From 73c741bbf9a80b1b78940eeb96a8dc7075230e5d Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Wed, 5 Feb 2025 20:16:00 +0000
Subject: [PATCH 0001/3886] mb/starlabs/starbook/adl: Disconnect the WLAN Sleep
 GPIO

The schematics show this pin isn't connected, so disconnect it.

Change-Id: Ib21048fa0972231410b7e8f7829a9eeac1d065c7
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86286
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
---
 src/mainboard/starlabs/starbook/variants/adl/gpio.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/mainboard/starlabs/starbook/variants/adl/gpio.c b/src/mainboard/starlabs/starbook/variants/adl/gpio.c
index 77be325ebf..e1ecddc7b4 100644
--- a/src/mainboard/starlabs/starbook/variants/adl/gpio.c
+++ b/src/mainboard/starlabs/starbook/variants/adl/gpio.c
@@ -37,7 +37,7 @@ const struct pad_config gpio_table[] = {
 	/* GPD8:	Suspend Clock					*/
 	PAD_CFG_NF(GPD8, NONE, DEEP, NF1),
 	/* GPD9:	Wireless LAN Sleep				*/
-	PAD_CFG_NF(GPD9, NONE, DEEP, NF1),
+	PAD_NC(GPD9, NONE),
 	/* GPD10:	Sleep S5					*/
 	PAD_NC(GPD10, NONE),
 	/* GPD11:	LAN PHY Enable					*/

From 66d7d922e1ee7bf7ac30079db4396c8a5e6d5f41 Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Wed, 5 Feb 2025 20:17:03 +0000
Subject: [PATCH 0002/3886] mb/starlabs/starbook/adl: Change the HPD to DEEP
 reset

DEEP proves more reliable on Linux with USB-C displays.

Change-Id: I04e243c6409af64fef0996b474aa448ce32b2da9
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86287
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/starlabs/starbook/variants/adl/gpio.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/mainboard/starlabs/starbook/variants/adl/gpio.c b/src/mainboard/starlabs/starbook/variants/adl/gpio.c
index e1ecddc7b4..0d15429184 100644
--- a/src/mainboard/starlabs/starbook/variants/adl/gpio.c
+++ b/src/mainboard/starlabs/starbook/variants/adl/gpio.c
@@ -75,7 +75,7 @@ const struct pad_config gpio_table[] = {
 	/* A18:		DDI B DP HPD					*/
 	PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1),
 	/* A19:		TCP0 HPD					*/
-	PAD_CFG_NF(GPP_A19, NONE, PLTRST, NF1),
+	PAD_CFG_NF(GPP_A19, NONE, DEEP, NF1),
 	/* A20:		Test Point 44					*/
 	PAD_NC(GPP_A20, NONE),
 	/* A21:		Fingerprint Reader Interrupt			*/

From 78c9f0e96d8173f691cbf2580afb0d8e85d223ba Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Wed, 5 Feb 2025 20:17:54 +0000
Subject: [PATCH 0003/3886] mb/starlabs/starbook/adl: Remove OverCurrent config

The schematics show that these are not connected, so disconnect
the GPIOs and set the ports to OC_SKIP.

Change-Id: I9e2b087b348fbae12edaf085fb61776277514c93
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86288
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
---
 src/mainboard/starlabs/starbook/variants/adl/devicetree.cb | 6 +++---
 src/mainboard/starlabs/starbook/variants/adl/gpio.c        | 4 ++--
 2 files changed, 5 insertions(+), 5 deletions(-)

diff --git a/src/mainboard/starlabs/starbook/variants/adl/devicetree.cb b/src/mainboard/starlabs/starbook/variants/adl/devicetree.cb
index 341ea4075b..217c375148 100644
--- a/src/mainboard/starlabs/starbook/variants/adl/devicetree.cb
+++ b/src/mainboard/starlabs/starbook/variants/adl/devicetree.cb
@@ -39,12 +39,12 @@ chip soc/intel/alderlake
 		device ref gna		on  end
 		device ref xhci		on
 			# Motherboard USB 3.0 Type-C
-			register "usb2_ports[0]"		= "USB2_PORT_MID(OC5)"
-			register "usb3_ports[2]"		= "USB3_PORT_DEFAULT(OC3)"
+			register "usb2_ports[0]"		= "USB2_PORT_MID(OC_SKIP)"
+			register "usb3_ports[2]"		= "USB3_PORT_DEFAULT(OC_SKIP)"
 
 			# Motherboard USB 3.0 Type-A
 			register "usb2_ports[2]"		= "USB2_PORT_MID(OC_SKIP)"
-			register "usb3_ports[0]"		= "USB3_PORT_DEFAULT(OC5)"
+			register "usb3_ports[0]"		= "USB3_PORT_DEFAULT(OC_SKIP)"
 
 			# Daughterboard USB 3.0 Type-A
 			register "usb2_ports[6]"		= "USB2_PORT_MID(OC0)"
diff --git a/src/mainboard/starlabs/starbook/variants/adl/gpio.c b/src/mainboard/starlabs/starbook/variants/adl/gpio.c
index 0d15429184..0e71085278 100644
--- a/src/mainboard/starlabs/starbook/variants/adl/gpio.c
+++ b/src/mainboard/starlabs/starbook/variants/adl/gpio.c
@@ -69,7 +69,7 @@ const struct pad_config gpio_table[] = {
 	/* A15:		Test Point 52					*/
 	PAD_NC(GPP_A15, NONE),
 	/* A16:		USB OverCurrent 3				*/
-	PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1),
+	PAD_NC(GPP_A16, NONE),
 	/* A17:		Not Connected					*/
 	PAD_NC(GPP_A17, NONE),
 	/* A18:		DDI B DP HPD					*/
@@ -257,7 +257,7 @@ const struct pad_config gpio_table[] = {
 	/* E8:		DRAM Sleep					*/
 	PAD_CFG_NF(GPP_E8, NONE, DEEP, NF1),
 	/* E9:		USB OverCurrent 0				*/
-	PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1),
+	PAD_NC(GPP_E9, NONE),
 	/* E10:		PWD Amplifier Input				*/
 	PAD_NC(GPP_E10, NONE),
 	/* E11:		TPM IRQ						*/

From fa3fd6871aeece48257eac3c085f0132fd49d720 Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Wed, 5 Feb 2025 20:19:21 +0000
Subject: [PATCH 0004/3886] mb/starlabs/starbook/adl: Change soft strap GPIO to
 DEEP reset

This has no noticable affect apart from being more consistant with
other boards.

Change-Id: Ia2d9284a7dfd29f47356860d6085c7aa5b94adb4
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86289
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/starlabs/starbook/variants/adl/gpio.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/mainboard/starlabs/starbook/variants/adl/gpio.c b/src/mainboard/starlabs/starbook/variants/adl/gpio.c
index 0e71085278..fb3d64d593 100644
--- a/src/mainboard/starlabs/starbook/variants/adl/gpio.c
+++ b/src/mainboard/starlabs/starbook/variants/adl/gpio.c
@@ -310,7 +310,7 @@ const struct pad_config gpio_table[] = {
 	/* F9:		EC Sleep S0					*/
 	PAD_NC(GPP_F9, NONE),
 	/* F10:		Weak Internal PD 20K				*/
-	PAD_CFG_GPO(GPP_F10, 0, PLTRST),
+	PAD_CFG_GPO(GPP_F10, 0, DEEP),
 	/* F11:		TPM ID						*/
 	PAD_NC(GPP_F11, NONE),
 	/* F12:		Not Connected					*/

From f56b8b49e80d8c2625eca27d0b3b146a28da7179 Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Fri, 31 Jan 2025 11:28:20 -0600
Subject: [PATCH 0005/3886] drivers/intel/gma: Fix alignment of extended VBT in
 opregion
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Intel's reference implementation in Slimbootloader pads the area
allocated for the extended VBT to the nearest 512-byte boundary, which
strongly suggests that the Windows driver expects the same.

TEST=build/boot Linux 6.9, Win11 on starlabs/starlite_adl, verify
VBT read properly by OS.

Change-Id: Ib3784eea6eb929ffec9672fc123b833c11c057e8
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86275
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/drivers/intel/gma/opregion.c | 11 +++++++----
 1 file changed, 7 insertions(+), 4 deletions(-)

diff --git a/src/drivers/intel/gma/opregion.c b/src/drivers/intel/gma/opregion.c
index f97d37350a..92665e0552 100644
--- a/src/drivers/intel/gma/opregion.c
+++ b/src/drivers/intel/gma/opregion.c
@@ -287,7 +287,7 @@ static inline bool uses_relative_vbt_addr(opregion_header_t *header)
  * values correctly for the opregion.
  */
 static void opregion_add_ext_vbt(igd_opregion_t *opregion, uint8_t *ext_vbt,
-				optionrom_vbt_t *vbt)
+				optionrom_vbt_t *vbt, size_t ext_vbt_size)
 {
 	opregion_header_t *header = &opregion->header;
 	/* Copy VBT into extended VBT region (at offset 8 KiB) */
@@ -301,7 +301,7 @@ static void opregion_add_ext_vbt(igd_opregion_t *opregion, uint8_t *ext_vbt,
 	else
 		opregion->mailbox3.rvda = (uintptr_t)ext_vbt;
 
-	opregion->mailbox3.rvds = vbt->hdr_vbt_size;
+	opregion->mailbox3.rvds = ext_vbt_size;
 }
 
 /* Initialize IGD OpRegion, called from ACPI code and OS drivers */
@@ -311,6 +311,7 @@ enum cb_err intel_gma_init_igd_opregion(void)
 	struct region_device rdev;
 	optionrom_vbt_t *vbt = NULL;
 	size_t opregion_size = sizeof(igd_opregion_t);
+	size_t ext_vbt_size;
 
 	if (acpi_is_wakeup_s3())
 		return intel_gma_restore_opregion();
@@ -331,7 +332,9 @@ enum cb_err intel_gma_init_igd_opregion(void)
 	}
 
 	/* Add the space for the extended VBT header even if it's not used */
-	opregion_size += vbt->hdr_vbt_size;
+	/* Align the VBT to nearest 512 byte boundary */
+	ext_vbt_size = ALIGN_UP(vbt->hdr_vbt_size, 512);
+	opregion_size += ext_vbt_size;
 
 	opregion = cbmem_add(CBMEM_ID_IGD_OPREGION, opregion_size);
 	if (!opregion) {
@@ -353,7 +356,7 @@ enum cb_err intel_gma_init_igd_opregion(void)
 	if (is_ext_vbt_required(opregion, vbt)) {
 		/* Place extended VBT just after opregion */
 		uint8_t *ext_vbt = (uint8_t *)opregion + sizeof(*opregion);
-		opregion_add_ext_vbt(opregion, ext_vbt, vbt);
+		opregion_add_ext_vbt(opregion, ext_vbt, vbt, ext_vbt_size);
 	} else {
 		/* Raw VBT size which can fit in gvd1 */
 		memcpy(opregion->vbt.gvd1, vbt, vbt->hdr_vbt_size);

From 857a92ef4b8655db23fdb3d8e728436eb2bc88c6 Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Tue, 4 Feb 2025 10:32:58 -0600
Subject: [PATCH 0006/3886] drivers/intel/gma: Don't advertise support for
 opregion mailbox #2
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

IGD mailbox #2, Software SCI Interface, is not supported by coreboot
currently, as it requires supporting the Get BIOS Data (GBDA) and
System BIOS Callbacks (SBCB) interfaces. Since coreboot doesn't
support these, don't advertise mailbox #2 support.

This eliminates an error with the Linux display drivers:
"SWSCI request timed out"

TEST=build/boot Linux 6.9, Win11 on starlabs/starlite_adl

Change-Id: I8efcf9c5d384b6e0ce159d65cb1497c2e2e47f42
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86276
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
---
 src/drivers/intel/gma/opregion.h | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/src/drivers/intel/gma/opregion.h b/src/drivers/intel/gma/opregion.h
index 7b6a85db52..2de9213743 100644
--- a/src/drivers/intel/gma/opregion.h
+++ b/src/drivers/intel/gma/opregion.h
@@ -41,8 +41,7 @@ typedef struct {
 #define IGD_MBOX4	(1 << 3)
 #define IGD_MBOX5	(1 << 4)
 
-#define MAILBOXES_MOBILE  (IGD_MBOX1 | IGD_MBOX2 | IGD_MBOX3 | \
-			   IGD_MBOX4 | IGD_MBOX5)
+#define MAILBOXES_MOBILE  (IGD_MBOX1 | IGD_MBOX3 | IGD_MBOX4 | IGD_MBOX5)
 #define MAILBOXES_DESKTOP (IGD_MBOX2 | IGD_MBOX4)
 
 #define SBIOS_VERSION_SIZE 32

From 4526bc68df27313697027f8f8a05421f2e475cff Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Tue, 4 Feb 2025 13:39:26 -0600
Subject: [PATCH 0007/3886] drivers/intel/gma: Drop unused MAILBOXES_DESKTOP
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

MAILBOXES_DESKTOP is unused, and the IGD opregion spec makes no
distinction in the mailboxes supported between desktop and mobile
platforms. Rename MAILBOXES_MOBILE to IGD_MAILBOXES for consistency
with other mailbox variables and clean up the comment.

Change-Id: Ia06fe75702887aa6953bf17bd4bc14af4038bec5
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86279
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/drivers/intel/gma/opregion.c | 4 ++--
 src/drivers/intel/gma/opregion.h | 3 +--
 2 files changed, 3 insertions(+), 4 deletions(-)

diff --git a/src/drivers/intel/gma/opregion.c b/src/drivers/intel/gma/opregion.c
index 92665e0552..4f5f802a4e 100644
--- a/src/drivers/intel/gma/opregion.c
+++ b/src/drivers/intel/gma/opregion.c
@@ -367,8 +367,8 @@ enum cb_err intel_gma_init_igd_opregion(void)
 	/* 8kb */
 	opregion->header.size = sizeof(igd_opregion_t) / 1024;
 
-	// FIXME We just assume we're mobile for now
-	opregion->header.mailboxes = MAILBOXES_MOBILE;
+	// Supported mailboxes
+	opregion->header.mailboxes = IGD_MAILBOXES;
 
 	// TODO Initialize Mailbox 1
 	opregion->mailbox1.clid = 1;
diff --git a/src/drivers/intel/gma/opregion.h b/src/drivers/intel/gma/opregion.h
index 2de9213743..77fccf8e54 100644
--- a/src/drivers/intel/gma/opregion.h
+++ b/src/drivers/intel/gma/opregion.h
@@ -41,8 +41,7 @@ typedef struct {
 #define IGD_MBOX4	(1 << 3)
 #define IGD_MBOX5	(1 << 4)
 
-#define MAILBOXES_MOBILE  (IGD_MBOX1 | IGD_MBOX3 | IGD_MBOX4 | IGD_MBOX5)
-#define MAILBOXES_DESKTOP (IGD_MBOX2 | IGD_MBOX4)
+#define IGD_MAILBOXES	(IGD_MBOX1 | IGD_MBOX3 | IGD_MBOX4 | IGD_MBOX5)
 
 #define SBIOS_VERSION_SIZE 32
 

From d5ad4ce36c2a247e31f48a046ae976276e9bab07 Mon Sep 17 00:00:00 2001
From: Bora Guvendik <bora.guvendik@intel.com>
Date: Tue, 4 Feb 2025 09:50:44 -0800
Subject: [PATCH 0008/3886] soc/intel/pantherlake: Add ability to set SaGv work
 points
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Hook up SaGv work point UPDs.

BUG=none
TEST=Boot to OS.

Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Change-Id: Ie38d007edc293727066f2bc9f67037e6fbe77aa5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86277
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
---
 src/soc/intel/pantherlake/chip.h                | 8 ++++++++
 src/soc/intel/pantherlake/romstage/fsp_params.c | 5 +++++
 2 files changed, 13 insertions(+)

diff --git a/src/soc/intel/pantherlake/chip.h b/src/soc/intel/pantherlake/chip.h
index e879fadb60..cd91e31dd0 100644
--- a/src/soc/intel/pantherlake/chip.h
+++ b/src/soc/intel/pantherlake/chip.h
@@ -42,6 +42,14 @@ struct ibecc_config {
 	uint16_t region_mask[MAX_IBECC_REGIONS];
 };
 
+/* SaGv gears */
+enum soc_intel_pantherlake_sagv_gears {
+	GEAR_AUTO = 0,
+	GEAR_1 = 1,
+	GEAR_2 = 2,
+	GEAR_4 = 4,
+};
+
 enum soc_intel_pantherlake_power_limits {
 	PTL_U_1_CORE,
 	PTL_H_1_CORE,
diff --git a/src/soc/intel/pantherlake/romstage/fsp_params.c b/src/soc/intel/pantherlake/romstage/fsp_params.c
index 5b968918b2..0c17d020c3 100644
--- a/src/soc/intel/pantherlake/romstage/fsp_params.c
+++ b/src/soc/intel/pantherlake/romstage/fsp_params.c
@@ -73,6 +73,11 @@ static void fill_fspm_mrc_params(FSP_M_CONFIG *m_cfg,
 			m_cfg->SaGvWpMask = config->sagv_wp_bitmap;
 		else
 			m_cfg->SaGvWpMask = SAGV_POINTS_0_1_2_3;
+
+		for (size_t i = 0; i < HOB_MAX_SAGV_POINTS; i++) {
+			m_cfg->SaGvFreq[i] = config->sagv_freq_mhz[i];
+			m_cfg->SaGvGear[i] = config->sagv_gear[i];
+		}
 	}
 
 	if (config->max_dram_speed_mts)

From d0f895a5484f06f6e27716022eb03a0ef54471e9 Mon Sep 17 00:00:00 2001
From: Bora Guvendik <bora.guvendik@intel.com>
Date: Tue, 4 Feb 2025 08:05:07 -0800
Subject: [PATCH 0009/3886] mb/google/fatcat: Set frequency and gears for SaGv
 work points

Update sagv gears and frequency values as per recommendation
from power and performance team.

BUG=none
TEST=Boot to OS.

Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Change-Id: I315fcac387680df9312880120b7e6d33bded38e0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86274
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
---
 .../fatcat/variants/baseboard/fatcat/devicetree.cb   | 12 ++++++++++++
 1 file changed, 12 insertions(+)

diff --git a/src/mainboard/google/fatcat/variants/baseboard/fatcat/devicetree.cb b/src/mainboard/google/fatcat/variants/baseboard/fatcat/devicetree.cb
index 342c534b7b..c217a159e1 100644
--- a/src/mainboard/google/fatcat/variants/baseboard/fatcat/devicetree.cb
+++ b/src/mainboard/google/fatcat/variants/baseboard/fatcat/devicetree.cb
@@ -33,6 +33,18 @@ chip soc/intel/pantherlake
 	# Enable SAGv
 	register "sagv" = "SAGV_ENABLED"
 
+	register "sagv_freq_mhz[0]" = "2400"
+	register "sagv_gear[0]" = "GEAR_4"
+
+	register "sagv_freq_mhz[1]" = "3200"
+	register "sagv_gear[1]" = "GEAR_4"
+
+	register "sagv_freq_mhz[2]" = "6000"
+	register "sagv_gear[2]" = "GEAR_4"
+
+	register "sagv_freq_mhz[3]" = "6400"
+	register "sagv_gear[3]" = "GEAR_4"
+
 	# Enable s0ix
 	register "s0ix_enable" = "true"
 

From e75cc637cee589e3da2c78f67d133cffe1175d26 Mon Sep 17 00:00:00 2001
From: Amanda Huang <amanda_hwang@compal.corp-partner.google.com>
Date: Thu, 6 Feb 2025 02:44:03 +0800
Subject: [PATCH 0010/3886] mb/google/fatcat/var/francka: Decrease trace length
 of USB-A phy to short

To resolve the issue of not being able to boot from USB on Francka, the USB PHY settings need to be modified.

BUG=b:394206896
TEST=Build and test Type-A port function works fine

Change-Id: I140b8a2047768d3aeb0d5919aad998bd9dcd099f
Signed-off-by: Amanda Huang <amanda_hwang@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86285
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
---
 src/mainboard/google/fatcat/variants/francka/overridetree.cb | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/mainboard/google/fatcat/variants/francka/overridetree.cb b/src/mainboard/google/fatcat/variants/francka/overridetree.cb
index 9d2dd2f0bf..dc76b85639 100644
--- a/src/mainboard/google/fatcat/variants/francka/overridetree.cb
+++ b/src/mainboard/google/fatcat/variants/francka/overridetree.cb
@@ -28,9 +28,9 @@ chip soc/intel/pantherlake
 
 	register "max_dram_speed_mts" = "7467"
 
-	register "usb2_ports[1]" = "USB2_PORT_MID(OC0)" # Type-A Port A0
+	register "usb2_ports[1]" = "USB2_PORT_SHORT(OC0)" # Type-A Port A0
 	register "usb2_ports[3]" = "USB2_PORT_TYPE_C(OC_SKIP)" # USB2_C0
-	register "usb2_ports[4]" = "USB2_PORT_MID(OC0)" # Type-A Port A1
+	register "usb2_ports[4]" = "USB2_PORT_SHORT(OC0)" # Type-A Port A1
 	register "usb2_ports[5]" = "USB2_PORT_TYPE_C(OC_SKIP)" # USB2_C1
 	register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" # USB HUB (USB2 Camera)
 	register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # CNVi BT or discrete BT

From 21f0df3c1ab1fa174dcd3d6c66f00047ba9e7e66 Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Thu, 6 Feb 2025 20:37:49 +0000
Subject: [PATCH 0011/3886] mb/starlabs/starbook/mtl: Correct DIMM Speed Size

The DDR5 modules have a speed size of 1024 bytes, not 512. Update
Kconfig to reflect this.

Change-Id: Ic7b691104ff8b0061a485f01709a2f53046cc94a
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86306
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
---
 src/mainboard/starlabs/starbook/Kconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/src/mainboard/starlabs/starbook/Kconfig b/src/mainboard/starlabs/starbook/Kconfig
index b7e1c63b46..1565f88290 100644
--- a/src/mainboard/starlabs/starbook/Kconfig
+++ b/src/mainboard/starlabs/starbook/Kconfig
@@ -139,6 +139,7 @@ config DEVICETREE
 	default "variants/\$(CONFIG_VARIANT_DIR)/devicetree.cb"
 
 config DIMM_SPD_SIZE
+	default 1024 if BOARD_STARLABS_STARBOOK_MTL
 	default 512
 
 config DRIVER_TPM_SPI_CHIP

From 4ef7804bc4ec957dff23390e85ae931b66ee4c30 Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Thu, 6 Feb 2025 20:39:03 +0000
Subject: [PATCH 0012/3886] mb/starlabs/starbook/mtl: Add rcomp configuration

Add rcomp configuration values taken from the AMI CRB. This fixes
failed memory training for certain memory modules.

Change-Id: If7a29bbd015d45eac178480ba6cae42912e25195
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86307
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
---
 src/mainboard/starlabs/starbook/variants/mtl/romstage.c | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/src/mainboard/starlabs/starbook/variants/mtl/romstage.c b/src/mainboard/starlabs/starbook/variants/mtl/romstage.c
index 14b2664cbd..26a4e5eb3c 100644
--- a/src/mainboard/starlabs/starbook/variants/mtl/romstage.c
+++ b/src/mainboard/starlabs/starbook/variants/mtl/romstage.c
@@ -13,6 +13,10 @@ void mainboard_memory_init_params(FSPM_UPD *mupd)
 		.UserBd = BOARD_TYPE_MOBILE,
 		.ddr_config = {
 			.dq_pins_interleaved = false,
+		},
+		.rcomp = {
+			.resistor = 100,
+			.targets = {70, 30, 25, 25, 25},
 		}
 	};
 

From 6e7b44f4f3ada7f365c34edf522eb5f2346fc25d Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Thu, 6 Feb 2025 19:52:53 +0000
Subject: [PATCH 0013/3886] ec/starlabs/merlin: Add an option to disable the
 fan

Add an option alongside the three existing curves to just turn
off the fan.

Change-Id: I39f6599056fe0116abbd7e2eb4084f77a7c395d3
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86304
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
---
 src/ec/starlabs/merlin/ec.h              | 1 +
 src/ec/starlabs/merlin/ite.c             | 5 +++--
 src/mainboard/starlabs/starbook/cfr.c    | 1 +
 src/mainboard/starlabs/starfighter/cfr.c | 1 +
 4 files changed, 6 insertions(+), 2 deletions(-)

diff --git a/src/ec/starlabs/merlin/ec.h b/src/ec/starlabs/merlin/ec.h
index d5e1788e79..82572bde73 100644
--- a/src/ec/starlabs/merlin/ec.h
+++ b/src/ec/starlabs/merlin/ec.h
@@ -79,6 +79,7 @@
 #define FAN_NORMAL		0x00
 #define FAN_AGGRESSIVE		0xbb
 #define FAN_QUIET		0xaa
+#define FAN_DISABLED		0xcc
 
 /* Fn Lock State */
 #define UNLOCKED		0x00
diff --git a/src/ec/starlabs/merlin/ite.c b/src/ec/starlabs/merlin/ite.c
index 1dd83a8c83..6eaa3e9915 100644
--- a/src/ec/starlabs/merlin/ite.c
+++ b/src/ec/starlabs/merlin/ite.c
@@ -175,14 +175,15 @@ static void merlin_init(struct device *dev)
 	 *
 	 * Setting:	fan_mode
 	 *
-	 * Values:	Quiet, Normal, Aggressive
+	 * Values:	Disabled, Quiet, Normal, Aggressive
 	 * Default:	Normal
 	 *
 	 */
 	const uint8_t fan_mode[] = {
 		FAN_NORMAL,
 		FAN_AGGRESSIVE,
-		FAN_QUIET
+		FAN_QUIET,
+		FAN_DISABLED
 	};
 
 	if (CONFIG(EC_STARLABS_FAN))
diff --git a/src/mainboard/starlabs/starbook/cfr.c b/src/mainboard/starlabs/starbook/cfr.c
index 82488fe660..9b47f48345 100644
--- a/src/mainboard/starlabs/starbook/cfr.c
+++ b/src/mainboard/starlabs/starbook/cfr.c
@@ -69,6 +69,7 @@ static const struct sm_object fan_mode = SM_DECLARE_ENUM({
 				{ "Normal",		0		},
 				{ "Aggressive",		1		},
 				{ "Quiet",		2		},
+				{ "Disabled",		3		},
 				SM_ENUM_VALUE_END			},
 });
 
diff --git a/src/mainboard/starlabs/starfighter/cfr.c b/src/mainboard/starlabs/starfighter/cfr.c
index 6802b751a3..7c8a123062 100644
--- a/src/mainboard/starlabs/starfighter/cfr.c
+++ b/src/mainboard/starlabs/starfighter/cfr.c
@@ -62,6 +62,7 @@ static const struct sm_object fan_mode = SM_DECLARE_ENUM({
 				{ "Normal",		0		},
 				{ "Aggressive",		1		},
 				{ "Quiet",		2		},
+				{ "Disabled",		3		},
 				SM_ENUM_VALUE_END			},
 });
 

From 0f3589b3d7f166060f2d87b21f5d748abed741cd Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Thu, 6 Feb 2025 20:16:58 +0000
Subject: [PATCH 0014/3886] ec/starlabs/merlin: Add an option to disabled the
 lid switch

Previously, the lid switch could be set to not wake the system.

Add another option to ignore the switch entirely.

Change-Id: I1dd666a44b332ffbbef4420799eeffd746fd1664
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86305
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/starlabs/starbook/cfr.c     | 7 ++++---
 src/mainboard/starlabs/starfighter/cfr.c  | 7 ++++---
 src/mainboard/starlabs/starlite_adl/cfr.c | 7 ++++---
 3 files changed, 12 insertions(+), 9 deletions(-)

diff --git a/src/mainboard/starlabs/starbook/cfr.c b/src/mainboard/starlabs/starbook/cfr.c
index 9b47f48345..bf0e4b0bcf 100644
--- a/src/mainboard/starlabs/starbook/cfr.c
+++ b/src/mainboard/starlabs/starbook/cfr.c
@@ -126,11 +126,12 @@ static const struct sm_object kbl_timeout = SM_DECLARE_ENUM({
 static const struct sm_object lid_switch = SM_DECLARE_ENUM({
 	.opt_name	= "lid_switch",
 	.ui_name	= "Lid Switch",
-	.ui_helptext	= "Enable or disable the lid switch.",
+	.ui_helptext	= "Configure what opening or closing the lid will do.",
 	.default_value	= 0,
 	.values		= (const struct sm_enum_value[]) {
-				{ "Enabled",		0	},
-				{ "Disabled",		1	},
+				{ "Normal",		0	},
+				{ "Sleep Only",		1	},
+				{ "Disabled",		2	},
 				SM_ENUM_VALUE_END		},
 });
 #endif
diff --git a/src/mainboard/starlabs/starfighter/cfr.c b/src/mainboard/starlabs/starfighter/cfr.c
index 7c8a123062..f310f86a64 100644
--- a/src/mainboard/starlabs/starfighter/cfr.c
+++ b/src/mainboard/starlabs/starfighter/cfr.c
@@ -108,11 +108,12 @@ static const struct sm_object kbl_timeout = SM_DECLARE_ENUM({
 static const struct sm_object lid_switch = SM_DECLARE_ENUM({
 	.opt_name	= "lid_switch",
 	.ui_name	= "Lid Switch",
-	.ui_helptext	= "Enable or disable the lid switch.",
+	.ui_helptext	= "Configure what opening or closing the lid will do.",
 	.default_value	= 0,
 	.values		= (const struct sm_enum_value[]) {
-				{ "Enabled",		0	},
-				{ "Disabled",		1	},
+				{ "Normal",		0	},
+				{ "Sleep Only",		1	},
+				{ "Disabled",		2	},
 				SM_ENUM_VALUE_END		},
 });
 #endif
diff --git a/src/mainboard/starlabs/starlite_adl/cfr.c b/src/mainboard/starlabs/starlite_adl/cfr.c
index 58a09a3d7c..a8e44fa11c 100644
--- a/src/mainboard/starlabs/starlite_adl/cfr.c
+++ b/src/mainboard/starlabs/starlite_adl/cfr.c
@@ -73,11 +73,12 @@ static const struct sm_object gna = SM_DECLARE_BOOL({
 static const struct sm_object lid_switch = SM_DECLARE_ENUM({
 	.opt_name	= "lid_switch",
 	.ui_name	= "Lid Switch",
-	.ui_helptext	= "Enable or disable the lid switch.",
+	.ui_helptext	= "Configure what opening or closing the lid will do.",
 	.default_value	= 0,
 	.values		= (const struct sm_enum_value[]) {
-				{ "Enabled",		0	},
-				{ "Disabled",		1	},
+				{ "Normal",		0	},
+				{ "Sleep Only",		1	},
+				{ "Disabled",		2	},
 				SM_ENUM_VALUE_END		},
 });
 #endif

From 9f6a871414d2e8e6b9444a6707c8de67c3396142 Mon Sep 17 00:00:00 2001
From: Yidi Lin <yidilin@chromium.org>
Date: Wed, 5 Feb 2025 16:12:30 +0800
Subject: [PATCH 0015/3886] mb/google/rauru: Support the panel with a load
 switch control

The Rauru follower device goes `load switch` path to ensure the
discharge timing meets the panel power-off sequence. Refactor panel.c to
support this hardware change.

Remove PANEL from fw_config since this is a board-specific change.

BRANCH=rauru
BUG=b:339580836
TEST=verify firmware screen on Navi

Change-Id: I57dcaa2a0b5af94fe3fa3eaf04e9f3159c51d144
Signed-off-by: Yidi Lin <yidilin@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86282
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
---
 src/mainboard/google/rauru/devicetree.cb |  7 -------
 src/mainboard/google/rauru/panel.c       | 14 +++++++-------
 2 files changed, 7 insertions(+), 14 deletions(-)

diff --git a/src/mainboard/google/rauru/devicetree.cb b/src/mainboard/google/rauru/devicetree.cb
index 55cc91c307..1705dbeb9b 100644
--- a/src/mainboard/google/rauru/devicetree.cb
+++ b/src/mainboard/google/rauru/devicetree.cb
@@ -8,13 +8,6 @@ fw_config
 	end
 end
 
-fw_config
-	field PANEL 18 21
-		option DEFAULT 0
-		option OLED 1
-	end
-end
-
 chip soc/mediatek/mt8196
 	device cpu_cluster 0 on end
 
diff --git a/src/mainboard/google/rauru/panel.c b/src/mainboard/google/rauru/panel.c
index 8564f4ca04..37e4001159 100644
--- a/src/mainboard/google/rauru/panel.c
+++ b/src/mainboard/google/rauru/panel.c
@@ -27,23 +27,23 @@ static struct panel_description panel = {
 	.orientation = LB_FB_ORIENTATION_NORMAL,
 };
 
-static void power_on_oled_panel(void)
+static void power_on_load_switch(void)
 {
 	gpio_output(GPIO_EN_PP3300_EDP_X, 1);
 	gpio_set_mode(GPIO_EDP_HPD_1V8, GPIO_FUNC(EINT13, EDP_TX_HPD));
 }
 
-static struct panel_description oled_panel = {
+static struct panel_description edp_panel = {
 	.configure_backlight = configure_backlight,
-	.power_on = power_on_oled_panel,
+	.power_on = power_on_load_switch,
 	.disp_path = DISP_PATH_EDP,
 	.orientation = LB_FB_ORIENTATION_NORMAL,
 };
 
 struct panel_description *get_active_panel(void)
 {
-	if (fw_config_probe(FW_CONFIG(PANEL, OLED))) {
-		return &oled_panel;
-	}
-	return &panel;
+	if (CONFIG(BOARD_GOOGLE_RAURU))
+		return &panel;
+
+	return &edp_panel;
 }

From 57fbd9c92c0f39039d86806189bddde873eaed1f Mon Sep 17 00:00:00 2001
From: Yidi Lin <yidilin@chromium.org>
Date: Thu, 6 Feb 2025 16:21:26 +0800
Subject: [PATCH 0016/3886] mb/google/rauru: Pull HPD pin up

Pull HPD (Hot Plug Detect) pin up in order to detect the panel.

BRANCH=rauru
BUG=b:376357839
TEST=Verify FW screen on Navi and Hylia

Change-Id: Ie11ceabad0b9872729125936d90b93b5d6d7cea6
Signed-off-by: Yidi Lin <yidilin@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86294
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/google/rauru/panel.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/src/mainboard/google/rauru/panel.c b/src/mainboard/google/rauru/panel.c
index 37e4001159..92d2f30cf1 100644
--- a/src/mainboard/google/rauru/panel.c
+++ b/src/mainboard/google/rauru/panel.c
@@ -31,6 +31,7 @@ static void power_on_load_switch(void)
 {
 	gpio_output(GPIO_EN_PP3300_EDP_X, 1);
 	gpio_set_mode(GPIO_EDP_HPD_1V8, GPIO_FUNC(EINT13, EDP_TX_HPD));
+	gpio_set_pull(GPIO_EDP_HPD_1V8, GPIO_PULL_ENABLE, GPIO_PULL_UP);
 }
 
 static struct panel_description edp_panel = {

From 8deb8e94ad7d5ebcc0631c5b39d4941d41ea9715 Mon Sep 17 00:00:00 2001
From: Yidi Lin <yidilin@chromium.org>
Date: Thu, 6 Feb 2025 18:12:34 +0800
Subject: [PATCH 0017/3886] soc/mediatek/mt8196: Correct assert conditions

Correct the assert conditions in dptx_hal_setswing_preemphasis() and
dptx_hal_phy_set_swing_preemphasis().

BRANCH=rauru
BUG=b:376357839
TEST=Verify FW screen with a 4 lanes panel on Hylia

Change-Id: I8830b05c976ea2ba987de6333b93e2394d3403ba
Signed-off-by: Yidi Lin <yidilin@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86302
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/soc/mediatek/mt8196/dptx_hal.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/soc/mediatek/mt8196/dptx_hal.c b/src/soc/mediatek/mt8196/dptx_hal.c
index 168d62bc32..e6078aea88 100644
--- a/src/soc/mediatek/mt8196/dptx_hal.c
+++ b/src/soc/mediatek/mt8196/dptx_hal.c
@@ -87,7 +87,7 @@ bool dptx_hal_hpd_high(struct mtk_dp *mtk_dp)
 bool dptx_hal_setswing_preemphasis(struct mtk_dp *mtk_dp, int lane_num, u8 swing_value,
 				   u8 preemphasis)
 {
-	assert(lane_num < DPTX_LANE_MAX);
+	assert(lane_num <= DPTX_LANE_MAX);
 
 	for (int i = 0; i < lane_num; ++i) {
 		mtk_dp_phy_mask(mtk_dp, driving_offset[i],
@@ -348,7 +348,7 @@ void dptx_hal_set_txlane(struct mtk_dp *mtk_dp, u8 value)
 void dptx_hal_phy_set_swing_preemphasis(struct mtk_dp *mtk_dp, u8 lane_count, u8 *swing_val,
 					 u8 *preemphasis)
 {
-	assert(lane_count < DPTX_LANE_MAX);
+	assert(lane_count <= DPTX_LANE_MAX);
 
 	for (int i = 0; i < lane_count; ++i) {
 		mtk_dp_phy_mask(mtk_dp, driving_offset[i],

From fa703f7b94723ea75a0632ade9c3083620d31544 Mon Sep 17 00:00:00 2001
From: Vladimir Serbinenko <phcoder@gmail.com>
Date: Mon, 3 Feb 2025 03:17:22 +0100
Subject: [PATCH 0018/3886] intel/acpi: Put BSP as the first entry
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Linux complains in dmesg as a firmware bug that BSP is not the first
entry.
NetBSD hangs and OpenBSD panics early on boot.
With this patch I was able to boot NetBSD and OpenBSD on darp10-b when
loaded in GRUB.
Note: vanilla bootloaders for NetBSD and OpenBSD still result in an
apparent hang for an unknown reason.

Change-Id: I520a2e080c9f07a5866729ae2283990d20c0d691
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86247
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
---
 src/soc/intel/common/block/acpi/cpu_hybrid.c | 41 ++++++++++++++------
 1 file changed, 29 insertions(+), 12 deletions(-)

diff --git a/src/soc/intel/common/block/acpi/cpu_hybrid.c b/src/soc/intel/common/block/acpi/cpu_hybrid.c
index ee4777ae69..0e7ec53ea6 100644
--- a/src/soc/intel/common/block/acpi/cpu_hybrid.c
+++ b/src/soc/intel/common/block/acpi/cpu_hybrid.c
@@ -18,8 +18,8 @@
 struct cpu_apic_info_type {
 	/*
 	 * Ordered APIC IDs based on core type.
-	 * Array begins with Performance Cores' APIC IDs,
-	 * then followed by Efficeint Cores's APIC IDs.
+	 * Array begins with BSP, then come all Performance Cores' APIC IDs,
+	 * then followed by Efficient Cores's APIC IDs.
 	 */
 	int32_t apic_ids[CONFIG_MAX_CPUS];
 
@@ -27,11 +27,15 @@ struct cpu_apic_info_type {
 	uint16_t total_cpu_cnt;
 
 	/*
-	 * Total Performance core count. This will be used
-	 * to identify the start of Efficient Cores's
+	 * This will be used to identify the start of Efficient Cores's
 	 * APIC ID list
 	 */
-	uint16_t perf_cpu_cnt;
+	uint16_t eff_cores_start;
+
+	/*
+	 * Set to true if bsp is a performance core
+	 */
+	bool is_bsp_perf;
 };
 
 static struct cpu_apic_info_type cpu_apic_info;
@@ -48,12 +52,25 @@ static void acpi_set_hybrid_cpu_apicid_order(void *unused)
 	int32_t eff_apic_ids[CONFIG_MAX_CPUS] = {0};
 	extern struct cpu_info cpu_infos[];
 	uint32_t i, j = 0;
+	u32 bsp_lapicid = lapicid();
+
+	/* As per spec first comes BSP.
+	   See 5.2.12.1 MADT Processor Local APIC / SAPIC Structure Entry Order
+	   " platform firmware should list the boot processor as the first
+	     processor entry in the MADT. "
+	 */
+	cpu_apic_info.apic_ids[0] = bsp_lapicid;
 
 	for (i = 0; i < ARRAY_SIZE(cpu_apic_info.apic_ids); i++) {
 		if (!cpu_infos[i].cpu)
 			continue;
+		if (cpu_infos[i].cpu->path.apic.apic_id == bsp_lapicid) {
+			cpu_apic_info.is_bsp_perf =
+				cpu_infos[i].cpu->path.apic.core_type == CPU_TYPE_PERF;
+			continue;
+		}
 		if (cpu_infos[i].cpu->path.apic.core_type == CPU_TYPE_PERF)
-			cpu_apic_info.apic_ids[perf_core_cnt++] =
+			cpu_apic_info.apic_ids[1 + perf_core_cnt++] =
 				cpu_infos[i].cpu->path.apic.apic_id;
 		else
 			eff_apic_ids[eff_core_cnt++] =
@@ -61,18 +78,18 @@ static void acpi_set_hybrid_cpu_apicid_order(void *unused)
 	}
 
 	if (perf_core_cnt > 1)
-		bubblesort(cpu_apic_info.apic_ids, perf_core_cnt, NUM_ASCENDING);
+		bubblesort(cpu_apic_info.apic_ids + 1, perf_core_cnt, NUM_ASCENDING);
 
-	for (i = perf_core_cnt; j < eff_core_cnt; i++, j++)
+	for (i = perf_core_cnt + 1; j < eff_core_cnt; i++, j++)
 		cpu_apic_info.apic_ids[i] = eff_apic_ids[j];
 
 	if (eff_core_cnt > 1)
-		bubblesort(&cpu_apic_info.apic_ids[perf_core_cnt], eff_core_cnt, NUM_ASCENDING);
+		bubblesort(&cpu_apic_info.apic_ids[perf_core_cnt + 1], eff_core_cnt, NUM_ASCENDING);
 
 	/* Populate total core count */
-	cpu_apic_info.total_cpu_cnt = perf_core_cnt + eff_core_cnt;
+	cpu_apic_info.total_cpu_cnt = perf_core_cnt + eff_core_cnt + 1;
 
-	cpu_apic_info.perf_cpu_cnt = perf_core_cnt;
+	cpu_apic_info.eff_cores_start = perf_core_cnt + 1;
 }
 
 static unsigned long acpi_create_madt_lapics_hybrid(unsigned long current)
@@ -132,7 +149,7 @@ static void acpigen_cppc_update_nominal_freq_perf(const char *pkg_path, s32 core
 
 	acpi_get_cpu_nomi_perf(&eff_core_nom_perf, &perf_core_nom_perf);
 
-	if (core_id < cpu_apic_info.perf_cpu_cnt)
+	if (core_id == 0 ? cpu_apic_info.is_bsp_perf : (core_id < cpu_apic_info.eff_cores_start))
 		acpigen_set_package_element_int(pkg_path, CPPC_NOM_PERF_IDX, perf_core_nom_perf);
 	else
 		acpigen_set_package_element_int(pkg_path, CPPC_NOM_PERF_IDX,

From 4a2135d21eda950fd072e218cc071eba580d5b8a Mon Sep 17 00:00:00 2001
From: John Su <john_su@compal.corp-partner.google.com>
Date: Mon, 3 Feb 2025 23:25:25 +0800
Subject: [PATCH 0019/3886] mb/google/trulo/var/uldrenite: Add fw_config probe
 for Cellular

Use fw_config to probe Cellular.

BUG=b:392040004
BRANCH=firmware-trulo-15217.771.B
TEST=emerge-nissa coreboot chromeos-bootimage

Change-Id: Ib664f543c6012b44a0a604d0943416519d92a057
Signed-off-by: John Su <john_su@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86255
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
---
 .../brya/variants/uldrenite/overridetree.cb    | 17 ++++++++++++++---
 .../google/brya/variants/uldrenite/variant.c   | 18 ++++++++++++++++++
 2 files changed, 32 insertions(+), 3 deletions(-)

diff --git a/src/mainboard/google/brya/variants/uldrenite/overridetree.cb b/src/mainboard/google/brya/variants/uldrenite/overridetree.cb
index 3c067505fe..862968efd4 100644
--- a/src/mainboard/google/brya/variants/uldrenite/overridetree.cb
+++ b/src/mainboard/google/brya/variants/uldrenite/overridetree.cb
@@ -1,4 +1,8 @@
 fw_config
+	field DB_CELLULAR 1 2
+		option CELLULAR_ABSENT		0
+		option CELLULAR_RW350R		1
+	end
 	field TOUCHSCREEN 4 4
 		option TOUCHSCREEN_UNKNOWN	0
 		option TOUCHSCREEN_NONE		1
@@ -278,7 +282,9 @@ chip soc/intel/alderlake
 					chip drivers/usb/acpi
 						register "desc" = ""USB2 WWAN""
 						register "type" = "UPC_TYPE_INTERNAL"
-						device ref usb2_port5 on end
+						device ref usb2_port5 on
+							probe DB_CELLULAR CELLULAR_RW350R
+						end
 					end
 					chip drivers/usb/acpi
 						register "desc" = ""USB2 User Facing Camera""
@@ -459,7 +465,9 @@ chip soc/intel/alderlake
 				register "srcclk_pin" = "2"
 				register "ext_pm_support" = "ACPI_PCIE_RP_EMIT_ALL"
 				register "skip_on_off_support" = "true"
-				device generic 0 alias rp2_rtd3 on end
+				device generic 0 alias rp2_rtd3 on
+					probe DB_CELLULAR CELLULAR_RW350R
+				end
 			end
 			chip drivers/wwan/fm
 				register "fcpo_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_H23)"
@@ -468,8 +476,11 @@ chip soc/intel/alderlake
 				register "wake_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_E16)"
 				register "add_acpi_dma_property" = "true"
 				use rp2_rtd3 as rtd3dev
-				device generic 0 alias rp2_wwan on end
+				device generic 0 alias rp2_wwan on
+					probe DB_CELLULAR CELLULAR_RW350R
+				end
 			end
+			probe DB_CELLULAR CELLULAR_RW350R
 		end # PCIE2 WWAN card
 		device ref shared_sram on end
 		device ref heci1 on end
diff --git a/src/mainboard/google/brya/variants/uldrenite/variant.c b/src/mainboard/google/brya/variants/uldrenite/variant.c
index 96b22918f6..f5bbaf6924 100644
--- a/src/mainboard/google/brya/variants/uldrenite/variant.c
+++ b/src/mainboard/google/brya/variants/uldrenite/variant.c
@@ -37,6 +37,17 @@ static const struct pad_config touchscreen_disable_pads[] = {
 	PAD_NC(GPP_E17, NONE),
 };
 
+static const struct pad_config lte_disable_pads[] = {
+	/* A8  : WWAN_RF_DISABLE_ODL */
+	PAD_NC(GPP_A8, NONE),
+	/* F12 : WWAN_RST_L */
+	PAD_NC_LOCK(GPP_F12, NONE, LOCK_CONFIG),
+	/* F13 : PLTRST_WWAN# */
+	PAD_NC(GPP_F13, NONE),
+	/* H23  : WWAN_EN */
+	PAD_NC(GPP_H23, NONE),
+};
+
 void fw_config_gpio_padbased_override(struct pad_config *padbased_table)
 {
 	if (fw_config_probe(FW_CONFIG(TOUCHSCREEN, TOUCHSCREEN_NONE))) {
@@ -44,10 +55,17 @@ void fw_config_gpio_padbased_override(struct pad_config *padbased_table)
 		gpio_padbased_override(padbased_table, touchscreen_disable_pads,
 				ARRAY_SIZE(touchscreen_disable_pads));
 	}
+	if (fw_config_probe(FW_CONFIG(DB_CELLULAR, CELLULAR_ABSENT))) {
+		printk(BIOS_INFO, "Disable Cellular GPIO pins.\n");
+		gpio_padbased_override(padbased_table, lte_disable_pads,
+				ARRAY_SIZE(lte_disable_pads));
+	}
 }
 
 void variant_init(void)
 {
+	if (fw_config_probe(FW_CONFIG(DB_CELLULAR, CELLULAR_ABSENT)))
+		return;
 	/*
 	 * RW350R power on seuqence:
 	 * De-assert WWAN_EN -> 20ms -> de-assert WWAN_RST -> 30ms ->

From 99cfad508a49993beb4826097cce9d772c778c92 Mon Sep 17 00:00:00 2001
From: Filip Brozovic <fbrozovic@gmail.com>
Date: Tue, 21 Jan 2025 11:59:11 +0100
Subject: [PATCH 0020/3886] CFR: Add version field to root struct

Add a version field to the CFR root struct so parsers can check
compatibility when parsing structs.

Change-Id: Ifcb950f1bdedc0ab925f3841befb7e7001c0f7f4
Signed-off-by: Filip Brozovic <fbrozovic@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86080
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
---
 src/commonlib/include/commonlib/cfr.h             | 2 ++
 src/commonlib/include/commonlib/coreboot_tables.h | 1 +
 src/drivers/option/cfr.c                          | 1 +
 3 files changed, 4 insertions(+)

diff --git a/src/commonlib/include/commonlib/cfr.h b/src/commonlib/include/commonlib/cfr.h
index cc8431a2db..5d8b37bf56 100644
--- a/src/commonlib/include/commonlib/cfr.h
+++ b/src/commonlib/include/commonlib/cfr.h
@@ -49,6 +49,8 @@
  *
  */
 
+#define CFR_VERSION 0x00000000
+
 enum cfr_tags {
 	CFR_TAG_OPTION_FORM		= 1,
 	CFR_TAG_ENUM_VALUE		= 2,
diff --git a/src/commonlib/include/commonlib/coreboot_tables.h b/src/commonlib/include/commonlib/coreboot_tables.h
index def48b7797..78dbe8ef4c 100644
--- a/src/commonlib/include/commonlib/coreboot_tables.h
+++ b/src/commonlib/include/commonlib/coreboot_tables.h
@@ -602,6 +602,7 @@ struct lb_efi_fw_info {
 struct lb_cfr {
 	uint32_t tag;
 	uint32_t size;
+	uint32_t version;
 	uint32_t checksum;	/* Checksum of the variable payload. */
 	/* struct lb_cfr_option_form		forms[] */
 };
diff --git a/src/drivers/option/cfr.c b/src/drivers/option/cfr.c
index e833d7bdba..15c4fd9b4e 100644
--- a/src/drivers/option/cfr.c
+++ b/src/drivers/option/cfr.c
@@ -307,6 +307,7 @@ void cfr_write_setup_menu(struct lb_cfr *cfr_root, struct sm_obj_form *sm_root[]
 
 	cfr_root->tag = LB_TAG_CFR_ROOT;
 	cfr_root->size = sizeof(*cfr_root);
+	cfr_root->version = CFR_VERSION;
 
 	current += cfr_root->size;
 	while (sm_root && sm_root[i])

From 17cc750e8bf9ac979756942f3e104febef6dc364 Mon Sep 17 00:00:00 2001
From: Filip Brozovic <fbrozovic@gmail.com>
Date: Tue, 14 Jan 2025 22:42:41 +0100
Subject: [PATCH 0021/3886] CFR: add dependencies based on specific option
 values

Implements a way for CFR options to depend on another option
being set to one or more specific values. This is achieved
by writing a list of values as a varbinary struct.

Change-Id: Iaf7965551490969052eb27c207fa524470d4dd6a
Signed-off-by: Filip Brozovic <fbrozovic@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85987
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 Documentation/drivers/cfr_internal.md | 36 ++++++++++++-
 src/commonlib/include/commonlib/cfr.h |  8 ++-
 src/drivers/option/cfr.c              | 78 ++++++++++++++++++++-------
 src/drivers/option/cfr_frontend.h     | 24 ++++++---
 4 files changed, 117 insertions(+), 29 deletions(-)

diff --git a/Documentation/drivers/cfr_internal.md b/Documentation/drivers/cfr_internal.md
index 95fef66eee..b2355d7b62 100644
--- a/Documentation/drivers/cfr_internal.md
+++ b/Documentation/drivers/cfr_internal.md
@@ -50,8 +50,9 @@ static const struct sm_object serial_number = SM_DECLARE_VARCHAR({
 
 The CFR options can have a dependency that must be evaluated at runtime by
 the OS/payload that parses the CFR record and displays the UI.
-By using the `WITH_DEP()` macro you can specify another numberic option that
-is checked to hide the current option.
+By using the `WITH_DEP()` macro you can specify another numeric option that
+is checked to hide the current option. The `WITH_DEP_VALUES()` macro allows
+specifying one or more values that cause the dependent option to be displayed.
 
 **Example:** Declares a dependency from `sata_disable_port0` to `sata_enable`.
 The option `sata_disable_port0` will be hidden as long as "sata_enable" is 0.
@@ -76,6 +77,37 @@ static struct sm_object sata_disable_port0 = SM_DECLARE_BOOL({
 }, WITH_DEP(&sata_enable));
 ```
 
+**Example:** Declares a dependency from `com1_termination` to `com1_mode`.
+The option `com1_termination` will only be shown if `com1_mode` is set to RS-485.
+
+```
+#define COM_MODE_DISABLED 3
+#define COM_MODE_RS232    0
+#define COM_MODE_RS485    1
+
+static struct sm_object com1_mode = SM_DECLARE_ENUM({
+	.flags		= CFR_OPTFLAG_RUNTIME,
+	.opt_name	= "com1_mode",
+	.ui_name	= "COM1 Mode",
+	.ui_helptext	= NULL,
+	.default_value	= 1,
+	.values		= (const struct sm_enum_value[]) {
+				{ "Disabled", COM_MODE_DISABLED },
+				{ "RS-232",   COM_MODE_RS232    },
+				{ "RS-485",   COM_MODE_RS485    },
+				SM_ENUM_VALUE_END },
+});
+
+static struct sm_object com1_termination = SM_DECLARE_BOOL({
+	.flags		= CFR_OPTFLAG_RUNTIME,
+	.opt_name	= "com1_termination",
+	.ui_name	= "Enable COM1 termination resistors",
+	.ui_helptext	= NULL,
+	.default_value	= false,
+}, WITH_DEP_VALUES(&com1_mode, COM_MODE_RS485));
+
+```
+
 ### Providing mainboard custom options
 
 A mainboard that uses CFR can provide a list of custom options
diff --git a/src/commonlib/include/commonlib/cfr.h b/src/commonlib/include/commonlib/cfr.h
index 5d8b37bf56..570ce3c2d1 100644
--- a/src/commonlib/include/commonlib/cfr.h
+++ b/src/commonlib/include/commonlib/cfr.h
@@ -63,6 +63,7 @@ enum cfr_tags {
 	CFR_TAG_VARCHAR_UI_HELPTEXT	= 9,
 	CFR_TAG_VARCHAR_DEF_VALUE	= 10,
 	CFR_TAG_OPTION_COMMENT		= 11,
+	CFR_TAG_DEP_VALUES		= 12,
 };
 
 /*
@@ -104,7 +105,8 @@ enum cfr_option_flags {
 struct __packed lb_cfr_varbinary {
 	uint32_t tag;		/*
 				 * CFR_TAG_VARCHAR_OPT_NAME, CFR_TAG_VARCHAR_UI_NAME,
-				 * CFR_TAG_VARCHAR_UI_HELPTEXT or CFR_TAG_VARCHAR_DEF_VALUE
+				 * CFR_TAG_VARCHAR_UI_HELPTEXT, CFR_TAG_VARCHAR_DEF_VALUE
+				 * or CFR_TAG_DEP_VALUES
 				 */
 	uint32_t size;		/* Length of the entire structure */
 	uint32_t data_length;	/* Length of data, including NULL terminator for strings */
@@ -136,6 +138,7 @@ struct __packed lb_cfr_numeric_option {
 	 * struct lb_cfr_varbinary		opt_name
 	 * struct lb_cfr_varbinary		ui_name
 	 * struct lb_cfr_varbinary		ui_helptext (Optional)
+	 * struct lb_cfr_varbinary		dependency_values (Optional)
 	 * struct lb_cfr_enum_value		enum_values[]
 	 */
 };
@@ -153,6 +156,7 @@ struct __packed lb_cfr_varchar_option {
 	 * struct lb_cfr_varbinary		opt_name
 	 * struct lb_cfr_varbinary		ui_name
 	 * struct lb_cfr_varbinary		ui_helptext (Optional)
+	 * struct lb_cfr_varbinary		dependency_values (Optional)
 	 */
 };
 
@@ -172,6 +176,7 @@ struct __packed lb_cfr_option_comment {
 	/*
 	 * struct lb_cfr_varbinary		ui_name
 	 * struct lb_cfr_varbinary		ui_helptext (Optional)
+	 * struct lb_cfr_varbinary		dependency_values (Optional)
 	 */
 };
 
@@ -186,6 +191,7 @@ struct __packed lb_cfr_option_form {
 	uint32_t flags;		/* enum cfr_option_flags */
 	/*
 	 * struct lb_cfr_varbinary		ui_name
+	 * struct lb_cfr_varbinary		dependency_values (Optional)
 	 * struct lb_cfr_varchar_option		options[]
 	 */
 };
diff --git a/src/drivers/option/cfr.c b/src/drivers/option/cfr.c
index 15c4fd9b4e..c439ed9546 100644
--- a/src/drivers/option/cfr.c
+++ b/src/drivers/option/cfr.c
@@ -69,6 +69,25 @@ static uint32_t sm_write_ui_helptext(char *current, const char *string)
 	return write_cfr_varchar(current, string, CFR_TAG_VARCHAR_UI_HELPTEXT);
 }
 
+static uint32_t sm_write_dep_values(char *current,
+				    const uint32_t *dep_values, const uint32_t num_dep_values)
+{
+	/* Dependency values are optional */
+	if (!dep_values || !num_dep_values)
+		return 0;
+
+	struct lb_cfr_varbinary *cfr_values = (struct lb_cfr_varbinary *)current;
+	cfr_values->tag = CFR_TAG_DEP_VALUES;
+	cfr_values->data_length = sizeof(*dep_values) * num_dep_values;
+	char *data = current + sizeof(*cfr_values);
+	memcpy(data, dep_values, cfr_values->data_length);
+
+	/* Make sure that every TAG/SIZE field is always aligned to LB_ENTRY_ALIGN */
+	cfr_values->size = ALIGN_UP(sizeof(*cfr_values) + cfr_values->data_length, LB_ENTRY_ALIGN);
+
+	return cfr_values->size;
+}
+
 static uint32_t sm_write_enum_value(char *current, const struct sm_enum_value *e)
 {
 	struct lb_cfr_enum_value *enum_val = (struct lb_cfr_enum_value *)current;
@@ -86,7 +105,7 @@ static uint32_t sm_write_enum_value(char *current, const struct sm_enum_value *e
 static uint32_t write_numeric_option(char *current, uint32_t tag, const uint64_t object_id,
 		const char *opt_name, const char *ui_name, const char *ui_helptext,
 		uint32_t flags, uint32_t default_value, const struct sm_enum_value *values,
-		const uint64_t dep_id)
+		const uint64_t dep_id, const uint32_t *dep_values, const uint32_t num_dep_values)
 {
 	struct lb_cfr_numeric_option *option = (struct lb_cfr_numeric_option *)current;
 	size_t len;
@@ -110,6 +129,7 @@ static uint32_t write_numeric_option(char *current, uint32_t tag, const uint64_t
 		return 0;
 	current += len;
 	current += sm_write_ui_helptext(current, ui_helptext);
+	current += sm_write_dep_values(current, dep_values, num_dep_values);
 
 	if (option->tag == CFR_TAG_OPTION_ENUM && values) {
 		for (const struct sm_enum_value *e = values; e->ui_name; e++) {
@@ -122,35 +142,41 @@ static uint32_t write_numeric_option(char *current, uint32_t tag, const uint64_t
 }
 
 static uint32_t sm_write_opt_enum(char *current, const struct sm_obj_enum *sm_enum,
-				  const uint64_t object_id, const uint64_t dep_id)
+				  const uint64_t object_id, const uint64_t dep_id,
+				  const uint32_t *dep_values, const uint32_t num_dep_values)
 
 {
 	return write_numeric_option(current, CFR_TAG_OPTION_ENUM, object_id,
 			sm_enum->opt_name, sm_enum->ui_name, sm_enum->ui_helptext,
 			sm_enum->flags, sm_enum->default_value, sm_enum->values,
-			dep_id);
+			dep_id, dep_values, num_dep_values);
 }
 
 static uint32_t sm_write_opt_number(char *current, const struct sm_obj_number *sm_number,
-				    const uint64_t object_id, const uint64_t dep_id)
+				    const uint64_t object_id, const uint64_t dep_id,
+				    const uint32_t *dep_values, const uint32_t num_dep_values)
 
 {
 	return write_numeric_option(current, CFR_TAG_OPTION_NUMBER, object_id,
 			sm_number->opt_name, sm_number->ui_name, sm_number->ui_helptext,
-			sm_number->flags, sm_number->default_value, NULL, dep_id);
+			sm_number->flags, sm_number->default_value, NULL, dep_id,
+			dep_values, num_dep_values);
 }
 
 static uint32_t sm_write_opt_bool(char *current, const struct sm_obj_bool *sm_bool,
-				  const uint64_t object_id, const uint64_t dep_id)
+				  const uint64_t object_id, const uint64_t dep_id,
+				  const uint32_t *dep_values, const uint32_t num_dep_values)
 
 {
 	return write_numeric_option(current, CFR_TAG_OPTION_BOOL, object_id,
 			sm_bool->opt_name, sm_bool->ui_name, sm_bool->ui_helptext,
-			sm_bool->flags, sm_bool->default_value, NULL, dep_id);
+			sm_bool->flags, sm_bool->default_value, NULL, dep_id,
+			dep_values, num_dep_values);
 }
 
 static uint32_t sm_write_opt_varchar(char *current, const struct sm_obj_varchar *sm_varchar,
-				     const uint64_t object_id, const uint64_t dep_id)
+				     const uint64_t object_id, const uint64_t dep_id,
+				     const uint32_t *dep_values, const uint32_t num_dep_values)
 
 {
 	struct lb_cfr_varchar_option *option = (struct lb_cfr_varchar_option *)current;
@@ -175,13 +201,15 @@ static uint32_t sm_write_opt_varchar(char *current, const struct sm_obj_varchar
 		return 0;
 	current += len;
 	current += sm_write_ui_helptext(current, sm_varchar->ui_helptext);
+	current += sm_write_dep_values(current, dep_values, num_dep_values);
 
 	option->size = cfr_record_size((char *)option, current);
 	return option->size;
 }
 
 static uint32_t sm_write_opt_comment(char *current, const struct sm_obj_comment *sm_comment,
-				     const uint32_t object_id, const uint32_t dep_id)
+				     const uint32_t object_id, const uint32_t dep_id,
+				     const uint32_t *dep_values, const uint32_t num_dep_values)
 {
 	struct lb_cfr_option_comment *comment = (struct lb_cfr_option_comment *)current;
 	size_t len;
@@ -200,6 +228,7 @@ static uint32_t sm_write_opt_comment(char *current, const struct sm_obj_comment
 		return 0;
 	current += len;
 	current += sm_write_ui_helptext(current, sm_comment->ui_helptext);
+	current += sm_write_dep_values(current, dep_values, num_dep_values);
 
 	comment->size = cfr_record_size((char *)comment, current);
 	return comment->size;
@@ -215,7 +244,8 @@ static uint64_t sm_gen_obj_id(void *ptr)
 static uint32_t sm_write_object(char *current, const struct sm_object *sm_obj);
 
 static uint32_t sm_write_form(char *current, struct sm_obj_form *sm_form,
-			      const uint64_t object_id, const uint64_t dep_id)
+			      const uint64_t object_id, const uint64_t dep_id,
+			      const uint32_t *dep_values, const uint32_t num_dep_values)
 {
 	struct lb_cfr_option_form *form = (struct lb_cfr_option_form *)current;
 	size_t len;
@@ -234,6 +264,7 @@ static uint32_t sm_write_form(char *current, struct sm_obj_form *sm_form,
 	if (!len)
 		return 0;
 	current += len;
+	current += sm_write_dep_values(current, dep_values, num_dep_values);
 
 	while (sm_form->obj_list[i])
 		current += sm_write_object(current, sm_form->obj_list[i++]);
@@ -245,6 +276,8 @@ static uint32_t sm_write_form(char *current, struct sm_obj_form *sm_form,
 static uint32_t sm_write_object(char *current, const struct sm_object *sm_obj)
 {
 	uint64_t dep_id, obj_id;
+	const uint32_t *dep_values;
+	uint32_t num_dep_values;
 	struct sm_object sm_obj_copy;
 	assert(sm_obj);
 
@@ -253,10 +286,14 @@ static uint32_t sm_write_object(char *current, const struct sm_object *sm_obj)
 
 	/* Set dependency ID */
 	dep_id = 0;
+	dep_values = NULL;
+	num_dep_values = 0;
 	if (sm_obj->dep) {
-		assert(sm_obj->dep->kind == SM_OBJ_BOOL);
-		if (sm_obj->dep->kind == SM_OBJ_BOOL)
+		if (sm_obj->dep->kind == SM_OBJ_BOOL || sm_obj->dep->kind == SM_OBJ_ENUM) {
 			dep_id = sm_gen_obj_id((void *)sm_obj->dep);
+			dep_values = sm_obj->dep_values;
+			num_dep_values = sm_obj->num_dep_values;
+		}
 	}
 
 	/* Invoke callback to update fields */
@@ -273,21 +310,22 @@ static uint32_t sm_write_object(char *current, const struct sm_object *sm_obj)
 		return 0;
 	case SM_OBJ_ENUM:
 		return sm_write_opt_enum(current, &sm_obj->sm_enum, obj_id,
-					 dep_id);
+					 dep_id, dep_values, num_dep_values);
 	case SM_OBJ_NUMBER:
 		return sm_write_opt_number(current, &sm_obj->sm_number, obj_id,
-					   dep_id);
+					   dep_id, dep_values, num_dep_values);
 	case SM_OBJ_BOOL:
 		return sm_write_opt_bool(current, &sm_obj->sm_bool, obj_id,
-					 dep_id);
+					 dep_id, dep_values, num_dep_values);
 	case SM_OBJ_VARCHAR:
 		return sm_write_opt_varchar(current, &sm_obj->sm_varchar, obj_id,
-					    dep_id);
+					    dep_id, dep_values, num_dep_values);
 	case SM_OBJ_COMMENT:
 		return sm_write_opt_comment(current, &sm_obj->sm_comment, obj_id,
-					    dep_id);
+					    dep_id, dep_values, num_dep_values);
 	case SM_OBJ_FORM:
-		return sm_write_form(current, (struct sm_obj_form *)&sm_obj->sm_form, obj_id, dep_id);
+		return sm_write_form(current, (struct sm_obj_form *)&sm_obj->sm_form, obj_id,
+				     dep_id, dep_values, num_dep_values);
 	default:
 		BUG();
 		printk(BIOS_ERR, "Unknown setup menu object kind %u, ignoring\n", sm_obj->kind);
@@ -311,13 +349,13 @@ void cfr_write_setup_menu(struct lb_cfr *cfr_root, struct sm_obj_form *sm_root[]
 
 	current += cfr_root->size;
 	while (sm_root && sm_root[i])
-		current += sm_write_form(current, sm_root[i++], 0, 0);
+		current += sm_write_form(current, sm_root[i++], 0, 0, NULL, 0);
 
 	/*
 	 * Add generic forms.
 	 */
 	for (obj = &_cfr_forms[0]; obj != &_ecfr_forms[0]; obj++)
-		current += sm_write_form(current, obj, 0, 0);
+		current += sm_write_form(current, obj, 0, 0, NULL, 0);
 
 	cfr_root->size = cfr_record_size((char *)cfr_root, current);
 
diff --git a/src/drivers/option/cfr_frontend.h b/src/drivers/option/cfr_frontend.h
index 2161853f01..21c18e779f 100644
--- a/src/drivers/option/cfr_frontend.h
+++ b/src/drivers/option/cfr_frontend.h
@@ -75,6 +75,8 @@ enum sm_object_kind {
 struct sm_object {
 	enum sm_object_kind kind;
 	const struct sm_object *dep;
+	const uint32_t *dep_values;
+	const uint32_t num_dep_values;
 	void (*ctor)(const struct sm_object *obj, struct sm_object *new);	/* Called on object creation */
 	union {
 		struct sm_obj_enum sm_enum;
@@ -87,21 +89,31 @@ struct sm_object {
 };
 
 /* sm_object helpers with type checking */
-#define SM_DECLARE_ENUM(...)	{ .kind = SM_OBJ_ENUM,    .dep = NULL, \
+#define SM_DECLARE_ENUM(...)	{ .kind = SM_OBJ_ENUM,    .dep = NULL,     \
+				  .dep_values = NULL, .num_dep_values = 0, \
 				  .ctor = NULL, .sm_enum    = __VA_ARGS__ }
-#define SM_DECLARE_NUMBER(...)	{ .kind = SM_OBJ_NUMBER,  .dep = NULL, \
+#define SM_DECLARE_NUMBER(...)	{ .kind = SM_OBJ_NUMBER,  .dep = NULL,     \
+				  .dep_values = NULL, .num_dep_values = 0, \
 				  .ctor = NULL, .sm_number  = __VA_ARGS__ }
-#define SM_DECLARE_BOOL(...)	{ .kind = SM_OBJ_BOOL,    .dep = NULL, \
+#define SM_DECLARE_BOOL(...)	{ .kind = SM_OBJ_BOOL,    .dep = NULL,     \
+				  .dep_values = NULL, .num_dep_values = 0, \
 				  .ctor = NULL, .sm_bool    = __VA_ARGS__ }
-#define SM_DECLARE_VARCHAR(...)	{ .kind = SM_OBJ_VARCHAR, .dep = NULL, \
+#define SM_DECLARE_VARCHAR(...)	{ .kind = SM_OBJ_VARCHAR, .dep = NULL,     \
+				  .dep_values = NULL, .num_dep_values = 0, \
 				  .ctor = NULL, .sm_varchar = __VA_ARGS__ }
-#define SM_DECLARE_COMMENT(...)	{ .kind = SM_OBJ_COMMENT, .dep = NULL, \
+#define SM_DECLARE_COMMENT(...)	{ .kind = SM_OBJ_COMMENT, .dep = NULL,     \
+				  .dep_values = NULL, .num_dep_values = 0, \
 				  .ctor = NULL, .sm_comment = __VA_ARGS__ }
-#define SM_DECLARE_FORM(...)	{ .kind = SM_OBJ_FORM,    .dep = NULL, \
+#define SM_DECLARE_FORM(...)	{ .kind = SM_OBJ_FORM,    .dep = NULL,     \
+				  .dep_values = NULL, .num_dep_values = 0, \
 				  .ctor = NULL, .sm_form    = __VA_ARGS__ }
 
 #define WITH_CALLBACK(c) .ctor = (c)
 #define WITH_DEP(d) .dep = (d)
+#define WITH_DEP_VALUES(d, ...)							\
+	.dep = (d),								\
+	.dep_values = ((const uint32_t[]) { __VA_ARGS__ }),			\
+	.num_dep_values = sizeof((uint32_t[]) { __VA_ARGS__ }) / sizeof(uint32_t)
 
 void cfr_write_setup_menu(struct lb_cfr *cfr_root, struct sm_obj_form *sm_root[]);
 

From 3a6481aeb2fb7547afd7b2795a5479e24afbd4e6 Mon Sep 17 00:00:00 2001
From: Filip Brozovic <fbrozovic@gmail.com>
Date: Tue, 21 Jan 2025 12:02:10 +0100
Subject: [PATCH 0022/3886] CFR: Add min/max/step values and hex display flag
 for number options

This commit adds support for minimum/maximum limit values as well as
step sizes for CFR number options. Additionally, add a new flag that
specifies the option should be displayed in hexadecimal notation instead
of decimal.

Change-Id: I2e70f1430fb1911f1ad974832f8abfe76f928ac3
Signed-off-by: Filip Brozovic <fbrozovic@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86039
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
---
 src/commonlib/include/commonlib/cfr.h | 14 ++++++++++++++
 src/drivers/option/cfr.c              | 18 ++++++++++++------
 src/drivers/option/cfr_frontend.h     |  4 ++++
 3 files changed, 30 insertions(+), 6 deletions(-)

diff --git a/src/commonlib/include/commonlib/cfr.h b/src/commonlib/include/commonlib/cfr.h
index 570ce3c2d1..af68269e29 100644
--- a/src/commonlib/include/commonlib/cfr.h
+++ b/src/commonlib/include/commonlib/cfr.h
@@ -121,6 +121,15 @@ struct __packed lb_cfr_enum_value {
 	 */
 };
 
+/*
+ * The optional flags describe how a numeric option is to be displayed.
+ * CFR_NUM_OPT_DISPFLAG_HEX:
+ *   Displays a NUMBER option in hexadecimal instead of decimal notation.
+ */
+enum cfr_numeric_option_display_flags {
+	CFR_NUM_OPT_DISPFLAG_HEX	= 1 << 0,
+};
+
 /* Supports multiple option types: ENUM, NUMBER, BOOL */
 struct __packed lb_cfr_numeric_option {
 	uint32_t tag;		/*
@@ -134,6 +143,11 @@ struct __packed lb_cfr_numeric_option {
 				 */
 	uint32_t flags;		/* enum cfr_option_flags */
 	uint32_t default_value;
+	uint32_t min;
+	uint32_t max;
+	uint32_t step;
+	uint32_t display_flags;	/* enum cfr_numeric_option_display_flags */
+
 	/*
 	 * struct lb_cfr_varbinary		opt_name
 	 * struct lb_cfr_varbinary		ui_name
diff --git a/src/drivers/option/cfr.c b/src/drivers/option/cfr.c
index c439ed9546..26bdd55f4d 100644
--- a/src/drivers/option/cfr.c
+++ b/src/drivers/option/cfr.c
@@ -104,8 +104,9 @@ static uint32_t sm_write_enum_value(char *current, const struct sm_enum_value *e
 
 static uint32_t write_numeric_option(char *current, uint32_t tag, const uint64_t object_id,
 		const char *opt_name, const char *ui_name, const char *ui_helptext,
-		uint32_t flags, uint32_t default_value, const struct sm_enum_value *values,
-		const uint64_t dep_id, const uint32_t *dep_values, const uint32_t num_dep_values)
+		uint32_t flags, uint32_t default_value, uint32_t min, uint32_t max, uint32_t step,
+		uint32_t display_flags, const struct sm_enum_value *values, const uint64_t dep_id,
+		const uint32_t *dep_values, const uint32_t num_dep_values)
 {
 	struct lb_cfr_numeric_option *option = (struct lb_cfr_numeric_option *)current;
 	size_t len;
@@ -117,6 +118,10 @@ static uint32_t write_numeric_option(char *current, uint32_t tag, const uint64_t
 	if (option->flags & (CFR_OPTFLAG_INACTIVE | CFR_OPTFLAG_VOLATILE))
 		option->flags |= CFR_OPTFLAG_READONLY;
 	option->default_value = default_value;
+	option->min = (min <= max) ? min : 0;
+	option->max = (min == 0 && max == 0) ? UINT32_MAX : max;
+	option->step = step;
+	option->display_flags = display_flags;
 	option->size = sizeof(*option);
 
 	current += option->size;
@@ -148,7 +153,7 @@ static uint32_t sm_write_opt_enum(char *current, const struct sm_obj_enum *sm_en
 {
 	return write_numeric_option(current, CFR_TAG_OPTION_ENUM, object_id,
 			sm_enum->opt_name, sm_enum->ui_name, sm_enum->ui_helptext,
-			sm_enum->flags, sm_enum->default_value, sm_enum->values,
+			sm_enum->flags, sm_enum->default_value, 0, 0, 0, 0, sm_enum->values,
 			dep_id, dep_values, num_dep_values);
 }
 
@@ -159,8 +164,9 @@ static uint32_t sm_write_opt_number(char *current, const struct sm_obj_number *s
 {
 	return write_numeric_option(current, CFR_TAG_OPTION_NUMBER, object_id,
 			sm_number->opt_name, sm_number->ui_name, sm_number->ui_helptext,
-			sm_number->flags, sm_number->default_value, NULL, dep_id,
-			dep_values, num_dep_values);
+			sm_number->flags, sm_number->default_value, sm_number->min, sm_number->max,
+			sm_number->step, sm_number->display_flags, NULL, dep_id, dep_values,
+			num_dep_values);
 }
 
 static uint32_t sm_write_opt_bool(char *current, const struct sm_obj_bool *sm_bool,
@@ -170,7 +176,7 @@ static uint32_t sm_write_opt_bool(char *current, const struct sm_obj_bool *sm_bo
 {
 	return write_numeric_option(current, CFR_TAG_OPTION_BOOL, object_id,
 			sm_bool->opt_name, sm_bool->ui_name, sm_bool->ui_helptext,
-			sm_bool->flags, sm_bool->default_value, NULL, dep_id,
+			sm_bool->flags, sm_bool->default_value, 0, 0, 0, 0, NULL, dep_id,
 			dep_values, num_dep_values);
 }
 
diff --git a/src/drivers/option/cfr_frontend.h b/src/drivers/option/cfr_frontend.h
index 21c18e779f..17332bdca4 100644
--- a/src/drivers/option/cfr_frontend.h
+++ b/src/drivers/option/cfr_frontend.h
@@ -30,6 +30,10 @@ struct sm_obj_number {
 	const char *ui_name;
 	const char *ui_helptext;
 	uint32_t default_value;
+	uint32_t min;
+	uint32_t max;
+	uint32_t step;
+	uint32_t display_flags;	/* enum cfr_numeric_option_display_flags */
 };
 
 struct sm_obj_bool {

From a7755bb35f7929de806ee3adf730f8c1d8de744e Mon Sep 17 00:00:00 2001
From: Yunlong Jia <yunlong.jia@ecs.corp-partner.google.com>
Date: Thu, 6 Feb 2025 10:25:14 +0000
Subject: [PATCH 0023/3886] mb/google/nissa/var/gothrax: Add 2 Hynix parts to
 RAM ID table

Add the support RAM parts for gothrax.
Here is the ram part number list:
DRAM Part Name                 ID to assign
MT62F512M32D2DR-031 WT:B       0 (0000)
H58G56AK6BX069                 1 (0001)
K3LKBKB0BM-MGCP                2 (0010)
H9JCNNNBK3MLYR-N6E             0 (0000)
H9JCNNNCP3MLYR-N6E             3 (0011)

BUG=b:394756067
BRANCH=None
TEST=emerge-nissa coreboot

Change-Id: I9945ef9f8b9f5de8aedc34e4bc41c29a702be819
Signed-off-by: Yunlong Jia <yunlong.jia@ecs.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86296
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/google/brya/variants/gothrax/memory/Makefile.mk  | 3 ++-
 .../google/brya/variants/gothrax/memory/dram_id.generated.txt  | 2 ++
 .../google/brya/variants/gothrax/memory/mem_parts_used.txt     | 2 ++
 3 files changed, 6 insertions(+), 1 deletion(-)

diff --git a/src/mainboard/google/brya/variants/gothrax/memory/Makefile.mk b/src/mainboard/google/brya/variants/gothrax/memory/Makefile.mk
index d3c1f68a7f..96e2023b84 100644
--- a/src/mainboard/google/brya/variants/gothrax/memory/Makefile.mk
+++ b/src/mainboard/google/brya/variants/gothrax/memory/Makefile.mk
@@ -4,6 +4,7 @@
 # ./util/spd_tools/bin/part_id_gen ADL lp5 src/mainboard/google/brya/variants/gothrax/memory src/mainboard/google/brya/variants/gothrax/memory/mem_parts_used.txt
 
 SPD_SOURCES =
-SPD_SOURCES += spd/lp5/set-0/spd-1.hex      # ID = 0(0b0000)  Parts = MT62F512M32D2DR-031 WT:B
+SPD_SOURCES += spd/lp5/set-0/spd-1.hex      # ID = 0(0b0000)  Parts = MT62F512M32D2DR-031 WT:B, H9JCNNNBK3MLYR-N6E
 SPD_SOURCES += spd/lp5/set-0/spd-3.hex      # ID = 1(0b0001)  Parts = H58G56AK6BX069
 SPD_SOURCES += spd/lp5/set-0/spd-3.hex      # ID = 2(0b0010)  Parts = K3LKBKB0BM-MGCP
+SPD_SOURCES += spd/lp5/set-0/spd-2.hex      # ID = 3(0b0011)  Parts = H9JCNNNCP3MLYR-N6E
diff --git a/src/mainboard/google/brya/variants/gothrax/memory/dram_id.generated.txt b/src/mainboard/google/brya/variants/gothrax/memory/dram_id.generated.txt
index 7db6e24407..ee10ecfe49 100644
--- a/src/mainboard/google/brya/variants/gothrax/memory/dram_id.generated.txt
+++ b/src/mainboard/google/brya/variants/gothrax/memory/dram_id.generated.txt
@@ -7,3 +7,5 @@ DRAM Part Name                 ID to assign
 MT62F512M32D2DR-031 WT:B       0 (0000)
 H58G56AK6BX069                 1 (0001)
 K3LKBKB0BM-MGCP                2 (0010)
+H9JCNNNBK3MLYR-N6E             0 (0000)
+H9JCNNNCP3MLYR-N6E             3 (0011)
diff --git a/src/mainboard/google/brya/variants/gothrax/memory/mem_parts_used.txt b/src/mainboard/google/brya/variants/gothrax/memory/mem_parts_used.txt
index f38995e01b..5d050345ae 100644
--- a/src/mainboard/google/brya/variants/gothrax/memory/mem_parts_used.txt
+++ b/src/mainboard/google/brya/variants/gothrax/memory/mem_parts_used.txt
@@ -13,3 +13,5 @@
 MT62F512M32D2DR-031 WT:B,
 H58G56AK6BX069,*1
 K3LKBKB0BM-MGCP,
+H9JCNNNBK3MLYR-N6E,
+H9JCNNNCP3MLYR-N6E,

From 1b2c7c588d39d334942ee9baebe702e5a311c9aa Mon Sep 17 00:00:00 2001
From: jamie_chen <jamie_chen@compal.corp-partner.google.com>
Date: Thu, 6 Feb 2025 10:12:10 +0800
Subject: [PATCH 0024/3886] mb/google/trulo/var/uldrenite: Add WIFI SAR table

Add WIFI SAR table for uldrenite.

BUG=b:384453900
BRANCH=firmware-trulo-15217.771.B
TEST=emerge-nissa coreboot chromeos-bootimage

Change-Id: Ieb7f7ba54aaa6bdf1a19e59e57eb46cfafd655fe
Signed-off-by: jamie_chen <jamie_chen@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86291
Reviewed-by: Jayvik Desai <jayvik@google.com>
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
---
 src/mainboard/google/brya/Kconfig                      | 1 +
 src/mainboard/google/brya/variants/uldrenite/variant.c | 6 ++++++
 2 files changed, 7 insertions(+)

diff --git a/src/mainboard/google/brya/Kconfig b/src/mainboard/google/brya/Kconfig
index dfa571e6ce..58b8922448 100644
--- a/src/mainboard/google/brya/Kconfig
+++ b/src/mainboard/google/brya/Kconfig
@@ -638,6 +638,7 @@ config BOARD_GOOGLE_ULDREN
 config BOARD_GOOGLE_ULDRENITE
 	select BOARD_GOOGLE_BASEBOARD_TRULO
 	select BOARD_ROMSIZE_KB_32768
+	select CHROMEOS_WIFI_SAR if CHROMEOS
 	select SOC_INTEL_TCSS_USE_PDC_PMC_USBC_MUX_CONFIGURATION
 	select HAVE_PCIE_WWAN
 	select HAVE_WWAN_POWER_SEQUENCE
diff --git a/src/mainboard/google/brya/variants/uldrenite/variant.c b/src/mainboard/google/brya/variants/uldrenite/variant.c
index f5bbaf6924..41ab7b8c14 100644
--- a/src/mainboard/google/brya/variants/uldrenite/variant.c
+++ b/src/mainboard/google/brya/variants/uldrenite/variant.c
@@ -5,10 +5,16 @@
 #include <console/console.h>
 #include <delay.h>
 #include <fw_config.h>
+#include <sar.h>
 
 #define RW350R_RST_DELAY_MS 20
 #define RW350R_PERST_DELAY_MS 30
 
+const char *get_wifi_sar_cbfs_filename(void)
+{
+	return "wifi_sar_0.hex";
+}
+
 static const struct pad_config rw350r_en_pad[] = {
 	/* H23 : LTE_PWR_OFF_EN */
 	PAD_CFG_GPO(GPP_H23, 1, DEEP),

From e914a551a232a22310ad479ccc56e007c99a2f74 Mon Sep 17 00:00:00 2001
From: Ian Feng <ian_feng@compal.corp-partner.google.com>
Date: Tue, 4 Feb 2025 14:47:59 +0800
Subject: [PATCH 0025/3886] mb/google/fatcat/var/francka: Enable CNVi wifi core

Enable CNVi wifi core for francka.

BUG=b:391772114
TEST=Build and boot to OS in francka.
lspci:
00:14.3 Network controller: Intel Corporation Device e440

Change-Id: I80c38882aab801dedb05355774e5b930a8528fed
Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86262
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jayvik Desai <jayvik@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
---
 src/mainboard/google/fatcat/variants/francka/overridetree.cb | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/src/mainboard/google/fatcat/variants/francka/overridetree.cb b/src/mainboard/google/fatcat/variants/francka/overridetree.cb
index dc76b85639..58ced1aa07 100644
--- a/src/mainboard/google/fatcat/variants/francka/overridetree.cb
+++ b/src/mainboard/google/fatcat/variants/francka/overridetree.cb
@@ -53,6 +53,9 @@ chip soc/intel/pantherlake
 	# TCSS USB3
 	register "tcss_aux_ori" = "1"
 
+	# Enable CNVi WiFi
+	register "cnvi_wifi_core" = "true"
+
 	register "serial_io_i2c_mode" = "{
 		[PchSerialIoIndexI2C0]  = PchSerialIoPci,
 		[PchSerialIoIndexI2C1]  = PchSerialIoPci,

From 16bd8b206535e279a4e7b89ca99fdc2c6420946d Mon Sep 17 00:00:00 2001
From: David Wu <david_wu@quanta.corp-partner.google.com>
Date: Tue, 4 Feb 2025 19:44:10 +0800
Subject: [PATCH 0026/3886] mb/google/nissa/var/riven: Add fw_config probe for
 all wifi

Add fw_config probe to enable all wifi for factory use.

BUG=None
TEST=emerge-nissa coreboot chromeos-bootimage

Change-Id: Ic7326266fd8d69cb76257b01c1d9083a2e30a2b3
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86266
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jayvik Desai <jayvik@google.com>
---
 src/mainboard/google/brya/variants/riven/overridetree.cb | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/src/mainboard/google/brya/variants/riven/overridetree.cb b/src/mainboard/google/brya/variants/riven/overridetree.cb
index 359c4275df..9e5fa3cd2e 100644
--- a/src/mainboard/google/brya/variants/riven/overridetree.cb
+++ b/src/mainboard/google/brya/variants/riven/overridetree.cb
@@ -21,6 +21,9 @@ fw_config
 		option WFC_MIPI_OVTI5675	1
 		option WFC_MIPI_OVTI8856	2
 	end
+	field ALL_WIFI 19 19
+		option WIFI_ENABLE		1
+	end
 end
 
 chip soc/intel/alderlake
@@ -230,6 +233,7 @@ chip soc/intel/alderlake
 				register "enable_cnvi_ddr_rfim" = "true"
 				device generic 0 on
 					probe WIFI_TYPE WIFI_CNVI
+					probe ALL_WIFI WIFI_ENABLE
 				end
 			end
 		end
@@ -482,6 +486,7 @@ chip soc/intel/alderlake
 		end
 		device ref pcie_rp4 on
 			probe WIFI_TYPE WIFI_PCIE
+			probe ALL_WIFI WIFI_ENABLE
 			# Enable wlan PCIe 4 using clk 2
 			register "pch_pcie_rp[PCH_RP(4)]" = "{
 				.clk_src = 2,
@@ -495,6 +500,7 @@ chip soc/intel/alderlake
 				use usb2_port8 as bluetooth_companion
 				device pci 00.0 on
 					probe WIFI_TYPE WIFI_PCIE
+					probe ALL_WIFI WIFI_ENABLE
 				end
 			end
 			chip soc/intel/common/block/pcie/rtd3
@@ -503,6 +509,7 @@ chip soc/intel/alderlake
 				register "srcclk_pin" = "2"
 				device generic 0 on
 					probe WIFI_TYPE WIFI_PCIE
+					probe ALL_WIFI WIFI_ENABLE
 				end
 			end
 		end
@@ -624,6 +631,7 @@ chip soc/intel/alderlake
 							"ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D4)"
 						device ref usb2_port8 on
 							probe WIFI_TYPE WIFI_PCIE
+							probe ALL_WIFI WIFI_ENABLE
 						end
 					end
 					chip drivers/usb/acpi
@@ -633,6 +641,7 @@ chip soc/intel/alderlake
 							"ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D4)"
 						device ref usb2_port10 on
 							probe WIFI_TYPE WIFI_CNVI
+							probe ALL_WIFI WIFI_ENABLE
 						end
 					end
 					chip drivers/usb/acpi

From 656f26ee3c3797dd058ddec7994f4f5696ad5149 Mon Sep 17 00:00:00 2001
From: Brandon Weeks <bweeks@google.com>
Date: Mon, 3 Feb 2025 16:17:37 -0800
Subject: [PATCH 0027/3886] soc/intel/alderlake: Add missing min sleep state
 for SMBUS device

Fixes:
Unknown min d_state for PCI: 00:1f.4

Change-Id: I8050c8d574ea5908d5ad3f1e5a034257fabb72c5
Signed-off-by: Brandon Weeks <bweeks@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86259
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
---
 src/soc/intel/alderlake/acpi.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/src/soc/intel/alderlake/acpi.c b/src/soc/intel/alderlake/acpi.c
index 463112fb6a..4c5a515142 100644
--- a/src/soc/intel/alderlake/acpi.c
+++ b/src/soc/intel/alderlake/acpi.c
@@ -217,6 +217,7 @@ static struct min_sleep_state min_pci_sleep_states[] = {
 	{ PCH_DEVFN_ESPI,	ACPI_DEVICE_SLEEP_D0 },
 	{ PCH_DEVFN_PMC,	ACPI_DEVICE_SLEEP_D0 },
 	{ PCH_DEVFN_HDA,	ACPI_DEVICE_SLEEP_D0 },
+	{ PCH_DEVFN_SMBUS,	ACPI_DEVICE_SLEEP_D0 },
 	{ PCH_DEVFN_SPI,	ACPI_DEVICE_SLEEP_D3 },
 	{ PCH_DEVFN_GBE,	ACPI_DEVICE_SLEEP_D3 },
 };

From bbe8a63e346b4dfb70ed1d93dad21d4f213d9f12 Mon Sep 17 00:00:00 2001
From: Subrata Banik <subratabanik@google.com>
Date: Thu, 6 Feb 2025 10:51:01 +0530
Subject: [PATCH 0028/3886] mainboard/google/fatcat: Set TCC offset

This commit sets the TCC offset for the Fatcat baseboard variant.
A value of 10 was chosen, resulting in a TCC trip point of 100C
(Tjmax of 110C - offset of 10C).

This allows for thermal throttling to begin at a more appropriate
temperature.

Fatcat variants can override the TCC offset as per platform
requirements between power and/or performance.

TEST=Able to build and boot to CrOS.

Change-Id: I2a57fd3b06378f4e62872ffeb116a65561100e33
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86292
Reviewed-by: Jamie Ryu <jamie.m.ryu@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
---
 .../google/fatcat/variants/baseboard/fatcat/devicetree.cb      | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/src/mainboard/google/fatcat/variants/baseboard/fatcat/devicetree.cb b/src/mainboard/google/fatcat/variants/baseboard/fatcat/devicetree.cb
index c217a159e1..b09f9e324b 100644
--- a/src/mainboard/google/fatcat/variants/baseboard/fatcat/devicetree.cb
+++ b/src/mainboard/google/fatcat/variants/baseboard/fatcat/devicetree.cb
@@ -51,6 +51,9 @@ chip soc/intel/pantherlake
 	# DPTF enable
 	register "dptf_enable" = "true"
 
+	# Setting TCC of 100C = Tj max (110) - TCC_Offset (10)
+	register "tcc_offset" = "10"
+
 	# Disable C1 C-state auto-demotion
 	register "disable_c1_state_auto_demotion" = "true"
 	# Disable PKGC-state auto-demotion

From 259306a296ed9d8ccc87214eb930ffd15f23640e Mon Sep 17 00:00:00 2001
From: Jarried Lin <jarried.lin@mediatek.corp-partner.google.com>
Date: Fri, 7 Feb 2025 15:36:31 +0800
Subject: [PATCH 0029/3886] mb/google/rauru: Deassert PCIe PERST# earlier in
 romstage

Reorder the PCIe reset before mtk_dram_init to overlap the de-assert
time with the DRAM initialization process. This change helps to optimize
the initialization sequence and reduce overall boot time.

BRANCH=rauru
TEST=Build pass
BUG=b:391333055

Change-Id: I24b254ff3a3cbe6d9a60a8e6afea2c621e0a07e2
Signed-off-by: Jarried Lin <jarried.lin@mediatek.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86311
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
---
 src/mainboard/google/rauru/romstage.c | 5 ++---
 1 file changed, 2 insertions(+), 3 deletions(-)

diff --git a/src/mainboard/google/rauru/romstage.c b/src/mainboard/google/rauru/romstage.c
index 7860dfd092..584af61d0f 100644
--- a/src/mainboard/google/rauru/romstage.c
+++ b/src/mainboard/google/rauru/romstage.c
@@ -47,11 +47,10 @@ void platform_romstage_main(void)
 	clk_buf_init();
 	if (CONFIG(RTC))
 		rtc_boot();
+	if (CONFIG(PCI))
+		mtk_pcie_deassert_perst();
 	mtk_dram_init();
 	modem_power_down();
 	dvfs_init();
 	thermal_init();
-
-	if (CONFIG(PCI))
-		mtk_pcie_deassert_perst();
 }

From 5ff1ce69635097080edecce7b0b6cfe557e8046c Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Fri, 7 Feb 2025 19:55:16 +0000
Subject: [PATCH 0030/3886] ec/starlabs/merlin: Remove unused name objects

These are not referenced anywhere, so remove them.

Change-Id: Ieb66099dcb9e13b26e6a7a752584537c060c8c18
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86317
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/ec/starlabs/merlin/acpi/ec.asl | 24 ------------------------
 1 file changed, 24 deletions(-)

diff --git a/src/ec/starlabs/merlin/acpi/ec.asl b/src/ec/starlabs/merlin/acpi/ec.asl
index 8fa16c5d05..35604840cb 100644
--- a/src/ec/starlabs/merlin/acpi/ec.asl
+++ b/src/ec/starlabs/merlin/acpi/ec.asl
@@ -11,30 +11,6 @@ Scope (\_SB.PCI0.LPCB)
 		Name (_GPE, CONFIG_EC_GPE_SCI)
 		Name (ECAV, 0x00)
 		Name (ECTK, 0x01)
-		Name (B2ST, 0x00)
-		Name (CFAN, 0x00)
-		Name (CMDR, 0x00)
-		Name (DOCK, 0x00)
-		Name (PLMX, 0x00)
-		Name (PECH, 0x00)
-		Name (PECL, 0x00)
-		Name (PENV, 0x00)
-		Name (PINV, 0x00)
-		Name (PPSH, 0x00)
-		Name (PPSL, 0x00)
-		Name (PSTP, 0x00)
-		Name (RPWR, 0x00)
-		Name (VPWR, 0x00)
-		Name (WTMS, 0x00)
-		Name (AWT2, 0x00)
-		Name (AWT1, 0x00)
-		Name (AWT0, 0x00)
-		Name (DLED, 0x00)
-		Name (SPT2, 0x00)
-		Name (PB10, 0x00)
-		Name (IWCW, 0x00)
-		Name (IWCR, 0x00)
-		Name (PVOL, 0x00)
 		Mutex (ECMT, 0x00)
 
 		Name (BFFR, ResourceTemplate()

From bf4da5f27276a8ab86ae24a0bd939c12cdcf7aa4 Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Thu, 6 Feb 2025 20:41:30 +0000
Subject: [PATCH 0031/3886] mb/starlabs/starbook/mtl: Enable Early Command
 Training

Enable Early Command Training.

Test=build and boot `starbook/mtl`, verify no issues in  FSP debug log
and enter/ exit s3.

Change-Id: I18d94537ec662e11ef09065569e1695403490012
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86308
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/starlabs/starbook/variants/mtl/romstage.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/mainboard/starlabs/starbook/variants/mtl/romstage.c b/src/mainboard/starlabs/starbook/variants/mtl/romstage.c
index 26a4e5eb3c..d938badb5a 100644
--- a/src/mainboard/starlabs/starbook/variants/mtl/romstage.c
+++ b/src/mainboard/starlabs/starbook/variants/mtl/romstage.c
@@ -9,7 +9,7 @@ void mainboard_memory_init_params(FSPM_UPD *mupd)
 {
 	const struct mb_cfg mem_config = {
 		.type = MEM_TYPE_DDR5,
-		.ect = false,
+		.ect = true,
 		.UserBd = BOARD_TYPE_MOBILE,
 		.ddr_config = {
 			.dq_pins_interleaved = false,

From ceaed25bf1800dff0432f26e06f2eee15b67ceab Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Thu, 6 Feb 2025 21:08:34 +0000
Subject: [PATCH 0032/3886] mb/starlabs/starbook/mtl: Change the user board
 type

Change the board type to ULX as seen in the AMI CRB. This fixes
failed memory training for certain memory modules.

Change-Id: I951387fcfc0be8fb931b4c5ac0b5f022e057b371
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86310
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
---
 src/mainboard/starlabs/starbook/variants/mtl/romstage.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/mainboard/starlabs/starbook/variants/mtl/romstage.c b/src/mainboard/starlabs/starbook/variants/mtl/romstage.c
index d938badb5a..7d9b9ae4fd 100644
--- a/src/mainboard/starlabs/starbook/variants/mtl/romstage.c
+++ b/src/mainboard/starlabs/starbook/variants/mtl/romstage.c
@@ -10,7 +10,7 @@ void mainboard_memory_init_params(FSPM_UPD *mupd)
 	const struct mb_cfg mem_config = {
 		.type = MEM_TYPE_DDR5,
 		.ect = true,
-		.UserBd = BOARD_TYPE_MOBILE,
+		.UserBd = BOARD_TYPE_ULT_ULX,
 		.ddr_config = {
 			.dq_pins_interleaved = false,
 		},

From 1ac3bee7d67aa28a20aa59cfbd3cd0298e6669a7 Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Fri, 7 Feb 2025 09:38:19 +0000
Subject: [PATCH 0033/3886] ec/starlabs/merlin: Only include virtual button
 driver for detachables

Including the Virtual Button Driver made laptops report as a detachable
in tablet mode. Adjust how it's included, so they report as laptops.

Change-Id: Idc2076c400524744836e2f52124ccb8502622b04
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86315
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/ec/starlabs/merlin/acpi/dock.asl | 2 --
 src/ec/starlabs/merlin/acpi/ec.asl   | 2 ++
 src/ec/starlabs/merlin/acpi/hid.asl  | 4 ++++
 3 files changed, 6 insertions(+), 2 deletions(-)

diff --git a/src/ec/starlabs/merlin/acpi/dock.asl b/src/ec/starlabs/merlin/acpi/dock.asl
index 8d648bc8b9..dd234f160b 100644
--- a/src/ec/starlabs/merlin/acpi/dock.asl
+++ b/src/ec/starlabs/merlin/acpi/dock.asl
@@ -31,12 +31,10 @@ Device (VBTN)
 
 	Method (VGBS, 0)
 	{
-#if CONFIG(SYSTEM_TYPE_DETACHABLE)
 		If (!GRXS (GPP_F15))
 		{
 			Return (0x40)
 		}
-#endif
 		Return (0x00)
 	}
 }
diff --git a/src/ec/starlabs/merlin/acpi/ec.asl b/src/ec/starlabs/merlin/acpi/ec.asl
index 35604840cb..f3fdb07334 100644
--- a/src/ec/starlabs/merlin/acpi/ec.asl
+++ b/src/ec/starlabs/merlin/acpi/ec.asl
@@ -117,7 +117,9 @@ Scope (\_SB.PCI0.LPCB)
 		#include "events.asl"
 #endif
 		#include "lid.asl"
+#if CONFIG(SYSTEM_TYPE_DETACHABLE)
 		#include "dock.asl"
+#endif
 
 		Method (_REG, 2, NotSerialized)
 		{
diff --git a/src/ec/starlabs/merlin/acpi/hid.asl b/src/ec/starlabs/merlin/acpi/hid.asl
index f3bfff611e..a63723916e 100644
--- a/src/ec/starlabs/merlin/acpi/hid.asl
+++ b/src/ec/starlabs/merlin/acpi/hid.asl
@@ -366,7 +366,11 @@ Device (HIDD)							// HID Device
 					//
 					Case (0x08)
 					{
+#if CONFIG(SYSTEM_TYPE_DETACHABLE)
 						Return (\_SB.PCI0.LPCB.EC.VBTN.VGBS())
+#else
+						Return (0x00)
+#endif
 					}
 					//
 					// Function 9 H2BC. Button implemented state.

From d958b270a25cff3d9dabf2721646198e72219ccf Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Thu, 6 Feb 2025 21:04:09 -0600
Subject: [PATCH 0034/3886] mb/starlabs/starbook_mtl: Fix USB port
 assignments/descriptions

Fix USB port assignments/descriptions to match actual topology.

TEST=build/boot Win11 on starlabs/starbook_mtl. Verify ports
match assignmented in devicetree using USBTreeview.

Change-Id: Ifb5ac4cf95c8f10706404479dea48ba20a90e286
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86320
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
---
 .../starbook/variants/mtl/devicetree.cb       | 44 +++++++++----------
 1 file changed, 22 insertions(+), 22 deletions(-)

diff --git a/src/mainboard/starlabs/starbook/variants/mtl/devicetree.cb b/src/mainboard/starlabs/starbook/variants/mtl/devicetree.cb
index a1384388a1..d9d8deea38 100644
--- a/src/mainboard/starlabs/starbook/variants/mtl/devicetree.cb
+++ b/src/mainboard/starlabs/starbook/variants/mtl/devicetree.cb
@@ -33,33 +33,33 @@ chip soc/intel/meteorlake
 		device ref tcss_xhci	on
 			chip drivers/usb/acpi
 				device ref tcss_root_hub on
-					chip drivers/usb/acpi
-						register "desc"		= ""Front USB Type-C""
-						register "type"		= "UPC_TYPE_C_USB2_SS_SWITCH"
-						register "group"	= "ACPI_PLD_GROUP(0, 0)"
-						device ref tcss_usb3_port1 on end
-					end
 					chip drivers/usb/acpi
 						register "desc"		= ""Back USB Type-C""
 						register "type"		= "UPC_TYPE_C_USB2_SS_SWITCH"
+						register "group"	= "ACPI_PLD_GROUP(0, 0)"
+						device ref tcss_usb3_port0 on end
+					end
+					chip drivers/usb/acpi
+						register "desc"		= ""Front USB Type-C""
+						register "type"		= "UPC_TYPE_C_USB2_SS_SWITCH"
 						register "group"	= "ACPI_PLD_GROUP(0, 1)"
-						device ref tcss_usb3_port2 on end
+						device ref tcss_usb3_port1 on end
 					end
 				end
 			end
 		end
 		device ref gna		on  end
 		device ref xhci		on
-			# Motherboard USB 3.0 Type-C Front	9557 mil
+			# Motherboard USB 3.0 Type-C Back	7893 mil
 			register "usb2_ports[0]"		= "USB2_PORT_TYPE_C(OC_SKIP)"
 			register "tcss_ports[0]"		= "TCSS_PORT_DEFAULT(OC_SKIP)"
 
-			# Motherboard USB 3.0 Type-C Back	7893 mil
-			register "usb2_ports[1]"		= "USB2_PORT_TYPE_C(OC_SKIP)"
+			# Motherboard USB 3.0 Type-C Front	9557 mil
+			register "usb2_ports[2]"		= "USB2_PORT_TYPE_C(OC_SKIP)"
 			register "tcss_ports[1]"		= "TCSS_PORT_DEFAULT(OC_SKIP)"
 
 			# Motherboard USB 3.0 Type-A		8916 mil
-			register "usb2_ports[2]"		= "USB2_PORT_MID(OC_SKIP)"
+			register "usb2_ports[1]"		= "USB2_PORT_MID(OC_SKIP)"
 			register "usb3_ports[0]"		= "USB3_PORT_DEFAULT(OC_SKIP)"
 
 			# Daughterboard USB 3.0 Type-A		2229 mil
@@ -78,22 +78,22 @@ chip soc/intel/meteorlake
 			chip drivers/usb/acpi
 				device ref xhci_root_hub on
 					chip drivers/usb/acpi
-						register "desc"		= ""Front USB Type-C""
+						register "desc"		= ""Back USB Type-C""
 						register "type"		= "UPC_TYPE_C_USB2_SS_SWITCH"
 						register "group"	= "ACPI_PLD_GROUP(0, 0)"
 						device ref usb2_port1 on end
 					end
 					chip drivers/usb/acpi
-						register "desc"		= ""Back USB Type-C""
+						register "desc"		= ""Front USB Type-C""
 						register "type"		= "UPC_TYPE_C_USB2_SS_SWITCH"
 						register "group"	= "ACPI_PLD_GROUP(0, 1)"
-						device ref usb2_port2 on end
+						device ref usb2_port3 on end
 					end
 					chip drivers/usb/acpi
 						register "desc"		= ""Left USB Type-A""
 						register "type"		= "UPC_TYPE_USB3_A"
 						register "group"	= "ACPI_PLD_GROUP(0, 2)"
-						device ref usb2_port3 on end
+						device ref usb2_port2 on end
 					end
 					chip drivers/usb/acpi
 						register "desc"		= ""Left USB Type-A""
@@ -102,13 +102,13 @@ chip soc/intel/meteorlake
 						device ref usb3_port1 on end
 					end
 					chip drivers/usb/acpi
-						register "desc"		= ""Right USB Type-A""
+						register "desc"		= ""Right Rear USB Type-A""
 						register "type"		= "UPC_TYPE_USB3_A"
 						register "group"	= "ACPI_PLD_GROUP(0, 3)"
 						device ref usb2_port7 on end
 					end
 					chip drivers/usb/acpi
-						register "desc"		= ""Right USB Type-A""
+						register "desc"		= ""Right Rear USB Type-A""
 						register "type"		= "UPC_TYPE_USB3_A"
 						register "group"	= "ACPI_PLD_GROUP(0, 3)"
 						device ref usb3_port2 on end
@@ -120,8 +120,8 @@ chip soc/intel/meteorlake
 						device ref usb2_port5 on end
 					end
 					chip drivers/usb/acpi
-						register "desc"		= ""MicroSD Card Reader""
-						register "type"		= "UPC_TYPE_INTERNAL"
+						register "desc"		= ""USB 2.0 Hub""
+						register "type"		= "UPC_TYPE_HUB"
 						register "group"	= "ACPI_PLD_GROUP(0, 5)"
 						device ref usb2_port8 on end
 					end
@@ -236,12 +236,12 @@ chip soc/intel/meteorlake
 				device generic 0 on
 					chip drivers/intel/pmc_mux/conn
 						use usb2_port1 as usb2_port
-						use tcss_usb3_port1 as usb3_port
+						use tcss_usb3_port0 as usb3_port
 						device generic 0 alias conn0 on end
 					end
 					chip drivers/intel/pmc_mux/conn
-						use usb2_port2 as usb2_port
-						use tcss_usb3_port2 as usb3_port
+						use usb2_port3 as usb2_port
+						use tcss_usb3_port1 as usb3_port
 						device generic 1 alias conn1 on end
 					end
 				end

From 04ccbbc4640ad59ab17ca7494ebf3ea042a8ff0e Mon Sep 17 00:00:00 2001
From: Yidi Lin <yidilin@chromium.org>
Date: Sat, 8 Feb 2025 12:17:59 +0800
Subject: [PATCH 0035/3886] soc/mediatek/common: Measure mtk_fsp_load_and_run()
 execution time

Measure mtk_fsp_load_and_run() execution time. This info helps AP boot
time analysis. The logs show as below.

[INFO ]  mtk_fsp_load_and_run: run fallback/mtk_fsp_romstage at phase 0x30 in 0 msecs
[INFO ]  mtk_fsp_load_and_run: run fallback/mtk_fsp_ramstage at phase 0x50 in 41 msecs

BUG=none
BRANCH=rauru
TEST=cbmem -1|grep "mtk_fsp_load_and_run"

Change-Id: I61706952bef4590c5bfd09707a08a4f1a25fbda2
Signed-off-by: Yidi Lin <yidilin@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86325
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
---
 src/soc/mediatek/common/mtk_fsp.c | 7 +++++--
 1 file changed, 5 insertions(+), 2 deletions(-)

diff --git a/src/soc/mediatek/common/mtk_fsp.c b/src/soc/mediatek/common/mtk_fsp.c
index bc1b5d5f08..073a0798cc 100644
--- a/src/soc/mediatek/common/mtk_fsp.c
+++ b/src/soc/mediatek/common/mtk_fsp.c
@@ -3,6 +3,7 @@
 #include <cbfs.h>
 #include <console/console.h>
 #include <soc/mtk_fsp.h>
+#include <timer.h>
 
 #define MAX_PARAM_ENTRIES 32
 #define FSP_INTF_SIZE (sizeof(struct mtk_fsp_intf) + \
@@ -82,7 +83,9 @@ static const char *mtk_fsp_file(void)
 enum cb_err mtk_fsp_load_and_run(void)
 {
 	struct prog fsp = PROG_INIT(PROG_REFCODE, mtk_fsp_file());
+	struct stopwatch sw;
 
+	stopwatch_init(&sw);
 	if (cbfs_prog_stage_load(&fsp)) {
 		printk(BIOS_ERR, "%s: CBFS load program failed\n", __func__);
 		return CB_ERR;
@@ -101,8 +104,8 @@ enum cb_err mtk_fsp_load_and_run(void)
 		return CB_ERR;
 	}
 
-	printk(BIOS_INFO, "%s: run %s at phase %#x done\n",
-	       __func__, mtk_fsp_file(), intf->phase);
+	printk(BIOS_INFO, "%s: run %s at phase %#x in %lld msecs\n",
+	       __func__, mtk_fsp_file(), intf->phase, stopwatch_duration_msecs(&sw));
 
 	return CB_SUCCESS;
 }

From cd414d9d619d7cca9d456c542fa61513444fcad8 Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Thu, 6 Feb 2025 21:00:10 -0600
Subject: [PATCH 0036/3886] soc/intel/meteorlake: Add missing USB port
 definitions

The TCSS_XHCI controller has a single USB2 port followed by 4 USB3
ports; the XHCI controller has 12 USB2 ports followed by 2 USB3
ports. The topology was queried from the root hub on each controller
and returned via the descriptor.

Add the 2 missing USB2 ports to the XHCI controller and the one to
the TSS_XHCI controller.

TEST=build/boot Win11, Linux 6.x on starlabs/starbook_mtl.

Change-Id: I5dc97f150ff064d55e7969f10c1cea8ba72d6bfb
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86319
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
---
 src/soc/intel/meteorlake/chipset.cb | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/src/soc/intel/meteorlake/chipset.cb b/src/soc/intel/meteorlake/chipset.cb
index 9087dd8adb..7b26670ff8 100644
--- a/src/soc/intel/meteorlake/chipset.cb
+++ b/src/soc/intel/meteorlake/chipset.cb
@@ -69,6 +69,9 @@ chip soc/intel/meteorlake
 			chip drivers/usb/acpi
 				register "type" = "UPC_TYPE_HUB"
 				device usb 0.0 alias tcss_root_hub off
+					chip drivers/usb/acpi
+						device usb 2.0 alias tcss_usb2_port1 off end
+					end
 					chip drivers/usb/acpi
 						device usb 3.0 alias tcss_usb3_port0 off end
 					end
@@ -131,6 +134,12 @@ chip soc/intel/meteorlake
 					chip drivers/usb/acpi
 						device usb 2.9 alias usb2_port10 off end
 					end
+					chip drivers/usb/acpi
+						device usb 2.a alias usb2_port11 off end
+					end
+					chip drivers/usb/acpi
+						device usb 2.b alias usb2_port12 off end
+					end
 					chip drivers/usb/acpi
 						device usb 3.0 alias usb3_port1 off end
 					end

From 6d0e35b68d872171175caef5f1272408407c8c46 Mon Sep 17 00:00:00 2001
From: Alicja Michalska <alicja.michalska@9elements.com>
Date: Wed, 22 Jan 2025 01:13:14 +0100
Subject: [PATCH 0037/3886] mb/erying/tgl: Drop specifying which timers to use

With 8254 timer enabled, system would hang while entering s0ix state.
If we build coreboot with both timers =N, system enters s0ix state
(although it doesn't cut the power to the platform) and can be woken
up by pressing the key on the keyboard.

Since there's less potential for data loss in case of accidental
suspend, I think it makes sense to do it this way.

Change-Id: If6e0ac1d289447c292a49111251d321c951078e2
Signed-off-by: Alicja Michalska <alicja.michalska@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86093
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/erying/tgl/Kconfig | 6 ------
 1 file changed, 6 deletions(-)

diff --git a/src/mainboard/erying/tgl/Kconfig b/src/mainboard/erying/tgl/Kconfig
index 01e5dd98aa..e8a2a1fd72 100644
--- a/src/mainboard/erying/tgl/Kconfig
+++ b/src/mainboard/erying/tgl/Kconfig
@@ -30,12 +30,6 @@ config MAINBOARD_PART_NUMBER
 config CBFS_SIZE
 	default 0xA00000
 
-config USE_PM_ACPI_TIMER
-	default n
-
-config USE_LEGACY_8254_TIMER
-	default y
-
 config PCIEXP_ASPM
 	default n
 

From 17c94b65c8dfe99d1f3bbd6eccd917cd8bc50002 Mon Sep 17 00:00:00 2001
From: Hualin Wei <weihualin@huaqin.corp-partner.google.com>
Date: Sat, 8 Feb 2025 09:41:17 +0800
Subject: [PATCH 0038/3886] mb/google/nissa/var/pujjoniru: Tune I2C_5
 parameters

1. Modify the I2C frequency of the touchpad to below 400 KHz to
meet the spec.
2. Modify the Thd dat of DATA between 0.3 us and 0.9 us to meet
the spec.

Before:
I2C5 - 407KHz
Thd  - 0.06us

After:
I2C5 - 387Khz
Thd  - 0.34us

BUG=b:391796230,b:391788680
TEST=Check that the wave form meets the spec.

Change-Id: I3c8c8d3b78236247ca7be810ac152085f615a6ef
Signed-off-by: Hualin Wei <weihualin@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86324
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Qinghong Zeng <zengqinghong@huaqin.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
---
 .../google/brya/variants/pujjoniru/overridetree.cb          | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/src/mainboard/google/brya/variants/pujjoniru/overridetree.cb b/src/mainboard/google/brya/variants/pujjoniru/overridetree.cb
index 02ab63358e..11098ac4ed 100644
--- a/src/mainboard/google/brya/variants/pujjoniru/overridetree.cb
+++ b/src/mainboard/google/brya/variants/pujjoniru/overridetree.cb
@@ -82,9 +82,9 @@ chip soc/intel/alderlake
 			.speed = I2C_SPEED_FAST,
 			.speed_config[0] = {
 				.speed = I2C_SPEED_FAST,
-				.scl_lcnt = 152,
-				.scl_hcnt = 79,
-				.sda_hold = 7,
+				.scl_lcnt = 150,
+				.scl_hcnt = 85,
+				.sda_hold = 35,
 			}
 		},
 	}"

From 976a28bcfa81868faaf6d51145f24aecb7a5cc3c Mon Sep 17 00:00:00 2001
From: Jayvik Desai <jayvik@google.com>
Date: Fri, 7 Feb 2025 14:52:48 +0530
Subject: [PATCH 0039/3886] soc/intel/ptl: Disable FSP_UGOP_EARLY_SIGN_OF_LIFE
 for pantherlake

This patch disables eSOL Kconfig until the feature is ready in PTL
FSP-uGOP binary.

TEST=Able to build and boot google/fatcat to OS.

Change-Id: I99dd516816995b6cdfdcec618c06c7dbe061718a
Signed-off-by: Jayvik Desai <jayvik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86314
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/soc/intel/pantherlake/Kconfig | 1 -
 1 file changed, 1 deletion(-)

diff --git a/src/soc/intel/pantherlake/Kconfig b/src/soc/intel/pantherlake/Kconfig
index dde401bfb5..53260208bf 100644
--- a/src/soc/intel/pantherlake/Kconfig
+++ b/src/soc/intel/pantherlake/Kconfig
@@ -17,7 +17,6 @@ config SOC_INTEL_PANTHERLAKE_BASE
 	select FAST_SPI_SUPPORTS_EXT_BIOS_WINDOW
 	select FSP_COMPRESS_FSP_S_LZ4
 	select FSP_M_XIP
-	select FSP_UGOP_EARLY_SIGN_OF_LIFE
 	select FSP_USES_CB_DEBUG_EVENT_HANDLER
 	select FSPS_HAS_ARCH_UPD
 	select GENERIC_GPIO_LIB

From d25a73d9a7ce25ec9b7a7652385c6b11033a3e8f Mon Sep 17 00:00:00 2001
From: Subrata Banik <subratabanik@google.com>
Date: Thu, 30 Jan 2025 09:20:53 +0000
Subject: [PATCH 0040/3886] util/cbfstool/eventlog: Add low battery event type

This commit adds a new event type, `ELOG_TYPE_LOW_BATTERY_INDICATOR`,
to the event log. This event is logged when the system boots due to
a low battery condition.  It includes the reason for the shutdown,
currently only supporting "Power Off".

BUG=b:339673254
TEST=Able to capture the eventlog for low battery boot event.

```
> elogtool list
9 | 2025-02-03 09:44:19+0530 | Low Battery Boot  | Power Off
```

Change-Id: I5cc5e5f540657c7dfd174a4928e697a272da813a
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86223
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
---
 src/commonlib/bsd/include/commonlib/bsd/elog.h |  3 +++
 util/cbfstool/eventlog.c                       | 12 ++++++++++++
 2 files changed, 15 insertions(+)

diff --git a/src/commonlib/bsd/include/commonlib/bsd/elog.h b/src/commonlib/bsd/include/commonlib/bsd/elog.h
index f7dc4a1ac0..01f97f6957 100644
--- a/src/commonlib/bsd/include/commonlib/bsd/elog.h
+++ b/src/commonlib/bsd/include/commonlib/bsd/elog.h
@@ -389,6 +389,9 @@ struct elog_event_extended_event {
 #define  ELOG_FW_POST_RAM_CSE_SYNC         0x1
 #define  ELOG_FW_CSE_SYNC_AT_PAYLOAD       0x2
 
+#define ELOG_TYPE_LOW_BATTERY_INDICATOR   0xbe
+#define  ELOG_FW_ISSUE_SHUTDOWN            0x0
+
 /* Only the 7-LSB are used for size */
 #define ELOG_MAX_EVENT_SIZE                    0x7F
 
diff --git a/util/cbfstool/eventlog.c b/util/cbfstool/eventlog.c
index 4746670513..2312b75f8b 100644
--- a/util/cbfstool/eventlog.c
+++ b/util/cbfstool/eventlog.c
@@ -170,6 +170,7 @@ static void eventlog_print_type(const struct event_header *event)
 		{ELOG_TYPE_PSR_DATA_LOST, "PSR data lost"},
 		{ELOG_TYPE_FW_SPLASH_SCREEN, "Firmware Splash Screen"},
 		{ELOG_TYPE_FW_CSE_SYNC, "Firmware CSE sync"},
+		{ELOG_TYPE_LOW_BATTERY_INDICATOR, "Low Battery boot"},
 		{ELOG_TYPE_EOL, "End of log"},
 	};
 
@@ -491,6 +492,11 @@ static int eventlog_print_data(const struct event_header *event)
 		{0, NULL},
 	};
 
+	static const struct valstr low_battery_status[] = {
+		{ELOG_FW_ISSUE_SHUTDOWN, "Power Off"},
+		{0, NULL},
+	};
+
 	size_t elog_type_to_min_size[] = {
 		[ELOG_TYPE_LOG_CLEAR]		= sizeof(uint16_t),
 		[ELOG_TYPE_BOOT]		= sizeof(uint32_t),
@@ -513,6 +519,7 @@ static int eventlog_print_data(const struct event_header *event)
 		[ELOG_TYPE_PSR_DATA_BACKUP]	= sizeof(uint8_t),
 		[ELOG_TYPE_FW_SPLASH_SCREEN]	= sizeof(uint8_t),
 		[ELOG_TYPE_FW_CSE_SYNC]		= sizeof(uint8_t),
+		[ELOG_TYPE_LOW_BATTERY_INDICATOR]	= sizeof(uint8_t),
 		[0xff]				= 0,
 	};
 
@@ -684,6 +691,11 @@ static int eventlog_print_data(const struct event_header *event)
 		eventlog_printf("%s", val2str(*cse_event, cse_sync_path_types));
 		break;
 	}
+	case ELOG_TYPE_LOW_BATTERY_INDICATOR: {
+		const uint8_t *low_battery_event = event_get_data(event);
+		eventlog_printf("%s", val2str(*low_battery_event, low_battery_status));
+		break;
+	}
 	default:
 		break;
 	}

From 597dba2e344a317d8a335c00a98f3229d803c2b7 Mon Sep 17 00:00:00 2001
From: Paul Menzel <pmenzel@molgen.mpg.de>
Date: Sun, 9 Feb 2025 07:51:57 +0100
Subject: [PATCH 0041/3886] drivers/asmedia/asm1061: Align = only with tabs and
 not spaces

The `.devices` line only had once space before the =, as the tab
boundary is directly after the s of devices. The lines above had once
space after the last tab, so the equal sign is closer to the left side.
As the whole file aligns the equal sign, replace the space by a tab, and
do *not* go the route of not aligning the equal signs.

Change-Id: Ic49dc56263cafce3cfe40bb3ed7036fa25300f9f
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86335
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
---
 src/drivers/asmedia/asm1061.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/src/drivers/asmedia/asm1061.c b/src/drivers/asmedia/asm1061.c
index 6d2edaa94e..29d2704f45 100644
--- a/src/drivers/asmedia/asm1061.c
+++ b/src/drivers/asmedia/asm1061.c
@@ -42,7 +42,7 @@ static const unsigned short pci_device_ids[] = {
 };
 
 static const struct pci_driver asmedia_asm1061 __pci_driver = {
-	.ops	 = &asm1061_ops,
-	.vendor	 = 0x1b21,
-	.devices = pci_device_ids,
+	.ops		= &asm1061_ops,
+	.vendor		= 0x1b21,
+	.devices	= pci_device_ids,
 };

From a810b2762db5c8c07cd2689560411ce2a7ad665f Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Sat, 8 Feb 2025 19:42:34 +0000
Subject: [PATCH 0042/3886] mb/starlabs/*: Use a safe configurations for DRAM
 Sleep GPIO

The configuration used was copied from other boards in the tree,
NF1/NF2. However, no Intel documents says that GPP_E8 has a native
function.

As it remains unclear if the other boards in the tree are
misconfiugured, or the documents are incorrect, revert to a safe
configuration for the GPIO.

Change-Id: I49b8faa7f8712ad0ead22b7ccbfa6deca6046368
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86332
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
---
 src/mainboard/starlabs/byte_adl/variants/mk_ii/gpio.c    | 2 +-
 src/mainboard/starlabs/starbook/variants/adl/gpio.c      | 2 +-
 src/mainboard/starlabs/starbook/variants/adl_n/gpio.c    | 2 +-
 src/mainboard/starlabs/starbook/variants/rpl/gpio.c      | 2 +-
 src/mainboard/starlabs/starfighter/variants/rpl/gpio.c   | 2 +-
 src/mainboard/starlabs/starlite_adl/variants/mk_v/gpio.c | 2 +-
 6 files changed, 6 insertions(+), 6 deletions(-)

diff --git a/src/mainboard/starlabs/byte_adl/variants/mk_ii/gpio.c b/src/mainboard/starlabs/byte_adl/variants/mk_ii/gpio.c
index f17e3ae5b8..8ec1666014 100644
--- a/src/mainboard/starlabs/byte_adl/variants/mk_ii/gpio.c
+++ b/src/mainboard/starlabs/byte_adl/variants/mk_ii/gpio.c
@@ -256,7 +256,7 @@ const struct pad_config gpio_table[] = {
 	/* E7:		Embedded Controller SMI				*/
 	PAD_NC(GPP_E7, NONE),
 	/* E8:		DRAM Sleep					*/
-	PAD_NC(GPP_E8, NONE),
+	PAD_CFG_GPO(GPP_E8, 1, DEEP),
 	/* E9:		USB OverCurrent 0				*/
 	PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1),
 	/* E10:		Not Connected					*/
diff --git a/src/mainboard/starlabs/starbook/variants/adl/gpio.c b/src/mainboard/starlabs/starbook/variants/adl/gpio.c
index fb3d64d593..2ab629f291 100644
--- a/src/mainboard/starlabs/starbook/variants/adl/gpio.c
+++ b/src/mainboard/starlabs/starbook/variants/adl/gpio.c
@@ -255,7 +255,7 @@ const struct pad_config gpio_table[] = {
 	/* E7:		Embedded Controller SMI				*/
 	PAD_NC(GPP_E7, NONE),
 	/* E8:		DRAM Sleep					*/
-	PAD_CFG_NF(GPP_E8, NONE, DEEP, NF1),
+	PAD_CFG_GPO(GPP_E8, 1, DEEP),
 	/* E9:		USB OverCurrent 0				*/
 	PAD_NC(GPP_E9, NONE),
 	/* E10:		PWD Amplifier Input				*/
diff --git a/src/mainboard/starlabs/starbook/variants/adl_n/gpio.c b/src/mainboard/starlabs/starbook/variants/adl_n/gpio.c
index b59ad9dcd0..835d8f6251 100644
--- a/src/mainboard/starlabs/starbook/variants/adl_n/gpio.c
+++ b/src/mainboard/starlabs/starbook/variants/adl_n/gpio.c
@@ -255,7 +255,7 @@ const struct pad_config gpio_table[] = {
 	/* E7:		Embedded Controller SMI				*/
 	PAD_NC(GPP_E7, NONE),
 	/* E8:		DRAM Sleep					*/
-	PAD_CFG_NF(GPP_E8, NONE, DEEP, NF2),
+	PAD_CFG_GPO(GPP_E8, 1, DEEP),
 	/* E9:		USB OverCurrent 0				*/
 	PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1),
 	/* E10:		PWD Amplifier Input				*/
diff --git a/src/mainboard/starlabs/starbook/variants/rpl/gpio.c b/src/mainboard/starlabs/starbook/variants/rpl/gpio.c
index e8c2550268..5e3cd0006a 100644
--- a/src/mainboard/starlabs/starbook/variants/rpl/gpio.c
+++ b/src/mainboard/starlabs/starbook/variants/rpl/gpio.c
@@ -255,7 +255,7 @@ const struct pad_config gpio_table[] = {
 	/* E7:		Embedded Controller SMI				*/
 	PAD_NC(GPP_E7, NONE),
 	/* E8:		DRAM Sleep					*/
-	PAD_CFG_NF(GPP_E8, NONE, DEEP, NF1),
+	PAD_CFG_GPO(GPP_E8, 1, DEEP),
 	/* E9:		USB OverCurrent 0				*/
 	PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1),
 	/* E10:		PWD Amplifier Input				*/
diff --git a/src/mainboard/starlabs/starfighter/variants/rpl/gpio.c b/src/mainboard/starlabs/starfighter/variants/rpl/gpio.c
index 18c5651fdb..a69b210a30 100644
--- a/src/mainboard/starlabs/starfighter/variants/rpl/gpio.c
+++ b/src/mainboard/starlabs/starfighter/variants/rpl/gpio.c
@@ -260,7 +260,7 @@ const struct pad_config gpio_table[] = {
 	/* E7:		Embedded Controller SMI				*/
 	PAD_NC(GPP_E7, NONE),
 	/* E8:		DRAM Sleep					*/
-	PAD_CFG_NF(GPP_E8, NONE, DEEP, NF1),
+	PAD_CFG_GPO(GPP_E8, 1, DEEP),
 	/* E9:		USB OverCurrent 0				*/
 	PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1),
 	/* E10:		Not Connected					*/
diff --git a/src/mainboard/starlabs/starlite_adl/variants/mk_v/gpio.c b/src/mainboard/starlabs/starlite_adl/variants/mk_v/gpio.c
index 4ca0ca5948..edde160dec 100644
--- a/src/mainboard/starlabs/starlite_adl/variants/mk_v/gpio.c
+++ b/src/mainboard/starlabs/starlite_adl/variants/mk_v/gpio.c
@@ -254,7 +254,7 @@ const struct pad_config gpio_table[] = {
 	/* E7:		Embedded Controller SMI				*/
 	PAD_NC(GPP_E7, NONE),
 	/* E8:		DRAM Sleep					*/
-	PAD_CFG_NF(GPP_E8, NONE, DEEP, NF2),
+	PAD_CFG_GPO(GPP_E8, 1, DEEP),
 	/* E9:		USB OverCurrent 0				*/
 	PAD_NC(GPP_E9, NONE),
 	/* E10:		PWD Amplifier Input				*/

From 39fc3587dddc47770a1f93b614b6d7b881a5532b Mon Sep 17 00:00:00 2001
From: Subrata Banik <subratabanik@google.com>
Date: Mon, 10 Feb 2025 09:55:09 +0530
Subject: [PATCH 0043/3886] mb/google/fatcat: Add power limits for additional
 PTL-H variants

This commit adds power limit configurations for additional variants of
the Intel PTL-H platform found on Fatcat. Specifically, it adds entries
for PCI Device IDs 2, 3, and 4. These configurations define the PL1,
PL2, and PL4 power limits, as well as the associated CPU TDP and
power limits index.  The PL4 values are currently placeholders and
marked for future fine-tuning.

BUG=b:395130929
TEST=Able to boot google/fatcat with 65W USB-C PD charger.

Change-Id: I86befb07f39a5e292365ea40ea08d0f93f38a7a6
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86339
Reviewed-by: Jayvik Desai <jayvik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
---
 .../variants/baseboard/fatcat/ramstage.c      | 30 +++++++++++++++++++
 1 file changed, 30 insertions(+)

diff --git a/src/mainboard/google/fatcat/variants/baseboard/fatcat/ramstage.c b/src/mainboard/google/fatcat/variants/baseboard/fatcat/ramstage.c
index 4b9cfd2747..969cd4a7c0 100644
--- a/src/mainboard/google/fatcat/variants/baseboard/fatcat/ramstage.c
+++ b/src/mainboard/google/fatcat/variants/baseboard/fatcat/ramstage.c
@@ -18,6 +18,36 @@ const struct cpu_tdp_power_limits power_optimized_limits[] = {
 		.pl2_max_power = 50000,
 		.pl4_power = 50000 /* TODO: needs fine tuning */
 	},
+	{
+		.mch_id = PCI_DID_INTEL_PTL_H_ID_2,
+		.cpu_tdp = 25,
+		.power_limits_index = PTL_H_1_CORE,
+		.pl1_min_power = 10000,
+		.pl1_max_power = 25000,
+		.pl2_min_power = 50000,
+		.pl2_max_power = 50000,
+		.pl4_power = 50000 /* TODO: needs fine tuning */
+	},
+	{
+		.mch_id = PCI_DID_INTEL_PTL_H_ID_3,
+		.cpu_tdp = 25,
+		.power_limits_index = PTL_H_2_CORE,
+		.pl1_min_power = 10000,
+		.pl1_max_power = 25000,
+		.pl2_min_power = 50000,
+		.pl2_max_power = 50000,
+		.pl4_power = 50000 /* TODO: needs fine tuning */
+	},
+	{
+		.mch_id = PCI_DID_INTEL_PTL_H_ID_4,
+		.cpu_tdp = 25,
+		.power_limits_index = PTL_H_2_CORE,
+		.pl1_min_power = 10000,
+		.pl1_max_power = 25000,
+		.pl2_min_power = 50000,
+		.pl2_max_power = 50000,
+		.pl4_power = 50000 /* TODO: needs fine tuning */
+	},
 };
 
 void baseboard_devtree_update(void)

From b994bbdd28923a12bd7ea2e3a83e37534a779b87 Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Mon, 10 Feb 2025 16:22:31 +0000
Subject: [PATCH 0044/3886] mb/starlabs/starbook/adl_n: Disconnect unused GPIOs

These are not connected, so configure them as such.

Change-Id: I5dfeb5c1503ca85baf3641f1f5803519ec517b81
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86347
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
---
 src/mainboard/starlabs/starbook/variants/adl_n/gpio.c | 10 +++++-----
 1 file changed, 5 insertions(+), 5 deletions(-)

diff --git a/src/mainboard/starlabs/starbook/variants/adl_n/gpio.c b/src/mainboard/starlabs/starbook/variants/adl_n/gpio.c
index 835d8f6251..e61c9a0d2e 100644
--- a/src/mainboard/starlabs/starbook/variants/adl_n/gpio.c
+++ b/src/mainboard/starlabs/starbook/variants/adl_n/gpio.c
@@ -37,7 +37,7 @@ const struct pad_config gpio_table[] = {
 	/* GPD8:	Suspend Clock					*/
 	PAD_CFG_NF(GPD8, NONE, DEEP, NF1),
 	/* GPD9:	Wireless LAN Sleep				*/
-	PAD_CFG_NF(GPD9, NONE, DEEP, NF1),
+	PAD_NC(GPD9, NONE),
 	/* GPD10:	Sleep S5					*/
 	PAD_NC(GPD10, NONE),
 	/* GPD11:	LAN PHY Enable					*/
@@ -60,8 +60,8 @@ const struct pad_config gpio_table[] = {
 	/* A10:		ESPI Reset					*/
 	/* A11:		Not Connected					*/
 	PAD_NC(GPP_A11, NONE),
-	/* A12:		PCH M.2 SSD PEDET				*/
-	PAD_CFG_NF(GPP_A12, NONE, DEEP, NF1),
+	/* A12:		Not Connected					*/
+	PAD_NC(GPP_A12, NONE),
 	/* A13:		BlueTooth RF Kill				*/
 	PAD_CFG_GPO_GPIO_DRIVER(GPP_A13, 1, DEEP, NONE),
 	/* A14:		Test Point 45					*/
@@ -69,7 +69,7 @@ const struct pad_config gpio_table[] = {
 	/* A15:		Test Point 52					*/
 	PAD_NC(GPP_A15, NONE),
 	/* A16:		USB OverCurrent 3				*/
-	PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1),
+	PAD_NC(GPP_A16, NONE),
 	/* A17:		Not Connected					*/
 	PAD_NC(GPP_A17, NONE),
 	/* A18:		DDI B DP HPD					*/
@@ -257,7 +257,7 @@ const struct pad_config gpio_table[] = {
 	/* E8:		DRAM Sleep					*/
 	PAD_CFG_GPO(GPP_E8, 1, DEEP),
 	/* E9:		USB OverCurrent 0				*/
-	PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1),
+	PAD_NC(GPP_E9, NONE),
 	/* E10:		PWD Amplifier Input				*/
 	PAD_NC(GPP_E10, NONE),
 	/* E11:		TPM IRQ						*/

From 7d7802088a96690372f54d449ce90f9aaf9b107f Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Mon, 10 Feb 2025 14:35:37 +0000
Subject: [PATCH 0045/3886] mb/starlabs/*: Correct PAD ownership

Commit `57aca97a2c6e524b442c80d67b033a813bf10e8e` correctly changed the
reset types of GPIOs used in ACPI, but incorrectly set the pads to GPIO
mode, rather than ACPI mode.

This patch corrects that.

Change-Id: I7207d4d00e810c15d071eca0bea83796989e3735
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86344
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
---
 .../starlabs/byte_adl/variants/mk_ii/gpio.c          | 10 +++++-----
 src/mainboard/starlabs/starbook/variants/adl/gpio.c  | 10 +++++-----
 .../starlabs/starbook/variants/adl_n/gpio.c          | 10 +++++-----
 src/mainboard/starlabs/starbook/variants/cml/gpio.c  |  4 ++--
 src/mainboard/starlabs/starbook/variants/mtl/gpio.c  | 10 +++++-----
 src/mainboard/starlabs/starbook/variants/rpl/gpio.c  | 10 +++++-----
 src/mainboard/starlabs/starbook/variants/tgl/gpio.c  |  6 +++---
 .../starlabs/starfighter/variants/rpl/gpio.c         | 12 ++++++------
 .../starlabs/starlite_adl/variants/mk_v/gpio.c       | 12 ++++++------
 9 files changed, 42 insertions(+), 42 deletions(-)

diff --git a/src/mainboard/starlabs/byte_adl/variants/mk_ii/gpio.c b/src/mainboard/starlabs/byte_adl/variants/mk_ii/gpio.c
index 8ec1666014..6981b85fc0 100644
--- a/src/mainboard/starlabs/byte_adl/variants/mk_ii/gpio.c
+++ b/src/mainboard/starlabs/byte_adl/variants/mk_ii/gpio.c
@@ -63,7 +63,7 @@ const struct pad_config gpio_table[] = {
 	/* A12:		PCH M.2 SSD PEDET				*/
 	PAD_CFG_NF(GPP_A12, NONE, DEEP, NF1),
 	/* A13:		BlueTooth RF Kill				*/
-	PAD_CFG_GPO_GPIO_DRIVER(GPP_A13, 1, DEEP, NONE),
+	PAD_CFG_GPO(GPP_A13, 1, DEEP),
 	/* A14:		Type C VBUS OverCurrent				*/
 	PAD_CFG_NF(GPP_A14, NONE, DEEP, NF1),
 	/* A15:		Test Point 3					*/
@@ -229,7 +229,7 @@ const struct pad_config gpio_table[] = {
 	/* D15:		Not Connected					*/
 	PAD_NC(GPP_D15, NONE),
 	/* D16:		PCH M.2 SSD Power Enable			*/
-	PAD_CFG_GPO_GPIO_DRIVER(GPP_D16, 1, DEEP, NONE),
+	PAD_CFG_GPO(GPP_D16, 1, DEEP),
 	/* D17:		Not Connected					*/
 	PAD_NC(GPP_D17, NONE),
 	/* D18:		Not Connected					*/
@@ -244,7 +244,7 @@ const struct pad_config gpio_table[] = {
 	/* E2:		Not Connected					*/
 	PAD_NC(GPP_E2, NONE),
 	/* E3:		WiFi RF Kill					*/
-	PAD_CFG_GPO_GPIO_DRIVER(GPP_E3, 1, DEEP, NONE),
+	PAD_CFG_GPO(GPP_E3, 1, DEEP),
 	/* E4:		Test Point 7					*/
 	PAD_NC(GPP_E4, NONE),
 	/* E5:		Not Connected					*/
@@ -340,7 +340,7 @@ const struct pad_config gpio_table[] = {
 	PAD_NC(GPP_F23, NONE),
 
 	/* H0:		PCH M.2 SSD Reset				*/
-	PAD_CFG_GPO_GPIO_DRIVER(GPP_H0, 1, PLTRST, NONE),
+	PAD_CFG_GPO(GPP_H0, 1, PLTRST),
 	/* H1:		BFX Strap 2 Bit 3	Weak Internal PD 20K	*/
 	PAD_CFG_GPO(GPP_H1, 0, DEEP),
 	/* H2:		Wireless LAN Reset				*/
@@ -452,7 +452,7 @@ const struct pad_config gpio_table[] = {
 	PAD_NC(GPP_R7, NONE),
 
 	/* BT_EN */
-	PAD_CFG_GPO_GPIO_DRIVER(GPP_VGPIO_0, 1, DEEP, NONE),
+	PAD_CFG_GPO(GPP_VGPIO_0, 1, DEEP),
 
 	/* CNVi BT UART0 */
 	PAD_NC(GPP_VGPIO_6, NONE),
diff --git a/src/mainboard/starlabs/starbook/variants/adl/gpio.c b/src/mainboard/starlabs/starbook/variants/adl/gpio.c
index 2ab629f291..4cc9888040 100644
--- a/src/mainboard/starlabs/starbook/variants/adl/gpio.c
+++ b/src/mainboard/starlabs/starbook/variants/adl/gpio.c
@@ -63,7 +63,7 @@ const struct pad_config gpio_table[] = {
 	/* A12:		PCH M.2 SSD PEDET				*/
 	PAD_CFG_NF(GPP_A12, NONE, DEEP, NF1),
 	/* A13:		BlueTooth RF Kill				*/
-	PAD_CFG_GPO_GPIO_DRIVER(GPP_A13, 1, DEEP, NONE),
+	PAD_CFG_GPO(GPP_A13, 1, DEEP),
 	/* A14:		Test Point 45					*/
 	PAD_NC(GPP_A14, NONE),
 	/* A15:		Test Point 52					*/
@@ -228,7 +228,7 @@ const struct pad_config gpio_table[] = {
 	/* D15:		Not Connected					*/
 	PAD_NC(GPP_D15, NONE),
 	/* D16:		PCH M.2 SSD Power Enable			*/
-	PAD_CFG_GPO_GPIO_DRIVER(GPP_D16, 1, DEEP, NONE),
+	PAD_CFG_GPO(GPP_D16, 1, DEEP),
 	/* D17:		Not used		Fingerprint ID		*/
 	PAD_NC(GPP_D17, NONE),
 	/* D18:		Not Connected					*/
@@ -243,7 +243,7 @@ const struct pad_config gpio_table[] = {
 	/* E2:		Not Connected					*/
 	PAD_NC(GPP_E2, NONE),
 	/* E3:		WiFi RF Kill					*/
-	PAD_CFG_GPO_GPIO_DRIVER(GPP_E3, 1, DEEP, NONE),
+	PAD_CFG_GPO(GPP_E3, 1, DEEP),
 	/* E4:		Test Point 14					*/
 	PAD_NC(GPP_E4, NONE),
 	/* E5:		Not Connected					*/
@@ -339,11 +339,11 @@ const struct pad_config gpio_table[] = {
 	PAD_NC(GPP_F23, NONE),
 
 	/* H0:		PCH M.2 SSD Reset				*/
-	PAD_CFG_GPO_GPIO_DRIVER(GPP_H0, 1, PLTRST, NONE),
+	PAD_CFG_GPO(GPP_H0, 1, PLTRST),
 	/* H1:		BFX Strap 2 Bit 3	Weak Internal PD 20K	*/
 	PAD_CFG_GPO(GPP_H1, 0, DEEP),
 	/* H2:		Wireless LAN Reset				*/
-	PAD_CFG_GPO_GPIO_DRIVER(GPP_H2, 1, PLTRST, NONE),
+	PAD_CFG_GPO(GPP_H2, 1, PLTRST),
 	/* H3:		Not Connected					*/
 	PAD_NC(GPP_H3, NONE),
 	/* H4:		I2C 0 SDA		Touchpad		*/
diff --git a/src/mainboard/starlabs/starbook/variants/adl_n/gpio.c b/src/mainboard/starlabs/starbook/variants/adl_n/gpio.c
index e61c9a0d2e..3c5c7d0b97 100644
--- a/src/mainboard/starlabs/starbook/variants/adl_n/gpio.c
+++ b/src/mainboard/starlabs/starbook/variants/adl_n/gpio.c
@@ -63,7 +63,7 @@ const struct pad_config gpio_table[] = {
 	/* A12:		Not Connected					*/
 	PAD_NC(GPP_A12, NONE),
 	/* A13:		BlueTooth RF Kill				*/
-	PAD_CFG_GPO_GPIO_DRIVER(GPP_A13, 1, DEEP, NONE),
+	PAD_CFG_GPO(GPP_A13, 1, DEEP),
 	/* A14:		Test Point 45					*/
 	PAD_NC(GPP_A14, NONE),
 	/* A15:		Test Point 52					*/
@@ -228,7 +228,7 @@ const struct pad_config gpio_table[] = {
 	/* D15:		Not Connected					*/
 	PAD_NC(GPP_D15, NONE),
 	/* D16:		PCH M.2 SSD Power Enable			*/
-	PAD_CFG_GPO_GPIO_DRIVER(GPP_D16, 1, DEEP, NONE),
+	PAD_CFG_GPO(GPP_D16, 1, DEEP),
 	/* D17:		Not used		Fingerprint ID		*/
 	PAD_NC(GPP_D17, NONE),
 	/* D18:		Not Connected					*/
@@ -243,7 +243,7 @@ const struct pad_config gpio_table[] = {
 	/* E2:		Not Connected					*/
 	PAD_NC(GPP_E2, NONE),
 	/* E3:		WiFi RF Kill					*/
-	PAD_CFG_GPO_GPIO_DRIVER(GPP_E3, 1, DEEP, NONE),
+	PAD_CFG_GPO(GPP_E3, 1, DEEP),
 	/* E4:		Test Point 14					*/
 	PAD_NC(GPP_E4, NONE),
 	/* E5:		Not Connected					*/
@@ -339,11 +339,11 @@ const struct pad_config gpio_table[] = {
 	PAD_NC(GPP_F23, NONE),
 
 	/* H0:		PCH M.2 SSD Reset				*/
-	PAD_CFG_GPO_GPIO_DRIVER(GPP_H0, 1, PLTRST, NONE),
+	PAD_CFG_GPO(GPP_H0, 1, PLTRST),
 	/* H1:		BFX Strap 2 Bit 3	Weak Internal PD 20K	*/
 	PAD_CFG_GPO(GPP_H1, 0, DEEP),
 	/* H2:		Wireless LAN Reset				*/
-	PAD_CFG_GPO_GPIO_DRIVER(GPP_H2, 1, PLTRST, NONE),
+	PAD_CFG_GPO(GPP_H2, 1, PLTRST),
 	/* H3:		Not Connected					*/
 	PAD_NC(GPP_H3, NONE),
 	/* H4:		I2C 0 SDA		Touchpad		*/
diff --git a/src/mainboard/starlabs/starbook/variants/cml/gpio.c b/src/mainboard/starlabs/starbook/variants/cml/gpio.c
index 2baac30998..e29cd8199b 100644
--- a/src/mainboard/starlabs/starbook/variants/cml/gpio.c
+++ b/src/mainboard/starlabs/starbook/variants/cml/gpio.c
@@ -116,7 +116,7 @@ const struct pad_config gpio_table[] = {
 	/* B3:	CLICK_PAD_INT_R_N		*/
 	PAD_CFG_GPI_APIC_LOW(GPP_B3, NONE, PLTRST),
 	/* B4:	BT_RF_KILL_N			*/
-	PAD_CFG_GPO_GPIO_DRIVER(GPP_B4, 1, DEEP, NONE),
+	PAD_CFG_GPO(GPP_B4, 1, DEEP),
 	/* B5:	 WLAN_CLKREQ#			*/
 	PAD_CFG_NF(GPP_B5, NONE, DEEP, NF1),
 	/* B6:	 CLKREQ1_SSD_N			*/
@@ -161,7 +161,7 @@ const struct pad_config gpio_table[] = {
 	/* C1:	 SMB_DATA			*/
 	PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1),
 	/* C2:	 WIFI_RF_KILL_N			*/
-	PAD_CFG_GPO_GPIO_DRIVER(GPP_C2, 1, DEEP, NONE),
+	PAD_CFG_GPO(GPP_C2, 1, DEEP),
 	/* C3:	Not Connected			*/
 	PAD_NC(GPP_C3, NONE),
 	/* C4:	Not Connected			*/
diff --git a/src/mainboard/starlabs/starbook/variants/mtl/gpio.c b/src/mainboard/starlabs/starbook/variants/mtl/gpio.c
index 02f1db7484..e64baa3a9a 100644
--- a/src/mainboard/starlabs/starbook/variants/mtl/gpio.c
+++ b/src/mainboard/starlabs/starbook/variants/mtl/gpio.c
@@ -249,14 +249,14 @@ const struct pad_config gpio_table[] = {
 	 * End:		GPP_H23
 	 */
 	/* H00:	M.2_PCH_SSD_RESET_N		*/
-	PAD_CFG_GPO_GPIO_DRIVER(GPP_H00, 1, PLTRST, NONE),
+	PAD_CFG_GPO(GPP_H00, 1, PLTRST),
 	/* H01:	FLASH RECOVERY
 	 *		HIGH:	ENABLED
 	 *		LOW:	DISABLED
 	 *		WEAK INTERNAL PD 20K	*/
 	PAD_NC(GPP_H01, NONE),
 	/* H02:	WLAN_RST_N			*/
-	PAD_CFG_GPO_GPIO_DRIVER(GPP_H02, 1, PLTRST, NONE),
+	PAD_CFG_GPO(GPP_H02, 1, PLTRST),
 	/* H03:					*/
 	PAD_NC(GPP_H03, NONE),
 	/* H04:					*/
@@ -266,7 +266,7 @@ const struct pad_config gpio_table[] = {
 	/* H06:					*/
 	PAD_NC(GPP_H06, NONE),
 	/* H07:	M.2_CPU_SSD_PWREN		*/
-	PAD_CFG_GPO_GPIO_DRIVER(GPP_H07, 1, DEEP, NONE),
+	PAD_CFG_GPO(GPP_H07, 1, DEEP),
 	/* H08:					*/
 	PAD_NC(GPP_H08, NONE),
 	/* H09:					*/
@@ -432,9 +432,9 @@ const struct pad_config gpio_table[] = {
 	/* B17:					*/
 	PAD_NC(GPP_B17, NONE),
 	/* B18:	BT_RF_KILL_N			*/
-	PAD_CFG_GPO_GPIO_DRIVER(GPP_B18, 1, DEEP, NONE),
+	PAD_CFG_GPO(GPP_B18, 1, DEEP),
 	/* B19:	WIFI_RF_KILL_N			*/
-	PAD_CFG_GPO_GPIO_DRIVER(GPP_B19, 1, DEEP, NONE),
+	PAD_CFG_GPO(GPP_B19, 1, DEEP),
 	/* B20:					*/
 	PAD_NC(GPP_B20, NONE),
 	/* B21:					*/
diff --git a/src/mainboard/starlabs/starbook/variants/rpl/gpio.c b/src/mainboard/starlabs/starbook/variants/rpl/gpio.c
index 5e3cd0006a..542aa32b71 100644
--- a/src/mainboard/starlabs/starbook/variants/rpl/gpio.c
+++ b/src/mainboard/starlabs/starbook/variants/rpl/gpio.c
@@ -63,7 +63,7 @@ const struct pad_config gpio_table[] = {
 	/* A12:		PCH M.2 SSD PEDET				*/
 	PAD_NC(GPP_A12, NONE),
 	/* A13:		BlueTooth RF Kill				*/
-	PAD_CFG_GPO_GPIO_DRIVER(GPP_A13, 1, DEEP, NONE),
+	PAD_CFG_GPO(GPP_A13, 1, DEEP),
 	/* A14:		Test Point 45					*/
 	PAD_NC(GPP_A14, NONE),
 	/* A15:		Test Point 52					*/
@@ -224,7 +224,7 @@ const struct pad_config gpio_table[] = {
 	/* D13:		Wireless LAN Wake				*/
 	PAD_NC(GPP_D13, NONE),
 	/* D14:		CPU M.2 SSD Power Enable			*/
-	PAD_CFG_GPO_GPIO_DRIVER(GPP_D14, 1, DEEP, NONE),
+	PAD_CFG_GPO(GPP_D14, 1, DEEP),
 	/* D15:		Not Connected					*/
 	PAD_NC(GPP_D15, NONE),
 	/* D16:		PCH M.2 SSD Power Enable			*/
@@ -243,9 +243,9 @@ const struct pad_config gpio_table[] = {
 	/* E2:		Not Connected					*/
 	PAD_NC(GPP_E2, NONE),
 	/* E3:		WiFi RF Kill					*/
-	PAD_CFG_GPO_GPIO_DRIVER(GPP_E3, 1, DEEP, NONE),
+	PAD_CFG_GPO(GPP_E3, 1, DEEP),
 	/* E4:		Retimer Force Power				*/
-	PAD_CFG_GPO_GPIO_DRIVER(GPP_E4, 0, DEEP, NONE),
+	PAD_CFG_GPO(GPP_E4, 0, DEEP),
 	/* E5:		Not Connected					*/
 	PAD_NC(GPP_E5, NONE),
 	/* E6:		JTAG ODT		No internal PD
@@ -330,7 +330,7 @@ const struct pad_config gpio_table[] = {
 	/* F19:		Not Connected					*/
 	PAD_NC(GPP_F19, NONE),
 	/* F20:		CPU M.2 SSD Reset				*/
-	PAD_CFG_GPO_GPIO_DRIVER(GPP_F20, 1, PLTRST, NONE),
+	PAD_CFG_GPO(GPP_F20, 1, PLTRST),
 	/* F21:		GPPC_F21					*/
 	PAD_NC(GPP_F21, NONE),
 	/* F22:		Not Connected					*/
diff --git a/src/mainboard/starlabs/starbook/variants/tgl/gpio.c b/src/mainboard/starlabs/starbook/variants/tgl/gpio.c
index f1350c5b8e..2526f7fa68 100644
--- a/src/mainboard/starlabs/starbook/variants/tgl/gpio.c
+++ b/src/mainboard/starlabs/starbook/variants/tgl/gpio.c
@@ -66,7 +66,7 @@ const struct pad_config gpio_table[] = {
 	/* A10:	WLAN_PCM_IN			*/
 	PAD_NC(GPP_A10, NONE),
 	/* A11:	M2_CPU_SSD_RST_N		*/
-	PAD_CFG_GPO_GPIO_DRIVER(GPP_A11, 1, PLTRST, NONE),
+	PAD_CFG_GPO(GPP_A11, 1, PLTRST),
 	/* A12:	SATAGP_1			*/
 	PAD_CFG_NF(GPP_A12, UP_20K, DEEP, NF1),
 	/* A13:	Not Connected			*/
@@ -90,7 +90,7 @@ const struct pad_config gpio_table[] = {
 	/* A22:	Not Connected			*/
 	PAD_NC(GPP_A22, NONE),
 	/* A23:	TC_RETIMER_FORCE_PWR		*/
-	PAD_CFG_GPO_GPIO_DRIVER(GPP_A23, 0, DEEP, NONE),
+	PAD_CFG_GPO(GPP_A23, 0, DEEP),
 
 	/* B0:	CORE_VID_0			*/
 	PAD_CFG_NF(GPP_B0, NONE, DEEP, NF1),
@@ -219,7 +219,7 @@ const struct pad_config gpio_table[] = {
 	/* D15:	Not Connected			*/
 	PAD_NC(GPP_D15, NONE),
 	/* D16:	CPU_SSD_PWREN			*/
-	PAD_CFG_GPO_GPIO_DRIVER(GPP_D16, 1, DEEP, NONE),
+	PAD_CFG_GPO(GPP_D16, 1, DEEP),
 	/* D17:	Not Connected			*/
 	PAD_NC(GPP_D17, NONE),
 	/* D18:	Not Connected			*/
diff --git a/src/mainboard/starlabs/starfighter/variants/rpl/gpio.c b/src/mainboard/starlabs/starfighter/variants/rpl/gpio.c
index a69b210a30..bfd06741d1 100644
--- a/src/mainboard/starlabs/starfighter/variants/rpl/gpio.c
+++ b/src/mainboard/starlabs/starfighter/variants/rpl/gpio.c
@@ -72,7 +72,7 @@ const struct pad_config gpio_table[] = {
 	/* A12:		PCH M.2 SSD PEDET				*/
 	PAD_CFG_NF(GPP_A12, NONE, DEEP, NF1),
 	/* A13:		BlueTooth RF Kill				*/
-	PAD_CFG_GPO_GPIO_DRIVER(GPP_A13, 1, DEEP, NONE),
+	PAD_CFG_GPO(GPP_A13, 1, DEEP),
 	/* A14:		Test Point 45					*/
 	PAD_NC(GPP_A14, NONE),
 	/* A15:		Test Point 52					*/
@@ -229,7 +229,7 @@ const struct pad_config gpio_table[] = {
 	/* D13:		Wireless LAN Wake				*/
 	PAD_NC(GPP_D13, NONE),
 	/* D14:		CPU M.2 SSD Power Enable			*/
-	PAD_CFG_GPO_GPIO_DRIVER(GPP_D14, 1, DEEP, NONE),
+	PAD_CFG_GPO(GPP_D14, 1, DEEP),
 	/* D15:		Not Connected					*/
 	PAD_NC(GPP_D15, NONE),
 	/* D16:		PCH M.2 SSD Power Enable			*/
@@ -248,9 +248,9 @@ const struct pad_config gpio_table[] = {
 	/* E2:		Not Connected					*/
 	PAD_NC(GPP_E2, NONE),
 	/* E3:		WiFi RF Kill					*/
-	PAD_CFG_GPO_GPIO_DRIVER(GPP_E3, 1, DEEP, NONE),
+	PAD_CFG_GPO(GPP_E3, 1, DEEP),
 	/* E4:		Retimer Force Power				*/
-	PAD_CFG_GPO_GPIO_DRIVER(GPP_E4, 0, DEEP, NONE),
+	PAD_CFG_GPO(GPP_E4, 0, DEEP),
 	/* E5:		Not Connected					*/
 	PAD_NC(GPP_E5, NONE),
 	/* E6:		JTAG ODT		No internal PD
@@ -327,7 +327,7 @@ const struct pad_config gpio_table[] = {
 	/* F19:		Not Connected					*/
 	PAD_NC(GPP_F19, NONE),
 	/* F20:		CPU M.2 SSD Reset				*/
-	PAD_CFG_GPO_GPIO_DRIVER(GPP_F20, 1, PLTRST, NONE),
+	PAD_CFG_GPO(GPP_F20, 1, PLTRST),
 	/* F21:		GPPC_F21					*/
 	PAD_NC(GPP_F21, NONE),
 	/* F22:		Not Connected					*/
@@ -340,7 +340,7 @@ const struct pad_config gpio_table[] = {
 	/* H1:		BFX Strap 2 Bit 3	Weak Internal PD 20K	*/
 	PAD_CFG_GPO(GPP_H1, 0, DEEP),
 	/* H2:		Wireless LAN Reset				*/
-	PAD_CFG_GPO_GPIO_DRIVER(GPP_H2, 1, PLTRST, NONE),
+	PAD_CFG_GPO(GPP_H2, 1, PLTRST),
 	/* H3:		Not Connected					*/
 	PAD_NC(GPP_H3, NONE),
 	/* H4:		I2C 0 SDA		Touchpad		*/
diff --git a/src/mainboard/starlabs/starlite_adl/variants/mk_v/gpio.c b/src/mainboard/starlabs/starlite_adl/variants/mk_v/gpio.c
index edde160dec..f7a9737aa3 100644
--- a/src/mainboard/starlabs/starlite_adl/variants/mk_v/gpio.c
+++ b/src/mainboard/starlabs/starlite_adl/variants/mk_v/gpio.c
@@ -63,7 +63,7 @@ const struct pad_config gpio_table[] = {
 	/* A12:		Not Connected					*/
 	PAD_NC(GPP_A12, NONE),
 	/* A13:		BlueTooth RF Kill				*/
-	PAD_CFG_GPO_GPIO_DRIVER(GPP_A13, 1, DEEP, NONE),
+	PAD_CFG_GPO(GPP_A13, 1, DEEP),
 	/* A14:		Camera Power Enable				*/
 	PAD_NC(GPP_A14, NONE),
 	/* A15:		Camera Reset					*/
@@ -227,7 +227,7 @@ const struct pad_config gpio_table[] = {
 	/* D15:		Not Connected					*/
 	PAD_NC(GPP_D15, NONE),
 	/* D16:		PCH M.2 SSD Power Enable			*/
-	PAD_CFG_GPO_GPIO_DRIVER(GPP_D16, 1, DEEP, NONE),
+	PAD_CFG_GPO(GPP_D16, 1, DEEP),
 	/* D17:		Not used		Fingerprint ID		*/
 	PAD_NC(GPP_D17, NONE),
 	/* D18:		Bluetooth Wake					*/
@@ -242,7 +242,7 @@ const struct pad_config gpio_table[] = {
 	/* E2:		Not Connected					*/
 	PAD_NC(GPP_E2, NONE),
 	/* E3:		WiFi RF Kill					*/
-	PAD_CFG_GPO_GPIO_DRIVER(GPP_E3, 1, DEEP, NONE),
+	PAD_CFG_GPO(GPP_E3, 1, DEEP),
 	/* E4:		P Offset					*/
 	PAD_NC(GPP_E4, NONE),
 	/* E5:		P Out						*/
@@ -323,7 +323,7 @@ const struct pad_config gpio_table[] = {
 	/* F16:		Not Connected					*/
 	PAD_NC(GPP_F16, NONE),
 	/* F17:		Touch Panel Reset				*/
-	PAD_CFG_GPO_GPIO_DRIVER(GPP_F17, 1, PLTRST, NONE),
+	PAD_CFG_GPO(GPP_F17, 1, PLTRST),
 	/* F18:		Touch Panel Interrupt				*/
 	PAD_CFG_GPI_APIC(GPP_F18, NONE, PLTRST, LEVEL, INVERT),
 	/* F19:		Not Connected					*/
@@ -338,7 +338,7 @@ const struct pad_config gpio_table[] = {
 	PAD_NC(GPP_F23, NONE),
 
 	/* H0:		PCH M.2 SSD Reset				*/
-	PAD_CFG_GPO_GPIO_DRIVER(GPP_H0, 1, PLTRST, NONE),
+	PAD_CFG_GPO(GPP_H0, 1, PLTRST),
 	/* H1:		BFX Strap 2 Bit 3	Weak Internal PD 20K	*/
 	PAD_CFG_GPO(GPP_H1, 0, DEEP),
 	/* H2:		Wireless LAN Reset				*/
@@ -450,7 +450,7 @@ const struct pad_config gpio_table[] = {
 	PAD_NC(GPP_R7, NONE),
 
 	/* BT_EN */
-	PAD_CFG_GPO_GPIO_DRIVER(GPP_VGPIO_0, 1, DEEP, NONE),
+	PAD_CFG_GPO(GPP_VGPIO_0, 1, DEEP),
 
 	/* CNVi BT UART0 */
 	PAD_NC(GPP_VGPIO_6, NONE),

From 0c72983da26389460f26b4181e27de5c9ab49e45 Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Fri, 7 Feb 2025 16:39:03 -0600
Subject: [PATCH 0046/3886] ec/starlabs/merlin: Only include lid switch ACPI
 when needed

Desktop devices don't need and shouldn't define a lid switch.

TEST=build/boot starlabs/byte,starlite_adl

Change-Id: Iecf3e2558e244cc0bec301a505c0bc86684954aa
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86322
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
---
 src/ec/starlabs/merlin/acpi/ec.asl | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/ec/starlabs/merlin/acpi/ec.asl b/src/ec/starlabs/merlin/acpi/ec.asl
index f3fdb07334..ae5092772f 100644
--- a/src/ec/starlabs/merlin/acpi/ec.asl
+++ b/src/ec/starlabs/merlin/acpi/ec.asl
@@ -112,11 +112,11 @@ Scope (\_SB.PCI0.LPCB)
 		#include "ac.asl"
 #if CONFIG(SYSTEM_TYPE_LAPTOP) || CONFIG(SYSTEM_TYPE_DETACHABLE)
 		#include "battery.asl"
+		#include "lid.asl"
 #endif
 #if !CONFIG(EC_STARLABS_MERLIN)
 		#include "events.asl"
 #endif
-		#include "lid.asl"
 #if CONFIG(SYSTEM_TYPE_DETACHABLE)
 		#include "dock.asl"
 #endif

From 46e9d5a3989e25c558ec1cf9868fd05e1e0d0cb3 Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Fri, 10 Jan 2025 10:57:59 -0600
Subject: [PATCH 0047/3886] mb/starlabs/starlite_adl: Increase display
 brightness at POST

Adjust the POST brightness level in the VBT from 50 to 150 (max 255).

Change-Id: I1704a3479c38510b29427d582ee14c740401cd38
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86345
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 .../starlite_adl/variants/mk_v/data.vbt       | Bin 9216 -> 9216 bytes
 1 file changed, 0 insertions(+), 0 deletions(-)

diff --git a/src/mainboard/starlabs/starlite_adl/variants/mk_v/data.vbt b/src/mainboard/starlabs/starlite_adl/variants/mk_v/data.vbt
index cbd4a5ae19445168ea76f731d248f15d89164774..a985a4b18a819d4122a5aecef554467f36113e3f 100644
GIT binary patch
delta 41
xcmZqhXz-XI#ca)BFgcM?c%#8&KE`R2FYswkzR$-qS(smAvOK@UW^4YVA^-{641NFr

delta 46
zcmZqhXz-XI#oWVSFgcM?c%#8&K1QR-7x=U%-{<4uWMg1p0Aa~V{N|gj`HzYK052^I
Ay8r+H


From 773a405b7b5cdd828a0cebc0a420a7756c75dc24 Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Fri, 7 Feb 2025 12:24:33 -0600
Subject: [PATCH 0048/3886] {ec,mb}/starlabs: Consolidate EC-related CFR
 options in ec directory

Move all of the EC-related CFR options into a header in the ec
directory, so it can be reused across multiple boards.

TEST=build/boot starlabs/starbook_mtl,starlite_adl and verify CFR
options work properly.

Change-Id: I831559184de917b32e4993e8e34ffbc7b7e883e4
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86318
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/ec/starlabs/merlin/cfr.h              | 114 ++++++++++++++++++++++
 src/mainboard/starlabs/lite/cfr.c         |  23 +----
 src/mainboard/starlabs/starbook/cfr.c     |  77 +--------------
 src/mainboard/starlabs/starfighter/cfr.c  |  77 +--------------
 src/mainboard/starlabs/starlite_adl/cfr.c |  54 +---------
 5 files changed, 118 insertions(+), 227 deletions(-)
 create mode 100644 src/ec/starlabs/merlin/cfr.h

diff --git a/src/ec/starlabs/merlin/cfr.h b/src/ec/starlabs/merlin/cfr.h
new file mode 100644
index 0000000000..b56e7d2e52
--- /dev/null
+++ b/src/ec/starlabs/merlin/cfr.h
@@ -0,0 +1,114 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+/*
+ * CFR enums and structs which are used to control EC settings.
+ */
+
+#include <drivers/option/cfr_frontend.h>
+#include "ec.h"
+
+/*
+ * Keyboard Backlight Timeout
+ */
+static const struct sm_object kbl_timeout = SM_DECLARE_ENUM({
+	.opt_name	= "kbl_timeout",
+	.ui_name	= "Keyboard Backlight Timeout",
+	.ui_helptext	= "Set the amount of time before the keyboard backlight turns off"
+			  " when un-used",
+	.default_value	= 0,
+	.values		= (struct sm_enum_value[]) {
+				{ "30 seconds",		0	},
+				{ "1 minute",		1	},
+				{ "3 minutes",		2	},
+				{ "5 minutes",		3	},
+				{ "Never",		4	},
+				SM_ENUM_VALUE_END		},
+});
+
+
+/*
+ * Function-Control Swap
+ */
+static const struct sm_object fn_ctrl_swap = SM_DECLARE_BOOL({
+	.opt_name	= "fn_ctrl_swap",
+	.ui_name	= "Fn Ctrl Reverse",
+	.ui_helptext	= "Swap the functions of the [Fn] and [Ctrl] keys",
+	.default_value	= false,
+});
+
+/*
+ * Maximum Battery Charge Level
+ */
+static const struct sm_object max_charge = SM_DECLARE_ENUM({
+	.opt_name	= "max_charge",
+	.ui_name	= "Maximum Charge Level",
+	.ui_helptext	= "Set the maximum level the battery will charge to.",
+	.default_value	= 0,
+	.values		= (const struct sm_enum_value[]) {
+				{ "100%",		0	},
+				{ "80%",		1	},
+				{ "60%",		2	},
+				SM_ENUM_VALUE_END		},
+});
+
+/*
+ * Fan Mode
+ */
+static const struct sm_object fan_mode = SM_DECLARE_ENUM({
+	.opt_name	= "fan_mode",
+	.ui_name	= "Fan Mode",
+	.ui_helptext	= "Adjust the fan curve to prioritize performance or noise levels.",
+	.default_value	= 0,
+	.values		= (const struct sm_enum_value[]) {
+				{ "Normal",		0		},
+				{ "Aggressive",		1		},
+				{ "Quiet",		2		},
+				{ "Disabled",		3		},
+				SM_ENUM_VALUE_END			},
+});
+
+/*
+ * Charging Speed
+ */
+static const struct sm_object charging_speed = SM_DECLARE_ENUM({
+	.opt_name	= "charging_speed",
+	.ui_name	= "Charging Speed",
+	.ui_helptext	= "Set the maximum speed to charge the battery. Charging faster"
+			  " will increase heat and battery wear.",
+	.default_value	= 1,
+	.values		= (const struct sm_enum_value[]) {
+				{ "1.0C",		0	},
+				{ "0.5C",		1	},
+				{ "0.2C",		2	},
+				SM_ENUM_VALUE_END		},
+});
+
+/*
+ * Lid Switch
+ */
+static const struct sm_object lid_switch = SM_DECLARE_ENUM({
+	.opt_name	= "lid_switch",
+	.ui_name	= "Lid Switch",
+	.ui_helptext	= "Configure what opening or closing the lid will do.",
+	.default_value	= 0,
+	.values		= (const struct sm_enum_value[]) {
+				{ "Normal",		0	},
+				{ "Sleep Only",		1	},
+				{ "Disabled",		2	},
+				SM_ENUM_VALUE_END		},
+});
+
+/*
+ * Power LED Brightness
+ */
+static const struct sm_object power_led = SM_DECLARE_ENUM({
+	.opt_name	= "power_led",
+	.ui_name	= "Power LED Brightness",
+	.ui_helptext	= "Control the maximum brightness of the power LED",
+	.default_value	= 0,
+	.values		= (const struct sm_enum_value[]) {
+				{ "Normal",		0		},
+				{ "Reduced",		1		},
+				SM_ENUM_VALUE_END,
+	},
+});
diff --git a/src/mainboard/starlabs/lite/cfr.c b/src/mainboard/starlabs/lite/cfr.c
index e0d22e6b69..251f55c339 100644
--- a/src/mainboard/starlabs/lite/cfr.c
+++ b/src/mainboard/starlabs/lite/cfr.c
@@ -3,6 +3,7 @@
 #include <boot/coreboot_tables.h>
 #include <commonlib/coreboot_tables.h>
 #include <drivers/option/cfr_frontend.h>
+#include <ec/starlabs/merlin/cfr.h>
 #include <inttypes.h>
 #include <intelblocks/pcie_rp.h>
 #include <string.h>
@@ -54,28 +55,6 @@ static const struct sm_object fast_charge = SM_DECLARE_BOOL({
 });
 #endif
 
-static const struct sm_object fn_ctrl_swap = SM_DECLARE_BOOL({
-	.opt_name	= "fn_ctrl_swap",
-	.ui_name	= "Fn Ctrl Reverse",
-	.ui_helptext	= "Swap the functions of the [Fn] and [Ctrl] keys",
-	.default_value	= false,
-});
-
-static const struct sm_object kbl_timeout = SM_DECLARE_ENUM({
-	.opt_name	= "kbl_timeout",
-	.ui_name	= "Keyboard Backlight Timeout",
-	.ui_helptext	= "Set the amount of time before the keyboard backlight turns off"
-			  " when un-used",
-	.default_value	= 0,
-	.values		= (struct sm_enum_value[]) {
-				{ "30 seconds",		0	},
-				{ "1 minute",		1	},
-				{ "3 minutes",		2	},
-				{ "5 minutes",		3	},
-				{ "Never",		4	},
-				SM_ENUM_VALUE_END		},
-});
-
 static const struct sm_object power_on_after_fail = SM_DECLARE_BOOL({
 	.opt_name	= "power_on_after_fail",
 	.ui_name	= "Power on after failure",
diff --git a/src/mainboard/starlabs/starbook/cfr.c b/src/mainboard/starlabs/starbook/cfr.c
index bf0e4b0bcf..1e08ba1c12 100644
--- a/src/mainboard/starlabs/starbook/cfr.c
+++ b/src/mainboard/starlabs/starbook/cfr.c
@@ -3,6 +3,7 @@
 #include <boot/coreboot_tables.h>
 #include <commonlib/coreboot_tables.h>
 #include <drivers/option/cfr_frontend.h>
+#include <ec/starlabs/merlin/cfr.h>
 #include <inttypes.h>
 #include <intelblocks/pcie_rp.h>
 #include <string.h>
@@ -27,21 +28,6 @@ static const struct sm_object card_reader = SM_DECLARE_BOOL({
 	.default_value	= true,
 });
 
-#if CONFIG(EC_STARLABS_CHARGING_SPEED)
-static const struct sm_object charging_speed = SM_DECLARE_ENUM({
-	.opt_name	= "charging_speed",
-	.ui_name	= "Charging Speed",
-	.ui_helptext	= "Set the maximum speed to charge the battery. Charging faster"
-			  " will increase heat and battery wear.",
-	.default_value	= 1,
-	.values		= (const struct sm_enum_value[]) {
-				{ "1.0C",		0	},
-				{ "0.5C",		1	},
-				{ "0.2C",		2	},
-				SM_ENUM_VALUE_END		},
-});
-#endif
-
 static const struct sm_object debug_level = SM_DECLARE_ENUM({
 	.opt_name	= "debug_level",
 	.ui_name	= "Debug Level",
@@ -60,19 +46,6 @@ static const struct sm_object debug_level = SM_DECLARE_ENUM({
 				SM_ENUM_VALUE_END			},
 });
 
-static const struct sm_object fan_mode = SM_DECLARE_ENUM({
-	.opt_name	= "fan_mode",
-	.ui_name	= "Fan Mode",
-	.ui_helptext	= "Adjust the fan curve to prioritize performance or noise levels.",
-	.default_value	= 0,
-	.values		= (const struct sm_enum_value[]) {
-				{ "Normal",		0		},
-				{ "Aggressive",		1		},
-				{ "Quiet",		2		},
-				{ "Disabled",		3		},
-				SM_ENUM_VALUE_END			},
-});
-
 #if CONFIG(BOARD_STARLABS_STARBOOK_ADL) || CONFIG(BOARD_STARLABS_STARBOOK_RPL)
 static const struct sm_object fingerprint_reader = SM_DECLARE_BOOL({
 	.opt_name	= "fingerprint_reader",
@@ -82,13 +55,6 @@ static const struct sm_object fingerprint_reader = SM_DECLARE_BOOL({
 });
 #endif
 
-static const struct sm_object fn_ctrl_swap = SM_DECLARE_BOOL({
-	.opt_name	= "fn_ctrl_swap",
-	.ui_name	= "Fn Ctrl Reverse",
-	.ui_helptext	= "Swap the functions of the [Fn] and [Ctrl] keys",
-	.default_value	= false,
-});
-
 #if CONFIG(SOC_INTEL_TIGERLAKE) || CONFIG(SOC_INTEL_ALDERLAKE) || CONFIG(SOC_INTEL_RAPTORLAKE)
 static const struct sm_object gna = SM_DECLARE_BOOL({
 	.opt_name	= "gna",
@@ -107,47 +73,6 @@ static const struct sm_object hyper_threading = SM_DECLARE_BOOL({
 });
 #endif
 
-static const struct sm_object kbl_timeout = SM_DECLARE_ENUM({
-	.opt_name	= "kbl_timeout",
-	.ui_name	= "Keyboard Backlight Timeout",
-	.ui_helptext	= "Set the amount of time before the keyboard backlight turns off"
-			  " when un-used",
-	.default_value	= 0,
-	.values		= (struct sm_enum_value[]) {
-				{ "30 seconds",		0	},
-				{ "1 minute",		1	},
-				{ "3 minutes",		2	},
-				{ "5 minutes",		3	},
-				{ "Never",		4	},
-				SM_ENUM_VALUE_END		},
-});
-
-#if CONFIG(EC_STARLABS_LID_SWITCH)
-static const struct sm_object lid_switch = SM_DECLARE_ENUM({
-	.opt_name	= "lid_switch",
-	.ui_name	= "Lid Switch",
-	.ui_helptext	= "Configure what opening or closing the lid will do.",
-	.default_value	= 0,
-	.values		= (const struct sm_enum_value[]) {
-				{ "Normal",		0	},
-				{ "Sleep Only",		1	},
-				{ "Disabled",		2	},
-				SM_ENUM_VALUE_END		},
-});
-#endif
-
-static const struct sm_object max_charge = SM_DECLARE_ENUM({
-	.opt_name	= "max_charge",
-	.ui_name	= "Maximum Charge Level",
-	.ui_helptext	= "Set the maximum level the battery will charge to.",
-	.default_value	= 0,
-	.values		= (const struct sm_enum_value[]) {
-				{ "100%",		0	},
-				{ "80%",		1	},
-				{ "60%",		2	},
-				SM_ENUM_VALUE_END		},
-});
-
 static const struct sm_object me_state = SM_DECLARE_ENUM({
 	.opt_name	= "me_state",
 	.ui_name	= "Intel Management Engine",
diff --git a/src/mainboard/starlabs/starfighter/cfr.c b/src/mainboard/starlabs/starfighter/cfr.c
index f310f86a64..7e040cce31 100644
--- a/src/mainboard/starlabs/starfighter/cfr.c
+++ b/src/mainboard/starlabs/starfighter/cfr.c
@@ -3,6 +3,7 @@
 #include <boot/coreboot_tables.h>
 #include <commonlib/coreboot_tables.h>
 #include <drivers/option/cfr_frontend.h>
+#include <ec/starlabs/merlin/cfr.h>
 #include <inttypes.h>
 #include <intelblocks/pcie_rp.h>
 #include <string.h>
@@ -20,21 +21,6 @@ static const struct sm_object boot_option = SM_DECLARE_ENUM({
 				SM_ENUM_VALUE_END			},
 });
 
-#if CONFIG(EC_STARLABS_CHARGING_SPEED)
-static const struct sm_object charging_speed = SM_DECLARE_ENUM({
-	.opt_name	= "charging_speed",
-	.ui_name	= "Charging Speed",
-	.ui_helptext	= "Set the maximum speed to charge the battery. Charging faster"
-			  " will increase heat and battery wear.",
-	.default_value	= 1,
-	.values		= (const struct sm_enum_value[]) {
-				{ "1.0C",		0	},
-				{ "0.5C",		1	},
-				{ "0.2C",		2	},
-				SM_ENUM_VALUE_END		},
-});
-#endif
-
 static const struct sm_object debug_level = SM_DECLARE_ENUM({
 	.opt_name	= "debug_level",
 	.ui_name	= "Debug Level",
@@ -53,26 +39,6 @@ static const struct sm_object debug_level = SM_DECLARE_ENUM({
 				SM_ENUM_VALUE_END			},
 });
 
-static const struct sm_object fan_mode = SM_DECLARE_ENUM({
-	.opt_name	= "fan_mode",
-	.ui_name	= "Fan Mode",
-	.ui_helptext	= "Adjust the fan curve to prioritize performance or noise levels.",
-	.default_value	= 0,
-	.values		= (const struct sm_enum_value[]) {
-				{ "Normal",		0		},
-				{ "Aggressive",		1		},
-				{ "Quiet",		2		},
-				{ "Disabled",		3		},
-				SM_ENUM_VALUE_END			},
-});
-
-static const struct sm_object fn_ctrl_swap = SM_DECLARE_BOOL({
-	.opt_name	= "fn_ctrl_swap",
-	.ui_name	= "Fn Ctrl Reverse",
-	.ui_helptext	= "Swap the functions of the [Fn] and [Ctrl] keys",
-	.default_value	= false,
-});
-
 #if CONFIG(SOC_INTEL_TIGERLAKE) || CONFIG(SOC_INTEL_ALDERLAKE) || CONFIG(SOC_INTEL_RAPTORLAKE)
 static const struct sm_object gna = SM_DECLARE_BOOL({
 	.opt_name	= "gna",
@@ -89,47 +55,6 @@ static const struct sm_object hyper_threading = SM_DECLARE_BOOL({
 	.default_value	= true,
 });
 
-static const struct sm_object kbl_timeout = SM_DECLARE_ENUM({
-	.opt_name	= "kbl_timeout",
-	.ui_name	= "Keyboard Backlight Timeout",
-	.ui_helptext	= "Set the amount of time before the keyboard backlight turns off"
-			  " when un-used",
-	.default_value	= 0,
-	.values		= (struct sm_enum_value[]) {
-				{ "30 seconds",		0	},
-				{ "1 minute",		1	},
-				{ "3 minutes",		2	},
-				{ "5 minutes",		3	},
-				{ "Never",		4	},
-				SM_ENUM_VALUE_END		},
-});
-
-#if CONFIG(EC_STARLABS_LID_SWITCH)
-static const struct sm_object lid_switch = SM_DECLARE_ENUM({
-	.opt_name	= "lid_switch",
-	.ui_name	= "Lid Switch",
-	.ui_helptext	= "Configure what opening or closing the lid will do.",
-	.default_value	= 0,
-	.values		= (const struct sm_enum_value[]) {
-				{ "Normal",		0	},
-				{ "Sleep Only",		1	},
-				{ "Disabled",		2	},
-				SM_ENUM_VALUE_END		},
-});
-#endif
-
-static const struct sm_object max_charge = SM_DECLARE_ENUM({
-	.opt_name	= "max_charge",
-	.ui_name	= "Maximum Charge Level",
-	.ui_helptext	= "Set the maximum level the battery will charge to.",
-	.default_value	= 0,
-	.values		= (const struct sm_enum_value[]) {
-				{ "100%",		0	},
-				{ "80%",		1	},
-				{ "60%",		2	},
-				SM_ENUM_VALUE_END		},
-});
-
 static const struct sm_object me_state = SM_DECLARE_ENUM({
 	.opt_name	= "me_state",
 	.ui_name	= "Intel Management Engine",
diff --git a/src/mainboard/starlabs/starlite_adl/cfr.c b/src/mainboard/starlabs/starlite_adl/cfr.c
index a8e44fa11c..a00a7a7f4a 100644
--- a/src/mainboard/starlabs/starlite_adl/cfr.c
+++ b/src/mainboard/starlabs/starlite_adl/cfr.c
@@ -3,6 +3,7 @@
 #include <boot/coreboot_tables.h>
 #include <commonlib/coreboot_tables.h>
 #include <drivers/option/cfr_frontend.h>
+#include <ec/starlabs/merlin/cfr.h>
 #include <inttypes.h>
 #include <intelblocks/pcie_rp.h>
 #include <string.h>
@@ -27,21 +28,6 @@ static const struct sm_object boot_option = SM_DECLARE_ENUM({
 				SM_ENUM_VALUE_END			},
 });
 
-#if CONFIG(EC_STARLABS_CHARGING_SPEED)
-static const struct sm_object charging_speed = SM_DECLARE_ENUM({
-	.opt_name	= "charging_speed",
-	.ui_name	= "Charging Speed",
-	.ui_helptext	= "Set the maximum speed to charge the battery. Charging faster"
-			  " will increase heat and battery wear.",
-	.default_value	= 1,
-	.values		= (const struct sm_enum_value[]) {
-				{ "1.0C",		0	},
-				{ "0.5C",		1	},
-				{ "0.2C",		2	},
-				SM_ENUM_VALUE_END		},
-});
-#endif
-
 static const struct sm_object debug_level = SM_DECLARE_ENUM({
 	.opt_name	= "debug_level",
 	.ui_name	= "Debug Level",
@@ -69,32 +55,6 @@ static const struct sm_object gna = SM_DECLARE_BOOL({
 });
 #endif
 
-#if CONFIG(EC_STARLABS_LID_SWITCH)
-static const struct sm_object lid_switch = SM_DECLARE_ENUM({
-	.opt_name	= "lid_switch",
-	.ui_name	= "Lid Switch",
-	.ui_helptext	= "Configure what opening or closing the lid will do.",
-	.default_value	= 0,
-	.values		= (const struct sm_enum_value[]) {
-				{ "Normal",		0	},
-				{ "Sleep Only",		1	},
-				{ "Disabled",		2	},
-				SM_ENUM_VALUE_END		},
-});
-#endif
-
-static const struct sm_object max_charge = SM_DECLARE_ENUM({
-	.opt_name	= "max_charge",
-	.ui_name	= "Maximum Charge Level",
-	.ui_helptext	= "Set the maximum level the battery will charge to.",
-	.default_value	= 0,
-	.values		= (const struct sm_enum_value[]) {
-				{ "100%",		0	},
-				{ "80%",		1	},
-				{ "60%",		2	},
-				SM_ENUM_VALUE_END		},
-});
-
 static const struct sm_object me_state = SM_DECLARE_ENUM({
 	.opt_name	= "me_state",
 	.ui_name	= "Intel Management Engine",
@@ -194,18 +154,6 @@ static const struct sm_object pciexp_l1ss = SM_DECLARE_ENUM({
 });
 #endif
 
-static const struct sm_object power_led = SM_DECLARE_ENUM({
-	.opt_name	= "power_led",
-	.ui_name	= "Power LED Brightness",
-	.ui_helptext	= "Control the maximum brightness of the power LED",
-	.default_value	= 0,
-	.values		= (const struct sm_enum_value[]) {
-				{ "Normal",		0		},
-				{ "Reduced",		1		},
-				SM_ENUM_VALUE_END,
-	},
-});
-
 static const struct sm_object reboot_counter = SM_DECLARE_NUMBER({
 	.opt_name	= "reboot_counter",
 	.ui_name	= "Reboot Counter",

From 8d87fd7d320bab05540edef90f0ada0bc2385f87 Mon Sep 17 00:00:00 2001
From: Patrick Rudolph <patrick.rudolph@9elements.com>
Date: Thu, 6 Feb 2025 09:19:09 +0100
Subject: [PATCH 0049/3886] soc/amd: Document VBIOS handling

The code flow isn't that obvious in the beginning. You pass an address
of the VBIOS to FSP, but don't load any VBIOS until BS_DEV_RESOURCES
phase.
Add comments to document what is done and when. This will help to
improve the code in the next step.

Change-Id: I643bc9088306d99cc0fbb79648809e16b068fb33
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86298
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
---
 src/soc/amd/cezanne/fsp_s_params.c           |  5 +++++
 src/soc/amd/common/block/graphics/graphics.c | 16 +++++++++++++---
 src/soc/amd/glinda/fsp_s_params.c            |  5 +++++
 src/soc/amd/mendocino/fsp_s_params.c         |  5 +++++
 src/soc/amd/phoenix/fsp_s_params.c           |  5 +++++
 src/soc/amd/picasso/fsp_s_params.c           |  5 +++++
 6 files changed, 38 insertions(+), 3 deletions(-)

diff --git a/src/soc/amd/cezanne/fsp_s_params.c b/src/soc/amd/cezanne/fsp_s_params.c
index 60f3942802..b9770f3ef5 100644
--- a/src/soc/amd/cezanne/fsp_s_params.c
+++ b/src/soc/amd/cezanne/fsp_s_params.c
@@ -8,6 +8,11 @@
 
 static void fsp_assign_vbios_upds(FSP_S_CONFIG *scfg)
 {
+	/*
+	 * The VBIOS contains the ATOMBIOS tables that will be modified as
+	 * part of FSP GOP init. We can delay loading of the VBIOS until
+	 * before FSP notify AFTER_PCI_ENUM.
+	 */
 	scfg->vbios_buffer = CONFIG(RUN_FSP_GOP) ? PCI_VGA_RAM_IMAGE_START : 0;
 }
 
diff --git a/src/soc/amd/common/block/graphics/graphics.c b/src/soc/amd/common/block/graphics/graphics.c
index ea7308a850..77420aebaa 100644
--- a/src/soc/amd/common/block/graphics/graphics.c
+++ b/src/soc/amd/common/block/graphics/graphics.c
@@ -147,9 +147,13 @@ static const char *graphics_acpi_name(const struct device *dev)
 }
 
 /*
- * Even though AMD does not need VBT we still need to implement the
- * vbt_get() function to not break the build with GOP driver enabled
- * (see fsps_return_value_handler() in fsp2_0/silicon_init.c
+ * On AMD platforms the VBT is called ATOMBIOS and is always part of the
+ * VGA Option ROM. As part of the FSP GOP init the ATOMBIOS tables are
+ * updated in place. Thus the VBIOS must be loaded into RAM before FSP GOP
+ * runs. The address of the VBIOS must be passed to FSP-S using UPDs, but
+ * loading of the VBIOS can be delayed until before FSP AFTER_PCI_ENUM
+ * notify is called. FSP expects a pointer to the PCI option rom instead
+ * a pointer to the ATOMBIOS table directly.
  */
 void *vbt_get(void)
 {
@@ -165,6 +169,7 @@ static void graphics_set_resources(struct device *const dev)
 	if (!CONFIG(RUN_FSP_GOP))
 		return;
 
+	/* Load the VBIOS before FSP AFTER_PCI_ENUM notify is called. */
 	timestamp_add_now(TS_OPROM_INITIALIZE);
 	if (CONFIG(USE_SELECTIVE_GOP_INIT) && vbios_cache_is_valid() &&
 			!display_init_required()) {
@@ -172,6 +177,11 @@ static void graphics_set_resources(struct device *const dev)
 		timestamp_add_now(TS_OPROM_COPY_END);
 		return;
 	}
+
+	/*
+	 * VBIOS cache was not used, so load it from CBFS and let FSP GOP
+	 * initialize the ATOMBIOS tables.
+	 */
 	rom = pci_rom_probe(dev);
 	if (rom == NULL) {
 		printk(BIOS_ERR, "%s: Unable to find ROM for %s\n",
diff --git a/src/soc/amd/glinda/fsp_s_params.c b/src/soc/amd/glinda/fsp_s_params.c
index 597f7a9ea3..e03795792d 100644
--- a/src/soc/amd/glinda/fsp_s_params.c
+++ b/src/soc/amd/glinda/fsp_s_params.c
@@ -10,6 +10,11 @@
 
 static void fsp_assign_vbios_upds(FSP_S_CONFIG *scfg)
 {
+	/*
+	 * The VBIOS contains the ATOMBIOS tables that will be modified as
+	 * part of FSP GOP init. We can delay loading of the VBIOS until
+	 * before FSP notify AFTER_PCI_ENUM.
+	 */
 	scfg->vbios_buffer = CONFIG(RUN_FSP_GOP) ? PCI_VGA_RAM_IMAGE_START : 0;
 }
 
diff --git a/src/soc/amd/mendocino/fsp_s_params.c b/src/soc/amd/mendocino/fsp_s_params.c
index 50923e9af7..5c37334f5a 100644
--- a/src/soc/amd/mendocino/fsp_s_params.c
+++ b/src/soc/amd/mendocino/fsp_s_params.c
@@ -20,6 +20,11 @@ static void fsp_assign_vbios_upds(FSP_S_CONFIG *scfg)
 		printk(BIOS_SPEW, "%s: using VBIOS cache; skipping GOP driver.\n", __func__);
 		return;
 	}
+	/*
+	 * The VBIOS contains the ATOMBIOS tables that will be modified as
+	 * part of FSP GOP init. We can delay loading of the VBIOS until
+	 * before FSP notify AFTER_PCI_ENUM.
+	 */
 	printk(BIOS_SPEW, "%s: not using VBIOS cache; running GOP driver.\n", __func__);
 	scfg->vbios_buffer = CONFIG(RUN_FSP_GOP) ? PCI_VGA_RAM_IMAGE_START : 0;
 }
diff --git a/src/soc/amd/phoenix/fsp_s_params.c b/src/soc/amd/phoenix/fsp_s_params.c
index 46c8e76d94..883cde0f89 100644
--- a/src/soc/amd/phoenix/fsp_s_params.c
+++ b/src/soc/amd/phoenix/fsp_s_params.c
@@ -10,6 +10,11 @@
 
 static void fsp_assign_vbios_upds(FSP_S_CONFIG *scfg)
 {
+	/*
+	 * The VBIOS contains the ATOMBIOS tables that will be modified as
+	 * part of FSP GOP init. We can delay loading of the VBIOS until
+	 * before FSP notify AFTER_PCI_ENUM.
+	 */
 	scfg->vbios_buffer = CONFIG(RUN_FSP_GOP) ? PCI_VGA_RAM_IMAGE_START : 0;
 }
 
diff --git a/src/soc/amd/picasso/fsp_s_params.c b/src/soc/amd/picasso/fsp_s_params.c
index 9f491d6516..d4cfa276c1 100644
--- a/src/soc/amd/picasso/fsp_s_params.c
+++ b/src/soc/amd/picasso/fsp_s_params.c
@@ -185,6 +185,11 @@ static void fsp_edp_tuning_upds(FSP_S_CONFIG *scfg,
 
 static void fsp_assign_vbios_upds(FSP_S_CONFIG *scfg)
 {
+	/*
+	 * The VBIOS contains the ATOMBIOS tables that will be modified as
+	 * part of FSP GOP init. We can delay loading of the VBIOS until
+	 * before FSP notify AFTER_PCI_ENUM.
+	 */
 	scfg->vbios_buffer_addr = CONFIG(RUN_FSP_GOP) ? PCI_VGA_RAM_IMAGE_START : 0;
 }
 

From 9c5496ecb06b12b6ea1cd0e9c8ca266bab381565 Mon Sep 17 00:00:00 2001
From: Lu Tang <lu.tang@mediatek.corp-partner.google.com>
Date: Fri, 7 Feb 2025 14:10:53 +0800
Subject: [PATCH 0050/3886] soc/mediatek/mt8196: Set the driving strength of
 SPMI-P to maximum

To fix the SPMI-P glitch, the driving strength of SPMI-P needs to be set
to a maximum value of 16mA. Additionally, a hardware solution of
external pull-down is also required.

BRANCH=rauru
TEST=Build passed and booted successfully. The platform remained idle
for approximately 20 hours without hang.
BUG=b:383634290

Signed-off-by: Lu Tang <lu.tang@mediatek.corp-partner.google.com>
Change-Id: I131fd04c0313c7ed64bbd123f61d9a6849c8def4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86341
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
---
 src/soc/mediatek/mt8196/pmif_spmi.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/src/soc/mediatek/mt8196/pmif_spmi.c b/src/soc/mediatek/mt8196/pmif_spmi.c
index c4a984f5a6..cb78249662 100644
--- a/src/soc/mediatek/mt8196/pmif_spmi.c
+++ b/src/soc/mediatek/mt8196/pmif_spmi.c
@@ -165,9 +165,9 @@ void pmif_spmi_iocfg(void)
 	/* SPMI_M 10mA */
 	gpio_set_driving(GPIO(SPMI_M_SCL), GPIO_DRV_10_MA);
 	gpio_set_driving(GPIO(SPMI_M_SDA), GPIO_DRV_10_MA);
-	/* SPMI_P 14mA */
-	gpio_set_driving(GPIO(SPMI_P_SCL), GPIO_DRV_14_MA);
-	gpio_set_driving(GPIO(SPMI_P_SDA), GPIO_DRV_14_MA);
+	/* SPMI_P 16mA */
+	gpio_set_driving(GPIO(SPMI_P_SCL), GPIO_DRV_16_MA);
+	gpio_set_driving(GPIO(SPMI_P_SDA), GPIO_DRV_16_MA);
 	/* SPMI-P set Pull-Down mode */
 	gpio_set_pull(GPIO(SPMI_P_SCL), GPIO_PULL_ENABLE, GPIO_PULL_DOWN);
 	gpio_set_pull(GPIO(SPMI_P_SDA), GPIO_PULL_ENABLE, GPIO_PULL_DOWN);

From 93cef8791b0e58112957e3f5b533bae565c1b83e Mon Sep 17 00:00:00 2001
From: Guangjie Song <guangjie.song@mediatek.com>
Date: Tue, 14 Jan 2025 15:01:58 +0800
Subject: [PATCH 0051/3886] soc/mediatek/mt8196: Correct MMinfra vote register

Correct MMinfra vote register to fix MMinfra power off failure during
suspend.

BRANCH=rauru
BUG=b:377628718
TEST=Bootup OK and Suspend/Resume OK, with MMinfra kernel/vcp patch,
mminfra can be turned off to reduce power consumption by 50mW.

Signed-off-by: Guangjie Song <guangjie.song@mediatek.com>
Change-Id: I7c23c3c53c68b0de85d8b6189b685de7f8398e8b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86342
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
---
 src/soc/mediatek/mt8196/mtcmos.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/soc/mediatek/mt8196/mtcmos.c b/src/soc/mediatek/mt8196/mtcmos.c
index 367e74b464..e274be8639 100644
--- a/src/soc/mediatek/mt8196/mtcmos.c
+++ b/src/soc/mediatek/mt8196/mtcmos.c
@@ -42,8 +42,8 @@
 #define MMVOTE_MTCMOS_1_CLR		((void *)(MMVOTE_BASE + 0x0224))
 #define MMVOTE_MTCMOS_1_DONE		((void *)(MMVOTE_BASE + 0x142C))
 #define MMVOTE_MTCMOS_1_PM_ACK		((void *)(MMVOTE_BASE + 0x5518))
-#define MMINFRA_MTCMOS_1_SET		((void *)(MMVOTE_BASE + 0x43220))
-#define MMINFRA_MTCMOS_1_CLR		((void *)(MMVOTE_BASE + 0x43224))
+#define MMINFRA_MTCMOS_1_SET		((void *)(MMVOTE_BASE + 0x20220))
+#define MMINFRA_MTCMOS_1_CLR		((void *)(MMVOTE_BASE + 0x20224))
 
 #define DISP_VDISP_AO_CONFIG_CG		0x3E800108
 #define DISP_DPC_DISP0_MTCMOS_CFG	0x3E8F0500

From d5a3f9998fd904c90c33c6cd33c52a0c21fa707f Mon Sep 17 00:00:00 2001
From: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Date: Mon, 3 Feb 2025 13:39:14 +0800
Subject: [PATCH 0052/3886] mb/google/nissa/var/dirks: Add initial override
 devicetree

Add initial override devicetree for dirks based on the
latest schematic (0W4_TWL_A_MB_0120.pdf).

    - Add eMMC DLL tuning value (copy from riven)
    - Configure I2C buses
    - Configure USB ports
    - Configure audio codec
    - Configure WIFI6(CNVi) and WIFI7(PCIe)

Note :
There will be a separate CL to configure the implementation of
repurposing the TCSS port to USB Type-A after FSP support is added.

BUG=b:389391653
TEST=none.

Change-Id: Ic0b80e3121d94ede771ecc30cf0c66a67b9a41d0
Signed-off-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86250
Reviewed-by: Jayvik Desai <jayvik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
---
 .../brya/variants/dirks/overridetree.cb       | 347 +++++++++++++++++-
 1 file changed, 345 insertions(+), 2 deletions(-)

diff --git a/src/mainboard/google/brya/variants/dirks/overridetree.cb b/src/mainboard/google/brya/variants/dirks/overridetree.cb
index 4f2c04a57a..bc1c1867bb 100644
--- a/src/mainboard/google/brya/variants/dirks/overridetree.cb
+++ b/src/mainboard/google/brya/variants/dirks/overridetree.cb
@@ -1,6 +1,349 @@
 chip soc/intel/alderlake
 
-        device domain 0 on
-        end
+	register "sagv" = "SaGv_Enabled"
 
+	# EMMC Tx CMD Delay
+	# Refer to EDS-Vol2-42.3.7.
+	# [14:8] steps of delay for DDR mode, each 125ps, range: 0 - 39.
+	# [6:0] steps of delay for SDR mode, each 125ps, range: 0 - 39.
+	register "common_soc_config.emmc_dll.emmc_tx_cmd_cntl" = "0x505"
+
+	# EMMC TX DATA Delay 1
+	# Refer to EDS-Vol2-42.3.8.
+	# [14:8] steps of delay for HS400, each 125ps, range: 0 - 78.
+	# [6:0] steps of delay for SDR104/HS200, each 125ps, range: 0 - 79.
+	register "common_soc_config.emmc_dll.emmc_tx_data_cntl1" = "0x909"
+
+	# EMMC TX DATA Delay 2
+	# Refer to EDS-Vol2-42.3.9.
+	# [30:24] steps of delay for SDR50, each 125ps, range: 0 - 79.
+	# [22:16] steps of delay for DDR50, each 125ps, range: 0 - 78.
+	# [14:8] steps of delay for SDR25/HS50, each 125ps, range: 0 -79.
+	# [6:0] steps of delay for SDR12, each 125ps. Range: 0 - 79.
+	register "common_soc_config.emmc_dll.emmc_tx_data_cntl2" = "0x1C2A2828"
+
+	# EMMC RX CMD/DATA Delay 1
+	# Refer to EDS-Vol2-42.3.10.
+	# [30:24] steps of delay for SDR50, each 125ps, range: 0 - 119.
+	# [22:16] steps of delay for DDR50, each 125ps, range: 0 - 78.
+	# [14:8] steps of delay for SDR25/HS50, each 125ps, range: 0 - 119.
+	# [6:0] steps of delay for SDR12, each 125ps, range: 0 - 119.
+	register "common_soc_config.emmc_dll.emmc_rx_cmd_data_cntl1" = "0x1C1B4F1B"
+
+	# EMMC RX CMD/DATA Delay 2
+	# Refer to EDS-Vol2-42.3.12.
+	# [17:16] stands for Rx Clock before Output Buffer,
+	#         00: Rx clock after output buffer,
+	#         01: Rx clock before output buffer,
+	#         10: Automatic selection based on working mode.
+	#         11: Reserved
+	# [14:8] steps of delay for Auto Tuning Mode, each 125ps, range: 0 - 39.
+	# [6:0] steps of delay for HS200, each 125ps, range: 0 - 79.
+	register "common_soc_config.emmc_dll.emmc_rx_cmd_data_cntl2" = "0x10023"
+
+	# EMMC Rx Strobe Delay
+	# Refer to EDS-Vol2-42.3.11.
+	# [14:8] Rx Strobe Delay DLL 1(HS400 Mode), each 125ps, range: 0 - 39.
+	# [6:0] Rx Strobe Delay DLL 2(HS400 Mode), each 125ps, range: 0 - 39.
+	register "common_soc_config.emmc_dll.emmc_rx_strobe_cntl" = "0x11515"
+
+	# SOC Aux orientation override:
+	# This is a bitfield that corresponds to up to 4 TCSS ports.
+	# Bits (0,1) allocated for TCSS Port1 configuration and Bits (2,3)for TCSS Port2.
+	# TcssAuxOri = 0101b
+	# Bit0,Bit2 set to "1" indicates no retimer on USBC Ports
+	# Bit1,Bit3 set to "0" indicates Aux lines are not swapped on the
+	# motherboard to USBC connector
+	register "tcss_aux_ori" = "0x1"
+
+	register "typec_aux_bias_pads[0]" = "{.pad_auxp_dc = GPP_A21, .pad_auxn_dc = GPP_A22}"
+
+	register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC_SKIP)"	# USB2_C0
+	register "usb2_ports[1]" = "USB2_PORT_MID(OC0)"		# USB2_A0
+	register "usb2_ports[2]" = "USB2_PORT_MID(OC1)"		# USB2_A1
+	register "usb2_ports[3]" = "USB2_PORT_MID(OC2)"		# USB2_A2
+	register "usb2_ports[4]" = "USB2_PORT_MID(OC3)"		# USB2_A3
+	register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)"	# USB2_A4
+	register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)"	# Bluetooth port for PCIe WLAN
+	register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)"	# Bluetooth port for CNVi WLAN
+
+	register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)"	# USB3/2 Type A port A1
+	register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)"	# USB3/2 Type A port A2
+	register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)"	# USB3/2 Type A port A3
+	register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)"	# USB3/2 Type A port A4
+
+	register "tcss_ports[0]" = "TCSS_PORT_DEFAULT(OC_SKIP)" # USB3_C0
+	register "tcss_ports[1]" = "TCSS_PORT_DEFAULT(OC_SKIP)" # USB3/2 Type A port A0
+
+	register "serial_io_i2c_mode" = "{
+	[PchSerialIoIndexI2C0] = PchSerialIoPci,
+	[PchSerialIoIndexI2C1] = PchSerialIoDisabled,
+	[PchSerialIoIndexI2C2] = PchSerialIoDisabled,
+	[PchSerialIoIndexI2C3] = PchSerialIoPci,
+	[PchSerialIoIndexI2C4] = PchSerialIoDisabled,
+	[PchSerialIoIndexI2C5] = PchSerialIoDisabled,
+	}"
+
+	# Enable the Cnvi BT Audio Offload
+	register "cnvi_bt_audio_offload" = "1"
+
+	# Intel Common SoC Config
+	#+-------------------+---------------------------+
+	#| Field             |  Value                    |
+	#+-------------------+---------------------------+
+	#| I2C0              | TPM. Early init is        |
+	#|                   | required to set up a BAR  |
+	#|                   | for TPM communication     |
+	#| I2C3              | Audio                     |
+	#+-------------------+---------------------------+
+	register "common_soc_config" = "{
+		.i2c[0] = {
+			.early_init = 1,
+			.speed = I2C_SPEED_FAST_PLUS,
+			.speed_config[0] = {
+				.speed = I2C_SPEED_FAST_PLUS,
+				.scl_lcnt = 55,
+				.scl_hcnt = 30,
+				.sda_hold = 7,
+			}
+		},
+		.i2c[3] = {
+			.speed = I2C_SPEED_FAST,
+			.speed_config[0] = {
+				.speed = I2C_SPEED_FAST,
+				.scl_lcnt = 158,
+				.scl_hcnt = 79,
+				.sda_hold = 7,
+			}
+		},
+	}"
+
+	device domain 0 on
+		device ref dtt on
+			chip drivers/intel/dptf
+				## sensor information
+				register "options.tsr[0].desc" = ""Memory""
+				register "options.tsr[1].desc" = ""Charger""
+				register "options.tsr[2].desc" = ""Ambient""
+
+				# TODO: below values are initial reference values only
+				## Passive Policy
+				register "policies.passive" = "{
+					[0] = DPTF_PASSIVE(CPU,         CPU,           95, 5000),
+					[1] = DPTF_PASSIVE(CPU,         TEMP_SENSOR_0, 75, 5000),
+					[2] = DPTF_PASSIVE(CHARGER,     TEMP_SENSOR_1, 75, 5000),
+					[3] = DPTF_PASSIVE(CPU,         TEMP_SENSOR_2, 75, 5000),
+				}"
+
+				## Critical Policy
+				register "policies.critical" = "{
+					[0] = DPTF_CRITICAL(CPU,               105, SHUTDOWN),
+					[1] = DPTF_CRITICAL(TEMP_SENSOR_0,      85, SHUTDOWN),
+					[2] = DPTF_CRITICAL(TEMP_SENSOR_1,      85, SHUTDOWN),
+					[3] = DPTF_CRITICAL(TEMP_SENSOR_2,      85, SHUTDOWN),
+				}"
+
+				register "controls.power_limits" = "{
+					.pl1 = {
+							.min_power = 5500,
+							.max_power = 6000,
+							.time_window_min = 28 * MSECS_PER_SEC,
+							.time_window_max = 28 * MSECS_PER_SEC,
+							.granularity = 200
+						},
+					.pl2 = {
+							.min_power = 25000,
+							.max_power = 25000,
+							.time_window_min = 1,
+							.time_window_max = 1,
+							.granularity = 1000
+						}
+				}"
+
+				## Charger Performance Control (Control, mA)
+				register "controls.charger_perf" = "{
+					[0] = { 255, 1700 },
+					[1] = {  24, 1500 },
+					[2] = {  16, 1000 },
+					[3] = {   8,  500 }
+				}"
+
+				device generic 0 on end
+			end
+		end
+		device ref cnvi_wifi on
+			chip drivers/wifi/generic
+				register "enable_cnvi_ddr_rfim" = "true"
+				device generic 0 on end
+			end
+		end
+		device ref i2c3 on
+			chip drivers/i2c/generic
+				register "hid" = ""RTL5682""
+				register "name" = ""RT58""
+				register "desc" = ""Headset Codec""
+				register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_A23)"
+				# Set the jd_src to RT5668_JD1 for jack detection
+				register "property_count" = "1"
+				register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER"
+				register "property_list[0].name" = ""realtek,jd-src""
+				register "property_list[0].integer" = "1"
+				device i2c 1a on end
+			end
+		end
+		device ref hda on
+			chip drivers/sof
+				register "jack_tplg" = "rt5682"
+				device generic 0 on end
+			end
+		end
+		device ref pcie_rp11 on
+			# Enable wlan PCIe 11 using clk 2
+			register "pch_pcie_rp[PCH_RP(10)]" = "{
+				.clk_src = 2,
+				.clk_req = 2,
+				.flags = PCIE_RP_LTR | PCIE_RP_AER,
+			}"
+			chip drivers/wifi/generic
+				register "wake" = "GPE0_DW1_03"
+				register "add_acpi_dma_property" = "true"
+				use usb2_port8 as bluetooth_companion
+				device pci 00.0 on end
+			end
+			chip soc/intel/common/block/pcie/rtd3
+				register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B11)"
+				register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_H20)"
+				register "srcclk_pin" = "2"
+				device generic 0 on end
+			end
+		end
+		device ref emmc on end
+		device ref pch_espi on
+			chip ec/google/chromeec
+				use conn0 as mux_conn[0]
+				device pnp 0c09.0 on end
+			end
+		end
+		device ref pmc hidden
+			chip drivers/intel/pmc_mux
+				device generic 0 on
+					chip drivers/intel/pmc_mux/conn
+						use usb2_port1 as usb2_port
+						use tcss_usb3_port1 as usb3_port
+						device generic 0 alias conn0 on end
+					end
+				end
+			end
+		end
+		device ref tcss_xhci on
+			chip drivers/usb/acpi
+				device ref tcss_root_hub on
+					chip drivers/usb/acpi
+						register "desc" = ""USB3 Type-C Port C0""
+						register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
+						register "use_custom_pld" = "true"
+						register "custom_pld" = "ACPI_PLD_TYPE_C(BACK, RIGHT, ACPI_PLD_GROUP(2, 1))"
+						device ref tcss_usb3_port1 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB3 Type-A Port A0""
+						register "type" = "UPC_TYPE_A"
+						register "use_custom_pld" = "true"
+						register "custom_pld" = "ACPI_PLD_TYPE_A(FRONT, RIGHT, ACPI_PLD_GROUP(1, 1))"
+						device ref tcss_usb3_port2 on end
+					end
+				end
+			end
+		end
+		device ref xhci on
+			chip drivers/usb/acpi
+				device ref xhci_root_hub on
+					chip drivers/usb/acpi
+						register "desc" = ""USB2 Type-C Port C0""
+						register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
+						register "use_custom_pld" = "true"
+						register "custom_pld" = "ACPI_PLD_TYPE_C(BACK, RIGHT, ACPI_PLD_GROUP(2, 1))"
+						device ref usb2_port1 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB2 Type-A Port A0""
+						register "type" = "UPC_TYPE_A"
+						register "use_custom_pld" = "true"
+						register "custom_pld" = "ACPI_PLD_TYPE_A(FRONT, RIGHT, ACPI_PLD_GROUP(1, 1))"
+						device ref usb2_port2 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB2 Type-A Port A1""
+						register "type" = "UPC_TYPE_A"
+						register "use_custom_pld" = "true"
+						register "custom_pld" = "ACPI_PLD_TYPE_A(BACK, LEFT, ACPI_PLD_GROUP(2, 3))"
+						device ref usb2_port3 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB2 Type-A Port A2""
+						register "type" = "UPC_TYPE_A"
+						register "use_custom_pld" = "true"
+						register "custom_pld" = "ACPI_PLD_TYPE_A(FRONT, CENTER, ACPI_PLD_GROUP(1, 2))"
+						device ref usb2_port4 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB2 Type-A Port A3""
+						register "type" = "UPC_TYPE_A"
+						register "use_custom_pld" = "true"
+						register "custom_pld" = "ACPI_PLD_TYPE_A(FRONT, LEFT, ACPI_PLD_GROUP(1, 3))"
+						device ref usb2_port5 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB2 Type-A Port A4""
+						register "type" = "UPC_TYPE_A"
+						register "use_custom_pld" = "true"
+						register "custom_pld" = "ACPI_PLD_TYPE_A(BACK, CENTER, ACPI_PLD_GROUP(2, 2))"
+						device ref usb2_port6 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB2 Bluetooth""
+						register "type" = "UPC_TYPE_INTERNAL"
+						register "reset_gpio" =
+							"ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D4)"
+						device ref usb2_port8 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""CNVI Bluetooth""
+						register "type" = "UPC_TYPE_INTERNAL"
+						register "reset_gpio" =
+							"ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D4)"
+						device ref usb2_port10 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB3 Type-A Port A1""
+						register "type" = "UPC_TYPE_USB3_A"
+						register "use_custom_pld" = "true"
+						register "custom_pld" = "ACPI_PLD_TYPE_A(BACK, LEFT, ACPI_PLD_GROUP(2, 3))"
+						device ref usb3_port1 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB3 Type-A Port A2""
+						register "type" = "UPC_TYPE_USB3_A"
+						register "use_custom_pld" = "true"
+						register "custom_pld" = "ACPI_PLD_TYPE_A(FRONT, CENTER, ACPI_PLD_GROUP(1, 2))"
+						device ref usb3_port2 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB3 Type-A Port A3""
+						register "type" = "UPC_TYPE_USB3_A"
+						register "use_custom_pld" = "true"
+						register "custom_pld" = "ACPI_PLD_TYPE_A(FRONT, LEFT, ACPI_PLD_GROUP(1, 3))"
+						device ref usb3_port3 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB3 Type-A Port A4""
+						register "type" = "UPC_TYPE_USB3_A"
+						register "use_custom_pld" = "true"
+						register "custom_pld" = "ACPI_PLD_TYPE_A(BACK, CENTER, ACPI_PLD_GROUP(2, 2))"
+						device ref usb3_port4 on end
+					end
+				end
+			end
+		end
+	end
 end

From ba3af158aa2462e261ebcf67d0d11fd56323a8d4 Mon Sep 17 00:00:00 2001
From: Julius Werner <jwerner@chromium.org>
Date: Thu, 23 Jan 2025 16:48:22 -0800
Subject: [PATCH 0053/3886] libpayload: Unify selfboot() implementations

selfboot() doesn't really need to be architecture dependent. All
architectures are essentially doing the same thing with a normal
function call, only x86_32 needs an extra attribute. arm64 and x86 also
previously haven't been passing the coreboot table pointer, even though
they should. This patch fixes that.

Change-Id: If14040e38d968b5eea31cd6cd25efb1845a7b081
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86142
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 payloads/libpayload/arch/arm/Makefile.mk      |  1 -
 payloads/libpayload/arch/arm64/Makefile.mk    |  1 -
 payloads/libpayload/arch/arm64/selfboot.c     | 34 -------------------
 payloads/libpayload/arch/x86/Makefile.mk      |  2 +-
 payloads/libpayload/arch/x86/selfboot.c       | 34 -------------------
 payloads/libpayload/libc/Makefile.mk          |  1 +
 .../libpayload/{arch/arm => libc}/selfboot.c  | 13 ++++---
 7 files changed, 8 insertions(+), 78 deletions(-)
 delete mode 100644 payloads/libpayload/arch/arm64/selfboot.c
 delete mode 100644 payloads/libpayload/arch/x86/selfboot.c
 rename payloads/libpayload/{arch/arm => libc}/selfboot.c (89%)

diff --git a/payloads/libpayload/arch/arm/Makefile.mk b/payloads/libpayload/arch/arm/Makefile.mk
index 47c271b993..3308135515 100644
--- a/payloads/libpayload/arch/arm/Makefile.mk
+++ b/payloads/libpayload/arch/arm/Makefile.mk
@@ -39,7 +39,6 @@ libc-y += timer.c coreboot.c util.S
 libc-y += virtual.c
 libc-y += exception_asm.S exception.c
 libc-y += cache.c cpu.S
-libc-y += selfboot.c
 
 # Will fall back to default_memXXX() in libc/memory.c if GPL not allowed.
 libc-$(CONFIG_LP_GPL) += memcpy.S memset.S memmove.S
diff --git a/payloads/libpayload/arch/arm64/Makefile.mk b/payloads/libpayload/arch/arm64/Makefile.mk
index d6cc51efdf..a4fda1dfe6 100644
--- a/payloads/libpayload/arch/arm64/Makefile.mk
+++ b/payloads/libpayload/arch/arm64/Makefile.mk
@@ -36,7 +36,6 @@ libc-y += virtual.c
 libc-y += memcpy.S memset.S memmove.S
 libc-y += exception_asm.S exception.c
 libc-y += cache.c cpu.S
-libc-y += selfboot.c
 libc-y += mmu.c
 
 libgdb-y += gdb.c
diff --git a/payloads/libpayload/arch/arm64/selfboot.c b/payloads/libpayload/arch/arm64/selfboot.c
deleted file mode 100644
index 5c3e4459e9..0000000000
--- a/payloads/libpayload/arch/arm64/selfboot.c
+++ /dev/null
@@ -1,34 +0,0 @@
-/*
- * Copyright 2014 Google Inc.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- * 3. The name of the author may not be used to endorse or promote products
- *    derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- */
-
-#include <libpayload.h>
-
-void selfboot(void *entry)
-{
-	void (*entry_func)(void) = entry;
-	entry_func();
-}
diff --git a/payloads/libpayload/arch/x86/Makefile.mk b/payloads/libpayload/arch/x86/Makefile.mk
index 35e69cbe4d..b2aaacce44 100644
--- a/payloads/libpayload/arch/x86/Makefile.mk
+++ b/payloads/libpayload/arch/x86/Makefile.mk
@@ -40,7 +40,7 @@ libc-$(CONFIG_LP_ARCH_X86_64) += pt.S
 libc-y += main.c sysinfo.c
 libc-y += timer.c coreboot.c util.S
 libc-y += virtual.c
-libc-y += selfboot.c cache.c
+libc-y += cache.c
 libc-y += exception.c
 libc-y += delay.c
 libc-$(CONFIG_LP_ARCH_X86_32) += exec.c
diff --git a/payloads/libpayload/arch/x86/selfboot.c b/payloads/libpayload/arch/x86/selfboot.c
deleted file mode 100644
index 5c3e4459e9..0000000000
--- a/payloads/libpayload/arch/x86/selfboot.c
+++ /dev/null
@@ -1,34 +0,0 @@
-/*
- * Copyright 2014 Google Inc.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- * 3. The name of the author may not be used to endorse or promote products
- *    derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- */
-
-#include <libpayload.h>
-
-void selfboot(void *entry)
-{
-	void (*entry_func)(void) = entry;
-	entry_func();
-}
diff --git a/payloads/libpayload/libc/Makefile.mk b/payloads/libpayload/libc/Makefile.mk
index 3d070ebe5b..063118a925 100644
--- a/payloads/libpayload/libc/Makefile.mk
+++ b/payloads/libpayload/libc/Makefile.mk
@@ -38,6 +38,7 @@ libc-$(CONFIG_LP_LIBC) += hexdump.c
 libc-$(CONFIG_LP_LIBC) += coreboot.c
 libc-$(CONFIG_LP_LIBC) += fmap.c
 libc-$(CONFIG_LP_LIBC) += fpmath.c
+libc-$(CONFIG_LP_LIBC) += selfboot.c
 
 ifeq ($(CONFIG_LP_VBOOT_LIB),y)
 libc-$(CONFIG_LP_LIBC) += lp_vboot.c
diff --git a/payloads/libpayload/arch/arm/selfboot.c b/payloads/libpayload/libc/selfboot.c
similarity index 89%
rename from payloads/libpayload/arch/arm/selfboot.c
rename to payloads/libpayload/libc/selfboot.c
index 70cc79e08f..3e226b472c 100644
--- a/payloads/libpayload/arch/arm/selfboot.c
+++ b/payloads/libpayload/libc/selfboot.c
@@ -1,5 +1,5 @@
 /*
- * Copyright 2014 Google Inc.
+ * Copyright 2025 Google LLC
  *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
@@ -31,10 +31,9 @@ extern void *cb_header_ptr;
 
 void selfboot(void *entry)
 {
-	__asm__ __volatile__(
-		"mov r0, %[cb_header_ptr]\n"
-		"bx %[entry]\n"
-		:: [cb_header_ptr]"r"(cb_header_ptr), [entry]"r"(entry)
-		: "r0"
-	);
+#if CONFIG(LP_ARCH_X86_32)
+	__attribute__((__regparm__(0)))
+#endif
+	void (*entry_func)(void *arg) = entry;
+	entry_func(cb_header_ptr);
 }

From 8fad6b043c7e7e17af72040134c96717f4af67ea Mon Sep 17 00:00:00 2001
From: Yu-Ping Wu <yupingso@chromium.org>
Date: Tue, 11 Feb 2025 14:48:21 +0000
Subject: [PATCH 0054/3886] Update blobs submodule to upstream main

Updating from commit id 14f8fcc1b426:
2024-11-28 05:07:49 +0000 - (soc/mediatek/mt8196: Update SSPM firmware to v2.0)

to commit id a0726508b86d:
2025-02-06 17:31:46 +0800 - (soc/mediatek/mt8196: Update SSPM firmware to v4.0)

This brings in 10 new commits:
a0726508b86d soc/mediatek/mt8196: Update SSPM firmware to v4.0
efe57af33c41 soc/mediatek/mt8196: Add mtk_fsp_ramstage version v1.0
ec3eb123e329 soc/mediatek/mt8196: Update SSPM firmware to v3.0
f7428ce40d6a soc/mediatek/mt8186: Update SSPM firmware from v2.0.1 to v2.0.2
4b3be4b01f10 soc/mediatek/mt8196: Add mtk_fsp_romstage version v1.0
11da5595c96c soc/mediatek/mt8196: Add PI_IMG firmware v1.0
491c2f791901 soc/mediatek/mt8196: Update MCUPM firmware to v1.1
316468e7befd soc/mediatek/mt8196: Add GPUEB firmware v1.0
288ebf18db56 soc/mediatek/mt8196: Add SPM firmware v1.0
7130fc0c8eba soc/mediatek/mt8196: Update DRAM blob to 0.4.0

Change-Id: Ic0e99e28c9705c769042a29fbf86e44af9ba7e68
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86365
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 3rdparty/blobs | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/3rdparty/blobs b/3rdparty/blobs
index 14f8fcc1b4..a0726508b8 160000
--- a/3rdparty/blobs
+++ b/3rdparty/blobs
@@ -1 +1 @@
-Subproject commit 14f8fcc1b426cb0884a21a9b715da6e0c1c7f434
+Subproject commit a0726508b86dafe490ff9908274eff408298b15d

From 71824342dfbbe36b908c19667f68048e6ac00193 Mon Sep 17 00:00:00 2001
From: John Su <john_su@compal.corp-partner.google.com>
Date: Sun, 9 Feb 2025 23:41:29 +0800
Subject: [PATCH 0055/3886] mb/google/trulo/var/uldrenite: Add fw_config probe
 for USB-C ports

Use fw_config to probe USB-C ports.

BUG=b:392040004
BRANCH=firmware-trulo-15217.771.B
TEST=emerge-nissa coreboot chromeos-bootimage

Change-Id: Ic0161e8b85c5a2afe6ec8473497d21a5737f4f70
Signed-off-by: John Su <john_su@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86338
Reviewed-by: Jayvik Desai <jayvik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
---
 .../google/brya/variants/uldrenite/overridetree.cb   | 12 ++++++++++--
 1 file changed, 10 insertions(+), 2 deletions(-)

diff --git a/src/mainboard/google/brya/variants/uldrenite/overridetree.cb b/src/mainboard/google/brya/variants/uldrenite/overridetree.cb
index 862968efd4..285db4aa96 100644
--- a/src/mainboard/google/brya/variants/uldrenite/overridetree.cb
+++ b/src/mainboard/google/brya/variants/uldrenite/overridetree.cb
@@ -7,6 +7,10 @@ fw_config
 		option TOUCHSCREEN_UNKNOWN	0
 		option TOUCHSCREEN_NONE		1
 	end
+	field MB_TYPEC 7 7
+		option MB_C_TWO			0
+		option MB_C_ONE			1
+	end
 end
 
 chip soc/intel/alderlake
@@ -250,7 +254,9 @@ chip soc/intel/alderlake
 						register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
 						register "use_custom_pld" = "true"
 						register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, RIGHT, ACPI_PLD_GROUP(2, 1))"
-						device ref tcss_usb3_port2 on end
+						device ref tcss_usb3_port2 on
+							probe MB_TYPEC MB_C_TWO
+						end
 					end
 				end
 			end
@@ -270,7 +276,9 @@ chip soc/intel/alderlake
 						register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
 						register "use_custom_pld" = "true"
 						register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(2, 1))"
-						device ref usb2_port2 on end
+						device ref usb2_port2 on
+							probe MB_TYPEC MB_C_TWO
+						end
 					end
 					chip drivers/usb/acpi
 						register "desc" = ""USB2 Type-A Port A0 (MLB)""

From c0506ad1e09fd17f0cc5a2a7ebb457eff230f024 Mon Sep 17 00:00:00 2001
From: Yu-Ping Wu <yupingso@chromium.org>
Date: Tue, 11 Feb 2025 16:07:02 +0800
Subject: [PATCH 0056/3886] soc/mediatek/mt8196: Require mtk_fsp_*.elf to exist

As MT8196 won't be able to boot up without mtk_fsp_romstage.elf and
mtk_fsp_ramstage.elf, ensure their presence in build time.

Change-Id: I668319ae1f63818e324002e7ae4d888479edb9cf
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86355
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
---
 src/soc/mediatek/mt8196/Makefile.mk | 4 ----
 1 file changed, 4 deletions(-)

diff --git a/src/soc/mediatek/mt8196/Makefile.mk b/src/soc/mediatek/mt8196/Makefile.mk
index 4dd2d2d8f9..85b670afb3 100644
--- a/src/soc/mediatek/mt8196/Makefile.mk
+++ b/src/soc/mediatek/mt8196/Makefile.mk
@@ -125,17 +125,13 @@ FSP_ROMSTAGE_CBFS := $(CONFIG_CBFS_PREFIX)/mtk_fsp_romstage
 $(FSP_ROMSTAGE_CBFS)-file := $(MT8196_BLOB_DIR)/mtk_fsp_romstage.elf
 $(FSP_ROMSTAGE_CBFS)-type := stage
 $(FSP_ROMSTAGE_CBFS)-compression := $(CBFS_PRERAM_COMPRESS_FLAG)
-ifneq ($(wildcard $($(FSP_ROMSTAGE_CBFS)-file)),)
 cbfs-files-y += $(FSP_ROMSTAGE_CBFS)
-endif
 
 FSP_RAMSTAGE_CBFS := $(CONFIG_CBFS_PREFIX)/mtk_fsp_ramstage
 $(FSP_RAMSTAGE_CBFS)-file := $(MT8196_BLOB_DIR)/mtk_fsp_ramstage.elf
 $(FSP_RAMSTAGE_CBFS)-type := stage
 $(FSP_RAMSTAGE_CBFS)-compression := $(CBFS_COMPRESS_FLAG)
-ifneq ($(wildcard $($(FSP_RAMSTAGE_CBFS)-file)),)
 cbfs-files-y += $(FSP_RAMSTAGE_CBFS)
-endif
 
 $(objcbfs)/bootblock.bin: $(objcbfs)/bootblock.raw.bin
 	./util/mtkheader/gen-bl-img.py mt8196 sf $< $@

From 5e14f1f5251b771dd17a0779475a03791750ff35 Mon Sep 17 00:00:00 2001
From: Guangjie Song <guangjie.song@mediatek.com>
Date: Mon, 13 Jan 2025 20:08:23 +0800
Subject: [PATCH 0057/3886] soc/mediatek/mt8196: Remove tvdpll3 disable/enable

The tvdpll3 cannot be disabled during suspend because of the enable
operation, so we remove the enable operation. Hardware can now
automatically enable and disable tvdpll3 based on the clock demand of
its downstream.

BRANCH=rauru
BUG=b:377628718
TEST=Bootup OK, Suspend/Resume OK and FW screen shown OK, with MMinfra
kernel/vcp patch, mminfra can be turned off to reduce power consumption.

Signed-off-by: Guangjie Song <guangjie.song@mediatek.com>
Change-Id: Ib9c72a1602c1f76dc94cca5c4a61a542a853560b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86343
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
---
 src/soc/mediatek/mt8196/pll.c | 4 ----
 1 file changed, 4 deletions(-)

diff --git a/src/soc/mediatek/mt8196/pll.c b/src/soc/mediatek/mt8196/pll.c
index 59a9b0943f..2007197003 100644
--- a/src/soc/mediatek/mt8196/pll.c
+++ b/src/soc/mediatek/mt8196/pll.c
@@ -1572,11 +1572,7 @@ void mt_pll_set_tvd_pll1_freq(u32 freq)
 {
 	const struct pll *pll = &plls[CLK_APMIXED2_TVDPLL3];
 
-	clrbits32(pll->reg, MT8196_PLL_EN);
 	pll_set_rate(pll, freq);
-	setbits32(pll->reg, MT8196_PLL_EN);
-
-	udelay(PLL_EN_DELAY);
 }
 
 void mt_pll_edp_mux_set_sel(u32 sel)

From d669736841dc9813fef6780ba833d5cff6ac7605 Mon Sep 17 00:00:00 2001
From: Shunxi Zhang <ot_shunxi.zhang@mediatek.com>
Date: Mon, 10 Feb 2025 16:47:28 +0800
Subject: [PATCH 0058/3886] soc/mediatek/mt8196: Fix RTC recovery by disabling
 external XTAL

Configure PMIC register 0x50c bit0 which decides whether to use external
xtal. This bit of mt6685 should be set to 1, to disable external xtal.

BRANCH=rauru
BUG=b:395485005
TEST=emerge-rauru coreboot chromeos-bootimage, remove battery and
charger, then insert battery and charge, RTC boots normally.

Signed-off-by: Shunxi Zhang <ot_shunxi.zhang@mediatek.com>
Change-Id: Iea44f13af030f24c02993dd43a35a9d8b4f72179
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86353
Reviewed-by: Shunxi Zhang <ot_shunxi.zhang@mediatek.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
---
 src/soc/mediatek/mt8196/mt6685_rtc.c | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/src/soc/mediatek/mt8196/mt6685_rtc.c b/src/soc/mediatek/mt8196/mt6685_rtc.c
index 4564a3144a..4e63f10664 100644
--- a/src/soc/mediatek/mt8196/mt6685_rtc.c
+++ b/src/soc/mediatek/mt8196/mt6685_rtc.c
@@ -345,6 +345,10 @@ static void rtc_recovery_flow(void)
 {
 	printk(BIOS_INFO, "%s: enter\n", __func__);
 
+	config_interface(SCK_TOP_XTAL_SEL_ADDR, 1, SCK_TOP_XTAL_SEL_MASK,
+			 SCK_TOP_XTAL_SEL_SHIFT);
+	udelay(100);
+
 	if (!retry(RECOVERY_RETRY_COUNT,
 		   rtc_frequency_meter_check() &&
 		   rtc_init_after_recovery())) {

From 825ad863b5d972dd26c759309664fdaa260381d1 Mon Sep 17 00:00:00 2001
From: Subrata Banik <subratabanik@google.com>
Date: Mon, 10 Feb 2025 09:56:40 +0530
Subject: [PATCH 0059/3886] mb/google/fatcat: Use TDP macros for CPU TDP values

This commit replaces the hardcoded 25 values for CPU TDP with the
TDP_25W macro.

Change-Id: I45cf507fe5300466519aafb0b920c8ae1d62ace0
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86340
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
---
 .../google/fatcat/variants/baseboard/fatcat/ramstage.c    | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/src/mainboard/google/fatcat/variants/baseboard/fatcat/ramstage.c b/src/mainboard/google/fatcat/variants/baseboard/fatcat/ramstage.c
index 969cd4a7c0..a808c90f00 100644
--- a/src/mainboard/google/fatcat/variants/baseboard/fatcat/ramstage.c
+++ b/src/mainboard/google/fatcat/variants/baseboard/fatcat/ramstage.c
@@ -10,7 +10,7 @@
 const struct cpu_tdp_power_limits power_optimized_limits[] = {
 	{
 		.mch_id = PCI_DID_INTEL_PTL_H_ID_1,
-		.cpu_tdp = 25,
+		.cpu_tdp = TDP_25W,
 		.power_limits_index = PTL_H_1_CORE,
 		.pl1_min_power = 10000,
 		.pl1_max_power = 25000,
@@ -20,7 +20,7 @@ const struct cpu_tdp_power_limits power_optimized_limits[] = {
 	},
 	{
 		.mch_id = PCI_DID_INTEL_PTL_H_ID_2,
-		.cpu_tdp = 25,
+		.cpu_tdp = TDP_25W,
 		.power_limits_index = PTL_H_1_CORE,
 		.pl1_min_power = 10000,
 		.pl1_max_power = 25000,
@@ -30,7 +30,7 @@ const struct cpu_tdp_power_limits power_optimized_limits[] = {
 	},
 	{
 		.mch_id = PCI_DID_INTEL_PTL_H_ID_3,
-		.cpu_tdp = 25,
+		.cpu_tdp = TDP_25W,
 		.power_limits_index = PTL_H_2_CORE,
 		.pl1_min_power = 10000,
 		.pl1_max_power = 25000,
@@ -40,7 +40,7 @@ const struct cpu_tdp_power_limits power_optimized_limits[] = {
 	},
 	{
 		.mch_id = PCI_DID_INTEL_PTL_H_ID_4,
-		.cpu_tdp = 25,
+		.cpu_tdp = TDP_25W,
 		.power_limits_index = PTL_H_2_CORE,
 		.pl1_min_power = 10000,
 		.pl1_max_power = 25000,

From 46f38d05d6c5d6dc3314723f8aef363707197bd5 Mon Sep 17 00:00:00 2001
From: Subrata Banik <subratabanik@google.com>
Date: Sun, 9 Feb 2025 07:53:42 +0000
Subject: [PATCH 0060/3886] ec/google/chromeec: Implement early power off

This commit implements the `google_chromeec_do_early_poweroff`
function for the Chrome EC. This allows the system to power
off before memory initialization by triggering an EC reset
with EC_REBOOT_COLD_AP_OFF.

BUG=b:339673254
TEST=Able to build and boot google/brox.

Change-Id: Ia53469feb2a020b38a5414728159b09c86c7e32d
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86337
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
---
 src/ec/google/chromeec/ec.c | 7 +++++++
 src/ec/google/chromeec/ec.h | 8 ++++++++
 2 files changed, 15 insertions(+)

diff --git a/src/ec/google/chromeec/ec.c b/src/ec/google/chromeec/ec.c
index 2e8961f5f2..cc581ffb7b 100644
--- a/src/ec/google/chromeec/ec.c
+++ b/src/ec/google/chromeec/ec.c
@@ -8,6 +8,7 @@
 #include <device/device.h>
 #include <device/path.h>
 #include <elog.h>
+#include <halt.h>
 #include <rtc.h>
 #include <security/vboot/vboot_common.h>
 #include <stdlib.h>
@@ -1669,3 +1670,9 @@ bool google_chromeec_is_battery_present(void)
 
 	return false;
 }
+
+void google_chromeec_do_early_poweroff(void)
+{
+	google_chromeec_reboot(EC_REBOOT_COLD_AP_OFF, 0);
+	halt();
+}
diff --git a/src/ec/google/chromeec/ec.h b/src/ec/google/chromeec/ec.h
index b11b7a834a..08d4f2771d 100644
--- a/src/ec/google/chromeec/ec.h
+++ b/src/ec/google/chromeec/ec.h
@@ -471,6 +471,14 @@ bool google_chromeec_is_below_critical_threshold(void);
  */
 bool google_chromeec_is_battery_present(void);
 
+/*
+ * Performs early power off.
+ *
+ * This function handles the necessary steps to initiate an early power off
+ * sequence.
+ */
+void google_chromeec_do_early_poweroff(void);
+
 /**
  * Determine if the UCSI stack is currently active.
  *

From a89c4624bdd2f212262ef79c092ba17a918fac7c Mon Sep 17 00:00:00 2001
From: John Su <john_su@compal.corp-partner.google.com>
Date: Tue, 11 Feb 2025 17:53:20 +0800
Subject: [PATCH 0061/3886] mb/trulo/var/uldrenite: Remove GPP_E13 from being
 used as RAM ID3

Remove GPP_E13 from being used as RAM ID3.
Planned to be used as a strap pin to disable memory channels
for x32 memory configuration.

BUG=b:379311559
BRANCH=firmware-trulo-15217.771.B
TEST=emerge-nissa coreboot chromeos-bootimage

Change-Id: I418f84255959452d5a63612ab703ec11d81f2e33
Signed-off-by: John Su <john_su@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86362
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/google/brya/variants/uldrenite/gpio.c   | 4 ++--
 src/mainboard/google/brya/variants/uldrenite/memory.c | 4 +---
 2 files changed, 3 insertions(+), 5 deletions(-)

diff --git a/src/mainboard/google/brya/variants/uldrenite/gpio.c b/src/mainboard/google/brya/variants/uldrenite/gpio.c
index 4b900fbbec..13bc2169e1 100644
--- a/src/mainboard/google/brya/variants/uldrenite/gpio.c
+++ b/src/mainboard/google/brya/variants/uldrenite/gpio.c
@@ -184,8 +184,8 @@ static const struct pad_config gpio_table[] = {
 	PAD_NC_LOCK(GPP_E11, NONE, LOCK_CONFIG),
 	/* E12 : THC0_SPI1_IO1 ==> RAM_ID2 */
 	PAD_CFG_GPI_LOCK(GPP_E12, NONE, LOCK_CONFIG),
-	/* E13 : NC ==> RAM_ID3 */
-	PAD_CFG_GPI_LOCK(GPP_E13, NONE, LOCK_CONFIG),
+	/* E13 : NC */
+	PAD_NC_LOCK(GPP_E13, NONE, LOCK_CONFIG),
 	/* E14 : DDSP_HPDA ==> EDP_HPD */
 	PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1),
 	/* E15 : NC */
diff --git a/src/mainboard/google/brya/variants/uldrenite/memory.c b/src/mainboard/google/brya/variants/uldrenite/memory.c
index 03e97a1906..9ade7c2013 100644
--- a/src/mainboard/google/brya/variants/uldrenite/memory.c
+++ b/src/mainboard/google/brya/variants/uldrenite/memory.c
@@ -81,13 +81,11 @@ int variant_memory_sku(void)
 	 * GPIO_MEM_CONFIG_0	GPP_E2
 	 * GPIO_MEM_CONFIG_1	GPP_E1
 	 * GPIO_MEM_CONFIG_2	GPP_E12
-	 * GPIO_MEM_CONFIG_3	GPP_E13
 	 */
 	gpio_t spd_gpios[] = {
 		GPP_E2,
 		GPP_E1,
-		GPP_E12,
-		GPP_E13
+		GPP_E12
 	};
 
 	return gpio_base2_value(spd_gpios, ARRAY_SIZE(spd_gpios));

From b6c02d660c1293eddc88017a9ee360e55280ff9f Mon Sep 17 00:00:00 2001
From: John Su <john_su@compal.corp-partner.google.com>
Date: Tue, 11 Feb 2025 18:13:30 +0800
Subject: [PATCH 0062/3886] mb/trulo/var/uldrenite: Support x32 memory
 configuration

Use the GPP_E13 level to determine whether x32 memory configuration
is supported.

BUG=b:379311559
BRANCH=firmware-trulo-15217.771.B
TEST=emerge-nissa coreboot chromeos-bootimage

Change-Id: Idd3534bba0379a7bb06f8fbbeb9469e938e5a629
Signed-off-by: John Su <john_su@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86364
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
---
 src/mainboard/google/brya/Kconfig                  |  1 +
 .../google/brya/variants/uldrenite/gpio.c          |  6 ++++--
 .../google/brya/variants/uldrenite/memory.c        | 14 ++++++++++++++
 3 files changed, 19 insertions(+), 2 deletions(-)

diff --git a/src/mainboard/google/brya/Kconfig b/src/mainboard/google/brya/Kconfig
index 58b8922448..8d09f2e562 100644
--- a/src/mainboard/google/brya/Kconfig
+++ b/src/mainboard/google/brya/Kconfig
@@ -644,6 +644,7 @@ config BOARD_GOOGLE_ULDRENITE
 	select HAVE_WWAN_POWER_SEQUENCE
 	select DRIVERS_WWAN_FM350GL
 	select SOC_INTEL_COMMON_BLOCK_HDA_VERB
+	select ENFORCE_MEM_CHANNEL_DISABLE
 
 config BOARD_GOOGLE_VELL
 	select BOARD_GOOGLE_BASEBOARD_BRYA
diff --git a/src/mainboard/google/brya/variants/uldrenite/gpio.c b/src/mainboard/google/brya/variants/uldrenite/gpio.c
index 13bc2169e1..f926e3ac47 100644
--- a/src/mainboard/google/brya/variants/uldrenite/gpio.c
+++ b/src/mainboard/google/brya/variants/uldrenite/gpio.c
@@ -184,8 +184,8 @@ static const struct pad_config gpio_table[] = {
 	PAD_NC_LOCK(GPP_E11, NONE, LOCK_CONFIG),
 	/* E12 : THC0_SPI1_IO1 ==> RAM_ID2 */
 	PAD_CFG_GPI_LOCK(GPP_E12, NONE, LOCK_CONFIG),
-	/* E13 : NC */
-	PAD_NC_LOCK(GPP_E13, NONE, LOCK_CONFIG),
+	/* E13 : NC ==> GPP_E13_STRAP */
+	PAD_CFG_GPI_LOCK(GPP_E13, NONE, LOCK_CONFIG),
 	/* E14 : DDSP_HPDA ==> EDP_HPD */
 	PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1),
 	/* E15 : NC */
@@ -418,6 +418,8 @@ static const struct pad_config early_gpio_table[] = {
 	PAD_CFG_GPI_APIC(GPP_A17, NONE, PLTRST, LEVEL, INVERT),
 	/* E3 : PROC_GP0 ==> SOC_WP_OD */
 	PAD_CFG_GPI_GPIO_DRIVER(GPP_E3, NONE, DEEP),
+	/* E13 : NC ==> GPP_E13_STRAP */
+	PAD_CFG_GPI_LOCK(GPP_E13, NONE, LOCK_CONFIG),
 	/* F12 : NC ==> WWAN_RST_L */
 	PAD_CFG_GPO(GPP_F12, 0, DEEP),
 	/* F13 : NC ==> PLTRST_WWAN# */
diff --git a/src/mainboard/google/brya/variants/uldrenite/memory.c b/src/mainboard/google/brya/variants/uldrenite/memory.c
index 9ade7c2013..372355a05c 100644
--- a/src/mainboard/google/brya/variants/uldrenite/memory.c
+++ b/src/mainboard/google/brya/variants/uldrenite/memory.c
@@ -3,6 +3,7 @@
 #include <baseboard/variants.h>
 #include <gpio.h>
 #include <soc/romstage.h>
+#include <soc/meminit.h>
 
 static const struct mb_cfg variant_memcfg = {
 	.type = MEM_TYPE_LP5X,
@@ -109,3 +110,16 @@ void variant_get_spd_info(struct mem_spd *spd_info)
 	spd_info->topo = MEM_TOPO_MEMORY_DOWN;
 	spd_info->cbfs_index = variant_memory_sku();
 }
+
+uint8_t mb_get_channel_disable_mask(void)
+{
+	/*
+	 * GPP_E13 High -> One RAM Chip
+	 * GPP_E13 Low  -> Two RAM Chip
+	 */
+	if (gpio_get(GPP_E13)) {
+		/* Disable all other channels except first two on each controller */
+		return (BIT(2) | BIT(3));
+	}
+	return 0;
+}

From f21969acb25b0587ded2a859c31c539fe65a12e4 Mon Sep 17 00:00:00 2001
From: Lu Tang <lu.tang@mediatek.corp-partner.google.com>
Date: Tue, 11 Feb 2025 17:36:52 +0800
Subject: [PATCH 0063/3886] soc/mediatek/mt8196: Set MT6316 deglitch time from
 2ns to 4ns

To fix the SPMI-P glitch, set the mt6316 deglitch time from 2ns to 4ns.
Additionally, a hardware solution of SPMI damping to 0 ohm is needed.

BRANCH=rauru
TEST=Build passed and booted successfully. 10 platforms have passed CPU
stress tests over multiple iterations.
BUG=b:386438329

Signed-off-by: Lu Tang <lu.tang@mediatek.corp-partner.google.com>
Change-Id: I77bd50cc6c25d6dcded57d9d65d92a0dd19c3c86
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86371
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Knox Chiou <knoxchiou@google.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
---
 src/soc/mediatek/common/include/soc/mt6316.h | 1 +
 src/soc/mediatek/common/mt6316.c             | 9 +++++++++
 2 files changed, 10 insertions(+)

diff --git a/src/soc/mediatek/common/include/soc/mt6316.h b/src/soc/mediatek/common/include/soc/mt6316.h
index 920cb34af9..ce955f94e3 100644
--- a/src/soc/mediatek/common/include/soc/mt6316.h
+++ b/src/soc/mediatek/common/include/soc/mt6316.h
@@ -29,6 +29,7 @@ enum {
 	MT6316_PMIC_TEST_CON9		= 0x222,
 	MT6316_PMIC_PLT_DIG_WPK		= 0x3B1,
 	MT6316_PMIC_PLT_DIG_WPK_H	= 0x3B2,
+	MT6316_PMIC_SPMI_RSV1		= 0x43A,
 	MT6316_BUCK_TOP_ELR0		= 0x1448,
 	MT6316_BUCK_TOP_ELR1		= 0x1449,
 	MT6316_BUCK_TOP_ELR2		= 0x144A,
diff --git a/src/soc/mediatek/common/mt6316.c b/src/soc/mediatek/common/mt6316.c
index 89c8c83cb0..9ed5d29c21 100644
--- a/src/soc/mediatek/common/mt6316.c
+++ b/src/soc/mediatek/common/mt6316.c
@@ -169,6 +169,14 @@ static void mt6316_set_all_test_con9(void)
 		mt6316_write8(mt6316_slave_id[i], MT6316_PMIC_TEST_CON9, 0x20);
 }
 
+static void mt6316_set_all_deglitch(void)
+{
+	/* Set deglitch time from 2ns to 4ns */
+	for (int i = 0; i < ARRAY_SIZE(mt6316_slave_id); i++)
+		mt6316_write_field(mt6316_slave_id[i],
+				   MT6316_PMIC_SPMI_RSV1, 0x0A, 0xFF, 0);
+}
+
 static void init_pmif_arb(void)
 {
 	if (pmif_arb)
@@ -196,4 +204,5 @@ void mt6316_init(void)
 
 	mt6316_init_setting();
 	mt6316_set_all_test_con9();
+	mt6316_set_all_deglitch();
 }

From 15df34c16d7e6e48f7038530fa24f60295baa81a Mon Sep 17 00:00:00 2001
From: Patrick Rudolph <patrick.rudolph@9elements.com>
Date: Mon, 27 Jan 2025 17:04:14 +0100
Subject: [PATCH 0064/3886] mb/amd/birman_plus: Add SMMSTORE to FMAP

Add the SMMSTORE region to the default FMAP to allow
building for EDK2 as payload.

TEST: Still boots on AMD/Birman+

Change-Id: I661fcc55bf30aa6f1f3cc8a57e6d0eaf2fed4621
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86177
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/amd/birman_plus/board_glinda.fmd | 1 +
 1 file changed, 1 insertion(+)

diff --git a/src/mainboard/amd/birman_plus/board_glinda.fmd b/src/mainboard/amd/birman_plus/board_glinda.fmd
index 756709044e..17673b5156 100644
--- a/src/mainboard/amd/birman_plus/board_glinda.fmd
+++ b/src/mainboard/amd/birman_plus/board_glinda.fmd
@@ -3,6 +3,7 @@ FLASH@0xFF000000 16M {
 		EC_SIG 4K
 		FMAP 4K
 		COREBOOT(CBFS)
+		SMMSTORE(PRESERVE) 256K
 		EC_BODY@15872K 256K
 		RW_MRC_CACHE 120K
 	}

From 03b5a4160adc9de57ea78605838e715e8287a09c Mon Sep 17 00:00:00 2001
From: Patrick Rudolph <patrick.rudolph@9elements.com>
Date: Tue, 28 Jan 2025 09:17:24 +0100
Subject: [PATCH 0065/3886] mb/amd/birman_plus: Use actual flash size of 64 MiB
 instead of 16 MiB

Birman+ has a 64MiB flash chip.

Update the mainboards Kconfig comment and fix the FMD to generate a
64MiB ROM. Until now only the first 16MiB are being used.

TEST: Still boots on AMD/Birman+

Change-Id: I72e3dcb0c3a308c3b0fd981b56cc7c1ef60095cc
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86179
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/amd/birman_plus/Kconfig          | 2 +-
 src/mainboard/amd/birman_plus/board_glinda.fmd | 4 ++--
 2 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/src/mainboard/amd/birman_plus/Kconfig b/src/mainboard/amd/birman_plus/Kconfig
index 02f3f23c68..9794383360 100644
--- a/src/mainboard/amd/birman_plus/Kconfig
+++ b/src/mainboard/amd/birman_plus/Kconfig
@@ -2,7 +2,7 @@
 
 config BOARD_AMD_BIRMANPLUS_COMMON
 	def_bool n
-	select BOARD_ROMSIZE_KB_16384	# Birman actually has a 32MiB ROM
+	select BOARD_ROMSIZE_KB_16384   # Birman+ actually has a 64MiB ROM
 	select EC_ACPI
 	select SOC_AMD_COMMON_BLOCK_USE_ESPI if !SOC_AMD_COMMON_BLOCK_SIMNOW_BUILD
 	select DRIVERS_PCIE_RTD3_DEVICE
diff --git a/src/mainboard/amd/birman_plus/board_glinda.fmd b/src/mainboard/amd/birman_plus/board_glinda.fmd
index 17673b5156..b9465768be 100644
--- a/src/mainboard/amd/birman_plus/board_glinda.fmd
+++ b/src/mainboard/amd/birman_plus/board_glinda.fmd
@@ -1,5 +1,5 @@
-FLASH@0xFF000000 16M {
-	BIOS {
+FLASH 64M {
+	BIOS 16M {
 		EC_SIG 4K
 		FMAP 4K
 		COREBOOT(CBFS)

From 74efa4e3968ceeeea58602e9de3d34e1df5dae1d Mon Sep 17 00:00:00 2001
From: Jarried Lin <jarried.lin@mediatek.corp-partner.google.com>
Date: Thu, 13 Feb 2025 13:32:03 +0800
Subject: [PATCH 0066/3886] mb/google/rauru: Correct GPIO name for BEEP_ON

Rename GPIO_BEEP_ON_OD to GPIO_BEEP_ON to match the schematics.

BRANCH=rauru
TEST=Build pass
BUG=b:317009620

Change-Id: Ica48ed4f4e2cd6a159203ba1f8c17ac371a08f87
Signed-off-by: Jarried Lin <jarried.lin@mediatek.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86391
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
---
 src/mainboard/google/rauru/chromeos.c | 4 ++--
 src/mainboard/google/rauru/gpio.h     | 2 +-
 2 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/src/mainboard/google/rauru/chromeos.c b/src/mainboard/google/rauru/chromeos.c
index 6a8431fc6d..b7844b7afb 100644
--- a/src/mainboard/google/rauru/chromeos.c
+++ b/src/mainboard/google/rauru/chromeos.c
@@ -14,7 +14,7 @@ void setup_chromeos_gpios(void)
 	gpio_input(GPIO_SD_CD_AP_ODL);
 	gpio_output(GPIO_AP_EC_WARM_RST_REQ, 0);
 	gpio_output(GPIO_AP_FP_FW_UP_STRAP, 0);
-	gpio_output(GPIO_BEEP_ON_OD, 0);
+	gpio_output(GPIO_BEEP_ON, 0);
 	gpio_output(GPIO_EN_PWR_FP, 0);
 	gpio_output(GPIO_EN_SPKR, 0);
 	gpio_output(GPIO_FP_RST_1V8_S3_L, 0);
@@ -39,7 +39,7 @@ void fill_lb_gpios(struct lb_gpios *gpios)
 
 	struct lb_gpio nau8318_gpios[] = {
 		{GPIO_EN_SPKR.id, ACTIVE_HIGH, -1, "speaker enable"},
-		{GPIO_BEEP_ON_OD.id, ACTIVE_HIGH, -1, "beep enable"},
+		{GPIO_BEEP_ON.id, ACTIVE_HIGH, -1, "beep enable"},
 	};
 
 	struct lb_gpio smartamp_gpios[] = {
diff --git a/src/mainboard/google/rauru/gpio.h b/src/mainboard/google/rauru/gpio.h
index f35135c484..fd15463a7a 100644
--- a/src/mainboard/google/rauru/gpio.h
+++ b/src/mainboard/google/rauru/gpio.h
@@ -5,7 +5,7 @@
 
 #include <soc/gpio.h>
 
-#define GPIO_BEEP_ON_OD		GPIO(PERIPHERAL_EN1)
+#define GPIO_BEEP_ON		GPIO(PERIPHERAL_EN1)
 #define GPIO_EN_SPKR		GPIO(PERIPHERAL_EN0)
 #define GPIO_SD_CD_AP_ODL	GPIO(EINT11)
 #define GPIO_GSC_AP_INT_ODL	GPIO(EINT18)

From 93b70934bc97cae82dbbe37577c57154e2f61f4c Mon Sep 17 00:00:00 2001
From: Wenzhen Yu <wenzhen.yu@mediatek.com>
Date: Wed, 12 Feb 2025 17:37:44 +0800
Subject: [PATCH 0067/3886] mb/google/rauru: Notify EC that AP is in S0

GPIO_AP_SUSPEND_L is supposed to be high in S0, and low in S3. EC uses
this pin to determine the AP power state. This pin should be set as
early as possible in bootblock.

BRANCH=rauru
TEST=Build pass, reboot pass, suspend/resume pass.
BUG=b:395737458

Signed-off-by: Wenzhen Yu <wenzhen.yu@mediatek.com>
Change-Id: I6ea56208256bb6f11fb6b0adf7627403963295bc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86381
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
---
 src/mainboard/google/rauru/chromeos.c | 1 +
 src/mainboard/google/rauru/gpio.h     | 1 +
 2 files changed, 2 insertions(+)

diff --git a/src/mainboard/google/rauru/chromeos.c b/src/mainboard/google/rauru/chromeos.c
index b7844b7afb..5196fbe87a 100644
--- a/src/mainboard/google/rauru/chromeos.c
+++ b/src/mainboard/google/rauru/chromeos.c
@@ -19,6 +19,7 @@ void setup_chromeos_gpios(void)
 	gpio_output(GPIO_EN_SPKR, 0);
 	gpio_output(GPIO_FP_RST_1V8_S3_L, 0);
 	gpio_output(GPIO_XHCI_INIT_DONE, 0);
+	gpio_output(GPIO_AP_SUSPEND_L, 1);
 }
 
 void fill_lb_gpios(struct lb_gpios *gpios)
diff --git a/src/mainboard/google/rauru/gpio.h b/src/mainboard/google/rauru/gpio.h
index fd15463a7a..bdbfc2b6ef 100644
--- a/src/mainboard/google/rauru/gpio.h
+++ b/src/mainboard/google/rauru/gpio.h
@@ -14,6 +14,7 @@
 #define GPIO_AP_EC_WARM_RST_REQ GPIO(EINT29)
 #define GPIO_FP_RST_1V8_S3_L	GPIO(EINT26)
 #define GPIO_AP_FP_FW_UP_STRAP	GPIO(EINT27)
+#define GPIO_AP_SUSPEND_L	GPIO(EINT38)
 #define GPIO_EN_PWR_FP		GPIO(PERIPHERAL_EN3)
 #define GPIO_BL_PWM_1V8		GPIO(DISP_PWM)
 

From f48b4d16ca39ce24a94106cdef6abe869495b735 Mon Sep 17 00:00:00 2001
From: Yu-Ping Wu <yupingso@chromium.org>
Date: Thu, 13 Feb 2025 15:50:28 +0800
Subject: [PATCH 0068/3886] mb/google/rauru: Set up open-drain ChromeOS pins

Set open-drain GPIOs for ChromeOS as input and bias-disable mode.
After applying this patch, the voltage of these pins will become the
expected value 1.8V (previously 1.0V), preventing wrong judgement of
low/high.

BUG=b:396106564
TEST=emerge-rauru coreboot
BRANCH=rauru

Change-Id: I76c7931a56540a395eaf934125bded7fede84992
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86398
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
---
 src/mainboard/google/rauru/chromeos.c | 32 +++++++++++++++++++++++++--
 src/mainboard/google/rauru/gpio.h     | 32 ++++++++++++++++++++++++---
 2 files changed, 59 insertions(+), 5 deletions(-)

diff --git a/src/mainboard/google/rauru/chromeos.c b/src/mainboard/google/rauru/chromeos.c
index 5196fbe87a..33316393ac 100644
--- a/src/mainboard/google/rauru/chromeos.c
+++ b/src/mainboard/google/rauru/chromeos.c
@@ -9,9 +9,37 @@
 
 void setup_chromeos_gpios(void)
 {
-	gpio_input(GPIO_EC_AP_INT_ODL);
-	gpio_input(GPIO_GSC_AP_INT_ODL);
+	/* Set up open-drain pins */
+	gpio_input(GPIO_RSVD_GPI0);
+	gpio_input(GPIO_EC_AP_DSI_HPD_OD);
+	gpio_input(GPIO_RSVD_GPI2);
+	gpio_input(GPIO_AP_WP_ODL);
+	gpio_input(GPIO_ALS_INT_SCP_ODL);
+	gpio_input(GPIO_LID_ACCEL_INT_SCP_L);
+	gpio_input(GPIO_IMU_INT_SCP_L);
+	gpio_input(GPIO_TCHSCR_INT_1V8_ODL);
+	gpio_input(GPIO_TCHPAD_INT_ODL);
+	gpio_input(GPIO_SPKR_INT_ODL);
+	gpio_input(GPIO_HP_INT_ODL);
 	gpio_input(GPIO_SD_CD_AP_ODL);
+	gpio_input(GPIO_FP_AP_INT_1V8_S3_ODL);
+	gpio_input(GPIO_EDP_HPD_1V8);
+	gpio_input(GPIO_SAR_INT_ODL);
+	gpio_input(GPIO_RSVD_GPI15);
+	gpio_input(GPIO_RSVD_GPI16);
+	gpio_input(GPIO_RSVD_GPI17);
+	gpio_input(GPIO_GSC_AP_INT_ODL);
+	gpio_input(GPIO_EC_AP_INT_ODL);
+	gpio_input(GPIO_RSVD_GPI20);
+	gpio_input(GPIO_RSVD_GPI21);
+	gpio_input(GPIO_RSVD_GPI22);
+	gpio_input(GPIO_EC_AP_DP_HPD_OD);
+	gpio_input(GPIO_PCIE_SSD_WAKE_OBFF_1V8_ODL);
+	gpio_input(GPIO_PCIE_SSD_CLKREQ_1V8_ODL);
+	gpio_input(GPIO_PCIE_WLAN_WAKE_OBFF_1V2_ODL);
+	gpio_input(GPIO_PCIE_WLAN_CLKREQ_1V2_ODL);
+
+	/* Set up GPIOs */
 	gpio_output(GPIO_AP_EC_WARM_RST_REQ, 0);
 	gpio_output(GPIO_AP_FP_FW_UP_STRAP, 0);
 	gpio_output(GPIO_BEEP_ON, 0);
diff --git a/src/mainboard/google/rauru/gpio.h b/src/mainboard/google/rauru/gpio.h
index bdbfc2b6ef..ed7ec89123 100644
--- a/src/mainboard/google/rauru/gpio.h
+++ b/src/mainboard/google/rauru/gpio.h
@@ -5,11 +5,37 @@
 
 #include <soc/gpio.h>
 
+#define GPIO_RSVD_GPI0			GPIO(EINT0)
+#define GPIO_EC_AP_DSI_HPD_OD		GPIO(EINT1)
+#define GPIO_RSVD_GPI2			GPIO(EINT2)
+#define GPIO_AP_WP_ODL			GPIO(EINT3)
+#define GPIO_ALS_INT_SCP_ODL		GPIO(EINT4)
+#define GPIO_LID_ACCEL_INT_SCP_L	GPIO(EINT5)
+#define GPIO_IMU_INT_SCP_L		GPIO(EINT6)
+#define GPIO_TCHSCR_INT_1V8_ODL		GPIO(EINT7)
+#define GPIO_TCHPAD_INT_ODL		GPIO(EINT8)
+#define GPIO_SPKR_INT_ODL		GPIO(EINT9)
+#define GPIO_HP_INT_ODL			GPIO(EINT10)
+#define GPIO_SD_CD_AP_ODL		GPIO(EINT11)
+#define GPIO_FP_AP_INT_1V8_S3_ODL	GPIO(EINT12)
+#define GPIO_EDP_HPD_1V8		GPIO(EINT13)
+#define GPIO_SAR_INT_ODL		GPIO(EINT14)
+#define GPIO_RSVD_GPI15			GPIO(EINT15)
+#define GPIO_RSVD_GPI16			GPIO(EINT16)
+#define GPIO_RSVD_GPI17			GPIO(EINT17)
+#define GPIO_GSC_AP_INT_ODL		GPIO(EINT18)
+#define GPIO_EC_AP_INT_ODL		GPIO(EINT19)
+#define GPIO_RSVD_GPI20			GPIO(EINT20)
+#define GPIO_RSVD_GPI21			GPIO(EINT21)
+#define GPIO_RSVD_GPI22			GPIO(EINT22)
+#define GPIO_EC_AP_DP_HPD_OD		GPIO(EINT32)
+#define GPIO_PCIE_SSD_WAKE_OBFF_1V8_ODL		GPIO(BPI_D_BUS0)
+#define GPIO_PCIE_SSD_CLKREQ_1V8_ODL		GPIO(BPI_D_BUS2)
+#define GPIO_PCIE_WLAN_WAKE_OBFF_1V2_ODL	GPIO(PCIE0_WAKEN)
+#define GPIO_PCIE_WLAN_CLKREQ_1V2_ODL		GPIO(PCIE0_CLKREQN)
+
 #define GPIO_BEEP_ON		GPIO(PERIPHERAL_EN1)
 #define GPIO_EN_SPKR		GPIO(PERIPHERAL_EN0)
-#define GPIO_SD_CD_AP_ODL	GPIO(EINT11)
-#define GPIO_GSC_AP_INT_ODL	GPIO(EINT18)
-#define GPIO_EC_AP_INT_ODL	GPIO(EINT19)
 #define GPIO_XHCI_INIT_DONE	GPIO(EINT28)
 #define GPIO_AP_EC_WARM_RST_REQ GPIO(EINT29)
 #define GPIO_FP_RST_1V8_S3_L	GPIO(EINT26)

From 7da6c68eed14fb84af2f93e3fa5dc3bef602cb82 Mon Sep 17 00:00:00 2001
From: Patrick Rudolph <patrick.rudolph@9elements.com>
Date: Thu, 6 Feb 2025 09:34:20 +0100
Subject: [PATCH 0069/3886] soc/amd/common/block/graphics: Use vbt_get()
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Implement vbt_get() on AMD and return the VBIOS location. This allows
to drop the hardcoded addresses used in various places and return an
address in DRAM that is reserved for FSP use.

TEST: amd/birman+ still gets passed the correct VBIOS address.

Change-Id: I92d76fc4df88fbce792b9d7c912c6799617704a0
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86299
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ana Carolina Cabral <ana.cpmelo95@gmail.com>
---
 src/drivers/intel/fsp2_0/silicon_init.c       |  5 ++++
 src/soc/amd/cezanne/fsp_s_params.c            |  3 ++-
 src/soc/amd/common/block/graphics/graphics.c  | 24 +++++++------------
 .../amd/common/block/include/amdblocks/vbt.h  | 22 +++++++++++++++++
 src/soc/amd/glinda/fsp_s_params.c             |  3 ++-
 src/soc/amd/mendocino/fsp_s_params.c          |  3 ++-
 src/soc/amd/phoenix/fsp_s_params.c            |  3 ++-
 src/soc/amd/picasso/fsp_s_params.c            |  3 ++-
 8 files changed, 46 insertions(+), 20 deletions(-)
 create mode 100644 src/soc/amd/common/block/include/amdblocks/vbt.h

diff --git a/src/drivers/intel/fsp2_0/silicon_init.c b/src/drivers/intel/fsp2_0/silicon_init.c
index 1caf00ff73..fdac9f5b85 100644
--- a/src/drivers/intel/fsp2_0/silicon_init.c
+++ b/src/drivers/intel/fsp2_0/silicon_init.c
@@ -14,7 +14,12 @@
 #include <mrc_cache.h>
 #include <program_loading.h>
 #include <soc/intel/common/reset.h>
+#if CONFIG(SOC_AMD_COMMON)
+#include <amdblocks/vbt.h>
+#endif
+#if CONFIG(SOC_INTEL_COMMON)
 #include <soc/intel/common/vbt.h>
+#endif
 #include <stage_cache.h>
 #include <string.h>
 #include <timestamp.h>
diff --git a/src/soc/amd/cezanne/fsp_s_params.c b/src/soc/amd/cezanne/fsp_s_params.c
index b9770f3ef5..391461e2f7 100644
--- a/src/soc/amd/cezanne/fsp_s_params.c
+++ b/src/soc/amd/cezanne/fsp_s_params.c
@@ -2,6 +2,7 @@
 
 #include <acpi/acpi.h>
 #include <amdblocks/apob_cache.h>
+#include <amdblocks/vbt.h>
 #include <device/pci.h>
 #include <fsp/api.h>
 #include <program_loading.h>
@@ -13,7 +14,7 @@ static void fsp_assign_vbios_upds(FSP_S_CONFIG *scfg)
 	 * part of FSP GOP init. We can delay loading of the VBIOS until
 	 * before FSP notify AFTER_PCI_ENUM.
 	 */
-	scfg->vbios_buffer = CONFIG(RUN_FSP_GOP) ? PCI_VGA_RAM_IMAGE_START : 0;
+	scfg->vbios_buffer = (uintptr_t)vbt_get();
 }
 
 void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
diff --git a/src/soc/amd/common/block/graphics/graphics.c b/src/soc/amd/common/block/graphics/graphics.c
index 77420aebaa..f80484da8f 100644
--- a/src/soc/amd/common/block/graphics/graphics.c
+++ b/src/soc/amd/common/block/graphics/graphics.c
@@ -4,6 +4,7 @@
 #include <acpi/acpigen.h>
 #include <amdblocks/graphics.h>
 #include <amdblocks/vbios_cache.h>
+#include <amdblocks/vbt.h>
 #include <boot/coreboot_tables.h>
 #include <bootmode.h>
 #include <bootstate.h>
@@ -12,7 +13,6 @@
 #include <device/pci.h>
 #include <fmap.h>
 #include <security/vboot/vbios_cache_hash_tpm.h>
-#include <soc/intel/common/vbt.h>
 #include <timestamp.h>
 
 static bool vbios_loaded_from_cache = false;
@@ -146,17 +146,11 @@ static const char *graphics_acpi_name(const struct device *dev)
 	return "IGFX";
 }
 
-/*
- * On AMD platforms the VBT is called ATOMBIOS and is always part of the
- * VGA Option ROM. As part of the FSP GOP init the ATOMBIOS tables are
- * updated in place. Thus the VBIOS must be loaded into RAM before FSP GOP
- * runs. The address of the VBIOS must be passed to FSP-S using UPDs, but
- * loading of the VBIOS can be delayed until before FSP AFTER_PCI_ENUM
- * notify is called. FSP expects a pointer to the PCI option rom instead
- * a pointer to the ATOMBIOS table directly.
- */
 void *vbt_get(void)
 {
+	if (CONFIG(RUN_FSP_GOP))
+		return (void *)(uintptr_t)PCI_VGA_RAM_IMAGE_START;
+
 	return NULL;
 }
 
@@ -259,12 +253,12 @@ static void write_vbios_cache_to_fmap(void *unused)
 	}
 
 	/* copy from PCI_VGA_RAM_IMAGE_START to rdev */
-	if (rdev_writeat(&rw_vbios_cache, (void *)PCI_VGA_RAM_IMAGE_START, 0,
+	if (rdev_writeat(&rw_vbios_cache, vbt_get(), 0,
 						VBIOS_CACHE_FMAP_SIZE) != VBIOS_CACHE_FMAP_SIZE)
 		printk(BIOS_ERR, "Failed to save vbios data to flash; rdev_writeat() failed.\n");
 
-	/* copy modified vbios data from PCI_VGA_RAM_IMAGE_START to buffer before hashing */
-	memcpy(vbios_data, (void *)PCI_VGA_RAM_IMAGE_START, VBIOS_CACHE_FMAP_SIZE);
+	/* copy modified vbios data to buffer before hashing */
+	memcpy(vbios_data, vbt_get(), VBIOS_CACHE_FMAP_SIZE);
 
 	/* save data hash to TPM NVRAM for validation on subsequent boots */
 	vbios_cache_update_hash(vbios_data, VBIOS_CACHE_FMAP_SIZE);
@@ -279,8 +273,8 @@ static void write_vbios_cache_to_fmap(void *unused)
  */
 void vbios_load_from_cache(void)
 {
-	/* copy cached vbios data from buffer to PCI_VGA_RAM_IMAGE_START */
-	memcpy((void *)PCI_VGA_RAM_IMAGE_START, vbios_data, VBIOS_CACHE_FMAP_SIZE);
+	/* copy cached vbios data from buffer to address used by FSP */
+	memcpy(vbt_get(), vbios_data, VBIOS_CACHE_FMAP_SIZE);
 
 	/* mark cache as used so we know not to write it later */
 	vbios_loaded_from_cache = true;
diff --git a/src/soc/amd/common/block/include/amdblocks/vbt.h b/src/soc/amd/common/block/include/amdblocks/vbt.h
new file mode 100644
index 0000000000..05fc5e3433
--- /dev/null
+++ b/src/soc/amd/common/block/include/amdblocks/vbt.h
@@ -0,0 +1,22 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef _AMD_BLOCK_VBT_H_
+#define _AMD_BLOCK_VBT_H_
+
+/*
+ * On AMD platforms the VBT is called ATOMBIOS and is always part of the
+ * VGA Option ROM. As part of the FSP GOP init the ATOMBIOS tables are
+ * updated in place. Thus the VBIOS must be loaded into RAM before FSP GOP
+ * runs. The address of the VBIOS must be passed to FSP-S using UPDs, but
+ * loading of the VBIOS can be delayed until before FSP AFTER_PCI_ENUM
+ * notify is called. FSP expects a pointer to the PCI Option Rom instead of
+ * a pointer to the ATOMBIOS table directly.
+ *
+ * Returns a pointer to the VGA Option ROM in DRAM after checking
+ * prerequisites for Pre OS Graphics initialization. When returning
+ * non NULL the Option ROM might not be loaded at this address yet,
+ * but is guaranteed to be present at end of BS_DEV_RESOURCES phase.
+ */
+void *vbt_get(void);
+
+#endif
diff --git a/src/soc/amd/glinda/fsp_s_params.c b/src/soc/amd/glinda/fsp_s_params.c
index e03795792d..980eea8367 100644
--- a/src/soc/amd/glinda/fsp_s_params.c
+++ b/src/soc/amd/glinda/fsp_s_params.c
@@ -4,6 +4,7 @@
 
 #include <acpi/acpi.h>
 #include <amdblocks/apob_cache.h>
+#include <amdblocks/vbt.h>
 #include <device/pci.h>
 #include <fsp/api.h>
 #include <program_loading.h>
@@ -15,7 +16,7 @@ static void fsp_assign_vbios_upds(FSP_S_CONFIG *scfg)
 	 * part of FSP GOP init. We can delay loading of the VBIOS until
 	 * before FSP notify AFTER_PCI_ENUM.
 	 */
-	scfg->vbios_buffer = CONFIG(RUN_FSP_GOP) ? PCI_VGA_RAM_IMAGE_START : 0;
+	scfg->vbios_buffer = (uintptr_t)vbt_get();
 }
 
 void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
diff --git a/src/soc/amd/mendocino/fsp_s_params.c b/src/soc/amd/mendocino/fsp_s_params.c
index 5c37334f5a..5393eba911 100644
--- a/src/soc/amd/mendocino/fsp_s_params.c
+++ b/src/soc/amd/mendocino/fsp_s_params.c
@@ -5,6 +5,7 @@
 #include <acpi/acpi.h>
 #include <amdblocks/apob_cache.h>
 #include <amdblocks/vbios_cache.h>
+#include <amdblocks/vbt.h>
 #include <bootmode.h>
 #include <bootsplash.h>
 #include <console/console.h>
@@ -26,7 +27,7 @@ static void fsp_assign_vbios_upds(FSP_S_CONFIG *scfg)
 	 * before FSP notify AFTER_PCI_ENUM.
 	 */
 	printk(BIOS_SPEW, "%s: not using VBIOS cache; running GOP driver.\n", __func__);
-	scfg->vbios_buffer = CONFIG(RUN_FSP_GOP) ? PCI_VGA_RAM_IMAGE_START : 0;
+	scfg->vbios_buffer = (uintptr_t)vbt_get();
 }
 
 void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
diff --git a/src/soc/amd/phoenix/fsp_s_params.c b/src/soc/amd/phoenix/fsp_s_params.c
index 883cde0f89..9ce09f807f 100644
--- a/src/soc/amd/phoenix/fsp_s_params.c
+++ b/src/soc/amd/phoenix/fsp_s_params.c
@@ -4,6 +4,7 @@
 
 #include <acpi/acpi.h>
 #include <amdblocks/apob_cache.h>
+#include <amdblocks/vbt.h>
 #include <device/pci.h>
 #include <fsp/api.h>
 #include <program_loading.h>
@@ -15,7 +16,7 @@ static void fsp_assign_vbios_upds(FSP_S_CONFIG *scfg)
 	 * part of FSP GOP init. We can delay loading of the VBIOS until
 	 * before FSP notify AFTER_PCI_ENUM.
 	 */
-	scfg->vbios_buffer = CONFIG(RUN_FSP_GOP) ? PCI_VGA_RAM_IMAGE_START : 0;
+	scfg->vbios_buffer = (uintptr_t)vbt_get();
 }
 
 void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
diff --git a/src/soc/amd/picasso/fsp_s_params.c b/src/soc/amd/picasso/fsp_s_params.c
index d4cfa276c1..fd6f81767d 100644
--- a/src/soc/amd/picasso/fsp_s_params.c
+++ b/src/soc/amd/picasso/fsp_s_params.c
@@ -2,6 +2,7 @@
 
 #include <assert.h>
 #include <amdblocks/ioapic.h>
+#include <amdblocks/vbt.h>
 #include <device/pci.h>
 #include <soc/iomap.h>
 #include <soc/pci_devs.h>
@@ -190,7 +191,7 @@ static void fsp_assign_vbios_upds(FSP_S_CONFIG *scfg)
 	 * part of FSP GOP init. We can delay loading of the VBIOS until
 	 * before FSP notify AFTER_PCI_ENUM.
 	 */
-	scfg->vbios_buffer_addr = CONFIG(RUN_FSP_GOP) ? PCI_VGA_RAM_IMAGE_START : 0;
+	scfg->vbios_buffer_addr = (uintptr_t)vbt_get();
 }
 
 void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)

From 33f6375ca534747a50a6ca0f3958acbf6df50f44 Mon Sep 17 00:00:00 2001
From: Patrick Rudolph <patrick.rudolph@9elements.com>
Date: Thu, 6 Feb 2025 11:21:08 +0100
Subject: [PATCH 0070/3886] soc/amd/common/block/graphics: Support non VGA IGDs

On glinda the IGD is no longer VGA compatible. It doesn't
advertise itself as a VGA compatible devices and doesn't decode
the legacy VGA ranges 0x3C0-0x3CF, 0x3D4.

Introduce a new Kconfig and select it where necessary to keep
existing behaviour on older SoC while fixing FSP GOP init on
glinda. The VBIOS will get loaded into the D-segment instead
the C-segment, which is typically used by VGA.

TEST: FSP GOP on amd/birman+ is able to find the VBIOS.
      amdgpu driver still doesn't work as the VFCT table isn't
      generated on amd/glinda.

Change-Id: I6ab28aab74f3169d45d7d852a37ddfcfc75b7c88
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86300
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Ana Carolina Cabral <ana.cpmelo95@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/soc/amd/common/block/graphics/Kconfig    | 8 ++++++++
 src/soc/amd/common/block/graphics/graphics.c | 9 ++++++---
 src/soc/amd/glinda/Kconfig                   | 3 ++-
 3 files changed, 16 insertions(+), 4 deletions(-)

diff --git a/src/soc/amd/common/block/graphics/Kconfig b/src/soc/amd/common/block/graphics/Kconfig
index 3b2eaed565..b7401fbcdf 100644
--- a/src/soc/amd/common/block/graphics/Kconfig
+++ b/src/soc/amd/common/block/graphics/Kconfig
@@ -35,3 +35,11 @@ config SOC_AMD_COMMON_BLOCK_GRAPHICS_ACP
 	help
 	  Select this option to provide Audio CoProcessor ACPI device for pre-Ryzen APUs for
 	  use by custom Windows drivers.
+
+config SOC_AMD_COMMON_BLOCK_GRAPHICS_NO_VGA
+	bool
+	depends on SOC_AMD_COMMON_BLOCK_GRAPHICS
+	help
+	  Select this option when the IGD is not VGA compatible. On newer platforms the IGD
+	  advertises itself as a Display device, but not as a VGA Display controller.
+	  The IGD does not decode the legacy I/O ranges 0x3C0-0x3CF, 0x3D4.
diff --git a/src/soc/amd/common/block/graphics/graphics.c b/src/soc/amd/common/block/graphics/graphics.c
index f80484da8f..369fd85192 100644
--- a/src/soc/amd/common/block/graphics/graphics.c
+++ b/src/soc/amd/common/block/graphics/graphics.c
@@ -148,10 +148,13 @@ static const char *graphics_acpi_name(const struct device *dev)
 
 void *vbt_get(void)
 {
-	if (CONFIG(RUN_FSP_GOP))
-		return (void *)(uintptr_t)PCI_VGA_RAM_IMAGE_START;
+	if (!CONFIG(RUN_FSP_GOP))
+		return NULL;
 
-	return NULL;
+	if (CONFIG(SOC_AMD_COMMON_BLOCK_GRAPHICS_NO_VGA))
+		return (void *)(uintptr_t)PCI_RAM_IMAGE_START;
+
+	return (void *)(uintptr_t)PCI_VGA_RAM_IMAGE_START;
 }
 
 static void graphics_set_resources(struct device *const dev)
diff --git a/src/soc/amd/glinda/Kconfig b/src/soc/amd/glinda/Kconfig
index aa8c85e3e5..39fb785691 100644
--- a/src/soc/amd/glinda/Kconfig
+++ b/src/soc/amd/glinda/Kconfig
@@ -47,7 +47,8 @@ config SOC_AMD_GLINDA
 	select SOC_AMD_COMMON_BLOCK_DATA_FABRIC_MULTI_PCI_SEGMENT
 	select SOC_AMD_COMMON_BLOCK_ESPI_EXTENDED_DECODE_RANGES # TODO: Check if this is still correct
 	select SOC_AMD_COMMON_BLOCK_GPP_CLK
-	select SOC_AMD_COMMON_BLOCK_GRAPHICS		# TODO: Check if this is still correct
+	select SOC_AMD_COMMON_BLOCK_GRAPHICS
+	select SOC_AMD_COMMON_BLOCK_GRAPHICS_NO_VGA
 	select SOC_AMD_COMMON_BLOCK_HAS_ESPI		# TODO: Check if this is still correct
 	select SOC_AMD_COMMON_BLOCK_HAS_ESPI_ALERT_ENABLE # TODO: Check if this is still correct
 	select SOC_AMD_COMMON_BLOCK_I2C			# TODO: Check if this is still correct

From 935a423f26d390e5003ed15781d4bfbf76ce0501 Mon Sep 17 00:00:00 2001
From: Patrick Rudolph <patrick.rudolph@9elements.com>
Date: Tue, 11 Feb 2025 15:24:20 +0100
Subject: [PATCH 0071/3886] device/pci_rom: Use correct endian conversion

The Option ROM contains lots of 16bit values that are being used,
thus use the 16bit endianness conversion function over the 32bit
variant to avoid confusion.

TEST: Still works on amd/birman+.

Change-Id: I571be97a930ad018e1d1316117cefe5bd1c68f9b
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86383
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Andy Ebrahiem <ahmet.ebrahiem@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/device/pci_rom.c | 14 +++++++-------
 1 file changed, 7 insertions(+), 7 deletions(-)

diff --git a/src/device/pci_rom.c b/src/device/pci_rom.c
index d60720eb49..7e19646d52 100644
--- a/src/device/pci_rom.c
+++ b/src/device/pci_rom.c
@@ -93,16 +93,16 @@ struct rom_header *pci_rom_probe(const struct device *dev)
 
 	printk(BIOS_SPEW,
 	       "PCI expansion ROM, signature 0x%04x, INIT size 0x%04x, data ptr 0x%04x\n",
-	       le32_to_cpu(rom_header->signature),
-	       rom_header->size * 512, le32_to_cpu(rom_header->data));
+	       le16_to_cpu(rom_header->signature),
+	       rom_header->size * 512, le16_to_cpu(rom_header->data));
 
-	if (le32_to_cpu(rom_header->signature) != PCI_ROM_HDR) {
+	if (le16_to_cpu(rom_header->signature) != PCI_ROM_HDR) {
 		printk(BIOS_ERR, "Incorrect expansion ROM header signature %04x\n",
-		       le32_to_cpu(rom_header->signature));
+		       le16_to_cpu(rom_header->signature));
 		return NULL;
 	}
 
-	rom_data = (((void *)rom_header) + le32_to_cpu(rom_header->data));
+	rom_data = (((void *)rom_header) + le16_to_cpu(rom_header->data));
 
 	printk(BIOS_SPEW, "PCI ROM image, vendor ID %04x, device ID %04x,\n",
 	       rom_data->vendor, rom_data->device);
@@ -144,9 +144,9 @@ struct rom_header *pci_rom_load(struct device *dev,
 							    + image_size);
 
 		rom_data = (struct pci_data *)((void *)rom_header
-				+ le32_to_cpu(rom_header->data));
+				+ le16_to_cpu(rom_header->data));
 
-		image_size = le32_to_cpu(rom_data->ilen) * 512;
+		image_size = le16_to_cpu(rom_data->ilen) * 512;
 	} while ((rom_data->type != 0) && (rom_data->indicator != 0)); // make sure we got x86 version
 
 	if (rom_data->type != 0)

From 5f5aa79cca8190001f4b4ce14dd7805ad047b68f Mon Sep 17 00:00:00 2001
From: Patrick Rudolph <patrick.rudolph@9elements.com>
Date: Tue, 11 Feb 2025 16:08:55 +0100
Subject: [PATCH 0072/3886] device/pci_rom: Move VBIOS checksum fix

Move the VBIOS checksum code into the soc/amd folder, as it's
specific to AMD's FSP. The code now fixes the VBIOS in place
instead only fixing it for the VFCT table.

TEST: VBIOS has correct checksum after loading in BS_DEV_RESOURCES.
      VBIOS checksum is invalid entering graphics_dev_init().
      VBIOS checksum is correct leaving graphics_dev_init().

Change-Id: I63aaaefaf01ea456e2ed39cd0891e552a7fb5135
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86384
Reviewed-by: Ana Carolina Cabral <ana.cpmelo95@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
---
 src/device/pci_rom.c                  |  9 ---------
 src/soc/amd/common/fsp/fsp_graphics.c | 20 ++++++++++++++++++++
 2 files changed, 20 insertions(+), 9 deletions(-)

diff --git a/src/device/pci_rom.c b/src/device/pci_rom.c
index 7e19646d52..0fe94dbb56 100644
--- a/src/device/pci_rom.c
+++ b/src/device/pci_rom.c
@@ -242,15 +242,6 @@ ati_rom_acpi_fill_vfct(const struct device *device, acpi_vfct_t *vfct_struct,
 
 	vfct_struct->VBIOSImageOffset = (size_t)header - (size_t)vfct_struct;
 
-	/* Calculate and set checksum for VBIOS data if FSP GOP driver used,
-	   Since GOP driver modifies ATOMBIOS tables at end of VBIOS */
-	if (CONFIG(RUN_FSP_GOP)) {
-		/* Clear existing checksum before recalculating */
-		header->VbiosContent[VFCT_VBIOS_CHECKSUM_OFFSET] = 0;
-		header->VbiosContent[VFCT_VBIOS_CHECKSUM_OFFSET] =
-				acpi_checksum(header->VbiosContent, header->ImageLength);
-	}
-
 	current += header->ImageLength;
 	return current;
 }
diff --git a/src/soc/amd/common/fsp/fsp_graphics.c b/src/soc/amd/common/fsp/fsp_graphics.c
index 3e082e66ac..776711bd69 100644
--- a/src/soc/amd/common/fsp/fsp_graphics.c
+++ b/src/soc/amd/common/fsp/fsp_graphics.c
@@ -1,6 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0-or-later */
 
 #include <amdblocks/graphics.h>
+#include <amdblocks/vbt.h>
 #include <console/console.h>
 #include <device/device.h>
 #include <device/pci.h>
@@ -15,4 +16,23 @@ void fsp_graphics_init(struct device *const dev)
 	else
 		printk(BIOS_ERR, "%s: Unable to find resource for %s\n",
 				__func__, dev_path(dev));
+
+	/*
+	 * Calculate and set checksum for VBIOS data if FSP GOP driver used,
+	 * Since GOP driver modifies ATOMBIOS tables at end of BS_DEV_RESOURCES.
+	 * While Linux does not verify the checksum the Windows kernel driver does.
+	 */
+	struct rom_header *vbios = (struct rom_header *)vbt_get();
+	if (!vbios || !vbios->size) {
+		printk(BIOS_ERR, "%s: No VGA BIOS loaded for %s\n",
+				__func__, dev_path(dev));
+		return;
+	}
+
+	uint8_t *data = (uint8_t *)vbios;
+
+	/* Clear existing checksum before recalculating */
+	data[VFCT_VBIOS_CHECKSUM_OFFSET] = 0;
+	data[VFCT_VBIOS_CHECKSUM_OFFSET] =
+			acpi_checksum(data, vbios->size * 512);
 }

From 8a0d68d8047e7f46351899c959e2015bbb7ff09f Mon Sep 17 00:00:00 2001
From: Zheng Bao <fishbaozi@gmail.com>
Date: Mon, 23 Sep 2024 11:14:57 +0800
Subject: [PATCH 0073/3886] amdfwtool: Set entry address mode based on current
 table header

The address field of each PSP or BIOS entry defines the location of
the entry.
For the family newer than Cezanne, the upper 2 bits define the address
mode. In table header, the address mode of the table is set. They have
the same definition.
  Address Mode 0: Physical Address
  Address Mode 1: Relative Address to entire BIOS image
  Address Mode 2: Relative Address to PSP/BIOS directory
  Address Mode 3: Relative Address to slot N

In common case, the address mode of entry should be the same as its
table. In spec, it says, "attribute is ignored if the directory
address mode is not 2 or 3",
In the old code, if the header defines address mode as relative BIOS(1),
the entry address mode is not set. That meets the spec. PSP doesn't
use, but amdfwtool can use it to record the address mode and transfer
it to table. That can reduce the code complexity.

Identidal binary test passes on platforms which are not based on
Cezanne, V2000A, Genoa. Booting test passes on Majolica/Cezanne.

Change-Id: I156b315d350d9e7217afc7442ca80277bb7f9095
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84530
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
---
 util/amdfwtool/amdfwtool.c | 11 ++++++++---
 1 file changed, 8 insertions(+), 3 deletions(-)

diff --git a/util/amdfwtool/amdfwtool.c b/util/amdfwtool/amdfwtool.c
index 7f17b71361..42d13d8aa8 100644
--- a/util/amdfwtool/amdfwtool.c
+++ b/util/amdfwtool/amdfwtool.c
@@ -382,10 +382,15 @@ amd_bios_entry amd_bios_table[] = {
 #define BUFF_TO_RUN_MODE(ctx, ptr, mode) RUN_OFFSET_MODE((ctx), ((char *)(ptr) - (ctx).rom), \
 		(ctx).address_mode < (mode) ? (ctx).address_mode : (mode))
 #define BUFF_ROOM(ctx) ((ctx).rom_size - (ctx).current)
-/* Only set the address mode in entry if the table is mode 2. */
+/* AMD PSP Spec: Only set the address mode in entry if the table is mode 2 or 3. */
+/* For address mode 3, it is not be used in any SOC family yet.
+   For address mode 1, we can use it to store and transfer the address mode.
+   It can reduce the complexity. */
 #define SET_ADDR_MODE(table, mode) \
-		((table)->header.additional_info_fields.address_mode ==	\
-		AMD_ADDR_REL_TAB ? (mode) : 0)
+		((table)->header.additional_info_fields.address_mode == AMD_ADDR_REL_TAB ||  \
+		 (table)->header.additional_info_fields.address_mode == AMD_ADDR_REL_BIOS || \
+		 (table)->header.additional_info_fields.address_mode == AMD_ADDR_REL_SLOT    \
+		 ? (mode) : 0)
 #define SET_ADDR_MODE_BY_TABLE(table) \
 		SET_ADDR_MODE((table), (table)->header.additional_info_fields.address_mode)
 

From 94e9663f33d00d1043d9d733d081a86da44ecec7 Mon Sep 17 00:00:00 2001
From: Maximilian Brune <maximilian.brune@9elements.com>
Date: Mon, 23 Sep 2024 15:52:09 +0200
Subject: [PATCH 0074/3886] mb/amd/birman_plus: Update devicetree

The devicetree was still a copy of a previous mainboard.
This patch updates the devicetree for the birman_plus mainboard.
Birman plus is an AMD reference board.

sources:
- document #58168 Rev 1.01 "Birman+ User Guide"
- birman+ schematic

Change-Id: I1cc2e4c8f722048b24d84cf782855ae7a8d64c42
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84500
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ana Carolina Cabral <ana.cpmelo95@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
---
 src/mainboard/amd/birman_plus/Kconfig         |  1 +
 .../amd/birman_plus/devicetree_glinda.cb      | 54 ++++++++++++++-----
 2 files changed, 43 insertions(+), 12 deletions(-)

diff --git a/src/mainboard/amd/birman_plus/Kconfig b/src/mainboard/amd/birman_plus/Kconfig
index 9794383360..91e39bf260 100644
--- a/src/mainboard/amd/birman_plus/Kconfig
+++ b/src/mainboard/amd/birman_plus/Kconfig
@@ -6,6 +6,7 @@ config BOARD_AMD_BIRMANPLUS_COMMON
 	select EC_ACPI
 	select SOC_AMD_COMMON_BLOCK_USE_ESPI if !SOC_AMD_COMMON_BLOCK_SIMNOW_BUILD
 	select DRIVERS_PCIE_RTD3_DEVICE
+	select DRIVERS_I2C_GENERIC
 	select MAINBOARD_HAS_CHROMEOS
 	select PCIEXP_ASPM
 	select PCIEXP_CLK_PM
diff --git a/src/mainboard/amd/birman_plus/devicetree_glinda.cb b/src/mainboard/amd/birman_plus/devicetree_glinda.cb
index 5a7fd00c2a..07642aa557 100644
--- a/src/mainboard/amd/birman_plus/devicetree_glinda.cb
+++ b/src/mainboard/amd/birman_plus/devicetree_glinda.cb
@@ -1,7 +1,5 @@
 # SPDX-License-Identifier: GPL-2.0-only
 
-# TODO: Update for birmanplus
-
 chip soc/amd/glinda
 	register "common_config.espi_config" = "{
 		.std_io_decode_bitmap = ESPI_DECODE_IO_0x80_EN | ESPI_DECODE_IO_0X2E_0X2F_EN | ESPI_DECODE_IO_0X60_0X64_EN,
@@ -178,20 +176,40 @@ chip soc/amd/glinda
 		.ComboPhyStaticConfig[2] = USB_COMBO_PHY_MODE_USB_C,
 	}"
 
-	register "gpp_clk_config[0]" = "GPP_CLK_REQ"
-	register "gpp_clk_config[1]" = "GPP_CLK_REQ"
-	register "gpp_clk_config[2]" = "GPP_CLK_OFF"
-	register "gpp_clk_config[3]" = "GPP_CLK_REQ"
+	register "gpp_clk_config[0]" = "GPP_CLK_REQ" # MXM
+	register "gpp_clk_config[1]" = "GPP_CLK_REQ" # NVMe SSD1
+	register "gpp_clk_config[2]" = "GPP_CLK_REQ" # NVMe SSD0
+	register "gpp_clk_config[3]" = "GPP_CLK_REQ" # WLAN
+	register "gpp_clk_config[4]" = "GPP_CLK_REQ" # WWAN
+	register "gpp_clk_config[5]" = "GPP_CLK_REQ" # SD
+	register "gpp_clk_config[6]" = "GPP_CLK_REQ" # GBE
 
 	device domain 0 on
 		device ref iommu on end
-		device ref gpp_bridge_2_1 on end # GBE
-		device ref gpp_bridge_2_2 on end # WIFI
-		device ref gpp_bridge_2_3 on end # NVMe SSD
+		device ref gpp_bridge_2_1 on end # NVME SSD0
+		device ref gpp_bridge_2_2 on end # SD
+		device ref gpp_bridge_2_3 on end # WLAN
+		device ref gpp_bridge_2_4 on end # GBE
+		device ref gpp_bridge_2_5 on end # WWAN
+		device ref gpp_bridge_3_1 on end # PCIe x4/x8 (ENABLE_SSD1_BIRMANPLUS)
+		device ref gpp_bridge_3_2 on end # NVME SSD1 (ENABLE_SSD1_BIRMANPLUS)
+
 		device ref gpp_bridge_a on  # Internal GPP Bridge 0 to Bus A
 			device ref gfx on end # Internal GPU (GFX)
 			device ref gfx_hda on end # Display HD Audio Controller (GFXAZ)
 			device ref crypto on end # Crypto Coprocessor
+			device ref xhci_1 on # USB 3.1 (USB1)
+				chip drivers/usb/acpi
+					device ref xhci_1_root_hub on
+						chip drivers/usb/acpi
+							device ref usb3_port7 on end
+						end
+						chip drivers/usb/acpi
+							device ref usb2_port7 on end
+						end
+					end
+				end
+			end
 			device ref acp on end # Audio Processor (ACP)
 		end
 		device ref gpp_bridge_c on  # Internal GPP Bridge 2 to Bus C
@@ -216,9 +234,13 @@ chip soc/amd/glinda
 						chip drivers/usb/acpi
 							device ref usb2_port5 on end
 						end
+						chip drivers/usb/acpi
+							device ref usb2_port6 on end
+						end
 					end
 				end
 			end
+
 			device ref usb4_xhci_0 on
 				chip drivers/usb/acpi
 					device ref usb4_xhci_0_root_hub on
@@ -232,7 +254,6 @@ chip soc/amd/glinda
 				end
 			end
 			device ref usb4_xhci_1 on
-				ops xhci_pci_ops
 				chip drivers/usb/acpi
 					register "type" = "UPC_TYPE_HUB"
 					device ref usb4_xhci_1_root_hub on
@@ -250,8 +271,17 @@ chip soc/amd/glinda
 
 	device ref i2c_0 on end
 	device ref i2c_1 on end
-	device ref i2c_2 on end
+	device ref i2c_2 on
+		chip drivers/i2c/generic
+			register "hid" = "ACPI_DT_NAMESPACE_HID"
+			register "desc" = ""TMP420 3 channel temperature sensor""
+			register "uid" = "1"
+			register "compat_string" = ""ti,tmp432""
+			device i2c 4d on end
+		end
+	end
 	device ref i2c_3 on end
 	device ref uart_0 on end # UART0
-
+	device ref uart_2 on end # UART2
+	device ref uart_4 on end # UART4
 end

From 6d61022b8f5517ae1f17ff10d858f4f3c6f1700c Mon Sep 17 00:00:00 2001
From: Kenneth Chan <kenneth.chan@quanta.corp-partner.google.com>
Date: Thu, 13 Feb 2025 15:34:06 +0800
Subject: [PATCH 0075/3886] mb/google/rex/var/kanix: Update LAN clock request
 setting

According to the EVT's circuit(kanix_250116.pdf) change,
update LAN clock request to GPP_C11.

BUG=b:386025819
BRANCH=firmware-rex-15709.B
TEST=emerge-rex coreboot chromeos-bootimage; test LAN function on kanix
Change-Id: I5d27585717897203d6ac81ca47551be5771918c3
Signed-off-by: Kenneth Chan <kenneth.chan@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86397
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/google/rex/variants/kanix/gpio.c | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/src/mainboard/google/rex/variants/kanix/gpio.c b/src/mainboard/google/rex/variants/kanix/gpio.c
index 401a0834ca..4b757a1ae5 100644
--- a/src/mainboard/google/rex/variants/kanix/gpio.c
+++ b/src/mainboard/google/rex/variants/kanix/gpio.c
@@ -117,8 +117,8 @@ static const struct pad_config gpio_table[] = {
 	PAD_NC(GPP_C09, NONE),
 	/* GPP_C10 : net NC is not present in the given design */
 	PAD_NC(GPP_C10, NONE),
-	/* GPP_C11 : Not Connected */
-	PAD_NC(GPP_C11, NONE),
+	/* GPP_C11 : [] ==> LAN_CLKREQ_ODL */
+	PAD_CFG_NF(GPP_C11, NONE, DEEP, NF1),
 	/* GPP_C12 : NC pad. */
 	PAD_NC(GPP_C12, NONE),
 	/* GPP_C13 : Not connected */
@@ -174,8 +174,8 @@ static const struct pad_config gpio_table[] = {
 	PAD_CFG_NF(GPP_D16, NONE, DEEP, NF2),
 	/* GPP_D17 : [] ==> I2S_SOC_RX_HP_TX */
 	PAD_CFG_NF(GPP_D17, NONE, DEEP, NF2),
-	/* GPP_D18 : [] ==> LAN_CLKREQ_ODL */
-	PAD_CFG_NF(GPP_D18, NONE, DEEP, NF1),
+	/* GPP_D18 : Not Connected */
+	PAD_NC(GPP_D18, NONE),
 	/* GPP_D19 : [] ==> EC_SOC_REC_SWITCH_ODL */
 	PAD_CFG_GPI_LOCK(GPP_D19, NONE, LOCK_CONFIG),
 	/* GPP_D20 : [] ==> SSD_CLKREQ_ODL */

From d6eff7060a58d7317518d4f9f201ec639940b61a Mon Sep 17 00:00:00 2001
From: David Wu <david_wu@quanta.corp-partner.google.com>
Date: Thu, 13 Feb 2025 14:04:41 +0800
Subject: [PATCH 0076/3886] mb/google/nissa/var/craask: Modify eMMC DLL tuning
 value

Craask cannot boot into OS from 2nd source eMMC.
Update eMMC DLL tuning value to improve initialization reliability

BUG=b:375497774
TEST=Cold reboot stress test over 2500 cycles

Change-Id: I415beb84ac09f8c3e80c3df12bc323a06baf812d
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86395
Reviewed-by: Simon Yang <simon1.yang@intel.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/google/brya/variants/craask/overridetree.cb | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/mainboard/google/brya/variants/craask/overridetree.cb b/src/mainboard/google/brya/variants/craask/overridetree.cb
index 069deb33db..ee8a63dd18 100644
--- a/src/mainboard/google/brya/variants/craask/overridetree.cb
+++ b/src/mainboard/google/brya/variants/craask/overridetree.cb
@@ -70,7 +70,7 @@ chip soc/intel/alderlake
 	# [22:16] steps of delay for DDR50, each 125ps, range: 0 - 78.
 	# [14:8] steps of delay for SDR25/HS50, each 125ps, range: 0 - 119.
 	# [6:0] steps of delay for SDR12, each 125ps, range: 0 - 119.
-	register "common_soc_config.emmc_dll.emmc_rx_cmd_data_cntl1" = "0x1C1B4F3C"
+	register "common_soc_config.emmc_dll.emmc_rx_cmd_data_cntl1" = "0x1C1B4F1B"
 
 	# EMMC RX CMD/DATA Delay 2
 	# Refer to EDS-Vol2-42.3.12.

From b7d144a41c0721f457c1ad88ea2ad860a7b34e84 Mon Sep 17 00:00:00 2001
From: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Date: Fri, 28 Jun 2024 12:50:25 +0000
Subject: [PATCH 0077/3886] Documentation/mainboard/lenovo: Add ThinkCentre
 M710s

Change-Id: I90311257a28bd463712c4d43f8b83baa745509cc
Signed-off-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80411
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 Documentation/mainboard/index.md              |   1 +
 .../mainboard/lenovo/thinkcentre_m710s.md     |  81 ++++++++++++++++++
 .../lenovo/thinkcentre_m710s_spi_location.jpg | Bin 0 -> 84413 bytes
 3 files changed, 82 insertions(+)
 create mode 100644 Documentation/mainboard/lenovo/thinkcentre_m710s.md
 create mode 100644 Documentation/mainboard/lenovo/thinkcentre_m710s_spi_location.jpg

diff --git a/Documentation/mainboard/index.md b/Documentation/mainboard/index.md
index f9f904877b..518c02a994 100644
--- a/Documentation/mainboard/index.md
+++ b/Documentation/mainboard/index.md
@@ -184,6 +184,7 @@ mAL-10 <kontron/mal10.md>
 Mainboard codenames <lenovo/codenames.md>
 Hardware Maintenance Manual of ThinkPads <lenovo/thinkpad_hmm.md>
 R60 <lenovo/r60.md>
+ThinkCentre M710s <lenovo/thinkcentre_m710s.md>
 T4xx common <lenovo/t4xx_series.md>
 X2xx common <lenovo/x2xx_series.md>
 M920 Tiny <lenovo/m920q.md>
diff --git a/Documentation/mainboard/lenovo/thinkcentre_m710s.md b/Documentation/mainboard/lenovo/thinkcentre_m710s.md
new file mode 100644
index 0000000000..0f9adffba8
--- /dev/null
+++ b/Documentation/mainboard/lenovo/thinkcentre_m710s.md
@@ -0,0 +1,81 @@
+# Lenovo ThinkCentre M710s
+
+This page provides technical documentation on [Lenovo ThinkCentre M710s].
+
+## Flash chip
+
+```{eval-rst}
++----------+-------------+
+| Type     | Value       |
++==========+=============+
+| Socketed | yes         |
++----------+-------------+
+| Model    | W25Q64JV-.Q |
++----------+-------------+
+| Size     | 8MiB        |
++----------+-------------+
+| Package  | SOIC-8      |
++----------+-------------+
+```
+
+The flash chip is divided into the following regions.
+
+	00000000:00000fff fd
+	00200000:007fffff bios
+	00003000:001fffff me
+	00001000:00002fff gbe
+
+## Flashing
+
+The flash chip cannot be flashed internally when running vendor firmware, and must
+be flashed externally using a programmer of your choice.
+
+Steps on how to open the chassis and get access to the mainboard are described
+in the [hardware maintenance manual]. Follow the steps shown from
+"[Removing the computer cover]" until step 1 of "[Replacing the storage drive]".
+
+The SPI flash should be easy to identify and the location is shown in the image
+below. See the [datasheet] and [flashing firmware tutorial] for more information.
+
+![](thinkcentre_m710s_spi_location.jpg)
+
+## Status
+
+### Working
+ * Ubuntu 22.04.1 (Linux 6.5.0) using payloads:
+   * SeaBIOS
+   * MrChromebox's EDK 2 fork
+   * Tianocore's EDK 2
+ * Internal flashing (from coreboot)
+ * PEG (PCIe Graphics)
+ * PCIe
+ * SATA
+ * M.2 SSD
+ * M.2 WLAN (+ Bluetooth)
+ * LAN
+ * USB
+ * Memory card reader
+ * CPU fan
+ * VGA
+ * Display ports
+ * Audio (output)
+ * COM1
+ * TPM
+
+### Not working
+ * Super I/O not well supported (there may be some minor issues)
+ * Power button LED
+ * ME cleaner
+
+### Untested
+ * Audio (input)
+ * COM2 header
+ * LPT header
+ * PS/2 keyboard and mouse
+
+[Lenovo ThinkCentre M710s]: https://www.lenovo.com/us/en/p/desktops/thinkcentre/m-series-sff/thinkcentre-m710s/11tc1md710s
+[hardware maintenance manual]: https://download.lenovo.com/pccbbs/thinkcentre_pdf/m710s_ug_hmm_en.pdf
+[Removing the computer cover]: https://download.lenovo.com/pccbbs/thinkcentre_pdf/m710s_ug_hmm_en.pdf#page=28
+[Replacing the storage drive]: https://download.lenovo.com/pccbbs/thinkcentre_pdf/m710s_ug_hmm_en.pdf#page=31
+[datasheet]: https://www.winbond.com/hq/product/code-storage-flash-memory/serial-nor-flash/?__locale=en&partNo=W25Q64JV
+[flashing firmware tutorial]: ../../tutorial/flashing_firmware/index.md
diff --git a/Documentation/mainboard/lenovo/thinkcentre_m710s_spi_location.jpg b/Documentation/mainboard/lenovo/thinkcentre_m710s_spi_location.jpg
new file mode 100644
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HcmV?d00001


From c63a1988847aafa3ee2a38fb166b00777269aaa0 Mon Sep 17 00:00:00 2001
From: Alper Nebi Yasak <alpernebiyasak@gmail.com>
Date: Wed, 24 Apr 2024 21:23:57 +0300
Subject: [PATCH 0078/3886] drivers/qemu/bochs: Use arch-independent data port

The QEMU Bochs display driver uses 0x1CF as its VBE DISPI data port, but
this is only present on x86. Instead, use the port at 0x1D0 [1] which is
available on both x86 and non-x86 architectures. The data port is also
calculated inline based on the VBE DISPI index port while reading and
writing, update those expressions as well.

[1] https://web.archive.org/web/20240404032816/https://www.qemu.org/docs/master/specs/standard-vga.html#io-ports-used

Change-Id: I899beb742d42c26f3e57023f05ff459094fce5f1
Signed-off-by: Alper Nebi Yasak <alpernebiyasak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82061
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/drivers/emulation/qemu/bochs.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/src/drivers/emulation/qemu/bochs.c b/src/drivers/emulation/qemu/bochs.c
index 2e0526fa8f..70d17cb716 100644
--- a/src/drivers/emulation/qemu/bochs.c
+++ b/src/drivers/emulation/qemu/bochs.c
@@ -14,7 +14,7 @@
 
 /* VGA init. We use the Bochs VESA VBE extensions  */
 #define VBE_DISPI_IOPORT_INDEX          0x01CE
-#define VBE_DISPI_IOPORT_DATA           0x01CF
+#define VBE_DISPI_IOPORT_DATA           0x01D0
 
 #define VBE_DISPI_INDEX_ID              0x0
 #define VBE_DISPI_INDEX_XRES            0x1
@@ -46,7 +46,7 @@ static void bochs_write(struct resource *res, int index, int val)
 {
 	if (res->flags & IORESOURCE_IO) {
 		outw(index, res->base);
-		outw(val, res->base + 1);
+		outw(val, res->base + 2);
 	} else {
 		write16(res2mmio(res, 0x500 + index * 2, 0), val);
 	}
@@ -56,7 +56,7 @@ static int bochs_read(struct resource *res, int index)
 {
 	if (res->flags & IORESOURCE_IO) {
 		outw(index, res->base);
-		return inw(res->base + 1);
+		return inw(res->base + 2);
 	} else {
 		return read16(res2mmio(res, 0x500 + index * 2, 0));
 	}

From a132aba3995d2d47732afc9cb34961a3f96e65a1 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Michael=20B=C3=BCchler?= <michael.buechler@posteo.net>
Date: Sun, 7 Jan 2024 12:39:53 +0100
Subject: [PATCH 0079/3886] board_status/getrevision.sh: Ignore non-annotated
 tags
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Local tags (e.g. to keep track of builds) should not be used to describe
a board status report. This has happened in some cases, e.g. [1].

According to the Git 2.41.0 manual for git-describe, the '--tagged'
parameter is a way to also use any "lightweight (non-annotated) tag" in
addition to annotated tags, which are always used even without this
parameter. All coreboot release tags seem to be annotated, so this
option should be safe to drop.

[1] https://review.coreboot.org/plugins/gitiles/board-status/+/b8c47429bad5afc5cd7f798cad3dece9790a1f83

Signed-off-by: Michael Büchler <michael.buechler@posteo.net>
Change-Id: I54b302415e569a3385559cc85323ce34462042ad
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79837
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 util/board_status/getrevision.sh | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/util/board_status/getrevision.sh b/util/board_status/getrevision.sh
index ced20fc451..a982f8d815 100755
--- a/util/board_status/getrevision.sh
+++ b/util/board_status/getrevision.sh
@@ -112,7 +112,7 @@ tagged_revision() {
 	local r
 
 	if git_is_file_tracked "$1" ; then
-		r=$(git describe --tags --dirty)
+		r=$(git describe --dirty)
 	else
 		return ${EXIT_FAILURE}
 	fi

From a614e3c50f706af1e897cf20440e48de144148bb Mon Sep 17 00:00:00 2001
From: Patrick Rudolph <siro@das-labor.org>
Date: Fri, 2 Jul 2021 07:34:54 +0200
Subject: [PATCH 0080/3886] Documentation: Improve x86_64

* Move x86_64 documentation to dedicated page
* Update with better description of current implementation
* Update TODOs

Change-Id: Ia5ba51be629a8c878aad64d3297176457cf8e855
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79160
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
---
 Documentation/arch/x86/index.md  |  88 +------------------------
 Documentation/arch/x86/x86_64.md | 109 +++++++++++++++++++++++++++++++
 2 files changed, 110 insertions(+), 87 deletions(-)
 create mode 100644 Documentation/arch/x86/x86_64.md

diff --git a/Documentation/arch/x86/index.md b/Documentation/arch/x86/index.md
index f2597ac9ce..1c5edb32ab 100644
--- a/Documentation/arch/x86/index.md
+++ b/Documentation/arch/x86/index.md
@@ -6,91 +6,5 @@ This section contains documentation about coreboot on x86 architecture.
 :maxdepth: 1
 
 x86 PAE support <pae.md>
+x86_64 support <x86_64.md>
 ```
-
-## State of x86_64 support
-Some SOCs now support 64bit mode. Search for HAVE_X86_64_SUPPORT in Kconfig.
-
-In order to add support for x86_64 the following assumptions were made:
-* The CPU supports long mode
-* All memory returned by malloc must be below 4GiB in physical memory
-* All code that is to be run must be below 4GiB in physical memory
-* The high dword of pointers is always zero
-* The reference implementation is qemu
-* x86 payloads are loaded below 4GiB in physical memory and are jumped
-  to in *protected mode*
-
-## Assumptions for all stages using the reference implementation
-* 0-4GiB are identity mapped using 2MiB-pages as WB
-* Memory above 4GiB isn't accessible
-* page tables reside in memory mapped ROM
-* A stage can install new page tables in RAM
-
-## Page tables
-A `pagetables` cbfs file is generated based on an assembly file.
-
-To generate the static page tables it must know the physical address where to
-place the file.
-
-The page tables contains the following structure:
-* PML4E pointing to PDPE
-* PDPE with *$n* entries each pointing to PDE
-* *$n* PDEs with 512 entries each
-
-At the moment *$n* is 4, which results in identity mapping the lower 4 GiB.
-
-## Basic x86_64 support
-Basic support for x86_64 has been implemented for QEMU mainboard target.
-
-## Reference implementation
-The reference implementation is
-```{toctree}
-:maxdepth: 1
-
-QEMU i440fx <../../mainboard/emulation/qemu-i440fx.md>
-QEMU Q35 <../../mainboard/emulation/qemu-q35.md>
-```
-
-## TODO
-* Identity map memory above 4GiB in ramstage
-
-## Future work
-
-1. Fine grained page tables for SMM:
-   * Must not have execute and write permissions for the same page.
-   * Must allow only that TSEG pages can be marked executable
-2. Support 64bit PCI BARs above 4GiB
-3. Place and run code above 4GiB
-
-## Porting other boards
-* Fix compilation errors
-* Test how well CAR works with x86_64 and paging
-* Improve mode switches
-
-## Known problems on real hardware
-
-Running VGA rom directly fails. Yabel works fine though.
-
-## Known bugs on KVM enabled qemu
-
-The `x86_64` reference code runs fine in qemu soft-cpu, but has serious issues
-when using KVM mode on some machines. The workaround is to *not* place
-page-tables in ROM, as done in
-[CB:49228](https://review.coreboot.org/c/coreboot/+/49228).
-
-Here's a list of known issues:
-
-* After entering long mode, the FPU doesn't work anymore, including accessing
-  MMX registers. It works fine before entering long mode. It works fine when
-  switching back to protected mode. Other registers, like SSE registers, are
-  working fine.
-* Reading from virtual memory, when the page tables are stored in ROM, causes
-  the MMU to abort the "page table walking" mechanism when the lower address
-  bits of the virtual address to be translated have a specific pattern.
-  Instead of loading the correct physical page, the one containing the
-  page tables in ROM will be loaded and used, which breaks code and data as
-  the page table doesn't contain the expected data. This in turn leads to
-  undefined behaviour whenever the 'wrong' address is being read.
-* Disabling paging in compatibility mode crashes the CPU.
-* Returning from long mode to compatibility mode crashes the CPU.
-* Entering long mode crashes on AMD host platforms.
diff --git a/Documentation/arch/x86/x86_64.md b/Documentation/arch/x86/x86_64.md
new file mode 100644
index 0000000000..b9aebd013c
--- /dev/null
+++ b/Documentation/arch/x86/x86_64.md
@@ -0,0 +1,109 @@
+# x86_64 architecture documentation
+
+This section documents coreboot's x86_64 support. When enabled,
+every coreboot stage is built for x86_64, contrary to UEFI's implementation
+that only runs some stages in x86_64.
+On UEFI the PEI phase, which is x86_32, brings up DRAM and installs
+page tables for the x86_64 DXE and BDS phases.
+
+## Toolchain requirements for x86_64 support
+* The compiler must support generating code for the *large memory model*
+  (-mcmodel=large). It's supported since GCC 4.4.
+
+  Page tables can be used to provide security benefits, such as by marking
+  memory as non-executable or removing it entirely. This could be useful
+  for SMM to mark regular DRAM as NX.
+
+  The large memory model causes the compiler to emit 64bit addressing
+  instructions, which increases code size. In theory, this is roughly
+  made up for by the faster execution of the x86_64 code.
+
+* All x86 coreboot stages and payloads must be loaded below 4GiB in
+  physical memory. When jumping to the payload coreboot will drop from
+  long mode back to protected mode to keep compatibility with these payloads.
+
+## Comparison to UEFI
+On UEFI the SEC and PEI phases (similar to coreboot's bootblock and romstage)
+are run in x86_32 mode. The following (guessed) reasons are likely:
+* There's no need for x86_64 as memory hasn't been trained yet. The whole 4GiB
+  address space, including CAR, memory mapped SPI flash and PCI BARs, are
+  accessible in x86_32.
+* When the EFI specification was written compilers did not support
+  *large memory model*, required in CAR when using a 1:1 page mapping
+* Code is 20% bigger in x86_64 due to *large memory model* where pointers and
+  function calls always use 8 byte addressing. However flash size was very
+  limited, compared to today's flash chips, when the EFI spec was written.
+
+## Current software constraints for x86_64 support
+The following constraints are coreboot limitations as it was intended to run in
+protected mode only. The code still assumes 32bit pointers in some places and thus:
+* The high dword of pointers must always be zero.
+* All memory returned by malloc must be below 4GiB in physical memory.
+* All code that is to be run must be below 4GiB in physical memory.
+* CBMEM must reside below 4GiB in physical memory.
+
+Any software within coreboot must not access memory resources above 4GiB until
+end of BS_DEV_RESOURCES in ramstage. Only at that point the full memory map is
+known and identity mapped.
+
+## Supported boards
+On the supported boards you can enable x86_64 compilation by setting the
+Kconfig `USE_X86_64_SUPPORT`. This config option is enabled if the SOC/CPU
+selects `HAVE_X86_64_SUPPORT`.
+
+## Protected mode wrappers
+On some platforms binary blobs are run to initialize parts of the hardware.
+When these binary blobs have been compiled for x86_32, then coreboot must
+switch to protected mode in order to call and run the blobs. Once the invoked
+blobs finish running, coreboot needs to switch back to long mode.
+
+Since every BLOB is different a SoC must be enabled to support x86_64 mode
+by providing the correct wrapper around the x86_32 BLOBs.
+
+## TODO
+* Support more platforms
+* Fix running VGA Option ROMs
+* Fix running MRC.bin (Sandy Bridge / Haswell boards)
+* Identity map memory above 4GiB in ramstage
+* Fine grained page tables for SMM:
+   * Must not have execute and write permissions for the same page.
+   * Must only allow TSEG pages to be marked as executable.
+   * Must reside in SMRAM.
+   * Must be placed together with SMM rmodule.
+* Support 64bit PCI BARs above 4GiB
+* Jump to compatible payloads in long mode
+
+## Porting other boards
+* Fix compilation errors
+* Test how well CAR works with x86_64 and paging
+* Improve mode switches
+* Test libgfxinit / VGA Option ROMs / FSP
+
+## Known bugs on real hardware
+
+According to Intel x86_64 mode hasn't been validated in CAR environments.
+However, coreboot developers working on x86_64 support have tried this on
+various Intel platforms, and so far haven't found any issues with CAR when
+running in x86_64 mode.
+
+## Known bugs on KVM enabled QEMU
+
+The `x86_64` reference code runs fine in QEMU's soft-cpu, but has serious issues
+when using KVM mode on some machines. This is due to various mechanisms trying
+to accelerate the code execution.
+
+Known issues in QEMU:
+* After entering long mode, the FPU doesn't work anymore, including accessing
+  MMX registers. It works fine before entering long mode. It works fine when
+  switching back to protected mode. Other registers, like SSE registers, are
+  working fine.
+* Reading from virtual memory, when the page tables are stored in ROM, causes
+  the MMU to abort the "page table walking" mechanism when the lower address
+  bits of the virtual address to be translated have a specific pattern.
+  Instead of loading the correct physical page, the one containing the
+  page tables in ROM will be loaded and used, which breaks code and data as
+  the page table doesn't contain the expected data. This in turn leads to
+  undefined behaviour whenever the 'wrong' address is being read.
+* Disabling paging in compatibility mode crashes the CPU.
+* Returning from long mode to compatibility mode crashes the CPU.
+* Entering long mode crashes on AMD host platforms.

From 7073ec43b0d82e0713260cb2952cfb70786ca1c5 Mon Sep 17 00:00:00 2001
From: Maximilian Brune <maximilian.brune@9elements.com>
Date: Fri, 9 Aug 2024 13:45:57 +0200
Subject: [PATCH 0081/3886] arch/riscv: Add common FDT build

Currently all platforms on RISC-V require a FDT.
The inclusion of the FDT is currently done in the platform Makefiles.
In order to factor out some common code this patch adds the inclusion
in the architecture Makefile. The FDT must be aligned to 8 byte
according to device tree spec. It avoids misaligned access.

Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: I3b304a89646fe84c98e9f199f315bebb156de16c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83848
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
---
 src/arch/riscv/Kconfig     | 15 +++++++++++++++
 src/arch/riscv/Makefile.mk | 23 +++++++++++++++++++++++
 2 files changed, 38 insertions(+)

diff --git a/src/arch/riscv/Kconfig b/src/arch/riscv/Kconfig
index b7fc0cab01..8fa7854ea2 100644
--- a/src/arch/riscv/Kconfig
+++ b/src/arch/riscv/Kconfig
@@ -144,4 +144,19 @@ config RISCV_GET_HART_COUNT_AT_RUNTIME
 	  SOC/Mainboards select this option in case the number of harts is not known at
 	  build time. In this case the SOC must have a scheme in place to discover all harts.
 
+config RISCV_DTS
+	bool
+	default n
+	help
+	  This option is selected by mainboards that include a devicetree
+	  source file (not to be confused with the coreboot devicetree.cb files).
+	  The devicetree will be preprocessed and compiled into a FDT (flattened devicetree).
+	  Said FDT will be put into a CBFS file for use in runtime.
+
+config RISCV_DTS_FILE
+	string
+	depends on RISCV_DTS
+	help
+	  Path to the devicetree source file in .dts format.
+
 endif # if ARCH_RISCV
diff --git a/src/arch/riscv/Makefile.mk b/src/arch/riscv/Makefile.mk
index bda392adb4..3efd8959cc 100644
--- a/src/arch/riscv/Makefile.mk
+++ b/src/arch/riscv/Makefile.mk
@@ -67,6 +67,29 @@ all-y += \
 	$(top)/src/lib/memset.c
 all-$(CONFIG_RISCV_USE_ARCH_TIMER) += arch_timer.c
 
+## FDT (Flattened Devicetree) inclusion
+
+ifeq ($(CONFIG_RISCV_DTS),y)
+
+# at some point dtc may be compiled by our toolchain
+DTC ?= dtc
+CPPFLAGS_dts += -nostdinc -P -x assembler-with-cpp -I src/arch/riscv/include
+
+$(obj)/preprocessed.dts: $(call strip_quotes, $(CONFIG_RISCV_DTS_FILE))
+	$(CPP_riscv) $(CPPFLAGS_dts) -o $@ $<
+
+$(obj)/dtb: $(obj)/preprocessed.dts
+	$(DTC) -I dts -O dtb -o $@ $<
+
+# This may be optimized in the future by letting cbfstool parse our FDT into a unflattened
+# devicetree blob in build time, so that we only need to flatten it in runtime instead of
+# unflatten and flatten it in runtime.
+cbfs-files-y += DTB
+DTB-file := $(obj)/dtb
+DTB-type := raw
+DTB-align := 8 # according to spec device trees needs to be 8 byte aligned
+
+endif # CONFIG_RISCV_DTS
 
 ################################################################################
 ## bootblock

From 94d4707649718687e2a59e6ecc6361ba6a64587b Mon Sep 17 00:00:00 2001
From: Maximilian Brune <maximilian.brune@9elements.com>
Date: Fri, 9 Aug 2024 13:50:50 +0200
Subject: [PATCH 0082/3886] util/riscv: Add starfive Image building tool

Add the tooling necessary to build an Image that can be found and
started by ROM code of the JH7110 SOC.

source: https://github.com/starfive-tech/Tools

Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: Iab16c1e1f15f24e85c0ef1a3e838d024e1e49286
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83849
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 util/lint/lint-extended-015-final-newlines    |   3 +-
 util/lint/lint-stable-009-old-licenses        |   1 +
 .../riscv/starfive-jh7110-spl-tool/.gitignore |  10 +
 util/riscv/starfive-jh7110-spl-tool/LICENSE   | 365 ++++++++++++++++++
 util/riscv/starfive-jh7110-spl-tool/Makefile  |  16 +
 util/riscv/starfive-jh7110-spl-tool/README.md |  54 +++
 util/riscv/starfive-jh7110-spl-tool/crc32.c   |  35 ++
 .../riscv/starfive-jh7110-spl-tool/spl_tool.c | 244 ++++++++++++
 8 files changed, 727 insertions(+), 1 deletion(-)
 create mode 100644 util/riscv/starfive-jh7110-spl-tool/.gitignore
 create mode 100644 util/riscv/starfive-jh7110-spl-tool/LICENSE
 create mode 100644 util/riscv/starfive-jh7110-spl-tool/Makefile
 create mode 100644 util/riscv/starfive-jh7110-spl-tool/README.md
 create mode 100644 util/riscv/starfive-jh7110-spl-tool/crc32.c
 create mode 100644 util/riscv/starfive-jh7110-spl-tool/spl_tool.c

diff --git a/util/lint/lint-extended-015-final-newlines b/util/lint/lint-extended-015-final-newlines
index 18ca75b7e6..7324213034 100755
--- a/util/lint/lint-extended-015-final-newlines
+++ b/util/lint/lint-extended-015-final-newlines
@@ -24,7 +24,8 @@ build/\|\
 \.git/\|\
 coreboot-builds/\|\
 util/nvidia/cbootimage/\|\
-^util/goswid/vendor"
+^util/goswid/vendor\|\
+^util/riscv/starfive-jh7110-spl-tool"
 EXCLUDED_FILES='\.gif$\|\.jpg$\|\.cksum$\|\.bin$\|\.vbt$\|\.hex$\|\.ico$\|\.o$\|\.bz2$\|\.xz$\|^.tmpconfig\|\.pyc$\|_shipped$\|sha256$\|\.png$\|\.patch$\|\.apcb$'
 
 HAVE_FILE=$(command -v file 1>/dev/null 2>&1; echo $?)
diff --git a/util/lint/lint-stable-009-old-licenses b/util/lint/lint-stable-009-old-licenses
index 45c01c73a6..202a1a9b5e 100755
--- a/util/lint/lint-stable-009-old-licenses
+++ b/util/lint/lint-stable-009-old-licenses
@@ -31,6 +31,7 @@ _shipped$|\
 ^util/lint/lint-000-license-headers|\
 ^util/lint/lint-stable-009-old-licenses|\
 ^util/nvidia/cbootimage|\
+^util/riscv/starfive-jh7110-spl-tool|\
 ^3rdparty|\
 __pycache__|\
 ^payloads/external\
diff --git a/util/riscv/starfive-jh7110-spl-tool/.gitignore b/util/riscv/starfive-jh7110-spl-tool/.gitignore
new file mode 100644
index 0000000000..26c88884ee
--- /dev/null
+++ b/util/riscv/starfive-jh7110-spl-tool/.gitignore
@@ -0,0 +1,10 @@
+_*
+*.swp
+*.o
+*.out
+*.key
+*.diff
+*.patch
+*.out
+tags
+spl_tool
diff --git a/util/riscv/starfive-jh7110-spl-tool/LICENSE b/util/riscv/starfive-jh7110-spl-tool/LICENSE
new file mode 100644
index 0000000000..36cc8c3b75
--- /dev/null
+++ b/util/riscv/starfive-jh7110-spl-tool/LICENSE
@@ -0,0 +1,365 @@
+================================================================
+  * Copyright 2018-2023 Shanghai StarFive Technology Co., Ltd.
+================================================================
+
+spl_tool license:
+
+Valid-License-Identifier: GPL-2.0
+Valid-License-Identifier: GPL-2.0-only
+Valid-License-Identifier: GPL-2.0+
+Valid-License-Identifier: GPL-2.0-or-later
+SPDX-URL: https://spdx.org/licenses/GPL-2.0.html
+Usage-Guide:
+  To use this license in source code, put one of the following SPDX
+  tag/value pairs into a comment according to the placement
+  guidelines in the licensing rules documentation.
+  For 'GNU General Public License (GPL) version 2 only' use:
+    SPDX-License-Identifier: GPL-2.0
+  or
+    SPDX-License-Identifier: GPL-2.0-only
+  For 'GNU General Public License (GPL) version 2 or any later version' use:
+    SPDX-License-Identifier: GPL-2.0+
+  or
+    SPDX-License-Identifier: GPL-2.0-or-later
+License-Text:
+
+		    GNU GENERAL PUBLIC LICENSE
+		       Version 2, June 1991
+
+ Copyright (C) 1989, 1991 Free Software Foundation, Inc.
+                       51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+ Everyone is permitted to copy and distribute verbatim copies
+ of this license document, but changing it is not allowed.
+
+			    Preamble
+
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+License is intended to guarantee your freedom to share and change free
+software--to make sure the software is free for all its users.  This
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+Foundation's software and to any other program whose authors commit to
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+
+	    How to Apply These Terms to Your New Programs
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+    but WITHOUT ANY WARRANTY; without even the implied warranty of
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+This General Public License does not permit incorporating your program into
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diff --git a/util/riscv/starfive-jh7110-spl-tool/Makefile b/util/riscv/starfive-jh7110-spl-tool/Makefile
new file mode 100644
index 0000000000..c6b4d9b8c0
--- /dev/null
+++ b/util/riscv/starfive-jh7110-spl-tool/Makefile
@@ -0,0 +1,16 @@
+# SPDX-License-Identifier: GPL-2.0+
+override CFLAGS=-Wall -Wno-unused-result -Wno-format-truncation -O2
+
+SRCS = $(wildcard *.c)
+OBJS = $(SRCS:.c=.o)
+
+all: spl_tool
+
+%.o: %.c
+	$(CC) $(CFLAGS) -c -o $@ $<
+
+spl_tool: $(OBJS)
+	$(CC) $(CFLAGS) $(LDFLAGS) $(OBJS) -o $@
+
+clean:
+	rm -f *.o spl_tool
diff --git a/util/riscv/starfive-jh7110-spl-tool/README.md b/util/riscv/starfive-jh7110-spl-tool/README.md
new file mode 100644
index 0000000000..e9f61e7dda
--- /dev/null
+++ b/util/riscv/starfive-jh7110-spl-tool/README.md
@@ -0,0 +1,54 @@
+## DESCRIPTION
+
+spl_tool is a jh7110 signature tool used to generate spl header information and generate u-boot-spl.bin.normal.out.
+
+spl_tool can also fix the issue of emmc booting.
+
+## Prerequisites
+
+Install required additional packages:
+
+```bash
+$ sudo apt-get install gcc make git
+```
+
+## Build
+
+just run `make`
+
+```bash
+$ make
+```
+
+## Run
+
+usage
+
+```bash
+$ ./spl_tool  -h
+
+			StarFive spl tool
+
+usage:
+-c, --creat-splhdr	creat spl hdr
+-i, --fix-imghdr	fixed img hdr for emmc boot.
+-a, --spl-bak-addr	set backup SPL addr(default: 0x200000)
+-v, --version		set version (default: 0x01010101)
+-f, --file		input file name(spl/img)
+-h, --help		show this information
+```
+
+Generate uboot-spl.bin.normal.out
+
+```bash
+$./spl_tool -c -f $(Uboot_PATH)/spl/u-boot-spl.bin
+ubsplhdr.sofs:0x240, ubsplhdr.bofs:0x200000, ubsplhdr.vers:0x1010101 name:$(Uboot_PATH)/spl/u-boot-spl.bin
+SPL written to $(Uboot_PATH)/spl/u-boot-spl.bin.normal.out successfully.
+```
+
+Fix the emmc boot issue
+
+```bash
+$ ./spl_tool -i -f sdcard.img
+IMG  sdcard.img fixed hdr successfully.
+```
\ No newline at end of file
diff --git a/util/riscv/starfive-jh7110-spl-tool/crc32.c b/util/riscv/starfive-jh7110-spl-tool/crc32.c
new file mode 100644
index 0000000000..1394f97c9f
--- /dev/null
+++ b/util/riscv/starfive-jh7110-spl-tool/crc32.c
@@ -0,0 +1,35 @@
+// SPDX-License-Identifier: GPL-2.0+
+#include <sys/types.h>
+#include <stdlib.h>
+#include <stdint.h>
+
+static uint32_t crc32_reverse(uint32_t x)
+{
+	x = ((x & 0x55555555) << 1) | ((x >> 1) & 0x55555555);
+	x = ((x & 0x33333333) << 2) | ((x >> 2) & 0x33333333);
+	x = ((x & 0x0F0F0F0F) << 4) | ((x >> 4) & 0x0F0F0F0F);
+	x = (x << 24) | ((x & 0xFF00) << 8) | ((x >> 8) & 0xFF00) | (x >> 24);
+	return x;
+}
+
+uint32_t crc32(uint32_t iv, uint32_t sv, const void *data, size_t n)
+{
+	const unsigned char *ptr;
+	unsigned x;
+	uint32_t byte, crc;
+
+	crc = iv;
+	ptr = data;
+	while (n--) {
+		byte = *ptr++;
+		byte = crc32_reverse(byte);
+		for (x = 0; x < 8; x++, byte <<= 1) crc = ((crc ^ byte) & 0x80000000U) ? (crc << 1) ^ sv : (crc << 1);
+	}
+
+	return crc;
+}
+
+uint32_t crc32_final(uint32_t iv)
+{
+	return crc32_reverse(iv ^ ~0U);
+}
diff --git a/util/riscv/starfive-jh7110-spl-tool/spl_tool.c b/util/riscv/starfive-jh7110-spl-tool/spl_tool.c
new file mode 100644
index 0000000000..039e520dea
--- /dev/null
+++ b/util/riscv/starfive-jh7110-spl-tool/spl_tool.c
@@ -0,0 +1,244 @@
+// SPDX-License-Identifier: GPL-2.0+
+#define _GNU_SOURCE
+#include <sys/types.h>
+#include <sys/stat.h>
+#include <fcntl.h>
+#include <getopt.h>
+#include <stdio.h>
+#include <stdlib.h>
+#include <stdint.h>
+#include <string.h>
+#include <stdbool.h>
+#include <unistd.h>
+#include <endian.h>
+#include <errno.h>
+#include <limits.h>
+
+#define NOSIZE ((size_t)-1)
+
+extern uint32_t crc32(uint32_t iv, uint32_t sv, const void *data, size_t n);
+extern uint32_t crc32_final(uint32_t iv);
+
+/* all uint32_t ends up little endian in output header */
+struct __attribute__((__packed__)) ubootsplhdr {
+	uint32_t sofs;		/* offset of spl header: 64+256+256 = 0x240 */
+	uint32_t bofs;		/* SBL_BAK_OFFSET: Offset of backup SBL from Flash info start (from input_sbl_normal.cfg) */
+	uint8_t  zro2[636];
+	uint32_t vers;		/* version: shall be 0x01010101
+				 * (from https://doc-en.rvspace.org/VisionFive2/SWTRM/VisionFive2_SW_TRM/create_spl.html) */
+	uint32_t fsiz;		/* u-boot-spl.bin size in bytes */
+	uint32_t res1;		/* Offset from HDR to SPL_IMAGE, 0x400 (00 04 00 00) currently */
+	uint32_t crcs;		/* CRC32 of u-boot-spl.bin */
+	uint8_t  zro3[364];
+};
+
+struct hdr_conf_t {
+	const char name[PATH_MAX];
+	uint32_t vers;
+	uint32_t bofs;
+	bool creat_hdr_flag;
+	bool fixed_img_hdr_flag;
+};
+
+static struct ubootsplhdr ubsplhdr;
+static struct ubootsplhdr imghdr;
+static struct hdr_conf_t g_hdr_conf;
+
+static char ubootspl[181072-sizeof(struct ubootsplhdr)+1];
+static char outpath[PATH_MAX];
+
+#define DEFVERSID 0x01010101
+#define DEFBACKUP 0x200000U
+#define CRCFAILED 0x5A5A5A5A
+
+static void xerror(int errnoval, const char *s)
+{
+	if (errnoval) perror(s);
+	else fprintf(stderr, "%s\n", s);
+	exit(2);
+}
+
+static void usage(void)
+{
+	const char help[] = {
+		"\n            StarFive spl tool\n\n"
+		"usage:\n"
+		"-c, --creat-splhdr	creat spl hdr\n"
+		"-i, --fix-imghdr	fixed img hdr for emmc boot.\n"
+		"-a, --spl-bak-addr	set backup SPL addr(default: 0x200000)\n"
+		"-v, --version		set version (default: 0x01010101)\n"
+		"-f, --file		input file name(spl/img)\n"
+		"-h, --help		show this information\n"
+	};
+	puts(help);
+}
+
+static int parse_args(int argc, char **argv)
+{
+	uint32_t v;
+
+	enum {
+		OPTION_CREAD_HDR = 1,
+		OPTION_FIXED_HDR,
+		OPTION_SBL_BAK_OFFSET,
+		OPTION_VERSION,
+		OPTION_FILENAME,
+		OPTION_HELP,
+	};
+
+	static struct option long_options[] =
+	{
+		{"creat-splhdr" , no_argument, NULL, OPTION_CREAD_HDR},
+		{"fix-imghdr" , no_argument, NULL, OPTION_FIXED_HDR},
+		{"spl-bak-addr" , required_argument, NULL, OPTION_SBL_BAK_OFFSET},
+		{"version", required_argument, NULL, OPTION_VERSION},
+		{"file", required_argument, NULL, OPTION_FILENAME},
+		{"help", no_argument, NULL, OPTION_HELP},
+		{0, 0, 0, 0}
+	};
+
+	while (1)
+	{
+		/* getopt_long stores the option index here. */
+		int option_index = 0;
+
+		int c = getopt_long(argc, argv, "cio:v:f:h", long_options, &option_index);
+
+		/* Detect the end of the options. */
+		if (c == -1)
+		    break;
+
+		switch (c) {
+		case 0:
+			/* If this option set a flag, do nothing else now. */
+			if (long_options[option_index].flag != 0)
+			break;
+
+		case 'c':
+		case OPTION_CREAD_HDR:
+			g_hdr_conf.creat_hdr_flag = true;
+			g_hdr_conf.fixed_img_hdr_flag = false;
+			break;
+
+		case 'i':
+		case OPTION_FIXED_HDR:
+			g_hdr_conf.fixed_img_hdr_flag = true;
+			g_hdr_conf.creat_hdr_flag = false;
+			break;
+
+		case 'a':
+		case OPTION_SBL_BAK_OFFSET:
+			v = (uint32_t)strtoul(optarg, NULL, 16);
+			v = htole32(v);
+			g_hdr_conf.bofs = v;
+			break;
+
+		case 'v':
+		case OPTION_VERSION:
+			v = (uint32_t)strtoul(optarg, NULL, 16);
+			v = htole32(v);
+			g_hdr_conf.vers = v;
+			break;
+
+		case 'f':
+		case OPTION_FILENAME:
+			strcpy((char*)g_hdr_conf.name, optarg);
+			break;
+
+		case 'h':
+		case OPTION_HELP:
+			usage();
+			break;
+
+		default:
+			usage();
+			break;
+		}
+	}
+	return 0;
+}
+
+int spl_creat_hdr(struct hdr_conf_t *conf)
+{
+	int fd;
+	uint32_t v;
+	size_t sz;
+
+	if (!conf->creat_hdr_flag)
+		return 0;
+
+	ubsplhdr.sofs = htole32(0x240U);
+	ubsplhdr.res1 = htole32(0x400U);
+	ubsplhdr.bofs = conf->bofs ? conf->bofs : htole32(DEFBACKUP);
+	ubsplhdr.vers = conf->vers ? conf->vers : htole32(DEFVERSID);
+
+	printf("ubsplhdr.sofs:%#x, ubsplhdr.bofs:%#x, ubsplhdr.vers:%#x name:%s\n",
+		ubsplhdr.sofs, ubsplhdr.bofs, ubsplhdr.vers, conf->name);
+
+	fd = open(conf->name, O_RDONLY);
+	if (fd == -1) xerror(errno, conf->name);
+
+	sz = (size_t)read(fd, ubootspl, sizeof(ubootspl));
+	if (sz == NOSIZE) xerror(errno, conf->name);
+	if (sz >= (sizeof(ubootspl)))
+		xerror(0, "File too large! Please rebuild your SPL with -Os. Maximum allowed size is 180048 bytes.");
+	v = htole32((uint32_t)sz);
+	ubsplhdr.fsiz = v;
+
+	close(fd);
+	snprintf(outpath, sizeof(outpath), "%s.normal.out", conf->name);
+	fd = creat(outpath, 0666);
+	if (fd == -1) xerror(errno, outpath);
+
+	v = crc32(~0U, 0x04c11db7U, ubootspl, sz);
+	v = crc32_final(v);
+	v = htole32(v);
+	ubsplhdr.crcs = v;
+
+	write(fd, &ubsplhdr, sizeof(struct ubootsplhdr));
+	write(fd, ubootspl, sz);
+
+	close(fd);
+
+	printf("SPL written to %s successfully.\n", outpath);
+
+	return 0;
+}
+
+int img_fixed_hdr(struct hdr_conf_t *conf)
+{
+	int fd;
+	size_t sz;
+
+	if (!conf->fixed_img_hdr_flag)
+		return 0;
+
+	fd = open(conf->name, O_RDWR);
+	if (fd == -1) xerror(errno, conf->name);
+
+	sz = (size_t)read(fd, &imghdr, sizeof(imghdr));
+	if (sz == NOSIZE) xerror(errno, conf->name);
+
+	/* When starting with emmc, bootrom will read 0x0 instead of partition 0. (Known issues).
+	Read GPT PMBR+Header, then write the backup address at 0x4, and write the wrong CRC
+	check value at 0x290, so that bootrom CRC check fails and jump to the backup address
+	to load the real spl. */
+
+	imghdr.bofs = conf->bofs ? conf->bofs : htole32(DEFBACKUP);
+	imghdr.crcs = htole32(CRCFAILED);
+
+	lseek(fd, 0x0, SEEK_SET);
+	write(fd, &imghdr, sizeof(imghdr));
+	close(fd);
+
+	printf("IMG  %s fixed hdr successfully.\n", conf->name);
+
+	return 0;
+}
+
+int main(int argc, char **argv)
+{
+	parse_args(argc, argv);
+	spl_creat_hdr(&g_hdr_conf);
+	img_fixed_hdr(&g_hdr_conf);
+}

From 7c31377bf9e1fe7cffecf0e8c08bf7ab03a0e887 Mon Sep 17 00:00:00 2001
From: Maximilian Brune <maximilian.brune@9elements.com>
Date: Sun, 29 Sep 2024 13:27:33 +0200
Subject: [PATCH 0083/3886] util/lint/lint-000-license-headers: Add license

This adds the "GPL-2.0 OR MIT" license combination.
It is used in subsequent patches that adds source files originally from
the linux kernel.

OR operator:
https://web.archive.org/web/20240730192545/https://spdx.github.io/spdx-spec/v2.3/SPDX-license-expressions/#d42-disjunctive-or-operator

Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: I07c508aa6134b063801de36199af9a312a7d6bed
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84584
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
---
 util/lint/lint-000-license-headers | 1 +
 1 file changed, 1 insertion(+)

diff --git a/util/lint/lint-000-license-headers b/util/lint/lint-000-license-headers
index 44657d27c9..bff8bb48d0 100755
--- a/util/lint/lint-000-license-headers
+++ b/util/lint/lint-000-license-headers
@@ -121,6 +121,7 @@ check_for_license 'HPND-sell-variant'
 check_for_license 'ISC'
 check_for_license 'MIT'
 check_for_license 'X11'
+check_for_license 'GPL-2.0 OR MIT'
 
 # This is 4 clause ("with advertising") but the University of Berkeley
 # declared that 4th clause void, see

From 4e8943801b4a4ceed376070387fb90066eabc29d Mon Sep 17 00:00:00 2001
From: Maximilian Brune <maximilian.brune@9elements.com>
Date: Mon, 13 Jan 2025 18:00:15 +0100
Subject: [PATCH 0084/3886] payloads/external/Makefile.mk: Update linuxboot
 warning

Only print the warning if Linuxboot payload is actually selected,
because we don't care otherwise.

Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: I5008d685c52c1d4e0d7eba44c964c51a2a6f99c3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85957
Reviewed-by: Ana Carolina Cabral <ana.cpmelo95@gmail.com>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
---
 payloads/external/Makefile.mk | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/payloads/external/Makefile.mk b/payloads/external/Makefile.mk
index 299f1eee0b..c279121493 100644
--- a/payloads/external/Makefile.mk
+++ b/payloads/external/Makefile.mk
@@ -396,7 +396,10 @@ ifeq ($(CONFIG_LINUXBOOT_CROSS_COMPILE_PATH),"")
     CONFIG_LINUXBOOT_CROSS_COMPILE_PATH=$(CROSS_COMPILE_$(LINUXBOOT_CROSS_COMPILE_ARCH-y))
 endif # CONFIG_LINUXBOOT_CROSS_COMPILE_PATH
 else  # CONFIG_LINUXBOOT_CROSS_COMPILE
+ifeq ($(CONFIG_PAYLOAD_LINUXBOOT),y)
+    # only print warning when Linuxboot payload is actually selected
     $(warning "Using host toolchain to build Linuxboot")
+endif # CONFIG_PAYLOAD_LINUXBOOT
 endif # CONFIG_LINUXBOOT_CROSS_COMPILE
 .PHONY: linuxboot
 payloads/external/LinuxBoot/build/Image payloads/external/LinuxBoot/build/initramfs linuxboot:

From 4ab0e333ad88151815190f97d0f789bbb0b8fd7f Mon Sep 17 00:00:00 2001
From: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Date: Tue, 11 Feb 2025 15:59:25 +0800
Subject: [PATCH 0085/3886] mb/google/nissa/var/dirks: Update GPIO table

Configure buzzer to GPP_D2 based on schematic change.

BUG=b:389391653
TEST=emerge-nissa coreboot

Change-Id: Iefc6aefeae0a3a05ba04fb2718c6c3a3058de5f8
Signed-off-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86351
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/google/brya/variants/dirks/gpio.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/mainboard/google/brya/variants/dirks/gpio.c b/src/mainboard/google/brya/variants/dirks/gpio.c
index 94eaff5691..209ca047dc 100644
--- a/src/mainboard/google/brya/variants/dirks/gpio.c
+++ b/src/mainboard/google/brya/variants/dirks/gpio.c
@@ -19,8 +19,6 @@ static const struct pad_config override_gpio_table[] = {
 
 	/* B4 : LAN_PERST_L */
 	PAD_CFG_GPO(GPP_B4, 1, PLTRST),
-	/* B14 : SPKR ==> PWM_PP3300_BUZZER */
-	PAD_CFG_GPO_LOCK(GPP_B14, 0, LOCK_CONFIG),
 	/* B16 : I2C5_SDA ==> NC */
 	PAD_NC(GPP_B16, NONE),
 	/* B17 : I2C5_SCL ==> NC */
@@ -37,6 +35,8 @@ static const struct pad_config override_gpio_table[] = {
 	/* C7  : SML1DATA ==> NC */
 	PAD_NC(GPP_C7, NONE),
 
+	/* D2  :  PWM_PP3300_BUZZER */
+	PAD_CFG_GPO(GPP_D2, 0, DEEP),
 	/* D3  : ISH_GP3 ==> NC */
 	PAD_NC(GPP_D3, NONE),
 	/* D6  : SRCCLKREQ1# ==> NC */

From c60991870ec167483b566b78f2163c00df18b63c Mon Sep 17 00:00:00 2001
From: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Date: Tue, 11 Feb 2025 15:53:29 +0800
Subject: [PATCH 0086/3886] mb/google/nissa/var/dirks: Use a separate ec.h for
 dirks

Dirks are chromebox, so they need different settings in ec.h.
Add a new dirks baseboard ec.h and use it for dirks.Remove
everything related to:

- Lid
- Battery
- Built-in keyboard
- AC connect/disconnect
- Mode changes

BUG=b:389391653
TEST=emerge-nissa coreboot

Change-Id: I8089a2aff3032a4271212765f65881a09f42c1ae
Signed-off-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86354
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
---
 .../nissa/include/baseboard/dirks/ec.h        | 44 +++++++++++++++++++
 .../brya/variants/dirks/include/variant/ec.h  |  2 +-
 2 files changed, 45 insertions(+), 1 deletion(-)
 create mode 100644 src/mainboard/google/brya/variants/baseboard/nissa/include/baseboard/dirks/ec.h

diff --git a/src/mainboard/google/brya/variants/baseboard/nissa/include/baseboard/dirks/ec.h b/src/mainboard/google/brya/variants/baseboard/nissa/include/baseboard/dirks/ec.h
new file mode 100644
index 0000000000..d9697d7c3c
--- /dev/null
+++ b/src/mainboard/google/brya/variants/baseboard/nissa/include/baseboard/dirks/ec.h
@@ -0,0 +1,44 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#ifndef __BASEBOARD_EC_H__
+#define __BASEBOARD_EC_H__
+
+#include <ec/ec.h>
+#include <ec/google/chromeec/ec_commands.h>
+#include <baseboard/gpio.h>
+
+#define MAINBOARD_EC_SCI_EVENTS \
+	(EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_THRESHOLD) |\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_START)    |\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_STOP)     |\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_MKBP)              |\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_PD_MCU)            |\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_USB_MUX))
+#define MAINBOARD_EC_SMI_EVENTS 0
+/* EC can wake from S5 with power button */
+#define MAINBOARD_EC_S5_WAKE_EVENTS \
+	(EC_HOST_EVENT_MASK(EC_HOST_EVENT_POWER_BUTTON))
+/* EC can wake from S3 with power button */
+#define MAINBOARD_EC_S3_WAKE_EVENTS (MAINBOARD_EC_S5_WAKE_EVENTS)
+#define MAINBOARD_EC_S0IX_WAKE_EVENTS \
+	(MAINBOARD_EC_S3_WAKE_EVENTS |\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_USB_MUX)          |\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_HANG_DETECT))
+/* Log EC wake events plus EC shutdown events */
+#define MAINBOARD_EC_LOG_EVENTS \
+	(EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_SHUTDOWN) |\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_PANIC))
+/*
+ * ACPI related definitions for ASL code.
+ */
+/* Enable cros_ec_keyb device */
+#define EC_ENABLE_MKBP_DEVICE
+#define EC_ENABLE_WAKE_PIN      GPE_EC_WAKE
+/* Enable EC backed PD MCU device in ACPI */
+#define EC_ENABLE_PD_MCU_DEVICE
+#define SIO_EC_MEMMAP_ENABLE     /* EC Memory Map Resources */
+#define SIO_EC_HOST_ENABLE       /* EC Host Interface Resources */
+
+#define EC_ENABLE_SYNC_IRQ       /* Enable tight timestamp support */
+
+#endif /* __BASEBOARD_EC_H__ */
diff --git a/src/mainboard/google/brya/variants/dirks/include/variant/ec.h b/src/mainboard/google/brya/variants/dirks/include/variant/ec.h
index 7a2a6ff8b7..469e75c834 100644
--- a/src/mainboard/google/brya/variants/dirks/include/variant/ec.h
+++ b/src/mainboard/google/brya/variants/dirks/include/variant/ec.h
@@ -3,6 +3,6 @@
 #ifndef __VARIANT_EC_H__
 #define __VARIANT_EC_H__
 
-#include <baseboard/ec.h>
+#include <baseboard/dirks/ec.h>
 
 #endif

From fc9a192d3433eba1e8b191b0f2b1795cc9123fad Mon Sep 17 00:00:00 2001
From: Maximilian Brune <maximilian.brune@9elements.com>
Date: Sat, 4 Jan 2025 22:19:01 +0100
Subject: [PATCH 0087/3886] mb/emulation/spike-riscv/uart.c: Update UART
 address

Spike Simulator commit 191634d2854d implemented a ns16550 serial device
which puts the base address at 0x10000000.

Tested: Start Spike Simulator and see that coreboot prints onto the UART.

Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: I0e3db9d8b141c733bf609f906018096e3594ce83
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85852
Reviewed-by: Nicholas Chin <nic.c3.14@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/emulation/spike-riscv/uart.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/mainboard/emulation/spike-riscv/uart.c b/src/mainboard/emulation/spike-riscv/uart.c
index 4ea2466878..e93594c560 100644
--- a/src/mainboard/emulation/spike-riscv/uart.c
+++ b/src/mainboard/emulation/spike-riscv/uart.c
@@ -5,5 +5,5 @@
 
 uintptr_t uart_platform_base(unsigned int idx)
 {
-	return (uintptr_t)0x02100000;
+	return (uintptr_t)0x10000000;
 }

From ff353fe88de03c9b22d2bf3aa01fae00ac06090c Mon Sep 17 00:00:00 2001
From: Subrata Banik <subratabanik@google.com>
Date: Thu, 13 Feb 2025 10:09:32 +0530
Subject: [PATCH 0088/3886] mb/google/fatcat: Increase PL4 power limits for
 PTL-H variants

Increase PL4 power limit values for all Intel PTL-H variants on Fatcat
from 50000 to 65000 to ensure successful boot and adequate performance
with 45W and 65W USB-C adapters. This prevents system bottlenecks when
using lower-wattage power supplies.

BUG=b:395130929
TEST=Verified successful boot with 45W and 65W USB-C travel adapters,
as well as 96W/106W USB-C adapters.

Change-Id: I6073e748e9f8c7317f0ad9a1193699e34703bdba
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86388
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 .../google/fatcat/variants/baseboard/fatcat/ramstage.c    | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/src/mainboard/google/fatcat/variants/baseboard/fatcat/ramstage.c b/src/mainboard/google/fatcat/variants/baseboard/fatcat/ramstage.c
index a808c90f00..030b587579 100644
--- a/src/mainboard/google/fatcat/variants/baseboard/fatcat/ramstage.c
+++ b/src/mainboard/google/fatcat/variants/baseboard/fatcat/ramstage.c
@@ -16,7 +16,7 @@ const struct cpu_tdp_power_limits power_optimized_limits[] = {
 		.pl1_max_power = 25000,
 		.pl2_min_power = 50000,
 		.pl2_max_power = 50000,
-		.pl4_power = 50000 /* TODO: needs fine tuning */
+		.pl4_power = 65000
 	},
 	{
 		.mch_id = PCI_DID_INTEL_PTL_H_ID_2,
@@ -26,7 +26,7 @@ const struct cpu_tdp_power_limits power_optimized_limits[] = {
 		.pl1_max_power = 25000,
 		.pl2_min_power = 50000,
 		.pl2_max_power = 50000,
-		.pl4_power = 50000 /* TODO: needs fine tuning */
+		.pl4_power = 65000
 	},
 	{
 		.mch_id = PCI_DID_INTEL_PTL_H_ID_3,
@@ -36,7 +36,7 @@ const struct cpu_tdp_power_limits power_optimized_limits[] = {
 		.pl1_max_power = 25000,
 		.pl2_min_power = 50000,
 		.pl2_max_power = 50000,
-		.pl4_power = 50000 /* TODO: needs fine tuning */
+		.pl4_power = 65000
 	},
 	{
 		.mch_id = PCI_DID_INTEL_PTL_H_ID_4,
@@ -46,7 +46,7 @@ const struct cpu_tdp_power_limits power_optimized_limits[] = {
 		.pl1_max_power = 25000,
 		.pl2_min_power = 50000,
 		.pl2_max_power = 50000,
-		.pl4_power = 50000 /* TODO: needs fine tuning */
+		.pl4_power = 65000
 	},
 };
 

From 121ab8e2013f448419ec5192e73b9036a922b692 Mon Sep 17 00:00:00 2001
From: Subrata Banik <subratabanik@google.com>
Date: Wed, 5 Feb 2025 09:32:28 +0000
Subject: [PATCH 0089/3886] lib: Refactor ux_locales_get_text API

This patch refactors the `ux_locales_get_text` API to handle fallback
text (English) internally, rather than relying on the caller. It
introduces message IDs for lookups, enabling the API to locate both
the UX locale name and fallback text based on the ID.

With this patch, `ux_locales_get_text` API locates UX locales message
based on message ID.

`ux_locales_get_text` retrieves fallback text message depending
upon the message ID if UX locales is not available.

This centralizes fallback handling and simplifies adding future
messages without per-SoC duplication.

BUG=b:339673254
TEST=Built and booted google/brox. Verified eSOL display.

Change-Id: I4952802396265b9ee8d164d6e43a7f2b3599d6c0
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86283
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
---
 src/include/ux_locales.h                      |  9 +-
 src/lib/ux_locales.c                          | 37 ++++++--
 src/soc/intel/alderlake/romstage/ux.c         | 10 +-
 .../intel/meteorlake/romstage/fsp_params.c    |  9 +-
 tests/lib/ux_locales-test.c                   | 95 +++++++++----------
 5 files changed, 85 insertions(+), 75 deletions(-)

diff --git a/src/include/ux_locales.h b/src/include/ux_locales.h
index 1affd925d1..e8710839b0 100644
--- a/src/include/ux_locales.h
+++ b/src/include/ux_locales.h
@@ -5,14 +5,19 @@
 
 #include <types.h>
 
+enum ux_locale_msg {
+	UX_LOCALE_MSG_MEMORY_TRAINING,
+	UX_LOCALE_MSG_NUM,
+};
+
 /* Unmap the preram_locales if it has been mapped. No-op otherwise. */
 void ux_locales_unmap(void);
 
 /*
- * Get the localized text for a given string name.
+ * Get the localized text for a given message ID as per `enum ux_locale_msg`.
  * This function will try to read the language ID from vboot API, and search the
  * corresponding translation from CBFS preram_locales.
  */
-const char *ux_locales_get_text(const char *name);
+const char *ux_locales_get_text(enum ux_locale_msg msg_id);
 
 #endif  // _UX_LOCALES_H_
diff --git a/src/lib/ux_locales.c b/src/lib/ux_locales.c
index b389548955..b9f153772e 100644
--- a/src/lib/ux_locales.c
+++ b/src/lib/ux_locales.c
@@ -1,6 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
 #include <cbfs.h>
+#include <commonlib/bsd/helpers.h>
 #include <console/console.h>
 #include <security/vboot/misc.h>
 #include <stddef.h>
@@ -20,6 +21,18 @@
 #define DELIM_STR 0x00
 #define DELIM_NAME 0x01
 
+/* Mapping of different default UX local message based on message ID */
+static const struct {
+	const char *ux_locale_name;
+	const char *ux_locale_fallback_text;
+} ux_locale_msg_list[] = {
+	[UX_LOCALE_MSG_MEMORY_TRAINING] = {
+		"memory_training_desc",
+		"Your device is finishing an update. This may take 1-2 minutes.\n"
+		"Please do not turn off your device."
+	},
+};
+
 /*
  * Devices which support early vga have the capability to show localized text in
  * Code Page 437 encoding. (see src/drivers/pc80/vga/vga_font_8x16.c)
@@ -113,18 +126,28 @@ static size_t search_for_id(const char *data, size_t offset, size_t size,
 	return search_for(data, offset, size, int_to_str, DELIM_STR);
 }
 
-const char *ux_locales_get_text(const char *name)
+const char *ux_locales_get_text(enum ux_locale_msg msg_id)
 {
 	const char *data;
 	size_t size, offset, name_offset, next_name_offset, next;
 	uint32_t lang_id = 0; /* default language English (0) */
 	unsigned char version;
+	const char *name;
+	const char *fallback_text;
+
+	if (msg_id >= UX_LOCALE_MSG_NUM) {
+		printk(BIOS_ERR, "%s: Unknown message id = %d.\n", __func__, msg_id);
+		return "Trying to display an unknown message?";
+	}
+
+	name = ux_locale_msg_list[msg_id].ux_locale_name;
+	fallback_text = ux_locale_msg_list[msg_id].ux_locale_fallback_text;
 
 	data = locales_get_map(&size, false);
 	if (!data || size == 0) {
 		printk(BIOS_ERR, "%s: %s not found.\n", __func__,
 		       PRERAM_LOCALES_NAME);
-		return NULL;
+		return fallback_text;
 	}
 
 	if (CONFIG(VBOOT)) {
@@ -146,14 +169,14 @@ const char *ux_locales_get_text(const char *name)
 	if (version != PRERAM_LOCALES_VERSION_BYTE) {
 		printk(BIOS_ERR, "%s: The version %u is not the expected one %u\n",
 		       __func__, version, PRERAM_LOCALES_VERSION_BYTE);
-		return NULL;
+		return fallback_text;
 	}
 
 	/* Search for name. Skip the version byte. */
 	offset = search_for_name(data, 1, size, name);
 	if (offset >= size) {
 		printk(BIOS_ERR, "%s: Name %s not found.\n", __func__, name);
-		return NULL;
+		return fallback_text;
 	}
 	name_offset = offset;
 
@@ -171,21 +194,21 @@ const char *ux_locales_get_text(const char *name)
 			offset = search_for_id(data, name_offset, next_name_offset, 0);
 		if (offset >= next_name_offset) {
 			printk(BIOS_ERR, "%s: Neither %d nor 0 found.\n", __func__, lang_id);
-			return NULL;
+			return fallback_text;
 		}
 	}
 
 	/* Move to the corresponding localized_string. */
 	offset = move_next(data, offset, next_name_offset, DELIM_STR);
 	if (offset >= next_name_offset)
-		return NULL;
+		return fallback_text;
 
 	/* Validity check that the returned string must be NULL terminated. */
 	next = move_next(data, offset, next_name_offset, DELIM_STR) - 1;
 	if (next >= next_name_offset || data[next] != '\0') {
 		printk(BIOS_ERR, "%s: %s is not NULL terminated.\n",
 		       __func__, PRERAM_LOCALES_NAME);
-		return NULL;
+		return fallback_text;
 	}
 
 	return data + offset;
diff --git a/src/soc/intel/alderlake/romstage/ux.c b/src/soc/intel/alderlake/romstage/ux.c
index 0fb73c188d..d0961c51ec 100644
--- a/src/soc/intel/alderlake/romstage/ux.c
+++ b/src/soc/intel/alderlake/romstage/ux.c
@@ -8,8 +8,6 @@
 
 #include "ux.h"
 
-#define UX_MEMORY_TRAINING_DESC "memory_training_desc"
-
 bool ux_inform_user_of_update_operation(const char *name)
 {
 	timestamp_add_now(TS_ESOL_START);
@@ -22,12 +20,8 @@ bool ux_inform_user_of_update_operation(const char *name)
 
 	printk(BIOS_INFO, "Informing user on-display of %s.\n", name);
 
-	const char *text = ux_locales_get_text(UX_MEMORY_TRAINING_DESC);
-	/* No localized text found; fallback to built-in English. */
-	if (!text)
-		text = "Your device is finishing an update. "
-		       "This may take 1-2 minutes.\n"
-		       "Please do not turn off your device.";
+	const char *text = ux_locales_get_text(UX_LOCALE_MSG_MEMORY_TRAINING);
+
 	vga_write_text(VGA_TEXT_CENTER, VGA_TEXT_HORIZONTAL_MIDDLE,
 		       (const unsigned char *)text);
 	ux_locales_unmap();
diff --git a/src/soc/intel/meteorlake/romstage/fsp_params.c b/src/soc/intel/meteorlake/romstage/fsp_params.c
index 82706ed3bf..dd9d2b54c6 100644
--- a/src/soc/intel/meteorlake/romstage/fsp_params.c
+++ b/src/soc/intel/meteorlake/romstage/fsp_params.c
@@ -436,8 +436,6 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg,
 		fill_fspm_params[i](m_cfg, config);
 }
 
-#define UX_MEMORY_TRAINING_DESC	"memory_training_desc"
-
 #define VGA_INIT_CONTROL_ENABLE		BIT(0)
 /* Tear down legacy VGA mode before exiting FSP-M. */
 #define VGA_INIT_CONTROL_TEAR_DOWN	BIT(1)
@@ -465,12 +463,7 @@ static void fill_fspm_sign_of_life(FSP_M_CONFIG *m_cfg,
 	if (!vga_init_control)
 		return;
 
-	const char *text = ux_locales_get_text(UX_MEMORY_TRAINING_DESC);
-	/* No localized text found; fallback to built-in English. */
-	if (!text)
-		text = "Your device is finishing an update. "
-		       "This may take 1-2 minutes.\n"
-		       "Please do not turn off your device.";
+	const char *text = ux_locales_get_text(UX_LOCALE_MSG_MEMORY_TRAINING);
 
 	vbt = cbfs_map("vbt.bin", &vbt_size);
 	if (!vbt) {
diff --git a/tests/lib/ux_locales-test.c b/tests/lib/ux_locales-test.c
index 5fe18e773c..63f2f56318 100644
--- a/tests/lib/ux_locales-test.c
+++ b/tests/lib/ux_locales-test.c
@@ -7,22 +7,14 @@
 #include <ux_locales.h>
 #include <vb2_api.h>
 
-#define DATA_DEFAULT                                                                           \
-	(                                                                                      \
-		"\x01"  /* Version. */                                                         \
-		"name_1\x00"  /* name_1, langs = [0, 2, 30]. */                                \
-		"0\x00translation_1_0\x00"                                                     \
-		"2\x00translation_1_2\x00"                                                     \
-		"30\x00translation_1_30\x00"                                                   \
-		"\x01"                                                                         \
-		"name_15\x00"  /* name_15, langs = [4, 25, 60]. */                             \
-		"4\x00translation_15_4\x00"                                                    \
-		"25\x00translation_15_25\x00"                                                  \
-		"60\x00translation_15_60\x00"                                                  \
-		"\x01"                                                                         \
-		"name_20\x00"  /* name_20, langs = [8]. */                                     \
-		"8\x00translation_20_8\x00"                                                    \
-		"\x01"                                                                         \
+#define DATA_DEFAULT \
+	( \
+		"\x01" /* Version. */                                                       \
+		"memory_training_desc\x00" /* memory_training_desc, langs = [0, 2, 30]. */  \
+		"0\x00memory_training_desc_0\x00"                                           \
+		"2\x00memory_training_desc_2\x00"                                           \
+		"30\x00memory_training_desc_30\x00"                                         \
+		"\x01"                                                                      \
 	)
 const unsigned char data_default[] = DATA_DEFAULT;
 
@@ -73,7 +65,7 @@ struct vb2_context *vboot_get_context(void)
 
 /* Test states for test_ux_locales_get_text with valid CBFS data. */
 struct ux_locales_test_state {
-	const char *name;
+	enum ux_locale_msg msg_id;
 	uint32_t lang_id;
 	const char *expect;
 };
@@ -116,9 +108,12 @@ static void test_ux_locales_get_text(void **state)
 	struct ux_locales_test_state *s = *state;
 	const char *ret;
 
-	will_return(_cbfs_alloc, true);
-	will_return(vb2api_get_locale_id, s->lang_id);
-	ret = ux_locales_get_text(s->name);
+	if (s->msg_id < UX_LOCALE_MSG_NUM) {
+		will_return(_cbfs_alloc, true);
+		will_return(vb2api_get_locale_id, s->lang_id);
+	}
+
+	ret = ux_locales_get_text(s->msg_id);
 	if (s->expect) {
 		assert_non_null(ret);
 		assert_string_equal(ret, s->expect);
@@ -131,14 +126,18 @@ static void test_ux_locales_bad_cbfs(void **state)
 {
 	will_return(_cbfs_alloc, false);
 	will_return_maybe(vb2api_get_locale_id, 0);
-	assert_null(ux_locales_get_text("name_1"));
+	assert_string_equal(ux_locales_get_text(UX_LOCALE_MSG_MEMORY_TRAINING),
+		 "Your device is finishing an update. This may take 1-2 minutes.\n"
+		 "Please do not turn off your device.");
 }
 
 static void test_ux_locales_bad_version(void **state)
 {
 	will_return(_cbfs_alloc, true);
 	will_return(vb2api_get_locale_id, 0);
-	assert_null(ux_locales_get_text("name_1"));
+	assert_string_equal(ux_locales_get_text(UX_LOCALE_MSG_MEMORY_TRAINING),
+		 "Your device is finishing an update. This may take 1-2 minutes.\n"
+		 "Please do not turn off your device.");
 }
 
 static void test_ux_locales_two_calls(void **state)
@@ -148,26 +147,26 @@ static void test_ux_locales_two_calls(void **state)
 	/* We do not need to ensure that we cached the cbfs region. */
 	will_return_always(_cbfs_alloc, true);
 
-	/* Call #1: read (15, 60). */
-	will_return(vb2api_get_locale_id, 60);
-	ret = ux_locales_get_text("name_15");
+	/* Call #1: read (1, 30). */
+	will_return(vb2api_get_locale_id, 30);
+	ret = ux_locales_get_text(UX_LOCALE_MSG_MEMORY_TRAINING);
 	assert_non_null(ret);
-	assert_string_equal(ret, "translation_15_60");
+	assert_string_equal(ret, "memory_training_desc_30");
 
 	/* Call #2: read (1, 0). */
 	will_return(vb2api_get_locale_id, 0);
-	ret = ux_locales_get_text("name_1");
+	ret = ux_locales_get_text(UX_LOCALE_MSG_MEMORY_TRAINING);
 	assert_non_null(ret);
-	assert_string_equal(ret, "translation_1_0");
+	assert_string_equal(ret, "memory_training_desc_0");
 }
 
 static void test_ux_locales_null_terminated(void **state)
 {
 	will_return_always(_cbfs_alloc, true);
-	will_return_always(vb2api_get_locale_id, 8);
+	will_return_always(vb2api_get_locale_id, 30);
 
 	/* Verify the access to the very last text. */
-	assert_non_null(ux_locales_get_text("name_20"));
+	assert_non_null(ux_locales_get_text(UX_LOCALE_MSG_MEMORY_TRAINING));
 
 	/* Modify the last 2 bytes from "\x00\x01" to "XX" and unmap, */
 	data.raw[data.size - 1] = 'X';
@@ -175,24 +174,27 @@ static void test_ux_locales_null_terminated(void **state)
 	ux_locales_unmap();
 
 	/* The last few characters are now changed so that the data is not NULL terminated.
-	   This will prevent us from accessing the last text. */
-	assert_null(ux_locales_get_text("name_20"));
+	   This will prevent us from accessing the last text therefore, make use of fallback
+	   text message */
+	assert_string_equal(ux_locales_get_text(UX_LOCALE_MSG_MEMORY_TRAINING),
+			 "Your device is finishing an update. This may take 1-2 minutes.\n"
+			 "Please do not turn off your device.");
 }
 
 /*
- * This macro helps test ux_locales_get_text with `_name` and `_lang_id`.
+ * This macro helps test ux_locales_get_text with `_msg_id` and `_lang_id`.
  * If `_expect` is NULL, then the function should not find anything.
  * Otherwise, the function should find the corresponding expect value.
  */
-#define UX_LOCALES_GET_TEXT_TEST(_name, _lang_id, _expect)                                     \
+#define UX_LOCALES_GET_TEXT_TEST(_msg_id, _lang_id, _expect)                               \
 	((struct CMUnitTest) {                                                                 \
-		.name = "test_ux_locales_get_text(name=" _name ", lang_id=" #_lang_id          \
+		.name = "test_ux_locales_get_text(msg_id=" #_msg_id ", lang_id=" #_lang_id          \
 			", expect=" #_expect ")",                                              \
 		.test_func = test_ux_locales_get_text,                                         \
 		.setup_func = setup_default,                                                   \
 		.teardown_func = teardown_unmap,                                               \
 		.initial_state = &(struct ux_locales_test_state) {                             \
-			.name = _name,                                                         \
+			.msg_id = _msg_id,                                                         \
 			.lang_id = _lang_id,                                                   \
 			.expect = _expect,                                                     \
 		},                                                                             \
@@ -202,21 +204,14 @@ int main(void)
 {
 	const struct CMUnitTest tests[] = {
 		/* Get text successfully. */
-		UX_LOCALES_GET_TEXT_TEST("name_1", 0, "translation_1_0"),
-		/* Get text with name and id both in the middle. */
-		UX_LOCALES_GET_TEXT_TEST("name_15", 25, "translation_15_25"),
-		/* Ensure we check the whole string of 'name'.
-		   ('name_2' is the prefix of 'name_20') */
-		UX_LOCALES_GET_TEXT_TEST("name_2", 3, NULL),
-		/* Ensure we check the whole string of 'lang_id'.
-		   (id:'2' is the prefix of id:'25' in 'name_15') */
-		UX_LOCALES_GET_TEXT_TEST("name_15", 2, NULL),
-		/* Ensure we will fallback to 0. */
-		UX_LOCALES_GET_TEXT_TEST("name_1", 7, "translation_1_0"),
-		/* Do not search for locale id with unmatched name. */
-		UX_LOCALES_GET_TEXT_TEST("name_15", 8, NULL),
+		UX_LOCALES_GET_TEXT_TEST(UX_LOCALE_MSG_MEMORY_TRAINING, 0, "memory_training_desc_0"),
+		UX_LOCALES_GET_TEXT_TEST(UX_LOCALE_MSG_MEMORY_TRAINING, 2, "memory_training_desc_2"),
+		/* Check the whole string of lang_id. */
+		UX_LOCALES_GET_TEXT_TEST(UX_LOCALE_MSG_MEMORY_TRAINING, 3, "memory_training_desc_0"),
 		/* Validity check of lang_id > 100. We will fallback to 0. */
-		UX_LOCALES_GET_TEXT_TEST("name_1", 100, "translation_1_0"),
+		UX_LOCALES_GET_TEXT_TEST(UX_LOCALE_MSG_MEMORY_TRAINING, 100, "memory_training_desc_0"),
+		/* Ensure we show fallback message if `msg_id >= UX_LOCALE_MSG_NUM` */
+		UX_LOCALES_GET_TEXT_TEST(UX_LOCALE_MSG_NUM, 0, "Trying to display an unknown message?"),
 		/* cbfs not found. */
 		cmocka_unit_test_setup_teardown(test_ux_locales_bad_cbfs, setup_default,
 						teardown_unmap),

From cf6f4920995ac2424065daa102023d870e0af496 Mon Sep 17 00:00:00 2001
From: Subrata Banik <subratabanik@google.com>
Date: Wed, 5 Feb 2025 09:52:18 +0000
Subject: [PATCH 0090/3886] soc/intel/alderlake: Use helper for UX messages

This commit introduces `ux_inform_user_of_operation` to reduce code
duplication when displaying UX messages.

`ux_inform_user_of_update_operation` now calls this helper, passing
the message ID. This allows easier addition of other UX messages.

BUG=b:339673254
TEST=Built and booted google/brox. Verified display eSOL.

Change-Id: Ib31f7633e7b3f84122419e4ce39e2b5044cb9a96
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86278
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
---
 src/soc/intel/alderlake/romstage/ux.c | 12 ++++++++----
 1 file changed, 8 insertions(+), 4 deletions(-)

diff --git a/src/soc/intel/alderlake/romstage/ux.c b/src/soc/intel/alderlake/romstage/ux.c
index d0961c51ec..4e647275ce 100644
--- a/src/soc/intel/alderlake/romstage/ux.c
+++ b/src/soc/intel/alderlake/romstage/ux.c
@@ -8,19 +8,18 @@
 
 #include "ux.h"
 
-bool ux_inform_user_of_update_operation(const char *name)
+static bool ux_inform_user_of_operation(const char *name, enum ux_locale_msg id)
 {
 	timestamp_add_now(TS_ESOL_START);
 
-	if (!CONFIG(CHROMEOS_ENABLE_ESOL) ||
-	    !early_graphics_init()) {
+	if (!CONFIG(CHROMEOS_ENABLE_ESOL) || !early_graphics_init()) {
 		timestamp_add_now(TS_ESOL_END);
 		return false;
 	}
 
 	printk(BIOS_INFO, "Informing user on-display of %s.\n", name);
 
-	const char *text = ux_locales_get_text(UX_LOCALE_MSG_MEMORY_TRAINING);
+	const char *text = ux_locales_get_text(id);
 
 	vga_write_text(VGA_TEXT_CENTER, VGA_TEXT_HORIZONTAL_MIDDLE,
 		       (const unsigned char *)text);
@@ -28,3 +27,8 @@ bool ux_inform_user_of_update_operation(const char *name)
 	timestamp_add_now(TS_ESOL_END);
 	return true;
 }
+
+bool ux_inform_user_of_update_operation(const char *name)
+{
+	return ux_inform_user_of_operation(name, UX_LOCALE_MSG_MEMORY_TRAINING);
+}

From f8381b902398bddf81a980e8e690523a18b063c5 Mon Sep 17 00:00:00 2001
From: Subrata Banik <subratabanik@google.com>
Date: Fri, 7 Feb 2025 07:42:01 +0000
Subject: [PATCH 0091/3886] lib: Add low battery UX locale message

This commit adds a new UX locale message to display a warning when the
battery is critically low.

The message informs the user about the low battery and indicates that
the system is shutting down.

This change ensures that users are notified before the system
unexpectedly shuts down due to low battery.

BUG=b:339673254
TEST=Built and booted google/brox.

Change-Id: I75c7a0d4d439901098c7f17a1dc90355307116ac
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86284
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
---
 src/include/ux_locales.h    |  1 +
 src/lib/ux_locales.c        |  4 ++++
 tests/lib/ux_locales-test.c | 16 +++++++++++-----
 3 files changed, 16 insertions(+), 5 deletions(-)

diff --git a/src/include/ux_locales.h b/src/include/ux_locales.h
index e8710839b0..35c56b7c4d 100644
--- a/src/include/ux_locales.h
+++ b/src/include/ux_locales.h
@@ -7,6 +7,7 @@
 
 enum ux_locale_msg {
 	UX_LOCALE_MSG_MEMORY_TRAINING,
+	UX_LOCALE_MSG_LOW_BATTERY,
 	UX_LOCALE_MSG_NUM,
 };
 
diff --git a/src/lib/ux_locales.c b/src/lib/ux_locales.c
index b9f153772e..528a5ae178 100644
--- a/src/lib/ux_locales.c
+++ b/src/lib/ux_locales.c
@@ -31,6 +31,10 @@ static const struct {
 		"Your device is finishing an update. This may take 1-2 minutes.\n"
 		"Please do not turn off your device."
 	},
+	[UX_LOCALE_MSG_LOW_BATTERY] = {
+		"low_battery_desc",
+		"Battery low. Shutting down."
+	},
 };
 
 /*
diff --git a/tests/lib/ux_locales-test.c b/tests/lib/ux_locales-test.c
index 63f2f56318..4edac5c9d2 100644
--- a/tests/lib/ux_locales-test.c
+++ b/tests/lib/ux_locales-test.c
@@ -15,6 +15,9 @@
 		"2\x00memory_training_desc_2\x00"                                           \
 		"30\x00memory_training_desc_30\x00"                                         \
 		"\x01"                                                                      \
+		"low_battery_desc\x00" /* low_battery_desc, langs = [8]. */                 \
+		"8\x00low_battery_desc_8\x00"                                               \
+		"\x01"                                                                      \
 	)
 const unsigned char data_default[] = DATA_DEFAULT;
 
@@ -163,10 +166,10 @@ static void test_ux_locales_two_calls(void **state)
 static void test_ux_locales_null_terminated(void **state)
 {
 	will_return_always(_cbfs_alloc, true);
-	will_return_always(vb2api_get_locale_id, 30);
+	will_return_always(vb2api_get_locale_id, 8);
 
 	/* Verify the access to the very last text. */
-	assert_non_null(ux_locales_get_text(UX_LOCALE_MSG_MEMORY_TRAINING));
+	assert_non_null(ux_locales_get_text(UX_LOCALE_MSG_LOW_BATTERY));
 
 	/* Modify the last 2 bytes from "\x00\x01" to "XX" and unmap, */
 	data.raw[data.size - 1] = 'X';
@@ -176,9 +179,8 @@ static void test_ux_locales_null_terminated(void **state)
 	/* The last few characters are now changed so that the data is not NULL terminated.
 	   This will prevent us from accessing the last text therefore, make use of fallback
 	   text message */
-	assert_string_equal(ux_locales_get_text(UX_LOCALE_MSG_MEMORY_TRAINING),
-			 "Your device is finishing an update. This may take 1-2 minutes.\n"
-			 "Please do not turn off your device.");
+	assert_string_equal(ux_locales_get_text(UX_LOCALE_MSG_LOW_BATTERY),
+			 "Battery low. Shutting down.");
 }
 
 /*
@@ -206,12 +208,16 @@ int main(void)
 		/* Get text successfully. */
 		UX_LOCALES_GET_TEXT_TEST(UX_LOCALE_MSG_MEMORY_TRAINING, 0, "memory_training_desc_0"),
 		UX_LOCALES_GET_TEXT_TEST(UX_LOCALE_MSG_MEMORY_TRAINING, 2, "memory_training_desc_2"),
+		UX_LOCALES_GET_TEXT_TEST(UX_LOCALE_MSG_LOW_BATTERY, 8, "low_battery_desc_8"),
 		/* Check the whole string of lang_id. */
 		UX_LOCALES_GET_TEXT_TEST(UX_LOCALE_MSG_MEMORY_TRAINING, 3, "memory_training_desc_0"),
 		/* Validity check of lang_id > 100. We will fallback to 0. */
 		UX_LOCALES_GET_TEXT_TEST(UX_LOCALE_MSG_MEMORY_TRAINING, 100, "memory_training_desc_0"),
 		/* Ensure we show fallback message if `msg_id >= UX_LOCALE_MSG_NUM` */
 		UX_LOCALES_GET_TEXT_TEST(UX_LOCALE_MSG_NUM, 0, "Trying to display an unknown message?"),
+		/* Do not search for locale id with unmatched name. */
+		UX_LOCALES_GET_TEXT_TEST(UX_LOCALE_MSG_LOW_BATTERY, 4,
+			 "Battery low. Shutting down."),
 		/* cbfs not found. */
 		cmocka_unit_test_setup_teardown(test_ux_locales_bad_cbfs, setup_default,
 						teardown_unmap),

From e5949cfef846f969c7631c2661230a14cb424b0a Mon Sep 17 00:00:00 2001
From: Subrata Banik <subratabanik@google.com>
Date: Thu, 30 Jan 2025 09:49:48 +0000
Subject: [PATCH 0092/3886] soc/intel/alderlake: Display low battery message on
 screen
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

This commit adds a function ux_inform_user_of_poweroff_operation
to display a message on the screen when the system is powering off due
to critically low battery. The message is centered on the screen and
displays a localized string "Battery critically low. Shutting down.".
If no localized string is found, a default English message is displayed.

This implementation relies on CHROMEOS_ENABLE_ESOL Kconfig which is used
to render text message for early sign-of-life.

BUG=b:339673254
TEST=Able to capture the eventlog for low battery boot event.

Change-Id: I3b24d2c89ade8cc62b7e47c487d52d47b7f3376d
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86224
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/soc/intel/alderlake/romstage/ux.c | 5 +++++
 src/soc/intel/alderlake/romstage/ux.h | 1 +
 2 files changed, 6 insertions(+)

diff --git a/src/soc/intel/alderlake/romstage/ux.c b/src/soc/intel/alderlake/romstage/ux.c
index 4e647275ce..03e6acdaa5 100644
--- a/src/soc/intel/alderlake/romstage/ux.c
+++ b/src/soc/intel/alderlake/romstage/ux.c
@@ -32,3 +32,8 @@ bool ux_inform_user_of_update_operation(const char *name)
 {
 	return ux_inform_user_of_operation(name, UX_LOCALE_MSG_MEMORY_TRAINING);
 }
+
+bool ux_inform_user_of_poweroff_operation(const char *name)
+{
+	return ux_inform_user_of_operation(name, UX_LOCALE_MSG_LOW_BATTERY);
+}
diff --git a/src/soc/intel/alderlake/romstage/ux.h b/src/soc/intel/alderlake/romstage/ux.h
index 14c10e7ffd..c556c63df1 100644
--- a/src/soc/intel/alderlake/romstage/ux.h
+++ b/src/soc/intel/alderlake/romstage/ux.h
@@ -4,5 +4,6 @@
 #define _SOC_INTEL_ALDERLAKE_ROMSTAGE_UX_H_
 
 bool ux_inform_user_of_update_operation(const char *name);
+bool ux_inform_user_of_poweroff_operation(const char *name);
 
 #endif /* _SOC_INTEL_ALDERLAKE_ROMSTAGE_UX_H_ */

From ae0adb7c160180652f2234cc631ffb5d88bdb428 Mon Sep 17 00:00:00 2001
From: Subrata Banik <subratabanik@google.com>
Date: Fri, 14 Feb 2025 09:37:09 +0000
Subject: [PATCH 0093/3886] lib: Introduce early power off support Kconfig
 option

This commit introduces the `HAVE_EARLY_POWEROFF_SUPPORT` Kconfig option
and the `platform_do_early_poweroff()` API.

The Kconfig option enables platform-specific early power off support,
which is often required on Intel platforms. The corresponding API allows
platforms to implement the necessary hardware operations for early power
off, typically before memory initialization.

BUG=b:339673254
TEST=Able to build and boot google/brox.

Change-Id: I05b9882e100825a4fb733163a65f820c8c943361
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86417
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/include/reset.h | 15 +++++++++++++++
 src/lib/Kconfig     | 16 ++++++++++++++++
 2 files changed, 31 insertions(+)

diff --git a/src/include/reset.h b/src/include/reset.h
index 95fe0660ad..a5d5aecf4f 100644
--- a/src/include/reset.h
+++ b/src/include/reset.h
@@ -41,4 +41,19 @@ __noreturn void board_reset(void);
  */
 void do_board_reset(void);
 
+/*
+ * Performs platform-specific actions for early power off.
+ *
+ * This function handles the necessary steps to initiate an early power off
+ * sequence. This might involve configuring specific hardware registers,
+ * sending commands to power management controllers, or performing other
+ * platform-specific operations. It is crucial that this
+ * function is implemented correctly to ensure a clean and controlled shutdown.
+ *
+ * Note: Issuing power off early before memory initialization is not supported use case on
+ *       Intel chipset, therefore, it might need a special platform specific handing
+ *       to power-off the platform early.
+ */
+void platform_do_early_poweroff(void);
+
 #endif
diff --git a/src/lib/Kconfig b/src/lib/Kconfig
index 2c1a93cff1..ad706261b8 100644
--- a/src/lib/Kconfig
+++ b/src/lib/Kconfig
@@ -159,3 +159,19 @@ config PROBE_RAM
 config HAVE_CUSTOM_BMP_LOGO
 	def_bool n
 	depends on BMP_LOGO
+
+config HAVE_EARLY_POWEROFF_SUPPORT
+	bool
+	help
+	  Enable platform-specific early power off support.
+
+	  This option should be selected if the platform requires special handling
+	  to power off the system before memory initialization. This is often
+	  necessary on Intel platforms, as directly powering off before memory
+	  initialization is typically not supported by the chipset.
+
+	  Selecting this option indicates that the platform implements the
+	  `platform_do_early_poweroff()` function, which performs the
+	  necessary hardware operations to initiate an early power off sequence.
+	  This might involve configuring hardware registers, sending commands to
+	  power management controllers, or other platform-specific operations.

From 0fe338c88b06d70c5f7e64efcabf1991068daf98 Mon Sep 17 00:00:00 2001
From: Subrata Banik <subratabanik@google.com>
Date: Fri, 14 Feb 2025 09:42:22 +0000
Subject: [PATCH 0094/3886] soc/intel/cmn/pmc: Add support for early power off

This commit adds support for early power off on Intel platforms
along with existing PMC based implementation to support power off
at later stage (like ramstage).

A new function, `platform_do_early_poweroff`, is added to the
pmclib to handle platform-specific early power off procedures.
This function is called before memory initialization (in romstage or
earlier).

Note: While Intel chipsets do not support power off before silicon
initialization, this change leverages Chrome EC APIs to enable power off
in romstage for low-battery boot on ChromeOS devices. Power off failures
in ramstage prior to FSP-S are outside the scope of this change.

BUG=b:339673254
TEST=Able to build and boot google/brox.

Change-Id: I39f516640b3f75ab4c6a09826922289c0533f79b
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86336
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
---
 src/soc/intel/common/block/pmc/pmclib.c | 17 ++++++++++++++++-
 1 file changed, 16 insertions(+), 1 deletion(-)

diff --git a/src/soc/intel/common/block/pmc/pmclib.c b/src/soc/intel/common/block/pmc/pmclib.c
index 8c48e8873f..64b9bb997c 100644
--- a/src/soc/intel/common/block/pmc/pmclib.c
+++ b/src/soc/intel/common/block/pmc/pmclib.c
@@ -15,6 +15,7 @@
 #include <intelblocks/gpio.h>
 #include <intelblocks/tco.h>
 #include <option.h>
+#include <reset.h>
 #include <security/vboot/vboot_common.h>
 #include <soc/pci_devs.h>
 #include <soc/pm.h>
@@ -615,7 +616,8 @@ void vboot_platform_prepare_reboot(void)
 	pmc_write_pm1_control(pm1_cnt);
 }
 
-void poweroff(void)
+/* Helper function to perform poweroff operation using PMC chipset register. */
+static void pmc_control_poweroff(void)
 {
 	pmc_enable_pm1_control(SLP_EN | (SLP_TYP_S5 << SLP_TYP_SHIFT));
 
@@ -628,6 +630,19 @@ void poweroff(void)
 		halt();
 }
 
+void poweroff(void)
+{
+	if (!ENV_ROMSTAGE_OR_BEFORE) {
+		pmc_control_poweroff();
+	} else if (CONFIG(HAVE_EARLY_POWEROFF_SUPPORT)) {
+		platform_do_early_poweroff();
+	} else {
+		printk(BIOS_EMERG, "This platform cannot be powered off until the silicon"
+			" initialization is complete, hanging!\n");
+		halt();
+	}
+}
+
 void pmc_gpe_init(void)
 {
 	uint32_t gpio_cfg = 0;

From c8fc650c5b7c9319be9082ca0d61fc6c96a3095a Mon Sep 17 00:00:00 2001
From: Subrata Banik <subratabanik@google.com>
Date: Fri, 14 Feb 2025 09:49:51 +0000
Subject: [PATCH 0095/3886] ec/google/chromeec: Implement early power off
 support

This commit renames the `google_chromeec_do_early_poweroff()` function
to `platform_do_early_poweroff()`, aligning it with the API that adds
early power off support using the Chrome EC.

It selects the `HAVE_EARLY_POWEROFF_SUPPORT` Kconfig option for platform
to perform early power off procedures.

Change-Id: I0c634d69de36fe8bdb6a61c121e321d3626ac3ff
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86379
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
---
 src/ec/google/chromeec/Kconfig | 1 +
 src/ec/google/chromeec/ec.c    | 9 ++++++++-
 src/ec/google/chromeec/ec.h    | 8 --------
 3 files changed, 9 insertions(+), 9 deletions(-)

diff --git a/src/ec/google/chromeec/Kconfig b/src/ec/google/chromeec/Kconfig
index a39ac8e81d..851ebb9352 100644
--- a/src/ec/google/chromeec/Kconfig
+++ b/src/ec/google/chromeec/Kconfig
@@ -3,6 +3,7 @@
 config EC_GOOGLE_CHROMEEC
 	bool
 	select EC_SUPPORTS_DPTF_TEVT
+	select HAVE_EARLY_POWEROFF_SUPPORT
 	help
 	  Google's Chrome EC
 
diff --git a/src/ec/google/chromeec/ec.c b/src/ec/google/chromeec/ec.c
index cc581ffb7b..5844071a1e 100644
--- a/src/ec/google/chromeec/ec.c
+++ b/src/ec/google/chromeec/ec.c
@@ -9,6 +9,7 @@
 #include <device/path.h>
 #include <elog.h>
 #include <halt.h>
+#include <reset.h>
 #include <rtc.h>
 #include <security/vboot/vboot_common.h>
 #include <stdlib.h>
@@ -1671,7 +1672,13 @@ bool google_chromeec_is_battery_present(void)
 	return false;
 }
 
-void google_chromeec_do_early_poweroff(void)
+/*
+ * Performs early power off.
+ *
+ * This function handles the necessary steps to initiate an early power off
+ * sequence.
+ */
+void platform_do_early_poweroff(void)
 {
 	google_chromeec_reboot(EC_REBOOT_COLD_AP_OFF, 0);
 	halt();
diff --git a/src/ec/google/chromeec/ec.h b/src/ec/google/chromeec/ec.h
index 08d4f2771d..b11b7a834a 100644
--- a/src/ec/google/chromeec/ec.h
+++ b/src/ec/google/chromeec/ec.h
@@ -471,14 +471,6 @@ bool google_chromeec_is_below_critical_threshold(void);
  */
 bool google_chromeec_is_battery_present(void);
 
-/*
- * Performs early power off.
- *
- * This function handles the necessary steps to initiate an early power off
- * sequence.
- */
-void google_chromeec_do_early_poweroff(void);
-
 /**
  * Determine if the UCSI stack is currently active.
  *

From 801d0a1491c48bfb56e91214bec9eb8d21646193 Mon Sep 17 00:00:00 2001
From: Subrata Banik <subratabanik@google.com>
Date: Tue, 11 Feb 2025 14:53:39 +0000
Subject: [PATCH 0096/3886] lib: Centralize logo.bmp inclusion in
 lib/Makefile.mk

This commit moves the logo.bmp inclusion logic from
`src/drivers/intel/fsp2_0/Makefile.mk` to `src/lib/Makefile.mk`.

This change centralizes the logo inclusion logic within the `lib`
directory, aligning it with the location of `bmp_logo.c` and making
it independent of the FSP 2.0 driver.

Change-Id: I16ed1cf29b839c25b6ea1c2f10faf3d99dd707c9
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86367
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
---
 src/drivers/intel/fsp2_0/Makefile.mk | 12 ------------
 src/lib/Makefile.mk                  | 12 ++++++++++++
 2 files changed, 12 insertions(+), 12 deletions(-)

diff --git a/src/drivers/intel/fsp2_0/Makefile.mk b/src/drivers/intel/fsp2_0/Makefile.mk
index 4cb24ffb56..18a62e3b57 100644
--- a/src/drivers/intel/fsp2_0/Makefile.mk
+++ b/src/drivers/intel/fsp2_0/Makefile.mk
@@ -126,18 +126,6 @@ $(obj)/Fsp_2_S.fd: $(call strip_quotes,$(CONFIG_FSP_FD_PATH_2)) $(obj)/Fsp_M.fd
 	true
 endif
 
-# Add logo to the cbfs image
-ifneq ($(CONFIG_HAVE_CUSTOM_BMP_LOGO),y)
-cbfs-files-$(CONFIG_BMP_LOGO) += logo.bmp
-logo.bmp-file := $(call strip_quotes,$(CONFIG_FSP2_0_LOGO_FILE_NAME))
-logo.bmp-type := raw
-ifeq ($(CONFIG_BMP_LOGO_COMPRESS_LZMA),y)
-logo.bmp-compression := LZMA
-else ifeq ($(CONFIG_BMP_LOGO_COMPRESS_LZ4),y)
-logo.bmp-compression := LZ4
-endif
-endif
-
 ifneq ($(call strip_quotes,$(CONFIG_FSP_HEADER_PATH)),)
 CPPFLAGS_common+=-I$(CONFIG_FSP_HEADER_PATH)
 endif
diff --git a/src/lib/Makefile.mk b/src/lib/Makefile.mk
index 40df2b8f56..292f5d2889 100644
--- a/src/lib/Makefile.mk
+++ b/src/lib/Makefile.mk
@@ -420,3 +420,15 @@ header_pointer-position := -4
 header_pointer-type := "cbfs header"
 
 romstage-y += ux_locales.c
+
+# Add logo to the cbfs image
+ifneq ($(CONFIG_HAVE_CUSTOM_BMP_LOGO),y)
+cbfs-files-$(CONFIG_BMP_LOGO) += logo.bmp
+logo.bmp-file := $(call strip_quotes,$(CONFIG_FSP2_0_LOGO_FILE_NAME))
+logo.bmp-type := raw
+ifeq ($(CONFIG_BMP_LOGO_COMPRESS_LZMA),y)
+logo.bmp-compression := LZMA
+else ifeq ($(CONFIG_BMP_LOGO_COMPRESS_LZ4),y)
+logo.bmp-compression := LZ4
+endif
+endif

From 40b9e5569668a813ff32ef2ee547315f8208439d Mon Sep 17 00:00:00 2001
From: Subrata Banik <subratabanik@google.com>
Date: Tue, 11 Feb 2025 15:05:55 +0000
Subject: [PATCH 0097/3886] lib: Refactor logo.bmp inclusion with helper macro

This commit refactors the logo.bmp inclusion logic to use a helper
macro, `add_bmp_logo_file_to_cbfs`. This centralizes the logic for
adding BMP logo files to the CBFS image and improves code readability.

Change-Id: I135c1f2af02064b72bc1f747336ac98ffdb20842
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86368
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
---
 src/lib/Makefile.mk | 20 ++++++++++++++------
 1 file changed, 14 insertions(+), 6 deletions(-)

diff --git a/src/lib/Makefile.mk b/src/lib/Makefile.mk
index 292f5d2889..93e76d4af3 100644
--- a/src/lib/Makefile.mk
+++ b/src/lib/Makefile.mk
@@ -422,13 +422,21 @@ header_pointer-type := "cbfs header"
 romstage-y += ux_locales.c
 
 # Add logo to the cbfs image
-ifneq ($(CONFIG_HAVE_CUSTOM_BMP_LOGO),y)
-cbfs-files-$(CONFIG_BMP_LOGO) += logo.bmp
-logo.bmp-file := $(call strip_quotes,$(CONFIG_FSP2_0_LOGO_FILE_NAME))
-logo.bmp-type := raw
+BMP_LOGO_COMPRESS_FLAG := $(CBFS_COMPRESS_FLAG)
 ifeq ($(CONFIG_BMP_LOGO_COMPRESS_LZMA),y)
-logo.bmp-compression := LZMA
+	BMP_LOGO_COMPRESS_FLAG := LZMA
 else ifeq ($(CONFIG_BMP_LOGO_COMPRESS_LZ4),y)
-logo.bmp-compression := LZ4
+	BMP_LOGO_COMPRESS_FLAG := LZ4
 endif
+
+define add_bmp_logo_file_to_cbfs
+cbfs-files-$$($(1)) += $(2)
+$(2)-file := $$(call strip_quotes,$$($(3)))
+$(2)-type := raw
+$(2)-compression := $$(BMP_LOGO_COMPRESS_FLAG)
+endef
+
+ifneq ($(CONFIG_HAVE_CUSTOM_BMP_LOGO),y)
+$(eval $(call add_bmp_logo_file_to_cbfs,CONFIG_BMP_LOGO, logo.bmp,\
+	      CONFIG_FSP2_0_LOGO_FILE_NAME))
 endif

From 1c8a058c08e14af06579d2a7c9a9ae093038a48d Mon Sep 17 00:00:00 2001
From: Subrata Banik <subratabanik@google.com>
Date: Tue, 11 Feb 2025 15:16:31 +0000
Subject: [PATCH 0098/3886] drivers/intel/fsp2_0: Add low battery indicator
 screen

This commit adds low battery indicator bitmap into CBFS. This screen
is displayed when the system detects a critically low battery condition.

The screen displays a logo and can be configured with a custom path.

An option to display an early low battery indicator in text mode is also
included. This early indicator can defer the firmware update.

This feature is controlled by the PLATFORM_HAS_LOW_BATTERY_INDICATOR
Kconfig option.

BUG=b:339673254
TEST=Able to see low-battery user notification in text mode before
memory init. Verified low-battery boot event listed in the eventlog.

Change-Id: I711c53455639b449fe85903139bbc06cdab08d09
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86225
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
---
 src/drivers/intel/fsp2_0/Kconfig | 49 ++++++++++++++++++++++++++++++++
 src/lib/Makefile.mk              |  3 ++
 2 files changed, 52 insertions(+)

diff --git a/src/drivers/intel/fsp2_0/Kconfig b/src/drivers/intel/fsp2_0/Kconfig
index c5c485bad2..42551503ff 100644
--- a/src/drivers/intel/fsp2_0/Kconfig
+++ b/src/drivers/intel/fsp2_0/Kconfig
@@ -522,4 +522,53 @@ config BUILDING_WITH_DEBUG_FSP
 	  Enable this option if you are using a debug build of the FSP (Firmware Support Package)
 	  in your project.
 
+config PLATFORM_HAS_LOW_BATTERY_INDICATOR
+	bool "Display low battery indicator"
+	depends on BMP_LOGO
+	help
+	  If enabled, this option displays a low battery indicator screen. This screen can be
+	  used to warn the user that the battery is low and that they should plug in the device.
+
+	  This option requires that the system have a display and that the BMP_LOGO option is
+	  enabled.
+
+config PLATFORM_LOW_BATTERY_SHUTDOWN_DELAY_SEC
+	int
+	default 5
+	depends on PLATFORM_HAS_LOW_BATTERY_INDICATOR
+	help
+	  Delay, in seconds, before system shutdown due to low battery.
+	  This delay allows the user to observe the low-battery indicator.
+	  The default value of 5 seconds aligns with standard user experience (UX) practices.
+	  Platforms may override this value based on specific product requirements.
+
+config HAVE_ESOL_SUPPORT_FOR_LOW_BATTERY_INDICATOR
+	bool
+	depends on FSP_UGOP_EARLY_SIGN_OF_LIFE || MAINBOARD_HAS_EARLY_LIBGFXINIT
+	help
+	  Enable low-battery indicator support in eSOL.
+
+	  This option should be selected if the eSOL feature (using either libgfxinit or FSP uGOP)
+	  supports displaying a low-battery indicator.
+
+	  Platforms selecting `MAINBOARD_HAS_EARLY_LIBGFXINIT` can default enable this option.
+
+	  For platforms using FSP uGOP, this option should only be enabled if uGOP has implemented
+	  the necessary low-battery handling. This allows platforms to control low-battery
+	  indicator support based on uGOP readiness.
+
+config PLATFORM_HAS_EARLY_LOW_BATTERY_INDICATOR
+	bool "Display low battery indicator in romstage"
+	depends on PLATFORM_HAS_LOW_BATTERY_INDICATOR && HAVE_ESOL_SUPPORT_FOR_LOW_BATTERY_INDICATOR
+	help
+	  If enabled, this option displays a low battery indicator during romstage (before memory
+	  is available) in text mode in the firmware and defer the firmware update. This screen
+	  can be used to warn the user that the battery is low and that they should plug in the
+	  device.
+
+config PLATFORM_LOW_BATTERY_INDICATOR_LOGO_PATH
+	string "Path to low battery logo file"
+	depends on PLATFORM_HAS_LOW_BATTERY_INDICATOR
+	default "3rdparty/blobs/mainboard/\$(MAINBOARDDIR)/low_battery.bmp"
+
 endif
diff --git a/src/lib/Makefile.mk b/src/lib/Makefile.mk
index 93e76d4af3..5e1e81a5d0 100644
--- a/src/lib/Makefile.mk
+++ b/src/lib/Makefile.mk
@@ -440,3 +440,6 @@ ifneq ($(CONFIG_HAVE_CUSTOM_BMP_LOGO),y)
 $(eval $(call add_bmp_logo_file_to_cbfs,CONFIG_BMP_LOGO, logo.bmp,\
 	      CONFIG_FSP2_0_LOGO_FILE_NAME))
 endif
+
+$(eval $(call add_bmp_logo_file_to_cbfs,CONFIG_PLATFORM_HAS_LOW_BATTERY_INDICATOR, \
+	      low_battery.bmp,CONFIG_PLATFORM_LOW_BATTERY_INDICATOR_LOGO_PATH))

From e5cc73cb9499adecbf8f8254f18ff44142c25397 Mon Sep 17 00:00:00 2001
From: Subrata Banik <subratabanik@google.com>
Date: Tue, 11 Feb 2025 09:09:56 +0000
Subject: [PATCH 0099/3886] soc/intel/common: Add low battery shutdown function

This commit adds a `do_low_battery_poweroff()` function to handle
platform power off due to critically low battery levels.

This provides a standardized way to handle low battery shutdowns across
platforms.

Additionally, the delay to the `do_low_battery_poweroff()` function,
allowing time for the low battery indicator to be displayed before
powering off. The delay is configurable through the
`PLATFORM_LOW_BATTERY_SHUTDOWN_DELAY_SEC` Kconfig option.

Finally, a low battery indicator event is logged using `elog`
before the delay.

This functionality (elog and delay) is enabled when the
`PLATFORM_HAS_LOW_BATTERY_INDICATOR` Kconfig option is selected.

BUG=b:339673254
TEST=Able to build and boot google/brox.

Change-Id: I92e9003c70c2608770972f1a302f954ebdf17bc4
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86361
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/soc/intel/common/reset.c | 12 ++++++++++++
 src/soc/intel/common/reset.h |  7 +++++++
 2 files changed, 19 insertions(+)

diff --git a/src/soc/intel/common/reset.c b/src/soc/intel/common/reset.c
index c6c394bd44..3fefa57d30 100644
--- a/src/soc/intel/common/reset.c
+++ b/src/soc/intel/common/reset.c
@@ -3,6 +3,8 @@
 #include <arch/cache.h>
 #include <cf9_reset.h>
 #include <console/console.h>
+#include <delay.h>
+#include <elog.h>
 #include <halt.h>
 #include <reset.h>
 
@@ -21,3 +23,13 @@ void do_board_reset(void)
 {
 	full_reset();
 }
+
+void do_low_battery_poweroff(void)
+{
+	if (CONFIG(PLATFORM_HAS_LOW_BATTERY_INDICATOR)) {
+		elog_add_event_byte(ELOG_TYPE_LOW_BATTERY_INDICATOR, ELOG_FW_ISSUE_SHUTDOWN);
+		delay(CONFIG_PLATFORM_LOW_BATTERY_SHUTDOWN_DELAY_SEC);
+	}
+
+	poweroff();
+}
diff --git a/src/soc/intel/common/reset.h b/src/soc/intel/common/reset.h
index 658223c32a..8331853023 100644
--- a/src/soc/intel/common/reset.h
+++ b/src/soc/intel/common/reset.h
@@ -25,4 +25,11 @@ __noreturn void global_reset(void);
  */
 efi_return_status_t fsp_get_pch_reset_status(void);
 
+/*
+ * Issue power off due to low battery
+ *
+ * Call this function to power off the platform if the battery level is critically low.
+ */
+void do_low_battery_poweroff(void);
+
 #endif	/* _INTEL_COMMON_RESET_H_ */

From a518709e2583fb683ac9cc1d578e3b962ed089d4 Mon Sep 17 00:00:00 2001
From: Subrata Banik <subratabanik@google.com>
Date: Wed, 5 Feb 2025 15:38:50 +0000
Subject: [PATCH 0100/3886] drivers/intel/fsp2_0: Add platform callback for
 critical shutdown

This commit adds the `platform_is_low_battery_shutdown_needed` callback
to the FSP API. This allows platforms to integrate low-battery handling
logic directly into the FSP silicon initialization process. By checking
for critical conditions (e.g., low battery) within this callback after
FSP silicon initialization, the platform can initiate a controlled
shutdown before proceeding with further boot stages, preventing abrupt
shutdowns later in the boot process.

BUG=b:339673254
TEST=Able to build and boot google/brox.

Change-Id: I2d6677d70dea3d24f5a19d70608fd21229a271a0
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86226
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
---
 src/drivers/intel/fsp2_0/include/fsp/api.h | 13 +++++++++++++
 src/drivers/intel/fsp2_0/silicon_init.c    |  3 +++
 src/lib/bmp_logo.c                         |  9 ++++++++-
 3 files changed, 24 insertions(+), 1 deletion(-)

diff --git a/src/drivers/intel/fsp2_0/include/fsp/api.h b/src/drivers/intel/fsp2_0/include/fsp/api.h
index 971be0d207..28b24ce95f 100644
--- a/src/drivers/intel/fsp2_0/include/fsp/api.h
+++ b/src/drivers/intel/fsp2_0/include/fsp/api.h
@@ -50,6 +50,19 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd);
 /* Callbacks for SoC/Mainboard specific overrides */
 void platform_fsp_memory_multi_phase_init_cb(uint32_t phase_index);
 void platform_fsp_silicon_multi_phase_init_cb(uint32_t phase_index);
+/*
+ * Platform specific callbacks for power-off handling.
+ *
+ * These callbacks allow the platform to determine if a power-off is
+ * necessary due to various reasons, such as low battery detection.
+ *
+ * Additionally, API to perform platform specific power-off
+ */
+#if CONFIG(PLATFORM_HAS_LOW_BATTERY_INDICATOR)
+bool platform_is_low_battery_shutdown_needed(void);
+#else
+static inline bool platform_is_low_battery_shutdown_needed(void) { return false; }
+#endif
 /* Check if MultiPhase Si Init is enabled */
 bool fsp_is_multi_phase_init_enabled(void);
 /*
diff --git a/src/drivers/intel/fsp2_0/silicon_init.c b/src/drivers/intel/fsp2_0/silicon_init.c
index fdac9f5b85..f3472420bc 100644
--- a/src/drivers/intel/fsp2_0/silicon_init.c
+++ b/src/drivers/intel/fsp2_0/silicon_init.c
@@ -259,6 +259,9 @@ void fsp_silicon_init(void)
 	fsps_load();
 	do_silicon_init(&fsps_hdr);
 
+	if (platform_is_low_battery_shutdown_needed())
+		do_low_battery_poweroff();
+
 	if (CONFIG(CACHE_MRC_SETTINGS) && CONFIG(FSP_NVS_DATA_POST_SILICON_INIT))
 		save_memory_training_data();
 
diff --git a/src/lib/bmp_logo.c b/src/lib/bmp_logo.c
index becb605645..5a5adaafb5 100644
--- a/src/lib/bmp_logo.c
+++ b/src/lib/bmp_logo.c
@@ -4,6 +4,7 @@
 #include <bootsplash.h>
 #include <cbfs.h>
 #include <cbmem.h>
+#include <fsp/api.h>
 #include <stdint.h>
 #include <vendorcode/google/chromeos/chromeos.h>
 
@@ -19,6 +20,7 @@ const char *bmp_logo_filename(void)
 void *bmp_load_logo(size_t *logo_size)
 {
 	void *logo_buffer;
+	const char *logo_name;
 
 	/* CBMEM is locked for S3 resume path. */
 	if (acpi_is_wakeup_s3())
@@ -32,7 +34,12 @@ void *bmp_load_logo(size_t *logo_size)
 	if (!logo_buffer)
 		return NULL;
 
-	*logo_size = cbfs_load(bmp_logo_filename(), logo_buffer, 1 * MiB);
+	if (platform_is_low_battery_shutdown_needed())
+		logo_name = "low_battery.bmp";
+	else
+		logo_name = bmp_logo_filename();
+
+	*logo_size = cbfs_load(logo_name, logo_buffer, 1 * MiB);
 	if (*logo_size == 0)
 		return NULL;
 

From 1a58ae5e09137853e1356ad421f58baddd94adac Mon Sep 17 00:00:00 2001
From: Subrata Banik <subratabanik@google.com>
Date: Thu, 6 Feb 2025 12:17:08 +0000
Subject: [PATCH 0101/3886] vc/google/chromeos: Implement platform callback for
 critical shutdown

This commit implements `platform_is_low_battery_shutdown_needed` and
callback for ChromeOS.

- platform_is_low_battery_shutdown_needed: API to check if low battery
   shutdown is needed.

BUG=b:339673254
TEST=Verified low battery boot event logging and controlled shutdown.

Change-Id: I119f80a45c045a6095cae98f179c755a2e948e9c
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86228
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
---
 src/vendorcode/google/chromeos/Makefile.mk |  3 ++
 src/vendorcode/google/chromeos/battery.c   | 34 ++++++++++++++++++++++
 2 files changed, 37 insertions(+)
 create mode 100644 src/vendorcode/google/chromeos/battery.c

diff --git a/src/vendorcode/google/chromeos/Makefile.mk b/src/vendorcode/google/chromeos/Makefile.mk
index 67b50f6bdd..6eb010e8eb 100644
--- a/src/vendorcode/google/chromeos/Makefile.mk
+++ b/src/vendorcode/google/chromeos/Makefile.mk
@@ -19,7 +19,10 @@ verstage-y += watchdog.c
 romstage-y += watchdog.c
 ramstage-y += watchdog.c
 
+romstage-$(CONFIG_PLATFORM_HAS_EARLY_LOW_BATTERY_INDICATOR) += battery.c
 romstage-$(CONFIG_CHROMEOS_DRAM_PART_NUMBER_IN_CBI) += dram_part_num_override.c
+
+ramstage-$(CONFIG_PLATFORM_HAS_LOW_BATTERY_INDICATOR) += battery.c
 ramstage-$(CONFIG_CHROMEOS_FW_SPLASH_SCREEN) += splash.c
 
 # Add logo to the cbfs image
diff --git a/src/vendorcode/google/chromeos/battery.c b/src/vendorcode/google/chromeos/battery.c
new file mode 100644
index 0000000000..febc4dcc02
--- /dev/null
+++ b/src/vendorcode/google/chromeos/battery.c
@@ -0,0 +1,34 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <ec/google/chromeec/ec.h>
+#include <fsp/api.h>
+
+/*
+ * Check if low battery shutdown is needed
+ *
+ * This function checks if the system needs to shut down due to a critically low
+ * battery level. It performs the following actions:
+ *
+ * 1. If Chrome EC is not supported, returns false (no shutdown needed).
+ * 2. Uses static variables to cache the result and avoid repeated checks.
+ * 3. If the battery level has not been checked yet:
+ *    - Queries the Chrome EC to determine if the battery is below the critical threshold.
+ *    - If the battery is below the threshold, sets the result to true.
+ * 4. Returns the cached result.
+ */
+bool platform_is_low_battery_shutdown_needed(void)
+{
+	if (!CONFIG(EC_GOOGLE_CHROMEEC))
+		return false;
+
+	static bool result = false;
+	static bool checked = false;
+
+	if (!checked) {
+		if (google_chromeec_is_below_critical_threshold())
+			result = true;
+		checked = true;
+	}
+
+	return result;
+}

From 80801e7f694b263fc8faca207e3af1aad3523bc4 Mon Sep 17 00:00:00 2001
From: Subrata Banik <subratabanik@google.com>
Date: Thu, 6 Feb 2025 12:58:05 +0000
Subject: [PATCH 0102/3886] soc/intel/alderlake: Handle critical low battery
 early in romstage

This commit implements early handling of critical low battery
conditions in the romstage for Alder Lake platforms.

A message is displayed to the user via
ux_inform_user_of_poweroff_operation. A short delay is introduced to
allow the user to see the message. A low battery event is logged.
The system is shut down via the Chrome EC.

This early handling prevents the system from proceeding with
boot (while performing firmware update) if the battery is critically
low and ensures a clean shutdown. This is particularly important for
ChromeOS devices.

BUG=b:339673254
TEST=Verified low battery boot event logging and controlled shutdown.

Change-Id: Ib4be86ed17818ee05b7bec0337a90f80017183c2
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86227
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/soc/intel/alderlake/romstage/fsp_params.c | 24 +++++++++++++++++++
 1 file changed, 24 insertions(+)

diff --git a/src/soc/intel/alderlake/romstage/fsp_params.c b/src/soc/intel/alderlake/romstage/fsp_params.c
index 4a03b7438f..71791ae90b 100644
--- a/src/soc/intel/alderlake/romstage/fsp_params.c
+++ b/src/soc/intel/alderlake/romstage/fsp_params.c
@@ -8,6 +8,7 @@
 #include <device/device.h>
 #include <drivers/wifi/generic/wifi.h>
 #include <elog.h>
+#include <fsp/api.h>
 #include <fsp/fsp_debug_event.h>
 #include <fsp/util.h>
 #include <gpio.h>
@@ -16,6 +17,7 @@
 #include <intelblocks/cse.h>
 #include <intelblocks/pcie_rp.h>
 #include <option.h>
+#include <soc/intel/common/reset.h>
 #include <soc/iomap.h>
 #include <soc/msr.h>
 #include <soc/pci_devs.h>
@@ -427,6 +429,28 @@ static void fill_fspm_sign_of_life(FSP_M_CONFIG *m_cfg,
 	 * user with an on-screen text message.
 	 */
 	if (!arch_upd->NvsBufferPtr) {
+		/*
+		 * Low Battery Check During Firmware Update (Chrome OS specific):
+		 *    - If `PLATFORM_HAS_EARLY_LOW_BATTERY_INDICATOR` is enabled AND the
+		 *      system is in firmware update mode (If valid MRC cache data is not found,
+		 *      it means that the system needs to perform), it checks if the battery level is
+		 *      critically low.
+		 *    - This is because memory training, which can take a significant amount of
+		 *      time, might cause an abrupt shutdown due to low battery, interrupting the
+		 *      firmware update process and potentially leaving the system in an unstable
+		 *      state.
+		 *    - To prevent this, if the battery is critically low, the system is powered
+		 *      off to allow it to charge. This ensures that the firmware update process
+		 *      can complete without interruption.
+		 *    - Since a functional GFX mode display may not be ready at this stage, VGA
+		 *      mode is used to display a text message informing the user about the
+		 *      shutdown.
+		 */
+		if (CONFIG(PLATFORM_HAS_EARLY_LOW_BATTERY_INDICATOR) &&
+				 platform_is_low_battery_shutdown_needed()) {
+			ux_inform_user_of_poweroff_operation("low-battery shutdown");
+			do_low_battery_poweroff();
+		}
 		esol_required = true;
 		name = "memory training";
 		elog_add_event_byte(ELOG_TYPE_FW_EARLY_SOL, ELOG_FW_EARLY_SOL_MRC);

From 72947a131fef10b69ebd406006c0188a25acc32b Mon Sep 17 00:00:00 2001
From: Subrata Banik <subratabanik@google.com>
Date: Fri, 14 Feb 2025 11:36:12 +0000
Subject: [PATCH 0103/3886] soc/intel/alderlake: Enable low-battery indicator
 support

This patch enables the `HAVE_ESOL_SUPPORT_FOR_LOW_BATTERY_INDICATOR`
Kconfig option for Alder Lake SoC platform that has support for
CHROMEOS_ENABLE_ESOL.

This allows the eSOL feature (depending upon CHROMEOS_ENABLE_ESOL)
to display a low-battery indicator.

BUG=b:339673254
TEST=Verified low battery boot event logging and controlled shutdown.

Change-Id: I8b49a487ca80a2aeeb8b4d8e4c2259217e854444
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86316
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
---
 src/soc/intel/alderlake/Kconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig
index 4f374eba64..fc94695f18 100644
--- a/src/soc/intel/alderlake/Kconfig
+++ b/src/soc/intel/alderlake/Kconfig
@@ -22,6 +22,7 @@ config SOC_INTEL_ALDERLAKE
 	select FSPS_HAS_ARCH_UPD
 	select GENERIC_GPIO_LIB
 	select HAVE_DEBUG_RAM_SETUP
+	select HAVE_ESOL_SUPPORT_FOR_LOW_BATTERY_INDICATOR if CHROMEOS_ENABLE_ESOL
 	select HAVE_FSP_GOP
 	select HAVE_HYPERTHREADING
 	select INTEL_DESCRIPTOR_MODE_CAPABLE

From 5aebeb4056faf13faf9e384ec87c07fb19f03ae7 Mon Sep 17 00:00:00 2001
From: Maximilian Brune <maximilian.brune@9elements.com>
Date: Tue, 4 Feb 2025 15:42:45 +0100
Subject: [PATCH 0104/3886] soc/amd/glinda/chipset.cb: Enable
 gpp_bridge_[a/b/c] by default

Since FSP doesn't support disabling bridges and has no UPDs for that,
they must be enabled in DT to make sure they are properly initialized
during PCI enumeration as expected by the payload (EDK2 for example).
It might be OK to have them set to off when all devices behind the
bridge are also off and FSP disables those secondary devices.

In general something that cannot be hidden/shut off shouldn't be marked
as such, as later stages (payload/OS) might find it active, but
unconfigured.

Change-Id: Id28a29481f9a1bc570e47a9cb75613d3621b0d44
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86270
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/soc/amd/glinda/chipset.cb | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/src/soc/amd/glinda/chipset.cb b/src/soc/amd/glinda/chipset.cb
index f328797ec2..a76be1ad31 100644
--- a/src/soc/amd/glinda/chipset.cb
+++ b/src/soc/amd/glinda/chipset.cb
@@ -32,7 +32,7 @@ chip soc/amd/glinda
 		device pci 03.6 alias gpp_bridge_3_6 off ops amd_external_pcie_gpp_ops end
 
 		device pci 08.0 on end # Dummy device function, do not disable
-		device pci 08.1 alias gpp_bridge_a off  # Internal GPP Bridge 0 to Bus A
+		device pci 08.1 alias gpp_bridge_a on  # Internal GPP Bridge 0 to Bus A
 			ops amd_internal_pcie_gpp_ops
 			device pci 0.0 alias gfx off ops amd_graphics_ops end # Internal GPU (GFX)
 			device pci 0.1 alias gfx_hda off end # Display HD Audio Controller (GFXAZ)
@@ -56,13 +56,13 @@ chip soc/amd/glinda
 			device pci 0.7 alias mp2 off end # Sensor Fusion Hub (MP2)
 		end
 
-		device pci 08.2 alias gpp_bridge_b off # Internal GPP Bridge 1 to Bus B
+		device pci 08.2 alias gpp_bridge_b on # Internal GPP Bridge 1 to Bus B
 			ops amd_internal_pcie_gpp_ops
 			device pci 0.0 on end # dummy, do not disable
 			device pci 0.1 alias npu off end # Neural Processing Unit (NPU)
 		end
 
-		device pci 08.3 alias gpp_bridge_c off # Internal GPP Bridge 2 to Bus C
+		device pci 08.3 alias gpp_bridge_c on # Internal GPP Bridge 2 to Bus C
 			ops amd_internal_pcie_gpp_ops
 
 			device pci 0.0 alias xhci_0 off

From 3d07c761f7621ada5a875f2ac46b19de1e0981be Mon Sep 17 00:00:00 2001
From: Maximilian Brune <maximilian.brune@9elements.com>
Date: Tue, 4 Feb 2025 15:48:54 +0100
Subject: [PATCH 0105/3886] soc/amd/phoenix/chipset_*: Enable
 gpp_bridge_[a/b/c] by default

Since FSP doesn't support disabling bridges and has no UPDs for that,
they must be enabled in DT to make sure they are properly initialized
during PCI enumeration as expected by the payload (EDK2 for example).
It might be OK to have them set to off when all devices behind the
bridge are also off and FSP disables those secondary devices.

In general something that cannot be hidden/shut off shouldn't be marked
as such, as later stages (payload/OS) might find it active, but
unconfigured.

Change-Id: Ic226fd93b431467c7fa3a53140102ff4fd327f40
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86271
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/google/myst/variants/baseboard/devicetree.cb | 1 +
 src/soc/amd/phoenix/chipset_fsp.cb                         | 6 +++---
 src/soc/amd/phoenix/chipset_opensil.cb                     | 6 +++---
 3 files changed, 7 insertions(+), 6 deletions(-)

diff --git a/src/mainboard/google/myst/variants/baseboard/devicetree.cb b/src/mainboard/google/myst/variants/baseboard/devicetree.cb
index 97994c7885..55a14c077b 100644
--- a/src/mainboard/google/myst/variants/baseboard/devicetree.cb
+++ b/src/mainboard/google/myst/variants/baseboard/devicetree.cb
@@ -310,6 +310,7 @@ chip soc/amd/phoenix
 			device ref acp on end # Audio Processor (ACP)
 			device ref mp2 on end # Sensor Fusion Hub (MP2)
 		end
+		device ref gpp_bridge_b off end # Internal GPP Bridge 1 to Bus B
 		device ref gpp_bridge_c on  # Internal GPP Bridge 2 to Bus C
 			device ref usb4_xhci_0 on
 				chip drivers/usb/acpi
diff --git a/src/soc/amd/phoenix/chipset_fsp.cb b/src/soc/amd/phoenix/chipset_fsp.cb
index 2d1e17080a..d461ac5d49 100644
--- a/src/soc/amd/phoenix/chipset_fsp.cb
+++ b/src/soc/amd/phoenix/chipset_fsp.cb
@@ -30,7 +30,7 @@ chip soc/amd/phoenix
 		device pci 04.1 alias usb4_pcie_bridge_1 off end
 
 		device pci 08.0 on end # Dummy device function, do not disable
-		device pci 08.1 alias gpp_bridge_a off  # Internal GPP Bridge 0 to Bus A
+		device pci 08.1 alias gpp_bridge_a on  # Internal GPP Bridge 0 to Bus A
 			ops amd_internal_pcie_gpp_ops
 			device pci 0.0 alias gfx off ops amd_graphics_ops end # Internal GPU (GFX)
 			device pci 0.1 alias gfx_hda off end # Display HD Audio Controller (GFXAZ)
@@ -82,13 +82,13 @@ chip soc/amd/phoenix
 			device pci 0.6 alias hda off end # Audio Processor HD Audio Controller (main AZ)
 			device pci 0.7 alias mp2 off end # Sensor Fusion Hub (MP2)
 		end
-		device pci 08.2 alias gpp_bridge_b off # Internal GPP Bridge 1 to Bus B
+		device pci 08.2 alias gpp_bridge_b on # Internal GPP Bridge 1 to Bus B
 			ops amd_internal_pcie_gpp_ops
 			device pci 0.0 on end # dummy, do not disable
 			device pci 0.1 alias ipu off end
 		end
 
-		device pci 08.3 alias gpp_bridge_c off # Internal GPP Bridge 2 to Bus C
+		device pci 08.3 alias gpp_bridge_c on # Internal GPP Bridge 2 to Bus C
 			ops amd_internal_pcie_gpp_ops
 			device pci 0.0 on end # dummy, do not disable
 			device pci 0.3 alias usb4_xhci_0 off
diff --git a/src/soc/amd/phoenix/chipset_opensil.cb b/src/soc/amd/phoenix/chipset_opensil.cb
index 42f36bcc34..fd1563b670 100644
--- a/src/soc/amd/phoenix/chipset_opensil.cb
+++ b/src/soc/amd/phoenix/chipset_opensil.cb
@@ -50,7 +50,7 @@ chip soc/amd/phoenix
 		device pci 04.1 alias usb4_pcie_bridge_1 off end
 
 		device pci 08.0 on end # Dummy device function, do not disable
-		device pci 08.1 alias gpp_bridge_a off  # Internal GPP Bridge 0 to Bus A
+		device pci 08.1 alias gpp_bridge_a on  # Internal GPP Bridge 0 to Bus A
 			ops amd_internal_pcie_gpp_ops
 			device pci 0.0 alias gfx off ops amd_graphics_ops end # Internal GPU (GFX)
 			device pci 0.1 alias gfx_hda off end # Display HD Audio Controller (GFXAZ)
@@ -102,13 +102,13 @@ chip soc/amd/phoenix
 			device pci 0.6 alias hda off end # Audio Processor HD Audio Controller (main AZ)
 			device pci 0.7 alias mp2 off end # Sensor Fusion Hub (MP2)
 		end
-		device pci 08.2 alias gpp_bridge_b off # Internal GPP Bridge 1 to Bus B
+		device pci 08.2 alias gpp_bridge_b on # Internal GPP Bridge 1 to Bus B
 			ops amd_internal_pcie_gpp_ops
 			device pci 0.0 on end # dummy, do not disable
 			device pci 0.1 alias ipu off end
 		end
 
-		device pci 08.3 alias gpp_bridge_c off # Internal GPP Bridge 2 to Bus C
+		device pci 08.3 alias gpp_bridge_c on # Internal GPP Bridge 2 to Bus C
 			ops amd_internal_pcie_gpp_ops
 			device pci 0.0 on end # dummy, do not disable
 			device pci 0.3 alias usb4_xhci_0 off

From 72401fc03924866e63264a228125aaa1f09cccaa Mon Sep 17 00:00:00 2001
From: Maximilian Brune <maximilian.brune@9elements.com>
Date: Tue, 4 Feb 2025 15:56:22 +0100
Subject: [PATCH 0106/3886] soc/amd/mendocino/chipset_*: Enable
 gpp_bridge_[a/b/c] by default

Since FSP doesn't support disabling bridges and has no UPDs for that,
they must be enabled in DT to make sure they are properly initialized
during PCI enumeration as expected by the payload (EDK2 for example).
It might be OK to have them set to off when all devices behind the
bridge are also off and FSP disables those secondary devices.

In general something that cannot be hidden/shut off shouldn't be marked
as such, as later stages (payload/OS) might find it active, but
unconfigured.

Change-Id: Ife30f73495d44c98717e147602de10f5a6a89358
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86273
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
---
 src/soc/amd/mendocino/chipset_mendocino.cb | 4 ++--
 src/soc/amd/mendocino/chipset_rembrandt.cb | 6 +++---
 2 files changed, 5 insertions(+), 5 deletions(-)

diff --git a/src/soc/amd/mendocino/chipset_mendocino.cb b/src/soc/amd/mendocino/chipset_mendocino.cb
index 6ee1e63f18..3458caed06 100644
--- a/src/soc/amd/mendocino/chipset_mendocino.cb
+++ b/src/soc/amd/mendocino/chipset_mendocino.cb
@@ -16,7 +16,7 @@ chip soc/amd/mendocino
 		device pci 02.4 alias gpp_bridge_3 hidden ops amd_external_pcie_gpp_ops end
 
 		device pci 08.0 on end # Dummy device function, do not disable
-		device pci 08.1 alias gpp_bridge_a off  # Internal GPP Bridge 0 to Bus A
+		device pci 08.1 alias gpp_bridge_a on  # Internal GPP Bridge 0 to Bus A
 			ops amd_internal_pcie_gpp_ops
 			device pci 0.0 alias gfx off ops amd_graphics_ops end # Internal GPU (GFX)
 			device pci 0.1 alias gfx_hda off end # Display HD Audio Controller (GFXAZ)
@@ -65,7 +65,7 @@ chip soc/amd/mendocino
 			device pci 0.6 alias hda off end # Audio Processor HD Audio Controller (main AZ)
 			device pci 0.7 alias mp2 off end # Sensor Fusion Hub (MP2)
 		end
-		device pci 08.3 alias gpp_bridge_c off # Internal GPP Bridge 2 to Bus C
+		device pci 08.3 alias gpp_bridge_c on # Internal GPP Bridge 2 to Bus C
 			ops amd_internal_pcie_gpp_ops
 			device pci 0.0 alias xhci_2 off end # Might also be a dummy device with different PCI DID
 			# When using this as XHCI2, the mainboard devicetree needs to add ops xhci_pci_ops
diff --git a/src/soc/amd/mendocino/chipset_rembrandt.cb b/src/soc/amd/mendocino/chipset_rembrandt.cb
index ef3bfa9a56..aef0a8978b 100644
--- a/src/soc/amd/mendocino/chipset_rembrandt.cb
+++ b/src/soc/amd/mendocino/chipset_rembrandt.cb
@@ -18,7 +18,7 @@ chip soc/amd/mendocino
 		device pci 02.6 alias gpp_bridge_5 hidden ops amd_external_pcie_gpp_ops end
 
 		device pci 08.0 on end # Dummy device function, do not disable
-		device pci 08.1 alias gpp_bridge_a off  # Internal GPP Bridge 0 to Bus A
+		device pci 08.1 alias gpp_bridge_a on  # Internal GPP Bridge 0 to Bus A
 			ops amd_internal_pcie_gpp_ops
 			device pci 0.0 alias gfx off ops amd_graphics_ops end # Internal GPU (GFX)
 			device pci 0.1 alias gfx_hda off end # Display HD Audio Controller (GFXAZ)
@@ -67,8 +67,8 @@ chip soc/amd/mendocino
 			device pci 0.6 alias hda off end # Audio Processor HD Audio Controller (main AZ)
 			device pci 0.7 alias mp2 off end # Sensor Fusion Hub (MP2)
 		end
-		device pci 08.2 alias gpp_bridge_b off ops amd_internal_pcie_gpp_ops end # Internal GPP Bridge 1 to Bus B
-		device pci 08.3 alias gpp_bridge_c off # Internal GPP Bridge 2 to Bus C
+		device pci 08.2 alias gpp_bridge_b on ops amd_internal_pcie_gpp_ops end # Internal GPP Bridge 1 to Bus B
+		device pci 08.3 alias gpp_bridge_c on # Internal GPP Bridge 2 to Bus C
 			ops amd_internal_pcie_gpp_ops
 			device pci 0.0 alias xhci_2 off end # Might also be a dummy device with different PCI DID
 			# When using this as XHCI2, the mainboard devicetree needs to add ops xhci_pci_ops

From 9cbde37fc3b1c2ffe77f988a7952a56cddfebfe6 Mon Sep 17 00:00:00 2001
From: Maximilian Brune <maximilian.brune@9elements.com>
Date: Fri, 14 Feb 2025 15:05:01 +0100
Subject: [PATCH 0107/3886] soc/amd/glinda: Fix pci int defs

commit 540d605f4849 ("soc/amd/glinda: Update pci int defs") forgot to
update the offset after adding GEventSmi and GEventSci.

source:
PPR #57254 Rev 1.59 Table 137

Change-Id: I702f16e681d57c5e44f91c805a9aeb71eb160bd3
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86421
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
---
 src/soc/amd/glinda/acpi/pci_int_defs.asl | 4 +---
 1 file changed, 1 insertion(+), 3 deletions(-)

diff --git a/src/soc/amd/glinda/acpi/pci_int_defs.asl b/src/soc/amd/glinda/acpi/pci_int_defs.asl
index 61ecd449b4..53ced22723 100644
--- a/src/soc/amd/glinda/acpi/pci_int_defs.asl
+++ b/src/soc/amd/glinda/acpi/pci_int_defs.asl
@@ -1,7 +1,5 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
-/* TODO: Update for Glinda */
-
 /* PCI IRQ mapping registers, C00h-C01h. */
 OperationRegion(PRQM, SystemIO, 0x00000c00, 0x00000002)
 	Field(PRQM, ByteAcc, NoLock, Preserve) {
@@ -51,7 +49,7 @@ IndexField(PRQI, PRQD, ByteAcc, NoLock, Preserve) {
 	IORG, 0x00000008,	/* Index 0x86: INTG */
 	IORH, 0x00000008,	/* Index 0x87: INTH */
 
-	Offset (0xE2),
+	Offset (0xE0),
 	IGSC, 0x00000008,	/* Index 0xE0: GEventSci */
 	IGSM, 0x00000008,	/* Index 0xE1: GEventSmi */
 	IGPI, 0x00000008,	/* Index 0xE2: GPIO */

From 5688932d255723410bea91addc46e2d6b415619e Mon Sep 17 00:00:00 2001
From: Ian Feng <ian_feng@compal.corp-partner.google.com>
Date: Fri, 14 Feb 2025 13:54:57 +0800
Subject: [PATCH 0108/3886] mb/google/fatcat/var/francka: Configure the finger
 print pins

Configure correct finger print pins, And change power sequence.
FP_PWR_EN - GPP_H03
FP_RST_OD - GPP_H17
FPMCU_INT - GPP_D17
FPMCU_FW_UPDATE - GPP_F20

BUG=b:393985006
TEST=Boot to OS in francka and fingerprint function work well.

Change-Id: I0d9b1d042da1bd81d0f3a32140247948cdab983c
Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86413
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
---
 .../google/fatcat/variants/francka/gpio.c     | 20 +++++++++----------
 .../fatcat/variants/francka/overridetree.cb   | 14 +++++++++----
 2 files changed, 20 insertions(+), 14 deletions(-)

diff --git a/src/mainboard/google/fatcat/variants/francka/gpio.c b/src/mainboard/google/fatcat/variants/francka/gpio.c
index 88191224de..6265b1667d 100644
--- a/src/mainboard/google/fatcat/variants/francka/gpio.c
+++ b/src/mainboard/google/fatcat/variants/francka/gpio.c
@@ -186,7 +186,7 @@ static const struct pad_config gpio_table[] = {
 	/* GPP_D16:     HDA_RST# */
 	PAD_NC(GPP_D16, NONE),
 	/* GPP_D17:     FPMCU_INT# */
-	PAD_CFG_GPI_INT(GPP_D17, NONE, PLTRST, LEVEL),
+	PAD_CFG_GPI_IRQ_WAKE(GPP_D17, NONE, PWROK, LEVEL, INVERT),
 	/* GPP_D18:     CLKREQ_PCIE#6 */
 	PAD_CFG_NF(GPP_D18, NONE, DEEP, NF1),
 	/* GPP_D19:     SOC_SD_RST# */
@@ -286,16 +286,16 @@ static const struct pad_config gpio_table[] = {
 	PAD_NC(GPP_F14, NONE),
 	/* GPP_F15:     Not used */
 	PAD_NC(GPP_F15, NONE),
-	/* GPP_F16:     SOC_THC_1_RST# */
-	PAD_CFG_GPO(GPP_F16, 0, DEEP),
+	/* GPP_F16:     Not used */
+	PAD_NC(GPP_F16, NONE),
 	/* GPP_F17:     SOC_THC_1_CS# */
 	PAD_CFG_NF(GPP_F17, NONE, DEEP, NF5),
-	/* GPP_F18:     SOC_THC_1_INT# */
-	PAD_CFG_GPI_APIC(GPP_F18, NONE, PWROK, LEVEL, INVERT),
+	/* GPP_F18:     Not used */
+	PAD_NC(GPP_F18, NONE),
 	/* GPP_F19:     Not used */
 	PAD_NC(GPP_F19, NONE),
 	/* GPP_F20:     AP_FP_FW_UP_STRAP */
-	PAD_CFG_GPO(GPP_F20, 1, DEEP),
+	PAD_CFG_GPO_LOCK(GPP_F20, 0, LOCK_CONFIG),
 	/* GPP_F22:     Not used */
 	PAD_NC(GPP_F22, NONE),
 	/* GPP_F23:     SLP_S0#_GATE */
@@ -308,7 +308,7 @@ static const struct pad_config gpio_table[] = {
 	/* GPP_H02:     Not used */
 	PAD_NC(GPP_H02, NONE),
 	/* GPP_H03:     EN_PWR_FP */
-	PAD_CFG_GPO(GPP_H03, 0, DEEP),
+	PAD_CFG_GPO(GPP_H03, 1, DEEP),
 	/* GPP_H04:     COEX1 */
 	PAD_CFG_NF(GPP_H04, NONE, DEEP, NF2),
 	/* GPP_H05:     COEX2 */
@@ -334,7 +334,7 @@ static const struct pad_config gpio_table[] = {
 	/* GPP_H16:     SOC_AUDIO_STRAP */
 	PAD_CFG_GPI(GPP_H16, NONE, DEEP),
 	/* GPP_H17:     FP_RST_1V8_OD# */
-	PAD_CFG_GPO(GPP_H17, 1, DEEP),
+	PAD_CFG_GPO_LOCK(GPP_H17, 1, LOCK_CONFIG),
 	/* GPP_H19:     Not used*/
 	PAD_NC(GPP_H19, NONE),
 	/* GPP_H20:     Not used */
@@ -420,10 +420,10 @@ static const struct pad_config romstage_gpio_table[] = {
 	PAD_CFG_NF(GPP_C00, NONE, DEEP, NF1),
 	/* GPP_C01:     SOC_SMBDATA */
 	PAD_CFG_NF(GPP_C01, NONE, DEEP, NF1),
-	/* GPP_F16:     SOC_THC_1_RST# */
-	PAD_CFG_GPO(GPP_F16, 0, DEEP),
 	/* GPP_H03:     EN_PWR_FP */
 	PAD_CFG_GPO(GPP_H03, 0, DEEP),
+	/* GPP_H17:     FP_RST_1V8_OD# */
+	PAD_CFG_GPO(GPP_H17, 0, DEEP),
 };
 
 const struct pad_config *variant_gpio_table(size_t *num)
diff --git a/src/mainboard/google/fatcat/variants/francka/overridetree.cb b/src/mainboard/google/fatcat/variants/francka/overridetree.cb
index 58ced1aa07..580e96fb3a 100644
--- a/src/mainboard/google/fatcat/variants/francka/overridetree.cb
+++ b/src/mainboard/google/fatcat/variants/francka/overridetree.cb
@@ -62,6 +62,12 @@ chip soc/intel/pantherlake
 		[PchSerialIoIndexI2C4]  = PchSerialIoPci,
 	}"
 
+	register "serial_io_gspi_mode" = "{
+		[PchSerialIoIndexGSPI0] = PchSerialIoDisabled,
+		[PchSerialIoIndexGSPI1] = PchSerialIoPci,
+		[PchSerialIoIndexGSPI0A] = PchSerialIoDisabled,
+	}"
+
 	# Intel Common SoC Config
 	#+-------------------+---------------------------+
 	#| Field             |  Value                    |
@@ -292,13 +298,13 @@ chip soc/intel/pantherlake
 				register "hid" = "ACPI_DT_NAMESPACE_HID"
 				register "uid" = "1"
 				register "compat_string" = ""google,cros-ec-spi""
-				register "irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_F18_IRQ)"
-				register "wake" = "GPE0_DW2_15"
+				register "irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_D17_IRQ)"
+				register "wake" = "GPE0_DW1_17"
 				register "has_power_resource" = "true"
-				register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_F16)"
+				register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_H17)"
 				register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_H03)"
 				register "enable_delay_ms" = "3"
-				device spi 0 hidden end
+				device spi 0 on end
 			end # FPMCU
 		end
 	end

From c1ad986f3a2f68ea33c338ab16496ef1ddc260f7 Mon Sep 17 00:00:00 2001
From: John Su <john_su@compal.corp-partner.google.com>
Date: Fri, 14 Feb 2025 14:55:25 +0800
Subject: [PATCH 0109/3886] mb/trulo/var/uldrenite: Fix WWAN_RST pin

Fix WWAN_RST pin due to previous incorrect configuration.

BUG=b:395430920
TEST=emerge-nissa coreboot

Change-Id: I6012a11e5c54e79e31b0cbfca657174274658368
Signed-off-by: John Su <john_su@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86415
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
---
 .../google/brya/variants/uldrenite/include/variant/gpio.h       | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/mainboard/google/brya/variants/uldrenite/include/variant/gpio.h b/src/mainboard/google/brya/variants/uldrenite/include/variant/gpio.h
index 25edb0c108..612ea2adbb 100644
--- a/src/mainboard/google/brya/variants/uldrenite/include/variant/gpio.h
+++ b/src/mainboard/google/brya/variants/uldrenite/include/variant/gpio.h
@@ -7,7 +7,7 @@
 
 #define WWAN_FCPO	GPP_H23
 #define WWAN_RST	GPP_F12
-#define WWAN_PERST	GPP_H13
+#define WWAN_PERST	GPP_F13
 #define T1_OFF_MS	20
 #define T2_OFF_MS	10
 

From 19bcc7653b542cc75c9f8d200927cdba2f03c1c5 Mon Sep 17 00:00:00 2001
From: John Su <john_su@compal.corp-partner.google.com>
Date: Fri, 14 Feb 2025 16:08:01 +0800
Subject: [PATCH 0110/3886] mb/trulo/var/uldrenite: Remove GPP_B5 and B6 as ISH
 function

It will cause suspend to fail to enter S0ix. After discussion
with SOC and HW teams, remove GPP_B5 and B6 as ISH function and
disable ISH on the devicetree.

BUG=b:383696667, b:395005219
TEST=emerge-nissa coreboot

Change-Id: Id3d26f1b604b889f4fdb6e45218f4118499c303e
Signed-off-by: John Su <john_su@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86416
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
---
 src/mainboard/google/brya/variants/uldrenite/gpio.c       | 8 ++++----
 .../google/brya/variants/uldrenite/overridetree.cb        | 1 +
 2 files changed, 5 insertions(+), 4 deletions(-)

diff --git a/src/mainboard/google/brya/variants/uldrenite/gpio.c b/src/mainboard/google/brya/variants/uldrenite/gpio.c
index f926e3ac47..3e11b48d0a 100644
--- a/src/mainboard/google/brya/variants/uldrenite/gpio.c
+++ b/src/mainboard/google/brya/variants/uldrenite/gpio.c
@@ -61,10 +61,10 @@ static const struct pad_config gpio_table[] = {
 	PAD_CFG_GPI_IRQ_WAKE(GPP_B3, NONE, PWROK, LEVEL, INVERT),
 	/* B4  : PROC_GP3 ==> EN_PP3300_UCAM_X */
 	PAD_CFG_GPO_LOCK(GPP_B4, 1, LOCK_CONFIG),
-	/* B5  : GPP_B5 ==> ISH_I2C0_SCL */
-	PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_B5, NONE, DEEP, NF1),
-	/* B6  : GPP_B6 ==> ISH_I2C0_SDA */
-	PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_B6, NONE, DEEP, NF1),
+	/* B5  : GPP_B5 ==> NC */
+	PAD_NC(GPP_B5, NONE),
+	/* B6  : GPP_B6 ==> NC */
+	PAD_NC(GPP_B6, NONE),
 	/* B7  : GPP_B7 ==> NC */
 	PAD_NC_LOCK(GPP_B7, NONE, LOCK_CONFIG),
 	/* B8  : GPP_B8 ==> NC */
diff --git a/src/mainboard/google/brya/variants/uldrenite/overridetree.cb b/src/mainboard/google/brya/variants/uldrenite/overridetree.cb
index 285db4aa96..dd129d7b9e 100644
--- a/src/mainboard/google/brya/variants/uldrenite/overridetree.cb
+++ b/src/mainboard/google/brya/variants/uldrenite/overridetree.cb
@@ -490,6 +490,7 @@ chip soc/intel/alderlake
 			end
 			probe DB_CELLULAR CELLULAR_RW350R
 		end # PCIE2 WWAN card
+		device ref ish off end
 		device ref shared_sram on end
 		device ref heci1 on end
 		device ref pmc hidden end

From 4aeaa453e32d97e8a732de75192be8f6c3e84ea8 Mon Sep 17 00:00:00 2001
From: Hualin Wei <weihualin@huaqin.corp-partner.google.com>
Date: Thu, 13 Feb 2025 19:37:56 +0800
Subject: [PATCH 0111/3886] mb/google/nissa/var/pujjoniru: Update DTT settings
 for thermal control

update DTT settings for thermal control, according to
b:395802079#comment2.

BUG=b:395802079
TEST=emerge-nissa coreboot

Change-Id: Ia32911488464af4e5070543e2ec630c339ab1925
Signed-off-by: Hualin Wei <weihualin@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86404
Reviewed-by: Qinghong Zeng <zengqinghong@huaqin.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
---
 .../brya/variants/pujjoniru/overridetree.cb   | 154 +++++++++++-------
 1 file changed, 96 insertions(+), 58 deletions(-)

diff --git a/src/mainboard/google/brya/variants/pujjoniru/overridetree.cb b/src/mainboard/google/brya/variants/pujjoniru/overridetree.cb
index 11098ac4ed..60d3117d05 100644
--- a/src/mainboard/google/brya/variants/pujjoniru/overridetree.cb
+++ b/src/mainboard/google/brya/variants/pujjoniru/overridetree.cb
@@ -101,35 +101,79 @@ chip soc/intel/alderlake
 			.tdp_pl4 = 78,
 	}"
 
+	register "power_limits_config[ADL_N_081_15W_CORE]" = "{
+			.tdp_pl1_override = 15,
+			.tdp_pl2_override = 25,
+			.tdp_pl4 = 114,
+	}"
+
 	device domain 0 on
 		device ref dtt on
 			chip drivers/intel/dptf
 				## sensor information
-				register "options.tsr[0].desc" = ""CPU_VR""
+				register "options.tsr[0].desc" = ""5V""
 				register "options.tsr[1].desc" = ""CPU""
-				register "options.tsr[2].desc" = ""Ambient""
+				register "options.tsr[2].desc" = ""AMB""
 				register "options.tsr[3].desc" = ""Charger""
 
 				# TODO: below values are initial reference values only
+				## Active Policy
+				register "policies.active" = "{
+					[0] = {
+						.target = DPTF_TEMP_SENSOR_0,
+						.thresholds = {
+								TEMP_PCT(80, 90),
+								TEMP_PCT(75, 80),
+								TEMP_PCT(70, 70),
+								TEMP_PCT(60, 50),
+						}
+					},
+					[1] = {
+						.target = DPTF_TEMP_SENSOR_1,
+						.thresholds = {
+								TEMP_PCT(51, 69),
+								TEMP_PCT(48, 57),
+								TEMP_PCT(44, 50),
+								TEMP_PCT(42, 45),
+								TEMP_PCT(40, 39),
+						}
+					},
+					[2] = {
+						.target = DPTF_TEMP_SENSOR_2,
+						.thresholds = {
+								TEMP_PCT(75, 90),
+								TEMP_PCT(70, 80),
+								TEMP_PCT(65, 70),
+								TEMP_PCT(55, 50),
+						}
+					},
+					[3] = {
+						.target = DPTF_TEMP_SENSOR_3,
+						.thresholds = {
+								TEMP_PCT(90, 90),
+								TEMP_PCT(85, 80),
+								TEMP_PCT(75, 70),
+								TEMP_PCT(70, 50),
+						}
+					}
+				}"
+
 				## Passive Policy
 				register "policies.passive" = "{
-					[0] = DPTF_PASSIVE(CPU,	CPU,	85, 6000),
-					[1] = DPTF_PASSIVE(CPU,	TEMP_SENSOR_0,	85, 6000),
-					[2] = DPTF_PASSIVE(CPU,	TEMP_SENSOR_1,	85, 6000),
-					[3] = DPTF_PASSIVE(CPU,	TEMP_SENSOR_2,	85, 5000),
-					[4] = DPTF_PASSIVE(CHARGER,	TEMP_SENSOR_3,	85, 6000),
+					[1] = DPTF_PASSIVE(CPU,	TEMP_SENSOR_1,	85, 4000),
+					[2] = DPTF_PASSIVE(CHARGER,	TEMP_SENSOR_3,	80, 5000),
 				}"
 
 				## Critical Policy
 				register "policies.critical" = "{
-					[0] = DPTF_CRITICAL(TEMP_SENSOR_1,	90,	SHUTDOWN),
-					[1] = DPTF_CRITICAL(TEMP_SENSOR_2,	90,	SHUTDOWN),
+					[1] = DPTF_CRITICAL(TEMP_SENSOR_1,	95,	SHUTDOWN),
+					[2] = DPTF_CRITICAL(TEMP_SENSOR_3,	95,	SHUTDOWN),
 				}"
 
 				register "controls.power_limits" = "{
 					.pl1 = {
 							.min_power = 6000,
-							.max_power = 6000,
+							.max_power = 9000,
 							.time_window_min = 28 * MSECS_PER_SEC,
 							.time_window_max = 32 * MSECS_PER_SEC,
 							.granularity = 200
@@ -145,9 +189,9 @@ chip soc/intel/alderlake
 
 				## Charger Performance Control (Control, mA)
 				register "controls.charger_perf" = "{
-						[0] = { 255, 3000 },
-						[1] = {  24, 1500 },
-						[2] = {  16, 1000 },
+						[0] = { 255, 4200 },
+						[1] = {  48, 3000 },
+						[2] = {  32, 2000 },
 						[3] = {   8,  500 }
 				}"
 
@@ -175,9 +219,9 @@ chip soc/intel/alderlake
 
 			chip drivers/intel/dptf
 				## sensor information
-				register "options.tsr[0].desc" = ""CPU_VR""
+				register "options.tsr[0].desc" = ""5V""
 				register "options.tsr[1].desc" = ""CPU""
-				register "options.tsr[2].desc" = ""Ambient""
+				register "options.tsr[2].desc" = ""AMB""
 				register "options.tsr[3].desc" = ""Charger""
 
 				# TODO: below values are initial reference values only
@@ -186,70 +230,64 @@ chip soc/intel/alderlake
 					[0] = {
 						.target = DPTF_TEMP_SENSOR_0,
 						.thresholds = {
-								TEMP_PCT(85, 90),
-								TEMP_PCT(54, 64),
-								TEMP_PCT(52, 52),
-								TEMP_PCT(50, 44),
-								TEMP_PCT(48, 38),
-								TEMP_PCT(45, 34),
+								TEMP_PCT(80, 90),
+								TEMP_PCT(75, 80),
+								TEMP_PCT(70, 70),
+								TEMP_PCT(65, 50),
 						}
 					},
 					[1] = {
 						.target = DPTF_TEMP_SENSOR_1,
 						.thresholds = {
-								TEMP_PCT(75, 90),
-								TEMP_PCT(70, 80),
-								TEMP_PCT(65, 70),
-								TEMP_PCT(60, 60),
-								TEMP_PCT(55, 50),
-								TEMP_PCT(50, 40),
+								TEMP_PCT(51, 69),
+								TEMP_PCT(48, 57),
+								TEMP_PCT(44, 50),
+								TEMP_PCT(42, 45),
+								TEMP_PCT(40, 39),
 						}
 					},
 					[2] = {
 						.target = DPTF_TEMP_SENSOR_2,
+						.thresholds = {
+								TEMP_PCT(75, 90),
+								TEMP_PCT(70, 80),
+								TEMP_PCT(65, 70),
+								TEMP_PCT(55, 50),
+						}
+					},
+					[3] = {
+						.target = DPTF_TEMP_SENSOR_3,
 						.thresholds = {
 								TEMP_PCT(90, 90),
 								TEMP_PCT(85, 80),
 								TEMP_PCT(75, 70),
 								TEMP_PCT(70, 50),
 						}
-					},
-					[3] = {
-						.target = DPTF_TEMP_SENSOR_3,
-						.thresholds = {
-								TEMP_PCT(80, 90),
-								TEMP_PCT(75, 80),
-								TEMP_PCT(70, 70),
-								TEMP_PCT(65, 50),
-						}
 					}
 				}"
 				## Passive Policy
 				register "policies.passive" = "{
-					[0] = DPTF_PASSIVE(CPU,	CPU,	85,	6000),
-					[1] = DPTF_PASSIVE(CPU,	TEMP_SENSOR_0,	85,	6000),
-					[2] = DPTF_PASSIVE(CPU,	TEMP_SENSOR_1,	85,	6000),
-					[3] = DPTF_PASSIVE(CPU,	TEMP_SENSOR_2,	85,	6000),
-					[4] = DPTF_PASSIVE(CHARGER,	TEMP_SENSOR_3,	85,	6000),
+					[1] = DPTF_PASSIVE(CPU,	TEMP_SENSOR_1,	85,	5000),
+					[2] = DPTF_PASSIVE(CHARGER,	TEMP_SENSOR_3,	80,	5000),
 				}"
 
 				## Critical Policy
 				register "policies.critical" = "{
-					[0] = DPTF_CRITICAL(TEMP_SENSOR_1,	90,	SHUTDOWN),
-					[1] = DPTF_CRITICAL(TEMP_SENSOR_2,	90,	SHUTDOWN),
+					[0] = DPTF_CRITICAL(TEMP_SENSOR_1,	95,	SHUTDOWN),
+					[1] = DPTF_CRITICAL(TEMP_SENSOR_3,	95,	SHUTDOWN),
 				}"
 
 				register "controls.power_limits" = "{
 					.pl1 = {
-							.min_power = 15000,
+							.min_power = 12000,
 							.max_power = 15000,
 							.time_window_min = 28 * MSECS_PER_SEC,
 							.time_window_max = 32 * MSECS_PER_SEC,
 							.granularity = 200
 						},
 					.pl2 = {
-							.min_power = 35000,
-							.max_power = 35000,
+							.min_power = 25000,
+							.max_power = 25000,
 							.time_window_min = 28 * MSECS_PER_SEC,
 							.time_window_max = 32 * MSECS_PER_SEC,
 							.granularity = 1000
@@ -258,23 +296,23 @@ chip soc/intel/alderlake
 
 				## Charger Performance Control (Control, mA)
 				register "controls.charger_perf" = "{
-					[0] = { 255, 3000 },
-					[1] = {  24, 2000 },
-					[2] = {  16, 1000 },
+					[0] = { 255, 4200 },
+					[1] = {  48, 3000 },
+					[2] = {  32, 2000 },
 					[3] = {   8,  500 }
 				}"
 
 				## Fan Performance Control (Percent, Speed, Noise, Power)
 				register "controls.fan_perf" = "{
-					[0] = {  100, 4000, 220, 1640, },
-					[1] = {  90, 3700, 220, 1640, },
-					[2] = {  80, 3500, 180, 1310, },
-					[3] = {  70, 3300, 145, 1030, },
-					[4] = {  60, 3100, 115, 765, },
-					[5] = {  50, 2800,  90,  545, },
-					[6] = {  40, 2500,  55,  365, },
-					[7] = {  30, 2100,  30,  220, },
-					[8] = {  20, 1500,  15,  120, },
+					[0] = {  90, 4734, 220, 1640, },
+					[1] = {  80, 4443, 180, 1310, },
+					[2] = {  70, 4108, 145, 1030, },
+					[3] = {  60, 3752, 115, 765, },
+					[4] = {  50, 3352,  90,  545, },
+					[5] = {  40, 2897,  55,  365, },
+					[6] = {  30, 2363,  30,  220, },
+					[7] = {  20, 1752,  15,  120, },
+					[8] = {  10,  918,  10,  60, },
 					[9] = {   0,    0,   0,   50, }
 				}"
 

From ac6212805d471c20d91ba79ab0d71c79d9c62336 Mon Sep 17 00:00:00 2001
From: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Date: Thu, 13 Feb 2025 14:42:14 +0800
Subject: [PATCH 0112/3886] src/Kconfig: Add config SYSTEM_TYPE_BOX

Add config SYSTEM_TYPE_BOX to allow proper system type selection for
devices like chromebox, mac-mini etc.

Change-Id: I887413cbc09fb0725b2ffd621fe10991b7dbcf6d
Signed-off-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86396
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Eric Lai <ericllai@google.com>
---
 src/Kconfig | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/src/Kconfig b/src/Kconfig
index 320d6db32c..1d71840308 100644
--- a/src/Kconfig
+++ b/src/Kconfig
@@ -652,6 +652,13 @@ endmenu
 # load site-local kconfig to allow user specific defaults and overrides
 source "site-local/Kconfig"
 
+config SYSTEM_TYPE_BOX
+	default n
+	bool
+	help
+	  For devices like chromebox, mac-mini etc. These devices
+	  without built-in display and operates on AC supply alone.
+
 config SYSTEM_TYPE_LAPTOP
 	default n
 	bool

From 6e3c56dcd011a61de4a4dc9ea46666305de8a7ef Mon Sep 17 00:00:00 2001
From: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Date: Thu, 13 Feb 2025 14:45:44 +0800
Subject: [PATCH 0113/3886] mb/google/brya/Kconfig: Select SYSTEM_TYPE_BOX for
 Dirks

Dirks is a Chromebox device, so select SYSTEM_TYPE_BOX for it. Other
nissa variants will continue to have SYSTEM_TYPE_LAPTOP selected.

BUG=b:389391653
TEST=emerge-nissa coreboot
     check CONFIG_CSE_RESET_CLEAR_EC_AP_IDLE_FLAG=y
     check CONFIG_CR50_RESET_CLEAR_EC_AP_IDLE_FLAG=y

Change-Id: Iabc9afdfdb07d4d6cb4d3fb4b43bfdc3cf2aa383
Signed-off-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86392
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
---
 src/mainboard/google/brya/Kconfig | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/src/mainboard/google/brya/Kconfig b/src/mainboard/google/brya/Kconfig
index 8d09f2e562..213d49967c 100644
--- a/src/mainboard/google/brya/Kconfig
+++ b/src/mainboard/google/brya/Kconfig
@@ -97,7 +97,7 @@ config BOARD_GOOGLE_BASEBOARD_NISSA
 	select SOC_INTEL_ALDERLAKE_PCH_N
 	select SOC_INTEL_CSE_LITE_COMPRESS_ME_RW
 	select SOC_INTEL_CSE_LITE_SYNC_IN_RAMSTAGE
-	select SYSTEM_TYPE_LAPTOP
+	select SYSTEM_TYPE_LAPTOP if !SYSTEM_TYPE_BOX
 	select TPM_GOOGLE_TI50
 	select SOC_INTEL_COMMON_MMC_OVERRIDE
 
@@ -223,6 +223,7 @@ config BOARD_GOOGLE_CROTA
 config BOARD_GOOGLE_DIRKS
 	select BOARD_GOOGLE_BASEBOARD_NISSA
 	select SOC_INTEL_TWINLAKE
+	select SYSTEM_TYPE_BOX
 
 config BOARD_GOOGLE_DOCHI
 	select BOARD_GOOGLE_BASEBOARD_BRYA

From 29054bc9c76d22c6fb0058bbe3dd5609dd07598e Mon Sep 17 00:00:00 2001
From: Subrata Banik <subratabanik@google.com>
Date: Thu, 13 Feb 2025 11:35:46 +0530
Subject: [PATCH 0114/3886] soc/intel/pantherlake: Skip exposing CPUJTAG at
 kernel

This patch prevents exposing the CPU JTAG GPIO pads. These are
internal GPIO pins used for debugging the SoC and should not be
configurable from the kernel pinctrl driver.

TEST=Able to build and boot google/fatat. Decompile ACPI table
using iasl and ensure CPUJTAG entry not present.

Change-Id: I4d920acb95275fbf72b83b822eddc41829511626
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86393
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
Reviewed-by: Jayvik Desai <jayvik@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
---
 src/soc/intel/pantherlake/acpi/gpio.asl       | 43 ++++---------------
 .../pantherlake/include/soc/gpio_soc_defs.h   |  1 -
 2 files changed, 8 insertions(+), 36 deletions(-)

diff --git a/src/soc/intel/pantherlake/acpi/gpio.asl b/src/soc/intel/pantherlake/acpi/gpio.asl
index c16513b801..653f00b72b 100644
--- a/src/soc/intel/pantherlake/acpi/gpio.asl
+++ b/src/soc/intel/pantherlake/acpi/gpio.asl
@@ -27,10 +27,10 @@ Method (GADD, 1, NotSerialized)
 		Local1 = Arg0 - COM1_GRP_PAD_START
 	}
 	/* GPIO Community 3 */
-	If (Arg0 >= COM3_GRP_PAD_START && Arg0 <= COM3_GRP_PAD_END)
+	If (Arg0 >= GPP_H00 && Arg0 <= COM3_GRP_PAD_END)
 	{
 		Local0 = PID_GPIOCOM3
-		Local1 = Arg0 - COM3_GRP_PAD_START
+		Local1 = Arg0 - GPP_H00
 	}
 	/* GPIO Community 4 */
 	If (Arg0 >= COM4_GRP_PAD_START && Arg0 <= COM4_GRP_PAD_END)
@@ -438,7 +438,7 @@ Device (GPI1)
 	}
 }
 
-/* GPIO Community 3: CPUJTAG, GPP_H, GPP_A, VGPIO3 */
+/* GPIO Community 3: GPP_H, GPP_A, VGPIO3 */
 Device (GPI3)
 {
 	Name (_HID, ACPI_GPIO_HID)
@@ -471,7 +471,7 @@ Device (GPI3)
 			Package (0x02)
 			{
 				"intc-gpio-group-count",
-				NUM_COM3_GROUPS
+				NUM_COM3_GROUPS - 1 /* Skip CPUJTAG */
 			},
 
 			Package (0x02)
@@ -508,12 +508,6 @@ Device (GPI3)
 		ToUUID ("dbb8e3e6-5886-4ba6-8795-1319f52a966b"),
 		Package (0x04)
 		{
-			Package (0x02)
-			{
-				"intc-gpio-group-0-subproperties",
-				JTAG
-			},
-
 			Package (0x02)
 			{
 				"intc-gpio-group-1-subproperties",
@@ -533,31 +527,10 @@ Device (GPI3)
 			}
 		}
 	})
-	/* first bank/group in community 3: CPUJTAG */
-	Name (JTAG, Package (0x02)
-	{
-		ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
-		Package (0x03)
-		{
-			Package (0x02)
-			{
-				"intc-gpio-group-name",
-				GPP_CPUJTAG_NAME
-			},
-
-			Package (0x02)
-			{
-				"intc-gpio-pad-count",
-				NUM_GRP_CPUJTAG_PADS
-			},
-
-			Package (0x02)
-			{
-				"intc-gpio-group-offset",
-				GPP_CPUJTAG_START_OFFSET
-			}
-		}
-	})
+	/*
+	 * Don't expose first bank/group in community 3: CPUJTAG because
+	 * CPUJTAG doesn't required to be controlled by kernel pinctrl driver.
+	 */
 	/* 2nd bank/group in community 3: GPP_H */
 	Name (GPPH, Package (0x02)
 	{
diff --git a/src/soc/intel/pantherlake/include/soc/gpio_soc_defs.h b/src/soc/intel/pantherlake/include/soc/gpio_soc_defs.h
index 0937d1e81f..69f2f7e4ac 100644
--- a/src/soc/intel/pantherlake/include/soc/gpio_soc_defs.h
+++ b/src/soc/intel/pantherlake/include/soc/gpio_soc_defs.h
@@ -37,7 +37,6 @@
 #define GPP_C_NAME		"GPP_C"
 #define GPP_F_NAME		"GPP_F"
 #define GPP_E_NAME		"GPP_E"
-#define GPP_CPUJTAG_NAME	"GPUJTAG"
 #define GPP_H_NAME		"GPP_H"
 #define GPP_A_NAME		"GPP_A"
 #define GPP_VGPIO3_NAME		"vGPIO_3"

From 145b174116e8a1eaac8add48090835248f3dd17d Mon Sep 17 00:00:00 2001
From: Riku Viitanen <riku.viitanen@protonmail.com>
Date: Fri, 14 Feb 2025 01:02:11 +0200
Subject: [PATCH 0115/3886] mb/hp/snb_ivb_desktops/dt: Remove what matches
 defaults

These are unnecessary because they are the same as the chipset
devicetree defaults.

Change-Id: Id26f09674457720ad56a19b6b0884b8012be9019
Signed-off-by: Riku Viitanen <riku.viitanen@protonmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86412
Reviewed-by: Nicholas Chin <nic.c3.14@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 .../hp/snb_ivb_desktops/devicetree.cb         | 20 -------------------
 1 file changed, 20 deletions(-)

diff --git a/src/mainboard/hp/snb_ivb_desktops/devicetree.cb b/src/mainboard/hp/snb_ivb_desktops/devicetree.cb
index 6f3d28ea9b..a381c3b2a5 100644
--- a/src/mainboard/hp/snb_ivb_desktops/devicetree.cb
+++ b/src/mainboard/hp/snb_ivb_desktops/devicetree.cb
@@ -1,44 +1,27 @@
 ## SPDX-License-Identifier: GPL-2.0-only
 
 chip northbridge/intel/sandybridge
-	register "gfx.use_spread_spectrum_clock" = "0"
-	register "gpu_dp_b_hotplug" = "0"
-	register "gpu_dp_c_hotplug" = "0"
-	register "gpu_dp_d_hotplug" = "0"
 	# BTX mainboard: Reversed mapping
 	register "spd_addresses" = "{0x53, 0x52, 0x51, 0x50}"
 
 	device domain 0 on
-		device ref host_bridge on  end
 		device ref peg10 on  end
 		device ref igd on  end
-		device ref peg60 off end
 
 		chip southbridge/intel/bd82x6x # Intel Series 7 PCH
-			register "docking_supported" = "false"
 			register "gen1_dec" = "0x00fc0601"
 			register "gen2_dec" = "0x00fc0801"
-			register "pcie_hotplug_map" = "{ 0, 0, 0, 0, 0, 0, 0, 0 }"
 			register "pcie_port_coalesce" = "true"
 			register "sata_interface_speed_support" = "0x3"
 			register "spi_lvscc" = "0x2005"
 			register "spi_uvscc" = "0x2005"
 
-			device ref mei1 on  end
-			device ref mei2 off end
-			device ref me_ide_r off end
 			device ref me_kt on  end
 			device ref gbe on  end
 			device ref ehci2 on  end
 			device ref hda on  end
 			device ref pcie_rp1 on  end
-			device ref pcie_rp2 off end
-			device ref pcie_rp3 off end
-			device ref pcie_rp4 off end
 			device ref pcie_rp5 on  end
-			device ref pcie_rp6 off end
-			device ref pcie_rp7 off end
-			device ref pcie_rp8 off end
 			device ref ehci1 on  end
 			device ref pci_bridge on  end
 			device ref lpc on
@@ -147,9 +130,6 @@ chip northbridge/intel/sandybridge
 				end
 			end
 			device ref sata1 on  end
-			device ref smbus on  end
-			device ref sata2 off end
-			device ref thermal off end
 		end
 	end
 end

From d1a5a345b4593adde9d04f8d8cba5cdbb1cdfc20 Mon Sep 17 00:00:00 2001
From: Yidi Lin <yidilin@chromium.org>
Date: Mon, 17 Feb 2025 08:20:24 +0000
Subject: [PATCH 0116/3886] Update arm-trusted-firmware submodule to upstream
 master

Updating from commit id 15e5c6c91d48:
2024-12-05 16:00:37 +0100 - (Merge changes I00d2de7b,I5ec82646 into integration)

to commit id 0c370e2d592b:
2025-02-04 18:14:07 +0100 - (Merge "feat(mt8196): add SMMU driver for PM" into integration)

This brings in 414 new commits.

Change-Id: I5cb4fab45fb82463f0ae3332e46995d30d123352
Signed-off-by: Yidi Lin <yidilin@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86478
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 3rdparty/arm-trusted-firmware | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/3rdparty/arm-trusted-firmware b/3rdparty/arm-trusted-firmware
index 15e5c6c91d..0c370e2d59 160000
--- a/3rdparty/arm-trusted-firmware
+++ b/3rdparty/arm-trusted-firmware
@@ -1 +1 @@
-Subproject commit 15e5c6c91d483aa52908154cc80e48956e234232
+Subproject commit 0c370e2d592b96554ac6d5dca4242733ab14300f

From f07b2f2091afbaa423bb6a47e2edf912f720abf4 Mon Sep 17 00:00:00 2001
From: Elyes Haouas <ehaouas@noos.fr>
Date: Mon, 17 Feb 2025 17:22:58 +0100
Subject: [PATCH 0117/3886] mb/google/kukui: Drop non-existent directory from
 subdir-y

Change-Id: Ifafec925439375dc2c9237244eff24c7bbe56bd6
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86486
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
---
 src/mainboard/google/kukui/Makefile.mk | 1 -
 1 file changed, 1 deletion(-)

diff --git a/src/mainboard/google/kukui/Makefile.mk b/src/mainboard/google/kukui/Makefile.mk
index 7b0298d61e..e1df671d56 100644
--- a/src/mainboard/google/kukui/Makefile.mk
+++ b/src/mainboard/google/kukui/Makefile.mk
@@ -1,7 +1,6 @@
 ## SPDX-License-Identifier: GPL-2.0-only
 
 subdirs-y += sdram_params/
-subdirs-y += panel_params/
 
 bootblock-y += bootblock.c
 bootblock-y += reset.c

From 31d583facacfe112aea609dd1b43e0e854d3eec4 Mon Sep 17 00:00:00 2001
From: Subrata Banik <subratabanik@google.com>
Date: Fri, 14 Feb 2025 19:16:50 +0530
Subject: [PATCH 0118/3886] soc/intel/pantherlake: Enable Thunderbolt
 authentication

This commit enables Thunderbolt authentication for Panther Lake by
assigning `ioe_tcss_valid_tbt_auth` to the valid_tbt_auth field in
`soc_tcss_ops`.

For the SoC's integrated PD solution, AUX BIAS PAD programming is not
required and has been removed.

TEST=Verified all USB-C ports are functional.

With this patch, \_SB.PCI0.TDM0._DSD exists in the SSDT, containing:
```
  Scope (\_SB.PCI0.TDM0)
    {
        Name (_DSD, Package (0x04)  // _DSD: Device-Specific Data
        {
            ToUUID ("c44d002f-69f9-4e7d-a904-a7baabdf43f7"),
            Package (0x01)
            {
                Package (0x02)
                {
                    "IMR_VALID",
                    One
                }
            },

            ToUUID ("6c501103-c189-4296-ba72-9bf5a26ebe5d"),
            Package (0x01)
            {
                Package (0x02)
                {
                    "WAKE_SUPPORTED",
                    One
                }
         }
    }
```

Change-Id: I28eac7cfd6511d8680cdae4f830afa73ad201a17
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86420
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jayvik Desai <jayvik@google.com>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
---
 src/soc/intel/pantherlake/tcss.c | 10 ++++++++--
 1 file changed, 8 insertions(+), 2 deletions(-)

diff --git a/src/soc/intel/pantherlake/tcss.c b/src/soc/intel/pantherlake/tcss.c
index 99cbdd2d67..c66a5c68ce 100644
--- a/src/soc/intel/pantherlake/tcss.c
+++ b/src/soc/intel/pantherlake/tcss.c
@@ -2,9 +2,15 @@
 
 #include <intelblocks/tcss.h>
 #include <soc/soc_chip.h>
+#include <static.h>
 
 const struct soc_tcss_ops tcss_ops = {
-/* TODO: Implement AUX BIAS PAD Programming if required */
 	.configure_aux_bias_pads = NULL,
-	.valid_tbt_auth = NULL,
+	.valid_tbt_auth = ioe_tcss_valid_tbt_auth,
 };
+
+bool ioe_tcss_valid_tbt_auth(void)
+{
+	const config_t *config = config_of_soc();
+	return config->tbt_authentication;
+}

From cae4caaf8461cbaf6f2d80ca69d616f4c60805d8 Mon Sep 17 00:00:00 2001
From: Cliff Huang <cliff.huang@intel.com>
Date: Wed, 5 Feb 2025 15:19:35 -0800
Subject: [PATCH 0119/3886] soc/intel/pantherlake: Enable multiple ACPI devices
 for GPIO

In the Panther Lake architecture, each GPIO community functions as a
separate pin control entity. Therefore, when specifying a GPIO
identifier, one should use the community-specific offset, not the number
from the first pad within the GPIO series. This is achieved by selecting
the Kconfig option SOC_INTEL_COMMON_BLOCK_GPIO_MULTI_ACPI_DEVICES within
the Panther Lake SOC Kconfig file.

The numbers within the _CRS GpioInt and GpIo objects in the SSDT should
be offsets within the community. The GPIO identifier employed should
correspond to the offset from the respective community.

Let's take an example. In the fatcat board overridetree.cb,
ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E19) points to GPIO Group E. The pad
starts at 74. It is inside community 1, which starts at 48. The correct
GPIO reference is (19 + 74) - 48 = 45, or 0x002D in hexadecimal.

Here are two notable changes in the fatcat board SSDT introduced by this
commit.

- ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E19)

                       "\\_SB.PCI0.GPI1", 0x00, ResourceConsumer, ,
                       )
                       {   // Pin list
  -                        0x0033
  +                        0x002D
                       }
               })
               Name (_DSD, Package (0x02)  // _DSD: Device-Specific Data

- ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A16)

                   "\\_SB.PCI0.GPI3", 0x00, ResourceConsumer, ,
                   )
                   {   // Pin list
  -                    0x0050
  +                    0x003B
                   }
           })
           Name (_DSD, Package (0x02)  // _DSD: Device-Specific Data

This change is verified via S0ix in Google Fatcat board with
touchscreen/touchpad attached as the wake source.

BUG=none
TEST=Check the number from CRS GpinInt and GpIo objects in the SSDT, and
     ensure that the GPIO number used matches the community offset.
     Configure touchscreen/touchpad in THC-i2c mode on factcat board and
	 enter S0ix and check that it can be waked by touchscreen/touchpad.

Signed-off-by: Cliff Huang <cliff.huang@intel.com>
Change-Id: Ic2ba67518fa173e13975478ccae5f8a1772ebf08
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86290
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
---
 src/soc/intel/pantherlake/Kconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/src/soc/intel/pantherlake/Kconfig b/src/soc/intel/pantherlake/Kconfig
index 53260208bf..df95e529e3 100644
--- a/src/soc/intel/pantherlake/Kconfig
+++ b/src/soc/intel/pantherlake/Kconfig
@@ -65,6 +65,7 @@ config SOC_INTEL_PANTHERLAKE_BASE
 	select SOC_INTEL_COMMON_BLOCK_GPIO_DUAL_ROUTE_SUPPORT
 	select SOC_INTEL_COMMON_BLOCK_GPIO_IOSTANDBY
 	select SOC_INTEL_COMMON_BLOCK_GPIO_LOCK_USING_PCR
+	select SOC_INTEL_COMMON_BLOCK_GPIO_MULTI_ACPI_DEVICES
 	select SOC_INTEL_COMMON_BLOCK_GPIO_PMODE_4BITS
 	select SOC_INTEL_COMMON_BLOCK_GSPI_VERSION_2
 	select SOC_INTEL_COMMON_BLOCK_HDA

From 6e6b5ed915ba6dd9bbc42aedf099e98672e8d220 Mon Sep 17 00:00:00 2001
From: Tyler Wang <tyler.wang@quanta.corp-partner.google.com>
Date: Mon, 2 Dec 2024 20:02:43 +0800
Subject: [PATCH 0120/3886] mb/google/rex/var/kanix: Add Fn key scancode

The Fn key on kanix emits the scancode 94 (0x5e).

BUG=b:384580437
TEST=Build and test on kanix, the fn key works normally

Change-Id: Ia693813dafe1bd35840dfb892827598a7ca9c88f
Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85438
Reviewed-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
---
 src/mainboard/google/rex/Kconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/src/mainboard/google/rex/Kconfig b/src/mainboard/google/rex/Kconfig
index 73f28f335f..8dcd5cc957 100644
--- a/src/mainboard/google/rex/Kconfig
+++ b/src/mainboard/google/rex/Kconfig
@@ -71,6 +71,7 @@ config BOARD_GOOGLE_MODEL_KANIX
 	def_bool n
 	select BOARD_GOOGLE_BASEBOARD_REX
 	select DRIVERS_GENERIC_ALC1015
+	select MAINBOARD_HAS_GOOGLE_STRAUSS_KEYBOARD
 	select RT8168_GEN_ACPI_POWER_RESOURCE
 	select RT8168_GET_MAC_FROM_VPD
 	select RT8168_SET_LED_MODE

From 6304435023d32331ac9922d1b7f18f7e6e2fe9f7 Mon Sep 17 00:00:00 2001
From: Alok Agarwal <alok.agarwal@intel.com>
Date: Thu, 6 Feb 2025 15:53:01 +0530
Subject: [PATCH 0121/3886] vc/intel/fsp/ptl: Update header files from 2454_00
 to 3015_00

Update header files for FSP for Panther Lake platform to version
3015_00, with the previous version being 2454_00.

Changes include:
- Updating UPD Offset in FspmUpd.h and FspsUpd.h
- Adding Sign-of-Life related UPDs in FspmUpd.h
- Adding VMD related UPDs in FspsUpd.h

BUG=b:394189627
TEST=Able to build google/fatcat.

Change-Id: I87176515d4bdd8906842fd7c2ade1e6acd339212
Signed-off-by: Alok Agarwal <alok.agarwal@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86297
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jayvik Desai <jayvik@google.com>
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
---
 .../intel/fsp/fsp2_0/pantherlake/FspmUpd.h    | 2207 +++++++++--------
 .../intel/fsp/fsp2_0/pantherlake/FspsUpd.h    |  511 ++--
 2 files changed, 1460 insertions(+), 1258 deletions(-)

diff --git a/src/vendorcode/intel/fsp/fsp2_0/pantherlake/FspmUpd.h b/src/vendorcode/intel/fsp/fsp2_0/pantherlake/FspmUpd.h
index 2c38f00c4b..82a790eec3 100644
--- a/src/vendorcode/intel/fsp/fsp2_0/pantherlake/FspmUpd.h
+++ b/src/vendorcode/intel/fsp/fsp2_0/pantherlake/FspmUpd.h
@@ -1,6 +1,6 @@
 /** @file
 
-Copyright (c) 2024, Intel Corporation. All rights reserved.<BR>
+Copyright (c) 2025, Intel Corporation. All rights reserved.<BR>
 
 Redistribution and use in source and binary forms, with or without modification,
 are permitted provided that the following conditions are met:
@@ -230,659 +230,191 @@ typedef struct {
 **/
   UINT16                      RcompTarget[5];
 
-/** Offset 0x011C - LowerBasicMemTestSize feature
+/** Offset 0x011C - Dqs Map CPU to DRAM MC 0 CH 0
+  Set Dqs mapping relationship between CPU and DRAM, Channel 0: board-dependent
+**/
+  UINT8                       DqsMapCpu2DramMc0Ch0[2];
+
+/** Offset 0x011E - Dqs Map CPU to DRAM MC 0 CH 1
+  Set Dqs mapping relationship between CPU and DRAM, Channel 1: board-dependent
+**/
+  UINT8                       DqsMapCpu2DramMc0Ch1[2];
+
+/** Offset 0x0120 - Dqs Map CPU to DRAM MC 0 CH 2
+  Set Dqs mapping relationship between CPU and DRAM, Channel 2: board-dependent
+**/
+  UINT8                       DqsMapCpu2DramMc0Ch2[2];
+
+/** Offset 0x0122 - Dqs Map CPU to DRAM MC 0 CH 3
+  Set Dqs mapping relationship between CPU and DRAM, Channel 3: board-dependent
+**/
+  UINT8                       DqsMapCpu2DramMc0Ch3[2];
+
+/** Offset 0x0124 - Dqs Map CPU to DRAM MC 1 CH 0
+  Set Dqs mapping relationship between CPU and DRAM, Channel 0: board-dependent
+**/
+  UINT8                       DqsMapCpu2DramMc1Ch0[2];
+
+/** Offset 0x0126 - Dqs Map CPU to DRAM MC 1 CH 1
+  Set Dqs mapping relationship between CPU and DRAM, Channel 1: board-dependent
+**/
+  UINT8                       DqsMapCpu2DramMc1Ch1[2];
+
+/** Offset 0x0128 - Dqs Map CPU to DRAM MC 1 CH 2
+  Set Dqs mapping relationship between CPU and DRAM, Channel 2: board-dependent
+**/
+  UINT8                       DqsMapCpu2DramMc1Ch2[2];
+
+/** Offset 0x012A - Dqs Map CPU to DRAM MC 1 CH 3
+  Set Dqs mapping relationship between CPU and DRAM, Channel 3: board-dependent
+**/
+  UINT8                       DqsMapCpu2DramMc1Ch3[2];
+
+/** Offset 0x012C - Dq Map CPU to DRAM MC 0 CH 0
+  Set Dq mapping relationship between CPU and DRAM, Channel 0: board-dependent
+**/
+  UINT8                       DqMapCpu2DramMc0Ch0[16];
+
+/** Offset 0x013C - Dq Map CPU to DRAM MC 0 CH 1
+  Set Dq mapping relationship between CPU and DRAM, Channel 1: board-dependent
+**/
+  UINT8                       DqMapCpu2DramMc0Ch1[16];
+
+/** Offset 0x014C - Dq Map CPU to DRAM MC 0 CH 2
+  Set Dq mapping relationship between CPU and DRAM, Channel 2: board-dependent
+**/
+  UINT8                       DqMapCpu2DramMc0Ch2[16];
+
+/** Offset 0x015C - Dq Map CPU to DRAM MC 0 CH 3
+  Set Dq mapping relationship between CPU and DRAM, Channel 3: board-dependent
+**/
+  UINT8                       DqMapCpu2DramMc0Ch3[16];
+
+/** Offset 0x016C - Dq Map CPU to DRAM MC 1 CH 0
+  Set Dq mapping relationship between CPU and DRAM, Channel 0: board-dependent
+**/
+  UINT8                       DqMapCpu2DramMc1Ch0[16];
+
+/** Offset 0x017C - Dq Map CPU to DRAM MC 1 CH 1
+  Set Dq mapping relationship between CPU and DRAM, Channel 1: board-dependent
+**/
+  UINT8                       DqMapCpu2DramMc1Ch1[16];
+
+/** Offset 0x018C - Dq Map CPU to DRAM MC 1 CH 2
+  Set Dq mapping relationship between CPU and DRAM, Channel 2: board-dependent
+**/
+  UINT8                       DqMapCpu2DramMc1Ch2[16];
+
+/** Offset 0x019C - Dq Map CPU to DRAM MC 1 CH 3
+  Set Dq mapping relationship between CPU and DRAM, Channel 3: board-dependent
+**/
+  UINT8                       DqMapCpu2DramMc1Ch3[16];
+
+/** Offset 0x01AC - LowerBasicMemTestSize
   Reduce BasicMemTest size. 0: Disabled (default), regular BasicMemTest. 1: Enabled,
   shorter BasicMemTest (faster boot)
   $EN_DIS
 **/
   UINT8                       LowerBasicMemTestSize;
 
-/** Offset 0x011D - Reserved
+/** Offset 0x01AD - Reserved
 **/
   UINT8                       Reserved5[2];
 
-/** Offset 0x011F - CaVrefHigh feature
-  Reduce BasicMemTest size. 0: Disabled (default), regular BasicMemTest. 1: Enabled,
-  shorter BasicMemTest (faster boot)
-  $EN_DIS
+/** Offset 0x01AF - CaVrefHigh
+  DDR5 CA Sweep High Vref Value for DDR5 OC
 **/
   UINT8                       CaVrefHigh;
 
-/** Offset 0x0120 - CsVrefLow feature
-  Reduce BasicMemTest size. 0: Disabled (default), regular BasicMemTest. 1: Enabled,
-  shorter BasicMemTest (faster boot)
-  $EN_DIS
-**/
-  UINT8                       CsVrefLow;
-
-/** Offset 0x0121 - CsVrefHigh feature
-  Reduce BasicMemTest size. 0: Disabled (default), regular BasicMemTest. 1: Enabled,
-  shorter BasicMemTest (faster boot)
-  $EN_DIS
-**/
-  UINT8                       CsVrefHigh;
-
-/** Offset 0x0122 - CaVrefLow feature
-  Reduce BasicMemTest size. 0: Disabled (default), regular BasicMemTest. 1: Enabled,
-  shorter BasicMemTest (faster boot)
-  $EN_DIS
+/** Offset 0x01B0 - CaVrefLow
+  DDR5 CA Sweep Low Vref Value for DDR5 OC
 **/
   UINT8                       CaVrefLow;
 
-/** Offset 0x0123 - DFETap2StepSize feature
-  Reduce BasicMemTest size. 0: Disabled (default), regular BasicMemTest. 1: Enabled,
-  shorter BasicMemTest (faster boot)
-  $EN_DIS
+/** Offset 0x01B1 - CsVrefHigh
+  DDR5 CS Sweep High Vref Value for DDR5 OC
 **/
-  UINT8                       DFETap2StepSize;
+  UINT8                       CsVrefHigh;
 
-/** Offset 0x0124 - Vdd2Mv feature
-  Reduce BasicMemTest size. 0: Disabled (default), regular BasicMemTest. 1: Enabled,
-  shorter BasicMemTest (faster boot)
-  $EN_DIS
+/** Offset 0x01B2 - CsVrefLow
+  DDR5 CS Sweep Low Vref Value for DDR5 OC
 **/
-  UINT16                      Vdd2Mv;
+  UINT8                       CsVrefLow;
 
-/** Offset 0x0126 - Vdd2Mv feature
-  Reduce BasicMemTest size. 0: Disabled (default), regular BasicMemTest. 1: Enabled,
-  shorter BasicMemTest (faster boot)
-  $EN_DIS
-**/
-  UINT16                      tWTR_S;
-
-/** Offset 0x0128 - Vdd2Mv feature
-  Reduce BasicMemTest size. 0: Disabled (default), regular BasicMemTest. 1: Enabled,
-  shorter BasicMemTest (faster boot)
-  $EN_DIS
-**/
-  UINT16                      tCCD_L;
-
-/** Offset 0x012A - Vdd2Mv feature
-  Reduce BasicMemTest size. 0: Disabled (default), regular BasicMemTest. 1: Enabled,
-  shorter BasicMemTest (faster boot)
-  $EN_DIS
-**/
-  UINT16                      tWTR_L;
-
-/** Offset 0x012C - Vdd2Mv feature
-  Reduce BasicMemTest size. 0: Disabled (default), regular BasicMemTest. 1: Enabled,
-  shorter BasicMemTest (faster boot)
-  $EN_DIS
-**/
-  UINT16                      tRRD_S;
-
-/** Offset 0x012E - Vdd2Mv feature
-  Reduce BasicMemTest size. 0: Disabled (default), regular BasicMemTest. 1: Enabled,
-  shorter BasicMemTest (faster boot)
-  $EN_DIS
-**/
-  UINT16                      tRRD_L;
-
-/** Offset 0x0130 - Vdd2Mv feature
-  Reduce BasicMemTest size. 0: Disabled (default), regular BasicMemTest. 1: Enabled,
-  shorter BasicMemTest (faster boot)
-  $EN_DIS
-**/
-  UINT16                      tRFC4;
-
-/** Offset 0x0132 - Vdd2Mv feature
-  Reduce BasicMemTest size. 0: Disabled (default), regular BasicMemTest. 1: Enabled,
-  shorter BasicMemTest (faster boot)
-  $EN_DIS
-**/
-  UINT16                      tRFC2;
-
-/** Offset 0x0134 - Vdd2Mv feature
-  Reduce BasicMemTest size. 0: Disabled (default), regular BasicMemTest. 1: Enabled,
-  shorter BasicMemTest (faster boot)
-  $EN_DIS
-**/
-  UINT16                      tRFCpb;
-
-/** Offset 0x0136 - Reserved
-**/
-  UINT8                       Reserved6[7];
-
-/** Offset 0x013D - Vdd2Mv feature
-  Reduce BasicMemTest size. 0: Disabled (default), regular BasicMemTest. 1: Enabled,
-  shorter BasicMemTest (faster boot)
-  $EN_DIS
-**/
-  UINT8                       LpMode;
-
-/** Offset 0x013E - LowerBasicMemTestSize feature
-  Reduce BasicMemTest size. 0: Disabled (default), regular BasicMemTest. 1: Enabled,
-  shorter BasicMemTest (faster boot)
-  $EN_DIS
+/** Offset 0x01B3 - DIMM DFE Tap1 Step Size
+  DIMM DFE Tap1 Step Size for DDR5 OC
 **/
   UINT8                       DFETap1StepSize;
 
-/** Offset 0x013F - Dqs Map CPU to DRAM MC 0 CH 0
-  Set Dqs mapping relationship between CPU and DRAM, Channel 0: board-dependent
+/** Offset 0x01B4 - DIMM DFE Tap2 Step Size
+  DIMM DFE Tap2 Step Size for DDR5 OC
 **/
-  UINT8                       DqsMapCpu2DramMc0Ch0[2];
+  UINT8                       DFETap2StepSize;
 
-/** Offset 0x0141 - Dqs Map CPU to DRAM MC 0 CH 1
-  Set Dqs mapping relationship between CPU and DRAM, Channel 1: board-dependent
+/** Offset 0x01B5 - Reserved
 **/
-  UINT8                       DqsMapCpu2DramMc0Ch1[2];
+  UINT8                       Reserved6;
 
-/** Offset 0x0143 - Dqs Map CPU to DRAM MC 0 CH 2
-  Set Dqs mapping relationship between CPU and DRAM, Channel 2: board-dependent
+/** Offset 0x01B6 - VDD2 override
+  VDD2 override for DDR5 OC; 0 - Auto
 **/
-  UINT8                       DqsMapCpu2DramMc0Ch2[2];
+  UINT16                      Vdd2Mv;
 
-/** Offset 0x0145 - Dqs Map CPU to DRAM MC 0 CH 3
-  Set Dqs mapping relationship between CPU and DRAM, Channel 3: board-dependent
-**/
-  UINT8                       DqsMapCpu2DramMc0Ch3[2];
-
-/** Offset 0x0147 - Dqs Map CPU to DRAM MC 1 CH 0
-  Set Dqs mapping relationship between CPU and DRAM, Channel 0: board-dependent
-**/
-  UINT8                       DqsMapCpu2DramMc1Ch0[2];
-
-/** Offset 0x0149 - Dqs Map CPU to DRAM MC 1 CH 1
-  Set Dqs mapping relationship between CPU and DRAM, Channel 1: board-dependent
-**/
-  UINT8                       DqsMapCpu2DramMc1Ch1[2];
-
-/** Offset 0x014B - Dqs Map CPU to DRAM MC 1 CH 2
-  Set Dqs mapping relationship between CPU and DRAM, Channel 2: board-dependent
-**/
-  UINT8                       DqsMapCpu2DramMc1Ch2[2];
-
-/** Offset 0x014D - Dqs Map CPU to DRAM MC 1 CH 3
-  Set Dqs mapping relationship between CPU and DRAM, Channel 3: board-dependent
-**/
-  UINT8                       DqsMapCpu2DramMc1Ch3[2];
-
-/** Offset 0x014F - Dq Map CPU to DRAM MC 0 CH 0
-  Set Dq mapping relationship between CPU and DRAM, Channel 0: board-dependent
-**/
-  UINT8                       DqMapCpu2DramMc0Ch0[16];
-
-/** Offset 0x015F - Dq Map CPU to DRAM MC 0 CH 1
-  Set Dq mapping relationship between CPU and DRAM, Channel 1: board-dependent
-**/
-  UINT8                       DqMapCpu2DramMc0Ch1[16];
-
-/** Offset 0x016F - Dq Map CPU to DRAM MC 0 CH 2
-  Set Dq mapping relationship between CPU and DRAM, Channel 2: board-dependent
-**/
-  UINT8                       DqMapCpu2DramMc0Ch2[16];
-
-/** Offset 0x017F - Dq Map CPU to DRAM MC 0 CH 3
-  Set Dq mapping relationship between CPU and DRAM, Channel 3: board-dependent
-**/
-  UINT8                       DqMapCpu2DramMc0Ch3[16];
-
-/** Offset 0x018F - Dq Map CPU to DRAM MC 1 CH 0
-  Set Dq mapping relationship between CPU and DRAM, Channel 0: board-dependent
-**/
-  UINT8                       DqMapCpu2DramMc1Ch0[16];
-
-/** Offset 0x019F - Dq Map CPU to DRAM MC 1 CH 1
-  Set Dq mapping relationship between CPU and DRAM, Channel 1: board-dependent
-**/
-  UINT8                       DqMapCpu2DramMc1Ch1[16];
-
-/** Offset 0x01AF - Dq Map CPU to DRAM MC 1 CH 2
-  Set Dq mapping relationship between CPU and DRAM, Channel 2: board-dependent
-**/
-  UINT8                       DqMapCpu2DramMc1Ch2[16];
-
-/** Offset 0x01BF - Dq Map CPU to DRAM MC 1 CH 3
-  Set Dq mapping relationship between CPU and DRAM, Channel 3: board-dependent
-**/
-  UINT8                       DqMapCpu2DramMc1Ch3[16];
-
-/** Offset 0x01CF - Reserved
-**/
-  UINT8                       Reserved7[2];
-
-/** Offset 0x01D1 - MRC OCSafeMode
-  OverClocking Safe Mode
-  0:CMOS, 1:Break, 2:Force
-**/
-  UINT8                       OCSafeMode;
-
-/** Offset 0x01D2 - Reserved
-**/
-  UINT8                       Reserved8;
-
-/** Offset 0x01D3 - Dqs Pins Interleaved Setting
-  Indicates DqPinsInterleaved setting: board-dependent
-  $EN_DIS
-**/
-  UINT8                       DqPinsInterleaved;
-
-/** Offset 0x01D4 - Reserved
-**/
-  UINT8                       Reserved9[2];
-
-/** Offset 0x01D6 - MRC Fast Boot
-  Enables/Disable the MRC fast path thru the MRC
-  $EN_DIS
-**/
-  UINT16                      MrcFastBoot;
-
-/** Offset 0x01D8 - Rank Margin Tool per Task
-  This option enables the user to execute Rank Margin Tool per major training step
-  in the MRC.
-  $EN_DIS
-**/
-  UINT8                       RmtPerTask;
-
-/** Offset 0x01D9 - Training Trace
-  This option enables the trained state tracing feature in MRC.  This feature will
-  print out the key training parameters state across major training steps.
-  $EN_DIS
-**/
-  UINT8                       TrainTrace;
-
-/** Offset 0x01DA - Probeless Trace
-  Probeless Trace: 0=Disabled, 1=Enable. Enabling Probeless Trace will reserve 128MB.
-  This also requires IED to be enabled.
-  $EN_DIS
-**/
-  UINT8                       ProbelessTrace;
-
-/** Offset 0x01DB - Reserved
-**/
-  UINT8                       Reserved10;
-
-/** Offset 0x01DC - DDR Frequency Limit
-  Maximum Memory Frequency Selections in Mhz. Options are 1067, 1333, 1600, 1867,
-  2133, 2400, 2667, 2933 and 0 for Auto.
-  1067:1067, 1333:1333, 1600:1600, 1867:1867, 2133:2133, 2400:2400, 2667:2667, 2933:2933, 0:Auto
-**/
-  UINT16                      DdrFreqLimit;
-
-/** Offset 0x01DE - SAGV
-  System Agent dynamic frequency support.
-  0:Disabled, 1:Enabled
-**/
-  UINT8                       SaGv;
-
-/** Offset 0x01DF - SAGV WP Mask
-  System Agent dynamic frequency workpoints that memory will be training at the enabled
-  frequencies.
-  0x3:Points0_1, 0x7:Points0_1_2, 0xF:AllPoints0_1_2_3
-**/
-  UINT8                       SaGvWpMask;
-
-/** Offset 0x01E0 - SAGV Gear Ratio
-  Gear Selection for SAGV points. 0 - Auto, 1-1 Gear 1, 2-Gear 2
-**/
-  UINT8                       SaGvGear[4];
-
-/** Offset 0x01E4 - SAGV Frequency
-  SAGV Frequency per point in Mhz. 0 for Auto and a ratio of 133/100MHz: 1333/1300.
-**/
-  UINT16                      SaGvFreq[4];
-
-/** Offset 0x01EC - SAGV Disabled Gear Ratio
-  Gear Selection for SAGV Disabled. 0 - Auto, 1-1 Gear 1, 2-Gear 2
-**/
-  UINT8                       GearRatio;
-
-/** Offset 0x01ED - Rank Margin Tool
-  Enable/disable Rank Margin Tool.
-  $EN_DIS
-**/
-  UINT8                       RMT;
-
-/** Offset 0x01EE - Controller 0 Channel 0 DIMM Control
-  Enable / Disable DIMMs on Controller 0 Channel 0
-  $EN_DIS
-**/
-  UINT8                       DisableMc0Ch0;
-
-/** Offset 0x01EF - Controller 0 Channel 1 DIMM Control
-  Enable / Disable DIMMs on Controller 0 Channel 1
-  $EN_DIS
-**/
-  UINT8                       DisableMc0Ch1;
-
-/** Offset 0x01F0 - Controller 0 Channel 2 DIMM Control
-  Enable / Disable DIMMs on Controller 0 Channel 2
-  $EN_DIS
-**/
-  UINT8                       DisableMc0Ch2;
-
-/** Offset 0x01F1 - Controller 0 Channel 3 DIMM Control
-  Enable / Disable DIMMs on Controller 0 Channel 3
-  $EN_DIS
-**/
-  UINT8                       DisableMc0Ch3;
-
-/** Offset 0x01F2 - Controller 1 Channel 0 DIMM Control
-  Enable / Disable DIMMs on Controller 1 Channel 0
-  $EN_DIS
-**/
-  UINT8                       DisableMc1Ch0;
-
-/** Offset 0x01F3 - Controller 1 Channel 1 DIMM Control
-  Enable / Disable DIMMs on Controller 1 Channel 1
-  $EN_DIS
-**/
-  UINT8                       DisableMc1Ch1;
-
-/** Offset 0x01F4 - Controller 1 Channel 2 DIMM Control
-  Enable / Disable DIMMs on Controller 1 Channel 2
-  $EN_DIS
-**/
-  UINT8                       DisableMc1Ch2;
-
-/** Offset 0x01F5 - Controller 1 Channel 3 DIMM Control
-  Enable / Disable DIMMs on Controller 1 Channel 3
-  $EN_DIS
-**/
-  UINT8                       DisableMc1Ch3;
-
-/** Offset 0x01F6 - Scrambler Support
-  This option enables data scrambling in memory.
-  $EN_DIS
-**/
-  UINT8                       ScramblerSupport;
-
-/** Offset 0x01F7 - Reserved
-**/
-  UINT8                       Reserved11[3];
-
-/** Offset 0x01FA - Memory Ratio
-  Automatic or the frequency will equal ratio times reference clock. Set to Auto to
-  recalculate memory timings listed below.
-  0:Auto, 4:4, 5:5, 6:6, 7:7, 8:8, 9:9, 10:10, 11:11, 12:12, 13:13, 14:14, 15:15
-**/
-  UINT16                      Ratio;
-
-/** Offset 0x01FC - tCL
-  CAS Latency, 0: AUTO, max: 255. Only used if FspmUpd->FspmConfig.SpdProfileSelected
-  == 1 (Custom Profile).
-**/
-  UINT16                      tCL;
-
-/** Offset 0x01FE - tCWL
-  Min CAS Write Latency Delay Time, 0: AUTO, max: 255. Only used if FspmUpd->FspmConfig.SpdProfileSelected
-  == 1 (Custom Profile).
-**/
-  UINT16                      tCWL;
-
-/** Offset 0x0200 - tFAW
-  Min Four Activate Window Delay Time, 0: AUTO, max: 65535. Only used if FspmUpd->FspmConfig.SpdProfileSelected
-  == 1 (Custom Profile).
-**/
-  UINT16                      tFAW;
-
-/** Offset 0x0202 - SPD Profile Selected
-  Select DIMM timing profile. Options are 0=Default Profile, 1=Custom Profile, 2=XMP
-  Profile 1, 3=XMP Profile 2
-  0:Default Profile, 1:Custom Profile, 2:XMP Profile 1, 3:XMP Profile 2
-**/
-  UINT8                       SpdProfileSelected;
-
-/** Offset 0x0203
-**/
-  UINT8                       RXVREFPERBIT;
-
-/** Offset 0x0204 - Reserved
-**/
-  UINT8                       Reserved12;
-
-/** Offset 0x0205 - Ch Hash Override
-  Select if Channel Hash setting values will be taken from input parameters or automatically
-  taken from POR values depending on DRAM type detected. NOTE: ONLY if Memory interleaved Mode
-  $EN_DIS
-**/
-  UINT8                       ChHashOverride;
-
-/** Offset 0x0206 - Reserved
-**/
-  UINT8                       Reserved13[2];
-
-/** Offset 0x0208 - DQS Rise/Fall
-  Enables/Disable DQS Rise/Fall
-  $EN_DIS
-**/
-  UINT8                       RDDQSODTT;
-
-/** Offset 0x0209 - Reserved
-**/
-  UINT8                       Reserved14[2];
-
-/** Offset 0x020B - Functional Duty Cycle Correction for DDR5 CLK
-  Enable/Disable Functional Duty Cycle Correction for DDR5 CLK
-  0:Disable, 1:Enable
-**/
-  UINT8                       FUNCDCCCLK;
-
-/** Offset 0x020C - Functional Duty Cycle Correction for DDR5 DQS
-  Enable/Disable Functional Duty Cycle Correction for DDR5 DQS
-  0:Disable, 1:Enable
-**/
-  UINT8                       FUNCDCCDQS;
-
-/** Offset 0x020D
-**/
-  UINT8                       FUNCDCCWCK;
-
-/** Offset 0x020E - Duty Cycle Correction for LP5 DCA
-  Enable/Disable Duty Cycle Correction for LP5 DCA
-  $EN_DIS
-**/
-  UINT8                       DCCLP5WCKDCA;
-
-/** Offset 0x020F - Reserved
-**/
-  UINT8                       Reserved15;
-
-/** Offset 0x0210 - DQ/DQS Swizzle Training
-  Enable/Disable DQ/DQS Swizzle Training
-  $EN_DIS
-**/
-  UINT32                      DQDQSSWZ;
-
-/** Offset 0x0214 - Reserved
-**/
-  UINT8                      Reserved16[4];
-
-/** Offset 0x0218 - Functional Duty Cycle Correction for Data DQ
-  Enable/Disable Functional Duty Cycle Correction for Data DQ
-  0:Disable, 1:Enable
-**/
-  UINT8                       FUNCDCCDQ;
-
-/** Offset 0x0219 - Reserved
-**/
-  UINT8                       Reserved17[5];
-
-/** Offset 0x021E - tRAS
+/** Offset 0x01B8 - tRAS
   RAS Active Time, 0: AUTO, max: 65535. Only used if FspmUpd->FspmConfig.SpdProfileSelected
   == 1 (Custom Profile).
 **/
   UINT16                      tRAS;
 
-/** Offset 0x0220 - tRCD/tRP
+/** Offset 0x01BA - tRCD/tRP
   RAS to CAS delay time and Row Precharge delay time, 0: AUTO, max: 255. Only used
   if FspmUpd->FspmConfig.SpdProfileSelected == 1 (Custom Profile).
 **/
   UINT16                      tRCDtRP;
 
-/** Offset 0x0222 - Reserved
-**/
-  UINT8                       Reserved18[2];
-
-/** Offset 0x0224 - tREFI
+/** Offset 0x01BC - tREFI
   Refresh Interval, 0: AUTO, max: 65535. Only used if FspmUpd->FspmConfig.SpdProfileSelected
   == 1 (Custom Profile).
 **/
   UINT32                      tREFI;
 
-/** Offset 0x0228 - Unmatched Rx Calibration
-  Enable/Disable Rx Unmatched Calibration
-  $EN_DIS
+/** Offset 0x01C0 - tCL
+  CAS Latency, 0: AUTO, max: 255. Only used if FspmUpd->FspmConfig.SpdProfileSelected
+  == 1 (Custom Profile).
 **/
-  UINT32                      RXUNMATCHEDCAL;
+  UINT16                      tCL;
 
-/** Offset 0x022C - Hard Post Package Repair
-  Enables/Disable Hard Post Package Repair
-  $EN_DIS
+/** Offset 0x01C2 - tCWL
+  Min CAS Write Latency Delay Time, 0: AUTO, max: 255. Only used if FspmUpd->FspmConfig.SpdProfileSelected
+  == 1 (Custom Profile).
 **/
-  UINT32                      PPR;
+  UINT16                      tCWL;
 
-/** Offset 0x0230 - Reserved
+/** Offset 0x01C4 - tFAW
+  Min Four Activate Window Delay Time, 0: AUTO, max: 65535. Only used if FspmUpd->FspmConfig.SpdProfileSelected
+  == 1 (Custom Profile).
 **/
-  UINT8                       Reserved19;
+  UINT16                      tFAW;
 
-/** Offset 0x0231 - PPR Run Once
-  When Eanble, PPR will run only once and then is disabled at next training cycle
-  $EN_DIS
-**/
-  UINT8                       PprRunOnce;
-
-/** Offset 0x0232 - PPR Run During Fastboot
-  When Eanble, PPR will run during fastboot
-  $EN_DIS
-**/
-  UINT8                       PprRunAtFastboot;
-
-/** Offset 0x0233 - PPR Repair Type
-  PPR Repair Type: 0:Do not Repair (Default), 1:Soft Repair, 2:Hard Repair
-  0:Do not Repair (Default), 1:Soft Repair, 2:Hard Repair
-**/
-  UINT8                       PprRepairType;
-
-/** Offset 0x0234 - PPR Error Injection
-  When Eanble, PPR will inject bad rows during testing
-  $EN_DIS
-**/
-  UINT8                       PprErrorInjection;
-
-/** Offset 0x0235 - PPR Repair Controller
-  PPR repair controller: User chooses to force repair specifc address
-**/
-  UINT8                       PprRepairController;
-
-/** Offset 0x0236 - PPR Repair Channel
-  PPR repair Channel: User chooses to force repair specifc address
-**/
-  UINT8                       PprRepairChannel;
-
-/** Offset 0x0237 - PPR Repair Dimm
-  PPR repair Dimm: User chooses to force repair specifc address
-**/
-  UINT8                       PprRepairDimm;
-
-/** Offset 0x0238 - PPR Repair Rank
-  PPR repair Rank: User chooses to force repair specifc address
-**/
-  UINT8                       PprRepairRank;
-
-/** Offset 0x0239 - Reserved
-**/
-  UINT8                       Reserved20[3];
-
-/** Offset 0x023C - PPR Repair Row
-  PPR repair Row: User chooses to force repair specifc address
-**/
-  UINT32                      PprRepairRow;
-
-/** Offset 0x0240 - Reserved
-**/
-  UINT8                      Reserved21[8];
-
-/** Offset 0x0248 - PPR Repair BankGroup
-  PPR repair BankGroup: User chooses to force repair specifc address
-**/
-  UINT8                       PprRepairBankGroup;
-
-/** Offset 0x0249 - Reserved
-**/
-  UINT8                       Reserved22;
-
-/** Offset 0x024A - tCCD_L_WR
-  Number of tCK cycles for the channel DIMM's minimum Write-to-Write delay for same
-  bank groups
-**/
-  UINT16                      tCCD_L_WR;
-
-/** Offset 0x024C - LVR Auto Trim
-  Enable/disable LVR Auto Trim
-  $EN_DIS
-**/
-  UINT32                      LVRAUTOTRIM;
-
-/** Offset 0x0250 - Power Saving Meter Update
-  Enable/Disable Power Saving Meter Update
-  $EN_DIS
-**/
-  UINT32                      PWRMETER;
-
-/** Offset 0x0254 - Compensation Optimization
-  Enable/Disable Compensation Optimization
-  $EN_DIS
-**/
-  UINT32                      OPTIMIZECOMP;
-
-/** Offset 0x0258 - Write DQ/DQS Retraining
-  Enable/Disable Write DQ/DQS Retraining
-  $EN_DIS
-**/
-  UINT32                      WRTRETRAIN;
-
-/** Offset 0x025C - Pre-Training Comp Calibration
-  Enable/Disable Pre-Training Comp Calibration
-  $EN_DIS
-**/
-  UINT32                      DDRPRECOMP;
-
-/** Offset 0x0260 - Reserved
-**/
-  UINT8                      Reserved23[12];
-
-/** Offset 0x026C - RDDQODTT
-  Enable/disable Read DQ ODT Training
-  $EN_DIS
-**/
-  UINT32                      RDDQODTT;
-
-/** Offset 0x0270 - RDCTLET
-  Enable/disable Read CTLE Training
-  $EN_DIS
-**/
-  UINT32                      RDCTLET;
-
-/** Offset 0x0274 - RxVref Pre EMPHASIS Training
-  Enable/Disable Pre EMPHASIS Training
-  $EN_DIS
-**/
-  UINT8                       EMPHASIS;
-
-/** Offset 0x0275 - Reserved
-**/
-  UINT8                       Reserved24;
-
-/** Offset 0x0276 - tRFC
+/** Offset 0x01C6 - tRFC
   Min Refresh Recovery Delay Time, 0: AUTO, max: 65535. Only used if FspmUpd->FspmConfig.SpdProfileSelected
   == 1 (Custom Profile).
 **/
   UINT16                      tRFC;
 
-/** Offset 0x0278 - tRRD
+/** Offset 0x01C8 - tRRD
   Min Row Active to Row Active Delay Time, 0: AUTO, max: 255. Only used if FspmUpd->FspmConfig.SpdProfileSelected
   == 1 (Custom Profile).
 **/
   UINT16                      tRRD;
 
-/** Offset 0x027A - tRTP
+/** Offset 0x01CA - tRTP
   Min Internal Read to Precharge Command Delay Time, 0: AUTO, max: 255. Only used
   if FspmUpd->FspmConfig.SpdProfileSelected == 1 (Custom Profile).
 **/
   UINT16                      tRTP;
 
-/** Offset 0x027C - tWR
+/** Offset 0x01CC - tWR
   Min Write Recovery Time, 0: AUTO, legal values: 5, 6, 7, 8, 10, 12, 14, 16, 18,
   20, 24, 30, 34, 40. Only used if FspmUpd->FspmConfig.SpdProfileSelected == 1 (Custom Profile).
   0:Auto, 5:5, 6:6, 7:7, 8:8, 10:10, 12:12, 14:14, 16:16, 18:18, 20:20, 24:24, 30:30,
@@ -890,522 +422,943 @@ typedef struct {
 **/
   UINT16                      tWR;
 
-/** Offset 0x027E - tWTR
+/** Offset 0x01CE - tWTR
   Min Internal Write to Read Command Delay Time, 0: AUTO, max: 255. Only used if FspmUpd->FspmConfig.SpdProfileSelected
   == 1 (Custom Profile).
 **/
   UINT16                      tWTR;
 
-/** Offset 0x0280 - NMode
+/** Offset 0x01D0 - tWTR_S
+  tWTR_S value for OC Custom Profile, 0 - Auto
+**/
+  UINT16                      tWTR_S;
+
+/** Offset 0x01D2 - tWTR_L
+  tWTR_L value for OC Custom Profile, 0 - Auto
+**/
+  UINT16                      tWTR_L;
+
+/** Offset 0x01D4 - tCCD_L
+  tCCD_L value for OC Custom Profile, 0 - Auto
+**/
+  UINT16                      tCCD_L;
+
+/** Offset 0x01D6 - tRRD_S
+  tRRD_S value for OC Custom Profile, 0 - Auto
+**/
+  UINT16                      tRRD_S;
+
+/** Offset 0x01D8 - tRRD_L
+  tRRD_L value for OC Custom Profile, 0 - Auto
+**/
+  UINT16                      tRRD_L;
+
+/** Offset 0x01DA - tRFC4
+  tRFC4 value for OC Custom Profile, 0 - Auto
+**/
+  UINT16                      tRFC4;
+
+/** Offset 0x01DC - tRFC2
+  tRFC2 value for OC Custom Profile, 0 - Auto
+**/
+  UINT16                      tRFC2;
+
+/** Offset 0x01DE - tRFCpb
+  tRFCpb value for OC Custom Profile, 0 - Auto
+**/
+  UINT16                      tRFCpb;
+
+/** Offset 0x01E0 - tCCD_L_WR
+  Number of tCK cycles for the channel DIMM's minimum Write-to-Write delay for same
+  bank groups, for OC Custom Profile, 0 - Auto
+**/
+  UINT16                      tCCD_L_WR;
+
+/** Offset 0x01E2 - Reserved
+**/
+  UINT8                       Reserved7[2];
+
+/** Offset 0x01E4 - LPMode Support
+  Bit[0]: Enable Lpmode0p5 (Idle_enable), Bit[1]: Enable Lpmode2 (Powerdown_enable),
+  Bit[2]: Enable Lpmode3 (Selfrefresh_enable)
+**/
+  UINT8                       LpMode;
+
+/** Offset 0x01E5 - Reserved
+**/
+  UINT8                       Reserved8[2];
+
+/** Offset 0x01E7 - MRC OCSafeMode
+  OverClocking Safe Mode for tCL
+  $EN_DIS
+**/
+  UINT8                       OCSafeMode;
+
+/** Offset 0x01E8 - Reserved
+**/
+  UINT8                       Reserved9;
+
+/** Offset 0x01E9 - Dqs Pins Interleaved Setting
+  Indicates DqPinsInterleaved setting: board-dependent
+  $EN_DIS
+**/
+  UINT8                       DqPinsInterleaved;
+
+/** Offset 0x01EA - Smram Mask
+  The SMM Regions AB-SEG and/or H-SEG reserved
+  0: Neither, 1:AB-SEG, 2:H-SEG, 3: Both
+**/
+  UINT8                       SmramMask;
+
+/** Offset 0x01EB - MRC Fast Boot
+  Enables/Disable the MRC fast path thru the MRC
+  $EN_DIS
+**/
+  UINT8                       MrcFastBoot;
+
+/** Offset 0x01EC - Rank Margin Tool per Task
+  This option enables the user to execute Rank Margin Tool per major training step
+  in the MRC.
+  $EN_DIS
+**/
+  UINT8                       RmtPerTask;
+
+/** Offset 0x01ED - Training Trace
+  This option enables the trained state tracing feature in MRC.  This feature will
+  print out the key training parameters state across major training steps.
+  $EN_DIS
+**/
+  UINT8                       TrainTrace;
+
+/** Offset 0x01EE - Probeless Trace
+  Probeless Trace: 0=Disabled, 1=Enable. Enabling Probeless Trace will reserve 128MB.
+  This also requires IED to be enabled.
+  $EN_DIS
+**/
+  UINT8                       ProbelessTrace;
+
+/** Offset 0x01EF - Reserved
+**/
+  UINT8                       Reserved10;
+
+/** Offset 0x01F0 - DDR Frequency Limit
+  Maximum Memory Frequency Selections in Mhz. Options are 1067, 1333, 1600, 1867,
+  2133, 2400, 2667, 2933 and 0 for Auto.
+  1067:1067, 1333:1333, 1600:1600, 1867:1867, 2133:2133, 2400:2400, 2667:2667, 2933:2933, 0:Auto
+**/
+  UINT16                      DdrFreqLimit;
+
+/** Offset 0x01F2 - SAGV
+  System Agent dynamic frequency support.
+  0:Disabled, 1:Enabled
+**/
+  UINT8                       SaGv;
+
+/** Offset 0x01F3 - SAGV WP Mask
+  System Agent dynamic frequency workpoints that memory will be training at the enabled
+  frequencies.
+  0x3:Points0_1, 0x7:Points0_1_2, 0xF:AllPoints0_1_2_3
+**/
+  UINT8                       SaGvWpMask;
+
+/** Offset 0x01F4 - SAGV Gear Ratio
+  Gear Selection for SAGV points. 0 - Auto, 1-1 Gear 1, 2-Gear 2
+**/
+  UINT8                       SaGvGear[4];
+
+/** Offset 0x01F8 - SAGV Frequency
+  SAGV Frequency per point in Mhz. 0 for Auto and a ratio of 133/100MHz: 1333/1300.
+**/
+  UINT16                      SaGvFreq[4];
+
+/** Offset 0x0200 - SAGV Disabled Gear Ratio
+  Gear Selection for SAGV Disabled. 0 - Auto, 1-1 Gear 1, 2-Gear 2
+**/
+  UINT8                       GearRatio;
+
+/** Offset 0x0201 - Rank Margin Tool
+  Enable/disable Rank Margin Tool.
+  $EN_DIS
+**/
+  UINT8                       RMT;
+
+/** Offset 0x0202 - Controller 0 Channel 0 DIMM Control
+  Enable / Disable DIMMs on Controller 0 Channel 0
+  $EN_DIS
+**/
+  UINT8                       DisableMc0Ch0;
+
+/** Offset 0x0203 - Controller 0 Channel 1 DIMM Control
+  Enable / Disable DIMMs on Controller 0 Channel 1
+  $EN_DIS
+**/
+  UINT8                       DisableMc0Ch1;
+
+/** Offset 0x0204 - Controller 0 Channel 2 DIMM Control
+  Enable / Disable DIMMs on Controller 0 Channel 2
+  $EN_DIS
+**/
+  UINT8                       DisableMc0Ch2;
+
+/** Offset 0x0205 - Controller 0 Channel 3 DIMM Control
+  Enable / Disable DIMMs on Controller 0 Channel 3
+  $EN_DIS
+**/
+  UINT8                       DisableMc0Ch3;
+
+/** Offset 0x0206 - Controller 1 Channel 0 DIMM Control
+  Enable / Disable DIMMs on Controller 1 Channel 0
+  $EN_DIS
+**/
+  UINT8                       DisableMc1Ch0;
+
+/** Offset 0x0207 - Controller 1 Channel 1 DIMM Control
+  Enable / Disable DIMMs on Controller 1 Channel 1
+  $EN_DIS
+**/
+  UINT8                       DisableMc1Ch1;
+
+/** Offset 0x0208 - Controller 1 Channel 2 DIMM Control
+  Enable / Disable DIMMs on Controller 1 Channel 2
+  $EN_DIS
+**/
+  UINT8                       DisableMc1Ch2;
+
+/** Offset 0x0209 - Controller 1 Channel 3 DIMM Control
+  Enable / Disable DIMMs on Controller 1 Channel 3
+  $EN_DIS
+**/
+  UINT8                       DisableMc1Ch3;
+
+/** Offset 0x020A - Scrambler Support
+  This option enables data scrambling in memory.
+  $EN_DIS
+**/
+  UINT8                       ScramblerSupport;
+
+/** Offset 0x020B - Reserved
+**/
+  UINT8                       Reserved11;
+
+/** Offset 0x020C - Memory Voltage
+  DRAM voltage (Vdd) (supply voltage for input buffers and core logic of the DRAM
+  chips) in millivolts. <b>0=Platform Default (no override)</b>, 1200=1.2V, 1350=1.35V etc.
+  0:Default, 1200:1.20 Volts, 1250:1.25 Volts, 1300:1.30 Volts, 1350:1.35 Volts, 1400:1.40
+  Volts, 1450:1.45 Volts, 1500:1.50 Volts, 1550:1.55 Volts, 1600:1.60 Volts, 1650:1.65 Volts
+**/
+  UINT16                      VddVoltage;
+
+/** Offset 0x020E - Memory Ratio
+  Automatic or the frequency will equal ratio times reference clock. Set to Auto to
+  recalculate memory timings listed below.
+  0:Auto, 4:4, 5:5, 6:6, 7:7, 8:8, 9:9, 10:10, 11:11, 12:12, 13:13, 14:14, 15:15
+**/
+  UINT16                      Ratio;
+
+/** Offset 0x0210 - SPD Profile Selected
+  Select DIMM timing profile. Options are 0=Default Profile, 1=Custom Profile, 2=XMP
+  Profile 1, 3=XMP Profile 2
+  0:Default Profile, 1:Custom Profile, 2:XMP Profile 1, 3:XMP Profile 2
+**/
+  UINT8                       SpdProfileSelected;
+
+/** Offset 0x0211
+**/
+  UINT8                       RXVREFPERBIT;
+
+/** Offset 0x0212 - Reserved
+**/
+  UINT8                       Reserved12;
+
+/** Offset 0x0213 - Ch Hash Override
+  Select if Channel Hash setting values will be taken from input parameters or automatically
+  taken from POR values depending on DRAM type detected. NOTE: ONLY if Memory interleaved Mode
+  $EN_DIS
+**/
+  UINT8                       ChHashOverride;
+
+/** Offset 0x0214 - Reserved
+**/
+  UINT8                       Reserved13[2];
+
+/** Offset 0x0216 - DQS Rise/Fall
+  Enables/Disable DQS Rise/Fall
+  $EN_DIS
+**/
+  UINT8                       RDDQSODTT;
+
+/** Offset 0x0217 - Reserved
+**/
+  UINT8                       Reserved14[2];
+
+/** Offset 0x0219 - Functional Duty Cycle Correction for DDR5 CLK
+  Enable/Disable Functional Duty Cycle Correction for DDR5 CLK
+  0:Disable, 1:Enable
+**/
+  UINT8                       FUNCDCCCLK;
+
+/** Offset 0x021A - Functional Duty Cycle Correction for DDR5 DQS
+  Enable/Disable Functional Duty Cycle Correction for DDR5 DQS
+  0:Disable, 1:Enable
+**/
+  UINT8                       FUNCDCCDQS;
+
+/** Offset 0x021B
+**/
+  UINT8                       FUNCDCCWCK;
+
+/** Offset 0x021C - Duty Cycle Correction for LP5 DCA
+  Enable/Disable Duty Cycle Correction for LP5 DCA
+  $EN_DIS
+**/
+  UINT8                       DCCLP5WCKDCA;
+
+/** Offset 0x021D - DQ/DQS Swizzle Training
+  Enable/Disable DQ/DQS Swizzle Training
+  $EN_DIS
+**/
+  UINT8                       DQDQSSWZ;
+
+/** Offset 0x021E - Reserved
+**/
+  UINT8                       Reserved15;
+
+/** Offset 0x021F - Functional Duty Cycle Correction for Data DQ
+  Enable/Disable Functional Duty Cycle Correction for Data DQ
+  0:Disable, 1:Enable
+**/
+  UINT8                       FUNCDCCDQ;
+
+/** Offset 0x0220 - Reserved
+**/
+  UINT8                       Reserved16[5];
+
+/** Offset 0x0225 - Unmatched Rx Calibration
+  Enable/Disable Rx Unmatched Calibration
+  $EN_DIS
+**/
+  UINT8                       RXUNMATCHEDCAL;
+
+/** Offset 0x0226 - Hard Post Package Repair
+  Enables/Disable Hard Post Package Repair
+  $EN_DIS
+**/
+  UINT8                       PPR;
+
+/** Offset 0x0227 - Reserved
+**/
+  UINT8                       Reserved17;
+
+/** Offset 0x0228 - PPR Run Once
+  When Eanble, PPR will run only once and then is disabled at next training cycle
+  $EN_DIS
+**/
+  UINT8                       PprRunOnce;
+
+/** Offset 0x0229 - PPR Run During Fastboot
+  When Eanble, PPR will run during fastboot
+  $EN_DIS
+**/
+  UINT8                       PprRunAtFastboot;
+
+/** Offset 0x022A - PPR Repair Type
+  PPR Repair Type: 0:Do not Repair (Default), 1:Soft Repair, 2:Hard Repair
+  0:Do not Repair (Default), 1:Soft Repair, 2:Hard Repair
+**/
+  UINT8                       PprRepairType;
+
+/** Offset 0x022B - PPR Error Injection
+  When Eanble, PPR will inject bad rows during testing
+  $EN_DIS
+**/
+  UINT8                       PprErrorInjection;
+
+/** Offset 0x022C - PPR Repair Controller
+  PPR repair controller: User chooses to force repair specifc address
+**/
+  UINT8                       PprRepairController;
+
+/** Offset 0x022D - PPR Repair Channel
+  PPR repair Channel: User chooses to force repair specifc address
+**/
+  UINT8                       PprRepairChannel;
+
+/** Offset 0x022E - PPR Repair Dimm
+  PPR repair Dimm: User chooses to force repair specifc address
+**/
+  UINT8                       PprRepairDimm;
+
+/** Offset 0x022F - PPR Repair Rank
+  PPR repair Rank: User chooses to force repair specifc address
+**/
+  UINT8                       PprRepairRank;
+
+/** Offset 0x0230 - PPR Repair Row
+  PPR repair Row: User chooses to force repair specifc address
+**/
+  UINT32                      PprRepairRow;
+
+/** Offset 0x0234 - Reserved
+**/
+  UINT8                      Reserved18[8];
+
+/** Offset 0x023C - PPR Repair BankGroup
+  PPR repair BankGroup: User chooses to force repair specifc address
+**/
+  UINT8                       PprRepairBankGroup;
+
+/** Offset 0x023D - LVR Auto Trim
+  Enable/disable LVR Auto Trim
+  $EN_DIS
+**/
+  UINT8                       LVRAUTOTRIM;
+
+/** Offset 0x023E - Compensation Optimization
+  Enable/Disable Compensation Optimization
+  $EN_DIS
+**/
+  UINT8                       OPTIMIZECOMP;
+
+/** Offset 0x023F - Write DQ/DQS Retraining
+  Enable/Disable Write DQ/DQS Retraining
+  $EN_DIS
+**/
+  UINT8                       WRTRETRAIN;
+
+/** Offset 0x0240 - Reserved
+**/
+  UINT8                       Reserved19[3];
+
+/** Offset 0x0243 - RDDQODTT
+  Enable/disable Read DQ ODT Training
+  $EN_DIS
+**/
+  UINT8                       RDDQODTT;
+
+/** Offset 0x0244 - RDCTLET
+  Enable/disable Read CTLE Training
+  $EN_DIS
+**/
+  UINT8                       RDCTLET;
+
+/** Offset 0x0245 - RxVref Pre EMPHASIS Training
+  Enable/Disable Pre EMPHASIS Training
+  $EN_DIS
+**/
+  UINT8                       EMPHASIS;
+
+/** Offset 0x0246 - RX DQS VOC Centring Training
+  Enable/Disable RX DQS VOC Centring Training
+  $EN_DIS
+**/
+  UINT8                       RXDQSVOCC;
+
+/** Offset 0x0247 - NMode
   System command rate, range 0-2, 0 means auto, 1 = 1N, 2 = 2N
 **/
   UINT8                       NModeSupport;
 
-/** Offset 0x0281 - LPDDR ODT RttWr
+/** Offset 0x0248 - LPDDR ODT RttWr
   Initial RttWr for LP4/5 in Ohms. 0x0 - Auto
 **/
   UINT8                       LpddrRttWr;
 
-/** Offset 0x0282 - Retrain on Fast flow Failure
+/** Offset 0x0249 - Retrain on Fast flow Failure
   Restart MRC in Cold mode if SW MemTest fails during Fast flow.
   $EN_DIS
 **/
   UINT8                       RetrainOnFastFail;
 
-/** Offset 0x0283 - LPDDR ODT RttCa
+/** Offset 0x024A - LPDDR ODT RttCa
   Initial RttCa for LP4/5 in Ohms. 0x0 - Auto
 **/
   UINT8                       LpddrRttCa;
 
-/** Offset 0x0284 - DIMM DFE Training
+/** Offset 0x024B - DIMM DFE Training
   Enable/Disable DIMM DFE Training
   $EN_DIS
 **/
   UINT8                       WRTDIMMDFE;
 
-/** Offset 0x0285 - DDR5 ODT Timing Config
+/** Offset 0x024C - DDR5 ODT Timing Config
   Enable/Disable DDR5 ODT TIMING CONFIG
   $EN_DIS
 **/
   UINT8                       DDR5ODTTIMING;
 
-/** Offset 0x0286 - HobBufferSize
+/** Offset 0x024D - HobBufferSize
   Size to set HOB Buffer. 0:Default, 1: 1 Byte, 2: 1 KB, 3: Max value(assuming 63KB
   total HOB size).
   0:Default, 1: 1 Byte, 2: 1 KB, 3: Max value
 **/
   UINT8                       HobBufferSize;
 
-/** Offset 0x0287 - Early Command Training
+/** Offset 0x024E - Early Command Training
   Enables/Disable Early Command Training
   $EN_DIS
 **/
   UINT8                       ECT;
 
-/** Offset 0x0288 - SenseAmp Offset Training
+/** Offset 0x024F - SenseAmp Offset Training
   Enables/Disable SenseAmp Offset Training
   $EN_DIS
 **/
   UINT8                       SOT;
 
-/** Offset 0x0289 - Early ReadMPR Timing Centering 2D
+/** Offset 0x0250 - Early ReadMPR Timing Centering 2D
   Enables/Disable Early ReadMPR Timing Centering 2D
   $EN_DIS
 **/
   UINT8                       ERDMPRTC2D;
 
-/** Offset 0x028A - Read MPR Training
+/** Offset 0x0251 - Read MPR Training
   Enables/Disable Read MPR Training
   $EN_DIS
 **/
   UINT8                       RDMPRT;
 
-/** Offset 0x028B - Receive Enable Training
+/** Offset 0x0252 - Receive Enable Training
   Enables/Disable Receive Enable Training
   $EN_DIS
 **/
   UINT8                       RCVET;
 
-/** Offset 0x028C - Jedec Write Leveling
+/** Offset 0x0253 - Jedec Write Leveling
   Enables/Disable Jedec Write Leveling
   $EN_DIS
 **/
   UINT8                       JWRL;
 
-/** Offset 0x028D - Early Write Time Centering 2D
+/** Offset 0x0254 - Early Write Time Centering 2D
   Enables/Disable Early Write Time Centering 2D
   $EN_DIS
 **/
   UINT8                       EWRTC2D;
 
-/** Offset 0x028E - Early Read Time Centering 2D
+/** Offset 0x0255 - Early Read Time Centering 2D
   Enables/Disable Early Read Time Centering 2D
   $EN_DIS
 **/
   UINT8                       ERDTC2D;
 
-/** Offset 0x028F - Unmatched Write Time Centering 1D
+/** Offset 0x0256 - Unmatched Write Time Centering 1D
   Enable/Disable Unmatched Write Time Centering 1D
   $EN_DIS
 **/
   UINT8                       UNMATCHEDWRTC1D;
 
-/** Offset 0x0290 - Write Timing Centering 1D
+/** Offset 0x0257 - Write Timing Centering 1D
   Enables/Disable Write Timing Centering 1D
   $EN_DIS
 **/
   UINT8                       WRTC1D;
 
-/** Offset 0x0291 - Write Voltage Centering 1D
+/** Offset 0x0258 - Write Voltage Centering 1D
   Enables/Disable Write Voltage Centering 1D
   $EN_DIS
 **/
   UINT8                       WRVC1D;
 
-/** Offset 0x0292 - Read Timing Centering 1D
+/** Offset 0x0259 - Read Timing Centering 1D
   Enables/Disable Read Timing Centering 1D
   $EN_DIS
 **/
   UINT8                       RDTC1D;
 
-/** Offset 0x0293 - Dimm ODT Training
+/** Offset 0x025A - Dimm ODT Training
   Enables/Disable Dimm ODT Training
   $EN_DIS
 **/
   UINT8                       DIMMODTT;
 
-/** Offset 0x0294 - DIMM RON Training
+/** Offset 0x025B - DIMM RON Training
   Enables/Disable DIMM RON Training
   $EN_DIS
 **/
   UINT8                       DIMMRONT;
 
-/** Offset 0x0295 - Write Drive Strength/Equalization 2D
+/** Offset 0x025C - Write Drive Strength/Equalization 2D
   Enables/Disable Write Drive Strength/Equalization 2D
   $EN_DIS
 **/
   UINT8                       WRDSEQT;
 
-/** Offset 0x0296 - Read Equalization Training
+/** Offset 0x025D - Read Equalization Training
   Enables/Disable Read Equalization Training
   $EN_DIS
 **/
   UINT8                       RDEQT;
 
-/** Offset 0x0297 - Write Timing Centering 2D
+/** Offset 0x025E - Write Timing Centering 2D
   Enables/Disable Write Timing Centering 2D
   $EN_DIS
 **/
   UINT8                       WRTC2D;
 
-/** Offset 0x0298 - Read Timing Centering 2D
+/** Offset 0x025F - Read Timing Centering 2D
   Enables/Disable Read Timing Centering 2D
   $EN_DIS
 **/
   UINT8                       RDTC2D;
 
-/** Offset 0x0299 - Write Voltage Centering 2D
+/** Offset 0x0260 - Write Voltage Centering 2D
   Enables/Disable Write Voltage Centering 2D
   $EN_DIS
 **/
   UINT8                       WRVC2D;
 
-/** Offset 0x029A - Read Voltage Centering 2D
+/** Offset 0x0261 - Read Voltage Centering 2D
   Enables/Disable Read Voltage Centering 2D
   $EN_DIS
 **/
   UINT8                       RDVC2D;
 
-/** Offset 0x029B - Command Voltage Centering
+/** Offset 0x0262 - Command Voltage Centering
   Enables/Disable Command Voltage Centering
   $EN_DIS
 **/
   UINT8                       CMDVC;
 
-/** Offset 0x029C - Late Command Training
+/** Offset 0x0263 - Late Command Training
   Enables/Disable Late Command Training
   $EN_DIS
 **/
   UINT8                       LCT;
 
-/** Offset 0x029D - Round Trip Latency Training
+/** Offset 0x0264 - Round Trip Latency Training
   Enables/Disable Round Trip Latency Training
   $EN_DIS
 **/
   UINT8                       RTL;
 
-/** Offset 0x029E - Turn Around Timing Training
+/** Offset 0x0265 - Turn Around Timing Training
   Enables/Disable Turn Around Timing Training
   $EN_DIS
 **/
   UINT8                       TAT;
 
-/** Offset 0x029F - Reserved
+/** Offset 0x0266 - Reserved
 **/
-  UINT8                       Reserved25;
+  UINT8                       Reserved20;
 
-/** Offset 0x02A0 - DIMM SPD Alias Test
+/** Offset 0x0267 - DIMM SPD Alias Test
   Enables/Disable DIMM SPD Alias Test
   $EN_DIS
 **/
   UINT8                       ALIASCHK;
 
-/** Offset 0x02A1 - Receive Enable Centering 1D
+/** Offset 0x0268 - Receive Enable Centering 1D
   Enables/Disable Receive Enable Centering 1D
   $EN_DIS
 **/
   UINT8                       RCVENC1D;
 
-/** Offset 0x02A2 - Retrain Margin Check
+/** Offset 0x0269 - Retrain Margin Check
   Enables/Disable Retrain Margin Check
   $EN_DIS
 **/
   UINT8                       RMC;
 
-/** Offset 0x02A3 - ECC Support
+/** Offset 0x026A - ECC Support
   Enables/Disable ECC Support
   $EN_DIS
 **/
   UINT8                       EccSupport;
 
-/** Offset 0x02A4 - Reserved
+/** Offset 0x026B - Reserved
 **/
-  UINT8                       Reserved26[2];
+  UINT8                       Reserved21[2];
 
-/** Offset 0x02A6 - Ibecc
+/** Offset 0x026D - Ibecc
   In-Band ECC Support
   $EN_DIS
 **/
   UINT8                       Ibecc;
 
-/** Offset 0x02A7 - IbeccParity
+/** Offset 0x026E - IbeccParity
   In-Band ECC Parity Control
   $EN_DIS
 **/
   UINT8                       IbeccParity;
 
-/** Offset 0x02A8 - Reserved
+/** Offset 0x026F - Reserved
 **/
-  UINT8                      Reserved27[4];
+  UINT8                       Reserved22;
 
-/** Offset 0x02AC - IbeccOperationMode
+/** Offset 0x0270 - IbeccOperationMode
   In-Band ECC Operation Mode
   0:Protect base on address range, 1: Non-protected, 2: All protected
 **/
   UINT8                       IbeccOperationMode;
 
-/** Offset 0x02AD - IbeccProtectedRegionEnable
+/** Offset 0x0271 - IbeccProtectedRegionEnable
   In-Band ECC Protected Region Enable
   $EN_DIS
 **/
   UINT8                       IbeccProtectedRegionEnable[8];
 
-/** Offset 0x02B5 - Reserved
+/** Offset 0x0279 - Reserved
 **/
-  UINT8                       Reserved28;
+  UINT8                       Reserved23;
 
-/** Offset 0x02B6 - IbeccProtectedRegionBases
+/** Offset 0x027A - IbeccProtectedRegionBases
   IBECC Protected Region Bases per IBECC instance
 **/
   UINT16                      IbeccProtectedRegionBase[8];
 
-/** Offset 0x02C6 - IbeccProtectedRegionMasks
+/** Offset 0x028A - IbeccProtectedRegionMasks
   IBECC Protected Region Masks
 **/
   UINT16                      IbeccProtectedRegionMask[8];
 
-/** Offset 0x02D6 - Memory Remap
+/** Offset 0x029A - Memory Remap
   Enables/Disable Memory Remap
   $EN_DIS
 **/
   UINT8                       RemapEnable;
 
-/** Offset 0x02D7 - Reserved
-**/
-  UINT8                       Reserved29;
-
-/** Offset 0x02D8 - Rank Interleave support
+/** Offset 0x029B - Rank Interleave support
   Enables/Disable Rank Interleave support. NOTE: RI and HORI can not be enabled at
   the same time.
   $EN_DIS
 **/
-  UINT32                      RankInterleave;
+  UINT8                       RankInterleave;
 
-/** Offset 0x02DC - Enhanced Interleave support
+/** Offset 0x029C - Enhanced Interleave support
   Enables/Disable Enhanced Interleave support
   $EN_DIS
 **/
-  UINT32                      EnhancedInterleave;
+  UINT8                       EnhancedInterleave;
 
-/** Offset 0x02E0 - Ch Hash Support
+/** Offset 0x029D - Ch Hash Support
   Enable/Disable Channel Hash Support. NOTE: ONLY if Memory interleaved Mode
   $EN_DIS
 **/
-  UINT32                      ChHashEnable;
+  UINT8                       ChHashEnable;
 
-/** Offset 0x02E4 - DDR PowerDown and idle counter
+/** Offset 0x029E - DDR PowerDown and idle counter
   Enables/Disable DDR PowerDown and idle counter(For LPDDR Only)
   $EN_DIS
 **/
-  UINT32                      EnablePwrDn;
+  UINT8                       EnablePwrDn;
 
-/** Offset 0x02E8 - DDR PowerDown and idle counter
+/** Offset 0x029F - DDR PowerDown and idle counter
   Enables/Disable DDR PowerDown and idle counter(For LPDDR Only)
   $EN_DIS
 **/
   UINT8                       EnablePwrDnLpddr;
 
-/** Offset 0x02E9 - Reserved
-**/
-  UINT8                       Reserved30[3];
-
-/** Offset 0x02EC - SelfRefresh Enable
+/** Offset 0x02A0 - SelfRefresh Enable
   Enables/Disable SelfRefresh Enable
   $EN_DIS
 **/
-  UINT32                      SrefCfgEna;
+  UINT8                       SrefCfgEna;
 
-/** Offset 0x02F0 - Throttler CKEMin Defeature
+/** Offset 0x02A1 - Throttler CKEMin Defeature
   Enables/Disable Throttler CKEMin Defeature(For LPDDR Only)
   $EN_DIS
 **/
   UINT8                       ThrtCkeMinDefeatLpddr;
 
-/** Offset 0x02F1 - Reserved
-**/
-  UINT8                       Reserved31[3];
-
-/** Offset 0x02F4 - Throttler CKEMin Defeature
+/** Offset 0x02A2 - Throttler CKEMin Defeature
   Enables/Disable Throttler CKEMin Defeature
   $EN_DIS
 **/
-  UINT32                      ThrtCkeMinDefeat;
+  UINT8                       ThrtCkeMinDefeat;
 
-/** Offset 0x02F8 - Exit On Failure (MRC)
+/** Offset 0x02A3 - Exit On Failure (MRC)
   Enables/Disable Exit On Failure (MRC)
   $EN_DIS
 **/
   UINT8                       ExitOnFailure;
 
-/** Offset 0x02F9 - Reserved
+/** Offset 0x02A4 - Reserved
 **/
-  UINT8                       Reserved32[2];
+  UINT8                       Reserved24[2];
 
-/** Offset 0x02FB - Read Voltage Centering 1D
+/** Offset 0x02A6 - Read Voltage Centering 1D
   Enable/Disable Read Voltage Centering 1D
   $EN_DIS
 **/
   UINT8                       RDVC1D;
 
-/** Offset 0x02FC - TxDqTCO Comp Training
+/** Offset 0x02A7 - TxDqTCO Comp Training
   Enable/Disable TxDqTCO Comp Training
   $EN_DIS
 **/
   UINT8                       TXTCO;
 
-/** Offset 0x02FD - ClkTCO Comp Training
+/** Offset 0x02A8 - ClkTCO Comp Training
   Enable/Disable ClkTCO Comp Training
   $EN_DIS
 **/
   UINT8                       CLKTCO;
 
-/** Offset 0x02FE - CMD Slew Rate Training
+/** Offset 0x02A9 - CMD Slew Rate Training
   Enable/Disable CMD Slew Rate Training
   $EN_DIS
 **/
   UINT8                       CMDSR;
 
-/** Offset 0x02FF - CMD Drive Strength and Tx Equalization
+/** Offset 0x02AA - CMD Drive Strength and Tx Equalization
   Enable/Disable CMD Drive Strength and Tx Equalization
   $EN_DIS
 **/
   UINT8                       CMDDSEQ;
 
-/** Offset 0x0300 - DIMM CA ODT Training
+/** Offset 0x02AB - DIMM CA ODT Training
   Enable/Disable DIMM CA ODT Training
   $EN_DIS
 **/
   UINT8                       DIMMODTCA;
 
-/** Offset 0x0301 - Read Vref Decap Training*
+/** Offset 0x02AC - Read Vref Decap Training*
   Enable/Disable Read Vref Decap Training*
   $EN_DIS
 **/
   UINT8                       RDVREFDC;
 
-/** Offset 0x0302 - Vddq Training
-  Enable/Disable Vddq Training
-  $EN_DIS
-**/
-  UINT8                       VDDQT;
-
-/** Offset 0x0303 - Rank Margin Tool Per Bit
+/** Offset 0x02AD - Rank Margin Tool Per Bit
   Enable/Disable Rank Margin Tool Per Bit
   $EN_DIS
 **/
   UINT8                       RMTBIT;
 
-/** Offset 0x0304 - Ref PI Calibration
+/** Offset 0x02AE - Ref PI Calibration
   Enable/Disable Ref PI Calibration
   $EN_DIS
 **/
   UINT8                       REFPI;
 
-/** Offset 0x0305 - VccClk FF Offset Correction
+/** Offset 0x02AF - VccClk FF Offset Correction
   Enable/Disable VccClk FF Offset Correction
   0:Disable, 1:Enable
 **/
   UINT8                       VCCCLKFF;
 
-/** Offset 0x0306 - Reserved
-**/
-  UINT8                       Reserved33[2];
-
-/** Offset 0x0308 - Data PI Linearity Calibration
+/** Offset 0x02B0 - Data PI Linearity Calibration
   Enable/Disable {Data PI Linearity Calibration
   $EN_DIS
 **/
-  UINT32                      DATAPILIN;
+  UINT8                       DATAPILIN;
 
-/** Offset 0x030C - Ddr5 Rx Cross-Talk Cancellation
+/** Offset 0x02B1 - Ddr5 Rx Cross-Talk Cancellation
   Enable/Disable {Ddr5 Rx Cross-Talk Cancellation
   $EN_DIS
 **/
   UINT8                       DDR5XTALK;
 
-/** Offset 0x030D - Retrain On Working Channel
+/** Offset 0x02B2 - Retrain On Working Channel
   Enables/Disable Retrain On Working Channel feature
   $EN_DIS
 **/
   UINT8                       RetrainToWorkingChannel;
 
-/** Offset 0x030E - Reserved
+/** Offset 0x02B3 - Row Press
+  Enables/Disable Row Press feature
+  $EN_DIS
 **/
-  UINT8                       Reserved34;
+  UINT8                       RowPressEn;
 
-/** Offset 0x030F - Select if ZQ pin is shared between Rank0 and Rank1 in DDR4 DDP
-  ESelect if ZQ pin is shared between Rank0 and Rank1 in DDR4 DDP
+/** Offset 0x02B4 - Reserved
+**/
+  UINT8                       Reserved25;
+
+/** Offset 0x02B5 - DDR5 MR7 WICA support
+  Enable if DDR5 DRAM Device supports MR7 WICA 0.5 tCK offset alignment
   $EN_DIS
 **/
   UINT8                       IsDdr5MR7WicaSupported;
 
-/** Offset 0x0310 - Ch Hash Interleaved Bit
+/** Offset 0x02B6 - Ch Hash Interleaved Bit
   Select the BIT to be used for Channel Interleaved mode. NOTE: BIT7 will interlave
   the channels at a 2 cacheline granularity, BIT8 at 4 and BIT9 at 8. Default is BIT8
   0:BIT6, 1:BIT7, 2:BIT8, 3:BIT9, 4:BIT10, 5:BIT11, 6:BIT12, 7:BIT13
 **/
   UINT8                       ChHashInterleaveBit;
 
-/** Offset 0x0311 - Reserved
+/** Offset 0x02B7 - Reserved
 **/
-  UINT8                       Reserved35;
+  UINT8                       Reserved26;
 
-/** Offset 0x0312 - Ch Hash Mask
+/** Offset 0x02B8 - Ch Hash Mask
   Set the BIT(s) to be included in the XOR function. NOTE BIT mask corresponds to
   BITS [19:6] Default is 0x30CC
 **/
   UINT16                      ChHashMask;
 
-/** Offset 0x0314 - Reserved
+/** Offset 0x02BA - Reserved
 **/
-  UINT8                      Reserved36[2];
+  UINT8                       Reserved27;
 
-/** Offset 0x0316 - Throttler CKEMin Timer
+/** Offset 0x02BB - Throttler CKEMin Timer
   Timer value for CKEMin, range[255;0]. Req'd min of SC_ROUND_T + BYTE_LENGTH (4).
   Dfault is 0x00
 **/
   UINT8                       ThrtCkeMinTmr;
 
-/** Offset 0x0317 - Allow Opp Ref Below Write Threhold
+/** Offset 0x02BC - Allow Opp Ref Below Write Threhold
   Allow opportunistic refreshes while we don't exit power down.
   $EN_DIS
 **/
   UINT8                       AllowOppRefBelowWriteThrehold;
 
-/** Offset 0x0318 - Write Threshold
+/** Offset 0x02BD - Write Threshold
   Number of writes that can be accumulated while CKE is low before CKE is asserted.
 **/
   UINT8                       WriteThreshold;
 
-/** Offset 0x0319 - MC_REFRESH_RATE
+/** Offset 0x02BE - MC_REFRESH_RATE
   Type of Refresh Rate used to prevent Row Hammer. Default is NORMAL Refresh
   0:NORMAL Refresh, 1:1x Refresh, 2:2x Refresh, 3:4x Refresh
 **/
   UINT8                       McRefreshRate;
 
-/** Offset 0x031A - Refresh Watermarks
+/** Offset 0x02BF - Refresh Watermarks
   Refresh Watermarks: 0-Low, 1-High (default)
   0:Set Refresh Watermarks to Low, 1:Set Refresh Watermarks to High (Default)
 **/
   UINT8                       RefreshWm;
 
-/** Offset 0x031B - Reserved
+/** Offset 0x02C0 - User Manual Threshold
+  Disabled: Predefined threshold will be used.\n
+  Enabled: User Input will be used.
+  $EN_DIS
 **/
-  UINT8                       Reserved37[2];
+  UINT8                       UserThresholdEnable;
 
-/** Offset 0x031D - Power Down Mode
+/** Offset 0x02C1 - User Manual Budget
+  Disabled: Configuration of memories will defined the Budget value.\n
+  Enabled: User Input will be used.
+  $EN_DIS
+**/
+  UINT8                       UserBudgetEnable;
+
+/** Offset 0x02C2 - Power Down Mode
   This option controls command bus tristating during idle periods
   0x0:No Power Down, 0x1:APD, 0x6:PPD DLL OFF, 0xFF:Auto
 **/
   UINT8                       PowerDownMode;
 
-/** Offset 0x031E - Pwr Down Idle Timer
+/** Offset 0x02C3 - Pwr Down Idle Timer
   The minimum value should = to the worst case Roundtrip delay + Burst_Length. 0 means
   AUTO: 64 for ULX/ULT, 128 for DT/Halo
 **/
   UINT8                       PwdwnIdleCounter;
 
-/** Offset 0x031F - Page Close Idle Timeout
+/** Offset 0x02C4 - Page Close Idle Timeout
   This option controls Page Close Idle Timeout
   0:Enabled, 1:Disabled
 **/
   UINT8                       DisPgCloseIdleTimeout;
 
-/** Offset 0x0320 - Reserved
+/** Offset 0x02C5 - Bitmask of ranks that have CA bus terminated
+  LPDDR5: Bitmask of ranks that have CA bus terminated. <b>0x01=Default, Rank0 is
+  terminating and Rank1 is non-terminating</b>
 **/
-  UINT8                       Reserved38;
+  UINT8                       CmdRanksTerminated;
 
-/** Offset 0x0321 - MRC Safe Mode Override
+/** Offset 0x02C6 - MRC Safe Mode Override
   SafeModeOverride[0] Enable DdrSafeMode override, SafeModeOverride[1] Enable McSafeMode
   override, SafeModeOverride[2] Enable MrcSafeMode override, SafeModeOverride[3]
   Enable Training Algorithm (TrainingEnables) safe mode override, SafeModeOverride[4]
@@ -1413,18 +1366,18 @@ typedef struct {
 **/
   UINT8                       SafeModeOverride;
 
-/** Offset 0x0322 - Reserved
+/** Offset 0x02C7 - Reserved
 **/
-  UINT8                       Reserved39[2];
+  UINT8                       Reserved28[5];
 
-/** Offset 0x0324 - DDR Phy Safe Mode Support
+/** Offset 0x02CC - DDR Phy Safe Mode Support
   DdrSafeMode[0]: Basic PM Features, DdrSafeMode[1]: Spine Gating, DdrSafeMode[2]:
   Advanced DCC, DdrSafeMode[3]: R2R Training, DdrSafeMode[4]: Transformer Mode, DdrSafeMode[5]:
   PLL Operation, DdrSafeMode[6]: Safe ODT
 **/
   UINT32                      DdrSafeMode;
 
-/** Offset 0x0328 - Mc Safe Mode Support
+/** Offset 0x02D0 - Mc Safe Mode Support
   McSafeMode[0]: Clk Gate / BGF, McSafeMode[1]: CKE Pdwn, McSafeMode[2]: Tristate,
   McSafeMode[3]: PHY Power States / Clock Spine, McSafeMode[4]: Same Rank TA, McSafeMode[5]:
   Different Rank TA, McSafeMode[6]: MR4_Period / ZQCAL_Period McSafeMode[7]: LP5
@@ -1433,349 +1386,360 @@ typedef struct {
 **/
   UINT8                       McSafeMode;
 
-/** Offset 0x0329 - Ask MRC to clear memory content
+/** Offset 0x02D1 - Ask MRC to clear memory content
   Ask MRC to clear memory content <b>0: Do not Clear Memory;</b> 1: Clear Memory.
   $EN_DIS
 **/
   UINT8                       CleanMemory;
 
-/** Offset 0x032A - Reserved
+/** Offset 0x02D2 - Reserved
 **/
-  UINT8                       Reserved40[8];
+  UINT8                       Reserved29[8];
 
-/** Offset 0x0332 - RMTLoopCount
+/** Offset 0x02DA - RMTLoopCount
   Specifies the Loop Count to be used during Rank Margin Tool Testing. 0 - AUTO
 **/
   UINT8                       RMTLoopCount;
 
-/** Offset 0x0333 - DdrOneDpc
+/** Offset 0x02DB - DdrOneDpc
   DDR 1DPC performance feature for 2R DIMMs. Can be enabled on DIMM0 or DIMM1 only,
   or on both (default)
   0: Disabled, 1: Enabled on DIMM0 only, 2: Enabled on DIMM1 only, 3: Enabled
 **/
   UINT8                       DdrOneDpc;
 
-/** Offset 0x0334 - Vddq Voltage Override
+/** Offset 0x02DC - Vddq Voltage Override
   # is multiple of 1mV where 0 means Auto.
 **/
   UINT16                      VddqVoltageOverride;
 
-/** Offset 0x0336 - VccIog Voltage Override
+/** Offset 0x02DE - VccIog Voltage Override
   # is multiple of 1mV where 0 means Auto.
 **/
   UINT16                      VccIogVoltageOverride;
 
-/** Offset 0x0338 - VccClk Voltage Override
+/** Offset 0x02E0 - VccClk Voltage Override
   # is multiple of 1mV where 0 means Auto.
 **/
   UINT16                      VccClkVoltageOverride;
 
-/** Offset 0x033A - ThrtCkeMinTmrLpddr
+/** Offset 0x02E2 - ThrtCkeMinTmrLpddr
   Throttler CKE min timer for LPDDR: 0=Minimal, 0xFF=Maximum, <b>0x00=Default</b>
 **/
   UINT8                       ThrtCkeMinTmrLpddr;
 
-/** Offset 0x033B - Reserved
+/** Offset 0x02E3 - Reserved
 **/
-  UINT8                       Reserved41;
+  UINT8                       Reserved30;
 
-/** Offset 0x033C - Margin limit check L2
+/** Offset 0x02E4 - Margin limit check L2
   Margin limit check L2 threshold: <b>100=Default</b>
 **/
   UINT16                      MarginLimitL2;
 
-/** Offset 0x033E - Extended Bank Hashing
+/** Offset 0x02E6 - Extended Bank Hashing
   Eanble/Disable ExtendedBankHashing
   $EN_DIS
 **/
   UINT8                       ExtendedBankHashing;
 
-/** Offset 0x033F - Reserved
+/** Offset 0x02E7 - Reserved
 **/
-  UINT8                       Reserved42;
+  UINT8                       Reserved31;
 
-/** Offset 0x0340 - Command Pins Mapping
+/** Offset 0x02E8 - LP5 Command Pins Mapping
   BitMask where bits [3:0] are Controller 0 Channel [3:0] and bits [7:4] are Controller
   1 Channel [3:0]. 0 = CCC pin mapping is Ascending, 1 = CCC pin mapping is Descending.
 **/
   UINT8                       Lp5CccConfig;
 
-/** Offset 0x0341 - Command Pins Mirrored
+/** Offset 0x02E9 - Command Pins Mirrored
   BitMask where bits [3:0] are Controller 0 Channel [3:0] and bits [7:4] are Controller
   1 Channel [3:0]. 0 = No Command Mirror and 1 = Command Mirror.
 **/
   UINT8                       CmdMirror;
 
-/** Offset 0x0342 - Time Measure
+/** Offset 0x02EA - Time Measure
   Time Measure: 0(Default)=Disable, 1=Enable
   $EN_DIS
 **/
   UINT8                       MrcTimeMeasure;
 
-/** Offset 0x0343 - Reserved
+/** Offset 0x02EB - Reserved
 **/
-  UINT8                       Reserved43[8];
+  UINT8                       Reserved32[66];
 
-/** Offset 0x034B - Board Type
+/** Offset 0x032D - Board Type
   MrcBoardType, Options are 0=Mobile/Mobile Halo, 1=Desktop/DT Halo, 5=ULT/ULX/Mobile
   Halo, 7=UP Server
   0:Mobile/Mobile Halo, 1:Desktop/DT Halo, 5:ULT/ULX/Mobile Halo, 7:UP Server
 **/
   UINT8                       UserBd;
 
-/** Offset 0x034C - Spd Address Table
+/** Offset 0x032E - Spd Address Table
   Specify SPD Address table for CH0D0/CH0D1/CH1D0&CH1D1. MemorySpdPtr will be used
   if SPD Address is 00
 **/
   UINT8                       SpdAddressTable[16];
 
-/** Offset 0x035C - Enable/Disable MRC TXT dependency
+/** Offset 0x033E - Enable/Disable MRC TXT dependency
   When enabled MRC execution will wait for TXT initialization to be done first. Disabled(0x0)(Default):
   MRC will not wait for TXT initialization, Enabled(0x1): MRC will wait for TXT initialization
   $EN_DIS
 **/
   UINT8                       TxtImplemented;
 
-/** Offset 0x035D - Reserved
+/** Offset 0x033F - Reserved
 **/
-  UINT8                       Reserved44;
+  UINT8                       Reserved33;
 
-/** Offset 0x035E - Skip external display device scanning
+/** Offset 0x0340 - Skip external display device scanning
   Enable: Do not scan for external display device, Disable (Default): Scan external
   display devices
   $EN_DIS
 **/
   UINT8                       SkipExtGfxScan;
 
-/** Offset 0x035F - Generate BIOS Data ACPI Table
+/** Offset 0x0341 - Generate BIOS Data ACPI Table
   Enable: Generate BDAT for MRC RMT or SA PCIe data. Disable (Default): Do not generate it
   $EN_DIS
 **/
   UINT8                       BdatEnable;
 
-/** Offset 0x0360 - BdatTestType
+/** Offset 0x0342 - BdatTestType
   Indicates the type of Memory Training data to populate into the BDAT ACPI table.
   0:RMT per Rank, 1:RMT per Bit, 2:Margin2D
 **/
   UINT8                       BdatTestType;
 
-/** Offset 0x0361 - Enable PCH HSIO PCIE Rx Set Ctle
+/** Offset 0x0343 - Enable PCH HSIO PCIE Rx Set Ctle
   Enable PCH PCIe Gen 3 Set CTLE Value.
 **/
   UINT8                       PchPcieHsioRxSetCtleEnable[28];
 
-/** Offset 0x037D - PCH HSIO PCIE Rx Set Ctle Value
+/** Offset 0x035F - PCH HSIO PCIE Rx Set Ctle Value
   PCH PCIe Gen 3 Set CTLE Value.
 **/
   UINT8                       PchPcieHsioRxSetCtle[28];
 
-/** Offset 0x0399 - Enble PCH HSIO PCIE TX Gen 1 Downscale Amplitude Adjustment value override
+/** Offset 0x037B - Enble PCH HSIO PCIE TX Gen 1 Downscale Amplitude Adjustment value override
   0: Disable; 1: Enable.
 **/
   UINT8                       PchPcieHsioTxGen1DownscaleAmpEnable[28];
 
-/** Offset 0x03B5 - PCH HSIO PCIE Gen 2 TX Output Downscale Amplitude Adjustment value
+/** Offset 0x0397 - PCH HSIO PCIE Gen 2 TX Output Downscale Amplitude Adjustment value
   PCH PCIe Gen 2 TX Output Downscale Amplitude Adjustment value.
 **/
   UINT8                       PchPcieHsioTxGen1DownscaleAmp[28];
 
-/** Offset 0x03D1 - Enable PCH HSIO PCIE TX Gen 2 Downscale Amplitude Adjustment value override
+/** Offset 0x03B3 - Enable PCH HSIO PCIE TX Gen 2 Downscale Amplitude Adjustment value override
   0: Disable; 1: Enable.
 **/
   UINT8                       PchPcieHsioTxGen2DownscaleAmpEnable[28];
 
-/** Offset 0x03ED - PCH HSIO PCIE Gen 2 TX Output Downscale Amplitude Adjustment value
+/** Offset 0x03CF - PCH HSIO PCIE Gen 2 TX Output Downscale Amplitude Adjustment value
   PCH PCIe Gen 2 TX Output Downscale Amplitude Adjustment value.
 **/
   UINT8                       PchPcieHsioTxGen2DownscaleAmp[28];
 
-/** Offset 0x0409 - Enable PCH HSIO PCIE TX Gen 3 Downscale Amplitude Adjustment value override
+/** Offset 0x03EB - Enable PCH HSIO PCIE TX Gen 3 Downscale Amplitude Adjustment value override
   0: Disable; 1: Enable.
 **/
   UINT8                       PchPcieHsioTxGen3DownscaleAmpEnable[28];
 
-/** Offset 0x0425 - PCH HSIO PCIE Gen 3 TX Output Downscale Amplitude Adjustment value
+/** Offset 0x0407 - PCH HSIO PCIE Gen 3 TX Output Downscale Amplitude Adjustment value
   PCH PCIe Gen 3 TX Output Downscale Amplitude Adjustment value.
 **/
   UINT8                       PchPcieHsioTxGen3DownscaleAmp[28];
 
-/** Offset 0x0441 - Enable PCH HSIO PCIE Gen 1 TX Output De-Emphasis Adjustment Setting value override
+/** Offset 0x0423 - Enable PCH HSIO PCIE Gen 1 TX Output De-Emphasis Adjustment Setting value override
   0: Disable; 1: Enable.
 **/
   UINT8                       PchPcieHsioTxGen1DeEmphEnable[28];
 
-/** Offset 0x045D - PCH HSIO PCIE Gen 1 TX Output De-Emphasis Adjustment value
+/** Offset 0x043F - PCH HSIO PCIE Gen 1 TX Output De-Emphasis Adjustment value
   PCH PCIe Gen 1 TX Output De-Emphasis Adjustment Setting.
 **/
   UINT8                       PchPcieHsioTxGen1DeEmph[28];
 
-/** Offset 0x0479 - Enable PCH HSIO PCIE Gen 2 TX Output -3.5dB De-Emphasis Adjustment Setting value override
+/** Offset 0x045B - Enable PCH HSIO PCIE Gen 2 TX Output -3.5dB De-Emphasis Adjustment Setting value override
   0: Disable; 1: Enable.
 **/
   UINT8                       PchPcieHsioTxGen2DeEmph3p5Enable[28];
 
-/** Offset 0x0495 - PCH HSIO PCIE Gen 2 TX Output -3.5dB De-Emphasis Adjustment value
+/** Offset 0x0477 - PCH HSIO PCIE Gen 2 TX Output -3.5dB De-Emphasis Adjustment value
   PCH PCIe Gen 2 TX Output -3.5dB De-Emphasis Adjustment Setting.
 **/
   UINT8                       PchPcieHsioTxGen2DeEmph3p5[28];
 
-/** Offset 0x04B1 - Enable PCH HSIO PCIE Gen 2 TX Output -6.0dB De-Emphasis Adjustment Setting value override
+/** Offset 0x0493 - Enable PCH HSIO PCIE Gen 2 TX Output -6.0dB De-Emphasis Adjustment Setting value override
   0: Disable; 1: Enable.
 **/
   UINT8                       PchPcieHsioTxGen2DeEmph6p0Enable[28];
 
-/** Offset 0x04CD - PCH HSIO PCIE Gen 2 TX Output -6.0dB De-Emphasis Adjustment value
+/** Offset 0x04AF - PCH HSIO PCIE Gen 2 TX Output -6.0dB De-Emphasis Adjustment value
   PCH PCIe Gen 2 TX Output -6.0dB De-Emphasis Adjustment Setting.
 **/
   UINT8                       PchPcieHsioTxGen2DeEmph6p0[28];
 
-/** Offset 0x04E9 - HD Audio DMIC Link Clock Select
+/** Offset 0x04CB - HD Audio DMIC Link Clock Select
   Determines DMIC<N> Clock Source. 0: Both, 1: ClkA, 2: ClkB
   0: Both, 1: ClkA, 2: ClkB
 **/
   UINT8                       PchHdaAudioLinkDmicClockSelect[2];
 
-/** Offset 0x04EB - Enable Intel HD Audio (Azalia)
+/** Offset 0x04CD - Enable Intel HD Audio (Azalia)
   0: Disable, 1: Enable (Default) Azalia controller
   $EN_DIS
 **/
   UINT8                       PchHdaEnable;
 
-/** Offset 0x04EC - Universal Audio Architecture compliance for DSP enabled system
+/** Offset 0x04CE - Universal Audio Architecture compliance for DSP enabled system
   0: Not-UAA Compliant (Intel SST driver supported only), 1: UAA Compliant (HDA Inbox
   driver or SST driver supported).
   $EN_DIS
 **/
   UINT8                       PchHdaDspUaaCompliance;
 
-/** Offset 0x04ED - Enable HD Audio Link
+/** Offset 0x04CF - Enable HD Audio Link
   Enable/disable HD Audio Link. Muxed with SSP0/SSP1/SNDW1.
   $EN_DIS
 **/
   UINT8                       PchHdaAudioLinkHdaEnable;
 
-/** Offset 0x04EE - Enable HDA SDI lanes
+/** Offset 0x04D0 - Enable HDA SDI lanes
   Enable/disable HDA SDI lanes.
 **/
   UINT8                       PchHdaSdiEnable[2];
 
-/** Offset 0x04F0 - Enable HD Audio DMIC_N Link
+/** Offset 0x04D2 - Enable HD Audio DMIC_N Link
   Enable/disable HD Audio DMIC1 link. Muxed with SNDW3.
 **/
   UINT8                       PchHdaAudioLinkDmicEnable[2];
 
-/** Offset 0x04F2 - Reserved
-**/
-  UINT8                       Reserved45[2];
-
-/** Offset 0x04F4 - DMIC<N> ClkA Pin Muxing (N - DMIC number)
+/** Offset 0x04D4 - DMIC<N> ClkA Pin Muxing (N - DMIC number)
   Determines DMIC<N> ClkA Pin muxing. See  GPIO_*_MUXING_DMIC<N>_CLKA_*
 **/
   UINT32                      PchHdaAudioLinkDmicClkAPinMux[2];
 
-/** Offset 0x04FC - Enable HD Audio DSP
+/** Offset 0x04DC - Enable HD Audio DSP
   Enable/disable HD Audio DSP feature.
   $EN_DIS
 **/
   UINT8                       PchHdaDspEnable;
 
-/** Offset 0x04FD - Reserved
+/** Offset 0x04DD - Reserved
 **/
-  UINT8                       Reserved46[3];
+  UINT8                       Reserved34[3];
 
-/** Offset 0x0500 - DMIC<N> Data Pin Muxing
+/** Offset 0x04E0 - DMIC<N> Data Pin Muxing
   Determines DMIC<N> Data Pin muxing. See GPIO_*_MUXING_DMIC<N>_DATA_*
 **/
   UINT32                      PchHdaAudioLinkDmicDataPinMux[2];
 
-/** Offset 0x0508 - Enable HD Audio SSP0 Link
+/** Offset 0x04E8 - Enable HD Audio SSP0 Link
   Enable/disable HD Audio SSP_N/I2S link. Muxed with HDA. N-number 0-5
 **/
   UINT8                       PchHdaAudioLinkSspEnable[7];
 
-/** Offset 0x050F - Reserved
+/** Offset 0x04EF - Reserved
 **/
-  UINT8                       Reserved47[117];
+  UINT8                       Reserved35[117];
 
-/** Offset 0x0584 - Enable HD Audio SoundWire#N Link
+/** Offset 0x0564 - Enable HD Audio SoundWire#N Link
   Enable/disable HD Audio SNDW#N link. Muxed with HDA.
 **/
   UINT8                       PchHdaAudioLinkSndwEnable[5];
 
-/** Offset 0x0589 - iDisp-Link Frequency
+/** Offset 0x0569 - iDisp-Link Frequency
   iDisp-Link Freq (PCH_HDAUDIO_LINK_FREQUENCY enum): 4: 96MHz, 3: 48MHz.
   4: 96MHz, 3: 48MHz
 **/
   UINT8                       PchHdaIDispLinkFrequency;
 
-/** Offset 0x058A - iDisp-Link T-mode
+/** Offset 0x056A - iDisp-Link T-mode
   iDisp-Link T-Mode (PCH_HDAUDIO_IDISP_TMODE enum): 0: 2T, 2: 4T, 3: 8T, 4: 16T
   0: 2T, 2: 4T, 3: 8T, 4: 16T
 **/
   UINT8                       PchHdaIDispLinkTmode;
 
-/** Offset 0x058B - Reserved
+/** Offset 0x056B - Reserved
 **/
-  UINT8                       Reserved48[45];
+  UINT8                       Reserved36[45];
 
-/** Offset 0x05B8 - iDisplay Audio Codec disconnection
+/** Offset 0x0598 - iDisplay Audio Codec disconnection
   0: Not disconnected, enumerable, 1: Disconnected SDI, not enumerable.
   $EN_DIS
 **/
   UINT8                       PchHdaIDispCodecDisconnect;
 
-/** Offset 0x05B9 - Reserved
+/** Offset 0x0599 - Reserved
 **/
-  UINT8                       Reserved49[5];
+  UINT8                       Reserved37[5];
 
-/** Offset 0x05BE - HDA Power/Clock Gating (PGD/CGD)
+/** Offset 0x059E - HDA Power/Clock Gating (PGD/CGD)
   Enable/Disable HD Audio Power and Clock Gating(POR: Enable). 0: PLATFORM_POR, 1:
   FORCE_ENABLE, 2: FORCE_DISABLE.
   0: POR, 1: Force Enable, 2: Force Disable
 **/
   UINT8                       PchHdaTestPowerClockGating;
 
-/** Offset 0x05BF - Reserved
+/** Offset 0x059F - Reserved
 **/
-  UINT8                       Reserved50[7];
+  UINT8                       Reserved38;
 
-/** Offset 0x05C6 - Usage type for ClkSrc
+/** Offset 0x05A0 - Audio Sub System IDs
+  Set default Audio Sub System IDs. If its set to 0 then value from Strap is used.
+**/
+  UINT32                      PchHdaSubSystemIds;
+
+/** Offset 0x05A4 - Reserved
+**/
+  UINT8                       Reserved39;
+
+/** Offset 0x05A5 - PCH LPC Enhance the port 8xh decoding
+  Original LPC only decodes one byte of port 80h.
+  $EN_DIS
+**/
+  UINT8                       PchLpcEnhancePort8xhDecoding;
+
+/** Offset 0x05A6 - Usage type for ClkSrc
   0-23: PCH rootport, 0x70:LAN, 0x80: unspecified but in use (free running), 0xFF: not used
 **/
   UINT8                       PcieClkSrcUsage[18];
 
-/** Offset 0x05D8 - ClkReq-to-ClkSrc mapping
+/** Offset 0x05B8 - ClkReq-to-ClkSrc mapping
   Number of ClkReq signal assigned to ClkSrc
 **/
   UINT8                       PcieClkSrcClkReq[18];
 
-/** Offset 0x05EA - Reserved
+/** Offset 0x05CA - Reserved
 **/
-  UINT8                       Reserved51[46];
+  UINT8                       Reserved40[46];
 
-/** Offset 0x0618 - Enable PCIE RP Mask
+/** Offset 0x05F8 - Enable PCIE RP Mask
   Enable/disable PCIE Root Ports. 0: disable, 1: enable. One bit for each port, bit0
   for port1, bit1 for port2, and so on.
 **/
   UINT32                      PcieRpEnableMask;
 
-/** Offset 0x061C - Debug Interfaces
+/** Offset 0x05FC - Debug Interfaces
   Debug Interfaces. BIT0-RAM, BIT1-UART, BIT3-USB3, BIT4-Serial IO, BIT5-TraceHub,
   BIT2 - Not used.
 **/
   UINT8                       PcdDebugInterfaceFlags;
 
-/** Offset 0x061D - Reserved
+/** Offset 0x05FD - Reserved
 **/
-  UINT8                       Reserved52[3];
+  UINT8                       Reserved41[3];
 
-/** Offset 0x0620 - Serial Io Uart Debug Mmio Base
+/** Offset 0x0600 - Serial Io Uart Debug Mmio Base
   Select SerialIo Uart default MMIO resource in SEC/PEI phase when PcdLpssUartMode
   = SerialIoUartPci.
 **/
   UINT32                      SerialIoUartDebugMmioBase;
 
-/** Offset 0x0624 - PcdSerialDebugLevel
+/** Offset 0x0604 - PcdSerialDebugLevel
   Serial Debug Message Level. 0:Disable, 1:Error Only, 2:Error & Warnings, 3:Load,
   Error, Warnings & Info, 4:Load, Error, Warnings, Info & Event, 5:Load, Error, Warnings,
   Info & Verbose.
@@ -1784,7 +1748,7 @@ typedef struct {
 **/
   UINT8                       PcdSerialDebugLevel;
 
-/** Offset 0x0625 - SerialDebugMrcLevel
+/** Offset 0x0605 - SerialDebugMrcLevel
   MRC Serial Debug Message Level. 0:Disable, 1:Error Only, 2:Error & Warnings, 3:Load,
   Error, Warnings & Info, 4:Load, Error, Warnings, Info & Event, 5:Load, Error, Warnings,
   Info & Verbose.
@@ -1793,318 +1757,318 @@ typedef struct {
 **/
   UINT8                       SerialDebugMrcLevel;
 
-/** Offset 0x0626 - Serial Io Uart Debug Controller Number
+/** Offset 0x0606 - Serial Io Uart Debug Controller Number
   Select SerialIo Uart Controller for debug. Note: If UART0 is selected as CNVi BT
   Core interface, it cannot be used for debug purpose.
   0:SerialIoUart0, 1:SerialIoUart1, 2:SerialIoUart2
 **/
   UINT8                       SerialIoUartDebugControllerNumber;
 
-/** Offset 0x0627 - Serial Io Uart Debug Parity
+/** Offset 0x0607 - Serial Io Uart Debug Parity
   Set default Parity.
   0: DefaultParity, 1: NoParity, 2: EvenParity, 3: OddParity
 **/
   UINT8                       SerialIoUartDebugParity;
 
-/** Offset 0x0628 - Serial Io Uart Debug BaudRate
+/** Offset 0x0608 - Serial Io Uart Debug BaudRate
   Set default BaudRate Supported from 0 - default to 6000000. Recommended values 9600,
   19200, 57600, 115200, 460800, 921600, 1500000, 1843200, 3000000, 3686400, 6000000
 **/
   UINT32                      SerialIoUartDebugBaudRate;
 
-/** Offset 0x062C - Serial Io Uart Debug Stop Bits
+/** Offset 0x060C - Serial Io Uart Debug Stop Bits
   Set default stop bits.
   0: DefaultStopBits, 1: OneStopBit, 2: OneFiveStopBits, 3: TwoStopBits
 **/
   UINT8                       SerialIoUartDebugStopBits;
 
-/** Offset 0x062D - Serial Io Uart Debug Data Bits
+/** Offset 0x060D - Serial Io Uart Debug Data Bits
   Set default word length. 0: Default, 5,6,7,8
   5:5BITS, 6:6BITS, 7:7BITS, 8:8BITS
 **/
   UINT8                       SerialIoUartDebugDataBits;
 
-/** Offset 0x062E - IMGU CLKOUT Configuration
+/** Offset 0x060E - IMGU CLKOUT Configuration
   The configuration of IMGU CLKOUT, 0: Disable;<b>1: Enable</b>.
   $EN_DIS
 **/
   UINT8                       ImguClkOutEn[6];
 
-/** Offset 0x0634 - Enable/Disable SA IPU
+/** Offset 0x0614 - Enable/Disable SA IPU
   Enable(Default): Enable SA IPU, Disable: Disable SA IPU
   $EN_DIS
 **/
   UINT8                       SaIpuEnable;
 
-/** Offset 0x0635 - Disable and Lock Watch Dog Register
+/** Offset 0x0615 - Disable and Lock Watch Dog Register
   Set 1 to clear WDT status, then disable and lock WDT registers.
   $EN_DIS
 **/
   UINT8                       WdtDisableAndLock;
 
-/** Offset 0x0636 - Reserved
+/** Offset 0x0616 - Reserved
 **/
-  UINT8                       Reserved53[6];
+  UINT8                       Reserved42[2];
 
-/** Offset 0x063C - HECI Timeouts
+/** Offset 0x0618 - HECI Timeouts
   0: Disable, 1: Enable (Default) timeout check for HECI
   $EN_DIS
 **/
   UINT8                       HeciTimeouts;
 
-/** Offset 0x063D - HECI2 Interface Communication
+/** Offset 0x0619 - HECI2 Interface Communication
   Test, 0: disable, 1: enable, Adds or Removes HECI2 Device from PCI space.
   $EN_DIS
 **/
   UINT8                       HeciCommunication2;
 
-/** Offset 0x063E - Check HECI message before send
+/** Offset 0x061A - Check HECI message before send
   Test, 0: disable, 1: enable, Enable/Disable message check.
   $EN_DIS
 **/
   UINT8                       DisableMessageCheck;
 
-/** Offset 0x063F - Force ME DID Init Status
+/** Offset 0x061B - Force ME DID Init Status
   Test, 0: disable, 1: Success, 2: No Memory in Channels, 3: Memory Init Error, Set
   ME DID init stat value
   $EN_DIS
 **/
   UINT8                       DidInitStat;
 
-/** Offset 0x0640 - Enable KT device
+/** Offset 0x061C - Enable KT device
   Test, 0: POR, 1: enable, 2: disable, Enable or Disable KT device.
   $EN_DIS
 **/
   UINT8                       KtDeviceEnable;
 
-/** Offset 0x0641 - CPU Replaced Polling Disable
+/** Offset 0x061D - CPU Replaced Polling Disable
   Test, 0: disable, 1: enable, Setting this option disables CPU replacement polling loop
   $EN_DIS
 **/
   UINT8                       DisableCpuReplacedPolling;
 
-/** Offset 0x0642 - Skip CPU replacement check
+/** Offset 0x061E - Skip CPU replacement check
   Test, 0: disable, 1: enable, Setting this option to skip CPU replacement check
   $EN_DIS
 **/
   UINT8                       SkipCpuReplacementCheck;
 
-/** Offset 0x0643 - Skip MBP HOB
+/** Offset 0x061F - Skip MBP HOB
   Test, 0: disable, 1: enable, Enable/Disable sending MBP message and creating MBP Hob.
   $EN_DIS
 **/
   UINT8                       SkipMbpHob;
 
-/** Offset 0x0644 - Reserved
+/** Offset 0x0620 - Reserved
 **/
-  UINT8                       Reserved54[2];
+  UINT8                       Reserved43[2];
 
-/** Offset 0x0646 - ISA Serial Base selection
+/** Offset 0x0622 - ISA Serial Base selection
   Select ISA Serial Base address. Default is 0x3F8.
   0:0x3F8, 1:0x2F8
 **/
   UINT8                       PcdIsaSerialUartBase;
 
-/** Offset 0x0647 - PcdSerialDebugBaudRate
+/** Offset 0x0623 - PcdSerialDebugBaudRate
   Baud Rate for Serial Debug Messages. 3:9600, 4:19200, 6:56700, 7:115200.
   3:9600, 4:19200, 6:56700, 7:115200
 **/
   UINT8                       PcdSerialDebugBaudRate;
 
-/** Offset 0x0648 - Post Code Output Port
+/** Offset 0x0624 - Post Code Output Port
   This option configures Post Code Output Port
 **/
   UINT16                      PostCodeOutputPort;
 
-/** Offset 0x064A - Reserved
+/** Offset 0x0626 - Reserved
 **/
-  UINT8                       Reserved55[26];
+  UINT8                       Reserved44[22];
 
-/** Offset 0x0664 - Enable SMBus
+/** Offset 0x063C - Enable SMBus
   Enable/disable SMBus controller.
   $EN_DIS
 **/
   UINT8                       SmbusEnable;
 
-/** Offset 0x0665 - Enable SMBus ARP support
+/** Offset 0x063D - Enable SMBus ARP support
   Enable SMBus ARP support.
   $EN_DIS
 **/
   UINT8                       SmbusArpEnable;
 
-/** Offset 0x0666 - Number of RsvdSmbusAddressTable.
+/** Offset 0x063E - Number of RsvdSmbusAddressTable.
   The number of elements in the RsvdSmbusAddressTable.
 **/
   UINT8                       PchNumRsvdSmbusAddresses;
 
-/** Offset 0x0667 - Reserved
+/** Offset 0x063F - Reserved
 **/
-  UINT8                       Reserved56;
+  UINT8                       Reserved45;
 
-/** Offset 0x0668 - SMBUS Base Address
+/** Offset 0x0640 - SMBUS Base Address
   SMBUS Base Address (IO space).
 **/
   UINT16                      PchSmbusIoBase;
 
-/** Offset 0x066A - Enable SMBus Alert Pin
+/** Offset 0x0642 - Enable SMBus Alert Pin
   Enable SMBus Alert Pin.
   $EN_DIS
 **/
   UINT8                       PchSmbAlertEnable;
 
-/** Offset 0x066B - Reserved
+/** Offset 0x0643 - Reserved
 **/
-  UINT8                       Reserved57[13];
+  UINT8                       Reserved46[13];
 
-/** Offset 0x0678 - Smbus dynamic power gating
+/** Offset 0x0650 - Smbus dynamic power gating
   Disable or Enable Smbus dynamic power gating.
   $EN_DIS
 **/
   UINT8                       SmbusDynamicPowerGating;
 
-/** Offset 0x0679 - SMBUS SPD Write Disable
+/** Offset 0x0651 - SMBUS SPD Write Disable
   Set/Clear Smbus SPD Write Disable. 0: leave SPD Write Disable bit; 1: set SPD Write
   Disable bit. For security recommendations, SPD write disable bit must be set.
   $EN_DIS
 **/
   UINT8                       SmbusSpdWriteDisable;
 
-/** Offset 0x067A - Enable/Disable SA OcSupport
+/** Offset 0x0652 - Enable/Disable SA OcSupport
   Enable: Enable SA OcSupport, Disable(Default): Disable SA OcSupport
   $EN_DIS
 **/
   UINT8                       SaOcSupport;
 
-/** Offset 0x067B - Reserved
+/** Offset 0x0653 - Reserved
 **/
-  UINT8                       Reserved58[18];
+  UINT8                       Reserved47[18];
 
-/** Offset 0x068D - Over clocking support
+/** Offset 0x0665 - Over clocking support
   Over clocking support; <b>0: Disable</b>; 1: Enable
   $EN_DIS
 **/
   UINT8                       OcSupport;
 
-/** Offset 0x068E - Reserved
+/** Offset 0x0666 - Reserved
 **/
-  UINT8                       Reserved59;
+  UINT8                       Reserved48;
 
-/** Offset 0x068F - Realtime Memory Timing
+/** Offset 0x0667 - Realtime Memory Timing
   0(Default): Disabled, 1: Enabled. When enabled, it will allow the system to perform
   realtime memory timing changes after MRC_DONE.
   0: Disabled, 1: Enabled
 **/
   UINT8                       RealtimeMemoryTiming;
 
-/** Offset 0x0690 - core voltage override
+/** Offset 0x0668 - core voltage override
   The core voltage override which is applied to the entire range of cpu core frequencies.
   Valid Range 0 to 2000
 **/
   UINT16                      CoreVoltageOverride;
 
-/** Offset 0x0692 - Core Turbo voltage Offset
+/** Offset 0x066A - Core Turbo voltage Offset
   The voltage offset applied to the core while operating in turbo mode.Valid Range 0 to 1000
 **/
   UINT16                      CoreVoltageOffset;
 
-/** Offset 0x0694 - Core PLL voltage offset
+/** Offset 0x066C - Core PLL voltage offset
   Core PLL voltage offset. <b>0: No offset</b>. Range 0-15
 **/
   UINT8                       CorePllVoltageOffset;
 
-/** Offset 0x0695 - AVX2 Ratio Offset
+/** Offset 0x066D - AVX2 Ratio Offset
   0(Default)= No Offset. Range 0 - 31. Specifies number of bins to decrease AVX ratio
   vs. Core Ratio. Uses Mailbox MSR 0x150, cmd 0x1B.
 **/
   UINT8                       Avx2RatioOffset;
 
-/** Offset 0x0696 - BCLK Adaptive Voltage Enable
+/** Offset 0x066E - BCLK Adaptive Voltage Enable
   When enabled, the CPU V/F curves are aware of BCLK frequency when calculated. </b>0:
   Disable;<b> 1: Enable
   $EN_DIS
 **/
   UINT8                       BclkAdaptiveVoltage;
 
-/** Offset 0x0697 - Ring Downbin
+/** Offset 0x066F - Ring Downbin
   Ring Downbin enable/disable. When enabled, CPU will ensure the ring ratio is always
   lower than the core ratio.0: Disable; <b>1: Enable.</b>
   $EN_DIS
 **/
   UINT8                       RingDownBin;
 
-/** Offset 0x0698 - Row Hammer pTRR LFSR0 Mask
+/** Offset 0x0670 - Row Hammer pTRR LFSR0 Mask
   Row Hammer pTRR LFSR0 Mask, 1/2^(value)
 **/
   UINT8                       Lfsr0Mask;
 
-/** Offset 0x0699 - Margin Limit Check
+/** Offset 0x0671 - Margin Limit Check
   Margin Limit Check. Choose level of margin check
   0:Disable, 1:L1, 2:L2, 3:Both
 **/
   UINT8                       MarginLimitCheck;
 
-/** Offset 0x069A - Row Hammer pTRR LFSR1 Mask
+/** Offset 0x0672 - Row Hammer pTRR LFSR1 Mask
   Row Hammer pTRR LFSR1 Mask, 1/2^(value)
 **/
   UINT8                       Lfsr1Mask;
 
-/** Offset 0x069B - Reserved
+/** Offset 0x0673 - Reserved
 **/
-  UINT8                       Reserved60[2];
+  UINT8                       Reserved49[2];
 
-/** Offset 0x069D - TjMax Offset
+/** Offset 0x0675 - TjMax Offset
   TjMax offset.Specified value here is clipped by pCode (125 - TjMax Offset) to support
   TjMax in the range of 62 to 115 deg Celsius. Valid Range 10 - 63
 **/
   UINT8                       TjMaxOffset;
 
-/** Offset 0x069E - Reserved
+/** Offset 0x0676 - Reserved
 **/
-  UINT8                      Reserved61[48];
+  UINT8                      Reserved50[48];
 
-/** Offset 0x06CE - Core VF Point Offset
+/** Offset 0x06A6 - Core VF Point Offset
   Array used to specifies the Core Voltage Offset applied to the each selected VF
   Point. This voltage is specified in millivolts.
 **/
   UINT16                      CoreVfPointOffset[15];
 
-/** Offset 0x06EC - Core VF Point Offset Prefix
+/** Offset 0x06C4 - Core VF Point Offset Prefix
   Sets the CoreVfPointOffset value as positive or negative for corresponding core
   VF Point; <b>0: Positive </b>; 1: Negative.
   0:Positive, 1:Negative
 **/
   UINT8                       CoreVfPointOffsetPrefix[15];
 
-/** Offset 0x06FB - Core VF Point Ratio
+/** Offset 0x06D3 - Core VF Point Ratio
   Array for the each selected Core VF Point to display the ration.
 **/
   UINT8                       CoreVfPointRatio[15];
 
-/** Offset 0x070A - Reserved
+/** Offset 0x06E2 - Reserved
 **/
-  UINT8                       Reserved62[26];
+  UINT8                       Reserved51[26];
 
-/** Offset 0x0724 - Per Core Max Ratio override
+/** Offset 0x06FC - Per Core Max Ratio override
   Enable or disable Per Core PState OC supported by writing OCMB 0x1D to program new
   favored core ratio to each Core. <b>0: Disable</b>, 1: enable
   $EN_DIS
 **/
   UINT8                       PerCoreRatioOverride;
 
-/** Offset 0x0725 - Reserved
+/** Offset 0x06FD - Reserved
 **/
-  UINT8                       Reserved63[25];
+  UINT8                       Reserved52[25];
 
-/** Offset 0x073E - Per Core Current Max Ratio
+/** Offset 0x0716 - Per Core Current Max Ratio
   Array for the Per Core Max Ratio
 **/
   UINT8                       PerCoreRatio[8];
 
-/** Offset 0x0746 - Reserved
+/** Offset 0x071E - Reserved
 **/
-  UINT8                       Reserved64[8];
+  UINT8                       Reserved53[8];
 
-/** Offset 0x074E - Pvd Ratio Threshold for SOC/CPU die
+/** Offset 0x0726 - Pvd Ratio Threshold for SOC/CPU die
   Array of Pvd Ratio Threshold for SOC/CPU die is the threshold value for input ratio
   (P0 to Pn) to select the multiplier so that the output is within the DCO frequency
   range. As per the die selected, this threshold is applied to SA and MC/CMI PLL
@@ -2113,63 +2077,63 @@ typedef struct {
 **/
   UINT8                       PvdRatioThreshold;
 
-/** Offset 0x074F - Reserved
+/** Offset 0x0727 - Reserved
 **/
-  UINT8                       Reserved65[65];
+  UINT8                       Reserved54[65];
 
-/** Offset 0x0790 - CPU BCLK OC Frequency
+/** Offset 0x0768 - CPU BCLK OC Frequency
   CPU BCLK OC Frequency in KHz units. 98000000Hz = 98MHz <b>0 - Auto</b>. Range is
   40Mhz-1000Mhz.
 **/
   UINT32                      CpuBclkOcFrequency;
 
-/** Offset 0x0794 - Reserved
+/** Offset 0x076C - Reserved
 **/
-  UINT8                      Reserved66[13];
+  UINT8                      Reserved55[13];
 
-/** Offset 0x07A1 - Avx2 Voltage Guardband Scaling Factor
+/** Offset 0x0779 - Avx2 Voltage Guardband Scaling Factor
   AVX2 Voltage Guardband Scale factor applied to AVX2 workloads. Range is 0-200 in
   1/100 units, where a value of 125 would apply a 1.25 scale factor.
 **/
   UINT8                       Avx2VoltageScaleFactor;
 
-/** Offset 0x07A2 - Ring PLL voltage offset
+/** Offset 0x077A - Ring PLL voltage offset
   Core PLL voltage offset. <b>0: No offset</b>. Range 0-15
 **/
   UINT8                       RingPllVoltageOffset;
 
-/** Offset 0x07A3 - Reserved
+/** Offset 0x077B - Reserved
 **/
-  UINT8                       Reserved67[5];
+  UINT8                       Reserved56[5];
 
-/** Offset 0x07A8 - Enable PCH ISH Controller
+/** Offset 0x0780 - Enable PCH ISH Controller
   0: Disable, 1: Enable (Default) ISH Controller
   $EN_DIS
 **/
   UINT8                       PchIshEnable;
 
-/** Offset 0x07A9 - Reserved
+/** Offset 0x0781 - Reserved
 **/
-  UINT8                       Reserved68;
+  UINT8                       Reserved57;
 
-/** Offset 0x07AA - BiosSize
+/** Offset 0x0782 - BiosSize
   The size of the BIOS region of the IFWI. Used if FspmUpd->FspmConfig.BiosGuard !=
   0. If BiosGuard is enabled, MRC will increase the size of the DPR (DMA Protected
   Range) so that a BIOS Update Script can be stored in the DPR.
 **/
   UINT16                      BiosSize;
 
-/** Offset 0x07AC - BiosGuard
+/** Offset 0x0784 - BiosGuard
   Enable/Disable. 0: Disable, Enable/Disable BIOS Guard feature, 1: enable
   $EN_DIS
 **/
   UINT8                       BiosGuard;
 
-/** Offset 0x07AD
+/** Offset 0x0785
 **/
   UINT8                       BiosGuardToolsInterface;
 
-/** Offset 0x07AE - Txt
+/** Offset 0x0786 - Txt
   Enables utilization of additional hardware capabilities provided by Intel (R) Trusted
   Execution Technology. Changes require a full power cycle to take effect. <b>0:
   Disable</b>, 1: Enable
@@ -2177,318 +2141,415 @@ typedef struct {
 **/
   UINT8                       Txt;
 
-/** Offset 0x07AF - Skip Stop PBET Timer Enable/Disable
+/** Offset 0x0787 - Skip Stop PBET Timer Enable/Disable
   Skip Stop PBET Timer; <b>0: Disable</b>; 1: Enable
   $EN_DIS
 **/
   UINT8                       SkipStopPbet;
 
-/** Offset 0x07B0 - Reserved
+/** Offset 0x0788 - Reserved
 **/
-  UINT8                       Reserved69[38];
+  UINT8                       Reserved58[3];
 
-/** Offset 0x07D6 - BIST on Reset
+/** Offset 0x078B - MKTME Key-Id Bits Override Enable
+  Configure Trust Domain Extension (TDX) to isolate VMs from Virtual-Machine Manager
+  (VMM)/hypervisor <b>0: Disable</b>; 1: Enable.
+  $EN_DIS
+**/
+  UINT8                       GenerateNewTmeKey;
+
+/** Offset 0x078C - Reserved
+**/
+  UINT8                       Reserved59[4];
+
+/** Offset 0x0790 - TME Exclude Base Address
+  TME Exclude Base Address.
+**/
+  UINT64                      TmeExcludeBase;
+
+/** Offset 0x0798 - TME Exclude Size Value
+  TME Exclude Size Value.
+**/
+  UINT64                      TmeExcludeSize;
+
+/** Offset 0x07A0 - Reserved
+**/
+  UINT8                      Reserved60[14];
+
+/** Offset 0x07AE - BIST on Reset
   Enable/Disable BIST (Built-In Self Test) on reset. <b>0: Disable</b>; 1: Enable.
   $EN_DIS
 **/
   UINT8                       BistOnReset;
 
-/** Offset 0x07D7 - Reserved
+/** Offset 0x07AF - Reserved
 **/
-  UINT8                       Reserved70;
+  UINT8                       Reserved61;
 
-/** Offset 0x07D8 - Enable or Disable VMX
+/** Offset 0x07B0 - Enable or Disable VMX
   Enable or Disable VMX, When enabled, a VMM can utilize the additional hardware capabilities
   provided by Vanderpool Technology. 0: Disable; <b>1: Enable</b>.
   $EN_DIS
 **/
   UINT8                       VmxEnable;
 
-/** Offset 0x07D9 - Processor Early Power On Configuration FCLK setting
+/** Offset 0x07B1 - Processor Early Power On Configuration FCLK setting
   FCLK frequency can take values of 400MHz, 800MHz and 1GHz. <b>0: 800 MHz (ULT/ULX)</b>.
   <b>1: 1 GHz (DT/Halo)</b>. Not supported on ULT/ULX.- 2: 400 MHz. - 3: Reserved
   0:800 MHz, 1: 1 GHz, 2: 400 MHz, 3: Reserved
 **/
   UINT8                       FClkFrequency;
 
-/** Offset 0x07DA - Enable CPU CrashLog
+/** Offset 0x07B2 - Enable CPU CrashLog
   Enable or Disable CPU CrashLog; 0: Disable; <b>1: Enable</b>.
   $EN_DIS
 **/
   UINT8                       CpuCrashLogEnable;
 
-/** Offset 0x07DB - Enable or Disable TME
+/** Offset 0x07B3 - Enable or Disable TME
   Configure Total Memory Encryption (TME) to protect DRAM data from physical attacks.
   <b>0: Disable</b>; 1: Enable.
   $EN_DIS
 **/
   UINT8                       TmeEnable;
 
-/** Offset 0x07DC - CPU Run Control
+/** Offset 0x07B4 - CPU Run Control
   Enable, Disable or Do not configure CPU Run Control; 0: Disable; 1: Enable ; <b>2:
   No Change</b>
   0:Disabled, 1:Enabled, 2:No Change
 **/
   UINT8                       DebugInterfaceEnable;
 
-/** Offset 0x07DD - CPU Run Control Lock
+/** Offset 0x07B5 - CPU Run Control Lock
   Lock or Unlock CPU Run Control; 0: Disable; <b>1: Enable</b>.
   $EN_DIS
 **/
   UINT8                       DebugInterfaceLockEnable;
 
-/** Offset 0x07DE - Enable CPU CrashLog GPRs dump
+/** Offset 0x07B6 - Enable CPU CrashLog GPRs dump
   Enable or Disable CPU CrashLog GPRs dump; <b>0: Disable</b>; 1: Enable; 2: Only
   disable Smm GPRs dump
   0:Disabled, 1:Enabled, 2:Only Smm GPRs Disabled
 **/
   UINT8                       CrashLogGprs;
 
-/** Offset 0x07DF - Over clocking Lock
+/** Offset 0x07B7 - Over clocking Lock
   Lock Overclocking. 0: Disable; <b>1: Enable</b>
   $EN_DIS
 **/
   UINT8                       OcLock;
 
-/** Offset 0x07E0 - CPU ratio value
+/** Offset 0x07B8 - CPU ratio value
   This value must be between Max Efficiency Ratio (LFM) and Maximum non-turbo ratio
   set by Hardware (HFM). Valid Range 0 to 63.
 **/
   UINT8                       CpuRatio;
 
-/** Offset 0x07E1 - Number of active big cores
+/** Offset 0x07B9 - Number of active big cores
   Number of P-cores to enable in each processor package. Note: Number of P-Cores and
   E-Cores are looked at together. When both are {0,0
   0:Disable all big cores, 1:1, 2:2, 3:3, 0xFF:Active all big cores
 **/
   UINT8                       ActiveCoreCount;
 
-/** Offset 0x07E2 - Reserved
+/** Offset 0x07BA - Reserved
 **/
-  UINT8                       Reserved71[6];
+  UINT8                       Reserved62[6];
 
-/** Offset 0x07E8 - PrmrrSize
+/** Offset 0x07C0 - PrmrrSize
   Enable/Disable. 0: Disable, define default value of PrmrrSize , 1: enable
 **/
   UINT32                      PrmrrSize;
 
-/** Offset 0x07EC - Tseg Size
+/** Offset 0x07C4 - Tseg Size
   Size of SMRAM memory reserved. 0x400000 for Release build and 0x1000000 for Debug build
   0x0400000:4MB, 0x01000000:16MB
 **/
   UINT32                      TsegSize;
 
-/** Offset 0x07F0 - SmmRelocationEnable Enable
+/** Offset 0x07C8 - SmmRelocationEnable Enable
   Enable or Disable SmmRelocationEnable. <b>0: Disable</b>, 1:Enable
   $EN_DIS
 **/
   UINT8                       SmmRelocationEnable;
 
-/** Offset 0x07F1 - TCC Activation Offset
+/** Offset 0x07C9 - TCC Activation Offset
   TCC Activation Offset. Offset from factory set TCC activation temperature at which
   the Thermal Control Circuit must be activated. TCC will be activated at TCC Activation
   Temperature, in volts. <b>Default = 0h</b>.
 **/
   UINT8                       TccActivationOffset;
 
-/** Offset 0x07F2 - Reserved
+/** Offset 0x07CA - Reserved
 **/
-  UINT8                       Reserved72[98];
+  UINT8                       Reserved63[98];
 
-/** Offset 0x0854 - SinitMemorySize
+/** Offset 0x082C - SinitMemorySize
   Enable/Disable. 0: Disable, define default value of SinitMemorySize , 1: enable
 **/
   UINT32                      SinitMemorySize;
 
-/** Offset 0x0858 - TxtDprMemoryBase
+/** Offset 0x0830 - TxtDprMemoryBase
   Enable/Disable. 0: Disable, define default value of TxtDprMemoryBase , 1: enable
 **/
   UINT64                      TxtDprMemoryBase;
 
-/** Offset 0x0860 - TxtHeapMemorySize
+/** Offset 0x0838 - TxtHeapMemorySize
   Enable/Disable. 0: Disable, define default value of TxtHeapMemorySize , 1: enable
 **/
   UINT32                      TxtHeapMemorySize;
 
-/** Offset 0x0864 - TxtDprMemorySize
+/** Offset 0x083C - TxtDprMemorySize
   Reserve DPR memory size (0-255) MB. 0: Disable, define default value of TxtDprMemorySize
   , 1: enable
 **/
   UINT32                      TxtDprMemorySize;
 
-/** Offset 0x0868 - TxtLcpPdBase
+/** Offset 0x0840 - TxtLcpPdBase
   Enable/Disable. 0: Disable, define default value of TxtLcpPdBase , 1: enable
 **/
   UINT64                      TxtLcpPdBase;
 
-/** Offset 0x0870 - TxtLcpPdSize
+/** Offset 0x0848 - TxtLcpPdSize
   Enable/Disable. 0: Disable, define default value of TxtLcpPdSize , 1: enable
 **/
   UINT64                      TxtLcpPdSize;
 
-/** Offset 0x0878 - BiosAcmBase
+/** Offset 0x0850 - BiosAcmBase
   Enable/Disable. 0: Disable, define default value of BiosAcmBase , 1: enable
 **/
   UINT64                      BiosAcmBase;
 
-/** Offset 0x0880 - BiosAcmSize
+/** Offset 0x0858 - BiosAcmSize
   Enable/Disable. 0: Disable, define default value of BiosAcmSize , 1: enable
 **/
   UINT32                      BiosAcmSize;
 
-/** Offset 0x0884 - ApStartupBase
+/** Offset 0x085C - ApStartupBase
   Enable/Disable. 0: Disable, define default value of BiosAcmBase , 1: enable
 **/
   UINT32                      ApStartupBase;
 
-/** Offset 0x0888 - TgaSize
+/** Offset 0x0860 - TgaSize
   Enable/Disable. 0: Disable, define default value of TgaSize , 1: enable
 **/
   UINT32                      TgaSize;
 
-/** Offset 0x088C - IsTPMPresence
+/** Offset 0x0864 - IsTPMPresence
   IsTPMPresence default values
 **/
   UINT8                       IsTPMPresence;
 
-/** Offset 0x088D - Reserved
+/** Offset 0x0865 - Acoustic Noise Mitigation feature
+  Enabling this option will help mitigate acoustic noise on certain SKUs when the
+  CPU is in deeper C state. <b>0: Disabled</b>; 1: Enabled
+  $EN_DIS
 **/
-  UINT8                       Reserved73[157];
+  UINT8                       AcousticNoiseMitigation;
 
-/** Offset 0x092A - Thermal Design Current enable/disable
+/** Offset 0x0866 - Reserved
+**/
+  UINT8                       Reserved64[2];
+
+/** Offset 0x0868 - Platform Power Pmax
+  PSYS PMax power, defined in 1/8 Watt increments. <b>0 - Auto</b> Specified in 1/8
+  Watt increments. Range 0-1024 Watts(0-8191). Value of 800 = 100W
+**/
+  UINT16                      PsysPmax;
+
+/** Offset 0x086A - Reserved
+**/
+  UINT8                      Reserved65[12];
+
+/** Offset 0x0876 - AcLoadline
+  AC Loadline defined in 1/100 mOhms. A value of 100 = 1.00 mOhm, and 1255 = 12.55
+  mOhm. Range is 0-6249 (0-62.49 mOhms). 0 = AUTO/HW default. [0] for IA, [1] for
+  GT, [2] for SA, [3] through [5] are Reserved.
+**/
+  UINT16                      AcLoadline[6];
+
+/** Offset 0x0882 - DcLoadline
+  DC Loadline defined in 1/100 mOhms. A value of 100 = 1.00 mOhm, and 1255 = 12.55
+  mOhm. Range is 0-6249 (0-62.49 mOhms). 0 = AUTO/HW default. [0] for IA, [1] for
+  GT, [2] for SA, [3] through [5] are Reserved.
+**/
+  UINT16                      DcLoadline[6];
+
+/** Offset 0x088E - Reserved
+**/
+  UINT8                      Reserved66[116];
+
+/** Offset 0x0902 - Thermal Design Current enable/disable
   Thermal Design Current enable/disable; <b>0: Disable</b>; 1: Enable. [0] for IA,
   [1] for GT, [2] for SA, [3] for atom, [4]-[5] are Reserved.
 **/
   UINT8                       TdcEnable[6];
 
-/** Offset 0x0930 - Reserved
+/** Offset 0x0908 - Reserved
 **/
-  UINT8                       Reserved74[24];
+  UINT8                       Reserved67[6];
 
-/** Offset 0x0948 - Thermal Design Current time window
+/** Offset 0x090E - Disable Fast Slew Rate for Deep Package C States for VR domains
+  This option needs to be configured to reduce acoustic noise during deeper C states.
+  False: Don't disable Fast ramp during deeper C states; True: Disable Fast ramp
+  during deeper C state. [0] for IA, [1] for GT, [2] for SA, [3] through [5] are
+  Reserved. <b>0: False</b>; 1: True
+  $EN_DIS
+**/
+  UINT8                       FastPkgCRampDisable[6];
+
+/** Offset 0x0914 - Slew Rate configuration for Deep Package C States for VR domains
+  Set VR IA/GT/SA Slow Slew Rate for Deep Package C State ramp time; Slow slew rate
+  equals to Fast divided by number, the number is 2, 4, 8, 16 to slow down the slew
+  rate to help minimize acoustic noise; divide by 16 is disabled for GT/SA. <b>0:
+  Fast/2</b>; 1: Fast/4; 2: Fast/8; 3: Fast/16; 0xFF: Ignore the configuration
+  0: Fast/2, 1: Fast/4, 2: Fast/8, 3: Fast/16, 0xFF: Ignore the configuration
+**/
+  UINT8                       SlowSlewRate[6];
+
+/** Offset 0x091A - Reserved
+**/
+  UINT8                       Reserved68[6];
+
+/** Offset 0x0920 - Thermal Design Current time window
   Auto = 0 is default. Range is from 1ms to 448s. <b>0: Auto</b>. [0] for IA, [1]
   for GT, [2] for SA, [3] for atom, [4]-[5] are Reserved.
 **/
   UINT32                      TdcTimeWindow[6];
 
-/** Offset 0x0960 - Reserved
+/** Offset 0x0938 - Reserved
 **/
-  UINT8                       Reserved75[8];
+  UINT8                       Reserved69[8];
 
-/** Offset 0x0968 - DLVR RFI Enable
+/** Offset 0x0940 - DLVR RFI Enable
   Enable/Disable DLVR RFI frequency hopping. 0: Disable; <b>1: Enable</b>.
   $EN_DIS
 **/
   UINT8                       DlvrRfiEnable;
 
-/** Offset 0x0969 - Reserved
+/** Offset 0x0941 - Reserved
 **/
-  UINT8                       Reserved76[25];
+  UINT8                       Reserved70[13];
 
-/** Offset 0x0982 - Enable/Disable VR FastVmode. The VR will initiate reactive protection if Fast Vmode is enabled.
+/** Offset 0x094E - VR Fast Vmode ICC Limit support
+  Voltage Regulator Fast Vmode ICC Limit. A value of 400 = 100A. A value of 0 corresponds
+  to feature disabled (no reactive protection). This value represents the current
+  threshold where the VR would initiate reactive protection if Fast Vmode is enabled.
+  The value is represented in 1/4 A increments. Range 0-2040. [0] for IA, [1] for
+  GT, [2] for SA, [3] through [5] are Reserved.
+**/
+  UINT16                      IccLimit[6];
+
+/** Offset 0x095A - Enable/Disable VR FastVmode. The VR will initiate reactive protection if Fast Vmode is enabled.
   Enable/Disable VR FastVmode; <b>0: Disable</b>; 1: Enable.For all VR by domain
   0: Disable, 1: Enable
 **/
   UINT8                       EnableFastVmode[6];
 
-/** Offset 0x0988 - Reserved
+/** Offset 0x0960 - Enable/Disable CEP
+  Control for enabling/disabling CEP (Current Excursion Protection). <b>0: Disable</b>; 1: Enable
+  0: Disable, 1: Enable
 **/
-  UINT8                      Reserved77[26];
+  UINT8                       CepEnable[6];
 
-/** Offset 0x09A2 - PCH Port80 Route
+/** Offset 0x0966 - Reserved
+**/
+  UINT8                       Reserved71[28];
+
+/** Offset 0x0982 - PCH Port80 Route
   Control where the Port 80h cycles are sent, 0: LPC; 1: PCI.
   $EN_DIS
 **/
   UINT8                       PchPort80Route;
 
-/** Offset 0x09A3 - GPIO Override
+/** Offset 0x0983 - GPIO Override
   Gpio Override Level - FSP will not configure any GPIOs and rely on GPIO setings
   before moved to FSP. Available configurations 0: Disable; 1: Level 1 - Skips GPIO
   configuration in PEI/FSPM/FSPT phase;2: Level 2 - Reserved for future use
 **/
   UINT8                       GpioOverride;
 
-/** Offset 0x09A4 - Reserved
+/** Offset 0x0984 - Reserved
 **/
-  UINT8                       Reserved78[4];
+  UINT8                       Reserved72[4];
 
-/** Offset 0x09A8 - PMR Size
+/** Offset 0x0988 - PMR Size
   Size of PMR memory buffer. 0x400000 for normal boot and 0x200000 for S3 boot
 **/
   UINT32                      DmaBufferSize;
 
-/** Offset 0x09AC - The policy for VTd driver behavior
+/** Offset 0x098C - The policy for VTd driver behavior
   BIT0: Enable IOMMU during boot, BIT1: Enable IOMMU when transfer control to OS
 **/
   UINT8                       PreBootDmaMask;
 
-/** Offset 0x09AD - State of DMA_CONTROL_GUARANTEE bit in the DMAR table
+/** Offset 0x098D - State of DMA_CONTROL_GUARANTEE bit in the DMAR table
   0=Disable/Clear, 1=Enable/Set
   $EN_DIS
 **/
   UINT8                       DmaControlGuarantee;
 
-/** Offset 0x09AE - Disable VT-d
+/** Offset 0x098E - Disable VT-d
   0=Enable/FALSE(VT-d enabled), 1=Disable/TRUE (VT-d disabled)
   $EN_DIS
 **/
   UINT8                       VtdDisable;
 
-/** Offset 0x09AF - Reserved
+/** Offset 0x098F - Reserved
 **/
-  UINT8                       Reserved79;
+  UINT8                       Reserved73;
 
-/** Offset 0x09B0 - Base addresses for VT-d function MMIO access
+/** Offset 0x0990 - Base addresses for VT-d function MMIO access
   Base addresses for VT-d MMIO access per VT-d engine
 **/
   UINT32                      VtdBaseAddress[9];
 
-/** Offset 0x09D4 - Reserved
+/** Offset 0x09B4 - Reserved
 **/
-  UINT8                       Reserved80[20];
+  UINT8                       Reserved74[20];
 
-/** Offset 0x09E8 - MMIO Size
+/** Offset 0x09C8 - MMIO Size
   Size of MMIO space reserved for devices. 0(Default)=Auto, non-Zero=size in MB
 **/
   UINT16                      MmioSize;
 
-/** Offset 0x09EA - MMIO size adjustment for AUTO mode
+/** Offset 0x09CA - MMIO size adjustment for AUTO mode
   Positive number means increasing MMIO size, Negative value means decreasing MMIO
   size: 0 (Default)=no change to AUTO mode MMIO size
 **/
   UINT16                      MmioSizeAdjustment;
 
-/** Offset 0x09EC - Reserved
+/** Offset 0x09CC - Reserved
 **/
-  UINT8                      Reserved81[36];
+  UINT8                      Reserved75[36];
 
-/** Offset 0x0A10 - Enable above 4GB MMIO resource support
+/** Offset 0x09F0 - Enable above 4GB MMIO resource support
   Enable/disable above 4GB MMIO resource support
   $EN_DIS
 **/
   UINT8                       EnableAbove4GBMmio;
 
-/** Offset 0x0A11 - Enable/Disable SA CRID
+/** Offset 0x09F1 - Enable/Disable SA CRID
   Enable: SA CRID, Disable (Default): SA CRID
   $EN_DIS
 **/
   UINT8                       CridEnable;
 
-/** Offset 0x0A12 - Reserved
+/** Offset 0x09F2 - Reserved
 **/
-  UINT8                       Reserved82[10];
+  UINT8                       Reserved76[10];
 
-/** Offset 0x0A1C - Enable/Disable CrashLog Device
+/** Offset 0x09FC - Enable/Disable CrashLog Device
   Enable or Disable CrashLog/Telemetry Device  0- Disable, <b>1- Enable</b>
   $EN_DIS
 **/
   UINT32                      CpuCrashLogDevice;
 
-/** Offset 0x0A20 - Reserved
+/** Offset 0x0A00 - Reserved
 **/
-  UINT8                      Reserved83[20];
+  UINT8                      Reserved77[20];
 
-/** Offset 0x0A34 - Platform Debug Option
+/** Offset 0x0A14 - Platform Debug Option
   Enabled Trace active: TraceHub is enabled and trace is active, blocks s0ix.\n
   \n
   Enabled Trace ready: TraceHub is enabled and allowed S0ix.\n
@@ -2501,122 +2562,122 @@ typedef struct {
 **/
   UINT8                       PlatformDebugOption;
 
-/** Offset 0x0A35 - Reserved
+/** Offset 0x0A15 - Reserved
 **/
-  UINT8                       Reserved84[14];
+  UINT8                       Reserved78[14];
 
-/** Offset 0x0A43 - Program GPIOs for LFP on DDI port-A device
+/** Offset 0x0A23 - Program GPIOs for LFP on DDI port-A device
   0=Disabled,1(Default)=eDP, 2=MIPI DSI
   0:Disabled, 1:eDP, 2:MIPI DSI
 **/
   UINT8                       DdiPortAConfig;
 
-/** Offset 0x0A44 - Reserved
+/** Offset 0x0A24 - Reserved
 **/
-  UINT8                      Reserved85[2];
+  UINT8                      Reserved79[2];
 
-/** Offset 0x0A46 - Program GPIOs for LFP on DDI port-B device
+/** Offset 0x0A26 - Program GPIOs for LFP on DDI port-B device
   0(Default)=Disabled,1=eDP, 2=MIPI DSI
   0:Disabled, 1:eDP, 2:MIPI DSI
 **/
   UINT8                       DdiPortBConfig;
 
-/** Offset 0x0A47 - Enable or disable HPD of DDI port A
+/** Offset 0x0A27 - Enable or disable HPD of DDI port A
   0(Default)=Disable, 1=Enable
   $EN_DIS
 **/
   UINT8                       DdiPortAHpd;
 
-/** Offset 0x0A48 - Enable or disable HPD of DDI port B
+/** Offset 0x0A28 - Enable or disable HPD of DDI port B
   0=Disable, 1(Default)=Enable
   $EN_DIS
 **/
   UINT8                       DdiPortBHpd;
 
-/** Offset 0x0A49 - Enable or disable HPD of DDI port C
+/** Offset 0x0A29 - Enable or disable HPD of DDI port C
   0(Default)=Disable, 1=Enable
   $EN_DIS
 **/
   UINT8                       DdiPortCHpd;
 
-/** Offset 0x0A4A - Enable or disable HPD of DDI port 1
+/** Offset 0x0A2A - Enable or disable HPD of DDI port 1
   0=Disable, 1(Default)=Enable
   $EN_DIS
 **/
   UINT8                       DdiPort1Hpd;
 
-/** Offset 0x0A4B - Enable or disable HPD of DDI port 2
+/** Offset 0x0A2B - Enable or disable HPD of DDI port 2
   0(Default)=Disable, 1=Enable
   $EN_DIS
 **/
   UINT8                       DdiPort2Hpd;
 
-/** Offset 0x0A4C - Enable or disable HPD of DDI port 3
+/** Offset 0x0A2C - Enable or disable HPD of DDI port 3
   0(Default)=Disable, 1=Enable
   $EN_DIS
 **/
   UINT8                       DdiPort3Hpd;
 
-/** Offset 0x0A4D - Enable or disable HPD of DDI port 4
+/** Offset 0x0A2D - Enable or disable HPD of DDI port 4
   0(Default)=Disable, 1=Enable
   $EN_DIS
 **/
   UINT8                       DdiPort4Hpd;
 
-/** Offset 0x0A4E - Enable or disable DDC of DDI port A
+/** Offset 0x0A2E - Enable or disable DDC of DDI port A
   0(Default)=Disable, 1=Enable
   $EN_DIS
 **/
   UINT8                       DdiPortADdc;
 
-/** Offset 0x0A4F - Enable or disable DDC of DDI port B
+/** Offset 0x0A2F - Enable or disable DDC of DDI port B
   0=Disable, 1(Default)=Enable
   $EN_DIS
 **/
   UINT8                       DdiPortBDdc;
 
-/** Offset 0x0A50 - Enable or disable DDC of DDI port C
+/** Offset 0x0A30 - Enable or disable DDC of DDI port C
   0(Default)=Disable, 1=Enable
   $EN_DIS
 **/
   UINT8                       DdiPortCDdc;
 
-/** Offset 0x0A51 - Enable DDC setting of DDI Port 1
+/** Offset 0x0A31 - Enable DDC setting of DDI Port 1
   0(Default)=Disable, 1=Enable
   $EN_DIS
 **/
   UINT8                       DdiPort1Ddc;
 
-/** Offset 0x0A52 - Enable DDC setting of DDI Port 2
+/** Offset 0x0A32 - Enable DDC setting of DDI Port 2
   0(Default)=Disable, 1=Enable
   $EN_DIS
 **/
   UINT8                       DdiPort2Ddc;
 
-/** Offset 0x0A53 - Enable DDC setting of DDI Port 3
+/** Offset 0x0A33 - Enable DDC setting of DDI Port 3
   0(Default)=Disable, 1=Enable
   $EN_DIS
 **/
   UINT8                       DdiPort3Ddc;
 
-/** Offset 0x0A54 - Enable DDC setting of DDI Port 4
+/** Offset 0x0A34 - Enable DDC setting of DDI Port 4
   0(Default)=Disable, 1=Enable
   $EN_DIS
 **/
   UINT8                       DdiPort4Ddc;
 
-/** Offset 0x0A55 - Reserved
+/** Offset 0x0A35 - Reserved
 **/
-  UINT8                       Reserved86[3];
+  UINT8                       Reserved80[3];
 
-/** Offset 0x0A58 - Temporary MMIO address for GMADR
+/** Offset 0x0A38 - Temporary MMIO address for GMADR
   The reference code will use this as Temporary MMIO address space to access GMADR
   Registers.Platform should provide conflict free Temporary MMIO Range: GmAdr to
   (GmAdr + 256MB). Default is (PciExpressBaseAddress - 256MB) to (PciExpressBaseAddress - 0x1)
 **/
   UINT64                      LMemBar;
 
-/** Offset 0x0A60 - Temporary MMIO address for GTTMMADR
+/** Offset 0x0A40 - Temporary MMIO address for GTTMMADR
   The reference code will use this as Temporary MMIO address space to access GTTMMADR
   Registers.Platform should provide conflict free Temporary MMIO Range: GttMmAdr
   to (GttMmAdr + 2MB MMIO + 6MB Reserved + GttSize). Default is (GmAdr - (2MB MMIO
@@ -2624,104 +2685,164 @@ typedef struct {
 **/
   UINT64                      GttMmAdr;
 
-/** Offset 0x0A68 - Reserved
+/** Offset 0x0A48 - Reserved
 **/
-  UINT8                      Reserved87[2];
+  UINT8                      Reserved81[2];
 
-/** Offset 0x0A6A - Enable/Disable Memory Bandwidth Compression
+/** Offset 0x0A4A - Enable/Disable Memory Bandwidth Compression
   0=Disable, 1(Default)=Enable
   $EN_DIS
 **/
   UINT8                       MemoryBandwidthCompression;
 
-/** Offset 0x0A6B - Panel Power Enable
+/** Offset 0x0A4B - Panel Power Enable
   Control for enabling/disabling VDD force bit (Required only for early enabling of
   eDP panel). 0=Disable, 1(Default)=Enable
   $EN_DIS
 **/
   UINT8                       PanelPowerEnable;
 
-/** Offset 0x0A6C - Selection of the primary display device
+/** Offset 0x0A4C - Selection of the primary display device
   3(Default)=AUTO, 0=IGFX, 4=Hybrid Graphics
   3:AUTO, 0:IGFX, 4:HG
 **/
   UINT8                       PrimaryDisplay;
 
-/** Offset 0x0A6D - TCSS USB HOST (xHCI) Enable
+/** Offset 0x0A4D - Internal Graphics Data Stolen Memory GSM2
+  Size of memory preallocated for internal graphics GSM2.
+  0:2GB, 1:4GB, 2:6GB, 3:8GB, 4:10GB, 5:12GB, 6:14GB, 7:16GB, 8:18GB, 9:20GB, 10:22GB,
+  11:24GB, 12:26GB, 13:28GB, 14:30GB, 15:32GB, 0xFF:No Allocation
+**/
+  UINT8                       IGpuGsm2Size;
+
+/** Offset 0x0A4E - Reserved
+**/
+  UINT8                       Reserved82[2];
+
+/** Offset 0x0A50 - Intel Graphics VBT (Video BIOS Table) Size
+  Size of Internal Graphics VBT Image
+**/
+  UINT32                      VbtSize;
+
+/** Offset 0x0A54 - Reserved
+**/
+  UINT8                       Reserved83[4];
+
+/** Offset 0x0A58 - Graphics Configuration Ptr
+  Points to VBT
+**/
+  UINT64                      VbtPtr;
+
+/** Offset 0x0A60 - SOL Training Message Pointer
+  Points to SOL Message String
+**/
+  UINT64                      VgaMessage;
+
+/** Offset 0x0A68 - Platform LID Status for LFP Displays.
+  LFP Display Lid Status (LID_STATUS enum): 0 (Default): LidClosed, 1: LidOpen.
+  0: LidClosed, 1: LidOpen
+**/
+  UINT8                       LidStatus;
+
+/** Offset 0x0A69 - Control SOL VGA Initialition sequence
+  Initialise SOL Init
+  0x0: NO SOL VGA Init, 0x1: SOL VGA Init
+**/
+  UINT8                       VgaInitControl;
+
+/** Offset 0x0A6A - TCSS USB HOST (xHCI) Enable
   Set TCSS XHCI. 0:Disabled  1:Enabled - Must be enabled if xDCI is enabled below
   $EN_DIS
 **/
   UINT8                       TcssXhciEn;
 
-/** Offset 0x0A6E - Reserved
+/** Offset 0x0A6B - Reserved
 **/
-  UINT8                       Reserved88[4];
+  UINT8                       Reserved84[4];
 
-/** Offset 0x0A72 - TCSS Type C Port 0
+/** Offset 0x0A6F - TCSS Type C Port 0
   Set TCSS Type C Port 0 Type, Options are 0=DISABLE, 1=DP_ONLY, 2=NO_TBT, 3=NO_PCIE,
   7=FULL_FUN
   0:DISABLE, 1:DP_ONLY, 2:NO_TBT, 3: NO_PCIE, 7:FULL_FUN
 **/
   UINT8                       TcssPort0;
 
-/** Offset 0x0A73 - TCSS Type C Port 1
+/** Offset 0x0A70 - TCSS Type C Port 1
   Set TCSS Type C Port 1 Type, Options are 0=DISABLE, 1=DP_ONLY, 2=NO_TBT, 3=NO_PCIE,
   7=FULL_FUN
   0:DISABLE, 1:DP_ONLY, 2:NO_TBT, 3: NO_PCIE, 7:FULL_FUN
 **/
   UINT8                       TcssPort1;
 
-/** Offset 0x0A74 - TCSS Type C Port 2
+/** Offset 0x0A71 - TCSS Type C Port 2
   Set TCSS Type C Port 2 Type, Options are 0=DISABLE, 1=DP_ONLY, 2=NO_TBT, 3=NO_PCIE,
   7=FULL_FUN
   0:DISABLE, 1:DP_ONLY, 2:NO_TBT, 3: NO_PCIE, 7:FULL_FUN
 **/
   UINT8                       TcssPort2;
 
-/** Offset 0x0A75 - TCSS Type C Port 3
+/** Offset 0x0A72 - TCSS Type C Port 3
   Set TCSS Type C Port 3 Type, Options are 0=DISABLE, 1=DP_ONLY, 2=NO_TBT, 3=NO_PCIE,
   7=FULL_FUN
   0:DISABLE, 1:DP_ONLY, 2:NO_TBT, 3: NO_PCIE, 7:FULL_FUN
 **/
   UINT8                       TcssPort3;
 
-/** Offset 0x0A76 - Reserved
+/** Offset 0x0A73 - Reserved
 **/
-  UINT8                       Reserved89[2];
+  UINT8                       Reserved85;
 
-/** Offset 0x0A78 - TypeC port GPIO setting
+/** Offset 0x0A74 - TypeC port GPIO setting
   GPIO Pin number for Type C Aux orientation setting, use the GpioPad that is defined
   in GpioPinsXXX.h as argument.(XXX is platform name, Ex: Ptl = PantherLake)
 **/
   UINT32                      IomTypeCPortPadCfg[12];
 
-/** Offset 0x0AA8 - TCSS Aux Orientation Override Enable
+/** Offset 0x0AA4 - TCSS Aux Orientation Override Enable
   Bits 0, 2, ... 10 control override enables, bits 1, 3, ... 11 control overrides
 **/
   UINT16                      TcssAuxOri;
 
-/** Offset 0x0AAA - TCSS HSL Orientation Override Enable
+/** Offset 0x0AA6 - TCSS HSL Orientation Override Enable
   Bits 0, 2, ... 10 control override enables, bits 1, 3, ... 11 control overrides
 **/
   UINT16                      TcssHslOri;
 
-/** Offset 0x0AAC - CNVi DDR RFI Mitigation
+/** Offset 0x0AA8 - CNVi DDR RFI Mitigation
   Enable/Disable DDR RFI Mitigation. Default is ENABLE. 0: DISABLE, 1: ENABLE
   $EN_DIS
 **/
   UINT8                       CnviDdrRfim;
 
-/** Offset 0x0AAD - SOC Trace Hub Mode
+/** Offset 0x0AA9 - SOC Trace Hub Mode
   Enable/Disable SOC TraceHub
   $EN_DIS
 **/
   UINT8                       SocTraceHubMode;
 
-/** Offset 0x0AAE - Reserved
+/** Offset 0x0AAA - SOC Trace Hub Memory Region 0 buffer Size
+  Select size of memory region 0 buffer. Memory allocated by BIOS only applies to
+  ITH tool running on the host. For ITH tool running on the target, choose None/OS,
+  memory shall be allocated by tool. User should be cautious to choose the amount
+  of memory. If chosen size is larger than half of system memory, setup will automatically
+  rollback to default value.
+  0x00:1MB, 0x03:8MB, 0x06:64MB, 0x07:128MB, 0x08:256MB, 0x09:512MB, 0x0A:1GB, 0x0B:2GB,
+  0x0C:4GB, 0x0D:8GB, 0x0E:0MB
 **/
-  UINT8                      Reserved90[4];
+  UINT16                      SocTraceHubMemReg0Size;
 
-/** Offset 0x0AB2 - Internal Graphics Pre-allocated Memory
+/** Offset 0x0AAC - SOC Trace Hub Memory Region 0 buffer Size
+  Select size of memory region 1 buffer. Memory allocated by BIOS only applies to
+  ITH tool running on the host. For ITH tool running on the target, choose None/OS,
+  memory shall be allocated by tool. User should be cautious to choose the amount
+  of memory. If chosen size is larger than half of system memory, setup will automatically
+  rollback to default value.
+  0x00:1MB, 0x03:8MB, 0x06:64MB, 0x07:128MB, 0x08:256MB, 0x09:512MB, 0x0A:1GB, 0x0B:2GB,
+  0x0C:4GB, 0x0D:8GB, 0x0E:0MB
+**/
+  UINT16                      SocTraceHubMemReg1Size;
+
+/** Offset 0x0AAE - Internal Graphics Pre-allocated Memory
   Size of memory preallocated for internal graphics.
   0x00:0MB, 0x01:32MB, 0x02:64MB, 0x03:96MB, 0x04:128MB, 0xF0:4MB, 0xF1:8MB, 0xF2:12MB,
   0xF3:16MB, 0xF4:20MB, 0xF5:24MB, 0xF6:28MB, 0xF7:32MB, 0xF8:36MB, 0xF9:40MB, 0xFA:44MB,
@@ -2729,175 +2850,175 @@ typedef struct {
 **/
   UINT16                      IgdDvmt50PreAlloc;
 
-/** Offset 0x0AB4 - Internal Graphics
+/** Offset 0x0AB0 - Internal Graphics
   Enable/disable internal graphics.
   $EN_DIS
 **/
   UINT8                       InternalGraphics;
 
-/** Offset 0x0AB5 - Reserved
+/** Offset 0x0AB1 - Reserved
 **/
-  UINT8                       Reserved91[7];
+  UINT8                       Reserved86[7];
 
-/** Offset 0x0ABC - DynamicMemoryBoost
+/** Offset 0x0AB8 - DynamicMemoryBoost
   Enable/Disable Dynamic Memory Boost Feature. Only valid if SpdProfileSelected is
   an XMP Profile; otherwise ignored. <b>0=Disabled</b>, 1=Enabled.
   $EN_DIS
 **/
   UINT32                      DynamicMemoryBoost;
 
-/** Offset 0x0AC0 - RealtimeMemoryFrequency
+/** Offset 0x0ABC - RealtimeMemoryFrequency
   Enable/Disable Realtime Memory Frequency feature. Only valid if SpdProfileSelected
   is an XMP Profile; otherwise ignored. <b>0=Disabled</b>, 1=Enabled.
   $EN_DIS
 **/
   UINT32                      RealtimeMemoryFrequency;
 
-/** Offset 0x0AC4 - Reserved
+/** Offset 0x0AC0 - Reserved
 **/
-  UINT8                      Reserved92[9];
+  UINT8                      Reserved87[9];
 
-/** Offset 0x0ACD - Vref Offset
+/** Offset 0x0AC9 - Vref Offset
   Offset to be applied to DDRDATACH0_CR_DDRCRDATAOFFSETTRAIN.VrefOffset
   0xFA:-6, 0xFB:-5, 0xFC:-4, 0xFD:-3, 0xFE:-2, 0xFF:-1, 0:0, 1:+1, 2:+2, 3:+3, 4:+4,
   5:+5, 6:+6
 **/
   UINT8                       VrefOffset;
 
-/** Offset 0x0ACE - Reserved
+/** Offset 0x0ACA - Reserved
 **/
-  UINT8                       Reserved93[2];
+  UINT8                       Reserved88[2];
 
-/** Offset 0x0AD0 - tRRSG Delta
+/** Offset 0x0ACC - tRRSG Delta
   Delay between Read-to-Read commands in the same Bank Group. 0 - Auto. Signed TAT
   delta is (Value - 128). Input value range of [1..255] will give a TAT delta range
   of [-127..127]
 **/
   UINT8                       tRRSG;
 
-/** Offset 0x0AD1 - tRRDG Delta
+/** Offset 0x0ACD - tRRDG Delta
   Delay between Read-to-Read commands in different Bank Group. 0 - Auto. Signed TAT
   delta is (Value - 128). Input value range of [1..255] will give a TAT delta range
   of [-127..127]
 **/
   UINT8                       tRRDG;
 
-/** Offset 0x0AD2 - tRRDR Delta
+/** Offset 0x0ACE - tRRDR Delta
   Delay between Read-to-Read commands in different Ranks. 0 - Auto. Signed TAT delta
   is (Value - 128). Input value range of [1..255] will give a TAT delta range of
   [-127..127]
 **/
   UINT8                       tRRDR;
 
-/** Offset 0x0AD3 - tRRDD Delta
+/** Offset 0x0ACF - tRRDD Delta
   Delay between Read-to-Read commands in different DIMMs. 0 - Auto. Signed TAT delta
   is (Value - 128). Input value range of [1..255] will give a TAT delta range of
   [-127..127]
 **/
   UINT8                       tRRDD;
 
-/** Offset 0x0AD4 - tWRSG Delta
+/** Offset 0x0AD0 - tWRSG Delta
   Delay between Write-to-Read commands in the same Bank Group. 0 - Auto. Signed TAT
   delta is (Value - 128). Input value range of [1..255] will give a TAT delta range
   of [-127..127]
 **/
   UINT8                       tWRSG;
 
-/** Offset 0x0AD5 - tWRDG Delta
+/** Offset 0x0AD1 - tWRDG Delta
   Delay between Write-to-Read commands in different Bank Group. 0 - Auto. Signed TAT
   delta is (Value - 128). Input value range of [1..255] will give a TAT delta range
   of [-127..127]
 **/
   UINT8                       tWRDG;
 
-/** Offset 0x0AD6 - tWRDR Delta
+/** Offset 0x0AD2 - tWRDR Delta
   Delay between Write-to-Read commands in different Ranks. 0 - Auto. Signed TAT delta
   is (Value - 128). Input value range of [1..255] will give a TAT delta range of
   [-127..127]
 **/
   UINT8                       tWRDR;
 
-/** Offset 0x0AD7 - tWRDD Delta
+/** Offset 0x0AD3 - tWRDD Delta
   Delay between Write-to-Read commands in different DIMMs. 0 - Auto. Signed TAT delta
   is (Value - 128). Input value range of [1..255] will give a TAT delta range of
   [-127..127]
 **/
   UINT8                       tWRDD;
 
-/** Offset 0x0AD8 - tWWSG Delta
+/** Offset 0x0AD4 - tWWSG Delta
   Delay between Write-to-Write commands in the same Bank Group. 0 - Auto. Signed TAT
   delta is (Value - 128). Input value range of [1..255] will give a TAT delta range
   of [-127..127]
 **/
   UINT8                       tWWSG;
 
-/** Offset 0x0AD9 - tWWDG Delta
+/** Offset 0x0AD5 - tWWDG Delta
   Delay between Write-to-Write commands in different Bank Group. 0 - Auto. Signed
   TAT delta is (Value - 128). Input value range of [1..255] will give a TAT delta
   range of [-127..127]
 **/
   UINT8                       tWWDG;
 
-/** Offset 0x0ADA - tWWDR Delta
+/** Offset 0x0AD6 - tWWDR Delta
   Delay between Write-to-Write commands in different Ranks. 0 - Auto. Signed TAT delta
   is (Value - 128). Input value range of [1..255] will give a TAT delta range of
   [-127..127]
 **/
   UINT8                       tWWDR;
 
-/** Offset 0x0ADB - tWWDD Delta
+/** Offset 0x0AD7 - tWWDD Delta
   Delay between Write-to-Write commands in different DIMMs. 0 - Auto. Signed TAT delta
   is (Value - 128). Input value range of [1..255] will give a TAT delta range of
   [-127..127]
 **/
   UINT8                       tWWDD;
 
-/** Offset 0x0ADC - tRWSG Delta
+/** Offset 0x0AD8 - tRWSG Delta
   Delay between Read-to-Write commands in the same Bank Group. 0 - Auto. Signed TAT
   delta is (Value - 128). Input value range of [1..255] will give a TAT delta range
   of [-127..127]
 **/
   UINT8                       tRWSG;
 
-/** Offset 0x0ADD - tRWDG Delta
+/** Offset 0x0AD9 - tRWDG Delta
   Delay between Read-to-Write commands in different Bank Group. 0 - Auto. Signed TAT
   delta is (Value - 128). Input value range of [1..255] will give a TAT delta range
   of [-127..127]
 **/
   UINT8                       tRWDG;
 
-/** Offset 0x0ADE - tRWDR Delta
+/** Offset 0x0ADA - tRWDR Delta
   Delay between Read-to-Write commands in different Ranks. 0 - Auto. Signed TAT delta
   is (Value - 128). Input value range of [1..255] will give a TAT delta range of
   [-127..127]
 **/
   UINT8                       tRWDR;
 
-/** Offset 0x0ADF - tRWDD Delta
+/** Offset 0x0ADB - tRWDD Delta
   Delay between Read-to-Write commands in different DIMMs. 0 - Auto. Signed TAT delta
   is (Value - 128). Input value range of [1..255] will give a TAT delta range of
   [-127..127]
 **/
   UINT8                       tRWDD;
 
-/** Offset 0x0AE0 - Reserved
+/** Offset 0x0ADC - Reserved
 **/
-  UINT8                       Reserved94[13];
+  UINT8                       Reserved89[13];
 
-/** Offset 0x0AED - PPR ForceRepair
+/** Offset 0x0AE9 - PPR ForceRepair
   When Eanble, PPR will force repair some rows many times (90)
   $EN_DIS
 **/
   UINT8                       PprForceRepair;
 
-/** Offset 0x0AEE - PPR Repair Bank
+/** Offset 0x0AEA - PPR Repair Bank
   PPR repair Bank: User chooses to force repair specifc address
 **/
   UINT8                       PprRepairBank;
 
-/** Offset 0x0AEF - Reserved
+/** Offset 0x0AEB - Reserved
 **/
-  UINT8                       Reserved95[33];
+  UINT8                       Reserved90[53];
 } FSP_M_CONFIG;
 
 /** Fsp M UPD Configuration
@@ -2916,11 +3037,11 @@ typedef struct {
 **/
   FSP_M_CONFIG                FspmConfig;
 
-/** Offset 0x0B10
+/** Offset 0x0B20
 **/
-  UINT8                       UnusedUpdSpace55[6];
+  UINT8                       UnusedUpdSpace0[6];
 
-/** Offset 0x0B16
+/** Offset 0x0B26
 **/
   UINT16                      UpdTerminator;
 } FSPM_UPD;
diff --git a/src/vendorcode/intel/fsp/fsp2_0/pantherlake/FspsUpd.h b/src/vendorcode/intel/fsp/fsp2_0/pantherlake/FspsUpd.h
index 4617ec7fe4..a6dde65ef9 100644
--- a/src/vendorcode/intel/fsp/fsp2_0/pantherlake/FspsUpd.h
+++ b/src/vendorcode/intel/fsp/fsp2_0/pantherlake/FspsUpd.h
@@ -1,6 +1,6 @@
 /** @file
 
-Copyright (c) 2024, Intel Corporation. All rights reserved.<BR>
+Copyright (c) 2025, Intel Corporation. All rights reserved.<BR>
 
 Redistribution and use in source and binary forms, with or without modification,
 are permitted provided that the following conditions are met:
@@ -489,9 +489,14 @@ typedef struct {
 **/
   UINT16                      ITbtDmaLtr[2];
 
-/** Offset 0x0158 - Reserved
+/** Offset 0x0158 - ITbt Usb4CmMode value
+  ITbt Usb4CmMode value. 0:Firmware CM, 1:Software CM
 **/
-  UINT8                       Reserved14[16];
+  UINT8                       Usb4CmMode;
+
+/** Offset 0x0159 - Reserved
+**/
+  UINT8                       Reserved14[15];
 
 /** Offset 0x0168 - IEH Mode
   Integrated Error Handler Mode, 0: Bypass, 1: Enable
@@ -767,7 +772,16 @@ typedef struct {
 
 /** Offset 0x0259 - Reserved
 **/
-  UINT8                       Reserved17[27];
+  UINT8                       Reserved17[22];
+
+/** Offset 0x026F - Enable PCH ISH I3C pins assigned
+  Set if ISH I3C native pins are to be enabled by BIOS. 0: Disable; 1: Enable.
+**/
+  UINT8                       PchIshI3cEnable[2];
+
+/** Offset 0x0271 - Reserved
+**/
+  UINT8                       Reserved18[3];
 
 /** Offset 0x0274 - Power button debounce configuration
   Debounce time for PWRBTN in microseconds. For values not supported by HW, they will
@@ -822,9 +836,11 @@ typedef struct {
 **/
   UINT8                       PchPmWolEnableOverride;
 
-/** Offset 0x027F - Reserved
+/** Offset 0x027F - PCH Pm WoW lan Enable
+  Determine if WLAN wake from Sx, corresponds to the HOST_WLAN_PP_EN bit in the PWRM_CFG3 register.
+  $EN_DIS
 **/
-  UINT8                       Reserved18;
+  UINT8                       PchPmWoWlanEnable;
 
 /** Offset 0x0280 - PCH Pm Slp S3 Min Assert
   SLP_S3 Minimum Assertion Width Policy. Default is PchSlpS350ms.
@@ -1386,748 +1402,813 @@ typedef struct {
 **/
   UINT8                       PchSerialIoI2cPadsTermination[8];
 
-/** Offset 0x0F68 - Reserved
+/** Offset 0x0F68 - I3C Device Mode
+  Selects I3c operation mode. Available modes: 0:SerialIoI3cDisabled, 1:SerialIoI3cPci,
+  2:SerialIoI3cPhantom (only applicable to I3C1, controlls GPIO enabling)
 **/
-  UINT8                       Reserved30[148];
+  UINT8                       SerialIoI3cMode[3];
 
-/** Offset 0x0FFC - TypeC port GPIO setting
+/** Offset 0x0F6B - Reserved
+**/
+  UINT8                       Reserved30[48];
+
+/** Offset 0x0F9B - Enable VMD controller
+  Enable/disable to VMD controller.0: Disable; 1: Enable(Default)
+  $EN_DIS
+**/
+  UINT8                       VmdEnable;
+
+/** Offset 0x0F9C - Enable VMD Global Mapping
+  Enable/disable to VMD controller.0: Disable(Default); 1: Enable
+  $EN_DIS
+**/
+  UINT8                       VmdGlobalMapping;
+
+/** Offset 0x0F9D - Map port under VMD
+  Map/UnMap port under VMD
+  $EN_DIS
+**/
+  UINT8                       VmdPort[31];
+
+/** Offset 0x0FBC - Reserved
+**/
+  UINT8                       Reserved31[31];
+
+/** Offset 0x0FDB - VMD Port Device
+  VMD Root port device number.
+**/
+  UINT8                       VmdPortDev[31];
+
+/** Offset 0x0FFA - VMD Port Func
+  VMD Root port function number.
+**/
+  UINT8                       VmdPortFunc[31];
+
+/** Offset 0x1019 - Reserved
+**/
+  UINT8                       Reserved32[7];
+
+/** Offset 0x1020 - VMD Variable
+  VMD Variable Pointer.
+**/
+  UINT64                      VmdVariablePtr;
+
+/** Offset 0x1028 - Reserved
+**/
+  UINT8                      Reserved33[4];
+
+/** Offset 0x102C - Temporary MemBar1 address for VMD
+  VMD Variable Pointer.
+**/
+  UINT32                      VmdMemBar1Base;
+
+/** Offset 0x1030 - Temporary MemBar2 address for VMD
+  VMD Variable Pointer.
+**/
+  UINT32                      VmdMemBar2Base;
+
+/** Offset 0x1034 - Enable D3 Hot in TCSS
+  This policy will enable/disable D3 hot support in IOM
+  $EN_DIS
+**/
+  UINT8                       D3HotEnable;
+
+/** Offset 0x1035 - Reserved
+**/
+  UINT8                       Reserved34[3];
+
+/** Offset 0x1038 - TypeC port GPIO setting
   GPIO Ping number for Type C Aux orientation setting, use the GpioPad that is defined
   in GpioPinsXXXH.h and GpioPinsXXXLp.h as argument.(XXX is platform name, Ex: Lnl
   = LunarLake)
 **/
   UINT32                      IomTypeCPortPadCfg[12];
 
-/** Offset 0x102C - CPU USB3 Port Over Current Pin
+/** Offset 0x1068 - CPU USB3 Port Over Current Pin
   Describe the specific over current pin number of USBC Port N.
 **/
   UINT8                       CpuUsb3OverCurrentPin[10];
 
-/** Offset 0x1036 - Enable D3 Cold in TCSS
+/** Offset 0x1072 - Enable D3 Cold in TCSS
   This policy will enable/disable D3 cold support in IOM
   $EN_DIS
 **/
   UINT8                       D3ColdEnable;
 
-/** Offset 0x1037 - TC State in TCSS
+/** Offset 0x1073 - TC State in TCSS
   This TC C-State Limit in IOM
 **/
   UINT8                       TcCstateLimit;
 
-/** Offset 0x1038 - Reserved
+/** Offset 0x1074 - Reserved
 **/
-  UINT8                       Reserved31[2];
+  UINT8                       Reserved35[2];
 
-/** Offset 0x103A - Enable/Disable PMC-PD Solution
+/** Offset 0x1076 - Enable/Disable PMC-PD Solution
   This policy will enable/disable PMC-PD Solution vs EC-TCPC Solution
   $EN_DIS
 **/
   UINT8                       PmcPdEnable;
 
-/** Offset 0x103B - Reserved
+/** Offset 0x1077 - Reserved
 **/
-  UINT8                       Reserved32;
+  UINT8                       Reserved36;
 
-/** Offset 0x103C - TCSS Aux Orientation Override Enable
+/** Offset 0x1078 - TCSS Aux Orientation Override Enable
   Bits 0, 2, ... 10 control override enables, bits 1, 3, ... 11 control overrides
 **/
   UINT16                      TcssAuxOri;
 
-/** Offset 0x103E - TCSS HSL Orientation Override Enable
+/** Offset 0x107A - TCSS HSL Orientation Override Enable
   Bits 0, 2, ... 10 control override enables, bits 1, 3, ... 11 control overrides
 **/
   UINT16                      TcssHslOri;
 
-/** Offset 0x1040 - TCSS USB Port Enable
+/** Offset 0x107C - TCSS USB Port Enable
   Bits 0, 1, ... max Type C port control enables
 **/
   UINT8                       UsbTcPortEn;
 
-/** Offset 0x1041 - VCCST request for IOM
+/** Offset 0x107D - VCCST request for IOM
   This policy will enable/disable VCCST and also decides if message would be replayed in S4/S5
   $EN_DIS
 **/
   UINT8                       VccSt;
 
-/** Offset 0x1042 - Enable/Disable PTM
+/** Offset 0x107E - Enable/Disable PTM
   This policy will enable/disable Precision Time Measurement for TCSS PCIe Root Ports
   $EN_DIS
 **/
   UINT8                       PtmEnabled[4];
 
-/** Offset 0x1046 - PCIE RP Ltr Enable
+/** Offset 0x1082 - PCIE RP Ltr Enable
   Latency Tolerance Reporting Mechanism.
 **/
   UINT8                       SaPcieItbtRpLtrEnable[4];
 
-/** Offset 0x104A - PCIE RP Snoop Latency Override Mode
+/** Offset 0x1086 - PCIE RP Snoop Latency Override Mode
   Latency Tolerance Reporting, Snoop Latency Override Mode.
 **/
   UINT8                       SaPcieItbtRpSnoopLatencyOverrideMode[4];
 
-/** Offset 0x104E - PCIE RP Snoop Latency Override Multiplier
+/** Offset 0x108A - PCIE RP Snoop Latency Override Multiplier
   Latency Tolerance Reporting, Snoop Latency Override Multiplier.
 **/
   UINT8                       SaPcieItbtRpSnoopLatencyOverrideMultiplier[4];
 
-/** Offset 0x1052 - PCIE RP Snoop Latency Override Value
+/** Offset 0x108E - PCIE RP Snoop Latency Override Value
   Latency Tolerance Reporting, Snoop Latency Override Value.
 **/
   UINT16                      SaPcieItbtRpSnoopLatencyOverrideValue[4];
 
-/** Offset 0x105A - PCIE RP Non Snoop Latency Override Mode
+/** Offset 0x1096 - PCIE RP Non Snoop Latency Override Mode
   Latency Tolerance Reporting, Non-Snoop Latency Override Mode.
 **/
   UINT8                       SaPcieItbtRpNonSnoopLatencyOverrideMode[4];
 
-/** Offset 0x105E - PCIE RP Non Snoop Latency Override Multiplier
+/** Offset 0x109A - PCIE RP Non Snoop Latency Override Multiplier
   Latency Tolerance Reporting, Non-Snoop Latency Override Multiplier.
 **/
   UINT8                       SaPcieItbtRpNonSnoopLatencyOverrideMultiplier[4];
 
-/** Offset 0x1062 - PCIE RP Non Snoop Latency Override Value
+/** Offset 0x109E - PCIE RP Non Snoop Latency Override Value
   Latency Tolerance Reporting, Non-Snoop Latency Override Value.
 **/
   UINT16                      SaPcieItbtRpNonSnoopLatencyOverrideValue[4];
 
-/** Offset 0x106A - Force LTR Override
+/** Offset 0x10A6 - Force LTR Override
   Force LTR Override.
 **/
   UINT8                       SaPcieItbtRpForceLtrOverride[4];
 
-/** Offset 0x106E - PCIE RP Ltr Config Lock
+/** Offset 0x10AA - PCIE RP Ltr Config Lock
   0: Disable; 1: Enable.
 **/
   UINT8                       SaPcieItbtRpLtrConfigLock[4];
 
-/** Offset 0x1072 - Reserved
+/** Offset 0x10AE - Reserved
 **/
-  UINT8                       Reserved33[4];
+  UINT8                       Reserved37[4];
 
-/** Offset 0x1076 - Touch Host Controller Assignment
+/** Offset 0x10B2 - Touch Host Controller Assignment
   Assign THC 0x0:ThcAssignmentNone, 0x1:ThcAssignmentThc0, 0x2:ThcAssignmentThc1
 **/
   UINT8                       ThcAssignment[2];
 
-/** Offset 0x1078 - Touch Host Controller Interrupt Pin Mux
+/** Offset 0x10B4 - Touch Host Controller Interrupt Pin Mux
   Set THC Pin Muxing Value if signal can be enabled on multiple pads. Refer to GPIO_*_MUXING_THC_SPIx_INTB_*
   for possible values.
 **/
   UINT8                       ThcInterruptPinMuxing[8];
 
-/** Offset 0x1080 - Touch Host Controller Mode
+/** Offset 0x10BC - Touch Host Controller Mode
   Switch between Intel THC protocol and Industry standard HID Over SPI protocol. 0x0:Thc, 0x1:Hid
 **/
   UINT8                       ThcMode[2];
 
-/** Offset 0x1082 - Touch Host Controller Wake On Touch
+/** Offset 0x10BE - Touch Host Controller Wake On Touch
   Based on this setting vGPIO for given THC will be in native mode, and additional
   _CRS for wake will be exposed in ACPI
 **/
   UINT8                       ThcWakeOnTouch[2];
 
-/** Offset 0x1084 - Reserved
+/** Offset 0x10C0 - Reserved
 **/
-  UINT8                      Reserved34[337];
+  UINT8                      Reserved38[337];
 
-/** Offset 0x11D5 - PCHHOT# pin
+/** Offset 0x1211 - PCHHOT# pin
   Enable PCHHOT# pin assertion when temperature is higher than PchHotLevel. 0: disable, 1: enable
   $EN_DIS
 **/
   UINT8                       PchHotEnable;
 
-/** Offset 0x11D6 - Thermal Throttling Custimized T0Level Value
+/** Offset 0x1212 - Thermal Throttling Custimized T0Level Value
   Custimized T0Level value.
 **/
   UINT16                      PchT0Level;
 
-/** Offset 0x11D8 - Thermal Throttling Custimized T1Level Value
+/** Offset 0x1214 - Thermal Throttling Custimized T1Level Value
   Custimized T1Level value.
 **/
   UINT16                      PchT1Level;
 
-/** Offset 0x11DA - Thermal Throttling Custimized T2Level Value
+/** Offset 0x1216 - Thermal Throttling Custimized T2Level Value
   Custimized T2Level value.
 **/
   UINT16                      PchT2Level;
 
-/** Offset 0x11DC - Enable The Thermal Throttle
+/** Offset 0x1218 - Enable The Thermal Throttle
   Enable the thermal throttle function.
   $EN_DIS
 **/
   UINT8                       PchTTEnable;
 
-/** Offset 0x11DD - PMSync State 13
+/** Offset 0x1219 - PMSync State 13
   When set to 1 and the programmed GPIO pin is a 1, then PMSync state 13 will force
   at least T2 state.
   $EN_DIS
 **/
   UINT8                       PchTTState13Enable;
 
-/** Offset 0x11DE - Thermal Throttle Lock
+/** Offset 0x121A - Thermal Throttle Lock
   Thermal Throttle Lock.
   $EN_DIS
 **/
   UINT8                       PchTTLock;
 
-/** Offset 0x11DF - Thermal Throttling Suggested Setting
+/** Offset 0x121B - Thermal Throttling Suggested Setting
   Thermal Throttling Suggested Setting.
   $EN_DIS
 **/
   UINT8                       TTSuggestedSetting;
 
-/** Offset 0x11E0 - Thermal Device Temperature
+/** Offset 0x121C - Thermal Device Temperature
   Decides the temperature.
 **/
   UINT16                      PchTemperatureHotLevel;
 
-/** Offset 0x11E2
+/** Offset 0x121E
 **/
   UINT8                       PchTsnEnable[4];
 
-/** Offset 0x11E6 - Enable TSN Multi-VC
-  Enable/disable Multi Virtual Channels(VC) in TSN.
-  $EN_DIS
+/** Offset 0x1222 - Reserved
 **/
-  UINT8                       PchTsnMultiVcEnable;
+  UINT8                      Reserved39[34];
 
-/** Offset 0x11E7 - Reserved
-**/
-  UINT8                       Reserved35[33];
-
-/** Offset 0x1208 - Enable USB2 ports
+/** Offset 0x1244 - Enable USB2 ports
   Enable/disable per USB2 ports. One byte for each port, byte0 for port0, byte1 for
   port1, and so on.
 **/
   UINT8                       PortUsb20Enable[16];
 
-/** Offset 0x1218 - Enable USB3 ports
+/** Offset 0x1254 - Enable USB3 ports
   Enable/disable per USB3 ports. One byte for each port, byte0 for port0, byte1 for
   port1, and so on.
 **/
   UINT8                       PortUsb30Enable[10];
 
-/** Offset 0x1222 - Enable xDCI controller
+/** Offset 0x125E - Enable xDCI controller
   Enable/disable to xDCI controller.
   $EN_DIS
 **/
   UINT8                       XdciEnable;
 
-/** Offset 0x1223 - USB PDO Programming
+/** Offset 0x125F - USB PDO Programming
   Enable/disable PDO programming for USB in PEI phase. Disabling will allow for programming
   during later phase. 1: enable, 0: disable
   $EN_DIS
 **/
   UINT8                       UsbPdoProgramming;
 
-/** Offset 0x1224 - Reserved
+/** Offset 0x1260 - Reserved
 **/
-  UINT8                       Reserved36;
+  UINT8                       Reserved40;
 
-/** Offset 0x1225 - PCH USB OverCurrent mapping enable
+/** Offset 0x1261 - PCH USB OverCurrent mapping enable
   1: Will program USB OC pin mapping in xHCI controller memory, 0: Will clear OC pin
   mapping allow for NOA usage of OC pins
   $EN_DIS
 **/
   UINT8                       PchUsbOverCurrentEnable;
 
-/** Offset 0x1226 - USB2 Port Over Current Pin
+/** Offset 0x1262 - USB2 Port Over Current Pin
   Describe the specific over current pin number of USB 2.0 Port N.
 **/
   UINT8                       Usb2OverCurrentPin[16];
 
-/** Offset 0x1236 - USB3 Port Over Current Pin
+/** Offset 0x1272 - USB3 Port Over Current Pin
   Describe the specific over current pin number of USB 3.0 Port N.
 **/
   UINT8                       Usb3OverCurrentPin[10];
 
-/** Offset 0x1240 - Enable xHCI LTR override
+/** Offset 0x127C - Enable xHCI LTR override
   Enables override of recommended LTR values for xHCI
   $EN_DIS
 **/
   UINT8                       PchUsbLtrOverrideEnable;
 
-/** Offset 0x1241 - Reserved
+/** Offset 0x127D - Reserved
 **/
-  UINT8                       Reserved37[3];
+  UINT8                       Reserved41[3];
 
-/** Offset 0x1244 - xHCI High Idle Time LTR override
+/** Offset 0x1280 - xHCI High Idle Time LTR override
   Value used for overriding LTR recommendation for xHCI High Idle Time LTR setting
 **/
   UINT32                      PchUsbLtrHighIdleTimeOverride;
 
-/** Offset 0x1248 - xHCI Medium Idle Time LTR override
+/** Offset 0x1284 - xHCI Medium Idle Time LTR override
   Value used for overriding LTR recommendation for xHCI Medium Idle Time LTR setting
 **/
   UINT32                      PchUsbLtrMediumIdleTimeOverride;
 
-/** Offset 0x124C - xHCI Low Idle Time LTR override
+/** Offset 0x1288 - xHCI Low Idle Time LTR override
   Value used for overriding LTR recommendation for xHCI Low Idle Time LTR setting
 **/
   UINT32                      PchUsbLtrLowIdleTimeOverride;
 
-/** Offset 0x1250 - USB2 Port Reset Message Enable
+/** Offset 0x128C - USB2 Port Reset Message Enable
   0: Disable USB2 Port Reset Message; 1: Enable USB2 Port Reset Message; This must
   be enable for USB2 Port those are paired with CPU XHCI Port
 **/
   UINT8                       PortResetMessageEnable[16];
 
-/** Offset 0x1260 - PCH USB OverCurrent mapping lock enable
+/** Offset 0x129C - PCH USB OverCurrent mapping lock enable
   If this policy option is enabled then BIOS will program OCCFDONE bit in xHCI meaning
   that OC mapping data will be consumed by xHCI and OC mapping registers will be locked.
   $EN_DIS
 **/
   UINT8                       PchXhciOcLock;
 
-/** Offset 0x1261 - USB Per Port HS Preemphasis Bias
+/** Offset 0x129D - USB Per Port HS Preemphasis Bias
   USB Per Port HS Preemphasis Bias. 000b-0mV, 001b-11.25mV, 010b-16.9mV, 011b-28.15mV,
   100b-28.15mV, 101b-39.35mV, 110b-45mV, 111b-56.3mV. One byte for each port.
 **/
   UINT8                       Usb2PhyPetxiset[16];
 
-/** Offset 0x1271 - USB Per Port HS Transmitter Bias
+/** Offset 0x12AD - USB Per Port HS Transmitter Bias
   USB Per Port HS Transmitter Bias. 000b-0mV, 001b-11.25mV, 010b-16.9mV, 011b-28.15mV,
   100b-28.15mV, 101b-39.35mV, 110b-45mV, 111b-56.3mV, One byte for each port.
 **/
   UINT8                       Usb2PhyTxiset[16];
 
-/** Offset 0x1281 - USB Per Port HS Transmitter Emphasis
+/** Offset 0x12BD - USB Per Port HS Transmitter Emphasis
   USB Per Port HS Transmitter Emphasis. 00b - Emphasis OFF, 01b - De-emphasis ON,
   10b - Pre-emphasis ON, 11b - Pre-emphasis & De-emphasis ON. One byte for each port.
 **/
   UINT8                       Usb2PhyPredeemp[16];
 
-/** Offset 0x1291 - USB Per Port Half Bit Pre-emphasis
+/** Offset 0x12CD - USB Per Port Half Bit Pre-emphasis
   USB Per Port Half Bit Pre-emphasis. 1b - half-bit pre-emphasis, 0b - full-bit pre-emphasis.
   One byte for each port.
 **/
   UINT8                       Usb2PhyPehalfbit[16];
 
-/** Offset 0x12A1 - Enable the write to USB 3.0 TX Output -3.5dB De-Emphasis Adjustment
+/** Offset 0x12DD - Enable the write to USB 3.0 TX Output -3.5dB De-Emphasis Adjustment
   Enable the write to USB 3.0 TX Output -3.5dB De-Emphasis Adjustment. Each value
   in arrary can be between 0-1. One byte for each port.
 **/
   UINT8                       Usb3HsioTxDeEmphEnable[10];
 
-/** Offset 0x12AB - USB 3.0 TX Output -3.5dB De-Emphasis Adjustment Setting
+/** Offset 0x12E7 - USB 3.0 TX Output -3.5dB De-Emphasis Adjustment Setting
   USB 3.0 TX Output -3.5dB De-Emphasis Adjustment Setting, HSIO_TX_DWORD5[21:16],
   <b>Default = 29h</b> (approximately -3.5dB De-Emphasis). One byte for each port.
 **/
   UINT8                       Usb3HsioTxDeEmph[10];
 
-/** Offset 0x12B5 - Enable the write to USB 3.0 TX Output Downscale Amplitude Adjustment
+/** Offset 0x12F1 - Enable the write to USB 3.0 TX Output Downscale Amplitude Adjustment
   Enable the write to USB 3.0 TX Output Downscale Amplitude Adjustment, Each value
   in arrary can be between 0-1. One byte for each port.
 **/
   UINT8                       Usb3HsioTxDownscaleAmpEnable[10];
 
-/** Offset 0x12BF - USB 3.0 TX Output Downscale Amplitude Adjustment
+/** Offset 0x12FB - USB 3.0 TX Output Downscale Amplitude Adjustment
   USB 3.0 TX Output Downscale Amplitude Adjustment, HSIO_TX_DWORD8[21:16], <b>Default
   = 00h</b>. One byte for each port.
 **/
   UINT8                       Usb3HsioTxDownscaleAmp[10];
 
-/** Offset 0x12C9
+/** Offset 0x1305
 **/
   UINT8                       PchUsb3HsioCtrlAdaptOffsetCfgEnable[10];
 
-/** Offset 0x12D3
+/** Offset 0x130F
 **/
   UINT8                       PchUsb3HsioFilterSelNEnable[10];
 
-/** Offset 0x12DD
+/** Offset 0x1319
 **/
   UINT8                       PchUsb3HsioFilterSelPEnable[10];
 
-/** Offset 0x12E7
+/** Offset 0x1323
 **/
   UINT8                       PchUsb3HsioOlfpsCfgPullUpDwnResEnable[10];
 
-/** Offset 0x12F1
+/** Offset 0x132D
 **/
   UINT8                       PchUsb3HsioCtrlAdaptOffsetCfg[10];
 
-/** Offset 0x12FB
+/** Offset 0x1337
 **/
   UINT8                       PchUsb3HsioOlfpsCfgPullUpDwnRes[10];
 
-/** Offset 0x1305
+/** Offset 0x1341
 **/
   UINT8                       PchUsb3HsioFilterSelN[10];
 
-/** Offset 0x130F
+/** Offset 0x134B
 **/
   UINT8                       PchUsb3HsioFilterSelP[10];
 
-/** Offset 0x1319 - Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 3
+/** Offset 0x1355 - Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 3
   Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 3, Each
   value in array can be between 0-1. One byte for each port.
 **/
   UINT8                       Usb3HsioTxRate3UniqTranEnable[10];
 
-/** Offset 0x1323 - USB 3.0 TX Output Unique Transition Bit Scale for rate 3
+/** Offset 0x135F - USB 3.0 TX Output Unique Transition Bit Scale for rate 3
   USB 3.0 TX Output Unique Transition Bit Scale for rate 3, HSIO_TX_DWORD9[6:0], <b>Default
   = 4Ch</b>. One byte for each port.
 **/
   UINT8                       Usb3HsioTxRate3UniqTran[10];
 
-/** Offset 0x132D - Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 2
+/** Offset 0x1369 - Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 2
   Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 2, Each
   value in array can be between 0-1. One byte for each port.
 **/
   UINT8                       Usb3HsioTxRate2UniqTranEnable[10];
 
-/** Offset 0x1337 - USB 3.0 TX Output Unique Transition Bit Scale for rate 2
+/** Offset 0x1373 - USB 3.0 TX Output Unique Transition Bit Scale for rate 2
   USB 3.0 TX Output Unique Transition Bit Scale for rate 2, HSIO_TX_DWORD9[14:8],
   <b>Default = 4Ch</b>. One byte for each port.
 **/
   UINT8                       Usb3HsioTxRate2UniqTran[10];
 
-/** Offset 0x1341 - Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 1
+/** Offset 0x137D - Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 1
   Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 1, Each
   value in array can be between 0-1. One byte for each port.
 **/
   UINT8                       Usb3HsioTxRate1UniqTranEnable[10];
 
-/** Offset 0x134B - USB 3.0 TX Output Unique Transition Bit Scale for rate 1
+/** Offset 0x1387 - USB 3.0 TX Output Unique Transition Bit Scale for rate 1
   USB 3.0 TX Output Unique Transition Bit Scale for rate 1, HSIO_TX_DWORD9[22:16],
   <b>Default = 4Ch</b>. One byte for each port.
 **/
   UINT8                       Usb3HsioTxRate1UniqTran[10];
 
-/** Offset 0x1355 - Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 0
+/** Offset 0x1391 - Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 0
   Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 0, Each
   value in array can be between 0-1. One byte for each port.
 **/
   UINT8                       Usb3HsioTxRate0UniqTranEnable[10];
 
-/** Offset 0x135F - USB 3.0 TX Output Unique Transition Bit Scale for rate 0
+/** Offset 0x139B - USB 3.0 TX Output Unique Transition Bit Scale for rate 0
   USB 3.0 TX Output Unique Transition Bit Scale for rate 0, HSIO_TX_DWORD9[30:24],
   <b>Default = 4Ch</b>. One byte for each port.
 **/
   UINT8                       Usb3HsioTxRate0UniqTran[10];
 
-/** Offset 0x1369 - Reserved
+/** Offset 0x13A5 - Reserved
 **/
-  UINT8                       Reserved38[4];
+  UINT8                       Reserved42[4];
 
-/** Offset 0x136D - Enable/Disable NPU Device
+/** Offset 0x13A9 - Enable/Disable NPU Device
   Enable(Default): Enable NPU Device, Disable: Disable NPU Device
   $EN_DIS
 **/
   UINT8                       NpuEnable;
 
-/** Offset 0x136E - Enable LAN
+/** Offset 0x13AA - Enable LAN
   Enable/disable LAN controller.
   $EN_DIS
 **/
   UINT8                       PchLanEnable;
 
-/** Offset 0x136F - Enable PCH Lan LTR capabilty of PCH internal LAN
+/** Offset 0x13AB - Enable PCH Lan LTR capabilty of PCH internal LAN
   0: Disable; 1: Enable.
   $EN_DIS
 **/
   UINT8                       PchLanLtrEnable;
 
-/** Offset 0x1370 - Reserved
+/** Offset 0x13AC - Reserved
 **/
-  UINT8                       Reserved39;
+  UINT8                       Reserved43;
 
-/** Offset 0x1371 - Skip Ssid Programming.
+/** Offset 0x13AD - Skip Ssid Programming.
   When set to TRUE, silicon code will not do any SSID programming and platform code
   needs to handle that by itself properly.
   $EN_DIS
 **/
   UINT8                       SiSkipSsidProgramming;
 
-/** Offset 0x1372 - Change Default SVID
+/** Offset 0x13AE - Change Default SVID
   Change the default SVID used in FSP to programming internal devices. This is only
   valid when SkipSsidProgramming is FALSE.
 **/
   UINT16                      SiCustomizedSvid;
 
-/** Offset 0x1374 - Change Default SSID
+/** Offset 0x13B0 - Change Default SSID
   Change the default SSID used in FSP to programming internal devices. This is only
   valid when SkipSsidProgramming is FALSE.
 **/
   UINT16                      SiCustomizedSsid;
 
-/** Offset 0x1376 - Reserved
+/** Offset 0x13B2 - Reserved
 **/
-  UINT8                       Reserved40[2];
+  UINT8                       Reserved44[6];
 
-/** Offset 0x1378 - SVID SDID table Poniter.
+/** Offset 0x13B8 - SVID SDID table Poniter.
   The address of the table of SVID SDID to customize each SVID SDID entry. This is
   only valid when SkipSsidProgramming is FALSE.
 **/
   UINT64                      SiSsidTablePtr;
 
-/** Offset 0x1380 - Number of ssid table.
+/** Offset 0x13C0 - Number of ssid table.
   SiNumberOfSsidTableEntry should match the table entries created in SiSsidTablePtr.
   This is only valid when SkipSsidProgramming is FALSE.
 **/
   UINT16                      SiNumberOfSsidTableEntry;
 
-/** Offset 0x1382 - Reserved
+/** Offset 0x13C2 - Reserved
 **/
-  UINT8                       Reserved41[10];
+  UINT8                       Reserved45[10];
 
-/** Offset 0x138C - LogoPixelHeight Address
+/** Offset 0x13CC - LogoPixelHeight Address
   Address of LogoPixelHeight
 **/
   UINT32                      LogoPixelHeight;
 
-/** Offset 0x1390 - LogoPixelWidth Address
+/** Offset 0x13D0 - LogoPixelWidth Address
   Address of LogoPixelWidth
 **/
   UINT32                      LogoPixelWidth;
 
-/** Offset 0x1394 - Reserved
+/** Offset 0x13D4 - Reserved
 **/
-  UINT8                       Reserved42[4];
+  UINT8                       Reserved46[4];
 
-/** Offset 0x1398 - Blt Buffer Address
+/** Offset 0x13D8 - Blt Buffer Address
   Address of Blt buffer
 **/
   UINT64                      BltBufferAddress;
 
-/** Offset 0x13A0 - Graphics Configuration Ptr
+/** Offset 0x13E0 - Graphics Configuration Ptr
   Points to VBT
 **/
   UINT64                      GraphicsConfigPtr;
 
-/** Offset 0x13A8 - Enable/Disable SkipFspGop
+/** Offset 0x13E8 - Enable/Disable SkipFspGop
   Enable: Skip FSP provided GOP driver, Disable(Default): Use FSP provided GOP driver
   $EN_DIS
 **/
   UINT8                       SkipFspGop;
 
-/** Offset 0x13A9 - Reserved
+/** Offset 0x13E9 - Reserved
 **/
-  UINT8                       Reserved43;
+  UINT8                       Reserved47;
 
-/** Offset 0x13AA - Enable/Disable IGFX RenderStandby
+/** Offset 0x13EA - Enable/Disable IGFX RenderStandby
   Enable(Default): Enable IGFX RenderStandby, Disable: Disable IGFX RenderStandby
   $EN_DIS
 **/
   UINT8                       RenderStandby;
 
-/** Offset 0x13AB - Reserved
+/** Offset 0x13EB - Reserved
 **/
-  UINT8                       Reserved44[3];
+  UINT8                       Reserved48[3];
 
-/** Offset 0x13AE - Enable/Disable PavpEnable
+/** Offset 0x13EE - Enable/Disable PavpEnable
   Enable(Default): Enable PavpEnable, Disable: Disable PavpEnable
   $EN_DIS
 **/
   UINT8                       PavpEnable;
 
-/** Offset 0x13AF - Enable/Disable PeiGraphicsPeimInit
+/** Offset 0x13EF - Enable/Disable PeiGraphicsPeimInit
   <b>Enable(Default):</b> FSP will initialize the framebuffer and provide it via EFI_PEI_GRAPHICS_INFO_HOB.
   Disable: FSP will NOT initialize the framebuffer.
   $EN_DIS
 **/
   UINT8                       PeiGraphicsPeimInit;
 
-/** Offset 0x13B0 - Reserved
+/** Offset 0x13F0 - Reserved
 **/
-  UINT8                       Reserved45[4];
+  UINT8                       Reserved49[4];
 
-/** Offset 0x13B4 - Intel Graphics VBT (Video BIOS Table) Size
+/** Offset 0x13F4 - Intel Graphics VBT (Video BIOS Table) Size
   Size of Internal Graphics VBT Image
 **/
   UINT32                      VbtSize;
 
-/** Offset 0x13B8 - Platform LID Status for LFP Displays.
+/** Offset 0x13F8 - Platform LID Status for LFP Displays.
   LFP Display Lid Status (LID_STATUS enum): 0 (Default): LidClosed, 1: LidOpen.
   0: LidClosed, 1: LidOpen
 **/
   UINT8                       LidStatus;
 
-/** Offset 0x13B9 - Reserved
+/** Offset 0x13F9 - Reserved
 **/
-  UINT8                       Reserved46[11];
+  UINT8                       Reserved50[11];
 
-/** Offset 0x13C4 - Address of PCH_DEVICE_INTERRUPT_CONFIG table.
+/** Offset 0x1404 - Address of PCH_DEVICE_INTERRUPT_CONFIG table.
   The address of the table of PCH_DEVICE_INTERRUPT_CONFIG.
 **/
   UINT32                      DevIntConfigPtr;
 
-/** Offset 0x13C8 - Number of DevIntConfig Entry
+/** Offset 0x1408 - Number of DevIntConfig Entry
   Number of Device Interrupt Configuration Entry. If this is not zero, the DevIntConfigPtr
   must not be NULL.
 **/
   UINT8                       NumOfDevIntConfig;
 
-/** Offset 0x13C9 - Select GPIO IRQ Route
+/** Offset 0x1409 - Select GPIO IRQ Route
   GPIO IRQ Select. The valid value is 14 or 15.
 **/
   UINT8                       GpioIrqRoute;
 
-/** Offset 0x13CA - Select SciIrqSelect
+/** Offset 0x140A - Select SciIrqSelect
   SCI IRQ Select. The valid value is 9, 10, 11, and 20, 21, 22, 23 for APIC only.
 **/
   UINT8                       SciIrqSelect;
 
-/** Offset 0x13CB - Select TcoIrqSelect
+/** Offset 0x140B - Select TcoIrqSelect
   TCO IRQ Select. The valid value is 9, 10, 11, 20, 21, 22, 23.
 **/
   UINT8                       TcoIrqSelect;
 
-/** Offset 0x13CC - Enable/Disable Tco IRQ
+/** Offset 0x140C - Enable/Disable Tco IRQ
   Enable/disable TCO IRQ
   $EN_DIS
 **/
   UINT8                       TcoIrqEnable;
 
-/** Offset 0x13CD - Reserved
+/** Offset 0x140D - Reserved
 **/
-  UINT8                       Reserved47[5];
+  UINT8                       Reserved51[5];
 
-/** Offset 0x13D2 - Mask to enable the usage of external V1p05 VR rail in specific S0ix or Sx states
+/** Offset 0x1412 - Mask to enable the usage of external V1p05 VR rail in specific S0ix or Sx states
   Enable External V1P05 Rail in: BIT0:S0i1/S0i2, BIT1:S0i3, BIT2:S3, BIT3:S4, BIT5:S5
 **/
   UINT8                       PchFivrExtV1p05RailEnabledStates;
 
-/** Offset 0x13D3 - Mask to enable the platform configuration of external V1p05 VR rail
+/** Offset 0x1413 - Mask to enable the platform configuration of external V1p05 VR rail
   External V1P05 Rail Supported Configuration
 **/
   UINT8                       PchFivrExtV1p05RailSupportedVoltageStates;
 
-/** Offset 0x13D4 - External V1P05 Voltage Value that will be used in S0i2/S0i3 states
+/** Offset 0x1414 - External V1P05 Voltage Value that will be used in S0i2/S0i3 states
   Value is given in 2.5mV increments (0=0mV, 1=2.5mV, 2=5mV...)
 **/
   UINT16                      PchFivrExtV1p05RailVoltage;
 
-/** Offset 0x13D6 - External V1P05 Icc Max Value
+/** Offset 0x1416 - External V1P05 Icc Max Value
   Granularity of this setting is 1mA and maximal possible value is 200mA
 **/
   UINT8                       PchFivrExtV1p05RailIccMax;
 
-/** Offset 0x13D7 - Mask to enable the usage of external Vnn VR rail in specific S0ix or Sx states
+/** Offset 0x1417 - Mask to enable the usage of external Vnn VR rail in specific S0ix or Sx states
   Enable External Vnn Rail in: BIT0:S0i1/S0i2, BIT1:S0i3, BIT2:S3, BIT3:S4, BIT5:S5
 **/
   UINT8                       PchFivrExtVnnRailEnabledStates;
 
-/** Offset 0x13D8 - Mask to enable the platform configuration of external Vnn VR rail
+/** Offset 0x1418 - Mask to enable the platform configuration of external Vnn VR rail
   External Vnn Rail Supported Configuration
 **/
   UINT8                       PchFivrExtVnnRailSupportedVoltageStates;
 
-/** Offset 0x13D9 - Reserved
+/** Offset 0x1419 - Reserved
 **/
-  UINT8                       Reserved48;
+  UINT8                       Reserved52;
 
-/** Offset 0x13DA - External Vnn Voltage Value that will be used in S0ix/Sx states
+/** Offset 0x141A - External Vnn Voltage Value that will be used in S0ix/Sx states
   Value is given in 2.5mV increments (0=0mV, 1=2.5mV, 2=5mV...), Default is set to 420
 **/
   UINT16                      PchFivrExtVnnRailVoltage;
 
-/** Offset 0x13DC - External Vnn Icc Max Value that will be used in S0ix/Sx states
+/** Offset 0x141C - External Vnn Icc Max Value that will be used in S0ix/Sx states
   Granularity of this setting is 1mA and maximal possible value is 200mA
 **/
   UINT8                       PchFivrExtVnnRailIccMax;
 
-/** Offset 0x13DD - Mask to enable the usage of external Vnn VR rail in Sx states
+/** Offset 0x141D - Mask to enable the usage of external Vnn VR rail in Sx states
   Use only if Ext Vnn Rail config is different in Sx. Enable External Vnn Rail in
   Sx: BIT0-1:Reserved, BIT2:S3, BIT3:S4, BIT5:S5
 **/
   UINT8                       PchFivrExtVnnRailSxEnabledStates;
 
-/** Offset 0x13DE - External Vnn Voltage Value that will be used in Sx states
+/** Offset 0x141E - External Vnn Voltage Value that will be used in Sx states
   Use only if Ext Vnn Rail config is different in Sx. Value is given in 2.5mV increments
   (0=0mV, 1=2.5mV, 2=5mV...)
 **/
   UINT16                      PchFivrExtVnnRailSxVoltage;
 
-/** Offset 0x13E0 - External Vnn Icc Max Value that will be used in Sx states
+/** Offset 0x1420 - External Vnn Icc Max Value that will be used in Sx states
   Use only if Ext Vnn Rail config is different in Sx. Granularity of this setting
   is 1mA and maximal possible value is 200mA
 **/
   UINT8                       PchFivrExtVnnRailSxIccMax;
 
-/** Offset 0x13E1 - Transition time in microseconds from Low Current Mode Voltage to High Current Mode Voltage
+/** Offset 0x1421 - Transition time in microseconds from Low Current Mode Voltage to High Current Mode Voltage
   This field has 1us resolution. When value is 0 PCH will not transition VCCIN_AUX
   to low current mode voltage.
 **/
   UINT8                       PchFivrVccinAuxLowToHighCurModeVolTranTime;
 
-/** Offset 0x13E2 - Transition time in microseconds from Retention Mode Voltage to High Current Mode Voltage
+/** Offset 0x1422 - Transition time in microseconds from Retention Mode Voltage to High Current Mode Voltage
   This field has 1us resolution. When value is 0 PCH will not transition VCCIN_AUX
   to retention mode voltage.
 **/
   UINT8                       PchFivrVccinAuxRetToHighCurModeVolTranTime;
 
-/** Offset 0x13E3 - Transition time in microseconds from Retention Mode Voltage to Low Current Mode Voltage
+/** Offset 0x1423 - Transition time in microseconds from Retention Mode Voltage to Low Current Mode Voltage
   This field has 1us resolution. When value is 0 PCH will not transition VCCIN_AUX
   to retention mode voltage.
 **/
   UINT8                       PchFivrVccinAuxRetToLowCurModeVolTranTime;
 
-/** Offset 0x13E4 - Transition time in microseconds from Off (0V) to High Current Mode Voltage
+/** Offset 0x1424 - Transition time in microseconds from Off (0V) to High Current Mode Voltage
   This field has 1us resolution. When value is 0 Transition to 0V is disabled.
 **/
   UINT16                      PchFivrVccinAuxOffToHighCurModeVolTranTime;
 
-/** Offset 0x13E6 - FIVR Dynamic Power Management
+/** Offset 0x1426 - FIVR Dynamic Power Management
   Enable/Disable FIVR Dynamic Power Management.
   $EN_DIS
 **/
   UINT8                       PchFivrDynPm;
 
-/** Offset 0x13E7 - Reserved
+/** Offset 0x1427 - Reserved
 **/
-  UINT8                       Reserved49;
+  UINT8                       Reserved53;
 
-/** Offset 0x13E8 - External V1P05 Icc Max Value
+/** Offset 0x1428 - External V1P05 Icc Max Value
   Granularity of this setting is 1mA and maximal possible value is 500mA
 **/
   UINT16                      PchFivrExtV1p05RailIccMaximum;
 
-/** Offset 0x13EA - External Vnn Icc Max Value that will be used in S0ix/Sx states
+/** Offset 0x142A - External Vnn Icc Max Value that will be used in S0ix/Sx states
   Granularity of this setting is 1mA and maximal possible value is 500mA
 **/
   UINT16                      PchFivrExtVnnRailIccMaximum;
 
-/** Offset 0x13EC - External Vnn Icc Max Value that will be used in Sx states
+/** Offset 0x142C - External Vnn Icc Max Value that will be used in Sx states
   Use only if Ext Vnn Rail config is different in Sx. Granularity of this setting
   is 1mA and maximal possible value is 500mA
 **/
   UINT16                      PchFivrExtVnnRailSxIccMaximum;
 
-/** Offset 0x13EE - External V1P05 Control Ramp Timer value
+/** Offset 0x142E - External V1P05 Control Ramp Timer value
   Hold off time to be used when changing the v1p05_ctrl for external bypass value in us
 **/
   UINT8                       PchFivrExtV1p05RailCtrlRampTmr;
 
-/** Offset 0x13EF - External VNN Control Ramp Timer value
+/** Offset 0x142F - External VNN Control Ramp Timer value
   Hold off time to be used when changing the vnn_ctrl for external bypass value in us
 **/
   UINT8                       PchFivrExtVnnRailCtrlRampTmr;
 
-/** Offset 0x13F0 - PCH Compatibility Revision ID
+/** Offset 0x1430 - PCH Compatibility Revision ID
   This member describes whether or not the CRID feature of PCH should be enabled.
   $EN_DIS
 **/
   UINT8                       PchCrid;
 
-/** Offset 0x13F1 - PCH Legacy IO Low Latency Enable
+/** Offset 0x1431 - PCH Legacy IO Low Latency Enable
   Set to enable low latency of legacy IO. <b>0: Disable</b>, 1: Enable
   $EN_DIS
 **/
   UINT8                       PchLegacyIoLowLatency;
 
-/** Offset 0x13F2 - Reserved
+/** Offset 0x1432 - Reserved
 **/
-  UINT8                       Reserved50;
+  UINT8                       Reserved54;
 
-/** Offset 0x13F3 - PCH Unlock SideBand access
+/** Offset 0x1433 - PCH Unlock SideBand access
   The SideBand PortID mask for certain end point (e.g. PSFx) will be locked before
   3rd party code execution. 0: Lock SideBand access; 1: Unlock SideBand access.
   $EN_DIS
 **/
   UINT8                       PchSbAccessUnlock;
 
-/** Offset 0x13F4 - Enable 8254 Static Clock Gating
+/** Offset 0x1434 - Enable 8254 Static Clock Gating
   Set 8254CGE=1 is required for SLP_S0 support. However, set 8254CGE=1 in POST time
   might fail to boot legacy OS using 8254 timer. Make sure it is disabled to support
   legacy OS using 8254 timer. Also enable this while S0ix is enabled.
@@ -2135,7 +2216,7 @@ typedef struct {
 **/
   UINT8                       Enable8254ClockGating;
 
-/** Offset 0x13F5 - Enable 8254 Static Clock Gating On S3
+/** Offset 0x1435 - Enable 8254 Static Clock Gating On S3
   This is only applicable when Enable8254ClockGating is disabled. FSP will do the
   8254 CGE programming on S3 resume when Enable8254ClockGatingOnS3 is enabled. This
   avoids the SMI requirement for the programming.
@@ -2143,174 +2224,174 @@ typedef struct {
 **/
   UINT8                       Enable8254ClockGatingOnS3;
 
-/** Offset 0x13F6 - Enable PCH Io Apic Entry 24-119
+/** Offset 0x1436 - Enable PCH Io Apic Entry 24-119
   0: Disable; 1: Enable.
   $EN_DIS
 **/
   UINT8                       PchIoApicEntry24_119;
 
-/** Offset 0x13F7 - PCH Io Apic ID
+/** Offset 0x1437 - PCH Io Apic ID
   This member determines IOAPIC ID. Default is 0x02.
 **/
   UINT8                       PchIoApicId;
 
-/** Offset 0x13F8 - CNVi Configuration
+/** Offset 0x1438 - CNVi Configuration
   This option allows for automatic detection of Connectivity Solution. [Auto Detection]
   assumes that CNVi will be enabled when available, [Disable] allows for disabling CNVi.
   0:Disable, 1:Auto
 **/
   UINT8                       CnviMode;
 
-/** Offset 0x13F9 - CNVi Wi-Fi Core
+/** Offset 0x1439 - CNVi Wi-Fi Core
   Enable/Disable CNVi Wi-Fi Core, Default is ENABLE. 0: DISABLE, 1: ENABLE
   $EN_DIS
 **/
   UINT8                       CnviWifiCore;
 
-/** Offset 0x13FA - CNVi BT Core
+/** Offset 0x143A - CNVi BT Core
   Enable/Disable CNVi BT Core, Default is ENABLE. 0: DISABLE, 1: ENABLE
   $EN_DIS
 **/
   UINT8                       CnviBtCore;
 
-/** Offset 0x13FB - CNVi BT Interface
+/** Offset 0x143B - CNVi BT Interface
   This option configures BT device interface to either USB/PCI
   1:USB, 2:PCI
 **/
   UINT8                       CnviBtInterface;
 
-/** Offset 0x13FC - CNVi BT Audio Offload
+/** Offset 0x143C - CNVi BT Audio Offload
   Enable/Disable BT Audio Offload, Default is ENABLE. 0: DISABLE, 1: ENABLE
   $EN_DIS
 **/
   UINT8                       CnviBtAudioOffload;
 
-/** Offset 0x13FD - Reserved
+/** Offset 0x143D - Reserved
 **/
-  UINT8                       Reserved51[3];
+  UINT8                       Reserved55[3];
 
-/** Offset 0x1400 - CNVi RF_RESET pin muxing
+/** Offset 0x1440 - CNVi RF_RESET pin muxing
   Select CNVi RF_RESET# pin depending on board routing. LP/P/M: GPP_A8 = 0x2942E408(default)
   or GPP_F4 = 0x194CE404. H/S: 0. Refer to GPIO_*_MUXING_CNVI_RF_RESET_* in GpioPins*.h.
 **/
   UINT32                      CnviRfResetPinMux;
 
-/** Offset 0x1404 - CNVi CLKREQ pin muxing
+/** Offset 0x1444 - CNVi CLKREQ pin muxing
   Select CNVi CLKREQ pin depending on board routing. LP/P/M: GPP_A9 = 0x3942E609(default)
   or GPP_F5 = 0x394CE605. H/S: 0. Refer to GPIO_*_MUXING_CNVI_CRF_XTAL_CLKREQ_* in
   GpioPins*.h.
 **/
   UINT32                      CnviClkreqPinMux;
 
-/** Offset 0x1408 - Reserved
+/** Offset 0x1448 - Reserved
 **/
-  UINT8                       Reserved52;
+  UINT8                       Reserved56;
 
-/** Offset 0x1409 - Enable Device 4
+/** Offset 0x1449 - Enable Device 4
   Enable/disable Device 4
   $EN_DIS
 **/
   UINT8                       Device4Enable;
 
-/** Offset 0x140A - Skip PAM regsiter lock
+/** Offset 0x144A - Skip PAM regsiter lock
   Enable: PAM register will not be locked by RC, platform code should lock it, Disable(Default):
   PAM registers will be locked by RC
   $EN_DIS
 **/
   UINT8                       SkipPamLock;
 
-/** Offset 0x140B - Reserved
+/** Offset 0x144B - Reserved
 **/
-  UINT8                       Reserved53;
+  UINT8                       Reserved57;
 
-/** Offset 0x140C - PCH HDA Verb Table Entry Number
+/** Offset 0x144C - PCH HDA Verb Table Entry Number
   Number of Entries in Verb Table.
 **/
   UINT8                       PchHdaVerbTableEntryNum;
 
-/** Offset 0x140D - Reserved
+/** Offset 0x144D - Reserved
 **/
-  UINT8                       Reserved54[3];
+  UINT8                       Reserved58[3];
 
-/** Offset 0x1410 - PCH HDA Verb Table Pointer
+/** Offset 0x1450 - PCH HDA Verb Table Pointer
   Pointer to Array of pointers to Verb Table.
 **/
   UINT64                      PchHdaVerbTablePtr;
 
-/** Offset 0x1418 - PCH HDA Codec Sx Wake Capability
+/** Offset 0x1458 - PCH HDA Codec Sx Wake Capability
   Capability to detect wake initiated by a codec in Sx
 **/
   UINT8                       PchHdaCodecSxWakeCapability;
 
-/** Offset 0x1419 - Enable Pme
+/** Offset 0x1459 - Enable Pme
   Enable Azalia wake-on-ring.
   $EN_DIS
 **/
   UINT8                       PchHdaPme;
 
-/** Offset 0x141A - HD Audio Link Frequency
+/** Offset 0x145A - HD Audio Link Frequency
   HDA Link Freq (PCH_HDAUDIO_LINK_FREQUENCY enum): 0: 6MHz, 1: 12MHz, 2: 24MHz.
   0: 6MHz, 1: 12MHz, 2: 24MHz
 **/
   UINT8                       PchHdaLinkFrequency;
 
-/** Offset 0x141B - Reserved
+/** Offset 0x145B - Reserved
 **/
-  UINT8                       Reserved55[2];
+  UINT8                       Reserved59[2];
 
-/** Offset 0x141D - HD Audio Microphone Privacy applied for SoundWire Link number 0 in HW Mode
+/** Offset 0x145D - HD Audio Microphone Privacy applied for SoundWire Link number 0 in HW Mode
   HD Audio Microphone Privacy applied for SoundWire Link number 0 in HW Mode: 0: Disable, 1: Enable
   $EN_DIS
 **/
   UINT8                       PchHdaMicPrivacyHwModeSoundWire0;
 
-/** Offset 0x141E - HD Audio Microphone Privacy applied for SoundWire Link number 1 in HW Mode
+/** Offset 0x145E - HD Audio Microphone Privacy applied for SoundWire Link number 1 in HW Mode
   HD Audio Microphone Privacy applied for SoundWire Link number 1 in HW Mode: 0: Disable, 1: Enable
   $EN_DIS
 **/
   UINT8                       PchHdaMicPrivacyHwModeSoundWire1;
 
-/** Offset 0x141F - HD Audio Microphone Privacy applied for SoundWire Link number 2 in HW Mode
+/** Offset 0x145F - HD Audio Microphone Privacy applied for SoundWire Link number 2 in HW Mode
   HD Audio Microphone Privacy applied for SoundWire Link number 2 in HW Mode: 0: Disable, 1: Enable
   $EN_DIS
 **/
   UINT8                       PchHdaMicPrivacyHwModeSoundWire2;
 
-/** Offset 0x1420 - HD Audio Microphone Privacy applied for SoundWire Link number 3 in HW Mode
+/** Offset 0x1460 - HD Audio Microphone Privacy applied for SoundWire Link number 3 in HW Mode
   HD Audio Microphone Privacy applied for SoundWire Link number 3 in HW Mode: 0: Disable, 1: Enable
   $EN_DIS
 **/
   UINT8                       PchHdaMicPrivacyHwModeSoundWire3;
 
-/** Offset 0x1421 - HD Audio Microphone Privacy applied for SoundWire Link number 4 in HW Mode
+/** Offset 0x1461 - HD Audio Microphone Privacy applied for SoundWire Link number 4 in HW Mode
   HD Audio Microphone Privacy applied for SoundWire Link number 4 in HW Mode: 0: Disable, 1: Enable
   $EN_DIS
 **/
   UINT8                       PchHdaMicPrivacyHwModeSoundWire4;
 
-/** Offset 0x1422 - HD Audio Microphone Privacy applied for Dmic in HW Mode
+/** Offset 0x1462 - HD Audio Microphone Privacy applied for Dmic in HW Mode
   HD Audio Microphone Privacy applied for Dmic in HW Mode: 0: Disable, 1: Enable
   $EN_DIS
 **/
   UINT8                       PchHdaMicPrivacyHwModeDmic;
 
-/** Offset 0x1423 - Reserved
+/** Offset 0x1463 - Reserved
 **/
-  UINT8                       Reserved56[13];
+  UINT8                       Reserved60[13];
 
-/** Offset 0x1430 - Pointer to ChipsetInit Binary
+/** Offset 0x1470 - Pointer to ChipsetInit Binary
   ChipsetInit Binary Pointer.
 **/
   UINT64                      ChipsetInitBinPtr;
 
-/** Offset 0x1438 - Length of ChipsetInit Binary
+/** Offset 0x1478 - Length of ChipsetInit Binary
   ChipsetInit Binary Length.
 **/
   UINT32                      ChipsetInitBinLen;
 
-/** Offset 0x143C - Reserved
+/** Offset 0x147C - Reserved
 **/
-  UINT8                       Reserved57[36];
+  UINT8                       Reserved61[36];
 } FSP_S_CONFIG;
 
 /** Fsp S UPD Configuration
@@ -2329,11 +2410,11 @@ typedef struct {
 **/
   FSP_S_CONFIG                FspsConfig;
 
-/** Offset 0x1460
+/** Offset 0x14A0
 **/
-  UINT8                       UnusedUpdSpace36[6];
+  UINT8                       FspsUpdRsvd36[6];
 
-/** Offset 0x1466
+/** Offset 0x14A6
 **/
   UINT16                      UpdTerminator;
 } FSPS_UPD;

From 09670ec9d61a987917f7854ef3e39625c18122fa Mon Sep 17 00:00:00 2001
From: Ronak Kanabar <ronak.kanabar@intel.com>
Date: Thu, 6 Feb 2025 16:02:45 +0530
Subject: [PATCH 0122/3886] soc/intel/pantherlake: Add support for VMD device

This commit adds support for VMD (Volume Management Device) in the
Panther Lake SoC. VMD is a feature that allows the management of NVMe
storage devices by abstracting the PCIe root complex. It provides a way
to manage multiple NVMe drives more efficiently.

Changes include:
- Adding VMD to the `min_pci_sleep_states` array in `acpi.c`.
- Updating `chipset.cb` to include the VMD device.
- Disabling the VMD device by default.
- Introducing a new function `fill_fsps_vmd_params`.
- Defining the VMD device and function numbers in `pci_devs.h`.

BUG=b:391083063
TEST=Able to build and boot google/fatcat. Observed that VmdEnable UPD
     is disabled in debug FSP logs.

Change-Id: Ie391196e7b4537d1146ac30177a0ba472a1bfb43
Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86301
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Jayvik Desai <jayvik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
---
 src/soc/intel/pantherlake/acpi.c                 | 1 +
 src/soc/intel/pantherlake/chipset.cb             | 1 +
 src/soc/intel/pantherlake/fsp_params.c           | 7 +++++++
 src/soc/intel/pantherlake/include/soc/pci_devs.h | 4 ++++
 4 files changed, 13 insertions(+)

diff --git a/src/soc/intel/pantherlake/acpi.c b/src/soc/intel/pantherlake/acpi.c
index 5df3ef928d..1c965f411e 100644
--- a/src/soc/intel/pantherlake/acpi.c
+++ b/src/soc/intel/pantherlake/acpi.c
@@ -193,6 +193,7 @@ static struct min_sleep_state min_pci_sleep_states[] = {
 	{ PCI_DEVFN_TCSS_XDCI,	ACPI_DEVICE_SLEEP_D3 },
 	{ SA_DEVFN_TCSS_DMA0,	ACPI_DEVICE_SLEEP_D3 },
 	{ SA_DEVFN_TCSS_DMA1,	ACPI_DEVICE_SLEEP_D3 },
+	{ PCI_DEVFN_VMD,        ACPI_DEVICE_SLEEP_D3 },
 	{ PCI_DEVFN_THC0,	ACPI_DEVICE_SLEEP_D3 },
 	{ PCI_DEVFN_THC1,	ACPI_DEVICE_SLEEP_D3 },
 	{ PCH_DEVFN_XHCI,	ACPI_DEVICE_SLEEP_D3 },
diff --git a/src/soc/intel/pantherlake/chipset.cb b/src/soc/intel/pantherlake/chipset.cb
index 0f7967b184..0c57a7def6 100644
--- a/src/soc/intel/pantherlake/chipset.cb
+++ b/src/soc/intel/pantherlake/chipset.cb
@@ -86,6 +86,7 @@ chip soc/intel/pantherlake
 		device pci 0d.1 alias tcss_xdci off end
 		device pci 0d.2 alias tcss_dma0 off end
 		device pci 0d.3 alias tcss_dma1 off end
+		device pci 0e.0 alias vmd off end
 		device pci 10.0 alias thc0 off end
 		device pci 10.1 alias thc1 off end
 		device pci 12.0 alias ish off end
diff --git a/src/soc/intel/pantherlake/fsp_params.c b/src/soc/intel/pantherlake/fsp_params.c
index a78059d512..fefd3e0890 100644
--- a/src/soc/intel/pantherlake/fsp_params.c
+++ b/src/soc/intel/pantherlake/fsp_params.c
@@ -560,6 +560,12 @@ static void fill_fsps_cnvi_params(FSP_S_CONFIG *s_cfg,
 	s_cfg->CnviBtInterface = is_devfn_enabled(PCI_DEVFN_CNVI_BT) ? 2 : 1;
 }
 
+static void fill_fsps_vmd_params(FSP_S_CONFIG *s_cfg,
+				 const struct soc_intel_pantherlake_config *config)
+{
+	s_cfg->VmdEnable = is_devfn_enabled(PCI_DEVFN_VMD);
+}
+
 static void fill_fsps_pmcpd_params(FSP_S_CONFIG *s_cfg,
 				   const struct soc_intel_pantherlake_config *config)
 {
@@ -710,6 +716,7 @@ static void soc_silicon_init_params(FSP_S_CONFIG *s_cfg,
 		fill_fsps_pci_ssid_params,
 		fill_fsps_lan_params,
 		fill_fsps_cnvi_params,
+		fill_fsps_vmd_params,
 		fill_fsps_pmcpd_params,
 		fill_fsps_thc_params,
 		fill_fsps_8254_params,
diff --git a/src/soc/intel/pantherlake/include/soc/pci_devs.h b/src/soc/intel/pantherlake/include/soc/pci_devs.h
index 5c74b6d7ef..a69f4820c8 100644
--- a/src/soc/intel/pantherlake/include/soc/pci_devs.h
+++ b/src/soc/intel/pantherlake/include/soc/pci_devs.h
@@ -79,6 +79,10 @@
 #define  PCI_DEV_TCSS_DMA0	_PCI_DEV(TCSS, 2)
 #define  PCI_DEV_TCSS_DMA1	_PCI_DEV(TCSS, 3)
 
+#define PCI_DEV_SLOT_VMD	0x0e
+#define  PCI_DEVFN_VMD		_PCI_DEVFN(VMD, 0)
+#define  PCI_DEV_VMD		_PCI_DEV(VMD, 0)
+
 #define PCI_DEV_SLOT_THC	0x10
 #define  PCI_DEVFN_THC0		_PCI_DEVFN(THC, 0)
 #define  PCI_DEVFN_THC1		_PCI_DEVFN(THC, 1)

From 9aaa3e99d3c59d2aadf7dbcdf63426e9a424e1ce Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Thu, 13 Feb 2025 19:06:50 -0600
Subject: [PATCH 0123/3886] src/acpi/acpigen: Increase LENSTACK_SIZE from 10 to
 15

Some upcoming patches run up against the existing limit, which
was added 16 years ago without any justification as to the size.
Bump the size from 10 to 15, to prevent tripping the runtime assertion.

TEST=Tested with rest of patch train

Change-Id: I8362b3a63a23bea0ce47920e5d41cd2535dbc084
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86427
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
---
 src/acpi/acpigen.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/acpi/acpigen.c b/src/acpi/acpigen.c
index f682522bc8..7d24b9e131 100644
--- a/src/acpi/acpigen.c
+++ b/src/acpi/acpigen.c
@@ -1,7 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
 /* How much nesting do we support? */
-#define ACPIGEN_LENSTACK_SIZE 10
+#define ACPIGEN_LENSTACK_SIZE 15
 
 /* If you need to change this, change acpigen_pop_len too */
 #define ACPIGEN_RSVD_PKGLEN_BYTES	3

From d81378d1d7235fb4d740145e969d24ef9779b571 Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Tue, 18 Feb 2025 16:28:27 +0000
Subject: [PATCH 0124/3886] drivers/usb/intel_bluetooth: Use correct function
 to close scope

The scope should be closed with `acpigen_write_scope_end`, rather
than `acpigen_pop_len`.

Change-Id: I80df2ee1b51d7dbba85e556bee0fd7513ac933bb
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86500
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/drivers/usb/acpi/intel_bluetooth.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/drivers/usb/acpi/intel_bluetooth.c b/src/drivers/usb/acpi/intel_bluetooth.c
index 4cefcf28b6..5794a5bc37 100644
--- a/src/drivers/usb/acpi/intel_bluetooth.c
+++ b/src/drivers/usb/acpi/intel_bluetooth.c
@@ -352,5 +352,5 @@ void acpi_device_intel_bt_common(unsigned int enable_gpio, unsigned int reset_gp
 	}
 	acpigen_pop_len();
 
-	acpigen_pop_len();
+	acpigen_write_scope_end();
 }

From 7377896e119adbe0b7f30cbbbf9d682be53c0e6c Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Tue, 18 Feb 2025 20:27:19 +0000
Subject: [PATCH 0125/3886] mb/starlabs/{lite_adl,byte_adl}: Disable CNVi Audio
 Offload

Both of these boards use the Intel 9560, which does not
support audio offload so configure it accordingly.

Change-Id: Idcdbd7cc83eda50ece74ce823bef60b16b49600c
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86502
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/starlabs/byte_adl/variants/mk_ii/devicetree.cb    | 2 --
 src/mainboard/starlabs/starlite_adl/variants/mk_v/devicetree.cb | 2 --
 2 files changed, 4 deletions(-)

diff --git a/src/mainboard/starlabs/byte_adl/variants/mk_ii/devicetree.cb b/src/mainboard/starlabs/byte_adl/variants/mk_ii/devicetree.cb
index 6ba3e7de25..bbedc9657a 100644
--- a/src/mainboard/starlabs/byte_adl/variants/mk_ii/devicetree.cb
+++ b/src/mainboard/starlabs/byte_adl/variants/mk_ii/devicetree.cb
@@ -2,7 +2,6 @@ chip soc/intel/alderlake
 	# FSP UPDs
 	register "enable_c6dram"		= "true"
 	register "eist_enable"			= "true"
-	register "cnvi_bt_audio_offload"	= "true"
 	register "cnvi_bt_core"			= "true"
 	register "sagv"				= "SaGv_Enabled"
 
@@ -123,7 +122,6 @@ chip soc/intel/alderlake
 						register "type"		= "UPC_TYPE_INTERNAL"
 						register "group"	= "ACPI_PLD_GROUP(0, 5)"
 						register "is_intel_bluetooth" = "1"
-						register "cnvi_bt_audio_offload" = "1"
 						register "enable_gpio"	= "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_VGPIO_0)"
 						register "reset_gpio"	= "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A13)"
 						device ref usb2_port10 on end
diff --git a/src/mainboard/starlabs/starlite_adl/variants/mk_v/devicetree.cb b/src/mainboard/starlabs/starlite_adl/variants/mk_v/devicetree.cb
index 16603f3569..0c9b7a5dde 100644
--- a/src/mainboard/starlabs/starlite_adl/variants/mk_v/devicetree.cb
+++ b/src/mainboard/starlabs/starlite_adl/variants/mk_v/devicetree.cb
@@ -1,6 +1,5 @@
 chip soc/intel/alderlake
 	# FSP UPDs
-	register "cnvi_bt_audio_offload"	= "true"
 	register "cnvi_bt_core"			= "true"
 	register "enable_c6dram"		= "true"
 	register "eist_enable"			= "true"
@@ -108,7 +107,6 @@ chip soc/intel/alderlake
 						register "desc"		= ""CNVi Bluetooth""
 						register "type"		= "UPC_TYPE_INTERNAL"
 						register "is_intel_bluetooth" = "1"
-						register "cnvi_bt_audio_offload" = "1"
 						register "enable_gpio"	= "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_VGPIO_0)"
 						register "reset_gpio"	= "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A13)"
 						register "group"	= "ACPI_PLD_GROUP(0, 5)"

From 5776ea9d0493c5ed99298611b5a0bd755762bdf1 Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Tue, 18 Feb 2025 20:28:57 +0000
Subject: [PATCH 0126/3886] drivers/usb/intel_bluetooth: Make AOLD Method
 NotSerialized

This method only returns a package, so it does not need to be
serialized.

Change-Id: I5e61e92b0cffb28aaa070db3e9e8e2ff0e7c4251
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86503
Reviewed-by: Andy Ebrahiem <ahmet.ebrahiem@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
---
 src/drivers/usb/acpi/intel_bluetooth.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/drivers/usb/acpi/intel_bluetooth.c b/src/drivers/usb/acpi/intel_bluetooth.c
index 5794a5bc37..d83bcb285d 100644
--- a/src/drivers/usb/acpi/intel_bluetooth.c
+++ b/src/drivers/usb/acpi/intel_bluetooth.c
@@ -230,7 +230,7 @@ void acpi_device_intel_bt(unsigned int reset_gpio, unsigned int enable_gpio, boo
 	acpigen_pop_len();
 
 /*
- *	Method (AOLD, 0, Serialized)
+ *	Method (AOLD, 0, NotSerialized)
  *	{
  *		Name (AODS, Package (0x03)
  *		{
@@ -242,7 +242,7 @@ void acpi_device_intel_bt(unsigned int reset_gpio, unsigned int enable_gpio, boo
  *		Return (AODS)
  *	}
  */
-	acpigen_write_method_serialized("AOLD", 0);
+	acpigen_write_method("AOLD", 0);
 	{
 		acpigen_write_name("AODS");
 		acpigen_write_package(3);

From 741017dfe85c633d1897710f33e4249cd4f108c0 Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Tue, 18 Feb 2025 20:30:14 +0000
Subject: [PATCH 0127/3886] drivers/usb/acpi: Make SBTE Method NotSerialized

This method calls STXS and CTXS, which are both serialized so this
method itself does not need to be serialized.

Change-Id: Ia46eaa8746bcff5a57831c14a2845139116b01da
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86504
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Andy Ebrahiem <ahmet.ebrahiem@9elements.com>
---
 src/drivers/usb/acpi/intel_bluetooth.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/drivers/usb/acpi/intel_bluetooth.c b/src/drivers/usb/acpi/intel_bluetooth.c
index d83bcb285d..2678d52faf 100644
--- a/src/drivers/usb/acpi/intel_bluetooth.c
+++ b/src/drivers/usb/acpi/intel_bluetooth.c
@@ -267,7 +267,7 @@ void acpi_device_intel_bt_common(unsigned int enable_gpio, unsigned int reset_gp
 	acpigen_write_mutex("CNMT", 0);
 
 /*
- *	Method (SBTE, 1, Serialized)
+ *	Method (SBTE, 1, NotSerialized)
  *	{
  *		If (Arg0 == 1)
  *		{
@@ -277,7 +277,7 @@ void acpi_device_intel_bt_common(unsigned int enable_gpio, unsigned int reset_gp
  *		}
  *	}
  */
-	acpigen_write_method_serialized("SBTE", 1);
+	acpigen_write_method("SBTE", 1);
 	{
 		if (enable_gpio) {
 			acpigen_write_if_lequal_op_int(ARG0_OP, 1);

From 017260c5345e9db5b79972676773b55dd7dfe8cb Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Tue, 18 Feb 2025 20:32:34 +0000
Subject: [PATCH 0128/3886] driver/usb/intel_bluetooth: Set BTRK to
 NotSerialized

This method calls STXS and CTXS, which are both serialized so this
method itself does not need to be serialized.

Change-Id: I6d9d6d3b765bba918c08f64458bd1fdad18eff18
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86505
Reviewed-by: Andy Ebrahiem <ahmet.ebrahiem@9elements.com>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/drivers/usb/acpi/intel_bluetooth.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/drivers/usb/acpi/intel_bluetooth.c b/src/drivers/usb/acpi/intel_bluetooth.c
index 2678d52faf..a979b42ebf 100644
--- a/src/drivers/usb/acpi/intel_bluetooth.c
+++ b/src/drivers/usb/acpi/intel_bluetooth.c
@@ -311,7 +311,7 @@ void acpi_device_intel_bt_common(unsigned int enable_gpio, unsigned int reset_gp
 	acpigen_pop_len();
 
 /*
- *	Method (BTRK, 1, Serialized)
+ *	Method (BTRK, 1, NotSerialized)
  *	{
  *		If (Arg0 == 1)
  *		{
@@ -321,7 +321,7 @@ void acpi_device_intel_bt_common(unsigned int enable_gpio, unsigned int reset_gp
  *		}
  *	}
  */
-	acpigen_write_method_serialized("BTRK", 1);
+	acpigen_write_method("BTRK", 1);
 	{
 		acpigen_write_if_lequal_op_int(ARG0_OP, 1);
 		{

From e2ea7f22c6355d15515c049ca0dc4352173a0c01 Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Tue, 18 Feb 2025 20:51:47 +0000
Subject: [PATCH 0129/3886] soc/intel/cnvi: Remove _S0W and DSW Methods

coreboot already has a way to configure wakeup from wireless through
the `wifi/generic` driver, so remove these to avoid conflicts.

Change-Id: I744ef37690b7a2478ec29a43b987b43592df2235
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86506
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/soc/intel/common/block/cnvi/cnvi.c | 20 --------------------
 1 file changed, 20 deletions(-)

diff --git a/src/soc/intel/common/block/cnvi/cnvi.c b/src/soc/intel/common/block/cnvi/cnvi.c
index 87e9bbb72e..a4263af646 100644
--- a/src/soc/intel/common/block/cnvi/cnvi.c
+++ b/src/soc/intel/common/block/cnvi/cnvi.c
@@ -86,19 +86,6 @@ static void cnvw_fill_ssdt(const struct device *dev)
 	acpigen_write_field("CWAR", fields2, ARRAY_SIZE(fields2),
 		FIELD_BYTEACC | FIELD_NOLOCK | FIELD_PRESERVE);
 
-/*
- *	Method (_S0W, 0, NotSerialized)  // _S0W: S0 Device Wake State
- *	{
- *		Return (ACPI_DEVICE_SLEEP_D3_HOT)
- *	}
- */
-	acpigen_write_method("_S0W", 0);
-	{
-		acpigen_write_return_integer(ACPI_DEVICE_SLEEP_D3_HOT);
-	}
-	acpigen_pop_len();
-
-
 /*
  *	Name (RSTT, Zero)
  */
@@ -326,10 +313,6 @@ static void cnvw_fill_ssdt(const struct device *dev)
  *	Method (_PS3, 0, Serialized)
  *	{
  *	}
- *
- *	Method (_DSW, 3)
- *	{
- *	}
  */
 	acpigen_write_method_serialized("_PS0", 0);
 	acpigen_pop_len();
@@ -337,9 +320,6 @@ static void cnvw_fill_ssdt(const struct device *dev)
 	acpigen_write_method_serialized("_PS3", 0);
 	acpigen_pop_len();
 
-	acpigen_write_method("_DSW", 3);
-	acpigen_pop_len();
-
 /*
  *	Method (CFLR, 0, NotSerialized)
  *	{

From ad81102108ead197276d0a8dba83703b6facf817 Mon Sep 17 00:00:00 2001
From: Brian Hsu <Brian_Hsu@pegatron.corp-partner.google.com>
Date: Tue, 11 Feb 2025 14:33:03 +0800
Subject: [PATCH 0130/3886] mb/google/nissa/var/guren: Create empty variant for
 guren

Create the template files to a new directory named for the guren variant.

BUG=b:397149037
BRANCH=firmware-nissa-15217.B
TEST=None

Change-Id: I23803aaceb122d2b9e3c2215914643593afa1246
Signed-off-by: Brian Hsu <Brian_Hsu@pegatron.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86492
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
---
 src/mainboard/google/brya/Kconfig                     |  7 +++++++
 src/mainboard/google/brya/Kconfig.name                |  3 +++
 .../google/brya/variants/guren/include/variant/ec.h   |  8 ++++++++
 .../google/brya/variants/guren/include/variant/gpio.h |  8 ++++++++
 .../google/brya/variants/guren/memory/Makefile.mk     |  5 +++++
 .../brya/variants/guren/memory/dram_id.generated.txt  |  1 +
 .../brya/variants/guren/memory/mem_parts_used.txt     | 11 +++++++++++
 .../google/brya/variants/guren/overridetree.cb        |  6 ++++++
 8 files changed, 49 insertions(+)
 create mode 100644 src/mainboard/google/brya/variants/guren/include/variant/ec.h
 create mode 100644 src/mainboard/google/brya/variants/guren/include/variant/gpio.h
 create mode 100644 src/mainboard/google/brya/variants/guren/memory/Makefile.mk
 create mode 100644 src/mainboard/google/brya/variants/guren/memory/dram_id.generated.txt
 create mode 100644 src/mainboard/google/brya/variants/guren/memory/mem_parts_used.txt
 create mode 100644 src/mainboard/google/brya/variants/guren/overridetree.cb

diff --git a/src/mainboard/google/brya/Kconfig b/src/mainboard/google/brya/Kconfig
index 213d49967c..fc18f8f660 100644
--- a/src/mainboard/google/brya/Kconfig
+++ b/src/mainboard/google/brya/Kconfig
@@ -295,6 +295,9 @@ config BOARD_GOOGLE_GOTHRAX
 	select DRIVERS_I2C_SX9324_SUPPORT_LEGACY_LINUX_DRIVER
 	select HAVE_WWAN_POWER_SEQUENCE
 
+config BOARD_GOOGLE_GUREN
+	select BOARD_GOOGLE_BASEBOARD_NISSA
+
 config BOARD_GOOGLE_HADES
 	select BOARD_GOOGLE_BASEBOARD_HADES
 	select DRIVERS_GENESYSLOGIC_GL9755
@@ -766,6 +769,7 @@ config DRIVER_TPM_I2C_BUS
 	default 0x1 if BOARD_GOOGLE_GLADIOS
 	default 0x0 if BOARD_GOOGLE_GLASSWAY
 	default 0x0 if BOARD_GOOGLE_GOTHRAX
+	default 0x0 if BOARD_GOOGLE_GUREN
 	default 0x3 if BOARD_GOOGLE_HADES
 	default 0x0 if BOARD_GOOGLE_JOXER
 	default 0x1 if BOARD_GOOGLE_KANO
@@ -847,6 +851,7 @@ config TPM_TIS_ACPI_INTERRUPT
 	default 13 if BOARD_GOOGLE_GLADIOS
 	default 13 if BOARD_GOOGLE_GLASSWAY
 	default 13 if BOARD_GOOGLE_GOTHRAX
+	default 13 if BOARD_GOOGLE_GUREN
 	default 20 if BOARD_GOOGLE_HADES # GPE0_DW0_20 (GPP_A20_IRQ)
 	default 13 if BOARD_GOOGLE_JOXER
 	default 13 if BOARD_GOOGLE_KANO
@@ -932,6 +937,7 @@ config MAINBOARD_PART_NUMBER
 	default "Gladios" if BOARD_GOOGLE_GLADIOS
 	default "Glassway" if BOARD_GOOGLE_GLASSWAY
 	default "Gothrax" if BOARD_GOOGLE_GOTHRAX
+	default "Guren" if BOARD_GOOGLE_GUREN
 	default "Hades" if BOARD_GOOGLE_HADES
 	default "Joxer" if BOARD_GOOGLE_JOXER
 	default "Kano" if BOARD_GOOGLE_KANO
@@ -1006,6 +1012,7 @@ config VARIANT_DIR
 	default "gladios" if BOARD_GOOGLE_GLADIOS
 	default "glassway" if BOARD_GOOGLE_GLASSWAY
 	default "gothrax" if BOARD_GOOGLE_GOTHRAX
+	default "guren" if BOARD_GOOGLE_GUREN
 	default "hades" if BOARD_GOOGLE_HADES
 	default "joxer" if BOARD_GOOGLE_JOXER
 	default "kano" if BOARD_GOOGLE_KANO
diff --git a/src/mainboard/google/brya/Kconfig.name b/src/mainboard/google/brya/Kconfig.name
index 50bfaeff34..6007aa2c2a 100644
--- a/src/mainboard/google/brya/Kconfig.name
+++ b/src/mainboard/google/brya/Kconfig.name
@@ -68,6 +68,9 @@ config BOARD_GOOGLE_GLASSWAY
 config BOARD_GOOGLE_GOTHRAX
 	bool "->  Gothrax"
 
+config BOARD_GOOGLE_GUREN
+	bool "->  Guren"
+
 config BOARD_GOOGLE_HADES
 	bool "->  Hades"
 
diff --git a/src/mainboard/google/brya/variants/guren/include/variant/ec.h b/src/mainboard/google/brya/variants/guren/include/variant/ec.h
new file mode 100644
index 0000000000..7a2a6ff8b7
--- /dev/null
+++ b/src/mainboard/google/brya/variants/guren/include/variant/ec.h
@@ -0,0 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#ifndef __VARIANT_EC_H__
+#define __VARIANT_EC_H__
+
+#include <baseboard/ec.h>
+
+#endif
diff --git a/src/mainboard/google/brya/variants/guren/include/variant/gpio.h b/src/mainboard/google/brya/variants/guren/include/variant/gpio.h
new file mode 100644
index 0000000000..c4fe342621
--- /dev/null
+++ b/src/mainboard/google/brya/variants/guren/include/variant/gpio.h
@@ -0,0 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#ifndef VARIANT_GPIO_H
+#define VARIANT_GPIO_H
+
+#include <baseboard/gpio.h>
+
+#endif
diff --git a/src/mainboard/google/brya/variants/guren/memory/Makefile.mk b/src/mainboard/google/brya/variants/guren/memory/Makefile.mk
new file mode 100644
index 0000000000..eace2e443e
--- /dev/null
+++ b/src/mainboard/google/brya/variants/guren/memory/Makefile.mk
@@ -0,0 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+# This is an auto-generated file. Do not edit!!
+# Add memory parts in mem_parts_used.txt and run spd_tools to regenerate.
+
+SPD_SOURCES = placeholder
diff --git a/src/mainboard/google/brya/variants/guren/memory/dram_id.generated.txt b/src/mainboard/google/brya/variants/guren/memory/dram_id.generated.txt
new file mode 100644
index 0000000000..fa247902ee
--- /dev/null
+++ b/src/mainboard/google/brya/variants/guren/memory/dram_id.generated.txt
@@ -0,0 +1 @@
+DRAM Part Name                 ID to assign
diff --git a/src/mainboard/google/brya/variants/guren/memory/mem_parts_used.txt b/src/mainboard/google/brya/variants/guren/memory/mem_parts_used.txt
new file mode 100644
index 0000000000..2499005682
--- /dev/null
+++ b/src/mainboard/google/brya/variants/guren/memory/mem_parts_used.txt
@@ -0,0 +1,11 @@
+# This is a CSV file containing a list of memory parts used by this variant.
+# One part per line with an optional fixed ID in column 2.
+# Only include a fixed ID if it is required for legacy reasons!
+# Generated IDs are dependent on the order of parts in this file,
+# so new parts must always be added at the end of the file!
+#
+# Generate an updated Makefile.mk and dram_id.generated.txt by running the
+# part_id_gen tool from util/spd_tools.
+# See util/spd_tools/README.md for more details and instructions.
+
+# Part Name
diff --git a/src/mainboard/google/brya/variants/guren/overridetree.cb b/src/mainboard/google/brya/variants/guren/overridetree.cb
new file mode 100644
index 0000000000..4f2c04a57a
--- /dev/null
+++ b/src/mainboard/google/brya/variants/guren/overridetree.cb
@@ -0,0 +1,6 @@
+chip soc/intel/alderlake
+
+        device domain 0 on
+        end
+
+end

From 584cdc99b708eeee8e9930569c9ba51e524c4368 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Micha=C5=82=20Kope=C4=87?= <michal.kopec@3mdeb.com>
Date: Mon, 27 May 2024 11:20:12 +0200
Subject: [PATCH 0131/3886] mb/novacustom: add V5x0TU board (Meteor Lake)
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

NovaCustom (Clevo) V5x0TU are two laptops with Intel Core Ultra (Meteor
Lake) series processors.

Two variants (V540TU and V560TU) are supported. Their EC firmware is
different due to keyboard layout changes. On coreboot's side, the only
difference are SMBIOS strings.

Working:
- DDR5 SODIMM in slot RAM2
- M.2 2280 PCIe slots
- Thunderbolt, USB ports
- Video outputs in OS and firmware via FSP GOP
- I2C touchpad, webcam, SD Card reader
- S0ix
- Booting Ubuntu 24.04 with edk2 UefiPayload
- Vboot, TPM measured boot

VBT was extracted from Clevo Insyde firmware, version v1.07.2.

Change-Id: I82c73ddb1e76a9baf9b97e13124aa249ae1c2771
Signed-off-by: Michał Kopeć <michal.kopec@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82673
Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/novacustom/Kconfig              |  17 +
 src/mainboard/novacustom/Kconfig.name         |   4 +
 src/mainboard/novacustom/mtl-h/Kconfig        | 105 ++++
 src/mainboard/novacustom/mtl-h/Kconfig.name   |   7 +
 src/mainboard/novacustom/mtl-h/Makefile.mk    |  14 +
 .../novacustom/mtl-h/acpi/backlight.asl       |  32 +
 .../novacustom/mtl-h/acpi/mainboard.asl       |  11 +
 src/mainboard/novacustom/mtl-h/board_info.txt |   6 +
 src/mainboard/novacustom/mtl-h/bootblock.c    |   9 +
 src/mainboard/novacustom/mtl-h/cmos.default   |   3 +
 src/mainboard/novacustom/mtl-h/cmos.layout    |  46 ++
 src/mainboard/novacustom/mtl-h/data.vbt       | Bin 0 -> 7680 bytes
 src/mainboard/novacustom/mtl-h/devicetree.cb  | 316 ++++++++++
 src/mainboard/novacustom/mtl-h/dsdt.asl       |  34 ++
 src/mainboard/novacustom/mtl-h/fadt.c         |   8 +
 src/mainboard/novacustom/mtl-h/gpio.c         | 574 ++++++++++++++++++
 src/mainboard/novacustom/mtl-h/gpio_early.c   |  16 +
 src/mainboard/novacustom/mtl-h/hda_verb.c     |  42 ++
 .../novacustom/mtl-h/include/mainboard/gpio.h |  17 +
 src/mainboard/novacustom/mtl-h/ramstage.c     |  42 ++
 src/mainboard/novacustom/mtl-h/romstage.c     |  31 +
 src/mainboard/novacustom/mtl-h/vboot-rwab.fmd |  49 ++
 22 files changed, 1383 insertions(+)
 create mode 100644 src/mainboard/novacustom/Kconfig
 create mode 100644 src/mainboard/novacustom/Kconfig.name
 create mode 100644 src/mainboard/novacustom/mtl-h/Kconfig
 create mode 100644 src/mainboard/novacustom/mtl-h/Kconfig.name
 create mode 100644 src/mainboard/novacustom/mtl-h/Makefile.mk
 create mode 100644 src/mainboard/novacustom/mtl-h/acpi/backlight.asl
 create mode 100644 src/mainboard/novacustom/mtl-h/acpi/mainboard.asl
 create mode 100644 src/mainboard/novacustom/mtl-h/board_info.txt
 create mode 100644 src/mainboard/novacustom/mtl-h/bootblock.c
 create mode 100644 src/mainboard/novacustom/mtl-h/cmos.default
 create mode 100644 src/mainboard/novacustom/mtl-h/cmos.layout
 create mode 100644 src/mainboard/novacustom/mtl-h/data.vbt
 create mode 100644 src/mainboard/novacustom/mtl-h/devicetree.cb
 create mode 100644 src/mainboard/novacustom/mtl-h/dsdt.asl
 create mode 100644 src/mainboard/novacustom/mtl-h/fadt.c
 create mode 100644 src/mainboard/novacustom/mtl-h/gpio.c
 create mode 100644 src/mainboard/novacustom/mtl-h/gpio_early.c
 create mode 100644 src/mainboard/novacustom/mtl-h/hda_verb.c
 create mode 100644 src/mainboard/novacustom/mtl-h/include/mainboard/gpio.h
 create mode 100644 src/mainboard/novacustom/mtl-h/ramstage.c
 create mode 100644 src/mainboard/novacustom/mtl-h/romstage.c
 create mode 100644 src/mainboard/novacustom/mtl-h/vboot-rwab.fmd

diff --git a/src/mainboard/novacustom/Kconfig b/src/mainboard/novacustom/Kconfig
new file mode 100644
index 0000000000..e159480899
--- /dev/null
+++ b/src/mainboard/novacustom/Kconfig
@@ -0,0 +1,17 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
+if VENDOR_NOVACUSTOM
+
+choice
+	prompt "Mainboard model"
+
+source "src/mainboard/novacustom/*/Kconfig.name"
+
+endchoice
+
+source "src/mainboard/novacustom/*/Kconfig"
+
+config MAINBOARD_VENDOR
+	default "NovaCustom"
+
+endif # VENDOR_NOVACUSTOM
diff --git a/src/mainboard/novacustom/Kconfig.name b/src/mainboard/novacustom/Kconfig.name
new file mode 100644
index 0000000000..242b3bbf3f
--- /dev/null
+++ b/src/mainboard/novacustom/Kconfig.name
@@ -0,0 +1,4 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
+config VENDOR_NOVACUSTOM
+	bool "NovaCustom"
diff --git a/src/mainboard/novacustom/mtl-h/Kconfig b/src/mainboard/novacustom/mtl-h/Kconfig
new file mode 100644
index 0000000000..5d608b40ac
--- /dev/null
+++ b/src/mainboard/novacustom/mtl-h/Kconfig
@@ -0,0 +1,105 @@
+config BOARD_NOVACUSTOM_MTLH_COMMON
+	def_bool n
+	select BOARD_ROMSIZE_KB_32768
+	select DRIVERS_GENERIC_BAYHUB_LV2
+	select DRIVERS_GFX_GENERIC
+	select DRIVERS_I2C_HID
+	select DRIVERS_INTEL_PMC
+	select DRIVERS_INTEL_USB4_RETIMER
+	select DRIVERS_WIFI_GENERIC
+	select EC_DASHARO_EC
+	select HAVE_ACPI_TABLES
+	select HAVE_CMOS_DEFAULT
+	select HAVE_OPTION_TABLE
+	select INTEL_GMA_HAVE_VBT
+	select MAINBOARD_HAS_TPM2
+	select MEMORY_MAPPED_TPM
+	select NO_UART_ON_SUPERIO
+	select PMC_IPC_ACPI_INTERFACE
+	select SOC_INTEL_COMMON_BLOCK_HDA_VERB
+	select SOC_INTEL_CRASHLOG
+	select SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES
+	select SOC_INTEL_METEORLAKE_U_H
+	select SPD_READ_BY_WORD
+	select SYSTEM_TYPE_LAPTOP
+
+config BOARD_NOVACUSTOM_V5X0TU_BASE
+	bool
+	select BOARD_NOVACUSTOM_MTLH_COMMON
+	select MAINBOARD_USES_IFD_GBE_REGION
+
+config BOARD_NOVACUSTOM_V540TU
+	bool
+	select BOARD_NOVACUSTOM_V5X0TU_BASE
+
+config BOARD_NOVACUSTOM_V560TU
+	bool
+	select BOARD_NOVACUSTOM_V5X0TU_BASE
+
+if BOARD_NOVACUSTOM_MTLH_COMMON
+
+config MAINBOARD_DIR
+	default "novacustom/mtl-h"
+
+config MAINBOARD_PART_NUMBER
+	default "V54x_6x_TU" if BOARD_NOVACUSTOM_V5X0TU_BASE
+
+config MAINBOARD_SMBIOS_PRODUCT_NAME
+	default "V54x_6x_TU" if BOARD_NOVACUSTOM_V5X0TU_BASE
+
+config MAINBOARD_SMBIOS_MANUFACTURER
+	default "Notebook"
+
+config MAINBOARD_VERSION
+	default "V540TU" if BOARD_NOVACUSTOM_V540TU
+	default "V560TU" if BOARD_NOVACUSTOM_V560TU
+
+config MAINBOARD_FAMILY
+	string
+	default "Not Applicable" # Match Insyde firmware, for Windows Update
+
+config CBFS_SIZE
+	default 0xA00000
+
+config CONSOLE_POST
+	default y
+
+config DIMM_SPD_SIZE
+	default 1024
+
+config POST_DEVICE
+	default n
+
+config USE_PM_ACPI_TIMER
+	default n
+
+config VBOOT
+	select GBB_FLAG_DISABLE_EC_SOFTWARE_SYNC
+	select GBB_FLAG_DISABLE_FWMP
+	select GBB_FLAG_DISABLE_LID_SHUTDOWN
+	select GBB_FLAG_DISABLE_PD_SOFTWARE_SYNC
+	select HAS_RECOVERY_MRC_CACHE
+	select VBOOT_ALWAYS_ENABLE_DISPLAY
+	select VBOOT_CLEAR_RECOVERY_IN_RAMSTAGE
+	select VBOOT_MOCK_SECDATA
+	select VBOOT_NO_BOARD_SUPPORT
+
+config VBOOT_SLOTS_RW_AB
+	default y if VBOOT
+
+config VBOOT_VBNV_OFFSET
+	default 0x28
+
+config TPM_PIRQ
+	default 0x61 # GPP_E01
+
+config FMDFILE
+	default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/vboot-rwab.fmd" if VBOOT && VBOOT_SLOTS_RW_AB
+
+config SOC_INTEL_CSE_SEND_EOP_EARLY
+	default n
+
+config EC_DASHARO_EC_FLASH_SIZE
+	default 0x40000
+
+endif
diff --git a/src/mainboard/novacustom/mtl-h/Kconfig.name b/src/mainboard/novacustom/mtl-h/Kconfig.name
new file mode 100644
index 0000000000..ff079a0f52
--- /dev/null
+++ b/src/mainboard/novacustom/mtl-h/Kconfig.name
@@ -0,0 +1,7 @@
+comment "Meteor Lake H"
+
+config BOARD_NOVACUSTOM_V540TU
+	bool "V540TU (14\")"
+
+config BOARD_NOVACUSTOM_V560TU
+	bool "V560TU (16\")"
diff --git a/src/mainboard/novacustom/mtl-h/Makefile.mk b/src/mainboard/novacustom/mtl-h/Makefile.mk
new file mode 100644
index 0000000000..9a35f5a80b
--- /dev/null
+++ b/src/mainboard/novacustom/mtl-h/Makefile.mk
@@ -0,0 +1,14 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
+CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/include
+
+bootblock-y += bootblock.c
+bootblock-y += gpio_early.c
+
+romstage-y += romstage.c
+
+ramstage-y += ramstage.c
+ramstage-y += hda_verb.c
+ramstage-y += gpio.c
+
+ramstage-$(CONFIG_HAVE_ACPI_TABLES) += fadt.c
diff --git a/src/mainboard/novacustom/mtl-h/acpi/backlight.asl b/src/mainboard/novacustom/mtl-h/acpi/backlight.asl
new file mode 100644
index 0000000000..01fa83ea61
--- /dev/null
+++ b/src/mainboard/novacustom/mtl-h/acpi/backlight.asl
@@ -0,0 +1,32 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <drivers/intel/gma/acpi/gma.asl>
+
+Scope (GFX0)
+{
+	Name (BRIG, Package (23) {
+		40, /* default AC */
+		40, /* default Battery */
+		0,
+		5,
+		10,
+		15,
+		20,
+		25,
+		30,
+		35,
+		40,
+		45,
+		50,
+		55,
+		60,
+		65,
+		70,
+		75,
+		80,
+		85,
+		90,
+		95,
+		100
+	})
+}
diff --git a/src/mainboard/novacustom/mtl-h/acpi/mainboard.asl b/src/mainboard/novacustom/mtl-h/acpi/mainboard.asl
new file mode 100644
index 0000000000..ec229038c2
--- /dev/null
+++ b/src/mainboard/novacustom/mtl-h/acpi/mainboard.asl
@@ -0,0 +1,11 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#define EC_GPE_SCI 0x6E
+#define EC_GPE_SWI 0x6B
+#include <ec/dasharo/ec/acpi/ec.asl>
+
+Scope (\_SB) {
+	Scope (PCI0) {
+		#include "backlight.asl"
+	}
+}
diff --git a/src/mainboard/novacustom/mtl-h/board_info.txt b/src/mainboard/novacustom/mtl-h/board_info.txt
new file mode 100644
index 0000000000..4b3db962d5
--- /dev/null
+++ b/src/mainboard/novacustom/mtl-h/board_info.txt
@@ -0,0 +1,6 @@
+Vendor name: NovaCustom
+Category: laptop
+ROM package: WSON-8
+ROM protocol: SPI
+ROM socketed: n
+Flashrom support: y
diff --git a/src/mainboard/novacustom/mtl-h/bootblock.c b/src/mainboard/novacustom/mtl-h/bootblock.c
new file mode 100644
index 0000000000..8d06adc9d7
--- /dev/null
+++ b/src/mainboard/novacustom/mtl-h/bootblock.c
@@ -0,0 +1,9 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <bootblock_common.h>
+#include <mainboard/gpio.h>
+
+void bootblock_mainboard_early_init(void)
+{
+	mainboard_configure_early_gpios();
+}
diff --git a/src/mainboard/novacustom/mtl-h/cmos.default b/src/mainboard/novacustom/mtl-h/cmos.default
new file mode 100644
index 0000000000..62715bc6ba
--- /dev/null
+++ b/src/mainboard/novacustom/mtl-h/cmos.default
@@ -0,0 +1,3 @@
+boot_option=Fallback
+debug_level=Debug
+me_state=Enable
diff --git a/src/mainboard/novacustom/mtl-h/cmos.layout b/src/mainboard/novacustom/mtl-h/cmos.layout
new file mode 100644
index 0000000000..66b8665b47
--- /dev/null
+++ b/src/mainboard/novacustom/mtl-h/cmos.layout
@@ -0,0 +1,46 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
+entries
+
+0	304	r	0	reserved_memory
+
+# coreboot config options: ramtop
+304	80	h	0	ramtop
+
+# RTC_BOOT_BYTE (coreboot hardcoded)
+384	1	e	4	boot_option
+388	4	h	0	reboot_counter
+
+# RTC_CLK_ALTCENTURY
+400	8	r	0	century
+
+412	4	e	6	debug_level
+416	1	e	2	me_state
+417	3	h	0	me_state_counter
+
+# Vboot non-volatile data
+432	128	r	0	vbnv
+
+984	16	h	0	check_sum
+
+enumerations
+
+2	0	Enable
+2	1	Disable
+
+4	0	Fallback
+4	1	Normal
+
+6	0	Emergency
+6	1	Alert
+6	2	Critical
+6	3	Error
+6	4	Warning
+6	5	Notice
+6	6	Info
+6	7	Debug
+6	8	Spew
+
+checksums
+
+checksum 408 431 984
diff --git a/src/mainboard/novacustom/mtl-h/data.vbt b/src/mainboard/novacustom/mtl-h/data.vbt
new file mode 100644
index 0000000000000000000000000000000000000000..59c3c783a59dbc11cd961b3de3b40557542db287
GIT binary patch
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diff --git a/src/mainboard/novacustom/mtl-h/devicetree.cb b/src/mainboard/novacustom/mtl-h/devicetree.cb
new file mode 100644
index 0000000000..663d6940dc
--- /dev/null
+++ b/src/mainboard/novacustom/mtl-h/devicetree.cb
@@ -0,0 +1,316 @@
+chip soc/intel/meteorlake
+	# Common SoC configuration
+	register "common_soc_config" = "{
+		// Touchpad I2C bus
+		.i2c[0] = {
+			.speed = I2C_SPEED_FAST,
+			.rise_time_ns = 80,
+			.fall_time_ns = 110,
+		},
+	}"
+
+	# Enable Enhanced Intel SpeedStep
+	register "eist_enable" = "1"
+
+	# Enable S0ix / Modern Standby
+	register "s0ix_enable" = "1"
+
+	# SaGv configuration
+	register "sagv" = "SAGV_ENABLED"
+
+	# Disable C1 and Package C-state auto-demotion
+	register "disable_c1_state_auto_demotion" = "1"
+	register "disable_package_c_state_demotion" = "1"
+
+	# Enable Energy Reporting
+	register "pch_pm_energy_report_enable" = "1"
+
+	# Thermal
+	register "tcc_offset" = "10" # TCC of 100C
+
+	register "usb2_ports" = "{
+		[0] = USB2_PORT_LONG(OC_SKIP),	 /* USB Type-A Port 1 (Left) */
+		[1] = USB2_PORT_TYPE_C(OC_SKIP), /* USB Type-C Port 1 (Non-TBT) */
+		[2] = USB2_PORT_MID(OC_SKIP),	 /* USB Type-A Port 2 (Right) */
+		[5] = USB2_PORT_TYPE_C(OC_SKIP), /* USB Type-C Port 2 (TBT) */
+		[6] = USB2_PORT_LONG(OC_SKIP),	 /* Integrated Camera */
+		[9] = USB2_PORT_MID(OC_SKIP),	 /* Bluetooth on M.2 2230 */
+	}"
+
+	register "usb3_ports" = "{
+		[0] = USB3_PORT_DEFAULT(OC_SKIP), /* USB Type-A Port 1 (Left) */
+		[1] = USB3_PORT_DEFAULT(OC_SKIP), /* USB Type-A Port 2 (Right) */
+	}"
+
+	register "tcss_ports" = "{
+		[0] = TCSS_PORT_DEFAULT(OC_SKIP), /* USB Type-C Port 1 (TBT) */
+		[1] = TCSS_PORT_DEFAULT(OC_SKIP), /* USB Type-C Port 2 (Non-TBT) */
+	}"
+
+	device cpu_cluster 0 on end
+	device domain 0 on
+		subsystemid 0x1558 0xa743 inherit
+		device ref system_agent on end
+		device ref igpu on
+			register "ddi_port_A_config" = "1"
+			register "ddi_ports_config" = "{
+				[DDI_PORT_A] = DDI_ENABLE_HPD, 			/* eDP */
+				[DDI_PORT_2] = DDI_ENABLE_DDC | DDI_ENABLE_HPD,	/* HDMI 2.1 */
+			}"
+			chip drivers/gfx/generic
+				register "device_count" = "6"
+				# DDIA for eDP
+				register "device[0].name" = ""LCD0""
+				register "device[0].type" = "panel"
+				# DDIB unused
+				register "device[1].name" = ""DD01""
+				# TCP0 for Thunderbolt 4
+				register "device[2].name" = ""DD02""
+				register "device[2].use_pld" = "true"
+				register "device[2].pld" = "ACPI_PLD_TYPE_C(RIGHT, CENTER, ACPI_PLD_GROUP(1, 1))"
+				# TCP1 unused
+				register "device[3].name" = ""DD03""
+				# TCP2 for HDMI 2.1
+				register "device[4].name" = ""DD04""
+				# TCP3 unused
+				register "device[5].name" = ""DD05""
+				device generic 0 on end
+			end
+		end
+		device ref dtt on end
+		device ref pcie_rp10 on # M.2 2280 #2
+			register "pcie_rp[PCH_RP(10)]" = "{
+				.clk_src = 8,
+				.clk_req = 8,
+				.flags = PCIE_RP_LTR | PCIE_RP_AER | PCIE_RP_CLK_REQ_DETECT,
+			}"
+			chip soc/intel/common/block/pcie/rtd3
+				register "is_storage" = "true"
+				register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D01)"
+				register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A13)"
+				register "srcclk_pin" = "8"
+				device generic 0 on end
+			end
+			smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M.2/M 2280 (J_SSD2)" "SlotDataBusWidth4X"
+		end
+		device ref pcie_rp11 on # M.2 2280 #1
+			register "pcie_rp[PCH_RP(11)]" = "{
+				.clk_src = 7,
+				.clk_req = 7,
+				.flags = PCIE_RP_LTR | PCIE_RP_AER | PCIE_RP_CLK_REQ_DETECT,
+			}"
+			chip soc/intel/common/block/pcie/rtd3
+				register "is_storage" = "true"
+				register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D05)"
+				register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D02)"
+				register "srcclk_pin" = "7"
+				device generic 0 on end
+			end
+			smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M.2/M 2280 (J_SSD1)" "SlotDataBusWidth4X"
+		end
+		device ref tbt_pcie_rp0 on end
+		device ref gna on end
+		device ref crashlog on end
+		device ref vpu on end
+		device ref tcss_xhci on
+			chip drivers/usb/acpi
+				device ref tcss_root_hub on
+					chip drivers/usb/acpi
+						register "desc" = ""USB3 Type-C Port 1 (TBT)""
+						register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
+						register "use_custom_pld" = "true"
+						register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, CENTER, ACPI_PLD_GROUP(1, 1))"
+						device ref tcss_usb3_port0 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB3 Type-C Port 2""
+						register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
+						register "use_custom_pld" = "true"
+						register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, LEFT, ACPI_PLD_GROUP(1, 2))"
+						device ref tcss_usb3_port1 on end
+					end
+				end
+			end
+		end
+		device ref tcss_dma0 on
+			chip drivers/intel/usb4/retimer
+				register "dfp[0].power_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B21)"
+				use tcss_usb3_port0 as dfp[0].typec_port
+				device generic 0 on end
+			end
+		end
+		device ref ioe_shared_sram on end
+		device ref xhci on
+			chip drivers/usb/acpi
+				device ref xhci_root_hub on
+					chip drivers/usb/acpi
+						register "desc" = ""USB2 Type-A Left""
+						register "type" = "UPC_TYPE_A"
+						register "use_custom_pld" = "true"
+						register "custom_pld" = "ACPI_PLD_TYPE_A(LEFT, CENTER, ACPI_PLD_GROUP(2, 1))"
+						device ref usb2_port1 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB2 Type-C Port 2""
+						register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
+						register "use_custom_pld" = "true"
+						register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, LEFT, ACPI_PLD_GROUP(1, 2))"
+						device ref usb2_port2 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB2 Type-A Right""
+						register "type" = "UPC_TYPE_A"
+						register "use_custom_pld" = "true"
+						register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, RIGHT, ACPI_PLD_GROUP(1, 3))"
+						device ref usb2_port3 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB2 Type-C Port 1 (TBT)""
+						register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
+						register "use_custom_pld" = "true"
+						register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, CENTER, ACPI_PLD_GROUP(1, 2))"
+						device ref usb2_port6 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB2 Camera""
+						register "type" = "UPC_TYPE_INTERNAL"
+						device ref usb2_port7 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB2 Bluetooth""
+						register "type" = "UPC_TYPE_INTERNAL"
+						device ref usb2_port10 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB3 Type-A Left""
+						register "type" = "UPC_TYPE_USB3_A"
+						register "use_custom_pld" = "true"
+						register "custom_pld" = "ACPI_PLD_TYPE_A(LEFT, CENTER, ACPI_PLD_GROUP(2, 1))"
+						device ref usb3_port1 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB3 Type-A Right""
+						register "type" = "UPC_TYPE_USB3_A"
+						register "use_custom_pld" = "true"
+						register "custom_pld" = "ACPI_PLD_TYPE_A(RIGHT, RIGHT, ACPI_PLD_GROUP(1, 3))"
+						device ref usb3_port2 on end
+					end
+				end
+			end
+		end
+		device ref pmc_shared_sram on end
+		device ref cnvi_wifi on
+			register "cnvi_wifi_core" = "true"
+			register "cnvi_bt_core" = "true"
+			register "cnvi_bt_audio_offload" = "true"
+			chip drivers/wifi/generic
+				register "wake" = "GPE0_PME_B0"
+				register "add_acpi_dma_property" = "true"
+				register "enable_cnvi_ddr_rfim" = "true"
+				device generic 0 on end
+			end
+		end
+		device ref i2c0 on # Touchpad
+			register "serial_io_i2c_mode[PchSerialIoIndexI2C0]" = "PchSerialIoPci"
+			chip drivers/i2c/hid
+				register "generic.hid" = ""ELAN0412""
+				register "generic.desc" = ""ELAN Touchpad""
+				register "generic.irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPP_B00)"
+				register "generic.detect" = "1"
+				register "hid_desc_reg_offset" = "0x01"
+				device i2c 15 on end
+			end
+			chip drivers/i2c/hid
+				register "generic.hid" = ""FTCS1000""
+				register "generic.desc" = ""FocalTech Touchpad""
+				register "generic.irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPP_B00)"
+				register "generic.detect" = "1"
+				register "hid_desc_reg_offset" = "0x01"
+				device i2c 38 on end
+			end
+		end
+		device ref i2c1 on # USB-PD EEPROM
+			register "serial_io_i2c_mode[PchSerialIoIndexI2C1]" = "PchSerialIoPci"
+		end
+		device ref i2c3 on # Pantone ROM
+			register "serial_io_i2c_mode[PchSerialIoIndexI2C3]" = "PchSerialIoPci"
+		end
+		device ref pcie_rp5 on # GLAN
+			register "pcie_rp[PCH_RP(5)]" = "{
+				.clk_src = 2,
+				.clk_req = 2,
+				.flags = PCIE_RP_LTR | PCIE_RP_CLK_SRC_UNUSED,
+			}"
+			register "pcie_clk_config_flag[2]" = "PCIE_CLK_LAN"
+		end
+		device ref pcie_rp6 on # SD Card Reader
+			register "pcie_rp[PCH_RP(6)]" = "{
+				.clk_src = 3,
+				.clk_req = 3,
+				.flags = PCIE_RP_LTR | PCIE_RP_AER,
+			}"
+			chip drivers/generic/bayhub_lv2
+				register "enable_power_saving" = "1"
+				device pci 00.0 on end
+			end
+		end
+		device ref pcie_rp8 on # M.2 2230
+			register "pcie_rp[PCH_RP(8)]" = "{
+				.clk_src = 5,
+				.clk_req = 5,
+				.flags = PCIE_RP_LTR | PCIE_RP_AER,
+			}"
+			chip drivers/wifi/generic
+				register "wake" = "GPE0_DW2_09"
+				register "add_acpi_dma_property" = "true"
+				device pci 00.0 on end
+			end
+			smbios_slot_desc "SlotTypeM2Socket1_SD" "SlotLengthOther" "M.2/E 2230 (J_WLAN1)" "SlotDataBusWidth1X"
+		end
+		device ref uart0 on # BIOS Debug Port
+			register "serial_io_uart_mode[PchSerialIoIndexUART0]" = "PchSerialIoPci"
+		end
+		device ref soc_espi on
+			register "gen1_dec" = "0x00040069" # EC PM channel
+			register "gen2_dec" = "0x00fc0e01" # AP/EC command
+			register "gen3_dec" = "0x00fc0f01" # AP/EC debug
+			chip drivers/pc80/tpm # SLB 9672 TPM 2.0
+				device pnp 0c31.0 on end
+			end
+		end
+		device ref pmc hidden
+			register "pmc_gpe0_dw0" = "PMC_GPP_V"
+			register "pmc_gpe0_dw1" = "PMC_GPP_B"
+			register "pmc_gpe0_dw2" = "PMC_GPP_S"
+			chip drivers/intel/pmc_mux
+				device generic 0 on
+					chip drivers/intel/pmc_mux/conn
+						# USB Type-C Port 1 (TBT)
+						use usb2_port6 as usb2_port
+						use tcss_usb3_port0 as usb3_port
+						device generic 0 alias conn0 on end
+					end
+					chip drivers/intel/pmc_mux/conn
+						# USB Type-C Port 2 (Non-TBT)
+						use usb2_port2 as usb2_port
+						use tcss_usb3_port1 as usb3_port
+						device generic 1 alias conn1 on end
+					end
+				end
+			end
+		end
+		device ref hda on
+			subsystemid 0x1558 0xa763
+			#register "pch_hda_audio_link_hda_enable" = "1"
+			register "pch_hda_sdi_enable[0]" = "1"
+			register "pch_hda_dsp_enable" = "1"
+			register "pch_hda_idisp_codec_enable" = "1"
+			register "pch_hda_idisp_link_frequency" = "HDA_LINKFREQ_96MHZ"
+			register "pch_hda_idisp_link_tmode" = "HDA_TMODE_8T"
+
+		end
+		device ref smbus on end
+		device ref fast_spi on end
+		device ref gbe on end
+	end
+end
diff --git a/src/mainboard/novacustom/mtl-h/dsdt.asl b/src/mainboard/novacustom/mtl-h/dsdt.asl
new file mode 100644
index 0000000000..06e7263d07
--- /dev/null
+++ b/src/mainboard/novacustom/mtl-h/dsdt.asl
@@ -0,0 +1,34 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <acpi/acpi.h>
+DefinitionBlock(
+	"dsdt.aml",
+	"DSDT",
+	ACPI_DSDT_REV_2,
+	OEM_ID,
+	ACPI_TABLE_CREATOR,
+	0x20110725
+)
+{
+	#include <acpi/dsdt_top.asl>
+	#include <soc/intel/common/block/acpi/acpi/platform.asl>
+	#include <soc/intel/common/block/acpi/acpi/globalnvs.asl>
+	#include <cpu/intel/common/acpi/cpu.asl>
+
+	Device (\_SB.PCI0)
+	{
+		#include <soc/intel/common/block/acpi/acpi/northbridge.asl>
+		#include <soc/intel/meteorlake/acpi/southbridge.asl>
+		#include <soc/intel/meteorlake/acpi/tcss.asl>
+	}
+
+	/* Chipset specific sleep states */
+	#include <southbridge/intel/common/acpi/sleepstates.asl>
+
+	Scope (\_SB.PCI0.LPCB)
+	{
+		#include <drivers/pc80/pc/ps2_controller.asl>
+	}
+
+	#include "acpi/mainboard.asl"
+}
diff --git a/src/mainboard/novacustom/mtl-h/fadt.c b/src/mainboard/novacustom/mtl-h/fadt.c
new file mode 100644
index 0000000000..f983717e09
--- /dev/null
+++ b/src/mainboard/novacustom/mtl-h/fadt.c
@@ -0,0 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <acpi/acpi.h>
+
+void mainboard_fill_fadt(acpi_fadt_t *fadt)
+{
+	fadt->preferred_pm_profile = PM_MOBILE;
+}
diff --git a/src/mainboard/novacustom/mtl-h/gpio.c b/src/mainboard/novacustom/mtl-h/gpio.c
new file mode 100644
index 0000000000..f52b044a9e
--- /dev/null
+++ b/src/mainboard/novacustom/mtl-h/gpio.c
@@ -0,0 +1,574 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <mainboard/gpio.h>
+#include <soc/gpio.h>
+
+/* Pad configuration was generated automatically using intelp2m utility */
+static const struct pad_config gpio_table[] = {
+
+	/* ------- GPIO Community 0 ------- */
+
+	/* ------- GPIO Group V ------- */
+
+	/* GPP_V00 - BATLOW# */
+	PAD_CFG_NF(GPP_V00, UP_20K, DEEP, NF1),
+	/* GPP_V01 - ACPRESENT */
+	PAD_CFG_NF(GPP_V01, NATIVE, DEEP, NF1),
+	/* GPP_V02 - SOC_WAKE# */
+	PAD_CFG_NF(GPP_V02, NATIVE, DEEP, NF1),
+	/* GPP_V03 - PWRBTN# */
+	PAD_CFG_NF(GPP_V03, UP_20K, DEEP, NF1),
+	/* GPP_V04 - SLP_S3# */
+	PAD_CFG_NF(GPP_V04, NONE, DEEP, NF1),
+	/* GPP_V05 - SLP_S4# */
+	PAD_CFG_NF(GPP_V05, NONE, DEEP, NF1),
+	/* GPP_V06 - SLP_A# */
+	PAD_CFG_NF(GPP_V06, NONE, DEEP, NF1),
+	/* GPP_V07 - GPIO */
+	PAD_CFG_GPO(GPP_V07, 0, DEEP),
+	/* GPP_V08 - SUSCLK */
+	PAD_CFG_NF(GPP_V08, NONE, DEEP, NF1),
+	/* GPP_V09 - SLP_WLAN# */
+	PAD_CFG_NF(GPP_V09, NONE, DEEP, NF1),
+	/* GPP_V10 - SLP_S5# */
+	PAD_CFG_NF(GPP_V10, NONE, DEEP, NF1),
+	/* GPP_V11 - LANPHYPC */
+	PAD_CFG_NF(GPP_V11, NONE, DEEP, NF1),
+	/* GPP_V12 - SLP_LAN# */
+	PAD_CFG_NF(GPP_V12, NONE, DEEP, NF1),
+	/* GPP_V13 - GPIO */
+	PAD_CFG_GPO(GPP_V13, 0, DEEP),
+	/* GPP_V14 - WAKE# */
+	PAD_CFG_NF(GPP_V14, NONE, DEEP, NF1),
+	/* GPP_V15 - GPIO */
+	PAD_CFG_GPO(GPP_V15, 0, DEEP),
+	/* GPP_V16 - GPIO */
+	PAD_CFG_GPO(GPP_V16, 0, DEEP),
+	/* GPP_V17 - GPIO */
+	PAD_CFG_GPO(GPP_V17, 0, DEEP),
+	/* GPP_V18 - GPIO */
+	PAD_CFG_GPO(GPP_V18, 0, DEEP),
+	/* GPP_V19 - n/a */
+	PAD_CFG_NF(GPP_V19, NONE, DEEP, NF1),
+	/* GPP_V20 - n/a */
+	PAD_CFG_NF(GPP_V20, NONE, DEEP, NF1),
+	/* GPP_V21 - n/a */
+	PAD_CFG_NF(GPP_V21, NONE, DEEP, NF1),
+	/* GPP_V22 - GPIO */
+	PAD_CFG_GPO(GPP_V22, 0, DEEP),
+	/* GPP_V23 - GPIO */
+	PAD_CFG_GPO(GPP_V23, 0, DEEP),
+
+	/* ------- GPIO Group GPP_C ------- */
+
+	/* GPP_C00 - SMBCLK */
+	PAD_CFG_NF(GPP_C00, UP_20K, DEEP, NF1),
+	/* GPP_C01 - SMBDATA */
+	PAD_CFG_NF(GPP_C01, UP_20K, DEEP, NF1),
+	/* GPP_C02 - GPIO */
+	PAD_CFG_GPO(GPP_C02, 0, DEEP),
+	/* GPP_C03 - SML0CLK */
+	PAD_CFG_NF(GPP_C03, NONE, DEEP, NF1),
+	/* GPP_C04 - SML0DATA */
+	PAD_CFG_NF(GPP_C04, NONE, DEEP, NF1),
+	/* GPP_C05 - GPIO */
+	PAD_CFG_GPO(GPP_C05, 0, DEEP),
+	/* GPP_C06 - SML1CLK */
+	PAD_CFG_NF(GPP_C06, NONE, RSMRST, NF1),
+	/* GPP_C07 - SML1DATA */
+	PAD_CFG_NF(GPP_C07, NONE, RSMRST, NF1),
+	/* GPP_C08 - GPIO */
+	PAD_CFG_GPO(GPP_C08, 0, DEEP),
+	/* GPP_C09 - GPIO */
+	PAD_CFG_GPO(GPP_C09, 0, DEEP),
+	/* GPP_C10 - GPIO */
+	PAD_CFG_GPO(GPP_C10, 0, DEEP),
+	/* GPP_C11 - SRCCLKREQ2# */
+	PAD_CFG_NF(GPP_C11, NONE, DEEP, NF1),
+	/* GPP_C12 - SRCCLKREQ3# */
+	PAD_CFG_NF(GPP_C12, NONE, DEEP, NF1),
+	/* GPP_C13 - GPIO */
+	PAD_CFG_GPO(GPP_C13, 0, DEEP),
+	/* GPP_C14 - GPIO */
+	PAD_CFG_GPO(GPP_C14, 0, DEEP),
+	/* GPP_C15 - GPIO */
+	PAD_CFG_GPO(GPP_C15, 0, DEEP),
+	/* GPP_C16 - TBT_LSX0_TXD */
+	PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1),
+	/* GPP_C17 - TBT_LSX0_RXD */
+	PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1),
+	/* GPP_C18 - GPIO */
+	PAD_CFG_GPO(GPP_C18, 0, DEEP),
+	/* GPP_C19 - GPIO */
+	PAD_CFG_GPO(GPP_C19, 0, DEEP),
+	/* GPP_C20 - DDP2_CTRLCLK */
+	PAD_CFG_NF(GPP_C20, NONE, DEEP, NF2),
+	/* GPP_C21 - DDP2_CTRLDATA */
+	PAD_CFG_NF(GPP_C21, NONE, DEEP, NF2),
+	/* GPP_C22 - GPIO */
+	PAD_CFG_GPO(GPP_C22, 0, DEEP),
+	/* GPP_C23 - GPIO */
+	PAD_CFG_GPO(GPP_C23, 0, DEEP),
+
+	/* ------- GPIO Community 1 ------- */
+
+	/* ------- GPIO Group GPP_A ------- */
+
+	/* GPP_A00 - ESPI_IO0 */
+	PAD_CFG_NF(GPP_A00, UP_20K, DEEP, NF1),
+	/* GPP_A01 - ESPI_IO1 */
+	PAD_CFG_NF(GPP_A01, UP_20K, DEEP, NF1),
+	/* GPP_A02 - ESPI_IO2 */
+	PAD_CFG_NF(GPP_A02, UP_20K, DEEP, NF1),
+	/* GPP_A03 - ESPI_IO3 */
+	PAD_CFG_NF(GPP_A03, UP_20K, DEEP, NF1),
+	/* GPP_A04 - ESPI_CS0# */
+	PAD_CFG_NF(GPP_A04, UP_20K, DEEP, NF1),
+	/* GPP_A05 - ESPI_CLK */
+	PAD_CFG_NF(GPP_A05, UP_20K, DEEP, NF1),
+	/* GPP_A06 - ESPI_RESET# */
+	PAD_CFG_NF(GPP_A06, NONE, DEEP, NF1),
+	/* GPP_A07 - GPIO */
+	PAD_CFG_GPO(GPP_A07, 0, DEEP),
+	/* GPP_A08 - GPIO */
+	PAD_CFG_GPO(GPP_A08, 0, DEEP),
+	/* GPP_A09 - GPIO */
+	PAD_CFG_GPO(GPP_A09, 0, DEEP),
+	/* GPP_A10 - GPIO */
+	PAD_CFG_GPO(GPP_A10, 0, DEEP),
+	/* GPP_A11 - GPIO */
+	PAD_CFG_GPO(GPP_A11, 0, DEEP),
+	/* GPP_A12 - GPIO */
+	PAD_CFG_GPI_TRIG_OWN(GPP_A12, NONE, DEEP, OFF, ACPI),
+	/* GPP_A13 - GPIO */
+	PAD_CFG_TERM_GPO(GPP_A13, 1, UP_20K, PLTRST),
+	/* GPP_A14 - GPIO */
+	PAD_CFG_GPO(GPP_A14, 0, DEEP),
+	/* GPP_A15 - GPIO */
+	PAD_CFG_GPO(GPP_A15, 0, DEEP),
+	/* GPP_A16 - RSVD */
+	PAD_CFG_NF(GPP_A16, UP_20K, DEEP, NF1),
+	/* GPP_A17 - GPIO */
+	PAD_CFG_GPO(GPP_A17, 0, DEEP),
+	/* GPP_A18 - GPIO */
+	PAD_CFG_GPO(GPP_A18, 0, DEEP),
+	/* GPP_A19 - GPIO */
+	PAD_CFG_GPO(GPP_A19, 0, DEEP),
+	/* GPP_A20 - GPIO */
+	PAD_CFG_GPO(GPP_A20, 0, DEEP),
+	/* GPP_A21 - PMCALERT# */
+	PAD_CFG_NF(GPP_A21, NATIVE, DEEP, NF1),
+	/* GPP_A22 - GPIO */
+	PAD_NC(GPP_A22, NATIVE),
+	/* GPP_A23 - GPIO */
+	PAD_NC(GPP_A23, NATIVE),
+	/* GPP_ESPI_CLK_LPBK - n/a */
+	PAD_CFG_NF(GPP_ESPI_CLK_LPBK, NONE, DEEP, NF1),
+
+	/* ------- GPIO Group GPP_E ------- */
+
+	/* GPP_E00 - GPIO */
+	PAD_CFG_GPO(GPP_E00, 0, DEEP),
+	/* GPP_E01 - GPIO */
+	PAD_CFG_GPI_APIC(GPP_E01, UP_20K, DEEP, LEVEL, NONE),
+	/* GPP_E02 - GPIO */
+	PAD_CFG_GPI_TRIG_OWN(GPP_E02, NONE, DEEP, OFF, ACPI),
+	/* GPP_E03 - GPIO */
+	PAD_CFG_GPI_TRIG_OWN(GPP_E03, NONE, DEEP, OFF, ACPI),
+	/* GPP_E04 - GPIO */
+	PAD_CFG_GPO(GPP_E04, 0, DEEP),
+	/* GPP_E05 - GPIO */
+	PAD_CFG_GPO(GPP_E05, 0, DEEP),
+	/* GPP_E06 - GPIO */
+	PAD_CFG_GPO(GPP_E06, 0, DEEP),
+	/* GPP_E07 - GPIO */
+	PAD_CFG_GPO(GPP_E07, 0, DEEP),
+	/* GPP_E08 - GPIO */
+	PAD_CFG_GPO(GPP_E08, 0, DEEP),
+	/* GPP_E09 - GPIO */
+	PAD_CFG_GPI_TRIG_OWN(GPP_E09, NONE, DEEP, OFF, ACPI),
+	/* GPP_E10 - GPIO */
+	PAD_CFG_GPO(GPP_E10, 0, DEEP),
+	/* GPP_E11 - GPIO */
+	PAD_CFG_GPI_TRIG_OWN(GPP_E11, NONE, DEEP, OFF, ACPI),
+	/* GPP_E12 - GPIO */
+	PAD_CFG_GPO(GPP_E12, 0, DEEP),
+	/* GPP_E13 - GPIO */
+	PAD_CFG_GPO(GPP_E13, 0, DEEP),
+	/* GPP_E14 - DDSP_HPDA */
+	PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1),
+	/* GPP_E15 - GPIO */
+	PAD_CFG_GPO(GPP_E15, 0, DEEP),
+	/* GPP_E16 - VRALERT# */
+	PAD_CFG_NF(GPP_E16, NONE, DEEP, NF2),
+	/* GPP_E17 - GPIO */
+	PAD_CFG_GPO(GPP_E17, 0, DEEP),
+	/* GPP_E18 - GPIO */
+	PAD_CFG_GPO(GPP_E18, 0, DEEP),
+	/* GPP_E19 - GPIO */
+	PAD_CFG_GPO(GPP_E19, 0, DEEP),
+	/* GPP_E20 - GPIO */
+	PAD_CFG_GPO(GPP_E20, 0, DEEP),
+	/* GPP_E21 - GPIO */
+	PAD_CFG_GPO(GPP_E21, 0, DEEP),
+	/* GPP_E22 - GPIO */
+	PAD_CFG_GPO(GPP_E22, 0, DEEP),
+	/* GPP_E23 - GPIO */
+	PAD_NC(GPP_E23, NONE),
+	/* GPP_THC0_GSPI_CLK_LPBK - GPIO */
+	PAD_NC(GPP_THC0_GSPI_CLK_LPBK, NONE),
+
+	/* ------- GPIO Community 3 ------- */
+
+	/* ------- GPIO Group GPP_H ------- */
+
+	/* GPP_H00 - GPIO */
+	PAD_CFG_GPO(GPP_H00, 0, DEEP),
+	/* GPP_H01 - GPIO */
+	PAD_CFG_GPO(GPP_H01, 0, DEEP),
+	/* GPP_H02 - GPIO */
+	PAD_CFG_GPO(GPP_H02, 0, DEEP),
+	/* GPP_H03 - GPIO */
+	PAD_CFG_GPO(GPP_H03, 0, DEEP),
+	/* GPP_H04 - GPIO */
+	PAD_CFG_GPO(GPP_H04, 0, DEEP),
+	/* GPP_H05 - GPIO */
+	PAD_CFG_GPO(GPP_H05, 0, DEEP),
+	/* GPP_H06 - I2C3_SDA */
+	PAD_CFG_NF(GPP_H06, NONE, DEEP, NF1),
+	/* GPP_H07 - I2C3_SCL */
+	PAD_CFG_NF(GPP_H07, NONE, DEEP, NF1),
+	/* GPP_H08 - GPIO */
+	PAD_CFG_GPO(GPP_H08, 0, DEEP),
+	/* GPP_H09 - GPIO */
+	PAD_CFG_GPO(GPP_H09, 0, DEEP),
+	/* GPP_H10 - GPIO */
+	PAD_CFG_GPO(GPP_H10, 0, DEEP),
+	/* GPP_H11 - GPIO */
+	PAD_CFG_GPO(GPP_H11, 0, DEEP),
+	/* GPP_H12 - GPIO */
+	PAD_CFG_GPO(GPP_H12, 0, DEEP),
+	/* GPP_H13 - PROC_C10_GATE# */
+	PAD_CFG_NF(GPP_H13, NONE, DEEP, NF1),
+	/* GPP_H14 - GPIO */
+	PAD_CFG_GPO(GPP_H14, 0, DEEP),
+	/* GPP_H15 - GPIO */
+	PAD_CFG_GPO(GPP_H15, 0, DEEP),
+	/* GPP_H16 - GPIO */
+	PAD_CFG_GPO(GPP_H16, 0, DEEP),
+	/* GPP_H17 - GPIO */
+	PAD_CFG_GPO(GPP_H17, 0, DEEP),
+	/* GPP_H18 - GPIO */
+	PAD_CFG_GPO(GPP_H18, 0, DEEP),
+	/* GPP_H19 - I2C0_SDA */
+	PAD_CFG_NF(GPP_H19, NONE, DEEP, NF1),
+	/* GPP_H20 - I2C0_SCL */
+	PAD_CFG_NF(GPP_H20, NONE, DEEP, NF1),
+	/* GPP_H21 - I2C1_SDA */
+	PAD_CFG_NF(GPP_H21, NONE, DEEP, NF1),
+	/* GPP_H22 - I2C1_SCL */
+	PAD_CFG_NF(GPP_H22, NONE, DEEP, NF1),
+	/* GPP_H23 - GPIO */
+	PAD_NC(GPP_H23, NONE),
+	/* GPP_LPI3C1_CLK_LPBK - GPIO */
+	PAD_NC(GPP_LPI3C1_CLK_LPBK, NATIVE),
+	/* GPP_LPI3C0_CLK_LPBK - n/a */
+	PAD_CFG_NF(GPP_LPI3C0_CLK_LPBK, NATIVE, DEEP, NF2),
+
+	/* ------- GPIO Group GPP_F ------- */
+
+	/* GPP_F00 - CNV_BRI_DT */
+	PAD_CFG_NF(GPP_F00, NONE, DEEP, NF1),
+	/* GPP_F01 - CNV_BRI_RSP */
+	PAD_CFG_NF(GPP_F01, UP_20K, DEEP, NF1),
+	/* GPP_F02 - CNV_RGI_DT */
+	PAD_CFG_NF(GPP_F02, NONE, DEEP, NF1),
+	/* GPP_F03 - CNV_RGI_RSP */
+	PAD_CFG_NF(GPP_F03, UP_20K, DEEP, NF1),
+	/* GPP_F04 - CNV_RF_RESET# */
+	PAD_CFG_NF(GPP_F04, NONE, DEEP, NF1),
+	/* GPP_F05 - MODEM_CLKREQ */
+	PAD_CFG_NF(GPP_F05, NONE, DEEP, NF3),
+	/* GPP_F06 - GPIO */
+	PAD_CFG_GPO(GPP_F06, 0, DEEP),
+	/* GPP_F07 - GPIO */
+	PAD_CFG_GPO(GPP_F07, 0, DEEP),
+	/* GPP_F08 - GPIO */
+	PAD_CFG_GPO(GPP_F08, 0, DEEP),
+	/* GPP_F09 - GPIO */
+	PAD_CFG_GPI_TRIG_OWN(GPP_F09, NONE, DEEP, OFF, ACPI),
+	/* GPP_F10 - GPIO */
+	PAD_CFG_GPO(GPP_F10, 0, DEEP),
+	/* GPP_F11 - GPIO */
+	PAD_CFG_GPO(GPP_F11, 0, DEEP),
+	/* GPP_F12 - GPIO */
+	PAD_CFG_GPI_TRIG_OWN(GPP_F12, NONE, DEEP, OFF, ACPI),
+	/* GPP_F13 - GPIO */
+	PAD_CFG_GPI_TRIG_OWN(GPP_F13, NONE, DEEP, OFF, ACPI),
+	/* GPP_F14 - GPIO */
+	PAD_CFG_GPO(GPP_F14, 0, DEEP),
+	/* GPP_F15 - GPIO */
+	PAD_CFG_GPO(GPP_F15, 0, DEEP),
+	/* GPP_F16 - GPIO */
+	PAD_CFG_GPO(GPP_F16, 0, DEEP),
+	/* GPP_F17 - GPIO */
+	PAD_CFG_GPO(GPP_F17, 0, DEEP),
+	/* GPP_F18 - GPIO */
+	PAD_CFG_GPO(GPP_F18, 0, DEEP),
+	/* GPP_F19 - GPIO */
+	PAD_CFG_GPO(GPP_F19, 0, DEEP),
+	/* GPP_F20 - GPIO */
+	PAD_CFG_GPO(GPP_F20, 0, DEEP),
+	/* GPP_F21 - GPIO */
+	PAD_CFG_GPO(GPP_F21, 0, DEEP),
+	/* GPP_F22 - GPIO */
+	PAD_CFG_GPO(GPP_F22, 0, DEEP),
+	/* GPP_F23 - GPIO */
+	PAD_CFG_GPO(GPP_F23, 0, DEEP),
+	/* GPP_THC1_GSPI1_CLK_LPBK - GPIO */
+	PAD_NC(GPP_THC1_GSPI1_CLK_LPBK, NONE),
+	/* GPP_GSPI0A_CLK_LOOPBK - GPIO */
+	PAD_NC(GPP_GSPI0A_CLK_LOOPBK, NONE),
+
+	/* ------- GPIO Group SPI ------- */
+
+	/* ------- GPIO Group VGPIO3 ------- */
+
+	/* GPP_VGPIO3_USB0 - GPP_VGPIO3_USB0 */
+	PAD_CFG_NF(GPP_VGPIO3_USB0, NONE, DEEP, NF1),
+	/* GPP_VGPIO3_USB1 - GPP_VGPIO3_USB1 */
+	PAD_CFG_NF(GPP_VGPIO3_USB1, NONE, DEEP, NF1),
+	/* GPP_VGPIO3_USB2 - GPP_VGPIO3_USB2 */
+	PAD_CFG_NF(GPP_VGPIO3_USB2, NONE, DEEP, NF1),
+	/* GPP_VGPIO3_USB3 - GPP_VGPIO3_USB3 */
+	PAD_CFG_NF(GPP_VGPIO3_USB3, NONE, DEEP, NF1),
+	/* GPP_VGPIO3_USB4 - GPP_VGPIO3_USB4 */
+	PAD_CFG_NF(GPP_VGPIO3_USB4, NONE, DEEP, NF1),
+	/* GPP_VGPIO3_USB5 - GPP_VGPIO3_USB5 */
+	PAD_CFG_NF(GPP_VGPIO3_USB5, NONE, DEEP, NF1),
+	/* GPP_VGPIO3_USB6 - GPP_VGPIO3_USB6 */
+	PAD_CFG_NF(GPP_VGPIO3_USB6, NONE, DEEP, NF1),
+	/* GPP_VGPIO3_USB7 - GPP_VGPIO3_USB7 */
+	PAD_CFG_NF(GPP_VGPIO3_USB7, NONE, DEEP, NF1),
+	/* GPP_VGPIO3_TS0 - GPIO */
+	PAD_CFG_GPI_TRIG_OWN(GPP_VGPIO3_TS0, NONE, DEEP, OFF, ACPI),
+	/* GPP_VGPIO3_TS1 - GPIO */
+	PAD_CFG_GPI_TRIG_OWN(GPP_VGPIO3_TS1, NONE, DEEP, OFF, ACPI),
+	/* GPP_VGPIO3_THC0 - GPIO */
+	PAD_CFG_GPI_TRIG_OWN(GPP_VGPIO3_THC0, NONE, DEEP, OFF, ACPI),
+	/* GPP_VGPIO3_THC1 - GPIO */
+	PAD_CFG_GPI_TRIG_OWN(GPP_VGPIO3_THC1, NONE, DEEP, OFF, ACPI),
+	/* GPP_VGPIO3_THC2 - GPIO */
+	PAD_CFG_GPI_TRIG_OWN(GPP_VGPIO3_THC2, NONE, DEEP, OFF, ACPI),
+	/* GPP_VGPIO3_THC3 - GPIO */
+	PAD_CFG_GPI_TRIG_OWN(GPP_VGPIO3_THC3, NONE, DEEP, OFF, ACPI),
+
+	/* ------- GPIO Community 4 ------- */
+
+	/* ------- GPIO Group GPP_S ------- */
+
+	/* GPP_S00 - GPIO */
+	PAD_CFG_GPO(GPP_S00, 0, DEEP),
+	/* GPP_S01 - GPIO */
+	PAD_CFG_GPO(GPP_S01, 0, DEEP),
+	/* GPP_S02 - GPIO */
+	PAD_CFG_GPO(GPP_S02, 0, DEEP),
+	/* GPP_S03 - GPIO */
+	PAD_CFG_GPO(GPP_S03, 0, DEEP),
+	/* GPP_S04 - GPIO */
+	PAD_CFG_GPO(GPP_S04, 0, DEEP),
+	/* GPP_S05 - GPIO */
+	PAD_CFG_GPO(GPP_S05, 0, DEEP),
+	/* GPP_S06 - GPIO */
+	PAD_CFG_GPO(GPP_S06, 0, DEEP),
+	/* GPP_S07 - GPIO */
+	PAD_CFG_GPO(GPP_S07, 0, DEEP),
+
+	/* ------- GPIO Group JTAG ------- */
+
+	/* ------- GPIO Community 5 ------- */
+
+	/* ------- GPIO Group GPP_B ------- */
+
+	/* GPP_B00 - GPIO */
+	PAD_CFG_GPI_INT(GPP_B00, NONE, PLTRST, LEVEL),
+	/* GPP_B01 - GPIO */
+	PAD_CFG_GPO(GPP_B01, 0, DEEP),
+	/* GPP_B02 - GPIO */
+	PAD_CFG_GPO(GPP_B02, 0, DEEP),
+	/* GPP_B03 - GPIO */
+	PAD_CFG_GPO(GPP_B03, 0, DEEP),
+	/* GPP_B04 - GPIO */
+	PAD_CFG_GPO(GPP_B04, 0, DEEP),
+	/* GPP_B05 - GPIO */
+	PAD_CFG_GPO(GPP_B05, 0, DEEP),
+	/* GPP_B06 - GPIO */
+	PAD_CFG_GPO(GPP_B06, 0, DEEP),
+	/* GPP_B07 - GPIO */
+	PAD_CFG_GPO(GPP_B07, 0, DEEP),
+	/* GPP_B08 - GPIO */
+	PAD_CFG_GPO(GPP_B08, 0, DEEP),
+	/* GPP_B09 - GPIO */
+	PAD_CFG_GPO(GPP_B09, 0, DEEP),
+	/* GPP_B10 - GPIO */
+	PAD_CFG_GPO(GPP_B10, 0, DEEP),
+	/* GPP_B11 - DDSP_HPD2 */
+	PAD_CFG_NF(GPP_B11, NONE, DEEP, NF2),
+	/* GPP_B12 - SLP_S0# */
+	PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1),
+	/* GPP_B13 - PLTRST# */
+	PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1),
+	/* GPP_B14 - GPIO */
+	PAD_CFG_GPI_TRIG_OWN(GPP_B14, NONE, DEEP, OFF, ACPI),
+	/* GPP_B15 - GPIO */
+	PAD_CFG_GPI_TRIG_OWN(GPP_B15, NONE, DEEP, OFF, ACPI),
+	/* GPP_B16 - GPIO */
+	PAD_CFG_GPO(GPP_B16, 0, DEEP),
+	/* GPP_B17 - GPIO */
+	PAD_CFG_GPO(GPP_B17, 0, DEEP),
+	/* GPP_B18 - GPIO */
+	PAD_CFG_GPO(GPP_B18, 1, DEEP),
+	/* GPP_B19 - GPIO */
+	PAD_CFG_GPO(GPP_B19, 1, DEEP),
+	/* GPP_B20 - GPIO */
+	PAD_CFG_GPO(GPP_B20, 0, DEEP),
+	/* GPP_B21 - GPIO */
+	PAD_CFG_GPO(GPP_B21, 0, PLTRST),
+	/* GPP_B22 - GPIO */
+	PAD_CFG_GPO(GPP_B22, 0, DEEP),
+	/* GPP_B23 - GPIO */
+	PAD_CFG_GPO(GPP_B23, 0, DEEP),
+	/* GPP_ACI3C0_CLK_LPBK - n/a */
+	PAD_CFG_NF(GPP_ACI3C0_CLK_LPBK, NATIVE, DEEP, NF4),
+
+	/* ------- GPIO Group GPP_D ------- */
+
+	/* GPP_D00 - GPIO */
+	PAD_CFG_GPO(GPP_D00, 1, DEEP),
+	/* GPP_D01 - GPIO */
+	PAD_CFG_GPO(GPP_D01, 1, DEEP),
+	/* GPP_D02 - GPIO */
+	PAD_CFG_GPO(GPP_D02, 1, DEEP),
+	/* GPP_D03 - GPIO */
+	PAD_CFG_GPO(GPP_D03, 0, DEEP),
+	/* GPP_D04 - GPIO */
+	PAD_CFG_GPO(GPP_D04, 0, DEEP),
+	/* GPP_D05 - GPIO */
+	PAD_CFG_GPO(GPP_D05, 1, DEEP),
+	/* GPP_D06 - GPIO */
+	PAD_CFG_GPO(GPP_D06, 0, DEEP),
+	/* GPP_D07 - GPIO */
+	PAD_CFG_GPO(GPP_D07, 0, DEEP),
+	/* GPP_D08 - GPIO */
+	PAD_CFG_GPO(GPP_D08, 0, DEEP),
+	/* GPP_D09 - GPIO */
+	PAD_CFG_GPO(GPP_D09, 0, DEEP),
+	/* GPP_D10 - HDA_BCLK */
+	PAD_CFG_NF(GPP_D10, NONE, DEEP, NF1),
+	/* GPP_D11 - HDA_SYNC */
+	PAD_CFG_NF(GPP_D11, NATIVE, DEEP, NF1),
+	/* GPP_D12 - HDA_SDO */
+	PAD_CFG_NF(GPP_D12, NATIVE, DEEP, NF1),
+	/* GPP_D13 - HDA_SDI0 */
+	PAD_CFG_NF(GPP_D13, NATIVE, DEEP, NF1),
+	/* GPP_D14 - GPIO */
+	PAD_CFG_GPO(GPP_D14, 0, DEEP),
+	/* GPP_D15 - GPIO */
+	PAD_CFG_GPO(GPP_D15, 0, DEEP),
+	/* GPP_D16 - GPIO */
+	PAD_CFG_GPO(GPP_D16, 0, DEEP),
+	/* GPP_D17 - HDA_RST# */
+	PAD_CFG_NF(GPP_D17, NONE, DEEP, NF1),
+	/* GPP_D18 - SRCCLKREQ6# */
+	PAD_CFG_NF(GPP_D18, NONE, DEEP, NF1),
+	/* GPP_D19 - SRCCLKREQ7# */
+	PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1),
+	/* GPP_D20 - SRCCLKREQ8# */
+	PAD_CFG_NF(GPP_D20, NONE, DEEP, NF1),
+	/* GPP_D21 - SRCCLKREQ5# */
+	PAD_CFG_NF(GPP_D21, NONE, DEEP, NF2),
+	/* GPP_D22 - n/a */
+	PAD_CFG_NF(GPP_D22, NATIVE, DEEP, NF1),
+	/* GPP_D23 - n/a */
+	PAD_CFG_NF(GPP_D23, NATIVE, DEEP, NF1),
+	/* GPP_BOOTHALT_B - n/a */
+	PAD_CFG_NF(GPP_BOOTHALT_B, UP_20K, DEEP, NF1),
+
+	/* ------- GPIO Group VGPIO ------- */
+
+	/* VGPIO00 - GPIO */
+	PAD_CFG_GPO(GPP_VGPIO00, 1, DEEP),
+	/* VGPIO04 - GPIO */
+	PAD_CFG_GPI_TRIG_OWN(GPP_VGPIO04, NONE, DEEP, OFF, ACPI),
+	/* VGPIO05 - GPIO */
+	PAD_CFG_GPO(GPP_VGPIO05, 1, DEEP),
+	/* VGPIO06 - GPIO */
+	PAD_CFG_GPIO_BIDIRECT(GPP_VGPIO06, 0, NONE, DEEP, LEVEL, ACPI),
+	/* VGPIO07 - GPIO */
+	PAD_CFG_GPIO_BIDIRECT(GPP_VGPIO07, 0, NONE, DEEP, LEVEL, ACPI),
+	/* VGPIO08 - GPIO */
+	PAD_CFG_GPIO_BIDIRECT(GPP_VGPIO08, 0, NONE, DEEP, LEVEL, ACPI),
+	/* VGPIO09 - GPIO */
+	PAD_CFG_GPIO_BIDIRECT(GPP_VGPIO09, 0, NONE, DEEP, LEVEL, ACPI),
+	/* VGPIO10 - VGPIO10 */
+	PAD_CFG_NF(GPP_VGPIO10, NONE, DEEP, NF1),
+	/* VGPIO11 - VGPIO11 */
+	PAD_CFG_NF(GPP_VGPIO11, NONE, DEEP, NF1),
+	/* VGPIO12 - VGPIO12 */
+	PAD_CFG_NF(GPP_VGPIO12, NONE, DEEP, NF1),
+	/* VGPIO13 - VGPIO13 */
+	PAD_CFG_NF(GPP_VGPIO13, NONE, DEEP, NF1),
+	/* VGPIO18 - GPIO */
+	PAD_CFG_GPIO_BIDIRECT(GPP_VGPIO18, 0, NONE, DEEP, LEVEL, ACPI),
+	/* VGPIO19 - GPIO */
+	PAD_CFG_GPIO_BIDIRECT(GPP_VGPIO19, 0, NONE, DEEP, LEVEL, ACPI),
+	/* VGPIO20 - GPIO */
+	PAD_CFG_GPIO_BIDIRECT(GPP_VGPIO20, 0, NONE, DEEP, LEVEL, ACPI),
+	/* VGPIO21 - GPIO */
+	PAD_CFG_GPIO_BIDIRECT(GPP_VGPIO21, 0, NONE, DEEP, LEVEL, ACPI),
+	/* VGPIO22 - VGPIO22 */
+	PAD_CFG_NF(GPP_VGPIO22, NONE, DEEP, NF1),
+	/* VGPIO23 - VGPIO23 */
+	PAD_CFG_NF(GPP_VGPIO23, NONE, DEEP, NF1),
+	/* VGPIO24 - VGPIO24 */
+	PAD_CFG_NF(GPP_VGPIO24, NONE, DEEP, NF1),
+	/* VGPIO25 - VGPIO25 */
+	PAD_CFG_NF(GPP_VGPIO25, NONE, DEEP, NF1),
+	/* VGPIO30 - RESERVED */
+	PAD_CFG_NF(GPP_VGPIO30, NONE, DEEP, NF3),
+	/* VGPIO31 - RESERVED */
+	PAD_CFG_NF(GPP_VGPIO31, NONE, DEEP, NF3),
+	/* VGPIO32 - RESERVED */
+	PAD_CFG_NF(GPP_VGPIO32, NONE, DEEP, NF3),
+	/* VGPIO33 - RESERVED */
+	PAD_CFG_NF(GPP_VGPIO33, NONE, DEEP, NF3),
+	/* VGPIO34 - VGPIO34 */
+	PAD_CFG_NF(GPP_VGPIO34, NONE, DEEP, NF1),
+	/* VGPIO35 - VGPIO35 */
+	PAD_CFG_NF(GPP_VGPIO35, NONE, DEEP, NF1),
+	/* VGPIO36 - VGPIO36 */
+	PAD_CFG_NF(GPP_VGPIO36, NONE, DEEP, NF1),
+	/* VGPIO37 - VGPIO37 */
+	PAD_CFG_NF(GPP_VGPIO37, NONE, DEEP, NF1),
+	/* VGPIO40 - RESERVED */
+	PAD_CFG_NF(GPP_VGPIO40, NONE, DEEP, NF2),
+	/* VGPIO41 - RESERVED */
+	PAD_CFG_NF(GPP_VGPIO41, NONE, DEEP, NF2),
+	/* VGPIO42 - RESERVED */
+	PAD_CFG_NF(GPP_VGPIO42, NONE, DEEP, NF2),
+	/* VGPIO43 - RESERVED */
+	PAD_CFG_NF(GPP_VGPIO43, NONE, DEEP, NF2),
+	/* VGPIO44 - VGPIO44 */
+	PAD_CFG_NF(GPP_VGPIO44, NONE, DEEP, NF1),
+	/* VGPIO45 - VGPIO45 */
+	PAD_CFG_NF(GPP_VGPIO45, NONE, DEEP, NF1),
+	/* VGPIO46 - VGPIO46 */
+	PAD_CFG_NF(GPP_VGPIO46, NONE, DEEP, NF1),
+	/* VGPIO47 - VGPIO47 */
+	PAD_CFG_NF(GPP_VGPIO47, NONE, DEEP, NF1),
+};
+
+void mainboard_configure_gpios(void)
+{
+	gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table));
+}
diff --git a/src/mainboard/novacustom/mtl-h/gpio_early.c b/src/mainboard/novacustom/mtl-h/gpio_early.c
new file mode 100644
index 0000000000..c47883e3d6
--- /dev/null
+++ b/src/mainboard/novacustom/mtl-h/gpio_early.c
@@ -0,0 +1,16 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <mainboard/gpio.h>
+#include <soc/gpio.h>
+
+static const struct pad_config early_gpio_table[] = {
+	/* GPP_C00 - SMBCLK */
+	PAD_CFG_NF(GPP_C00, UP_20K, DEEP, NF1),
+	/* GPP_C01 - SMBDATA */
+	PAD_CFG_NF(GPP_C01, UP_20K, DEEP, NF1),
+};
+
+void mainboard_configure_early_gpios(void)
+{
+	gpio_configure_pads(early_gpio_table, ARRAY_SIZE(early_gpio_table));
+}
diff --git a/src/mainboard/novacustom/mtl-h/hda_verb.c b/src/mainboard/novacustom/mtl-h/hda_verb.c
new file mode 100644
index 0000000000..cd7493e6d3
--- /dev/null
+++ b/src/mainboard/novacustom/mtl-h/hda_verb.c
@@ -0,0 +1,42 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <device/azalia_device.h>
+
+const u32 cim_verb_data[] = {
+	/* Realtek, ALC245 */
+	0x10ec0245, /* Vendor ID */
+	0x1558a763, /* Subsystem ID */
+	13, /* Number of entries */
+	AZALIA_SUBVENDOR(0, 0x1558a763),
+	AZALIA_RESET(1),
+	AZALIA_PIN_CFG(0, 0x12, 0x90a60130),
+	AZALIA_PIN_CFG(0, 0x13, 0x40000000),
+	AZALIA_PIN_CFG(0, 0x14, 0x90170110),
+	AZALIA_PIN_CFG(0, 0x17, 0x411111f0),
+	AZALIA_PIN_CFG(0, 0x18, 0x411111f0),
+	AZALIA_PIN_CFG(0, 0x19, 0x411111f0),
+	AZALIA_PIN_CFG(0, 0x1a, 0x411111f0),
+	AZALIA_PIN_CFG(0, 0x1b, 0x411111f0),
+	AZALIA_PIN_CFG(0, 0x1d, 0x40789b2d),
+	AZALIA_PIN_CFG(0, 0x1e, 0x411111f0),
+	AZALIA_PIN_CFG(0, 0x21, 0x04211020),
+
+	/* Intel Meteor Lake HDMI */
+	0x8086281d, /* Vendor ID */
+	0x80860101, /* Subsystem ID */
+	10, /* Number of entries */
+	AZALIA_SUBVENDOR(2, 0x80860101),
+	AZALIA_PIN_CFG(2, 0x04, 0x18560010),
+	AZALIA_PIN_CFG(2, 0x06, 0x18560010),
+	AZALIA_PIN_CFG(2, 0x08, 0x18560010),
+	AZALIA_PIN_CFG(2, 0x0a, 0x18560010),
+	AZALIA_PIN_CFG(2, 0x0b, 0x18560010),
+	AZALIA_PIN_CFG(2, 0x0c, 0x18560010),
+	AZALIA_PIN_CFG(2, 0x0d, 0x18560010),
+	AZALIA_PIN_CFG(2, 0x0e, 0x18560010),
+	AZALIA_PIN_CFG(2, 0x0f, 0x18560010),
+};
+
+const u32 pc_beep_verbs[] = {};
+
+AZALIA_ARRAY_SIZES;
diff --git a/src/mainboard/novacustom/mtl-h/include/mainboard/gpio.h b/src/mainboard/novacustom/mtl-h/include/mainboard/gpio.h
new file mode 100644
index 0000000000..57924a615f
--- /dev/null
+++ b/src/mainboard/novacustom/mtl-h/include/mainboard/gpio.h
@@ -0,0 +1,17 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef MAINBOARD_GPIO_H
+#define MAINBOARD_GPIO_H
+
+#ifndef PAD_CFG_GPIO_BIDIRECT
+#define PAD_CFG_GPIO_BIDIRECT(pad, val, pull, rst, trig, own)		\
+	_PAD_CFG_STRUCT(pad,						\
+		PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_TRIG(trig) |	\
+		PAD_BUF(NO_DISABLE) | val,				\
+		PAD_PULL(pull) | PAD_CFG_OWN_GPIO(own))
+#endif
+
+void mainboard_configure_early_gpios(void);
+void mainboard_configure_gpios(void);
+
+#endif
diff --git a/src/mainboard/novacustom/mtl-h/ramstage.c b/src/mainboard/novacustom/mtl-h/ramstage.c
new file mode 100644
index 0000000000..cd7031ba01
--- /dev/null
+++ b/src/mainboard/novacustom/mtl-h/ramstage.c
@@ -0,0 +1,42 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <ec/dasharo/ec/acpi.h>
+#include <mainboard/gpio.h>
+#include <smbios.h>
+#include <soc/ramstage.h>
+
+const char *smbios_system_sku(void)
+{
+	return "Not Applicable";
+}
+
+smbios_enclosure_type smbios_mainboard_enclosure_type(void)
+{
+	return SMBIOS_ENCLOSURE_NOTEBOOK;
+}
+
+smbios_wakeup_type smbios_system_wakeup_type(void)
+{
+	return SMBIOS_WAKEUP_TYPE_POWER_SWITCH;
+}
+
+static void mainboard_init(void *chip_info)
+{
+	mainboard_configure_gpios();
+}
+
+struct chip_operations mainboard_ops = {
+	.init = mainboard_init,
+};
+
+void mainboard_silicon_init_params(FSP_S_CONFIG *params)
+{
+	// Enable reporting CPU C10 state over eSPI
+	params->PchEspiHostC10ReportEnable = 1;
+
+	// Pinmux configuration
+	params->CnviRfResetPinMux = 0x194CE404; // GPP_F04
+	params->CnviClkreqPinMux = 0x394CE605;  // GPP_F05
+
+	params->LidStatus = dasharo_ec_get_lid_state();
+}
diff --git a/src/mainboard/novacustom/mtl-h/romstage.c b/src/mainboard/novacustom/mtl-h/romstage.c
new file mode 100644
index 0000000000..8fdd9eca61
--- /dev/null
+++ b/src/mainboard/novacustom/mtl-h/romstage.c
@@ -0,0 +1,31 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <soc/meminit.h>
+#include <soc/romstage.h>
+
+void mainboard_memory_init_params(FSPM_UPD *mupd)
+{
+	const bool half_populated = false;
+
+	static const struct mb_cfg mem_config = {
+		.type = MEM_TYPE_DDR5,
+
+		.ect = true, /* Early Command Training */
+
+		.UserBd = BOARD_TYPE_ULT_ULX,
+	};
+	const struct mem_spd dimm_module_spd_info = {
+		.topo = MEM_TOPO_DIMM_MODULE,
+
+		.smbus = {
+			[0] = {
+				.addr_dimm[0] = 0x50,
+			},
+			[1] = {
+				.addr_dimm[0] = 0x52,
+			},
+		},
+	};
+
+	memcfg_init(mupd, &mem_config, &dimm_module_spd_info, half_populated);
+}
diff --git a/src/mainboard/novacustom/mtl-h/vboot-rwab.fmd b/src/mainboard/novacustom/mtl-h/vboot-rwab.fmd
new file mode 100644
index 0000000000..18a5027593
--- /dev/null
+++ b/src/mainboard/novacustom/mtl-h/vboot-rwab.fmd
@@ -0,0 +1,49 @@
+FLASH 32M {
+	SI_ALL 9M {
+		SI_DESC 16K
+		SI_GBE 8K
+		SI_ME
+	}
+	SI_BIOS {
+		RW_SECTION_A 7M {
+			VBLOCK_A 8K
+			FW_MAIN_A(CBFS)
+			RW_FWID_A 256
+		}
+
+		# This section starts at the 16M boundary in SPI flash.
+		# MTL does not support a region crossing this boundary,
+		# because the SPI flash is memory-mapped into two non-
+		# contiguous windows.
+		RW_MISC 2M {
+			UNIFIED_MRC_CACHE(PRESERVE) 128K {
+				RECOVERY_MRC_CACHE 64K
+				RW_MRC_CACHE 64K
+			}
+			SMMSTORE(PRESERVE) 256K
+			RW_ELOG(PRESERVE) 16K
+			RW_SHARED 16K {
+				SHARED_DATA 8K
+				VBLOCK_DEV 8K
+			}
+			RW_NVRAM(PRESERVE) 24K
+			BOOTSPLASH(CBFS) 1M
+		}
+
+		RW_SECTION_B 7M {
+			VBLOCK_B 8K
+			FW_MAIN_B(CBFS)
+			RW_FWID_B 256
+		}
+
+		WP_RO 7M {
+			RO_VPD(PRESERVE) 16K
+			RO_SECTION {
+				FMAP 2K
+				RO_FRID 256
+				GBB@4K 12K
+				COREBOOT(CBFS)
+			}
+		}
+	}
+}

From 2988beac8e5df0b5cddd9b7c7fbcf9ca12b679b0 Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Sun, 16 Feb 2025 13:00:15 -0600
Subject: [PATCH 0132/3886] Kconfig: Rework SYSTEM_TYPE_XX to better map to
 SMBIOS

Add SYSTEM_TYPE_SERVER and SYSTEM_TYPE_ALL_INE_ONE; rename
SYSTEM_TYPE_BOX to SYSTEM_TYPE_MINIPC. Map these entries to the
analogous SMBIOS enclosure types.

Follow-on patches will have mainboards select these new SYSTEM_TYPE
entries as appropriate.

Change-Id: I2a35101ccc60daf4863568216ef145c9c701140b
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86454
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Andy Ebrahiem <ahmet.ebrahiem@9elements.com>
---
 src/Kconfig                       | 28 ++++++++++++++++++----------
 src/lib/smbios_defaults.c         |  6 ++++++
 src/mainboard/google/brya/Kconfig |  4 ++--
 3 files changed, 26 insertions(+), 12 deletions(-)

diff --git a/src/Kconfig b/src/Kconfig
index 1d71840308..e4c8467f21 100644
--- a/src/Kconfig
+++ b/src/Kconfig
@@ -652,18 +652,11 @@ endmenu
 # load site-local kconfig to allow user specific defaults and overrides
 source "site-local/Kconfig"
 
-config SYSTEM_TYPE_BOX
-	default n
-	bool
-	help
-	  For devices like chromebox, mac-mini etc. These devices
-	  without built-in display and operates on AC supply alone.
-
-config SYSTEM_TYPE_LAPTOP
+config SYSTEM_TYPE_ALL_IN_ONE
 	default n
 	bool
 
-config SYSTEM_TYPE_TABLET
+config SYSTEM_TYPE_CONVERTIBLE
 	default n
 	bool
 
@@ -671,7 +664,22 @@ config SYSTEM_TYPE_DETACHABLE
 	default n
 	bool
 
-config SYSTEM_TYPE_CONVERTIBLE
+config SYSTEM_TYPE_LAPTOP
+	default n
+	bool
+
+config SYSTEM_TYPE_MINIPC
+	default n
+	bool
+	help
+	  For devices like chromebox, mac-mini etc. These devices
+	  without built-in display and operates on AC supply alone.
+
+config SYSTEM_TYPE_SERVER
+	default n
+	bool
+
+config SYSTEM_TYPE_TABLET
 	default n
 	bool
 
diff --git a/src/lib/smbios_defaults.c b/src/lib/smbios_defaults.c
index 0ad6442a4f..ba6b231741 100644
--- a/src/lib/smbios_defaults.c
+++ b/src/lib/smbios_defaults.c
@@ -99,6 +99,12 @@ __weak smbios_enclosure_type smbios_mainboard_enclosure_type(void)
 		return SMBIOS_ENCLOSURE_CONVERTIBLE;
 	else if (CONFIG(SYSTEM_TYPE_DETACHABLE))
 		return SMBIOS_ENCLOSURE_DETACHABLE;
+	else if (CONFIG(SYSTEM_TYPE_SERVER))
+		return SMBIOS_ENCLOSURE_MAIN_SERVER_CHASSIS;
+	else if (CONFIG(SYSTEM_TYPE_MINIPC))
+		return SMBIOS_ENCLOSURE_MINI_PC;
+	else if (CONFIG(SYSTEM_TYPE_ALL_IN_ONE))
+		return SMBIOS_ENCLOSURE_ALL_IN_ONE;
 	else
 		return SMBIOS_ENCLOSURE_DESKTOP;
 }
diff --git a/src/mainboard/google/brya/Kconfig b/src/mainboard/google/brya/Kconfig
index fc18f8f660..31948fbdb7 100644
--- a/src/mainboard/google/brya/Kconfig
+++ b/src/mainboard/google/brya/Kconfig
@@ -97,7 +97,7 @@ config BOARD_GOOGLE_BASEBOARD_NISSA
 	select SOC_INTEL_ALDERLAKE_PCH_N
 	select SOC_INTEL_CSE_LITE_COMPRESS_ME_RW
 	select SOC_INTEL_CSE_LITE_SYNC_IN_RAMSTAGE
-	select SYSTEM_TYPE_LAPTOP if !SYSTEM_TYPE_BOX
+	select SYSTEM_TYPE_LAPTOP if !SYSTEM_TYPE_MINIPC
 	select TPM_GOOGLE_TI50
 	select SOC_INTEL_COMMON_MMC_OVERRIDE
 
@@ -223,7 +223,7 @@ config BOARD_GOOGLE_CROTA
 config BOARD_GOOGLE_DIRKS
 	select BOARD_GOOGLE_BASEBOARD_NISSA
 	select SOC_INTEL_TWINLAKE
-	select SYSTEM_TYPE_BOX
+	select SYSTEM_TYPE_MINIPC
 
 config BOARD_GOOGLE_DOCHI
 	select BOARD_GOOGLE_BASEBOARD_BRYA

From 620eb090ddeb49dbe78512f057af45f22bc6764e Mon Sep 17 00:00:00 2001
From: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Date: Mon, 17 Feb 2025 10:44:34 +0800
Subject: [PATCH 0133/3886] mb/trulo/var/uldrenite: Add Fn support and clean up
 Kconfig order

Support Fn key on uldrenite emits a scancode of 94 (0x5e) and order the
Kconfig.

BUG=b:394749952
TEST=fn + top row (F1~F12) keys work fine

Change-Id: I92c1bd200f1849a460943bdb96ab122d464a0f40
Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86474
Reviewed-by: John Su <john_su@compal.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Andy Ebrahiem <ahmet.ebrahiem@9elements.com>
Reviewed-by: Eric Lai <ericllai@google.com>
---
 src/mainboard/google/brya/Kconfig | 7 ++++---
 1 file changed, 4 insertions(+), 3 deletions(-)

diff --git a/src/mainboard/google/brya/Kconfig b/src/mainboard/google/brya/Kconfig
index 31948fbdb7..2e57055b1e 100644
--- a/src/mainboard/google/brya/Kconfig
+++ b/src/mainboard/google/brya/Kconfig
@@ -643,12 +643,13 @@ config BOARD_GOOGLE_ULDRENITE
 	select BOARD_GOOGLE_BASEBOARD_TRULO
 	select BOARD_ROMSIZE_KB_32768
 	select CHROMEOS_WIFI_SAR if CHROMEOS
-	select SOC_INTEL_TCSS_USE_PDC_PMC_USBC_MUX_CONFIGURATION
+	select DRIVERS_WWAN_FM350GL
+	select ENFORCE_MEM_CHANNEL_DISABLE
 	select HAVE_PCIE_WWAN
 	select HAVE_WWAN_POWER_SEQUENCE
-	select DRIVERS_WWAN_FM350GL
+	select MAINBOARD_HAS_GOOGLE_STRAUSS_KEYBOARD
 	select SOC_INTEL_COMMON_BLOCK_HDA_VERB
-	select ENFORCE_MEM_CHANNEL_DISABLE
+	select SOC_INTEL_TCSS_USE_PDC_PMC_USBC_MUX_CONFIGURATION
 
 config BOARD_GOOGLE_VELL
 	select BOARD_GOOGLE_BASEBOARD_BRYA

From fe018334af248392316e32b309a4c0241e9ba585 Mon Sep 17 00:00:00 2001
From: David Wu <david_wu@quanta.corp-partner.google.com>
Date: Mon, 20 Jan 2025 15:57:39 +0800
Subject: [PATCH 0134/3886] mb/google/brya: Create moxie variant

Create the moxie variant of the kuldax project by
copying the files to a new directory named for the variant.

BUG=b:389391652
TEST=util/abuild/abuild -p none -t google/brya -x -a
make sure the build includes GOOGLE_MOXIE

Change-Id: Ie2b4888e4150cf2110fbcd57906b3496c97f6712
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86061
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jayvik Desai <jayvik@google.com>
Reviewed-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
---
 src/mainboard/google/brya/Kconfig             |  12 +
 src/mainboard/google/brya/Kconfig.name        |   3 +
 .../google/brya/variants/moxie/Makefile.mk    |   9 +
 .../google/brya/variants/moxie/data.vbt       | Bin 0 -> 8704 bytes
 .../google/brya/variants/moxie/fw_config.c    |  75 ++++
 .../google/brya/variants/moxie/gpio.c         | 133 +++++++
 .../brya/variants/moxie/include/variant/ec.h  |   8 +
 .../variants/moxie/include/variant/gpio.h     |   8 +
 .../brya/variants/moxie/overridetree.cb       | 347 ++++++++++++++++++
 .../google/brya/variants/moxie/ramstage.c     |  58 +++
 .../google/brya/variants/moxie/variant.c      |  23 ++
 11 files changed, 676 insertions(+)
 create mode 100644 src/mainboard/google/brya/variants/moxie/Makefile.mk
 create mode 100644 src/mainboard/google/brya/variants/moxie/data.vbt
 create mode 100644 src/mainboard/google/brya/variants/moxie/fw_config.c
 create mode 100644 src/mainboard/google/brya/variants/moxie/gpio.c
 create mode 100644 src/mainboard/google/brya/variants/moxie/include/variant/ec.h
 create mode 100644 src/mainboard/google/brya/variants/moxie/include/variant/gpio.h
 create mode 100644 src/mainboard/google/brya/variants/moxie/overridetree.cb
 create mode 100644 src/mainboard/google/brya/variants/moxie/ramstage.c
 create mode 100644 src/mainboard/google/brya/variants/moxie/variant.c

diff --git a/src/mainboard/google/brya/Kconfig b/src/mainboard/google/brya/Kconfig
index 2e57055b1e..9b0d59bc6e 100644
--- a/src/mainboard/google/brya/Kconfig
+++ b/src/mainboard/google/brya/Kconfig
@@ -361,6 +361,14 @@ config BOARD_GOOGLE_MOLI
 	select BOARD_GOOGLE_BASEBOARD_BRASK
 	select INTEL_GMA_HAVE_VBT
 
+config BOARD_GOOGLE_MOXIE
+	select BOARD_GOOGLE_BASEBOARD_BRASK
+	select CHROMEOS_WIFI_SAR if CHROMEOS
+	select DRIVERS_GENESYSLOGIC_GL9755
+	select EC_GOOGLE_CHROMEEC_INCLUDE_SSFC_IN_FW_CONFIG
+	select INTEL_GMA_HAVE_VBT
+	select SOC_INTEL_RAPTORLAKE
+
 config BOARD_GOOGLE_NIVVIKS
 	select BOARD_GOOGLE_BASEBOARD_NISSA
 	select BOARD_ROMSIZE_KB_32768
@@ -780,6 +788,7 @@ config DRIVER_TPM_I2C_BUS
 	default 0x1 if BOARD_GOOGLE_MARASOV
 	default 0x1 if BOARD_GOOGLE_MITHRAX
 	default 0x1 if BOARD_GOOGLE_MOLI
+	default 0x1 if BOARD_GOOGLE_MOXIE
 	default 0x0 if BOARD_GOOGLE_NEREID
 	default 0x0 if BOARD_GOOGLE_NIVVIKS
 	default 0x1 if BOARD_GOOGLE_NOVA
@@ -862,6 +871,7 @@ config TPM_TIS_ACPI_INTERRUPT
 	default 13 if BOARD_GOOGLE_MARASOV
 	default 13 if BOARD_GOOGLE_MITHRAX
 	default 13 if BOARD_GOOGLE_MOLI
+	default 13 if BOARD_GOOGLE_MOXIE
 	default 13 if BOARD_GOOGLE_NEREID
 	default 13 if BOARD_GOOGLE_NIVVIKS
 	default 13 if BOARD_GOOGLE_NOVA
@@ -948,6 +958,7 @@ config MAINBOARD_PART_NUMBER
 	default "Marasov" if BOARD_GOOGLE_MARASOV
 	default "Mithrax" if BOARD_GOOGLE_MITHRAX
 	default "Moli" if BOARD_GOOGLE_MOLI
+	default "Moxie" if BOARD_GOOGLE_MOXIE
 	default "Nereid" if BOARD_GOOGLE_NEREID
 	default "Nivviks" if BOARD_GOOGLE_NIVVIKS
 	default "Nokris" if BOARD_GOOGLE_NOKRIS
@@ -1023,6 +1034,7 @@ config VARIANT_DIR
 	default "marasov" if BOARD_GOOGLE_MARASOV
 	default "mithrax" if BOARD_GOOGLE_MITHRAX
 	default "moli" if BOARD_GOOGLE_MOLI
+	default "moxie" if BOARD_GOOGLE_MOXIE
 	default "nereid" if BOARD_GOOGLE_NEREID
 	default "nereid" if BOARD_GOOGLE_TEREID
 	default "nivviks" if BOARD_GOOGLE_NIVVIKS
diff --git a/src/mainboard/google/brya/Kconfig.name b/src/mainboard/google/brya/Kconfig.name
index 6007aa2c2a..db99d326f3 100644
--- a/src/mainboard/google/brya/Kconfig.name
+++ b/src/mainboard/google/brya/Kconfig.name
@@ -98,6 +98,9 @@ config BOARD_GOOGLE_MITHRAX
 config BOARD_GOOGLE_MOLI
 	bool "->  Moli"
 
+config BOARD_GOOGLE_MOXIE
+	bool "->  Moxie"
+
 config BOARD_GOOGLE_NIVVIKS
 	bool "->  Nivviks"
 
diff --git a/src/mainboard/google/brya/variants/moxie/Makefile.mk b/src/mainboard/google/brya/variants/moxie/Makefile.mk
new file mode 100644
index 0000000000..e31aaa1707
--- /dev/null
+++ b/src/mainboard/google/brya/variants/moxie/Makefile.mk
@@ -0,0 +1,9 @@
+# SPDX-License-Identifier: GPL-2.0-only
+bootblock-y += gpio.c
+
+romstage-y += gpio.c
+
+ramstage-y += gpio.c
+ramstage-y += ramstage.c
+ramstage-$(CONFIG_FW_CONFIG) += fw_config.c
+ramstage-$(CONFIG_FW_CONFIG) += variant.c
diff --git a/src/mainboard/google/brya/variants/moxie/data.vbt b/src/mainboard/google/brya/variants/moxie/data.vbt
new file mode 100644
index 0000000000000000000000000000000000000000..7d14588c613c3501ddb3970a2254560b709b00a0
GIT binary patch
literal 8704
zcmeHMO>7%Q6n?X7Z(QS$Z4<R_Xu~9_QYSRY+G#@?S?c;Hp>FeIJ85twq&TS!jp{aT
znxcS^vPd}uA*7X%P+EbokPwhlICJr(5D6r#9x9MHMB-9aaI3_n#k`r_*m2qrmr`gd
zKkMy`=e_y%y>Dh`XLk>c`A4a5AlMfj@SW~!4^xx`C~&_qg~tcQ9~vGR5Bf%Z<Nkr+
zz-jsi?1dj1|GWc`AY{M8ttjr$rP*Z46>X)1)00!FWM?pW<-+WAnuY@*>N|HXnM%$~
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zAOeI5z;2>G(C<5O^?|lmt#+6|y?}ZZbsqIS)DKZVLHz>tYt(O0Z=n8&`ZMaUsK2A`
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z%gULH+*R2A_h;B$V*D0sAH7x_nbMlXrRS!x11Poa@PEgnc8Tw;c6c6@@GA^d7^pB%
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M@5b+0upw=K0cSRME&u=k

literal 0
HcmV?d00001

diff --git a/src/mainboard/google/brya/variants/moxie/fw_config.c b/src/mainboard/google/brya/variants/moxie/fw_config.c
new file mode 100644
index 0000000000..42613af163
--- /dev/null
+++ b/src/mainboard/google/brya/variants/moxie/fw_config.c
@@ -0,0 +1,75 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <bootstate.h>
+#include <console/console.h>
+#include <fw_config.h>
+#include <gpio.h>
+
+static const struct pad_config dmic_enable_pads[] = {
+	PAD_CFG_NF(GPP_R6, NONE, DEEP, NF3),	/* DMIC_CLK1_R */
+	PAD_CFG_NF(GPP_R7, NONE, DEEP, NF3),	/* DMIC_DATA1_R */
+};
+
+static const struct pad_config dmic_disable_pads[] = {
+	PAD_NC(GPP_R6, NONE),
+	PAD_NC(GPP_R7, NONE),
+};
+
+static const struct pad_config i2s_enable_pads[] = {
+	PAD_CFG_NF(GPP_R0, NONE, DEEP, NF2),	/* I2S_HP_SCLK_R */
+	PAD_CFG_NF(GPP_R1, NONE, DEEP, NF2),	/* I2S_HP_SFRM_R */
+	PAD_CFG_NF(GPP_R2, DN_20K, DEEP, NF2),	/* I2S_PCH_TX_HP_RX_STRAP */
+	PAD_CFG_NF(GPP_R3, NONE, DEEP, NF2),	/* I2S_PCH_RX_HP_TX */
+};
+
+static const struct pad_config i2s_disable_pads[] = {
+	PAD_NC(GPP_R0, NONE),
+	PAD_NC(GPP_R1, NONE),
+	PAD_NC(GPP_R2, NONE),
+	PAD_NC(GPP_R3, NONE),
+};
+
+static const struct pad_config bt_i2s_enable_pads[] = {
+	PAD_CFG_NF(GPP_VGPIO_30, NONE, DEEP, NF3),	/* BT_I2S_BCLK */
+	PAD_CFG_NF(GPP_VGPIO_31, NONE, DEEP, NF3),	/* BT_I2S_SYNC */
+	PAD_CFG_NF(GPP_VGPIO_32, NONE, DEEP, NF3),	/* BT_I2S_SDO */
+	PAD_CFG_NF(GPP_VGPIO_33, NONE, DEEP, NF3),	/* BT_I2S_SDI */
+	PAD_CFG_NF(GPP_VGPIO_34, NONE, DEEP, NF1),	/* SSP2_SCLK */
+	PAD_CFG_NF(GPP_VGPIO_35, NONE, DEEP, NF1),	/* SSP2_SFRM */
+	PAD_CFG_NF(GPP_VGPIO_36, NONE, DEEP, NF1),	/* SSP_TXD */
+	PAD_CFG_NF(GPP_VGPIO_37, NONE, DEEP, NF1),	/* SSP_RXD */
+};
+
+static const struct pad_config bt_i2s_disable_pads[] = {
+	PAD_NC(GPP_VGPIO_30, NONE),
+	PAD_NC(GPP_VGPIO_31, NONE),
+	PAD_NC(GPP_VGPIO_32, NONE),
+	PAD_NC(GPP_VGPIO_33, NONE),
+	PAD_NC(GPP_VGPIO_34, NONE),
+	PAD_NC(GPP_VGPIO_35, NONE),
+	PAD_NC(GPP_VGPIO_36, NONE),
+	PAD_NC(GPP_VGPIO_37, NONE),
+};
+
+static void fw_config_handle(void *unused)
+{
+	if (!fw_config_is_provisioned() || fw_config_probe(FW_CONFIG(AUDIO, AUDIO_UNKNOWN))) {
+		printk(BIOS_INFO, "Disable audio related GPIO pins.\n");
+		gpio_configure_pads(i2s_disable_pads, ARRAY_SIZE(i2s_disable_pads));
+		gpio_configure_pads(dmic_disable_pads, ARRAY_SIZE(dmic_disable_pads));
+		gpio_configure_pads(bt_i2s_disable_pads, ARRAY_SIZE(bt_i2s_disable_pads));
+		return;
+	}
+
+	if (fw_config_probe(FW_CONFIG(AUDIO, NAU88L25B_I2S))) {
+		printk(BIOS_INFO, "Configure audio over I2S with NAU88L25B.\n");
+		gpio_configure_pads(dmic_enable_pads, ARRAY_SIZE(dmic_enable_pads));
+		gpio_configure_pads(i2s_enable_pads, ARRAY_SIZE(i2s_enable_pads));
+		printk(BIOS_INFO, "BT offload enabled\n");
+		gpio_configure_pads(bt_i2s_enable_pads, ARRAY_SIZE(bt_i2s_enable_pads));
+	} else {
+		printk(BIOS_INFO, "BT offload disabled\n");
+		gpio_configure_pads(bt_i2s_disable_pads, ARRAY_SIZE(bt_i2s_disable_pads));
+	}
+}
+BOOT_STATE_INIT_ENTRY(BS_DEV_ENABLE, BS_ON_ENTRY, fw_config_handle, NULL);
diff --git a/src/mainboard/google/brya/variants/moxie/gpio.c b/src/mainboard/google/brya/variants/moxie/gpio.c
new file mode 100644
index 0000000000..556e8b694c
--- /dev/null
+++ b/src/mainboard/google/brya/variants/moxie/gpio.c
@@ -0,0 +1,133 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <baseboard/gpio.h>
+#include <baseboard/variants.h>
+#include <commonlib/helpers.h>
+#include <soc/gpio.h>
+
+/* Pad configuration in ramstage */
+static const struct pad_config override_gpio_table[] = {
+	/* A14 : USB_OC1# ==> HDMIA_HPD */
+	PAD_CFG_NF(GPP_A14, NONE, DEEP, NF2),
+	/* A15 : USB_OC2# ==> NC */
+	PAD_NC(GPP_A15, NONE),
+	/* A19 : DDSP_HPD1 ==> NC */
+	PAD_NC(GPP_A19, NONE),
+	/* A20 : DDSP_HPD2 ==> NC */
+	PAD_NC(GPP_A20, NONE),
+	/* A21 : DDPC_CTRCLK ==> NC */
+	PAD_NC(GPP_A21, NONE),
+	/* A22 : DDPC_CTRLDATA ==> NC */
+	PAD_NC(GPP_A22, NONE),
+
+	/* B7  : ISH_12C1_SDA ==> PCH_I2C_MISCB_SDA */
+	PAD_CFG_NF_LOCK(GPP_B7, NONE, NF2, LOCK_CONFIG),
+	/* B8  : ISH_I2C1_SCL ==> PCH_I2C_MISCB_SCL */
+	PAD_CFG_NF_LOCK(GPP_B8, NONE, NF2, LOCK_CONFIG),
+
+	/* C3 : SML0CLK ==> USB_C0_AUX_DC_P */
+	PAD_CFG_NF(GPP_C3, NONE, DEEP, NF6),
+	/* C4 : SML0DATA ==> USB_C0_AUX_DC_N */
+	PAD_CFG_NF(GPP_C4, NONE, DEEP, NF6),
+
+	/* D0  : ISH_GP0 ==> NC */
+	PAD_NC_LOCK(GPP_D0, NONE, LOCK_CONFIG),
+	/* D1  : ISH_GP1 ==> NC */
+	PAD_NC_LOCK(GPP_D1, NONE, LOCK_CONFIG),
+	/* D2  : ISH_GP2 ==> NC */
+	PAD_NC_LOCK(GPP_D2, NONE, LOCK_CONFIG),
+	/* D3  : ISH_GP3 ==> NC */
+	PAD_NC_LOCK(GPP_D3, NONE, LOCK_CONFIG),
+	/* D9  : ISH_SPI_CS# ==> NC */
+	PAD_NC_LOCK(GPP_D9, NONE, LOCK_CONFIG),
+
+	/* E20 : DDP2_CTRLCLK ==> HDMIA_CTRLCLK */
+	PAD_CFG_NF(GPP_E20, NONE, DEEP, NF1),
+	/* E21 : DDP2_CTRLDATA ==> HDMIA_CTRLDATA_STRAP */
+	PAD_CFG_NF(GPP_E21, NONE, DEEP, NF1),
+
+	/* F11 : THC1_SPI2_CLK ==> NC */
+	PAD_NC_LOCK(GPP_F11, NONE, LOCK_CONFIG),
+	/* F12 : GSXDOUT ==> NC */
+	PAD_NC_LOCK(GPP_F12, NONE, LOCK_CONFIG),
+	/* F13 : GSXDOUT ==> NC */
+	PAD_NC_LOCK(GPP_F13, NONE, LOCK_CONFIG),
+	/* F15 : GSXSRESET# ==> NC */
+	PAD_NC_LOCK(GPP_F15, NONE, LOCK_CONFIG),
+	/* F16 : GSXCLK ==> NC */
+	PAD_NC_LOCK(GPP_F16, NONE, LOCK_CONFIG),
+
+	/* R4 : HDA_RST# ==> NC */
+	PAD_NC(GPP_R4, NONE),
+	/* R5 : HDA_SDI1 ==> NC */
+	PAD_NC(GPP_R5, NONE),
+};
+
+/* Early pad configuration in bootblock */
+static const struct pad_config early_gpio_table[] = {
+	/* A13 : PMC_I2C_SCL ==> GSC_PCH_INT_ODL */
+	PAD_CFG_GPI_APIC(GPP_A13, NONE, PLTRST, LEVEL, INVERT),
+	/* B4  : PROC_GP3 ==> SSD_PERST_L */
+	PAD_CFG_GPO(GPP_B4, 0, DEEP),
+	/* E15 : RSVD_TP ==> PCH_WP_OD */
+	PAD_CFG_GPI_GPIO_DRIVER(GPP_E15, NONE, DEEP),
+	/* F14 : GSXDIN ==> EN_PP3300_SSD */
+	PAD_CFG_GPO(GPP_F14, 1, DEEP),
+	/* F18 : THC1_SPI2_INT# ==> EC_IN_RW_OD */
+	PAD_CFG_GPI(GPP_F18, NONE, DEEP),
+	/* H6  : I2C1_SDA ==> PCH_I2C_TPM_SDA */
+	PAD_CFG_NF(GPP_H6, NONE, DEEP, NF1),
+	/* H7  : I2C1_SCL ==> PCH_I2C_TPM_SCL */
+	PAD_CFG_NF(GPP_H7, NONE, DEEP, NF1),
+	/* H10 : UART0_RXD ==> UART_PCH_RX_DBG_TX */
+	PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2),
+	/* H11 : UART0_TXD ==> UART_PCH_TX_DBG_RX */
+	PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2),
+	/* H13 : I2C7_SCL ==> EN_PP3300_SD */
+	PAD_CFG_GPO(GPP_H13, 1, DEEP),
+
+	/* CPU PCIe VGPIO for PEG60 */
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_48, NONE, PLTRST, NF1),
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_49, NONE, PLTRST, NF1),
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_50, NONE, PLTRST, NF1),
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_51, NONE, PLTRST, NF1),
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_52, NONE, PLTRST, NF1),
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_53, NONE, PLTRST, NF1),
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_54, NONE, PLTRST, NF1),
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_55, NONE, PLTRST, NF1),
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_56, NONE, PLTRST, NF1),
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_57, NONE, PLTRST, NF1),
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_58, NONE, PLTRST, NF1),
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_59, NONE, PLTRST, NF1),
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_60, NONE, PLTRST, NF1),
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_61, NONE, PLTRST, NF1),
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_62, NONE, PLTRST, NF1),
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_63, NONE, PLTRST, NF1),
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_76, NONE, PLTRST, NF1),
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_77, NONE, PLTRST, NF1),
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_78, NONE, PLTRST, NF1),
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_79, NONE, PLTRST, NF1),
+};
+
+static const struct pad_config romstage_gpio_table[] = {
+	/* B4  : PROC_GP3 ==> SSD_PERST_L */
+	PAD_CFG_GPO(GPP_B4, 1, DEEP),
+};
+
+const struct pad_config *variant_gpio_override_table(size_t *num)
+{
+	*num = ARRAY_SIZE(override_gpio_table);
+	return override_gpio_table;
+}
+
+const struct pad_config *variant_early_gpio_table(size_t *num)
+{
+	*num = ARRAY_SIZE(early_gpio_table);
+	return early_gpio_table;
+}
+
+const struct pad_config *variant_romstage_gpio_table(size_t *num)
+{
+	*num = ARRAY_SIZE(romstage_gpio_table);
+	return romstage_gpio_table;
+}
diff --git a/src/mainboard/google/brya/variants/moxie/include/variant/ec.h b/src/mainboard/google/brya/variants/moxie/include/variant/ec.h
new file mode 100644
index 0000000000..7a2a6ff8b7
--- /dev/null
+++ b/src/mainboard/google/brya/variants/moxie/include/variant/ec.h
@@ -0,0 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#ifndef __VARIANT_EC_H__
+#define __VARIANT_EC_H__
+
+#include <baseboard/ec.h>
+
+#endif
diff --git a/src/mainboard/google/brya/variants/moxie/include/variant/gpio.h b/src/mainboard/google/brya/variants/moxie/include/variant/gpio.h
new file mode 100644
index 0000000000..c4fe342621
--- /dev/null
+++ b/src/mainboard/google/brya/variants/moxie/include/variant/gpio.h
@@ -0,0 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#ifndef VARIANT_GPIO_H
+#define VARIANT_GPIO_H
+
+#include <baseboard/gpio.h>
+
+#endif
diff --git a/src/mainboard/google/brya/variants/moxie/overridetree.cb b/src/mainboard/google/brya/variants/moxie/overridetree.cb
new file mode 100644
index 0000000000..19a20a14ec
--- /dev/null
+++ b/src/mainboard/google/brya/variants/moxie/overridetree.cb
@@ -0,0 +1,347 @@
+fw_config
+	field AUDIO 0 2
+		option AUDIO_UNKNOWN	0
+		option NAU88L25B_I2S	1
+	end
+	field BJ_POWER 3 4
+		option BJ_POWER_150W	0
+		option BJ_POWER_230W	1
+		option BJ_POWER_65W	2
+		option BJ_POWER_135W	3
+	end
+	field MB_USBC 6 7
+		option TC_USB4	0
+		option TC_USB3	1
+	end
+	field USB_HUB 32
+		option HUB_ABSENT	0
+		option HUB_PRESENT	1
+	end
+end
+
+chip soc/intel/alderlake
+	register "domain_vr_config[VR_DOMAIN_IA]" = "{
+		.enable_fast_vmode = 1,
+	}"
+
+	register "sagv" = "SaGv_Enabled"
+
+	register "usb2_ports[1]" = "USB2_PORT_EMPTY"	# Disable USB2 Port 1
+	register "usb2_ports[2]" = "USB2_PORT_EMPTY"	# Disable USB2 Port 2
+	register "usb2_ports[4]" = "USB2_PORT_EMPTY"	# Disable USB2 Port 4
+
+	register "usb3_ports[0]" = "{
+		.enable           = 1,
+		.ocpin            = OC_SKIP,
+		.tx_de_emp        = 0x2B,
+		.tx_downscale_amp = 0x00,
+	}" # Type-A port A0
+	register "usb3_ports[1]" = "{
+		.enable           = 1,
+		.ocpin            = OC_SKIP,
+		.tx_de_emp        = 0x2B,
+		.tx_downscale_amp = 0x00,
+	}" # Type-A port A1
+
+	register "serial_io_gspi_mode" = "{
+		[PchSerialIoIndexGSPI0] = PchSerialIoDisabled,
+		[PchSerialIoIndexGSPI1] = PchSerialIoDisabled,
+	}"
+
+	register "ddi_ports_config" = "{
+		[DDI_PORT_A] = DDI_ENABLE_HPD,
+		[DDI_PORT_B] = DDI_ENABLE_HPD | DDI_ENABLE_DDC,
+		[DDI_PORT_1] = DDI_ENABLE_HPD,
+		[DDI_PORT_3] = DDI_ENABLE_HPD | DDI_ENABLE_DDC,
+	}"
+
+	register "power_limits_config[RPL_P_282_242_142_15W_CORE]" = "{
+		.tdp_pl1_override = 15,
+		.tdp_pl2_override = 55,
+		.tdp_pl4 = 100,
+	}"
+
+	device domain 0 on
+		device ref dtt on
+			chip drivers/intel/dptf
+				## sensor information
+				register "options.tsr[0].desc" = ""DRAM""
+				register "options.tsr[1].desc" = ""Charger""
+
+				# TODO: below values are initial reference values only
+				## Active Policy
+				register "policies.active" = "{
+					[0] = {
+						.target = DPTF_CPU,
+						.thresholds = {
+								TEMP_PCT(85, 90),
+								TEMP_PCT(80, 80),
+								TEMP_PCT(75, 70),
+						}
+					}
+				}"
+
+				## Passive Policy
+				register "policies.passive" = "{
+					[0] = DPTF_PASSIVE(CPU,         CPU,           95, 5000),
+					[1] = DPTF_PASSIVE(CPU,         TEMP_SENSOR_0, 75, 5000),
+					[2] = DPTF_PASSIVE(CHARGER,     TEMP_SENSOR_1, 75, 5000),
+				}"
+
+				## Critical Policy
+				register "policies.critical" = "{
+					[0] = DPTF_CRITICAL(CPU,               105, SHUTDOWN),
+					[1] = DPTF_CRITICAL(TEMP_SENSOR_0,      85, SHUTDOWN),
+					[2] = DPTF_CRITICAL(TEMP_SENSOR_1,      85, SHUTDOWN),
+				}"
+
+				register "controls.power_limits" = "{
+					.pl1 = {
+							.min_power = 3000,
+							.max_power = 15000,
+							.time_window_min = 28 * MSECS_PER_SEC,
+							.time_window_max = 32 * MSECS_PER_SEC,
+							.granularity = 200,
+						},
+					.pl2 = {
+							.min_power = 55000,
+							.max_power = 55000,
+							.time_window_min = 28 * MSECS_PER_SEC,
+							.time_window_max = 32 * MSECS_PER_SEC,
+							.granularity = 1000,
+						}
+				}"
+
+				## Charger Performance Control (Control, mA)
+				register "controls.charger_perf" = "{
+					[0] = { 255, 1700 },
+					[1] = {  24, 1500 },
+					[2] = {  16, 1000 },
+					[3] = {   8,  500 }
+				}"
+
+				## Fan Performance Control (Percent, Speed, Noise, Power)
+				register "controls.fan_perf" = "{
+					[0] = {  90, 6700, 220, 2200, },
+					[1] = {  80, 5800, 180, 1800, },
+					[2] = {  70, 5000, 145, 1450, },
+					[3] = {  60, 4900, 115, 1150, },
+					[4] = {  50, 3838,  90,  900, },
+					[5] = {  40, 2904,  55,  550, },
+					[6] = {  30, 2337,  30,  300, },
+					[7] = {  20, 1608,  15,  150, },
+					[8] = {  10,  800,  10,  100, },
+					[9] = {   0,    0,   0,   50, }
+				}"
+
+				## Fan options
+				register "options.fan.fine_grained_control" = "true"
+				register "options.fan.step_size" = "2"
+
+				device generic 0 alias dptf_policy on end
+			end
+		end
+		device ref pcie4_0 on
+			# Enable CPU PCIE RP 1 using CLK 0
+			register "cpu_pcie_rp[CPU_RP(1)]" = "{
+				.clk_req = 0,
+				.clk_src = 0,
+				.flags = PCIE_RP_LTR | PCIE_RP_AER,
+			}"
+		end
+		device ref tbt_pcie_rp0 on
+			probe MB_USBC TC_USB4
+		end
+		device ref tbt_pcie_rp1 on
+			probe MB_USBC TC_USB4
+		end
+		device ref tbt_pcie_rp2 on
+			probe MB_USBC TC_USB4
+		end
+		device ref tcss_dma0 on
+			probe MB_USBC TC_USB4
+			chip drivers/intel/usb4/retimer
+				register "dfp[0].power_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E4)"
+				use tcss_usb3_port1 as dfp[0].typec_port
+				device generic 0 on end
+			end
+		end
+		device ref cnvi_wifi on
+			chip drivers/wifi/generic
+				register "wake" = "GPE0_PME_B0"
+				device generic 0 on end
+			end
+		end
+		device ref i2c0 on
+			chip drivers/i2c/nau8825
+				register "irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPP_A23)"
+				register "jkdet_enable" = "1"
+				register "jkdet_pull_enable" = "0"
+				register "jkdet_pull_up" = "0"
+				register "jkdet_polarity" = "1"      # ActiveLow
+				register "vref_impedance" = "2"      # 125kOhm
+				register "micbias_voltage" = "6"     # 2.754
+				register "sar_threshold_num" = "4"
+				register "sar_threshold[0]" = "0x0C"
+				register "sar_threshold[1]" = "0x1C"
+				register "sar_threshold[2]" = "0x38"
+				register "sar_threshold[3]" = "0x60"
+				register "sar_hysteresis" = "1"
+				register "sar_voltage" = "0"          # VDDA
+				register "sar_compare_time" = "0"     # 500ns
+				register "sar_sampling_time" = "0"    # 2us
+				register "short_key_debounce" = "2"   # 100ms
+				register "jack_insert_debounce" = "7" # 512ms
+				register "jack_eject_debounce" = "7"  # 512ms
+				device i2c 1a on
+					probe AUDIO NAU88L25B_I2S
+				end
+			end
+		end
+		device ref pcie_rp7 on
+			chip drivers/net
+				register "wake" = "GPE0_DW0_07"
+				register "led_feature" = "0xe0"
+				register "customized_leds" = "0x05af"
+				register "customized_led0" = "0x23f"
+				register "customized_led2" = "0x028"
+				register "enable_aspm_l1_2" = "1"
+				register "add_acpi_dma_property" = "true"
+				device pci 00.0 on end
+			end
+		end # RTL8125 and RTL8111K Ethernet NIC
+		device ref pcie_rp8 on
+			chip soc/intel/common/block/pcie/rtd3
+				register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_H13)"
+				register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D18)"
+				register "srcclk_pin" = "3"
+				device generic 0 on end
+			end
+		end	#PCIE8 SD card
+		device ref gspi1 off end
+		device ref pch_espi on
+			chip ec/google/chromeec
+				use conn0 as mux_conn[0]
+				device pnp 0c09.0 on end
+			end
+		end
+		device ref pmc hidden
+			chip drivers/intel/pmc_mux
+				device generic 0 on
+					chip drivers/intel/pmc_mux/conn
+						use usb2_port1 as usb2_port
+						use tcss_usb3_port1 as usb3_port
+						device generic 0 alias conn0 on end
+					end
+				end
+			end
+		end
+		device ref tcss_xhci on
+			chip drivers/usb/acpi
+				device ref tcss_root_hub on
+					chip drivers/usb/acpi
+						register "desc" = ""USB3 Type-C Port C0 (MLB)""
+						register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
+						register "use_custom_pld" = "true"
+						register "custom_pld" = "ACPI_PLD_TYPE_C(BACK, RIGHT, ACPI_PLD_GROUP(1, 1))"
+						device ref tcss_usb3_port1 on end
+					end
+				end
+			end
+		end
+		device ref xhci on
+			chip drivers/usb/acpi
+				device ref xhci_root_hub on
+					chip drivers/usb/acpi
+						register "desc" = ""USB2 Type-C Port C0 (MLB)""
+						register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
+						register "use_custom_pld" = "true"
+						register "custom_pld" = "ACPI_PLD_TYPE_C(BACK, RIGHT, ACPI_PLD_GROUP(1, 1))"
+						device ref usb2_port1 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB2 Type-A Port A3 (MLB)""
+						register "type" = "UPC_TYPE_A"
+						register "use_custom_pld" = "true"
+						register "custom_pld" = "ACPI_PLD_TYPE_A(BACK, LEFT, ACPI_PLD_GROUP(5, 1))"
+						device ref usb2_port6 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB2 Type-A Port A2 (MLB)""
+						register "type" = "UPC_TYPE_A"
+						register "use_custom_pld" = "true"
+						register "custom_pld" = "ACPI_PLD_TYPE_A(BACK, CENTER, ACPI_PLD_GROUP(6, 1))"
+						device ref usb2_port7 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB2 Type-A Port A1 (MLB)""
+						register "type" = "UPC_TYPE_A"
+						register "use_custom_pld" = "true"
+						register "custom_pld" = "ACPI_PLD_TYPE_A(FRONT, LEFT, ACPI_PLD_GROUP(4, 1))"
+						device ref usb2_port8 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB2 Type-A Port A0 (MLB)""
+						register "type" = "UPC_TYPE_A"
+						register "use_custom_pld" = "true"
+						register "custom_pld" = "ACPI_PLD_TYPE_A(FRONT, RIGHT, ACPI_PLD_GROUP(1, 2))"
+						device ref usb2_port9 on
+							probe USB_HUB HUB_ABSENT
+						end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB2 Hub for Type-A Port A0/A4/A5 (MLB)""
+						register "type" = "UPC_TYPE_INTERNAL"
+						device ref usb2_port9 on
+							probe USB_HUB HUB_PRESENT
+						end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB2 Bluetooth""
+						register "type" = "UPC_TYPE_INTERNAL"
+						register "reset_gpio" =
+							"ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D4)"
+						device ref usb2_port10 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB3 Type-A Port A0 (MLB)""
+						register "type" = "UPC_TYPE_USB3_A"
+						register "use_custom_pld" = "true"
+						register "custom_pld" = "ACPI_PLD_TYPE_A(FRONT, RIGHT, ACPI_PLD_GROUP(1, 2))"
+						device ref usb3_port1 on
+							probe USB_HUB HUB_ABSENT
+						end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB3 Hub for Type-A Port A0/A4/A5 (MLB)""
+						register "type" = "UPC_TYPE_INTERNAL"
+						device ref usb3_port1 on
+							probe USB_HUB HUB_PRESENT
+						end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB3 Type-A Port A1 (MLB)""
+						register "type" = "UPC_TYPE_USB3_A"
+						register "use_custom_pld" = "true"
+						register "custom_pld" = "ACPI_PLD_TYPE_A(FRONT, LEFT, ACPI_PLD_GROUP(4, 1))"
+						device ref usb3_port2 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB3 Type-A Port A2 (MLB)""
+						register "type" = "UPC_TYPE_USB3_A"
+						register "use_custom_pld" = "true"
+						register "custom_pld" = "ACPI_PLD_TYPE_A(BACK, CENTER, ACPI_PLD_GROUP(6, 1))"
+						device ref usb3_port3 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB3 Type-A Port A3 (MLB)""
+						register "type" = "UPC_TYPE_USB3_A"
+						register "use_custom_pld" = "true"
+						register "custom_pld" = "ACPI_PLD_TYPE_A(BACK, LEFT, ACPI_PLD_GROUP(5, 1))"
+						device ref usb3_port4 on end
+					end
+				end
+			end
+		end
+	end
+end
diff --git a/src/mainboard/google/brya/variants/moxie/ramstage.c b/src/mainboard/google/brya/variants/moxie/ramstage.c
new file mode 100644
index 0000000000..f4f80bebe0
--- /dev/null
+++ b/src/mainboard/google/brya/variants/moxie/ramstage.c
@@ -0,0 +1,58 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <baseboard/variants.h>
+#include <chip.h>
+#include <device/device.h>
+#include <device/pci_ids.h>
+#include <device/pci_ops.h>
+#include <ec/google/chromeec/ec.h>
+#include <fw_config.h>
+#include <intelblocks/power_limit.h>
+
+const struct cpu_power_limits limits[] = {
+	/* SKU_ID, TDP (Watts), pl1_min, pl1_max, pl2_min, pl2_max, pl4 */
+	{ PCI_DID_INTEL_RPL_P_ID_5, 15, 15000, 15000,  55000,  55000, 100000 },
+	{ PCI_DID_INTEL_RPL_P_ID_4, 15, 15000, 15000,  55000,  55000, 100000 },
+	{ PCI_DID_INTEL_RPL_P_ID_3, 15, 15000, 15000,  55000,  55000, 100000 },
+};
+
+const struct system_power_limits sys_limits[] = {
+	/* SKU_ID, TDP (Watts), psys_pl2 (Watts) */
+	{ PCI_DID_INTEL_RPL_P_ID_5, 15, 138 },
+	{ PCI_DID_INTEL_RPL_P_ID_4, 15, 138 },
+	{ PCI_DID_INTEL_RPL_P_ID_3, 15, 138 },
+};
+
+/*
+ * Psys_pmax considerations.
+ *
+ * Given the hardware design in moxie, the serial shunt resistor is 0.005ohm.
+ * The full scale of hardware PSYS signal 1.6v maps to system current 11.25A
+ * instead of real system power. The equation is shown below:
+ * PSYS = 1.6v = (0.005ohm x 11.25A) x 50 (INA213, gain 50V/V) x R501/(R501 + R510)
+ * R501/(R501 + R510) = 0.57 = 20K / (20K + 15K)
+ *
+ * The Psys_pmax is a SW setting which tells IMVP9.1 the mapping b/w system input
+ * current and the actual system power. Since there is no voltage information
+ * from PSYS, different voltage input would map to different Psys_pmax settings:
+ * For Type-C 15V, the Psys_pmax should be 15v x 11.25A = 168.75W
+ * For Type-C 20V, the Psys_pmax should be 20v x 11.25A = 225W
+ * For a barrel jack, the Psys_pmax should be 20v x 11.25A = 225W
+ *
+ * Imagine that there is a type-c 100W (20V/5A) connected to DUT w/ full loading,
+ * and the Psys_pmax setting is 225W. Then IMVP9.1 can calculate the current system
+ * power = 225W * 5A / 11.25A = 100W, which is the actual system power.
+ */
+const struct psys_config psys_config = {
+	.efficiency = 97,
+	.psys_imax_ma = 11250,
+	.bj_volts_mv = 20000
+};
+
+void variant_devtree_update(void)
+{
+	size_t total_entries = ARRAY_SIZE(limits);
+	variant_update_psys_power_limits(limits, sys_limits, total_entries, &psys_config);
+
+	variant_update_power_limits(limits, total_entries);
+}
diff --git a/src/mainboard/google/brya/variants/moxie/variant.c b/src/mainboard/google/brya/variants/moxie/variant.c
new file mode 100644
index 0000000000..b7cba968a5
--- /dev/null
+++ b/src/mainboard/google/brya/variants/moxie/variant.c
@@ -0,0 +1,23 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <baseboard/variants.h>
+#include <chip.h>
+#include <fw_config.h>
+#include <sar.h>
+
+const char *get_wifi_sar_cbfs_filename(void)
+{
+	return "wifi_sar_0.hex";
+}
+
+void variant_update_soc_chip_config(struct soc_intel_alderlake_config *config)
+{
+	config->cnvi_bt_audio_offload = fw_config_probe(FW_CONFIG(AUDIO,
+							NAU88L25B_I2S));
+
+	if (fw_config_probe(FW_CONFIG(MB_USBC, TC_USB3))) {
+		config->tcss_aux_ori = 1;
+		config->typec_aux_bias_pads[0].pad_auxp_dc = GPP_C3;
+		config->typec_aux_bias_pads[0].pad_auxn_dc = GPP_C4;
+	}
+}

From 2e2b35062e0df056a0168e3219e9b3c321319170 Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Sun, 16 Feb 2025 18:14:33 -0600
Subject: [PATCH 0135/3886] mb/google/brya: Set SYSTEM_TYPE_MINIPC for brask
 baseboard boards

Brask devices are all Chromeboxes, so select SYSTEM_TYPE_MINIPC to
ensure the SMBIOS enclosure type is set correctly.

Change-Id: I133a26223ad204dfad67e136cf342d2fb2a7205e
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86469
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
---
 src/mainboard/google/brya/Kconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/src/mainboard/google/brya/Kconfig b/src/mainboard/google/brya/Kconfig
index 9b0d59bc6e..0f1c3c50e6 100644
--- a/src/mainboard/google/brya/Kconfig
+++ b/src/mainboard/google/brya/Kconfig
@@ -68,6 +68,7 @@ config BOARD_GOOGLE_BASEBOARD_BRASK
 	select RT8168_GET_MAC_FROM_VPD
 	select RT8168_SET_LED_MODE
 	select SOC_INTEL_ALDERLAKE_PCH_P
+	select SYSTEM_TYPE_MINIPC
 	select TPM_GOOGLE_CR50
 
 config BOARD_GOOGLE_BASEBOARD_HADES

From d0c1a4966fa9cf6d98c2441316c26e881750369c Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Sun, 16 Feb 2025 18:19:46 -0600
Subject: [PATCH 0136/3886] mb/purism/librem_cnl: Set SYSTEM_TYPE_MINIPC for
 Librem mini v1/v2

Ensures SMBIOS enslosure type set properly.

Change-Id: I047e6319b70f2747796869151bf361afe4c3e961
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86470
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathon Hall <jonathon.hall@puri.sm>
---
 src/mainboard/purism/librem_cnl/Kconfig | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/src/mainboard/purism/librem_cnl/Kconfig b/src/mainboard/purism/librem_cnl/Kconfig
index ab6a67f48d..a718678605 100644
--- a/src/mainboard/purism/librem_cnl/Kconfig
+++ b/src/mainboard/purism/librem_cnl/Kconfig
@@ -20,6 +20,7 @@ config BOARD_PURISM_LIBREM_MINI
 	select HAVE_OPTION_TABLE
 	select SOC_INTEL_WHISKEYLAKE
 	select SUPERIO_ITE_IT8528E
+	select SYSTEM_TYPE_MINIPC
 
 config BOARD_PURISM_LIBREM_MINI_V2
 	select BOARD_PURISM_BASEBOARD_LIBREM_CNL
@@ -27,6 +28,7 @@ config BOARD_PURISM_LIBREM_MINI_V2
 	select HAVE_OPTION_TABLE
 	select SOC_INTEL_COMETLAKE_1
 	select SUPERIO_ITE_IT8528E
+	select SYSTEM_TYPE_MINIPC
 
 config BOARD_PURISM_LIBREM_14
 	select BOARD_PURISM_BASEBOARD_LIBREM_CNL

From 2d35aceeb3013cbceae9aea7f648195be87524f5 Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Sun, 16 Feb 2025 18:21:24 -0600
Subject: [PATCH 0137/3886] mb/starlabs/byte: Set SYSTEM_TYPE_MINIPC

Ensures SMBIOS enclosure type set properly.

Change-Id: I65ca75a57dbc4a9251316d48bf660dd631c716dd
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86471
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/starlabs/byte_adl/Kconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/src/mainboard/starlabs/byte_adl/Kconfig b/src/mainboard/starlabs/byte_adl/Kconfig
index 77a4ea4c0e..51fa7aa77a 100644
--- a/src/mainboard/starlabs/byte_adl/Kconfig
+++ b/src/mainboard/starlabs/byte_adl/Kconfig
@@ -10,6 +10,7 @@ config BOARD_STARLABS_BYTE_SERIES
 	select INTEL_LPSS_UART_FOR_CONSOLE
 	select NO_UART_ON_SUPERIO
 	select SOC_INTEL_COMMON_BLOCK_HDA_VERB
+	select SYSTEM_TYPE_MINIPC
 	select VALIDATE_INTEL_DESCRIPTOR
 
 config BOARD_STARLABS_BYTE_ADL

From 270d4b6b334ce64cafc18e970dc7cf88b517100d Mon Sep 17 00:00:00 2001
From: David Wu <david_wu@quanta.corp-partner.google.com>
Date: Mon, 17 Feb 2025 15:50:42 +0800
Subject: [PATCH 0138/3886] mb/google/nissa/var/dirks: Generate SPD ID for
 supported parts

Add supported memory parts in mem_parts_used.txt, and generate
SPD id for these parts.

1. K3KL9L90CM-MGCT (SAMSUNG)
2. H58G66BK8BX067 (HYNIX)

BUG=b:388117663
TEST=Run part_id_gen tool and check the generated files.

Change-Id: I1ca97e28852660cae0352d771e30c9348a5939a0
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86477
Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/google/brya/variants/dirks/memory/Makefile.mk     | 2 ++
 .../google/brya/variants/dirks/memory/dram_id.generated.txt     | 2 ++
 .../google/brya/variants/dirks/memory/mem_parts_used.txt        | 2 ++
 3 files changed, 6 insertions(+)

diff --git a/src/mainboard/google/brya/variants/dirks/memory/Makefile.mk b/src/mainboard/google/brya/variants/dirks/memory/Makefile.mk
index 2d0d1bb0d8..67b6ac1b88 100644
--- a/src/mainboard/google/brya/variants/dirks/memory/Makefile.mk
+++ b/src/mainboard/google/brya/variants/dirks/memory/Makefile.mk
@@ -10,3 +10,5 @@ SPD_SOURCES += spd/lp5/set-0/spd-5.hex      # ID = 2(0b0010)  Parts = K3LKLKL0EM
 SPD_SOURCES += spd/lp5/set-0/spd-3.hex      # ID = 3(0b0011)  Parts = K3LKBKB0BM-MGCP
 SPD_SOURCES += spd/lp5/set-0/spd-7.hex      # ID = 4(0b0100)  Parts = K3KL8L80CM-MGCT
 SPD_SOURCES += spd/lp5/set-0/spd-11.hex      # ID = 5(0b0101)  Parts = H58G56BK8BX068
+SPD_SOURCES += spd/lp5/set-0/spd-8.hex      # ID = 6(0b0110)  Parts = K3KL9L90CM-MGCT
+SPD_SOURCES += spd/lp5/set-0/spd-10.hex      # ID = 7(0b0111)  Parts = H58G66BK8BX067
diff --git a/src/mainboard/google/brya/variants/dirks/memory/dram_id.generated.txt b/src/mainboard/google/brya/variants/dirks/memory/dram_id.generated.txt
index c10bbb76e2..059f1e69be 100644
--- a/src/mainboard/google/brya/variants/dirks/memory/dram_id.generated.txt
+++ b/src/mainboard/google/brya/variants/dirks/memory/dram_id.generated.txt
@@ -12,3 +12,5 @@ K3LKBKB0BM-MGCP                3 (0011)
 H9JCNNNCP3MLYR-N6E             0 (0000)
 K3KL8L80CM-MGCT                4 (0100)
 H58G56BK8BX068                 5 (0101)
+K3KL9L90CM-MGCT                6 (0110)
+H58G66BK8BX067                 7 (0111)
diff --git a/src/mainboard/google/brya/variants/dirks/memory/mem_parts_used.txt b/src/mainboard/google/brya/variants/dirks/memory/mem_parts_used.txt
index 2c18a19d34..61be3e79aa 100644
--- a/src/mainboard/google/brya/variants/dirks/memory/mem_parts_used.txt
+++ b/src/mainboard/google/brya/variants/dirks/memory/mem_parts_used.txt
@@ -17,3 +17,5 @@ K3LKBKB0BM-MGCP
 H9JCNNNCP3MLYR-N6E
 K3KL8L80CM-MGCT
 H58G56BK8BX068
+K3KL9L90CM-MGCT
+H58G66BK8BX067

From 3783e06c339d361067b3b82e4c83df0106255f38 Mon Sep 17 00:00:00 2001
From: Felix Held <felix-coreboot@felixheld.de>
Date: Fri, 14 Feb 2025 20:21:08 +0100
Subject: [PATCH 0139/3886] acpi/acpigen: fix typo in
 acpigen_write_if_lequal_op_op comment

Change-Id: I2e4159e1e34560dacffbb6b9e392c2d2e2ad6887
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86463
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/acpi/acpigen.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/acpi/acpigen.c b/src/acpi/acpigen.c
index 7d24b9e131..308cf5ac85 100644
--- a/src/acpi/acpigen.c
+++ b/src/acpi/acpigen.c
@@ -1586,7 +1586,7 @@ void acpigen_write_if_and(uint8_t arg1, uint8_t arg2)
  * Generates ACPI code for checking if operand1 and operand2 are equal.
  * Both operand1 and operand2 are ACPI ops.
  *
- * If (Lequal (op,1 op2))
+ * If (Lequal (op1, op2))
  */
 void acpigen_write_if_lequal_op_op(uint8_t op1, uint8_t op2)
 {

From c972e6113f053fd8fa67282b16ccccb3eecf6c6c Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Sun, 16 Feb 2025 13:08:58 -0600
Subject: [PATCH 0140/3886] mb/google/auron: Clean up Kconfig selections

Select the newly-added SYSTEM_TYPE_ALL_IN_ONE for Buddy variant, and
use that as a discriminator to de-duplicate selections for system
type and HAVE_SPD_IN_CBFS.

Change-Id: I0d28bc496ff6bcfa9947a4d15ed2d8f75cf74ac3
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86455
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
---
 src/mainboard/google/auron/Kconfig | 13 +++----------
 1 file changed, 3 insertions(+), 10 deletions(-)

diff --git a/src/mainboard/google/auron/Kconfig b/src/mainboard/google/auron/Kconfig
index 72f7758b55..2381c797d9 100644
--- a/src/mainboard/google/auron/Kconfig
+++ b/src/mainboard/google/auron/Kconfig
@@ -10,6 +10,7 @@ config BOARD_GOOGLE_BASEBOARD_AURON
 	select HAVE_ACPI_RESUME
 	select HAVE_ACPI_TABLES
 	select HAVE_OPTION_TABLE
+	select HAVE_SPD_IN_CBFS if !SYSTEM_TYPE_ALL_IN_ONE
 	select INTEL_GMA_HAVE_VBT
 	select INTEL_INT15
 	select MAINBOARD_HAS_CHROMEOS
@@ -17,34 +18,26 @@ config BOARD_GOOGLE_BASEBOARD_AURON
 	select MEMORY_MAPPED_TPM
 	select MAINBOARD_HAS_TPM1
 	select SOC_INTEL_BROADWELL
+	select SYSTEM_TYPE_LAPTOP if !SYSTEM_TYPE_ALL_IN_ONE
 
 config BOARD_GOOGLE_AURON_PAINE
 	select BOARD_GOOGLE_BASEBOARD_AURON
-	select HAVE_SPD_IN_CBFS
-	select SYSTEM_TYPE_LAPTOP
 
 config BOARD_GOOGLE_AURON_YUNA
 	select BOARD_GOOGLE_BASEBOARD_AURON
-	select HAVE_SPD_IN_CBFS
-	select SYSTEM_TYPE_LAPTOP
 
 config BOARD_GOOGLE_BUDDY
 	select BOARD_GOOGLE_BASEBOARD_AURON
+	select SYSTEM_TYPE_ALL_IN_ONE
 
 config BOARD_GOOGLE_GANDOF
 	select BOARD_GOOGLE_BASEBOARD_AURON
-	select HAVE_SPD_IN_CBFS
-	select SYSTEM_TYPE_LAPTOP
 
 config BOARD_GOOGLE_LULU
 	select BOARD_GOOGLE_BASEBOARD_AURON
-	select HAVE_SPD_IN_CBFS
-	select SYSTEM_TYPE_LAPTOP
 
 config BOARD_GOOGLE_SAMUS
 	select BOARD_GOOGLE_BASEBOARD_AURON
-	select HAVE_SPD_IN_CBFS
-	select SYSTEM_TYPE_LAPTOP
 
 if BOARD_GOOGLE_BASEBOARD_AURON
 

From d0f5fc744495a5a261ae3bf78cd1b69178073cc5 Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Sun, 16 Feb 2025 13:11:39 -0600
Subject: [PATCH 0141/3886] mb/google/beltino: Set SMBIOS system type

Beltino variants will now correctly show their SMBIOS type as an
all-in-one (monroe) or a mini-pc (all other variants) rather than the
default desktop type.

Change-Id: Ia9f17236c415b626fd5d553a453cf43d4145ef41
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86456
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/google/beltino/Kconfig | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/src/mainboard/google/beltino/Kconfig b/src/mainboard/google/beltino/Kconfig
index b3695cc383..8bde8e6d1c 100644
--- a/src/mainboard/google/beltino/Kconfig
+++ b/src/mainboard/google/beltino/Kconfig
@@ -15,12 +15,14 @@ config BOARD_GOOGLE_BASEBOARD_BELTINO
 	select NORTHBRIDGE_INTEL_HASWELL
 	select SOUTHBRIDGE_INTEL_LYNXPOINT
 	select SUPERIO_ITE_IT8772F
+	select SYSTEM_TYPE_MINIPC if !SYSTEM_TYPE_ALL_IN_ONE
 
 config BOARD_GOOGLE_MCCLOUD
 	select BOARD_GOOGLE_BASEBOARD_BELTINO
 
 config BOARD_GOOGLE_MONROE
 	select BOARD_GOOGLE_BASEBOARD_BELTINO
+	select SYSTEM_TYPE_ALL_IN_ONE
 
 config BOARD_GOOGLE_PANTHER
 	select BOARD_GOOGLE_BASEBOARD_BELTINO

From de964a7de360671ecb0e5d99338d51f1e27852c6 Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Sun, 16 Feb 2025 15:09:16 -0600
Subject: [PATCH 0142/3886] mb/google/cyan: Set SYSTEM_TYPE_CONVERTIBLE for
 cyan/kefka

Cyan and Kefka are convertible devices, so set them as such so their
SMBIOS type is set correctly, necessary for some Linux tablet drivers.

Change-Id: Ief81c7ba83eb5326dd6199508a3194008dee243b
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86457
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/google/cyan/Kconfig | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/src/mainboard/google/cyan/Kconfig b/src/mainboard/google/cyan/Kconfig
index 2bb6b9238c..eacc8ef87d 100644
--- a/src/mainboard/google/cyan/Kconfig
+++ b/src/mainboard/google/cyan/Kconfig
@@ -29,12 +29,14 @@ config BOARD_GOOGLE_CELES
 
 config BOARD_GOOGLE_CYAN
 	select BOARD_GOOGLE_BASEBOARD_CYAN
+	select SYSTEM_TYPE_CONVERTIBLE
 
 config BOARD_GOOGLE_EDGAR
 	select BOARD_GOOGLE_BASEBOARD_CYAN
 
 config BOARD_GOOGLE_KEFKA
 	select BOARD_GOOGLE_BASEBOARD_CYAN
+	select SYSTEM_TYPE_CONVERTIBLE
 
 config BOARD_GOOGLE_REKS
 	select BOARD_GOOGLE_BASEBOARD_CYAN

From 2974781987e83dee014bcc3a02c9099bbe6da8aa Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Sun, 16 Feb 2025 15:12:00 -0600
Subject: [PATCH 0143/3886] mb/google/fizz: Set SMBIOS system type

Fizz variants will now correctly show their SMBIOS type as an
all-in-one (karma) or a mini-pc (all other variants) rather than the
default desktop type.

Change-Id: Ida61c68d3664115ca29cb11e6820edb1496e4709
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86458
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/google/fizz/Kconfig | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/src/mainboard/google/fizz/Kconfig b/src/mainboard/google/fizz/Kconfig
index 44ea908fda..84a514566e 100644
--- a/src/mainboard/google/fizz/Kconfig
+++ b/src/mainboard/google/fizz/Kconfig
@@ -24,6 +24,7 @@ config BOARD_GOOGLE_BASEBOARD_FIZZ
 	select RT8168_GET_MAC_FROM_VPD
 	select RT8168_SUPPORT_LEGACY_VPD_MAC
 	select RT8168_SET_LED_MODE
+	select SYSTEM_TYPE_MINIPC if !SYSTEM_TYPE_ALL_IN_ONE
 	select TPM_GOOGLE_CR50
 
 config BOARD_GOOGLE_FIZZ
@@ -34,6 +35,7 @@ config BOARD_GOOGLE_KARMA
 	select DRIVERS_GENERIC_MAX98357A
 	select DRIVERS_I2C_DA7219
 	select EXCLUDE_NATIVE_SD_INTERFACE
+	select SYSTEM_TYPE_ALL_IN_ONE
 
 config BOARD_GOOGLE_ENDEAVOUR
 	select BOARD_GOOGLE_BASEBOARD_FIZZ

From a06faf96873ad1005010ef44d65b3fbbc0546b77 Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Sun, 16 Feb 2025 15:14:04 -0600
Subject: [PATCH 0144/3886] mb/google/jecht: Set SMBIOS system type

Jecht variants will now correctly show their SMBIOS type as mini-pc
rather than the default desktop type.

Change-Id: I4f1be147bcfdad6247101db5b5943301466e60ad
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86459
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
---
 src/mainboard/google/jecht/Kconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/src/mainboard/google/jecht/Kconfig b/src/mainboard/google/jecht/Kconfig
index c8cf7d61ca..eb3b985e5a 100644
--- a/src/mainboard/google/jecht/Kconfig
+++ b/src/mainboard/google/jecht/Kconfig
@@ -13,6 +13,7 @@ config BOARD_GOOGLE_BASEBOARD_JECHT
 	select MAINBOARD_HAS_TPM1
 	select SOC_INTEL_BROADWELL
 	select SUPERIO_ITE_IT8772F
+	select SYSTEM_TYPE_MINIPC
 
 config BOARD_GOOGLE_GUADO
 	select BOARD_GOOGLE_BASEBOARD_JECHT

From 77d50109bbb54076b4dfbf9aa8badda79d051c66 Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Sun, 16 Feb 2025 15:21:52 -0600
Subject: [PATCH 0145/3886] mb/google/puff: Set SMBIOS system type

Puff variants will now correctly show their SMBIOS type as an
all-in-one (dooly, scout) or a mini-pc (all other variants) rather than
the default desktop type.

Change-Id: Id24ff40f0aacade359f281def8be2a41c752d0d6
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86460
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
---
 src/mainboard/google/puff/Kconfig | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/src/mainboard/google/puff/Kconfig b/src/mainboard/google/puff/Kconfig
index 0abe53a10e..3e64f05388 100644
--- a/src/mainboard/google/puff/Kconfig
+++ b/src/mainboard/google/puff/Kconfig
@@ -35,6 +35,7 @@ config BOARD_GOOGLE_BASEBOARD_PUFF
 	select SPD_CACHE_IN_FMAP
 	select SPD_READ_BY_WORD
 	select SPI_TPM
+	select SYSTEM_TYPE_MINIPC if !SYSTEM_TYPE_ALL_IN_ONE
 	select TPM_GOOGLE_CR50
 
 config BOARD_GOOGLE_AMBASSADOR
@@ -44,6 +45,7 @@ config BOARD_GOOGLE_AMBASSADOR
 config BOARD_GOOGLE_DOOLY
 	select BOARD_GOOGLE_BASEBOARD_PUFF
 	select INTEL_GMA_HAVE_VBT
+	select SYSTEM_TYPE_ALL_IN_ONE
 
 config BOARD_GOOGLE_DUFFY_LEGACY
 	select BOARD_GOOGLE_BASEBOARD_PUFF
@@ -85,6 +87,7 @@ config BOARD_GOOGLE_PUFF
 
 config BOARD_GOOGLE_SCOUT
 	select BOARD_GOOGLE_BASEBOARD_PUFF
+	select SYSTEM_TYPE_ALL_IN_ONE
 
 config BOARD_GOOGLE_WYVERN
 	select BOARD_GOOGLE_BASEBOARD_PUFF

From ab24ddbb49c4c63125121acaa0304587f88065c2 Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Sun, 16 Feb 2025 15:22:59 -0600
Subject: [PATCH 0146/3886] mb/google/puff: Add missing device names to
 Kconfig.name

Taken from:
https://dl.google.com/dl/edgedl/chromeos/recovery/recovery2.json
https://dl.google.com/dl/edgedl/chromeos/recovery/workspaceHardware_recovery2.json

Change-Id: I1da5c129c3912b4158bdc5349eb038265f80bf85
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86461
Reviewed-by: Andy Ebrahiem <ahmet.ebrahiem@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
---
 src/mainboard/google/puff/Kconfig.name | 10 +++++-----
 1 file changed, 5 insertions(+), 5 deletions(-)

diff --git a/src/mainboard/google/puff/Kconfig.name b/src/mainboard/google/puff/Kconfig.name
index fe35e0697b..fa5b0f5ee6 100644
--- a/src/mainboard/google/puff/Kconfig.name
+++ b/src/mainboard/google/puff/Kconfig.name
@@ -3,10 +3,10 @@
 comment "Puff"
 
 config BOARD_GOOGLE_AMBASSADOR
-	bool "->  Ambassador"
+	bool "->  Ambassador (Meet Compute System [Intel 10th Gen])"
 
 config BOARD_GOOGLE_DOOLY
-	bool "->  Dooly"
+	bool "->  Dooly (HP Chromebase 21.5)"
 
 config BOARD_GOOGLE_DUFFY_LEGACY
 	bool "->  Duffy Legacy (32MB)"
@@ -18,7 +18,7 @@ config BOARD_GOOGLE_FAFFY
 	bool "->  Faffy (ASUS Fanless Chromebox)"
 
 config BOARD_GOOGLE_GENESIS
-	bool "->  Genesis"
+	bool "->  Genesis (Meet Compute System - Series One [Intel 10th Gen])"
 
 config BOARD_GOOGLE_KAISA_LEGACY
 	bool "->  Kaisa Legacy (32MB)"
@@ -27,7 +27,7 @@ config BOARD_GOOGLE_KAISA
 	bool "->  Kaisa (Acer Chromebox CXI4)"
 
 config BOARD_GOOGLE_MOONBUGGY
-	bool "->  Moonbuggy"
+	bool "->  Moonbuggy (Series One Board 65)"
 
 config BOARD_GOOGLE_NOIBAT
 	bool "->  Noibat (HP Chromebox G3)"
@@ -36,7 +36,7 @@ config BOARD_GOOGLE_PUFF
 	bool "->  Puff"
 
 config BOARD_GOOGLE_SCOUT
-	bool "->  Scout"
+	bool "->  Scout (Series One Desk 27)"
 
 config BOARD_GOOGLE_WYVERN
 	bool "->  Wyvern (CTL Chromebox CBx2)"

From 3e062c82709ba28a95c33640a70d916c6c23086b Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Sun, 16 Feb 2025 15:26:40 -0600
Subject: [PATCH 0147/3886] mb/google/rambi: Set system type for ninja/sumo
 variants

Set these to minipc and all-in-one respectively now that these
system types exist, so that the SMBIOS enclosure type is correctly
set vs defaulting to desktop.

Change-Id: I661401dcd7fe348a07e34ace309c0a8b7e0f00eb
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86462
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
---
 src/mainboard/google/rambi/Kconfig | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/src/mainboard/google/rambi/Kconfig b/src/mainboard/google/rambi/Kconfig
index 65339e02e4..750eba1e30 100644
--- a/src/mainboard/google/rambi/Kconfig
+++ b/src/mainboard/google/rambi/Kconfig
@@ -63,6 +63,7 @@ config BOARD_GOOGLE_KIP
 config BOARD_GOOGLE_NINJA
 	select BOARD_GOOGLE_BASEBOARD_RAMBI
 	select INTEL_GMA_HAVE_VBT
+	select SYSTEM_TYPE_MINIPC
 
 config BOARD_GOOGLE_ORCO
 	select BOARD_GOOGLE_BASEBOARD_RAMBI
@@ -86,6 +87,7 @@ config BOARD_GOOGLE_RAMBI
 config BOARD_GOOGLE_SUMO
 	select BOARD_GOOGLE_BASEBOARD_RAMBI
 	select INTEL_GMA_HAVE_VBT
+	select SYSTEM_TYPE_ALL_IN_ONE
 
 config BOARD_GOOGLE_SWANKY
 	select BOARD_GOOGLE_BASEBOARD_RAMBI

From 2320593a3ba51a6caa7af0afdb261db77aa75b5b Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Sun, 16 Feb 2025 18:07:34 -0600
Subject: [PATCH 0148/3886] mb/google/glados/var/cave: Set
 SYSTEM_TYPE_CONVERTIBLE

Cave is a 2-in-1 device, this sets the SMBIOS enclosure type properly.

Change-Id: I8f2ec82c97676aa315c18286b5e2eb94d46004ec
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86467
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Reviewed-by: Andy Ebrahiem <ahmet.ebrahiem@9elements.com>
---
 src/mainboard/google/glados/Kconfig | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/src/mainboard/google/glados/Kconfig b/src/mainboard/google/glados/Kconfig
index 57d54d0be8..287d938341 100644
--- a/src/mainboard/google/glados/Kconfig
+++ b/src/mainboard/google/glados/Kconfig
@@ -20,7 +20,7 @@ config BOARD_GOOGLE_BASEBOARD_GLADOS
 	select MEMORY_MAPPED_TPM
 	select MAINBOARD_HAS_TPM1
 	select SOC_INTEL_SKYLAKE
-	select SYSTEM_TYPE_LAPTOP
+	select SYSTEM_TYPE_LAPTOP if !SYSTEM_TYPE_CONVERTIBLE
 
 config BOARD_GOOGLE_ASUKA
 	select BOARD_GOOGLE_BASEBOARD_GLADOS
@@ -43,6 +43,7 @@ config BOARD_GOOGLE_CAVE
 	select INTEL_GMA_HAVE_VBT
 	select MAINBOARD_NO_FSP_GOP
 	select NHLT_MAX98357 if INCLUDE_NHLT_BLOBS
+	select SYSTEM_TYPE_CONVERTIBLE
 
 config BOARD_GOOGLE_CHELL
 	select BOARD_GOOGLE_BASEBOARD_GLADOS

From c5a0beed9a456cb32302a36e757c54a86ccced5f Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Sun, 16 Feb 2025 18:09:38 -0600
Subject: [PATCH 0149/3886] mb/google/skyrim/var/frostflow: Set
 SYSTEM_TYPE_CONVERTIBLE

Frostflow is a 2-in-1 device, this sets the SMBIOS enclosure type
properly.

Change-Id: I6c3306270cbc80bb55fb536a1fc51a5546287649
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86468
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
---
 src/mainboard/google/skyrim/Kconfig | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/src/mainboard/google/skyrim/Kconfig b/src/mainboard/google/skyrim/Kconfig
index dc28fbca72..756db5f69a 100644
--- a/src/mainboard/google/skyrim/Kconfig
+++ b/src/mainboard/google/skyrim/Kconfig
@@ -11,6 +11,7 @@ config BOARD_GOOGLE_FROSTFLOW
 	select DRIVERS_GENESYSLOGIC_GL9755
 	select FEATURE_TABLET_MODE_DPTC
 	select SOC_AMD_COMMON_BLOCK_ACPI_DPTC
+	select SYSTEM_TYPE_CONVERTIBLE
 
 config BOARD_GOOGLE_MARKARTH
 	select BOARD_GOOGLE_BASEBOARD_SKYRIM
@@ -67,7 +68,7 @@ config BOARD_SPECIFIC_OPTIONS
 	select SOC_AMD_COMMON_BLOCK_I2C3_TPM_SHARED_WITH_PSP
 	select SOC_AMD_COMMON_BLOCK_USE_ESPI
 	select SOC_AMD_GFX_CACHE_VBIOS_IN_FMAP if CHROMEOS && RUN_FSP_GOP
-	select SYSTEM_TYPE_LAPTOP
+	select SYSTEM_TYPE_LAPTOP if !SYSTEM_TYPE_CONVERTIBLE
 	select TPM_GOOGLE_TI50
 
 config DEVICETREE

From 61b99e9527ff836d62e5765c6df81893ba6573c9 Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Tue, 18 Feb 2025 11:19:17 +0000
Subject: [PATCH 0150/3886] mb/starlabs/starbook/mtl: Correct HDMI HPD GPIO
 config

This GPIO should be NF2, not NF1.

Change-Id: I012acfa43ada5641b37f38892a1e3bfbc6e74843
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86495
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
---
 src/mainboard/starlabs/starbook/variants/mtl/gpio.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/mainboard/starlabs/starbook/variants/mtl/gpio.c b/src/mainboard/starlabs/starbook/variants/mtl/gpio.c
index e64baa3a9a..f95109418f 100644
--- a/src/mainboard/starlabs/starbook/variants/mtl/gpio.c
+++ b/src/mainboard/starlabs/starbook/variants/mtl/gpio.c
@@ -428,7 +428,7 @@ const struct pad_config gpio_table[] = {
 	/* B15:					*/
 	PAD_NC(GPP_B15, NONE),
 	/* B16:	DDIB_DP_HPD			*/
-	PAD_CFG_NF(GPP_B16, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_B16, NONE, DEEP, NF2),
 	/* B17:					*/
 	PAD_NC(GPP_B17, NONE),
 	/* B18:	BT_RF_KILL_N			*/

From 1f2bb567af019be6490a4399e0ca75364e31920f Mon Sep 17 00:00:00 2001
From: Rui Zhou <zhourui@huaqin.corp-partner.google.com>
Date: Mon, 17 Feb 2025 17:06:18 +0800
Subject: [PATCH 0151/3886] mb/google/nissa/var/rull: Adjust SSD power
 sequencing to give the SSD more preparation time

Improve SSD reset time by enabling earlier sequencing, save 230ms

BUG=b:397098950
TEST=build and boot normal using NVMe

Change-Id: I2e48a6614e8bded36d03138869b0eba7e1acb567
Signed-off-by: Rui Zhou <zhourui@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86483
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
---
 src/mainboard/google/brya/variants/rull/gpio.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/src/mainboard/google/brya/variants/rull/gpio.c b/src/mainboard/google/brya/variants/rull/gpio.c
index 81bd2800b1..24096d73bc 100644
--- a/src/mainboard/google/brya/variants/rull/gpio.c
+++ b/src/mainboard/google/brya/variants/rull/gpio.c
@@ -141,6 +141,8 @@ static const struct pad_config early_gpio_table[] = {
 };
 
 static const struct pad_config romstage_gpio_table[] = {
+	/* B4  : SSD_PERST_L */
+	PAD_CFG_GPO(GPP_B4, 1, DEEP),
 };
 
 const struct pad_config *variant_gpio_override_table(size_t *num)

From 71b62486022073a7e129baaa7546a516bbc197a3 Mon Sep 17 00:00:00 2001
From: John Su <john_su@compal.corp-partner.google.com>
Date: Fri, 7 Feb 2025 00:26:33 +0800
Subject: [PATCH 0152/3886] mb/google/trulo/var/uldrenite: Add FW_CONFIG probe
 for fivr

Uldrenite will support internal fivr in next phase and using fw_config
to decide the board with internal or external fivr.

BUG=b:394752422
BRANCH=firmware-trulo-15217.771.B
TEST=boot to ChromeOS, cold reboot/suspend/recovery mode/install OS
work normally

Change-Id: I14233090f2445461cf422c1257f21556fd745b43
Signed-off-by: John Su <john_su@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86303
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 .../brya/variants/uldrenite/overridetree.cb   | 19 ++++-----------
 .../google/brya/variants/uldrenite/variant.c  | 24 +++++++++++++++++++
 2 files changed, 28 insertions(+), 15 deletions(-)

diff --git a/src/mainboard/google/brya/variants/uldrenite/overridetree.cb b/src/mainboard/google/brya/variants/uldrenite/overridetree.cb
index dd129d7b9e..fdc933eb3b 100644
--- a/src/mainboard/google/brya/variants/uldrenite/overridetree.cb
+++ b/src/mainboard/google/brya/variants/uldrenite/overridetree.cb
@@ -3,6 +3,10 @@ fw_config
 		option CELLULAR_ABSENT		0
 		option CELLULAR_RW350R		1
 	end
+	field EXT_VR 3 3
+		option EXT_VR_PRESENT		0
+		option EXT_VR_ABSENT		1
+	end
 	field TOUCHSCREEN 4 4
 		option TOUCHSCREEN_UNKNOWN	0
 		option TOUCHSCREEN_NONE		1
@@ -100,21 +104,6 @@ chip soc/intel/alderlake
 	register "pch_hda_idisp_link_frequency" = "HDA_LINKFREQ_96MHZ"
 	register "pch_hda_idisp_codec_enable" = "1"
 
-	# Configure external V1P05/Vnn/VnnSx Rails
-	register "ext_fivr_settings" = "{
-		.configure_ext_fivr = 1,
-		.v1p05_enable_bitmap = FIVR_ENABLE_ALL_SX & ~FIVR_ENABLE_S0,
-		.vnn_enable_bitmap = FIVR_ENABLE_ALL_SX,
-		.vnn_sx_enable_bitmap = FIVR_ENABLE_ALL_SX,
-		.v1p05_supported_voltage_bitmap = FIVR_VOLTAGE_NORMAL,
-		.vnn_supported_voltage_bitmap = FIVR_VOLTAGE_MIN_ACTIVE,
-		.v1p05_voltage_mv = 1050,
-		.vnn_voltage_mv = 780,
-		.vnn_sx_voltage_mv = 1050,
-		.v1p05_icc_max_ma = 500,
-		.vnn_icc_max_ma = 500,
-	}"
-
 	register "serial_io_i2c_mode" = "{
 		[PchSerialIoIndexI2C0] = PchSerialIoPci,
 		[PchSerialIoIndexI2C1] = PchSerialIoPci,
diff --git a/src/mainboard/google/brya/variants/uldrenite/variant.c b/src/mainboard/google/brya/variants/uldrenite/variant.c
index 41ab7b8c14..3620c3a0c8 100644
--- a/src/mainboard/google/brya/variants/uldrenite/variant.c
+++ b/src/mainboard/google/brya/variants/uldrenite/variant.c
@@ -83,3 +83,27 @@ void variant_init(void)
 	mdelay(RW350R_PERST_DELAY_MS);
 	gpio_configure_pads(rw350r_perst_pad, ARRAY_SIZE(rw350r_perst_pad));
 }
+
+void variant_update_soc_chip_config(struct soc_intel_alderlake_config *config)
+{
+	if (fw_config_probe(FW_CONFIG(EXT_VR, EXT_VR_PRESENT))) {
+		/* # Configure external V1P05/Vnn/VnnSx Rails */
+		config->ext_fivr_settings.configure_ext_fivr = 1;
+		config->ext_fivr_settings.v1p05_enable_bitmap =
+				FIVR_ENABLE_ALL_SX & ~FIVR_ENABLE_S0;
+		config->ext_fivr_settings.vnn_enable_bitmap =
+				FIVR_ENABLE_ALL_SX;
+		config->ext_fivr_settings.vnn_sx_enable_bitmap =
+				FIVR_ENABLE_ALL_SX;
+		config->ext_fivr_settings.v1p05_supported_voltage_bitmap =
+				FIVR_VOLTAGE_NORMAL;
+		config->ext_fivr_settings.vnn_supported_voltage_bitmap =
+				FIVR_VOLTAGE_MIN_ACTIVE;
+		config->ext_fivr_settings.v1p05_voltage_mv = 1050;
+		config->ext_fivr_settings.vnn_voltage_mv = 780;
+		config->ext_fivr_settings.vnn_sx_voltage_mv = 1050;
+		config->ext_fivr_settings.v1p05_icc_max_ma = 500;
+		config->ext_fivr_settings.vnn_icc_max_ma = 500;
+		printk(BIOS_INFO, "Configured External FIVR\n");
+	}
+}

From adc53a8837e6872d25fec9da98b6bb7b359eefe1 Mon Sep 17 00:00:00 2001
From: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com>
Date: Fri, 7 Feb 2025 17:01:04 +0900
Subject: [PATCH 0153/3886] mb/google/nissa: Create meliks variant

Create the meliks variant of the nissa reference board by copying
the template files to a new directory named for the variant.

(Auto-Generated by create_coreboot_variant.sh version 4.5.0)

BUG=b:394359785
BRANCH=None
TEST=util/abuild/abuild -p none -t google/brya -x -a
make sure the build includes GOOGLE_MELIKS

Change-Id: Iff5e27ef06a44976c2724751de0f9c6d5cf6eaaf
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86373
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/google/brya/Kconfig                     | 10 ++++++++++
 src/mainboard/google/brya/Kconfig.name                |  3 +++
 .../google/brya/variants/meliks/include/variant/ec.h  |  8 ++++++++
 .../brya/variants/meliks/include/variant/gpio.h       |  8 ++++++++
 .../google/brya/variants/meliks/memory/Makefile.mk    |  5 +++++
 .../brya/variants/meliks/memory/dram_id.generated.txt |  1 +
 .../brya/variants/meliks/memory/mem_parts_used.txt    | 11 +++++++++++
 .../google/brya/variants/meliks/overridetree.cb       |  6 ++++++
 8 files changed, 52 insertions(+)
 create mode 100644 src/mainboard/google/brya/variants/meliks/include/variant/ec.h
 create mode 100644 src/mainboard/google/brya/variants/meliks/include/variant/gpio.h
 create mode 100644 src/mainboard/google/brya/variants/meliks/memory/Makefile.mk
 create mode 100644 src/mainboard/google/brya/variants/meliks/memory/dram_id.generated.txt
 create mode 100644 src/mainboard/google/brya/variants/meliks/memory/mem_parts_used.txt
 create mode 100644 src/mainboard/google/brya/variants/meliks/overridetree.cb

diff --git a/src/mainboard/google/brya/Kconfig b/src/mainboard/google/brya/Kconfig
index 0f1c3c50e6..fd88c1b9f9 100644
--- a/src/mainboard/google/brya/Kconfig
+++ b/src/mainboard/google/brya/Kconfig
@@ -351,6 +351,12 @@ config BOARD_GOOGLE_MARASOV
 	select SOC_INTEL_RAPTORLAKE
 	select USE_UNIFIED_AP_FIRMWARE_FOR_UFS_AND_NON_UFS
 
+config BOARD_GOOGLE_MELIKS
+	select BOARD_GOOGLE_BASEBOARD_NISSA
+	select DRIVERS_I2C_DA7219
+	select DRIVERS_INTEL_MIPI_CAMERA
+	select SOC_INTEL_TWINLAKE
+
 config BOARD_GOOGLE_MITHRAX
 	select BOARD_GOOGLE_BASEBOARD_BRYA
 	select CHROMEOS_WIFI_SAR if CHROMEOS
@@ -826,6 +832,7 @@ config DRIVER_TPM_I2C_BUS
 	default 0x1 if BOARD_GOOGLE_ZYDRON
 	default 0x0 if BOARD_GOOGLE_TELITH
 	default 0x0 if BOARD_GOOGLE_PUJJOGATWIN
+	default 0x0 if BOARD_GOOGLE_MELIKS
 
 config DRIVER_TPM_I2C_ADDR
 	hex
@@ -909,6 +916,7 @@ config TPM_TIS_ACPI_INTERRUPT
 	default 13 if BOARD_GOOGLE_ZYDRON
 	default 13 if BOARD_GOOGLE_TELITH
 	default 13 if BOARD_GOOGLE_PUJJOGATWIN
+	default 13 if BOARD_GOOGLE_MELIKS
 
 config OVERRIDE_DEVICETREE
 	default "variants/\$(CONFIG_VARIANT_DIR)/overridetree_pujjogatwin.cb" if BOARD_GOOGLE_PUJJOGATWIN
@@ -1000,6 +1008,7 @@ config MAINBOARD_PART_NUMBER
 	default "Pujjoga" if BOARD_GOOGLE_PUJJOGA
 	default "Telith" if BOARD_GOOGLE_TELITH
 	default "Pujjogatwin" if BOARD_GOOGLE_PUJJOGATWIN
+	default "Meliks" if BOARD_GOOGLE_MELIKS
 
 config VARIANT_DIR
 	default "agah" if BOARD_GOOGLE_AGAH
@@ -1076,6 +1085,7 @@ config VARIANT_DIR
 	default "pujjoga" if BOARD_GOOGLE_PUJJOGA
 	default "telith" if BOARD_GOOGLE_TELITH
 	default "pujjoga" if BOARD_GOOGLE_PUJJOGATWIN
+	default "meliks" if BOARD_GOOGLE_MELIKS
 
 config VBOOT
 	select VBOOT_EARLY_EC_SYNC if !(BOARD_GOOGLE_BASEBOARD_NISSA || BOARD_GOOGLE_BASEBOARD_TRULO)
diff --git a/src/mainboard/google/brya/Kconfig.name b/src/mainboard/google/brya/Kconfig.name
index db99d326f3..ac4c262d78 100644
--- a/src/mainboard/google/brya/Kconfig.name
+++ b/src/mainboard/google/brya/Kconfig.name
@@ -223,3 +223,6 @@ config BOARD_GOOGLE_ORISA
 
 config BOARD_GOOGLE_TELITH
 	bool "->  Telith"
+
+config BOARD_GOOGLE_MELIKS
+	bool "->  Meliks"
diff --git a/src/mainboard/google/brya/variants/meliks/include/variant/ec.h b/src/mainboard/google/brya/variants/meliks/include/variant/ec.h
new file mode 100644
index 0000000000..7a2a6ff8b7
--- /dev/null
+++ b/src/mainboard/google/brya/variants/meliks/include/variant/ec.h
@@ -0,0 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#ifndef __VARIANT_EC_H__
+#define __VARIANT_EC_H__
+
+#include <baseboard/ec.h>
+
+#endif
diff --git a/src/mainboard/google/brya/variants/meliks/include/variant/gpio.h b/src/mainboard/google/brya/variants/meliks/include/variant/gpio.h
new file mode 100644
index 0000000000..c4fe342621
--- /dev/null
+++ b/src/mainboard/google/brya/variants/meliks/include/variant/gpio.h
@@ -0,0 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#ifndef VARIANT_GPIO_H
+#define VARIANT_GPIO_H
+
+#include <baseboard/gpio.h>
+
+#endif
diff --git a/src/mainboard/google/brya/variants/meliks/memory/Makefile.mk b/src/mainboard/google/brya/variants/meliks/memory/Makefile.mk
new file mode 100644
index 0000000000..eace2e443e
--- /dev/null
+++ b/src/mainboard/google/brya/variants/meliks/memory/Makefile.mk
@@ -0,0 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+# This is an auto-generated file. Do not edit!!
+# Add memory parts in mem_parts_used.txt and run spd_tools to regenerate.
+
+SPD_SOURCES = placeholder
diff --git a/src/mainboard/google/brya/variants/meliks/memory/dram_id.generated.txt b/src/mainboard/google/brya/variants/meliks/memory/dram_id.generated.txt
new file mode 100644
index 0000000000..fa247902ee
--- /dev/null
+++ b/src/mainboard/google/brya/variants/meliks/memory/dram_id.generated.txt
@@ -0,0 +1 @@
+DRAM Part Name                 ID to assign
diff --git a/src/mainboard/google/brya/variants/meliks/memory/mem_parts_used.txt b/src/mainboard/google/brya/variants/meliks/memory/mem_parts_used.txt
new file mode 100644
index 0000000000..2499005682
--- /dev/null
+++ b/src/mainboard/google/brya/variants/meliks/memory/mem_parts_used.txt
@@ -0,0 +1,11 @@
+# This is a CSV file containing a list of memory parts used by this variant.
+# One part per line with an optional fixed ID in column 2.
+# Only include a fixed ID if it is required for legacy reasons!
+# Generated IDs are dependent on the order of parts in this file,
+# so new parts must always be added at the end of the file!
+#
+# Generate an updated Makefile.mk and dram_id.generated.txt by running the
+# part_id_gen tool from util/spd_tools.
+# See util/spd_tools/README.md for more details and instructions.
+
+# Part Name
diff --git a/src/mainboard/google/brya/variants/meliks/overridetree.cb b/src/mainboard/google/brya/variants/meliks/overridetree.cb
new file mode 100644
index 0000000000..4f2c04a57a
--- /dev/null
+++ b/src/mainboard/google/brya/variants/meliks/overridetree.cb
@@ -0,0 +1,6 @@
+chip soc/intel/alderlake
+
+        device domain 0 on
+        end
+
+end

From 804d2c8306947cbb90ec44f302231a3e35bb86cb Mon Sep 17 00:00:00 2001
From: John Su <john_su@compal.corp-partner.google.com>
Date: Wed, 19 Feb 2025 01:58:12 +0800
Subject: [PATCH 0154/3886] mb/trulo/var/uldrenite: Decrease ROM size to 16MB

According to the design, the SPI ROM will be replaced
with a 16MB size, so the Kconfig is modified to 16MB.

BUG=b:397372760
TEST=emerge-nissa coreboot and check rom size is 16MB

Change-Id: I3ef1aa2401d44259e4301f65e2ba0ac7b9418bbd
Signed-off-by: John Su <john_su@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86501
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/google/brya/Kconfig | 1 -
 1 file changed, 1 deletion(-)

diff --git a/src/mainboard/google/brya/Kconfig b/src/mainboard/google/brya/Kconfig
index fd88c1b9f9..aac2393017 100644
--- a/src/mainboard/google/brya/Kconfig
+++ b/src/mainboard/google/brya/Kconfig
@@ -656,7 +656,6 @@ config BOARD_GOOGLE_ULDREN
 
 config BOARD_GOOGLE_ULDRENITE
 	select BOARD_GOOGLE_BASEBOARD_TRULO
-	select BOARD_ROMSIZE_KB_32768
 	select CHROMEOS_WIFI_SAR if CHROMEOS
 	select DRIVERS_WWAN_FM350GL
 	select ENFORCE_MEM_CHANNEL_DISABLE

From a0d0327685b47ea74e77afb2d13465c04629b055 Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Wed, 19 Feb 2025 19:45:24 +0000
Subject: [PATCH 0155/3886] mb/starlabs/starbook/{kbl,cml}: Unselect LIBGFXINIT

Unselect LIBGFXINIT to bring these two variants inline with the
others.

Change-Id: If0fdc9ffd391f2710f252be7358d87644a77b36a
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86515
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
---
 src/mainboard/starlabs/starbook/Kconfig | 2 --
 1 file changed, 2 deletions(-)

diff --git a/src/mainboard/starlabs/starbook/Kconfig b/src/mainboard/starlabs/starbook/Kconfig
index 1565f88290..e4e4c63c9f 100644
--- a/src/mainboard/starlabs/starbook/Kconfig
+++ b/src/mainboard/starlabs/starbook/Kconfig
@@ -24,7 +24,6 @@ config BOARD_STARLABS_LABTOP_KBL
 	select CRB_TPM
 	select HAVE_INTEL_PTT
 	select HAVE_SPD_IN_CBFS
-	select MAINBOARD_HAS_LIBGFXINIT
 	select SOC_INTEL_KABYLAKE
 	select SPI_FLASH_GIGADEVICE
 	select TPM2
@@ -41,7 +40,6 @@ config BOARD_STARLABS_LABTOP_CML
 	select HAVE_INTEL_PTT
 	select HAVE_SPD_IN_CBFS
 	select CRB_TPM
-	select MAINBOARD_HAS_LIBGFXINIT
 	select SOC_INTEL_COMETLAKE_1
 	select SPI_FLASH_WINBOND
 	select TPM2

From 0438858b2122d567b3e197561c80722878ba34ab Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Mon, 10 Feb 2025 16:20:52 +0000
Subject: [PATCH 0156/3886] mb/starlabs/starbook_adl_n: Fix USB port
 assignments/descriptions

Fix USB port assignments/descriptions to match actual topology.

TEST=build/boot Win11 on starlabs/starbook_adl_n. Verify ports
match assignmented in devicetree using USBTreeview.

Change-Id: If0b341f1c5f99b53df8fff69f8a58fa732adbbc4
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86346
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
---
 .../starbook/variants/adl_n/devicetree.cb     | 43 +++++--------------
 1 file changed, 11 insertions(+), 32 deletions(-)

diff --git a/src/mainboard/starlabs/starbook/variants/adl_n/devicetree.cb b/src/mainboard/starlabs/starbook/variants/adl_n/devicetree.cb
index d84c243767..2c66936923 100644
--- a/src/mainboard/starlabs/starbook/variants/adl_n/devicetree.cb
+++ b/src/mainboard/starlabs/starbook/variants/adl_n/devicetree.cb
@@ -37,23 +37,19 @@ chip soc/intel/alderlake
 				[DDI_PORT_1]				= DDI_ENABLE_HPD,
 			}"
 		end
-		device ref gna		on  end
-		device ref xhci		on
+		device ref gna	on  end
+		device ref xhci on
 			# Motherboard USB 3.0 Type-C Front	9557 mil
-			register "usb2_ports[1]"		= "USB2_PORT_TYPE_C(OC_SKIP)"
-			register "usb3_ports[2]"		= "USB3_PORT_DEFAULT(OC_SKIP)"
-
-			# Motherboard USB 3.0 Type-C Back	7893 mil
 			register "usb2_ports[2]"		= "USB2_PORT_TYPE_C(OC_SKIP)"
-			register "usb3_ports[3]"		= "USB3_PORT_DEFAULT(OC_SKIP)"
+			register "usb3_ports[2]"		= "USB3_PORT_DEFAULT(OC_SKIP)"
 
 			# Motherboard USB 3.0 Type-A		8916 mil
 			register "usb2_ports[6]"		= "USB2_PORT_MID(OC_SKIP)"
-			register "usb3_ports[0]"		= "USB3_PORT_DEFAULT(OC_SKIP)"
+			register "usb3_ports[1]"		= "USB3_PORT_DEFAULT(OC_SKIP)"
 
 			# Daughterboard USB 3.0 Type-A		2229 mil
 			register "usb2_ports[0]"		= "USB2_PORT_SHORT(OC_SKIP)"
-			register "usb3_ports[1]"		= "USB3_PORT_DEFAULT(OC_SKIP)"
+			register "usb3_ports[0]"		= "USB3_PORT_DEFAULT(OC_SKIP)"
 
 			# Internal Webcam			9070 mil
 			register "usb2_ports[CONFIG_CCD_PORT]"	= "USB2_PORT_MID(OC_SKIP)"
@@ -66,18 +62,6 @@ chip soc/intel/alderlake
 
 			chip drivers/usb/acpi
 				device ref xhci_root_hub on
-					chip drivers/usb/acpi
-						register "desc"		= ""Back USB Type-C""
-						register "type"		= "UPC_TYPE_C_USB2_SS"
-						register "group"	= "ACPI_PLD_GROUP(0, 0)"
-						device ref usb2_port2 on end
-					end
-					chip drivers/usb/acpi
-						register "desc"		= ""Back USB Type-C""
-						register "type"		= "UPC_TYPE_C_USB2_SS"
-						register "group"	= "ACPI_PLD_GROUP(0, 0)"
-						device ref usb3_port3 on end
-					end
 					chip drivers/usb/acpi
 						register "desc"		= ""Front USB Type-C""
 						register "type"		= "UPC_TYPE_C_USB2_SS_SWITCH"
@@ -88,7 +72,7 @@ chip soc/intel/alderlake
 						register "desc"		= ""Front USB Type-C""
 						register "type"		= "UPC_TYPE_C_USB2_SS_SWITCH"
 						register "group"	= "ACPI_PLD_GROUP(0, 1)"
-						device ref usb3_port4 on end
+						device ref usb3_port3 on end
 					end
 					chip drivers/usb/acpi
 						register "desc"		= ""Left USB Type-A""
@@ -100,7 +84,7 @@ chip soc/intel/alderlake
 						register "desc"		= ""Left USB Type-A""
 						register "type"		= "UPC_TYPE_USB3_A"
 						register "group"	= "ACPI_PLD_GROUP(0, 2)"
-						device ref usb3_port1 on end
+						device ref usb3_port2 on end
 					end
 					chip drivers/usb/acpi
 						register "desc"		= ""Right USB Type-A""
@@ -112,7 +96,7 @@ chip soc/intel/alderlake
 						register "desc"		= ""Right USB Type-A""
 						register "type"		= "UPC_TYPE_USB3_A"
 						register "group"	= "ACPI_PLD_GROUP(0, 3)"
-						device ref usb3_port2 on end
+						device ref usb3_port1 on end
 					end
 					chip drivers/usb/acpi
 						register "desc"		= ""Internal Webcam""
@@ -205,8 +189,8 @@ chip soc/intel/alderlake
 		device ref uart0	on  end
 		device ref pch_espi	on
 			register "gen1_dec"			= "0x00040069"
-			register "gen2_dec"			= "0x00fc0e01"
-			register "gen3_dec"			= "0x00fc0f01"
+			register "gen2_dec"			= "0x00040069"
+			register "gen3_dec"			= "0x00040069"
 
 			chip drivers/pc80/tpm
 				device pnp 0c31.0 on end
@@ -239,15 +223,10 @@ chip soc/intel/alderlake
 			chip drivers/intel/pmc_mux
 				device generic 0 on
 					chip drivers/intel/pmc_mux/conn
-						use usb2_port2 as usb2_port
+						use usb2_port3 as usb2_port
 						use usb3_port3 as usb3_port
 						device generic 0 alias conn0 on end
 					end
-					chip drivers/intel/pmc_mux/conn
-						use usb2_port3 as usb2_port
-						use usb3_port4 as usb3_port
-						device generic 1 alias conn1 on end
-					end
 				end
 			end
 		end

From 9495063993e32345b138fa99631d03309f3506f1 Mon Sep 17 00:00:00 2001
From: Zhixing Ma <zhixing.ma@intel.corp-partner.google.com>
Date: Mon, 13 Jan 2025 13:20:12 -0800
Subject: [PATCH 0157/3886] mainboard/google/fatcat: Fix SMBIOS Processor
 upgrade info
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

The current SMBIOS for fatcat is missing processor upgrade information.
This patch adds the missing value by enabling kconfig flag
CPU_INTEL_SOCKET_OTHER.
Refer to SMBIOS spec sheet for documentation on cpu socket values:
https://web.archive.org/web/20221012222420/https://www.dmtf.org/sites/default/files/standards/documents/DSP0134_3.6.0.pdf

Output of dmidecode:
Handle 0x0004, DMI type 4, 48 bytes
Processor Information
        Socket Designation: CPU0
        Type: Central Processor
        Family: Pentium Pro
        Manufacturer: GenuineIntel
        ID: C0 06 0C 00 FF FB EB BF
        Signature: Type 0, Family 6, Model 204, Stepping 0
        Flags: ...
        Version: Genuine Intel(R) 0000
        Voltage: Unknown
        External Clock: 100 MHz
        Max Speed: 3200 MHz
        Current Speed: 3000 MHz
        Status: Populated, Enabled
-       Upgrade: Unknown
+       Upgrade: Other

BUG=NONE
TEST=Boot and verified that SMBIOS processor upgrade value is correct.

Change-Id: Ica92d15e4a6123f928fceb77c7638e4c45d6dc7d
Signed-off-by: Zhixing Ma <zhixing.ma@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85960
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
---
 src/mainboard/google/fatcat/Kconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/src/mainboard/google/fatcat/Kconfig b/src/mainboard/google/fatcat/Kconfig
index e82081d822..13d791a812 100644
--- a/src/mainboard/google/fatcat/Kconfig
+++ b/src/mainboard/google/fatcat/Kconfig
@@ -3,6 +3,7 @@
 config BOARD_GOOGLE_FATCAT_COMMON
 	def_bool n
 	select BOARD_ROMSIZE_KB_32768
+	select CPU_INTEL_SOCKET_OTHER
 	select DRIVERS_GFX_GENERIC
 	select DRIVERS_I2C_GENERIC
 	select DRIVERS_I2C_HID

From 4b1c4e7ee8fc1cceed8569baed7ba5456e075942 Mon Sep 17 00:00:00 2001
From: Zheng Bao <fishbaozi@gmail.com>
Date: Fri, 20 Sep 2024 17:55:32 +0800
Subject: [PATCH 0158/3886] amdfwtool: Reorder the PSP L2 and BIOS L2 for A/B
 recovery

For A/B recovery, it is better, even though it is not mandatory, to
put BIOS level 2 table next to its PSP level2. So the relative
addresses of BIOS table are the same. So all the data in B could be a
copy of A.

Identical binary test on all non A/B recovery platform.
Booting test on Majolica with A/B recovery enabled.

Change-Id: Ia25277d307329a2fa66d38d1a7fc21b18246cfe6
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84440
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
---
 util/amdfwtool/amdfwtool.c | 20 ++++++++++----------
 1 file changed, 10 insertions(+), 10 deletions(-)

diff --git a/util/amdfwtool/amdfwtool.c b/util/amdfwtool/amdfwtool.c
index 42d13d8aa8..0de0475b9a 100644
--- a/util/amdfwtool/amdfwtool.c
+++ b/util/amdfwtool/amdfwtool.c
@@ -1770,11 +1770,17 @@ int main(int argc, char **argv)
 			/* Do 2nd PSP directory followed by 1st */
 			integrate_psp_firmwares(&ctx,
 						amd_psp_fw_table, PSPL2_COOKIE, &cb_config);
+			if (cb_config.recovery_ab)
+				integrate_bios_firmwares(&ctx,
+						amd_bios_table, BHDL2_COOKIE, &cb_config);
+
 			if (cb_config.recovery_ab && !cb_config.recovery_ab_single_copy) {
 				/* Create a copy of PSP Directory 2 in the backup slot B.
 				   Related biosdir2_b copy will be created later. */
 				integrate_psp_firmwares(&ctx,
 						amd_psp_fw_table, PSPL2_COOKIE, &cb_config);
+				integrate_bios_firmwares(&ctx,
+						amd_bios_table, BHDL2_COOKIE, &cb_config);
 			} else {
 				/*
 				 * Either the platform is using only
@@ -1790,6 +1796,8 @@ int main(int argc, char **argv)
 				integrate_psp_firmwares(&ctx,
 					amd_psp_fw_table, PSP_COOKIE, &cb_config);
 			integrate_psp_levels(&ctx, &cb_config);
+			if (cb_config.recovery_ab)
+				integrate_bios_levels(&ctx, &cb_config);
 		} else {
 			/* flat: PSP 1 cookie and no pointer to 2nd table */
 			integrate_psp_firmwares(&ctx,
@@ -1805,21 +1813,13 @@ int main(int argc, char **argv)
 			add_combo_entry(ctx.psp_combo_dir, ctx.pspdir, combo_index, &ctx, &cb_config);
 		}
 
-		if (have_bios_tables(amd_bios_table)) {
+		if (have_bios_tables(amd_bios_table) && !cb_config.recovery_ab) {
 			if (cb_config.multi_level) {
 				/* Do 2nd level BIOS directory followed by 1st */
 				integrate_bios_firmwares(&ctx,
 						amd_bios_table, BHDL2_COOKIE, &cb_config);
-				if (cb_config.recovery_ab) {
-					if (ctx.pspdir2_b != NULL) {
-						integrate_bios_firmwares(&ctx,
-								amd_bios_table, BHDL2_COOKIE,
-								&cb_config);
-					}
-				} else {
-					integrate_bios_firmwares(&ctx,
+				integrate_bios_firmwares(&ctx,
 							amd_bios_table, BHD_COOKIE, &cb_config);
-				}
 				integrate_bios_levels(&ctx, &cb_config);
 			} else {
 				/* flat: BHD1 cookie and no pointer to 2nd table */

From daf32b75c6f1a3dca782998ea405429a97a7936c Mon Sep 17 00:00:00 2001
From: Zheng Bao <fishbaozi@gmail.com>
Date: Sat, 21 Sep 2024 11:22:11 +0800
Subject: [PATCH 0159/3886] amdfwtool: Merge all the steps for A/B recovery
 into one branch

Clean up the code to make it more logical.
This is for later changes to reorder the PSP Level 1, Level 2, ISH and
BIOS tables.

TEST=Identical test on all AMD platform

Change-Id: I5f7213fd42c7f0ff5ecd9e504a6654cdfb1e3513
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84531
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 util/amdfwtool/amdfwtool.c | 25 ++++++-------------------
 1 file changed, 6 insertions(+), 19 deletions(-)

diff --git a/util/amdfwtool/amdfwtool.c b/util/amdfwtool/amdfwtool.c
index 0de0475b9a..89aff6aaa7 100644
--- a/util/amdfwtool/amdfwtool.c
+++ b/util/amdfwtool/amdfwtool.c
@@ -1770,34 +1770,21 @@ int main(int argc, char **argv)
 			/* Do 2nd PSP directory followed by 1st */
 			integrate_psp_firmwares(&ctx,
 						amd_psp_fw_table, PSPL2_COOKIE, &cb_config);
-			if (cb_config.recovery_ab)
+			if (cb_config.recovery_ab) {
 				integrate_bios_firmwares(&ctx,
 						amd_bios_table, BHDL2_COOKIE, &cb_config);
-
-			if (cb_config.recovery_ab && !cb_config.recovery_ab_single_copy) {
-				/* Create a copy of PSP Directory 2 in the backup slot B.
-				   Related biosdir2_b copy will be created later. */
-				integrate_psp_firmwares(&ctx,
+				if (!cb_config.recovery_ab_single_copy) {
+					integrate_psp_firmwares(&ctx,
 						amd_psp_fw_table, PSPL2_COOKIE, &cb_config);
-				integrate_bios_firmwares(&ctx,
+					integrate_bios_firmwares(&ctx,
 						amd_bios_table, BHDL2_COOKIE, &cb_config);
-			} else {
-				/*
-				 * Either the platform is using only
-				 * one slot or B is same as above
-				 * directories for A. Skip creating
-				 * pspdir2_b here to save flash space.
-				 * Related biosdir2_b will be skipped
-				 * automatically.
-				 */
-				ctx.pspdir2_b = NULL; /* More explicitly */
+				}
+				integrate_bios_levels(&ctx, &cb_config);
 			}
 			if (!cb_config.combo_new_rab || combo_index == 0)
 				integrate_psp_firmwares(&ctx,
 					amd_psp_fw_table, PSP_COOKIE, &cb_config);
 			integrate_psp_levels(&ctx, &cb_config);
-			if (cb_config.recovery_ab)
-				integrate_bios_levels(&ctx, &cb_config);
 		} else {
 			/* flat: PSP 1 cookie and no pointer to 2nd table */
 			integrate_psp_firmwares(&ctx,

From 018c9a6388a650806799031ca5b1a9f9fef78bfa Mon Sep 17 00:00:00 2001
From: Zheng Bao <fishbaozi@gmail.com>
Date: Sat, 14 Dec 2024 09:04:14 +0800
Subject: [PATCH 0160/3886] amdfwtool: Add combo_index into context

We need to know how many combo entries have been processed.
It will be checked in functions in later change.

Change-Id: I4b026b0630a18d1f46bff98ffe5f11e7f930d7a8
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85590
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 util/amdfwtool/amdfwtool.c | 27 +++++++++++++--------------
 util/amdfwtool/amdfwtool.h |  1 +
 2 files changed, 14 insertions(+), 14 deletions(-)

diff --git a/util/amdfwtool/amdfwtool.c b/util/amdfwtool/amdfwtool.c
index 89aff6aaa7..7b5e70e3c3 100644
--- a/util/amdfwtool/amdfwtool.c
+++ b/util/amdfwtool/amdfwtool.c
@@ -1628,7 +1628,6 @@ static bool needs_new_combo_layout(enum platform soc_id)
 int main(int argc, char **argv)
 {
 	int retval = 0;
-	int combo_index = 0;
 	int targetfd;
 	context ctx = { 0 };
 	uint32_t romsig_offset;
@@ -1719,17 +1718,17 @@ int main(int argc, char **argv)
 			ctx.bhd_combo_dir = new_combo_dir(&ctx, BHD2_COOKIE);
 	}
 
-	combo_index = 0;
+	ctx.combo_index = 0;
 	if (cb_config.config)
 		cb_config.combo_config[0] = cb_config.config;
 
 	do {
 		if (cb_config.use_combo && cb_config.debug)
-			printf("Processing %dth combo entry\n", combo_index);
+			printf("Processing %dth combo entry\n", ctx.combo_index);
 
 		/* The pspdir level 1 is special. For new combo layout, all the combo entries
 		   share one pspdir L1. It should not be cleared at each iteration. */
-		if (!cb_config.combo_new_rab || combo_index == 0) {
+		if (!cb_config.combo_new_rab || ctx.combo_index == 0) {
 			ctx.pspdir = NULL;
 			ctx.pspdir_bak = NULL;
 		}
@@ -1746,14 +1745,14 @@ int main(int argc, char **argv)
 		 *  and make it clear this will not affect non-combo
 		 *  case.
 		 */
-		if (cb_config.use_combo && combo_index > 0) {
+		if (cb_config.use_combo && ctx.combo_index > 0) {
 			/* Restore the table as clean data. */
 			memcpy(amd_psp_fw_table, ctx.amd_psp_fw_table_clean,
 				sizeof(amd_psp_fw_table));
 			memcpy(amd_bios_table, ctx.amd_bios_table_clean,
 				sizeof(amd_bios_table));
-			assert_fw_entry(combo_index, MAX_COMBO_ENTRIES, &ctx);
-			open_process_config(cb_config.combo_config[combo_index], &cb_config);
+			assert_fw_entry(ctx.combo_index, MAX_COMBO_ENTRIES, &ctx);
+			open_process_config(cb_config.combo_config[ctx.combo_index], &cb_config);
 
 			/* In most cases, the address modes are same. */
 			if (cb_config.need_ish)
@@ -1763,7 +1762,7 @@ int main(int argc, char **argv)
 			else
 				ctx.address_mode = AMD_ADDR_PHYSICAL;
 
-			register_apcb_combo(&cb_config, combo_index, &ctx);
+			register_apcb_combo(&cb_config, ctx.combo_index, &ctx);
 		}
 
 		if (cb_config.multi_level) {
@@ -1781,7 +1780,7 @@ int main(int argc, char **argv)
 				}
 				integrate_bios_levels(&ctx, &cb_config);
 			}
-			if (!cb_config.combo_new_rab || combo_index == 0)
+			if (!cb_config.combo_new_rab || ctx.combo_index == 0)
 				integrate_psp_firmwares(&ctx,
 					amd_psp_fw_table, PSP_COOKIE, &cb_config);
 			integrate_psp_levels(&ctx, &cb_config);
@@ -1791,13 +1790,13 @@ int main(int argc, char **argv)
 					amd_psp_fw_table, PSP_COOKIE, &cb_config);
 		}
 
-		if (!cb_config.use_combo || (cb_config.combo_new_rab && combo_index == 0)) {
+		if (!cb_config.use_combo || (cb_config.combo_new_rab && ctx.combo_index == 0)) {
 			/* For new combo layout, there is only 1 PSP level 1 directory. */
 			fill_psp_directory_to_efs(ctx.amd_romsig_ptr, ctx.pspdir, &ctx, &cb_config);
 			fill_psp_bak_directory_to_efs(ctx.amd_romsig_ptr, ctx.pspdir_bak, &ctx, &cb_config);
 		} else if (cb_config.use_combo && !cb_config.combo_new_rab) {
 			fill_psp_directory_to_efs(ctx.amd_romsig_ptr, ctx.psp_combo_dir, &ctx, &cb_config);
-			add_combo_entry(ctx.psp_combo_dir, ctx.pspdir, combo_index, &ctx, &cb_config);
+			add_combo_entry(ctx.psp_combo_dir, ctx.pspdir, ctx.combo_index, &ctx, &cb_config);
 		}
 
 		if (have_bios_tables(amd_bios_table) && !cb_config.recovery_ab) {
@@ -1822,13 +1821,13 @@ int main(int argc, char **argv)
 				 */
 				fill_bios_directory_to_efs(ctx.amd_romsig_ptr, ctx.bhd_combo_dir,
 					&ctx, &cb_config);
-				add_combo_entry(ctx.bhd_combo_dir, ctx.biosdir, combo_index, &ctx, &cb_config);
+				add_combo_entry(ctx.bhd_combo_dir, ctx.biosdir, ctx.combo_index, &ctx, &cb_config);
 			}
 		}
 		if (cb_config.debug)
 			dump_image_addresses(&ctx);
-	} while (cb_config.use_combo && ++combo_index < MAX_COMBO_ENTRIES &&
-					cb_config.combo_config[combo_index] != NULL);
+	} while (cb_config.use_combo && ++ctx.combo_index < MAX_COMBO_ENTRIES &&
+					cb_config.combo_config[ctx.combo_index] != NULL);
 
 	targetfd = open(cb_config.output, O_RDWR | O_CREAT | O_TRUNC, 0666);
 	if (targetfd >= 0) {
diff --git a/util/amdfwtool/amdfwtool.h b/util/amdfwtool/amdfwtool.h
index f87fbf56ce..3c773f70d5 100644
--- a/util/amdfwtool/amdfwtool.h
+++ b/util/amdfwtool/amdfwtool.h
@@ -447,6 +447,7 @@ typedef struct _context {
 	uint32_t current;	/* pointer within flash & proxy buffer */
 	uint32_t current_pointer_saved;
 	uint32_t current_table;
+	uint32_t combo_index;
 	void *amd_psp_fw_table_clean;
 	void *amd_bios_table_clean;
 	struct _combo_apcb {

From b1fb0dff2477a01fbe20fa22fe580f84972a091b Mon Sep 17 00:00:00 2001
From: Tongtong Pan <pantongtong@huaqin.corp-partner.google.com>
Date: Fri, 21 Feb 2025 10:46:49 +0800
Subject: [PATCH 0161/3886] mb/google/fatcat/var/felino: Enable CNVi wifi core

Enable CNVi wifi core for felino.

BUG=b:388982526
TEST=abuild -v -a -x -c max -p none -t google/fatcat -b felino

Change-Id: Ib5a98dc481b0c64612ffd50242262714f114b5b7
Signed-off-by: Tongtong Pan <pantongtong@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86549
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com>
---
 src/mainboard/google/fatcat/variants/felino/overridetree.cb | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/src/mainboard/google/fatcat/variants/felino/overridetree.cb b/src/mainboard/google/fatcat/variants/felino/overridetree.cb
index d401ed2c63..62b4160b74 100644
--- a/src/mainboard/google/fatcat/variants/felino/overridetree.cb
+++ b/src/mainboard/google/fatcat/variants/felino/overridetree.cb
@@ -28,6 +28,9 @@ chip soc/intel/pantherlake
 		.tdp_pl2_override = 25,
 	}"
 
+	# Enable CNVi WiFi
+	register "cnvi_wifi_core" = "true"
+
 	register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC_SKIP)" # USB2_C0
 	register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC_SKIP)" # USB2_C1
 	register "usb2_ports[4]" = "USB2_PORT_MID(OC_SKIP)" # Type-A Port A0  # USB HUB (USB2 Camera)

From 67dab0c3c942b58f5421bc9d87312ac6793f5093 Mon Sep 17 00:00:00 2001
From: Nicolas Kochlowski <nickkochlowski@gmail.com>
Date: Thu, 19 Dec 2024 12:36:50 -0300
Subject: [PATCH 0162/3886] drivers/amd/opensil/memmap.c: Factor out common
 memmap code to driver

Refactor the vendorcode openSIL memory map code and move all common
calls that do not require any openSIL headers to the driver. Improve
the legibility of the logic to return memory hole type string.

Change-Id: I80b9bdd7fd633c7b12d695ced5d4b9b518570d80
Signed-off-by: Nicolas Kochlowski <nickkochlowski@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85634
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
---
 src/drivers/amd/opensil/Makefile.mk           |  1 +
 src/drivers/amd/opensil/memmap.c              | 89 +++++++++++++++++
 src/drivers/amd/opensil/opensil.h             |  3 +
 src/soc/amd/genoa_poc/domain.c                |  5 +-
 src/soc/amd/phoenix/memmap.c                  |  4 +-
 src/vendorcode/amd/opensil/genoa_poc/memmap.c | 97 +++----------------
 src/vendorcode/amd/opensil/opensil.h          |  5 +-
 src/vendorcode/amd/opensil/stub/ramstage.c    | 10 +-
 8 files changed, 124 insertions(+), 90 deletions(-)
 create mode 100644 src/drivers/amd/opensil/memmap.c

diff --git a/src/drivers/amd/opensil/Makefile.mk b/src/drivers/amd/opensil/Makefile.mk
index 98377186aa..6ed46d1f81 100644
--- a/src/drivers/amd/opensil/Makefile.mk
+++ b/src/drivers/amd/opensil/Makefile.mk
@@ -8,5 +8,6 @@ romstage-y += romstage.c
 
 ramstage-y += acpi.c
 ramstage-y += ramstage.c
+ramstage-y += memmap.c
 
 endif
diff --git a/src/drivers/amd/opensil/memmap.c b/src/drivers/amd/opensil/memmap.c
new file mode 100644
index 0000000000..9b80a882ef
--- /dev/null
+++ b/src/drivers/amd/opensil/memmap.c
@@ -0,0 +1,89 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <bootstate.h>
+#include <cbmem.h>
+#include <cpu/amd/mtrr.h>
+#include <string.h>
+#include <vendorcode/amd/opensil/opensil.h>
+
+#include "opensil.h"
+
+/*
+ * This structure definition must align exactly with the MEMORY_HOLE_TYPES structure
+ * defined in openSIL to ensure accurate casting.
+ */
+typedef struct {
+	uint64_t base;
+	uint64_t size;
+	uint32_t type;
+	uint32_t reserved;
+} HOLE_INFO;
+
+/* This assumes holes are allocated */
+void amd_opensil_add_memmap(struct device *dev, unsigned long *idx)
+{
+	uint64_t top_of_mem = 0;
+	uint32_t n_holes = 0;
+	void *hole_info = NULL;
+
+	/* Account for UMA and TSEG */
+	const uint32_t mem_usable = cbmem_top();
+	const uint32_t top_mem = ALIGN_DOWN(get_top_of_mem_below_4gb(), 1 * MiB);
+	if (mem_usable != top_mem)
+		reserved_ram_from_to(dev, (*idx)++, mem_usable, top_mem);
+
+	/* Holes in upper DRAM */
+	/* This assumes all the holes in upper DRAM are continuous */
+	opensil_get_hole_info(&n_holes, &top_of_mem, &hole_info);
+	if (hole_info == NULL)
+		return;
+
+	/* Check if we're done */
+	if (top_of_mem <= 4ULL * GiB)
+		return;
+
+	HOLE_INFO *holes = (HOLE_INFO *)hole_info;
+
+	uint64_t lowest_upper_hole_base = top_of_mem;
+	uint64_t highest_upper_hole_end = 4ULL * GiB;
+	for (size_t hole = 0; hole < n_holes; hole++) {
+		if (!strcmp(opensil_get_hole_info_type(holes[hole].type), "MMIO"))
+			continue;
+		if (holes[hole].base < 4ULL * GiB)
+			continue;
+		lowest_upper_hole_base = MIN(lowest_upper_hole_base, holes[hole].base);
+		highest_upper_hole_end = MAX(highest_upper_hole_end, holes[hole].base + holes[hole].size);
+		if (!strcmp(opensil_get_hole_info_type(holes[hole].type), "UMA"))
+			mmio_range(dev, (*idx)++, holes[hole].base, holes[hole].size);
+		else
+			reserved_ram_range(dev, (*idx)++, holes[hole].base, holes[hole].size);
+	}
+
+	ram_from_to(dev, (*idx)++, 4ULL * GiB, lowest_upper_hole_base);
+
+	if (top_of_mem > highest_upper_hole_end)
+		ram_from_to(dev, (*idx)++, highest_upper_hole_end, top_of_mem);
+}
+
+static void print_memory_holes(void *unused)
+{
+	uint64_t top_of_mem = 0;
+	uint32_t n_holes = 0;
+	void *hole_info = NULL;
+
+	opensil_get_hole_info(&n_holes, &top_of_mem, &hole_info);
+	if (hole_info == NULL)
+		return;
+
+	HOLE_INFO *holes = (HOLE_INFO *)hole_info;
+
+	printk(BIOS_DEBUG, "APOB: top of memory 0x%016llx\n", top_of_mem);
+	printk(BIOS_DEBUG, "The following holes are reported in APOB\n");
+	for (size_t hole = 0; hole < n_holes; hole++) {
+		printk(BIOS_DEBUG, "  Base: 0x%016llx, Size: 0x%016llx, Type: %02d:%s\n",
+			holes[hole].base, holes[hole].size, holes[hole].type,
+			opensil_get_hole_info_type(holes[hole].type));
+	}
+}
+
+BOOT_STATE_INIT_ENTRY(BS_DEV_RESOURCES, BS_ON_ENTRY, print_memory_holes, NULL);
diff --git a/src/drivers/amd/opensil/opensil.h b/src/drivers/amd/opensil/opensil.h
index f2bcd6b900..e6efbdc80a 100644
--- a/src/drivers/amd/opensil/opensil.h
+++ b/src/drivers/amd/opensil/opensil.h
@@ -4,11 +4,14 @@
 #define OPENSIL_DRIVER_H
 
 #include <acpi/acpi.h>
+#include <device/device.h>
 
 /* Set up openSIL env and call TP1 */
 void amd_opensil_silicon_init(void);
 /* Set global and per-device MPIO configurations */
 void configure_mpio(void);
+/* Add the memory map to dev, starting at index idx, returns last use idx */
+void amd_opensil_add_memmap(struct device *dev, unsigned long *idx);
 /* Fill in FADT from openSIL */
 void amd_opensil_fill_fadt_io_ports(acpi_fadt_t *fadt);
 
diff --git a/src/soc/amd/genoa_poc/domain.c b/src/soc/amd/genoa_poc/domain.c
index 65b13958cb..d45d317605 100644
--- a/src/soc/amd/genoa_poc/domain.c
+++ b/src/soc/amd/genoa_poc/domain.c
@@ -9,17 +9,16 @@
 #include <arch/ioapic.h>
 #include <console/console.h>
 #include <device/device.h>
+#include <drivers/amd/opensil/opensil.h>
 #include <types.h>
 
-#include <vendorcode/amd/opensil/opensil.h>
-
 #define IOHC_IOAPIC_BASE_ADDR_LO 0x2f0
 
 void read_soc_memmap_resources(struct device *domain, unsigned long *idx)
 {
 	read_lower_soc_memmap_resources(domain, idx);
 
-	add_opensil_memmap(domain, idx);
+	amd_opensil_add_memmap(domain, idx);
 }
 
 static void genoa_domain_set_resources(struct device *domain)
diff --git a/src/soc/amd/phoenix/memmap.c b/src/soc/amd/phoenix/memmap.c
index d29dcbee63..1b45b9c93c 100644
--- a/src/soc/amd/phoenix/memmap.c
+++ b/src/soc/amd/phoenix/memmap.c
@@ -4,8 +4,8 @@
 #include <amdblocks/memmap.h>
 #include <amdblocks/root_complex.h>
 #include <device/device.h>
+#include <drivers/amd/opensil/opensil.h>
 #include <stdint.h>
-#include <vendorcode/amd/opensil/opensil.h>
 
 /*
  *                     +--------------------------------+
@@ -69,5 +69,5 @@ void read_soc_memmap_resources(struct device *dev, unsigned long *idx)
 	if (CONFIG(PLATFORM_USES_FSP2_0))
 		read_fsp_resources(dev, idx);
 	else
-		add_opensil_memmap(dev, idx);
+		amd_opensil_add_memmap(dev, idx);
 }
diff --git a/src/vendorcode/amd/opensil/genoa_poc/memmap.c b/src/vendorcode/amd/opensil/genoa_poc/memmap.c
index ece9877183..eed1be7e5f 100644
--- a/src/vendorcode/amd/opensil/genoa_poc/memmap.c
+++ b/src/vendorcode/amd/opensil/genoa_poc/memmap.c
@@ -1,20 +1,17 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
-#include <bootstate.h>
-#include <stdint.h>
-#include <stdbool.h>
 #include <SilCommon.h>
 #include <Sil-api.h> // needed above ApobCmn.h
 #include <ApobCmn.h>
-#include <device/device.h>
 #include <xPRF-api.h>
-#include <cpu/amd/mtrr.h>
-#include <cbmem.h>
-#include <amdblocks/memmap.h>
 
 #include "../opensil.h"
 
-static const char *hole_info_type(MEMORY_HOLE_TYPES type)
+_Static_assert(sizeof(uint32_t) == sizeof(((MEMORY_HOLE_DESCRIPTOR){0}).Type),
+	"Unexpected size of MEMORY_HOLE_TYPES in the MEMORY_HOLE_DESCRIPTOR "
+	"struct which doesn't match the code in drivers/amd/opensil/memmap.c");
+
+const char *opensil_get_hole_info_type(uint32_t type)
 {
 	const struct hole_type {
 		MEMORY_HOLE_TYPES type;
@@ -40,85 +37,21 @@ static const char *hole_info_type(MEMORY_HOLE_TYPES type)
 	};
 
 	int i;
+	MEMORY_HOLE_TYPES enum_type = (MEMORY_HOLE_TYPES)type; // Cast int to enum
 	for (i = 0; i < ARRAY_SIZE(types); i++)
-		if (type == types[i].type)
-			break;
-	if (i == ARRAY_SIZE(types))
-		return "Unknown type";
-	return types[i].string;
+		if (enum_type == types[i].type)
+			return types[i].string;
+	return "Unknown type";
 }
 
-static uint64_t top_of_mem;
-static uint32_t n_holes;
-static MEMORY_HOLE_DESCRIPTOR *hole_info;
-
-static void get_hole_info(void)
+void opensil_get_hole_info(uint32_t *n_holes, uint64_t *top_of_mem, void **hole_info)
 {
-	static bool done;
-	if (done)
-		return;
-        SIL_STATUS status = xPrfGetSystemMemoryMap(&n_holes, &top_of_mem, (void **)&hole_info);
+        SIL_STATUS status = xPrfGetSystemMemoryMap(n_holes, top_of_mem, hole_info);
 	SIL_STATUS_report("xPrfGetSystemMemoryMap", status);
 	// Make sure hole_info does not get initialized to something odd by xPRF on failure
-	if (status != SilPass)
-		hole_info = NULL;
-	done = true;
-}
-
-
-static void print_memory_holes(void *unused)
-{
-	get_hole_info();
-	if (hole_info == NULL)
-		return;
-
-	printk(BIOS_DEBUG, "APOB: top of memory 0x%016llx\n", top_of_mem);
-	printk(BIOS_DEBUG, "The following holes are reported in APOB\n");
-	for (int hole = 0; hole < n_holes; hole++) {
-		printk(BIOS_DEBUG, "  Base: 0x%016llx, Size: 0x%016llx, Type: %02d:%s\n",
-		       hole_info[hole].Base, hole_info[hole].Size, hole_info[hole].Type,
-		       hole_info_type(hole_info[hole].Type));
+	if (status != SilPass) {
+		*hole_info = NULL;
+		*n_holes = 0;
+		*top_of_mem = 0;
 	}
 }
-
-BOOT_STATE_INIT_ENTRY(BS_DEV_RESOURCES, BS_ON_ENTRY, print_memory_holes, NULL);
-
-// This assumes holes are allocated
-void add_opensil_memmap(struct device *dev, unsigned long *idx)
-{
-	// Account for UMA and TSEG
-	const uint32_t mem_usable = cbmem_top();
-	const uint32_t top_mem = ALIGN_DOWN(get_top_of_mem_below_4gb(), 1 * MiB);
-	if (mem_usable != top_mem)
-		reserved_ram_from_to(dev, (*idx)++, mem_usable, top_mem);
-
-	// Check if we're done
-	if (top_of_mem <= 4ULL * GiB)
-		return;
-
-	// Holes in upper DRAM
-	// This assumes all the holes in upper DRAM are continuous
-	get_hole_info();
-	if (hole_info == NULL)
-		return;
-	uint64_t lowest_upper_hole_base = top_of_mem;
-	uint64_t highest_upper_hole_end = 4ULL * GiB;
-	for (int hole = 0; hole < n_holes; hole++) {
-		if (hole_info[hole].Type == MMIO)
-			continue;
-		if (hole_info[hole].Base < 4ULL * GiB)
-			continue;
-		lowest_upper_hole_base = MIN(lowest_upper_hole_base, hole_info[hole].Base);
-		highest_upper_hole_end = MAX(highest_upper_hole_end, hole_info[hole].Base + hole_info[hole].Size);
-		if (hole_info[hole].Type == UMA)
-			mmio_range(dev, (*idx)++, hole_info[hole].Base, hole_info[hole].Size);
-		else
-			reserved_ram_range(dev, (*idx)++, hole_info[hole].Base, hole_info[hole].Size);
-	}
-
-	ram_from_to(dev, (*idx)++, 4ULL * GiB, lowest_upper_hole_base);
-
-	// Do we need this?
-	if (top_of_mem > highest_upper_hole_end)
-		ram_from_to(dev, (*idx)++, highest_upper_hole_end, top_of_mem);
-}
diff --git a/src/vendorcode/amd/opensil/opensil.h b/src/vendorcode/amd/opensil/opensil.h
index c84a180b86..3ed896067f 100644
--- a/src/vendorcode/amd/opensil/opensil.h
+++ b/src/vendorcode/amd/opensil/opensil.h
@@ -8,8 +8,9 @@
 #include <types.h>
 
 void SIL_STATUS_report(const char *function, const int status);
-// Add the memory map to dev, starting at index idx, returns last use idx
-void add_opensil_memmap(struct device *dev, unsigned long *idx);
+
+void opensil_get_hole_info(uint32_t *n_holes, uint64_t *top_of_mem, void **hole_info);
+const char *opensil_get_hole_info_type(uint32_t type);
 
 void opensil_fill_fadt(acpi_fadt_t *fadt);
 unsigned long add_opensil_acpi_table(unsigned long current, acpi_rsdp_t *rsdp);
diff --git a/src/vendorcode/amd/opensil/stub/ramstage.c b/src/vendorcode/amd/opensil/stub/ramstage.c
index 5da6134ce3..d2e3d6aa21 100644
--- a/src/vendorcode/amd/opensil/stub/ramstage.c
+++ b/src/vendorcode/amd/opensil/stub/ramstage.c
@@ -5,9 +5,17 @@
 
 #include "../opensil.h"
 
-void add_opensil_memmap(struct device *dev, unsigned long *idx)
+void opensil_get_hole_info(uint32_t *n_holes, uint64_t *top_of_mem, void **hole_info)
+{
+	*n_holes = 0;
+	*top_of_mem = 0xc0000000;
+	printk(BIOS_NOTICE, "openSIL stub: %s\n", __func__);
+}
+
+const char *opensil_get_hole_info_type(uint32_t type)
 {
 	printk(BIOS_NOTICE, "openSIL stub: %s\n", __func__);
+	return "";
 }
 
 void opensil_fill_fadt(acpi_fadt_t *fadt)

From 14ff47783b97d748c81d20cc4b27f90325c219ae Mon Sep 17 00:00:00 2001
From: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Date: Thu, 20 Feb 2025 15:37:46 +0800
Subject: [PATCH 0163/3886] mb/google/nissa/var/dirks: Update ddi_ports_config

Update ddi_ports_config to match VBT's settings.

DDI_PORT_A = HDMI
DDI_PORT_B = HDMI
DDI_PORT_1 = Type-C DP

BUG=b:389391653
TEST=emerge-nissa coreboot

Change-Id: I67e9fcf4a3caa303ec8d873507a7533389c095ae
Signed-off-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86537
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com>
---
 .../google/brya/variants/dirks/overridetree.cb         | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/src/mainboard/google/brya/variants/dirks/overridetree.cb b/src/mainboard/google/brya/variants/dirks/overridetree.cb
index bc1c1867bb..a953b4ca76 100644
--- a/src/mainboard/google/brya/variants/dirks/overridetree.cb
+++ b/src/mainboard/google/brya/variants/dirks/overridetree.cb
@@ -87,6 +87,16 @@ chip soc/intel/alderlake
 	# Enable the Cnvi BT Audio Offload
 	register "cnvi_bt_audio_offload" = "1"
 
+	# Disable eDP on DDI portA
+	register "ddi_portA_config" = "0"
+
+	# Enable HPD and DDC for DDI port A
+	register "ddi_ports_config" = "{
+		[DDI_PORT_A] = DDI_ENABLE_HPD | DDI_ENABLE_DDC,
+		[DDI_PORT_B] = DDI_ENABLE_HPD | DDI_ENABLE_DDC,
+		[DDI_PORT_1] = DDI_ENABLE_HPD
+	}"
+
 	# Intel Common SoC Config
 	#+-------------------+---------------------------+
 	#| Field             |  Value                    |

From e3cf1bc4ccba5fdcf4aaccfc24a5b9240492775f Mon Sep 17 00:00:00 2001
From: Dinesh Gehlot <digehlot@google.com>
Date: Fri, 14 Feb 2025 20:05:51 +0530
Subject: [PATCH 0164/3886] mb/google/brya: Do not select HAVE_ACPI_RESUME

This patch removes the HAVE_ACPI_RESUME config option from the Google
Brya mainboard configuration. The Intel Alder Lake SoC does not support
S3 (ACPI sleep state) entry/exit, and attempting S3 validation could
lead to abnormal platform behavior. This change ensures that `_S3` is
not listed as a valid wake source in the DSDT (Differentiated System
Description Table) after booting to the OS.

BUG=b:337274309
TEST=Boot verfied google/trulo.
TEST=Veified that the _S3 name variable is not present in the DSDT ASL.

Change-Id: Ic0dce9c7779333ca079001e3763e843a4aad9a81
Signed-off-by: Dinesh Gehlot <digehlot@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86422
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/google/brya/Kconfig | 1 -
 1 file changed, 1 deletion(-)

diff --git a/src/mainboard/google/brya/Kconfig b/src/mainboard/google/brya/Kconfig
index aac2393017..1ca5094e92 100644
--- a/src/mainboard/google/brya/Kconfig
+++ b/src/mainboard/google/brya/Kconfig
@@ -28,7 +28,6 @@ config BOARD_GOOGLE_BRYA_COMMON
 	select FW_CONFIG
 	select FW_CONFIG_SOURCE_CHROMEEC_CBI
 	select GOOGLE_SMBIOS_MAINBOARD_VERSION
-	select HAVE_ACPI_RESUME
 	select HAVE_ACPI_TABLES
 	select HAVE_FSP_LOGO_SUPPORT if RUN_FSP_GOP
 	select I2C_TPM

From 61f7e5a6cfcd08890d9a730a8a594dbc4bc7afbe Mon Sep 17 00:00:00 2001
From: Vince Liu <vince-wl.liu@mediatek.corp-partner.google.com>
Date: Tue, 18 Feb 2025 14:44:37 +0800
Subject: [PATCH 0165/3886] soc/mediatek/mt8196: Move common functions to
 gpio_eint_v2.c

Move gpio_get_eint_reg() and gpio_calc_eint_pos_bit() to common code
to avoid redundant definitions for other platforms such as MT8189.

BUG=b:379008996
BRANCH=none
TEST=build passed.

Signed-off-by: Vince Liu <vince-wl.liu@mediatek.corp-partner.google.com>
Change-Id: Id21f627a49f730f3a0db786a148f81806aeba287
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86541
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/soc/mediatek/common/gpio_eint_v2.c        | 55 ++++++++++++++
 .../common/include/soc/gpio_eint_v2.h         | 25 +++++++
 src/soc/mediatek/mt8196/Makefile.mk           |  3 +-
 src/soc/mediatek/mt8196/gpio_eint.c           | 72 ++-----------------
 4 files changed, 87 insertions(+), 68 deletions(-)
 create mode 100644 src/soc/mediatek/common/gpio_eint_v2.c
 create mode 100644 src/soc/mediatek/common/include/soc/gpio_eint_v2.h

diff --git a/src/soc/mediatek/common/gpio_eint_v2.c b/src/soc/mediatek/common/gpio_eint_v2.c
new file mode 100644
index 0000000000..5e848fe279
--- /dev/null
+++ b/src/soc/mediatek/common/gpio_eint_v2.c
@@ -0,0 +1,55 @@
+/* SPDX-License-Identifier: GPL-2.0-only OR MIT */
+
+#include <console/console.h>
+#include <soc/addressmap.h>
+#include <soc/gpio.h>
+#include <soc/gpio_eint_v2.h>
+
+void gpio_calc_eint_pos_bit(gpio_t gpio, u32 *pos, u32 *bit)
+{
+	uint32_t idx = gpio.id;
+
+	*pos = 0;
+	*bit = 0;
+
+	if (idx >= eint_data_len)
+		return;
+
+	uint8_t index = eint_data[idx].index;
+
+	*pos = index / MAX_EINT_REG_BITS;
+	*bit = index % MAX_EINT_REG_BITS;
+}
+
+struct eint_regs *gpio_get_eint_reg(gpio_t gpio)
+{
+	uint32_t idx = gpio.id;
+	uintptr_t addr;
+
+	if (idx >= eint_data_len)
+		return NULL;
+
+	switch (eint_data[idx].instance) {
+	case EINT_E:
+		addr = EINT_E_BASE;
+		break;
+	case EINT_S:
+		addr = EINT_S_BASE;
+		break;
+	case EINT_W:
+		addr = EINT_W_BASE;
+		break;
+	case EINT_N:
+		addr = EINT_N_BASE;
+		break;
+	case EINT_C:
+		addr = EINT_C_BASE;
+		break;
+	default:
+		printk(BIOS_ERR, "%s: Failed to look up a valid EINT base for %d\n",
+		       __func__, idx);
+		return NULL;
+	}
+
+	return (void *)addr;
+}
diff --git a/src/soc/mediatek/common/include/soc/gpio_eint_v2.h b/src/soc/mediatek/common/include/soc/gpio_eint_v2.h
new file mode 100644
index 0000000000..6f4acc61e9
--- /dev/null
+++ b/src/soc/mediatek/common/include/soc/gpio_eint_v2.h
@@ -0,0 +1,25 @@
+/* SPDX-License-Identifier: GPL-2.0-only OR MIT */
+
+#ifndef __SOC_MEDIATEK_COMMON_INCLUDE_SOC_GPIO_EINT_V2_H__
+#define __SOC_MEDIATEK_COMMON_INCLUDE_SOC_GPIO_EINT_V2_H__
+
+#include <stdint.h>
+
+enum {
+	EINT_INVALID = 0,
+	EINT_E,
+	EINT_S,
+	EINT_W,
+	EINT_N,
+	EINT_C,
+};
+
+struct eint_info {
+	uint8_t instance;
+	uint8_t index;
+};
+
+extern const struct eint_info eint_data[];
+extern const size_t eint_data_len;
+
+#endif /* __SOC_MEDIATEK_COMMON_INCLUDE_SOC_GPIO_EINT_V2_H__ */
diff --git a/src/soc/mediatek/mt8196/Makefile.mk b/src/soc/mediatek/mt8196/Makefile.mk
index 85b670afb3..1793104d42 100644
--- a/src/soc/mediatek/mt8196/Makefile.mk
+++ b/src/soc/mediatek/mt8196/Makefile.mk
@@ -3,7 +3,8 @@
 ifeq ($(CONFIG_SOC_MEDIATEK_MT8196),y)
 
 all-y += ../common/flash_controller.c
-all-y += ../common/gpio.c ../common/gpio_op.c gpio.c gpio_eint.c
+all-y += ../common/gpio.c ../common/gpio_op.c gpio.c
+all-y += ../common/gpio_eint_v2.c gpio_eint.c
 all-y += ../common/i2c.c i2c.c
 all-y += ../common/pll.c pll.c
 all-$(CONFIG_SPI_FLASH) += ../common/spi.c spi.c
diff --git a/src/soc/mediatek/mt8196/gpio_eint.c b/src/soc/mediatek/mt8196/gpio_eint.c
index f24860d128..9263e9e576 100644
--- a/src/soc/mediatek/mt8196/gpio_eint.c
+++ b/src/soc/mediatek/mt8196/gpio_eint.c
@@ -1,29 +1,14 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
+/* SPDX-License-Identifier: GPL-2.0-only OR MIT */
 
 /*
  * This file is created based on MT8196_EINT_Datasheet
  * Chapter number: 1
  */
 
-#include <console/console.h>
-#include <soc/addressmap.h>
-#include <soc/gpio.h>
+#include <commonlib/bsd/helpers.h>
+#include <soc/gpio_eint_v2.h>
 
-enum {
-	EINT_INVALID = 0,
-	EINT_E,
-	EINT_S,
-	EINT_W,
-	EINT_N,
-	EINT_C,
-};
-
-struct eint_info {
-	uint8_t instance;
-	uint8_t index;
-};
-
-static struct eint_info eint_data[] = {
+const struct eint_info eint_data[] = {
 	/* instance, index */
 	[0] = { EINT_W, 0 },
 	[1] = { EINT_W, 1 },
@@ -258,51 +243,4 @@ static struct eint_info eint_data[] = {
 };
 _Static_assert(ARRAY_SIZE(eint_data) == 293, "Incorrect eint_data size");
 
-void gpio_calc_eint_pos_bit(gpio_t gpio, u32 *pos, u32 *bit)
-{
-	uint32_t idx = gpio.id;
-
-	*pos = 0;
-	*bit = 0;
-
-	if (idx >= ARRAY_SIZE(eint_data))
-		return;
-
-	uint8_t index = eint_data[idx].index;
-
-	*pos = index / MAX_EINT_REG_BITS;
-	*bit = index % MAX_EINT_REG_BITS;
-}
-
-struct eint_regs *gpio_get_eint_reg(gpio_t gpio)
-{
-	uint32_t idx = gpio.id;
-	uintptr_t addr;
-
-	if (idx >= ARRAY_SIZE(eint_data))
-		return NULL;
-
-	switch (eint_data[idx].instance) {
-	case EINT_E:
-		addr = EINT_E_BASE;
-		break;
-	case EINT_S:
-		addr = EINT_S_BASE;
-		break;
-	case EINT_W:
-		addr = EINT_W_BASE;
-		break;
-	case EINT_N:
-		addr = EINT_N_BASE;
-		break;
-	case EINT_C:
-		addr = EINT_C_BASE;
-		break;
-	default:
-		printk(BIOS_ERR, "%s: Failed to look up a valid EINT base for %d\n",
-		       __func__, idx);
-		return NULL;
-	}
-
-	return (void *)addr;
-}
+const size_t eint_data_len = ARRAY_SIZE(eint_data);

From ac80241fc9a1f71423c3cf1b25ce66c958105ba6 Mon Sep 17 00:00:00 2001
From: Vince Liu <vince-wl.liu@mediatek.corp-partner.google.com>
Date: Wed, 19 Feb 2025 13:26:12 +0800
Subject: [PATCH 0166/3886] soc/mediatek/mt8189: Reduce bootblock size by
 separating SPI NOR GPIOs

In the bootblock stage, only SPI NOR related GPIOs are used. To optimize the code size, separate the SPI NOR GPIO driving information. This modification reduces the bootblock code size by 1KB.

BUG=b:379008996
BRANCH=none
TEST=booted successfully

Signed-off-by: Vince Liu <vince-wl.liu@mediatek.corp-partner.google.com>
Change-Id: If7e8e5c7db59b5f181db14f6e66df2f333dbb6d4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86538
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
---
 src/soc/mediatek/mt8189/gpio.c | 42 ++++++++++++++++++++++++++++++----
 1 file changed, 37 insertions(+), 5 deletions(-)

diff --git a/src/soc/mediatek/mt8189/gpio.c b/src/soc/mediatek/mt8189/gpio.c
index 27179c38e2..dde8d14ad5 100644
--- a/src/soc/mediatek/mt8189/gpio.c
+++ b/src/soc/mediatek/mt8189/gpio.c
@@ -8,6 +8,26 @@
 #include <device/mmio.h>
 #include <gpio.h>
 
+#define SPI_NOR_GPIO_BASE	150
+
+enum {
+	SPI_NOR_CK = 0,
+	SPI_NOR_CS = 1,
+	SPI_NOR_IO0 = 2,
+	SPI_NOR_IO1 = 3,
+	SPI_NOR_IO2 = 4,
+	SPI_NOR_IO3 = 5,
+};
+
+static const struct gpio_drv_info bootblock_gpio_driving_info[] = {
+	[SPI_NOR_CK] = { 0x10, 12, 3, },
+	[SPI_NOR_CS] = { 0x10, 27, 3, },
+	[SPI_NOR_IO0] = { 0x10, 15, 3, },
+	[SPI_NOR_IO1] = { 0x10, 18, 3, },
+	[SPI_NOR_IO2] = { 0x10, 21, 3, },
+	[SPI_NOR_IO3] = { 0x10, 24, 3, },
+};
+
 static const struct gpio_drv_info gpio_driving_info[] = {
 	[0] = { 0x10, 15, 3, },
 	[1] = { 0x10, 9, 3, },
@@ -261,14 +281,26 @@ void *gpio_find_reg_addr(gpio_t gpio)
 
 const struct gpio_drv_info *get_gpio_driving_info(uint32_t raw_id)
 {
-	if (raw_id >= ARRAY_SIZE(gpio_driving_info))
-		return NULL;
-	return &gpio_driving_info[raw_id];
+	if (ENV_BOOTBLOCK) {
+		uint32_t id = raw_id - SPI_NOR_GPIO_BASE;
+
+		if (id >= ARRAY_SIZE(bootblock_gpio_driving_info))
+			return NULL;
+		return &bootblock_gpio_driving_info[id];
+	} else {
+		if (raw_id >= ARRAY_SIZE(gpio_driving_info))
+			return NULL;
+		return &gpio_driving_info[raw_id];
+	}
 }
 
 const struct gpio_drv_info *get_gpio_driving_adv_info(uint32_t raw_id)
 {
-	if (raw_id >= ARRAY_SIZE(gpio_driving_adv_info))
+	if (ENV_BOOTBLOCK) {
 		return NULL;
-	return &gpio_driving_adv_info[raw_id];
+	} else {
+		if (raw_id >= ARRAY_SIZE(gpio_driving_adv_info))
+			return NULL;
+		return &gpio_driving_adv_info[raw_id];
+	}
 }

From d0c6ff5f265851386feda73e9da14e2c00360eb4 Mon Sep 17 00:00:00 2001
From: Nicholas Chin <nic.c3.14@gmail.com>
Date: Fri, 16 Dec 2022 08:29:22 -0700
Subject: [PATCH 0167/3886] mb/lenovo: Add ThinkCentre M900 (Skylake/LGA 1151)

The mainboard is marked IQ1X0MS, though it is also known as the MS-7988.
The Small Form Factor version was used for this port, though the Mini
Tower seems to use the exact same board. Other systems such as the
ThinkCentre M800, ThinkStation P310, ThinkStation P320, and IdeaCentre
700-25ISH appear to use the same PCB with different configurations of
components.
All the code in this port was originally copied from the Asrock H110M
and then modified to match the actual configuration of the M900. The VBT
was extracted using `intelvbttool -l -v data.vbt` while running version
FWKTBFA of the vendor firmware.

Working:
- Boots to Linux with SeaBIOS 1.16.3
- Boots to Linux with EDK2 (MrChromebox uefipayload_202408)
- Display Ports
- VGA port
- PCIe slots
- Console over serial port
- Front and rear USB 3.0 ports and internal USB2.0 headers
- Front and rear audio jacks
- Internal speaker
- SATA ports 1-4 (5 and 6 are not populated on the M900)
- Hardware monitoring via nct6683 kernel module
- Gigabit Ethernet
- S3 suspend/resume

Unknown/untested:
- M.2 E-key slot
- Parallel port header
- PS/2 Mouse/Keyboard via KB_MS1 header
- TPM

Change-Id: I4e70c9f42c19f130a00170b32ae74b61f0483a22
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74187
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
---
 src/mainboard/lenovo/m900/Kconfig           |  36 +++
 src/mainboard/lenovo/m900/Kconfig.name      |   4 +
 src/mainboard/lenovo/m900/Makefile.mk       |   6 +
 src/mainboard/lenovo/m900/acpi/ec.asl       |   3 +
 src/mainboard/lenovo/m900/acpi/superio.asl  |   3 +
 src/mainboard/lenovo/m900/board_info.txt    |   6 +
 src/mainboard/lenovo/m900/bootblock.c       |  53 +++++
 src/mainboard/lenovo/m900/cmos.default      |   3 +
 src/mainboard/lenovo/m900/cmos.layout       |  57 +++++
 src/mainboard/lenovo/m900/data.vbt          | Bin 0 -> 3834 bytes
 src/mainboard/lenovo/m900/devicetree.cb     | 188 +++++++++++++++
 src/mainboard/lenovo/m900/dsdt.asl          |  25 ++
 src/mainboard/lenovo/m900/gma-mainboard.ads |  19 ++
 src/mainboard/lenovo/m900/gpio.h            | 244 ++++++++++++++++++++
 src/mainboard/lenovo/m900/hda_verb.c        |  32 +++
 src/mainboard/lenovo/m900/ramstage.c        |  13 ++
 src/mainboard/lenovo/m900/romstage.c        |  39 ++++
 17 files changed, 731 insertions(+)
 create mode 100644 src/mainboard/lenovo/m900/Kconfig
 create mode 100644 src/mainboard/lenovo/m900/Kconfig.name
 create mode 100644 src/mainboard/lenovo/m900/Makefile.mk
 create mode 100644 src/mainboard/lenovo/m900/acpi/ec.asl
 create mode 100644 src/mainboard/lenovo/m900/acpi/superio.asl
 create mode 100644 src/mainboard/lenovo/m900/board_info.txt
 create mode 100644 src/mainboard/lenovo/m900/bootblock.c
 create mode 100644 src/mainboard/lenovo/m900/cmos.default
 create mode 100644 src/mainboard/lenovo/m900/cmos.layout
 create mode 100644 src/mainboard/lenovo/m900/data.vbt
 create mode 100644 src/mainboard/lenovo/m900/devicetree.cb
 create mode 100644 src/mainboard/lenovo/m900/dsdt.asl
 create mode 100644 src/mainboard/lenovo/m900/gma-mainboard.ads
 create mode 100644 src/mainboard/lenovo/m900/gpio.h
 create mode 100644 src/mainboard/lenovo/m900/hda_verb.c
 create mode 100644 src/mainboard/lenovo/m900/ramstage.c
 create mode 100644 src/mainboard/lenovo/m900/romstage.c

diff --git a/src/mainboard/lenovo/m900/Kconfig b/src/mainboard/lenovo/m900/Kconfig
new file mode 100644
index 0000000000..882f3131c7
--- /dev/null
+++ b/src/mainboard/lenovo/m900/Kconfig
@@ -0,0 +1,36 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
+if BOARD_LENOVO_M900
+
+config BOARD_SPECIFIC_OPTIONS
+	def_bool y
+	select BOARD_ROMSIZE_KB_16384
+	select HAVE_ACPI_RESUME
+	select HAVE_ACPI_TABLES
+	select HAVE_CMOS_DEFAULT
+	select HAVE_OPTION_TABLE
+	select INTEL_GMA_HAVE_VBT
+	select INTEL_INT15
+	select MAINBOARD_HAS_LIBGFXINIT
+	select MAINBOARD_HAS_TPM1
+	select MAINBOARD_USES_IFD_GBE_REGION
+	select MEMORY_MAPPED_TPM
+	select SKYLAKE_SOC_PCH_H
+	select SOC_INTEL_COMMON_BLOCK_HDA_VERB
+	select SOC_INTEL_SKYLAKE
+	# Actual chip is NCT6685
+	select SUPERIO_NUVOTON_NCT6687D
+
+config DIMM_SPD_SIZE
+	default 512 # DDR4
+
+config DISABLE_HECI1_AT_PRE_BOOT
+	default y
+
+config MAINBOARD_DIR
+	default "lenovo/m900"
+
+config MAINBOARD_PART_NUMBER
+	default "M900"
+
+endif
diff --git a/src/mainboard/lenovo/m900/Kconfig.name b/src/mainboard/lenovo/m900/Kconfig.name
new file mode 100644
index 0000000000..92481401d4
--- /dev/null
+++ b/src/mainboard/lenovo/m900/Kconfig.name
@@ -0,0 +1,4 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
+config BOARD_LENOVO_M900
+	bool "ThinkCentre M900"
diff --git a/src/mainboard/lenovo/m900/Makefile.mk b/src/mainboard/lenovo/m900/Makefile.mk
new file mode 100644
index 0000000000..ef44a4c074
--- /dev/null
+++ b/src/mainboard/lenovo/m900/Makefile.mk
@@ -0,0 +1,6 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
+bootblock-y += bootblock.c
+
+ramstage-y += ramstage.c
+ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads
diff --git a/src/mainboard/lenovo/m900/acpi/ec.asl b/src/mainboard/lenovo/m900/acpi/ec.asl
new file mode 100644
index 0000000000..16990d45f4
--- /dev/null
+++ b/src/mainboard/lenovo/m900/acpi/ec.asl
@@ -0,0 +1,3 @@
+/* SPDX-License-Identifier: CC-PDDC */
+
+/* Please update the license if adding licensable material. */
diff --git a/src/mainboard/lenovo/m900/acpi/superio.asl b/src/mainboard/lenovo/m900/acpi/superio.asl
new file mode 100644
index 0000000000..16990d45f4
--- /dev/null
+++ b/src/mainboard/lenovo/m900/acpi/superio.asl
@@ -0,0 +1,3 @@
+/* SPDX-License-Identifier: CC-PDDC */
+
+/* Please update the license if adding licensable material. */
diff --git a/src/mainboard/lenovo/m900/board_info.txt b/src/mainboard/lenovo/m900/board_info.txt
new file mode 100644
index 0000000000..a19aea3a9a
--- /dev/null
+++ b/src/mainboard/lenovo/m900/board_info.txt
@@ -0,0 +1,6 @@
+Category: desktop
+ROM package: SOIC-8
+ROM protocol: SPI
+ROM socketed: n
+Flashrom support: y
+Release year: 2015
diff --git a/src/mainboard/lenovo/m900/bootblock.c b/src/mainboard/lenovo/m900/bootblock.c
new file mode 100644
index 0000000000..8afe6b36ec
--- /dev/null
+++ b/src/mainboard/lenovo/m900/bootblock.c
@@ -0,0 +1,53 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <bootblock_common.h>
+#include <device/pnp_ops.h>
+#include <superio/nuvoton/common/nuvoton.h>
+#include <superio/nuvoton/nct6687d/nct6687d.h>
+
+#define GLOBAL_DEV PNP_DEV(0x2e, 0)
+/* Change to NCT6687D_SP1 to use COM2 header */
+#define SERIAL_DEV PNP_DEV(0x2e, NCT6687D_SP2)
+#define POWER_DEV  PNP_DEV(0x2e, NCT6687D_SLEEP_PWR)
+
+void bootblock_mainboard_early_init(void)
+{
+	nuvoton_pnp_enter_conf_state(GLOBAL_DEV);
+
+	/*
+	 * Replicate non-default vendor settings (mostly multi-function pin
+	 * selection settings) in the global LDN. It seems like some bits are
+	 * set to non-default values before coreboot configures them; possibly
+	 * by the MCU firmware. Comments provided for notable settings.
+	 */
+	pnp_write_config(GLOBAL_DEV, 0x13, 0x0c);
+	/* Pins 121, 122 as TACHPWM */
+	pnp_write_config(GLOBAL_DEV, 0x15, 0xf0);
+	/* Pin 125 as TACHPWM */
+	pnp_write_config(GLOBAL_DEV, 0x1a, 0x07);
+	pnp_write_config(GLOBAL_DEV, 0x1b, 0xf0);
+	pnp_write_config(GLOBAL_DEV, 0x1d, 0x08);
+	/* Pins 95, 98, 124 as TACHPWM */
+	pnp_write_config(GLOBAL_DEV, 0x1e, 0xfc);
+	/* Pins 126, 127 as TACHPWM */
+	pnp_write_config(GLOBAL_DEV, 0x1f, 0xf0);
+	pnp_write_config(GLOBAL_DEV, 0x22, 0xbc);
+	pnp_write_config(GLOBAL_DEV, 0x23, 0xdf);
+	/* Route pins 29-36 to COM A (COM2 header) */
+	pnp_write_config(GLOBAL_DEV, 0x24, 0x61);
+	pnp_write_config(GLOBAL_DEV, 0x25, 0xff);
+	/* Route pins to parallel port */
+	pnp_write_config(GLOBAL_DEV, 0x27, 0xbe);
+	pnp_write_config(GLOBAL_DEV, 0x29, 0xfd);
+	/* Route pins 7-13 to COM B (Back panel COM1) */
+	pnp_write_config(GLOBAL_DEV, 0x2a, 0xcf);
+
+	/* Configure pin for PECI */
+	pnp_set_logical_device(POWER_DEV);
+	pnp_write_config(POWER_DEV, 0xf3, 0x0c);
+
+	nuvoton_pnp_exit_conf_state(GLOBAL_DEV);
+
+	/* Back panel COM1 */
+	nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
+}
diff --git a/src/mainboard/lenovo/m900/cmos.default b/src/mainboard/lenovo/m900/cmos.default
new file mode 100644
index 0000000000..f3330e5070
--- /dev/null
+++ b/src/mainboard/lenovo/m900/cmos.default
@@ -0,0 +1,3 @@
+boot_option=Fallback
+debug_level=Debug
+power_on_after_fail=Disable
diff --git a/src/mainboard/lenovo/m900/cmos.layout b/src/mainboard/lenovo/m900/cmos.layout
new file mode 100644
index 0000000000..2c67e5aabf
--- /dev/null
+++ b/src/mainboard/lenovo/m900/cmos.layout
@@ -0,0 +1,57 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
+# -----------------------------------------------------------------
+entries
+
+#start-bit length  config config-ID	name
+
+# -----------------------------------------------------------------
+0	120	r	0	reserved_memory
+
+# -----------------------------------------------------------------
+# RTC_BOOT_BYTE (coreboot hardcoded)
+384	1	e	4	boot_option
+388	4	h	0	reboot_counter
+
+# -----------------------------------------------------------------
+# coreboot config options: console
+395	4	e	6	debug_level
+
+# coreboot config options: cpu
+400	1	e	2	hyper_threading
+
+# coreboot config options: southbridge
+409	2	e	7	power_on_after_fail
+
+# coreboot config options: bootloader
+# Used by vboot
+416	128	r	0	vbnv
+
+# coreboot config options: check sums
+984	16	h	0	check_sum
+
+# -----------------------------------------------------------------
+
+enumerations
+
+#ID	value	text
+2	0	Enable
+2	1	Disable
+4	0	Fallback
+4	1	Normal
+6	0	Emergency
+6	1	Alert
+6	2	Critical
+6	3	Error
+6	4	Warning
+6	5	Notice
+6	6	Info
+6	7	Debug
+6	8	Spew
+7	0	Disable
+7	1	Enable
+7	2	Keep
+# -----------------------------------------------------------------
+checksums
+
+checksum 392 415 984
diff --git a/src/mainboard/lenovo/m900/data.vbt b/src/mainboard/lenovo/m900/data.vbt
new file mode 100644
index 0000000000000000000000000000000000000000..37bfddfb43c614b63451ccbd2b275dd38449a081
GIT binary patch
literal 3834
zcmds3U2GIp6h5=FyEAiVww+Ev%7XO>2yKCOx`hh0#Mz&gF5S}Y52Yj~Y++YvEVTAV
zi$S|2O~eOfO^g9Uqz@(<UaU{X_yRF8RT4vD#1|9sO?cA4gFnD}?#w{{f?bJ3@l4J=
z_nbNRn|seW_ug686Y0jT)_sX^YZJPZ1`~cS8mD$KMdIyU`(xqm@cu}mJ=%&h@CbZW
zbo&}WS`b!hwPxLu@gt*|fr`#bf=$%4MiSUIc%XkEQxnUKJU==(gvn?e!v_y$1~S8a
zqnR{z_3R8I#|^N^SpPs8caI%DkQr`34o2QsyQR8r3u0}kCRA4wGHbU|e|tk+UBi~`
z0TyeDwznnYiEwwkeK)puVl3Vj?&@l4izN18va`J<9*K81#R814B|12Cbh!VyL!(#`
zt;CRNnwtr)7VRlxbZ~g68p8tv*vWlHuro7~8GbR7t`0Ch{yfND0YLD9bO8jo6@s({
z>kwiVq%1%LuNN$9am;2dI(W7U9xuT9SsMV7Lhzz(BOqJa!V6y<0$rDXHMrOL?<4@<
z_oDzFT|mKhBWJYWa*BJgQpZaMpicluD4>UTI2NMowc7Pk0Q~%&WD4kfntO2zVL`R+
zWovG;$ji0kT&KJJh1P|-<G9eeP@nY@X}LFFcJz5|kzm66QaS7tD_~Ugz^mdmSmT|6
zW(lER(%~5KN#ct>2Hz6@Kzx<>I`J)H$<LsKcop#z#5Kg*iKE1A#CwVRi2Y-5Gw;a)
zrGO|axU$5NpnKuXO30pZ?PpxO^0S=@V6IeMId2Jnq2%+D1h?~Fmq9)+@8C1A2!UcD
z#9X8nS0-#Jib+@RCP{wK>+1Quk|H%k&x32(MPA4b<?|1FPb-C8w39@+ani}+9)SGW
zfC%HjN@$b0WN3Dv@2Jb(1Aov_q{chOh4SBg6Xa*Ysw&}<#Nd*2LpV|T-|X?2=}SCL
zTxUzo(f{dobqicpvN^o+s4l10IOyf~XL;-yT9HSlva;x~)j@+6sDLtv!8%w5DM;G4
zt_;q(J!c_>nGm6P(a<?4)U5~-_{e-4Y3GOlD&Ge2sElW2<71h9CgYE?ab0G&WL&El
zTNU=Sf*HklNnyto{6H~2RoLeWUR8`g6y{^Nkr_J}+sW`SGbR{&o#98!xWL#&hQBaF
zR9Qg9I@M@WS-Xm3s_~l2-cs=s)%a3n->CSTYN#4puHjRf(WbGz8or_#CpC6j3siZ0
zS<e+ATT*0Slk%`emD}slY<WY_N&1R6&>6WnDfJVAvpqEwdp%1dOcf*4_O8Z?>@p`t
z<@FODCmk9;43<VnuLLU$>&>zg^$tQ={e<Y;?levCa)d^@aqqnfvkFdifN7aSbPIE$
zInY4f)5d+lf)K{BBdA;Y90Vcf`x^)!){I~22(Gt!PtDFj$k~4kn&qD^U=A%$Tjqi3
zkY$~pMesZKr`F>uB$CfQ-gB-4%FX7Sn+qPvoPF}rR0@g1vFhAZDp+or=;neV>CMrv
z4@EL76|#zo#_ZJ4^jbow;-j2g<m_8coAON-P!I1`PF?DlTw^9rueggKg39|8$wCm!
zDr+V+nKsKhoO_7ZgGfgQN4U?Lv=IUhf)5K=#kC+zC2@tRnNdE<j)Rz^{b)yWn_UmQ
z$nRa%o`!7M3)?nZy_;uqAwsc@05bTO-WQb?q_R+&()AKP%9#TlqC{GvIk`XCcO)~g
zyYF!3f1vP1&8LmW!M{u20KMmS&Cq|{18MUMX#NZUHZ6xYn#mZa|GYhPS*2l<@DBVW
NR!;+*xJwU3_fK;a%rXD~

literal 0
HcmV?d00001

diff --git a/src/mainboard/lenovo/m900/devicetree.cb b/src/mainboard/lenovo/m900/devicetree.cb
new file mode 100644
index 0000000000..4f96ac186e
--- /dev/null
+++ b/src/mainboard/lenovo/m900/devicetree.cb
@@ -0,0 +1,188 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
+chip soc/intel/skylake
+	register "deep_sx_config" = "DSX_EN_WAKE_PIN"
+
+	register "eist_enable" = "1"
+
+	# GPE configuration
+	# Note that GPE events called out in ASL code rely on this
+	# route. i.e. If this route changes then the affected GPE
+	# offset bits also need to be changed.
+	register "gpe0_dw0" = "GPP_G"
+	register "gpe0_dw1" = "GPP_D"
+	register "gpe0_dw2" = "GPP_E"
+
+	# Enabling SLP_S3#, SLP_S4#, SLP_SUS and SLP_A Stretch
+	# SLP_S3 Minimum Assertion Width. Values 0: 60us, 1: 1ms, 2: 50ms, 3: 2s
+	register "PmConfigSlpS3MinAssert" = "0x02"
+
+	# SLP_S4 Minimum Assertion Width. Values 0: default, 1: 1s, 2: 2s, 3: 3s, 4: 4s
+	register "PmConfigSlpS4MinAssert" = "0x04"
+
+	# SLP_SUS Minimum Assertion Width. Values 0: 0ms, 1: 500ms, 2: 1s, 3: 4s
+	register "PmConfigSlpSusMinAssert" = "0x03"
+
+	# SLP_A Minimum Assertion Width. Values 0: 0ms, 1: 4s, 2: 98ms, 3: 2s
+	register "PmConfigSlpAMinAssert" = "0x03"
+
+	# PL2 override 91W
+	register "power_limits_config" = "{
+		.tdp_pl2_override = 91,
+	}"
+
+	device domain 0 on
+		subsystemid 0x17aa 0x30bc inherit
+
+		device ref peg0 on
+			smbios_slot_desc "SlotTypePciExpressGen3" "SlotLengthOther"
+					 "PCIE16X_1" "SlotDataBusWidth16X"
+		end
+		device ref igpu on
+			register "PrimaryDisplay" = "Display_PEG"
+		end
+		device ref sa_thermal on end
+		device ref south_xhci on
+			register "usb2_ports" = "{
+				[0] = USB2_PORT_MID(OC0), /* Rear port 5 */
+				[1] = USB2_PORT_MID(OC0), /* Rear port 6 */
+				[2] = USB2_PORT_EMPTY, /* BMC slot not populated */
+				[3] = USB2_PORT_MID(OC_SKIP), /* M.2 */
+				[4] = USB2_PORT_MID(OC4), /* Front port 1 */
+				[5] = USB2_PORT_MID(OC4), /* Front port 2 */
+				[6] = USB2_PORT_MID(OC2), /* Rear port 3 */
+				[7] = USB2_PORT_MID(OC3), /* Rear port 4 */
+				[8] = USB2_PORT_MID(OC5), /* FUSB_1 Header */
+				[9] = USB2_PORT_MID(OC5), /* FUSB_1 Header */
+				[10] = USB2_PORT_MID(6), /* FUSB_2 Header */
+				[11] = USB2_PORT_MID(6), /* FUSB_2 Header */
+				[12] = USB2_PORT_MID(OC1), /* Rear port 7 */
+				[13] = USB2_PORT_MID(OC1), /* Rear port 8 */
+			}"
+
+			register "usb3_ports" = "{
+				[0] = USB3_PORT_DEFAULT(OC0), /* Rear port 5 */
+				[1] = USB3_PORT_DEFAULT(OC0), /* Rear port 6 */
+				[2] = USB3_PORT_DEFAULT(OC2), /* Rear port 3 */
+				[3] = USB3_PORT_DEFAULT(OC3), /* Rear port 4 */
+				[4] = USB3_PORT_DEFAULT(OC4), /* Front port 1 */
+				[5] = USB3_PORT_DEFAULT(OC4), /* Front port 2 */
+				[6] = USB3_PORT_DEFAULT(OC1), /* Rear port 7 */
+				[7] = USB3_PORT_DEFAULT(OC1), /* Rear port 8 */
+				[8] = USB3_PORT_EMPTY, /* HSIO used for PCIe */
+				[9] = USB3_PORT_EMPTY, /* HSIO used for PCIe */
+			}"
+		end
+		device ref thermal on end
+		device ref heci1 on end
+		device ref sata on
+			register "SataSalpSupport" = "true"
+			register "SataPortsEnable" = "{
+				[0] = true,
+				[1] = true,
+				[2] = true,
+				[3] = true,
+			}"
+		end
+		device ref pcie_rp5 on
+			register "PcieRpEnable[4]"			= "true"
+			register "PcieRpClkReqSupport[4]"		= "false"
+			register "PcieRpAdvancedErrorReporting[4]"	= "true"
+			register "PcieRpLtrEnable[4]"			= "true"
+			register "PcieRpClkSrcNumber[4]"		= "1"
+			register "PcieRpHotPlug[4]"			= "true"
+
+			smbios_slot_desc "SlotTypePciExpressGen3" "SlotLengthOther"
+					 "PCIE1X_1" "SlotDataBusWidth1X"
+		end
+		device ref pcie_rp7 on # M.2 E-key
+			register "PcieRpEnable[6]"			= "true"
+			register "PcieRpClkReqSupport[6]"		= "true"
+			register "PcieRpClkReqNumber[6]"		= "4"
+			register "PcieRpAdvancedErrorReporting[6]"	= "true"
+			register "PcieRpLtrEnable[6]"			= "true"
+			register "PcieRpClkSrcNumber[6]"		= "7"
+			register "PcieRpHotPlug[6]"			= "true"
+
+			smbios_slot_desc "SlotTypeM2Socket1_SD" "SlotLengthOther"
+					 "M_2" "SlotDataBusWidth1X"
+		end
+		device ref pcie_rp9 on
+			register "PcieRpEnable[8]"			= "true"
+			register "PcieRpClkReqSupport[8]"		= "false"
+			register "PcieRpAdvancedErrorReporting[8]"	= "true"
+			register "PcieRpLtrEnable[8]"			= "true"
+			register "PcieRpClkSrcNumber[8]"		= "2"
+			register "PcieRpHotPlug[8]"			= "true"
+
+			smbios_slot_desc "SlotTypePciExpressGen3X16" "SlotLengthOther"
+					 "PCIE4X_1" "SlotDataBusWidth4X"
+		end
+		device ref lpc_espi on
+			register "gen1_dec" = "0x00fc0201"
+			register "gen2_dec" = "0x003c0a01"
+			register "gen3_dec" = "0x00040069"
+			register "gen4_dec" = "0x000c0081"
+			register "serirq_mode" = "SERIRQ_CONTINUOUS"
+
+			# Actually a NCT6685D, but the 6687D seems similar enough
+			chip superio/nuvoton/nct6687d
+				device pnp 2e.1 on		# Parallel port
+					io 0x60 = 0x278
+					irq 0x70 = 7
+					drq 0x74 = 3
+				end
+				device pnp 2e.2 on		# COM1 - optional module
+					io 0x60 = 0x2f8
+					irq 0x70 = 3
+				end
+				device pnp 2e.3 on		# COM2, IR
+					io 0x60 = 0x3f8
+					irq 0x70 = 4
+				end
+				device pnp 2e.5 on		# Keyboard
+					io 0x60 = 0x60
+					io 0x62 = 0x64
+					irq 0x70 = 1
+					irq 0x72 = 12
+				end
+				device pnp 2e.6 off end		# CIR
+				device pnp 2e.7 off end		# GPIO0-7
+				device pnp 2e.8 off end		# P80 UART
+				device pnp 2e.9 off end		# GPIO8-9, GPIO1-8 AF
+				device pnp 2e.a on		# ACPI
+					io 0x60 = 0xa10
+					irq 0xe7 = 0x0f
+					irq 0xe8 = 0xe0
+					irq 0xec = 0x00
+					irq 0xee = 0xff
+				end
+				device pnp 2e.b on		# EC
+					io 0x60 = 0xa20
+				end
+				device pnp 2e.c off end		# RTC
+				device pnp 2e.d off end		# Deep Sleep
+				device pnp 2e.e on		# TACH/PWM assignment
+					# Pin 122 TACHIN0, Pin 121 PWMOUT0 (CPU Fan)
+					irq 0xe1 = 0x80
+					# Pin 98 TACHIN2, Pin 95 PWMOUT2 (AUX1 Fan)
+					irq 0xe2 = 0xa2
+					# Pin 125 TACHIN3, Pin 124 PWMOUT3 (AUX2 Fan)
+					irq 0xe3 = 0xb3
+					irq 0xe4 = 0x10 # Pin 126 PWMOUT1 (SYS Fan)
+					irq 0xe5 = 0x09 # Pin 127 TACHIN1 (SYS Fan)
+				end
+				device pnp 2e.f off end		# Function register
+			end
+			chip drivers/pc80/tpm
+				device pnp 0c31.0 on end
+			end
+		end
+		device ref hda on
+			register "PchHdaVcType" = "Vc1"
+		end
+		device ref smbus on end
+		device ref fast_spi on end
+		device ref gbe on end
+	end
+end
diff --git a/src/mainboard/lenovo/m900/dsdt.asl b/src/mainboard/lenovo/m900/dsdt.asl
new file mode 100644
index 0000000000..dda17a53a8
--- /dev/null
+++ b/src/mainboard/lenovo/m900/dsdt.asl
@@ -0,0 +1,25 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <acpi/acpi.h>
+DefinitionBlock(
+	"dsdt.aml",
+	"DSDT",
+	ACPI_DSDT_REV_2,
+	OEM_ID,
+	ACPI_TABLE_CREATOR,
+	0x20110725
+)
+{
+	#include <acpi/dsdt_top.asl>
+	#include <soc/intel/common/block/acpi/acpi/platform.asl>
+	#include <soc/intel/common/block/acpi/acpi/globalnvs.asl>
+	#include <cpu/intel/common/acpi/cpu.asl>
+
+	Device (\_SB.PCI0)
+	{
+		#include <soc/intel/skylake/acpi/systemagent.asl>
+		#include <soc/intel/skylake/acpi/pch.asl>
+	}
+
+	#include <southbridge/intel/common/acpi/sleepstates.asl>
+}
diff --git a/src/mainboard/lenovo/m900/gma-mainboard.ads b/src/mainboard/lenovo/m900/gma-mainboard.ads
new file mode 100644
index 0000000000..dd45ad4576
--- /dev/null
+++ b/src/mainboard/lenovo/m900/gma-mainboard.ads
@@ -0,0 +1,19 @@
+-- SPDX-License-Identifier: GPL-2.0-or-later
+
+with HW.GFX.GMA;
+with HW.GFX.GMA.Display_Probing;
+
+use HW.GFX.GMA;
+use HW.GFX.GMA.Display_Probing;
+
+private package GMA.Mainboard is
+
+	ports : constant Port_List :=
+		(DP1, -- mainboard VGA port
+		 DP2, -- DP++ port 1
+		 DP3, -- DP++ port 2
+		 HDMI2, -- DP++ port 1
+		 HDMI3, -- DP++ port 2
+		 others => Disabled);
+
+end GMA.Mainboard;
diff --git a/src/mainboard/lenovo/m900/gpio.h b/src/mainboard/lenovo/m900/gpio.h
new file mode 100644
index 0000000000..d9146cee42
--- /dev/null
+++ b/src/mainboard/lenovo/m900/gpio.h
@@ -0,0 +1,244 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef CFG_GPIO_H
+#define CFG_GPIO_H
+
+#include <gpio.h>
+
+/* Pad configuration was generated automatically using intelp2m utility */
+static const struct pad_config gpio_table[] = {
+
+	/* ------- GPIO Community 0 ------- */
+
+	/* ------- GPIO Group GPP_A ------- */
+	PAD_CFG_NF(GPP_A0, NONE, PLTRST, NF1),
+	PAD_CFG_NF(GPP_A1, UP_20K, PLTRST, NF1),
+	PAD_CFG_NF(GPP_A2, UP_20K, PLTRST, NF1),
+	PAD_CFG_NF(GPP_A3, UP_20K, PLTRST, NF1),
+	PAD_CFG_NF(GPP_A4, UP_20K, PLTRST, NF1),
+	PAD_CFG_NF(GPP_A5, NONE, PLTRST, NF1),
+	PAD_CFG_NF(GPP_A6, NONE, PLTRST, NF1),
+	PAD_CFG_NF(GPP_A7, NONE, PLTRST, NF1),
+	PAD_CFG_NF(GPP_A8, NONE, PLTRST, NF1),
+	PAD_CFG_NF(GPP_A9, DN_20K, PLTRST, NF1),
+	PAD_CFG_NF(GPP_A10, DN_20K, PLTRST, NF1),
+	PAD_CFG_NF(GPP_A11, NONE, PLTRST, NF1),
+	PAD_CFG_NF(GPP_A12, NONE, PLTRST, NF1),
+	PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_A14, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_A15, UP_20K, DEEP, NF1),
+	PAD_CFG_TERM_GPO(GPP_A16, 0, UP_20K, DEEP),
+	PAD_CFG_GPO(GPP_A17, 1, PLTRST),
+	PAD_CFG_GPO(GPP_A18, 0, PLTRST),
+	PAD_CFG_TERM_GPO(GPP_A19, 0, UP_20K, DEEP),
+	PAD_CFG_GPO(GPP_A20, 0, PLTRST),
+	PAD_CFG_GPI_TRIG_OWN(GPP_A21, NONE, PLTRST, OFF, ACPI),
+	PAD_CFG_GPI_TRIG_OWN(GPP_A22, NONE, PLTRST, OFF, ACPI),
+	PAD_CFG_GPI_TRIG_OWN(GPP_A23, NONE, PLTRST, OFF, ACPI),
+
+	/* ------- GPIO Group GPP_B ------- */
+	PAD_CFG_GPO(GPP_B0, 0, PLTRST),
+	PAD_CFG_GPO(GPP_B1, 0, PLTRST),
+	PAD_CFG_NF(GPP_B2, NONE, PLTRST, NF1),
+	PAD_CFG_GPO(GPP_B3, 0, PLTRST),
+	PAD_CFG_GPO(GPP_B4, 0, PLTRST),
+	PAD_CFG_GPI_TRIG_OWN(GPP_B5, NONE, PLTRST, OFF, ACPI),
+	PAD_CFG_GPO(GPP_B6, 0, PLTRST),
+	PAD_CFG_GPI_TRIG_OWN(GPP_B7, NONE, PLTRST, OFF, ACPI),
+	PAD_CFG_GPI_TRIG_OWN(GPP_B8, NONE, PLTRST, OFF, ACPI),
+	PAD_CFG_GPO(GPP_B9, 0, PLTRST),
+	PAD_CFG_NF(GPP_B10, NONE, PLTRST, NF1),
+	PAD_CFG_GPO(GPP_B11, 0, PLTRST),
+	PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_B14, DN_20K, PLTRST, NF1),
+	PAD_CFG_GPO(GPP_B15, 0, PLTRST),
+	PAD_CFG_GPO(GPP_B16, 0, PLTRST),
+	PAD_CFG_GPO(GPP_B17, 0, PLTRST),
+	PAD_CFG_NF(GPP_B18, NONE, PLTRST, NF1),
+	PAD_CFG_GPO(GPP_B19, 0, PLTRST),
+	PAD_CFG_GPI_DUAL_ROUTE(GPP_B20, NONE, PLTRST, OFF, NONE, NMI, SMI),
+	PAD_CFG_GPO(GPP_B21, 0, PLTRST),
+	PAD_CFG_NF(GPP_B22, NONE, PLTRST, NF1),
+	PAD_CFG_NF(GPP_B23, DN_20K, PLTRST, NF1),
+
+	/* ------- GPIO Community 1 ------- */
+
+	/* ------- GPIO Group GPP_C ------- */
+	PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_C2, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_C5, NONE, PLTRST, NF1),
+	PAD_CFG_NF(GPP_C6, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_C7, NONE, DEEP, NF1),
+	PAD_CFG_GPI_TRIG_OWN(GPP_C8, NONE, PLTRST, OFF, ACPI),
+	PAD_CFG_GPO(GPP_C9, 0, PLTRST),
+	PAD_CFG_GPO(GPP_C10, 0, PLTRST),
+	PAD_CFG_GPI_TRIG_OWN(GPP_C11, NONE, PLTRST, OFF, ACPI),
+	PAD_CFG_GPO(GPP_C12, 1, PLTRST),
+	PAD_CFG_GPO(GPP_C13, 1, PLTRST),
+	PAD_CFG_GPI_TRIG_OWN(GPP_C14, NONE, PLTRST, OFF, ACPI),
+	PAD_CFG_GPO(GPP_C15, 1, PLTRST),
+	PAD_CFG_GPO(GPP_C16, 0, PLTRST),
+	PAD_CFG_GPO(GPP_C17, 0, PLTRST),
+	PAD_CFG_GPO(GPP_C18, 0, PLTRST),
+	PAD_CFG_GPO(GPP_C19, 0, PLTRST),
+	PAD_CFG_GPO(GPP_C20, 0, PLTRST),
+	PAD_CFG_GPO(GPP_C21, 0, PLTRST),
+	PAD_CFG_GPO(GPP_C22, 0, PLTRST),
+	PAD_CFG_GPO(GPP_C23, 0, PLTRST),
+
+	/* ------- GPIO Group GPP_D ------- */
+	PAD_CFG_GPO(GPP_D0, 0, PLTRST),
+	PAD_CFG_GPO(GPP_D1, 1, PLTRST),
+	PAD_CFG_NF(GPP_D2, NONE, PLTRST, NF1),
+	PAD_CFG_NF(GPP_D3, NONE, PLTRST, NF1),
+	PAD_CFG_GPO(GPP_D4, 1, RSMRST),
+	PAD_CFG_GPO(GPP_D5, 0, RSMRST),
+	PAD_CFG_GPO(GPP_D6, 0, RSMRST),
+	PAD_CFG_GPO(GPP_D7, 0, RSMRST),
+	PAD_CFG_GPO(GPP_D8, 0, RSMRST),
+	PAD_CFG_GPO(GPP_D9, 0, RSMRST),
+	PAD_CFG_GPO(GPP_D10, 0, RSMRST),
+	PAD_CFG_GPI_TRIG_OWN(GPP_D11, NONE, PLTRST, OFF, ACPI),
+	PAD_CFG_GPI_TRIG_OWN(GPP_D12, NONE, PLTRST, OFF, ACPI),
+	PAD_CFG_GPI_TRIG_OWN(GPP_D13, NONE, PLTRST, OFF, ACPI),
+	PAD_CFG_GPI_TRIG_OWN(GPP_D14, NONE, PLTRST, OFF, ACPI),
+	PAD_CFG_GPI_TRIG_OWN(GPP_D15, NONE, PLTRST, OFF, ACPI),
+	PAD_CFG_GPO(GPP_D16, 0, PLTRST),
+	PAD_CFG_GPI_TRIG_OWN(GPP_D17, NONE, PLTRST, LEVEL, ACPI),
+	PAD_CFG_GPI_TRIG_OWN(GPP_D18, NONE, PLTRST, OFF, ACPI),
+	PAD_CFG_GPO(GPP_D19, 0, PLTRST),
+	PAD_CFG_GPO(GPP_D20, 0, PLTRST),
+	PAD_CFG_GPO(GPP_D21, 0, PLTRST),
+	PAD_CFG_GPO(GPP_D22, 0, PLTRST),
+	PAD_CFG_GPO(GPP_D23, 0, PLTRST),
+
+	/* ------- GPIO Group GPP_E ------- */
+	PAD_CFG_TERM_GPO(GPP_E0, 0, UP_20K, PLTRST),
+	PAD_CFG_TERM_GPO(GPP_E1, 0, UP_20K, PLTRST),
+	PAD_CFG_TERM_GPO(GPP_E2, 0, UP_20K, PLTRST),
+	PAD_CFG_GPO(GPP_E3, 0, PLTRST),
+	PAD_CFG_GPO(GPP_E4, 0, PLTRST),
+	PAD_CFG_GPO(GPP_E5, 0, PLTRST),
+	PAD_CFG_GPO(GPP_E6, 0, PLTRST),
+	PAD_CFG_GPO(GPP_E7, 0, PLTRST),
+	PAD_CFG_NF(GPP_E8, NONE, PLTRST, NF1),
+	PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_E10, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_E11, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_E12, NONE, DEEP, NF1),
+
+	/* ------- GPIO Group GPP_F ------- */
+	PAD_CFG_GPO(GPP_F0, 0, PLTRST),
+	PAD_CFG_NF(GPP_F1, NONE, PLTRST, NF1),
+	PAD_CFG_NF(GPP_F2, NONE, PLTRST, NF1),
+	PAD_CFG_GPO(GPP_F3, 0, PLTRST),
+	PAD_CFG_GPO(GPP_F4, 0, PLTRST),
+	PAD_CFG_NF(GPP_F5, NONE, DEEP, NF1),
+	PAD_CFG_GPI_TRIG_OWN(GPP_F6, NONE, DEEP, OFF, ACPI),
+	PAD_CFG_GPO(GPP_F7, 0, DEEP),
+	PAD_CFG_GPO(GPP_F8, 0, PLTRST),
+	PAD_CFG_GPO(GPP_F9, 0, PLTRST),
+	PAD_CFG_NF(GPP_F10, NONE, PLTRST, NF1),
+	PAD_CFG_NF(GPP_F11, NONE, PLTRST, NF1),
+	PAD_CFG_NF(GPP_F12, NONE, PLTRST, NF1),
+	PAD_CFG_NF(GPP_F13, NONE, PLTRST, NF1),
+	PAD_CFG_GPI_APIC_HIGH(GPP_F14, NONE, DEEP),
+	PAD_CFG_NF(GPP_F15, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_F16, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_F17, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_F18, NONE, PLTRST, NF1),
+	PAD_CFG_GPO(GPP_F19, 0, PLTRST),
+	PAD_CFG_GPO(GPP_F20, 0, PLTRST),
+	PAD_CFG_GPO(GPP_F21, 0, PLTRST),
+	PAD_CFG_GPO(GPP_F22, 1, PLTRST),
+	PAD_CFG_GPO(GPP_F23, 0, PLTRST),
+
+	/* ------- GPIO Group GPP_G ------- */
+	PAD_CFG_GPI_TRIG_OWN(GPP_G0, NONE, PLTRST, OFF, ACPI),
+	PAD_CFG_GPI_TRIG_OWN(GPP_G1, NONE, PLTRST, OFF, ACPI),
+	PAD_CFG_GPI_TRIG_OWN(GPP_G2, NONE, PLTRST, OFF, ACPI),
+	PAD_CFG_GPO(GPP_G3, 0, PLTRST),
+	PAD_CFG_GPO(GPP_G4, 0, PLTRST),
+	PAD_CFG_GPO(GPP_G5, 0, PLTRST),
+	PAD_CFG_GPO(GPP_G6, 0, PLTRST),
+	PAD_CFG_GPO(GPP_G7, 0, PLTRST),
+	PAD_CFG_GPO(GPP_G8, 0, PLTRST),
+	PAD_CFG_GPO(GPP_G9, 0, PLTRST),
+	PAD_CFG_GPO(GPP_G10, 0, PLTRST),
+	PAD_CFG_GPI_TRIG_OWN(GPP_G11, NONE, PLTRST, OFF, ACPI),
+	PAD_CFG_GPI_TRIG_OWN(GPP_G12, NONE, PLTRST, OFF, ACPI),
+	PAD_CFG_GPI_TRIG_OWN(GPP_G13, NONE, PLTRST, OFF, ACPI),
+	PAD_CFG_GPI_TRIG_OWN(GPP_G14, NONE, PLTRST, OFF, ACPI),
+	PAD_CFG_GPI_TRIG_OWN(GPP_G15, NONE, PLTRST, OFF, ACPI),
+	PAD_CFG_GPI_TRIG_OWN(GPP_G16, NONE, PLTRST, OFF, ACPI),
+	PAD_CFG_GPI_TRIG_OWN(GPP_G17, NONE, PLTRST, OFF, ACPI),
+	PAD_CFG_GPO(GPP_G18, 1, PLTRST),
+	PAD_CFG_GPI_SCI(GPP_G19, NONE, PLTRST, LEVEL, INVERT),
+	PAD_CFG_GPO(GPP_G20, 0, PLTRST),
+	PAD_CFG_GPI_TRIG_OWN(GPP_G21, NONE, PLTRST, OFF, ACPI),
+	PAD_CFG_GPO(GPP_G22, 0, PLTRST),
+	PAD_CFG_GPO(GPP_G23, 0, PLTRST),
+
+	/* ------- GPIO Group GPP_H ------- */
+	PAD_CFG_GPO(GPP_H0, 0, PLTRST),
+	PAD_CFG_GPO(GPP_H1, 0, RSMRST),
+	PAD_CFG_GPI_TRIG_OWN(GPP_H2, NONE, PLTRST, OFF, ACPI),
+	PAD_CFG_GPO(GPP_H3, 0, PLTRST),
+	PAD_CFG_GPO(GPP_H4, 0, PLTRST),
+	PAD_CFG_GPO(GPP_H5, 0, PLTRST),
+	PAD_CFG_GPO(GPP_H6, 0, PLTRST),
+	PAD_CFG_GPO(GPP_H7, 0, PLTRST),
+	PAD_CFG_GPO(GPP_H8, 0, PLTRST),
+	PAD_CFG_GPO(GPP_H9, 0, PLTRST),
+	PAD_CFG_GPO(GPP_H10, 1, PLTRST),
+	PAD_CFG_GPO(GPP_H11, 1, PLTRST),
+	PAD_CFG_GPO(GPP_H12, 0, PLTRST),
+	PAD_CFG_GPO(GPP_H13, 0, PLTRST),
+	PAD_CFG_GPO(GPP_H14, 0, PLTRST),
+	PAD_CFG_GPO(GPP_H15, 1, PLTRST),
+	PAD_CFG_GPO(GPP_H16, 0, PLTRST),
+	PAD_CFG_GPO(GPP_H17, 0, PLTRST),
+	PAD_CFG_GPO(GPP_H18, 1, PLTRST),
+	PAD_CFG_GPO(GPP_H19, 0, PLTRST),
+	PAD_CFG_GPO(GPP_H20, 0, PLTRST),
+	PAD_CFG_GPO(GPP_H21, 0, PLTRST),
+	PAD_CFG_GPO(GPP_H22, 0, PLTRST),
+	PAD_CFG_GPO(GPP_H23, 0, PLTRST),
+
+	/* ------- GPIO Community 2 ------- */
+
+	/* -------- GPIO Group GPD -------- */
+	PAD_CFG_NF(GPD0, NONE, PLTRST, NF1),
+	PAD_CFG_NF(GPD1, NONE, PWROK, NF1),
+	PAD_CFG_NF(GPD2, DN_20K, PWROK, NF1),
+	PAD_CFG_NF(GPD3, UP_20K, PWROK, NF1),
+	PAD_CFG_NF(GPD4, NONE, PWROK, NF1),
+	PAD_CFG_NF(GPD5, NONE, PWROK, NF1),
+	PAD_CFG_NF(GPD6, NONE, PWROK, NF1),
+	PAD_CFG_GPO(GPD7, 0, PWROK),
+	PAD_CFG_NF(GPD8, NONE, PWROK, NF1),
+	PAD_CFG_GPO(GPD9, 0, PWROK),
+	PAD_CFG_NF(GPD10, NONE, PWROK, NF1),
+	PAD_CFG_NF(GPD11, NONE, PWROK, NF1),
+
+	/* ------- GPIO Community 3 ------- */
+
+	/* ------- GPIO Group GPP_I ------- */
+	PAD_CFG_NF(GPP_I0, NONE, PLTRST, NF1),
+	PAD_CFG_NF(GPP_I1, NONE, PLTRST, NF1),
+	PAD_CFG_NF(GPP_I2, NONE, PLTRST, NF1),
+	PAD_CFG_GPI_DUAL_ROUTE(GPP_I3, NONE, PLTRST, OFF, NONE, SMI, NMI),
+	PAD_CFG_GPI_TRIG_OWN(GPP_I4, NONE, PLTRST, OFF, ACPI),
+	PAD_CFG_GPO(GPP_I5, 0, PLTRST),
+	PAD_CFG_GPI_TRIG_OWN(GPP_I6, DN_20K, PLTRST, OFF, ACPI),
+	PAD_CFG_NF(GPP_I7, NONE, PLTRST, NF1),
+	PAD_CFG_NF(GPP_I8, DN_20K, PLTRST, NF1),
+	PAD_CFG_NF(GPP_I9, NONE, PLTRST, NF1),
+	PAD_CFG_NF(GPP_I10, DN_20K, PLTRST, NF1),
+};
+
+#endif /* CFG_GPIO_H */
diff --git a/src/mainboard/lenovo/m900/hda_verb.c b/src/mainboard/lenovo/m900/hda_verb.c
new file mode 100644
index 0000000000..e400a59e59
--- /dev/null
+++ b/src/mainboard/lenovo/m900/hda_verb.c
@@ -0,0 +1,32 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <device/azalia_device.h>
+
+const u32 cim_verb_data[] = {
+	0x10ec0662, /* Codec Vendor / Device ID: Realtek ALC662 rev3 */
+	0x17aa30bc, /* Subsystem ID */
+	12,	    /* Number of 4 dword sets */
+	AZALIA_SUBVENDOR(0, 0x17aa30bc),
+	AZALIA_PIN_CFG(0, 0x12, 0x40000000),
+	AZALIA_PIN_CFG(0, 0x14, 0x01014020),
+	AZALIA_PIN_CFG(0, 0x15, 0x99130110),
+	AZALIA_PIN_CFG(0, 0x16, AZALIA_PIN_CFG_NC(0)),
+	AZALIA_PIN_CFG(0, 0x18, 0x01a19040),
+	AZALIA_PIN_CFG(0, 0x19, 0x02a19050),
+	AZALIA_PIN_CFG(0, 0x1a, 0x0181304f),
+	AZALIA_PIN_CFG(0, 0x1b, 0x02214030),
+	AZALIA_PIN_CFG(0, 0x1c, AZALIA_PIN_CFG_NC(0)),
+	AZALIA_PIN_CFG(0, 0x1d, 0x4047c62b),
+	AZALIA_PIN_CFG(0, 0x1e, AZALIA_PIN_CFG_NC(0)),
+
+	0x80862809, /* Codec Vendor / Device ID: Intel Skylake HDMI */
+	0x80860101, /* Subsystem ID */
+	4,	    /* Number of 4 dword sets */
+	AZALIA_SUBVENDOR(2, 0x80860101),
+	AZALIA_PIN_CFG(2, 0x05, 0x58560010),
+	AZALIA_PIN_CFG(2, 0x06, 0x18560020),
+	AZALIA_PIN_CFG(2, 0x07, 0x18560030),
+};
+
+const u32 pc_beep_verbs[] = {};
+AZALIA_ARRAY_SIZES;
diff --git a/src/mainboard/lenovo/m900/ramstage.c b/src/mainboard/lenovo/m900/ramstage.c
new file mode 100644
index 0000000000..4ae8415907
--- /dev/null
+++ b/src/mainboard/lenovo/m900/ramstage.c
@@ -0,0 +1,13 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <device/device.h>
+#include "gpio.h"
+
+static void init_mainboard(void *chip_info)
+{
+	gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table));
+}
+
+struct chip_operations mainboard_ops = {
+	.init = init_mainboard,
+};
diff --git a/src/mainboard/lenovo/m900/romstage.c b/src/mainboard/lenovo/m900/romstage.c
new file mode 100644
index 0000000000..1a94d61c91
--- /dev/null
+++ b/src/mainboard/lenovo/m900/romstage.c
@@ -0,0 +1,39 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <assert.h>
+#include <soc/romstage.h>
+#include <spd_bin.h>
+#include <stdint.h>
+#include <string.h>
+
+void mainboard_memory_init_params(FSPM_UPD *mupd)
+{
+	const u16 rcomp_resistors[3] = {121, 75, 100};
+
+	const u16 rcomp_targets[5] = {50, 26, 20, 20, 26};
+
+	FSP_M_CONFIG *const mem_cfg = &mupd->FspmConfig;
+
+	struct spd_block blk = {
+		.addr_map = {0x50, 0x51, 0x52, 0x53},
+	};
+
+	mem_cfg->DqPinsInterleaved = 1;
+	mem_cfg->CaVrefConfig = 2;
+	get_spd_smbus(&blk);
+	mem_cfg->MemorySpdDataLen = blk.len;
+	mem_cfg->MemorySpdPtr00 = (uintptr_t)blk.spd_array[0];
+	mem_cfg->MemorySpdPtr01 = (uintptr_t)blk.spd_array[1];
+	mem_cfg->MemorySpdPtr10 = (uintptr_t)blk.spd_array[2];
+	mem_cfg->MemorySpdPtr11 = (uintptr_t)blk.spd_array[3];
+	dump_spd_info(&blk);
+
+	assert(sizeof(mem_cfg->RcompResistor) == sizeof(rcomp_resistors));
+	assert(sizeof(mem_cfg->RcompTarget) == sizeof(rcomp_targets));
+
+	memcpy(mem_cfg->RcompResistor, rcomp_resistors, sizeof(mem_cfg->RcompResistor));
+	memcpy(mem_cfg->RcompTarget, rcomp_targets, sizeof(mem_cfg->RcompTarget));
+
+	/* use virtual channel 1 for the dmi interface of the PCH */
+	mupd->FspmTestConfig.DmiVc1 = 1;
+}

From d46943d84917a5bf67353379acfb2ec6fd1dd208 Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Mon, 10 Feb 2025 16:19:19 +0000
Subject: [PATCH 0168/3886] mb/starlabs/starlite_adl: Reconfigure the vGPIO's
 for CNVi BT

It seems FSP will only automatically configure the vGPIO's for
CNVi Bluetooth if USB 2 Port 7 is used. On this board, USB 2
Port 9 is used, so manually confgiure the vGPIO's related to
CNVi for USB Bluetooth instead of UART.

Change-Id: I8d1c337523450de41f11fc9bfbc9b52825d7311c
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86387
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 .../starlite_adl/variants/mk_v/gpio.c         | 32 ++++++++++++-------
 1 file changed, 21 insertions(+), 11 deletions(-)

diff --git a/src/mainboard/starlabs/starlite_adl/variants/mk_v/gpio.c b/src/mainboard/starlabs/starlite_adl/variants/mk_v/gpio.c
index f7a9737aa3..8a0b804904 100644
--- a/src/mainboard/starlabs/starlite_adl/variants/mk_v/gpio.c
+++ b/src/mainboard/starlabs/starlite_adl/variants/mk_v/gpio.c
@@ -449,26 +449,36 @@ const struct pad_config gpio_table[] = {
 	/* R7:		Not Connected					*/
 	PAD_NC(GPP_R7, NONE),
 
-	/* BT_EN */
+	/* CNV_BTEN */
 	PAD_CFG_GPO(GPP_VGPIO_0, 1, DEEP),
-
-	/* CNVi BT UART0 */
+	/* CNV_BT_HOST_WAKEB */
+	PAD_NC(GPP_VGPIO_4, NONE),
+	/* CNV_BT_IF_SELECT */
+	PAD_CFG_GPO(GPP_VGPIO_5, 1, DEEP),
+	/* vCNV_BT_UART_TXD */
 	PAD_NC(GPP_VGPIO_6, NONE),
+	/* vCNV_BT_UART_RXD */
 	PAD_NC(GPP_VGPIO_7, NONE),
+	/* vCNV_BT_UART_CTS_B */
 	PAD_NC(GPP_VGPIO_8, NONE),
+	/* vCNV_BT_UART_RTS_B */
 	PAD_NC(GPP_VGPIO_9, NONE),
-
-	/* CNVi UART0 */
+	/* vUART0_TXD */
 	PAD_NC(GPP_VGPIO_18, NONE),
+	/* vUART0_RXD */
 	PAD_NC(GPP_VGPIO_19, NONE),
+	/* vUART0_CTS_B */
 	PAD_NC(GPP_VGPIO_20, NONE),
+	/* vUART0_RTS_B */
 	PAD_NC(GPP_VGPIO_21, NONE),
-
-	/* BT I2S */
-	PAD_CFG_NF(GPP_VGPIO_30, NONE, DEEP, NF3),
-	PAD_CFG_NF(GPP_VGPIO_31, NONE, DEEP, NF3),
-	PAD_CFG_NF(GPP_VGPIO_32, NONE, DEEP, NF3),
-	PAD_CFG_NF(GPP_VGPIO_33, NONE, DEEP, NF3),
+	/* BT_I2S_BCLK */
+	PAD_NC(GPP_VGPIO_30, NONE),
+	/* BT_I2S_SYNC */
+	PAD_NC(GPP_VGPIO_31, NONE),
+	/* BT_I2S_SDO */
+	PAD_NC(GPP_VGPIO_32, NONE),
+	/* BT_I2S_SDI */
+	PAD_NC(GPP_VGPIO_33, NONE),
 };
 
 const struct pad_config *variant_gpio_table(size_t *num)

From 7dd2cf2f85aef7f303ad6c466c2146613a663c56 Mon Sep 17 00:00:00 2001
From: Jakub Czapiga <czapiga@google.com>
Date: Wed, 19 Feb 2025 11:36:28 +0000
Subject: [PATCH 0169/3886] util/cbmem: Use uintN_t instead of uN int types

Replace all occurrences of u8, u16, u32 and u64 with their respective
alternatives of uint8_t. There is no need to unnecessarily compress code
by using standard types aliases.

BUG=b:391874512
TEST=Compile cbmem

Change-Id: I4fdb4a31923368342ef218144f8cb44624cd4b2a
Signed-off-by: Jakub Czapiga <czapiga@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86556
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
---
 util/cbmem/cbmem.c | 35 +++++++++++++++--------------------
 1 file changed, 15 insertions(+), 20 deletions(-)

diff --git a/util/cbmem/cbmem.c b/util/cbmem/cbmem.c
index 15b6770315..bdb6794dbf 100644
--- a/util/cbmem/cbmem.c
+++ b/util/cbmem/cbmem.c
@@ -35,13 +35,8 @@
 #include <x86intrin.h>
 #endif
 
-typedef uint8_t u8;
-typedef uint16_t u16;
-typedef uint32_t u32;
-typedef uint64_t u64;
-
 /* Return < 0 on error, 0 on success. */
-static int parse_cbtable(u64 address, size_t table_size);
+static int parse_cbtable(uint64_t address, size_t table_size);
 
 struct mapping {
 	void *virt;
@@ -178,8 +173,8 @@ static size_t mapping_size(const struct mapping *mapping)
  */
 static void *aligned_memcpy(void *dest, const void *src, size_t n)
 {
-	u8 *d = dest;
-	const volatile u8 *s = src;	/* volatile to prevent optimization */
+	uint8_t *d = dest;
+	const volatile uint8_t *s = src;	/* volatile to prevent optimization */
 
 	while ((uintptr_t)s & (sizeof(size_t) - 1)) {
 		if (n-- == 0)
@@ -353,7 +348,7 @@ static int parse_cbtable_entries(const struct mapping *table_mapping)
 }
 
 /* Return < 0 on error, 0 on success. */
-static int parse_cbtable(u64 address, size_t table_size)
+static int parse_cbtable(uint64_t address, size_t table_size)
 {
 	const void *buf;
 	struct mapping header_mapping;
@@ -441,7 +436,7 @@ static unsigned long arch_tick_frequency(void)
 	char freqs[100];
 	int  size;
 	char *endp;
-	u64 rv;
+	uint64_t rv;
 
 	const char* freq_file =
 		"/sys/devices/system/cpu/cpu0/cpufreq/cpuinfo_max_freq";
@@ -509,7 +504,7 @@ static void timestamp_set_tick_freq(unsigned long table_tick_freq_mhz)
 	debug("Timestamp tick frequency: %ld MHz\n", tick_freq_mhz);
 }
 
-static u64 arch_convert_raw_ts_entry(u64 ts)
+static uint64_t arch_convert_raw_ts_entry(uint64_t ts)
 {
 	return ts / tick_freq_mhz;
 }
@@ -518,14 +513,14 @@ static u64 arch_convert_raw_ts_entry(u64 ts)
  * Print an integer in 'normalized' form - with commas separating every three
  * decimal orders.
  */
-static void print_norm(u64 v)
+static void print_norm(uint64_t v)
 {
 	if (v >= 1000) {
 		/* print the higher order sections first */
 		print_norm(v / 1000);
-		printf(",%3.3u", (u32)(v % 1000));
+		printf(",%3.3u", (uint32_t)(v % 1000));
 	} else {
-		printf("%u", (u32)(v % 1000));
+		printf("%u", (uint32_t)(v % 1000));
 	}
 }
 
@@ -1096,9 +1091,9 @@ static void dump_tpm_log(void)
 }
 
 struct cbmem_console {
-	u32 size;
-	u32 cursor;
-	u8  body[];
+	uint32_t size;
+	uint32_t cursor;
+	uint8_t  body[];
 }  __attribute__ ((__packed__));
 
 #define CBMC_CURSOR_MASK ((1 << 28) - 1)
@@ -1828,7 +1823,7 @@ int main(int argc, char** argv)
 
 	int i;
 	size_t size_to_read = addr_cells * 4 + size_cells * 4;
-	u8 *dtbuffer = alloca(size_to_read);
+	uint8_t *dtbuffer = alloca(size_to_read);
 	if (read(fd, dtbuffer, size_to_read) < 0) {
 		perror(reg);
 		return 1;
@@ -1836,13 +1831,13 @@ int main(int argc, char** argv)
 	close(fd);
 
 	/* No variable-length byte swap function anywhere in C... how sad. */
-	u64 baseaddr = 0;
+	uint64_t baseaddr = 0;
 	for (i = 0; i < addr_cells * 4; i++) {
 		baseaddr <<= 8;
 		baseaddr |= *dtbuffer;
 		dtbuffer++;
 	}
-	u64 cb_table_size = 0;
+	uint64_t cb_table_size = 0;
 	for (i = 0; i < size_cells * 4; i++) {
 		cb_table_size <<= 8;
 		cb_table_size |= *dtbuffer;

From b63f8a1d0e28f95dc225fc8abdc787f7e397ad1c Mon Sep 17 00:00:00 2001
From: David Wu <david_wu@quanta.corp-partner.google.com>
Date: Thu, 20 Feb 2025 16:49:02 +0800
Subject: [PATCH 0170/3886] mb/google/nissa/var/dirks: Add fw_config probe for
 WIFI Type

Use fw_config to probe WIFI Type.

BUG=b:389391653
TEST=emerge-nissa coreboot

Change-Id: Iaefda61e4929d48f02ce7190e9e45d70b32b75e3
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86540
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 .../brya/variants/dirks/overridetree.cb       | 39 ++++++++++++++++---
 1 file changed, 34 insertions(+), 5 deletions(-)

diff --git a/src/mainboard/google/brya/variants/dirks/overridetree.cb b/src/mainboard/google/brya/variants/dirks/overridetree.cb
index a953b4ca76..8b7bc438fe 100644
--- a/src/mainboard/google/brya/variants/dirks/overridetree.cb
+++ b/src/mainboard/google/brya/variants/dirks/overridetree.cb
@@ -1,3 +1,15 @@
+fw_config
+	field WIFI_SAR_ID 0 0
+		option ID_0			0
+		option ID_1			1
+	end
+	field WIFI_TYPE 1 2
+		option WIFI_ALL			0
+		option WIFI_CNVI		1
+		option WIFI_PCIE		2
+	end
+end
+
 chip soc/intel/alderlake
 
 	register "sagv" = "SaGv_Enabled"
@@ -184,7 +196,10 @@ chip soc/intel/alderlake
 		device ref cnvi_wifi on
 			chip drivers/wifi/generic
 				register "enable_cnvi_ddr_rfim" = "true"
-				device generic 0 on end
+				device generic 0 on
+					probe WIFI_TYPE WIFI_CNVI
+					probe WIFI_TYPE WIFI_ALL
+				end
 			end
 		end
 		device ref i2c3 on
@@ -209,6 +224,8 @@ chip soc/intel/alderlake
 		end
 		device ref pcie_rp11 on
 			# Enable wlan PCIe 11 using clk 2
+			probe WIFI_TYPE WIFI_PCIE
+			probe WIFI_TYPE WIFI_ALL
 			register "pch_pcie_rp[PCH_RP(10)]" = "{
 				.clk_src = 2,
 				.clk_req = 2,
@@ -218,13 +235,19 @@ chip soc/intel/alderlake
 				register "wake" = "GPE0_DW1_03"
 				register "add_acpi_dma_property" = "true"
 				use usb2_port8 as bluetooth_companion
-				device pci 00.0 on end
+				device pci 00.0 on
+					probe WIFI_TYPE WIFI_PCIE
+					probe WIFI_TYPE WIFI_ALL
+				end
 			end
 			chip soc/intel/common/block/pcie/rtd3
 				register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B11)"
 				register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_H20)"
 				register "srcclk_pin" = "2"
-				device generic 0 on end
+				device generic 0 on
+					probe WIFI_TYPE WIFI_PCIE
+					probe WIFI_TYPE WIFI_ALL
+				end
 			end
 		end
 		device ref emmc on end
@@ -315,14 +338,20 @@ chip soc/intel/alderlake
 						register "type" = "UPC_TYPE_INTERNAL"
 						register "reset_gpio" =
 							"ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D4)"
-						device ref usb2_port8 on end
+						device ref usb2_port8 on
+							probe WIFI_TYPE WIFI_PCIE
+							probe WIFI_TYPE WIFI_ALL
+						end
 					end
 					chip drivers/usb/acpi
 						register "desc" = ""CNVI Bluetooth""
 						register "type" = "UPC_TYPE_INTERNAL"
 						register "reset_gpio" =
 							"ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D4)"
-						device ref usb2_port10 on end
+						device ref usb2_port10 on
+							probe WIFI_TYPE WIFI_CNVI
+							probe WIFI_TYPE WIFI_ALL
+						end
 					end
 					chip drivers/usb/acpi
 						register "desc" = ""USB3 Type-A Port A1""

From 4dd07e0355ee21fd8ab16e33409ec033e613e49c Mon Sep 17 00:00:00 2001
From: Elyes Haouas <ehaouas@noos.fr>
Date: Wed, 17 Apr 2024 17:02:31 +0200
Subject: [PATCH 0171/3886] soc/intel/common/block/cse: Drop unused symbols

SOC_INTEL_CSE_RW_A_FMAP_NAME, SOC_INTEL_CSE_RW_B_FMAP_NAME and
SOC_INTEL_CSE_RW_HASH_CBFS_NAME are not used.

Change-Id: I0639f03baf4edcf5f01d6673137dfbab1f2d4a25
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81976
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
---
 src/soc/intel/common/block/cse/Kconfig | 18 ------------------
 1 file changed, 18 deletions(-)

diff --git a/src/soc/intel/common/block/cse/Kconfig b/src/soc/intel/common/block/cse/Kconfig
index 657494a03a..bfef3d5db8 100644
--- a/src/soc/intel/common/block/cse/Kconfig
+++ b/src/soc/intel/common/block/cse/Kconfig
@@ -195,30 +195,12 @@ config SOC_INTEL_CSE_FMAP_NAME
 	help
 	 Name of CSE region in FMAP
 
-config SOC_INTEL_CSE_RW_A_FMAP_NAME
-	string "Location of CSE RW A in FMAP" if SOC_INTEL_CSE_RW_UPDATE
-	default "ME_RW_A"
-	help
-	 Name of CSE RW A region in FMAP
-
-config SOC_INTEL_CSE_RW_B_FMAP_NAME
-	string "Location of CSE RW B in FMAP" if SOC_INTEL_CSE_RW_UPDATE
-	default "ME_RW_B"
-	help
-	 Name of CSE RW B region in FMAP
-
 config SOC_INTEL_CSE_RW_CBFS_NAME
 	string "CBFS entry name for CSE RW blob" if SOC_INTEL_CSE_RW_UPDATE
 	default "me_rw"
 	help
 	 CBFS entry name for Intel CSE CBFS RW blob
 
-config SOC_INTEL_CSE_RW_HASH_CBFS_NAME
-	string "CBFS name for CSE RW hash file" if SOC_INTEL_CSE_RW_UPDATE
-	default "me_rw.hash"
-	help
-	 CBFS name for Intel CSE CBFS RW hash file
-
 config SOC_INTEL_CSE_RW_VERSION_CBFS_NAME
 	string "CBFS name for CSE RW version file" if SOC_INTEL_CSE_RW_UPDATE
 	default "me_rw.version"

From 9e6a52fb506416c817e516cea2423364cce4c616 Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Sun, 23 Feb 2025 20:00:02 +0000
Subject: [PATCH 0172/3886] mb/starlabs/byte_adl: Disconnect WLAN Sleep GPIO

This GPIO is not connected, so configure it accordingly.

Change-Id: I4b3421f1ab676599ffec6b2f46429ce937704e40
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86564
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/starlabs/byte_adl/variants/mk_ii/gpio.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/mainboard/starlabs/byte_adl/variants/mk_ii/gpio.c b/src/mainboard/starlabs/byte_adl/variants/mk_ii/gpio.c
index 6981b85fc0..a1b95d020d 100644
--- a/src/mainboard/starlabs/byte_adl/variants/mk_ii/gpio.c
+++ b/src/mainboard/starlabs/byte_adl/variants/mk_ii/gpio.c
@@ -37,7 +37,7 @@ const struct pad_config gpio_table[] = {
 	/* GPD8:	Suspend Clock					*/
 	PAD_CFG_NF(GPD8, NONE, DEEP, NF1),
 	/* GPD9:	Wireless LAN Sleep				*/
-	PAD_CFG_NF(GPD9, NONE, DEEP, NF1),
+	PAD_NC(GPD9, NONE),
 	/* GPD10:	Sleep S5					*/
 	PAD_NC(GPD10, NONE),
 	/* GPD11:	LAN PHY Enable					*/

From b84ad781f2a93f3c2e79a1bceb227b59f0d48e5a Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Sun, 23 Feb 2025 20:01:44 +0000
Subject: [PATCH 0173/3886] mb/starlabs/byte_adl: Reconfigure the vGPIO's for
 CNVi BT

Manually confgiure the vGPIO's related to CNVi for USB Bluetooth
instead of UART.

Change-Id: I7d6007e40b2edbadeb5611f6cd67df0c1e6ee8a6
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86565
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 .../starlabs/byte_adl/variants/mk_ii/gpio.c   | 32 ++++++++++++-------
 1 file changed, 21 insertions(+), 11 deletions(-)

diff --git a/src/mainboard/starlabs/byte_adl/variants/mk_ii/gpio.c b/src/mainboard/starlabs/byte_adl/variants/mk_ii/gpio.c
index a1b95d020d..71b706d270 100644
--- a/src/mainboard/starlabs/byte_adl/variants/mk_ii/gpio.c
+++ b/src/mainboard/starlabs/byte_adl/variants/mk_ii/gpio.c
@@ -451,26 +451,36 @@ const struct pad_config gpio_table[] = {
 	/* R7:		Not Connected					*/
 	PAD_NC(GPP_R7, NONE),
 
-	/* BT_EN */
+	/* CNV_BTEN */
 	PAD_CFG_GPO(GPP_VGPIO_0, 1, DEEP),
-
-	/* CNVi BT UART0 */
+	/* CNV_BT_HOST_WAKEB */
+	PAD_NC(GPP_VGPIO_4, NONE),
+	/* CNV_BT_IF_SELECT */
+	PAD_CFG_GPO(GPP_VGPIO_5, 1, DEEP),
+	/* vCNV_BT_UART_TXD */
 	PAD_NC(GPP_VGPIO_6, NONE),
+	/* vCNV_BT_UART_RXD */
 	PAD_NC(GPP_VGPIO_7, NONE),
+	/* vCNV_BT_UART_CTS_B */
 	PAD_NC(GPP_VGPIO_8, NONE),
+	/* vCNV_BT_UART_RTS_B */
 	PAD_NC(GPP_VGPIO_9, NONE),
-
-	/* CNVi UART0 */
+	/* vUART0_TXD */
 	PAD_NC(GPP_VGPIO_18, NONE),
+	/* vUART0_RXD */
 	PAD_NC(GPP_VGPIO_19, NONE),
+	/* vUART0_CTS_B */
 	PAD_NC(GPP_VGPIO_20, NONE),
+	/* vUART0_RTS_B */
 	PAD_NC(GPP_VGPIO_21, NONE),
-
-	/* BT I2S */
-	PAD_CFG_NF(GPP_VGPIO_30, NONE, DEEP, NF3),
-	PAD_CFG_NF(GPP_VGPIO_31, NONE, DEEP, NF3),
-	PAD_CFG_NF(GPP_VGPIO_32, NONE, DEEP, NF3),
-	PAD_CFG_NF(GPP_VGPIO_33, NONE, DEEP, NF3),
+	/* BT_I2S_BCLK */
+	PAD_NC(GPP_VGPIO_30, NONE),
+	/* BT_I2S_SYNC */
+	PAD_NC(GPP_VGPIO_31, NONE),
+	/* BT_I2S_SDO */
+	PAD_NC(GPP_VGPIO_32, NONE),
+	/* BT_I2S_SDI */
+	PAD_NC(GPP_VGPIO_33, NONE),
 };
 
 const struct pad_config *variant_gpio_table(size_t *num)

From d9d731d97dffd46459b8455b4c0dc73ffb684e97 Mon Sep 17 00:00:00 2001
From: Tongtong Pan <pantongtong@huaqin.corp-partner.google.com>
Date: Thu, 20 Feb 2025 19:49:33 +0800
Subject: [PATCH 0174/3886] mb/google/fatcat/var/felino: Modify the
 overridetree.cb for enable touchpad

Modify the overridetree.cb configuration and gpio.c to enable touchpad.

BUG=b:388982526
TEST=abuild -v -a -x -c max -p none -t google/fatcat -b felino

Change-Id: I47667120f098727f0d3ef05c17ea48f62b13c135
Signed-off-by: Tongtong Pan <pantongtong@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86542
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
---
 .../google/fatcat/variants/felino/gpio.c       | 10 +++++-----
 .../fatcat/variants/felino/overridetree.cb     | 18 ++++++++++--------
 2 files changed, 15 insertions(+), 13 deletions(-)

diff --git a/src/mainboard/google/fatcat/variants/felino/gpio.c b/src/mainboard/google/fatcat/variants/felino/gpio.c
index 6c75a416b6..e5ca754dea 100644
--- a/src/mainboard/google/fatcat/variants/felino/gpio.c
+++ b/src/mainboard/google/fatcat/variants/felino/gpio.c
@@ -222,10 +222,10 @@ static const struct pad_config gpio_table[] = {
 	PAD_NC(GPP_E10, NONE),
 	/* GPP_E11:     NC */
 	PAD_NC(GPP_E11, NONE),
-	/* GPP_E12:     I2C0_SOC_SCL */
-	PAD_CFG_NF(GPP_E12, NONE, DEEP, NF1),
-	/* GPP_E13:     I2C0_SOC_SDA */
-	PAD_CFG_NF(GPP_E13, NONE, DEEP, NF1),
+	/* GPP_E12:     I2C4_SOC_SCL */
+	PAD_CFG_NF(GPP_E12, NONE, DEEP, NF8),
+	/* GPP_E13:     I2C4_SOC_SDA */
+	PAD_CFG_NF(GPP_E13, NONE, DEEP, NF8),
 	/* GPP_E14:     NC */
 	PAD_NC(GPP_E14, NONE),
 	/* GPP_E15:     NC */
@@ -235,7 +235,7 @@ static const struct pad_config gpio_table[] = {
 	/* GPP_E17:     NC */
 	PAD_NC(GPP_E17, NONE),
 	/* GPP_E18:     TOUCHPAD_INT_N */
-	PAD_CFG_NF(GPP_E18, NONE, DEEP, NF3),
+	PAD_CFG_GPI_APIC(GPP_E18, NONE, PLTRST, LEVEL, NONE),
 	/* GPP_E19:     HW_ID5 */
 	PAD_CFG_GPO(GPP_E19, 1, PLTRST),
 	/* GPP_E20:     HW_ID4 */
diff --git a/src/mainboard/google/fatcat/variants/felino/overridetree.cb b/src/mainboard/google/fatcat/variants/felino/overridetree.cb
index 62b4160b74..6b4d32e0a0 100644
--- a/src/mainboard/google/fatcat/variants/felino/overridetree.cb
+++ b/src/mainboard/google/fatcat/variants/felino/overridetree.cb
@@ -70,6 +70,9 @@ chip soc/intel/pantherlake
 		},
 		.i2c[4] = {
 			.speed = I2C_SPEED_FAST,
+			.rise_time_ns = 650,
+			.fall_time_ns = 350,
+			.data_hold_time_ns = 400,
 		},
 	}"
 
@@ -231,14 +234,13 @@ chip soc/intel/pantherlake
 		end # I2C1
 
 		device ref i2c4 on
-			chip drivers/i2c/hid
-				register "generic.hid" = ""P3840""
-				register "generic.desc" = ""Synaptics TOUCHPAD""
-				register "generic.irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_E18_IRQ)"
-				register "generic.uid" = "5"
-				register "generic.detect" = "1"
-				register "hid_desc_reg_offset" = "0x20"
-				device i2c 2c on end
+			chip drivers/i2c/generic
+				register "hid" = ""ELAN0000""
+				register "desc" = ""ELAN Touchpad""
+				register "irq" = "ACPI_IRQ_WAKE_EDGE_LOW(GPP_E18_IRQ)"
+				register "wake" = "GPE0_DW2_18"
+				register "detect" = "1"
+				device i2c 0x15 on end
 			end
 		end # I2C4
 

From 9c0edfa76bfabe87f083da84c1c53734787f6a95 Mon Sep 17 00:00:00 2001
From: Elyes Haouas <ehaouas@noos.fr>
Date: Thu, 20 Feb 2025 07:53:41 +0100
Subject: [PATCH 0175/3886] libpayload/tests: Remove unused test files

Change-Id: Id2cec6a56ba5ce98832aced6fc2cfd8ebda91f02
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86536
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 payloads/libpayload/tests/Makefile        | 12 --------
 payloads/libpayload/tests/cbfs-x86-test.c | 34 -----------------------
 2 files changed, 46 deletions(-)
 delete mode 100644 payloads/libpayload/tests/Makefile
 delete mode 100644 payloads/libpayload/tests/cbfs-x86-test.c

diff --git a/payloads/libpayload/tests/Makefile b/payloads/libpayload/tests/Makefile
deleted file mode 100644
index 8c55053af7..0000000000
--- a/payloads/libpayload/tests/Makefile
+++ /dev/null
@@ -1,12 +0,0 @@
-CC=gcc -g -m32
-INCLUDES=-I. -I../include -I../include/x86
-TARGETS=cbfs-x86-test
-
-cbfs-x86-test: cbfs-x86-test.c ../arch/x86/rom_media.c ../libcbfs/ram_media.c ../libcbfs/cbfs.c
-	$(CC) -o $@ $^ $(INCLUDES)
-
-
-all: $(TARGETS)
-
-run: all
-	for i in $(TARGETS); do ./$$i; done
diff --git a/payloads/libpayload/tests/cbfs-x86-test.c b/payloads/libpayload/tests/cbfs-x86-test.c
deleted file mode 100644
index 81029656fc..0000000000
--- a/payloads/libpayload/tests/cbfs-x86-test.c
+++ /dev/null
@@ -1,34 +0,0 @@
-/* system headers */
-#include <stdlib.h>
-#include <stdio.h>
-
-/* libpayload headers */
-#include "cbfs.h"
-
-int fail(const char* str)
-{
-	fprintf(stderr, "%s", str);
-	exit(1);
-}
-
-int main(int argc, char** argv)
-{
-	FILE *cbfs = fopen("data/cbfs-x86.bin", "rb");
-	if (!cbfs) fail("could not open test file\n");
-	if (fseek(cbfs, 0, SEEK_END) != 0) fail("seek to end failed\n");
-
-	long size = ftell(cbfs);
-	if (size == -1) fail("could not determine file size\n");
-	if (fseek(cbfs, 0, SEEK_SET) != 0) fail("seek to start failed\n");
-
-	void *data = malloc(size);
-	if (!data) fail("could not allocate buffer\n");
-
-	if (fread(data, size, 1, cbfs) != 1) fail("could not read data\n");
-	if (fclose(cbfs)) fail("could not close file\n");
-
-	if (setup_cbfs_from_ram(data, size) != 0) fail("could not setup CBFS in RAM\n");
-	struct cbfs_file *file = cbfs_find("foo");
-	if (file == NULL) fail("could not find file in CBFS\n");
-	exit(0);
-}

From 5a7c1c6729a5cc0d26123ae0c97d8547d35ee602 Mon Sep 17 00:00:00 2001
From: Kapil Porwal <kapilporwal@google.com>
Date: Mon, 24 Feb 2025 12:35:05 +0530
Subject: [PATCH 0176/3886] mb/google/trulo: Lock GPIO pad configuration for
 GPP_F17

BUG=b:397905085
TEST=Make sure that GPP_F17 pad configuration is locked.

Change-Id: I9211ac70539d251746332448691d22b454bc6a2b
Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86579
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Jayvik Desai <jayvik@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
---
 src/mainboard/google/brya/variants/trulo/gpio.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/mainboard/google/brya/variants/trulo/gpio.c b/src/mainboard/google/brya/variants/trulo/gpio.c
index c813154cf8..3ccc54a3e2 100644
--- a/src/mainboard/google/brya/variants/trulo/gpio.c
+++ b/src/mainboard/google/brya/variants/trulo/gpio.c
@@ -242,7 +242,7 @@ static const struct pad_config gpio_table[] = {
 	/* F16 : NC */
 	PAD_NC_LOCK(GPP_F16, NONE, LOCK_CONFIG),
 	/* F17 : THC1_SPI2_RST# ==> EC_SOC_WAKE_ODL */
-	PAD_CFG_GPI_IRQ_WAKE(GPP_F17, NONE, PWROK, EDGE_SINGLE, INVERT),
+	PAD_CFG_GPI_IRQ_WAKE_LOCK(GPP_F17, NONE, EDGE_SINGLE, INVERT, LOCK_CONFIG),
 	/* F18 : THC1_SPI2_INT# ==> EC_IN_RW_OD */
 	PAD_CFG_GPI_LOCK(GPP_F18, NONE, LOCK_CONFIG),
 	/* F19 : Not available */

From 5c53441738c8eb72da1f7caf5633ae9a94020d96 Mon Sep 17 00:00:00 2001
From: Kapil Porwal <kapilporwal@google.com>
Date: Fri, 21 Feb 2025 19:25:35 +0530
Subject: [PATCH 0177/3886] mb/google/trulo: Update GPIO wake pins

List of changes -
1. Make GPP_B3 IRQ only pin.
2. Remove redundant GPE option from touchpad device.

BUG=b:397905085
TEST=Verified wake from S0ix using touchpad.

Change-Id: I055a60476e4a37bf74940802157bb9cd30bac3c4
Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86555
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jayvik Desai <jayvik@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
---
 src/mainboard/google/brya/variants/trulo/gpio.c          | 2 +-
 src/mainboard/google/brya/variants/trulo/overridetree.cb | 1 -
 2 files changed, 1 insertion(+), 2 deletions(-)

diff --git a/src/mainboard/google/brya/variants/trulo/gpio.c b/src/mainboard/google/brya/variants/trulo/gpio.c
index 3ccc54a3e2..fb805d6f28 100644
--- a/src/mainboard/google/brya/variants/trulo/gpio.c
+++ b/src/mainboard/google/brya/variants/trulo/gpio.c
@@ -58,7 +58,7 @@ static const struct pad_config gpio_table[] = {
 	/* B2  : NC */
 	PAD_NC(GPP_B2, NONE),
 	/* B3  : CPU_GP2 ==> EC_TP_INT */
-	PAD_CFG_GPI_IRQ_WAKE(GPP_B3, NONE, PWROK, LEVEL, INVERT),
+	PAD_CFG_GPI_APIC(GPP_B3, NONE, PWROK, LEVEL, INVERT),
 	/* B4  : PROC_GP3 ==> EN_PP3300_UCAM_X */
 	PAD_CFG_GPO_LOCK(GPP_B4, 1, LOCK_CONFIG),
 	/* B5  : GPP_B5 ==> ISH_I2C0_SCL */
diff --git a/src/mainboard/google/brya/variants/trulo/overridetree.cb b/src/mainboard/google/brya/variants/trulo/overridetree.cb
index cdc777b0b0..4c21173a76 100644
--- a/src/mainboard/google/brya/variants/trulo/overridetree.cb
+++ b/src/mainboard/google/brya/variants/trulo/overridetree.cb
@@ -455,7 +455,6 @@ chip soc/intel/alderlake
 				register "hid" = ""ELAN0000""
 				register "desc" = ""ELAN Touchpad""
 				register "irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_B3_IRQ)"
-				register "wake" = "GPE0_DW1_03"
 				register "detect" = "1"
 				device i2c 15 on end
 			end

From d64385f307943caf7f2a612992bf4afaf71bfa25 Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Wed, 19 Feb 2025 09:47:40 +0000
Subject: [PATCH 0178/3886] acpi: Fix incorrect TPM2 table generation for
 CRB_TPM

If CONFIG(CRB_TPM) is enabled but the TPM is inactive, and no other TPM
interface (SPI, I2C, Memory-Mapped) is configured, the function would
incorrectly fallback to generate a TPM2 table for FIFO mode.

This commit adds a check to ensure crb_tpm_is_active() is only
called if CONFIG(CRB_TPM) is enabled and no other TPM interface
is present. If the CRB TPM is inactive and no other TPMs are
available, the function now exits early to prevent generating
an invalid TPM2 table.

Test=boot `starlabs/starlite_adl` and check Linux doesn't probe for a
TPM when PTT is not active.

Change-Id: I153779aa1f3d84ffeb694543f9da1d09b120f98f
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86513
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
---
 src/acpi/acpi.c | 6 +++++-
 1 file changed, 5 insertions(+), 1 deletion(-)

diff --git a/src/acpi/acpi.c b/src/acpi/acpi.c
index 8f5c09fd08..06879540bf 100644
--- a/src/acpi/acpi.c
+++ b/src/acpi/acpi.c
@@ -258,6 +258,10 @@ static void acpi_create_tpm2(acpi_header_t *header, void *unused)
 	if (tlcl_get_family() != TPM_2)
 		return;
 
+	if (CONFIG(CRB_TPM) && !(CONFIG(SPI_TPM) || CONFIG(I2C_TPM) || CONFIG(MEMORY_MAPPED_TPM)))
+		if (!crb_tpm_is_active())
+			return;
+
 	acpi_tpm2_t *tpm2 = (acpi_tpm2_t *)header;
 	u32 tpm2_log_len;
 	void *lasa;
@@ -275,7 +279,7 @@ static void acpi_create_tpm2(acpi_header_t *header, void *unused)
 
 	/* Hard to detect for coreboot. Just set it to 0 */
 	tpm2->platform_class = 0;
-	if (CONFIG(CRB_TPM) && crb_tpm_is_active()) {
+	if (CONFIG(CRB_TPM)) {
 		/* Must be set to 7 for CRB Support */
 		tpm2->control_area = CONFIG_CRB_TPM_BASE_ADDRESS + 0x40;
 		tpm2->start_method = 7;

From bf649fb150eb21f241d101c5ed1aa87a0826a8ea Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Tue, 11 Feb 2025 20:40:28 +0000
Subject: [PATCH 0179/3886] drivers/crb: Always generate TPM ACPI Tables

Commit `fb2c09d5162719a72f0fbc533bec0aa3e8458b93` stopped the SSDT
containing TPM tables if PTT was not active, as at the time, the
table unconditionally reported the device present in the _STA
method.

Commit `d503ce1277b968daf9f96bb2215c8ec0e8a17f8a` made the _STA to
return an accurate state, so now, the tables can always be
generated and Linux will report the presence correctly.

Change-Id: I594bf25a207b809c1ae2632eb1aea0d0fb6df35e
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86369
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
---
 src/drivers/crb/tis.c | 5 -----
 1 file changed, 5 deletions(-)

diff --git a/src/drivers/crb/tis.c b/src/drivers/crb/tis.c
index 0222f6d92d..b51a04f54f 100644
--- a/src/drivers/crb/tis.c
+++ b/src/drivers/crb/tis.c
@@ -210,11 +210,6 @@ static struct device_operations __maybe_unused crb_ops = {
 
 static void enable_dev(struct device *dev)
 {
-	if (crb_tis_probe(NULL) == NULL) {
-		dev->enabled = 0;
-		return;
-	}
-
 #if !DEVTREE_EARLY
 	dev->ops = &crb_ops;
 #endif

From 024a23e47869d197b18541dbd21df0d451f75403 Mon Sep 17 00:00:00 2001
From: Guangjie Song <guangjie.song@mediatek.com>
Date: Mon, 10 Feb 2025 19:24:38 +0800
Subject: [PATCH 0180/3886] soc/mediatek/mt8196: Disable HWRot's clocks

HWRot (Hardware Root of trust) is not used, so we disable its clocks to
save power. This patch is a subitem of Vcore power consumption
improvement. The whole work improves SoC power consumption from 120mW to
90mW in suspend.

BRANCH=rauru
BUG=b:377628718
TEST=Bootup OK & Suspend/Resume passed

Signed-off-by: Guangjie Song <guangjie.song@mediatek.com>
Change-Id: I25e607e8e8b2d52608d279e1862f423ca50aab6a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86553
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/soc/mediatek/mt8196/pll.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/soc/mediatek/mt8196/pll.c b/src/soc/mediatek/mt8196/pll.c
index 2007197003..91d2fed669 100644
--- a/src/soc/mediatek/mt8196/pll.c
+++ b/src/soc/mediatek/mt8196/pll.c
@@ -1628,14 +1628,14 @@ void mt_pll_post_init(void)
 	write32(&mtk_topckgen->clk_cfg[12].set, 0x80800000);
 	write32(&mtk_topckgen->clk_cfg[15].set, 0x8000);
 	write32(&mtk_topckgen->clk_cfg[16].set, 0x800000);
-	write32(&mtk_topckgen->clk_cfg[18].set, 0x80000000);
+	write32(&mtk_topckgen->clk_cfg[18].set, 0x80800000);
 	write32(&mtk_topckgen->clk_cfg[19].set, 0x80808000);
 	write32(&mtk_topckgen->clk_cfg[20].set, 0x80808080);
 	write32(&mtk_topckgen->clk_cfg[21].set, 0x80808080);
 	write32(&mtk_topckgen->clk_cfg[22].set, 0x80);
 
 	write32(&mtk_vlpsys->vlp_clk_cfg[6].set, 0x80);
-	write32(&mtk_vlpsys->vlp_clk_cfg[10].set, 0x80800000);
+	write32(&mtk_vlpsys->vlp_clk_cfg[10].set, 0x80808000);
 	write32(&mtk_vlpsys->vlp_clk_cfg[11].set, 0x80);
 
 	write32(&mtk_topckgen2->cksys2_clk_cfg[0].set, 0x80808080);

From a8139c0b87053dbe9868da01c8e64e64e62786e3 Mon Sep 17 00:00:00 2001
From: Maximilian Brune <maximilian.brune@9elements.com>
Date: Mon, 24 Feb 2025 17:21:35 +0100
Subject: [PATCH 0181/3886] treewide: Rename PM4LE -> PML4E
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

The x86 (AMD and Intel) spec defines it as Page-Map Level-4 Entry.
It is annoying when searching for the wrong abbreviation in the spec so
fix it everywhere it occurs.

source: Intel 64 spec April 2022 and AMD64 spec April 2024.

Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: I730235beea69b3720f080bbade083c2eeed26587
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86587
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Benjamin Doron <benjamin.doron00@gmail.com>
Reviewed-by: Andy Ebrahiem <ahmet.ebrahiem@9elements.com>
---
 payloads/libpayload/arch/x86/head_64.S                |  4 ++--
 payloads/libpayload/arch/x86/pt.S                     |  8 ++++----
 src/cpu/intel/car/core2/cache_as_ram.S                |  2 +-
 src/cpu/intel/car/non-evict/cache_as_ram.S            |  2 +-
 src/cpu/intel/car/p4-netburst/cache_as_ram.S          |  2 +-
 src/cpu/x86/64bit/mode_switch2.S                      |  2 +-
 src/cpu/x86/64bit/pt.S                                |  4 ++--
 src/cpu/x86/64bit/pt1G.S                              |  4 ++--
 src/cpu/x86/smm/smm_module_loader.c                   | 10 +++++-----
 src/soc/amd/common/block/cpu/noncar/pre_c.S           |  2 +-
 src/soc/intel/common/block/cpu/car/cache_as_ram.S     |  2 +-
 src/soc/intel/common/block/cpu/car/cache_as_ram_fsp.S |  2 +-
 12 files changed, 22 insertions(+), 22 deletions(-)

diff --git a/payloads/libpayload/arch/x86/head_64.S b/payloads/libpayload/arch/x86/head_64.S
index 65242749fa..1fd0d01e7a 100644
--- a/payloads/libpayload/arch/x86/head_64.S
+++ b/payloads/libpayload/arch/x86/head_64.S
@@ -70,7 +70,7 @@ _entry:
 	movl %eax, cb_header_ptr
 
 	call init_page_table
-	movl $pm4le, %eax
+	movl $pml4e, %eax
 
 	/* load identity mapped page tables */
 	movl %eax, %cr3
@@ -107,7 +107,7 @@ _init64:
 	movq %rdi, cb_header_ptr
 
 	call init_page_table
-	movq $pm4le, %rax
+	movq $pml4e, %rax
 
 	/* load identity mapped page tables */
 	movq %rax, %cr3
diff --git a/payloads/libpayload/arch/x86/pt.S b/payloads/libpayload/arch/x86/pt.S
index 0e6e7bffef..080d044b84 100644
--- a/payloads/libpayload/arch/x86/pt.S
+++ b/payloads/libpayload/arch/x86/pt.S
@@ -41,10 +41,10 @@
 #define _D    (1ULL << 6)
 #define _PS   (1ULL << 7)
 
-.section .bss.pm4le
-.global pm4le
+.section .bss.pml4e
+.global pml4e
 .align 4096
-pm4le:
+pml4e:
 .skip 8
 
 .section .bss.main_page_table
@@ -144,6 +144,6 @@ no_overflow_1gb:
 
 leave:
 	or $(_PRES + _RW + _US + _A), %eax
-	mov %eax, pm4le
+	mov %eax, pml4e
 
 	ret
diff --git a/src/cpu/intel/car/core2/cache_as_ram.S b/src/cpu/intel/car/core2/cache_as_ram.S
index 227ddf4c22..de945a9396 100644
--- a/src/cpu/intel/car/core2/cache_as_ram.S
+++ b/src/cpu/intel/car/core2/cache_as_ram.S
@@ -163,7 +163,7 @@ addrsize_set_high:
 	subl	$4, %esp
 
 #if ENV_X86_64
-	setup_longmode $PM4LE
+	setup_longmode $PML4E
 
 	movd	%mm2, %rdi
 	shlq	$32, %rdi
diff --git a/src/cpu/intel/car/non-evict/cache_as_ram.S b/src/cpu/intel/car/non-evict/cache_as_ram.S
index 9485cd44fb..7186422595 100644
--- a/src/cpu/intel/car/non-evict/cache_as_ram.S
+++ b/src/cpu/intel/car/non-evict/cache_as_ram.S
@@ -214,7 +214,7 @@ end_microcode_update:
 	andl	$0xfffffff0, %esp
 
 #if ENV_X86_64
-	setup_longmode $PM4LE
+	setup_longmode $PML4E
 
 	movd	%mm2, %rdi
 	shlq	$32, %rdi
diff --git a/src/cpu/intel/car/p4-netburst/cache_as_ram.S b/src/cpu/intel/car/p4-netburst/cache_as_ram.S
index 1cb422dbfc..1843954539 100644
--- a/src/cpu/intel/car/p4-netburst/cache_as_ram.S
+++ b/src/cpu/intel/car/p4-netburst/cache_as_ram.S
@@ -363,7 +363,7 @@ fill_cache:
 	subl	$4, %esp
 
 #if ENV_X86_64
-	setup_longmode $PM4LE
+	setup_longmode $PML4E
 
 	movd	%mm2, %rdi
 	shlq	$32, %rdi	/* BIST */
diff --git a/src/cpu/x86/64bit/mode_switch2.S b/src/cpu/x86/64bit/mode_switch2.S
index 18c6425d7f..3be56c4c5a 100644
--- a/src/cpu/x86/64bit/mode_switch2.S
+++ b/src/cpu/x86/64bit/mode_switch2.S
@@ -21,7 +21,7 @@ long_mode_call_3arg:
 	mov	%esp, %ebp
 
 	/* Enter long mode, preserves ebx */
-	setup_longmode $PM4LE
+	setup_longmode $PML4E
 
 	/* Align stack */
 	movabs	$0xfffffffffffffff0, %rax
diff --git a/src/cpu/x86/64bit/pt.S b/src/cpu/x86/64bit/pt.S
index 4b2f3c8163..1297296a37 100644
--- a/src/cpu/x86/64bit/pt.S
+++ b/src/cpu/x86/64bit/pt.S
@@ -17,9 +17,9 @@
 #define _GEN_DIR(a) (_PRES + _RW + _US + _A + (a))
 #define _GEN_PAGE(a) (_PRES + _RW + _US + _PS + _A +  _D + (a))
 
-.global PM4LE
+.global PML4E
 .align 4096
-PM4LE:
+PML4E:
 .quad _GEN_DIR(PDPT)
 
 .align 4096
diff --git a/src/cpu/x86/64bit/pt1G.S b/src/cpu/x86/64bit/pt1G.S
index 3502964d15..42cdfb17d0 100644
--- a/src/cpu/x86/64bit/pt1G.S
+++ b/src/cpu/x86/64bit/pt1G.S
@@ -17,9 +17,9 @@
 #define _GEN_DIR(a) (_PRES + _RW + _US + _A + (a))
 #define _GEN_PAGE(a) (_PRES + _RW + _US + _PS + _A +  _D + (a))
 
-.global PM4LE
+.global PML4E
 .align 4096
-PM4LE:
+PML4E:
 .quad _GEN_DIR(PDPT)
 
 .align 4096
diff --git a/src/cpu/x86/smm/smm_module_loader.c b/src/cpu/x86/smm/smm_module_loader.c
index c6d0753c6b..ba92e1ff2f 100644
--- a/src/cpu/x86/smm/smm_module_loader.c
+++ b/src/cpu/x86/smm/smm_module_loader.c
@@ -420,27 +420,27 @@ static int append_and_check_region(const struct region smram,
 #define _GEN_PAGE(a) (_PRES + _RW + _US + _PS + _A +  _D + (a))
 #define PAGE_SIZE 8
 
-/* Return the PM4LE */
+/* Return the PML4E */
 static uintptr_t install_page_table(const uintptr_t handler_base)
 {
 	const bool one_g_pages = !!(cpuid_edx(0x80000001) & (1 << 26));
 	/* 4 1G pages or 4 PDPE entries with 512 * 2M pages */
 	const size_t pages_needed = one_g_pages ? 4 : 2048 + 4;
 	const uintptr_t pages_base = ALIGN_DOWN(handler_base - pages_needed * PAGE_SIZE, 4096);
-	const uintptr_t pm4le = ALIGN_DOWN(pages_base - 8, 4096);
+	const uintptr_t pml4e = ALIGN_DOWN(pages_base - 8, 4096);
 
 	if (one_g_pages) {
 		for (size_t i = 0; i < 4; i++)
 			write64p(pages_base + i * PAGE_SIZE, _GEN_PAGE(1ull * GiB * i));
-		write64p(pm4le, _GEN_DIR(pages_base));
+		write64p(pml4e, _GEN_DIR(pages_base));
 	} else {
 		for (size_t i = 0; i < 2048; i++)
 			write64p(pages_base + i * PAGE_SIZE, _GEN_PAGE(2ull * MiB * i));
-		write64p(pm4le, _GEN_DIR(pages_base + 2048 * PAGE_SIZE));
+		write64p(pml4e, _GEN_DIR(pages_base + 2048 * PAGE_SIZE));
 		for (size_t i = 0; i < 4; i++)
 			write64p(pages_base + (2048 + i) * PAGE_SIZE, _GEN_DIR(pages_base + 4096 * i));
 	}
-	return pm4le;
+	return pml4e;
 }
 
 /*
diff --git a/src/soc/amd/common/block/cpu/noncar/pre_c.S b/src/soc/amd/common/block/cpu/noncar/pre_c.S
index 0e0be524f2..b75458815e 100644
--- a/src/soc/amd/common/block/cpu/noncar/pre_c.S
+++ b/src/soc/amd/common/block/cpu/noncar/pre_c.S
@@ -28,7 +28,7 @@ bootblock_pre_c_entry:
 	post_code(POSTCODE_BOOTBLOCK_PRE_C_ENTRY)
 
 #if ENV_X86_64
-	setup_longmode $PM4LE
+	setup_longmode $PML4E
 #endif
 
 	/* Clear .bss section */
diff --git a/src/soc/intel/common/block/cpu/car/cache_as_ram.S b/src/soc/intel/common/block/cpu/car/cache_as_ram.S
index 2c4beebf46..b84a06e0ba 100644
--- a/src/soc/intel/common/block/cpu/car/cache_as_ram.S
+++ b/src/soc/intel/common/block/cpu/car/cache_as_ram.S
@@ -280,7 +280,7 @@ car_init_done:
 	andl	$0xfffffff0, %esp
 
 #if ENV_X86_64
-	setup_longmode $PM4LE
+	setup_longmode $PML4E
 
 	movd	%mm2, %rdi
 	shlq	$32, %rdi
diff --git a/src/soc/intel/common/block/cpu/car/cache_as_ram_fsp.S b/src/soc/intel/common/block/cpu/car/cache_as_ram_fsp.S
index 4e057f046d..ed735dbce3 100644
--- a/src/soc/intel/common/block/cpu/car/cache_as_ram_fsp.S
+++ b/src/soc/intel/common/block/cpu/car/cache_as_ram_fsp.S
@@ -83,7 +83,7 @@ CAR_init_done:
 	movl	%ecx, temp_memory_start
 
 #if ENV_X86_64
-	setup_longmode $PM4LE
+	setup_longmode $PML4E
 	movl	%ebp, %edi
 	shlq	$32, %rdi
 	movd	%mm1, %rsi

From d9da2628292123e571e58947200fbf56afda677e Mon Sep 17 00:00:00 2001
From: Subrata Banik <subratabanik@google.com>
Date: Mon, 24 Feb 2025 11:40:35 +0530
Subject: [PATCH 0182/3886] soc/intel/common/reset: Mark
 do_low_battery_poweroff with __noreturn
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

In the low battery poweroff scenario, the platform should halt after
issuing the poweroff command. This ensures that no further code
execution occurs, preventing potential issues.

Additionally, the do_low_battery_poweroff() function is marked with
__noreturn to indicate that it does not return. This is appropriate
because the platform will either power off or halt.

TEST=Able to compile google/fatcat.

Change-Id: Ieb77645283360b5731ca48b94551712b99109a1c
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86578
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jayvik Desai <jayvik@google.com>
---
 src/soc/intel/common/reset.c | 1 +
 src/soc/intel/common/reset.h | 2 +-
 2 files changed, 2 insertions(+), 1 deletion(-)

diff --git a/src/soc/intel/common/reset.c b/src/soc/intel/common/reset.c
index 3fefa57d30..307be5769a 100644
--- a/src/soc/intel/common/reset.c
+++ b/src/soc/intel/common/reset.c
@@ -32,4 +32,5 @@ void do_low_battery_poweroff(void)
 	}
 
 	poweroff();
+	halt();
 }
diff --git a/src/soc/intel/common/reset.h b/src/soc/intel/common/reset.h
index 8331853023..71fe05d638 100644
--- a/src/soc/intel/common/reset.h
+++ b/src/soc/intel/common/reset.h
@@ -30,6 +30,6 @@ efi_return_status_t fsp_get_pch_reset_status(void);
  *
  * Call this function to power off the platform if the battery level is critically low.
  */
-void do_low_battery_poweroff(void);
+__noreturn void do_low_battery_poweroff(void);
 
 #endif	/* _INTEL_COMMON_RESET_H_ */

From e4ee0ce5ac8c479f7966d047642258ca0f3048e8 Mon Sep 17 00:00:00 2001
From: Anil Kumar <anil.kumar.k@intel.com>
Date: Thu, 7 Nov 2024 13:48:41 -0800
Subject: [PATCH 0183/3886] soc/intel/pantherlake: Display Sign-of-Life during
 memory training

This commit activates the Firmware Support Package (FSP) Memory
Sign-of-Life feature (FSP_UGOP_EARLY_SIGN_OF_LIFE), which allows for the
display of a user-configurable text message on-screen during memory
initialization. This feature enhances the user experience by providing
reassurance that the memory training process is underway and may take
some time.

The following FSP-M UPDs (Updateable Product Data) are utilized:

- VgaInitControl (boolean): Initializes graphics, establishes VGA text
  mode, and centers the VgaMessage text on the screen. It clears the
  screen, disables VGA text mode, and deactivates graphics upon exiting
  the FSP-M (Firmware Support Package - Memory Initialization).

- VbtPtr (address): This is a pointer to the VBT (Video BIOS Table)
  binary.

- VbtSize (unsigned integer): Indicates the size of the VBT binary.

- LidStatus (boolean): Given the limited resources available at early
  boot stages, the text message is shown on a single monitor. The lid
  status determines the most appropriate display to use:

  - 0: If the lid is closed, display the text message on an external
       display if one is available; otherwise, display nothing.

  - 1: If the lid is open, display the message on the internal display;
       if unavailable, default to an external display.

- VgaMessage (string): Specifies the text message to be displayed.

When the FSP_UGOP_EARLY_SIGN_OF_LIFE flag is set, coreboot is configured
to use the UPDs mentioned above to show a text message during the memory
training phase. This text message can be customized through the locale
text mechanism using the identifier memory_training_desc.

In addition, the newly introduced code records an extra event to
indicate when early Sign-Of-Life has been requested, to cover the Memory
Reference Code (MRC) training scenario. This event logging is crucial
for debugging and analyzing the boot process, especially in production
environments where it helps in pinpointing the exact stage where a boot
issue might occur.

TEST="Enabling FSP-M Sign-of-Life" message is present in the log upon
     the first boot, and a message is displayed on the screen while the
     FSP performs MRC training.

Signed-off-by: Anil Kumar <anil.kumar.k@intel.com>
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Change-Id: I993eb0d59cd01fa62f35a77f84e262e389efb367
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85454
Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
---
 src/soc/intel/pantherlake/Kconfig             |  1 +
 .../intel/pantherlake/romstage/fsp_params.c   | 36 +++++++++++++++++++
 2 files changed, 37 insertions(+)

diff --git a/src/soc/intel/pantherlake/Kconfig b/src/soc/intel/pantherlake/Kconfig
index df95e529e3..a54f0defe5 100644
--- a/src/soc/intel/pantherlake/Kconfig
+++ b/src/soc/intel/pantherlake/Kconfig
@@ -17,6 +17,7 @@ config SOC_INTEL_PANTHERLAKE_BASE
 	select FAST_SPI_SUPPORTS_EXT_BIOS_WINDOW
 	select FSP_COMPRESS_FSP_S_LZ4
 	select FSP_M_XIP
+	select FSP_UGOP_EARLY_SIGN_OF_LIFE
 	select FSP_USES_CB_DEBUG_EVENT_HANDLER
 	select FSPS_HAS_ARCH_UPD
 	select GENERIC_GPIO_LIB
diff --git a/src/soc/intel/pantherlake/romstage/fsp_params.c b/src/soc/intel/pantherlake/romstage/fsp_params.c
index 0c17d020c3..8de99d2f95 100644
--- a/src/soc/intel/pantherlake/romstage/fsp_params.c
+++ b/src/soc/intel/pantherlake/romstage/fsp_params.c
@@ -1,7 +1,9 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
+#include <bootmode.h>
 #include <cpu/intel/common/common.h>
 #include <cpu/x86/msr.h>
+#include <elog.h>
 #include <fsp/debug.h>
 #include <fsp/fsp_debug_event.h>
 #include <fsp/util.h>
@@ -11,6 +13,7 @@
 #include <soc/pcie.h>
 #include <soc/romstage.h>
 #include <static.h>
+#include <ux_locales.h>
 
 #define FSP_CLK_NOTUSED		0xff
 #define FSP_CLK_LAN		0x70
@@ -355,6 +358,35 @@ static void fill_fsp_event_handler(FSPM_UPD *mupd)
 	fsp_control_log_level(mupd, fsp_debug_enable);
 }
 
+static void fill_fspm_sign_of_life(FSPM_UPD *mupd)
+{
+	FSP_M_CONFIG *m_cfg = &mupd->FspmConfig;
+	FSPM_ARCHx_UPD *arch_upd = &mupd->FspmArchUpd;
+	void *vbt;
+	size_t vbt_size;
+
+	if (arch_upd->NvsBufferPtr)
+		return;
+
+	/* To enhance the user experience, let's display on-screen guidance during memory
+	   training, acknowledging that the process may require patience. */
+
+	vbt = cbfs_map("vbt.bin", &vbt_size);
+	if (!vbt) {
+		printk(BIOS_ERR, "Could not load vbt.bin\n");
+		return;
+	}
+
+	printk(BIOS_INFO, "Enabling FSP-M Sign-of-Life\n");
+	elog_add_event_byte(ELOG_TYPE_FW_EARLY_SOL, ELOG_FW_EARLY_SOL_MRC);
+
+	m_cfg->VgaInitControl = 1;
+	m_cfg->VbtPtr = (efi_uintn_t)vbt;
+	m_cfg->VbtSize = vbt_size;
+	m_cfg->LidStatus = CONFIG(VBOOT_LID_SWITCH) ? get_lid_switch() : CONFIG(RUN_FSP_GOP);
+	m_cfg->VgaMessage = (efi_uintn_t)ux_locales_get_text(UX_LOCALE_MSG_MEMORY_TRAINING);
+}
+
 void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version)
 {
 	const struct soc_intel_pantherlake_config *config = config_of_soc();
@@ -363,6 +395,10 @@ void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version)
 		fill_fsp_event_handler(mupd);
 
 	soc_memory_init_params(&mupd->FspmConfig, config);
+
+	if (CONFIG(FSP_UGOP_EARLY_SIGN_OF_LIFE))
+		fill_fspm_sign_of_life(mupd);
+
 	mainboard_memory_init_params(mupd);
 }
 

From 77e8b821cbda0570731ac4f20745c0f9a6692642 Mon Sep 17 00:00:00 2001
From: Subrata Banik <subratabanik@google.com>
Date: Sun, 16 Feb 2025 22:55:04 +0530
Subject: [PATCH 0184/3886] drivers/intel/fsp2_0: Add early low-battery
 shutdown during memory init

This commit introduces an early low-battery shutdown mechanism during
FSP memory initialization. This is particularly important during
firmware updates, where memory training can consume significant power
and lead to abrupt shutdowns, potentially corrupting the firmware.

The changes include:

- Adding platform_display_early_shutdown_notification() to notify the
user of the impending shutdown.
- Checking platform_is_low_battery_shutdown_needed() to determine if a
shutdown is necessary.
- Implementing a shutdown sequence if low battery is detected during
memory init, especially when no MRC cache is found (i.e. firmware
update).
- Deferring shutdown on systems without MAINBOARD_HAS_EARLY_LIBGFXINIT
so that FSP-M (uGOP) can display a message.

This prevents firmware update corruption due to low battery.

BUG=b:339673254
TEST=Verified low battery boot event logging and controlled shutdown.

Change-Id: Ia135b238d1e16722c2ca8d3b461e83b4ce513adf
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86452
Reviewed-by: Jayvik Desai <jayvik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
---
 src/drivers/intel/fsp2_0/include/fsp/api.h | 20 ++++++++++++
 src/drivers/intel/fsp2_0/memory_init.c     | 36 ++++++++++++++++++++++
 2 files changed, 56 insertions(+)

diff --git a/src/drivers/intel/fsp2_0/include/fsp/api.h b/src/drivers/intel/fsp2_0/include/fsp/api.h
index 28b24ce95f..d159b71e02 100644
--- a/src/drivers/intel/fsp2_0/include/fsp/api.h
+++ b/src/drivers/intel/fsp2_0/include/fsp/api.h
@@ -63,6 +63,26 @@ bool platform_is_low_battery_shutdown_needed(void);
 #else
 static inline bool platform_is_low_battery_shutdown_needed(void) { return false; }
 #endif
+
+/*
+ * Displays an early shutdown notification to the user.
+ *
+ * This function is responsible to perform the needful operations for informing
+ * the user that the system is about to shut down prematurely. The implementation
+ * might be different depending upon the underlying technology that can be used for
+ * implementing eSOL for user notification.
+ *
+ * Argument: NULL for platform with libgfxinit and FSP-M UPD pointer for uGOP.
+ *
+ * Note: This function should be called before the actual shutdown process begins,
+ * allowing the user to potentially save data or take other necessary actions.
+ */
+#if CONFIG(PLATFORM_HAS_EARLY_LOW_BATTERY_INDICATOR)
+void platform_display_early_shutdown_notification(void *arg);
+#else
+static inline void platform_display_early_shutdown_notification(void *arg) { /* nop */ }
+#endif
+
 /* Check if MultiPhase Si Init is enabled */
 bool fsp_is_multi_phase_init_enabled(void);
 /*
diff --git a/src/drivers/intel/fsp2_0/memory_init.c b/src/drivers/intel/fsp2_0/memory_init.c
index ce0d2831e3..38627c6b06 100644
--- a/src/drivers/intel/fsp2_0/memory_init.c
+++ b/src/drivers/intel/fsp2_0/memory_init.c
@@ -19,6 +19,7 @@
 #include <security/tpm/tspi.h>
 #include <security/vboot/antirollback.h>
 #include <security/vboot/vboot_common.h>
+#include <soc/intel/common/reset.h>
 #include <string.h>
 #include <symbols.h>
 #include <timestamp.h>
@@ -331,6 +332,31 @@ static void fspm_multi_phase_init(const struct fsp_header *hdr)
 	timestamp_add_now(TS_FSP_MULTI_PHASE_MEM_INIT_END);
 }
 
+/**
+ * Checks for low battery during firmware update and initiates shutdown if necessary.
+ *
+ * This function checks if the system is in firmware update mode (indicated by
+ * a missing MRC cache) and if the battery is critically low. If both conditions
+ * are met, it initiates a shutdown to prevent interruption of the firmware
+ * update process.
+ */
+static void handle_low_battery_during_firmware_update(bool *defer_shutdown, FSPM_UPD *fspm_upd)
+{
+	if (!CONFIG(PLATFORM_HAS_EARLY_LOW_BATTERY_INDICATOR) ||
+			 !platform_is_low_battery_shutdown_needed())
+		return;
+
+	if (CONFIG(MAINBOARD_HAS_EARLY_LIBGFXINIT)) {
+		platform_display_early_shutdown_notification(NULL);
+		/* User has been notified of low battery; safe to power off. */
+		do_low_battery_poweroff(); /* Do not return */
+	}
+
+	/* Defer shutdown until FSP-M (uGOP) display text message for user notification */
+	platform_display_early_shutdown_notification(fspm_upd);
+	*defer_shutdown = true;
+}
+
 static void do_fsp_memory_init(const struct fspm_context *context, bool s3wake)
 {
 	efi_return_status_t status;
@@ -338,6 +364,7 @@ static void do_fsp_memory_init(const struct fspm_context *context, bool s3wake)
 	FSPM_UPD fspm_upd, *upd;
 	FSPM_ARCHx_UPD *arch_upd;
 	uint32_t version;
+	bool poweroff_after_fsp_execution = false;
 	const struct fsp_header *hdr = &context->header;
 	const struct memranges *memmap = &context->memmap;
 
@@ -389,6 +416,11 @@ static void do_fsp_memory_init(const struct fspm_context *context, bool s3wake)
 		early_ramtop_enable_cache_range();
 #endif
 
+	/* Low battery check during firmware update */
+	if (!arch_upd->NvsBufferPtr)
+		handle_low_battery_during_firmware_update(&poweroff_after_fsp_execution,
+				 &fspm_upd);
+
 	/* Give SoC and mainboard a chance to update the UPD */
 	platform_fsp_memory_init_params_cb(&fspm_upd, version);
 
@@ -425,6 +457,10 @@ static void do_fsp_memory_init(const struct fspm_context *context, bool s3wake)
 	null_breakpoint_init();
 	stack_canary_breakpoint_init();
 
+	/* User has been notified of low battery; safe to power off. */
+	if (poweroff_after_fsp_execution)
+		do_low_battery_poweroff();
+
 	post_code(POSTCODE_FSP_MEMORY_EXIT);
 	timestamp_add_now(TS_FSP_MEMORY_INIT_END);
 

From 3a57364bc4b4d54253674645ee6513a843e6f5e4 Mon Sep 17 00:00:00 2001
From: Subrata Banik <subratabanik@google.com>
Date: Sun, 16 Feb 2025 23:05:30 +0530
Subject: [PATCH 0185/3886] soc/intel/adl: Delegate low-battery shutdown
 notification to platform

This commit removes the SoC-specific implementation of the early
low-battery shutdown notification. The generic implementation now
resides within the FSP driver layer, requiring only platform-specific
customization.

Platforms can now implement platform_display_early_shutdown_notification()
when CONFIG(PLATFORM_HAS_EARLY_LOW_BATTERY_INDICATOR) is enabled. This
function utilizes ux_inform_user_of_poweroff_operation() to display a
"low-battery shutdown" message using libgfxinit.

BUG=b:339673254
TEST=Verified low battery boot event logging and controlled shutdown.

Change-Id: If9f68b2b5cc710e00584b451f904e60d724d1e32
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86453
Reviewed-by: Andy Ebrahiem <ahmet.ebrahiem@9elements.com>
Reviewed-by: Jayvik Desai <jayvik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/soc/intel/alderlake/romstage/fsp_params.c | 29 +++++--------------
 1 file changed, 7 insertions(+), 22 deletions(-)

diff --git a/src/soc/intel/alderlake/romstage/fsp_params.c b/src/soc/intel/alderlake/romstage/fsp_params.c
index 71791ae90b..24b2c8c002 100644
--- a/src/soc/intel/alderlake/romstage/fsp_params.c
+++ b/src/soc/intel/alderlake/romstage/fsp_params.c
@@ -415,6 +415,13 @@ static void debug_override_memory_init_params(FSP_M_CONFIG *mupd)
 	debug_get_pch_cpu_tracehub_modes(&mupd->CpuTraceHubMode, &mupd->PchTraceHubMode);
 }
 
+#if CONFIG(PLATFORM_HAS_EARLY_LOW_BATTERY_INDICATOR)
+void platform_display_early_shutdown_notification(void *arg)
+{
+	ux_inform_user_of_poweroff_operation("low-battery shutdown");
+}
+#endif
+
 static void fill_fspm_sign_of_life(FSP_M_CONFIG *m_cfg,
 				   FSPM_ARCH_UPD *arch_upd)
 {
@@ -429,28 +436,6 @@ static void fill_fspm_sign_of_life(FSP_M_CONFIG *m_cfg,
 	 * user with an on-screen text message.
 	 */
 	if (!arch_upd->NvsBufferPtr) {
-		/*
-		 * Low Battery Check During Firmware Update (Chrome OS specific):
-		 *    - If `PLATFORM_HAS_EARLY_LOW_BATTERY_INDICATOR` is enabled AND the
-		 *      system is in firmware update mode (If valid MRC cache data is not found,
-		 *      it means that the system needs to perform), it checks if the battery level is
-		 *      critically low.
-		 *    - This is because memory training, which can take a significant amount of
-		 *      time, might cause an abrupt shutdown due to low battery, interrupting the
-		 *      firmware update process and potentially leaving the system in an unstable
-		 *      state.
-		 *    - To prevent this, if the battery is critically low, the system is powered
-		 *      off to allow it to charge. This ensures that the firmware update process
-		 *      can complete without interruption.
-		 *    - Since a functional GFX mode display may not be ready at this stage, VGA
-		 *      mode is used to display a text message informing the user about the
-		 *      shutdown.
-		 */
-		if (CONFIG(PLATFORM_HAS_EARLY_LOW_BATTERY_INDICATOR) &&
-				 platform_is_low_battery_shutdown_needed()) {
-			ux_inform_user_of_poweroff_operation("low-battery shutdown");
-			do_low_battery_poweroff();
-		}
 		esol_required = true;
 		name = "memory training";
 		elog_add_event_byte(ELOG_TYPE_FW_EARLY_SOL, ELOG_FW_EARLY_SOL_MRC);

From 3130c410c6b4e2f8608de1c0f8f73b0e7124b033 Mon Sep 17 00:00:00 2001
From: Subrata Banik <subratabanik@google.com>
Date: Tue, 18 Feb 2025 12:27:43 +0530
Subject: [PATCH 0186/3886] soc/intel/pantherlake: Implement UX help APIs for
 eSOL handling
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

This patch refactors the eSOL implementation for Panther Lake and
introduces two new APIs, mirroring those in Alder Lake, to manage:

- Low battery shutdown notifications
- Firmware update memory training

BUG=b:397302064
TEST=Built and booted google/fatcat successfully.

Change-Id: I14229af4a4920414f3c572576d67fa6d665681cd
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86509
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Reviewed-by: Jayvik Desai <jayvik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 .../intel/pantherlake/romstage/Makefile.mk    |  1 +
 src/soc/intel/pantherlake/romstage/ux.c       | 67 +++++++++++++++++++
 src/soc/intel/pantherlake/romstage/ux.h       |  9 +++
 3 files changed, 77 insertions(+)
 create mode 100644 src/soc/intel/pantherlake/romstage/ux.c
 create mode 100644 src/soc/intel/pantherlake/romstage/ux.h

diff --git a/src/soc/intel/pantherlake/romstage/Makefile.mk b/src/soc/intel/pantherlake/romstage/Makefile.mk
index 99c1d2ca25..999241c738 100644
--- a/src/soc/intel/pantherlake/romstage/Makefile.mk
+++ b/src/soc/intel/pantherlake/romstage/Makefile.mk
@@ -4,3 +4,4 @@ romstage-y += fsp_params.c
 romstage-y += ../../../../cpu/intel/car/romstage.c
 romstage-y += romstage.c
 romstage-y += systemagent.c
+romstage-y += ux.c
diff --git a/src/soc/intel/pantherlake/romstage/ux.c b/src/soc/intel/pantherlake/romstage/ux.c
new file mode 100644
index 0000000000..9fcb418157
--- /dev/null
+++ b/src/soc/intel/pantherlake/romstage/ux.c
@@ -0,0 +1,67 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <bootmode.h>
+#include <console/console.h>
+#include <fsp/util.h>
+#include <timestamp.h>
+#include <ux_locales.h>
+
+#include "ux.h"
+
+static bool ux_inform_user_of_operation(const char *name, enum ux_locale_msg id,
+		 FSPM_UPD *mupd)
+{
+	timestamp_add_now(TS_ESOL_START);
+
+	if (!CONFIG(CHROMEOS_ENABLE_ESOL)) {
+		timestamp_add_now(TS_ESOL_END);
+		return false;
+	}
+
+	FSP_M_CONFIG *m_cfg = &mupd->FspmConfig;
+	void *vbt;
+	size_t vbt_size;
+	static bool ux_done = false;
+
+	/*
+	 * Prevents multiple VGA text messages from being rendered during the boot process.
+	 *
+	 * This function is designed to be called only once. Subsequent calls are intentionally
+	 * ignored to avoid overwriting previously displayed messages. For example, if a
+	 * low-battery shutdown notification is scheduled, a later call with a firmware
+	 * update notification could result in the low-battery message being lost.
+	 */
+	if (ux_done) {
+		timestamp_add_now(TS_ESOL_END);
+		return true;
+	}
+
+	printk(BIOS_INFO, "Informing user on-display of %s.\n", name);
+
+	vbt = cbfs_map("vbt.bin", &vbt_size);
+	if (!vbt) {
+		printk(BIOS_ERR, "Could not load vbt.bin\n");
+		return false;
+	}
+
+	m_cfg->VgaInitControl = 1;
+	m_cfg->VbtPtr = (efi_uintn_t)vbt;
+	m_cfg->VbtSize = vbt_size;
+	m_cfg->LidStatus = CONFIG(VBOOT_LID_SWITCH) ? get_lid_switch() : CONFIG(RUN_FSP_GOP);
+	m_cfg->VgaMessage = (efi_uintn_t)ux_locales_get_text(id);
+
+	ux_done = true;
+
+	timestamp_add_now(TS_ESOL_END);
+	return true;
+}
+
+bool ux_inform_user_of_update_operation(const char *name, FSPM_UPD *mupd)
+{
+	return ux_inform_user_of_operation(name, UX_LOCALE_MSG_MEMORY_TRAINING, mupd);
+}
+
+bool ux_inform_user_of_poweroff_operation(const char *name, FSPM_UPD *mupd)
+{
+	return ux_inform_user_of_operation(name, UX_LOCALE_MSG_LOW_BATTERY, mupd);
+}
diff --git a/src/soc/intel/pantherlake/romstage/ux.h b/src/soc/intel/pantherlake/romstage/ux.h
new file mode 100644
index 0000000000..bcee87f24d
--- /dev/null
+++ b/src/soc/intel/pantherlake/romstage/ux.h
@@ -0,0 +1,9 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef _SOC_INTEL_PANTHERLAKE_ROMSTAGE_UX_H_
+#define _SOC_INTEL_PANTHERLAKE_ROMSTAGE_UX_H_
+
+bool ux_inform_user_of_update_operation(const char *name, FSPM_UPD *mupd);
+bool ux_inform_user_of_poweroff_operation(const char *name, FSPM_UPD *mupd);
+
+#endif /* _SOC_INTEL_PANTHERLAKE_ROMSTAGE_UX_H_ */

From 2f57986700dfd55ec875372fee0979d0309f0bd7 Mon Sep 17 00:00:00 2001
From: Subrata Banik <subratabanik@google.com>
Date: Tue, 25 Feb 2025 13:37:37 +0530
Subject: [PATCH 0187/3886] soc/intel/pantherlake: Centralize FSP-M eSOL UX
 with common APIs

Refactor the FSP-M early Sign-of-Life (eSOL) implementation to utilize
the UX APIs defined in `ux.c`.

This eliminates redundant code and ensures consistent messaging during
critical boot phases, such as memory training.

BUG=b:339673254
TEST=Verified eSOL message over eDP while booting google/fatcat.

Change-Id: Icf22c39c21e2357b2a548398700a1488f4ef463a
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86592
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
---
 .../intel/pantherlake/romstage/fsp_params.c   | 21 +++----------------
 1 file changed, 3 insertions(+), 18 deletions(-)

diff --git a/src/soc/intel/pantherlake/romstage/fsp_params.c b/src/soc/intel/pantherlake/romstage/fsp_params.c
index 8de99d2f95..a8f86a8e56 100644
--- a/src/soc/intel/pantherlake/romstage/fsp_params.c
+++ b/src/soc/intel/pantherlake/romstage/fsp_params.c
@@ -1,6 +1,5 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
-#include <bootmode.h>
 #include <cpu/intel/common/common.h>
 #include <cpu/x86/msr.h>
 #include <elog.h>
@@ -13,7 +12,8 @@
 #include <soc/pcie.h>
 #include <soc/romstage.h>
 #include <static.h>
-#include <ux_locales.h>
+
+#include "ux.h"
 
 #define FSP_CLK_NOTUSED		0xff
 #define FSP_CLK_LAN		0x70
@@ -360,31 +360,16 @@ static void fill_fsp_event_handler(FSPM_UPD *mupd)
 
 static void fill_fspm_sign_of_life(FSPM_UPD *mupd)
 {
-	FSP_M_CONFIG *m_cfg = &mupd->FspmConfig;
 	FSPM_ARCHx_UPD *arch_upd = &mupd->FspmArchUpd;
-	void *vbt;
-	size_t vbt_size;
 
 	if (arch_upd->NvsBufferPtr)
 		return;
 
 	/* To enhance the user experience, let's display on-screen guidance during memory
 	   training, acknowledging that the process may require patience. */
-
-	vbt = cbfs_map("vbt.bin", &vbt_size);
-	if (!vbt) {
-		printk(BIOS_ERR, "Could not load vbt.bin\n");
-		return;
-	}
-
 	printk(BIOS_INFO, "Enabling FSP-M Sign-of-Life\n");
 	elog_add_event_byte(ELOG_TYPE_FW_EARLY_SOL, ELOG_FW_EARLY_SOL_MRC);
-
-	m_cfg->VgaInitControl = 1;
-	m_cfg->VbtPtr = (efi_uintn_t)vbt;
-	m_cfg->VbtSize = vbt_size;
-	m_cfg->LidStatus = CONFIG(VBOOT_LID_SWITCH) ? get_lid_switch() : CONFIG(RUN_FSP_GOP);
-	m_cfg->VgaMessage = (efi_uintn_t)ux_locales_get_text(UX_LOCALE_MSG_MEMORY_TRAINING);
+	ux_inform_user_of_update_operation("memory training", mupd);
 }
 
 void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version)

From 80db7cdae04bb2a5c47035c3a0ad3bb5b6380d6b Mon Sep 17 00:00:00 2001
From: Subrata Banik <subratabanik@google.com>
Date: Tue, 25 Feb 2025 13:10:23 +0530
Subject: [PATCH 0188/3886] soc/intel/pantherlake: Add early shutdown
 notification hook

This commit display UX message for low-battery shutdown using
platform_display_early_shutdown_notification().

This commit also enables the HAVE_ESOL_SUPPORT_FOR_LOW_BATTERY_INDICATOR
Kconfig option, which is required for displaying the VGA text message
during early shutdown.

BUG=b:339673254
TEST=Verified low battery boot event logging and controlled shutdown.

Change-Id: I45c0fb07b984fcde6209631612cb8b4a08ac2041
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86476
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jayvik Desai <jayvik@google.com>
---
 src/soc/intel/pantherlake/Kconfig               | 1 +
 src/soc/intel/pantherlake/romstage/fsp_params.c | 8 ++++++++
 2 files changed, 9 insertions(+)

diff --git a/src/soc/intel/pantherlake/Kconfig b/src/soc/intel/pantherlake/Kconfig
index a54f0defe5..fc8664a927 100644
--- a/src/soc/intel/pantherlake/Kconfig
+++ b/src/soc/intel/pantherlake/Kconfig
@@ -22,6 +22,7 @@ config SOC_INTEL_PANTHERLAKE_BASE
 	select FSPS_HAS_ARCH_UPD
 	select GENERIC_GPIO_LIB
 	select HAVE_DEBUG_RAM_SETUP
+	select HAVE_ESOL_SUPPORT_FOR_LOW_BATTERY_INDICATOR if CHROMEOS_ENABLE_ESOL
 	select HAVE_FSP_GOP
 	select HAVE_FSP_LOGO_SUPPORT if RUN_FSP_GOP
 	select HAVE_HYPERTHREADING
diff --git a/src/soc/intel/pantherlake/romstage/fsp_params.c b/src/soc/intel/pantherlake/romstage/fsp_params.c
index a8f86a8e56..93c8777d82 100644
--- a/src/soc/intel/pantherlake/romstage/fsp_params.c
+++ b/src/soc/intel/pantherlake/romstage/fsp_params.c
@@ -289,6 +289,14 @@ static void fill_fspm_vr_config_params(FSP_M_CONFIG *m_cfg,
 		m_cfg->EnableFastVmode[i] = 0;
 }
 
+#if CONFIG(PLATFORM_HAS_EARLY_LOW_BATTERY_INDICATOR)
+void platform_display_early_shutdown_notification(void *arg)
+{
+	FSPM_UPD *mupd = arg;
+	ux_inform_user_of_poweroff_operation("low-battery shutdown", mupd);
+}
+#endif
+
 static void soc_memory_init_params(FSP_M_CONFIG *m_cfg,
 				   const struct soc_intel_pantherlake_config *config)
 {

From 2a10fac565b942d0dac1efe388331f1627025e67 Mon Sep 17 00:00:00 2001
From: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com>
Date: Wed, 12 Feb 2025 19:25:03 +0900
Subject: [PATCH 0189/3886] mb/google/nissa/var/meliks: Update memory DQ/DQS
 map

Update memory DQ/DQS map configuration by following schematics.

BUG=b:394359785
TEST=Build coreboot and verified booting to depthcharge

Change-Id: Iae3f2c65b4d1004d1d9ebf76b099fc7f50e8365f
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86376
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
---
 .../google/brya/variants/meliks/Makefile.mk   |  2 +
 .../google/brya/variants/meliks/memory.c      | 97 +++++++++++++++++++
 2 files changed, 99 insertions(+)
 create mode 100644 src/mainboard/google/brya/variants/meliks/Makefile.mk
 create mode 100644 src/mainboard/google/brya/variants/meliks/memory.c

diff --git a/src/mainboard/google/brya/variants/meliks/Makefile.mk b/src/mainboard/google/brya/variants/meliks/Makefile.mk
new file mode 100644
index 0000000000..c44e4f0364
--- /dev/null
+++ b/src/mainboard/google/brya/variants/meliks/Makefile.mk
@@ -0,0 +1,2 @@
+# SPDX-License-Identifier: GPL-2.0-only
+romstage-y += memory.c
diff --git a/src/mainboard/google/brya/variants/meliks/memory.c b/src/mainboard/google/brya/variants/meliks/memory.c
new file mode 100644
index 0000000000..d7f73fb9a0
--- /dev/null
+++ b/src/mainboard/google/brya/variants/meliks/memory.c
@@ -0,0 +1,97 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <baseboard/gpio.h>
+#include <baseboard/variants.h>
+#include <gpio.h>
+#include <soc/romstage.h>
+#include <boardid.h>
+
+static const struct mb_cfg variant_memcfg = {
+	.type = MEM_TYPE_LP5X,
+
+	.rcomp = {
+		/* Baseboard uses only 100ohm Rcomp resistors */
+		.resistor = 100,
+	},
+
+	/* DQ byte map */
+	.lpx_dq_map = {
+		.ddr0 = {
+			.dq0 = { 15, 10,  8, 11, 14, 13,  9, 12 },
+			.dq1 = {  3,  1,  2,  0,  7,  5,  4,  6 },
+		},
+		.ddr1 = {
+			.dq0 = {  7,  0,  3,  2,  1,  4,  6,  5 },
+			.dq1 = { 12,  9,  8, 11, 10, 13, 15, 14 },
+		},
+		.ddr2 = {
+			.dq0 = {  2,  1,  3,  0,  4,  6,  5,  7 },
+			.dq1 = {  8,  9, 10, 11, 13, 14, 12, 15 },
+		},
+		.ddr3 = {
+			.dq0 = {  3,  0,  1,  2,  5,  6,  4,  7 },
+			.dq1 = { 13,  9, 11,  8, 14, 15, 10, 12 },
+		},
+		.ddr4 = {
+			.dq0 = { 15, 10,  8, 11, 14, 13,  9, 12 },
+			.dq1 = {  3,  1,  2,  0,  7,  5,  4,  6 },
+		},
+		.ddr5 = {
+			.dq0 = {  7,  0,  3,  2,  1,  4,  6,  5 },
+			.dq1 = { 12,  9,  8, 11, 10, 13, 15, 14 },
+		},
+		.ddr6 = {
+			.dq0 = {  2,  1,  3,  0,  4,  6,  5,  7 },
+			.dq1 = {  8,  9, 10, 11, 13, 14, 12, 15 },
+		},
+		.ddr7 = {
+			.dq0 = {  3,  0,  1,  2,  5,  6,  4,  7 },
+			.dq1 = { 13,  9, 11,  8, 14, 15, 10, 12 },
+		},
+	},
+
+	/* DQS CPU<>DRAM map */
+	.lpx_dqs_map = {
+		.ddr0 = { .dqs0 = 1, .dqs1 = 0 },
+		.ddr1 = { .dqs0 = 0, .dqs1 = 1 },
+		.ddr2 = { .dqs0 = 0, .dqs1 = 1 },
+		.ddr3 = { .dqs0 = 0, .dqs1 = 1 },
+		.ddr4 = { .dqs0 = 1, .dqs1 = 0 },
+		.ddr5 = { .dqs0 = 0, .dqs1 = 1 },
+		.ddr6 = { .dqs0 = 0, .dqs1 = 1 },
+		.ddr7 = { .dqs0 = 0, .dqs1 = 1 },
+	},
+
+	.lp5x_config = {
+		.ccc_config = 0xff,
+	},
+
+	.ect = 1, /* Early Command Training */
+
+	.UserBd = BOARD_TYPE_MOBILE,
+};
+
+const struct mb_cfg *variant_memory_params(void)
+{
+	return &variant_memcfg;
+}
+
+int variant_memory_sku(void)
+{
+	/*
+	 * Memory configuration board straps
+	 * GPIO_MEM_CONFIG_0	GPP_E1
+	 * GPIO_MEM_CONFIG_1	GPP_E2
+	 * GPIO_MEM_CONFIG_2	GPP_E3
+	 */
+	gpio_t spd_gpios[] = {
+		GPP_E1,
+		GPP_E2,
+		GPP_E3,
+	};
+
+	if (board_id() == BOARD_ID_UNKNOWN)
+		return 0;
+
+	return gpio_base2_value(spd_gpios, ARRAY_SIZE(spd_gpios));
+}

From 76fecd1e55fef5732f99416c1fb6354215c16af2 Mon Sep 17 00:00:00 2001
From: Brian Hsu <Brian_Hsu@pegatron.corp-partner.google.com>
Date: Thu, 20 Feb 2025 12:34:17 +0800
Subject: [PATCH 0190/3886] mb/google/nissa/var/guren: Generate SPD ID for 7
 supported memory parts

Add supported memory parts in mem_parts_used list, and generate SPD ID
for these parts.

DRAM Part Name       Vendor      Model Spec         ID to assign
K3KL8L80CM-MGCT      Samsung     LPDDR5X 7500 32Gb  0 (0000)
K3KL6L60GM-MGCT      Samsung     LPDDR5X 7500 16Gb  1 (0001)
H58G56AK6BX069       SK hynix    LPDDR5 6400 32Gb   2 (0010)
H9JCNNNBK3MLYR-N6E   SK hynix    LPDDR5 6400 16Gb   3 (0011)
H58G66AK6BX070       SK hynix    LPDDR5 6400 64Gb   4 (0100)
K3KL9L90CM-MGCT      Samsung     LPDDR5X 7500 64Gb  5 (0101)
K3LKBKB0BM-MGCP      Samsung     LPDDR5 6400 16Gb   2 (0010)

BUG=b:397149037
BRANCH=firmware-nissa-15217.B
TEST=Run command "go run ./util/spd_tools/src/part_id_gen/\
     part_id_gen.go ADL lp5 \
     src/mainboard/google/brya/variants/guren/memory/ \
     src/mainboard/google/brya/variants/guren/memory/\
     mem_parts_used.txt"

Change-Id: Ibc8626ea51e1143706b8c627f21d33c3ade6a232
Signed-off-by: Brian Hsu <Brian_Hsu@pegatron.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86535
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jayvik Desai <jayvik@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
---
 .../google/brya/variants/guren/memory/Makefile.mk    | 11 +++++++++--
 .../brya/variants/guren/memory/dram_id.generated.txt | 12 ++++++++++++
 .../brya/variants/guren/memory/mem_parts_used.txt    |  7 +++++++
 3 files changed, 28 insertions(+), 2 deletions(-)

diff --git a/src/mainboard/google/brya/variants/guren/memory/Makefile.mk b/src/mainboard/google/brya/variants/guren/memory/Makefile.mk
index eace2e443e..943dfba198 100644
--- a/src/mainboard/google/brya/variants/guren/memory/Makefile.mk
+++ b/src/mainboard/google/brya/variants/guren/memory/Makefile.mk
@@ -1,5 +1,12 @@
 # SPDX-License-Identifier: GPL-2.0-or-later
 # This is an auto-generated file. Do not edit!!
-# Add memory parts in mem_parts_used.txt and run spd_tools to regenerate.
+# Generated by:
+# /tmp/go-build776947141/b001/exe/part_id_gen ADL lp5 src/mainboard/google/brya/variants/guren/memory/ src/mainboard/google/brya/variants/guren/memory/mem_parts_used.txt
 
-SPD_SOURCES = placeholder
+SPD_SOURCES =
+SPD_SOURCES += spd/lp5/set-0/spd-7.hex      # ID = 0(0b0000)  Parts = K3KL8L80CM-MGCT
+SPD_SOURCES += spd/lp5/set-0/spd-9.hex      # ID = 1(0b0001)  Parts = K3KL6L60GM-MGCT
+SPD_SOURCES += spd/lp5/set-0/spd-3.hex      # ID = 2(0b0010)  Parts = H58G56AK6BX069, K3LKBKB0BM-MGCP
+SPD_SOURCES += spd/lp5/set-0/spd-1.hex      # ID = 3(0b0011)  Parts = H9JCNNNBK3MLYR-N6E
+SPD_SOURCES += spd/lp5/set-0/spd-6.hex      # ID = 4(0b0100)  Parts = H58G66AK6BX070
+SPD_SOURCES += spd/lp5/set-0/spd-8.hex      # ID = 5(0b0101)  Parts = K3KL9L90CM-MGCT
diff --git a/src/mainboard/google/brya/variants/guren/memory/dram_id.generated.txt b/src/mainboard/google/brya/variants/guren/memory/dram_id.generated.txt
index fa247902ee..62cd085718 100644
--- a/src/mainboard/google/brya/variants/guren/memory/dram_id.generated.txt
+++ b/src/mainboard/google/brya/variants/guren/memory/dram_id.generated.txt
@@ -1 +1,13 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+# This is an auto-generated file. Do not edit!!
+# Generated by:
+# /tmp/go-build776947141/b001/exe/part_id_gen ADL lp5 src/mainboard/google/brya/variants/guren/memory/ src/mainboard/google/brya/variants/guren/memory/mem_parts_used.txt
+
 DRAM Part Name                 ID to assign
+K3KL8L80CM-MGCT                0 (0000)
+K3KL6L60GM-MGCT                1 (0001)
+H58G56AK6BX069                 2 (0010)
+H9JCNNNBK3MLYR-N6E             3 (0011)
+H58G66AK6BX070                 4 (0100)
+K3KL9L90CM-MGCT                5 (0101)
+K3LKBKB0BM-MGCP                2 (0010)
diff --git a/src/mainboard/google/brya/variants/guren/memory/mem_parts_used.txt b/src/mainboard/google/brya/variants/guren/memory/mem_parts_used.txt
index 2499005682..a7e81204ae 100644
--- a/src/mainboard/google/brya/variants/guren/memory/mem_parts_used.txt
+++ b/src/mainboard/google/brya/variants/guren/memory/mem_parts_used.txt
@@ -9,3 +9,10 @@
 # See util/spd_tools/README.md for more details and instructions.
 
 # Part Name
+K3KL8L80CM-MGCT
+K3KL6L60GM-MGCT
+H58G56AK6BX069
+H9JCNNNBK3MLYR-N6E
+H58G66AK6BX070
+K3KL9L90CM-MGCT
+K3LKBKB0BM-MGCP

From ebd8e77596d6fc3b05c119a03660b4d9db2c1299 Mon Sep 17 00:00:00 2001
From: Hualin Wei <weihualin@huaqin.corp-partner.google.com>
Date: Fri, 21 Feb 2025 20:37:10 +0800
Subject: [PATCH 0191/3886] mb/google/nissa/var/pujjoniru: Modify the gpio of
 GPIO_PCH_WP

According to the circuit schematic diagram, pujjoniru uses GPP_E17
as a write-protected gpio,so it is necessary to add the GPIO_PCH_WP
definition for GPP_E17 in gpio.h.

Duo to cros_gpios under variants/baseboard/nissa/gpio.c will call
GPIO_PCH_WP under variants/baseboard/nissa/include/baseboard/gpio.h,
causing our modifications to not take effect.

In order to achieve the above modification, we follow brya, we
modify DECLARE_CROS_GPIOS in variants/baseboard/nissa/gpio.c to
DECLARE_WEAK_CROS_GPIOS, so that the cros_gpios we defined in
/pujjoniru/gpio.c can overwrite variants/baseboard/nissa/gpio.c

BUG=b:396594296
TEST=wp status update verified by toggling it on and off.

Change-Id: Ic92ff33a5fde50a1a400043b2daba0414eb9e255
Signed-off-by: Hualin Wei <weihualin@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86554
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Qinghong Zeng <zengqinghong@huaqin.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
---
 .../google/brya/variants/baseboard/nissa/gpio.c       |  2 +-
 src/mainboard/google/brya/variants/pujjoniru/gpio.c   | 11 ++++++++++-
 .../brya/variants/pujjoniru/include/variant/gpio.h    |  5 +++--
 3 files changed, 14 insertions(+), 4 deletions(-)

diff --git a/src/mainboard/google/brya/variants/baseboard/nissa/gpio.c b/src/mainboard/google/brya/variants/baseboard/nissa/gpio.c
index 520bbe08eb..9f322f6874 100644
--- a/src/mainboard/google/brya/variants/baseboard/nissa/gpio.c
+++ b/src/mainboard/google/brya/variants/baseboard/nissa/gpio.c
@@ -453,7 +453,7 @@ static const struct cros_gpio cros_gpios[] = {
 	CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME),
 	CROS_GPIO_WP_AH(GPIO_PCH_WP, CROS_GPIO_DEVICE_NAME),
 };
-DECLARE_CROS_GPIOS(cros_gpios);
+DECLARE_WEAK_CROS_GPIOS(cros_gpios);
 
 const struct pad_config *__weak variant_romstage_gpio_table(size_t *num)
 {
diff --git a/src/mainboard/google/brya/variants/pujjoniru/gpio.c b/src/mainboard/google/brya/variants/pujjoniru/gpio.c
index 1241b60c8f..60cf8f2889 100644
--- a/src/mainboard/google/brya/variants/pujjoniru/gpio.c
+++ b/src/mainboard/google/brya/variants/pujjoniru/gpio.c
@@ -1,9 +1,10 @@
 /* SPDX-License-Identifier: GPL-2.0-or-later */
 
-#include <baseboard/gpio.h>
+#include <variant/gpio.h>
 #include <baseboard/variants.h>
 #include <commonlib/helpers.h>
 #include <soc/gpio.h>
+#include <vendorcode/google/chromeos/chromeos.h>
 
 /* Pad configuration in ramstage */
 static const struct pad_config override_gpio_table[] = {
@@ -72,6 +73,8 @@ static const struct pad_config override_gpio_table[] = {
 	PAD_CFG_NF_LOCK(GPP_E12, NONE, NF7, LOCK_CONFIG),
 	/* E13  : NC ==> GSPI1_SOC_MOSI_TCHSCR */
 	PAD_CFG_NF_LOCK(GPP_E13, NONE, NF7, LOCK_CONFIG),
+	/* E17 : THC0_SPI1_IO1 ==> SOC_WP_OD */
+	PAD_CFG_GPI_GPIO_DRIVER_LOCK(GPP_E17, NONE, LOCK_CONFIG),
 	/* E20 : DDP2_CTRLCLK ==> NC */
 	PAD_NC_LOCK(GPP_E20, NONE, LOCK_CONFIG),
 	/* E21 : DDP2_CTRLDATA ==> GPP_E21_STRAP */
@@ -201,3 +204,9 @@ const struct pad_config *variant_romstage_gpio_table(size_t *num)
 	*num = ARRAY_SIZE(romstage_gpio_table);
 	return romstage_gpio_table;
 }
+
+static const struct cros_gpio cros_gpios[] = {
+	CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME),
+	CROS_GPIO_WP_AH(GPIO_PCH_WP, CROS_GPIO_DEVICE_NAME),
+};
+DECLARE_CROS_GPIOS(cros_gpios);
diff --git a/src/mainboard/google/brya/variants/pujjoniru/include/variant/gpio.h b/src/mainboard/google/brya/variants/pujjoniru/include/variant/gpio.h
index c4fe342621..2bfb4bfdab 100644
--- a/src/mainboard/google/brya/variants/pujjoniru/include/variant/gpio.h
+++ b/src/mainboard/google/brya/variants/pujjoniru/include/variant/gpio.h
@@ -3,6 +3,7 @@
 #ifndef VARIANT_GPIO_H
 #define VARIANT_GPIO_H
 
-#include <baseboard/gpio.h>
-
+#undef GPIO_PCH_WP
+/* WP signal to PCH */
+#define GPIO_PCH_WP		GPP_E17
 #endif

From 75759bfada4d29d141b3ec6ac45ef0eb58c7a0d5 Mon Sep 17 00:00:00 2001
From: Hualin Wei <weihualin@huaqin.corp-partner.google.com>
Date: Tue, 25 Feb 2025 09:31:13 +0800
Subject: [PATCH 0192/3886] mb/google/nissa/var/pujjoniru: Add Fn key scancode

The Fn key on pujjoniru emits a scancode of 94 (0x5e).

BUG=b:398943428
TEST=Flash Pujjoniru, boot to Linux kernel, and verify that KEY_FN is
generated when pressed using `evtest`.

Change-Id: I8eb7f253a637741b0aa45aac4d1d59bd0309d559
Signed-off-by: Hualin Wei <weihualin@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86589
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Qinghong Zeng <zengqinghong@huaqin.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
---
 src/mainboard/google/brya/Kconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/src/mainboard/google/brya/Kconfig b/src/mainboard/google/brya/Kconfig
index 1ca5094e92..5ab7d5de6c 100644
--- a/src/mainboard/google/brya/Kconfig
+++ b/src/mainboard/google/brya/Kconfig
@@ -482,6 +482,7 @@ config BOARD_GOOGLE_PUJJONIRU
 	select DRIVERS_GENERIC_GPIO_KEYS
 	select DRIVERS_GFX_GENERIC
 	select DRIVERS_AUDIO_SOF
+	select MAINBOARD_HAS_GOOGLE_STRAUSS_KEYBOARD
 	select SOC_INTEL_TWINLAKE
 
 config BOARD_GOOGLE_QUANDISO

From cb446c0404b43c4678b6d8cbf7e57631e56d28d0 Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Wed, 2 Oct 2024 12:22:20 +0100
Subject: [PATCH 0193/3886] soc/intel/alderlake: Add IRQ mapping for PEG PCI-E
 ports
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

ACPI _PRT method was missing from PEG (SoC PCI-E) links, resulting in
OS complaining about interrupt routing:
    pcieport 0000:00:06.0: can't derive routing for PCI INT A

Tested on `starbook_adl` with Ubuntu 24.04 by running SSD
benchmark with GNOME disks and suspend.

Change-Id: I2e36cee37716d3b003b9ce250f28fdf5581a15bc
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84620
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
---
 src/soc/intel/alderlake/acpi/pcie.asl       | 36 +++++++++++++++++++++
 src/soc/intel/alderlake/acpi/pcie_pch_s.asl | 12 +++++++
 2 files changed, 48 insertions(+)

diff --git a/src/soc/intel/alderlake/acpi/pcie.asl b/src/soc/intel/alderlake/acpi/pcie.asl
index f37c1684b0..50d9464169 100644
--- a/src/soc/intel/alderlake/acpi/pcie.asl
+++ b/src/soc/intel/alderlake/acpi/pcie.asl
@@ -309,16 +309,52 @@ Device (RP12)
 Device (PEG0)
 {
 	Name (_ADR, 0x00060000)
+
+	OperationRegion (RPCS, PCI_Config, 0x4c, 4)
+	Field (RPCS, AnyAcc, NoLock, Preserve)
+	{
+		, 24,
+		RPPN, 8,	/* Root Port Number */
+	}
+
+	Method (_PRT)
+	{
+		Return (IRQM (RPPN))
+	}
 }
 
 Device (PEG1)
 {
 	Name (_ADR, 0x00060002)
+
+	OperationRegion (RPCS, PCI_Config, 0x4c, 4)
+	Field (RPCS, AnyAcc, NoLock, Preserve)
+	{
+		, 24,
+		RPPN, 8,	/* Root Port Number */
+	}
+
+	Method (_PRT)
+	{
+		Return (IRQM (RPPN))
+	}
 }
 
 Device (PEG2)
 {
 	Name (_ADR, 0x00010000)
+
+	OperationRegion (RPCS, PCI_Config, 0x4c, 4)
+	Field (RPCS, AnyAcc, NoLock, Preserve)
+	{
+		, 24,
+		RPPN, 8,	/* Root Port Number */
+	}
+
+	Method (_PRT)
+	{
+		Return (IRQM (RPPN))
+	}
 }
 #endif
 
diff --git a/src/soc/intel/alderlake/acpi/pcie_pch_s.asl b/src/soc/intel/alderlake/acpi/pcie_pch_s.asl
index 5437730af1..c2f22b54c0 100644
--- a/src/soc/intel/alderlake/acpi/pcie_pch_s.asl
+++ b/src/soc/intel/alderlake/acpi/pcie_pch_s.asl
@@ -275,14 +275,26 @@ Device (RP28)
 Device (PEG0)
 {
 	Name (_ADR, 0x00060000)
+	Method (_PRT)
+	{
+		Return (IRQM (1))
+	}
 }
 
 Device (PEG1)
 {
 	Name (_ADR, 0x00010000)
+	Method (_PRT)
+	{
+		Return (IRQM (1))
+	}
 }
 
 Device (PEG2)
 {
 	Name (_ADR, 0x00010001)
+	Method (_PRT)
+	{
+		Return (IRQM (2))
+	}
 }

From 4e99ffcb022104b77476999e8b68743f4d00164a Mon Sep 17 00:00:00 2001
From: Elyes Haouas <ehaouas@noos.fr>
Date: Sat, 11 May 2024 18:48:22 +0200
Subject: [PATCH 0194/3886] intel/broadwell/spd: Use <spd.h> and <dram/ddr3.h>

Use already defined macros in <spd.h> and <dram/ddr3.h>.

TEST=Built purism/librem_bdw (Librem 13 v1) with BUILD_TIMELESS=1, no
change in output ROM.

Change-Id: Id38b97017b43f1421129fed0bb9c1fff5c3423d8
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82315
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/soc/intel/broadwell/spd.c | 31 +++++++++++++------------------
 1 file changed, 13 insertions(+), 18 deletions(-)

diff --git a/src/soc/intel/broadwell/spd.c b/src/soc/intel/broadwell/spd.c
index 1af66f1d67..419334db70 100644
--- a/src/soc/intel/broadwell/spd.c
+++ b/src/soc/intel/broadwell/spd.c
@@ -2,22 +2,17 @@
 
 #include <cbfs.h>
 #include <console/console.h>
+#include <device/dram/ddr3.h>
 #include <soc/pei_data.h>
 #include <soc/pei_wrapper.h>
+#include <spd.h>
 #include <string.h>
 #include <types.h>
 
-#define SPD_DRAM_TYPE		2
-#define SPD_DRAM_DDR3		0x0b
-#define SPD_DRAM_LPDDR3		0xf1
 #define SPD_DENSITY_BANKS	4
 #define SPD_ADDRESSING		5
 #define SPD_ORGANIZATION	7
 #define SPD_BUS_DEV_WIDTH	8
-#define SPD_PART_OFF		128
-#define SPD_PART_LEN		18
-
-#define SPD_LEN			256
 
 static void print_spd_info(uint8_t spd[])
 {
@@ -28,7 +23,7 @@ static void print_spd_info(uint8_t spd[])
 	const int spd_ranks[8] = {  1,  2,  3,  4, -1, -1, -1, -1 };
 	const int spd_devw[8]  = {  4,  8, 16, 32, -1, -1, -1, -1 };
 	const int spd_busw[8]  = {  8, 16, 32, 64, -1, -1, -1, -1 };
-	char spd_name[SPD_PART_LEN+1] = { 0 };
+	char spd_name[SPD_DDR3_PART_LEN + 1] = { 0 };
 
 	int banks = spd_banks[(spd[SPD_DENSITY_BANKS] >> 4) & 7];
 	int capmb = spd_capmb[spd[SPD_DENSITY_BANKS] & 7] * 256;
@@ -40,21 +35,21 @@ static void print_spd_info(uint8_t spd[])
 
 	/* Module type */
 	printk(BIOS_INFO, "SPD: module type is ");
-	switch (spd[SPD_DRAM_TYPE]) {
-	case SPD_DRAM_DDR3:
+	switch (spd[SPD_MEMORY_TYPE]) {
+	case SPD_MEMORY_TYPE_SDRAM_DDR3:
 		printk(BIOS_INFO, "DDR3\n");
 		break;
-	case SPD_DRAM_LPDDR3:
+	case SPD_MEMORY_TYPE_LPDDR3_INTEL:
 		printk(BIOS_INFO, "LPDDR3\n");
 		break;
 	default:
-		printk(BIOS_INFO, "Unknown (%02x)\n", spd[SPD_DRAM_TYPE]);
+		printk(BIOS_INFO, "Unknown (%02x)\n", spd[SPD_MEMORY_TYPE]);
 		break;
 	}
 
 	/* Module Part Number */
-	memcpy(spd_name, &spd[SPD_PART_OFF], SPD_PART_LEN);
-	spd_name[SPD_PART_LEN] = 0;
+	memcpy(spd_name, &spd[SPD_DDR3_PART_NUM], SPD_DDR3_PART_LEN);
+	spd_name[SPD_DDR3_PART_LEN] = 0;
 	printk(BIOS_INFO, "SPD: module part is %s\n", spd_name);
 
 	printk(BIOS_INFO, "SPD: banks %d, ranks %d, rows %d, columns %d, "
@@ -79,15 +74,15 @@ void copy_spd(struct pei_data *pei_data, struct spd_info *spdi)
 	if (!spd_file)
 		die("SPD data not found.");
 
-	if (spd_file_len < SPD_LEN)
+	if (spd_file_len < SPD_SIZE_MAX_DDR3)
 		die("Missing SPD data.");
 
-	if (spd_file_len < ((spdi->spd_index + 1) * SPD_LEN)) {
+	if (spd_file_len < ((spdi->spd_index + 1) * SPD_SIZE_MAX_DDR3)) {
 		printk(BIOS_ERR, "SPD index override to 0 - old hardware?\n");
 		spdi->spd_index = 0;
 	}
 
-	uint8_t *const spd = spd_file + (spdi->spd_index * SPD_LEN);
+	uint8_t *const spd = spd_file + (spdi->spd_index * SPD_SIZE_MAX_DDR3);
 
 	/* Make sure a valid SPD was found */
 	if (spd[0] == 0)
@@ -97,6 +92,6 @@ void copy_spd(struct pei_data *pei_data, struct spd_info *spdi)
 
 	for (size_t i = 0; i < ARRAY_SIZE(spdi->addresses); i++) {
 		if (spdi->addresses[i] == SPD_MEMORY_DOWN)
-			memcpy(pei_data->spd_data[i / 2][i % 2], spd, SPD_LEN);
+			memcpy(pei_data->spd_data[i / 2][i % 2], spd, SPD_SIZE_MAX_DDR3);
 	}
 }

From c1acd33247ac674311b4915af9b3505e8daa8d0e Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Tue, 25 Feb 2025 08:49:50 +0000
Subject: [PATCH 0195/3886] mb/starlabs/starbook/kbl: Update the verb table

Use the newer verb for the ALC2669-VB6 from `starbook/mtl`,
as the current verb table failed to detect headphones being
connected.

Change-Id: Iaa50c6622f3ca75fbeff96300e08eb00e071c8b6
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86594
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
---
 .../starlabs/starbook/variants/kbl/hda_verb.c | 116 +++++++++++++-----
 1 file changed, 82 insertions(+), 34 deletions(-)

diff --git a/src/mainboard/starlabs/starbook/variants/kbl/hda_verb.c b/src/mainboard/starlabs/starbook/variants/kbl/hda_verb.c
index 9c023897f0..7da0991336 100644
--- a/src/mainboard/starlabs/starbook/variants/kbl/hda_verb.c
+++ b/src/mainboard/starlabs/starbook/variants/kbl/hda_verb.c
@@ -1,73 +1,121 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
 #include <device/azalia_device.h>
+#include <stdint.h>
+
+#define DMIC		0x12
+#define SPEAKERS	0x14
+#define HEADPHONE	0x15
+#define MONO		0x17
+#define MIC1		0x18
+#define MIC2		0x19
+#define LINE1		0x1a
+#define LINE2		0x1b
+#define PC_BEEP		0x1d
+#define S_PDIF		0x1e
 
 const u32 cim_verb_data[] = {
 	/* coreboot specific header */
-	0x10ec0269, /* Codec Vendor / Device ID: Realtek ALC269 */
-	0x10ec10d0, /* Subsystem ID */
-	18,	/* Number of jacks (NID entries) */
+	0x10ec0269,	/* Codec Vendor / Device ID: Realtek ALC269 */
+	0x10ec10d0,	/* Subsystem ID */
+	18,		/* Number of verb entries */
 
 	/* Reset Codec First */
 	AZALIA_RESET(0x1),
 
-	/* HDA Codec Subsystem ID Verb-table */
-	AZALIA_SUBVENDOR(0, 0x10ec10d0),
+	/* HDA Codec Subsystem ID */
+	AZALIA_SUBVENDOR(0, 0x1e507038),
 
-	/* Pin Widget Verb-table */
-	AZALIA_PIN_CFG(0, 0x01, 0x00000000),
-	AZALIA_PIN_CFG(0, 0x12, 0x90a61120),
-	AZALIA_PIN_CFG(0, 0x14, 0x90171110),
-	AZALIA_PIN_CFG(0, 0x15, 0x04ab1020),
-	AZALIA_PIN_CFG(0, 0x17, 0x411111F0),
-	AZALIA_PIN_CFG(0, 0x18, 0x04AB1020),
-	AZALIA_PIN_CFG(0, 0x19, 0x411111F0),
-	AZALIA_PIN_CFG(0, 0x1A, 0x411111F0),
-	AZALIA_PIN_CFG(0, 0x1B, 0x411111F0),
-	AZALIA_PIN_CFG(0, 0x1D, 0x411111F0),
-	AZALIA_PIN_CFG(0, 0x1E, 0x411111F0),
+	AZALIA_PIN_CFG(0, 0x01,		0x00000000),
+	AZALIA_PIN_CFG(0, DMIC,		AZALIA_PIN_DESC(					\
+						AZALIA_INTEGRATED,				\
+						AZALIA_INTERNAL | AZALIA_TOP,			\
+						AZALIA_MIC_IN,					\
+						AZALIA_TYPE_UNKNOWN,				\
+						AZALIA_BLACK,					\
+						AZALIA_JACK_PRESENCE_DETECT,			\
+						3,						\
+						0						\
+					)),
+
+	AZALIA_PIN_CFG(0, SPEAKERS,	AZALIA_PIN_DESC(					\
+						AZALIA_INTEGRATED,				\
+						AZALIA_INTERNAL | AZALIA_FRONT,			\
+						AZALIA_SPEAKER,					\
+						AZALIA_TYPE_UNKNOWN,				\
+						AZALIA_BLACK,					\
+						AZALIA_JACK_PRESENCE_DETECT,			\
+						1,						\
+						0						\
+					)),
+	AZALIA_PIN_CFG(0, HEADPHONE,	AZALIA_PIN_DESC(					\
+						AZALIA_JACK,					\
+						AZALIA_EXTERNAL_PRIMARY_CHASSIS | AZALIA_RIGHT,	\
+						AZALIA_HP_OUT,					\
+						AZALIA_STEREO_MONO_1_8,				\
+						AZALIA_BLACK,					\
+						AZALIA_JACK_PRESENCE_DETECT,			\
+						2,						\
+						0						\
+					)),
+	AZALIA_PIN_CFG(0, MONO,		AZALIA_PIN_CFG_NC(0)),
+	AZALIA_PIN_CFG(0, MIC1,		AZALIA_PIN_DESC(					\
+						AZALIA_JACK,					\
+						AZALIA_EXTERNAL_PRIMARY_CHASSIS | AZALIA_RIGHT,	\
+						AZALIA_MIC_IN,					\
+						AZALIA_STEREO_MONO_1_8,				\
+						AZALIA_BLACK,					\
+						AZALIA_JACK_PRESENCE_DETECT,			\
+						4,						\
+						0						\
+					)),
+	AZALIA_PIN_CFG(0, MIC2,		AZALIA_PIN_CFG_NC(0)),
+	AZALIA_PIN_CFG(0, LINE1,	AZALIA_PIN_CFG_NC(0)),
+	AZALIA_PIN_CFG(0, LINE2,	AZALIA_PIN_CFG_NC(0)),
+	AZALIA_PIN_CFG(0, PC_BEEP,	AZALIA_PIN_CFG_NC(0)),
+	AZALIA_PIN_CFG(0, S_PDIF,	AZALIA_PIN_CFG_NC(0)),
 
-	/* ALC269 Default 1 */
 	0x02050018,
-	0x02043984,
-	0x0205001C,
-	0x02040800,
+	0x02040184,
+
+	0x0205001C,
+	0x02044b00,
 
-	/* ALC269 Default 2 */
 	0x02050024,
 	0x02040000,
+
 	0x02050004,
 	0x02040080,
 
-	/* ALC269 Default 3 */
 	0x02050008,
-	0x02040300,
+	0x02040000,
+
 	0x0205000C,
 	0x02043F00,
 
-	/* ALC269 Default 4 */
-	0x02050015,
-	0x02048002,
 	0x02050015,
 	0x02048002,
 
-	/* ALC269 Default 5 */
+	0x02050015,
+	0x02048002,
+
 	0x00C37080,
 	0x00270610,
 	0x00D37080,
 	0x00370610,
 
-	0x8086280b, /* Codec Vendor / Device ID: Intel */
-	0x80860101, /* Subsystem ID */
-	4,	    /* Number of 4 dword sets */
+	0x8086280d,	/* Codec Vendor / Device ID: Intel */
+	0x80860101,	/* Subsystem ID */
+	4,		/* Number of 4 dword sets */
 
 	AZALIA_SUBVENDOR(2, 0x80860101),
 
 	AZALIA_PIN_CFG(2, 0x05, 0x18560010),
-	AZALIA_PIN_CFG(2, 0x06, 0x18560010),
-	AZALIA_PIN_CFG(2, 0x07, 0x18560010),
+	AZALIA_PIN_CFG(2, 0x06, 0x18560020),
+	AZALIA_PIN_CFG(2, 0x07, 0x18560030),
 };
 
-const u32 pc_beep_verbs[] = {};
+const u32 pc_beep_verbs[] = {
+};
 
 AZALIA_ARRAY_SIZES;

From 2e9f1f0990609ffa8dd3633ee5b3a5d7c05168eb Mon Sep 17 00:00:00 2001
From: John Su <john_su@compal.corp-partner.google.com>
Date: Tue, 18 Feb 2025 14:51:40 +0800
Subject: [PATCH 0196/3886] mb/google/brya/var/agah: Remove the AGAH DPTF OEM
 variant

Because the AGAH EC code is based on monitoring adapter current to
choose the corresponding DPTF OEM variable table, but not every
project follows this design. Based on the comment below, the AGAH
EC code was removed in 2023, so remove the AGAH DPTF OEM variant,
allowing each OEM to adjust in EC ASL accordingly.

BUG=b:394177292
BRANCH=None
TEST=None

Change-Id: I2929eaa65a518b06f32e33cc31ae4a01bcfb77e8
Signed-off-by: John Su <john_su@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86493
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/ec/google/chromeec/acpi/ec.asl | 8 --------
 1 file changed, 8 deletions(-)

diff --git a/src/ec/google/chromeec/acpi/ec.asl b/src/ec/google/chromeec/acpi/ec.asl
index 436207cb13..8e241fcfe1 100644
--- a/src/ec/google/chromeec/acpi/ec.asl
+++ b/src/ec/google/chromeec/acpi/ec.asl
@@ -379,14 +379,6 @@ Device (EC0)
 		Printf ("EC: THROTTLE START")
 		\_TZ.THRT (1)
 #endif
-
-#ifdef DPTF_ENABLE_OEM_VARIABLES
-		Local0 = ToInteger(EOVD) & EC_OEM_VARIABLE_DATA_MASK
-		\_SB.DPTF.ODUP(0, Local0)
-		Local0 = \_SB.DPTF.ODGT(0)
-		\_SB.DPTF.ODVP()
-		Notify (\_SB.DPTF, INT3400_ODVP_CHANGED)
-#endif
 	}
 
 	// Throttle Stop

From 632ae13fe0ea459b29d10c25d23d89cfca20e3b7 Mon Sep 17 00:00:00 2001
From: "joel.bueno" <joel.bueno@openchip.com>
Date: Mon, 24 Feb 2025 19:01:59 +0100
Subject: [PATCH 0197/3886] soc/riscv/ucb: Switch to FDT parsing to get memory
 size
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Currently, coreboot tries to manually probe the memory for
the Spike target as part of the SOC_UCB_RISCV target.

However, Spike already passes a pointer to the device tree,
so use it instead to get the memory size (like qemu-riscv does).

TEST=Compile for SPIKE-RISCV and run (cmdline: spike -m1024 build/coreboot.elf)

Change-Id: I5c826ab5e4896e07a78632d5d594377a3d6a7a43
Signed-off-by: joel.bueno <joel.bueno@openchip.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86588
Reviewed-by: Carlos López <carlos.lopezr4096@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
---
 src/soc/ucb/riscv/Kconfig |  1 +
 src/soc/ucb/riscv/cbmem.c | 10 +++++++++-
 2 files changed, 10 insertions(+), 1 deletion(-)

diff --git a/src/soc/ucb/riscv/Kconfig b/src/soc/ucb/riscv/Kconfig
index bd0945e908..e8a8d376ba 100644
--- a/src/soc/ucb/riscv/Kconfig
+++ b/src/soc/ucb/riscv/Kconfig
@@ -9,6 +9,7 @@ config SOC_UCB_RISCV
 	select ARCH_ROMSTAGE_RISCV
 	select ARCH_RAMSTAGE_RISCV
 	select RISCV_USE_ARCH_TIMER
+	select FLATTENED_DEVICE_TREE
 	bool
 	default n
 
diff --git a/src/soc/ucb/riscv/cbmem.c b/src/soc/ucb/riscv/cbmem.c
index 5c423a05bb..ff3f5db3fc 100644
--- a/src/soc/ucb/riscv/cbmem.c
+++ b/src/soc/ucb/riscv/cbmem.c
@@ -1,10 +1,18 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
+#include <assert.h>
 #include <cbmem.h>
 #include <symbols.h>
 #include <ramdetect.h>
+#include <commonlib/device_tree.h>
+#include <mcall.h>
 
 uintptr_t cbmem_top_chipset(void)
 {
-	return (uintptr_t)_dram + (probe_ramsize((uintptr_t)_dram, CONFIG_DRAM_SIZE_MB) * MiB);
+	uint64_t top;
+
+	top = fdt_get_memory_top((void *)HLS()->fdt);
+	ASSERT_MSG(top, "Failed reading memory range from FDT");
+
+	return MIN(top, (uint64_t)4 * GiB - 1);
 }

From f4bf05051855b54621b3b88b88b7d8340cd6a938 Mon Sep 17 00:00:00 2001
From: Patrick Rudolph <patrick.rudolph@9elements.com>
Date: Sat, 22 Feb 2025 11:51:22 +0100
Subject: [PATCH 0198/3886] cpu/x86/64bit: Allow to map more of the address
 space

On AMD platforms the SPI flash can be accessed using the ROM3
mapping in upper MMIO space. To reach the MMIO window the default
page tables must be extended to cover the address by default.

Add support for a SoC specific default address space being used on
x86_64, where the default of 4GiB/512GiB remains.
The size can be specified by the Kconfig CPU_PT_ROM_MAP_GB option.

Used in the following patch to use ROM3 mapping on AMD platforms.

TEST: Access ROM3 bar at 0xfd00000000 on amd/birman+ using x86_64
TEST: x86_64 still works on qemu/q35.

Change-Id: If669426f2b5ae40dd5c62e17f3a0234783b7d462
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86580
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
---
 src/cpu/x86/64bit/pt.S   | 23 ++++++++++++++---------
 src/cpu/x86/64bit/pt1G.S | 12 ++++++++----
 src/cpu/x86/Kconfig      |  9 +++++++++
 3 files changed, 31 insertions(+), 13 deletions(-)

diff --git a/src/cpu/x86/64bit/pt.S b/src/cpu/x86/64bit/pt.S
index 1297296a37..5b10b10118 100644
--- a/src/cpu/x86/64bit/pt.S
+++ b/src/cpu/x86/64bit/pt.S
@@ -20,16 +20,21 @@
 .global PML4E
 .align 4096
 PML4E:
-.quad _GEN_DIR(PDPT)
-
-.align 4096
-PDT: /* identity map 2MiB pages */
-.rept 2048
-.quad _GEN_PAGE(0x200000 * ((. - PDT) >> 3))
+/* For every 512GiB generate a pointer to the corresponding PDPT */
+.rept (CONFIG_CPU_PT_ROM_MAP_GB + 511) / 512
+.quad _GEN_DIR(PDPT + 4096 * ((. - PML4E) >> 3)) /* Point to PDPT */
 .endr
 
 .align 4096
-PDPT: /* Point to PDT */
-.rept 4
-.quad _GEN_DIR(PDT + 4096 * ((. - PDPT) >> 3))
+PDT:
+/* For every 2MiB generate a page entry. In one GiB there are 512 pages. */
+.rept 512 * CONFIG_CPU_PT_ROM_MAP_GB
+.quad _GEN_PAGE(0x200000 * ((. - PDT) >> 3)) /* identity map 2MiB page */
+.endr
+
+.align 4096
+PDPT:
+/* For every 1GiB generate a pointer to the corresponding PDT */
+.rept CONFIG_CPU_PT_ROM_MAP_GB
+.quad _GEN_DIR(PDT + 4096 * ((. - PDPT) >> 3)) /* Point to PDT */
 .endr
diff --git a/src/cpu/x86/64bit/pt1G.S b/src/cpu/x86/64bit/pt1G.S
index 42cdfb17d0..b1f443301d 100644
--- a/src/cpu/x86/64bit/pt1G.S
+++ b/src/cpu/x86/64bit/pt1G.S
@@ -20,10 +20,14 @@
 .global PML4E
 .align 4096
 PML4E:
-.quad _GEN_DIR(PDPT)
+/* For every 512GiB generate a pointer to the corresponding PDPT */
+.rept (CONFIG_CPU_PT_ROM_MAP_GB + 511) / 512
+.quad _GEN_DIR(PDPT + 4096 * ((. - PML4E) >> 3)) /* Point to PDPT */
+.endr
 
 .align 4096
-PDPT: /* identity map 1GiB pages * 512 */
-.rept 512
-.quad _GEN_PAGE(0x40000000 * ((. - PDPT) >> 3))
+PDPT:
+/* For every 1GiB generate a page entry */
+.rept CONFIG_CPU_PT_ROM_MAP_GB
+.quad _GEN_PAGE(0x40000000 * ((. - PDPT) >> 3)) /* identity map 1GiB page */
 .endr
diff --git a/src/cpu/x86/Kconfig b/src/cpu/x86/Kconfig
index 828c0f9ce2..15c884e1e8 100644
--- a/src/cpu/x86/Kconfig
+++ b/src/cpu/x86/Kconfig
@@ -159,6 +159,15 @@ config NEED_SMALL_2MB_PAGE_TABLES
 	  Select this option from boards/SoCs that do not support the Page1GB
 	  CPUID feature (CPUID.80000001H:EDX.bit26).
 
+config CPU_PT_ROM_MAP_GB
+	int
+	default 4 if NEED_SMALL_2MB_PAGE_TABLES
+	default 512
+	help
+	  GiB of the lower address space to identity map when using x86_64
+	  page tables in ROM. Higher values require more space in SPI flash.
+	  SoC can overwrite the value if necessary.
+
 config SMM_ASEG
 	bool
 	default n

From 2494c28a49b9cc575c74920b6d91b3c9fc09d4ab Mon Sep 17 00:00:00 2001
From: Patrick Rudolph <patrick.rudolph@9elements.com>
Date: Sat, 22 Feb 2025 15:11:41 +0100
Subject: [PATCH 0199/3886] soc/amd/glinda: Enable x86_64 support

The code compiles and works fine in x86_64. Thus allow the user
to use x86_64.

TEST: Booted on amd/birman+ to OS using EDK2 as payload.

Change-Id: If1b5d91a376770c0f0e1a4ee46dd625b401fbfa6
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86581
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ana Carolina Cabral <ana.cpmelo95@gmail.com>
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
---
 src/soc/amd/glinda/Kconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/src/soc/amd/glinda/Kconfig b/src/soc/amd/glinda/Kconfig
index 39fb785691..70bdb69d6d 100644
--- a/src/soc/amd/glinda/Kconfig
+++ b/src/soc/amd/glinda/Kconfig
@@ -90,6 +90,7 @@ config SOC_AMD_GLINDA
 	select VBOOT_DEFINE_WIDEVINE_COUNTERS if VBOOT_STARTS_BEFORE_BOOTBLOCK
 	select X86_AMD_FIXED_MTRRS
 	select X86_INIT_NEED_1_SIPI
+	select HAVE_X86_64_SUPPORT
 	help
 	  AMD Glinda support
 

From ec7b6a5a246e648697672de6a265ad9db5591ee9 Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Tue, 28 Jan 2025 14:28:04 +0000
Subject: [PATCH 0200/3886] mb/starlabs/*: Unify IO genx_dec configuration
 across all boards

Change-Id: I614b4cbf6ad502e69f463d71a2536b017c483907
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86188
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/starlabs/lite/variants/glk/devicetree.cb     | 5 +++--
 src/mainboard/starlabs/lite/variants/glkr/devicetree.cb    | 5 +++--
 src/mainboard/starlabs/starbook/variants/adl/devicetree.cb | 6 +++---
 .../starlabs/starbook/variants/adl_n/devicetree.cb         | 4 ++--
 src/mainboard/starlabs/starbook/variants/cml/devicetree.cb | 7 +++----
 src/mainboard/starlabs/starbook/variants/kbl/devicetree.cb | 7 +++----
 src/mainboard/starlabs/starbook/variants/rpl/devicetree.cb | 6 +++---
 src/mainboard/starlabs/starbook/variants/tgl/devicetree.cb | 4 ++--
 .../starlabs/starfighter/variants/rpl/devicetree.cb        | 6 +++---
 .../starlabs/starlite_adl/variants/mk_v/devicetree.cb      | 2 +-
 10 files changed, 26 insertions(+), 26 deletions(-)

diff --git a/src/mainboard/starlabs/lite/variants/glk/devicetree.cb b/src/mainboard/starlabs/lite/variants/glk/devicetree.cb
index 46aedd17b1..a8962af514 100644
--- a/src/mainboard/starlabs/lite/variants/glk/devicetree.cb
+++ b/src/mainboard/starlabs/lite/variants/glk/devicetree.cb
@@ -102,8 +102,9 @@ chip soc/intel/apollolake
 		device ref uart2	on  end
 		device ref spi2		on  end
 		device ref lpc_espi	on
-			register "gen1_dec"			= "0x000c06a1"
-			register "gen2_dec"			= "0x000c0081"
+			register "gen1_dec"			= "0x00040069"
+			register "gen2_dec"			= "0x00fc0201"
+			register "gen3_dec"			= "0x000c0081"
 
 			chip ec/starlabs/merlin
 				# Port pair 4Eh/4Fh
diff --git a/src/mainboard/starlabs/lite/variants/glkr/devicetree.cb b/src/mainboard/starlabs/lite/variants/glkr/devicetree.cb
index c906dbbc83..bd25b0e68d 100644
--- a/src/mainboard/starlabs/lite/variants/glkr/devicetree.cb
+++ b/src/mainboard/starlabs/lite/variants/glkr/devicetree.cb
@@ -102,8 +102,9 @@ chip soc/intel/apollolake
 		device ref uart2	on  end
 		device ref spi2		on  end
 		device ref lpc_espi	on
-			register "gen1_dec"			= "0x000c06a1"
-			register "gen2_dec"			= "0x000c0081"
+			register "gen1_dec"			= "0x00040069"
+			register "gen2_dec"			= "0x00fc0201"
+			register "gen3_dec"			= "0x000c0081"
 
 			chip ec/starlabs/merlin
 				# Port pair 4Eh/4Fh
diff --git a/src/mainboard/starlabs/starbook/variants/adl/devicetree.cb b/src/mainboard/starlabs/starbook/variants/adl/devicetree.cb
index 217c375148..ccbad90b06 100644
--- a/src/mainboard/starlabs/starbook/variants/adl/devicetree.cb
+++ b/src/mainboard/starlabs/starbook/variants/adl/devicetree.cb
@@ -200,9 +200,9 @@ chip soc/intel/alderlake
 		end
 		device ref uart0	on  end
 		device ref pch_espi	on
-			register "gen1_dec"			= "0x00fc0201"
-			register "gen2_dec"			= "0x00000381"
-			register "gen3_dec"			= "0x00000511"
+			register "gen1_dec"			= "0x00040069"
+			register "gen2_dec"			= "0x00fc0201"
+			register "gen3_dec"			= "0x000c0081"
 
 			chip drivers/pc80/tpm
 				device pnp 0c31.0 on end
diff --git a/src/mainboard/starlabs/starbook/variants/adl_n/devicetree.cb b/src/mainboard/starlabs/starbook/variants/adl_n/devicetree.cb
index 2c66936923..5f19e50113 100644
--- a/src/mainboard/starlabs/starbook/variants/adl_n/devicetree.cb
+++ b/src/mainboard/starlabs/starbook/variants/adl_n/devicetree.cb
@@ -189,8 +189,8 @@ chip soc/intel/alderlake
 		device ref uart0	on  end
 		device ref pch_espi	on
 			register "gen1_dec"			= "0x00040069"
-			register "gen2_dec"			= "0x00040069"
-			register "gen3_dec"			= "0x00040069"
+			register "gen2_dec"			= "0x00fc0201"
+			register "gen3_dec"			= "0x000c0081"
 
 			chip drivers/pc80/tpm
 				device pnp 0c31.0 on end
diff --git a/src/mainboard/starlabs/starbook/variants/cml/devicetree.cb b/src/mainboard/starlabs/starbook/variants/cml/devicetree.cb
index 9ab9179882..f0398c7d97 100644
--- a/src/mainboard/starlabs/starbook/variants/cml/devicetree.cb
+++ b/src/mainboard/starlabs/starbook/variants/cml/devicetree.cb
@@ -165,10 +165,9 @@ chip soc/intel/cannonlake
 			smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M.2/M 2280" "SlotDataBusWidth4X"
 		end
 		device ref lpc_espi on
-			register "gen1_dec"			= "0x000c0681"
-			register "gen2_dec"			= "0x000c1641"
-			register "gen3_dec"			= "0x00fc0201"
-			register "gen4_dec"			= "0x000c0081"
+			register "gen1_dec"			= "0x00040069"
+			register "gen2_dec"			= "0x00fc0201"
+			register "gen3_dec"			= "0x000c0081"
 
 			chip ec/starlabs/merlin
 				# Port pair 4Eh/4Fh
diff --git a/src/mainboard/starlabs/starbook/variants/kbl/devicetree.cb b/src/mainboard/starlabs/starbook/variants/kbl/devicetree.cb
index ed61df852c..3ab819ed56 100644
--- a/src/mainboard/starlabs/starbook/variants/kbl/devicetree.cb
+++ b/src/mainboard/starlabs/starbook/variants/kbl/devicetree.cb
@@ -105,10 +105,9 @@ chip soc/intel/skylake
 		end
 		device ref uart0	on  end
 		device ref lpc_espi on
-			register "gen1_dec"			= "0x000c0681"
-			register "gen2_dec"			= "0x000c1641"
-			register "gen3_dec"			= "0x00000069"
-			register "gen4_dec"			= "0x0000006d"
+			register "gen1_dec"			= "0x00040069"
+			register "gen2_dec"			= "0x00fc0201"
+			register "gen3_dec"			= "0x000c0081"
 
 			chip ec/starlabs/merlin
 				# Port pair 4Eh/4Fh
diff --git a/src/mainboard/starlabs/starbook/variants/rpl/devicetree.cb b/src/mainboard/starlabs/starbook/variants/rpl/devicetree.cb
index abc4a7a8ce..52e0411406 100644
--- a/src/mainboard/starlabs/starbook/variants/rpl/devicetree.cb
+++ b/src/mainboard/starlabs/starbook/variants/rpl/devicetree.cb
@@ -211,9 +211,9 @@ chip soc/intel/alderlake
 		end
 		device ref uart0	on  end
 		device ref pch_espi	on
-			register "gen1_dec"			= "0x00fc0201"
-			register "gen2_dec"			= "0x00000381"
-			register "gen3_dec"			= "0x00000511"
+			register "gen1_dec"			= "0x00040069"
+			register "gen2_dec"			= "0x00fc0201"
+			register "gen3_dec"			= "0x000c0081"
 
 			chip drivers/pc80/tpm
 				device pnp 0c31.0 on end
diff --git a/src/mainboard/starlabs/starbook/variants/tgl/devicetree.cb b/src/mainboard/starlabs/starbook/variants/tgl/devicetree.cb
index 938a18ff94..7a7c386996 100644
--- a/src/mainboard/starlabs/starbook/variants/tgl/devicetree.cb
+++ b/src/mainboard/starlabs/starbook/variants/tgl/devicetree.cb
@@ -215,8 +215,8 @@ chip soc/intel/tigerlake
 		end
 		device ref gspi1	on  end
 		device ref pch_espi	on
-			register "gen1_dec"			= "0x000c1641"
-			register "gen2_dec"			= "0x000c0681"
+			register "gen1_dec"			= "0x00040069"
+			register "gen2_dec"			= "0x00fc0201"
 			register "gen3_dec"			= "0x000c0081"
 			chip drivers/pc80/tpm
 				device pnp 0c31.0 on end
diff --git a/src/mainboard/starlabs/starfighter/variants/rpl/devicetree.cb b/src/mainboard/starlabs/starfighter/variants/rpl/devicetree.cb
index 50cb8ae087..c37ff7271f 100644
--- a/src/mainboard/starlabs/starfighter/variants/rpl/devicetree.cb
+++ b/src/mainboard/starlabs/starfighter/variants/rpl/devicetree.cb
@@ -238,9 +238,9 @@ chip soc/intel/alderlake
 		end
 		device ref uart0	on  end
 		device ref pch_espi	on
-			register "gen1_dec"			= "0x00fc0201"
-			register "gen2_dec"			= "0x00000381"
-			register "gen3_dec"			= "0x00000511"
+			register "gen1_dec"			= "0x00040069"
+			register "gen2_dec"			= "0x00fc0201"
+			register "gen3_dec"			= "0x000c0081"
 
 			chip drivers/pc80/tpm
 				device pnp 0c31.0 on end
diff --git a/src/mainboard/starlabs/starlite_adl/variants/mk_v/devicetree.cb b/src/mainboard/starlabs/starlite_adl/variants/mk_v/devicetree.cb
index 0c9b7a5dde..5b8bd2c2d0 100644
--- a/src/mainboard/starlabs/starlite_adl/variants/mk_v/devicetree.cb
+++ b/src/mainboard/starlabs/starlite_adl/variants/mk_v/devicetree.cb
@@ -175,7 +175,7 @@ chip soc/intel/alderlake
 		end
 		device ref uart0	on  end
 		device ref pch_espi	on
-			register "gen1_dec"				= "0x3c030070"
+			register "gen1_dec"				= "0x00040069"
 			register "gen2_dec"				= "0x00fc0201"
 			register "gen3_dec"				= "0x000c0081"
 

From ed85f0128176e782b36b7a634271816b8c7e0231 Mon Sep 17 00:00:00 2001
From: Elyes Haouas <ehaouas@noos.fr>
Date: Tue, 1 Nov 2022 13:29:09 +0100
Subject: [PATCH 0201/3886] mb/*/*/irq_tables.c: Use PCI_DEVFN(dev, fn)

Change-Id: Ic97bf7c8f04edbb56f200c34060d22a8c5fb7ec2
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69066
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
---
 .../asus/p2b/variants/p2b-d/irq_tables.c      | 17 ++++----
 .../asus/p2b/variants/p2b-ds/irq_tables.c     | 19 +++++----
 .../asus/p2b/variants/p2b-f/irq_tables.c      | 19 +++++----
 .../asus/p2b/variants/p2b-ls/irq_tables.c     | 21 +++++-----
 .../asus/p2b/variants/p2b/irq_tables.c        | 17 ++++----
 .../asus/p2b/variants/p3b-f/irq_tables.c      | 21 +++++-----
 .../emulation/qemu-i440fx/irq_tables.c        | 17 ++++----
 src/mainboard/getac/p470/irq_tables.c         | 41 ++++++++++---------
 src/mainboard/ibase/mb899/irq_tables.c        | 41 ++++++++++---------
 src/mainboard/intel/d945gclf/irq_tables.c     | 41 ++++++++++---------
 src/mainboard/kontron/986lcd-m/irq_tables.c   | 41 ++++++++++---------
 src/mainboard/lenovo/x60/irq_tables.c         | 33 +++++++--------
 src/mainboard/roda/rk886ex/irq_tables.c       | 41 ++++++++++---------
 13 files changed, 191 insertions(+), 178 deletions(-)

diff --git a/src/mainboard/asus/p2b/variants/p2b-d/irq_tables.c b/src/mainboard/asus/p2b/variants/p2b-d/irq_tables.c
index 358260b67d..4cab6be0f8 100644
--- a/src/mainboard/asus/p2b/variants/p2b-d/irq_tables.c
+++ b/src/mainboard/asus/p2b/variants/p2b-d/irq_tables.c
@@ -1,13 +1,14 @@
 /* SPDX-License-Identifier: GPL-2.0-or-later */
 
 #include <arch/pirq_routing.h>
+#include <device/pci_def.h>
 
 static const struct irq_routing_table intel_irq_routing_table = {
 	PIRQ_SIGNATURE,
 	PIRQ_VERSION,
 	32 + 16 * CONFIG_IRQ_SLOT_COUNT,/* Max. number of devices on the bus */
 	0x00,			/* Interrupt router bus */
-	(0x04 << 3) | 0x0,	/* Interrupt router device */
+	PCI_DEVFN(0x04, 0),	/* Interrupt router device */
 	0,			/* IRQs devoted exclusively to PCI usage */
 	0x8086,			/* Vendor */
 	0x122e,			/* Device */
@@ -16,13 +17,13 @@ static const struct irq_routing_table intel_irq_routing_table = {
 	0x54,			/* Checksum */
 	/* clang-format off */
 	{
-		/* bus,        dev | fn,   {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */
-		{0x00, (0x0c << 3) | 0x0, {{0x60, 0x1eb8}, {0x61, 0x1eb8}, {0x62, 0x1eb8}, {0x63, 0x1eb8}}, 0x1, 0x0},
-		{0x00, (0x0b << 3) | 0x0, {{0x61, 0x1eb8}, {0x62, 0x1eb8}, {0x63, 0x1eb8}, {0x60, 0x1eb8}}, 0x2, 0x0},
-		{0x00, (0x0a << 3) | 0x0, {{0x62, 0x1eb8}, {0x63, 0x1eb8}, {0x60, 0x1eb8}, {0x61, 0x1eb8}}, 0x3, 0x0},
-		{0x00, (0x09 << 3) | 0x0, {{0x63, 0x1eb8}, {0x60, 0x1eb8}, {0x61, 0x1eb8}, {0x62, 0x1eb8}}, 0x4, 0x0},
-		{0x00, (0x04 << 3) | 0x0, {{0x60, 0x1eb8}, {0x61, 0x1eb8}, {0x62, 0x1eb8}, {0x63, 0x1eb8}}, 0x0, 0x0},
-		{0x00, (0x01 << 3) | 0x0, {{0x60, 0x1eb8}, {0x61, 0x1eb8}, {0x62, 0x1eb8}, {0x63, 0x1eb8}}, 0x0, 0x0},
+	       /* bus, PCI_DEVFN(dev, fn),  {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */
+		{0x00, PCI_DEVFN(0x0c, 0), {{0x60, 0x1eb8}, {0x61, 0x1eb8}, {0x62, 0x1eb8}, {0x63, 0x1eb8}}, 0x1, 0x0},
+		{0x00, PCI_DEVFN(0x0b, 0), {{0x61, 0x1eb8}, {0x62, 0x1eb8}, {0x63, 0x1eb8}, {0x60, 0x1eb8}}, 0x2, 0x0},
+		{0x00, PCI_DEVFN(0x0a, 0), {{0x62, 0x1eb8}, {0x63, 0x1eb8}, {0x60, 0x1eb8}, {0x61, 0x1eb8}}, 0x3, 0x0},
+		{0x00, PCI_DEVFN(0x09, 0), {{0x63, 0x1eb8}, {0x60, 0x1eb8}, {0x61, 0x1eb8}, {0x62, 0x1eb8}}, 0x4, 0x0},
+		{0x00, PCI_DEVFN(0x04, 0), {{0x60, 0x1eb8}, {0x61, 0x1eb8}, {0x62, 0x1eb8}, {0x63, 0x1eb8}}, 0x0, 0x0},
+		{0x00, PCI_DEVFN(0x01, 0), {{0x60, 0x1eb8}, {0x61, 0x1eb8}, {0x62, 0x1eb8}, {0x63, 0x1eb8}}, 0x0, 0x0},
 	}
 	/* clang-format on */
 };
diff --git a/src/mainboard/asus/p2b/variants/p2b-ds/irq_tables.c b/src/mainboard/asus/p2b/variants/p2b-ds/irq_tables.c
index 0b78c0bd0e..863db32d0d 100644
--- a/src/mainboard/asus/p2b/variants/p2b-ds/irq_tables.c
+++ b/src/mainboard/asus/p2b/variants/p2b-ds/irq_tables.c
@@ -1,13 +1,14 @@
 /* SPDX-License-Identifier: GPL-2.0-or-later */
 
 #include <arch/pirq_routing.h>
+#include <device/pci_def.h>
 
 static const struct irq_routing_table intel_irq_routing_table = {
 	PIRQ_SIGNATURE,
 	PIRQ_VERSION,
 	32 + 16 * CONFIG_IRQ_SLOT_COUNT,/* Max. number of devices on the bus */
 	0x00,			/* Interrupt router bus */
-	(0x04 << 3) | 0x0,	/* Interrupt router device */
+	PCI_DEVFN(0x04, 0),	/* Interrupt router device */
 	0,			/* IRQs devoted exclusively to PCI usage */
 	0x8086,			/* Vendor */
 	0x122e,			/* Device */
@@ -16,14 +17,14 @@ static const struct irq_routing_table intel_irq_routing_table = {
 	0x36,			/* Checksum */
 	/* clang-format off */
 	{
-		/* bus,        dev | fn,   {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */
-		{0x00, (0x0c << 3) | 0x0, {{0x60, 0x1eb8}, {0x61, 0x1eb8}, {0x62, 0x1eb8}, {0x63, 0x1eb8}}, 0x1, 0x0},
-		{0x00, (0x0b << 3) | 0x0, {{0x61, 0x1eb8}, {0x62, 0x1eb8}, {0x63, 0x1eb8}, {0x60, 0x1eb8}}, 0x2, 0x0},
-		{0x00, (0x0a << 3) | 0x0, {{0x62, 0x1eb8}, {0x63, 0x1eb8}, {0x60, 0x1eb8}, {0x61, 0x1eb8}}, 0x3, 0x0},
-		{0x00, (0x09 << 3) | 0x0, {{0x63, 0x1eb8}, {0x60, 0x1eb8}, {0x61, 0x1eb8}, {0x62, 0x1eb8}}, 0x4, 0x0},
-		{0x00, (0x04 << 3) | 0x0, {{0x60, 0x1eb8}, {0x61, 0x1eb8}, {0x62, 0x1eb8}, {0x63, 0x1eb8}}, 0x0, 0x0},
-		{0x00, (0x01 << 3) | 0x0, {{0x60, 0x1eb8}, {0x61, 0x1eb8}, {0x62, 0x1eb8}, {0x63, 0x1eb8}}, 0x0, 0x0},
-		{0x00, (0x06 << 3) | 0x0, {{0x63, 0x1eb8}, {0x60, 0x1eb8}, {0x61, 0x1eb8}, {0x62, 0x1eb8}}, 0x0, 0x0},
+	       /* bus, PCI_DEVFN(dev, fn),  link, bitmap},  {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */
+		{0x00, PCI_DEVFN(0x0c, 0), {{0x60, 0x1eb8}, {0x61, 0x1eb8}, {0x62, 0x1eb8}, {0x63, 0x1eb8}}, 0x1, 0x0},
+		{0x00, PCI_DEVFN(0x0b, 0), {{0x61, 0x1eb8}, {0x62, 0x1eb8}, {0x63, 0x1eb8}, {0x60, 0x1eb8}}, 0x2, 0x0},
+		{0x00, PCI_DEVFN(0x0a, 0), {{0x62, 0x1eb8}, {0x63, 0x1eb8}, {0x60, 0x1eb8}, {0x61, 0x1eb8}}, 0x3, 0x0},
+		{0x00, PCI_DEVFN(0x09, 0), {{0x63, 0x1eb8}, {0x60, 0x1eb8}, {0x61, 0x1eb8}, {0x62, 0x1eb8}}, 0x4, 0x0},
+		{0x00, PCI_DEVFN(0x04, 0), {{0x60, 0x1eb8}, {0x61, 0x1eb8}, {0x62, 0x1eb8}, {0x63, 0x1eb8}}, 0x0, 0x0},
+		{0x00, PCI_DEVFN(0x01, 0), {{0x60, 0x1eb8}, {0x61, 0x1eb8}, {0x62, 0x1eb8}, {0x63, 0x1eb8}}, 0x0, 0x0},
+		{0x00, PCI_DEVFN(0x06, 0), {{0x63, 0x1eb8}, {0x60, 0x1eb8}, {0x61, 0x1eb8}, {0x62, 0x1eb8}}, 0x0, 0x0},
 	}
 	/* clang-format on */
 };
diff --git a/src/mainboard/asus/p2b/variants/p2b-f/irq_tables.c b/src/mainboard/asus/p2b/variants/p2b-f/irq_tables.c
index 8c57ca6e40..c6b1d27a2c 100644
--- a/src/mainboard/asus/p2b/variants/p2b-f/irq_tables.c
+++ b/src/mainboard/asus/p2b/variants/p2b-f/irq_tables.c
@@ -1,13 +1,14 @@
 /* SPDX-License-Identifier: GPL-2.0-or-later */
 
 #include <arch/pirq_routing.h>
+#include <device/pci_def.h>
 
 static const struct irq_routing_table intel_irq_routing_table = {
 	PIRQ_SIGNATURE,
 	PIRQ_VERSION,
 	32 + 16 * CONFIG_IRQ_SLOT_COUNT,/* Max. number of devices on the bus */
 	0x00,			/* Interrupt router bus */
-	(0x04 << 3) | 0x0,	/* Interrupt router device */
+	PCI_DEVFN(0x04, 0),	/* Interrupt router device */
 	0,			/* IRQs devoted exclusively to PCI usage */
 	0x8086,			/* Vendor */
 	0x122e,			/* Device */
@@ -16,14 +17,14 @@ static const struct irq_routing_table intel_irq_routing_table = {
 	0xf9,			/* Checksum */
 	/* clang-format off */
 	{
-		/* bus,       dev|fn,   {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap},  slot, rfu */
-		{0x00,(0x0c << 3)|0x0, {{0x60, 0x1eb8}, {0x61, 0x1eb8}, {0x62, 0x1eb8}, {0x63, 0x01eb8}}, 0x1, 0x0},
-		{0x00,(0x0b << 3)|0x0, {{0x61, 0x1eb8}, {0x62, 0x1eb8}, {0x63, 0x1eb8}, {0x60, 0x01eb8}}, 0x2, 0x0},
-		{0x00,(0x0a << 3)|0x0, {{0x62, 0x1eb8}, {0x63, 0x1eb8}, {0x60, 0x1eb8}, {0x61, 0x01eb8}}, 0x3, 0x0},
-		{0x00,(0x09 << 3)|0x0, {{0x63, 0x1eb8}, {0x60, 0x1eb8}, {0x61, 0x1eb8}, {0x62, 0x01eb8}}, 0x4, 0x0},
-		{0x00,(0x0d << 3)|0x0, {{0x63, 0x1eb8}, {0x60, 0x1eb8}, {0x61, 0x1eb8}, {0x62, 0x01eb8}}, 0x5, 0x0},
-		{0x00,(0x04 << 3)|0x0, {{0x60, 0x1eb8}, {0x61, 0x1eb8}, {0x62, 0x1eb8}, {0x63, 0x01eb8}}, 0x0, 0x0},
-		{0x00,(0x01 << 3)|0x0, {{0x60, 0x1eb8}, {0x61, 0x1eb8}, {0x62, 0x1eb8}, {0x63, 0x01eb8}}, 0x0, 0x0},
+	       /* bus,PCI_DEVFN(dev, fn),  {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap},  slot, rfu */
+		{0x00,PCI_DEVFN(0x0c, 0), {{0x60, 0x1eb8}, {0x61, 0x1eb8}, {0x62, 0x1eb8}, {0x63, 0x01eb8}}, 0x1, 0x0},
+		{0x00,PCI_DEVFN(0x0b, 0), {{0x61, 0x1eb8}, {0x62, 0x1eb8}, {0x63, 0x1eb8}, {0x60, 0x01eb8}}, 0x2, 0x0},
+		{0x00,PCI_DEVFN(0x0a, 0), {{0x62, 0x1eb8}, {0x63, 0x1eb8}, {0x60, 0x1eb8}, {0x61, 0x01eb8}}, 0x3, 0x0},
+		{0x00,PCI_DEVFN(0x09, 0), {{0x63, 0x1eb8}, {0x60, 0x1eb8}, {0x61, 0x1eb8}, {0x62, 0x01eb8}}, 0x4, 0x0},
+		{0x00,PCI_DEVFN(0x0d, 0), {{0x63, 0x1eb8}, {0x60, 0x1eb8}, {0x61, 0x1eb8}, {0x62, 0x01eb8}}, 0x5, 0x0},
+		{0x00,PCI_DEVFN(0x04, 0), {{0x60, 0x1eb8}, {0x61, 0x1eb8}, {0x62, 0x1eb8}, {0x63, 0x01eb8}}, 0x0, 0x0},
+		{0x00,PCI_DEVFN(0x01, 0), {{0x60, 0x1eb8}, {0x61, 0x1eb8}, {0x62, 0x1eb8}, {0x63, 0x01eb8}}, 0x0, 0x0},
 	}
 	/* clang-format on */
 };
diff --git a/src/mainboard/asus/p2b/variants/p2b-ls/irq_tables.c b/src/mainboard/asus/p2b/variants/p2b-ls/irq_tables.c
index 1bad19bbfc..e03af5e2ea 100644
--- a/src/mainboard/asus/p2b/variants/p2b-ls/irq_tables.c
+++ b/src/mainboard/asus/p2b/variants/p2b-ls/irq_tables.c
@@ -1,13 +1,14 @@
 /* SPDX-License-Identifier: GPL-2.0-or-later */
 
 #include <arch/pirq_routing.h>
+#include <device/pci_def.h>
 
 static const struct irq_routing_table intel_irq_routing_table = {
 	PIRQ_SIGNATURE,
 	PIRQ_VERSION,
 	32 + 16 * CONFIG_IRQ_SLOT_COUNT,/* Max. number of devices on the bus */
 	0x00,			/* Interrupt router bus */
-	(0x04 << 3) | 0x0,	/* Interrupt router device */
+	PCI_DEVFN(0x04, 0),	/* Interrupt router device */
 	0,			/* IRQs devoted exclusively to PCI usage */
 	0x8086,			/* Vendor */
 	0x122e,			/* Device */
@@ -19,15 +20,15 @@ static const struct irq_routing_table intel_irq_routing_table = {
 				 */
 	/* clang-format off */
 	{
-		/* bus,        dev | fn,   {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */
-		{0x00, (0x0c << 3) | 0x0, {{0x60, 0x1eb8}, {0x61, 0x1eb8}, {0x62, 0x1eb8}, {0x63, 0x1eb8}}, 0x1, 0x0},
-		{0x00, (0x0b << 3) | 0x0, {{0x61, 0x1eb8}, {0x62, 0x1eb8}, {0x63, 0x1eb8}, {0x60, 0x1eb8}}, 0x2, 0x0},
-		{0x00, (0x0a << 3) | 0x0, {{0x62, 0x1eb8}, {0x63, 0x1eb8}, {0x60, 0x1eb8}, {0x61, 0x1eb8}}, 0x3, 0x0},
-		{0x00, (0x09 << 3) | 0x0, {{0x63, 0x1eb8}, {0x60, 0x1eb8}, {0x61, 0x1eb8}, {0x62, 0x1eb8}}, 0x4, 0x0},
-		{0x00, (0x04 << 3) | 0x0, {{0x60, 0x1eb8}, {0x61, 0x1eb8}, {0x62, 0x1eb8}, {0x63, 0x1eb8}}, 0x0, 0x0},
-		{0x00, (0x01 << 3) | 0x0, {{0x60, 0x1eb8}, {0x61, 0x1eb8}, {0x62, 0x1eb8}, {0x63, 0x1eb8}}, 0x0, 0x0},
-		{0x00, (0x06 << 3) | 0x0, {{0x63, 0x1eb8}, {0x60, 0x1eb8}, {0x61, 0x1eb8}, {0x62, 0x1eb8}}, 0x0, 0x0},
-		{0x00, (0x07 << 3) | 0x0, {{0x62, 0x1eb8}, {0x63, 0x1eb8}, {0x60, 0x1eb8}, {0x61, 0x1eb8}}, 0x0, 0x0},
+	       /* bus, PCI_DEVFN(dev, fn),  {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */
+		{0x00, PCI_DEVFN(0x0c, 0), {{0x60, 0x1eb8}, {0x61, 0x1eb8}, {0x62, 0x1eb8}, {0x63, 0x1eb8}}, 0x1, 0x0},
+		{0x00, PCI_DEVFN(0x0b, 0), {{0x61, 0x1eb8}, {0x62, 0x1eb8}, {0x63, 0x1eb8}, {0x60, 0x1eb8}}, 0x2, 0x0},
+		{0x00, PCI_DEVFN(0x0a, 0), {{0x62, 0x1eb8}, {0x63, 0x1eb8}, {0x60, 0x1eb8}, {0x61, 0x1eb8}}, 0x3, 0x0},
+		{0x00, PCI_DEVFN(0x09, 0), {{0x63, 0x1eb8}, {0x60, 0x1eb8}, {0x61, 0x1eb8}, {0x62, 0x1eb8}}, 0x4, 0x0},
+		{0x00, PCI_DEVFN(0x04, 0), {{0x60, 0x1eb8}, {0x61, 0x1eb8}, {0x62, 0x1eb8}, {0x63, 0x1eb8}}, 0x0, 0x0},
+		{0x00, PCI_DEVFN(0x01, 0), {{0x60, 0x1eb8}, {0x61, 0x1eb8}, {0x62, 0x1eb8}, {0x63, 0x1eb8}}, 0x0, 0x0},
+		{0x00, PCI_DEVFN(0x06, 0), {{0x63, 0x1eb8}, {0x60, 0x1eb8}, {0x61, 0x1eb8}, {0x62, 0x1eb8}}, 0x0, 0x0},
+		{0x00, PCI_DEVFN(0x07, 0), {{0x62, 0x1eb8}, {0x63, 0x1eb8}, {0x60, 0x1eb8}, {0x61, 0x1eb8}}, 0x0, 0x0},
 	}
 	/* clang-format on */
 };
diff --git a/src/mainboard/asus/p2b/variants/p2b/irq_tables.c b/src/mainboard/asus/p2b/variants/p2b/irq_tables.c
index 8967f845cf..0c78d6ff10 100644
--- a/src/mainboard/asus/p2b/variants/p2b/irq_tables.c
+++ b/src/mainboard/asus/p2b/variants/p2b/irq_tables.c
@@ -1,13 +1,14 @@
 /* SPDX-License-Identifier: GPL-2.0-or-later */
 
 #include <arch/pirq_routing.h>
+#include <device/pci_def.h>
 
 static const struct irq_routing_table intel_irq_routing_table = {
 	PIRQ_SIGNATURE,
 	PIRQ_VERSION,
 	32 + 16 * CONFIG_IRQ_SLOT_COUNT,/* Max. number of devices on the bus */
 	0x00,			/* Interrupt router bus */
-	(0x04 << 3) | 0x0,	/* Interrupt router device */
+	PCI_DEVFN(0x04, 0),	/* Interrupt router device */
 	0,			/* IRQs devoted exclusively to PCI usage */
 	0x8086,			/* Vendor */
 	0x122e,			/* Device */
@@ -16,13 +17,13 @@ static const struct irq_routing_table intel_irq_routing_table = {
 	0x54,			/* Checksum */
 	/* clang-format off */
 	{
-		/* bus,       dev|fn,   {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap},  slot, rfu */
-		{0x00,(0x0c << 3)|0x0, {{0x60, 0x1eb8}, {0x61, 0x1eb8}, {0x62, 0x1eb8}, {0x63, 0x01eb8}}, 0x1, 0x0},
-		{0x00,(0x0b << 3)|0x0, {{0x61, 0x1eb8}, {0x62, 0x1eb8}, {0x63, 0x1eb8}, {0x60, 0x01eb8}}, 0x2, 0x0},
-		{0x00,(0x0a << 3)|0x0, {{0x62, 0x1eb8}, {0x63, 0x1eb8}, {0x60, 0x1eb8}, {0x61, 0x01eb8}}, 0x3, 0x0},
-		{0x00,(0x09 << 3)|0x0, {{0x63, 0x1eb8}, {0x60, 0x1eb8}, {0x61, 0x1eb8}, {0x62, 0x01eb8}}, 0x4, 0x0},
-		{0x00,(0x04 << 3)|0x0, {{0x60, 0x1eb8}, {0x61, 0x1eb8}, {0x62, 0x1eb8}, {0x63, 0x01eb8}}, 0x0, 0x0},
-		{0x00,(0x01 << 3)|0x0, {{0x60, 0x1eb8}, {0x61, 0x1eb8}, {0x62, 0x1eb8}, {0x63, 0x01eb8}}, 0x0, 0x0},
+	       /* bus,PCI_DEVFN(dev, fn),  {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap},  slot, rfu */
+		{0x00,PCI_DEVFN(0x0c, 0), {{0x60, 0x1eb8}, {0x61, 0x1eb8}, {0x62, 0x1eb8}, {0x63, 0x01eb8}}, 0x1, 0x0},
+		{0x00,PCI_DEVFN(0x0b, 0), {{0x61, 0x1eb8}, {0x62, 0x1eb8}, {0x63, 0x1eb8}, {0x60, 0x01eb8}}, 0x2, 0x0},
+		{0x00,PCI_DEVFN(0x0a, 0), {{0x62, 0x1eb8}, {0x63, 0x1eb8}, {0x60, 0x1eb8}, {0x61, 0x01eb8}}, 0x3, 0x0},
+		{0x00,PCI_DEVFN(0x09, 0), {{0x63, 0x1eb8}, {0x60, 0x1eb8}, {0x61, 0x1eb8}, {0x62, 0x01eb8}}, 0x4, 0x0},
+		{0x00,PCI_DEVFN(0x04, 0), {{0x60, 0x1eb8}, {0x61, 0x1eb8}, {0x62, 0x1eb8}, {0x63, 0x01eb8}}, 0x0, 0x0},
+		{0x00,PCI_DEVFN(0x01, 0), {{0x60, 0x1eb8}, {0x61, 0x1eb8}, {0x62, 0x1eb8}, {0x63, 0x01eb8}}, 0x0, 0x0},
 	}
 	/* clang-format on */
 };
diff --git a/src/mainboard/asus/p2b/variants/p3b-f/irq_tables.c b/src/mainboard/asus/p2b/variants/p3b-f/irq_tables.c
index 39c2058672..3e2284e549 100644
--- a/src/mainboard/asus/p2b/variants/p3b-f/irq_tables.c
+++ b/src/mainboard/asus/p2b/variants/p3b-f/irq_tables.c
@@ -1,13 +1,14 @@
 /* SPDX-License-Identifier: GPL-2.0-or-later */
 
 #include <arch/pirq_routing.h>
+#include <device/pci_def.h>
 
 static const struct irq_routing_table intel_irq_routing_table = {
 	PIRQ_SIGNATURE,
 	PIRQ_VERSION,
 	32 + 16 * CONFIG_IRQ_SLOT_COUNT,/* Max. number of devices on the bus */
 	0x00,			/* Interrupt router bus */
-	(0x04 << 3) | 0x0,	/* Interrupt router device */
+	PCI_DEVFN(0x04, 0),	/* Interrupt router device */
 	0,			/* IRQs devoted exclusively to PCI usage */
 	0x8086,			/* Vendor */
 	0x122e,			/* Device */
@@ -16,15 +17,15 @@ static const struct irq_routing_table intel_irq_routing_table = {
 	0x95,			/* Checksum */
 	/* clang-format off */
 	{
-		/* bus,       dev|fn,   {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap},  slot, rfu */
-		{0x00,(0x0c << 3)|0x0, {{0x60, 0x1eb8}, {0x61, 0x1eb8}, {0x62, 0x1eb8}, {0x63, 0x01eb8}}, 0x1, 0x0},
-		{0x00,(0x0b << 3)|0x0, {{0x61, 0x1eb8}, {0x62, 0x1eb8}, {0x63, 0x1eb8}, {0x60, 0x01eb8}}, 0x2, 0x0},
-		{0x00,(0x0a << 3)|0x0, {{0x62, 0x1eb8}, {0x63, 0x1eb8}, {0x60, 0x1eb8}, {0x61, 0x01eb8}}, 0x3, 0x0},
-		{0x00,(0x09 << 3)|0x0, {{0x63, 0x1eb8}, {0x60, 0x1eb8}, {0x61, 0x1eb8}, {0x62, 0x01eb8}}, 0x4, 0x0},
-		{0x00,(0x0d << 3)|0x0, {{0x63, 0x1eb8}, {0x60, 0x1eb8}, {0x61, 0x1eb8}, {0x62, 0x01eb8}}, 0x5, 0x0},
-		{0x00,(0x0e << 3)|0x0, {{0x62, 0x1eb8}, {0x63, 0x1eb8}, {0x60, 0x1eb8}, {0x61, 0x01eb8}}, 0x6, 0x0},
-		{0x00,(0x04 << 3)|0x0, {{0x60, 0x1eb8}, {0x61, 0x1eb8}, {0x62, 0x1eb8}, {0x63, 0x01eb8}}, 0x0, 0x0},
-		{0x00,(0x01 << 3)|0x0, {{0x60, 0x1eb8}, {0x61, 0x1eb8}, {0x62, 0x1eb8}, {0x63, 0x01eb8}}, 0x0, 0x0},
+	       /* bus,PCI_DEVFN(dev, fn),  {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap},  slot, rfu */
+		{0x00,PCI_DEVFN(0x0c, 0), {{0x60, 0x1eb8}, {0x61, 0x1eb8}, {0x62, 0x1eb8}, {0x63, 0x01eb8}}, 0x1, 0x0},
+		{0x00,PCI_DEVFN(0x0b, 0), {{0x61, 0x1eb8}, {0x62, 0x1eb8}, {0x63, 0x1eb8}, {0x60, 0x01eb8}}, 0x2, 0x0},
+		{0x00,PCI_DEVFN(0x0a, 0), {{0x62, 0x1eb8}, {0x63, 0x1eb8}, {0x60, 0x1eb8}, {0x61, 0x01eb8}}, 0x3, 0x0},
+		{0x00,PCI_DEVFN(0x09, 0), {{0x63, 0x1eb8}, {0x60, 0x1eb8}, {0x61, 0x1eb8}, {0x62, 0x01eb8}}, 0x4, 0x0},
+		{0x00,PCI_DEVFN(0x0d, 0), {{0x63, 0x1eb8}, {0x60, 0x1eb8}, {0x61, 0x1eb8}, {0x62, 0x01eb8}}, 0x5, 0x0},
+		{0x00,PCI_DEVFN(0x0e, 0), {{0x62, 0x1eb8}, {0x63, 0x1eb8}, {0x60, 0x1eb8}, {0x61, 0x01eb8}}, 0x6, 0x0},
+		{0x00,PCI_DEVFN(0x04, 0), {{0x60, 0x1eb8}, {0x61, 0x1eb8}, {0x62, 0x1eb8}, {0x63, 0x01eb8}}, 0x0, 0x0},
+		{0x00,PCI_DEVFN(0x01, 0), {{0x60, 0x1eb8}, {0x61, 0x1eb8}, {0x62, 0x1eb8}, {0x63, 0x01eb8}}, 0x0, 0x0},
 	}
 	/* clang-format on */
 };
diff --git a/src/mainboard/emulation/qemu-i440fx/irq_tables.c b/src/mainboard/emulation/qemu-i440fx/irq_tables.c
index e288afd8c4..7d6f83d22c 100644
--- a/src/mainboard/emulation/qemu-i440fx/irq_tables.c
+++ b/src/mainboard/emulation/qemu-i440fx/irq_tables.c
@@ -1,13 +1,14 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
 #include <arch/pirq_routing.h>
+#include <device/pci_def.h>
 
 static const struct irq_routing_table intel_irq_routing_table = {
 	PIRQ_SIGNATURE,  /* u32 signature */
 	PIRQ_VERSION,    /* u16 version   */
 	32+16*CONFIG_IRQ_SLOT_COUNT,	 /* there can be total CONFIG_IRQ_SLOT_COUNT devices on the bus */
 	0x00,		 /* Where the interrupt router lies (bus) */
-	(0x01 << 3)|0x0,   /* Where the interrupt router lies (dev) */
+	PCI_DEVFN(0x01, 0),   /* Where the interrupt router lies (dev) */
 	0,		 /* IRQs devoted exclusively to PCI usage */
 	0x8086,		 /* Vendor */
 	0x7000,		 /* Device */
@@ -16,13 +17,13 @@ static const struct irq_routing_table intel_irq_routing_table = {
 	0x7,         /*  u8 checksum , this hase to set to some value that would give 0 after the sum of all bytes for this structure (including checksum) */
 	/* clang-format off */
 	{
-		/* bus,       dev|fn,   {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap},  slot, rfu */
-		{0x00,(0x01 << 3)|0x0, {{0x60, 0xdef8}, {0x61, 0xdef8}, {0x62, 0xdef8}, {0x63, 0x0def8}}, 0x0, 0x0},
-		{0x00,(0x02 << 3)|0x0, {{0x61, 0xdef8}, {0x62, 0xdef8}, {0x63, 0xdef8}, {0x60, 0x0def8}}, 0x1, 0x0},
-		{0x00,(0x03 << 3)|0x0, {{0x62, 0xdef8}, {0x63, 0xdef8}, {0x60, 0xdef8}, {0x61, 0x0def8}}, 0x2, 0x0},
-		{0x00,(0x04 << 3)|0x0, {{0x63, 0xdef8}, {0x60, 0xdef8}, {0x61, 0xdef8}, {0x62, 0x0def8}}, 0x3, 0x0},
-		{0x00,(0x05 << 3)|0x0, {{0x60, 0xdef8}, {0x61, 0xdef8}, {0x62, 0xdef8}, {0x63, 0x0def8}}, 0x4, 0x0},
-		{0x00,(0x06 << 3)|0x0, {{0x61, 0xdef8}, {0x62, 0xdef8}, {0x63, 0xdef8}, {0x60, 0x0def8}}, 0x5, 0x0},
+	       /* bus,PCI_DEVFN(dev, fn),  {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap},  slot, rfu */
+		{0x00,PCI_DEVFN(0x01, 0), {{0x60, 0xdef8}, {0x61, 0xdef8}, {0x62, 0xdef8}, {0x63, 0x0def8}}, 0x0, 0x0},
+		{0x00,PCI_DEVFN(0x02, 0), {{0x61, 0xdef8}, {0x62, 0xdef8}, {0x63, 0xdef8}, {0x60, 0x0def8}}, 0x1, 0x0},
+		{0x00,PCI_DEVFN(0x03, 0), {{0x62, 0xdef8}, {0x63, 0xdef8}, {0x60, 0xdef8}, {0x61, 0x0def8}}, 0x2, 0x0},
+		{0x00,PCI_DEVFN(0x04, 0), {{0x63, 0xdef8}, {0x60, 0xdef8}, {0x61, 0xdef8}, {0x62, 0x0def8}}, 0x3, 0x0},
+		{0x00,PCI_DEVFN(0x05, 0), {{0x60, 0xdef8}, {0x61, 0xdef8}, {0x62, 0xdef8}, {0x63, 0x0def8}}, 0x4, 0x0},
+		{0x00,PCI_DEVFN(0x06, 0), {{0x61, 0xdef8}, {0x62, 0xdef8}, {0x63, 0xdef8}, {0x60, 0x0def8}}, 0x5, 0x0},
 	}
 	/* clang-format on */
 };
diff --git a/src/mainboard/getac/p470/irq_tables.c b/src/mainboard/getac/p470/irq_tables.c
index 1d5c97e654..e0c807378d 100644
--- a/src/mainboard/getac/p470/irq_tables.c
+++ b/src/mainboard/getac/p470/irq_tables.c
@@ -1,13 +1,14 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
 #include <arch/pirq_routing.h>
+#include <device/pci_def.h>
 
 static const struct irq_routing_table intel_irq_routing_table = {
 	PIRQ_SIGNATURE,  /* u32 signature */
 	PIRQ_VERSION,    /* u16 version   */
 	32+16*CONFIG_IRQ_SLOT_COUNT,	 /* There can be total 18 devices on the bus */
 	0x00,		 /* Where the interrupt router lies (bus) */
-	(0x1f << 3)|0x0,   /* Where the interrupt router lies (dev) */
+	PCI_DEVFN(0x1f, 0),   /* Where the interrupt router lies (dev) */
 	0,		 /* IRQs devoted exclusively to PCI usage */
 	0x8086,		 /* Vendor */
 	0x27b0,		 /* Device */
@@ -16,25 +17,25 @@ static const struct irq_routing_table intel_irq_routing_table = {
 	0xf,		 /* u8 checksum. */
 	/* clang-format off */
 	{
-		/* bus,       dev|fn,   {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap},  slot, rfu */
-		{0x00,(0x01 << 3)|0x0, {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0x0dcd8}}, 0x0, 0x0}, // PCIe?
-		{0x00,(0x02 << 3)|0x0, {{0x60, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // VGA
-		{0x00,(0x1e << 3)|0x0, {{0x61, 0xdcf8}, {0x68, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // PCI bridge
-		{0x00,(0x1f << 3)|0x0, {{0x62, 0xdcf8}, {0x63, 0xdcd8}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // LPC
-		{0x00,(0x1d << 3)|0x0, {{0x6b, 0xdcf8}, {0x63, 0xdcd8}, {0x62, 0xdcf8}, {0x60, 0x0dcf8}}, 0x0, 0x0}, // USB#1
-		{0x00,(0x1b << 3)|0x0, {{0x60, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // Audio device
-		{0x00,(0x1c << 3)|0x0, {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0x0dcd8}}, 0x2, 0x0}, // PCIe bridge
-		{0x04,(0x00 << 3)|0x0, {{0x60, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // Firewire
-		{0x04,(0x01 << 3)|0x0, {{0x68, 0xdcf8}, {0x69, 0xdcf8}, {0x6a, 0xdcf8}, {0x6b, 0x0dcf8}}, 0x1, 0x0}, // PCI Bridge
-		{0x04,(0x02 << 3)|0x0, {{0x69, 0xdcf8}, {0x6a, 0xdcf8}, {0x6b, 0xdcf8}, {0x68, 0x0dcf8}}, 0x2, 0x0},
-		{0x04,(0x03 << 3)|0x0, {{0x6a, 0xdcf8}, {0x6b, 0xdcf8}, {0x68, 0xdcf8}, {0x69, 0x0dcf8}}, 0x3, 0x0},
-		{0x04,(0x04 << 3)|0x0, {{0x6b, 0xdcf8}, {0x68, 0xdcf8}, {0x69, 0xdcf8}, {0x6a, 0x0dcf8}}, 0x4, 0x0},
-		{0x04,(0x05 << 3)|0x0, {{0x63, 0xdcd8}, {0x62, 0xdcf8}, {0x61, 0xdcf8}, {0x60, 0x0dcf8}}, 0x5, 0x0},
-		{0x04,(0x06 << 3)|0x0, {{0x62, 0xdcf8}, {0x61, 0xdcf8}, {0x60, 0xdcf8}, {0x63, 0x0dcd8}}, 0x6, 0x0},
-		{0x04,(0x09 << 3)|0x0, {{0x69, 0xdcf8}, {0x6a, 0xdcf8}, {0x6b, 0xdcf8}, {0x68, 0x0dcf8}}, 0x9, 0x0},
-		{0x01,(0x00 << 3)|0x0, {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0x0dcd8}}, 0x0, 0x0}, // Ethernet 8168
-		{0x02,(0x00 << 3)|0x0, {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0x0dcd8}}, 0x9, 0x0},
-		{0x03,(0x00 << 3)|0x0, {{0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0xdcd8}, {0x60, 0x0dcf8}}, 0xa, 0x0},
+	       /* bus,PCI_DEVFN(dev, fn),  {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap},  slot, rfu */
+		{0x00,PCI_DEVFN(0x01, 0), {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0x0dcd8}}, 0x0, 0x0}, // PCIe?
+		{0x00,PCI_DEVFN(0x02, 0), {{0x60, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // VGA
+		{0x00,PCI_DEVFN(0x1e, 0), {{0x61, 0xdcf8}, {0x68, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // PCI bridge
+		{0x00,PCI_DEVFN(0x1f, 0), {{0x62, 0xdcf8}, {0x63, 0xdcd8}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // LPC
+		{0x00,PCI_DEVFN(0x1d, 0), {{0x6b, 0xdcf8}, {0x63, 0xdcd8}, {0x62, 0xdcf8}, {0x60, 0x0dcf8}}, 0x0, 0x0}, // USB#1
+		{0x00,PCI_DEVFN(0x1b, 0), {{0x60, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // Audio device
+		{0x00,PCI_DEVFN(0x1c, 0), {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0x0dcd8}}, 0x2, 0x0}, // PCIe bridge
+		{0x04,PCI_DEVFN(0x00, 0), {{0x60, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // Firewire
+		{0x04,PCI_DEVFN(0x01, 0), {{0x68, 0xdcf8}, {0x69, 0xdcf8}, {0x6a, 0xdcf8}, {0x6b, 0x0dcf8}}, 0x1, 0x0}, // PCI Bridge
+		{0x04,PCI_DEVFN(0x02, 0), {{0x69, 0xdcf8}, {0x6a, 0xdcf8}, {0x6b, 0xdcf8}, {0x68, 0x0dcf8}}, 0x2, 0x0},
+		{0x04,PCI_DEVFN(0x03, 0), {{0x6a, 0xdcf8}, {0x6b, 0xdcf8}, {0x68, 0xdcf8}, {0x69, 0x0dcf8}}, 0x3, 0x0},
+		{0x04,PCI_DEVFN(0x04, 0), {{0x6b, 0xdcf8}, {0x68, 0xdcf8}, {0x69, 0xdcf8}, {0x6a, 0x0dcf8}}, 0x4, 0x0},
+		{0x04,PCI_DEVFN(0x05, 0), {{0x63, 0xdcd8}, {0x62, 0xdcf8}, {0x61, 0xdcf8}, {0x60, 0x0dcf8}}, 0x5, 0x0},
+		{0x04,PCI_DEVFN(0x06, 0), {{0x62, 0xdcf8}, {0x61, 0xdcf8}, {0x60, 0xdcf8}, {0x63, 0x0dcd8}}, 0x6, 0x0},
+		{0x04,PCI_DEVFN(0x09, 0), {{0x69, 0xdcf8}, {0x6a, 0xdcf8}, {0x6b, 0xdcf8}, {0x68, 0x0dcf8}}, 0x9, 0x0},
+		{0x01,PCI_DEVFN(0x00, 0), {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0x0dcd8}}, 0x0, 0x0}, // Ethernet 8168
+		{0x02,PCI_DEVFN(0x00, 0), {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0x0dcd8}}, 0x9, 0x0},
+		{0x03,PCI_DEVFN(0x00, 0), {{0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0xdcd8}, {0x60, 0x0dcf8}}, 0xa, 0x0},
 	}
 	/* clang-format on */
 };
diff --git a/src/mainboard/ibase/mb899/irq_tables.c b/src/mainboard/ibase/mb899/irq_tables.c
index 7974422b6c..e40eec2fd8 100644
--- a/src/mainboard/ibase/mb899/irq_tables.c
+++ b/src/mainboard/ibase/mb899/irq_tables.c
@@ -1,13 +1,14 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
 #include <arch/pirq_routing.h>
+#include <device/pci_def.h>
 
 static const struct irq_routing_table intel_irq_routing_table = {
 	PIRQ_SIGNATURE,  /* u32 signature */
 	PIRQ_VERSION,    /* u16 version   */
 	32+16*CONFIG_IRQ_SLOT_COUNT,	 /* There can be total CONFIG_IRQ_SLOT_COUNT devices on the bus */
 	0x00,		 /* Where the interrupt router lies (bus) */
-	(0x1f << 3)|0x0,   /* Where the interrupt router lies (dev) */
+	PCI_DEVFN(0x1f, 0),   /* Where the interrupt router lies (dev) */
 	0,		 /* IRQs devoted exclusively to PCI usage */
 	0x8086,		 /* Vendor */
 	0x27b9,		 /* Device */
@@ -16,25 +17,25 @@ static const struct irq_routing_table intel_irq_routing_table = {
 	0xf,		 /* u8 checksum. */
 	/* clang-format off */
 	{
-		/* bus,       dev|fn,   {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap},  slot, rfu */
-		{0x00,(0x01 << 3)|0x0, {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0x0dcd8}}, 0x0, 0x0}, // PCIe?
-		{0x00,(0x02 << 3)|0x0, {{0x60, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // VGA
-		{0x00,(0x1e << 3)|0x0, {{0x61, 0xdcf8}, {0x68, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // PCI bridge
-		{0x00,(0x1f << 3)|0x0, {{0x62, 0xdcf8}, {0x63, 0xdcd8}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // LPC
-		{0x00,(0x1d << 3)|0x0, {{0x6b, 0xdcf8}, {0x63, 0xdcd8}, {0x62, 0xdcf8}, {0x60, 0x0dcf8}}, 0x0, 0x0}, // USB#1
-		{0x00,(0x1b << 3)|0x0, {{0x60, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // Audio device
-		{0x00,(0x1c << 3)|0x0, {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0x0dcd8}}, 0x2, 0x0}, // PCIe bridge
-		{0x04,(0x00 << 3)|0x0, {{0x60, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // Firewire
-		{0x04,(0x01 << 3)|0x0, {{0x68, 0xdcf8}, {0x69, 0xdcf8}, {0x6a, 0xdcf8}, {0x6b, 0x0dcf8}}, 0x1, 0x0}, // PCI Bridge
-		{0x04,(0x02 << 3)|0x0, {{0x69, 0xdcf8}, {0x6a, 0xdcf8}, {0x6b, 0xdcf8}, {0x68, 0x0dcf8}}, 0x2, 0x0},
-		{0x04,(0x03 << 3)|0x0, {{0x6a, 0xdcf8}, {0x6b, 0xdcf8}, {0x68, 0xdcf8}, {0x69, 0x0dcf8}}, 0x3, 0x0},
-		{0x04,(0x04 << 3)|0x0, {{0x6b, 0xdcf8}, {0x68, 0xdcf8}, {0x69, 0xdcf8}, {0x6a, 0x0dcf8}}, 0x4, 0x0},
-		{0x04,(0x05 << 3)|0x0, {{0x63, 0xdcd8}, {0x62, 0xdcf8}, {0x61, 0xdcf8}, {0x60, 0x0dcf8}}, 0x5, 0x0},
-		{0x04,(0x06 << 3)|0x0, {{0x62, 0xdcf8}, {0x61, 0xdcf8}, {0x60, 0xdcf8}, {0x63, 0x0dcd8}}, 0x6, 0x0},
-		{0x04,(0x09 << 3)|0x0, {{0x69, 0xdcf8}, {0x6a, 0xdcf8}, {0x6b, 0xdcf8}, {0x68, 0x0dcf8}}, 0x9, 0x0},
-		{0x01,(0x00 << 3)|0x0, {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0x0dcd8}}, 0x0, 0x0}, // Ethernet Marvell 88E8053
-		{0x02,(0x00 << 3)|0x0, {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0x0dcd8}}, 0x9, 0x0},
-		{0x03,(0x00 << 3)|0x0, {{0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0xdcd8}, {0x60, 0x0dcf8}}, 0xa, 0x0},
+	       /* bus,PCI_DEVFN(dev, fn),  {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap},  slot, rfu */
+		{0x00,PCI_DEVFN(0x01, 0), {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0x0dcd8}}, 0x0, 0x0}, // PCIe?
+		{0x00,PCI_DEVFN(0x02, 0), {{0x60, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // VGA
+		{0x00,PCI_DEVFN(0x1e, 0), {{0x61, 0xdcf8}, {0x68, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // PCI bridge
+		{0x00,PCI_DEVFN(0x1f, 0), {{0x62, 0xdcf8}, {0x63, 0xdcd8}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // LPC
+		{0x00,PCI_DEVFN(0x1d, 0), {{0x6b, 0xdcf8}, {0x63, 0xdcd8}, {0x62, 0xdcf8}, {0x60, 0x0dcf8}}, 0x0, 0x0}, // USB#1
+		{0x00,PCI_DEVFN(0x1b, 0), {{0x60, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // Audio device
+		{0x00,PCI_DEVFN(0x1c, 0), {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0x0dcd8}}, 0x2, 0x0}, // PCIe bridge
+		{0x04,PCI_DEVFN(0x00, 0), {{0x60, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // Firewire
+		{0x04,PCI_DEVFN(0x01, 0), {{0x68, 0xdcf8}, {0x69, 0xdcf8}, {0x6a, 0xdcf8}, {0x6b, 0x0dcf8}}, 0x1, 0x0}, // PCI Bridge
+		{0x04,PCI_DEVFN(0x02, 0), {{0x69, 0xdcf8}, {0x6a, 0xdcf8}, {0x6b, 0xdcf8}, {0x68, 0x0dcf8}}, 0x2, 0x0},
+		{0x04,PCI_DEVFN(0x03, 0), {{0x6a, 0xdcf8}, {0x6b, 0xdcf8}, {0x68, 0xdcf8}, {0x69, 0x0dcf8}}, 0x3, 0x0},
+		{0x04,PCI_DEVFN(0x04, 0), {{0x6b, 0xdcf8}, {0x68, 0xdcf8}, {0x69, 0xdcf8}, {0x6a, 0x0dcf8}}, 0x4, 0x0},
+		{0x04,PCI_DEVFN(0x05, 0), {{0x63, 0xdcd8}, {0x62, 0xdcf8}, {0x61, 0xdcf8}, {0x60, 0x0dcf8}}, 0x5, 0x0},
+		{0x04,PCI_DEVFN(0x06, 0), {{0x62, 0xdcf8}, {0x61, 0xdcf8}, {0x60, 0xdcf8}, {0x63, 0x0dcd8}}, 0x6, 0x0},
+		{0x04,PCI_DEVFN(0x09, 0), {{0x69, 0xdcf8}, {0x6a, 0xdcf8}, {0x6b, 0xdcf8}, {0x68, 0x0dcf8}}, 0x9, 0x0},
+		{0x01,PCI_DEVFN(0x00, 0), {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0x0dcd8}}, 0x0, 0x0}, // Ethernet Marvell 88E8053
+		{0x02,PCI_DEVFN(0x00, 0), {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0x0dcd8}}, 0x9, 0x0},
+		{0x03,PCI_DEVFN(0x00, 0), {{0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0xdcd8}, {0x60, 0x0dcf8}}, 0xa, 0x0},
 	}
 	/* clang-format on */
 };
diff --git a/src/mainboard/intel/d945gclf/irq_tables.c b/src/mainboard/intel/d945gclf/irq_tables.c
index 4e1f6b9f18..44cf175f55 100644
--- a/src/mainboard/intel/d945gclf/irq_tables.c
+++ b/src/mainboard/intel/d945gclf/irq_tables.c
@@ -1,13 +1,14 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
 #include <arch/pirq_routing.h>
+#include <device/pci_def.h>
 
 static const struct irq_routing_table intel_irq_routing_table = {
 	PIRQ_SIGNATURE,  /* u32 signature */
 	PIRQ_VERSION,    /* u16 version   */
 	32+16*18,	 /* There can be total 18 devices on the bus */
 	0x00,		 /* Where the interrupt router lies (bus) */
-	(0x1f << 3)|0x0,   /* Where the interrupt router lies (dev) */
+	PCI_DEVFN(0x1f, 0),   /* Where the interrupt router lies (dev) */
 	0,		 /* IRQs devoted exclusively to PCI usage */
 	0x8086,		 /* Vendor */
 	0x27b0,		 /* Device */
@@ -16,25 +17,25 @@ static const struct irq_routing_table intel_irq_routing_table = {
 	0xf,		 /* u8 checksum. */
 	/* clang-format off */
 	{
-		/* bus,       dev|fn,   {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap},  slot, rfu */
-		{0x00,(0x01 << 3)|0x0, {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0x0dcd8}}, 0x0, 0x0}, // PCIe?
-		{0x00,(0x02 << 3)|0x0, {{0x60, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // VGA
-		{0x00,(0x1e << 3)|0x0, {{0x61, 0xdcf8}, {0x68, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // PCI bridge
-		{0x00,(0x1f << 3)|0x0, {{0x62, 0xdcf8}, {0x63, 0xdcd8}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // LPC
-		{0x00,(0x1d << 3)|0x0, {{0x6b, 0xdcf8}, {0x63, 0xdcd8}, {0x62, 0xdcf8}, {0x60, 0x0dcf8}}, 0x0, 0x0}, // USB#1
-		{0x00,(0x1b << 3)|0x0, {{0x60, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // Audio device
-		{0x00,(0x1c << 3)|0x0, {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0x0dcd8}}, 0x2, 0x0}, // PCIe bridge
-		{0x04,(0x00 << 3)|0x0, {{0x60, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // Firewire
-		{0x04,(0x01 << 3)|0x0, {{0x68, 0xdcf8}, {0x69, 0xdcf8}, {0x6a, 0xdcf8}, {0x6b, 0x0dcf8}}, 0x1, 0x0}, // PCI Bridge
-		{0x04,(0x02 << 3)|0x0, {{0x69, 0xdcf8}, {0x6a, 0xdcf8}, {0x6b, 0xdcf8}, {0x68, 0x0dcf8}}, 0x2, 0x0},
-		{0x04,(0x03 << 3)|0x0, {{0x6a, 0xdcf8}, {0x6b, 0xdcf8}, {0x68, 0xdcf8}, {0x69, 0x0dcf8}}, 0x3, 0x0},
-		{0x04,(0x04 << 3)|0x0, {{0x6b, 0xdcf8}, {0x68, 0xdcf8}, {0x69, 0xdcf8}, {0x6a, 0x0dcf8}}, 0x4, 0x0},
-		{0x04,(0x05 << 3)|0x0, {{0x63, 0xdcd8}, {0x62, 0xdcf8}, {0x61, 0xdcf8}, {0x60, 0x0dcf8}}, 0x5, 0x0},
-		{0x04,(0x06 << 3)|0x0, {{0x62, 0xdcf8}, {0x61, 0xdcf8}, {0x60, 0xdcf8}, {0x63, 0x0dcd8}}, 0x6, 0x0},
-		{0x04,(0x09 << 3)|0x0, {{0x69, 0xdcf8}, {0x6a, 0xdcf8}, {0x6b, 0xdcf8}, {0x68, 0x0dcf8}}, 0x9, 0x0},
-		{0x01,(0x00 << 3)|0x0, {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0x0dcd8}}, 0x0, 0x0}, // Ethernet 8168
-		{0x02,(0x00 << 3)|0x0, {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0x0dcd8}}, 0x9, 0x0},
-		{0x03,(0x00 << 3)|0x0, {{0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0xdcd8}, {0x60, 0x0dcf8}}, 0xa, 0x0},
+	       /* bus,PCI_DEVFN(dev, fn),  {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap},  slot, rfu */
+		{0x00,PCI_DEVFN(0x01, 0), {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0x0dcd8}}, 0x0, 0x0}, // PCIe?
+		{0x00,PCI_DEVFN(0x02, 0), {{0x60, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // VGA
+		{0x00,PCI_DEVFN(0x1e, 0), {{0x61, 0xdcf8}, {0x68, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // PCI bridge
+		{0x00,PCI_DEVFN(0x1f, 0), {{0x62, 0xdcf8}, {0x63, 0xdcd8}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // LPC
+		{0x00,PCI_DEVFN(0x1d, 0), {{0x6b, 0xdcf8}, {0x63, 0xdcd8}, {0x62, 0xdcf8}, {0x60, 0x0dcf8}}, 0x0, 0x0}, // USB#1
+		{0x00,PCI_DEVFN(0x1b, 0), {{0x60, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // Audio device
+		{0x00,PCI_DEVFN(0x1c, 0), {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0x0dcd8}}, 0x2, 0x0}, // PCIe bridge
+		{0x04,PCI_DEVFN(0x00, 0), {{0x60, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // Firewire
+		{0x04,PCI_DEVFN(0x01, 0), {{0x68, 0xdcf8}, {0x69, 0xdcf8}, {0x6a, 0xdcf8}, {0x6b, 0x0dcf8}}, 0x1, 0x0}, // PCI Bridge
+		{0x04,PCI_DEVFN(0x02, 0), {{0x69, 0xdcf8}, {0x6a, 0xdcf8}, {0x6b, 0xdcf8}, {0x68, 0x0dcf8}}, 0x2, 0x0},
+		{0x04,PCI_DEVFN(0x03, 0), {{0x6a, 0xdcf8}, {0x6b, 0xdcf8}, {0x68, 0xdcf8}, {0x69, 0x0dcf8}}, 0x3, 0x0},
+		{0x04,PCI_DEVFN(0x04, 0), {{0x6b, 0xdcf8}, {0x68, 0xdcf8}, {0x69, 0xdcf8}, {0x6a, 0x0dcf8}}, 0x4, 0x0},
+		{0x04,PCI_DEVFN(0x05, 0), {{0x63, 0xdcd8}, {0x62, 0xdcf8}, {0x61, 0xdcf8}, {0x60, 0x0dcf8}}, 0x5, 0x0},
+		{0x04,PCI_DEVFN(0x06, 0), {{0x62, 0xdcf8}, {0x61, 0xdcf8}, {0x60, 0xdcf8}, {0x63, 0x0dcd8}}, 0x6, 0x0},
+		{0x04,PCI_DEVFN(0x09, 0), {{0x69, 0xdcf8}, {0x6a, 0xdcf8}, {0x6b, 0xdcf8}, {0x68, 0x0dcf8}}, 0x9, 0x0},
+		{0x01,PCI_DEVFN(0x00, 0), {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0x0dcd8}}, 0x0, 0x0}, // Ethernet 8168
+		{0x02,PCI_DEVFN(0x00, 0), {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0x0dcd8}}, 0x9, 0x0},
+		{0x03,PCI_DEVFN(0x00, 0), {{0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0xdcd8}, {0x60, 0x0dcf8}}, 0xa, 0x0},
 	}
 	/* clang-format on */
 };
diff --git a/src/mainboard/kontron/986lcd-m/irq_tables.c b/src/mainboard/kontron/986lcd-m/irq_tables.c
index 2545aa8bfa..65db97c23e 100644
--- a/src/mainboard/kontron/986lcd-m/irq_tables.c
+++ b/src/mainboard/kontron/986lcd-m/irq_tables.c
@@ -1,13 +1,14 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
 #include <arch/pirq_routing.h>
+#include <device/pci_def.h>
 
 static const struct irq_routing_table intel_irq_routing_table = {
 	PIRQ_SIGNATURE,  /* u32 signature */
 	PIRQ_VERSION,    /* u16 version   */
 	32+16*CONFIG_IRQ_SLOT_COUNT,	 /* There can be total CONFIG_IRQ_SLOT_COUNT devices on the bus */
 	0x00,		 /* Where the interrupt router lies (bus) */
-	(0x1f << 3)|0x0,   /* Where the interrupt router lies (dev) */
+	PCI_DEVFN(0x1f, 0),   /* Where the interrupt router lies (dev) */
 	0,		 /* IRQs devoted exclusively to PCI usage */
 	0x8086,		 /* Vendor */
 	0x27b0,		 /* Device */
@@ -16,25 +17,25 @@ static const struct irq_routing_table intel_irq_routing_table = {
 	0xf,		 /* u8 checksum. */
 	/* clang-format off */
 	{
-		/* bus,       dev|fn,   {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap},  slot, rfu */
-		{0x00,(0x01 << 3)|0x0, {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0x0dcd8}}, 0x0, 0x0}, /* PCIe? */
-		{0x00,(0x02 << 3)|0x0, {{0x60, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, /* VGA */
-		{0x00,(0x1e << 3)|0x0, {{0x61, 0xdcf8}, {0x68, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, /* PCI bridge */
-		{0x00,(0x1f << 3)|0x0, {{0x62, 0xdcf8}, {0x63, 0xdcd8}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, /* LPC */
-		{0x00,(0x1d << 3)|0x0, {{0x6b, 0xdcf8}, {0x63, 0xdcd8}, {0x62, 0xdcf8}, {0x60, 0x0dcf8}}, 0x0, 0x0}, /* USB#1 */
-		{0x00,(0x1b << 3)|0x0, {{0x60, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, /* Audio device */
-		{0x00,(0x1c << 3)|0x0, {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0x0dcd8}}, 0x2, 0x0}, /* PCIe bridge */
-		{0x04,(0x00 << 3)|0x0, {{0x60, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, /* Firewire */
-		{0x04,(0x01 << 3)|0x0, {{0x68, 0xdcf8}, {0x69, 0xdcf8}, {0x6a, 0xdcf8}, {0x6b, 0x0dcf8}}, 0x1, 0x0}, /* PCI Bridge */
-		{0x04,(0x02 << 3)|0x0, {{0x69, 0xdcf8}, {0x6a, 0xdcf8}, {0x6b, 0xdcf8}, {0x68, 0x0dcf8}}, 0x2, 0x0},
-		{0x04,(0x03 << 3)|0x0, {{0x6a, 0xdcf8}, {0x6b, 0xdcf8}, {0x68, 0xdcf8}, {0x69, 0x0dcf8}}, 0x3, 0x0},
-		{0x04,(0x04 << 3)|0x0, {{0x6b, 0xdcf8}, {0x68, 0xdcf8}, {0x69, 0xdcf8}, {0x6a, 0x0dcf8}}, 0x4, 0x0},
-		{0x04,(0x05 << 3)|0x0, {{0x63, 0xdcd8}, {0x62, 0xdcf8}, {0x61, 0xdcf8}, {0x60, 0x0dcf8}}, 0x5, 0x0},
-		{0x04,(0x06 << 3)|0x0, {{0x62, 0xdcf8}, {0x61, 0xdcf8}, {0x60, 0xdcf8}, {0x63, 0x0dcd8}}, 0x6, 0x0},
-		{0x04,(0x09 << 3)|0x0, {{0x69, 0xdcf8}, {0x6a, 0xdcf8}, {0x6b, 0xdcf8}, {0x68, 0x0dcf8}}, 0x9, 0x0},
-		{0x01,(0x00 << 3)|0x0, {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0x0dcd8}}, 0x0, 0x0}, /* Ethernet 8168 */
-		{0x02,(0x00 << 3)|0x0, {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0x0dcd8}}, 0x9, 0x0},
-		{0x03,(0x00 << 3)|0x0, {{0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0xdcd8}, {0x60, 0x0dcf8}}, 0xa, 0x0},
+	       /* bus,PCI_DEVFN(dev, fn),  {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap},  slot, rfu */
+		{0x00,PCI_DEVFN(0x01, 0), {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0x0dcd8}}, 0x0, 0x0}, /* PCIe? */
+		{0x00,PCI_DEVFN(0x02, 0), {{0x60, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, /* VGA */
+		{0x00,PCI_DEVFN(0x1e, 0), {{0x61, 0xdcf8}, {0x68, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, /* PCI bridge */
+		{0x00,PCI_DEVFN(0x1f, 0), {{0x62, 0xdcf8}, {0x63, 0xdcd8}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, /* LPC */
+		{0x00,PCI_DEVFN(0x1d, 0), {{0x6b, 0xdcf8}, {0x63, 0xdcd8}, {0x62, 0xdcf8}, {0x60, 0x0dcf8}}, 0x0, 0x0}, /* USB#1 */
+		{0x00,PCI_DEVFN(0x1b, 0), {{0x60, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, /* Audio device */
+		{0x00,PCI_DEVFN(0x1c, 0), {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0x0dcd8}}, 0x2, 0x0}, /* PCIe bridge */
+		{0x04,PCI_DEVFN(0x00, 0), {{0x60, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, /* Firewire */
+		{0x04,PCI_DEVFN(0x01, 0), {{0x68, 0xdcf8}, {0x69, 0xdcf8}, {0x6a, 0xdcf8}, {0x6b, 0x0dcf8}}, 0x1, 0x0}, /* PCI Bridge */
+		{0x04,PCI_DEVFN(0x02, 0), {{0x69, 0xdcf8}, {0x6a, 0xdcf8}, {0x6b, 0xdcf8}, {0x68, 0x0dcf8}}, 0x2, 0x0},
+		{0x04,PCI_DEVFN(0x03, 0), {{0x6a, 0xdcf8}, {0x6b, 0xdcf8}, {0x68, 0xdcf8}, {0x69, 0x0dcf8}}, 0x3, 0x0},
+		{0x04,PCI_DEVFN(0x04, 0), {{0x6b, 0xdcf8}, {0x68, 0xdcf8}, {0x69, 0xdcf8}, {0x6a, 0x0dcf8}}, 0x4, 0x0},
+		{0x04,PCI_DEVFN(0x05, 0), {{0x63, 0xdcd8}, {0x62, 0xdcf8}, {0x61, 0xdcf8}, {0x60, 0x0dcf8}}, 0x5, 0x0},
+		{0x04,PCI_DEVFN(0x06, 0), {{0x62, 0xdcf8}, {0x61, 0xdcf8}, {0x60, 0xdcf8}, {0x63, 0x0dcd8}}, 0x6, 0x0},
+		{0x04,PCI_DEVFN(0x09, 0), {{0x69, 0xdcf8}, {0x6a, 0xdcf8}, {0x6b, 0xdcf8}, {0x68, 0x0dcf8}}, 0x9, 0x0},
+		{0x01,PCI_DEVFN(0x00, 0), {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0x0dcd8}}, 0x0, 0x0}, /* Ethernet 8168 */
+		{0x02,PCI_DEVFN(0x00, 0), {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0x0dcd8}}, 0x9, 0x0},
+		{0x03,PCI_DEVFN(0x00, 0), {{0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0xdcd8}, {0x60, 0x0dcf8}}, 0xa, 0x0},
 	}
 	/* clang-format on */
 };
diff --git a/src/mainboard/lenovo/x60/irq_tables.c b/src/mainboard/lenovo/x60/irq_tables.c
index b39a440fdd..adfb84d55b 100644
--- a/src/mainboard/lenovo/x60/irq_tables.c
+++ b/src/mainboard/lenovo/x60/irq_tables.c
@@ -1,13 +1,14 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
 #include <arch/pirq_routing.h>
+#include <device/pci_def.h>
 
 static const struct irq_routing_table intel_irq_routing_table = {
 	PIRQ_SIGNATURE,		/* u32 signature */
 	PIRQ_VERSION,		/* u16 version */
 	32 + 16 * 15,		/* Max. number of devices on the bus */
 	0x00,			/* Interrupt router bus */
-	(0x1f << 3) | 0x0,	/* Interrupt router dev */
+	PCI_DEVFN(0x1f, 0),	/* Interrupt router dev */
 	0,			/* IRQs devoted exclusively to PCI usage */
 	0x8086,			/* Vendor */
 	0x122e,			/* Device */
@@ -19,21 +20,21 @@ static const struct irq_routing_table intel_irq_routing_table = {
 				 */
 	/* clang-format off */
 	{
-		/* bus,        dev | fn,   {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */
-		{0x00, (0x02 << 3) | 0x0, {{0x00, 0xdef8}, {0x61, 0x1cf8}, {0x00, 0xdef8}, {0x00, 0xdef8}}, 0x0, 0x0}, /* VGA       0:02.0 */
-		{0x00, (0x1b << 3) | 0x0, {{0x00, 0xdef8}, {0x61, 0x1cf8}, {0x00, 0xdef8}, {0x00, 0xdef8}}, 0x0, 0x0}, /* HD Audio  0:1b.0 */
-		{0x00, (0x1c << 3) | 0x0, {{0x68, 0x1cf8}, {0x69, 0x1cf8}, {0x6a, 0x1cf8}, {0x6b, 0x1cf8}}, 0x0, 0x0}, /* PCIe      0:1c.0 */
-		{0x00, (0x1c << 3) | 0x1, {{0x68, 0x1cf8}, {0x69, 0x1cf8}, {0x6a, 0x1cf8}, {0x6b, 0x1cf8}}, 0x0, 0x0}, /* PCIe      0:1c.1 */
-		{0x00, (0x1c << 3) | 0x2, {{0x68, 0x1cf8}, {0x69, 0x1cf8}, {0x6a, 0x1cf8}, {0x6b, 0x1cf8}}, 0x0, 0x0}, /* PCIe      0:1c.2 */
-		{0x00, (0x1c << 3) | 0x3, {{0x68, 0x1cf8}, {0x69, 0x1cf8}, {0x6a, 0x1cf8}, {0x6b, 0x1cf8}}, 0x0, 0x0}, /* PCIe      0:1c.3 */
-		{0x00, (0x1d << 3) | 0x0, {{0x60, 0x1cf8}, {0x61, 0x1cf8}, {0x62, 0x1cf8}, {0x63, 0x1cf8}}, 0x0, 0x0}, /* USB       0:1d.0 */
-		{0x00, (0x1d << 3) | 0x1, {{0x60, 0x1cf8}, {0x61, 0x1cf8}, {0x62, 0x1cf8}, {0x63, 0x1cf8}}, 0x0, 0x0}, /* USB       0:1d.1 */
-		{0x00, (0x1d << 3) | 0x2, {{0x60, 0x1cf8}, {0x61, 0x1cf8}, {0x62, 0x1cf8}, {0x63, 0x1cf8}}, 0x0, 0x0}, /* USB       0:1d.2 */
-		{0x00, (0x1d << 3) | 0x3, {{0x60, 0x1cf8}, {0x61, 0x1cf8}, {0x62, 0x1cf8}, {0x63, 0x1cf8}}, 0x0, 0x0}, /* USB       0:1d.3 */
-		{0x00, (0x1e << 3) | 0x0, {{0x60, 0x1cf8}, {0x61, 0x1cf8}, {0x62, 0x1cf8}, {0x63, 0x1cf8}}, 0x0, 0x0}, /* PCI       0:1e.0 */
-		{0x00, (0x1f << 3) | 0x0, {{0x6b, 0x1cf8}, {0x60, 0x1cf8}, {0x60, 0x1cf8}, {0x00, 0xdef8}}, 0x0, 0x0}, /* LPC       0:1f.0 */
-		{0x00, (0x1f << 3) | 0x1, {{0x6b, 0x1cf8}, {0x60, 0x1cf8}, {0x60, 0x1cf8}, {0x00, 0xdef8}}, 0x0, 0x0}, /* IDE       0:1f.1 */
-		{0x00, (0x1f << 3) | 0x2, {{0x6b, 0x1cf8}, {0x60, 0x1cf8}, {0x60, 0x1cf8}, {0x00, 0xdef8}}, 0x0, 0x0}, /* SATA      0:1f.2 */
+	       /* bus, PCI_DEVFN(dev, fn),  {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */
+		{0x00, PCI_DEVFN(0x02, 0), {{0x00, 0xdef8}, {0x61, 0x1cf8}, {0x00, 0xdef8}, {0x00, 0xdef8}}, 0x0, 0x0}, /* VGA       0:02.0 */
+		{0x00, PCI_DEVFN(0x1b, 0), {{0x00, 0xdef8}, {0x61, 0x1cf8}, {0x00, 0xdef8}, {0x00, 0xdef8}}, 0x0, 0x0}, /* HD Audio  0:1b.0 */
+		{0x00, PCI_DEVFN(0x1c, 0), {{0x68, 0x1cf8}, {0x69, 0x1cf8}, {0x6a, 0x1cf8}, {0x6b, 0x1cf8}}, 0x0, 0x0}, /* PCIe      0:1c.0 */
+		{0x00, PCI_DEVFN(0x1c, 1), {{0x68, 0x1cf8}, {0x69, 0x1cf8}, {0x6a, 0x1cf8}, {0x6b, 0x1cf8}}, 0x0, 0x0}, /* PCIe      0:1c.1 */
+		{0x00, PCI_DEVFN(0x1c, 2), {{0x68, 0x1cf8}, {0x69, 0x1cf8}, {0x6a, 0x1cf8}, {0x6b, 0x1cf8}}, 0x0, 0x0}, /* PCIe      0:1c.2 */
+		{0x00, PCI_DEVFN(0x1c, 3), {{0x68, 0x1cf8}, {0x69, 0x1cf8}, {0x6a, 0x1cf8}, {0x6b, 0x1cf8}}, 0x0, 0x0}, /* PCIe      0:1c.3 */
+		{0x00, PCI_DEVFN(0x1d, 0), {{0x60, 0x1cf8}, {0x61, 0x1cf8}, {0x62, 0x1cf8}, {0x63, 0x1cf8}}, 0x0, 0x0}, /* USB       0:1d.0 */
+		{0x00, PCI_DEVFN(0x1d, 1), {{0x60, 0x1cf8}, {0x61, 0x1cf8}, {0x62, 0x1cf8}, {0x63, 0x1cf8}}, 0x0, 0x0}, /* USB       0:1d.1 */
+		{0x00, PCI_DEVFN(0x1d, 2), {{0x60, 0x1cf8}, {0x61, 0x1cf8}, {0x62, 0x1cf8}, {0x63, 0x1cf8}}, 0x0, 0x0}, /* USB       0:1d.2 */
+		{0x00, PCI_DEVFN(0x1d, 3), {{0x60, 0x1cf8}, {0x61, 0x1cf8}, {0x62, 0x1cf8}, {0x63, 0x1cf8}}, 0x0, 0x0}, /* USB       0:1d.3 */
+		{0x00, PCI_DEVFN(0x1e, 0), {{0x60, 0x1cf8}, {0x61, 0x1cf8}, {0x62, 0x1cf8}, {0x63, 0x1cf8}}, 0x0, 0x0}, /* PCI       0:1e.0 */
+		{0x00, PCI_DEVFN(0x1f, 0), {{0x6b, 0x1cf8}, {0x60, 0x1cf8}, {0x60, 0x1cf8}, {0x00, 0xdef8}}, 0x0, 0x0}, /* LPC       0:1f.0 */
+		{0x00, PCI_DEVFN(0x1f, 1), {{0x6b, 0x1cf8}, {0x60, 0x1cf8}, {0x60, 0x1cf8}, {0x00, 0xdef8}}, 0x0, 0x0}, /* IDE       0:1f.1 */
+		{0x00, PCI_DEVFN(0x1f, 2), {{0x6b, 0x1cf8}, {0x60, 0x1cf8}, {0x60, 0x1cf8}, {0x00, 0xdef8}}, 0x0, 0x0}, /* SATA      0:1f.2 */
 	}
 	/* clang-format on */
 };
diff --git a/src/mainboard/roda/rk886ex/irq_tables.c b/src/mainboard/roda/rk886ex/irq_tables.c
index bacf5fe273..73b7412c0d 100644
--- a/src/mainboard/roda/rk886ex/irq_tables.c
+++ b/src/mainboard/roda/rk886ex/irq_tables.c
@@ -1,13 +1,14 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
 #include <arch/pirq_routing.h>
+#include <device/pci_def.h>
 
 static const struct irq_routing_table intel_irq_routing_table = {
 	PIRQ_SIGNATURE,  /* u32 signature */
 	PIRQ_VERSION,    /* u16 version   */
 	32+16*18,	 /* There can be total 18 devices on the bus */
 	0x00,		 /* Where the interrupt router lies (bus) */
-	(0x1f << 3)|0x0,   /* Where the interrupt router lies (dev) */
+	PCI_DEVFN(0x1f, 0),   /* Where the interrupt router lies (dev) */
 	0,		 /* IRQs devoted exclusively to PCI usage */
 	0x8086,		 /* Vendor */
 	0x27b0,		 /* Device */
@@ -16,25 +17,25 @@ static const struct irq_routing_table intel_irq_routing_table = {
 	0xf,		 /* u8 checksum. */
 	/* clang-format off */
 	{
-		/* bus,       dev|fn,   {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap},  slot, rfu */
-		{0x00,(0x01 << 3)|0x0, {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0x0dcd8}}, 0x0, 0x0}, /* PCIe? */
-		{0x00,(0x02 << 3)|0x0, {{0x60, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, /* VGA */
-		{0x00,(0x1e << 3)|0x0, {{0x61, 0xdcf8}, {0x68, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, /* PCI bridge */
-		{0x00,(0x1f << 3)|0x0, {{0x62, 0xdcf8}, {0x63, 0xdcd8}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, /* LPC */
-		{0x00,(0x1d << 3)|0x0, {{0x6b, 0xdcf8}, {0x63, 0xdcd8}, {0x62, 0xdcf8}, {0x60, 0x0dcf8}}, 0x0, 0x0}, /* USB#1 */
-		{0x00,(0x1b << 3)|0x0, {{0x60, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, /* Audio device */
-		{0x00,(0x1c << 3)|0x0, {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0x0dcd8}}, 0x2, 0x0}, /* PCIe bridge */
-		{0x04,(0x00 << 3)|0x0, {{0x60, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, /* Firewire */
-		{0x04,(0x01 << 3)|0x0, {{0x68, 0xdcf8}, {0x69, 0xdcf8}, {0x6a, 0xdcf8}, {0x6b, 0x0dcf8}}, 0x1, 0x0}, /* PCI Bridge */
-		{0x04,(0x02 << 3)|0x0, {{0x69, 0xdcf8}, {0x6a, 0xdcf8}, {0x6b, 0xdcf8}, {0x68, 0x0dcf8}}, 0x2, 0x0},
-		{0x04,(0x03 << 3)|0x0, {{0x6a, 0xdcf8}, {0x6b, 0xdcf8}, {0x68, 0xdcf8}, {0x69, 0x0dcf8}}, 0x3, 0x0},
-		{0x04,(0x04 << 3)|0x0, {{0x6b, 0xdcf8}, {0x68, 0xdcf8}, {0x69, 0xdcf8}, {0x6a, 0x0dcf8}}, 0x4, 0x0},
-		{0x04,(0x05 << 3)|0x0, {{0x63, 0xdcd8}, {0x62, 0xdcf8}, {0x61, 0xdcf8}, {0x60, 0x0dcf8}}, 0x5, 0x0},
-		{0x04,(0x06 << 3)|0x0, {{0x62, 0xdcf8}, {0x61, 0xdcf8}, {0x60, 0xdcf8}, {0x63, 0x0dcd8}}, 0x6, 0x0},
-		{0x04,(0x09 << 3)|0x0, {{0x69, 0xdcf8}, {0x6a, 0xdcf8}, {0x6b, 0xdcf8}, {0x68, 0x0dcf8}}, 0x9, 0x0},
-		{0x01,(0x00 << 3)|0x0, {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0x0dcd8}}, 0x0, 0x0}, /* Ethernet 8168 */
-		{0x02,(0x00 << 3)|0x0, {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0x0dcd8}}, 0x9, 0x0},
-		{0x03,(0x00 << 3)|0x0, {{0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0xdcd8}, {0x60, 0x0dcf8}}, 0xa, 0x0},
+	       /* bus,PCI_DEVFN(dev, fn),  {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap},  slot, rfu */
+		{0x00,PCI_DEVFN(0x01, 0), {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0x0dcd8}}, 0x0, 0x0}, /* PCIe? */
+		{0x00,PCI_DEVFN(0x02, 0), {{0x60, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, /* VGA */
+		{0x00,PCI_DEVFN(0x1e, 0), {{0x61, 0xdcf8}, {0x68, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, /* PCI bridge */
+		{0x00,PCI_DEVFN(0x1f, 0), {{0x62, 0xdcf8}, {0x63, 0xdcd8}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, /* LPC */
+		{0x00,PCI_DEVFN(0x1d, 0), {{0x6b, 0xdcf8}, {0x63, 0xdcd8}, {0x62, 0xdcf8}, {0x60, 0x0dcf8}}, 0x0, 0x0}, /* USB#1 */
+		{0x00,PCI_DEVFN(0x1b, 0), {{0x60, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, /* Audio device */
+		{0x00,PCI_DEVFN(0x1c, 0), {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0x0dcd8}}, 0x2, 0x0}, /* PCIe bridge */
+		{0x04,PCI_DEVFN(0x00, 0), {{0x60, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, /* Firewire */
+		{0x04,PCI_DEVFN(0x01, 0), {{0x68, 0xdcf8}, {0x69, 0xdcf8}, {0x6a, 0xdcf8}, {0x6b, 0x0dcf8}}, 0x1, 0x0}, /* PCI Bridge */
+		{0x04,PCI_DEVFN(0x02, 0), {{0x69, 0xdcf8}, {0x6a, 0xdcf8}, {0x6b, 0xdcf8}, {0x68, 0x0dcf8}}, 0x2, 0x0},
+		{0x04,PCI_DEVFN(0x03, 0), {{0x6a, 0xdcf8}, {0x6b, 0xdcf8}, {0x68, 0xdcf8}, {0x69, 0x0dcf8}}, 0x3, 0x0},
+		{0x04,PCI_DEVFN(0x04, 0), {{0x6b, 0xdcf8}, {0x68, 0xdcf8}, {0x69, 0xdcf8}, {0x6a, 0x0dcf8}}, 0x4, 0x0},
+		{0x04,PCI_DEVFN(0x05, 0), {{0x63, 0xdcd8}, {0x62, 0xdcf8}, {0x61, 0xdcf8}, {0x60, 0x0dcf8}}, 0x5, 0x0},
+		{0x04,PCI_DEVFN(0x06, 0), {{0x62, 0xdcf8}, {0x61, 0xdcf8}, {0x60, 0xdcf8}, {0x63, 0x0dcd8}}, 0x6, 0x0},
+		{0x04,PCI_DEVFN(0x09, 0), {{0x69, 0xdcf8}, {0x6a, 0xdcf8}, {0x6b, 0xdcf8}, {0x68, 0x0dcf8}}, 0x9, 0x0},
+		{0x01,PCI_DEVFN(0x00, 0), {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0x0dcd8}}, 0x0, 0x0}, /* Ethernet 8168 */
+		{0x02,PCI_DEVFN(0x00, 0), {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0x0dcd8}}, 0x9, 0x0},
+		{0x03,PCI_DEVFN(0x00, 0), {{0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0xdcd8}, {0x60, 0x0dcf8}}, 0xa, 0x0},
 	}
 	/* clang-format on */
 };

From ce3b7f0e34257ea20a5694b2180d6f7bcf321079 Mon Sep 17 00:00:00 2001
From: Bora Guvendik <bora.guvendik@intel.com>
Date: Fri, 25 Oct 2024 17:06:21 -0700
Subject: [PATCH 0202/3886] soc/intel/pantherlake: Inject CSE TS into CBMEM
 timestamp table

Get boot performance timestamps from CSE and inject them into CBMEM
timestamp table. For Panther Lake, remove "Die Management Unit (DMU)
load completed" and add "ESE completed AUnit loading" instead.

 990:CSME ROM started execution                        0
 992:ESE completed AUnit loading                       0
 944:CSE sent 'Boot Stall Done' to PMC                 174,000
 945:CSE started to handle ICC configuration           274,000 (100,000)
 946:CSE sent 'Host BIOS Prep Done' to PMC             274,000 (0)
 947:CSE received 'CPU Reset Done Ack sent' from PMC   448,000 (174,000)
   0:1st timestamp                                     556,874 (108,874)

BUG=b:376218080
TEST=Able to see TS elapse prior to IA reset on Fatcat

Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Change-Id: Ie7716b8c371b82c13da1b0217dce1a16e7b95cee
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84872
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/soc/intel/common/block/cse/Kconfig        |  7 ++++
 .../block/include/intelblocks/cse_telemetry.h |  2 +
 .../include/intelblocks/cse_telemetry_v3.h    | 41 +++++++++++++++++++
 src/soc/intel/pantherlake/cse_telemetry.c     |  4 +-
 4 files changed, 52 insertions(+), 2 deletions(-)
 create mode 100644 src/soc/intel/common/block/include/intelblocks/cse_telemetry_v3.h

diff --git a/src/soc/intel/common/block/cse/Kconfig b/src/soc/intel/common/block/cse/Kconfig
index bfef3d5db8..d1548a1fcb 100644
--- a/src/soc/intel/common/block/cse/Kconfig
+++ b/src/soc/intel/common/block/cse/Kconfig
@@ -295,6 +295,13 @@ config SOC_INTEL_CSE_PRE_CPU_RESET_TELEMETRY_V2
 	  This config will make mainboard use version 2 of the CSE timestamp
 	  definitions, it can be used for Meteor Lake M/P.
 
+config SOC_INTEL_CSE_PRE_CPU_RESET_TELEMETRY_V3
+	bool
+	select SOC_INTEL_CSE_PRE_CPU_RESET_TELEMETRY
+	help
+	  This config will make mainboard use version 3 of the CSE timestamp
+	  definitions, it can be used for Panther Lake U/H.
+
 config SOC_INTEL_CSE_LITE_SYNC_IN_ROMSTAGE
 	bool
 	default !SOC_INTEL_CSE_LITE_SYNC_IN_RAMSTAGE
diff --git a/src/soc/intel/common/block/include/intelblocks/cse_telemetry.h b/src/soc/intel/common/block/include/intelblocks/cse_telemetry.h
index 291a264725..66cc7f40db 100644
--- a/src/soc/intel/common/block/include/intelblocks/cse_telemetry.h
+++ b/src/soc/intel/common/block/include/intelblocks/cse_telemetry.h
@@ -7,6 +7,8 @@
 #include "cse_telemetry_v1.h"
 #elif CONFIG(SOC_INTEL_CSE_PRE_CPU_RESET_TELEMETRY_V2)
 #include "cse_telemetry_v2.h"
+#elif CONFIG(SOC_INTEL_CSE_PRE_CPU_RESET_TELEMETRY_V3)
+#include "cse_telemetry_v3.h"
 #endif
 
 #endif // SOC_INTEL_COMMON_CSE_TELEMETRY_H
diff --git a/src/soc/intel/common/block/include/intelblocks/cse_telemetry_v3.h b/src/soc/intel/common/block/include/intelblocks/cse_telemetry_v3.h
new file mode 100644
index 0000000000..6dbadff986
--- /dev/null
+++ b/src/soc/intel/common/block/include/intelblocks/cse_telemetry_v3.h
@@ -0,0 +1,41 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#ifndef SOC_INTEL_COMMON_CSE_TELEMETRY_V3_H
+#define SOC_INTEL_COMMON_CSE_TELEMETRY_V3_H
+
+enum cse_boot_perf_data_v3 {
+	/* CSME ROM start execution  */
+	PERF_DATA_CSME_ROM_START = 0,
+
+	/* 1 - 5 Reserved */
+
+	/* CSME RBE set "Boot Stall Done" indication to PMC */
+	PERF_DATA_CSME_RBE_BOOT_STALL_DONE_TO_PMC = 6,
+
+	/* 7 - 14 Reserved */
+
+	/* CSME got ICC_CFG_START message from PMC */
+	PERF_DATA_CSME_GOT_ICC_CFG_START_MSG_FROM_PMC = 15,
+
+	/* 15 - 16 Reserved */
+
+	/* CSME set "Host Boot Prep Done" indication to PMC */
+	PERF_DATA_CSME_HOST_BOOT_PREP_DONE = 17,
+
+	/* 18 - 32 Reserved */
+
+	/* PMC sent "Core Reset Done Ack - Sent" message to CSME */
+	PERF_DATA_PMC_SENT_CRDA = 33,
+
+	/* 34 - 35 Reserved */
+
+	/* ESE completed AUnit loading */
+	PERF_DATA_ESE_LOAD_AUNIT_COMPLETED = 36,
+
+	/* 37 - 62 Reserved */
+
+	/* Timestamp when CSME responded to BupGetBootData message itself */
+	PERF_DATA_CSME_GET_PERF_RESPONSE = 63,
+};
+
+#endif /* SOC_INTEL_COMMON_CSE_TELEMETRY_V3_H */
diff --git a/src/soc/intel/pantherlake/cse_telemetry.c b/src/soc/intel/pantherlake/cse_telemetry.c
index 6a599c9306..60faeb2b31 100644
--- a/src/soc/intel/pantherlake/cse_telemetry.c
+++ b/src/soc/intel/pantherlake/cse_telemetry.c
@@ -24,6 +24,6 @@ void soc_cbmem_inject_telemetry_data(s64 *ts, s64 current_time)
 		start_stamp + ts[PERF_DATA_CSME_HOST_BOOT_PREP_DONE]);
 	timestamp_add(TS_ME_RECEIVED_CRDA_FROM_PMC,
 		start_stamp + ts[PERF_DATA_PMC_SENT_CRDA]);
-	timestamp_add(TS_ISSE_DMU_LOAD_END,
-		start_stamp + ts[PERF_DATA_ISSE_DMU_LOAD_COMPLETED]);
+	timestamp_add(TS_ESE_LOAD_AUNIT_END,
+		start_stamp + ts[PERF_DATA_ESE_LOAD_AUNIT_COMPLETED]);
 }

From b927d558bb452cf723c34ff9c363dca3cc6b9909 Mon Sep 17 00:00:00 2001
From: John Su <john_su@compal.corp-partner.google.com>
Date: Thu, 13 Feb 2025 14:31:44 +0800
Subject: [PATCH 0203/3886] mb/google/trulo/var/uldrenite: Enable DPTF
 oem_variables

Support oem_variables and change based on EC notify event.

BUG=b:394177292
BRANCH=firmware-trulo-15217.771.B
TEST=emerge-nissa coreboot

Change-Id: Iac18cb968906a9dfe53836432ba8dbefee1dcc8e
Signed-off-by: John Su <john_su@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86394
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
---
 .../google/brya/variants/uldrenite/include/variant/ec.h     | 3 +++
 .../google/brya/variants/uldrenite/overridetree.cb          | 6 +++++-
 2 files changed, 8 insertions(+), 1 deletion(-)

diff --git a/src/mainboard/google/brya/variants/uldrenite/include/variant/ec.h b/src/mainboard/google/brya/variants/uldrenite/include/variant/ec.h
index 7a2a6ff8b7..818cdef7df 100644
--- a/src/mainboard/google/brya/variants/uldrenite/include/variant/ec.h
+++ b/src/mainboard/google/brya/variants/uldrenite/include/variant/ec.h
@@ -5,4 +5,7 @@
 
 #include <baseboard/ec.h>
 
+/* Enable DPTF OEM variable */
+#define DPTF_ENABLE_OEM_VARIABLES
+
 #endif
diff --git a/src/mainboard/google/brya/variants/uldrenite/overridetree.cb b/src/mainboard/google/brya/variants/uldrenite/overridetree.cb
index fdc933eb3b..5571fe7902 100644
--- a/src/mainboard/google/brya/variants/uldrenite/overridetree.cb
+++ b/src/mainboard/google/brya/variants/uldrenite/overridetree.cb
@@ -225,7 +225,11 @@ chip soc/intel/alderlake
 					[3] = {   8,  500 }
 				}"
 
-				device generic 0 on end
+				register "oem_data.oem_variables" = "{
+						[0] = 0x0
+				}"
+
+				device generic 0 alias dptf_policy on end
 			end
 		end # DPTF
 		device ref tcss_xhci on

From a53d8ad8ac01f5ea127899c045a853bb5ca26174 Mon Sep 17 00:00:00 2001
From: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com>
Date: Wed, 12 Feb 2025 19:21:44 +0900
Subject: [PATCH 0204/3886] mb/google/nissa/var/meliks: Generate SPD ID for 3
 supported parts

Add supported memory parts in mem_parts_used.txt, and generate
SPD id for these parts.

- K3KL6L60GM-MGCT (Samsung)
- MT62F512M32D2DR-031 WT:B (Micron)
- K3KL8L80DM-MGCU (Samsung)

BUG=b:394359785
TEST=Build coreboot and verified booting to depthcharge

Change-Id: Ief1272ef4cb7971c3abfe6ee982b019121f54793
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86375
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
---
 .../google/brya/variants/meliks/memory/Makefile.mk        | 8 ++++++--
 .../brya/variants/meliks/memory/dram_id.generated.txt     | 8 ++++++++
 .../google/brya/variants/meliks/memory/mem_parts_used.txt | 3 +++
 3 files changed, 17 insertions(+), 2 deletions(-)

diff --git a/src/mainboard/google/brya/variants/meliks/memory/Makefile.mk b/src/mainboard/google/brya/variants/meliks/memory/Makefile.mk
index eace2e443e..1f7a706678 100644
--- a/src/mainboard/google/brya/variants/meliks/memory/Makefile.mk
+++ b/src/mainboard/google/brya/variants/meliks/memory/Makefile.mk
@@ -1,5 +1,9 @@
 # SPDX-License-Identifier: GPL-2.0-or-later
 # This is an auto-generated file. Do not edit!!
-# Add memory parts in mem_parts_used.txt and run spd_tools to regenerate.
+# Generated by:
+# util/spd_tools/bin/part_id_gen ADL lp5 src/mainboard/google/brya/variants/meliks/memory src/mainboard/google/brya/variants/meliks/memory/mem_parts_used.txt
 
-SPD_SOURCES = placeholder
+SPD_SOURCES =
+SPD_SOURCES += spd/lp5/set-0/spd-9.hex      # ID = 0(0b0000)  Parts = K3KL6L60GM-MGCT
+SPD_SOURCES += spd/lp5/set-0/spd-1.hex      # ID = 1(0b0001)  Parts = MT62F512M32D2DR-031 WT:B
+SPD_SOURCES += spd/lp5/set-0/spd-11.hex      # ID = 2(0b0010)  Parts = K3KL8L80DM-MGCU
diff --git a/src/mainboard/google/brya/variants/meliks/memory/dram_id.generated.txt b/src/mainboard/google/brya/variants/meliks/memory/dram_id.generated.txt
index fa247902ee..5ca8b34c83 100644
--- a/src/mainboard/google/brya/variants/meliks/memory/dram_id.generated.txt
+++ b/src/mainboard/google/brya/variants/meliks/memory/dram_id.generated.txt
@@ -1 +1,9 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+# This is an auto-generated file. Do not edit!!
+# Generated by:
+# util/spd_tools/bin/part_id_gen ADL lp5 src/mainboard/google/brya/variants/meliks/memory src/mainboard/google/brya/variants/meliks/memory/mem_parts_used.txt
+
 DRAM Part Name                 ID to assign
+K3KL6L60GM-MGCT                0 (0000)
+MT62F512M32D2DR-031 WT:B       1 (0001)
+K3KL8L80DM-MGCU                2 (0010)
diff --git a/src/mainboard/google/brya/variants/meliks/memory/mem_parts_used.txt b/src/mainboard/google/brya/variants/meliks/memory/mem_parts_used.txt
index 2499005682..cb07b5236e 100644
--- a/src/mainboard/google/brya/variants/meliks/memory/mem_parts_used.txt
+++ b/src/mainboard/google/brya/variants/meliks/memory/mem_parts_used.txt
@@ -9,3 +9,6 @@
 # See util/spd_tools/README.md for more details and instructions.
 
 # Part Name
+K3KL6L60GM-MGCT
+MT62F512M32D2DR-031 WT:B
+K3KL8L80DM-MGCU

From 4ba6dc6b1c23cea0813f93335b8d4d37bae9aed3 Mon Sep 17 00:00:00 2001
From: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com>
Date: Wed, 12 Feb 2025 18:33:24 +0900
Subject: [PATCH 0205/3886] =?UTF-8?q?mb/google/nissa/var/meliks:=20Copy=20?=
 =?UTF-8?q?pirrha=E2=80=99s=20overridetree=20as=20initial=20one?=
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Upload the initial devicetree for meliks.

All devices and port usages are the same as pirrha, just copied from
pirrha's devicetree for the initial configuration except
typec_aux_bias_pads[0] since pirrha had incorrect setting.

About detection method of the touch screen device, the panel-built-in
touch screen for meliks needs some delay after panel power up, so it
may not be detected in coreboot phase. So we would keep `probed`
instead of `detect` for this special touch screen device to avoid
missing it in OS.

BUG=b:394359785
BRANCH=nissa
TEST=FW_NAME=meliks emerge-nissa coreboot

Change-Id: Ifd6dfbeca7276dbacd72f9145ed7119566c8faef
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86377
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
---
 .../brya/variants/meliks/overridetree.cb      | 510 +++++++++++++++++-
 1 file changed, 508 insertions(+), 2 deletions(-)

diff --git a/src/mainboard/google/brya/variants/meliks/overridetree.cb b/src/mainboard/google/brya/variants/meliks/overridetree.cb
index 4f2c04a57a..1d9ced5eb8 100644
--- a/src/mainboard/google/brya/variants/meliks/overridetree.cb
+++ b/src/mainboard/google/brya/variants/meliks/overridetree.cb
@@ -1,6 +1,512 @@
 chip soc/intel/alderlake
+	# GPE configuration
+	register "pmc_gpe0_dw1" = "GPP_C"
 
-        device domain 0 on
-        end
+	# Enable MIPI DSI on DDI port A
+	register "ddi_portA_config" = "2" # MIPI DSI
 
+	register "sagv" = "SaGv_Enabled"
+
+	# SOC Aux orientation override:
+	# This is a bitfield that corresponds to up to 4 TCSS ports.
+	# Bits (0,1) allocated for TCSS Port1 configuration and Bits (2,3)for TCSS Port2.
+	# TcssAuxOri = 0101b
+	# Bit0,Bit2 set to "1" indicates no retimer on USBC Ports
+	# Bit1,Bit3 set to "0" indicates Aux lines are not swapped on the
+	# motherboard to USBC connector
+	register "tcss_aux_ori" = "5"
+
+	register "typec_aux_bias_pads[0]" = "{.pad_auxp_dc = GPP_A14, .pad_auxn_dc = GPP_A15}"
+	register "typec_aux_bias_pads[1]" = "{.pad_auxp_dc = GPP_A21, .pad_auxn_dc = GPP_A22}"
+
+	register "usb2_ports[0]" = "{
+		.enable = 1,
+		.ocpin = OC_SKIP,
+		.pre_emp_bias = USB2_BIAS_28P15MV,
+		.tx_bias = USB2_BIAS_0MV,
+		.tx_emp_enable = USB2_DE_EMP_ON_PRE_EMP_ON,
+		.pre_emp_bit = USB2_FULL_BIT_PRE_EMP,
+		.type_c = 1,
+	}" # USB2_C0
+	register "usb2_ports[1]" = "{
+		.enable = 1,
+		.ocpin = OC_SKIP,
+		.pre_emp_bias = USB2_BIAS_28P15MV,
+		.tx_bias = USB2_BIAS_11P25MV,
+		.tx_emp_enable = USB2_DE_EMP_ON_PRE_EMP_ON,
+		.pre_emp_bit = USB2_FULL_BIT_PRE_EMP,
+		.type_c = 1,
+	}" # USB2_C1
+	register "usb2_ports[3]" = "{
+		.enable = 1,
+		.ocpin = OC_SKIP,
+		.pre_emp_bias = USB2_BIAS_28P15MV,
+		.tx_bias = USB2_BIAS_11P25MV,
+		.tx_emp_enable = USB2_DE_EMP_ON_PRE_EMP_ON,
+		.pre_emp_bit = USB2_FULL_BIT_PRE_EMP,
+	}" # USB2_A0
+	register "usb2_ports[4]" = "{
+		.enable = 1,
+		.ocpin = OC_SKIP,
+		.pre_emp_bias = USB2_BIAS_28P15MV,
+		.tx_bias = USB2_BIAS_0MV,
+		.tx_emp_enable = USB2_DE_EMP_ON,
+		.pre_emp_bit = USB2_FULL_BIT_PRE_EMP,
+	}" # uSD
+	register "usb2_ports[5]" = "{
+		.enable = 1,
+		.ocpin = OC_SKIP,
+		.tx_bias = USB2_BIAS_0MV,
+		.tx_emp_enable = USB2_DE_EMP_ON_PRE_EMP_ON,
+		.pre_emp_bias = USB2_BIAS_28P15MV,
+		.pre_emp_bit = USB2_FULL_BIT_PRE_EMP,
+	}" # UFCamera
+	register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)"	# Bluetooth port for CNVi WLAN
+
+	register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB3/2 Type A port A1
+
+	register "tcss_ports[0]" = "TCSS_PORT_DEFAULT(OC_SKIP)"
+	register "tcss_ports[1]" = "TCSS_PORT_DEFAULT(OC_SKIP)"
+
+	register "serial_io_i2c_mode" = "{
+		[PchSerialIoIndexI2C0] = PchSerialIoPci,
+		[PchSerialIoIndexI2C1] = PchSerialIoPci,
+		[PchSerialIoIndexI2C2] = PchSerialIoPci,
+		[PchSerialIoIndexI2C3] = PchSerialIoPci,
+		[PchSerialIoIndexI2C4] = PchSerialIoPci,
+		[PchSerialIoIndexI2C5] = PchSerialIoPci,
+	}"
+
+	# Configure external V1P05/Vnn/VnnSx Rails
+	register "ext_fivr_settings" = "{
+		.configure_ext_fivr = 1,
+		.v1p05_enable_bitmap = FIVR_ENABLE_ALL_SX & ~FIVR_ENABLE_S0,
+		.vnn_enable_bitmap = FIVR_ENABLE_ALL_SX ,
+		.vnn_sx_enable_bitmap = FIVR_ENABLE_ALL_SX ,
+		.v1p05_supported_voltage_bitmap = FIVR_VOLTAGE_NORMAL,
+		.vnn_supported_voltage_bitmap = FIVR_VOLTAGE_MIN_RETENTION,
+		.v1p05_voltage_mv = 1050,
+		.vnn_voltage_mv = 780,
+		.vnn_sx_voltage_mv = 1050,
+		.v1p05_icc_max_ma = 500,
+		.vnn_icc_max_ma = 500,
+	}"
+
+	# VR Settings
+	register "domain_vr_config[VR_DOMAIN_IA]" = "{
+		.vr_config_enable = 1,
+		.tdc_timewindow = 1000,
+		.ac_loadline = 500,
+		.dc_loadline = 500,
+		.psi1threshold = VR_CFG_AMP(20),
+		.psi2threshold = VR_CFG_AMP(5),
+		.psi3threshold = VR_CFG_AMP(1),
+	}"
+
+	register "domain_vr_config[VR_DOMAIN_GT]" = "{
+		.vr_config_enable = 1,
+		.tdc_timewindow = 1000,
+		.psi1threshold = VR_CFG_AMP(13),
+		.psi2threshold = VR_CFG_AMP(5),
+		.psi3threshold = VR_CFG_AMP(1),
+
+	}"
+
+	# Enable the Cnvi BT Audio Offload
+	register "cnvi_bt_audio_offload" = "1"
+
+	# Intel Common SoC Config
+	#+-------------------+---------------------------+
+	#| Field             |  Value                    |
+	#+-------------------+---------------------------+
+	#| I2C0              | TPM. Early init is        |
+	#|                   | required to set up a BAR  |
+	#|                   | for TPM communication     |
+	#| I2C1              | Touchscreen               |
+	#| I2C2              | WCAM                      |
+	#| I2C3              | Audio                     |
+	#| I2C4              | EMR                       |
+	#| I2C5              | Trackpad                  |
+	#+-------------------+---------------------------+
+	register "common_soc_config" = "{
+		.panel_orientation = LB_FB_ORIENTATION_RIGHT_UP,
+		.i2c[0] = {
+			.early_init = 1,
+			.speed = I2C_SPEED_FAST_PLUS,
+			.speed_config[0] = {
+				.speed = I2C_SPEED_FAST_PLUS,
+				.scl_lcnt = 55,
+				.scl_hcnt = 30,
+				.sda_hold = 7,
+			}
+		},
+		.i2c[1] = {
+			.speed = I2C_SPEED_FAST,
+			.speed_config[0] = {
+				.speed = I2C_SPEED_FAST,
+				.scl_lcnt = 157,
+				.scl_hcnt = 79,
+				.sda_hold = 7,
+			}
+		},
+		.i2c[2] = {
+			.speed = I2C_SPEED_FAST,
+			.speed_config[0] = {
+				.speed = I2C_SPEED_FAST,
+				.scl_lcnt = 157,
+				.scl_hcnt = 79,
+				.sda_hold = 7,
+			}
+		},
+		.i2c[3] = {
+			.speed = I2C_SPEED_FAST,
+			.speed_config[0] = {
+				.speed = I2C_SPEED_FAST,
+				.scl_lcnt = 158,
+				.scl_hcnt = 79,
+				.sda_hold = 7,
+			}
+		},
+		.i2c[4] = {
+			.speed = I2C_SPEED_FAST,
+			.speed_config[0] = {
+				.speed = I2C_SPEED_FAST,
+				.scl_lcnt = 158,
+				.scl_hcnt = 79,
+				.sda_hold = 7,
+			}
+		},
+		.i2c[5] = {
+			.speed = I2C_SPEED_FAST,
+			.speed_config[0] = {
+				.speed = I2C_SPEED_FAST,
+				.scl_lcnt = 158,
+				.scl_hcnt = 79,
+				.sda_hold = 7,
+			}
+		},
+	}"
+
+	device domain 0 on
+		device ref dtt on
+			chip drivers/intel/dptf
+				## sensor information
+				register "options.tsr[0].desc" = ""Memory""
+				register "options.tsr[1].desc" = ""Charger""
+				register "options.tsr[2].desc" = ""Ambient""
+				register "options.tsr[3].desc" = ""Sub Charger""
+
+				# TODO: below values are initial reference values only
+				## Passive Policy
+				register "policies.passive" = "{
+					[0] = DPTF_PASSIVE(CPU,         CPU,           95, 5000),
+					[1] = DPTF_PASSIVE(CPU,         TEMP_SENSOR_0, 75, 5000),
+					[2] = DPTF_PASSIVE(CHARGER,     TEMP_SENSOR_1, 75, 5000),
+					[3] = DPTF_PASSIVE(CPU,         TEMP_SENSOR_2, 75, 5000),
+					[3] = DPTF_PASSIVE(CPU,         TEMP_SENSOR_3, 75, 5000),
+				}"
+
+				## Critical Policy
+				register "policies.critical" = "{
+					[0] = DPTF_CRITICAL(CPU,               105, SHUTDOWN),
+					[1] = DPTF_CRITICAL(TEMP_SENSOR_0,      85, SHUTDOWN),
+					[2] = DPTF_CRITICAL(TEMP_SENSOR_1,      85, SHUTDOWN),
+					[3] = DPTF_CRITICAL(TEMP_SENSOR_2,      85, SHUTDOWN),
+					[4] = DPTF_CRITICAL(TEMP_SENSOR_3,      85, SHUTDOWN),
+				}"
+
+				register "controls.power_limits" = "{
+					.pl1 = {
+							.min_power = 3000,
+							.max_power = 6000,
+							.time_window_min = 28 * MSECS_PER_SEC,
+							.time_window_max = 32 * MSECS_PER_SEC,
+							.granularity = 200
+						},
+					.pl2 = {
+							.min_power = 25000,
+							.max_power = 25000,
+							.time_window_min = 1,
+							.time_window_max = 1,
+							.granularity = 1000
+						}
+				}"
+
+				## Charger Performance Control (Control, mA)
+				register "controls.charger_perf" = "{
+					[0] = { 255, 1700 },
+					[1] = {  24, 1500 },
+					[2] = {  16, 1000 },
+					[3] = {   8,  500 }
+				}"
+
+				device generic 0 on end
+			end
+		end
+		device ref ipu on
+			chip drivers/intel/mipi_camera
+				register "acpi_uid" = "0x50000"
+				register "acpi_name" = ""IPU0""
+				register "device_type" = "INTEL_ACPI_CAMERA_CIO2"
+				register "cio2_num_ports" = "1"
+				register "cio2_lanes_used" = "{4}" # 4 CSI Camera lanes are used
+				register "cio2_lane_endpoint[0]" = ""^I2C2.CAM0""
+				register "cio2_prt[0]" = "2"
+				device generic 0 on end
+			end
+		end
+		device ref cnvi_wifi on
+			chip drivers/wifi/generic
+				register "enable_cnvi_ddr_rfim" = "true"
+				device generic 0 on end
+			end
+		end
+		device ref i2c1 on
+			chip drivers/i2c/hid
+				register "generic.hid" = ""HX121A""
+				register "generic.desc" = ""HX Touchscreen""
+				register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_C7_IRQ)"
+				register "generic.probed" = "1"
+				register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C1)"
+				register "generic.reset_delay_ms" = "200"
+				register "generic.reset_off_delay_ms" = "2"
+				register "generic.has_power_resource" = "1"
+				register "hid_desc_reg_offset" = "0x1"
+				device i2c 4F on end
+			end
+		end
+		device ref i2c2 on
+			chip drivers/intel/mipi_camera
+				register "acpi_hid" = ""OVTI8856""
+				register "acpi_uid" = "0"
+				register "acpi_name" = ""CAM0""
+				register "chip_name" = ""Ov 8856 Camera""
+				register "device_type" = "INTEL_ACPI_CAMERA_SENSOR"
+
+				register "ssdb.lanes_used" = "4"
+				register "ssdb.link_used" = "1"
+				register "ssdb.vcm_type" = "0x0C"
+				register "vcm_name" = ""VCM0""
+				register "num_freq_entries" = "2"
+				register "link_freq[0]" = "360000000"
+				register "link_freq[1]" = "180000000"
+				register "remote_name" = ""IPU0""
+
+				register "has_power_resource" = "true"
+				#Controls
+				register "clk_panel.clks[0].clknum" = "IMGCLKOUT_3"
+				register "clk_panel.clks[0].freq" = "FREQ_19_2_MHZ"
+
+				register "gpio_panel.gpio[0].gpio_num" = "GPP_D15"  # EN_PP2800_WCAM_X
+				register "gpio_panel.gpio[1].gpio_num" = "GPP_D16"  # EN_PP1800_PP1200_WCAM_X
+				register "gpio_panel.gpio[2].gpio_num" = "GPP_D3"   # WCAM_RST_L
+
+				#_ON
+				register "on_seq.ops_cnt" = "5"
+				register "on_seq.ops[0]" = "SEQ_OPS_CLK_ENABLE(0, 0)"
+				register "on_seq.ops[1]" = "SEQ_OPS_GPIO_ENABLE(0, 5)"
+				register "on_seq.ops[2]" = "SEQ_OPS_GPIO_ENABLE(1, 5)"
+				register "on_seq.ops[3]" = "SEQ_OPS_GPIO_DISABLE(2, 5)"
+				register "on_seq.ops[4]" = "SEQ_OPS_GPIO_ENABLE(2, 5)"
+
+				#_OFF
+				register "off_seq.ops_cnt" = "4"
+				register "off_seq.ops[0]" = "SEQ_OPS_CLK_DISABLE(0, 0)"
+				register "off_seq.ops[1]" = "SEQ_OPS_GPIO_DISABLE(2, 0)"
+				register "off_seq.ops[2]" = "SEQ_OPS_GPIO_DISABLE(1, 0)"
+				register "off_seq.ops[3]" = "SEQ_OPS_GPIO_DISABLE(0, 0)"
+
+				device i2c 36 on end
+			end
+			chip drivers/intel/mipi_camera
+				register "acpi_uid" = "3"
+				register "acpi_name" = ""VCM0""
+				register "chip_name" = ""DW AF DAC""
+				register "device_type" = "INTEL_ACPI_CAMERA_VCM"
+
+				register "pr0" = ""\\_SB.PCI0.I2C2.CAM0.PRIC""
+				register "vcm_compat" = ""dongwoon,dw9714""
+
+				device i2c 0C on end
+			end
+			chip drivers/intel/mipi_camera
+				register "acpi_hid" = "ACPI_DT_NAMESPACE_HID"
+				register "acpi_uid" = "1"
+				register "acpi_name" = ""NVM0""
+				register "chip_name" = ""GT24C08""
+				register "device_type" = "INTEL_ACPI_CAMERA_NVM"
+
+				register "pr0" = ""\\_SB.PCI0.I2C2.CAM0.PRIC""
+
+				register "nvm_size" = "0x2000"
+				register "nvm_pagesize" = "1"
+				register "nvm_readonly" = "1"
+				register "nvm_width" = "0x10"
+				register "nvm_compat" = ""atmel,24c08""
+
+				device i2c 50 on end
+			end
+		end
+		device ref i2c3 on
+			chip drivers/i2c/da7219
+				register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_A23)"
+				register "btn_cfg" = "50"
+				register "mic_det_thr" = "200"
+				register "jack_ins_deb" = "20"
+				register "jack_det_rate" = ""32ms_64ms""
+				register "jack_rem_deb" = "1"
+				register "a_d_btn_thr" = "0xa"
+				register "d_b_btn_thr" = "0x16"
+				register "b_c_btn_thr" = "0x21"
+				register "c_mic_btn_thr" = "0x3e"
+				register "btn_avg" = "4"
+				register "adc_1bit_rpt" = "1"
+				register "micbias_lvl" = "2600"
+				register "mic_amp_in_sel" = ""diff""
+				device i2c 1a on end
+			end
+		end
+		device ref i2c4 on
+			chip drivers/i2c/hid
+				register "generic.hid" = ""WCOM014B""
+				register "generic.desc" = ""WCOM Digitizer""
+				register "generic.irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPP_F12)"
+				register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C0)"
+				register "generic.enable_delay_ms" = "20"
+				register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_F16)"
+				register "generic.reset_delay_ms" = "100"
+				register "generic.has_power_resource" = "1"
+				register "hid_desc_reg_offset" = "0x1"
+				device i2c 09 on end
+			end
+		end
+		device ref i2c5 on
+			chip drivers/i2c/hid
+				register "generic.hid" = ""ZNT0000""
+				register "generic.desc" = ""Zinitix Touchpad""
+				register "generic.irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_F14_IRQ)"
+				register "generic.wake" = "GPE0_DW2_14"
+				register "generic.detect" = "1"
+				register "hid_desc_reg_offset" = "0xE"
+				device i2c 40 on end
+			end
+		end
+		device ref hda on
+			chip drivers/generic/max98357a
+				register "hid" = ""MX98360A""
+				register "sdmode_gpio" =  "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A11)"
+				register "sdmode_delay" = "5"
+				device generic 0 on end
+			end
+			chip drivers/sof
+				register "spkr_tplg" = "max98360a"
+				register "jack_tplg" = "da7219"
+				register "mic_tplg" = "_2ch_pdm0"
+				device generic 0 on end
+			end
+		end
+		device ref pcie_rp7 off end
+		device ref pcie_rp9 off end
+		device ref ish on
+			chip drivers/intel/ish
+				register "add_acpi_dma_property" = "true"
+				device generic 0 on end
+			end
+		end
+		device ref ufs on end
+		device ref pch_espi on
+			chip ec/google/chromeec
+				use conn0 as mux_conn[0]
+				use conn1 as mux_conn[1]
+				device pnp 0c09.0 on end
+			end
+		end
+		device ref pmc hidden
+			chip drivers/intel/pmc_mux
+				device generic 0 on
+					chip drivers/intel/pmc_mux/conn
+						use usb2_port1 as usb2_port
+						use tcss_usb3_port1 as usb3_port
+						device generic 0 alias conn0 on end
+					end
+					chip drivers/intel/pmc_mux/conn
+						use usb2_port2 as usb2_port
+						use tcss_usb3_port2 as usb3_port
+						device generic 1 alias conn1 on end
+					end
+				end
+			end
+		end
+		device ref tcss_xhci on
+			chip drivers/usb/acpi
+				device ref tcss_root_hub on
+					chip drivers/usb/acpi
+						register "desc" = ""USB3 Type-C Port C0 (MLB)""
+						register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
+						register "use_custom_pld" = "true"
+						register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(1, 1))"
+						device ref tcss_usb3_port1 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB3 Type-C Port C1 (DB)""
+						register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
+						register "use_custom_pld" = "true"
+						register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, RIGHT, ACPI_PLD_GROUP(2, 1))"
+						device ref tcss_usb3_port2 on end
+					end
+				end
+			end
+		end
+		device ref xhci on
+			chip drivers/usb/acpi
+				device ref xhci_root_hub on
+					chip drivers/usb/acpi
+						register "desc" = ""USB2 Type-C Port C0 (MLB)""
+						register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
+						register "use_custom_pld" = "true"
+						register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(1, 1))"
+						device ref usb2_port1 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB2 Type-C Port C1 (DB)""
+						register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
+						register "use_custom_pld" = "true"
+						register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, RIGHT, ACPI_PLD_GROUP(2, 1))"
+						device ref usb2_port2 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB2 Type-A Port A1 (DB)""
+						register "type" = "UPC_TYPE_A"
+						register "use_custom_pld" = "true"
+						register "custom_pld" = "ACPI_PLD_TYPE_A(RIGHT, LEFT, ACPI_PLD_GROUP(4, 1))"
+						device ref usb2_port4 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB2 SDCard""
+						register "type" = "UPC_TYPE_EXPRESSCARD"
+						device ref usb2_port5 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB2 Camera""
+						register "type" = "UPC_TYPE_INTERNAL"
+						device ref usb2_port6 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB2 Bluetooth""
+						register "type" = "UPC_TYPE_INTERNAL"
+						register "reset_gpio" =
+							"ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D4)"
+						device ref usb2_port10 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB3 Type-A Port A1 (DB)""
+						register "type" = "UPC_TYPE_USB3_A"
+						register "use_custom_pld" = "true"
+						register "custom_pld" = "ACPI_PLD_TYPE_A(RIGHT, LEFT, ACPI_PLD_GROUP(4, 1))"
+						device ref usb3_port2 on end
+					end
+				end
+			end
+		end
+	end
 end

From f46f2cb6782fe00bd4ead528da99cf3465b7d28f Mon Sep 17 00:00:00 2001
From: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com>
Date: Wed, 12 Feb 2025 18:39:08 +0900
Subject: [PATCH 0206/3886] mb/google/nissa/var/meliks: Update GPIO
 configuration

Update the initial GPIO configuration for meliks by referring to
the schematics.

BUG=b:394359785
BRANCH=nissa
TEST=FW_NAME=meliks emerge-nissa coreboot

Change-Id: I33e1e3be5f2530feb396e7413f3f0cd75d5f38ca
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86378
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
---
 .../google/brya/variants/meliks/Makefile.mk   |   4 +
 .../google/brya/variants/meliks/gpio.c        | 109 ++++++++++++++++++
 .../variants/meliks/include/variant/gpio.h    |   2 +
 3 files changed, 115 insertions(+)
 create mode 100644 src/mainboard/google/brya/variants/meliks/gpio.c

diff --git a/src/mainboard/google/brya/variants/meliks/Makefile.mk b/src/mainboard/google/brya/variants/meliks/Makefile.mk
index c44e4f0364..227b163fc8 100644
--- a/src/mainboard/google/brya/variants/meliks/Makefile.mk
+++ b/src/mainboard/google/brya/variants/meliks/Makefile.mk
@@ -1,2 +1,6 @@
 # SPDX-License-Identifier: GPL-2.0-only
+bootblock-y += gpio.c
+
 romstage-y += memory.c
+
+ramstage-y += gpio.c
diff --git a/src/mainboard/google/brya/variants/meliks/gpio.c b/src/mainboard/google/brya/variants/meliks/gpio.c
new file mode 100644
index 0000000000..431b613c0a
--- /dev/null
+++ b/src/mainboard/google/brya/variants/meliks/gpio.c
@@ -0,0 +1,109 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <baseboard/gpio.h>
+#include <baseboard/variants.h>
+#include <commonlib/helpers.h>
+#include <soc/gpio.h>
+
+/* Pad configuration in ramstage */
+static const struct pad_config override_gpio_table[] = {
+	/* A14 : USB_C0_AUX_DC_P */
+	PAD_CFG_NF(GPP_A14, NONE, DEEP, NF6),
+	/* A15 : USB_C0_AUX_DC_N */
+	PAD_CFG_NF(GPP_A15, NONE, DEEP, NF6),
+
+	/* B11 : PMCALERT# ==> EN_PP3300_WLAN */
+	PAD_CFG_GPO(GPP_B11, 1, DEEP),
+
+	/* D6  : WWAN_EN ==> NC */
+	PAD_NC(GPP_D6, NONE),
+	/* D7  : WLAN_CLKREQ_ODL ==> NC */
+	PAD_NC(GPP_D7, NONE),
+	/* D8  : SD_CLKREQ_ODL ==> NC */
+	PAD_NC(GPP_D8, NONE),
+
+	/* E14 : EDP_HPD ==> NC */
+	PAD_NC(GPP_E14, NONE),
+	/* E20 : HDMI_DDC_SCL ==> NC */
+	PAD_NC(GPP_E20, NONE),
+	/* E21 : DDP2_CTRLDATA ==> HDMI_DDC_SDA_STRAP */
+	PAD_CFG_NF(GPP_E21, NONE, DEEP, NF1),
+	/* E22 : DDPA_CTRLCLK ==> LCD_RST_N - used for MIPI Power seq. */
+	PAD_CFG_NF(GPP_E22, NONE, DEEP, NF1),
+	/* E23 : NC */
+	PAD_NC(GPP_E23, NONE),
+
+	/* F6  : NC */
+	PAD_NC(GPP_F6, NONE),
+	/* F12 : GSXDOUT ==> EMR_INT_ODL */
+	PAD_CFG_GPI_INT(GPP_F12, NONE, PLTRST, LEVEL),
+	/* F13 : SOC_PEN_DETECT_R_ODL ==> NC */
+	PAD_NC(GPP_F13, NONE),
+	/* F15 : SOC_PEN_DETECT_OEL ==> NC */
+	PAD_NC(GPP_F15, NONE),
+	/* F16 : GSXCLK ==> EMR_RESET_L */
+	PAD_CFG_GPO(GPP_F16, 0, DEEP),
+
+	/* H3  : NC */
+	PAD_NC(GPP_H3, NONE),
+	/* H8  : I2C4_SDA ==> SOC_I2C_EMR_SDA */
+	PAD_CFG_NF(GPP_H8, NONE, DEEP, NF1),
+	/* H9  : I2C4_SCL ==> SOC_I2C_EMR_SCL */
+	PAD_CFG_NF(GPP_H9, NONE, DEEP, NF1),
+	/* H12 : SD_PERST_L ==> NC */
+	PAD_NC(GPP_H12, NONE),
+	/* H19 : NC */
+	PAD_NC(GPP_H19, NONE),
+	/* H20 : NC */
+	PAD_NC(GPP_H20, NONE),
+
+	/* Configure the virtual CNVi Bluetooth I2S GPIO pads */
+	/* BT_I2S_BCLK */
+	PAD_CFG_NF(GPP_VGPIO_30, NONE, DEEP, NF3),
+	/* BT_I2S_SYNC */
+	PAD_CFG_NF(GPP_VGPIO_31, NONE, DEEP, NF3),
+	/* BT_I2S_SDO */
+	PAD_CFG_NF(GPP_VGPIO_32, NONE, DEEP, NF3),
+	/* BT_I2S_SDI */
+	PAD_CFG_NF(GPP_VGPIO_33, NONE, DEEP, NF3),
+	/* SSP2_SCLK */
+	PAD_CFG_NF(GPP_VGPIO_34, NONE, DEEP, NF1),
+	/* SSP2_SFRM */
+	PAD_CFG_NF(GPP_VGPIO_35, NONE, DEEP, NF1),
+	/* SSP_TXD */
+	PAD_CFG_NF(GPP_VGPIO_36, NONE, DEEP, NF1),
+	/* SSP_RXD */
+	PAD_CFG_NF(GPP_VGPIO_37, NONE, DEEP, NF1),
+};
+
+/* Early pad configuration in bootblock for pirrha */
+static const struct pad_config early_gpio_table[] = {
+	/* A13 : GPP_A13 ==> GSC_SOC_INT_ODL */
+	PAD_CFG_GPI_APIC(GPP_A13, NONE, PLTRST, LEVEL, INVERT),
+	/* E12 : THC0_SPI1_IO1 ==> SOC_WP_OD */
+	PAD_CFG_GPI_GPIO_DRIVER(GPP_E12, NONE, DEEP),
+	/* F18 : THC1_SPI2_INT# ==> EC_IN_RW_OD */
+	PAD_CFG_GPI(GPP_F18, NONE, DEEP),
+	/* H4  : I2C0_SDA ==> SOC_I2C_GSC_SDA */
+	PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1),
+	/* H5  : I2C0_SCL ==> SOC_I2C_GSC_SCL */
+	PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1),
+	/* H10 : UART0_RXD ==> UART_SOC_RX_DBG_TX */
+	PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2),
+	/* H11 : UART0_TXD ==> UART_SOC_TX_DBG_RX */
+	PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2),
+	/* H13 : UART0_CTS# ==> EN_PP3300_SD_X */
+	PAD_CFG_GPO(GPP_H13, 1, DEEP),
+};
+
+const struct pad_config *variant_gpio_override_table(size_t *num)
+{
+	*num = ARRAY_SIZE(override_gpio_table);
+	return override_gpio_table;
+}
+
+const struct pad_config *variant_early_gpio_table(size_t *num)
+{
+	*num = ARRAY_SIZE(early_gpio_table);
+	return early_gpio_table;
+}
diff --git a/src/mainboard/google/brya/variants/meliks/include/variant/gpio.h b/src/mainboard/google/brya/variants/meliks/include/variant/gpio.h
index c4fe342621..b98b09d2e2 100644
--- a/src/mainboard/google/brya/variants/meliks/include/variant/gpio.h
+++ b/src/mainboard/google/brya/variants/meliks/include/variant/gpio.h
@@ -5,4 +5,6 @@
 
 #include <baseboard/gpio.h>
 
+#define SD_CARD_POWER		GPP_H13
+
 #endif

From 5cc8685fcdb2d13bdcc887ef45fd9b8eafc72a68 Mon Sep 17 00:00:00 2001
From: Shuo Liu <shuo.liu@intel.com>
Date: Mon, 13 Mar 2023 22:40:09 +0800
Subject: [PATCH 0207/3886] util/cbfstool: Add missing \n and use __func__ in
 debug messages

For adding missing \n, find all potential missings by below script
and apply manual checks and fixes.

grep -nE "(DEBUG|ERROR)\(\".+[^\\n]\"" util/cbfstool/ -r

For using __func__ in debug message, below script is used with
manual checks and fixes.

grep -nE "DEBUG\(.+:" util/cbfstool/ -r

Change-Id: I3e2c225dc16a65470f9f94db89d8ec3711e781c8
Signed-off-by: Shuo Liu <shuo.liu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86567
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 util/cbfstool/cbfs_image.c | 28 ++++++++++++++--------------
 util/cbfstool/fit.c        |  8 ++++----
 2 files changed, 18 insertions(+), 18 deletions(-)

diff --git a/util/cbfstool/cbfs_image.c b/util/cbfstool/cbfs_image.c
index e9353570cb..bb7c6f102a 100644
--- a/util/cbfstool/cbfs_image.c
+++ b/util/cbfstool/cbfs_image.c
@@ -257,13 +257,13 @@ int cbfs_legacy_image_create(struct cbfs_image *image,
 	void *header_loc;
 	size_t size = image->buffer.size;
 
-	DEBUG("cbfs_image_create: bootblock=0x%x+0x%zx, "
-	      "header=0x%x+0x%zx, entries_offset=0x%x\n",
+	DEBUG("%s: bootblock=0x%x+0x%zx, "
+	      "header=0x%x+0x%zx, entries_offset=0x%x\n", __func__,
 	      bootblock_offset, bootblock->size, header_offset,
 	      sizeof(image->header), entries_offset);
 
-	DEBUG("cbfs_create_image: (real offset) bootblock=0x%x, "
-	      "header=0x%x, entries_offset=0x%x\n",
+	DEBUG("%s: (real offset) bootblock=0x%x, "
+	      "header=0x%x, entries_offset=0x%x\n", __func__,
 	      bootblock_offset, header_offset, entries_offset);
 
 	// Prepare bootblock
@@ -636,7 +636,7 @@ static int cbfs_add_entry_at(struct cbfs_image *image,
 	if (header_offset % align)
 		header_offset -= header_offset % align;
 	if (header_offset < addr) {
-		ERROR("No space to hold cbfs_file header.");
+		ERROR("No space to hold cbfs_file header.\n");
 		return -1;
 	}
 
@@ -771,7 +771,7 @@ int cbfs_add_entry(struct cbfs_image *image, struct buffer *buffer,
 		entry_size = addr_next - addr;
 		max_null_entry_size = MAX(max_null_entry_size, entry_size);
 
-		DEBUG("cbfs_add_entry: space at 0x%x+0x%x(%d) bytes\n",
+		DEBUG("%s: space at 0x%x+0x%x(%d) bytes\n", __func__,
 		      addr, entry_size, entry_size);
 
 		/* Will the file fit? Don't yet worry if we have space for a new
@@ -783,10 +783,10 @@ int cbfs_add_entry(struct cbfs_image *image, struct buffer *buffer,
 		// Test for complicated cases
 		if (content_offset > 0) {
 			if (addr_next < content_offset) {
-				DEBUG("Not for specified offset yet");
+				DEBUG("Not for specified offset yet.\n");
 				continue;
 			} else if (addr > content_offset) {
-				DEBUG("Exceed specified content_offset.");
+				DEBUG("Exceed specified content_offset.\n");
 				break;
 			} else if (addr + header_size > content_offset) {
 				ERROR("Not enough space for header.\n");
@@ -830,7 +830,7 @@ struct cbfs_file *cbfs_get_entry(struct cbfs_image *image, const char *name)
 	     entry && cbfs_is_valid_entry(image, entry);
 	     entry = cbfs_find_next_entry(image, entry)) {
 		if (strcasecmp(entry->filename, name) == 0) {
-			DEBUG("cbfs_get_entry: found %s\n", name);
+			DEBUG("%s: found %s\n", __func__, name);
 			return entry;
 		}
 	}
@@ -1323,7 +1323,7 @@ int cbfs_remove_entry(struct cbfs_image *image, const char *name)
 		ERROR("CBFS file %s not found.\n", name);
 		return -1;
 	}
-	DEBUG("cbfs_remove_entry: Removed %s @ 0x%x\n",
+	DEBUG("%s: Removed %s @ 0x%x\n", __func__,
 	      entry->filename, cbfs_get_entry_addr(image, entry));
 	entry->type = htobe32(CBFS_TYPE_DELETED);
 	cbfs_legacy_walk(image, cbfs_merge_empty_entry, NULL);
@@ -1879,7 +1879,7 @@ struct cbfs_file_attribute *cbfs_add_file_attr(struct cbfs_file *header,
 	} while (next != NULL);
 	uint32_t header_size = be32toh(header->offset) + size;
 	if (header_size > CBFS_METADATA_MAX_SIZE) {
-		DEBUG("exceeding allocated space for cbfs_file headers");
+		DEBUG("exceeding allocated space for cbfs_file headers.\n");
 		return NULL;
 	}
 	/* attr points to the last valid attribute now.
@@ -2024,14 +2024,14 @@ int32_t cbfs_locate_entry(struct cbfs_image *image, size_t size,
 		offset = absolute_align(image, addr + metadata_size, align);
 		if (is_in_same_page(offset, size, page_size) &&
 		    is_in_range(addr, addr_next, metadata_size, offset, size)) {
-			DEBUG("cbfs_locate_entry: FIT (PAGE1).");
+			DEBUG("%s: FIT (PAGE1).\n", __func__);
 			return offset;
 		}
 
 		addr2 = align_up(addr, page_size);
 		offset = absolute_align(image, addr2, align);
 		if (is_in_range(addr, addr_next, metadata_size, offset, size)) {
-			DEBUG("cbfs_locate_entry: OVERLAP (PAGE2).");
+			DEBUG("%s: OVERLAP (PAGE2).\n", __func__);
 			return offset;
 		}
 
@@ -2041,7 +2041,7 @@ int32_t cbfs_locate_entry(struct cbfs_image *image, size_t size,
 		addr3 = addr2 + page_size;
 		offset = absolute_align(image, addr3, align);
 		if (is_in_range(addr, addr_next, metadata_size, offset, size)) {
-			DEBUG("cbfs_locate_entry: OVERLAP+ (PAGE3).");
+			DEBUG("%s: OVERLAP+ (PAGE3).\n", __func__);
 			return offset;
 		}
 	}
diff --git a/util/cbfstool/fit.c b/util/cbfstool/fit.c
index d4e48f1946..ca60720b2c 100644
--- a/util/cbfstool/fit.c
+++ b/util/cbfstool/fit.c
@@ -719,12 +719,12 @@ int fit_add_entry(struct fit_table *fit,
 	struct fit_entry *entry;
 
 	if (!fit) {
-		ERROR("Internal error.");
+		ERROR("Internal error.\n");
 		return 1;
 	}
 
 	if (fit_free_space(fit, max_fit_entries) < 1) {
-		ERROR("No space left in FIT.");
+		ERROR("No space left in FIT.\n");
 		return 1;
 	}
 
@@ -781,12 +781,12 @@ int fit_delete_entry(struct fit_table *fit,
 		     const size_t idx)
 {
 	if (!fit) {
-		ERROR("Internal error.");
+		ERROR("Internal error.\n");
 		return 1;
 	}
 
 	if (idx >= fit_table_entries(fit)) {
-		ERROR("Index out of range.");
+		ERROR("Index out of range.\n");
 		return 1;
 	}
 

From 0870f977c81ad871a8a497ef8ee002214b6f43f7 Mon Sep 17 00:00:00 2001
From: Brian Hsu <Brian_Hsu@pegatron.corp-partner.google.com>
Date: Tue, 11 Feb 2025 15:34:31 +0800
Subject: [PATCH 0208/3886] mb/google/nissa/var/guren: Add initial override
 devicetree

The schematic is the same as Glassway project and only difference for CPU.
Therefore, we clone the coreboot settings of glassway to guren
then remove some configurations to meet those keypart/design for guren.

BUG=b:397149037
BRANCH=firmware-nissa-15217.B
TEST=Local build successfully and boot to OOBE normally.

Change-Id: Ia43a78c340426069571172319be1675b3d94eba4
Signed-off-by: Brian Hsu <Brian_Hsu@pegatron.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86602
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
---
 src/mainboard/google/brya/Kconfig             |   9 +
 .../google/brya/variants/guren/Makefile.mk    |  11 +
 .../google/brya/variants/guren/data.vbt       | Bin 0 -> 9216 bytes
 .../google/brya/variants/guren/fw_config.c    |  45 ++
 .../google/brya/variants/guren/gpio.c         | 120 ++++
 .../variants/guren/include/variant/gpio.h     |   4 +
 .../brya/variants/guren/overridetree.cb       | 638 +++++++++++++++++-
 .../google/brya/variants/guren/ramstage.c     |   9 +
 .../google/brya/variants/guren/variant.c      |  19 +
 9 files changed, 850 insertions(+), 5 deletions(-)
 create mode 100644 src/mainboard/google/brya/variants/guren/Makefile.mk
 create mode 100644 src/mainboard/google/brya/variants/guren/data.vbt
 create mode 100644 src/mainboard/google/brya/variants/guren/fw_config.c
 create mode 100644 src/mainboard/google/brya/variants/guren/gpio.c
 create mode 100644 src/mainboard/google/brya/variants/guren/ramstage.c
 create mode 100644 src/mainboard/google/brya/variants/guren/variant.c

diff --git a/src/mainboard/google/brya/Kconfig b/src/mainboard/google/brya/Kconfig
index 5ab7d5de6c..0cc66243b5 100644
--- a/src/mainboard/google/brya/Kconfig
+++ b/src/mainboard/google/brya/Kconfig
@@ -297,6 +297,15 @@ config BOARD_GOOGLE_GOTHRAX
 
 config BOARD_GOOGLE_GUREN
 	select BOARD_GOOGLE_BASEBOARD_NISSA
+	select CHROMEOS_WIFI_SAR if CHROMEOS
+	select DRIVERS_GENERIC_GPIO_KEYS
+	select DRIVERS_GENESYSLOGIC_GL9750
+	select DRIVERS_I2C_SX9324
+	select DRIVERS_I2C_SX9324_SUPPORT_LEGACY_LINUX_DRIVER
+	select EC_GOOGLE_CHROMEEC_INCLUDE_SSFC_IN_FW_CONFIG
+	select HAVE_WWAN_POWER_SEQUENCE
+	select INTEL_GMA_HAVE_VBT
+	select SOC_INTEL_TWINLAKE
 
 config BOARD_GOOGLE_HADES
 	select BOARD_GOOGLE_BASEBOARD_HADES
diff --git a/src/mainboard/google/brya/variants/guren/Makefile.mk b/src/mainboard/google/brya/variants/guren/Makefile.mk
new file mode 100644
index 0000000000..b4698058ab
--- /dev/null
+++ b/src/mainboard/google/brya/variants/guren/Makefile.mk
@@ -0,0 +1,11 @@
+# SPDX-License-Identifier: GPL-2.0-only
+bootblock-y += gpio.c
+
+romstage-y += gpio.c
+
+ramstage-$(CONFIG_FW_CONFIG) += fw_config.c
+ramstage-y += gpio.c
+
+ramstage-y += variant.c
+
+ramstage-y += ramstage.c
diff --git a/src/mainboard/google/brya/variants/guren/data.vbt b/src/mainboard/google/brya/variants/guren/data.vbt
new file mode 100644
index 0000000000000000000000000000000000000000..ba47065a880a6a07a4332704ec9131e10d252d8f
GIT binary patch
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z{~`mepDG9FrEwxdG4ZM@OsnkK)Ym=n6_ZH+h={Ais>z@be3|vOR@!dggM&?HUYf_-
z>ngk?bI4Q-99KWXyJ`CZ(<lZX4ejtO3rRqQZPw122evYsC(CC3C~T`NL<_K0W!Y9{
z71AA=q61~g=F76(?PD}*Ut~RGB9?O4tT&1V`ukypk?Dw&MjV*s={OUxnP(I-3M|`_
ztrEFgpB;tG7H1T<udpCpr#ZC(nAS74u!$UW$1-_o5VnZ$hFbY;$4dhCLxqBuI3DQ{
zjarIU8D2`dL@Zw9UPmpqx~w>Fyp1o?&M>~9<9&dm7_rEA|B}x?8^6cF2HNuSe`Vkg
DU$Axx

literal 0
HcmV?d00001

diff --git a/src/mainboard/google/brya/variants/guren/fw_config.c b/src/mainboard/google/brya/variants/guren/fw_config.c
new file mode 100644
index 0000000000..52dff5c3ad
--- /dev/null
+++ b/src/mainboard/google/brya/variants/guren/fw_config.c
@@ -0,0 +1,45 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <baseboard/gpio.h>
+#include <baseboard/variants.h>
+#include <console/console.h>
+#include <fw_config.h>
+
+static const struct pad_config hdmi_disable_pads[] = {
+	/* A20  : DDSP_HPD2 ==> NC */
+	PAD_NC_LOCK(GPP_A20, NONE, LOCK_CONFIG),
+	/* E20 : DDP2_CTRLCLK ==> NC */
+	PAD_NC_LOCK(GPP_E20, NONE, LOCK_CONFIG),
+	/* E21 : DDP2_CTRLDATA ==> NC */
+	PAD_NC_LOCK(GPP_E21, NONE, LOCK_CONFIG),
+};
+
+static const struct pad_config lte_disable_pads[] = {
+	/* A8  : WWAN_RF_DISABLE_ODL */
+	PAD_NC(GPP_A8, NONE),
+	/* D6  : WWAN_EN */
+	PAD_NC(GPP_D6, NONE),
+	/* F12 : WWAN_RST_L */
+	PAD_NC_LOCK(GPP_F12, NONE, LOCK_CONFIG),
+	/* H19 : SOC_I2C_SUB_INT_ODL */
+	PAD_NC(GPP_H19, NONE),
+	/* H23 : WWAN_SAR_DETECT_ODL */
+	PAD_NC(GPP_H23, NONE),
+};
+
+void fw_config_gpio_padbased_override(struct pad_config *padbased_table)
+{
+	if (!fw_config_probe(FW_CONFIG(DB_USB, DB_HDMI_LTE))) {
+		printk(BIOS_INFO, "Disable HDMI GPIO pins.\n");
+		gpio_padbased_override(padbased_table, hdmi_disable_pads,
+						ARRAY_SIZE(hdmi_disable_pads));
+	}
+
+	/* Set to Disable LTE-related GPIO pins when field DB_USB is not DB_1C_LTE and DB_HDMI_LTE. */
+	if (!fw_config_probe(FW_CONFIG(DB_USB, DB_1C_LTE))
+		&& !fw_config_probe(FW_CONFIG(DB_USB, DB_HDMI_LTE))) {
+		printk(BIOS_INFO, "Disable LTE GPIO pins.\n");
+		gpio_padbased_override(padbased_table, lte_disable_pads,
+						ARRAY_SIZE(lte_disable_pads));
+	}
+}
diff --git a/src/mainboard/google/brya/variants/guren/gpio.c b/src/mainboard/google/brya/variants/guren/gpio.c
new file mode 100644
index 0000000000..0c462659c9
--- /dev/null
+++ b/src/mainboard/google/brya/variants/guren/gpio.c
@@ -0,0 +1,120 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <baseboard/gpio.h>
+#include <baseboard/variants.h>
+#include <soc/gpio.h>
+
+/* Pad configuration in ramstage for guren */
+static const struct pad_config override_gpio_table[] = {
+	/* A8  : WWAN_RF_DISABLE_ODL */
+	PAD_CFG_GPO(GPP_A8, 1, DEEP),
+	/* D3  : ISH_GP3 ==> NC */
+	PAD_NC_LOCK(GPP_D3, NONE, LOCK_CONFIG),
+	/* D6  : WWAN_EN */
+	PAD_CFG_GPO(GPP_D6, 1, DEEP),
+	/* D7  : SRCCLKREQ2# ==> WLAN_CLKREQ_ODL */
+	PAD_CFG_NF(GPP_D7, NONE, DEEP, NF1),
+	/* D15 : ISH_UART0_RTS# ==> NC */
+	PAD_NC_LOCK(GPP_D15, NONE, LOCK_CONFIG),
+	/* D16 : ISH_UART0_CTS# ==> NC */
+	PAD_NC_LOCK(GPP_D16, NONE, LOCK_CONFIG),
+	/* D17 : PCIE SLOT1 WAKE N */
+	PAD_NC_LOCK(GPP_D17, NONE, LOCK_CONFIG),
+	/* E4 : SDD_STRAP1 */
+	PAD_CFG_GPI(GPP_E4, NONE, DEEP),
+	/* E5 : SDD_STRAP2 */
+	PAD_CFG_GPI(GPP_E5, NONE, DEEP),
+	/* F12 : WWAN_RST_L */
+	PAD_CFG_GPO_LOCK(GPP_F12, 1, LOCK_CONFIG),
+	/* F13 : GSXSLOAD ==> NC */
+	PAD_NC_LOCK(GPP_F13, NONE, LOCK_CONFIG),
+	/* F15 : GSXSRESET# ==> NC */
+	PAD_NC_LOCK(GPP_F15, NONE, LOCK_CONFIG),
+	/* H19 : SOC_I2C_SUB_INT_ODL */
+	PAD_CFG_GPI_APIC(GPP_H19, NONE, PLTRST, LEVEL, NONE),
+	/* H22 : IMGCLKOUT3 ==> NC */
+	PAD_NC_LOCK(GPP_H22, NONE, LOCK_CONFIG),
+	/* H23 : WWAN_SAR_DETECT_ODL */
+	PAD_CFG_GPO(GPP_H23, 1, DEEP),
+	/* R4 : I2S2_SCLK ==> DMIC_UCAM_CLK_R */
+	PAD_CFG_NF(GPP_R4, NONE, DEEP, NF3),
+	/* R5 : I2S2_SFRM ==> DMIC_UCAM_DATA_R */
+	PAD_CFG_NF(GPP_R5, NONE, DEEP, NF3),
+	/* R6 : DMIC_CLK_A_1A ==> NC */
+	PAD_NC_LOCK(GPP_R6, NONE, LOCK_CONFIG),
+
+	/* Configure the virtual CNVi Bluetooth I2S GPIO pads */
+	/* BT_I2S_BCLK */
+	PAD_CFG_NF(GPP_VGPIO_30, NONE, DEEP, NF3),
+	/* BT_I2S_SYNC */
+	PAD_CFG_NF(GPP_VGPIO_31, NONE, DEEP, NF3),
+	/* BT_I2S_SDO */
+	PAD_CFG_NF(GPP_VGPIO_32, NONE, DEEP, NF3),
+	/* BT_I2S_SDI */
+	PAD_CFG_NF(GPP_VGPIO_33, NONE, DEEP, NF3),
+	/* SSP2_SCLK */
+	PAD_CFG_NF(GPP_VGPIO_34, NONE, DEEP, NF1),
+	/* SSP2_SFRM */
+	PAD_CFG_NF(GPP_VGPIO_35, NONE, DEEP, NF1),
+	/* SSP_TXD */
+	PAD_CFG_NF(GPP_VGPIO_36, NONE, DEEP, NF1),
+	/* SSP_RXD */
+	PAD_CFG_NF(GPP_VGPIO_37, NONE, DEEP, NF1),
+};
+
+/* Early pad configuration in bootblock for guren */
+static const struct pad_config early_gpio_table[] = {
+	/* F12 : GSXDOUT ==> WWAN_RST_L */
+	PAD_CFG_GPO(GPP_F12, 0, DEEP),
+	/* H12 : UART0_RTS# ==> SD_PERST_L */
+	PAD_CFG_GPO(GPP_H12, 0, DEEP),
+	/* A13 : GPP_A13 ==> GSC_SOC_INT_ODL */
+	PAD_CFG_GPI_APIC(GPP_A13, NONE, PLTRST, LEVEL, INVERT),
+	/* D6  : SRCCLKREQ1# ==> WWAN_EN */
+	PAD_CFG_GPO(GPP_D6, 1, DEEP),
+	/* E12 : THC0_SPI1_IO1 ==> SOC_WP_OD */
+	PAD_CFG_GPI_GPIO_DRIVER(GPP_E12, NONE, DEEP),
+	/* F18 : THC1_SPI2_INT# ==> EC_IN_RW_OD */
+	PAD_CFG_GPI(GPP_F18, NONE, DEEP),
+	/* H4  : I2C0_SDA ==> SOC_I2C_GSC_SDA */
+	PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1),
+	/* H5  : I2C0_SCL ==> SOC_I2C_GSC_SCL */
+	PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1),
+	/* H10 : UART0_RXD ==> UART_SOC_RX_DBG_TX */
+	PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2),
+	/* H11 : UART0_TXD ==> UART_SOC_TX_DBG_RX */
+	PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2),
+	/* H13 : UART0_CTS# ==> EN_PP3300_SD_X */
+	PAD_CFG_GPO(GPP_H13, 1, DEEP),
+};
+
+static const struct pad_config romstage_gpio_table[] = {
+	/* Enable touchscreen, hold in reset */
+	/* C0  : SMBCLK ==> EN_PP3300_TCHSCR */
+	PAD_CFG_GPO(GPP_C0, 1, DEEP),
+	/* C1  : SMBDATA ==> USI_RST_L */
+	PAD_CFG_GPO(GPP_C1, 0, DEEP),
+	/* C6  : SML1CLK ==> TCHSCR_REPORT_EN */
+	PAD_CFG_GPO(GPP_C6, 0, DEEP),
+	/* H12 : UART0_RTS# ==> SD_PERST_L */
+	PAD_CFG_GPO(GPP_H12, 1, DEEP),
+};
+
+const struct pad_config *variant_gpio_override_table(size_t *num)
+{
+	*num = ARRAY_SIZE(override_gpio_table);
+	return override_gpio_table;
+}
+
+const struct pad_config *variant_early_gpio_table(size_t *num)
+{
+	*num = ARRAY_SIZE(early_gpio_table);
+	return early_gpio_table;
+}
+
+
+const struct pad_config *variant_romstage_gpio_table(size_t *num)
+{
+	*num = ARRAY_SIZE(romstage_gpio_table);
+	return romstage_gpio_table;
+}
diff --git a/src/mainboard/google/brya/variants/guren/include/variant/gpio.h b/src/mainboard/google/brya/variants/guren/include/variant/gpio.h
index c4fe342621..c96b01fc15 100644
--- a/src/mainboard/google/brya/variants/guren/include/variant/gpio.h
+++ b/src/mainboard/google/brya/variants/guren/include/variant/gpio.h
@@ -5,4 +5,8 @@
 
 #include <baseboard/gpio.h>
 
+#define WWAN_FCPO	GPP_D6
+#define WWAN_RST	GPP_F12
+#define T2_OFF_MS	20
+
 #endif
diff --git a/src/mainboard/google/brya/variants/guren/overridetree.cb b/src/mainboard/google/brya/variants/guren/overridetree.cb
index 4f2c04a57a..95c4b58307 100644
--- a/src/mainboard/google/brya/variants/guren/overridetree.cb
+++ b/src/mainboard/google/brya/variants/guren/overridetree.cb
@@ -1,6 +1,634 @@
-chip soc/intel/alderlake
-
-        device domain 0 on
-        end
-
+fw_config
+	field THERMAL_SOLUTION 0
+		option THERMAL_SOLUTION_PASSIVE  0
+		option THERMAL_SOLUTION_ACTIVE   1
+	end
+	field DB_USB 5 8
+		option DB_NONE			0
+		option DB_1C			1
+		option DB_1A			2
+		option DB_1C_1A			3
+		option DB_1C_LTE		4
+		option DB_HDMI_LTE		5
+	end
+	field SD_CARD 9
+		option SD_ABSENT		 0
+		option SD_GL9750S		 1
+	end
+	field WIFI_SAR_ID 11 13
+		option WIFI_SAR_ID_INTEL_CONVERTIBLE		 0
+		option WIFI_SAR_ID_INTEL_CLAMSHELL		 1
+	end
+	field TOUCHSCREEN_SOURCE 32 34
+		option TOUCHSCREEN_UNPROVISIONED	0
+		option TOUCHSCREEN_ELAN0001		1
+	end
+end
+
+chip soc/intel/alderlake
+	register "sagv" = "SaGv_Enabled"
+
+	# EMMC Tx CMD Delay
+	# Refer to EDS-Vol2-42.3.7.
+	# [14:8] steps of delay for DDR mode, each 125ps, range: 0 - 39.
+	# [6:0] steps of delay for SDR mode, each 125ps, range: 0 - 39.
+	register "common_soc_config.emmc_dll.emmc_tx_cmd_cntl" = "0x505"
+
+	# EMMC TX DATA Delay 1
+	# Refer to EDS-Vol2-42.3.8.
+	# [14:8] steps of delay for HS400, each 125ps, range: 0 - 78.
+	# [6:0] steps of delay for SDR104/HS200, each 125ps, range: 0 - 79.
+	register "common_soc_config.emmc_dll.emmc_tx_data_cntl1" = "0x909"
+
+	# EMMC TX DATA Delay 2
+	# Refer to EDS-Vol2-42.3.9.
+	# [30:24] steps of delay for SDR50, each 125ps, range: 0 - 79.
+	# [22:16] steps of delay for DDR50, each 125ps, range: 0 - 78.
+	# [14:8] steps of delay for SDR25/HS50, each 125ps, range: 0 -79.
+	# [6:0] steps of delay for SDR12, each 125ps. Range: 0 - 79.
+	register "common_soc_config.emmc_dll.emmc_tx_data_cntl2" = "0x1C2A2828"
+
+	# EMMC RX CMD/DATA Delay 1
+	# Refer to EDS-Vol2-42.3.10.
+	# [30:24] steps of delay for SDR50, each 125ps, range: 0 - 119.
+	# [22:16] steps of delay for DDR50, each 125ps, range: 0 - 78.
+	# [14:8] steps of delay for SDR25/HS50, each 125ps, range: 0 - 119.
+	# [6:0] steps of delay for SDR12, each 125ps, range: 0 - 119.
+	register "common_soc_config.emmc_dll.emmc_rx_cmd_data_cntl1" = "0x1C1B4F1B"
+
+	# EMMC RX CMD/DATA Delay 2
+	# Refer to EDS-Vol2-42.3.12.
+	# [17:16] stands for Rx Clock before Output Buffer,
+	#         00: Rx clock after output buffer,
+	#         01: Rx clock before output buffer,
+	#         10: Automatic selection based on working mode.
+	#         11: Reserved
+	# [14:8] steps of delay for Auto Tuning Mode, each 125ps, range: 0 - 39.
+	# [6:0] steps of delay for HS200, each 125ps, range: 0 - 79.
+	register "common_soc_config.emmc_dll.emmc_rx_cmd_data_cntl2" = "0x10048"
+
+	# EMMC Rx Strobe Delay
+	# Refer to EDS-Vol2-42.3.11.
+	# [14:8] Rx Strobe Delay DLL 1(HS400 Mode), each 125ps, range: 0 - 39.
+	# [6:0] Rx Strobe Delay DLL 2(HS400 Mode), each 125ps, range: 0 - 39.
+	register "common_soc_config.emmc_dll.emmc_rx_strobe_cntl" = "0x01515"
+
+	# SOC Aux orientation override:
+	# This is a bitfield that corresponds to up to 4 TCSS ports.
+	# Bits (0,1) allocated for TCSS Port1 configuration and Bits (2,3)for TCSS Port2.
+	# TcssAuxOri = 0101b
+	# Bit0,Bit2 set to "1" indicates no retimer on USBC Ports
+	# Bit1,Bit3 set to "0" indicates Aux lines are not swapped on the
+	# motherboard to USBC connector
+	register "tcss_aux_ori" = "5"
+
+	register "typec_aux_bias_pads[0]" = "{.pad_auxp_dc = GPP_E22, .pad_auxn_dc = GPP_E23}"
+	register "typec_aux_bias_pads[1]" = "{.pad_auxp_dc = GPP_A21, .pad_auxn_dc = GPP_A22}"
+
+	register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)"	# Bluetooth port for CNVi WLAN
+
+	# Configure external V1P05/Vnn/VnnSx Rails
+	register "ext_fivr_settings" = "{
+		.configure_ext_fivr = 1,
+		.v1p05_enable_bitmap = FIVR_ENABLE_ALL_SX & ~FIVR_ENABLE_S0,
+		.vnn_enable_bitmap = FIVR_ENABLE_ALL_SX,
+		.vnn_sx_enable_bitmap = FIVR_ENABLE_ALL_SX,
+		.v1p05_supported_voltage_bitmap = FIVR_VOLTAGE_NORMAL,
+		.vnn_supported_voltage_bitmap = FIVR_VOLTAGE_MIN_ACTIVE,
+		.v1p05_voltage_mv = 1050,
+		.vnn_voltage_mv = 780,
+		.vnn_sx_voltage_mv = 1050,
+		.v1p05_icc_max_ma = 500,
+		.vnn_icc_max_ma = 500,
+	}"
+
+	# Enable the Cnvi BT Audio Offload
+	register "cnvi_bt_audio_offload" = "1"
+
+	# Intel Common SoC Config
+	#+-------------------+---------------------------+
+	#| Field             |  Value                    |
+	#+-------------------+---------------------------+
+	#| I2C0              | TPM. Early init is        |
+	#|                   | required to set up a BAR  |
+	#|                   | for TPM communication     |
+	#| I2C1              | Touchscreen               |
+	#| I2C2              | Sub-board(PSensor)/WCAM   |
+	#| I2C3              | Audio                     |
+	#| I2C5              | Trackpad                  |
+	#+-------------------+---------------------------+
+	register "common_soc_config" = "{
+		.i2c[0] = {
+			.early_init = 1,
+			.speed = I2C_SPEED_FAST_PLUS,
+			.speed_config[0] = {
+				.speed = I2C_SPEED_FAST_PLUS,
+				.scl_lcnt = 55,
+				.scl_hcnt = 30,
+				.sda_hold = 7,
+			}
+		},
+		.i2c[1] = {
+			.speed = I2C_SPEED_FAST,
+			.speed_config[0] = {
+				.speed = I2C_SPEED_FAST,
+				.scl_lcnt = 157,
+				.scl_hcnt = 79,
+				.sda_hold = 40,
+			}
+		},
+		.i2c[2] = {
+			.speed = I2C_SPEED_FAST,
+			.speed_config[0] = {
+				.speed = I2C_SPEED_FAST,
+				.scl_lcnt = 157,
+				.scl_hcnt = 79,
+				.sda_hold = 7,
+			}
+		},
+		.i2c[3] = {
+			.speed = I2C_SPEED_FAST,
+			.speed_config[0] = {
+				.speed = I2C_SPEED_FAST,
+				.scl_lcnt = 158,
+				.scl_hcnt = 79,
+				.sda_hold = 7,
+			}
+		},
+		.i2c[5] = {
+			.speed = I2C_SPEED_FAST,
+			.speed_config[0] = {
+				.speed = I2C_SPEED_FAST,
+				.scl_lcnt = 158,
+				.scl_hcnt = 79,
+				.sda_hold = 40,
+			}
+		},
+	}"
+
+	device domain 0 on
+		device ref dtt on
+			chip drivers/intel/dptf
+				## sensor information
+				register "options.tsr[0].desc" = ""Memory""
+				register "options.tsr[1].desc" = ""Charger""
+				register "options.tsr[2].desc" = ""Ambient""
+
+				# TODO: below values are initial reference values only
+				## Passive Policy
+				register "policies.passive" = "{
+					[0] = DPTF_PASSIVE(CPU,         CPU,           95, 5000),
+					[1] = DPTF_PASSIVE(CPU,         TEMP_SENSOR_0, 75, 5000),
+					[2] = DPTF_PASSIVE(CHARGER,     TEMP_SENSOR_1, 75, 5000),
+					[3] = DPTF_PASSIVE(CPU,         TEMP_SENSOR_2, 75, 5000),
+				}"
+
+				## Critical Policy
+				register "policies.critical" = "{
+					[0] = DPTF_CRITICAL(CPU,               105, SHUTDOWN),
+					[1] = DPTF_CRITICAL(TEMP_SENSOR_0,      85, SHUTDOWN),
+					[2] = DPTF_CRITICAL(TEMP_SENSOR_1,      85, SHUTDOWN),
+					[3] = DPTF_CRITICAL(TEMP_SENSOR_2,      85, SHUTDOWN),
+				}"
+
+				register "controls.power_limits" = "{
+					.pl1 = {
+							.min_power = 3000,
+							.max_power = 6000,
+							.time_window_min = 28 * MSECS_PER_SEC,
+							.time_window_max = 32 * MSECS_PER_SEC,
+							.granularity = 200
+						},
+					.pl2 = {
+							.min_power = 25000,
+							.max_power = 25000,
+							.time_window_min = 1,
+							.time_window_max = 1,
+							.granularity = 1000
+						}
+				}"
+
+				## Charger Performance Control (Control, mA)
+				register "controls.charger_perf" = "{
+					[0] = { 255, 1700 },
+					[1] = {  24, 1500 },
+					[2] = {  16, 1000 },
+					[3] = {   8,  500 }
+				}"
+
+				device generic 0 on
+					probe THERMAL_SOLUTION THERMAL_SOLUTION_PASSIVE
+				end
+			end
+			chip drivers/intel/dptf
+				## sensor information
+				register "options.tsr[0].desc" = ""Memory""
+				register "options.tsr[1].desc" = ""Charger""
+				register "options.tsr[2].desc" = ""Ambient""
+
+				# TODO: below values are initial reference values only
+				## Active Policy
+				register "policies.active" = "{
+					[0] = {
+						.target = DPTF_CPU,
+						.thresholds = {
+								TEMP_PCT(85, 90),
+								TEMP_PCT(80, 80),
+								TEMP_PCT(75, 70),
+								TEMP_PCT(70, 50),
+								TEMP_PCT(65, 30),
+						}
+					},
+					[1] = {
+						.target = DPTF_TEMP_SENSOR_2,
+						.thresholds = {
+								TEMP_PCT(50, 90),
+								TEMP_PCT(48, 70),
+								TEMP_PCT(46, 60),
+								TEMP_PCT(43, 40),
+								TEMP_PCT(40, 30),
+						}
+					}
+				}"
+
+				# TODO: below values are initial reference values only
+				## Passive Policy
+				register "policies.passive" = "{
+					[0] = DPTF_PASSIVE(CPU,         CPU,           95, 5000),
+					[1] = DPTF_PASSIVE(CPU,         TEMP_SENSOR_0, 75, 5000),
+					[2] = DPTF_PASSIVE(CHARGER,     TEMP_SENSOR_1, 75, 5000),
+					[3] = DPTF_PASSIVE(CPU,         TEMP_SENSOR_2, 75, 5000),
+				}"
+
+				## Critical Policy
+				register "policies.critical" = "{
+					[0] = DPTF_CRITICAL(CPU,               105, SHUTDOWN),
+					[1] = DPTF_CRITICAL(TEMP_SENSOR_0,      85, SHUTDOWN),
+					[2] = DPTF_CRITICAL(TEMP_SENSOR_1,      85, SHUTDOWN),
+					[3] = DPTF_CRITICAL(TEMP_SENSOR_2,      85, SHUTDOWN),
+				}"
+
+				register "controls.power_limits" = "{
+					.pl1 = {
+							.min_power = 12000,
+							.max_power = 15000,
+							.time_window_min = 28 * MSECS_PER_SEC,
+							.time_window_max = 32 * MSECS_PER_SEC,
+							.granularity = 200
+						},
+					.pl2 = {
+							.min_power = 35000,
+							.max_power = 35000,
+							.time_window_min = 1,
+							.time_window_max = 1,
+							.granularity = 1000
+						}
+				}"
+
+				## Charger Performance Control (Control, mA)
+				register "controls.charger_perf" = "{
+					[0] = { 255, 1700 },
+					[1] = {  24, 1500 },
+					[2] = {  16, 1000 },
+					[3] = {   8,  500 }
+				}"
+
+				## Fan Performance Control (Percent, Speed, Noise, Power)
+				register "controls.fan_perf" = "{
+					[0] = { 100, 6000, 220, 2200, },
+					[1] = {  92, 5500, 180, 1800, },
+					[2] = {  85, 5000, 145, 1450, },
+					[3] = {  70, 4400, 115, 1150, },
+					[4] = {  56, 3900,  90,  900, },
+					[5] = {  45, 3300,  55,  550, },
+					[6] = {  38, 3000,  30,  300, },
+					[7] = {  33, 2900,  15,  150, },
+					[8] = {  10,  800,  10,  100, },
+					[9] = {   0,    0,   0,   50, }
+				}"
+
+				## Fan options
+				register "options.fan.fine_grained_control" = "true"
+				register "options.fan.step_size" = "2"
+
+				device generic 1 on
+					probe THERMAL_SOLUTION THERMAL_SOLUTION_ACTIVE
+				end
+			end
+		end
+		device ref cnvi_wifi on
+			chip drivers/wifi/generic
+				register "enable_cnvi_ddr_rfim" = "true"
+				device generic 0 on end
+			end
+		end
+		device ref i2c1 on
+			chip drivers/i2c/generic
+				register "hid" = ""ELAN0001""
+				register "desc" = ""ELAN Touchscreen""
+				register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_C7_IRQ)"
+				register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C1)"
+				register "reset_delay_ms" = "20"
+				register "reset_off_delay_ms" = "4"
+				register "stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C6)"
+				register "stop_delay_ms" = "5"
+				register "stop_off_delay_ms" = "25"
+				register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C0)"
+				register "enable_delay_ms" = "25"
+				register "has_power_resource" = "true"
+				device i2c 10 on
+					probe TOUCHSCREEN_SOURCE TOUCHSCREEN_ELAN0001
+				end
+			end
+
+		end #I2C1
+		device ref i2c2 on
+			chip drivers/i2c/sx9324
+				register "desc" = ""SAR Proximity Sensor""
+				register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_H19_IRQ)"
+				register "speed" = "I2C_SPEED_FAST"
+				register "uid" = "1"
+				register "reg_gnrl_ctrl0" = "0x16"
+				register "reg_gnrl_ctrl1" = "0x21"
+				register "reg_afe_ctrl0" = "0x20"
+				register "reg_afe_ctrl3" = "0x00"
+				register "reg_afe_ctrl4" = "0x46"
+				register "reg_afe_ctrl6" = "0x00"
+				register "reg_afe_ctrl7" = "0x46"
+				register "reg_afe_ph0" = "0x3d"
+				register "reg_afe_ph1" = "0x1b"
+				register "reg_afe_ph2" = "0x1f"
+				register "reg_afe_ph3" = "0x3d"
+				register "reg_afe_ctrl8" = "0x12"
+				register "reg_afe_ctrl9" = "0x08"
+				register "reg_prox_ctrl0" = "0x0b"
+				register "reg_prox_ctrl1" = "0x0b"
+				register "reg_prox_ctrl2" = "0x20"
+				register "reg_prox_ctrl3" = "0x20"
+				register "reg_prox_ctrl4" = "0x0c"
+				register "reg_prox_ctrl5" = "0x00"
+				register "reg_prox_ctrl6" = "0x20"
+				register "reg_prox_ctrl7" = "0xc0"
+				register "reg_adv_ctrl0" = "0x00"
+				register "reg_adv_ctrl1" = "0x00"
+				register "reg_adv_ctrl2" = "0x00"
+				register "reg_adv_ctrl3" = "0x00"
+				register "reg_adv_ctrl4" = "0x00"
+				register "reg_adv_ctrl5" = "0x05"
+				register "reg_adv_ctrl6" = "0x00"
+				register "reg_adv_ctrl7" = "0x00"
+				register "reg_adv_ctrl8" = "0x00"
+				register "reg_adv_ctrl9" = "0x00"
+				register "reg_adv_ctrl10" = "0x00"
+				register "reg_adv_ctrl11" = "0x00"
+				register "reg_adv_ctrl12" = "0x00"
+				register "reg_adv_ctrl13" = "0x00"
+				register "reg_adv_ctrl14" = "0x80"
+				register "reg_adv_ctrl15" = "0x0c"
+				register "reg_adv_ctrl16" = "0x04"
+				register "reg_adv_ctrl17" = "0x70"
+				register "reg_adv_ctrl18" = "0x20"
+				register "reg_adv_ctrl19" = "0x00"
+				register "reg_adv_ctrl20" = "0x00"
+				register "reg_irq_msk" = "0x60"
+				register "reg_irq_cfg0" = "0x00"
+				register "reg_irq_cfg1" = "0x80"
+				register "reg_irq_cfg2" = "0x00"
+
+				register "ph0_pin" = "{1, 3, 3}"
+				register "ph1_pin" = "{3, 2, 1}"
+				register "ph2_pin" = "{3, 3, 1}"
+				register "ph3_pin" = "{1, 3, 3}"
+				register "ph01_resolution" = "512"
+				register "ph23_resolution" = "512"
+				register "startup_sensor" = "1"
+				register "ph01_proxraw_strength" = "3"
+				register "ph23_proxraw_strength" = "3"
+				register "avg_pos_strength" = "256"
+				register "cs_idle_sleep" = ""gnd""
+				register "int_comp_resistor" = ""lowest""
+				register "input_precharge_resistor_ohms" = "4000"
+				register "input_analog_gain" = "1"
+				device i2c 28 on
+					probe DB_USB DB_1C_LTE
+					probe DB_USB DB_HDMI_LTE
+				end
+			end
+		end #I2C2
+		device ref i2c3 on
+			chip drivers/i2c/generic
+				register "hid" = ""10EC5650""
+				register "name" = ""RT58""
+				register "desc" = ""Realtek RT5650""
+				register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_A23)"
+				register "property_count" = "1"
+				register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER"
+				register "property_list[0].name" = ""realtek,jd-mode""
+				register "property_list[0].integer" = "2"
+				device i2c 1a on end
+			end
+		end #I2C3
+		device ref i2c5 on
+			chip drivers/i2c/generic
+				register "hid" = ""ELAN0000""
+				register "desc" = ""ELAN Touchpad""
+				register "irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_F14_IRQ)"
+				register "wake" = "GPE0_DW2_14"
+				register "detect" = "1"
+				device i2c 15 on end
+			end
+			chip drivers/i2c/hid
+				register "generic.hid" = ""PNP0C50""
+				register "generic.desc" = ""PIXART Touchpad""
+				register "generic.irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_F14_IRQ)"
+				register "generic.wake" = "GPE0_DW2_14"
+				register "generic.detect" = "1"
+				register "hid_desc_reg_offset" = "0x20"
+				device i2c 2c on end
+			end
+		end #I2C5
+		device ref pcie_rp4 on
+			# Enable wlan PCIe 4 using clk 2
+			register "pch_pcie_rp[PCH_RP(4)]" = "{
+				.clk_src = 2,
+				.clk_req = 2,
+				.flags = PCIE_RP_LTR | PCIE_RP_AER,
+			}"
+			chip drivers/wifi/generic
+				register "add_acpi_dma_property" = "true"
+				device pci 00.0 on end
+			end
+		end
+		device ref pcie_rp7 on
+			# Enable SD Card PCIe 7 using clk 3
+			register "pch_pcie_rp[PCH_RP(7)]" = "{
+				.clk_src = 3,
+				.clk_req = 3,
+				.flags = PCIE_RP_HOTPLUG | PCIE_RP_LTR | PCIE_RP_AER,
+			}"
+			chip soc/intel/common/block/pcie/rtd3
+				register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_H13)"
+				register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_H12)"
+				register "srcclk_pin" = "3"
+				device generic 0 on end
+			end
+			probe SD_CARD SD_GL9750S
+		end
+		device ref emmc on
+			probe STORAGE STORAGE_EMMC
+		end
+		device ref ish on
+			chip drivers/intel/ish
+				register "add_acpi_dma_property" = "true"
+				device generic 0 on end
+			end
+			probe STORAGE STORAGE_UFS
+		end
+		device ref ufs on
+			probe STORAGE STORAGE_UFS
+		end
+		device ref pch_espi on
+			chip ec/google/chromeec
+				use conn0 as mux_conn[0]
+				use conn1 as mux_conn[1]
+				device pnp 0c09.0 on end
+			end
+		end
+		device ref pmc hidden
+			chip drivers/intel/pmc_mux
+				device generic 0 on
+					chip drivers/intel/pmc_mux/conn
+						use usb2_port1 as usb2_port
+						use tcss_usb3_port1 as usb3_port
+						device generic 0 alias conn0 on end
+					end
+					chip drivers/intel/pmc_mux/conn
+						use usb2_port2 as usb2_port
+						use tcss_usb3_port2 as usb3_port
+						device generic 1 alias conn1 on
+							probe DB_USB DB_1C
+							probe DB_USB DB_1A
+							probe DB_USB DB_1C_1A
+							probe DB_USB DB_1C_LTE
+						end
+					end
+				end
+			end
+		end
+		device ref tcss_xhci on
+			chip drivers/usb/acpi
+				device ref tcss_root_hub on
+					chip drivers/usb/acpi
+						register "desc" = ""USB3 Type-C Port C0 (MLB)""
+						register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
+						register "use_custom_pld" = "true"
+						register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(1, 1))"
+						device ref tcss_usb3_port1 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB3 Type-C Port C1 (DB)""
+						register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
+                                                register "use_custom_pld" = "true"
+                                                register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, RIGHT, ACPI_PLD_GROUP(2, 1))"
+						device ref tcss_usb3_port2 on
+							probe DB_USB DB_1C
+							probe DB_USB DB_1C_1A
+							probe DB_USB DB_1C_LTE
+						end
+					end
+				end
+			end
+		end
+		device ref xhci on
+			chip drivers/usb/acpi
+				device ref xhci_root_hub on
+					chip drivers/usb/acpi
+						register "desc" = ""USB2 Type-C Port C0 (MLB)""
+						register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
+                                                register "use_custom_pld" = "true"
+                                                register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(1, 1))"
+						device ref usb2_port1 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB2 Type-C Port C1 (DB)""
+						register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
+                                                register "use_custom_pld" = "true"
+                                                register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, RIGHT, ACPI_PLD_GROUP(2, 1))"
+						device ref usb2_port2 on
+							probe DB_USB DB_1C
+							probe DB_USB DB_1C_1A
+							probe DB_USB DB_1C_LTE
+						end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB2 Type-A Port A0 (MLB)""
+						register "type" = "UPC_TYPE_A"
+                                                register "use_custom_pld" = "true"
+                                                register "custom_pld" = "ACPI_PLD_TYPE_A(LEFT, RIGHT, ACPI_PLD_GROUP(3, 1))"
+						device ref usb2_port3 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB2 Type-A Port A1 (DB)""
+						register "type" = "UPC_TYPE_A"
+                                                register "use_custom_pld" = "true"
+                                                register "custom_pld" = "ACPI_PLD_TYPE_A(RIGHT, LEFT, ACPI_PLD_GROUP(4, 1))"
+						device ref usb2_port4 on
+							probe DB_USB DB_1A
+							probe DB_USB DB_1C_1A
+						end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB2 WWAN""
+						register "type" = "UPC_TYPE_INTERNAL"
+						device ref usb2_port4 on
+							probe DB_USB DB_1C_LTE
+							probe DB_USB DB_HDMI_LTE
+						end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB2 Camera""
+						register "type" = "UPC_TYPE_INTERNAL"
+						device ref usb2_port6 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB2 Camera""
+						register "type" = "UPC_TYPE_INTERNAL"
+						device ref usb2_port7 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB2 Bluetooth""
+						register "type" = "UPC_TYPE_INTERNAL"
+						register "reset_gpio" =
+							"ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D4)"
+						device ref usb2_port8 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB3 Type-A Port A0 (MLB)""
+						register "type" = "UPC_TYPE_USB3_A"
+                                                register "use_custom_pld" = "true"
+                                                register "custom_pld" = "ACPI_PLD_TYPE_A(LEFT, RIGHT, ACPI_PLD_GROUP(3, 1))"
+						device ref usb3_port1 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB3 Type-A Port A1 (DB)""
+						register "type" = "UPC_TYPE_USB3_A"
+                                                register "use_custom_pld" = "true"
+                                                register "custom_pld" = "ACPI_PLD_TYPE_A(RIGHT, LEFT, ACPI_PLD_GROUP(4, 1))"
+						device ref usb3_port2 on
+							probe DB_USB DB_1A
+							probe DB_USB DB_1C_1A
+						end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB3 WWAN""
+						register "type" = "UPC_TYPE_INTERNAL"
+						device ref usb3_port2 on
+							probe DB_USB DB_1C_LTE
+							probe DB_USB DB_HDMI_LTE
+						end
+					end
+				end
+			end
+		end
+	end
 end
diff --git a/src/mainboard/google/brya/variants/guren/ramstage.c b/src/mainboard/google/brya/variants/guren/ramstage.c
new file mode 100644
index 0000000000..6d63eaa8f7
--- /dev/null
+++ b/src/mainboard/google/brya/variants/guren/ramstage.c
@@ -0,0 +1,9 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <soc/ramstage.h>
+
+void mainboard_silicon_init_params(FSP_S_CONFIG *params)
+{
+	params->VccInAuxImonIccImax = 100; // 25 * 4 for ADL-N
+	printk(BIOS_INFO, "Override VccInAuxImonIccImax = %d\n", params->VccInAuxImonIccImax);
+}
diff --git a/src/mainboard/google/brya/variants/guren/variant.c b/src/mainboard/google/brya/variants/guren/variant.c
new file mode 100644
index 0000000000..ff71b6415e
--- /dev/null
+++ b/src/mainboard/google/brya/variants/guren/variant.c
@@ -0,0 +1,19 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <baseboard/variants.h>
+#include <chip.h>
+#include <fw_config.h>
+#include <sar.h>
+
+const char *get_wifi_sar_cbfs_filename(void)
+{
+	return get_wifi_sar_fw_config_filename(FW_CONFIG_FIELD(WIFI_SAR_ID));
+}
+
+void variant_update_soc_chip_config(struct soc_intel_alderlake_config *config)
+{
+	if (fw_config_probe(FW_CONFIG(DB_USB, DB_HDMI_LTE))) {
+		printk(BIOS_INFO, "Enable DDI PORT 2 for HPD and DDC.\n");
+		config->ddi_ports_config[DDI_PORT_2] = DDI_ENABLE_HPD | DDI_ENABLE_DDC;
+	}
+}

From f7ca6600adbeb8a31c07d05b24940958c91cce38 Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Thu, 27 Feb 2025 19:41:29 +0000
Subject: [PATCH 0209/3886] mb/starlabs/starbook/mtl: Set the MMIO Size to 3GiB

This is required when using 96GB of memory.

Change-Id: I3a2a3e737eeb9282a4edf09eb0a24019ceeb016e
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86623
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/starlabs/starbook/variants/mtl/romstage.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/src/mainboard/starlabs/starbook/variants/mtl/romstage.c b/src/mainboard/starlabs/starbook/variants/mtl/romstage.c
index 7d9b9ae4fd..addcae5915 100644
--- a/src/mainboard/starlabs/starbook/variants/mtl/romstage.c
+++ b/src/mainboard/starlabs/starbook/variants/mtl/romstage.c
@@ -44,4 +44,5 @@ void mainboard_memory_init_params(FSPM_UPD *mupd)
 		mupd->FspmConfig.PcieRpEnableMask &= ~(1 << 8);
 
 	mupd->FspmConfig.PchHdaSubSystemIds = 0x70381e50;
+	mupd->FspmConfig.MmioSize = 0xb00;
 };

From f2d91575ac003c902968ef2c214dac8b00f06e61 Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Thu, 13 Feb 2025 09:21:58 +0000
Subject: [PATCH 0210/3886] drivers/wifi/generic: Add Methods to control CNVi
 enable GPIO

Add two new methods, CNVS and CNVC, that can check and control
the enable GPIO for a CNVi module.

These will be used by the common code for WiFi SW RF Kill (Low
Power Mode).

Change-Id: I09d0011ede6f739511a61daf2f1b317f6500a343
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86402
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
---
 src/drivers/wifi/generic/acpi.c | 60 +++++++++++++++++++++++++++++++++
 src/drivers/wifi/generic/chip.h | 10 ++++++
 2 files changed, 70 insertions(+)

diff --git a/src/drivers/wifi/generic/acpi.c b/src/drivers/wifi/generic/acpi.c
index 7820987eca..8cab106d36 100644
--- a/src/drivers/wifi/generic/acpi.c
+++ b/src/drivers/wifi/generic/acpi.c
@@ -1181,6 +1181,60 @@ const char *wifi_pcie_acpi_name(const struct device *dev)
 	return wifi_acpi_name;
 }
 
+#if CONFIG(SOC_INTEL_COMMON_BLOCK_CNVI)
+static void write_cnvi_control(const struct acpi_gpio *gpio)
+{
+
+	acpigen_write_scope("\\_SB.PCI0");
+
+/*
+ *	CNVi Status
+ *
+ *	Method (CNVS, 0)
+ *	{
+ *		Local0 = \_SB.PCI0.GTXS (gpio)
+ *		Return (Local0)
+ *	}
+ */
+	acpigen_write_method("CNVS", 0);
+	{
+		acpigen_get_tx_gpio(gpio);
+		acpigen_write_return_op(LOCAL0_OP);
+	}
+	acpigen_pop_len();
+/*
+ *	CNVi Control
+ *
+ *	Method (CNVC, 1, NotSerialized)
+ *	{
+ *		If ((Arg0 == One))
+ *		{
+ *			\_SB.PCI0.STXS (gpio)
+ *		}
+ *		Else
+ *		{
+ *			\_SB.PCI0.CTXS (gpio)
+ *		}
+ *	}
+ */
+	acpigen_write_method("CNVC", 1);
+	{
+		acpigen_write_if_lequal_op_int(ARG0_OP, 1);
+		{
+			acpigen_enable_tx_gpio(gpio);
+		}
+		acpigen_write_else();
+		{
+			acpigen_disable_tx_gpio(gpio);
+		}
+		acpigen_pop_len();
+	}
+	acpigen_pop_len();
+
+	acpigen_write_scope_end();
+}
+#endif
+
 void wifi_cnvi_fill_ssdt(const struct device *dev)
 {
 	const char *path;
@@ -1192,4 +1246,10 @@ void wifi_cnvi_fill_ssdt(const struct device *dev)
 		return;
 
 	wifi_ssdt_write_properties(dev, path);
+
+#if CONFIG(SOC_INTEL_COMMON_BLOCK_CNVI)
+	const struct drivers_wifi_generic_config *config = dev->chip_info;
+	if (config->cnvi_enable_gpio.pin_count)
+		write_cnvi_control(&config->cnvi_enable_gpio);
+#endif
 }
diff --git a/src/drivers/wifi/generic/chip.h b/src/drivers/wifi/generic/chip.h
index 302dd144ef..f6a68e2068 100644
--- a/src/drivers/wifi/generic/chip.h
+++ b/src/drivers/wifi/generic/chip.h
@@ -3,6 +3,8 @@
 #ifndef _WIFI_GENERIC_H_
 #define _WIFI_GENERIC_H_
 
+#include <acpi/acpi_device.h>
+
 /**
  * struct drivers_wifi_generic_config - Data structure to contain generic wifi config
  * @wake: Wake pin for ACPI _PRW
@@ -20,6 +22,14 @@ struct drivers_wifi_generic_config {
 	 */
 	bool enable_cnvi_ddr_rfim;
 
+#if CONFIG(SOC_INTEL_COMMON_BLOCK_CNVI)
+	/*
+	 * Enable GPIO for CNVi that will be used for WiFi SW RF Kill (Low
+	 * Power Mode).
+	 */
+	struct acpi_gpio cnvi_enable_gpio;
+#endif
+
 	/* Pointer to the Bluetooth companion device */
 	DEVTREE_CONST struct device *bluetooth_companion;
 };

From def337aa7ec6fb1d4c4f668fa5884cf17cb45efb Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Thu, 13 Feb 2025 09:27:19 +0000
Subject: [PATCH 0211/3886] soc/intel/common: Add support for WiFi SW RF Kill
 on CNVi

Hook CNVC and CNVS Methods into the power resource for the CNVi
which is provided via the `wifi/generic` driver to allow for WiFi
SW RF Kill (low power mode) support.

Add corresponding _PS3 and _PS0 Methods, change the power resource
to S0 from S5, and rename the power resource from WRST to CNVP for
better relevance.

Test=boot `starlabs/starlite_adl`, disconnect wireless and verify
with inteltool that the WIFI_RF_KILL GPIO is asserted.

Change-Id: I22292ad97c439e50fe5d7a6b79f77847e71ca62c
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86403
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
---
 src/soc/intel/common/block/cnvi/cnvi.c | 119 ++++++++++++++++++++-----
 1 file changed, 98 insertions(+), 21 deletions(-)

diff --git a/src/soc/intel/common/block/cnvi/cnvi.c b/src/soc/intel/common/block/cnvi/cnvi.c
index a4263af646..e0a9566b1f 100644
--- a/src/soc/intel/common/block/cnvi/cnvi.c
+++ b/src/soc/intel/common/block/cnvi/cnvi.c
@@ -92,17 +92,30 @@ static void cnvw_fill_ssdt(const struct device *dev)
 	acpigen_write_name_integer("RSTT", 0);
 
 /*
- *	PowerResource(WRST, 5, 0)
+ *	PowerResource(CNVP, 0, 0)
  *	{
  *		Method(_STA)
  *		{
- *			Return (0x01)
+ *			If (CondRefOf (\_SB.PCI0.CNVS)) {
+ *				Local0 = \_SB.PCI0.CNVS()
+ *				Return (Local0)
+ *			}
+ *			Else
+ *			{
+ *				Return (0x01)
+ *			}
  *		}
  *		Method(_ON, 0)
  *		{
+ *			If (CondRefOf (\_SB.PCI0.CNVC)) {
+ *				\_SB.PCI0.CNVS(1)
+ *			}
  *		}
  *		Method(_OFF, 0)
  *		{
+ *			If (CondRefOf (\_SB.PCI0.CNVC)) {
+ *				\_SB.PCI0.CNVS(0)
+ *			}
  *		}
  *		Method(_RST, 0, NotSerialized)
  *		{
@@ -150,18 +163,46 @@ static void cnvw_fill_ssdt(const struct device *dev)
  *	}
  *
  */
-	acpigen_write_power_res("WRST", 5, 0, NULL, 0);
+	acpigen_write_power_res("CNVP", 0, 0, NULL, 0);
 	{
 		acpigen_write_method("_STA", 0);
 		{
-			acpigen_write_return_integer(1);
+			acpigen_write_if_cond_ref_of("\\_SB.PCI0.CNVS");
+			{
+				acpigen_write_store();
+				acpigen_emit_namestring("\\_SB.PCI0.CNVS");
+				acpigen_emit_byte(LOCAL0_OP);
+
+				acpigen_write_return_op(LOCAL0_OP);
+			}
+			acpigen_write_else();
+			{
+				acpigen_write_return_integer(1);
+			}
+			acpigen_pop_len();
 		}
 		acpigen_pop_len();
 
 		acpigen_write_method("_ON", 0);
+		{
+			acpigen_write_if_cond_ref_of("\\_SB.PCI0.CNVC");
+			{
+				acpigen_emit_namestring("\\_SB.PCI0.CNVC");
+				acpigen_emit_byte(1);
+			}
+			acpigen_pop_len();
+		}
 		acpigen_pop_len();
 
 		acpigen_write_method("_OFF", 0);
+		{
+			acpigen_write_if_cond_ref_of("\\_SB.PCI0.CNVC");
+			{
+				acpigen_emit_namestring("\\_SB.PCI0.CNVC");
+				acpigen_emit_byte(0);
+			}
+			acpigen_pop_len();
+		}
 		acpigen_pop_len();
 
 		acpigen_write_method("_RST", 0);
@@ -266,13 +307,64 @@ static void cnvw_fill_ssdt(const struct device *dev)
 /*
  *	Name (_PRR, Package (0x01)
  *	{
- *		WRST
+ *		CNVP
  *	})
  */
 	acpigen_write_name("_PRR");
 	{
 		acpigen_write_package(1);
-		acpigen_emit_namestring("WRST");
+		acpigen_emit_namestring("CNVP");
+	}
+	acpigen_pop_len();
+
+/*
+ *	Name (_PR0, Package (0x01)
+ *	{
+ *		CNVP
+ *	})
+ */
+	acpigen_write_name("_PR0");
+	{
+		acpigen_write_package(1);
+		acpigen_emit_namestring("CNVP");
+	}
+	acpigen_pop_len();
+
+/*
+ *	Method (_PS0, 0, NotSerialized)
+ *	{
+ *		If (CondRefOf (\_SB.PCI0.CNVC)) {
+ *			\_SB.PCI0.CNVS(1)
+ *		}
+ *	}
+ */
+	acpigen_write_method("_PS0", 0);
+	{
+		acpigen_write_if_cond_ref_of("\\_SB.PCI0.CNVC");
+		{
+			acpigen_emit_namestring("\\_SB.PCI0.CNVC");
+			acpigen_emit_byte(1);
+		}
+		acpigen_pop_len();
+	}
+	acpigen_pop_len();
+
+/*
+ *	Method (_PS3, 0, NotSerialized)
+ *	{
+ *		If (CondRefOf (\_SB.PCI0.CNVC)) {
+ *			\_SB.PCI0.CNVS(0)
+ *		}
+ *	}
+ */
+	acpigen_write_method("_PS3", 0);
+	{
+		acpigen_write_if_cond_ref_of("\\_SB.PCI0.CNVC");
+		{
+			acpigen_emit_namestring("\\_SB.PCI0.CNVC");
+			acpigen_emit_byte(0);
+		}
+		acpigen_pop_len();
 	}
 	acpigen_pop_len();
 
@@ -305,21 +397,6 @@ static void cnvw_fill_ssdt(const struct device *dev)
 	}
 	acpigen_pop_len();
 
-/*
- *	Method (_PS0, 0, Serialized)
- *	{
- *	}
- *
- *	Method (_PS3, 0, Serialized)
- *	{
- *	}
- */
-	acpigen_write_method_serialized("_PS0", 0);
-	acpigen_pop_len();
-
-	acpigen_write_method_serialized("_PS3", 0);
-	acpigen_pop_len();
-
 /*
  *	Method (CFLR, 0, NotSerialized)
  *	{

From 0476770659485ad42a91a1975eac15fb7bee559a Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Sat, 15 Feb 2025 19:45:22 +0000
Subject: [PATCH 0212/3886] soc/intel/cnvi: Deref BTRK as it might not exist

Check for the existence of BTRK method before attempting to
call it, as coreboot doesn't enforce its creation.

Change-Id: Ibb0dace635c6a014ce65ae3d1c96a92ff991ce5b
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86450
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
---
 src/soc/intel/common/block/cnvi/cnvi.c | 26 ++++++++++++++++----------
 1 file changed, 16 insertions(+), 10 deletions(-)

diff --git a/src/soc/intel/common/block/cnvi/cnvi.c b/src/soc/intel/common/block/cnvi/cnvi.c
index e0a9566b1f..f0821973f2 100644
--- a/src/soc/intel/common/block/cnvi/cnvi.c
+++ b/src/soc/intel/common/block/cnvi/cnvi.c
@@ -129,11 +129,13 @@ static void cnvw_fill_ssdt(const struct device *dev)
  *					If (((PCRR (CNVI_SIDEBAND_ID, CNVI_ABORT_PLDR) & CNVI_ABORT_REQUEST) == Zero))
  *					{
  *						Local2 = Zero
- *						If ((\_SB.PCI0.GBTR() == One))
- *						{
- *							\_SB.PCI0.BTRK (Zero)
- *							Sleep (105)
- *							Local2 = One
+ *						If (CondRefOf (\_SB.PCI0.GBTR)) {
+ *							If ((\_SB.PCI0.GBTR() == One))
+ *							{
+ *								\_SB.PCI0.BTRK (Zero)
+ *								Sleep (105)
+ *								Local2 = One
+ *							}
  *						}
  *						PCRO (CNVI_SIDEBAND_ID, CNVI_ABORT_PLDR, CNVI_ABORT_REQUEST | CNVI_ABORT_ENABLE)
  *						Sleep (10)
@@ -233,14 +235,18 @@ static void cnvw_fill_ssdt(const struct device *dev)
 					acpigen_write_if_lequal_op_int(LOCAL0_OP, 0);
 					{
 						acpigen_write_store_int_to_op(0, LOCAL2_OP);
-						acpigen_write_if_lequal_namestr_int("\\_SB.PCI0.GBTR", 1);
+						acpigen_write_if_cond_ref_of("\\_SB.PCI0.GBTR");
 						{
-							acpigen_emit_namestring("\\_SB.PCI0.BTRK");
-							acpigen_emit_byte(0);
+							acpigen_write_if_lequal_namestr_int("\\_SB.PCI0.GBTR", 1);
+							{
+								acpigen_emit_namestring("\\_SB.PCI0.BTRK");
+								acpigen_emit_byte(0);
 
-							acpigen_write_sleep(105);
+								acpigen_write_sleep(105);
 
-							acpigen_write_store_ops(1, LOCAL2_OP);
+								acpigen_write_store_ops(1, LOCAL2_OP);
+							}
+							acpigen_pop_len();
 						}
 						acpigen_pop_len();
 

From e4832dce9398525c3f6b08c3cee61531d877541f Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Fri, 14 Feb 2025 20:09:03 +0000
Subject: [PATCH 0213/3886] mb/starlabs/{byte_adl,starlite_adl}: Enable SW RF
 Kill for CNVi

Specify an enable GPIO for CNVi wireless so that the driver will
add support for WiFi SW RF Kill.

Test=boot starlite_adl/byte_adl, and use acpi_call dkms to check
that _OFF and _ON Methods in the power resource successfully
disable the wireless.

Change-Id: Ib172230f2c9e926870e35f040ce1b80628561863
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86428
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
---
 src/mainboard/starlabs/byte_adl/variants/mk_ii/devicetree.cb    | 1 +
 src/mainboard/starlabs/starlite_adl/variants/mk_v/devicetree.cb | 1 +
 2 files changed, 2 insertions(+)

diff --git a/src/mainboard/starlabs/byte_adl/variants/mk_ii/devicetree.cb b/src/mainboard/starlabs/byte_adl/variants/mk_ii/devicetree.cb
index bbedc9657a..df79411fa2 100644
--- a/src/mainboard/starlabs/byte_adl/variants/mk_ii/devicetree.cb
+++ b/src/mainboard/starlabs/byte_adl/variants/mk_ii/devicetree.cb
@@ -133,6 +133,7 @@ chip soc/intel/alderlake
 		device ref cnvi_wifi	on
 			chip drivers/wifi/generic
 				register "add_acpi_dma_property"	= "true"
+				register "cnvi_enable_gpio"		= "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E3)"
 				register "enable_cnvi_ddr_rfim"		= "true"
 				device generic 0 on end
 			end
diff --git a/src/mainboard/starlabs/starlite_adl/variants/mk_v/devicetree.cb b/src/mainboard/starlabs/starlite_adl/variants/mk_v/devicetree.cb
index 5b8bd2c2d0..247c5bcaa7 100644
--- a/src/mainboard/starlabs/starlite_adl/variants/mk_v/devicetree.cb
+++ b/src/mainboard/starlabs/starlite_adl/variants/mk_v/devicetree.cb
@@ -119,6 +119,7 @@ chip soc/intel/alderlake
 		device ref cnvi_wifi	on
 			chip drivers/wifi/generic
 				register "add_acpi_dma_property"	= "true"
+				register "cnvi_enable_gpio"		= "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E3)"
 				register "enable_cnvi_ddr_rfim"		= "true"
 				device generic 0 on end
 			end

From aab800b1a405745ef4216e48df8c8b8ec7b8b67d Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Mon, 17 Feb 2025 16:55:36 +0000
Subject: [PATCH 0214/3886] soc/intel/cnvi: Increase the reset delay to 160ms
 from 105ms

The Intel reference code for Thunder Peak increase the reset delay
to 160ms from 105ms seen on Jefferson Peak, Cyclone Peak and others.

For the sake of 110ms, use 160ms to cover all use cases.

Change-Id: I19c1bf7eeffa340e2564381a184ebfaca89bf364
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86489
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
---
 src/soc/intel/common/block/cnvi/cnvi.c | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/src/soc/intel/common/block/cnvi/cnvi.c b/src/soc/intel/common/block/cnvi/cnvi.c
index f0821973f2..e23ada8d8a 100644
--- a/src/soc/intel/common/block/cnvi/cnvi.c
+++ b/src/soc/intel/common/block/cnvi/cnvi.c
@@ -133,7 +133,7 @@ static void cnvw_fill_ssdt(const struct device *dev)
  *							If ((\_SB.PCI0.GBTR() == One))
  *							{
  *								\_SB.PCI0.BTRK (Zero)
- *								Sleep (105)
+ *								Sleep (160
  *								Local2 = One
  *							}
  *						}
@@ -146,7 +146,7 @@ static void cnvw_fill_ssdt(const struct device *dev)
  *							If ((Local2 == One))
  *							{
  *								\_SB.PCI0.BTRK (One)
- *								Sleep (105)
+ *								Sleep (160)
  *							}
  *						}
  *						Else
@@ -242,7 +242,7 @@ static void cnvw_fill_ssdt(const struct device *dev)
 								acpigen_emit_namestring("\\_SB.PCI0.BTRK");
 								acpigen_emit_byte(0);
 
-								acpigen_write_sleep(105);
+								acpigen_write_sleep(160);
 
 								acpigen_write_store_ops(1, LOCAL2_OP);
 							}
@@ -283,7 +283,7 @@ static void cnvw_fill_ssdt(const struct device *dev)
 								{
 									acpigen_emit_namestring("\\_SB.PCI0.BTRK");
 									acpigen_emit_byte(1);
-									acpigen_write_sleep(105);
+									acpigen_write_sleep(160);
 								}
 								acpigen_pop_len();
 							}

From 9f351c76a343942b1f07c7ad577360c3db48c665 Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Thu, 13 Feb 2025 09:13:06 +0000
Subject: [PATCH 0215/3886] drivers/usb/acpi: Account for GPIO polarity

Whilst the GPIO's used for Intel Bluetooth should always be consistent
as to whether they're active high or active low, adjust the driver to
pass the GPIO as a pointer, so that it can correctly account for
polarity.

Change-Id: Ib481d49d536b702fef149af882209501c61de6da
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86400
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
---
 src/drivers/usb/acpi/chip.h            |  9 ++---
 src/drivers/usb/acpi/intel_bluetooth.c | 47 ++++++++++++++++----------
 src/drivers/usb/acpi/usb_acpi.c        |  8 ++---
 3 files changed, 38 insertions(+), 26 deletions(-)

diff --git a/src/drivers/usb/acpi/chip.h b/src/drivers/usb/acpi/chip.h
index f5edba4f58..434d856d12 100644
--- a/src/drivers/usb/acpi/chip.h
+++ b/src/drivers/usb/acpi/chip.h
@@ -88,10 +88,11 @@ struct drivers_usb_acpi_config {
 bool usb_acpi_get_pld(const struct device *usb_device, struct acpi_pld *pld);
 
 /* Intel Bluetooth */
-void acpi_device_intel_bt(unsigned int reset_gpio,
-			  unsigned int enable_gpio,
+void acpi_device_intel_bt(const struct acpi_gpio *enable_gpio,
+			  const struct acpi_gpio *reset_gpio,
 			  bool audio_offload);
-void acpi_device_intel_bt_common(unsigned int enable_gpio,
-				 unsigned int reset_gpio);
+
+void acpi_device_intel_bt_common(const struct acpi_gpio *enable_gpio,
+				 const struct acpi_gpio *reset_gpio);
 
 #endif /* __USB_ACPI_CHIP_H__ */
diff --git a/src/drivers/usb/acpi/intel_bluetooth.c b/src/drivers/usb/acpi/intel_bluetooth.c
index a979b42ebf..151930fc4a 100644
--- a/src/drivers/usb/acpi/intel_bluetooth.c
+++ b/src/drivers/usb/acpi/intel_bluetooth.c
@@ -44,7 +44,9 @@ static void not_supported(void *arg)
 void (*reset_supported[])(void *) = { check_reset_delay, set_reset_delay };
 void (*reset_unsupported[])(void *) = { not_supported };
 
-void acpi_device_intel_bt(unsigned int reset_gpio, unsigned int enable_gpio, bool audio_offload)
+void acpi_device_intel_bt(const struct acpi_gpio *enable_gpio,
+			  const struct acpi_gpio *reset_gpio,
+			  bool audio_offload)
 {
 /*
  *	Name (RDLY, 0x69)
@@ -91,8 +93,10 @@ void acpi_device_intel_bt(unsigned int reset_gpio, unsigned int enable_gpio, boo
 
 	struct dsm_uuid uuid_callbacks[] = {
 		DSM_UUID("aa10f4e0-81ac-4233-abf6-3b2ac50e28d9",
-			reset_gpio ? reset_supported : reset_unsupported,
-			reset_gpio ? ARRAY_SIZE(reset_supported) : ARRAY_SIZE(reset_unsupported),
+			reset_gpio->pin_count ?
+				reset_supported : reset_unsupported,
+			reset_gpio->pin_count ?
+				ARRAY_SIZE(reset_supported) : ARRAY_SIZE(reset_unsupported),
 			NULL),
 	};
 
@@ -130,7 +134,7 @@ void acpi_device_intel_bt(unsigned int reset_gpio, unsigned int enable_gpio, boo
 	{
 		acpigen_write_method("_STA", 0);
 		{
-			if (enable_gpio) {
+			if (enable_gpio->pin_count) {
 				acpigen_write_store();
 				acpigen_emit_namestring("\\_SB.PCI0.GBTE");
 				acpigen_emit_byte(LOCAL0_OP);
@@ -144,7 +148,7 @@ void acpi_device_intel_bt(unsigned int reset_gpio, unsigned int enable_gpio, boo
 
 		acpigen_write_method("_ON", 0);
 		{
-			if (enable_gpio) {
+			if (enable_gpio->pin_count) {
 				acpigen_emit_namestring("\\_SB.PCI0.SBTE");
 				acpigen_emit_byte(1);
 			}
@@ -153,7 +157,7 @@ void acpi_device_intel_bt(unsigned int reset_gpio, unsigned int enable_gpio, boo
 
 		acpigen_write_method("_OFF", 0);
 		{
-			if (enable_gpio) {
+			if (enable_gpio->pin_count) {
 				acpigen_emit_namestring("\\_SB.PCI0.SBTE");
 				acpigen_emit_byte(0);
 			}
@@ -162,7 +166,7 @@ void acpi_device_intel_bt(unsigned int reset_gpio, unsigned int enable_gpio, boo
 
 		acpigen_write_method("_RST", 0);
 		{
-			if (reset_gpio) {
+			if (reset_gpio->pin_count) {
 				acpigen_write_store();
 				acpigen_write_acquire("\\_SB.PCI0.CNMT", 1000);
 				acpigen_emit_byte(LOCAL0_OP);
@@ -258,7 +262,8 @@ void acpi_device_intel_bt(unsigned int reset_gpio, unsigned int enable_gpio, boo
 	acpigen_pop_len();
 }
 
-void acpi_device_intel_bt_common(unsigned int enable_gpio, unsigned int reset_gpio)
+void acpi_device_intel_bt_common(const struct acpi_gpio *enable_gpio,
+				 const struct acpi_gpio *reset_gpio)
 {
 	acpigen_write_scope("\\_SB.PCI0");
 /*
@@ -279,14 +284,14 @@ void acpi_device_intel_bt_common(unsigned int enable_gpio, unsigned int reset_gp
  */
 	acpigen_write_method("SBTE", 1);
 	{
-		if (enable_gpio) {
+		if (enable_gpio->pin_count) {
 			acpigen_write_if_lequal_op_int(ARG0_OP, 1);
 			{
-				acpigen_soc_set_tx_gpio(enable_gpio);
+				acpigen_enable_tx_gpio(enable_gpio);
 			}
 			acpigen_write_else();
 			{
-				acpigen_soc_clear_tx_gpio(enable_gpio);
+				acpigen_disable_tx_gpio(enable_gpio);
 			}
 			acpigen_pop_len();
 		}
@@ -301,8 +306,8 @@ void acpi_device_intel_bt_common(unsigned int enable_gpio, unsigned int reset_gp
  */
 	acpigen_write_method("GBTE", 0);
 	{
-		if (enable_gpio) {
-			acpigen_soc_get_tx_gpio(enable_gpio);
+		if (enable_gpio->pin_count) {
+			acpigen_get_tx_gpio(enable_gpio);
 			acpigen_write_return_op(LOCAL0_OP);
 		} else {
 			acpigen_write_return_integer(0);
@@ -325,11 +330,13 @@ void acpi_device_intel_bt_common(unsigned int enable_gpio, unsigned int reset_gp
 	{
 		acpigen_write_if_lequal_op_int(ARG0_OP, 1);
 		{
-			acpigen_soc_set_tx_gpio(reset_gpio);
+			/* De-assert reset */
+			acpigen_disable_tx_gpio(reset_gpio);
 		}
 		acpigen_write_else();
 		{
-			acpigen_soc_clear_tx_gpio(reset_gpio);
+			/* Assert Reset */
+			acpigen_enable_tx_gpio(reset_gpio);
 		}
 		acpigen_pop_len();
 	}
@@ -338,13 +345,17 @@ void acpi_device_intel_bt_common(unsigned int enable_gpio, unsigned int reset_gp
 /*
  *	Method (GBTR, 0, NotSerialized)
  *	{
- *		 Return (GTXS (reset_gpio))
+ *		Local0 = GTXS (reset_gpio)
+ *		Local0 ^= One
+ *		Return (Local0)
  *	}
  */
 	acpigen_write_method("GBTR", 0);
 	{
-		if (reset_gpio) {
-			acpigen_soc_get_tx_gpio(reset_gpio);
+		if (reset_gpio->pin_count) {
+			/* Return 1 if not in reset */
+			acpigen_get_tx_gpio(reset_gpio);
+			acpigen_write_xor(LOCAL0_OP, 1, LOCAL0_OP);
 			acpigen_write_return_op(LOCAL0_OP);
 		} else {
 			acpigen_write_return_op(0);
diff --git a/src/drivers/usb/acpi/usb_acpi.c b/src/drivers/usb/acpi/usb_acpi.c
index a920fa1e58..8173c06960 100644
--- a/src/drivers/usb/acpi/usb_acpi.c
+++ b/src/drivers/usb/acpi/usb_acpi.c
@@ -111,8 +111,8 @@ static void usb_acpi_fill_ssdt_generator(const struct device *dev)
 	}
 
 	if (config->is_intel_bluetooth)
-		acpi_device_intel_bt(config->reset_gpio.pins[0],
-				     config->enable_gpio.pins[0],
+		acpi_device_intel_bt(&config->enable_gpio,
+				     &config->reset_gpio,
 				     config->cnvi_bt_audio_offload);
 
 	acpigen_pop_len();
@@ -122,8 +122,8 @@ static void usb_acpi_fill_ssdt_generator(const struct device *dev)
 	 * other code to access it i.e. CNVi driver.
 	 */
 	if (config->is_intel_bluetooth)
-		acpi_device_intel_bt_common(config->enable_gpio.pins[0],
-					    config->reset_gpio.pins[0]);
+		acpi_device_intel_bt_common(&config->enable_gpio,
+					    &config->reset_gpio);
 
 	printk(BIOS_INFO, "%s: %s at %s\n", path,
 	       config->desc ? : dev->chip_ops->name, dev_path(dev));

From 970d983083bd0a370357c6fe5d44ac6c7be8c84c Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Thu, 13 Feb 2025 09:14:47 +0000
Subject: [PATCH 0216/3886] drivers/usb/intel_bluetooth: Guard BTRK if no GPIO
 passed

Don't attempt any GPIO operations of there isn't a reset
GPIO specified.

Change-Id: I9c97963e61f790f2d9c55d8ec1a384a5779782b4
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86401
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/drivers/usb/acpi/intel_bluetooth.c | 22 ++++++++++++----------
 1 file changed, 12 insertions(+), 10 deletions(-)

diff --git a/src/drivers/usb/acpi/intel_bluetooth.c b/src/drivers/usb/acpi/intel_bluetooth.c
index 151930fc4a..6307dcb35d 100644
--- a/src/drivers/usb/acpi/intel_bluetooth.c
+++ b/src/drivers/usb/acpi/intel_bluetooth.c
@@ -328,17 +328,19 @@ void acpi_device_intel_bt_common(const struct acpi_gpio *enable_gpio,
  */
 	acpigen_write_method("BTRK", 1);
 	{
-		acpigen_write_if_lequal_op_int(ARG0_OP, 1);
-		{
-			/* De-assert reset */
-			acpigen_disable_tx_gpio(reset_gpio);
+		if (reset_gpio->pin_count) {
+			acpigen_write_if_lequal_op_int(ARG0_OP, 1);
+			{
+				/* De-assert reset */
+				acpigen_disable_tx_gpio(reset_gpio);
+			}
+			acpigen_write_else();
+			{
+				/* Assert Reset */
+				acpigen_enable_tx_gpio(reset_gpio);
+			}
+			acpigen_pop_len();
 		}
-		acpigen_write_else();
-		{
-			/* Assert Reset */
-			acpigen_enable_tx_gpio(reset_gpio);
-		}
-		acpigen_pop_len();
 	}
 	acpigen_pop_len();
 

From c166b6d95c0eff3d922fab682866b7a41520bb0e Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Tue, 25 Feb 2025 09:52:08 +0000
Subject: [PATCH 0217/3886] drivers/usb/intel-bluetooth: Remove the _PR3 Object

_PR3 should return resources required for the device to be in D3Hot
for which the Intel Bluetooth needs none, so remove it.

Change-Id: I65f206899affd46d791c2ba39235a1af320395d2
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86595
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/drivers/usb/acpi/intel_bluetooth.c | 13 -------------
 1 file changed, 13 deletions(-)

diff --git a/src/drivers/usb/acpi/intel_bluetooth.c b/src/drivers/usb/acpi/intel_bluetooth.c
index 6307dcb35d..5ed42c8f2f 100644
--- a/src/drivers/usb/acpi/intel_bluetooth.c
+++ b/src/drivers/usb/acpi/intel_bluetooth.c
@@ -220,19 +220,6 @@ void acpi_device_intel_bt(const struct acpi_gpio *enable_gpio,
 	}
 	acpigen_pop_len();
 
-/*
- *	Name (_PR3, Package (0x01)
- *	{
- *		BTRT
- *	})
- */
-	acpigen_write_name("_PR3");
-	{
-		acpigen_write_package(1);
-		acpigen_emit_namestring("BTRT");
-	}
-	acpigen_pop_len();
-
 /*
  *	Method (AOLD, 0, NotSerialized)
  *	{

From b6c2d01d011462206ca29c532dbbcc2b5afcf8dd Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Tue, 18 Feb 2025 21:28:00 +0000
Subject: [PATCH 0218/3886] driver/usb/intel_bluetooth: Add PS0 and PS3 methods

Add PS0 and PS3 methods that return the Bluetooth power
resource. This allows the OS to turn on or off the device.

This fixes and issue where the Bluetooth reported a power
failure in device manager.

Change-Id: I0e37fc0369b1dc2b166f851daa183b145a09eb32
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86507
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/drivers/usb/acpi/intel_bluetooth.c | 26 ++++++++++++++++++++++++++
 1 file changed, 26 insertions(+)

diff --git a/src/drivers/usb/acpi/intel_bluetooth.c b/src/drivers/usb/acpi/intel_bluetooth.c
index 5ed42c8f2f..97fb4816f8 100644
--- a/src/drivers/usb/acpi/intel_bluetooth.c
+++ b/src/drivers/usb/acpi/intel_bluetooth.c
@@ -220,6 +220,32 @@ void acpi_device_intel_bt(const struct acpi_gpio *enable_gpio,
 	}
 	acpigen_pop_len();
 
+/*
+ *	Method (_PS0, 0, NotSerialized)
+ *	{
+ *		\_SB.PCI0.SBTE(1)
+ *	}
+ */
+	acpigen_write_method("_PS0", 0);
+	{
+		acpigen_emit_namestring("\\_SB.PCI0.SBTE");
+		acpigen_emit_byte(1);
+	}
+	acpigen_pop_len();
+
+/*
+ *	Name (_PS3, Package (0x01)
+ *	{
+ *		\_SB.PCI0.SBTE(0)
+ *	}
+ */
+	acpigen_write_method("_PS3", 0);
+	{
+		acpigen_emit_namestring("\\_SB.PCI0.SBTE");
+		acpigen_emit_byte(0);
+	}
+	acpigen_pop_len();
+
 /*
  *	Method (AOLD, 0, NotSerialized)
  *	{

From 1633ae8378e1afeee2061f6885ddeb8d47dc9981 Mon Sep 17 00:00:00 2001
From: Zhaoqing Jiu <zhaoqing.jiu@mediatek.corp-partner.google.com>
Date: Thu, 20 Feb 2025 15:37:47 +0800
Subject: [PATCH 0219/3886] soc/mediatek/mt8196: Adjust thermal trip point
 parameters

Adjust thermal trip point parameters so the thermal can trigger the
interrupt at the expected trip point.

BRANCH=rauru
BUG=b:389026545
TEST=Boot up and check temperature in coreboot log:
[INFO ]  [LVTS_MSR] ts0 msr_all=141d0, msr_temp=16848, temp=41086
[INFO ]  lvts_tscpu_thermal_read_tc_temp order 0 ts_name 0 temp 41086 rg_temp 41073(42059)
[INFO ]  [LVTS_MSR] ts1 msr_all=141e3, msr_temp=16867, temp=41540
[INFO ]  lvts_tscpu_thermal_read_tc_temp order 1 ts_name 1 temp 41540 rg_temp 41526(42523)
[INFO ]  [LVTS_MSR] ts2 msr_all=14199, msr_temp=16793, temp=39772[0m
[INFO ]  lvts_tscpu_thermal_read_tc_temp order 2 ts_name 2 temp 39772 rg_temp 39760(40715)
[INFO ]  [LVTS_MSR] ts3 msr_all=141c2, msr_temp=16834, temp=40751
[INFO ]  lvts_tscpu_thermal_read_tc_temp order 3 ts_name 3 temp 40751 rg_temp 40739(41717)
[INFO ]  [LVTS_MSR] ts4 msr_all=141d0, msr_temp=16848, temp=41086
[INFO ]  lvts_tscpu_thermal_read_tc_temp order 0 ts_name 4 temp 41086 rg_temp 41073(42059)
[INFO ]  [LVTS_MSR] ts5 msr_all=141b3, msr_temp=16819, temp=40393
[INFO ]  lvts_tscpu_thermal_read_tc_temp order 1 ts_name 5 temp 40393 rg_temp 40380(41350)
[INFO ]  [LVTS_MSR] ts6 msr_all=14194, msr_temp=16788, temp=39652
[INFO ]  lvts_tscpu_thermal_read_tc_temp order 2 ts_name 6 temp 39652 rg_temp 39641(40593)
[INFO ]  [LVTS_MSR] ts7 msr_all=14186, msr_temp=16774, temp=39318
[INFO ]  lvts_tscpu_thermal_read_tc_temp order 3 ts_name 7 temp 39318 rg_temp 39307(40251)

Signed-off-by: Zhaoqing Jiu <zhaoqing.jiu@mediatek.corp-partner.google.com>
Change-Id: Ia7361edd7f75b82fff4241ec94488ed1ef07346f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86552
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
---
 src/soc/mediatek/mt8196/include/soc/thermal_internal.h | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/soc/mediatek/mt8196/include/soc/thermal_internal.h b/src/soc/mediatek/mt8196/include/soc/thermal_internal.h
index b5841178c2..55c300d7e1 100644
--- a/src/soc/mediatek/mt8196/include/soc/thermal_internal.h
+++ b/src/soc/mediatek/mt8196/include/soc/thermal_internal.h
@@ -171,8 +171,8 @@ check_member(mtk_thermal_controller_regs, lvtsspare, 0x0f0);
 #define AP_RST_SET			(INFRACFG_AO_SEC_BASE + 0xf30)
 #define AP_RST_CLR			(INFRACFG_AO_SEC_BASE + 0xf34)
 
-#define LVTS_COF_T_SLP_GLD		358830
-#define LVTS_COF_COUNT_R_GLD		34389
+#define LVTS_COF_T_SLP_GLD		391460
+#define LVTS_COF_COUNT_R_GLD		34412
 #define LVTS_COF_T_CONST_OFS		0
 
 #define DEFAULT_EFUSE_GOLDEN_TEMP	60

From 3ef23c9a881fee5a6a639eabfb85d98b4d7776d5 Mon Sep 17 00:00:00 2001
From: Cliff Huang <cliff.huang@intel.com>
Date: Thu, 13 Feb 2025 22:58:54 -0800
Subject: [PATCH 0220/3886] soc/intel/common/gpio: Add macro for interrupt GPI
 with driver mode

Adds PAD_CFG_GPI_APIC_DRIVER macros to configure interrupt pad with
driver mode. This is needed when a PAD is configured as an interrupt
such that the corresponding GPI_IS status bit can be updated by the
host controller hardware.

BUG=none
TEST=Check a GPIO pad that is used as interrupt via GpioInt in the ACPI
device _CRS method and check the interrupt has been assigned in
/proc/interrupts.

Signed-off-by: Cliff Huang <cliff.huang@intel.com>
Change-Id: Ibc1ed3089c24302bc7eb02318714b8ec464fad01
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86414
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Reviewed-by: Kyoung Il Kim <kyoung.il.kim@intel.com>
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 .../intel/common/block/include/intelblocks/gpio_defs.h    | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/src/soc/intel/common/block/include/intelblocks/gpio_defs.h b/src/soc/intel/common/block/include/intelblocks/gpio_defs.h
index f0ff08c492..bcf8e73f7e 100644
--- a/src/soc/intel/common/block/include/intelblocks/gpio_defs.h
+++ b/src/soc/intel/common/block/include/intelblocks/gpio_defs.h
@@ -436,6 +436,14 @@
 		PAD_IRQ_CFG(IOAPIC, trig, inv), PAD_PULL(pull) |		\
 		PAD_IOSSTATE(TxDRxE))
 
+/* General purpose input, routed to APIC, HostOwn  */
+#define PAD_CFG_GPI_APIC_DRIVER(pad, pull, rst, trig, inv)				\
+	_PAD_CFG_STRUCT(pad,							\
+		PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_BUF(TX_DISABLE) |		\
+		PAD_IRQ_CFG(IOAPIC, trig, inv), PAD_PULL(pull) |		\
+		PAD_IOSSTATE(TxDRxE) | \
+		PAD_CFG_OWN_GPIO(DRIVER))
+
 /* General purpose input with lock, routed to APIC */
 #define PAD_CFG_GPI_APIC_LOCK(pad, pull, trig, inv, lock_action)		\
 	_PAD_CFG_STRUCT_LOCK(pad,						\

From 0ac29ad3ce7340c462d9580aafc6f965a3014137 Mon Sep 17 00:00:00 2001
From: Maximilian Brune <maximilian.brune@9elements.com>
Date: Thu, 12 Sep 2024 17:36:13 -0700
Subject: [PATCH 0221/3886] device/dram/ddr5: Add 7500 MT/s support

Before I got the following error:
[ERROR]  DDR5 speed of 3750 MHz is out of range

tested: glinda based mainboard

Change-Id: I141f63c4fc505a9e16eed132a9a550441f4ad68d
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86543
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
Reviewed-by: Andy Ebrahiem <ahmet.ebrahiem@9elements.com>
Reviewed-by: Marvin Drees <marvin.drees@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Naresh Solanki <naresh.solanki@9elements.com>
---
 src/device/dram/ddr5.c | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/src/device/dram/ddr5.c b/src/device/dram/ddr5.c
index b546abf4d4..90b67f857b 100644
--- a/src/device/dram/ddr5.c
+++ b/src/device/dram/ddr5.c
@@ -21,6 +21,7 @@ enum ddr5_speed_grade {
 	DDR5_5500,
 	DDR5_6000,
 	DDR5_6400,
+	DDR5_7500,
 };
 
 struct ddr5_speed_attr {
@@ -108,6 +109,11 @@ static const struct ddr5_speed_attr ddr5_speeds[] = {
 		.max_clock_mhz = 3200,
 		.reported_mts = 6400
 	},
+	[DDR5_7500] = {
+		.min_clock_mhz = 3201,
+		.max_clock_mhz = 3750,
+		.reported_mts = 7500
+	},
 };
 
 /**

From f1fbcf76479851e61d84a9e888585161c8902cb9 Mon Sep 17 00:00:00 2001
From: John Su <john_su@compal.corp-partner.google.com>
Date: Wed, 19 Feb 2025 23:17:25 +0800
Subject: [PATCH 0222/3886] mb/trulo/var/uldrenite: Fix boot time caused by
 WWAN initialization

The previous approach would increase the delay time by 50 ms. So move
WWAN power sequence to GPIO control to reduce boot time caused by WWAN
initialization. Additionally, add a 150ms delay to T0_OFF_MS before powering off the WWAN. This ensures that the WWAN Power OFF Sequence operates correctly during a reboot.

BUG=b:383212261
BRANCH=firmware-trulo-15217.771.B
TEST=Confirm the measured WWAN power sequence

Change-Id: Ie01019eca7eaa4bbb34dd80aeb65b9b6b08587fd
Signed-off-by: John Su <john_su@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86514
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
---
 .../google/brya/variants/uldrenite/gpio.c     | 10 +++---
 .../variants/uldrenite/include/variant/gpio.h |  1 +
 .../google/brya/variants/uldrenite/variant.c  | 32 -------------------
 src/mainboard/google/brya/wwan_power.asl      |  3 ++
 4 files changed, 10 insertions(+), 36 deletions(-)

diff --git a/src/mainboard/google/brya/variants/uldrenite/gpio.c b/src/mainboard/google/brya/variants/uldrenite/gpio.c
index 3e11b48d0a..e8355d37e8 100644
--- a/src/mainboard/google/brya/variants/uldrenite/gpio.c
+++ b/src/mainboard/google/brya/variants/uldrenite/gpio.c
@@ -232,9 +232,9 @@ static const struct pad_config gpio_table[] = {
 	/* F11 : NC */
 	PAD_NC_LOCK(GPP_F11, NONE, LOCK_CONFIG),
 	/* F12 : NC ==> WWAN_RST_L */
-	PAD_CFG_GPO(GPP_F12, 0, DEEP),
+	PAD_CFG_GPO(GPP_F12, 1, DEEP),
 	/* F13 : NC ==> PLTRST_WWAN# */
-	PAD_CFG_GPO(GPP_F13, 0, DEEP),
+	PAD_CFG_GPO(GPP_F13, 1, DEEP),
 	/* F14 : NC */
 	PAD_NC(GPP_F14, NONE),
 	/* F15 : NC */
@@ -303,7 +303,7 @@ static const struct pad_config gpio_table[] = {
 	/* H22 : NC */
 	PAD_NC(GPP_H22, NONE),
 	/* H23 : LTE_PWR_OFF_EN */
-	PAD_CFG_GPO(GPP_H23, 0, DEEP),
+	PAD_CFG_GPO(GPP_H23, 1, DEEP),
 
 	/* R0  : HDA_BCLK ==> HDA_BIT_CLK */
 	PAD_CFG_NF(GPP_R0, NONE, DEEP, NF1),
@@ -435,7 +435,7 @@ static const struct pad_config early_gpio_table[] = {
 	/* H11 : UART0_TXD ==> UART_SOC_TX_DBG_RX */
 	PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2),
 	/* H23 : LTE_PWR_OFF_EN */
-	PAD_CFG_GPO(GPP_H23, 0, DEEP),
+	PAD_CFG_GPO(GPP_H23, 1, DEEP),
 };
 
 /* Fill romstage gpio configuration */
@@ -445,6 +445,8 @@ static const struct pad_config romstage_gpio_table[] = {
 	PAD_CFG_GPO(GPP_E17, 1, DEEP),
 	/* D15  : GPP_D15 ==> SOC_TS_I2C_RST# */
 	PAD_CFG_GPO(GPP_D15, 0, DEEP),
+	/* F12 : NC ==> WWAN_RST_L */
+	PAD_CFG_GPO(GPP_F12, 1, DEEP),
 };
 
 const struct pad_config *variant_gpio_table(size_t *num)
diff --git a/src/mainboard/google/brya/variants/uldrenite/include/variant/gpio.h b/src/mainboard/google/brya/variants/uldrenite/include/variant/gpio.h
index 612ea2adbb..e7524565d0 100644
--- a/src/mainboard/google/brya/variants/uldrenite/include/variant/gpio.h
+++ b/src/mainboard/google/brya/variants/uldrenite/include/variant/gpio.h
@@ -10,5 +10,6 @@
 #define WWAN_PERST	GPP_F13
 #define T1_OFF_MS	20
 #define T2_OFF_MS	10
+#define T0_OFF_MS	150
 
 #endif
diff --git a/src/mainboard/google/brya/variants/uldrenite/variant.c b/src/mainboard/google/brya/variants/uldrenite/variant.c
index 3620c3a0c8..421799694a 100644
--- a/src/mainboard/google/brya/variants/uldrenite/variant.c
+++ b/src/mainboard/google/brya/variants/uldrenite/variant.c
@@ -7,27 +7,11 @@
 #include <fw_config.h>
 #include <sar.h>
 
-#define RW350R_RST_DELAY_MS 20
-#define RW350R_PERST_DELAY_MS 30
-
 const char *get_wifi_sar_cbfs_filename(void)
 {
 	return "wifi_sar_0.hex";
 }
 
-static const struct pad_config rw350r_en_pad[] = {
-	/* H23 : LTE_PWR_OFF_EN */
-	PAD_CFG_GPO(GPP_H23, 1, DEEP),
-};
-static const struct pad_config rw350r_rst_pad[] = {
-	/* F12 : WWAN_RST_L */
-	PAD_CFG_GPO_LOCK(GPP_F12, 1, LOCK_CONFIG),
-};
-static const struct pad_config rw350r_perst_pad[] = {
-	/* F13 : PLTRST_WWAN# */
-	PAD_CFG_GPO(GPP_F13, 1, DEEP),
-};
-
 static const struct pad_config touchscreen_disable_pads[] = {
 	/* A21  : TCHSCR_REPORT_EN */
 	PAD_NC(GPP_A21, NONE),
@@ -68,22 +52,6 @@ void fw_config_gpio_padbased_override(struct pad_config *padbased_table)
 	}
 }
 
-void variant_init(void)
-{
-	if (fw_config_probe(FW_CONFIG(DB_CELLULAR, CELLULAR_ABSENT)))
-		return;
-	/*
-	 * RW350R power on seuqence:
-	 * De-assert WWAN_EN -> 20ms -> de-assert WWAN_RST -> 30ms ->
-	 * de-assert WWAN_PERST
-	 */
-	gpio_configure_pads(rw350r_en_pad, ARRAY_SIZE(rw350r_en_pad));
-	mdelay(RW350R_RST_DELAY_MS);
-	gpio_configure_pads(rw350r_rst_pad, ARRAY_SIZE(rw350r_rst_pad));
-	mdelay(RW350R_PERST_DELAY_MS);
-	gpio_configure_pads(rw350r_perst_pad, ARRAY_SIZE(rw350r_perst_pad));
-}
-
 void variant_update_soc_chip_config(struct soc_intel_alderlake_config *config)
 {
 	if (fw_config_probe(FW_CONFIG(EXT_VR, EXT_VR_PRESENT))) {
diff --git a/src/mainboard/google/brya/wwan_power.asl b/src/mainboard/google/brya/wwan_power.asl
index f19a5ef4e9..4f9b788bc5 100644
--- a/src/mainboard/google/brya/wwan_power.asl
+++ b/src/mainboard/google/brya/wwan_power.asl
@@ -11,4 +11,7 @@ Method (MPTS, 1)
 	\_SB.PCI0.CTXS(WWAN_RST);
 	Sleep(T2_OFF_MS)
 	\_SB.PCI0.CTXS(WWAN_FCPO);
+#if CONFIG(BOARD_GOOGLE_ULDRENITE)
+	Sleep(T0_OFF_MS)
+#endif
 }

From d5bd4fbdfa6561e9003b9523ceb5389a1e656062 Mon Sep 17 00:00:00 2001
From: John Su <john_su@compal.corp-partner.google.com>
Date: Thu, 27 Feb 2025 17:52:29 +0800
Subject: [PATCH 0223/3886] mb/trulo: Add host event
 EC_HOST_EVENT_BODY_DETECT_CHANGE

Add host event EC_HOST_EVENT_BODY_DETECT_CHANGE for trulo.

BRANCH=firmware-trulo-15217.771.B
BUG=b:394177292
TEST=bodydetectmode on|off, verify host event is received

Change-Id: Ifac0460e0e8feb33ad0085d250928adb593bb8ca
Signed-off-by: John Su <john_su@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86615
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 .../brya/variants/baseboard/trulo/include/baseboard/ec.h       | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/src/mainboard/google/brya/variants/baseboard/trulo/include/baseboard/ec.h b/src/mainboard/google/brya/variants/baseboard/trulo/include/baseboard/ec.h
index 3d2fc5a4b3..5bf2995d94 100644
--- a/src/mainboard/google/brya/variants/baseboard/trulo/include/baseboard/ec.h
+++ b/src/mainboard/google/brya/variants/baseboard/trulo/include/baseboard/ec.h
@@ -22,7 +22,8 @@
 	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_MKBP)              |\
 	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_PD_MCU)            |\
 	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_MODE_CHANGE)       |\
-	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_USB_MUX))
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_USB_MUX)           |\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_BODY_DETECT_CHANGE))
 
 #define MAINBOARD_EC_SMI_EVENTS \
 	(EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED))

From 70ca54bf37624e1d17a4e7b7e824294214468208 Mon Sep 17 00:00:00 2001
From: Maximilian Brune <maximilian.brune@9elements.com>
Date: Fri, 1 Mar 2024 16:17:45 +0100
Subject: [PATCH 0224/3886] mb/emulation/qemu-riscv: Add support for 512 harts
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

QEMU has a maximum of 512 of emulated harts supported.

Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: I149c8d8a43733c8ba3e02a84b0a3606d98f8b2c1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81083
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
Reviewed-by: Carlos López <carlos.lopezr4096@gmail.com>
---
 src/commonlib/Makefile.mk                     |  1 +
 src/mainboard/emulation/qemu-riscv/Kconfig    |  4 ++-
 .../emulation/qemu-riscv/Makefile.mk          |  3 ++
 .../emulation/qemu-riscv/memlayout.ld         |  2 +-
 src/mainboard/emulation/qemu-riscv/smp.c      | 28 +++++++++++++++++++
 5 files changed, 36 insertions(+), 2 deletions(-)
 create mode 100644 src/mainboard/emulation/qemu-riscv/smp.c

diff --git a/src/commonlib/Makefile.mk b/src/commonlib/Makefile.mk
index a274d5fc96..91648c5170 100644
--- a/src/commonlib/Makefile.mk
+++ b/src/commonlib/Makefile.mk
@@ -32,6 +32,7 @@ romstage-$(CONFIG_PLATFORM_USES_FSP2_0) += fsp_relocate.c
 endif
 ramstage-$(CONFIG_PLATFORM_USES_FSP2_0) += fsp_relocate.c
 
+bootblock-$(CONFIG_FLATTENED_DEVICE_TREE) += device_tree.c
 romstage-$(CONFIG_FLATTENED_DEVICE_TREE) += device_tree.c
 ramstage-$(CONFIG_FLATTENED_DEVICE_TREE) += device_tree.c
 
diff --git a/src/mainboard/emulation/qemu-riscv/Kconfig b/src/mainboard/emulation/qemu-riscv/Kconfig
index 9b5a6f0dce..286e68441e 100644
--- a/src/mainboard/emulation/qemu-riscv/Kconfig
+++ b/src/mainboard/emulation/qemu-riscv/Kconfig
@@ -26,6 +26,7 @@ config BOARD_SPECIFIC_OPTIONS
 	select FLATTENED_DEVICE_TREE
 	select MISSING_BOARD_RESET
 	select DRIVERS_UART_8250MEM
+	select RISCV_GET_HART_COUNT_AT_RUNTIME
 	select RISCV_HAS_OPENSBI
 	select ARCH_RISCV_S
 	select ARCH_RISCV_U
@@ -35,6 +36,7 @@ config BOARD_SPECIFIC_OPTIONS
 	select ARCH_ROMSTAGE_RISCV
 	select ARCH_RAMSTAGE_RISCV
 	select RISCV_USE_ARCH_TIMER
+	select FLATTENED_DEVICE_TREE
 
 config MEMLAYOUT_LD_FILE
 	string
@@ -48,7 +50,7 @@ config MAINBOARD_PART_NUMBER
 
 config MAX_CPUS
 	int
-	default 1
+	default 512 # QEMUs current limit for the virt target
 
 config RISCV_ARCH
 	string
diff --git a/src/mainboard/emulation/qemu-riscv/Makefile.mk b/src/mainboard/emulation/qemu-riscv/Makefile.mk
index bed0f80392..0f240aacd1 100644
--- a/src/mainboard/emulation/qemu-riscv/Makefile.mk
+++ b/src/mainboard/emulation/qemu-riscv/Makefile.mk
@@ -4,12 +4,14 @@ bootblock-y += mainboard.c
 bootblock-y += uart.c
 bootblock-y += rom_media.c
 bootblock-y += clint.c
+bootblock-y += smp.c
 
 romstage-y += cbmem.c
 romstage-y += romstage.c
 romstage-y += uart.c
 romstage-y += rom_media.c
 romstage-y += clint.c
+romstage-y += smp.c
 
 ramstage-y += mainboard.c
 ramstage-y += uart.c
@@ -17,5 +19,6 @@ ramstage-y += rom_media.c
 ramstage-y += clint.c
 ramstage-y += cbmem.c
 ramstage-y += chip.c
+ramstage-y += smp.c
 
 CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/include
diff --git a/src/mainboard/emulation/qemu-riscv/memlayout.ld b/src/mainboard/emulation/qemu-riscv/memlayout.ld
index 9c16496e11..9a52ec2035 100644
--- a/src/mainboard/emulation/qemu-riscv/memlayout.ld
+++ b/src/mainboard/emulation/qemu-riscv/memlayout.ld
@@ -16,5 +16,5 @@ SECTIONS
 	PRERAM_CBMEM_CONSOLE(QEMU_VIRT_DRAM + 128K + 256K + 256K + 2M,  8K)
 	FMAP_CACHE(QEMU_VIRT_DRAM + 128K + 256K + 256K + 2M + 8K,  2K)
 	CBFS_MCACHE(QEMU_VIRT_DRAM + 128K + 256K + 256K + 2M + 8K + 2K,  10K)
-	STACK(QEMU_VIRT_DRAM + 128K + 256K + 256K + 2M + 8K + 2K + 10K, 4M)
+	STACK(QEMU_VIRT_DRAM + 128K + 256K + 256K + 2M + 8K + 2K + 10K, 4K * CONFIG_MAX_CPUS)
 }
diff --git a/src/mainboard/emulation/qemu-riscv/smp.c b/src/mainboard/emulation/qemu-riscv/smp.c
new file mode 100644
index 0000000000..b6dce4719e
--- /dev/null
+++ b/src/mainboard/emulation/qemu-riscv/smp.c
@@ -0,0 +1,28 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <mcall.h>
+#include <arch/smp/smp.h>
+#include <commonlib/device_tree.h>
+#include <console/console.h>
+
+unsigned int smp_get_hart_count(void)
+{
+	if (!fdt_is_valid(HLS()->fdt))
+		goto error;
+
+	uint32_t cpus_offset = fdt_find_node_by_path(HLS()->fdt, "/cpus", NULL, NULL);
+	if (!cpus_offset)
+		goto error;
+
+	static u32 harts[CONFIG_MAX_CPUS]; // too big for the stack
+	size_t count_harts = fdt_find_subnodes_by_prefix(HLS()->fdt, cpus_offset, "cpu@",
+							 NULL, NULL, harts, CONFIG_MAX_CPUS);
+	if (!count_harts)
+		goto error;
+
+	printk(BIOS_DEBUG, "found %zu harts in devicetree\n", count_harts);
+	return count_harts;
+error:
+	printk(BIOS_ERR, "%s: Failed to read devicetree to get number of harts\n", __func__);
+	return 1; // Return single hart on failure to keep booting
+}

From 4cfc5db6b64f3b13c72b917734563d011b0d876d Mon Sep 17 00:00:00 2001
From: Fred Reitberger <reitbergerfred@gmail.com>
Date: Tue, 4 Oct 2022 15:07:49 -0400
Subject: [PATCH 0225/3886] soc/amd/common: Support sbin ucode files

Recent PI releases have been distributing the ucode patch files as sbin
files instead of bin files. The sbin uses a 256 byte amd_fw_header to
wrap the bin file.

Offset 0x14 of the header is the size field. The can be extracted with
od to get the size of the ucode bin file. The bin file can then be
extracted with dd and placed in the build directory for inclusion as a
cbfs file.

In the case where both an sbin and bin ucode file are present, the bin
file will be added and a note will print at the start of the build about
the sbin file being skipped.

TEST=builds with only bin, only sbin, non-matching bin and sbin,
matching bin and sbin files

Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: I29768ea19543bdc76662e687f59bf31b76f555ae
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68122
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/soc/amd/common/Makefile.mk           |  2 -
 src/soc/amd/common/block/cpu/Makefile.mk | 56 +++++++++++++++++++-----
 2 files changed, 45 insertions(+), 13 deletions(-)

diff --git a/src/soc/amd/common/Makefile.mk b/src/soc/amd/common/Makefile.mk
index 626260f93e..a030687817 100644
--- a/src/soc/amd/common/Makefile.mk
+++ b/src/soc/amd/common/Makefile.mk
@@ -38,8 +38,6 @@ AMDFW_CFG_WITH_PATH = $(shell echo "$(AMDFW_CFG_FILES)" | tr ' ' '\n' | grep "/"
 DEP_FILES = $(patsubst %,$(FIRMWARE_LOCATION)/%, $(AMDFW_CFG_IN_FW_LOC)) \
 	$(AMDFW_CFG_WITH_PATH)
 
-amd_microcode_bins += $(wildcard ${FIRMWARE_LOCATION}/*U?odePatch*.bin)
-
 ifeq ($(CONFIG_RESET_VECTOR_IN_RAM),y)
 $(objcbfs)/bootblock.bin: $(obj)/amdfw.rom $(obj)/fmap_config.h
 	cp $< $@
diff --git a/src/soc/amd/common/block/cpu/Makefile.mk b/src/soc/amd/common/block/cpu/Makefile.mk
index 1c4331cb91..ea40801bc6 100644
--- a/src/soc/amd/common/block/cpu/Makefile.mk
+++ b/src/soc/amd/common/block/cpu/Makefile.mk
@@ -9,18 +9,52 @@ ramstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_SVI3) += svi3.c
 ramstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_UCODE) += update_microcode.c
 
 ifeq ($(CONFIG_SOC_AMD_COMMON_BLOCK_UCODE),y)
-define add-ucode-as-cbfs
-$(if $(value cpu_microcode_$(2).bin-file),$(info File1: $(cpu_microcode_$(2).bin-file)) $(info File2: $(1)) $(error Error: The cbfs filename "cpu_microcode_$(2).bin" is used for both above files. Check your microcode patches for duplicates.))
-cbfs-files-y += cpu_microcode_$(2).bin
-cpu_microcode_$(2).bin-file := $(1)
-cpu_microcode_$(2).bin-type := microcode
 
-ifeq ($(CONFIG_SOC_AMD_COMMON_BLOCK_LPC_SPI_DMA),y)
-cpu_microcode_$(2).bin-align := 64
-else
-cpu_microcode_$(2).bin-align := 16
+define add-ucode-as-cbfs
+
+# check for duplicate microcode files. Same sbin and bin ucode is allowed here though, because mendocino has a duplicate.
+ifeq ($(cpu_microcode_$(2).bin-file), $(obj)/cpu_microcode_$(2).$(3))
+    $$(info Tried to add ucode: $(1))
+    $$(error Error: The cbfs filename "cpu_microcode_$(2).bin" is already used. Check your microcode patches for duplicates.)
 endif
+
+# offset 0x14 contains the size of the unwrapped ucode file
+# .sbin files contain a 256 wrapper around the usual microcode file
+$(obj)/cpu_microcode_$(2).$(3): $(1)
+	echo $$< "->" $$@
+	if   [ $(3) = "bin" ]; then \
+	  cp $$< $$@; \
+	elif [ $(3) = "sbin" ]; then \
+	  size=$$$$(od --endian little --address-radix n --read-bytes 4 --skip-bytes 0x14 --format u4 $$<); \
+	  dd status=none ibs=1 skip=256 count=$$$$((size)) if=$$< of=$$@; \
+	fi
+
+# if there is both a sbin and bin microcode only include the bin one to keep the old behaviour
+ifeq ($(cpu_microcode_$(2).bin-file),)
+    cbfs-files-y += cpu_microcode_$(2).bin
+    cpu_microcode_$(2).bin-file := $(obj)/cpu_microcode_$(2).$(3)
+    cpu_microcode_$(2).bin-type := microcode
+
+    ifeq ($(CONFIG_SOC_AMD_COMMON_BLOCK_LPC_SPI_DMA),y)
+        cpu_microcode_$(2).bin-align := 64
+    else
+        cpu_microcode_$(2).bin-align := 16
+    endif
+endif
+
 endef
 
-$(foreach ucode,$(amd_microcode_bins),$(eval $(call add-ucode-as-cbfs,$(ucode),$(shell hexdump -n 2 -s 0x18 -e '"%x"' $(ucode)))))
-endif
+amd_microcode_bins  += $(wildcard ${FIRMWARE_LOCATION}/*U?odePatch*.bin)
+amd_microcode_sbins += $(wildcard ${FIRMWARE_LOCATION}/*UcodePatch_*.sbin)
+
+# Function to grab bytes from a file and format them as desired
+# $(call extract-bytes,filename,bytes-to-read,offset-to-bytes,output-format)
+extract-bytes = $(shell echo $(shell od --endian little --address-radix n --read-bytes $(2) --skip-bytes $(3) --format $(4) $(1)))
+
+$(foreach ucode, $(amd_microcode_bins), \
+    $(eval $(call add-ucode-as-cbfs,$(ucode),$(call extract-bytes,$(ucode),2,0x18,x2),bin)))
+
+$(foreach ucode, $(amd_microcode_sbins), \
+    $(eval $(call add-ucode-as-cbfs,$(ucode),$(call extract-bytes,$(ucode),2,0x118,x2),sbin)))
+
+endif #ifeq ($(CONFIG_SOC_AMD_COMMON_BLOCK_UCODE),y)

From af2d11f96328dd2fd16be8c4881f7b536736bec4 Mon Sep 17 00:00:00 2001
From: Frank Wu <frank_wu@compal.corp-partner.google.com>
Date: Tue, 25 Feb 2025 16:11:08 +0800
Subject: [PATCH 0226/3886] mb/google/fatcat/var/francka: Adjust NVMe SSD power
 sequence

Move SSD enable/reset pins to romstage to have more time for initialization.

BUG=b:398070426
BRANCH=None
TEST=Build francka and do EC reset to check the SSD boots to OS successfully

Change-Id: I468ba34a54046ef6ed3d5ec4c625a87bb5255640
Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86593
Reviewed-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/google/fatcat/variants/francka/gpio.c | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/src/mainboard/google/fatcat/variants/francka/gpio.c b/src/mainboard/google/fatcat/variants/francka/gpio.c
index 6265b1667d..f2868fc638 100644
--- a/src/mainboard/google/fatcat/variants/francka/gpio.c
+++ b/src/mainboard/google/fatcat/variants/francka/gpio.c
@@ -416,6 +416,8 @@ static const struct pad_config early_gpio_table[] = {
 
 /* Pad configuration in romstage */
 static const struct pad_config romstage_gpio_table[] = {
+	/* GPP_B16:     SOC_SSD2_EN */
+	PAD_CFG_GPO(GPP_B16, 1, PLTRST),
 	/* GPP_C00:     SOC_SMBCLK */
 	PAD_CFG_NF(GPP_C00, NONE, DEEP, NF1),
 	/* GPP_C01:     SOC_SMBDATA */
@@ -424,6 +426,8 @@ static const struct pad_config romstage_gpio_table[] = {
 	PAD_CFG_GPO(GPP_H03, 0, DEEP),
 	/* GPP_H17:     FP_RST_1V8_OD# */
 	PAD_CFG_GPO(GPP_H17, 0, DEEP),
+	/* GPP_E03:     SOC_SSD2_RST# */
+	PAD_CFG_GPO(GPP_E03, 1, PLTRST),
 };
 
 const struct pad_config *variant_gpio_table(size_t *num)

From d8aaa220c8f0004e43331ff248d7eef6be3dd13a Mon Sep 17 00:00:00 2001
From: Vesek <venda.straka@gmail.com>
Date: Thu, 2 Jan 2025 06:40:48 +0100
Subject: [PATCH 0227/3886] mb/hp: Add Pro 3400

Based on autoport and HP Pro 3500.
As part of this change renamed 3500 to 3x00 and added this as
it's variant.

It's an almost identical board to the 3500 but has a smaller flash.

Other differences between boards were identified by autoport.
They may or may not important but were included anyway.

Tested on HP Pro 3400, behaves exactly as 3500 described in the docs.
Changes were not significant enough to require retesting on 3500.

Change-Id: I833996f6eddcaac91fb0ad0cd95fcc2a99447387
Signed-off-by: Vesek <venda.straka@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85825
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
---
 Documentation/mainboard/hp/pro_3500_series.md |  76 +++----
 Documentation/mainboard/index.md              |   2 +-
 src/mainboard/hp/pro_3500_series/Kconfig      |  37 ----
 src/mainboard/hp/pro_3x00_series/Kconfig      |  48 +++++
 .../Kconfig.name                              |   3 +
 .../Makefile.mk                               |   4 +-
 .../acpi/ec.asl                               |   0
 .../acpi/platform.asl                         |   0
 .../acpi/superio.asl                          |   0
 .../acpi_tables.c                             |   0
 .../hp/pro_3x00_series/board_info.txt         |   5 +
 src/mainboard/hp/pro_3x00_series/cmos.default |   8 +
 src/mainboard/hp/pro_3x00_series/cmos.layout  |  68 +++++++
 .../common_defines.h                          |   0
 .../devicetree.cb                             |  16 --
 .../dsdt.asl                                  |   3 +-
 .../early_init.c                              |   0
 .../gma-mainboard.ads                         |   0
 .../hda_verb.c                                |   0
 .../led.c                                     |   0
 .../led.h                                     |   0
 .../mainboard.c                               |   0
 .../smihandler.c                              |   0
 .../variants/pro_3400_series/board_info.txt   |   5 +
 .../variants/pro_3400_series/data.vbt         | Bin 0 -> 7168 bytes
 .../variants/pro_3400_series/gpio.c           | 189 ++++++++++++++++++
 .../variants/pro_3400_series/overridetree.cb  |  27 +++
 .../variants}/pro_3500_series/board_info.txt  |   1 -
 .../variants}/pro_3500_series/data.vbt        | Bin
 .../variants}/pro_3500_series/gpio.c          |   0
 .../variants/pro_3500_series/overridetree.cb  |  27 +++
 31 files changed, 425 insertions(+), 94 deletions(-)
 delete mode 100644 src/mainboard/hp/pro_3500_series/Kconfig
 create mode 100644 src/mainboard/hp/pro_3x00_series/Kconfig
 rename src/mainboard/hp/{pro_3500_series => pro_3x00_series}/Kconfig.name (63%)
 rename src/mainboard/hp/{pro_3500_series => pro_3x00_series}/Makefile.mk (69%)
 rename src/mainboard/hp/{pro_3500_series => pro_3x00_series}/acpi/ec.asl (100%)
 rename src/mainboard/hp/{pro_3500_series => pro_3x00_series}/acpi/platform.asl (100%)
 rename src/mainboard/hp/{pro_3500_series => pro_3x00_series}/acpi/superio.asl (100%)
 rename src/mainboard/hp/{pro_3500_series => pro_3x00_series}/acpi_tables.c (100%)
 create mode 100644 src/mainboard/hp/pro_3x00_series/board_info.txt
 create mode 100644 src/mainboard/hp/pro_3x00_series/cmos.default
 create mode 100644 src/mainboard/hp/pro_3x00_series/cmos.layout
 rename src/mainboard/hp/{pro_3500_series => pro_3x00_series}/common_defines.h (100%)
 rename src/mainboard/hp/{pro_3500_series => pro_3x00_series}/devicetree.cb (91%)
 rename src/mainboard/hp/{pro_3500_series => pro_3x00_series}/dsdt.asl (99%)
 rename src/mainboard/hp/{pro_3500_series => pro_3x00_series}/early_init.c (100%)
 rename src/mainboard/hp/{pro_3500_series => pro_3x00_series}/gma-mainboard.ads (100%)
 rename src/mainboard/hp/{pro_3500_series => pro_3x00_series}/hda_verb.c (100%)
 rename src/mainboard/hp/{pro_3500_series => pro_3x00_series}/led.c (100%)
 rename src/mainboard/hp/{pro_3500_series => pro_3x00_series}/led.h (100%)
 rename src/mainboard/hp/{pro_3500_series => pro_3x00_series}/mainboard.c (100%)
 rename src/mainboard/hp/{pro_3500_series => pro_3x00_series}/smihandler.c (100%)
 create mode 100644 src/mainboard/hp/pro_3x00_series/variants/pro_3400_series/board_info.txt
 create mode 100644 src/mainboard/hp/pro_3x00_series/variants/pro_3400_series/data.vbt
 create mode 100644 src/mainboard/hp/pro_3x00_series/variants/pro_3400_series/gpio.c
 create mode 100644 src/mainboard/hp/pro_3x00_series/variants/pro_3400_series/overridetree.cb
 rename src/mainboard/hp/{ => pro_3x00_series/variants}/pro_3500_series/board_info.txt (83%)
 rename src/mainboard/hp/{ => pro_3x00_series/variants}/pro_3500_series/data.vbt (100%)
 rename src/mainboard/hp/{ => pro_3x00_series/variants}/pro_3500_series/gpio.c (100%)
 create mode 100644 src/mainboard/hp/pro_3x00_series/variants/pro_3500_series/overridetree.cb

diff --git a/Documentation/mainboard/hp/pro_3500_series.md b/Documentation/mainboard/hp/pro_3500_series.md
index 881bf372f4..3280066875 100644
--- a/Documentation/mainboard/hp/pro_3500_series.md
+++ b/Documentation/mainboard/hp/pro_3500_series.md
@@ -1,43 +1,53 @@
-# HP Pro 3500 Series
+# HP Pro 3x00 Series
 
-This page describes how to run coreboot on the [Pro 3500 Series]
-desktop from [HP].
+This page describes how to run coreboot on the [Pro 3400 Series] and [Pro 3500 Series]
+desktops from [HP].
 
 ## State
 
 All peripherals should work. Automatic fan control as well as S3 are
 working. The board was tested to boot Linux and Windows. EHCI debug
-is untested. When using MrChromebox edk2 with secure boot build in, the
-board will hang on each boot for about 20 seconds before continuing.
-With disabled ME, the SuperIO will not get CPU temperatures via PECI and
-therefore the automatic fan control will not increase the fan speed.
+is untested. With disabled ME, the SuperIO will not get CPU
+temperatures via PECI and therefore the automatic fan control
+will not increase the fan speed.
 
 ## Flashing coreboot
 
 ```{eval-rst}
-+---------------------+-------------------------+
-| Type                | Value                   |
-+=====================+=========================+
-| Socketed flash      | No                      |
-+---------------------+-------------------------+
-| Model               | W25Q64FVSIG             |
-+---------------------+-------------------------+
-| Size                | 8 MiB                   |
-+---------------------+-------------------------+
-| In circuit flashing | Yes                     |
-+---------------------+-------------------------+
-| Package             | SOIC-8                  |
-+---------------------+-------------------------+
-| Write protection    | See below               |
-+---------------------+-------------------------+
-| Dual BIOS feature   | No                      |
-+---------------------+-------------------------+
-| Internal flashing   | Yes                     |
-+---------------------+-------------------------+
++---------------------+-----------------------------------------+
+| Type                | Value                                   |
++=====================+=========================================+
+| Socketed flash      | No                                      |
++---------------------+-----------------------------------------+
+| Model               | W25Q32BVSIG (3400) / W25Q64FVSIG (3500) |
++---------------------+-----------------------------------------+
+| Size                | 4 MiB (3400) / 8 MiB (3500)             |
++---------------------+-----------------------------------------+
+| In circuit flashing | Yes                                     |
++---------------------+-----------------------------------------+
+| Package             | SOIC-8                                  |
++---------------------+-----------------------------------------+
+| Write protection    | See below                               |
++---------------------+-----------------------------------------+
+| Dual BIOS feature   | No                                      |
++---------------------+-----------------------------------------+
+| Internal flashing   | Yes                                     |
++---------------------+-----------------------------------------+
 ```
 
 ### Flash layout
 The original layout of the flash should look like this:
+
+#### Pro 3400
+```
+00000000:00000fff fd
+00180000:003fffff bios
+00001000:0017ffff me
+00fff000:00000fff gbe
+00fff000:00000fff pd
+```
+
+#### Pro 3500
 ```
 00000000:00000fff fd
 00400000:007fffff bios
@@ -48,8 +58,7 @@ The original layout of the flash should look like this:
 
 ### Internal programming
 
-The SPI flash can be accessed using [flashrom] (although it reports as
-"N25Q064..3E", it works fine).
+The SPI flash can be accessed using [flashrom].
 
 With a missing FDO jumper, `fd` region is read-only, `bios` region is
 read-write and `me` region is locked. Vendor firmware will additionally
@@ -62,9 +71,7 @@ region will be modified on shutdown. Cut the AC power or do a restart
 from the OS.
 
 **Position of FDO jumper (E2) close to the F_USB3**
-![][pro_3500_jumper]
-
-[pro_3500_jumper]: pro_3500_series_jumper.avif
+![FDO jumper position](pro_3500_series_jumper.avif)
 
 ### External programming
 
@@ -76,9 +83,7 @@ The supply needs to quickly reach 3V3 or else the chip is also unstable
 until cleanly power cycled.
 
 **Position of SOIC-8 flash and pin-header near ATX power connector**
-![][pro_3500_flash]
-
-[pro_3500_flash]: pro_3500_series_flash.avif
+![Flash position](pro_3500_series_flash.avif)
 
 ## Technology
 
@@ -98,6 +103,7 @@ until cleanly power cycled.
 +------------------+--------------------------------------------------+
 ```
 
-[Pro 3500 Series]: https://support.hp.com/us-en/document/c03364089
+[Pro 3400 Series]: https://support.hp.com/us-en/product/details/hp-pro-3400-microtower-pc/5160137
+[Pro 3500 Series]: https://support.hp.com/us-en/product/details/hp-pro-3500-microtower-pc/5270849
 [HP]: https://www.hp.com/
 [flashrom]: https://flashrom.org/Flashrom
diff --git a/Documentation/mainboard/index.md b/Documentation/mainboard/index.md
index 518c02a994..177abff452 100644
--- a/Documentation/mainboard/index.md
+++ b/Documentation/mainboard/index.md
@@ -139,7 +139,7 @@ GA-H61M-S2PV <gigabyte/ga-h61m-s2pv.md>
 Compaq 8200 Elite SFF <hp/compaq_8200_sff.md>
 Compaq 8300 Elite SFF <hp/compaq_8300_sff.md>
 Compaq Elite 8300 USDT <hp/compaq_8300_usdt.md>
-Pro 3500 Series <hp/pro_3500_series.md>
+Pro 3x00 Series <hp/pro_3500_series.md>
 Z220 Workstation SFF <hp/z220_sff.md>
 ```
 
diff --git a/src/mainboard/hp/pro_3500_series/Kconfig b/src/mainboard/hp/pro_3500_series/Kconfig
deleted file mode 100644
index ab77654b39..0000000000
--- a/src/mainboard/hp/pro_3500_series/Kconfig
+++ /dev/null
@@ -1,37 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0-or-later
-
-if BOARD_HP_PRO_3500_SERIES
-
-config BOARD_SPECIFIC_OPTIONS
-	def_bool y
-	select BOARD_ROMSIZE_KB_8192
-	select HAVE_ACPI_RESUME
-	select HAVE_ACPI_TABLES
-	select INTEL_GMA_HAVE_VBT
-	select MAINBOARD_HAS_LIBGFXINIT
-	select MAINBOARD_USES_IFD_GBE_REGION
-	select NORTHBRIDGE_INTEL_SANDYBRIDGE
-	select NO_UART_ON_SUPERIO
-	select SERIRQ_CONTINUOUS_MODE
-	select SOUTHBRIDGE_INTEL_BD82X6X
-	select SUPERIO_ITE_IT8772F
-	select USE_NATIVE_RAMINIT
-
-config CBFS_SIZE
-	default 0x400000
-
-config MAINBOARD_DIR
-	default "hp/pro_3500_series"
-
-config MAINBOARD_PART_NUMBER
-	default "Pro 3500 Series"
-
-config VGA_BIOS_ID
-	default "8086,0152"
-
-config DRAM_RESET_GATE_GPIO
-	default 60
-
-config USBDEBUG_HCD_INDEX
-	default 2
-endif
diff --git a/src/mainboard/hp/pro_3x00_series/Kconfig b/src/mainboard/hp/pro_3x00_series/Kconfig
new file mode 100644
index 0000000000..47f24db10d
--- /dev/null
+++ b/src/mainboard/hp/pro_3x00_series/Kconfig
@@ -0,0 +1,48 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+config BOARD_HP_PRO_3X00_SERIES_COMMON
+	def_bool n
+	select HAVE_ACPI_RESUME
+	select HAVE_ACPI_TABLES
+	select HAVE_CMOS_DEFAULT
+	select HAVE_OPTION_TABLE
+	select INTEL_GMA_HAVE_VBT
+	select MAINBOARD_HAS_LIBGFXINIT
+	select NORTHBRIDGE_INTEL_SANDYBRIDGE
+	select NO_UART_ON_SUPERIO
+	select SERIRQ_CONTINUOUS_MODE
+	select SOUTHBRIDGE_INTEL_BD82X6X
+	select SUPERIO_ITE_IT8772F
+	select USE_NATIVE_RAMINIT
+
+config BOARD_HP_PRO_3400_SERIES
+	select BOARD_HP_PRO_3X00_SERIES_COMMON
+	select BOARD_ROMSIZE_KB_4096
+
+config BOARD_HP_PRO_3500_SERIES
+	select BOARD_HP_PRO_3X00_SERIES_COMMON
+	select BOARD_ROMSIZE_KB_8192
+
+if BOARD_HP_PRO_3X00_SERIES_COMMON
+
+config CBFS_SIZE
+	default 0x200000 if BOARD_ROMSIZE_KB_4096
+	default 0x400000 if BOARD_ROMSIZE_KB_8192
+
+config MAINBOARD_DIR
+	default "hp/pro_3x00_series"
+
+config VARIANT_DIR
+	default "pro_3400_series" if BOARD_HP_PRO_3400_SERIES
+	default "pro_3500_series" if BOARD_HP_PRO_3500_SERIES
+
+config MAINBOARD_PART_NUMBER
+	default "Pro 3400 Series" if BOARD_HP_PRO_3400_SERIES
+	default "Pro 3500 Series" if BOARD_HP_PRO_3500_SERIES
+
+config OVERRIDE_DEVICETREE
+	default "variants/\$(CONFIG_VARIANT_DIR)/overridetree.cb"
+
+config USBDEBUG_HCD_INDEX
+	default 2
+endif
diff --git a/src/mainboard/hp/pro_3500_series/Kconfig.name b/src/mainboard/hp/pro_3x00_series/Kconfig.name
similarity index 63%
rename from src/mainboard/hp/pro_3500_series/Kconfig.name
rename to src/mainboard/hp/pro_3x00_series/Kconfig.name
index fd1222c68a..fea2e4f707 100644
--- a/src/mainboard/hp/pro_3500_series/Kconfig.name
+++ b/src/mainboard/hp/pro_3x00_series/Kconfig.name
@@ -1,4 +1,7 @@
 # SPDX-License-Identifier: GPL-2.0-or-later
 
+config BOARD_HP_PRO_3400_SERIES
+	bool "Pro 3400 Series"
+
 config BOARD_HP_PRO_3500_SERIES
 	bool "Pro 3500 Series"
diff --git a/src/mainboard/hp/pro_3500_series/Makefile.mk b/src/mainboard/hp/pro_3x00_series/Makefile.mk
similarity index 69%
rename from src/mainboard/hp/pro_3500_series/Makefile.mk
rename to src/mainboard/hp/pro_3x00_series/Makefile.mk
index 6554ed5e8c..bc01687e99 100644
--- a/src/mainboard/hp/pro_3500_series/Makefile.mk
+++ b/src/mainboard/hp/pro_3x00_series/Makefile.mk
@@ -1,11 +1,11 @@
 # SPDX-License-Identifier: GPL-2.0-or-later
 
 bootblock-y += early_init.c
-bootblock-y += gpio.c
+bootblock-y += variants/$(VARIANT_DIR)/gpio.c
 bootblock-y += led.c
 
 romstage-y += early_init.c
-romstage-y += gpio.c
+romstage-y += variants/$(VARIANT_DIR)/gpio.c
 
 ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads
 
diff --git a/src/mainboard/hp/pro_3500_series/acpi/ec.asl b/src/mainboard/hp/pro_3x00_series/acpi/ec.asl
similarity index 100%
rename from src/mainboard/hp/pro_3500_series/acpi/ec.asl
rename to src/mainboard/hp/pro_3x00_series/acpi/ec.asl
diff --git a/src/mainboard/hp/pro_3500_series/acpi/platform.asl b/src/mainboard/hp/pro_3x00_series/acpi/platform.asl
similarity index 100%
rename from src/mainboard/hp/pro_3500_series/acpi/platform.asl
rename to src/mainboard/hp/pro_3x00_series/acpi/platform.asl
diff --git a/src/mainboard/hp/pro_3500_series/acpi/superio.asl b/src/mainboard/hp/pro_3x00_series/acpi/superio.asl
similarity index 100%
rename from src/mainboard/hp/pro_3500_series/acpi/superio.asl
rename to src/mainboard/hp/pro_3x00_series/acpi/superio.asl
diff --git a/src/mainboard/hp/pro_3500_series/acpi_tables.c b/src/mainboard/hp/pro_3x00_series/acpi_tables.c
similarity index 100%
rename from src/mainboard/hp/pro_3500_series/acpi_tables.c
rename to src/mainboard/hp/pro_3x00_series/acpi_tables.c
diff --git a/src/mainboard/hp/pro_3x00_series/board_info.txt b/src/mainboard/hp/pro_3x00_series/board_info.txt
new file mode 100644
index 0000000000..7114c27cfe
--- /dev/null
+++ b/src/mainboard/hp/pro_3x00_series/board_info.txt
@@ -0,0 +1,5 @@
+Category: desktop
+ROM package: SOIC-8
+ROM socketed: no
+Flashrom support: yes
+Release year: 2011-2012
diff --git a/src/mainboard/hp/pro_3x00_series/cmos.default b/src/mainboard/hp/pro_3x00_series/cmos.default
new file mode 100644
index 0000000000..7c313be420
--- /dev/null
+++ b/src/mainboard/hp/pro_3x00_series/cmos.default
@@ -0,0 +1,8 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
+boot_option=Fallback
+debug_level=Debug
+gfx_uma_size=64M
+nmi=Disable
+power_on_after_fail=Disable
+sata_mode=AHCI
diff --git a/src/mainboard/hp/pro_3x00_series/cmos.layout b/src/mainboard/hp/pro_3x00_series/cmos.layout
new file mode 100644
index 0000000000..e6dba00063
--- /dev/null
+++ b/src/mainboard/hp/pro_3x00_series/cmos.layout
@@ -0,0 +1,68 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
+# -----------------------------------------------------------------
+entries
+
+# start-bit	length	config	enum-ID	name
+0		384	r	0	reserved_memory
+
+# -----------------------------------------------------------------
+# RTC_BOOT_BYTE (coreboot hardcoded)
+384		1	e	3	boot_option
+388		4	h	0	reboot_counter
+
+# -----------------------------------------------------------------
+# coreboot config options: console
+395		4	e	4	debug_level
+
+# coreboot config options: southbridge
+408		1	e	1	nmi
+409		2	e	5	power_on_after_fail
+411		1	e	6	sata_mode
+
+# coreboot config options: northbridge
+412		3	e	7	gfx_uma_size
+
+# coreboot config options: check sums
+984		16	h	0	check_sum
+
+# -----------------------------------------------------------------
+
+enumerations
+
+#ID	value	text
+1	0	Disable
+1	1	Enable
+
+3	0	Fallback
+3	1	Normal
+
+4	0	Emergency
+4	1	Alert
+4	2	Critical
+4	3	Error
+4	4	Warning
+4	5	Notice
+4	6	Info
+4	7	Debug
+4	8	Spew
+
+5	0	Disable
+5	1	Enable
+5	2	Keep
+
+6	0	AHCI
+6	1	Compatible
+
+7	0	32M
+7	1	64M
+7	2	96M
+7	3	128M
+7	4	160M
+7	5	192M
+7	6	224M
+
+# -----------------------------------------------------------------
+checksums
+
+checksum 392 415 984
diff --git a/src/mainboard/hp/pro_3500_series/common_defines.h b/src/mainboard/hp/pro_3x00_series/common_defines.h
similarity index 100%
rename from src/mainboard/hp/pro_3500_series/common_defines.h
rename to src/mainboard/hp/pro_3x00_series/common_defines.h
diff --git a/src/mainboard/hp/pro_3500_series/devicetree.cb b/src/mainboard/hp/pro_3x00_series/devicetree.cb
similarity index 91%
rename from src/mainboard/hp/pro_3500_series/devicetree.cb
rename to src/mainboard/hp/pro_3x00_series/devicetree.cb
index 3d9cf6170b..cf75313432 100644
--- a/src/mainboard/hp/pro_3500_series/devicetree.cb
+++ b/src/mainboard/hp/pro_3x00_series/devicetree.cb
@@ -22,22 +22,6 @@ chip northbridge/intel/sandybridge
 			register "sata_port_map" = "0x33"
 			register "spi_lvscc" = "0x2005"
 			register "spi_uvscc" = "0x2005"
-			register "usb_port_config" = "{
-				{ 1,  6, 0 },
-				{ 1,  6, 0 },
-				{ 1,  6, 1 },
-				{ 1,  9, 1 },
-				{ 1, 10, 2 },
-				{ 1, 11, 2 },
-				{ 1,  6, 3 },
-				{ 1,  6, 3 },
-				{ 1,  6, 4 },
-				{ 1, 12, 4 },
-				{ 1,  6, 6 },
-				{ 1, 11, 5 },
-				{ 1,  6, 5 },
-				{ 1,  6, 6 },
-			}"
 			device ref ehci2 on end
 			device ref hda on end
 			device ref pcie_rp2 on end # MINI_PCIE
diff --git a/src/mainboard/hp/pro_3500_series/dsdt.asl b/src/mainboard/hp/pro_3x00_series/dsdt.asl
similarity index 99%
rename from src/mainboard/hp/pro_3500_series/dsdt.asl
rename to src/mainboard/hp/pro_3x00_series/dsdt.asl
index cbdf0c6fba..cee4939fe0 100644
--- a/src/mainboard/hp/pro_3500_series/dsdt.asl
+++ b/src/mainboard/hp/pro_3x00_series/dsdt.asl
@@ -1,8 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
+
 #define BRIGHTNESS_UP \_SB.PCI0.GFX0.INCB
 #define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.DECB
-
-
 #include <acpi/acpi.h>
 
 DefinitionBlock(
diff --git a/src/mainboard/hp/pro_3500_series/early_init.c b/src/mainboard/hp/pro_3x00_series/early_init.c
similarity index 100%
rename from src/mainboard/hp/pro_3500_series/early_init.c
rename to src/mainboard/hp/pro_3x00_series/early_init.c
diff --git a/src/mainboard/hp/pro_3500_series/gma-mainboard.ads b/src/mainboard/hp/pro_3x00_series/gma-mainboard.ads
similarity index 100%
rename from src/mainboard/hp/pro_3500_series/gma-mainboard.ads
rename to src/mainboard/hp/pro_3x00_series/gma-mainboard.ads
diff --git a/src/mainboard/hp/pro_3500_series/hda_verb.c b/src/mainboard/hp/pro_3x00_series/hda_verb.c
similarity index 100%
rename from src/mainboard/hp/pro_3500_series/hda_verb.c
rename to src/mainboard/hp/pro_3x00_series/hda_verb.c
diff --git a/src/mainboard/hp/pro_3500_series/led.c b/src/mainboard/hp/pro_3x00_series/led.c
similarity index 100%
rename from src/mainboard/hp/pro_3500_series/led.c
rename to src/mainboard/hp/pro_3x00_series/led.c
diff --git a/src/mainboard/hp/pro_3500_series/led.h b/src/mainboard/hp/pro_3x00_series/led.h
similarity index 100%
rename from src/mainboard/hp/pro_3500_series/led.h
rename to src/mainboard/hp/pro_3x00_series/led.h
diff --git a/src/mainboard/hp/pro_3500_series/mainboard.c b/src/mainboard/hp/pro_3x00_series/mainboard.c
similarity index 100%
rename from src/mainboard/hp/pro_3500_series/mainboard.c
rename to src/mainboard/hp/pro_3x00_series/mainboard.c
diff --git a/src/mainboard/hp/pro_3500_series/smihandler.c b/src/mainboard/hp/pro_3x00_series/smihandler.c
similarity index 100%
rename from src/mainboard/hp/pro_3500_series/smihandler.c
rename to src/mainboard/hp/pro_3x00_series/smihandler.c
diff --git a/src/mainboard/hp/pro_3x00_series/variants/pro_3400_series/board_info.txt b/src/mainboard/hp/pro_3x00_series/variants/pro_3400_series/board_info.txt
new file mode 100644
index 0000000000..9a9d75de47
--- /dev/null
+++ b/src/mainboard/hp/pro_3x00_series/variants/pro_3400_series/board_info.txt
@@ -0,0 +1,5 @@
+Category: desktop
+ROM package: SOIC-8
+ROM socketed: n
+Flashrom support: y
+Release year: 2011
diff --git a/src/mainboard/hp/pro_3x00_series/variants/pro_3400_series/data.vbt b/src/mainboard/hp/pro_3x00_series/variants/pro_3400_series/data.vbt
new file mode 100644
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zCQSyn#bCz*R&m!0nJBJPWwm2*6=^z;rjo5@Jgj^+ZEbqR(bfiSs9|w0cqp~zAcAA{
zb5X0ouny(J9#7fg9Kd5T6!?<)-?+Un0*;<p`cAy|<m&oo;QcOAFANNJK$QL))^q3J
oj+v?~fs1uffuaIM1&Rt36(}lDRG_FpQGucYMFolq{JRSL2?B~!^8f$<

literal 0
HcmV?d00001

diff --git a/src/mainboard/hp/pro_3x00_series/variants/pro_3400_series/gpio.c b/src/mainboard/hp/pro_3x00_series/variants/pro_3400_series/gpio.c
new file mode 100644
index 0000000000..bac321c735
--- /dev/null
+++ b/src/mainboard/hp/pro_3x00_series/variants/pro_3400_series/gpio.c
@@ -0,0 +1,189 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <southbridge/intel/common/gpio.h>
+
+static const struct pch_gpio_set1 pch_gpio_set1_mode = {
+	.gpio0 = GPIO_MODE_GPIO,
+	.gpio1 = GPIO_MODE_GPIO,
+	.gpio2 = GPIO_MODE_NATIVE,
+	.gpio3 = GPIO_MODE_NATIVE,
+	.gpio4 = GPIO_MODE_NATIVE,
+	.gpio5 = GPIO_MODE_NATIVE,
+	.gpio6 = GPIO_MODE_GPIO,
+	.gpio7 = GPIO_MODE_GPIO,
+	.gpio8 = GPIO_MODE_GPIO,
+	.gpio9 = GPIO_MODE_NATIVE,
+	.gpio10 = GPIO_MODE_NATIVE,
+	.gpio11 = GPIO_MODE_NATIVE,
+	.gpio12 = GPIO_MODE_GPIO,
+	.gpio13 = GPIO_MODE_GPIO,
+	.gpio14 = GPIO_MODE_NATIVE,
+	.gpio15 = GPIO_MODE_GPIO,
+	.gpio16 = GPIO_MODE_GPIO,
+	.gpio17 = GPIO_MODE_GPIO,
+	.gpio18 = GPIO_MODE_NATIVE,
+	.gpio19 = GPIO_MODE_NATIVE,
+	.gpio20 = GPIO_MODE_NATIVE,
+	.gpio21 = GPIO_MODE_NATIVE,
+	.gpio22 = GPIO_MODE_GPIO,
+	.gpio23 = GPIO_MODE_NATIVE,
+	.gpio24 = GPIO_MODE_GPIO,
+	.gpio25 = GPIO_MODE_NATIVE,
+	.gpio26 = GPIO_MODE_NATIVE,
+	.gpio27 = GPIO_MODE_GPIO,
+	.gpio28 = GPIO_MODE_GPIO,
+	.gpio29 = GPIO_MODE_GPIO,
+	.gpio30 = GPIO_MODE_NATIVE,
+	.gpio31 = GPIO_MODE_GPIO,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_direction = {
+	.gpio0 = GPIO_DIR_INPUT,
+	.gpio1 = GPIO_DIR_INPUT,
+	.gpio6 = GPIO_DIR_INPUT,
+	.gpio7 = GPIO_DIR_INPUT,
+	.gpio8 = GPIO_DIR_OUTPUT,
+	.gpio12 = GPIO_DIR_INPUT,
+	.gpio13 = GPIO_DIR_INPUT,
+	.gpio15 = GPIO_DIR_OUTPUT,
+	.gpio16 = GPIO_DIR_INPUT,
+	.gpio17 = GPIO_DIR_INPUT,
+	.gpio22 = GPIO_DIR_INPUT,
+	.gpio24 = GPIO_DIR_OUTPUT,
+	.gpio27 = GPIO_DIR_INPUT,
+	.gpio28 = GPIO_DIR_OUTPUT,
+	.gpio29 = GPIO_DIR_OUTPUT,
+	.gpio31 = GPIO_DIR_INPUT,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_level = {
+	.gpio8 = GPIO_LEVEL_HIGH,
+	.gpio15 = GPIO_LEVEL_LOW,
+	.gpio24 = GPIO_LEVEL_LOW,
+	.gpio28 = GPIO_LEVEL_LOW,
+	.gpio29 = GPIO_LEVEL_HIGH,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_reset = {
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_invert = {
+	.gpio13 = GPIO_INVERT,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_blink = {
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_mode = {
+	.gpio32 = GPIO_MODE_GPIO,
+	.gpio33 = GPIO_MODE_GPIO,
+	.gpio34 = GPIO_MODE_GPIO,
+	.gpio35 = GPIO_MODE_GPIO,
+	.gpio36 = GPIO_MODE_GPIO,
+	.gpio37 = GPIO_MODE_GPIO,
+	.gpio38 = GPIO_MODE_GPIO,
+	.gpio39 = GPIO_MODE_GPIO,
+	.gpio40 = GPIO_MODE_NATIVE,
+	.gpio41 = GPIO_MODE_NATIVE,
+	.gpio42 = GPIO_MODE_NATIVE,
+	.gpio43 = GPIO_MODE_GPIO,
+	.gpio44 = GPIO_MODE_NATIVE,
+	.gpio45 = GPIO_MODE_NATIVE,
+	.gpio46 = GPIO_MODE_NATIVE,
+	.gpio47 = GPIO_MODE_NATIVE,
+	.gpio48 = GPIO_MODE_GPIO,
+	.gpio49 = GPIO_MODE_GPIO,
+	.gpio50 = GPIO_MODE_NATIVE,
+	.gpio51 = GPIO_MODE_NATIVE,
+	.gpio52 = GPIO_MODE_NATIVE,
+	.gpio53 = GPIO_MODE_NATIVE,
+	.gpio54 = GPIO_MODE_NATIVE,
+	.gpio55 = GPIO_MODE_NATIVE,
+	.gpio56 = GPIO_MODE_NATIVE,
+	.gpio57 = GPIO_MODE_GPIO,
+	.gpio58 = GPIO_MODE_NATIVE,
+	.gpio59 = GPIO_MODE_NATIVE,
+	.gpio60 = GPIO_MODE_GPIO,
+	.gpio61 = GPIO_MODE_GPIO,
+	.gpio62 = GPIO_MODE_NATIVE,
+	.gpio63 = GPIO_MODE_NATIVE,
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_direction = {
+	.gpio32 = GPIO_DIR_OUTPUT,
+	.gpio33 = GPIO_DIR_OUTPUT,
+	.gpio34 = GPIO_DIR_INPUT,
+	.gpio35 = GPIO_DIR_INPUT,
+	.gpio36 = GPIO_DIR_INPUT,
+	.gpio37 = GPIO_DIR_INPUT,
+	.gpio38 = GPIO_DIR_INPUT,
+	.gpio39 = GPIO_DIR_INPUT,
+	.gpio43 = GPIO_DIR_INPUT,
+	.gpio48 = GPIO_DIR_INPUT,
+	.gpio49 = GPIO_DIR_INPUT,
+	.gpio57 = GPIO_DIR_INPUT,
+	.gpio60 = GPIO_DIR_OUTPUT,
+	.gpio61 = GPIO_DIR_OUTPUT,
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_level = {
+	.gpio32 = GPIO_LEVEL_HIGH,
+	.gpio33 = GPIO_LEVEL_HIGH,
+	.gpio60 = GPIO_LEVEL_LOW,
+	.gpio61 = GPIO_LEVEL_HIGH,
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_reset = {
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_mode = {
+	.gpio64 = GPIO_MODE_NATIVE,
+	.gpio65 = GPIO_MODE_NATIVE,
+	.gpio66 = GPIO_MODE_NATIVE,
+	.gpio67 = GPIO_MODE_NATIVE,
+	.gpio68 = GPIO_MODE_GPIO,
+	.gpio69 = GPIO_MODE_GPIO,
+	.gpio70 = GPIO_MODE_GPIO,
+	.gpio71 = GPIO_MODE_GPIO,
+	.gpio72 = GPIO_MODE_GPIO,
+	.gpio73 = GPIO_MODE_NATIVE,
+	.gpio74 = GPIO_MODE_NATIVE,
+	.gpio75 = GPIO_MODE_NATIVE,
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_direction = {
+	.gpio68 = GPIO_DIR_INPUT,
+	.gpio69 = GPIO_DIR_INPUT,
+	.gpio70 = GPIO_DIR_INPUT,
+	.gpio71 = GPIO_DIR_INPUT,
+	.gpio72 = GPIO_DIR_INPUT,
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_level = {
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_reset = {
+};
+
+const struct pch_gpio_map mainboard_gpio_map = {
+	.set1 = {
+		.mode		= &pch_gpio_set1_mode,
+		.direction	= &pch_gpio_set1_direction,
+		.level		= &pch_gpio_set1_level,
+		.blink		= &pch_gpio_set1_blink,
+		.invert		= &pch_gpio_set1_invert,
+		.reset		= &pch_gpio_set1_reset,
+	},
+	.set2 = {
+		.mode		= &pch_gpio_set2_mode,
+		.direction	= &pch_gpio_set2_direction,
+		.level		= &pch_gpio_set2_level,
+		.reset		= &pch_gpio_set2_reset,
+	},
+	.set3 = {
+		.mode		= &pch_gpio_set3_mode,
+		.direction	= &pch_gpio_set3_direction,
+		.level		= &pch_gpio_set3_level,
+		.reset		= &pch_gpio_set3_reset,
+	},
+};
diff --git a/src/mainboard/hp/pro_3x00_series/variants/pro_3400_series/overridetree.cb b/src/mainboard/hp/pro_3x00_series/variants/pro_3400_series/overridetree.cb
new file mode 100644
index 0000000000..fbbdbf6232
--- /dev/null
+++ b/src/mainboard/hp/pro_3x00_series/variants/pro_3400_series/overridetree.cb
@@ -0,0 +1,27 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
+chip northbridge/intel/sandybridge
+	device domain 0x0 on
+		chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH
+			register "usb_port_config" = "{
+				{ 0,  6, -1 },
+				{ 1,  6,  0 },
+				{ 1,  6,  0 },
+				{ 1,  6,  1 },
+				{ 1,  6,  1 },
+				{ 1,  6,  2 },
+				{ 0,  6, -1 },
+				{ 0,  6, -1 },
+				{ 1, 12,  5 },
+				{ 1, 12,  5 },
+				{ 1, 12,  6 },
+				{ 1, 12,  6 },
+				{ 0,  6, -1 },
+				{ 0,  6, -1 },
+			}"
+
+			# Dummy device, sconfig requires at least one device per chip
+			device ref ehci1 on end
+		end
+	end
+end
diff --git a/src/mainboard/hp/pro_3500_series/board_info.txt b/src/mainboard/hp/pro_3x00_series/variants/pro_3500_series/board_info.txt
similarity index 83%
rename from src/mainboard/hp/pro_3500_series/board_info.txt
rename to src/mainboard/hp/pro_3x00_series/variants/pro_3500_series/board_info.txt
index 178039429c..5ddb210df7 100644
--- a/src/mainboard/hp/pro_3500_series/board_info.txt
+++ b/src/mainboard/hp/pro_3x00_series/variants/pro_3500_series/board_info.txt
@@ -1,6 +1,5 @@
 Category: desktop
 ROM package: SOIC-8
-ROM protocol: SPI
 ROM socketed: n
 Flashrom support: y
 Release year: 2012
diff --git a/src/mainboard/hp/pro_3500_series/data.vbt b/src/mainboard/hp/pro_3x00_series/variants/pro_3500_series/data.vbt
similarity index 100%
rename from src/mainboard/hp/pro_3500_series/data.vbt
rename to src/mainboard/hp/pro_3x00_series/variants/pro_3500_series/data.vbt
diff --git a/src/mainboard/hp/pro_3500_series/gpio.c b/src/mainboard/hp/pro_3x00_series/variants/pro_3500_series/gpio.c
similarity index 100%
rename from src/mainboard/hp/pro_3500_series/gpio.c
rename to src/mainboard/hp/pro_3x00_series/variants/pro_3500_series/gpio.c
diff --git a/src/mainboard/hp/pro_3x00_series/variants/pro_3500_series/overridetree.cb b/src/mainboard/hp/pro_3x00_series/variants/pro_3500_series/overridetree.cb
new file mode 100644
index 0000000000..9e9fa86c9c
--- /dev/null
+++ b/src/mainboard/hp/pro_3x00_series/variants/pro_3500_series/overridetree.cb
@@ -0,0 +1,27 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
+chip northbridge/intel/sandybridge
+	device domain 0x0 on
+		chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH
+			register "usb_port_config" = "{
+				{ 1,  6, 0 },
+				{ 1,  6, 0 },
+				{ 1,  6, 1 },
+				{ 1,  9, 1 },
+				{ 1, 10, 2 },
+				{ 1, 11, 2 },
+				{ 1,  6, 3 },
+				{ 1,  6, 3 },
+				{ 1,  6, 4 },
+				{ 1, 12, 4 },
+				{ 1,  6, 6 },
+				{ 1, 11, 5 },
+				{ 1,  6, 5 },
+				{ 1,  6, 6 },
+			}"
+
+			# Dummy device, sconfig requires at least one device per chip
+			device ref ehci1 on end
+		end
+	end
+end

From ddc373afabfc087e3c1dd6e5e37196d44e5f6e51 Mon Sep 17 00:00:00 2001
From: Vesek <venda.straka@gmail.com>
Date: Sat, 4 Jan 2025 02:09:59 +0100
Subject: [PATCH 0228/3886] Doc/mb/hp: Rename pro_3500_series to pro_3x00
 series

The pro_3500_series was converted to a variant to include the Pro 3400, so rename the corresponding documentation.

Change-Id: I5977f223d6f004a801e163397d1c97febd7ee1d4
Signed-off-by: Vesek <venda.straka@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85846
Reviewed-by: Nicholas Chin <nic.c3.14@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 .../hp/{pro_3500_series.md => pro_3x00_series.md}   |   4 ++--
 ...series_flash.avif => pro_3x00_series_flash.avif} | Bin
 ...ries_jumper.avif => pro_3x00_series_jumper.avif} | Bin
 Documentation/mainboard/index.md                    |   2 +-
 4 files changed, 3 insertions(+), 3 deletions(-)
 rename Documentation/mainboard/hp/{pro_3500_series.md => pro_3x00_series.md} (97%)
 rename Documentation/mainboard/hp/{pro_3500_series_flash.avif => pro_3x00_series_flash.avif} (100%)
 rename Documentation/mainboard/hp/{pro_3500_series_jumper.avif => pro_3x00_series_jumper.avif} (100%)

diff --git a/Documentation/mainboard/hp/pro_3500_series.md b/Documentation/mainboard/hp/pro_3x00_series.md
similarity index 97%
rename from Documentation/mainboard/hp/pro_3500_series.md
rename to Documentation/mainboard/hp/pro_3x00_series.md
index 3280066875..a92c4f5c3f 100644
--- a/Documentation/mainboard/hp/pro_3500_series.md
+++ b/Documentation/mainboard/hp/pro_3x00_series.md
@@ -71,7 +71,7 @@ region will be modified on shutdown. Cut the AC power or do a restart
 from the OS.
 
 **Position of FDO jumper (E2) close to the F_USB3**
-![FDO jumper position](pro_3500_series_jumper.avif)
+![FDO jumper position](pro_3x00_series_jumper.avif)
 
 ### External programming
 
@@ -83,7 +83,7 @@ The supply needs to quickly reach 3V3 or else the chip is also unstable
 until cleanly power cycled.
 
 **Position of SOIC-8 flash and pin-header near ATX power connector**
-![Flash position](pro_3500_series_flash.avif)
+![Flash position](pro_3x00_series_flash.avif)
 
 ## Technology
 
diff --git a/Documentation/mainboard/hp/pro_3500_series_flash.avif b/Documentation/mainboard/hp/pro_3x00_series_flash.avif
similarity index 100%
rename from Documentation/mainboard/hp/pro_3500_series_flash.avif
rename to Documentation/mainboard/hp/pro_3x00_series_flash.avif
diff --git a/Documentation/mainboard/hp/pro_3500_series_jumper.avif b/Documentation/mainboard/hp/pro_3x00_series_jumper.avif
similarity index 100%
rename from Documentation/mainboard/hp/pro_3500_series_jumper.avif
rename to Documentation/mainboard/hp/pro_3x00_series_jumper.avif
diff --git a/Documentation/mainboard/index.md b/Documentation/mainboard/index.md
index 177abff452..f2be295f1f 100644
--- a/Documentation/mainboard/index.md
+++ b/Documentation/mainboard/index.md
@@ -139,7 +139,7 @@ GA-H61M-S2PV <gigabyte/ga-h61m-s2pv.md>
 Compaq 8200 Elite SFF <hp/compaq_8200_sff.md>
 Compaq 8300 Elite SFF <hp/compaq_8300_sff.md>
 Compaq Elite 8300 USDT <hp/compaq_8300_usdt.md>
-Pro 3x00 Series <hp/pro_3500_series.md>
+Pro 3x00 Series <hp/pro_3x00_series.md>
 Z220 Workstation SFF <hp/z220_sff.md>
 ```
 

From 670ed107de640055a943f357486b1e68fa4b7da2 Mon Sep 17 00:00:00 2001
From: Vesek <venda.straka@gmail.com>
Date: Sat, 4 Jan 2025 02:20:42 +0100
Subject: [PATCH 0229/3886] mb/hp/pro_3x00_series: Remove unused ACPI
 brightness control

These lines are not needed because this mainboard does not have
an integrated display to control.

Tested on HP Pro 3400 Series.

Change-Id: Id39cd18713cc596eb2c92e028dad480fe7de8ef2
Signed-off-by: Vesek <venda.straka@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85847
Reviewed-by: Nicholas Chin <nic.c3.14@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/hp/pro_3x00_series/dsdt.asl | 3 ---
 1 file changed, 3 deletions(-)

diff --git a/src/mainboard/hp/pro_3x00_series/dsdt.asl b/src/mainboard/hp/pro_3x00_series/dsdt.asl
index cee4939fe0..9b86d2ac74 100644
--- a/src/mainboard/hp/pro_3x00_series/dsdt.asl
+++ b/src/mainboard/hp/pro_3x00_series/dsdt.asl
@@ -1,7 +1,5 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
-#define BRIGHTNESS_UP \_SB.PCI0.GFX0.INCB
-#define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.DECB
 #include <acpi/acpi.h>
 
 DefinitionBlock(
@@ -23,7 +21,6 @@ DefinitionBlock(
 	Device (\_SB.PCI0)
 	{
 		#include <northbridge/intel/sandybridge/acpi/sandybridge.asl>
-		#include <drivers/intel/gma/acpi/default_brightness_levels.asl>
 		#include <southbridge/intel/bd82x6x/acpi/pch.asl>
 	}
 }

From 7164abff0b5460f5621369656a81a1fbc1fe6186 Mon Sep 17 00:00:00 2001
From: Sergii Dmytruk <sergii.dmytruk@3mdeb.com>
Date: Mon, 23 Sep 2024 21:07:55 +0300
Subject: [PATCH 0230/3886] drivers/efi/capsules: check for overflows of
 capsule sizes

As was pointed out in comments on CB:83422 [0], the code lacks overflow
checks:
 - when computing size of capsules in a single capsule block
 - when computing size of capsules in all capsule blocks

If an overflow is triggered, the code might allocate a capsule buffer
smaller than the data that's going to be written to it leading to
overwriting memory after the buffer.

[0]: https://review.coreboot.org/c/coreboot/+/83422

Change-Id: I43d17d77197fc2cbd721d47941101551603c352a
Signed-off-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84541
Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/drivers/efi/capsules.c | 16 +++++++++++++++-
 1 file changed, 15 insertions(+), 1 deletion(-)

diff --git a/src/drivers/efi/capsules.c b/src/drivers/efi/capsules.c
index e674e33228..38178c618e 100644
--- a/src/drivers/efi/capsules.c
+++ b/src/drivers/efi/capsules.c
@@ -344,7 +344,15 @@ static struct block_descr check_capsule_block(struct block_descr first_block,
 			goto error;
 		}
 
-		data_size += ALIGN_UP(capsule_hdr->CapsuleImageSize, CAPSULE_ALIGNMENT);
+		uint64_t capsule_size =
+			ALIGN_UP((uint64_t)capsule_hdr->CapsuleImageSize, CAPSULE_ALIGNMENT);
+		if (data_size + capsule_size < data_size) { /* overflow detection */
+			printk(BIOS_ERR,
+			       "capsules: capsules block size is too large (%#llx + %#llx) for uint64.\n",
+			       data_size, capsule_size);
+			goto error;
+		}
+		data_size += capsule_size;
 
 		uint32_t size_left = capsule_hdr->CapsuleImageSize;
 		while (size_left != 0) {
@@ -384,6 +392,12 @@ static struct block_descr check_capsule_block(struct block_descr first_block,
 	}
 
 	/* Increase the size only on successful parsing of the capsule block. */
+	if (*total_data_size + data_size < *total_data_size) { /* overflow detection */
+		printk(BIOS_ERR,
+		       "capsules: total capsule's size is too large (%#llx + %#llx) for uint64.\n",
+		       *total_data_size, data_size);
+		goto error;
+	}
 	*total_data_size += data_size;
 
 	return block;

From 39d890073f015571652c1700bc57284fe58935cb Mon Sep 17 00:00:00 2001
From: Jeremy Compostella <jeremy.compostella@intel.com>
Date: Tue, 24 Sep 2024 11:31:05 -0700
Subject: [PATCH 0231/3886] mb/intel/ptlrvp: Add Intel Panther Lake RVP as copy
 of google/fatcat

This commit introduces the Intel Panther Lake (PTL) Reference Validation
Platform (RVP) mainboard definition. It is aligned with the Google
Fatcat mainboard in the coreboot codebase, with the commit hash
e2ea7f22c6355d15515c049ca0dc4352173a0c01.

Intel's proprietary platform, commonly referred to as PTLRVP, and
Google's Fatcat mainboard share a considerable degree of similarity in
their design and capabilities. Nevertheless, Intel faces unique
challenges and requires specific board configurations that Google does
not. Consequently, there is a necessity for a specialized mainboard
tailored to Intel's individual needs.

To maintain consistency with the Fatcat board definition, the Chrome OS
Board Information (CBI) firmware configuration aligns with that of
Google Fatcat. If necessary, new bits will be appended, starting from
the end of the 32-bit firmware configuration field.

BUG=b:398880064
TEST=The Intel PTLRVP board successfully boots to the operating System.

Change-Id: I914f73ff06bfb801fc319b45b23d7ce4cb7a6d60
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84564
Reviewed-by: Cliff Huang <cliff.huang@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
---
 src/mainboard/intel/ptlrvp/Kconfig            | 144 +++
 src/mainboard/intel/ptlrvp/Kconfig.name       |   6 +
 src/mainboard/intel/ptlrvp/Makefile.mk        |  26 +
 src/mainboard/intel/ptlrvp/board_info.txt     |   6 +
 src/mainboard/intel/ptlrvp/bootblock.c        |  13 +
 src/mainboard/intel/ptlrvp/chromeos.c         |  34 +
 src/mainboard/intel/ptlrvp/chromeos.fmd       |  50 +
 src/mainboard/intel/ptlrvp/dsdt.asl           |  42 +
 src/mainboard/intel/ptlrvp/ec.c               |  22 +
 src/mainboard/intel/ptlrvp/mainboard.c        |  74 ++
 src/mainboard/intel/ptlrvp/romstage.c         |  36 +
 src/mainboard/intel/ptlrvp/smihandler.c       |  29 +
 src/mainboard/intel/ptlrvp/spd/Makefile.mk    |   6 +
 .../baseboard/include/baseboard/variants.h    |  40 +
 .../variants/baseboard/ptlrvp/Makefile.mk     |   4 +
 .../variants/baseboard/ptlrvp/devicetree.cb   |  99 ++
 .../baseboard/ptlrvp/include/baseboard/ec.h   |  82 ++
 .../baseboard/ptlrvp/include/baseboard/gpio.h |  17 +
 .../ptlrvp/variants/baseboard/ptlrvp/memory.c |  31 +
 .../variants/baseboard/ptlrvp/ramstage.c      |  62 ++
 .../intel/ptlrvp/variants/ptlrvp/Makefile.mk  |   9 +
 .../intel/ptlrvp/variants/ptlrvp/fw_config.c  | 651 +++++++++++++
 .../intel/ptlrvp/variants/ptlrvp/gpio.c       | 419 +++++++++
 .../intel/ptlrvp/variants/ptlrvp/hda_verb.c   | 126 +++
 .../variants/ptlrvp/include/variant/ec.h      |   8 +
 .../variants/ptlrvp/include/variant/gpio.h    |  12 +
 .../intel/ptlrvp/variants/ptlrvp/memory.c     |  76 ++
 .../ptlrvp/variants/ptlrvp/memory/Makefile.mk |   7 +
 .../ptlrvp/memory/dram_id.generated.txt       |   7 +
 .../variants/ptlrvp/memory/mem_parts_used.txt |  12 +
 .../ptlrvp/variants/ptlrvp/overridetree.cb    | 890 ++++++++++++++++++
 .../intel/ptlrvp/variants/ptlrvp/variant.c    |  30 +
 32 files changed, 3070 insertions(+)
 create mode 100644 src/mainboard/intel/ptlrvp/Kconfig
 create mode 100644 src/mainboard/intel/ptlrvp/Kconfig.name
 create mode 100644 src/mainboard/intel/ptlrvp/Makefile.mk
 create mode 100644 src/mainboard/intel/ptlrvp/board_info.txt
 create mode 100644 src/mainboard/intel/ptlrvp/bootblock.c
 create mode 100644 src/mainboard/intel/ptlrvp/chromeos.c
 create mode 100644 src/mainboard/intel/ptlrvp/chromeos.fmd
 create mode 100644 src/mainboard/intel/ptlrvp/dsdt.asl
 create mode 100644 src/mainboard/intel/ptlrvp/ec.c
 create mode 100644 src/mainboard/intel/ptlrvp/mainboard.c
 create mode 100644 src/mainboard/intel/ptlrvp/romstage.c
 create mode 100644 src/mainboard/intel/ptlrvp/smihandler.c
 create mode 100644 src/mainboard/intel/ptlrvp/spd/Makefile.mk
 create mode 100644 src/mainboard/intel/ptlrvp/variants/baseboard/include/baseboard/variants.h
 create mode 100644 src/mainboard/intel/ptlrvp/variants/baseboard/ptlrvp/Makefile.mk
 create mode 100644 src/mainboard/intel/ptlrvp/variants/baseboard/ptlrvp/devicetree.cb
 create mode 100644 src/mainboard/intel/ptlrvp/variants/baseboard/ptlrvp/include/baseboard/ec.h
 create mode 100644 src/mainboard/intel/ptlrvp/variants/baseboard/ptlrvp/include/baseboard/gpio.h
 create mode 100644 src/mainboard/intel/ptlrvp/variants/baseboard/ptlrvp/memory.c
 create mode 100644 src/mainboard/intel/ptlrvp/variants/baseboard/ptlrvp/ramstage.c
 create mode 100644 src/mainboard/intel/ptlrvp/variants/ptlrvp/Makefile.mk
 create mode 100644 src/mainboard/intel/ptlrvp/variants/ptlrvp/fw_config.c
 create mode 100644 src/mainboard/intel/ptlrvp/variants/ptlrvp/gpio.c
 create mode 100644 src/mainboard/intel/ptlrvp/variants/ptlrvp/hda_verb.c
 create mode 100644 src/mainboard/intel/ptlrvp/variants/ptlrvp/include/variant/ec.h
 create mode 100644 src/mainboard/intel/ptlrvp/variants/ptlrvp/include/variant/gpio.h
 create mode 100644 src/mainboard/intel/ptlrvp/variants/ptlrvp/memory.c
 create mode 100644 src/mainboard/intel/ptlrvp/variants/ptlrvp/memory/Makefile.mk
 create mode 100644 src/mainboard/intel/ptlrvp/variants/ptlrvp/memory/dram_id.generated.txt
 create mode 100644 src/mainboard/intel/ptlrvp/variants/ptlrvp/memory/mem_parts_used.txt
 create mode 100644 src/mainboard/intel/ptlrvp/variants/ptlrvp/overridetree.cb
 create mode 100644 src/mainboard/intel/ptlrvp/variants/ptlrvp/variant.c

diff --git a/src/mainboard/intel/ptlrvp/Kconfig b/src/mainboard/intel/ptlrvp/Kconfig
new file mode 100644
index 0000000000..dd60855d3c
--- /dev/null
+++ b/src/mainboard/intel/ptlrvp/Kconfig
@@ -0,0 +1,144 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
+config BOARD_INTEL_PTLRVP_COMMON
+	def_bool n
+	select BOARD_ROMSIZE_KB_32768
+	select DRIVERS_GFX_GENERIC
+	select DRIVERS_I2C_GENERIC
+	select DRIVERS_I2C_HID
+	select DRIVERS_INTEL_DPTF
+	select DRIVERS_INTEL_MIPI_CAMERA
+	select DRIVERS_INTEL_PMC
+	select DRIVERS_INTEL_SOUNDWIRE
+	select DRIVERS_WWAN_FM350GL
+	select DRIVERS_AUDIO_SOF
+	select DRIVERS_SOUNDWIRE_ALC_BASE_7XX
+	select DRIVERS_SPI_ACPI
+	select DUMP_SMBIOS_TYPE17
+	select EC_ACPI
+	select EC_GOOGLE_CHROMEEC
+	select EC_GOOGLE_CHROMEEC_BOARDID
+	select EC_GOOGLE_CHROMEEC_ESPI
+	select EC_GOOGLE_CHROMEEC_SKUID
+	select FW_CONFIG
+	select FW_CONFIG_SOURCE_CHROMEEC_CBI
+	select GENERATE_SMBIOS_TABLES
+	select GOOGLE_SMBIOS_MAINBOARD_VERSION
+	select HAVE_ACPI_RESUME
+	select HAVE_ACPI_TABLES
+	select HAVE_SPD_IN_CBFS
+	select I2C_TPM
+	select INTEL_LPSS_UART_FOR_CONSOLE
+	select MAINBOARD_DISABLE_STAGE_CACHE
+	select MAINBOARD_HAS_TPM2
+	select MB_COMPRESS_RAMSTAGE_LZ4
+	select PMC_IPC_ACPI_INTERFACE
+	select SOC_INTEL_COMMON_BLOCK_VARIANT_POWER_LIMIT
+	select SOC_INTEL_CSE_LITE_SYNC_BY_PAYLOAD
+	select SOC_INTEL_CSE_SEND_EOP_BY_PAYLOAD
+	select SOC_INTEL_PANTHERLAKE_U_H
+	select SOC_INTEL_TCSS_USE_PDC_PMC_USBC_MUX_CONFIGURATION
+
+config BOARD_INTEL_BASEBOARD_PTLRVP
+	def_bool n
+	select BOARD_INTEL_PTLRVP_COMMON
+	select CHROMEOS_WIFI_SAR if CHROMEOS
+	select DRIVERS_INTEL_ISH
+	select DRIVER_INTEL_ISH_HAS_MAIN_FW
+	select DRIVERS_INTEL_USB4_RETIMER
+	select HAVE_SLP_S0_GATE
+	select MAINBOARD_HAS_CHROMEOS
+	select MEMORY_SOLDERDOWN
+	select SOC_INTEL_COMMON_BLOCK_HDA_VERB
+	select SOC_INTEL_IOE_DIE_SUPPORT
+	select SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES
+	select SYSTEM_TYPE_LAPTOP
+	select TPM_GOOGLE_TI50
+
+config BOARD_INTEL_MODEL_PTLRVP
+	def_bool n
+	select BOARD_INTEL_BASEBOARD_PTLRVP
+	select DRIVERS_GENERIC_BAYHUB_LV2
+	select DRIVERS_GENERIC_MAX98357A
+
+config BOARD_INTEL_PTLRVP
+	select BOARD_INTEL_MODEL_PTLRVP
+	select EC_GOOGLE_CHROMEEC_MEC
+	select MAINBOARD_USES_IFD_EC_REGION
+
+if BOARD_INTEL_PTLRVP_COMMON
+
+config BASEBOARD_DIR
+	string
+	default "ptlrvp"
+
+config CHROMEOS
+	select EC_GOOGLE_CHROMEEC_SWITCHES
+	select GBB_FLAG_DISABLE_EC_SOFTWARE_SYNC
+	select GBB_FLAG_FORCE_DEV_BOOT_USB
+	select GBB_FLAG_FORCE_MANUAL_RECOVERY
+	select HAS_RECOVERY_MRC_CACHE
+
+config CHROMEOS_WIFI_SAR
+	bool "Enable SAR options for ChromeOS build"
+	depends on CHROMEOS
+	select DSAR_ENABLE
+	select GEO_SAR_ENABLE
+	select SAR_ENABLE
+	select USE_SAR
+
+config DEVICETREE
+	default "variants/baseboard/\$(CONFIG_BASEBOARD_DIR)/devicetree.cb"
+
+config DIMM_SPD_SIZE
+	default 512
+
+config DRIVER_TPM_I2C_ADDR
+	hex
+	default 0x50
+
+config DRIVER_TPM_I2C_BUS
+	hex
+	default 0x03 if BOARD_INTEL_MODEL_PTLRVP
+
+config HAVE_SLP_S0_GATE
+	def_bool n
+
+config MAINBOARD_DIR
+	default "intel/ptlrvp"
+
+config MAINBOARD_FAMILY
+	string
+	default "Intel_Ptlrvp"
+
+config MAINBOARD_PART_NUMBER
+	default "Ptlrvp" if BOARD_INTEL_PTLRVP
+
+config MEMORY_SOLDERDOWN
+	def_bool n
+	select CHROMEOS_DRAM_PART_NUMBER_IN_CBI if CHROMEOS
+	select HAVE_SPD_IN_CBFS
+
+config TPM_TIS_ACPI_INTERRUPT
+	int
+	default 47 if BOARD_INTEL_MODEL_PTLRVP # GPE0_DW1_15 (GPP_D15)
+
+# FIXME: update as per board schematics
+config UART_FOR_CONSOLE
+	int
+	default 0
+
+config USE_PM_ACPI_TIMER
+	default n
+
+config VARIANT_DIR
+	string
+	default "ptlrvp" if BOARD_INTEL_MODEL_PTLRVP
+
+config OVERRIDE_DEVICETREE
+	default "variants/\$(CONFIG_VARIANT_DIR)/overridetree.cb"
+
+config VBOOT
+	select VBOOT_LID_SWITCH
+
+endif # BOARD_INTEL_PTLRVP_COMMON
diff --git a/src/mainboard/intel/ptlrvp/Kconfig.name b/src/mainboard/intel/ptlrvp/Kconfig.name
new file mode 100644
index 0000000000..f8d8f17dc1
--- /dev/null
+++ b/src/mainboard/intel/ptlrvp/Kconfig.name
@@ -0,0 +1,6 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
+comment "Ptlrvp"
+
+config BOARD_INTEL_PTLRVP
+	bool "-> Ptlrvp"
diff --git a/src/mainboard/intel/ptlrvp/Makefile.mk b/src/mainboard/intel/ptlrvp/Makefile.mk
new file mode 100644
index 0000000000..aea91d577a
--- /dev/null
+++ b/src/mainboard/intel/ptlrvp/Makefile.mk
@@ -0,0 +1,26 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
+bootblock-y += bootblock.c
+
+verstage-$(CONFIG_CHROMEOS) += chromeos.c
+
+romstage-y += romstage.c
+romstage-$(CONFIG_CHROMEOS) += chromeos.c
+
+ramstage-y += mainboard.c
+ramstage-$(CONFIG_CHROMEOS) += chromeos.c
+ramstage-y += ec.c
+ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_HDA_VERB) += variants/$(VARIANT_DIR)/hda_verb.c
+
+smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c
+
+BASEBOARD_DIR:=$(call strip_quotes,$(CONFIG_BASEBOARD_DIR))
+
+subdirs-y += variants/baseboard/$(BASEBOARD_DIR)
+subdirs-y += variants/$(VARIANT_DIR)
+subdirs-y += variants/$(VARIANT_DIR)/memory
+subdirs-$(CONFIG_HAVE_SPD_IN_CBFS) += spd
+
+CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/baseboard/include
+CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/baseboard/$(BASEBOARD_DIR)/include
+CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/include
diff --git a/src/mainboard/intel/ptlrvp/board_info.txt b/src/mainboard/intel/ptlrvp/board_info.txt
new file mode 100644
index 0000000000..c7de62f6c6
--- /dev/null
+++ b/src/mainboard/intel/ptlrvp/board_info.txt
@@ -0,0 +1,6 @@
+Vendor name: Intel
+Board name: Ptlrvp
+Category: laptop
+ROM protocol: SPI
+ROM socketed: n
+Flashrom support: y
diff --git a/src/mainboard/intel/ptlrvp/bootblock.c b/src/mainboard/intel/ptlrvp/bootblock.c
new file mode 100644
index 0000000000..6ee655ee58
--- /dev/null
+++ b/src/mainboard/intel/ptlrvp/bootblock.c
@@ -0,0 +1,13 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <baseboard/variants.h>
+#include <bootblock_common.h>
+
+void bootblock_mainboard_early_init(void)
+{
+	const struct pad_config *pads;
+	size_t num;
+
+	pads = variant_early_gpio_table(&num);
+	gpio_configure_pads(pads, num);
+}
diff --git a/src/mainboard/intel/ptlrvp/chromeos.c b/src/mainboard/intel/ptlrvp/chromeos.c
new file mode 100644
index 0000000000..5ed041f52b
--- /dev/null
+++ b/src/mainboard/intel/ptlrvp/chromeos.c
@@ -0,0 +1,34 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <baseboard/gpio.h>
+#include <bootmode.h>
+#include <boot/coreboot_tables.h>
+#include <gpio.h>
+#include <types.h>
+
+void fill_lb_gpios(struct lb_gpios *gpios)
+{
+	struct lb_gpio chromeos_gpios[] = {
+#if CONFIG(VBOOT_LID_SWITCH)
+		{-1, ACTIVE_HIGH, get_lid_switch(), "lid"},
+#else
+		/* fake LID open to avoid shutdown in depthcharge */
+		{-1, ACTIVE_HIGH, 1, "lid"},
+#endif
+		{-1, ACTIVE_HIGH, 0, "power"},
+		{-1, ACTIVE_HIGH, gfx_get_init_done(), "oprom"},
+		{-1, ACTIVE_HIGH, 0, "EC in RW"},
+	};
+	lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios));
+}
+
+int get_write_protect_state(void)
+{
+	return gpio_get(GPIO_PCH_WP);
+}
+
+int get_ec_is_trusted(void)
+{
+	/* VB2_CONTEXT_EC_TRUSTED should be set according to the Ti50 boot mode. */
+	return 0;
+}
diff --git a/src/mainboard/intel/ptlrvp/chromeos.fmd b/src/mainboard/intel/ptlrvp/chromeos.fmd
new file mode 100644
index 0000000000..693f485e4a
--- /dev/null
+++ b/src/mainboard/intel/ptlrvp/chromeos.fmd
@@ -0,0 +1,50 @@
+FLASH 32M {
+	SI_ALL 8M {
+		SI_DESC 16K
+		SI_EC 576K
+		SI_ME
+	}
+	SI_BIOS 24M {
+		RW_SECTION_A 8M {
+			VBLOCK_A 8K
+			FW_MAIN_A(CBFS)
+			RW_FWID_A 64
+		}
+		# This section starts at the 16M boundary in SPI flash.
+		# PTL does not support a region crossing this boundary,
+		# because the SPI flash is memory-mapped into two non-
+		# contiguous windows.
+		RW_SECTION_B 8M {
+			VBLOCK_B 8K
+			FW_MAIN_B(CBFS)
+			RW_FWID_B 64
+		}
+		RW_MISC 1M {
+			UNIFIED_MRC_CACHE(PRESERVE) 128K {
+				RECOVERY_MRC_CACHE 64K
+				RW_MRC_CACHE 64K
+			}
+			RW_ELOG(PRESERVE) 16K
+			RW_SHARED 16K {
+				SHARED_DATA 8K
+				VBLOCK_DEV 8K
+			}
+			RW_VPD(PRESERVE) 8K
+			RW_NVRAM(PRESERVE) 24K
+		}
+		RW_LEGACY(CBFS) 1M
+		RW_UNUSED 2M
+		# Make WP_RO region align with SPI vendor
+		# memory protected range specification.
+		WP_RO 4M {
+			RO_VPD(PRESERVE) 16K
+			RO_GSCVD 8K
+			RO_SECTION {
+				FMAP 2K
+				RO_FRID 64
+				GBB@4K 12K
+				COREBOOT(CBFS)
+			}
+		}
+	}
+}
diff --git a/src/mainboard/intel/ptlrvp/dsdt.asl b/src/mainboard/intel/ptlrvp/dsdt.asl
new file mode 100644
index 0000000000..03882c6327
--- /dev/null
+++ b/src/mainboard/intel/ptlrvp/dsdt.asl
@@ -0,0 +1,42 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <acpi/acpi.h>
+#include <variant/ec.h>
+#include <variant/gpio.h>
+
+DefinitionBlock(
+	"dsdt.aml",
+	"DSDT",
+	ACPI_DSDT_REV_2,
+	OEM_ID,
+	ACPI_TABLE_CREATOR,
+	0x20240917
+)
+{
+	#include <acpi/dsdt_top.asl>
+	#include <soc/intel/common/block/acpi/acpi/platform.asl>
+
+	/* global NVS and variables */
+	#include <soc/intel/common/block/acpi/acpi/globalnvs.asl>
+
+	#include <cpu/intel/common/acpi/cpu.asl>
+
+	Device (\_SB.PCI0) {
+		#include <soc/intel/common/block/acpi/acpi/northbridge.asl>
+		#include <soc/intel/pantherlake/acpi/southbridge.asl>
+		#include <soc/intel/pantherlake/acpi/tcss.asl>
+	}
+
+#if CONFIG(EC_GOOGLE_CHROMEEC)
+	/* ChromeOS Embedded Controller */
+	Scope (\_SB.PCI0.LPCB)
+	{
+		/* ACPI code for EC SuperIO functions */
+		#include <ec/google/chromeec/acpi/superio.asl>
+		/* ACPI code for EC functions */
+		#include <ec/google/chromeec/acpi/ec.asl>
+	}
+#endif
+
+	#include <southbridge/intel/common/acpi/sleepstates.asl>
+}
diff --git a/src/mainboard/intel/ptlrvp/ec.c b/src/mainboard/intel/ptlrvp/ec.c
new file mode 100644
index 0000000000..f828bc5547
--- /dev/null
+++ b/src/mainboard/intel/ptlrvp/ec.c
@@ -0,0 +1,22 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <acpi/acpi.h>
+#include <console/console.h>
+#include <ec/ec.h>
+#include <ec/google/chromeec/ec.h>
+#include <variant/ec.h>
+
+void mainboard_ec_init(void)
+{
+	static const struct google_chromeec_event_info info = {
+		.log_events = MAINBOARD_EC_LOG_EVENTS,
+		.sci_events = MAINBOARD_EC_SCI_EVENTS,
+		.s3_wake_events = MAINBOARD_EC_S3_WAKE_EVENTS,
+		.s5_wake_events = MAINBOARD_EC_S5_WAKE_EVENTS,
+		.s0ix_wake_events = MAINBOARD_EC_S0IX_WAKE_EVENTS,
+	};
+
+	printk(BIOS_DEBUG, "mainboard: EC init\n");
+
+	google_chromeec_events_init(&info, acpi_is_wakeup_s3());
+}
diff --git a/src/mainboard/intel/ptlrvp/mainboard.c b/src/mainboard/intel/ptlrvp/mainboard.c
new file mode 100644
index 0000000000..f514eb96d1
--- /dev/null
+++ b/src/mainboard/intel/ptlrvp/mainboard.c
@@ -0,0 +1,74 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <acpi/acpi.h>
+#include <acpi/acpigen.h>
+#include <baseboard/gpio.h>
+#include <baseboard/variants.h>
+#include <device/device.h>
+#include <ec/ec.h>
+#include <soc/ramstage.h>
+#include <stdlib.h>
+#include <vendorcode/google/chromeos/chromeos.h>
+
+void __weak fw_config_gpio_padbased_override(struct pad_config *padbased_table)
+{
+	/* default implementation does nothing */
+}
+
+void mainboard_update_soc_chip_config(struct soc_intel_pantherlake_config *config)
+{
+	variant_update_soc_chip_config(config);
+}
+
+void __weak variant_update_soc_chip_config(struct soc_intel_pantherlake_config *config)
+{
+	/* default implementation does nothing */
+}
+
+static void mainboard_init(void *chip_info)
+{
+	struct pad_config *padbased_table;
+	const struct pad_config *base_pads;
+	size_t base_num;
+
+	padbased_table = new_padbased_table();
+	base_pads = variant_gpio_table(&base_num);
+	gpio_padbased_override(padbased_table, base_pads, base_num);
+	fw_config_gpio_padbased_override(padbased_table);
+	gpio_configure_pads_with_padbased(padbased_table);
+	free(padbased_table);
+	baseboard_devtree_update();
+}
+
+void __weak baseboard_devtree_update(void)
+{
+	/* Override dev tree settings per baseboard */
+}
+
+void __weak variant_generate_s0ix_hook(enum s0ix_entry entry)
+{
+	/* Add board-specific MS0X entries */
+	/*
+	   if (s0ix_entry == S0IX_ENTRY) {
+		implement variant operations here
+	   }
+	   if (s0ix_entry == S0IX_EXIT) {
+		implement variant operations here
+	   }
+	 */
+}
+
+static void mainboard_dev_init(struct device *dev)
+{
+	mainboard_ec_init();
+}
+
+static void mainboard_enable(struct device *dev)
+{
+	dev->ops->init = mainboard_dev_init;
+}
+
+struct chip_operations mainboard_ops = {
+	.init = mainboard_init,
+	.enable_dev = mainboard_enable,
+};
diff --git a/src/mainboard/intel/ptlrvp/romstage.c b/src/mainboard/intel/ptlrvp/romstage.c
new file mode 100644
index 0000000000..7b56e28e3c
--- /dev/null
+++ b/src/mainboard/intel/ptlrvp/romstage.c
@@ -0,0 +1,36 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <baseboard/variants.h>
+#include <fsp/api.h>
+#include <soc/romstage.h>
+#include <string.h>
+
+/*
+ * Placeholder to configure GPIO early from romstage relying on the FW_CONFIG.
+ *
+ * If any platform would like to override early GPIOs, they should override from
+ * the variant directory.
+ */
+__weak void fw_config_configure_pre_mem_gpio(void)
+{
+	/* Nothing to do */
+}
+
+void mainboard_memory_init_params(FSPM_UPD *memupd)
+{
+	const struct pad_config *pads;
+	size_t pads_num;
+	const struct mb_cfg *mem_config = variant_memory_params();
+	bool half_populated = variant_is_half_populated();
+	struct mem_spd spd_info;
+
+	pads = variant_romstage_gpio_table(&pads_num);
+	if (pads_num)
+		gpio_configure_pads(pads, pads_num);
+	fw_config_configure_pre_mem_gpio();
+
+	memset(&spd_info, 0, sizeof(spd_info));
+	variant_get_spd_info(&spd_info);
+
+	memcfg_init(memupd, mem_config, &spd_info, half_populated);
+}
diff --git a/src/mainboard/intel/ptlrvp/smihandler.c b/src/mainboard/intel/ptlrvp/smihandler.c
new file mode 100644
index 0000000000..9208d51613
--- /dev/null
+++ b/src/mainboard/intel/ptlrvp/smihandler.c
@@ -0,0 +1,29 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <cpu/x86/smm.h>
+#include <ec/google/chromeec/ec.h>
+#include <ec/google/chromeec/smm.h>
+#include <elog.h>
+#include <intelblocks/smihandler.h>
+#include <variant/ec.h>
+
+void mainboard_smi_sleep(u8 slp_typ)
+{
+	chromeec_smi_sleep(slp_typ, MAINBOARD_EC_S3_WAKE_EVENTS, MAINBOARD_EC_S5_WAKE_EVENTS);
+}
+
+int mainboard_smi_apmc(u8 apmc)
+{
+	chromeec_smi_apmc(apmc, MAINBOARD_EC_SCI_EVENTS, MAINBOARD_EC_SMI_EVENTS);
+	return 0;
+}
+
+void elog_gsmi_cb_mainboard_log_wake_source(void)
+{
+	google_chromeec_log_events(MAINBOARD_EC_LOG_EVENTS | MAINBOARD_EC_S0IX_WAKE_EVENTS);
+}
+
+void mainboard_smi_espi_handler(void)
+{
+	chromeec_smi_process_events();
+}
diff --git a/src/mainboard/intel/ptlrvp/spd/Makefile.mk b/src/mainboard/intel/ptlrvp/spd/Makefile.mk
new file mode 100644
index 0000000000..be4d98bd1d
--- /dev/null
+++ b/src/mainboard/intel/ptlrvp/spd/Makefile.mk
@@ -0,0 +1,6 @@
+## SPDX-License-Identifier: GPL-2.0-or-later
+##
+
+ifneq ($(SPD_SOURCES),)
+LIB_SPD_DEPS := $(SPD_SOURCES)
+endif
diff --git a/src/mainboard/intel/ptlrvp/variants/baseboard/include/baseboard/variants.h b/src/mainboard/intel/ptlrvp/variants/baseboard/include/baseboard/variants.h
new file mode 100644
index 0000000000..2a70408e0d
--- /dev/null
+++ b/src/mainboard/intel/ptlrvp/variants/baseboard/include/baseboard/variants.h
@@ -0,0 +1,40 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#ifndef __BASEBOARD_VARIANTS_H__
+#define __BASEBOARD_VARIANTS_H__
+
+#include <chip.h>
+#include <soc/gpio.h>
+#include <soc/meminit.h>
+#include <stdint.h>
+#include <vendorcode/google/chromeos/chromeos.h>
+
+/* The next set of functions return the gpio table and fill in the number of entries for
+ * each table.
+ */
+
+const struct pad_config *variant_gpio_table(size_t *num);
+const struct pad_config *variant_early_gpio_table(size_t *num);
+const struct pad_config *variant_romstage_gpio_table(size_t *num);
+void fw_config_configure_pre_mem_gpio(void);
+void fw_config_gpio_padbased_override(struct pad_config *padbased_table);
+
+const struct mb_cfg *variant_memory_params(void);
+void variant_get_spd_info(struct mem_spd *spd_info);
+int variant_memory_sku(void);
+bool variant_is_half_populated(void);
+void variant_update_soc_chip_config(struct soc_intel_pantherlake_config *config);
+
+enum s0ix_entry {
+	S0IX_EXIT,
+	S0IX_ENTRY,
+};
+
+void variant_generate_s0ix_hook(enum s0ix_entry entry);
+
+/* Modify devictree settings during ramstage by baseboard */
+void baseboard_devtree_update(void);
+/* Modify devictree settings during ramstage by dedicated variant */
+void variant_devtree_update(void);
+
+#endif /*__BASEBOARD_VARIANTS_H__ */
diff --git a/src/mainboard/intel/ptlrvp/variants/baseboard/ptlrvp/Makefile.mk b/src/mainboard/intel/ptlrvp/variants/baseboard/ptlrvp/Makefile.mk
new file mode 100644
index 0000000000..47123cd318
--- /dev/null
+++ b/src/mainboard/intel/ptlrvp/variants/baseboard/ptlrvp/Makefile.mk
@@ -0,0 +1,4 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
+romstage-y += memory.c
+ramstage-y += ramstage.c
diff --git a/src/mainboard/intel/ptlrvp/variants/baseboard/ptlrvp/devicetree.cb b/src/mainboard/intel/ptlrvp/variants/baseboard/ptlrvp/devicetree.cb
new file mode 100644
index 0000000000..2cf249f9aa
--- /dev/null
+++ b/src/mainboard/intel/ptlrvp/variants/baseboard/ptlrvp/devicetree.cb
@@ -0,0 +1,99 @@
+chip soc/intel/pantherlake
+	# GPE configuration
+	register "pmc_gpe0_dw0" = "GPP_A"
+	register "pmc_gpe0_dw1" = "GPP_D"
+	register "pmc_gpe0_dw2" = "GPP_E"
+
+	# For Ptlrvp variants with microchip EC:
+	#	EC host command ranges are in 0x800-0x807 & 0x200-0x20f
+	# For Ptlrvp variants with ITE/Nuvoton EC:
+	# 	EC host command ranges are in 0x800-0x8ff & 0x200-0x20f
+	register "gen1_dec" = "CONFIG(BOARD_INTEL_PTLRVP) ? 0x00040801 : 0x00fc0801"
+	register "gen2_dec" = "0x000c0201"
+	# EC memory map range is 0x900-0x9ff
+	register "gen3_dec" = "0x00fc0901"
+
+	register "usb2_ports[0]" = "USB2_PORT_EMPTY"	# Disable USB2.0 Port 0
+	register "usb2_ports[1]" = "USB2_PORT_EMPTY"	# Disable USB2.0 Port 1
+	register "usb2_ports[2]" = "USB2_PORT_EMPTY"	# Disable USB2.0 Port 2
+	register "usb2_ports[3]" = "USB2_PORT_EMPTY"	# Disable USB2.0 Port 3
+	register "usb2_ports[4]" = "USB2_PORT_EMPTY"	# Disable USB2.0 Port 4
+	register "usb2_ports[5]" = "USB2_PORT_EMPTY"	# Disable USB2.0 Port 5
+	register "usb2_ports[6]" = "USB2_PORT_EMPTY"	# Disable USB2.0 Port 6
+	register "usb2_ports[7]" = "USB2_PORT_EMPTY"	# Disable USB2.0 Port 7
+
+	register "usb3_ports[0]" = "USB3_PORT_EMPTY"	# Disable USB3.0 Port 0
+	register "usb3_ports[1]" = "USB3_PORT_EMPTY"	# Disable USB3.0 Port 1
+
+	register "tcss_ports[0]" = "TCSS_PORT_EMPTY"	# Disable USB-C Port 0
+	register "tcss_ports[1]" = "TCSS_PORT_EMPTY"	# Disable USB-C Port 1
+	register "tcss_ports[2]" = "TCSS_PORT_EMPTY"	# Disable USB-C Port 2
+	register "tcss_ports[3]" = "TCSS_PORT_EMPTY"	# Disable USB-C Port 3
+
+	# Enable SAGv
+	register "sagv" = "SAGV_ENABLED"
+
+	register "sagv_freq_mhz[0]" = "2400"
+	register "sagv_gear[0]" = "GEAR_4"
+
+	register "sagv_freq_mhz[1]" = "3200"
+	register "sagv_gear[1]" = "GEAR_4"
+
+	register "sagv_freq_mhz[2]" = "6000"
+	register "sagv_gear[2]" = "GEAR_4"
+
+	register "sagv_freq_mhz[3]" = "6400"
+	register "sagv_gear[3]" = "GEAR_4"
+
+	# Enable s0ix
+	register "s0ix_enable" = "true"
+
+	# DPTF enable
+	register "dptf_enable" = "true"
+
+	# Setting TCC of 100C = Tj max (110) - TCC_Offset (10)
+	register "tcc_offset" = "10"
+
+	# Disable C1 C-state auto-demotion
+	register "disable_c1_state_auto_demotion" = "true"
+	# Disable PKGC-state auto-demotion
+	register "disable_package_c_state_demotion" = "true"
+
+	# Enable Energy Reporting
+	register "pch_pm_energy_report_enable" = "true"
+
+	# Enable CNVi BT
+	register "cnvi_bt_core" = "true"
+
+	register "serial_io_uart_mode" = "{
+		[PchSerialIoIndexUART0] = PchSerialIoSkipInit,
+		[PchSerialIoIndexUART1] = PchSerialIoDisabled,
+		[PchSerialIoIndexUART2] = PchSerialIoDisabled,
+	}"
+
+	register "serial_io_gspi_mode" = "{
+		[PchSerialIoIndexGSPI0] = PchSerialIoPci,
+		[PchSerialIoIndexGSPI1] = PchSerialIoPci,
+		[PchSerialIoIndexGSPI0A] = PchSerialIoPci,
+	}"
+
+	register "pch_hda_dsp_enable" = "true"
+	register "pch_hda_idisp_link_tmode" = "HDA_TMODE_8T"
+	register "pch_hda_idisp_link_frequency" = "HDA_LINKFREQ_96MHZ"
+	register "pch_hda_idisp_codec_enable" = "true"
+	register "pch_hda_sdi_enable" = "{ true, false }"
+
+	device domain 0 on
+		device ref dtt on end
+		device ref npu on end
+		device ref xhci on end
+		device ref pmc_shared_sram on end
+		device ref heci1 on end
+		device ref uart0 on end
+		device ref soc_espi on
+			chip ec/google/chromeec
+				device pnp 0c09.0 on end
+			end
+		end
+	end
+end
diff --git a/src/mainboard/intel/ptlrvp/variants/baseboard/ptlrvp/include/baseboard/ec.h b/src/mainboard/intel/ptlrvp/variants/baseboard/ptlrvp/include/baseboard/ec.h
new file mode 100644
index 0000000000..f3e31b0448
--- /dev/null
+++ b/src/mainboard/intel/ptlrvp/variants/baseboard/ptlrvp/include/baseboard/ec.h
@@ -0,0 +1,82 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#ifndef __BASEBOARD_EC_H__
+#define __BASEBOARD_EC_H__
+
+#include <baseboard/gpio.h>
+#include <ec/ec.h>
+#include <ec/google/chromeec/ec_commands.h>
+
+#define MAINBOARD_EC_SCI_EVENTS \
+	(EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_CONNECTED)      |\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_DISCONNECTED)   |\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY)           |\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_CRITICAL)  |\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_LOW)       |\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_STATUS)    |\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED)        |\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN)          |\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_MKBP)              |\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_MODE_CHANGE)       |\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_PD_MCU)            |\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_THRESHOLD) |\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_START)    |\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_STOP)     |\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_USB_MUX))
+#define MAINBOARD_EC_SMI_EVENTS \
+	(EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED))
+/* EC can wake from S5 with lid or power button */
+#define MAINBOARD_EC_S5_WAKE_EVENTS \
+	(EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN)     |\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_POWER_BUTTON))
+/*
+ * EC can wake from S3/S0ix with:
+ * 1. Lid open
+ * 2. AC Connect/Disconnect
+ * 3. Power button
+ * 4. Key press
+ * 5. Mode change
+ * 6. Low battery
+ */
+#define MAINBOARD_EC_S3_WAKE_EVENTS \
+	(EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_CONNECTED)     | \
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_DISCONNECTED)  | \
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_CRITICAL) | \
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_SHUTDOWN) | \
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEY_PRESSED)      | \
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_MODE_CHANGE)      | \
+	 MAINBOARD_EC_S5_WAKE_EVENTS)
+#define MAINBOARD_EC_S0IX_WAKE_EVENTS \
+	(EC_HOST_EVENT_MASK(EC_HOST_EVENT_HANG_DETECT) | \
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_USB_MUX)         | \
+	 MAINBOARD_EC_S3_WAKE_EVENTS)
+/* Log EC wake events plus EC shutdown events */
+#define MAINBOARD_EC_LOG_EVENTS \
+	(EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_SHUTDOWN) |\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_PANIC) |\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_SHUTDOWN))
+/*
+ * ACPI related definitions for ASL code.
+ */
+
+/* Enable EC backed ALS device in ACPI */
+#define EC_ENABLE_ALS_DEVICE
+
+/* Enable Keyboard Backlight */
+#define EC_ENABLE_KEYBOARD_BACKLIGHT
+
+/* Enable LID switch and provide wake pin for EC */
+#define EC_ENABLE_LID_SWITCH
+#define EC_ENABLE_WAKE_PIN      GPE_EC_WAKE
+
+/* Enable MKBP for buttons and switches */
+#define EC_ENABLE_MKBP_DEVICE
+
+/* Enable EC backed PD MCU device in ACPI */
+#define EC_ENABLE_PD_MCU_DEVICE
+
+#define SIO_EC_ENABLE_PS2K       /* Enable PS/2 Keyboard */
+#define SIO_EC_HOST_ENABLE       /* EC Host Interface Resources */
+#define SIO_EC_MEMMAP_ENABLE     /* EC Memory Map Resources */
+
+#endif /* __BASEBOARD_EC_H__ */
diff --git a/src/mainboard/intel/ptlrvp/variants/baseboard/ptlrvp/include/baseboard/gpio.h b/src/mainboard/intel/ptlrvp/variants/baseboard/ptlrvp/include/baseboard/gpio.h
new file mode 100644
index 0000000000..5a77e4eb2c
--- /dev/null
+++ b/src/mainboard/intel/ptlrvp/variants/baseboard/ptlrvp/include/baseboard/gpio.h
@@ -0,0 +1,17 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#ifndef __BASEBOARD_GPIO_H__
+#define __BASEBOARD_GPIO_H__
+
+#include <soc/gpe.h>
+#include <soc/gpio.h>
+
+/* FIXME: update below code as per board schematics */
+/* eSPI virtual wire reporting */
+#define EC_SCI_GPI	GPE0_ESPI
+/* GPIO IRQ for tight timestamps / wake support */
+#define EC_SYNC_IRQ	0
+/* WP signal to PCH */
+#define GPIO_PCH_WP	0
+
+#endif /* __BASEBOARD_GPIO_H__ */
diff --git a/src/mainboard/intel/ptlrvp/variants/baseboard/ptlrvp/memory.c b/src/mainboard/intel/ptlrvp/variants/baseboard/ptlrvp/memory.c
new file mode 100644
index 0000000000..4f621f38ce
--- /dev/null
+++ b/src/mainboard/intel/ptlrvp/variants/baseboard/ptlrvp/memory.c
@@ -0,0 +1,31 @@
+/* SPDX-License-Identifier: GPL-3.0-or-later */
+
+#include <baseboard/variants.h>
+
+static const struct mb_cfg baseboard_memcfg = {
+	.type = MEM_TYPE_LP5X,
+
+	/* TODO: Add Memory configuration */
+	.ect = 1, /* Early Command Training */
+};
+
+const struct mb_cfg *__weak variant_memory_params(void)
+{
+	return &baseboard_memcfg;
+}
+
+int __weak variant_memory_sku(void)
+{
+	return 0;
+}
+
+bool __weak variant_is_half_populated(void)
+{
+	return 0;
+}
+
+void __weak variant_get_spd_info(struct mem_spd *spd_info)
+{
+	spd_info->topo = MEM_TOPO_MEMORY_DOWN;
+	spd_info->cbfs_index = variant_memory_sku();
+}
diff --git a/src/mainboard/intel/ptlrvp/variants/baseboard/ptlrvp/ramstage.c b/src/mainboard/intel/ptlrvp/variants/baseboard/ptlrvp/ramstage.c
new file mode 100644
index 0000000000..030b587579
--- /dev/null
+++ b/src/mainboard/intel/ptlrvp/variants/baseboard/ptlrvp/ramstage.c
@@ -0,0 +1,62 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <baseboard/variants.h>
+#include <ec/google/chromeec/ec.h>
+
+/*
+ * SKU_ID, TDP (Watts), pl1_min (milliWatts), pl1_max (milliWatts),
+ * pl2_min (milliWatts), pl2_max (milliWatts), pl4 (milliWatts)
+ */
+const struct cpu_tdp_power_limits power_optimized_limits[] = {
+	{
+		.mch_id = PCI_DID_INTEL_PTL_H_ID_1,
+		.cpu_tdp = TDP_25W,
+		.power_limits_index = PTL_H_1_CORE,
+		.pl1_min_power = 10000,
+		.pl1_max_power = 25000,
+		.pl2_min_power = 50000,
+		.pl2_max_power = 50000,
+		.pl4_power = 65000
+	},
+	{
+		.mch_id = PCI_DID_INTEL_PTL_H_ID_2,
+		.cpu_tdp = TDP_25W,
+		.power_limits_index = PTL_H_1_CORE,
+		.pl1_min_power = 10000,
+		.pl1_max_power = 25000,
+		.pl2_min_power = 50000,
+		.pl2_max_power = 50000,
+		.pl4_power = 65000
+	},
+	{
+		.mch_id = PCI_DID_INTEL_PTL_H_ID_3,
+		.cpu_tdp = TDP_25W,
+		.power_limits_index = PTL_H_2_CORE,
+		.pl1_min_power = 10000,
+		.pl1_max_power = 25000,
+		.pl2_min_power = 50000,
+		.pl2_max_power = 50000,
+		.pl4_power = 65000
+	},
+	{
+		.mch_id = PCI_DID_INTEL_PTL_H_ID_4,
+		.cpu_tdp = TDP_25W,
+		.power_limits_index = PTL_H_2_CORE,
+		.pl1_min_power = 10000,
+		.pl1_max_power = 25000,
+		.pl2_min_power = 50000,
+		.pl2_max_power = 50000,
+		.pl4_power = 65000
+	},
+};
+
+void baseboard_devtree_update(void)
+{
+	/* Don't optimize the power limit if booting with barrel attached */
+	if (google_chromeec_is_barrel_charger_present())
+		return;
+
+	if (!google_chromeec_is_battery_present())
+		variant_update_cpu_power_limits(power_optimized_limits,
+						ARRAY_SIZE(power_optimized_limits));
+}
diff --git a/src/mainboard/intel/ptlrvp/variants/ptlrvp/Makefile.mk b/src/mainboard/intel/ptlrvp/variants/ptlrvp/Makefile.mk
new file mode 100644
index 0000000000..eb361dfe89
--- /dev/null
+++ b/src/mainboard/intel/ptlrvp/variants/ptlrvp/Makefile.mk
@@ -0,0 +1,9 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
+bootblock-y += gpio.c
+romstage-y += gpio.c
+romstage-y += memory.c
+romstage-$(CONFIG_FW_CONFIG) += fw_config.c
+ramstage-y += gpio.c
+ramstage-$(CONFIG_FW_CONFIG) += variant.c
+ramstage-$(CONFIG_FW_CONFIG) += fw_config.c
diff --git a/src/mainboard/intel/ptlrvp/variants/ptlrvp/fw_config.c b/src/mainboard/intel/ptlrvp/variants/ptlrvp/fw_config.c
new file mode 100644
index 0000000000..9419caf709
--- /dev/null
+++ b/src/mainboard/intel/ptlrvp/variants/ptlrvp/fw_config.c
@@ -0,0 +1,651 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <baseboard/variants.h>
+#include <console/console.h>
+#include <fw_config.h>
+#include <gpio.h>
+#include <inttypes.h>
+
+/* t: base table; o: override table */
+#define GPIO_PADBASED_OVERRIDE(t, o) gpio_padbased_override(t, o, ARRAY_SIZE(o))
+/* t: table */
+#define GPIO_CONFIGURE_PADS(t) gpio_configure_pads(t, ARRAY_SIZE(t))
+
+static const struct pad_config i2s_enable_pads[] = {
+	/* I2S_MCLK1_OUT */
+	PAD_CFG_NF(GPP_D09, NONE, DEEP, NF2),
+	/* I2S0_SCLK_HDR */
+	PAD_CFG_NF(GPP_D10, NONE, DEEP, NF2),
+	/* I2S0_SFRM_HDR */
+	PAD_CFG_NF(GPP_D11, NONE, DEEP, NF2),
+	/* I2S0_TXD_HDR */
+	PAD_CFG_NF(GPP_D12, NONE, DEEP, NF2),
+	/* I2S0_RXD_HDR */
+	PAD_CFG_NF(GPP_D13, NONE, DEEP, NF2),
+	/* I2S1_SCLK_HDR */
+	PAD_CFG_NF(GPP_S00, NONE, DEEP, NF6),
+	/* I2S1_SFRM_HDR */
+	PAD_CFG_NF(GPP_S01, NONE, DEEP, NF6),
+	/* I2S1_TXD_HDR */
+	PAD_CFG_NF(GPP_S02, NONE, DEEP, NF6),
+	/* I2S1_RXD_HDR */
+	PAD_CFG_NF(GPP_S03, NONE, DEEP, NF6),
+
+	/* DMIC_CLK */
+	PAD_CFG_NF(GPP_D16, NONE, DEEP, NF3),
+	/* DMIC_DATA */
+	PAD_CFG_NF(GPP_D17, NONE, DEEP, NF3),
+
+	/* DMIC_CLK */
+	PAD_CFG_NF(GPP_S04, NONE, DEEP, NF5),
+	/* DMIC_DATA */
+	PAD_CFG_NF(GPP_S05, NONE, DEEP, NF5),
+};
+
+static const struct pad_config hda_enable_pads[] = {
+	/* HDA_BCLK */
+	PAD_CFG_NF(GPP_D10, NONE, DEEP, NF1),
+	/* HDA_SYNC */
+	PAD_CFG_NF(GPP_D11, NATIVE, DEEP, NF1),
+	/* HDA_SDO */
+	PAD_CFG_NF(GPP_D12, NATIVE, DEEP, NF1),
+	/* HDA_SDI_0 */
+	PAD_CFG_NF(GPP_D13, NATIVE, DEEP, NF1),
+	/* HDA_RST_B */
+	PAD_CFG_NF(GPP_D16, NONE, DEEP, NF1),
+	/* HDA_SDI_1 */
+	PAD_CFG_NF(GPP_D17, NATIVE, DEEP, NF1),
+
+	/* DMIC_CLK */
+	PAD_CFG_NF(GPP_S04, NONE, DEEP, NF5),
+	/* DMIC_DATA */
+	PAD_CFG_NF(GPP_S05, NONE, DEEP, NF5),
+};
+
+static const struct pad_config sndw_external_codec_enable_pads[] = {
+	/* Soundwire - External codec - JE Header */
+	/* SNDW3_CLK */
+	PAD_CFG_NF(GPP_S00, NONE, DEEP, NF1),
+	/* SNDW3_DATA0 */
+	PAD_CFG_NF(GPP_S01, NONE, DEEP, NF1),
+	/* SNDW0_CLK */
+	PAD_CFG_NF(GPP_S02, NONE, DEEP, NF3),
+	/* SNDW0_DATA */
+	PAD_CFG_NF(GPP_S03, NONE, DEEP, NF3),
+	/* SNDW2_CLK */
+	PAD_CFG_NF(GPP_S04, NONE, DEEP, NF2),
+	/* SNDW2_DATA */
+	PAD_CFG_NF(GPP_S05, NONE, DEEP, NF2),
+	/* SNDW1_CLK */
+	PAD_CFG_NF(GPP_S06, NONE, DEEP, NF3),
+	/* SNDW1_DATA */
+	PAD_CFG_NF(GPP_S07, NONE, DEEP, NF3),
+
+	/* GPP_D13: RST_HP_L */
+	PAD_CFG_GPO(GPP_D13, 1, PLTRST),
+};
+
+static const struct pad_config bt_i2s_enable_pads[] = {
+	/* GPP_V30 : [] ==> BT_I2S_BCLK - SSP2 */
+	PAD_CFG_NF(GPP_VGPIO30, NONE, DEEP, NF3),
+	/* GPP_V31 : [] ==> BT_I2S_SYNC - SSP2 */
+	PAD_CFG_NF(GPP_VGPIO31, NONE, DEEP, NF3),
+	/* GPP_V32 : [] ==> BT_I2S_SDO - SSP2 */
+	PAD_CFG_NF(GPP_VGPIO32, NONE, DEEP, NF3),
+	/* GPP_V33 : [] ==> BT_I2S_SDI - SSP2 */
+	PAD_CFG_NF(GPP_VGPIO33, NONE, DEEP, NF3),
+	/* GPP_V34 : [] ==> SSP_SCLK */
+	PAD_CFG_NF(GPP_VGPIO34, NONE, DEEP, NF1),
+	/* GPP_V35 : [] ==> SSP_SFRM */
+	PAD_CFG_NF(GPP_VGPIO35, NONE, DEEP, NF1),
+	/* GPP_V36 : [] ==> SSP_TXD */
+	PAD_CFG_NF(GPP_VGPIO36, NONE, DEEP, NF1),
+	/* GPP_V37 : [] ==> SSP_RXD */
+	PAD_CFG_NF(GPP_VGPIO37, NONE, DEEP, NF1),
+};
+
+static const struct pad_config bt_i2s_disable_pads[] = {
+	/* GPP_V30 : [] ==> BT_I2S_BCLK */
+	PAD_NC(GPP_VGPIO30, NONE),
+	/* GPP_V31 : [] ==> BT_I2S_SYNC */
+	PAD_NC(GPP_VGPIO31, NONE),
+	/* GPP_V32 : [] ==> BT_I2S_SDO */
+	PAD_NC(GPP_VGPIO32, NONE),
+	/* GPP_V33 : [] ==> BT_I2S_SDI */
+	PAD_NC(GPP_VGPIO33, NONE),
+	/* GPP_V34 : [] ==> SSP2_SCLK */
+	PAD_NC(GPP_VGPIO34, NONE),
+	/* GPP_V35 : [] ==> SSP2_SFRM */
+	PAD_NC(GPP_VGPIO35, NONE),
+	/* GPP_V36 : [] ==> SSP_TXD */
+	PAD_NC(GPP_VGPIO36, NONE),
+	/* GPP_V37 : [] ==> SSP_RXD */
+	PAD_NC(GPP_VGPIO37, NONE),
+};
+
+static const struct pad_config sndw_alc722_enable_pads[] = {
+	/* SNDW3_CLK   */
+	PAD_CFG_NF(GPP_S00, NONE, DEEP, NF1),
+	/* SNDW3_DATA0 */
+	PAD_CFG_NF(GPP_S01, NONE, DEEP, NF1),
+	/* SNDW3_DATA1 */
+	PAD_CFG_NF(GPP_S02, NONE, DEEP, NF1),
+	/* SNDW3_DATA2 */
+	PAD_CFG_NF(GPP_S03, NONE, DEEP, NF1),
+	/* DMIC_CLK_A0 */
+	PAD_CFG_NF(GPP_S04, NONE, DEEP, NF5),
+	/* DMIC_DATA_0 */
+	PAD_CFG_NF(GPP_S05, NONE, DEEP, NF5),
+	/* SNDW1_CLK   */
+	PAD_CFG_NF(GPP_S06, NONE, DEEP, NF3),
+	/* SNDW1_DATA  */
+	PAD_CFG_NF(GPP_S07, NONE, DEEP, NF3),
+
+	/* DMIC_CLK */
+	PAD_CFG_NF(GPP_D16, NONE, DEEP, NF3),
+	/* DMIC_DATA */
+	PAD_CFG_NF(GPP_D17, NONE, DEEP, NF3),
+};
+
+static const struct pad_config audio_disable_pads[] = {
+	PAD_NC(GPP_S00, NONE),
+	PAD_NC(GPP_S01, NONE),
+	PAD_NC(GPP_S02, NONE),
+	PAD_NC(GPP_S03, NONE),
+	PAD_NC(GPP_S04, NONE),
+	PAD_NC(GPP_S05, NONE),
+	PAD_NC(GPP_S06, NONE),
+	PAD_NC(GPP_S07, NONE),
+	PAD_NC(GPP_D09, NONE),
+	PAD_NC(GPP_D10, NONE),
+	PAD_NC(GPP_D11, NONE),
+	PAD_NC(GPP_D12, NONE),
+	PAD_NC(GPP_D13, NONE),
+	PAD_NC(GPP_D16, NONE),
+	PAD_NC(GPP_D17, NONE),
+};
+
+static const struct pad_config pre_mem_x1slot_pads[] = {
+	/* GPP_A08:     X1_PCIE_SLOT_PWR_EN */
+	PAD_CFG_GPO(GPP_A08, 0, PLTRST),
+};
+static const struct pad_config x1slot_pads[] = {
+	/* GPP_A08:     X1_PCIE_SLOT_PWR_EN */
+	PAD_CFG_GPO(GPP_A08, 1, PLTRST),
+	/* GPP_D19:     X1_DT_PCIE_RST_N */
+	PAD_CFG_GPO(GPP_D19, 1, PLTRST),
+	/* GPP_B25:     X1_SLOT_WAKE_N */
+	PAD_CFG_GPI_SCI_LOW(GPP_B25, NONE, DEEP, LEVEL),
+};
+
+static const struct pad_config x1slot_disable_pads[] = {
+	/* GPP_A08:     X1_PCIE_SLOT_PWR_EN */
+	PAD_CFG_GPO(GPP_A08, 0, PLTRST),
+	/* GPP_D19:     X1_DT_PCIE_RST_N */
+	PAD_NC(GPP_D19, NONE),
+	/* GPP_B25:     X1_SLOT_WAKE_N */
+	PAD_NC(GPP_B25, NONE)
+};
+
+/*
+ * WWAN: power sequence requires three stages:
+ * step 1: 3.3V power, FCP# (Full Card Power), RST#, and PERST# off
+ * step 2: deassert FCP#
+ * step 3: deassert RST# first, and then PERST#.
+ * NOTE: Since PERST# is gated by platform reset, PERST# deassertion will happen
+ * at much later time and time between RST# and PERSET# is guaranteed.
+ */
+static const struct pad_config pre_mem_wwan_pwr_seq1_pads[] = {
+	/* GPP_H16:     WWAN_PWREN */
+	PAD_CFG_GPO(GPP_H16, 1, PLTRST),
+	/* GPP_A09:  M.2_WWAN_FCP_OFF_N */
+	PAD_CFG_GPO(GPP_A09, 0, PLTRST),
+	/* GPP_B20:     M.2_WWAN_RST_N */
+	PAD_CFG_GPO(GPP_B20, 0, PLTRST),
+	/* GPP_D03:     M.2_WWAN_PERST_GPIO_N */
+	PAD_CFG_GPO(GPP_D03, 0, PLTRST),
+};
+
+static const struct pad_config pre_mem_wwan_pwr_seq2_pads[] = {
+	/* GPP_A09:     M.2_WWAN_FCP_OFF_N */
+	PAD_CFG_GPO(GPP_A09, 1, PLTRST),
+};
+
+static const struct pad_config wwan_pwr_seq3_pads[] = {
+	/* GPP_D03:     M.2_WWAN_PERST_GPIO_N */
+	PAD_CFG_GPO(GPP_D03, 1, PLTRST),
+	/* GPP_B20:     M.2_WWAN_RST_N */
+	PAD_CFG_GPO(GPP_B20, 1, PLTRST),
+	/* GPP_E02:     WWAN_WAKE_GPIO_N */
+	PAD_CFG_GPI_SCI_LOW(GPP_E02, NONE, DEEP, LEVEL),
+};
+
+static const struct pad_config wwan_disable_pads[] = {
+	/* GPP_A09:     M.2_WWAN_FCP_OFF_N */
+	PAD_NC(GPP_A09, NONE),
+	/* GPP_D03:     M.2_WWAN_PERST_GPIO_N */
+	PAD_NC(GPP_D03, NONE),
+	/* GPP_B20:     M.2_WWAN_RST_N */
+	PAD_NC(GPP_B20, NONE),
+	/* GPP_H16:     WWAN_PWREN */
+	PAD_NC(GPP_H16, NONE),
+	/* GPP_A10:     M.2_WWAN_DISABLE_N */
+	PAD_NC(GPP_A10, NONE),
+	/* GPP_E02:     WWAN_WAKE_GPIO_N */
+	PAD_NC(GPP_E02, NONE),
+};
+
+/* Gen4 NVME: at the top M.2 slot */
+static const struct pad_config pre_mem_gen4_ssd_pwr_pads[] = {
+	/* GPP_B10:     GEN4_SSD_PWREN */
+	PAD_CFG_GPO(GPP_B10, 0, PLTRST),
+};
+
+static const struct pad_config gen4_ssd_pads[] = {
+	/* GPP_B10:     GEN4_SSD_PWREN */
+	PAD_CFG_GPO(GPP_B10, 1, PLTRST),
+	/* GPP_B09:     M2_GEN4_SSD_RESET_N */
+	PAD_CFG_GPO(GPP_B09, 1, PLTRST),
+};
+
+static const struct pad_config ufs_enable_pads[] = {
+	/* GPP_D21:     GPP_D21_UFS_REFCLK */
+	PAD_CFG_NF(GPP_D21, NONE, DEEP, NF1),
+};
+
+/* Gen5 NVME: at the bottom M.2 slot */
+static const struct pad_config pre_mem_gen5_ssd_pwr_pads[] = {
+	/* GPP_B16:     GEN5_SSD_PWREN */
+	PAD_CFG_GPO(GPP_B16, 0, PLTRST),
+};
+
+static const struct pad_config gen5_ssd_pads[] = {
+	/* GPP_B16:     GEN5_SSD_PWREN */
+	PAD_CFG_GPO(GPP_B16, 1, PLTRST),
+	/* GPP_E03:     M2_GEN5_SSD_RESET_N */
+	PAD_CFG_GPO(GPP_E03, 1, PLTRST),
+};
+
+static const struct pad_config peg_x4slot_wake_disable_pads[] = {
+	/* GPP_D24:     PEG_SLOT_WAKE_N */
+	PAD_NC(GPP_D24, NONE),
+	/* GPP_D25:     X4_SLOT_WAKE_N */
+	PAD_NC(GPP_D25, NONE),
+};
+
+static const struct pad_config pcie_wlan_enable_pads[] = {
+	/* GPP_A11:     WLAN_RST_N */
+	PAD_CFG_GPO(GPP_A11, 1, PLTRST),
+	/* GPP_A12:     WIFI_WAKE_N */
+	PAD_CFG_GPI_SCI_LOW(GPP_A12, NONE, DEEP, LEVEL),
+};
+
+static const struct pad_config pcie_wlan_disable_pads[] = {
+	/* GPP_A11:     WLAN_RST_N */
+	PAD_NC(GPP_A11, NONE),
+	/* GPP_A12:     WIFI_WAKE_N */
+	PAD_NC(GPP_A12, NONE),
+};
+
+static const struct pad_config cnvi_enable_pads[] = {
+	/* NOTE: IOSSTAGE: 'Ignore' for S0ix */
+	PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_F00, NONE, DEEP, NF1),
+	/* GPP_F01:     M.2_CNV_BRI_RSP_BT_UART2_RXD */
+	/* NOTE: IOSSTAGE: 'Ignore' for S0ix */
+	PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_F01, NONE, DEEP, NF1),
+	/* GPP_F02:     M.2_CNV_RGI_DT_BT_UART2_TXD */
+	/* NOTE: IOSSTAGE: 'Ignore' for S0ix */
+	PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_F02, NONE, DEEP, NF1),
+	/* GPP_F03:     M.2_CNV_RGI_RSP_BT_UART2_CTS_N */
+	/* NOTE: IOSSTAGE: 'Ignore' for S0ix */
+	PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_F03, NONE, DEEP, NF1),
+	/* GPP_F04:     CNV_RF_RESET_R_N */
+	/* NOTE: IOSSTAGE: 'Ignore' for S0ix */
+	PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_F04, NONE, DEEP, NF1),
+	/* GPP_F05:     CRF_CLKREQ_R */
+	/* NOTE: IOSSTAGE: 'Ignore' for S0ix */
+	PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_F05, NONE, DEEP, NF3),
+	/* GPP_A16:     BT_RF_KILL_N */
+	PAD_CFG_GPO(GPP_A16, 1, DEEP),
+	/* GPP_A17:     WIFI_RF_KILL_N */
+	PAD_CFG_GPO(GPP_A17, 1, DEEP),
+};
+
+static const struct pad_config cnvi_disable_pads[] = {
+	/* GPP_F00:     M.2_CNV_BRI_DT_BT_UART2_RTS_N */
+	PAD_NC(GPP_F00, NONE),
+	/* GPP_F01:     M.2_CNV_BRI_RSP_BT_UART2_RXD */
+	PAD_NC(GPP_F01, NONE),
+	/* GPP_F02:     M.2_CNV_RGI_DT_BT_UART2_TXD */
+	PAD_NC(GPP_F02, NONE),
+	/* GPP_F03:     M.2_CNV_RGI_RSP_BT_UART2_CTS_N */
+	PAD_NC(GPP_F03, NONE),
+	/* GPP_F04:     CNV_RF_RESET_R_N */
+	PAD_NC(GPP_F04, NONE),
+	/* GPP_F05:     CRF_CLKREQ_R */
+	PAD_NC(GPP_F05, NONE),
+
+	/* GPP_A16:     BT_RF_KILL_N */
+	PAD_NC(GPP_A16, NONE),
+	/* GPP_A17:     WIFI_RF_KILL_N */
+	PAD_NC(GPP_A17, NONE),
+};
+
+static const struct pad_config touchscreen_disable_pads[] = {
+	/* GPP_F08:     TCH_PNL1_PWR_EN */
+	PAD_CFG_GPO(GPP_F08, 0, PLTRST),
+
+	/* GPP_E11:     THC0_SPI1_CLK_TCH_PNL1 */
+	PAD_NC(GPP_E11, NONE),
+	/* GPP_E12:     THC0_SPI1_IO_0_I2C4_SCL_TCH_PNL1 NF8: I2C4_SCL */
+	PAD_NC(GPP_E12, NONE),
+	/* GPP_E13:     THC0_SPI1_IO_1_I2C4_SDA_TCH_PNL1 NF8: I2C4 SDA */
+	PAD_NC(GPP_E13, NONE),
+	/* GPP_E14:     THC0_SPI1_IO_2_TCH_PNL1 */
+	PAD_NC(GPP_E14, NONE),
+	/* GPP_E15:     THC0_SPI1_IO_3_TCH_PNL1 */
+	PAD_NC(GPP_E15, NONE),
+	/* GPP_E16:     THC0_SPI1_RST_N_TCH_PNL1 */
+	PAD_NC(GPP_E16, NONE),
+	/* GPP_E17:     THC0_SPI1_CS0_N_TCH_PNL1 */
+	PAD_NC(GPP_E17, NONE),
+	/* GPP_E18:     THC0_SPI1_INT_N_TCH_PNL1 */
+	PAD_NC(GPP_E18, NONE),
+};
+
+static const struct pad_config touchscreen_lpss_i2c_enable_pads[] = {
+	/* GPP_E11:     THC0_SPI1_CLK_TCH_PNL1 */
+	PAD_NC(GPP_E11, NONE),
+	/* GPP_E12:     THC0_SPI1_IO_0_I2C4_SCL_TCH_PNL1 NF8: I2C4_SCL */
+	PAD_CFG_NF(GPP_E12, NONE, DEEP, NF8),
+	/* GPP_E13:     THC0_SPI1_IO_1_I2C4_SDA_TCH_PNL1 NF8: I2C4 SDA */
+	PAD_CFG_NF(GPP_E13, NONE, DEEP, NF8),
+	/* GPP_E14:     THC0_SPI1_IO_2_TCH_PNL1 */
+	PAD_NC(GPP_E14, NONE),
+	/* GPP_E15:     THC0_SPI1_IO_3_TCH_PNL1 */
+	PAD_NC(GPP_E15, NONE),
+	/* GPP_E16:     THC0_SPI1_RST_N_TCH_PNL1 */
+	PAD_CFG_GPO(GPP_E16, 1, DEEP),
+	/* GPP_E17:     THC0_SPI1_CS0_N_TCH_PNL1 */
+	PAD_NC(GPP_E17, NONE),
+	/* GPP_E18:     THC0_SPI1_INT_N_TCH_PNL1 */
+	PAD_CFG_GPI_APIC(GPP_E18, NONE, PLTRST, LEVEL, NONE),
+};
+
+static const struct pad_config touchscreen_thc_i2c_enable_pads[] = {
+	/* GPP_E11:     THC0_SPI1_CLK_TCH_PNL1 */
+	PAD_NC(GPP_E11, NONE),
+	/* GPP_E12:     THC0_SPI1_IO_0_I2C4_SCL_TCH_PNL1 NF1: THC I2C0_SCL */
+	PAD_CFG_NF(GPP_E12, NONE, DEEP, NF1),
+	/* GPP_E13:     THC0_SPI1_IO_1_I2C4_SDA_TCH_PNL1 NF1: THC I2C0 SDA */
+	PAD_CFG_NF(GPP_E13, NONE, DEEP, NF1),
+	/* GPP_E14:     THC0_SPI1_IO_2_TCH_PNL1 */
+	PAD_NC(GPP_E14, NONE),
+	/* GPP_E15:     THC0_SPI1_IO_3_TCH_PNL1 */
+	PAD_NC(GPP_E15, NONE),
+	/* GPP_E16:     THC0_SPI1_RST_N_TCH_PNL1 */
+	PAD_CFG_GPO(GPP_E16, 1, DEEP),
+	/* GPP_E17:     THC0_SPI1_CS0_N_TCH_PNL1 */
+	PAD_NC(GPP_E17, NONE),
+	/* GPP_E18:     THC0_SPI1_INT_N_TCH_PNL1 */
+	PAD_CFG_GPI_APIC(GPP_E18, NONE, PLTRST, LEVEL, NONE),
+};
+
+static const struct pad_config touchscreen_gspi_enable_pads[] = {
+	/* GPP_E11:     THC0_SPI1_CLK_TCH_PNL1 NF5: GSPI0 */
+	PAD_CFG_NF(GPP_E11, NONE, DEEP, NF5),
+	/* GPP_E12:     THC0_SPI1_IO_0_I2C4_SCL_TCH_PNL1 NF5: GSPI0 */
+	PAD_CFG_NF(GPP_E12, NONE, DEEP, NF5),
+	/* GPP_E13:     THC0_SPI1_IO_1_I2C4_SDA_TCH_PNL1 NF5: GSPI0 */
+	PAD_CFG_NF(GPP_E13, NONE, DEEP, NF5),
+	/* GPP_E14:     THC0_SPI1_IO_2_TCH_PNL1 */
+	PAD_NC(GPP_E14, NONE),
+	/* GPP_E15:     THC0_SPI1_IO_3_TCH_PNL1 */
+	PAD_NC(GPP_E15, NONE),
+	/* GPP_E16:     THC0_SPI1_RST_N_TCH_PNL1 */
+	PAD_CFG_GPO(GPP_E16, 1, DEEP),
+	/* GPP_E17:     THC0_SPI1_CS0_N_TCH_PNL1 NF5: GSPI0 */
+	PAD_CFG_NF(GPP_E17, NONE, DEEP, NF5),
+	/* GPP_E18:     THC0_SPI1_INT_N_TCH_PNL1 */
+	PAD_CFG_GPI_APIC(GPP_E18, NONE, PLTRST, EDGE_SINGLE, INVERT)
+};
+
+static const struct pad_config touchscreen_thc_spi_enable_pads[] = {
+	/* GPP_E11:     THC0_SPI1_CLK_TCH_PNL1 NF3: THC HID-SPI */
+	PAD_CFG_NF(GPP_E11, NONE, DEEP, NF3),
+	/* GPP_E12:     THC0_SPI1_IO_0_I2C4_SCL_TCH_PNL1 NF3: THC HID-SPI */
+	PAD_CFG_NF(GPP_E12, NONE, DEEP, NF3),
+	/* GPP_E13:     THC0_SPI1_IO_1_I2C4_SDA_TCH_PNL1 NF3: THC HID-SPI */
+	PAD_CFG_NF(GPP_E13, NONE, DEEP, NF3),
+	/* GPP_E14:     THC0_SPI1_IO_2_TCH_PNL1 NF3: THC HID-SPI */
+	PAD_CFG_NF(GPP_E14, NONE, DEEP, NF3),
+	/* GPP_E15:     THC0_SPI1_IO_3_TCH_PNL1 NF3: THC HID-SPI */
+	PAD_CFG_NF(GPP_E15, NONE, DEEP, NF3),
+	/* GPP_E16:     THC0_SPI1_RST_N_TCH_PNL1 NF3: THC HID-SPI */
+	/* THC NOTE: use GPO instead of NF for THC0 Rst */
+	PAD_CFG_GPO(GPP_E16, 1, DEEP),
+	/* GPP_E17:     THC0_SPI1_CS0_N_TCH_PNL1 NF3: THC HID-SPI */
+	PAD_CFG_NF(GPP_E17, NONE, DEEP, NF3),
+	/* GPP_E18:     THC0_SPI1_INT_N_TCH_PNL1 NF3: THC HID-SPI */
+	PAD_CFG_NF(GPP_E18, NONE, DEEP, NF3),
+};
+
+static const struct pad_config touchpad_thc_i2c_enable_pads[] = {
+	/* GPP_F12:     NF1: thc_i2c1_scl */
+	PAD_CFG_NF(GPP_F12, NONE, DEEP, NF1),
+	/* GPP_F13:     NF1: thc_i2c1_sda */
+	PAD_CFG_NF(GPP_F13, NONE, DEEP, NF1),
+};
+
+static const struct pad_config touchpad_lpss_i2c_enable_pads[] = {
+	/* GPP_F12:     THC_I2C1_SCL_TCH_PAD */
+	PAD_CFG_NF(GPP_F12, NONE, DEEP, NF8),
+	/* GPP_F13:     THC_I2C1_SDA_TCH_PAD */
+	PAD_CFG_NF(GPP_F13, NONE, DEEP, NF8),
+	/* GPP_A13:     TCH_PAD_INT_N */
+	PAD_CFG_GPI_IRQ_WAKE(GPP_A13, NONE, PWROK, EDGE_SINGLE, INVERT),
+};
+
+static const struct pad_config touchpad_i2c_disable_pads[] = {
+	/* GPP_F12:     THC_I2C1_SCL_TCH_PAD */
+	PAD_NC(GPP_F12, NONE),
+	/* GPP_F13:     THC_I2C1_SDA_TCH_PAD */
+	PAD_NC(GPP_F13, NONE),
+	/* GPP_A13:     TCH_PAD_INT_N */
+	PAD_NC(GPP_A13, NONE),
+};
+
+static const struct pad_config ish_disable_pads[] = {
+	/* GPP_D06:     NC */
+	PAD_NC(GPP_D06, NONE),
+	/* GPP_E05:     NC */
+	PAD_NC(GPP_E05, NONE),
+	/* GPP_F23:     NC */
+	PAD_NC(GPP_F23, NONE),
+};
+
+static const struct pad_config ish_enable_pads[] = {
+	/* GPP_D06:     ISH_UART0_TXD */
+	PAD_CFG_NF(GPP_D06, NONE, DEEP, NF2),
+	/* GPP_E05:     ISH_GP_7_SNSR_HDR */
+	PAD_CFG_NF(GPP_E05, NONE, DEEP, NF4),
+	/* GPP_F23:     ISH_GP_9A */
+	PAD_CFG_NF(GPP_F23, NONE, DEEP, NF8),
+};
+
+static const struct pad_config fp_disable_pads[] = {
+	PAD_NC(GPP_C15, NONE),
+	/* GPP_D01:     MOD_TCSS1_TYP_A_VBUS_EN */
+	PAD_CFG_GPO(GPP_D01, 1, DEEP),
+	/* FIXME: b/390031369
+	 * use dedicated GPIO PIN for codec enable
+	 * when FPS is enabled.
+	 */
+	/* GPP_E19:     CODEC_EN */
+	PAD_CFG_GPO(GPP_E19, 1, PLTRST),
+	PAD_NC(GPP_E20, NONE),
+	PAD_NC(GPP_F14, NONE),
+	PAD_NC(GPP_F15, NONE),
+	PAD_NC(GPP_F16, NONE),
+	PAD_NC(GPP_F18, NONE),
+};
+
+static const struct pad_config fp_enable_pads[] = {
+	/* GPP_C15:     FPS_RST_N */
+	PAD_CFG_GPO_LOCK(GPP_C15, 1, LOCK_CONFIG),
+	/* GPP_D01:     FPS_SOC_INT_L */
+	PAD_CFG_GPI_IRQ_WAKE(GPP_D01, NONE, PWROK, LEVEL, INVERT),
+	/* GPP_E19:     FPMCU_PWREN */
+	PAD_CFG_GPO(GPP_E19, 1, DEEP),
+	/* GPP_E20:     FPMCU_FW_UPDATE */
+	PAD_CFG_GPO_LOCK(GPP_E20, 0, LOCK_CONFIG),
+	/* GPP_F14:     GPSI0A_MOSI */
+	PAD_CFG_NF(GPP_F14, NONE, DEEP, NF8),
+	/* GPP_F15:     GSPI0A_MISO */
+	PAD_CFG_NF(GPP_F15, NONE, DEEP, NF8),
+	/* GPP_F16:     GPSI0A_CLK */
+	PAD_CFG_NF(GPP_F16, NONE, DEEP, NF8),
+	/* GPP_F18:     GSPI0A_CS0 */
+	PAD_CFG_NF(GPP_F18, NONE, DEEP, NF8),
+};
+
+static const struct pad_config pre_mem_fp_enable_pads[] = {
+	/* GPP_C15:     FPS_RST_N */
+	PAD_CFG_GPO(GPP_C15, 0, DEEP),
+};
+
+void fw_config_configure_pre_mem_gpio(void)
+{
+	if (!fw_config_is_provisioned()) {
+		printk(BIOS_WARNING, "FW_CONFIG is not provisioned, Exiting\n");
+		return;
+	}
+
+	if (!fw_config_probe(FW_CONFIG(CELLULAR, CELLULAR_ABSENT)))
+		GPIO_CONFIGURE_PADS(pre_mem_wwan_pwr_seq1_pads);
+
+	if (fw_config_probe(FW_CONFIG(STORAGE, STORAGE_NVME_GEN4))) {
+		GPIO_CONFIGURE_PADS(pre_mem_gen4_ssd_pwr_pads);
+	} else if (fw_config_probe(FW_CONFIG(STORAGE, STORAGE_NVME_GEN5))) {
+		GPIO_CONFIGURE_PADS(pre_mem_gen5_ssd_pwr_pads);
+	} else if (fw_config_probe(FW_CONFIG(STORAGE, STORAGE_UNKNOWN))) {
+		GPIO_CONFIGURE_PADS(pre_mem_gen4_ssd_pwr_pads);
+		GPIO_CONFIGURE_PADS(pre_mem_gen5_ssd_pwr_pads);
+	}
+
+	if (!fw_config_probe(FW_CONFIG(SD, SD_NONE)))
+		GPIO_CONFIGURE_PADS(pre_mem_x1slot_pads);
+
+	/*
+	 * NOTE: We place WWAN sequence 2 here. According to the WWAN FIBOCOM
+	 * FM350-GL datasheet, the minimum time requirement (Tpr: time between 3.3V
+	 * and FCP#) is '0'. Therefore, it will be fine even though there is no
+	 * GPIO configured for other PADs via fw_config to have the time delay
+	 * introduced in between sequence 1 and 2. Also, FCP# was not the last PAD
+	 * configured in sequence 1. Although the Tpr is '0' in the datasheet, three
+	 * stages are preserved at this time to guarantee the sequence shown in the
+	 * datasheet timing diagram.
+	 */
+	if (!fw_config_probe(FW_CONFIG(CELLULAR, CELLULAR_ABSENT)))
+		GPIO_CONFIGURE_PADS(pre_mem_wwan_pwr_seq2_pads);
+
+	if (fw_config_probe(FW_CONFIG(FP, FP_PRESENT)))
+		GPIO_CONFIGURE_PADS(pre_mem_fp_enable_pads);
+
+}
+
+void fw_config_gpio_padbased_override(struct pad_config *padbased_table)
+{
+	if (!fw_config_is_provisioned()) {
+		printk(BIOS_WARNING, "FW_CONFIG is not provisioned, Exiting\n");
+		return;
+	}
+
+	if (fw_config_probe(FW_CONFIG(STORAGE, STORAGE_NVME_GEN4))) {
+		GPIO_PADBASED_OVERRIDE(padbased_table, gen4_ssd_pads);
+	} else if (fw_config_probe(FW_CONFIG(STORAGE, STORAGE_NVME_GEN5))) {
+		GPIO_PADBASED_OVERRIDE(padbased_table, gen5_ssd_pads);
+	} else if (fw_config_probe(FW_CONFIG(STORAGE, STORAGE_UFS))) {
+		GPIO_PADBASED_OVERRIDE(padbased_table, ufs_enable_pads);
+	} else if (fw_config_probe(FW_CONFIG(STORAGE, STORAGE_UNKNOWN))) {
+		GPIO_PADBASED_OVERRIDE(padbased_table, gen4_ssd_pads);
+		GPIO_PADBASED_OVERRIDE(padbased_table, gen5_ssd_pads);
+		GPIO_PADBASED_OVERRIDE(padbased_table, ufs_enable_pads);
+	}
+
+	if (fw_config_probe(FW_CONFIG(AUDIO, AUDIO_NONE))) {
+		GPIO_PADBASED_OVERRIDE(padbased_table, audio_disable_pads);
+		GPIO_PADBASED_OVERRIDE(padbased_table, bt_i2s_disable_pads);
+	} else if (fw_config_probe(FW_CONFIG(AUDIO, AUDIO_MAX98360_ALC5682I_I2S))) {
+		printk(BIOS_INFO, "Configure GPIOs for I2S MAX98360 ALC5682 audio.\n");
+		GPIO_PADBASED_OVERRIDE(padbased_table, i2s_enable_pads);
+		printk(BIOS_INFO, "Configure GPIOs for BT offload mode.\n");
+		GPIO_PADBASED_OVERRIDE(padbased_table, bt_i2s_enable_pads);
+	} else if (fw_config_probe(FW_CONFIG(AUDIO, AUDIO_MAX98373_ALC5682_SNDW))) {
+		GPIO_PADBASED_OVERRIDE(padbased_table, sndw_external_codec_enable_pads);
+		GPIO_PADBASED_OVERRIDE(padbased_table, bt_i2s_disable_pads);
+	} else if (fw_config_probe(FW_CONFIG(AUDIO, AUDIO_ALC722_SNDW)) ||
+			fw_config_probe(FW_CONFIG(AUDIO, AUDIO_ALC721_SNDW))) {
+		printk(BIOS_INFO, "Configure GPIOs for Soundwire audio.\n");
+		GPIO_PADBASED_OVERRIDE(padbased_table, sndw_alc722_enable_pads);
+		printk(BIOS_INFO, "Configure GPIOs for BT offload mode.\n");
+		GPIO_PADBASED_OVERRIDE(padbased_table, bt_i2s_enable_pads);
+	} else if (fw_config_probe(FW_CONFIG(AUDIO, AUDIO_ALC256_HDA))) {
+		printk(BIOS_INFO, "Configure GPIOs for HDA ALC 256 mode.\n");
+		GPIO_PADBASED_OVERRIDE(padbased_table, hda_enable_pads);
+		GPIO_PADBASED_OVERRIDE(padbased_table, bt_i2s_disable_pads);
+	}
+
+	if (fw_config_probe(FW_CONFIG(WIFI, WIFI_PCIE_6)) ||
+		fw_config_probe(FW_CONFIG(WIFI, WIFI_PCIE_7))) {
+		GPIO_PADBASED_OVERRIDE(padbased_table, pcie_wlan_enable_pads);
+		GPIO_PADBASED_OVERRIDE(padbased_table, cnvi_disable_pads);
+	} else if (fw_config_probe(FW_CONFIG(WIFI, WIFI_CNVI_6)) ||
+		fw_config_probe(FW_CONFIG(WIFI, WIFI_CNVI_7))) {
+		GPIO_PADBASED_OVERRIDE(padbased_table, cnvi_enable_pads);
+		GPIO_PADBASED_OVERRIDE(padbased_table, pcie_wlan_disable_pads);
+	}
+
+	if (fw_config_probe(FW_CONFIG(CELLULAR, CELLULAR_PCIE)) ||
+		fw_config_probe(FW_CONFIG(CELLULAR, CELLULAR_USB))) {
+		GPIO_PADBASED_OVERRIDE(padbased_table, wwan_pwr_seq3_pads);
+	} else {
+		GPIO_PADBASED_OVERRIDE(padbased_table, wwan_disable_pads);
+	}
+
+	if (fw_config_probe(FW_CONFIG(SD, SD_NONE)))
+		GPIO_PADBASED_OVERRIDE(padbased_table, x1slot_disable_pads);
+	else
+		GPIO_PADBASED_OVERRIDE(padbased_table, x1slot_pads);
+
+	if (fw_config_probe(FW_CONFIG(TOUCHPAD, TOUCHPAD_LPSS_I2C)))
+		GPIO_PADBASED_OVERRIDE(padbased_table, touchpad_lpss_i2c_enable_pads);
+	else if (fw_config_probe(FW_CONFIG(TOUCHPAD, TOUCHPAD_THC_I2C)))
+		GPIO_PADBASED_OVERRIDE(padbased_table, touchpad_thc_i2c_enable_pads);
+	else
+		GPIO_PADBASED_OVERRIDE(padbased_table, touchpad_i2c_disable_pads);
+
+	if (fw_config_probe(FW_CONFIG(TOUCHSCREEN, TOUCHSCREEN_LPSS_I2C)))
+		GPIO_PADBASED_OVERRIDE(padbased_table, touchscreen_lpss_i2c_enable_pads);
+	else if (fw_config_probe(FW_CONFIG(TOUCHSCREEN, TOUCHSCREEN_THC_I2C)))
+		GPIO_PADBASED_OVERRIDE(padbased_table, touchscreen_thc_i2c_enable_pads);
+	else if (fw_config_probe(FW_CONFIG(TOUCHSCREEN, TOUCHSCREEN_GSPI)))
+		GPIO_PADBASED_OVERRIDE(padbased_table, touchscreen_gspi_enable_pads);
+	else if (fw_config_probe(FW_CONFIG(TOUCHSCREEN, TOUCHSCREEN_THC_SPI)))
+		GPIO_PADBASED_OVERRIDE(padbased_table, touchscreen_thc_spi_enable_pads);
+	else
+		GPIO_PADBASED_OVERRIDE(padbased_table, touchscreen_disable_pads);
+
+	if (fw_config_probe(FW_CONFIG(ISH, ISH_DISABLE)))
+		GPIO_PADBASED_OVERRIDE(padbased_table, ish_disable_pads);
+	else
+		GPIO_PADBASED_OVERRIDE(padbased_table, ish_enable_pads);
+
+	/* NOTE: disable PEG (x8 slot) and x4 slot wake for now */
+	GPIO_PADBASED_OVERRIDE(padbased_table, peg_x4slot_wake_disable_pads);
+
+	if (fw_config_probe(FW_CONFIG(FP, FP_PRESENT)))
+		GPIO_CONFIGURE_PADS(fp_enable_pads);
+	else
+		GPIO_CONFIGURE_PADS(fp_disable_pads);
+}
diff --git a/src/mainboard/intel/ptlrvp/variants/ptlrvp/gpio.c b/src/mainboard/intel/ptlrvp/variants/ptlrvp/gpio.c
new file mode 100644
index 0000000000..1accd4d597
--- /dev/null
+++ b/src/mainboard/intel/ptlrvp/variants/ptlrvp/gpio.c
@@ -0,0 +1,419 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <baseboard/gpio.h>
+#include <baseboard/variants.h>
+#include <boardid.h>
+#include <soc/gpio.h>
+
+/* Pad configuration in ramstage*/
+static const struct pad_config gpio_table[] = {
+	/* GPP_A00:     ESPI_IO0_EC_R */
+	/*  GPP_A00 : GPP_A00 ==> ESPI_IO0_EC_R configured on reset, do not touch */
+
+	/* GPP_A01:     ESPI_IO1_EC_R */
+	/*  GPP_A01 : GPP_A01 ==> ESPI_IO1_EC_R configured on reset, do not touch */
+
+	/* GPP_A02:     ESPI_IO2_EC_R */
+	/*  GPP_A02 : GPP_A02 ==> ESPI_IO2_EC_R configured on reset, do not touch */
+
+	/* GPP_A03:     ESPI_IO3_EC_R */
+	/*  GPP_A03 : GPP_A03 ==> ESPI_IO3_EC_R configured on reset, do not touch */
+
+	/* GPP_A04:     ESPI_CS0_EC_R_N */
+	/*  GPP_A04 : GPP_A04 ==> ESPI_CS0_HDR_L configured on reset, do not touch */
+
+	/* GPP_A05:     ESPI_CLK_EC_R */
+	/*  GPP_A05 : GPP_A05 ==> ESPI_CLK_HDR configured on reset, do not touch */
+
+	/* GPP_A06:     ESPI_RST_EC_R_N */
+	/*  GPP_A06 : GPP_A06 ==> ESPI_RST_HDR configured on reset, do not touch */
+
+	/* GPP_A09:     M.2_WWAN_FCP_OFF_N */
+	PAD_CFG_GPO(GPP_A09, 1, PLTRST),
+	/* GPP_A10:     M.2_WWAN_DISABLE_N */
+	PAD_CFG_GPO(GPP_A10, 1, PLTRST),
+	/* GPP_A11:     WLAN_RST_N */
+	PAD_CFG_GPO(GPP_A11, 1, PLTRST),
+	/* GPP_A12:     WIFI_WAKE_N */
+	PAD_CFG_GPI_SCI_LOW(GPP_A12, NONE, DEEP, LEVEL),
+	/* GPP_A15:     GPP_A15_DNX_FORCE_RELOAD */
+	PAD_CFG_NF(GPP_A15, NONE, DEEP, NF1),
+	/* GPP_A16:     BT_RF_KILL_N */
+	PAD_CFG_GPO(GPP_A16, 1, DEEP),
+	/* GPP_A17:     WIFI_RF_KILL_N */
+	PAD_CFG_GPO(GPP_A17, 1, DEEP),
+
+	/* GPP_B00:     USBC_SML_CLK_PD */
+	PAD_CFG_NF(GPP_B00, NONE, DEEP, NF1),
+	/* GPP_B01:     USBC_SML_DATA_PD */
+	PAD_CFG_NF(GPP_B01, NONE, DEEP, NF1),
+	/* GPP_B02:     ISH_I2C0_SDA_SNSR_HDR */
+	/* NOTE: IOSSTAGE: 'Ignore' for S0ix */
+	PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_B02, NONE, DEEP, NF3),
+	/* GPP_B03:     ISH_I2C0_SCL_SNSR_HDR */
+	/* NOTE: IOSSTAGE: 'Ignore' for S0ix */
+	PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_B03, NONE, DEEP, NF3),
+	/* GPP_B04:     ISH_GP_0_SNSR_HDR */
+	PAD_CFG_NF(GPP_B04, NONE, DEEP, NF4),
+	/* GPP_B05:     ISH_GP_1_SNSR_HDR */
+	PAD_CFG_NF(GPP_B05, NONE, DEEP, NF4),
+	/* GPP_B06:     ISH_GP_2_SNSR_HDR */
+	PAD_CFG_NF(GPP_B06, NONE, DEEP, NF4),
+	/* GPP_B07:     ISH_GP_3_SNSR_HDR */
+	PAD_CFG_NF(GPP_B07, NONE, DEEP, NF4),
+	/* GPP_B08:     ISH_GP_4_SNSR_HDR */
+	PAD_CFG_NF(GPP_B08, NONE, DEEP, NF4),
+	/* GPP_B09:     M2_GEN4_SSD_RESET_N */
+	PAD_CFG_GPO(GPP_B09, 1, PLTRST),
+	/* GPP_B10:     GEN4_SSD_PWREN */
+	PAD_CFG_GPO(GPP_B10, 1, PLTRST),
+	/* GPP_B11:     MOD_TCSS1_DISP_HPD3 */
+	PAD_CFG_NF(GPP_B11, NONE, DEEP, NF2),
+	/* GPP_B12:     PM_SLP_S0_N */
+	PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1),
+	/* GPP_B13:     PLT_RST_N */
+	PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1),
+	/* GPP_B14:     MOD_TCSS2_DISP_HPD4 */
+	PAD_CFG_NF(GPP_B14, NONE, DEEP, NF2),
+	/* GPP_B15:     MOD_TCSS_USB_TYP_A_OC3_N */
+	PAD_CFG_NF(GPP_B15, NONE, DEEP, NF1),
+	/* GPP_B16:     GEN5_SSD_PWREN */
+	PAD_CFG_GPO(GPP_B16, 1, PLTRST),
+	/* GPP_B17:     Not used */
+	PAD_NC(GPP_B17, NONE),
+	/* GPP_B18:     ISH_I2C2_SDA_SNSR_HDR */
+	/* NOTE: IOSSTAGE: 'Ignore' for S0ix */
+	PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_B18, NONE, DEEP, NF1),
+	/* GPP_B19:     ISH_I2C2_SCL_SNSR_HDR */
+	/* NOTE: IOSSTAGE: 'Ignore' for S0ix */
+	PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_B19, NONE, DEEP, NF1),
+	/* GPP_B20:     M.2_WWAN_RST_N */
+	PAD_CFG_GPO(GPP_B20, 1, PLTRST),
+	/* GPP_B21:     TCP_RETIMER_FORCE_PWR */
+	PAD_CFG_GPO(GPP_B21, 0, DEEP),
+	/* GPP_B22:     ISH_GP_5_SNSR_HDR */
+	PAD_CFG_NF(GPP_B22, NONE, DEEP, NF4),
+	/* GPP_B23:     ISH_GP_6_SNSR_HDR */
+	PAD_CFG_NF(GPP_B23, NONE, DEEP, NF4),
+	/* GPP_B24:     ESPI_ALERT0_EC_R_N */
+	PAD_NC(GPP_B24, NONE),
+
+	/* GPP_C00:     GPP_C0_SMBCLK */
+	PAD_CFG_NF(GPP_C00, NONE, DEEP, NF1),
+	/* GPP_C01:     GPP_C1_SMBDATA */
+	PAD_CFG_NF(GPP_C01, NONE, DEEP, NF1),
+	/* GPP_C02:     Not used */
+	PAD_NC(GPP_C02, NONE),
+	/* GPP_C03:     TCP_LAN_SML0_SCL_R */
+	PAD_CFG_NF(GPP_C03, NONE, DEEP, NF1),
+	/* GPP_C04:     TCP_LAN_SML0_SDA_R */
+	PAD_CFG_NF(GPP_C04, NONE, DEEP, NF1),
+	/* GPP_C06:     SML1_CLK */
+	PAD_CFG_NF(GPP_C06, NONE, DEEP, NF1),
+	/* GPP_C07:     SML1_DATA */
+	PAD_CFG_NF(GPP_C07, NONE, DEEP, NF1),
+	/* GPP_C09:     CLKREQ0_X8_GEN5_DT_CEM_SLOT_N */
+	PAD_CFG_NF(GPP_C09, NONE, DEEP, NF1),
+	/* GPP_C10:     CLKREQ1_X4_GEN5_M2_SSD_N */
+	PAD_CFG_NF(GPP_C10, NONE, DEEP, NF1),
+	/* GPP_C11:     CLKREQ2_X1_GEN4_DT_CEM_SLOT_N */
+	PAD_CFG_NF(GPP_C11, NONE, DEEP, NF1),
+	/* GPP_C12:     CLKREQ3_X1_GEN1_GBE_LAN_N */
+	PAD_CFG_NF(GPP_C12, NONE, DEEP, NF1),
+	/* GPP_C13:     CLKREQ4_X1_GEN4_M2_WLAN_N */
+	PAD_CFG_NF(GPP_C13, NONE, DEEP, NF1),
+	/* GPP_C14:     CLKREQ5_X1_GEN4_M2_WWAN_N */
+	PAD_CFG_NF(GPP_C14, NONE, DEEP, NF1),
+	/* GPP_C16:     TBT_LSX0_TXD  */
+	PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1),
+	/* GPP_C17:     TBT_LSX0_RXD  */
+	PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1),
+	/* GPP_C18:     TBT_LSX1_TXD  */
+	PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1),
+	/* GPP_C19:     TBT_LSX1_RXD */
+	PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1),
+	/* GPP_C20:     MOD_TCSS1_LS_TX_DDC_SCL */
+	PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1),
+	/* GPP_C21:     MOD_TCSS1_LS_RX_DDC_SDA */
+	PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1),
+	/* GPP_C22:     MOD_TCSS2_LS_TX_DDC_SCL */
+	PAD_CFG_NF(GPP_C22, NONE, DEEP, NF2),
+	/* GPP_C23:     MOD_TCSS2_LS_RX_DDC_SDA */
+	PAD_CFG_NF(GPP_C23, NONE, DEEP, NF2),
+
+	/* GPP_D00:     IMGCLKOUT_1 */
+	PAD_CFG_NF(GPP_D00, NONE, DEEP, NF1),
+	/* GPP_D02:     Not used */
+	PAD_NC(GPP_D02, NONE),
+	/* GPP_D03:     M.2_WWAN_PERST_GPIO_N */
+	PAD_CFG_GPO(GPP_D03, 1, PLTRST),
+	/* GPP_D04:     IMGCLKOUT_0 */
+	PAD_CFG_NF(GPP_D04, NONE, DEEP, NF1),
+	/* GPP_D05:     disable ISH_UART0_RXD */
+	PAD_NC(GPP_D05, NONE),
+	/* GPP_D07:     NC */
+	PAD_NC(GPP_D07, NONE),
+	/* GPP_D08:     NC */
+	PAD_NC(GPP_D08, NONE),
+	/* GPP_D09:     PEG_SLOT_RST_N */
+	PAD_CFG_GPO(GPP_D09, 1, PLTRST),
+	/* GPP_D10:     HDA_BCLK */
+	PAD_CFG_NF(GPP_D10, NONE, DEEP, NF1),
+	/* GPP_D11:     HDA_SYNC */
+	PAD_CFG_NF(GPP_D11, NONE, DEEP, NF1),
+	/* GPP_D12:     HDA_SDO */
+	PAD_CFG_NF(GPP_D12, NONE, DEEP, NF1),
+	/* GPP_D13:     HDA_SDI0 */
+	PAD_CFG_NF(GPP_D13, NONE, DEEP, NF1),
+	/* GPP_D14:     COINLESS_MODE_SELECT */
+	PAD_CFG_GPI_TRIG_OWN(GPP_D14, NONE, PLTRST, LEVEL, ACPI),
+	/* GPP_D15:     SPI_TPM_INT_N */
+	PAD_CFG_GPI_APIC_LOCK(GPP_D15, NONE, LEVEL, INVERT, LOCK_CONFIG),
+	/* GPP_D16:     HDA_RST_N_HDR */
+	PAD_CFG_NF(GPP_D16, NONE, DEEP, NF1),
+	/* GPP_D17:     HDA_SDI1_HDR */
+	PAD_CFG_NF(GPP_D17, NONE, DEEP, NF1),
+	/* GPP_D18:     CLKREQ6_X4_GEN4_M2_SSD_N */
+	PAD_CFG_NF(GPP_D18, NONE, DEEP, NF1),
+	/* GPP_D20:     CSE_EARLY_SW */
+	PAD_CFG_GPI_SCI_HIGH(GPP_D20, NONE, DEEP, LEVEL),
+	/* GPP_D21:     NC */
+	PAD_NC(GPP_D21, NONE),
+	/* GPP_D22:     BPKI3C_SDA */
+	PAD_CFG_NF(GPP_D22, NONE, DEEP, NF1),
+	/* GPP_D23:     BPKI3C_SCL */
+	PAD_CFG_NF(GPP_D23, NONE, DEEP, NF1),
+	/* GPP_D24:     PEG_SLOT_WAKE_N */
+	PAD_CFG_GPI_SCI_LOW(GPP_D24, NONE, DEEP, LEVEL),
+	/* GPP_D25:     X4_SLOT_WAKE_N */
+	PAD_CFG_GPI_SCI_LOW(GPP_D25, NONE, DEEP, LEVEL),
+
+	/* GPP_E01:     CRD2_RST_N */
+	PAD_CFG_GPO(GPP_E01, 1, PLTRST),
+	/* GPP_E02:     WWAN_WAKE_GPIO_N  */
+	PAD_CFG_GPI_SCI_LOW(GPP_E02, NONE, DEEP, LEVEL),
+	/* GPP_E03:     M2_GEN5_SSD_RESET_N */
+	PAD_CFG_GPO(GPP_E03, 1, PLTRST),
+	/* GPP_E06:     SECURE_CAM_SW */
+	PAD_CFG_GPI_TRIG_OWN(GPP_E06, NONE, PLTRST, LEVEL, ACPI),
+	/* GPP_E07:     Not used */
+	PAD_NC(GPP_E07, NONE),
+	/* GPP_E08:     Not used */
+	PAD_NC(GPP_E08, NONE),
+	/* GPP_E09:     USB_RD_FP_CONN_12_OC0_N */
+	PAD_CFG_NF(GPP_E09, NONE, DEEP, NF1),
+	/* GPP_E10:     CRD1_RST_N */
+	PAD_CFG_GPO(GPP_E10, 1, PLTRST),
+	/* GPP_E11:     THC0_SPI1_CLK_TCH_PNL1 */
+	PAD_CFG_NF(GPP_E11, NONE, DEEP, NF3),
+	/* GPP_E12:     THC0_SPI1_IO_0_I2C4_SCL_TCH_PNL1 */
+	PAD_CFG_NF(GPP_E12, NONE, DEEP, NF3),
+	/* GPP_E13:     THC0_SPI1_IO_1_I2C4_SDA_TCH_PNL1 */
+	PAD_CFG_NF(GPP_E13, NONE, DEEP, NF3),
+	/* GPP_E14:     THC0_SPI1_IO_2_TCH_PNL1 */
+	PAD_CFG_NF(GPP_E14, NONE, DEEP, NF3),
+	/* GPP_E15:     THC0_SPI1_IO_3_TCH_PNL1 */
+	PAD_CFG_NF(GPP_E15, NONE, DEEP, NF3),
+	/* GPP_E16:     THC0_SPI1_RST_N_TCH_PNL1 */
+	/* THC NOTE: use GPO instead of GPO for THC0 Rst */
+	PAD_CFG_GPO(GPP_E16, 1, DEEP),
+	/* GPP_E17:     THC0_SPI1_CS0_N_TCH_PNL1 */
+	PAD_CFG_NF(GPP_E17, NONE, DEEP, NF3),
+	/* GPP_E18:     THC0_SPI1_INT_N_TCH_PNL1 */
+	PAD_CFG_NF(GPP_E18, NONE, DEEP, NF3),
+	/* GPP_E21:     I2C_PMC_PD_INT_N */
+	PAD_CFG_NF(GPP_E21, NONE, DEEP, NF1),
+	/* GPP_E22:     THC0_SPI1_DSYNC */
+	PAD_CFG_NF(GPP_E22, NONE, DEEP, NF3),
+
+	/* GPP_F00:     M.2_CNV_BRI_DT_BT_UART2_RTS_N */
+	/* NOTE: IOSSTAGE: 'Ignore' for S0ix */
+	PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_F00, NONE, DEEP, NF1),
+	/* GPP_F01:     M.2_CNV_BRI_RSP_BT_UART2_RXD */
+	/* NOTE: IOSSTAGE: 'Ignore' for S0ix */
+	PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_F01, NONE, DEEP, NF1),
+	/* GPP_F02:     M.2_CNV_RGI_DT_BT_UART2_TXD */
+	/* NOTE: IOSSTAGE: 'Ignore' for S0ix */
+	PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_F02, NONE, DEEP, NF1),
+	/* GPP_F03:     M.2_CNV_RGI_RSP_BT_UART2_CTS_N */
+	/* NOTE: IOSSTAGE: 'Ignore' for S0ix */
+	PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_F03, NONE, DEEP, NF1),
+	/* GPP_F04:     CNV_RF_RESET_R_N */
+	/* NOTE: IOSSTAGE: 'Ignore' for S0ix */
+	PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_F04, NONE, DEEP, NF1),
+	/* GPP_F05:     CRF_CLKREQ_R */
+	/* NOTE: IOSSTAGE: 'Ignore' for S0ix */
+	PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_F05, NONE, DEEP, NF3),
+	/* GPP_F06:     WLAN_WWAN_COEX3 */
+	PAD_CFG_NF(GPP_F06, NONE, DEEP, NF1),
+	/* GPP_F07:     IMGCLKOUT_2 */
+	PAD_CFG_NF(GPP_F07, NONE, DEEP, NF2),
+	/* GPP_F08:     TCH_PNL1_PWR_EN */
+	PAD_CFG_GPO(GPP_F08, 1, PLTRST),
+	/* GPP_F09:     NC */
+	PAD_NC(GPP_F09, NONE),
+	/* GPP_F10:     PEG_SLOT_PWR_EN_N */
+	PAD_CFG_GPO(GPP_F10, 0, PLTRST),
+	/* GPP_F11:     MOD_TCSS2_TYP_A_VBUS_EN */
+	PAD_CFG_GPO(GPP_F11, 1, DEEP),
+	/* GPP_F12:     THC_I2C1_SCL_TCH_PAD */
+	PAD_CFG_NF(GPP_F12, NONE, DEEP, NF8),
+	/* GPP_F13:     THC_I2C1_SDA_TCH_PAD */
+	PAD_CFG_NF(GPP_F13, NONE, DEEP, NF8),
+	/* GPP_F17:     Not used */
+	PAD_CFG_GPI_INT(GPP_F17, NONE, PLTRST, EDGE_BOTH),
+	/* GPP_F19:     GPP_PRIVACY_LED_CAM2 */
+	PAD_CFG_GPO(GPP_F19, 0, PLTRST),
+	/* GPP_F20:     GPP_PRIVACY_LED_CAM1_CVS_HST_WAKE */
+	PAD_CFG_GPO(GPP_F20, 0, PLTRST),
+	/* GPP_F22:     THC1_SPI2_DSYNC */
+	PAD_CFG_NF(GPP_F22, NONE, DEEP, NF3),
+
+	/* GPP_H00:     Not used */
+	PAD_NC(GPP_H00, NONE),
+	/* GPP_H01:     CRD_CAM_STROBE */
+	PAD_CFG_GPO(GPP_H01, 0, PLTRST),
+	/* GPP_H02:     DEBUG_TRACE_PNP */
+	PAD_CFG_GPO(GPP_H02, 1, PLTRST),
+	/* GPP_H03:     MIC MUTE */
+	PAD_CFG_NF(GPP_H03, NONE, DEEP, NF1),
+	/* GPP_H04:     I2C2_SDA_CAM_FLSH */
+	PAD_CFG_NF(GPP_H04, NONE, DEEP, NF1),
+	/* GPP_H05:     I2C2_SCL_CAM_FLSH */
+	PAD_CFG_NF(GPP_H05, NONE, DEEP, NF1),
+	/* GPP_H06:     I2C3_SDA_PSS */
+	PAD_CFG_NF(GPP_H06, NONE, DEEP, NF1),
+	/* GPP_H07:     I2C3_SCL_PSS */
+	PAD_CFG_NF(GPP_H07, NONE, DEEP, NF1),
+	/* GPP_H08:     UART0_BUF_RXD */
+	PAD_CFG_NF(GPP_H08, NONE, DEEP, NF1),
+	/* GPP_H09:     UART0_BUF_TXD */
+	PAD_CFG_NF(GPP_H09, NONE, DEEP, NF1),
+	/* GPP_H10:     UART0_BUF_RTS */
+	PAD_CFG_NF(GPP_H10, NONE, DEEP, NF1),
+	/* GPP_H11:     UART0_BUF_CTS */
+	PAD_CFG_NF(GPP_H11, NONE, DEEP, NF1),
+	/* GPP_H13:     CPU_C10_GATE_N_R */
+	PAD_CFG_NF(GPP_H13, NONE, DEEP, NF1),
+	/* GPP_H14:     NC */
+	PAD_NC(GPP_H14, NONE),
+	/* GPP_H15:     NC */
+	PAD_NC(GPP_H15, NONE),
+	/* GPP_H16:     WWAN_PWREN */
+	PAD_CFG_GPO(GPP_H16, 1, PLTRST),
+	/* GPP_H17:     MIC MUTE LED */
+	PAD_CFG_NF(GPP_H17, NONE, DEEP, NF1),
+	/* GPP_H19:     I3C0_SDA_HDR */
+	PAD_CFG_NF(GPP_H19, NONE, DEEP, NF2),
+	/* GPP_H20:     I3C0_SCL_HDR */
+	PAD_CFG_NF(GPP_H20, NONE, DEEP, NF2),
+	/* GPP_H21:     I2C1_SDA_I3C1_SDA_CAM_FLSH_CVS */
+	PAD_CFG_NF(GPP_H21, NONE, DEEP, NF1),
+	/* GPP_H22:     I2C1_SCL_I3C1_SCL_CAM_FLSH_CVS */
+	PAD_CFG_NF(GPP_H22, NONE, DEEP, NF1),
+
+	/* GPP_S00:     SNDW3_CLK_CODEC */
+	PAD_CFG_NF(GPP_S00, NONE, DEEP, NF1),
+	/* GPP_S01:     SNDW3_DATA0_CODEC */
+	PAD_CFG_NF(GPP_S01, NONE, DEEP, NF1),
+	/* GPP_S02:     SNDW3_DATA1_CODEC */
+	PAD_CFG_NF(GPP_S02, NONE, DEEP, NF1),
+	/* GPP_S03:     SNDW3_DATA2_CODEC */
+	PAD_CFG_NF(GPP_S03, NONE, DEEP, NF1),
+	/* GPP_S04:     SNDW2_CLK */
+	PAD_CFG_NF(GPP_S04, NONE, DEEP, NF2),
+	/* GPP_S05:     SNDW2_DATA0 */
+	PAD_CFG_NF(GPP_S05, NONE, DEEP, NF2),
+	/* GPP_S06:     SNDW1_CLK */
+	PAD_CFG_NF(GPP_S06, NONE, DEEP, NF3),
+	/* GPP_S07:     SNDW1_DATA0 */
+	PAD_CFG_NF(GPP_S07, NONE, DEEP, NF3),
+
+	/* GPP_V00:     PM_BATLOW_N */
+	PAD_CFG_NF(GPP_V00, NONE, DEEP, NF1),
+	/* GPP_V01:     BC_ACOK_MCP */
+	PAD_CFG_NF(GPP_V01, NONE, DEEP, NF1),
+	/* GPP_V02:     LANWAKE_N_R */
+	PAD_CFG_NF(GPP_V02, NONE, DEEP, NF1),
+	/* GPP_V03:     PWRBTN_MCP_N */
+	PAD_CFG_NF(GPP_V03, NONE, DEEP, NF1),
+	/* GPP_V04:     PM_SLP_S3_N */
+	PAD_CFG_NF(GPP_V04, NONE, DEEP, NF1),
+	/* GPP_V05:     PM_SLP_S4_N */
+	PAD_CFG_NF(GPP_V05, NONE, DEEP, NF1),
+	/* GPP_V06:     PM_SLP_A_N */
+	PAD_CFG_NF(GPP_V06, NONE, DEEP, NF1),
+	/* GPP_V07:     Not used */
+	PAD_NC(GPP_V07, NONE),
+	/* GPP_V08:     SLP_WLAN_N */
+	PAD_CFG_NF(GPP_V08, NONE, DEEP, NF1),
+	/* GPP_V09:     PM_SLP_S5_N */
+	PAD_CFG_NF(GPP_V09, NONE, DEEP, NF1),
+	/* GPP_V10:     LANPHYPC_R_N */
+	PAD_CFG_NF(GPP_V10, NONE, DEEP, NF1),
+	/* GPP_V11:     PM_SLP_LAN_N */
+	PAD_CFG_NF(GPP_V11, NONE, DEEP, NF1),
+	/* GPP_V12:     WAKE_N */
+	PAD_CFG_NF(GPP_V12, NONE, DEEP, NF1),
+	/* GPP_V13:     GPP_V13_CATERR_N */
+	PAD_CFG_NF(GPP_V13, NONE, DEEP, NF1),
+	/* GPP_V14:     GPP_V14_FORCEPR_N */
+	PAD_CFG_NF(GPP_V14, NONE, DEEP, NF1),
+	/* GPP_V15:     GPP_V15_THERMTRIP_N */
+	PAD_CFG_NF(GPP_V15, NONE, DEEP, NF1),
+	/* GPP_V16:     GPP_V16_VCCST_EN */
+	PAD_CFG_NF(GPP_V16, NONE, DEEP, NF1),
+	/* GPP_V17:     TCP_RT_S0IX_ENTRY_EXIT_N */
+	PAD_CFG_GPO(GPP_V17, 1, DEEP),
+};
+
+/* Early pad configuration in bootblock */
+static const struct pad_config early_gpio_table[] = {
+	/* GPP_H08:     UART0_BUF_RXD */
+	PAD_CFG_NF(GPP_H08, NONE, DEEP, NF1),
+	/* GPP_H09:     UART0_BUF_TXD */
+	PAD_CFG_NF(GPP_H09, NONE, DEEP, NF1),
+
+	/* GPP_H06: I2C3_SDA_PSS */
+	PAD_CFG_NF(GPP_H06, NONE, DEEP, NF1),
+	/* GPP_H07: I2C3_SCL_PSS */
+	PAD_CFG_NF(GPP_H07, NONE, DEEP, NF1),
+	/* GPP_D15: SPI_TPM_INT_N */
+	PAD_CFG_GPI_APIC(GPP_D15, NONE, PLTRST, LEVEL, INVERT),
+};
+
+/* Pad configuration in romstage */
+static const struct pad_config romstage_gpio_table[] = {
+	/* GPP_C00:     GPP_C0_SMBCLK */
+	PAD_CFG_NF(GPP_C00, NONE, DEEP, NF1),
+	/* GPP_C01:     GPP_C1_SMBDATA */
+	PAD_CFG_NF(GPP_C01, NONE, DEEP, NF1),
+};
+
+const struct pad_config *variant_gpio_table(size_t *num)
+{
+	*num = ARRAY_SIZE(gpio_table);
+	return gpio_table;
+}
+
+const struct pad_config *variant_early_gpio_table(size_t *num)
+{
+	*num = ARRAY_SIZE(early_gpio_table);
+	return early_gpio_table;
+}
+
+/* Create the stub for romstage gpio, typically use for power sequence */
+const struct pad_config *variant_romstage_gpio_table(size_t *num)
+{
+	*num = ARRAY_SIZE(romstage_gpio_table);
+	return romstage_gpio_table;
+}
+
+static const struct cros_gpio cros_gpios[] = {
+	CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE0_NAME),
+	CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE1_NAME),
+	CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE2_NAME),
+	CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE3_NAME),
+};
+
+DECLARE_CROS_GPIOS(cros_gpios);
diff --git a/src/mainboard/intel/ptlrvp/variants/ptlrvp/hda_verb.c b/src/mainboard/intel/ptlrvp/variants/ptlrvp/hda_verb.c
new file mode 100644
index 0000000000..2f703b78ee
--- /dev/null
+++ b/src/mainboard/intel/ptlrvp/variants/ptlrvp/hda_verb.c
@@ -0,0 +1,126 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <device/azalia_device.h>
+
+const u32 cim_verb_data[] = {
+	/* coreboot specific header */
+	0x10ec0256,	/* Codec Vendor / Device ID: Realtek ALC256 */
+	0x10ec12ac,	/* Subsystem ID */
+	0x00000013,	/* Number of jacks (NID entries) */
+
+	AZALIA_RESET(0x1),
+	/* NID 0x01, HDA Codec Subsystem ID Verb Table */
+	AZALIA_SUBVENDOR(0, 0x10ec12ac),
+
+	/* Pin Widget Verb Table */
+	/*
+	 * DMIC
+	 * Requirement is to use PCH DMIC. Hence,
+	 * commented out codec's Internal DMIC.
+	 * AZALIA_PIN_CFG(0, 0x12, 0x90A60130),
+	 * AZALIA_PIN_CFG(0, 0x13, 0x40000000),
+	 */
+	/* Pin widget 0x14 - Front (Port-D) */
+	AZALIA_PIN_CFG(0, 0x14, 0x90170110),
+	/* Pin widget 0x18 - NPC */
+	AZALIA_PIN_CFG(0, 0x18, 0x411111F0),
+	/* Pin widget 0x19 - MIC2 (Port-F) */
+	AZALIA_PIN_CFG(0, 0x19, 0x04A11040),
+	/* Pin widget 0x1A - LINE1 (Port-C) */
+	AZALIA_PIN_CFG(0, 0x1a, 0x411111F0),
+	/* Pin widget 0x1B - NPC */
+	AZALIA_PIN_CFG(0, 0x1b, 0x411111F0),
+	/* Pin widget 0x1D - BEEP-IN */
+	AZALIA_PIN_CFG(0, 0x1d, 0x40610041),
+	/* Pin widget 0x1E - NPC */
+	AZALIA_PIN_CFG(0, 0x1e, 0x411111F0),
+	/* Pin widget 0x21 - HP1-OUT (Port-I) */
+	AZALIA_PIN_CFG(0, 0x21, 0x04211020),
+	/*
+	 * Widget node 0x20 - 1
+	 * Codec hidden reset and speaker power 2W/4ohm
+	 */
+	0x0205001A,
+	0x0204C003,
+	0x02050038,
+	0x02047901,
+	/*
+	 * Widget node 0x20 - 2
+	 * Class D power on Reset
+	 */
+	0x0205003C,
+	0x02040354,
+	0x0205003C,
+	0x02040314,
+	/*
+	 * Widget node 0x20 - 3
+	 * Disable AGC and set AGC limit to -1.5dB
+	 */
+	0x02050016,
+	0x02040C50,
+	0x02050012,
+	0x0204EBC1,
+	/*
+	 * Widget node 0x20 - 4
+	 * Set AGC Post gain +1.5dB then Enable AGC
+	 */
+	0x02050013,
+	0x02044023,
+	0x02050016,
+	0x02040E50,
+	/*
+	 * Widget node 0x20 - 5
+	 * Silence detector enabling + Set EAPD to verb control
+	 */
+	0x02050037,
+	0x0204FE15,
+	0x02050010,
+	0x02040020,
+	/*
+	 * Widget node 0x20 - 6
+	 * Silence data mode Threshold (-90dB)
+	 */
+	0x02050030,
+	0x0204A000,
+	0x0205001B,
+	0x02040A4B,
+	/*
+	 * Widget node 0x20 - 7
+	 * Default setting-1
+	 */
+	0x05750003,
+	0x05740DA3,
+	0x02050046,
+	0x02040004,
+	/*
+	 * Widget node 0x20 - 8
+	 * support 1 pin detect two port
+	 */
+	0x02050009,
+	0x0204E003,
+	0x0205000A,
+	0x02047770,
+	/*
+	 * Widget node 0x20 - 9
+	 * To set LDO1/LDO2 as default
+	 */
+	0x02050008,
+	0x02046A0C,
+	0x02050008,
+	0x02046A0C,
+};
+
+const u32 pc_beep_verbs[] = {
+	/* Dos beep path - 1 */
+	0x01470C00,
+	0x02050036,
+	0x02047151,
+	0x01470740,
+	/* Dos beep path - 2 */
+	0x0143b000,
+	0x01470C02,
+	0x01470C02,
+	0x01470C02,
+};
+
+AZALIA_ARRAY_SIZES;
diff --git a/src/mainboard/intel/ptlrvp/variants/ptlrvp/include/variant/ec.h b/src/mainboard/intel/ptlrvp/variants/ptlrvp/include/variant/ec.h
new file mode 100644
index 0000000000..4fc0622f15
--- /dev/null
+++ b/src/mainboard/intel/ptlrvp/variants/ptlrvp/include/variant/ec.h
@@ -0,0 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#ifndef MAINBOARD_EC_H
+#define MAINBOARD_EC_H
+
+#include <baseboard/ec.h>
+
+#endif /* MAINBOARD_GPIO_H */
diff --git a/src/mainboard/intel/ptlrvp/variants/ptlrvp/include/variant/gpio.h b/src/mainboard/intel/ptlrvp/variants/ptlrvp/include/variant/gpio.h
new file mode 100644
index 0000000000..238a99e0ed
--- /dev/null
+++ b/src/mainboard/intel/ptlrvp/variants/ptlrvp/include/variant/gpio.h
@@ -0,0 +1,12 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#ifndef __MAINBOARD_GPIO_H__
+#define __MAINBOARD_GPIO_H__
+
+#include <baseboard/gpio.h>
+
+/* TODO: Add GPIO as per ptlrvp board */
+/* EC wake is LAN_WAKE# which is a special DeepSX wake pin */
+#define GPE_EC_WAKE	GPE0_LAN_WAK
+
+#endif /* __MAINBOARD_GPIO_H__ */
diff --git a/src/mainboard/intel/ptlrvp/variants/ptlrvp/memory.c b/src/mainboard/intel/ptlrvp/variants/ptlrvp/memory.c
new file mode 100644
index 0000000000..e0908adabd
--- /dev/null
+++ b/src/mainboard/intel/ptlrvp/variants/ptlrvp/memory.c
@@ -0,0 +1,76 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <baseboard/variants.h>
+#include <soc/romstage.h>
+#include <soc/meminit.h>
+
+static const struct mb_cfg lp5_mem_config = {
+	.type = MEM_TYPE_LP5X,
+
+	.lpx_dq_map = {
+		.ddr0 = {
+			.dq0 = {  13,  14,  12,  15, 11,  10,  8,  9, },
+			.dq1 = {  7,  5,  4,  6,  0,  3,  1,  2 },
+		},
+		.ddr1 = {
+			.dq0 = {  1,  3,  0,  2,  7,  4,  6,  5, },
+			.dq1 = {  12,  13,  14,  15,  11,  10,  9,  8 },
+		},
+		.ddr2 = {
+			.dq0 = {  0,  2,  1,  3,  6,  4,  7,  5 },
+			.dq1 = {  14,  13,  15,  12,  8,  11,  10,  9, },
+		},
+		.ddr3 = {
+			.dq0 = {  6,  5,  7,  4,  2,  3,  1,  0, },
+			.dq1 = {  10,  8,  11,  9,  12,  15,  13,  14 },
+		},
+		.ddr4 = {
+			.dq0 = {  2,  1,  3,  0,  4,  7,  5,  6 },
+			.dq1 = {  15,  14,  12,  13,  9,  11,  10,  8, },
+		},
+		.ddr5 = {
+			.dq0 = {  6,  5,  7,  4,  3,  1,  0,  2, },
+			.dq1 = {  10,  9,  11,  8,  13,  14,  12,  15 },
+		},
+		.ddr6 = {
+			.dq0 = {  9,  10,  11,  8,  14,  12,  13, 15, },
+			.dq1 = {  0,  1,  2,  3,  5,  7,  4,  6 },
+		},
+		.ddr7 = {
+			.dq0 = {  0,  1,  2,  3,  7,  5,  6,  4, },
+			.dq1 = {  14,  13,  15,  12,  10,  8,  11,  9 },
+		},
+	},
+
+	.lpx_dqs_map = {
+		.ddr0 = { .dqs0 = 1, .dqs1 = 0 },
+		.ddr1 = { .dqs0 = 0, .dqs1 = 1 },
+		.ddr2 = { .dqs0 = 0, .dqs1 = 1 },
+		.ddr3 = { .dqs0 = 0, .dqs1 = 1 },
+		.ddr4 = { .dqs0 = 0, .dqs1 = 1 },
+		.ddr5 = { .dqs0 = 0, .dqs1 = 1 },
+		.ddr6 = { .dqs0 = 1, .dqs1 = 0 },
+		.ddr7 = { .dqs0 = 0, .dqs1 = 1 }
+	},
+
+	.ect = true, /* Early Command Training */
+
+	.lp_ddr_dq_dqs_re_training = 1,
+
+	.user_bd = BOARD_TYPE_ULT_ULX,
+
+	.lp5x_config = {
+		.ccc_config = 0xFF,
+	},
+};
+
+const struct mb_cfg *variant_memory_params(void)
+{
+	return &lp5_mem_config;
+}
+
+void variant_get_spd_info(struct mem_spd *spd_info)
+{
+	spd_info->topo = MEM_TOPO_MEMORY_DOWN;
+	spd_info->cbfs_index = 0;
+}
diff --git a/src/mainboard/intel/ptlrvp/variants/ptlrvp/memory/Makefile.mk b/src/mainboard/intel/ptlrvp/variants/ptlrvp/memory/Makefile.mk
new file mode 100644
index 0000000000..14126ce67d
--- /dev/null
+++ b/src/mainboard/intel/ptlrvp/variants/ptlrvp/memory/Makefile.mk
@@ -0,0 +1,7 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+# This is an auto-generated file. Do not edit!!
+# Generated by:
+# ./util/spd_tools/bin/part_id_gen PTL lp5 src/mainboard/intel/ptlrvp/variants/ptlrvp/memory src/mainboard/intel/ptlrvp/variants/ptlrvp/memory/mem_parts_used.txt
+
+SPD_SOURCES =
+SPD_SOURCES += spd/lp5/set-0/spd-7.hex      # ID = 0(0b0000)  Parts = H58G56BK7BX068
diff --git a/src/mainboard/intel/ptlrvp/variants/ptlrvp/memory/dram_id.generated.txt b/src/mainboard/intel/ptlrvp/variants/ptlrvp/memory/dram_id.generated.txt
new file mode 100644
index 0000000000..21082111da
--- /dev/null
+++ b/src/mainboard/intel/ptlrvp/variants/ptlrvp/memory/dram_id.generated.txt
@@ -0,0 +1,7 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+# This is an auto-generated file. Do not edit!!
+# Generated by:
+# ./util/spd_tools/bin/part_id_gen PTL lp5 src/mainboard/intel/ptlrvp/variants/ptlrvp/memory src/mainboard/intel/ptlrvp/variants/ptlrvp/memory/mem_parts_used.txt
+
+DRAM Part Name                 ID to assign
+H58G56BK7BX068                 0 (0000)
diff --git a/src/mainboard/intel/ptlrvp/variants/ptlrvp/memory/mem_parts_used.txt b/src/mainboard/intel/ptlrvp/variants/ptlrvp/memory/mem_parts_used.txt
new file mode 100644
index 0000000000..17ee7efc60
--- /dev/null
+++ b/src/mainboard/intel/ptlrvp/variants/ptlrvp/memory/mem_parts_used.txt
@@ -0,0 +1,12 @@
+# This is a CSV file containing a list of memory parts used by this variant.
+# One part per line with an optional fixed ID in column 2.
+# Only include a fixed ID if it is required for legacy reasons!
+# Generated IDs are dependent on the order of parts in this file,
+# so new parts must always be added at the end of the file!
+#
+# Generate an updated Makefile.mk and dram_id.generated.txt by running the
+# part_id_gen tool from util/spd_tools.
+# See util/spd_tools/README.md for more details and instructions.
+
+# Part Name
+H58G56BK7BX068
diff --git a/src/mainboard/intel/ptlrvp/variants/ptlrvp/overridetree.cb b/src/mainboard/intel/ptlrvp/variants/ptlrvp/overridetree.cb
new file mode 100644
index 0000000000..cb4c21a1f7
--- /dev/null
+++ b/src/mainboard/intel/ptlrvp/variants/ptlrvp/overridetree.cb
@@ -0,0 +1,890 @@
+fw_config
+	field AUDIO 0 3
+		option AUDIO_NONE			0
+		option AUDIO_MAX98373_ALC5682_SNDW	1
+		option AUDIO_ALC722_SNDW		2
+		option AUDIO_ALC256_HDA			3
+		option AUDIO_MAX98360_ALC5682I_I2S	4
+		option AUDIO_ALC721_SNDW		5
+	end
+	field WIFI 4 5
+		option WIFI_CNVI_6		0
+		option WIFI_CNVI_7		1
+		option WIFI_PCIE_6		2
+		option WIFI_PCIE_7		3
+	end
+	field CELLULAR 6 7
+		option CELLULAR_ABSENT		0
+		option CELLULAR_USB		1
+		option CELLULAR_PCIE		2
+	end
+	field TOUCHSCREEN 8 10
+		option TOUCHSCREEN_NONE		0
+		option TOUCHSCREEN_LPSS_I2C	1
+		option TOUCHSCREEN_GSPI		2
+		option TOUCHSCREEN_THC_SPI	3
+		option TOUCHSCREEN_THC_I2C	4
+	end
+	field TOUCHPAD 11 12
+		option TOUCHPAD_NONE		0
+		option TOUCHPAD_THC_I2C		1
+		option TOUCHPAD_LPSS_I2C	2
+	end
+	field SD 13 14
+		option SD_NONE			0
+		option SD_GENSYS		1
+		option SD_BAYHUB		2
+	end
+	field STORAGE 15 16
+		option STORAGE_UNKNOWN		0
+		option STORAGE_NVME_GEN4	1
+		option STORAGE_NVME_GEN5	2
+		option STORAGE_UFS		3
+	end
+	field FP 17
+		option FP_ABSENT		0
+		option FP_PRESENT		1
+	end
+	field DISPLAY 18
+		option DISPLAY_ABSENT		0
+		option DISPLAY_PRESENT		1
+	end
+	field KB 19
+		option KB_ABSENT		0
+		option KB_PRESENT		1
+	end
+	field UFC 20 21
+		option UFC_ABSENT		0
+		option UFC_MIPI			1
+		option UFC_USB			2
+	end
+	field WFC 22 23
+		option WFC_ABSENT		0
+		option WFC_MIPI			1
+		option WFC_USB			2
+	end
+	field ISH 24
+		option ISH_DISABLE		0
+		option ISH_ENABLE		1
+	end
+end
+
+chip soc/intel/pantherlake
+
+	register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC_SKIP)" # USB2_C0
+	register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC_SKIP)" # USB2_C1
+	register "usb2_ports[2]" = "USB2_PORT_TYPE_C(OC_SKIP)" # USB2_C2
+	register "usb2_ports[3]" = "USB2_PORT_TYPE_C(OC_SKIP)" # USB2_C3
+	register "usb2_ports[4]" = "USB2_PORT_MID(OC0)" # Type-A Port A0
+	register "usb2_ports[5]" = "USB2_PORT_MID(OC0)" # Type-A Port A1 / WWAN with rework
+	register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # CNVi BT or discrete BT
+
+	register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)" # USB3.2 x1 Type-A Con #1
+	register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC0)" # USB3.2 x1 Type-A Con #2 / M.2 WWAN with rework
+
+	register "tcss_ports[0]" = "TCSS_PORT_DEFAULT(OC_SKIP)"
+	register "tcss_ports[1]" = "TCSS_PORT_DEFAULT(OC_SKIP)"
+	register "tcss_ports[2]" = "TCSS_PORT_DEFAULT(OC_SKIP)"
+	register "tcss_ports[3]" = "TCSS_PORT_DEFAULT(OC_SKIP)"
+
+	register "tcss_cap_policy[0]" = "TCSS_TYPE_C_PORT_FULL_FUN"
+	register "tcss_cap_policy[1]" = "TCSS_TYPE_C_PORT_FULL_FUN"
+	register "tcss_cap_policy[2]" = "TCSS_TYPE_C_PORT_FULL_FUN"
+	register "tcss_cap_policy[3]" = "TCSS_TYPE_C_PORT_FULL_FUN"
+
+	# Enable EDP in PortA
+	register "ddi_port_A_config" = "1"
+	register "ddi_ports_config" = "{
+                [DDI_PORT_A] = DDI_ENABLE_HPD,
+        }"
+
+	register "serial_io_i2c_mode" = "{
+		[PchSerialIoIndexI2C0]  = PchSerialIoPci,
+		[PchSerialIoIndexI2C1]  = PchSerialIoPci,
+		[PchSerialIoIndexI2C2]  = PchSerialIoPci,
+		[PchSerialIoIndexI2C3]  = PchSerialIoPci,
+		[PchSerialIoIndexI2C4]  = PchSerialIoPci,
+		[PchSerialIoIndexI2C5]  = PchSerialIoPci,
+	}"
+
+	register "serial_io_gspi_mode" = "{
+		[PchSerialIoIndexGSPI0] = PchSerialIoPci,
+		[PchSerialIoIndexGSPI1] = PchSerialIoDisabled,
+		[PchSerialIoIndexGSPI0A] = PchSerialIoDisabled,
+	}"
+
+	# Intel Common SoC Config
+	#+-------------------+---------------------------+
+	#| Field             |  Value                    |
+	#+-------------------+---------------------------+
+	#| I2C1              | Camera(CRD1)              |
+	#| I2C2              | Camera(CRD2)              |
+	#| I2C3              | Audio, TPM(cr50)          |
+	#| I2C4              | Touchscreen               |
+	#| I2C5              | Touchpad                  |
+	#+-------------------+---------------------------+
+	register "common_soc_config" = "{
+		.chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT,
+		.i2c[1] = {
+			.speed = I2C_SPEED_FAST,
+		},
+		.i2c[2] = {
+			.speed = I2C_SPEED_FAST,
+		},
+		.i2c[3] = {
+			.early_init = 1,
+			.speed = I2C_SPEED_FAST,
+		},
+		.i2c[4] = {
+			.speed = I2C_SPEED_FAST,
+		},
+		.i2c[5] = {
+			.speed = I2C_SPEED_FAST,
+		},
+	}"
+
+	device domain 0 on
+		device ref igpu on
+			probe DISPLAY DISPLAY_PRESENT
+			chip drivers/gfx/generic
+				register "device_count" = "5"
+				# DDIA for eDP
+				register "device[0].name" = ""LCD0""
+				register "device[0].type" = "panel"
+				# DDIB for HDMI
+				# If HDMI is not enumerated in the kernel, then no GFX device should be added for DDIB
+				register "device[1].name" = ""DD01""
+				# TCP0 (DP-1) for port C0
+				register "device[2].name" = ""DD02""
+				register "device[2].use_pld" = "true"
+				register "device[2].pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(1, 1))"
+				# TCP1 (DP-2) for port C1
+				register "device[3].name" = ""DD03""
+				register "device[3].use_pld" = "true"
+				register "device[3].pld" = "ACPI_PLD_TYPE_C(LEFT, RIGHT, ACPI_PLD_GROUP(2, 1))"
+				# TCP2 (DP-3) for port C2
+				register "device[4].name" = ""DD04""
+				register "device[4].use_pld" = "true"
+				register "device[4].pld" = "ACPI_PLD_TYPE_C(RIGHT, LEFT, ACPI_PLD_GROUP(3, 1))"
+				device generic 0 on end
+			end
+		end
+
+		device ref dtt on
+			chip drivers/intel/dptf
+				## sensor information
+				register "options.tsr[0].desc" = ""DDR_SOC""
+				register "options.tsr[1].desc" = ""Ambient""
+				register "options.tsr[2].desc" = ""Charger""
+				register "options.tsr[3].desc" = ""wwan""
+
+				## Active Policy
+				# FIXME: below values are initial reference values only
+				register "policies.active" = "{
+						[0] = {
+							.target = DPTF_TEMP_SENSOR_0,
+							.thresholds = {
+									TEMP_PCT(70, 97),
+									TEMP_PCT(65, 90),
+									TEMP_PCT(60, 80),
+									TEMP_PCT(55, 75),
+									TEMP_PCT(50, 65),
+									TEMP_PCT(45, 45),
+									TEMP_PCT(43, 30),
+								}
+							},
+						[1] = {
+							.target = DPTF_TEMP_SENSOR_1,
+							.thresholds = {
+									TEMP_PCT(70, 97),
+									TEMP_PCT(65, 90),
+									TEMP_PCT(60, 80),
+									TEMP_PCT(55, 75),
+									TEMP_PCT(50, 65),
+									TEMP_PCT(45, 45),
+									TEMP_PCT(43, 30),
+								}
+							},
+						[2] = {
+							.target = DPTF_TEMP_SENSOR_2,
+							.thresholds = {
+									TEMP_PCT(75, 90),
+									TEMP_PCT(70, 80),
+									TEMP_PCT(65, 70),
+									TEMP_PCT(60, 50),
+								}
+							},
+						[3] = {
+							.target = DPTF_TEMP_SENSOR_3,
+							.thresholds = {
+									TEMP_PCT(75, 90),
+									TEMP_PCT(70, 80),
+									TEMP_PCT(65, 70),
+									TEMP_PCT(60, 60),
+									TEMP_PCT(55, 50),
+									TEMP_PCT(50, 40),
+									TEMP_PCT(45, 30),
+								}
+							}
+				}"
+
+				## Passive Policy
+				# TODO: below values are initial reference values only
+				register "policies.passive" = "{
+						[0] = DPTF_PASSIVE(CPU,         CPU,           95, 5000),
+						[1] = DPTF_PASSIVE(CPU,         TEMP_SENSOR_0, 80, 5000),
+						[2] = DPTF_PASSIVE(CPU,         TEMP_SENSOR_1, 80, 5000),
+						[3] = DPTF_PASSIVE(CHARGER,     TEMP_SENSOR_2, 75, 5000),
+						[4] = DPTF_PASSIVE(CPU,         TEMP_SENSOR_3, 80, 5000),
+				}"
+
+				## Critical Policy
+				# TODO: below values are initial reference values only
+				register "policies.critical" = "{
+						[0] = DPTF_CRITICAL(CPU,          105, SHUTDOWN),
+						[1] = DPTF_CRITICAL(TEMP_SENSOR_0, 85, SHUTDOWN),
+						[2] = DPTF_CRITICAL(TEMP_SENSOR_1, 85, SHUTDOWN),
+						[3] = DPTF_CRITICAL(TEMP_SENSOR_2, 85, SHUTDOWN),
+						[4] = DPTF_CRITICAL(TEMP_SENSOR_3, 85, SHUTDOWN),
+				}"
+
+				## Power Limits Control
+				register "controls.power_limits" = "{
+						.pl1 = {
+							.min_power = 25000,
+							.max_power = 25000,
+							.time_window_min = 28 * MSECS_PER_SEC,
+							.time_window_max = 32 * MSECS_PER_SEC,
+							.granularity = 200,
+						},
+						.pl2 = {
+							.min_power = 95000,
+							.max_power = 95000,
+							.time_window_min = 28 * MSECS_PER_SEC,
+							.time_window_max = 32 * MSECS_PER_SEC,
+							.granularity = 1000,
+						}
+				}"
+
+				## Charger Performance Control (Control, mA)
+				register "controls.charger_perf" = "{
+						[0] = { 255, 3000 },
+						[1] = {  24, 1500 },
+						[2] = {  16, 1000 },
+						[3] = {   8,  500 }
+				}"
+
+				## Fan Performance Control (Percent, Speed, Noise, Power)
+				register "controls.fan_perf" = "{
+						[0] = {  90, 6700, 220, 2200, },
+						[1] = {  80, 5800, 180, 1800, },
+						[2] = {  70, 5000, 145, 1450, },
+						[3] = {  60, 4900, 115, 1150, },
+						[4] = {  50, 3838,  90,  900, },
+						[5] = {  40, 2904,  55,  550, },
+						[6] = {  30, 2337,  30,  300, },
+						[7] = {  20, 1608,  15,  150, },
+						[8] = {  10,  800,  10,  100, },
+						[9] = {   0,    0,   0,   50, }
+				}"
+
+				## Fan options
+				register "options.fan.fine_grained_control" = "true"
+				register "options.fan.step_size" = "2"
+
+				device generic 0 alias dptf_policy on end
+			end
+		end
+
+		device ref ipu on
+			chip drivers/intel/mipi_camera
+				register "acpi_uid" = "0x50000"
+				register "acpi_name" = ""IPU0""
+				register "device_type" = "INTEL_ACPI_CAMERA_CIO2"
+				register "cio2_num_ports" = "2"
+				register "cio2_lanes_used" = "{4,2}" # 4 and 2 CSI Camera lanes are used
+				register "cio2_lane_endpoint[0]" = ""^I2C1.CAM0""
+				register "cio2_lane_endpoint[1]" = ""^I2C2.CAM1""
+				register "cio2_prt[0]" = "0"
+				register "cio2_prt[1]" = "2"
+				device generic 0 on
+					probe UFC UFC_MIPI
+					probe WFC WFC_MIPI
+				end
+			end
+		end
+
+		device ref iaa off end
+
+		device ref thc0 on
+			probe TOUCHSCREEN TOUCHSCREEN_THC_SPI
+			probe TOUCHSCREEN TOUCHSCREEN_THC_I2C
+			# THC0 is function 0; hence it needs to be enabled when THC1 is to be enabled.
+			probe TOUCHPAD TOUCHPAD_THC_I2C
+		end
+		device ref thc1 on
+			probe TOUCHPAD TOUCHPAD_THC_I2C
+		end
+
+		device ref tbt_pcie_rp0 on end
+		device ref tbt_pcie_rp1 on end
+		device ref tbt_pcie_rp2 on end
+		device ref tbt_pcie_rp3 on end
+		device ref tcss_xhci on
+			chip drivers/usb/acpi
+				device ref tcss_root_hub on
+					chip drivers/usb/acpi
+						register "desc" = ""USB3 Type-C Port C0""
+						register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
+						register "group" = "ACPI_PLD_GROUP(4, 2)"
+						device ref tcss_usb3_port0 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB3 Type-C Port C1""
+						register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
+						register "group" = "ACPI_PLD_GROUP(3, 2)"
+						device ref tcss_usb3_port1 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB3 Type-C Port C2""
+						register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
+						register "group" = "ACPI_PLD_GROUP(2, 2)"
+						device ref tcss_usb3_port2 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB3 Type-C Port C3""
+						register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
+						register "group" = "ACPI_PLD_GROUP(1, 2)"
+						device ref tcss_usb3_port3 on end
+					end
+				end
+			end
+		end
+
+		device ref tcss_dma0 on
+			chip drivers/intel/usb4/retimer
+				register "dfp[0].power_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B21)"
+				use tcss_usb3_port0 as dfp[0].typec_port
+				device generic 0 on end
+			end
+			chip drivers/intel/usb4/retimer
+				register "dfp[1].power_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B21)"
+				use tcss_usb3_port1 as dfp[1].typec_port
+				device generic 0 on end
+			end
+		end
+		device ref tcss_dma1 on
+			chip drivers/intel/usb4/retimer
+				register "dfp[0].power_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B21)"
+				use tcss_usb3_port2 as dfp[0].typec_port
+				device generic 0 on end
+			end
+			chip drivers/intel/usb4/retimer
+				register "dfp[1].power_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B21)"
+				use tcss_usb3_port3 as dfp[1].typec_port
+				device generic 0 on end
+			end
+		end
+
+		device ref ish on
+			probe ISH ISH_ENABLE
+			probe FP FP_PRESENT
+			chip drivers/intel/ish
+				register "add_acpi_dma_property" = "true"
+				device generic 0 on end
+			end
+		end
+
+		device ref xhci on
+			chip drivers/usb/acpi
+				device ref xhci_root_hub on
+					chip drivers/usb/acpi
+						register "desc" = ""USB2 Type-C Port C0""
+						register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
+						register "group" = "ACPI_PLD_GROUP(1, 1)"
+						device ref usb2_port1 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB2 Type-C Port C1""
+						register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
+						register "group" = "ACPI_PLD_GROUP(2, 1)"
+						device ref usb2_port2 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB2 Type-C Port C2""
+						register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
+						register "group" = "ACPI_PLD_GROUP(3, 1)"
+						device ref usb2_port3 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB2 Type-C Port C3""
+						register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
+						register "group" = "ACPI_PLD_GROUP(4, 1)"
+						device ref usb2_port4 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB2 Type-A Port 1""
+						register "type" = "UPC_TYPE_A"
+						register "group" = "ACPI_PLD_GROUP(5, 1)"
+						device ref usb2_port5 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB2 Type-A Port 2""
+						register "type" = "UPC_TYPE_A"
+						register "group" = "ACPI_PLD_GROUP(6, 1)"
+						device ref usb2_port6 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB2 Type-A Port 3""
+						register "type" = "UPC_TYPE_A"
+						register "group" = "ACPI_PLD_GROUP(7, 1)"
+						device ref usb2_port7 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB2 Bluetooth""
+						register "type" = "UPC_TYPE_INTERNAL"
+						register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A16)"
+						device ref usb2_port8 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB3 Type-A Port 1""
+						register "type" = "UPC_TYPE_USB3_A"
+						register "group" = "ACPI_PLD_GROUP(1, 2)"
+						device ref usb3_port1 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB3 Type-A Port 2""
+						register "type" = "UPC_TYPE_USB3_A"
+						register "group" = "ACPI_PLD_GROUP(2, 2)"
+						device ref usb3_port2 on end
+					end
+				end
+			end
+		end
+
+		device ref ufs on
+			probe STORAGE STORAGE_UFS
+			probe STORAGE STORAGE_UNKNOWN
+		end
+
+		device ref pcie_rp2 on
+			probe CELLULAR CELLULAR_PCIE
+			register "pcie_rp[PCIE_RP(2)]" = "{
+				.clk_src = 5,
+				.clk_req = 5,
+				.flags = PCIE_RP_CLK_REQ_DETECT | PCIE_RP_LTR | PCIE_RP_AER,
+			}"
+			chip soc/intel/common/block/pcie/rtd3
+				register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D03)"
+				register "reset_off_delay_ms" = "20"
+				register "srcclk_pin" = "5"
+				register "ext_pm_support" = "ACPI_PCIE_RP_EMIT_ALL"
+				register "skip_on_off_support" = "true"
+				register "use_rp_mutex" = "true"
+				device generic 0 alias rp2_rtd3 on end
+			end
+			chip drivers/wwan/fm
+				register "fcpo_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A09)"
+				register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B20)"
+				register "perst_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D03)"
+				register "wake_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_E02)"
+				register "add_acpi_dma_property" = "true"
+				use rp2_rtd3 as rtd3dev
+				device generic 0 on end
+			end
+		end # WWAN
+		device ref pcie_rp3 on
+			probe SD SD_GENSYS
+			probe SD SD_BAYHUB
+			# Enable PCH PCIE x1 slot using CLK 3
+			register "pcie_rp[PCIE_RP(3)]" = "{
+				.clk_src = 2,
+				.clk_req = 2,
+				.flags = PCIE_RP_CLK_REQ_DETECT | PCIE_RP_LTR | PCIE_RP_AER,
+			}"
+			chip soc/intel/common/block/pcie/rtd3
+				register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A08)"
+				register "enable_delay_ms" = "100"
+				register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D19)"
+				register "reset_delay_ms" = "20"
+				register "srcclk_pin" = "2"
+				device generic 0 on end
+			end
+		end # PCIE x1 slot
+		device ref pcie_rp4 on
+			probe WIFI WIFI_PCIE_6
+			probe WIFI WIFI_PCIE_7
+			register "pcie_rp[PCH_RP(4)]" = "{
+				.clk_src = 4,
+				.clk_req = 4,
+				.flags = PCIE_RP_CLK_REQ_DETECT | PCIE_RP_LTR | PCIE_RP_AER,
+			}"
+			chip soc/intel/common/block/pcie/rtd3
+				register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A11)"
+				register "srcclk_pin" = "4"
+				device pci 00.0 on end
+			end
+			chip drivers/wifi/generic
+				register "add_acpi_dma_property" = "true"
+				register "wake" = "GPE0_DW0_12" # GPP_A12
+				use usb2_port7 as bluetooth_companion
+				device pci 00.0 on end
+			end
+		end # discrete WLAN
+		device ref pcie_rp5 on
+			probe STORAGE STORAGE_NVME_GEN4
+			probe STORAGE STORAGE_UNKNOWN
+			register "pcie_rp[PCIE_RP(5)]" = "{
+			.clk_src = 6,
+			.clk_req = 6,
+			.flags = PCIE_RP_CLK_REQ_DETECT | PCIE_RP_LTR | PCIE_RP_AER,
+			}"
+			chip soc/intel/common/block/pcie/rtd3
+				register "is_storage" = "true"
+				register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B10)"
+				register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B09)"
+				register "srcclk_pin" = "6"
+				device generic 0 on end
+			end
+		end # Gen4 M.2 SSD
+		device ref pcie_rp9 on
+			probe STORAGE STORAGE_NVME_GEN5
+			probe STORAGE STORAGE_UNKNOWN
+			register "pcie_rp[PCIE_RP(9)]" = "{
+			.clk_src = 1,
+			.clk_req = 1,
+			.flags = PCIE_RP_CLK_REQ_DETECT | PCIE_RP_LTR | PCIE_RP_AER,
+			}"
+			chip soc/intel/common/block/pcie/rtd3
+				register "is_storage" = "true"
+				register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B16)"
+				register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_E03)"
+				register "srcclk_pin" = "1"
+				device generic 0 on end
+			end
+		end # Gen5 M.2 SSD
+		device ref cnvi_wifi on
+			probe WIFI WIFI_CNVI_6
+			probe WIFI WIFI_CNVI_7
+			chip drivers/wifi/generic
+				register "wake" = "GPE0_PME_B0"
+				register "add_acpi_dma_property" = "true"
+				register "enable_cnvi_ddr_rfim" = "true"
+				device generic 0 on end
+			end
+		end # CNVi
+		# NOTE: i2c0 is function 0; hence it needs to be enabled when any of i2c1-5 is enabled.
+		# TPM device is under i2c3. Therefore, i2c0 needs to be enabled anyways.
+		device ref i2c0 on end
+		device ref i2c1 on
+			chip drivers/intel/mipi_camera
+				register "acpi_hid" = ""OVTIDB10""
+				register "acpi_uid" = "0"
+				register "acpi_name" = ""CAM0""
+				register "chip_name" = ""Ov 13b10 Camera""
+				register "device_type" = "INTEL_ACPI_CAMERA_SENSOR"
+
+				register "ssdb.vcm_type" = "0x0C"
+				register "vcm_name" = ""VCM1""
+
+				register "ssdb.lanes_used" = "4"
+				register "num_freq_entries" = "1"
+				register "link_freq[0]" = "560 * MHz" # 560 MHz
+				register "remote_name" = ""IPU0""
+				register "max_dstate_for_probe" = "ACPI_DEVICE_SLEEP_D3_COLD"
+
+				register "has_power_resource" = "true"
+				#Controls
+				register "clk_panel.clks[0].clknum" = "0" # IMGCLKOUT_0
+				register "clk_panel.clks[0].freq" = "1" #19.2 Mhz
+				register "gpio_panel.gpio[0].gpio_num" = "GPP_C05" #power_enable
+				register "gpio_panel.gpio[1].gpio_num" = "GPP_E10" #reset
+
+				#_ON
+				register "on_seq.ops_cnt" = "4"
+				register "on_seq.ops[0]" = "SEQ_OPS_CLK_ENABLE(0, 0)"
+				register "on_seq.ops[1]" = "SEQ_OPS_GPIO_ENABLE(0, 2)"
+				register "on_seq.ops[2]" = "SEQ_OPS_GPIO_DISABLE(1, 1)"
+				register "on_seq.ops[3]" = "SEQ_OPS_GPIO_ENABLE(1, 1)"
+
+				#_OFF
+				register "off_seq.ops_cnt" = "3"
+				register "off_seq.ops[0]" = "SEQ_OPS_CLK_DISABLE(0, 0)"
+				register "off_seq.ops[1]" = "SEQ_OPS_GPIO_DISABLE(1, 0)"
+				register "off_seq.ops[2]" = "SEQ_OPS_GPIO_DISABLE(0, 0)"
+
+				device i2c 36 on
+					probe WFC WFC_MIPI
+				end
+			end
+			chip drivers/intel/mipi_camera
+				register "acpi_uid" = "3"
+				register "acpi_name" = ""VCM1""
+				register "chip_name" = ""DW AF VCM""
+				register "device_type" = "INTEL_ACPI_CAMERA_VCM"
+
+				register "vcm_compat" = ""dongwoon,dw9714""
+
+				register "max_dstate_for_probe" = "ACPI_DEVICE_SLEEP_D0"
+
+				register "has_power_resource" = "true"
+
+				#Controls
+				register "gpio_panel.gpio[0].gpio_num" = "GPP_C05" #power_enable
+
+				#_ON
+				register "on_seq.ops_cnt" = "1"
+				register "on_seq.ops[0]" = "SEQ_OPS_GPIO_ENABLE(0, 0)"
+
+				#_OFF
+				register "off_seq.ops_cnt" = "1"
+				register "off_seq.ops[0]" = "SEQ_OPS_GPIO_DISABLE(0, 0)"
+
+				device i2c 0C on
+					probe WFC WFC_MIPI
+				end
+			end
+			chip drivers/intel/mipi_camera
+				register "acpi_uid" = "1"
+				register "acpi_name" = ""NVM1""
+				register "chip_name" = ""BRCA016GWZ""
+				register "device_type" = "INTEL_ACPI_CAMERA_NVM"
+
+				register "nvm_compat" = ""atmel,24c16""
+
+				register "nvm_size" = "0x800"
+				register "nvm_pagesize" = "0x01"
+				register "nvm_readonly" = "0x01"
+				register "nvm_width" = "0x08"
+
+				register "max_dstate_for_probe" = "ACPI_DEVICE_SLEEP_D0"
+
+				register "has_power_resource" = "true"
+
+				#Controls
+				register "gpio_panel.gpio[0].gpio_num" = "GPP_C05" #power_enable
+
+				#_ON
+				register "on_seq.ops_cnt" = "1"
+				register "on_seq.ops[0]" = "SEQ_OPS_GPIO_ENABLE(0, 0)"
+
+				#_OFF
+				register "off_seq.ops_cnt" = "1"
+				register "off_seq.ops[0]" = "SEQ_OPS_GPIO_DISABLE(0, 0)"
+
+				device i2c 50 on
+					probe WFC WFC_MIPI
+				end
+			end
+		end # I2C1
+		device ref i2c2 on
+			chip drivers/intel/mipi_camera
+				register "acpi_hid" = ""OVTIDB10""
+				register "acpi_uid" = "0"
+				register "acpi_name" = ""CAM1""
+				register "chip_name" = ""Ov 13b10 Camera""
+				register "device_type" = "INTEL_ACPI_CAMERA_SENSOR"
+
+				register "ssdb.vcm_type" = "0x0C"
+				register "vcm_name" = ""VCM1""
+
+				register "ssdb.lanes_used" = "2"
+				register "num_freq_entries" = "1"
+				register "link_freq[0]" = "560 * MHz" # 560 MHz
+				register "remote_name" = ""IPU0""
+				register "max_dstate_for_probe" = "ACPI_DEVICE_SLEEP_D3_COLD"
+
+				register "has_power_resource" = "true"
+				#Controls
+				register "clk_panel.clks[0].clknum" = "1" # IMGCLKOUT_1
+				register "clk_panel.clks[0].freq" = "1" #19.2 Mhz
+				register "gpio_panel.gpio[0].gpio_num" = "GPP_C08" #power_enable
+				register "gpio_panel.gpio[1].gpio_num" = "GPP_E01" #reset
+
+				#_ON
+				register "on_seq.ops_cnt" = "4"
+				register "on_seq.ops[0]" = "SEQ_OPS_CLK_ENABLE(0, 0)"
+				register "on_seq.ops[1]" = "SEQ_OPS_GPIO_ENABLE(0, 2)"
+				register "on_seq.ops[2]" = "SEQ_OPS_GPIO_DISABLE(1, 1)"
+				register "on_seq.ops[3]" = "SEQ_OPS_GPIO_ENABLE(1, 1)"
+
+				#_OFF
+				register "off_seq.ops_cnt" = "3"
+				register "off_seq.ops[0]" = "SEQ_OPS_CLK_DISABLE(0, 0)"
+				register "off_seq.ops[1]" = "SEQ_OPS_GPIO_DISABLE(1, 0)"
+				register "off_seq.ops[2]" = "SEQ_OPS_GPIO_DISABLE(0, 0)"
+
+				device i2c 36 on
+					probe UFC UFC_MIPI
+				end
+			end
+			chip drivers/intel/mipi_camera
+				register "acpi_uid" = "3"
+				register "acpi_name" = ""VCM1""
+				register "chip_name" = ""DW AF VCM""
+				register "device_type" = "INTEL_ACPI_CAMERA_VCM"
+
+				register "vcm_compat" = ""dongwoon,dw9714""
+
+				register "max_dstate_for_probe" = "ACPI_DEVICE_SLEEP_D0"
+
+				register "has_power_resource" = "true"
+
+				#Controls
+				register "gpio_panel.gpio[0].gpio_num" = "GPP_C08" #power_enable
+
+				#_ON
+				register "on_seq.ops_cnt" = "1"
+				register "on_seq.ops[0]" = "SEQ_OPS_GPIO_ENABLE(0, 0)"
+
+				#_OFF
+				register "off_seq.ops_cnt" = "1"
+				register "off_seq.ops[0]" = "SEQ_OPS_GPIO_DISABLE(0, 0)"
+
+				device i2c 0C on
+					probe UFC UFC_MIPI
+				end
+			end
+			chip drivers/intel/mipi_camera
+				register "acpi_uid" = "1"
+				register "acpi_name" = ""NVM1""
+				register "chip_name" = ""BRCA016GWZ""
+				register "device_type" = "INTEL_ACPI_CAMERA_NVM"
+
+				register "nvm_compat" = ""atmel,24c16""
+
+				register "nvm_size" = "0x800"
+				register "nvm_pagesize" = "0x01"
+				register "nvm_readonly" = "0x01"
+				register "nvm_width" = "0x08"
+
+				register "max_dstate_for_probe" = "ACPI_DEVICE_SLEEP_D0"
+
+				register "has_power_resource" = "true"
+
+				#Controls
+				register "gpio_panel.gpio[0].gpio_num" = "GPP_C08" #power_enable
+
+				#_ON
+				register "on_seq.ops_cnt" = "1"
+				register "on_seq.ops[0]" = "SEQ_OPS_GPIO_ENABLE(0, 0)"
+
+				#_OFF
+				register "off_seq.ops_cnt" = "1"
+				register "off_seq.ops[0]" = "SEQ_OPS_GPIO_DISABLE(0, 0)"
+
+				device i2c 50 on
+					probe UFC UFC_MIPI
+				end
+			end
+		end # I2C2
+		device ref i2c3 on
+			chip drivers/i2c/generic
+				register "hid" = ""RTL5682""
+				register "name" = ""RT58""
+				register "desc" = ""Headset Codec""
+				register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_F17)"
+				# Set the jd_src to RT5668_JD1 for jack detection
+				register "property_count" = "1"
+				register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER"
+				register "property_list[0].name" = ""realtek,jd-src""
+				register "property_list[0].integer" = "1"
+				device i2c 1a on
+					probe AUDIO AUDIO_MAX98360_ALC5682I_I2S
+				end
+			end
+			chip drivers/i2c/tpm
+				register "hid" = ""GOOG0005""
+				register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_D15_IRQ)"
+				device i2c 50 on end
+			end
+		end # I2C3
+		device ref i2c4 on
+			chip drivers/i2c/hid
+				register "generic.hid" = ""ELAN6918""
+				register "generic.desc" = ""ELAN Touchscreen""
+				register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_E18_IRQ)"
+				register "generic.probed" = "1"
+				register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_E16)"
+				register "generic.reset_delay_ms" = "20"
+				register "generic.reset_off_delay_ms" = "2"
+				register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_F08)"
+				register "generic.enable_delay_ms" = "1"
+				register "generic.has_power_resource" = "1"
+				register "hid_desc_reg_offset" = "0x01"
+				device i2c 16 on
+					probe TOUCHSCREEN TOUCHSCREEN_LPSS_I2C
+				end
+			end
+		end # I2C4
+		device ref i2c5 on
+			chip drivers/i2c/hid
+				register "generic.hid" = ""HFW68H""
+				register "generic.desc" = ""Hynitron TOUCHPAD""
+				register "generic.irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_A13_IRQ)"
+				register "generic.wake" = "GPE0_DW0_13"
+				register "generic.uid" = "5"
+				register "generic.detect" = "1"
+				register "hid_desc_reg_offset" = "0x20"
+				device i2c 2c on
+					probe TOUCHPAD TOUCHPAD_LPSS_I2C
+				end
+			end
+		end # I2C5
+
+		device ref gspi0 on
+			chip drivers/spi/acpi
+				register "name" = ""CRFP""
+				register "hid" = "ACPI_DT_NAMESPACE_HID"
+				register "uid" = "1"
+				register "compat_string" = ""google,cros-ec-spi""
+				register "irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_D01_IRQ)"
+				register "wake" = "GPE0_DW1_01"
+				register "has_power_resource" = "true"
+				register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C15)"
+				register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E19)"
+				register "enable_delay_ms" = "3"
+				device spi 0 on
+					probe FP FP_PRESENT
+				end
+			end # FPMCU
+		end
+
+		device ref smbus on end
+		device ref npk on end
+		device ref hda on
+			chip drivers/intel/soundwire
+				device generic 0 on
+					chip drivers/soundwire/alc711
+						register "desc" = ""Headset Codec""
+						register "alc711_address.version" = "SOUNDWIRE_VERSION_1_2"
+						register "alc711_address.class" = "MIPI_CLASS_SDCA"
+						register "alc711_address.part_id" = "MIPI_DEV_ID_REALTEK_ALC722"
+						# SoundWire Link 1 ID 1
+						device generic 1.1 on
+							probe AUDIO AUDIO_ALC722_SNDW
+						end
+					end
+					chip drivers/soundwire/alc711
+						register "desc" = ""Headset Codec""
+						register "alc711_address.version" = "SOUNDWIRE_VERSION_1_2"
+						register "alc711_address.class" = "MIPI_CLASS_SDCA"
+						register "alc711_address.part_id" = "MIPI_DEV_ID_REALTEK_ALC721"
+						# SoundWire Link 3 ID 1
+						device generic 3.1 on
+							probe AUDIO AUDIO_ALC721_SNDW
+						end
+					end
+				end
+			end
+			chip drivers/generic/max98357a
+				register "hid" = ""MX98360A""
+				register "sdmode_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E19)"
+				register "sdmode_delay" = "5"
+				device generic 0 on
+					probe AUDIO AUDIO_MAX98360_ALC5682I_I2S
+				end
+			end
+		end
+	end
+end
diff --git a/src/mainboard/intel/ptlrvp/variants/ptlrvp/variant.c b/src/mainboard/intel/ptlrvp/variants/ptlrvp/variant.c
new file mode 100644
index 0000000000..c7aa7aa605
--- /dev/null
+++ b/src/mainboard/intel/ptlrvp/variants/ptlrvp/variant.c
@@ -0,0 +1,30 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <acpi/acpigen.h>
+#include <baseboard/variants.h>
+#include <fw_config.h>
+#include <sar.h>
+
+const char *get_wifi_sar_cbfs_filename(void)
+{
+	return get_wifi_sar_fw_config_filename(FW_CONFIG_FIELD(WIFI));
+}
+
+void variant_update_soc_chip_config(struct soc_intel_pantherlake_config *config)
+{
+	config->cnvi_wifi_core = false;
+	config->cnvi_bt_core = false;
+	/* CNVi */
+	if (fw_config_probe(FW_CONFIG(WIFI, WIFI_CNVI_6)) ||
+		fw_config_probe(FW_CONFIG(WIFI, WIFI_CNVI_7))) {
+		config->cnvi_wifi_core = true;
+		config->cnvi_bt_core = true;
+
+		if (fw_config_probe(FW_CONFIG(AUDIO, AUDIO_MAX98360_ALC5682I_I2S)) ||
+			fw_config_probe(FW_CONFIG(AUDIO, AUDIO_ALC722_SNDW)) ||
+			fw_config_probe(FW_CONFIG(AUDIO, AUDIO_ALC721_SNDW))) {
+			printk(BIOS_INFO, "BT audio offload configured.\n");
+			config->cnvi_bt_audio_offload = true;
+		}
+	}
+}

From 5e491f613f5c7afe30bd967041d03580aa5785e6 Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Thu, 27 Feb 2025 11:23:20 -0600
Subject: [PATCH 0232/3886] soc/intel/meteorlake: Allow boards to disable
 INTEL_TME
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Allow boards to disable TME (total memory encryption) by guarding
selection of TME_KEY_REGENERATION_ON_WARM_BOOT on INTEL_TME.
This way, boards can set INTEL_TME to n in their Kconfig without
generating an unmet dependencies error.

The default behavior/Kconfig selections are unmodified with this change.

Change-Id: I0df1437798e7cafa228ca0e5ae0c32eff774ed09
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86621
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/soc/intel/meteorlake/Kconfig | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/soc/intel/meteorlake/Kconfig b/src/soc/intel/meteorlake/Kconfig
index bc0183d442..d5b4a065a8 100644
--- a/src/soc/intel/meteorlake/Kconfig
+++ b/src/soc/intel/meteorlake/Kconfig
@@ -99,7 +99,7 @@ config SOC_INTEL_METEORLAKE
 	select SOC_INTEL_MEM_MAPPED_PM_CONFIGURATION
 	select SSE2
 	select SUPPORT_CPU_UCODE_IN_CBFS
-	select TME_KEY_REGENERATION_ON_WARM_BOOT
+	select TME_KEY_REGENERATION_ON_WARM_BOOT if INTEL_TME
 	select TSC_MONOTONIC_TIMER
 	select UDELAY_TSC
 	select UDK_202302_BINDING

From 8303a71a9192755a2a5586af4c27aad18a1d12c3 Mon Sep 17 00:00:00 2001
From: Weimin Wu <wuweimin@huaqin.corp-partner.google.com>
Date: Fri, 28 Feb 2025 10:47:08 +0800
Subject: [PATCH 0233/3886] mb/google/fatcat/var/felino: Enable Type-C Ports
 and TBT

Test with PDC fw 19.16.3.

BUG=b:397313651
TEST=
1. FW_NAME=felino emerge-fatcat coreboot-private-files-baseboard-fatcat coreboot chromeos-bootimage
2. Type-C Ports and TBT work fine.

Change-Id: Icbed4d16911665e820382a483607e6dae44b7f8c
Signed-off-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86633
Reviewed-by: Tongtong Pan <pantongtong@huaqin.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 .../google/fatcat/variants/felino/gpio.c      |  6 +--
 .../fatcat/variants/felino/overridetree.cb    | 37 ++++++++++++-------
 2 files changed, 27 insertions(+), 16 deletions(-)

diff --git a/src/mainboard/google/fatcat/variants/felino/gpio.c b/src/mainboard/google/fatcat/variants/felino/gpio.c
index e5ca754dea..a32d44b7d5 100644
--- a/src/mainboard/google/fatcat/variants/felino/gpio.c
+++ b/src/mainboard/google/fatcat/variants/felino/gpio.c
@@ -68,7 +68,7 @@ static const struct pad_config gpio_table[] = {
 	/* GPP_B09:     NC */
 	PAD_NC(GPP_B09, NONE),
 	/* GPP_B10:     SOC_DP1_HDMI_HPD */
-	PAD_CFG_NF(GPP_B10, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_B10, NONE, DEEP, NF2),
 	/* GPP_B11:     PD1_OC_P0_P1_N */
 	PAD_NC(GPP_B11, NONE),
 	/* GPP_B12:     SLP_S0_SOC_N */
@@ -137,9 +137,9 @@ static const struct pad_config gpio_table[] = {
 	/* GPP_C17:     NC  */
 	PAD_NC(GPP_C17, NONE),
 	/* GPP_C18:     TCP3_DDC_SCL  */
-	PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_C18, NONE, DEEP, NF2),
 	/* GPP_C19:     TCP3_DDC_SDA */
-	PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_C19, NONE, DEEP, NF2),
 	/* GPP_C20:     TBT_LSX1_TXD */
 	PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1),
 	/* GPP_C21:     TBT_LSX1_RXD */
diff --git a/src/mainboard/google/fatcat/variants/felino/overridetree.cb b/src/mainboard/google/fatcat/variants/felino/overridetree.cb
index 6b4d32e0a0..c13aa43a91 100644
--- a/src/mainboard/google/fatcat/variants/felino/overridetree.cb
+++ b/src/mainboard/google/fatcat/variants/felino/overridetree.cb
@@ -34,11 +34,17 @@ chip soc/intel/pantherlake
 	register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC_SKIP)" # USB2_C0
 	register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC_SKIP)" # USB2_C1
 	register "usb2_ports[4]" = "USB2_PORT_MID(OC_SKIP)" # Type-A Port A0  # USB HUB (USB2 Camera)
-	register "usb2_ports[5]" = "USB2_PORT_MID(OC3)" # Type-A Port A1 /
+	register "usb2_ports[5]" = "USB2_PORT_LONG(OC3)" # Type-A Port A1 /
 	register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # CNVi BT or discrete BT
 
 	register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB3.2 x1 Type-A Con #2 /
 
+	register "tcss_ports[2]" = "TCSS_PORT_DEFAULT(OC_SKIP)"
+	register "tcss_ports[3]" = "TCSS_PORT_DEFAULT(OC_SKIP)"
+
+	register "tcss_cap_policy[2]" = "TCSS_TYPE_C_PORT_FULL_FUN"
+	register "tcss_cap_policy[3]" = "TCSS_TYPE_C_PORT_FULL_FUN"
+
 	#gpe configuration
 	register "pmc_gpe0_dw0" = "GPP_A"
 	register "pmc_gpe0_dw1" = "GPP_D"
@@ -83,6 +89,9 @@ chip soc/intel/pantherlake
 
 		device ref iaa off end
 
+device ref tbt_pcie_rp0 on end
+		device ref tbt_pcie_rp2 on end
+		device ref tbt_pcie_rp3 on end
 		device ref tcss_xhci on
 			chip drivers/usb/acpi
 				device ref tcss_root_hub on
@@ -93,7 +102,7 @@ chip soc/intel/pantherlake
 						device ref tcss_usb3_port2 on end
 					end
 					chip drivers/usb/acpi
-						register "desc" = ""USB3 Type-C Port C3""
+						register "desc" = ""USB3 Type-C Port C1""
 						register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
 						register "group" = "ACPI_PLD_GROUP(1, 2)"
 						device ref tcss_usb3_port3 on end
@@ -102,6 +111,19 @@ chip soc/intel/pantherlake
 			end
 		end
 
+		device ref tcss_dma1 on
+			chip drivers/intel/usb4/retimer
+				register "dfp[0].power_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_F11)"
+				use tcss_usb3_port3 as dfp[0].typec_port
+				device generic 0 on end
+			end
+			chip drivers/intel/usb4/retimer
+				register "dfp[1].power_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_F11)"
+				use tcss_usb3_port2 as dfp[1].typec_port
+				device generic 0 on end
+			end
+		end
+
 		device ref xhci on
 			chip drivers/usb/acpi
 				device ref xhci_root_hub on
@@ -145,17 +167,6 @@ chip soc/intel/pantherlake
 			end
 		end
 
-		device ref tcss_dma1 on
-			chip drivers/intel/usb4/retimer
-				use tcss_usb3_port2 as dfp[0].typec_port
-				device generic 0 on end
-			end
-			chip drivers/intel/usb4/retimer
-				use tcss_usb3_port3 as dfp[1].typec_port
-				device generic 0 on end
-			end
-		end
-
 		device ref pcie_rp1 on
 			# Enable PCH PCIE x1 slot using CLK 2
 			register "pcie_rp[PCIE_RP(3)]" = "{

From c3273e3896948586c0b8d9fbed4981b288058674 Mon Sep 17 00:00:00 2001
From: Tongtong Pan <pantongtong@huaqin.corp-partner.google.com>
Date: Thu, 27 Feb 2025 15:40:34 +0800
Subject: [PATCH 0234/3886] mb/google/fatcat/var/felino: Add Fn key scancode

The Fn key on felino emits a scancode of 94 (0x5e).

BUG=b:395822961
TEST=Flash Felino, boot to Linux kernel, and verify that KEY_FN is
generated when pressed using `evtest`.

Change-Id: I297cc3dea577acff6c85804ba1f7e5778fc63736
Signed-off-by: Tongtong Pan <pantongtong@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86613
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/google/fatcat/Kconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/src/mainboard/google/fatcat/Kconfig b/src/mainboard/google/fatcat/Kconfig
index 13d791a812..a425d7ee66 100644
--- a/src/mainboard/google/fatcat/Kconfig
+++ b/src/mainboard/google/fatcat/Kconfig
@@ -80,6 +80,7 @@ config BOARD_GOOGLE_FATCATITE
 
 config BOARD_GOOGLE_FELINO
 	select BOARD_GOOGLE_BASEBOARD_FATCAT
+	select MAINBOARD_HAS_GOOGLE_STRAUSS_KEYBOARD
 
 config BOARD_GOOGLE_FRANCKA
 	select BOARD_GOOGLE_BASEBOARD_FATCAT

From 2d2343308a86f7b5f211679cedd9def101193a10 Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Thu, 27 Feb 2025 19:49:09 +0000
Subject: [PATCH 0235/3886] soc/intel/meteorlake: Don't generate a TME on S3
 exit

Generate a new TME key will cause S3 exit to fail, so
don't do it.

Change-Id: Ie19cb7f11ad633405a9fc3c1faf1c3cc53113f51
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86625
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
---
 src/soc/intel/meteorlake/romstage/fsp_params.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/src/soc/intel/meteorlake/romstage/fsp_params.c b/src/soc/intel/meteorlake/romstage/fsp_params.c
index dd9d2b54c6..8e49afa101 100644
--- a/src/soc/intel/meteorlake/romstage/fsp_params.c
+++ b/src/soc/intel/meteorlake/romstage/fsp_params.c
@@ -1,5 +1,6 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
+#include <acpi/acpi.h>
 #include <assert.h>
 #include <bootmode.h>
 #include <console/console.h>
@@ -190,7 +191,7 @@ static void fill_fspm_cpu_params(FSP_M_CONFIG *m_cfg,
 static void fill_tme_params(FSP_M_CONFIG *m_cfg)
 {
 	m_cfg->TmeEnable = CONFIG(INTEL_TME) && is_tme_supported();
-	if (!m_cfg->TmeEnable)
+	if (!m_cfg->TmeEnable || acpi_is_wakeup_s3())
 		return;
 	m_cfg->GenerateNewTmeKey = CONFIG(TME_KEY_REGENERATION_ON_WARM_BOOT) &&
 			 CONFIG(SOC_INTEL_COMMON_BASECODE_RAMTOP);

From f114b018b03501ea466f485d1484e6569e87335b Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Fri, 28 Feb 2025 12:30:51 +0000
Subject: [PATCH 0236/3886] mb/starlabs/starbook/mtl: Don't reconfigure GPIOs
 in ramstage

GPP_H08 and GPP_H09 are configured in the bootblock, so remove the
configuration in ramstage to allow the serial output in ramstage.

Change-Id: I4b813370cf259fb1ca138dd1922c16f801b40cc4
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86650
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
---
 src/mainboard/starlabs/starbook/variants/mtl/gpio.c | 4 ----
 1 file changed, 4 deletions(-)

diff --git a/src/mainboard/starlabs/starbook/variants/mtl/gpio.c b/src/mainboard/starlabs/starbook/variants/mtl/gpio.c
index f95109418f..7a8e660c75 100644
--- a/src/mainboard/starlabs/starbook/variants/mtl/gpio.c
+++ b/src/mainboard/starlabs/starbook/variants/mtl/gpio.c
@@ -267,10 +267,6 @@ const struct pad_config gpio_table[] = {
 	PAD_NC(GPP_H06, NONE),
 	/* H07:	M.2_CPU_SSD_PWREN		*/
 	PAD_CFG_GPO(GPP_H07, 1, DEEP),
-	/* H08:					*/
-	PAD_NC(GPP_H08, NONE),
-	/* H09:					*/
-	PAD_NC(GPP_H09, NONE),
 	/* H10:					*/
 	PAD_NC(GPP_H10, NONE),
 	/* H11:					*/

From f0f66be2c345b4f92f7eb4d0a4852e3702b81397 Mon Sep 17 00:00:00 2001
From: Pranava Y N <pranavayn@google.com>
Date: Fri, 28 Feb 2025 16:11:46 +0530
Subject: [PATCH 0237/3886] mb/google/brya/bujia: Enable RTD3 for SSD

Add PCIe RTD3 support so NVMe gets placed into D3 state when entering
S0ix. Some SSDs block the CPU from reaching C10 during the S0ix
suspend without the RTD3 configuration.

BUG=b:391612392
TEST=Run suspend_stress_test on Bujia and verify that the device
suspends to S0ix.

Change-Id: Idee14e7d4df0a9cf8b06b33a52016c1b9228e459
Signed-off-by: Pranava Y N <pranavayn@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86644
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
---
 src/mainboard/google/brya/variants/bujia/overridetree.cb | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/src/mainboard/google/brya/variants/bujia/overridetree.cb b/src/mainboard/google/brya/variants/bujia/overridetree.cb
index 6db60acb67..370c0520c6 100644
--- a/src/mainboard/google/brya/variants/bujia/overridetree.cb
+++ b/src/mainboard/google/brya/variants/bujia/overridetree.cb
@@ -119,6 +119,13 @@ chip soc/intel/alderlake
 				.clk_src = 0,
 				.flags = PCIE_RP_LTR | PCIE_RP_AER,
 			}"
+			chip soc/intel/common/block/pcie/rtd3
+				register "is_storage" = "true"
+				register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_F14)"
+				register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B4)"
+				register "srcclk_pin" = "0"
+				device generic 0 on end
+			end
 		end #NVME
 		device ref tbt_pcie_rp0 off end
 		device ref tbt_pcie_rp1 off end

From dc9d6fdee3dc3d291838f09cf05596a9830700fe Mon Sep 17 00:00:00 2001
From: Pranava Y N <pranavayn@google.com>
Date: Fri, 28 Feb 2025 17:03:46 +0530
Subject: [PATCH 0238/3886] mb/google/brya/lisbon: Enable RTD3 for SSD

Add PCIe RTD3 support so NVMe gets placed into D3 state when entering
S0ix. Some SSDs block the CPU from reaching C10 during the S0ix
suspend without the RTD3 configuration.

BUG=b:391612392
TEST=Run suspend_stress_test on lisbon and verify that the device
suspends to S0ix.

Change-Id: I124b63061650c85ed84324f3e1558a583a1875e0
Signed-off-by: Pranava Y N <pranavayn@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86645
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
---
 src/mainboard/google/brya/variants/lisbon/overridetree.cb | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/src/mainboard/google/brya/variants/lisbon/overridetree.cb b/src/mainboard/google/brya/variants/lisbon/overridetree.cb
index 4c3fffff6f..6c3eaf952a 100644
--- a/src/mainboard/google/brya/variants/lisbon/overridetree.cb
+++ b/src/mainboard/google/brya/variants/lisbon/overridetree.cb
@@ -149,6 +149,13 @@ chip soc/intel/alderlake
 				.clk_src = 0,
 				.flags = PCIE_RP_LTR | PCIE_RP_AER,
 			}"
+			chip soc/intel/common/block/pcie/rtd3
+				register "is_storage" = "true"
+				register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_F14)"
+				register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B4)"
+				register "srcclk_pin" = "0"
+				device generic 0 on end
+			end
 			probe STORAGE STORAGE_NVME
 		end #NVMe
 		device ref tbt_pcie_rp0 off end

From 172853a8ceddb90e8305bade0e9c600443cc2cad Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Fri, 28 Feb 2025 14:18:19 +0000
Subject: [PATCH 0239/3886] mb/starlabs/starbook/mtl: Don't configure MUX pins

These were incorrectly copied from Alder Lake so remove them
as they are not correct nor needed.

Change-Id: I70708212c4652ed77c875242340c30edf5b935a1
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86651
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 .../starlabs/starbook/variants/mtl/Makefile.mk     |  1 -
 .../starlabs/starbook/variants/mtl/ramstage.c      | 14 --------------
 2 files changed, 15 deletions(-)
 delete mode 100644 src/mainboard/starlabs/starbook/variants/mtl/ramstage.c

diff --git a/src/mainboard/starlabs/starbook/variants/mtl/Makefile.mk b/src/mainboard/starlabs/starbook/variants/mtl/Makefile.mk
index 9abc069b38..2a505c35c7 100644
--- a/src/mainboard/starlabs/starbook/variants/mtl/Makefile.mk
+++ b/src/mainboard/starlabs/starbook/variants/mtl/Makefile.mk
@@ -7,4 +7,3 @@ romstage-y += romstage.c
 ramstage-y += devtree.c
 ramstage-y += gpio.c
 ramstage-y += hda_verb.c
-ramstage-y += ramstage.c
diff --git a/src/mainboard/starlabs/starbook/variants/mtl/ramstage.c b/src/mainboard/starlabs/starbook/variants/mtl/ramstage.c
deleted file mode 100644
index c01c4dd10f..0000000000
--- a/src/mainboard/starlabs/starbook/variants/mtl/ramstage.c
+++ /dev/null
@@ -1,14 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <option.h>
-#include <soc/ramstage.h>
-
-void mainboard_silicon_init_params(FSP_S_CONFIG *supd)
-{
-	/*
-	 * FSP defaults to pins that are used for LPC; given that
-	 * coreboot only supports eSPI, set these pins accordingly.
-	 */
-	supd->PchSerialIoI2cSdaPinMux[0]	= 0x1947c404;	// GPP_H4
-	supd->PchSerialIoI2cSclPinMux[0]	= 0x1947a405;	// GPP_H5
-}

From b8a88f851ea8f567d9fc571815f58722589a2f16 Mon Sep 17 00:00:00 2001
From: Shuo Liu <shuo.liu@intel.com>
Date: Thu, 27 Feb 2025 19:12:39 +0800
Subject: [PATCH 0240/3886] Kconfig: Update prompt and help text for CBFS_SIZE
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Kconfig item CBFS_SIZE is actually indicating the host firmware
size, a.k.a. coreboot owned flash region size, covering
CBFS, FMAP, console, MRC cache, VPD, etc. Revise the prompt and
help documentation to reflect recent usage updates.

Change-Id: I762042fae6357ee368b22a47b8e1168902041675
Signed-off-by: Shuo Liu <shuo.liu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86571
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/Kconfig | 19 ++++++++++---------
 1 file changed, 10 insertions(+), 9 deletions(-)

diff --git a/src/Kconfig b/src/Kconfig
index e4c8467f21..58c2e07ea9 100644
--- a/src/Kconfig
+++ b/src/Kconfig
@@ -634,18 +634,19 @@ config FMDFILE
 	  When an fmd is specified, it overrides the default format.
 
 config CBFS_SIZE
-	hex "Size of CBFS filesystem in ROM"
+	hex "Size of coreboot owned area in ROM"
 	depends on FMDFILE = ""
 	# Default value set at the end of the file
 	help
-	  This is the part of the ROM actually managed by CBFS, located at the
-	  end of the ROM (passed through cbfstool -o) on x86 and at the start
-	  of the ROM (passed through cbfstool -s) everywhere else. It defaults
-	  to span the whole ROM on all but Intel systems that use an Intel Firmware
-	  Descriptor.  It can be overridden to make coreboot live alongside other
-	  components like ChromeOS's vboot/FMAP or Intel's IFD / ME / TXE
-	  binaries. This symbol should only be used to generate a default FMAP and
-	  is unused when a non-default fmd file is provided via CONFIG_FMDFILE.
+	  This is the part of ROM (Read-Only Memory) actually managed by coreboot,
+	  located at the end of the ROM on x86 systems and at the start of the ROM
+	  everywhere else. It defaults to span the whole ROM on all systems except for
+	  Intel systems that use an Intel Flash Descriptor. It can be overridden to
+	  make coreboot live alongside other vendor blobs like Intel's IFD (Intel
+	  Flash Descriptor), ME (Management Engine), and TXE (Trusted Execution
+	  Engine) binaries. This symbol is only used to generate a default FMAP
+	  (Flash Memory Map) and is unused when a .fmd file is provided
+	  via CONFIG_FMDFILE.
 
 endmenu
 

From 927f16085a4080a58b73c7ca3f1cc3124f37ad88 Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Thu, 27 Feb 2025 10:00:09 +0000
Subject: [PATCH 0241/3886] mb/starlabs/starbook/mtl: Correct GPP_D21
 configuration

This GPIO is used for clock request 5, which is NF2.

Change-Id: Ic5712090339a39a269aa1aefca9f54da11cb6528
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86654
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/starlabs/starbook/variants/mtl/gpio.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/mainboard/starlabs/starbook/variants/mtl/gpio.c b/src/mainboard/starlabs/starbook/variants/mtl/gpio.c
index 7a8e660c75..d330400fc2 100644
--- a/src/mainboard/starlabs/starbook/variants/mtl/gpio.c
+++ b/src/mainboard/starlabs/starbook/variants/mtl/gpio.c
@@ -490,7 +490,7 @@ const struct pad_config gpio_table[] = {
 	PAD_CFG_NF(GPP_D20, NONE, DEEP, NF1),
 	/* D21:	CLKREQ5
 	 *			WLAN		*/
-	PAD_CFG_NF(GPP_D21, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_D21, NONE, DEEP, NF2),
 	/* D22:					*/
 	PAD_NC(GPP_D22, NONE),
 	/* D23:					*/

From fe107c1ad217243d68e55d7e238fc59c15d30d70 Mon Sep 17 00:00:00 2001
From: Naresh Solanki <naresh.solanki@9elements.com>
Date: Sat, 23 Nov 2024 18:07:48 +0530
Subject: [PATCH 0242/3886] soc/amd/cpu: smbios: Set external clock to 100 MHz

Set external clock to 100MHz.

source: PPR #57254

Change-Id: I99f73695019612d58b0c78c6985370d23c78b729
Signed-off-by: Naresh Solanki <naresh.solanki@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85636
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
---
 src/soc/amd/glinda/cpu.c | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/src/soc/amd/glinda/cpu.c b/src/soc/amd/glinda/cpu.c
index a7161270d2..26380077f2 100644
--- a/src/soc/amd/glinda/cpu.c
+++ b/src/soc/amd/glinda/cpu.c
@@ -7,11 +7,16 @@
 #include <cpu/amd/microcode.h>
 #include <cpu/cpu.h>
 #include <device/device.h>
+#include <smbios.h>
 #include <soc/cpu.h>
 
 _Static_assert(CONFIG_MAX_CPUS == 24, "Do not override MAX_CPUS. To reduce the number of "
 	"available cores, use the downcore_mode and disable_smt devicetree settings instead.");
 
+unsigned int smbios_processor_external_clock(void)
+{
+	return 100; // 100 MHz
+}
 static void zen_2_3_init(struct device *dev)
 {
 	check_mca();

From 00b4a61dc53c68b47d1452c387409f2eadf32c93 Mon Sep 17 00:00:00 2001
From: Naresh Solanki <naresh.solanki@9elements.com>
Date: Wed, 27 Nov 2024 01:41:40 +0530
Subject: [PATCH 0243/3886] soc/amd/glinda/cpu: Update smbios parameters

Update smbios parameters for cache type, operation mode & error
correction type.

source: UEFI reference BIOS

Change-Id: If8eaa54c9a0086f4d397a7ddb01009acfd3f1aee
Signed-off-by: Naresh Solanki <naresh.solanki@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85637
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/soc/amd/glinda/cpu.c | 16 ++++++++++++++++
 1 file changed, 16 insertions(+)

diff --git a/src/soc/amd/glinda/cpu.c b/src/soc/amd/glinda/cpu.c
index 26380077f2..680b0957d3 100644
--- a/src/soc/amd/glinda/cpu.c
+++ b/src/soc/amd/glinda/cpu.c
@@ -17,6 +17,22 @@ unsigned int smbios_processor_external_clock(void)
 {
 	return 100; // 100 MHz
 }
+
+unsigned int smbios_cache_error_correction_type(u8 level)
+{
+	return SMBIOS_CACHE_ERROR_CORRECTION_MULTI_BIT;
+}
+
+unsigned int smbios_cache_conf_operation_mode(u8 level)
+{
+	return SMBIOS_CACHE_OP_MODE_WRITE_BACK;
+}
+
+unsigned int smbios_cache_sram_type(void)
+{
+	return SMBIOS_CACHE_SRAM_TYPE_PIPELINE_BURST;
+}
+
 static void zen_2_3_init(struct device *dev)
 {
 	check_mca();

From 3794f9f94a9363d618ed9bad4ba22b0a37b5bea2 Mon Sep 17 00:00:00 2001
From: Sergii Dmytruk <sergii.dmytruk@3mdeb.com>
Date: Mon, 23 Sep 2024 21:10:57 +0300
Subject: [PATCH 0244/3886] drivers/efi/capsules.c: fix recording capsule size

As mentioned in comments on CB:83422, size of the current data
block (which is also the last block of a capsule) was incorrectly used
in place of the capsule size:
 - when publishing a capsule in CBMEM (this worked in practice because
   CapsuleApp.efi allocates a continuous physical memory)
 - when aligning target address (which could move output pointer past
   previously allocated buffer by up to 7 bytes per capsule block)

Change-Id: I97a528e2611fcd711c555d0f01e9aadcd2031217
Signed-off-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84542
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/drivers/efi/capsules.c | 12 ++++++++----
 1 file changed, 8 insertions(+), 4 deletions(-)

diff --git a/src/drivers/efi/capsules.c b/src/drivers/efi/capsules.c
index 38178c618e..e8078bbd48 100644
--- a/src/drivers/efi/capsules.c
+++ b/src/drivers/efi/capsules.c
@@ -596,6 +596,7 @@ static void coalesce_capsules(struct block_descr block_chain, uint8_t *target)
 {
 	struct block_descr block = block_chain;
 	uint8_t *capsule_start = NULL;
+	uint32_t capsule_size = 0;
 	uint32_t size_left = 0;
 
 	/* No safety checks in this function, as all of them were done earlier. */
@@ -610,8 +611,10 @@ static void coalesce_capsules(struct block_descr block_chain, uint8_t *target)
 		if (size_left == 0) {
 			const EFI_CAPSULE_HEADER *capsule_hdr =
 				map_range(block.addr, sizeof(*capsule_hdr));
-			size_left = capsule_hdr->CapsuleImageSize;
+			capsule_size = capsule_hdr->CapsuleImageSize;
 			capsule_start = target;
+
+			size_left = capsule_size;
 		}
 
 		uint64_t addr = block.addr;
@@ -641,13 +644,14 @@ static void coalesce_capsules(struct block_descr block_chain, uint8_t *target)
 			}
 
 			uefi_capsules[uefi_capsule_count].base = (uintptr_t)capsule_start;
-			uefi_capsules[uefi_capsule_count].len = block.len;
+			uefi_capsules[uefi_capsule_count].len = capsule_size;
 			uefi_capsule_count++;
 
 			/* This is to align start of the next capsule (assumes that
 			   initial value of target was suitably aligned). */
-			if (!IS_ALIGNED(block.len, CAPSULE_ALIGNMENT))
-				target += ALIGN_UP(block.len, CAPSULE_ALIGNMENT) - block.len;
+			if (!IS_ALIGNED(capsule_size, CAPSULE_ALIGNMENT))
+				target += ALIGN_UP(capsule_size, CAPSULE_ALIGNMENT) -
+					  capsule_size;
 		}
 	}
 

From e90fc546e75ecf272920481266c1249de6cf17d5 Mon Sep 17 00:00:00 2001
From: Elyes Haouas <ehaouas@noos.fr>
Date: Thu, 24 Oct 2024 19:01:59 +0200
Subject: [PATCH 0245/3886] cpu/intel/haswell: Usee boolean for
 haswell_is_ult()

haswell_is_ult() returns CONFIG(INTEL_LYNXPOINT_LP) which is a boolean,
so use boolean instead of int.

Change-Id: I3c98ee819fc937ed6da9ee1340c2af10cec19eb3
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84857
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nicholas Chin <nic.c3.14@gmail.com>
---
 src/cpu/intel/haswell/haswell.h | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/src/cpu/intel/haswell/haswell.h b/src/cpu/intel/haswell/haswell.h
index 5697d0f36e..f63b0ef4b3 100644
--- a/src/cpu/intel/haswell/haswell.h
+++ b/src/cpu/intel/haswell/haswell.h
@@ -4,6 +4,7 @@
 #define _CPU_INTEL_HASWELL_H
 
 #include <cpu/cpu.h>
+#include <stdbool.h>
 #include <stdint.h>
 
 /* CPU types without stepping */
@@ -181,7 +182,7 @@ static inline u32 cpu_stepping(void)
 	return cpuid_eax(1) & 0xf;
 }
 
-static inline int haswell_is_ult(void)
+static inline bool haswell_is_ult(void)
 {
 	return CONFIG(INTEL_LYNXPOINT_LP);
 }

From 362232d2365064286c4202ff2d2777fd8e855c24 Mon Sep 17 00:00:00 2001
From: Maximilian Brune <maximilian.brune@9elements.com>
Date: Thu, 27 Feb 2025 21:30:43 +0100
Subject: [PATCH 0246/3886] soc/amd/glinda/Kconfig: Increase APOB NV size

A glinda based platform reports:
[WARN] RAM APOB data is too large (3b3b0 + 8) > 1e000

APOB NV size is not enough on recent platforms to cache memory training,
which causes the same amount of boot time on subsequent boots as on the
first boot.

Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: I8cc1f1e4f8d6f99c8e2b717926b66a5a683bffdc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86624
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
---
 src/mainboard/amd/birman/board_glinda.fmd         | 2 +-
 src/mainboard/amd/birman/chromeos_glinda.fmd      | 2 +-
 src/mainboard/amd/birman_plus/board_glinda.fmd    | 2 +-
 src/mainboard/amd/birman_plus/chromeos_glinda.fmd | 2 +-
 src/soc/amd/glinda/Kconfig                        | 2 +-
 5 files changed, 5 insertions(+), 5 deletions(-)

diff --git a/src/mainboard/amd/birman/board_glinda.fmd b/src/mainboard/amd/birman/board_glinda.fmd
index 756709044e..bc09fe75d5 100644
--- a/src/mainboard/amd/birman/board_glinda.fmd
+++ b/src/mainboard/amd/birman/board_glinda.fmd
@@ -4,6 +4,6 @@ FLASH@0xFF000000 16M {
 		FMAP 4K
 		COREBOOT(CBFS)
 		EC_BODY@15872K 256K
-		RW_MRC_CACHE 120K
+		RW_MRC_CACHE 256K
 	}
 }
diff --git a/src/mainboard/amd/birman/chromeos_glinda.fmd b/src/mainboard/amd/birman/chromeos_glinda.fmd
index 66227c2778..420ed6e6d4 100644
--- a/src/mainboard/amd/birman/chromeos_glinda.fmd
+++ b/src/mainboard/amd/birman/chromeos_glinda.fmd
@@ -30,6 +30,6 @@ FLASH@0xFF000000 16M {
 		SMMSTORE(PRESERVE) 256K
 		RW_LEGACY(CBFS)
 		EC_BODY@15872K 256K
-		RW_MRC_CACHE(PRESERVE) 120K
+		RW_MRC_CACHE(PRESERVE) 256K
 	}
 }
diff --git a/src/mainboard/amd/birman_plus/board_glinda.fmd b/src/mainboard/amd/birman_plus/board_glinda.fmd
index b9465768be..96e1e8d8f0 100644
--- a/src/mainboard/amd/birman_plus/board_glinda.fmd
+++ b/src/mainboard/amd/birman_plus/board_glinda.fmd
@@ -5,6 +5,6 @@ FLASH 64M {
 		COREBOOT(CBFS)
 		SMMSTORE(PRESERVE) 256K
 		EC_BODY@15872K 256K
-		RW_MRC_CACHE 120K
+		RW_MRC_CACHE 256K
 	}
 }
diff --git a/src/mainboard/amd/birman_plus/chromeos_glinda.fmd b/src/mainboard/amd/birman_plus/chromeos_glinda.fmd
index 66227c2778..420ed6e6d4 100644
--- a/src/mainboard/amd/birman_plus/chromeos_glinda.fmd
+++ b/src/mainboard/amd/birman_plus/chromeos_glinda.fmd
@@ -30,6 +30,6 @@ FLASH@0xFF000000 16M {
 		SMMSTORE(PRESERVE) 256K
 		RW_LEGACY(CBFS)
 		EC_BODY@15872K 256K
-		RW_MRC_CACHE(PRESERVE) 120K
+		RW_MRC_CACHE(PRESERVE) 256K
 	}
 }
diff --git a/src/soc/amd/glinda/Kconfig b/src/soc/amd/glinda/Kconfig
index 70bdb69d6d..1bd5b2f179 100644
--- a/src/soc/amd/glinda/Kconfig
+++ b/src/soc/amd/glinda/Kconfig
@@ -123,7 +123,7 @@ config PSP_APOB_DRAM_ADDRESS
 
 config PSP_APOB_DRAM_SIZE
 	hex
-	default 0x1E000
+	default 0x40000
 
 config PSP_SHAREDMEM_BASE
 	hex

From 118b3941374992def5b784f8a6d03b9972e48891 Mon Sep 17 00:00:00 2001
From: Elyes Haouas <ehaouas@noos.fr>
Date: Thu, 24 Oct 2024 19:16:45 +0200
Subject: [PATCH 0247/3886] sb/intel/lynxpoint/pch: Use boolean for pch_is_lp()

pch_is_lp() returns CONFIG(INTEL_LYNXPOINT_LP) which is a boolean,
so use boolean instead of int.

Change-Id: Ic7bf801f549077cbd493e0a53ba7eff7a72728fb
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84859
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/southbridge/intel/lynxpoint/pch.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/southbridge/intel/lynxpoint/pch.h b/src/southbridge/intel/lynxpoint/pch.h
index 07f4b9dc16..c64b3e3e10 100644
--- a/src/southbridge/intel/lynxpoint/pch.h
+++ b/src/southbridge/intel/lynxpoint/pch.h
@@ -100,7 +100,7 @@ struct usb3_port_config {
 extern const struct usb2_port_config mainboard_usb2_ports[MAX_USB2_PORTS];
 extern const struct usb3_port_config mainboard_usb3_ports[MAX_USB3_PORTS];
 
-static inline int pch_is_lp(void)
+static inline bool pch_is_lp(void)
 {
 	return CONFIG(INTEL_LYNXPOINT_LP);
 }

From 1ce69c9db008c0f31e761855ad7d2d729833c5fe Mon Sep 17 00:00:00 2001
From: Maxim Polyakov <max.senia.poliak@gmail.com>
Date: Thu, 24 Nov 2022 23:54:40 +0300
Subject: [PATCH 0248/3886] util/intelp2m: Drop multi-template support

Exclude the template to parse gpio.h, since coreboot no longer has such
files with raw DW register values. The new GPIO config should be
generated using inteltool.log only.

TEST: make test = PASS

Change-Id: I07124cca487f11641c4e107134efb8cfc29c6731
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70307
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
---
 util/intelp2m/config/config.go        | 63 ++++++++++-----------------
 util/intelp2m/main.go                 | 10 -----
 util/intelp2m/parser/parser.go        | 40 +++++++----------
 util/intelp2m/parser/template.go      | 56 +-----------------------
 util/intelp2m/parser/template_test.go |  2 +-
 util/intelp2m/platforms/adl/macro.go  | 17 +++-----
 util/intelp2m/platforms/cnl/macro.go  | 26 +++++------
 util/intelp2m/platforms/ebg/macro.go  | 20 ++++-----
 util/intelp2m/platforms/jsl/macro.go  | 26 +++++------
 util/intelp2m/platforms/lbg/macro.go  | 15 +++----
 util/intelp2m/platforms/mtl/macro.go  | 25 +++++------
 util/intelp2m/platforms/snr/macro.go  | 22 ++++------
 util/intelp2m/platforms/tgl/macro.go  | 18 +++-----
 util/intelp2m/version.txt             |  2 +-
 14 files changed, 111 insertions(+), 231 deletions(-)

diff --git a/util/intelp2m/config/config.go b/util/intelp2m/config/config.go
index 5578a05853..7b4486b3be 100644
--- a/util/intelp2m/config/config.go
+++ b/util/intelp2m/config/config.go
@@ -3,36 +3,15 @@ package config
 import "os"
 
 const (
-	TempInteltool  int  = 0
-	TempGpioh      int  = 1
-	TempSpec       int  = 2
-)
-
-var template int = 0
-
-func TemplateSet(temp int) bool {
-	if temp > TempSpec {
-		return false
-	} else {
-		template = temp
-		return true
-	}
-}
-
-func TemplateGet() int {
-	return template
-}
-
-const (
-	SunriseType    uint8  = 0
-	LewisburgType  uint8  = 1
-	ApolloType     uint8  = 2
-	CannonType     uint8  = 3
-	TigerType      uint8  = 4
-	AlderType      uint8  = 5
-	JasperType     uint8  = 6
-	MeteorType     uint8  = 7
-	EmmitsburgType uint8  = 8
+	SunriseType    uint8 = 0
+	LewisburgType  uint8 = 1
+	ApolloType     uint8 = 2
+	CannonType     uint8 = 3
+	TigerType      uint8 = 4
+	AlderType      uint8 = 5
+	JasperType     uint8 = 6
+	MeteorType     uint8 = 7
+	EmmitsburgType uint8 = 8
 )
 
 var key uint8 = SunriseType
@@ -48,6 +27,7 @@ var platform = map[string]uint8{
 	"mtl": MeteorType,
 	"ebg": EmmitsburgType,
 }
+
 func PlatformSet(name string) int {
 	if platformType, valid := platform[name]; valid {
 		key = platformType
@@ -90,6 +70,7 @@ var InputRegDumpFile *os.File = nil
 var OutputGenFile *os.File = nil
 
 var ignoredFieldsFormat bool = false
+
 func IgnoredFieldsFlagSet(flag bool) {
 	ignoredFieldsFormat = flag
 }
@@ -98,6 +79,7 @@ func AreFieldsIgnored() bool {
 }
 
 var nonCheckingFlag bool = false
+
 func NonCheckingFlagSet(flag bool) {
 	nonCheckingFlag = flag
 }
@@ -105,8 +87,8 @@ func IsNonCheckingFlagUsed() bool {
 	return nonCheckingFlag
 }
 
-
 var infolevel int = 0
+
 func InfoLevelSet(lvl int) {
 	infolevel = lvl
 }
@@ -115,17 +97,20 @@ func InfoLevelGet() int {
 }
 
 var fldstyle uint8 = CbFlds
+
 const (
-	NoFlds  uint8  = 0
-	CbFlds  uint8  = 1 // coreboot style
-	FspFlds uint8  = 2 // FSP/edk2 style
-	RawFlds uint8  = 3 // raw DW0/1 values
+	NoFlds  uint8 = 0
+	CbFlds  uint8 = 1 // coreboot style
+	FspFlds uint8 = 2 // FSP/edk2 style
+	RawFlds uint8 = 3 // raw DW0/1 values
 )
+
 var fldstylemap = map[string]uint8{
-	"none" : NoFlds,
-	"cb"   : CbFlds,
-	"fsp"  : FspFlds,
-	"raw"  : RawFlds}
+	"none": NoFlds,
+	"cb":   CbFlds,
+	"fsp":  FspFlds,
+	"raw":  RawFlds}
+
 func FldStyleSet(name string) int {
 	if style, valid := fldstylemap[name]; valid {
 		fldstyle = style
diff --git a/util/intelp2m/main.go b/util/intelp2m/main.go
index 5e17721187..25ae03aaef 100644
--- a/util/intelp2m/main.go
+++ b/util/intelp2m/main.go
@@ -61,11 +61,6 @@ func main() {
 		flag.Bool("iiii", false, "Show target PAD_CFG() macro in the comments"),
 	}
 
-	template := flag.Int("t", 0, "template type number\n"+
-		"\t0 - inteltool.log (default)\n"+
-		"\t1 - gpio.h\n"+
-		"\t2 - your template\n\t")
-
 	platform := flag.String("p", "snr", "set platform:\n"+
 		"\tsnr - Sunrise PCH or Skylake/Kaby Lake SoC\n"+
 		"\tlbg - Lewisburg PCH with Xeon SP\n"+
@@ -96,11 +91,6 @@ func main() {
 		}
 	}
 
-	if !config.TemplateSet(*template) {
-		fmt.Printf("Error! Unknown template format of input file!\n")
-		os.Exit(1)
-	}
-
 	if valid := config.PlatformSet(*platform); valid != 0 {
 		fmt.Printf("Error: invalid platform -%s!\n", *platform)
 		os.Exit(1)
diff --git a/util/intelp2m/parser/parser.go b/util/intelp2m/parser/parser.go
index c30c69547d..54cadce5df 100644
--- a/util/intelp2m/parser/parser.go
+++ b/util/intelp2m/parser/parser.go
@@ -61,12 +61,10 @@ type ParserData struct {
 // return the host software ownership form the parser struct
 func (parser *ParserData) hostOwnershipGet(id string) uint8 {
 	var ownership uint8 = 0
-	status, group := parser.platform.GroupNameExtract(id)
-	if config.TemplateGet() == config.TempInteltool && status {
-		numder, _ := strconv.Atoi(strings.TrimLeft(id, group))
-		if (parser.ownership[group] & (1 << uint8(numder))) != 0 {
-			ownership = 1
-		}
+	_, group := parser.platform.GroupNameExtract(id)
+	numder, _ := strconv.Atoi(strings.TrimLeft(id, group))
+	if (parser.ownership[group] & (1 << uint8(numder))) != 0 {
+		ownership = 1
 	}
 	return ownership
 }
@@ -76,22 +74,17 @@ func (parser *ParserData) hostOwnershipGet(id string) uint8 {
 func (parser *ParserData) padInfoExtract() int {
 	var function, id string
 	var dw0, dw1 uint32
-	var template = map[int]template{
-		config.TempInteltool: UseInteltoolLogTemplate,
-		config.TempGpioh:     useGpioHTemplate,
-		config.TempSpec:      useYourTemplate,
+	if rc := UseTemplate(parser.line, &function, &id, &dw0, &dw1); rc != 0 {
+		return rc
 	}
-	if template[config.TemplateGet()](parser.line, &function, &id, &dw0, &dw1) == 0 {
-		pad := padInfo{id: id,
-			function:  function,
-			dw0:       dw0,
-			dw1:       dw1,
-			ownership: parser.hostOwnershipGet(id)}
-		parser.padmap = append(parser.padmap, pad)
-		return 0
-	}
-	fmt.Printf("This template (%d) does not match!\n", config.TemplateGet())
-	return -1
+	pad := padInfo{id: id,
+		function:  function,
+		dw0:       dw0,
+		dw1:       dw1,
+		ownership: parser.hostOwnershipGet(id)}
+	parser.padmap = append(parser.padmap, pad)
+	return 0
+
 }
 
 // communityGroupExtract
@@ -143,8 +136,7 @@ func (parser *ParserData) Register(nameTemplate string) (
 	offset uint32,
 	value uint32,
 ) {
-	if strings.Contains(parser.line, nameTemplate) &&
-		config.TemplateGet() == config.TempInteltool {
+	if strings.Contains(parser.line, nameTemplate) {
 		if registerInfoTemplate(parser.line, &name, &offset, &value) == 0 {
 			fmt.Printf("\n\t/* %s : 0x%x : 0x%x */\n", name, offset, value)
 			return true, name, offset, value
@@ -173,7 +165,7 @@ func (parser *ParserData) padOwnershipExtract() bool {
 //	information from the inteltool log was successfully parsed.
 func (parser *ParserData) padConfigurationExtract() bool {
 	// Only for Sunrise or CannonLake, and only for inteltool.log file template
-	if config.TemplateGet() != config.TempInteltool || config.IsPlatformApollo() {
+	if config.IsPlatformApollo() {
 		return false
 	}
 	return parser.padOwnershipExtract()
diff --git a/util/intelp2m/parser/template.go b/util/intelp2m/parser/template.go
index fc67e73cd7..e7efa734e7 100644
--- a/util/intelp2m/parser/template.go
+++ b/util/intelp2m/parser/template.go
@@ -32,7 +32,7 @@ func tokenCheck(c rune) bool {
 	return c != '_' && c != '#' && !unicode.IsLetter(c) && !unicode.IsNumber(c)
 }
 
-// useGpioHTemplate
+// UseTemplate
 // line      : string from file with pad config map
 // *function : the string that means the pad function
 // *id       : pad id string
@@ -40,9 +40,7 @@ func tokenCheck(c rune) bool {
 // *dw1      : DW1 register value
 // return
 //   error status
-func UseInteltoolLogTemplate(line string, function *string,
-	id *string, dw0 *uint32, dw1 *uint32) int {
-
+func UseTemplate(line string, function *string, id *string, dw0 *uint32, dw1 *uint32) int {
 	var val uint64
 	// 0x0520: 0x0000003c44000600 GPP_B12  SLP_S0#
 	// 0x0438: 0xffffffffffffffff GPP_C7   RESERVED
@@ -64,56 +62,6 @@ func UseInteltoolLogTemplate(line string, function *string,
 	return 0
 }
 
-// useGpioHTemplate
-// line      : string from file with pad config map
-// *function : the string that means the pad function
-// *id       : pad id string
-// *dw0      : DW0 register value
-// *dw1      : DW1 register value
-// return
-//   error status
-func useGpioHTemplate(line string, function *string,
-	id *string, dw0 *uint32, dw1 *uint32) int {
-
-	// /* RCIN# */	_PAD_CFG_STRUCT(GPP_A0, 0x44000702, 0x00000000),
-	// _PAD_CFG_STRUCT(GPP_A0, 0x44000702, 0x00000000), /* RCIN# */
-	// _PAD_CFG_STRUCT(GPP_A0, 0x44000702, 0x00000000)
-	fields := strings.FieldsFunc(line, tokenCheck)
-	for i, field := range fields {
-		if field == "_PAD_CFG_STRUCT" {
-			if len(fields) < 4 {
-				/* the number of definitions does not match the format */
-				return -1
-			}
-
-			if !strings.Contains(fields[i+2], "0x") || !strings.Contains(fields[i+3], "0x") {
-				/* definitions inside the macro do not match the pattern */
-				return -1
-			}
-			*id = fields[i+1]
-			fmt.Sscanf(fields[i+2], "0x%x", dw0)
-			fmt.Sscanf(fields[i+3], "0x%x", dw1)
-			*function = extractPadFuncFromComment(line)
-			return 0
-		}
-	}
-	return -1
-}
-
-// useYourTemplate
-func useYourTemplate(line string, function *string,
-	id *string, dw0 *uint32, dw1 *uint32) int {
-
-	// ADD YOUR TEMPLATE HERE
-	*function = ""
-	*id = ""
-	*dw0 = 0
-	*dw1 = 0
-
-	fmt.Printf("ADD YOUR TEMPLATE!\n")
-	return -1
-}
-
 // registerInfoTemplate
 // line    : (in)  string from file with pad config map
 // *name   : (out) register name
diff --git a/util/intelp2m/parser/template_test.go b/util/intelp2m/parser/template_test.go
index 98ccb3fc0a..95f8ebf546 100644
--- a/util/intelp2m/parser/template_test.go
+++ b/util/intelp2m/parser/template_test.go
@@ -20,7 +20,7 @@ func TestTemp(t *testing.T) {
 			dw0, dw1 uint32
 		)
 		line := fmt.Sprintf("0x0520: 0x%08x%08x %s %s", ref_dw1, ref_dw0, ref_id, ref_fn)
-		_ = parser.UseInteltoolLogTemplate(line, &fn, &id, &dw0, &dw1)
+		_ = parser.UseTemplate(line, &fn, &id, &dw0, &dw1)
 		if fn != ref_fn {
 			t.Errorf("function from '%s':\nExpects:  '%s'\nActually: '%s'\n\n",
 				line, ref_fn, fn)
diff --git a/util/intelp2m/platforms/adl/macro.go b/util/intelp2m/platforms/adl/macro.go
index d7b1f58f0b..2c4b5d81cf 100644
--- a/util/intelp2m/platforms/adl/macro.go
+++ b/util/intelp2m/platforms/adl/macro.go
@@ -1,14 +1,13 @@
 package adl
 
 import (
-	"strings"
 	"fmt"
+	"strings"
 
+	"review.coreboot.org/coreboot.git/util/intelp2m/fields"
+	"review.coreboot.org/coreboot.git/util/intelp2m/platforms/cnl"
 	"review.coreboot.org/coreboot.git/util/intelp2m/platforms/common"
 	"review.coreboot.org/coreboot.git/util/intelp2m/platforms/snr"
-	"review.coreboot.org/coreboot.git/util/intelp2m/platforms/cnl"
-	"review.coreboot.org/coreboot.git/util/intelp2m/config"
-	"review.coreboot.org/coreboot.git/util/intelp2m/fields"
 )
 
 const (
@@ -37,10 +36,6 @@ type PlatformSpecific struct {
 // RemmapRstSrc - remmap Pad Reset Source Config
 func (PlatformSpecific) RemmapRstSrc() {
 	macro := common.GetMacro()
-	if config.TemplateGet() != config.TempInteltool {
-		// Use reset source remapping only if the input file is inteltool.log dump
-		return
-	}
 	if strings.Contains(macro.PadIdGet(), "GPD") {
 		// See reset map for the Alderlake GPD Group in the Community 2:
 		// https://github.com/coreboot/coreboot/blob/master/src/soc/intel/alderlake/gpio.c#L21
@@ -51,9 +46,9 @@ func (PlatformSpecific) RemmapRstSrc() {
 	dw0 := macro.Register(PAD_CFG_DW0)
 	var remapping = map[uint8]uint32{
 		0: common.RST_RSMRST << common.PadRstCfgShift,
-		1: common.RST_DEEP   << common.PadRstCfgShift,
+		1: common.RST_DEEP << common.PadRstCfgShift,
 		2: common.RST_PLTRST << common.PadRstCfgShift,
-		3: common.RST_PWROK  << common.PadRstCfgShift,
+		3: common.RST_PWROK << common.PadRstCfgShift,
 	}
 	resetsrc, valid := remapping[dw0.GetResetConfig()]
 	if valid {
@@ -61,7 +56,7 @@ func (PlatformSpecific) RemmapRstSrc() {
 		ResetConfigFieldVal := (dw0.ValueGet() & 0x3fffffff) | remapping[dw0.GetResetConfig()]
 		dw0.ValueSet(ResetConfigFieldVal)
 	} else {
-		fmt.Println("Invalid Pad Reset Config [ 0x", resetsrc ," ] for ", macro.PadIdGet())
+		fmt.Println("Invalid Pad Reset Config [ 0x", resetsrc, " ] for ", macro.PadIdGet())
 	}
 	dw0.CntrMaskFieldsClear(common.PadRstCfgMask)
 }
diff --git a/util/intelp2m/platforms/cnl/macro.go b/util/intelp2m/platforms/cnl/macro.go
index ae568d5096..6aa6140ef9 100644
--- a/util/intelp2m/platforms/cnl/macro.go
+++ b/util/intelp2m/platforms/cnl/macro.go
@@ -1,12 +1,12 @@
 package cnl
 
 import (
-	"strings"
 	"fmt"
+	"strings"
 
-	"review.coreboot.org/coreboot.git/util/intelp2m/platforms/common"
 	"review.coreboot.org/coreboot.git/util/intelp2m/config"
 	"review.coreboot.org/coreboot.git/util/intelp2m/fields"
+	"review.coreboot.org/coreboot.git/util/intelp2m/platforms/common"
 	"review.coreboot.org/coreboot.git/util/intelp2m/platforms/snr"
 )
 
@@ -35,13 +35,9 @@ type PlatformSpecific struct {
 // RemmapRstSrc - remmap Pad Reset Source Config
 func (PlatformSpecific) RemmapRstSrc() {
 	macro := common.GetMacro()
-	if config.TemplateGet() != config.TempInteltool {
-		// Use reset source remapping only if the input file is inteltool.log dump
-		return
-	}
 	if strings.Contains(macro.PadIdGet(), "GPP_A") ||
-			strings.Contains(macro.PadIdGet(), "GPP_B") ||
-			strings.Contains(macro.PadIdGet(), "GPP_G") {
+		strings.Contains(macro.PadIdGet(), "GPP_B") ||
+		strings.Contains(macro.PadIdGet(), "GPP_G") {
 		// See reset map for the Cannonlake Groups the Community 0:
 		// https://github.com/coreboot/coreboot/blob/master/src/soc/intel/cannonlake/gpio.c#L14
 		// remmap is not required because it is the same as common.
@@ -51,7 +47,7 @@ func (PlatformSpecific) RemmapRstSrc() {
 	dw0 := macro.Register(PAD_CFG_DW0)
 	var remapping = map[uint8]uint32{
 		0: common.RST_RSMRST << common.PadRstCfgShift,
-		1: common.RST_DEEP   << common.PadRstCfgShift,
+		1: common.RST_DEEP << common.PadRstCfgShift,
 		2: common.RST_PLTRST << common.PadRstCfgShift,
 	}
 	resetsrc, valid := remapping[dw0.GetResetConfig()]
@@ -60,7 +56,7 @@ func (PlatformSpecific) RemmapRstSrc() {
 		ResetConfigFieldVal := (dw0.ValueGet() & 0x3fffffff) | remapping[dw0.GetResetConfig()]
 		dw0.ValueSet(ResetConfigFieldVal)
 	} else {
-		fmt.Println("Invalid Pad Reset Config [ 0x", resetsrc ," ] for ", macro.PadIdGet())
+		fmt.Println("Invalid Pad Reset Config [ 0x", resetsrc, " ] for ", macro.PadIdGet())
 	}
 	dw0.CntrMaskFieldsClear(common.PadRstCfgMask)
 }
@@ -85,9 +81,9 @@ func (PlatformSpecific) Pull() {
 	if !valid {
 		str = "INVALID"
 		fmt.Println("Error",
-				macro.PadIdGet(),
-				" invalid TERM value = ",
-				int(dw1.GetTermination()))
+			macro.PadIdGet(),
+			" invalid TERM value = ",
+			int(dw1.GetTermination()))
 	}
 	macro.Separator().Add(str)
 }
@@ -146,7 +142,7 @@ func (PlatformSpecific) GpiMacroAdd() {
 	macro := common.GetMacro()
 	var ids []string
 	macro.Set("PAD_CFG_GPI")
-	for routeid, isRoute := range map[string]func() (bool) {
+	for routeid, isRoute := range map[string]func() bool{
 		"IOAPIC": ioApicRoute,
 		"SCI":    sciRoute,
 		"SMI":    smiRoute,
@@ -204,7 +200,7 @@ func (platform PlatformSpecific) NoConnMacroAdd() {
 // return: string of macro
 //         error
 func (PlatformSpecific) GenMacro(id string, dw0 uint32, dw1 uint32, ownership uint8) string {
-	macro := common.GetInstanceMacro(PlatformSpecific{InheritanceMacro : snr.PlatformSpecific{}},
+	macro := common.GetInstanceMacro(PlatformSpecific{InheritanceMacro: snr.PlatformSpecific{}},
 		fields.InterfaceGet())
 	macro.Clear()
 	macro.Register(PAD_CFG_DW0).CntrMaskFieldsClear(common.AllFields)
diff --git a/util/intelp2m/platforms/ebg/macro.go b/util/intelp2m/platforms/ebg/macro.go
index 64d6f32409..1fb0a3273a 100644
--- a/util/intelp2m/platforms/ebg/macro.go
+++ b/util/intelp2m/platforms/ebg/macro.go
@@ -3,11 +3,10 @@ package ebg
 import (
 	"fmt"
 
-	"review.coreboot.org/coreboot.git/util/intelp2m/platforms/common"
-	"review.coreboot.org/coreboot.git/util/intelp2m/config"
 	"review.coreboot.org/coreboot.git/util/intelp2m/fields"
-	"review.coreboot.org/coreboot.git/util/intelp2m/platforms/snr"
 	"review.coreboot.org/coreboot.git/util/intelp2m/platforms/cnl"
+	"review.coreboot.org/coreboot.git/util/intelp2m/platforms/common"
+	"review.coreboot.org/coreboot.git/util/intelp2m/platforms/snr"
 )
 
 const (
@@ -37,14 +36,10 @@ type PlatformSpecific struct {
 // RemmapRstSrc - remmap Pad Reset Source Config
 func (PlatformSpecific) RemmapRstSrc() {
 	macro := common.GetMacro()
-	if config.TemplateGet() != config.TempInteltool {
-		// Use reset source remapping only if the input file is inteltool.log dump
-		return
-	}
 	dw0 := macro.Register(PAD_CFG_DW0)
 	var remapping = map[uint8]uint32{
 		0: common.RST_RSMRST << common.PadRstCfgShift,
-		1: common.RST_DEEP   << common.PadRstCfgShift,
+		1: common.RST_DEEP << common.PadRstCfgShift,
 		2: common.RST_PLTRST << common.PadRstCfgShift,
 	}
 	resetsrc, valid := remapping[dw0.GetResetConfig()]
@@ -53,7 +48,7 @@ func (PlatformSpecific) RemmapRstSrc() {
 		ResetConfigFieldVal := (dw0.ValueGet() & 0x3fffffff) | remapping[dw0.GetResetConfig()]
 		dw0.ValueSet(ResetConfigFieldVal)
 	} else {
-		fmt.Println("Invalid Pad Reset Config [ 0x", resetsrc ," ] for ", macro.PadIdGet())
+		fmt.Println("Invalid Pad Reset Config [ 0x", resetsrc, " ] for ", macro.PadIdGet())
 	}
 	dw0.CntrMaskFieldsClear(common.PadRstCfgMask)
 }
@@ -88,12 +83,13 @@ func (platform PlatformSpecific) NoConnMacroAdd() {
 // dw0 : DW0 config register value
 // dw1 : DW1 config register value
 // return: string of macro
-//         error
+//
+//	error
 func (platform PlatformSpecific) GenMacro(id string, dw0 uint32, dw1 uint32, ownership uint8) string {
 	macro := common.GetInstanceMacro(
 		PlatformSpecific{
-			InheritanceMacro : cnl.PlatformSpecific{
-				InheritanceMacro : snr.PlatformSpecific{},
+			InheritanceMacro: cnl.PlatformSpecific{
+				InheritanceMacro: snr.PlatformSpecific{},
 			},
 		},
 		fields.InterfaceGet(),
diff --git a/util/intelp2m/platforms/jsl/macro.go b/util/intelp2m/platforms/jsl/macro.go
index 89cf2f0cc7..42c254b190 100644
--- a/util/intelp2m/platforms/jsl/macro.go
+++ b/util/intelp2m/platforms/jsl/macro.go
@@ -1,14 +1,13 @@
 package jsl
 
 import (
-	"strings"
 	"fmt"
+	"strings"
 
+	"review.coreboot.org/coreboot.git/util/intelp2m/fields"
+	"review.coreboot.org/coreboot.git/util/intelp2m/platforms/cnl"
 	"review.coreboot.org/coreboot.git/util/intelp2m/platforms/common"
 	"review.coreboot.org/coreboot.git/util/intelp2m/platforms/snr"
-	"review.coreboot.org/coreboot.git/util/intelp2m/platforms/cnl"
-	"review.coreboot.org/coreboot.git/util/intelp2m/config"
-	"review.coreboot.org/coreboot.git/util/intelp2m/fields"
 )
 
 const (
@@ -37,15 +36,11 @@ type PlatformSpecific struct {
 // RemmapRstSrc - remmap Pad Reset Source Config
 func (PlatformSpecific) RemmapRstSrc() {
 	macro := common.GetMacro()
-	if config.TemplateGet() != config.TempInteltool {
-		// Use reset source remapping only if the input file is inteltool.log dump
-		return
-	}
 	if strings.Contains(macro.PadIdGet(), "GPP_F") ||
-			strings.Contains(macro.PadIdGet(), "GPP_B") ||
-			strings.Contains(macro.PadIdGet(), "GPP_A") ||
-			strings.Contains(macro.PadIdGet(), "GPP_S") ||
-			strings.Contains(macro.PadIdGet(), "GPP_R") {
+		strings.Contains(macro.PadIdGet(), "GPP_B") ||
+		strings.Contains(macro.PadIdGet(), "GPP_A") ||
+		strings.Contains(macro.PadIdGet(), "GPP_S") ||
+		strings.Contains(macro.PadIdGet(), "GPP_R") {
 		// See reset map for the Jasper Lake Community 0:
 		// https://github.com/coreboot/coreboot/blob/master/src/soc/intel/jasperlake/gpio.c#L21
 		// remmap is not required because it is the same as common.
@@ -55,7 +50,7 @@ func (PlatformSpecific) RemmapRstSrc() {
 	dw0 := macro.Register(PAD_CFG_DW0)
 	var remapping = map[uint8]uint32{
 		0: common.RST_RSMRST << common.PadRstCfgShift,
-		1: common.RST_DEEP   << common.PadRstCfgShift,
+		1: common.RST_DEEP << common.PadRstCfgShift,
 		2: common.RST_PLTRST << common.PadRstCfgShift,
 	}
 	resetsrc, valid := remapping[dw0.GetResetConfig()]
@@ -64,7 +59,7 @@ func (PlatformSpecific) RemmapRstSrc() {
 		ResetConfigFieldVal := (dw0.ValueGet() & 0x3fffffff) | remapping[dw0.GetResetConfig()]
 		dw0.ValueSet(ResetConfigFieldVal)
 	} else {
-		fmt.Println("Invalid Pad Reset Config [ 0x", resetsrc ," ] for ", macro.PadIdGet())
+		fmt.Println("Invalid Pad Reset Config [ 0x", resetsrc, " ] for ", macro.PadIdGet())
 	}
 	dw0.CntrMaskFieldsClear(common.PadRstCfgMask)
 }
@@ -99,7 +94,8 @@ func (platform PlatformSpecific) NoConnMacroAdd() {
 // dw0 : DW0 config register value
 // dw1 : DW1 config register value
 // return: string of macro
-//         error
+//
+//	error
 func (PlatformSpecific) GenMacro(id string, dw0 uint32, dw1 uint32, ownership uint8) string {
 	macro := common.GetInstanceMacro(
 		PlatformSpecific{
diff --git a/util/intelp2m/platforms/lbg/macro.go b/util/intelp2m/platforms/lbg/macro.go
index 3c71ca87dc..8a706e3d5d 100644
--- a/util/intelp2m/platforms/lbg/macro.go
+++ b/util/intelp2m/platforms/lbg/macro.go
@@ -3,9 +3,8 @@ package lbg
 import (
 	"fmt"
 
-	"review.coreboot.org/coreboot.git/util/intelp2m/platforms/common"
-	"review.coreboot.org/coreboot.git/util/intelp2m/config"
 	"review.coreboot.org/coreboot.git/util/intelp2m/fields"
+	"review.coreboot.org/coreboot.git/util/intelp2m/platforms/common"
 	"review.coreboot.org/coreboot.git/util/intelp2m/platforms/snr"
 )
 
@@ -36,14 +35,10 @@ type PlatformSpecific struct {
 // RemmapRstSrc - remmap Pad Reset Source Config
 func (PlatformSpecific) RemmapRstSrc() {
 	macro := common.GetMacro()
-	if config.TemplateGet() != config.TempInteltool {
-		// Use reset source remapping only if the input file is inteltool.log dump
-		return
-	}
 	dw0 := macro.Register(PAD_CFG_DW0)
 	var remapping = map[uint8]uint32{
 		0: common.RST_RSMRST << common.PadRstCfgShift,
-		1: common.RST_DEEP   << common.PadRstCfgShift,
+		1: common.RST_DEEP << common.PadRstCfgShift,
 		2: common.RST_PLTRST << common.PadRstCfgShift,
 	}
 	resetsrc, valid := remapping[dw0.GetResetConfig()]
@@ -52,7 +47,7 @@ func (PlatformSpecific) RemmapRstSrc() {
 		ResetConfigFieldVal := (dw0.ValueGet() & 0x3fffffff) | remapping[dw0.GetResetConfig()]
 		dw0.ValueSet(ResetConfigFieldVal)
 	} else {
-		fmt.Println("Invalid Pad Reset Config [ 0x", resetsrc ," ] for ", macro.PadIdGet())
+		fmt.Println("Invalid Pad Reset Config [ 0x", resetsrc, " ] for ", macro.PadIdGet())
 	}
 	dw0.CntrMaskFieldsClear(common.PadRstCfgMask)
 }
@@ -91,8 +86,8 @@ func (platform PlatformSpecific) NoConnMacroAdd() {
 func (platform PlatformSpecific) GenMacro(id string, dw0 uint32, dw1 uint32, ownership uint8) string {
 	// The GPIO controller architecture in Lewisburg and Sunrise are very similar,
 	// so we will inherit some platform-dependent functions from Sunrise.
-	macro := common.GetInstanceMacro(PlatformSpecific{InheritanceMacro : snr.PlatformSpecific{}},
-			fields.InterfaceGet())
+	macro := common.GetInstanceMacro(PlatformSpecific{InheritanceMacro: snr.PlatformSpecific{}},
+		fields.InterfaceGet())
 	macro.Clear()
 	macro.Register(PAD_CFG_DW0).CntrMaskFieldsClear(common.AllFields)
 	macro.Register(PAD_CFG_DW1).CntrMaskFieldsClear(common.AllFields)
diff --git a/util/intelp2m/platforms/mtl/macro.go b/util/intelp2m/platforms/mtl/macro.go
index 512dd719e3..06d05996c3 100644
--- a/util/intelp2m/platforms/mtl/macro.go
+++ b/util/intelp2m/platforms/mtl/macro.go
@@ -1,14 +1,13 @@
 package mtl
 
 import (
-	"strings"
 	"fmt"
+	"strings"
 
+	"review.coreboot.org/coreboot.git/util/intelp2m/fields"
+	"review.coreboot.org/coreboot.git/util/intelp2m/platforms/cnl"
 	"review.coreboot.org/coreboot.git/util/intelp2m/platforms/common"
 	"review.coreboot.org/coreboot.git/util/intelp2m/platforms/snr"
-	"review.coreboot.org/coreboot.git/util/intelp2m/platforms/cnl"
-	"review.coreboot.org/coreboot.git/util/intelp2m/config"
-	"review.coreboot.org/coreboot.git/util/intelp2m/fields"
 )
 
 const (
@@ -37,23 +36,19 @@ type PlatformSpecific struct {
 // RemmapRstSrc - remmap Pad Reset Source Config
 func (PlatformSpecific) RemmapRstSrc() {
 	macro := common.GetMacro()
-	if config.TemplateGet() != config.TempInteltool {
-		// Use reset source remapping only if the input file is inteltool.log dump
-		return
-	}
 	if strings.Contains(macro.PadIdGet(), "GPD") {
 		// See reset map for the MeteorLake GPD group at
-                // https://github.com/coreboot/coreboot/blob/master/src/soc/intel/meteorlake/gpio.c#L10
-                // remmap is not required because it is the same as common.
+		// https://github.com/coreboot/coreboot/blob/master/src/soc/intel/meteorlake/gpio.c#L10
+		// remmap is not required because it is the same as common.
 		return
 	}
 
 	dw0 := macro.Register(PAD_CFG_DW0)
 	var remapping = map[uint8]uint32{
 		0: common.RST_RSMRST << common.PadRstCfgShift,
-		1: common.RST_DEEP   << common.PadRstCfgShift,
+		1: common.RST_DEEP << common.PadRstCfgShift,
 		2: common.RST_PLTRST << common.PadRstCfgShift,
-		3: common.RST_PWROK  << common.PadRstCfgShift,
+		3: common.RST_PWROK << common.PadRstCfgShift,
 	}
 	resetsrc, valid := remapping[dw0.GetResetConfig()]
 	if valid {
@@ -61,7 +56,7 @@ func (PlatformSpecific) RemmapRstSrc() {
 		ResetConfigFieldVal := (dw0.ValueGet() & 0x3fffffff) | remapping[dw0.GetResetConfig()]
 		dw0.ValueSet(ResetConfigFieldVal)
 	} else {
-		fmt.Println("Invalid Pad Reset Config [ 0x", resetsrc ," ] for ", macro.PadIdGet())
+		fmt.Println("Invalid Pad Reset Config [ 0x", resetsrc, " ] for ", macro.PadIdGet())
 	}
 	dw0.CntrMaskFieldsClear(common.PadRstCfgMask)
 }
@@ -92,12 +87,12 @@ func (platform PlatformSpecific) NoConnMacroAdd() {
 	platform.InheritanceMacro.NoConnMacroAdd()
 }
 
-
 // GenMacro - generate pad macro
 // dw0 : DW0 config register value
 // dw1 : DW1 config register value
 // return: string of macro
-//         error
+//
+//	error
 func (PlatformSpecific) GenMacro(id string, dw0 uint32, dw1 uint32, ownership uint8) string {
 	macro := common.GetInstanceMacro(
 		PlatformSpecific{
diff --git a/util/intelp2m/platforms/snr/macro.go b/util/intelp2m/platforms/snr/macro.go
index 382616c6a3..d96e83e2e2 100644
--- a/util/intelp2m/platforms/snr/macro.go
+++ b/util/intelp2m/platforms/snr/macro.go
@@ -1,12 +1,12 @@
 package snr
 
 import (
-	"strings"
 	"fmt"
+	"strings"
 
-	"review.coreboot.org/coreboot.git/util/intelp2m/platforms/common"
 	"review.coreboot.org/coreboot.git/util/intelp2m/config"
 	"review.coreboot.org/coreboot.git/util/intelp2m/fields"
+	"review.coreboot.org/coreboot.git/util/intelp2m/platforms/common"
 )
 
 const (
@@ -20,15 +20,11 @@ const (
 	MAX_DW_NUM  = common.MAX_DW_NUM
 )
 
-type PlatformSpecific struct {}
+type PlatformSpecific struct{}
 
 // RemmapRstSrc - remmap Pad Reset Source Config
 func (PlatformSpecific) RemmapRstSrc() {
 	macro := common.GetMacro()
-	if config.TemplateGet() != config.TempInteltool {
-		// Use reset source remapping only if the input file is inteltool.log dump
-		return
-	}
 	if strings.Contains(macro.PadIdGet(), "GPD") {
 		// See reset map for the Sunrise GPD Group in the Community 2:
 		// https://github.com/coreboot/coreboot/blob/master/src/soc/intel/skylake/gpio.c#L15
@@ -39,7 +35,7 @@ func (PlatformSpecific) RemmapRstSrc() {
 	dw0 := macro.Register(PAD_CFG_DW0)
 	var remapping = map[uint8]uint32{
 		0: common.RST_RSMRST << common.PadRstCfgShift,
-		1: common.RST_DEEP   << common.PadRstCfgShift,
+		1: common.RST_DEEP << common.PadRstCfgShift,
 		2: common.RST_PLTRST << common.PadRstCfgShift,
 	}
 	resetsrc, valid := remapping[dw0.GetResetConfig()]
@@ -48,7 +44,7 @@ func (PlatformSpecific) RemmapRstSrc() {
 		ResetConfigFieldVal := (dw0.ValueGet() & 0x3fffffff) | remapping[dw0.GetResetConfig()]
 		dw0.ValueSet(ResetConfigFieldVal)
 	} else {
-		fmt.Println("Invalid Pad Reset Config [ 0x", resetsrc ," ] for ", macro.PadIdGet())
+		fmt.Println("Invalid Pad Reset Config [ 0x", resetsrc, " ] for ", macro.PadIdGet())
 	}
 	dw0.CntrMaskFieldsClear(common.PadRstCfgMask)
 }
@@ -73,9 +69,9 @@ func (PlatformSpecific) Pull() {
 	if !valid {
 		str = "INVALID"
 		fmt.Println("Error",
-				macro.PadIdGet(),
-				" invalid TERM value = ",
-				int(dw1.GetTermination()))
+			macro.PadIdGet(),
+			" invalid TERM value = ",
+			int(dw1.GetTermination()))
 	}
 	macro.Separator().Add(str)
 }
@@ -146,7 +142,7 @@ func (PlatformSpecific) GpiMacroAdd() {
 	macro := common.GetMacro()
 	var ids []string
 	macro.Set("PAD_CFG_GPI")
-	for routeid, isRoute := range map[string]func() (bool) {
+	for routeid, isRoute := range map[string]func() bool{
 		"IOAPIC": ioApicRoute,
 		"SCI":    sciRoute,
 		"SMI":    smiRoute,
diff --git a/util/intelp2m/platforms/tgl/macro.go b/util/intelp2m/platforms/tgl/macro.go
index 3b436ee3bb..c925eeb30c 100644
--- a/util/intelp2m/platforms/tgl/macro.go
+++ b/util/intelp2m/platforms/tgl/macro.go
@@ -1,14 +1,13 @@
 package tgl
 
 import (
-	"strings"
 	"fmt"
+	"strings"
 
+	"review.coreboot.org/coreboot.git/util/intelp2m/fields"
+	"review.coreboot.org/coreboot.git/util/intelp2m/platforms/cnl"
 	"review.coreboot.org/coreboot.git/util/intelp2m/platforms/common"
 	"review.coreboot.org/coreboot.git/util/intelp2m/platforms/snr"
-	"review.coreboot.org/coreboot.git/util/intelp2m/platforms/cnl"
-	"review.coreboot.org/coreboot.git/util/intelp2m/config"
-	"review.coreboot.org/coreboot.git/util/intelp2m/fields"
 )
 
 const (
@@ -37,10 +36,6 @@ type PlatformSpecific struct {
 // RemmapRstSrc - remmap Pad Reset Source Config
 func (PlatformSpecific) RemmapRstSrc() {
 	macro := common.GetMacro()
-	if config.TemplateGet() != config.TempInteltool {
-		// Use reset source remapping only if the input file is inteltool.log dump
-		return
-	}
 	if strings.Contains(macro.PadIdGet(), "GPD") {
 		// See reset map for the TigerLake Community 2:
 		// https://github.com/coreboot/coreboot/blob/master/src/soc/intel/tigerlake/gpio.c#L21
@@ -51,7 +46,7 @@ func (PlatformSpecific) RemmapRstSrc() {
 	dw0 := macro.Register(PAD_CFG_DW0)
 	var remapping = map[uint8]uint32{
 		0: common.RST_RSMRST << common.PadRstCfgShift,
-		1: common.RST_DEEP   << common.PadRstCfgShift,
+		1: common.RST_DEEP << common.PadRstCfgShift,
 		2: common.RST_PLTRST << common.PadRstCfgShift,
 	}
 	resetsrc, valid := remapping[dw0.GetResetConfig()]
@@ -60,7 +55,7 @@ func (PlatformSpecific) RemmapRstSrc() {
 		ResetConfigFieldVal := (dw0.ValueGet() & 0x3fffffff) | remapping[dw0.GetResetConfig()]
 		dw0.ValueSet(ResetConfigFieldVal)
 	} else {
-		fmt.Println("Invalid Pad Reset Config [ 0x", resetsrc ," ] for ", macro.PadIdGet())
+		fmt.Println("Invalid Pad Reset Config [ 0x", resetsrc, " ] for ", macro.PadIdGet())
 	}
 	dw0.CntrMaskFieldsClear(common.PadRstCfgMask)
 }
@@ -95,7 +90,8 @@ func (platform PlatformSpecific) NoConnMacroAdd() {
 // dw0 : DW0 config register value
 // dw1 : DW1 config register value
 // return: string of macro
-//         error
+//
+//	error
 func (PlatformSpecific) GenMacro(id string, dw0 uint32, dw1 uint32, ownership uint8) string {
 	macro := common.GetInstanceMacro(
 		PlatformSpecific{
diff --git a/util/intelp2m/version.txt b/util/intelp2m/version.txt
index 9459d4ba2a..5625e59da8 100644
--- a/util/intelp2m/version.txt
+++ b/util/intelp2m/version.txt
@@ -1 +1 @@
-1.1
+1.2

From 5fe0b88b157222191c0b8b9c3a9973a888449de7 Mon Sep 17 00:00:00 2001
From: Maxim Polyakov <max.senia.poliak@gmail.com>
Date: Sat, 26 Nov 2022 00:14:17 +0300
Subject: [PATCH 0249/3886] util/intelp2m/config: Rework configuration package

- Reduce the number of methods for updating settings and redefine types
  to make the code cleaner and more readable.
- Move the configuration to the p2m package to add settings from new
  utilities based on the intelp2m code.
- Make some code style fixes.

TEST: make test = PASS

Change-Id: Ia1b19ae3122bcf6ec740ae4683d62f31570670b1
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70308
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
---
 util/intelp2m/config/config.go             | 135 --------------------
 util/intelp2m/config/p2m/config.go         |  83 ++++++++++++
 util/intelp2m/fields/cb/cb.go              | 142 +++++++++++----------
 util/intelp2m/fields/fields.go             |  18 +--
 util/intelp2m/main.go                      |  93 ++++++--------
 util/intelp2m/parser/parser.go             |  32 ++---
 util/intelp2m/parser/parser_test.go        |  20 ++-
 util/intelp2m/platforms/apl/macro.go       |  46 +++----
 util/intelp2m/platforms/cnl/macro.go       |   9 +-
 util/intelp2m/platforms/common/macro.go    |  51 ++++----
 util/intelp2m/platforms/common/register.go |  13 +-
 util/intelp2m/platforms/snr/macro.go       |   9 +-
 util/intelp2m/platforms/test/suite.go      |  14 +-
 13 files changed, 306 insertions(+), 359 deletions(-)
 delete mode 100644 util/intelp2m/config/config.go
 create mode 100644 util/intelp2m/config/p2m/config.go

diff --git a/util/intelp2m/config/config.go b/util/intelp2m/config/config.go
deleted file mode 100644
index 7b4486b3be..0000000000
--- a/util/intelp2m/config/config.go
+++ /dev/null
@@ -1,135 +0,0 @@
-package config
-
-import "os"
-
-const (
-	SunriseType    uint8 = 0
-	LewisburgType  uint8 = 1
-	ApolloType     uint8 = 2
-	CannonType     uint8 = 3
-	TigerType      uint8 = 4
-	AlderType      uint8 = 5
-	JasperType     uint8 = 6
-	MeteorType     uint8 = 7
-	EmmitsburgType uint8 = 8
-)
-
-var key uint8 = SunriseType
-
-var platform = map[string]uint8{
-	"snr": SunriseType,
-	"lbg": LewisburgType,
-	"apl": ApolloType,
-	"cnl": CannonType,
-	"tgl": TigerType,
-	"adl": AlderType,
-	"jsl": JasperType,
-	"mtl": MeteorType,
-	"ebg": EmmitsburgType,
-}
-
-func PlatformSet(name string) int {
-	if platformType, valid := platform[name]; valid {
-		key = platformType
-		return 0
-	}
-	return -1
-}
-func PlatformGet() uint8 {
-	return key
-}
-func IsPlatform(platformType uint8) bool {
-	return platformType == key
-}
-func IsPlatformApollo() bool {
-	return IsPlatform(ApolloType)
-}
-func IsPlatformSunrise() bool {
-	return IsPlatform(SunriseType)
-}
-func IsPlatformLewisburg() bool {
-	return IsPlatform(LewisburgType)
-}
-func IsPlatformCannonLake() bool {
-	return IsPlatform(CannonType)
-}
-func IsPlatformTigerLake() bool {
-	return IsPlatform(TigerType)
-}
-func IsPlatformAlderLakeH() bool {
-	return IsPlatform(AlderType)
-}
-func IsPlatformMeteorLake() bool {
-	return IsPlatform(MeteorType)
-}
-func IsPlatformEmmitsburg() bool {
-	return IsPlatform(EmmitsburgType)
-}
-
-var InputRegDumpFile *os.File = nil
-var OutputGenFile *os.File = nil
-
-var ignoredFieldsFormat bool = false
-
-func IgnoredFieldsFlagSet(flag bool) {
-	ignoredFieldsFormat = flag
-}
-func AreFieldsIgnored() bool {
-	return ignoredFieldsFormat
-}
-
-var nonCheckingFlag bool = false
-
-func NonCheckingFlagSet(flag bool) {
-	nonCheckingFlag = flag
-}
-func IsNonCheckingFlagUsed() bool {
-	return nonCheckingFlag
-}
-
-var infolevel int = 0
-
-func InfoLevelSet(lvl int) {
-	infolevel = lvl
-}
-func InfoLevelGet() int {
-	return infolevel
-}
-
-var fldstyle uint8 = CbFlds
-
-const (
-	NoFlds  uint8 = 0
-	CbFlds  uint8 = 1 // coreboot style
-	FspFlds uint8 = 2 // FSP/edk2 style
-	RawFlds uint8 = 3 // raw DW0/1 values
-)
-
-var fldstylemap = map[string]uint8{
-	"none": NoFlds,
-	"cb":   CbFlds,
-	"fsp":  FspFlds,
-	"raw":  RawFlds}
-
-func FldStyleSet(name string) int {
-	if style, valid := fldstylemap[name]; valid {
-		fldstyle = style
-		return 0
-	}
-	return -1
-}
-func FldStyleGet() uint8 {
-	return fldstyle
-}
-func IsFieldsMacroUsed() bool {
-	return FldStyleGet() != NoFlds
-}
-func IsCbStyleMacro() bool {
-	return FldStyleGet() == CbFlds
-}
-func IsFspStyleMacro() bool {
-	return FldStyleGet() == FspFlds
-}
-func IsRawFields() bool {
-	return FldStyleGet() == RawFlds
-}
diff --git a/util/intelp2m/config/p2m/config.go b/util/intelp2m/config/p2m/config.go
new file mode 100644
index 0000000000..ce03ee0c36
--- /dev/null
+++ b/util/intelp2m/config/p2m/config.go
@@ -0,0 +1,83 @@
+package p2m
+
+import (
+	"fmt"
+	"os"
+)
+
+type PlatformType int
+type FieldType int
+
+const (
+	Sunrise PlatformType = iota
+	Lewisburg
+	Apollo
+	Cannon
+	Alder
+	Jasper
+	Tiger
+	Meteor
+	Emmitsburg
+)
+
+const (
+	NoFlds  FieldType = iota
+	CbFlds            // coreboot style
+	FspFlds           // FSP/edk2 style
+	RawFlds           // raw DW0/1 values
+)
+
+var platforms = map[string]PlatformType{
+	"snr": Sunrise,
+	"lbg": Lewisburg,
+	"apl": Apollo,
+	"cnl": Cannon,
+	"tgl": Tiger,
+	"adl": Alder,
+	"jsl": Jasper,
+	"mtl": Meteor,
+	"ebg": Emmitsburg,
+}
+
+var fields = map[string]FieldType{
+	"none": NoFlds,
+	"cb":   CbFlds,
+	"fsp":  FspFlds,
+	"raw":  RawFlds,
+}
+
+type Settings struct {
+	Version       string
+	Platform      PlatformType
+	Field         FieldType
+	InputFile     *os.File
+	OutputFile    *os.File
+	IgnoredFields bool
+	AutoCheck     bool
+	GenLevel      int
+}
+
+var Config = Settings{
+	Version:       "unknown",
+	Platform:      Sunrise,
+	Field:         CbFlds,
+	IgnoredFields: false,
+	AutoCheck:     true,
+	GenLevel:      0,
+}
+
+func SetPlatformType(format string) error {
+	if _, exist := platforms[format]; !exist {
+		return fmt.Errorf("unknown platform type %s", format)
+	}
+	Config.Platform = platforms[format]
+	return nil
+}
+
+func SetFieldType(format string) error {
+	if _, exist := fields[format]; !exist {
+		return fmt.Errorf("unknown field type %s", format)
+	}
+	Config.Field = fields[format]
+	return nil
+}
diff --git a/util/intelp2m/fields/cb/cb.go b/util/intelp2m/fields/cb/cb.go
index a70b2a63a8..efc80184f6 100644
--- a/util/intelp2m/fields/cb/cb.go
+++ b/util/intelp2m/fields/cb/cb.go
@@ -1,11 +1,11 @@
 package cb
 
 import (
-	"review.coreboot.org/coreboot.git/util/intelp2m/config"
+	"review.coreboot.org/coreboot.git/util/intelp2m/config/p2m"
 	"review.coreboot.org/coreboot.git/util/intelp2m/platforms/common"
 )
 
-type FieldMacros struct {}
+type FieldMacros struct{}
 
 // field - data structure for creating a new bitfield macro object
 // PAD_FUNC(NF3)
@@ -42,7 +42,9 @@ func generate(fields ...*field) {
 			}
 		}
 	}
-	if allhidden { macro.Add("0") }
+	if allhidden {
+		macro.Add("0")
+	}
 }
 
 // DecodeDW0 - decode value of DW0 register
@@ -50,80 +52,80 @@ func (FieldMacros) DecodeDW0() {
 	macro := common.GetMacro()
 	dw0 := macro.Register(common.PAD_CFG_DW0)
 	generate(
-		&field {
-			prefix : "PAD_FUNC",
+		&field{
+			prefix: "PAD_FUNC",
 			// TODO: Find another way to hide PAD_FUNC(GPIO) in the comment with
 			// ignored fields
-			unhide : config.InfoLevelGet() < 3 || dw0.GetPadMode() != 0,
-			configurator : func() { macro.Padfn() },
+			unhide:       p2m.Config.GenLevel < 3 || dw0.GetPadMode() != 0,
+			configurator: func() { macro.Padfn() },
 		},
 
-		&field {
-			prefix : "PAD_RESET",
-			unhide : dw0.GetResetConfig() != 0,
-			configurator : func() { macro.Rstsrc() },
+		&field{
+			prefix:       "PAD_RESET",
+			unhide:       dw0.GetResetConfig() != 0,
+			configurator: func() { macro.Rstsrc() },
 		},
 
-		&field {
-			prefix : "PAD_TRIG",
-			unhide : dw0.GetRXLevelEdgeConfiguration() != 0,
-			configurator : func() { macro.Trig() },
+		&field{
+			prefix:       "PAD_TRIG",
+			unhide:       dw0.GetRXLevelEdgeConfiguration() != 0,
+			configurator: func() { macro.Trig() },
 		},
 
-		&field {
-			prefix : "PAD_IRQ_ROUTE",
-			name   : "IOAPIC",
-			unhide : dw0.GetGPIOInputRouteIOxAPIC() != 0,
+		&field{
+			prefix: "PAD_IRQ_ROUTE",
+			name:   "IOAPIC",
+			unhide: dw0.GetGPIOInputRouteIOxAPIC() != 0,
 		},
 
-		&field {
-			prefix : "PAD_IRQ_ROUTE",
-			name   : "SCI",
-			unhide : dw0.GetGPIOInputRouteSCI() != 0,
+		&field{
+			prefix: "PAD_IRQ_ROUTE",
+			name:   "SCI",
+			unhide: dw0.GetGPIOInputRouteSCI() != 0,
 		},
 
-		&field {
-			prefix : "PAD_IRQ_ROUTE",
-			name   : "SMI",
-			unhide : dw0.GetGPIOInputRouteSMI() != 0,
+		&field{
+			prefix: "PAD_IRQ_ROUTE",
+			name:   "SMI",
+			unhide: dw0.GetGPIOInputRouteSMI() != 0,
 		},
 
-		&field {
-			prefix : "PAD_IRQ_ROUTE",
-			name   : "NMI",
-			unhide : dw0.GetGPIOInputRouteNMI() != 0,
+		&field{
+			prefix: "PAD_IRQ_ROUTE",
+			name:   "NMI",
+			unhide: dw0.GetGPIOInputRouteNMI() != 0,
 		},
 
-		&field {
-			prefix : "PAD_RX_POL",
-			unhide : dw0.GetRxInvert() != 0,
-			configurator : func() { macro.Invert() },
+		&field{
+			prefix:       "PAD_RX_POL",
+			unhide:       dw0.GetRxInvert() != 0,
+			configurator: func() { macro.Invert() },
 		},
 
-		&field {
-			prefix : "PAD_BUF",
-			unhide : dw0.GetGPIORxTxDisableStatus() != 0,
-			configurator : func() { macro.Bufdis() },
+		&field{
+			prefix:       "PAD_BUF",
+			unhide:       dw0.GetGPIORxTxDisableStatus() != 0,
+			configurator: func() { macro.Bufdis() },
 		},
 
-		&field {
-			name   : "(1 << 29)",
-			unhide : dw0.GetRXPadStateSelect() != 0,
+		&field{
+			name:   "(1 << 29)",
+			unhide: dw0.GetRXPadStateSelect() != 0,
 		},
 
-		&field {
-			name   : "(1 << 28)",
-			unhide : dw0.GetRXRawOverrideStatus() != 0,
+		&field{
+			name:   "(1 << 28)",
+			unhide: dw0.GetRXRawOverrideStatus() != 0,
 		},
 
-		&field {
-			name   : "(1 << 1)",
-			unhide : dw0.GetGPIORXState() != 0,
+		&field{
+			name:   "(1 << 1)",
+			unhide: dw0.GetGPIORXState() != 0,
 		},
 
-		&field {
-			name   : "1",
-			unhide : dw0.GetGPIOTXState() != 0,
+		&field{
+			name:   "1",
+			unhide: dw0.GetGPIOTXState() != 0,
 		},
 	)
 }
@@ -133,33 +135,33 @@ func (FieldMacros) DecodeDW1() {
 	macro := common.GetMacro()
 	dw1 := macro.Register(common.PAD_CFG_DW1)
 	generate(
-		&field {
-			name   : "PAD_CFG1_TOL_1V8",
-			unhide : dw1.GetPadTol() != 0,
+		&field{
+			name:   "PAD_CFG1_TOL_1V8",
+			unhide: dw1.GetPadTol() != 0,
 		},
 
-		&field {
-			prefix : "PAD_PULL",
-			unhide : dw1.GetTermination() != 0,
-			configurator : func() { macro.Pull() },
+		&field{
+			prefix:       "PAD_PULL",
+			unhide:       dw1.GetTermination() != 0,
+			configurator: func() { macro.Pull() },
 		},
 
-		&field {
-			prefix : "PAD_IOSSTATE",
-			unhide : dw1.GetIOStandbyState() != 0,
-			configurator : func() { macro.IOSstate() },
+		&field{
+			prefix:       "PAD_IOSSTATE",
+			unhide:       dw1.GetIOStandbyState() != 0,
+			configurator: func() { macro.IOSstate() },
 		},
 
-		&field {
-			prefix : "PAD_IOSTERM",
-			unhide : dw1.GetIOStandbyTermination() != 0,
-			configurator : func() { macro.IOTerm() },
+		&field{
+			prefix:       "PAD_IOSTERM",
+			unhide:       dw1.GetIOStandbyTermination() != 0,
+			configurator: func() { macro.IOTerm() },
 		},
 
-		&field {
-			prefix : "PAD_CFG_OWN_GPIO",
-			unhide : macro.IsOwnershipDriver(),
-			configurator : func() { macro.Own() },
+		&field{
+			prefix:       "PAD_CFG_OWN_GPIO",
+			unhide:       macro.IsOwnershipDriver(),
+			configurator: func() { macro.Own() },
 		},
 	)
 }
diff --git a/util/intelp2m/fields/fields.go b/util/intelp2m/fields/fields.go
index 4f14c815d2..4e41aff4ca 100644
--- a/util/intelp2m/fields/fields.go
+++ b/util/intelp2m/fields/fields.go
@@ -1,21 +1,21 @@
 package fields
 
 import (
-	"review.coreboot.org/coreboot.git/util/intelp2m/config"
-	"review.coreboot.org/coreboot.git/util/intelp2m/platforms/common"
-	"review.coreboot.org/coreboot.git/util/intelp2m/fields/fsp"
+	"review.coreboot.org/coreboot.git/util/intelp2m/config/p2m"
 	"review.coreboot.org/coreboot.git/util/intelp2m/fields/cb"
+	"review.coreboot.org/coreboot.git/util/intelp2m/fields/fsp"
 	"review.coreboot.org/coreboot.git/util/intelp2m/fields/raw"
+	"review.coreboot.org/coreboot.git/util/intelp2m/platforms/common"
 )
 
 // InterfaceSet - set the interface for decoding configuration
 // registers DW0 and DW1.
 func InterfaceGet() common.Fields {
-	var fldstylemap = map[uint8]common.Fields{
-		config.NoFlds  : cb.FieldMacros{}, // analyze fields using cb macros
-		config.CbFlds  : cb.FieldMacros{},
-		config.FspFlds : fsp.FieldMacros{},
-		config.RawFlds : raw.FieldMacros{},
+	var fldstylemap = map[p2m.FieldType]common.Fields{
+		p2m.NoFlds:  cb.FieldMacros{}, // analyze fields using cb macros
+		p2m.CbFlds:  cb.FieldMacros{},
+		p2m.FspFlds: fsp.FieldMacros{},
+		p2m.RawFlds: raw.FieldMacros{},
 	}
-	return fldstylemap[config.FldStyleGet()]
+	return fldstylemap[p2m.Config.Field]
 }
diff --git a/util/intelp2m/main.go b/util/intelp2m/main.go
index 25ae03aaef..f0e2203c3f 100644
--- a/util/intelp2m/main.go
+++ b/util/intelp2m/main.go
@@ -4,22 +4,23 @@ import (
 	"flag"
 	"fmt"
 	"os"
+	"path/filepath"
 
-	"review.coreboot.org/coreboot.git/util/intelp2m/config"
+	"review.coreboot.org/coreboot.git/util/intelp2m/config/p2m"
 	"review.coreboot.org/coreboot.git/util/intelp2m/parser"
 )
 
 type Printer struct{}
 
 func (Printer) Linef(lvl int, format string, args ...interface{}) {
-	if config.InfoLevelGet() >= lvl {
-		fmt.Fprintf(config.OutputGenFile, format, args...)
+	if p2m.Config.GenLevel >= lvl {
+		fmt.Fprintf(p2m.Config.OutputFile, format, args...)
 	}
 }
 
 func (Printer) Line(lvl int, str string) {
-	if config.InfoLevelGet() >= lvl {
-		fmt.Fprint(config.OutputGenFile, str)
+	if p2m.Config.GenLevel >= lvl {
+		fmt.Fprint(p2m.Config.OutputFile, str)
 	}
 }
 
@@ -36,25 +37,22 @@ func printVersion() {
 // main
 func main() {
 	// Command line arguments
-	inputFileName := flag.String("file",
-		"inteltool.log",
+	inputFilePath := flag.String("file", "inteltool.log",
 		"the path to the inteltool log file\n")
 
-	outputFileName := flag.String("o",
+	outputFilePath := flag.String("o",
 		"generate/gpio.h",
 		"the path to the generated file with GPIO configuration\n")
 
-	ignFlag := flag.Bool("ign",
-		false,
+	ignored := flag.Bool("ign", false,
 		"exclude fields that should be ignored from advanced macros\n")
 
-	nonCheckFlag := flag.Bool("n",
-		false,
+	unchecking := flag.Bool("n", false,
 		"Generate macros without checking.\n"+
 			"\tIn this case, some fields of the configuration registers\n"+
 			"\tDW0 will be ignored.\n")
 
-	infoLevels := []*bool{
+	levels := []*bool{
 		flag.Bool("i", false, "Show pads function in the comments"),
 		flag.Bool("ii", false, "Show DW0/DW1 value in the comments"),
 		flag.Bool("iii", false, "Show ignored bit fields in the comments"),
@@ -72,63 +70,55 @@ func main() {
 		"\tmtl - MeteorLake SoC\n"+
 		"\tebg - Emmitsburg PCH with Xeon SP\n")
 
-	fieldstyle := flag.String("fld", "none", "set fields macros style:\n"+
+	field := flag.String("fld", "none", "set fields macros style:\n"+
 		"\tcb  - use coreboot style for bit fields macros\n"+
 		"\tfsp - use fsp style\n"+
 		"\traw - do not convert, print as is\n")
 
-	printVersion()
 	flag.Parse()
+	printVersion()
 
-	config.IgnoredFieldsFlagSet(*ignFlag)
-	config.NonCheckingFlagSet(*nonCheckFlag)
-
-	for level, flag := range infoLevels {
-		if *flag {
-			config.InfoLevelSet(level + 1)
+	// settings
+	p2m.Config.Version = Version
+	p2m.Config.IgnoredFields = *ignored
+	p2m.Config.AutoCheck = !(*unchecking)
+	for level, set := range levels {
+		if *set {
+			p2m.Config.GenLevel = level + 1
 			fmt.Printf("Info level: Use level %d!\n", level+1)
 			break
 		}
 	}
 
-	if valid := config.PlatformSet(*platform); valid != 0 {
-		fmt.Printf("Error: invalid platform -%s!\n", *platform)
+	if err := p2m.SetPlatformType(*platform); err != nil {
+		fmt.Printf("Error: %v\n", err)
 		os.Exit(1)
 	}
 
-	fmt.Println("Log file:", *inputFileName)
-	fmt.Println("Output generated file:", *outputFileName)
-
-	inputRegDumpFile, err := os.Open(*inputFileName)
-	if err != nil {
-		fmt.Printf("Error: inteltool log file was not found!\n")
+	if err := p2m.SetFieldType(*field); err != nil {
+		fmt.Printf("Error: %v\n", err)
 		os.Exit(1)
 	}
 
-	if config.FldStyleSet(*fieldstyle) != 0 {
-		fmt.Printf("Error! Unknown bit fields style option -%s!\n", *fieldstyle)
+	if file, err := os.Open(*inputFilePath); err != nil {
+		fmt.Printf("input file error: %v", err)
+		os.Exit(1)
+	} else {
+		p2m.Config.InputFile = file
+	}
+	defer p2m.Config.InputFile.Close()
+
+	if err := os.MkdirAll(filepath.Dir(*outputFilePath), os.ModePerm); err != nil {
+		fmt.Printf("failed to create output directory: %v", err)
 		os.Exit(1)
 	}
-
-	// create dir for output files
-	err = os.MkdirAll("generate", os.ModePerm)
-	if err != nil {
-		fmt.Printf("Error! Can not create a directory for the generated files!\n")
+	if file, err := os.Create(*outputFilePath); err != nil {
+		fmt.Printf("failed to create output file: %v", err)
 		os.Exit(1)
+	} else {
+		p2m.Config.OutputFile = file
 	}
-
-	// create empty gpio.h file
-	outputGenFile, err := os.Create(*outputFileName)
-	if err != nil {
-		fmt.Printf("Error: unable to generate GPIO config file!\n")
-		os.Exit(1)
-	}
-
-	defer inputRegDumpFile.Close()
-	defer outputGenFile.Close()
-
-	config.OutputGenFile = outputGenFile
-	config.InputRegDumpFile = inputRegDumpFile
+	defer p2m.Config.OutputFile.Close()
 
 	prs := parser.ParserData{}
 	prs.Parse()
@@ -146,15 +136,16 @@ func main() {
 
 /* Pad configuration was generated automatically using intelp2m %s */
 static const struct pad_config gpio_table[] = {`, Version)
-	config.OutputGenFile.WriteString(header + "\n")
+	p2m.Config.OutputFile.WriteString(header + "\n")
 	// Add the pads map
 
 	if err := generator.Run(); err != nil {
 		fmt.Printf("Error: %v", err)
 		os.Exit(1)
 	}
-	config.OutputGenFile.WriteString(`};
+	p2m.Config.OutputFile.WriteString(`};
 
 #endif /* CFG_GPIO_H */
 `)
+	os.Exit(0)
 }
diff --git a/util/intelp2m/parser/parser.go b/util/intelp2m/parser/parser.go
index 54cadce5df..f2756107bf 100644
--- a/util/intelp2m/parser/parser.go
+++ b/util/intelp2m/parser/parser.go
@@ -7,7 +7,7 @@ import (
 	"strconv"
 	"strings"
 
-	"review.coreboot.org/coreboot.git/util/intelp2m/config"
+	"review.coreboot.org/coreboot.git/util/intelp2m/config/p2m"
 	"review.coreboot.org/coreboot.git/util/intelp2m/platforms/adl"
 	"review.coreboot.org/coreboot.git/util/intelp2m/platforms/apl"
 	"review.coreboot.org/coreboot.git/util/intelp2m/platforms/cnl"
@@ -96,28 +96,28 @@ func (parser *ParserData) communityGroupExtract() {
 // PlatformSpecificInterfaceSet - specific interface for the platform selected
 // in the configuration
 func (parser *ParserData) PlatformSpecificInterfaceSet() {
-	var platform = map[uint8]PlatformSpecific{
-		config.SunriseType: snr.PlatformSpecific{},
+	platform := map[p2m.PlatformType]PlatformSpecific{
+		p2m.Sunrise: snr.PlatformSpecific{},
 		// See platforms/lbg/macro.go
-		config.LewisburgType: lbg.PlatformSpecific{
+		p2m.Lewisburg: lbg.PlatformSpecific{
 			InheritanceTemplate: snr.PlatformSpecific{},
 		},
-		config.ApolloType: apl.PlatformSpecific{},
-		config.CannonType: cnl.PlatformSpecific{
+		p2m.Apollo: apl.PlatformSpecific{},
+		p2m.Cannon: cnl.PlatformSpecific{
 			InheritanceTemplate: snr.PlatformSpecific{},
 		},
-		config.TigerType:  tgl.PlatformSpecific{},
-		config.AlderType:  adl.PlatformSpecific{},
-		config.JasperType: jsl.PlatformSpecific{},
-		config.MeteorType: mtl.PlatformSpecific{},
+		p2m.Tiger:  tgl.PlatformSpecific{},
+		p2m.Alder:  adl.PlatformSpecific{},
+		p2m.Jasper: jsl.PlatformSpecific{},
+		p2m.Meteor: mtl.PlatformSpecific{},
 		// See platforms/ebg/macro.go
-		config.EmmitsburgType: ebg.PlatformSpecific{
+		p2m.Emmitsburg: ebg.PlatformSpecific{
 			InheritanceTemplate: cnl.PlatformSpecific{
 				InheritanceTemplate: snr.PlatformSpecific{},
 			},
 		},
 	}
-	parser.platform = platform[config.PlatformGet()]
+	parser.platform = platform[p2m.Config.Platform]
 }
 
 // Register - read specific platform registers (32 bits)
@@ -164,8 +164,7 @@ func (parser *ParserData) padOwnershipExtract() bool {
 //
 //	information from the inteltool log was successfully parsed.
 func (parser *ParserData) padConfigurationExtract() bool {
-	// Only for Sunrise or CannonLake, and only for inteltool.log file template
-	if config.IsPlatformApollo() {
+	if p2m.Config.Platform == p2m.Apollo {
 		return false
 	}
 	return parser.padOwnershipExtract()
@@ -183,7 +182,8 @@ func (parser *ParserData) Parse() {
 	// map of thepad ownership registers for the GPIO controller
 	parser.ownership = make(map[string]uint32)
 
-	scanner := bufio.NewScanner(config.InputRegDumpFile)
+	file := p2m.Config.InputFile
+	scanner := bufio.NewScanner(file)
 	for scanner.Scan() {
 		parser.line = scanner.Text()
 		isIncluded, _ := common.KeywordsCheck(parser.line, "GPIO Community", "GPIO Group")
@@ -234,7 +234,7 @@ func (g Generator) Run() error {
 			g.Linef(2, "\n\t/* %s - %s */\n\t/* DW0: 0x%0.8x, DW1: 0x%0.8x */\n",
 				pad.id, pad.function, pad.dw0, pad.dw1)
 			g.Linef(0, "\t%s", macro)
-			if config.InfoLevelGet() == 1 {
+			if p2m.Config.GenLevel == 1 {
 				g.Linef(1, "\t/* %s */", pad.function)
 			}
 			g.Line(0, "\n")
diff --git a/util/intelp2m/parser/parser_test.go b/util/intelp2m/parser/parser_test.go
index 4f0e4523d1..5e59ade566 100644
--- a/util/intelp2m/parser/parser_test.go
+++ b/util/intelp2m/parser/parser_test.go
@@ -5,7 +5,7 @@ import (
 	"os"
 	"testing"
 
-	"review.coreboot.org/coreboot.git/util/intelp2m/config"
+	"review.coreboot.org/coreboot.git/util/intelp2m/config/p2m"
 	"review.coreboot.org/coreboot.git/util/intelp2m/parser"
 )
 
@@ -16,19 +16,20 @@ type Printer struct {
 }
 
 func (p *Printer) Linef(lvl int, format string, args ...interface{}) {
-	if config.InfoLevelGet() >= lvl {
+	if p2m.Config.GenLevel >= lvl {
 		p.lines = append(p.lines, fmt.Sprintf(format, args...))
 	}
 }
 
 func (p *Printer) Line(lvl int, str string) {
-	if config.InfoLevelGet() >= lvl {
+	if p2m.Config.GenLevel >= lvl {
 		p.lines = append(p.lines, str)
 	}
 }
 
 func TestParser(t *testing.T) {
 	t.Run("PARSER/PARSE-INTELTOOL-FILE", func(t *testing.T) {
+		var err error
 		reference := []string{
 			"\n\t/* ------- GPIO Community 0 ------- */\n",
 			"\n\t/* ------- GPIO Group GPP_A ------- */\n",
@@ -62,18 +63,15 @@ func TestParser(t *testing.T) {
 			"\tPAD_CFG_NF(GPP_I1, NONE, PLTRST, NF1),", "\t/* DDPC_HPD1 */", "\n",
 			"\tPAD_CFG_NF(GPP_I2, NONE, PLTRST, NF1),", "\t/* DDPD_HPD2 */", "\n",
 		}
-
-		input, err := os.Open(testLogFilePath)
-		if err != nil {
+		if p2m.Config.InputFile, err = os.Open(testLogFilePath); err != nil {
 			t.Errorf("Something is wrong with the test file - %s!\n", testLogFilePath)
 			os.Exit(1)
 		}
-		defer input.Close()
+		defer p2m.Config.InputFile.Close()
 
-		config.InputRegDumpFile = input
-		config.FldStyleSet("none")
-		config.NonCheckingFlagSet(true)
-		config.InfoLevelSet(1)
+		p2m.Config.AutoCheck = false
+		p2m.Config.Field = p2m.NoFlds
+		p2m.Config.GenLevel = 1
 
 		prs := parser.ParserData{}
 		prs.Parse()
diff --git a/util/intelp2m/platforms/apl/macro.go b/util/intelp2m/platforms/apl/macro.go
index 31972777d3..e5ac7c2a49 100644
--- a/util/intelp2m/platforms/apl/macro.go
+++ b/util/intelp2m/platforms/apl/macro.go
@@ -4,9 +4,9 @@ import (
 	"fmt"
 	"strconv"
 
-	"review.coreboot.org/coreboot.git/util/intelp2m/platforms/common"
-	"review.coreboot.org/coreboot.git/util/intelp2m/config"
+	"review.coreboot.org/coreboot.git/util/intelp2m/config/p2m"
 	"review.coreboot.org/coreboot.git/util/intelp2m/fields"
+	"review.coreboot.org/coreboot.git/util/intelp2m/platforms/common"
 )
 
 const (
@@ -21,18 +21,18 @@ const (
 )
 
 const (
-	PULL_NONE    = 0x0  // 0 000: none
-	PULL_DN_5K   = 0x2  // 0 010: 5k wpd (Only available on SMBus GPIOs)
-	PULL_DN_20K  = 0x4  // 0 100: 20k wpd
+	PULL_NONE   = 0x0 // 0 000: none
+	PULL_DN_5K  = 0x2 // 0 010: 5k wpd (Only available on SMBus GPIOs)
+	PULL_DN_20K = 0x4 // 0 100: 20k wpd
 	// PULL_NONE = 0x8  // 1 000: none
-	PULL_UP_1K   = 0x9  // 1 001: 1k wpu (Only available on I2C GPIOs)
-	PULL_UP_2K   = 0xb  // 1 011: 2k wpu (Only available on I2C GPIOs)
-	PULL_UP_20K  = 0xc  // 1 100: 20k wpu
-	PULL_UP_667  = 0xd  // 1 101: 1k & 2k wpu (Only available on I2C GPIOs)
-	PULL_NATIVE  = 0xf  // 1 111: (optional) Native controller selected by Pad Mode
+	PULL_UP_1K  = 0x9 // 1 001: 1k wpu (Only available on I2C GPIOs)
+	PULL_UP_2K  = 0xb // 1 011: 2k wpu (Only available on I2C GPIOs)
+	PULL_UP_20K = 0xc // 1 100: 20k wpu
+	PULL_UP_667 = 0xd // 1 101: 1k & 2k wpu (Only available on I2C GPIOs)
+	PULL_NATIVE = 0xf // 1 111: (optional) Native controller selected by Pad Mode
 )
 
-type PlatformSpecific struct {}
+type PlatformSpecific struct{}
 
 // RemmapRstSrc - remmap Pad Reset Source Config
 // remmap is not required because it is the same as common.
@@ -52,7 +52,6 @@ func (PlatformSpecific) Pull() {
 		PULL_UP_20K: "UP_20K",
 		PULL_UP_667: "UP_667",
 		PULL_NATIVE: "NATIVE",
-
 	}
 	terminationFieldValue := dw1.GetTermination()
 	str, valid := pull[terminationFieldValue]
@@ -107,7 +106,7 @@ func sciRoute() bool {
 		// PAD_CFG_GPI_SCI_IOS(GPIO_141, NONE, DEEP, EDGE_SINGLE, INVERT, IGNORE, DISPUPD),
 		macro.Add("_SCI_IOS")
 		macro.Add("(").Id().Pull().Rstsrc().Trig().Invert().IOSstate().IOTerm()
-	} else if dw0.GetRXLevelEdgeConfiguration() & 0x1 != 0 {
+	} else if dw0.GetRXLevelEdgeConfiguration()&0x1 != 0 {
 		// e.g. PAD_CFG_GPI_ACPI_SCI(GPP_G2, NONE, DEEP, YES),
 		macro.Add("_ACPI_SCI").Add("(").Id().Pull().Rstsrc().Invert()
 	} else {
@@ -130,7 +129,7 @@ func smiRoute() bool {
 		// PAD_CFG_GPI_SMI_IOS(GPIO_41, UP_20K, DEEP, EDGE_SINGLE, NONE, IGNORE, SAME),
 		macro.Add("_SMI_IOS")
 		macro.Add("(").Id().Pull().Rstsrc().Trig().Invert().IOSstate().IOTerm()
-	} else if dw0.GetRXLevelEdgeConfiguration() & 0x1 != 0 {
+	} else if dw0.GetRXLevelEdgeConfiguration()&0x1 != 0 {
 		// e.g. PAD_CFG_GPI_ACPI_SMI(GPP_I3, NONE, DEEP, YES),
 		macro.Add("_ACPI_SMI").Add("(").Id().Pull().Rstsrc().Invert()
 	} else {
@@ -143,10 +142,11 @@ func smiRoute() bool {
 
 // Generate macro for GPI port
 func (PlatformSpecific) GpiMacroAdd() {
-	macro := common.GetMacro()
 	var ids []string
+
+	macro := common.GetMacro()
 	macro.Set("PAD_CFG_GPI")
-	for routeid, isRoute := range map[string]func() (bool) {
+	for routeid, isRoute := range map[string]func() bool{
 		"IOAPIC": ioApicRoute,
 		"SCI":    sciRoute,
 		"SMI":    smiRoute,
@@ -157,7 +157,7 @@ func (PlatformSpecific) GpiMacroAdd() {
 		}
 	}
 
-	switch argc := len(ids); argc {
+	switch config, argc := p2m.Config, len(ids); argc {
 	case 0:
 		dw1 := macro.Register(PAD_CFG_DW1)
 		isIOStandbyStateUsed := dw1.GetIOStandbyState() != 0
@@ -176,14 +176,14 @@ func (PlatformSpecific) GpiMacroAdd() {
 		}
 	case 1:
 		// GPI with IRQ route
-		if config.AreFieldsIgnored() {
+		if config.IgnoredFields {
 			macro.SetPadOwnership(common.PAD_OWN_ACPI)
 		}
 	case 2:
 		// PAD_CFG_GPI_DUAL_ROUTE(pad, pull, rst, trig, inv, route1, route2)
 		macro.Set("PAD_CFG_GPI_DUAL_ROUTE(").Id().Pull().Rstsrc().Trig().Invert()
 		macro.Add(", " + ids[0] + ", " + ids[1] + "),")
-		if config.AreFieldsIgnored() {
+		if config.IgnoredFields {
 			macro.SetPadOwnership(common.PAD_OWN_ACPI)
 		}
 	default:
@@ -193,12 +193,11 @@ func (PlatformSpecific) GpiMacroAdd() {
 	}
 }
 
-
 // Adds PAD_CFG_GPO macro with arguments
 func (PlatformSpecific) GpoMacroAdd() {
 	macro := common.GetMacro()
-	dw0 :=  macro.Register(PAD_CFG_DW0)
-	dw1 :=  macro.Register(PAD_CFG_DW1)
+	dw0 := macro.Register(PAD_CFG_DW0)
+	dw1 := macro.Register(PAD_CFG_DW1)
 	term := dw1.GetTermination()
 
 	macro.Set("PAD_CFG")
@@ -291,7 +290,8 @@ func (PlatformSpecific) NoConnMacroAdd() {
 // dw0 : DW0 config register value
 // dw1 : DW1 config register value
 // return: string of macro
-//         error
+//
+//	error
 func (PlatformSpecific) GenMacro(id string, dw0 uint32, dw1 uint32, ownership uint8) string {
 	macro := common.GetInstanceMacro(PlatformSpecific{}, fields.InterfaceGet())
 	// use platform-specific interface in Macro struct
diff --git a/util/intelp2m/platforms/cnl/macro.go b/util/intelp2m/platforms/cnl/macro.go
index 6aa6140ef9..19fee99cb9 100644
--- a/util/intelp2m/platforms/cnl/macro.go
+++ b/util/intelp2m/platforms/cnl/macro.go
@@ -4,7 +4,7 @@ import (
 	"fmt"
 	"strings"
 
-	"review.coreboot.org/coreboot.git/util/intelp2m/config"
+	"review.coreboot.org/coreboot.git/util/intelp2m/config/p2m"
 	"review.coreboot.org/coreboot.git/util/intelp2m/fields"
 	"review.coreboot.org/coreboot.git/util/intelp2m/platforms/common"
 	"review.coreboot.org/coreboot.git/util/intelp2m/platforms/snr"
@@ -159,7 +159,7 @@ func (PlatformSpecific) GpiMacroAdd() {
 		macro.Add("_TRIG_OWN").Add("(").Id().Pull().Rstsrc().Trig().Own().Add("),")
 	case 1:
 		// GPI with IRQ route
-		if config.AreFieldsIgnored() {
+		if p2m.Config.IgnoredFields {
 			// Set Host Software Ownership to ACPI mode
 			macro.SetPadOwnership(common.PAD_OWN_ACPI)
 		}
@@ -168,7 +168,7 @@ func (PlatformSpecific) GpiMacroAdd() {
 		// PAD_CFG_GPI_DUAL_ROUTE(pad, pull, rst, trig, inv, route1, route2)
 		macro.Set("PAD_CFG_GPI_DUAL_ROUTE(").Id().Pull().Rstsrc().Trig().Invert()
 		macro.Add(", " + ids[0] + ", " + ids[1] + "),")
-		if config.AreFieldsIgnored() {
+		if p2m.Config.IgnoredFields {
 			// Set Host Software Ownership to ACPI mode
 			macro.SetPadOwnership(common.PAD_OWN_ACPI)
 		}
@@ -198,7 +198,8 @@ func (platform PlatformSpecific) NoConnMacroAdd() {
 // dw0 : DW0 config register value
 // dw1 : DW1 config register value
 // return: string of macro
-//         error
+//
+//	error
 func (PlatformSpecific) GenMacro(id string, dw0 uint32, dw1 uint32, ownership uint8) string {
 	macro := common.GetInstanceMacro(PlatformSpecific{InheritanceMacro: snr.PlatformSpecific{}},
 		fields.InterfaceGet())
diff --git a/util/intelp2m/platforms/common/macro.go b/util/intelp2m/platforms/common/macro.go
index ddb612a9a9..853fcf2489 100644
--- a/util/intelp2m/platforms/common/macro.go
+++ b/util/intelp2m/platforms/common/macro.go
@@ -4,7 +4,7 @@ import (
 	"strconv"
 	"sync"
 
-	"review.coreboot.org/coreboot.git/util/intelp2m/config"
+	"review.coreboot.org/coreboot.git/util/intelp2m/config/p2m"
 )
 
 type Fields interface {
@@ -33,9 +33,9 @@ const (
 )
 
 const (
-	IOSTERM_SAME	= 0x0
-	IOSTERM_DISPUPD	= 0x1
-	IOSTERM_ENPD	= 0x2
+	IOSTERM_SAME    = 0x0
+	IOSTERM_DISPUPD = 0x1
+	IOSTERM_ENPD    = 0x2
 	IOSTERM_ENPU    = 0x3
 )
 
@@ -77,13 +77,13 @@ type Macro struct {
 	Fields
 }
 
-var	instanceMacro *Macro
-var	once           sync.Once
+var instanceMacro *Macro
+var once sync.Once
 
 // GetInstance returns singleton
 func GetInstanceMacro(p PlatformSpecific, f Fields) *Macro {
 	once.Do(func() {
-		instanceMacro = &Macro{ Platform : p, Fields : f }
+		instanceMacro = &Macro{Platform: p, Fields: f}
 	})
 	return instanceMacro
 }
@@ -159,7 +159,7 @@ func (macro *Macro) Separator() *Macro {
 // return: Macro
 func (macro *Macro) Rstsrc() *Macro {
 	dw0 := macro.Register(PAD_CFG_DW0)
-	var resetsrc = map[uint8]string {
+	var resetsrc = map[uint8]string{
 		0: "PWROK",
 		1: "DEEP",
 		2: "PLTRST",
@@ -199,7 +199,7 @@ func (macro *Macro) Trig() *Macro {
 // return: Macro
 func (macro *Macro) Invert() *Macro {
 	macro.Separator()
-	if macro.Register(PAD_CFG_DW0).GetRxInvert() !=0 {
+	if macro.Register(PAD_CFG_DW0).GetRxInvert() != 0 {
 		return macro.Add("INVERT")
 	}
 	return macro.Add("NONE")
@@ -227,8 +227,8 @@ func (macro *Macro) Own() *Macro {
 	return macro.Separator().Add("ACPI")
 }
 
-//Adds pad native function (PMODE) as a new argument
-//return: Macro
+// Adds pad native function (PMODE) as a new argument
+// return: Macro
 func (macro *Macro) Padfn() *Macro {
 	dw0 := macro.Register(PAD_CFG_DW0)
 	nfnum := int(dw0.GetPadMode())
@@ -287,22 +287,21 @@ func (macro *Macro) check() *Macro {
 
 // or - Set " | " if its needed
 func (macro *Macro) Or() *Macro {
-
-		if str := macro.Get(); str[len(str) - 1] == ')' {
-			macro.Add(" | ")
-		}
-		return macro
+	if str := macro.Get(); str[len(str)-1] == ')' {
+		macro.Add(" | ")
+	}
+	return macro
 }
 
 // DecodeIgnored - Add info about ignored field mask
 // reg : PAD_CFG_DW0 or PAD_CFG_DW1 register
 func (macro *Macro) DecodeIgnored(reg uint8) *Macro {
-	var decode = map[uint8]func() {
+	var decode = map[uint8]func(){
 		PAD_CFG_DW0: macro.Fields.DecodeDW0,
 		PAD_CFG_DW1: macro.Fields.DecodeDW1,
 	}
 	decodefn, valid := decode[reg]
-	if !valid || config.IsFspStyleMacro() {
+	if !valid || p2m.Config.Field == p2m.FspFlds {
 		return macro
 	}
 	dw := macro.Register(reg)
@@ -328,21 +327,21 @@ func (macro *Macro) GenerateFields() *Macro {
 	dw0Ignored := dw0.IgnoredFieldsGet()
 	dw1Ignored := dw1.IgnoredFieldsGet()
 
-	if config.InfoLevelGet() != 4 {
+	if p2m.Config.GenLevel != 4 {
 		macro.Clear()
 	}
-	if config.InfoLevelGet() >= 3 {
+	if p2m.Config.GenLevel >= 3 {
 		// Add string of reference macro as a comment
 		reference := macro.Get()
 		macro.Clear()
 		/* DW0 : PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1 - IGNORED */
 		macro.DecodeIgnored(PAD_CFG_DW0).DecodeIgnored(PAD_CFG_DW1)
-		if config.InfoLevelGet() >= 4 {
+		if p2m.Config.GenLevel >= 4 {
 			/* PAD_CFG_NF(GPP_B23, 20K_PD, PLTRST, NF2), */
 			macro.Add("/* ").Add(reference).Add(" */\n\t")
 		}
 	}
-	if config.AreFieldsIgnored() {
+	if p2m.Config.IgnoredFields {
 		// Consider bit fields that should be ignored when regenerating
 		// advansed macros
 		var tempVal uint32 = dw0.ValueGet() & ^dw0Ignored
@@ -404,17 +403,17 @@ func (macro *Macro) Generate() string {
 		macro.Platform.NativeFunctionMacroAdd()
 	}
 
-	if config.IsFieldsMacroUsed() {
+	if p2m.Config.Field != p2m.NoFlds {
 		// Clear control mask to generate advanced macro only
 		return macro.GenerateFields().Get()
 	}
 
-	if config.IsNonCheckingFlagUsed() {
+	if !p2m.Config.AutoCheck {
 		body := macro.Get()
-		if config.InfoLevelGet() >= 3 {
+		if p2m.Config.GenLevel >= 3 {
 			macro.Clear().DecodeIgnored(PAD_CFG_DW0).DecodeIgnored(PAD_CFG_DW1)
 			comment := macro.Get()
-			if config.InfoLevelGet() >= 4 {
+			if p2m.Config.GenLevel >= 4 {
 				macro.Clear().Add("/* ")
 				macro.Fields.GenerateString()
 				macro.Add(" */\n\t")
diff --git a/util/intelp2m/platforms/common/register.go b/util/intelp2m/platforms/common/register.go
index 2aa51b92e9..2596b8d2cb 100644
--- a/util/intelp2m/platforms/common/register.go
+++ b/util/intelp2m/platforms/common/register.go
@@ -85,7 +85,7 @@ func (reg *Register) ReadOnlyFieldsGet() uint32 {
 // Returns true if the macro is generated correctly
 func (reg *Register) MaskCheck() bool {
 	mask := ^(reg.mask | reg.roFileds)
-	return reg.value&mask == 0
+	return (reg.value & mask) == 0
 }
 
 // getResetConfig - get Reset Configuration from PADRSTCFG field in PAD_CFG_DW0_GPx register
@@ -97,14 +97,17 @@ func (reg *Register) getFieldVal(mask uint32, shift uint8) uint8 {
 // CntrMaskFieldsClear - clear filed in control mask
 // fieldMask - mask of the field to be cleared
 func (reg *Register) CntrMaskFieldsClear(fieldMask uint32) {
-	reg.mask &= ^fieldMask;
+	reg.mask &= ^fieldMask
 }
 
 // IgnoredFieldsGet - return mask of unchecked (ignored) fields.
-//                    These bit fields were not read when the macro was
-//                    generated.
+//
+//	These bit fields were not read when the macro was
+//	generated.
+//
 // return
-//   mask of ignored bit field
+//
+//	mask of ignored bit field
 func (reg *Register) IgnoredFieldsGet() uint32 {
 	mask := reg.mask | reg.roFileds
 	return reg.value & ^mask
diff --git a/util/intelp2m/platforms/snr/macro.go b/util/intelp2m/platforms/snr/macro.go
index d96e83e2e2..aa3be5d9bb 100644
--- a/util/intelp2m/platforms/snr/macro.go
+++ b/util/intelp2m/platforms/snr/macro.go
@@ -4,7 +4,7 @@ import (
 	"fmt"
 	"strings"
 
-	"review.coreboot.org/coreboot.git/util/intelp2m/config"
+	"review.coreboot.org/coreboot.git/util/intelp2m/config/p2m"
 	"review.coreboot.org/coreboot.git/util/intelp2m/fields"
 	"review.coreboot.org/coreboot.git/util/intelp2m/platforms/common"
 )
@@ -159,7 +159,7 @@ func (PlatformSpecific) GpiMacroAdd() {
 		macro.Add("_TRIG_OWN").Add("(").Id().Pull().Rstsrc().Trig().Own().Add("),")
 	case 1:
 		// GPI with IRQ route
-		if config.AreFieldsIgnored() {
+		if p2m.Config.IgnoredFields {
 			// Set Host Software Ownership to ACPI mode
 			macro.SetPadOwnership(common.PAD_OWN_ACPI)
 		}
@@ -168,7 +168,7 @@ func (PlatformSpecific) GpiMacroAdd() {
 		// PAD_CFG_GPI_DUAL_ROUTE(pad, pull, rst, trig, inv, route1, route2)
 		macro.Set("PAD_CFG_GPI_DUAL_ROUTE(").Id().Pull().Rstsrc().Trig().Invert()
 		macro.Add(", " + ids[0] + ", " + ids[1] + "),")
-		if config.AreFieldsIgnored() {
+		if p2m.Config.IgnoredFields {
 			// Set Host Software Ownership to ACPI mode
 			macro.SetPadOwnership(common.PAD_OWN_ACPI)
 		}
@@ -246,7 +246,8 @@ func (PlatformSpecific) NoConnMacroAdd() {
 // dw0 : DW0 config register value
 // dw1 : DW1 config register value
 // return: string of macro
-//         error
+//
+//	error
 func (PlatformSpecific) GenMacro(id string, dw0 uint32, dw1 uint32, ownership uint8) string {
 	macro := common.GetInstanceMacro(PlatformSpecific{}, fields.InterfaceGet())
 	macro.Clear()
diff --git a/util/intelp2m/platforms/test/suite.go b/util/intelp2m/platforms/test/suite.go
index 8ec4886357..0b5074a0d9 100644
--- a/util/intelp2m/platforms/test/suite.go
+++ b/util/intelp2m/platforms/test/suite.go
@@ -4,7 +4,7 @@ import (
 	"fmt"
 	"testing"
 
-	"review.coreboot.org/coreboot.git/util/intelp2m/config"
+	"review.coreboot.org/coreboot.git/util/intelp2m/config/p2m"
 )
 
 type (
@@ -29,14 +29,18 @@ type (
 )
 
 func (p Pad) toShortMacro(platform PlatformSpecificIf) string {
-	config.FldStyleSet("none")
-	config.NonCheckingFlagSet(true)
+	if err := p2m.SetFieldType("none"); err != nil {
+		panic(err)
+	}
+	p2m.Config.AutoCheck = false
 	return platform.GenMacro(p.ID, p.DW0, p.DW1, p.Ownership)
 }
 
 func (p Pad) toLongMacro(platform PlatformSpecificIf) string {
-	config.FldStyleSet("cb")
-	config.NonCheckingFlagSet(false)
+	if err := p2m.SetFieldType("cb"); err != nil {
+		panic(err)
+	}
+	p2m.Config.AutoCheck = true
 	return platform.GenMacro(p.ID, p.DW0, p.DW1, p.Ownership)
 }
 

From a581660031a0e18931fedccc0dba2da7536e759a Mon Sep 17 00:00:00 2001
From: Maxim Polyakov <max.senia.poliak@gmail.com>
Date: Sun, 27 Nov 2022 00:46:28 +0300
Subject: [PATCH 0250/3886] util/intelp2m/register: Rework package code

Split all methods between DW0 and DW1 to avoid the mistake of using any
DW0 method with DW1 receiver and make the code safer. Also make some
code style fixes.

TEST: make test = PASS

Change-Id: Id64e2a5e29f1d561597004ac83d32e3c80c16ebd
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70309
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 util/intelp2m/fields/cb/cb.go                 |   4 +-
 util/intelp2m/fields/fsp/fsp.go               |  94 ++++---
 util/intelp2m/fields/raw/raw.go               |  11 +-
 util/intelp2m/fields/test/suite.go            |   8 +-
 util/intelp2m/parser/template.go              |   4 +-
 util/intelp2m/parser/template_test.go         |   4 +-
 util/intelp2m/platforms/adl/adl_test.go       |   8 +-
 util/intelp2m/platforms/adl/macro.go          |  46 +--
 util/intelp2m/platforms/apl/macro.go          |  94 ++++---
 util/intelp2m/platforms/cnl/cnl_test.go       |   8 +-
 util/intelp2m/platforms/cnl/macro.go          |  74 ++---
 util/intelp2m/platforms/common/macro.go       | 250 ++++++++---------
 util/intelp2m/platforms/common/register.go    | 265 ------------------
 .../platforms/common/register/bits/bits.go    |  92 ++++++
 .../intelp2m/platforms/common/register/dw0.go |  97 +++++++
 .../intelp2m/platforms/common/register/dw1.go |  51 ++++
 .../platforms/common/register/register.go     |  45 +++
 util/intelp2m/platforms/ebg/ebg_test.go       |   8 +-
 util/intelp2m/platforms/ebg/macro.go          |  44 +--
 util/intelp2m/platforms/jsl/jsl_test.go       |   8 +-
 util/intelp2m/platforms/jsl/macro.go          |  45 +--
 util/intelp2m/platforms/lbg/macro.go          |  55 ++--
 util/intelp2m/platforms/mtl/macro.go          |  46 +--
 util/intelp2m/platforms/mtl/mtl_test.go       |   8 +-
 util/intelp2m/platforms/snr/macro.go          |  90 +++---
 util/intelp2m/platforms/tgl/macro.go          |  44 +--
 util/intelp2m/platforms/tgl/tgl_test.go       |   8 +-
 27 files changed, 779 insertions(+), 732 deletions(-)
 delete mode 100644 util/intelp2m/platforms/common/register.go
 create mode 100644 util/intelp2m/platforms/common/register/bits/bits.go
 create mode 100644 util/intelp2m/platforms/common/register/dw0.go
 create mode 100644 util/intelp2m/platforms/common/register/dw1.go
 create mode 100644 util/intelp2m/platforms/common/register/register.go

diff --git a/util/intelp2m/fields/cb/cb.go b/util/intelp2m/fields/cb/cb.go
index efc80184f6..f6a1411356 100644
--- a/util/intelp2m/fields/cb/cb.go
+++ b/util/intelp2m/fields/cb/cb.go
@@ -50,7 +50,7 @@ func generate(fields ...*field) {
 // DecodeDW0 - decode value of DW0 register
 func (FieldMacros) DecodeDW0() {
 	macro := common.GetMacro()
-	dw0 := macro.Register(common.PAD_CFG_DW0)
+	dw0 := macro.GetRegisterDW0()
 	generate(
 		&field{
 			prefix: "PAD_FUNC",
@@ -133,7 +133,7 @@ func (FieldMacros) DecodeDW0() {
 // DecodeDW1 - decode value of DW1 register
 func (FieldMacros) DecodeDW1() {
 	macro := common.GetMacro()
-	dw1 := macro.Register(common.PAD_CFG_DW1)
+	dw1 := macro.GetRegisterDW1()
 	generate(
 		&field{
 			name:   "PAD_CFG1_TOL_1V8",
diff --git a/util/intelp2m/fields/fsp/fsp.go b/util/intelp2m/fields/fsp/fsp.go
index b6224cd03c..db6b4ad294 100644
--- a/util/intelp2m/fields/fsp/fsp.go
+++ b/util/intelp2m/fields/fsp/fsp.go
@@ -2,16 +2,16 @@ package fsp
 
 import "review.coreboot.org/coreboot.git/util/intelp2m/platforms/common"
 
-type FieldMacros struct {}
+type FieldMacros struct{}
 
 // field - data structure for creating a new bitfield macro object
 // configmap : map to select the current configuration
 // value     : the key value in the configmap
 // override  : overrides the function to generate the current bitfield macro
 type field struct {
-	configmap map[uint8]string
-	value     uint8
-	override  func(configuration map[uint8]string, value uint8)
+	configmap map[uint32]string
+	value     uint32
+	override  func(configuration map[uint32]string, value uint32)
 }
 
 // generate - wrapper for generating bitfield macros string
@@ -37,16 +37,18 @@ func generate(fields ...*field) {
 // DecodeDW0 - decode value of DW0 register
 func (FieldMacros) DecodeDW0() {
 	macro := common.GetMacro()
-	dw0 := macro.Register(common.PAD_CFG_DW0)
+	dw0 := macro.GetRegisterDW0()
 
-	ownershipStatus := func() uint8 {
-		if macro.IsOwnershipDriver() { return 1 }
+	ownershipStatus := func() uint32 {
+		if macro.IsOwnershipDriver() {
+			return 1
+		}
 		return 0
 	}
 
 	generate(
-		&field {
-			configmap : map[uint8]string{
+		&field{
+			configmap: map[uint32]string{
 				0: "GpioPadModeGpio",
 				1: "GpioPadModeNative1",
 				2: "GpioPadModeNative2",
@@ -54,79 +56,79 @@ func (FieldMacros) DecodeDW0() {
 				4: "GpioPadModeNative4",
 				5: "GpioPadModeNative5",
 			},
-			value : dw0.GetPadMode(),
+			value: dw0.GetPadMode(),
 		},
 
-		&field {
-			configmap : map[uint8]string {
+		&field{
+			configmap: map[uint32]string{
 				0: "GpioHostOwnAcpi",
 				1: "GpioHostOwnGpio",
 			},
-			value : ownershipStatus(),
+			value: ownershipStatus(),
 		},
 
-		&field {
-			configmap : map[uint8]string {
-				0:          "GpioDirInOut",
-				1:          "GpioDirIn",
-				2:          "GpioDirOut",
-				3:          "GpioDirNone",
-				1 << 4 | 0: "GpioDirInInvOut",
-				1 << 4 | 1: "GpioDirInInv",
+		&field{
+			configmap: map[uint32]string{
+				0:            "GpioDirInOut",
+				1:            "GpioDirIn",
+				2:            "GpioDirOut",
+				3:            "GpioDirNone",
+				(1 << 4):     "GpioDirInInvOut",
+				(1 << 4) | 1: "GpioDirInInv",
 			},
-			value : dw0.GetRxInvert() << 4 | dw0.GetGPIORxTxDisableStatus(),
+			value: dw0.GetRxInvert()<<4 | dw0.GetGPIORxTxDisableStatus(),
 		},
 
-		&field {
-			configmap : map[uint8]string {
+		&field{
+			configmap: map[uint32]string{
 				0: "GpioOutLow",
 				1: "GpioOutHigh",
 			},
-			value : dw0.GetGPIOTXState(),
+			value: dw0.GetGPIOTXState(),
 		},
 
-		&field {
-			configmap : map[uint8]string {
+		&field{
+			configmap: map[uint32]string{
 				1 << 0: "GpioIntNmi",
 				1 << 1: "GpioIntSmi",
 				1 << 2: "GpioIntSci",
 				1 << 3: "GpioIntApic",
 			},
-			override : func(configmap map[uint8]string, value uint8) {
-				mask := dw0.GetGPIOInputRouteIOxAPIC() << 3 |
-							dw0.GetGPIOInputRouteSCI() << 2 |
-							dw0.GetGPIOInputRouteSMI() << 1 |
-							dw0.GetGPIOInputRouteNMI()
+			override: func(configmap map[uint32]string, value uint32) {
+				mask := dw0.GetGPIOInputRouteIOxAPIC()<<3 |
+					dw0.GetGPIOInputRouteSCI()<<2 |
+					dw0.GetGPIOInputRouteSMI()<<1 |
+					dw0.GetGPIOInputRouteNMI()
 				if mask == 0 {
 					macro.Add("GpioIntDis | ")
 					return
 				}
 				for bit, fieldmacro := range configmap {
-					if mask & bit != 0 {
+					if mask&bit != 0 {
 						macro.Add(fieldmacro).Add(" | ")
 					}
 				}
 			},
 		},
 
-		&field {
-			configmap : map[uint8]string {
+		&field{
+			configmap: map[uint32]string{
 				0: "GpioIntLevel",
 				1: "GpioIntEdge",
 				2: "GpioIntLvlEdgDis",
 				3: "GpioIntBothEdge",
 			},
-			value : dw0.GetRXLevelEdgeConfiguration(),
+			value: dw0.GetRXLevelEdgeConfiguration(),
 		},
 
-		&field {
-			configmap : map[uint8]string {
-				0: "GpioResetPwrGood",	// TODO: Has multiple values (to GPP and GPD)
+		&field{
+			configmap: map[uint32]string{
+				0: "GpioResetPwrGood", // TODO: Has multiple values (to GPP and GPD)
 				1: "GpioHostDeepReset",
 				2: "GpioPlatformReset",
 				3: "GpioResumeReset",
 			},
-			value : dw0.GetResetConfig(),
+			value: dw0.GetResetConfig(),
 		},
 	)
 }
@@ -134,18 +136,18 @@ func (FieldMacros) DecodeDW0() {
 // DecodeDW1 - decode value of DW1 register
 func (FieldMacros) DecodeDW1() {
 	macro := common.GetMacro()
-	dw1 := macro.Register(common.PAD_CFG_DW1)
+	dw1 := macro.GetRegisterDW1()
 	generate(
-		&field {
-			override : func(configmap map[uint8]string, value uint8) {
+		&field{
+			override: func(configmap map[uint32]string, value uint32) {
 				if dw1.GetPadTol() != 0 {
 					macro.Add("GpioTolerance1v8 | ")
 				}
 			},
 		},
 
-		&field {
-			configmap : map[uint8]string {
+		&field{
+			configmap: map[uint32]string{
 				0x0: "GpioTermNone",
 				0x2: "GpioTermWpd5K",
 				0x4: "GpioTermWpd20K",
@@ -156,7 +158,7 @@ func (FieldMacros) DecodeDW1() {
 				0xd: "GpioTermWpu1K2K",
 				0xf: "GpioTermNative",
 			},
-			value : dw1.GetTermination(),
+			value: dw1.GetTermination(),
 		},
 	)
 }
diff --git a/util/intelp2m/fields/raw/raw.go b/util/intelp2m/fields/raw/raw.go
index fbac5b53d0..4efccd5c5e 100644
--- a/util/intelp2m/fields/raw/raw.go
+++ b/util/intelp2m/fields/raw/raw.go
@@ -1,22 +1,21 @@
 package raw
 
 import (
-	"fmt"
 	"review.coreboot.org/coreboot.git/util/intelp2m/platforms/common"
 )
 
-type FieldMacros struct {}
+type FieldMacros struct{}
 
 func (FieldMacros) DecodeDW0() {
 	macro := common.GetMacro()
-	// Do not decode, print as is.
-	macro.Add(fmt.Sprintf("0x%0.8x", macro.Register(common.PAD_CFG_DW0).ValueGet()))
+	dw0 := macro.GetRegisterDW0()
+	macro.Add(dw0.String())
 }
 
 func (FieldMacros) DecodeDW1() {
 	macro := common.GetMacro()
-	// Do not decode, print as is.
-	macro.Add(fmt.Sprintf("0x%0.8x", macro.Register(common.PAD_CFG_DW1).ValueGet()))
+	dw1 := macro.GetRegisterDW1()
+	macro.Add(dw1.String())
 }
 
 // GenerateString - generates the entire string of bitfield macros.
diff --git a/util/intelp2m/fields/test/suite.go b/util/intelp2m/fields/test/suite.go
index a61062e130..3041de2136 100644
--- a/util/intelp2m/fields/test/suite.go
+++ b/util/intelp2m/fields/test/suite.go
@@ -29,13 +29,13 @@ func (suite Suite) Run(t *testing.T, label string, decoderIf common.Fields) {
 	t.Run(label, func(t *testing.T) {
 		platform := snr.PlatformSpecific{}
 		macro := common.GetInstanceMacro(platform, decoderIf)
-		dw0 := macro.Register(common.PAD_CFG_DW0)
-		dw1 := macro.Register(common.PAD_CFG_DW1)
+		dw0 := macro.GetRegisterDW0()
+		dw1 := macro.GetRegisterDW1()
 		for _, tc := range suite {
 			macro.Clear()
 			macro.PadIdSet("").SetPadOwnership(tc.Ownership)
-			dw0.ValueSet(tc.DW0)
-			dw1.ValueSet(tc.DW1)
+			dw0.Value = tc.DW0
+			dw1.Value = tc.DW1
 			macro.Fields.GenerateString()
 			if err := tc.Check(macro.Get()); err != nil {
 				t.Errorf("Test failed: %v", err)
diff --git a/util/intelp2m/parser/template.go b/util/intelp2m/parser/template.go
index e7efa734e7..49b938fd56 100644
--- a/util/intelp2m/parser/template.go
+++ b/util/intelp2m/parser/template.go
@@ -6,7 +6,7 @@ import (
 	"unicode"
 )
 
-const INTSEL_MASK uint32 = 0xffffff00
+const IntSelMask uint32 = 0xffffff00
 
 type template func(string, *string, *string, *uint32, *uint32) int
 
@@ -57,7 +57,7 @@ func UseTemplate(line string, function *string, id *string, dw0 *uint32, dw1 *ui
 			*function += "/" + fields[i]
 		}
 		// clear RO Interrupt Select (INTSEL)
-		*dw1 &= INTSEL_MASK
+		*dw1 &= IntSelMask
 	}
 	return 0
 }
diff --git a/util/intelp2m/parser/template_test.go b/util/intelp2m/parser/template_test.go
index 95f8ebf546..9abdd72f83 100644
--- a/util/intelp2m/parser/template_test.go
+++ b/util/intelp2m/parser/template_test.go
@@ -30,9 +30,9 @@ func TestTemp(t *testing.T) {
 		} else if dw0 != ref_dw0 {
 			t.Errorf("dw0 from '%s':\nExpects:  '0x%08x'\nActually: '0x%08x'\n\n",
 				line, ref_dw0, dw0)
-		} else if dw1 != (ref_dw1 & parser.INTSEL_MASK) {
+		} else if dw1 != (ref_dw1 & parser.IntSelMask) {
 			t.Errorf("dw1 from '%s':\nExpects:  '0x%08x'\nActually: '0x%08x'\n\n",
-				line, (ref_dw1 & parser.INTSEL_MASK), dw1)
+				line, (ref_dw1 & parser.IntSelMask), dw1)
 		}
 	})
 }
diff --git a/util/intelp2m/platforms/adl/adl_test.go b/util/intelp2m/platforms/adl/adl_test.go
index 36bd645cc5..1f2400a710 100644
--- a/util/intelp2m/platforms/adl/adl_test.go
+++ b/util/intelp2m/platforms/adl/adl_test.go
@@ -51,7 +51,7 @@ func TestGenMacro(t *testing.T) {
 			Pad: test.Pad{ID: "GPP_E5", DW0: 0xEEEEEEEE, DW1: 0xEEEEEEEE, Ownership: 1},
 			Macro: test.Macro{
 				Short: "PAD_CFG_NF_1V8(GPP_E5, UP_2K, PWROK, NF3),",
-				Long:  "_PAD_CFG_STRUCT(GPP_E5, PAD_FUNC(NF3) | PAD_TRIG(EDGE_BOTH) | PAD_IRQ_ROUTE(SCI) | PAD_IRQ_ROUTE(SMI) | PAD_IRQ_ROUTE(NMI) | PAD_RX_POL(INVERT) | PAD_BUF(RX_DISABLE) | (1 << 29) | (1 << 1), PAD_CFG1_TOL_1V8PAD_PULL(UP_2K) | PAD_IOSSTATE(IGNORE) | PAD_IOSTERM(ENPD) | PAD_CFG_OWN_GPIO(DRIVER)),",
+				Long:  "_PAD_CFG_STRUCT(GPP_E5, PAD_FUNC(NF3) | PAD_TRIG(EDGE_BOTH) | PAD_IRQ_ROUTE(SCI) | PAD_IRQ_ROUTE(SMI) | PAD_IRQ_ROUTE(NMI) | PAD_RX_POL(INVERT) | PAD_BUF(RX_DISABLE) | (1 << 29) | (1 << 1), PAD_CFG1_TOL_1V8PAD_PULL(UP_2K) | PAD_IOSSTATE(ERROR) | PAD_IOSTERM(ENPD) | PAD_CFG_OWN_GPIO(DRIVER)),",
 			},
 		},
 		{
@@ -65,14 +65,14 @@ func TestGenMacro(t *testing.T) {
 			Pad: test.Pad{ID: "GPP_G7", DW0: 0xBBBBBBBB, DW1: 0xBBBBBBBB, Ownership: 1},
 			Macro: test.Macro{
 				Short: "PAD_CFG_NF_1V8(GPP_G7, INVALID, PLTRST, NF6),",
-				Long:  "_PAD_CFG_STRUCT(GPP_G7, PAD_FUNC(NF6) | PAD_RESET(PLTRST) | PAD_TRIG(EDGE_SINGLE) | PAD_IRQ_ROUTE(IOAPIC) | PAD_IRQ_ROUTE(SCI) | PAD_IRQ_ROUTE(NMI) | PAD_RX_POL(INVERT) | PAD_BUF(TX_RX_DISABLE) | (1 << 29) | (1 << 28) | (1 << 1) | 1, PAD_CFG1_TOL_1V8PAD_PULL(INVALID) | PAD_IOSSTATE(IGNORE) | PAD_IOSTERM(ENPU) | PAD_CFG_OWN_GPIO(DRIVER)),",
+				Long:  "_PAD_CFG_STRUCT(GPP_G7, PAD_FUNC(NF6) | PAD_RESET(PLTRST) | PAD_TRIG(EDGE_SINGLE) | PAD_IRQ_ROUTE(IOAPIC) | PAD_IRQ_ROUTE(SCI) | PAD_IRQ_ROUTE(NMI) | PAD_RX_POL(INVERT) | PAD_BUF(TX_RX_DISABLE) | (1 << 29) | (1 << 28) | (1 << 1) | 1, PAD_CFG1_TOL_1V8PAD_PULL(INVALID) | PAD_IOSSTATE(ERROR) | PAD_IOSTERM(ENPU) | PAD_CFG_OWN_GPIO(DRIVER)),",
 			},
 		},
 		{
 			Pad: test.Pad{ID: "GPP_H8", DW0: 0x77777777, DW1: 0x77777777, Ownership: 0},
 			Macro: test.Macro{
 				Short: "PAD_CFG_NF_1V8(GPP_H8, UP_667, DEEP, NF5),",
-				Long:  "_PAD_CFG_STRUCT(GPP_H8, PAD_FUNC(NF5) | PAD_RESET(DEEP) | PAD_TRIG(EDGE_BOTH) | PAD_IRQ_ROUTE(IOAPIC) | PAD_IRQ_ROUTE(SMI) | PAD_IRQ_ROUTE(NMI) | PAD_BUF(TX_RX_DISABLE) | (1 << 29) | (1 << 28) | (1 << 1) | 1, PAD_CFG1_TOL_1V8PAD_PULL(UP_667) | PAD_IOSSTATE(IGNORE) | PAD_IOSTERM(ENPU)),",
+				Long:  "_PAD_CFG_STRUCT(GPP_H8, PAD_FUNC(NF5) | PAD_RESET(DEEP) | PAD_TRIG(EDGE_BOTH) | PAD_IRQ_ROUTE(IOAPIC) | PAD_IRQ_ROUTE(SMI) | PAD_IRQ_ROUTE(NMI) | PAD_BUF(TX_RX_DISABLE) | (1 << 29) | (1 << 28) | (1 << 1) | 1, PAD_CFG1_TOL_1V8PAD_PULL(UP_667) | PAD_IOSSTATE(ERROR) | PAD_IOSTERM(ENPU)),",
 			},
 		},
 	}.Run(t, "INTEL-ALDER-LAKE-PCH/SLIDING-ZERO-IN-NIBBLE-TEST", alderlake)
@@ -82,7 +82,7 @@ func TestGenMacro(t *testing.T) {
 			Pad: test.Pad{ID: "GPP_I9", DW0: 0x33333333, DW1: 0x33333333, Ownership: 1},
 			Macro: test.Macro{
 				Short: "PAD_CFG_NF_1V8(GPP_I9, UP_20K, RSMRST, NF4),",
-				Long:  "_PAD_CFG_STRUCT(GPP_I9, PAD_FUNC(NF4) | PAD_RESET(RSMRST) | PAD_TRIG(EDGE_SINGLE) | PAD_IRQ_ROUTE(IOAPIC) | PAD_IRQ_ROUTE(NMI) | PAD_BUF(TX_RX_DISABLE) | (1 << 29) | (1 << 28) | (1 << 1) | 1, PAD_CFG1_TOL_1V8PAD_PULL(UP_20K) | PAD_IOSSTATE(IGNORE) | PAD_IOSTERM(ENPU) | PAD_CFG_OWN_GPIO(DRIVER)),",
+				Long:  "_PAD_CFG_STRUCT(GPP_I9, PAD_FUNC(NF4) | PAD_RESET(RSMRST) | PAD_TRIG(EDGE_SINGLE) | PAD_IRQ_ROUTE(IOAPIC) | PAD_IRQ_ROUTE(NMI) | PAD_BUF(TX_RX_DISABLE) | (1 << 29) | (1 << 28) | (1 << 1) | 1, PAD_CFG1_TOL_1V8PAD_PULL(UP_20K) | PAD_IOSSTATE(ERROR) | PAD_IOSTERM(ENPU) | PAD_CFG_OWN_GPIO(DRIVER)),",
 			},
 		},
 		{
diff --git a/util/intelp2m/platforms/adl/macro.go b/util/intelp2m/platforms/adl/macro.go
index 2c4b5d81cf..7c4f4357bb 100644
--- a/util/intelp2m/platforms/adl/macro.go
+++ b/util/intelp2m/platforms/adl/macro.go
@@ -7,6 +7,7 @@ import (
 	"review.coreboot.org/coreboot.git/util/intelp2m/fields"
 	"review.coreboot.org/coreboot.git/util/intelp2m/platforms/cnl"
 	"review.coreboot.org/coreboot.git/util/intelp2m/platforms/common"
+	"review.coreboot.org/coreboot.git/util/intelp2m/platforms/common/register/bits"
 	"review.coreboot.org/coreboot.git/util/intelp2m/platforms/snr"
 )
 
@@ -15,12 +16,6 @@ const (
 	PAD_CFG_DW1_RO_FIELDS = 0xfdffc3ff
 )
 
-const (
-	PAD_CFG_DW0 = common.PAD_CFG_DW0
-	PAD_CFG_DW1 = common.PAD_CFG_DW1
-	MAX_DW_NUM  = common.MAX_DW_NUM
-)
-
 type InheritanceMacro interface {
 	Pull()
 	GpiMacroAdd()
@@ -43,22 +38,22 @@ func (PlatformSpecific) RemmapRstSrc() {
 		return
 	}
 
-	dw0 := macro.Register(PAD_CFG_DW0)
-	var remapping = map[uint8]uint32{
-		0: common.RST_RSMRST << common.PadRstCfgShift,
-		1: common.RST_DEEP << common.PadRstCfgShift,
-		2: common.RST_PLTRST << common.PadRstCfgShift,
-		3: common.RST_PWROK << common.PadRstCfgShift,
+	dw0 := macro.GetRegisterDW0()
+	remapping := map[uint32]uint32{
+		0: (bits.RstCfgRSMRST << bits.DW0PadRstCfg),
+		1: (bits.RstCfgDEEP << bits.DW0PadRstCfg),
+		2: (bits.RstCfgPLTRST << bits.DW0PadRstCfg),
+		3: (bits.RstCfgPWROK << bits.DW0PadRstCfg),
 	}
 	resetsrc, valid := remapping[dw0.GetResetConfig()]
 	if valid {
 		// dw0.SetResetConfig(resetsrc)
-		ResetConfigFieldVal := (dw0.ValueGet() & 0x3fffffff) | remapping[dw0.GetResetConfig()]
-		dw0.ValueSet(ResetConfigFieldVal)
+		ResetConfigFieldVal := (dw0.Value & 0x3fffffff) | remapping[dw0.GetResetConfig()]
+		dw0.Value = ResetConfigFieldVal
 	} else {
 		fmt.Println("Invalid Pad Reset Config [ 0x", resetsrc, " ] for ", macro.PadIdGet())
 	}
-	dw0.CntrMaskFieldsClear(common.PadRstCfgMask)
+	dw0.CntrMaskFieldsClear(0b11 << bits.DW0PadRstCfg)
 }
 
 // Adds The Pad Termination (TERM) parameter from PAD_CFG_DW1 to the macro
@@ -88,11 +83,11 @@ func (platform PlatformSpecific) NoConnMacroAdd() {
 }
 
 // GenMacro - generate pad macro
-// dw0 : DW0 config register value
-// dw1 : DW1 config register value
+// dw0Val : DW0 config register value
+// dw1Val : DW1 config register value
 // return: string of macro
 //         error
-func (PlatformSpecific) GenMacro(id string, dw0 uint32, dw1 uint32, ownership uint8) string {
+func (PlatformSpecific) GenMacro(id string, dw0Val uint32, dw1Val uint32, ownership uint8) string {
 	macro := common.GetInstanceMacro(
 		PlatformSpecific{
 			InheritanceMacro: cnl.PlatformSpecific{
@@ -102,10 +97,17 @@ func (PlatformSpecific) GenMacro(id string, dw0 uint32, dw1 uint32, ownership ui
 		fields.InterfaceGet(),
 	)
 	macro.Clear()
-	macro.Register(PAD_CFG_DW0).CntrMaskFieldsClear(common.AllFields)
-	macro.Register(PAD_CFG_DW1).CntrMaskFieldsClear(common.AllFields)
+	dw0 := macro.GetRegisterDW0()
+	dw0.CntrMaskFieldsClear(bits.All32)
+
+	dw1 := macro.GetRegisterDW1()
+	dw1.CntrMaskFieldsClear(bits.All32)
+
+	dw0.Value = dw0Val
+	dw1.Value = dw1Val
+
+	dw0.ReadOnly = PAD_CFG_DW0_RO_FIELDS
+	dw1.ReadOnly = PAD_CFG_DW1_RO_FIELDS
 	macro.PadIdSet(id).SetPadOwnership(ownership)
-	macro.Register(PAD_CFG_DW0).ValueSet(dw0).ReadOnlyFieldsSet(PAD_CFG_DW0_RO_FIELDS)
-	macro.Register(PAD_CFG_DW1).ValueSet(dw1).ReadOnlyFieldsSet(PAD_CFG_DW1_RO_FIELDS)
 	return macro.Generate()
 }
diff --git a/util/intelp2m/platforms/apl/macro.go b/util/intelp2m/platforms/apl/macro.go
index e5ac7c2a49..3e5bf74603 100644
--- a/util/intelp2m/platforms/apl/macro.go
+++ b/util/intelp2m/platforms/apl/macro.go
@@ -7,6 +7,7 @@ import (
 	"review.coreboot.org/coreboot.git/util/intelp2m/config/p2m"
 	"review.coreboot.org/coreboot.git/util/intelp2m/fields"
 	"review.coreboot.org/coreboot.git/util/intelp2m/platforms/common"
+	"review.coreboot.org/coreboot.git/util/intelp2m/platforms/common/register/bits"
 )
 
 const (
@@ -14,12 +15,6 @@ const (
 	PAD_CFG_DW1_RO_FIELDS = 0xfffc00ff
 )
 
-const (
-	PAD_CFG_DW0 = common.PAD_CFG_DW0
-	PAD_CFG_DW1 = common.PAD_CFG_DW1
-	MAX_DW_NUM  = common.MAX_DW_NUM
-)
-
 const (
 	PULL_NONE   = 0x0 // 0 000: none
 	PULL_DN_5K  = 0x2 // 0 010: 5k wpd (Only available on SMBus GPIOs)
@@ -42,8 +37,8 @@ func (PlatformSpecific) RemmapRstSrc() {}
 // return: macro
 func (PlatformSpecific) Pull() {
 	macro := common.GetMacro()
-	dw1 := macro.Register(PAD_CFG_DW1)
-	var pull = map[uint8]string{
+	dw1 := macro.GetRegisterDW1()
+	var pull = map[uint32]string{
 		PULL_NONE:   "NONE",
 		PULL_DN_5K:  "DN_5K",
 		PULL_DN_20K: "DN_20K",
@@ -53,10 +48,9 @@ func (PlatformSpecific) Pull() {
 		PULL_UP_667: "UP_667",
 		PULL_NATIVE: "NATIVE",
 	}
-	terminationFieldValue := dw1.GetTermination()
-	str, valid := pull[terminationFieldValue]
-	if !valid {
-		str = strconv.Itoa(int(terminationFieldValue))
+	str, exist := pull[dw1.GetTermination()]
+	if !exist {
+		str = strconv.Itoa(int(dw1.GetTermination()))
 		fmt.Println("Error", macro.PadIdGet(), " invalid TERM value = ", str)
 	}
 	macro.Separator().Add(str)
@@ -65,8 +59,8 @@ func (PlatformSpecific) Pull() {
 // Generate macro to cause peripheral IRQ when configured in GPIO input mode
 func ioApicRoute() bool {
 	macro := common.GetMacro()
-	dw0 := macro.Register(PAD_CFG_DW0)
-	dw1 := macro.Register(PAD_CFG_DW1)
+	dw0 := macro.GetRegisterDW0()
+	dw1 := macro.GetRegisterDW1()
 	if dw0.GetGPIOInputRouteIOxAPIC() == 0 {
 		return false
 	}
@@ -86,7 +80,7 @@ func ioApicRoute() bool {
 // Generate macro to cause NMI when configured in GPIO input mode
 func nmiRoute() bool {
 	macro := common.GetMacro()
-	if macro.Register(PAD_CFG_DW0).GetGPIOInputRouteNMI() == 0 {
+	if macro.GetRegisterDW0().GetGPIOInputRouteNMI() == 0 {
 		return false
 	}
 	// e.g. PAD_CFG_GPI_NMI(GPIO_24, UP_20K, DEEP, LEVEL, INVERT),
@@ -97,8 +91,8 @@ func nmiRoute() bool {
 // Generate macro to cause SCI when configured in GPIO input mode
 func sciRoute() bool {
 	macro := common.GetMacro()
-	dw0 := macro.Register(PAD_CFG_DW0)
-	dw1 := macro.Register(PAD_CFG_DW0)
+	dw0 := macro.GetRegisterDW0()
+	dw1 := macro.GetRegisterDW1()
 	if dw0.GetGPIOInputRouteSCI() == 0 {
 		return false
 	}
@@ -120,8 +114,8 @@ func sciRoute() bool {
 // Generate macro to cause SMI when configured in GPIO input mode
 func smiRoute() bool {
 	macro := common.GetMacro()
-	dw0 := macro.Register(PAD_CFG_DW0)
-	dw1 := macro.Register(PAD_CFG_DW1)
+	dw0 := macro.GetRegisterDW0()
+	dw1 := macro.GetRegisterDW1()
 	if dw0.GetGPIOInputRouteSMI() == 0 {
 		return false
 	}
@@ -159,7 +153,7 @@ func (PlatformSpecific) GpiMacroAdd() {
 
 	switch config, argc := p2m.Config, len(ids); argc {
 	case 0:
-		dw1 := macro.Register(PAD_CFG_DW1)
+		dw1 := macro.GetRegisterDW1()
 		isIOStandbyStateUsed := dw1.GetIOStandbyState() != 0
 		isIOStandbyTerminationUsed := dw1.GetIOStandbyTermination() != 0
 		if isIOStandbyStateUsed && !isIOStandbyTerminationUsed {
@@ -189,15 +183,15 @@ func (PlatformSpecific) GpiMacroAdd() {
 	default:
 		// Clear the control mask so that the check fails and "Advanced" macro is
 		// generated
-		macro.Register(PAD_CFG_DW0).CntrMaskFieldsClear(common.AllFields)
+		macro.GetRegisterDW0().CntrMaskFieldsClear(bits.All32)
 	}
 }
 
 // Adds PAD_CFG_GPO macro with arguments
 func (PlatformSpecific) GpoMacroAdd() {
 	macro := common.GetMacro()
-	dw0 := macro.Register(PAD_CFG_DW0)
-	dw1 := macro.Register(PAD_CFG_DW1)
+	dw0 := macro.GetRegisterDW0()
+	dw1 := macro.GetRegisterDW1()
 	term := dw1.GetTermination()
 
 	macro.Set("PAD_CFG")
@@ -219,22 +213,22 @@ func (PlatformSpecific) GpoMacroAdd() {
 	}
 	macro.Add("),")
 
-	if dw0.GetRXLevelEdgeConfiguration() != common.TRIG_OFF {
+	if dw0.GetRXLevelEdgeConfiguration() != bits.TrigOFF {
 		// ignore if trig = OFF is not set
-		dw0.CntrMaskFieldsClear(common.RxLevelEdgeConfigurationMask)
+		dw0.CntrMaskFieldsClear(bits.DW0[bits.DW0RxLevelEdgeConfiguration])
 	}
 }
 
 // Adds PAD_CFG_NF macro with arguments
 func (PlatformSpecific) NativeFunctionMacroAdd() {
 	macro := common.GetMacro()
-	dw1 := macro.Register(PAD_CFG_DW1)
+	dw1 := macro.GetRegisterDW1()
 	isIOStandbyStateUsed := dw1.GetIOStandbyState() != 0
 	isIOStandbyTerminationUsed := dw1.GetIOStandbyTermination() != 0
 
 	macro.Set("PAD_CFG_NF")
 	if !isIOStandbyTerminationUsed && isIOStandbyStateUsed {
-		if dw1.GetIOStandbyState() == common.StandbyIgnore {
+		if dw1.GetIOStandbyState() == bits.IOStateStandbyIgnore {
 			// PAD_CFG_NF_IOSTANDBY_IGNORE(PMU_SLP_S0_B, NONE, DEEP, NF1),
 			macro.Add("_IOSTANDBY_IGNORE(").Id().Pull().Rstsrc().Padfn()
 		} else {
@@ -250,27 +244,26 @@ func (PlatformSpecific) NativeFunctionMacroAdd() {
 	}
 	macro.Add("),")
 
-	if dw0 := macro.Register(PAD_CFG_DW0); dw0.GetGPIORxTxDisableStatus() != 0 {
+	if dw0 := macro.GetRegisterDW0(); dw0.GetGPIORxTxDisableStatus() != 0 {
 		// Since the bufbis parameter will be ignored for NF, we should clear
 		// the corresponding bits in the control mask.
-		dw0.CntrMaskFieldsClear(common.RxTxBufDisableMask)
+		dw0.CntrMaskFieldsClear(bits.DW0[bits.DW0RxTxBufDisable])
 	}
 }
 
 // Adds PAD_NC macro
 func (PlatformSpecific) NoConnMacroAdd() {
 	macro := common.GetMacro()
-	dw1 := macro.Register(PAD_CFG_DW1)
 
-	if dw1.GetIOStandbyState() == common.TxDRxE {
-		dw0 := macro.Register(PAD_CFG_DW0)
+	dw0, dw1 := macro.GetRegisterDW0(), macro.GetRegisterDW1()
+	if dw1.GetIOStandbyState() == bits.IOStateTxDRxE {
 
 		// See comments in sunrise/macro.go : NoConnMacroAdd()
-		if dw0.GetRXLevelEdgeConfiguration() != common.TRIG_OFF {
-			dw0.CntrMaskFieldsClear(common.RxLevelEdgeConfigurationMask)
+		if dw0.GetRXLevelEdgeConfiguration() != bits.TrigOFF {
+			dw0.CntrMaskFieldsClear(bits.DW0[bits.DW0RxLevelEdgeConfiguration])
 		}
 		if dw0.GetResetConfig() != 1 { // 1 = RST_DEEP
-			dw0.CntrMaskFieldsClear(common.PadRstCfgMask)
+			dw0.CntrMaskFieldsClear(bits.DW0[bits.DW0PadRstCfg])
 		}
 
 		// PAD_NC(OSC_CLK_OUT_1, DN_20K)
@@ -287,18 +280,27 @@ func (PlatformSpecific) NoConnMacroAdd() {
 }
 
 // GenMacro - generate pad macro
-// dw0 : DW0 config register value
-// dw1 : DW1 config register value
+// dw0Val : DW0 config register value
+// dw1Val : DW1 config register value
 // return: string of macro
-//
-//	error
-func (PlatformSpecific) GenMacro(id string, dw0 uint32, dw1 uint32, ownership uint8) string {
-	macro := common.GetInstanceMacro(PlatformSpecific{}, fields.InterfaceGet())
-	// use platform-specific interface in Macro struct
+func (PlatformSpecific) GenMacro(id string, dw0Val uint32, dw1Val uint32, ownership uint8) string {
+	macro := common.GetInstanceMacro(
+		PlatformSpecific{},
+		fields.InterfaceGet(),
+	)
+	macro.Clear()
+
+	dw0 := macro.GetRegisterDW0()
+	dw0.CntrMaskFieldsClear(bits.All32)
+
+	dw1 := macro.GetRegisterDW1()
+	dw1.CntrMaskFieldsClear(bits.All32)
+
+	dw0.Value = dw0Val
+	dw1.Value = dw1Val
+	dw0.ReadOnly = PAD_CFG_DW0_RO_FIELDS
+	dw1.ReadOnly = PAD_CFG_DW1_RO_FIELDS
+
 	macro.PadIdSet(id).SetPadOwnership(ownership)
-	macro.Register(PAD_CFG_DW0).CntrMaskFieldsClear(common.AllFields)
-	macro.Register(PAD_CFG_DW1).CntrMaskFieldsClear(common.AllFields)
-	macro.Register(PAD_CFG_DW0).ValueSet(dw0).ReadOnlyFieldsSet(PAD_CFG_DW0_RO_FIELDS)
-	macro.Register(PAD_CFG_DW1).ValueSet(dw1).ReadOnlyFieldsSet(PAD_CFG_DW1_RO_FIELDS)
 	return macro.Generate()
 }
diff --git a/util/intelp2m/platforms/cnl/cnl_test.go b/util/intelp2m/platforms/cnl/cnl_test.go
index ad2b65ef64..e7fe0d546f 100644
--- a/util/intelp2m/platforms/cnl/cnl_test.go
+++ b/util/intelp2m/platforms/cnl/cnl_test.go
@@ -48,7 +48,7 @@ func TestGenMacro(t *testing.T) {
 			Pad: test.Pad{ID: "GPP_F5", DW0: 0xEEEEEEEE, DW1: 0xEEEEEEEE, Ownership: 1},
 			Macro: test.Macro{
 				Short: "PAD_CFG_NF_1V8(GPP_F5, UP_2K, RSMRST, NF3),",
-				Long:  "_PAD_CFG_STRUCT(GPP_F5, PAD_FUNC(NF3) | PAD_RESET(RSMRST) | PAD_TRIG(EDGE_BOTH) | PAD_IRQ_ROUTE(SCI) | PAD_IRQ_ROUTE(SMI) | PAD_IRQ_ROUTE(NMI) | PAD_RX_POL(INVERT) | PAD_BUF(RX_DISABLE) | (1 << 29) | (1 << 1), PAD_CFG1_TOL_1V8PAD_PULL(UP_2K) | PAD_IOSSTATE(IGNORE) | PAD_IOSTERM(ENPD) | PAD_CFG_OWN_GPIO(DRIVER)),",
+				Long:  "_PAD_CFG_STRUCT(GPP_F5, PAD_FUNC(NF3) | PAD_RESET(RSMRST) | PAD_TRIG(EDGE_BOTH) | PAD_IRQ_ROUTE(SCI) | PAD_IRQ_ROUTE(SMI) | PAD_IRQ_ROUTE(NMI) | PAD_RX_POL(INVERT) | PAD_BUF(RX_DISABLE) | (1 << 29) | (1 << 1), PAD_CFG1_TOL_1V8PAD_PULL(UP_2K) | PAD_IOSSTATE(ERROR) | PAD_IOSTERM(ENPD) | PAD_CFG_OWN_GPIO(DRIVER)),",
 			},
 		},
 		{
@@ -62,14 +62,14 @@ func TestGenMacro(t *testing.T) {
 			Pad: test.Pad{ID: "GPD7", DW0: 0xBBBBBBBB, DW1: 0xBBBBBBBB, Ownership: 1},
 			Macro: test.Macro{
 				Short: "PAD_CFG_NF_1V8(GPD7, INVALID, PLTRST, NF6),",
-				Long:  "_PAD_CFG_STRUCT(GPD7, PAD_FUNC(NF6) | PAD_RESET(PLTRST) | PAD_TRIG(EDGE_SINGLE) | PAD_IRQ_ROUTE(IOAPIC) | PAD_IRQ_ROUTE(SCI) | PAD_IRQ_ROUTE(NMI) | PAD_RX_POL(INVERT) | PAD_BUF(TX_RX_DISABLE) | (1 << 29) | (1 << 28) | (1 << 1) | 1, PAD_CFG1_TOL_1V8PAD_PULL(INVALID) | PAD_IOSSTATE(IGNORE) | PAD_IOSTERM(ENPU) | PAD_CFG_OWN_GPIO(DRIVER)),",
+				Long:  "_PAD_CFG_STRUCT(GPD7, PAD_FUNC(NF6) | PAD_RESET(PLTRST) | PAD_TRIG(EDGE_SINGLE) | PAD_IRQ_ROUTE(IOAPIC) | PAD_IRQ_ROUTE(SCI) | PAD_IRQ_ROUTE(NMI) | PAD_RX_POL(INVERT) | PAD_BUF(TX_RX_DISABLE) | (1 << 29) | (1 << 28) | (1 << 1) | 1, PAD_CFG1_TOL_1V8PAD_PULL(INVALID) | PAD_IOSSTATE(ERROR) | PAD_IOSTERM(ENPU) | PAD_CFG_OWN_GPIO(DRIVER)),",
 			},
 		},
 		{
 			Pad: test.Pad{ID: "GPP_C8", DW0: 0x77777777, DW1: 0x77777777, Ownership: 0},
 			Macro: test.Macro{
 				Short: "PAD_CFG_NF_1V8(GPP_C8, UP_667, DEEP, NF5),",
-				Long:  "_PAD_CFG_STRUCT(GPP_C8, PAD_FUNC(NF5) | PAD_RESET(DEEP) | PAD_TRIG(EDGE_BOTH) | PAD_IRQ_ROUTE(IOAPIC) | PAD_IRQ_ROUTE(SMI) | PAD_IRQ_ROUTE(NMI) | PAD_BUF(TX_RX_DISABLE) | (1 << 29) | (1 << 28) | (1 << 1) | 1, PAD_CFG1_TOL_1V8PAD_PULL(UP_667) | PAD_IOSSTATE(IGNORE) | PAD_IOSTERM(ENPU)),",
+				Long:  "_PAD_CFG_STRUCT(GPP_C8, PAD_FUNC(NF5) | PAD_RESET(DEEP) | PAD_TRIG(EDGE_BOTH) | PAD_IRQ_ROUTE(IOAPIC) | PAD_IRQ_ROUTE(SMI) | PAD_IRQ_ROUTE(NMI) | PAD_BUF(TX_RX_DISABLE) | (1 << 29) | (1 << 28) | (1 << 1) | 1, PAD_CFG1_TOL_1V8PAD_PULL(UP_667) | PAD_IOSSTATE(ERROR) | PAD_IOSTERM(ENPU)),",
 			},
 		},
 	}.Run(t, "INTEL-CANNON-LAKE-PCH/SLIDING-ZERO-IN-NIBBLE-TEST", cannonlake)
@@ -79,7 +79,7 @@ func TestGenMacro(t *testing.T) {
 			Pad: test.Pad{ID: "GPP_E9", DW0: 0x33333333, DW1: 0x33333333, Ownership: 1},
 			Macro: test.Macro{
 				Short: "PAD_CFG_NF_1V8(GPP_E9, UP_20K, RSMRST, NF4),",
-				Long:  "_PAD_CFG_STRUCT(GPP_E9, PAD_FUNC(NF4) | PAD_RESET(RSMRST) | PAD_TRIG(EDGE_SINGLE) | PAD_IRQ_ROUTE(IOAPIC) | PAD_IRQ_ROUTE(NMI) | PAD_BUF(TX_RX_DISABLE) | (1 << 29) | (1 << 28) | (1 << 1) | 1, PAD_CFG1_TOL_1V8PAD_PULL(UP_20K) | PAD_IOSSTATE(IGNORE) | PAD_IOSTERM(ENPU) | PAD_CFG_OWN_GPIO(DRIVER)),",
+				Long:  "_PAD_CFG_STRUCT(GPP_E9, PAD_FUNC(NF4) | PAD_RESET(RSMRST) | PAD_TRIG(EDGE_SINGLE) | PAD_IRQ_ROUTE(IOAPIC) | PAD_IRQ_ROUTE(NMI) | PAD_BUF(TX_RX_DISABLE) | (1 << 29) | (1 << 28) | (1 << 1) | 1, PAD_CFG1_TOL_1V8PAD_PULL(UP_20K) | PAD_IOSSTATE(ERROR) | PAD_IOSTERM(ENPU) | PAD_CFG_OWN_GPIO(DRIVER)),",
 			},
 		},
 		{
diff --git a/util/intelp2m/platforms/cnl/macro.go b/util/intelp2m/platforms/cnl/macro.go
index 19fee99cb9..ab524f5e15 100644
--- a/util/intelp2m/platforms/cnl/macro.go
+++ b/util/intelp2m/platforms/cnl/macro.go
@@ -7,6 +7,7 @@ import (
 	"review.coreboot.org/coreboot.git/util/intelp2m/config/p2m"
 	"review.coreboot.org/coreboot.git/util/intelp2m/fields"
 	"review.coreboot.org/coreboot.git/util/intelp2m/platforms/common"
+	"review.coreboot.org/coreboot.git/util/intelp2m/platforms/common/register/bits"
 	"review.coreboot.org/coreboot.git/util/intelp2m/platforms/snr"
 )
 
@@ -15,12 +16,6 @@ const (
 	PAD_CFG_DW1_RO_FIELDS = 0xfdffc3ff
 )
 
-const (
-	PAD_CFG_DW0 = common.PAD_CFG_DW0
-	PAD_CFG_DW1 = common.PAD_CFG_DW1
-	MAX_DW_NUM  = common.MAX_DW_NUM
-)
-
 type InheritanceMacro interface {
 	GpoMacroAdd()
 	NativeFunctionMacroAdd()
@@ -44,29 +39,30 @@ func (PlatformSpecific) RemmapRstSrc() {
 		return
 	}
 
-	dw0 := macro.Register(PAD_CFG_DW0)
-	var remapping = map[uint8]uint32{
-		0: common.RST_RSMRST << common.PadRstCfgShift,
-		1: common.RST_DEEP << common.PadRstCfgShift,
-		2: common.RST_PLTRST << common.PadRstCfgShift,
+	dw0 := macro.GetRegisterDW0()
+	var remapping = map[uint32]uint32{
+		0: bits.RstCfgRSMRST << bits.DW0PadRstCfg,
+		1: bits.RstCfgDEEP << bits.DW0PadRstCfg,
+		2: bits.RstCfgPLTRST << bits.DW0PadRstCfg,
 	}
 	resetsrc, valid := remapping[dw0.GetResetConfig()]
 	if valid {
 		// dw0.SetResetConfig(resetsrc)
-		ResetConfigFieldVal := (dw0.ValueGet() & 0x3fffffff) | remapping[dw0.GetResetConfig()]
-		dw0.ValueSet(ResetConfigFieldVal)
+		ResetConfigFieldVal := (dw0.Value & 0x3fffffff) | remapping[dw0.GetResetConfig()]
+		dw0.Value = ResetConfigFieldVal
 	} else {
 		fmt.Println("Invalid Pad Reset Config [ 0x", resetsrc, " ] for ", macro.PadIdGet())
 	}
-	dw0.CntrMaskFieldsClear(common.PadRstCfgMask)
+	mask := bits.DW0[bits.DW0PadRstCfg]
+	dw0.CntrMaskFieldsClear(mask)
 }
 
 // Adds The Pad Termination (TERM) parameter from PAD_CFG_DW1 to the macro
 // as a new argument
 func (PlatformSpecific) Pull() {
 	macro := common.GetMacro()
-	dw1 := macro.Register(PAD_CFG_DW1)
-	var pull = map[uint8]string{
+	dw1 := macro.GetRegisterDW1()
+	var pull = map[uint32]string{
 		0x0: "NONE",
 		0x2: "DN_5K",
 		0x4: "DN_20K",
@@ -91,7 +87,7 @@ func (PlatformSpecific) Pull() {
 // Generate macro to cause peripheral IRQ when configured in GPIO input mode
 func ioApicRoute() bool {
 	macro := common.GetMacro()
-	dw0 := macro.Register(PAD_CFG_DW0)
+	dw0 := macro.GetRegisterDW0()
 	if dw0.GetGPIOInputRouteIOxAPIC() == 0 {
 		return false
 	}
@@ -105,7 +101,7 @@ func ioApicRoute() bool {
 // Generate macro to cause NMI when configured in GPIO input mode
 func nmiRoute() bool {
 	macro := common.GetMacro()
-	if macro.Register(PAD_CFG_DW0).GetGPIOInputRouteNMI() == 0 {
+	if macro.GetRegisterDW0().GetGPIOInputRouteNMI() == 0 {
 		return false
 	}
 	// PAD_CFG_GPI_NMI(GPIO_24, UP_20K, DEEP, LEVEL, INVERT),
@@ -116,8 +112,7 @@ func nmiRoute() bool {
 // Generate macro to cause SCI when configured in GPIO input mode
 func sciRoute() bool {
 	macro := common.GetMacro()
-	dw0 := macro.Register(PAD_CFG_DW0)
-	if dw0.GetGPIOInputRouteSCI() == 0 {
+	if macro.GetRegisterDW0().GetGPIOInputRouteSCI() == 0 {
 		return false
 	}
 	// PAD_CFG_GPI_SCI(pad, pull, rst, trig, inv)
@@ -128,8 +123,8 @@ func sciRoute() bool {
 // Generate macro to cause SMI when configured in GPIO input mode
 func smiRoute() bool {
 	macro := common.GetMacro()
-	dw0 := macro.Register(PAD_CFG_DW0)
-	if dw0.GetGPIOInputRouteSMI() == 0 {
+
+	if macro.GetRegisterDW0().GetGPIOInputRouteSMI() == 0 {
 		return false
 	}
 	// PAD_CFG_GPI_SMI(pad, pull, rst, trig, inv)
@@ -175,7 +170,7 @@ func (PlatformSpecific) GpiMacroAdd() {
 	default:
 		// Clear the control mask so that the check fails and "Advanced" macro is
 		// generated
-		macro.Register(PAD_CFG_DW0).CntrMaskFieldsClear(common.AllFields)
+		macro.GetRegisterDW0().CntrMaskFieldsClear(bits.All32)
 	}
 }
 
@@ -195,19 +190,30 @@ func (platform PlatformSpecific) NoConnMacroAdd() {
 }
 
 // GenMacro - generate pad macro
-// dw0 : DW0 config register value
-// dw1 : DW1 config register value
+// dw0Val : DW0 config register value
+// dw1Val : DW1 config register value
 // return: string of macro
-//
-//	error
-func (PlatformSpecific) GenMacro(id string, dw0 uint32, dw1 uint32, ownership uint8) string {
-	macro := common.GetInstanceMacro(PlatformSpecific{InheritanceMacro: snr.PlatformSpecific{}},
-		fields.InterfaceGet())
+func (PlatformSpecific) GenMacro(id string, dw0Val uint32, dw1Val uint32, ownership uint8) string {
+	macro := common.GetInstanceMacro(
+		PlatformSpecific{
+			InheritanceMacro: snr.PlatformSpecific{},
+		},
+		fields.InterfaceGet(),
+	)
 	macro.Clear()
-	macro.Register(PAD_CFG_DW0).CntrMaskFieldsClear(common.AllFields)
-	macro.Register(PAD_CFG_DW1).CntrMaskFieldsClear(common.AllFields)
+
+	dw0 := macro.GetRegisterDW0()
+	dw0.CntrMaskFieldsClear(bits.All32)
+
+	dw1 := macro.GetRegisterDW1()
+	dw1.CntrMaskFieldsClear(bits.All32)
+
+	dw0.Value = dw0Val
+	dw1.Value = dw1Val
+
+	dw0.ReadOnly = PAD_CFG_DW0_RO_FIELDS
+	dw1.ReadOnly = PAD_CFG_DW1_RO_FIELDS
+
 	macro.PadIdSet(id).SetPadOwnership(ownership)
-	macro.Register(PAD_CFG_DW0).ValueSet(dw0).ReadOnlyFieldsSet(PAD_CFG_DW0_RO_FIELDS)
-	macro.Register(PAD_CFG_DW1).ValueSet(dw1).ReadOnlyFieldsSet(PAD_CFG_DW1_RO_FIELDS)
 	return macro.Generate()
 }
diff --git a/util/intelp2m/platforms/common/macro.go b/util/intelp2m/platforms/common/macro.go
index 853fcf2489..782a61e5b7 100644
--- a/util/intelp2m/platforms/common/macro.go
+++ b/util/intelp2m/platforms/common/macro.go
@@ -1,10 +1,13 @@
 package common
 
 import (
+	"fmt"
 	"strconv"
 	"sync"
 
 	"review.coreboot.org/coreboot.git/util/intelp2m/config/p2m"
+	"review.coreboot.org/coreboot.git/util/intelp2m/platforms/common/register"
+	"review.coreboot.org/coreboot.git/util/intelp2m/platforms/common/register/bits"
 )
 
 type Fields interface {
@@ -18,41 +21,6 @@ const (
 	PAD_OWN_DRIVER = 1
 )
 
-const (
-	TxLASTRxE     = 0x0
-	Tx0RxDCRx0    = 0x1
-	Tx0RxDCRx1    = 0x2
-	Tx1RxDCRx0    = 0x3
-	Tx1RxDCRx1    = 0x4
-	Tx0RxE        = 0x5
-	Tx1RxE        = 0x6
-	HIZCRx0       = 0x7
-	HIZCRx1       = 0x8
-	TxDRxE        = 0x9
-	StandbyIgnore = 0xf
-)
-
-const (
-	IOSTERM_SAME    = 0x0
-	IOSTERM_DISPUPD = 0x1
-	IOSTERM_ENPD    = 0x2
-	IOSTERM_ENPU    = 0x3
-)
-
-const (
-	TRIG_LEVEL       = 0
-	TRIG_EDGE_SINGLE = 1
-	TRIG_OFF         = 2
-	TRIG_EDGE_BOTH   = 3
-)
-
-const (
-	RST_PWROK  = 0
-	RST_DEEP   = 1
-	RST_PLTRST = 2
-	RST_RSMRST = 3
-)
-
 // PlatformSpecific - platform-specific interface
 type PlatformSpecific interface {
 	RemmapRstSrc()
@@ -70,7 +38,8 @@ type PlatformSpecific interface {
 // Reg      : structure of configuration register values and their masks
 type Macro struct {
 	Platform  PlatformSpecific
-	Reg       [MAX_DW_NUM]Register
+	DW0       register.DW0
+	DW1       register.DW1
 	padID     string
 	str       string
 	ownership uint8
@@ -110,10 +79,12 @@ func (macro *Macro) IsOwnershipDriver() bool {
 	return macro.ownership == PAD_OWN_DRIVER
 }
 
-// returns <Register> data configuration structure
-// number : register number
-func (macro *Macro) Register(number uint8) *Register {
-	return &macro.Reg[number]
+func (macro *Macro) GetRegisterDW0() *register.DW0 {
+	return &macro.DW0
+}
+
+func (macro *Macro) GetRegisterDW1() *register.DW1 {
+	return &macro.DW1
 }
 
 // add a string to macro
@@ -158,14 +129,18 @@ func (macro *Macro) Separator() *Macro {
 // Adds the PADRSTCFG parameter from DW0 to the macro as a new argument
 // return: Macro
 func (macro *Macro) Rstsrc() *Macro {
-	dw0 := macro.Register(PAD_CFG_DW0)
-	var resetsrc = map[uint8]string{
-		0: "PWROK",
-		1: "DEEP",
-		2: "PLTRST",
-		3: "RSMRST",
+	dw0 := macro.GetRegisterDW0()
+	resetsrc := map[uint32]string{
+		0b00: "PWROK",
+		0b01: "DEEP",
+		0b10: "PLTRST",
+		0b11: "RSMRST",
 	}
-	return macro.Separator().Add(resetsrc[dw0.GetResetConfig()])
+	source, exist := resetsrc[dw0.GetResetConfig()]
+	if !exist {
+		source = "ERROR"
+	}
+	return macro.Separator().Add(source)
 }
 
 // Adds The Pad Termination (TERM) parameter from DW1 to the macro as a new argument
@@ -178,44 +153,51 @@ func (macro *Macro) Pull() *Macro {
 // Adds Pad GPO value to macro string as a new argument
 // return: Macro
 func (macro *Macro) Val() *Macro {
-	dw0 := macro.Register(PAD_CFG_DW0)
+	dw0 := macro.GetRegisterDW0()
 	return macro.Separator().Add(strconv.Itoa(int(dw0.GetGPIOTXState())))
 }
 
 // Adds Pad GPO value to macro string as a new argument
 // return: Macro
 func (macro *Macro) Trig() *Macro {
-	dw0 := macro.Register(PAD_CFG_DW0)
-	var trig = map[uint8]string{
-		0x0: "LEVEL",
-		0x1: "EDGE_SINGLE",
-		0x2: "OFF",
-		0x3: "EDGE_BOTH",
+	dw0 := macro.GetRegisterDW0()
+	trig := map[uint32]string{
+		0b00: "LEVEL",
+		0b01: "EDGE_SINGLE",
+		0b10: "OFF",
+		0b11: "EDGE_BOTH",
 	}
-	return macro.Separator().Add(trig[dw0.GetRXLevelEdgeConfiguration()])
+	level, exist := trig[dw0.GetRXLevelEdgeConfiguration()]
+	if !exist {
+		level = "ERROR"
+	}
+	return macro.Separator().Add(level)
 }
 
 // Adds Pad Polarity Inversion Stage (RXINV) to macro string as a new argument
 // return: Macro
 func (macro *Macro) Invert() *Macro {
-	macro.Separator()
-	if macro.Register(PAD_CFG_DW0).GetRxInvert() != 0 {
-		return macro.Add("INVERT")
+	if macro.GetRegisterDW0().GetRxInvert() != 0 {
+		return macro.Separator().Add("INVERT")
 	}
-	return macro.Add("NONE")
+	return macro.Separator().Add("NONE")
 }
 
 // Adds input/output buffer state
 // return: Macro
 func (macro *Macro) Bufdis() *Macro {
-	var buffDisStat = map[uint8]string{
-		0x0: "NO_DISABLE",    // both buffers are enabled
-		0x1: "TX_DISABLE",    // output buffer is disabled
-		0x2: "RX_DISABLE",    // input buffer is disabled
-		0x3: "TX_RX_DISABLE", // both buffers are disabled
+	dw0 := macro.GetRegisterDW0()
+	states := map[uint32]string{
+		0b00: "NO_DISABLE",    // both buffers are enabled
+		0b01: "TX_DISABLE",    // output buffer is disabled
+		0b10: "RX_DISABLE",    // input buffer is disabled
+		0b11: "TX_RX_DISABLE", // both buffers are disabled
 	}
-	state := macro.Register(PAD_CFG_DW0).GetGPIORxTxDisableStatus()
-	return macro.Separator().Add(buffDisStat[state])
+	state, exist := states[dw0.GetGPIORxTxDisableStatus()]
+	if !exist {
+		state = "ERROR"
+	}
+	return macro.Separator().Add(state)
 }
 
 // Adds macro to set the host software ownership
@@ -230,10 +212,9 @@ func (macro *Macro) Own() *Macro {
 // Adds pad native function (PMODE) as a new argument
 // return: Macro
 func (macro *Macro) Padfn() *Macro {
-	dw0 := macro.Register(PAD_CFG_DW0)
-	nfnum := int(dw0.GetPadMode())
-	if nfnum != 0 {
-		return macro.Separator().Add("NF" + strconv.Itoa(nfnum))
+	dw0 := macro.GetRegisterDW0()
+	if number := dw0.GetPadMode(); number != 0 {
+		return macro.Separator().Add(fmt.Sprintf("NF%d", number))
 	}
 	// GPIO used only for PAD_FUNC(x) macro
 	return macro.Add("GPIO")
@@ -242,44 +223,49 @@ func (macro *Macro) Padfn() *Macro {
 // Add a line to the macro that defines IO Standby State
 // return: macro
 func (macro *Macro) IOSstate() *Macro {
-	var stateMacro = map[uint8]string{
-		TxLASTRxE:     "TxLASTRxE",
-		Tx0RxDCRx0:    "Tx0RxDCRx0",
-		Tx0RxDCRx1:    "Tx0RxDCRx1",
-		Tx1RxDCRx0:    "Tx1RxDCRx0",
-		Tx1RxDCRx1:    "Tx1RxDCRx1",
-		Tx0RxE:        "Tx0RxE",
-		Tx1RxE:        "Tx1RxE",
-		HIZCRx0:       "HIZCRx0",
-		HIZCRx1:       "HIZCRx1",
-		TxDRxE:        "TxDRxE",
-		StandbyIgnore: "IGNORE",
+	states := map[uint32]string{
+		bits.IOStateTxLASTRxE:     "TxLASTRxE",
+		bits.IOStateTx0RxDCRx0:    "Tx0RxDCRx0",
+		bits.IOStateTx0RxDCRx1:    "Tx0RxDCRx1",
+		bits.IOStateTx1RxDCRx0:    "Tx1RxDCRx0",
+		bits.IOStateTx1RxDCRx1:    "Tx1RxDCRx1",
+		bits.IOStateTx0RxE:        "Tx0RxE",
+		bits.IOStateTx1RxE:        "Tx1RxE",
+		bits.IOStateHIZCRx0:       "HIZCRx0",
+		bits.IOStateHIZCRx1:       "HIZCRx1",
+		bits.IOStateTxDRxE:        "TxDRxE",
+		bits.IOStateStandbyIgnore: "IGNORE",
 	}
-	dw1 := macro.Register(PAD_CFG_DW1)
-	str, valid := stateMacro[dw1.GetIOStandbyState()]
-	if !valid {
+	dw1 := macro.GetRegisterDW1()
+	state, exist := states[dw1.GetIOStandbyState()]
+	if !exist {
 		// ignore setting for incorrect value
-		str = "IGNORE"
+		state = "ERROR"
 	}
-	return macro.Separator().Add(str)
+	return macro.Separator().Add(state)
 }
 
 // Add a line to the macro that defines IO Standby Termination
 // return: macro
 func (macro *Macro) IOTerm() *Macro {
-	var ioTermMacro = map[uint8]string{
-		IOSTERM_SAME:    "SAME",
-		IOSTERM_DISPUPD: "DISPUPD",
-		IOSTERM_ENPD:    "ENPD",
-		IOSTERM_ENPU:    "ENPU",
+	dw1 := macro.GetRegisterDW1()
+	terminations := map[uint32]string{
+		bits.IOTermSAME:    "SAME",
+		bits.IOTermDISPUPD: "DISPUPD",
+		bits.IOTermENPD:    "ENPD",
+		bits.IOTermENPU:    "ENPU",
 	}
-	dw1 := macro.Register(PAD_CFG_DW1)
-	return macro.Separator().Add(ioTermMacro[dw1.GetIOStandbyTermination()])
+	termination, exist := terminations[dw1.GetIOStandbyTermination()]
+	if !exist {
+		termination = "ERROR"
+	}
+	return macro.Separator().Add(termination)
 }
 
 // Check created macro
 func (macro *Macro) check() *Macro {
-	if !macro.Register(PAD_CFG_DW0).MaskCheck() {
+	dw0 := macro.GetRegisterDW0()
+	if !dw0.MaskCheck() {
 		return macro.GenerateFields()
 	}
 	return macro
@@ -293,35 +279,42 @@ func (macro *Macro) Or() *Macro {
 	return macro
 }
 
-// DecodeIgnored - Add info about ignored field mask
-// reg : PAD_CFG_DW0 or PAD_CFG_DW1 register
-func (macro *Macro) DecodeIgnored(reg uint8) *Macro {
-	var decode = map[uint8]func(){
-		PAD_CFG_DW0: macro.Fields.DecodeDW0,
-		PAD_CFG_DW1: macro.Fields.DecodeDW1,
-	}
-	decodefn, valid := decode[reg]
-	if !valid || p2m.Config.Field == p2m.FspFlds {
+func (macro *Macro) DecodeIgnoredFieldsDW0() *Macro {
+	if p2m.Config.Field == p2m.FspFlds {
 		return macro
 	}
-	dw := macro.Register(reg)
-	ignored := dw.IgnoredFieldsGet()
-	if ignored != 0 {
-		temp := dw.ValueGet()
-		dw.ValueSet(ignored)
-		regnum := strconv.Itoa(int(reg))
-		macro.Add("/* DW" + regnum + ": ")
-		decodefn()
+	dw0 := macro.GetRegisterDW0()
+	if ignored := dw0.IgnoredFieldsGet(); ignored != 0 {
+		saved := dw0.Value
+		dw0.Value = ignored
+		macro.Add("/* DW0: ")
+		macro.Fields.DecodeDW0()
 		macro.Add(" - IGNORED */\n\t")
-		dw.ValueSet(temp)
+		dw0.Value = saved
+	}
+	return macro
+}
+
+func (macro *Macro) DecodeIgnoredFieldsDW1() *Macro {
+	if p2m.Config.Field == p2m.FspFlds {
+		return macro
+	}
+	dw1 := macro.GetRegisterDW1()
+	if ignored := dw1.IgnoredFieldsGet(); ignored != 0 {
+		saved := dw1.Value
+		dw1.Value = ignored
+		macro.Add("/* DW0: ")
+		macro.DecodeDW1()
+		macro.Add(" - IGNORED */\n\t")
+		dw1.Value = saved
 	}
 	return macro
 }
 
 // GenerateFields - generate bitfield macros
 func (macro *Macro) GenerateFields() *Macro {
-	dw0 := macro.Register(PAD_CFG_DW0)
-	dw1 := macro.Register(PAD_CFG_DW1)
+	dw0 := macro.GetRegisterDW0()
+	dw1 := macro.GetRegisterDW1()
 
 	// Get mask of ignored bit fields.
 	dw0Ignored := dw0.IgnoredFieldsGet()
@@ -335,7 +328,8 @@ func (macro *Macro) GenerateFields() *Macro {
 		reference := macro.Get()
 		macro.Clear()
 		/* DW0 : PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1 - IGNORED */
-		macro.DecodeIgnored(PAD_CFG_DW0).DecodeIgnored(PAD_CFG_DW1)
+		macro.DecodeIgnoredFieldsDW0()
+		macro.DecodeIgnoredFieldsDW1()
 		if p2m.Config.GenLevel >= 4 {
 			/* PAD_CFG_NF(GPP_B23, 20K_PD, PLTRST, NF2), */
 			macro.Add("/* ").Add(reference).Add(" */\n\t")
@@ -344,11 +338,11 @@ func (macro *Macro) GenerateFields() *Macro {
 	if p2m.Config.IgnoredFields {
 		// Consider bit fields that should be ignored when regenerating
 		// advansed macros
-		var tempVal uint32 = dw0.ValueGet() & ^dw0Ignored
-		dw0.ValueSet(tempVal)
+		tempVal := dw0.Value & ^dw0Ignored
+		dw0.Value = tempVal
 
-		tempVal = dw1.ValueGet() & ^dw1Ignored
-		dw1.ValueSet(tempVal)
+		tempVal = dw1.Value & ^dw1Ignored
+		dw1.Value = tempVal
 	}
 
 	macro.Fields.GenerateString()
@@ -357,7 +351,7 @@ func (macro *Macro) GenerateFields() *Macro {
 
 // Generate macro for bi-directional GPIO port
 func (macro *Macro) Bidirection() {
-	dw1 := macro.Register(PAD_CFG_DW1)
+	dw1 := macro.GetRegisterDW1()
 	ios := dw1.GetIOStandbyState() != 0 || dw1.GetIOStandbyTermination() != 0
 	macro.Set("PAD_CFG_GPIO_BIDIRECT")
 	if ios {
@@ -372,19 +366,15 @@ func (macro *Macro) Bidirection() {
 	macro.Own().Add("),")
 }
 
-const (
-	rxDisable uint8 = 0x2
-	txDisable uint8 = 0x1
-)
-
 // Gets base string of current macro
 // return: string of macro
 func (macro *Macro) Generate() string {
-	dw0 := macro.Register(PAD_CFG_DW0)
+	const rxDisable uint32 = 0x2
+	const txDisable uint32 = 0x1
 
 	macro.Platform.RemmapRstSrc()
 	macro.Set("PAD_CFG")
-	if dw0.GetPadMode() == 0 {
+	if dw0 := macro.GetRegisterDW0(); dw0.GetPadMode() == 0 {
 		// GPIO
 		switch dw0.GetGPIORxTxDisableStatus() {
 		case txDisable:
@@ -411,7 +401,9 @@ func (macro *Macro) Generate() string {
 	if !p2m.Config.AutoCheck {
 		body := macro.Get()
 		if p2m.Config.GenLevel >= 3 {
-			macro.Clear().DecodeIgnored(PAD_CFG_DW0).DecodeIgnored(PAD_CFG_DW1)
+			macro.Clear()
+			macro.DecodeIgnoredFieldsDW0()
+			macro.DecodeIgnoredFieldsDW1()
 			comment := macro.Get()
 			if p2m.Config.GenLevel >= 4 {
 				macro.Clear().Add("/* ")
diff --git a/util/intelp2m/platforms/common/register.go b/util/intelp2m/platforms/common/register.go
deleted file mode 100644
index 2596b8d2cb..0000000000
--- a/util/intelp2m/platforms/common/register.go
+++ /dev/null
@@ -1,265 +0,0 @@
-package common
-
-// Bit field constants for PAD_CFG_DW0 register
-const (
-	AllFields uint32 = 0xffffffff
-
-	PadRstCfgShift uint8  = 30
-	PadRstCfgMask  uint32 = 0x3 << PadRstCfgShift
-
-	RxPadStateSelectShift uint8  = 29
-	RxPadStateSelectMask  uint32 = 0x1 << RxPadStateSelectShift
-
-	RxRawOverrideTo1Shift uint8  = 28
-	RxRawOverrideTo1Mask  uint32 = 0x1 << RxRawOverrideTo1Shift
-
-	RxLevelEdgeConfigurationShift uint8  = 25
-	RxLevelEdgeConfigurationMask  uint32 = 0x3 << RxLevelEdgeConfigurationShift
-
-	RxInvertShift uint8  = 23
-	RxInvertMask  uint32 = 0x1 << RxInvertShift
-
-	RxTxEnableConfigShift uint8  = 21
-	RxTxEnableConfigMask  uint32 = 0x3 << RxTxEnableConfigShift
-
-	InputRouteIOxApicShift uint8  = 20
-	InputRouteIOxApicMask  uint32 = 0x1 << InputRouteIOxApicShift
-
-	InputRouteSCIShift uint8  = 19
-	InputRouteSCIMask  uint32 = 0x1 << InputRouteSCIShift
-
-	InputRouteSMIShift uint8  = 18
-	InputRouteSMIMask  uint32 = 0x1 << InputRouteSMIShift
-
-	InputRouteNMIShift uint8  = 17
-	InputRouteNMIMask  uint32 = 0x1 << InputRouteNMIShift
-
-	PadModeShift uint8  = 10
-	PadModeMask  uint32 = 0x7 << PadModeShift
-
-	RxTxBufDisableShift uint8  = 8
-	RxTxBufDisableMask  uint32 = 0x3 << RxTxBufDisableShift
-
-	RxStateShift uint8  = 1
-	RxStateMask  uint32 = 0x1 << RxStateShift
-
-	TxStateMask uint32 = 0x1
-)
-
-// config DW registers
-const (
-	PAD_CFG_DW0 = 0
-	PAD_CFG_DW1 = 1
-	MAX_DW_NUM  = 2
-)
-
-// Register - configuration data structure based on DW0/1 dw value
-// value    : register value
-// mask     : bit fileds mask
-// roFileds : read only fields mask
-type Register struct {
-	value    uint32
-	mask     uint32
-	roFileds uint32
-}
-
-func (reg *Register) ValueSet(value uint32) *Register {
-	reg.value = value
-	return reg
-}
-
-func (reg *Register) ValueGet() uint32 {
-	return reg.value
-}
-
-func (reg *Register) ReadOnlyFieldsSet(fileldMask uint32) *Register {
-	reg.roFileds = fileldMask
-	return reg
-}
-
-func (reg *Register) ReadOnlyFieldsGet() uint32 {
-	return reg.roFileds
-}
-
-// Check the mask of the new macro
-// Returns true if the macro is generated correctly
-func (reg *Register) MaskCheck() bool {
-	mask := ^(reg.mask | reg.roFileds)
-	return (reg.value & mask) == 0
-}
-
-// getResetConfig - get Reset Configuration from PADRSTCFG field in PAD_CFG_DW0_GPx register
-func (reg *Register) getFieldVal(mask uint32, shift uint8) uint8 {
-	reg.mask |= mask
-	return uint8((reg.value & mask) >> shift)
-}
-
-// CntrMaskFieldsClear - clear filed in control mask
-// fieldMask - mask of the field to be cleared
-func (reg *Register) CntrMaskFieldsClear(fieldMask uint32) {
-	reg.mask &= ^fieldMask
-}
-
-// IgnoredFieldsGet - return mask of unchecked (ignored) fields.
-//
-//	These bit fields were not read when the macro was
-//	generated.
-//
-// return
-//
-//	mask of ignored bit field
-func (reg *Register) IgnoredFieldsGet() uint32 {
-	mask := reg.mask | reg.roFileds
-	return reg.value & ^mask
-}
-
-// getResetConfig - returns type reset source for corresponding pad
-// PADRSTCFG field in PAD_CFG_DW0 register
-func (reg *Register) GetResetConfig() uint8 {
-	return reg.getFieldVal(PadRstCfgMask, PadRstCfgShift)
-}
-
-// getRXPadStateSelect - returns RX Pad State (RXINV)
-// 0 = Raw RX pad state directly from RX buffer
-// 1 = Internal RX pad state
-func (reg *Register) GetRXPadStateSelect() uint8 {
-	return reg.getFieldVal(RxPadStateSelectMask, RxPadStateSelectShift)
-}
-
-// getRXRawOverrideStatus - returns 1 if the selected pad state is being
-// overridden to '1' (RXRAW1 field)
-func (reg *Register) GetRXRawOverrideStatus() uint8 {
-	return reg.getFieldVal(RxRawOverrideTo1Mask, RxRawOverrideTo1Shift)
-}
-
-// getRXLevelEdgeConfiguration - returns RX Level/Edge Configuration (RXEVCFG)
-// 0h = Level, 1h = Edge, 2h = Drive '0', 3h = Reserved (implement as setting 0h)
-func (reg *Register) GetRXLevelEdgeConfiguration() uint8 {
-	return reg.getFieldVal(RxLevelEdgeConfigurationMask, RxLevelEdgeConfigurationShift)
-}
-
-// GetRxInvert - returns RX Invert state (RXINV)
-// 1 - Inversion, 0 - No inversion
-func (reg *Register) GetRxInvert() uint8 {
-	return reg.getFieldVal(RxInvertMask, RxInvertShift)
-}
-
-// getRxTxEnableConfig - returns RX/TX Enable Config (RXTXENCFG)
-// 0 = Function defined in Pad Mode controls TX and RX Enables
-// 1 = Function controls TX Enable and RX Disabled with RX drive 0 internally
-// 2 = Function controls TX Enable and RX Disabled with RX drive 1 internally
-// 3 = Function controls TX Enabled and RX is always enabled
-func (reg *Register) GetRxTxEnableConfig() uint8 {
-	return reg.getFieldVal(RxTxEnableConfigMask, RxTxEnableConfigShift)
-}
-
-// getGPIOInputRouteIOxAPIC - returns 1 if the pad can be routed to cause
-// peripheral IRQ when configured in GPIO input mode.
-func (reg *Register) GetGPIOInputRouteIOxAPIC() uint8 {
-	return reg.getFieldVal(InputRouteIOxApicMask, InputRouteIOxApicShift)
-}
-
-// getGPIOInputRouteSCI - returns 1 if the pad can be routed to cause SCI when
-// configured in GPIO input mode.
-func (reg *Register) GetGPIOInputRouteSCI() uint8 {
-	return reg.getFieldVal(InputRouteSCIMask, InputRouteSCIShift)
-}
-
-// getGPIOInputRouteSMI - returns 1 if the pad can be routed to cause SMI when
-// configured in GPIO input mode
-func (reg *Register) GetGPIOInputRouteSMI() uint8 {
-	return reg.getFieldVal(InputRouteSMIMask, InputRouteSMIShift)
-}
-
-// getGPIOInputRouteNMI - returns 1 if the pad can be routed to cause NMI when
-// configured in GPIO input mode
-func (reg *Register) GetGPIOInputRouteNMI() uint8 {
-	return reg.getFieldVal(InputRouteNMIMask, InputRouteNMIShift)
-}
-
-// getPadMode - reutrns pad mode or one of the native functions
-// 0h = GPIO control the Pad.
-// 1h = native function 1, if applicable, controls the Pad
-// 2h = native function 2, if applicable, controls the Pad
-// 3h = native function 3, if applicable, controls the Pad
-// 4h = enable GPIO blink/PWM capability if applicable
-func (reg *Register) GetPadMode() uint8 {
-	return reg.getFieldVal(PadModeMask, PadModeShift)
-}
-
-// getGPIORxTxDisableStatus - returns GPIO RX/TX buffer state (GPIORXDIS | GPIOTXDIS)
-// 0 - both are enabled, 1 - TX Disable, 2 - RX Disable, 3 - both are disabled
-func (reg *Register) GetGPIORxTxDisableStatus() uint8 {
-	return reg.getFieldVal(RxTxBufDisableMask, RxTxBufDisableShift)
-}
-
-// getGPIORXState - returns GPIO RX State (GPIORXSTATE)
-func (reg *Register) GetGPIORXState() uint8 {
-	return reg.getFieldVal(RxStateMask, RxStateShift)
-}
-
-// getGPIOTXState - returns GPIO TX State (GPIOTXSTATE)
-func (reg *Register) GetGPIOTXState() uint8 {
-	return reg.getFieldVal(TxStateMask, 0)
-}
-
-// Bit field constants for PAD_CFG_DW1 register
-const (
-	PadTolShift uint8  = 25
-	PadTolMask  uint32 = 0x1 << PadTolShift
-
-	IOStandbyStateShift uint8  = 14
-	IOStandbyStateMask  uint32 = 0xF << IOStandbyStateShift
-
-	TermShift uint8  = 10
-	TermMask  uint32 = 0xF << TermShift
-
-	IOStandbyTerminationShift uint8  = 8
-	IOStandbyTerminationMask  uint32 = 0x3 << IOStandbyTerminationShift
-
-	InterruptSelectMask uint32 = 0xFF
-)
-
-// GetPadTol
-func (reg *Register) GetPadTol() uint8 {
-	return reg.getFieldVal(PadTolMask, PadTolShift)
-}
-
-// getIOStandbyState - return IO Standby State (IOSSTATE)
-// 0 = Tx enabled driving last value driven, Rx enabled
-// 1 = Tx enabled driving 0, Rx disabled and Rx driving 0 back to its controller internally
-// 2 = Tx enabled driving 0, Rx disabled and Rx driving 1 back to its controller internally
-// 3 = Tx enabled driving 1, Rx disabled and Rx driving 0 back to its controller internally
-// 4 = Tx enabled driving 1, Rx disabled and Rx driving 1 back to its controller internally
-// 5 = Tx enabled driving 0, Rx enabled
-// 6 = Tx enabled driving 1, Rx enabled
-// 7 = Hi-Z, Rx driving 0 back to its controller internally
-// 8 = Hi-Z, Rx driving 1 back to its controller internally
-// 9 = Tx disabled, Rx enabled
-// 15 = IO-Standby is ignored for this pin (same as functional mode)
-// Others reserved
-func (reg *Register) GetIOStandbyState() uint8 {
-	return reg.getFieldVal(IOStandbyStateMask, IOStandbyStateShift)
-}
-
-// getIOStandbyTermination - return IO Standby Termination (IOSTERM)
-// 0 = Same as functional mode (no change)
-// 1 = Disable Pull-up and Pull-down (no on-die termination)
-// 2 = Enable Pull-down
-// 3 = Enable Pull-up
-func (reg *Register) GetIOStandbyTermination() uint8 {
-	return reg.getFieldVal(IOStandbyTerminationMask, IOStandbyTerminationShift)
-}
-
-// getTermination - returns the pad termination state defines the different weak
-// pull-up and pull-down settings that are supported by the buffer
-// 0000 = none; 0010 = 5k PD; 0100 = 20k PD; 1010 = 5k PU; 1100 = 20k PU;
-// 1111 = Native controller selected
-func (reg *Register) GetTermination() uint8 {
-	return reg.getFieldVal(TermMask, TermShift)
-}
-
-// getInterruptSelect - returns Interrupt Line number from the GPIO controller
-func (reg *Register) GetInterruptSelect() uint8 {
-	return reg.getFieldVal(InterruptSelectMask, 0)
-}
diff --git a/util/intelp2m/platforms/common/register/bits/bits.go b/util/intelp2m/platforms/common/register/bits/bits.go
new file mode 100644
index 0000000000..a156e20147
--- /dev/null
+++ b/util/intelp2m/platforms/common/register/bits/bits.go
@@ -0,0 +1,92 @@
+package bits
+
+type Offset uint8
+
+const All32 uint32 = 0b11111111111111111111111111111111
+
+const (
+	DW0PadRstCfg                Offset = 30
+	DW0RxPadStateSelect         Offset = 29
+	DW0RxRawOverrideTo1         Offset = 28
+	DW0RxLevelEdgeConfiguration Offset = 25
+	DW0RxInvert                 Offset = 23
+	DW0RxTxEnableConfig         Offset = 21
+	DW0InputRouteIOxApic        Offset = 20
+	DW0InputRouteSCI            Offset = 19
+	DW0InputRouteSMI            Offset = 18
+	DW0InputRouteNMI            Offset = 17
+	DW0PadMode                  Offset = 10
+	DW0RxTxBufDisable           Offset = 8
+	DW0RxState                  Offset = 1
+	DW0TxState                  Offset = 0
+)
+
+const (
+	RstCfgPWROK  = 0b00
+	RstCfgDEEP   = 0b01
+	RstCfgPLTRST = 0b10
+	RstCfgRSMRST = 0b11
+)
+
+const (
+	TrigLEVEL       = 0b00
+	TrigEDGE_SINGLE = 0b01
+	TrigOFF         = 0b10
+	TrigEDGE_BOTH   = 0b11
+)
+
+type Fields map[Offset]uint32
+
+var DW0 = Fields{
+	DW0PadRstCfg:                0b11 << DW0PadRstCfg,
+	DW0RxPadStateSelect:         0b1 << DW0RxPadStateSelect,
+	DW0RxRawOverrideTo1:         0b1 << DW0RxRawOverrideTo1,
+	DW0RxLevelEdgeConfiguration: 0b11 << DW0RxLevelEdgeConfiguration,
+	DW0RxInvert:                 0b1 << DW0RxInvert,
+	DW0RxTxEnableConfig:         0b11 << DW0RxTxEnableConfig,
+	DW0InputRouteIOxApic:        0b1 << DW0InputRouteIOxApic,
+	DW0InputRouteSCI:            0b1 << DW0InputRouteSCI,
+	DW0InputRouteSMI:            0b1 << DW0InputRouteSMI,
+	DW0InputRouteNMI:            0b1 << DW0InputRouteNMI,
+	DW0PadMode:                  0b111 << DW0PadMode,
+	DW0RxTxBufDisable:           0b11 << DW0RxTxBufDisable,
+	DW0RxState:                  0b1 << DW0RxState,
+	DW0TxState:                  0b1 << DW0TxState,
+}
+
+const (
+	DW1PadTol               Offset = 25
+	DW1IOStandbyState       Offset = 14
+	DW1Term                 Offset = 10
+	DW1IOStandbyTermination Offset = 8
+	DW1InterruptSelect      Offset = 0
+)
+
+const (
+	IOStateTxLASTRxE     = 0b0000
+	IOStateTx0RxDCRx0    = 0b0001
+	IOStateTx0RxDCRx1    = 0b0010
+	IOStateTx1RxDCRx0    = 0b0011
+	IOStateTx1RxDCRx1    = 0b0100
+	IOStateTx0RxE        = 0b0101
+	IOStateTx1RxE        = 0b0110
+	IOStateHIZCRx0       = 0b0111
+	IOStateHIZCRx1       = 0b1000
+	IOStateTxDRxE        = 0b1001
+	IOStateStandbyIgnore = 0b1111
+)
+
+const (
+	IOTermSAME    = 0b00
+	IOTermDISPUPD = 0b01
+	IOTermENPD    = 0b10
+	IOTermENPU    = 0b11
+)
+
+var DW1 = Fields{
+	DW1PadTol:               0b1 << DW1PadTol,
+	DW1IOStandbyState:       0b1111 << DW1IOStandbyState,
+	DW1Term:                 0b1111 << DW1Term,
+	DW1IOStandbyTermination: 0b11 << DW1IOStandbyTermination,
+	DW1InterruptSelect:      0b11111111 << DW1InterruptSelect,
+}
diff --git a/util/intelp2m/platforms/common/register/dw0.go b/util/intelp2m/platforms/common/register/dw0.go
new file mode 100644
index 0000000000..8cf23841e4
--- /dev/null
+++ b/util/intelp2m/platforms/common/register/dw0.go
@@ -0,0 +1,97 @@
+package register
+
+import "review.coreboot.org/coreboot.git/util/intelp2m/platforms/common/register/bits"
+
+type DW0 struct {
+	Register
+}
+
+// getResetConfig() returns type reset source for corresponding pad
+// PADRSTCFG field in PAD_CFG_DW0 register
+func (dw0 *DW0) GetResetConfig() uint32 {
+	return dw0.GetFieldVal(bits.DW0, bits.DW0PadRstCfg)
+}
+
+// getRXPadStateSelect() returns RX Pad State (RXINV)
+// 0 = Raw RX pad state directly from RX buffer
+// 1 = Internal RX pad state
+func (dw0 *DW0) GetRXPadStateSelect() uint32 {
+	return dw0.GetFieldVal(bits.DW0, bits.DW0RxPadStateSelect)
+}
+
+// getRXRawOverrideStatus() returns 1 if the selected pad state is being
+// overridden to '1' (RXRAW1 field)
+func (dw0 *DW0) GetRXRawOverrideStatus() uint32 {
+	return dw0.GetFieldVal(bits.DW0, bits.DW0RxRawOverrideTo1)
+}
+
+// getRXLevelEdgeConfiguration() returns RX Level/Edge Configuration (RXEVCFG)
+// 0h = Level, 1h = Edge, 2h = Drive '0', 3h = Reserved (implement as setting 0h)
+func (dw0 *DW0) GetRXLevelEdgeConfiguration() uint32 {
+	return dw0.GetFieldVal(bits.DW0, bits.DW0RxLevelEdgeConfiguration)
+}
+
+// GetRxInvert() returns RX Invert state (RXINV)
+// 1 - Inversion, 0 - No inversion
+func (dw0 *DW0) GetRxInvert() uint32 {
+	return dw0.GetFieldVal(bits.DW0, bits.DW0RxInvert)
+}
+
+// getRxTxEnableConfig() returns RX/TX Enable Config (RXTXENCFG)
+// 0 = Function defined in Pad Mode controls TX and RX Enables
+// 1 = Function controls TX Enable and RX Disabled with RX drive 0 internally
+// 2 = Function controls TX Enable and RX Disabled with RX drive 1 internally
+// 3 = Function controls TX Enabled and RX is always enabled
+func (dw0 *DW0) GetRxTxEnableConfig() uint32 {
+	return dw0.GetFieldVal(bits.DW0, bits.DW0RxTxEnableConfig)
+}
+
+// getGPIOInputRouteIOxAPIC() returns 1 if the pad can be routed to cause
+// peripheral IRQ when configured in GPIO input mode.
+func (dw0 *DW0) GetGPIOInputRouteIOxAPIC() uint32 {
+	return dw0.GetFieldVal(bits.DW0, bits.DW0InputRouteIOxApic)
+}
+
+// getGPIOInputRouteSCI() returns 1 if the pad can be routed to cause SCI when
+// configured in GPIO input mode.
+func (dw0 *DW0) GetGPIOInputRouteSCI() uint32 {
+	return dw0.GetFieldVal(bits.DW0, bits.DW0InputRouteSCI)
+}
+
+// getGPIOInputRouteSMI() returns 1 if the pad can be routed to cause SMI when
+// configured in GPIO input mode
+func (dw0 *DW0) GetGPIOInputRouteSMI() uint32 {
+	return dw0.GetFieldVal(bits.DW0, bits.DW0InputRouteSMI)
+}
+
+// getGPIOInputRouteNMI() returns 1 if the pad can be routed to cause NMI when
+// configured in GPIO input mode
+func (dw0 *DW0) GetGPIOInputRouteNMI() uint32 {
+	return dw0.GetFieldVal(bits.DW0, bits.DW0InputRouteNMI)
+}
+
+// getPadMode() reutrns pad mode or one of the native functions
+// 0h = GPIO control the Pad.
+// 1h = native function 1, if applicable, controls the Pad
+// 2h = native function 2, if applicable, controls the Pad
+// 3h = native function 3, if applicable, controls the Pad
+// 4h = enable GPIO blink/PWM capability if applicable
+func (dw0 *DW0) GetPadMode() uint32 {
+	return dw0.GetFieldVal(bits.DW0, bits.DW0PadMode)
+}
+
+// getGPIORxTxDisableStatus() returns GPIO RX/TX buffer state (GPIORXDIS | GPIOTXDIS)
+// 0 - both are enabled, 1 - TX Disable, 2 - RX Disable, 3 - both are disabled
+func (dw0 *DW0) GetGPIORxTxDisableStatus() uint32 {
+	return dw0.GetFieldVal(bits.DW0, bits.DW0RxTxBufDisable)
+}
+
+// getGPIORXState() returns GPIO RX State (GPIORXSTATE)
+func (dw0 *DW0) GetGPIORXState() uint32 {
+	return dw0.GetFieldVal(bits.DW0, bits.DW0RxState)
+}
+
+// getGPIOTXState() returns GPIO TX State (GPIOTXSTATE)
+func (dw0 *DW0) GetGPIOTXState() uint32 {
+	return dw0.GetFieldVal(bits.DW0, 0)
+}
diff --git a/util/intelp2m/platforms/common/register/dw1.go b/util/intelp2m/platforms/common/register/dw1.go
new file mode 100644
index 0000000000..0336562bc6
--- /dev/null
+++ b/util/intelp2m/platforms/common/register/dw1.go
@@ -0,0 +1,51 @@
+package register
+
+import "review.coreboot.org/coreboot.git/util/intelp2m/platforms/common/register/bits"
+
+type DW1 struct {
+	Register
+}
+
+// GetPadTol()
+func (dw1 *DW1) GetPadTol() uint32 {
+	return dw1.GetFieldVal(bits.DW1, bits.DW1PadTol)
+}
+
+// GetIOStandbyState() returns IO Standby State (IOSSTATE)
+// 0 = Tx enabled driving last value driven, Rx enabled
+// 1 = Tx enabled driving 0, Rx disabled and Rx driving 0 back to its controller internally
+// 2 = Tx enabled driving 0, Rx disabled and Rx driving 1 back to its controller internally
+// 3 = Tx enabled driving 1, Rx disabled and Rx driving 0 back to its controller internally
+// 4 = Tx enabled driving 1, Rx disabled and Rx driving 1 back to its controller internally
+// 5 = Tx enabled driving 0, Rx enabled
+// 6 = Tx enabled driving 1, Rx enabled
+// 7 = Hi-Z, Rx driving 0 back to its controller internally
+// 8 = Hi-Z, Rx driving 1 back to its controller internally
+// 9 = Tx disabled, Rx enabled
+// 15 = IO-Standby is ignored for this pin (same as functional mode)
+// Others reserved
+func (dw1 *DW1) GetIOStandbyState() uint32 {
+	return dw1.GetFieldVal(bits.DW1, bits.DW1IOStandbyState)
+}
+
+// GetIOStandbyTermination() returns IO Standby Termination (IOSTERM)
+// 0 = Same as functional mode (no change)
+// 1 = Disable Pull-up and Pull-down (no on-die termination)
+// 2 = Enable Pull-down
+// 3 = Enable Pull-up
+func (dw1 *DW1) GetIOStandbyTermination() uint32 {
+	return dw1.GetFieldVal(bits.DW1, bits.DW1IOStandbyTermination)
+}
+
+// GetTermination() returns the pad termination state defines the different weak
+// pull-up and pull-down settings that are supported by the buffer
+// 0000 = none; 0010 = 5k PD; 0100 = 20k PD; 1010 = 5k PU; 1100 = 20k PU;
+// 1111 = Native controller selected
+func (dw1 *DW1) GetTermination() uint32 {
+	return dw1.GetFieldVal(bits.DW1, bits.DW1Term)
+}
+
+// GetInterruptSelect() returns Interrupt Line number from the GPIO controller
+func (dw1 *DW1) GetInterruptSelect() uint32 {
+	return dw1.GetFieldVal(bits.DW1, bits.DW1InterruptSelect)
+}
diff --git a/util/intelp2m/platforms/common/register/register.go b/util/intelp2m/platforms/common/register/register.go
new file mode 100644
index 0000000000..48cc240092
--- /dev/null
+++ b/util/intelp2m/platforms/common/register/register.go
@@ -0,0 +1,45 @@
+package register
+
+import (
+	"fmt"
+
+	"review.coreboot.org/coreboot.git/util/intelp2m/platforms/common/register/bits"
+)
+
+type Register struct {
+	Value    uint32
+	Mask     uint32
+	ReadOnly uint32
+}
+
+// MaskCheck() checks the mask of the new macro
+// Returns true if the macro is generated correctly
+func (r Register) MaskCheck() bool {
+	mask := ^(r.Mask | r.ReadOnly)
+	return (r.Value & mask) == 0
+}
+
+// GetFieldVal() gets the value of the register bit field
+func (r *Register) GetFieldVal(bitfields bits.Fields, offset bits.Offset) uint32 {
+	mask := bitfields[offset]
+	r.Mask |= mask
+	return (r.Value & mask) >> offset
+}
+
+// CntrMaskFieldsClear() clears filed in control mask
+// fieldMask : bitfields mask to be cleared
+func (r *Register) CntrMaskFieldsClear(fieldMask uint32) {
+	r.Mask &= ^fieldMask
+}
+
+// IgnoredFieldsGet() returns mask of unchecked (ignored) fields.
+// These bit fields were not read when the macro was generated.
+// return : mask of ignored bit field
+func (r Register) IgnoredFieldsGet() uint32 {
+	mask := r.Mask | r.ReadOnly
+	return r.Value & ^mask
+}
+
+func (r Register) String() string {
+	return fmt.Sprintf("0x%0.8x", r.Value)
+}
diff --git a/util/intelp2m/platforms/ebg/ebg_test.go b/util/intelp2m/platforms/ebg/ebg_test.go
index bed3cb65f6..13e977a063 100644
--- a/util/intelp2m/platforms/ebg/ebg_test.go
+++ b/util/intelp2m/platforms/ebg/ebg_test.go
@@ -51,7 +51,7 @@ func TestGenMacro(t *testing.T) {
 			Pad: test.Pad{ID: "GPP_E5", DW0: 0xEEEEEEEE, DW1: 0xEEEEEEEE, Ownership: 1},
 			Macro: test.Macro{
 				Short: "PAD_CFG_NF_1V8(GPP_E5, UP_2K, RSMRST, NF3),",
-				Long:  "_PAD_CFG_STRUCT(GPP_E5, PAD_FUNC(NF3) | PAD_RESET(RSMRST) | PAD_TRIG(EDGE_BOTH) | PAD_IRQ_ROUTE(SCI) | PAD_IRQ_ROUTE(SMI) | PAD_IRQ_ROUTE(NMI) | PAD_RX_POL(INVERT) | PAD_BUF(RX_DISABLE) | (1 << 29) | (1 << 1), PAD_CFG1_TOL_1V8PAD_PULL(UP_2K) | PAD_IOSSTATE(IGNORE) | PAD_IOSTERM(ENPD) | PAD_CFG_OWN_GPIO(DRIVER)),",
+				Long:  "_PAD_CFG_STRUCT(GPP_E5, PAD_FUNC(NF3) | PAD_RESET(RSMRST) | PAD_TRIG(EDGE_BOTH) | PAD_IRQ_ROUTE(SCI) | PAD_IRQ_ROUTE(SMI) | PAD_IRQ_ROUTE(NMI) | PAD_RX_POL(INVERT) | PAD_BUF(RX_DISABLE) | (1 << 29) | (1 << 1), PAD_CFG1_TOL_1V8PAD_PULL(UP_2K) | PAD_IOSSTATE(ERROR) | PAD_IOSTERM(ENPD) | PAD_CFG_OWN_GPIO(DRIVER)),",
 			},
 		},
 		{
@@ -65,14 +65,14 @@ func TestGenMacro(t *testing.T) {
 			Pad: test.Pad{ID: "GPP_J7", DW0: 0xBBBBBBBB, DW1: 0xBBBBBBBB, Ownership: 1},
 			Macro: test.Macro{
 				Short: "PAD_CFG_NF_1V8(GPP_J7, INVALID, PLTRST, NF6),",
-				Long:  "_PAD_CFG_STRUCT(GPP_J7, PAD_FUNC(NF6) | PAD_RESET(PLTRST) | PAD_TRIG(EDGE_SINGLE) | PAD_IRQ_ROUTE(IOAPIC) | PAD_IRQ_ROUTE(SCI) | PAD_IRQ_ROUTE(NMI) | PAD_RX_POL(INVERT) | PAD_BUF(TX_RX_DISABLE) | (1 << 29) | (1 << 28) | (1 << 1) | 1, PAD_CFG1_TOL_1V8PAD_PULL(INVALID) | PAD_IOSSTATE(IGNORE) | PAD_IOSTERM(ENPU) | PAD_CFG_OWN_GPIO(DRIVER)),",
+				Long:  "_PAD_CFG_STRUCT(GPP_J7, PAD_FUNC(NF6) | PAD_RESET(PLTRST) | PAD_TRIG(EDGE_SINGLE) | PAD_IRQ_ROUTE(IOAPIC) | PAD_IRQ_ROUTE(SCI) | PAD_IRQ_ROUTE(NMI) | PAD_RX_POL(INVERT) | PAD_BUF(TX_RX_DISABLE) | (1 << 29) | (1 << 28) | (1 << 1) | 1, PAD_CFG1_TOL_1V8PAD_PULL(INVALID) | PAD_IOSSTATE(ERROR) | PAD_IOSTERM(ENPU) | PAD_CFG_OWN_GPIO(DRIVER)),",
 			},
 		},
 		{
 			Pad: test.Pad{ID: "GPP_I8", DW0: 0x77777777, DW1: 0x77777777, Ownership: 0},
 			Macro: test.Macro{
 				Short: "PAD_CFG_NF_1V8(GPP_I8, UP_667, DEEP, NF5),",
-				Long:  "_PAD_CFG_STRUCT(GPP_I8, PAD_FUNC(NF5) | PAD_RESET(DEEP) | PAD_TRIG(EDGE_BOTH) | PAD_IRQ_ROUTE(IOAPIC) | PAD_IRQ_ROUTE(SMI) | PAD_IRQ_ROUTE(NMI) | PAD_BUF(TX_RX_DISABLE) | (1 << 29) | (1 << 28) | (1 << 1) | 1, PAD_CFG1_TOL_1V8PAD_PULL(UP_667) | PAD_IOSSTATE(IGNORE) | PAD_IOSTERM(ENPU)),",
+				Long:  "_PAD_CFG_STRUCT(GPP_I8, PAD_FUNC(NF5) | PAD_RESET(DEEP) | PAD_TRIG(EDGE_BOTH) | PAD_IRQ_ROUTE(IOAPIC) | PAD_IRQ_ROUTE(SMI) | PAD_IRQ_ROUTE(NMI) | PAD_BUF(TX_RX_DISABLE) | (1 << 29) | (1 << 28) | (1 << 1) | 1, PAD_CFG1_TOL_1V8PAD_PULL(UP_667) | PAD_IOSSTATE(ERROR) | PAD_IOSTERM(ENPU)),",
 			},
 		},
 	}.Run(t, "INTEL-EMMITSBURG-PCH/SLIDING-ZERO-IN-NIBBLE-TEST", emmitsburg)
@@ -82,7 +82,7 @@ func TestGenMacro(t *testing.T) {
 			Pad: test.Pad{ID: "GPP_L9", DW0: 0x33333333, DW1: 0x33333333, Ownership: 1},
 			Macro: test.Macro{
 				Short: "PAD_CFG_NF_1V8(GPP_L9, UP_20K, RSMRST, NF4),",
-				Long:  "_PAD_CFG_STRUCT(GPP_L9, PAD_FUNC(NF4) | PAD_RESET(RSMRST) | PAD_TRIG(EDGE_SINGLE) | PAD_IRQ_ROUTE(IOAPIC) | PAD_IRQ_ROUTE(NMI) | PAD_BUF(TX_RX_DISABLE) | (1 << 29) | (1 << 28) | (1 << 1) | 1, PAD_CFG1_TOL_1V8PAD_PULL(UP_20K) | PAD_IOSSTATE(IGNORE) | PAD_IOSTERM(ENPU) | PAD_CFG_OWN_GPIO(DRIVER)),",
+				Long:  "_PAD_CFG_STRUCT(GPP_L9, PAD_FUNC(NF4) | PAD_RESET(RSMRST) | PAD_TRIG(EDGE_SINGLE) | PAD_IRQ_ROUTE(IOAPIC) | PAD_IRQ_ROUTE(NMI) | PAD_BUF(TX_RX_DISABLE) | (1 << 29) | (1 << 28) | (1 << 1) | 1, PAD_CFG1_TOL_1V8PAD_PULL(UP_20K) | PAD_IOSSTATE(ERROR) | PAD_IOSTERM(ENPU) | PAD_CFG_OWN_GPIO(DRIVER)),",
 			},
 		},
 		{
diff --git a/util/intelp2m/platforms/ebg/macro.go b/util/intelp2m/platforms/ebg/macro.go
index 1fb0a3273a..9dba566907 100644
--- a/util/intelp2m/platforms/ebg/macro.go
+++ b/util/intelp2m/platforms/ebg/macro.go
@@ -6,6 +6,7 @@ import (
 	"review.coreboot.org/coreboot.git/util/intelp2m/fields"
 	"review.coreboot.org/coreboot.git/util/intelp2m/platforms/cnl"
 	"review.coreboot.org/coreboot.git/util/intelp2m/platforms/common"
+	"review.coreboot.org/coreboot.git/util/intelp2m/platforms/common/register/bits"
 	"review.coreboot.org/coreboot.git/util/intelp2m/platforms/snr"
 )
 
@@ -14,12 +15,6 @@ const (
 	PAD_CFG_DW1_RO_FIELDS = 0xfdffc3ff
 )
 
-const (
-	PAD_CFG_DW0 = common.PAD_CFG_DW0
-	PAD_CFG_DW1 = common.PAD_CFG_DW1
-	MAX_DW_NUM  = common.MAX_DW_NUM
-)
-
 type InheritanceMacro interface {
 	Pull()
 	GpiMacroAdd()
@@ -36,21 +31,22 @@ type PlatformSpecific struct {
 // RemmapRstSrc - remmap Pad Reset Source Config
 func (PlatformSpecific) RemmapRstSrc() {
 	macro := common.GetMacro()
-	dw0 := macro.Register(PAD_CFG_DW0)
-	var remapping = map[uint8]uint32{
-		0: common.RST_RSMRST << common.PadRstCfgShift,
-		1: common.RST_DEEP << common.PadRstCfgShift,
-		2: common.RST_PLTRST << common.PadRstCfgShift,
+	dw0 := macro.GetRegisterDW0()
+	var remapping = map[uint32]uint32{
+		0: bits.RstCfgRSMRST << bits.DW0PadRstCfg,
+		1: bits.RstCfgDEEP << bits.DW0PadRstCfg,
+		2: bits.RstCfgPLTRST << bits.DW0PadRstCfg,
 	}
 	resetsrc, valid := remapping[dw0.GetResetConfig()]
 	if valid {
 		// dw0.SetResetConfig(resetsrc)
-		ResetConfigFieldVal := (dw0.ValueGet() & 0x3fffffff) | remapping[dw0.GetResetConfig()]
-		dw0.ValueSet(ResetConfigFieldVal)
+		ResetConfigFieldVal := (dw0.Value & 0x3fffffff) | remapping[dw0.GetResetConfig()]
+		dw0.Value = ResetConfigFieldVal
 	} else {
 		fmt.Println("Invalid Pad Reset Config [ 0x", resetsrc, " ] for ", macro.PadIdGet())
 	}
-	dw0.CntrMaskFieldsClear(common.PadRstCfgMask)
+	mask := bits.DW0[bits.DW0PadRstCfg]
+	dw0.CntrMaskFieldsClear(mask)
 }
 
 // Adds The Pad Termination (TERM) parameter from PAD_CFG_DW1 to the macro
@@ -83,9 +79,7 @@ func (platform PlatformSpecific) NoConnMacroAdd() {
 // dw0 : DW0 config register value
 // dw1 : DW1 config register value
 // return: string of macro
-//
-//	error
-func (platform PlatformSpecific) GenMacro(id string, dw0 uint32, dw1 uint32, ownership uint8) string {
+func (platform PlatformSpecific) GenMacro(id string, dw0Val, dw1Val uint32, ownership uint8) string {
 	macro := common.GetInstanceMacro(
 		PlatformSpecific{
 			InheritanceMacro: cnl.PlatformSpecific{
@@ -95,10 +89,18 @@ func (platform PlatformSpecific) GenMacro(id string, dw0 uint32, dw1 uint32, own
 		fields.InterfaceGet(),
 	)
 	macro.Clear()
-	macro.Register(PAD_CFG_DW0).CntrMaskFieldsClear(common.AllFields)
-	macro.Register(PAD_CFG_DW1).CntrMaskFieldsClear(common.AllFields)
+
+	dw0 := macro.GetRegisterDW0()
+	dw0.CntrMaskFieldsClear(bits.All32)
+
+	dw1 := macro.GetRegisterDW1()
+	dw1.CntrMaskFieldsClear(bits.All32)
+
+	dw0.Value = dw0Val
+	dw1.Value = dw1Val
+	dw0.ReadOnly = PAD_CFG_DW0_RO_FIELDS
+	dw1.ReadOnly = PAD_CFG_DW1_RO_FIELDS
+
 	macro.PadIdSet(id).SetPadOwnership(ownership)
-	macro.Register(PAD_CFG_DW0).ValueSet(dw0).ReadOnlyFieldsSet(PAD_CFG_DW0_RO_FIELDS)
-	macro.Register(PAD_CFG_DW1).ValueSet(dw1).ReadOnlyFieldsSet(PAD_CFG_DW1_RO_FIELDS)
 	return macro.Generate()
 }
diff --git a/util/intelp2m/platforms/jsl/jsl_test.go b/util/intelp2m/platforms/jsl/jsl_test.go
index d090ea79c3..143617fb9a 100644
--- a/util/intelp2m/platforms/jsl/jsl_test.go
+++ b/util/intelp2m/platforms/jsl/jsl_test.go
@@ -51,7 +51,7 @@ func TestGenMacro(t *testing.T) {
 			Pad: test.Pad{ID: "GPP_E5", DW0: 0xEEEEEEEE, DW1: 0xEEEEEEEE, Ownership: 1},
 			Macro: test.Macro{
 				Short: "PAD_CFG_NF_1V8(GPP_E5, UP_2K, RSMRST, NF3),",
-				Long:  "_PAD_CFG_STRUCT(GPP_E5, PAD_FUNC(NF3) | PAD_RESET(RSMRST) | PAD_TRIG(EDGE_BOTH) | PAD_IRQ_ROUTE(SCI) | PAD_IRQ_ROUTE(SMI) | PAD_IRQ_ROUTE(NMI) | PAD_RX_POL(INVERT) | PAD_BUF(RX_DISABLE) | (1 << 29) | (1 << 1), PAD_CFG1_TOL_1V8PAD_PULL(UP_2K) | PAD_IOSSTATE(IGNORE) | PAD_IOSTERM(ENPD) | PAD_CFG_OWN_GPIO(DRIVER)),",
+				Long:  "_PAD_CFG_STRUCT(GPP_E5, PAD_FUNC(NF3) | PAD_RESET(RSMRST) | PAD_TRIG(EDGE_BOTH) | PAD_IRQ_ROUTE(SCI) | PAD_IRQ_ROUTE(SMI) | PAD_IRQ_ROUTE(NMI) | PAD_RX_POL(INVERT) | PAD_BUF(RX_DISABLE) | (1 << 29) | (1 << 1), PAD_CFG1_TOL_1V8PAD_PULL(UP_2K) | PAD_IOSSTATE(ERROR) | PAD_IOSTERM(ENPD) | PAD_CFG_OWN_GPIO(DRIVER)),",
 			},
 		},
 		{
@@ -65,14 +65,14 @@ func TestGenMacro(t *testing.T) {
 			Pad: test.Pad{ID: "GPP_G7", DW0: 0xBBBBBBBB, DW1: 0xBBBBBBBB, Ownership: 1},
 			Macro: test.Macro{
 				Short: "PAD_CFG_NF_1V8(GPP_G7, INVALID, PLTRST, NF6),",
-				Long:  "_PAD_CFG_STRUCT(GPP_G7, PAD_FUNC(NF6) | PAD_RESET(PLTRST) | PAD_TRIG(EDGE_SINGLE) | PAD_IRQ_ROUTE(IOAPIC) | PAD_IRQ_ROUTE(SCI) | PAD_IRQ_ROUTE(NMI) | PAD_RX_POL(INVERT) | PAD_BUF(TX_RX_DISABLE) | (1 << 29) | (1 << 28) | (1 << 1) | 1, PAD_CFG1_TOL_1V8PAD_PULL(INVALID) | PAD_IOSSTATE(IGNORE) | PAD_IOSTERM(ENPU) | PAD_CFG_OWN_GPIO(DRIVER)),",
+				Long:  "_PAD_CFG_STRUCT(GPP_G7, PAD_FUNC(NF6) | PAD_RESET(PLTRST) | PAD_TRIG(EDGE_SINGLE) | PAD_IRQ_ROUTE(IOAPIC) | PAD_IRQ_ROUTE(SCI) | PAD_IRQ_ROUTE(NMI) | PAD_RX_POL(INVERT) | PAD_BUF(TX_RX_DISABLE) | (1 << 29) | (1 << 28) | (1 << 1) | 1, PAD_CFG1_TOL_1V8PAD_PULL(INVALID) | PAD_IOSSTATE(ERROR) | PAD_IOSTERM(ENPU) | PAD_CFG_OWN_GPIO(DRIVER)),",
 			},
 		},
 		{
 			Pad: test.Pad{ID: "GPP_H8", DW0: 0x77777777, DW1: 0x77777777, Ownership: 0},
 			Macro: test.Macro{
 				Short: "PAD_CFG_NF_1V8(GPP_H8, UP_667, DEEP, NF5),",
-				Long:  "_PAD_CFG_STRUCT(GPP_H8, PAD_FUNC(NF5) | PAD_RESET(DEEP) | PAD_TRIG(EDGE_BOTH) | PAD_IRQ_ROUTE(IOAPIC) | PAD_IRQ_ROUTE(SMI) | PAD_IRQ_ROUTE(NMI) | PAD_BUF(TX_RX_DISABLE) | (1 << 29) | (1 << 28) | (1 << 1) | 1, PAD_CFG1_TOL_1V8PAD_PULL(UP_667) | PAD_IOSSTATE(IGNORE) | PAD_IOSTERM(ENPU)),",
+				Long:  "_PAD_CFG_STRUCT(GPP_H8, PAD_FUNC(NF5) | PAD_RESET(DEEP) | PAD_TRIG(EDGE_BOTH) | PAD_IRQ_ROUTE(IOAPIC) | PAD_IRQ_ROUTE(SMI) | PAD_IRQ_ROUTE(NMI) | PAD_BUF(TX_RX_DISABLE) | (1 << 29) | (1 << 28) | (1 << 1) | 1, PAD_CFG1_TOL_1V8PAD_PULL(UP_667) | PAD_IOSSTATE(ERROR) | PAD_IOSTERM(ENPU)),",
 			},
 		},
 	}.Run(t, "INTEL-JASPER-LAKE-PCH/SLIDING-ZERO-IN-NIBBLE-TEST", jasperlake)
@@ -82,7 +82,7 @@ func TestGenMacro(t *testing.T) {
 			Pad: test.Pad{ID: "GPP_R9", DW0: 0x33333333, DW1: 0x33333333, Ownership: 1},
 			Macro: test.Macro{
 				Short: "PAD_CFG_NF_1V8(GPP_R9, UP_20K, PWROK, NF4),",
-				Long:  "_PAD_CFG_STRUCT(GPP_R9, PAD_FUNC(NF4) | PAD_TRIG(EDGE_SINGLE) | PAD_IRQ_ROUTE(IOAPIC) | PAD_IRQ_ROUTE(NMI) | PAD_BUF(TX_RX_DISABLE) | (1 << 29) | (1 << 28) | (1 << 1) | 1, PAD_CFG1_TOL_1V8PAD_PULL(UP_20K) | PAD_IOSSTATE(IGNORE) | PAD_IOSTERM(ENPU) | PAD_CFG_OWN_GPIO(DRIVER)),",
+				Long:  "_PAD_CFG_STRUCT(GPP_R9, PAD_FUNC(NF4) | PAD_TRIG(EDGE_SINGLE) | PAD_IRQ_ROUTE(IOAPIC) | PAD_IRQ_ROUTE(NMI) | PAD_BUF(TX_RX_DISABLE) | (1 << 29) | (1 << 28) | (1 << 1) | 1, PAD_CFG1_TOL_1V8PAD_PULL(UP_20K) | PAD_IOSSTATE(ERROR) | PAD_IOSTERM(ENPU) | PAD_CFG_OWN_GPIO(DRIVER)),",
 			},
 		},
 		{
diff --git a/util/intelp2m/platforms/jsl/macro.go b/util/intelp2m/platforms/jsl/macro.go
index 42c254b190..d21eda151a 100644
--- a/util/intelp2m/platforms/jsl/macro.go
+++ b/util/intelp2m/platforms/jsl/macro.go
@@ -7,6 +7,7 @@ import (
 	"review.coreboot.org/coreboot.git/util/intelp2m/fields"
 	"review.coreboot.org/coreboot.git/util/intelp2m/platforms/cnl"
 	"review.coreboot.org/coreboot.git/util/intelp2m/platforms/common"
+	"review.coreboot.org/coreboot.git/util/intelp2m/platforms/common/register/bits"
 	"review.coreboot.org/coreboot.git/util/intelp2m/platforms/snr"
 )
 
@@ -15,12 +16,6 @@ const (
 	PAD_CFG_DW1_RO_FIELDS = 0xdfffc3ff
 )
 
-const (
-	PAD_CFG_DW0 = common.PAD_CFG_DW0
-	PAD_CFG_DW1 = common.PAD_CFG_DW1
-	MAX_DW_NUM  = common.MAX_DW_NUM
-)
-
 type InheritanceMacro interface {
 	Pull()
 	GpiMacroAdd()
@@ -47,21 +42,22 @@ func (PlatformSpecific) RemmapRstSrc() {
 		return
 	}
 
-	dw0 := macro.Register(PAD_CFG_DW0)
-	var remapping = map[uint8]uint32{
-		0: common.RST_RSMRST << common.PadRstCfgShift,
-		1: common.RST_DEEP << common.PadRstCfgShift,
-		2: common.RST_PLTRST << common.PadRstCfgShift,
+	dw0 := macro.GetRegisterDW0()
+	var remapping = map[uint32]uint32{
+		0: bits.RstCfgRSMRST << bits.DW0PadRstCfg,
+		1: bits.RstCfgDEEP << bits.DW0PadRstCfg,
+		2: bits.RstCfgPLTRST << bits.DW0PadRstCfg,
 	}
 	resetsrc, valid := remapping[dw0.GetResetConfig()]
 	if valid {
 		// dw0.SetResetConfig(resetsrc)
-		ResetConfigFieldVal := (dw0.ValueGet() & 0x3fffffff) | remapping[dw0.GetResetConfig()]
-		dw0.ValueSet(ResetConfigFieldVal)
+		ResetConfigFieldVal := (dw0.Value & 0x3fffffff) | remapping[dw0.GetResetConfig()]
+		dw0.Value = ResetConfigFieldVal
 	} else {
 		fmt.Println("Invalid Pad Reset Config [ 0x", resetsrc, " ] for ", macro.PadIdGet())
 	}
-	dw0.CntrMaskFieldsClear(common.PadRstCfgMask)
+	mask := bits.DW0[bits.DW0PadRstCfg]
+	dw0.CntrMaskFieldsClear(mask)
 }
 
 // Adds The Pad Termination (TERM) parameter from PAD_CFG_DW1 to the macro
@@ -94,9 +90,7 @@ func (platform PlatformSpecific) NoConnMacroAdd() {
 // dw0 : DW0 config register value
 // dw1 : DW1 config register value
 // return: string of macro
-//
-//	error
-func (PlatformSpecific) GenMacro(id string, dw0 uint32, dw1 uint32, ownership uint8) string {
+func (PlatformSpecific) GenMacro(id string, dw0Val, dw1Val uint32, ownership uint8) string {
 	macro := common.GetInstanceMacro(
 		PlatformSpecific{
 			InheritanceMacro: cnl.PlatformSpecific{
@@ -106,10 +100,19 @@ func (PlatformSpecific) GenMacro(id string, dw0 uint32, dw1 uint32, ownership ui
 		fields.InterfaceGet(),
 	)
 	macro.Clear()
-	macro.Register(PAD_CFG_DW0).CntrMaskFieldsClear(common.AllFields)
-	macro.Register(PAD_CFG_DW1).CntrMaskFieldsClear(common.AllFields)
+
+	macro.Clear()
+	dw0 := macro.GetRegisterDW0()
+	dw0.CntrMaskFieldsClear(bits.All32)
+
+	dw1 := macro.GetRegisterDW1()
+	dw1.CntrMaskFieldsClear(bits.All32)
+
+	dw0.Value = dw0Val
+	dw1.Value = dw1Val
+	dw0.ReadOnly = PAD_CFG_DW0_RO_FIELDS
+	dw1.ReadOnly = PAD_CFG_DW1_RO_FIELDS
+
 	macro.PadIdSet(id).SetPadOwnership(ownership)
-	macro.Register(PAD_CFG_DW0).ValueSet(dw0).ReadOnlyFieldsSet(PAD_CFG_DW0_RO_FIELDS)
-	macro.Register(PAD_CFG_DW1).ValueSet(dw1).ReadOnlyFieldsSet(PAD_CFG_DW1_RO_FIELDS)
 	return macro.Generate()
 }
diff --git a/util/intelp2m/platforms/lbg/macro.go b/util/intelp2m/platforms/lbg/macro.go
index 8a706e3d5d..9cbd4f0570 100644
--- a/util/intelp2m/platforms/lbg/macro.go
+++ b/util/intelp2m/platforms/lbg/macro.go
@@ -5,6 +5,7 @@ import (
 
 	"review.coreboot.org/coreboot.git/util/intelp2m/fields"
 	"review.coreboot.org/coreboot.git/util/intelp2m/platforms/common"
+	"review.coreboot.org/coreboot.git/util/intelp2m/platforms/common/register/bits"
 	"review.coreboot.org/coreboot.git/util/intelp2m/platforms/snr"
 )
 
@@ -13,12 +14,6 @@ const (
 	PAD_CFG_DW1_RO_FIELDS = 0xfdffc3ff
 )
 
-const (
-	PAD_CFG_DW0 = common.PAD_CFG_DW0
-	PAD_CFG_DW1 = common.PAD_CFG_DW1
-	MAX_DW_NUM  = common.MAX_DW_NUM
-)
-
 type InheritanceMacro interface {
 	Pull()
 	GpiMacroAdd()
@@ -35,21 +30,22 @@ type PlatformSpecific struct {
 // RemmapRstSrc - remmap Pad Reset Source Config
 func (PlatformSpecific) RemmapRstSrc() {
 	macro := common.GetMacro()
-	dw0 := macro.Register(PAD_CFG_DW0)
-	var remapping = map[uint8]uint32{
-		0: common.RST_RSMRST << common.PadRstCfgShift,
-		1: common.RST_DEEP << common.PadRstCfgShift,
-		2: common.RST_PLTRST << common.PadRstCfgShift,
+	dw0 := macro.GetRegisterDW0()
+	remapping := map[uint32]uint32{
+		0: (bits.RstCfgRSMRST << bits.DW0PadRstCfg),
+		1: (bits.RstCfgDEEP << bits.DW0PadRstCfg),
+		2: (bits.RstCfgPLTRST << bits.DW0PadRstCfg),
 	}
 	resetsrc, valid := remapping[dw0.GetResetConfig()]
 	if valid {
 		// dw0.SetResetConfig(resetsrc)
-		ResetConfigFieldVal := (dw0.ValueGet() & 0x3fffffff) | remapping[dw0.GetResetConfig()]
-		dw0.ValueSet(ResetConfigFieldVal)
+		ResetConfigFieldVal := (dw0.Value & 0x3fffffff) | remapping[dw0.GetResetConfig()]
+		dw0.Value = ResetConfigFieldVal
 	} else {
 		fmt.Println("Invalid Pad Reset Config [ 0x", resetsrc, " ] for ", macro.PadIdGet())
 	}
-	dw0.CntrMaskFieldsClear(common.PadRstCfgMask)
+	mask := bits.DW0[bits.DW0PadRstCfg]
+	dw0.CntrMaskFieldsClear(mask)
 }
 
 // Adds The Pad Termination (TERM) parameter from PAD_CFG_DW1 to the macro
@@ -79,20 +75,31 @@ func (platform PlatformSpecific) NoConnMacroAdd() {
 }
 
 // GenMacro - generate pad macro
-// dw0 : DW0 config register value
-// dw1 : DW1 config register value
+// dw0val : DW0 config register value
+// dw1val : DW1 config register value
 // return: string of macro
-//         error
-func (platform PlatformSpecific) GenMacro(id string, dw0 uint32, dw1 uint32, ownership uint8) string {
+func (platform PlatformSpecific) GenMacro(id string, dw0Val uint32, dw1Val uint32, ownership uint8) string {
 	// The GPIO controller architecture in Lewisburg and Sunrise are very similar,
 	// so we will inherit some platform-dependent functions from Sunrise.
-	macro := common.GetInstanceMacro(PlatformSpecific{InheritanceMacro: snr.PlatformSpecific{}},
-		fields.InterfaceGet())
+	macro := common.GetInstanceMacro(
+		PlatformSpecific{
+			InheritanceMacro: snr.PlatformSpecific{},
+		},
+		fields.InterfaceGet(),
+	)
 	macro.Clear()
-	macro.Register(PAD_CFG_DW0).CntrMaskFieldsClear(common.AllFields)
-	macro.Register(PAD_CFG_DW1).CntrMaskFieldsClear(common.AllFields)
+
+	dw0 := macro.GetRegisterDW0()
+	dw0.CntrMaskFieldsClear(bits.All32)
+
+	dw1 := macro.GetRegisterDW1()
+	dw1.CntrMaskFieldsClear(bits.All32)
+
+	dw0.Value = dw0Val
+	dw1.Value = dw1Val
+	dw0.ReadOnly = PAD_CFG_DW0_RO_FIELDS
+	dw1.ReadOnly = PAD_CFG_DW1_RO_FIELDS
+
 	macro.PadIdSet(id).SetPadOwnership(ownership)
-	macro.Register(PAD_CFG_DW0).ValueSet(dw0).ReadOnlyFieldsSet(PAD_CFG_DW0_RO_FIELDS)
-	macro.Register(PAD_CFG_DW1).ValueSet(dw1).ReadOnlyFieldsSet(PAD_CFG_DW1_RO_FIELDS)
 	return macro.Generate()
 }
diff --git a/util/intelp2m/platforms/mtl/macro.go b/util/intelp2m/platforms/mtl/macro.go
index 06d05996c3..d672752b5b 100644
--- a/util/intelp2m/platforms/mtl/macro.go
+++ b/util/intelp2m/platforms/mtl/macro.go
@@ -7,6 +7,7 @@ import (
 	"review.coreboot.org/coreboot.git/util/intelp2m/fields"
 	"review.coreboot.org/coreboot.git/util/intelp2m/platforms/cnl"
 	"review.coreboot.org/coreboot.git/util/intelp2m/platforms/common"
+	"review.coreboot.org/coreboot.git/util/intelp2m/platforms/common/register/bits"
 	"review.coreboot.org/coreboot.git/util/intelp2m/platforms/snr"
 )
 
@@ -15,12 +16,6 @@ const (
 	PAD_CFG_DW1_RO_FIELDS = 0xfdffc3ff
 )
 
-const (
-	PAD_CFG_DW0 = common.PAD_CFG_DW0
-	PAD_CFG_DW1 = common.PAD_CFG_DW1
-	MAX_DW_NUM  = common.MAX_DW_NUM
-)
-
 type InheritanceMacro interface {
 	Pull()
 	GpiMacroAdd()
@@ -43,22 +38,23 @@ func (PlatformSpecific) RemmapRstSrc() {
 		return
 	}
 
-	dw0 := macro.Register(PAD_CFG_DW0)
-	var remapping = map[uint8]uint32{
-		0: common.RST_RSMRST << common.PadRstCfgShift,
-		1: common.RST_DEEP << common.PadRstCfgShift,
-		2: common.RST_PLTRST << common.PadRstCfgShift,
-		3: common.RST_PWROK << common.PadRstCfgShift,
+	dw0 := macro.GetRegisterDW0()
+	var remapping = map[uint32]uint32{
+		0: bits.RstCfgRSMRST << bits.DW0PadRstCfg,
+		1: bits.RstCfgDEEP << bits.DW0PadRstCfg,
+		2: bits.RstCfgPLTRST << bits.DW0PadRstCfg,
+		3: bits.RstCfgPWROK << bits.RstCfgPWROK,
 	}
 	resetsrc, valid := remapping[dw0.GetResetConfig()]
 	if valid {
 		// dw0.SetResetConfig(resetsrc)
-		ResetConfigFieldVal := (dw0.ValueGet() & 0x3fffffff) | remapping[dw0.GetResetConfig()]
-		dw0.ValueSet(ResetConfigFieldVal)
+		ResetConfigFieldVal := (dw0.Value & 0x3fffffff) | remapping[dw0.GetResetConfig()]
+		dw0.Value = ResetConfigFieldVal
 	} else {
 		fmt.Println("Invalid Pad Reset Config [ 0x", resetsrc, " ] for ", macro.PadIdGet())
 	}
-	dw0.CntrMaskFieldsClear(common.PadRstCfgMask)
+	mask := bits.DW0[bits.DW0PadRstCfg]
+	dw0.CntrMaskFieldsClear(mask)
 }
 
 // Adds The Pad Termination (TERM) parameter from PAD_CFG_DW1 to the macro
@@ -91,9 +87,7 @@ func (platform PlatformSpecific) NoConnMacroAdd() {
 // dw0 : DW0 config register value
 // dw1 : DW1 config register value
 // return: string of macro
-//
-//	error
-func (PlatformSpecific) GenMacro(id string, dw0 uint32, dw1 uint32, ownership uint8) string {
+func (PlatformSpecific) GenMacro(id string, dw0Val, dw1Val uint32, ownership uint8) string {
 	macro := common.GetInstanceMacro(
 		PlatformSpecific{
 			InheritanceMacro: cnl.PlatformSpecific{
@@ -103,10 +97,18 @@ func (PlatformSpecific) GenMacro(id string, dw0 uint32, dw1 uint32, ownership ui
 		fields.InterfaceGet(),
 	)
 	macro.Clear()
-	macro.Register(PAD_CFG_DW0).CntrMaskFieldsClear(common.AllFields)
-	macro.Register(PAD_CFG_DW1).CntrMaskFieldsClear(common.AllFields)
+
+	dw0 := macro.GetRegisterDW0()
+	dw0.CntrMaskFieldsClear(bits.All32)
+
+	dw1 := macro.GetRegisterDW1()
+	dw1.CntrMaskFieldsClear(bits.All32)
+
+	dw0.Value = dw0Val
+	dw1.Value = dw1Val
+	dw0.ReadOnly = PAD_CFG_DW0_RO_FIELDS
+	dw1.ReadOnly = PAD_CFG_DW1_RO_FIELDS
+
 	macro.PadIdSet(id).SetPadOwnership(ownership)
-	macro.Register(PAD_CFG_DW0).ValueSet(dw0).ReadOnlyFieldsSet(PAD_CFG_DW0_RO_FIELDS)
-	macro.Register(PAD_CFG_DW1).ValueSet(dw1).ReadOnlyFieldsSet(PAD_CFG_DW1_RO_FIELDS)
 	return macro.Generate()
 }
diff --git a/util/intelp2m/platforms/mtl/mtl_test.go b/util/intelp2m/platforms/mtl/mtl_test.go
index 07bb99b191..11f8727883 100644
--- a/util/intelp2m/platforms/mtl/mtl_test.go
+++ b/util/intelp2m/platforms/mtl/mtl_test.go
@@ -51,7 +51,7 @@ func TestGenMacro(t *testing.T) {
 			Pad: test.Pad{ID: "GPP_H5", DW0: 0xEEEEEEEE, DW1: 0xEEEEEEEE, Ownership: 1},
 			Macro: test.Macro{
 				Short: "PAD_CFG_NF_1V8(GPP_H5, UP_2K, PWROK, NF3),",
-				Long:  "_PAD_CFG_STRUCT(GPP_H5, PAD_FUNC(NF3) | PAD_TRIG(EDGE_BOTH) | PAD_IRQ_ROUTE(SCI) | PAD_IRQ_ROUTE(SMI) | PAD_IRQ_ROUTE(NMI) | PAD_RX_POL(INVERT) | PAD_BUF(RX_DISABLE) | (1 << 29) | (1 << 1), PAD_CFG1_TOL_1V8PAD_PULL(UP_2K) | PAD_IOSSTATE(IGNORE) | PAD_IOSTERM(ENPD) | PAD_CFG_OWN_GPIO(DRIVER)),",
+				Long:  "_PAD_CFG_STRUCT(GPP_H5, PAD_FUNC(NF3) | PAD_TRIG(EDGE_BOTH) | PAD_IRQ_ROUTE(SCI) | PAD_IRQ_ROUTE(SMI) | PAD_IRQ_ROUTE(NMI) | PAD_RX_POL(INVERT) | PAD_BUF(RX_DISABLE) | (1 << 29) | (1 << 1), PAD_CFG1_TOL_1V8PAD_PULL(UP_2K) | PAD_IOSSTATE(ERROR) | PAD_IOSTERM(ENPD) | PAD_CFG_OWN_GPIO(DRIVER)),",
 			},
 		},
 		{
@@ -65,14 +65,14 @@ func TestGenMacro(t *testing.T) {
 			Pad: test.Pad{ID: "GPP_S7", DW0: 0xBBBBBBBB, DW1: 0xBBBBBBBB, Ownership: 1},
 			Macro: test.Macro{
 				Short: "PAD_CFG_NF_1V8(GPP_S7, INVALID, PLTRST, NF6),",
-				Long:  "_PAD_CFG_STRUCT(GPP_S7, PAD_FUNC(NF6) | PAD_RESET(PLTRST) | PAD_TRIG(EDGE_SINGLE) | PAD_IRQ_ROUTE(IOAPIC) | PAD_IRQ_ROUTE(SCI) | PAD_IRQ_ROUTE(NMI) | PAD_RX_POL(INVERT) | PAD_BUF(TX_RX_DISABLE) | (1 << 29) | (1 << 28) | (1 << 1) | 1, PAD_CFG1_TOL_1V8PAD_PULL(INVALID) | PAD_IOSSTATE(IGNORE) | PAD_IOSTERM(ENPU) | PAD_CFG_OWN_GPIO(DRIVER)),",
+				Long:  "_PAD_CFG_STRUCT(GPP_S7, PAD_FUNC(NF6) | PAD_RESET(PLTRST) | PAD_TRIG(EDGE_SINGLE) | PAD_IRQ_ROUTE(IOAPIC) | PAD_IRQ_ROUTE(SCI) | PAD_IRQ_ROUTE(NMI) | PAD_RX_POL(INVERT) | PAD_BUF(TX_RX_DISABLE) | (1 << 29) | (1 << 28) | (1 << 1) | 1, PAD_CFG1_TOL_1V8PAD_PULL(INVALID) | PAD_IOSSTATE(ERROR) | PAD_IOSTERM(ENPU) | PAD_CFG_OWN_GPIO(DRIVER)),",
 			},
 		},
 		{
 			Pad: test.Pad{ID: "GPP_B8", DW0: 0x77777777, DW1: 0x77777777, Ownership: 0},
 			Macro: test.Macro{
 				Short: "PAD_CFG_NF_1V8(GPP_B8, UP_667, DEEP, NF5),",
-				Long:  "_PAD_CFG_STRUCT(GPP_B8, PAD_FUNC(NF5) | PAD_RESET(DEEP) | PAD_TRIG(EDGE_BOTH) | PAD_IRQ_ROUTE(IOAPIC) | PAD_IRQ_ROUTE(SMI) | PAD_IRQ_ROUTE(NMI) | PAD_BUF(TX_RX_DISABLE) | (1 << 29) | (1 << 28) | (1 << 1) | 1, PAD_CFG1_TOL_1V8PAD_PULL(UP_667) | PAD_IOSSTATE(IGNORE) | PAD_IOSTERM(ENPU)),",
+				Long:  "_PAD_CFG_STRUCT(GPP_B8, PAD_FUNC(NF5) | PAD_RESET(DEEP) | PAD_TRIG(EDGE_BOTH) | PAD_IRQ_ROUTE(IOAPIC) | PAD_IRQ_ROUTE(SMI) | PAD_IRQ_ROUTE(NMI) | PAD_BUF(TX_RX_DISABLE) | (1 << 29) | (1 << 28) | (1 << 1) | 1, PAD_CFG1_TOL_1V8PAD_PULL(UP_667) | PAD_IOSSTATE(ERROR) | PAD_IOSTERM(ENPU)),",
 			},
 		},
 	}.Run(t, "INTEL-METEOR-LAKE-PCH/SLIDING-ZERO-IN-NIBBLE-TEST", meteorlake)
@@ -82,7 +82,7 @@ func TestGenMacro(t *testing.T) {
 			Pad: test.Pad{ID: "GPP_D9", DW0: 0x33333333, DW1: 0x33333333, Ownership: 1},
 			Macro: test.Macro{
 				Short: "PAD_CFG_NF_1V8(GPP_D9, UP_20K, RSMRST, NF4),",
-				Long:  "_PAD_CFG_STRUCT(GPP_D9, PAD_FUNC(NF4) | PAD_RESET(RSMRST) | PAD_TRIG(EDGE_SINGLE) | PAD_IRQ_ROUTE(IOAPIC) | PAD_IRQ_ROUTE(NMI) | PAD_BUF(TX_RX_DISABLE) | (1 << 29) | (1 << 28) | (1 << 1) | 1, PAD_CFG1_TOL_1V8PAD_PULL(UP_20K) | PAD_IOSSTATE(IGNORE) | PAD_IOSTERM(ENPU) | PAD_CFG_OWN_GPIO(DRIVER)),",
+				Long:  "_PAD_CFG_STRUCT(GPP_D9, PAD_FUNC(NF4) | PAD_RESET(RSMRST) | PAD_TRIG(EDGE_SINGLE) | PAD_IRQ_ROUTE(IOAPIC) | PAD_IRQ_ROUTE(NMI) | PAD_BUF(TX_RX_DISABLE) | (1 << 29) | (1 << 28) | (1 << 1) | 1, PAD_CFG1_TOL_1V8PAD_PULL(UP_20K) | PAD_IOSSTATE(ERROR) | PAD_IOSTERM(ENPU) | PAD_CFG_OWN_GPIO(DRIVER)),",
 			},
 		},
 		{
diff --git a/util/intelp2m/platforms/snr/macro.go b/util/intelp2m/platforms/snr/macro.go
index aa3be5d9bb..7eee4bf351 100644
--- a/util/intelp2m/platforms/snr/macro.go
+++ b/util/intelp2m/platforms/snr/macro.go
@@ -7,6 +7,7 @@ import (
 	"review.coreboot.org/coreboot.git/util/intelp2m/config/p2m"
 	"review.coreboot.org/coreboot.git/util/intelp2m/fields"
 	"review.coreboot.org/coreboot.git/util/intelp2m/platforms/common"
+	"review.coreboot.org/coreboot.git/util/intelp2m/platforms/common/register/bits"
 )
 
 const (
@@ -14,12 +15,6 @@ const (
 	PAD_CFG_DW1_RO_FIELDS = 0xfdffc3ff
 )
 
-const (
-	PAD_CFG_DW0 = common.PAD_CFG_DW0
-	PAD_CFG_DW1 = common.PAD_CFG_DW1
-	MAX_DW_NUM  = common.MAX_DW_NUM
-)
-
 type PlatformSpecific struct{}
 
 // RemmapRstSrc - remmap Pad Reset Source Config
@@ -32,29 +27,30 @@ func (PlatformSpecific) RemmapRstSrc() {
 		return
 	}
 
-	dw0 := macro.Register(PAD_CFG_DW0)
-	var remapping = map[uint8]uint32{
-		0: common.RST_RSMRST << common.PadRstCfgShift,
-		1: common.RST_DEEP << common.PadRstCfgShift,
-		2: common.RST_PLTRST << common.PadRstCfgShift,
+	dw0 := macro.GetRegisterDW0()
+	remapping := map[uint32]uint32{
+		0: bits.RstCfgRSMRST << bits.DW0PadRstCfg,
+		1: bits.RstCfgDEEP << bits.DW0PadRstCfg,
+		2: bits.RstCfgPLTRST << bits.DW0PadRstCfg,
 	}
 	resetsrc, valid := remapping[dw0.GetResetConfig()]
 	if valid {
 		// dw0.SetResetConfig(resetsrc)
-		ResetConfigFieldVal := (dw0.ValueGet() & 0x3fffffff) | remapping[dw0.GetResetConfig()]
-		dw0.ValueSet(ResetConfigFieldVal)
+		ResetConfigFieldVal := (dw0.Value & 0x3fffffff) | remapping[dw0.GetResetConfig()]
+		dw0.Value = ResetConfigFieldVal
 	} else {
 		fmt.Println("Invalid Pad Reset Config [ 0x", resetsrc, " ] for ", macro.PadIdGet())
 	}
-	dw0.CntrMaskFieldsClear(common.PadRstCfgMask)
+	mask := bits.DW0[bits.DW0PadRstCfg]
+	dw0.CntrMaskFieldsClear(mask)
 }
 
 // Adds The Pad Termination (TERM) parameter from PAD_CFG_DW1 to the macro
 // as a new argument
 func (PlatformSpecific) Pull() {
 	macro := common.GetMacro()
-	dw1 := macro.Register(PAD_CFG_DW1)
-	var pull = map[uint8]string{
+	dw1 := macro.GetRegisterDW1()
+	var pull = map[uint32]string{
 		0x0: "NONE",
 		0x2: "DN_5K",
 		0x4: "DN_20K",
@@ -79,13 +75,13 @@ func (PlatformSpecific) Pull() {
 // Generate macro to cause peripheral IRQ when configured in GPIO input mode
 func ioApicRoute() bool {
 	macro := common.GetMacro()
-	dw0 := macro.Register(PAD_CFG_DW0)
+	dw0 := macro.GetRegisterDW0()
 	if dw0.GetGPIOInputRouteIOxAPIC() == 0 {
 		return false
 	}
 
 	macro.Add("_APIC")
-	if dw0.GetRXLevelEdgeConfiguration() == common.TRIG_LEVEL {
+	if dw0.GetRXLevelEdgeConfiguration() == bits.TrigLEVEL {
 		if dw0.GetRxInvert() != 0 {
 			// PAD_CFG_GPI_APIC_LOW(pad, pull, rst)
 			macro.Add("_LOW")
@@ -105,7 +101,7 @@ func ioApicRoute() bool {
 // Generate macro to cause NMI when configured in GPIO input mode
 func nmiRoute() bool {
 	macro := common.GetMacro()
-	if macro.Register(PAD_CFG_DW0).GetGPIOInputRouteNMI() == 0 {
+	if macro.GetRegisterDW0().GetGPIOInputRouteNMI() == 0 {
 		return false
 	}
 	// PAD_CFG_GPI_NMI(GPIO_24, UP_20K, DEEP, LEVEL, INVERT),
@@ -116,7 +112,7 @@ func nmiRoute() bool {
 // Generate macro to cause SCI when configured in GPIO input mode
 func sciRoute() bool {
 	macro := common.GetMacro()
-	dw0 := macro.Register(PAD_CFG_DW0)
+	dw0 := macro.GetRegisterDW0()
 	if dw0.GetGPIOInputRouteSCI() == 0 {
 		return false
 	}
@@ -128,7 +124,7 @@ func sciRoute() bool {
 // Generate macro to cause SMI when configured in GPIO input mode
 func smiRoute() bool {
 	macro := common.GetMacro()
-	dw0 := macro.Register(PAD_CFG_DW0)
+	dw0 := macro.GetRegisterDW0()
 	if dw0.GetGPIOInputRouteSMI() == 0 {
 		return false
 	}
@@ -175,23 +171,24 @@ func (PlatformSpecific) GpiMacroAdd() {
 	default:
 		// Clear the control mask so that the check fails and "Advanced" macro is
 		// generated
-		macro.Register(PAD_CFG_DW0).CntrMaskFieldsClear(common.AllFields)
+		macro.GetRegisterDW0().CntrMaskFieldsClear(bits.All32)
 	}
 }
 
 // Adds PAD_CFG_GPO macro with arguments
 func (PlatformSpecific) GpoMacroAdd() {
 	macro := common.GetMacro()
-	dw0 := macro.Register(PAD_CFG_DW0)
-	term := macro.Register(PAD_CFG_DW1).GetTermination()
+	dw0 := macro.GetRegisterDW0()
+	term := macro.GetRegisterDW1().GetTermination()
 
 	// #define PAD_CFG_GPO(pad, val, rst)                \
 	//    _PAD_CFG_STRUCT(pad,                           \
 	//      PAD_FUNC(GPIO) | PAD_RESET(rst) |            \
 	//      PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | !!val, \
 	//      PAD_PULL(NONE) | PAD_IOSSTATE(TxLASTRxE))
-	if dw0.GetRXLevelEdgeConfiguration() != common.TRIG_OFF {
-		dw0.CntrMaskFieldsClear(common.RxLevelEdgeConfigurationMask)
+	if dw0.GetRXLevelEdgeConfiguration() != bits.TrigOFF {
+		mask := bits.DW0[bits.DW0RxLevelEdgeConfiguration]
+		dw0.CntrMaskFieldsClear(mask)
 	}
 	macro.Set("PAD_CFG")
 	if macro.IsOwnershipDriver() {
@@ -215,7 +212,7 @@ func (PlatformSpecific) NativeFunctionMacroAdd() {
 	macro := common.GetMacro()
 	// e.g. PAD_CFG_NF(GPP_D23, NONE, DEEP, NF1)
 	macro.Set("PAD_CFG_NF")
-	if macro.Register(PAD_CFG_DW1).GetPadTol() != 0 {
+	if macro.GetRegisterDW1().GetPadTol() != 0 {
 		macro.Add("_1V8")
 	}
 	macro.Add("(").Id().Pull().Rstsrc().Padfn().Add("),")
@@ -228,33 +225,44 @@ func (PlatformSpecific) NoConnMacroAdd() {
 	// _PAD_CFG_STRUCT(pad,
 	//     PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE),
 	//     PAD_PULL(pull) | PAD_IOSSTATE(TxDRxE)),
-	dw0 := macro.Register(PAD_CFG_DW0)
+	dw0 := macro.GetRegisterDW0()
 
 	// Some fields of the configuration registers are hidden inside the macros,
 	// we should check them to update the corresponding bits in the control mask.
-	if dw0.GetRXLevelEdgeConfiguration() != common.TRIG_OFF {
-		dw0.CntrMaskFieldsClear(common.RxLevelEdgeConfigurationMask)
+	if dw0.GetRXLevelEdgeConfiguration() != bits.TrigOFF {
+		mask := bits.DW0[bits.DW0RxLevelEdgeConfiguration]
+		dw0.CntrMaskFieldsClear(mask)
 	}
 	if dw0.GetResetConfig() != 1 { // 1 = RST_DEEP
-		dw0.CntrMaskFieldsClear(common.PadRstCfgMask)
+		mask := bits.DW0[bits.DW0PadRstCfg]
+		dw0.CntrMaskFieldsClear(mask)
 	}
 
 	macro.Set("PAD_NC").Add("(").Id().Pull().Add("),")
 }
 
 // GenMacro - generate pad macro
-// dw0 : DW0 config register value
-// dw1 : DW1 config register value
+// dw0Val : DW0 config register value
+// dw1Val : DW1 config register value
 // return: string of macro
-//
-//	error
-func (PlatformSpecific) GenMacro(id string, dw0 uint32, dw1 uint32, ownership uint8) string {
-	macro := common.GetInstanceMacro(PlatformSpecific{}, fields.InterfaceGet())
+func (PlatformSpecific) GenMacro(id string, dw0Val uint32, dw1Val uint32, ownership uint8) string {
+	macro := common.GetInstanceMacro(
+		PlatformSpecific{},
+		fields.InterfaceGet(),
+	)
 	macro.Clear()
-	macro.Register(PAD_CFG_DW0).CntrMaskFieldsClear(common.AllFields)
-	macro.Register(PAD_CFG_DW1).CntrMaskFieldsClear(common.AllFields)
+
+	dw0 := macro.GetRegisterDW0()
+	dw0.CntrMaskFieldsClear(bits.All32)
+
+	dw1 := macro.GetRegisterDW1()
+	dw1.CntrMaskFieldsClear(bits.All32)
+
+	dw0.Value = dw0Val
+	dw1.Value = dw1Val
+	dw0.ReadOnly = PAD_CFG_DW0_RO_FIELDS
+	dw1.ReadOnly = PAD_CFG_DW1_RO_FIELDS
+
 	macro.PadIdSet(id).SetPadOwnership(ownership)
-	macro.Register(PAD_CFG_DW0).ValueSet(dw0).ReadOnlyFieldsSet(PAD_CFG_DW0_RO_FIELDS)
-	macro.Register(PAD_CFG_DW1).ValueSet(dw1).ReadOnlyFieldsSet(PAD_CFG_DW1_RO_FIELDS)
 	return macro.Generate()
 }
diff --git a/util/intelp2m/platforms/tgl/macro.go b/util/intelp2m/platforms/tgl/macro.go
index c925eeb30c..fdd324fcdd 100644
--- a/util/intelp2m/platforms/tgl/macro.go
+++ b/util/intelp2m/platforms/tgl/macro.go
@@ -7,6 +7,7 @@ import (
 	"review.coreboot.org/coreboot.git/util/intelp2m/fields"
 	"review.coreboot.org/coreboot.git/util/intelp2m/platforms/cnl"
 	"review.coreboot.org/coreboot.git/util/intelp2m/platforms/common"
+	"review.coreboot.org/coreboot.git/util/intelp2m/platforms/common/register/bits"
 	"review.coreboot.org/coreboot.git/util/intelp2m/platforms/snr"
 )
 
@@ -15,12 +16,6 @@ const (
 	PAD_CFG_DW1_RO_FIELDS = 0xfdffc3ff
 )
 
-const (
-	PAD_CFG_DW0 = common.PAD_CFG_DW0
-	PAD_CFG_DW1 = common.PAD_CFG_DW1
-	MAX_DW_NUM  = common.MAX_DW_NUM
-)
-
 type InheritanceMacro interface {
 	Pull()
 	GpiMacroAdd()
@@ -43,21 +38,22 @@ func (PlatformSpecific) RemmapRstSrc() {
 		return
 	}
 
-	dw0 := macro.Register(PAD_CFG_DW0)
-	var remapping = map[uint8]uint32{
-		0: common.RST_RSMRST << common.PadRstCfgShift,
-		1: common.RST_DEEP << common.PadRstCfgShift,
-		2: common.RST_PLTRST << common.PadRstCfgShift,
+	dw0 := macro.GetRegisterDW0()
+	var remapping = map[uint32]uint32{
+		0: bits.RstCfgRSMRST << bits.DW0PadRstCfg,
+		1: bits.RstCfgDEEP << bits.DW0PadRstCfg,
+		2: bits.RstCfgPLTRST << bits.DW0PadRstCfg,
 	}
 	resetsrc, valid := remapping[dw0.GetResetConfig()]
 	if valid {
 		// dw0.SetResetConfig(resetsrc)
-		ResetConfigFieldVal := (dw0.ValueGet() & 0x3fffffff) | remapping[dw0.GetResetConfig()]
-		dw0.ValueSet(ResetConfigFieldVal)
+		ResetConfigFieldVal := (dw0.Value & 0x3fffffff) | remapping[dw0.GetResetConfig()]
+		dw0.Value = ResetConfigFieldVal
 	} else {
 		fmt.Println("Invalid Pad Reset Config [ 0x", resetsrc, " ] for ", macro.PadIdGet())
 	}
-	dw0.CntrMaskFieldsClear(common.PadRstCfgMask)
+	mask := bits.DW0[bits.DW0PadRstCfg]
+	dw0.CntrMaskFieldsClear(mask)
 }
 
 // Adds The Pad Termination (TERM) parameter from PAD_CFG_DW1 to the macro
@@ -90,9 +86,7 @@ func (platform PlatformSpecific) NoConnMacroAdd() {
 // dw0 : DW0 config register value
 // dw1 : DW1 config register value
 // return: string of macro
-//
-//	error
-func (PlatformSpecific) GenMacro(id string, dw0 uint32, dw1 uint32, ownership uint8) string {
+func (PlatformSpecific) GenMacro(id string, dw0Val, dw1Val uint32, ownership uint8) string {
 	macro := common.GetInstanceMacro(
 		PlatformSpecific{
 			InheritanceMacro: cnl.PlatformSpecific{
@@ -102,10 +96,18 @@ func (PlatformSpecific) GenMacro(id string, dw0 uint32, dw1 uint32, ownership ui
 		fields.InterfaceGet(),
 	)
 	macro.Clear()
-	macro.Register(PAD_CFG_DW0).CntrMaskFieldsClear(common.AllFields)
-	macro.Register(PAD_CFG_DW1).CntrMaskFieldsClear(common.AllFields)
+
+	dw0 := macro.GetRegisterDW0()
+	dw0.CntrMaskFieldsClear(bits.All32)
+
+	dw1 := macro.GetRegisterDW1()
+	dw1.CntrMaskFieldsClear(bits.All32)
+
+	dw0.Value = dw0Val
+	dw1.Value = dw1Val
+	dw0.ReadOnly = PAD_CFG_DW0_RO_FIELDS
+	dw1.ReadOnly = PAD_CFG_DW1_RO_FIELDS
+
 	macro.PadIdSet(id).SetPadOwnership(ownership)
-	macro.Register(PAD_CFG_DW0).ValueSet(dw0).ReadOnlyFieldsSet(PAD_CFG_DW0_RO_FIELDS)
-	macro.Register(PAD_CFG_DW1).ValueSet(dw1).ReadOnlyFieldsSet(PAD_CFG_DW1_RO_FIELDS)
 	return macro.Generate()
 }
diff --git a/util/intelp2m/platforms/tgl/tgl_test.go b/util/intelp2m/platforms/tgl/tgl_test.go
index e37567e4fa..a968f96fab 100644
--- a/util/intelp2m/platforms/tgl/tgl_test.go
+++ b/util/intelp2m/platforms/tgl/tgl_test.go
@@ -51,7 +51,7 @@ func TestGenMacro(t *testing.T) {
 			Pad: test.Pad{ID: "GPP_C5", DW0: 0xEEEEEEEE, DW1: 0xEEEEEEEE, Ownership: 1},
 			Macro: test.Macro{
 				Short: "PAD_CFG_NF_1V8(GPP_C5, UP_2K, RSMRST, NF3),",
-				Long:  "_PAD_CFG_STRUCT(GPP_C5, PAD_FUNC(NF3) | PAD_RESET(RSMRST) | PAD_TRIG(EDGE_BOTH) | PAD_IRQ_ROUTE(SCI) | PAD_IRQ_ROUTE(SMI) | PAD_IRQ_ROUTE(NMI) | PAD_RX_POL(INVERT) | PAD_BUF(RX_DISABLE) | (1 << 29) | (1 << 1), PAD_CFG1_TOL_1V8PAD_PULL(UP_2K) | PAD_IOSSTATE(IGNORE) | PAD_IOSTERM(ENPD) | PAD_CFG_OWN_GPIO(DRIVER)),",
+				Long:  "_PAD_CFG_STRUCT(GPP_C5, PAD_FUNC(NF3) | PAD_RESET(RSMRST) | PAD_TRIG(EDGE_BOTH) | PAD_IRQ_ROUTE(SCI) | PAD_IRQ_ROUTE(SMI) | PAD_IRQ_ROUTE(NMI) | PAD_RX_POL(INVERT) | PAD_BUF(RX_DISABLE) | (1 << 29) | (1 << 1), PAD_CFG1_TOL_1V8PAD_PULL(UP_2K) | PAD_IOSSTATE(ERROR) | PAD_IOSTERM(ENPD) | PAD_CFG_OWN_GPIO(DRIVER)),",
 			},
 		},
 		{
@@ -65,14 +65,14 @@ func TestGenMacro(t *testing.T) {
 			Pad: test.Pad{ID: "GPP_G7", DW0: 0xBBBBBBBB, DW1: 0xBBBBBBBB, Ownership: 1},
 			Macro: test.Macro{
 				Short: "PAD_CFG_NF_1V8(GPP_G7, INVALID, PLTRST, NF6),",
-				Long:  "_PAD_CFG_STRUCT(GPP_G7, PAD_FUNC(NF6) | PAD_RESET(PLTRST) | PAD_TRIG(EDGE_SINGLE) | PAD_IRQ_ROUTE(IOAPIC) | PAD_IRQ_ROUTE(SCI) | PAD_IRQ_ROUTE(NMI) | PAD_RX_POL(INVERT) | PAD_BUF(TX_RX_DISABLE) | (1 << 29) | (1 << 28) | (1 << 1) | 1, PAD_CFG1_TOL_1V8PAD_PULL(INVALID) | PAD_IOSSTATE(IGNORE) | PAD_IOSTERM(ENPU) | PAD_CFG_OWN_GPIO(DRIVER)),",
+				Long:  "_PAD_CFG_STRUCT(GPP_G7, PAD_FUNC(NF6) | PAD_RESET(PLTRST) | PAD_TRIG(EDGE_SINGLE) | PAD_IRQ_ROUTE(IOAPIC) | PAD_IRQ_ROUTE(SCI) | PAD_IRQ_ROUTE(NMI) | PAD_RX_POL(INVERT) | PAD_BUF(TX_RX_DISABLE) | (1 << 29) | (1 << 28) | (1 << 1) | 1, PAD_CFG1_TOL_1V8PAD_PULL(INVALID) | PAD_IOSSTATE(ERROR) | PAD_IOSTERM(ENPU) | PAD_CFG_OWN_GPIO(DRIVER)),",
 			},
 		},
 		{
 			Pad: test.Pad{ID: "GPD8", DW0: 0x77777777, DW1: 0x77777777, Ownership: 0},
 			Macro: test.Macro{
 				Short: "PAD_CFG_NF_1V8(GPD8, UP_667, DEEP, NF5),",
-				Long:  "_PAD_CFG_STRUCT(GPD8, PAD_FUNC(NF5) | PAD_RESET(DEEP) | PAD_TRIG(EDGE_BOTH) | PAD_IRQ_ROUTE(IOAPIC) | PAD_IRQ_ROUTE(SMI) | PAD_IRQ_ROUTE(NMI) | PAD_BUF(TX_RX_DISABLE) | (1 << 29) | (1 << 28) | (1 << 1) | 1, PAD_CFG1_TOL_1V8PAD_PULL(UP_667) | PAD_IOSSTATE(IGNORE) | PAD_IOSTERM(ENPU)),",
+				Long:  "_PAD_CFG_STRUCT(GPD8, PAD_FUNC(NF5) | PAD_RESET(DEEP) | PAD_TRIG(EDGE_BOTH) | PAD_IRQ_ROUTE(IOAPIC) | PAD_IRQ_ROUTE(SMI) | PAD_IRQ_ROUTE(NMI) | PAD_BUF(TX_RX_DISABLE) | (1 << 29) | (1 << 28) | (1 << 1) | 1, PAD_CFG1_TOL_1V8PAD_PULL(UP_667) | PAD_IOSSTATE(ERROR) | PAD_IOSTERM(ENPU)),",
 			},
 		},
 	}.Run(t, "INTEL-TIGER-LAKE-PCH/SLIDING-ZERO-IN-NIBBLE-TEST", tigerlake)
@@ -82,7 +82,7 @@ func TestGenMacro(t *testing.T) {
 			Pad: test.Pad{ID: "GPP_E9", DW0: 0x33333333, DW1: 0x33333333, Ownership: 1},
 			Macro: test.Macro{
 				Short: "PAD_CFG_NF_1V8(GPP_E9, UP_20K, RSMRST, NF4),",
-				Long:  "_PAD_CFG_STRUCT(GPP_E9, PAD_FUNC(NF4) | PAD_RESET(RSMRST) | PAD_TRIG(EDGE_SINGLE) | PAD_IRQ_ROUTE(IOAPIC) | PAD_IRQ_ROUTE(NMI) | PAD_BUF(TX_RX_DISABLE) | (1 << 29) | (1 << 28) | (1 << 1) | 1, PAD_CFG1_TOL_1V8PAD_PULL(UP_20K) | PAD_IOSSTATE(IGNORE) | PAD_IOSTERM(ENPU) | PAD_CFG_OWN_GPIO(DRIVER)),",
+				Long:  "_PAD_CFG_STRUCT(GPP_E9, PAD_FUNC(NF4) | PAD_RESET(RSMRST) | PAD_TRIG(EDGE_SINGLE) | PAD_IRQ_ROUTE(IOAPIC) | PAD_IRQ_ROUTE(NMI) | PAD_BUF(TX_RX_DISABLE) | (1 << 29) | (1 << 28) | (1 << 1) | 1, PAD_CFG1_TOL_1V8PAD_PULL(UP_20K) | PAD_IOSSTATE(ERROR) | PAD_IOSTERM(ENPU) | PAD_CFG_OWN_GPIO(DRIVER)),",
 			},
 		},
 		{

From 2e9dd0ade2e310203a299e02e80f99393118635f Mon Sep 17 00:00:00 2001
From: Maxim Polyakov <max.senia.poliak@gmail.com>
Date: Sat, 3 Dec 2022 22:41:42 +0300
Subject: [PATCH 0251/3886] util/intelp2m: Update cli options

- Redesign the options format.
- Add automatic completion of arguments for bash.
  [complete -C `pwd`/intelp2m ./intelp2m] to enable

TEST: make test = PASS

Change-Id: I08ff379b99b018b1099aa5d70fea47026bc84045
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70310
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 util/intelp2m/cli/completion.go    |  22 +++
 util/intelp2m/cli/options.go       | 232 +++++++++++++++++++++++++++++
 util/intelp2m/config/p2m/config.go |   4 +-
 util/intelp2m/main.go              |  91 ++---------
 util/intelp2m/version.txt          |   2 +-
 5 files changed, 270 insertions(+), 81 deletions(-)
 create mode 100644 util/intelp2m/cli/completion.go
 create mode 100644 util/intelp2m/cli/options.go

diff --git a/util/intelp2m/cli/completion.go b/util/intelp2m/cli/completion.go
new file mode 100644
index 0000000000..b322a87d10
--- /dev/null
+++ b/util/intelp2m/cli/completion.go
@@ -0,0 +1,22 @@
+package cli
+
+import (
+	"flag"
+	"fmt"
+	"os"
+	"strings"
+)
+
+func UseComplete() bool {
+	if _, ok := os.LookupEnv("COMP_LINE"); ok {
+		argument := os.Args[2]
+		argument = strings.TrimLeft(argument, "-")
+		flag.VisitAll(func(f *flag.Flag) {
+			if argument == "" || strings.HasPrefix(f.Name, argument) {
+				fmt.Println("-" + f.Name)
+			}
+		})
+		return true
+	}
+	return false
+}
diff --git a/util/intelp2m/cli/options.go b/util/intelp2m/cli/options.go
new file mode 100644
index 0000000000..c6adbcffd8
--- /dev/null
+++ b/util/intelp2m/cli/options.go
@@ -0,0 +1,232 @@
+package cli
+
+import (
+	"flag"
+	"fmt"
+	"os"
+	"path/filepath"
+
+	"review.coreboot.org/coreboot.git/util/intelp2m/config/p2m"
+)
+
+var name = filepath.Base(os.Args[0])
+
+const usagePlatform = `usage: -platform <type>
+    type: adl | apl | cnl | ebg | jsl | lbg | mtl | snr | tgl | ?
+        adl - Alder Lake PCH
+        apl - Apollo Lake SoC
+        cnl - CannonLake-LP or Whiskeylake/Coffeelake/Cometlake-U SoC
+        ebg - Emmitsburg PCH with Xeon SP
+        jsl - Jasper Lake SoC
+        lbg - Lewisburg PCH with Xeon SP
+        mtl - MeteorLake SoC
+        snr - Sunrise PCH or Skylake/Kaby Lake SoC
+        tgl - TigerLake-H SoC
+        ?   - show details
+`
+const usageFields = `usage: -fields <type>
+    type: cb | fsp | raw | ?
+        cb  - coreboot style
+        fsp - Intel FSP style
+        raw - raw register value (don't convert, print as is)
+        ?   - show details
+`
+const usageExclude = `usage: -e | -exclude
+    Exclude fields that should be ignored to generate "short" macro.
+    Details:
+        The utility should ignore "PAD_TRIG(OFF)" field in the "_PAD_CFG_STRUCT(GPP_I12,
+        PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, 0)"
+        "long" macro to generate the "PAD_CFG_GPO(GPP_I12, 1, PLTRST)" macro.
+
+        The utility with this option generates the "long" macro with only those fields that are
+        required to create the "short" one (in thia case without the "PAD_TRIG(OFF)" field):
+        "_PAD_CFG_STRUCT(GPP_I12, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_BUF(RX_DISABLE) | 1, 0)"
+`
+
+const usageUnchecked = `usage: -u | -unchecked
+    Disable automatic bitfield checking before generating.
+    Details:
+        The utility automatically checks the bit fields of the DW registers before generating
+        the macro. If a bit is set in the register and it is not used in the "short" macro, the
+        utility will generate the "long" one instead of the first one.
+
+        This option is used to disable automatic verification. In this case, all macros are
+        generated in the "short" format:
+            PAD_NC(GPP_F18, NONE),
+            PAD_CFG_NF(GPP_F19, NONE, PLTRST, NF1),
+            ...
+`
+
+const usageInfo = `usage: -i | -ii | -iii | -iiii
+    Generate additional information about macros.
+    Level 1 information (-i):
+        _PAD_CFG_STRUCT(GPP_A4, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | (1 << 1), 0), /* LAD3 */
+
+    Level 2 information (-ii):
+        /* GPP_A4 - LAD3 */
+        /* DW0: 0x80000402, DW1: 0x00000000 */
+        _PAD_CFG_STRUCT(GPP_A4, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | (1 << 1), 0),
+
+    Level 3 information (-iii):
+        /* GPP_A3 - LAD2 */
+        /* DW0: 0x80000402, DW1: 0x00000000 */
+        /* DW0: (1 << 1) - IGNORED */
+        _PAD_CFG_STRUCT(GPP_A3, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | (1 << 1), 0),
+
+    Level 4 information (-iiii):
+        /* GPP_A4 - LAD3 */
+        /* DW0: 0x80000402, DW1: 0x00000000 */
+        /* DW0: (1 << 1) - IGNORED */
+        /* PAD_CFG_NF(GPP_A4, NONE, PLTRST, NF1), */
+        _PAD_CFG_STRUCT(GPP_A4, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | (1 << 1), 0),
+`
+
+const usage = `
+basic functions:
+    -h | -help              Print help
+    -v | -version           Print version
+         -file <path>       Set path to the inteltool file. <inteltool.log> by default
+         -out <path>        Set path to the generated file. <generate/gpio.h> by default
+    -p | -platform <type>   Set the PCH platform type. <sunrise> by default
+                            (enter ? to show datails)
+
+generation of long composite macros with bit field definitions:
+    -f | -fields <type>     Set the bitfield type for the generated long macro
+                            (enter ? to show datails)
+
+control flags:
+    -e | -exclude           Exclude fields that should be ignored to generate short macro
+    -u | -unchecked         Disable automatic bitfield checking before generating
+                            (enter ? to show datails)
+
+generate additional information:
+    -i                      Add function to the comments
+    -ii                     Add DW0/DW1 register value to the comments
+    -iii                    Add ignored bitfields to the comments
+    -iiii                   Add target PAD_CFG() macro to the comments
+                            (enter ? to show datails)
+`
+
+func Usage() {
+	fmt.Printf(`usage: %s <switches> %s`, name, usage)
+}
+
+func cbOptionsPlatform(value string) error {
+	if value == "?" {
+		fmt.Printf("%s", usagePlatform)
+		os.Exit(0)
+	}
+
+	if err := p2m.SetPlatformType(value); err != nil {
+		fmt.Printf("error: %v\n%s", err, usagePlatform)
+		os.Exit(0)
+	}
+
+	return nil
+}
+
+func cbOptionsFields(value string) error {
+	if value == "?" {
+		fmt.Printf("%s", usageFields)
+		os.Exit(0)
+	}
+
+	if err := p2m.SetFieldType(value); err != nil {
+		fmt.Printf("error: %v\n%s", err, usageFields)
+		os.Exit(0)
+	}
+
+	return nil
+}
+
+func cbOptionsExclude(_ string) error {
+	if numArgs := flag.NArg(); numArgs == 1 {
+		if flag.Arg(0) == "?" {
+			fmt.Printf("%s", usageExclude)
+		}
+		Usage()
+		os.Exit(0)
+	}
+	p2m.Config.IgnoredFields = true
+	return nil
+}
+
+func cbOptionsUnchecked(_ string) error {
+	if numArgs := flag.NArg(); numArgs == 1 {
+		if flag.Arg(0) == "?" {
+			fmt.Printf("%s", usageUnchecked)
+		}
+		Usage()
+		os.Exit(0)
+	}
+	p2m.Config.AutoCheck = false
+	return nil
+}
+
+func cbOptionsInfo(_ string) error {
+	if numArgs := flag.NArg(); numArgs == 1 {
+		if flag.Arg(0) == "?" {
+			fmt.Printf("%s", usageInfo)
+			os.Exit(0)
+		}
+		Usage()
+		os.Exit(0)
+	}
+
+	table := map[string]int{
+		"-i":    1,
+		"-ii":   2,
+		"-iii":  3,
+		"-iiii": 4,
+	}
+	for _, arg := range os.Args {
+		if level, exist := table[arg]; exist {
+			p2m.Config.GenLevel = level
+			return nil
+		}
+	}
+	Usage()
+	return nil
+}
+
+func ParseOptions() {
+	flag.Usage = Usage
+	flag.StringVar(&p2m.Config.InputPath, "file", "inteltool.log", "")
+	flag.StringVar(&p2m.Config.OutputPath, "out", "generate/gpio.h", "")
+	help := flag.Bool("help", false, "")
+
+	vers, v := flag.Bool("version", false, ""), flag.Bool("v", false, "")
+
+	flag.Func("platform", usagePlatform, cbOptionsPlatform)
+	flag.Func("p", usagePlatform, cbOptionsPlatform)
+
+	flag.Func("fields", usageFields, cbOptionsFields)
+	flag.Func("f", usageFields, cbOptionsFields)
+
+	flag.BoolFunc("exclude", usageExclude, cbOptionsExclude)
+	flag.BoolFunc("e", usageExclude, cbOptionsExclude)
+
+	flag.BoolFunc("unchecked", usageUnchecked, cbOptionsUnchecked)
+	flag.BoolFunc("u", usageUnchecked, cbOptionsUnchecked)
+
+	flag.BoolFunc("i", usageInfo, cbOptionsInfo)
+	flag.BoolFunc("ii", usageInfo, cbOptionsInfo)
+	flag.BoolFunc("iii", usageInfo, cbOptionsInfo)
+	flag.BoolFunc("iiii", usageInfo, cbOptionsInfo)
+
+	if UseComplete() {
+		os.Exit(0)
+	}
+
+	flag.Parse()
+
+	if *help {
+		Usage()
+		os.Exit(0)
+	}
+
+	if *vers || *v {
+		fmt.Println(p2m.Config.Version)
+		os.Exit(0)
+	}
+}
diff --git a/util/intelp2m/config/p2m/config.go b/util/intelp2m/config/p2m/config.go
index ce03ee0c36..07efb5b7bb 100644
--- a/util/intelp2m/config/p2m/config.go
+++ b/util/intelp2m/config/p2m/config.go
@@ -50,6 +50,8 @@ type Settings struct {
 	Version       string
 	Platform      PlatformType
 	Field         FieldType
+	InputPath     string
+	OutputPath    string
 	InputFile     *os.File
 	OutputFile    *os.File
 	IgnoredFields bool
@@ -60,7 +62,7 @@ type Settings struct {
 var Config = Settings{
 	Version:       "unknown",
 	Platform:      Sunrise,
-	Field:         CbFlds,
+	Field:         NoFlds,
 	IgnoredFields: false,
 	AutoCheck:     true,
 	GenLevel:      0,
diff --git a/util/intelp2m/main.go b/util/intelp2m/main.go
index f0e2203c3f..47a1516c98 100644
--- a/util/intelp2m/main.go
+++ b/util/intelp2m/main.go
@@ -1,11 +1,11 @@
 package main
 
 import (
-	"flag"
 	"fmt"
 	"os"
 	"path/filepath"
 
+	"review.coreboot.org/coreboot.git/util/intelp2m/cli"
 	"review.coreboot.org/coreboot.git/util/intelp2m/config/p2m"
 	"review.coreboot.org/coreboot.git/util/intelp2m/parser"
 )
@@ -24,101 +24,34 @@ func (Printer) Line(lvl int, str string) {
 	}
 }
 
-var (
-	// Version is injected into main during project build
-	Version string = "Unknown"
-)
-
-// printVersion - print the utility version in the console
-func printVersion() {
-	fmt.Printf("[ intelp2m ] Version: %s\n", Version)
-}
+// Version is injected into main during project build
+var Version string = "Unknown"
 
 // main
 func main() {
-	// Command line arguments
-	inputFilePath := flag.String("file", "inteltool.log",
-		"the path to the inteltool log file\n")
-
-	outputFilePath := flag.String("o",
-		"generate/gpio.h",
-		"the path to the generated file with GPIO configuration\n")
-
-	ignored := flag.Bool("ign", false,
-		"exclude fields that should be ignored from advanced macros\n")
-
-	unchecking := flag.Bool("n", false,
-		"Generate macros without checking.\n"+
-			"\tIn this case, some fields of the configuration registers\n"+
-			"\tDW0 will be ignored.\n")
-
-	levels := []*bool{
-		flag.Bool("i", false, "Show pads function in the comments"),
-		flag.Bool("ii", false, "Show DW0/DW1 value in the comments"),
-		flag.Bool("iii", false, "Show ignored bit fields in the comments"),
-		flag.Bool("iiii", false, "Show target PAD_CFG() macro in the comments"),
-	}
-
-	platform := flag.String("p", "snr", "set platform:\n"+
-		"\tsnr - Sunrise PCH or Skylake/Kaby Lake SoC\n"+
-		"\tlbg - Lewisburg PCH with Xeon SP\n"+
-		"\tapl - Apollo Lake SoC\n"+
-		"\tcnl - CannonLake-LP or Whiskeylake/Coffeelake/Cometlake-U SoC\n"+
-		"\ttgl - TigerLake-H SoC\n"+
-		"\tadl - AlderLake PCH\n"+
-		"\tjsl - Jasper Lake SoC\n"+
-		"\tmtl - MeteorLake SoC\n"+
-		"\tebg - Emmitsburg PCH with Xeon SP\n")
-
-	field := flag.String("fld", "none", "set fields macros style:\n"+
-		"\tcb  - use coreboot style for bit fields macros\n"+
-		"\tfsp - use fsp style\n"+
-		"\traw - do not convert, print as is\n")
-
-	flag.Parse()
-	printVersion()
-
-	// settings
 	p2m.Config.Version = Version
-	p2m.Config.IgnoredFields = *ignored
-	p2m.Config.AutoCheck = !(*unchecking)
-	for level, set := range levels {
-		if *set {
-			p2m.Config.GenLevel = level + 1
-			fmt.Printf("Info level: Use level %d!\n", level+1)
-			break
-		}
-	}
 
-	if err := p2m.SetPlatformType(*platform); err != nil {
-		fmt.Printf("Error: %v\n", err)
-		os.Exit(1)
-	}
+	cli.ParseOptions()
 
-	if err := p2m.SetFieldType(*field); err != nil {
-		fmt.Printf("Error: %v\n", err)
-		os.Exit(1)
-	}
-
-	if file, err := os.Open(*inputFilePath); err != nil {
-		fmt.Printf("input file error: %v", err)
+	if file, err := os.Open(p2m.Config.InputPath); err != nil {
+		fmt.Printf("input file error: %v\n", err)
 		os.Exit(1)
 	} else {
 		p2m.Config.InputFile = file
+		defer file.Close()
 	}
-	defer p2m.Config.InputFile.Close()
 
-	if err := os.MkdirAll(filepath.Dir(*outputFilePath), os.ModePerm); err != nil {
-		fmt.Printf("failed to create output directory: %v", err)
+	if err := os.MkdirAll(filepath.Dir(p2m.Config.OutputPath), os.ModePerm); err != nil {
+		fmt.Printf("failed to create output directory: %v\n", err)
 		os.Exit(1)
 	}
-	if file, err := os.Create(*outputFilePath); err != nil {
-		fmt.Printf("failed to create output file: %v", err)
+	if file, err := os.Create(p2m.Config.OutputPath); err != nil {
+		fmt.Printf("failed to create output file: %v\n", err)
 		os.Exit(1)
 	} else {
 		p2m.Config.OutputFile = file
+		defer file.Close()
 	}
-	defer p2m.Config.OutputFile.Close()
 
 	prs := parser.ParserData{}
 	prs.Parse()
diff --git a/util/intelp2m/version.txt b/util/intelp2m/version.txt
index 5625e59da8..7e32cd5698 100644
--- a/util/intelp2m/version.txt
+++ b/util/intelp2m/version.txt
@@ -1 +1 @@
-1.2
+1.3

From be7eb061310e560e48e9c77cd4d006282f0df1cf Mon Sep 17 00:00:00 2001
From: Maxim Polyakov <max.senia.poliak@gmail.com>
Date: Mon, 5 Dec 2022 11:41:51 +0300
Subject: [PATCH 0252/3886] util/intelp2m: Add logger

Add logging to a file, ./logs.txt by default. --logs option is used to
override this path. Error messages are duplicated to the console.

Change-Id: I97aba146b6d8866a7fa46bac80c27c0896b26cf7
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70542
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 util/intelp2m/.gitignore           |  2 +-
 util/intelp2m/cli/options.go       |  3 ++
 util/intelp2m/config/p2m/config.go |  1 +
 util/intelp2m/logs/logs.go         | 50 ++++++++++++++++++++++++++++++
 util/intelp2m/main.go              | 11 +++++++
 util/intelp2m/version.txt          |  2 +-
 6 files changed, 67 insertions(+), 2 deletions(-)
 create mode 100644 util/intelp2m/logs/logs.go

diff --git a/util/intelp2m/.gitignore b/util/intelp2m/.gitignore
index c973792029..e4ad107438 100644
--- a/util/intelp2m/.gitignore
+++ b/util/intelp2m/.gitignore
@@ -1,2 +1,2 @@
 intelp2m
-generate/gpio.h
+gpio.h
diff --git a/util/intelp2m/cli/options.go b/util/intelp2m/cli/options.go
index c6adbcffd8..6001039966 100644
--- a/util/intelp2m/cli/options.go
+++ b/util/intelp2m/cli/options.go
@@ -87,6 +87,7 @@ basic functions:
     -v | -version           Print version
          -file <path>       Set path to the inteltool file. <inteltool.log> by default
          -out <path>        Set path to the generated file. <generate/gpio.h> by default
+         -logs <path>       Override the log file path. <logs.txt> by default
     -p | -platform <type>   Set the PCH platform type. <sunrise> by default
                             (enter ? to show datails)
 
@@ -193,6 +194,8 @@ func ParseOptions() {
 	flag.Usage = Usage
 	flag.StringVar(&p2m.Config.InputPath, "file", "inteltool.log", "")
 	flag.StringVar(&p2m.Config.OutputPath, "out", "generate/gpio.h", "")
+	flag.StringVar(&p2m.Config.LogsPath, "logs", "logs.txt", "")
+
 	help := flag.Bool("help", false, "")
 
 	vers, v := flag.Bool("version", false, ""), flag.Bool("v", false, "")
diff --git a/util/intelp2m/config/p2m/config.go b/util/intelp2m/config/p2m/config.go
index 07efb5b7bb..6fe9a00f3f 100644
--- a/util/intelp2m/config/p2m/config.go
+++ b/util/intelp2m/config/p2m/config.go
@@ -52,6 +52,7 @@ type Settings struct {
 	Field         FieldType
 	InputPath     string
 	OutputPath    string
+	LogsPath      string
 	InputFile     *os.File
 	OutputFile    *os.File
 	IgnoredFields bool
diff --git a/util/intelp2m/logs/logs.go b/util/intelp2m/logs/logs.go
new file mode 100644
index 0000000000..579ac818de
--- /dev/null
+++ b/util/intelp2m/logs/logs.go
@@ -0,0 +1,50 @@
+package logs
+
+import (
+	"fmt"
+	"log"
+	"os"
+
+	"review.coreboot.org/coreboot.git/util/intelp2m/config/p2m"
+)
+
+var (
+	linfo    *log.Logger
+	lwarning *log.Logger
+	lerror   *log.Logger
+)
+
+func Init() (*os.File, error) {
+
+	flags := os.O_RDWR | os.O_CREATE | os.O_APPEND
+	file, err := os.OpenFile(p2m.Config.LogsPath, flags, 0666)
+	if err != nil {
+		fmt.Printf("logs: error opening %s file: %v", p2m.Config.LogsPath, err)
+		return nil, err
+	}
+
+	attributes := log.Lshortfile
+	linfo = log.New(file, "INFO:    ", attributes)
+	lwarning = log.New(file, "WARNING: ", attributes)
+	lerror = log.New(file, "ERROR:   ", attributes)
+	return file, nil
+}
+
+func Infof(format string, v ...any) {
+	if linfo != nil {
+		linfo.Output(2, fmt.Sprintf(format, v...))
+	}
+}
+
+func Warnf(format string, v ...any) {
+	if lwarning != nil {
+		lwarning.Output(2, fmt.Sprintf(format, v...))
+	}
+}
+
+func Errorf(format string, v ...any) {
+	if lerror != nil {
+		lerror.Output(2, fmt.Sprintf(format, v...))
+	}
+	log.Output(2, fmt.Sprintf(format, v...))
+}
diff --git a/util/intelp2m/main.go b/util/intelp2m/main.go
index 47a1516c98..a4b4b22941 100644
--- a/util/intelp2m/main.go
+++ b/util/intelp2m/main.go
@@ -7,6 +7,7 @@ import (
 
 	"review.coreboot.org/coreboot.git/util/intelp2m/cli"
 	"review.coreboot.org/coreboot.git/util/intelp2m/config/p2m"
+	"review.coreboot.org/coreboot.git/util/intelp2m/logs"
 	"review.coreboot.org/coreboot.git/util/intelp2m/parser"
 )
 
@@ -33,6 +34,13 @@ func main() {
 
 	cli.ParseOptions()
 
+	if file, err := logs.Init(); err != nil {
+		fmt.Printf("logs init error: %v\n", err)
+		os.Exit(1)
+	} else {
+		defer file.Close()
+	}
+
 	if file, err := os.Open(p2m.Config.InputPath); err != nil {
 		fmt.Printf("input file error: %v\n", err)
 		os.Exit(1)
@@ -53,6 +61,8 @@ func main() {
 		defer file.Close()
 	}
 
+	logs.Infof("start %s", os.Args[0])
+
 	prs := parser.ParserData{}
 	prs.Parse()
 
@@ -80,5 +90,6 @@ static const struct pad_config gpio_table[] = {`, Version)
 
 #endif /* CFG_GPIO_H */
 `)
+	logs.Infof("exit from %s\n", os.Args[0])
 	os.Exit(0)
 }
diff --git a/util/intelp2m/version.txt b/util/intelp2m/version.txt
index 7e32cd5698..c068b2447c 100644
--- a/util/intelp2m/version.txt
+++ b/util/intelp2m/version.txt
@@ -1 +1 @@
-1.3
+1.4

From 2c2e92f7f7e939668a2435c088647aa7634254b1 Mon Sep 17 00:00:00 2001
From: Maxim Polyakov <max.senia.poliak@gmail.com>
Date: Tue, 6 Dec 2022 14:29:42 +0300
Subject: [PATCH 0253/3886] util/intelp2m: Drop non-DWx register analysis
 support

The utility can parse the value of non-DWx registers, if they are
present in the inteltool dump. However, the functions that allow the
inteltool utility to print the value of such registers have not been
added to the master branch, and it makes no sense to support such
functions in intelp2m, besides, their implementation is far from ideal.
Remove this unused functionality. This will be restored in the future in
a different form and after corresponding changes in inteltool.

TEST: make test = PASS

Change-Id: If5c77ff942a620897c085be4135cb879a0d40a00
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56887
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 util/intelp2m/parser/parser.go          | 77 +------------------------
 util/intelp2m/parser/template.go        | 22 +------
 util/intelp2m/platforms/adl/template.go | 19 ++----
 util/intelp2m/platforms/apl/template.go | 12 +---
 util/intelp2m/platforms/cnl/template.go | 14 +----
 util/intelp2m/platforms/ebg/macro.go    |  1 -
 util/intelp2m/platforms/ebg/template.go | 21 ++-----
 util/intelp2m/platforms/jsl/template.go | 17 ++----
 util/intelp2m/platforms/lbg/template.go | 15 ++---
 util/intelp2m/platforms/mtl/template.go | 17 ++----
 util/intelp2m/platforms/snr/template.go | 18 ++----
 util/intelp2m/platforms/tgl/template.go | 21 ++-----
 util/intelp2m/version.txt               |  2 +-
 13 files changed, 40 insertions(+), 216 deletions(-)

diff --git a/util/intelp2m/parser/parser.go b/util/intelp2m/parser/parser.go
index f2756107bf..4fd15a357d 100644
--- a/util/intelp2m/parser/parser.go
+++ b/util/intelp2m/parser/parser.go
@@ -4,8 +4,6 @@ import (
 	"bufio"
 	"errors"
 	"fmt"
-	"strconv"
-	"strings"
 
 	"review.coreboot.org/coreboot.git/util/intelp2m/config/p2m"
 	"review.coreboot.org/coreboot.git/util/intelp2m/platforms/adl"
@@ -23,7 +21,6 @@ import (
 // PlatformSpecific - platform-specific interface
 type PlatformSpecific interface {
 	GenMacro(id string, dw0 uint32, dw1 uint32, ownership uint8) string
-	GroupNameExtract(line string) (bool, string)
 	KeywordCheck(line string) bool
 }
 
@@ -55,20 +52,6 @@ type ParserData struct {
 	ownership map[string]uint32
 }
 
-// hostOwnershipGet - get the host software ownership value for the corresponding
-// pad ID
-// id : pad ID string
-// return the host software ownership form the parser struct
-func (parser *ParserData) hostOwnershipGet(id string) uint8 {
-	var ownership uint8 = 0
-	_, group := parser.platform.GroupNameExtract(id)
-	numder, _ := strconv.Atoi(strings.TrimLeft(id, group))
-	if (parser.ownership[group] & (1 << uint8(numder))) != 0 {
-		ownership = 1
-	}
-	return ownership
-}
-
 // padInfoExtract - adds a new entry to pad info map
 // return error status
 func (parser *ParserData) padInfoExtract() int {
@@ -81,7 +64,7 @@ func (parser *ParserData) padInfoExtract() int {
 		function:  function,
 		dw0:       dw0,
 		dw1:       dw1,
-		ownership: parser.hostOwnershipGet(id)}
+		ownership: 0}
 	parser.padmap = append(parser.padmap, pad)
 	return 0
 
@@ -111,65 +94,11 @@ func (parser *ParserData) PlatformSpecificInterfaceSet() {
 		p2m.Jasper: jsl.PlatformSpecific{},
 		p2m.Meteor: mtl.PlatformSpecific{},
 		// See platforms/ebg/macro.go
-		p2m.Emmitsburg: ebg.PlatformSpecific{
-			InheritanceTemplate: cnl.PlatformSpecific{
-				InheritanceTemplate: snr.PlatformSpecific{},
-			},
-		},
+		p2m.Emmitsburg: ebg.PlatformSpecific{},
 	}
 	parser.platform = platform[p2m.Config.Platform]
 }
 
-// Register - read specific platform registers (32 bits)
-// line         : string from file with pad config map
-// nameTemplate : register name femplate to filter parsed lines
-// return
-//
-//	valid  : true if the dump of the register in intertool.log is set in accordance
-//	         with the template
-//	name   : full register name
-//	offset : register offset relative to the base address
-//	value  : register value
-func (parser *ParserData) Register(nameTemplate string) (
-	valid bool,
-	name string,
-	offset uint32,
-	value uint32,
-) {
-	if strings.Contains(parser.line, nameTemplate) {
-		if registerInfoTemplate(parser.line, &name, &offset, &value) == 0 {
-			fmt.Printf("\n\t/* %s : 0x%x : 0x%x */\n", name, offset, value)
-			return true, name, offset, value
-		}
-	}
-	return false, "ERROR", 0, 0
-}
-
-// padOwnershipExtract - extract Host Software Pad Ownership from inteltool dump
-//
-//	return true if success
-func (parser *ParserData) padOwnershipExtract() bool {
-	var group string
-	status, name, offset, value := parser.Register("HOSTSW_OWN_GPP_")
-	if status {
-		_, group = parser.platform.GroupNameExtract(parser.line)
-		parser.ownership[group] = value
-		fmt.Printf("\n\t/* padOwnershipExtract: [offset 0x%x] %s = 0x%x */\n",
-			offset, name, parser.ownership[group])
-	}
-	return status
-}
-
-// padConfigurationExtract - reads GPIO configuration registers and returns true if the
-//
-//	information from the inteltool log was successfully parsed.
-func (parser *ParserData) padConfigurationExtract() bool {
-	if p2m.Config.Platform == p2m.Apollo {
-		return false
-	}
-	return parser.padOwnershipExtract()
-}
-
 // Parse pads groupe information in the inteltool log file
 // ConfigFile : name of inteltool log file
 func (parser *ParserData) Parse() {
@@ -189,7 +118,7 @@ func (parser *ParserData) Parse() {
 		isIncluded, _ := common.KeywordsCheck(parser.line, "GPIO Community", "GPIO Group")
 		if isIncluded {
 			parser.communityGroupExtract()
-		} else if !parser.padConfigurationExtract() && parser.platform.KeywordCheck(parser.line) {
+		} else if parser.platform.KeywordCheck(parser.line) {
 			if parser.padInfoExtract() != 0 {
 				fmt.Println("...error!")
 			}
diff --git a/util/intelp2m/parser/template.go b/util/intelp2m/parser/template.go
index 49b938fd56..7d3e1aa819 100644
--- a/util/intelp2m/parser/template.go
+++ b/util/intelp2m/parser/template.go
@@ -38,8 +38,9 @@ func tokenCheck(c rune) bool {
 // *id       : pad id string
 // *dw0      : DW0 register value
 // *dw1      : DW1 register value
+//
 // return
-//   error status
+// error status
 func UseTemplate(line string, function *string, id *string, dw0 *uint32, dw1 *uint32) int {
 	var val uint64
 	// 0x0520: 0x0000003c44000600 GPP_B12  SLP_S0#
@@ -61,22 +62,3 @@ func UseTemplate(line string, function *string, id *string, dw0 *uint32, dw1 *ui
 	}
 	return 0
 }
-
-// registerInfoTemplate
-// line    : (in)  string from file with pad config map
-// *name   : (out) register name
-// *offset : (out) offset name
-// *value  : (out) register value
-// return
-//   error status
-func registerInfoTemplate(line string, name *string, offset *uint32, value *uint32) int {
-	// 0x0088: 0x00ffffff (HOSTSW_OWN_GPP_F)
-	// 0x0100: 0x00000000 (GPI_IS_GPP_A)
-	if fields := strings.FieldsFunc(line, tokenCheck); len(fields) == 3 {
-		*name = fields[2]
-		fmt.Sscanf(fields[1], "0x%x", value)
-		fmt.Sscanf(fields[0], "0x%x", offset)
-		return 0
-	}
-	return -1
-}
diff --git a/util/intelp2m/platforms/adl/template.go b/util/intelp2m/platforms/adl/template.go
index 672be84070..1642670144 100644
--- a/util/intelp2m/platforms/adl/template.go
+++ b/util/intelp2m/platforms/adl/template.go
@@ -2,22 +2,13 @@ package adl
 
 import "review.coreboot.org/coreboot.git/util/intelp2m/platforms/common"
 
-// GroupNameExtract - This function extracts the group ID, if it exists in a row
-// line      : string from the configuration file
-// return
-//     bool   : true if the string contains a group identifier
-//     string : group identifier
-func (PlatformSpecific) GroupNameExtract(line string) (bool, string) {
-	return common.KeywordsCheck(line,
-		"GPP_A", "GPP_B", "GPP_C", "GPP_D", "GPP_E", "GPP_F", "GPP_G",
-		"GPP_H", "GPP_I", "GPP_J", "GPP_K", "GPP_R", "GPP_S", "GPP_T",
-		"GPD", "VGPIO_USB", "VGPIO_PCIE")
-
-}
+// Group : "GPP_A", "GPP_B", "GPP_C", "GPP_D", "GPP_E", "GPP_F", "GPP_G",
+//         "GPP_H", "GPP_I", "GPP_J", "GPP_K", "GPP_R", "GPP_S", "GPP_T",
+//         "GPD", "VGPIO_USB", "VGPIO_PCIE"
 
 // KeywordCheck - This function is used to filter parsed lines of the configuration file and
-//                returns true if the keyword is contained in the line.
-// line      : string from the configuration file
+// returns true if the keyword is contained in the line.
+// line : string from the configuration file
 func (PlatformSpecific) KeywordCheck(line string) bool {
 	isIncluded, _ := common.KeywordsCheck(line, "GPP_", "GPD", "VGPIO")
 	return isIncluded
diff --git a/util/intelp2m/platforms/apl/template.go b/util/intelp2m/platforms/apl/template.go
index 05d505f786..36040cab96 100644
--- a/util/intelp2m/platforms/apl/template.go
+++ b/util/intelp2m/platforms/apl/template.go
@@ -2,18 +2,8 @@ package apl
 
 import "review.coreboot.org/coreboot.git/util/intelp2m/platforms/common"
 
-// GroupNameExtract - This function extracts the group ID, if it exists in a row
-// line      : string from the configuration file
-// return
-//     bool   : true if the string contains a group identifier
-//     string : group identifier
-func (PlatformSpecific) GroupNameExtract(line string) (bool, string) {
-	// Not supported
-	return false, ""
-}
-
 // KeywordCheck - This function is used to filter parsed lines of the configuration file and
-//                returns true if the keyword is contained in the line.
+// returns true if the keyword is contained in the line.
 // line      : string from the configuration file
 func (PlatformSpecific) KeywordCheck(line string) bool {
 	isIncluded, _ := common.KeywordsCheck(line,
diff --git a/util/intelp2m/platforms/cnl/template.go b/util/intelp2m/platforms/cnl/template.go
index b38d9689f4..886a59a920 100644
--- a/util/intelp2m/platforms/cnl/template.go
+++ b/util/intelp2m/platforms/cnl/template.go
@@ -1,23 +1,13 @@
 package cnl
 
-import "review.coreboot.org/coreboot.git/util/intelp2m/platforms/common"
-
 type InheritanceTemplate interface {
 	KeywordCheck(line string) bool
 }
 
-// GroupNameExtract - This function extracts the group ID, if it exists in a row
-// line      : string from the configuration file
-// return
-//     bool   : true if the string contains a group identifier
-//     string : group identifier
-func (PlatformSpecific) GroupNameExtract(line string) (bool, string) {
-	return common.KeywordsCheck(line,
-		"GPP_A", "GPP_B", "GPP_G", "GPP_D", "GPP_F", "GPP_H", "GPD", "GPP_C", "GPP_E")
-}
+// Group: "GPP_A", "GPP_B", "GPP_G", "GPP_D", "GPP_F", "GPP_H", "GPD", "GPP_C", "GPP_E"
 
 // KeywordCheck - This function is used to filter parsed lines of the configuration file and
-//                returns true if the keyword is contained in the line.
+// returns true if the keyword is contained in the line.
 // line      : string from the configuration file
 func (platform PlatformSpecific) KeywordCheck(line string) bool {
 	return platform.InheritanceTemplate.KeywordCheck(line)
diff --git a/util/intelp2m/platforms/ebg/macro.go b/util/intelp2m/platforms/ebg/macro.go
index 9dba566907..8026a2d484 100644
--- a/util/intelp2m/platforms/ebg/macro.go
+++ b/util/intelp2m/platforms/ebg/macro.go
@@ -25,7 +25,6 @@ type InheritanceMacro interface {
 
 type PlatformSpecific struct {
 	InheritanceMacro
-	InheritanceTemplate
 }
 
 // RemmapRstSrc - remmap Pad Reset Source Config
diff --git a/util/intelp2m/platforms/ebg/template.go b/util/intelp2m/platforms/ebg/template.go
index 0ec9bc31a8..32ba246ec9 100644
--- a/util/intelp2m/platforms/ebg/template.go
+++ b/util/intelp2m/platforms/ebg/template.go
@@ -2,25 +2,12 @@ package ebg
 
 import "review.coreboot.org/coreboot.git/util/intelp2m/platforms/common"
 
-type InheritanceTemplate interface {
-	GroupNameExtract(line string) (bool, string)
-	KeywordCheck(line string) bool
-}
-
-// GroupNameExtract - This function extracts the group ID, if it exists in a row
-// line      : string from the configuration file
-// return
-//     bool   : true if the string contains a group identifier
-//     string : group identifier
-func (platform PlatformSpecific) GroupNameExtract(line string) (bool, string) {
-	return common.KeywordsCheck(line,
-		"GPPC_A", "GPPC_B", "GPPC_S", "GPPC_C", "GPP_D", "GPP_E", "GPPC_H", "GPP_J",
-		"GPP_I", "GPP_L", "GPP_M", "GPP_N")
-}
+// Group : "GPPC_A", "GPPC_B", "GPPC_S", "GPPC_C", "GPP_D", "GPP_E", "GPPC_H", "GPP_J",
+//         "GPP_I", "GPP_L", "GPP_M", "GPP_N"
 
 // KeywordCheck - This function is used to filter parsed lines of the configuration file and
-//                returns true if the keyword is contained in the line.
-// line      : string from the configuration file
+// returns true if the keyword is contained in the line.
+// line : string from the configuration file
 func (platform PlatformSpecific) KeywordCheck(line string) bool {
 	isIncluded, _ := common.KeywordsCheck(line, "GPP_", "GPPC_")
 	return isIncluded
diff --git a/util/intelp2m/platforms/jsl/template.go b/util/intelp2m/platforms/jsl/template.go
index 203b27ebdc..ec6e9c91a9 100644
--- a/util/intelp2m/platforms/jsl/template.go
+++ b/util/intelp2m/platforms/jsl/template.go
@@ -2,21 +2,12 @@ package jsl
 
 import "review.coreboot.org/coreboot.git/util/intelp2m/platforms/common"
 
-// GroupNameExtract - This function extracts the group ID, if it exists in a row
-// line      : string from the configuration file
-// return
-//     bool   : true if the string contains a group identifier
-//     string : group identifier
-func (PlatformSpecific) GroupNameExtract(line string) (bool, string) {
-	return common.KeywordsCheck(line,
-		"GPP_A", "GPP_B", "GPP_C", "GPP_D", "GPP_E", "GPP_F", "GPP_G",
-		"GPP_H", "GPP_R", "GPP_S", "GPP_T", "GPD", "HVMOS", "VGPIO5")
-
-}
+// Group : "GPP_A", "GPP_B", "GPP_C", "GPP_D", "GPP_E", "GPP_F", "GPP_G", "GPP_H", "GPP_R",
+//         "GPP_S", "GPP_T", "GPD", "HVMOS", "VGPIO5"
 
 // KeywordCheck - This function is used to filter parsed lines of the configuration file and
-//                returns true if the keyword is contained in the line.
-// line      : string from the configuration file
+// returns true if the keyword is contained in the line.
+// line : string from the configuration file
 func (PlatformSpecific) KeywordCheck(line string) bool {
 	isIncluded, _ := common.KeywordsCheck(line, "GPP_", "GPD", "VGPIO")
 	return isIncluded
diff --git a/util/intelp2m/platforms/lbg/template.go b/util/intelp2m/platforms/lbg/template.go
index 74c39efadf..d76f2cdef3 100644
--- a/util/intelp2m/platforms/lbg/template.go
+++ b/util/intelp2m/platforms/lbg/template.go
@@ -1,22 +1,15 @@
 package lbg
 
 type InheritanceTemplate interface {
-	GroupNameExtract(line string) (bool, string)
 	KeywordCheck(line string) bool
 }
 
-// GroupNameExtract - This function extracts the group ID, if it exists in a row
-// line      : string from the configuration file
-// return
-//     bool   : true if the string contains a group identifier
-//     string : group identifier
-func (platform PlatformSpecific) GroupNameExtract(line string) (bool, string) {
-	return platform.InheritanceTemplate.GroupNameExtract(line)
-}
+// Group: "GPP_A", "GPP_B", "GPP_F", "GPP_C", "GPP_D", "GPP_E", "GPD", "GPP_I", "GPP_J",
+//        "GPP_K", "GPP_G", "GPP_H", "GPP_L"
 
 // KeywordCheck - This function is used to filter parsed lines of the configuration file and
-//                returns true if the keyword is contained in the line.
-// line      : string from the configuration file
+// returns true if the keyword is contained in the line.
+// line : string from the configuration file
 func (platform PlatformSpecific) KeywordCheck(line string) bool {
 	return platform.InheritanceTemplate.KeywordCheck(line)
 }
diff --git a/util/intelp2m/platforms/mtl/template.go b/util/intelp2m/platforms/mtl/template.go
index 76a65f3f18..3f44928909 100644
--- a/util/intelp2m/platforms/mtl/template.go
+++ b/util/intelp2m/platforms/mtl/template.go
@@ -2,21 +2,12 @@ package mtl
 
 import "review.coreboot.org/coreboot.git/util/intelp2m/platforms/common"
 
-// GroupNameExtract - This function extracts the group ID, if it exists in a row
-// line      : string from the configuration file
-// return
-//     bool   : true if the string contains a group identifier
-//     string : group identifier
-func (PlatformSpecific) GroupNameExtract(line string) (bool, string) {
-	return common.KeywordsCheck(line,
-		"GPP_V", "GPP_C", "GPP_A", "GPP_E", "GPP_H", "GPP_F", "GPP_S",
-		"GPP_B", "GPP_D", "GPD", "VGPIO_USB", "VGPIO_PCIE")
-
-}
+// Group : "GPP_V", "GPP_C", "GPP_A", "GPP_E", "GPP_H", "GPP_F", "GPP_S", "GPP_B", "GPP_D",
+//         "GPD", "VGPIO_USB", "VGPIO_PCIE"
 
 // KeywordCheck - This function is used to filter parsed lines of the configuration file and
-//                returns true if the keyword is contained in the line.
-// line      : string from the configuration file
+// returns true if the keyword is contained in the line.
+// line : string from the configuration file
 func (PlatformSpecific) KeywordCheck(line string) bool {
 	isIncluded, _ := common.KeywordsCheck(line, "GPP_", "GPD", "VGPIO")
 	return isIncluded
diff --git a/util/intelp2m/platforms/snr/template.go b/util/intelp2m/platforms/snr/template.go
index 2a5dfc3643..4d02743463 100644
--- a/util/intelp2m/platforms/snr/template.go
+++ b/util/intelp2m/platforms/snr/template.go
@@ -2,22 +2,14 @@ package snr
 
 import "review.coreboot.org/coreboot.git/util/intelp2m/platforms/common"
 
-// GroupNameExtract - This function extracts the group ID, if it exists in a row
-// line      : string from the configuration file
-// return
-//     bool   : true if the string contains a group identifier
-//     string : group identifier
-func (PlatformSpecific) GroupNameExtract(line string) (bool, string) {
-	return common.KeywordsCheck(line,
-		"GPP_A", "GPP_B", "GPP_F", "GPP_C", "GPP_D", "GPP_E", "GPD", "GPP_I", "GPP_J",
-		"GPP_K", "GPP_G", "GPP_H", "GPP_L")
-}
+// Group: "GPP_A", "GPP_B", "GPP_F", "GPP_C", "GPP_D", "GPP_E", "GPD", "GPP_I", "GPP_J",
+//        "GPP_K", "GPP_G", "GPP_H", "GPP_L"
 
 // KeywordCheck - This function is used to filter parsed lines of the configuration file and
-//                returns true if the keyword is contained in the line.
+// returns true if the keyword is contained in the line.
 // line : string from the configuration file
 // Returns false if no word was found, or true otherwise
 func (PlatformSpecific) KeywordCheck(line string) bool {
-	isIncluded, _ := common.KeywordsCheck(line, "GPP_", "GPD")
-	return isIncluded
+	included, _ := common.KeywordsCheck(line, "GPP_", "GPD")
+	return included
 }
diff --git a/util/intelp2m/platforms/tgl/template.go b/util/intelp2m/platforms/tgl/template.go
index 5a93aee06b..4e9a2ba069 100644
--- a/util/intelp2m/platforms/tgl/template.go
+++ b/util/intelp2m/platforms/tgl/template.go
@@ -2,23 +2,12 @@ package tgl
 
 import "review.coreboot.org/coreboot.git/util/intelp2m/platforms/common"
 
-// GroupNameExtract - This function extracts the group ID, if it exists in a row
-// line      : string from the configuration file
-// return
-//
-//	bool   : true if the string contains a group identifier
-//	string : group identifier
-func (PlatformSpecific) GroupNameExtract(line string) (bool, string) {
-	return common.KeywordsCheck(line,
-		"GPP_A", "GPP_R", "GPP_B", "GPP_D", "GPP_C", "GPP_S", "GPP_G",
-		"GPD", "GPP_E", "GPP_F", "GPP_H", "GPP_J", "GPP_K", "GPP_I",
-		"VGPIO_USB", "VGPIO_PCIE")
+// Group : "GPP_A", "GPP_R", "GPP_B", "GPP_D", "GPP_C", "GPP_S", "GPP_G", "GPD", "GPP_E",
+//         "GPP_F", "GPP_H", "GPP_J", "GPP_K", "GPP_I", "VGPIO_USB", "VGPIO_PCIE"
 
-}
-
-// KeywordCheck - This function is used to filter parsed lines of the configuration file and
-// returns true if the keyword is contained in the line.
-// line  : string from the configuration file
+// KeywordCheck - This function is used to filter parsed lines of the configuration file
+// and returns true if the keyword is contained in the line.
+// line : string from the configuration file
 func (PlatformSpecific) KeywordCheck(line string) bool {
 	isIncluded, _ := common.KeywordsCheck(line, "GPP_", "GPD", "VGPIO")
 	return isIncluded
diff --git a/util/intelp2m/version.txt b/util/intelp2m/version.txt
index c068b2447c..c239c60cba 100644
--- a/util/intelp2m/version.txt
+++ b/util/intelp2m/version.txt
@@ -1 +1 @@
-1.4
+1.5

From e91324707ed2e94279c60d87c83a38ec884c84e4 Mon Sep 17 00:00:00 2001
From: Maxim Polyakov <max.senia.poliak@gmail.com>
Date: Thu, 8 Dec 2022 10:44:46 +0300
Subject: [PATCH 0254/3886] util/intelp2m: Rewrite parser

- Split the parser code into several packages to make its testing of its
  functions more convenient and detailed. This also makes embedding the
  parser in third-party applications more flexible - there is no need to
  use all the functionality of the parser.

- Clean up code and remove unnecessary objects to make intelp2m simpler
  and more readable.

- Change the common macro format to be consistent with the new parser.

- Rename the results directory containing gpio.h to output to avoid
  confusion with the generator package directory.

- At the moment there is no mechanism for setting the Ownership flag.
  This will be added in later versions.

Tests:
- make test = PASS
- gpio.h for Apollo Lake before and after the patch is the same

Change-Id: I9a29322dd31faf9ae100165f08f207360cbf9f80
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70543
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
---
 util/intelp2m/Makefile                        |   2 +-
 util/intelp2m/cli/options.go                  |   3 +-
 util/intelp2m/config/p2m/config.go            |  11 +-
 util/intelp2m/generator/generator.go          |  64 +++++
 util/intelp2m/generator/generator_test.go     |  63 +++++
 util/intelp2m/generator/header/header.go      |  30 +++
 util/intelp2m/generator/printer/printer.go    |  35 +++
 .../generator/testsuites/i0nocomments.go      |  46 ++++
 .../generator/testsuites/i1comments.go        |  46 ++++
 .../generator/testsuites/i2AutoCheck.go       |  97 +++++++
 .../generator/testsuites/i3Uncheck.go         | 111 ++++++++
 .../testsuites/i4ExcludeUnusedCbFlds.go       | 127 +++++++++
 util/intelp2m/main.go                         |  79 ++----
 util/intelp2m/parser/parser.go                | 245 +++++++-----------
 util/intelp2m/parser/parser_test.go           |  88 +------
 util/intelp2m/parser/template.go              |  64 -----
 util/intelp2m/parser/template/template.go     |  48 ++++
 .../parser/{ => template}/template_test.go    |  22 +-
 util/intelp2m/parser/test/suite.go            | 152 +++++++++++
 .../{test => testlog}/inteltool_test.log      |   0
 util/intelp2m/platforms/common/macro.go       |   8 +-
 util/intelp2m/platforms/interfaces.go         |  38 +++
 22 files changed, 1014 insertions(+), 365 deletions(-)
 create mode 100644 util/intelp2m/generator/generator.go
 create mode 100644 util/intelp2m/generator/generator_test.go
 create mode 100644 util/intelp2m/generator/header/header.go
 create mode 100644 util/intelp2m/generator/printer/printer.go
 create mode 100644 util/intelp2m/generator/testsuites/i0nocomments.go
 create mode 100644 util/intelp2m/generator/testsuites/i1comments.go
 create mode 100644 util/intelp2m/generator/testsuites/i2AutoCheck.go
 create mode 100644 util/intelp2m/generator/testsuites/i3Uncheck.go
 create mode 100644 util/intelp2m/generator/testsuites/i4ExcludeUnusedCbFlds.go
 delete mode 100644 util/intelp2m/parser/template.go
 create mode 100644 util/intelp2m/parser/template/template.go
 rename util/intelp2m/parser/{ => template}/template_test.go (60%)
 create mode 100644 util/intelp2m/parser/test/suite.go
 rename util/intelp2m/parser/{test => testlog}/inteltool_test.log (100%)
 create mode 100644 util/intelp2m/platforms/interfaces.go

diff --git a/util/intelp2m/Makefile b/util/intelp2m/Makefile
index 5f6bc29261..cb1ce43c1b 100644
--- a/util/intelp2m/Makefile
+++ b/util/intelp2m/Makefile
@@ -5,7 +5,7 @@ THIS_FILE := $(lastword $(MAKEFILE_LIST))
 THIS_DIR  := $(abspath $(dir $(THIS_FILE)))
 SCRIPTS_DIR := $(THIS_DIR)/scripts/linux
 
-OUTPUT_DIR := $(THIS_DIR)/generate
+OUTPUT_DIR := $(THIS_DIR)/output
 VERSION ?= $(shell $(SCRIPTS_DIR)/version.sh)
 LDFLAGS = "-X main.Version=$(VERSION)"
 
diff --git a/util/intelp2m/cli/options.go b/util/intelp2m/cli/options.go
index 6001039966..1d4e5ec030 100644
--- a/util/intelp2m/cli/options.go
+++ b/util/intelp2m/cli/options.go
@@ -192,8 +192,9 @@ func cbOptionsInfo(_ string) error {
 
 func ParseOptions() {
 	flag.Usage = Usage
+
 	flag.StringVar(&p2m.Config.InputPath, "file", "inteltool.log", "")
-	flag.StringVar(&p2m.Config.OutputPath, "out", "generate/gpio.h", "")
+	flag.StringVar(&p2m.Config.OutputPath, "out", "output/gpio.h", "")
 	flag.StringVar(&p2m.Config.LogsPath, "logs", "logs.txt", "")
 
 	help := flag.Bool("help", false, "")
diff --git a/util/intelp2m/config/p2m/config.go b/util/intelp2m/config/p2m/config.go
index 6fe9a00f3f..4271200c09 100644
--- a/util/intelp2m/config/p2m/config.go
+++ b/util/intelp2m/config/p2m/config.go
@@ -2,7 +2,6 @@ package p2m
 
 import (
 	"fmt"
-	"os"
 )
 
 type PlatformType int
@@ -53,14 +52,12 @@ type Settings struct {
 	InputPath     string
 	OutputPath    string
 	LogsPath      string
-	InputFile     *os.File
-	OutputFile    *os.File
 	IgnoredFields bool
 	AutoCheck     bool
 	GenLevel      int
 }
 
-var Config = Settings{
+var defaultConfig = Settings{
 	Version:       "unknown",
 	Platform:      Sunrise,
 	Field:         NoFlds,
@@ -69,6 +66,12 @@ var Config = Settings{
 	GenLevel:      0,
 }
 
+var Config = defaultConfig
+
+func SettingsReset() {
+	Config = defaultConfig
+}
+
 func SetPlatformType(format string) error {
 	if _, exist := platforms[format]; !exist {
 		return fmt.Errorf("unknown platform type %s", format)
diff --git a/util/intelp2m/generator/generator.go b/util/intelp2m/generator/generator.go
new file mode 100644
index 0000000000..906e9458e3
--- /dev/null
+++ b/util/intelp2m/generator/generator.go
@@ -0,0 +1,64 @@
+package generator
+
+import (
+	"fmt"
+
+	"review.coreboot.org/coreboot.git/util/intelp2m/config/p2m"
+	"review.coreboot.org/coreboot.git/util/intelp2m/logs"
+	"review.coreboot.org/coreboot.git/util/intelp2m/parser"
+)
+
+type collector []string
+
+func (c *collector) Line(str string) {
+	*c = append(*c, str)
+}
+
+func (c *collector) Linef(format string, args ...interface{}) {
+	*c = append(*c, fmt.Sprintf(format, args...))
+}
+
+// Run() generates strings with macros
+func Run(entries []parser.Entry) ([]string, error) {
+	if len(entries) == 0 {
+		err := fmt.Errorf("entries array is empty")
+		logs.Errorf("%v", err)
+		return nil, err
+	}
+	collection := make(collector, 0)
+	logs.Infof("run")
+	for _, entry := range entries {
+		switch entry.EType {
+		case parser.EntryGroup:
+			collection.Line("\n")
+			collection.Linef("\t/* %s */\n", entry.Function)
+
+		case parser.EntryReserved:
+			if p2m.Config.GenLevel >= 2 {
+				collection.Line("\n")
+			}
+			collection.Linef("\t/* %s - %s */\n", entry.ID, entry.Function)
+
+		case parser.EntryPad:
+			if p2m.Config.GenLevel >= 2 {
+				collection.Line("\n")
+				collection.Linef("\t/* %s - %s */\n", entry.ID, entry.Function)
+				collection.Linef("\t/* DW0: 0x%0.8x, DW1: 0x%0.8x */\n", entry.DW0, entry.DW1)
+			}
+			lines := entry.ToMacro()
+			if p2m.Config.GenLevel == 1 && len(lines) != 0 {
+				collection.Linef("\t%s\t/* %s */\n", lines[0], entry.Function)
+				break
+			}
+
+			for i := range lines {
+				collection.Linef("\t%s\n", lines[i])
+			}
+
+		default:
+			logs.Errorf("unknown entry type: %d", int(entry.EType))
+		}
+	}
+	logs.Infof("successfully completed: %d rows", len(collection))
+	return collection, nil
+}
diff --git a/util/intelp2m/generator/generator_test.go b/util/intelp2m/generator/generator_test.go
new file mode 100644
index 0000000000..56bf9d4c47
--- /dev/null
+++ b/util/intelp2m/generator/generator_test.go
@@ -0,0 +1,63 @@
+package generator_test
+
+import (
+	"strings"
+	"testing"
+
+	"review.coreboot.org/coreboot.git/util/intelp2m/config/p2m"
+	"review.coreboot.org/coreboot.git/util/intelp2m/generator"
+	"review.coreboot.org/coreboot.git/util/intelp2m/generator/testsuites"
+	parsertest "review.coreboot.org/coreboot.git/util/intelp2m/parser/test"
+)
+
+func do(t *testing.T, reference string) {
+	actually, err := generator.Run(parsertest.Suite)
+	if err != nil {
+		t.Errorf("failed to run generator: %v", err)
+	}
+
+	expects := strings.SplitAfter(reference, "\n")
+	for i := range actually {
+		if expects[i] != actually[i] {
+			t.Errorf("row number %d:\n\tExpects: <%s>\n\tActually <%s>",
+				i, expects[i], actually[i])
+		}
+	}
+}
+
+func TestGenerator(t *testing.T) {
+	t.Run("GENERATOR/I0-NO-COMMENTS", func(t *testing.T) {
+		p2m.SettingsReset()
+		p2m.Config.AutoCheck = false
+		do(t, testsuites.ReferenceI0NoComments)
+	})
+
+	t.Run("GENERATOR/I1-WITH-COMMENTS", func(t *testing.T) {
+		p2m.SettingsReset()
+		p2m.Config.AutoCheck = false
+		p2m.Config.GenLevel = 1
+		do(t, testsuites.ReferenceI1Comments)
+	})
+
+	t.Run("GENERATOR/I2-AUTO-CHECK", func(t *testing.T) {
+		p2m.SettingsReset()
+		p2m.Config.GenLevel = 2
+		do(t, testsuites.ReferenceI2AutoCheck)
+	})
+
+	t.Run("GENERATOR/I3-UNCHECK", func(t *testing.T) {
+		p2m.SettingsReset()
+		p2m.Config.AutoCheck = false
+		p2m.Config.IgnoredFields = true
+		p2m.Config.GenLevel = 3
+		do(t, testsuites.ReferenceI3Uncheck)
+	})
+
+	t.Run("GENERATOR/I4-EXCLUDE-UNUSED-CB-FIELDS", func(t *testing.T) {
+		p2m.SettingsReset()
+		p2m.Config.IgnoredFields = true
+		p2m.Config.Field = p2m.CbFlds
+		p2m.Config.GenLevel = 4
+		do(t, testsuites.ReferenceI4ExcludeUnusedCbFlds)
+	})
+}
diff --git a/util/intelp2m/generator/header/header.go b/util/intelp2m/generator/header/header.go
new file mode 100644
index 0000000000..4383e055b6
--- /dev/null
+++ b/util/intelp2m/generator/header/header.go
@@ -0,0 +1,30 @@
+package header
+
+import (
+	"fmt"
+
+	"review.coreboot.org/coreboot.git/util/intelp2m/config/p2m"
+)
+
+const fileHeader string = `/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef CFG_GPIO_H
+#define CFG_GPIO_H
+
+#include <gpio.h>
+
+/* Pad configuration was generated automatically using intelp2m %s */
+static const struct pad_config gpio_table[] = {`
+
+const completion string = `};
+
+#endif /* CFG_GPIO_H */
+`
+
+func Add(lines []string) []string {
+	wrapper := make([]string, 0)
+	wrapper = append(wrapper, fmt.Sprintf(fileHeader, p2m.Config.Version))
+	wrapper = append(wrapper, lines...)
+	wrapper = append(wrapper, completion)
+	return wrapper
+}
diff --git a/util/intelp2m/generator/printer/printer.go b/util/intelp2m/generator/printer/printer.go
new file mode 100644
index 0000000000..4c5856a8c1
--- /dev/null
+++ b/util/intelp2m/generator/printer/printer.go
@@ -0,0 +1,35 @@
+package printer
+
+import (
+	"fmt"
+	"os"
+	"path/filepath"
+
+	"review.coreboot.org/coreboot.git/util/intelp2m/config/p2m"
+	"review.coreboot.org/coreboot.git/util/intelp2m/logs"
+)
+
+func Do(rows []string) error {
+	path := p2m.Config.OutputPath
+	if err := os.MkdirAll(filepath.Dir(path), os.ModePerm); err != nil {
+		logs.Errorf("failed to create output directory: %v", err)
+		return err
+	}
+
+	file, err := os.Create(path)
+	if err != nil {
+		logs.Errorf("failed to create output file: %v", err)
+		return err
+	}
+	defer file.Close()
+
+	logs.Infof("write lines to file %s", path)
+	for i := range rows {
+		if _, err := fmt.Fprint(file, rows[i]); err != nil {
+			logs.Errorf("failed to write: %v", err)
+			return err
+		}
+	}
+	logs.Infof("successfully completed: %d rows", len(rows))
+	return nil
+}
diff --git a/util/intelp2m/generator/testsuites/i0nocomments.go b/util/intelp2m/generator/testsuites/i0nocomments.go
new file mode 100644
index 0000000000..7333468c24
--- /dev/null
+++ b/util/intelp2m/generator/testsuites/i0nocomments.go
@@ -0,0 +1,46 @@
+package testsuites
+
+const ReferenceI0NoComments = `
+	/* ------- GPIO Community 0 ------- */
+
+	/* ------- GPIO Group GPP_A ------- */
+	PAD_CFG_NF(GPP_A0, NONE, PLTRST, NF1),
+	PAD_CFG_NF(GPP_A1, UP_20K, PLTRST, NF1),
+	PAD_CFG_NF(GPP_A5, NONE, PLTRST, NF1),
+	PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1),
+	PAD_CFG_GPI_TRIG_OWN(GPP_A23, NONE, PLTRST, OFF, ACPI),
+
+	/* ------- GPIO Group GPP_B ------- */
+	/* GPP_C1 - RESERVED */
+	PAD_CFG_GPI_TRIG_OWN(GPP_B0, NONE, PLTRST, OFF, ACPI),
+	PAD_CFG_NF(GPP_B23, DN_20K, PLTRST, NF2),
+
+	/* ------- GPIO Community 1 ------- */
+
+	/* ------- GPIO Group GPP_C ------- */
+	PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1),
+	PAD_CFG_GPI_TRIG_OWN(GPP_C5, NONE, PLTRST, OFF, ACPI),
+	/* GPP_C6 - RESERVED */
+	/* GPP_C7 - RESERVED */
+	PAD_CFG_NF(GPP_C22, NONE, PLTRST, NF1),
+
+	/* ------- GPIO Group GPP_D ------- */
+
+	/* ------- GPIO Group GPP_E ------- */
+	PAD_CFG_NF(GPP_E0, UP_20K, PLTRST, NF1),
+
+	/* ------- GPIO Group GPP_G ------- */
+	PAD_CFG_NF(GPP_G19, NONE, PLTRST, NF1),
+
+	/* ------- GPIO Community 2 ------- */
+
+	/* -------- GPIO Group GPD -------- */
+	PAD_CFG_NF(GPD9, NONE, PWROK, NF1),
+
+	/* ------- GPIO Community 3 ------- */
+
+	/* ------- GPIO Group GPP_I ------- */
+	PAD_CFG_NF(GPP_I0, NONE, PLTRST, NF1),
+	PAD_CFG_NF(GPP_I1, NONE, PLTRST, NF1),
+	PAD_CFG_NF(GPP_I2, NONE, PLTRST, NF1),
+`
diff --git a/util/intelp2m/generator/testsuites/i1comments.go b/util/intelp2m/generator/testsuites/i1comments.go
new file mode 100644
index 0000000000..ca082ed120
--- /dev/null
+++ b/util/intelp2m/generator/testsuites/i1comments.go
@@ -0,0 +1,46 @@
+package testsuites
+
+const ReferenceI1Comments = `
+	/* ------- GPIO Community 0 ------- */
+
+	/* ------- GPIO Group GPP_A ------- */
+	PAD_CFG_NF(GPP_A0, NONE, PLTRST, NF1),	/* RCIN# */
+	PAD_CFG_NF(GPP_A1, UP_20K, PLTRST, NF1),	/* LAD0 */
+	PAD_CFG_NF(GPP_A5, NONE, PLTRST, NF1),	/* LFRAME# */
+	PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1),	/* SUSWARN#/SUSPWRDNACK */
+	PAD_CFG_GPI_TRIG_OWN(GPP_A23, NONE, PLTRST, OFF, ACPI),	/* GPIO */
+
+	/* ------- GPIO Group GPP_B ------- */
+	/* GPP_C1 - RESERVED */
+	PAD_CFG_GPI_TRIG_OWN(GPP_B0, NONE, PLTRST, OFF, ACPI),	/* GPIO */
+	PAD_CFG_NF(GPP_B23, DN_20K, PLTRST, NF2),	/* PCHHOT# */
+
+	/* ------- GPIO Community 1 ------- */
+
+	/* ------- GPIO Group GPP_C ------- */
+	PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1),	/* SMBCLK */
+	PAD_CFG_GPI_TRIG_OWN(GPP_C5, NONE, PLTRST, OFF, ACPI),	/* GPIO */
+	/* GPP_C6 - RESERVED */
+	/* GPP_C7 - RESERVED */
+	PAD_CFG_NF(GPP_C22, NONE, PLTRST, NF1),	/* UART2_RTS# */
+
+	/* ------- GPIO Group GPP_D ------- */
+
+	/* ------- GPIO Group GPP_E ------- */
+	PAD_CFG_NF(GPP_E0, UP_20K, PLTRST, NF1),	/* SATAXPCIE0 */
+
+	/* ------- GPIO Group GPP_G ------- */
+	PAD_CFG_NF(GPP_G19, NONE, PLTRST, NF1),	/* SMI# */
+
+	/* ------- GPIO Community 2 ------- */
+
+	/* -------- GPIO Group GPD -------- */
+	PAD_CFG_NF(GPD9, NONE, PWROK, NF1),	/* SLP_WLAN# */
+
+	/* ------- GPIO Community 3 ------- */
+
+	/* ------- GPIO Group GPP_I ------- */
+	PAD_CFG_NF(GPP_I0, NONE, PLTRST, NF1),	/* DDPB_HPD0 */
+	PAD_CFG_NF(GPP_I1, NONE, PLTRST, NF1),	/* DDPC_HPD1 */
+	PAD_CFG_NF(GPP_I2, NONE, PLTRST, NF1),	/* DDPD_HPD2 */
+`
diff --git a/util/intelp2m/generator/testsuites/i2AutoCheck.go b/util/intelp2m/generator/testsuites/i2AutoCheck.go
new file mode 100644
index 0000000000..514cc57eef
--- /dev/null
+++ b/util/intelp2m/generator/testsuites/i2AutoCheck.go
@@ -0,0 +1,97 @@
+package testsuites
+
+const ReferenceI2AutoCheck string = `
+	/* ------- GPIO Community 0 ------- */
+
+	/* ------- GPIO Group GPP_A ------- */
+
+	/* GPP_A0 - RCIN# */
+	/* DW0: 0x84000502, DW1: 0x00000000 */
+	_PAD_CFG_STRUCT(GPP_A0, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0),
+
+	/* GPP_A1 - LAD0 */
+	/* DW0: 0x84000402, DW1: 0x00003000 */
+	_PAD_CFG_STRUCT(GPP_A1, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | (1 << 1), PAD_PULL(UP_20K)),
+
+	/* GPP_A5 - LFRAME# */
+	/* DW0: 0x84000600, DW1: 0x00000000 */
+	_PAD_CFG_STRUCT(GPP_A5, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), 0),
+
+	/* GPP_A13 - SUSWARN#/SUSPWRDNACK */
+	/* DW0: 0x44000600, DW1: 0x00000000 */
+	_PAD_CFG_STRUCT(GPP_A13, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), 0),
+
+	/* GPP_A23 - GPIO */
+	/* DW0: 0x84000102, DW1: 0x00000000 */
+	_PAD_CFG_STRUCT(GPP_A23, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0),
+
+	/* ------- GPIO Group GPP_B ------- */
+
+	/* GPP_C1 - RESERVED */
+
+	/* GPP_B0 - GPIO */
+	/* DW0: 0x84000100, DW1: 0x00000000 */
+	PAD_CFG_GPI_TRIG_OWN(GPP_B0, NONE, PLTRST, OFF, ACPI),
+
+	/* GPP_B23 - PCHHOT# */
+	/* DW0: 0x84000a01, DW1: 0x00001000 */
+	_PAD_CFG_STRUCT(GPP_B23, PAD_FUNC(NF2) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, PAD_PULL(DN_20K)),
+
+	/* ------- GPIO Community 1 ------- */
+
+	/* ------- GPIO Group GPP_C ------- */
+
+	/* GPP_C0 - SMBCLK */
+	/* DW0: 0x44000502, DW1: 0x00000000 */
+	_PAD_CFG_STRUCT(GPP_C0, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0),
+
+	/* GPP_C5 - GPIO */
+	/* DW0: 0x84000100, DW1: 0x00000000 */
+	PAD_CFG_GPI_TRIG_OWN(GPP_C5, NONE, PLTRST, OFF, ACPI),
+
+	/* GPP_C6 - RESERVED */
+
+	/* GPP_C7 - RESERVED */
+
+	/* GPP_C22 - UART2_RTS# */
+	/* DW0: 0x84000600, DW1: 0x00000000 */
+	_PAD_CFG_STRUCT(GPP_C22, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), 0),
+
+	/* ------- GPIO Group GPP_D ------- */
+
+	/* ------- GPIO Group GPP_E ------- */
+
+	/* GPP_E0 - SATAXPCIE0 */
+	/* DW0: 0x84000502, DW1: 0x00003000 */
+	_PAD_CFG_STRUCT(GPP_E0, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), PAD_PULL(UP_20K)),
+
+	/* ------- GPIO Group GPP_G ------- */
+
+	/* GPP_G19 - SMI# */
+	/* DW0: 0x84000500, DW1: 0x00000000 */
+	_PAD_CFG_STRUCT(GPP_G19, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), 0),
+
+	/* ------- GPIO Community 2 ------- */
+
+	/* -------- GPIO Group GPD -------- */
+
+	/* GPD9 - SLP_WLAN# */
+	/* DW0: 0x04000600, DW1: 0x00000000 */
+	_PAD_CFG_STRUCT(GPD9, PAD_FUNC(NF1) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), 0),
+
+	/* ------- GPIO Community 3 ------- */
+
+	/* ------- GPIO Group GPP_I ------- */
+
+	/* GPP_I0 - DDPB_HPD0 */
+	/* DW0: 0x84000500, DW1: 0x00000000 */
+	_PAD_CFG_STRUCT(GPP_I0, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), 0),
+
+	/* GPP_I1 - DDPC_HPD1 */
+	/* DW0: 0x84000502, DW1: 0x00000000 */
+	_PAD_CFG_STRUCT(GPP_I1, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0),
+
+	/* GPP_I2 - DDPD_HPD2 */
+	/* DW0: 0x84000502, DW1: 0x00000000 */
+	_PAD_CFG_STRUCT(GPP_I2, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0),
+`
diff --git a/util/intelp2m/generator/testsuites/i3Uncheck.go b/util/intelp2m/generator/testsuites/i3Uncheck.go
new file mode 100644
index 0000000000..26f505eee7
--- /dev/null
+++ b/util/intelp2m/generator/testsuites/i3Uncheck.go
@@ -0,0 +1,111 @@
+package testsuites
+
+const ReferenceI3Uncheck string = `
+	/* ------- GPIO Community 0 ------- */
+
+	/* ------- GPIO Group GPP_A ------- */
+
+	/* GPP_A0 - RCIN# */
+	/* DW0: 0x84000502, DW1: 0x00000000 */
+	/* DW0: PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1) - IGNORED */
+	PAD_CFG_NF(GPP_A0, NONE, PLTRST, NF1),
+
+	/* GPP_A1 - LAD0 */
+	/* DW0: 0x84000402, DW1: 0x00003000 */
+	/* DW0: PAD_TRIG(OFF) | (1 << 1) - IGNORED */
+	PAD_CFG_NF(GPP_A1, UP_20K, PLTRST, NF1),
+
+	/* GPP_A5 - LFRAME# */
+	/* DW0: 0x84000600, DW1: 0x00000000 */
+	/* DW0: PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) - IGNORED */
+	PAD_CFG_NF(GPP_A5, NONE, PLTRST, NF1),
+
+	/* GPP_A13 - SUSWARN#/SUSPWRDNACK */
+	/* DW0: 0x44000600, DW1: 0x00000000 */
+	/* DW0: PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) - IGNORED */
+	PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1),
+
+	/* GPP_A23 - GPIO */
+	/* DW0: 0x84000102, DW1: 0x00000000 */
+	/* DW0: (1 << 1) - IGNORED */
+	PAD_CFG_GPI_TRIG_OWN(GPP_A23, NONE, PLTRST, OFF, ACPI),
+
+	/* ------- GPIO Group GPP_B ------- */
+
+	/* GPP_C1 - RESERVED */
+
+	/* GPP_B0 - GPIO */
+	/* DW0: 0x84000100, DW1: 0x00000000 */
+	PAD_CFG_GPI_TRIG_OWN(GPP_B0, NONE, PLTRST, OFF, ACPI),
+
+	/* GPP_B23 - PCHHOT# */
+	/* DW0: 0x84000a01, DW1: 0x00001000 */
+	/* DW0: PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1 - IGNORED */
+	PAD_CFG_NF(GPP_B23, DN_20K, PLTRST, NF2),
+
+	/* ------- GPIO Community 1 ------- */
+
+	/* ------- GPIO Group GPP_C ------- */
+
+	/* GPP_C0 - SMBCLK */
+	/* DW0: 0x44000502, DW1: 0x00000000 */
+	/* DW0: PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1) - IGNORED */
+	PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1),
+
+	/* GPP_C5 - GPIO */
+	/* DW0: 0x84000100, DW1: 0x00000000 */
+	PAD_CFG_GPI_TRIG_OWN(GPP_C5, NONE, PLTRST, OFF, ACPI),
+
+	/* GPP_C6 - RESERVED */
+
+	/* GPP_C7 - RESERVED */
+
+	/* GPP_C22 - UART2_RTS# */
+	/* DW0: 0x84000600, DW1: 0x00000000 */
+	/* DW0: PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) - IGNORED */
+	PAD_CFG_NF(GPP_C22, NONE, PLTRST, NF1),
+
+	/* ------- GPIO Group GPP_D ------- */
+
+	/* ------- GPIO Group GPP_E ------- */
+
+	/* GPP_E0 - SATAXPCIE0 */
+	/* DW0: 0x84000502, DW1: 0x00003000 */
+	/* DW0: PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1) - IGNORED */
+	PAD_CFG_NF(GPP_E0, UP_20K, PLTRST, NF1),
+
+	/* ------- GPIO Group GPP_G ------- */
+
+	/* GPP_G19 - SMI# */
+	/* DW0: 0x84000500, DW1: 0x00000000 */
+	/* DW0: PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) - IGNORED */
+	PAD_CFG_NF(GPP_G19, NONE, PLTRST, NF1),
+
+	/* ------- GPIO Community 2 ------- */
+
+	/* -------- GPIO Group GPD -------- */
+
+	/* GPD9 - SLP_WLAN# */
+	/* DW0: 0x04000600, DW1: 0x00000000 */
+	/* DW0: PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) - IGNORED */
+	PAD_CFG_NF(GPD9, NONE, PWROK, NF1),
+
+	/* ------- GPIO Community 3 ------- */
+
+	/* ------- GPIO Group GPP_I ------- */
+
+	/* GPP_I0 - DDPB_HPD0 */
+	/* DW0: 0x84000500, DW1: 0x00000000 */
+	/* DW0: PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) - IGNORED */
+	PAD_CFG_NF(GPP_I0, NONE, PLTRST, NF1),
+
+	/* GPP_I1 - DDPC_HPD1 */
+	/* DW0: 0x84000502, DW1: 0x00000000 */
+	/* DW0: PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1) - IGNORED */
+	PAD_CFG_NF(GPP_I1, NONE, PLTRST, NF1),
+
+	/* GPP_I2 - DDPD_HPD2 */
+	/* DW0: 0x84000502, DW1: 0x00000000 */
+	/* DW0: PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1) - IGNORED */
+	PAD_CFG_NF(GPP_I2, NONE, PLTRST, NF1),
+`
diff --git a/util/intelp2m/generator/testsuites/i4ExcludeUnusedCbFlds.go b/util/intelp2m/generator/testsuites/i4ExcludeUnusedCbFlds.go
new file mode 100644
index 0000000000..46f09995fc
--- /dev/null
+++ b/util/intelp2m/generator/testsuites/i4ExcludeUnusedCbFlds.go
@@ -0,0 +1,127 @@
+package testsuites
+
+const ReferenceI4ExcludeUnusedCbFlds string = `
+	/* ------- GPIO Community 0 ------- */
+
+	/* ------- GPIO Group GPP_A ------- */
+
+	/* GPP_A0 - RCIN# */
+	/* DW0: 0x84000502, DW1: 0x00000000 */
+	/* DW0: PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1) - IGNORED */
+	/* PAD_CFG_NF(GPP_A0, NONE, PLTRST, NF1), */
+	_PAD_CFG_STRUCT(GPP_A0, PAD_FUNC(NF1) | PAD_RESET(PLTRST), 0),
+
+	/* GPP_A1 - LAD0 */
+	/* DW0: 0x84000402, DW1: 0x00003000 */
+	/* DW0: PAD_TRIG(OFF) | (1 << 1) - IGNORED */
+	/* PAD_CFG_NF(GPP_A1, UP_20K, PLTRST, NF1), */
+	_PAD_CFG_STRUCT(GPP_A1, PAD_FUNC(NF1) | PAD_RESET(PLTRST), PAD_PULL(UP_20K)),
+
+	/* GPP_A5 - LFRAME# */
+	/* DW0: 0x84000600, DW1: 0x00000000 */
+	/* DW0: PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) - IGNORED */
+	/* PAD_CFG_NF(GPP_A5, NONE, PLTRST, NF1), */
+	_PAD_CFG_STRUCT(GPP_A5, PAD_FUNC(NF1) | PAD_RESET(PLTRST), 0),
+
+	/* GPP_A13 - SUSWARN#/SUSPWRDNACK */
+	/* DW0: 0x44000600, DW1: 0x00000000 */
+	/* DW0: PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) - IGNORED */
+	/* PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1), */
+	_PAD_CFG_STRUCT(GPP_A13, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),
+
+	/* GPP_A23 - GPIO */
+	/* DW0: 0x84000102, DW1: 0x00000000 */
+	/* DW0: (1 << 1) - IGNORED */
+	/* PAD_CFG_GPI_TRIG_OWN(GPP_A23, NONE, PLTRST, OFF, ACPI), */
+	_PAD_CFG_STRUCT(GPP_A23, PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), 0),
+
+	/* ------- GPIO Group GPP_B ------- */
+
+	/* GPP_C1 - RESERVED */
+
+	/* GPP_B0 - GPIO */
+	/* DW0: 0x84000100, DW1: 0x00000000 */
+	/* PAD_CFG_GPI_TRIG_OWN(GPP_B0, NONE, PLTRST, OFF, ACPI), */
+	_PAD_CFG_STRUCT(GPP_B0, PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), 0),
+
+	/* GPP_B23 - PCHHOT# */
+	/* DW0: 0x84000a01, DW1: 0x00001000 */
+	/* DW0: PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1 - IGNORED */
+	/* PAD_CFG_NF(GPP_B23, DN_20K, PLTRST, NF2), */
+	_PAD_CFG_STRUCT(GPP_B23, PAD_FUNC(NF2) | PAD_RESET(PLTRST), PAD_PULL(DN_20K)),
+
+	/* ------- GPIO Community 1 ------- */
+
+	/* ------- GPIO Group GPP_C ------- */
+
+	/* GPP_C0 - SMBCLK */
+	/* DW0: 0x44000502, DW1: 0x00000000 */
+	/* DW0: PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1) - IGNORED */
+	/* PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), */
+	_PAD_CFG_STRUCT(GPP_C0, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),
+
+	/* GPP_C5 - GPIO */
+	/* DW0: 0x84000100, DW1: 0x00000000 */
+	/* PAD_CFG_GPI_TRIG_OWN(GPP_C5, NONE, PLTRST, OFF, ACPI), */
+	_PAD_CFG_STRUCT(GPP_C5, PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), 0),
+
+	/* GPP_C6 - RESERVED */
+
+	/* GPP_C7 - RESERVED */
+
+	/* GPP_C22 - UART2_RTS# */
+	/* DW0: 0x84000600, DW1: 0x00000000 */
+	/* DW0: PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) - IGNORED */
+	/* PAD_CFG_NF(GPP_C22, NONE, PLTRST, NF1), */
+	_PAD_CFG_STRUCT(GPP_C22, PAD_FUNC(NF1) | PAD_RESET(PLTRST), 0),
+
+	/* ------- GPIO Group GPP_D ------- */
+
+	/* ------- GPIO Group GPP_E ------- */
+
+	/* GPP_E0 - SATAXPCIE0 */
+	/* DW0: 0x84000502, DW1: 0x00003000 */
+	/* DW0: PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1) - IGNORED */
+	/* PAD_CFG_NF(GPP_E0, UP_20K, PLTRST, NF1), */
+	_PAD_CFG_STRUCT(GPP_E0, PAD_FUNC(NF1) | PAD_RESET(PLTRST), PAD_PULL(UP_20K)),
+
+	/* ------- GPIO Group GPP_G ------- */
+
+	/* GPP_G19 - SMI# */
+	/* DW0: 0x84000500, DW1: 0x00000000 */
+	/* DW0: PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) - IGNORED */
+	/* PAD_CFG_NF(GPP_G19, NONE, PLTRST, NF1), */
+	_PAD_CFG_STRUCT(GPP_G19, PAD_FUNC(NF1) | PAD_RESET(PLTRST), 0),
+
+	/* ------- GPIO Community 2 ------- */
+
+	/* -------- GPIO Group GPD -------- */
+
+	/* GPD9 - SLP_WLAN# */
+	/* DW0: 0x04000600, DW1: 0x00000000 */
+	/* DW0: PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) - IGNORED */
+	/* PAD_CFG_NF(GPD9, NONE, PWROK, NF1), */
+	_PAD_CFG_STRUCT(GPD9, PAD_FUNC(NF1), 0),
+
+	/* ------- GPIO Community 3 ------- */
+
+	/* ------- GPIO Group GPP_I ------- */
+
+	/* GPP_I0 - DDPB_HPD0 */
+	/* DW0: 0x84000500, DW1: 0x00000000 */
+	/* DW0: PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) - IGNORED */
+	/* PAD_CFG_NF(GPP_I0, NONE, PLTRST, NF1), */
+	_PAD_CFG_STRUCT(GPP_I0, PAD_FUNC(NF1) | PAD_RESET(PLTRST), 0),
+
+	/* GPP_I1 - DDPC_HPD1 */
+	/* DW0: 0x84000502, DW1: 0x00000000 */
+	/* DW0: PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1) - IGNORED */
+	/* PAD_CFG_NF(GPP_I1, NONE, PLTRST, NF1), */
+	_PAD_CFG_STRUCT(GPP_I1, PAD_FUNC(NF1) | PAD_RESET(PLTRST), 0),
+
+	/* GPP_I2 - DDPD_HPD2 */
+	/* DW0: 0x84000502, DW1: 0x00000000 */
+	/* DW0: PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1) - IGNORED */
+	/* PAD_CFG_NF(GPP_I2, NONE, PLTRST, NF1), */
+	_PAD_CFG_STRUCT(GPP_I2, PAD_FUNC(NF1) | PAD_RESET(PLTRST), 0),
+`
diff --git a/util/intelp2m/main.go b/util/intelp2m/main.go
index a4b4b22941..84227a7b8d 100644
--- a/util/intelp2m/main.go
+++ b/util/intelp2m/main.go
@@ -3,28 +3,17 @@ package main
 import (
 	"fmt"
 	"os"
-	"path/filepath"
+	"time"
 
 	"review.coreboot.org/coreboot.git/util/intelp2m/cli"
 	"review.coreboot.org/coreboot.git/util/intelp2m/config/p2m"
+	"review.coreboot.org/coreboot.git/util/intelp2m/generator"
+	"review.coreboot.org/coreboot.git/util/intelp2m/generator/header"
+	"review.coreboot.org/coreboot.git/util/intelp2m/generator/printer"
 	"review.coreboot.org/coreboot.git/util/intelp2m/logs"
 	"review.coreboot.org/coreboot.git/util/intelp2m/parser"
 )
 
-type Printer struct{}
-
-func (Printer) Linef(lvl int, format string, args ...interface{}) {
-	if p2m.Config.GenLevel >= lvl {
-		fmt.Fprintf(p2m.Config.OutputFile, format, args...)
-	}
-}
-
-func (Printer) Line(lvl int, str string) {
-	if p2m.Config.GenLevel >= lvl {
-		fmt.Fprint(p2m.Config.OutputFile, str)
-	}
-}
-
 // Version is injected into main during project build
 var Version string = "Unknown"
 
@@ -41,55 +30,29 @@ func main() {
 		defer file.Close()
 	}
 
-	if file, err := os.Open(p2m.Config.InputPath); err != nil {
-		fmt.Printf("input file error: %v\n", err)
-		os.Exit(1)
-	} else {
-		p2m.Config.InputFile = file
-		defer file.Close()
-	}
+	year, month, day := time.Now().Date()
+	hour, min, sec := time.Now().Clock()
+	logs.Infof("%d-%d-%d %d:%d:%d", year, month, day, hour, min, sec)
+	logs.Infof("============ start ============")
 
-	if err := os.MkdirAll(filepath.Dir(p2m.Config.OutputPath), os.ModePerm); err != nil {
-		fmt.Printf("failed to create output directory: %v\n", err)
+	entries, err := parser.Run()
+	if err != nil {
+		fmt.Print("failed to run parser")
 		os.Exit(1)
 	}
-	if file, err := os.Create(p2m.Config.OutputPath); err != nil {
-		fmt.Printf("failed to create output file: %v\n", err)
-		os.Exit(1)
-	} else {
-		p2m.Config.OutputFile = file
-		defer file.Close()
-	}
 
-	logs.Infof("start %s", os.Args[0])
-
-	prs := parser.ParserData{}
-	prs.Parse()
-
-	generator := parser.Generator{
-		PrinterIf: Printer{},
-		Data:      &prs,
-	}
-	header := fmt.Sprintf(`/* SPDX-License-Identifier: GPL-2.0-only */
-
-#ifndef CFG_GPIO_H
-#define CFG_GPIO_H
-
-#include <gpio.h>
-
-/* Pad configuration was generated automatically using intelp2m %s */
-static const struct pad_config gpio_table[] = {`, Version)
-	p2m.Config.OutputFile.WriteString(header + "\n")
-	// Add the pads map
-
-	if err := generator.Run(); err != nil {
-		fmt.Printf("Error: %v", err)
+	lines, err := generator.Run(entries)
+	if err != nil {
+		fmt.Print("failed to run generator")
 		os.Exit(1)
 	}
-	p2m.Config.OutputFile.WriteString(`};
+	lines = header.Add(lines)
 
-#endif /* CFG_GPIO_H */
-`)
-	logs.Infof("exit from %s\n", os.Args[0])
+	if err := printer.Do(lines); err != nil {
+		fmt.Print("printer error")
+		os.Exit(1)
+	}
+
+	logs.Infof("========== completed ==========")
 	os.Exit(0)
 }
diff --git a/util/intelp2m/parser/parser.go b/util/intelp2m/parser/parser.go
index 4fd15a357d..b410912128 100644
--- a/util/intelp2m/parser/parser.go
+++ b/util/intelp2m/parser/parser.go
@@ -2,172 +2,127 @@ package parser
 
 import (
 	"bufio"
-	"errors"
 	"fmt"
+	"os"
+	"strings"
 
 	"review.coreboot.org/coreboot.git/util/intelp2m/config/p2m"
-	"review.coreboot.org/coreboot.git/util/intelp2m/platforms/adl"
-	"review.coreboot.org/coreboot.git/util/intelp2m/platforms/apl"
-	"review.coreboot.org/coreboot.git/util/intelp2m/platforms/cnl"
+	"review.coreboot.org/coreboot.git/util/intelp2m/logs"
+	"review.coreboot.org/coreboot.git/util/intelp2m/parser/template"
+	"review.coreboot.org/coreboot.git/util/intelp2m/platforms"
 	"review.coreboot.org/coreboot.git/util/intelp2m/platforms/common"
-	"review.coreboot.org/coreboot.git/util/intelp2m/platforms/ebg"
-	"review.coreboot.org/coreboot.git/util/intelp2m/platforms/jsl"
-	"review.coreboot.org/coreboot.git/util/intelp2m/platforms/lbg"
-	"review.coreboot.org/coreboot.git/util/intelp2m/platforms/mtl"
-	"review.coreboot.org/coreboot.git/util/intelp2m/platforms/snr"
-	"review.coreboot.org/coreboot.git/util/intelp2m/platforms/tgl"
+	"review.coreboot.org/coreboot.git/util/intelp2m/platforms/common/register/bits"
 )
 
-// PlatformSpecific - platform-specific interface
-type PlatformSpecific interface {
-	GenMacro(id string, dw0 uint32, dw1 uint32, ownership uint8) string
-	KeywordCheck(line string) bool
+type EntryType int
+
+const (
+	EntryEmpty EntryType = iota
+	EntryPad
+	EntryGroup
+	EntryReserved
+)
+
+// Parser entry
+// ID        : pad id string
+// Function  : the string that means the pad function
+// DW0       : DW0 register struct
+// DW1       : DW1 register struct
+// 0wnership : host software ownership
+type Entry struct {
+	EType     EntryType
+	ID        string
+	Function  string
+	DW0       uint32
+	DW1       uint32
+	Ownership uint8
 }
 
-// padInfo - information about pad
-// id        : pad id string
-// offset    : the offset of the register address relative to the base
-// function  : the string that means the pad function
-// dw0       : DW0 register value
-// dw1       : DW1 register value
-// ownership : host software ownership
-type padInfo struct {
-	id        string
-	offset    uint16
-	function  string
-	dw0       uint32
-	dw1       uint32
-	ownership uint8
+func (e *Entry) ToMacro() []string {
+	platform := platforms.GetSpecificInterface()
+	line := platform.GenMacro(e.ID, e.DW0, e.DW1, e.Ownership)
+	slices := strings.Split(line, "\n")
+	return slices
 }
 
-// ParserData - global data
-// line       : string from the configuration file
-// padmap     : pad info map
-// RawFmt     : flag for generating pads config file with DW0/1 reg raw values
-// Template   : structure template type of ConfigFile
-type ParserData struct {
-	platform  PlatformSpecific
-	line      string
-	padmap    []padInfo
-	ownership map[string]uint32
-}
-
-// padInfoExtract - adds a new entry to pad info map
-// return error status
-func (parser *ParserData) padInfoExtract() int {
-	var function, id string
-	var dw0, dw1 uint32
-	if rc := UseTemplate(parser.line, &function, &id, &dw0, &dw1); rc != 0 {
-		return rc
+// extractPad() extracts pad information from a string
+func extractPad(line string) (Entry, error) {
+	function, id, dw0, dw1, err := template.Apply(line)
+	if err != nil {
+		logs.Errorf("%v", err)
+		return Entry{EType: EntryEmpty}, err
 	}
-	pad := padInfo{id: id,
-		function:  function,
-		dw0:       dw0,
-		dw1:       dw1,
-		ownership: 0}
-	parser.padmap = append(parser.padmap, pad)
-	return 0
 
-}
-
-// communityGroupExtract
-func (parser *ParserData) communityGroupExtract() {
-	pad := padInfo{function: parser.line}
-	parser.padmap = append(parser.padmap, pad)
-}
-
-// PlatformSpecificInterfaceSet - specific interface for the platform selected
-// in the configuration
-func (parser *ParserData) PlatformSpecificInterfaceSet() {
-	platform := map[p2m.PlatformType]PlatformSpecific{
-		p2m.Sunrise: snr.PlatformSpecific{},
-		// See platforms/lbg/macro.go
-		p2m.Lewisburg: lbg.PlatformSpecific{
-			InheritanceTemplate: snr.PlatformSpecific{},
-		},
-		p2m.Apollo: apl.PlatformSpecific{},
-		p2m.Cannon: cnl.PlatformSpecific{
-			InheritanceTemplate: snr.PlatformSpecific{},
-		},
-		p2m.Tiger:  tgl.PlatformSpecific{},
-		p2m.Alder:  adl.PlatformSpecific{},
-		p2m.Jasper: jsl.PlatformSpecific{},
-		p2m.Meteor: mtl.PlatformSpecific{},
-		// See platforms/ebg/macro.go
-		p2m.Emmitsburg: ebg.PlatformSpecific{},
+	pad := Entry{
+		EType:     EntryPad,
+		Function:  function,
+		ID:        id,
+		DW0:       dw0,
+		DW1:       dw1,
+		Ownership: 0,
 	}
-	parser.platform = platform[p2m.Config.Platform]
+
+	if dw0 == bits.All32 {
+		pad.EType = EntryReserved
+	}
+
+	return pad, nil
 }
 
-// Parse pads groupe information in the inteltool log file
-// ConfigFile : name of inteltool log file
-func (parser *ParserData) Parse() {
-	// Read all lines from inteltool log file
-	fmt.Println("Parse IntelTool Log File...")
+// extractGroup() extracts information about the pad group from the string
+func extractGroup(line string) Entry {
+	group := Entry{
+		EType:    EntryGroup,
+		Function: line,
+	}
+	return group
+}
 
-	// determine the platform type and set the interface for it
-	parser.PlatformSpecificInterfaceSet()
+// Extract() extracts pad information from a string
+func Extract(line string, platform platforms.SpecificIf) Entry {
+	if included, _ := common.KeywordsCheck(line, "GPIO Community", "GPIO Group"); included {
+		return extractGroup(line)
+	}
 
-	// map of thepad ownership registers for the GPIO controller
-	parser.ownership = make(map[string]uint32)
+	if platform.KeywordCheck(line) {
+		pad, err := extractPad(line)
+		if err != nil {
+			logs.Errorf("extract pad info from %s: %v", line, err)
+			return Entry{EType: EntryEmpty}
+		}
+		return pad
+	}
+	logs.Infof("skip line <%s>", line)
+	return Entry{EType: EntryEmpty}
+}
 
-	file := p2m.Config.InputFile
+// Run() starts the file parsing process
+func Run() ([]Entry, error) {
+	entries := make([]Entry, 0)
+
+	platform := platforms.GetSpecificInterface()
+	if platform == nil {
+		return nil, fmt.Errorf("unknown platform")
+	}
+
+	file, err := os.Open(p2m.Config.InputPath)
+	if err != nil {
+		err = fmt.Errorf("input file error: %v", err)
+		logs.Errorf("%v", err)
+		return nil, err
+	}
+	defer file.Close()
+
+	logs.Infof("parse %s file", p2m.Config.InputPath)
 	scanner := bufio.NewScanner(file)
 	for scanner.Scan() {
-		parser.line = scanner.Text()
-		isIncluded, _ := common.KeywordsCheck(parser.line, "GPIO Community", "GPIO Group")
-		if isIncluded {
-			parser.communityGroupExtract()
-		} else if parser.platform.KeywordCheck(parser.line) {
-			if parser.padInfoExtract() != 0 {
-				fmt.Println("...error!")
-			}
+		line := scanner.Text()
+		entry := Extract(line, platform)
+		if entry.EType != EntryEmpty {
+			entries = append(entries, entry)
 		}
 	}
-	fmt.Println("...done!")
-}
 
-type PrinterIf interface {
-	Linef(lvl int, format string, args ...interface{})
-	Line(lvl int, str string)
-}
-
-type Generator struct {
-	Data      *ParserData // information from the parser
-	PrinterIf             // interface for printing
-}
-
-// Run - generate a new gpio file based on the information from the parser
-func (g Generator) Run() error {
-	if g.PrinterIf == nil && g.Data == nil {
-		return errors.New("Generator: Incorrect initialization")
-	}
-	for _, pad := range g.Data.padmap {
-		switch pad.dw0 {
-		case 0x00000000:
-			// titleFprint - print GPIO group title to file
-			// /* ------- GPIO Group GPP_L ------- */
-			g.Linef(0, "\n\t/* %s */\n", pad.function)
-		case 0xffffffff:
-			// reservedFprint - print reserved GPIO to file as comment
-			// /* GPP_H17 - RESERVED */
-			g.Line(2, "\n")
-			// small comment about reserved port
-			g.Linef(0, "\t/* %s - %s */\n", pad.id, pad.function)
-		default:
-			// padInfoMacroFprint - print information about current pad to file using
-			// special macros:
-			// PAD_CFG_NF(GPP_F1, 20K_PU, PLTRST, NF1), /* SATAXPCIE4 */
-			platform := g.Data.platform
-			macro := platform.GenMacro(pad.id, pad.dw0, pad.dw1, pad.ownership)
-			g.Linef(2, "\n\t/* %s - %s */\n\t/* DW0: 0x%0.8x, DW1: 0x%0.8x */\n",
-				pad.id, pad.function, pad.dw0, pad.dw1)
-			g.Linef(0, "\t%s", macro)
-			if p2m.Config.GenLevel == 1 {
-				g.Linef(1, "\t/* %s */", pad.function)
-			}
-			g.Line(0, "\n")
-		}
-	}
-	return nil
+	logs.Infof("successfully completed: %d entries", len(entries))
+	return entries, nil
 }
diff --git a/util/intelp2m/parser/parser_test.go b/util/intelp2m/parser/parser_test.go
index 5e59ade566..a628c673ea 100644
--- a/util/intelp2m/parser/parser_test.go
+++ b/util/intelp2m/parser/parser_test.go
@@ -1,102 +1,32 @@
 package parser_test
 
 import (
-	"fmt"
-	"os"
 	"testing"
 
 	"review.coreboot.org/coreboot.git/util/intelp2m/config/p2m"
 	"review.coreboot.org/coreboot.git/util/intelp2m/parser"
+	"review.coreboot.org/coreboot.git/util/intelp2m/parser/test"
 )
 
-const testLogFilePath = "test/inteltool_test.log"
-
-type Printer struct {
-	lines []string
-}
-
-func (p *Printer) Linef(lvl int, format string, args ...interface{}) {
-	if p2m.Config.GenLevel >= lvl {
-		p.lines = append(p.lines, fmt.Sprintf(format, args...))
-	}
-}
-
-func (p *Printer) Line(lvl int, str string) {
-	if p2m.Config.GenLevel >= lvl {
-		p.lines = append(p.lines, str)
-	}
-}
+const TestLogFilePath = "./testlog/inteltool_test.log"
 
 func TestParser(t *testing.T) {
 	t.Run("PARSER/PARSE-INTELTOOL-FILE", func(t *testing.T) {
-		var err error
-		reference := []string{
-			"\n\t/* ------- GPIO Community 0 ------- */\n",
-			"\n\t/* ------- GPIO Group GPP_A ------- */\n",
-			"\tPAD_CFG_NF(GPP_A0, NONE, PLTRST, NF1),", "\t/* RCIN# */", "\n",
-			"\tPAD_CFG_NF(GPP_A1, UP_20K, PLTRST, NF1),", "\t/* LAD0 */", "\n",
-			"\tPAD_CFG_NF(GPP_A5, NONE, PLTRST, NF1),", "\t/* LFRAME# */", "\n",
-			"\tPAD_CFG_NF(GPP_A13, NONE, DEEP, NF1),", "\t/* SUSWARN#/SUSPWRDNACK */", "\n",
-			"\tPAD_CFG_GPI_TRIG_OWN(GPP_A23, NONE, PLTRST, OFF, ACPI),", "\t/* GPIO */", "\n",
-			"\n\t/* ------- GPIO Group GPP_B ------- */\n",
-			"\t/* GPP_C1 - RESERVED */\n",
-			"\tPAD_CFG_GPI_TRIG_OWN(GPP_B0, NONE, PLTRST, OFF, ACPI),", "\t/* GPIO */", "\n",
-			"\tPAD_CFG_NF(GPP_B23, DN_20K, PLTRST, NF2),", "\t/* PCHHOT# */", "\n",
-			"\n\t/* ------- GPIO Community 1 ------- */\n",
-			"\n\t/* ------- GPIO Group GPP_C ------- */\n",
-			"\tPAD_CFG_NF(GPP_C0, NONE, DEEP, NF1),", "\t/* SMBCLK */", "\n",
-			"\tPAD_CFG_GPI_TRIG_OWN(GPP_C5, NONE, PLTRST, OFF, ACPI),", "\t/* GPIO */", "\n",
-			"\t/* GPP_C6 - RESERVED */\n",
-			"\t/* GPP_C7 - RESERVED */\n",
-			"\tPAD_CFG_NF(GPP_C22, NONE, PLTRST, NF1),", "\t/* UART2_RTS# */", "\n",
-			"\n\t/* ------- GPIO Group GPP_D ------- */\n",
-			"\n\t/* ------- GPIO Group GPP_E ------- */\n",
-			"\tPAD_CFG_NF(GPP_E0, UP_20K, PLTRST, NF1),", "\t/* SATAXPCIE0 */", "\n",
-			"\n\t/* ------- GPIO Group GPP_G ------- */\n",
-			"\tPAD_CFG_NF(GPP_G19, NONE, PLTRST, NF1),", "\t/* SMI# */", "\n",
-			"\n\t/* ------- GPIO Community 2 ------- */\n",
-			"\n\t/* -------- GPIO Group GPD -------- */\n",
-			"\tPAD_CFG_NF(GPD9, NONE, PWROK, NF1),", "\t/* SLP_WLAN# */", "\n",
-			"\n\t/* ------- GPIO Community 3 ------- */\n",
-			"\n\t/* ------- GPIO Group GPP_I ------- */\n",
-			"\tPAD_CFG_NF(GPP_I0, NONE, PLTRST, NF1),", "\t/* DDPB_HPD0 */", "\n",
-			"\tPAD_CFG_NF(GPP_I1, NONE, PLTRST, NF1),", "\t/* DDPC_HPD1 */", "\n",
-			"\tPAD_CFG_NF(GPP_I2, NONE, PLTRST, NF1),", "\t/* DDPD_HPD2 */", "\n",
-		}
-		if p2m.Config.InputFile, err = os.Open(testLogFilePath); err != nil {
-			t.Errorf("Something is wrong with the test file - %s!\n", testLogFilePath)
-			os.Exit(1)
-		}
-		defer p2m.Config.InputFile.Close()
 
 		p2m.Config.AutoCheck = false
 		p2m.Config.Field = p2m.NoFlds
 		p2m.Config.GenLevel = 1
+		p2m.Config.InputPath = TestLogFilePath
 
-		prs := parser.ParserData{}
-		prs.Parse()
-
-		printer := Printer{lines: make([]string, 0)}
-		generator := parser.Generator{
-			PrinterIf: &printer,
-			Data:      &prs,
+		entries, err := parser.Run()
+		if err != nil {
+			t.Errorf("failed to run parser: %v", err)
 		}
 
-		if err := generator.Run(); err != nil {
-			t.Errorf("Generator: %v", err)
-			os.Exit(1)
-		}
-
-		if len(printer.lines) == len(reference) {
-			for i := range printer.lines {
-				if printer.lines[i] != reference[i] {
-					t.Errorf("\nExpects:  '%s'\nActually: '%s'\n\n", reference[i], printer.lines[i])
-					return
-				}
+		for i := range test.Suite {
+			if entries[i] != test.Suite[i] {
+				t.Errorf("\nExpects:  '%v'\nActually: '%v'\n\n", test.Suite[i], entries[i])
 			}
-		} else {
-			t.Errorf("%d does not match the reference slice len - %d!",
-				len(reference), len(printer.lines))
 		}
 	})
 }
diff --git a/util/intelp2m/parser/template.go b/util/intelp2m/parser/template.go
deleted file mode 100644
index 7d3e1aa819..0000000000
--- a/util/intelp2m/parser/template.go
+++ /dev/null
@@ -1,64 +0,0 @@
-package parser
-
-import (
-	"fmt"
-	"strings"
-	"unicode"
-)
-
-const IntSelMask uint32 = 0xffffff00
-
-type template func(string, *string, *string, *uint32, *uint32) int
-
-// extractPadFuncFromComment
-// line   : string from file with pad config map
-// return : pad function string
-func extractPadFuncFromComment(line string) string {
-	if !strings.Contains(line, "/*") && !strings.Contains(line, "*/") {
-		return ""
-	}
-
-	fields := strings.Fields(line)
-	for i, field := range fields {
-		if field == "/*" && len(fields) >= i+2 {
-			return fields[i+1]
-		}
-	}
-	return ""
-}
-
-// tokenCheck
-func tokenCheck(c rune) bool {
-	return c != '_' && c != '#' && !unicode.IsLetter(c) && !unicode.IsNumber(c)
-}
-
-// UseTemplate
-// line      : string from file with pad config map
-// *function : the string that means the pad function
-// *id       : pad id string
-// *dw0      : DW0 register value
-// *dw1      : DW1 register value
-//
-// return
-// error status
-func UseTemplate(line string, function *string, id *string, dw0 *uint32, dw1 *uint32) int {
-	var val uint64
-	// 0x0520: 0x0000003c44000600 GPP_B12  SLP_S0#
-	// 0x0438: 0xffffffffffffffff GPP_C7   RESERVED
-	if fields := strings.FieldsFunc(line, tokenCheck); len(fields) >= 4 {
-		fmt.Sscanf(fields[1], "0x%x", &val)
-		*dw0 = uint32(val & 0xffffffff)
-		*dw1 = uint32(val >> 32)
-		*id = fields[2]
-		*function = fields[3]
-		// Sometimes the configuration file contains compound functions such as
-		// SUSWARN#/SUSPWRDNACK. Since the template does not take this into account,
-		// need to collect all parts of the pad function back into a single word
-		for i := 4; i < len(fields); i++ {
-			*function += "/" + fields[i]
-		}
-		// clear RO Interrupt Select (INTSEL)
-		*dw1 &= IntSelMask
-	}
-	return 0
-}
diff --git a/util/intelp2m/parser/template/template.go b/util/intelp2m/parser/template/template.go
new file mode 100644
index 0000000000..95dfa4272d
--- /dev/null
+++ b/util/intelp2m/parser/template/template.go
@@ -0,0 +1,48 @@
+package template
+
+import (
+	"fmt"
+	"strings"
+	"unicode"
+
+	"review.coreboot.org/coreboot.git/util/intelp2m/logs"
+	"review.coreboot.org/coreboot.git/util/intelp2m/platforms/common/register/bits"
+)
+
+func token(c rune) bool {
+	return c != '_' && c != '#' && !unicode.IsLetter(c) && !unicode.IsNumber(c)
+}
+
+// Apply
+// line     : string from file with pad config map
+// return
+// function : the string that means the pad function
+// id       : pad id string
+// dw0      : DW0 register value
+// dw1      : DW1 register value
+// err      : error
+func Apply(line string) (function string, id string, dw0 uint32, dw1 uint32, err error) {
+	// 0x0520: 0x0000003c44000600 GPP_B12  SLP_S0#
+	// 0x0438: 0xffffffffffffffff GPP_C7   RESERVED
+	slices := strings.FieldsFunc(line, token)
+	number := len(slices)
+	if number >= 4 {
+		var val uint64
+		fmt.Sscanf(slices[1], "0x%x", &val)
+		dw0 = uint32(val & 0xffffffff)
+		dw1 = uint32(val >> 32)
+		id = slices[2]
+		function = slices[3]
+		// Sometimes the configuration file contains compound functions such as
+		// SUSWARN#/SUSPWRDNACK. Since the template does not take this into account,
+		// need to collect all parts of the pad function back into a single word
+		for i := 4; i < len(slices); i++ {
+			function += "/" + slices[i]
+		}
+		// clear RO Interrupt Select (INTSEL)
+		dw1 &^= bits.DW1[bits.DW1InterruptSelect]
+		return function, id, dw0, dw1, nil
+	}
+	logs.Errorf("template: more than %d elements are needed", number)
+	return "", "", 0, 0, fmt.Errorf("template error")
+}
diff --git a/util/intelp2m/parser/template_test.go b/util/intelp2m/parser/template/template_test.go
similarity index 60%
rename from util/intelp2m/parser/template_test.go
rename to util/intelp2m/parser/template/template_test.go
index 9abdd72f83..76fe98ab09 100644
--- a/util/intelp2m/parser/template_test.go
+++ b/util/intelp2m/parser/template/template_test.go
@@ -1,26 +1,30 @@
-package parser_test
+package template_test
 
 import (
 	"fmt"
 	"testing"
 
-	"review.coreboot.org/coreboot.git/util/intelp2m/parser"
+	"review.coreboot.org/coreboot.git/util/intelp2m/parser/template"
 )
 
 func TestTemp(t *testing.T) {
 	t.Run("TEMPLATE/INTELTOOL-LINE", func(t *testing.T) {
 		const (
-			ref_fn  string = "SLP_S0#"
-			ref_id  string = "GPP_B12"
-			ref_dw0 uint32 = 0x44000600
-			ref_dw1 uint32 = 0x0000003c
+			IntSelMask uint32 = 0xffffff00
+			ref_fn     string = "SLP_S0#"
+			ref_id     string = "GPP_B12"
+			ref_dw0    uint32 = 0x44000600
+			ref_dw1    uint32 = 0x0000003c
 		)
 		var (
 			fn, id   string
 			dw0, dw1 uint32
 		)
 		line := fmt.Sprintf("0x0520: 0x%08x%08x %s %s", ref_dw1, ref_dw0, ref_id, ref_fn)
-		_ = parser.UseTemplate(line, &fn, &id, &dw0, &dw1)
+		fn, id, dw0, dw1, err := template.Apply(line)
+		if err != nil {
+			t.Errorf("template application failure: %d", err)
+		}
 		if fn != ref_fn {
 			t.Errorf("function from '%s':\nExpects:  '%s'\nActually: '%s'\n\n",
 				line, ref_fn, fn)
@@ -30,9 +34,9 @@ func TestTemp(t *testing.T) {
 		} else if dw0 != ref_dw0 {
 			t.Errorf("dw0 from '%s':\nExpects:  '0x%08x'\nActually: '0x%08x'\n\n",
 				line, ref_dw0, dw0)
-		} else if dw1 != (ref_dw1 & parser.IntSelMask) {
+		} else if dw1 != (ref_dw1 & IntSelMask) {
 			t.Errorf("dw1 from '%s':\nExpects:  '0x%08x'\nActually: '0x%08x'\n\n",
-				line, (ref_dw1 & parser.IntSelMask), dw1)
+				line, (ref_dw1 & IntSelMask), dw1)
 		}
 	})
 }
diff --git a/util/intelp2m/parser/test/suite.go b/util/intelp2m/parser/test/suite.go
new file mode 100644
index 0000000000..1a96b4fa41
--- /dev/null
+++ b/util/intelp2m/parser/test/suite.go
@@ -0,0 +1,152 @@
+package test
+
+import (
+	"review.coreboot.org/coreboot.git/util/intelp2m/parser"
+)
+
+var Suite = []parser.Entry{
+	// {2  ------- GPIO Community 0 ------- 00000000 00000000 0}
+	{EType: parser.EntryGroup, Function: "------- GPIO Community 0 -------"},
+	// {2  ------- GPIO Group GPP_A ------- 00000000 00000000 0}
+	{EType: parser.EntryGroup, Function: "------- GPIO Group GPP_A -------"},
+	{ // {1 GPP_A0 RCIN# 84000502 00000000 0}
+		EType:    parser.EntryPad,
+		Function: "RCIN#",
+		ID:       "GPP_A0",
+		DW0:      0x84000502,
+	},
+	{ // {1 GPP_A1 LAD0 84000402 00003000 0}
+		EType:    parser.EntryPad,
+		Function: "LAD0",
+		ID:       "GPP_A1",
+		DW0:      0x84000402,
+		DW1:      0x00003000,
+	},
+	{ // {1 GPP_A5 LFRAME# 84000600 00000000 0}
+		EType:    parser.EntryPad,
+		Function: "LFRAME#",
+		ID:       "GPP_A5",
+		DW0:      0x84000600,
+	},
+	{ // {1 GPP_A13 SUSWARN#/SUSPWRDNACK 44000600 00000000 0}
+		EType:    parser.EntryPad,
+		Function: "SUSWARN#/SUSPWRDNACK",
+		ID:       "GPP_A13",
+		DW0:      0x44000600,
+	},
+	{ // {1 GPP_A23 GPIO 84000102 00000000 0}
+		EType:    parser.EntryPad,
+		Function: "GPIO",
+		ID:       "GPP_A23",
+		DW0:      0x84000102,
+	},
+	// {2  ------- GPIO Group GPP_B ------- 00000000 00000000 0}
+	{EType: parser.EntryGroup, Function: "------- GPIO Group GPP_B -------"},
+	{ // {3 GPP_C1 RESERVED ffffffff ffffff00 0}
+		EType:    parser.EntryReserved,
+		Function: "RESERVED",
+		ID:       "GPP_C1",
+		DW0:      0xffffffff,
+		DW1:      0xffffff00,
+	},
+	{ // {1 GPP_B0 GPIO 84000100 00000000 0}
+		EType:    parser.EntryPad,
+		Function: "GPIO",
+		ID:       "GPP_B0",
+		DW0:      0x84000100,
+	},
+	{ // {1 GPP_B23 PCHHOT# 84000a01 00001000 0}
+		EType:    parser.EntryPad,
+		Function: "PCHHOT#",
+		ID:       "GPP_B23",
+		DW0:      0x84000a01,
+		DW1:      0x00001000,
+	},
+	// {2  ------- GPIO Community 1 ------- 00000000 00000000 0}
+	{EType: parser.EntryGroup, Function: "------- GPIO Community 1 -------"},
+	// {2  ------- GPIO Group GPP_C ------- 00000000 00000000 0}
+	{EType: parser.EntryGroup, Function: "------- GPIO Group GPP_C -------"},
+	{ // {1 GPP_C0 SMBCLK 44000502 00000000 0}
+		EType:    parser.EntryPad,
+		Function: "SMBCLK",
+		ID:       "GPP_C0",
+		DW0:      0x44000502,
+	},
+	{ // {1 GPP_C5 GPIO 84000100 00000000 0}
+		EType:    parser.EntryPad,
+		Function: "GPIO",
+		ID:       "GPP_C5",
+		DW0:      0x84000100,
+	},
+	{ // {3 GPP_C6 RESERVED ffffffff ffffff00 0}
+		EType:    parser.EntryReserved,
+		Function: "RESERVED",
+		ID:       "GPP_C6",
+		DW0:      0xffffffff,
+		DW1:      0xffffff00,
+	},
+	{ // {3 GPP_C7 RESERVED ffffffff ffffff00 0}
+		EType:    parser.EntryReserved,
+		Function: "RESERVED",
+		ID:       "GPP_C7",
+		DW0:      0xffffffff,
+		DW1:      0xffffff00,
+	},
+	{ // {1 GPP_C22 UART2_RTS# 84000600 00000000 0}
+		EType:    parser.EntryPad,
+		Function: "UART2_RTS#",
+		ID:       "GPP_C22",
+		DW0:      0x84000600,
+	},
+	// {2  ------- GPIO Group GPP_D ------- 00000000 00000000 0}
+	{EType: parser.EntryGroup, Function: "------- GPIO Group GPP_D -------"},
+	// {2  ------- GPIO Group GPP_E ------- 00000000 00000000 0}
+	{EType: parser.EntryGroup, Function: "------- GPIO Group GPP_E -------"},
+	{ // {1 GPP_E0 SATAXPCIE0 84000502 00003000 0}
+		EType:    parser.EntryPad,
+		Function: "SATAXPCIE0",
+		ID:       "GPP_E0",
+		DW0:      0x84000502,
+		DW1:      0x00003000,
+	},
+	// {2  ------- GPIO Group GPP_G ------- 00000000 00000000 0}
+	{EType: parser.EntryGroup, Function: "------- GPIO Group GPP_G -------"},
+	{ // {1 GPP_G19 SMI# 84000500 00000000 0}
+		EType:    parser.EntryPad,
+		Function: "SMI#",
+		ID:       "GPP_G19",
+		DW0:      0x84000500,
+	},
+	// {2  ------- GPIO Community 2 ------- 00000000 00000000 0}
+	{EType: parser.EntryGroup, Function: "------- GPIO Community 2 -------"},
+	// {2  -------- GPIO Group GPD -------- 00000000 00000000 0}
+	{EType: parser.EntryGroup, Function: "-------- GPIO Group GPD --------"},
+	{ // {1 GPD9 SLP_WLAN# 04000600 00000000 0}
+		EType:    parser.EntryPad,
+		Function: "SLP_WLAN#",
+		ID:       "GPD9",
+		DW0:      0x04000600,
+	},
+	// {2  ------- GPIO Community 3 ------- 00000000 00000000 0}
+	{EType: parser.EntryGroup, Function: "------- GPIO Community 3 -------"},
+	// {2  ------- GPIO Group GPP_I ------- 00000000 00000000 0}
+	{EType: parser.EntryGroup, Function: "------- GPIO Group GPP_I -------"},
+	{ // {1 GPP_I0 DDPB_HPD0 84000500 00000000 0}
+		EType:    parser.EntryPad,
+		Function: "DDPB_HPD0",
+		ID:       "GPP_I0",
+		DW0:      0x84000500,
+	},
+	{ // {1 GPP_I1 DDPC_HPD1 84000502 00000000 0}
+		EType:    parser.EntryPad,
+		Function: "DDPC_HPD1",
+		ID:       "GPP_I1",
+		DW0:      0x84000502,
+	},
+	{ // {1 GPP_I2 DDPD_HPD2 84000502 00000000 0}
+		EType:    parser.EntryPad,
+		Function: "DDPD_HPD2",
+		ID:       "GPP_I2",
+		DW0:      0x84000502,
+	},
+}
diff --git a/util/intelp2m/parser/test/inteltool_test.log b/util/intelp2m/parser/testlog/inteltool_test.log
similarity index 100%
rename from util/intelp2m/parser/test/inteltool_test.log
rename to util/intelp2m/parser/testlog/inteltool_test.log
diff --git a/util/intelp2m/platforms/common/macro.go b/util/intelp2m/platforms/common/macro.go
index 782a61e5b7..56b147cee2 100644
--- a/util/intelp2m/platforms/common/macro.go
+++ b/util/intelp2m/platforms/common/macro.go
@@ -289,7 +289,7 @@ func (macro *Macro) DecodeIgnoredFieldsDW0() *Macro {
 		dw0.Value = ignored
 		macro.Add("/* DW0: ")
 		macro.Fields.DecodeDW0()
-		macro.Add(" - IGNORED */\n\t")
+		macro.Add(" - IGNORED */\n")
 		dw0.Value = saved
 	}
 	return macro
@@ -305,7 +305,7 @@ func (macro *Macro) DecodeIgnoredFieldsDW1() *Macro {
 		dw1.Value = ignored
 		macro.Add("/* DW0: ")
 		macro.DecodeDW1()
-		macro.Add(" - IGNORED */\n\t")
+		macro.Add(" - IGNORED */\n")
 		dw1.Value = saved
 	}
 	return macro
@@ -332,7 +332,7 @@ func (macro *Macro) GenerateFields() *Macro {
 		macro.DecodeIgnoredFieldsDW1()
 		if p2m.Config.GenLevel >= 4 {
 			/* PAD_CFG_NF(GPP_B23, 20K_PD, PLTRST, NF2), */
-			macro.Add("/* ").Add(reference).Add(" */\n\t")
+			macro.Add("/* ").Add(reference).Add(" */\n")
 		}
 	}
 	if p2m.Config.IgnoredFields {
@@ -408,7 +408,7 @@ func (macro *Macro) Generate() string {
 			if p2m.Config.GenLevel >= 4 {
 				macro.Clear().Add("/* ")
 				macro.Fields.GenerateString()
-				macro.Add(" */\n\t")
+				macro.Add(" */\n")
 				comment += macro.Get()
 			}
 			return comment + body
diff --git a/util/intelp2m/platforms/interfaces.go b/util/intelp2m/platforms/interfaces.go
new file mode 100644
index 0000000000..455da26cd7
--- /dev/null
+++ b/util/intelp2m/platforms/interfaces.go
@@ -0,0 +1,38 @@
+package platforms
+
+import (
+	"review.coreboot.org/coreboot.git/util/intelp2m/config/p2m"
+	"review.coreboot.org/coreboot.git/util/intelp2m/logs"
+	"review.coreboot.org/coreboot.git/util/intelp2m/platforms/adl"
+	"review.coreboot.org/coreboot.git/util/intelp2m/platforms/apl"
+	"review.coreboot.org/coreboot.git/util/intelp2m/platforms/cnl"
+	"review.coreboot.org/coreboot.git/util/intelp2m/platforms/lbg"
+	"review.coreboot.org/coreboot.git/util/intelp2m/platforms/snr"
+)
+
+type SpecificIf interface {
+	GenMacro(id string, dw0 uint32, dw1 uint32, ownership uint8) string
+	KeywordCheck(line string) bool
+}
+
+func GetSpecificInterface() SpecificIf {
+	platforms := map[p2m.PlatformType]SpecificIf{
+		p2m.Alder:   adl.PlatformSpecific{},
+		p2m.Apollo:  apl.PlatformSpecific{},
+		p2m.Sunrise: snr.PlatformSpecific{},
+		p2m.Cannon: cnl.PlatformSpecific{
+			InheritanceTemplate: snr.PlatformSpecific{},
+			InheritanceMacro:    snr.PlatformSpecific{},
+		},
+		p2m.Lewisburg: lbg.PlatformSpecific{
+			InheritanceTemplate: snr.PlatformSpecific{},
+			InheritanceMacro:    snr.PlatformSpecific{},
+		},
+	}
+	platform, exist := platforms[p2m.Config.Platform]
+	if !exist {
+		logs.Errorf("unknown platform type %d", int(p2m.Config.Platform))
+		return nil
+	}
+	return platform
+}

From 85054dbccb2cd38b4a40b04819cebbf6ab50b333 Mon Sep 17 00:00:00 2001
From: Maxim Polyakov <max.senia.poliak@gmail.com>
Date: Tue, 20 Dec 2022 21:00:45 +0300
Subject: [PATCH 0255/3886] util/intelp2m: Rework platforms and fields packages

- embed the base platform and redefine its methods if they differ;
- separate the macro structures from the platform;
- move more functions to common;
- undo use of a single global instance of the microstructure.

TEST:
1) 'make test' = PASS
2) './intelp2m -p cnl -iiii -file inteltool.log' = gpio.h before and
   after the commit is the same.

Change-Id: I2e0aa56efa2430ac6524c6977f8b6fd13113edf9
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71167
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 util/intelp2m/fields/cb/cb.go                 |  32 +-
 util/intelp2m/fields/cb/cb_test.go            |   6 +-
 util/intelp2m/fields/fields.go                |  12 +-
 util/intelp2m/fields/fsp/fsp.go               |  55 +--
 util/intelp2m/fields/fsp/fsp_test.go          |   6 +-
 util/intelp2m/fields/raw/raw.go               |  33 +-
 util/intelp2m/fields/raw/raw_test.go          |   6 +-
 util/intelp2m/fields/test/suite.go            |  28 +-
 util/intelp2m/parser/parser.go                |  31 +-
 util/intelp2m/platforms/adl/adl_test.go       |  41 +-
 util/intelp2m/platforms/adl/macro.go          | 112 ++---
 util/intelp2m/platforms/adl/template.go       |  14 +-
 util/intelp2m/platforms/apl/apl_test.go       |  53 +-
 util/intelp2m/platforms/apl/macro.go          | 256 +++++-----
 util/intelp2m/platforms/apl/template.go       |   7 +-
 util/intelp2m/platforms/cnl/cnl_test.go       |  38 +-
 util/intelp2m/platforms/cnl/macro.go          | 200 +++-----
 util/intelp2m/platforms/cnl/template.go       |  17 +-
 util/intelp2m/platforms/common/common.go      |  25 +
 util/intelp2m/platforms/common/macro.go       | 453 +++++++++---------
 .../platforms/common/register/helper.go       |   5 +
 util/intelp2m/platforms/ebg/ebg_test.go       |  41 +-
 util/intelp2m/platforms/ebg/macro.go          | 108 +----
 util/intelp2m/platforms/ebg/template.go       |   4 +-
 util/intelp2m/platforms/interfaces.go         |  38 --
 util/intelp2m/platforms/jsl/jsl_test.go       |  41 +-
 util/intelp2m/platforms/jsl/macro.go          | 118 ++---
 util/intelp2m/platforms/jsl/template.go       |   4 +-
 util/intelp2m/platforms/lbg/lbg_test.go       |  56 +--
 util/intelp2m/platforms/lbg/macro.go          | 105 +---
 util/intelp2m/platforms/lbg/template.go       |  19 +-
 util/intelp2m/platforms/mtl/macro.go          | 111 ++---
 util/intelp2m/platforms/mtl/mtl_test.go       |  41 +-
 util/intelp2m/platforms/mtl/template.go       |   4 +-
 util/intelp2m/platforms/platforms.go          |  62 +++
 util/intelp2m/platforms/snr/macro.go          | 231 ++++-----
 util/intelp2m/platforms/snr/snr_test.go       |  65 +--
 util/intelp2m/platforms/snr/template.go       |  13 +-
 util/intelp2m/platforms/test/suite.go         |  46 +-
 util/intelp2m/platforms/tgl/macro.go          | 109 +----
 util/intelp2m/platforms/tgl/template.go       |   4 +-
 util/intelp2m/platforms/tgl/tgl_test.go       |  45 +-
 42 files changed, 1126 insertions(+), 1569 deletions(-)
 create mode 100644 util/intelp2m/platforms/common/common.go
 create mode 100644 util/intelp2m/platforms/common/register/helper.go
 delete mode 100644 util/intelp2m/platforms/interfaces.go
 create mode 100644 util/intelp2m/platforms/platforms.go

diff --git a/util/intelp2m/fields/cb/cb.go b/util/intelp2m/fields/cb/cb.go
index f6a1411356..80dceafce2 100644
--- a/util/intelp2m/fields/cb/cb.go
+++ b/util/intelp2m/fields/cb/cb.go
@@ -5,7 +5,7 @@ import (
 	"review.coreboot.org/coreboot.git/util/intelp2m/platforms/common"
 )
 
-type FieldMacros struct{}
+type FieldCollection struct{}
 
 // field - data structure for creating a new bitfield macro object
 // PAD_FUNC(NF3)
@@ -22,8 +22,7 @@ type field struct {
 
 // generate - wrapper for generating bitfield macros string
 // fields : field structure
-func generate(fields ...*field) {
-	macro := common.GetMacro()
+func generate(macro *common.Macro, fields ...*field) {
 	var allhidden bool = true
 	for _, field := range fields {
 		if field.unhide {
@@ -48,10 +47,9 @@ func generate(fields ...*field) {
 }
 
 // DecodeDW0 - decode value of DW0 register
-func (FieldMacros) DecodeDW0() {
-	macro := common.GetMacro()
-	dw0 := macro.GetRegisterDW0()
-	generate(
+func (FieldCollection) DecodeDW0(macro *common.Macro) *common.Macro {
+	dw0 := macro.Platform.GetRegisterDW0()
+	generate(macro,
 		&field{
 			prefix: "PAD_FUNC",
 			// TODO: Find another way to hide PAD_FUNC(GPIO) in the comment with
@@ -128,13 +126,13 @@ func (FieldMacros) DecodeDW0() {
 			unhide: dw0.GetGPIOTXState() != 0,
 		},
 	)
+	return macro
 }
 
 // DecodeDW1 - decode value of DW1 register
-func (FieldMacros) DecodeDW1() {
-	macro := common.GetMacro()
-	dw1 := macro.GetRegisterDW1()
-	generate(
+func (FieldCollection) DecodeDW1(macro *common.Macro) *common.Macro {
+	dw1 := macro.Platform.GetRegisterDW1()
+	generate(macro,
 		&field{
 			name:   "PAD_CFG1_TOL_1V8",
 			unhide: dw1.GetPadTol() != 0,
@@ -164,14 +162,12 @@ func (FieldMacros) DecodeDW1() {
 			configurator: func() { macro.Own() },
 		},
 	)
+	return macro
 }
 
-// GenerateString - generates the entire string of bitfield macros.
-func (bitfields FieldMacros) GenerateString() {
-	macro := common.GetMacro()
+// GenerateMacro generates the field macro collection
+func (f FieldCollection) GenerateMacro(macro *common.Macro) *common.Macro {
 	macro.Add("_PAD_CFG_STRUCT(").Id().Add(", ")
-	bitfields.DecodeDW0()
-	macro.Add(", ")
-	bitfields.DecodeDW1()
-	macro.Add("),")
+	f.DecodeDW0(macro).Add(", ")
+	return f.DecodeDW1(macro).Add("),")
 }
diff --git a/util/intelp2m/fields/cb/cb_test.go b/util/intelp2m/fields/cb/cb_test.go
index 64d735e2b7..e553551199 100644
--- a/util/intelp2m/fields/cb/cb_test.go
+++ b/util/intelp2m/fields/cb/cb_test.go
@@ -3,13 +3,15 @@ package cb_test
 import (
 	"testing"
 
-	"review.coreboot.org/coreboot.git/util/intelp2m/fields/cb"
+	"review.coreboot.org/coreboot.git/util/intelp2m/config/p2m"
 	"review.coreboot.org/coreboot.git/util/intelp2m/fields/test"
 )
 
 // sliding-one
 
 func TestCbFields(t *testing.T) {
+	p2m.SettingsReset()
+	p2m.Config.Field = p2m.CbFlds
 	referenceSlice := []string{
 		"_PAD_CFG_STRUCT(, PAD_FUNC(GPIO) | PAD_RESET(PLTRST), 0),",
 		"_PAD_CFG_STRUCT(, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),",
@@ -44,5 +46,5 @@ func TestCbFields(t *testing.T) {
 		"_PAD_CFG_STRUCT(, PAD_FUNC(GPIO) | (1 << 1), 0),",
 		"_PAD_CFG_STRUCT(, PAD_FUNC(GPIO) | 1, 0),",
 	}
-	test.SlidingOneTestSuiteCreate(referenceSlice).Run(t, "SLIDING-ONE-TEST", cb.FieldMacros{})
+	test.SlidingOneTestSuiteCreate(referenceSlice).Run(t, "SLIDING-ONE-TEST")
 }
diff --git a/util/intelp2m/fields/fields.go b/util/intelp2m/fields/fields.go
index 4e41aff4ca..19074f9ad1 100644
--- a/util/intelp2m/fields/fields.go
+++ b/util/intelp2m/fields/fields.go
@@ -10,12 +10,12 @@ import (
 
 // InterfaceSet - set the interface for decoding configuration
 // registers DW0 and DW1.
-func InterfaceGet() common.Fields {
-	var fldstylemap = map[p2m.FieldType]common.Fields{
-		p2m.NoFlds:  cb.FieldMacros{}, // analyze fields using cb macros
-		p2m.CbFlds:  cb.FieldMacros{},
-		p2m.FspFlds: fsp.FieldMacros{},
-		p2m.RawFlds: raw.FieldMacros{},
+func Get() common.FieldsIf {
+	var fldstylemap = map[p2m.FieldType]common.FieldsIf{
+		p2m.NoFlds:  cb.FieldCollection{}, // analyze fields using cb macros
+		p2m.CbFlds:  cb.FieldCollection{},
+		p2m.FspFlds: fsp.FieldCollection{},
+		p2m.RawFlds: raw.FieldCollection{},
 	}
 	return fldstylemap[p2m.Config.Field]
 }
diff --git a/util/intelp2m/fields/fsp/fsp.go b/util/intelp2m/fields/fsp/fsp.go
index db6b4ad294..e8d140af07 100644
--- a/util/intelp2m/fields/fsp/fsp.go
+++ b/util/intelp2m/fields/fsp/fsp.go
@@ -2,7 +2,7 @@ package fsp
 
 import "review.coreboot.org/coreboot.git/util/intelp2m/platforms/common"
 
-type FieldMacros struct{}
+type FieldCollection struct{}
 
 // field - data structure for creating a new bitfield macro object
 // configmap : map to select the current configuration
@@ -14,10 +14,8 @@ type field struct {
 	override  func(configuration map[uint32]string, value uint32)
 }
 
-// generate - wrapper for generating bitfield macros string
-// fields : field structure
-func generate(fields ...*field) {
-	macro := common.GetMacro()
+// generate() generates bitfield macro data struct
+func generate(macro *common.Macro, fields ...*field) {
 	for _, field := range fields {
 		if field.override != nil {
 			// override if necessary
@@ -35,9 +33,8 @@ func generate(fields ...*field) {
 }
 
 // DecodeDW0 - decode value of DW0 register
-func (FieldMacros) DecodeDW0() {
-	macro := common.GetMacro()
-	dw0 := macro.GetRegisterDW0()
+func (FieldCollection) DecodeDW0(macro *common.Macro) *common.Macro {
+	dw0 := macro.Platform.GetRegisterDW0()
 
 	ownershipStatus := func() uint32 {
 		if macro.IsOwnershipDriver() {
@@ -46,7 +43,7 @@ func (FieldMacros) DecodeDW0() {
 		return 0
 	}
 
-	generate(
+	generate(macro,
 		&field{
 			configmap: map[uint32]string{
 				0: "GpioPadModeGpio",
@@ -131,13 +128,13 @@ func (FieldMacros) DecodeDW0() {
 			value: dw0.GetResetConfig(),
 		},
 	)
+	return macro
 }
 
-// DecodeDW1 - decode value of DW1 register
-func (FieldMacros) DecodeDW1() {
-	macro := common.GetMacro()
-	dw1 := macro.GetRegisterDW1()
-	generate(
+// DecodeDW1() decodes DW1 register value and adds it to the macro string
+func (FieldCollection) DecodeDW1(macro *common.Macro) *common.Macro {
+	dw1 := macro.Platform.GetRegisterDW1()
+	generate(macro,
 		&field{
 			override: func(configmap map[uint32]string, value uint32) {
 				if dw1.GetPadTol() != 0 {
@@ -145,29 +142,27 @@ func (FieldMacros) DecodeDW1() {
 				}
 			},
 		},
-
 		&field{
 			configmap: map[uint32]string{
-				0x0: "GpioTermNone",
-				0x2: "GpioTermWpd5K",
-				0x4: "GpioTermWpd20K",
-				0x9: "GpioTermWpu1K",
-				0xa: "GpioTermWpu5K",
-				0xb: "GpioTermWpu2K",
-				0xc: "GpioTermWpu20K",
-				0xd: "GpioTermWpu1K2K",
-				0xf: "GpioTermNative",
+				0b0000: "GpioTermNone",
+				0b0010: "GpioTermWpd5K",
+				0b0100: "GpioTermWpd20K",
+				0b1001: "GpioTermWpu1K",
+				0b1010: "GpioTermWpu5K",
+				0b1011: "GpioTermWpu2K",
+				0b1100: "GpioTermWpu20K",
+				0b1101: "GpioTermWpu1K2K",
+				0b1111: "GpioTermNative",
 			},
 			value: dw1.GetTermination(),
 		},
 	)
+	return macro
 }
 
-// GenerateString - generates the entire string of bitfield macros.
-func (bitfields FieldMacros) GenerateString() {
-	macro := common.GetMacro()
+// GenerateMacro() generates the field macro collection and adds it to the macro string
+func (f FieldCollection) GenerateMacro(macro *common.Macro) *common.Macro {
 	macro.Add("{ GPIO_SKL_H_").Id().Add(", { ")
-	bitfields.DecodeDW0()
-	bitfields.DecodeDW1()
-	macro.Add(" GpioPadConfigLock } },") // TODO: configure GpioPadConfigLock
+	f.DecodeDW0(macro)
+	return f.DecodeDW1(macro).Add(" GpioPadConfigLock } },") // TODO: configure GpioPadConfigLock
 }
diff --git a/util/intelp2m/fields/fsp/fsp_test.go b/util/intelp2m/fields/fsp/fsp_test.go
index 90bbc0e884..3b6d8c6650 100644
--- a/util/intelp2m/fields/fsp/fsp_test.go
+++ b/util/intelp2m/fields/fsp/fsp_test.go
@@ -3,11 +3,13 @@ package fsp_test
 import (
 	"testing"
 
-	"review.coreboot.org/coreboot.git/util/intelp2m/fields/fsp"
+	"review.coreboot.org/coreboot.git/util/intelp2m/config/p2m"
 	"review.coreboot.org/coreboot.git/util/intelp2m/fields/test"
 )
 
 func TestFSPFields(t *testing.T) {
+	p2m.SettingsReset()
+	p2m.Config.Field = p2m.FspFlds
 	referenceSlice := []string{
 		"{ GPIO_SKL_H_, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirInOut, GpioOutLow, GpioIntDis | GpioIntLevel, GpioPlatformReset, GpioTermNone,  GpioPadConfigLock } },",
 		"{ GPIO_SKL_H_, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirInOut, GpioOutLow, GpioIntDis | GpioIntLevel, GpioHostDeepReset, GpioTermNone,  GpioPadConfigLock } },",
@@ -42,5 +44,5 @@ func TestFSPFields(t *testing.T) {
 		"{ GPIO_SKL_H_, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirInOut, GpioOutLow, GpioIntDis | GpioIntLevel, GpioResetPwrGood, GpioTermNone,  GpioPadConfigLock } },",
 		"{ GPIO_SKL_H_, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirInOut, GpioOutHigh, GpioIntDis | GpioIntLevel, GpioResetPwrGood, GpioTermNone,  GpioPadConfigLock } },",
 	}
-	test.SlidingOneTestSuiteCreate(referenceSlice).Run(t, "SLIDING-ONE-TEST", fsp.FieldMacros{})
+	test.SlidingOneTestSuiteCreate(referenceSlice).Run(t, "SLIDING-ONE-TEST")
 }
diff --git a/util/intelp2m/fields/raw/raw.go b/util/intelp2m/fields/raw/raw.go
index 4efccd5c5e..12338a0adb 100644
--- a/util/intelp2m/fields/raw/raw.go
+++ b/util/intelp2m/fields/raw/raw.go
@@ -1,29 +1,24 @@
 package raw
 
-import (
-	"review.coreboot.org/coreboot.git/util/intelp2m/platforms/common"
-)
+import "review.coreboot.org/coreboot.git/util/intelp2m/platforms/common"
 
-type FieldMacros struct{}
+type FieldCollection struct{}
 
-func (FieldMacros) DecodeDW0() {
-	macro := common.GetMacro()
-	dw0 := macro.GetRegisterDW0()
-	macro.Add(dw0.String())
+// DecodeDW0() decodes DW0 register value and adds it to the macro string
+func (FieldCollection) DecodeDW0(macro *common.Macro) *common.Macro {
+	dw0 := macro.Platform.GetRegisterDW0()
+	return macro.Add(dw0.String())
 }
 
-func (FieldMacros) DecodeDW1() {
-	macro := common.GetMacro()
-	dw1 := macro.GetRegisterDW1()
-	macro.Add(dw1.String())
+// DecodeDW1() decodes DW1 register value and adds it to the macro string
+func (FieldCollection) DecodeDW1(macro *common.Macro) *common.Macro {
+	dw1 := macro.Platform.GetRegisterDW1()
+	return macro.Add(dw1.String())
 }
 
-// GenerateString - generates the entire string of bitfield macros.
-func (bitfields FieldMacros) GenerateString() {
-	macro := common.GetMacro()
+// GenerateMacro() generates the field macro collection and adds it to the macro string
+func (f FieldCollection) GenerateMacro(macro *common.Macro) *common.Macro {
 	macro.Add("_PAD_CFG_STRUCT(").Id().Add(", ")
-	bitfields.DecodeDW0()
-	macro.Add(", ")
-	bitfields.DecodeDW1()
-	macro.Add("),")
+	f.DecodeDW0(macro).Add(", ")
+	return f.DecodeDW1(macro).Add("),")
 }
diff --git a/util/intelp2m/fields/raw/raw_test.go b/util/intelp2m/fields/raw/raw_test.go
index 8cab698ab7..067f6aa5ac 100644
--- a/util/intelp2m/fields/raw/raw_test.go
+++ b/util/intelp2m/fields/raw/raw_test.go
@@ -3,11 +3,13 @@ package raw_test
 import (
 	"testing"
 
-	"review.coreboot.org/coreboot.git/util/intelp2m/fields/raw"
+	"review.coreboot.org/coreboot.git/util/intelp2m/config/p2m"
 	"review.coreboot.org/coreboot.git/util/intelp2m/fields/test"
 )
 
 func TestRAWFields(t *testing.T) {
+	p2m.SettingsReset()
+	p2m.Config.Field = p2m.RawFlds
 	referenceSlice := []string{
 		"_PAD_CFG_STRUCT(, 0x80000000, 0x80000000),",
 		"_PAD_CFG_STRUCT(, 0x40000000, 0x40000000),",
@@ -42,5 +44,5 @@ func TestRAWFields(t *testing.T) {
 		"_PAD_CFG_STRUCT(, 0x00000002, 0x00000002),",
 		"_PAD_CFG_STRUCT(, 0x00000001, 0x00000001),",
 	}
-	test.SlidingOneTestSuiteCreate(referenceSlice).Run(t, "SLIDING-ONE-TEST", raw.FieldMacros{})
+	test.SlidingOneTestSuiteCreate(referenceSlice).Run(t, "SLIDING-ONE-TEST")
 }
diff --git a/util/intelp2m/fields/test/suite.go b/util/intelp2m/fields/test/suite.go
index 3041de2136..816a3a8105 100644
--- a/util/intelp2m/fields/test/suite.go
+++ b/util/intelp2m/fields/test/suite.go
@@ -4,8 +4,9 @@ import (
 	"fmt"
 	"testing"
 
+	"review.coreboot.org/coreboot.git/util/intelp2m/fields"
+	"review.coreboot.org/coreboot.git/util/intelp2m/platforms"
 	"review.coreboot.org/coreboot.git/util/intelp2m/platforms/common"
-	"review.coreboot.org/coreboot.git/util/intelp2m/platforms/snr"
 )
 
 type TestCase struct {
@@ -16,7 +17,7 @@ type TestCase struct {
 
 func (tc TestCase) Check(actuallyMacro string) error {
 	if actuallyMacro != tc.Reference {
-		return fmt.Errorf(`TestCase: DW0 = %d, DW1 = %d, Ownership = %d:
+		return fmt.Errorf(`TestCase: DW0 = 0x%x, DW1 = 0x%x, Ownership = %d:
 Expects:  '%s'
 Actually: '%s'`, tc.DW0, tc.DW1, tc.Ownership, tc.Reference, actuallyMacro)
 	}
@@ -25,19 +26,20 @@ Actually: '%s'`, tc.DW0, tc.DW1, tc.Ownership, tc.Reference, actuallyMacro)
 
 type Suite []TestCase
 
-func (suite Suite) Run(t *testing.T, label string, decoderIf common.Fields) {
+func (suite Suite) Run(t *testing.T, label string) {
 	t.Run(label, func(t *testing.T) {
-		platform := snr.PlatformSpecific{}
-		macro := common.GetInstanceMacro(platform, decoderIf)
-		dw0 := macro.GetRegisterDW0()
-		dw1 := macro.GetRegisterDW1()
 		for _, tc := range suite {
-			macro.Clear()
-			macro.PadIdSet("").SetPadOwnership(tc.Ownership)
-			dw0.Value = tc.DW0
-			dw1.Value = tc.DW1
-			macro.Fields.GenerateString()
-			if err := tc.Check(macro.Get()); err != nil {
+			constructor, err := platforms.GetConstructor()
+			if err != nil {
+				panic(err)
+			}
+			macro := common.CreateFrom(
+				"",
+				tc.Ownership == 1,
+				constructor(tc.DW0, tc.DW1),
+				fields.Get(),
+			)
+			if err := tc.Check(macro.Fields.GenerateMacro(&macro).String()); err != nil {
 				t.Errorf("Test failed: %v", err)
 			}
 		}
diff --git a/util/intelp2m/parser/parser.go b/util/intelp2m/parser/parser.go
index b410912128..4575549544 100644
--- a/util/intelp2m/parser/parser.go
+++ b/util/intelp2m/parser/parser.go
@@ -7,6 +7,7 @@ import (
 	"strings"
 
 	"review.coreboot.org/coreboot.git/util/intelp2m/config/p2m"
+	"review.coreboot.org/coreboot.git/util/intelp2m/fields"
 	"review.coreboot.org/coreboot.git/util/intelp2m/logs"
 	"review.coreboot.org/coreboot.git/util/intelp2m/parser/template"
 	"review.coreboot.org/coreboot.git/util/intelp2m/platforms"
@@ -35,13 +36,16 @@ type Entry struct {
 	Function  string
 	DW0       uint32
 	DW1       uint32
-	Ownership uint8
+	Ownership bool
 }
 
 func (e *Entry) ToMacro() []string {
-	platform := platforms.GetSpecificInterface()
-	line := platform.GenMacro(e.ID, e.DW0, e.DW1, e.Ownership)
-	slices := strings.Split(line, "\n")
+	constructor, err := platforms.GetConstructor()
+	if err != nil {
+		panic(err)
+	}
+	macro := common.CreateFrom(e.ID, e.Ownership, constructor(e.DW0, e.DW1), fields.Get())
+	slices := strings.Split(macro.Generate(), "\n")
 	return slices
 }
 
@@ -49,7 +53,7 @@ func (e *Entry) ToMacro() []string {
 func extractPad(line string) (Entry, error) {
 	function, id, dw0, dw1, err := template.Apply(line)
 	if err != nil {
-		logs.Errorf("%v", err)
+		logs.Errorf("extraction error: %v", err)
 		return Entry{EType: EntryEmpty}, err
 	}
 
@@ -59,7 +63,7 @@ func extractPad(line string) (Entry, error) {
 		ID:        id,
 		DW0:       dw0,
 		DW1:       dw1,
-		Ownership: 0,
+		Ownership: common.Acpi,
 	}
 
 	if dw0 == bits.All32 {
@@ -79,12 +83,14 @@ func extractGroup(line string) Entry {
 }
 
 // Extract() extracts pad information from a string
-func Extract(line string, platform platforms.SpecificIf) Entry {
+func Extract(line string) Entry {
 	if included, _ := common.KeywordsCheck(line, "GPIO Community", "GPIO Group"); included {
 		return extractGroup(line)
 	}
-
-	if platform.KeywordCheck(line) {
+	if checkKeyword := platforms.GetKeywordChekingAction(); checkKeyword == nil {
+		logs.Errorf("information extraction error: skip line <%s>", line)
+		return Entry{EType: EntryEmpty}
+	} else if checkKeyword(line) {
 		pad, err := extractPad(line)
 		if err != nil {
 			logs.Errorf("extract pad info from %s: %v", line, err)
@@ -100,11 +106,6 @@ func Extract(line string, platform platforms.SpecificIf) Entry {
 func Run() ([]Entry, error) {
 	entries := make([]Entry, 0)
 
-	platform := platforms.GetSpecificInterface()
-	if platform == nil {
-		return nil, fmt.Errorf("unknown platform")
-	}
-
 	file, err := os.Open(p2m.Config.InputPath)
 	if err != nil {
 		err = fmt.Errorf("input file error: %v", err)
@@ -117,7 +118,7 @@ func Run() ([]Entry, error) {
 	scanner := bufio.NewScanner(file)
 	for scanner.Scan() {
 		line := scanner.Text()
-		entry := Extract(line, platform)
+		entry := Extract(line)
 		if entry.EType != EntryEmpty {
 			entries = append(entries, entry)
 		}
diff --git a/util/intelp2m/platforms/adl/adl_test.go b/util/intelp2m/platforms/adl/adl_test.go
index 1f2400a710..68b118781a 100644
--- a/util/intelp2m/platforms/adl/adl_test.go
+++ b/util/intelp2m/platforms/adl/adl_test.go
@@ -3,108 +3,103 @@ package adl_test
 import (
 	"testing"
 
-	"review.coreboot.org/coreboot.git/util/intelp2m/platforms/adl"
-	"review.coreboot.org/coreboot.git/util/intelp2m/platforms/cnl"
-	"review.coreboot.org/coreboot.git/util/intelp2m/platforms/snr"
+	"review.coreboot.org/coreboot.git/util/intelp2m/config/p2m"
+	"review.coreboot.org/coreboot.git/util/intelp2m/platforms/common"
 	"review.coreboot.org/coreboot.git/util/intelp2m/platforms/test"
 )
 
 func TestGenMacro(t *testing.T) {
-	alderlake := adl.PlatformSpecific{
-		InheritanceMacro: cnl.PlatformSpecific{
-			InheritanceMacro: snr.PlatformSpecific{},
-		},
-	}
+	p2m.Config.Platform = p2m.Alder
 	test.Suite{
 		{
-			Pad: test.Pad{ID: "GPP_A1", DW0: 0x11111111, DW1: 0x11111111, Ownership: 1},
+			Pad: test.Pad{ID: "GPP_A1", DW0: 0x11111111, DW1: 0x11111111, Ownership: common.Driver},
 			Macro: test.Macro{
 				Short: "PAD_CFG_NF(GPP_A1, DN_20K, RSMRST, NF4),",
 				Long:  "_PAD_CFG_STRUCT(GPP_A1, PAD_FUNC(NF4) | PAD_RESET(RSMRST) | PAD_IRQ_ROUTE(IOAPIC) | PAD_BUF(TX_DISABLE) | (1 << 28) | 1, PAD_PULL(DN_20K) | PAD_IOSSTATE(Tx1RxDCRx1) | PAD_IOSTERM(DISPUPD) | PAD_CFG_OWN_GPIO(DRIVER)),",
 			},
 		},
 		{
-			Pad: test.Pad{ID: "GPP_B2", DW0: 0x22222222, DW1: 0x22222222, Ownership: 0},
+			Pad: test.Pad{ID: "GPP_B2", DW0: 0x22222222, DW1: 0x22222222, Ownership: common.Acpi},
 			Macro: test.Macro{
 				Short: "PAD_CFG_TERM_GPO(GPP_B2, 0, INVALID, RSMRST),",
 				Long:  "_PAD_CFG_STRUCT(GPP_B2, PAD_FUNC(GPIO) | PAD_RESET(RSMRST) | PAD_TRIG(EDGE_SINGLE) | PAD_IRQ_ROUTE(NMI) | PAD_BUF(RX_DISABLE) | (1 << 29) | (1 << 1), PAD_CFG1_TOL_1V8PAD_PULL(INVALID) | PAD_IOSSTATE(HIZCRx1) | PAD_IOSTERM(ENPD)),",
 			},
 		},
 		{
-			Pad: test.Pad{ID: "GPP_C3", DW0: 0x44444444, DW1: 0x44444444, Ownership: 1},
+			Pad: test.Pad{ID: "GPP_C3", DW0: 0x44444444, DW1: 0x44444444, Ownership: common.Driver},
 			Macro: test.Macro{
 				Short: "PAD_CFG_NF(GPP_C3, INVALID, DEEP, NF1),",
 				Long:  "_PAD_CFG_STRUCT(GPP_C3, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_IRQ_ROUTE(SMI), PAD_PULL(INVALID) | PAD_IOSSTATE(Tx0RxDCRx0) | PAD_CFG_OWN_GPIO(DRIVER)),",
 			},
 		},
 		{
-			Pad: test.Pad{ID: "GPP_D4", DW0: 0x88888888, DW1: 0x88888888, Ownership: 0},
+			Pad: test.Pad{ID: "GPP_D4", DW0: 0x88888888, DW1: 0x88888888, Ownership: common.Acpi},
 			Macro: test.Macro{
 				Short: "PAD_CFG_NF(GPP_D4, DN_5K, PLTRST, NF2),",
 				Long:  "_PAD_CFG_STRUCT(GPP_D4, PAD_FUNC(NF2) | PAD_RESET(PLTRST) | PAD_IRQ_ROUTE(SCI) | PAD_RX_POL(INVERT), PAD_PULL(DN_5K) | PAD_IOSSTATE(Tx0RxDCRx1)),",
 			},
 		},
-	}.Run(t, "INTEL-ALDER-LAKE-PCH/SLIDING-ONE-IN-NIBBLE-TEST", alderlake)
+	}.Run(t, "INTEL-ALDER-LAKE-PCH/SLIDING-ONE-IN-NIBBLE-TEST")
 
 	test.Suite{
 		{
-			Pad: test.Pad{ID: "GPP_E5", DW0: 0xEEEEEEEE, DW1: 0xEEEEEEEE, Ownership: 1},
+			Pad: test.Pad{ID: "GPP_E5", DW0: 0xEEEEEEEE, DW1: 0xEEEEEEEE, Ownership: common.Driver},
 			Macro: test.Macro{
 				Short: "PAD_CFG_NF_1V8(GPP_E5, UP_2K, PWROK, NF3),",
 				Long:  "_PAD_CFG_STRUCT(GPP_E5, PAD_FUNC(NF3) | PAD_TRIG(EDGE_BOTH) | PAD_IRQ_ROUTE(SCI) | PAD_IRQ_ROUTE(SMI) | PAD_IRQ_ROUTE(NMI) | PAD_RX_POL(INVERT) | PAD_BUF(RX_DISABLE) | (1 << 29) | (1 << 1), PAD_CFG1_TOL_1V8PAD_PULL(UP_2K) | PAD_IOSSTATE(ERROR) | PAD_IOSTERM(ENPD) | PAD_CFG_OWN_GPIO(DRIVER)),",
 			},
 		},
 		{
-			Pad: test.Pad{ID: "GPP_F6", DW0: 0xDDDDDDDD, DW1: 0xDDDDDDDD, Ownership: 0},
+			Pad: test.Pad{ID: "GPP_F6", DW0: 0xDDDDDDDD, DW1: 0xDDDDDDDD, Ownership: common.Acpi},
 			Macro: test.Macro{
 				Short: "PAD_CFG_NF(GPP_F6, INVALID, PWROK, NF7),",
 				Long:  "_PAD_CFG_STRUCT(GPP_F6, PAD_FUNC(NF7) | PAD_TRIG(OFF) | PAD_IRQ_ROUTE(IOAPIC) | PAD_IRQ_ROUTE(SCI) | PAD_IRQ_ROUTE(SMI) | PAD_RX_POL(INVERT) | PAD_BUF(TX_DISABLE) | (1 << 28) | 1, PAD_PULL(INVALID) | PAD_IOSSTATE(HIZCRx0) | PAD_IOSTERM(DISPUPD)),",
 			},
 		},
 		{
-			Pad: test.Pad{ID: "GPP_G7", DW0: 0xBBBBBBBB, DW1: 0xBBBBBBBB, Ownership: 1},
+			Pad: test.Pad{ID: "GPP_G7", DW0: 0xBBBBBBBB, DW1: 0xBBBBBBBB, Ownership: common.Driver},
 			Macro: test.Macro{
 				Short: "PAD_CFG_NF_1V8(GPP_G7, INVALID, PLTRST, NF6),",
 				Long:  "_PAD_CFG_STRUCT(GPP_G7, PAD_FUNC(NF6) | PAD_RESET(PLTRST) | PAD_TRIG(EDGE_SINGLE) | PAD_IRQ_ROUTE(IOAPIC) | PAD_IRQ_ROUTE(SCI) | PAD_IRQ_ROUTE(NMI) | PAD_RX_POL(INVERT) | PAD_BUF(TX_RX_DISABLE) | (1 << 29) | (1 << 28) | (1 << 1) | 1, PAD_CFG1_TOL_1V8PAD_PULL(INVALID) | PAD_IOSSTATE(ERROR) | PAD_IOSTERM(ENPU) | PAD_CFG_OWN_GPIO(DRIVER)),",
 			},
 		},
 		{
-			Pad: test.Pad{ID: "GPP_H8", DW0: 0x77777777, DW1: 0x77777777, Ownership: 0},
+			Pad: test.Pad{ID: "GPP_H8", DW0: 0x77777777, DW1: 0x77777777, Ownership: common.Acpi},
 			Macro: test.Macro{
 				Short: "PAD_CFG_NF_1V8(GPP_H8, UP_667, DEEP, NF5),",
 				Long:  "_PAD_CFG_STRUCT(GPP_H8, PAD_FUNC(NF5) | PAD_RESET(DEEP) | PAD_TRIG(EDGE_BOTH) | PAD_IRQ_ROUTE(IOAPIC) | PAD_IRQ_ROUTE(SMI) | PAD_IRQ_ROUTE(NMI) | PAD_BUF(TX_RX_DISABLE) | (1 << 29) | (1 << 28) | (1 << 1) | 1, PAD_CFG1_TOL_1V8PAD_PULL(UP_667) | PAD_IOSSTATE(ERROR) | PAD_IOSTERM(ENPU)),",
 			},
 		},
-	}.Run(t, "INTEL-ALDER-LAKE-PCH/SLIDING-ZERO-IN-NIBBLE-TEST", alderlake)
+	}.Run(t, "INTEL-ALDER-LAKE-PCH/SLIDING-ZERO-IN-NIBBLE-TEST")
 
 	test.Suite{
 		{
-			Pad: test.Pad{ID: "GPP_I9", DW0: 0x33333333, DW1: 0x33333333, Ownership: 1},
+			Pad: test.Pad{ID: "GPP_I9", DW0: 0x33333333, DW1: 0x33333333, Ownership: common.Driver},
 			Macro: test.Macro{
 				Short: "PAD_CFG_NF_1V8(GPP_I9, UP_20K, RSMRST, NF4),",
 				Long:  "_PAD_CFG_STRUCT(GPP_I9, PAD_FUNC(NF4) | PAD_RESET(RSMRST) | PAD_TRIG(EDGE_SINGLE) | PAD_IRQ_ROUTE(IOAPIC) | PAD_IRQ_ROUTE(NMI) | PAD_BUF(TX_RX_DISABLE) | (1 << 29) | (1 << 28) | (1 << 1) | 1, PAD_CFG1_TOL_1V8PAD_PULL(UP_20K) | PAD_IOSSTATE(ERROR) | PAD_IOSTERM(ENPU) | PAD_CFG_OWN_GPIO(DRIVER)),",
 			},
 		},
 		{
-			Pad: test.Pad{ID: "GPP_J10", DW0: 0x66666666, DW1: 0x66666666, Ownership: 0},
+			Pad: test.Pad{ID: "GPP_J10", DW0: 0x66666666, DW1: 0x66666666, Ownership: common.Acpi},
 			Macro: test.Macro{
 				Short: "PAD_CFG_NF_1V8(GPP_J10, UP_1K, DEEP, NF1),",
 				Long:  "_PAD_CFG_STRUCT(GPP_J10, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(EDGE_BOTH) | PAD_IRQ_ROUTE(SMI) | PAD_IRQ_ROUTE(NMI) | PAD_BUF(RX_DISABLE) | (1 << 29) | (1 << 1), PAD_CFG1_TOL_1V8PAD_PULL(UP_1K) | PAD_IOSSTATE(TxDRxE) | PAD_IOSTERM(ENPD)),",
 			},
 		},
 		{
-			Pad: test.Pad{ID: "GPP_K11", DW0: 0xCCCCCCCC, DW1: 0xCCCCCCCC, Ownership: 1},
+			Pad: test.Pad{ID: "GPP_K11", DW0: 0xCCCCCCCC, DW1: 0xCCCCCCCC, Ownership: common.Driver},
 			Macro: test.Macro{
 				Short: "PAD_CFG_NF(GPP_K11, INVALID, PWROK, NF3),",
 				Long:  "_PAD_CFG_STRUCT(GPP_K11, PAD_FUNC(NF3) | PAD_TRIG(OFF) | PAD_IRQ_ROUTE(SCI) | PAD_IRQ_ROUTE(SMI) | PAD_RX_POL(INVERT), PAD_PULL(INVALID) | PAD_IOSSTATE(Tx1RxDCRx0) | PAD_CFG_OWN_GPIO(DRIVER)),",
 			},
 		},
 		{
-			Pad: test.Pad{ID: "GPP_R12", DW0: 0x99999999, DW1: 0x99999999, Ownership: 0},
+			Pad: test.Pad{ID: "GPP_R12", DW0: 0x99999999, DW1: 0x99999999, Ownership: common.Acpi},
 			Macro: test.Macro{
 				Short: "PAD_CFG_NF(GPP_R12, INVALID, PLTRST, NF6),",
 				Long:  "_PAD_CFG_STRUCT(GPP_R12, PAD_FUNC(NF6) | PAD_RESET(PLTRST) | PAD_IRQ_ROUTE(IOAPIC) | PAD_IRQ_ROUTE(SCI) | PAD_RX_POL(INVERT) | PAD_BUF(TX_DISABLE) | (1 << 28) | 1, PAD_PULL(INVALID) | PAD_IOSSTATE(Tx1RxE) | PAD_IOSTERM(DISPUPD)),",
 			},
 		},
-	}.Run(t, "INTEL-ALDER-LAKE-PCH/SLIDING-ONE-ONE-IN-NIBBLE-TEST", alderlake)
+	}.Run(t, "INTEL-ALDER-LAKE-PCH/SLIDING-ONE-ONE-IN-NIBBLE-TEST")
 }
diff --git a/util/intelp2m/platforms/adl/macro.go b/util/intelp2m/platforms/adl/macro.go
index 7c4f4357bb..19e9bd20e5 100644
--- a/util/intelp2m/platforms/adl/macro.go
+++ b/util/intelp2m/platforms/adl/macro.go
@@ -1,113 +1,57 @@
 package adl
 
 import (
-	"fmt"
 	"strings"
 
-	"review.coreboot.org/coreboot.git/util/intelp2m/fields"
+	"review.coreboot.org/coreboot.git/util/intelp2m/logs"
 	"review.coreboot.org/coreboot.git/util/intelp2m/platforms/cnl"
 	"review.coreboot.org/coreboot.git/util/intelp2m/platforms/common"
 	"review.coreboot.org/coreboot.git/util/intelp2m/platforms/common/register/bits"
-	"review.coreboot.org/coreboot.git/util/intelp2m/platforms/snr"
 )
 
 const (
-	PAD_CFG_DW0_RO_FIELDS = (0x1 << 27) | (0x1 << 24) | (0x3 << 21) | (0xf << 16) | 0xfc
-	PAD_CFG_DW1_RO_FIELDS = 0xfdffc3ff
+	DW0Mask uint32 = (0b1 << 27) | (0b1 << 24) | (0b11 << 21) | (0b1111 << 16) | 0b11111100
+	DW1Mask uint32 = 0b11111101111111111100001111111111
 )
 
-type InheritanceMacro interface {
-	Pull()
-	GpiMacroAdd()
-	GpoMacroAdd()
-	NativeFunctionMacroAdd()
-	NoConnMacroAdd()
+type BasePlatform struct {
+	// based on the Cannon Lake platform
+	cnl.BasePlatform
 }
 
-type PlatformSpecific struct {
-	InheritanceMacro
+func InitBasePlatform(dw0, dw0mask uint32, dw1, dw1mask uint32) BasePlatform {
+	return BasePlatform{cnl.InitBasePlatform(dw0, dw0mask, dw1, dw1mask)}
 }
 
-// RemmapRstSrc - remmap Pad Reset Source Config
-func (PlatformSpecific) RemmapRstSrc() {
-	macro := common.GetMacro()
-	if strings.Contains(macro.PadIdGet(), "GPD") {
+func GetPlatform(dw0, dw1 uint32) common.PlatformIf {
+	p := InitBasePlatform(dw0, DW0Mask, dw1, DW1Mask)
+	return &p
+}
+
+// Override BasePlatform.RemapRstSrc()
+func (p *BasePlatform) RemapRstSrc(m *common.Macro) {
+	if strings.Contains(m.GetPadId(), "GPD") {
 		// See reset map for the Alderlake GPD Group in the Community 2:
 		// https://github.com/coreboot/coreboot/blob/master/src/soc/intel/alderlake/gpio.c#L21
 		// remmap is not required because it is the same as common.
 		return
 	}
 
-	dw0 := macro.GetRegisterDW0()
 	remapping := map[uint32]uint32{
-		0: (bits.RstCfgRSMRST << bits.DW0PadRstCfg),
-		1: (bits.RstCfgDEEP << bits.DW0PadRstCfg),
-		2: (bits.RstCfgPLTRST << bits.DW0PadRstCfg),
-		3: (bits.RstCfgPWROK << bits.DW0PadRstCfg),
+		0b00: bits.RstCfgRSMRST << bits.DW0PadRstCfg,
+		0b01: bits.RstCfgDEEP << bits.DW0PadRstCfg,
+		0b10: bits.RstCfgPLTRST << bits.DW0PadRstCfg,
+		0b11: bits.RstCfgPWROK << bits.DW0PadRstCfg,
 	}
-	resetsrc, valid := remapping[dw0.GetResetConfig()]
+	dw0 := p.GetRegisterDW0()
+	source, valid := remapping[dw0.GetResetConfig()]
 	if valid {
-		// dw0.SetResetConfig(resetsrc)
-		ResetConfigFieldVal := (dw0.Value & 0x3fffffff) | remapping[dw0.GetResetConfig()]
-		dw0.Value = ResetConfigFieldVal
+		dw0.Value &= 0x3fffffff
+		dw0.Value |= source
 	} else {
-		fmt.Println("Invalid Pad Reset Config [ 0x", resetsrc, " ] for ", macro.PadIdGet())
+		logs.Errorf("%s: skip re-mapping: DW0 %s: invalid reset config source value 0b%b",
+			m.GetPadId(), dw0, dw0.GetResetConfig())
 	}
-	dw0.CntrMaskFieldsClear(0b11 << bits.DW0PadRstCfg)
-}
-
-// Adds The Pad Termination (TERM) parameter from PAD_CFG_DW1 to the macro
-// as a new argument
-func (platform PlatformSpecific) Pull() {
-	platform.InheritanceMacro.Pull()
-}
-
-// Adds PAD_CFG_GPI macro with arguments
-func (platform PlatformSpecific) GpiMacroAdd() {
-	platform.InheritanceMacro.GpiMacroAdd()
-}
-
-// Adds PAD_CFG_GPO macro with arguments
-func (platform PlatformSpecific) GpoMacroAdd() {
-	platform.InheritanceMacro.GpoMacroAdd()
-}
-
-// Adds PAD_CFG_NF macro with arguments
-func (platform PlatformSpecific) NativeFunctionMacroAdd() {
-	platform.InheritanceMacro.NativeFunctionMacroAdd()
-}
-
-// Adds PAD_NC macro
-func (platform PlatformSpecific) NoConnMacroAdd() {
-	platform.InheritanceMacro.NoConnMacroAdd()
-}
-
-// GenMacro - generate pad macro
-// dw0Val : DW0 config register value
-// dw1Val : DW1 config register value
-// return: string of macro
-//         error
-func (PlatformSpecific) GenMacro(id string, dw0Val uint32, dw1Val uint32, ownership uint8) string {
-	macro := common.GetInstanceMacro(
-		PlatformSpecific{
-			InheritanceMacro: cnl.PlatformSpecific{
-				InheritanceMacro: snr.PlatformSpecific{},
-			},
-		},
-		fields.InterfaceGet(),
-	)
-	macro.Clear()
-	dw0 := macro.GetRegisterDW0()
-	dw0.CntrMaskFieldsClear(bits.All32)
-
-	dw1 := macro.GetRegisterDW1()
-	dw1.CntrMaskFieldsClear(bits.All32)
-
-	dw0.Value = dw0Val
-	dw1.Value = dw1Val
-
-	dw0.ReadOnly = PAD_CFG_DW0_RO_FIELDS
-	dw1.ReadOnly = PAD_CFG_DW1_RO_FIELDS
-	macro.PadIdSet(id).SetPadOwnership(ownership)
-	return macro.Generate()
+	mask := bits.DW0[bits.DW0PadRstCfg]
+	dw0.CntrMaskFieldsClear(mask)
 }
diff --git a/util/intelp2m/platforms/adl/template.go b/util/intelp2m/platforms/adl/template.go
index 1642670144..4af499dbab 100644
--- a/util/intelp2m/platforms/adl/template.go
+++ b/util/intelp2m/platforms/adl/template.go
@@ -2,14 +2,12 @@ package adl
 
 import "review.coreboot.org/coreboot.git/util/intelp2m/platforms/common"
 
-// Group : "GPP_A", "GPP_B", "GPP_C", "GPP_D", "GPP_E", "GPP_F", "GPP_G",
-//         "GPP_H", "GPP_I", "GPP_J", "GPP_K", "GPP_R", "GPP_S", "GPP_T",
-//         "GPD", "VGPIO_USB", "VGPIO_PCIE"
-
-// KeywordCheck - This function is used to filter parsed lines of the configuration file and
-// returns true if the keyword is contained in the line.
-// line : string from the configuration file
-func (PlatformSpecific) KeywordCheck(line string) bool {
+// CheckKeyword() parses lines of the configuration file and returns true if the keyword is
+// contained in the line
+// "GPP_A", "GPP_B", "GPP_C", "GPP_D", "GPP_E", "GPP_F", "GPP_G",
+// "GPP_H", "GPP_I", "GPP_J", "GPP_K", "GPP_R", "GPP_S", "GPP_T",
+// "GPD", "VGPIO_USB", "VGPIO_PCIE"
+func CheckKeyword(line string) bool {
 	isIncluded, _ := common.KeywordsCheck(line, "GPP_", "GPD", "VGPIO")
 	return isIncluded
 }
diff --git a/util/intelp2m/platforms/apl/apl_test.go b/util/intelp2m/platforms/apl/apl_test.go
index 42d15ba4eb..1735346505 100644
--- a/util/intelp2m/platforms/apl/apl_test.go
+++ b/util/intelp2m/platforms/apl/apl_test.go
@@ -3,165 +3,166 @@ package apl_test
 import (
 	"testing"
 
-	"review.coreboot.org/coreboot.git/util/intelp2m/platforms/apl"
+	"review.coreboot.org/coreboot.git/util/intelp2m/config/p2m"
+	"review.coreboot.org/coreboot.git/util/intelp2m/platforms/common"
 	"review.coreboot.org/coreboot.git/util/intelp2m/platforms/test"
 )
 
 func TestGenMacro(t *testing.T) {
-	apollolake := apl.PlatformSpecific{}
+	p2m.Config.Platform = p2m.Apollo
 	test.Suite{
 		{ /* GPIO_0 - GPIO */
-			Pad: test.Pad{ID: "GPIO_0", DW0: 0x44000300, DW1: 0x1003d000, Ownership: 0},
+			Pad: test.Pad{ID: "GPIO_0", DW0: 0x44000300, DW1: 0x1003d000, Ownership: common.Acpi},
 			Macro: test.Macro{
 				Short: "PAD_CFG_GPIO_HI_Z(GPIO_0, DN_20K, DEEP, IGNORE, SAME),",
 				Long:  "_PAD_CFG_STRUCT(GPIO_0, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(DN_20K) | PAD_IOSSTATE(IGNORE)),",
 			},
 		},
 		{ /* GPIO_15 - GPIO */
-			Pad: test.Pad{ID: "GPIO_15", DW0: 0x44000000, DW1: 0x10001000, Ownership: 0},
+			Pad: test.Pad{ID: "GPIO_15", DW0: 0x44000000, DW1: 0x10001000, Ownership: common.Acpi},
 			Macro: test.Macro{
 				Short: "PAD_CFG_GPIO_BIDIRECT(GPIO_15, 0, DN_20K, DEEP, OFF, ACPI),",
 				Long:  "_PAD_CFG_STRUCT(GPIO_15, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF), PAD_PULL(DN_20K)),",
 			},
 		},
 		{ /* GPIO_16 - GPIO */
-			Pad: test.Pad{ID: "GPIO_16", DW0: 0x44000003, DW1: 0x10003000, Ownership: 0},
+			Pad: test.Pad{ID: "GPIO_16", DW0: 0x44000003, DW1: 0x10003000, Ownership: common.Acpi},
 			Macro: test.Macro{
 				Short: "PAD_CFG_GPIO_BIDIRECT(GPIO_16, 1, UP_20K, DEEP, OFF, ACPI),",
 				Long:  "_PAD_CFG_STRUCT(GPIO_16, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | (1 << 1) | 1, PAD_PULL(UP_20K)),",
 			},
 		},
 		{ /* GPIO_18 - GPIO */
-			Pad: test.Pad{ID: "GPIO_18", DW0: 0x44000102, DW1: 0x10003000, Ownership: 0},
+			Pad: test.Pad{ID: "GPIO_18", DW0: 0x44000102, DW1: 0x10003000, Ownership: common.Acpi},
 			Macro: test.Macro{
 				Short: "PAD_CFG_GPI_TRIG_OWN(GPIO_18, UP_20K, DEEP, OFF, ACPI),",
 				Long:  "_PAD_CFG_STRUCT(GPIO_18, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), PAD_PULL(UP_20K)),",
 			},
 		},
 		{ /* GPIO_21 - GPIO */
-			Pad: test.Pad{ID: "GPIO_21", DW0: 0x44000102, DW1: 0x10027000, Ownership: 0},
+			Pad: test.Pad{ID: "GPIO_21", DW0: 0x44000102, DW1: 0x10027000, Ownership: common.Acpi},
 			Macro: test.Macro{
 				Short: "PAD_CFG_GPI_TRIG_IOSSTATE_OWN(GPIO_21, UP_20K, DEEP, OFF, TxDRxE, ACPI),",
 				Long:  "_PAD_CFG_STRUCT(GPIO_21, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), PAD_PULL(UP_20K) | PAD_IOSSTATE(TxDRxE)),",
 			},
 		},
 		{ /* GPIO_22 - GPIO */
-			Pad: test.Pad{ID: "GPIO_22", DW0: 0x44800102, DW1: 0x10024100, Ownership: 1},
+			Pad: test.Pad{ID: "GPIO_22", DW0: 0x44800102, DW1: 0x10024100, Ownership: common.Driver},
 			Macro: test.Macro{
 				Short: "PAD_CFG_GPI_TRIG_IOS_OWN(GPIO_22, NONE, DEEP, OFF, TxDRxE, DISPUPD, DRIVER),",
 				Long:  "_PAD_CFG_STRUCT(GPIO_22, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_RX_POL(INVERT) | PAD_BUF(TX_DISABLE) | (1 << 1), PAD_IOSSTATE(TxDRxE) | PAD_IOSTERM(DISPUPD) | PAD_CFG_OWN_GPIO(DRIVER)),",
 			},
 		},
 		{ /* GPIO_25 - GPIO */
-			Pad: test.Pad{ID: "GPIO_25", DW0: 0x40880102, DW1: 0x00027100, Ownership: 0},
+			Pad: test.Pad{ID: "GPIO_25", DW0: 0x40880102, DW1: 0x00027100, Ownership: common.Acpi},
 			Macro: test.Macro{
 				Short: "PAD_CFG_GPI_SCI_IOS(GPIO_25, UP_20K, DEEP, LEVEL, INVERT, TxDRxE, DISPUPD),",
 				Long:  "_PAD_CFG_STRUCT(GPIO_25, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_IRQ_ROUTE(SCI) | PAD_RX_POL(INVERT) | PAD_BUF(TX_DISABLE) | (1 << 1), PAD_PULL(UP_20K) | PAD_IOSSTATE(TxDRxE) | PAD_IOSTERM(DISPUPD)),",
 			},
 		},
 		{ /* GPIO_26 - SATA_LEDN */
-			Pad: test.Pad{ID: "GPIO_26", DW0: 0x44001400, DW1: 0x00003c00, Ownership: 1},
+			Pad: test.Pad{ID: "GPIO_26", DW0: 0x44001400, DW1: 0x00003c00, Ownership: common.Driver},
 			Macro: test.Macro{
 				Short: "PAD_CFG_NF(GPIO_26, NATIVE, DEEP, NF5),",
 				Long:  "_PAD_CFG_STRUCT(GPIO_26, PAD_FUNC(NF5) | PAD_RESET(DEEP) | PAD_TRIG(OFF), PAD_PULL(NATIVE) | PAD_CFG_OWN_GPIO(DRIVER)),",
 			},
 		},
 		{ /* GPIO_27 - GPIO */
-			Pad: test.Pad{ID: "GPIO_27", DW0: 0x42880102, DW1: 0x00024100, Ownership: 0},
+			Pad: test.Pad{ID: "GPIO_27", DW0: 0x42880102, DW1: 0x00024100, Ownership: common.Acpi},
 			Macro: test.Macro{
 				Short: "PAD_CFG_GPI_SCI_IOS(GPIO_27, NONE, DEEP, EDGE_SINGLE, INVERT, TxDRxE, DISPUPD),",
 				Long:  "_PAD_CFG_STRUCT(GPIO_27, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(EDGE_SINGLE) | PAD_IRQ_ROUTE(SCI) | PAD_RX_POL(INVERT) | PAD_BUF(TX_DISABLE) | (1 << 1), PAD_IOSSTATE(TxDRxE) | PAD_IOSTERM(DISPUPD)),",
 			},
 		},
 		{ /* TDI - JTAG_TDI */
-			Pad: test.Pad{ID: "TDI", DW0: 0x44000700, DW1: 0x00c00000, Ownership: 0},
+			Pad: test.Pad{ID: "TDI", DW0: 0x44000700, DW1: 0x00c00000, Ownership: common.Acpi},
 			Macro: test.Macro{
 				Short: "PAD_CFG_NF(TDI, NONE, DEEP, NF1),",
 				Long:  "_PAD_CFG_STRUCT(TDI, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),",
 			},
 		},
 		{ /* CNV_BRI_DT - GPIO */
-			Pad: test.Pad{ID: "CNV_BRI_DT", DW0: 0x44000100, DW1: 0x1003d000, Ownership: 0},
+			Pad: test.Pad{ID: "CNV_BRI_DT", DW0: 0x44000100, DW1: 0x1003d000, Ownership: common.Acpi},
 			Macro: test.Macro{
 				Short: "PAD_CFG_GPI_TRIG_IOSSTATE_OWN(CNV_BRI_DT, DN_20K, DEEP, OFF, IGNORE, ACPI),",
 				Long:  "_PAD_CFG_STRUCT(CNV_BRI_DT, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), PAD_PULL(DN_20K) | PAD_IOSSTATE(IGNORE)),",
 			},
 		},
 		{ /* CNV_BRI_RSP - GPIO */
-			Pad: test.Pad{ID: "CNV_BRI_RSP", DW0: 0x44000201, DW1: 0x10003000, Ownership: 0},
+			Pad: test.Pad{ID: "CNV_BRI_RSP", DW0: 0x44000201, DW1: 0x10003000, Ownership: common.Acpi},
 			Macro: test.Macro{
 				Short: "PAD_CFG_TERM_GPO(CNV_BRI_RSP, 1, UP_20K, DEEP),",
 				Long:  "_PAD_CFG_STRUCT(CNV_BRI_RSP, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, PAD_PULL(UP_20K)),",
 			},
 		},
 		{ /* GPIO_188 - DDI0_DDC_SCL */
-			Pad: test.Pad{ID: "GPIO_188", DW0: 0x44000400, DW1: 0x0003fc00, Ownership: 0},
+			Pad: test.Pad{ID: "GPIO_188", DW0: 0x44000400, DW1: 0x0003fc00, Ownership: common.Acpi},
 			Macro: test.Macro{
 				Short: "PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_188, NATIVE, DEEP, NF1),",
 				Long:  "_PAD_CFG_STRUCT(GPIO_188, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF), PAD_PULL(NATIVE) | PAD_IOSSTATE(IGNORE)),",
 			},
 		},
 		{ /* GPIO_172 - SDCARD_CLK */
-			Pad: test.Pad{ID: "GPIO_172", DW0: 0x44000400, DW1: 0x00021100, Ownership: 0},
+			Pad: test.Pad{ID: "GPIO_172", DW0: 0x44000400, DW1: 0x00021100, Ownership: common.Acpi},
 			Macro: test.Macro{
 				Short: "PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_172, DN_20K, DEEP, NF1, HIZCRx1, DISPUPD),",
 				Long:  "_PAD_CFG_STRUCT(GPIO_172, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF), PAD_PULL(DN_20K) | PAD_IOSSTATE(HIZCRx1) | PAD_IOSTERM(DISPUPD)),",
 			},
 		},
 		{ /* GPIO_176 - SDCARD_D3 */
-			Pad: test.Pad{ID: "GPIO_176", DW0: 0x44000400, DW1: 0x00021000, Ownership: 0},
+			Pad: test.Pad{ID: "GPIO_176", DW0: 0x44000400, DW1: 0x00021000, Ownership: common.Acpi},
 			Macro: test.Macro{
 				Short: "PAD_CFG_NF_IOSSTATE(GPIO_176, DN_20K, DEEP, NF1, HIZCRx1),",
 				Long:  "_PAD_CFG_STRUCT(GPIO_176, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF), PAD_PULL(DN_20K) | PAD_IOSSTATE(HIZCRx1)),",
 			},
 		},
 		{ /* GPIO_177 - GPIO */
-			Pad: test.Pad{ID: "GPIO_177", DW0: 0x46000102, DW1: 0x10027000, Ownership: 1},
+			Pad: test.Pad{ID: "GPIO_177", DW0: 0x46000102, DW1: 0x10027000, Ownership: common.Driver},
 			Macro: test.Macro{
 				Short: "PAD_CFG_GPI_TRIG_IOSSTATE_OWN(GPIO_177, UP_20K, DEEP, EDGE_BOTH, TxDRxE, DRIVER),",
 				Long:  "_PAD_CFG_STRUCT(GPIO_177, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(EDGE_BOTH) | PAD_BUF(TX_DISABLE) | (1 << 1), PAD_PULL(UP_20K) | PAD_IOSSTATE(TxDRxE) | PAD_CFG_OWN_GPIO(DRIVER)),",
 			},
 		},
 		{ /* GPIO_186 - SDCARD_LVL_WP */
-			Pad: test.Pad{ID: "GPIO_186", DW0: 0x44000402, DW1: 0x00003000, Ownership: 0},
+			Pad: test.Pad{ID: "GPIO_186", DW0: 0x44000402, DW1: 0x00003000, Ownership: common.Acpi},
 			Macro: test.Macro{
 				Short: "PAD_CFG_NF(GPIO_186, UP_20K, DEEP, NF1),",
 				Long:  "_PAD_CFG_STRUCT(GPIO_186, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | (1 << 1), PAD_PULL(UP_20K)),",
 			},
 		},
 		{ /* GPIO_182 - EMMC_RCLK */
-			Pad: test.Pad{ID: "GPIO_182", DW0: 0x44000400, DW1: 0x0001d000, Ownership: 0},
+			Pad: test.Pad{ID: "GPIO_182", DW0: 0x44000400, DW1: 0x0001d000, Ownership: common.Acpi},
 			Macro: test.Macro{
 				Short: "PAD_CFG_NF_IOSSTATE(GPIO_182, DN_20K, DEEP, NF1, HIZCRx0),",
 				Long:  "_PAD_CFG_STRUCT(GPIO_182, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF), PAD_PULL(DN_20K) | PAD_IOSSTATE(HIZCRx0)),",
 			},
 		},
 		{ /* LPC_CLKOUT0 - LPC_CLKOUT0 */
-			Pad: test.Pad{ID: "LPC_CLKOUT0", DW0: 0x44000400, DW1: 0x00020100, Ownership: 0},
+			Pad: test.Pad{ID: "LPC_CLKOUT0", DW0: 0x44000400, DW1: 0x00020100, Ownership: common.Acpi},
 			Macro: test.Macro{
 				Short: "PAD_CFG_NF_IOSSTATE_IOSTERM(LPC_CLKOUT0, NONE, DEEP, NF1, HIZCRx1, DISPUPD),",
 				Long:  "_PAD_CFG_STRUCT(LPC_CLKOUT0, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF), PAD_IOSSTATE(HIZCRx1) | PAD_IOSTERM(DISPUPD)),",
 			},
 		},
-	}.Run(t, "INTEL-APOLLO-PCH/PAD-MAP", apollolake)
+	}.Run(t, "INTEL-APOLLO-PCH/PAD-MAP")
 
 	test.Suite{
 		{
-			Pad: test.Pad{ID: "GPP_1xx", DW0: 0xBFFFFFFF, DW1: 0xFFFFFFFF, Ownership: 1},
+			Pad: test.Pad{ID: "GPP_1xx", DW0: 0xBFFFFFFF, DW1: 0xFFFFFFFF, Ownership: common.Driver},
 			Macro: test.Macro{
 				Short: "PAD_CFG_NF_IOSSTATE_IOSTERM(GPP_1xx, NATIVE, PLTRST, NF7, IGNORE, ENPU),",
 				Long:  "_PAD_CFG_STRUCT(GPP_1xx, PAD_FUNC(NF7) | PAD_RESET(PLTRST) | PAD_TRIG(EDGE_BOTH) | PAD_IRQ_ROUTE(IOAPIC) | PAD_IRQ_ROUTE(SCI) | PAD_IRQ_ROUTE(SMI) | PAD_IRQ_ROUTE(NMI) | PAD_RX_POL(INVERT) | PAD_BUF(TX_RX_DISABLE) | (1 << 29) | (1 << 28) | (1 << 1) | 1, PAD_CFG1_TOL_1V8PAD_PULL(NATIVE) | PAD_IOSSTATE(IGNORE) | PAD_IOSTERM(ENPU) | PAD_CFG_OWN_GPIO(DRIVER)),",
 			},
 		},
-	}.Run(t, "INTEL-APOLLO-PCH/MASK", apollolake)
+	}.Run(t, "INTEL-APOLLO-PCH/MASK")
 
 	test.Suite{
 		{
-			Pad: test.Pad{ID: "GPP_2xx", DW0: 0x00000000, DW1: 0x00000000, Ownership: 0},
+			Pad: test.Pad{ID: "GPP_2xx", DW0: 0x00000000, DW1: 0x00000000, Ownership: common.Acpi},
 			Macro: test.Macro{
 				Short: "PAD_CFG_GPIO_BIDIRECT(GPP_2xx, 0, NONE, PWROK, LEVEL, ACPI),",
 				Long:  "_PAD_CFG_STRUCT(GPP_2xx, PAD_FUNC(GPIO), 0),",
 			},
 		},
-	}.Run(t, "INTEL-APOLLO-PCH/EMRTY", apollolake)
+	}.Run(t, "INTEL-APOLLO-PCH/EMRTY")
 }
diff --git a/util/intelp2m/platforms/apl/macro.go b/util/intelp2m/platforms/apl/macro.go
index 3e5bf74603..f20acc46a3 100644
--- a/util/intelp2m/platforms/apl/macro.go
+++ b/util/intelp2m/platforms/apl/macro.go
@@ -1,43 +1,47 @@
 package apl
 
 import (
-	"fmt"
-	"strconv"
-
 	"review.coreboot.org/coreboot.git/util/intelp2m/config/p2m"
-	"review.coreboot.org/coreboot.git/util/intelp2m/fields"
+	"review.coreboot.org/coreboot.git/util/intelp2m/logs"
 	"review.coreboot.org/coreboot.git/util/intelp2m/platforms/common"
 	"review.coreboot.org/coreboot.git/util/intelp2m/platforms/common/register/bits"
 )
 
 const (
-	PAD_CFG_DW0_RO_FIELDS = (0x1 << 27) | (0x1 << 24) | (0x3 << 21) | (0xf << 16) | 0xfc
-	PAD_CFG_DW1_RO_FIELDS = 0xfffc00ff
+	DW0Mask uint32 = (0b1 << 27) | (0b1 << 24) | (0b11 << 21) | (0b1111 << 16) | 0b11111100
+	DW1Mask uint32 = 0b11111111111111000000000011111111
 )
 
-const (
-	PULL_NONE   = 0x0 // 0 000: none
-	PULL_DN_5K  = 0x2 // 0 010: 5k wpd (Only available on SMBus GPIOs)
-	PULL_DN_20K = 0x4 // 0 100: 20k wpd
-	// PULL_NONE = 0x8  // 1 000: none
-	PULL_UP_1K  = 0x9 // 1 001: 1k wpu (Only available on I2C GPIOs)
-	PULL_UP_2K  = 0xb // 1 011: 2k wpu (Only available on I2C GPIOs)
-	PULL_UP_20K = 0xc // 1 100: 20k wpu
-	PULL_UP_667 = 0xd // 1 101: 1k & 2k wpu (Only available on I2C GPIOs)
-	PULL_NATIVE = 0xf // 1 111: (optional) Native controller selected by Pad Mode
-)
+type BasePlatform struct {
+	common.BasePlatform
+}
 
-type PlatformSpecific struct{}
+func InitBasePlatform(dw0, dw0mask uint32, dw1, dw1mask uint32) BasePlatform {
+	return BasePlatform{common.InitBasePlatform(dw0, dw0mask, dw1, dw1mask)}
+}
 
-// RemmapRstSrc - remmap Pad Reset Source Config
-// remmap is not required because it is the same as common.
-func (PlatformSpecific) RemmapRstSrc() {}
+func GetPlatform(dw0, dw1 uint32) common.PlatformIf {
+	p := InitBasePlatform(dw0, DW0Mask, dw1, DW1Mask)
+	return &p
+}
+
+// RemapRstSrc() remaps Pad Reset Source Config
+func (p *BasePlatform) RemapRstSrc(m *common.Macro) {}
+
+// Pull() adds The Pad Termination (TERM) parameter from PAD_CFG_DW1 to the macro
+func (p *BasePlatform) Pull(m *common.Macro) {
+	const (
+		PULL_NONE   = 0b0000 // 0 000: none
+		PULL_DN_5K  = 0b0010 // 0 010: 5k wpd (Only available on SMBus GPIOs)
+		PULL_DN_20K = 0b0100 // 0 100: 20k wpd
+		// PULL_NONE = 0b1000  // 1 000: none
+		PULL_UP_1K  = 0b1001 // 1 001: 1k wpu (Only available on I2C GPIOs)
+		PULL_UP_2K  = 0b1011 // 1 011: 2k wpu (Only available on I2C GPIOs)
+		PULL_UP_20K = 0b1100 // 1 100: 20k wpu
+		PULL_UP_667 = 0b1101 // 1 101: 1k & 2k wpu (Only available on I2C GPIOs)
+		PULL_NATIVE = 0b1111 // 1 111: (optional) Native controller selected by Pad Mode
+	)
 
-// Adds The Pad Termination (TERM) parameter from DW1 to the macro as a new argument
-// return: macro
-func (PlatformSpecific) Pull() {
-	macro := common.GetMacro()
-	dw1 := macro.GetRegisterDW1()
 	var pull = map[uint32]string{
 		PULL_NONE:   "NONE",
 		PULL_DN_5K:  "DN_5K",
@@ -48,259 +52,221 @@ func (PlatformSpecific) Pull() {
 		PULL_UP_667: "UP_667",
 		PULL_NATIVE: "NATIVE",
 	}
-	str, exist := pull[dw1.GetTermination()]
+	dw1 := p.GetRegisterDW1()
+	term, exist := pull[dw1.GetTermination()]
 	if !exist {
-		str = strconv.Itoa(int(dw1.GetTermination()))
-		fmt.Println("Error", macro.PadIdGet(), " invalid TERM value = ", str)
+		term = "INVALID"
+		logs.Errorf("%s: DW1 %s: invalid termination value 0b%b",
+			dw1, m.GetPadId(), dw1.GetTermination())
 	}
-	macro.Separator().Add(str)
+	m.Separator().Add(term)
 }
 
 // Generate macro to cause peripheral IRQ when configured in GPIO input mode
-func ioApicRoute() bool {
-	macro := common.GetMacro()
-	dw0 := macro.GetRegisterDW0()
-	dw1 := macro.GetRegisterDW1()
-	if dw0.GetGPIOInputRouteIOxAPIC() == 0 {
+func ioApicRoute(p *BasePlatform, m *common.Macro) bool {
+	if dw0 := p.GetRegisterDW0(); dw0.GetGPIOInputRouteIOxAPIC() == 0 {
 		return false
 	}
-	macro.Add("_APIC")
+	m.Add("_APIC")
+	dw1 := p.GetRegisterDW1()
 	if dw1.GetIOStandbyState() != 0 || dw1.GetIOStandbyTermination() != 0 {
 		// e.g. H1_PCH_INT_ODL
 		// PAD_CFG_GPI_APIC_IOS(GPIO_63, NONE, DEEP, LEVEL, INVERT, TxDRxE, DISPUPD),
-		macro.Add("_IOS(").Id().Pull().Rstsrc().Trig().Invert().IOSstate().IOTerm()
+		m.Add("_IOS(").Id().Pull().Rstsrc().Trig().Invert().IOSstate().IOTerm()
 	} else {
 		// PAD_CFG_GPI_APIC(pad, pull, rst, trig, inv)
-		macro.Add("(").Id().Pull().Rstsrc().Trig().Invert().Add("),")
+		m.Add("(").Id().Pull().Rstsrc().Trig().Invert().Add("),")
 	}
-	macro.Add("),")
+	m.Add("),")
 	return true
 }
 
 // Generate macro to cause NMI when configured in GPIO input mode
-func nmiRoute() bool {
-	macro := common.GetMacro()
-	if macro.GetRegisterDW0().GetGPIOInputRouteNMI() == 0 {
+func nmiRoute(p *BasePlatform, m *common.Macro) bool {
+	if dw0 := p.GetRegisterDW0(); dw0.GetGPIOInputRouteNMI() == 0 {
 		return false
 	}
 	// e.g. PAD_CFG_GPI_NMI(GPIO_24, UP_20K, DEEP, LEVEL, INVERT),
-	macro.Add("_NMI").Add("(").Id().Pull().Rstsrc().Trig().Invert().Add("),")
+	m.Add("_NMI").Add("(").Id().Pull().Rstsrc().Trig().Invert().Add("),")
 	return true
 }
 
 // Generate macro to cause SCI when configured in GPIO input mode
-func sciRoute() bool {
-	macro := common.GetMacro()
-	dw0 := macro.GetRegisterDW0()
-	dw1 := macro.GetRegisterDW1()
+func sciRoute(p *BasePlatform, m *common.Macro) bool {
+	dw0 := p.GetRegisterDW0()
 	if dw0.GetGPIOInputRouteSCI() == 0 {
 		return false
 	}
+
+	dw1 := p.GetRegisterDW1()
 	if dw1.GetIOStandbyState() != 0 || dw1.GetIOStandbyTermination() != 0 {
 		// PAD_CFG_GPI_SCI_IOS(GPIO_141, NONE, DEEP, EDGE_SINGLE, INVERT, IGNORE, DISPUPD),
-		macro.Add("_SCI_IOS")
-		macro.Add("(").Id().Pull().Rstsrc().Trig().Invert().IOSstate().IOTerm()
+		m.Add("_SCI_IOS")
+		m.Add("(").Id().Pull().Rstsrc().Trig().Invert().IOSstate().IOTerm()
 	} else if dw0.GetRXLevelEdgeConfiguration()&0x1 != 0 {
 		// e.g. PAD_CFG_GPI_ACPI_SCI(GPP_G2, NONE, DEEP, YES),
-		macro.Add("_ACPI_SCI").Add("(").Id().Pull().Rstsrc().Invert()
+		m.Add("_ACPI_SCI").Add("(").Id().Pull().Rstsrc().Invert()
 	} else {
 		// e.g. PAD_CFG_GPI_SCI(GPP_B18, UP_20K, PLTRST, LEVEL, INVERT),
-		macro.Add("_SCI").Add("(").Id().Pull().Rstsrc().Trig().Invert()
+		m.Add("_SCI").Add("(").Id().Pull().Rstsrc().Trig().Invert()
 	}
-	macro.Add("),")
+	m.Add("),")
 	return true
 }
 
 // Generate macro to cause SMI when configured in GPIO input mode
-func smiRoute() bool {
-	macro := common.GetMacro()
-	dw0 := macro.GetRegisterDW0()
-	dw1 := macro.GetRegisterDW1()
+func smiRoute(p *BasePlatform, m *common.Macro) bool {
+	dw0 := p.GetRegisterDW0()
 	if dw0.GetGPIOInputRouteSMI() == 0 {
 		return false
 	}
+	dw1 := p.GetRegisterDW1()
 	if dw1.GetIOStandbyState() != 0 || dw1.GetIOStandbyTermination() != 0 {
 		// PAD_CFG_GPI_SMI_IOS(GPIO_41, UP_20K, DEEP, EDGE_SINGLE, NONE, IGNORE, SAME),
-		macro.Add("_SMI_IOS")
-		macro.Add("(").Id().Pull().Rstsrc().Trig().Invert().IOSstate().IOTerm()
+		m.Add("_SMI_IOS")
+		m.Add("(").Id().Pull().Rstsrc().Trig().Invert().IOSstate().IOTerm()
 	} else if dw0.GetRXLevelEdgeConfiguration()&0x1 != 0 {
 		// e.g. PAD_CFG_GPI_ACPI_SMI(GPP_I3, NONE, DEEP, YES),
-		macro.Add("_ACPI_SMI").Add("(").Id().Pull().Rstsrc().Invert()
+		m.Add("_ACPI_SMI").Add("(").Id().Pull().Rstsrc().Invert()
 	} else {
 		// e.g. PAD_CFG_GPI_SMI(GPP_E3, NONE, PLTRST, EDGE_SINGLE, NONE),
-		macro.Add("_SMI").Add("(").Id().Pull().Rstsrc().Trig().Invert()
+		m.Add("_SMI").Add("(").Id().Pull().Rstsrc().Trig().Invert()
 	}
-	macro.Add("),")
+	m.Add("),")
 	return true
 }
 
-// Generate macro for GPI port
-func (PlatformSpecific) GpiMacroAdd() {
+// AddGpiMacro() adds PAD_CFG_GPI macro with arguments
+func (p *BasePlatform) AddGpiMacro(m *common.Macro) {
 	var ids []string
 
-	macro := common.GetMacro()
-	macro.Set("PAD_CFG_GPI")
-	for routeid, isRoute := range map[string]func() bool{
+	m.Set("PAD_CFG_GPI")
+	for routeid, isRoute := range map[string]func(*BasePlatform, *common.Macro) bool{
 		"IOAPIC": ioApicRoute,
 		"SCI":    sciRoute,
 		"SMI":    smiRoute,
 		"NMI":    nmiRoute,
 	} {
-		if isRoute() {
+		if isRoute(p, m) {
 			ids = append(ids, routeid)
 		}
 	}
 
 	switch config, argc := p2m.Config, len(ids); argc {
 	case 0:
-		dw1 := macro.GetRegisterDW1()
+		dw1 := p.GetRegisterDW1()
 		isIOStandbyStateUsed := dw1.GetIOStandbyState() != 0
 		isIOStandbyTerminationUsed := dw1.GetIOStandbyTermination() != 0
 		if isIOStandbyStateUsed && !isIOStandbyTerminationUsed {
-			macro.Add("_TRIG_IOSSTATE_OWN(")
+			m.Add("_TRIG_IOSSTATE_OWN(")
 			// PAD_CFG_GPI_TRIG_IOSSTATE_OWN(pad, pull, rst, trig, iosstate, own)
-			macro.Id().Pull().Rstsrc().Trig().IOSstate().Own().Add("),")
+			m.Id().Pull().Rstsrc().Trig().IOSstate().Own().Add("),")
 		} else if isIOStandbyTerminationUsed {
-			macro.Add("_TRIG_IOS_OWN(")
+			m.Add("_TRIG_IOS_OWN(")
 			// PAD_CFG_GPI_TRIG_IOS_OWN(pad, pull, rst, trig, iosstate, iosterm, own)
-			macro.Id().Pull().Rstsrc().Trig().IOSstate().IOTerm().Own().Add("),")
+			m.Id().Pull().Rstsrc().Trig().IOSstate().IOTerm().Own().Add("),")
 		} else {
 			// PAD_CFG_GPI_TRIG_OWN(pad, pull, rst, trig, own)
-			macro.Add("_TRIG_OWN(").Id().Pull().Rstsrc().Trig().Own().Add("),")
+			m.Add("_TRIG_OWN(").Id().Pull().Rstsrc().Trig().Own().Add("),")
 		}
 	case 1:
 		// GPI with IRQ route
 		if config.IgnoredFields {
-			macro.SetPadOwnership(common.PAD_OWN_ACPI)
+			m.SetOwnershipAcpi()
 		}
 	case 2:
 		// PAD_CFG_GPI_DUAL_ROUTE(pad, pull, rst, trig, inv, route1, route2)
-		macro.Set("PAD_CFG_GPI_DUAL_ROUTE(").Id().Pull().Rstsrc().Trig().Invert()
-		macro.Add(", " + ids[0] + ", " + ids[1] + "),")
+		m.Set("PAD_CFG_GPI_DUAL_ROUTE(").Id().Pull().Rstsrc().Trig().Invert()
+		m.Add(", " + ids[0] + ", " + ids[1] + "),")
 		if config.IgnoredFields {
-			macro.SetPadOwnership(common.PAD_OWN_ACPI)
+			m.SetOwnershipAcpi()
 		}
 	default:
 		// Clear the control mask so that the check fails and "Advanced" macro is
 		// generated
-		macro.GetRegisterDW0().CntrMaskFieldsClear(bits.All32)
+		dw0 := p.GetRegisterDW0()
+		dw0.CntrMaskFieldsClear(bits.All32)
 	}
 }
 
-// Adds PAD_CFG_GPO macro with arguments
-func (PlatformSpecific) GpoMacroAdd() {
-	macro := common.GetMacro()
-	dw0 := macro.GetRegisterDW0()
-	dw1 := macro.GetRegisterDW1()
-	term := dw1.GetTermination()
-
-	macro.Set("PAD_CFG")
+// AddGpoMacro() adds PAD_CFG_GPO macro with arguments
+func (p *BasePlatform) AddGpoMacro(m *common.Macro) {
+	m.Set("PAD_CFG")
+	dw1 := p.GetRegisterDW1()
 	if dw1.GetIOStandbyState() != 0 || dw1.GetIOStandbyTermination() != 0 {
 		// PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_91, 0, DEEP, NONE, Tx0RxDCRx0, DISPUPD),
 		// PAD_CFG_GPO_IOSSTATE_IOSTERM(pad, val, rst, pull, iosstate, ioterm)
-		macro.Add("_GPO_IOSSTATE_IOSTERM(").Id().Val().Rstsrc().Pull().IOSstate().IOTerm()
+		m.Add("_GPO_IOSSTATE_IOSTERM(").Id().Val().Rstsrc().Pull().IOSstate().IOTerm()
 	} else {
+		term := dw1.GetTermination()
 		if term != 0 {
 			// e.g. PAD_CFG_TERM_GPO(GPP_B23, 1, DN_20K, DEEP),
 			// PAD_CFG_TERM_GPO(pad, val, pull, rst)
-			macro.Add("_TERM")
+			m.Add("_TERM")
 		}
-		macro.Add("_GPO(").Id().Val()
+		m.Add("_GPO(").Id().Val()
 		if term != 0 {
-			macro.Pull()
+			m.Pull()
 		}
-		macro.Rstsrc()
+		m.Rstsrc()
 	}
-	macro.Add("),")
+	m.Add("),")
 
-	if dw0.GetRXLevelEdgeConfiguration() != bits.TrigOFF {
+	if dw0 := p.GetRegisterDW0(); dw0.GetRXLevelEdgeConfiguration() != bits.TrigOFF {
 		// ignore if trig = OFF is not set
 		dw0.CntrMaskFieldsClear(bits.DW0[bits.DW0RxLevelEdgeConfiguration])
 	}
 }
 
-// Adds PAD_CFG_NF macro with arguments
-func (PlatformSpecific) NativeFunctionMacroAdd() {
-	macro := common.GetMacro()
-	dw1 := macro.GetRegisterDW1()
+// AddNativeFunctionMacro() adds PAD_CFG_NF macro with arguments
+func (p *BasePlatform) AddNativeFunctionMacro(m *common.Macro) {
+	m.Set("PAD_CFG_NF")
+	dw1 := p.GetRegisterDW1()
 	isIOStandbyStateUsed := dw1.GetIOStandbyState() != 0
 	isIOStandbyTerminationUsed := dw1.GetIOStandbyTermination() != 0
-
-	macro.Set("PAD_CFG_NF")
 	if !isIOStandbyTerminationUsed && isIOStandbyStateUsed {
 		if dw1.GetIOStandbyState() == bits.IOStateStandbyIgnore {
 			// PAD_CFG_NF_IOSTANDBY_IGNORE(PMU_SLP_S0_B, NONE, DEEP, NF1),
-			macro.Add("_IOSTANDBY_IGNORE(").Id().Pull().Rstsrc().Padfn()
+			m.Add("_IOSTANDBY_IGNORE(").Id().Pull().Rstsrc().Padfn()
 		} else {
 			// PAD_CFG_NF_IOSSTATE(GPIO_22, UP_20K, DEEP, NF2, TxDRxE),
-			macro.Add("_IOSSTATE(").Id().Pull().Rstsrc().Padfn().IOSstate()
+			m.Add("_IOSSTATE(").Id().Pull().Rstsrc().Padfn().IOSstate()
 		}
 	} else if isIOStandbyTerminationUsed {
 		// PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_103, NATIVE, DEEP, NF1, MASK, SAME),
-		macro.Add("_IOSSTATE_IOSTERM(").Id().Pull().Rstsrc().Padfn().IOSstate().IOTerm()
+		m.Add("_IOSSTATE_IOSTERM(").Id().Pull().Rstsrc().Padfn().IOSstate().IOTerm()
 	} else {
 		// e.g. PAD_CFG_NF(GPP_D23, NONE, DEEP, NF1)
-		macro.Add("(").Id().Pull().Rstsrc().Padfn()
+		m.Add("(").Id().Pull().Rstsrc().Padfn()
 	}
-	macro.Add("),")
+	m.Add("),")
 
-	if dw0 := macro.GetRegisterDW0(); dw0.GetGPIORxTxDisableStatus() != 0 {
+	if dw0 := p.GetRegisterDW0(); dw0.GetGPIORxTxDisableStatus() != 0 {
 		// Since the bufbis parameter will be ignored for NF, we should clear
 		// the corresponding bits in the control mask.
 		dw0.CntrMaskFieldsClear(bits.DW0[bits.DW0RxTxBufDisable])
 	}
 }
 
-// Adds PAD_NC macro
-func (PlatformSpecific) NoConnMacroAdd() {
-	macro := common.GetMacro()
-
-	dw0, dw1 := macro.GetRegisterDW0(), macro.GetRegisterDW1()
-	if dw1.GetIOStandbyState() == bits.IOStateTxDRxE {
-
-		// See comments in sunrise/macro.go : NoConnMacroAdd()
+// AddNoConnMacro() adds PAD_NC macro
+func (p *BasePlatform) AddNoConnMacro(m *common.Macro) {
+	if dw1 := p.GetRegisterDW1(); dw1.GetIOStandbyState() == bits.IOStateTxDRxE {
+		dw0 := p.GetRegisterDW0()
+		// See comments in sunrise/m.go : AddNoConnMacro()
 		if dw0.GetRXLevelEdgeConfiguration() != bits.TrigOFF {
 			dw0.CntrMaskFieldsClear(bits.DW0[bits.DW0RxLevelEdgeConfiguration])
 		}
 		if dw0.GetResetConfig() != 1 { // 1 = RST_DEEP
 			dw0.CntrMaskFieldsClear(bits.DW0[bits.DW0PadRstCfg])
 		}
-
 		// PAD_NC(OSC_CLK_OUT_1, DN_20K)
-		macro.Set("PAD_NC").Add("(").Id().Pull().Add("),")
+		m.Set("PAD_NC").Add("(").Id().Pull().Add("),")
 		return
 	}
 	// PAD_CFG_GPIO_HI_Z(GPIO_81, UP_20K, DEEP, HIZCRx0, DISPUPD),
-	macro.Set("PAD_CFG_GPIO_")
-	if macro.IsOwnershipDriver() {
+	if m.Set("PAD_CFG_GPIO_"); m.IsOwnershipDriver() {
 		// PAD_CFG_GPIO_DRIVER_HI_Z(GPIO_55, UP_20K, DEEP, HIZCRx1, ENPU),
-		macro.Add("DRIVER_")
+		m.Add("DRIVER_")
 	}
-	macro.Add("HI_Z(").Id().Pull().Rstsrc().IOSstate().IOTerm().Add("),")
-}
-
-// GenMacro - generate pad macro
-// dw0Val : DW0 config register value
-// dw1Val : DW1 config register value
-// return: string of macro
-func (PlatformSpecific) GenMacro(id string, dw0Val uint32, dw1Val uint32, ownership uint8) string {
-	macro := common.GetInstanceMacro(
-		PlatformSpecific{},
-		fields.InterfaceGet(),
-	)
-	macro.Clear()
-
-	dw0 := macro.GetRegisterDW0()
-	dw0.CntrMaskFieldsClear(bits.All32)
-
-	dw1 := macro.GetRegisterDW1()
-	dw1.CntrMaskFieldsClear(bits.All32)
-
-	dw0.Value = dw0Val
-	dw1.Value = dw1Val
-	dw0.ReadOnly = PAD_CFG_DW0_RO_FIELDS
-	dw1.ReadOnly = PAD_CFG_DW1_RO_FIELDS
-
-	macro.PadIdSet(id).SetPadOwnership(ownership)
-	return macro.Generate()
+	m.Add("HI_Z(").Id().Pull().Rstsrc().IOSstate().IOTerm().Add("),")
 }
diff --git a/util/intelp2m/platforms/apl/template.go b/util/intelp2m/platforms/apl/template.go
index 36040cab96..014431d18a 100644
--- a/util/intelp2m/platforms/apl/template.go
+++ b/util/intelp2m/platforms/apl/template.go
@@ -2,10 +2,9 @@ package apl
 
 import "review.coreboot.org/coreboot.git/util/intelp2m/platforms/common"
 
-// KeywordCheck - This function is used to filter parsed lines of the configuration file and
-// returns true if the keyword is contained in the line.
-// line      : string from the configuration file
-func (PlatformSpecific) KeywordCheck(line string) bool {
+// CheckKeyword() parses lines of the configuration file and returns true if the keyword is
+// contained in the line
+func CheckKeyword(line string) bool {
 	isIncluded, _ := common.KeywordsCheck(line,
 		"GPIO_", "TCK", "TRST_B", "TMS", "TDI", "CX_PMODE", "CX_PREQ_B", "JTAGX", "CX_PRDY_B",
 		"TDO", "CNV_BRI_DT", "CNV_BRI_RSP", "CNV_RGI_DT", "CNV_RGI_RSP", "SVID0_ALERT_B",
diff --git a/util/intelp2m/platforms/cnl/cnl_test.go b/util/intelp2m/platforms/cnl/cnl_test.go
index e7fe0d546f..8efaedf117 100644
--- a/util/intelp2m/platforms/cnl/cnl_test.go
+++ b/util/intelp2m/platforms/cnl/cnl_test.go
@@ -3,105 +3,103 @@ package cnl_test
 import (
 	"testing"
 
-	"review.coreboot.org/coreboot.git/util/intelp2m/platforms/cnl"
-	"review.coreboot.org/coreboot.git/util/intelp2m/platforms/snr"
+	"review.coreboot.org/coreboot.git/util/intelp2m/config/p2m"
+	"review.coreboot.org/coreboot.git/util/intelp2m/platforms/common"
 	"review.coreboot.org/coreboot.git/util/intelp2m/platforms/test"
 )
 
 func TestGenMacro(t *testing.T) {
-	cannonlake := cnl.PlatformSpecific{
-		InheritanceMacro: snr.PlatformSpecific{},
-	}
+	p2m.Config.Platform = p2m.Cannon
 	test.Suite{
 		{
-			Pad: test.Pad{ID: "GPP_A1", DW0: 0x11111111, DW1: 0x11111111, Ownership: 1},
+			Pad: test.Pad{ID: "GPP_A1", DW0: 0x11111111, DW1: 0x11111111, Ownership: common.Driver},
 			Macro: test.Macro{
 				Short: "PAD_CFG_NF(GPP_A1, DN_20K, PWROK, NF4),",
 				Long:  "_PAD_CFG_STRUCT(GPP_A1, PAD_FUNC(NF4) | PAD_IRQ_ROUTE(IOAPIC) | PAD_BUF(TX_DISABLE) | (1 << 28) | 1, PAD_PULL(DN_20K) | PAD_IOSSTATE(Tx1RxDCRx1) | PAD_IOSTERM(DISPUPD) | PAD_CFG_OWN_GPIO(DRIVER)),",
 			},
 		},
 		{
-			Pad: test.Pad{ID: "GPP_B2", DW0: 0x22222222, DW1: 0x22222222, Ownership: 0},
+			Pad: test.Pad{ID: "GPP_B2", DW0: 0x22222222, DW1: 0x22222222, Ownership: common.Acpi},
 			Macro: test.Macro{
 				Short: "PAD_CFG_TERM_GPO(GPP_B2, 0, INVALID, PWROK),",
 				Long:  "_PAD_CFG_STRUCT(GPP_B2, PAD_FUNC(GPIO) | PAD_TRIG(EDGE_SINGLE) | PAD_IRQ_ROUTE(NMI) | PAD_BUF(RX_DISABLE) | (1 << 29) | (1 << 1), PAD_CFG1_TOL_1V8PAD_PULL(INVALID) | PAD_IOSSTATE(HIZCRx1) | PAD_IOSTERM(ENPD)),",
 			},
 		},
 		{
-			Pad: test.Pad{ID: "GPP_G3", DW0: 0x44444444, DW1: 0x44444444, Ownership: 1},
+			Pad: test.Pad{ID: "GPP_G3", DW0: 0x44444444, DW1: 0x44444444, Ownership: common.Driver},
 			Macro: test.Macro{
 				Short: "PAD_CFG_NF(GPP_G3, INVALID, DEEP, NF1),",
 				Long:  "_PAD_CFG_STRUCT(GPP_G3, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_IRQ_ROUTE(SMI), PAD_PULL(INVALID) | PAD_IOSSTATE(Tx0RxDCRx0) | PAD_CFG_OWN_GPIO(DRIVER)),",
 			},
 		},
 		{
-			Pad: test.Pad{ID: "GPP_D4", DW0: 0x88888888, DW1: 0x88888888, Ownership: 0},
+			Pad: test.Pad{ID: "GPP_D4", DW0: 0x88888888, DW1: 0x88888888, Ownership: common.Acpi},
 			Macro: test.Macro{
 				Short: "PAD_CFG_NF(GPP_D4, DN_5K, PLTRST, NF2),",
 				Long:  "_PAD_CFG_STRUCT(GPP_D4, PAD_FUNC(NF2) | PAD_RESET(PLTRST) | PAD_IRQ_ROUTE(SCI) | PAD_RX_POL(INVERT), PAD_PULL(DN_5K) | PAD_IOSSTATE(Tx0RxDCRx1)),",
 			},
 		},
-	}.Run(t, "INTEL-CANNON-LAKE-PCH/SLIDING-ONE-IN-NIBBLE-TEST", cannonlake)
+	}.Run(t, "INTEL-CANNON-LAKE-PCH/SLIDING-ONE-IN-NIBBLE-TEST")
 
 	test.Suite{
 		{
-			Pad: test.Pad{ID: "GPP_F5", DW0: 0xEEEEEEEE, DW1: 0xEEEEEEEE, Ownership: 1},
+			Pad: test.Pad{ID: "GPP_F5", DW0: 0xEEEEEEEE, DW1: 0xEEEEEEEE, Ownership: common.Driver},
 			Macro: test.Macro{
 				Short: "PAD_CFG_NF_1V8(GPP_F5, UP_2K, RSMRST, NF3),",
 				Long:  "_PAD_CFG_STRUCT(GPP_F5, PAD_FUNC(NF3) | PAD_RESET(RSMRST) | PAD_TRIG(EDGE_BOTH) | PAD_IRQ_ROUTE(SCI) | PAD_IRQ_ROUTE(SMI) | PAD_IRQ_ROUTE(NMI) | PAD_RX_POL(INVERT) | PAD_BUF(RX_DISABLE) | (1 << 29) | (1 << 1), PAD_CFG1_TOL_1V8PAD_PULL(UP_2K) | PAD_IOSSTATE(ERROR) | PAD_IOSTERM(ENPD) | PAD_CFG_OWN_GPIO(DRIVER)),",
 			},
 		},
 		{
-			Pad: test.Pad{ID: "GPP_H6", DW0: 0xDDDDDDDD, DW1: 0xDDDDDDDD, Ownership: 0},
+			Pad: test.Pad{ID: "GPP_H6", DW0: 0xDDDDDDDD, DW1: 0xDDDDDDDD, Ownership: common.Acpi},
 			Macro: test.Macro{
 				Short: "PAD_CFG_NF(GPP_H6, INVALID, RSMRST, NF7),",
 				Long:  "_PAD_CFG_STRUCT(GPP_H6, PAD_FUNC(NF7) | PAD_RESET(RSMRST) | PAD_TRIG(OFF) | PAD_IRQ_ROUTE(IOAPIC) | PAD_IRQ_ROUTE(SCI) | PAD_IRQ_ROUTE(SMI) | PAD_RX_POL(INVERT) | PAD_BUF(TX_DISABLE) | (1 << 28) | 1, PAD_PULL(INVALID) | PAD_IOSSTATE(HIZCRx0) | PAD_IOSTERM(DISPUPD)),",
 			},
 		},
 		{
-			Pad: test.Pad{ID: "GPD7", DW0: 0xBBBBBBBB, DW1: 0xBBBBBBBB, Ownership: 1},
+			Pad: test.Pad{ID: "GPD7", DW0: 0xBBBBBBBB, DW1: 0xBBBBBBBB, Ownership: common.Driver},
 			Macro: test.Macro{
 				Short: "PAD_CFG_NF_1V8(GPD7, INVALID, PLTRST, NF6),",
 				Long:  "_PAD_CFG_STRUCT(GPD7, PAD_FUNC(NF6) | PAD_RESET(PLTRST) | PAD_TRIG(EDGE_SINGLE) | PAD_IRQ_ROUTE(IOAPIC) | PAD_IRQ_ROUTE(SCI) | PAD_IRQ_ROUTE(NMI) | PAD_RX_POL(INVERT) | PAD_BUF(TX_RX_DISABLE) | (1 << 29) | (1 << 28) | (1 << 1) | 1, PAD_CFG1_TOL_1V8PAD_PULL(INVALID) | PAD_IOSSTATE(ERROR) | PAD_IOSTERM(ENPU) | PAD_CFG_OWN_GPIO(DRIVER)),",
 			},
 		},
 		{
-			Pad: test.Pad{ID: "GPP_C8", DW0: 0x77777777, DW1: 0x77777777, Ownership: 0},
+			Pad: test.Pad{ID: "GPP_C8", DW0: 0x77777777, DW1: 0x77777777, Ownership: common.Acpi},
 			Macro: test.Macro{
 				Short: "PAD_CFG_NF_1V8(GPP_C8, UP_667, DEEP, NF5),",
 				Long:  "_PAD_CFG_STRUCT(GPP_C8, PAD_FUNC(NF5) | PAD_RESET(DEEP) | PAD_TRIG(EDGE_BOTH) | PAD_IRQ_ROUTE(IOAPIC) | PAD_IRQ_ROUTE(SMI) | PAD_IRQ_ROUTE(NMI) | PAD_BUF(TX_RX_DISABLE) | (1 << 29) | (1 << 28) | (1 << 1) | 1, PAD_CFG1_TOL_1V8PAD_PULL(UP_667) | PAD_IOSSTATE(ERROR) | PAD_IOSTERM(ENPU)),",
 			},
 		},
-	}.Run(t, "INTEL-CANNON-LAKE-PCH/SLIDING-ZERO-IN-NIBBLE-TEST", cannonlake)
+	}.Run(t, "INTEL-CANNON-LAKE-PCH/SLIDING-ZERO-IN-NIBBLE-TEST")
 
 	test.Suite{
 		{
-			Pad: test.Pad{ID: "GPP_E9", DW0: 0x33333333, DW1: 0x33333333, Ownership: 1},
+			Pad: test.Pad{ID: "GPP_E9", DW0: 0x33333333, DW1: 0x33333333, Ownership: common.Driver},
 			Macro: test.Macro{
 				Short: "PAD_CFG_NF_1V8(GPP_E9, UP_20K, RSMRST, NF4),",
 				Long:  "_PAD_CFG_STRUCT(GPP_E9, PAD_FUNC(NF4) | PAD_RESET(RSMRST) | PAD_TRIG(EDGE_SINGLE) | PAD_IRQ_ROUTE(IOAPIC) | PAD_IRQ_ROUTE(NMI) | PAD_BUF(TX_RX_DISABLE) | (1 << 29) | (1 << 28) | (1 << 1) | 1, PAD_CFG1_TOL_1V8PAD_PULL(UP_20K) | PAD_IOSSTATE(ERROR) | PAD_IOSTERM(ENPU) | PAD_CFG_OWN_GPIO(DRIVER)),",
 			},
 		},
 		{
-			Pad: test.Pad{ID: "GPP_A10", DW0: 0x66666666, DW1: 0x66666666, Ownership: 0},
+			Pad: test.Pad{ID: "GPP_A10", DW0: 0x66666666, DW1: 0x66666666, Ownership: common.Acpi},
 			Macro: test.Macro{
 				Short: "PAD_CFG_NF_1V8(GPP_A10, UP_1K, DEEP, NF1),",
 				Long:  "_PAD_CFG_STRUCT(GPP_A10, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(EDGE_BOTH) | PAD_IRQ_ROUTE(SMI) | PAD_IRQ_ROUTE(NMI) | PAD_BUF(RX_DISABLE) | (1 << 29) | (1 << 1), PAD_CFG1_TOL_1V8PAD_PULL(UP_1K) | PAD_IOSSTATE(TxDRxE) | PAD_IOSTERM(ENPD)),",
 			},
 		},
 		{
-			Pad: test.Pad{ID: "GPP_B11", DW0: 0xCCCCCCCC, DW1: 0xCCCCCCCC, Ownership: 1},
+			Pad: test.Pad{ID: "GPP_B11", DW0: 0xCCCCCCCC, DW1: 0xCCCCCCCC, Ownership: common.Driver},
 			Macro: test.Macro{
 				Short: "PAD_CFG_NF(GPP_B11, INVALID, RSMRST, NF3),",
 				Long:  "_PAD_CFG_STRUCT(GPP_B11, PAD_FUNC(NF3) | PAD_RESET(RSMRST) | PAD_TRIG(OFF) | PAD_IRQ_ROUTE(SCI) | PAD_IRQ_ROUTE(SMI) | PAD_RX_POL(INVERT), PAD_PULL(INVALID) | PAD_IOSSTATE(Tx1RxDCRx0) | PAD_CFG_OWN_GPIO(DRIVER)),",
 			},
 		},
 		{
-			Pad: test.Pad{ID: "GPP_G12", DW0: 0x99999999, DW1: 0x99999999, Ownership: 0},
+			Pad: test.Pad{ID: "GPP_G12", DW0: 0x99999999, DW1: 0x99999999, Ownership: common.Acpi},
 			Macro: test.Macro{
 				Short: "PAD_CFG_NF(GPP_G12, INVALID, PLTRST, NF6),",
 				Long:  "_PAD_CFG_STRUCT(GPP_G12, PAD_FUNC(NF6) | PAD_RESET(PLTRST) | PAD_IRQ_ROUTE(IOAPIC) | PAD_IRQ_ROUTE(SCI) | PAD_RX_POL(INVERT) | PAD_BUF(TX_DISABLE) | (1 << 28) | 1, PAD_PULL(INVALID) | PAD_IOSSTATE(Tx1RxE) | PAD_IOSTERM(DISPUPD)),",
 			},
 		},
-	}.Run(t, "INTEL-CANNON-LAKE-PCH/SLIDING-ONE-ONE-IN-NIBBLE-TEST", cannonlake)
+	}.Run(t, "INTEL-CANNON-LAKE-PCH/SLIDING-ONE-ONE-IN-NIBBLE-TEST")
 }
diff --git a/util/intelp2m/platforms/cnl/macro.go b/util/intelp2m/platforms/cnl/macro.go
index ab524f5e15..7f5421510c 100644
--- a/util/intelp2m/platforms/cnl/macro.go
+++ b/util/intelp2m/platforms/cnl/macro.go
@@ -1,149 +1,140 @@
 package cnl
 
 import (
-	"fmt"
 	"strings"
 
 	"review.coreboot.org/coreboot.git/util/intelp2m/config/p2m"
-	"review.coreboot.org/coreboot.git/util/intelp2m/fields"
+	"review.coreboot.org/coreboot.git/util/intelp2m/logs"
 	"review.coreboot.org/coreboot.git/util/intelp2m/platforms/common"
 	"review.coreboot.org/coreboot.git/util/intelp2m/platforms/common/register/bits"
 	"review.coreboot.org/coreboot.git/util/intelp2m/platforms/snr"
 )
 
 const (
-	PAD_CFG_DW0_RO_FIELDS = (0x1 << 27) | (0x1 << 24) | (0x3 << 21) | (0xf << 16) | 0xfc
-	PAD_CFG_DW1_RO_FIELDS = 0xfdffc3ff
+	DW0Mask uint32 = (0b1 << 27) | (0b1 << 24) | (0b11 << 21) | (0b1111 << 16) | 0b11111100
+	DW1Mask uint32 = 0b11111101111111111100001111111111
 )
 
-type InheritanceMacro interface {
-	GpoMacroAdd()
-	NativeFunctionMacroAdd()
-	NoConnMacroAdd()
+type BasePlatform struct {
+	// based on the Sunrise platform
+	snr.BasePlatform
 }
 
-type PlatformSpecific struct {
-	InheritanceMacro
-	InheritanceTemplate
+func InitBasePlatform(dw0, dw0mask uint32, dw1, dw1mask uint32) BasePlatform {
+	return BasePlatform{snr.InitBasePlatform(dw0, dw0mask, dw1, dw1mask)}
 }
 
-// RemmapRstSrc - remmap Pad Reset Source Config
-func (PlatformSpecific) RemmapRstSrc() {
-	macro := common.GetMacro()
-	if strings.Contains(macro.PadIdGet(), "GPP_A") ||
-		strings.Contains(macro.PadIdGet(), "GPP_B") ||
-		strings.Contains(macro.PadIdGet(), "GPP_G") {
+func GetPlatform(dw0, dw1 uint32) common.PlatformIf {
+	p := InitBasePlatform(dw0, DW0Mask, dw1, DW1Mask)
+	return &p
+}
+
+// Override BasePlatform.RemapRstSrc()
+func (p *BasePlatform) RemapRstSrc(m *common.Macro) {
+	if strings.Contains(m.GetPadId(), "GPP_A") ||
+		strings.Contains(m.GetPadId(), "GPP_B") ||
+		strings.Contains(m.GetPadId(), "GPP_G") {
 		// See reset map for the Cannonlake Groups the Community 0:
 		// https://github.com/coreboot/coreboot/blob/master/src/soc/intel/cannonlake/gpio.c#L14
 		// remmap is not required because it is the same as common.
 		return
 	}
 
-	dw0 := macro.GetRegisterDW0()
-	var remapping = map[uint32]uint32{
-		0: bits.RstCfgRSMRST << bits.DW0PadRstCfg,
-		1: bits.RstCfgDEEP << bits.DW0PadRstCfg,
-		2: bits.RstCfgPLTRST << bits.DW0PadRstCfg,
+	dw0 := p.GetRegisterDW0()
+	remapping := map[uint32]uint32{
+		0b00: bits.RstCfgRSMRST << bits.DW0PadRstCfg,
+		0b01: bits.RstCfgDEEP << bits.DW0PadRstCfg,
+		0b10: bits.RstCfgPLTRST << bits.DW0PadRstCfg,
 	}
-	resetsrc, valid := remapping[dw0.GetResetConfig()]
+	source, valid := remapping[dw0.GetResetConfig()]
 	if valid {
-		// dw0.SetResetConfig(resetsrc)
-		ResetConfigFieldVal := (dw0.Value & 0x3fffffff) | remapping[dw0.GetResetConfig()]
-		dw0.Value = ResetConfigFieldVal
+		dw0.Value &= 0x3fffffff
+		dw0.Value |= source
 	} else {
-		fmt.Println("Invalid Pad Reset Config [ 0x", resetsrc, " ] for ", macro.PadIdGet())
+		logs.Errorf("%s: skip re-mapping: DW0 %s: invalid reset config source value 0b%b",
+			m.GetPadId(), dw0, dw0.GetResetConfig())
 	}
 	mask := bits.DW0[bits.DW0PadRstCfg]
 	dw0.CntrMaskFieldsClear(mask)
 }
 
-// Adds The Pad Termination (TERM) parameter from PAD_CFG_DW1 to the macro
-// as a new argument
-func (PlatformSpecific) Pull() {
-	macro := common.GetMacro()
-	dw1 := macro.GetRegisterDW1()
+// Override BasePlatform.Pull()
+func (p *BasePlatform) Pull(m *common.Macro) {
+	dw1 := p.GetRegisterDW1()
 	var pull = map[uint32]string{
-		0x0: "NONE",
-		0x2: "DN_5K",
-		0x4: "DN_20K",
-		0x9: "UP_1K",
-		0xa: "UP_5K",
-		0xb: "UP_2K",
-		0xc: "UP_20K",
-		0xd: "UP_667",
-		0xf: "NATIVE",
+		0b0000: "NONE",
+		0b0010: "DN_5K",
+		0b0100: "DN_20K",
+		0b1001: "UP_1K",
+		0b1010: "UP_5K",
+		0b1011: "UP_2K",
+		0b1100: "UP_20K",
+		0b1101: "UP_667",
+		0b1111: "NATIVE",
 	}
-	str, valid := pull[dw1.GetTermination()]
+	term, valid := pull[dw1.GetTermination()]
 	if !valid {
-		str = "INVALID"
-		fmt.Println("Error",
-			macro.PadIdGet(),
-			" invalid TERM value = ",
-			int(dw1.GetTermination()))
+		term = "INVALID"
+		logs.Errorf("%s: DW1 %s: invalid termination value 0b%b",
+			dw1, m.GetPadId(), dw1.GetTermination())
 	}
-	macro.Separator().Add(str)
+	m.Separator().Add(term)
 }
 
-// Generate macro to cause peripheral IRQ when configured in GPIO input mode
-func ioApicRoute() bool {
-	macro := common.GetMacro()
-	dw0 := macro.GetRegisterDW0()
+// ioApicRoute() generate macro to cause peripheral IRQ when configured in GPIO input mode
+func ioApicRoute(p *BasePlatform, m *common.Macro) bool {
+	dw0 := p.GetRegisterDW0()
 	if dw0.GetGPIOInputRouteIOxAPIC() == 0 {
 		return false
 	}
 
-	macro.Add("_APIC")
+	m.Add("_APIC")
 	// PAD_CFG_GPI_APIC(pad, pull, rst, trig, inv)
-	macro.Add("(").Id().Pull().Rstsrc().Trig().Invert().Add("),")
+	m.Add("(").Id().Pull().Rstsrc().Trig().Invert().Add("),")
 	return true
 }
 
-// Generate macro to cause NMI when configured in GPIO input mode
-func nmiRoute() bool {
-	macro := common.GetMacro()
-	if macro.GetRegisterDW0().GetGPIOInputRouteNMI() == 0 {
+// nmiRoute() generate macro to cause NMI when configured in GPIO input mode
+func nmiRoute(p *BasePlatform, m *common.Macro) bool {
+	if dw0 := p.GetRegisterDW0(); dw0.GetGPIOInputRouteNMI() == 0 {
 		return false
 	}
 	// PAD_CFG_GPI_NMI(GPIO_24, UP_20K, DEEP, LEVEL, INVERT),
-	macro.Add("_NMI").Add("(").Id().Pull().Rstsrc().Trig().Invert().Add("),")
+	m.Add("_NMI").Add("(").Id().Pull().Rstsrc().Trig().Invert().Add("),")
 	return true
 }
 
-// Generate macro to cause SCI when configured in GPIO input mode
-func sciRoute() bool {
-	macro := common.GetMacro()
-	if macro.GetRegisterDW0().GetGPIOInputRouteSCI() == 0 {
+// sciRoute() generate macro to cause SCI when configured in GPIO input mode
+func sciRoute(p *BasePlatform, m *common.Macro) bool {
+	if dw0 := p.GetRegisterDW0(); dw0.GetGPIOInputRouteSCI() == 0 {
 		return false
 	}
 	// PAD_CFG_GPI_SCI(pad, pull, rst, trig, inv)
-	macro.Add("_SCI").Add("(").Id().Pull().Rstsrc().Trig().Invert().Add("),")
+	m.Add("_SCI").Add("(").Id().Pull().Rstsrc().Trig().Invert().Add("),")
 	return true
 }
 
-// Generate macro to cause SMI when configured in GPIO input mode
-func smiRoute() bool {
-	macro := common.GetMacro()
-
-	if macro.GetRegisterDW0().GetGPIOInputRouteSMI() == 0 {
+// smiRoute() generates macro to cause SMI when configured in GPIO input mode
+func smiRoute(p *BasePlatform, m *common.Macro) bool {
+	if dw0 := p.GetRegisterDW0(); dw0.GetGPIOInputRouteSMI() == 0 {
 		return false
 	}
 	// PAD_CFG_GPI_SMI(pad, pull, rst, trig, inv)
-	macro.Add("_SMI").Add("(").Id().Pull().Rstsrc().Trig().Invert().Add("),")
+	m.Add("_SMI").Add("(").Id().Pull().Rstsrc().Trig().Invert().Add("),")
 	return true
 }
 
-// Adds PAD_CFG_GPI macro with arguments
-func (PlatformSpecific) GpiMacroAdd() {
-	macro := common.GetMacro()
+// Override BasePlatform.AddGpiMacro()
+func (p *BasePlatform) AddGpiMacro(m *common.Macro) {
 	var ids []string
-	macro.Set("PAD_CFG_GPI")
-	for routeid, isRoute := range map[string]func() bool{
+	m.Set("PAD_CFG_GPI")
+	for routeid, isRoute := range map[string]func(*BasePlatform, *common.Macro) bool{
 		"IOAPIC": ioApicRoute,
 		"SCI":    sciRoute,
 		"SMI":    smiRoute,
 		"NMI":    nmiRoute,
 	} {
-		if isRoute() {
+		if isRoute(p, m) {
 			ids = append(ids, routeid)
 		}
 	}
@@ -151,69 +142,26 @@ func (PlatformSpecific) GpiMacroAdd() {
 	switch argc := len(ids); argc {
 	case 0:
 		// e.g. PAD_CFG_GPI_TRIG_OWN(pad, pull, rst, trig, own)
-		macro.Add("_TRIG_OWN").Add("(").Id().Pull().Rstsrc().Trig().Own().Add("),")
+		m.Add("_TRIG_OWN").Add("(").Id().Pull().Rstsrc().Trig().Own().Add("),")
 	case 1:
 		// GPI with IRQ route
 		if p2m.Config.IgnoredFields {
 			// Set Host Software Ownership to ACPI mode
-			macro.SetPadOwnership(common.PAD_OWN_ACPI)
+			m.SetOwnershipAcpi()
 		}
 
 	case 2:
 		// PAD_CFG_GPI_DUAL_ROUTE(pad, pull, rst, trig, inv, route1, route2)
-		macro.Set("PAD_CFG_GPI_DUAL_ROUTE(").Id().Pull().Rstsrc().Trig().Invert()
-		macro.Add(", " + ids[0] + ", " + ids[1] + "),")
+		m.Set("PAD_CFG_GPI_DUAL_ROUTE(").Id().Pull().Rstsrc().Trig().Invert()
+		m.Add(", " + ids[0] + ", " + ids[1] + "),")
 		if p2m.Config.IgnoredFields {
 			// Set Host Software Ownership to ACPI mode
-			macro.SetPadOwnership(common.PAD_OWN_ACPI)
+			m.SetOwnershipAcpi()
 		}
 	default:
 		// Clear the control mask so that the check fails and "Advanced" macro is
 		// generated
-		macro.GetRegisterDW0().CntrMaskFieldsClear(bits.All32)
+		dw0 := p.GetRegisterDW0()
+		dw0.CntrMaskFieldsClear(bits.All32)
 	}
 }
-
-// Adds PAD_CFG_GPO macro with arguments
-func (platform PlatformSpecific) GpoMacroAdd() {
-	platform.InheritanceMacro.GpoMacroAdd()
-}
-
-// Adds PAD_CFG_NF macro with arguments
-func (platform PlatformSpecific) NativeFunctionMacroAdd() {
-	platform.InheritanceMacro.NativeFunctionMacroAdd()
-}
-
-// Adds PAD_NC macro
-func (platform PlatformSpecific) NoConnMacroAdd() {
-	platform.InheritanceMacro.NoConnMacroAdd()
-}
-
-// GenMacro - generate pad macro
-// dw0Val : DW0 config register value
-// dw1Val : DW1 config register value
-// return: string of macro
-func (PlatformSpecific) GenMacro(id string, dw0Val uint32, dw1Val uint32, ownership uint8) string {
-	macro := common.GetInstanceMacro(
-		PlatformSpecific{
-			InheritanceMacro: snr.PlatformSpecific{},
-		},
-		fields.InterfaceGet(),
-	)
-	macro.Clear()
-
-	dw0 := macro.GetRegisterDW0()
-	dw0.CntrMaskFieldsClear(bits.All32)
-
-	dw1 := macro.GetRegisterDW1()
-	dw1.CntrMaskFieldsClear(bits.All32)
-
-	dw0.Value = dw0Val
-	dw1.Value = dw1Val
-
-	dw0.ReadOnly = PAD_CFG_DW0_RO_FIELDS
-	dw1.ReadOnly = PAD_CFG_DW1_RO_FIELDS
-
-	macro.PadIdSet(id).SetPadOwnership(ownership)
-	return macro.Generate()
-}
diff --git a/util/intelp2m/platforms/cnl/template.go b/util/intelp2m/platforms/cnl/template.go
index 886a59a920..4c4192d6cc 100644
--- a/util/intelp2m/platforms/cnl/template.go
+++ b/util/intelp2m/platforms/cnl/template.go
@@ -1,14 +1,11 @@
 package cnl
 
-type InheritanceTemplate interface {
-	KeywordCheck(line string) bool
-}
+import "review.coreboot.org/coreboot.git/util/intelp2m/platforms/common"
 
-// Group: "GPP_A", "GPP_B", "GPP_G", "GPP_D", "GPP_F", "GPP_H", "GPD", "GPP_C", "GPP_E"
-
-// KeywordCheck - This function is used to filter parsed lines of the configuration file and
-// returns true if the keyword is contained in the line.
-// line      : string from the configuration file
-func (platform PlatformSpecific) KeywordCheck(line string) bool {
-	return platform.InheritanceTemplate.KeywordCheck(line)
+// CheckKeyword() parses lines of the configuration file and returns true if the keyword is
+// contained in the line
+// "GPP_A", "GPP_B", "GPP_G", "GPP_D", "GPP_F", "GPP_H", "GPD", "GPP_C", "GPP_E"
+func CheckKeyword(line string) bool {
+	included, _ := common.KeywordsCheck(line, "GPP_", "GPD")
+	return included
 }
diff --git a/util/intelp2m/platforms/common/common.go b/util/intelp2m/platforms/common/common.go
new file mode 100644
index 0000000000..57719842ca
--- /dev/null
+++ b/util/intelp2m/platforms/common/common.go
@@ -0,0 +1,25 @@
+package common
+
+import (
+	"review.coreboot.org/coreboot.git/util/intelp2m/platforms/common/register"
+)
+
+type BasePlatform struct {
+	dw0 register.DW0
+	dw1 register.DW1
+}
+
+func InitBasePlatform(dw0, dw0Mask uint32, dw1, dw1Mask uint32) BasePlatform {
+	return BasePlatform{
+		register.SetVal[register.DW0](dw0, dw0Mask),
+		register.SetVal[register.DW1](dw1, dw1Mask),
+	}
+}
+
+func (p *BasePlatform) GetRegisterDW0() *register.DW0 {
+	return &p.dw0
+}
+
+func (p *BasePlatform) GetRegisterDW1() *register.DW1 {
+	return &p.dw1
+}
diff --git a/util/intelp2m/platforms/common/macro.go b/util/intelp2m/platforms/common/macro.go
index 56b147cee2..0f544acb08 100644
--- a/util/intelp2m/platforms/common/macro.go
+++ b/util/intelp2m/platforms/common/macro.go
@@ -3,133 +3,113 @@ package common
 import (
 	"fmt"
 	"strconv"
-	"sync"
 
 	"review.coreboot.org/coreboot.git/util/intelp2m/config/p2m"
+	"review.coreboot.org/coreboot.git/util/intelp2m/logs"
 	"review.coreboot.org/coreboot.git/util/intelp2m/platforms/common/register"
 	"review.coreboot.org/coreboot.git/util/intelp2m/platforms/common/register/bits"
 )
 
-type Fields interface {
-	DecodeDW0()
-	DecodeDW1()
-	GenerateString()
-}
-
 const (
-	PAD_OWN_ACPI   = 0
-	PAD_OWN_DRIVER = 1
+	Driver bool = true
+	Acpi   bool = false
 )
 
-// PlatformSpecific - platform-specific interface
-type PlatformSpecific interface {
-	RemmapRstSrc()
-	Pull()
-	GpiMacroAdd()
-	GpoMacroAdd()
-	NativeFunctionMacroAdd()
-	NoConnMacroAdd()
+type FieldsIf interface {
+	DecodeDW0(*Macro) *Macro
+	DecodeDW1(*Macro) *Macro
+	GenerateMacro(*Macro) *Macro
+}
+
+type PlatformIf interface {
+	RemapRstSrc(*Macro)
+	Pull(*Macro)
+	AddGpiMacro(*Macro)
+	AddGpoMacro(*Macro)
+	AddNativeFunctionMacro(*Macro)
+	AddNoConnMacro(*Macro)
+	GetRegisterDW0() *register.DW0
+	GetRegisterDW1() *register.DW1
 }
 
-// Macro - contains macro information and methods
-// Platform : platform-specific interface
-// padID    : pad ID string
-// str      : macro string entirely
-// Reg      : structure of configuration register values and their masks
 type Macro struct {
-	Platform  PlatformSpecific
-	DW0       register.DW0
-	DW1       register.DW1
-	padID     string
-	str       string
-	ownership uint8
-	Fields
+	line      string
+	id        string
+	ownership bool
+	Platform  PlatformIf
+	Fields    FieldsIf
 }
 
-var instanceMacro *Macro
-var once sync.Once
-
-// GetInstance returns singleton
-func GetInstanceMacro(p PlatformSpecific, f Fields) *Macro {
-	once.Do(func() {
-		instanceMacro = &Macro{Platform: p, Fields: f}
-	})
-	return instanceMacro
-}
-
-func GetMacro() *Macro {
-	return GetInstanceMacro(nil, nil)
-}
-
-func (macro *Macro) PadIdGet() string {
-	return macro.padID
-}
-
-func (macro *Macro) PadIdSet(padid string) *Macro {
-	macro.padID = padid
-	return macro
-}
-
-func (macro *Macro) SetPadOwnership(own uint8) *Macro {
-	macro.ownership = own
-	return macro
-}
-
-func (macro *Macro) IsOwnershipDriver() bool {
-	return macro.ownership == PAD_OWN_DRIVER
-}
-
-func (macro *Macro) GetRegisterDW0() *register.DW0 {
-	return &macro.DW0
-}
-
-func (macro *Macro) GetRegisterDW1() *register.DW1 {
-	return &macro.DW1
-}
-
-// add a string to macro
-func (macro *Macro) Add(str string) *Macro {
-	macro.str += str
-	return macro
-}
-
-// set a string in a macro instead of its previous contents
-func (macro *Macro) Set(str string) *Macro {
-	macro.str = str
-	return macro
-}
-
-// get macro string
-func (macro *Macro) Get() string {
-	return macro.str
-}
-
-// set a string in a macro instead of its previous contents
-func (macro *Macro) Clear() *Macro {
-	macro.Set("")
-	return macro
-}
-
-// Adds PAD Id to the macro as a new argument
-// return: Macro
-func (macro *Macro) Id() *Macro {
-	return macro.Add(macro.padID)
-}
-
-// Add Separator to macro if needed
-func (macro *Macro) Separator() *Macro {
-	str := macro.Get()
-	c := str[len(str)-1]
-	if c != '(' && c != '_' {
-		macro.Add(", ")
+func CreateFrom(id string, ownership bool, pi PlatformIf, fi FieldsIf) Macro {
+	return Macro{
+		id:        id,
+		ownership: ownership,
+		Platform:  pi,
+		Fields:    fi,
 	}
-	return macro
 }
 
-// Adds the PADRSTCFG parameter from DW0 to the macro as a new argument
-// return: Macro
-func (macro *Macro) Rstsrc() *Macro {
-	dw0 := macro.GetRegisterDW0()
+func (m *Macro) String() string {
+	return m.line
+}
+
+func (m *Macro) GetPadId() string {
+	return m.id
+}
+
+func (m Macro) IsOwnershipDriver() bool {
+	return m.ownership
+}
+
+func (m *Macro) SetOwnershipAcpi() {
+	m.ownership = Acpi
+}
+
+func (m *Macro) SetOwnershipDriver() {
+	m.ownership = Driver
+}
+
+func (m *Macro) Add(str string) *Macro {
+	m.line += str
+	return m
+}
+
+func (m *Macro) Set(str string) *Macro {
+	m.line = str
+	return m
+}
+
+func (m *Macro) Clear() *Macro {
+	m.line = ""
+	return m
+}
+
+// Id() adds Pad Id to the macro string
+func (m *Macro) Id() *Macro {
+	return m.Add(m.id)
+}
+
+// Separator() adds separator ", " to macro if needed
+func (m *Macro) Separator() *Macro {
+	line := m.line
+	c := line[len(line)-1]
+	if c != '(' && c != '_' {
+		m.Add(", ")
+	}
+	return m
+}
+
+// or - Set " | " if its needed
+func (m *Macro) Or() *Macro {
+	if str := m.line; str[len(str)-1] == ')' {
+		m.Add(" | ")
+	}
+	return m
+}
+
+// Rstsrc() adds PADRSTCFG parameter
+func (m *Macro) Rstsrc() *Macro {
+	dw0 := m.Platform.GetRegisterDW0()
 	resetsrc := map[uint32]string{
 		0b00: "PWROK",
 		0b01: "DEEP",
@@ -138,29 +118,28 @@ func (macro *Macro) Rstsrc() *Macro {
 	}
 	source, exist := resetsrc[dw0.GetResetConfig()]
 	if !exist {
+		logs.Errorf("%s: ResetConfig error: map does not contain %d",
+			m.id, dw0.GetResetConfig())
 		source = "ERROR"
 	}
-	return macro.Separator().Add(source)
+	return m.Separator().Add(source)
 }
 
-// Adds The Pad Termination (TERM) parameter from DW1 to the macro as a new argument
-// return: Macro
-func (macro *Macro) Pull() *Macro {
-	macro.Platform.Pull()
-	return macro
+// Pull() adds Pad Termination TERM parameter
+func (m *Macro) Pull() *Macro {
+	m.Platform.Pull(m)
+	return m
 }
 
-// Adds Pad GPO value to macro string as a new argument
-// return: Macro
-func (macro *Macro) Val() *Macro {
-	dw0 := macro.GetRegisterDW0()
-	return macro.Separator().Add(strconv.Itoa(int(dw0.GetGPIOTXState())))
+// Val() adds pad GPO value to macro string
+func (m *Macro) Val() *Macro {
+	dw0 := m.Platform.GetRegisterDW0()
+	return m.Separator().Add(strconv.Itoa(int(dw0.GetGPIOTXState())))
 }
 
-// Adds Pad GPO value to macro string as a new argument
-// return: Macro
-func (macro *Macro) Trig() *Macro {
-	dw0 := macro.GetRegisterDW0()
+// Trig() adds Pad GPO value to macro string
+func (m *Macro) Trig() *Macro {
+	dw0 := m.Platform.GetRegisterDW0()
 	trig := map[uint32]string{
 		0b00: "LEVEL",
 		0b01: "EDGE_SINGLE",
@@ -169,24 +148,24 @@ func (macro *Macro) Trig() *Macro {
 	}
 	level, exist := trig[dw0.GetRXLevelEdgeConfiguration()]
 	if !exist {
+		logs.Errorf("%s: RXLevelEdgeConfig error: map does not contain %d",
+			m.id, dw0.GetRXLevelEdgeConfiguration())
 		level = "ERROR"
 	}
-	return macro.Separator().Add(level)
+	return m.Separator().Add(level)
 }
 
-// Adds Pad Polarity Inversion Stage (RXINV) to macro string as a new argument
-// return: Macro
-func (macro *Macro) Invert() *Macro {
-	if macro.GetRegisterDW0().GetRxInvert() != 0 {
-		return macro.Separator().Add("INVERT")
+// Invert() adds Pad Polarity Inversion Stage (RXINV) to macro string
+func (m *Macro) Invert() *Macro {
+	if dw0 := m.Platform.GetRegisterDW0(); dw0.GetRxInvert() != 0 {
+		return m.Separator().Add("INVERT")
 	}
-	return macro.Separator().Add("NONE")
+	return m.Separator().Add("NONE")
 }
 
-// Adds input/output buffer state
-// return: Macro
-func (macro *Macro) Bufdis() *Macro {
-	dw0 := macro.GetRegisterDW0()
+// Bufdis() adds input/output buffer state
+func (m *Macro) Bufdis() *Macro {
+	dw0 := m.Platform.GetRegisterDW0()
 	states := map[uint32]string{
 		0b00: "NO_DISABLE",    // both buffers are enabled
 		0b01: "TX_DISABLE",    // output buffer is disabled
@@ -195,34 +174,33 @@ func (macro *Macro) Bufdis() *Macro {
 	}
 	state, exist := states[dw0.GetGPIORxTxDisableStatus()]
 	if !exist {
+		logs.Errorf("%s: GPIORxTxDisableStatus error: map does not contain %d",
+			m.id, dw0.GetGPIORxTxDisableStatus())
 		state = "ERROR"
 	}
-	return macro.Separator().Add(state)
+	return m.Separator().Add(state)
 }
 
-// Adds macro to set the host software ownership
-// return: Macro
-func (macro *Macro) Own() *Macro {
-	if macro.IsOwnershipDriver() {
-		return macro.Separator().Add("DRIVER")
+// Own() adds macro to set the host software ownership
+func (m *Macro) Own() *Macro {
+	if m.IsOwnershipDriver() {
+		return m.Separator().Add("DRIVER")
 	}
-	return macro.Separator().Add("ACPI")
+	return m.Separator().Add("ACPI")
 }
 
-// Adds pad native function (PMODE) as a new argument
-// return: Macro
-func (macro *Macro) Padfn() *Macro {
-	dw0 := macro.GetRegisterDW0()
+// Padfn() adds pad native function (PMODE)
+func (m *Macro) Padfn() *Macro {
+	dw0 := m.Platform.GetRegisterDW0()
 	if number := dw0.GetPadMode(); number != 0 {
-		return macro.Separator().Add(fmt.Sprintf("NF%d", number))
+		return m.Separator().Add(fmt.Sprintf("NF%d", number))
 	}
 	// GPIO used only for PAD_FUNC(x) macro
-	return macro.Add("GPIO")
+	return m.Add("GPIO")
 }
 
-// Add a line to the macro that defines IO Standby State
-// return: macro
-func (macro *Macro) IOSstate() *Macro {
+// IOSstate() adds a line to the macro that defines IO Standby State
+func (m *Macro) IOSstate() *Macro {
 	states := map[uint32]string{
 		bits.IOStateTxLASTRxE:     "TxLASTRxE",
 		bits.IOStateTx0RxDCRx0:    "Tx0RxDCRx0",
@@ -236,19 +214,19 @@ func (macro *Macro) IOSstate() *Macro {
 		bits.IOStateTxDRxE:        "TxDRxE",
 		bits.IOStateStandbyIgnore: "IGNORE",
 	}
-	dw1 := macro.GetRegisterDW1()
+	dw1 := m.Platform.GetRegisterDW1()
 	state, exist := states[dw1.GetIOStandbyState()]
 	if !exist {
-		// ignore setting for incorrect value
+		logs.Errorf("%s: IOStandbyState error: map does not contain %d",
+			m.id, dw1.GetIOStandbyState())
 		state = "ERROR"
 	}
-	return macro.Separator().Add(state)
+	return m.Separator().Add(state)
 }
 
-// Add a line to the macro that defines IO Standby Termination
-// return: macro
-func (macro *Macro) IOTerm() *Macro {
-	dw1 := macro.GetRegisterDW1()
+// IOTerm() add a line to the macro that defines IO Standby Termination
+func (m *Macro) IOTerm() *Macro {
+	dw1 := m.Platform.GetRegisterDW1()
 	terminations := map[uint32]string{
 		bits.IOTermSAME:    "SAME",
 		bits.IOTermDISPUPD: "DISPUPD",
@@ -257,87 +235,94 @@ func (macro *Macro) IOTerm() *Macro {
 	}
 	termination, exist := terminations[dw1.GetIOStandbyTermination()]
 	if !exist {
+		logs.Errorf("%s: IOStandbyTermination error: map does not contain %d",
+			m.id, dw1.GetIOStandbyTermination())
 		termination = "ERROR"
 	}
-	return macro.Separator().Add(termination)
+	return m.Separator().Add(termination)
 }
 
 // Check created macro
-func (macro *Macro) check() *Macro {
-	dw0 := macro.GetRegisterDW0()
+func (m *Macro) Check() *Macro {
+	dw0 := m.Platform.GetRegisterDW0()
 	if !dw0.MaskCheck() {
-		return macro.GenerateFields()
+		return m.GenerateFields()
 	}
-	return macro
+	return m
 }
 
-// or - Set " | " if its needed
-func (macro *Macro) Or() *Macro {
-	if str := macro.Get(); str[len(str)-1] == ')' {
-		macro.Add(" | ")
-	}
-	return macro
-}
-
-func (macro *Macro) DecodeIgnoredFieldsDW0() *Macro {
+func (m *Macro) DecodeIgnoredFieldsDW0() *Macro {
 	if p2m.Config.Field == p2m.FspFlds {
-		return macro
+		logs.Infof("%s: decoding of extracted fields is not applied for fsp", m.id)
+		return m
+	} else if m.Fields == nil {
+		logs.Errorf("%s: field collection is not set in the macro structure", m.id)
+		return m
 	}
-	dw0 := macro.GetRegisterDW0()
+
+	dw0 := m.Platform.GetRegisterDW0()
 	if ignored := dw0.IgnoredFieldsGet(); ignored != 0 {
 		saved := dw0.Value
 		dw0.Value = ignored
-		macro.Add("/* DW0: ")
-		macro.Fields.DecodeDW0()
-		macro.Add(" - IGNORED */\n")
+		m.Add("/* DW0: ").Fields.DecodeDW0(m).Add(" - IGNORED */\n")
 		dw0.Value = saved
 	}
-	return macro
+
+	return m
 }
 
-func (macro *Macro) DecodeIgnoredFieldsDW1() *Macro {
+func (m *Macro) DecodeIgnoredFieldsDW1() *Macro {
 	if p2m.Config.Field == p2m.FspFlds {
-		return macro
+		logs.Infof("%s: decoding of extracted fields is not applied for fsp", m.id)
+		return m
+	} else if m.Fields == nil {
+		logs.Errorf("%s: field collection is not set in the macro structure", m.id)
+		return m
 	}
-	dw1 := macro.GetRegisterDW1()
+
+	dw1 := m.Platform.GetRegisterDW1()
 	if ignored := dw1.IgnoredFieldsGet(); ignored != 0 {
 		saved := dw1.Value
 		dw1.Value = ignored
-		macro.Add("/* DW0: ")
-		macro.DecodeDW1()
-		macro.Add(" - IGNORED */\n")
+		m.Add("/* DW1: ").Fields.DecodeDW1(m).Add(" - IGNORED */\n")
 		dw1.Value = saved
 	}
-	return macro
+
+	return m
 }
 
-// GenerateFields - generate bitfield macros
-func (macro *Macro) GenerateFields() *Macro {
-	dw0 := macro.GetRegisterDW0()
-	dw1 := macro.GetRegisterDW1()
+// GenerateFields() generates bitfield macros
+func (m *Macro) GenerateFields() *Macro {
+	if m.Fields == nil {
+		logs.Errorf("%s: field collection is not set in the macro structure", m.id)
+		return m
+	}
+
+	dw0 := m.Platform.GetRegisterDW0()
+	dw1 := m.Platform.GetRegisterDW1()
 
 	// Get mask of ignored bit fields.
 	dw0Ignored := dw0.IgnoredFieldsGet()
 	dw1Ignored := dw1.IgnoredFieldsGet()
 
 	if p2m.Config.GenLevel != 4 {
-		macro.Clear()
+		m.Clear()
 	}
 	if p2m.Config.GenLevel >= 3 {
-		// Add string of reference macro as a comment
-		reference := macro.Get()
-		macro.Clear()
+		// Add string of reference m as a comment
+		reference := m.line
+		m.Clear()
 		/* DW0 : PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1 - IGNORED */
-		macro.DecodeIgnoredFieldsDW0()
-		macro.DecodeIgnoredFieldsDW1()
+		m.DecodeIgnoredFieldsDW0()
+		m.DecodeIgnoredFieldsDW1()
 		if p2m.Config.GenLevel >= 4 {
 			/* PAD_CFG_NF(GPP_B23, 20K_PD, PLTRST, NF2), */
-			macro.Add("/* ").Add(reference).Add(" */\n")
+			m.Add("/* ").Add(reference).Add(" */\n")
 		}
 	}
 	if p2m.Config.IgnoredFields {
 		// Consider bit fields that should be ignored when regenerating
-		// advansed macros
+		// advansed ms
 		tempVal := dw0.Value & ^dw0Ignored
 		dw0.Value = tempVal
 
@@ -345,76 +330,72 @@ func (macro *Macro) GenerateFields() *Macro {
 		dw1.Value = tempVal
 	}
 
-	macro.Fields.GenerateString()
-	return macro
+	return m.Fields.GenerateMacro(m)
 }
 
-// Generate macro for bi-directional GPIO port
-func (macro *Macro) Bidirection() {
-	dw1 := macro.GetRegisterDW1()
+// Bidirection() generates macro for bi-directional GPIO port
+func (m *Macro) Bidirection() {
+	dw1 := m.Platform.GetRegisterDW1()
 	ios := dw1.GetIOStandbyState() != 0 || dw1.GetIOStandbyTermination() != 0
-	macro.Set("PAD_CFG_GPIO_BIDIRECT")
+	m.Set("PAD_CFG_GPIO_BIDIRECT")
 	if ios {
-		macro.Add("_IOS")
+		m.Add("_IOS")
 	}
 	// PAD_CFG_GPIO_BIDIRECT(pad, val, pull, rst, trig, own)
-	macro.Add("(").Id().Val().Pull().Rstsrc().Trig()
+	m.Add("(").Id().Val().Pull().Rstsrc().Trig()
 	if ios {
 		// PAD_CFG_GPIO_BIDIRECT_IOS(pad, val, pull, rst, trig, iosstate, iosterm, own)
-		macro.IOSstate().IOTerm()
+		m.IOSstate().IOTerm()
 	}
-	macro.Own().Add("),")
+	m.Own().Add("),")
 }
 
-// Gets base string of current macro
-// return: string of macro
-func (macro *Macro) Generate() string {
-	const rxDisable uint32 = 0x2
-	const txDisable uint32 = 0x1
-
-	macro.Platform.RemmapRstSrc()
-	macro.Set("PAD_CFG")
-	if dw0 := macro.GetRegisterDW0(); dw0.GetPadMode() == 0 {
-		// GPIO
-		switch dw0.GetGPIORxTxDisableStatus() {
+// Generate() generates string of macro
+func (m *Macro) Generate() string {
+	m.Platform.RemapRstSrc(m)
+	if dw0 := m.Platform.GetRegisterDW0(); dw0.GetPadMode() == 0 {
+		const txDisable uint32 = 0b01
+		const rxDisable uint32 = 0b10
+		switch m.Set("PAD_CFG"); dw0.GetGPIORxTxDisableStatus() {
 		case txDisable:
-			macro.Platform.GpiMacroAdd() // GPI
+			m.Platform.AddGpiMacro(m) // GPI
 
 		case rxDisable:
-			macro.Platform.GpoMacroAdd() // GPO
+			m.Platform.AddGpoMacro(m) // GPO
 
 		case rxDisable | txDisable:
-			macro.Platform.NoConnMacroAdd() // NC
+			m.Platform.AddNoConnMacro(m) // NC
 
 		default:
-			macro.Bidirection()
+			m.Bidirection()
 		}
 	} else {
-		macro.Platform.NativeFunctionMacroAdd()
+		m.Platform.AddNativeFunctionMacro(m)
 	}
 
 	if p2m.Config.Field != p2m.NoFlds {
-		// Clear control mask to generate advanced macro only
-		return macro.GenerateFields().Get()
+		// clear control mask to generate field collection macro
+		return m.GenerateFields().line
 	}
 
 	if !p2m.Config.AutoCheck {
-		body := macro.Get()
+		body := m.line
 		if p2m.Config.GenLevel >= 3 {
-			macro.Clear()
-			macro.DecodeIgnoredFieldsDW0()
-			macro.DecodeIgnoredFieldsDW1()
-			comment := macro.Get()
+			if m.Fields == nil {
+				logs.Errorf("%s: field collection is not set in the macro structure", m.id)
+				return body
+			}
+			m.Clear()
+			m.DecodeIgnoredFieldsDW0()
+			m.DecodeIgnoredFieldsDW1()
+			comment := m.line
 			if p2m.Config.GenLevel >= 4 {
-				macro.Clear().Add("/* ")
-				macro.Fields.GenerateString()
-				macro.Add(" */\n")
-				comment += macro.Get()
+				comment += m.Clear().Add("/* ").Fields.GenerateMacro(m).Add(" */\n").line
 			}
 			return comment + body
 		}
 		return body
 	}
 
-	return macro.check().Get()
+	return m.Check().line
 }
diff --git a/util/intelp2m/platforms/common/register/helper.go b/util/intelp2m/platforms/common/register/helper.go
new file mode 100644
index 0000000000..9d3dee0c2c
--- /dev/null
+++ b/util/intelp2m/platforms/common/register/helper.go
@@ -0,0 +1,5 @@
+package register
+
+func SetVal[T DW0 | DW1](value uint32, ro uint32) T {
+	return T{Register: Register{Value: value, ReadOnly: ro}}
+}
diff --git a/util/intelp2m/platforms/ebg/ebg_test.go b/util/intelp2m/platforms/ebg/ebg_test.go
index 13e977a063..1dcdf25424 100644
--- a/util/intelp2m/platforms/ebg/ebg_test.go
+++ b/util/intelp2m/platforms/ebg/ebg_test.go
@@ -3,108 +3,103 @@ package ebg_test
 import (
 	"testing"
 
-	"review.coreboot.org/coreboot.git/util/intelp2m/platforms/cnl"
-	"review.coreboot.org/coreboot.git/util/intelp2m/platforms/ebg"
-	"review.coreboot.org/coreboot.git/util/intelp2m/platforms/snr"
+	"review.coreboot.org/coreboot.git/util/intelp2m/config/p2m"
+	"review.coreboot.org/coreboot.git/util/intelp2m/platforms/common"
 	"review.coreboot.org/coreboot.git/util/intelp2m/platforms/test"
 )
 
 func TestGenMacro(t *testing.T) {
-	emmitsburg := ebg.PlatformSpecific{
-		InheritanceMacro: cnl.PlatformSpecific{
-			InheritanceMacro: snr.PlatformSpecific{},
-		},
-	}
+	p2m.Config.Platform = p2m.Emmitsburg
 	test.Suite{
 		{
-			Pad: test.Pad{ID: "GPPC_A1", DW0: 0x11111111, DW1: 0x11111111, Ownership: 1},
+			Pad: test.Pad{ID: "GPPC_A1", DW0: 0x11111111, DW1: 0x11111111, Ownership: common.Driver},
 			Macro: test.Macro{
 				Short: "PAD_CFG_NF(GPPC_A1, DN_20K, RSMRST, NF4),",
 				Long:  "_PAD_CFG_STRUCT(GPPC_A1, PAD_FUNC(NF4) | PAD_RESET(RSMRST) | PAD_IRQ_ROUTE(IOAPIC) | PAD_BUF(TX_DISABLE) | (1 << 28) | 1, PAD_PULL(DN_20K) | PAD_IOSSTATE(Tx1RxDCRx1) | PAD_IOSTERM(DISPUPD) | PAD_CFG_OWN_GPIO(DRIVER)),",
 			},
 		},
 		{
-			Pad: test.Pad{ID: "GPPC_B2", DW0: 0x22222222, DW1: 0x22222222, Ownership: 0},
+			Pad: test.Pad{ID: "GPPC_B2", DW0: 0x22222222, DW1: 0x22222222, Ownership: common.Acpi},
 			Macro: test.Macro{
 				Short: "PAD_CFG_TERM_GPO(GPPC_B2, 0, INVALID, RSMRST),",
 				Long:  "_PAD_CFG_STRUCT(GPPC_B2, PAD_FUNC(GPIO) | PAD_RESET(RSMRST) | PAD_TRIG(EDGE_SINGLE) | PAD_IRQ_ROUTE(NMI) | PAD_BUF(RX_DISABLE) | (1 << 29) | (1 << 1), PAD_CFG1_TOL_1V8PAD_PULL(INVALID) | PAD_IOSSTATE(HIZCRx1) | PAD_IOSTERM(ENPD)),",
 			},
 		},
 		{
-			Pad: test.Pad{ID: "GPPC_C3", DW0: 0x44444444, DW1: 0x44444444, Ownership: 1},
+			Pad: test.Pad{ID: "GPPC_C3", DW0: 0x44444444, DW1: 0x44444444, Ownership: common.Driver},
 			Macro: test.Macro{
 				Short: "PAD_CFG_NF(GPPC_C3, INVALID, DEEP, NF1),",
 				Long:  "_PAD_CFG_STRUCT(GPPC_C3, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_IRQ_ROUTE(SMI), PAD_PULL(INVALID) | PAD_IOSSTATE(Tx0RxDCRx0) | PAD_CFG_OWN_GPIO(DRIVER)),",
 			},
 		},
 		{
-			Pad: test.Pad{ID: "GPP_D4", DW0: 0x88888888, DW1: 0x88888888, Ownership: 0},
+			Pad: test.Pad{ID: "GPP_D4", DW0: 0x88888888, DW1: 0x88888888, Ownership: common.Acpi},
 			Macro: test.Macro{
 				Short: "PAD_CFG_NF(GPP_D4, DN_5K, PLTRST, NF2),",
 				Long:  "_PAD_CFG_STRUCT(GPP_D4, PAD_FUNC(NF2) | PAD_RESET(PLTRST) | PAD_IRQ_ROUTE(SCI) | PAD_RX_POL(INVERT), PAD_PULL(DN_5K) | PAD_IOSSTATE(Tx0RxDCRx1)),",
 			},
 		},
-	}.Run(t, "INTEL-EMMITSBURG-LAKE-PCH/SLIDING-ONE-IN-NIBBLE-TEST", emmitsburg)
+	}.Run(t, "INTEL-EMMITSBURG-LAKE-PCH/SLIDING-ONE-IN-NIBBLE-TEST")
 
 	test.Suite{
 		{
-			Pad: test.Pad{ID: "GPP_E5", DW0: 0xEEEEEEEE, DW1: 0xEEEEEEEE, Ownership: 1},
+			Pad: test.Pad{ID: "GPP_E5", DW0: 0xEEEEEEEE, DW1: 0xEEEEEEEE, Ownership: common.Driver},
 			Macro: test.Macro{
 				Short: "PAD_CFG_NF_1V8(GPP_E5, UP_2K, RSMRST, NF3),",
 				Long:  "_PAD_CFG_STRUCT(GPP_E5, PAD_FUNC(NF3) | PAD_RESET(RSMRST) | PAD_TRIG(EDGE_BOTH) | PAD_IRQ_ROUTE(SCI) | PAD_IRQ_ROUTE(SMI) | PAD_IRQ_ROUTE(NMI) | PAD_RX_POL(INVERT) | PAD_BUF(RX_DISABLE) | (1 << 29) | (1 << 1), PAD_CFG1_TOL_1V8PAD_PULL(UP_2K) | PAD_IOSSTATE(ERROR) | PAD_IOSTERM(ENPD) | PAD_CFG_OWN_GPIO(DRIVER)),",
 			},
 		},
 		{
-			Pad: test.Pad{ID: "GPPC_H6", DW0: 0xDDDDDDDD, DW1: 0xDDDDDDDD, Ownership: 0},
+			Pad: test.Pad{ID: "GPPC_H6", DW0: 0xDDDDDDDD, DW1: 0xDDDDDDDD, Ownership: common.Acpi},
 			Macro: test.Macro{
 				Short: "PAD_CFG_NF(GPPC_H6, INVALID, RSMRST, NF7),",
 				Long:  "_PAD_CFG_STRUCT(GPPC_H6, PAD_FUNC(NF7) | PAD_RESET(RSMRST) | PAD_TRIG(OFF) | PAD_IRQ_ROUTE(IOAPIC) | PAD_IRQ_ROUTE(SCI) | PAD_IRQ_ROUTE(SMI) | PAD_RX_POL(INVERT) | PAD_BUF(TX_DISABLE) | (1 << 28) | 1, PAD_PULL(INVALID) | PAD_IOSSTATE(HIZCRx0) | PAD_IOSTERM(DISPUPD)),",
 			},
 		},
 		{
-			Pad: test.Pad{ID: "GPP_J7", DW0: 0xBBBBBBBB, DW1: 0xBBBBBBBB, Ownership: 1},
+			Pad: test.Pad{ID: "GPP_J7", DW0: 0xBBBBBBBB, DW1: 0xBBBBBBBB, Ownership: common.Driver},
 			Macro: test.Macro{
 				Short: "PAD_CFG_NF_1V8(GPP_J7, INVALID, PLTRST, NF6),",
 				Long:  "_PAD_CFG_STRUCT(GPP_J7, PAD_FUNC(NF6) | PAD_RESET(PLTRST) | PAD_TRIG(EDGE_SINGLE) | PAD_IRQ_ROUTE(IOAPIC) | PAD_IRQ_ROUTE(SCI) | PAD_IRQ_ROUTE(NMI) | PAD_RX_POL(INVERT) | PAD_BUF(TX_RX_DISABLE) | (1 << 29) | (1 << 28) | (1 << 1) | 1, PAD_CFG1_TOL_1V8PAD_PULL(INVALID) | PAD_IOSSTATE(ERROR) | PAD_IOSTERM(ENPU) | PAD_CFG_OWN_GPIO(DRIVER)),",
 			},
 		},
 		{
-			Pad: test.Pad{ID: "GPP_I8", DW0: 0x77777777, DW1: 0x77777777, Ownership: 0},
+			Pad: test.Pad{ID: "GPP_I8", DW0: 0x77777777, DW1: 0x77777777, Ownership: common.Acpi},
 			Macro: test.Macro{
 				Short: "PAD_CFG_NF_1V8(GPP_I8, UP_667, DEEP, NF5),",
 				Long:  "_PAD_CFG_STRUCT(GPP_I8, PAD_FUNC(NF5) | PAD_RESET(DEEP) | PAD_TRIG(EDGE_BOTH) | PAD_IRQ_ROUTE(IOAPIC) | PAD_IRQ_ROUTE(SMI) | PAD_IRQ_ROUTE(NMI) | PAD_BUF(TX_RX_DISABLE) | (1 << 29) | (1 << 28) | (1 << 1) | 1, PAD_CFG1_TOL_1V8PAD_PULL(UP_667) | PAD_IOSSTATE(ERROR) | PAD_IOSTERM(ENPU)),",
 			},
 		},
-	}.Run(t, "INTEL-EMMITSBURG-PCH/SLIDING-ZERO-IN-NIBBLE-TEST", emmitsburg)
+	}.Run(t, "INTEL-EMMITSBURG-PCH/SLIDING-ZERO-IN-NIBBLE-TEST")
 
 	test.Suite{
 		{
-			Pad: test.Pad{ID: "GPP_L9", DW0: 0x33333333, DW1: 0x33333333, Ownership: 1},
+			Pad: test.Pad{ID: "GPP_L9", DW0: 0x33333333, DW1: 0x33333333, Ownership: common.Driver},
 			Macro: test.Macro{
 				Short: "PAD_CFG_NF_1V8(GPP_L9, UP_20K, RSMRST, NF4),",
 				Long:  "_PAD_CFG_STRUCT(GPP_L9, PAD_FUNC(NF4) | PAD_RESET(RSMRST) | PAD_TRIG(EDGE_SINGLE) | PAD_IRQ_ROUTE(IOAPIC) | PAD_IRQ_ROUTE(NMI) | PAD_BUF(TX_RX_DISABLE) | (1 << 29) | (1 << 28) | (1 << 1) | 1, PAD_CFG1_TOL_1V8PAD_PULL(UP_20K) | PAD_IOSSTATE(ERROR) | PAD_IOSTERM(ENPU) | PAD_CFG_OWN_GPIO(DRIVER)),",
 			},
 		},
 		{
-			Pad: test.Pad{ID: "GPP_M10", DW0: 0x66666666, DW1: 0x66666666, Ownership: 0},
+			Pad: test.Pad{ID: "GPP_M10", DW0: 0x66666666, DW1: 0x66666666, Ownership: common.Acpi},
 			Macro: test.Macro{
 				Short: "PAD_CFG_NF_1V8(GPP_M10, UP_1K, DEEP, NF1),",
 				Long:  "_PAD_CFG_STRUCT(GPP_M10, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(EDGE_BOTH) | PAD_IRQ_ROUTE(SMI) | PAD_IRQ_ROUTE(NMI) | PAD_BUF(RX_DISABLE) | (1 << 29) | (1 << 1), PAD_CFG1_TOL_1V8PAD_PULL(UP_1K) | PAD_IOSSTATE(TxDRxE) | PAD_IOSTERM(ENPD)),",
 			},
 		},
 		{
-			Pad: test.Pad{ID: "GPP_N11", DW0: 0xCCCCCCCC, DW1: 0xCCCCCCCC, Ownership: 1},
+			Pad: test.Pad{ID: "GPP_N11", DW0: 0xCCCCCCCC, DW1: 0xCCCCCCCC, Ownership: common.Driver},
 			Macro: test.Macro{
 				Short: "PAD_CFG_NF(GPP_N11, INVALID, RSMRST, NF3),",
 				Long:  "_PAD_CFG_STRUCT(GPP_N11, PAD_FUNC(NF3) | PAD_RESET(RSMRST) | PAD_TRIG(OFF) | PAD_IRQ_ROUTE(SCI) | PAD_IRQ_ROUTE(SMI) | PAD_RX_POL(INVERT), PAD_PULL(INVALID) | PAD_IOSSTATE(Tx1RxDCRx0) | PAD_CFG_OWN_GPIO(DRIVER)),",
 			},
 		},
 		{
-			Pad: test.Pad{ID: "GPPC_A12", DW0: 0x99999999, DW1: 0x99999999, Ownership: 0},
+			Pad: test.Pad{ID: "GPPC_A12", DW0: 0x99999999, DW1: 0x99999999, Ownership: common.Acpi},
 			Macro: test.Macro{
 				Short: "PAD_CFG_NF(GPPC_A12, INVALID, PLTRST, NF6),",
 				Long:  "_PAD_CFG_STRUCT(GPPC_A12, PAD_FUNC(NF6) | PAD_RESET(PLTRST) | PAD_IRQ_ROUTE(IOAPIC) | PAD_IRQ_ROUTE(SCI) | PAD_RX_POL(INVERT) | PAD_BUF(TX_DISABLE) | (1 << 28) | 1, PAD_PULL(INVALID) | PAD_IOSSTATE(Tx1RxE) | PAD_IOSTERM(DISPUPD)),",
 			},
 		},
-	}.Run(t, "INTEL-EMMITSBURG-LAKE-PCH/SLIDING-ONE-ONE-IN-NIBBLE-TEST", emmitsburg)
+	}.Run(t, "INTEL-EMMITSBURG-LAKE-PCH/SLIDING-ONE-ONE-IN-NIBBLE-TEST")
 }
diff --git a/util/intelp2m/platforms/ebg/macro.go b/util/intelp2m/platforms/ebg/macro.go
index 8026a2d484..771d6df6cd 100644
--- a/util/intelp2m/platforms/ebg/macro.go
+++ b/util/intelp2m/platforms/ebg/macro.go
@@ -1,105 +1,47 @@
 package ebg
 
 import (
-	"fmt"
-
-	"review.coreboot.org/coreboot.git/util/intelp2m/fields"
+	"review.coreboot.org/coreboot.git/util/intelp2m/logs"
 	"review.coreboot.org/coreboot.git/util/intelp2m/platforms/cnl"
 	"review.coreboot.org/coreboot.git/util/intelp2m/platforms/common"
 	"review.coreboot.org/coreboot.git/util/intelp2m/platforms/common/register/bits"
-	"review.coreboot.org/coreboot.git/util/intelp2m/platforms/snr"
 )
 
 const (
-	PAD_CFG_DW0_RO_FIELDS = (0x1 << 27) | (0x1 << 24) | (0x3 << 21) | (0xf << 16) | 0xfc
-	PAD_CFG_DW1_RO_FIELDS = 0xfdffc3ff
+	DW0Mask = (0b1 << 27) | (0b1 << 24) | (0b11 << 21) | (0b1111 << 16) | 0b11111100
+	DW1Mask = 0b11111101111111111100001111111111
 )
 
-type InheritanceMacro interface {
-	Pull()
-	GpiMacroAdd()
-	GpoMacroAdd()
-	NativeFunctionMacroAdd()
-	NoConnMacroAdd()
+type BasePlatform struct {
+	// based on the Cannon Lake platform
+	cnl.BasePlatform
 }
 
-type PlatformSpecific struct {
-	InheritanceMacro
+func InitBasePlatform(dw0, dw0mask uint32, dw1, dw1mask uint32) BasePlatform {
+	return BasePlatform{cnl.InitBasePlatform(dw0, dw0mask, dw1, dw1mask)}
 }
 
-// RemmapRstSrc - remmap Pad Reset Source Config
-func (PlatformSpecific) RemmapRstSrc() {
-	macro := common.GetMacro()
-	dw0 := macro.GetRegisterDW0()
-	var remapping = map[uint32]uint32{
-		0: bits.RstCfgRSMRST << bits.DW0PadRstCfg,
-		1: bits.RstCfgDEEP << bits.DW0PadRstCfg,
-		2: bits.RstCfgPLTRST << bits.DW0PadRstCfg,
+func GetPlatform(dw0, dw1 uint32) common.PlatformIf {
+	p := InitBasePlatform(dw0, DW0Mask, dw1, DW1Mask)
+	return &p
+}
+
+// Override BasePlatform.RemapRstSrc()
+func (p *BasePlatform) RemapRstSrc(m *common.Macro) {
+	remapping := map[uint32]uint32{
+		0b00: bits.RstCfgRSMRST << bits.DW0PadRstCfg,
+		0b01: bits.RstCfgDEEP << bits.DW0PadRstCfg,
+		0b10: bits.RstCfgPLTRST << bits.DW0PadRstCfg,
 	}
-	resetsrc, valid := remapping[dw0.GetResetConfig()]
+	dw0 := p.GetRegisterDW0()
+	source, valid := remapping[dw0.GetResetConfig()]
 	if valid {
-		// dw0.SetResetConfig(resetsrc)
-		ResetConfigFieldVal := (dw0.Value & 0x3fffffff) | remapping[dw0.GetResetConfig()]
-		dw0.Value = ResetConfigFieldVal
+		dw0.Value &= 0x3fffffff
+		dw0.Value |= source
 	} else {
-		fmt.Println("Invalid Pad Reset Config [ 0x", resetsrc, " ] for ", macro.PadIdGet())
+		logs.Errorf("%s: skip re-mapping: DW0 %s: invalid reset config source value 0b%b",
+			m.GetPadId(), dw0, dw0.GetResetConfig())
 	}
 	mask := bits.DW0[bits.DW0PadRstCfg]
 	dw0.CntrMaskFieldsClear(mask)
 }
-
-// Adds The Pad Termination (TERM) parameter from PAD_CFG_DW1 to the macro
-// as a new argument
-func (platform PlatformSpecific) Pull() {
-	platform.InheritanceMacro.Pull()
-}
-
-// Adds PAD_CFG_GPI macro with arguments
-func (platform PlatformSpecific) GpiMacroAdd() {
-	platform.InheritanceMacro.GpiMacroAdd()
-}
-
-// Adds PAD_CFG_GPO macro with arguments
-func (platform PlatformSpecific) GpoMacroAdd() {
-	platform.InheritanceMacro.GpoMacroAdd()
-}
-
-// Adds PAD_CFG_NF macro with arguments
-func (platform PlatformSpecific) NativeFunctionMacroAdd() {
-	platform.InheritanceMacro.NativeFunctionMacroAdd()
-}
-
-// Adds PAD_NC macro
-func (platform PlatformSpecific) NoConnMacroAdd() {
-	platform.InheritanceMacro.NoConnMacroAdd()
-}
-
-// GenMacro - generate pad macro
-// dw0 : DW0 config register value
-// dw1 : DW1 config register value
-// return: string of macro
-func (platform PlatformSpecific) GenMacro(id string, dw0Val, dw1Val uint32, ownership uint8) string {
-	macro := common.GetInstanceMacro(
-		PlatformSpecific{
-			InheritanceMacro: cnl.PlatformSpecific{
-				InheritanceMacro: snr.PlatformSpecific{},
-			},
-		},
-		fields.InterfaceGet(),
-	)
-	macro.Clear()
-
-	dw0 := macro.GetRegisterDW0()
-	dw0.CntrMaskFieldsClear(bits.All32)
-
-	dw1 := macro.GetRegisterDW1()
-	dw1.CntrMaskFieldsClear(bits.All32)
-
-	dw0.Value = dw0Val
-	dw1.Value = dw1Val
-	dw0.ReadOnly = PAD_CFG_DW0_RO_FIELDS
-	dw1.ReadOnly = PAD_CFG_DW1_RO_FIELDS
-
-	macro.PadIdSet(id).SetPadOwnership(ownership)
-	return macro.Generate()
-}
diff --git a/util/intelp2m/platforms/ebg/template.go b/util/intelp2m/platforms/ebg/template.go
index 32ba246ec9..451bd5dfdc 100644
--- a/util/intelp2m/platforms/ebg/template.go
+++ b/util/intelp2m/platforms/ebg/template.go
@@ -5,10 +5,10 @@ import "review.coreboot.org/coreboot.git/util/intelp2m/platforms/common"
 // Group : "GPPC_A", "GPPC_B", "GPPC_S", "GPPC_C", "GPP_D", "GPP_E", "GPPC_H", "GPP_J",
 //         "GPP_I", "GPP_L", "GPP_M", "GPP_N"
 
-// KeywordCheck - This function is used to filter parsed lines of the configuration file and
+// CheckKeyword - This function is used to filter parsed lines of the configuration file and
 // returns true if the keyword is contained in the line.
 // line : string from the configuration file
-func (platform PlatformSpecific) KeywordCheck(line string) bool {
+func CheckKeyword(line string) bool {
 	isIncluded, _ := common.KeywordsCheck(line, "GPP_", "GPPC_")
 	return isIncluded
 }
diff --git a/util/intelp2m/platforms/interfaces.go b/util/intelp2m/platforms/interfaces.go
deleted file mode 100644
index 455da26cd7..0000000000
--- a/util/intelp2m/platforms/interfaces.go
+++ /dev/null
@@ -1,38 +0,0 @@
-package platforms
-
-import (
-	"review.coreboot.org/coreboot.git/util/intelp2m/config/p2m"
-	"review.coreboot.org/coreboot.git/util/intelp2m/logs"
-	"review.coreboot.org/coreboot.git/util/intelp2m/platforms/adl"
-	"review.coreboot.org/coreboot.git/util/intelp2m/platforms/apl"
-	"review.coreboot.org/coreboot.git/util/intelp2m/platforms/cnl"
-	"review.coreboot.org/coreboot.git/util/intelp2m/platforms/lbg"
-	"review.coreboot.org/coreboot.git/util/intelp2m/platforms/snr"
-)
-
-type SpecificIf interface {
-	GenMacro(id string, dw0 uint32, dw1 uint32, ownership uint8) string
-	KeywordCheck(line string) bool
-}
-
-func GetSpecificInterface() SpecificIf {
-	platforms := map[p2m.PlatformType]SpecificIf{
-		p2m.Alder:   adl.PlatformSpecific{},
-		p2m.Apollo:  apl.PlatformSpecific{},
-		p2m.Sunrise: snr.PlatformSpecific{},
-		p2m.Cannon: cnl.PlatformSpecific{
-			InheritanceTemplate: snr.PlatformSpecific{},
-			InheritanceMacro:    snr.PlatformSpecific{},
-		},
-		p2m.Lewisburg: lbg.PlatformSpecific{
-			InheritanceTemplate: snr.PlatformSpecific{},
-			InheritanceMacro:    snr.PlatformSpecific{},
-		},
-	}
-	platform, exist := platforms[p2m.Config.Platform]
-	if !exist {
-		logs.Errorf("unknown platform type %d", int(p2m.Config.Platform))
-		return nil
-	}
-	return platform
-}
diff --git a/util/intelp2m/platforms/jsl/jsl_test.go b/util/intelp2m/platforms/jsl/jsl_test.go
index 143617fb9a..444ba4cad9 100644
--- a/util/intelp2m/platforms/jsl/jsl_test.go
+++ b/util/intelp2m/platforms/jsl/jsl_test.go
@@ -3,108 +3,103 @@ package jsl_test
 import (
 	"testing"
 
-	"review.coreboot.org/coreboot.git/util/intelp2m/platforms/cnl"
-	"review.coreboot.org/coreboot.git/util/intelp2m/platforms/jsl"
-	"review.coreboot.org/coreboot.git/util/intelp2m/platforms/snr"
+	"review.coreboot.org/coreboot.git/util/intelp2m/config/p2m"
+	"review.coreboot.org/coreboot.git/util/intelp2m/platforms/common"
 	"review.coreboot.org/coreboot.git/util/intelp2m/platforms/test"
 )
 
 func TestGenMacro(t *testing.T) {
-	jasperlake := jsl.PlatformSpecific{
-		InheritanceMacro: cnl.PlatformSpecific{
-			InheritanceMacro: snr.PlatformSpecific{},
-		},
-	}
+	p2m.Config.Platform = p2m.Jasper
 	test.Suite{
 		{
-			Pad: test.Pad{ID: "GPP_A1", DW0: 0x11111111, DW1: 0x11111111, Ownership: 1},
+			Pad: test.Pad{ID: "GPP_A1", DW0: 0x11111111, DW1: 0x11111111, Ownership: common.Driver},
 			Macro: test.Macro{
 				Short: "PAD_CFG_NF(GPP_A1, DN_20K, PWROK, NF4),",
 				Long:  "_PAD_CFG_STRUCT(GPP_A1, PAD_FUNC(NF4) | PAD_IRQ_ROUTE(IOAPIC) | PAD_BUF(TX_DISABLE) | (1 << 28) | 1, PAD_PULL(DN_20K) | PAD_IOSSTATE(Tx1RxDCRx1) | PAD_IOSTERM(DISPUPD) | PAD_CFG_OWN_GPIO(DRIVER)),",
 			},
 		},
 		{
-			Pad: test.Pad{ID: "GPP_B2", DW0: 0x22222222, DW1: 0x22222222, Ownership: 0},
+			Pad: test.Pad{ID: "GPP_B2", DW0: 0x22222222, DW1: 0x22222222, Ownership: common.Acpi},
 			Macro: test.Macro{
 				Short: "PAD_CFG_TERM_GPO(GPP_B2, 0, INVALID, PWROK),",
 				Long:  "_PAD_CFG_STRUCT(GPP_B2, PAD_FUNC(GPIO) | PAD_TRIG(EDGE_SINGLE) | PAD_IRQ_ROUTE(NMI) | PAD_BUF(RX_DISABLE) | (1 << 29) | (1 << 1), PAD_CFG1_TOL_1V8PAD_PULL(INVALID) | PAD_IOSSTATE(HIZCRx1) | PAD_IOSTERM(ENPD)),",
 			},
 		},
 		{
-			Pad: test.Pad{ID: "GPP_C3", DW0: 0x44444444, DW1: 0x44444444, Ownership: 1},
+			Pad: test.Pad{ID: "GPP_C3", DW0: 0x44444444, DW1: 0x44444444, Ownership: common.Driver},
 			Macro: test.Macro{
 				Short: "PAD_CFG_NF(GPP_C3, INVALID, DEEP, NF1),",
 				Long:  "_PAD_CFG_STRUCT(GPP_C3, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_IRQ_ROUTE(SMI), PAD_PULL(INVALID) | PAD_IOSSTATE(Tx0RxDCRx0) | PAD_CFG_OWN_GPIO(DRIVER)),",
 			},
 		},
 		{
-			Pad: test.Pad{ID: "GPP_D4", DW0: 0x88888888, DW1: 0x88888888, Ownership: 0},
+			Pad: test.Pad{ID: "GPP_D4", DW0: 0x88888888, DW1: 0x88888888, Ownership: common.Acpi},
 			Macro: test.Macro{
 				Short: "PAD_CFG_NF(GPP_D4, DN_5K, PLTRST, NF2),",
 				Long:  "_PAD_CFG_STRUCT(GPP_D4, PAD_FUNC(NF2) | PAD_RESET(PLTRST) | PAD_IRQ_ROUTE(SCI) | PAD_RX_POL(INVERT), PAD_PULL(DN_5K) | PAD_IOSSTATE(Tx0RxDCRx1)),",
 			},
 		},
-	}.Run(t, "INTEL-JASPER-LAKE-PCH/SLIDING-ONE-IN-NIBBLE-TEST", jasperlake)
+	}.Run(t, "INTEL-JASPER-LAKE-PCH/SLIDING-ONE-IN-NIBBLE-TEST")
 
 	test.Suite{
 		{
-			Pad: test.Pad{ID: "GPP_E5", DW0: 0xEEEEEEEE, DW1: 0xEEEEEEEE, Ownership: 1},
+			Pad: test.Pad{ID: "GPP_E5", DW0: 0xEEEEEEEE, DW1: 0xEEEEEEEE, Ownership: common.Driver},
 			Macro: test.Macro{
 				Short: "PAD_CFG_NF_1V8(GPP_E5, UP_2K, RSMRST, NF3),",
 				Long:  "_PAD_CFG_STRUCT(GPP_E5, PAD_FUNC(NF3) | PAD_RESET(RSMRST) | PAD_TRIG(EDGE_BOTH) | PAD_IRQ_ROUTE(SCI) | PAD_IRQ_ROUTE(SMI) | PAD_IRQ_ROUTE(NMI) | PAD_RX_POL(INVERT) | PAD_BUF(RX_DISABLE) | (1 << 29) | (1 << 1), PAD_CFG1_TOL_1V8PAD_PULL(UP_2K) | PAD_IOSSTATE(ERROR) | PAD_IOSTERM(ENPD) | PAD_CFG_OWN_GPIO(DRIVER)),",
 			},
 		},
 		{
-			Pad: test.Pad{ID: "GPP_F6", DW0: 0xDDDDDDDD, DW1: 0xDDDDDDDD, Ownership: 0},
+			Pad: test.Pad{ID: "GPP_F6", DW0: 0xDDDDDDDD, DW1: 0xDDDDDDDD, Ownership: common.Acpi},
 			Macro: test.Macro{
 				Short: "PAD_CFG_NF(GPP_F6, INVALID, RSMRST, NF7),",
 				Long:  "_PAD_CFG_STRUCT(GPP_F6, PAD_FUNC(NF7) | PAD_RESET(RSMRST) | PAD_TRIG(OFF) | PAD_IRQ_ROUTE(IOAPIC) | PAD_IRQ_ROUTE(SCI) | PAD_IRQ_ROUTE(SMI) | PAD_RX_POL(INVERT) | PAD_BUF(TX_DISABLE) | (1 << 28) | 1, PAD_PULL(INVALID) | PAD_IOSSTATE(HIZCRx0) | PAD_IOSTERM(DISPUPD)),",
 			},
 		},
 		{
-			Pad: test.Pad{ID: "GPP_G7", DW0: 0xBBBBBBBB, DW1: 0xBBBBBBBB, Ownership: 1},
+			Pad: test.Pad{ID: "GPP_G7", DW0: 0xBBBBBBBB, DW1: 0xBBBBBBBB, Ownership: common.Driver},
 			Macro: test.Macro{
 				Short: "PAD_CFG_NF_1V8(GPP_G7, INVALID, PLTRST, NF6),",
 				Long:  "_PAD_CFG_STRUCT(GPP_G7, PAD_FUNC(NF6) | PAD_RESET(PLTRST) | PAD_TRIG(EDGE_SINGLE) | PAD_IRQ_ROUTE(IOAPIC) | PAD_IRQ_ROUTE(SCI) | PAD_IRQ_ROUTE(NMI) | PAD_RX_POL(INVERT) | PAD_BUF(TX_RX_DISABLE) | (1 << 29) | (1 << 28) | (1 << 1) | 1, PAD_CFG1_TOL_1V8PAD_PULL(INVALID) | PAD_IOSSTATE(ERROR) | PAD_IOSTERM(ENPU) | PAD_CFG_OWN_GPIO(DRIVER)),",
 			},
 		},
 		{
-			Pad: test.Pad{ID: "GPP_H8", DW0: 0x77777777, DW1: 0x77777777, Ownership: 0},
+			Pad: test.Pad{ID: "GPP_H8", DW0: 0x77777777, DW1: 0x77777777, Ownership: common.Acpi},
 			Macro: test.Macro{
 				Short: "PAD_CFG_NF_1V8(GPP_H8, UP_667, DEEP, NF5),",
 				Long:  "_PAD_CFG_STRUCT(GPP_H8, PAD_FUNC(NF5) | PAD_RESET(DEEP) | PAD_TRIG(EDGE_BOTH) | PAD_IRQ_ROUTE(IOAPIC) | PAD_IRQ_ROUTE(SMI) | PAD_IRQ_ROUTE(NMI) | PAD_BUF(TX_RX_DISABLE) | (1 << 29) | (1 << 28) | (1 << 1) | 1, PAD_CFG1_TOL_1V8PAD_PULL(UP_667) | PAD_IOSSTATE(ERROR) | PAD_IOSTERM(ENPU)),",
 			},
 		},
-	}.Run(t, "INTEL-JASPER-LAKE-PCH/SLIDING-ZERO-IN-NIBBLE-TEST", jasperlake)
+	}.Run(t, "INTEL-JASPER-LAKE-PCH/SLIDING-ZERO-IN-NIBBLE-TEST")
 
 	test.Suite{
 		{
-			Pad: test.Pad{ID: "GPP_R9", DW0: 0x33333333, DW1: 0x33333333, Ownership: 1},
+			Pad: test.Pad{ID: "GPP_R9", DW0: 0x33333333, DW1: 0x33333333, Ownership: common.Driver},
 			Macro: test.Macro{
 				Short: "PAD_CFG_NF_1V8(GPP_R9, UP_20K, PWROK, NF4),",
 				Long:  "_PAD_CFG_STRUCT(GPP_R9, PAD_FUNC(NF4) | PAD_TRIG(EDGE_SINGLE) | PAD_IRQ_ROUTE(IOAPIC) | PAD_IRQ_ROUTE(NMI) | PAD_BUF(TX_RX_DISABLE) | (1 << 29) | (1 << 28) | (1 << 1) | 1, PAD_CFG1_TOL_1V8PAD_PULL(UP_20K) | PAD_IOSSTATE(ERROR) | PAD_IOSTERM(ENPU) | PAD_CFG_OWN_GPIO(DRIVER)),",
 			},
 		},
 		{
-			Pad: test.Pad{ID: "GPP_S10", DW0: 0x66666666, DW1: 0x66666666, Ownership: 0},
+			Pad: test.Pad{ID: "GPP_S10", DW0: 0x66666666, DW1: 0x66666666, Ownership: common.Acpi},
 			Macro: test.Macro{
 				Short: "PAD_CFG_NF_1V8(GPP_S10, UP_1K, DEEP, NF1),",
 				Long:  "_PAD_CFG_STRUCT(GPP_S10, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(EDGE_BOTH) | PAD_IRQ_ROUTE(SMI) | PAD_IRQ_ROUTE(NMI) | PAD_BUF(RX_DISABLE) | (1 << 29) | (1 << 1), PAD_CFG1_TOL_1V8PAD_PULL(UP_1K) | PAD_IOSSTATE(TxDRxE) | PAD_IOSTERM(ENPD)),",
 			},
 		},
 		{
-			Pad: test.Pad{ID: "GPP_T11", DW0: 0xCCCCCCCC, DW1: 0xCCCCCCCC, Ownership: 1},
+			Pad: test.Pad{ID: "GPP_T11", DW0: 0xCCCCCCCC, DW1: 0xCCCCCCCC, Ownership: common.Driver},
 			Macro: test.Macro{
 				Short: "PAD_CFG_NF(GPP_T11, INVALID, RSMRST, NF3),",
 				Long:  "_PAD_CFG_STRUCT(GPP_T11, PAD_FUNC(NF3) | PAD_RESET(RSMRST) | PAD_TRIG(OFF) | PAD_IRQ_ROUTE(SCI) | PAD_IRQ_ROUTE(SMI) | PAD_RX_POL(INVERT), PAD_PULL(INVALID) | PAD_IOSSTATE(Tx1RxDCRx0) | PAD_CFG_OWN_GPIO(DRIVER)),",
 			},
 		},
 		{
-			Pad: test.Pad{ID: "GPD12", DW0: 0x99999999, DW1: 0x99999999, Ownership: 0},
+			Pad: test.Pad{ID: "GPD12", DW0: 0x99999999, DW1: 0x99999999, Ownership: common.Acpi},
 			Macro: test.Macro{
 				Short: "PAD_CFG_NF(GPD12, INVALID, PLTRST, NF6),",
 				Long:  "_PAD_CFG_STRUCT(GPD12, PAD_FUNC(NF6) | PAD_RESET(PLTRST) | PAD_IRQ_ROUTE(IOAPIC) | PAD_IRQ_ROUTE(SCI) | PAD_RX_POL(INVERT) | PAD_BUF(TX_DISABLE) | (1 << 28) | 1, PAD_PULL(INVALID) | PAD_IOSSTATE(Tx1RxE) | PAD_IOSTERM(DISPUPD)),",
 			},
 		},
-	}.Run(t, "INTEL-JASPER-LAKE-PCH/SLIDING-ONE-ONE-IN-NIBBLE-TEST", jasperlake)
+	}.Run(t, "INTEL-JASPER-LAKE-PCH/SLIDING-ONE-ONE-IN-NIBBLE-TEST")
 }
diff --git a/util/intelp2m/platforms/jsl/macro.go b/util/intelp2m/platforms/jsl/macro.go
index d21eda151a..fa5cbedd7a 100644
--- a/util/intelp2m/platforms/jsl/macro.go
+++ b/util/intelp2m/platforms/jsl/macro.go
@@ -1,118 +1,60 @@
 package jsl
 
 import (
-	"fmt"
 	"strings"
 
-	"review.coreboot.org/coreboot.git/util/intelp2m/fields"
+	"review.coreboot.org/coreboot.git/util/intelp2m/logs"
 	"review.coreboot.org/coreboot.git/util/intelp2m/platforms/cnl"
 	"review.coreboot.org/coreboot.git/util/intelp2m/platforms/common"
 	"review.coreboot.org/coreboot.git/util/intelp2m/platforms/common/register/bits"
-	"review.coreboot.org/coreboot.git/util/intelp2m/platforms/snr"
 )
 
 const (
-	PAD_CFG_DW0_RO_FIELDS = (0x1 << 27) | (0x1 << 18) | (0x3f << 11) | (0x3f << 2) | (0x1 << 1)
-	PAD_CFG_DW1_RO_FIELDS = 0xdfffc3ff
+	DW0Mask = (0b1 << 27) | (0b1 << 18) | (0b00111111 << 11) | (0b00111111 << 2) | (0b1 << 1)
+	DW1Mask = 0b11111101111111111100001111111111
 )
 
-type InheritanceMacro interface {
-	Pull()
-	GpiMacroAdd()
-	GpoMacroAdd()
-	NativeFunctionMacroAdd()
-	NoConnMacroAdd()
+type BasePlatform struct {
+	// based on the Cannon Lake platform
+	cnl.BasePlatform
 }
 
-type PlatformSpecific struct {
-	InheritanceMacro
+func InitBasePlatform(dw0, dw0mask uint32, dw1, dw1mask uint32) BasePlatform {
+	return BasePlatform{cnl.InitBasePlatform(dw0, dw0mask, dw1, dw1mask)}
 }
 
-// RemmapRstSrc - remmap Pad Reset Source Config
-func (PlatformSpecific) RemmapRstSrc() {
-	macro := common.GetMacro()
-	if strings.Contains(macro.PadIdGet(), "GPP_F") ||
-		strings.Contains(macro.PadIdGet(), "GPP_B") ||
-		strings.Contains(macro.PadIdGet(), "GPP_A") ||
-		strings.Contains(macro.PadIdGet(), "GPP_S") ||
-		strings.Contains(macro.PadIdGet(), "GPP_R") {
+func GetPlatform(dw0, dw1 uint32) common.PlatformIf {
+	p := InitBasePlatform(dw0, DW0Mask, dw1, DW1Mask)
+	return &p
+}
+
+// Override the base platform method
+func (p *BasePlatform) RemapRstSrc(m *common.Macro) {
+	if strings.Contains(m.GetPadId(), "GPP_F") ||
+		strings.Contains(m.GetPadId(), "GPP_B") ||
+		strings.Contains(m.GetPadId(), "GPP_A") ||
+		strings.Contains(m.GetPadId(), "GPP_S") ||
+		strings.Contains(m.GetPadId(), "GPP_R") {
 		// See reset map for the Jasper Lake Community 0:
 		// https://github.com/coreboot/coreboot/blob/master/src/soc/intel/jasperlake/gpio.c#L21
 		// remmap is not required because it is the same as common.
 		return
 	}
 
-	dw0 := macro.GetRegisterDW0()
-	var remapping = map[uint32]uint32{
-		0: bits.RstCfgRSMRST << bits.DW0PadRstCfg,
-		1: bits.RstCfgDEEP << bits.DW0PadRstCfg,
-		2: bits.RstCfgPLTRST << bits.DW0PadRstCfg,
+	remapping := map[uint32]uint32{
+		0b00: bits.RstCfgRSMRST << bits.DW0PadRstCfg,
+		0b01: bits.RstCfgDEEP << bits.DW0PadRstCfg,
+		0b10: bits.RstCfgPLTRST << bits.DW0PadRstCfg,
 	}
-	resetsrc, valid := remapping[dw0.GetResetConfig()]
+	dw0 := p.GetRegisterDW0()
+	source, valid := remapping[dw0.GetResetConfig()]
 	if valid {
-		// dw0.SetResetConfig(resetsrc)
-		ResetConfigFieldVal := (dw0.Value & 0x3fffffff) | remapping[dw0.GetResetConfig()]
-		dw0.Value = ResetConfigFieldVal
+		dw0.Value &= 0x3fffffff
+		dw0.Value |= source
 	} else {
-		fmt.Println("Invalid Pad Reset Config [ 0x", resetsrc, " ] for ", macro.PadIdGet())
+		logs.Errorf("%s: skip re-mapping: DW0 %s: invalid reset config source value 0b%b",
+			m.GetPadId(), dw0, dw0.GetResetConfig())
 	}
 	mask := bits.DW0[bits.DW0PadRstCfg]
 	dw0.CntrMaskFieldsClear(mask)
 }
-
-// Adds The Pad Termination (TERM) parameter from PAD_CFG_DW1 to the macro
-// as a new argument
-func (platform PlatformSpecific) Pull() {
-	platform.InheritanceMacro.Pull()
-}
-
-// Adds PAD_CFG_GPI macro with arguments
-func (platform PlatformSpecific) GpiMacroAdd() {
-	platform.InheritanceMacro.GpiMacroAdd()
-}
-
-// Adds PAD_CFG_GPO macro with arguments
-func (platform PlatformSpecific) GpoMacroAdd() {
-	platform.InheritanceMacro.GpoMacroAdd()
-}
-
-// Adds PAD_CFG_NF macro with arguments
-func (platform PlatformSpecific) NativeFunctionMacroAdd() {
-	platform.InheritanceMacro.NativeFunctionMacroAdd()
-}
-
-// Adds PAD_NC macro
-func (platform PlatformSpecific) NoConnMacroAdd() {
-	platform.InheritanceMacro.NoConnMacroAdd()
-}
-
-// GenMacro - generate pad macro
-// dw0 : DW0 config register value
-// dw1 : DW1 config register value
-// return: string of macro
-func (PlatformSpecific) GenMacro(id string, dw0Val, dw1Val uint32, ownership uint8) string {
-	macro := common.GetInstanceMacro(
-		PlatformSpecific{
-			InheritanceMacro: cnl.PlatformSpecific{
-				InheritanceMacro: snr.PlatformSpecific{},
-			},
-		},
-		fields.InterfaceGet(),
-	)
-	macro.Clear()
-
-	macro.Clear()
-	dw0 := macro.GetRegisterDW0()
-	dw0.CntrMaskFieldsClear(bits.All32)
-
-	dw1 := macro.GetRegisterDW1()
-	dw1.CntrMaskFieldsClear(bits.All32)
-
-	dw0.Value = dw0Val
-	dw1.Value = dw1Val
-	dw0.ReadOnly = PAD_CFG_DW0_RO_FIELDS
-	dw1.ReadOnly = PAD_CFG_DW1_RO_FIELDS
-
-	macro.PadIdSet(id).SetPadOwnership(ownership)
-	return macro.Generate()
-}
diff --git a/util/intelp2m/platforms/jsl/template.go b/util/intelp2m/platforms/jsl/template.go
index ec6e9c91a9..acf6a5ab70 100644
--- a/util/intelp2m/platforms/jsl/template.go
+++ b/util/intelp2m/platforms/jsl/template.go
@@ -5,10 +5,10 @@ import "review.coreboot.org/coreboot.git/util/intelp2m/platforms/common"
 // Group : "GPP_A", "GPP_B", "GPP_C", "GPP_D", "GPP_E", "GPP_F", "GPP_G", "GPP_H", "GPP_R",
 //         "GPP_S", "GPP_T", "GPD", "HVMOS", "VGPIO5"
 
-// KeywordCheck - This function is used to filter parsed lines of the configuration file and
+// CheckKeyword - This function is used to filter parsed lines of the configuration file and
 // returns true if the keyword is contained in the line.
 // line : string from the configuration file
-func (PlatformSpecific) KeywordCheck(line string) bool {
+func CheckKeyword(line string) bool {
 	isIncluded, _ := common.KeywordsCheck(line, "GPP_", "GPD", "VGPIO")
 	return isIncluded
 }
diff --git a/util/intelp2m/platforms/lbg/lbg_test.go b/util/intelp2m/platforms/lbg/lbg_test.go
index 62eba80404..b077c5c923 100644
--- a/util/intelp2m/platforms/lbg/lbg_test.go
+++ b/util/intelp2m/platforms/lbg/lbg_test.go
@@ -3,173 +3,173 @@ package lbg_test
 import (
 	"testing"
 
-	"review.coreboot.org/coreboot.git/util/intelp2m/platforms/lbg"
-	"review.coreboot.org/coreboot.git/util/intelp2m/platforms/snr"
+	"review.coreboot.org/coreboot.git/util/intelp2m/config/p2m"
+	"review.coreboot.org/coreboot.git/util/intelp2m/platforms/common"
 	"review.coreboot.org/coreboot.git/util/intelp2m/platforms/test"
 )
 
 func TestGenMacro(t *testing.T) {
-	lewisburg := lbg.PlatformSpecific{InheritanceMacro: snr.PlatformSpecific{}}
+	p2m.Config.Platform = p2m.Lewisburg
 	test.Suite{
 		{ /* GPP_A1 - ESPI_ALERT1#  */
-			Pad: test.Pad{ID: "GPP_A1", DW0: 0x44000c00, DW1: 0x00003000, Ownership: 1},
+			Pad: test.Pad{ID: "GPP_A1", DW0: 0x44000c00, DW1: 0x00003000, Ownership: common.Driver},
 			Macro: test.Macro{
 				Short: "PAD_CFG_NF(GPP_A1, UP_20K, DEEP, NF3),",
 				Long:  "_PAD_CFG_STRUCT(GPP_A1, PAD_FUNC(NF3) | PAD_RESET(DEEP) | PAD_TRIG(OFF), PAD_PULL(UP_20K) | PAD_CFG_OWN_GPIO(DRIVER)),",
 			},
 		},
 		{ /* GPP_A12 - LFRAME# */
-			Pad: test.Pad{ID: "GPP_A12", DW0: 0x80880102, DW1: 0x00000000, Ownership: 0},
+			Pad: test.Pad{ID: "GPP_A12", DW0: 0x80880102, DW1: 0x00000000, Ownership: common.Acpi},
 			Macro: test.Macro{
 				Short: "PAD_CFG_GPI_SCI(GPP_A12, NONE, PLTRST, LEVEL, INVERT),",
 				Long:  "_PAD_CFG_STRUCT(GPP_A12, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_IRQ_ROUTE(SCI) | PAD_RX_POL(INVERT) | PAD_BUF(TX_DISABLE) | (1 << 1), 0),",
 			},
 		},
 		{ /* GPP_A16 - GPIO */
-			Pad: test.Pad{ID: "GPP_A16", DW0: 0x44000201, DW1: 0x00000000, Ownership: 1},
+			Pad: test.Pad{ID: "GPP_A16", DW0: 0x44000201, DW1: 0x00000000, Ownership: common.Driver},
 			Macro: test.Macro{
 				Short: "PAD_CFG_GPO_GPIO_DRIVER(GPP_A16, 1, DEEP, NONE),",
 				Long:  "_PAD_CFG_STRUCT(GPP_A16, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, PAD_CFG_OWN_GPIO(DRIVER)),",
 			},
 		},
 		{ /* GPP_A20 - GPIO */
-			Pad: test.Pad{ID: "GPP_A20", DW0: 0x04000100, DW1: 0x00000000, Ownership: 0},
+			Pad: test.Pad{ID: "GPP_A20", DW0: 0x04000100, DW1: 0x00000000, Ownership: common.Acpi},
 			Macro: test.Macro{
 				Short: "PAD_CFG_GPI_TRIG_OWN(GPP_A20, NONE, RSMRST, OFF, ACPI),",
 				Long:  "_PAD_CFG_STRUCT(GPP_A20, PAD_FUNC(GPIO) | PAD_RESET(RSMRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), 0),",
 			},
 		},
 		{ /* GPP_B10 - GPIO */
-			Pad: test.Pad{ID: "GPP_B10", DW0: 0x04000102, DW1: 0x00000000, Ownership: 0},
+			Pad: test.Pad{ID: "GPP_B10", DW0: 0x04000102, DW1: 0x00000000, Ownership: common.Acpi},
 			Macro: test.Macro{
 				Short: "PAD_CFG_GPI_TRIG_OWN(GPP_B10, NONE, RSMRST, OFF, ACPI),",
 				Long:  "_PAD_CFG_STRUCT(GPP_B10, PAD_FUNC(GPIO) | PAD_RESET(RSMRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0),",
 			},
 		},
 		{ /* GPP_B20 - GPIO */
-			Pad: test.Pad{ID: "GPP_B20", DW0: 0x04000200, DW1: 0x00000000, Ownership: 0},
+			Pad: test.Pad{ID: "GPP_B20", DW0: 0x04000200, DW1: 0x00000000, Ownership: common.Acpi},
 			Macro: test.Macro{
 				Short: "PAD_CFG_GPO(GPP_B20, 0, RSMRST),",
 				Long:  "_PAD_CFG_STRUCT(GPP_B20, PAD_FUNC(GPIO) | PAD_RESET(RSMRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), 0),",
 			},
 		},
 		{ /* GPP_B23 - PCHHOT# */
-			Pad: test.Pad{ID: "GPP_B23", DW0: 0x04000a00, DW1: 0x00000000, Ownership: 0},
+			Pad: test.Pad{ID: "GPP_B23", DW0: 0x04000a00, DW1: 0x00000000, Ownership: common.Acpi},
 			Macro: test.Macro{
 				Short: "PAD_CFG_NF(GPP_B23, NONE, RSMRST, NF2),",
 				Long:  "_PAD_CFG_STRUCT(GPP_B23, PAD_FUNC(NF2) | PAD_RESET(RSMRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), 0),",
 			},
 		},
 		{ /* GPP_F0 - SATAXPCIE3 */
-			Pad: test.Pad{ID: "GPP_F0", DW0: 0x04000502, DW1: 0x00000000, Ownership: 0},
+			Pad: test.Pad{ID: "GPP_F0", DW0: 0x04000502, DW1: 0x00000000, Ownership: common.Acpi},
 			Macro: test.Macro{
 				Short: "PAD_CFG_NF(GPP_F0, NONE, RSMRST, NF1),",
 				Long:  "_PAD_CFG_STRUCT(GPP_F0, PAD_FUNC(NF1) | PAD_RESET(RSMRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0),",
 			},
 		},
 		{ /* GPP_C10 - GPIO */
-			Pad: test.Pad{ID: "GPP_C10", DW0: 0x04000000, DW1: 0x00000000, Ownership: 0},
+			Pad: test.Pad{ID: "GPP_C10", DW0: 0x04000000, DW1: 0x00000000, Ownership: common.Acpi},
 			Macro: test.Macro{
 				Short: "PAD_CFG_GPIO_BIDIRECT(GPP_C10, 0, NONE, RSMRST, OFF, ACPI),",
 				Long:  "_PAD_CFG_STRUCT(GPP_C10, PAD_FUNC(GPIO) | PAD_RESET(RSMRST) | PAD_TRIG(OFF), 0),",
 			},
 		},
 		{ /* GPP_C23 - GPIO */
-			Pad: test.Pad{ID: "GPP_C23", DW0: 0x40880102, DW1: 0x00000000, Ownership: 0},
+			Pad: test.Pad{ID: "GPP_C23", DW0: 0x40880102, DW1: 0x00000000, Ownership: common.Acpi},
 			Macro: test.Macro{
 				Short: "PAD_CFG_GPI_SCI(GPP_C23, NONE, DEEP, LEVEL, INVERT),",
 				Long:  "_PAD_CFG_STRUCT(GPP_C23, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_IRQ_ROUTE(SCI) | PAD_RX_POL(INVERT) | PAD_BUF(TX_DISABLE) | (1 << 1), 0),",
 			},
 		},
 		{ /* GPP_D1 - GPIO */
-			Pad: test.Pad{ID: "GPP_D1", DW0: 0x04000200, DW1: 0x00000000, Ownership: 0},
+			Pad: test.Pad{ID: "GPP_D1", DW0: 0x04000200, DW1: 0x00000000, Ownership: common.Acpi},
 			Macro: test.Macro{
 				Short: "PAD_CFG_GPO(GPP_D1, 0, RSMRST),",
 				Long:  "_PAD_CFG_STRUCT(GPP_D1, PAD_FUNC(GPIO) | PAD_RESET(RSMRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), 0),",
 			},
 		},
 		{ /* GPP_D16 - GPIO */
-			Pad: test.Pad{ID: "GPP_D16", DW0: 0x84000100, DW1: 0x00000000, Ownership: 0},
+			Pad: test.Pad{ID: "GPP_D16", DW0: 0x84000100, DW1: 0x00000000, Ownership: common.Acpi},
 			Macro: test.Macro{
 				Short: "PAD_CFG_GPI_TRIG_OWN(GPP_D16, NONE, PLTRST, OFF, ACPI),",
 				Long:  "_PAD_CFG_STRUCT(GPP_D16, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), 0),",
 			},
 		},
 		{ /* GPP_E0 - SATAXPCIE0 */
-			Pad: test.Pad{ID: "GPP_E0", DW0: 0x04000502, DW1: 0x00000000, Ownership: 0},
+			Pad: test.Pad{ID: "GPP_E0", DW0: 0x04000502, DW1: 0x00000000, Ownership: common.Acpi},
 			Macro: test.Macro{
 				Short: "PAD_CFG_NF(GPP_E0, NONE, RSMRST, NF1),",
 				Long:  "_PAD_CFG_STRUCT(GPP_E0, PAD_FUNC(NF1) | PAD_RESET(RSMRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0),",
 			},
 		},
 		{ /* GPP_E7 - GPIO */
-			Pad: test.Pad{ID: "GPP_E7", DW0: 0x40840102, DW1: 0x00000000, Ownership: 1},
+			Pad: test.Pad{ID: "GPP_E7", DW0: 0x40840102, DW1: 0x00000000, Ownership: common.Driver},
 			Macro: test.Macro{
 				Short: "PAD_CFG_GPI_SMI(GPP_E7, NONE, DEEP, LEVEL, INVERT),",
 				Long:  "_PAD_CFG_STRUCT(GPP_E7, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_IRQ_ROUTE(SMI) | PAD_RX_POL(INVERT) | PAD_BUF(TX_DISABLE) | (1 << 1), PAD_CFG_OWN_GPIO(DRIVER)),",
 			},
 		},
 		{ /* GPP_F2 - GPIO */
-			Pad: test.Pad{ID: "GPP_F2", DW0: 0x44000300, DW1: 0x00000000, Ownership: 0},
+			Pad: test.Pad{ID: "GPP_F2", DW0: 0x44000300, DW1: 0x00000000, Ownership: common.Acpi},
 			Macro: test.Macro{
 				Short: "PAD_NC(GPP_F2, NONE),",
 				Long:  "_PAD_CFG_STRUCT(GPP_F2, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),",
 			},
 		},
 		{ /* GPP_F12 - GPIO */
-			Pad: test.Pad{ID: "GPP_F12", DW0: 0x80900102, DW1: 0x00000000, Ownership: 0},
+			Pad: test.Pad{ID: "GPP_F12", DW0: 0x80900102, DW1: 0x00000000, Ownership: common.Acpi},
 			Macro: test.Macro{
 				Short: "PAD_CFG_GPI_APIC_LOW(GPP_F12, NONE, PLTRST),",
 				Long:  "_PAD_CFG_STRUCT(GPP_F12, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_IRQ_ROUTE(IOAPIC) | PAD_RX_POL(INVERT) | PAD_BUF(TX_DISABLE) | (1 << 1), 0),",
 			},
 		},
 		{ /* GPP_F13 - GPIO */
-			Pad: test.Pad{ID: "GPP_F13", DW0: 0x80100102, DW1: 0x00000000, Ownership: 0},
+			Pad: test.Pad{ID: "GPP_F13", DW0: 0x80100102, DW1: 0x00000000, Ownership: common.Acpi},
 			Macro: test.Macro{
 				Short: "PAD_CFG_GPI_APIC_HIGH(GPP_F13, NONE, PLTRST),",
 				Long:  "_PAD_CFG_STRUCT(GPP_F13, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_IRQ_ROUTE(IOAPIC) | PAD_BUF(TX_DISABLE) | (1 << 1), 0),",
 			},
 		},
 		{ /* GPP_H10 - NC */
-			Pad: test.Pad{ID: "GPP_H10", DW0: 0x44000300, DW1: 0x00000000, Ownership: 0},
+			Pad: test.Pad{ID: "GPP_H10", DW0: 0x44000300, DW1: 0x00000000, Ownership: common.Acpi},
 			Macro: test.Macro{
 				Short: "PAD_NC(GPP_H10, NONE),",
 				Long:  "_PAD_CFG_STRUCT(GPP_H10, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),",
 			},
 		},
 		{ /* GPP_L1 - CSME_INTR_OUT */
-			Pad: test.Pad{ID: "GPP_L1", DW0: 0x44000700, DW1: 0x00000000, Ownership: 0},
+			Pad: test.Pad{ID: "GPP_L1", DW0: 0x44000700, DW1: 0x00000000, Ownership: common.Acpi},
 			Macro: test.Macro{
 				Short: "PAD_CFG_NF(GPP_L1, NONE, DEEP, NF1),",
 				Long:  "_PAD_CFG_STRUCT(GPP_L1, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),",
 			},
 		},
 		{ /* GPP_L19 - TESTCH1_CLK */
-			Pad: test.Pad{ID: "GPP_L19", DW0: 0x04000600, DW1: 0x00000000, Ownership: 0},
+			Pad: test.Pad{ID: "GPP_L19", DW0: 0x04000600, DW1: 0x00000000, Ownership: common.Acpi},
 			Macro: test.Macro{
 				Short: "PAD_CFG_NF(GPP_L19, NONE, RSMRST, NF1),",
 				Long:  "_PAD_CFG_STRUCT(GPP_L19, PAD_FUNC(NF1) | PAD_RESET(RSMRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), 0),",
 			},
 		},
-	}.Run(t, "INTEL-LEWISBURG-PCH/PAD-MAP", lewisburg)
+	}.Run(t, "INTEL-LEWISBURG-PCH/PAD-MAP")
 
 	test.Suite{
 		{
-			Pad: test.Pad{ID: "GPP_Axx", DW0: 0xBFFFFFFF, DW1: 0xFFFFFFFF, Ownership: 1},
+			Pad: test.Pad{ID: "GPP_Axx", DW0: 0xBFFFFFFF, DW1: 0xFFFFFFFF, Ownership: common.Driver},
 			Macro: test.Macro{
 				Short: "PAD_CFG_NF_1V8(GPP_Axx, NATIVE, PLTRST, NF7),",
 				Long:  "_PAD_CFG_STRUCT(GPP_Axx, PAD_FUNC(NF7) | PAD_RESET(PLTRST) | PAD_TRIG(EDGE_BOTH) | PAD_IRQ_ROUTE(IOAPIC) | PAD_IRQ_ROUTE(SCI) | PAD_IRQ_ROUTE(SMI) | PAD_IRQ_ROUTE(NMI) | PAD_RX_POL(INVERT) | PAD_BUF(TX_RX_DISABLE) | (1 << 29) | (1 << 28) | (1 << 1) | 1, PAD_CFG1_TOL_1V8PAD_PULL(NATIVE) | PAD_IOSSTATE(IGNORE) | PAD_IOSTERM(ENPU) | PAD_CFG_OWN_GPIO(DRIVER)),",
 			},
 		},
-	}.Run(t, "INTEL-LEWISBURG-PCH/MASK", lewisburg)
+	}.Run(t, "INTEL-LEWISBURG-PCH/MASK")
 
 	test.Suite{
 		{
-			Pad: test.Pad{ID: "GPP_Bxx", DW0: 0x00000000, DW1: 0x00000000, Ownership: 0},
+			Pad: test.Pad{ID: "GPP_Bxx", DW0: 0x00000000, DW1: 0x00000000, Ownership: common.Acpi},
 			Macro: test.Macro{
 				Short: "PAD_CFG_GPIO_BIDIRECT(GPP_Bxx, 0, NONE, RSMRST, LEVEL, ACPI),",
 				Long:  "_PAD_CFG_STRUCT(GPP_Bxx, PAD_FUNC(GPIO) | PAD_RESET(RSMRST), 0),",
 			},
 		},
-	}.Run(t, "INTEL-LEWISBURG-PCH/EMRTY", lewisburg)
+	}.Run(t, "INTEL-LEWISBURG-PCH/EMRTY")
 }
diff --git a/util/intelp2m/platforms/lbg/macro.go b/util/intelp2m/platforms/lbg/macro.go
index 9cbd4f0570..d1b53501b7 100644
--- a/util/intelp2m/platforms/lbg/macro.go
+++ b/util/intelp2m/platforms/lbg/macro.go
@@ -1,105 +1,48 @@
 package lbg
 
 import (
-	"fmt"
-
-	"review.coreboot.org/coreboot.git/util/intelp2m/fields"
+	"review.coreboot.org/coreboot.git/util/intelp2m/logs"
 	"review.coreboot.org/coreboot.git/util/intelp2m/platforms/common"
 	"review.coreboot.org/coreboot.git/util/intelp2m/platforms/common/register/bits"
 	"review.coreboot.org/coreboot.git/util/intelp2m/platforms/snr"
 )
 
 const (
-	PAD_CFG_DW0_RO_FIELDS = (0x1 << 27) | (0x1 << 24) | (0x3 << 21) | (0xf << 16) | 0xfc
-	PAD_CFG_DW1_RO_FIELDS = 0xfdffc3ff
+	DW0Mask uint32 = (0b1 << 27) | (0b1 << 24) | (0b11 << 21) | (0b1111 << 16) | 0b11111100
+	DW1Mask uint32 = 0b11111101111111111100001111111111
 )
 
-type InheritanceMacro interface {
-	Pull()
-	GpiMacroAdd()
-	GpoMacroAdd()
-	NativeFunctionMacroAdd()
-	NoConnMacroAdd()
+type BasePlatform struct {
+	// based on the Sunrise Point platform
+	snr.BasePlatform
 }
 
-type PlatformSpecific struct {
-	InheritanceMacro
-	InheritanceTemplate
+func InitBasePlatform(dw0, dw0mask uint32, dw1, dw1mask uint32) BasePlatform {
+	return BasePlatform{snr.InitBasePlatform(dw0, dw0mask, dw1, dw1mask)}
 }
 
-// RemmapRstSrc - remmap Pad Reset Source Config
-func (PlatformSpecific) RemmapRstSrc() {
-	macro := common.GetMacro()
-	dw0 := macro.GetRegisterDW0()
+func GetPlatform(dw0, dw1 uint32) common.PlatformIf {
+	p := InitBasePlatform(dw0, DW0Mask, dw1, DW1Mask)
+	return &p
+}
+
+// Override the base platform method
+func (p *BasePlatform) RemapRstSrc(m *common.Macro) {
+	dw0 := p.GetRegisterDW0()
 	remapping := map[uint32]uint32{
-		0: (bits.RstCfgRSMRST << bits.DW0PadRstCfg),
-		1: (bits.RstCfgDEEP << bits.DW0PadRstCfg),
-		2: (bits.RstCfgPLTRST << bits.DW0PadRstCfg),
+		0b00: bits.RstCfgRSMRST << bits.DW0PadRstCfg,
+		0b01: bits.RstCfgDEEP << bits.DW0PadRstCfg,
+		0b10: bits.RstCfgPLTRST << bits.DW0PadRstCfg,
 	}
-	resetsrc, valid := remapping[dw0.GetResetConfig()]
+	source, valid := remapping[dw0.GetResetConfig()]
 	if valid {
 		// dw0.SetResetConfig(resetsrc)
-		ResetConfigFieldVal := (dw0.Value & 0x3fffffff) | remapping[dw0.GetResetConfig()]
-		dw0.Value = ResetConfigFieldVal
+		dw0.Value &= 0x3fffffff
+		dw0.Value |= source
 	} else {
-		fmt.Println("Invalid Pad Reset Config [ 0x", resetsrc, " ] for ", macro.PadIdGet())
+		logs.Errorf("%s: skip re-mapping: DW0 %s: invalid reset config source value 0b%b",
+			m.GetPadId(), dw0, dw0.GetResetConfig())
 	}
 	mask := bits.DW0[bits.DW0PadRstCfg]
 	dw0.CntrMaskFieldsClear(mask)
 }
-
-// Adds The Pad Termination (TERM) parameter from PAD_CFG_DW1 to the macro
-// as a new argument
-func (platform PlatformSpecific) Pull() {
-	platform.InheritanceMacro.Pull()
-}
-
-// Adds PAD_CFG_GPI macro with arguments
-func (platform PlatformSpecific) GpiMacroAdd() {
-	platform.InheritanceMacro.GpiMacroAdd()
-}
-
-// Adds PAD_CFG_GPO macro with arguments
-func (platform PlatformSpecific) GpoMacroAdd() {
-	platform.InheritanceMacro.GpoMacroAdd()
-}
-
-// Adds PAD_CFG_NF macro with arguments
-func (platform PlatformSpecific) NativeFunctionMacroAdd() {
-	platform.InheritanceMacro.NativeFunctionMacroAdd()
-}
-
-// Adds PAD_NC macro
-func (platform PlatformSpecific) NoConnMacroAdd() {
-	platform.InheritanceMacro.NoConnMacroAdd()
-}
-
-// GenMacro - generate pad macro
-// dw0val : DW0 config register value
-// dw1val : DW1 config register value
-// return: string of macro
-func (platform PlatformSpecific) GenMacro(id string, dw0Val uint32, dw1Val uint32, ownership uint8) string {
-	// The GPIO controller architecture in Lewisburg and Sunrise are very similar,
-	// so we will inherit some platform-dependent functions from Sunrise.
-	macro := common.GetInstanceMacro(
-		PlatformSpecific{
-			InheritanceMacro: snr.PlatformSpecific{},
-		},
-		fields.InterfaceGet(),
-	)
-	macro.Clear()
-
-	dw0 := macro.GetRegisterDW0()
-	dw0.CntrMaskFieldsClear(bits.All32)
-
-	dw1 := macro.GetRegisterDW1()
-	dw1.CntrMaskFieldsClear(bits.All32)
-
-	dw0.Value = dw0Val
-	dw1.Value = dw1Val
-	dw0.ReadOnly = PAD_CFG_DW0_RO_FIELDS
-	dw1.ReadOnly = PAD_CFG_DW1_RO_FIELDS
-
-	macro.PadIdSet(id).SetPadOwnership(ownership)
-	return macro.Generate()
-}
diff --git a/util/intelp2m/platforms/lbg/template.go b/util/intelp2m/platforms/lbg/template.go
index d76f2cdef3..f4600850df 100644
--- a/util/intelp2m/platforms/lbg/template.go
+++ b/util/intelp2m/platforms/lbg/template.go
@@ -1,15 +1,12 @@
 package lbg
 
-type InheritanceTemplate interface {
-	KeywordCheck(line string) bool
-}
+import "review.coreboot.org/coreboot.git/util/intelp2m/platforms/common"
 
-// Group: "GPP_A", "GPP_B", "GPP_F", "GPP_C", "GPP_D", "GPP_E", "GPD", "GPP_I", "GPP_J",
-//        "GPP_K", "GPP_G", "GPP_H", "GPP_L"
-
-// KeywordCheck - This function is used to filter parsed lines of the configuration file and
-// returns true if the keyword is contained in the line.
-// line : string from the configuration file
-func (platform PlatformSpecific) KeywordCheck(line string) bool {
-	return platform.InheritanceTemplate.KeywordCheck(line)
+// CheckKeyword() parses lines of the configuration file and returns true if the keyword is
+// contained in the line
+// "GPP_A", "GPP_B", "GPP_F", "GPP_C", "GPP_D", "GPP_E", "GPD", "GPP_I", "GPP_J",
+// "GPP_K", "GPP_G", "GPP_H", "GPP_L"
+func CheckKeyword(line string) bool {
+	included, _ := common.KeywordsCheck(line, "GPP_", "GPD")
+	return included
 }
diff --git a/util/intelp2m/platforms/mtl/macro.go b/util/intelp2m/platforms/mtl/macro.go
index d672752b5b..13a3f11043 100644
--- a/util/intelp2m/platforms/mtl/macro.go
+++ b/util/intelp2m/platforms/mtl/macro.go
@@ -1,114 +1,57 @@
 package mtl
 
 import (
-	"fmt"
 	"strings"
 
-	"review.coreboot.org/coreboot.git/util/intelp2m/fields"
+	"review.coreboot.org/coreboot.git/util/intelp2m/logs"
 	"review.coreboot.org/coreboot.git/util/intelp2m/platforms/cnl"
 	"review.coreboot.org/coreboot.git/util/intelp2m/platforms/common"
 	"review.coreboot.org/coreboot.git/util/intelp2m/platforms/common/register/bits"
-	"review.coreboot.org/coreboot.git/util/intelp2m/platforms/snr"
 )
 
 const (
-	PAD_CFG_DW0_RO_FIELDS = (0x1 << 27) | (0x1 << 24) | (0x3 << 21) | (0xf << 16) | 0xfc
-	PAD_CFG_DW1_RO_FIELDS = 0xfdffc3ff
+	DW0Mask = (0b1 << 27) | (0b1 << 24) | (0b11 << 21) | (0b1111 << 16) | 0b11111100
+	DW1Mask = 0b11111101111111111100001111111111
 )
 
-type InheritanceMacro interface {
-	Pull()
-	GpiMacroAdd()
-	GpoMacroAdd()
-	NativeFunctionMacroAdd()
-	NoConnMacroAdd()
+type BasePlatform struct {
+	// based on the Cannon Lake platform
+	cnl.BasePlatform
 }
 
-type PlatformSpecific struct {
-	InheritanceMacro
+func InitBasePlatform(dw0, dw0mask uint32, dw1, dw1mask uint32) BasePlatform {
+	return BasePlatform{cnl.InitBasePlatform(dw0, dw0mask, dw1, dw1mask)}
 }
 
-// RemmapRstSrc - remmap Pad Reset Source Config
-func (PlatformSpecific) RemmapRstSrc() {
-	macro := common.GetMacro()
-	if strings.Contains(macro.PadIdGet(), "GPD") {
+func GetPlatform(dw0, dw1 uint32) common.PlatformIf {
+	p := InitBasePlatform(dw0, DW0Mask, dw1, DW1Mask)
+	return &p
+}
+
+// Override the base platform method
+func (p *BasePlatform) RemapRstSrc(m *common.Macro) {
+	if strings.Contains(m.GetPadId(), "GPD") {
 		// See reset map for the MeteorLake GPD group at
 		// https://github.com/coreboot/coreboot/blob/master/src/soc/intel/meteorlake/gpio.c#L10
 		// remmap is not required because it is the same as common.
 		return
 	}
 
-	dw0 := macro.GetRegisterDW0()
-	var remapping = map[uint32]uint32{
-		0: bits.RstCfgRSMRST << bits.DW0PadRstCfg,
-		1: bits.RstCfgDEEP << bits.DW0PadRstCfg,
-		2: bits.RstCfgPLTRST << bits.DW0PadRstCfg,
-		3: bits.RstCfgPWROK << bits.RstCfgPWROK,
+	remapping := map[uint32]uint32{
+		0b00: bits.RstCfgRSMRST << bits.DW0PadRstCfg,
+		0b01: bits.RstCfgDEEP << bits.DW0PadRstCfg,
+		0b10: bits.RstCfgPLTRST << bits.DW0PadRstCfg,
+		0b11: bits.RstCfgPWROK << bits.RstCfgPWROK,
 	}
-	resetsrc, valid := remapping[dw0.GetResetConfig()]
+	dw0 := p.GetRegisterDW0()
+	source, valid := remapping[dw0.GetResetConfig()]
 	if valid {
-		// dw0.SetResetConfig(resetsrc)
-		ResetConfigFieldVal := (dw0.Value & 0x3fffffff) | remapping[dw0.GetResetConfig()]
-		dw0.Value = ResetConfigFieldVal
+		dw0.Value &= 0x3fffffff
+		dw0.Value |= source
 	} else {
-		fmt.Println("Invalid Pad Reset Config [ 0x", resetsrc, " ] for ", macro.PadIdGet())
+		logs.Errorf("%s: skip re-mapping: DW0 %s: invalid reset config source value 0b%b",
+			m.GetPadId(), dw0, dw0.GetResetConfig())
 	}
 	mask := bits.DW0[bits.DW0PadRstCfg]
 	dw0.CntrMaskFieldsClear(mask)
 }
-
-// Adds The Pad Termination (TERM) parameter from PAD_CFG_DW1 to the macro
-// as a new argument
-func (platform PlatformSpecific) Pull() {
-	platform.InheritanceMacro.Pull()
-}
-
-// Adds PAD_CFG_GPI macro with arguments
-func (platform PlatformSpecific) GpiMacroAdd() {
-	platform.InheritanceMacro.GpiMacroAdd()
-}
-
-// Adds PAD_CFG_GPO macro with arguments
-func (platform PlatformSpecific) GpoMacroAdd() {
-	platform.InheritanceMacro.GpoMacroAdd()
-}
-
-// Adds PAD_CFG_NF macro with arguments
-func (platform PlatformSpecific) NativeFunctionMacroAdd() {
-	platform.InheritanceMacro.NativeFunctionMacroAdd()
-}
-
-// Adds PAD_NC macro
-func (platform PlatformSpecific) NoConnMacroAdd() {
-	platform.InheritanceMacro.NoConnMacroAdd()
-}
-
-// GenMacro - generate pad macro
-// dw0 : DW0 config register value
-// dw1 : DW1 config register value
-// return: string of macro
-func (PlatformSpecific) GenMacro(id string, dw0Val, dw1Val uint32, ownership uint8) string {
-	macro := common.GetInstanceMacro(
-		PlatformSpecific{
-			InheritanceMacro: cnl.PlatformSpecific{
-				InheritanceMacro: snr.PlatformSpecific{},
-			},
-		},
-		fields.InterfaceGet(),
-	)
-	macro.Clear()
-
-	dw0 := macro.GetRegisterDW0()
-	dw0.CntrMaskFieldsClear(bits.All32)
-
-	dw1 := macro.GetRegisterDW1()
-	dw1.CntrMaskFieldsClear(bits.All32)
-
-	dw0.Value = dw0Val
-	dw1.Value = dw1Val
-	dw0.ReadOnly = PAD_CFG_DW0_RO_FIELDS
-	dw1.ReadOnly = PAD_CFG_DW1_RO_FIELDS
-
-	macro.PadIdSet(id).SetPadOwnership(ownership)
-	return macro.Generate()
-}
diff --git a/util/intelp2m/platforms/mtl/mtl_test.go b/util/intelp2m/platforms/mtl/mtl_test.go
index 11f8727883..268d0df336 100644
--- a/util/intelp2m/platforms/mtl/mtl_test.go
+++ b/util/intelp2m/platforms/mtl/mtl_test.go
@@ -3,108 +3,103 @@ package mtl_test
 import (
 	"testing"
 
-	"review.coreboot.org/coreboot.git/util/intelp2m/platforms/cnl"
-	"review.coreboot.org/coreboot.git/util/intelp2m/platforms/mtl"
-	"review.coreboot.org/coreboot.git/util/intelp2m/platforms/snr"
+	"review.coreboot.org/coreboot.git/util/intelp2m/config/p2m"
+	"review.coreboot.org/coreboot.git/util/intelp2m/platforms/common"
 	"review.coreboot.org/coreboot.git/util/intelp2m/platforms/test"
 )
 
 func TestGenMacro(t *testing.T) {
-	meteorlake := mtl.PlatformSpecific{
-		InheritanceMacro: cnl.PlatformSpecific{
-			InheritanceMacro: snr.PlatformSpecific{},
-		},
-	}
+	p2m.Config.Platform = p2m.Meteor
 	test.Suite{
 		{
-			Pad: test.Pad{ID: "GPP_V1", DW0: 0x11111111, DW1: 0x11111111, Ownership: 1},
+			Pad: test.Pad{ID: "GPP_V1", DW0: 0x11111111, DW1: 0x11111111, Ownership: common.Driver},
 			Macro: test.Macro{
 				Short: "PAD_CFG_NF(GPP_V1, DN_20K, RSMRST, NF4),",
 				Long:  "_PAD_CFG_STRUCT(GPP_V1, PAD_FUNC(NF4) | PAD_RESET(RSMRST) | PAD_IRQ_ROUTE(IOAPIC) | PAD_BUF(TX_DISABLE) | (1 << 28) | 1, PAD_PULL(DN_20K) | PAD_IOSSTATE(Tx1RxDCRx1) | PAD_IOSTERM(DISPUPD) | PAD_CFG_OWN_GPIO(DRIVER)),",
 			},
 		},
 		{
-			Pad: test.Pad{ID: "GPP_C2", DW0: 0x22222222, DW1: 0x22222222, Ownership: 0},
+			Pad: test.Pad{ID: "GPP_C2", DW0: 0x22222222, DW1: 0x22222222, Ownership: common.Acpi},
 			Macro: test.Macro{
 				Short: "PAD_CFG_TERM_GPO(GPP_C2, 0, INVALID, RSMRST),",
 				Long:  "_PAD_CFG_STRUCT(GPP_C2, PAD_FUNC(GPIO) | PAD_RESET(RSMRST) | PAD_TRIG(EDGE_SINGLE) | PAD_IRQ_ROUTE(NMI) | PAD_BUF(RX_DISABLE) | (1 << 29) | (1 << 1), PAD_CFG1_TOL_1V8PAD_PULL(INVALID) | PAD_IOSSTATE(HIZCRx1) | PAD_IOSTERM(ENPD)),",
 			},
 		},
 		{
-			Pad: test.Pad{ID: "GPP_A3", DW0: 0x44444444, DW1: 0x44444444, Ownership: 1},
+			Pad: test.Pad{ID: "GPP_A3", DW0: 0x44444444, DW1: 0x44444444, Ownership: common.Driver},
 			Macro: test.Macro{
 				Short: "PAD_CFG_NF(GPP_A3, INVALID, DEEP, NF1),",
 				Long:  "_PAD_CFG_STRUCT(GPP_A3, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_IRQ_ROUTE(SMI), PAD_PULL(INVALID) | PAD_IOSSTATE(Tx0RxDCRx0) | PAD_CFG_OWN_GPIO(DRIVER)),",
 			},
 		},
 		{
-			Pad: test.Pad{ID: "GPP_E4", DW0: 0x88888888, DW1: 0x88888888, Ownership: 0},
+			Pad: test.Pad{ID: "GPP_E4", DW0: 0x88888888, DW1: 0x88888888, Ownership: common.Acpi},
 			Macro: test.Macro{
 				Short: "PAD_CFG_NF(GPP_E4, DN_5K, PLTRST, NF2),",
 				Long:  "_PAD_CFG_STRUCT(GPP_E4, PAD_FUNC(NF2) | PAD_RESET(PLTRST) | PAD_IRQ_ROUTE(SCI) | PAD_RX_POL(INVERT), PAD_PULL(DN_5K) | PAD_IOSSTATE(Tx0RxDCRx1)),",
 			},
 		},
-	}.Run(t, "INTEL-METEOR-LAKE-PCH/SLIDING-ONE-IN-NIBBLE-TEST", meteorlake)
+	}.Run(t, "INTEL-METEOR-LAKE-PCH/SLIDING-ONE-IN-NIBBLE-TEST")
 
 	test.Suite{
 		{
-			Pad: test.Pad{ID: "GPP_H5", DW0: 0xEEEEEEEE, DW1: 0xEEEEEEEE, Ownership: 1},
+			Pad: test.Pad{ID: "GPP_H5", DW0: 0xEEEEEEEE, DW1: 0xEEEEEEEE, Ownership: common.Driver},
 			Macro: test.Macro{
 				Short: "PAD_CFG_NF_1V8(GPP_H5, UP_2K, PWROK, NF3),",
 				Long:  "_PAD_CFG_STRUCT(GPP_H5, PAD_FUNC(NF3) | PAD_TRIG(EDGE_BOTH) | PAD_IRQ_ROUTE(SCI) | PAD_IRQ_ROUTE(SMI) | PAD_IRQ_ROUTE(NMI) | PAD_RX_POL(INVERT) | PAD_BUF(RX_DISABLE) | (1 << 29) | (1 << 1), PAD_CFG1_TOL_1V8PAD_PULL(UP_2K) | PAD_IOSSTATE(ERROR) | PAD_IOSTERM(ENPD) | PAD_CFG_OWN_GPIO(DRIVER)),",
 			},
 		},
 		{
-			Pad: test.Pad{ID: "GPP_F6", DW0: 0xDDDDDDDD, DW1: 0xDDDDDDDD, Ownership: 0},
+			Pad: test.Pad{ID: "GPP_F6", DW0: 0xDDDDDDDD, DW1: 0xDDDDDDDD, Ownership: common.Acpi},
 			Macro: test.Macro{
 				Short: "PAD_CFG_NF(GPP_F6, INVALID, PWROK, NF7),",
 				Long:  "_PAD_CFG_STRUCT(GPP_F6, PAD_FUNC(NF7) | PAD_TRIG(OFF) | PAD_IRQ_ROUTE(IOAPIC) | PAD_IRQ_ROUTE(SCI) | PAD_IRQ_ROUTE(SMI) | PAD_RX_POL(INVERT) | PAD_BUF(TX_DISABLE) | (1 << 28) | 1, PAD_PULL(INVALID) | PAD_IOSSTATE(HIZCRx0) | PAD_IOSTERM(DISPUPD)),",
 			},
 		},
 		{
-			Pad: test.Pad{ID: "GPP_S7", DW0: 0xBBBBBBBB, DW1: 0xBBBBBBBB, Ownership: 1},
+			Pad: test.Pad{ID: "GPP_S7", DW0: 0xBBBBBBBB, DW1: 0xBBBBBBBB, Ownership: common.Driver},
 			Macro: test.Macro{
 				Short: "PAD_CFG_NF_1V8(GPP_S7, INVALID, PLTRST, NF6),",
 				Long:  "_PAD_CFG_STRUCT(GPP_S7, PAD_FUNC(NF6) | PAD_RESET(PLTRST) | PAD_TRIG(EDGE_SINGLE) | PAD_IRQ_ROUTE(IOAPIC) | PAD_IRQ_ROUTE(SCI) | PAD_IRQ_ROUTE(NMI) | PAD_RX_POL(INVERT) | PAD_BUF(TX_RX_DISABLE) | (1 << 29) | (1 << 28) | (1 << 1) | 1, PAD_CFG1_TOL_1V8PAD_PULL(INVALID) | PAD_IOSSTATE(ERROR) | PAD_IOSTERM(ENPU) | PAD_CFG_OWN_GPIO(DRIVER)),",
 			},
 		},
 		{
-			Pad: test.Pad{ID: "GPP_B8", DW0: 0x77777777, DW1: 0x77777777, Ownership: 0},
+			Pad: test.Pad{ID: "GPP_B8", DW0: 0x77777777, DW1: 0x77777777, Ownership: common.Acpi},
 			Macro: test.Macro{
 				Short: "PAD_CFG_NF_1V8(GPP_B8, UP_667, DEEP, NF5),",
 				Long:  "_PAD_CFG_STRUCT(GPP_B8, PAD_FUNC(NF5) | PAD_RESET(DEEP) | PAD_TRIG(EDGE_BOTH) | PAD_IRQ_ROUTE(IOAPIC) | PAD_IRQ_ROUTE(SMI) | PAD_IRQ_ROUTE(NMI) | PAD_BUF(TX_RX_DISABLE) | (1 << 29) | (1 << 28) | (1 << 1) | 1, PAD_CFG1_TOL_1V8PAD_PULL(UP_667) | PAD_IOSSTATE(ERROR) | PAD_IOSTERM(ENPU)),",
 			},
 		},
-	}.Run(t, "INTEL-METEOR-LAKE-PCH/SLIDING-ZERO-IN-NIBBLE-TEST", meteorlake)
+	}.Run(t, "INTEL-METEOR-LAKE-PCH/SLIDING-ZERO-IN-NIBBLE-TEST")
 
 	test.Suite{
 		{
-			Pad: test.Pad{ID: "GPP_D9", DW0: 0x33333333, DW1: 0x33333333, Ownership: 1},
+			Pad: test.Pad{ID: "GPP_D9", DW0: 0x33333333, DW1: 0x33333333, Ownership: common.Driver},
 			Macro: test.Macro{
 				Short: "PAD_CFG_NF_1V8(GPP_D9, UP_20K, RSMRST, NF4),",
 				Long:  "_PAD_CFG_STRUCT(GPP_D9, PAD_FUNC(NF4) | PAD_RESET(RSMRST) | PAD_TRIG(EDGE_SINGLE) | PAD_IRQ_ROUTE(IOAPIC) | PAD_IRQ_ROUTE(NMI) | PAD_BUF(TX_RX_DISABLE) | (1 << 29) | (1 << 28) | (1 << 1) | 1, PAD_CFG1_TOL_1V8PAD_PULL(UP_20K) | PAD_IOSSTATE(ERROR) | PAD_IOSTERM(ENPU) | PAD_CFG_OWN_GPIO(DRIVER)),",
 			},
 		},
 		{
-			Pad: test.Pad{ID: "GPD10", DW0: 0x66666666, DW1: 0x66666666, Ownership: 0},
+			Pad: test.Pad{ID: "GPD10", DW0: 0x66666666, DW1: 0x66666666, Ownership: common.Acpi},
 			Macro: test.Macro{
 				Short: "PAD_CFG_NF_1V8(GPD10, UP_1K, DEEP, NF1),",
 				Long:  "_PAD_CFG_STRUCT(GPD10, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(EDGE_BOTH) | PAD_IRQ_ROUTE(SMI) | PAD_IRQ_ROUTE(NMI) | PAD_BUF(RX_DISABLE) | (1 << 29) | (1 << 1), PAD_CFG1_TOL_1V8PAD_PULL(UP_1K) | PAD_IOSSTATE(TxDRxE) | PAD_IOSTERM(ENPD)),",
 			},
 		},
 		{
-			Pad: test.Pad{ID: "GPP_V11", DW0: 0xCCCCCCCC, DW1: 0xCCCCCCCC, Ownership: 1},
+			Pad: test.Pad{ID: "GPP_V11", DW0: 0xCCCCCCCC, DW1: 0xCCCCCCCC, Ownership: common.Driver},
 			Macro: test.Macro{
 				Short: "PAD_CFG_NF(GPP_V11, INVALID, PWROK, NF3),",
 				Long:  "_PAD_CFG_STRUCT(GPP_V11, PAD_FUNC(NF3) | PAD_TRIG(OFF) | PAD_IRQ_ROUTE(SCI) | PAD_IRQ_ROUTE(SMI) | PAD_RX_POL(INVERT), PAD_PULL(INVALID) | PAD_IOSSTATE(Tx1RxDCRx0) | PAD_CFG_OWN_GPIO(DRIVER)),",
 			},
 		},
 		{
-			Pad: test.Pad{ID: "GPP_C12", DW0: 0x99999999, DW1: 0x99999999, Ownership: 0},
+			Pad: test.Pad{ID: "GPP_C12", DW0: 0x99999999, DW1: 0x99999999, Ownership: common.Acpi},
 			Macro: test.Macro{
 				Short: "PAD_CFG_NF(GPP_C12, INVALID, PLTRST, NF6),",
 				Long:  "_PAD_CFG_STRUCT(GPP_C12, PAD_FUNC(NF6) | PAD_RESET(PLTRST) | PAD_IRQ_ROUTE(IOAPIC) | PAD_IRQ_ROUTE(SCI) | PAD_RX_POL(INVERT) | PAD_BUF(TX_DISABLE) | (1 << 28) | 1, PAD_PULL(INVALID) | PAD_IOSSTATE(Tx1RxE) | PAD_IOSTERM(DISPUPD)),",
 			},
 		},
-	}.Run(t, "INTEL-METEOR-LAKE-PCH/SLIDING-ONE-ONE-IN-NIBBLE-TEST", meteorlake)
+	}.Run(t, "INTEL-METEOR-LAKE-PCH/SLIDING-ONE-ONE-IN-NIBBLE-TEST")
 }
diff --git a/util/intelp2m/platforms/mtl/template.go b/util/intelp2m/platforms/mtl/template.go
index 3f44928909..27951fefb5 100644
--- a/util/intelp2m/platforms/mtl/template.go
+++ b/util/intelp2m/platforms/mtl/template.go
@@ -5,10 +5,10 @@ import "review.coreboot.org/coreboot.git/util/intelp2m/platforms/common"
 // Group : "GPP_V", "GPP_C", "GPP_A", "GPP_E", "GPP_H", "GPP_F", "GPP_S", "GPP_B", "GPP_D",
 //         "GPD", "VGPIO_USB", "VGPIO_PCIE"
 
-// KeywordCheck - This function is used to filter parsed lines of the configuration file and
+// CheckKeyword - This function is used to filter parsed lines of the configuration file and
 // returns true if the keyword is contained in the line.
 // line : string from the configuration file
-func (PlatformSpecific) KeywordCheck(line string) bool {
+func CheckKeyword(line string) bool {
 	isIncluded, _ := common.KeywordsCheck(line, "GPP_", "GPD", "VGPIO")
 	return isIncluded
 }
diff --git a/util/intelp2m/platforms/platforms.go b/util/intelp2m/platforms/platforms.go
new file mode 100644
index 0000000000..cb65903e8b
--- /dev/null
+++ b/util/intelp2m/platforms/platforms.go
@@ -0,0 +1,62 @@
+package platforms
+
+import (
+	"fmt"
+
+	"review.coreboot.org/coreboot.git/util/intelp2m/config/p2m"
+	"review.coreboot.org/coreboot.git/util/intelp2m/logs"
+	"review.coreboot.org/coreboot.git/util/intelp2m/platforms/adl"
+	"review.coreboot.org/coreboot.git/util/intelp2m/platforms/apl"
+	"review.coreboot.org/coreboot.git/util/intelp2m/platforms/cnl"
+	"review.coreboot.org/coreboot.git/util/intelp2m/platforms/common"
+	"review.coreboot.org/coreboot.git/util/intelp2m/platforms/ebg"
+	"review.coreboot.org/coreboot.git/util/intelp2m/platforms/jsl"
+	"review.coreboot.org/coreboot.git/util/intelp2m/platforms/lbg"
+	"review.coreboot.org/coreboot.git/util/intelp2m/platforms/mtl"
+	"review.coreboot.org/coreboot.git/util/intelp2m/platforms/snr"
+	"review.coreboot.org/coreboot.git/util/intelp2m/platforms/tgl"
+)
+
+type KeywordAction func(line string) bool
+
+type Constructor func(dw0, dw1 uint32) common.PlatformIf
+
+var platformConstructorMap = map[p2m.PlatformType]Constructor{
+	p2m.Alder:      adl.GetPlatform,
+	p2m.Apollo:     apl.GetPlatform,
+	p2m.Cannon:     cnl.GetPlatform,
+	p2m.Sunrise:    snr.GetPlatform,
+	p2m.Tiger:      tgl.GetPlatform,
+	p2m.Jasper:     jsl.GetPlatform,
+	p2m.Meteor:     mtl.GetPlatform,
+	p2m.Emmitsburg: ebg.GetPlatform,
+	p2m.Lewisburg:  lbg.GetPlatform,
+}
+
+func GetKeywordChekingAction() KeywordAction {
+	actions := map[p2m.PlatformType]KeywordAction{
+		p2m.Alder:      adl.CheckKeyword,
+		p2m.Apollo:     apl.CheckKeyword,
+		p2m.Cannon:     cnl.CheckKeyword,
+		p2m.Sunrise:    snr.CheckKeyword,
+		p2m.Tiger:      tgl.CheckKeyword,
+		p2m.Jasper:     jsl.CheckKeyword,
+		p2m.Meteor:     mtl.CheckKeyword,
+		p2m.Emmitsburg: ebg.CheckKeyword,
+		p2m.Lewisburg:  lbg.CheckKeyword,
+	}
+	action, exist := actions[p2m.Config.Platform]
+	if !exist {
+		logs.Errorf("unregistered platform type %d", p2m.Config.Platform)
+		return nil
+	}
+	return action
+}
+
+func GetConstructor() (Constructor, error) {
+	constructor, exist := platformConstructorMap[p2m.Config.Platform]
+	if !exist {
+		return nil, fmt.Errorf("unregistered platform type %d", p2m.Config.Platform)
+	}
+	return constructor, nil
+}
diff --git a/util/intelp2m/platforms/snr/macro.go b/util/intelp2m/platforms/snr/macro.go
index 7eee4bf351..9a4ace4753 100644
--- a/util/intelp2m/platforms/snr/macro.go
+++ b/util/intelp2m/platforms/snr/macro.go
@@ -1,150 +1,149 @@
 package snr
 
 import (
-	"fmt"
 	"strings"
 
 	"review.coreboot.org/coreboot.git/util/intelp2m/config/p2m"
-	"review.coreboot.org/coreboot.git/util/intelp2m/fields"
+	"review.coreboot.org/coreboot.git/util/intelp2m/logs"
 	"review.coreboot.org/coreboot.git/util/intelp2m/platforms/common"
 	"review.coreboot.org/coreboot.git/util/intelp2m/platforms/common/register/bits"
 )
 
 const (
-	PAD_CFG_DW0_RO_FIELDS = (0x1 << 27) | (0x1 << 24) | (0x3 << 21) | (0xf << 16) | 0xfc
-	PAD_CFG_DW1_RO_FIELDS = 0xfdffc3ff
+	DW0Mask uint32 = (0b1 << 27) | (0b1 << 24) | (0b11 << 21) | (0b1111 << 16) | 0b11111100
+	DW1Mask uint32 = 0b11111101111111111100001111111111
 )
 
-type PlatformSpecific struct{}
+type BasePlatform struct {
+	common.BasePlatform
+}
 
-// RemmapRstSrc - remmap Pad Reset Source Config
-func (PlatformSpecific) RemmapRstSrc() {
-	macro := common.GetMacro()
-	if strings.Contains(macro.PadIdGet(), "GPD") {
+func InitBasePlatform(dw0, dw0mask uint32, dw1, dw1mask uint32) BasePlatform {
+	return BasePlatform{common.InitBasePlatform(dw0, dw0mask, dw1, dw1mask)}
+}
+
+func GetPlatform(dw0, dw1 uint32) common.PlatformIf {
+	p := InitBasePlatform(dw0, DW0Mask, dw1, DW1Mask)
+	return &p
+}
+
+// RemmapRstSrc() remaps Pad Reset Source Config
+func (p *BasePlatform) RemapRstSrc(m *common.Macro) {
+	if strings.Contains(m.GetPadId(), "GPD") {
 		// See reset map for the Sunrise GPD Group in the Community 2:
 		// https://github.com/coreboot/coreboot/blob/master/src/soc/intel/skylake/gpio.c#L15
 		// remmap is not required because it is the same as common.
 		return
 	}
 
-	dw0 := macro.GetRegisterDW0()
+	dw0 := p.GetRegisterDW0()
 	remapping := map[uint32]uint32{
-		0: bits.RstCfgRSMRST << bits.DW0PadRstCfg,
-		1: bits.RstCfgDEEP << bits.DW0PadRstCfg,
-		2: bits.RstCfgPLTRST << bits.DW0PadRstCfg,
+		0b00: bits.RstCfgRSMRST << bits.DW0PadRstCfg,
+		0b01: bits.RstCfgDEEP << bits.DW0PadRstCfg,
+		0b10: bits.RstCfgPLTRST << bits.DW0PadRstCfg,
 	}
-	resetsrc, valid := remapping[dw0.GetResetConfig()]
-	if valid {
-		// dw0.SetResetConfig(resetsrc)
-		ResetConfigFieldVal := (dw0.Value & 0x3fffffff) | remapping[dw0.GetResetConfig()]
-		dw0.Value = ResetConfigFieldVal
+
+	if source, valid := remapping[dw0.GetResetConfig()]; valid {
+		dw0.Value &= 0x3fffffff
+		dw0.Value |= source
 	} else {
-		fmt.Println("Invalid Pad Reset Config [ 0x", resetsrc, " ] for ", macro.PadIdGet())
+		logs.Errorf("%s: skip re-mapping: DW0 %s: invalid reset config source value 0b%b",
+			m.GetPadId(), dw0, dw0.GetResetConfig())
 	}
-	mask := bits.DW0[bits.DW0PadRstCfg]
-	dw0.CntrMaskFieldsClear(mask)
+	dw0.CntrMaskFieldsClear(bits.DW0[bits.DW0PadRstCfg])
 }
 
-// Adds The Pad Termination (TERM) parameter from PAD_CFG_DW1 to the macro
-// as a new argument
-func (PlatformSpecific) Pull() {
-	macro := common.GetMacro()
-	dw1 := macro.GetRegisterDW1()
+// Pull() adds The Pad Termination (TERM) parameter from PAD_CFG_DW1 to the macro
+func (p *BasePlatform) Pull(m *common.Macro) {
+	dw1 := p.GetRegisterDW1()
 	var pull = map[uint32]string{
-		0x0: "NONE",
-		0x2: "DN_5K",
-		0x4: "DN_20K",
-		0x9: "UP_1K",
-		0xa: "UP_5K",
-		0xb: "UP_2K",
-		0xc: "UP_20K",
-		0xd: "UP_667",
-		0xf: "NATIVE",
+		0b0000: "NONE",
+		0b0010: "DN_5K",
+		0b0100: "DN_20K",
+		0b1001: "UP_1K",
+		0b1010: "UP_5K",
+		0b1011: "UP_2K",
+		0b1100: "UP_20K",
+		0b1101: "UP_667",
+		0b1111: "NATIVE",
 	}
-	str, valid := pull[dw1.GetTermination()]
+	term, valid := pull[dw1.GetTermination()]
 	if !valid {
-		str = "INVALID"
-		fmt.Println("Error",
-			macro.PadIdGet(),
-			" invalid TERM value = ",
-			int(dw1.GetTermination()))
+		term = "INVALID"
+		logs.Errorf("%s: DW1 %s: invalid termination value 0b%b",
+			dw1, m.GetPadId(), dw1.GetTermination())
 	}
-	macro.Separator().Add(str)
+	m.Separator().Add(term)
 }
 
-// Generate macro to cause peripheral IRQ when configured in GPIO input mode
-func ioApicRoute() bool {
-	macro := common.GetMacro()
-	dw0 := macro.GetRegisterDW0()
+// ioApicRoute() generate macro to cause peripheral IRQ when configured in GPIO input mode
+func ioApicRoute(p *BasePlatform, m *common.Macro) bool {
+	dw0 := p.GetRegisterDW0()
 	if dw0.GetGPIOInputRouteIOxAPIC() == 0 {
 		return false
 	}
 
-	macro.Add("_APIC")
+	m.Add("_APIC")
 	if dw0.GetRXLevelEdgeConfiguration() == bits.TrigLEVEL {
 		if dw0.GetRxInvert() != 0 {
 			// PAD_CFG_GPI_APIC_LOW(pad, pull, rst)
-			macro.Add("_LOW")
+			m.Add("_LOW")
 		} else {
 			// PAD_CFG_GPI_APIC_HIGH(pad, pull, rst)
-			macro.Add("_HIGH")
+			m.Add("_HIGH")
 		}
-		macro.Add("(").Id().Pull().Rstsrc().Add("),")
+		m.Add("(").Id().Pull().Rstsrc().Add("),")
 		return true
 	}
 
 	// e.g. PAD_CFG_GPI_APIC_IOS(pad, pull, rst, trig, inv, iosstate, iosterm)
-	macro.Add("_IOS(").Id().Pull().Rstsrc().Trig().Invert().Add(", TxLASTRxE, SAME),")
+	m.Add("_IOS(").Id().Pull().Rstsrc().Trig().Invert().Add(", TxLASTRxE, SAME),")
 	return true
 }
 
-// Generate macro to cause NMI when configured in GPIO input mode
-func nmiRoute() bool {
-	macro := common.GetMacro()
-	if macro.GetRegisterDW0().GetGPIOInputRouteNMI() == 0 {
+// nmiRoute() generate macro to cause NMI when configured in GPIO input mode
+func nmiRoute(p *BasePlatform, m *common.Macro) bool {
+	if p.GetRegisterDW0().GetGPIOInputRouteNMI() == 0 {
 		return false
 	}
 	// PAD_CFG_GPI_NMI(GPIO_24, UP_20K, DEEP, LEVEL, INVERT),
-	macro.Add("_NMI").Add("(").Id().Pull().Rstsrc().Trig().Invert().Add("),")
+	m.Add("_NMI").Add("(").Id().Pull().Rstsrc().Trig().Invert().Add("),")
 	return true
 }
 
-// Generate macro to cause SCI when configured in GPIO input mode
-func sciRoute() bool {
-	macro := common.GetMacro()
-	dw0 := macro.GetRegisterDW0()
+// sciRoute() generate macro to cause SCI when configured in GPIO input mode
+func sciRoute(p *BasePlatform, m *common.Macro) bool {
+	dw0 := p.GetRegisterDW0()
 	if dw0.GetGPIOInputRouteSCI() == 0 {
 		return false
 	}
 	// PAD_CFG_GPI_SCI(GPP_B18, UP_20K, PLTRST, LEVEL, INVERT),
-	macro.Add("_SCI").Add("(").Id().Pull().Rstsrc().Trig().Invert().Add("),")
+	m.Add("_SCI").Add("(").Id().Pull().Rstsrc().Trig().Invert().Add("),")
 	return true
 }
 
-// Generate macro to cause SMI when configured in GPIO input mode
-func smiRoute() bool {
-	macro := common.GetMacro()
-	dw0 := macro.GetRegisterDW0()
+// smiRoute() generates macro to cause SMI when configured in GPIO input mode
+func smiRoute(p *BasePlatform, m *common.Macro) bool {
+	dw0 := p.GetRegisterDW0()
 	if dw0.GetGPIOInputRouteSMI() == 0 {
 		return false
 	}
 	// PAD_CFG_GPI_SMI(GPP_E7, NONE, DEEP, LEVEL, NONE),
-	macro.Add("_SMI").Add("(").Id().Pull().Rstsrc().Trig().Invert().Add("),")
+	m.Add("_SMI").Add("(").Id().Pull().Rstsrc().Trig().Invert().Add("),")
 	return true
 }
 
-// Adds PAD_CFG_GPI macro with arguments
-func (PlatformSpecific) GpiMacroAdd() {
-	macro := common.GetMacro()
+// AddGpiMacro() adds PAD_CFG_GPI macro with arguments
+func (p *BasePlatform) AddGpiMacro(m *common.Macro) {
 	var ids []string
-	macro.Set("PAD_CFG_GPI")
-	for routeid, isRoute := range map[string]func() bool{
+	m.Set("PAD_CFG_GPI")
+	for routeid, isRoute := range map[string]func(*BasePlatform, *common.Macro) bool{
 		"IOAPIC": ioApicRoute,
 		"SCI":    sciRoute,
 		"SMI":    smiRoute,
 		"NMI":    nmiRoute,
 	} {
-		if isRoute() {
+		if isRoute(p, m) {
 			ids = append(ids, routeid)
 		}
 	}
@@ -152,80 +151,77 @@ func (PlatformSpecific) GpiMacroAdd() {
 	switch argc := len(ids); argc {
 	case 0:
 		// e.g. PAD_CFG_GPI_TRIG_OWN(pad, pull, rst, trig, own)
-		macro.Add("_TRIG_OWN").Add("(").Id().Pull().Rstsrc().Trig().Own().Add("),")
+		m.Add("_TRIG_OWN").Add("(").Id().Pull().Rstsrc().Trig().Own().Add("),")
 	case 1:
 		// GPI with IRQ route
 		if p2m.Config.IgnoredFields {
 			// Set Host Software Ownership to ACPI mode
-			macro.SetPadOwnership(common.PAD_OWN_ACPI)
+			m.SetOwnershipAcpi()
 		}
 
 	case 2:
 		// PAD_CFG_GPI_DUAL_ROUTE(pad, pull, rst, trig, inv, route1, route2)
-		macro.Set("PAD_CFG_GPI_DUAL_ROUTE(").Id().Pull().Rstsrc().Trig().Invert()
-		macro.Add(", " + ids[0] + ", " + ids[1] + "),")
+		m.Set("PAD_CFG_GPI_DUAL_ROUTE(").Id().Pull().Rstsrc().Trig().Invert()
+		m.Add(", " + ids[0] + ", " + ids[1] + "),")
 		if p2m.Config.IgnoredFields {
 			// Set Host Software Ownership to ACPI mode
-			macro.SetPadOwnership(common.PAD_OWN_ACPI)
+			m.SetOwnershipAcpi()
 		}
 	default:
 		// Clear the control mask so that the check fails and "Advanced" macro is
 		// generated
-		macro.GetRegisterDW0().CntrMaskFieldsClear(bits.All32)
+		dw0 := p.GetRegisterDW0()
+		dw0.CntrMaskFieldsClear(bits.All32)
 	}
 }
 
-// Adds PAD_CFG_GPO macro with arguments
-func (PlatformSpecific) GpoMacroAdd() {
-	macro := common.GetMacro()
-	dw0 := macro.GetRegisterDW0()
-	term := macro.GetRegisterDW1().GetTermination()
-
+// AddGpoMacro() adds PAD_CFG_GPO macro with arguments
+func (p *BasePlatform) AddGpoMacro(m *common.Macro) {
 	// #define PAD_CFG_GPO(pad, val, rst)                \
 	//    _PAD_CFG_STRUCT(pad,                           \
 	//      PAD_FUNC(GPIO) | PAD_RESET(rst) |            \
 	//      PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | !!val, \
 	//      PAD_PULL(NONE) | PAD_IOSSTATE(TxLASTRxE))
-	if dw0.GetRXLevelEdgeConfiguration() != bits.TrigOFF {
+	if dw0 := p.GetRegisterDW0(); dw0.GetRXLevelEdgeConfiguration() != bits.TrigOFF {
 		mask := bits.DW0[bits.DW0RxLevelEdgeConfiguration]
 		dw0.CntrMaskFieldsClear(mask)
 	}
-	macro.Set("PAD_CFG")
-	if macro.IsOwnershipDriver() {
+	m.Set("PAD_CFG")
+	if m.IsOwnershipDriver() {
 		// PAD_CFG_GPO_GPIO_DRIVER(pad, val, rst, pull)
-		macro.Add("_GPO_GPIO_DRIVER").Add("(").Id().Val().Rstsrc().Pull().Add("),")
+		m.Add("_GPO_GPIO_DRIVER").Add("(").Id().Val().Rstsrc().Pull().Add("),")
 		return
 	}
+	dw1 := p.GetRegisterDW1()
+	term := dw1.GetTermination()
 	if term != 0 {
 		// e.g. PAD_CFG_TERM_GPO(GPP_B23, 1, DN_20K, DEEP),
-		macro.Add("_TERM")
+		m.Add("_TERM")
 	}
-	macro.Add("_GPO").Add("(").Id().Val()
+	m.Add("_GPO").Add("(").Id().Val()
 	if term != 0 {
-		macro.Pull()
+		m.Pull()
 	}
-	macro.Rstsrc().Add("),")
+	m.Rstsrc().Add("),")
 }
 
-// Adds PAD_CFG_NF macro with arguments
-func (PlatformSpecific) NativeFunctionMacroAdd() {
-	macro := common.GetMacro()
+// AddNativeFunctionMacro() adds PAD_CFG_NF macro with arguments
+func (p *BasePlatform) AddNativeFunctionMacro(m *common.Macro) {
 	// e.g. PAD_CFG_NF(GPP_D23, NONE, DEEP, NF1)
-	macro.Set("PAD_CFG_NF")
-	if macro.GetRegisterDW1().GetPadTol() != 0 {
-		macro.Add("_1V8")
+	m.Set("PAD_CFG_NF")
+	if p.GetRegisterDW1().GetPadTol() != 0 {
+		m.Add("_1V8")
 	}
-	macro.Add("(").Id().Pull().Rstsrc().Padfn().Add("),")
+	m.Add("(").Id().Pull().Rstsrc().Padfn().Add("),")
 }
 
-// Adds PAD_NC macro
-func (PlatformSpecific) NoConnMacroAdd() {
-	macro := common.GetMacro()
+// AddNoConnMacro() adds PAD_NC macro
+func (p *BasePlatform) AddNoConnMacro(m *common.Macro) {
 	// #define PAD_NC(pad, pull)
 	// _PAD_CFG_STRUCT(pad,
 	//     PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE),
 	//     PAD_PULL(pull) | PAD_IOSSTATE(TxDRxE)),
-	dw0 := macro.GetRegisterDW0()
+	dw0 := p.GetRegisterDW0()
 
 	// Some fields of the configuration registers are hidden inside the macros,
 	// we should check them to update the corresponding bits in the control mask.
@@ -237,32 +233,5 @@ func (PlatformSpecific) NoConnMacroAdd() {
 		mask := bits.DW0[bits.DW0PadRstCfg]
 		dw0.CntrMaskFieldsClear(mask)
 	}
-
-	macro.Set("PAD_NC").Add("(").Id().Pull().Add("),")
-}
-
-// GenMacro - generate pad macro
-// dw0Val : DW0 config register value
-// dw1Val : DW1 config register value
-// return: string of macro
-func (PlatformSpecific) GenMacro(id string, dw0Val uint32, dw1Val uint32, ownership uint8) string {
-	macro := common.GetInstanceMacro(
-		PlatformSpecific{},
-		fields.InterfaceGet(),
-	)
-	macro.Clear()
-
-	dw0 := macro.GetRegisterDW0()
-	dw0.CntrMaskFieldsClear(bits.All32)
-
-	dw1 := macro.GetRegisterDW1()
-	dw1.CntrMaskFieldsClear(bits.All32)
-
-	dw0.Value = dw0Val
-	dw1.Value = dw1Val
-	dw0.ReadOnly = PAD_CFG_DW0_RO_FIELDS
-	dw1.ReadOnly = PAD_CFG_DW1_RO_FIELDS
-
-	macro.PadIdSet(id).SetPadOwnership(ownership)
-	return macro.Generate()
+	m.Set("PAD_NC").Add("(").Id().Pull().Add("),")
 }
diff --git a/util/intelp2m/platforms/snr/snr_test.go b/util/intelp2m/platforms/snr/snr_test.go
index 8a52396ece..935e8c2ae1 100644
--- a/util/intelp2m/platforms/snr/snr_test.go
+++ b/util/intelp2m/platforms/snr/snr_test.go
@@ -3,207 +3,208 @@ package snr_test
 import (
 	"testing"
 
-	"review.coreboot.org/coreboot.git/util/intelp2m/platforms/snr"
+	"review.coreboot.org/coreboot.git/util/intelp2m/config/p2m"
+	"review.coreboot.org/coreboot.git/util/intelp2m/platforms/common"
 	"review.coreboot.org/coreboot.git/util/intelp2m/platforms/test"
 )
 
 func TestGenMacro(t *testing.T) {
-	sunrise := snr.PlatformSpecific{}
+	p2m.Config.Platform = p2m.Sunrise
 	test.Suite{
 		{ /* GPP_A1 - LAD0  */
-			Pad: test.Pad{ID: "GPP_A1", DW0: 0x84000402, DW1: 0x00003000, Ownership: 0},
+			Pad: test.Pad{ID: "GPP_A1", DW0: 0x84000402, DW1: 0x00003000, Ownership: common.Acpi},
 			Macro: test.Macro{
 				Short: "PAD_CFG_NF(GPP_A1, UP_20K, PLTRST, NF1),",
 				Long:  "_PAD_CFG_STRUCT(GPP_A1, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | (1 << 1), PAD_PULL(UP_20K)),",
 			},
 		},
 		{ /* GPP_A5 - LFRAME# */
-			Pad: test.Pad{ID: "GPP_A5", DW0: 0x84000600, DW1: 0x00000000, Ownership: 0},
+			Pad: test.Pad{ID: "GPP_A5", DW0: 0x84000600, DW1: 0x00000000, Ownership: common.Acpi},
 			Macro: test.Macro{
 				Short: "PAD_CFG_NF(GPP_A5, NONE, PLTRST, NF1),",
 				Long:  "_PAD_CFG_STRUCT(GPP_A5, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), 0),",
 			},
 		},
 		{ /* GPP_A22 - GPIO */
-			Pad: test.Pad{ID: "GPP_A22", DW0: 0x84000102, DW1: 0x00000000, Ownership: 0},
+			Pad: test.Pad{ID: "GPP_A22", DW0: 0x84000102, DW1: 0x00000000, Ownership: common.Acpi},
 			Macro: test.Macro{
 				Short: "PAD_CFG_GPI_TRIG_OWN(GPP_A22, NONE, PLTRST, OFF, ACPI),",
 				Long:  "_PAD_CFG_STRUCT(GPP_A22, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0),",
 			},
 		},
 		{ /* GPP_B3 - GPIO */
-			Pad: test.Pad{ID: "GPP_B3", DW0: 0x44000201, DW1: 0x00000000, Ownership: 0},
+			Pad: test.Pad{ID: "GPP_B3", DW0: 0x44000201, DW1: 0x00000000, Ownership: common.Acpi},
 			Macro: test.Macro{
 				Short: "PAD_CFG_GPO(GPP_B3, 1, DEEP),",
 				Long:  "_PAD_CFG_STRUCT(GPP_B3, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, 0),",
 			},
 		},
 		{ /* GPP_B5 - GPIO */
-			Pad: test.Pad{ID: "GPP_B5", DW0: 0x84000100, DW1: 0x00000000, Ownership: 0},
+			Pad: test.Pad{ID: "GPP_B5", DW0: 0x84000100, DW1: 0x00000000, Ownership: common.Acpi},
 			Macro: test.Macro{
 				Short: "PAD_CFG_GPI_TRIG_OWN(GPP_B5, NONE, PLTRST, OFF, ACPI),",
 				Long:  "_PAD_CFG_STRUCT(GPP_B5, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), 0),",
 			},
 		},
 		{ /* GPP_B8 - NC */
-			Pad: test.Pad{ID: "GPP_B8", DW0: 0x44000300, DW1: 0x00000000, Ownership: 0},
+			Pad: test.Pad{ID: "GPP_B8", DW0: 0x44000300, DW1: 0x00000000, Ownership: common.Acpi},
 			Macro: test.Macro{
 				Short: "PAD_NC(GPP_B8, NONE),",
 				Long:  "_PAD_CFG_STRUCT(GPP_B8, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),",
 			},
 		},
 		{ /* GPP_C2 - GPIO */
-			Pad: test.Pad{ID: "GPP_C2", DW0: 0x44000201, DW1: 0x00000000, Ownership: 0},
+			Pad: test.Pad{ID: "GPP_C2", DW0: 0x44000201, DW1: 0x00000000, Ownership: common.Acpi},
 			Macro: test.Macro{
 				Short: "PAD_CFG_GPO(GPP_C2, 1, DEEP),",
 				Long:  "_PAD_CFG_STRUCT(GPP_C2, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, 0),",
 			},
 		},
 		{ /* GPP_C10 - GPIO */
-			Pad: test.Pad{ID: "GPP_C10", DW0: 0x04000000, DW1: 0x00000000, Ownership: 0},
+			Pad: test.Pad{ID: "GPP_C10", DW0: 0x04000000, DW1: 0x00000000, Ownership: common.Acpi},
 			Macro: test.Macro{
 				Short: "PAD_CFG_GPIO_BIDIRECT(GPP_C10, 0, NONE, RSMRST, OFF, ACPI),",
 				Long:  "_PAD_CFG_STRUCT(GPP_C10, PAD_FUNC(GPIO) | PAD_RESET(RSMRST) | PAD_TRIG(OFF), 0),",
 			},
 		},
 		{ /* GPP_C22 - UART2_RTS#  */
-			Pad: test.Pad{ID: "GPP_C22", DW0: 0x84000600, DW1: 0x00000000, Ownership: 0},
+			Pad: test.Pad{ID: "GPP_C22", DW0: 0x84000600, DW1: 0x00000000, Ownership: common.Acpi},
 			Macro: test.Macro{
 				Short: "PAD_CFG_NF(GPP_C22, NONE, PLTRST, NF1),",
 				Long:  "_PAD_CFG_STRUCT(GPP_C22, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), 0),",
 			},
 		},
 		{ /* GPP_C23 - GPIO */
-			Pad: test.Pad{ID: "GPP_C23", DW0: 0x40880102, DW1: 0x00000000, Ownership: 0},
+			Pad: test.Pad{ID: "GPP_C23", DW0: 0x40880102, DW1: 0x00000000, Ownership: common.Acpi},
 			Macro: test.Macro{
 				Short: "PAD_CFG_GPI_SCI(GPP_C23, NONE, DEEP, LEVEL, INVERT),",
 				Long:  "_PAD_CFG_STRUCT(GPP_C23, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_IRQ_ROUTE(SCI) | PAD_RX_POL(INVERT) | PAD_BUF(TX_DISABLE) | (1 << 1), 0),",
 			},
 		},
 		{ /* GPP_D0 - GPIO */
-			Pad: test.Pad{ID: "GPP_D0", DW0: 0x84000200, DW1: 0x00000000, Ownership: 0},
+			Pad: test.Pad{ID: "GPP_D0", DW0: 0x84000200, DW1: 0x00000000, Ownership: common.Acpi},
 			Macro: test.Macro{
 				Short: "PAD_CFG_GPO(GPP_D0, 0, PLTRST),",
 				Long:  "_PAD_CFG_STRUCT(GPP_D0, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), 0),",
 			},
 		},
 		{ /* GPP_D16 - GPIO */
-			Pad: test.Pad{ID: "GPP_D16", DW0: 0x84000100, DW1: 0x00000000, Ownership: 0},
+			Pad: test.Pad{ID: "GPP_D16", DW0: 0x84000100, DW1: 0x00000000, Ownership: common.Acpi},
 			Macro: test.Macro{
 				Short: "PAD_CFG_GPI_TRIG_OWN(GPP_D16, NONE, PLTRST, OFF, ACPI),",
 				Long:  "_PAD_CFG_STRUCT(GPP_D16, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), 0),",
 			},
 		},
 		{ /* GPP_E0 - SATAXPCIE0 */
-			Pad: test.Pad{ID: "GPP_E0", DW0: 0x84000502, DW1: 0x00003000, Ownership: 0},
+			Pad: test.Pad{ID: "GPP_E0", DW0: 0x84000502, DW1: 0x00003000, Ownership: common.Acpi},
 			Macro: test.Macro{
 				Short: "PAD_CFG_NF(GPP_E0, UP_20K, PLTRST, NF1),",
 				Long:  "_PAD_CFG_STRUCT(GPP_E0, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), PAD_PULL(UP_20K)),",
 			},
 		},
 		{ /* GPP_E7 - GPIO */
-			Pad: test.Pad{ID: "GPP_E7", DW0: 0x84000102, DW1: 0x00000000, Ownership: 1},
+			Pad: test.Pad{ID: "GPP_E7", DW0: 0x84000102, DW1: 0x00000000, Ownership: common.Driver},
 			Macro: test.Macro{
 				Short: "PAD_CFG_GPI_TRIG_OWN(GPP_E7, NONE, PLTRST, OFF, DRIVER),",
 				Long:  "_PAD_CFG_STRUCT(GPP_E7, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), PAD_CFG_OWN_GPIO(DRIVER)),",
 			},
 		},
 		{ /* GPP_F2 - GPIO */
-			Pad: test.Pad{ID: "GPP_F2", DW0: 0x44000300, DW1: 0x00000000, Ownership: 0},
+			Pad: test.Pad{ID: "GPP_F2", DW0: 0x44000300, DW1: 0x00000000, Ownership: common.Acpi},
 			Macro: test.Macro{
 				Short: "PAD_NC(GPP_F2, NONE),",
 				Long:  "_PAD_CFG_STRUCT(GPP_F2, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),",
 			},
 		},
 		{ /* GPP_F12 - GPIO */
-			Pad: test.Pad{ID: "GPP_F12", DW0: 0x80900102, DW1: 0x00000000, Ownership: 0},
+			Pad: test.Pad{ID: "GPP_F12", DW0: 0x80900102, DW1: 0x00000000, Ownership: common.Acpi},
 			Macro: test.Macro{
 				Short: "PAD_CFG_GPI_APIC_LOW(GPP_F12, NONE, PLTRST),",
 				Long:  "_PAD_CFG_STRUCT(GPP_F12, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_IRQ_ROUTE(IOAPIC) | PAD_RX_POL(INVERT) | PAD_BUF(TX_DISABLE) | (1 << 1), 0),",
 			},
 		},
 		{ /* GPP_F13 - GPIO */
-			Pad: test.Pad{ID: "GPP_F13", DW0: 0x80100102, DW1: 0x00000000, Ownership: 0},
+			Pad: test.Pad{ID: "GPP_F13", DW0: 0x80100102, DW1: 0x00000000, Ownership: common.Acpi},
 			Macro: test.Macro{
 				Short: "PAD_CFG_GPI_APIC_HIGH(GPP_F13, NONE, PLTRST),",
 				Long:  "_PAD_CFG_STRUCT(GPP_F13, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_IRQ_ROUTE(IOAPIC) | PAD_BUF(TX_DISABLE) | (1 << 1), 0),",
 			},
 		},
 		{ /* GPP_F14 - GPIO */
-			Pad: test.Pad{ID: "GPP_F14", DW0: 0x40900102, DW1: 0x00000000, Ownership: 0},
+			Pad: test.Pad{ID: "GPP_F14", DW0: 0x40900102, DW1: 0x00000000, Ownership: common.Acpi},
 			Macro: test.Macro{
 				Short: "PAD_CFG_GPI_APIC_LOW(GPP_F14, NONE, DEEP),",
 				Long:  "_PAD_CFG_STRUCT(GPP_F14, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_IRQ_ROUTE(IOAPIC) | PAD_RX_POL(INVERT) | PAD_BUF(TX_DISABLE) | (1 << 1), 0),",
 			},
 		},
 		{ /* GPP_H13 - GPIO */
-			Pad: test.Pad{ID: "GPP_H13", DW0: 0x80100102, DW1: 0x00000000, Ownership: 0},
+			Pad: test.Pad{ID: "GPP_H13", DW0: 0x80100102, DW1: 0x00000000, Ownership: common.Acpi},
 			Macro: test.Macro{
 				Short: "PAD_CFG_GPI_APIC_HIGH(GPP_H13, NONE, PLTRST),",
 				Long:  "_PAD_CFG_STRUCT(GPP_H13, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_IRQ_ROUTE(IOAPIC) | PAD_BUF(TX_DISABLE) | (1 << 1), 0),",
 			},
 		},
 		{ /* GPD1 - GPIO */
-			Pad: test.Pad{ID: "GPD1", DW0: 0x04000200, DW1: 0x00000000, Ownership: 0},
+			Pad: test.Pad{ID: "GPD1", DW0: 0x04000200, DW1: 0x00000000, Ownership: common.Acpi},
 			Macro: test.Macro{
 				Short: "PAD_CFG_GPO(GPD1, 0, PWROK),",
 				Long:  "_PAD_CFG_STRUCT(GPD1, PAD_FUNC(GPIO) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), 0),",
 			},
 		},
 		{ /* GPD2 - LAN_WAKE# */
-			Pad: test.Pad{ID: "GPD2", DW0: 0x00080602, DW1: 0x00003c00, Ownership: 0},
+			Pad: test.Pad{ID: "GPD2", DW0: 0x00080602, DW1: 0x00003c00, Ownership: common.Acpi},
 			Macro: test.Macro{
 				Short: "PAD_CFG_NF(GPD2, NATIVE, PWROK, NF1),",
 				Long:  "_PAD_CFG_STRUCT(GPD2, PAD_FUNC(NF1) | PAD_IRQ_ROUTE(SCI) | PAD_BUF(RX_DISABLE) | (1 << 1), PAD_PULL(NATIVE)),",
 			},
 		},
 		{ /* GPD3 - PWRBTN# */
-			Pad: test.Pad{ID: "GPD3", DW0: 0x04000502, DW1: 0x00003000, Ownership: 0},
+			Pad: test.Pad{ID: "GPD3", DW0: 0x04000502, DW1: 0x00003000, Ownership: common.Acpi},
 			Macro: test.Macro{
 				Short: "PAD_CFG_NF(GPD3, UP_20K, PWROK, NF1),",
 				Long:  "_PAD_CFG_STRUCT(GPD3, PAD_FUNC(NF1) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), PAD_PULL(UP_20K)),",
 			},
 		},
 		{ /* GPD7 - GPIO */
-			Pad: test.Pad{ID: "GPD7", DW0: 0x84000103, DW1: 0x00000000, Ownership: 0},
+			Pad: test.Pad{ID: "GPD7", DW0: 0x84000103, DW1: 0x00000000, Ownership: common.Acpi},
 			Macro: test.Macro{
 				Short: "PAD_CFG_GPI_TRIG_OWN(GPD7, NONE, PLTRST, OFF, ACPI),",
 				Long:  "_PAD_CFG_STRUCT(GPD7, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1) | 1, 0),",
 			},
 		},
 		{ /* GPP_I1 - DDPC_HPD1 */
-			Pad: test.Pad{ID: "GPP_I1", DW0: 0x84000502, DW1: 0x00000000, Ownership: 0},
+			Pad: test.Pad{ID: "GPP_I1", DW0: 0x84000502, DW1: 0x00000000, Ownership: common.Acpi},
 			Macro: test.Macro{
 				Short: "PAD_CFG_NF(GPP_I1, NONE, PLTRST, NF1),",
 				Long:  "_PAD_CFG_STRUCT(GPP_I1, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0),",
 			},
 		},
 		{ /* GPP_I8 - DDPC_CTRLDATA */
-			Pad: test.Pad{ID: "GPP_I8", DW0: 0x84000500, DW1: 0x00001000, Ownership: 0},
+			Pad: test.Pad{ID: "GPP_I8", DW0: 0x84000500, DW1: 0x00001000, Ownership: common.Acpi},
 			Macro: test.Macro{
 				Short: "PAD_CFG_NF(GPP_I8, DN_20K, PLTRST, NF1),",
 				Long:  "_PAD_CFG_STRUCT(GPP_I8, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), PAD_PULL(DN_20K)),",
 			},
 		},
-	}.Run(t, "INTEL-SUNRISE-PCH/PAD-MAP", sunrise)
+	}.Run(t, "INTEL-SUNRISE-PCH/PAD-MAP")
 
 	test.Suite{
 		{
-			Pad: test.Pad{ID: "GPP_Axx", DW0: 0xBFFFFFFF, DW1: 0xFFFFFFFF, Ownership: 1},
+			Pad: test.Pad{ID: "GPP_Axx", DW0: 0xBFFFFFFF, DW1: 0xFFFFFFFF, Ownership: common.Driver},
 			Macro: test.Macro{
 				Short: "PAD_CFG_NF_1V8(GPP_Axx, NATIVE, PLTRST, NF7),",
 				Long:  "_PAD_CFG_STRUCT(GPP_Axx, PAD_FUNC(NF7) | PAD_RESET(PLTRST) | PAD_TRIG(EDGE_BOTH) | PAD_IRQ_ROUTE(IOAPIC) | PAD_IRQ_ROUTE(SCI) | PAD_IRQ_ROUTE(SMI) | PAD_IRQ_ROUTE(NMI) | PAD_RX_POL(INVERT) | PAD_BUF(TX_RX_DISABLE) | (1 << 29) | (1 << 28) | (1 << 1) | 1, PAD_CFG1_TOL_1V8PAD_PULL(NATIVE) | PAD_IOSSTATE(IGNORE) | PAD_IOSTERM(ENPU) | PAD_CFG_OWN_GPIO(DRIVER)),",
 			},
 		},
-	}.Run(t, "INTEL-SUNRISE-PCH/MASK", sunrise)
+	}.Run(t, "INTEL-SUNRISE-PCH/MASK")
 
 	test.Suite{
 		{
-			Pad: test.Pad{ID: "GPP_Bxx", DW0: 0x00000000, DW1: 0x00000000, Ownership: 0},
+			Pad: test.Pad{ID: "GPP_Bxx", DW0: 0x00000000, DW1: 0x00000000, Ownership: common.Acpi},
 			Macro: test.Macro{
 				Short: "PAD_CFG_GPIO_BIDIRECT(GPP_Bxx, 0, NONE, RSMRST, LEVEL, ACPI),",
 				Long:  "_PAD_CFG_STRUCT(GPP_Bxx, PAD_FUNC(GPIO) | PAD_RESET(RSMRST), 0),",
 			},
 		},
-	}.Run(t, "INTEL-SUNRISE-PCH/EMRTY", sunrise)
+	}.Run(t, "INTEL-SUNRISE-PCH/EMRTY")
 }
diff --git a/util/intelp2m/platforms/snr/template.go b/util/intelp2m/platforms/snr/template.go
index 4d02743463..22f477e62c 100644
--- a/util/intelp2m/platforms/snr/template.go
+++ b/util/intelp2m/platforms/snr/template.go
@@ -2,14 +2,11 @@ package snr
 
 import "review.coreboot.org/coreboot.git/util/intelp2m/platforms/common"
 
-// Group: "GPP_A", "GPP_B", "GPP_F", "GPP_C", "GPP_D", "GPP_E", "GPD", "GPP_I", "GPP_J",
-//        "GPP_K", "GPP_G", "GPP_H", "GPP_L"
-
-// KeywordCheck - This function is used to filter parsed lines of the configuration file and
-// returns true if the keyword is contained in the line.
-// line : string from the configuration file
-// Returns false if no word was found, or true otherwise
-func (PlatformSpecific) KeywordCheck(line string) bool {
+// CheckKeyword() parses lines of the configuration file and returns true if the keyword is
+// contained in the line
+// "GPP_A", "GPP_B", "GPP_F", "GPP_C", "GPP_D", "GPP_E", "GPD", "GPP_I", "GPP_J",
+// "GPP_K", "GPP_G", "GPP_H", "GPP_L"
+func CheckKeyword(line string) bool {
 	included, _ := common.KeywordsCheck(line, "GPP_", "GPD")
 	return included
 }
diff --git a/util/intelp2m/platforms/test/suite.go b/util/intelp2m/platforms/test/suite.go
index 0b5074a0d9..aa14d04677 100644
--- a/util/intelp2m/platforms/test/suite.go
+++ b/util/intelp2m/platforms/test/suite.go
@@ -5,6 +5,9 @@ import (
 	"testing"
 
 	"review.coreboot.org/coreboot.git/util/intelp2m/config/p2m"
+	"review.coreboot.org/coreboot.git/util/intelp2m/fields"
+	"review.coreboot.org/coreboot.git/util/intelp2m/platforms"
+	"review.coreboot.org/coreboot.git/util/intelp2m/platforms/common"
 )
 
 type (
@@ -12,7 +15,7 @@ type (
 		ID        string
 		DW0       uint32
 		DW1       uint32
-		Ownership uint8
+		Ownership bool
 	}
 	Macro struct {
 		Short string
@@ -22,43 +25,60 @@ type (
 		Pad
 		Macro
 	}
-	PlatformSpecificIf interface {
-		GenMacro(string, uint32, uint32, uint8) string
-	}
 	Suite []TestCase
 )
 
-func (p Pad) toShortMacro(platform PlatformSpecificIf) string {
+func (p Pad) toShortMacro() string {
 	if err := p2m.SetFieldType("none"); err != nil {
 		panic(err)
 	}
 	p2m.Config.AutoCheck = false
-	return platform.GenMacro(p.ID, p.DW0, p.DW1, p.Ownership)
+	constructor, err := platforms.GetConstructor()
+	if err != nil {
+		panic(err)
+	}
+	macro := common.CreateFrom(
+		p.ID,
+		p.Ownership,
+		constructor(p.DW0, p.DW1),
+		fields.Get(),
+	)
+	return macro.Generate()
 }
 
-func (p Pad) toLongMacro(platform PlatformSpecificIf) string {
+func (p Pad) toLongMacro() string {
 	if err := p2m.SetFieldType("cb"); err != nil {
 		panic(err)
 	}
 	p2m.Config.AutoCheck = true
-	return platform.GenMacro(p.ID, p.DW0, p.DW1, p.Ownership)
+	constructor, err := platforms.GetConstructor()
+	if err != nil {
+		panic(err)
+	}
+	macro := common.CreateFrom(
+		p.ID,
+		p.Ownership,
+		constructor(p.DW0, p.DW1),
+		fields.Get(),
+	)
+	return macro.Generate()
 }
 
-func (m *Macro) checkFor(platform PlatformSpecificIf, pad Pad) error {
+func (m *Macro) check(pad Pad) error {
 	var format string = "%s macro\nExpects:  '%s'\nActually: '%s'\n\n"
-	if actually := pad.toLongMacro(platform); m.Long != "" && m.Long != actually {
+	if actually := pad.toLongMacro(); m.Long != "" && m.Long != actually {
 		return fmt.Errorf(format, "LONG", m.Long, actually)
 	}
-	if actually := pad.toShortMacro(platform); m.Short != "" && m.Short != actually {
+	if actually := pad.toShortMacro(); m.Short != "" && m.Short != actually {
 		return fmt.Errorf(format, "SHORT", m.Short, actually)
 	}
 	return nil
 }
 
-func (suite Suite) Run(t *testing.T, label string, platform PlatformSpecificIf) {
+func (suite Suite) Run(t *testing.T, label string) {
 	t.Run(label, func(t *testing.T) {
 		for _, testcase := range suite {
-			if err := testcase.Macro.checkFor(platform, testcase.Pad); err != nil {
+			if err := testcase.Macro.check(testcase.Pad); err != nil {
 				t.Errorf("Test failed for pad %s\n%v", testcase.Pad.ID, err)
 			}
 		}
diff --git a/util/intelp2m/platforms/tgl/macro.go b/util/intelp2m/platforms/tgl/macro.go
index fdd324fcdd..64ed9bb579 100644
--- a/util/intelp2m/platforms/tgl/macro.go
+++ b/util/intelp2m/platforms/tgl/macro.go
@@ -1,113 +1,56 @@
 package tgl
 
 import (
-	"fmt"
 	"strings"
 
-	"review.coreboot.org/coreboot.git/util/intelp2m/fields"
+	"review.coreboot.org/coreboot.git/util/intelp2m/logs"
 	"review.coreboot.org/coreboot.git/util/intelp2m/platforms/cnl"
 	"review.coreboot.org/coreboot.git/util/intelp2m/platforms/common"
 	"review.coreboot.org/coreboot.git/util/intelp2m/platforms/common/register/bits"
-	"review.coreboot.org/coreboot.git/util/intelp2m/platforms/snr"
 )
 
 const (
-	PAD_CFG_DW0_RO_FIELDS = (0x1 << 27) | (0x1 << 24) | (0x3 << 21) | (0xf << 16) | 0xfc
-	PAD_CFG_DW1_RO_FIELDS = 0xfdffc3ff
+	DW0Mask = (0b1 << 27) | (0b1 << 24) | (0b11 << 21) | (0b1111 << 16) | 0b11111100
+	DW1Mask = 0b11111101111111111100001111111111
 )
 
-type InheritanceMacro interface {
-	Pull()
-	GpiMacroAdd()
-	GpoMacroAdd()
-	NativeFunctionMacroAdd()
-	NoConnMacroAdd()
+type BasePlatform struct {
+	// based on the Cannon Lake platform
+	cnl.BasePlatform
 }
 
-type PlatformSpecific struct {
-	InheritanceMacro
+func InitBasePlatform(dw0, dw0mask uint32, dw1, dw1mask uint32) BasePlatform {
+	return BasePlatform{cnl.InitBasePlatform(dw0, dw0mask, dw1, dw1mask)}
 }
 
-// RemmapRstSrc - remmap Pad Reset Source Config
-func (PlatformSpecific) RemmapRstSrc() {
-	macro := common.GetMacro()
-	if strings.Contains(macro.PadIdGet(), "GPD") {
+func GetPlatform(dw0, dw1 uint32) common.PlatformIf {
+	p := InitBasePlatform(dw0, DW0Mask, dw1, DW1Mask)
+	return &p
+}
+
+// Override BasePlatform.RemapRstSrc()
+func (p *BasePlatform) RemapRstSrc(m *common.Macro) {
+	if strings.Contains(m.GetPadId(), "GPD") {
 		// See reset map for the TigerLake Community 2:
 		// https://github.com/coreboot/coreboot/blob/master/src/soc/intel/tigerlake/gpio.c#L21
 		// remmap is not required because it is the same as common.
 		return
 	}
 
-	dw0 := macro.GetRegisterDW0()
-	var remapping = map[uint32]uint32{
-		0: bits.RstCfgRSMRST << bits.DW0PadRstCfg,
-		1: bits.RstCfgDEEP << bits.DW0PadRstCfg,
-		2: bits.RstCfgPLTRST << bits.DW0PadRstCfg,
+	remapping := map[uint32]uint32{
+		0b00: bits.RstCfgRSMRST << bits.DW0PadRstCfg,
+		0b01: bits.RstCfgDEEP << bits.DW0PadRstCfg,
+		0b10: bits.RstCfgPLTRST << bits.DW0PadRstCfg,
 	}
-	resetsrc, valid := remapping[dw0.GetResetConfig()]
+	dw0 := p.GetRegisterDW0()
+	source, valid := remapping[dw0.GetResetConfig()]
 	if valid {
-		// dw0.SetResetConfig(resetsrc)
-		ResetConfigFieldVal := (dw0.Value & 0x3fffffff) | remapping[dw0.GetResetConfig()]
-		dw0.Value = ResetConfigFieldVal
+		dw0.Value &= 0x3fffffff
+		dw0.Value |= source
 	} else {
-		fmt.Println("Invalid Pad Reset Config [ 0x", resetsrc, " ] for ", macro.PadIdGet())
+		logs.Errorf("%s: skip re-mapping: DW0 %s: invalid reset config source value 0b%b",
+			m.GetPadId(), dw0, dw0.GetResetConfig())
 	}
 	mask := bits.DW0[bits.DW0PadRstCfg]
 	dw0.CntrMaskFieldsClear(mask)
 }
-
-// Adds The Pad Termination (TERM) parameter from PAD_CFG_DW1 to the macro
-// as a new argument
-func (platform PlatformSpecific) Pull() {
-	platform.InheritanceMacro.Pull()
-}
-
-// Adds PAD_CFG_GPI macro with arguments
-func (platform PlatformSpecific) GpiMacroAdd() {
-	platform.InheritanceMacro.GpiMacroAdd()
-}
-
-// Adds PAD_CFG_GPO macro with arguments
-func (platform PlatformSpecific) GpoMacroAdd() {
-	platform.InheritanceMacro.GpoMacroAdd()
-}
-
-// Adds PAD_CFG_NF macro with arguments
-func (platform PlatformSpecific) NativeFunctionMacroAdd() {
-	platform.InheritanceMacro.NativeFunctionMacroAdd()
-}
-
-// Adds PAD_NC macro
-func (platform PlatformSpecific) NoConnMacroAdd() {
-	platform.InheritanceMacro.NoConnMacroAdd()
-}
-
-// GenMacro - generate pad macro
-// dw0 : DW0 config register value
-// dw1 : DW1 config register value
-// return: string of macro
-func (PlatformSpecific) GenMacro(id string, dw0Val, dw1Val uint32, ownership uint8) string {
-	macro := common.GetInstanceMacro(
-		PlatformSpecific{
-			InheritanceMacro: cnl.PlatformSpecific{
-				InheritanceMacro: snr.PlatformSpecific{},
-			},
-		},
-		fields.InterfaceGet(),
-	)
-	macro.Clear()
-
-	dw0 := macro.GetRegisterDW0()
-	dw0.CntrMaskFieldsClear(bits.All32)
-
-	dw1 := macro.GetRegisterDW1()
-	dw1.CntrMaskFieldsClear(bits.All32)
-
-	dw0.Value = dw0Val
-	dw1.Value = dw1Val
-	dw0.ReadOnly = PAD_CFG_DW0_RO_FIELDS
-	dw1.ReadOnly = PAD_CFG_DW1_RO_FIELDS
-
-	macro.PadIdSet(id).SetPadOwnership(ownership)
-	return macro.Generate()
-}
diff --git a/util/intelp2m/platforms/tgl/template.go b/util/intelp2m/platforms/tgl/template.go
index 4e9a2ba069..f6a0bcd4d0 100644
--- a/util/intelp2m/platforms/tgl/template.go
+++ b/util/intelp2m/platforms/tgl/template.go
@@ -5,10 +5,10 @@ import "review.coreboot.org/coreboot.git/util/intelp2m/platforms/common"
 // Group : "GPP_A", "GPP_R", "GPP_B", "GPP_D", "GPP_C", "GPP_S", "GPP_G", "GPD", "GPP_E",
 //         "GPP_F", "GPP_H", "GPP_J", "GPP_K", "GPP_I", "VGPIO_USB", "VGPIO_PCIE"
 
-// KeywordCheck - This function is used to filter parsed lines of the configuration file
+// CheckKeyword - This function is used to filter parsed lines of the configuration file
 // and returns true if the keyword is contained in the line.
 // line : string from the configuration file
-func (PlatformSpecific) KeywordCheck(line string) bool {
+func CheckKeyword(line string) bool {
 	isIncluded, _ := common.KeywordsCheck(line, "GPP_", "GPD", "VGPIO")
 	return isIncluded
 }
diff --git a/util/intelp2m/platforms/tgl/tgl_test.go b/util/intelp2m/platforms/tgl/tgl_test.go
index a968f96fab..e61f43d80e 100644
--- a/util/intelp2m/platforms/tgl/tgl_test.go
+++ b/util/intelp2m/platforms/tgl/tgl_test.go
@@ -3,108 +3,107 @@ package tgl_test
 import (
 	"testing"
 
-	"review.coreboot.org/coreboot.git/util/intelp2m/platforms/cnl"
-	"review.coreboot.org/coreboot.git/util/intelp2m/platforms/snr"
+	"review.coreboot.org/coreboot.git/util/intelp2m/config/p2m"
+	"review.coreboot.org/coreboot.git/util/intelp2m/platforms/common"
 	"review.coreboot.org/coreboot.git/util/intelp2m/platforms/test"
-	"review.coreboot.org/coreboot.git/util/intelp2m/platforms/tgl"
 )
 
 func TestGenMacro(t *testing.T) {
-	tigerlake := tgl.PlatformSpecific{
-		InheritanceMacro: cnl.PlatformSpecific{
-			InheritanceMacro: snr.PlatformSpecific{},
-		},
-	}
+	p2m.Config.Platform = p2m.Tiger
 	test.Suite{
 		{
-			Pad: test.Pad{ID: "GPP_A1", DW0: 0x11111111, DW1: 0x11111111, Ownership: 1},
+			Pad: test.Pad{ID: "GPP_A1", DW0: 0x11111111, DW1: 0x11111111, Ownership: common.Driver},
 			Macro: test.Macro{
 				Short: "PAD_CFG_NF(GPP_A1, DN_20K, RSMRST, NF4),",
 				Long:  "_PAD_CFG_STRUCT(GPP_A1, PAD_FUNC(NF4) | PAD_RESET(RSMRST) | PAD_IRQ_ROUTE(IOAPIC) | PAD_BUF(TX_DISABLE) | (1 << 28) | 1, PAD_PULL(DN_20K) | PAD_IOSSTATE(Tx1RxDCRx1) | PAD_IOSTERM(DISPUPD) | PAD_CFG_OWN_GPIO(DRIVER)),",
 			},
 		},
 		{
-			Pad: test.Pad{ID: "GPP_R2", DW0: 0x22222222, DW1: 0x22222222, Ownership: 0},
+			Pad: test.Pad{ID: "GPP_R2", DW0: 0x22222222, DW1: 0x22222222, Ownership: common.Acpi},
 			Macro: test.Macro{
 				Short: "PAD_CFG_TERM_GPO(GPP_R2, 0, INVALID, RSMRST),",
 				Long:  "_PAD_CFG_STRUCT(GPP_R2, PAD_FUNC(GPIO) | PAD_RESET(RSMRST) | PAD_TRIG(EDGE_SINGLE) | PAD_IRQ_ROUTE(NMI) | PAD_BUF(RX_DISABLE) | (1 << 29) | (1 << 1), PAD_CFG1_TOL_1V8PAD_PULL(INVALID) | PAD_IOSSTATE(HIZCRx1) | PAD_IOSTERM(ENPD)),",
 			},
 		},
 		{
-			Pad: test.Pad{ID: "GPP_B3", DW0: 0x44444444, DW1: 0x44444444, Ownership: 1},
+			Pad: test.Pad{ID: "GPP_B3", DW0: 0x44444444, DW1: 0x44444444, Ownership: common.Driver},
 			Macro: test.Macro{
 				Short: "PAD_CFG_NF(GPP_B3, INVALID, DEEP, NF1),",
 				Long:  "_PAD_CFG_STRUCT(GPP_B3, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_IRQ_ROUTE(SMI), PAD_PULL(INVALID) | PAD_IOSSTATE(Tx0RxDCRx0) | PAD_CFG_OWN_GPIO(DRIVER)),",
 			},
 		},
 		{
-			Pad: test.Pad{ID: "GPP_D4", DW0: 0x88888888, DW1: 0x88888888, Ownership: 0},
+			Pad: test.Pad{ID: "GPP_D4", DW0: 0x88888888, DW1: 0x88888888, Ownership: common.Acpi},
 			Macro: test.Macro{
 				Short: "PAD_CFG_NF(GPP_D4, DN_5K, PLTRST, NF2),",
 				Long:  "_PAD_CFG_STRUCT(GPP_D4, PAD_FUNC(NF2) | PAD_RESET(PLTRST) | PAD_IRQ_ROUTE(SCI) | PAD_RX_POL(INVERT), PAD_PULL(DN_5K) | PAD_IOSSTATE(Tx0RxDCRx1)),",
 			},
 		},
-	}.Run(t, "INTEL-TIGER-LAKE-PCH/SLIDING-ONE-IN-NIBBLE-TEST", tigerlake)
+	}.Run(t, "INTEL-TIGER-LAKE-PCH/SLIDING-ONE-IN-NIBBLE-TEST")
 
 	test.Suite{
 		{
-			Pad: test.Pad{ID: "GPP_C5", DW0: 0xEEEEEEEE, DW1: 0xEEEEEEEE, Ownership: 1},
+
+			Pad: test.Pad{ID: "GPP_C5", DW0: 0xEEEEEEEE, DW1: 0xEEEEEEEE, Ownership: common.Driver},
 			Macro: test.Macro{
 				Short: "PAD_CFG_NF_1V8(GPP_C5, UP_2K, RSMRST, NF3),",
 				Long:  "_PAD_CFG_STRUCT(GPP_C5, PAD_FUNC(NF3) | PAD_RESET(RSMRST) | PAD_TRIG(EDGE_BOTH) | PAD_IRQ_ROUTE(SCI) | PAD_IRQ_ROUTE(SMI) | PAD_IRQ_ROUTE(NMI) | PAD_RX_POL(INVERT) | PAD_BUF(RX_DISABLE) | (1 << 29) | (1 << 1), PAD_CFG1_TOL_1V8PAD_PULL(UP_2K) | PAD_IOSSTATE(ERROR) | PAD_IOSTERM(ENPD) | PAD_CFG_OWN_GPIO(DRIVER)),",
 			},
 		},
 		{
-			Pad: test.Pad{ID: "GPP_S6", DW0: 0xDDDDDDDD, DW1: 0xDDDDDDDD, Ownership: 0},
+			Pad: test.Pad{ID: "GPP_S6", DW0: 0xDDDDDDDD, DW1: 0xDDDDDDDD, Ownership: common.Acpi},
+
 			Macro: test.Macro{
 				Short: "PAD_CFG_NF(GPP_S6, INVALID, RSMRST, NF7),",
 				Long:  "_PAD_CFG_STRUCT(GPP_S6, PAD_FUNC(NF7) | PAD_RESET(RSMRST) | PAD_TRIG(OFF) | PAD_IRQ_ROUTE(IOAPIC) | PAD_IRQ_ROUTE(SCI) | PAD_IRQ_ROUTE(SMI) | PAD_RX_POL(INVERT) | PAD_BUF(TX_DISABLE) | (1 << 28) | 1, PAD_PULL(INVALID) | PAD_IOSSTATE(HIZCRx0) | PAD_IOSTERM(DISPUPD)),",
 			},
 		},
 		{
-			Pad: test.Pad{ID: "GPP_G7", DW0: 0xBBBBBBBB, DW1: 0xBBBBBBBB, Ownership: 1},
+			Pad: test.Pad{ID: "GPP_G7", DW0: 0xBBBBBBBB, DW1: 0xBBBBBBBB, Ownership: common.Driver},
 			Macro: test.Macro{
 				Short: "PAD_CFG_NF_1V8(GPP_G7, INVALID, PLTRST, NF6),",
 				Long:  "_PAD_CFG_STRUCT(GPP_G7, PAD_FUNC(NF6) | PAD_RESET(PLTRST) | PAD_TRIG(EDGE_SINGLE) | PAD_IRQ_ROUTE(IOAPIC) | PAD_IRQ_ROUTE(SCI) | PAD_IRQ_ROUTE(NMI) | PAD_RX_POL(INVERT) | PAD_BUF(TX_RX_DISABLE) | (1 << 29) | (1 << 28) | (1 << 1) | 1, PAD_CFG1_TOL_1V8PAD_PULL(INVALID) | PAD_IOSSTATE(ERROR) | PAD_IOSTERM(ENPU) | PAD_CFG_OWN_GPIO(DRIVER)),",
 			},
 		},
 		{
-			Pad: test.Pad{ID: "GPD8", DW0: 0x77777777, DW1: 0x77777777, Ownership: 0},
+
+			Pad: test.Pad{ID: "GPD8", DW0: 0x77777777, DW1: 0x77777777, Ownership: common.Acpi},
+
 			Macro: test.Macro{
 				Short: "PAD_CFG_NF_1V8(GPD8, UP_667, DEEP, NF5),",
 				Long:  "_PAD_CFG_STRUCT(GPD8, PAD_FUNC(NF5) | PAD_RESET(DEEP) | PAD_TRIG(EDGE_BOTH) | PAD_IRQ_ROUTE(IOAPIC) | PAD_IRQ_ROUTE(SMI) | PAD_IRQ_ROUTE(NMI) | PAD_BUF(TX_RX_DISABLE) | (1 << 29) | (1 << 28) | (1 << 1) | 1, PAD_CFG1_TOL_1V8PAD_PULL(UP_667) | PAD_IOSSTATE(ERROR) | PAD_IOSTERM(ENPU)),",
 			},
 		},
-	}.Run(t, "INTEL-TIGER-LAKE-PCH/SLIDING-ZERO-IN-NIBBLE-TEST", tigerlake)
+	}.Run(t, "INTEL-TIGER-LAKE-PCH/SLIDING-ZERO-IN-NIBBLE-TEST")
 
 	test.Suite{
 		{
-			Pad: test.Pad{ID: "GPP_E9", DW0: 0x33333333, DW1: 0x33333333, Ownership: 1},
+			Pad: test.Pad{ID: "GPP_E9", DW0: 0x33333333, DW1: 0x33333333, Ownership: common.Driver},
 			Macro: test.Macro{
 				Short: "PAD_CFG_NF_1V8(GPP_E9, UP_20K, RSMRST, NF4),",
 				Long:  "_PAD_CFG_STRUCT(GPP_E9, PAD_FUNC(NF4) | PAD_RESET(RSMRST) | PAD_TRIG(EDGE_SINGLE) | PAD_IRQ_ROUTE(IOAPIC) | PAD_IRQ_ROUTE(NMI) | PAD_BUF(TX_RX_DISABLE) | (1 << 29) | (1 << 28) | (1 << 1) | 1, PAD_CFG1_TOL_1V8PAD_PULL(UP_20K) | PAD_IOSSTATE(ERROR) | PAD_IOSTERM(ENPU) | PAD_CFG_OWN_GPIO(DRIVER)),",
 			},
 		},
 		{
-			Pad: test.Pad{ID: "GPP_F10", DW0: 0x66666666, DW1: 0x66666666, Ownership: 0},
+			Pad: test.Pad{ID: "GPP_F10", DW0: 0x66666666, DW1: 0x66666666, Ownership: common.Acpi},
 			Macro: test.Macro{
 				Short: "PAD_CFG_NF_1V8(GPP_F10, UP_1K, DEEP, NF1),",
 				Long:  "_PAD_CFG_STRUCT(GPP_F10, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(EDGE_BOTH) | PAD_IRQ_ROUTE(SMI) | PAD_IRQ_ROUTE(NMI) | PAD_BUF(RX_DISABLE) | (1 << 29) | (1 << 1), PAD_CFG1_TOL_1V8PAD_PULL(UP_1K) | PAD_IOSSTATE(TxDRxE) | PAD_IOSTERM(ENPD)),",
 			},
 		},
 		{
-			Pad: test.Pad{ID: "GPP_H11", DW0: 0xCCCCCCCC, DW1: 0xCCCCCCCC, Ownership: 1},
+			Pad: test.Pad{ID: "GPP_H11", DW0: 0xCCCCCCCC, DW1: 0xCCCCCCCC, Ownership: common.Driver},
 			Macro: test.Macro{
 				Short: "PAD_CFG_NF(GPP_H11, INVALID, RSMRST, NF3),",
 				Long:  "_PAD_CFG_STRUCT(GPP_H11, PAD_FUNC(NF3) | PAD_RESET(RSMRST) | PAD_TRIG(OFF) | PAD_IRQ_ROUTE(SCI) | PAD_IRQ_ROUTE(SMI) | PAD_RX_POL(INVERT), PAD_PULL(INVALID) | PAD_IOSSTATE(Tx1RxDCRx0) | PAD_CFG_OWN_GPIO(DRIVER)),",
 			},
 		},
 		{
-			Pad: test.Pad{ID: "GPP_J12", DW0: 0x99999999, DW1: 0x99999999, Ownership: 0},
+			Pad: test.Pad{ID: "GPP_J12", DW0: 0x99999999, DW1: 0x99999999, Ownership: common.Acpi},
 			Macro: test.Macro{
 				Short: "PAD_CFG_NF(GPP_J12, INVALID, PLTRST, NF6),",
 				Long:  "_PAD_CFG_STRUCT(GPP_J12, PAD_FUNC(NF6) | PAD_RESET(PLTRST) | PAD_IRQ_ROUTE(IOAPIC) | PAD_IRQ_ROUTE(SCI) | PAD_RX_POL(INVERT) | PAD_BUF(TX_DISABLE) | (1 << 28) | 1, PAD_PULL(INVALID) | PAD_IOSSTATE(Tx1RxE) | PAD_IOSTERM(DISPUPD)),",
 			},
 		},
-	}.Run(t, "INTEL-TIGER-LAKE-PCH/SLIDING-ONE-ONE-IN-NIBBLE-TEST", tigerlake)
+	}.Run(t, "INTEL-TIGER-LAKE-PCH/SLIDING-ONE-ONE-IN-NIBBLE-TEST")
 }

From d9c3e51a818abc49e1dafc115759984bbad26545 Mon Sep 17 00:00:00 2001
From: Maxim Polyakov <max.senia.poliak@gmail.com>
Date: Mon, 16 Dec 2024 17:19:15 +0300
Subject: [PATCH 0256/3886] util/intelp2m/platforms/cnl: Add missing VGPIO
 groups

Change-Id: Ib7c807c343c71e8420feaa481b7f0536a5f36533
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85608
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
---
 util/intelp2m/platforms/cnl/template.go | 22 ++++++++++++++++++----
 1 file changed, 18 insertions(+), 4 deletions(-)

diff --git a/util/intelp2m/platforms/cnl/template.go b/util/intelp2m/platforms/cnl/template.go
index 4c4192d6cc..f1bb525a6d 100644
--- a/util/intelp2m/platforms/cnl/template.go
+++ b/util/intelp2m/platforms/cnl/template.go
@@ -2,10 +2,24 @@ package cnl
 
 import "review.coreboot.org/coreboot.git/util/intelp2m/platforms/common"
 
-// CheckKeyword() parses lines of the configuration file and returns true if the keyword is
-// contained in the line
-// "GPP_A", "GPP_B", "GPP_G", "GPP_D", "GPP_F", "GPP_H", "GPD", "GPP_C", "GPP_E"
 func CheckKeyword(line string) bool {
-	included, _ := common.KeywordsCheck(line, "GPP_", "GPD")
+	// "GPP_" : "GPP_A", "GPP_B", "GPP_G", "GPP_D", "GPP_F", "GPP_H", "GPP_C", "GPP_E"
+	included, _ := common.KeywordsCheck(line, "GPP_", "GPD",
+		"I2S1_TXD", "CNV_BTEN", "CNV_GNEN", "CNV_WFEN", "CNV_WCEN", "vCNV_GNSS_HOST_WAKE_B",
+		"vSD3_CD_B", "CNV_BT_HOST_WAKE_B", "CNV_BT_IF_SELECT", "vCNV_BT_UART_TXD",
+		"vCNV_BT_UART_RXD", "vCNV_BT_UART_CTS_B", "vCNV_BT_UART_RTS_B", "vCNV_MFUART1_TXD",
+		"vCNV_MFUART1_RXD", "vCNV_MFUART1_CTS_B", "vCNV_MFUART1_RTS_B", "vCNV_GNSS_UART_TXD",
+		"vCNV_GNSS_UART_RXD", "vCNV_GNSS_UART_CTS_B", "vCNV_GNSS_UART_RTS_B", "vUART0_TXD",
+		"vUART0_RXD", "vUART0_CTS_B", "vUART0_RTS_B", "vISH_UART0_TXD", "vISH_UART0_RXD",
+		"vISH_UART0_CTS_B", "vISH_UART0_RTS_B", "vISH_UART1_TXD", "vISH_UART1_RXD",
+		"vISH_UART1_CTS_B", "vISH_UART1_RTS_B", "vCNV_BT_I2S_BCLK", "vCNV_BT_I2S_WS_SYNC",
+		"vCNV_BT_I2S_SDO", "vCNV_BT_I2S_SDI", "vSSP2_SCLK", "vSSP2_SFRM", "vSSP2_TXD",
+		"vSSP2_RXD", "SLP_LAN_B", "SLP_SUS_B", "WAKE_B", "DRAM_RESET_B", "SPI0_IO_2",
+		"SPI0_IO_3", "SPI0_MISO", "SPI0_MOSI", "SPI0_CS2_B", "SPI0_CS0_B", "SPI0_CS1_B",
+		"SPI0_CLK", "SPI0_CLK_LOOPBK", "HDACPU_SDI", "HDACPU_SDO", "HDACPU_SCLK", "PM_SYNC",
+		"PECI", "CPUPWRGD", "THRMTRIP_B", "PLTRST_CPU_B", "PM_DOWN", "TRIGGER_IN",
+		"TRIGGER_OUT", "PCH_TDO", "PCH_JTAGX", "PROC_PRDY_B", "PROC_PREQ_B", "CPU_TRST_B",
+		"PCH_TDI", "PCH_TMS", "PCH_TCK", "ITP_PMODE", "SYS_PWROK", "SYS_RESET_B", "CL_RST_B",
+		"HDA_BCLK", "HDA_RST_B", "HDA_SYNC", "HDA_SDO", "HDA_SDI0", "HDA_SDI1", "I2S1_SFRM")
 	return included
 }

From e833b4661d1ec05e34c0232994c0fcdc2d7e895b Mon Sep 17 00:00:00 2001
From: Maxim Polyakov <max.senia.poliak@gmail.com>
Date: Sun, 22 Dec 2024 12:50:47 +0300
Subject: [PATCH 0257/3886] util/intelp2m: Move remapping reset source to
 common

TEST: 'make test' = PASS

Change-Id: I315541b12f5f1fdf7c97c2ff8ddd305e30a447cc
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85731
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
---
 util/intelp2m/platforms/adl/macro.go     | 30 +++++++++---------------
 util/intelp2m/platforms/apl/macro.go     |  4 ++--
 util/intelp2m/platforms/cnl/macro.go     | 28 ++++++++--------------
 util/intelp2m/platforms/common/common.go | 22 +++++++++++++++++
 util/intelp2m/platforms/common/macro.go  |  4 ++--
 util/intelp2m/platforms/ebg/macro.go     | 27 ++++++++-------------
 util/intelp2m/platforms/jsl/macro.go     | 28 ++++++++--------------
 util/intelp2m/platforms/lbg/macro.go     | 28 ++++++++--------------
 util/intelp2m/platforms/mtl/macro.go     | 30 +++++++++---------------
 util/intelp2m/platforms/snr/macro.go     | 25 +++++++-------------
 util/intelp2m/platforms/tgl/macro.go     | 28 ++++++++--------------
 11 files changed, 107 insertions(+), 147 deletions(-)

diff --git a/util/intelp2m/platforms/adl/macro.go b/util/intelp2m/platforms/adl/macro.go
index 19e9bd20e5..63104d0ce8 100644
--- a/util/intelp2m/platforms/adl/macro.go
+++ b/util/intelp2m/platforms/adl/macro.go
@@ -14,6 +14,13 @@ const (
 	DW1Mask uint32 = 0b11111101111111111100001111111111
 )
 
+var remapping = common.ResetSources{
+	0b00: bits.RstCfgRSMRST << bits.DW0PadRstCfg,
+	0b01: bits.RstCfgDEEP << bits.DW0PadRstCfg,
+	0b10: bits.RstCfgPLTRST << bits.DW0PadRstCfg,
+	0b11: bits.RstCfgPWROK << bits.DW0PadRstCfg,
+}
+
 type BasePlatform struct {
 	// based on the Cannon Lake platform
 	cnl.BasePlatform
@@ -28,30 +35,15 @@ func GetPlatform(dw0, dw1 uint32) common.PlatformIf {
 	return &p
 }
 
-// Override BasePlatform.RemapRstSrc()
-func (p *BasePlatform) RemapRstSrc(m *common.Macro) {
+// Override BasePlatform.RemapResetSource()
+func (p *BasePlatform) RemapResetSource(m *common.Macro) {
 	if strings.Contains(m.GetPadId(), "GPD") {
 		// See reset map for the Alderlake GPD Group in the Community 2:
 		// https://github.com/coreboot/coreboot/blob/master/src/soc/intel/alderlake/gpio.c#L21
 		// remmap is not required because it is the same as common.
 		return
 	}
-
-	remapping := map[uint32]uint32{
-		0b00: bits.RstCfgRSMRST << bits.DW0PadRstCfg,
-		0b01: bits.RstCfgDEEP << bits.DW0PadRstCfg,
-		0b10: bits.RstCfgPLTRST << bits.DW0PadRstCfg,
-		0b11: bits.RstCfgPWROK << bits.DW0PadRstCfg,
+	if err := p.UpdateResetSource(remapping); err != nil {
+		logs.Errorf("remap reset source for %s: %v", m.GetPadId(), err)
 	}
-	dw0 := p.GetRegisterDW0()
-	source, valid := remapping[dw0.GetResetConfig()]
-	if valid {
-		dw0.Value &= 0x3fffffff
-		dw0.Value |= source
-	} else {
-		logs.Errorf("%s: skip re-mapping: DW0 %s: invalid reset config source value 0b%b",
-			m.GetPadId(), dw0, dw0.GetResetConfig())
-	}
-	mask := bits.DW0[bits.DW0PadRstCfg]
-	dw0.CntrMaskFieldsClear(mask)
 }
diff --git a/util/intelp2m/platforms/apl/macro.go b/util/intelp2m/platforms/apl/macro.go
index f20acc46a3..614d0bebd6 100644
--- a/util/intelp2m/platforms/apl/macro.go
+++ b/util/intelp2m/platforms/apl/macro.go
@@ -25,8 +25,8 @@ func GetPlatform(dw0, dw1 uint32) common.PlatformIf {
 	return &p
 }
 
-// RemapRstSrc() remaps Pad Reset Source Config
-func (p *BasePlatform) RemapRstSrc(m *common.Macro) {}
+// RemapResetSource() remaps Pad Reset Source Config
+func (p *BasePlatform) RemapResetSource(m *common.Macro) {}
 
 // Pull() adds The Pad Termination (TERM) parameter from PAD_CFG_DW1 to the macro
 func (p *BasePlatform) Pull(m *common.Macro) {
diff --git a/util/intelp2m/platforms/cnl/macro.go b/util/intelp2m/platforms/cnl/macro.go
index 7f5421510c..625df0aa5f 100644
--- a/util/intelp2m/platforms/cnl/macro.go
+++ b/util/intelp2m/platforms/cnl/macro.go
@@ -15,6 +15,12 @@ const (
 	DW1Mask uint32 = 0b11111101111111111100001111111111
 )
 
+var remapping = common.ResetSources{
+	0b00: bits.RstCfgRSMRST << bits.DW0PadRstCfg,
+	0b01: bits.RstCfgDEEP << bits.DW0PadRstCfg,
+	0b10: bits.RstCfgPLTRST << bits.DW0PadRstCfg,
+}
+
 type BasePlatform struct {
 	// based on the Sunrise platform
 	snr.BasePlatform
@@ -29,8 +35,8 @@ func GetPlatform(dw0, dw1 uint32) common.PlatformIf {
 	return &p
 }
 
-// Override BasePlatform.RemapRstSrc()
-func (p *BasePlatform) RemapRstSrc(m *common.Macro) {
+// Override BasePlatform.RemapResetSource()
+func (p *BasePlatform) RemapResetSource(m *common.Macro) {
 	if strings.Contains(m.GetPadId(), "GPP_A") ||
 		strings.Contains(m.GetPadId(), "GPP_B") ||
 		strings.Contains(m.GetPadId(), "GPP_G") {
@@ -39,23 +45,9 @@ func (p *BasePlatform) RemapRstSrc(m *common.Macro) {
 		// remmap is not required because it is the same as common.
 		return
 	}
-
-	dw0 := p.GetRegisterDW0()
-	remapping := map[uint32]uint32{
-		0b00: bits.RstCfgRSMRST << bits.DW0PadRstCfg,
-		0b01: bits.RstCfgDEEP << bits.DW0PadRstCfg,
-		0b10: bits.RstCfgPLTRST << bits.DW0PadRstCfg,
+	if err := p.UpdateResetSource(remapping); err != nil {
+		logs.Errorf("remap reset source for %s: %v", m.GetPadId(), err)
 	}
-	source, valid := remapping[dw0.GetResetConfig()]
-	if valid {
-		dw0.Value &= 0x3fffffff
-		dw0.Value |= source
-	} else {
-		logs.Errorf("%s: skip re-mapping: DW0 %s: invalid reset config source value 0b%b",
-			m.GetPadId(), dw0, dw0.GetResetConfig())
-	}
-	mask := bits.DW0[bits.DW0PadRstCfg]
-	dw0.CntrMaskFieldsClear(mask)
 }
 
 // Override BasePlatform.Pull()
diff --git a/util/intelp2m/platforms/common/common.go b/util/intelp2m/platforms/common/common.go
index 57719842ca..9f4edce7c3 100644
--- a/util/intelp2m/platforms/common/common.go
+++ b/util/intelp2m/platforms/common/common.go
@@ -1,9 +1,14 @@
 package common
 
 import (
+	"fmt"
+
 	"review.coreboot.org/coreboot.git/util/intelp2m/platforms/common/register"
+	"review.coreboot.org/coreboot.git/util/intelp2m/platforms/common/register/bits"
 )
 
+type ResetSources map[uint32]uint32
+
 type BasePlatform struct {
 	dw0 register.DW0
 	dw1 register.DW1
@@ -23,3 +28,20 @@ func (p *BasePlatform) GetRegisterDW0() *register.DW0 {
 func (p *BasePlatform) GetRegisterDW1() *register.DW1 {
 	return &p.dw1
 }
+
+// UpdateResetSource() updates the Pad Reset configuration fields in the DW0 register according
+// to the ResetSources{} map. Redefine this function for the corresponding platform if it has a
+// difference in logic or register bits.
+func (p *BasePlatform) UpdateResetSource(remapping ResetSources) error {
+	dw0 := p.GetRegisterDW0()
+	mask := bits.DW0[bits.DW0PadRstCfg]
+	source, valid := remapping[dw0.GetResetConfig()]
+	if !valid {
+		dw0.CntrMaskFieldsClear(mask)
+		return fmt.Errorf("invalid reset config source value 0b%b", dw0.GetResetConfig())
+	}
+	dw0.Value &= ^mask
+	dw0.Value |= source
+	dw0.CntrMaskFieldsClear(mask)
+	return nil
+}
diff --git a/util/intelp2m/platforms/common/macro.go b/util/intelp2m/platforms/common/macro.go
index 0f544acb08..76e76e81f5 100644
--- a/util/intelp2m/platforms/common/macro.go
+++ b/util/intelp2m/platforms/common/macro.go
@@ -22,7 +22,7 @@ type FieldsIf interface {
 }
 
 type PlatformIf interface {
-	RemapRstSrc(*Macro)
+	RemapResetSource(*Macro)
 	Pull(*Macro)
 	AddGpiMacro(*Macro)
 	AddGpoMacro(*Macro)
@@ -352,7 +352,7 @@ func (m *Macro) Bidirection() {
 
 // Generate() generates string of macro
 func (m *Macro) Generate() string {
-	m.Platform.RemapRstSrc(m)
+	m.Platform.RemapResetSource(m)
 	if dw0 := m.Platform.GetRegisterDW0(); dw0.GetPadMode() == 0 {
 		const txDisable uint32 = 0b01
 		const rxDisable uint32 = 0b10
diff --git a/util/intelp2m/platforms/ebg/macro.go b/util/intelp2m/platforms/ebg/macro.go
index 771d6df6cd..f1a967ece4 100644
--- a/util/intelp2m/platforms/ebg/macro.go
+++ b/util/intelp2m/platforms/ebg/macro.go
@@ -12,6 +12,12 @@ const (
 	DW1Mask = 0b11111101111111111100001111111111
 )
 
+var remapping = common.ResetSources{
+	0b00: bits.RstCfgRSMRST << bits.DW0PadRstCfg,
+	0b01: bits.RstCfgDEEP << bits.DW0PadRstCfg,
+	0b10: bits.RstCfgPLTRST << bits.DW0PadRstCfg,
+}
+
 type BasePlatform struct {
 	// based on the Cannon Lake platform
 	cnl.BasePlatform
@@ -26,22 +32,9 @@ func GetPlatform(dw0, dw1 uint32) common.PlatformIf {
 	return &p
 }
 
-// Override BasePlatform.RemapRstSrc()
-func (p *BasePlatform) RemapRstSrc(m *common.Macro) {
-	remapping := map[uint32]uint32{
-		0b00: bits.RstCfgRSMRST << bits.DW0PadRstCfg,
-		0b01: bits.RstCfgDEEP << bits.DW0PadRstCfg,
-		0b10: bits.RstCfgPLTRST << bits.DW0PadRstCfg,
+// Override BasePlatform.RemapResetSource()
+func (p *BasePlatform) RemapResetSource(m *common.Macro) {
+	if err := p.UpdateResetSource(remapping); err != nil {
+		logs.Errorf("remap reset source for %s: %v", m.GetPadId(), err)
 	}
-	dw0 := p.GetRegisterDW0()
-	source, valid := remapping[dw0.GetResetConfig()]
-	if valid {
-		dw0.Value &= 0x3fffffff
-		dw0.Value |= source
-	} else {
-		logs.Errorf("%s: skip re-mapping: DW0 %s: invalid reset config source value 0b%b",
-			m.GetPadId(), dw0, dw0.GetResetConfig())
-	}
-	mask := bits.DW0[bits.DW0PadRstCfg]
-	dw0.CntrMaskFieldsClear(mask)
 }
diff --git a/util/intelp2m/platforms/jsl/macro.go b/util/intelp2m/platforms/jsl/macro.go
index fa5cbedd7a..92cb66cf33 100644
--- a/util/intelp2m/platforms/jsl/macro.go
+++ b/util/intelp2m/platforms/jsl/macro.go
@@ -14,6 +14,12 @@ const (
 	DW1Mask = 0b11111101111111111100001111111111
 )
 
+var remapping = common.ResetSources{
+	0b00: bits.RstCfgRSMRST << bits.DW0PadRstCfg,
+	0b01: bits.RstCfgDEEP << bits.DW0PadRstCfg,
+	0b10: bits.RstCfgPLTRST << bits.DW0PadRstCfg,
+}
+
 type BasePlatform struct {
 	// based on the Cannon Lake platform
 	cnl.BasePlatform
@@ -28,8 +34,8 @@ func GetPlatform(dw0, dw1 uint32) common.PlatformIf {
 	return &p
 }
 
-// Override the base platform method
-func (p *BasePlatform) RemapRstSrc(m *common.Macro) {
+// Override BasePlatform.RemapResetSource()
+func (p *BasePlatform) RemapResetSource(m *common.Macro) {
 	if strings.Contains(m.GetPadId(), "GPP_F") ||
 		strings.Contains(m.GetPadId(), "GPP_B") ||
 		strings.Contains(m.GetPadId(), "GPP_A") ||
@@ -40,21 +46,7 @@ func (p *BasePlatform) RemapRstSrc(m *common.Macro) {
 		// remmap is not required because it is the same as common.
 		return
 	}
-
-	remapping := map[uint32]uint32{
-		0b00: bits.RstCfgRSMRST << bits.DW0PadRstCfg,
-		0b01: bits.RstCfgDEEP << bits.DW0PadRstCfg,
-		0b10: bits.RstCfgPLTRST << bits.DW0PadRstCfg,
+	if err := p.UpdateResetSource(remapping); err != nil {
+		logs.Errorf("remap reset source for %s: %v", m.GetPadId(), err)
 	}
-	dw0 := p.GetRegisterDW0()
-	source, valid := remapping[dw0.GetResetConfig()]
-	if valid {
-		dw0.Value &= 0x3fffffff
-		dw0.Value |= source
-	} else {
-		logs.Errorf("%s: skip re-mapping: DW0 %s: invalid reset config source value 0b%b",
-			m.GetPadId(), dw0, dw0.GetResetConfig())
-	}
-	mask := bits.DW0[bits.DW0PadRstCfg]
-	dw0.CntrMaskFieldsClear(mask)
 }
diff --git a/util/intelp2m/platforms/lbg/macro.go b/util/intelp2m/platforms/lbg/macro.go
index d1b53501b7..b58c8a956a 100644
--- a/util/intelp2m/platforms/lbg/macro.go
+++ b/util/intelp2m/platforms/lbg/macro.go
@@ -12,6 +12,12 @@ const (
 	DW1Mask uint32 = 0b11111101111111111100001111111111
 )
 
+var remapping = common.ResetSources{
+	0b00: bits.RstCfgRSMRST << bits.DW0PadRstCfg,
+	0b01: bits.RstCfgDEEP << bits.DW0PadRstCfg,
+	0b10: bits.RstCfgPLTRST << bits.DW0PadRstCfg,
+}
+
 type BasePlatform struct {
 	// based on the Sunrise Point platform
 	snr.BasePlatform
@@ -26,23 +32,9 @@ func GetPlatform(dw0, dw1 uint32) common.PlatformIf {
 	return &p
 }
 
-// Override the base platform method
-func (p *BasePlatform) RemapRstSrc(m *common.Macro) {
-	dw0 := p.GetRegisterDW0()
-	remapping := map[uint32]uint32{
-		0b00: bits.RstCfgRSMRST << bits.DW0PadRstCfg,
-		0b01: bits.RstCfgDEEP << bits.DW0PadRstCfg,
-		0b10: bits.RstCfgPLTRST << bits.DW0PadRstCfg,
+// Override BasePlatform.RemapResetSource()
+func (p *BasePlatform) RemapResetSource(m *common.Macro) {
+	if err := p.UpdateResetSource(remapping); err != nil {
+		logs.Errorf("remap reset source for %s: %v", m.GetPadId(), err)
 	}
-	source, valid := remapping[dw0.GetResetConfig()]
-	if valid {
-		// dw0.SetResetConfig(resetsrc)
-		dw0.Value &= 0x3fffffff
-		dw0.Value |= source
-	} else {
-		logs.Errorf("%s: skip re-mapping: DW0 %s: invalid reset config source value 0b%b",
-			m.GetPadId(), dw0, dw0.GetResetConfig())
-	}
-	mask := bits.DW0[bits.DW0PadRstCfg]
-	dw0.CntrMaskFieldsClear(mask)
 }
diff --git a/util/intelp2m/platforms/mtl/macro.go b/util/intelp2m/platforms/mtl/macro.go
index 13a3f11043..8740f5f783 100644
--- a/util/intelp2m/platforms/mtl/macro.go
+++ b/util/intelp2m/platforms/mtl/macro.go
@@ -14,6 +14,13 @@ const (
 	DW1Mask = 0b11111101111111111100001111111111
 )
 
+var remapping = common.ResetSources{
+	0b00: bits.RstCfgRSMRST << bits.DW0PadRstCfg,
+	0b01: bits.RstCfgDEEP << bits.DW0PadRstCfg,
+	0b10: bits.RstCfgPLTRST << bits.DW0PadRstCfg,
+	0b11: bits.RstCfgPWROK << bits.RstCfgPWROK,
+}
+
 type BasePlatform struct {
 	// based on the Cannon Lake platform
 	cnl.BasePlatform
@@ -28,30 +35,15 @@ func GetPlatform(dw0, dw1 uint32) common.PlatformIf {
 	return &p
 }
 
-// Override the base platform method
-func (p *BasePlatform) RemapRstSrc(m *common.Macro) {
+// Override BasePlatform.RemapResetSource()
+func (p *BasePlatform) RemapResetSource(m *common.Macro) {
 	if strings.Contains(m.GetPadId(), "GPD") {
 		// See reset map for the MeteorLake GPD group at
 		// https://github.com/coreboot/coreboot/blob/master/src/soc/intel/meteorlake/gpio.c#L10
 		// remmap is not required because it is the same as common.
 		return
 	}
-
-	remapping := map[uint32]uint32{
-		0b00: bits.RstCfgRSMRST << bits.DW0PadRstCfg,
-		0b01: bits.RstCfgDEEP << bits.DW0PadRstCfg,
-		0b10: bits.RstCfgPLTRST << bits.DW0PadRstCfg,
-		0b11: bits.RstCfgPWROK << bits.RstCfgPWROK,
+	if err := p.UpdateResetSource(remapping); err != nil {
+		logs.Errorf("remap reset source for %s: %v", m.GetPadId(), err)
 	}
-	dw0 := p.GetRegisterDW0()
-	source, valid := remapping[dw0.GetResetConfig()]
-	if valid {
-		dw0.Value &= 0x3fffffff
-		dw0.Value |= source
-	} else {
-		logs.Errorf("%s: skip re-mapping: DW0 %s: invalid reset config source value 0b%b",
-			m.GetPadId(), dw0, dw0.GetResetConfig())
-	}
-	mask := bits.DW0[bits.DW0PadRstCfg]
-	dw0.CntrMaskFieldsClear(mask)
 }
diff --git a/util/intelp2m/platforms/snr/macro.go b/util/intelp2m/platforms/snr/macro.go
index 9a4ace4753..7250608374 100644
--- a/util/intelp2m/platforms/snr/macro.go
+++ b/util/intelp2m/platforms/snr/macro.go
@@ -14,6 +14,12 @@ const (
 	DW1Mask uint32 = 0b11111101111111111100001111111111
 )
 
+var remapping = common.ResetSources{
+	0b00: bits.RstCfgRSMRST << bits.DW0PadRstCfg,
+	0b01: bits.RstCfgDEEP << bits.DW0PadRstCfg,
+	0b10: bits.RstCfgPLTRST << bits.DW0PadRstCfg,
+}
+
 type BasePlatform struct {
 	common.BasePlatform
 }
@@ -28,29 +34,16 @@ func GetPlatform(dw0, dw1 uint32) common.PlatformIf {
 }
 
 // RemmapRstSrc() remaps Pad Reset Source Config
-func (p *BasePlatform) RemapRstSrc(m *common.Macro) {
+func (p *BasePlatform) RemapResetSource(m *common.Macro) {
 	if strings.Contains(m.GetPadId(), "GPD") {
 		// See reset map for the Sunrise GPD Group in the Community 2:
 		// https://github.com/coreboot/coreboot/blob/master/src/soc/intel/skylake/gpio.c#L15
 		// remmap is not required because it is the same as common.
 		return
 	}
-
-	dw0 := p.GetRegisterDW0()
-	remapping := map[uint32]uint32{
-		0b00: bits.RstCfgRSMRST << bits.DW0PadRstCfg,
-		0b01: bits.RstCfgDEEP << bits.DW0PadRstCfg,
-		0b10: bits.RstCfgPLTRST << bits.DW0PadRstCfg,
+	if err := p.UpdateResetSource(remapping); err != nil {
+		logs.Errorf("remap reset source for %s: %v", m.GetPadId(), err)
 	}
-
-	if source, valid := remapping[dw0.GetResetConfig()]; valid {
-		dw0.Value &= 0x3fffffff
-		dw0.Value |= source
-	} else {
-		logs.Errorf("%s: skip re-mapping: DW0 %s: invalid reset config source value 0b%b",
-			m.GetPadId(), dw0, dw0.GetResetConfig())
-	}
-	dw0.CntrMaskFieldsClear(bits.DW0[bits.DW0PadRstCfg])
 }
 
 // Pull() adds The Pad Termination (TERM) parameter from PAD_CFG_DW1 to the macro
diff --git a/util/intelp2m/platforms/tgl/macro.go b/util/intelp2m/platforms/tgl/macro.go
index 64ed9bb579..6e63167b2a 100644
--- a/util/intelp2m/platforms/tgl/macro.go
+++ b/util/intelp2m/platforms/tgl/macro.go
@@ -14,6 +14,12 @@ const (
 	DW1Mask = 0b11111101111111111100001111111111
 )
 
+var remapping = common.ResetSources{
+	0b00: bits.RstCfgRSMRST << bits.DW0PadRstCfg,
+	0b01: bits.RstCfgDEEP << bits.DW0PadRstCfg,
+	0b10: bits.RstCfgPLTRST << bits.DW0PadRstCfg,
+}
+
 type BasePlatform struct {
 	// based on the Cannon Lake platform
 	cnl.BasePlatform
@@ -28,29 +34,15 @@ func GetPlatform(dw0, dw1 uint32) common.PlatformIf {
 	return &p
 }
 
-// Override BasePlatform.RemapRstSrc()
-func (p *BasePlatform) RemapRstSrc(m *common.Macro) {
+// Override BasePlatform.RemapResetSource()
+func (p *BasePlatform) RemapResetSource(m *common.Macro) {
 	if strings.Contains(m.GetPadId(), "GPD") {
 		// See reset map for the TigerLake Community 2:
 		// https://github.com/coreboot/coreboot/blob/master/src/soc/intel/tigerlake/gpio.c#L21
 		// remmap is not required because it is the same as common.
 		return
 	}
-
-	remapping := map[uint32]uint32{
-		0b00: bits.RstCfgRSMRST << bits.DW0PadRstCfg,
-		0b01: bits.RstCfgDEEP << bits.DW0PadRstCfg,
-		0b10: bits.RstCfgPLTRST << bits.DW0PadRstCfg,
+	if err := p.UpdateResetSource(remapping); err != nil {
+		logs.Errorf("remap reset source for %s: %v", m.GetPadId(), err)
 	}
-	dw0 := p.GetRegisterDW0()
-	source, valid := remapping[dw0.GetResetConfig()]
-	if valid {
-		dw0.Value &= 0x3fffffff
-		dw0.Value |= source
-	} else {
-		logs.Errorf("%s: skip re-mapping: DW0 %s: invalid reset config source value 0b%b",
-			m.GetPadId(), dw0, dw0.GetResetConfig())
-	}
-	mask := bits.DW0[bits.DW0PadRstCfg]
-	dw0.CntrMaskFieldsClear(mask)
 }

From 9e50202e4c0beb5f68154c94c76bb6b7a3eb829d Mon Sep 17 00:00:00 2001
From: Maxim Polyakov <max.senia.poliak@gmail.com>
Date: Mon, 23 Dec 2024 19:34:15 +0300
Subject: [PATCH 0258/3886] util/intelp2m: Move fields pakage to common

According to the architecture, this is part of the common block.
TEST: 'make test' = PASS

Change-Id: I6390182ab00d9ebd787e8da6f341e3ef85572991
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71235
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 util/intelp2m/parser/parser.go                              | 2 +-
 util/intelp2m/{ => platforms/common}/fields/cb/cb.go        | 0
 util/intelp2m/{ => platforms/common}/fields/cb/cb_test.go   | 2 +-
 util/intelp2m/{ => platforms/common}/fields/fields.go       | 6 +++---
 util/intelp2m/{ => platforms/common}/fields/fsp/fsp.go      | 0
 util/intelp2m/{ => platforms/common}/fields/fsp/fsp_test.go | 2 +-
 util/intelp2m/{ => platforms/common}/fields/raw/raw.go      | 0
 util/intelp2m/{ => platforms/common}/fields/raw/raw_test.go | 2 +-
 util/intelp2m/{ => platforms/common}/fields/test/suite.go   | 2 +-
 util/intelp2m/platforms/test/suite.go                       | 2 +-
 10 files changed, 9 insertions(+), 9 deletions(-)
 rename util/intelp2m/{ => platforms/common}/fields/cb/cb.go (100%)
 rename util/intelp2m/{ => platforms/common}/fields/cb/cb_test.go (96%)
 rename util/intelp2m/{ => platforms/common}/fields/fields.go (70%)
 rename util/intelp2m/{ => platforms/common}/fields/fsp/fsp.go (100%)
 rename util/intelp2m/{ => platforms/common}/fields/fsp/fsp_test.go (98%)
 rename util/intelp2m/{ => platforms/common}/fields/raw/raw.go (100%)
 rename util/intelp2m/{ => platforms/common}/fields/raw/raw_test.go (95%)
 rename util/intelp2m/{ => platforms/common}/fields/test/suite.go (94%)

diff --git a/util/intelp2m/parser/parser.go b/util/intelp2m/parser/parser.go
index 4575549544..91428f83de 100644
--- a/util/intelp2m/parser/parser.go
+++ b/util/intelp2m/parser/parser.go
@@ -7,11 +7,11 @@ import (
 	"strings"
 
 	"review.coreboot.org/coreboot.git/util/intelp2m/config/p2m"
-	"review.coreboot.org/coreboot.git/util/intelp2m/fields"
 	"review.coreboot.org/coreboot.git/util/intelp2m/logs"
 	"review.coreboot.org/coreboot.git/util/intelp2m/parser/template"
 	"review.coreboot.org/coreboot.git/util/intelp2m/platforms"
 	"review.coreboot.org/coreboot.git/util/intelp2m/platforms/common"
+	"review.coreboot.org/coreboot.git/util/intelp2m/platforms/common/fields"
 	"review.coreboot.org/coreboot.git/util/intelp2m/platforms/common/register/bits"
 )
 
diff --git a/util/intelp2m/fields/cb/cb.go b/util/intelp2m/platforms/common/fields/cb/cb.go
similarity index 100%
rename from util/intelp2m/fields/cb/cb.go
rename to util/intelp2m/platforms/common/fields/cb/cb.go
diff --git a/util/intelp2m/fields/cb/cb_test.go b/util/intelp2m/platforms/common/fields/cb/cb_test.go
similarity index 96%
rename from util/intelp2m/fields/cb/cb_test.go
rename to util/intelp2m/platforms/common/fields/cb/cb_test.go
index e553551199..f4fcba850e 100644
--- a/util/intelp2m/fields/cb/cb_test.go
+++ b/util/intelp2m/platforms/common/fields/cb/cb_test.go
@@ -4,7 +4,7 @@ import (
 	"testing"
 
 	"review.coreboot.org/coreboot.git/util/intelp2m/config/p2m"
-	"review.coreboot.org/coreboot.git/util/intelp2m/fields/test"
+	"review.coreboot.org/coreboot.git/util/intelp2m/platforms/common/fields/test"
 )
 
 // sliding-one
diff --git a/util/intelp2m/fields/fields.go b/util/intelp2m/platforms/common/fields/fields.go
similarity index 70%
rename from util/intelp2m/fields/fields.go
rename to util/intelp2m/platforms/common/fields/fields.go
index 19074f9ad1..dc5f7bd7b4 100644
--- a/util/intelp2m/fields/fields.go
+++ b/util/intelp2m/platforms/common/fields/fields.go
@@ -2,10 +2,10 @@ package fields
 
 import (
 	"review.coreboot.org/coreboot.git/util/intelp2m/config/p2m"
-	"review.coreboot.org/coreboot.git/util/intelp2m/fields/cb"
-	"review.coreboot.org/coreboot.git/util/intelp2m/fields/fsp"
-	"review.coreboot.org/coreboot.git/util/intelp2m/fields/raw"
 	"review.coreboot.org/coreboot.git/util/intelp2m/platforms/common"
+	"review.coreboot.org/coreboot.git/util/intelp2m/platforms/common/fields/cb"
+	"review.coreboot.org/coreboot.git/util/intelp2m/platforms/common/fields/fsp"
+	"review.coreboot.org/coreboot.git/util/intelp2m/platforms/common/fields/raw"
 )
 
 // InterfaceSet - set the interface for decoding configuration
diff --git a/util/intelp2m/fields/fsp/fsp.go b/util/intelp2m/platforms/common/fields/fsp/fsp.go
similarity index 100%
rename from util/intelp2m/fields/fsp/fsp.go
rename to util/intelp2m/platforms/common/fields/fsp/fsp.go
diff --git a/util/intelp2m/fields/fsp/fsp_test.go b/util/intelp2m/platforms/common/fields/fsp/fsp_test.go
similarity index 98%
rename from util/intelp2m/fields/fsp/fsp_test.go
rename to util/intelp2m/platforms/common/fields/fsp/fsp_test.go
index 3b6d8c6650..dd36e929c2 100644
--- a/util/intelp2m/fields/fsp/fsp_test.go
+++ b/util/intelp2m/platforms/common/fields/fsp/fsp_test.go
@@ -4,7 +4,7 @@ import (
 	"testing"
 
 	"review.coreboot.org/coreboot.git/util/intelp2m/config/p2m"
-	"review.coreboot.org/coreboot.git/util/intelp2m/fields/test"
+	"review.coreboot.org/coreboot.git/util/intelp2m/platforms/common/fields/test"
 )
 
 func TestFSPFields(t *testing.T) {
diff --git a/util/intelp2m/fields/raw/raw.go b/util/intelp2m/platforms/common/fields/raw/raw.go
similarity index 100%
rename from util/intelp2m/fields/raw/raw.go
rename to util/intelp2m/platforms/common/fields/raw/raw.go
diff --git a/util/intelp2m/fields/raw/raw_test.go b/util/intelp2m/platforms/common/fields/raw/raw_test.go
similarity index 95%
rename from util/intelp2m/fields/raw/raw_test.go
rename to util/intelp2m/platforms/common/fields/raw/raw_test.go
index 067f6aa5ac..d33229dac6 100644
--- a/util/intelp2m/fields/raw/raw_test.go
+++ b/util/intelp2m/platforms/common/fields/raw/raw_test.go
@@ -4,7 +4,7 @@ import (
 	"testing"
 
 	"review.coreboot.org/coreboot.git/util/intelp2m/config/p2m"
-	"review.coreboot.org/coreboot.git/util/intelp2m/fields/test"
+	"review.coreboot.org/coreboot.git/util/intelp2m/platforms/common/fields/test"
 )
 
 func TestRAWFields(t *testing.T) {
diff --git a/util/intelp2m/fields/test/suite.go b/util/intelp2m/platforms/common/fields/test/suite.go
similarity index 94%
rename from util/intelp2m/fields/test/suite.go
rename to util/intelp2m/platforms/common/fields/test/suite.go
index 816a3a8105..7fed3f3bba 100644
--- a/util/intelp2m/fields/test/suite.go
+++ b/util/intelp2m/platforms/common/fields/test/suite.go
@@ -4,9 +4,9 @@ import (
 	"fmt"
 	"testing"
 
-	"review.coreboot.org/coreboot.git/util/intelp2m/fields"
 	"review.coreboot.org/coreboot.git/util/intelp2m/platforms"
 	"review.coreboot.org/coreboot.git/util/intelp2m/platforms/common"
+	"review.coreboot.org/coreboot.git/util/intelp2m/platforms/common/fields"
 )
 
 type TestCase struct {
diff --git a/util/intelp2m/platforms/test/suite.go b/util/intelp2m/platforms/test/suite.go
index aa14d04677..07085368a8 100644
--- a/util/intelp2m/platforms/test/suite.go
+++ b/util/intelp2m/platforms/test/suite.go
@@ -5,9 +5,9 @@ import (
 	"testing"
 
 	"review.coreboot.org/coreboot.git/util/intelp2m/config/p2m"
-	"review.coreboot.org/coreboot.git/util/intelp2m/fields"
 	"review.coreboot.org/coreboot.git/util/intelp2m/platforms"
 	"review.coreboot.org/coreboot.git/util/intelp2m/platforms/common"
+	"review.coreboot.org/coreboot.git/util/intelp2m/platforms/common/fields"
 )
 
 type (

From da54bd60af60e1e6e1b92c272972f87c25f3234b Mon Sep 17 00:00:00 2001
From: Maxim Polyakov <max.senia.poliak@gmail.com>
Date: Mon, 9 Jan 2023 23:48:04 +0300
Subject: [PATCH 0259/3886] Documentation: Update information about intelp2m
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Change-Id: I80d5fb5d46b50193e8fecc647d9052a2e29af93f
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71757
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Filip Lewiński <filip.lewinski@3mdeb.com>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
---
 Documentation/util.md                      |   4 +-
 Documentation/util/intelp2m/gopackages.png | Bin 11594 -> 0 bytes
 Documentation/util/intelp2m/index.md       | 359 ++++++++++++---------
 util/README.md                             |   4 +-
 4 files changed, 215 insertions(+), 152 deletions(-)
 delete mode 100644 Documentation/util/intelp2m/gopackages.png

diff --git a/Documentation/util.md b/Documentation/util.md
index f902ba4fdd..e6d1402c8a 100644
--- a/Documentation/util.md
+++ b/Documentation/util.md
@@ -70,8 +70,8 @@ into a format which can be used in coreboot's verb table `Go`
 `C`
 * __intelmetool__ - Dump interesting things about Management Engine
 even if hidden `C`
-* __intelp2m__ - convert the configuration DW0/1 registers value from
-an inteltool dump to coreboot macros. `go`
+* __intelp2m__ - Convert the inteltool register dump to gpio.h with GPIO
+configuration for porting coreboot to your motherboard. `Go`
 * __inteltool__ - Provides information about the Intel CPU/chipset
 hardware configuration (register contents, MSRs, etc). `C`
 * __intelvbttool__ - Parse VBT from VGA BIOS `C`
diff --git a/Documentation/util/intelp2m/gopackages.png b/Documentation/util/intelp2m/gopackages.png
deleted file mode 100644
index fb81a1ce1f38dc5e5bee584a103adeb0dc371907..0000000000000000000000000000000000000000
GIT binary patch
literal 0
HcmV?d00001

literal 11594
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z4+5cD0H3lyj)598IyouukIGX|{T2k<4xIso<90VSZ$cnN(R6!{PJr?$_d6z@5D4Q}
z%7+T)miq((xi)(D_Dutn<pNR3UWl;WyrLn<eAVE?>C4Bz-a4Il{_&|ukD~mA_$$->
zRc1!sM2yA*57q~f=9hC%<(jw`g+w+o-?hGT>CPp+@Cg=MA(xy5gUQVwwYW^SyCk8O
zq|TJLOJScn-zpVLdbZ!Nvz%#lJD`Cq6E>jf_pfAjPO~&d?(83sNF;a_;u4Ka$U4-h
zp`h2%4Kh!fopmfSuGBqFc1j>=YimzUP4!(h!@Sv<czFG%Id!99wOw6Rl|#jl)VhNN
zJ85NrfuBcR1m|UqLL$|yjx%0QZp(oEd?N0l5mZ|VZK$s|WObHG9_Ba}R&?{j_UQ>Y
z`5NA%ji=`j;f6OjCiCaG*^P?~S(b%UEL2s0!2PaY$X#=gdK3wP+RAe|38bc{*GR=g
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diff --git a/Documentation/util/intelp2m/index.md b/Documentation/util/intelp2m/index.md
index 98b9c009d6..dd7994e19c 100644
--- a/Documentation/util/intelp2m/index.md
+++ b/Documentation/util/intelp2m/index.md
@@ -1,210 +1,273 @@
 Intel Pad to Macro (intelp2m) converter
 =======================================
 
-This utility allows one to convert the configuration DW0/1 register
-values from an inteltool dump to coreboot macros.
+The utility generates `output/gpio.h` with the GPIO configuration for SoC or PCH from intel.
+Use it to create coreboot port for your motherboard in the `src/mainboard/your-motherboard`
+directory. Depending on the settings, you can create several configuration formats:
+- [coreboot macros](../../getting_started/gpio.md);
+- [Intel FSP macros](../../soc/intel/fsp/index.md).
+
+Installing the latest version:
+
+```bash
+go install review.coreboot.org/coreboot.git/util/intelp2m@master
+```
+
+Including in the project as an external library:
+
+```bash
+go get review.coreboot.org/coreboot.git/util/intelp2m@master
+```
+
+## Build
+
+Since the utility is written in Go, you need to install the official
+[go-compiler and go-tools](https://go.dev/dl/) to build the executive
+image.
 
 ```bash
 cd util/intelp2m
 make
+./intelp2m -version
+```
+
+Set automatic argument completion:
+
+```bash
+complete -C `pwd`/intelp2m ./intelp2m
+```
+
+## Demo
+
+```bash
+./intelp2m -platform snr -file parser/testlog/inteltool_test.log
+```
+
+## Input data
+
+The chipset register dump obtained using [inteltool](../../util.md) is used as input data.
+
+```bash
+cd util/inteltool
+make
+sudo ./inteltool -G > inteltool.log
+```
+
+After this step, you can generate `gpio.h`:
+
+```bash
+./intelp2m -file ../inteltool/inteltool.log
+```
+
+More details in the help:
+
+```bash
 ./intelp2m -h
-./intelp2m -file /path/to/inteltool.log
 ```
 
 ## Platforms
 
-It is possible to use templates for parsing inteltool.log files.
-To specify such a pattern, use the option `-t <template number>`.
+The utility supports the following chipsets from Intel:
 
-```text
-    -t
-    template type number
-        0 - inteltool.log (default)
-        1 - gpio.h
-        2 - your template
-```
+* `adl` - Alder Lake PCH
+* `apl` - Apollo Lake SoC
+* `cnl` - CannonLake-LP or Whiskeylake/Coffeelake/Cometlake-U SoC
+* `ebg` - Emmitsburg PCH with Xeon SP
+* `jsl` - Jasper Lake SoC
+* `lbg` - Lewisburg PCH with Xeon SP
+* `mtl` - MeteorLake SoC
+* `snr` - Sunrise PCH or Skylake/Kaby Lake SoC
+* `tgl` - TigerLake-H SoC
 
-For example, using template type 1, you can parse gpio.h from an
-existing board in the coreboot project.
+The `-platform` option allows you to identify one of the above platforms:
 
 ```bash
-./intelp2m -t 1 -file coreboot/src/mainboard/yourboard/gpio.h
+./intelp2m -platform <platform> -file path/to/inteltool.log
 ```
 
-You can also add a template to 'parser/template.go' for your file type
-with the configuration of the pads.
+Show more details:
 
-platform type is set using the -p option (Sunrise by default):
+```bash
+./intelp2m -platform ?
+```
 
-```text
--p string
-  set up a platform
-    snr - Sunrise PCH with Skylake/Kaby Lake CPU
-    lbg - Lewisburg PCH with Xeon SP CPU
-    apl - Apollo Lake SoC
-    cnl - CannonLake-LP or Whiskeylake/Coffeelake/Cometlake-U SoC
-    adl - AlderLake PCH
-  (default "snr")
+## Auto-check macro
+
+The utility automatically checks the bit fields of the GPIO registers before generating the macro.
+If the bit is set to 1 in a register but isn't used in the "short" macro, the "long" macro is
+generated. This avoids data loss in the configuration.
+
+```c
+// the "short" macro:
+PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_39, UP_20K, DEEP, NF1, TxLASTRxE, DISPUPD),
+
+// the "long" macro:
+_PAD_CFG_STRUCT(GPIO_39, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF), PAD_PULL(UP_20K) | PAD_IOSTERM(DISPUPD)),
+
+// [*] PAD_TRIG(OFF) isn't used in the "short" macro.
+```
+
+The option `-u`, `-unchecked` is used to disable automatic verification.
+In this case, all macros in `gpio.h` are generated in the "short" format:
+
+```c
+...
+PAD_NC(GPP_F18, NONE),
+PAD_CFG_NF(GPP_F19, NONE, PLTRST, NF1),
+...
 ```
 
 ```bash
-./intelp2m -p <platform> -file path/to/inteltool.log
+./intelp2m -unchecked -platform apl -file path/to/inteltool.log
+```
+
+## Excluding fields from the macro
+
+The utility can generate "long" macros without fields that aren't used in "short" ones.
+The `-e`, `-exclude` option is used to exclude these fields from the generated macros in
+`gpio.h`:
+
+```bash
+./intelp2m -exclude -platform apl -file path/to/inteltool.log
+```
+
+```c
+_PAD_CFG_STRUCT(GPIO_39, PAD_FUNC(NF1) | PAD_RESET(DEEP), PAD_PULL(UP_20K) | PAD_IOSTERM(DISPUPD)),
+
+// [*] PAD_TRIG(OFF) field was excluded from the "long" macro.
 ```
 
 ## Packages
 
-![][pckgs]
+```text
++-------------------------------------------------------------------+
+|                              main                                 |
++-------------------------------------------------------------------+
+                         |                 |                 |
+                         V                 V                 V
++------------+   +--------------+   +-------------+   +-------------+
+|  template  |<--|    parser    |   |  generator  |   |   printer   |
++------------+   +--------------+   +-------------+   +-------------+
+                         |
+                         V
++-------------------------------------------------------------------+
+|                           platforms                               |
++-------------------------------------------------------------------+
+    |          |          |          |          |               |
+    V          V          V          V          V               V
++-------+  +-------+  +-------+  +-------+  +-------+       +-------+
+|  adl  |  |  apl  |  |  cnl  |  |  lbg  |  |  snr  | * * * | other |
++-------+  +-------+  +-------+  +-------+  +-------+       +-------+
+    |          |          |          |          |               |
+    V          V          V          V          V               V
++-------------------------------------------------------------------+
+|                             common                                |
++-------------------------------------------------------------------+
+                  |                           |              |
+                  V                           |              |
++------------------------------------+        |              |
+|               fields               |        |              |
++------------------------------------+        |              |
+     |            |             |             |              |
+     V            V             V             V              V
++--------+   +---------+   +---------+  +-----------+  +------------+
+|   cb   |   |   raw   |   |   fsp   |  |   macro   |  |  register  |
++--------+   +---------+   +---------+  +-----------+  +------------+
+```
 
-[pckgs]: gopackages.png
+## Format
 
-## Bit fields in macros
-
-Use the `-fld=cb` option to only generate a sequence of bit fields in
-a new macro:
+Depending on the options -i, -ii, -iii, -iiiii (information level),
+the utility can generate the configuration in different formats:
 
 ```bash
-./intelp2m -fld cb -p apl -file ../apollo-inteltool.log
+./intelp2m [-i | -ii | -iii | -iiii] -platform apl -file path/to/inteltool.log
 ```
 
+* i adding a function name:
+
 ```c
-_PAD_CFG_STRUCT(GPIO_37, PAD_FUNC(NF1) | PAD_TRIG(OFF) | PAD_TRIG(OFF), \
-    PAD_PULL(DN_20K)), /* LPSS_UART0_TXD */
+_PAD_CFG_STRUCT(GPIO_39, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF), PAD_PULL(UP_20K) | PAD_IOSTERM(DISPUPD)), /* LPSS_UART0_TXD */
 ```
 
-## Raw DW0, DW1 register value
-
-To generate the gpio.c with raw PAD_CFG_DW0 and PAD_CFG_DW1 register
-values you need to use the -fld=raw option:
-
-```bash
-./intelp2m -fld raw -file /path/to/inteltool.log
-```
-
-```c
-_PAD_CFG_STRUCT(GPP_A10, 0x44000500, 0x00000000),
-```
-
-```bash
-./intelp2m -iiii -fld raw -file /path/to/inteltool.log
-```
-
-```c
-/* GPP_A10 - CLKOUT_LPC1 */
-/* DW0: 0x44000500, DW1: 0x00000000 */
-/* DW0: 0x04000100 - IGNORED */
-/* PAD_CFG_NF(GPP_A10, NONE, DEEP, NF1), */
-_PAD_CFG_STRUCT(GPP_A10, 0x44000500, 0x00000000),
-```
-
-## Macro Check
-
-After generating the macro, the utility checks all used
-fields of the configuration registers. If some field has been
-ignored, the utility generates field macros. To not check
-macros, use the -n option:
-
-```bash
-./intelp2m -n -file /path/to/inteltool.log
-```
-
-In this case, some fields of the configuration registers
-DW0 will be ignored.
-
-```c
-PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_38, UP_20K, DEEP, NF1, HIZCRx1, DISPUPD),
-PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_39, UP_20K, DEEP, NF1, TxLASTRxE, DISPUPD),
-```
-
-## Information level
-
-The utility can generate additional information about the bit
-fields of the DW0 and DW1 configuration registers. Using the
-options -i, -ii, -iii, -iiii you can set the info level from
-1 to 4:
-
-```bash
-./intelp2m -i -file /path/to/inteltool.log
-```
-
-```c
-_PAD_CFG_STRUCT(GPIO_39, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF),\
-    PAD_PULL(UP_20K) | PAD_IOSTERM(DISPUPD)),    /* LPSS_UART0_TXD */
-```
-
-```bash
-./intelp2m -ii -file /path/to/inteltool.log
-./intelp2m -iii -file /path/to/inteltool.log
-./intelp2m -iiii -file /path/to/inteltool.log
-```
+* ii adds configuration register values:
 
 ```c
 /* GPIO_39 - LPSS_UART0_TXD */
-/* DW0: 0x44000400, DW1: 0x00003100 */ --> (ii)
-/* DW0 : PAD_TRIG(OFF) - IGNORED */ --> (iii)
-/* PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_39, UP_20K, DEEP, NF1, TxLASTRxE,
-   DISPUPD), */ --> (iiii)
-_PAD_CFG_STRUCT(GPIO_39, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF),
-    PAD_PULL(UP_20K) | PAD_IOSTERM(DISPUPD)),
+/* DW0: 0x44000400, DW1: 0x00003100 */
+_PAD_CFG_STRUCT(GPIO_39, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF), PAD_PULL(UP_20K) | PAD_IOSTERM(DISPUPD)),
 ```
 
-If the -n switch was used and macros was generated without checking:
+* iii adds information about ignored fields:
+
 ```c
-/* GPIO_39 - LPSS_UART0_TXD */ --> (i)
-/* DW0: 0x44000400, DW1: 0x00003100 */ --> (ii)
-/* DW0: PAD_TRIG(OFF) - IGNORED */ --> (iii)
-/* _PAD_CFG_STRUCT(GPIO_39, PAD_FUNC(NF1) | PAD_RESET(DEEP) |
-  PAD_TRIG(OFF), PAD_PULL(UP_20K) | PAD_IOSTERM(DISPUPD)), */ --> (iiii)
-PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_39, UP_20K, DEEP, NF1, TxLASTRxE, \
-    DISPUPD),
+/* GPIO_39 - LPSS_UART0_TXD */
+/* DW0: 0x44000400, DW1: 0x00003100 */
+/* DW0 : PAD_TRIG(OFF) - IGNORED */
+_PAD_CFG_STRUCT(GPIO_39, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF), PAD_PULL(UP_20K) | PAD_IOSTERM(DISPUPD)),
 ```
 
-## Ignoring Fields
-
-Utilities can generate the _PAD_CFG_STRUCT macro and exclude fields
-from it that are not in the corresponding PAD_CFG_*() macro:
-
-```bash
-./intelp2m -iiii -fld cb -ign -file /path/to/inteltool.log
-```
+* iiii adds the "short" macro corresponding to the current one (possibly after excluding unused fields):
 
 ```c
 /* GPIO_39 - LPSS_UART0_TXD */
 /* DW0: 0x44000400, DW1: 0x00003100 */
 /* DW0: PAD_TRIG(OFF) - IGNORED */
-/* PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_39, UP_20K, DEEP, NF1,
-   TxLASTRxE, DISPUPD), */
-_PAD_CFG_STRUCT(GPIO_39, PAD_FUNC(NF1) | PAD_RESET(DEEP), \
-    PAD_PULL(UP_20K) | PAD_IOSTERM(DISPUPD)),
+/* PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_39, UP_20K, DEEP, NF1, TxLASTRxE, DISPUPD), */
+_PAD_CFG_STRUCT(GPIO_39, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF), PAD_PULL(UP_20K) | PAD_IOSTERM(DISPUPD)),
 ```
 
-## FSP-style macro
-
-The utility allows one to generate macros that include fsp/edk2-platform
-style bitfields:
-
-```bash
-./intelp2m -i -fld fsp -p lbg -file ../crb-inteltool.log
-```
+The same without automatic check:
 
 ```c
-{ GPIO_SKL_H_GPP_A12, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirInInvOut,
-  GpioOutLow, GpioIntSci | GpioIntLvlEdgDis, GpioResetNormal, GpioTermNone,
-  GpioPadConfigLock },    /* GPIO */
+/* GPIO_39 - LPSS_UART0_TXD */
+/* DW0: 0x44000400, DW1: 0x00003100 */
+/* DW0: PAD_TRIG(OFF) - IGNORED */
+/* _PAD_CFG_STRUCT(GPIO_39, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF), PAD_PULL(UP_20K) | PAD_IOSTERM(DISPUPD)), */
+PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_39, UP_20K, DEEP, NF1, TxLASTRxE, DISPUPD),
 ```
 
+iiii generates an original macro in the comments.
+
+## Long macros with fields collection
+
+Depending on the value of the option -fields, the utility can generate
+long macros with different styles of the field collection:
+
 ```bash
-./intelp2m -iiii -fld fsp -p lbg -file ../crb-inteltool.log
+./intelp2m -fields [fsp | cb | raw] -platform apl -file ../apollo-inteltool.log
 ```
 
+* fsp
+
 ```c
-/* GPP_A12 - GPIO */
-/* DW0: 0x80880102, DW1: 0x00000000 */
-/* PAD_CFG_GPI_SCI(GPP_A12, NONE, PLTRST, LEVEL, INVERT), */
-{ GPIO_SKL_H_GPP_A12, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirInInvOut,
-  GpioOutLow, GpioIntSci | GpioIntLvlEdgDis, GpioResetNormal, GpioTermNone,
-  GpioPadConfigLock },
+{ GPIO_SKL_H_GPP_A12, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirInInvOut, GpioOutLow, GpioIntSci | GpioIntLvlEdgDis, GpioResetNormal GpioTermNone, GpioPadConfigLock },
 ```
 
-## Supported Chipsets
+* cb
 
-  Sunrise PCH, Lewisburg PCH, Apollo Lake SoC, CannonLake-LP SoCs
+```c
+_PAD_CFG_STRUCT(GPIO_39, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF), PAD_PULL(UP_20K) | PAD_IOSTERM(DISPUPD)),
+```
+
+* raw
+
+```c
+_PAD_CFG_STRUCT(GPP_A10, 0x44000500, 0x00000000),
+```
+
+Show more details:
+
+```bash
+./intelp2m -fields ?
+```
+
+## Unit testing
+
+Please run the tests before creating a new commit:
+
+```bash
+make test
+```
+
+If successful, all tests contain the PASS prefix.
diff --git a/util/README.md b/util/README.md
index 7a98bb6061..6d58d7a71b 100644
--- a/util/README.md
+++ b/util/README.md
@@ -61,8 +61,8 @@ into a format which can be used in coreboot's verb table `Go`
 `C`
 * __intelmetool__ - Dump interesting things about Management Engine
 even if hidden `C`
-* __intelp2m__ - convert the configuration DW0/1 registers value from
-an inteltool dump to coreboot macros. `go`
+* __intelp2m__ - Generate a GPIO configuration based on a register dump
+obtained using inteltool. `Go`
 * __inteltool__ - Provides information about the Intel CPU/chipset
 hardware configuration (register contents, MSRs, etc). `C`
 * __intelvbttool__ - Parse VBT from VGA BIOS `C`

From a4f4dc57691f1e46ec5270b614ce25776c2cd3d5 Mon Sep 17 00:00:00 2001
From: Maxim Polyakov <max.senia.poliak@gmail.com>
Date: Wed, 25 Dec 2024 22:08:31 +0300
Subject: [PATCH 0260/3886] util/intelp2m: Provide GPP group slice from each
 platform

Instead of a pointer to a function for analyzing the pad name, provide
GPP group slice with pad names to the parser. This will get rid of some
functions and files and make the code cleaner.

TEST:
- 'make test' = PASS;
- 'intelp2m -file parser/testlog/inteltool_test.log' = no errors.

Change-Id: I0d7818d3892450a37bffbf1ffd9524888e4675bf
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85769
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
---
 util/intelp2m/parser/parser.go             | 18 +++++++--
 util/intelp2m/platforms/adl/macro.go       |  5 +++
 util/intelp2m/platforms/adl/template.go    | 13 -------
 util/intelp2m/platforms/apl/macro.go       | 12 ++++++
 util/intelp2m/platforms/apl/template.go    | 19 ----------
 util/intelp2m/platforms/cnl/macro.go       | 20 ++++++++++
 util/intelp2m/platforms/cnl/template.go    | 25 -------------
 util/intelp2m/platforms/common/template.go | 15 --------
 util/intelp2m/platforms/ebg/macro.go       |  4 ++
 util/intelp2m/platforms/ebg/template.go    | 14 -------
 util/intelp2m/platforms/jsl/macro.go       |  4 ++
 util/intelp2m/platforms/jsl/template.go    | 14 -------
 util/intelp2m/platforms/lbg/macro.go       |  4 ++
 util/intelp2m/platforms/lbg/template.go    | 12 ------
 util/intelp2m/platforms/mtl/macro.go       |  4 ++
 util/intelp2m/platforms/mtl/template.go    | 14 -------
 util/intelp2m/platforms/platforms.go       | 43 +++++++++++-----------
 util/intelp2m/platforms/snr/macro.go       |  4 ++
 util/intelp2m/platforms/snr/template.go    | 12 ------
 util/intelp2m/platforms/tgl/macro.go       |  4 ++
 util/intelp2m/platforms/tgl/template.go    | 14 -------
 21 files changed, 96 insertions(+), 178 deletions(-)
 delete mode 100644 util/intelp2m/platforms/adl/template.go
 delete mode 100644 util/intelp2m/platforms/apl/template.go
 delete mode 100644 util/intelp2m/platforms/cnl/template.go
 delete mode 100644 util/intelp2m/platforms/common/template.go
 delete mode 100644 util/intelp2m/platforms/ebg/template.go
 delete mode 100644 util/intelp2m/platforms/jsl/template.go
 delete mode 100644 util/intelp2m/platforms/lbg/template.go
 delete mode 100644 util/intelp2m/platforms/mtl/template.go
 delete mode 100644 util/intelp2m/platforms/snr/template.go
 delete mode 100644 util/intelp2m/platforms/tgl/template.go

diff --git a/util/intelp2m/parser/parser.go b/util/intelp2m/parser/parser.go
index 91428f83de..35273e5ad7 100644
--- a/util/intelp2m/parser/parser.go
+++ b/util/intelp2m/parser/parser.go
@@ -82,15 +82,25 @@ func extractGroup(line string) Entry {
 	return group
 }
 
+// checkGPPG() checks whether the desired group is present in the string
+func checkKeywords(line string, slice []string) bool {
+	for _, key := range slice {
+		if strings.Contains(line, key) {
+			return true
+		}
+	}
+	return false
+}
+
 // Extract() extracts pad information from a string
 func Extract(line string) Entry {
-	if included, _ := common.KeywordsCheck(line, "GPIO Community", "GPIO Group"); included {
+	if checkKeywords(line, []string{"GPIO Community", "GPIO Group"}) {
 		return extractGroup(line)
 	}
-	if checkKeyword := platforms.GetKeywordChekingAction(); checkKeyword == nil {
-		logs.Errorf("information extraction error: skip line <%s>", line)
+	if gppg, err := platforms.GetGPPGroups(); err != nil {
+		logs.Errorf("extract error: %v: skip line <%s>", err, line)
 		return Entry{EType: EntryEmpty}
-	} else if checkKeyword(line) {
+	} else if checkKeywords(line, gppg) {
 		pad, err := extractPad(line)
 		if err != nil {
 			logs.Errorf("extract pad info from %s: %v", line, err)
diff --git a/util/intelp2m/platforms/adl/macro.go b/util/intelp2m/platforms/adl/macro.go
index 63104d0ce8..d17795bf32 100644
--- a/util/intelp2m/platforms/adl/macro.go
+++ b/util/intelp2m/platforms/adl/macro.go
@@ -14,6 +14,11 @@ const (
 	DW1Mask uint32 = 0b11111101111111111100001111111111
 )
 
+// "GPP_A", "GPP_B", "GPP_C", "GPP_D", "GPP_E", "GPP_F", "GPP_G",
+// "GPP_H", "GPP_I", "GPP_J", "GPP_K", "GPP_R", "GPP_S", "GPP_T",
+// "GPD", "VGPIO_USB", "VGPIO_PCIE"
+var GPPGroups = []string{"GPP_", "GPD", "VGPIO"}
+
 var remapping = common.ResetSources{
 	0b00: bits.RstCfgRSMRST << bits.DW0PadRstCfg,
 	0b01: bits.RstCfgDEEP << bits.DW0PadRstCfg,
diff --git a/util/intelp2m/platforms/adl/template.go b/util/intelp2m/platforms/adl/template.go
deleted file mode 100644
index 4af499dbab..0000000000
--- a/util/intelp2m/platforms/adl/template.go
+++ /dev/null
@@ -1,13 +0,0 @@
-package adl
-
-import "review.coreboot.org/coreboot.git/util/intelp2m/platforms/common"
-
-// CheckKeyword() parses lines of the configuration file and returns true if the keyword is
-// contained in the line
-// "GPP_A", "GPP_B", "GPP_C", "GPP_D", "GPP_E", "GPP_F", "GPP_G",
-// "GPP_H", "GPP_I", "GPP_J", "GPP_K", "GPP_R", "GPP_S", "GPP_T",
-// "GPD", "VGPIO_USB", "VGPIO_PCIE"
-func CheckKeyword(line string) bool {
-	isIncluded, _ := common.KeywordsCheck(line, "GPP_", "GPD", "VGPIO")
-	return isIncluded
-}
diff --git a/util/intelp2m/platforms/apl/macro.go b/util/intelp2m/platforms/apl/macro.go
index 614d0bebd6..103d602927 100644
--- a/util/intelp2m/platforms/apl/macro.go
+++ b/util/intelp2m/platforms/apl/macro.go
@@ -12,6 +12,18 @@ const (
 	DW1Mask uint32 = 0b11111111111111000000000011111111
 )
 
+var GPPGroups = []string{
+	"GPIO_", "TCK", "TRST_B", "TMS", "TDI", "CX_PMODE", "CX_PREQ_B", "JTAGX", "CX_PRDY_B",
+	"TDO", "CNV_BRI_DT", "CNV_BRI_RSP", "CNV_RGI_DT", "CNV_RGI_RSP", "SVID0_ALERT_B",
+	"SVID0_DATA", "SVID0_CLK", "PMC_SPI_FS", "PMC_SPI_RXD", "PMC_SPI_TXD", "PMC_SPI_CLK",
+	"PMIC_PWRGOOD", "PMIC_RESET_B", "PMIC_THERMTRIP_B", "PMIC_STDBY", "PROCHOT_B",
+	"PMIC_I2C_SCL", "PMIC_I2C_SDA", "FST_SPI_CLK_FB", "OSC_CLK_OUT_", "PMU_AC_PRESENT",
+	"PMU_BATLOW_B", "PMU_PLTRST_B", "PMU_PWRBTN_B", "PMU_RESETBUTTON_B", "PMU_SLP_S0_B",
+	"PMU_SLP_S3_B", "PMU_SLP_S4_B", "PMU_SUSCLK", "PMU_WAKE_B", "SUS_STAT_B", "SUSPWRDNACK",
+	"SMB_ALERTB", "SMB_CLK", "SMB_DATA", "LPC_ILB_SERIRQ", "LPC_CLKOUT", "LPC_AD", "LPC_CLKRUNB",
+	"LPC_FRAMEB",
+}
+
 type BasePlatform struct {
 	common.BasePlatform
 }
diff --git a/util/intelp2m/platforms/apl/template.go b/util/intelp2m/platforms/apl/template.go
deleted file mode 100644
index 014431d18a..0000000000
--- a/util/intelp2m/platforms/apl/template.go
+++ /dev/null
@@ -1,19 +0,0 @@
-package apl
-
-import "review.coreboot.org/coreboot.git/util/intelp2m/platforms/common"
-
-// CheckKeyword() parses lines of the configuration file and returns true if the keyword is
-// contained in the line
-func CheckKeyword(line string) bool {
-	isIncluded, _ := common.KeywordsCheck(line,
-		"GPIO_", "TCK", "TRST_B", "TMS", "TDI", "CX_PMODE", "CX_PREQ_B", "JTAGX", "CX_PRDY_B",
-		"TDO", "CNV_BRI_DT", "CNV_BRI_RSP", "CNV_RGI_DT", "CNV_RGI_RSP", "SVID0_ALERT_B",
-		"SVID0_DATA", "SVID0_CLK", "PMC_SPI_FS", "PMC_SPI_RXD", "PMC_SPI_TXD", "PMC_SPI_CLK",
-		"PMIC_PWRGOOD", "PMIC_RESET_B", "PMIC_THERMTRIP_B", "PMIC_STDBY", "PROCHOT_B",
-		"PMIC_I2C_SCL", "PMIC_I2C_SDA", "FST_SPI_CLK_FB", "OSC_CLK_OUT_", "PMU_AC_PRESENT",
-		"PMU_BATLOW_B", "PMU_PLTRST_B", "PMU_PWRBTN_B", "PMU_RESETBUTTON_B", "PMU_SLP_S0_B",
-		"PMU_SLP_S3_B", "PMU_SLP_S4_B", "PMU_SUSCLK", "PMU_WAKE_B", "SUS_STAT_B", "SUSPWRDNACK",
-		"SMB_ALERTB", "SMB_CLK", "SMB_DATA", "LPC_ILB_SERIRQ", "LPC_CLKOUT", "LPC_AD", "LPC_CLKRUNB",
-		"LPC_FRAMEB")
-	return isIncluded
-}
diff --git a/util/intelp2m/platforms/cnl/macro.go b/util/intelp2m/platforms/cnl/macro.go
index 625df0aa5f..9cb8765a1f 100644
--- a/util/intelp2m/platforms/cnl/macro.go
+++ b/util/intelp2m/platforms/cnl/macro.go
@@ -15,6 +15,26 @@ const (
 	DW1Mask uint32 = 0b11111101111111111100001111111111
 )
 
+var GPPGroups = []string{
+	"GPP_", "GPD", // "GPP_A", "GPP_B", "GPP_G", "GPP_D", "GPP_F", "GPP_H", "GPP_C", "GPP_E"
+	"I2S1_TXD", "CNV_BTEN", "CNV_GNEN", "CNV_WFEN", "CNV_WCEN", "vCNV_GNSS_HOST_WAKE_B",
+	"vSD3_CD_B", "CNV_BT_HOST_WAKE_B", "CNV_BT_IF_SELECT", "vCNV_BT_UART_TXD",
+	"vCNV_BT_UART_RXD", "vCNV_BT_UART_CTS_B", "vCNV_BT_UART_RTS_B", "vCNV_MFUART1_TXD",
+	"vCNV_MFUART1_RXD", "vCNV_MFUART1_CTS_B", "vCNV_MFUART1_RTS_B", "vCNV_GNSS_UART_TXD",
+	"vCNV_GNSS_UART_RXD", "vCNV_GNSS_UART_CTS_B", "vCNV_GNSS_UART_RTS_B", "vUART0_TXD",
+	"vUART0_RXD", "vUART0_CTS_B", "vUART0_RTS_B", "vISH_UART0_TXD", "vISH_UART0_RXD",
+	"vISH_UART0_CTS_B", "vISH_UART0_RTS_B", "vISH_UART1_TXD", "vISH_UART1_RXD",
+	"vISH_UART1_CTS_B", "vISH_UART1_RTS_B", "vCNV_BT_I2S_BCLK", "vCNV_BT_I2S_WS_SYNC",
+	"vCNV_BT_I2S_SDO", "vCNV_BT_I2S_SDI", "vSSP2_SCLK", "vSSP2_SFRM", "vSSP2_TXD",
+	"vSSP2_RXD", "SLP_LAN_B", "SLP_SUS_B", "WAKE_B", "DRAM_RESET_B", "SPI0_IO_2",
+	"SPI0_IO_3", "SPI0_MISO", "SPI0_MOSI", "SPI0_CS2_B", "SPI0_CS0_B", "SPI0_CS1_B",
+	"SPI0_CLK", "SPI0_CLK_LOOPBK", "HDACPU_SDI", "HDACPU_SDO", "HDACPU_SCLK", "PM_SYNC",
+	"PECI", "CPUPWRGD", "THRMTRIP_B", "PLTRST_CPU_B", "PM_DOWN", "TRIGGER_IN",
+	"TRIGGER_OUT", "PCH_TDO", "PCH_JTAGX", "PROC_PRDY_B", "PROC_PREQ_B", "CPU_TRST_B",
+	"PCH_TDI", "PCH_TMS", "PCH_TCK", "ITP_PMODE", "SYS_PWROK", "SYS_RESET_B", "CL_RST_B",
+	"HDA_BCLK", "HDA_RST_B", "HDA_SYNC", "HDA_SDO", "HDA_SDI0", "HDA_SDI1", "I2S1_SFRM",
+}
+
 var remapping = common.ResetSources{
 	0b00: bits.RstCfgRSMRST << bits.DW0PadRstCfg,
 	0b01: bits.RstCfgDEEP << bits.DW0PadRstCfg,
diff --git a/util/intelp2m/platforms/cnl/template.go b/util/intelp2m/platforms/cnl/template.go
deleted file mode 100644
index f1bb525a6d..0000000000
--- a/util/intelp2m/platforms/cnl/template.go
+++ /dev/null
@@ -1,25 +0,0 @@
-package cnl
-
-import "review.coreboot.org/coreboot.git/util/intelp2m/platforms/common"
-
-func CheckKeyword(line string) bool {
-	// "GPP_" : "GPP_A", "GPP_B", "GPP_G", "GPP_D", "GPP_F", "GPP_H", "GPP_C", "GPP_E"
-	included, _ := common.KeywordsCheck(line, "GPP_", "GPD",
-		"I2S1_TXD", "CNV_BTEN", "CNV_GNEN", "CNV_WFEN", "CNV_WCEN", "vCNV_GNSS_HOST_WAKE_B",
-		"vSD3_CD_B", "CNV_BT_HOST_WAKE_B", "CNV_BT_IF_SELECT", "vCNV_BT_UART_TXD",
-		"vCNV_BT_UART_RXD", "vCNV_BT_UART_CTS_B", "vCNV_BT_UART_RTS_B", "vCNV_MFUART1_TXD",
-		"vCNV_MFUART1_RXD", "vCNV_MFUART1_CTS_B", "vCNV_MFUART1_RTS_B", "vCNV_GNSS_UART_TXD",
-		"vCNV_GNSS_UART_RXD", "vCNV_GNSS_UART_CTS_B", "vCNV_GNSS_UART_RTS_B", "vUART0_TXD",
-		"vUART0_RXD", "vUART0_CTS_B", "vUART0_RTS_B", "vISH_UART0_TXD", "vISH_UART0_RXD",
-		"vISH_UART0_CTS_B", "vISH_UART0_RTS_B", "vISH_UART1_TXD", "vISH_UART1_RXD",
-		"vISH_UART1_CTS_B", "vISH_UART1_RTS_B", "vCNV_BT_I2S_BCLK", "vCNV_BT_I2S_WS_SYNC",
-		"vCNV_BT_I2S_SDO", "vCNV_BT_I2S_SDI", "vSSP2_SCLK", "vSSP2_SFRM", "vSSP2_TXD",
-		"vSSP2_RXD", "SLP_LAN_B", "SLP_SUS_B", "WAKE_B", "DRAM_RESET_B", "SPI0_IO_2",
-		"SPI0_IO_3", "SPI0_MISO", "SPI0_MOSI", "SPI0_CS2_B", "SPI0_CS0_B", "SPI0_CS1_B",
-		"SPI0_CLK", "SPI0_CLK_LOOPBK", "HDACPU_SDI", "HDACPU_SDO", "HDACPU_SCLK", "PM_SYNC",
-		"PECI", "CPUPWRGD", "THRMTRIP_B", "PLTRST_CPU_B", "PM_DOWN", "TRIGGER_IN",
-		"TRIGGER_OUT", "PCH_TDO", "PCH_JTAGX", "PROC_PRDY_B", "PROC_PREQ_B", "CPU_TRST_B",
-		"PCH_TDI", "PCH_TMS", "PCH_TCK", "ITP_PMODE", "SYS_PWROK", "SYS_RESET_B", "CL_RST_B",
-		"HDA_BCLK", "HDA_RST_B", "HDA_SYNC", "HDA_SDO", "HDA_SDI0", "HDA_SDI1", "I2S1_SFRM")
-	return included
-}
diff --git a/util/intelp2m/platforms/common/template.go b/util/intelp2m/platforms/common/template.go
deleted file mode 100644
index 296f169fb3..0000000000
--- a/util/intelp2m/platforms/common/template.go
+++ /dev/null
@@ -1,15 +0,0 @@
-package common
-
-import "strings"
-
-// KeywordsCheck - check if one of the keyword from the <keywords> group is included in the
-// <line> string. Returns false if no word was found, or true otherwise and also this word
-// itself
-func KeywordsCheck(line string, keywords ...string) (bool, string) {
-	for _, key := range keywords {
-		if strings.Contains(line, key) {
-			return true, key
-		}
-	}
-	return false, ""
-}
diff --git a/util/intelp2m/platforms/ebg/macro.go b/util/intelp2m/platforms/ebg/macro.go
index f1a967ece4..da2eeac123 100644
--- a/util/intelp2m/platforms/ebg/macro.go
+++ b/util/intelp2m/platforms/ebg/macro.go
@@ -12,6 +12,10 @@ const (
 	DW1Mask = 0b11111101111111111100001111111111
 )
 
+// "GPPC_A", "GPPC_B", "GPPC_S", "GPPC_C", "GPP_D", "GPP_E", "GPPC_H", "GPP_J", "GPP_I",
+// "GPP_L", "GPP_M", "GPP_N"
+var GPPGroups = []string{"GPP_", "GPPC_"}
+
 var remapping = common.ResetSources{
 	0b00: bits.RstCfgRSMRST << bits.DW0PadRstCfg,
 	0b01: bits.RstCfgDEEP << bits.DW0PadRstCfg,
diff --git a/util/intelp2m/platforms/ebg/template.go b/util/intelp2m/platforms/ebg/template.go
deleted file mode 100644
index 451bd5dfdc..0000000000
--- a/util/intelp2m/platforms/ebg/template.go
+++ /dev/null
@@ -1,14 +0,0 @@
-package ebg
-
-import "review.coreboot.org/coreboot.git/util/intelp2m/platforms/common"
-
-// Group : "GPPC_A", "GPPC_B", "GPPC_S", "GPPC_C", "GPP_D", "GPP_E", "GPPC_H", "GPP_J",
-//         "GPP_I", "GPP_L", "GPP_M", "GPP_N"
-
-// CheckKeyword - This function is used to filter parsed lines of the configuration file and
-// returns true if the keyword is contained in the line.
-// line : string from the configuration file
-func CheckKeyword(line string) bool {
-	isIncluded, _ := common.KeywordsCheck(line, "GPP_", "GPPC_")
-	return isIncluded
-}
diff --git a/util/intelp2m/platforms/jsl/macro.go b/util/intelp2m/platforms/jsl/macro.go
index 92cb66cf33..e249662601 100644
--- a/util/intelp2m/platforms/jsl/macro.go
+++ b/util/intelp2m/platforms/jsl/macro.go
@@ -14,6 +14,10 @@ const (
 	DW1Mask = 0b11111101111111111100001111111111
 )
 
+// "GPP_A", "GPP_B", "GPP_C", "GPP_D", "GPP_E", "GPP_F", "GPP_G", "GPP_H", "GPP_R", "GPP_S",
+// "GPP_T", "GPD", "HVMOS", "VGPIO5"
+var GPPGroups = []string{"GPP_", "GPD", "VGPIO"}
+
 var remapping = common.ResetSources{
 	0b00: bits.RstCfgRSMRST << bits.DW0PadRstCfg,
 	0b01: bits.RstCfgDEEP << bits.DW0PadRstCfg,
diff --git a/util/intelp2m/platforms/jsl/template.go b/util/intelp2m/platforms/jsl/template.go
deleted file mode 100644
index acf6a5ab70..0000000000
--- a/util/intelp2m/platforms/jsl/template.go
+++ /dev/null
@@ -1,14 +0,0 @@
-package jsl
-
-import "review.coreboot.org/coreboot.git/util/intelp2m/platforms/common"
-
-// Group : "GPP_A", "GPP_B", "GPP_C", "GPP_D", "GPP_E", "GPP_F", "GPP_G", "GPP_H", "GPP_R",
-//         "GPP_S", "GPP_T", "GPD", "HVMOS", "VGPIO5"
-
-// CheckKeyword - This function is used to filter parsed lines of the configuration file and
-// returns true if the keyword is contained in the line.
-// line : string from the configuration file
-func CheckKeyword(line string) bool {
-	isIncluded, _ := common.KeywordsCheck(line, "GPP_", "GPD", "VGPIO")
-	return isIncluded
-}
diff --git a/util/intelp2m/platforms/lbg/macro.go b/util/intelp2m/platforms/lbg/macro.go
index b58c8a956a..cf40429a9d 100644
--- a/util/intelp2m/platforms/lbg/macro.go
+++ b/util/intelp2m/platforms/lbg/macro.go
@@ -12,6 +12,10 @@ const (
 	DW1Mask uint32 = 0b11111101111111111100001111111111
 )
 
+// "GPP_A", "GPP_B", "GPP_F", "GPP_C", "GPP_D", "GPP_E", "GPD", "GPP_I", "GPP_J", "GPP_K",
+// "GPP_G", "GPP_H", "GPP_L"
+var GPPGroups = []string{"GPP_", "GPD"}
+
 var remapping = common.ResetSources{
 	0b00: bits.RstCfgRSMRST << bits.DW0PadRstCfg,
 	0b01: bits.RstCfgDEEP << bits.DW0PadRstCfg,
diff --git a/util/intelp2m/platforms/lbg/template.go b/util/intelp2m/platforms/lbg/template.go
deleted file mode 100644
index f4600850df..0000000000
--- a/util/intelp2m/platforms/lbg/template.go
+++ /dev/null
@@ -1,12 +0,0 @@
-package lbg
-
-import "review.coreboot.org/coreboot.git/util/intelp2m/platforms/common"
-
-// CheckKeyword() parses lines of the configuration file and returns true if the keyword is
-// contained in the line
-// "GPP_A", "GPP_B", "GPP_F", "GPP_C", "GPP_D", "GPP_E", "GPD", "GPP_I", "GPP_J",
-// "GPP_K", "GPP_G", "GPP_H", "GPP_L"
-func CheckKeyword(line string) bool {
-	included, _ := common.KeywordsCheck(line, "GPP_", "GPD")
-	return included
-}
diff --git a/util/intelp2m/platforms/mtl/macro.go b/util/intelp2m/platforms/mtl/macro.go
index 8740f5f783..25083bc045 100644
--- a/util/intelp2m/platforms/mtl/macro.go
+++ b/util/intelp2m/platforms/mtl/macro.go
@@ -14,6 +14,10 @@ const (
 	DW1Mask = 0b11111101111111111100001111111111
 )
 
+// "GPP_V", "GPP_C", "GPP_A", "GPP_E", "GPP_H", "GPP_F", "GPP_S", "GPP_B", "GPP_D", "GPD",
+// "VGPIO_USB", "VGPIO_PCIE"
+var GPPGroups = []string{"GPP_", "GPD", "VGPIO"}
+
 var remapping = common.ResetSources{
 	0b00: bits.RstCfgRSMRST << bits.DW0PadRstCfg,
 	0b01: bits.RstCfgDEEP << bits.DW0PadRstCfg,
diff --git a/util/intelp2m/platforms/mtl/template.go b/util/intelp2m/platforms/mtl/template.go
deleted file mode 100644
index 27951fefb5..0000000000
--- a/util/intelp2m/platforms/mtl/template.go
+++ /dev/null
@@ -1,14 +0,0 @@
-package mtl
-
-import "review.coreboot.org/coreboot.git/util/intelp2m/platforms/common"
-
-// Group : "GPP_V", "GPP_C", "GPP_A", "GPP_E", "GPP_H", "GPP_F", "GPP_S", "GPP_B", "GPP_D",
-//         "GPD", "VGPIO_USB", "VGPIO_PCIE"
-
-// CheckKeyword - This function is used to filter parsed lines of the configuration file and
-// returns true if the keyword is contained in the line.
-// line : string from the configuration file
-func CheckKeyword(line string) bool {
-	isIncluded, _ := common.KeywordsCheck(line, "GPP_", "GPD", "VGPIO")
-	return isIncluded
-}
diff --git a/util/intelp2m/platforms/platforms.go b/util/intelp2m/platforms/platforms.go
index cb65903e8b..22f2d9d881 100644
--- a/util/intelp2m/platforms/platforms.go
+++ b/util/intelp2m/platforms/platforms.go
@@ -4,7 +4,6 @@ import (
 	"fmt"
 
 	"review.coreboot.org/coreboot.git/util/intelp2m/config/p2m"
-	"review.coreboot.org/coreboot.git/util/intelp2m/logs"
 	"review.coreboot.org/coreboot.git/util/intelp2m/platforms/adl"
 	"review.coreboot.org/coreboot.git/util/intelp2m/platforms/apl"
 	"review.coreboot.org/coreboot.git/util/intelp2m/platforms/cnl"
@@ -17,10 +16,10 @@ import (
 	"review.coreboot.org/coreboot.git/util/intelp2m/platforms/tgl"
 )
 
-type KeywordAction func(line string) bool
-
 type Constructor func(dw0, dw1 uint32) common.PlatformIf
 
+var ErrUnregisteredPlatform = fmt.Errorf("unregistered platform type %d", p2m.Config.Platform)
+
 var platformConstructorMap = map[p2m.PlatformType]Constructor{
 	p2m.Alder:      adl.GetPlatform,
 	p2m.Apollo:     apl.GetPlatform,
@@ -33,30 +32,30 @@ var platformConstructorMap = map[p2m.PlatformType]Constructor{
 	p2m.Lewisburg:  lbg.GetPlatform,
 }
 
-func GetKeywordChekingAction() KeywordAction {
-	actions := map[p2m.PlatformType]KeywordAction{
-		p2m.Alder:      adl.CheckKeyword,
-		p2m.Apollo:     apl.CheckKeyword,
-		p2m.Cannon:     cnl.CheckKeyword,
-		p2m.Sunrise:    snr.CheckKeyword,
-		p2m.Tiger:      tgl.CheckKeyword,
-		p2m.Jasper:     jsl.CheckKeyword,
-		p2m.Meteor:     mtl.CheckKeyword,
-		p2m.Emmitsburg: ebg.CheckKeyword,
-		p2m.Lewisburg:  lbg.CheckKeyword,
-	}
-	action, exist := actions[p2m.Config.Platform]
-	if !exist {
-		logs.Errorf("unregistered platform type %d", p2m.Config.Platform)
-		return nil
-	}
-	return action
+var GppMap = map[p2m.PlatformType][]string{
+	p2m.Alder:      adl.GPPGroups,
+	p2m.Apollo:     apl.GPPGroups,
+	p2m.Cannon:     cnl.GPPGroups,
+	p2m.Sunrise:    snr.GPPGroups,
+	p2m.Tiger:      tgl.GPPGroups,
+	p2m.Jasper:     jsl.GPPGroups,
+	p2m.Meteor:     mtl.GPPGroups,
+	p2m.Emmitsburg: ebg.GPPGroups,
+	p2m.Lewisburg:  lbg.GPPGroups,
 }
 
 func GetConstructor() (Constructor, error) {
 	constructor, exist := platformConstructorMap[p2m.Config.Platform]
 	if !exist {
-		return nil, fmt.Errorf("unregistered platform type %d", p2m.Config.Platform)
+		return nil, ErrUnregisteredPlatform
 	}
 	return constructor, nil
 }
+
+func GetGPPGroups() ([]string, error) {
+	groups, exist := GppMap[p2m.Config.Platform]
+	if !exist {
+		return nil, ErrUnregisteredPlatform
+	}
+	return groups, nil
+}
diff --git a/util/intelp2m/platforms/snr/macro.go b/util/intelp2m/platforms/snr/macro.go
index 7250608374..3550177976 100644
--- a/util/intelp2m/platforms/snr/macro.go
+++ b/util/intelp2m/platforms/snr/macro.go
@@ -14,6 +14,10 @@ const (
 	DW1Mask uint32 = 0b11111101111111111100001111111111
 )
 
+// "GPP_A", "GPP_B", "GPP_F", "GPP_C", "GPP_D", "GPP_E", "GPD", "GPP_I", "GPP_J", "GPP_G",
+// "GPP_H", "GPP_L"
+var GPPGroups = []string{"GPP_", "GPD"}
+
 var remapping = common.ResetSources{
 	0b00: bits.RstCfgRSMRST << bits.DW0PadRstCfg,
 	0b01: bits.RstCfgDEEP << bits.DW0PadRstCfg,
diff --git a/util/intelp2m/platforms/snr/template.go b/util/intelp2m/platforms/snr/template.go
deleted file mode 100644
index 22f477e62c..0000000000
--- a/util/intelp2m/platforms/snr/template.go
+++ /dev/null
@@ -1,12 +0,0 @@
-package snr
-
-import "review.coreboot.org/coreboot.git/util/intelp2m/platforms/common"
-
-// CheckKeyword() parses lines of the configuration file and returns true if the keyword is
-// contained in the line
-// "GPP_A", "GPP_B", "GPP_F", "GPP_C", "GPP_D", "GPP_E", "GPD", "GPP_I", "GPP_J",
-// "GPP_K", "GPP_G", "GPP_H", "GPP_L"
-func CheckKeyword(line string) bool {
-	included, _ := common.KeywordsCheck(line, "GPP_", "GPD")
-	return included
-}
diff --git a/util/intelp2m/platforms/tgl/macro.go b/util/intelp2m/platforms/tgl/macro.go
index 6e63167b2a..7bd49a87bd 100644
--- a/util/intelp2m/platforms/tgl/macro.go
+++ b/util/intelp2m/platforms/tgl/macro.go
@@ -14,6 +14,10 @@ const (
 	DW1Mask = 0b11111101111111111100001111111111
 )
 
+// "GPP_A", "GPP_R", "GPP_B", "GPP_D", "GPP_C", "GPP_S", "GPP_G", "GPD", "GPP_E", "GPP_F",
+// "GPP_H", "GPP_J", "GPP_K", "GPP_I", "VGPIO_USB", "VGPIO_PCIE"
+var GPPGroups = []string{"GPP_", "GPD", "VGPIO"}
+
 var remapping = common.ResetSources{
 	0b00: bits.RstCfgRSMRST << bits.DW0PadRstCfg,
 	0b01: bits.RstCfgDEEP << bits.DW0PadRstCfg,
diff --git a/util/intelp2m/platforms/tgl/template.go b/util/intelp2m/platforms/tgl/template.go
deleted file mode 100644
index f6a0bcd4d0..0000000000
--- a/util/intelp2m/platforms/tgl/template.go
+++ /dev/null
@@ -1,14 +0,0 @@
-package tgl
-
-import "review.coreboot.org/coreboot.git/util/intelp2m/platforms/common"
-
-// Group : "GPP_A", "GPP_R", "GPP_B", "GPP_D", "GPP_C", "GPP_S", "GPP_G", "GPD", "GPP_E",
-//         "GPP_F", "GPP_H", "GPP_J", "GPP_K", "GPP_I", "VGPIO_USB", "VGPIO_PCIE"
-
-// CheckKeyword - This function is used to filter parsed lines of the configuration file
-// and returns true if the keyword is contained in the line.
-// line : string from the configuration file
-func CheckKeyword(line string) bool {
-	isIncluded, _ := common.KeywordsCheck(line, "GPP_", "GPD", "VGPIO")
-	return isIncluded
-}

From 864dea8d21b8434770826732ae5ac7a6137e6764 Mon Sep 17 00:00:00 2001
From: Maxim Polyakov <max.senia.poliak@gmail.com>
Date: Wed, 25 Dec 2024 22:18:01 +0300
Subject: [PATCH 0261/3886] intelp2m/platforms: Rename macro.go to match module
 name

Change-Id: I5eeb24d668a8d478720ecccf1522238e70dd8a71
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85770
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 util/intelp2m/platforms/adl/{macro.go => adl.go} | 0
 util/intelp2m/platforms/apl/{macro.go => apl.go} | 0
 util/intelp2m/platforms/cnl/{macro.go => cnl.go} | 0
 util/intelp2m/platforms/ebg/{macro.go => ebg.go} | 0
 util/intelp2m/platforms/jsl/{macro.go => jsl.go} | 0
 util/intelp2m/platforms/lbg/{macro.go => lbg.go} | 0
 util/intelp2m/platforms/mtl/{macro.go => mtl.go} | 0
 util/intelp2m/platforms/snr/{macro.go => snr.go} | 0
 util/intelp2m/platforms/tgl/{macro.go => tgl.go} | 0
 9 files changed, 0 insertions(+), 0 deletions(-)
 rename util/intelp2m/platforms/adl/{macro.go => adl.go} (100%)
 rename util/intelp2m/platforms/apl/{macro.go => apl.go} (100%)
 rename util/intelp2m/platforms/cnl/{macro.go => cnl.go} (100%)
 rename util/intelp2m/platforms/ebg/{macro.go => ebg.go} (100%)
 rename util/intelp2m/platforms/jsl/{macro.go => jsl.go} (100%)
 rename util/intelp2m/platforms/lbg/{macro.go => lbg.go} (100%)
 rename util/intelp2m/platforms/mtl/{macro.go => mtl.go} (100%)
 rename util/intelp2m/platforms/snr/{macro.go => snr.go} (100%)
 rename util/intelp2m/platforms/tgl/{macro.go => tgl.go} (100%)

diff --git a/util/intelp2m/platforms/adl/macro.go b/util/intelp2m/platforms/adl/adl.go
similarity index 100%
rename from util/intelp2m/platforms/adl/macro.go
rename to util/intelp2m/platforms/adl/adl.go
diff --git a/util/intelp2m/platforms/apl/macro.go b/util/intelp2m/platforms/apl/apl.go
similarity index 100%
rename from util/intelp2m/platforms/apl/macro.go
rename to util/intelp2m/platforms/apl/apl.go
diff --git a/util/intelp2m/platforms/cnl/macro.go b/util/intelp2m/platforms/cnl/cnl.go
similarity index 100%
rename from util/intelp2m/platforms/cnl/macro.go
rename to util/intelp2m/platforms/cnl/cnl.go
diff --git a/util/intelp2m/platforms/ebg/macro.go b/util/intelp2m/platforms/ebg/ebg.go
similarity index 100%
rename from util/intelp2m/platforms/ebg/macro.go
rename to util/intelp2m/platforms/ebg/ebg.go
diff --git a/util/intelp2m/platforms/jsl/macro.go b/util/intelp2m/platforms/jsl/jsl.go
similarity index 100%
rename from util/intelp2m/platforms/jsl/macro.go
rename to util/intelp2m/platforms/jsl/jsl.go
diff --git a/util/intelp2m/platforms/lbg/macro.go b/util/intelp2m/platforms/lbg/lbg.go
similarity index 100%
rename from util/intelp2m/platforms/lbg/macro.go
rename to util/intelp2m/platforms/lbg/lbg.go
diff --git a/util/intelp2m/platforms/mtl/macro.go b/util/intelp2m/platforms/mtl/mtl.go
similarity index 100%
rename from util/intelp2m/platforms/mtl/macro.go
rename to util/intelp2m/platforms/mtl/mtl.go
diff --git a/util/intelp2m/platforms/snr/macro.go b/util/intelp2m/platforms/snr/snr.go
similarity index 100%
rename from util/intelp2m/platforms/snr/macro.go
rename to util/intelp2m/platforms/snr/snr.go
diff --git a/util/intelp2m/platforms/tgl/macro.go b/util/intelp2m/platforms/tgl/tgl.go
similarity index 100%
rename from util/intelp2m/platforms/tgl/macro.go
rename to util/intelp2m/platforms/tgl/tgl.go

From 6789dea1d60e4c465020f555ecdedbfc42152c4f Mon Sep 17 00:00:00 2001
From: Alexander Couzens <lynxis@fe80.eu>
Date: Fri, 1 Dec 2023 15:43:28 +0000
Subject: [PATCH 0262/3886] util/intelp2m/platforms: Add support for Elkhart
 Lake

TEST:
- 'make test' = PASS;
- 'intelp2m -p ehl -file parser/testlog/inteltool_test.log' = no errors.

Change-Id: I0f60d182bc5cc3d0d1d1177fbda0cfe8e2279e46
Signed-off-by: Alexander Couzens <lynxis@fe80.eu>
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84191
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 Documentation/util/intelp2m/index.md    |   1 +
 util/intelp2m/cli/options.go            |   3 +-
 util/intelp2m/config/p2m/config.go      |   2 +
 util/intelp2m/platforms/ehl/ehl.go      |  54 +++++++++++++
 util/intelp2m/platforms/ehl/ehl_test.go | 103 ++++++++++++++++++++++++
 util/intelp2m/platforms/platforms.go    |   3 +
 util/intelp2m/version.txt               |   2 +-
 7 files changed, 166 insertions(+), 2 deletions(-)
 create mode 100644 util/intelp2m/platforms/ehl/ehl.go
 create mode 100644 util/intelp2m/platforms/ehl/ehl_test.go

diff --git a/Documentation/util/intelp2m/index.md b/Documentation/util/intelp2m/index.md
index dd7994e19c..758f8c4d72 100644
--- a/Documentation/util/intelp2m/index.md
+++ b/Documentation/util/intelp2m/index.md
@@ -73,6 +73,7 @@ The utility supports the following chipsets from Intel:
 * `apl` - Apollo Lake SoC
 * `cnl` - CannonLake-LP or Whiskeylake/Coffeelake/Cometlake-U SoC
 * `ebg` - Emmitsburg PCH with Xeon SP
+* `ehl` - Elkhart Lake SoC
 * `jsl` - Jasper Lake SoC
 * `lbg` - Lewisburg PCH with Xeon SP
 * `mtl` - MeteorLake SoC
diff --git a/util/intelp2m/cli/options.go b/util/intelp2m/cli/options.go
index 1d4e5ec030..0486efa04c 100644
--- a/util/intelp2m/cli/options.go
+++ b/util/intelp2m/cli/options.go
@@ -12,11 +12,12 @@ import (
 var name = filepath.Base(os.Args[0])
 
 const usagePlatform = `usage: -platform <type>
-    type: adl | apl | cnl | ebg | jsl | lbg | mtl | snr | tgl | ?
+    type: adl | apl | cnl | ebg | ehl | jsl | lbg | mtl | snr | tgl | ?
         adl - Alder Lake PCH
         apl - Apollo Lake SoC
         cnl - CannonLake-LP or Whiskeylake/Coffeelake/Cometlake-U SoC
         ebg - Emmitsburg PCH with Xeon SP
+        ehl - Elkhart Lake SoC
         jsl - Jasper Lake SoC
         lbg - Lewisburg PCH with Xeon SP
         mtl - MeteorLake SoC
diff --git a/util/intelp2m/config/p2m/config.go b/util/intelp2m/config/p2m/config.go
index 4271200c09..6d3aa1be23 100644
--- a/util/intelp2m/config/p2m/config.go
+++ b/util/intelp2m/config/p2m/config.go
@@ -17,6 +17,7 @@ const (
 	Tiger
 	Meteor
 	Emmitsburg
+	Elkhart
 )
 
 const (
@@ -36,6 +37,7 @@ var platforms = map[string]PlatformType{
 	"jsl": Jasper,
 	"mtl": Meteor,
 	"ebg": Emmitsburg,
+	"ehl": Elkhart,
 }
 
 var fields = map[string]FieldType{
diff --git a/util/intelp2m/platforms/ehl/ehl.go b/util/intelp2m/platforms/ehl/ehl.go
new file mode 100644
index 0000000000..d48b0165a9
--- /dev/null
+++ b/util/intelp2m/platforms/ehl/ehl.go
@@ -0,0 +1,54 @@
+package ehl
+
+import (
+	"review.coreboot.org/coreboot.git/util/intelp2m/logs"
+	"review.coreboot.org/coreboot.git/util/intelp2m/platforms/apl"
+	"review.coreboot.org/coreboot.git/util/intelp2m/platforms/common"
+)
+
+const (
+	DW0Mask = (0b1 << 27) | (0b1111 << 14) | 0b11111100
+	DW1Mask = 0b11111111111111000000000011111111
+)
+
+var GPPGroups = []string{"GPP_", "GPD_", "GPIO_", "VGPIO_"}
+
+type BasePlatform struct {
+	// based on the Apollo Lake SoC
+	apl.BasePlatform
+}
+
+func InitBasePlatform(dw0Val, dw0Mask uint32, dw1Val, dw1Mask uint32) BasePlatform {
+	return BasePlatform{apl.InitBasePlatform(dw0Val, dw0Mask, dw1Val, dw1Mask)}
+}
+
+func GetPlatform(dw0, dw1 uint32) common.PlatformIf {
+	p := InitBasePlatform(dw0, DW0Mask, dw1, DW1Mask)
+	return &p
+}
+
+// Override BasePlatform.Pull()
+func (p *BasePlatform) Pull(m *common.Macro) {
+	dw1 := p.GetRegisterDW1()
+	var pull = map[uint32]string{
+		0b0000: "NONE",
+		0b0001: "DN_1K",
+		0b0010: "DN_5K",
+		0b0100: "DN_20K",
+		0b1000: "UP_1K_5K_20K",
+		0b1001: "UP_1K",
+		0b1010: "UP_5K",
+		0b1011: "UP_1K_5K",
+		0b1100: "UP_20K",
+		0b1101: "UP_1K_20K",
+		0b1110: "UP_5K_20K",
+		0b1111: "NATIVE",
+	}
+	term, valid := pull[dw1.GetTermination()]
+	if !valid {
+		term = "ERROR"
+		logs.Errorf("%s: DW1 %s: invalid termination value 0b%b",
+			dw1, m.GetPadId(), dw1.GetTermination())
+	}
+	m.Separator().Add(term)
+}
diff --git a/util/intelp2m/platforms/ehl/ehl_test.go b/util/intelp2m/platforms/ehl/ehl_test.go
new file mode 100644
index 0000000000..4294cfcca4
--- /dev/null
+++ b/util/intelp2m/platforms/ehl/ehl_test.go
@@ -0,0 +1,103 @@
+package ehl_test
+
+import (
+	"testing"
+
+	"review.coreboot.org/coreboot.git/util/intelp2m/config/p2m"
+	"review.coreboot.org/coreboot.git/util/intelp2m/platforms/common"
+	"review.coreboot.org/coreboot.git/util/intelp2m/platforms/test"
+)
+
+func TestGenMacro(t *testing.T) {
+	p2m.Config.Platform = p2m.Elkhart
+	test.Suite{
+		{
+			Pad: test.Pad{ID: "GPIO_1", DW0: 0x11111111, DW1: 0x11111111, Ownership: common.Driver},
+			Macro: test.Macro{
+				Short: "PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_1, DN_20K, PWROK, NF4, Tx1RxDCRx1, DISPUPD),",
+				Long:  "_PAD_CFG_STRUCT(GPIO_1, PAD_FUNC(NF4) | PAD_IRQ_ROUTE(IOAPIC) | PAD_BUF(TX_DISABLE) | (1 << 28) | 1, PAD_PULL(DN_20K) | PAD_IOSSTATE(Tx1RxDCRx1) | PAD_IOSTERM(DISPUPD) | PAD_CFG_OWN_GPIO(DRIVER)),",
+			},
+		},
+		{
+			Pad: test.Pad{ID: "GPIO_2", DW0: 0x22222222, DW1: 0x22222222, Ownership: common.Acpi},
+			Macro: test.Macro{
+				Short: "PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_2, 0, PWROK, UP_1K_5K_20K, HIZCRx1, ENPD),",
+				Long:  "_PAD_CFG_STRUCT(GPIO_2, PAD_FUNC(GPIO) | PAD_TRIG(EDGE_SINGLE) | PAD_IRQ_ROUTE(NMI) | PAD_BUF(RX_DISABLE) | (1 << 29) | (1 << 1), PAD_CFG1_TOL_1V8PAD_PULL(UP_1K_5K_20K) | PAD_IOSSTATE(HIZCRx1) | PAD_IOSTERM(ENPD)),",
+			},
+		},
+		{
+			Pad: test.Pad{ID: "GPIO_3", DW0: 0x44444444, DW1: 0x44444444, Ownership: common.Driver},
+			Macro: test.Macro{
+				Short: "PAD_CFG_NF_IOSSTATE(GPIO_3, DN_1K, DEEP, NF1, Tx0RxDCRx0),",
+				Long:  "_PAD_CFG_STRUCT(GPIO_3, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_IRQ_ROUTE(SMI), PAD_PULL(DN_1K) | PAD_IOSSTATE(Tx0RxDCRx0) | PAD_CFG_OWN_GPIO(DRIVER)),",
+			},
+		},
+		{
+			Pad: test.Pad{ID: "GPIO_4", DW0: 0x88888888, DW1: 0x88888888, Ownership: common.Acpi},
+			Macro: test.Macro{
+				Short: "PAD_CFG_NF_IOSSTATE(GPIO_4, DN_5K, PLTRST, NF2, Tx0RxDCRx1),",
+				Long:  "_PAD_CFG_STRUCT(GPIO_4, PAD_FUNC(NF2) | PAD_RESET(PLTRST) | PAD_IRQ_ROUTE(SCI) | PAD_RX_POL(INVERT), PAD_PULL(DN_5K) | PAD_IOSSTATE(Tx0RxDCRx1)),",
+			},
+		},
+	}.Run(t, "INTEL-ELKHART-LAKE-PCH/SLIDING-ONE-IN-NIBBLE-TEST")
+	test.Suite{
+		{
+			Pad: test.Pad{ID: "GPIO_5", DW0: 0xEEEEEEEE, DW1: 0xEEEEEEEE, Ownership: common.Driver},
+			Macro: test.Macro{
+				Short: "PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_5, UP_1K_5K, RSMRST, NF3, ERROR, ENPD),",
+				Long:  "_PAD_CFG_STRUCT(GPIO_5, PAD_FUNC(NF3) | PAD_RESET(RSMRST) | PAD_TRIG(EDGE_BOTH) | PAD_IRQ_ROUTE(SCI) | PAD_IRQ_ROUTE(SMI) | PAD_IRQ_ROUTE(NMI) | PAD_RX_POL(INVERT) | PAD_BUF(RX_DISABLE) | (1 << 29) | (1 << 1), PAD_CFG1_TOL_1V8PAD_PULL(UP_1K_5K) | PAD_IOSSTATE(ERROR) | PAD_IOSTERM(ENPD) | PAD_CFG_OWN_GPIO(DRIVER)),",
+			},
+		},
+		{
+			Pad: test.Pad{ID: "GPIO_6", DW0: 0xDDDDDDDD, DW1: 0xDDDDDDDD, Ownership: common.Acpi},
+			Macro: test.Macro{
+				Short: "PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_6, ERROR, RSMRST, NF7, HIZCRx0, DISPUPD),",
+				Long:  "_PAD_CFG_STRUCT(GPIO_6, PAD_FUNC(NF7) | PAD_RESET(RSMRST) | PAD_TRIG(OFF) | PAD_IRQ_ROUTE(IOAPIC) | PAD_IRQ_ROUTE(SCI) | PAD_IRQ_ROUTE(SMI) | PAD_RX_POL(INVERT) | PAD_BUF(TX_DISABLE) | (1 << 28) | 1, PAD_PULL(ERROR) | PAD_IOSSTATE(HIZCRx0) | PAD_IOSTERM(DISPUPD)),",
+			},
+		},
+		{
+			Pad: test.Pad{ID: "GPIO_7", DW0: 0xBBBBBBBB, DW1: 0xBBBBBBBB, Ownership: common.Driver},
+			Macro: test.Macro{
+				Short: "PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_7, UP_5K_20K, PLTRST, NF6, ERROR, ENPU),",
+				Long:  "_PAD_CFG_STRUCT(GPIO_7, PAD_FUNC(NF6) | PAD_RESET(PLTRST) | PAD_TRIG(EDGE_SINGLE) | PAD_IRQ_ROUTE(IOAPIC) | PAD_IRQ_ROUTE(SCI) | PAD_IRQ_ROUTE(NMI) | PAD_RX_POL(INVERT) | PAD_BUF(TX_RX_DISABLE) | (1 << 29) | (1 << 28) | (1 << 1) | 1, PAD_CFG1_TOL_1V8PAD_PULL(UP_5K_20K) | PAD_IOSSTATE(ERROR) | PAD_IOSTERM(ENPU) | PAD_CFG_OWN_GPIO(DRIVER)),",
+			},
+		},
+		{
+			Pad: test.Pad{ID: "GPIO_8", DW0: 0x77777777, DW1: 0x77777777, Ownership: common.Acpi},
+			Macro: test.Macro{
+				Short: "PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_8, UP_1K_20K, DEEP, NF5, ERROR, ENPU),",
+				Long:  "_PAD_CFG_STRUCT(GPIO_8, PAD_FUNC(NF5) | PAD_RESET(DEEP) | PAD_TRIG(EDGE_BOTH) | PAD_IRQ_ROUTE(IOAPIC) | PAD_IRQ_ROUTE(SMI) | PAD_IRQ_ROUTE(NMI) | PAD_BUF(TX_RX_DISABLE) | (1 << 29) | (1 << 28) | (1 << 1) | 1, PAD_CFG1_TOL_1V8PAD_PULL(UP_1K_20K) | PAD_IOSSTATE(ERROR) | PAD_IOSTERM(ENPU)),",
+			},
+		},
+	}.Run(t, "INTEL-ELKHART-LAKE-PCH/SLIDING-ZERO-IN-NIBBLE-TEST")
+	test.Suite{
+		{
+			Pad: test.Pad{ID: "GPIO_9", DW0: 0x33333333, DW1: 0x33333333, Ownership: common.Driver},
+			Macro: test.Macro{
+				Short: "PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_9, UP_20K, PWROK, NF4, ERROR, ENPU),",
+				Long:  "_PAD_CFG_STRUCT(GPIO_9, PAD_FUNC(NF4) | PAD_TRIG(EDGE_SINGLE) | PAD_IRQ_ROUTE(IOAPIC) | PAD_IRQ_ROUTE(NMI) | PAD_BUF(TX_RX_DISABLE) | (1 << 29) | (1 << 28) | (1 << 1) | 1, PAD_CFG1_TOL_1V8PAD_PULL(UP_20K) | PAD_IOSSTATE(ERROR) | PAD_IOSTERM(ENPU) | PAD_CFG_OWN_GPIO(DRIVER)),",
+			},
+		},
+		{
+			Pad: test.Pad{ID: "GPIO_10", DW0: 0x66666666, DW1: 0x66666666, Ownership: common.Acpi},
+			Macro: test.Macro{
+				Short: "PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_10, UP_1K, DEEP, NF1, TxDRxE, ENPD),",
+				Long:  "_PAD_CFG_STRUCT(GPIO_10, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(EDGE_BOTH) | PAD_IRQ_ROUTE(SMI) | PAD_IRQ_ROUTE(NMI) | PAD_BUF(RX_DISABLE) | (1 << 29) | (1 << 1), PAD_CFG1_TOL_1V8PAD_PULL(UP_1K) | PAD_IOSSTATE(TxDRxE) | PAD_IOSTERM(ENPD)),",
+			},
+		},
+		{
+			Pad: test.Pad{ID: "GPIO_11", DW0: 0xCCCCCCCC, DW1: 0xCCCCCCCC, Ownership: common.Driver},
+			Macro: test.Macro{
+				Short: "PAD_CFG_NF_IOSSTATE(GPIO_11, ERROR, RSMRST, NF3, Tx1RxDCRx0),",
+				Long:  "_PAD_CFG_STRUCT(GPIO_11, PAD_FUNC(NF3) | PAD_RESET(RSMRST) | PAD_TRIG(OFF) | PAD_IRQ_ROUTE(SCI) | PAD_IRQ_ROUTE(SMI) | PAD_RX_POL(INVERT), PAD_PULL(ERROR) | PAD_IOSSTATE(Tx1RxDCRx0) | PAD_CFG_OWN_GPIO(DRIVER)),",
+			},
+		},
+		{
+			Pad: test.Pad{ID: "GPIO_12", DW0: 0x99999999, DW1: 0x99999999, Ownership: common.Acpi},
+			Macro: test.Macro{
+				Short: "PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_12, ERROR, PLTRST, NF6, Tx1RxE, DISPUPD),",
+				Long:  "_PAD_CFG_STRUCT(GPIO_12, PAD_FUNC(NF6) | PAD_RESET(PLTRST) | PAD_IRQ_ROUTE(IOAPIC) | PAD_IRQ_ROUTE(SCI) | PAD_RX_POL(INVERT) | PAD_BUF(TX_DISABLE) | (1 << 28) | 1, PAD_PULL(ERROR) | PAD_IOSSTATE(Tx1RxE) | PAD_IOSTERM(DISPUPD)),",
+			},
+		},
+	}.Run(t, "INTEL-ELKHART-LAKE-PCH/SLIDING-ONE-ONE-IN-NIBBLE-TEST")
+}
diff --git a/util/intelp2m/platforms/platforms.go b/util/intelp2m/platforms/platforms.go
index 22f2d9d881..2ac1733670 100644
--- a/util/intelp2m/platforms/platforms.go
+++ b/util/intelp2m/platforms/platforms.go
@@ -9,6 +9,7 @@ import (
 	"review.coreboot.org/coreboot.git/util/intelp2m/platforms/cnl"
 	"review.coreboot.org/coreboot.git/util/intelp2m/platforms/common"
 	"review.coreboot.org/coreboot.git/util/intelp2m/platforms/ebg"
+	"review.coreboot.org/coreboot.git/util/intelp2m/platforms/ehl"
 	"review.coreboot.org/coreboot.git/util/intelp2m/platforms/jsl"
 	"review.coreboot.org/coreboot.git/util/intelp2m/platforms/lbg"
 	"review.coreboot.org/coreboot.git/util/intelp2m/platforms/mtl"
@@ -30,6 +31,7 @@ var platformConstructorMap = map[p2m.PlatformType]Constructor{
 	p2m.Meteor:     mtl.GetPlatform,
 	p2m.Emmitsburg: ebg.GetPlatform,
 	p2m.Lewisburg:  lbg.GetPlatform,
+	p2m.Elkhart:    ehl.GetPlatform,
 }
 
 var GppMap = map[p2m.PlatformType][]string{
@@ -42,6 +44,7 @@ var GppMap = map[p2m.PlatformType][]string{
 	p2m.Meteor:     mtl.GPPGroups,
 	p2m.Emmitsburg: ebg.GPPGroups,
 	p2m.Lewisburg:  lbg.GPPGroups,
+	p2m.Elkhart:    ehl.GPPGroups,
 }
 
 func GetConstructor() (Constructor, error) {
diff --git a/util/intelp2m/version.txt b/util/intelp2m/version.txt
index c239c60cba..95e3ba8192 100644
--- a/util/intelp2m/version.txt
+++ b/util/intelp2m/version.txt
@@ -1 +1 @@
-1.5
+2.5

From 77cd0ce76843a6ced4a6c23b397c23053fc87ebc Mon Sep 17 00:00:00 2001
From: Elyes Haouas <ehaouas@noos.fr>
Date: Thu, 27 Feb 2025 12:38:30 +0100
Subject: [PATCH 0263/3886] coreboot-sdk: Remove unnecessary files

Reduces the size of the Docker image by removing all unnecessary files.

Change-Id: Ib8c658799217c3b6595e3b5fce8f5c8238054c45
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86617
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
---
 util/docker/coreboot-sdk/Dockerfile | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/util/docker/coreboot-sdk/Dockerfile b/util/docker/coreboot-sdk/Dockerfile
index 6c3a06b571..59013d6ac1 100644
--- a/util/docker/coreboot-sdk/Dockerfile
+++ b/util/docker/coreboot-sdk/Dockerfile
@@ -90,7 +90,8 @@ RUN \
 		xfonts-unifont \
 		xz-utils \
 		zlib1g-dev \
-	&& apt-get clean
+	&& apt-get clean \
+	&& rm -rf /var/lib/apt/lists/*
 
 RUN \
 	cd /tmp && \

From 3c96687c2c2ac3fda183c171337e7d4ae3ff4e59 Mon Sep 17 00:00:00 2001
From: Patrick Rudolph <patrick.rudolph@9elements.com>
Date: Fri, 28 Feb 2025 08:19:00 +0100
Subject: [PATCH 0264/3886] MAINTAINERS: Drop Patrick Rudolph from Xeon-SP

It's too broken to be maintained.

Change-Id: I2c6492f4e37b21bdc2b8d413fb30beaf16403345
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86641
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
---
 MAINTAINERS | 1 -
 1 file changed, 1 deletion(-)

diff --git a/MAINTAINERS b/MAINTAINERS
index 2ed4e227f3..8a2b21f869 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -964,7 +964,6 @@ M:	Johnny Lin <Johnny_Lin@wiwynn.com>
 M:	Tim Chu <Tim.Chu@quantatw.com>
 M:	Christian Walter <christian.walter@9elements.com>
 M:	Shuo Liu <shuo.liu@intel.com>
-M:	Patrick Rudolph <patrick.rudolph@9elements.com>
 M:	Lean Sheng Tan <sheng.tan@9elements.com>
 S:	Supported
 F:	src/soc/intel/xeon_sp/

From 0e775bc390fc4dd7499ba885e0fe609587c62646 Mon Sep 17 00:00:00 2001
From: Brandon Weeks <bweeks@google.com>
Date: Mon, 3 Feb 2025 16:28:28 -0800
Subject: [PATCH 0265/3886] mb/cwwk/adl: Fix HDMI, PCIe CLKREQ, EC, TPM

- Update VBT to fix HDMI
- Enable ITE environment controller
- Enable PTT fTPM
- Disable s0ix, it never worked and will crash if used
- Set CLKREQ# based on register values from vendor firmware
- Set pmc_gpe0_dw{0-3} to fix "Duplicate GPE DW register values"

Change-Id: I9365e76c593b7e4a334dcdc5ecd46da253e14716
Signed-off-by: Brandon Weeks <bweeks@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86260
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
---
 src/mainboard/cwwk/adl/Kconfig       |   2 +
 src/mainboard/cwwk/adl/data.vbt      | Bin 8704 -> 9216 bytes
 src/mainboard/cwwk/adl/devicetree.cb |  61 ++++++++++++++++++---------
 3 files changed, 42 insertions(+), 21 deletions(-)

diff --git a/src/mainboard/cwwk/adl/Kconfig b/src/mainboard/cwwk/adl/Kconfig
index 7f6c33a2b1..c8dbd04dd7 100644
--- a/src/mainboard/cwwk/adl/Kconfig
+++ b/src/mainboard/cwwk/adl/Kconfig
@@ -5,10 +5,12 @@ if BOARD_CWWK_ADL_N
 config BOARD_SPECIFIC_OPTIONS
 	def_bool y
 	select BOARD_ROMSIZE_KB_16384
+	select CRB_TPM
 	select DRIVERS_UART_8250IO
 	select FSP_TYPE_IOT
 	select HAVE_ACPI_RESUME
 	select HAVE_ACPI_TABLES
+	select HAVE_INTEL_PTT
 	select INTEL_GMA_HAVE_VBT
 	select SOC_INTEL_ALDERLAKE_PCH_N
 	select SUPERIO_ITE_IT8613E
diff --git a/src/mainboard/cwwk/adl/data.vbt b/src/mainboard/cwwk/adl/data.vbt
index 2a6c2076e34473c2213b05d306a53e4ea09f2c02..b97ff679580afd4e6b8b3d870e8b27752b0a0a37 100644
GIT binary patch
delta 461
zcmZXPy-Nc@5XEQrK8)Mk8I7b-5}QjUDaFPJ3c)6Sfe=NB*qAmTcwi+ccnmSE)*>2?
z*yaQgKd@2k6zs%GQwyi>&VwKh{C4*Z@6E98oLk<{8u^J6DsoQ_dqvwIF-o7_{D)Fx
z1tbW?)1o}k6jCQD@Q!dq$Y;V)p-xw8WZN{$uVQSA!V*1Hp{t8|JBmeNi7UV>7Z1{)
zh{9ZSBG*WK77<3nSO4par@+@td_zP=>~j+z1S*V{kPc&;H)VDzQs~AT(Y#O6zwQ59
z;y=Ro&bM+LUt2N@Y-ySGj3_0M{`I6?_eJtrH56@t2G|CBpaqV=G3bCUxB-vg1-yYC
z_yU6~e5h5ptEE%lD0N4Qg&y#XuJ}T~l#?2J#sQxi%6H6N>9<oIQ!I1Ms&L&L@z1S=
Jv|lry#ScIhR6YOz

delta 405
zcmY+8F-XHe6o%isOHNzRM2pg;B?TdiLly-=C4+_Hpp&>sg(9MpgE-n%w9xuyXVF2C
z;N%jJs)Hap2)a5;X9vMQNeBDG_wL@${~y<^HJ92&`?pf1Kv)+#fouQJBt3VkJ!8m;
ziDi*%L&vNvB41kU%PsqXMGxELx?ZW`Qlfl1DW;G;&hD5xq_;X^G$*5~IGg!ia==^b
zS4WV86H@(uRi*DDwkI2?CJ7>y40x@6wLoOx#MJIrvsn58#4hAYm2;G=*t+tr%CcpA
zDd~xwF%Dr5>QO%p8ratDJZ*wqun!Kw5fE?&&cO}116}X}KEN0F2DygBdO@!BlywP3
hY@M>2*79mMq-W1ZGv-7^_rsCl6*+KLqfcjf{0~<IK$QRh

diff --git a/src/mainboard/cwwk/adl/devicetree.cb b/src/mainboard/cwwk/adl/devicetree.cb
index 72a1a980df..0502434683 100644
--- a/src/mainboard/cwwk/adl/devicetree.cb
+++ b/src/mainboard/cwwk/adl/devicetree.cb
@@ -1,6 +1,8 @@
 chip soc/intel/alderlake
 
-	register "s0ix_enable" = "true"
+	register "pmc_gpe0_dw0" = "GPP_B"
+	register "pmc_gpe0_dw1" = "GPP_D"
+	register "pmc_gpe0_dw2" = "GPP_E"
 
 	register "usb2_ports[0]" = "USB2_PORT_SHORT(OC_SKIP)"
 	register "usb2_ports[1]" = "USB2_PORT_SHORT(OC_SKIP)"
@@ -14,45 +16,49 @@ chip soc/intel/alderlake
 	register "pch_pcie_rp[PCH_RP(1)]" = "{
 		.clk_src = 0,
 		.clk_req = 0,
-		.flags = PCIE_RP_LTR | PCIE_RP_AER,
+		.flags = PCIE_RP_AER | PCIE_RP_CLK_REQ_DETECT,
 	}"
 
 	register "pch_pcie_rp[PCH_RP(7)]" = "{
 		.clk_src = 1,
-		.flags = PCIE_RP_LTR | PCIE_RP_AER | PCIE_RP_CLK_REQ_UNUSED | PCIE_RP_BUILT_IN,
-		.pcie_rp_aspm = ASPM_DISABLE,
+		.clk_req = 1,
+		.flags = PCIE_RP_AER | PCIE_RP_CLK_REQ_DETECT | PCIE_RP_BUILT_IN,
+		.pcie_rp_aspm = ASPM_L0S,
 	}"
 
 	register "pch_pcie_rp[PCH_RP(9)]" = "{
 		.clk_src = 2,
-		.flags = PCIE_RP_LTR | PCIE_RP_AER | PCIE_RP_CLK_REQ_UNUSED | PCIE_RP_BUILT_IN,
-		.pcie_rp_aspm = ASPM_DISABLE,
+		.clk_req = 2,
+		.flags = PCIE_RP_AER | PCIE_RP_CLK_REQ_DETECT | PCIE_RP_BUILT_IN,
+		.pcie_rp_aspm = ASPM_L0S,
 	}"
 
 	register "pch_pcie_rp[PCH_RP(10)]" = "{
 		.clk_src = 3,
-		.flags = PCIE_RP_LTR | PCIE_RP_AER | PCIE_RP_CLK_REQ_UNUSED | PCIE_RP_BUILT_IN,
-		.pcie_rp_aspm = ASPM_DISABLE,
+		.clk_req = 3,
+		.flags = PCIE_RP_AER | PCIE_RP_CLK_REQ_DETECT | PCIE_RP_BUILT_IN,
+		.pcie_rp_aspm = ASPM_L0S,
 	}"
 
 	register "pch_pcie_rp[PCH_RP(11)]" = "{
 		.clk_src = 4,
-		.flags = PCIE_RP_LTR | PCIE_RP_AER | PCIE_RP_CLK_REQ_UNUSED | PCIE_RP_BUILT_IN,
-		.pcie_rp_aspm = ASPM_DISABLE,
+		.flags = PCIE_RP_AER | PCIE_RP_CLK_REQ_UNUSED | PCIE_RP_BUILT_IN,
+		.pcie_rp_aspm = ASPM_L0S,
 	}"
 
 	register "pch_pcie_rp[PCH_RP(12)]" = "{
 		.clk_src = 4,
-		.flags = PCIE_RP_LTR | PCIE_RP_AER | PCIE_RP_CLK_REQ_UNUSED,
-		.pcie_rp_aspm = ASPM_DISABLE,
+		.flags = PCIE_RP_AER | PCIE_RP_CLK_REQ_UNUSED | PCIE_RP_BUILT_IN,
+		.pcie_rp_aspm = ASPM_L0S,
 	}"
 
-	# Enable EDP in PortA
-	register "ddi_portA_config" = "1"
+	register "ddi_ports_config" = "{
+		[DDI_PORT_A] = DDI_ENABLE_HPD,
+		[DDI_PORT_B] = DDI_ENABLE_HPD | DDI_ENABLE_DDC,
+	}"
 
 	device domain 0 on
 		device ref igpu on end
-		device ref dtt on end
 		device ref crashlog off end
 		device ref xhci on end
 		device ref shared_sram on end
@@ -63,21 +69,34 @@ chip soc/intel/alderlake
 		device ref pcie_rp11 on end
 		device ref pcie_rp12 on end # M.2 E key port
 		device ref pch_espi on
+			register "gen1_dec" = "0x00fc0201"
+			register "gen2_dec" = "0x003c0a01"
+			register "gen3_dec" = "0x000c0081"
 			chip superio/ite/it8613e
+				register "FAN2.mode"   = "FAN_SMART_SOFTWARE" # CPU_FAN
+				register "FAN3.mode"   = "FAN_SMART_SOFTWARE" # SYS_FAN
 				device pnp 2e.0 off end
-				device pnp 2e.1 on      # COM 1
+				device pnp 2e.1 on       # COM 1
 					io 0x60 = 0x3f8
 					irq 0x70 = 0x4
 					irq 0xf0 = 0x1
 				end
-				device pnp 2e.4 off end # Environment Controller
-				device pnp 2e.5 off end # Keyboard
-				device pnp 2e.6 off end # Mouse
-				device pnp 2e.7 off end # GPIO
-				device pnp 2e.a off end # CIR
+				device pnp 2e.4 on       # Environment Controller
+                                        io 0x60 = 0x0a30
+                                        io 0x62 = 0x0a20
+                                        irq 0x70 = 0x00
+                                        irq 0x71 = 0x80
+				end
+				device pnp 2e.5 off end  # Keyboard
+				device pnp 2e.6 off end  # Mouse
+				device pnp 2e.7 off end  # GPIO
+				device pnp 2e.a off end  # CIR
 			end
 		end
 		device ref hda on end
 		device ref smbus on end
+		chip drivers/crb
+			device mmio 0xfed40000 on end
+		end
 	end
 end

From 3a5c1ae56a5944eddc3d73505746c899b40ac908 Mon Sep 17 00:00:00 2001
From: Felix Held <felix-coreboot@felixheld.de>
Date: Mon, 3 Mar 2025 15:15:23 +0100
Subject: [PATCH 0266/3886] Revert "soc/amd/glinda/cpu: Update smbios
 parameters"

This reverts commit 00b4a61dc53c68b47d1452c387409f2eadf32c93.

I have strong doubts that this is Glinda-specific, so this probably
should have been made common after verifying.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ie7fa0dca4c92f7bb0d49956aa9f1588b5fcba585
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86688
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
---
 src/soc/amd/glinda/cpu.c | 16 ----------------
 1 file changed, 16 deletions(-)

diff --git a/src/soc/amd/glinda/cpu.c b/src/soc/amd/glinda/cpu.c
index 680b0957d3..26380077f2 100644
--- a/src/soc/amd/glinda/cpu.c
+++ b/src/soc/amd/glinda/cpu.c
@@ -17,22 +17,6 @@ unsigned int smbios_processor_external_clock(void)
 {
 	return 100; // 100 MHz
 }
-
-unsigned int smbios_cache_error_correction_type(u8 level)
-{
-	return SMBIOS_CACHE_ERROR_CORRECTION_MULTI_BIT;
-}
-
-unsigned int smbios_cache_conf_operation_mode(u8 level)
-{
-	return SMBIOS_CACHE_OP_MODE_WRITE_BACK;
-}
-
-unsigned int smbios_cache_sram_type(void)
-{
-	return SMBIOS_CACHE_SRAM_TYPE_PIPELINE_BURST;
-}
-
 static void zen_2_3_init(struct device *dev)
 {
 	check_mca();

From ca4c0d07d49aeeb663b5c83a3d92fc99d9da3dd1 Mon Sep 17 00:00:00 2001
From: Felix Held <felix-coreboot@felixheld.de>
Date: Mon, 3 Mar 2025 15:15:52 +0100
Subject: [PATCH 0267/3886] Revert "soc/amd/cpu: smbios: Set external clock to
 100 MHz"

This reverts commit fe107c1ad217243d68e55d7e238fc59c15d30d70.

I have strong doubts that this is Glinda-specific, so this likely should
have been made common after verifying.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ib7282e2bec4d6aa5b74efa5621c825bc234cca82
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86689
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/soc/amd/glinda/cpu.c | 5 -----
 1 file changed, 5 deletions(-)

diff --git a/src/soc/amd/glinda/cpu.c b/src/soc/amd/glinda/cpu.c
index 26380077f2..a7161270d2 100644
--- a/src/soc/amd/glinda/cpu.c
+++ b/src/soc/amd/glinda/cpu.c
@@ -7,16 +7,11 @@
 #include <cpu/amd/microcode.h>
 #include <cpu/cpu.h>
 #include <device/device.h>
-#include <smbios.h>
 #include <soc/cpu.h>
 
 _Static_assert(CONFIG_MAX_CPUS == 24, "Do not override MAX_CPUS. To reduce the number of "
 	"available cores, use the downcore_mode and disable_smt devicetree settings instead.");
 
-unsigned int smbios_processor_external_clock(void)
-{
-	return 100; // 100 MHz
-}
 static void zen_2_3_init(struct device *dev)
 {
 	check_mca();

From 5b268a5654a474e555d2b1b39f441a61d82495c4 Mon Sep 17 00:00:00 2001
From: Felix Held <felix-coreboot@felixheld.de>
Date: Mon, 3 Mar 2025 15:36:37 +0100
Subject: [PATCH 0268/3886] soc/amd/common/cpu/noncar: report 100 MHz external
 clock in smbios

All AMD SoCs from family 17h on, so all using a non-CAR configuration
to boot, have a reference clock of 100 MHz, so report this for all of
them in the SMBIOS tables.

Change-Id: I9573cbb8ec816c797314415d0c60c72abf23a094
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86690
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/soc/amd/common/block/cpu/noncar/cpu.c | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/src/soc/amd/common/block/cpu/noncar/cpu.c b/src/soc/amd/common/block/cpu/noncar/cpu.c
index 136cb42e0e..74b29cdb66 100644
--- a/src/soc/amd/common/block/cpu/noncar/cpu.c
+++ b/src/soc/amd/common/block/cpu/noncar/cpu.c
@@ -26,6 +26,11 @@ unsigned int smbios_processor_family(struct cpuid_result res)
 	return 0x6b; /* Zen */
 }
 
+unsigned int smbios_processor_external_clock(void)
+{
+	return 100; /* 100 MHz */
+}
+
 void set_cstate_io_addr(void)
 {
 	msr_t cst_addr;

From 6df02490a709c3cd49dce5e0bce4a36bb24ce2ef Mon Sep 17 00:00:00 2001
From: Pranava Y N <pranavayn@google.com>
Date: Fri, 28 Feb 2025 17:07:05 +0530
Subject: [PATCH 0269/3886] mb/google/brya/vell: Enable RTD3 for SSD to resolve
 S0ix issue

Add PCIe RTD3 support so NVMe gets placed into D3 state when entering
S0ix. Some SSDs block the CPU from reaching C10 during the S0ix
suspend without the RTD3 configuration.

Enable and reset GPIOs are configured as per pin mapping in gpio.c.

BUG=b:391612392
TEST=Run suspend_stress_test on vell and verify that the device
suspends to S0ix.

Change-Id: I9015f992cc797af013e8882630220b3df41dc9b3
Signed-off-by: Pranava Y N <pranavayn@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86646
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
---
 src/mainboard/google/brya/variants/vell/overridetree.cb | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/src/mainboard/google/brya/variants/vell/overridetree.cb b/src/mainboard/google/brya/variants/vell/overridetree.cb
index 697d0ef674..6f9b325a19 100644
--- a/src/mainboard/google/brya/variants/vell/overridetree.cb
+++ b/src/mainboard/google/brya/variants/vell/overridetree.cb
@@ -191,6 +191,13 @@ chip soc/intel/alderlake
 				.clk_src = 1,
 				.flags = PCIE_RP_LTR | PCIE_RP_AER,
 			}"
+			chip soc/intel/common/block/pcie/rtd3
+				register "is_storage" = "true"
+				register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D3)"
+				register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B4)"
+				register "srcclk_pin" = "1"
+				device generic 0 on end
+			end
 		end
 		device ref tbt_pcie_rp3 on end
 		device ref cnvi_wifi on

From 002a9119c9d5f1712d17aba2713c3876c13163ad Mon Sep 17 00:00:00 2001
From: Pranava Y N <pranavayn@google.com>
Date: Fri, 28 Feb 2025 17:09:17 +0530
Subject: [PATCH 0270/3886] mb/google/brya/gaelin: Enable RTD3 for SSD to
 resolve S0ix issue

Some SSDs block the CPU from reaching C10 during the S0ix suspend
without the RTD3 configuration. Add PCIe RTD3 support so NVMe gets
placed into D3 state when entering S0ix.

Enable and reset GPIOs are configured as per pin mapping in gpio.c.

BUG=b:391612392
TEST=Run suspend_stress_test on gaelin and verify that the device
suspends to S0ix.

Change-Id: I4a3f4fbddae3806f548705e9a492379c0b38a415
Signed-off-by: Pranava Y N <pranavayn@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86647
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
---
 src/mainboard/google/brya/variants/gaelin/overridetree.cb | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/src/mainboard/google/brya/variants/gaelin/overridetree.cb b/src/mainboard/google/brya/variants/gaelin/overridetree.cb
index af4ff61531..014be974b2 100644
--- a/src/mainboard/google/brya/variants/gaelin/overridetree.cb
+++ b/src/mainboard/google/brya/variants/gaelin/overridetree.cb
@@ -70,6 +70,13 @@ chip soc/intel/alderlake
 				.clk_src = 0,
 				.flags = PCIE_RP_LTR | PCIE_RP_AER,
 			}"
+			chip soc/intel/common/block/pcie/rtd3
+				register "is_storage" = "true"
+				register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_F14)"
+				register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B4)"
+				register "srcclk_pin" = "0"
+				device generic 0 on end
+			end
 		end
 		device ref tcss_xhci on
 			chip drivers/usb/acpi

From 26d494b57a1450efa4d21cc5884435770e465ee9 Mon Sep 17 00:00:00 2001
From: Pranava Y N <pranavayn@google.com>
Date: Fri, 28 Feb 2025 17:11:07 +0530
Subject: [PATCH 0271/3886] mb/google/brya/gladios: Enable RTD3 for SSD to
 resolve S0ix issue

Some SSDs block the CPU from reaching C10 during the S0ix suspend
without the RTD3 configuration. Add PCIe RTD3 support so NVMe gets
placed into D3 state when entering S0ix.

Enable and reset GPIOs are configured as per pin mapping in gpio.c.

BUG=b:391612392
TEST=Run suspend_stress_test on gladios and verify that the device
suspends to S0ix.

Change-Id: I329e3a99e2e5c7cf4a51d7d8606987f5277d4584
Signed-off-by: Pranava Y N <pranavayn@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86648
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/google/brya/variants/gladios/overridetree.cb | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/src/mainboard/google/brya/variants/gladios/overridetree.cb b/src/mainboard/google/brya/variants/gladios/overridetree.cb
index 4c3fffff6f..6c3eaf952a 100644
--- a/src/mainboard/google/brya/variants/gladios/overridetree.cb
+++ b/src/mainboard/google/brya/variants/gladios/overridetree.cb
@@ -149,6 +149,13 @@ chip soc/intel/alderlake
 				.clk_src = 0,
 				.flags = PCIE_RP_LTR | PCIE_RP_AER,
 			}"
+			chip soc/intel/common/block/pcie/rtd3
+				register "is_storage" = "true"
+				register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_F14)"
+				register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B4)"
+				register "srcclk_pin" = "0"
+				device generic 0 on end
+			end
 			probe STORAGE STORAGE_NVME
 		end #NVMe
 		device ref tbt_pcie_rp0 off end

From 28930e9c18cefb19aa1996bbfd3fad3538b6bb1f Mon Sep 17 00:00:00 2001
From: Pranava Y N <pranavayn@google.com>
Date: Fri, 28 Feb 2025 17:14:48 +0530
Subject: [PATCH 0272/3886] mb/google/brya/nova: Enable RTD3 for SSD to resolve
 S0ix issue

Some SSDs block the CPU from reaching C10 during the S0ix suspend
without the RTD3 configuration. Add PCIe RTD3 support so NVMe gets
placed into D3 state when entering S0ix.

Enable and reset GPIOs are configured as per pin mapping in gpio.c.

BUG=b:391612392
TEST=Run suspend_stress_test on nova and verify that the device
suspends to S0ix.

Change-Id: Icb36285d0a12dcb098282b08ef794256af67b019
Signed-off-by: Pranava Y N <pranavayn@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86649
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/google/brya/variants/nova/overridetree.cb | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/src/mainboard/google/brya/variants/nova/overridetree.cb b/src/mainboard/google/brya/variants/nova/overridetree.cb
index c8bfc31b08..a615fdd70b 100644
--- a/src/mainboard/google/brya/variants/nova/overridetree.cb
+++ b/src/mainboard/google/brya/variants/nova/overridetree.cb
@@ -185,6 +185,13 @@ chip soc/intel/alderlake
 				.clk_src = 0,
 				.flags = PCIE_RP_LTR | PCIE_RP_AER,
 			}"
+			chip soc/intel/common/block/pcie/rtd3
+				register "is_storage" = "true"
+				register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_F14)"
+				register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B4)"
+				register "srcclk_pin" = "0"
+				device generic 0 on end
+			end
 		end
 		device ref cnvi_wifi on
 			chip drivers/wifi/generic

From 08076240bdc10894b8e790e4b52adf4344fff261 Mon Sep 17 00:00:00 2001
From: Pranava Y N <pranavayn@google.com>
Date: Mon, 3 Mar 2025 11:44:53 +0530
Subject: [PATCH 0273/3886] mb/google/brya: Enable RTD3 for SSD to resolve S0ix
 issue

Some SSDs block the CPU from reaching C10 during the S0ix suspend
without the RTD3 configuration. Add PCIe RTD3 support so NVMe gets
placed into D3 state when entering S0ix.

Enable and reset GPIOs are configured as per pin mapping in gpio.c.

BUG=b:391612392
TEST=Run suspend_stress_test on brya device and verify that the device
suspends to S0ix.

Change-Id: Ifc85b85ef57216dc394f9a2e1b25bb7154da658f
Signed-off-by: Pranava Y N <pranavayn@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86685
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 .../google/brya/variants/baseboard/brya/devicetree.cb      | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb b/src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb
index 6160ebf084..3a748ea0f1 100644
--- a/src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb
+++ b/src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb
@@ -192,6 +192,13 @@ chip soc/intel/alderlake
 				.clk_req = 1,
 				.flags = PCIE_RP_LTR | PCIE_RP_AER,
 			}"
+			chip soc/intel/common/block/pcie/rtd3
+				register "is_storage" = "true"
+				register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D11)"
+				register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B4)"
+				register "srcclk_pin" = "1"
+				device generic 0 on end
+			end
 		end	#PCIE9-12 SSD
 		device ref uart0 on end
 		device ref gspi1 on end

From 1ec46a45c4c7c41320943b50dbbb1c3b16dcc458 Mon Sep 17 00:00:00 2001
From: Pranava Y N <pranavayn@google.com>
Date: Mon, 3 Mar 2025 11:54:29 +0530
Subject: [PATCH 0274/3886] mb/google/brya/constitution: Enable RTD3 for SSD to
 resolve S0ix issue

Some SSDs block the CPU from reaching C10 during the S0ix suspend
without the RTD3 configuration. Add PCIe RTD3 support so NVMe gets
placed into D3 state when entering S0ix.

Enable and reset GPIOs are configured as per pin mapping in gpio.c.

BUG=b:391612392
TEST=Run suspend_stress_test on constitution device and verify that
the device suspends to S0ix.

Change-Id: Ia367911d6d55b1f769c1660a6f42118988975621
Signed-off-by: Pranava Y N <pranavayn@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86686
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 .../google/brya/variants/constitution/overridetree.cb      | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/src/mainboard/google/brya/variants/constitution/overridetree.cb b/src/mainboard/google/brya/variants/constitution/overridetree.cb
index 01e4a15a75..f6c5380586 100644
--- a/src/mainboard/google/brya/variants/constitution/overridetree.cb
+++ b/src/mainboard/google/brya/variants/constitution/overridetree.cb
@@ -145,6 +145,13 @@ chip soc/intel/alderlake
 				.clk_src = 0,
 				.flags = PCIE_RP_LTR | PCIE_RP_AER,
 			}"
+			chip soc/intel/common/block/pcie/rtd3
+				register "is_storage" = "true"
+				register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_F14)"
+				register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B4)"
+				register "srcclk_pin" = "0"
+				device generic 0 on end
+			end
 		end
 		device ref tcss_dma0 on
 			chip drivers/intel/usb4/retimer

From 7eb53f8623bc5b0e2dc6fdec604b729c48850132 Mon Sep 17 00:00:00 2001
From: Kapil Porwal <kapilporwal@google.com>
Date: Mon, 3 Mar 2025 11:06:33 +0530
Subject: [PATCH 0275/3886] soc/intel/ptl: Define config option for Wildcat
 Lake (WCL)
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

This is same as PTL U/H at the moment.

BUG=b:372502513
TEST=Build AP firmware image.

Change-Id: Ibc51cb90bc13a442587d3dc187638544cb633a0f
Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86691
Reviewed-by: Jayvik Desai <jayvik@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/soc/intel/pantherlake/Kconfig | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/src/soc/intel/pantherlake/Kconfig b/src/soc/intel/pantherlake/Kconfig
index fc8664a927..58e6c28686 100644
--- a/src/soc/intel/pantherlake/Kconfig
+++ b/src/soc/intel/pantherlake/Kconfig
@@ -127,6 +127,12 @@ config SOC_INTEL_PANTHERLAKE_H
 	help
 	  Choose this option if the mainboard is built using PTL-H 4Xe system-on-a-chip (SoC).
 
+config SOC_INTEL_WILDCATLAKE
+	bool
+	select SOC_INTEL_PANTHERLAKE_U_H
+	help
+	  Choose this option if the mainboard is built using WCL system-on-a-chip (SoC).
+
 if SOC_INTEL_PANTHERLAKE_BASE
 
 config SOC_INTEL_PANTHERLAKE_TCSS_USB4_SUPPORT

From c4afd04547e07e51e03f6e4dcd1d5a7271da5e92 Mon Sep 17 00:00:00 2001
From: Kapil Porwal <kapilporwal@google.com>
Date: Mon, 3 Mar 2025 11:10:12 +0530
Subject: [PATCH 0276/3886] mb/google/ocelot: Create Ocelot board

This is just a copy of fatcat at the moment.

BUG=b:372502513
TEST=Build AP firmware image.

Change-Id: Iee93610f3367f4c850b4fcc8827a4a4d44b46117
Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86692
Reviewed-by: Jayvik Desai <jayvik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
---
 src/mainboard/google/ocelot/Kconfig           | 143 +++
 src/mainboard/google/ocelot/Kconfig.name      |   6 +
 src/mainboard/google/ocelot/Makefile.mk       |  26 +
 src/mainboard/google/ocelot/board_info.txt    |   6 +
 src/mainboard/google/ocelot/bootblock.c       |  13 +
 src/mainboard/google/ocelot/chromeos.c        |  34 +
 src/mainboard/google/ocelot/chromeos.fmd      |  49 +
 src/mainboard/google/ocelot/dsdt.asl          |  42 +
 src/mainboard/google/ocelot/ec.c              |  22 +
 src/mainboard/google/ocelot/mainboard.c       |  74 ++
 src/mainboard/google/ocelot/romstage.c        |  36 +
 src/mainboard/google/ocelot/smihandler.c      |  29 +
 src/mainboard/google/ocelot/spd/Makefile.mk   |   6 +
 .../baseboard/include/baseboard/variants.h    |  40 +
 .../variants/baseboard/ocelot/Makefile.mk     |   4 +
 .../variants/baseboard/ocelot/devicetree.cb   |  99 ++
 .../baseboard/ocelot/include/baseboard/ec.h   |  87 ++
 .../baseboard/ocelot/include/baseboard/gpio.h |  21 +
 .../ocelot/variants/baseboard/ocelot/memory.c |  31 +
 .../variants/baseboard/ocelot/ramstage.c      |  62 ++
 .../google/ocelot/variants/ocelot/Makefile.mk |   9 +
 .../google/ocelot/variants/ocelot/fw_config.c | 651 +++++++++++++
 .../google/ocelot/variants/ocelot/gpio.c      | 424 +++++++++
 .../google/ocelot/variants/ocelot/hda_verb.c  | 126 +++
 .../variants/ocelot/include/variant/ec.h      |   8 +
 .../variants/ocelot/include/variant/gpio.h    |  11 +
 .../google/ocelot/variants/ocelot/memory.c    |  76 ++
 .../ocelot/variants/ocelot/memory/Makefile.mk |   7 +
 .../ocelot/memory/dram_id.generated.txt       |   7 +
 .../variants/ocelot/memory/mem_parts_used.txt |  12 +
 .../ocelot/variants/ocelot/overridetree.cb    | 890 ++++++++++++++++++
 .../google/ocelot/variants/ocelot/variant.c   |  30 +
 32 files changed, 3081 insertions(+)
 create mode 100644 src/mainboard/google/ocelot/Kconfig
 create mode 100644 src/mainboard/google/ocelot/Kconfig.name
 create mode 100644 src/mainboard/google/ocelot/Makefile.mk
 create mode 100644 src/mainboard/google/ocelot/board_info.txt
 create mode 100644 src/mainboard/google/ocelot/bootblock.c
 create mode 100644 src/mainboard/google/ocelot/chromeos.c
 create mode 100644 src/mainboard/google/ocelot/chromeos.fmd
 create mode 100644 src/mainboard/google/ocelot/dsdt.asl
 create mode 100644 src/mainboard/google/ocelot/ec.c
 create mode 100644 src/mainboard/google/ocelot/mainboard.c
 create mode 100644 src/mainboard/google/ocelot/romstage.c
 create mode 100644 src/mainboard/google/ocelot/smihandler.c
 create mode 100644 src/mainboard/google/ocelot/spd/Makefile.mk
 create mode 100644 src/mainboard/google/ocelot/variants/baseboard/include/baseboard/variants.h
 create mode 100644 src/mainboard/google/ocelot/variants/baseboard/ocelot/Makefile.mk
 create mode 100644 src/mainboard/google/ocelot/variants/baseboard/ocelot/devicetree.cb
 create mode 100644 src/mainboard/google/ocelot/variants/baseboard/ocelot/include/baseboard/ec.h
 create mode 100644 src/mainboard/google/ocelot/variants/baseboard/ocelot/include/baseboard/gpio.h
 create mode 100644 src/mainboard/google/ocelot/variants/baseboard/ocelot/memory.c
 create mode 100644 src/mainboard/google/ocelot/variants/baseboard/ocelot/ramstage.c
 create mode 100644 src/mainboard/google/ocelot/variants/ocelot/Makefile.mk
 create mode 100644 src/mainboard/google/ocelot/variants/ocelot/fw_config.c
 create mode 100644 src/mainboard/google/ocelot/variants/ocelot/gpio.c
 create mode 100644 src/mainboard/google/ocelot/variants/ocelot/hda_verb.c
 create mode 100644 src/mainboard/google/ocelot/variants/ocelot/include/variant/ec.h
 create mode 100644 src/mainboard/google/ocelot/variants/ocelot/include/variant/gpio.h
 create mode 100644 src/mainboard/google/ocelot/variants/ocelot/memory.c
 create mode 100644 src/mainboard/google/ocelot/variants/ocelot/memory/Makefile.mk
 create mode 100644 src/mainboard/google/ocelot/variants/ocelot/memory/dram_id.generated.txt
 create mode 100644 src/mainboard/google/ocelot/variants/ocelot/memory/mem_parts_used.txt
 create mode 100644 src/mainboard/google/ocelot/variants/ocelot/overridetree.cb
 create mode 100644 src/mainboard/google/ocelot/variants/ocelot/variant.c

diff --git a/src/mainboard/google/ocelot/Kconfig b/src/mainboard/google/ocelot/Kconfig
new file mode 100644
index 0000000000..38393bdbbd
--- /dev/null
+++ b/src/mainboard/google/ocelot/Kconfig
@@ -0,0 +1,143 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
+config BOARD_GOOGLE_OCELOT_COMMON
+	def_bool n
+	select BOARD_ROMSIZE_KB_32768
+	select CPU_INTEL_SOCKET_OTHER
+	select DRIVERS_GFX_GENERIC
+	select DRIVERS_I2C_GENERIC
+	select DRIVERS_I2C_HID
+	select DRIVERS_INTEL_DPTF
+	select DRIVERS_INTEL_MIPI_CAMERA
+	select DRIVERS_INTEL_PMC
+	select DRIVERS_INTEL_SOUNDWIRE
+	select DRIVERS_WWAN_FM350GL
+	select DRIVERS_AUDIO_SOF
+	select DRIVERS_SOUNDWIRE_ALC_BASE_7XX
+	select DRIVERS_SPI_ACPI
+	select DUMP_SMBIOS_TYPE17
+	select EC_ACPI
+	select EC_GOOGLE_CHROMEEC
+	select EC_GOOGLE_CHROMEEC_BOARDID
+	select EC_GOOGLE_CHROMEEC_ESPI
+	select EC_GOOGLE_CHROMEEC_SKUID
+	select FW_CONFIG
+	select FW_CONFIG_SOURCE_CHROMEEC_CBI
+	select GENERATE_SMBIOS_TABLES
+	select GOOGLE_SMBIOS_MAINBOARD_VERSION
+	select HAVE_ACPI_RESUME
+	select HAVE_ACPI_TABLES
+	select HAVE_SPD_IN_CBFS
+	select I2C_TPM
+	select INTEL_LPSS_UART_FOR_CONSOLE
+	select MAINBOARD_DISABLE_STAGE_CACHE
+	select MAINBOARD_HAS_TPM2
+	select MB_COMPRESS_RAMSTAGE_LZ4
+	select PMC_IPC_ACPI_INTERFACE
+	select SOC_INTEL_COMMON_BLOCK_VARIANT_POWER_LIMIT
+	select SOC_INTEL_CSE_LITE_SYNC_BY_PAYLOAD
+	select SOC_INTEL_CSE_SEND_EOP_BY_PAYLOAD
+	select SOC_INTEL_WILDCATLAKE
+	select SOC_INTEL_TCSS_USE_PDC_PMC_USBC_MUX_CONFIGURATION
+
+config BOARD_GOOGLE_BASEBOARD_OCELOT
+	def_bool n
+	select BOARD_GOOGLE_OCELOT_COMMON
+	select CHROMEOS_WIFI_SAR if CHROMEOS
+	select DRIVERS_INTEL_ISH
+	select DRIVER_INTEL_ISH_HAS_MAIN_FW
+	select DRIVERS_INTEL_USB4_RETIMER
+	select HAVE_SLP_S0_GATE
+	select MAINBOARD_HAS_CHROMEOS
+	select MEMORY_SOLDERDOWN
+	select SOC_INTEL_COMMON_BLOCK_HDA_VERB
+	select SOC_INTEL_IOE_DIE_SUPPORT
+	select SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES
+	select SYSTEM_TYPE_LAPTOP
+	select TPM_GOOGLE_TI50
+
+config BOARD_GOOGLE_OCELOT
+	select BOARD_GOOGLE_BASEBOARD_OCELOT
+	select DRIVERS_GENERIC_BAYHUB_LV2
+	select DRIVERS_GENERIC_MAX98357A
+	select EC_GOOGLE_CHROMEEC_MEC
+	select MAINBOARD_USES_IFD_EC_REGION
+	select SOC_INTEL_WILDCATLAKE
+
+if BOARD_GOOGLE_OCELOT_COMMON
+
+config BASEBOARD_DIR
+	string
+	default "ocelot"
+
+config CHROMEOS
+	select EC_GOOGLE_CHROMEEC_SWITCHES
+	select GBB_FLAG_DISABLE_EC_SOFTWARE_SYNC
+	select GBB_FLAG_FORCE_DEV_BOOT_USB
+	select GBB_FLAG_FORCE_MANUAL_RECOVERY
+	select HAS_RECOVERY_MRC_CACHE
+
+config CHROMEOS_WIFI_SAR
+	bool "Enable SAR options for ChromeOS build"
+	depends on CHROMEOS
+	select DSAR_ENABLE
+	select GEO_SAR_ENABLE
+	select SAR_ENABLE
+	select USE_SAR
+
+config DEVICETREE
+	default "variants/baseboard/\$(CONFIG_BASEBOARD_DIR)/devicetree.cb"
+
+config DIMM_SPD_SIZE
+	default 512
+
+config DRIVER_TPM_I2C_ADDR
+	hex
+	default 0x50
+
+config DRIVER_TPM_I2C_BUS
+	hex
+	default 0x03 if BOARD_GOOGLE_OCELOT
+
+config HAVE_SLP_S0_GATE
+	def_bool n
+
+config MAINBOARD_DIR
+	default "google/ocelot"
+
+config MAINBOARD_FAMILY
+	string
+	default "Google_Ocelot"
+
+# FIXME: update once Ocelot config is available
+config MAINBOARD_PART_NUMBER
+	default "Fatcat" if BOARD_GOOGLE_OCELOT
+
+config MEMORY_SOLDERDOWN
+	def_bool n
+	select CHROMEOS_DRAM_PART_NUMBER_IN_CBI if CHROMEOS
+	select HAVE_SPD_IN_CBFS
+
+config TPM_TIS_ACPI_INTERRUPT
+	int
+	default 47 if BOARD_GOOGLE_OCELOT # GPE0_DW1_15 (GPP_D15)
+
+# FIXME: update as per board schematics
+config UART_FOR_CONSOLE
+	int
+	default 0
+
+config USE_PM_ACPI_TIMER
+	default n
+
+config VARIANT_DIR
+	string
+	default "ocelot" if BOARD_GOOGLE_OCELOT
+
+config OVERRIDE_DEVICETREE
+	default "variants/\$(CONFIG_VARIANT_DIR)/overridetree.cb"
+
+config VBOOT
+	select VBOOT_LID_SWITCH
+
+endif # BOARD_GOOGLE_OCELOT_COMMON
diff --git a/src/mainboard/google/ocelot/Kconfig.name b/src/mainboard/google/ocelot/Kconfig.name
new file mode 100644
index 0000000000..e79c4b484a
--- /dev/null
+++ b/src/mainboard/google/ocelot/Kconfig.name
@@ -0,0 +1,6 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
+comment "Ocelot"
+
+config BOARD_GOOGLE_OCELOT
+	bool "-> Ocelot"
diff --git a/src/mainboard/google/ocelot/Makefile.mk b/src/mainboard/google/ocelot/Makefile.mk
new file mode 100644
index 0000000000..aea91d577a
--- /dev/null
+++ b/src/mainboard/google/ocelot/Makefile.mk
@@ -0,0 +1,26 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
+bootblock-y += bootblock.c
+
+verstage-$(CONFIG_CHROMEOS) += chromeos.c
+
+romstage-y += romstage.c
+romstage-$(CONFIG_CHROMEOS) += chromeos.c
+
+ramstage-y += mainboard.c
+ramstage-$(CONFIG_CHROMEOS) += chromeos.c
+ramstage-y += ec.c
+ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_HDA_VERB) += variants/$(VARIANT_DIR)/hda_verb.c
+
+smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c
+
+BASEBOARD_DIR:=$(call strip_quotes,$(CONFIG_BASEBOARD_DIR))
+
+subdirs-y += variants/baseboard/$(BASEBOARD_DIR)
+subdirs-y += variants/$(VARIANT_DIR)
+subdirs-y += variants/$(VARIANT_DIR)/memory
+subdirs-$(CONFIG_HAVE_SPD_IN_CBFS) += spd
+
+CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/baseboard/include
+CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/baseboard/$(BASEBOARD_DIR)/include
+CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/include
diff --git a/src/mainboard/google/ocelot/board_info.txt b/src/mainboard/google/ocelot/board_info.txt
new file mode 100644
index 0000000000..ad93913570
--- /dev/null
+++ b/src/mainboard/google/ocelot/board_info.txt
@@ -0,0 +1,6 @@
+Vendor name: Google
+Board name: Ocelot
+Category: laptop
+ROM protocol: SPI
+ROM socketed: n
+Flashrom support: y
diff --git a/src/mainboard/google/ocelot/bootblock.c b/src/mainboard/google/ocelot/bootblock.c
new file mode 100644
index 0000000000..6ee655ee58
--- /dev/null
+++ b/src/mainboard/google/ocelot/bootblock.c
@@ -0,0 +1,13 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <baseboard/variants.h>
+#include <bootblock_common.h>
+
+void bootblock_mainboard_early_init(void)
+{
+	const struct pad_config *pads;
+	size_t num;
+
+	pads = variant_early_gpio_table(&num);
+	gpio_configure_pads(pads, num);
+}
diff --git a/src/mainboard/google/ocelot/chromeos.c b/src/mainboard/google/ocelot/chromeos.c
new file mode 100644
index 0000000000..5ed041f52b
--- /dev/null
+++ b/src/mainboard/google/ocelot/chromeos.c
@@ -0,0 +1,34 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <baseboard/gpio.h>
+#include <bootmode.h>
+#include <boot/coreboot_tables.h>
+#include <gpio.h>
+#include <types.h>
+
+void fill_lb_gpios(struct lb_gpios *gpios)
+{
+	struct lb_gpio chromeos_gpios[] = {
+#if CONFIG(VBOOT_LID_SWITCH)
+		{-1, ACTIVE_HIGH, get_lid_switch(), "lid"},
+#else
+		/* fake LID open to avoid shutdown in depthcharge */
+		{-1, ACTIVE_HIGH, 1, "lid"},
+#endif
+		{-1, ACTIVE_HIGH, 0, "power"},
+		{-1, ACTIVE_HIGH, gfx_get_init_done(), "oprom"},
+		{-1, ACTIVE_HIGH, 0, "EC in RW"},
+	};
+	lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios));
+}
+
+int get_write_protect_state(void)
+{
+	return gpio_get(GPIO_PCH_WP);
+}
+
+int get_ec_is_trusted(void)
+{
+	/* VB2_CONTEXT_EC_TRUSTED should be set according to the Ti50 boot mode. */
+	return 0;
+}
diff --git a/src/mainboard/google/ocelot/chromeos.fmd b/src/mainboard/google/ocelot/chromeos.fmd
new file mode 100644
index 0000000000..0ff14e3691
--- /dev/null
+++ b/src/mainboard/google/ocelot/chromeos.fmd
@@ -0,0 +1,49 @@
+FLASH 32M {
+	SI_ALL 8M {
+		SI_DESC 16K
+		SI_ME
+	}
+	SI_BIOS 24M {
+		RW_SECTION_A 8M {
+			VBLOCK_A 8K
+			FW_MAIN_A(CBFS)
+			RW_FWID_A 64
+		}
+		# This section starts at the 16M boundary in SPI flash.
+		# PTL does not support a region crossing this boundary,
+		# because the SPI flash is memory-mapped into two non-
+		# contiguous windows.
+		RW_SECTION_B 8M {
+			VBLOCK_B 8K
+			FW_MAIN_B(CBFS)
+			RW_FWID_B 64
+		}
+		RW_MISC 1M {
+			UNIFIED_MRC_CACHE(PRESERVE) 128K {
+				RECOVERY_MRC_CACHE 64K
+				RW_MRC_CACHE 64K
+			}
+			RW_ELOG(PRESERVE) 16K
+			RW_SHARED 16K {
+				SHARED_DATA 8K
+				VBLOCK_DEV 8K
+			}
+			RW_VPD(PRESERVE) 8K
+			RW_NVRAM(PRESERVE) 24K
+		}
+		RW_LEGACY(CBFS) 1M
+		RW_UNUSED 2M
+		# Make WP_RO region align with SPI vendor
+		# memory protected range specification.
+		WP_RO 4M {
+			RO_VPD(PRESERVE) 16K
+			RO_GSCVD 8K
+			RO_SECTION {
+				FMAP 2K
+				RO_FRID 64
+				GBB@4K 12K
+				COREBOOT(CBFS)
+			}
+		}
+	}
+}
diff --git a/src/mainboard/google/ocelot/dsdt.asl b/src/mainboard/google/ocelot/dsdt.asl
new file mode 100644
index 0000000000..03882c6327
--- /dev/null
+++ b/src/mainboard/google/ocelot/dsdt.asl
@@ -0,0 +1,42 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <acpi/acpi.h>
+#include <variant/ec.h>
+#include <variant/gpio.h>
+
+DefinitionBlock(
+	"dsdt.aml",
+	"DSDT",
+	ACPI_DSDT_REV_2,
+	OEM_ID,
+	ACPI_TABLE_CREATOR,
+	0x20240917
+)
+{
+	#include <acpi/dsdt_top.asl>
+	#include <soc/intel/common/block/acpi/acpi/platform.asl>
+
+	/* global NVS and variables */
+	#include <soc/intel/common/block/acpi/acpi/globalnvs.asl>
+
+	#include <cpu/intel/common/acpi/cpu.asl>
+
+	Device (\_SB.PCI0) {
+		#include <soc/intel/common/block/acpi/acpi/northbridge.asl>
+		#include <soc/intel/pantherlake/acpi/southbridge.asl>
+		#include <soc/intel/pantherlake/acpi/tcss.asl>
+	}
+
+#if CONFIG(EC_GOOGLE_CHROMEEC)
+	/* ChromeOS Embedded Controller */
+	Scope (\_SB.PCI0.LPCB)
+	{
+		/* ACPI code for EC SuperIO functions */
+		#include <ec/google/chromeec/acpi/superio.asl>
+		/* ACPI code for EC functions */
+		#include <ec/google/chromeec/acpi/ec.asl>
+	}
+#endif
+
+	#include <southbridge/intel/common/acpi/sleepstates.asl>
+}
diff --git a/src/mainboard/google/ocelot/ec.c b/src/mainboard/google/ocelot/ec.c
new file mode 100644
index 0000000000..f828bc5547
--- /dev/null
+++ b/src/mainboard/google/ocelot/ec.c
@@ -0,0 +1,22 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <acpi/acpi.h>
+#include <console/console.h>
+#include <ec/ec.h>
+#include <ec/google/chromeec/ec.h>
+#include <variant/ec.h>
+
+void mainboard_ec_init(void)
+{
+	static const struct google_chromeec_event_info info = {
+		.log_events = MAINBOARD_EC_LOG_EVENTS,
+		.sci_events = MAINBOARD_EC_SCI_EVENTS,
+		.s3_wake_events = MAINBOARD_EC_S3_WAKE_EVENTS,
+		.s5_wake_events = MAINBOARD_EC_S5_WAKE_EVENTS,
+		.s0ix_wake_events = MAINBOARD_EC_S0IX_WAKE_EVENTS,
+	};
+
+	printk(BIOS_DEBUG, "mainboard: EC init\n");
+
+	google_chromeec_events_init(&info, acpi_is_wakeup_s3());
+}
diff --git a/src/mainboard/google/ocelot/mainboard.c b/src/mainboard/google/ocelot/mainboard.c
new file mode 100644
index 0000000000..f514eb96d1
--- /dev/null
+++ b/src/mainboard/google/ocelot/mainboard.c
@@ -0,0 +1,74 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <acpi/acpi.h>
+#include <acpi/acpigen.h>
+#include <baseboard/gpio.h>
+#include <baseboard/variants.h>
+#include <device/device.h>
+#include <ec/ec.h>
+#include <soc/ramstage.h>
+#include <stdlib.h>
+#include <vendorcode/google/chromeos/chromeos.h>
+
+void __weak fw_config_gpio_padbased_override(struct pad_config *padbased_table)
+{
+	/* default implementation does nothing */
+}
+
+void mainboard_update_soc_chip_config(struct soc_intel_pantherlake_config *config)
+{
+	variant_update_soc_chip_config(config);
+}
+
+void __weak variant_update_soc_chip_config(struct soc_intel_pantherlake_config *config)
+{
+	/* default implementation does nothing */
+}
+
+static void mainboard_init(void *chip_info)
+{
+	struct pad_config *padbased_table;
+	const struct pad_config *base_pads;
+	size_t base_num;
+
+	padbased_table = new_padbased_table();
+	base_pads = variant_gpio_table(&base_num);
+	gpio_padbased_override(padbased_table, base_pads, base_num);
+	fw_config_gpio_padbased_override(padbased_table);
+	gpio_configure_pads_with_padbased(padbased_table);
+	free(padbased_table);
+	baseboard_devtree_update();
+}
+
+void __weak baseboard_devtree_update(void)
+{
+	/* Override dev tree settings per baseboard */
+}
+
+void __weak variant_generate_s0ix_hook(enum s0ix_entry entry)
+{
+	/* Add board-specific MS0X entries */
+	/*
+	   if (s0ix_entry == S0IX_ENTRY) {
+		implement variant operations here
+	   }
+	   if (s0ix_entry == S0IX_EXIT) {
+		implement variant operations here
+	   }
+	 */
+}
+
+static void mainboard_dev_init(struct device *dev)
+{
+	mainboard_ec_init();
+}
+
+static void mainboard_enable(struct device *dev)
+{
+	dev->ops->init = mainboard_dev_init;
+}
+
+struct chip_operations mainboard_ops = {
+	.init = mainboard_init,
+	.enable_dev = mainboard_enable,
+};
diff --git a/src/mainboard/google/ocelot/romstage.c b/src/mainboard/google/ocelot/romstage.c
new file mode 100644
index 0000000000..7b56e28e3c
--- /dev/null
+++ b/src/mainboard/google/ocelot/romstage.c
@@ -0,0 +1,36 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <baseboard/variants.h>
+#include <fsp/api.h>
+#include <soc/romstage.h>
+#include <string.h>
+
+/*
+ * Placeholder to configure GPIO early from romstage relying on the FW_CONFIG.
+ *
+ * If any platform would like to override early GPIOs, they should override from
+ * the variant directory.
+ */
+__weak void fw_config_configure_pre_mem_gpio(void)
+{
+	/* Nothing to do */
+}
+
+void mainboard_memory_init_params(FSPM_UPD *memupd)
+{
+	const struct pad_config *pads;
+	size_t pads_num;
+	const struct mb_cfg *mem_config = variant_memory_params();
+	bool half_populated = variant_is_half_populated();
+	struct mem_spd spd_info;
+
+	pads = variant_romstage_gpio_table(&pads_num);
+	if (pads_num)
+		gpio_configure_pads(pads, pads_num);
+	fw_config_configure_pre_mem_gpio();
+
+	memset(&spd_info, 0, sizeof(spd_info));
+	variant_get_spd_info(&spd_info);
+
+	memcfg_init(memupd, mem_config, &spd_info, half_populated);
+}
diff --git a/src/mainboard/google/ocelot/smihandler.c b/src/mainboard/google/ocelot/smihandler.c
new file mode 100644
index 0000000000..9208d51613
--- /dev/null
+++ b/src/mainboard/google/ocelot/smihandler.c
@@ -0,0 +1,29 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <cpu/x86/smm.h>
+#include <ec/google/chromeec/ec.h>
+#include <ec/google/chromeec/smm.h>
+#include <elog.h>
+#include <intelblocks/smihandler.h>
+#include <variant/ec.h>
+
+void mainboard_smi_sleep(u8 slp_typ)
+{
+	chromeec_smi_sleep(slp_typ, MAINBOARD_EC_S3_WAKE_EVENTS, MAINBOARD_EC_S5_WAKE_EVENTS);
+}
+
+int mainboard_smi_apmc(u8 apmc)
+{
+	chromeec_smi_apmc(apmc, MAINBOARD_EC_SCI_EVENTS, MAINBOARD_EC_SMI_EVENTS);
+	return 0;
+}
+
+void elog_gsmi_cb_mainboard_log_wake_source(void)
+{
+	google_chromeec_log_events(MAINBOARD_EC_LOG_EVENTS | MAINBOARD_EC_S0IX_WAKE_EVENTS);
+}
+
+void mainboard_smi_espi_handler(void)
+{
+	chromeec_smi_process_events();
+}
diff --git a/src/mainboard/google/ocelot/spd/Makefile.mk b/src/mainboard/google/ocelot/spd/Makefile.mk
new file mode 100644
index 0000000000..be4d98bd1d
--- /dev/null
+++ b/src/mainboard/google/ocelot/spd/Makefile.mk
@@ -0,0 +1,6 @@
+## SPDX-License-Identifier: GPL-2.0-or-later
+##
+
+ifneq ($(SPD_SOURCES),)
+LIB_SPD_DEPS := $(SPD_SOURCES)
+endif
diff --git a/src/mainboard/google/ocelot/variants/baseboard/include/baseboard/variants.h b/src/mainboard/google/ocelot/variants/baseboard/include/baseboard/variants.h
new file mode 100644
index 0000000000..2a70408e0d
--- /dev/null
+++ b/src/mainboard/google/ocelot/variants/baseboard/include/baseboard/variants.h
@@ -0,0 +1,40 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#ifndef __BASEBOARD_VARIANTS_H__
+#define __BASEBOARD_VARIANTS_H__
+
+#include <chip.h>
+#include <soc/gpio.h>
+#include <soc/meminit.h>
+#include <stdint.h>
+#include <vendorcode/google/chromeos/chromeos.h>
+
+/* The next set of functions return the gpio table and fill in the number of entries for
+ * each table.
+ */
+
+const struct pad_config *variant_gpio_table(size_t *num);
+const struct pad_config *variant_early_gpio_table(size_t *num);
+const struct pad_config *variant_romstage_gpio_table(size_t *num);
+void fw_config_configure_pre_mem_gpio(void);
+void fw_config_gpio_padbased_override(struct pad_config *padbased_table);
+
+const struct mb_cfg *variant_memory_params(void);
+void variant_get_spd_info(struct mem_spd *spd_info);
+int variant_memory_sku(void);
+bool variant_is_half_populated(void);
+void variant_update_soc_chip_config(struct soc_intel_pantherlake_config *config);
+
+enum s0ix_entry {
+	S0IX_EXIT,
+	S0IX_ENTRY,
+};
+
+void variant_generate_s0ix_hook(enum s0ix_entry entry);
+
+/* Modify devictree settings during ramstage by baseboard */
+void baseboard_devtree_update(void);
+/* Modify devictree settings during ramstage by dedicated variant */
+void variant_devtree_update(void);
+
+#endif /*__BASEBOARD_VARIANTS_H__ */
diff --git a/src/mainboard/google/ocelot/variants/baseboard/ocelot/Makefile.mk b/src/mainboard/google/ocelot/variants/baseboard/ocelot/Makefile.mk
new file mode 100644
index 0000000000..47123cd318
--- /dev/null
+++ b/src/mainboard/google/ocelot/variants/baseboard/ocelot/Makefile.mk
@@ -0,0 +1,4 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
+romstage-y += memory.c
+ramstage-y += ramstage.c
diff --git a/src/mainboard/google/ocelot/variants/baseboard/ocelot/devicetree.cb b/src/mainboard/google/ocelot/variants/baseboard/ocelot/devicetree.cb
new file mode 100644
index 0000000000..8bfe819b7c
--- /dev/null
+++ b/src/mainboard/google/ocelot/variants/baseboard/ocelot/devicetree.cb
@@ -0,0 +1,99 @@
+chip soc/intel/pantherlake
+	# GPE configuration
+	register "pmc_gpe0_dw0" = "GPP_A"
+	register "pmc_gpe0_dw1" = "GPP_D"
+	register "pmc_gpe0_dw2" = "GPP_E"
+
+	# For Ocelot variants with microchip EC:
+	#	EC host command ranges are in 0x800-0x807 & 0x200-0x20f
+	# For Ocelot variants with ITE/Nuvoton EC:
+	# 	EC host command ranges are in 0x800-0x8ff & 0x200-0x20f
+	register "gen1_dec" = "CONFIG(BOARD_GOOGLE_OCELOT)? 0x00040801 : 0x00fc0801"
+	register "gen2_dec" = "0x000c0201"
+	# EC memory map range is 0x900-0x9ff
+	register "gen3_dec" = "0x00fc0901"
+
+	register "usb2_ports[0]" = "USB2_PORT_EMPTY"	# Disable USB2.0 Port 0
+	register "usb2_ports[1]" = "USB2_PORT_EMPTY"	# Disable USB2.0 Port 1
+	register "usb2_ports[2]" = "USB2_PORT_EMPTY"	# Disable USB2.0 Port 2
+	register "usb2_ports[3]" = "USB2_PORT_EMPTY"	# Disable USB2.0 Port 3
+	register "usb2_ports[4]" = "USB2_PORT_EMPTY"	# Disable USB2.0 Port 4
+	register "usb2_ports[5]" = "USB2_PORT_EMPTY"	# Disable USB2.0 Port 5
+	register "usb2_ports[6]" = "USB2_PORT_EMPTY"	# Disable USB2.0 Port 6
+	register "usb2_ports[7]" = "USB2_PORT_EMPTY"	# Disable USB2.0 Port 7
+
+	register "usb3_ports[0]" = "USB3_PORT_EMPTY"	# Disable USB3.0 Port 0
+	register "usb3_ports[1]" = "USB3_PORT_EMPTY"	# Disable USB3.0 Port 1
+
+	register "tcss_ports[0]" = "TCSS_PORT_EMPTY"	# Disable USB-C Port 0
+	register "tcss_ports[1]" = "TCSS_PORT_EMPTY"	# Disable USB-C Port 1
+	register "tcss_ports[2]" = "TCSS_PORT_EMPTY"	# Disable USB-C Port 2
+	register "tcss_ports[3]" = "TCSS_PORT_EMPTY"	# Disable USB-C Port 3
+
+	# Enable SAGv
+	register "sagv" = "SAGV_ENABLED"
+
+	register "sagv_freq_mhz[0]" = "2400"
+	register "sagv_gear[0]" = "GEAR_4"
+
+	register "sagv_freq_mhz[1]" = "3200"
+	register "sagv_gear[1]" = "GEAR_4"
+
+	register "sagv_freq_mhz[2]" = "6000"
+	register "sagv_gear[2]" = "GEAR_4"
+
+	register "sagv_freq_mhz[3]" = "6400"
+	register "sagv_gear[3]" = "GEAR_4"
+
+	# Enable s0ix
+	register "s0ix_enable" = "true"
+
+	# DPTF enable
+	register "dptf_enable" = "true"
+
+	# Setting TCC of 100C = Tj max (110) - TCC_Offset (10)
+	register "tcc_offset" = "10"
+
+	# Disable C1 C-state auto-demotion
+	register "disable_c1_state_auto_demotion" = "true"
+	# Disable PKGC-state auto-demotion
+	register "disable_package_c_state_demotion" = "true"
+
+	# Enable Energy Reporting
+	register "pch_pm_energy_report_enable" = "true"
+
+	# Enable CNVi BT
+	register "cnvi_bt_core" = "true"
+
+	register "serial_io_uart_mode" = "{
+		[PchSerialIoIndexUART0] = PchSerialIoSkipInit,
+		[PchSerialIoIndexUART1] = PchSerialIoDisabled,
+		[PchSerialIoIndexUART2] = PchSerialIoDisabled,
+	}"
+
+	register "serial_io_gspi_mode" = "{
+		[PchSerialIoIndexGSPI0] = PchSerialIoPci,
+		[PchSerialIoIndexGSPI1] = PchSerialIoPci,
+		[PchSerialIoIndexGSPI0A] = PchSerialIoPci,
+	}"
+
+	register "pch_hda_dsp_enable" = "true"
+	register "pch_hda_idisp_link_tmode" = "HDA_TMODE_8T"
+	register "pch_hda_idisp_link_frequency" = "HDA_LINKFREQ_96MHZ"
+	register "pch_hda_idisp_codec_enable" = "true"
+	register "pch_hda_sdi_enable" = "{ true, false }"
+
+	device domain 0 on
+		device ref dtt on end
+		device ref npu on end
+		device ref xhci on end
+		device ref pmc_shared_sram on end
+		device ref heci1 on end
+		device ref uart0 on end
+		device ref soc_espi on
+			chip ec/google/chromeec
+				device pnp 0c09.0 on end
+			end
+		end
+	end
+end
diff --git a/src/mainboard/google/ocelot/variants/baseboard/ocelot/include/baseboard/ec.h b/src/mainboard/google/ocelot/variants/baseboard/ocelot/include/baseboard/ec.h
new file mode 100644
index 0000000000..5804b303d0
--- /dev/null
+++ b/src/mainboard/google/ocelot/variants/baseboard/ocelot/include/baseboard/ec.h
@@ -0,0 +1,87 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#ifndef __BASEBOARD_EC_H__
+#define __BASEBOARD_EC_H__
+
+#include <baseboard/gpio.h>
+#include <ec/ec.h>
+#include <ec/google/chromeec/ec_commands.h>
+
+#define MAINBOARD_EC_SCI_EVENTS \
+	(EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_CONNECTED)      |\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_DISCONNECTED)   |\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY)           |\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_CRITICAL)  |\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_LOW)       |\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_STATUS)    |\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED)        |\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN)          |\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_MKBP)              |\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_MODE_CHANGE)       |\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_PD_MCU)            |\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_THRESHOLD) |\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_START)    |\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_STOP)     |\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_USB_MUX))
+#define MAINBOARD_EC_SMI_EVENTS \
+	(EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED))
+/* EC can wake from S5 with lid or power button */
+#define MAINBOARD_EC_S5_WAKE_EVENTS \
+	(EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN)     |\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_POWER_BUTTON))
+/*
+ * EC can wake from S3/S0ix with:
+ * 1. Lid open
+ * 2. AC Connect/Disconnect
+ * 3. Power button
+ * 4. Key press
+ * 5. Mode change
+ * 6. Low battery
+ */
+#define MAINBOARD_EC_S3_WAKE_EVENTS \
+	(EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_CONNECTED)     | \
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_DISCONNECTED)  | \
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_CRITICAL) | \
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_SHUTDOWN) | \
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEY_PRESSED)      | \
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_MODE_CHANGE)      | \
+	 MAINBOARD_EC_S5_WAKE_EVENTS)
+#define MAINBOARD_EC_S0IX_WAKE_EVENTS \
+	(EC_HOST_EVENT_MASK(EC_HOST_EVENT_HANG_DETECT) | \
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_USB_MUX)         | \
+	 MAINBOARD_EC_S3_WAKE_EVENTS)
+/* Log EC wake events plus EC shutdown events */
+#define MAINBOARD_EC_LOG_EVENTS \
+	(EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_SHUTDOWN) |\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_PANIC) |\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_SHUTDOWN))
+/*
+ * ACPI related definitions for ASL code.
+ */
+
+/* Enable EC backed ALS device in ACPI */
+#define EC_ENABLE_ALS_DEVICE
+
+/* Enable Keyboard Backlight */
+#define EC_ENABLE_KEYBOARD_BACKLIGHT
+
+/* Enable LID switch and provide wake pin for EC */
+#define EC_ENABLE_LID_SWITCH
+#define EC_ENABLE_WAKE_PIN      GPE_EC_WAKE
+
+/* Enable MKBP for buttons and switches */
+#define EC_ENABLE_MKBP_DEVICE
+
+/* Enable EC backed PD MCU device in ACPI */
+#define EC_ENABLE_PD_MCU_DEVICE
+
+#if !CONFIG(BOARD_GOOGLE_OCELOT)
+ #define EC_ENABLE_SYNC_IRQ      /* Enable tight timestamp / wake support */
+ #define EC_SYNC_IRQ_WAKE_CAPABLE /* Let the OS know ec_sync is wake capable */
+#endif
+
+#define SIO_EC_ENABLE_PS2K       /* Enable PS/2 Keyboard */
+#define SIO_EC_HOST_ENABLE       /* EC Host Interface Resources */
+#define SIO_EC_MEMMAP_ENABLE     /* EC Memory Map Resources */
+
+#endif /* __BASEBOARD_EC_H__ */
diff --git a/src/mainboard/google/ocelot/variants/baseboard/ocelot/include/baseboard/gpio.h b/src/mainboard/google/ocelot/variants/baseboard/ocelot/include/baseboard/gpio.h
new file mode 100644
index 0000000000..56c2fb0aca
--- /dev/null
+++ b/src/mainboard/google/ocelot/variants/baseboard/ocelot/include/baseboard/gpio.h
@@ -0,0 +1,21 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#ifndef __BASEBOARD_GPIO_H__
+#define __BASEBOARD_GPIO_H__
+
+#include <soc/gpe.h>
+#include <soc/gpio.h>
+
+/* eSPI virtual wire reporting */
+#define EC_SCI_GPI	GPE0_ESPI
+/*
+ * EC_SYNC_IRQ - GPIO IRQ for tight timestamps / wake support
+ * GPIO_PCH_WP - WP signal to PCH
+ */
+//TODO for Nuvo: #define EC_SYNC_IRQ	GPP_E07_IRQ
+#if CONFIG(BOARD_GOOGLE_OCELOT)
+ #define EC_SYNC_IRQ	0 /* Not Connected */
+#endif
+#define GPIO_PCH_WP	GPP_D02
+
+#endif /* __BASEBOARD_GPIO_H__ */
diff --git a/src/mainboard/google/ocelot/variants/baseboard/ocelot/memory.c b/src/mainboard/google/ocelot/variants/baseboard/ocelot/memory.c
new file mode 100644
index 0000000000..4f621f38ce
--- /dev/null
+++ b/src/mainboard/google/ocelot/variants/baseboard/ocelot/memory.c
@@ -0,0 +1,31 @@
+/* SPDX-License-Identifier: GPL-3.0-or-later */
+
+#include <baseboard/variants.h>
+
+static const struct mb_cfg baseboard_memcfg = {
+	.type = MEM_TYPE_LP5X,
+
+	/* TODO: Add Memory configuration */
+	.ect = 1, /* Early Command Training */
+};
+
+const struct mb_cfg *__weak variant_memory_params(void)
+{
+	return &baseboard_memcfg;
+}
+
+int __weak variant_memory_sku(void)
+{
+	return 0;
+}
+
+bool __weak variant_is_half_populated(void)
+{
+	return 0;
+}
+
+void __weak variant_get_spd_info(struct mem_spd *spd_info)
+{
+	spd_info->topo = MEM_TOPO_MEMORY_DOWN;
+	spd_info->cbfs_index = variant_memory_sku();
+}
diff --git a/src/mainboard/google/ocelot/variants/baseboard/ocelot/ramstage.c b/src/mainboard/google/ocelot/variants/baseboard/ocelot/ramstage.c
new file mode 100644
index 0000000000..030b587579
--- /dev/null
+++ b/src/mainboard/google/ocelot/variants/baseboard/ocelot/ramstage.c
@@ -0,0 +1,62 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <baseboard/variants.h>
+#include <ec/google/chromeec/ec.h>
+
+/*
+ * SKU_ID, TDP (Watts), pl1_min (milliWatts), pl1_max (milliWatts),
+ * pl2_min (milliWatts), pl2_max (milliWatts), pl4 (milliWatts)
+ */
+const struct cpu_tdp_power_limits power_optimized_limits[] = {
+	{
+		.mch_id = PCI_DID_INTEL_PTL_H_ID_1,
+		.cpu_tdp = TDP_25W,
+		.power_limits_index = PTL_H_1_CORE,
+		.pl1_min_power = 10000,
+		.pl1_max_power = 25000,
+		.pl2_min_power = 50000,
+		.pl2_max_power = 50000,
+		.pl4_power = 65000
+	},
+	{
+		.mch_id = PCI_DID_INTEL_PTL_H_ID_2,
+		.cpu_tdp = TDP_25W,
+		.power_limits_index = PTL_H_1_CORE,
+		.pl1_min_power = 10000,
+		.pl1_max_power = 25000,
+		.pl2_min_power = 50000,
+		.pl2_max_power = 50000,
+		.pl4_power = 65000
+	},
+	{
+		.mch_id = PCI_DID_INTEL_PTL_H_ID_3,
+		.cpu_tdp = TDP_25W,
+		.power_limits_index = PTL_H_2_CORE,
+		.pl1_min_power = 10000,
+		.pl1_max_power = 25000,
+		.pl2_min_power = 50000,
+		.pl2_max_power = 50000,
+		.pl4_power = 65000
+	},
+	{
+		.mch_id = PCI_DID_INTEL_PTL_H_ID_4,
+		.cpu_tdp = TDP_25W,
+		.power_limits_index = PTL_H_2_CORE,
+		.pl1_min_power = 10000,
+		.pl1_max_power = 25000,
+		.pl2_min_power = 50000,
+		.pl2_max_power = 50000,
+		.pl4_power = 65000
+	},
+};
+
+void baseboard_devtree_update(void)
+{
+	/* Don't optimize the power limit if booting with barrel attached */
+	if (google_chromeec_is_barrel_charger_present())
+		return;
+
+	if (!google_chromeec_is_battery_present())
+		variant_update_cpu_power_limits(power_optimized_limits,
+						ARRAY_SIZE(power_optimized_limits));
+}
diff --git a/src/mainboard/google/ocelot/variants/ocelot/Makefile.mk b/src/mainboard/google/ocelot/variants/ocelot/Makefile.mk
new file mode 100644
index 0000000000..eb361dfe89
--- /dev/null
+++ b/src/mainboard/google/ocelot/variants/ocelot/Makefile.mk
@@ -0,0 +1,9 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
+bootblock-y += gpio.c
+romstage-y += gpio.c
+romstage-y += memory.c
+romstage-$(CONFIG_FW_CONFIG) += fw_config.c
+ramstage-y += gpio.c
+ramstage-$(CONFIG_FW_CONFIG) += variant.c
+ramstage-$(CONFIG_FW_CONFIG) += fw_config.c
diff --git a/src/mainboard/google/ocelot/variants/ocelot/fw_config.c b/src/mainboard/google/ocelot/variants/ocelot/fw_config.c
new file mode 100644
index 0000000000..9419caf709
--- /dev/null
+++ b/src/mainboard/google/ocelot/variants/ocelot/fw_config.c
@@ -0,0 +1,651 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <baseboard/variants.h>
+#include <console/console.h>
+#include <fw_config.h>
+#include <gpio.h>
+#include <inttypes.h>
+
+/* t: base table; o: override table */
+#define GPIO_PADBASED_OVERRIDE(t, o) gpio_padbased_override(t, o, ARRAY_SIZE(o))
+/* t: table */
+#define GPIO_CONFIGURE_PADS(t) gpio_configure_pads(t, ARRAY_SIZE(t))
+
+static const struct pad_config i2s_enable_pads[] = {
+	/* I2S_MCLK1_OUT */
+	PAD_CFG_NF(GPP_D09, NONE, DEEP, NF2),
+	/* I2S0_SCLK_HDR */
+	PAD_CFG_NF(GPP_D10, NONE, DEEP, NF2),
+	/* I2S0_SFRM_HDR */
+	PAD_CFG_NF(GPP_D11, NONE, DEEP, NF2),
+	/* I2S0_TXD_HDR */
+	PAD_CFG_NF(GPP_D12, NONE, DEEP, NF2),
+	/* I2S0_RXD_HDR */
+	PAD_CFG_NF(GPP_D13, NONE, DEEP, NF2),
+	/* I2S1_SCLK_HDR */
+	PAD_CFG_NF(GPP_S00, NONE, DEEP, NF6),
+	/* I2S1_SFRM_HDR */
+	PAD_CFG_NF(GPP_S01, NONE, DEEP, NF6),
+	/* I2S1_TXD_HDR */
+	PAD_CFG_NF(GPP_S02, NONE, DEEP, NF6),
+	/* I2S1_RXD_HDR */
+	PAD_CFG_NF(GPP_S03, NONE, DEEP, NF6),
+
+	/* DMIC_CLK */
+	PAD_CFG_NF(GPP_D16, NONE, DEEP, NF3),
+	/* DMIC_DATA */
+	PAD_CFG_NF(GPP_D17, NONE, DEEP, NF3),
+
+	/* DMIC_CLK */
+	PAD_CFG_NF(GPP_S04, NONE, DEEP, NF5),
+	/* DMIC_DATA */
+	PAD_CFG_NF(GPP_S05, NONE, DEEP, NF5),
+};
+
+static const struct pad_config hda_enable_pads[] = {
+	/* HDA_BCLK */
+	PAD_CFG_NF(GPP_D10, NONE, DEEP, NF1),
+	/* HDA_SYNC */
+	PAD_CFG_NF(GPP_D11, NATIVE, DEEP, NF1),
+	/* HDA_SDO */
+	PAD_CFG_NF(GPP_D12, NATIVE, DEEP, NF1),
+	/* HDA_SDI_0 */
+	PAD_CFG_NF(GPP_D13, NATIVE, DEEP, NF1),
+	/* HDA_RST_B */
+	PAD_CFG_NF(GPP_D16, NONE, DEEP, NF1),
+	/* HDA_SDI_1 */
+	PAD_CFG_NF(GPP_D17, NATIVE, DEEP, NF1),
+
+	/* DMIC_CLK */
+	PAD_CFG_NF(GPP_S04, NONE, DEEP, NF5),
+	/* DMIC_DATA */
+	PAD_CFG_NF(GPP_S05, NONE, DEEP, NF5),
+};
+
+static const struct pad_config sndw_external_codec_enable_pads[] = {
+	/* Soundwire - External codec - JE Header */
+	/* SNDW3_CLK */
+	PAD_CFG_NF(GPP_S00, NONE, DEEP, NF1),
+	/* SNDW3_DATA0 */
+	PAD_CFG_NF(GPP_S01, NONE, DEEP, NF1),
+	/* SNDW0_CLK */
+	PAD_CFG_NF(GPP_S02, NONE, DEEP, NF3),
+	/* SNDW0_DATA */
+	PAD_CFG_NF(GPP_S03, NONE, DEEP, NF3),
+	/* SNDW2_CLK */
+	PAD_CFG_NF(GPP_S04, NONE, DEEP, NF2),
+	/* SNDW2_DATA */
+	PAD_CFG_NF(GPP_S05, NONE, DEEP, NF2),
+	/* SNDW1_CLK */
+	PAD_CFG_NF(GPP_S06, NONE, DEEP, NF3),
+	/* SNDW1_DATA */
+	PAD_CFG_NF(GPP_S07, NONE, DEEP, NF3),
+
+	/* GPP_D13: RST_HP_L */
+	PAD_CFG_GPO(GPP_D13, 1, PLTRST),
+};
+
+static const struct pad_config bt_i2s_enable_pads[] = {
+	/* GPP_V30 : [] ==> BT_I2S_BCLK - SSP2 */
+	PAD_CFG_NF(GPP_VGPIO30, NONE, DEEP, NF3),
+	/* GPP_V31 : [] ==> BT_I2S_SYNC - SSP2 */
+	PAD_CFG_NF(GPP_VGPIO31, NONE, DEEP, NF3),
+	/* GPP_V32 : [] ==> BT_I2S_SDO - SSP2 */
+	PAD_CFG_NF(GPP_VGPIO32, NONE, DEEP, NF3),
+	/* GPP_V33 : [] ==> BT_I2S_SDI - SSP2 */
+	PAD_CFG_NF(GPP_VGPIO33, NONE, DEEP, NF3),
+	/* GPP_V34 : [] ==> SSP_SCLK */
+	PAD_CFG_NF(GPP_VGPIO34, NONE, DEEP, NF1),
+	/* GPP_V35 : [] ==> SSP_SFRM */
+	PAD_CFG_NF(GPP_VGPIO35, NONE, DEEP, NF1),
+	/* GPP_V36 : [] ==> SSP_TXD */
+	PAD_CFG_NF(GPP_VGPIO36, NONE, DEEP, NF1),
+	/* GPP_V37 : [] ==> SSP_RXD */
+	PAD_CFG_NF(GPP_VGPIO37, NONE, DEEP, NF1),
+};
+
+static const struct pad_config bt_i2s_disable_pads[] = {
+	/* GPP_V30 : [] ==> BT_I2S_BCLK */
+	PAD_NC(GPP_VGPIO30, NONE),
+	/* GPP_V31 : [] ==> BT_I2S_SYNC */
+	PAD_NC(GPP_VGPIO31, NONE),
+	/* GPP_V32 : [] ==> BT_I2S_SDO */
+	PAD_NC(GPP_VGPIO32, NONE),
+	/* GPP_V33 : [] ==> BT_I2S_SDI */
+	PAD_NC(GPP_VGPIO33, NONE),
+	/* GPP_V34 : [] ==> SSP2_SCLK */
+	PAD_NC(GPP_VGPIO34, NONE),
+	/* GPP_V35 : [] ==> SSP2_SFRM */
+	PAD_NC(GPP_VGPIO35, NONE),
+	/* GPP_V36 : [] ==> SSP_TXD */
+	PAD_NC(GPP_VGPIO36, NONE),
+	/* GPP_V37 : [] ==> SSP_RXD */
+	PAD_NC(GPP_VGPIO37, NONE),
+};
+
+static const struct pad_config sndw_alc722_enable_pads[] = {
+	/* SNDW3_CLK   */
+	PAD_CFG_NF(GPP_S00, NONE, DEEP, NF1),
+	/* SNDW3_DATA0 */
+	PAD_CFG_NF(GPP_S01, NONE, DEEP, NF1),
+	/* SNDW3_DATA1 */
+	PAD_CFG_NF(GPP_S02, NONE, DEEP, NF1),
+	/* SNDW3_DATA2 */
+	PAD_CFG_NF(GPP_S03, NONE, DEEP, NF1),
+	/* DMIC_CLK_A0 */
+	PAD_CFG_NF(GPP_S04, NONE, DEEP, NF5),
+	/* DMIC_DATA_0 */
+	PAD_CFG_NF(GPP_S05, NONE, DEEP, NF5),
+	/* SNDW1_CLK   */
+	PAD_CFG_NF(GPP_S06, NONE, DEEP, NF3),
+	/* SNDW1_DATA  */
+	PAD_CFG_NF(GPP_S07, NONE, DEEP, NF3),
+
+	/* DMIC_CLK */
+	PAD_CFG_NF(GPP_D16, NONE, DEEP, NF3),
+	/* DMIC_DATA */
+	PAD_CFG_NF(GPP_D17, NONE, DEEP, NF3),
+};
+
+static const struct pad_config audio_disable_pads[] = {
+	PAD_NC(GPP_S00, NONE),
+	PAD_NC(GPP_S01, NONE),
+	PAD_NC(GPP_S02, NONE),
+	PAD_NC(GPP_S03, NONE),
+	PAD_NC(GPP_S04, NONE),
+	PAD_NC(GPP_S05, NONE),
+	PAD_NC(GPP_S06, NONE),
+	PAD_NC(GPP_S07, NONE),
+	PAD_NC(GPP_D09, NONE),
+	PAD_NC(GPP_D10, NONE),
+	PAD_NC(GPP_D11, NONE),
+	PAD_NC(GPP_D12, NONE),
+	PAD_NC(GPP_D13, NONE),
+	PAD_NC(GPP_D16, NONE),
+	PAD_NC(GPP_D17, NONE),
+};
+
+static const struct pad_config pre_mem_x1slot_pads[] = {
+	/* GPP_A08:     X1_PCIE_SLOT_PWR_EN */
+	PAD_CFG_GPO(GPP_A08, 0, PLTRST),
+};
+static const struct pad_config x1slot_pads[] = {
+	/* GPP_A08:     X1_PCIE_SLOT_PWR_EN */
+	PAD_CFG_GPO(GPP_A08, 1, PLTRST),
+	/* GPP_D19:     X1_DT_PCIE_RST_N */
+	PAD_CFG_GPO(GPP_D19, 1, PLTRST),
+	/* GPP_B25:     X1_SLOT_WAKE_N */
+	PAD_CFG_GPI_SCI_LOW(GPP_B25, NONE, DEEP, LEVEL),
+};
+
+static const struct pad_config x1slot_disable_pads[] = {
+	/* GPP_A08:     X1_PCIE_SLOT_PWR_EN */
+	PAD_CFG_GPO(GPP_A08, 0, PLTRST),
+	/* GPP_D19:     X1_DT_PCIE_RST_N */
+	PAD_NC(GPP_D19, NONE),
+	/* GPP_B25:     X1_SLOT_WAKE_N */
+	PAD_NC(GPP_B25, NONE)
+};
+
+/*
+ * WWAN: power sequence requires three stages:
+ * step 1: 3.3V power, FCP# (Full Card Power), RST#, and PERST# off
+ * step 2: deassert FCP#
+ * step 3: deassert RST# first, and then PERST#.
+ * NOTE: Since PERST# is gated by platform reset, PERST# deassertion will happen
+ * at much later time and time between RST# and PERSET# is guaranteed.
+ */
+static const struct pad_config pre_mem_wwan_pwr_seq1_pads[] = {
+	/* GPP_H16:     WWAN_PWREN */
+	PAD_CFG_GPO(GPP_H16, 1, PLTRST),
+	/* GPP_A09:  M.2_WWAN_FCP_OFF_N */
+	PAD_CFG_GPO(GPP_A09, 0, PLTRST),
+	/* GPP_B20:     M.2_WWAN_RST_N */
+	PAD_CFG_GPO(GPP_B20, 0, PLTRST),
+	/* GPP_D03:     M.2_WWAN_PERST_GPIO_N */
+	PAD_CFG_GPO(GPP_D03, 0, PLTRST),
+};
+
+static const struct pad_config pre_mem_wwan_pwr_seq2_pads[] = {
+	/* GPP_A09:     M.2_WWAN_FCP_OFF_N */
+	PAD_CFG_GPO(GPP_A09, 1, PLTRST),
+};
+
+static const struct pad_config wwan_pwr_seq3_pads[] = {
+	/* GPP_D03:     M.2_WWAN_PERST_GPIO_N */
+	PAD_CFG_GPO(GPP_D03, 1, PLTRST),
+	/* GPP_B20:     M.2_WWAN_RST_N */
+	PAD_CFG_GPO(GPP_B20, 1, PLTRST),
+	/* GPP_E02:     WWAN_WAKE_GPIO_N */
+	PAD_CFG_GPI_SCI_LOW(GPP_E02, NONE, DEEP, LEVEL),
+};
+
+static const struct pad_config wwan_disable_pads[] = {
+	/* GPP_A09:     M.2_WWAN_FCP_OFF_N */
+	PAD_NC(GPP_A09, NONE),
+	/* GPP_D03:     M.2_WWAN_PERST_GPIO_N */
+	PAD_NC(GPP_D03, NONE),
+	/* GPP_B20:     M.2_WWAN_RST_N */
+	PAD_NC(GPP_B20, NONE),
+	/* GPP_H16:     WWAN_PWREN */
+	PAD_NC(GPP_H16, NONE),
+	/* GPP_A10:     M.2_WWAN_DISABLE_N */
+	PAD_NC(GPP_A10, NONE),
+	/* GPP_E02:     WWAN_WAKE_GPIO_N */
+	PAD_NC(GPP_E02, NONE),
+};
+
+/* Gen4 NVME: at the top M.2 slot */
+static const struct pad_config pre_mem_gen4_ssd_pwr_pads[] = {
+	/* GPP_B10:     GEN4_SSD_PWREN */
+	PAD_CFG_GPO(GPP_B10, 0, PLTRST),
+};
+
+static const struct pad_config gen4_ssd_pads[] = {
+	/* GPP_B10:     GEN4_SSD_PWREN */
+	PAD_CFG_GPO(GPP_B10, 1, PLTRST),
+	/* GPP_B09:     M2_GEN4_SSD_RESET_N */
+	PAD_CFG_GPO(GPP_B09, 1, PLTRST),
+};
+
+static const struct pad_config ufs_enable_pads[] = {
+	/* GPP_D21:     GPP_D21_UFS_REFCLK */
+	PAD_CFG_NF(GPP_D21, NONE, DEEP, NF1),
+};
+
+/* Gen5 NVME: at the bottom M.2 slot */
+static const struct pad_config pre_mem_gen5_ssd_pwr_pads[] = {
+	/* GPP_B16:     GEN5_SSD_PWREN */
+	PAD_CFG_GPO(GPP_B16, 0, PLTRST),
+};
+
+static const struct pad_config gen5_ssd_pads[] = {
+	/* GPP_B16:     GEN5_SSD_PWREN */
+	PAD_CFG_GPO(GPP_B16, 1, PLTRST),
+	/* GPP_E03:     M2_GEN5_SSD_RESET_N */
+	PAD_CFG_GPO(GPP_E03, 1, PLTRST),
+};
+
+static const struct pad_config peg_x4slot_wake_disable_pads[] = {
+	/* GPP_D24:     PEG_SLOT_WAKE_N */
+	PAD_NC(GPP_D24, NONE),
+	/* GPP_D25:     X4_SLOT_WAKE_N */
+	PAD_NC(GPP_D25, NONE),
+};
+
+static const struct pad_config pcie_wlan_enable_pads[] = {
+	/* GPP_A11:     WLAN_RST_N */
+	PAD_CFG_GPO(GPP_A11, 1, PLTRST),
+	/* GPP_A12:     WIFI_WAKE_N */
+	PAD_CFG_GPI_SCI_LOW(GPP_A12, NONE, DEEP, LEVEL),
+};
+
+static const struct pad_config pcie_wlan_disable_pads[] = {
+	/* GPP_A11:     WLAN_RST_N */
+	PAD_NC(GPP_A11, NONE),
+	/* GPP_A12:     WIFI_WAKE_N */
+	PAD_NC(GPP_A12, NONE),
+};
+
+static const struct pad_config cnvi_enable_pads[] = {
+	/* NOTE: IOSSTAGE: 'Ignore' for S0ix */
+	PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_F00, NONE, DEEP, NF1),
+	/* GPP_F01:     M.2_CNV_BRI_RSP_BT_UART2_RXD */
+	/* NOTE: IOSSTAGE: 'Ignore' for S0ix */
+	PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_F01, NONE, DEEP, NF1),
+	/* GPP_F02:     M.2_CNV_RGI_DT_BT_UART2_TXD */
+	/* NOTE: IOSSTAGE: 'Ignore' for S0ix */
+	PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_F02, NONE, DEEP, NF1),
+	/* GPP_F03:     M.2_CNV_RGI_RSP_BT_UART2_CTS_N */
+	/* NOTE: IOSSTAGE: 'Ignore' for S0ix */
+	PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_F03, NONE, DEEP, NF1),
+	/* GPP_F04:     CNV_RF_RESET_R_N */
+	/* NOTE: IOSSTAGE: 'Ignore' for S0ix */
+	PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_F04, NONE, DEEP, NF1),
+	/* GPP_F05:     CRF_CLKREQ_R */
+	/* NOTE: IOSSTAGE: 'Ignore' for S0ix */
+	PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_F05, NONE, DEEP, NF3),
+	/* GPP_A16:     BT_RF_KILL_N */
+	PAD_CFG_GPO(GPP_A16, 1, DEEP),
+	/* GPP_A17:     WIFI_RF_KILL_N */
+	PAD_CFG_GPO(GPP_A17, 1, DEEP),
+};
+
+static const struct pad_config cnvi_disable_pads[] = {
+	/* GPP_F00:     M.2_CNV_BRI_DT_BT_UART2_RTS_N */
+	PAD_NC(GPP_F00, NONE),
+	/* GPP_F01:     M.2_CNV_BRI_RSP_BT_UART2_RXD */
+	PAD_NC(GPP_F01, NONE),
+	/* GPP_F02:     M.2_CNV_RGI_DT_BT_UART2_TXD */
+	PAD_NC(GPP_F02, NONE),
+	/* GPP_F03:     M.2_CNV_RGI_RSP_BT_UART2_CTS_N */
+	PAD_NC(GPP_F03, NONE),
+	/* GPP_F04:     CNV_RF_RESET_R_N */
+	PAD_NC(GPP_F04, NONE),
+	/* GPP_F05:     CRF_CLKREQ_R */
+	PAD_NC(GPP_F05, NONE),
+
+	/* GPP_A16:     BT_RF_KILL_N */
+	PAD_NC(GPP_A16, NONE),
+	/* GPP_A17:     WIFI_RF_KILL_N */
+	PAD_NC(GPP_A17, NONE),
+};
+
+static const struct pad_config touchscreen_disable_pads[] = {
+	/* GPP_F08:     TCH_PNL1_PWR_EN */
+	PAD_CFG_GPO(GPP_F08, 0, PLTRST),
+
+	/* GPP_E11:     THC0_SPI1_CLK_TCH_PNL1 */
+	PAD_NC(GPP_E11, NONE),
+	/* GPP_E12:     THC0_SPI1_IO_0_I2C4_SCL_TCH_PNL1 NF8: I2C4_SCL */
+	PAD_NC(GPP_E12, NONE),
+	/* GPP_E13:     THC0_SPI1_IO_1_I2C4_SDA_TCH_PNL1 NF8: I2C4 SDA */
+	PAD_NC(GPP_E13, NONE),
+	/* GPP_E14:     THC0_SPI1_IO_2_TCH_PNL1 */
+	PAD_NC(GPP_E14, NONE),
+	/* GPP_E15:     THC0_SPI1_IO_3_TCH_PNL1 */
+	PAD_NC(GPP_E15, NONE),
+	/* GPP_E16:     THC0_SPI1_RST_N_TCH_PNL1 */
+	PAD_NC(GPP_E16, NONE),
+	/* GPP_E17:     THC0_SPI1_CS0_N_TCH_PNL1 */
+	PAD_NC(GPP_E17, NONE),
+	/* GPP_E18:     THC0_SPI1_INT_N_TCH_PNL1 */
+	PAD_NC(GPP_E18, NONE),
+};
+
+static const struct pad_config touchscreen_lpss_i2c_enable_pads[] = {
+	/* GPP_E11:     THC0_SPI1_CLK_TCH_PNL1 */
+	PAD_NC(GPP_E11, NONE),
+	/* GPP_E12:     THC0_SPI1_IO_0_I2C4_SCL_TCH_PNL1 NF8: I2C4_SCL */
+	PAD_CFG_NF(GPP_E12, NONE, DEEP, NF8),
+	/* GPP_E13:     THC0_SPI1_IO_1_I2C4_SDA_TCH_PNL1 NF8: I2C4 SDA */
+	PAD_CFG_NF(GPP_E13, NONE, DEEP, NF8),
+	/* GPP_E14:     THC0_SPI1_IO_2_TCH_PNL1 */
+	PAD_NC(GPP_E14, NONE),
+	/* GPP_E15:     THC0_SPI1_IO_3_TCH_PNL1 */
+	PAD_NC(GPP_E15, NONE),
+	/* GPP_E16:     THC0_SPI1_RST_N_TCH_PNL1 */
+	PAD_CFG_GPO(GPP_E16, 1, DEEP),
+	/* GPP_E17:     THC0_SPI1_CS0_N_TCH_PNL1 */
+	PAD_NC(GPP_E17, NONE),
+	/* GPP_E18:     THC0_SPI1_INT_N_TCH_PNL1 */
+	PAD_CFG_GPI_APIC(GPP_E18, NONE, PLTRST, LEVEL, NONE),
+};
+
+static const struct pad_config touchscreen_thc_i2c_enable_pads[] = {
+	/* GPP_E11:     THC0_SPI1_CLK_TCH_PNL1 */
+	PAD_NC(GPP_E11, NONE),
+	/* GPP_E12:     THC0_SPI1_IO_0_I2C4_SCL_TCH_PNL1 NF1: THC I2C0_SCL */
+	PAD_CFG_NF(GPP_E12, NONE, DEEP, NF1),
+	/* GPP_E13:     THC0_SPI1_IO_1_I2C4_SDA_TCH_PNL1 NF1: THC I2C0 SDA */
+	PAD_CFG_NF(GPP_E13, NONE, DEEP, NF1),
+	/* GPP_E14:     THC0_SPI1_IO_2_TCH_PNL1 */
+	PAD_NC(GPP_E14, NONE),
+	/* GPP_E15:     THC0_SPI1_IO_3_TCH_PNL1 */
+	PAD_NC(GPP_E15, NONE),
+	/* GPP_E16:     THC0_SPI1_RST_N_TCH_PNL1 */
+	PAD_CFG_GPO(GPP_E16, 1, DEEP),
+	/* GPP_E17:     THC0_SPI1_CS0_N_TCH_PNL1 */
+	PAD_NC(GPP_E17, NONE),
+	/* GPP_E18:     THC0_SPI1_INT_N_TCH_PNL1 */
+	PAD_CFG_GPI_APIC(GPP_E18, NONE, PLTRST, LEVEL, NONE),
+};
+
+static const struct pad_config touchscreen_gspi_enable_pads[] = {
+	/* GPP_E11:     THC0_SPI1_CLK_TCH_PNL1 NF5: GSPI0 */
+	PAD_CFG_NF(GPP_E11, NONE, DEEP, NF5),
+	/* GPP_E12:     THC0_SPI1_IO_0_I2C4_SCL_TCH_PNL1 NF5: GSPI0 */
+	PAD_CFG_NF(GPP_E12, NONE, DEEP, NF5),
+	/* GPP_E13:     THC0_SPI1_IO_1_I2C4_SDA_TCH_PNL1 NF5: GSPI0 */
+	PAD_CFG_NF(GPP_E13, NONE, DEEP, NF5),
+	/* GPP_E14:     THC0_SPI1_IO_2_TCH_PNL1 */
+	PAD_NC(GPP_E14, NONE),
+	/* GPP_E15:     THC0_SPI1_IO_3_TCH_PNL1 */
+	PAD_NC(GPP_E15, NONE),
+	/* GPP_E16:     THC0_SPI1_RST_N_TCH_PNL1 */
+	PAD_CFG_GPO(GPP_E16, 1, DEEP),
+	/* GPP_E17:     THC0_SPI1_CS0_N_TCH_PNL1 NF5: GSPI0 */
+	PAD_CFG_NF(GPP_E17, NONE, DEEP, NF5),
+	/* GPP_E18:     THC0_SPI1_INT_N_TCH_PNL1 */
+	PAD_CFG_GPI_APIC(GPP_E18, NONE, PLTRST, EDGE_SINGLE, INVERT)
+};
+
+static const struct pad_config touchscreen_thc_spi_enable_pads[] = {
+	/* GPP_E11:     THC0_SPI1_CLK_TCH_PNL1 NF3: THC HID-SPI */
+	PAD_CFG_NF(GPP_E11, NONE, DEEP, NF3),
+	/* GPP_E12:     THC0_SPI1_IO_0_I2C4_SCL_TCH_PNL1 NF3: THC HID-SPI */
+	PAD_CFG_NF(GPP_E12, NONE, DEEP, NF3),
+	/* GPP_E13:     THC0_SPI1_IO_1_I2C4_SDA_TCH_PNL1 NF3: THC HID-SPI */
+	PAD_CFG_NF(GPP_E13, NONE, DEEP, NF3),
+	/* GPP_E14:     THC0_SPI1_IO_2_TCH_PNL1 NF3: THC HID-SPI */
+	PAD_CFG_NF(GPP_E14, NONE, DEEP, NF3),
+	/* GPP_E15:     THC0_SPI1_IO_3_TCH_PNL1 NF3: THC HID-SPI */
+	PAD_CFG_NF(GPP_E15, NONE, DEEP, NF3),
+	/* GPP_E16:     THC0_SPI1_RST_N_TCH_PNL1 NF3: THC HID-SPI */
+	/* THC NOTE: use GPO instead of NF for THC0 Rst */
+	PAD_CFG_GPO(GPP_E16, 1, DEEP),
+	/* GPP_E17:     THC0_SPI1_CS0_N_TCH_PNL1 NF3: THC HID-SPI */
+	PAD_CFG_NF(GPP_E17, NONE, DEEP, NF3),
+	/* GPP_E18:     THC0_SPI1_INT_N_TCH_PNL1 NF3: THC HID-SPI */
+	PAD_CFG_NF(GPP_E18, NONE, DEEP, NF3),
+};
+
+static const struct pad_config touchpad_thc_i2c_enable_pads[] = {
+	/* GPP_F12:     NF1: thc_i2c1_scl */
+	PAD_CFG_NF(GPP_F12, NONE, DEEP, NF1),
+	/* GPP_F13:     NF1: thc_i2c1_sda */
+	PAD_CFG_NF(GPP_F13, NONE, DEEP, NF1),
+};
+
+static const struct pad_config touchpad_lpss_i2c_enable_pads[] = {
+	/* GPP_F12:     THC_I2C1_SCL_TCH_PAD */
+	PAD_CFG_NF(GPP_F12, NONE, DEEP, NF8),
+	/* GPP_F13:     THC_I2C1_SDA_TCH_PAD */
+	PAD_CFG_NF(GPP_F13, NONE, DEEP, NF8),
+	/* GPP_A13:     TCH_PAD_INT_N */
+	PAD_CFG_GPI_IRQ_WAKE(GPP_A13, NONE, PWROK, EDGE_SINGLE, INVERT),
+};
+
+static const struct pad_config touchpad_i2c_disable_pads[] = {
+	/* GPP_F12:     THC_I2C1_SCL_TCH_PAD */
+	PAD_NC(GPP_F12, NONE),
+	/* GPP_F13:     THC_I2C1_SDA_TCH_PAD */
+	PAD_NC(GPP_F13, NONE),
+	/* GPP_A13:     TCH_PAD_INT_N */
+	PAD_NC(GPP_A13, NONE),
+};
+
+static const struct pad_config ish_disable_pads[] = {
+	/* GPP_D06:     NC */
+	PAD_NC(GPP_D06, NONE),
+	/* GPP_E05:     NC */
+	PAD_NC(GPP_E05, NONE),
+	/* GPP_F23:     NC */
+	PAD_NC(GPP_F23, NONE),
+};
+
+static const struct pad_config ish_enable_pads[] = {
+	/* GPP_D06:     ISH_UART0_TXD */
+	PAD_CFG_NF(GPP_D06, NONE, DEEP, NF2),
+	/* GPP_E05:     ISH_GP_7_SNSR_HDR */
+	PAD_CFG_NF(GPP_E05, NONE, DEEP, NF4),
+	/* GPP_F23:     ISH_GP_9A */
+	PAD_CFG_NF(GPP_F23, NONE, DEEP, NF8),
+};
+
+static const struct pad_config fp_disable_pads[] = {
+	PAD_NC(GPP_C15, NONE),
+	/* GPP_D01:     MOD_TCSS1_TYP_A_VBUS_EN */
+	PAD_CFG_GPO(GPP_D01, 1, DEEP),
+	/* FIXME: b/390031369
+	 * use dedicated GPIO PIN for codec enable
+	 * when FPS is enabled.
+	 */
+	/* GPP_E19:     CODEC_EN */
+	PAD_CFG_GPO(GPP_E19, 1, PLTRST),
+	PAD_NC(GPP_E20, NONE),
+	PAD_NC(GPP_F14, NONE),
+	PAD_NC(GPP_F15, NONE),
+	PAD_NC(GPP_F16, NONE),
+	PAD_NC(GPP_F18, NONE),
+};
+
+static const struct pad_config fp_enable_pads[] = {
+	/* GPP_C15:     FPS_RST_N */
+	PAD_CFG_GPO_LOCK(GPP_C15, 1, LOCK_CONFIG),
+	/* GPP_D01:     FPS_SOC_INT_L */
+	PAD_CFG_GPI_IRQ_WAKE(GPP_D01, NONE, PWROK, LEVEL, INVERT),
+	/* GPP_E19:     FPMCU_PWREN */
+	PAD_CFG_GPO(GPP_E19, 1, DEEP),
+	/* GPP_E20:     FPMCU_FW_UPDATE */
+	PAD_CFG_GPO_LOCK(GPP_E20, 0, LOCK_CONFIG),
+	/* GPP_F14:     GPSI0A_MOSI */
+	PAD_CFG_NF(GPP_F14, NONE, DEEP, NF8),
+	/* GPP_F15:     GSPI0A_MISO */
+	PAD_CFG_NF(GPP_F15, NONE, DEEP, NF8),
+	/* GPP_F16:     GPSI0A_CLK */
+	PAD_CFG_NF(GPP_F16, NONE, DEEP, NF8),
+	/* GPP_F18:     GSPI0A_CS0 */
+	PAD_CFG_NF(GPP_F18, NONE, DEEP, NF8),
+};
+
+static const struct pad_config pre_mem_fp_enable_pads[] = {
+	/* GPP_C15:     FPS_RST_N */
+	PAD_CFG_GPO(GPP_C15, 0, DEEP),
+};
+
+void fw_config_configure_pre_mem_gpio(void)
+{
+	if (!fw_config_is_provisioned()) {
+		printk(BIOS_WARNING, "FW_CONFIG is not provisioned, Exiting\n");
+		return;
+	}
+
+	if (!fw_config_probe(FW_CONFIG(CELLULAR, CELLULAR_ABSENT)))
+		GPIO_CONFIGURE_PADS(pre_mem_wwan_pwr_seq1_pads);
+
+	if (fw_config_probe(FW_CONFIG(STORAGE, STORAGE_NVME_GEN4))) {
+		GPIO_CONFIGURE_PADS(pre_mem_gen4_ssd_pwr_pads);
+	} else if (fw_config_probe(FW_CONFIG(STORAGE, STORAGE_NVME_GEN5))) {
+		GPIO_CONFIGURE_PADS(pre_mem_gen5_ssd_pwr_pads);
+	} else if (fw_config_probe(FW_CONFIG(STORAGE, STORAGE_UNKNOWN))) {
+		GPIO_CONFIGURE_PADS(pre_mem_gen4_ssd_pwr_pads);
+		GPIO_CONFIGURE_PADS(pre_mem_gen5_ssd_pwr_pads);
+	}
+
+	if (!fw_config_probe(FW_CONFIG(SD, SD_NONE)))
+		GPIO_CONFIGURE_PADS(pre_mem_x1slot_pads);
+
+	/*
+	 * NOTE: We place WWAN sequence 2 here. According to the WWAN FIBOCOM
+	 * FM350-GL datasheet, the minimum time requirement (Tpr: time between 3.3V
+	 * and FCP#) is '0'. Therefore, it will be fine even though there is no
+	 * GPIO configured for other PADs via fw_config to have the time delay
+	 * introduced in between sequence 1 and 2. Also, FCP# was not the last PAD
+	 * configured in sequence 1. Although the Tpr is '0' in the datasheet, three
+	 * stages are preserved at this time to guarantee the sequence shown in the
+	 * datasheet timing diagram.
+	 */
+	if (!fw_config_probe(FW_CONFIG(CELLULAR, CELLULAR_ABSENT)))
+		GPIO_CONFIGURE_PADS(pre_mem_wwan_pwr_seq2_pads);
+
+	if (fw_config_probe(FW_CONFIG(FP, FP_PRESENT)))
+		GPIO_CONFIGURE_PADS(pre_mem_fp_enable_pads);
+
+}
+
+void fw_config_gpio_padbased_override(struct pad_config *padbased_table)
+{
+	if (!fw_config_is_provisioned()) {
+		printk(BIOS_WARNING, "FW_CONFIG is not provisioned, Exiting\n");
+		return;
+	}
+
+	if (fw_config_probe(FW_CONFIG(STORAGE, STORAGE_NVME_GEN4))) {
+		GPIO_PADBASED_OVERRIDE(padbased_table, gen4_ssd_pads);
+	} else if (fw_config_probe(FW_CONFIG(STORAGE, STORAGE_NVME_GEN5))) {
+		GPIO_PADBASED_OVERRIDE(padbased_table, gen5_ssd_pads);
+	} else if (fw_config_probe(FW_CONFIG(STORAGE, STORAGE_UFS))) {
+		GPIO_PADBASED_OVERRIDE(padbased_table, ufs_enable_pads);
+	} else if (fw_config_probe(FW_CONFIG(STORAGE, STORAGE_UNKNOWN))) {
+		GPIO_PADBASED_OVERRIDE(padbased_table, gen4_ssd_pads);
+		GPIO_PADBASED_OVERRIDE(padbased_table, gen5_ssd_pads);
+		GPIO_PADBASED_OVERRIDE(padbased_table, ufs_enable_pads);
+	}
+
+	if (fw_config_probe(FW_CONFIG(AUDIO, AUDIO_NONE))) {
+		GPIO_PADBASED_OVERRIDE(padbased_table, audio_disable_pads);
+		GPIO_PADBASED_OVERRIDE(padbased_table, bt_i2s_disable_pads);
+	} else if (fw_config_probe(FW_CONFIG(AUDIO, AUDIO_MAX98360_ALC5682I_I2S))) {
+		printk(BIOS_INFO, "Configure GPIOs for I2S MAX98360 ALC5682 audio.\n");
+		GPIO_PADBASED_OVERRIDE(padbased_table, i2s_enable_pads);
+		printk(BIOS_INFO, "Configure GPIOs for BT offload mode.\n");
+		GPIO_PADBASED_OVERRIDE(padbased_table, bt_i2s_enable_pads);
+	} else if (fw_config_probe(FW_CONFIG(AUDIO, AUDIO_MAX98373_ALC5682_SNDW))) {
+		GPIO_PADBASED_OVERRIDE(padbased_table, sndw_external_codec_enable_pads);
+		GPIO_PADBASED_OVERRIDE(padbased_table, bt_i2s_disable_pads);
+	} else if (fw_config_probe(FW_CONFIG(AUDIO, AUDIO_ALC722_SNDW)) ||
+			fw_config_probe(FW_CONFIG(AUDIO, AUDIO_ALC721_SNDW))) {
+		printk(BIOS_INFO, "Configure GPIOs for Soundwire audio.\n");
+		GPIO_PADBASED_OVERRIDE(padbased_table, sndw_alc722_enable_pads);
+		printk(BIOS_INFO, "Configure GPIOs for BT offload mode.\n");
+		GPIO_PADBASED_OVERRIDE(padbased_table, bt_i2s_enable_pads);
+	} else if (fw_config_probe(FW_CONFIG(AUDIO, AUDIO_ALC256_HDA))) {
+		printk(BIOS_INFO, "Configure GPIOs for HDA ALC 256 mode.\n");
+		GPIO_PADBASED_OVERRIDE(padbased_table, hda_enable_pads);
+		GPIO_PADBASED_OVERRIDE(padbased_table, bt_i2s_disable_pads);
+	}
+
+	if (fw_config_probe(FW_CONFIG(WIFI, WIFI_PCIE_6)) ||
+		fw_config_probe(FW_CONFIG(WIFI, WIFI_PCIE_7))) {
+		GPIO_PADBASED_OVERRIDE(padbased_table, pcie_wlan_enable_pads);
+		GPIO_PADBASED_OVERRIDE(padbased_table, cnvi_disable_pads);
+	} else if (fw_config_probe(FW_CONFIG(WIFI, WIFI_CNVI_6)) ||
+		fw_config_probe(FW_CONFIG(WIFI, WIFI_CNVI_7))) {
+		GPIO_PADBASED_OVERRIDE(padbased_table, cnvi_enable_pads);
+		GPIO_PADBASED_OVERRIDE(padbased_table, pcie_wlan_disable_pads);
+	}
+
+	if (fw_config_probe(FW_CONFIG(CELLULAR, CELLULAR_PCIE)) ||
+		fw_config_probe(FW_CONFIG(CELLULAR, CELLULAR_USB))) {
+		GPIO_PADBASED_OVERRIDE(padbased_table, wwan_pwr_seq3_pads);
+	} else {
+		GPIO_PADBASED_OVERRIDE(padbased_table, wwan_disable_pads);
+	}
+
+	if (fw_config_probe(FW_CONFIG(SD, SD_NONE)))
+		GPIO_PADBASED_OVERRIDE(padbased_table, x1slot_disable_pads);
+	else
+		GPIO_PADBASED_OVERRIDE(padbased_table, x1slot_pads);
+
+	if (fw_config_probe(FW_CONFIG(TOUCHPAD, TOUCHPAD_LPSS_I2C)))
+		GPIO_PADBASED_OVERRIDE(padbased_table, touchpad_lpss_i2c_enable_pads);
+	else if (fw_config_probe(FW_CONFIG(TOUCHPAD, TOUCHPAD_THC_I2C)))
+		GPIO_PADBASED_OVERRIDE(padbased_table, touchpad_thc_i2c_enable_pads);
+	else
+		GPIO_PADBASED_OVERRIDE(padbased_table, touchpad_i2c_disable_pads);
+
+	if (fw_config_probe(FW_CONFIG(TOUCHSCREEN, TOUCHSCREEN_LPSS_I2C)))
+		GPIO_PADBASED_OVERRIDE(padbased_table, touchscreen_lpss_i2c_enable_pads);
+	else if (fw_config_probe(FW_CONFIG(TOUCHSCREEN, TOUCHSCREEN_THC_I2C)))
+		GPIO_PADBASED_OVERRIDE(padbased_table, touchscreen_thc_i2c_enable_pads);
+	else if (fw_config_probe(FW_CONFIG(TOUCHSCREEN, TOUCHSCREEN_GSPI)))
+		GPIO_PADBASED_OVERRIDE(padbased_table, touchscreen_gspi_enable_pads);
+	else if (fw_config_probe(FW_CONFIG(TOUCHSCREEN, TOUCHSCREEN_THC_SPI)))
+		GPIO_PADBASED_OVERRIDE(padbased_table, touchscreen_thc_spi_enable_pads);
+	else
+		GPIO_PADBASED_OVERRIDE(padbased_table, touchscreen_disable_pads);
+
+	if (fw_config_probe(FW_CONFIG(ISH, ISH_DISABLE)))
+		GPIO_PADBASED_OVERRIDE(padbased_table, ish_disable_pads);
+	else
+		GPIO_PADBASED_OVERRIDE(padbased_table, ish_enable_pads);
+
+	/* NOTE: disable PEG (x8 slot) and x4 slot wake for now */
+	GPIO_PADBASED_OVERRIDE(padbased_table, peg_x4slot_wake_disable_pads);
+
+	if (fw_config_probe(FW_CONFIG(FP, FP_PRESENT)))
+		GPIO_CONFIGURE_PADS(fp_enable_pads);
+	else
+		GPIO_CONFIGURE_PADS(fp_disable_pads);
+}
diff --git a/src/mainboard/google/ocelot/variants/ocelot/gpio.c b/src/mainboard/google/ocelot/variants/ocelot/gpio.c
new file mode 100644
index 0000000000..1c1219228c
--- /dev/null
+++ b/src/mainboard/google/ocelot/variants/ocelot/gpio.c
@@ -0,0 +1,424 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <baseboard/gpio.h>
+#include <baseboard/variants.h>
+#include <boardid.h>
+#include <soc/gpio.h>
+
+/* Pad configuration in ramstage*/
+static const struct pad_config gpio_table[] = {
+	/* GPP_A00:     ESPI_IO0_EC_R */
+	/*  GPP_A00 : GPP_A00 ==> ESPI_IO0_EC_R configured on reset, do not touch */
+
+	/* GPP_A01:     ESPI_IO1_EC_R */
+	/*  GPP_A01 : GPP_A01 ==> ESPI_IO1_EC_R configured on reset, do not touch */
+
+	/* GPP_A02:     ESPI_IO2_EC_R */
+	/*  GPP_A02 : GPP_A02 ==> ESPI_IO2_EC_R configured on reset, do not touch */
+
+	/* GPP_A03:     ESPI_IO3_EC_R */
+	/*  GPP_A03 : GPP_A03 ==> ESPI_IO3_EC_R configured on reset, do not touch */
+
+	/* GPP_A04:     ESPI_CS0_EC_R_N */
+	/*  GPP_A04 : GPP_A04 ==> ESPI_CS0_HDR_L configured on reset, do not touch */
+
+	/* GPP_A05:     ESPI_CLK_EC_R */
+	/*  GPP_A05 : GPP_A05 ==> ESPI_CLK_HDR configured on reset, do not touch */
+
+	/* GPP_A06:     ESPI_RST_EC_R_N */
+	/*  GPP_A06 : GPP_A06 ==> ESPI_RST_HDR configured on reset, do not touch */
+
+	/* GPP_A09:     M.2_WWAN_FCP_OFF_N */
+	PAD_CFG_GPO(GPP_A09, 1, PLTRST),
+	/* GPP_A10:     M.2_WWAN_DISABLE_N */
+	PAD_CFG_GPO(GPP_A10, 1, PLTRST),
+	/* GPP_A11:     WLAN_RST_N */
+	PAD_CFG_GPO(GPP_A11, 1, PLTRST),
+	/* GPP_A12:     WIFI_WAKE_N */
+	PAD_CFG_GPI_SCI_LOW(GPP_A12, NONE, DEEP, LEVEL),
+	/* GPP_A15:     GPP_A15_DNX_FORCE_RELOAD */
+	PAD_CFG_NF(GPP_A15, NONE, DEEP, NF1),
+	/* GPP_A16:     BT_RF_KILL_N */
+	PAD_CFG_GPO(GPP_A16, 1, DEEP),
+	/* GPP_A17:     WIFI_RF_KILL_N */
+	PAD_CFG_GPO(GPP_A17, 1, DEEP),
+
+	/* GPP_B00:     USBC_SML_CLK_PD */
+	PAD_CFG_NF(GPP_B00, NONE, DEEP, NF1),
+	/* GPP_B01:     USBC_SML_DATA_PD */
+	PAD_CFG_NF(GPP_B01, NONE, DEEP, NF1),
+	/* GPP_B02:     ISH_I2C0_SDA_SNSR_HDR */
+	/* NOTE: IOSSTAGE: 'Ignore' for S0ix */
+	PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_B02, NONE, DEEP, NF3),
+	/* GPP_B03:     ISH_I2C0_SCL_SNSR_HDR */
+	/* NOTE: IOSSTAGE: 'Ignore' for S0ix */
+	PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_B03, NONE, DEEP, NF3),
+	/* GPP_B04:     ISH_GP_0_SNSR_HDR */
+	PAD_CFG_NF(GPP_B04, NONE, DEEP, NF4),
+	/* GPP_B05:     ISH_GP_1_SNSR_HDR */
+	PAD_CFG_NF(GPP_B05, NONE, DEEP, NF4),
+	/* GPP_B06:     ISH_GP_2_SNSR_HDR */
+	PAD_CFG_NF(GPP_B06, NONE, DEEP, NF4),
+	/* GPP_B07:     ISH_GP_3_SNSR_HDR */
+	PAD_CFG_NF(GPP_B07, NONE, DEEP, NF4),
+	/* GPP_B08:     ISH_GP_4_SNSR_HDR */
+	PAD_CFG_NF(GPP_B08, NONE, DEEP, NF4),
+	/* GPP_B09:     M2_GEN4_SSD_RESET_N */
+	PAD_CFG_GPO(GPP_B09, 1, PLTRST),
+	/* GPP_B10:     GEN4_SSD_PWREN */
+	PAD_CFG_GPO(GPP_B10, 1, PLTRST),
+	/* GPP_B11:     MOD_TCSS1_DISP_HPD3 */
+	PAD_CFG_NF(GPP_B11, NONE, DEEP, NF2),
+	/* GPP_B12:     PM_SLP_S0_N */
+	PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1),
+	/* GPP_B13:     PLT_RST_N */
+	PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1),
+	/* GPP_B14:     MOD_TCSS2_DISP_HPD4 */
+	PAD_CFG_NF(GPP_B14, NONE, DEEP, NF2),
+	/* GPP_B15:     MOD_TCSS_USB_TYP_A_OC3_N */
+	PAD_CFG_NF(GPP_B15, NONE, DEEP, NF1),
+	/* GPP_B16:     GEN5_SSD_PWREN */
+	PAD_CFG_GPO(GPP_B16, 1, PLTRST),
+	/* GPP_B17:     Not used */
+	PAD_NC(GPP_B17, NONE),
+	/* GPP_B18:     ISH_I2C2_SDA_SNSR_HDR */
+	/* NOTE: IOSSTAGE: 'Ignore' for S0ix */
+	PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_B18, NONE, DEEP, NF1),
+	/* GPP_B19:     ISH_I2C2_SCL_SNSR_HDR */
+	/* NOTE: IOSSTAGE: 'Ignore' for S0ix */
+	PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_B19, NONE, DEEP, NF1),
+	/* GPP_B20:     M.2_WWAN_RST_N */
+	PAD_CFG_GPO(GPP_B20, 1, PLTRST),
+	/* GPP_B21:     TCP_RETIMER_FORCE_PWR */
+	PAD_CFG_GPO(GPP_B21, 0, DEEP),
+	/* GPP_B22:     ISH_GP_5_SNSR_HDR */
+	PAD_CFG_NF(GPP_B22, NONE, DEEP, NF4),
+	/* GPP_B23:     ISH_GP_6_SNSR_HDR */
+	PAD_CFG_NF(GPP_B23, NONE, DEEP, NF4),
+	/* GPP_B24:     ESPI_ALERT0_EC_R_N */
+	PAD_NC(GPP_B24, NONE),
+
+	/* GPP_C00:     GPP_C0_SMBCLK */
+	PAD_CFG_NF(GPP_C00, NONE, DEEP, NF1),
+	/* GPP_C01:     GPP_C1_SMBDATA */
+	PAD_CFG_NF(GPP_C01, NONE, DEEP, NF1),
+	/* GPP_C02:     Not used */
+	PAD_NC(GPP_C02, NONE),
+	/* GPP_C03:     TCP_LAN_SML0_SCL_R */
+	PAD_CFG_NF(GPP_C03, NONE, DEEP, NF1),
+	/* GPP_C04:     TCP_LAN_SML0_SDA_R */
+	PAD_CFG_NF(GPP_C04, NONE, DEEP, NF1),
+	/* GPP_C06:     SML1_CLK */
+	PAD_CFG_NF(GPP_C06, NONE, DEEP, NF1),
+	/* GPP_C07:     SML1_DATA */
+	PAD_CFG_NF(GPP_C07, NONE, DEEP, NF1),
+	/* GPP_C09:     CLKREQ0_X8_GEN5_DT_CEM_SLOT_N */
+	PAD_CFG_NF(GPP_C09, NONE, DEEP, NF1),
+	/* GPP_C10:     CLKREQ1_X4_GEN5_M2_SSD_N */
+	PAD_CFG_NF(GPP_C10, NONE, DEEP, NF1),
+	/* GPP_C11:     CLKREQ2_X1_GEN4_DT_CEM_SLOT_N */
+	PAD_CFG_NF(GPP_C11, NONE, DEEP, NF1),
+	/* GPP_C12:     CLKREQ3_X1_GEN1_GBE_LAN_N */
+	PAD_CFG_NF(GPP_C12, NONE, DEEP, NF1),
+	/* GPP_C13:     CLKREQ4_X1_GEN4_M2_WLAN_N */
+	PAD_CFG_NF(GPP_C13, NONE, DEEP, NF1),
+	/* GPP_C14:     CLKREQ5_X1_GEN4_M2_WWAN_N */
+	PAD_CFG_NF(GPP_C14, NONE, DEEP, NF1),
+	/* GPP_C16:     TBT_LSX0_TXD  */
+	PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1),
+	/* GPP_C17:     TBT_LSX0_RXD  */
+	PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1),
+	/* GPP_C18:     TBT_LSX1_TXD  */
+	PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1),
+	/* GPP_C19:     TBT_LSX1_RXD */
+	PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1),
+	/* GPP_C20:     MOD_TCSS1_LS_TX_DDC_SCL */
+	PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1),
+	/* GPP_C21:     MOD_TCSS1_LS_RX_DDC_SDA */
+	PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1),
+	/* GPP_C22:     MOD_TCSS2_LS_TX_DDC_SCL */
+	PAD_CFG_NF(GPP_C22, NONE, DEEP, NF2),
+	/* GPP_C23:     MOD_TCSS2_LS_RX_DDC_SDA */
+	PAD_CFG_NF(GPP_C23, NONE, DEEP, NF2),
+
+	/* GPP_D00:     IMGCLKOUT_1 */
+	PAD_CFG_NF(GPP_D00, NONE, DEEP, NF1),
+	/* GPP_D02:     Not used */
+	PAD_NC(GPP_D02, NONE),
+	/* GPP_D03:     M.2_WWAN_PERST_GPIO_N */
+	PAD_CFG_GPO(GPP_D03, 1, PLTRST),
+	/* GPP_D04:     IMGCLKOUT_0 */
+	PAD_CFG_NF(GPP_D04, NONE, DEEP, NF1),
+	/* GPP_D05:     disable ISH_UART0_RXD */
+	PAD_NC(GPP_D05, NONE),
+	/* GPP_D07:     NC */
+	PAD_NC(GPP_D07, NONE),
+	/* GPP_D08:     NC */
+	PAD_NC(GPP_D08, NONE),
+	/* GPP_D09:     PEG_SLOT_RST_N */
+	PAD_CFG_GPO(GPP_D09, 1, PLTRST),
+	/* GPP_D10:     HDA_BCLK */
+	PAD_CFG_NF(GPP_D10, NONE, DEEP, NF1),
+	/* GPP_D11:     HDA_SYNC */
+	PAD_CFG_NF(GPP_D11, NONE, DEEP, NF1),
+	/* GPP_D12:     HDA_SDO */
+	PAD_CFG_NF(GPP_D12, NONE, DEEP, NF1),
+	/* GPP_D13:     HDA_SDI0 */
+	PAD_CFG_NF(GPP_D13, NONE, DEEP, NF1),
+	/* GPP_D14:     COINLESS_MODE_SELECT */
+	PAD_CFG_GPI_TRIG_OWN(GPP_D14, NONE, PLTRST, LEVEL, ACPI),
+	/* GPP_D15:     SPI_TPM_INT_N */
+	PAD_CFG_GPI_APIC_LOCK(GPP_D15, NONE, LEVEL, INVERT, LOCK_CONFIG),
+	/* GPP_D16:     HDA_RST_N_HDR */
+	PAD_CFG_NF(GPP_D16, NONE, DEEP, NF1),
+	/* GPP_D17:     HDA_SDI1_HDR */
+	PAD_CFG_NF(GPP_D17, NONE, DEEP, NF1),
+	/* GPP_D18:     CLKREQ6_X4_GEN4_M2_SSD_N */
+	PAD_CFG_NF(GPP_D18, NONE, DEEP, NF1),
+	/* GPP_D20:     CSE_EARLY_SW */
+	PAD_CFG_GPI_SCI_HIGH(GPP_D20, NONE, DEEP, LEVEL),
+	/* GPP_D21:     NC */
+	PAD_NC(GPP_D21, NONE),
+	/* GPP_D22:     BPKI3C_SDA */
+	PAD_CFG_NF(GPP_D22, NONE, DEEP, NF1),
+	/* GPP_D23:     BPKI3C_SCL */
+	PAD_CFG_NF(GPP_D23, NONE, DEEP, NF1),
+	/* GPP_D24:     PEG_SLOT_WAKE_N */
+	PAD_CFG_GPI_SCI_LOW(GPP_D24, NONE, DEEP, LEVEL),
+	/* GPP_D25:     X4_SLOT_WAKE_N */
+	PAD_CFG_GPI_SCI_LOW(GPP_D25, NONE, DEEP, LEVEL),
+
+	/* GPP_E01:     CRD2_RST_N */
+	PAD_CFG_GPO(GPP_E01, 1, PLTRST),
+	/* GPP_E02:     WWAN_WAKE_GPIO_N  */
+	PAD_CFG_GPI_SCI_LOW(GPP_E02, NONE, DEEP, LEVEL),
+	/* GPP_E03:     M2_GEN5_SSD_RESET_N */
+	PAD_CFG_GPO(GPP_E03, 1, PLTRST),
+	/* GPP_E06:     SECURE_CAM_SW */
+	PAD_CFG_GPI_TRIG_OWN(GPP_E06, NONE, PLTRST, LEVEL, ACPI),
+#if CONFIG(BOARD_GOOGLE_OCELOT)
+	/* GPP_E07:     Not used */
+	PAD_NC(GPP_E07, NONE),
+#else
+	/* GPP_E07 : [] ==> EC_SOC_INT_ODL */
+	PAD_CFG_GPI_APIC_LOCK(GPP_E07, NONE, LEVEL, INVERT, LOCK_CONFIG),
+#endif
+	/* GPP_E08:     Not used */
+	PAD_NC(GPP_E08, NONE),
+	/* GPP_E09:     USB_RD_FP_CONN_12_OC0_N */
+	PAD_CFG_NF(GPP_E09, NONE, DEEP, NF1),
+	/* GPP_E10:     CRD1_RST_N */
+	PAD_CFG_GPO(GPP_E10, 1, PLTRST),
+	/* GPP_E11:     THC0_SPI1_CLK_TCH_PNL1 */
+	PAD_CFG_NF(GPP_E11, NONE, DEEP, NF3),
+	/* GPP_E12:     THC0_SPI1_IO_0_I2C4_SCL_TCH_PNL1 */
+	PAD_CFG_NF(GPP_E12, NONE, DEEP, NF3),
+	/* GPP_E13:     THC0_SPI1_IO_1_I2C4_SDA_TCH_PNL1 */
+	PAD_CFG_NF(GPP_E13, NONE, DEEP, NF3),
+	/* GPP_E14:     THC0_SPI1_IO_2_TCH_PNL1 */
+	PAD_CFG_NF(GPP_E14, NONE, DEEP, NF3),
+	/* GPP_E15:     THC0_SPI1_IO_3_TCH_PNL1 */
+	PAD_CFG_NF(GPP_E15, NONE, DEEP, NF3),
+	/* GPP_E16:     THC0_SPI1_RST_N_TCH_PNL1 */
+	/* THC NOTE: use GPO instead of GPO for THC0 Rst */
+	PAD_CFG_GPO(GPP_E16, 1, DEEP),
+	/* GPP_E17:     THC0_SPI1_CS0_N_TCH_PNL1 */
+	PAD_CFG_NF(GPP_E17, NONE, DEEP, NF3),
+	/* GPP_E18:     THC0_SPI1_INT_N_TCH_PNL1 */
+	PAD_CFG_NF(GPP_E18, NONE, DEEP, NF3),
+	/* GPP_E21:     I2C_PMC_PD_INT_N */
+	PAD_CFG_NF(GPP_E21, NONE, DEEP, NF1),
+	/* GPP_E22:     THC0_SPI1_DSYNC */
+	PAD_CFG_NF(GPP_E22, NONE, DEEP, NF3),
+
+	/* GPP_F00:     M.2_CNV_BRI_DT_BT_UART2_RTS_N */
+	/* NOTE: IOSSTAGE: 'Ignore' for S0ix */
+	PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_F00, NONE, DEEP, NF1),
+	/* GPP_F01:     M.2_CNV_BRI_RSP_BT_UART2_RXD */
+	/* NOTE: IOSSTAGE: 'Ignore' for S0ix */
+	PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_F01, NONE, DEEP, NF1),
+	/* GPP_F02:     M.2_CNV_RGI_DT_BT_UART2_TXD */
+	/* NOTE: IOSSTAGE: 'Ignore' for S0ix */
+	PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_F02, NONE, DEEP, NF1),
+	/* GPP_F03:     M.2_CNV_RGI_RSP_BT_UART2_CTS_N */
+	/* NOTE: IOSSTAGE: 'Ignore' for S0ix */
+	PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_F03, NONE, DEEP, NF1),
+	/* GPP_F04:     CNV_RF_RESET_R_N */
+	/* NOTE: IOSSTAGE: 'Ignore' for S0ix */
+	PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_F04, NONE, DEEP, NF1),
+	/* GPP_F05:     CRF_CLKREQ_R */
+	/* NOTE: IOSSTAGE: 'Ignore' for S0ix */
+	PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_F05, NONE, DEEP, NF3),
+	/* GPP_F06:     WLAN_WWAN_COEX3 */
+	PAD_CFG_NF(GPP_F06, NONE, DEEP, NF1),
+	/* GPP_F07:     IMGCLKOUT_2 */
+	PAD_CFG_NF(GPP_F07, NONE, DEEP, NF2),
+	/* GPP_F08:     TCH_PNL1_PWR_EN */
+	PAD_CFG_GPO(GPP_F08, 1, PLTRST),
+	/* GPP_F09:     NC */
+	PAD_NC(GPP_F09, NONE),
+	/* GPP_F10:     PEG_SLOT_PWR_EN_N */
+	PAD_CFG_GPO(GPP_F10, 0, PLTRST),
+	/* GPP_F11:     MOD_TCSS2_TYP_A_VBUS_EN */
+	PAD_CFG_GPO(GPP_F11, 1, DEEP),
+	/* GPP_F12:     THC_I2C1_SCL_TCH_PAD */
+	PAD_CFG_NF(GPP_F12, NONE, DEEP, NF8),
+	/* GPP_F13:     THC_I2C1_SDA_TCH_PAD */
+	PAD_CFG_NF(GPP_F13, NONE, DEEP, NF8),
+	/* GPP_F17:     Not used */
+	PAD_CFG_GPI_INT(GPP_F17, NONE, PLTRST, EDGE_BOTH),
+	/* GPP_F19:     GPP_PRIVACY_LED_CAM2 */
+	PAD_CFG_GPO(GPP_F19, 0, PLTRST),
+	/* GPP_F20:     GPP_PRIVACY_LED_CAM1_CVS_HST_WAKE */
+	PAD_CFG_GPO(GPP_F20, 0, PLTRST),
+	/* GPP_F22:     THC1_SPI2_DSYNC */
+	PAD_CFG_NF(GPP_F22, NONE, DEEP, NF3),
+
+	/* GPP_H00:     Not used */
+	PAD_NC(GPP_H00, NONE),
+	/* GPP_H01:     CRD_CAM_STROBE */
+	PAD_CFG_GPO(GPP_H01, 0, PLTRST),
+	/* GPP_H02:     DEBUG_TRACE_PNP */
+	PAD_CFG_GPO(GPP_H02, 1, PLTRST),
+	/* GPP_H03:     MIC MUTE */
+	PAD_CFG_NF(GPP_H03, NONE, DEEP, NF1),
+	/* GPP_H04:     I2C2_SDA_CAM_FLSH */
+	PAD_CFG_NF(GPP_H04, NONE, DEEP, NF1),
+	/* GPP_H05:     I2C2_SCL_CAM_FLSH */
+	PAD_CFG_NF(GPP_H05, NONE, DEEP, NF1),
+	/* GPP_H06:     I2C3_SDA_PSS */
+	PAD_CFG_NF(GPP_H06, NONE, DEEP, NF1),
+	/* GPP_H07:     I2C3_SCL_PSS */
+	PAD_CFG_NF(GPP_H07, NONE, DEEP, NF1),
+	/* GPP_H08:     UART0_BUF_RXD */
+	PAD_CFG_NF(GPP_H08, NONE, DEEP, NF1),
+	/* GPP_H09:     UART0_BUF_TXD */
+	PAD_CFG_NF(GPP_H09, NONE, DEEP, NF1),
+	/* GPP_H10:     UART0_BUF_RTS */
+	PAD_CFG_NF(GPP_H10, NONE, DEEP, NF1),
+	/* GPP_H11:     UART0_BUF_CTS */
+	PAD_CFG_NF(GPP_H11, NONE, DEEP, NF1),
+	/* GPP_H13:     CPU_C10_GATE_N_R */
+	PAD_CFG_NF(GPP_H13, NONE, DEEP, NF1),
+	/* GPP_H14:     NC */
+	PAD_NC(GPP_H14, NONE),
+	/* GPP_H15:     NC */
+	PAD_NC(GPP_H15, NONE),
+	/* GPP_H16:     WWAN_PWREN */
+	PAD_CFG_GPO(GPP_H16, 1, PLTRST),
+	/* GPP_H17:     MIC MUTE LED */
+	PAD_CFG_NF(GPP_H17, NONE, DEEP, NF1),
+	/* GPP_H19:     I3C0_SDA_HDR */
+	PAD_CFG_NF(GPP_H19, NONE, DEEP, NF2),
+	/* GPP_H20:     I3C0_SCL_HDR */
+	PAD_CFG_NF(GPP_H20, NONE, DEEP, NF2),
+	/* GPP_H21:     I2C1_SDA_I3C1_SDA_CAM_FLSH_CVS */
+	PAD_CFG_NF(GPP_H21, NONE, DEEP, NF1),
+	/* GPP_H22:     I2C1_SCL_I3C1_SCL_CAM_FLSH_CVS */
+	PAD_CFG_NF(GPP_H22, NONE, DEEP, NF1),
+
+	/* GPP_S00:     SNDW3_CLK_CODEC */
+	PAD_CFG_NF(GPP_S00, NONE, DEEP, NF1),
+	/* GPP_S01:     SNDW3_DATA0_CODEC */
+	PAD_CFG_NF(GPP_S01, NONE, DEEP, NF1),
+	/* GPP_S02:     SNDW3_DATA1_CODEC */
+	PAD_CFG_NF(GPP_S02, NONE, DEEP, NF1),
+	/* GPP_S03:     SNDW3_DATA2_CODEC */
+	PAD_CFG_NF(GPP_S03, NONE, DEEP, NF1),
+	/* GPP_S04:     SNDW2_CLK */
+	PAD_CFG_NF(GPP_S04, NONE, DEEP, NF2),
+	/* GPP_S05:     SNDW2_DATA0 */
+	PAD_CFG_NF(GPP_S05, NONE, DEEP, NF2),
+	/* GPP_S06:     SNDW1_CLK */
+	PAD_CFG_NF(GPP_S06, NONE, DEEP, NF3),
+	/* GPP_S07:     SNDW1_DATA0 */
+	PAD_CFG_NF(GPP_S07, NONE, DEEP, NF3),
+
+	/* GPP_V00:     PM_BATLOW_N */
+	PAD_CFG_NF(GPP_V00, NONE, DEEP, NF1),
+	/* GPP_V01:     BC_ACOK_MCP */
+	PAD_CFG_NF(GPP_V01, NONE, DEEP, NF1),
+	/* GPP_V02:     LANWAKE_N_R */
+	PAD_CFG_NF(GPP_V02, NONE, DEEP, NF1),
+	/* GPP_V03:     PWRBTN_MCP_N */
+	PAD_CFG_NF(GPP_V03, NONE, DEEP, NF1),
+	/* GPP_V04:     PM_SLP_S3_N */
+	PAD_CFG_NF(GPP_V04, NONE, DEEP, NF1),
+	/* GPP_V05:     PM_SLP_S4_N */
+	PAD_CFG_NF(GPP_V05, NONE, DEEP, NF1),
+	/* GPP_V06:     PM_SLP_A_N */
+	PAD_CFG_NF(GPP_V06, NONE, DEEP, NF1),
+	/* GPP_V07:     Not used */
+	PAD_NC(GPP_V07, NONE),
+	/* GPP_V08:     SLP_WLAN_N */
+	PAD_CFG_NF(GPP_V08, NONE, DEEP, NF1),
+	/* GPP_V09:     PM_SLP_S5_N */
+	PAD_CFG_NF(GPP_V09, NONE, DEEP, NF1),
+	/* GPP_V10:     LANPHYPC_R_N */
+	PAD_CFG_NF(GPP_V10, NONE, DEEP, NF1),
+	/* GPP_V11:     PM_SLP_LAN_N */
+	PAD_CFG_NF(GPP_V11, NONE, DEEP, NF1),
+	/* GPP_V12:     WAKE_N */
+	PAD_CFG_NF(GPP_V12, NONE, DEEP, NF1),
+	/* GPP_V13:     GPP_V13_CATERR_N */
+	PAD_CFG_NF(GPP_V13, NONE, DEEP, NF1),
+	/* GPP_V14:     GPP_V14_FORCEPR_N */
+	PAD_CFG_NF(GPP_V14, NONE, DEEP, NF1),
+	/* GPP_V15:     GPP_V15_THERMTRIP_N */
+	PAD_CFG_NF(GPP_V15, NONE, DEEP, NF1),
+	/* GPP_V16:     GPP_V16_VCCST_EN */
+	PAD_CFG_NF(GPP_V16, NONE, DEEP, NF1),
+	/* GPP_V17:     TCP_RT_S0IX_ENTRY_EXIT_N */
+	PAD_CFG_GPO(GPP_V17, 1, DEEP),
+};
+
+/* Early pad configuration in bootblock */
+static const struct pad_config early_gpio_table[] = {
+	/* GPP_H08:     UART0_BUF_RXD */
+	PAD_CFG_NF(GPP_H08, NONE, DEEP, NF1),
+	/* GPP_H09:     UART0_BUF_TXD */
+	PAD_CFG_NF(GPP_H09, NONE, DEEP, NF1),
+
+	/* GPP_H06: I2C3_SDA_PSS */
+	PAD_CFG_NF(GPP_H06, NONE, DEEP, NF1),
+	/* GPP_H07: I2C3_SCL_PSS */
+	PAD_CFG_NF(GPP_H07, NONE, DEEP, NF1),
+	/* GPP_D15: SPI_TPM_INT_N */
+	PAD_CFG_GPI_APIC(GPP_D15, NONE, PLTRST, LEVEL, INVERT),
+};
+
+/* Pad configuration in romstage */
+static const struct pad_config romstage_gpio_table[] = {
+	/* GPP_C00:     GPP_C0_SMBCLK */
+	PAD_CFG_NF(GPP_C00, NONE, DEEP, NF1),
+	/* GPP_C01:     GPP_C1_SMBDATA */
+	PAD_CFG_NF(GPP_C01, NONE, DEEP, NF1),
+};
+
+const struct pad_config *variant_gpio_table(size_t *num)
+{
+	*num = ARRAY_SIZE(gpio_table);
+	return gpio_table;
+}
+
+const struct pad_config *variant_early_gpio_table(size_t *num)
+{
+	*num = ARRAY_SIZE(early_gpio_table);
+	return early_gpio_table;
+}
+
+/* Create the stub for romstage gpio, typically use for power sequence */
+const struct pad_config *variant_romstage_gpio_table(size_t *num)
+{
+	*num = ARRAY_SIZE(romstage_gpio_table);
+	return romstage_gpio_table;
+}
+
+static const struct cros_gpio cros_gpios[] = {
+	CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE0_NAME),
+	CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE1_NAME),
+	CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE2_NAME),
+	CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE3_NAME),
+};
+
+DECLARE_CROS_GPIOS(cros_gpios);
diff --git a/src/mainboard/google/ocelot/variants/ocelot/hda_verb.c b/src/mainboard/google/ocelot/variants/ocelot/hda_verb.c
new file mode 100644
index 0000000000..2f703b78ee
--- /dev/null
+++ b/src/mainboard/google/ocelot/variants/ocelot/hda_verb.c
@@ -0,0 +1,126 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <device/azalia_device.h>
+
+const u32 cim_verb_data[] = {
+	/* coreboot specific header */
+	0x10ec0256,	/* Codec Vendor / Device ID: Realtek ALC256 */
+	0x10ec12ac,	/* Subsystem ID */
+	0x00000013,	/* Number of jacks (NID entries) */
+
+	AZALIA_RESET(0x1),
+	/* NID 0x01, HDA Codec Subsystem ID Verb Table */
+	AZALIA_SUBVENDOR(0, 0x10ec12ac),
+
+	/* Pin Widget Verb Table */
+	/*
+	 * DMIC
+	 * Requirement is to use PCH DMIC. Hence,
+	 * commented out codec's Internal DMIC.
+	 * AZALIA_PIN_CFG(0, 0x12, 0x90A60130),
+	 * AZALIA_PIN_CFG(0, 0x13, 0x40000000),
+	 */
+	/* Pin widget 0x14 - Front (Port-D) */
+	AZALIA_PIN_CFG(0, 0x14, 0x90170110),
+	/* Pin widget 0x18 - NPC */
+	AZALIA_PIN_CFG(0, 0x18, 0x411111F0),
+	/* Pin widget 0x19 - MIC2 (Port-F) */
+	AZALIA_PIN_CFG(0, 0x19, 0x04A11040),
+	/* Pin widget 0x1A - LINE1 (Port-C) */
+	AZALIA_PIN_CFG(0, 0x1a, 0x411111F0),
+	/* Pin widget 0x1B - NPC */
+	AZALIA_PIN_CFG(0, 0x1b, 0x411111F0),
+	/* Pin widget 0x1D - BEEP-IN */
+	AZALIA_PIN_CFG(0, 0x1d, 0x40610041),
+	/* Pin widget 0x1E - NPC */
+	AZALIA_PIN_CFG(0, 0x1e, 0x411111F0),
+	/* Pin widget 0x21 - HP1-OUT (Port-I) */
+	AZALIA_PIN_CFG(0, 0x21, 0x04211020),
+	/*
+	 * Widget node 0x20 - 1
+	 * Codec hidden reset and speaker power 2W/4ohm
+	 */
+	0x0205001A,
+	0x0204C003,
+	0x02050038,
+	0x02047901,
+	/*
+	 * Widget node 0x20 - 2
+	 * Class D power on Reset
+	 */
+	0x0205003C,
+	0x02040354,
+	0x0205003C,
+	0x02040314,
+	/*
+	 * Widget node 0x20 - 3
+	 * Disable AGC and set AGC limit to -1.5dB
+	 */
+	0x02050016,
+	0x02040C50,
+	0x02050012,
+	0x0204EBC1,
+	/*
+	 * Widget node 0x20 - 4
+	 * Set AGC Post gain +1.5dB then Enable AGC
+	 */
+	0x02050013,
+	0x02044023,
+	0x02050016,
+	0x02040E50,
+	/*
+	 * Widget node 0x20 - 5
+	 * Silence detector enabling + Set EAPD to verb control
+	 */
+	0x02050037,
+	0x0204FE15,
+	0x02050010,
+	0x02040020,
+	/*
+	 * Widget node 0x20 - 6
+	 * Silence data mode Threshold (-90dB)
+	 */
+	0x02050030,
+	0x0204A000,
+	0x0205001B,
+	0x02040A4B,
+	/*
+	 * Widget node 0x20 - 7
+	 * Default setting-1
+	 */
+	0x05750003,
+	0x05740DA3,
+	0x02050046,
+	0x02040004,
+	/*
+	 * Widget node 0x20 - 8
+	 * support 1 pin detect two port
+	 */
+	0x02050009,
+	0x0204E003,
+	0x0205000A,
+	0x02047770,
+	/*
+	 * Widget node 0x20 - 9
+	 * To set LDO1/LDO2 as default
+	 */
+	0x02050008,
+	0x02046A0C,
+	0x02050008,
+	0x02046A0C,
+};
+
+const u32 pc_beep_verbs[] = {
+	/* Dos beep path - 1 */
+	0x01470C00,
+	0x02050036,
+	0x02047151,
+	0x01470740,
+	/* Dos beep path - 2 */
+	0x0143b000,
+	0x01470C02,
+	0x01470C02,
+	0x01470C02,
+};
+
+AZALIA_ARRAY_SIZES;
diff --git a/src/mainboard/google/ocelot/variants/ocelot/include/variant/ec.h b/src/mainboard/google/ocelot/variants/ocelot/include/variant/ec.h
new file mode 100644
index 0000000000..4fc0622f15
--- /dev/null
+++ b/src/mainboard/google/ocelot/variants/ocelot/include/variant/ec.h
@@ -0,0 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#ifndef MAINBOARD_EC_H
+#define MAINBOARD_EC_H
+
+#include <baseboard/ec.h>
+
+#endif /* MAINBOARD_GPIO_H */
diff --git a/src/mainboard/google/ocelot/variants/ocelot/include/variant/gpio.h b/src/mainboard/google/ocelot/variants/ocelot/include/variant/gpio.h
new file mode 100644
index 0000000000..cced66807a
--- /dev/null
+++ b/src/mainboard/google/ocelot/variants/ocelot/include/variant/gpio.h
@@ -0,0 +1,11 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#ifndef __MAINBOARD_GPIO_H__
+#define __MAINBOARD_GPIO_H__
+
+#include <baseboard/gpio.h>
+
+/* EC wake is LAN_WAKE# which is a special DeepSX wake pin */
+#define GPE_EC_WAKE	GPE0_LAN_WAK
+
+#endif /* __MAINBOARD_GPIO_H__ */
diff --git a/src/mainboard/google/ocelot/variants/ocelot/memory.c b/src/mainboard/google/ocelot/variants/ocelot/memory.c
new file mode 100644
index 0000000000..e0908adabd
--- /dev/null
+++ b/src/mainboard/google/ocelot/variants/ocelot/memory.c
@@ -0,0 +1,76 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <baseboard/variants.h>
+#include <soc/romstage.h>
+#include <soc/meminit.h>
+
+static const struct mb_cfg lp5_mem_config = {
+	.type = MEM_TYPE_LP5X,
+
+	.lpx_dq_map = {
+		.ddr0 = {
+			.dq0 = {  13,  14,  12,  15, 11,  10,  8,  9, },
+			.dq1 = {  7,  5,  4,  6,  0,  3,  1,  2 },
+		},
+		.ddr1 = {
+			.dq0 = {  1,  3,  0,  2,  7,  4,  6,  5, },
+			.dq1 = {  12,  13,  14,  15,  11,  10,  9,  8 },
+		},
+		.ddr2 = {
+			.dq0 = {  0,  2,  1,  3,  6,  4,  7,  5 },
+			.dq1 = {  14,  13,  15,  12,  8,  11,  10,  9, },
+		},
+		.ddr3 = {
+			.dq0 = {  6,  5,  7,  4,  2,  3,  1,  0, },
+			.dq1 = {  10,  8,  11,  9,  12,  15,  13,  14 },
+		},
+		.ddr4 = {
+			.dq0 = {  2,  1,  3,  0,  4,  7,  5,  6 },
+			.dq1 = {  15,  14,  12,  13,  9,  11,  10,  8, },
+		},
+		.ddr5 = {
+			.dq0 = {  6,  5,  7,  4,  3,  1,  0,  2, },
+			.dq1 = {  10,  9,  11,  8,  13,  14,  12,  15 },
+		},
+		.ddr6 = {
+			.dq0 = {  9,  10,  11,  8,  14,  12,  13, 15, },
+			.dq1 = {  0,  1,  2,  3,  5,  7,  4,  6 },
+		},
+		.ddr7 = {
+			.dq0 = {  0,  1,  2,  3,  7,  5,  6,  4, },
+			.dq1 = {  14,  13,  15,  12,  10,  8,  11,  9 },
+		},
+	},
+
+	.lpx_dqs_map = {
+		.ddr0 = { .dqs0 = 1, .dqs1 = 0 },
+		.ddr1 = { .dqs0 = 0, .dqs1 = 1 },
+		.ddr2 = { .dqs0 = 0, .dqs1 = 1 },
+		.ddr3 = { .dqs0 = 0, .dqs1 = 1 },
+		.ddr4 = { .dqs0 = 0, .dqs1 = 1 },
+		.ddr5 = { .dqs0 = 0, .dqs1 = 1 },
+		.ddr6 = { .dqs0 = 1, .dqs1 = 0 },
+		.ddr7 = { .dqs0 = 0, .dqs1 = 1 }
+	},
+
+	.ect = true, /* Early Command Training */
+
+	.lp_ddr_dq_dqs_re_training = 1,
+
+	.user_bd = BOARD_TYPE_ULT_ULX,
+
+	.lp5x_config = {
+		.ccc_config = 0xFF,
+	},
+};
+
+const struct mb_cfg *variant_memory_params(void)
+{
+	return &lp5_mem_config;
+}
+
+void variant_get_spd_info(struct mem_spd *spd_info)
+{
+	spd_info->topo = MEM_TOPO_MEMORY_DOWN;
+	spd_info->cbfs_index = 0;
+}
diff --git a/src/mainboard/google/ocelot/variants/ocelot/memory/Makefile.mk b/src/mainboard/google/ocelot/variants/ocelot/memory/Makefile.mk
new file mode 100644
index 0000000000..23bc544fc6
--- /dev/null
+++ b/src/mainboard/google/ocelot/variants/ocelot/memory/Makefile.mk
@@ -0,0 +1,7 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+# This is an auto-generated file. Do not edit!!
+# Generated by:
+# ./util/spd_tools/bin/part_id_gen PTL lp5 src/mainboard/google/ocelot/variants/ocelot/memory src/mainboard/google/ocelot/variants/ocelot/memory/mem_parts_used.txt
+
+SPD_SOURCES =
+SPD_SOURCES += spd/lp5/set-0/spd-7.hex      # ID = 0(0b0000)  Parts = H58G56BK7BX068
diff --git a/src/mainboard/google/ocelot/variants/ocelot/memory/dram_id.generated.txt b/src/mainboard/google/ocelot/variants/ocelot/memory/dram_id.generated.txt
new file mode 100644
index 0000000000..8bdcd1a2f8
--- /dev/null
+++ b/src/mainboard/google/ocelot/variants/ocelot/memory/dram_id.generated.txt
@@ -0,0 +1,7 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+# This is an auto-generated file. Do not edit!!
+# Generated by:
+# ./util/spd_tools/bin/part_id_gen PTL lp5 src/mainboard/google/ocelot/variants/ocelot/memory src/mainboard/google/ocelot/variants/ocelot/memory/mem_parts_used.txt
+
+DRAM Part Name                 ID to assign
+H58G56BK7BX068                 0 (0000)
diff --git a/src/mainboard/google/ocelot/variants/ocelot/memory/mem_parts_used.txt b/src/mainboard/google/ocelot/variants/ocelot/memory/mem_parts_used.txt
new file mode 100644
index 0000000000..17ee7efc60
--- /dev/null
+++ b/src/mainboard/google/ocelot/variants/ocelot/memory/mem_parts_used.txt
@@ -0,0 +1,12 @@
+# This is a CSV file containing a list of memory parts used by this variant.
+# One part per line with an optional fixed ID in column 2.
+# Only include a fixed ID if it is required for legacy reasons!
+# Generated IDs are dependent on the order of parts in this file,
+# so new parts must always be added at the end of the file!
+#
+# Generate an updated Makefile.mk and dram_id.generated.txt by running the
+# part_id_gen tool from util/spd_tools.
+# See util/spd_tools/README.md for more details and instructions.
+
+# Part Name
+H58G56BK7BX068
diff --git a/src/mainboard/google/ocelot/variants/ocelot/overridetree.cb b/src/mainboard/google/ocelot/variants/ocelot/overridetree.cb
new file mode 100644
index 0000000000..cb4c21a1f7
--- /dev/null
+++ b/src/mainboard/google/ocelot/variants/ocelot/overridetree.cb
@@ -0,0 +1,890 @@
+fw_config
+	field AUDIO 0 3
+		option AUDIO_NONE			0
+		option AUDIO_MAX98373_ALC5682_SNDW	1
+		option AUDIO_ALC722_SNDW		2
+		option AUDIO_ALC256_HDA			3
+		option AUDIO_MAX98360_ALC5682I_I2S	4
+		option AUDIO_ALC721_SNDW		5
+	end
+	field WIFI 4 5
+		option WIFI_CNVI_6		0
+		option WIFI_CNVI_7		1
+		option WIFI_PCIE_6		2
+		option WIFI_PCIE_7		3
+	end
+	field CELLULAR 6 7
+		option CELLULAR_ABSENT		0
+		option CELLULAR_USB		1
+		option CELLULAR_PCIE		2
+	end
+	field TOUCHSCREEN 8 10
+		option TOUCHSCREEN_NONE		0
+		option TOUCHSCREEN_LPSS_I2C	1
+		option TOUCHSCREEN_GSPI		2
+		option TOUCHSCREEN_THC_SPI	3
+		option TOUCHSCREEN_THC_I2C	4
+	end
+	field TOUCHPAD 11 12
+		option TOUCHPAD_NONE		0
+		option TOUCHPAD_THC_I2C		1
+		option TOUCHPAD_LPSS_I2C	2
+	end
+	field SD 13 14
+		option SD_NONE			0
+		option SD_GENSYS		1
+		option SD_BAYHUB		2
+	end
+	field STORAGE 15 16
+		option STORAGE_UNKNOWN		0
+		option STORAGE_NVME_GEN4	1
+		option STORAGE_NVME_GEN5	2
+		option STORAGE_UFS		3
+	end
+	field FP 17
+		option FP_ABSENT		0
+		option FP_PRESENT		1
+	end
+	field DISPLAY 18
+		option DISPLAY_ABSENT		0
+		option DISPLAY_PRESENT		1
+	end
+	field KB 19
+		option KB_ABSENT		0
+		option KB_PRESENT		1
+	end
+	field UFC 20 21
+		option UFC_ABSENT		0
+		option UFC_MIPI			1
+		option UFC_USB			2
+	end
+	field WFC 22 23
+		option WFC_ABSENT		0
+		option WFC_MIPI			1
+		option WFC_USB			2
+	end
+	field ISH 24
+		option ISH_DISABLE		0
+		option ISH_ENABLE		1
+	end
+end
+
+chip soc/intel/pantherlake
+
+	register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC_SKIP)" # USB2_C0
+	register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC_SKIP)" # USB2_C1
+	register "usb2_ports[2]" = "USB2_PORT_TYPE_C(OC_SKIP)" # USB2_C2
+	register "usb2_ports[3]" = "USB2_PORT_TYPE_C(OC_SKIP)" # USB2_C3
+	register "usb2_ports[4]" = "USB2_PORT_MID(OC0)" # Type-A Port A0
+	register "usb2_ports[5]" = "USB2_PORT_MID(OC0)" # Type-A Port A1 / WWAN with rework
+	register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # CNVi BT or discrete BT
+
+	register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)" # USB3.2 x1 Type-A Con #1
+	register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC0)" # USB3.2 x1 Type-A Con #2 / M.2 WWAN with rework
+
+	register "tcss_ports[0]" = "TCSS_PORT_DEFAULT(OC_SKIP)"
+	register "tcss_ports[1]" = "TCSS_PORT_DEFAULT(OC_SKIP)"
+	register "tcss_ports[2]" = "TCSS_PORT_DEFAULT(OC_SKIP)"
+	register "tcss_ports[3]" = "TCSS_PORT_DEFAULT(OC_SKIP)"
+
+	register "tcss_cap_policy[0]" = "TCSS_TYPE_C_PORT_FULL_FUN"
+	register "tcss_cap_policy[1]" = "TCSS_TYPE_C_PORT_FULL_FUN"
+	register "tcss_cap_policy[2]" = "TCSS_TYPE_C_PORT_FULL_FUN"
+	register "tcss_cap_policy[3]" = "TCSS_TYPE_C_PORT_FULL_FUN"
+
+	# Enable EDP in PortA
+	register "ddi_port_A_config" = "1"
+	register "ddi_ports_config" = "{
+                [DDI_PORT_A] = DDI_ENABLE_HPD,
+        }"
+
+	register "serial_io_i2c_mode" = "{
+		[PchSerialIoIndexI2C0]  = PchSerialIoPci,
+		[PchSerialIoIndexI2C1]  = PchSerialIoPci,
+		[PchSerialIoIndexI2C2]  = PchSerialIoPci,
+		[PchSerialIoIndexI2C3]  = PchSerialIoPci,
+		[PchSerialIoIndexI2C4]  = PchSerialIoPci,
+		[PchSerialIoIndexI2C5]  = PchSerialIoPci,
+	}"
+
+	register "serial_io_gspi_mode" = "{
+		[PchSerialIoIndexGSPI0] = PchSerialIoPci,
+		[PchSerialIoIndexGSPI1] = PchSerialIoDisabled,
+		[PchSerialIoIndexGSPI0A] = PchSerialIoDisabled,
+	}"
+
+	# Intel Common SoC Config
+	#+-------------------+---------------------------+
+	#| Field             |  Value                    |
+	#+-------------------+---------------------------+
+	#| I2C1              | Camera(CRD1)              |
+	#| I2C2              | Camera(CRD2)              |
+	#| I2C3              | Audio, TPM(cr50)          |
+	#| I2C4              | Touchscreen               |
+	#| I2C5              | Touchpad                  |
+	#+-------------------+---------------------------+
+	register "common_soc_config" = "{
+		.chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT,
+		.i2c[1] = {
+			.speed = I2C_SPEED_FAST,
+		},
+		.i2c[2] = {
+			.speed = I2C_SPEED_FAST,
+		},
+		.i2c[3] = {
+			.early_init = 1,
+			.speed = I2C_SPEED_FAST,
+		},
+		.i2c[4] = {
+			.speed = I2C_SPEED_FAST,
+		},
+		.i2c[5] = {
+			.speed = I2C_SPEED_FAST,
+		},
+	}"
+
+	device domain 0 on
+		device ref igpu on
+			probe DISPLAY DISPLAY_PRESENT
+			chip drivers/gfx/generic
+				register "device_count" = "5"
+				# DDIA for eDP
+				register "device[0].name" = ""LCD0""
+				register "device[0].type" = "panel"
+				# DDIB for HDMI
+				# If HDMI is not enumerated in the kernel, then no GFX device should be added for DDIB
+				register "device[1].name" = ""DD01""
+				# TCP0 (DP-1) for port C0
+				register "device[2].name" = ""DD02""
+				register "device[2].use_pld" = "true"
+				register "device[2].pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(1, 1))"
+				# TCP1 (DP-2) for port C1
+				register "device[3].name" = ""DD03""
+				register "device[3].use_pld" = "true"
+				register "device[3].pld" = "ACPI_PLD_TYPE_C(LEFT, RIGHT, ACPI_PLD_GROUP(2, 1))"
+				# TCP2 (DP-3) for port C2
+				register "device[4].name" = ""DD04""
+				register "device[4].use_pld" = "true"
+				register "device[4].pld" = "ACPI_PLD_TYPE_C(RIGHT, LEFT, ACPI_PLD_GROUP(3, 1))"
+				device generic 0 on end
+			end
+		end
+
+		device ref dtt on
+			chip drivers/intel/dptf
+				## sensor information
+				register "options.tsr[0].desc" = ""DDR_SOC""
+				register "options.tsr[1].desc" = ""Ambient""
+				register "options.tsr[2].desc" = ""Charger""
+				register "options.tsr[3].desc" = ""wwan""
+
+				## Active Policy
+				# FIXME: below values are initial reference values only
+				register "policies.active" = "{
+						[0] = {
+							.target = DPTF_TEMP_SENSOR_0,
+							.thresholds = {
+									TEMP_PCT(70, 97),
+									TEMP_PCT(65, 90),
+									TEMP_PCT(60, 80),
+									TEMP_PCT(55, 75),
+									TEMP_PCT(50, 65),
+									TEMP_PCT(45, 45),
+									TEMP_PCT(43, 30),
+								}
+							},
+						[1] = {
+							.target = DPTF_TEMP_SENSOR_1,
+							.thresholds = {
+									TEMP_PCT(70, 97),
+									TEMP_PCT(65, 90),
+									TEMP_PCT(60, 80),
+									TEMP_PCT(55, 75),
+									TEMP_PCT(50, 65),
+									TEMP_PCT(45, 45),
+									TEMP_PCT(43, 30),
+								}
+							},
+						[2] = {
+							.target = DPTF_TEMP_SENSOR_2,
+							.thresholds = {
+									TEMP_PCT(75, 90),
+									TEMP_PCT(70, 80),
+									TEMP_PCT(65, 70),
+									TEMP_PCT(60, 50),
+								}
+							},
+						[3] = {
+							.target = DPTF_TEMP_SENSOR_3,
+							.thresholds = {
+									TEMP_PCT(75, 90),
+									TEMP_PCT(70, 80),
+									TEMP_PCT(65, 70),
+									TEMP_PCT(60, 60),
+									TEMP_PCT(55, 50),
+									TEMP_PCT(50, 40),
+									TEMP_PCT(45, 30),
+								}
+							}
+				}"
+
+				## Passive Policy
+				# TODO: below values are initial reference values only
+				register "policies.passive" = "{
+						[0] = DPTF_PASSIVE(CPU,         CPU,           95, 5000),
+						[1] = DPTF_PASSIVE(CPU,         TEMP_SENSOR_0, 80, 5000),
+						[2] = DPTF_PASSIVE(CPU,         TEMP_SENSOR_1, 80, 5000),
+						[3] = DPTF_PASSIVE(CHARGER,     TEMP_SENSOR_2, 75, 5000),
+						[4] = DPTF_PASSIVE(CPU,         TEMP_SENSOR_3, 80, 5000),
+				}"
+
+				## Critical Policy
+				# TODO: below values are initial reference values only
+				register "policies.critical" = "{
+						[0] = DPTF_CRITICAL(CPU,          105, SHUTDOWN),
+						[1] = DPTF_CRITICAL(TEMP_SENSOR_0, 85, SHUTDOWN),
+						[2] = DPTF_CRITICAL(TEMP_SENSOR_1, 85, SHUTDOWN),
+						[3] = DPTF_CRITICAL(TEMP_SENSOR_2, 85, SHUTDOWN),
+						[4] = DPTF_CRITICAL(TEMP_SENSOR_3, 85, SHUTDOWN),
+				}"
+
+				## Power Limits Control
+				register "controls.power_limits" = "{
+						.pl1 = {
+							.min_power = 25000,
+							.max_power = 25000,
+							.time_window_min = 28 * MSECS_PER_SEC,
+							.time_window_max = 32 * MSECS_PER_SEC,
+							.granularity = 200,
+						},
+						.pl2 = {
+							.min_power = 95000,
+							.max_power = 95000,
+							.time_window_min = 28 * MSECS_PER_SEC,
+							.time_window_max = 32 * MSECS_PER_SEC,
+							.granularity = 1000,
+						}
+				}"
+
+				## Charger Performance Control (Control, mA)
+				register "controls.charger_perf" = "{
+						[0] = { 255, 3000 },
+						[1] = {  24, 1500 },
+						[2] = {  16, 1000 },
+						[3] = {   8,  500 }
+				}"
+
+				## Fan Performance Control (Percent, Speed, Noise, Power)
+				register "controls.fan_perf" = "{
+						[0] = {  90, 6700, 220, 2200, },
+						[1] = {  80, 5800, 180, 1800, },
+						[2] = {  70, 5000, 145, 1450, },
+						[3] = {  60, 4900, 115, 1150, },
+						[4] = {  50, 3838,  90,  900, },
+						[5] = {  40, 2904,  55,  550, },
+						[6] = {  30, 2337,  30,  300, },
+						[7] = {  20, 1608,  15,  150, },
+						[8] = {  10,  800,  10,  100, },
+						[9] = {   0,    0,   0,   50, }
+				}"
+
+				## Fan options
+				register "options.fan.fine_grained_control" = "true"
+				register "options.fan.step_size" = "2"
+
+				device generic 0 alias dptf_policy on end
+			end
+		end
+
+		device ref ipu on
+			chip drivers/intel/mipi_camera
+				register "acpi_uid" = "0x50000"
+				register "acpi_name" = ""IPU0""
+				register "device_type" = "INTEL_ACPI_CAMERA_CIO2"
+				register "cio2_num_ports" = "2"
+				register "cio2_lanes_used" = "{4,2}" # 4 and 2 CSI Camera lanes are used
+				register "cio2_lane_endpoint[0]" = ""^I2C1.CAM0""
+				register "cio2_lane_endpoint[1]" = ""^I2C2.CAM1""
+				register "cio2_prt[0]" = "0"
+				register "cio2_prt[1]" = "2"
+				device generic 0 on
+					probe UFC UFC_MIPI
+					probe WFC WFC_MIPI
+				end
+			end
+		end
+
+		device ref iaa off end
+
+		device ref thc0 on
+			probe TOUCHSCREEN TOUCHSCREEN_THC_SPI
+			probe TOUCHSCREEN TOUCHSCREEN_THC_I2C
+			# THC0 is function 0; hence it needs to be enabled when THC1 is to be enabled.
+			probe TOUCHPAD TOUCHPAD_THC_I2C
+		end
+		device ref thc1 on
+			probe TOUCHPAD TOUCHPAD_THC_I2C
+		end
+
+		device ref tbt_pcie_rp0 on end
+		device ref tbt_pcie_rp1 on end
+		device ref tbt_pcie_rp2 on end
+		device ref tbt_pcie_rp3 on end
+		device ref tcss_xhci on
+			chip drivers/usb/acpi
+				device ref tcss_root_hub on
+					chip drivers/usb/acpi
+						register "desc" = ""USB3 Type-C Port C0""
+						register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
+						register "group" = "ACPI_PLD_GROUP(4, 2)"
+						device ref tcss_usb3_port0 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB3 Type-C Port C1""
+						register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
+						register "group" = "ACPI_PLD_GROUP(3, 2)"
+						device ref tcss_usb3_port1 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB3 Type-C Port C2""
+						register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
+						register "group" = "ACPI_PLD_GROUP(2, 2)"
+						device ref tcss_usb3_port2 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB3 Type-C Port C3""
+						register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
+						register "group" = "ACPI_PLD_GROUP(1, 2)"
+						device ref tcss_usb3_port3 on end
+					end
+				end
+			end
+		end
+
+		device ref tcss_dma0 on
+			chip drivers/intel/usb4/retimer
+				register "dfp[0].power_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B21)"
+				use tcss_usb3_port0 as dfp[0].typec_port
+				device generic 0 on end
+			end
+			chip drivers/intel/usb4/retimer
+				register "dfp[1].power_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B21)"
+				use tcss_usb3_port1 as dfp[1].typec_port
+				device generic 0 on end
+			end
+		end
+		device ref tcss_dma1 on
+			chip drivers/intel/usb4/retimer
+				register "dfp[0].power_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B21)"
+				use tcss_usb3_port2 as dfp[0].typec_port
+				device generic 0 on end
+			end
+			chip drivers/intel/usb4/retimer
+				register "dfp[1].power_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B21)"
+				use tcss_usb3_port3 as dfp[1].typec_port
+				device generic 0 on end
+			end
+		end
+
+		device ref ish on
+			probe ISH ISH_ENABLE
+			probe FP FP_PRESENT
+			chip drivers/intel/ish
+				register "add_acpi_dma_property" = "true"
+				device generic 0 on end
+			end
+		end
+
+		device ref xhci on
+			chip drivers/usb/acpi
+				device ref xhci_root_hub on
+					chip drivers/usb/acpi
+						register "desc" = ""USB2 Type-C Port C0""
+						register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
+						register "group" = "ACPI_PLD_GROUP(1, 1)"
+						device ref usb2_port1 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB2 Type-C Port C1""
+						register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
+						register "group" = "ACPI_PLD_GROUP(2, 1)"
+						device ref usb2_port2 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB2 Type-C Port C2""
+						register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
+						register "group" = "ACPI_PLD_GROUP(3, 1)"
+						device ref usb2_port3 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB2 Type-C Port C3""
+						register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
+						register "group" = "ACPI_PLD_GROUP(4, 1)"
+						device ref usb2_port4 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB2 Type-A Port 1""
+						register "type" = "UPC_TYPE_A"
+						register "group" = "ACPI_PLD_GROUP(5, 1)"
+						device ref usb2_port5 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB2 Type-A Port 2""
+						register "type" = "UPC_TYPE_A"
+						register "group" = "ACPI_PLD_GROUP(6, 1)"
+						device ref usb2_port6 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB2 Type-A Port 3""
+						register "type" = "UPC_TYPE_A"
+						register "group" = "ACPI_PLD_GROUP(7, 1)"
+						device ref usb2_port7 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB2 Bluetooth""
+						register "type" = "UPC_TYPE_INTERNAL"
+						register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A16)"
+						device ref usb2_port8 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB3 Type-A Port 1""
+						register "type" = "UPC_TYPE_USB3_A"
+						register "group" = "ACPI_PLD_GROUP(1, 2)"
+						device ref usb3_port1 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB3 Type-A Port 2""
+						register "type" = "UPC_TYPE_USB3_A"
+						register "group" = "ACPI_PLD_GROUP(2, 2)"
+						device ref usb3_port2 on end
+					end
+				end
+			end
+		end
+
+		device ref ufs on
+			probe STORAGE STORAGE_UFS
+			probe STORAGE STORAGE_UNKNOWN
+		end
+
+		device ref pcie_rp2 on
+			probe CELLULAR CELLULAR_PCIE
+			register "pcie_rp[PCIE_RP(2)]" = "{
+				.clk_src = 5,
+				.clk_req = 5,
+				.flags = PCIE_RP_CLK_REQ_DETECT | PCIE_RP_LTR | PCIE_RP_AER,
+			}"
+			chip soc/intel/common/block/pcie/rtd3
+				register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D03)"
+				register "reset_off_delay_ms" = "20"
+				register "srcclk_pin" = "5"
+				register "ext_pm_support" = "ACPI_PCIE_RP_EMIT_ALL"
+				register "skip_on_off_support" = "true"
+				register "use_rp_mutex" = "true"
+				device generic 0 alias rp2_rtd3 on end
+			end
+			chip drivers/wwan/fm
+				register "fcpo_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A09)"
+				register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B20)"
+				register "perst_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D03)"
+				register "wake_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_E02)"
+				register "add_acpi_dma_property" = "true"
+				use rp2_rtd3 as rtd3dev
+				device generic 0 on end
+			end
+		end # WWAN
+		device ref pcie_rp3 on
+			probe SD SD_GENSYS
+			probe SD SD_BAYHUB
+			# Enable PCH PCIE x1 slot using CLK 3
+			register "pcie_rp[PCIE_RP(3)]" = "{
+				.clk_src = 2,
+				.clk_req = 2,
+				.flags = PCIE_RP_CLK_REQ_DETECT | PCIE_RP_LTR | PCIE_RP_AER,
+			}"
+			chip soc/intel/common/block/pcie/rtd3
+				register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A08)"
+				register "enable_delay_ms" = "100"
+				register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D19)"
+				register "reset_delay_ms" = "20"
+				register "srcclk_pin" = "2"
+				device generic 0 on end
+			end
+		end # PCIE x1 slot
+		device ref pcie_rp4 on
+			probe WIFI WIFI_PCIE_6
+			probe WIFI WIFI_PCIE_7
+			register "pcie_rp[PCH_RP(4)]" = "{
+				.clk_src = 4,
+				.clk_req = 4,
+				.flags = PCIE_RP_CLK_REQ_DETECT | PCIE_RP_LTR | PCIE_RP_AER,
+			}"
+			chip soc/intel/common/block/pcie/rtd3
+				register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A11)"
+				register "srcclk_pin" = "4"
+				device pci 00.0 on end
+			end
+			chip drivers/wifi/generic
+				register "add_acpi_dma_property" = "true"
+				register "wake" = "GPE0_DW0_12" # GPP_A12
+				use usb2_port7 as bluetooth_companion
+				device pci 00.0 on end
+			end
+		end # discrete WLAN
+		device ref pcie_rp5 on
+			probe STORAGE STORAGE_NVME_GEN4
+			probe STORAGE STORAGE_UNKNOWN
+			register "pcie_rp[PCIE_RP(5)]" = "{
+			.clk_src = 6,
+			.clk_req = 6,
+			.flags = PCIE_RP_CLK_REQ_DETECT | PCIE_RP_LTR | PCIE_RP_AER,
+			}"
+			chip soc/intel/common/block/pcie/rtd3
+				register "is_storage" = "true"
+				register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B10)"
+				register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B09)"
+				register "srcclk_pin" = "6"
+				device generic 0 on end
+			end
+		end # Gen4 M.2 SSD
+		device ref pcie_rp9 on
+			probe STORAGE STORAGE_NVME_GEN5
+			probe STORAGE STORAGE_UNKNOWN
+			register "pcie_rp[PCIE_RP(9)]" = "{
+			.clk_src = 1,
+			.clk_req = 1,
+			.flags = PCIE_RP_CLK_REQ_DETECT | PCIE_RP_LTR | PCIE_RP_AER,
+			}"
+			chip soc/intel/common/block/pcie/rtd3
+				register "is_storage" = "true"
+				register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B16)"
+				register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_E03)"
+				register "srcclk_pin" = "1"
+				device generic 0 on end
+			end
+		end # Gen5 M.2 SSD
+		device ref cnvi_wifi on
+			probe WIFI WIFI_CNVI_6
+			probe WIFI WIFI_CNVI_7
+			chip drivers/wifi/generic
+				register "wake" = "GPE0_PME_B0"
+				register "add_acpi_dma_property" = "true"
+				register "enable_cnvi_ddr_rfim" = "true"
+				device generic 0 on end
+			end
+		end # CNVi
+		# NOTE: i2c0 is function 0; hence it needs to be enabled when any of i2c1-5 is enabled.
+		# TPM device is under i2c3. Therefore, i2c0 needs to be enabled anyways.
+		device ref i2c0 on end
+		device ref i2c1 on
+			chip drivers/intel/mipi_camera
+				register "acpi_hid" = ""OVTIDB10""
+				register "acpi_uid" = "0"
+				register "acpi_name" = ""CAM0""
+				register "chip_name" = ""Ov 13b10 Camera""
+				register "device_type" = "INTEL_ACPI_CAMERA_SENSOR"
+
+				register "ssdb.vcm_type" = "0x0C"
+				register "vcm_name" = ""VCM1""
+
+				register "ssdb.lanes_used" = "4"
+				register "num_freq_entries" = "1"
+				register "link_freq[0]" = "560 * MHz" # 560 MHz
+				register "remote_name" = ""IPU0""
+				register "max_dstate_for_probe" = "ACPI_DEVICE_SLEEP_D3_COLD"
+
+				register "has_power_resource" = "true"
+				#Controls
+				register "clk_panel.clks[0].clknum" = "0" # IMGCLKOUT_0
+				register "clk_panel.clks[0].freq" = "1" #19.2 Mhz
+				register "gpio_panel.gpio[0].gpio_num" = "GPP_C05" #power_enable
+				register "gpio_panel.gpio[1].gpio_num" = "GPP_E10" #reset
+
+				#_ON
+				register "on_seq.ops_cnt" = "4"
+				register "on_seq.ops[0]" = "SEQ_OPS_CLK_ENABLE(0, 0)"
+				register "on_seq.ops[1]" = "SEQ_OPS_GPIO_ENABLE(0, 2)"
+				register "on_seq.ops[2]" = "SEQ_OPS_GPIO_DISABLE(1, 1)"
+				register "on_seq.ops[3]" = "SEQ_OPS_GPIO_ENABLE(1, 1)"
+
+				#_OFF
+				register "off_seq.ops_cnt" = "3"
+				register "off_seq.ops[0]" = "SEQ_OPS_CLK_DISABLE(0, 0)"
+				register "off_seq.ops[1]" = "SEQ_OPS_GPIO_DISABLE(1, 0)"
+				register "off_seq.ops[2]" = "SEQ_OPS_GPIO_DISABLE(0, 0)"
+
+				device i2c 36 on
+					probe WFC WFC_MIPI
+				end
+			end
+			chip drivers/intel/mipi_camera
+				register "acpi_uid" = "3"
+				register "acpi_name" = ""VCM1""
+				register "chip_name" = ""DW AF VCM""
+				register "device_type" = "INTEL_ACPI_CAMERA_VCM"
+
+				register "vcm_compat" = ""dongwoon,dw9714""
+
+				register "max_dstate_for_probe" = "ACPI_DEVICE_SLEEP_D0"
+
+				register "has_power_resource" = "true"
+
+				#Controls
+				register "gpio_panel.gpio[0].gpio_num" = "GPP_C05" #power_enable
+
+				#_ON
+				register "on_seq.ops_cnt" = "1"
+				register "on_seq.ops[0]" = "SEQ_OPS_GPIO_ENABLE(0, 0)"
+
+				#_OFF
+				register "off_seq.ops_cnt" = "1"
+				register "off_seq.ops[0]" = "SEQ_OPS_GPIO_DISABLE(0, 0)"
+
+				device i2c 0C on
+					probe WFC WFC_MIPI
+				end
+			end
+			chip drivers/intel/mipi_camera
+				register "acpi_uid" = "1"
+				register "acpi_name" = ""NVM1""
+				register "chip_name" = ""BRCA016GWZ""
+				register "device_type" = "INTEL_ACPI_CAMERA_NVM"
+
+				register "nvm_compat" = ""atmel,24c16""
+
+				register "nvm_size" = "0x800"
+				register "nvm_pagesize" = "0x01"
+				register "nvm_readonly" = "0x01"
+				register "nvm_width" = "0x08"
+
+				register "max_dstate_for_probe" = "ACPI_DEVICE_SLEEP_D0"
+
+				register "has_power_resource" = "true"
+
+				#Controls
+				register "gpio_panel.gpio[0].gpio_num" = "GPP_C05" #power_enable
+
+				#_ON
+				register "on_seq.ops_cnt" = "1"
+				register "on_seq.ops[0]" = "SEQ_OPS_GPIO_ENABLE(0, 0)"
+
+				#_OFF
+				register "off_seq.ops_cnt" = "1"
+				register "off_seq.ops[0]" = "SEQ_OPS_GPIO_DISABLE(0, 0)"
+
+				device i2c 50 on
+					probe WFC WFC_MIPI
+				end
+			end
+		end # I2C1
+		device ref i2c2 on
+			chip drivers/intel/mipi_camera
+				register "acpi_hid" = ""OVTIDB10""
+				register "acpi_uid" = "0"
+				register "acpi_name" = ""CAM1""
+				register "chip_name" = ""Ov 13b10 Camera""
+				register "device_type" = "INTEL_ACPI_CAMERA_SENSOR"
+
+				register "ssdb.vcm_type" = "0x0C"
+				register "vcm_name" = ""VCM1""
+
+				register "ssdb.lanes_used" = "2"
+				register "num_freq_entries" = "1"
+				register "link_freq[0]" = "560 * MHz" # 560 MHz
+				register "remote_name" = ""IPU0""
+				register "max_dstate_for_probe" = "ACPI_DEVICE_SLEEP_D3_COLD"
+
+				register "has_power_resource" = "true"
+				#Controls
+				register "clk_panel.clks[0].clknum" = "1" # IMGCLKOUT_1
+				register "clk_panel.clks[0].freq" = "1" #19.2 Mhz
+				register "gpio_panel.gpio[0].gpio_num" = "GPP_C08" #power_enable
+				register "gpio_panel.gpio[1].gpio_num" = "GPP_E01" #reset
+
+				#_ON
+				register "on_seq.ops_cnt" = "4"
+				register "on_seq.ops[0]" = "SEQ_OPS_CLK_ENABLE(0, 0)"
+				register "on_seq.ops[1]" = "SEQ_OPS_GPIO_ENABLE(0, 2)"
+				register "on_seq.ops[2]" = "SEQ_OPS_GPIO_DISABLE(1, 1)"
+				register "on_seq.ops[3]" = "SEQ_OPS_GPIO_ENABLE(1, 1)"
+
+				#_OFF
+				register "off_seq.ops_cnt" = "3"
+				register "off_seq.ops[0]" = "SEQ_OPS_CLK_DISABLE(0, 0)"
+				register "off_seq.ops[1]" = "SEQ_OPS_GPIO_DISABLE(1, 0)"
+				register "off_seq.ops[2]" = "SEQ_OPS_GPIO_DISABLE(0, 0)"
+
+				device i2c 36 on
+					probe UFC UFC_MIPI
+				end
+			end
+			chip drivers/intel/mipi_camera
+				register "acpi_uid" = "3"
+				register "acpi_name" = ""VCM1""
+				register "chip_name" = ""DW AF VCM""
+				register "device_type" = "INTEL_ACPI_CAMERA_VCM"
+
+				register "vcm_compat" = ""dongwoon,dw9714""
+
+				register "max_dstate_for_probe" = "ACPI_DEVICE_SLEEP_D0"
+
+				register "has_power_resource" = "true"
+
+				#Controls
+				register "gpio_panel.gpio[0].gpio_num" = "GPP_C08" #power_enable
+
+				#_ON
+				register "on_seq.ops_cnt" = "1"
+				register "on_seq.ops[0]" = "SEQ_OPS_GPIO_ENABLE(0, 0)"
+
+				#_OFF
+				register "off_seq.ops_cnt" = "1"
+				register "off_seq.ops[0]" = "SEQ_OPS_GPIO_DISABLE(0, 0)"
+
+				device i2c 0C on
+					probe UFC UFC_MIPI
+				end
+			end
+			chip drivers/intel/mipi_camera
+				register "acpi_uid" = "1"
+				register "acpi_name" = ""NVM1""
+				register "chip_name" = ""BRCA016GWZ""
+				register "device_type" = "INTEL_ACPI_CAMERA_NVM"
+
+				register "nvm_compat" = ""atmel,24c16""
+
+				register "nvm_size" = "0x800"
+				register "nvm_pagesize" = "0x01"
+				register "nvm_readonly" = "0x01"
+				register "nvm_width" = "0x08"
+
+				register "max_dstate_for_probe" = "ACPI_DEVICE_SLEEP_D0"
+
+				register "has_power_resource" = "true"
+
+				#Controls
+				register "gpio_panel.gpio[0].gpio_num" = "GPP_C08" #power_enable
+
+				#_ON
+				register "on_seq.ops_cnt" = "1"
+				register "on_seq.ops[0]" = "SEQ_OPS_GPIO_ENABLE(0, 0)"
+
+				#_OFF
+				register "off_seq.ops_cnt" = "1"
+				register "off_seq.ops[0]" = "SEQ_OPS_GPIO_DISABLE(0, 0)"
+
+				device i2c 50 on
+					probe UFC UFC_MIPI
+				end
+			end
+		end # I2C2
+		device ref i2c3 on
+			chip drivers/i2c/generic
+				register "hid" = ""RTL5682""
+				register "name" = ""RT58""
+				register "desc" = ""Headset Codec""
+				register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_F17)"
+				# Set the jd_src to RT5668_JD1 for jack detection
+				register "property_count" = "1"
+				register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER"
+				register "property_list[0].name" = ""realtek,jd-src""
+				register "property_list[0].integer" = "1"
+				device i2c 1a on
+					probe AUDIO AUDIO_MAX98360_ALC5682I_I2S
+				end
+			end
+			chip drivers/i2c/tpm
+				register "hid" = ""GOOG0005""
+				register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_D15_IRQ)"
+				device i2c 50 on end
+			end
+		end # I2C3
+		device ref i2c4 on
+			chip drivers/i2c/hid
+				register "generic.hid" = ""ELAN6918""
+				register "generic.desc" = ""ELAN Touchscreen""
+				register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_E18_IRQ)"
+				register "generic.probed" = "1"
+				register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_E16)"
+				register "generic.reset_delay_ms" = "20"
+				register "generic.reset_off_delay_ms" = "2"
+				register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_F08)"
+				register "generic.enable_delay_ms" = "1"
+				register "generic.has_power_resource" = "1"
+				register "hid_desc_reg_offset" = "0x01"
+				device i2c 16 on
+					probe TOUCHSCREEN TOUCHSCREEN_LPSS_I2C
+				end
+			end
+		end # I2C4
+		device ref i2c5 on
+			chip drivers/i2c/hid
+				register "generic.hid" = ""HFW68H""
+				register "generic.desc" = ""Hynitron TOUCHPAD""
+				register "generic.irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_A13_IRQ)"
+				register "generic.wake" = "GPE0_DW0_13"
+				register "generic.uid" = "5"
+				register "generic.detect" = "1"
+				register "hid_desc_reg_offset" = "0x20"
+				device i2c 2c on
+					probe TOUCHPAD TOUCHPAD_LPSS_I2C
+				end
+			end
+		end # I2C5
+
+		device ref gspi0 on
+			chip drivers/spi/acpi
+				register "name" = ""CRFP""
+				register "hid" = "ACPI_DT_NAMESPACE_HID"
+				register "uid" = "1"
+				register "compat_string" = ""google,cros-ec-spi""
+				register "irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_D01_IRQ)"
+				register "wake" = "GPE0_DW1_01"
+				register "has_power_resource" = "true"
+				register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C15)"
+				register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E19)"
+				register "enable_delay_ms" = "3"
+				device spi 0 on
+					probe FP FP_PRESENT
+				end
+			end # FPMCU
+		end
+
+		device ref smbus on end
+		device ref npk on end
+		device ref hda on
+			chip drivers/intel/soundwire
+				device generic 0 on
+					chip drivers/soundwire/alc711
+						register "desc" = ""Headset Codec""
+						register "alc711_address.version" = "SOUNDWIRE_VERSION_1_2"
+						register "alc711_address.class" = "MIPI_CLASS_SDCA"
+						register "alc711_address.part_id" = "MIPI_DEV_ID_REALTEK_ALC722"
+						# SoundWire Link 1 ID 1
+						device generic 1.1 on
+							probe AUDIO AUDIO_ALC722_SNDW
+						end
+					end
+					chip drivers/soundwire/alc711
+						register "desc" = ""Headset Codec""
+						register "alc711_address.version" = "SOUNDWIRE_VERSION_1_2"
+						register "alc711_address.class" = "MIPI_CLASS_SDCA"
+						register "alc711_address.part_id" = "MIPI_DEV_ID_REALTEK_ALC721"
+						# SoundWire Link 3 ID 1
+						device generic 3.1 on
+							probe AUDIO AUDIO_ALC721_SNDW
+						end
+					end
+				end
+			end
+			chip drivers/generic/max98357a
+				register "hid" = ""MX98360A""
+				register "sdmode_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E19)"
+				register "sdmode_delay" = "5"
+				device generic 0 on
+					probe AUDIO AUDIO_MAX98360_ALC5682I_I2S
+				end
+			end
+		end
+	end
+end
diff --git a/src/mainboard/google/ocelot/variants/ocelot/variant.c b/src/mainboard/google/ocelot/variants/ocelot/variant.c
new file mode 100644
index 0000000000..c7aa7aa605
--- /dev/null
+++ b/src/mainboard/google/ocelot/variants/ocelot/variant.c
@@ -0,0 +1,30 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <acpi/acpigen.h>
+#include <baseboard/variants.h>
+#include <fw_config.h>
+#include <sar.h>
+
+const char *get_wifi_sar_cbfs_filename(void)
+{
+	return get_wifi_sar_fw_config_filename(FW_CONFIG_FIELD(WIFI));
+}
+
+void variant_update_soc_chip_config(struct soc_intel_pantherlake_config *config)
+{
+	config->cnvi_wifi_core = false;
+	config->cnvi_bt_core = false;
+	/* CNVi */
+	if (fw_config_probe(FW_CONFIG(WIFI, WIFI_CNVI_6)) ||
+		fw_config_probe(FW_CONFIG(WIFI, WIFI_CNVI_7))) {
+		config->cnvi_wifi_core = true;
+		config->cnvi_bt_core = true;
+
+		if (fw_config_probe(FW_CONFIG(AUDIO, AUDIO_MAX98360_ALC5682I_I2S)) ||
+			fw_config_probe(FW_CONFIG(AUDIO, AUDIO_ALC722_SNDW)) ||
+			fw_config_probe(FW_CONFIG(AUDIO, AUDIO_ALC721_SNDW))) {
+			printk(BIOS_INFO, "BT audio offload configured.\n");
+			config->cnvi_bt_audio_offload = true;
+		}
+	}
+}

From a7a76b0deea3cc93b8452db85380bb6727b55ebf Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Wed, 26 Feb 2025 11:33:00 -0600
Subject: [PATCH 0277/3886] soc/intel/meteorlake: Hook up FSP repo for IOT

IOT FSP binaries for MTL are available on github, so add FSP_TYPE_IOT
Kconfig option, select 'HAVE_INTEL_FSP_REPO', and add the paths for the
FSP headers and binary.

TEST=build/boot starlabs/starbook_mtl

Change-Id: I44ee923f4d1151f0e11104af7db53ce59551cf37
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86611
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
---
 src/soc/intel/meteorlake/Kconfig | 15 ++++++++++++++-
 1 file changed, 14 insertions(+), 1 deletion(-)

diff --git a/src/soc/intel/meteorlake/Kconfig b/src/soc/intel/meteorlake/Kconfig
index d5b4a065a8..cebf414f11 100644
--- a/src/soc/intel/meteorlake/Kconfig
+++ b/src/soc/intel/meteorlake/Kconfig
@@ -37,7 +37,7 @@ config SOC_INTEL_METEORLAKE
 	select INTEL_GMA_VERSION_2
 	select IOAPIC
 	select MP_SERVICES_PPI_V2
-	select MRC_CACHE_USING_MRC_VERSION
+	select MRC_CACHE_USING_MRC_VERSION if !FSP_USE_REPO
 	select MRC_SETTINGS_PROTECT
 	select PARALLEL_MP_AP_WORK
 	select PCIE_CLOCK_CONTROL_THROUGH_P2SB
@@ -345,14 +345,27 @@ config CONSOLE_CBMEM_BUFFER_SIZE
 	default 0x100000 if BUILDING_WITH_DEBUG_FSP
 	default 0x40000
 
+config FSP_TYPE_IOT
+	bool
+	select HAVE_INTEL_FSP_REPO
+	default n
+	help
+	  This option allows to select FSP IOT type from 3rdparty/fsp repo
+
+config FSP_USE_REPO
+	default y if FSP_TYPE_IOT
+	default n
+
 config FSP_HEADER_PATH
 	string "Location of FSP headers"
+	default "3rdparty/fsp/MeteorLakeFspBinPkg/IoT/MeteorLake/Include" if FSP_USE_REPO && FSP_TYPE_IOT
 	default "src/vendorcode/intel/fsp/fsp2_0/meteorlake/x86_64/" if HAVE_X86_64_SUPPORT
 	default "src/vendorcode/intel/fsp/fsp2_0/meteorlake/x86_32/"
 
 config FSP_FD_PATH
 	string
 	depends on FSP_USE_REPO
+	default "3rdparty/fsp/MeteorLakeFspBinPkg/IoT/MeteorLake/Fsp.fd" if FSP_TYPE_IOT
 	default "3rdparty/fsp/MeteorLakeFspBinPkg/Fsp.fd"
 
 # Override platform debug consent value:

From 5c4f49708c75ad1d474c12edced1d41acdabdda3 Mon Sep 17 00:00:00 2001
From: Yang Wu <wuyang5@huaqin.corp-partner.google.com>
Date: Wed, 26 Feb 2025 21:04:51 +0800
Subject: [PATCH 0278/3886] mb/google/geralt: Adjust VSP/VSN voltage for
 CSOT_PNA957QT1_1 panel

The system default VSP/VSN voltage for Ciri is +-5.7V, which causes
the Gray screen pattern to display abnormally with screen corruption.

According to CSOT panel vendor's requirement, VSP/VSN for the
CSOT_PNA957QT1_1 panel needs to be adjusted to +-6V. So modify the
relevant register values accordingly.

BUG=b:399728328
TEST=Boot to firmware screen and kernel, measure the voltage.
BRANCH=geralt

Change-Id: I1b69303317f5ef47818f4a6a0c851bf650285e51
Signed-off-by: Yang Wu <wuyang5@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86640
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
---
 src/mainboard/google/geralt/panel_ciri.c | 24 ++++++++++++++++++------
 1 file changed, 18 insertions(+), 6 deletions(-)

diff --git a/src/mainboard/google/geralt/panel_ciri.c b/src/mainboard/google/geralt/panel_ciri.c
index 4c21e90b3c..448f0c4fff 100644
--- a/src/mainboard/google/geralt/panel_ciri.c
+++ b/src/mainboard/google/geralt/panel_ciri.c
@@ -7,12 +7,14 @@
 #include "panel.h"
 
 #define PMIC_TPS65132_I2C	I2C3
+#define VOLTAGE_5_7V	0x11
+#define VOLTAGE_6V	0x14
 
-static void power_on_mipi_himax_83102j(void)
+static void power_on_mipi_himax_83102j(uint8_t voltage_reg_val)
 {
 	const struct tps65132s_reg_setting reg_settings[] = {
-		{ PMIC_TPS65132_VPOS, 0x11, 0x1f },
-		{ PMIC_TPS65132_VNEG, 0x11, 0x1f },
+		{ PMIC_TPS65132_VPOS, voltage_reg_val, 0x1f },
+		{ PMIC_TPS65132_VNEG, voltage_reg_val, 0x1f },
 		{ PMIC_TPS65132_DLYX, 0x55, 0xff },
 		{ PMIC_TPS65132_ASSDD, 0x5b, 0xff },
 	};
@@ -27,10 +29,20 @@ static void power_on_mipi_himax_83102j(void)
 	power_on_mipi_panel(&cfg);
 }
 
+static void power_on_mipi_himax_83102j_5_7v(void)
+{
+	power_on_mipi_himax_83102j(VOLTAGE_5_7V);
+}
+
+static void power_on_mipi_himax_83102j_6v(void)
+{
+	power_on_mipi_himax_83102j(VOLTAGE_6V);
+}
+
 static struct panel_description ciri_panels[] = {
 	[17] = {
 		.name = "BOE_NV110WUM_L60",
-		.power_on = power_on_mipi_himax_83102j,
+		.power_on = power_on_mipi_himax_83102j_5_7v,
 		.configure_backlight = configure_mipi_pwm_backlight,
 		.orientation = LB_FB_ORIENTATION_LEFT_UP,
 		.disp_path = DISP_PATH_MIPI,
@@ -39,7 +51,7 @@ static struct panel_description ciri_panels[] = {
 
 	[34] = {
 		.name = "IVO_T109NW41",
-		.power_on = power_on_mipi_himax_83102j,
+		.power_on = power_on_mipi_himax_83102j_5_7v,
 		.configure_backlight = configure_mipi_pwm_backlight,
 		.orientation = LB_FB_ORIENTATION_LEFT_UP,
 		.disp_path = DISP_PATH_MIPI,
@@ -48,7 +60,7 @@ static struct panel_description ciri_panels[] = {
 
 	[51] = {
 		.name = "CSOT_PNA957QT1_1",
-		.power_on = power_on_mipi_himax_83102j,
+		.power_on = power_on_mipi_himax_83102j_6v,
 		.configure_backlight = configure_mipi_pwm_backlight,
 		.orientation = LB_FB_ORIENTATION_LEFT_UP,
 		.disp_path = DISP_PATH_MIPI,

From 4a2a3e7b96459668a5d130f3f8ea0fc05b06027c Mon Sep 17 00:00:00 2001
From: Felix Held <felix-coreboot@felixheld.de>
Date: Fri, 14 Feb 2025 20:32:05 +0100
Subject: [PATCH 0279/3886] acpi/acpigen: implement
 acpigen_write_if_lnotequal_*

Implement functions to write the AML bytes corresponding to
'If (LNotEqual (...))' which is equivalent to 'If (LNot (LEqual (...)))'
for the value types combinations 2 OPs, OP and value, and namestring and
value.

TEST=Calling 'acpigen_write_if_lnotequal_op_int' results in the AML code
sequence being written which decompiles to ASL as expected.

Change-Id: I6c664bc4d30a49ae990eeb9f0e0776cac37efc57
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86464
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
---
 src/acpi/acpigen.c         | 57 ++++++++++++++++++++++++++++++++++++++
 src/include/acpi/acpigen.h |  3 ++
 2 files changed, 60 insertions(+)

diff --git a/src/acpi/acpigen.c b/src/acpi/acpigen.c
index 308cf5ac85..eaf95e018f 100644
--- a/src/acpi/acpigen.c
+++ b/src/acpi/acpigen.c
@@ -1596,6 +1596,25 @@ void acpigen_write_if_lequal_op_op(uint8_t op1, uint8_t op2)
 	acpigen_emit_byte(op2);
 }
 
+/*
+ * Generates ACPI code for checking if operand1 and operand2 are not equal.
+ * Both operand1 and operand2 are ACPI ops.
+ *
+ * If (Lnotequal (op1, op2))
+ *
+ * This is equivalent to
+ *
+ * If (Lnot (Lequal (op1, op2)))
+ */
+void acpigen_write_if_lnotequal_op_op(uint8_t op1, uint8_t op2)
+{
+	acpigen_write_if();
+	acpigen_emit_byte(LNOT_OP);
+	acpigen_emit_byte(LEQUAL_OP);
+	acpigen_emit_byte(op1);
+	acpigen_emit_byte(op2);
+}
+
 /*
  * Generates ACPI code for checking if operand1 is greater than operand2.
  * Both operand1 and operand2 are ACPI ops.
@@ -1624,6 +1643,25 @@ void acpigen_write_if_lequal_op_int(uint8_t op, uint64_t val)
 	acpigen_write_integer(val);
 }
 
+/*
+ * Generates ACPI code for checking if operand1 and operand2 are not equal, where,
+ * operand1 is ACPI op and operand2 is an integer.
+ *
+ * If (Lnotequal (op, val))
+ *
+ * This is equivalent to
+ *
+ * If (Lnot (Lequal (op, val)))
+ */
+void acpigen_write_if_lnotequal_op_int(uint8_t op, uint64_t val)
+{
+	acpigen_write_if();
+	acpigen_emit_byte(LNOT_OP);
+	acpigen_emit_byte(LEQUAL_OP);
+	acpigen_emit_byte(op);
+	acpigen_write_integer(val);
+}
+
 /*
  * Generates ACPI code for checking if operand is greater than the value, where,
  * operand is ACPI op and val is an integer.
@@ -1652,6 +1690,25 @@ void acpigen_write_if_lequal_namestr_int(const char *namestr, uint64_t val)
 	acpigen_write_integer(val);
 }
 
+/*
+ * Generates ACPI code for checking if operand1 and operand2 are not equal, where,
+ * operand1 is namestring and operand2 is an integer.
+ *
+ * If (Lnotequal ("namestr", val))
+ *
+ * * This is equivalent to
+ *
+ * If (Lnot (Lequal ("namestr", val)))
+ */
+void acpigen_write_if_lnotequal_namestr_int(const char *namestr, uint64_t val)
+{
+	acpigen_write_if();
+	acpigen_emit_byte(LNOT_OP);
+	acpigen_emit_byte(LEQUAL_OP);
+	acpigen_emit_namestring(namestr);
+	acpigen_write_integer(val);
+}
+
 /*
  * Generates ACPI code for checking if operand1 and operand2 are equal, where,
  * operand1 is namestring and operand2 is an integer.
diff --git a/src/include/acpi/acpigen.h b/src/include/acpi/acpigen.h
index 8129263475..56b4f780f7 100644
--- a/src/include/acpi/acpigen.h
+++ b/src/include/acpi/acpigen.h
@@ -506,10 +506,13 @@ void acpigen_write_debug_sprintf(const char *fmt, ...) __printf(1, 2);
 void acpigen_write_if(void);
 void acpigen_write_if_and(uint8_t arg1, uint8_t arg2);
 void acpigen_write_if_lequal_op_op(uint8_t op, uint8_t val);
+void acpigen_write_if_lnotequal_op_op(uint8_t op, uint8_t val);
 void acpigen_write_if_lgreater_op_op(uint8_t op1, uint8_t op2);
 void acpigen_write_if_lequal_op_int(uint8_t op, uint64_t val);
+void acpigen_write_if_lnotequal_op_int(uint8_t op, uint64_t val);
 void acpigen_write_if_lgreater_op_int(uint8_t op, uint64_t val);
 void acpigen_write_if_lequal_namestr_int(const char *namestr, uint64_t val);
+void acpigen_write_if_lnotequal_namestr_int(const char *namestr, uint64_t val);
 void acpigen_write_if_lgreater_namestr_int(const char *namestr, uint64_t val);
 __always_inline void acpigen_write_if_end(void)
 {

From 92d75be20b2b209f2da8448d1e2f0644cdba3a41 Mon Sep 17 00:00:00 2001
From: Felix Held <felix-coreboot@felixheld.de>
Date: Wed, 26 Feb 2025 19:05:59 +0100
Subject: [PATCH 0280/3886] src/acpigen: implement
 acpigen_write_create[_buffer]_bit_field

Implement functions to write the AML bytes corresponding to
CreateBitField for both OP buffers and named buffers.

TEST=Calling 'acpigen_write_create_buffer_bit_field' results in the AML
code sequence being written which decompiles to ASL as expected.

Change-Id: Ia5c06c2e8564b64de386871b2faf79c433e5a1da
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86630
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/acpi/acpigen.c         | 10 ++++++++++
 src/include/acpi/acpigen.h |  2 ++
 2 files changed, 12 insertions(+)

diff --git a/src/acpi/acpigen.c b/src/acpi/acpigen.c
index eaf95e018f..e577d8f96c 100644
--- a/src/acpi/acpigen.c
+++ b/src/acpi/acpigen.c
@@ -2461,6 +2461,11 @@ static void _create_field(uint8_t aml_op, uint8_t srcop, size_t byte_offset, con
 	acpigen_emit_namestring(name);
 }
 
+void acpigen_write_create_bit_field(uint8_t op, size_t bit_offset, const char *name)
+{
+	_create_field(CREATE_BIT_OP, op, bit_offset, name);
+}
+
 void acpigen_write_create_byte_field(uint8_t op, size_t byte_offset, const char *name)
 {
 	_create_field(CREATE_BYTE_OP, op, byte_offset, name);
@@ -2490,6 +2495,11 @@ static void _create_buffer_field(uint8_t aml_op, const char *src_buf, size_t byt
 	acpigen_emit_namestring(field);
 }
 
+void acpigen_write_create_buffer_bit_field(const char *src_buf, size_t bit_offset, const char *field)
+{
+	_create_buffer_field(CREATE_BIT_OP, src_buf, bit_offset, field);
+}
+
 void acpigen_write_create_buffer_byte_field(const char *src_buf, size_t byte_offset, const char *field)
 {
 	_create_buffer_field(CREATE_BYTE_OP, src_buf, byte_offset, field);
diff --git a/src/include/acpi/acpigen.h b/src/include/acpi/acpigen.h
index 56b4f780f7..a83be04048 100644
--- a/src/include/acpi/acpigen.h
+++ b/src/include/acpi/acpigen.h
@@ -535,10 +535,12 @@ void acpigen_write_pld(const struct acpi_pld *pld);
 void acpigen_write_ADR(uint64_t adr);
 struct soundwire_address;
 void acpigen_write_ADR_soundwire_device(const struct soundwire_address *address);
+void acpigen_write_create_bit_field(uint8_t op, size_t bit_offset, const char *name);
 void acpigen_write_create_byte_field(uint8_t op, size_t byte_offset, const char *name);
 void acpigen_write_create_word_field(uint8_t op, size_t byte_offset, const char *name);
 void acpigen_write_create_dword_field(uint8_t op, size_t byte_offset, const char *name);
 void acpigen_write_create_qword_field(uint8_t op, size_t byte_offset, const char *name);
+void acpigen_write_create_buffer_bit_field(const char *src_buf, size_t bit_offset, const char *field);
 void acpigen_write_create_buffer_byte_field(const char *src_buf, size_t byte_offset, const char *name);
 void acpigen_write_create_buffer_word_field(const char *src_buf, size_t byte_offset, const char *name);
 void acpigen_write_create_buffer_dword_field(const char *src_buf, size_t byte_offset, const char *name);

From 7437c16c27731b4e84a88d2daff294a4b197fef4 Mon Sep 17 00:00:00 2001
From: Felix Held <felix-coreboot@felixheld.de>
Date: Wed, 26 Feb 2025 19:53:03 +0100
Subject: [PATCH 0281/3886] src/acpigen: support 0-initialized buffer in
 acpigen_write_byte_buffer

Previously, the 'acpigen_write_byte_buffer' function required both the
byte buffer length and the initialization data byte array 'arr'. The
ACPI spec however allows buffer declarations with only the length, but
without an initialization data byte array. In this case the AML
interpreter will create a buffer of the given length with all bytes
initialized to 0x00. In order to not need another function, allow the
'arr' parameter for the pointer to the initialization data byte array to
be NULL and in that case don't write the optional buffer initialization
byte array.

TEST=Calling 'acpigen_write_byte_buffer' with 'NULL' as first parameter
results in the AML code sequence being written which decompiles to ASL
as expected.

Change-Id: Ie756489e02f994c38d38907a97fb215d30f4a636
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86631
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/acpi/acpigen.c | 8 ++++++--
 1 file changed, 6 insertions(+), 2 deletions(-)

diff --git a/src/acpi/acpigen.c b/src/acpi/acpigen.c
index e577d8f96c..081fa2b25d 100644
--- a/src/acpi/acpigen.c
+++ b/src/acpi/acpigen.c
@@ -1775,6 +1775,8 @@ void acpigen_write_to_integer_from_namestring(const char *source, uint8_t dst_op
 	acpigen_emit_byte(dst_op);
 }
 
+/* The initializer byte array 'arr' is optional. When 'arr' is NULL, the AML interpreter will
+   create a 0-initialized byte buffer */
 void acpigen_write_byte_buffer(uint8_t *arr, size_t size)
 {
 	size_t i;
@@ -1783,8 +1785,10 @@ void acpigen_write_byte_buffer(uint8_t *arr, size_t size)
 	acpigen_write_len_f();
 	acpigen_write_integer(size);
 
-	for (i = 0; i < size; i++)
-		acpigen_emit_byte(arr[i]);
+	if (arr != NULL) {
+		for (i = 0; i < size; i++)
+			acpigen_emit_byte(arr[i]);
+	}
 
 	acpigen_pop_len();
 }

From 50ba957b176d7b9da7ceb9e167460d8c26d33699 Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Wed, 6 Sep 2023 08:57:40 -0500
Subject: [PATCH 0282/3886] soc/amd/cezanne: Add ACPI opregion to root complex

Add an ACPI OperationRegion to access an SMN access index/data register
pair in the root complex. To access the PCI config space registers, the
ECAM MMCONF MMIO region is used which matches the UEFI reference
implementation.

TEST=The AML code sequence written by this decompiles to the expected
ASL code.

Change-Id: I4d00c86647e51e5cae621fe788f0a1b06471a443
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77682
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/soc/amd/cezanne/root_complex.c | 46 ++++++++++++++++++++++++++++++
 1 file changed, 46 insertions(+)

diff --git a/src/soc/amd/cezanne/root_complex.c b/src/soc/amd/cezanne/root_complex.c
index d9999b9163..15958dc0a8 100644
--- a/src/soc/amd/cezanne/root_complex.c
+++ b/src/soc/amd/cezanne/root_complex.c
@@ -59,6 +59,52 @@ static void root_complex_fill_ssdt(const struct device *device)
 {
 	if (CONFIG(SOC_AMD_COMMON_BLOCK_ACPI_DPTC))
 		acipgen_dptci();
+
+	/* Add ACPI device, opregion to host bridge needed for ACP driver.
+	 *
+	 * This is used by an ACPI method in the ACP's ACPI code to access different mailbox
+	 * interfaces in th hardware. Some ACP drivers will use that to both notify the PSP
+	 * that the DSP firmware has been loaded, so that the PSP can validate the firmware
+	 * and set the qualifier bit to enable running it, and to configure the ACP's clock
+	 * source.
+	 *
+	 * As this SMN access is not arbitrated and there may be other drivers or parts of
+	 * the firmware attempting to use the SMN access register pair, there is a risk of
+	 * conflict / incorrect data, but given the frequency and duration of accesses, the
+	 * risk is deemed to be quite low.
+	 *
+	 *	Scope (\_SB.PCI0)
+	 *	{
+	 *		Device (GNB)
+	 *		{
+	 *			Name (_ADR, 0x0000000000000000)
+	 *			Method (_STA, 0, NotSerialized)
+	 *			{
+	 *				Return (0x0F)
+	 *			}
+	 *		}
+	 *	}
+	 *	Scope (\_SB.PCI0.GNB)
+	 *	{
+	 *		OperationRegion(SMN, SystemMemory , 0xF80000B8, 0x8)
+	 *		Field(SMN, AnyAcc, NoLock, Preserve) {
+	 *			SMNA,   32,
+	 *			SMND,   32,
+	 *		}
+	 *	}
+	 */
+	acpi_device_write_pci_dev(device);
+	acpigen_write_scope(acpi_device_path(device));
+	struct opregion opreg = OPREGION("SMN", SYSTEMMEMORY,
+					 CONFIG_ECAM_MMCONF_BASE_ADDRESS + 0xb8, 0x8);
+	acpigen_write_opregion(&opreg);
+	static const struct fieldlist list[] = {
+		FIELDLIST_NAMESTR("SMNA", 32),
+		FIELDLIST_NAMESTR("SMND", 32),
+	};
+	acpigen_write_field(opreg.name, list, ARRAY_SIZE(list),
+			FIELD_ANYACC | FIELD_NOLOCK | FIELD_PRESERVE);
+	acpigen_write_scope_end();
 }
 
 static const char *gnb_acpi_name(const struct device *dev)

From a23c2dd2465b3e835336fe7c694f6a76283dbe68 Mon Sep 17 00:00:00 2001
From: Felix Held <felix-coreboot@felixheld.de>
Date: Sun, 16 Feb 2025 22:11:27 +0100
Subject: [PATCH 0283/3886] soc/amd/block/acp: add SSDT generation callback
 into SoC code

Some SoCs require adding SoC-specific methods to the ACP's SSDT entry.
In order to not add SoC-specific code to the common ACP code, add the
'acp_soc_write_ssdt_entry' callback into the SoC-specific code and guard
it via the 'SOC_AMD_COMMON_BLOCK_ACP_SOC_SPECIFIC_SSDT_ENTRY' Kconfig
symbol to neither need weak functions or stubs in every SoC code.

Change-Id: I0ca5272d28938c8b90b645884a0d8b306a77d473
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86465
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
---
 src/soc/amd/common/block/acp/Kconfig             | 6 ++++++
 src/soc/amd/common/block/acp/acp.c               | 2 ++
 src/soc/amd/common/block/include/amdblocks/acp.h | 3 +++
 3 files changed, 11 insertions(+)

diff --git a/src/soc/amd/common/block/acp/Kconfig b/src/soc/amd/common/block/acp/Kconfig
index bc2dddc1f9..a6ff48327b 100644
--- a/src/soc/amd/common/block/acp/Kconfig
+++ b/src/soc/amd/common/block/acp/Kconfig
@@ -11,3 +11,9 @@ config SOC_AMD_COMMON_BLOCK_ACP_GEN2
 	help
 	  Select this option to perform Audio Co-Processor(ACP) configuration.
 	  Used by the ACP in AMD mendocino (family 17h) and possibly newer CPUs.
+
+config SOC_AMD_COMMON_BLOCK_ACP_SOC_SPECIFIC_SSDT_ENTRY
+	bool
+	help
+	  Select this option to call into the SoC code when generating the SSDT
+	  entry for the Audio Co-Processor (ACP).
diff --git a/src/soc/amd/common/block/acp/acp.c b/src/soc/amd/common/block/acp/acp.c
index a43792eea7..4985980bf5 100644
--- a/src/soc/amd/common/block/acp/acp.c
+++ b/src/soc/amd/common/block/acp/acp.c
@@ -39,6 +39,8 @@ static void acp_fill_ssdt(const struct device *dev)
 {
 	acpi_device_write_pci_dev(dev);
 	acp_fill_wov_method(dev);
+	if (CONFIG(SOC_AMD_COMMON_BLOCK_ACP_SOC_SPECIFIC_SSDT_ENTRY))
+		acp_soc_write_ssdt_entry(dev);
 }
 
 struct device_operations amd_acp_ops = {
diff --git a/src/soc/amd/common/block/include/amdblocks/acp.h b/src/soc/amd/common/block/include/amdblocks/acp.h
index 04112ca272..3ec38c93d5 100644
--- a/src/soc/amd/common/block/include/amdblocks/acp.h
+++ b/src/soc/amd/common/block/include/amdblocks/acp.h
@@ -3,6 +3,7 @@
 #ifndef AMD_COMMON_ACP_H
 #define AMD_COMMON_ACP_H
 
+#include <device/device.h>
 #include <types.h>
 
 struct acp_config {
@@ -44,4 +45,6 @@ struct acp_config {
 	bool dmic_present;
 };
 
+void acp_soc_write_ssdt_entry(const struct device *dev);
+
 #endif /* AMD_COMMON_ACP_H */

From f60d630727feb799d072d8756cc30789002cbb99 Mon Sep 17 00:00:00 2001
From: Felix Held <felix-coreboot@felixheld.de>
Date: Sun, 16 Feb 2025 22:13:14 +0100
Subject: [PATCH 0284/3886] soc/amd/cezanne/acpi: Add ACP SMN access interface

Add two ACPI methods to access a PSP mailbox interface via an SMN
register pair in the host bridge.

TEST=The AML code sequence written by this decompiles to the expected
ASL code.

Change-Id: I282f1fa2898f76659700450ee1f4b11f79d2d030
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77703
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/soc/amd/cezanne/Kconfig |  1 +
 src/soc/amd/cezanne/acpi.c  | 41 +++++++++++++++++++++++++++++++++++++
 2 files changed, 42 insertions(+)

diff --git a/src/soc/amd/cezanne/Kconfig b/src/soc/amd/cezanne/Kconfig
index 7b97ce731a..d0a2c5ec74 100644
--- a/src/soc/amd/cezanne/Kconfig
+++ b/src/soc/amd/cezanne/Kconfig
@@ -27,6 +27,7 @@ config SOC_AMD_CEZANNE
 	select RTC
 	select SOC_AMD_COMMON
 	select SOC_AMD_COMMON_BLOCK_ACP_GEN1
+	select SOC_AMD_COMMON_BLOCK_ACP_SOC_SPECIFIC_SSDT_ENTRY
 	select SOC_AMD_COMMON_BLOCK_ACPI
 	select SOC_AMD_COMMON_BLOCK_ACPIMMIO
 	select SOC_AMD_COMMON_BLOCK_ACPIMMIO_PM_IO_ACCESS
diff --git a/src/soc/amd/cezanne/acpi.c b/src/soc/amd/cezanne/acpi.c
index 4481c46ae8..140c1af9b4 100644
--- a/src/soc/amd/cezanne/acpi.c
+++ b/src/soc/amd/cezanne/acpi.c
@@ -4,6 +4,7 @@
 
 #include <acpi/acpi.h>
 #include <acpi/acpigen.h>
+#include <amdblocks/acp.h>
 #include <amdblocks/acpi.h>
 #include <amdblocks/cppc.h>
 #include <amdblocks/cpu.h>
@@ -91,3 +92,43 @@ const acpi_cstate_t *get_cstate_config_data(size_t *size)
 	*size = ARRAY_SIZE(cstate_cfg_table);
 	return cstate_cfg_table;
 }
+
+static void acp_soc_write_smn_access_methods(void)
+{
+	acpigen_write_method_serialized("SMNR", 1);
+	acpigen_write_store_op_to_namestr(ARG0_OP, "\\_SB.PCI0.GNB.SMNA");
+	acpigen_write_return_namestr("\\_SB.PCI0.GNB.SMND");
+	acpigen_write_method_end();
+
+	acpigen_write_method_serialized("SMNW", 2);
+	acpigen_write_store_op_to_namestr(ARG0_OP, "\\_SB.PCI0.GNB.SMNA");
+	acpigen_write_store_op_to_namestr(ARG1_OP, "\\_SB.PCI0.GNB.SMND");
+	acpigen_write_method_end();
+}
+
+void acp_soc_write_ssdt_entry(const struct device *dev)
+{
+	/*
+	 * SMN interface using the SMN OperationRegion on the host bridge
+	 *
+	 * Scope (\_SB.PCI0.GP41.ACPD)
+	 * {
+	 *	Method (SMNR, 1, Serialized)
+	 *	{
+	 *		Store (Arg0, \_SB.PCI0.GNB.SMNA)
+	 *		Return (\_SB.PCI0.GNB.SMND)
+	 *	}
+	 *
+	 *	Method (SMNW, 2, Serialized)
+	 *	{
+	 *		Store (Arg0, \_SB.PCI0.GNB.SMNA)
+	 *		Store (Arg1, \_SB.PCI0.GNB.SMND)
+	 *	}
+	 * }
+	 */
+	acpigen_write_scope(acpi_device_path(dev));
+
+	acp_soc_write_smn_access_methods();
+
+	acpigen_write_scope_end();
+}

From 2727adbeeab36269c083fa7dd653d52cd176344e Mon Sep 17 00:00:00 2001
From: Felix Held <felix-coreboot@felixheld.de>
Date: Sun, 16 Feb 2025 22:30:43 +0100
Subject: [PATCH 0285/3886] soc/amd/cezanne/acpi: Add ACP MSG0 method

Add the MSG0 method to the ACP's SSDT entry, so that the ACP driver can
talk to a two different mailbox interfaces via this ACPI MSG0 method
interface. This is used by some drivers to configure the ACP's clock
source and to notify the PSP that the audio DSP firmware has been loaded
so that the PSP can validate the firmware and set the qualifier bit to
enable running it.

TEST=The AML code sequence written by this decompiles to the expected
ASL code and the driver is able to initialize the ACP correctly by
calling the MSG0 method twice with different parameters.

Change-Id: I34f641fbfe40b5df7f0ff2fc173510c5cf2a7f61
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86466
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
---
 src/soc/amd/cezanne/acpi.c | 185 ++++++++++++++++++++++++++++++++++++-
 1 file changed, 184 insertions(+), 1 deletion(-)

diff --git a/src/soc/amd/cezanne/acpi.c b/src/soc/amd/cezanne/acpi.c
index 140c1af9b4..b54b88b2e8 100644
--- a/src/soc/amd/cezanne/acpi.c
+++ b/src/soc/amd/cezanne/acpi.c
@@ -106,10 +106,145 @@ static void acp_soc_write_smn_access_methods(void)
 	acpigen_write_method_end();
 }
 
+/* write value of ACPI variable into SMN register */
+static void acp_soc_write_smn_register_write(uint8_t op, uint32_t smn_address)
+{
+	acpigen_emit_namestring("^SMNW");
+	acpigen_write_integer(smn_address);
+	acpigen_emit_byte(op);
+}
+
+/* read SMN register and store value into ACPI variable */
+static void acp_soc_write_smn_register_read(uint32_t smn_address, uint8_t op)
+{
+	acpigen_write_store();
+	acpigen_emit_namestring("^SMNR");
+	acpigen_write_integer(smn_address);
+	acpigen_emit_byte(op);
+}
+
+static void acp_soc_write_mailbox_access(void)
+{
+	acp_soc_write_smn_register_write(ARG0_OP, 0x00058A74);
+	acp_soc_write_smn_register_write(ARG1_OP, 0x00058A54);
+	acp_soc_write_smn_register_write(ARG2_OP, 0x00058A14);
+	acp_soc_write_smn_register_read(0x00058A74, LOCAL0_OP);
+
+	/* While (LEqual (Local0, 0)) */
+	acpigen_emit_byte(WHILE_OP);
+	acpigen_write_len_f();
+	acpigen_emit_byte(LEQUAL_OP);
+	acpigen_emit_byte(LOCAL0_OP);
+	acpigen_emit_byte(ZERO_OP);
+
+	acp_soc_write_smn_register_read(0x00058A74, LOCAL0_OP);
+
+	acpigen_pop_len(); /* While */
+
+	acp_soc_write_smn_register_read(0x00058A54, LOCAL1_OP);
+
+	acpigen_write_return_op(LOCAL1_OP);
+}
+
+static void acp_soc_write_psp_mbox_buffer_field(void)
+{
+	acpigen_write_name("MBOX");
+	acpigen_write_byte_buffer(NULL, 4);
+	acpigen_write_create_buffer_word_field("MBOX", 0, "STAT");
+	acpigen_write_create_buffer_byte_field("MBOX", 2, "CMDI");
+	acpigen_write_create_buffer_bit_field("MBOX", 31, "REDY");
+}
+
+static void acp_soc_write_psp_read_mbox_from_hw(void)
+{
+	acp_soc_write_smn_register_read(0x03810570, LOCAL0_OP);
+	acpigen_write_store_op_to_namestr(LOCAL0_OP, "MBOX");
+}
+
+static void acp_soc_write_psp_write_mbox_to_hw(void)
+{
+	acpigen_write_store_namestr_to_op("MBOX", LOCAL0_OP);
+	acp_soc_write_smn_register_write(LOCAL0_OP, 0x03810570);
+}
+
+static void acp_soc_write_psp_mailbox_access(void)
+{
+
+	acp_soc_write_psp_mbox_buffer_field();
+
+	acp_soc_write_psp_read_mbox_from_hw();
+
+	/* While (LOr (LNotEqual (REDY, 0x1), LNotEqual (CMDI, 0x00))) */
+	acpigen_emit_byte(WHILE_OP);
+	acpigen_write_len_f();
+	acpigen_emit_byte(LOR_OP);
+	acpigen_emit_byte(LNOT_OP);
+	acpigen_emit_byte(LEQUAL_OP);
+	acpigen_emit_namestring("REDY");
+	acpigen_write_integer(1);
+	acpigen_emit_byte(LNOT_OP);
+	acpigen_emit_byte(LEQUAL_OP);
+	acpigen_emit_namestring("CMDI");
+	acpigen_write_integer(0);
+
+	acp_soc_write_psp_read_mbox_from_hw();
+
+	acpigen_pop_len(); /* While */
+
+	acpigen_write_store_int_to_op(0, LOCAL0_OP);
+	acpigen_write_store_op_to_namestr(LOCAL0_OP, "MBOX");
+	acpigen_write_store_int_to_namestr(0x33, "CMDI");
+
+	acp_soc_write_psp_write_mbox_to_hw();
+
+	acpigen_write_sleep(1);
+
+	acp_soc_write_psp_read_mbox_from_hw();
+
+	/* While (LNotEqual (CMDI, 0x00)) */
+	acpigen_emit_byte(WHILE_OP);
+	acpigen_write_len_f();
+	acpigen_emit_byte(LNOT_OP);
+	acpigen_emit_byte(LEQUAL_OP);
+	acpigen_emit_namestring("CMDI");
+	acpigen_write_integer(0);
+
+	acp_soc_write_psp_read_mbox_from_hw();
+
+	acpigen_pop_len(); /* While */
+
+	acpigen_write_return_op(LOCAL0_OP);
+}
+
+static void acp_soc_write_msg0_method(void)
+{
+	acpigen_write_method_serialized("MSG0", 3);
+
+	/* If (ARG2 != 0x9) */
+	acpigen_write_if_lnotequal_op_int(ARG2_OP, 0x9);
+
+	acp_soc_write_mailbox_access();
+
+	acpigen_write_else();
+
+	acp_soc_write_psp_mailbox_access();
+
+	acpigen_write_if_end();
+
+	acpigen_write_method_end(); /* MSG0 */
+}
+
 void acp_soc_write_ssdt_entry(const struct device *dev)
 {
 	/*
-	 * SMN interface using the SMN OperationRegion on the host bridge
+	 * SMN and mailbox interface using the SMN OperationRegion on the host bridge
+	 *
+	 * Provide both SMN read/write methods for direct SMN register access and the MSG0
+	 * method which is used by some ACP drivers to access two different mailbox interfaces
+	 * in the hardware. One mailbox interface is used to configure the ACP's clock source,
+	 * the other one is used to notify the PSP that the DSP firmware has been loaded, so
+	 * that the PSP can validate the firmware and set the qualifier bit to enable running
+	 * it.
 	 *
 	 * Scope (\_SB.PCI0.GP41.ACPD)
 	 * {
@@ -124,11 +259,59 @@ void acp_soc_write_ssdt_entry(const struct device *dev)
 	 *		Store (Arg0, \_SB.PCI0.GNB.SMNA)
 	 *		Store (Arg1, \_SB.PCI0.GNB.SMND)
 	 *	}
+	 *
+	 *	Method (MSG0, 3, Serialized)
+	 *	{
+	 *		If (LNotEqual (Arg2, 0x09))
+	 *		{
+	 *			^SMNW (0x00058A74, Arg0)
+	 *			^SMNW (0x00058A54, Arg1)
+	 *			^SMNW (0x00058A14, Arg2)
+	 *			Store (^SMNR (0x00058A74), Local0)
+	 *			While (LEqual (Local0, Zero))
+	 *			{
+	 *				Store (^SMNR (0x00058A74), Local0)
+	 *			}
+	 *			Store (^SMNR (0x00058A54), Local1)
+	 *			Return (Local1)
+	 *		}
+	 *		Else
+	 *		{
+	 *			Name (MBOX, Buffer (0x04){})
+	 *			CreateWordField (MBOX, Zero, STAT)
+	 *			CreateByteField (MBOX, 0x02, CMDI)
+	 *			CreateBitField (MBOX, 0x1F, REDY)
+	 *			Store (^SMNR (0x03810570), Local0)
+	 *			Store (Local0, MBOX)
+	 *			While (LOr (LNotEqual (REDY, One), LNotEqual (CMDI, Zero)))
+	 *			{
+	 *				Store (^SMNR (0x03810570), Local0)
+	 *				Store (Local0, MBOX)
+	 *			}
+	 *			Store (Zero, Local0)
+	 *			Store (Local0, MBOX)
+	 *			Store (0x33, CMDI)
+	 *			Store (MBOX, Local0)
+	 *			^SMNW (0x03810570, Local0)
+	 *			Sleep (One)
+	 *			Store (^SMNR (0x03810570), Local0)
+	 *			Store (Local0, MBOX)
+	 *			While (LNotEqual (CMDI, Zero))
+	 *			{
+	 *				Store (^SMNR (0x03810570), Local0)
+	 *				Store (Local0, MBOX)
+	 *			}
+	 *			Return (Local0)
+	 *		}
+	 *	}
 	 * }
 	 */
+
 	acpigen_write_scope(acpi_device_path(dev));
 
 	acp_soc_write_smn_access_methods();
 
+	acp_soc_write_msg0_method();
+
 	acpigen_write_scope_end();
 }

From 90cde7f66fc21f9778a93ee652c9501ab4b351dc Mon Sep 17 00:00:00 2001
From: Maximilian Brune <maximilian.brune@9elements.com>
Date: Tue, 4 Mar 2025 22:40:32 +0100
Subject: [PATCH 0286/3886] soc/amd/glinda/xhci.c: Fix gpe_configure_sci
 argument

Change-Id: Ia2964d73483a4308f1fb9f194b60a3dbbee5c713
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86721
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
---
 src/soc/amd/glinda/xhci.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/soc/amd/glinda/xhci.c b/src/soc/amd/glinda/xhci.c
index 70a0d84864..b67bb5a060 100644
--- a/src/soc/amd/glinda/xhci.c
+++ b/src/soc/amd/glinda/xhci.c
@@ -69,7 +69,7 @@ enum cb_err pci_xhci_get_wake_gpe(const struct device *dev, int *gpe)
 
 static void configure_xhci_sci(void *unused)
 {
-	gpe_configure_sci(xhci_sci_sources, ARRAY_SIZE(xhci_sci_sources) - 1);
+	gpe_configure_sci(xhci_sci_sources, ARRAY_SIZE(xhci_sci_sources));
 }
 
 BOOT_STATE_INIT_ENTRY(BS_POST_DEVICE, BS_ON_ENTRY, configure_xhci_sci, NULL);

From 3cb5308d074e4af74f97103ea099cdd2824d7908 Mon Sep 17 00:00:00 2001
From: Yidi Lin <yidilin@chromium.org>
Date: Wed, 5 Mar 2025 03:11:10 +0000
Subject: [PATCH 0287/3886] Update arm-trusted-firmware submodule to upstream
 master

Updating from commit id 0c370e2d592b:
2025-02-04 18:14:07 +0100 - (Merge "feat(mt8196): add SMMU driver for PM" into integration)

to commit id e5a1f4abeec3:
2025-03-03 16:21:54 +0100 - (Merge "feat(mt8196): fix MT8196 gpio driver" into integration)

This brings in 215 new commits.

Change-Id: I15af95b97566ee3660f3d4a650920fd60ec81d34
Signed-off-by: Yidi Lin <yidilin@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86722
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 3rdparty/arm-trusted-firmware | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/3rdparty/arm-trusted-firmware b/3rdparty/arm-trusted-firmware
index 0c370e2d59..e5a1f4abee 160000
--- a/3rdparty/arm-trusted-firmware
+++ b/3rdparty/arm-trusted-firmware
@@ -1 +1 @@
-Subproject commit 0c370e2d592b96554ac6d5dca4242733ab14300f
+Subproject commit e5a1f4abeec3311e65412a2905873a110a9abdd1

From 39341b494a76bcfd721f1b7ee9ebfb29a0420867 Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Wed, 5 Mar 2025 11:44:42 +0000
Subject: [PATCH 0288/3886] mb/starlabs/starbook/mtl: Add generic Graphics
 driver config

Change-Id: I68d44902a17695538dc4f1f2c38576bb02d8be8a
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86729
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
---
 src/mainboard/starlabs/starbook/Kconfig       |  1 +
 .../starbook/variants/mtl/devicetree.cb       | 43 +++++++++++++++----
 2 files changed, 35 insertions(+), 9 deletions(-)

diff --git a/src/mainboard/starlabs/starbook/Kconfig b/src/mainboard/starlabs/starbook/Kconfig
index e4e4c63c9f..b8b4da4621 100644
--- a/src/mainboard/starlabs/starbook/Kconfig
+++ b/src/mainboard/starlabs/starbook/Kconfig
@@ -102,6 +102,7 @@ config BOARD_STARLABS_STARBOOK_RPL
 config BOARD_STARLABS_STARBOOK_MTL
 	select BOARD_ROMSIZE_KB_32768
 	select BOARD_STARLABS_STARBOOK_SERIES
+	select DRIVERS_GFX_GENERIC
 	select DRIVERS_INTEL_PMC
 	select EC_STARLABS_CHARGING_SPEED
 	select EC_STARLABS_KBL_LEVELS
diff --git a/src/mainboard/starlabs/starbook/variants/mtl/devicetree.cb b/src/mainboard/starlabs/starbook/variants/mtl/devicetree.cb
index d9d8deea38..7b9be13795 100644
--- a/src/mainboard/starlabs/starbook/variants/mtl/devicetree.cb
+++ b/src/mainboard/starlabs/starbook/variants/mtl/devicetree.cb
@@ -21,7 +21,28 @@ chip soc/intel/meteorlake
 	# Device Tree
 	device domain 0 on
 		device ref igpu		on
-			register "gfx"				= "GMA_DEFAULT_PANEL(0)"
+			chip drivers/gfx/generic
+				register "device_count"		= "6"
+				# [DDIA] eDP
+				register "device[0].name"	= ""LCD0""
+				register "device[0].type"	= "panel"
+				# [DDIB] HDMI
+				register "device[1].name"	= ""DD01""
+				# [TCP0] Type-C
+				register "device[2].name"	= ""DD02""
+				register "device[2].use_pld"	= "true"
+				register "device[2].pld"	= "ACPI_PLD_TYPE_C(LEFT, CENTER, ACPI_PLD_GROUP(0, 0))"
+				# [TCP1] Type-C
+				register "device[3].name"	= ""DD03""
+				register "device[3].use_pld"	= "true"
+				register "device[3].pld"	= "ACPI_PLD_TYPE_C(LEFT, CENTER, ACPI_PLD_GROUP(0, 1))"
+				# [TCP2] N/A
+				register "device[4].name"	= ""DD04""
+				# [TCP3] N/A
+				register "device[5].name"	= ""DD05""
+				device generic 0 on end
+			end
+
 			register "ddi_port_A_config"		= "1"
 			register "ddi_ports_config" = "{
 				[DDI_PORT_A]			= DDI_ENABLE_HPD,
@@ -34,15 +55,17 @@ chip soc/intel/meteorlake
 			chip drivers/usb/acpi
 				device ref tcss_root_hub on
 					chip drivers/usb/acpi
-						register "desc"		= ""Back USB Type-C""
-						register "type"		= "UPC_TYPE_C_USB2_SS_SWITCH"
-						register "group"	= "ACPI_PLD_GROUP(0, 0)"
+						register "desc"			= ""Back USB Type-C""
+						register "type"			= "UPC_TYPE_C_USB2_SS_SWITCH"
+						register "use_custom_pld"	= "true"
+						register "custom_pld"		= "ACPI_PLD_TYPE_C(LEFT, CENTER, ACPI_PLD_GROUP(0, 0))"
 						device ref tcss_usb3_port0 on end
 					end
 					chip drivers/usb/acpi
-						register "desc"		= ""Front USB Type-C""
-						register "type"		= "UPC_TYPE_C_USB2_SS_SWITCH"
-						register "group"	= "ACPI_PLD_GROUP(0, 1)"
+						register "desc"			= ""Front USB Type-C""
+						register "type"			= "UPC_TYPE_C_USB2_SS_SWITCH"
+						register "use_custom_pld"	= "true"
+						register "custom_pld"		= "ACPI_PLD_TYPE_C(LEFT, CENTER, ACPI_PLD_GROUP(0, 1))"
 						device ref tcss_usb3_port1 on end
 					end
 				end
@@ -80,13 +103,15 @@ chip soc/intel/meteorlake
 					chip drivers/usb/acpi
 						register "desc"		= ""Back USB Type-C""
 						register "type"		= "UPC_TYPE_C_USB2_SS_SWITCH"
-						register "group"	= "ACPI_PLD_GROUP(0, 0)"
+						register "use_custom_pld" = "true"
+						register "custom_pld"	= "ACPI_PLD_TYPE_C(LEFT, CENTER, ACPI_PLD_GROUP(0, 0))"
 						device ref usb2_port1 on end
 					end
 					chip drivers/usb/acpi
 						register "desc"		= ""Front USB Type-C""
 						register "type"		= "UPC_TYPE_C_USB2_SS_SWITCH"
-						register "group"	= "ACPI_PLD_GROUP(0, 1)"
+						register "use_custom_pld"	= "true"
+						register "custom_pld"	= "ACPI_PLD_TYPE_C(LEFT, CENTER, ACPI_PLD_GROUP(0, 1))"
 						device ref usb2_port3 on end
 					end
 					chip drivers/usb/acpi

From 39244ba6760305a4574599aba89caa67854ae043 Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Wed, 5 Mar 2025 11:39:47 +0000
Subject: [PATCH 0289/3886] mb/starlabs/*: Set tcc_offset instead of
 pch_thermal_trip

Some boards configure pch_thermal_trip based on the performance
profile, and some set tcc_offset.

tcc_offset makes more sense here, so change all the boards to be
the same.

Change-Id: Id55b5d971c895baa1ba97137351fbd0aea3317d8
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86728
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/starlabs/byte_adl/variants/mk_ii/devtree.c | 9 +++------
 src/mainboard/starlabs/starbook/variants/adl/devtree.c   | 9 +++------
 src/mainboard/starlabs/starbook/variants/adl_n/devtree.c | 9 +++------
 src/mainboard/starlabs/starbook/variants/mtl/devtree.c   | 9 +++------
 src/mainboard/starlabs/starbook/variants/rpl/devtree.c   | 9 +++------
 .../starlabs/starfighter/variants/rpl/devtree.c          | 9 +++------
 .../starlabs/starlite_adl/variants/mk_v/devtree.c        | 9 +++------
 7 files changed, 21 insertions(+), 42 deletions(-)

diff --git a/src/mainboard/starlabs/byte_adl/variants/mk_ii/devtree.c b/src/mainboard/starlabs/byte_adl/variants/mk_ii/devtree.c
index d762e75457..55ae2b39ac 100644
--- a/src/mainboard/starlabs/byte_adl/variants/mk_ii/devtree.c
+++ b/src/mainboard/starlabs/byte_adl/variants/mk_ii/devtree.c
@@ -13,9 +13,6 @@ void devtree_update(void)
 {
 	config_t *cfg = config_of_soc();
 
-	struct soc_intel_common_config *common_config;
-	common_config = chip_get_common_soc_structure();
-
 	struct soc_power_limits_config *soc_conf_4core =
 		&cfg->power_limits_config[ADL_N_041_6W_CORE];
 
@@ -34,15 +31,15 @@ void devtree_update(void)
 	switch (get_power_profile(PP_POWER_SAVER)) {
 	case PP_POWER_SAVER:
 		performance_scale			-= 50;
-		common_config->pch_thermal_trip		= 30;
+		cfg->tcc_offset				= 30;
 		break;
 	case PP_BALANCED:
 		performance_scale			-= 25;
-		common_config->pch_thermal_trip		= 25;
+		cfg->tcc_offset				= 25;
 		break;
 	case PP_PERFORMANCE:
 		/* Use the Intel defaults */
-		common_config->pch_thermal_trip		= 20;
+		cfg->tcc_offset				= 20;
 		break;
 	}
 
diff --git a/src/mainboard/starlabs/starbook/variants/adl/devtree.c b/src/mainboard/starlabs/starbook/variants/adl/devtree.c
index c563d2d1f7..0f40aaf1b1 100644
--- a/src/mainboard/starlabs/starbook/variants/adl/devtree.c
+++ b/src/mainboard/starlabs/starbook/variants/adl/devtree.c
@@ -13,9 +13,6 @@ void devtree_update(void)
 {
 	config_t *cfg = config_of_soc();
 
-	struct soc_intel_common_config *common_config;
-	common_config = chip_get_common_soc_structure();
-
 	struct soc_power_limits_config *soc_conf_10core =
 		&cfg->power_limits_config[ADL_P_282_442_482_28W_CORE];
 
@@ -38,15 +35,15 @@ void devtree_update(void)
 	switch (get_power_profile(PP_POWER_SAVER)) {
 	case PP_POWER_SAVER:
 		performance_scale			-= 50;
-		common_config->pch_thermal_trip		= 20;
+		cfg->tcc_offset				= 20;
 		break;
 	case PP_BALANCED:
 		performance_scale			-= 25;
-		common_config->pch_thermal_trip		= 15;
+		cfg->tcc_offset				= 15;
 		break;
 	case PP_PERFORMANCE:
 		/* Use the Intel defaults */
-		common_config->pch_thermal_trip		= 10;
+		cfg->tcc_offset				= 10;
 		break;
 	}
 
diff --git a/src/mainboard/starlabs/starbook/variants/adl_n/devtree.c b/src/mainboard/starlabs/starbook/variants/adl_n/devtree.c
index fe8716e226..a4cc362853 100644
--- a/src/mainboard/starlabs/starbook/variants/adl_n/devtree.c
+++ b/src/mainboard/starlabs/starbook/variants/adl_n/devtree.c
@@ -13,9 +13,6 @@ void devtree_update(void)
 {
 	config_t *cfg = config_of_soc();
 
-	struct soc_intel_common_config *common_config;
-	common_config = chip_get_common_soc_structure();
-
 	struct soc_power_limits_config *soc_conf_4core =
 		&cfg->power_limits_config[ADL_N_041_6W_CORE];
 
@@ -33,15 +30,15 @@ void devtree_update(void)
 	switch (get_power_profile(PP_POWER_SAVER)) {
 	case PP_POWER_SAVER:
 		performance_scale			-= 50;
-		common_config->pch_thermal_trip		= 20;
+		cfg->tcc_offset				= 20;
 		break;
 	case PP_BALANCED:
 		performance_scale			-= 25;
-		common_config->pch_thermal_trip		= 15;
+		cfg->tcc_offset				= 15;
 		break;
 	case PP_PERFORMANCE:
 		/* Use the Intel defaults */
-		common_config->pch_thermal_trip		= 10;
+		cfg->tcc_offset				= 10;
 		break;
 	}
 
diff --git a/src/mainboard/starlabs/starbook/variants/mtl/devtree.c b/src/mainboard/starlabs/starbook/variants/mtl/devtree.c
index a8944797df..1d0176d514 100644
--- a/src/mainboard/starlabs/starbook/variants/mtl/devtree.c
+++ b/src/mainboard/starlabs/starbook/variants/mtl/devtree.c
@@ -13,9 +13,6 @@ void devtree_update(void)
 {
 	config_t *cfg = config_of_soc();
 
-	struct soc_intel_common_config *common_config;
-	common_config = chip_get_common_soc_structure();
-
 	struct soc_power_limits_config *soc_conf_20core =
 		&cfg->power_limits_config[MTL_P_682_482_CORE];
 
@@ -33,15 +30,15 @@ void devtree_update(void)
 	switch (get_power_profile(PP_POWER_SAVER)) {
 	case PP_POWER_SAVER:
 		performance_scale			-= 50;
-		common_config->pch_thermal_trip		= 30;
+		cfg->tcc_offset				= 30;
 		break;
 	case PP_BALANCED:
 		performance_scale			-= 25;
-		common_config->pch_thermal_trip		= 25;
+		cfg->tcc_offset				= 25;
 		break;
 	case PP_PERFORMANCE:
 		/* Use the Intel defaults */
-		common_config->pch_thermal_trip		= 20;
+		cfg->tcc_offset				= 20;
 		break;
 	}
 
diff --git a/src/mainboard/starlabs/starbook/variants/rpl/devtree.c b/src/mainboard/starlabs/starbook/variants/rpl/devtree.c
index a8ebcde87c..5c2fc238dd 100644
--- a/src/mainboard/starlabs/starbook/variants/rpl/devtree.c
+++ b/src/mainboard/starlabs/starbook/variants/rpl/devtree.c
@@ -13,9 +13,6 @@ void devtree_update(void)
 {
 	config_t *cfg = config_of_soc();
 
-	struct soc_intel_common_config *common_config;
-	common_config = chip_get_common_soc_structure();
-
 	struct soc_power_limits_config *soc_conf_6core =
 		&cfg->power_limits_config[RPL_P_282_242_142_15W_CORE];
 
@@ -40,15 +37,15 @@ void devtree_update(void)
 	switch (get_power_profile(PP_POWER_SAVER)) {
 	case PP_POWER_SAVER:
 		performance_scale			-= 50;
-		common_config->pch_thermal_trip		= 30;
+		cfg->tcc_offset				= 30;
 		break;
 	case PP_BALANCED:
 		performance_scale			-= 25;
-		common_config->pch_thermal_trip		= 25;
+		cfg->tcc_offset				= 25;
 		break;
 	case PP_PERFORMANCE:
 		/* Use the Intel defaults */
-		common_config->pch_thermal_trip		= 20;
+		cfg->tcc_offset				= 20;
 		break;
 	}
 
diff --git a/src/mainboard/starlabs/starfighter/variants/rpl/devtree.c b/src/mainboard/starlabs/starfighter/variants/rpl/devtree.c
index c9b576a385..2bea4e81b3 100644
--- a/src/mainboard/starlabs/starfighter/variants/rpl/devtree.c
+++ b/src/mainboard/starlabs/starfighter/variants/rpl/devtree.c
@@ -13,9 +13,6 @@ void devtree_update(void)
 {
 	config_t *cfg = config_of_soc();
 
-	struct soc_intel_common_config *common_config;
-	common_config = chip_get_common_soc_structure();
-
 	struct soc_power_limits_config *soc_conf_6core =
 		&cfg->power_limits_config[RPL_P_282_242_142_15W_CORE];
 
@@ -41,15 +38,15 @@ void devtree_update(void)
 	switch (get_power_profile(PP_POWER_SAVER)) {
 	case PP_POWER_SAVER:
 		performance_scale			-= 50;
-		common_config->pch_thermal_trip		= 30;
+		cfg->tcc_offset				= 30;
 		break;
 	case PP_BALANCED:
 		performance_scale			-= 25;
-		common_config->pch_thermal_trip		= 25;
+		cfg->tcc_offset				= 25;
 		break;
 	case PP_PERFORMANCE:
 		/* Use the Intel defaults */
-		common_config->pch_thermal_trip		= 20;
+		cfg->tcc_offset				= 20;
 		break;
 	}
 
diff --git a/src/mainboard/starlabs/starlite_adl/variants/mk_v/devtree.c b/src/mainboard/starlabs/starlite_adl/variants/mk_v/devtree.c
index c2a95f7ac7..6805e32d05 100644
--- a/src/mainboard/starlabs/starlite_adl/variants/mk_v/devtree.c
+++ b/src/mainboard/starlabs/starlite_adl/variants/mk_v/devtree.c
@@ -13,9 +13,6 @@ void devtree_update(void)
 {
 	config_t *cfg = config_of_soc();
 
-	struct soc_intel_common_config *common_config;
-	common_config = chip_get_common_soc_structure();
-
 	struct soc_power_limits_config *soc_conf_4core =
 		&cfg->power_limits_config[ADL_N_041_6W_CORE];
 
@@ -36,15 +33,15 @@ void devtree_update(void)
 	switch (get_power_profile(PP_POWER_SAVER)) {
 	case PP_POWER_SAVER:
 		performance_scale			-= 50;
-		common_config->pch_thermal_trip		= 30;
+		cfg->tcc_offset				= 30;
 		break;
 	case PP_BALANCED:
 		performance_scale			-= 25;
-		common_config->pch_thermal_trip		= 25;
+		cfg->tcc_offset				= 25;
 		break;
 	case PP_PERFORMANCE:
 		/* Use the Intel defaults */
-		common_config->pch_thermal_trip		= 20;
+		cfg->tcc_offset				= 20;
 		break;
 	}
 

From 3a8835f0e87784344a6219a3eea1868879c0dda0 Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Wed, 5 Mar 2025 15:20:35 +0000
Subject: [PATCH 0290/3886] mb/starlabs/*: Unify tcc_offset settings

Add a simply macro to make the value set for tcc_offset easier to
read.

Then, unify the settings across all boards:
* 70, 80 and 90 degrees for fanless boards
* 80, 90 and 100 degrees for fanned boards

Change-Id: I5c0323aea0d9d3b09e60f88c3a95c821ab1d3b7d
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86740
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/starlabs/byte_adl/variants/mk_ii/devtree.c | 9 ++++++---
 src/mainboard/starlabs/starbook/variants/adl/devtree.c   | 9 ++++++---
 src/mainboard/starlabs/starbook/variants/adl_n/devtree.c | 9 ++++++---
 src/mainboard/starlabs/starbook/variants/cml/devtree.c   | 9 ++++++---
 src/mainboard/starlabs/starbook/variants/kbl/devtree.c   | 9 ++++++---
 src/mainboard/starlabs/starbook/variants/mtl/devtree.c   | 9 ++++++---
 src/mainboard/starlabs/starbook/variants/rpl/devtree.c   | 9 ++++++---
 src/mainboard/starlabs/starbook/variants/tgl/devtree.c   | 9 ++++++---
 .../starlabs/starfighter/variants/rpl/devtree.c          | 9 ++++++---
 .../starlabs/starlite_adl/variants/mk_v/devtree.c        | 9 ++++++---
 10 files changed, 60 insertions(+), 30 deletions(-)

diff --git a/src/mainboard/starlabs/byte_adl/variants/mk_ii/devtree.c b/src/mainboard/starlabs/byte_adl/variants/mk_ii/devtree.c
index 55ae2b39ac..f10cfed870 100644
--- a/src/mainboard/starlabs/byte_adl/variants/mk_ii/devtree.c
+++ b/src/mainboard/starlabs/byte_adl/variants/mk_ii/devtree.c
@@ -9,6 +9,9 @@
 #include <types.h>
 #include <variants.h>
 
+#define TJ_MAX		105
+#define TCC(temp)	(TJ_MAX - temp)
+
 void devtree_update(void)
 {
 	config_t *cfg = config_of_soc();
@@ -31,15 +34,15 @@ void devtree_update(void)
 	switch (get_power_profile(PP_POWER_SAVER)) {
 	case PP_POWER_SAVER:
 		performance_scale			-= 50;
-		cfg->tcc_offset				= 30;
+		cfg->tcc_offset				= TCC(70);
 		break;
 	case PP_BALANCED:
 		performance_scale			-= 25;
-		cfg->tcc_offset				= 25;
+		cfg->tcc_offset				= TCC(80);
 		break;
 	case PP_PERFORMANCE:
 		/* Use the Intel defaults */
-		cfg->tcc_offset				= 20;
+		cfg->tcc_offset				= TCC(90);
 		break;
 	}
 
diff --git a/src/mainboard/starlabs/starbook/variants/adl/devtree.c b/src/mainboard/starlabs/starbook/variants/adl/devtree.c
index 0f40aaf1b1..5bbf8a3b40 100644
--- a/src/mainboard/starlabs/starbook/variants/adl/devtree.c
+++ b/src/mainboard/starlabs/starbook/variants/adl/devtree.c
@@ -9,6 +9,9 @@
 #include <types.h>
 #include <variants.h>
 
+#define TJ_MAX		110
+#define TCC(temp)	(TJ_MAX - temp)
+
 void devtree_update(void)
 {
 	config_t *cfg = config_of_soc();
@@ -35,15 +38,15 @@ void devtree_update(void)
 	switch (get_power_profile(PP_POWER_SAVER)) {
 	case PP_POWER_SAVER:
 		performance_scale			-= 50;
-		cfg->tcc_offset				= 20;
+		cfg->tcc_offset				= TCC(80);
 		break;
 	case PP_BALANCED:
 		performance_scale			-= 25;
-		cfg->tcc_offset				= 15;
+		cfg->tcc_offset				= TCC(90);
 		break;
 	case PP_PERFORMANCE:
 		/* Use the Intel defaults */
-		cfg->tcc_offset				= 10;
+		cfg->tcc_offset				= TCC(100);
 		break;
 	}
 
diff --git a/src/mainboard/starlabs/starbook/variants/adl_n/devtree.c b/src/mainboard/starlabs/starbook/variants/adl_n/devtree.c
index a4cc362853..1197f14cc6 100644
--- a/src/mainboard/starlabs/starbook/variants/adl_n/devtree.c
+++ b/src/mainboard/starlabs/starbook/variants/adl_n/devtree.c
@@ -9,6 +9,9 @@
 #include <types.h>
 #include <variants.h>
 
+#define TJ_MAX		105
+#define TCC(temp)	(TJ_MAX - temp)
+
 void devtree_update(void)
 {
 	config_t *cfg = config_of_soc();
@@ -30,15 +33,15 @@ void devtree_update(void)
 	switch (get_power_profile(PP_POWER_SAVER)) {
 	case PP_POWER_SAVER:
 		performance_scale			-= 50;
-		cfg->tcc_offset				= 20;
+		cfg->tcc_offset				= TCC(70);
 		break;
 	case PP_BALANCED:
 		performance_scale			-= 25;
-		cfg->tcc_offset				= 15;
+		cfg->tcc_offset				= TCC(80);
 		break;
 	case PP_PERFORMANCE:
 		/* Use the Intel defaults */
-		cfg->tcc_offset				= 10;
+		cfg->tcc_offset				= TCC(90);
 		break;
 	}
 
diff --git a/src/mainboard/starlabs/starbook/variants/cml/devtree.c b/src/mainboard/starlabs/starbook/variants/cml/devtree.c
index b28c9f6cdc..85b5174392 100644
--- a/src/mainboard/starlabs/starbook/variants/cml/devtree.c
+++ b/src/mainboard/starlabs/starbook/variants/cml/devtree.c
@@ -9,6 +9,9 @@
 #include <types.h>
 #include <variants.h>
 
+#define TJ_MAX		100
+#define TCC(temp)	(TJ_MAX - temp)
+
 void devtree_update(void)
 {
 	config_t *cfg = config_of_soc();
@@ -29,15 +32,15 @@ void devtree_update(void)
 	switch (get_power_profile(PP_POWER_SAVER)) {
 	case PP_POWER_SAVER:
 		performance_scale		-= 50;
-		cfg->tcc_offset			= 20;
+		cfg->tcc_offset			= TCC(80);
 		break;
 	case PP_BALANCED:
 		performance_scale		-= 25;
-		cfg->tcc_offset			= 15;
+		cfg->tcc_offset			= TCC(90);
 		break;
 	case PP_PERFORMANCE:
 		/* Use the Intel defaults */
-		cfg->tcc_offset			= 10;
+		cfg->tcc_offset			= TCC(100);
 		break;
 	}
 
diff --git a/src/mainboard/starlabs/starbook/variants/kbl/devtree.c b/src/mainboard/starlabs/starbook/variants/kbl/devtree.c
index 2599db86f8..4c7394515f 100644
--- a/src/mainboard/starlabs/starbook/variants/kbl/devtree.c
+++ b/src/mainboard/starlabs/starbook/variants/kbl/devtree.c
@@ -9,6 +9,9 @@
 #include <types.h>
 #include <variants.h>
 
+#define TJ_MAX		100
+#define TCC(temp)	(TJ_MAX - temp)
+
 void devtree_update(void)
 {
 	config_t *cfg = config_of_soc();
@@ -29,15 +32,15 @@ void devtree_update(void)
 	switch (get_power_profile(PP_POWER_SAVER)) {
 	case PP_POWER_SAVER:
 		performance_scale		-= 50;
-		cfg->tcc_offset			= 20;
+		cfg->tcc_offset			= TCC(80);
 		break;
 	case PP_BALANCED:
 		performance_scale		-= 25;
-		cfg->tcc_offset			= 15;
+		cfg->tcc_offset			= TCC(90);
 		break;
 	case PP_PERFORMANCE:
 		/* Use the Intel defaults */
-		cfg->tcc_offset			= 10;
+		cfg->tcc_offset			= TCC(100);
 		break;
 	}
 
diff --git a/src/mainboard/starlabs/starbook/variants/mtl/devtree.c b/src/mainboard/starlabs/starbook/variants/mtl/devtree.c
index 1d0176d514..c329bacffa 100644
--- a/src/mainboard/starlabs/starbook/variants/mtl/devtree.c
+++ b/src/mainboard/starlabs/starbook/variants/mtl/devtree.c
@@ -9,6 +9,9 @@
 #include <types.h>
 #include <variants.h>
 
+#define TJ_MAX		110
+#define TCC(temp)	(TJ_MAX - temp)
+
 void devtree_update(void)
 {
 	config_t *cfg = config_of_soc();
@@ -30,15 +33,15 @@ void devtree_update(void)
 	switch (get_power_profile(PP_POWER_SAVER)) {
 	case PP_POWER_SAVER:
 		performance_scale			-= 50;
-		cfg->tcc_offset				= 30;
+		cfg->tcc_offset				= TCC(80);
 		break;
 	case PP_BALANCED:
 		performance_scale			-= 25;
-		cfg->tcc_offset				= 25;
+		cfg->tcc_offset				= TCC(90);
 		break;
 	case PP_PERFORMANCE:
 		/* Use the Intel defaults */
-		cfg->tcc_offset				= 20;
+		cfg->tcc_offset				= TCC(100);
 		break;
 	}
 
diff --git a/src/mainboard/starlabs/starbook/variants/rpl/devtree.c b/src/mainboard/starlabs/starbook/variants/rpl/devtree.c
index 5c2fc238dd..76031d0f1f 100644
--- a/src/mainboard/starlabs/starbook/variants/rpl/devtree.c
+++ b/src/mainboard/starlabs/starbook/variants/rpl/devtree.c
@@ -9,6 +9,9 @@
 #include <types.h>
 #include <variants.h>
 
+#define TJ_MAX		110
+#define TCC(temp)	(TJ_MAX - temp)
+
 void devtree_update(void)
 {
 	config_t *cfg = config_of_soc();
@@ -37,15 +40,15 @@ void devtree_update(void)
 	switch (get_power_profile(PP_POWER_SAVER)) {
 	case PP_POWER_SAVER:
 		performance_scale			-= 50;
-		cfg->tcc_offset				= 30;
+		cfg->tcc_offset				= TCC(80);
 		break;
 	case PP_BALANCED:
 		performance_scale			-= 25;
-		cfg->tcc_offset				= 25;
+		cfg->tcc_offset				= TCC(90);
 		break;
 	case PP_PERFORMANCE:
 		/* Use the Intel defaults */
-		cfg->tcc_offset				= 20;
+		cfg->tcc_offset				= TCC(100);
 		break;
 	}
 
diff --git a/src/mainboard/starlabs/starbook/variants/tgl/devtree.c b/src/mainboard/starlabs/starbook/variants/tgl/devtree.c
index 6b7d4233a0..8f6e39b066 100644
--- a/src/mainboard/starlabs/starbook/variants/tgl/devtree.c
+++ b/src/mainboard/starlabs/starbook/variants/tgl/devtree.c
@@ -9,6 +9,9 @@
 #include <types.h>
 #include <variants.h>
 
+#define TJ_MAX		100
+#define TCC(temp)	(TJ_MAX - temp)
+
 void devtree_update(void)
 {
 	config_t *cfg = config_of_soc();
@@ -38,15 +41,15 @@ void devtree_update(void)
 	switch (get_power_profile(PP_POWER_SAVER)) {
 	case PP_POWER_SAVER:
 		performance_scale			-= 50;
-		cfg->tcc_offset				= 30;
+		cfg->tcc_offset				= TCC(80);
 		break;
 	case PP_BALANCED:
 		performance_scale			-= 25;
-		cfg->tcc_offset				= 25;
+		cfg->tcc_offset				= TCC(90);
 		break;
 	case PP_PERFORMANCE:
 		/* Use the Intel defaults */
-		cfg->tcc_offset				= 20;
+		cfg->tcc_offset				= TCC(100);
 		break;
 	}
 
diff --git a/src/mainboard/starlabs/starfighter/variants/rpl/devtree.c b/src/mainboard/starlabs/starfighter/variants/rpl/devtree.c
index 2bea4e81b3..7a4111dddb 100644
--- a/src/mainboard/starlabs/starfighter/variants/rpl/devtree.c
+++ b/src/mainboard/starlabs/starfighter/variants/rpl/devtree.c
@@ -9,6 +9,9 @@
 #include <types.h>
 #include <variants.h>
 
+#define TJ_MAX		110
+#define TCC(temp)	(TJ_MAX - temp)
+
 void devtree_update(void)
 {
 	config_t *cfg = config_of_soc();
@@ -38,15 +41,15 @@ void devtree_update(void)
 	switch (get_power_profile(PP_POWER_SAVER)) {
 	case PP_POWER_SAVER:
 		performance_scale			-= 50;
-		cfg->tcc_offset				= 30;
+		cfg->tcc_offset				= TCC(80);
 		break;
 	case PP_BALANCED:
 		performance_scale			-= 25;
-		cfg->tcc_offset				= 25;
+		cfg->tcc_offset				= TCC(90);
 		break;
 	case PP_PERFORMANCE:
 		/* Use the Intel defaults */
-		cfg->tcc_offset				= 20;
+		cfg->tcc_offset				= TCC(100);
 		break;
 	}
 
diff --git a/src/mainboard/starlabs/starlite_adl/variants/mk_v/devtree.c b/src/mainboard/starlabs/starlite_adl/variants/mk_v/devtree.c
index 6805e32d05..08359ee7b1 100644
--- a/src/mainboard/starlabs/starlite_adl/variants/mk_v/devtree.c
+++ b/src/mainboard/starlabs/starlite_adl/variants/mk_v/devtree.c
@@ -9,6 +9,9 @@
 #include <types.h>
 #include <variants.h>
 
+#define TJ_MAX		105
+#define TCC(temp)	(TJ_MAX - temp)
+
 void devtree_update(void)
 {
 	config_t *cfg = config_of_soc();
@@ -33,15 +36,15 @@ void devtree_update(void)
 	switch (get_power_profile(PP_POWER_SAVER)) {
 	case PP_POWER_SAVER:
 		performance_scale			-= 50;
-		cfg->tcc_offset				= 30;
+		cfg->tcc_offset				= TCC(70);
 		break;
 	case PP_BALANCED:
 		performance_scale			-= 25;
-		cfg->tcc_offset				= 25;
+		cfg->tcc_offset				= TCC(80);
 		break;
 	case PP_PERFORMANCE:
 		/* Use the Intel defaults */
-		cfg->tcc_offset				= 20;
+		cfg->tcc_offset				= TCC(90);
 		break;
 	}
 

From bea62e221d0190c87cc618015d1c067c2b8db235 Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Wed, 5 Mar 2025 15:24:19 +0000
Subject: [PATCH 0291/3886] mb/starlabs/starbook/mtl: Configure tcss_aux_ori

Both USB Type-C ports do not have retimers, so configure this
accordingly.

Change-Id: I341e54984b768ff5b1020c6d127b0c4b18b8725c
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86741
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
---
 src/mainboard/starlabs/starbook/variants/mtl/devicetree.cb | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/src/mainboard/starlabs/starbook/variants/mtl/devicetree.cb b/src/mainboard/starlabs/starbook/variants/mtl/devicetree.cb
index 7b9be13795..ac0195c1f3 100644
--- a/src/mainboard/starlabs/starbook/variants/mtl/devicetree.cb
+++ b/src/mainboard/starlabs/starbook/variants/mtl/devicetree.cb
@@ -52,6 +52,8 @@ chip soc/intel/meteorlake
 			}"
 		end
 		device ref tcss_xhci	on
+			register "tcss_aux_ori"			= "(BIT(0) | BIT(2))"
+
 			chip drivers/usb/acpi
 				device ref tcss_root_hub on
 					chip drivers/usb/acpi

From 17da392ae85c796765df9db997ea74afa5465d93 Mon Sep 17 00:00:00 2001
From: Kapil Porwal <kapilporwal@google.com>
Date: Thu, 6 Mar 2025 13:57:54 +0530
Subject: [PATCH 0292/3886] soc/intel,mb/google: Use the correct SoC config

Change-Id: I657a4d45901f6b2bab8daa6c93509190896cab62
Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86748
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
Reviewed-by: Pranava Y N <pranavayn@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/google/ocelot/Kconfig | 3 +--
 src/soc/intel/pantherlake/Kconfig   | 6 ------
 2 files changed, 1 insertion(+), 8 deletions(-)

diff --git a/src/mainboard/google/ocelot/Kconfig b/src/mainboard/google/ocelot/Kconfig
index 38393bdbbd..b4adda22d7 100644
--- a/src/mainboard/google/ocelot/Kconfig
+++ b/src/mainboard/google/ocelot/Kconfig
@@ -37,7 +37,7 @@ config BOARD_GOOGLE_OCELOT_COMMON
 	select SOC_INTEL_COMMON_BLOCK_VARIANT_POWER_LIMIT
 	select SOC_INTEL_CSE_LITE_SYNC_BY_PAYLOAD
 	select SOC_INTEL_CSE_SEND_EOP_BY_PAYLOAD
-	select SOC_INTEL_WILDCATLAKE
+	select SOC_INTEL_PANTHERLAKE_U_H
 	select SOC_INTEL_TCSS_USE_PDC_PMC_USBC_MUX_CONFIGURATION
 
 config BOARD_GOOGLE_BASEBOARD_OCELOT
@@ -62,7 +62,6 @@ config BOARD_GOOGLE_OCELOT
 	select DRIVERS_GENERIC_MAX98357A
 	select EC_GOOGLE_CHROMEEC_MEC
 	select MAINBOARD_USES_IFD_EC_REGION
-	select SOC_INTEL_WILDCATLAKE
 
 if BOARD_GOOGLE_OCELOT_COMMON
 
diff --git a/src/soc/intel/pantherlake/Kconfig b/src/soc/intel/pantherlake/Kconfig
index 58e6c28686..fc8664a927 100644
--- a/src/soc/intel/pantherlake/Kconfig
+++ b/src/soc/intel/pantherlake/Kconfig
@@ -127,12 +127,6 @@ config SOC_INTEL_PANTHERLAKE_H
 	help
 	  Choose this option if the mainboard is built using PTL-H 4Xe system-on-a-chip (SoC).
 
-config SOC_INTEL_WILDCATLAKE
-	bool
-	select SOC_INTEL_PANTHERLAKE_U_H
-	help
-	  Choose this option if the mainboard is built using WCL system-on-a-chip (SoC).
-
 if SOC_INTEL_PANTHERLAKE_BASE
 
 config SOC_INTEL_PANTHERLAKE_TCSS_USB4_SUPPORT

From c8f9199f12eb96ab3c70943ac28fd8faa7c82af0 Mon Sep 17 00:00:00 2001
From: Subrata Banik <subratabanik@google.com>
Date: Tue, 4 Mar 2025 19:08:46 +0000
Subject: [PATCH 0293/3886] {drivers, mb, soc}: Drop `HAVE_FSP_LOGO_SUPPORT`
 Kconfig
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

This change eliminates the HAVE_FSP_LOGO_SUPPORT Kconfig option.

It was initially used to control BMP_LOGO selection within the FSP2.0
driver. However, upcoming refactoring will move BMP_LOGO and its
implementation to the `lib` directory therefore, BMP_LOGO can be
used by both FSP and non-FSP SoC platforms.

BUG=b:400738815
TEST=Able to build and boot google/brox.

Change-Id: I899bbfcf7e747abe69ff0866c4594a42278891b9
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86719
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
---
 src/drivers/intel/fsp2_0/Kconfig  | 5 -----
 src/mainboard/google/brox/Kconfig | 1 -
 src/mainboard/google/brya/Kconfig | 1 -
 src/soc/amd/mendocino/Kconfig     | 1 -
 src/soc/intel/apollolake/Kconfig  | 1 -
 src/soc/intel/cannonlake/Kconfig  | 1 -
 src/soc/intel/meteorlake/Kconfig  | 1 -
 src/soc/intel/pantherlake/Kconfig | 1 -
 src/soc/intel/skylake/Kconfig     | 1 -
 9 files changed, 13 deletions(-)

diff --git a/src/drivers/intel/fsp2_0/Kconfig b/src/drivers/intel/fsp2_0/Kconfig
index 42551503ff..317fea21c0 100644
--- a/src/drivers/intel/fsp2_0/Kconfig
+++ b/src/drivers/intel/fsp2_0/Kconfig
@@ -265,14 +265,9 @@ config FSP_PLATFORM_MEMORY_SETTINGS_VERSIONS
 	  This allows deployed systems to bump their version number
 	  with the same FSP which will trigger a retrain of the memory.
 
-config HAVE_FSP_LOGO_SUPPORT
-	bool
-	default n
-
 config BMP_LOGO
 	bool "Enable logo"
 	default n
-	depends on HAVE_FSP_LOGO_SUPPORT
 	help
 	  Uses the FSP to display the boot logo. This method supports a
 	  BMP file only. The uncompressed size can be up to 1 MB. The logo can
diff --git a/src/mainboard/google/brox/Kconfig b/src/mainboard/google/brox/Kconfig
index 1731d517a5..6f50880e2e 100644
--- a/src/mainboard/google/brox/Kconfig
+++ b/src/mainboard/google/brox/Kconfig
@@ -21,7 +21,6 @@ config BOARD_GOOGLE_BROX_COMMON
 	select FW_CONFIG_SOURCE_CHROMEEC_CBI
 	select GOOGLE_SMBIOS_MAINBOARD_VERSION
 	select HAVE_ACPI_TABLES
-	select HAVE_FSP_LOGO_SUPPORT if RUN_FSP_GOP
 	select I2C_TPM
 	select INTEL_LPSS_UART_FOR_CONSOLE
 	select MAINBOARD_HAS_CHROMEOS
diff --git a/src/mainboard/google/brya/Kconfig b/src/mainboard/google/brya/Kconfig
index 0cc66243b5..a630323984 100644
--- a/src/mainboard/google/brya/Kconfig
+++ b/src/mainboard/google/brya/Kconfig
@@ -29,7 +29,6 @@ config BOARD_GOOGLE_BRYA_COMMON
 	select FW_CONFIG_SOURCE_CHROMEEC_CBI
 	select GOOGLE_SMBIOS_MAINBOARD_VERSION
 	select HAVE_ACPI_TABLES
-	select HAVE_FSP_LOGO_SUPPORT if RUN_FSP_GOP
 	select I2C_TPM
 	select INTEL_LPSS_UART_FOR_CONSOLE
 	select MAINBOARD_HAS_CHROMEOS
diff --git a/src/soc/amd/mendocino/Kconfig b/src/soc/amd/mendocino/Kconfig
index ee6c968d2e..f67ecb27ef 100644
--- a/src/soc/amd/mendocino/Kconfig
+++ b/src/soc/amd/mendocino/Kconfig
@@ -17,7 +17,6 @@ config SOC_AMD_REMBRANDT_BASE
 	select HAVE_CF9_RESET
 	select HAVE_EM100_SUPPORT
 	select HAVE_FSP_GOP
-	select HAVE_FSP_LOGO_SUPPORT if RUN_FSP_GOP
 	select HAVE_SMI_HANDLER
 	select IDT_IN_EVERY_STAGE
 	select PARALLEL_MP_AP_WORK
diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig
index 55f59b3bed..4b770da889 100644
--- a/src/soc/intel/apollolake/Kconfig
+++ b/src/soc/intel/apollolake/Kconfig
@@ -26,7 +26,6 @@ config SOC_INTEL_APOLLOLAKE
 	select HAVE_CF9_RESET_PREPARE
 	select HAVE_DPTF_EISA_HID
 	select HAVE_FSP_GOP
-	select HAVE_FSP_LOGO_SUPPORT
 	select HAVE_INTEL_FSP_REPO if !SOC_INTEL_GEMINILAKE
 	select HAVE_SMI_HANDLER
 	select INTEL_DESCRIPTOR_MODE_CAPABLE
diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig
index 59b09a5d33..67ab428a49 100644
--- a/src/soc/intel/cannonlake/Kconfig
+++ b/src/soc/intel/cannonlake/Kconfig
@@ -19,7 +19,6 @@ config SOC_INTEL_CANNONLAKE_BASE
 	select GENERIC_GPIO_LIB
 	select HAVE_DPTF_EISA_HID
 	select HAVE_FSP_GOP
-	select HAVE_FSP_LOGO_SUPPORT
 	select HAVE_HYPERTHREADING
 	select HAVE_INTEL_FSP_REPO
 	select HAVE_SMI_HANDLER
diff --git a/src/soc/intel/meteorlake/Kconfig b/src/soc/intel/meteorlake/Kconfig
index cebf414f11..2a692740c3 100644
--- a/src/soc/intel/meteorlake/Kconfig
+++ b/src/soc/intel/meteorlake/Kconfig
@@ -25,7 +25,6 @@ config SOC_INTEL_METEORLAKE
 	select GENERIC_GPIO_LIB
 	select HAVE_DEBUG_RAM_SETUP
 	select HAVE_FSP_GOP
-	select HAVE_FSP_LOGO_SUPPORT if RUN_FSP_GOP
 	select HAVE_HYPERTHREADING
 	select HAVE_INTEL_COMPLIANCE_TEST_MODE
 	select HAVE_SMI_HANDLER
diff --git a/src/soc/intel/pantherlake/Kconfig b/src/soc/intel/pantherlake/Kconfig
index fc8664a927..d372a6fdd7 100644
--- a/src/soc/intel/pantherlake/Kconfig
+++ b/src/soc/intel/pantherlake/Kconfig
@@ -24,7 +24,6 @@ config SOC_INTEL_PANTHERLAKE_BASE
 	select HAVE_DEBUG_RAM_SETUP
 	select HAVE_ESOL_SUPPORT_FOR_LOW_BATTERY_INDICATOR if CHROMEOS_ENABLE_ESOL
 	select HAVE_FSP_GOP
-	select HAVE_FSP_LOGO_SUPPORT if RUN_FSP_GOP
 	select HAVE_HYPERTHREADING
 	select HAVE_INTEL_COMPLIANCE_TEST_MODE
 	select HAVE_SMI_HANDLER
diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig
index 22017c848b..4ad33496b2 100644
--- a/src/soc/intel/skylake/Kconfig
+++ b/src/soc/intel/skylake/Kconfig
@@ -15,7 +15,6 @@ config SOC_INTEL_COMMON_SKYLAKE_BASE
 	select FSP_M_XIP
 	select GENERIC_GPIO_LIB
 	select HAVE_FSP_GOP
-	select HAVE_FSP_LOGO_SUPPORT
 	select HAVE_HYPERTHREADING
 	select HAVE_INTEL_FSP_REPO
 	select INTEL_CAR_NEM_ENHANCED

From cf8f0693a60ba32ce65e522eca00d1ba37082920 Mon Sep 17 00:00:00 2001
From: Subrata Banik <subratabanik@google.com>
Date: Wed, 5 Mar 2025 10:53:51 +0000
Subject: [PATCH 0294/3886] {drivers, lib}: Rename FSP*_LOGO_FILE_NAME to
 BMP_LOGO_FILE_NAME
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

This commit standardizes the Kconfig option for the boot logo file name
across FSP drivers and the common library.

The `FSP1_1_LOGO_FILE_NAME` and `FSP2_0_LOGO_FILE_NAME` options are
renamed to `BMP_LOGO_FILE_NAME`.

BUG=b:400738815
TEST=Able to build and boot google/brox.

Change-Id: I6a6c2c6d235ad9643879b00232930c8a0d2e3801
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86725
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
---
 src/drivers/intel/fsp1_1/Kconfig     | 2 +-
 src/drivers/intel/fsp1_1/Makefile.mk | 2 +-
 src/drivers/intel/fsp2_0/Kconfig     | 2 +-
 src/lib/Makefile.mk                  | 2 +-
 4 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/src/drivers/intel/fsp1_1/Kconfig b/src/drivers/intel/fsp1_1/Kconfig
index 3ab90963fe..aabcabbf26 100644
--- a/src/drivers/intel/fsp1_1/Kconfig
+++ b/src/drivers/intel/fsp1_1/Kconfig
@@ -85,7 +85,7 @@ config BMP_LOGO
 	  Uses the FSP to display the boot logo. This method supports a
 	  BMP file only. The uncompressed size can be up to 1 MB.
 
-config FSP1_1_LOGO_FILE_NAME
+config BMP_LOGO_FILE_NAME
 	string "Logo file"
 	depends on BMP_LOGO
 	default "3rdparty/blobs/mainboard/\$(MAINBOARDDIR)/logo.bmp"
diff --git a/src/drivers/intel/fsp1_1/Makefile.mk b/src/drivers/intel/fsp1_1/Makefile.mk
index c890f350e1..28489fe133 100644
--- a/src/drivers/intel/fsp1_1/Makefile.mk
+++ b/src/drivers/intel/fsp1_1/Makefile.mk
@@ -38,7 +38,7 @@ endif
 
 # Add logo to the cbfs image
 cbfs-files-$(CONFIG_BMP_LOGO) += logo.bmp
-logo.bmp-file := $(call strip_quotes,$(CONFIG_FSP1_1_LOGO_FILE_NAME))
+logo.bmp-file := $(call strip_quotes,$(CONFIG_BMP_LOGO_FILE_NAME))
 logo.bmp-type := raw
 logo.bmp-compression := LZMA
 
diff --git a/src/drivers/intel/fsp2_0/Kconfig b/src/drivers/intel/fsp2_0/Kconfig
index 317fea21c0..c9fa8e560f 100644
--- a/src/drivers/intel/fsp2_0/Kconfig
+++ b/src/drivers/intel/fsp2_0/Kconfig
@@ -302,7 +302,7 @@ config BMP_LOGO_COMPRESS_LZ4
 
 endchoice
 
-config FSP2_0_LOGO_FILE_NAME
+config BMP_LOGO_FILE_NAME
 	string "Logo file"
 	depends on BMP_LOGO
 	default "3rdparty/blobs/mainboard/\$(MAINBOARDDIR)/logo.bmp"
diff --git a/src/lib/Makefile.mk b/src/lib/Makefile.mk
index 5e1e81a5d0..84b982dbf6 100644
--- a/src/lib/Makefile.mk
+++ b/src/lib/Makefile.mk
@@ -438,7 +438,7 @@ endef
 
 ifneq ($(CONFIG_HAVE_CUSTOM_BMP_LOGO),y)
 $(eval $(call add_bmp_logo_file_to_cbfs,CONFIG_BMP_LOGO, logo.bmp,\
-	      CONFIG_FSP2_0_LOGO_FILE_NAME))
+	      CONFIG_BMP_LOGO_FILE_NAME))
 endif
 
 $(eval $(call add_bmp_logo_file_to_cbfs,CONFIG_PLATFORM_HAS_LOW_BATTERY_INDICATOR, \

From efb1806d3d26b623d67e6536f1201ebd77edc821 Mon Sep 17 00:00:00 2001
From: Subrata Banik <subratabanik@google.com>
Date: Wed, 5 Mar 2025 12:05:29 +0000
Subject: [PATCH 0295/3886] {drivers, lib}: Move BMP_LOGO Kconfig options to
 common library
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

This commit relocates the BMP_LOGO related Kconfig options from the
FSP1.1 and FSP2.0 drivers to the common library (lib/).

This change:

-   Centralizes the BMP_LOGO configuration, making it accessible to
    all drivers and platforms.
-   Removes duplicate Kconfig entries from the FSP drivers.
-   Prepares for future refactoring where BMP_LOGO will be handled
    entirely within the library, enabling its use by both FSP and
    non-FSP platforms.

The following Kconfig options are moved under "Boot Logo Configuration"
menu option:

-   `BMP_LOGO`
-   `BMP_LOGO_COMPRESS_LZMA`
-   `BMP_LOGO_COMPRESS_LZ4`
-   `BMP_LOGO_FILE_NAME`
-   `HAVE_BMP_LOGO_COMPRESS_LZMA`
-   `HAVE_CUSTOM_BMP_LOGO`

BUG=b:400738815
TEST=Able to build and boot google/brox.

Change-Id: I9bbfade9b919cfbd0b689a67c988ed8c65deb597
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86730
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/drivers/intel/fsp1_1/Kconfig     | 12 --------
 src/drivers/intel/fsp1_1/Makefile.mk |  6 ----
 src/drivers/intel/fsp2_0/Kconfig     | 42 -------------------------
 src/lib/Kconfig                      | 46 ++++++++++++++++++++++++++++
 4 files changed, 46 insertions(+), 60 deletions(-)

diff --git a/src/drivers/intel/fsp1_1/Kconfig b/src/drivers/intel/fsp1_1/Kconfig
index aabcabbf26..3460202eb1 100644
--- a/src/drivers/intel/fsp1_1/Kconfig
+++ b/src/drivers/intel/fsp1_1/Kconfig
@@ -78,16 +78,4 @@ config SKIP_FSP_CAR
 	help
 	  Selected by platforms that implement their own CAR setup.
 
-config BMP_LOGO
-	bool "Enable logo"
-	default n
-	help
-	  Uses the FSP to display the boot logo. This method supports a
-	  BMP file only. The uncompressed size can be up to 1 MB.
-
-config BMP_LOGO_FILE_NAME
-	string "Logo file"
-	depends on BMP_LOGO
-	default "3rdparty/blobs/mainboard/\$(MAINBOARDDIR)/logo.bmp"
-
 endif #PLATFORM_USES_FSP1_1
diff --git a/src/drivers/intel/fsp1_1/Makefile.mk b/src/drivers/intel/fsp1_1/Makefile.mk
index 28489fe133..0415d09b5a 100644
--- a/src/drivers/intel/fsp1_1/Makefile.mk
+++ b/src/drivers/intel/fsp1_1/Makefile.mk
@@ -36,10 +36,4 @@ fsp.bin-options := --xip $(TXTIBB)
 fsp.bin-COREBOOT-position := $(CONFIG_FSP_LOC)
 endif
 
-# Add logo to the cbfs image
-cbfs-files-$(CONFIG_BMP_LOGO) += logo.bmp
-logo.bmp-file := $(call strip_quotes,$(CONFIG_BMP_LOGO_FILE_NAME))
-logo.bmp-type := raw
-logo.bmp-compression := LZMA
-
 endif
diff --git a/src/drivers/intel/fsp2_0/Kconfig b/src/drivers/intel/fsp2_0/Kconfig
index c9fa8e560f..ffe0778971 100644
--- a/src/drivers/intel/fsp2_0/Kconfig
+++ b/src/drivers/intel/fsp2_0/Kconfig
@@ -265,48 +265,6 @@ config FSP_PLATFORM_MEMORY_SETTINGS_VERSIONS
 	  This allows deployed systems to bump their version number
 	  with the same FSP which will trigger a retrain of the memory.
 
-config BMP_LOGO
-	bool "Enable logo"
-	default n
-	help
-	  Uses the FSP to display the boot logo. This method supports a
-	  BMP file only. The uncompressed size can be up to 1 MB. The logo can
-	  be compressed based on either `BMP_LOGO_COMPRESS_*` configs (default LZMA).
-
-config HAVE_BMP_LOGO_COMPRESS_LZMA
-	bool
-	depends on BMP_LOGO
-	default y
-
-choice
-	prompt "BMP Logo compression"
-	depends on BMP_LOGO
-	default BMP_LOGO_COMPRESS_LZMA if HAVE_BMP_LOGO_COMPRESS_LZMA
-	default BMP_LOGO_COMPRESS_LZ4
-
-config BMP_LOGO_COMPRESS_LZMA
-	bool "Use LZMA compression for BMP logo"
-	help
-	  This option enables the use of LZMA compression for the BMP logo.
-	  LZMA is a lossless compression algorithm that can significantly reduce
-	  the size of the logo, without sacrificing quality.
-
-	  If this option is not enabled, the BMP logo will be uncompressed.
-
-config BMP_LOGO_COMPRESS_LZ4
-	bool "Compress BMP logo using LZ4"
-	help
-	  This option enables compression of the BMP logo using the LZ4 algorithm.
-	  Although the size reduction is not as efficient as LZMA compression, however,
-	  it can also make the boot process slightly faster compared to the LZMA.
-
-endchoice
-
-config BMP_LOGO_FILE_NAME
-	string "Logo file"
-	depends on BMP_LOGO
-	default "3rdparty/blobs/mainboard/\$(MAINBOARDDIR)/logo.bmp"
-
 config FSP_COMPRESS_FSP_S_LZMA
 	bool
 
diff --git a/src/lib/Kconfig b/src/lib/Kconfig
index ad706261b8..dce3c44b5b 100644
--- a/src/lib/Kconfig
+++ b/src/lib/Kconfig
@@ -156,10 +156,56 @@ config PROBE_RAM
 	  When enabled it will be possible to detect usable RAM using probe_ram
 	  function.
 
+menu "Boot Logo Configuration"
+
+config BMP_LOGO
+	bool "Enable logo"
+	default n
+	help
+	  Uses the FSP to display the boot logo. This method supports a
+	  BMP file only. The uncompressed size can be up to 1 MB. The logo can
+	  be compressed based on either `BMP_LOGO_COMPRESS_*` configs (default LZMA).
+
 config HAVE_CUSTOM_BMP_LOGO
 	def_bool n
 	depends on BMP_LOGO
 
+config HAVE_BMP_LOGO_COMPRESS_LZMA
+	bool
+	depends on BMP_LOGO
+	default y
+
+choice
+	prompt "BMP Logo compression"
+	depends on BMP_LOGO
+	default BMP_LOGO_COMPRESS_LZMA if HAVE_BMP_LOGO_COMPRESS_LZMA
+	default BMP_LOGO_COMPRESS_LZ4
+
+config BMP_LOGO_COMPRESS_LZMA
+	bool "Use LZMA compression for BMP logo"
+	help
+	  This option enables the use of LZMA compression for the BMP logo.
+	  LZMA is a lossless compression algorithm that can significantly reduce
+	  the size of the logo, without sacrificing quality.
+
+	  If this option is not enabled, the BMP logo will be uncompressed.
+
+config BMP_LOGO_COMPRESS_LZ4
+	bool "Compress BMP logo using LZ4"
+	help
+	  This option enables compression of the BMP logo using the LZ4 algorithm.
+	  Although the size reduction is not as efficient as LZMA compression, however,
+	  it can also make the boot process slightly faster compared to the LZMA.
+
+endchoice
+
+config BMP_LOGO_FILE_NAME
+	string "Logo file"
+	depends on BMP_LOGO
+	default "3rdparty/blobs/mainboard/\$(MAINBOARDDIR)/logo.bmp"
+
+endmenu
+
 config HAVE_EARLY_POWEROFF_SUPPORT
 	bool
 	help

From 1e7ba810c6bba7b31995fe9b1998ffa264acf835 Mon Sep 17 00:00:00 2001
From: Subrata Banik <subratabanik@google.com>
Date: Wed, 5 Mar 2025 12:17:01 +0000
Subject: [PATCH 0296/3886] {commonlib, lib}: Rename CBMEM_ID_FSP_LOGO to
 CBMEM_ID_BMP_LOGO
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

This commit renames the cbmem ID from CBMEM_ID_FSP_LOGO to
CBMEM_ID_BMP_LOGO.

This change:

-   Standardizes the naming to reflect the actual content, which is a
    BMP logo.
-   Removes the FSP-specific prefix, making the ID more generic and
    suitable for use in the common library.
-   Aligns the code with the recent Kconfig changes that moved BMP_LOGO
    related options to the common library.

BUG=b:400738815
TEST=Able to build and boot google/brox.

Change-Id: I838d4e6ad0efdef063f2cc78bb83d1d37e065f45
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86731
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
---
 src/commonlib/bsd/include/commonlib/bsd/cbmem_id.h | 4 ++--
 src/lib/bmp_logo.c                                 | 2 +-
 2 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/src/commonlib/bsd/include/commonlib/bsd/cbmem_id.h b/src/commonlib/bsd/include/commonlib/bsd/cbmem_id.h
index b88a0831b9..7873d5856f 100644
--- a/src/commonlib/bsd/include/commonlib/bsd/cbmem_id.h
+++ b/src/commonlib/bsd/include/commonlib/bsd/cbmem_id.h
@@ -81,7 +81,7 @@
 #define CBMEM_ID_FMAP		0x464d4150
 #define CBMEM_ID_CBFS_RO_MCACHE	0x524d5346
 #define CBMEM_ID_CBFS_RW_MCACHE	0x574d5346
-#define CBMEM_ID_FSP_LOGO	0x4c4f474f
+#define CBMEM_ID_BMP_LOGO	0x4c4f474f
 #define CBMEM_ID_SMM_COMBUFFER	0x53534d32
 #define CBMEM_ID_TYPE_C_INFO	0x54595045
 #define CBMEM_ID_MEM_CHIP_INFO	0x5048434D
@@ -164,7 +164,7 @@
 	{ CBMEM_ID_FMAP,		"FMAP       "}, \
 	{ CBMEM_ID_CBFS_RO_MCACHE,	"RO MCACHE  "}, \
 	{ CBMEM_ID_CBFS_RW_MCACHE,	"RW MCACHE  "}, \
-	{ CBMEM_ID_FSP_LOGO,		"FSP LOGO   "}, \
+	{ CBMEM_ID_BMP_LOGO,		"BMP LOGO   "}, \
 	{ CBMEM_ID_SMM_COMBUFFER,	"SMM COMBUFFER"}, \
 	{ CBMEM_ID_TYPE_C_INFO,		"TYPE_C INFO"},\
 	{ CBMEM_ID_MEM_CHIP_INFO,	"MEM CHIP INFO"},\
diff --git a/src/lib/bmp_logo.c b/src/lib/bmp_logo.c
index 5a5adaafb5..6e3267ee87 100644
--- a/src/lib/bmp_logo.c
+++ b/src/lib/bmp_logo.c
@@ -26,7 +26,7 @@ void *bmp_load_logo(size_t *logo_size)
 	if (acpi_is_wakeup_s3())
 		return NULL;
 
-	logo_entry = cbmem_entry_add(CBMEM_ID_FSP_LOGO, 1 * MiB);
+	logo_entry = cbmem_entry_add(CBMEM_ID_BMP_LOGO, 1 * MiB);
 	if (!logo_entry)
 		return NULL;
 

From 36fd23d143002222a1d9dfb1c0ecc2cd77e60abc Mon Sep 17 00:00:00 2001
From: Varun Upadhyay <varun.upadhyay@intel.com>
Date: Tue, 18 Feb 2025 09:29:13 +0530
Subject: [PATCH 0297/3886] vc/intel/fsp/twinlake: Update FSP headers from
 v5222.01 to v5293.00

Update generated FSP headers for Twinlake from v5293.00

Changes include:
- Add EnableTcssCovTypeA and MappingPchXhciUsbA in FspsUpd.h
- Update UPD Offset in FspsUpd.h

BUG=b:390225562
TEST=Able to build and boot google/Trulo

Change-Id: I6e0bd39addf9f6d48b27748678c70f54abd79cbe
Signed-off-by: Varun Upadhyay <varun.upadhyay@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86591
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
---
 src/vendorcode/intel/fsp/fsp2_0/twinlake/FspsUpd.h | 13 ++++++++++++-
 1 file changed, 12 insertions(+), 1 deletion(-)

diff --git a/src/vendorcode/intel/fsp/fsp2_0/twinlake/FspsUpd.h b/src/vendorcode/intel/fsp/fsp2_0/twinlake/FspsUpd.h
index add6425988..b5e96c1846 100644
--- a/src/vendorcode/intel/fsp/fsp2_0/twinlake/FspsUpd.h
+++ b/src/vendorcode/intel/fsp/fsp2_0/twinlake/FspsUpd.h
@@ -3856,7 +3856,18 @@ typedef struct {
 
 /** Offset 0x0F96 - Reserved
 **/
-  UINT8                       Reserved53[16];
+  UINT8                       Reserved53[8];
+
+/** Offset 0x0F9E - Type C Port x Convert to Type A
+  Enable / Disable (default) Type C Port x Convert to Type A
+  $EN_DIS
+**/
+  UINT8                       EnableTcssCovTypeA[4];
+
+/** Offset 0x0FA2 - PCH xhci port x for Type C Port x mapping
+  input PCH xhci port x for Type C Port 0 mapping.
+**/
+  UINT8                       MappingPchXhciUsbA[4];
 
 /** Offset 0x0FA6 - FOMS Control Policy
   Choose the Foms Control Policy, <b>Default = 0 </b>

From d43ac436dad7bacdc4cbf32ab63fccf2ef4b3c05 Mon Sep 17 00:00:00 2001
From: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Date: Mon, 3 Feb 2025 14:03:54 +0800
Subject: [PATCH 0298/3886] mb/google/nissa/var/dirks: Configure TCSS port 1 to
 USB Type-A

Configure EnableTcssCovTypeA and MappingPchXhciUsbA to repurpose
TCSS port 1 to USB Type-A (Document Number: 742076)

USB Ports for dirks:
(FRONT) USBA 10G x 3
(REAR)  USBA 10G x 2 + USBC 10G x 1

BUG=b:389391653
TEST=none.

Change-Id: Ib227995cde8d871ff58c89ccb09221226640a7e6
Signed-off-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85991
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/google/brya/variants/dirks/Makefile.mk |  1 +
 src/mainboard/google/brya/variants/dirks/ramstage.c  | 12 ++++++++++++
 2 files changed, 13 insertions(+)
 create mode 100644 src/mainboard/google/brya/variants/dirks/ramstage.c

diff --git a/src/mainboard/google/brya/variants/dirks/Makefile.mk b/src/mainboard/google/brya/variants/dirks/Makefile.mk
index d38141ca24..bc39984d6c 100644
--- a/src/mainboard/google/brya/variants/dirks/Makefile.mk
+++ b/src/mainboard/google/brya/variants/dirks/Makefile.mk
@@ -4,3 +4,4 @@ bootblock-y += gpio.c
 romstage-y += gpio.c
 
 ramstage-y += gpio.c
+ramstage-y += ramstage.c
diff --git a/src/mainboard/google/brya/variants/dirks/ramstage.c b/src/mainboard/google/brya/variants/dirks/ramstage.c
new file mode 100644
index 0000000000..d66241f413
--- /dev/null
+++ b/src/mainboard/google/brya/variants/dirks/ramstage.c
@@ -0,0 +1,12 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <soc/ramstage.h>
+
+void mainboard_silicon_init_params(FSP_S_CONFIG *params)
+{
+	/*Enable Type C port1 convert to Type A*/
+	params->EnableTcssCovTypeA[1] = 1;
+	/* PCH xchi port number for Type C port1 port mapping */
+	params->MappingPchXhciUsbA[1] = 2;
+
+}

From 1b7e1adc908a04e129cc74626997ae9c33cef9da Mon Sep 17 00:00:00 2001
From: Zhaoqing Jiu <zhaoqing.jiu@mediatek.corp-partner.google.com>
Date: Mon, 3 Mar 2025 16:19:33 +0800
Subject: [PATCH 0299/3886] soc/mediatek/mt8196: Remove unused LVTS controllers

Controller2 and controller3 are disabled, so remove them from source
code.

BRANCH=rauru
BUG=b:389026545
TEST=Boot up to kernel

Signed-off-by: Zhaoqing Jiu <zhaoqing.jiu@mediatek.corp-partner.google.com>
Change-Id: I69c1e76e7de544fd4e24e8e94e4f676de783e205
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86687
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
---
 .../mt8196/include/soc/thermal_internal.h     | 20 ------
 src/soc/mediatek/mt8196/thermal.c             | 65 -------------------
 2 files changed, 85 deletions(-)

diff --git a/src/soc/mediatek/mt8196/include/soc/thermal_internal.h b/src/soc/mediatek/mt8196/include/soc/thermal_internal.h
index 55c300d7e1..2e9b4a9c34 100644
--- a/src/soc/mediatek/mt8196/include/soc/thermal_internal.h
+++ b/src/soc/mediatek/mt8196/include/soc/thermal_internal.h
@@ -23,28 +23,18 @@ enum lvts_sensor {
 	L_TS_LVTS12_1,		/* LVTS12-1 SOC-BOT */
 	L_TS_LVTS12_2,		/* LVTS12-2 SOC-BOT */
 	L_TS_LVTS12_3,		/* LVTS12-3 SOC-BOT */
-	L_TS_LVTS13_0,		/* LVTS13-0 MD-AP */
-	L_TS_LVTS13_1,		/* LVTS13-1 MD-AP */
-	L_TS_LVTS13_2,		/* LVTS13-2 MD-AP */
-	L_TS_LVTS13_3,		/* LVTS13-3 MD-AP */
-	L_TS_LVTS14_0,		/* LVTS14-0 SOC-ADCT */
-	L_TS_LVTS14_3,		/* LVTS14-3 SOC-ADCT */
 	L_TS_LVTS_NUM,
 };
 
 enum lvts_tc {
 	LVTS_AP_CONTROLLER0 = 0,
 	LVTS_AP_CONTROLLER1,
-	LVTS_AP_CONTROLLER2,
-	LVTS_AP_CONTROLLER3,
 	LVTS_CONTROLLER_NUM,
 };
 
 enum lvts_tc_offset {
 	TS_OFFSET_AP_CONTROLLER0 = 0,
 	TS_OFFSET_AP_CONTROLLER1 = 0x100,
-	TS_OFFSET_AP_CONTROLLER2 = 0x200,
-	TS_OFFSET_AP_CONTROLLER3 = 0x300,
 };
 
 enum sensor_switch_status {
@@ -52,11 +42,6 @@ enum sensor_switch_status {
 	SEN_ON,
 };
 
-enum controller_switch_status {
-	CTRL_OFF,
-	CTRL_ON,
-};
-
 struct lvts_thermal_controller_speed {
 	uint32_t group_interval_delay;
 	uint32_t period_unit;
@@ -67,7 +52,6 @@ struct lvts_thermal_controller_speed {
 struct lvts_thermal_controller {
 	enum lvts_sensor ts[MAX_TS_NUMBER];
 	enum sensor_switch_status sensor_on_off[MAX_TS_NUMBER];
-	enum controller_switch_status ctrl_on_off;
 	size_t ts_number;
 	int reboot_temperature;
 	int dominator_ts_idx;
@@ -80,10 +64,6 @@ static struct mtk_thermal_controller_regs *const
 	mtk_lvts_ap_controller0 = (void *)(THERM_CTRL_BASE + TS_OFFSET_AP_CONTROLLER0);
 static struct mtk_thermal_controller_regs *const
 	mtk_lvts_ap_controller1 = (void *)(THERM_CTRL_BASE + TS_OFFSET_AP_CONTROLLER1);
-static struct mtk_thermal_controller_regs *const
-	mtk_lvts_ap_controller2 = (void *)(THERM_CTRL_BASE + TS_OFFSET_AP_CONTROLLER2);
-static struct mtk_thermal_controller_regs *const
-	mtk_lvts_ap_controller3 = (void *)(THERM_CTRL_BASE + TS_OFFSET_AP_CONTROLLER3);
 
 struct mtk_thermal_controller_regs {
 	u32 lvtsmonctl0_0;
diff --git a/src/soc/mediatek/mt8196/thermal.c b/src/soc/mediatek/mt8196/thermal.c
index 001cd06554..dbd59049e2 100644
--- a/src/soc/mediatek/mt8196/thermal.c
+++ b/src/soc/mediatek/mt8196/thermal.c
@@ -40,7 +40,6 @@ static const struct lvts_thermal_controller lvts_tscpu_g_tc[LVTS_CONTROLLER_NUM]
 	[LVTS_AP_CONTROLLER0] = { /* SOC-TOP */
 		.ts = {L_TS_LVTS11_0, L_TS_LVTS11_1, L_TS_LVTS11_2, L_TS_LVTS11_3},
 		.sensor_on_off = {SEN_ON, SEN_ON, SEN_ON, SEN_ON},
-		.ctrl_on_off = CTRL_ON,
 		.ts_number = 4,
 		.reboot_temperature = 118800,
 		.dominator_ts_idx = 0,
@@ -55,7 +54,6 @@ static const struct lvts_thermal_controller lvts_tscpu_g_tc[LVTS_CONTROLLER_NUM]
 	[LVTS_AP_CONTROLLER1] = { /* SOC-BOT */
 		.ts = {L_TS_LVTS12_0, L_TS_LVTS12_1, L_TS_LVTS12_2, L_TS_LVTS12_3},
 		.sensor_on_off = {SEN_ON, SEN_ON, SEN_ON, SEN_ON},
-		.ctrl_on_off = CTRL_ON,
 		.ts_number = 4,
 		.reboot_temperature = 118800,
 		.dominator_ts_idx = 0,
@@ -67,36 +65,6 @@ static const struct lvts_thermal_controller lvts_tscpu_g_tc[LVTS_CONTROLLER_NUM]
 		},
 		.regs = mtk_lvts_ap_controller1,
 	},
-	[LVTS_AP_CONTROLLER2] = { /* MD-AP */
-		.ts = {L_TS_LVTS13_0, L_TS_LVTS13_1, L_TS_LVTS13_2, L_TS_LVTS13_3},
-		.sensor_on_off = {SEN_ON, SEN_ON, SEN_ON, SEN_ON},
-		.ctrl_on_off = CTRL_OFF,
-		.ts_number = 4,
-		.reboot_temperature = 118800,
-		.dominator_ts_idx = 0,
-		.speed = {
-			.group_interval_delay = 0x7fff,
-			.period_unit = 0x001,
-			.filter_interval_delay = 0x001,
-			.sensor_interval_delay = 0x001,
-		},
-		.regs = mtk_lvts_ap_controller2,
-	},
-	[LVTS_AP_CONTROLLER3] = { /* SOC-ADCT */
-		.ts = {L_TS_LVTS14_0, L_TS_LVTS14_3},
-		.sensor_on_off = {SEN_ON, SEN_ON},
-		.ctrl_on_off = CTRL_OFF,
-		.ts_number = 2,
-		.reboot_temperature = 118800,
-		.dominator_ts_idx = 0,
-		.speed = {
-			.group_interval_delay = 0x7fff,
-			.period_unit = 0x001,
-			.filter_interval_delay = 0x001,
-			.sensor_interval_delay = 0x001,
-		},
-		.regs = mtk_lvts_ap_controller3,
-	},
 };
 
 static uint32_t golden_temp;
@@ -175,9 +143,6 @@ static void lvts_efuse_setting(void)
 
 	for (i = 0; i < ARRAY_SIZE(lvts_tscpu_g_tc); i++) {
 		const struct lvts_thermal_controller *tc = &lvts_tscpu_g_tc[i];
-		if (tc->ctrl_on_off == CTRL_OFF)
-			continue;
-
 		val_0 = 0;
 		val_1 = 0;
 		for (j = 0; j < tc->ts_number; j++) {
@@ -235,9 +200,6 @@ static void lvts_device_identification(void)
 	printk(BIOS_INFO, "===== %s begin ======\n", __func__);
 	for (i = 0; i < ARRAY_SIZE(lvts_tscpu_g_tc); i++) {
 		const struct lvts_thermal_controller *tc = &lvts_tscpu_g_tc[i];
-		if (tc->ctrl_on_off == CTRL_OFF)
-			continue;
-
 		/* Enable LVTS_CTRL Clock */
 		write32(&tc->regs->lvtsclken_0, 0x00000001);
 
@@ -268,10 +230,6 @@ static void lvts_device_enable_init_all_devices(void)
 	uint8_t cali_0, cali_1;
 
 	for (i = 0; i < ARRAY_SIZE(lvts_tscpu_g_tc); i++) {
-		const struct lvts_thermal_controller *tc = &lvts_tscpu_g_tc[i];
-		if (tc->ctrl_on_off == CTRL_OFF)
-			continue;
-
 		/* Stop Counting (RG_TSFM_ST=0) */
 		lvts_write_device(LVTS_DEVICE_WRITE_CONFIG, 0x03, 0x00, i);
 
@@ -406,9 +364,6 @@ static void read_all_tc_lvts_temperature(void)
 
 	for (i = 0; i < ARRAY_SIZE(lvts_tscpu_g_tc); i++) {
 		const struct lvts_thermal_controller *tc = &lvts_tscpu_g_tc[i];
-		if (tc->ctrl_on_off == CTRL_OFF)
-			continue;
-
 		for (j = 0; j < tc->ts_number; j++)
 			lvts_tscpu_thermal_read_tc_temp(tc, j);
 	}
@@ -442,8 +397,6 @@ static void lvts_disable_all_sensing_points(void)
 
 	for (i = 0; i < ARRAY_SIZE(lvts_tscpu_g_tc); i++) {
 		const struct lvts_thermal_controller *tc = &lvts_tscpu_g_tc[i];
-		if (tc->ctrl_on_off == CTRL_OFF)
-			continue;
 		write32(&tc->regs->lvtsmonctl0_0, LVTS_SINGLE_SENSE_MODE_EN);
 	}
 }
@@ -456,9 +409,6 @@ static int lvts_check_all_sensing_points_idle(void)
 	mask = BIT(10) | BIT(7) | BIT(0);
 	for (i = 0; i < ARRAY_SIZE(lvts_tscpu_g_tc); i++) {
 		const struct lvts_thermal_controller *tc = &lvts_tscpu_g_tc[i];
-		if (tc->ctrl_on_off == CTRL_OFF)
-			continue;
-
 		temp = read32(&tc->regs->lvtsmsrctl1_0);
 		if ((temp & mask) != 0)
 			return -1;
@@ -483,9 +433,6 @@ static void lvts_enable_all_sensing_points(void)
 
 	for (i = 0; i < ARRAY_SIZE(lvts_tscpu_g_tc); i++) {
 		const struct lvts_thermal_controller *tc = &lvts_tscpu_g_tc[i];
-		if (tc->ctrl_on_off == CTRL_OFF)
-			continue;
-
 		lvts_enable_sensing_points(tc);
 	}
 }
@@ -500,9 +447,6 @@ static void lvts_set_init_flag(void)
 
 	for (i = 0; i < ARRAY_SIZE(lvts_tscpu_g_tc); i++) {
 		const struct lvts_thermal_controller *tc = &lvts_tscpu_g_tc[i];
-		if (tc->ctrl_on_off == CTRL_OFF)
-			continue;
-
 		printk(BIOS_INFO, "%s %d:%zu, tc_base_addr:%p\n", __func__, i,
 		       tc->ts_number, tc->regs);
 
@@ -553,9 +497,6 @@ static void lvts_tscpu_thermal_initial_all_tc(void)
 
 	for (i = 0; i < ARRAY_SIZE(lvts_tscpu_g_tc); i++) {
 		const struct lvts_thermal_controller *tc = &lvts_tscpu_g_tc[i];
-		if (tc->ctrl_on_off == CTRL_OFF)
-			continue;
-
 		/*  set sensor index of LVTS */
 		write32(&tc->regs->lvtstssel_0, LVTS_SENSOR_POINT_SELECTION_SETTING);
 		/*  set calculation scale rules */
@@ -624,9 +565,6 @@ static void lvts_config_all_tc_hw_protect(void)
 
 	for (i = 0; i < ARRAY_SIZE(lvts_tscpu_g_tc); i++) {
 		const struct lvts_thermal_controller *tc = &lvts_tscpu_g_tc[i];
-		if (tc->ctrl_on_off == CTRL_OFF)
-			continue;
-
 		lvts_set_tc_trigger_hw_protect(tc);
 	}
 }
@@ -637,9 +575,6 @@ static bool lvts_lk_init_check(void)
 
 	for (i = 0; i < ARRAY_SIZE(lvts_tscpu_g_tc); i++) {
 		const struct lvts_thermal_controller *tc = &lvts_tscpu_g_tc[i];
-		if (tc->ctrl_on_off == CTRL_OFF)
-			continue;
-
 		/* Check LVTS device ID */
 		if ((read32(&tc->regs->lvtsspare[0]) & GENMASK(11, 0)) != LVTS_MAGIC)
 			return false;

From 1faea7389cce1c2435d5e35d335c1502ff416ac6 Mon Sep 17 00:00:00 2001
From: Zhaoqing Jiu <zhaoqing.jiu@mediatek.corp-partner.google.com>
Date: Fri, 21 Feb 2025 16:23:20 +0800
Subject: [PATCH 0300/3886] soc/mediatek/mt8196: Save HW protect temperature to
 SRAM

It will restore the HW protection settings based on the data saved in
the SRAM, after the system suspends and resumes.

BRANCH=rauru
BUG=b:389026545
TEST=Boot up and check temperature in coreboot log:
[INFO ]  [LVTS_MSR] ts0 msr_all=141d0, msr_temp=16848, temp=41086
[INFO ]  lvts_tscpu_thermal_read_tc_temp order 0 ts_name 0 temp 41086 rg_temp 41073(42059)
[INFO ]  [LVTS_MSR] ts1 msr_all=141e3, msr_temp=16867, temp=41540
[INFO ]  lvts_tscpu_thermal_read_tc_temp order 1 ts_name 1 temp 41540 rg_temp 41526(42523)
[INFO ]  [LVTS_MSR] ts2 msr_all=14199, msr_temp=16793, temp=39772[0m
[INFO ]  lvts_tscpu_thermal_read_tc_temp order 2 ts_name 2 temp 39772 rg_temp 39760(40715)
[INFO ]  [LVTS_MSR] ts3 msr_all=141c2, msr_temp=16834, temp=40751
[INFO ]  lvts_tscpu_thermal_read_tc_temp order 3 ts_name 3 temp 40751 rg_temp 40739(41717)
[INFO ]  [LVTS_MSR] ts4 msr_all=141d0, msr_temp=16848, temp=41086
[INFO ]  lvts_tscpu_thermal_read_tc_temp order 0 ts_name 4 temp 41086 rg_temp 41073(42059)
[INFO ]  [LVTS_MSR] ts5 msr_all=141b3, msr_temp=16819, temp=40393
[INFO ]  lvts_tscpu_thermal_read_tc_temp order 1 ts_name 5 temp 40393 rg_temp 40380(41350)
[INFO ]  [LVTS_MSR] ts6 msr_all=14194, msr_temp=16788, temp=39652
[INFO ]  lvts_tscpu_thermal_read_tc_temp order 2 ts_name 6 temp 39652 rg_temp 39641(40593)
[INFO ]  [LVTS_MSR] ts7 msr_all=14186, msr_temp=16774, temp=39318
[INFO ]  lvts_tscpu_thermal_read_tc_temp order 3 ts_name 7 temp 39318 rg_temp 39307(40251)

Signed-off-by: Zhaoqing Jiu <zhaoqing.jiu@mediatek.corp-partner.google.com>
Change-Id: Ib714c297871132907e286536c4b3aea1532f3869
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86551
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/soc/mediatek/mt8196/include/soc/thermal.h  |  2 ++
 .../mt8196/include/soc/thermal_internal.h      |  2 ++
 src/soc/mediatek/mt8196/thermal.c              |  8 ++++++++
 src/soc/mediatek/mt8196/thermal_sram.c         | 18 ++++++++++++++++++
 4 files changed, 30 insertions(+)

diff --git a/src/soc/mediatek/mt8196/include/soc/thermal.h b/src/soc/mediatek/mt8196/include/soc/thermal.h
index 6d2b523426..2494853f99 100644
--- a/src/soc/mediatek/mt8196/include/soc/thermal.h
+++ b/src/soc/mediatek/mt8196/include/soc/thermal.h
@@ -5,5 +5,7 @@
 
 void thermal_sram_init(void);
 void thermal_init(void);
+void thermal_write_reboot_temp_sram(uint32_t value);
+void thermal_write_reboot_msr_sram(unsigned int idx, uint32_t value);
 
 #endif /* SOC_MEDIATEK_MT8196_THERMAL_H */
diff --git a/src/soc/mediatek/mt8196/include/soc/thermal_internal.h b/src/soc/mediatek/mt8196/include/soc/thermal_internal.h
index 2e9b4a9c34..65c053d21e 100644
--- a/src/soc/mediatek/mt8196/include/soc/thermal_internal.h
+++ b/src/soc/mediatek/mt8196/include/soc/thermal_internal.h
@@ -55,6 +55,8 @@ struct lvts_thermal_controller {
 	size_t ts_number;
 	int reboot_temperature;
 	int dominator_ts_idx;
+	unsigned int reboot_msr_sram_idx;
+	bool has_reboot_temp_sram;
 	struct lvts_thermal_controller_speed speed;
 	struct mtk_thermal_controller_regs *regs;
 };
diff --git a/src/soc/mediatek/mt8196/thermal.c b/src/soc/mediatek/mt8196/thermal.c
index dbd59049e2..7ea2725283 100644
--- a/src/soc/mediatek/mt8196/thermal.c
+++ b/src/soc/mediatek/mt8196/thermal.c
@@ -43,6 +43,8 @@ static const struct lvts_thermal_controller lvts_tscpu_g_tc[LVTS_CONTROLLER_NUM]
 		.ts_number = 4,
 		.reboot_temperature = 118800,
 		.dominator_ts_idx = 0,
+		.reboot_msr_sram_idx = 0,
+		.has_reboot_temp_sram = true,
 		.speed = {
 			.group_interval_delay = 0x7fff,
 			.period_unit = 0x001,
@@ -57,6 +59,8 @@ static const struct lvts_thermal_controller lvts_tscpu_g_tc[LVTS_CONTROLLER_NUM]
 		.ts_number = 4,
 		.reboot_temperature = 118800,
 		.dominator_ts_idx = 0,
+		.reboot_msr_sram_idx = 1,
+		.has_reboot_temp_sram = false,
 		.speed = {
 			.group_interval_delay = 0x7fff,
 			.period_unit = 0x001,
@@ -543,6 +547,10 @@ static void lvts_set_tc_trigger_hw_protect(const struct lvts_thermal_controller
 		raw_high = MAX(raw_high, raw);
 	}
 
+	thermal_write_reboot_msr_sram(tc->reboot_msr_sram_idx, raw_high);
+	if (tc->has_reboot_temp_sram)
+		thermal_write_reboot_temp_sram(tc->reboot_temperature);
+
 	setbits32(&tc->regs->lvtsprotctl_0, 0x3FFF);
 	/* disable trigger SPM interrupt */
 	write32(&tc->regs->lvtsmonint_0, 0);
diff --git a/src/soc/mediatek/mt8196/thermal_sram.c b/src/soc/mediatek/mt8196/thermal_sram.c
index 5509792e4f..eb36bf478e 100644
--- a/src/soc/mediatek/mt8196/thermal_sram.c
+++ b/src/soc/mediatek/mt8196/thermal_sram.c
@@ -1,12 +1,16 @@
 /* SPDX-License-Identifier: GPL-2.0-only OR MIT */
 
 #include <arch/cache.h>
+#include <assert.h>
 #include <soc/thermal_internal.h>
 #include <string.h>
 
 /* SRAM for Thermal */
 #define THERMAL_SRAM_BASE		(_mcufw_reserved + 0x1000)
 #define THERMAL_SRAM_LEN		0x400
+#define THERMAL_REBOOT_TEMP_SRAM_OFFSET	0x39C
+#define THERMAL_REBOOT_MSR_SRAM_OFFSET	0x340
+#define THERMAL_REBOOT_MSR_SRAM_LEN	(6 * 4)
 
 static void thermal_cls_sram(void)
 {
@@ -59,3 +63,17 @@ void thermal_sram_init(void)
 	thermal_stat_cls_sram();
 	thermal_gpu_stat_cls_sram();
 }
+
+void thermal_write_reboot_temp_sram(uint32_t value)
+{
+	write32(THERMAL_SRAM_BASE + THERMAL_REBOOT_TEMP_SRAM_OFFSET, value);
+}
+
+void thermal_write_reboot_msr_sram(unsigned int idx, uint32_t value)
+{
+	unsigned int offset = 0;
+
+	assert((idx * 4) < THERMAL_REBOOT_MSR_SRAM_LEN);
+	offset = THERMAL_REBOOT_MSR_SRAM_OFFSET + idx * 4;
+	write32(THERMAL_SRAM_BASE + offset, value);
+}

From 7b36319fd9384935e94306b2c3203dccbb7a793f Mon Sep 17 00:00:00 2001
From: Subrata Banik <subratabanik@google.com>
Date: Thu, 6 Mar 2025 19:00:40 +0000
Subject: [PATCH 0301/3886] {drivers, lib}: Move low-battery user notification
 logic outside FSP

This patch refactors low-battery user notification logic (Kconfig,
APIs to check if low-battery rendering is required, low-battery
shutdown is required) outside FSP driver code to ensure in future
non-FSP platforms might still be able to leverage this feature/logics
to render the low-battery indicator icon during boot.

Specifically, it:

- Moves Kconfig options related to low-battery notifications from
  drivers/intel/fsp to lib/
- Relocates the low-battery check and shutdown APIs drivers/intel/fsp
  to bootsplash.h
* Adjusts the vendor driver to utilize the new APIs for low-battery
  rendering decisions.
* Drop the unwanted header file "fsp/api.h" from bmp_logo.c

This change avoids tight coupling of low-battery functionality to FSP,
promoting code reusability across platforms.

BUG=b:400738815
TEST=Able to build and boot google/brox.

Change-Id: Iaa730dac2bb4866183408b6390221f0bb8411a48
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86756
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
---
 src/drivers/intel/fsp2_0/Kconfig           | 49 ---------------------
 src/drivers/intel/fsp2_0/include/fsp/api.h | 14 ------
 src/drivers/intel/fsp2_0/memory_init.c     |  1 +
 src/include/bootsplash.h                   | 13 ++++++
 src/lib/Kconfig                            | 50 ++++++++++++++++++++++
 src/lib/bmp_logo.c                         |  1 -
 src/vendorcode/google/chromeos/battery.c   |  2 +-
 7 files changed, 65 insertions(+), 65 deletions(-)

diff --git a/src/drivers/intel/fsp2_0/Kconfig b/src/drivers/intel/fsp2_0/Kconfig
index ffe0778971..942591585d 100644
--- a/src/drivers/intel/fsp2_0/Kconfig
+++ b/src/drivers/intel/fsp2_0/Kconfig
@@ -475,53 +475,4 @@ config BUILDING_WITH_DEBUG_FSP
 	  Enable this option if you are using a debug build of the FSP (Firmware Support Package)
 	  in your project.
 
-config PLATFORM_HAS_LOW_BATTERY_INDICATOR
-	bool "Display low battery indicator"
-	depends on BMP_LOGO
-	help
-	  If enabled, this option displays a low battery indicator screen. This screen can be
-	  used to warn the user that the battery is low and that they should plug in the device.
-
-	  This option requires that the system have a display and that the BMP_LOGO option is
-	  enabled.
-
-config PLATFORM_LOW_BATTERY_SHUTDOWN_DELAY_SEC
-	int
-	default 5
-	depends on PLATFORM_HAS_LOW_BATTERY_INDICATOR
-	help
-	  Delay, in seconds, before system shutdown due to low battery.
-	  This delay allows the user to observe the low-battery indicator.
-	  The default value of 5 seconds aligns with standard user experience (UX) practices.
-	  Platforms may override this value based on specific product requirements.
-
-config HAVE_ESOL_SUPPORT_FOR_LOW_BATTERY_INDICATOR
-	bool
-	depends on FSP_UGOP_EARLY_SIGN_OF_LIFE || MAINBOARD_HAS_EARLY_LIBGFXINIT
-	help
-	  Enable low-battery indicator support in eSOL.
-
-	  This option should be selected if the eSOL feature (using either libgfxinit or FSP uGOP)
-	  supports displaying a low-battery indicator.
-
-	  Platforms selecting `MAINBOARD_HAS_EARLY_LIBGFXINIT` can default enable this option.
-
-	  For platforms using FSP uGOP, this option should only be enabled if uGOP has implemented
-	  the necessary low-battery handling. This allows platforms to control low-battery
-	  indicator support based on uGOP readiness.
-
-config PLATFORM_HAS_EARLY_LOW_BATTERY_INDICATOR
-	bool "Display low battery indicator in romstage"
-	depends on PLATFORM_HAS_LOW_BATTERY_INDICATOR && HAVE_ESOL_SUPPORT_FOR_LOW_BATTERY_INDICATOR
-	help
-	  If enabled, this option displays a low battery indicator during romstage (before memory
-	  is available) in text mode in the firmware and defer the firmware update. This screen
-	  can be used to warn the user that the battery is low and that they should plug in the
-	  device.
-
-config PLATFORM_LOW_BATTERY_INDICATOR_LOGO_PATH
-	string "Path to low battery logo file"
-	depends on PLATFORM_HAS_LOW_BATTERY_INDICATOR
-	default "3rdparty/blobs/mainboard/\$(MAINBOARDDIR)/low_battery.bmp"
-
 endif
diff --git a/src/drivers/intel/fsp2_0/include/fsp/api.h b/src/drivers/intel/fsp2_0/include/fsp/api.h
index d159b71e02..0cbefbe9ae 100644
--- a/src/drivers/intel/fsp2_0/include/fsp/api.h
+++ b/src/drivers/intel/fsp2_0/include/fsp/api.h
@@ -50,20 +50,6 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd);
 /* Callbacks for SoC/Mainboard specific overrides */
 void platform_fsp_memory_multi_phase_init_cb(uint32_t phase_index);
 void platform_fsp_silicon_multi_phase_init_cb(uint32_t phase_index);
-/*
- * Platform specific callbacks for power-off handling.
- *
- * These callbacks allow the platform to determine if a power-off is
- * necessary due to various reasons, such as low battery detection.
- *
- * Additionally, API to perform platform specific power-off
- */
-#if CONFIG(PLATFORM_HAS_LOW_BATTERY_INDICATOR)
-bool platform_is_low_battery_shutdown_needed(void);
-#else
-static inline bool platform_is_low_battery_shutdown_needed(void) { return false; }
-#endif
-
 /*
  * Displays an early shutdown notification to the user.
  *
diff --git a/src/drivers/intel/fsp2_0/memory_init.c b/src/drivers/intel/fsp2_0/memory_init.c
index 38627c6b06..f6945a2313 100644
--- a/src/drivers/intel/fsp2_0/memory_init.c
+++ b/src/drivers/intel/fsp2_0/memory_init.c
@@ -4,6 +4,7 @@
 #include <arch/stack_canary_breakpoint.h>
 #include <arch/symbols.h>
 #include <assert.h>
+#include <bootsplash.h>
 #include <cbfs.h>
 #include <cbmem.h>
 #include <cf9_reset.h>
diff --git a/src/include/bootsplash.h b/src/include/bootsplash.h
index 372e8c2062..7a57cd91f4 100644
--- a/src/include/bootsplash.h
+++ b/src/include/bootsplash.h
@@ -22,5 +22,18 @@ void set_bootsplash(unsigned char *framebuffer, unsigned int x_resolution,
 const char *bmp_logo_filename(void);
 void *bmp_load_logo(size_t *logo_size);
 void bmp_release_logo(void);
+/*
+ * Platform specific callbacks for power-off handling.
+ *
+ * These callbacks allow the platform to determine if a power-off is
+ * necessary due to various reasons, such as low battery detection.
+ *
+ * Additionally, API to perform platform specific power-off
+ */
+#if CONFIG(PLATFORM_HAS_LOW_BATTERY_INDICATOR)
+bool platform_is_low_battery_shutdown_needed(void);
+#else
+static inline bool platform_is_low_battery_shutdown_needed(void) { return false; }
+#endif
 
 #endif
diff --git a/src/lib/Kconfig b/src/lib/Kconfig
index dce3c44b5b..be3a19866f 100644
--- a/src/lib/Kconfig
+++ b/src/lib/Kconfig
@@ -204,6 +204,56 @@ config BMP_LOGO_FILE_NAME
 	depends on BMP_LOGO
 	default "3rdparty/blobs/mainboard/\$(MAINBOARDDIR)/logo.bmp"
 
+config HAVE_ESOL_SUPPORT_FOR_LOW_BATTERY_INDICATOR
+	bool
+	depends on FSP_UGOP_EARLY_SIGN_OF_LIFE || MAINBOARD_HAS_EARLY_LIBGFXINIT
+	help
+	  Enable low-battery indicator support in eSOL.
+
+	  This option should be selected if the eSOL feature (using either libgfxinit or FSP uGOP)
+	  supports displaying a low-battery indicator.
+
+	  Platforms selecting `MAINBOARD_HAS_EARLY_LIBGFXINIT` can default enable this option.
+
+	  For platforms using FSP uGOP, this option should only be enabled if uGOP has implemented
+	  the necessary low-battery handling. This allows platforms to control low-battery
+	  indicator support based on uGOP readiness.
+
+config PLATFORM_HAS_LOW_BATTERY_INDICATOR
+	bool "Display low battery indicator"
+	depends on BMP_LOGO
+	help
+	  If enabled, this option displays a low battery indicator screen. This screen can be
+	  used to warn the user that the battery is low and that they should plug in the device.
+
+	  This option requires that the system have a display and that the BMP_LOGO option is
+	  enabled.
+
+if PLATFORM_HAS_LOW_BATTERY_INDICATOR
+
+config PLATFORM_LOW_BATTERY_SHUTDOWN_DELAY_SEC
+	int
+	default 5
+	help
+	  Delay, in seconds, before system shutdown due to low battery.
+	  This delay allows the user to observe the low-battery indicator.
+	  The default value of 5 seconds aligns with standard user experience (UX) practices.
+	  Platforms may override this value based on specific product requirements.
+
+config PLATFORM_HAS_EARLY_LOW_BATTERY_INDICATOR
+	bool "Display low battery indicator in romstage"
+	depends on HAVE_ESOL_SUPPORT_FOR_LOW_BATTERY_INDICATOR
+	help
+	  If enabled, this option displays a low battery indicator during romstage (before memory
+	  is available) in text mode in the firmware and defer the firmware update. This screen
+	  can be used to warn the user that the battery is low and that they should plug in the
+	  device.
+
+config PLATFORM_LOW_BATTERY_INDICATOR_LOGO_PATH
+	string "Path to low battery logo file"
+	default "3rdparty/blobs/mainboard/\$(MAINBOARDDIR)/low_battery.bmp"
+endif
+
 endmenu
 
 config HAVE_EARLY_POWEROFF_SUPPORT
diff --git a/src/lib/bmp_logo.c b/src/lib/bmp_logo.c
index 6e3267ee87..bc636a6755 100644
--- a/src/lib/bmp_logo.c
+++ b/src/lib/bmp_logo.c
@@ -4,7 +4,6 @@
 #include <bootsplash.h>
 #include <cbfs.h>
 #include <cbmem.h>
-#include <fsp/api.h>
 #include <stdint.h>
 #include <vendorcode/google/chromeos/chromeos.h>
 
diff --git a/src/vendorcode/google/chromeos/battery.c b/src/vendorcode/google/chromeos/battery.c
index febc4dcc02..438098256b 100644
--- a/src/vendorcode/google/chromeos/battery.c
+++ b/src/vendorcode/google/chromeos/battery.c
@@ -1,7 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
 #include <ec/google/chromeec/ec.h>
-#include <fsp/api.h>
+#include <bootsplash.h>
 
 /*
  * Check if low battery shutdown is needed

From aadf6d59b2db77fe293bb303960dba8b093177b1 Mon Sep 17 00:00:00 2001
From: Angel Pons <th3fanbus@gmail.com>
Date: Sat, 7 May 2022 17:22:07 +0200
Subject: [PATCH 0302/3886] haswell NRI: Configure initial MC settings

Program initial memory controller settings. Many of these values will be
adjusted later during training.

Change-Id: If33846b51cb1bab5d0458fe626e13afb1bdc900e
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64186
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 .../intel/haswell/native_raminit/Makefile.mk  |   2 +
 .../haswell/native_raminit/configure_mc.c     | 835 ++++++++++++++++++
 .../haswell/native_raminit/raminit_main.c     |   2 +
 .../haswell/native_raminit/raminit_native.h   | 101 +++
 .../haswell/native_raminit/reg_structs.h      | 405 +++++++++
 .../haswell/native_raminit/timings_refresh.c  |  13 +
 .../intel/haswell/registers/mchbar.h          |  94 ++
 7 files changed, 1452 insertions(+)
 create mode 100644 src/northbridge/intel/haswell/native_raminit/configure_mc.c
 create mode 100644 src/northbridge/intel/haswell/native_raminit/reg_structs.h
 create mode 100644 src/northbridge/intel/haswell/native_raminit/timings_refresh.c

diff --git a/src/northbridge/intel/haswell/native_raminit/Makefile.mk b/src/northbridge/intel/haswell/native_raminit/Makefile.mk
index 2769e0bbb4..fc55277a65 100644
--- a/src/northbridge/intel/haswell/native_raminit/Makefile.mk
+++ b/src/northbridge/intel/haswell/native_raminit/Makefile.mk
@@ -1,8 +1,10 @@
 ## SPDX-License-Identifier: GPL-2.0-or-later
 
+romstage-y += configure_mc.c
 romstage-y += lookup_timings.c
 romstage-y += init_mpll.c
 romstage-y += io_comp_control.c
 romstage-y += raminit_main.c
 romstage-y += raminit_native.c
 romstage-y += spd_bitmunching.c
+romstage-y += timings_refresh.c
diff --git a/src/northbridge/intel/haswell/native_raminit/configure_mc.c b/src/northbridge/intel/haswell/native_raminit/configure_mc.c
new file mode 100644
index 0000000000..5562dbdf2e
--- /dev/null
+++ b/src/northbridge/intel/haswell/native_raminit/configure_mc.c
@@ -0,0 +1,835 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <assert.h>
+#include <commonlib/bsd/clamp.h>
+#include <console/console.h>
+#include <delay.h>
+#include <lib.h>
+#include <northbridge/intel/haswell/haswell.h>
+#include <string.h>
+#include <types.h>
+
+#include "raminit_native.h"
+
+static void program_misc_control(struct sysinfo *ctrl)
+{
+	if (!is_hsw_ult())
+		return;
+
+	const union ddr_scram_misc_control_reg ddr_scram_misc_ctrl = {
+		.ddr_no_ch_interleave = !ctrl->dq_pins_interleaved,
+		.lpddr_mode           = ctrl->lpddr,
+		.cke_mapping_ch0      = ctrl->lpddr ? ctrl->lpddr_cke_rank_map[0] : 0,
+		.cke_mapping_ch1      = ctrl->lpddr ? ctrl->lpddr_cke_rank_map[1] : 0,
+	};
+	mchbar_write32(DDR_SCRAM_MISC_CONTROL, ddr_scram_misc_ctrl.raw);
+}
+
+static void program_mrc_revision(void)
+{
+	mchbar_write32(MRC_REVISION, 0x01090000);	/* MRC 1.9.0 Build 0 */
+}
+
+static void program_ranks_used(struct sysinfo *ctrl)
+{
+	for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
+		mchbar_write8(MC_INIT_STATE_ch(channel), ctrl->rankmap[channel]);
+		if (!does_ch_exist(ctrl, channel)) {
+			mchbar_write32(DDR_CLK_ch_RANKS_USED(channel), 0);
+			mchbar_write32(DDR_CTL_ch_CTL_RANKS_USED(channel), 0);
+			mchbar_write32(DDR_CKE_ch_CTL_RANKS_USED(channel), 0);
+			continue;
+		}
+		uint32_t clk_ranks_used = ctrl->rankmap[channel];
+		if (ctrl->lpddr) {
+			/* With LPDDR, the clock usage goes by group instead */
+			clk_ranks_used = 0;
+			for (uint8_t group = 0; group < NUM_GROUPS; group++) {
+				if (ctrl->dq_byte_map[channel][CT_ITERATION_CLOCK][group])
+					clk_ranks_used |= BIT(group);
+			}
+		}
+		mchbar_write32(DDR_CLK_ch_RANKS_USED(channel), clk_ranks_used);
+
+		uint32_t ctl_ranks_used = ctrl->rankmap[channel];
+		if (is_hsw_ult()) {
+			/* Set ODT disable bits */
+			/** TODO: May need to do this after JEDEC reset/init **/
+			if (ctrl->lpddr && ctrl->lpddr_dram_odt)
+				ctl_ranks_used |= 2 << 4;	/* ODT is used on rank 0 */
+			else
+				ctl_ranks_used |= 3 << 4;
+		}
+		mchbar_write32(DDR_CTL_ch_CTL_RANKS_USED(channel), ctl_ranks_used);
+
+		uint32_t cke_ranks_used = ctrl->rankmap[channel];
+		if (ctrl->lpddr) {
+			/* Use CKE-to-rank mapping for LPDDR */
+			const uint8_t cke_rank_map = ctrl->lpddr_cke_rank_map[channel];
+			cke_ranks_used = 0;
+			for (uint8_t rank = 0; rank < NUM_SLOTRANKS; rank++) {
+				/* ULT only has 2 ranks per channel */
+				if (rank >= 2)
+					break;
+
+				if (!rank_in_ch(ctrl, rank, channel))
+					continue;
+
+				for (uint8_t cke = 0; cke < 4; cke++) {
+					if (rank == ((cke_rank_map >> cke) & 1))
+						cke_ranks_used |= BIT(cke);
+				}
+			}
+		}
+		mchbar_write32(DDR_CKE_ch_CTL_RANKS_USED(channel), cke_ranks_used);
+	}
+}
+
+static const uint8_t rxb_trad[2][5][4] = {
+	{	/* Vdd low */
+		/* 1067 MT/s,    1333 MT/s,    1600 MT/s,    1867 MT/s,    2133 MT/s, */
+		{4, 3, 3, 2}, {4, 4, 3, 2}, {5, 4, 3, 3}, {5, 4, 4, 3}, {5, 4, 4, 3},
+	},
+	{	/* Vdd hi */
+		/* 1067 MT/s,    1333 MT/s,    1600 MT/s,    1867 MT/s,    2133 MT/s, */
+		{4, 3, 3, 2}, {4, 4, 3, 2}, {5, 4, 3, 3}, {5, 4, 4, 3}, {4, 4, 3, 3},
+	},
+};
+
+static const uint8_t rxb_ultx[2][3][4] = {
+	{	/* Vdd low */
+		/* 1067 MT/s,    1333 MT/s,    1600 MT/s, */
+		{5, 6, 6, 5}, {5, 6, 6, 5}, {4, 6, 6, 6},
+	},
+	{	/* Vdd hi */
+		/* 1067 MT/s,    1333 MT/s,    1600 MT/s, */
+		{7, 6, 6, 5}, {7, 6, 6, 5}, {7, 6, 6, 6},
+	},
+};
+
+uint8_t get_rx_bias(const struct sysinfo *ctrl)
+{
+	const bool is_ult = is_hsw_ult();
+	const bool vddhi  = ctrl->vdd_mv > 1350;
+	const uint8_t max_rxf = is_ult ? ARRAY_SIZE(rxb_ultx[0]) : ARRAY_SIZE(rxb_trad[0]);
+	const uint8_t ref_clk = ctrl->base_freq == 133 ? 4 : 6;
+	const uint8_t rx_f    = clamp_s8(0, ctrl->multiplier - ref_clk, max_rxf - 1);
+	const uint8_t rx_cb   = mchbar_read32(DDR_CLK_CB_STATUS) & 0x3;
+	if (is_ult)
+		return rxb_ultx[vddhi][rx_f][rx_cb];
+	else
+		return rxb_trad[vddhi][rx_f][rx_cb];
+}
+
+static void program_ddr_data(struct sysinfo *ctrl, const bool dis_odt_static, const bool vddhi)
+{
+	const bool is_ult = is_hsw_ult();
+
+	for (uint8_t rank = 0; rank < NUM_SLOTRANKS; rank++) {
+		if (!does_rank_exist(ctrl, rank))
+			continue;
+
+		const union ddr_data_rx_train_rank_reg rx_train = {
+			.rcven = 64,
+			.dqs_p = 32,
+			.dqs_n = 32,
+		};
+		mchbar_write32(DDR_DATA_RX_TRAIN_RANK(rank), rx_train.raw);
+		mchbar_write32(DDR_DATA_RX_PER_BIT_RANK(rank), 0x88888888);
+
+		const union ddr_data_tx_train_rank_reg tx_train = {
+			.tx_eq     = TXEQFULLDRV | 11,
+			.dq_delay  = 96,
+			.dqs_delay = 64,
+		};
+		mchbar_write32(DDR_DATA_TX_TRAIN_RANK(rank), tx_train.raw);
+		mchbar_write32(DDR_DATA_TX_PER_BIT_RANK(rank), 0x88888888);
+
+		for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
+			for (uint8_t byte = 0; byte < ctrl->lanes; byte++) {
+				ctrl->tx_dq[channel][rank][byte] = tx_train.dq_delay;
+				ctrl->txdqs[channel][rank][byte] = tx_train.dqs_delay;
+				ctrl->tx_eq[channel][rank][byte] = tx_train.tx_eq;
+
+				ctrl->rcven[channel][rank][byte]  = rx_train.rcven;
+				ctrl->rxdqsp[channel][rank][byte] = rx_train.dqs_p;
+				ctrl->rxdqsn[channel][rank][byte] = rx_train.dqs_n;
+				ctrl->rx_eq[channel][rank][byte]  = rx_train.rx_eq;
+			}
+		}
+	}
+	mchbar_write32(DDR_DATA_TX_XTALK, 0);
+	mchbar_write32(DDR_DATA_RX_OFFSET_VDQ, 0x88888888);
+	mchbar_write32(DDR_DATA_OFFSET_TRAIN, 0);
+	mchbar_write32(DDR_DATA_OFFSET_COMP, 0);
+
+	const union ddr_data_control_0_reg data_control_0 = {
+		.internal_clocks_on = !is_ult,
+		.data_vccddq_hi     = vddhi,
+		.disable_odt_static = dis_odt_static,
+		.lpddr_mode         = ctrl->lpddr,
+		.odt_samp_extend_en = ctrl->lpddr,
+		.early_rleak_en     = ctrl->lpddr && ctrl->stepping >= STEPPING_C0,
+	};
+	mchbar_write32(DDR_DATA_CONTROL_0, data_control_0.raw);
+
+	const union ddr_data_control_1_reg data_control_1 = {
+		.dll_mask             = 1,
+		.rx_bias_ctl          = get_rx_bias(ctrl),
+		.odt_delay            = -2,
+		.odt_duration         = 7,
+		.sense_amp_delay      = -2,
+		.sense_amp_duration   = 7,
+	};
+	mchbar_write32(DDR_DATA_CONTROL_1, data_control_1.raw);
+
+	clear_data_offset_train_all(ctrl);
+
+	/* Stagger byte turn-on to reduce dI/dT */
+	const uint8_t byte_stagger[] = { 0, 4, 1, 5, 2, 6, 3, 7, 8 };
+	const uint8_t latency = 2 * ctrl->tAA - 6;
+	for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
+		if (!does_ch_exist(ctrl, channel))
+			continue;
+
+		union ddr_data_control_2_reg data_control_2 = {
+			.raw = 0,
+		};
+		if (is_ult) {
+			data_control_2.rx_dqs_amp_offset = 8;
+			data_control_2.rx_clk_stg_num    = 0x1f;
+			data_control_2.leaker_comp       = ctrl->lpddr ? 3 : 0;
+		}
+		for (uint8_t byte = 0; byte < ctrl->lanes; byte++) {
+			const uint8_t stg = latency * byte_stagger[byte] / ctrl->lanes;
+			data_control_2.rx_stagger_ctl = stg & 0x1f;
+			mchbar_write32(DQ_CONTROL_2(channel, byte), data_control_2.raw);
+			ctrl->data_offset_comp[channel][byte] = 0;
+			ctrl->dq_control_1[channel][byte] = data_control_1.raw;
+			ctrl->dq_control_2[channel][byte] = data_control_2.raw;
+		}
+		ctrl->dq_control_0[channel] = data_control_0.raw;
+	}
+}
+
+static void program_vsshi_control(struct sysinfo *ctrl, const uint16_t vsshi_mv)
+{
+	const uint32_t vsshi_control_reg = is_hsw_ult() ? 0x366c : 0x306c;
+	const union ddr_comp_vsshi_control_reg ddr_vsshi_control = {
+		.vsshi_target    = (vsshi_mv * 192) / ctrl->vdd_mv - 20,
+		.hi_bw_divider   = 1,
+		.lo_bw_divider   = 1,
+		.bw_error        = 2,
+		.panic_driver_en = 1,
+		.panic_voltage   = 24 / 8, /* Voltage in 8mV steps */
+		.gain_boost      = 1,
+	};
+	mchbar_write32(vsshi_control_reg, ddr_vsshi_control.raw);
+	mchbar_write32(DDR_COMP_VSSHI_CONTROL, ddr_vsshi_control.raw);
+}
+
+static void calc_vt_slope_code(const uint16_t slope, uint8_t *best_a, uint8_t *best_b)
+{
+	const int16_t coding[] = {0, -125, -62, -31, 250, 125, 62, 31};
+	*best_a = 0;
+	*best_b = 0;
+	int16_t best_err = slope;
+	for (uint8_t b = 0; b < ARRAY_SIZE(coding); b++) {
+		for (uint8_t a = b; a < ARRAY_SIZE(coding); a++) {
+			int16_t	error = slope - (coding[a] + coding[b]);
+			if (error < 0)
+				error = -error;
+
+			if (error < best_err) {
+				best_err = error;
+				*best_a = a;
+				*best_b = b;
+			}
+		}
+	}
+}
+
+static void program_dimm_vref(struct sysinfo *ctrl, const uint16_t vccio_mv, const bool vddhi)
+{
+	const bool is_ult = is_hsw_ult();
+
+	/* Static values for ULT */
+	uint8_t vt_slope_a = 4;
+	uint8_t vt_slope_b = 0;
+	if (!is_ult) {
+		/* On non-ULT, compute best slope code */
+		const uint16_t vt_slope = 1500 * vccio_mv / ctrl->vdd_mv - 1000;
+		calc_vt_slope_code(vt_slope, &vt_slope_a, &vt_slope_b);
+	}
+	const union ddr_data_vref_control_reg ddr_vref_control = {
+		.hi_bw_divider  = is_ult ? 0 : 3,
+		.lo_bw_divider  = 3,
+		.sample_divider = is_ult ? 1 : 3,
+		.slow_bw_error  = 1,
+		.hi_bw_enable   = 1,
+		.vt_slope_b     = vt_slope_b,
+		.vt_slope_a     = vt_slope_a,
+		.vt_offset      = 0,
+	};
+	mchbar_write32(is_ult ? 0xf68 : 0xf6c, ddr_vref_control.raw); /* Use CH1 byte 7 */
+
+	const union ddr_data_vref_adjust_reg ddr_vref_adjust = {
+		.en_dimm_vref_ca  = 1,
+		.en_dimm_vref_ch0 = 1,
+		.en_dimm_vref_ch1 = 1,
+		.vccddq_hi_qnnn_h = vddhi,
+		.hi_z_timer_ctrl  = 3,
+	};
+	ctrl->dimm_vref = ddr_vref_adjust;
+	mchbar_write32(DDR_DATA_VREF_ADJUST, ddr_vref_adjust.raw);
+}
+
+static uint32_t pi_code(const uint32_t code)
+{
+	return code << 21 | code << 14 | code << 7 | code << 0;
+}
+
+static void program_ddr_ca(struct sysinfo *ctrl, const bool vddhi)
+{
+	for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
+		if (!does_ch_exist(ctrl, channel))
+			continue;
+
+		const union ddr_clk_controls_reg ddr_clk_controls = {
+			.dll_mask   = 1,
+			.vccddq_hi  = vddhi,
+			.lpddr_mode = ctrl->lpddr,
+		};
+		mchbar_write32(DDR_CLK_ch_CONTROLS(channel), ddr_clk_controls.raw);
+
+		const union ddr_cmd_controls_reg ddr_cmd_controls = {
+			.dll_mask         = 1,
+			.vccddq_hi        = vddhi,
+			.lpddr_mode       = ctrl->lpddr,
+			.early_weak_drive = 3,
+			.cmd_tx_eq        = 1,
+		};
+		mchbar_write32(DDR_CMD_ch_CONTROLS(channel), ddr_cmd_controls.raw);
+
+		const union ddr_cke_ctl_controls_reg ddr_cke_controls = {
+			.dll_mask         = 1,
+			.vccddq_hi        = vddhi,
+			.lpddr_mode       = ctrl->lpddr,
+			.early_weak_drive = 3,
+			.cmd_tx_eq        = 1,
+			.ctl_tx_eq        = 1,
+			.ctl_sr_drv       = 2,
+		};
+		mchbar_write32(DDR_CKE_ch_CTL_CONTROLS(channel), ddr_cke_controls.raw);
+
+		const union ddr_cke_ctl_controls_reg ddr_ctl_controls = {
+			.dll_mask       = 1,
+			.vccddq_hi      = vddhi,
+			.lpddr_mode     = ctrl->lpddr,
+			.ctl_tx_eq      = 1,
+			.ctl_sr_drv     = 2,
+			.la_drv_en_ovrd = 1,	/* Must be set on ULT */
+		};
+		mchbar_write32(DDR_CTL_ch_CTL_CONTROLS(channel), ddr_ctl_controls.raw);
+
+		const uint8_t cmd_pi = ctrl->lpddr ? 96 : 64;
+		mchbar_write32(DDR_CMD_ch_PI_CODING(channel), pi_code(cmd_pi));
+		mchbar_write32(DDR_CKE_ch_CMD_PI_CODING(channel), pi_code(cmd_pi));
+		mchbar_write32(DDR_CKE_CTL_ch_CTL_PI_CODING(channel), pi_code(64));
+		mchbar_write32(DDR_CLK_ch_PI_CODING(channel), pi_code(64));
+
+		mchbar_write32(DDR_CMD_ch_COMP_OFFSET(channel), 0);
+		mchbar_write32(DDR_CLK_ch_COMP_OFFSET(channel), 0);
+		mchbar_write32(DDR_CKE_CTL_ch_CTL_COMP_OFFSET(channel), 0);
+
+		for (uint8_t group = 0; group < NUM_GROUPS; group++) {
+			ctrl->cke_cmd_pi_code[channel][group] = cmd_pi;
+			ctrl->cmd_north_pi_code[channel][group] = cmd_pi;
+			ctrl->cmd_south_pi_code[channel][group] = cmd_pi;
+		}
+		for (uint8_t rank = 0; rank < NUM_SLOTRANKS; rank++) {
+			ctrl->clk_pi_code[channel][rank] = 64;
+			ctrl->ctl_pi_code[channel][rank] = 64;
+		}
+	}
+}
+
+enum {
+	RCOMP_RD_ODT = 0,
+	RCOMP_WR_DS_DQ,
+	RCOMP_WR_DS_CMD,
+	RCOMP_WR_DS_CTL,
+	RCOMP_WR_DS_CLK,
+	RCOMP_MAX_CODES,
+};
+
+struct rcomp_info {
+	uint8_t resistor;
+	uint8_t sz_steps;
+	uint8_t target_r;
+	int8_t result;
+};
+
+static void program_rcomp_vref(struct sysinfo *ctrl, const bool dis_odt_static)
+{
+	const bool is_ult = is_hsw_ult();
+	/*
+	 * +-------------------------------+
+	 * | Rcomp resistor values in ohms |
+	 * +-----------+------+------+-----+
+	 * | Ball name | Trad | ULTX | Use |
+	 * +-----------+------+------+-----+
+	 * | SM_RCOMP0 | 100  | 200  | CMD |
+	 * | SM_RCOMP1 |  75  | 120  | DQ  |
+	 * | SM_RCOMP2 | 100  | 100  | ODT |
+	 * +-----------+------+------+-----+
+	 */
+	struct rcomp_info rcomp_cfg[RCOMP_MAX_CODES] = {
+		[RCOMP_RD_ODT] = {
+			.resistor = 50,
+			.sz_steps = 96,
+			.target_r = 50,
+		},
+		[RCOMP_WR_DS_DQ] = {
+			.resistor = 25,
+			.sz_steps = 64,
+			.target_r = 33,
+		},
+		[RCOMP_WR_DS_CMD] = {
+			.resistor = 20,
+			.sz_steps = 64,
+			.target_r = 20,
+		},
+		[RCOMP_WR_DS_CTL] = {
+			.resistor = 20,
+			.sz_steps = 64,
+			.target_r = 20,
+		},
+		[RCOMP_WR_DS_CLK] = {
+			.resistor = 25,
+			.sz_steps = 64,
+			.target_r = 29,
+		},
+	};
+	if (is_ult) {
+		rcomp_cfg[RCOMP_WR_DS_DQ].resistor = 40;
+		rcomp_cfg[RCOMP_WR_DS_DQ].target_r = 40;
+		rcomp_cfg[RCOMP_WR_DS_CLK].resistor = 40;
+	} else if (ctrl->dpc[0] == 2 || ctrl->dpc[1] == 2) {
+		rcomp_cfg[RCOMP_RD_ODT].target_r = 60;
+	}
+	for (uint8_t i = 0; i < RCOMP_MAX_CODES; i++) {
+		struct rcomp_info *const r = &rcomp_cfg[i];
+		const int32_t div = 2 * (r->resistor + r->target_r);
+		assert(div);
+		const int32_t vref = (r->sz_steps * (r->resistor - r->target_r)) / div;
+
+		/* DqOdt is 5 bits wide, the other Rcomp targets are 4 bits wide */
+		const int8_t comp_limit = i == RCOMP_RD_ODT ? 16 : 8;
+		r->result = clamp_s32(-comp_limit, vref, comp_limit - 1);
+	}
+	const union ddr_comp_ctl_0_reg ddr_comp_ctl_0 = {
+		.disable_odt_static = dis_odt_static,
+		.dq_drv_vref        = rcomp_cfg[RCOMP_WR_DS_DQ].result,
+		.dq_odt_vref        = rcomp_cfg[RCOMP_RD_ODT].result,
+		.cmd_drv_vref       = rcomp_cfg[RCOMP_WR_DS_CMD].result,
+		.ctl_drv_vref       = rcomp_cfg[RCOMP_WR_DS_CTL].result,
+		.clk_drv_vref       = rcomp_cfg[RCOMP_WR_DS_CLK].result,
+	};
+	ctrl->comp_ctl_0 = ddr_comp_ctl_0;
+	mchbar_write32(DDR_COMP_CTL_0, ctrl->comp_ctl_0.raw);
+}
+
+enum {
+	SCOMP_DQ = 0,
+	SCOMP_CMD,
+	SCOMP_CTL,
+	SCOMP_CLK,
+	SCOMP_MAX_CODES,
+};
+
+static void program_slew_rates(struct sysinfo *ctrl, const bool vddhi)
+{
+	const uint8_t min_cycle_delay[SCOMP_MAX_CODES] = { 46, 70, 70, 46 };
+	uint8_t buffer_stage_delay_ps[SCOMP_MAX_CODES] = { 59, 53, 53, 53 };
+	uint16_t comp_slew_rate_codes[SCOMP_MAX_CODES];
+
+	/* CMD Slew Rate = 1.8 for 2N */
+	if (ctrl->tCMD == 2)
+		buffer_stage_delay_ps[SCOMP_CMD] = 89;
+
+	/* CMD Slew Rate = 4 V/ns for double-pumped CMD bus */
+	if (ctrl->lpddr)
+		buffer_stage_delay_ps[SCOMP_CMD] = 63;
+
+	for (uint8_t i = 0; i < SCOMP_MAX_CODES; i++) {
+		uint16_t stages = DIV_ROUND_CLOSEST(ctrl->qclkps, buffer_stage_delay_ps[i]);
+		if (stages < 5)
+			stages = 5;
+
+		bool dll_pc = buffer_stage_delay_ps[i] < min_cycle_delay[i] || stages > 16;
+
+		/* Lock DLL... */
+		if (dll_pc)
+			comp_slew_rate_codes[i] = stages / 2 - 1;        /* to a phase */
+		else
+			comp_slew_rate_codes[i] = (stages - 1) | BIT(4); /* to a cycle */
+	}
+	union ddr_comp_ctl_1_reg ddr_comp_ctl_1 = {
+		.dq_scomp       = comp_slew_rate_codes[SCOMP_DQ],
+		.cmd_scomp      = comp_slew_rate_codes[SCOMP_CMD],
+		.ctl_scomp      = comp_slew_rate_codes[SCOMP_CTL],
+		.clk_scomp      = comp_slew_rate_codes[SCOMP_CLK],
+		.vccddq_hi      = vddhi,
+	};
+	ctrl->comp_ctl_1 = ddr_comp_ctl_1;
+	mchbar_write32(DDR_COMP_CTL_1, ctrl->comp_ctl_1.raw);
+}
+
+static uint32_t ln_x100(const uint32_t input_x100)
+{
+	uint32_t val = input_x100;
+	uint32_t ret = 0;
+	while (val > 271) {
+		val = (val * 1000) / 2718;
+		ret += 100;
+	}
+	return ret + (-16 * val * val + 11578 * val - 978860) / 10000;
+}
+
+static uint32_t compute_vsshi_vref(struct sysinfo *ctrl, const uint32_t vsshi_tgt, bool up)
+{
+	const uint32_t delta = 15;
+	const uint32_t c_die_vsshi = 2000;
+	const uint32_t r_cmd_ref = 100 * 10;
+	const uint32_t offset = up ? 64 : 0;
+	const uint32_t ln_vsshi = ln_x100((100 * vsshi_tgt) / (vsshi_tgt - delta));
+	const uint32_t r_target = (ctrl->qclkps * 2000) / (c_die_vsshi * ln_vsshi);
+	const uint32_t r_dividend = 128 * (up ? r_cmd_ref : r_target);
+	return r_dividend / (r_cmd_ref + r_target) - offset;
+}
+
+static void program_vsshi(struct sysinfo *ctrl, const uint16_t vccio_mv, const uint16_t vsshi)
+{
+	const uint16_t vsshi_down = vsshi + 24; /* Panic threshold of 24 mV */
+	const uint16_t vsshi_up = vccio_mv - vsshi_down;
+	const union ddr_comp_vsshi_reg ddr_comp_vsshi = {
+		.panic_drv_down_vref = compute_vsshi_vref(ctrl, vsshi_down, false),
+		.panic_drv_up_vref   = compute_vsshi_vref(ctrl, vsshi_up, true),
+		.vt_offset           = 128 * 450 / vccio_mv / 2,
+		.vt_slope_a          = 4,
+	};
+	mchbar_write32(DDR_COMP_VSSHI, ddr_comp_vsshi.raw);
+}
+
+static void program_misc(struct sysinfo *ctrl)
+{
+	ctrl->misc_control_0.raw = mchbar_read32(DDR_SCRAM_MISC_CONTROL);
+	ctrl->misc_control_0.weaklock_latency = 12;
+	ctrl->misc_control_0.wl_sleep_cycles  =  5;
+	ctrl->misc_control_0.wl_wake_cycles   =  2;
+	mchbar_write32(DDR_SCRAM_MISC_CONTROL, ctrl->misc_control_0.raw);
+	for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
+		/* Keep scrambling disabled for training */
+		mchbar_write32(DDR_SCRAMBLE_ch(channel), 0);
+	}
+}
+
+/* Very weird, application-specific function */
+static void override_comp(uint32_t value, uint32_t width, uint32_t shift, uint32_t offset)
+{
+	const uint32_t mask = (1 << width) - 1;
+	uint32_t reg32 = mchbar_read32(offset);
+	reg32 &= ~(mask << shift);
+	reg32 |= (value << shift);
+	mchbar_write32(offset, reg32);
+}
+
+static void program_ls_comp(struct sysinfo *ctrl)
+{
+	/* Disable periodic COMP */
+	const union pcu_comp_reg m_comp = {
+		.comp_disable  = 1,
+		.comp_interval = COMP_INT,
+		.comp_force    = 1,
+	};
+	mchbar_write32(M_COMP, m_comp.raw);
+	udelay(10);
+
+	/* Override level shifter compensation */
+	const uint32_t ls_comp = 2;
+	override_comp(ls_comp, 3, 28, DDR_DATA_RCOMP_DATA_1);
+	override_comp(ls_comp, 3, 24, DDR_CMD_COMP);
+	override_comp(ls_comp, 3, 24, DDR_CKE_CTL_COMP);
+	override_comp(ls_comp, 3, 23, DDR_CLK_COMP);
+	override_comp(ls_comp, 3, 28, DDR_COMP_DATA_COMP_1);
+	override_comp(ls_comp, 3, 24, DDR_COMP_CMD_COMP);
+	override_comp(ls_comp, 4, 24, DDR_COMP_CTL_COMP);
+	override_comp(ls_comp, 4, 23, DDR_COMP_CLK_COMP);
+	override_comp(ls_comp, 3, 24, DDR_COMP_OVERRIDE);
+
+	/* Manually update the COMP values */
+	union ddr_scram_misc_control_reg ddr_scram_misc_ctrl = ctrl->misc_control_0;
+	ddr_scram_misc_ctrl.force_comp_update = 1;
+	mchbar_write32(DDR_SCRAM_MISC_CONTROL, ddr_scram_misc_ctrl.raw);
+
+	/* Use a fixed offset between ODT Up/Dn */
+	const union ddr_comp_data_comp_1_reg data_comp_1 = {
+		.raw = mchbar_read32(DDR_COMP_DATA_COMP_1),
+	};
+	const uint32_t odt_offset = data_comp_1.rcomp_odt_down - data_comp_1.rcomp_odt_up;
+	ctrl->comp_ctl_0.odt_up_down_off  = odt_offset;
+	ctrl->comp_ctl_0.fixed_odt_offset = 1;
+	mchbar_write32(DDR_COMP_CTL_0, ctrl->comp_ctl_0.raw);
+}
+
+/** TODO: Deduplicate PCODE stuff, it's already implemented in CPU code **/
+static bool pcode_ready(void)
+{
+	const unsigned int delay_step = 10;
+	for (unsigned int i = 0; i < 1000; i += delay_step) {
+		if (!(mchbar_read32(BIOS_MAILBOX_INTERFACE) & MAILBOX_RUN_BUSY))
+			return true;
+
+		udelay(delay_step);
+	};
+	return false;
+}
+
+static uint32_t pcode_mailbox_read(const uint32_t command)
+{
+	if (!pcode_ready()) {
+		printk(BIOS_ERR, "PCODE: mailbox timeout on wait ready\n");
+		return 0;
+	}
+	mchbar_write32(BIOS_MAILBOX_INTERFACE, command | MAILBOX_RUN_BUSY);
+	if (!pcode_ready()) {
+		printk(BIOS_ERR, "PCODE: mailbox timeout on completion\n");
+		return 0;
+	}
+	return mchbar_read32(BIOS_MAILBOX_DATA);
+}
+
+static int pcode_mailbox_write(const uint32_t command, const uint32_t data)
+{
+	if (!pcode_ready()) {
+		printk(BIOS_ERR, "PCODE: mailbox timeout on wait ready\n");
+		return -1;
+	}
+	mchbar_write32(BIOS_MAILBOX_DATA, data);
+	mchbar_write32(BIOS_MAILBOX_INTERFACE, command | MAILBOX_RUN_BUSY);
+	if (!pcode_ready()) {
+		printk(BIOS_ERR, "PCODE: mailbox timeout on completion\n");
+		return -1;
+	}
+	return 0;
+}
+
+static void enable_2x_refresh(struct sysinfo *ctrl)
+{
+	if (!CONFIG(ENABLE_DDR_2X_REFRESH)) {
+		return;
+	}
+
+	printk(BIOS_DEBUG, "Enabling 2x Refresh\n");
+	const bool asr = ctrl->flags.asr;
+	const bool lpddr = ctrl->lpddr;
+
+	/* Mutually exclusive */
+	assert(!asr || !lpddr);
+	if (!asr) {
+		uint32_t desired_cfg = 0;
+		desired_cfg |= BIT(0);	/* Enable 2x refresh */
+		desired_cfg |= BIT(31);	/* Lock */
+		if (lpddr) {
+			desired_cfg |= 4 << 1;	/* LPDDR MR4 1/2 tREFI */
+		}
+		uint32_t reg32 = pcode_mailbox_read(MAILBOX_BIOS_CMD_READ_DDR_2X_REFRESH);
+		if (reg32 & BIT(31)) {
+			/* Locked, check if programmed correctly */
+			const uint32_t current_cfg = reg32;
+			if (current_cfg != desired_cfg) {
+				printk(BIOS_ERR,
+					"Mailbox 2x Refresh locked with wrong values: %x != %x",
+					current_cfg, desired_cfg);
+			}
+		} else {
+			/* Not locked, program desired value */
+			reg32 |= desired_cfg;
+			if (pcode_mailbox_write(MAILBOX_BIOS_CMD_WRITE_DDR_2X_REFRESH, reg32)) {
+				printk(BIOS_ERR, "Could not enable Mailbox 2x Refresh\n");
+			}
+		}
+		if (!lpddr) {
+			return;
+		}
+	}
+	assert(asr || lpddr);
+	uint16_t refi_reduction = 50;
+	if (lpddr) {
+		refi_reduction = 97;
+		mchbar_clrbits32(PCU_DDR_PTM_CTL, 1 << 7); /* DISABLE_DRAM_TS */
+	}
+	/* tREFI is saved in cache, so only update it in cold boots */
+	if (ctrl->bootmode == BOOTMODE_COLD) {
+		ctrl->tREFI *= refi_reduction;
+		ctrl->tREFI /= 100;
+	}
+}
+
+static void set_pcu_ddr_voltage(const uint16_t vdd_mv)
+{
+	/** TODO: Handle other voltages? **/
+	uint32_t pcu_ddr_voltage;
+	switch (vdd_mv) {
+	case 1200:
+		pcu_ddr_voltage = 3;
+		break;
+	case 1350:
+		pcu_ddr_voltage = 1;
+		break;
+	default:
+	case 1500:
+		pcu_ddr_voltage = 0;
+		break;
+	}
+	/* Set bits 0..2 */
+	mchbar_write32(PCU_DDR_VOLTAGE, pcu_ddr_voltage);
+}
+
+static void program_scheduler(struct sysinfo *ctrl)
+{
+	/*
+	 * ZQ calibration needs to be serialized for LPDDR3. Otherwise,
+	 * the processor issues LPDDR3 ZQ calibration in parallel when
+	 * exiting Package C7 or deeper. This causes problems for dual
+	 * and quad die packages since all ranks share the same ZQ pin.
+	 *
+	 * Erratum HSM94: LPDDR3 ZQ Calibration Following Deep Package
+	 * C-state Exit May Lead to Unpredictable System Behavior
+	 */
+	const union mcscheds_cbit_reg mcscheds_cbit = {
+		.dis_write_gap = 1,
+		.dis_odt       = is_hsw_ult() && !(ctrl->lpddr && ctrl->lpddr_dram_odt),
+		.serialize_zq  = ctrl->lpddr,
+	};
+	mchbar_write32(MCSCHEDS_CBIT, mcscheds_cbit.raw);
+	mchbar_write32(MCMNTS_SC_WDBWM, 0x553c3038);
+	if (ctrl->lpddr) {
+		for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
+			if (!does_ch_exist(ctrl, channel))
+				continue;
+
+			union mcmain_command_rate_limit_reg cmd_rate_limit = {
+				.raw = mchbar_read32(COMMAND_RATE_LIMIT_ch(channel)),
+			};
+			cmd_rate_limit.enable_cmd_limit = 1;
+			cmd_rate_limit.cmd_rate_limit   = 3;
+			mchbar_write32(COMMAND_RATE_LIMIT_ch(channel), cmd_rate_limit.raw);
+		}
+	}
+}
+
+static uint8_t biggest_channel(const struct sysinfo *const ctrl)
+{
+	_Static_assert(NUM_CHANNELS == 2, "Code assumes exactly two channels");
+	return !!(ctrl->channel_size_mb[0] < ctrl->channel_size_mb[1]);
+}
+
+static void dram_zones(struct sysinfo *ctrl)
+{
+	/** TODO: Activate channel hash here, if enabled **/
+	const uint8_t biggest = biggest_channel(ctrl);
+	const uint8_t smaller = !biggest;
+
+	/** TODO: Use stacked mode if Memory Trace is enabled **/
+	const union mad_chnl_reg mad_channel = {
+		.ch_a       = biggest,
+		.ch_b       = smaller,
+		.ch_c       = 2,
+		.lpddr_mode = ctrl->lpddr,
+	};
+	mchbar_write32(MAD_CHNL, mad_channel.raw);
+
+	const uint8_t channel_b_zone_size = ctrl->channel_size_mb[smaller] / 256;
+	const union mad_zr_reg mad_zr = {
+		.ch_b_double = channel_b_zone_size * 2,
+		.ch_b_single = channel_b_zone_size,
+	};
+	mchbar_write32(MAD_ZR, mad_zr.raw);
+}
+
+static uint8_t biggest_dimm(const struct raminit_dimm_info *dimms)
+{
+	_Static_assert(NUM_SLOTS <= 2, "Code assumes at most two DIMMs per channel.");
+	if (NUM_SLOTS == 1)
+		return 0;
+
+	return !!(dimms[0].data.size_mb < dimms[1].data.size_mb);
+}
+
+static void dram_dimm_mapping(struct sysinfo *ctrl)
+{
+	for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
+		if (!does_ch_exist(ctrl, channel)) {
+			const union mad_dimm_reg mad_dimm = {
+				.rank_interleave = 1,
+				.enh_interleave  = 1,
+			};
+			mchbar_write32(MAD_DIMM(channel), mad_dimm.raw);
+			continue;
+		}
+		const uint8_t biggest = biggest_dimm(ctrl->dimms[channel]);
+		const uint8_t smaller = !biggest;
+		const struct dimm_attr_ddr3_st *dimm_a = &ctrl->dimms[channel][biggest].data;
+		const struct dimm_attr_ddr3_st *dimm_b = &ctrl->dimms[channel][smaller].data;
+		union mad_dimm_reg mad_dimm = {
+			.dimm_a_size     = dimm_a->size_mb / 256,
+			.dimm_b_size     = dimm_b->size_mb / 256,
+			.dimm_a_sel      = biggest,
+			.dimm_a_ranks    = dimm_a->ranks == 2,
+			.dimm_b_ranks    = dimm_b->ranks == 2,
+			.dimm_a_width    = dimm_a->width == 16,
+			.dimm_b_width    = dimm_b->width == 16,
+			.rank_interleave = 1,
+			.enh_interleave  = 1,
+			.ecc_mode        = 0,	/* Do not enable ECC yet */
+		};
+		if (is_hsw_ult())
+			mad_dimm.dimm_b_width = mad_dimm.dimm_a_width;
+
+		mchbar_write32(MAD_DIMM(channel), mad_dimm.raw);
+		if (ctrl->lpddr)
+			die("%s: Missing LPDDR support (LPDDR_MR_PARAMS)\n", __func__);
+	}
+}
+
+enum raminit_status configure_mc(struct sysinfo *ctrl)
+{
+	const uint16_t vccio_mv = 1000;
+	const uint16_t vsshi_mv = ctrl->vdd_mv - 950;
+	const bool dis_odt_static = is_hsw_ult(); /* Disable static ODT legs on ULT */
+	const bool vddhi = ctrl->vdd_mv > 1350;
+
+	program_misc_control(ctrl);
+	program_mrc_revision();
+	program_ranks_used(ctrl);
+	program_ddr_data(ctrl, dis_odt_static, vddhi);
+	program_vsshi_control(ctrl, vsshi_mv);
+	program_dimm_vref(ctrl, vccio_mv, vddhi);
+	program_ddr_ca(ctrl, vddhi);
+	program_rcomp_vref(ctrl, dis_odt_static);
+	program_slew_rates(ctrl, vddhi);
+	program_vsshi(ctrl, vccio_mv, vsshi_mv);
+	program_misc(ctrl);
+	program_ls_comp(ctrl);
+	enable_2x_refresh(ctrl);
+	set_pcu_ddr_voltage(ctrl->vdd_mv);
+	configure_timings(ctrl);
+	configure_refresh(ctrl);
+	program_scheduler(ctrl);
+	dram_zones(ctrl);
+	dram_dimm_mapping(ctrl);
+
+	return RAMINIT_STATUS_SUCCESS;
+}
diff --git a/src/northbridge/intel/haswell/native_raminit/raminit_main.c b/src/northbridge/intel/haswell/native_raminit/raminit_main.c
index 28a7895ce3..a13ae5641e 100644
--- a/src/northbridge/intel/haswell/native_raminit/raminit_main.c
+++ b/src/northbridge/intel/haswell/native_raminit/raminit_main.c
@@ -23,6 +23,7 @@ static const struct task_entry cold_boot[] = {
 	{ collect_spd_info,                                       true, "PROCSPD",    },
 	{ initialise_mpll,                                        true, "INITMPLL",   },
 	{ convert_timings,                                        true, "CONVTIM",    },
+	{ configure_mc,                                           true, "CONFMC",     },
 };
 
 /* Return a generic stepping value to make stepping checks simpler */
@@ -54,6 +55,7 @@ static void initialize_ctrl(struct sysinfo *ctrl)
 
 	ctrl->cpu = cpu_get_cpuid();
 	ctrl->stepping = get_stepping(ctrl->cpu);
+	ctrl->vdd_mv = is_hsw_ult() ? 1350 : 1500; /** FIXME: Hardcoded, does it matter? **/
 	ctrl->dq_pins_interleaved = cfg->dq_pins_interleaved;
 	ctrl->bootmode = bootmode;
 }
diff --git a/src/northbridge/intel/haswell/native_raminit/raminit_native.h b/src/northbridge/intel/haswell/native_raminit/raminit_native.h
index e0ebd3a2a7..fffa6d5450 100644
--- a/src/northbridge/intel/haswell/native_raminit/raminit_native.h
+++ b/src/northbridge/intel/haswell/native_raminit/raminit_native.h
@@ -3,16 +3,41 @@
 #ifndef HASWELL_RAMINIT_NATIVE_H
 #define HASWELL_RAMINIT_NATIVE_H
 
+#include <assert.h>
 #include <device/dram/ddr3.h>
 #include <northbridge/intel/haswell/haswell.h>
+#include <string.h>
+#include <types.h>
+
+#include "reg_structs.h"
 
 /** TODO (Angel): Remove this after in-review patches are submitted **/
 #define SPD_LEN SPD_SIZE_MAX_DDR3
 
+/* Each channel has 4 ranks, spread across 2 slots */
+#define NUM_SLOTRANKS		4
+
+#define NUM_GROUPS		2
+
 /* 8 data lanes + 1 ECC lane */
 #define NUM_LANES		9
 #define NUM_LANES_NO_ECC	8
 
+#define COMP_INT		10
+
+/* Always use 12 legs for emphasis (not trained) */
+#define TXEQFULLDRV		(3 << 4)
+
+enum command_training_iteration {
+	CT_ITERATION_CLOCK = 0,
+	CT_ITERATION_CMD_NORTH,
+	CT_ITERATION_CMD_SOUTH,
+	CT_ITERATION_CKE,
+	CT_ITERATION_CTL,
+	CT_ITERATION_CMD_VREF,
+	MAX_CT_ITERATION,
+};
+
 enum raminit_boot_mode {
 	BOOTMODE_COLD,
 	BOOTMODE_WARM,
@@ -58,6 +83,9 @@ struct sysinfo {
 	 * LPDDR-specific functions have stubs which will halt upon execution.
 	 */
 	bool lpddr;
+	bool lpddr_dram_odt;
+	uint8_t lpddr_cke_rank_map[NUM_CHANNELS];
+	uint8_t dq_byte_map[NUM_CHANNELS][MAX_CT_ITERATION][2];
 
 	struct raminit_dimm_info dimms[NUM_CHANNELS][NUM_SLOTS];
 	union dimm_flags_ddr3_st flags;
@@ -94,16 +122,89 @@ struct sysinfo {
 	uint32_t mem_clock_mhz;
 	uint32_t mem_clock_fs;		/* Memory clock period in femtoseconds */
 	uint32_t qclkps;		/* Quadrature clock period in picoseconds */
+
+	uint16_t vdd_mv;
+
+	union ddr_scram_misc_control_reg misc_control_0;
+
+	union ddr_comp_ctl_0_reg comp_ctl_0;
+	union ddr_comp_ctl_1_reg comp_ctl_1;
+
+	union ddr_data_vref_adjust_reg dimm_vref;
+
+	uint32_t data_offset_train[NUM_CHANNELS][NUM_LANES];
+	uint32_t data_offset_comp[NUM_CHANNELS][NUM_LANES];
+
+	uint32_t dq_control_0[NUM_CHANNELS];
+	uint32_t dq_control_1[NUM_CHANNELS][NUM_LANES];
+	uint32_t dq_control_2[NUM_CHANNELS][NUM_LANES];
+
+	uint16_t tx_dq[NUM_CHANNELS][NUM_SLOTRANKS][NUM_LANES];
+	uint16_t txdqs[NUM_CHANNELS][NUM_SLOTRANKS][NUM_LANES];
+	uint8_t  tx_eq[NUM_CHANNELS][NUM_SLOTRANKS][NUM_LANES];
+
+	uint16_t rcven[NUM_CHANNELS][NUM_SLOTRANKS][NUM_LANES];
+	uint8_t  rx_eq[NUM_CHANNELS][NUM_SLOTRANKS][NUM_LANES];
+	uint8_t rxdqsp[NUM_CHANNELS][NUM_SLOTRANKS][NUM_LANES];
+	uint8_t rxdqsn[NUM_CHANNELS][NUM_SLOTRANKS][NUM_LANES];
+	int8_t  rxvref[NUM_CHANNELS][NUM_SLOTRANKS][NUM_LANES];
+
+	uint8_t clk_pi_code[NUM_CHANNELS][NUM_SLOTRANKS];
+	uint8_t ctl_pi_code[NUM_CHANNELS][NUM_SLOTRANKS];
+	uint8_t cke_pi_code[NUM_CHANNELS][NUM_SLOTRANKS];
+
+	uint8_t cke_cmd_pi_code[NUM_CHANNELS][NUM_GROUPS];
+	uint8_t cmd_north_pi_code[NUM_CHANNELS][NUM_GROUPS];
+	uint8_t cmd_south_pi_code[NUM_CHANNELS][NUM_GROUPS];
 };
 
+static inline bool is_hsw_ult(void)
+{
+	return CONFIG(INTEL_LYNXPOINT_LP);
+}
+
+static inline bool rank_in_mask(uint8_t rank, uint8_t rankmask)
+{
+	assert(rank < NUM_SLOTRANKS);
+	return !!(BIT(rank) & rankmask);
+}
+
+static inline bool does_ch_exist(const struct sysinfo *ctrl, uint8_t channel)
+{
+	return !!ctrl->dpc[channel];
+}
+
+static inline bool does_rank_exist(const struct sysinfo *ctrl, uint8_t rank)
+{
+	return rank_in_mask(rank, ctrl->rankmap[0] | ctrl->rankmap[1]);
+}
+
+static inline bool rank_in_ch(const struct sysinfo *ctrl, uint8_t rank, uint8_t channel)
+{
+	assert(channel < NUM_CHANNELS);
+	return rank_in_mask(rank, ctrl->rankmap[channel]);
+}
+
+/** TODO: Handling of data_offset_train could be improved, also coupled with reg updates **/
+static inline void clear_data_offset_train_all(struct sysinfo *ctrl)
+{
+	memset(ctrl->data_offset_train, 0, sizeof(ctrl->data_offset_train));
+}
+
 void raminit_main(enum raminit_boot_mode bootmode);
 
 enum raminit_status collect_spd_info(struct sysinfo *ctrl);
 enum raminit_status initialise_mpll(struct sysinfo *ctrl);
 enum raminit_status convert_timings(struct sysinfo *ctrl);
+enum raminit_status configure_mc(struct sysinfo *ctrl);
+
+void configure_timings(struct sysinfo *ctrl);
+void configure_refresh(struct sysinfo *ctrl);
 
 enum raminit_status wait_for_first_rcomp(void);
 
+uint8_t get_rx_bias(const struct sysinfo *ctrl);
+
 uint8_t get_tCWL(uint32_t mem_clock_mhz);
 uint32_t get_tREFI(uint32_t mem_clock_mhz);
 uint32_t get_tXP(uint32_t mem_clock_mhz);
diff --git a/src/northbridge/intel/haswell/native_raminit/reg_structs.h b/src/northbridge/intel/haswell/native_raminit/reg_structs.h
new file mode 100644
index 0000000000..d11cda4b3d
--- /dev/null
+++ b/src/northbridge/intel/haswell/native_raminit/reg_structs.h
@@ -0,0 +1,405 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#ifndef HASWELL_RAMINIT_REG_STRUCTS_H
+#define HASWELL_RAMINIT_REG_STRUCTS_H
+
+union ddr_data_rx_train_rank_reg {
+	struct __packed {
+		uint32_t rcven : 9; // Bits  8:0
+		uint32_t dqs_p : 6; // Bits 14:9
+		uint32_t rx_eq : 5; // Bits 19:15
+		uint32_t dqs_n : 6; // Bits 25:20
+		int32_t  vref  : 6; // Bits 31:26
+	};
+	uint32_t raw;
+};
+
+union ddr_data_tx_train_rank_reg {
+	struct __packed {
+		uint32_t dq_delay  : 9; // Bits  8:0
+		uint32_t dqs_delay : 9; // Bits 17:9
+		uint32_t           : 2; // Bits 19:18
+		uint32_t tx_eq     : 6; // Bits 25:20
+		uint32_t           : 6; // Bits 31:26
+	};
+	uint32_t raw;
+};
+
+union ddr_data_control_0_reg {
+	struct __packed {
+		uint32_t rx_training_mode      : 1; // Bits  0:0
+		uint32_t wl_training_mode      : 1; // Bits  1:1
+		uint32_t rl_training_mode      : 1; // Bits  2:2
+		uint32_t samp_train_mode       : 1; // Bits  3:3
+		uint32_t tx_on                 : 1; // Bits  4:4
+		uint32_t rf_on                 : 1; // Bits  5:5
+		uint32_t rx_pi_on              : 1; // Bits  6:6
+		uint32_t tx_pi_on              : 1; // Bits  7:7
+		uint32_t internal_clocks_on    : 1; // Bits  8:8
+		uint32_t repeater_clocks_on    : 1; // Bits  9:9
+		uint32_t tx_disable            : 1; // Bits 10:10
+		uint32_t rx_disable            : 1; // Bits 11:11
+		uint32_t tx_long               : 1; // Bits 12:12
+		uint32_t rx_dqs_ctle           : 2; // Bits 14:13
+		uint32_t rx_read_pointer       : 3; // Bits 17:15
+		uint32_t driver_segment_enable : 1; // Bits 18:18
+		uint32_t data_vccddq_hi        : 1; // Bits 19:19
+		uint32_t read_rf_rd            : 1; // Bits 20:20
+		uint32_t read_rf_wr            : 1; // Bits 21:21
+		uint32_t read_rf_rank          : 2; // Bits 23:22
+		uint32_t force_odt_on          : 1; // Bits 24:24
+		uint32_t odt_samp_off          : 1; // Bits 25:25
+		uint32_t disable_odt_static    : 1; // Bits 26:26
+		uint32_t ddr_cr_force_odt_on   : 1; // Bits 27:27
+		uint32_t lpddr_mode            : 1; // Bits 28:28
+		uint32_t en_read_preamble      : 1; // Bits 29:29
+		uint32_t odt_samp_extend_en    : 1; // Bits 30:30
+		uint32_t early_rleak_en        : 1; // Bits 31:31
+	};
+	uint32_t raw;
+};
+
+union ddr_data_control_1_reg {
+	struct __packed {
+		int32_t  ref_pi               : 4; // Bits 3:0
+		uint32_t dll_mask             : 2; // Bits 5:4
+		uint32_t dll_weaklock         : 1; // Bits 6:6
+		uint32_t sdll_segment_disable : 3; // Bits 9:7
+		uint32_t rx_bias_ctl          : 3; // Bits 12:10
+		int32_t  odt_delay            : 4; // Bits 16:13
+		uint32_t odt_duration         : 3; // Bits 19:17
+		int32_t  sense_amp_delay      : 4; // Bits 23:20
+		uint32_t sense_amp_duration   : 3; // Bits 26:24
+		uint32_t burst_end_odt_delay  : 3; // Bits 29:27   *** TODO: Check Broadwell ***
+		uint32_t lpddr_long_odt_en    : 1; // Bits 30:30
+		uint32_t                      : 1; // Bits 31:31
+	};
+	uint32_t raw;
+};
+
+/* NOTE: Bits 31:19 are only valid for Broadwell onwards */
+union ddr_data_control_2_reg {
+	struct __packed {
+		uint32_t rx_stagger_ctl    : 5; // Bits  4:0
+		uint32_t force_bias_on     : 1; // Bits  5:5
+		uint32_t force_rx_on       : 1; // Bits  6:6
+		uint32_t leaker_comp       : 2; // Bits  8:7
+		uint32_t rx_dqs_amp_offset : 4; // Bits 12:9
+		uint32_t rx_clk_stg_num    : 5; // Bits 17:13
+		uint32_t wl_long_delay     : 1; // Bits 18:18
+		uint32_t enable_vref_pwrdn : 1; // Bits 19:19
+		uint32_t ddr4_mode         : 1; // Bits 20:20
+		uint32_t en_vddq_odt       : 1; // Bits 21:21
+		uint32_t en_vtt_odt        : 1; // Bits 22:22
+		uint32_t en_const_z_eq_tx  : 1; // Bits 23:23
+		uint32_t tx_eq_dis         : 1; // Bits 24:24
+		uint32_t rx_vref_prog_mfc  : 1; // Bits 25:25
+		uint32_t cben              : 3; // Bits 28:26
+		uint32_t tx_deskew_disable : 1; // Bits 29:29
+		uint32_t rx_deskew_disable : 1; // Bits 30:30
+		uint32_t dq_slew_dly_byp   : 1; // Bits 31:31
+	};
+	uint32_t raw;
+};
+
+union ddr_comp_data_comp_1_reg {
+	struct __packed {
+		uint32_t rcomp_odt_up   : 6; // Bits  5:0
+		uint32_t                : 3; // Bits  8:6
+		uint32_t rcomp_odt_down : 6; // Bits 14:9
+		uint32_t                : 1; // Bits 15:15
+		uint32_t panic_drv_down : 6; // Bits 21:16
+		uint32_t panic_drv_up   : 6; // Bits 27:22
+		uint32_t ls_comp        : 3; // Bits 30:28
+		uint32_t                : 1; // Bits 31:31
+	};
+	uint32_t raw;
+};
+
+union ddr_comp_ctl_0_reg {
+	struct __packed {
+		uint32_t                    : 3; // Bits  2:0
+		uint32_t disable_odt_static : 1; // Bits  3:3
+		uint32_t odt_up_down_off    : 6; // Bits  9:4
+		uint32_t fixed_odt_offset   : 1; // Bits 10:10
+		int32_t  dq_drv_vref        : 4; // Bits 14:11
+		int32_t  dq_odt_vref        : 5; // Bits 19:15
+		int32_t  cmd_drv_vref       : 4; // Bits 23:20
+		int32_t  ctl_drv_vref       : 4; // Bits 27:24
+		int32_t  clk_drv_vref       : 4; // Bits 31:28
+	};
+	uint32_t raw;
+};
+
+union ddr_comp_ctl_1_reg {
+	struct __packed {
+		uint32_t dq_scomp       : 5; // Bits  4:0
+		uint32_t cmd_scomp      : 5; // Bits  9:5
+		uint32_t ctl_scomp      : 5; // Bits 14:10
+		uint32_t clk_scomp      : 5; // Bits 19:15
+		uint32_t tco_cmd_offset : 4; // Bits 23:20
+		uint32_t comp_clk_on    : 1; // Bits 24:24
+		uint32_t vccddq_hi      : 1; // Bits 25:25
+		uint32_t                : 3; // Bits 28:26
+		uint32_t dis_quick_comp : 1; // Bits 29:29
+		uint32_t sin_step       : 1; // Bits 30:30
+		uint32_t sin_step_adv   : 1; // Bits 31:31
+	};
+	uint32_t raw;
+};
+
+union ddr_data_vref_adjust_reg {
+	struct __packed {
+		int32_t  ca_vref_ctrl     : 7;// Bits  6:0
+		int32_t  ch1_vref_ctrl    : 7;// Bits 13:7
+		int32_t  ch0_vref_ctrl    : 7;// Bits 20:14
+		uint32_t en_dimm_vref_ca  : 1;// Bits 21:21
+		uint32_t en_dimm_vref_ch1 : 1;// Bits 22:22
+		uint32_t en_dimm_vref_ch0 : 1;// Bits 23:23
+		uint32_t hi_z_timer_ctrl  : 2;// Bits 25:24
+		uint32_t vccddq_hi_qnnn_h : 1;// Bits 26:26
+		uint32_t                  : 2;// Bits 28:27
+		uint32_t ca_slow_bw       : 1;// Bits 29:29
+		uint32_t ch0_slow_bw      : 1;// Bits 30:30
+		uint32_t ch1_slow_bw      : 1;// Bits 31:31
+	};
+	uint32_t raw;
+};
+
+union ddr_data_vref_control_reg {
+	struct __packed {
+		uint32_t hi_bw_divider   : 2; // Bits  1:0
+		uint32_t lo_bw_divider   : 2; // Bits  3:2
+		uint32_t sample_divider  : 3; // Bits  6:4
+		uint32_t open_loop       : 1; // Bits  7:7
+		uint32_t slow_bw_error   : 2; // Bits  9:8
+		uint32_t hi_bw_enable    : 1; // Bits 10:10
+		uint32_t                 : 1; // Bits 11:11
+		uint32_t vt_slope_b      : 3; // Bits 14:12
+		uint32_t vt_slope_a      : 3; // Bits 17:15
+		uint32_t vt_offset       : 3; // Bits 20:18
+		uint32_t sel_code        : 3; // Bits 23:21
+		uint32_t output_code     : 8; // Bits 31:24
+	};
+	uint32_t raw;
+};
+
+union ddr_comp_vsshi_reg {
+	struct __packed {
+		uint32_t panic_drv_down_vref : 6; // Bits  5:0
+		uint32_t panic_drv_up_vref   : 6; // Bits 11:6
+		uint32_t vt_offset           : 5; // Bits 16:12
+		uint32_t vt_slope_a          : 3; // Bits 19:17
+		uint32_t vt_slope_b          : 3; // Bits 22:20
+		uint32_t                     : 9; // Bits 31:23
+	};
+	uint32_t raw;
+};
+
+union ddr_comp_vsshi_control_reg {
+	struct __packed {
+		uint32_t vsshi_target    : 6; // Bits  5:0
+		uint32_t hi_bw_divider   : 2; // Bits  7:6
+		uint32_t lo_bw_divider   : 2; // Bits  9:8
+		uint32_t sample_divider  : 3; // Bits 12:10
+		uint32_t open_loop       : 1; // Bits 13:13
+		uint32_t bw_error        : 2; // Bits 15:14
+		uint32_t panic_driver_en : 1; // Bits 16:16
+		uint32_t                 : 1; // Bits 17:17
+		uint32_t panic_voltage   : 4; // Bits 21:18
+		uint32_t gain_boost      : 1; // Bits 22:22
+		uint32_t sel_code        : 1; // Bits 23:23
+		uint32_t output_code     : 8; // Bits 31:24
+	};
+	uint32_t raw;
+};
+
+union ddr_clk_controls_reg {
+	struct __packed {
+		uint32_t ref_pi             : 4; // Bits  3:0
+		uint32_t dll_mask           : 2; // Bits  5:4
+		uint32_t                    : 1; // Bits  6:6
+		uint32_t tx_on              : 1; // Bits  7:7
+		uint32_t internal_clocks_on : 1; // Bits  8:8
+		uint32_t repeater_clocks_on : 1; // Bits  9:9
+		uint32_t io_lb_ctl          : 2; // Bits 11:10
+		uint32_t odt_mode           : 1; // Bits 12:12
+		uint32_t                    : 8; // Bits 20:13
+		uint32_t rx_vref            : 6; // Bits 26:21
+		uint32_t vccddq_hi          : 1; // Bits 27:27
+		uint32_t dll_weaklock       : 1; // Bits 28:28
+		uint32_t lpddr_mode         : 1; // Bits 29:29
+		uint32_t                    : 2; // Bits 31:30
+	};
+	uint32_t raw;
+};
+
+union ddr_cmd_controls_reg {
+	struct __packed {
+		int32_t  ref_pi             : 4; // Bits  3:0
+		uint32_t dll_mask           : 2; // Bits  5:4
+		uint32_t                    : 1; // Bits  6:6
+		uint32_t tx_on              : 1; // Bits  7:7
+		uint32_t internal_clocks_on : 1; // Bits  8:8
+		uint32_t repeater_clocks_on : 1; // Bits  9:9
+		uint32_t io_lb_ctl          : 2; // Bits 11:10
+		uint32_t odt_mode           : 1; // Bits 12:12
+		uint32_t cmd_tx_eq          : 2; // Bits 14:13
+		uint32_t early_weak_drive   : 2; // Bits 16:15
+		uint32_t                    : 4; // Bits 20:17
+		int32_t  rx_vref            : 6; // Bits 26:21
+		uint32_t vccddq_hi          : 1; // Bits 27:27
+		uint32_t dll_weaklock       : 1; // Bits 28:28
+		uint32_t lpddr_mode         : 1; // Bits 29:29
+		uint32_t lpddr_ca_a_dis     : 1; // Bits 30:30
+		uint32_t lpddr_ca_b_dis     : 1; // Bits 31:31
+	};
+	uint32_t raw;
+};
+
+/* Same register definition for CKE and CTL fubs */
+union ddr_cke_ctl_controls_reg {
+	struct __packed {
+		int32_t  ref_pi             : 4; // Bits  3:0
+		uint32_t dll_mask           : 2; // Bits  5:4
+		uint32_t                    : 1; // Bits  6:6
+		uint32_t tx_on              : 1; // Bits  7:7
+		uint32_t internal_clocks_on : 1; // Bits  8:8
+		uint32_t repeater_clocks_on : 1; // Bits  9:9
+		uint32_t io_lb_ctl          : 2; // Bits 11:10
+		uint32_t odt_mode           : 1; // Bits 12:12
+		uint32_t cmd_tx_eq          : 2; // Bits 14:13
+		uint32_t early_weak_drive   : 2; // Bits 16:15
+		uint32_t ctl_tx_eq          : 2; // Bits 18:17
+		uint32_t ctl_sr_drv         : 2; // Bits 20:19
+		int32_t  rx_vref            : 6; // Bits 26:21
+		uint32_t vccddq_hi          : 1; // Bits 27:27
+		uint32_t dll_weaklock       : 1; // Bits 28:28
+		uint32_t lpddr_mode         : 1; // Bits 29:29
+		uint32_t la_drv_en_ovrd     : 1; // Bits 30:30
+		uint32_t lpddr_ca_a_dis     : 1; // Bits 31:31
+	};
+	uint32_t raw;
+};
+
+union ddr_scram_misc_control_reg {
+	struct __packed {
+		uint32_t wl_wake_cycles       :  2; // Bits  1:0
+		uint32_t wl_sleep_cycles      :  3; // Bits  4:2
+		uint32_t force_comp_update    :  1; // Bits  5:5
+		uint32_t weaklock_latency     :  4; // Bits  9:6
+		uint32_t ddr_no_ch_interleave :  1; // Bits 10:10
+		uint32_t lpddr_mode           :  1; // Bits 11:11
+		uint32_t cke_mapping_ch0      :  4; // Bits 15:12
+		uint32_t cke_mapping_ch1      :  4; // Bits 19:16
+		uint32_t                      : 12; // Bits 31:20
+	};
+	uint32_t raw;
+};
+
+union mcscheds_cbit_reg {
+	struct __packed {
+		uint32_t dis_opp_cas    : 1; // Bits  0:0
+		uint32_t dis_opp_is_cas : 1; // Bits  1:1
+		uint32_t dis_opp_ras    : 1; // Bits  2:2
+		uint32_t dis_opp_is_ras : 1; // Bits  3:3
+		uint32_t dis_1c_byp     : 1; // Bits  4:4
+		uint32_t dis_2c_byp     : 1; // Bits  5:5
+		uint32_t dis_deprd_opt  : 1; // Bits  6:6
+		uint32_t dis_pt_it      : 1; // Bits  7:7
+		uint32_t dis_prcnt_ring : 1; // Bits  8:8
+		uint32_t dis_prcnt_sa   : 1; // Bits  9:9
+		uint32_t dis_blkr_ph    : 1; // Bits 10:10
+		uint32_t dis_blkr_pe    : 1; // Bits 11:11
+		uint32_t dis_blkr_pm    : 1; // Bits 12:12
+		uint32_t dis_odt        : 1; // Bits 13:13
+		uint32_t oe_always_off  : 1; // Bits 14:14
+		uint32_t                : 1; // Bits 15:15
+		uint32_t dis_aom        : 1; // Bits 16:16
+		uint32_t block_rpq      : 1; // Bits 17:17
+		uint32_t block_wpq      : 1; // Bits 18:18
+		uint32_t invert_align   : 1; // Bits 19:19
+		uint32_t dis_write_gap  : 1; // Bits 20:20
+		uint32_t dis_zq         : 1; // Bits 21:21
+		uint32_t dis_tt         : 1; // Bits 22:22
+		uint32_t dis_opp_ref    : 1; // Bits 23:23
+		uint32_t long_zq        : 1; // Bits 24:24
+		uint32_t dis_srx_zq     : 1; // Bits 25:25
+		uint32_t serialize_zq   : 1; // Bits 26:26
+		uint32_t zq_fast_exec   : 1; // Bits 27:27
+		uint32_t dis_drive_nop  : 1; // Bits 28:28
+		uint32_t pres_wdb_ent   : 1; // Bits 29:29
+		uint32_t dis_clk_gate   : 1; // Bits 30:30
+		uint32_t                : 1; // Bits 31:31
+	};
+	uint32_t raw;
+};
+
+union mcmain_command_rate_limit_reg {
+	struct __packed {
+		uint32_t enable_cmd_limit :  1; // Bits  0:0
+		uint32_t cmd_rate_limit   :  3; // Bits  3:1
+		uint32_t reset_on_command :  4; // Bits  7:4
+		uint32_t reset_delay      :  4; // Bits 11:8
+		uint32_t ck_to_cke_delay  :  2; // Bits 13:12
+		uint32_t                  : 17; // Bits 30:14
+		uint32_t init_mrw_2n_cs   :  1; // Bits 31:31
+	};
+	uint32_t raw;
+};
+
+union mad_chnl_reg {
+	struct __packed {
+		uint32_t ch_a           :  2; // Bits  1:0
+		uint32_t ch_b           :  2; // Bits  3:2
+		uint32_t ch_c           :  2; // Bits  5:4
+		uint32_t stacked_mode   :  1; // Bits  6:6
+		uint32_t stkd_mode_bits :  3; // Bits  9:7
+		uint32_t lpddr_mode     :  1; // Bits 10:10
+		uint32_t                : 21; // Bits 31:11
+	};
+	uint32_t raw;
+};
+
+union mad_dimm_reg {
+	struct __packed {
+		uint32_t dimm_a_size     :  8;  // Bits  7:0
+		uint32_t dimm_b_size     :  8;  // Bits 15:8
+		uint32_t dimm_a_sel      :  1;  // Bits 16:16
+		uint32_t dimm_a_ranks    :  1;  // Bits 17:17
+		uint32_t dimm_b_ranks    :  1;  // Bits 18:18
+		uint32_t dimm_a_width    :  1;  // Bits 19:19
+		uint32_t dimm_b_width    :  1;  // Bits 20:20
+		uint32_t rank_interleave :  1;  // Bits 21:21
+		uint32_t enh_interleave  :  1;  // Bits 22:22
+		uint32_t                 :  1;  // Bits 23:23
+		uint32_t ecc_mode        :  2;  // Bits 25:24
+		uint32_t hori_mode       :  1;  // Bits 26:26
+		uint32_t hori_address    :  3;  // Bits 29:27
+		uint32_t                 :  2;  // Bits 31:30
+	};
+	uint32_t raw;
+};
+
+union mad_zr_reg {
+	struct __packed {
+		uint32_t             : 16; // Bits 15:0
+		uint32_t ch_b_double :  8; // Bits 23:16
+		uint32_t ch_b_single :  8; // Bits 31:24
+	};
+	uint32_t raw;
+};
+
+/* Same definition for P_COMP, M_COMP, D_COMP */
+union pcu_comp_reg {
+	struct __packed {
+		uint32_t comp_disable  :  1; // Bits  0:0
+		uint32_t comp_interval :  4; // Bits  4:1
+		uint32_t               :  3; // Bits  7:5
+		uint32_t comp_force    :  1; // Bits  8:8
+		uint32_t               : 23; // Bits 31:9
+	};
+	uint32_t raw;
+};
+
+#endif
diff --git a/src/northbridge/intel/haswell/native_raminit/timings_refresh.c b/src/northbridge/intel/haswell/native_raminit/timings_refresh.c
new file mode 100644
index 0000000000..a9d960f31b
--- /dev/null
+++ b/src/northbridge/intel/haswell/native_raminit/timings_refresh.c
@@ -0,0 +1,13 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include "raminit_native.h"
+
+void configure_timings(struct sysinfo *ctrl)
+{
+	/** TODO: Stub **/
+}
+
+void configure_refresh(struct sysinfo *ctrl)
+{
+	/** TODO: Stub **/
+}
diff --git a/src/northbridge/intel/haswell/registers/mchbar.h b/src/northbridge/intel/haswell/registers/mchbar.h
index 45f8174995..4c3f399b5d 100644
--- a/src/northbridge/intel/haswell/registers/mchbar.h
+++ b/src/northbridge/intel/haswell/registers/mchbar.h
@@ -7,9 +7,98 @@
 #define NUM_CHANNELS	2
 #define NUM_SLOTS	2
 
+/* Indexed register helper macros */
+#define _DDRIO_C_R_B(r, ch, rank, byte)	((r) + 0x100 * (ch) + 0x4 * (rank) + 0x200 * (byte))
+#define _MCMAIN_C_X(r, ch, x)		((r) + 0x400 * (ch) + 0x4 * (x))
+#define _MCMAIN_C(r, ch)		((r) + 0x400 * (ch))
+
 /* Register definitions */
+
+/* DDR DATA per-channel per-bytelane */
+#define DQ_CONTROL_2(ch, byte)			_DDRIO_C_R_B(0x0064, ch, 0, byte)
+
+/* DDR CKE per-channel */
+#define DDR_CKE_ch_CMD_COMP_OFFSET(ch)		_DDRIO_C_R_B(0x1204, ch, 0, 0)
+#define DDR_CKE_ch_CMD_PI_CODING(ch)		_DDRIO_C_R_B(0x1208, ch, 0, 0)
+
+#define DDR_CKE_ch_CTL_CONTROLS(ch)		_DDRIO_C_R_B(0x121c, ch, 0, 0)
+#define DDR_CKE_ch_CTL_RANKS_USED(ch)		_DDRIO_C_R_B(0x1220, ch, 0, 0)
+
+/* DDR CTL per-channel */
+#define DDR_CTL_ch_CTL_CONTROLS(ch)		_DDRIO_C_R_B(0x1c1c, ch, 0, 0)
+#define DDR_CTL_ch_CTL_RANKS_USED(ch)		_DDRIO_C_R_B(0x1c20, ch, 0, 0)
+
+/* DDR CLK per-channel */
+#define DDR_CLK_ch_RANKS_USED(ch)		_DDRIO_C_R_B(0x1800, ch, 0, 0)
+#define DDR_CLK_ch_COMP_OFFSET(ch)		_DDRIO_C_R_B(0x1808, ch, 0, 0)
+#define DDR_CLK_ch_PI_CODING(ch)		_DDRIO_C_R_B(0x180c, ch, 0, 0)
+#define DDR_CLK_ch_CONTROLS(ch)			_DDRIO_C_R_B(0x1810, ch, 0, 0)
+
+/* DDR Scrambler */
+#define DDR_SCRAMBLE_ch(ch)			(0x2000 + 4 * (ch))
+#define DDR_SCRAM_MISC_CONTROL			0x2008
+
+/* DDR CMDN/CMDS per-channel (writes go to both CMDN and CMDS fubs) */
+#define DDR_CMD_ch_COMP_OFFSET(ch)		_DDRIO_C_R_B(0x3204, ch, 0, 0)
+#define DDR_CMD_ch_PI_CODING(ch)		_DDRIO_C_R_B(0x3208, ch, 0, 0)
+#define DDR_CMD_ch_CONTROLS(ch)			_DDRIO_C_R_B(0x320c, ch, 0, 0)
+
+/* DDR CKE/CTL per-channel (writes go to both CKE and CTL fubs) */
+#define DDR_CKE_CTL_ch_CTL_COMP_OFFSET(ch)	_DDRIO_C_R_B(0x3414, ch, 0, 0)
+#define DDR_CKE_CTL_ch_CTL_PI_CODING(ch)	_DDRIO_C_R_B(0x3418, ch, 0, 0)
+
+/* DDR DATA broadcast */
+#define DDR_DATA_RX_TRAIN_RANK(rank)		_DDRIO_C_R_B(0x3600, 0, rank, 0)
+#define DDR_DATA_RX_PER_BIT_RANK(rank)		_DDRIO_C_R_B(0x3610, 0, rank, 0)
+#define DDR_DATA_TX_TRAIN_RANK(rank)		_DDRIO_C_R_B(0x3620, 0, rank, 0)
+#define DDR_DATA_TX_PER_BIT_RANK(rank)		_DDRIO_C_R_B(0x3630, 0, rank, 0)
+
+#define DDR_DATA_RCOMP_DATA_1			0x3644
+#define DDR_DATA_TX_XTALK			0x3648
+#define DDR_DATA_RX_OFFSET_VDQ			0x364c
+#define DDR_DATA_OFFSET_COMP			0x365c
+#define DDR_DATA_CONTROL_1			0x3660
+
+#define DDR_DATA_OFFSET_TRAIN			0x3670
+#define DDR_DATA_CONTROL_0			0x3674
+#define DDR_DATA_VREF_ADJUST			0x3678
+
+/* DDR CMD broadcast */
+#define DDR_CMD_COMP				0x3700
+
+/* DDR CKE/CTL broadcast */
+#define DDR_CKE_CTL_COMP			0x3810
+
+/* DDR CLK broadcast */
+#define DDR_CLK_COMP				0x3904
+#define DDR_CLK_CONTROLS			0x3910
+#define DDR_CLK_CB_STATUS			0x3918
+
+/* DDR COMP (global) */
+#define DDR_COMP_DATA_COMP_1			0x3a04
+#define DDR_COMP_CMD_COMP			0x3a08
+#define DDR_COMP_CTL_COMP			0x3a0c
+#define DDR_COMP_CLK_COMP			0x3a10
+#define DDR_COMP_CTL_0				0x3a14
+#define DDR_COMP_CTL_1				0x3a18
+#define DDR_COMP_VSSHI				0x3a1c
+#define DDR_COMP_OVERRIDE			0x3a20
+#define DDR_COMP_VSSHI_CONTROL			0x3a24
+
+/* MCMAIN per-channel */
+#define COMMAND_RATE_LIMIT_ch(ch)		_MCMAIN_C(0x4010, ch)
+
+#define MC_INIT_STATE_ch(ch)			_MCMAIN_C(0x42a0, ch)
+
+/* MCMAIN broadcast */
+#define MCSCHEDS_CBIT		0x4c20
+
+#define MCMNTS_SC_WDBWM		0x4f8c
+
+/* MCDECS */
 #define MAD_CHNL		0x5000 /* Address Decoder Channel Configuration */
 #define MAD_DIMM(ch)		(0x5004 + (ch) * 4)
+#define MAD_ZR			0x5014
 #define MC_INIT_STATE_G		0x5030
 #define MRC_REVISION		0x5034 /* MRC Revision */
 
@@ -28,6 +117,8 @@
 
 #define PCU_DDR_PTM_CTL		0x5880
 
+#define PCU_DDR_VOLTAGE		0x58a4
+
 /* Some power MSRs are also represented in MCHBAR */
 #define MCH_PKG_POWER_LIMIT_LO	0x59a0
 #define MCH_PKG_POWER_LIMIT_HI	0x59a4
@@ -48,6 +139,8 @@
 #define  MAILBOX_BIOS_CMD_FSM_MEASURE_INTVL	0x909
 #define  MAILBOX_BIOS_CMD_READ_PCH_POWER	0xa
 #define  MAILBOX_BIOS_CMD_READ_PCH_POWER_EXT	0xb
+#define  MAILBOX_BIOS_CMD_READ_DDR_2X_REFRESH	0x17
+#define  MAILBOX_BIOS_CMD_WRITE_DDR_2X_REFRESH	0x18
 #define  MAILBOX_BIOS_CMD_READ_C9C10_VOLTAGE	0x26
 #define  MAILBOX_BIOS_CMD_WRITE_C9C10_VOLTAGE	0x27
 
@@ -66,6 +159,7 @@
 #define MC_BIOS_REQ		0x5e00 /* Memory frequency request register */
 #define MC_BIOS_DATA		0x5e04 /* Miscellaneous information for BIOS */
 #define SAPMCTL			0x5f00
+#define M_COMP			0x5f08
 
 #define HDAUDRID		0x6008
 #define UMAGFXCTL		0x6020

From fdb57ee43dc47908b16823aa6ed4d6c08c8d6a48 Mon Sep 17 00:00:00 2001
From: Angel Pons <th3fanbus@gmail.com>
Date: Sat, 7 May 2022 20:59:58 +0200
Subject: [PATCH 0303/3886] haswell NRI: Add timings/refresh programming

Program the registers with timing and refresh parameters.

Change-Id: Id2ea339d2c9ea8b56c71d6e88ec76949653ff5c2
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64187
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
---
 .../haswell/native_raminit/lookup_timings.c   | 102 ++++++++
 .../haswell/native_raminit/raminit_native.h   |  14 ++
 .../haswell/native_raminit/reg_structs.h      |  93 +++++++
 .../haswell/native_raminit/timings_refresh.c  | 233 +++++++++++++++++-
 .../intel/haswell/registers/mchbar.h          |  12 +
 5 files changed, 452 insertions(+), 2 deletions(-)

diff --git a/src/northbridge/intel/haswell/native_raminit/lookup_timings.c b/src/northbridge/intel/haswell/native_raminit/lookup_timings.c
index 8b81c7c341..b8d6c1ef40 100644
--- a/src/northbridge/intel/haswell/native_raminit/lookup_timings.c
+++ b/src/northbridge/intel/haswell/native_raminit/lookup_timings.c
@@ -60,3 +60,105 @@ uint32_t get_tXP(const uint32_t mem_clock_mhz)
 	};
 	return lookup_timing(mem_clock_mhz, lut, ARRAY_SIZE(lut));
 }
+
+static uint32_t get_lpddr_tCKE(const uint32_t mem_clock_mhz)
+{
+	const struct timing_lookup lut[] = {
+		{  533,  4 },
+		{  666,  5 },
+		{ fmax,  6 },
+	};
+	return lookup_timing(mem_clock_mhz, lut, ARRAY_SIZE(lut));
+}
+
+static uint32_t get_ddr_tCKE(const uint32_t mem_clock_mhz)
+{
+	const struct timing_lookup lut[] = {
+		{  533,  3 },
+		{  800,  4 },
+		{  933,  5 },
+		{ 1200,  6 },
+		{ fmax,  7 },
+	};
+	return lookup_timing(mem_clock_mhz, lut, ARRAY_SIZE(lut));
+}
+
+uint32_t get_tCKE(const uint32_t mem_clock_mhz, const bool lpddr)
+{
+	return lpddr ? get_lpddr_tCKE(mem_clock_mhz) : get_ddr_tCKE(mem_clock_mhz);
+}
+
+uint32_t get_tXPDLL(const uint32_t mem_clock_mhz)
+{
+	const struct timing_lookup lut[] = {
+		{  400, 10 },
+		{  533, 13 },
+		{  666, 16 },
+		{  800, 20 },
+		{  933, 23 },
+		{ 1066, 26 },
+		{ 1200, 29 },
+		{ fmax, 32 },
+	};
+	return lookup_timing(mem_clock_mhz, lut, ARRAY_SIZE(lut));
+}
+
+uint32_t get_tAONPD(const uint32_t mem_clock_mhz)
+{
+	const struct timing_lookup lut[] = {
+		{  400,  4 },
+		{  533,  5 },
+		{  666,  6 },
+		{  800,  7 }, /* SNB had 8 */
+		{  933,  8 },
+		{ 1066, 10 },
+		{ 1200, 11 },
+		{ fmax, 12 },
+	};
+	return lookup_timing(mem_clock_mhz, lut, ARRAY_SIZE(lut));
+}
+
+uint32_t get_tMOD(const uint32_t mem_clock_mhz)
+{
+	const struct timing_lookup lut[] = {
+		{  800, 12 },
+		{  933, 14 },
+		{ 1066, 16 },
+		{ 1200, 18 },
+		{ fmax, 20 },
+	};
+	return lookup_timing(mem_clock_mhz, lut, ARRAY_SIZE(lut));
+}
+
+uint32_t get_tXS_offset(const uint32_t mem_clock_mhz)
+{
+	return DIV_ROUND_UP(mem_clock_mhz, 100);
+}
+
+static uint32_t get_lpddr_tZQOPER(const uint32_t mem_clock_mhz)
+{
+	return (mem_clock_mhz * 360) / 1000;
+}
+
+static uint32_t get_ddr_tZQOPER(const uint32_t mem_clock_mhz)
+{
+	const struct timing_lookup lut[] = {
+		{  800, 256 },
+		{  933, 299 },
+		{ 1066, 342 },
+		{ 1200, 384 },
+		{ fmax, 427 },
+	};
+	return lookup_timing(mem_clock_mhz, lut, ARRAY_SIZE(lut));
+}
+
+/* tZQOPER defines the period required for ZQCL after SR exit */
+uint32_t get_tZQOPER(const uint32_t mem_clock_mhz, const bool lpddr)
+{
+	return lpddr ? get_lpddr_tZQOPER(mem_clock_mhz) : get_ddr_tZQOPER(mem_clock_mhz);
+}
+
+uint32_t get_tZQCS(const uint32_t mem_clock_mhz, const bool lpddr)
+{
+	return DIV_ROUND_UP(get_tZQOPER(mem_clock_mhz, lpddr), 4);
+}
diff --git a/src/northbridge/intel/haswell/native_raminit/raminit_native.h b/src/northbridge/intel/haswell/native_raminit/raminit_native.h
index fffa6d5450..5915a2bab0 100644
--- a/src/northbridge/intel/haswell/native_raminit/raminit_native.h
+++ b/src/northbridge/intel/haswell/native_raminit/raminit_native.h
@@ -156,6 +156,12 @@ struct sysinfo {
 	uint8_t cke_cmd_pi_code[NUM_CHANNELS][NUM_GROUPS];
 	uint8_t cmd_north_pi_code[NUM_CHANNELS][NUM_GROUPS];
 	uint8_t cmd_south_pi_code[NUM_CHANNELS][NUM_GROUPS];
+
+	union tc_bank_reg tc_bank[NUM_CHANNELS];
+	union tc_bank_rank_a_reg tc_bankrank_a[NUM_CHANNELS];
+	union tc_bank_rank_b_reg tc_bankrank_b[NUM_CHANNELS];
+	union tc_bank_rank_c_reg tc_bankrank_c[NUM_CHANNELS];
+	union tc_bank_rank_d_reg tc_bankrank_d[NUM_CHANNELS];
 };
 
 static inline bool is_hsw_ult(void)
@@ -201,6 +207,14 @@ enum raminit_status configure_mc(struct sysinfo *ctrl);
 void configure_timings(struct sysinfo *ctrl);
 void configure_refresh(struct sysinfo *ctrl);
 
+uint32_t get_tCKE(uint32_t mem_clock_mhz, bool lpddr);
+uint32_t get_tXPDLL(uint32_t mem_clock_mhz);
+uint32_t get_tAONPD(uint32_t mem_clock_mhz);
+uint32_t get_tMOD(uint32_t mem_clock_mhz);
+uint32_t get_tXS_offset(uint32_t mem_clock_mhz);
+uint32_t get_tZQOPER(uint32_t mem_clock_mhz, bool lpddr);
+uint32_t get_tZQCS(uint32_t mem_clock_mhz, bool lpddr);
+
 enum raminit_status wait_for_first_rcomp(void);
 
 uint8_t get_rx_bias(const struct sysinfo *ctrl);
diff --git a/src/northbridge/intel/haswell/native_raminit/reg_structs.h b/src/northbridge/intel/haswell/native_raminit/reg_structs.h
index d11cda4b3d..70487e1640 100644
--- a/src/northbridge/intel/haswell/native_raminit/reg_structs.h
+++ b/src/northbridge/intel/haswell/native_raminit/reg_structs.h
@@ -335,6 +335,99 @@ union mcscheds_cbit_reg {
 	uint32_t raw;
 };
 
+union tc_bank_reg {
+	struct __packed {
+		uint32_t tRCD      : 5; // Bits  4:0
+		uint32_t tRP       : 5; // Bits  9:5
+		uint32_t tRAS      : 6; // Bits 15:10
+		uint32_t tRDPRE    : 4; // Bits 19:16
+		uint32_t tWRPRE    : 6; // Bits 25:20
+		uint32_t tRRD      : 4; // Bits 29:26
+		uint32_t tRPab_ext : 2; // Bits 31:30
+	};
+	uint32_t raw;
+};
+
+union tc_bank_rank_a_reg {
+	struct __packed {
+		uint32_t tCKE        : 4; // Bits  3:0
+		uint32_t tFAW        : 8; // Bits 11:4
+		uint32_t tRDRD_sr    : 3; // Bits 14:12
+		uint32_t tRDRD_dr    : 4; // Bits 18:15
+		uint32_t tRDRD_dd    : 4; // Bits 22:19
+		uint32_t tRDPDEN     : 5; // Bits 27:23
+		uint32_t             : 1; // Bits 28:28
+		uint32_t cmd_3st_dis : 1; // Bits 29:29
+		uint32_t cmd_stretch : 2; // Bits 31:30
+	};
+	uint32_t raw;
+};
+
+union tc_bank_rank_b_reg {
+	struct __packed {
+		uint32_t tWRRD_sr : 6; // Bits  5:0
+		uint32_t tWRRD_dr : 4; // Bits  9:6
+		uint32_t tWRRD_dd : 4; // Bits 13:10
+		uint32_t tWRWR_sr : 3; // Bits 16:14
+		uint32_t tWRWR_dr : 4; // Bits 20:17
+		uint32_t tWRWR_dd : 4; // Bits 24:21
+		uint32_t tWRPDEN  : 6; // Bits 30:25
+		uint32_t dec_wrd  : 1; // Bits 31:31
+	};
+	uint32_t raw;
+};
+
+union tc_bank_rank_c_reg {
+	struct __packed {
+		uint32_t tXPDLL   : 6; // Bits  5:0
+		uint32_t tXP      : 4; // Bits  9:6
+		uint32_t tAONPD   : 4; // Bits 13:10
+		uint32_t tRDWR_sr : 5; // Bits 18:14
+		uint32_t tRDWR_dr : 5; // Bits 23:19
+		uint32_t tRDWR_dd : 5; // Bits 28:24
+		uint32_t          : 3; // Bits 31:29
+	};
+	uint32_t raw;
+};
+
+/* NOTE: Non-ULT only implements the lower 21 bits (odt_write_delay is 2 bits) */
+union tc_bank_rank_d_reg {
+	struct __packed {
+		uint32_t tAA                : 5; // Bits  4:0
+		uint32_t tCWL               : 5; // Bits  9:5
+		uint32_t tCPDED             : 2; // Bits 11:10
+		uint32_t tPRPDEN            : 2; // Bits 13:12
+		uint32_t odt_read_delay     : 3; // Bits 16:14
+		uint32_t odt_read_duration  : 2; // Bits 18:17
+		uint32_t odt_write_duration : 3; // Bits 21:19
+		uint32_t odt_write_delay    : 3; // Bits 24:22
+		uint32_t odt_always_rank_0  : 1; // Bits 25:25
+		uint32_t cmd_delay          : 2; // Bits 27:26
+		uint32_t                    : 4; // Bits 31:28
+	};
+	uint32_t raw;
+};
+
+union tc_rftp_reg {
+	struct __packed {
+		uint32_t tREFI   : 16; // Bits 15:0
+		uint32_t tRFC    :  9; // Bits 24:16
+		uint32_t tREFIx9 :  7; // Bits 31:25
+	};
+	uint32_t raw;
+};
+
+union tc_srftp_reg {
+	struct __packed {
+		uint32_t tXSDLL     : 12; // Bits 11:0
+		uint32_t tXS_offset :  4; // Bits 15:12
+		uint32_t tZQOPER    : 10; // Bits 25:16
+		uint32_t            :  2; // Bits 27:26
+		uint32_t tMOD       :  4; // Bits 31:28
+	};
+	uint32_t raw;
+};
+
 union mcmain_command_rate_limit_reg {
 	struct __packed {
 		uint32_t enable_cmd_limit :  1; // Bits  0:0
diff --git a/src/northbridge/intel/haswell/native_raminit/timings_refresh.c b/src/northbridge/intel/haswell/native_raminit/timings_refresh.c
index a9d960f31b..54fee0121d 100644
--- a/src/northbridge/intel/haswell/native_raminit/timings_refresh.c
+++ b/src/northbridge/intel/haswell/native_raminit/timings_refresh.c
@@ -1,13 +1,242 @@
 /* SPDX-License-Identifier: GPL-2.0-or-later */
 
+#include <assert.h>
+#include <commonlib/bsd/clamp.h>
+#include <console/console.h>
+#include <delay.h>
+#include <device/pci_ops.h>
+#include <northbridge/intel/haswell/haswell.h>
+
 #include "raminit_native.h"
 
+#define BL		8	/* Burst length */
+#define tCCD		4
+#define tRPRE		1
+#define tWPRE		1
+#define tDLLK		512
+
+static bool is_sodimm(const enum spd_dimm_type_ddr3 type)
+{
+	return type == SPD_DDR3_DIMM_TYPE_SO_DIMM || type == SPD_DDR3_DIMM_TYPE_72B_SO_UDIMM;
+}
+
+static uint8_t get_odt_stretch(const struct sysinfo *const ctrl)
+{
+	for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
+		/* Only stretch with 2 DIMMs per channel */
+		if (ctrl->dpc[channel] != 2)
+			continue;
+
+		const struct raminit_dimm_info *dimms = ctrl->dimms[channel];
+
+		/* Only stretch when using SO-DIMMs */
+		if (!is_sodimm(dimms[0].data.dimm_type) || !is_sodimm(dimms[1].data.dimm_type))
+			continue;
+
+		/* Only stretch with mismatched card types */
+		if (dimms[0].data.reference_card == dimms[1].data.reference_card)
+			continue;
+
+		/* Stretch if one SO-DIMM is card F */
+		for (uint8_t slot = 0; slot < NUM_SLOTS; slot++) {
+			if (dimms[slot].data.reference_card == 5)
+				return 1;
+		}
+	}
+	return 0;
+}
+
+static union tc_bank_reg make_tc_bank(struct sysinfo *const ctrl)
+{
+	return (union tc_bank_reg) {
+		.tRCD      = ctrl->tRCD,
+		.tRP       = ctrl->tRP,
+		.tRAS      = ctrl->tRAS,
+		.tRDPRE    = ctrl->tRTP,
+		.tWRPRE    = 4 + ctrl->tCWL + ctrl->tWR,
+		.tRRD      = ctrl->tRRD,
+		.tRPab_ext = 0,	/** TODO: For LPDDR, this is ctrl->tRPab - ctrl->tRP **/
+	};
+}
+
+static union tc_bank_rank_a_reg make_tc_bankrank_a(struct sysinfo *ctrl, uint8_t odt_stretch)
+{
+	/* Use 3N mode for DDR during training, but always use 1N mode for LPDDR */
+	const uint32_t tCMD = ctrl->lpddr ? 0 : 3;
+	const uint32_t tRDRD_drdd = BL / 2 + 1 + tRPRE + odt_stretch + !!ctrl->lpddr;
+
+	return (union tc_bank_rank_a_reg) {
+		.tCKE        = get_tCKE(ctrl->mem_clock_mhz, ctrl->lpddr),
+		.tFAW        = ctrl->tFAW,
+		.tRDRD_sr    = tCCD,
+		.tRDRD_dr    = tRDRD_drdd,
+		.tRDRD_dd    = tRDRD_drdd,
+		.tRDPDEN     = ctrl->tAA + BL / 2 + 1,
+		.cmd_3st_dis = 1,	/* Disable command tri-state before training */
+		.cmd_stretch = tCMD,
+	};
+}
+
+static union tc_bank_rank_b_reg make_tc_bankrank_b(struct sysinfo *const ctrl)
+{
+	const uint8_t tWRRD_drdd = ctrl->tCWL - ctrl->tAA + BL / 2 + 2 + tRPRE;
+	const uint8_t tWRWR_drdd = BL / 2 + 2 + tWPRE;
+
+	return (union tc_bank_rank_b_reg) {
+		.tWRRD_sr = tCCD + ctrl->tCWL + ctrl->tWTR + 2,
+		.tWRRD_dr = ctrl->lpddr ? 8 : tWRRD_drdd,
+		.tWRRD_dd = ctrl->lpddr ? 8 : tWRRD_drdd,
+		.tWRWR_sr = tCCD,
+		.tWRWR_dr = tWRWR_drdd,
+		.tWRWR_dd = tWRWR_drdd,
+		.tWRPDEN  = ctrl->tWR + ctrl->tCWL + BL / 2,
+		.dec_wrd  = ctrl->tCWL >= 6,
+	};
+}
+
+static uint32_t get_tRDWR_sr(const struct sysinfo *ctrl)
+{
+	if (ctrl->lpddr) {
+		const uint32_t tdqsck_max = DIV_ROUND_UP(5500, ctrl->qclkps * 2);
+		return ctrl->tAA - ctrl->tCWL + tCCD + tWPRE + tdqsck_max + 1;
+	} else {
+		const bool fast_clock = ctrl->mem_clock_mhz > 666;
+		return ctrl->tAA - ctrl->tCWL + tCCD + tWPRE + 2 + fast_clock;
+	}
+}
+
+static union tc_bank_rank_c_reg make_tc_bankrank_c(struct sysinfo *ctrl, uint8_t odt_stretch)
+{
+	const uint32_t tRDWR_sr = get_tRDWR_sr(ctrl);
+	const uint32_t tRDWR_drdd = tRDWR_sr + odt_stretch;
+
+	return (union tc_bank_rank_c_reg) {
+		.tXPDLL   = get_tXPDLL(ctrl->mem_clock_mhz),
+		.tXP      = MAX(ctrl->tXP, 7),	/* Use a higher tXP for training */
+		.tAONPD   = get_tAONPD(ctrl->mem_clock_mhz),
+		.tRDWR_sr = tRDWR_sr,
+		.tRDWR_dr = tRDWR_drdd,
+		.tRDWR_dd = tRDWR_drdd,
+	};
+}
+
+static union tc_bank_rank_d_reg make_tc_bankrank_d(struct sysinfo *ctrl, uint8_t odt_stretch)
+{
+	const uint32_t odt_rd_delay = ctrl->tAA - ctrl->tCWL;
+	if (!ctrl->lpddr) {
+		return (union tc_bank_rank_d_reg) {
+			.tAA               = ctrl->tAA,
+			.tCWL              = ctrl->tCWL,
+			.tCPDED            = 1,
+			.tPRPDEN           = 1,
+			.odt_read_delay    = odt_rd_delay,
+			.odt_read_duration = odt_stretch,
+		};
+	}
+
+	/* tCWL has 1 extra clock because of tDQSS, subtract it here */
+	const uint32_t tCWL_lpddr = ctrl->tCWL - 1;
+	const uint32_t odt_wr_delay = tCWL_lpddr + DIV_ROUND_UP(3500, ctrl->qclkps * 2);
+	const uint32_t odt_wr_duration = DIV_ROUND_UP(3500 - 1750, ctrl->qclkps * 2) + 1;
+
+	return (union tc_bank_rank_d_reg) {
+		.tAA                = ctrl->tAA,
+		.tCWL               = tCWL_lpddr,
+		.tCPDED             = 2,	/* Required by JEDEC LPDDR3 spec */
+		.tPRPDEN            = 1,
+		.odt_read_delay     = odt_rd_delay,
+		.odt_read_duration  = odt_stretch,
+		.odt_write_delay    = odt_wr_delay,
+		.odt_write_duration = odt_wr_duration,
+		.odt_always_rank_0  = ctrl->lpddr_dram_odt
+	};
+}
+
+/* ZQCS period values, in (tREFI * 128) units */
+#define ZQCS_PERIOD_DDR3	128	/* tREFI * 128 = 7.8 us * 128 = 1ms */
+#define ZQCS_PERIOD_LPDDR3	256	/* tREFI * 128 = 3.9 us * 128 = 0.5ms */
+
+static uint32_t make_tc_zqcal(const struct sysinfo *const ctrl)
+{
+	const uint32_t zqcs_period = ctrl->lpddr ? ZQCS_PERIOD_LPDDR3 : ZQCS_PERIOD_DDR3;
+	const uint32_t tZQCS = get_tZQCS(ctrl->mem_clock_mhz, ctrl->lpddr);
+	return tZQCS << (is_hsw_ult() ? 10 : 8) | zqcs_period;
+}
+
+static union tc_rftp_reg make_tc_rftp(const struct sysinfo *const ctrl)
+{
+	/*
+	 * The tREFIx9 field should be programmed to minimum of 8.9 * tREFI (to allow
+	 * for possible delays from ZQ or isoc) and tRASmax (70us) divided by 1024.
+	 */
+	return (union tc_rftp_reg) {
+		.tREFI   = ctrl->tREFI,
+		.tRFC    = ctrl->tRFC,
+		.tREFIx9 = ctrl->tREFI * 89 / 10240,
+	};
+}
+
+static union tc_srftp_reg make_tc_srftp(const struct sysinfo *const ctrl)
+{
+	return (union tc_srftp_reg) {
+		.tXSDLL     = tDLLK,
+		.tXS_offset = get_tXS_offset(ctrl->mem_clock_mhz),
+		.tZQOPER    = get_tZQOPER(ctrl->mem_clock_mhz, ctrl->lpddr),
+		.tMOD       = get_tMOD(ctrl->mem_clock_mhz) - 8,
+	};
+}
+
 void configure_timings(struct sysinfo *ctrl)
 {
-	/** TODO: Stub **/
+	if (ctrl->lpddr)
+		die("%s: Missing support for LPDDR\n", __func__);
+
+	const uint8_t odt_stretch = get_odt_stretch(ctrl);
+	const union tc_bank_reg tc_bank = make_tc_bank(ctrl);
+	const union tc_bank_rank_a_reg tc_bank_rank_a = make_tc_bankrank_a(ctrl, odt_stretch);
+	const union tc_bank_rank_b_reg tc_bank_rank_b = make_tc_bankrank_b(ctrl);
+	const union tc_bank_rank_c_reg tc_bank_rank_c = make_tc_bankrank_c(ctrl, odt_stretch);
+	const union tc_bank_rank_d_reg tc_bank_rank_d = make_tc_bankrank_d(ctrl, odt_stretch);
+
+	const uint8_t wr_delay = tc_bank_rank_b.dec_wrd + 1;
+	uint8_t sc_wr_add_delay = 0;
+	sc_wr_add_delay |= wr_delay << 0;
+	sc_wr_add_delay |= wr_delay << 2;
+	sc_wr_add_delay |= wr_delay << 4;
+	sc_wr_add_delay |= wr_delay << 6;
+
+	for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
+		if (!does_ch_exist(ctrl, channel))
+			continue;
+
+		ctrl->tc_bank[channel] = tc_bank;
+		ctrl->tc_bankrank_a[channel] = tc_bank_rank_a;
+		ctrl->tc_bankrank_b[channel] = tc_bank_rank_b;
+		ctrl->tc_bankrank_c[channel] = tc_bank_rank_c;
+		ctrl->tc_bankrank_d[channel] = tc_bank_rank_d;
+
+		mchbar_write32(TC_BANK_ch(channel), ctrl->tc_bank[channel].raw);
+		mchbar_write32(TC_BANK_RANK_A_ch(channel), ctrl->tc_bankrank_a[channel].raw);
+		mchbar_write32(TC_BANK_RANK_B_ch(channel), ctrl->tc_bankrank_b[channel].raw);
+		mchbar_write32(TC_BANK_RANK_C_ch(channel), ctrl->tc_bankrank_c[channel].raw);
+		mchbar_write32(TC_BANK_RANK_D_ch(channel), ctrl->tc_bankrank_d[channel].raw);
+		mchbar_write8(SC_WR_ADD_DELAY_ch(channel), sc_wr_add_delay);
+	}
 }
 
 void configure_refresh(struct sysinfo *ctrl)
 {
-	/** TODO: Stub **/
+	const union tc_srftp_reg tc_srftp = make_tc_srftp(ctrl);
+	const union tc_rftp_reg  tc_rftp  = make_tc_rftp(ctrl);
+	const uint32_t tc_zqcal = make_tc_zqcal(ctrl);
+
+	for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
+		if (!does_ch_exist(ctrl, channel))
+			continue;
+
+		mchbar_setbits32(TC_RFP_ch(channel), 0xff);
+		mchbar_write32(TC_RFTP_ch(channel),  tc_rftp.raw);
+		mchbar_write32(TC_SRFTP_ch(channel), tc_srftp.raw);
+		mchbar_write32(TC_ZQCAL_ch(channel), tc_zqcal);
+	}
 }
diff --git a/src/northbridge/intel/haswell/registers/mchbar.h b/src/northbridge/intel/haswell/registers/mchbar.h
index 4c3f399b5d..2acc5cbbc8 100644
--- a/src/northbridge/intel/haswell/registers/mchbar.h
+++ b/src/northbridge/intel/haswell/registers/mchbar.h
@@ -86,9 +86,21 @@
 #define DDR_COMP_VSSHI_CONTROL			0x3a24
 
 /* MCMAIN per-channel */
+#define TC_BANK_ch(ch)				_MCMAIN_C(0x4000, ch)
+#define TC_BANK_RANK_A_ch(ch)			_MCMAIN_C(0x4004, ch)
+#define TC_BANK_RANK_B_ch(ch)			_MCMAIN_C(0x4008, ch)
+#define TC_BANK_RANK_C_ch(ch)			_MCMAIN_C(0x400c, ch)
 #define COMMAND_RATE_LIMIT_ch(ch)		_MCMAIN_C(0x4010, ch)
+#define TC_BANK_RANK_D_ch(ch)			_MCMAIN_C(0x4014, ch)
+#define SC_ROUNDT_LAT_ch(ch)			_MCMAIN_C(0x4024, ch)
 
+#define SC_WR_ADD_DELAY_ch(ch)			_MCMAIN_C(0x40d0, ch)
+
+#define TC_ZQCAL_ch(ch)				_MCMAIN_C(0x4290, ch)
+#define TC_RFP_ch(ch)				_MCMAIN_C(0x4294, ch)
+#define TC_RFTP_ch(ch)				_MCMAIN_C(0x4298, ch)
 #define MC_INIT_STATE_ch(ch)			_MCMAIN_C(0x42a0, ch)
+#define TC_SRFTP_ch(ch)				_MCMAIN_C(0x42a4, ch)
 
 /* MCMAIN broadcast */
 #define MCSCHEDS_CBIT		0x4c20

From e95c52ef0871bc8b57d7e8e560b2e139d9e7112e Mon Sep 17 00:00:00 2001
From: Angel Pons <th3fanbus@gmail.com>
Date: Sat, 7 May 2022 21:24:50 +0200
Subject: [PATCH 0304/3886] haswell NRI: Program memory map

This is very similar to Sandy/Ivy Bridge, except that there's several
registers to program in GDXCBAR. One of these GDXCBAR registers has a
lock bit that must be set in order for the memory controller to allow
normal access to DRAM. And it took me four months to realize this one
bit was the only reason why native raminit did not work.

Change-Id: I3af73a018a7ba948701a542e661e7fefd57591fe
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64188
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 .../intel/haswell/native_raminit/Makefile.mk  |   1 +
 .../intel/haswell/native_raminit/memory_map.c | 183 ++++++++++++++++++
 .../haswell/native_raminit/raminit_main.c     |   1 +
 .../haswell/native_raminit/raminit_native.h   |   1 +
 .../intel/haswell/registers/host_bridge.h     |   2 +
 5 files changed, 188 insertions(+)
 create mode 100644 src/northbridge/intel/haswell/native_raminit/memory_map.c

diff --git a/src/northbridge/intel/haswell/native_raminit/Makefile.mk b/src/northbridge/intel/haswell/native_raminit/Makefile.mk
index fc55277a65..37d527e972 100644
--- a/src/northbridge/intel/haswell/native_raminit/Makefile.mk
+++ b/src/northbridge/intel/haswell/native_raminit/Makefile.mk
@@ -4,6 +4,7 @@ romstage-y += configure_mc.c
 romstage-y += lookup_timings.c
 romstage-y += init_mpll.c
 romstage-y += io_comp_control.c
+romstage-y += memory_map.c
 romstage-y += raminit_main.c
 romstage-y += raminit_native.c
 romstage-y += spd_bitmunching.c
diff --git a/src/northbridge/intel/haswell/native_raminit/memory_map.c b/src/northbridge/intel/haswell/native_raminit/memory_map.c
new file mode 100644
index 0000000000..e3aded2b37
--- /dev/null
+++ b/src/northbridge/intel/haswell/native_raminit/memory_map.c
@@ -0,0 +1,183 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <device/pci_ops.h>
+#include <northbridge/intel/haswell/haswell.h>
+#include <southbridge/intel/lynxpoint/me.h>
+#include <types.h>
+
+#include "raminit_native.h"
+
+/* GDXCBAR */
+#define MPCOHTRK_GDXC_MOT_ADDRESS_LO		0x10
+#define MPCOHTRK_GDXC_MOT_ADDRESS_HI		0x14
+#define MPCOHTRK_GDXC_MOT_REGION		0x18
+
+#define MPCOHTRK_GDXC_OCLA_ADDRESS_LO		0x20
+#define MPCOHTRK_GDXC_OCLA_ADDRESS_HI		0x24
+#define MPCOHTRK_GDXC_OCLA_REGION		0x28
+
+/* This lock bit made me lose what little sanity I had left. - Angel Pons */
+#define MPCOHTRK_GDXC_OCLA_ADDRESS_HI_LOCK	BIT(2)
+
+static inline uint32_t gdxcbar_read32(const uintptr_t offset)
+{
+	return read32p((mchbar_read32(GDXCBAR) & ~1) + offset);
+}
+
+static inline void gdxcbar_write32(const uintptr_t offset, const uint32_t value)
+{
+	write32p((mchbar_read32(GDXCBAR) & ~1) + offset, value);
+}
+
+static inline void gdxcbar_clrsetbits32(const uintptr_t offset, uint32_t clear, uint32_t set)
+{
+	const uintptr_t address = (mchbar_read32(GDXCBAR) & ~1) + offset;
+	clrsetbits32((void *)address, clear, set);
+}
+
+#define gdxcbar_setbits32(offset, set)		gdxcbar_clrsetbits32(offset, 0, set)
+#define gdxcbar_clrbits32(offset, clear)	gdxcbar_clrsetbits32(offset, clear, 0)
+
+/* All values stored in here (except the bool) are specified in MiB */
+struct memory_map_data {
+	uint32_t dpr_size;
+	uint32_t tseg_size;
+	uint32_t gtt_size;
+	uint32_t gms_size;
+	uint32_t me_stolen_size;
+	uint32_t mmio_size;
+	uint32_t touud;
+	uint32_t remaplimit;
+	uint32_t remapbase;
+	uint32_t tom;
+	uint32_t tom_minus_me;
+	uint32_t tolud;
+	uint32_t bdsm_base;
+	uint32_t gtt_base;
+	uint32_t tseg_base;
+	bool reclaim_possible;
+};
+
+static void compute_memory_map(struct memory_map_data *map)
+{
+	map->tom_minus_me = map->tom - map->me_stolen_size;
+
+	/*
+	 * MMIO size will actually be slightly smaller than computed,
+	 * but matches what MRC does and is more MTRR-friendly given
+	 * that TSEG is treated as WB, but SMRR makes TSEG UC anyway.
+	 */
+	const uint32_t mmio_size = MIN(map->tom_minus_me, 4096) / 2;
+	map->gtt_base = ALIGN_DOWN(mmio_size, map->tseg_size);
+	map->tseg_base = map->gtt_base - map->tseg_size;
+	map->bdsm_base = map->gtt_base + map->gtt_size;
+	map->tolud = map->bdsm_base + map->gms_size;
+	map->reclaim_possible = map->tom_minus_me > map->tolud;
+
+	if (map->reclaim_possible) {
+		map->remapbase  = MAX(4096, map->tom_minus_me);
+		map->touud      = MIN(4096, map->tom_minus_me) + map->remapbase - map->tolud;
+		map->remaplimit = map->touud - 1;
+	} else {
+		map->remapbase  = 0;
+		map->remaplimit = 0;
+		map->touud = map->tom_minus_me;
+	}
+}
+
+static void display_memory_map(const struct memory_map_data *map)
+{
+	if (!CONFIG(DEBUG_RAM_SETUP))
+		return;
+
+	printk(BIOS_DEBUG, "============ MEMORY MAP ============\n");
+	printk(BIOS_DEBUG, "\n");
+	printk(BIOS_DEBUG, "dpr_size       = %u MiB\n", map->dpr_size);
+	printk(BIOS_DEBUG, "tseg_size      = %u MiB\n", map->tseg_size);
+	printk(BIOS_DEBUG, "gtt_size       = %u MiB\n", map->gtt_size);
+	printk(BIOS_DEBUG, "gms_size       = %u MiB\n", map->gms_size);
+	printk(BIOS_DEBUG, "me_stolen_size = %u MiB\n", map->me_stolen_size);
+	printk(BIOS_DEBUG, "\n");
+	printk(BIOS_DEBUG, "touud          = %u MiB\n", map->touud);
+	printk(BIOS_DEBUG, "remaplimit     = %u MiB\n", map->remaplimit);
+	printk(BIOS_DEBUG, "remapbase      = %u MiB\n", map->remapbase);
+	printk(BIOS_DEBUG, "tom            = %u MiB\n", map->tom);
+	printk(BIOS_DEBUG, "tom_minus_me   = %u MiB\n", map->tom_minus_me);
+	printk(BIOS_DEBUG, "tolud          = %u MiB\n", map->tolud);
+	printk(BIOS_DEBUG, "bdsm_base      = %u MiB\n", map->bdsm_base);
+	printk(BIOS_DEBUG, "gtt_base       = %u MiB\n", map->gtt_base);
+	printk(BIOS_DEBUG, "tseg_base      = %u MiB\n", map->tseg_base);
+	printk(BIOS_DEBUG, "\n");
+	printk(BIOS_DEBUG, "reclaim_possible = %s\n", map->reclaim_possible ? "Yes" : "No");
+}
+
+static void map_write_reg64(const uint16_t reg, const uint64_t size)
+{
+	const uint64_t value = size << 20;
+	pci_write_config32(HOST_BRIDGE, reg + 4, value >> 32);
+	pci_write_config32(HOST_BRIDGE, reg + 0, value >>  0);
+}
+
+static void map_write_reg32(const uint16_t reg, const uint32_t size)
+{
+	const uint32_t value = size << 20;
+	pci_write_config32(HOST_BRIDGE, reg, value);
+}
+
+static void program_memory_map(const struct memory_map_data *map)
+{
+	map_write_reg64(TOUUD, map->touud);
+	map_write_reg64(TOM,   map->tom);
+	if (map->reclaim_possible) {
+		map_write_reg64(REMAPBASE,  map->remapbase);
+		map_write_reg64(REMAPLIMIT, map->remaplimit);
+	}
+	if (map->me_stolen_size) {
+		map_write_reg64(MESEG_LIMIT, 0x80000 - map->me_stolen_size);
+		map_write_reg64(MESEG_BASE, map->tom_minus_me);
+		pci_or_config32(HOST_BRIDGE, MESEG_LIMIT, ME_STLEN_EN);
+	}
+	map_write_reg32(TOLUD, map->tolud);
+	map_write_reg32(BDSM,  map->bdsm_base);
+	map_write_reg32(BGSM,  map->gtt_base);
+	map_write_reg32(TSEG,  map->tseg_base);
+
+	const uint32_t dpr_reg = map->tseg_base << 20 | map->dpr_size << 4;
+	pci_write_config32(HOST_BRIDGE, DPR, dpr_reg);
+
+	const uint16_t gfx_stolen_size = GGC_IGD_MEM_IN_32MB_UNITS(map->gms_size / 32);
+	const uint16_t ggc = map->gtt_size << 8 | gfx_stolen_size;
+	pci_write_config16(HOST_BRIDGE, GGC, ggc);
+
+	/** TODO: Do not hardcode these? GDXC has weird alignment requirements, though. **/
+	gdxcbar_write32(MPCOHTRK_GDXC_MOT_ADDRESS_LO, 0);
+	gdxcbar_write32(MPCOHTRK_GDXC_MOT_ADDRESS_HI, 0);
+	gdxcbar_write32(MPCOHTRK_GDXC_MOT_REGION, 0);
+
+	gdxcbar_write32(MPCOHTRK_GDXC_OCLA_ADDRESS_LO, 0);
+	gdxcbar_write32(MPCOHTRK_GDXC_OCLA_ADDRESS_HI, 0);
+	gdxcbar_write32(MPCOHTRK_GDXC_OCLA_REGION, 0);
+
+	gdxcbar_setbits32(MPCOHTRK_GDXC_OCLA_ADDRESS_HI, MPCOHTRK_GDXC_OCLA_ADDRESS_HI_LOCK);
+}
+
+enum raminit_status configure_memory_map(struct sysinfo *ctrl)
+{
+	struct memory_map_data memory_map = {
+		.tom            = ctrl->channel_size_mb[0] + ctrl->channel_size_mb[1],
+		.dpr_size       = CONFIG_INTEL_TXT_DPR_SIZE,
+		.tseg_size      = CONFIG_SMM_TSEG_SIZE >> 20,
+		.me_stolen_size = intel_early_me_uma_size(),
+	};
+	/** FIXME: MRC hardcodes iGPU parameters, but we should not **/
+	const bool igpu_on = pci_read_config32(HOST_BRIDGE, DEVEN) & DEVEN_D2EN;
+	if (CONFIG(ONBOARD_VGA_IS_PRIMARY) || igpu_on) {
+		memory_map.gtt_size = 2;
+		memory_map.gms_size = 64;
+		pci_or_config32(HOST_BRIDGE, DEVEN, DEVEN_D2EN);
+	}
+	compute_memory_map(&memory_map);
+	display_memory_map(&memory_map);
+	program_memory_map(&memory_map);
+	return 0;
+}
diff --git a/src/northbridge/intel/haswell/native_raminit/raminit_main.c b/src/northbridge/intel/haswell/native_raminit/raminit_main.c
index a13ae5641e..a697343ef9 100644
--- a/src/northbridge/intel/haswell/native_raminit/raminit_main.c
+++ b/src/northbridge/intel/haswell/native_raminit/raminit_main.c
@@ -24,6 +24,7 @@ static const struct task_entry cold_boot[] = {
 	{ initialise_mpll,                                        true, "INITMPLL",   },
 	{ convert_timings,                                        true, "CONVTIM",    },
 	{ configure_mc,                                           true, "CONFMC",     },
+	{ configure_memory_map,                                   true, "MEMMAP",     },
 };
 
 /* Return a generic stepping value to make stepping checks simpler */
diff --git a/src/northbridge/intel/haswell/native_raminit/raminit_native.h b/src/northbridge/intel/haswell/native_raminit/raminit_native.h
index 5915a2bab0..8f937c4ccd 100644
--- a/src/northbridge/intel/haswell/native_raminit/raminit_native.h
+++ b/src/northbridge/intel/haswell/native_raminit/raminit_native.h
@@ -203,6 +203,7 @@ enum raminit_status collect_spd_info(struct sysinfo *ctrl);
 enum raminit_status initialise_mpll(struct sysinfo *ctrl);
 enum raminit_status convert_timings(struct sysinfo *ctrl);
 enum raminit_status configure_mc(struct sysinfo *ctrl);
+enum raminit_status configure_memory_map(struct sysinfo *ctrl);
 
 void configure_timings(struct sysinfo *ctrl);
 void configure_refresh(struct sysinfo *ctrl);
diff --git a/src/northbridge/intel/haswell/registers/host_bridge.h b/src/northbridge/intel/haswell/registers/host_bridge.h
index 1ee0ab2890..0228cf6bb9 100644
--- a/src/northbridge/intel/haswell/registers/host_bridge.h
+++ b/src/northbridge/intel/haswell/registers/host_bridge.h
@@ -34,6 +34,8 @@
 
 #define MESEG_BASE	0x70	/* Management Engine Base */
 #define MESEG_LIMIT	0x78	/* Management Engine Limit */
+#define  MELCK		(1 << 10)	/* ME Range Lock */
+#define  ME_STLEN_EN	(1 << 11)	/* ME Stolen Memory Enable */
 
 #define PAM0		0x80
 #define PAM1		0x81

From 06d0ee4372c7aa993eb7c1a531f363d12c41f218 Mon Sep 17 00:00:00 2001
From: Angel Pons <th3fanbus@gmail.com>
Date: Sat, 7 May 2022 21:49:40 +0200
Subject: [PATCH 0305/3886] haswell NRI: Add DDR3 JEDEC reset and init

Implement JEDEC reset and init sequence for DDR3. The MRS commands are
issued through the REUT (Robust Electrical Unified Testing) hardware.

Change-Id: I2a0c066537021b587599228086727cb1e041bff5
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64189
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
---
 .../intel/haswell/native_raminit/Makefile.mk  |   3 +
 .../intel/haswell/native_raminit/ddr3.c       | 217 ++++++++++++++++++
 .../haswell/native_raminit/io_comp_control.c  |  19 ++
 .../haswell/native_raminit/jedec_reset.c      | 120 ++++++++++
 .../haswell/native_raminit/raminit_main.c     |   2 +
 .../haswell/native_raminit/raminit_native.h   |  99 ++++++++
 .../haswell/native_raminit/reg_structs.h      | 154 +++++++++++++
 .../intel/haswell/native_raminit/reut.c       | 196 ++++++++++++++++
 .../intel/haswell/registers/mchbar.h          |  21 ++
 src/southbridge/intel/lynxpoint/pch.h         |   2 +
 10 files changed, 833 insertions(+)
 create mode 100644 src/northbridge/intel/haswell/native_raminit/ddr3.c
 create mode 100644 src/northbridge/intel/haswell/native_raminit/jedec_reset.c
 create mode 100644 src/northbridge/intel/haswell/native_raminit/reut.c

diff --git a/src/northbridge/intel/haswell/native_raminit/Makefile.mk b/src/northbridge/intel/haswell/native_raminit/Makefile.mk
index 37d527e972..e9212df9e6 100644
--- a/src/northbridge/intel/haswell/native_raminit/Makefile.mk
+++ b/src/northbridge/intel/haswell/native_raminit/Makefile.mk
@@ -1,11 +1,14 @@
 ## SPDX-License-Identifier: GPL-2.0-or-later
 
 romstage-y += configure_mc.c
+romstage-y += ddr3.c
+romstage-y += jedec_reset.c
 romstage-y += lookup_timings.c
 romstage-y += init_mpll.c
 romstage-y += io_comp_control.c
 romstage-y += memory_map.c
 romstage-y += raminit_main.c
 romstage-y += raminit_native.c
+romstage-y += reut.c
 romstage-y += spd_bitmunching.c
 romstage-y += timings_refresh.c
diff --git a/src/northbridge/intel/haswell/native_raminit/ddr3.c b/src/northbridge/intel/haswell/native_raminit/ddr3.c
new file mode 100644
index 0000000000..6ddb11488b
--- /dev/null
+++ b/src/northbridge/intel/haswell/native_raminit/ddr3.c
@@ -0,0 +1,217 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <assert.h>
+#include <console/console.h>
+#include <northbridge/intel/haswell/haswell.h>
+#include <types.h>
+
+#include "raminit_native.h"
+
+#define DDR3_RTTNOM(a, b, c) (((a) << 9) | ((b) << 6) | ((c) << 2))
+
+uint16_t encode_ddr3_rttnom(const uint32_t rttnom)
+{
+	switch (rttnom) {
+	case 0:		return DDR3_RTTNOM(0, 0, 0);	/* RttNom is disabled */
+	case 20:	return DDR3_RTTNOM(1, 0, 0);	/* RZQ/12 */
+	case 30:	return DDR3_RTTNOM(1, 0, 1);	/* RZQ/8 */
+	case 40:	return DDR3_RTTNOM(0, 1, 1);	/* RZQ/6 */
+	case 60:	return DDR3_RTTNOM(0, 0, 1);	/* RZQ/4 */
+	case 120:	return DDR3_RTTNOM(0, 1, 0);	/* RZQ/2 */
+	}
+	printk(BIOS_ERR, "%s: Invalid rtt_nom value %u\n", __func__, rttnom);
+	return 0;
+}
+
+static const uint8_t jedec_wr_t[12] = { 1, 2, 3, 4, 5, 5, 6, 6, 7, 7, 0, 0 };
+
+static void ddr3_program_mr0(struct sysinfo *ctrl, const uint8_t dll_reset)
+{
+	assert(ctrl->tWR >= 5 && ctrl->tWR <= 16);
+	assert(ctrl->tAA >= 4);
+	const uint8_t jedec_cas = ctrl->tAA - 4;
+	const union {
+		struct __packed {
+			uint16_t burst_length     : 2; // Bits  1:0
+			uint16_t cas_latency_msb  : 1; // Bits  2:2
+			uint16_t read_burst_type  : 1; // Bits  3:3
+			uint16_t cas_latency_low  : 3; // Bits  6:4
+			uint16_t test_mode        : 1; // Bits  7:7
+			uint16_t dll_reset        : 1; // Bits  8:8
+			uint16_t write_recovery   : 3; // Bits 11:9
+			uint16_t precharge_pd_dll : 1; // Bits 12:12
+			uint16_t                  : 3; // Bits 15:13
+		};
+		uint16_t raw;
+	} mr0reg = {
+		.burst_length     = 0,
+		.cas_latency_msb  = !!(jedec_cas & BIT(3)),
+		.read_burst_type  = 0,
+		.cas_latency_low  = jedec_cas & 0x7,
+		.dll_reset        = 1,
+		.write_recovery   = jedec_wr_t[ctrl->tWR - 5],
+		.precharge_pd_dll = 0,
+	};
+	for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
+		if (!does_ch_exist(ctrl, channel))
+			continue;
+
+		for (uint8_t slot = 0; slot < NUM_SLOTS; slot++) {
+			if (!rank_in_ch(ctrl, slot + slot, channel))
+				continue;
+
+			if (!ctrl->restore_mrs)
+				ctrl->mr0[channel][slot] = mr0reg.raw;
+		}
+		reut_issue_mrs_all(ctrl, channel, 0, ctrl->mr0[channel]);
+	}
+}
+
+void ddr3_program_mr1(struct sysinfo *ctrl, const uint8_t wl_mode, const uint8_t q_off)
+{
+	/*
+	 * JESD79-3F (JEDEC DDR3 spec) refers to bit 0 of MR1 as 'DLL Enable'.
+	 * However, its encoding is weird, and 'DLL Disable' makes more sense.
+	 *
+	 * Moreover, bit 5 is part of ODIC (Output Driver Impedance Control),
+	 * but all encodings where MR1 bit 5 is 1 are reserved. Thus, omit it.
+	 */
+	union {
+		struct __packed {
+			uint16_t dll_disable      : 1; // Bits  0:0
+			uint16_t od_impedance_ctl : 1; // Bits  1:1
+			uint16_t odt_rtt_nom_low  : 1; // Bits  2:2
+			uint16_t additive_latency : 2; // Bits  4:3
+			uint16_t                  : 1; // Bits  5:5
+			uint16_t odt_rtt_nom_mid  : 1; // Bits  6:6
+			uint16_t write_level_mode : 1; // Bits  7:7
+			uint16_t                  : 1; // Bits  8:8
+			uint16_t odt_rtt_nom_high : 1; // Bits  9:9
+			uint16_t                  : 1; // Bits 10:10
+			uint16_t t_dqs            : 1; // Bits 11:11
+			uint16_t q_off            : 1; // Bits 12:12
+			uint16_t                  : 3; // Bits 15:13
+		};
+		uint16_t raw;
+	} mr1reg = {
+		.dll_disable      = 0,
+		.od_impedance_ctl = 1,	/* RZQ/7 */
+		.additive_latency = 0,
+		.write_level_mode = wl_mode,
+		.t_dqs            = 0,
+		.q_off            = q_off,
+	};
+	for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
+		if (!does_ch_exist(ctrl, channel))
+			continue;
+
+		mr1reg.raw &= ~RTTNOM_MASK;
+		mr1reg.raw |= encode_ddr3_rttnom(ctrl->dpc[channel] == 2 ? 60 : 0);
+		for (uint8_t slot = 0; slot < NUM_SLOTS; slot++) {
+			if (!rank_in_ch(ctrl, slot + slot, channel))
+				continue;
+
+			if (!ctrl->restore_mrs)
+				ctrl->mr1[channel][slot] = mr1reg.raw;
+		}
+		reut_issue_mrs_all(ctrl, channel, 1, ctrl->mr1[channel]);
+	}
+}
+
+enum {
+	RTT_WR_OFF = 0,
+	RTT_WR_60  = 1,
+	RTT_WR_120 = 2,
+};
+
+static void ddr3_program_mr2(struct sysinfo *ctrl)
+{
+	assert(ctrl->tCWL >= 5);
+	const bool dimm_srt = ctrl->flags.ext_temp_refresh && !ctrl->flags.asr;
+
+	const union {
+		struct __packed {
+			uint16_t partial_array_sr  : 3; // Bits  0:2
+			uint16_t cas_write_latency : 3; // Bits  5:3
+			uint16_t auto_self_refresh : 1; // Bits  6:6
+			uint16_t self_refresh_temp : 1; // Bits  7:7
+			uint16_t                   : 1; // Bits  8:8
+			uint16_t odt_rtt_wr        : 2; // Bits 10:9
+			uint16_t                   : 5; // Bits 15:11
+		};
+		uint16_t raw;
+	} mr2reg = {
+		.partial_array_sr  = 0,
+		.cas_write_latency = ctrl->tCWL - 5,
+		.auto_self_refresh = ctrl->flags.asr,
+		.self_refresh_temp = dimm_srt,
+		.odt_rtt_wr        = is_hsw_ult() ? RTT_WR_120 : RTT_WR_60,
+	};
+	for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
+		if (!does_ch_exist(ctrl, channel))
+			continue;
+
+		for (uint8_t slot = 0; slot < NUM_SLOTS; slot++) {
+			if (!rank_in_ch(ctrl, slot + slot, channel))
+				continue;
+
+			if (!ctrl->restore_mrs)
+				ctrl->mr2[channel][slot] = mr2reg.raw;
+		}
+		/* MR2 shadow register is similar but not identical to MR2 */
+		if (!ctrl->restore_mrs) {
+			union tc_mr2_shadow_reg tc_mr2_shadow = {
+				.raw = mr2reg.raw & 0x073f,
+			};
+			for (uint8_t slot = 0; slot < NUM_SLOTS; slot++) {
+				if (!rank_in_ch(ctrl, slot + slot, channel))
+					continue;
+
+				if (dimm_srt)
+					tc_mr2_shadow.srt_available |= BIT(slot);
+
+				if (ctrl->rank_mirrored[channel] & BIT(slot + slot + 1))
+					tc_mr2_shadow.addr_bit_swizzle |= BIT(slot);
+			}
+			mchbar_write32(TC_MR2_SHADOW_ch(channel), tc_mr2_shadow.raw);
+		}
+		reut_issue_mrs_all(ctrl, channel, 2, ctrl->mr2[channel]);
+	}
+}
+
+static void ddr3_program_mr3(struct sysinfo *ctrl, const uint8_t mpr_mode)
+{
+	const union {
+		struct __packed {
+			uint16_t mpr_loc  :  2; // Bits  1:0
+			uint16_t mpr_mode :  1; // Bits  2:2
+			uint16_t          : 13; // Bits 15:3
+		};
+		uint16_t raw;
+	} mr3reg = {
+		.mpr_loc  = 0,
+		.mpr_mode = mpr_mode,
+	};
+	for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
+		if (!does_ch_exist(ctrl, channel))
+			continue;
+
+		for (uint8_t slot = 0; slot < NUM_SLOTS; slot++) {
+			if (!rank_in_ch(ctrl, slot + slot, channel))
+				continue;
+
+			if (!ctrl->restore_mrs)
+				ctrl->mr3[channel][slot] = mr3reg.raw;
+		}
+		reut_issue_mrs_all(ctrl, channel, 3, ctrl->mr3[channel]);
+	}
+}
+
+enum raminit_status ddr3_jedec_init(struct sysinfo *ctrl)
+{
+	ddr3_program_mr2(ctrl);
+	ddr3_program_mr3(ctrl, 0);
+	ddr3_program_mr1(ctrl, 0, 0);
+	ddr3_program_mr0(ctrl, 1);
+	return reut_issue_zq(ctrl, ctrl->chanmap, ZQ_INIT);
+}
diff --git a/src/northbridge/intel/haswell/native_raminit/io_comp_control.c b/src/northbridge/intel/haswell/native_raminit/io_comp_control.c
index d45b608dd3..8a55fd81b2 100644
--- a/src/northbridge/intel/haswell/native_raminit/io_comp_control.c
+++ b/src/northbridge/intel/haswell/native_raminit/io_comp_control.c
@@ -8,6 +8,25 @@
 
 #include "raminit_native.h"
 
+enum raminit_status io_reset(void)
+{
+	union mc_init_state_g_reg mc_init_state_g = {
+		.raw = mchbar_read32(MC_INIT_STATE_G),
+	};
+	mc_init_state_g.reset_io = 1;
+	mchbar_write32(MC_INIT_STATE_G, mc_init_state_g.raw);
+	struct stopwatch timer;
+	stopwatch_init_msecs_expire(&timer, 2000);
+	do {
+		mc_init_state_g.raw = mchbar_read32(MC_INIT_STATE_G);
+		if (mc_init_state_g.reset_io == 0)
+			return RAMINIT_STATUS_SUCCESS;
+
+	} while (!stopwatch_expired(&timer));
+	printk(BIOS_ERR, "Timed out waiting for DDR I/O reset to complete\n");
+	return RAMINIT_STATUS_POLL_TIMEOUT;
+}
+
 enum raminit_status wait_for_first_rcomp(void)
 {
 	struct stopwatch timer;
diff --git a/src/northbridge/intel/haswell/native_raminit/jedec_reset.c b/src/northbridge/intel/haswell/native_raminit/jedec_reset.c
new file mode 100644
index 0000000000..de0f676758
--- /dev/null
+++ b/src/northbridge/intel/haswell/native_raminit/jedec_reset.c
@@ -0,0 +1,120 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <console/console.h>
+#include <delay.h>
+#include <northbridge/intel/haswell/haswell.h>
+#include <southbridge/intel/lynxpoint/pch.h>
+#include <types.h>
+#include <timer.h>
+
+#include "raminit_native.h"
+
+static void assert_reset(const bool do_reset)
+{
+	if (is_hsw_ult()) {
+		uint32_t pm_cfg2 = RCBA32(PM_CFG2);
+		if (do_reset)
+			pm_cfg2 &= ~PM_CFG2_DRAM_RESET_CTL;
+		else
+			pm_cfg2 |= PM_CFG2_DRAM_RESET_CTL;
+		RCBA32(PM_CFG2) = pm_cfg2;
+	} else {
+		union mc_init_state_g_reg mc_init_state_g = {
+			.raw = mchbar_read32(MC_INIT_STATE_G),
+		};
+		mc_init_state_g.ddr_not_reset = !do_reset;
+		mchbar_write32(MC_INIT_STATE_G, mc_init_state_g.raw);
+	}
+}
+
+/*
+ * Perform JEDEC reset.
+ *
+ * If RTT_NOM is to be enabled in MR1, the ODT input signal must be
+ * statically held low in our system since RTT_NOM is always enabled.
+ */
+static void jedec_reset(struct sysinfo *ctrl)
+{
+	if (is_hsw_ult())
+		assert_reset(false);
+
+	union mc_init_state_g_reg mc_init_state_g = {
+		.ddr_not_reset     = 1,
+		.safe_self_refresh = 1,
+	};
+	mchbar_write32(MC_INIT_STATE_G, mc_init_state_g.raw);
+
+	union reut_misc_cke_ctrl_reg reut_misc_cke_ctrl = {
+		.cke_override = 0xf,
+		.cke_on       = 0,
+	};
+	mchbar_write32(REUT_MISC_CKE_CTRL, reut_misc_cke_ctrl.raw);
+
+	assert_reset(true);
+
+	/** TODO: check and switch DDR3 voltage here (mainboard-specific) **/
+
+	udelay(200);
+
+	assert_reset(false);
+
+	udelay(500);
+
+	mc_init_state_g.dclk_enable = 1;
+	mchbar_write32(MC_INIT_STATE_G, mc_init_state_g.raw);
+
+	/* Delay at least 20 nanoseconds for tCKSRX */
+	tick_delay(1);
+
+	for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
+		reut_misc_cke_ctrl.cke_on = ctrl->rankmap[channel];
+		mchbar_write32(REUT_ch_MISC_CKE_CTRL(channel), reut_misc_cke_ctrl.raw);
+	}
+
+	/*
+	 * Wait minimum of reset CKE exit time, tXPR.
+	 * Spec says MAX(tXS, 5 tCK). 5 tCK is 10 ns.
+	 */
+	tick_delay(1);
+}
+
+enum raminit_status do_jedec_init(struct sysinfo *ctrl)
+{
+	/* Never do a JEDEC reset in S3 resume */
+	if (ctrl->bootmode == BOOTMODE_S3)
+		return RAMINIT_STATUS_SUCCESS;
+
+	enum raminit_status status = io_reset();
+	if (status)
+		return status;
+
+	status = wait_for_first_rcomp();
+	if (status)
+		return status;
+
+	/* Force ODT low (JEDEC spec) */
+	const union reut_misc_odt_ctrl_reg reut_misc_odt_ctrl = {
+		.odt_override = 0xf,
+		.odt_on       = 0,
+	};
+	mchbar_write32(REUT_MISC_ODT_CTRL, reut_misc_odt_ctrl.raw);
+
+	/*
+	 * Note: Haswell MRC does not clear ODT override for LPDDR3. However,
+	 * Broadwell MRC does. Hell suspects this difference is important, as
+	 * there is an erratum in the specification update for Broadwell:
+	 *
+	 * Erratum BDM74: LPDDR3 Memory Training May Cause Platform Boot Failure
+	 */
+	if (ctrl->lpddr)
+		die("%s: LPDDR-specific JEDEC init not implemented\n", __func__);
+
+	jedec_reset(ctrl);
+	status = ddr3_jedec_init(ctrl);
+	if (!status)
+		ctrl->restore_mrs = true;
+
+	/* Release ODT override */
+	mchbar_write32(REUT_MISC_ODT_CTRL, 0);
+	return status;
+}
diff --git a/src/northbridge/intel/haswell/native_raminit/raminit_main.c b/src/northbridge/intel/haswell/native_raminit/raminit_main.c
index a697343ef9..137a45007d 100644
--- a/src/northbridge/intel/haswell/native_raminit/raminit_main.c
+++ b/src/northbridge/intel/haswell/native_raminit/raminit_main.c
@@ -25,6 +25,7 @@ static const struct task_entry cold_boot[] = {
 	{ convert_timings,                                        true, "CONVTIM",    },
 	{ configure_mc,                                           true, "CONFMC",     },
 	{ configure_memory_map,                                   true, "MEMMAP",     },
+	{ do_jedec_init,                                          true, "JEDECINIT",  },
 };
 
 /* Return a generic stepping value to make stepping checks simpler */
@@ -58,6 +59,7 @@ static void initialize_ctrl(struct sysinfo *ctrl)
 	ctrl->stepping = get_stepping(ctrl->cpu);
 	ctrl->vdd_mv = is_hsw_ult() ? 1350 : 1500; /** FIXME: Hardcoded, does it matter? **/
 	ctrl->dq_pins_interleaved = cfg->dq_pins_interleaved;
+	ctrl->restore_mrs = false;
 	ctrl->bootmode = bootmode;
 }
 
diff --git a/src/northbridge/intel/haswell/native_raminit/raminit_native.h b/src/northbridge/intel/haswell/native_raminit/raminit_native.h
index 8f937c4ccd..759d755d6d 100644
--- a/src/northbridge/intel/haswell/native_raminit/raminit_native.h
+++ b/src/northbridge/intel/haswell/native_raminit/raminit_native.h
@@ -28,6 +28,30 @@
 /* Always use 12 legs for emphasis (not trained) */
 #define TXEQFULLDRV		(3 << 4)
 
+/* DDR3 mode register bits */
+#define MR0_DLL_RESET		BIT(8)
+
+#define MR1_WL_ENABLE		BIT(7)
+#define MR1_QOFF_ENABLE		BIT(12) /* If set, output buffers disabled */
+
+#define RTTNOM_MASK		(BIT(9) | BIT(6) | BIT(2))
+
+/* ZQ calibration types */
+enum {
+	ZQ_INIT,	/* DDR3: ZQCL with tZQinit, LPDDR3: ZQ Init  with tZQinit  */
+	ZQ_LONG,	/* DDR3: ZQCL with tZQoper, LPDDR3: ZQ Long  with tZQCL    */
+	ZQ_SHORT,	/* DDR3: ZQCS with tZQCS,   LPDDR3: ZQ Short with tZQCS    */
+	ZQ_RESET,	/* DDR3: not used,          LPDDR3: ZQ Reset with tZQreset */
+};
+
+/* REUT initialisation modes */
+enum {
+	REUT_MODE_IDLE = 0,
+	REUT_MODE_TEST = 1,
+	REUT_MODE_MRS  = 2,
+	REUT_MODE_NOP  = 3, /* Normal operation mode */
+};
+
 enum command_training_iteration {
 	CT_ITERATION_CLOCK = 0,
 	CT_ITERATION_CMD_NORTH,
@@ -51,6 +75,7 @@ enum raminit_status {
 	RAMINIT_STATUS_UNSUPPORTED_MEMORY,
 	RAMINIT_STATUS_MPLL_INIT_FAILURE,
 	RAMINIT_STATUS_POLL_TIMEOUT,
+	RAMINIT_STATUS_REUT_ERROR,
 	RAMINIT_STATUS_UNSPECIFIED_ERROR, /** TODO: Deprecated in favor of specific values **/
 };
 
@@ -73,6 +98,7 @@ struct sysinfo {
 	uint32_t cpu;		/* CPUID value */
 
 	bool dq_pins_interleaved;
+	bool restore_mrs;
 
 	/** TODO: ECC support untested **/
 	bool is_ecc;
@@ -162,6 +188,11 @@ struct sysinfo {
 	union tc_bank_rank_b_reg tc_bankrank_b[NUM_CHANNELS];
 	union tc_bank_rank_c_reg tc_bankrank_c[NUM_CHANNELS];
 	union tc_bank_rank_d_reg tc_bankrank_d[NUM_CHANNELS];
+
+	uint16_t mr0[NUM_CHANNELS][NUM_SLOTS];
+	uint16_t mr1[NUM_CHANNELS][NUM_SLOTS];
+	uint16_t mr2[NUM_CHANNELS][NUM_SLOTS];
+	uint16_t mr3[NUM_CHANNELS][NUM_SLOTS];
 };
 
 static inline bool is_hsw_ult(void)
@@ -197,6 +228,53 @@ static inline void clear_data_offset_train_all(struct sysinfo *ctrl)
 	memset(ctrl->data_offset_train, 0, sizeof(ctrl->data_offset_train));
 }
 
+/* Number of ticks to wait in units of 69.841279 ns (citation needed) */
+static inline void tick_delay(const uint32_t delay)
+{
+	/* Just perform reads to a random register */
+	for (uint32_t start = 0; start <= delay; start++)
+		mchbar_read32(REUT_ERR_DATA_STATUS);
+}
+
+/*
+ * 64-bit MCHBAR registers need to be accessed atomically. If one uses
+ * two 32-bit ops instead, there will be problems with the REUT's CADB
+ * (Command Address Data Buffer): hardware automatically advances the
+ * pointer into the register file after a write to the input register.
+ */
+static inline uint64_t mchbar_read64(const uintptr_t x)
+{
+	const uint64_t *offset = (uint64_t *)(CONFIG_FIXED_MCHBAR_MMIO_BASE + x);
+	uint64_t mmxsave, v;
+	asm volatile (
+		"\n\t movq %%mm0, %0"
+		"\n\t movq %2, %%mm0"
+		"\n\t movq %%mm0, %1"
+		"\n\t movq %3, %%mm0"
+		"\n\t emms"
+		: "=m"(mmxsave),
+		  "=m"(v)
+		: "m"(offset[0]),
+		  "m"(mmxsave));
+	return v;
+}
+
+static inline void mchbar_write64(const uintptr_t x, const uint64_t v)
+{
+	const uint64_t *offset = (uint64_t *)(CONFIG_FIXED_MCHBAR_MMIO_BASE + x);
+	uint64_t mmxsave;
+	asm volatile (
+		"\n\t movq %%mm0, %0"
+		"\n\t movq %2, %%mm0"
+		"\n\t movq %%mm0, %1"
+		"\n\t movq %3, %%mm0"
+		"\n\t emms"
+		: "=m"(mmxsave)
+		: "m"(offset[0]),
+		  "m"(v),
+		  "m"(mmxsave));
+}
+
 void raminit_main(enum raminit_boot_mode bootmode);
 
 enum raminit_status collect_spd_info(struct sysinfo *ctrl);
@@ -204,6 +282,7 @@ enum raminit_status initialise_mpll(struct sysinfo *ctrl);
 enum raminit_status convert_timings(struct sysinfo *ctrl);
 enum raminit_status configure_mc(struct sysinfo *ctrl);
 enum raminit_status configure_memory_map(struct sysinfo *ctrl);
+enum raminit_status do_jedec_init(struct sysinfo *ctrl);
 
 void configure_timings(struct sysinfo *ctrl);
 void configure_refresh(struct sysinfo *ctrl);
@@ -216,8 +295,28 @@ uint32_t get_tXS_offset(uint32_t mem_clock_mhz);
 uint32_t get_tZQOPER(uint32_t mem_clock_mhz, bool lpddr);
 uint32_t get_tZQCS(uint32_t mem_clock_mhz, bool lpddr);
 
+enum raminit_status io_reset(void);
 enum raminit_status wait_for_first_rcomp(void);
 
+uint16_t encode_ddr3_rttnom(uint32_t rttnom);
+void ddr3_program_mr1(struct sysinfo *ctrl, uint8_t wl_mode, uint8_t q_off);
+enum raminit_status ddr3_jedec_init(struct sysinfo *ctrl);
+
+void reut_issue_mrs(
+	struct sysinfo *ctrl,
+	uint8_t channel,
+	uint8_t rankmask,
+	uint8_t mr,
+	uint16_t val);
+
+void reut_issue_mrs_all(
+	struct sysinfo *ctrl,
+	uint8_t channel,
+	uint8_t mr,
+	const uint16_t val[NUM_SLOTS]);
+
+enum raminit_status reut_issue_zq(struct sysinfo *ctrl, uint8_t chanmask, uint8_t zq_type);
+
 uint8_t get_rx_bias(const struct sysinfo *ctrl);
 
 uint8_t get_tCWL(uint32_t mem_clock_mhz);
diff --git a/src/northbridge/intel/haswell/native_raminit/reg_structs.h b/src/northbridge/intel/haswell/native_raminit/reg_structs.h
index 70487e1640..9929f617fe 100644
--- a/src/northbridge/intel/haswell/native_raminit/reg_structs.h
+++ b/src/northbridge/intel/haswell/native_raminit/reg_structs.h
@@ -335,6 +335,127 @@ union mcscheds_cbit_reg {
 	uint32_t raw;
 };
 
+union reut_pat_cadb_prog_reg {
+	struct __packed {
+		uint32_t addr : 16; // Bits 15:0
+		uint32_t      :  8; // Bits 23:16
+		uint32_t bank :  3; // Bits 26:24
+		uint32_t      :  5; // Bits 31:27
+		uint32_t cs   :  4; // Bits 35:32
+		uint32_t      :  4; // Bits 39:36
+		uint32_t cmd  :  3; // Bits 42:40
+		uint32_t      :  5; // Bits 47:43
+		uint32_t odt  :  4; // Bits 51:48
+		uint32_t      :  4; // Bits 55:52
+		uint32_t cke  :  4; // Bits 59:56
+		uint32_t      :  4; // Bits 63:60
+	};
+	uint64_t raw;
+	uint32_t raw32[2];
+};
+
+union reut_pat_cadb_mrs_reg {
+	struct __packed {
+		uint32_t delay_gap : 3; // Bits  2:0
+		uint32_t           : 5; // Bits  7:3
+		uint32_t start_ptr : 3; // Bits 10:8
+		uint32_t           : 5; // Bits 15:11
+		uint32_t end_ptr   : 3; // Bits 18:16
+		uint32_t           : 5; // Bits 23:19
+		uint32_t curr_ptr  : 3; // Bits 26:24
+		uint32_t           : 5; // Bits 31:27
+	};
+	uint32_t raw;
+};
+
+union reut_seq_cfg_reg {
+	struct __packed {
+		uint32_t                               :  3; // Bits  2:0
+		uint32_t stop_base_seq_on_wrap_trigger :  1; // Bits  3:3
+		uint32_t                               :  1; // Bits  4:4
+		uint32_t address_update_rate_mode      :  1; // Bits  5:5
+		uint32_t                               :  1; // Bits  6:6
+		uint32_t enable_dummy_reads            :  1; // Bits  7:7
+		uint32_t                               :  2; // Bits  9:8
+		uint32_t enable_constant_write_strobe  :  1; // Bits 10:10
+		uint32_t global_control                :  1; // Bits 11:11
+		uint32_t initialization_mode           :  2; // Bits 13:12
+		uint32_t                               :  2; // Bits 15:14
+		uint32_t early_steppings_loop_count    :  5; // Bits 20:16   *** Not on C0 ***
+		uint32_t                               :  3; // Bits 23:21
+		uint32_t subsequence_start_pointer     :  3; // Bits 26:24
+		uint32_t                               :  1; // Bits 27:27
+		uint32_t subsequence_end_pointer       :  3; // Bits 30:28
+		uint32_t                               :  1; // Bits 31:31
+		uint32_t start_test_delay              : 10; // Bits 41:32
+		uint32_t                               : 22; // Bits 63:42
+	};
+	uint64_t raw;
+	uint32_t raw32[2];
+};
+
+union reut_seq_ctl_reg {
+	struct __packed {
+		uint32_t start_test    :  1; // Bits  0:0
+		uint32_t stop_test     :  1; // Bits  1:1
+		uint32_t clear_errors  :  1; // Bits  2:2
+		uint32_t               :  1; // Bits  3:3
+		uint32_t stop_on_error :  1; // Bits  4:4
+		uint32_t               : 27; // Bits 31:5
+	};
+	uint32_t raw;
+};
+
+union reut_global_err_reg {
+	struct __packed {
+		uint32_t ch_error     :  2; // Bits  1:0
+		uint32_t              : 14; // Bits 15:2
+		uint32_t ch_test_done :  2; // Bits 17:16
+		uint32_t              : 14; // Bits 31:18
+	};
+	uint32_t raw;
+};
+
+union reut_misc_cke_ctrl_reg {
+	struct __packed {
+		uint32_t cke_override           :  4; // Bits  3:0
+		uint32_t                        :  4; // Bits  7:4
+		uint32_t cke_en_start_test_sync :  1; // Bits  8:8
+		uint32_t                        :  7; // Bits 15:9
+		uint32_t cke_on                 :  4; // Bits 19:16
+		uint32_t                        : 12; // Bits 31:20
+	};
+	uint32_t raw;
+};
+
+union reut_misc_odt_ctrl_reg {
+	struct __packed {
+		uint32_t odt_override     :  4; // Bits  3:0
+		uint32_t                  : 12; // Bits 15:4
+		uint32_t odt_on           :  4; // Bits 19:16
+		uint32_t                  : 11; // Bits 30:20
+		uint32_t mpr_train_ddr_on :  1; // Bits 31:31
+	};
+	uint32_t raw;
+};
+
+union mcscheds_dft_misc_reg {
+	struct __packed {
+		uint32_t wdar                 :  1; // Bits  0:0
+		uint32_t safe_mask_sel        :  3; // Bits  3:1
+		uint32_t force_rcv_en         :  1; // Bits  4:4
+		uint32_t                      :  3; // Bits  7:5
+		uint32_t ddr_qualifier        :  2; // Bits  9:8
+		uint32_t qualifier_length     :  2; // Bits 11:10
+		uint32_t wdb_block_en         :  1; // Bits 12:12
+		uint32_t rt_dft_read_ptr      :  4; // Bits 16:13
+		uint32_t rt_dft_read_enable   :  1; // Bits 17:17
+		uint32_t rt_dft_read_sel_addr :  1; // Bits 18:18
+		uint32_t                      : 13; // Bits 31:19
+	};
+	uint32_t raw;
+};
+
 union tc_bank_reg {
 	struct __packed {
 		uint32_t tRCD      : 5; // Bits  4:0
@@ -428,6 +549,18 @@ union tc_srftp_reg {
 	uint32_t raw;
 };
 
+union tc_mr2_shadow_reg {
+	struct __packed {
+		uint32_t mr2_shadow_low   :  6; // Bits  5:0
+		uint32_t srt_available    :  2; // Bits  7:6
+		uint32_t mr2_shadow_high  :  3; // Bits 10:8
+		uint32_t                  :  3; // Bits 13:11
+		uint32_t addr_bit_swizzle :  2; // Bits 15:14
+		uint32_t                  : 16; // Bits 31:16
+	};
+	uint32_t raw;
+};
+
 union mcmain_command_rate_limit_reg {
 	struct __packed {
 		uint32_t enable_cmd_limit :  1; // Bits  0:0
@@ -483,6 +616,27 @@ union mad_zr_reg {
 	uint32_t raw;
 };
 
+union mc_init_state_g_reg {
+	struct __packed {
+		uint32_t pu_mrc_done        :  1; // Bits  0:0
+		uint32_t ddr_not_reset      :  1; // Bits  1:1
+		uint32_t                    :  1; // Bits  2:2
+		uint32_t refresh_enable     :  1; // Bits  3:3
+		uint32_t                    :  1; // Bits  4:4
+		uint32_t mc_init_done_ack   :  1; // Bits  5:5
+		uint32_t                    :  1; // Bits  6:6
+		uint32_t mrc_done           :  1; // Bits  7:7
+		uint32_t safe_self_refresh  :  1; // Bits  8:8
+		uint32_t                    :  1; // Bits  9:9
+		uint32_t hvm_gate_ddr_reset :  1; // Bits 10:10
+		uint32_t                    : 11; // Bits 21:11
+		uint32_t dclk_enable        :  1; // Bits 22:22
+		uint32_t reset_io           :  1; // Bits 23:23
+		uint32_t                    :  8; // Bits 31:24
+	};
+	uint32_t raw;
+};
+
 /* Same definition for P_COMP, M_COMP, D_COMP */
 union pcu_comp_reg {
 	struct __packed {
diff --git a/src/northbridge/intel/haswell/native_raminit/reut.c b/src/northbridge/intel/haswell/native_raminit/reut.c
new file mode 100644
index 0000000000..31019f74a1
--- /dev/null
+++ b/src/northbridge/intel/haswell/native_raminit/reut.c
@@ -0,0 +1,196 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <console/console.h>
+#include <delay.h>
+#include <northbridge/intel/haswell/haswell.h>
+#include <timer.h>
+#include <types.h>
+
+#include "raminit_native.h"
+
+enum {
+	CADB_CMD_MRS = 0,
+	CADB_CMD_REF = 1,
+	CADB_CMD_PRE = 2,
+	CADB_CMD_ACT = 3,
+	CADB_CMD_WR  = 4,
+	CADB_CMD_RD  = 5,
+	CADB_CMD_ZQ  = 6,
+	CADB_CMD_NOP = 7,
+};
+
+/*
+ * DDR3 rank mirror swaps the following pins: A3<->A4, A5<->A6, A7<->A8, BA0<->BA1
+ *
+ * Note that the swapped bits are contiguous. We can use some XOR magic to swap the bits.
+ * Address lanes are at bits 0..15 and bank selects are at bits 24..26 on the REUT register.
+ */
+#define MIRROR_BITS	(BIT(24) | BIT(7) | BIT(5) | BIT(3))
+static uint64_t cadb_prog_rank_mirror(const uint64_t cadb_prog)
+{
+	/* First XOR: find which pairs of bits are different (need swapping) */
+	const uint64_t tmp64 = (cadb_prog ^ (cadb_prog >> 1)) & MIRROR_BITS;
+
+	/* Second XOR: invert the pairs of bits that have different values */
+	return cadb_prog ^ (tmp64 | tmp64 << 1);
+}
+
+static enum raminit_status reut_write_cadb_cmd(
+	struct sysinfo *ctrl,
+	const uint8_t channel,
+	const uint8_t rankmask,
+	const uint8_t cmd,
+	const uint8_t bank,
+	const uint16_t valarr[NUM_SLOTRANKS],
+	const uint8_t delay)
+{
+	union mcscheds_dft_misc_reg dft_misc = {
+		.raw = mchbar_read32(MCSCHEDS_DFT_MISC),
+	};
+	dft_misc.ddr_qualifier = 0;
+	mchbar_write32(MCSCHEDS_DFT_MISC, dft_misc.raw);
+
+	/* Pointer will be dynamically incremented after a write to CADB_PROG register */
+	mchbar_write8(REUT_ch_PAT_CADB_WRITE_PTR(channel), 0);
+
+	uint8_t count = 0;
+	for (uint8_t rank = 0; rank < NUM_SLOTRANKS; rank++) {
+		if (!(ctrl->rankmap[channel] & BIT(rank) & rankmask))
+			continue;
+
+		union reut_pat_cadb_prog_reg reut_cadb_prog = {
+			.addr = valarr[rank],
+			.bank = bank,
+			.cs   = ~BIT(rank), /* CS is active low */
+			.cmd  = cmd,
+			.cke  = 0xf,
+		};
+		if (ctrl->rank_mirrored[channel] & BIT(rank))
+			reut_cadb_prog.raw = cadb_prog_rank_mirror(reut_cadb_prog.raw);
+
+		mchbar_write64(REUT_ch_PAT_CADB_PROG(channel), reut_cadb_prog.raw);
+		count++;
+	}
+	if (!count) {
+		printk(BIOS_ERR, "%s: rankmask is invalid\n", __func__);
+		return RAMINIT_STATUS_UNSPECIFIED_ERROR;	/** FIXME: Is this needed? **/
+	}
+	const union reut_pat_cadb_mrs_reg reut_cadb_mrs = {
+		.delay_gap = delay ? delay : 3,
+		.end_ptr   = count - 1,
+	};
+	mchbar_write32(REUT_ch_PAT_CADB_MRS(channel), reut_cadb_mrs.raw);
+
+	const uint32_t reut_seq_cfg_save = mchbar_read32(REUT_ch_SEQ_CFG(channel));
+	union reut_seq_cfg_reg reut_seq_cfg = {
+		.raw = reut_seq_cfg_save,
+	};
+	reut_seq_cfg.global_control = 0;
+	reut_seq_cfg.initialization_mode = REUT_MODE_MRS;
+	mchbar_write32(REUT_ch_SEQ_CFG(channel), reut_seq_cfg.raw);
+	mchbar_write32(REUT_ch_SEQ_CTL(channel), (union reut_seq_ctl_reg) {
+		.start_test   = 1,
+		.clear_errors = 1,
+	}.raw);
+	enum raminit_status status = RAMINIT_STATUS_SUCCESS;
+	union reut_global_err_reg reut_global_err;
+	struct stopwatch timer;
+	stopwatch_init_msecs_expire(&timer, 100);
+	do {
+		reut_global_err.raw = mchbar_read32(REUT_GLOBAL_ERR);
+		if (reut_global_err.ch_error & BIT(channel)) {
+			printk(BIOS_ERR, "Unexpected REUT error for channel %u\n", channel);
+			status = RAMINIT_STATUS_REUT_ERROR;
+			break;
+		}
+		if (stopwatch_expired(&timer)) {
+			printk(BIOS_ERR, "%s: REUT timed out!\n", __func__);
+			status = RAMINIT_STATUS_POLL_TIMEOUT;
+			break;
+		}
+	} while (!(reut_global_err.ch_test_done & BIT(channel)));
+	mchbar_write32(REUT_ch_SEQ_CTL(channel), (union reut_seq_ctl_reg) {
+		.clear_errors = 1,
+	}.raw);
+	mchbar_write32(REUT_ch_SEQ_CFG(channel), reut_seq_cfg_save);
+	return status;
+}
+
+static enum raminit_status reut_write_cadb_cmd_all(
+	struct sysinfo *ctrl,
+	const uint8_t channel,
+	const uint8_t rankmask,
+	const uint8_t cmd,
+	const uint8_t bank,
+	const uint16_t val,
+	const uint8_t delay)
+{
+	const uint16_t valarr[NUM_SLOTRANKS] = { val, val, val, val };
+	return reut_write_cadb_cmd(ctrl, channel, rankmask, cmd, bank, valarr, delay);
+}
+
+void reut_issue_mrs(
+	struct sysinfo *ctrl,
+	const uint8_t channel,
+	const uint8_t rankmask,
+	const uint8_t mr,
+	const uint16_t val)
+{
+	reut_write_cadb_cmd_all(ctrl, channel, rankmask, CADB_CMD_MRS, mr, val, 0);
+}
+
+void reut_issue_mrs_all(
+	struct sysinfo *ctrl,
+	const uint8_t channel,
+	const uint8_t mr,
+	const uint16_t val[NUM_SLOTS])
+{
+	const uint16_t valarr[NUM_SLOTRANKS] = { val[0], val[0], val[1], val[1] };
+	reut_write_cadb_cmd(ctrl, channel, 0xf, CADB_CMD_MRS, mr, valarr, 0);
+}
+
+enum raminit_status reut_issue_zq(struct sysinfo *ctrl, uint8_t chanmask, uint8_t zq_type)
+{
+	/** TODO: Issuing ZQ commands differs for LPDDR **/
+	if (ctrl->lpddr)
+		die("%s: LPDDR not yet supported in ZQ calibration\n", __func__);
+
+	__maybe_unused uint8_t opcode; /* NOTE: Only used for LPDDR */
+	uint16_t zq = 0;
+	switch (zq_type) {
+	case ZQ_INIT:
+		zq = BIT(10);
+		opcode = 0xff;
+		break;
+	case ZQ_LONG:
+		zq = BIT(10);
+		opcode = 0xab;
+		break;
+	case ZQ_SHORT:
+		opcode = 0x56;
+		break;
+	case ZQ_RESET:
+		opcode = 0xc3;
+		break;
+	default:
+		die("%s: ZQ type %u is invalid\n", __func__, zq_type);
+	}
+
+	/* ZQCS on single-channel needs a longer delay */
+	const uint8_t delay = zq_type == ZQ_SHORT && (!ctrl->dpc[0] || !ctrl->dpc[1]) ? 7 : 1;
+	enum raminit_status status = RAMINIT_STATUS_SUCCESS;
+	for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
+		if (!(BIT(channel) & chanmask) || !does_ch_exist(ctrl, channel))
+			continue;
+
+		status = reut_write_cadb_cmd_all(ctrl, channel, 0xf, CADB_CMD_ZQ, 0, zq, delay);
+		if (status)
+			break;
+	}
+
+	/* Wait a bit after ZQ INIT and ZQCL commands */
+	if (zq)
+		udelay(1);
+
+	return status;
+}
diff --git a/src/northbridge/intel/haswell/registers/mchbar.h b/src/northbridge/intel/haswell/registers/mchbar.h
index 2acc5cbbc8..4fc78a7f43 100644
--- a/src/northbridge/intel/haswell/registers/mchbar.h
+++ b/src/northbridge/intel/haswell/registers/mchbar.h
@@ -96,15 +96,36 @@
 
 #define SC_WR_ADD_DELAY_ch(ch)			_MCMAIN_C(0x40d0, ch)
 
+#define REUT_ch_MISC_CKE_CTRL(ch)		_MCMAIN_C(0x4190, ch)
+
+#define REUT_ch_PAT_CADB_MRS(ch)		_MCMAIN_C(0x419c, ch)
+
+#define REUT_ch_PAT_CADB_WRITE_PTR(ch)		_MCMAIN_C(0x41bc, ch)
+#define REUT_ch_PAT_CADB_PROG(ch)		_MCMAIN_C(0x41c0, ch)
+
 #define TC_ZQCAL_ch(ch)				_MCMAIN_C(0x4290, ch)
 #define TC_RFP_ch(ch)				_MCMAIN_C(0x4294, ch)
 #define TC_RFTP_ch(ch)				_MCMAIN_C(0x4298, ch)
+#define TC_MR2_SHADOW_ch(ch)			_MCMAIN_C(0x429c, ch)
 #define MC_INIT_STATE_ch(ch)			_MCMAIN_C(0x42a0, ch)
 #define TC_SRFTP_ch(ch)				_MCMAIN_C(0x42a4, ch)
 
+#define REUT_GLOBAL_ERR				0x4804
+
+#define REUT_ch_SEQ_CFG(ch)			(0x48a8 + 8 * (ch))
+
+#define REUT_ch_SEQ_CTL(ch)			(0x48b8 + 4 * (ch))
+
 /* MCMAIN broadcast */
 #define MCSCHEDS_CBIT		0x4c20
 
+#define MCSCHEDS_DFT_MISC	0x4c30
+
+#define REUT_ERR_DATA_STATUS	0x4ce0
+
+#define REUT_MISC_CKE_CTRL	0x4d90
+#define REUT_MISC_ODT_CTRL	0x4d94
+
 #define MCMNTS_SC_WDBWM		0x4f8c
 
 /* MCDECS */
diff --git a/src/southbridge/intel/lynxpoint/pch.h b/src/southbridge/intel/lynxpoint/pch.h
index c64b3e3e10..3abca6ec9d 100644
--- a/src/southbridge/intel/lynxpoint/pch.h
+++ b/src/southbridge/intel/lynxpoint/pch.h
@@ -586,6 +586,8 @@ void mainboard_config_rcba(void);
 #define ACPIIRQEN	0x31e0	/* 32bit */
 #define OIC		0x31fe	/* 16bit */
 #define PRSTS		0x3310	/* 32bit */
+#define PM_CFG2		0x333c	/* 32bit */
+#define  PM_CFG2_DRAM_RESET_CTL	(1 << 26)	/* ULT only */
 #define PMSYNC_CONFIG	0x33c4	/* 32bit */
 #define PMSYNC_CONFIG2	0x33cc	/* 32bit */
 #define SOFT_RESET_CTRL 0x38f4

From 9d0897a0bc98e8b400c88b2a099c2ffe8d21b8e6 Mon Sep 17 00:00:00 2001
From: Angel Pons <th3fanbus@gmail.com>
Date: Sat, 7 May 2022 23:12:18 +0200
Subject: [PATCH 0306/3886] haswell NRI: Add pre-training steps

Implement pre-training steps, which consist of enabling ECC I/O and
filling the WDB (Write Data Buffer, stores test patterns) through a
magic LDAT port.

Change-Id: Ie2e09e3b218c4569ed8de5c5e1b05d491032e0f1
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64190
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 .../intel/haswell/native_raminit/Makefile.mk  |   1 +
 .../haswell/native_raminit/raminit_main.c     |  35 ++++
 .../haswell/native_raminit/raminit_native.h   |  24 +++
 .../haswell/native_raminit/reg_structs.h      |  45 +++++
 .../intel/haswell/native_raminit/setup_wdb.c  | 159 ++++++++++++++++++
 .../intel/haswell/registers/mchbar.h          |   9 +
 6 files changed, 273 insertions(+)
 create mode 100644 src/northbridge/intel/haswell/native_raminit/setup_wdb.c

diff --git a/src/northbridge/intel/haswell/native_raminit/Makefile.mk b/src/northbridge/intel/haswell/native_raminit/Makefile.mk
index e9212df9e6..8d7d4e4db0 100644
--- a/src/northbridge/intel/haswell/native_raminit/Makefile.mk
+++ b/src/northbridge/intel/haswell/native_raminit/Makefile.mk
@@ -10,5 +10,6 @@ romstage-y += memory_map.c
 romstage-y += raminit_main.c
 romstage-y += raminit_native.c
 romstage-y += reut.c
+romstage-y += setup_wdb.c
 romstage-y += spd_bitmunching.c
 romstage-y += timings_refresh.c
diff --git a/src/northbridge/intel/haswell/native_raminit/raminit_main.c b/src/northbridge/intel/haswell/native_raminit/raminit_main.c
index 137a45007d..cbc64315cd 100644
--- a/src/northbridge/intel/haswell/native_raminit/raminit_main.c
+++ b/src/northbridge/intel/haswell/native_raminit/raminit_main.c
@@ -3,6 +3,7 @@
 #include <assert.h>
 #include <console/console.h>
 #include <cpu/intel/haswell/haswell.h>
+#include <delay.h>
 #include <device/pci_ops.h>
 #include <northbridge/intel/haswell/chip.h>
 #include <northbridge/intel/haswell/haswell.h>
@@ -13,6 +14,39 @@
 
 #include "raminit_native.h"
 
+static enum raminit_status pre_training(struct sysinfo *ctrl)
+{
+	/* Skip on S3 resume */
+	if (ctrl->bootmode == BOOTMODE_S3)
+		return RAMINIT_STATUS_SUCCESS;
+
+	for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
+		for (uint8_t slot = 0; slot < NUM_SLOTS; slot++) {
+			if (!rank_in_ch(ctrl, slot + slot, channel))
+				continue;
+
+			printk(RAM_DEBUG, "C%uS%u:\n", channel, slot);
+			printk(RAM_DEBUG, "\tMR0: 0x%04x\n", ctrl->mr0[channel][slot]);
+			printk(RAM_DEBUG, "\tMR1: 0x%04x\n", ctrl->mr1[channel][slot]);
+			printk(RAM_DEBUG, "\tMR2: 0x%04x\n", ctrl->mr2[channel][slot]);
+			printk(RAM_DEBUG, "\tMR3: 0x%04x\n", ctrl->mr3[channel][slot]);
+			printk(RAM_DEBUG, "\n");
+		}
+		if (ctrl->is_ecc) {
+			union mad_dimm_reg mad_dimm = {
+				.raw = mchbar_read32(MAD_DIMM(channel)),
+			};
+			/* Enable ECC I/O */
+			mad_dimm.ecc_mode = 1;
+			mchbar_write32(MAD_DIMM(channel), mad_dimm.raw);
+			/* Wait 4 usec after enabling the ECC I/O, needed by HW */
+			udelay(4);
+		}
+	}
+	setup_wdb(ctrl);
+	return RAMINIT_STATUS_SUCCESS;
+}
+
 struct task_entry {
 	enum raminit_status (*task)(struct sysinfo *);
 	bool is_enabled;
@@ -26,6 +60,7 @@ static const struct task_entry cold_boot[] = {
 	{ configure_mc,                                           true, "CONFMC",     },
 	{ configure_memory_map,                                   true, "MEMMAP",     },
 	{ do_jedec_init,                                          true, "JEDECINIT",  },
+	{ pre_training,                                           true, "PRETRAIN",   },
 };
 
 /* Return a generic stepping value to make stepping checks simpler */
diff --git a/src/northbridge/intel/haswell/native_raminit/raminit_native.h b/src/northbridge/intel/haswell/native_raminit/raminit_native.h
index 759d755d6d..4d9487d79c 100644
--- a/src/northbridge/intel/haswell/native_raminit/raminit_native.h
+++ b/src/northbridge/intel/haswell/native_raminit/raminit_native.h
@@ -36,6 +36,13 @@
 
 #define RTTNOM_MASK		(BIT(9) | BIT(6) | BIT(2))
 
+#define BASIC_VA_PAT_SPREAD_8	0x01010101
+
+#define WDB_CACHE_LINE_SIZE	8
+
+#define NUM_WDB_CL_MUX_SEEDS	3
+#define NUM_CADB_MUX_SEEDS	3
+
 /* ZQ calibration types */
 enum {
 	ZQ_INIT,	/* DDR3: ZQCL with tZQinit, LPDDR3: ZQ Init  with tZQinit  */
@@ -317,6 +324,23 @@ void reut_issue_mrs_all(
 
 enum raminit_status reut_issue_zq(struct sysinfo *ctrl, uint8_t chanmask, uint8_t zq_type);
 
+void write_wdb_fixed_pat(
+	const struct sysinfo *ctrl,
+	const uint8_t patterns[],
+	const uint8_t pat_mask[],
+	uint8_t spread,
+	uint16_t start);
+
+void write_wdb_va_pat(
+	const struct sysinfo *ctrl,
+	uint32_t agg_mask,
+	uint32_t vic_mask,
+	uint8_t vic_rot,
+	uint16_t start);
+
+void program_wdb_lfsr(const struct sysinfo *ctrl, bool cleanup);
+void setup_wdb(const struct sysinfo *ctrl);
+
 uint8_t get_rx_bias(const struct sysinfo *ctrl);
 
 uint8_t get_tCWL(uint32_t mem_clock_mhz);
diff --git a/src/northbridge/intel/haswell/native_raminit/reg_structs.h b/src/northbridge/intel/haswell/native_raminit/reg_structs.h
index 9929f617fe..7aa8d8c8b2 100644
--- a/src/northbridge/intel/haswell/native_raminit/reg_structs.h
+++ b/src/northbridge/intel/haswell/native_raminit/reg_structs.h
@@ -335,6 +335,18 @@ union mcscheds_cbit_reg {
 	uint32_t raw;
 };
 
+union reut_pat_cl_mux_lmn_reg {
+	struct __packed {
+		uint32_t l_data_select : 1; // Bits  0:0
+		uint32_t en_sweep_freq : 1; // Bits  1:1
+		uint32_t               : 6; // Bits  7:2
+		uint32_t l_counter     : 8; // Bits 15:8
+		uint32_t m_counter     : 8; // Bits 23:16
+		uint32_t n_counter     : 8; // Bits 31:24
+	};
+	uint32_t raw;
+};
+
 union reut_pat_cadb_prog_reg {
 	struct __packed {
 		uint32_t addr : 16; // Bits 15:0
@@ -439,6 +451,39 @@ union reut_misc_odt_ctrl_reg {
 	uint32_t raw;
 };
 
+union ldat_pdat_reg {
+	struct __packed {
+		uint32_t fast_addr : 12; // Bits 11:0
+		uint32_t           :  4; // Bits 15:12
+		uint32_t addr_en   :  1; // Bits 16:16
+		uint32_t seq_en    :  1; // Bits 17:17
+		uint32_t pol_0     :  1; // Bits 18:18
+		uint32_t pol_1     :  1; // Bits 19:19
+		uint32_t cmd_a     :  4; // Bits 23:20
+		uint32_t cmd_b     :  4; // Bits 27:24
+		uint32_t cmd_c     :  4; // Bits 31:28
+	};
+	uint32_t raw;
+};
+
+union ldat_sdat_reg {
+	struct __packed {
+		uint32_t bank_sel   : 4; // Bits  3:0
+		uint32_t            : 1; // Bits  4:4
+		uint32_t array_sel  : 5; // Bits  9:5
+		uint32_t cmp        : 1; // Bits 10:10
+		uint32_t replicate  : 1; // Bits 11:11
+		uint32_t dword      : 4; // Bits 15:12
+		uint32_t mode       : 2; // Bits 17:16
+		uint32_t mpmap      : 6; // Bits 23:18
+		uint32_t mpb_offset : 4; // Bits 27:24
+		uint32_t stage_en   : 1; // Bits 28:28
+		uint32_t shadow     : 2; // Bits 30:29
+		uint32_t            : 1; // Bits 31:31
+	};
+	uint32_t raw;
+};
+
 union mcscheds_dft_misc_reg {
 	struct __packed {
 		uint32_t wdar                 :  1; // Bits  0:0
diff --git a/src/northbridge/intel/haswell/native_raminit/setup_wdb.c b/src/northbridge/intel/haswell/native_raminit/setup_wdb.c
new file mode 100644
index 0000000000..ec37c48415
--- /dev/null
+++ b/src/northbridge/intel/haswell/native_raminit/setup_wdb.c
@@ -0,0 +1,159 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <northbridge/intel/haswell/haswell.h>
+#include <types.h>
+
+#include "raminit_native.h"
+
+static void ldat_write_cacheline(
+	const struct sysinfo *const ctrl,
+	const uint8_t chunk,
+	const uint16_t start,
+	const uint64_t data)
+{
+	for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
+		if (!does_ch_exist(ctrl, channel))
+			continue;
+
+		/*
+		 * Do not do a 64-bit write here. The register is not aligned
+		 * to a 64-bit boundary, which could potentially cause issues.
+		 */
+		mchbar_write32(QCLK_ch_LDAT_DATA_IN_x(channel, 0), data & UINT32_MAX);
+		mchbar_write32(QCLK_ch_LDAT_DATA_IN_x(channel, 1), data >> 32);
+		/*
+		 * Set REPLICATE = 0 as you don't want to replicate the data.
+		 * Set BANK_SEL to the chunk you want to write the 64 bits to.
+		 * Set ARRAY_SEL = 0 (the MC WDB) and MODE = 1.
+		 */
+		const union ldat_sdat_reg ldat_sdat = {
+			.bank_sel = chunk,
+			.mode     = 1,
+		};
+		mchbar_write32(QCLK_ch_LDAT_SDAT(channel), ldat_sdat.raw);
+		/*
+		 * Finally, write the PDAT register indicating which cacheline
+		 * of the WDB you want to write to by setting FAST_ADDR field
+		 * to one of the 64 cache lines. Also set CMD_B in the PDAT
+		 * register to 4'b1000, indicating that this is a LDAT write.
+		 */
+		const union ldat_pdat_reg ldat_pdat = {
+			.fast_addr = MIN(start, 0xfff),
+			.cmd_b     = 8,
+		};
+		mchbar_write32(QCLK_ch_LDAT_PDAT(channel), ldat_pdat.raw);
+	}
+}
+
+static void clear_ldat_mode(const struct sysinfo *const ctrl)
+{
+	for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++)
+		mchbar_write32(QCLK_ch_LDAT_SDAT(channel), 0);
+}
+
+void write_wdb_fixed_pat(
+	const struct sysinfo *const ctrl,
+	const uint8_t patterns[],
+	const uint8_t pat_mask[],
+	const uint8_t spread,
+	const uint16_t start)
+{
+	for (uint8_t chunk = 0; chunk < WDB_CACHE_LINE_SIZE; chunk++) {
+		uint64_t data = 0;
+		for (uint8_t b = 0; b < 64; b++) {
+			const uint8_t beff  = b % spread;
+			const uint8_t burst = patterns[pat_mask[beff]];
+			if (burst & BIT(chunk))
+				data |= 1ULL << b;
+		}
+		ldat_write_cacheline(ctrl, chunk, start, data);
+	}
+	clear_ldat_mode(ctrl);
+}
+
+static inline uint32_t rol_u32(const uint32_t val)
+{
+	return (val << 1) | ((val >> 31) & 1);
+}
+
+void write_wdb_va_pat(
+	const struct sysinfo *const ctrl,
+	const uint32_t agg_mask,
+	const uint32_t vic_mask,
+	const uint8_t vic_rot,
+	const uint16_t start)
+{
+	static const uint8_t va_mask_to_compressed[4] = {0xaa, 0xc0, 0xcc, 0xf0};
+	uint32_t v_mask = vic_mask;
+	uint32_t a_mask = agg_mask;
+	for (uint8_t v = 0; v < vic_rot; v++) {
+		uint8_t compressed[32] = {0};
+		/* Iterate through all 32 bits and create a compressed version of cacheline */
+		for (uint8_t b = 0; b < ARRAY_SIZE(compressed); b++) {
+			const uint8_t vic = !!(v_mask & BIT(b));
+			const uint8_t agg = !!(a_mask & BIT(b));
+			const uint8_t index = !vic << 1 | agg << 0;
+			compressed[b] = va_mask_to_compressed[index];
+		}
+		for (uint8_t chunk = 0; chunk < WDB_CACHE_LINE_SIZE; chunk++) {
+			uint32_t data = 0;
+			for (uint8_t b = 0; b < ARRAY_SIZE(compressed); b++)
+				data |= !!(compressed[b] & BIT(chunk)) << b;
+
+			const uint64_t data64 = (uint64_t)data << 32 | data;
+			ldat_write_cacheline(ctrl, chunk, start + v, data64);
+		}
+		v_mask = rol_u32(v_mask);
+		a_mask = rol_u32(a_mask);
+	}
+	clear_ldat_mode(ctrl);
+}
+
+void program_wdb_lfsr(const struct sysinfo *ctrl, const bool cleanup)
+{
+	/* Cleanup LFSR seeds are sequential */
+	const uint32_t cleanup_seeds[NUM_WDB_CL_MUX_SEEDS] = { 0xaaaaaa, 0xcccccc, 0xf0f0f0 };
+	const uint32_t regular_seeds[NUM_WDB_CL_MUX_SEEDS] = { 0xa10ca1, 0xef0d08, 0xad0a1e };
+	const uint32_t *seeds = cleanup ? cleanup_seeds : regular_seeds;
+
+	for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
+		if (!does_ch_exist(ctrl, channel))
+			continue;
+
+		for (uint8_t i = 0; i < NUM_WDB_CL_MUX_SEEDS; i++) {
+			mchbar_write32(REUT_ch_PAT_WDB_CL_MUX_RD_x(channel, i), seeds[i]);
+			mchbar_write32(REUT_ch_PAT_WDB_CL_MUX_WR_x(channel, i), seeds[i]);
+		}
+	}
+}
+
+void setup_wdb(const struct sysinfo *ctrl)
+{
+	const uint32_t amask[9] = {
+		0x86186186, 0x18618618, 0x30c30c30,
+		0xa28a28a2, 0x8a28a28a, 0x14514514,
+		0x28a28a28, 0x92492492, 0x24924924,
+	};
+	const uint32_t vmask = 0x41041041;
+
+	/* Fill first 8 entries with simple 2-LFSR VA pattern */
+	write_wdb_va_pat(ctrl, 0, BASIC_VA_PAT_SPREAD_8, 8, 0);
+
+	/* Fill next 54 entries with 3-LFSR VA pattern */
+	for (uint8_t a = 0; a < ARRAY_SIZE(amask); a++)
+		write_wdb_va_pat(ctrl, amask[a], vmask, 6, 8 + a * 6);
+
+	program_wdb_lfsr(ctrl, false);
+	for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
+		if (!does_ch_exist(ctrl, channel))
+			continue;
+
+		const union reut_pat_cl_mux_lmn_reg wdb_cl_mux_lmn = {
+			.en_sweep_freq = 1,
+			.l_counter     = 1,
+			.m_counter     = 1,
+			.n_counter     = 10,
+		};
+		mchbar_write32(REUT_ch_PAT_WDB_CL_MUX_LMN(channel), wdb_cl_mux_lmn.raw);
+	}
+}
diff --git a/src/northbridge/intel/haswell/registers/mchbar.h b/src/northbridge/intel/haswell/registers/mchbar.h
index 4fc78a7f43..f8408e51a0 100644
--- a/src/northbridge/intel/haswell/registers/mchbar.h
+++ b/src/northbridge/intel/haswell/registers/mchbar.h
@@ -94,6 +94,11 @@
 #define TC_BANK_RANK_D_ch(ch)			_MCMAIN_C(0x4014, ch)
 #define SC_ROUNDT_LAT_ch(ch)			_MCMAIN_C(0x4024, ch)
 
+#define REUT_ch_PAT_WDB_CL_MUX_WR_x(ch, x)	_MCMAIN_C_X(0x4048, ch, x) /* x in 0 .. 2 */
+#define REUT_ch_PAT_WDB_CL_MUX_RD_x(ch, x)	_MCMAIN_C_X(0x4054, ch, x) /* x in 0 .. 2 */
+
+#define REUT_ch_PAT_WDB_CL_MUX_LMN(ch)		_MCMAIN_C(0x4078, ch)
+
 #define SC_WR_ADD_DELAY_ch(ch)			_MCMAIN_C(0x40d0, ch)
 
 #define REUT_ch_MISC_CKE_CTRL(ch)		_MCMAIN_C(0x4190, ch)
@@ -110,6 +115,10 @@
 #define MC_INIT_STATE_ch(ch)			_MCMAIN_C(0x42a0, ch)
 #define TC_SRFTP_ch(ch)				_MCMAIN_C(0x42a4, ch)
 
+#define QCLK_ch_LDAT_PDAT(ch)			_MCMAIN_C(0x42d0, ch)
+#define QCLK_ch_LDAT_SDAT(ch)			_MCMAIN_C(0x42d4, ch)
+#define QCLK_ch_LDAT_DATA_IN_x(ch, x)		_MCMAIN_C_X(0x42dc, ch, x) /* x in 0 .. 1 */
+
 #define REUT_GLOBAL_ERR				0x4804
 
 #define REUT_ch_SEQ_CFG(ch)			(0x48a8 + 8 * (ch))

From 726269858322fd1fd1910e4b3deb593a04bdf7b9 Mon Sep 17 00:00:00 2001
From: Angel Pons <th3fanbus@gmail.com>
Date: Sun, 8 May 2022 00:11:29 +0200
Subject: [PATCH 0307/3886] haswell NRI: Add REUT I/O test library

Implement a library to run I/O tests using the REUT hardware.

Change-Id: Id7b207cd0a3989ddd23c88c6b1f0cfa79d2c861f
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64191
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
---
 .../intel/haswell/native_raminit/Makefile.mk  |   1 +
 .../haswell/native_raminit/raminit_native.h   | 110 +++
 .../haswell/native_raminit/reg_structs.h      | 121 +++
 .../intel/haswell/native_raminit/testing_io.c | 744 ++++++++++++++++++
 .../intel/haswell/registers/mchbar.h          |  30 +
 5 files changed, 1006 insertions(+)
 create mode 100644 src/northbridge/intel/haswell/native_raminit/testing_io.c

diff --git a/src/northbridge/intel/haswell/native_raminit/Makefile.mk b/src/northbridge/intel/haswell/native_raminit/Makefile.mk
index 8d7d4e4db0..6e1b365602 100644
--- a/src/northbridge/intel/haswell/native_raminit/Makefile.mk
+++ b/src/northbridge/intel/haswell/native_raminit/Makefile.mk
@@ -12,4 +12,5 @@ romstage-y += raminit_native.c
 romstage-y += reut.c
 romstage-y += setup_wdb.c
 romstage-y += spd_bitmunching.c
+romstage-y += testing_io.c
 romstage-y += timings_refresh.c
diff --git a/src/northbridge/intel/haswell/native_raminit/raminit_native.h b/src/northbridge/intel/haswell/native_raminit/raminit_native.h
index 4d9487d79c..f029e7f076 100644
--- a/src/northbridge/intel/haswell/native_raminit/raminit_native.h
+++ b/src/northbridge/intel/haswell/native_raminit/raminit_native.h
@@ -59,6 +59,88 @@ enum {
 	REUT_MODE_NOP  = 3, /* Normal operation mode */
 };
 
+/* REUT error counter control */
+enum {
+	COUNT_ERRORS_PER_CHANNEL	= 0,
+	COUNT_ERRORS_PER_LANE		= 1,
+	COUNT_ERRORS_PER_BYTE_GROUP	= 2,
+	COUNT_ERRORS_PER_CHUNK		= 3,
+};
+
+enum wdb_dq_pattern {
+	BASIC_VA = 0,
+	SEGMENT_WDB,
+	CADB,
+	TURN_AROUND,
+	LMN_VA,
+	TURN_AROUND_WR,
+	TURN_AROUND_ODT,
+	RD_RD_TA,
+	RD_RD_TA_ALL,
+};
+
+enum reut_cmd_pat {
+	PAT_WR_RD,
+	PAT_WR,
+	PAT_RD,
+	PAT_RD_WR_TA,
+	PAT_WR_RD_TA,
+	PAT_ODT_TA,
+};
+
+/* REUT subsequence types (B = Base, O = Offset) */
+enum {
+	SUBSEQ_B_RD	= 0 << 22,
+	SUBSEQ_B_WR	= 1 << 22,
+	SUBSEQ_B_RD_WR	= 2 << 22,
+	SUBSEQ_B_WR_RD	= 3 << 22,
+	SUBSEQ_O_RD	= 4 << 22,
+	SUBSEQ_O_WR	= 5 << 22,
+};
+
+/* REUT mux control */
+enum {
+	REUT_MUX_LMN      = 0,
+	REUT_MUX_BTBUFFER = 1,
+	REUT_MUX_LFSR     = 2,
+};
+
+/* Increment scale */
+enum {
+	SCALE_LOGARITHM	= 0,
+	SCALE_LINEAR	= 1,
+};
+
+enum test_stop {
+	NSOE   = 0,	/* Never stop on error */
+	NTHSOE = 1,	/* Stop on the nth error (we use n = 1) */
+	ABGSOE = 2,	/* Stop on all byte groups error */
+	ALSOE  = 3,	/* Stop on all lanes error */
+};
+
+struct wdb_pat {
+	uint32_t start_ptr;	/* Starting pointer in WDB */
+	uint32_t stop_ptr;	/* Stopping pointer in WDB */
+	uint16_t inc_rate;	/* How quickly the WDB walks through cachelines */
+	uint8_t  dq_pattern;	/* DQ pattern to use (see enum wdb_dq_pattern above) */
+};
+
+struct reut_pole {
+	uint16_t start;
+	uint16_t stop;
+	uint16_t order;
+	uint32_t inc_rate;
+	uint16_t inc_val;
+	bool wrap_trigger;
+};
+
+struct reut_box {
+	struct reut_pole rank;
+	struct reut_pole bank;
+	struct reut_pole row;
+	struct reut_pole col;
+};
+
 enum command_training_iteration {
 	CT_ITERATION_CLOCK = 0,
 	CT_ITERATION_CMD_NORTH,
@@ -200,6 +282,10 @@ struct sysinfo {
 	uint16_t mr1[NUM_CHANNELS][NUM_SLOTS];
 	uint16_t mr2[NUM_CHANNELS][NUM_SLOTS];
 	uint16_t mr3[NUM_CHANNELS][NUM_SLOTS];
+
+	uint8_t dq_pat;
+
+	uint8_t dq_pat_lc;
 };
 
 static inline bool is_hsw_ult(void)
@@ -341,6 +427,30 @@ void write_wdb_va_pat(
 void program_wdb_lfsr(const struct sysinfo *ctrl, bool cleanup);
 void setup_wdb(const struct sysinfo *ctrl);
 
+void program_seq_addr(uint8_t channel, const struct reut_box *reut_addr, bool log_seq_addr);
+void program_loop_count(const struct sysinfo *ctrl, uint8_t channel, uint8_t lc_exp);
+
+void setup_io_test(
+	struct sysinfo *ctrl,
+	uint8_t chanmask,
+	enum reut_cmd_pat cmd_pat,
+	uint16_t num_cl,
+	uint8_t lc,
+	const struct reut_box *reut_addr,
+	enum test_stop soe,
+	const struct wdb_pat *pat,
+	uint8_t en_cadb,
+	uint8_t subseq_wait);
+
+void setup_io_test_cadb(struct sysinfo *ctrl, uint8_t chanmask, uint8_t lc, enum test_stop soe);
+void setup_io_test_basic_va(struct sysinfo *ctrl, uint8_t chm, uint8_t lc, enum test_stop soe);
+void setup_io_test_mpr(struct sysinfo *ctrl, uint8_t chanmask, uint8_t lc, enum test_stop soe);
+
+uint8_t select_reut_ranks(struct sysinfo *ctrl, uint8_t channel, uint8_t rankmask);
+
+void run_mpr_io_test(bool clear_errors);
+uint8_t run_io_test(struct sysinfo *ctrl, uint8_t chanmask, uint8_t dq_pat, bool clear_errors);
+
 uint8_t get_rx_bias(const struct sysinfo *ctrl);
 
 uint8_t get_tCWL(uint32_t mem_clock_mhz);
diff --git a/src/northbridge/intel/haswell/native_raminit/reg_structs.h b/src/northbridge/intel/haswell/native_raminit/reg_structs.h
index 7aa8d8c8b2..b943259b91 100644
--- a/src/northbridge/intel/haswell/native_raminit/reg_structs.h
+++ b/src/northbridge/intel/haswell/native_raminit/reg_structs.h
@@ -347,6 +347,54 @@ union reut_pat_cl_mux_lmn_reg {
 	uint32_t raw;
 };
 
+union reut_err_ctl_reg {
+	struct __packed {
+		uint32_t stop_on_nth_error              : 6; // Bits  5:0
+		uint32_t                                : 6; // Bits 11:6
+		uint32_t stop_on_error_control          : 2; // Bits 13:12
+		uint32_t                                : 2; // Bits 15:14
+		uint32_t selective_err_enable_chunk     : 8; // Bits 23:16
+		uint32_t selective_err_enable_cacheline : 8; // Bits 31:24
+	};
+	uint32_t raw;
+};
+
+union reut_pat_cadb_mux_ctrl_reg {
+	struct __packed {
+		uint32_t mux_0_ctrl     : 2; // Bits  1:0
+		uint32_t                : 2; // Bits  3:2
+		uint32_t mux_1_ctrl     : 2; // Bits  5:4
+		uint32_t                : 2; // Bits  7:6
+		uint32_t mux_2_ctrl     : 2; // Bits  9:8
+		uint32_t                : 6; // Bits 15:10
+		uint32_t sel_mux_0_ctrl : 2; // Bits 17:16
+		uint32_t                : 2; // Bits 19:18
+		uint32_t sel_mux_1_ctrl : 2; // Bits 21:20
+		uint32_t                : 2; // Bits 23:22
+		uint32_t sel_mux_2_ctrl : 2; // Bits 25:24
+		uint32_t                : 6; // Bits 31:26
+	};
+	uint32_t raw;
+};
+
+union reut_pat_wdb_cl_mux_cfg_reg {
+	struct __packed {
+		uint32_t mux_0_control         : 2; // Bits  1:0
+		uint32_t                       : 1; // Bits  2:2
+		uint32_t mux_1_control         : 2; // Bits  4:3
+		uint32_t                       : 1; // Bits  5:5
+		uint32_t mux_2_control         : 2; // Bits  7:6
+		uint32_t                       : 6; // Bits 13:8
+		uint32_t ecc_replace_byte_ctl  : 1; // Bits 14:14
+		uint32_t ecc_data_source_sel   : 1; // Bits 15:15
+		uint32_t save_lfsr_seed_rate   : 6; // Bits 21:16
+		uint32_t                       : 2; // Bits 23:22
+		uint32_t reload_lfsr_seed_rate : 3; // Bits 26:24
+		uint32_t                       : 5; // Bits 31:27
+	};
+	uint32_t raw;
+};
+
 union reut_pat_cadb_prog_reg {
 	struct __packed {
 		uint32_t addr : 16; // Bits 15:0
@@ -366,6 +414,19 @@ union reut_pat_cadb_prog_reg {
 	uint32_t raw32[2];
 };
 
+union reut_pat_wdb_cl_ctrl_reg {
+	struct __packed {
+		uint32_t inc_rate  :  5; // Bits 4:0
+		uint32_t inc_scale :  1; // Bits 5:5
+		uint32_t           :  2; // Bits 7:6
+		uint32_t start_ptr :  6; // Bits 13:8
+		uint32_t           :  2; // Bits 15:14
+		uint32_t end_ptr   :  6; // Bits 21:16
+		uint32_t           : 10; // Bits 31:22
+	};
+	uint32_t raw;
+};
+
 union reut_pat_cadb_mrs_reg {
 	struct __packed {
 		uint32_t delay_gap : 3; // Bits  2:0
@@ -406,6 +467,66 @@ union reut_seq_cfg_reg {
 	uint32_t raw32[2];
 };
 
+union reut_seq_base_addr_reg {
+	struct __packed {
+		uint32_t           :  3; // Bits  2:0
+		uint32_t col_addr  :  8; // Bits 10:3
+		uint32_t           : 13; // Bits 23:11
+		uint32_t row_addr  : 16; // Bits 39:24
+		uint32_t           :  8; // Bits 47:40
+		uint32_t bank_addr :  3; // Bits 50:48
+		uint32_t           :  5; // Bits 55:51
+		uint32_t rank_addr :  3; // Bits 58:56
+		uint32_t           :  5; // Bits 63:59
+	};
+	uint32_t raw32[2];
+	uint64_t raw;
+};
+
+union reut_seq_misc_ctl_reg {
+	struct __packed {
+		uint32_t col_addr_order       : 2; // Bits  1:0
+		uint32_t row_addr_order       : 2; // Bits  3:2
+		uint32_t bank_addr_order      : 2; // Bits  5:4
+		uint32_t rank_addr_order      : 2; // Bits  7:6
+		uint32_t                      : 5; // Bits 12:8
+		uint32_t addr_invert_rate     : 3; // Bits 15:13
+		uint32_t                      : 4; // Bits 19:16
+		uint32_t col_addr_invert_en   : 1; // Bits 20:20
+		uint32_t row_addr_invert_en   : 1; // Bits 21:21
+		uint32_t bank_addr_invert_en  : 1; // Bits 22:22
+		uint32_t rank_addr_invert_en  : 1; // Bits 23:23
+		uint32_t col_wrap_trigger_en  : 1; // Bits 24:24
+		uint32_t row_wrap_trigger_en  : 1; // Bits 25:25
+		uint32_t bank_wrap_trigger_en : 1; // Bits 26:26
+		uint32_t rank_wrap_trigger_en : 1; // Bits 27:27
+		uint32_t col_wrap_carry_en    : 1; // Bits 28:28
+		uint32_t row_wrap_carry_en    : 1; // Bits 29:29
+		uint32_t bank_wrap_carry_en   : 1; // Bits 30:30
+		uint32_t rank_wrap_carry_en   : 1; // Bits 31:31
+	};
+	uint32_t raw;
+};
+
+union reut_seq_addr_inc_ctl_reg {
+	struct __packed {
+		uint32_t                     :  3; // Bits  2:0
+		uint32_t col_addr_increment  :  8; // Bits 10:3
+		uint32_t                     :  1; // Bits 11:11
+		uint32_t col_addr_update     :  8; // Bits 19:12
+		uint32_t row_addr_increment  : 12; // Bits 31:20
+		uint32_t row_addr_update     :  6; // Bits 37:32
+		uint32_t bank_addr_increment :  3; // Bits 40:38
+		uint32_t                     :  3; // Bits 43:41
+		uint32_t bank_addr_update    :  8; // Bits 53:44
+		uint32_t rank_addr_increment :  3; // Bits 54:52
+		uint32_t                     :  1; // Bits 55:55
+		uint32_t rank_addr_update    :  8; // Bits 63:56
+	};
+	uint64_t raw;
+	uint32_t raw32[2];
+};
+
 union reut_seq_ctl_reg {
 	struct __packed {
 		uint32_t start_test    :  1; // Bits  0:0
diff --git a/src/northbridge/intel/haswell/native_raminit/testing_io.c b/src/northbridge/intel/haswell/native_raminit/testing_io.c
new file mode 100644
index 0000000000..2632c238f8
--- /dev/null
+++ b/src/northbridge/intel/haswell/native_raminit/testing_io.c
@@ -0,0 +1,744 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <console/console.h>
+#include <delay.h>
+#include <lib.h>
+#include <northbridge/intel/haswell/haswell.h>
+#include <timer.h>
+#include <types.h>
+
+#include "raminit_native.h"
+
+static void set_cadb_patterns(const uint8_t channel, const uint16_t seeds[NUM_CADB_MUX_SEEDS])
+{
+	for (uint8_t i = 0; i < NUM_CADB_MUX_SEEDS; i++)
+		mchbar_write32(REUT_ch_PAT_CADB_MUX_x(channel, i), seeds[i]);
+}
+
+static void setup_cadb(
+	struct sysinfo *ctrl,
+	const uint8_t channel,
+	const uint8_t vic_spread,
+	const uint8_t vic_bit)
+{
+	const bool lmn_en = false;
+
+	/*
+	 * Currently, always start writing at CADB row 0.
+	 * Could add a start point parameter in the future.
+	 */
+	mchbar_write8(REUT_ch_PAT_CADB_WRITE_PTR(channel), 0);
+	const uint8_t num_cadb_rows = 8;
+	for (uint8_t row = 0; row < num_cadb_rows; row++) {
+		const uint8_t lfsr0 = (row >> 0) & 1;
+		const uint8_t lfsr1 = (row >> 1) & 1;
+		uint64_t reg64 = 0;
+		for (uint8_t bit = 0; bit < 22; bit++) {
+			uint8_t bremap;
+			if (bit >= 19) {
+				/* (bremap in 40 .. 42) => CADB data control */
+				bremap = bit + 21;
+			} else if (bit >= 16) {
+				/* (bremap in 24 .. 26) => CADB data bank */
+				bremap = bit + 8;
+			} else {
+				/* (bremap in  0 .. 15) => CADB data address */
+				bremap = bit;
+			}
+			const uint8_t fine = bit % vic_spread;
+			reg64 |= ((uint64_t)(fine == vic_bit ? lfsr0 : lfsr1)) << bremap;
+		}
+		/*
+		 * Write row. CADB pointer is auto incremented after every write. This must be
+		 * a single 64-bit write, otherwise the CADB pointer will auto-increment twice.
+		 */
+		mchbar_write64(REUT_ch_PAT_CADB_PROG(channel), reg64);
+	}
+	const union reut_pat_cadb_mux_ctrl_reg cadb_mux_ctrl = {
+		.mux_0_ctrl = lmn_en ? REUT_MUX_LMN : REUT_MUX_LFSR,
+		.mux_1_ctrl = REUT_MUX_LFSR,
+		.mux_2_ctrl = REUT_MUX_LFSR,
+	};
+	mchbar_write32(REUT_ch_PAT_CADB_MUX_CTRL(channel), cadb_mux_ctrl.raw);
+	const union reut_pat_cl_mux_lmn_reg cadb_cl_mux_lmn = {
+		.en_sweep_freq = 1,
+		.l_counter     = 1,
+		.m_counter     = 1,
+		.n_counter     = 6,
+	};
+	mchbar_write32(REUT_ch_PAT_CADB_CL_MUX_LMN(channel), cadb_cl_mux_lmn.raw);
+	const uint16_t cadb_mux_seeds[NUM_CADB_MUX_SEEDS] = { 0x0ea1, 0xbeef, 0xdead };
+	set_cadb_patterns(channel, cadb_mux_seeds);
+}
+
+static uint32_t calc_rate(const uint32_t rate, const uint32_t lim, const uint8_t scale_bit)
+{
+	return rate > lim ? log2_ceil(rate - 1) : BIT(scale_bit) | rate;
+}
+
+void program_seq_addr(
+	const uint8_t channel,
+	const struct reut_box *reut_addr,
+	const bool log_seq_addr)
+{
+	const int loglevel = log_seq_addr ? BIOS_ERR : BIOS_NEVER;
+	const uint32_t div = 8;
+	union reut_seq_base_addr_reg reut_seq_addr_start = {
+		.col_addr  = reut_addr->col.start / div,
+		.row_addr  = reut_addr->row.start,
+		.bank_addr = reut_addr->bank.start,
+		.rank_addr = reut_addr->rank.start,
+	};
+	mchbar_write64(REUT_ch_SEQ_ADDR_START(channel), reut_seq_addr_start.raw);
+	reut_seq_addr_start.raw = mchbar_read64(REUT_ch_SEQ_ADDR_START(channel));
+	printk(loglevel, "\tStart column:     %u\n", reut_seq_addr_start.col_addr);
+	printk(loglevel, "\tStart row:        %u\n", reut_seq_addr_start.row_addr);
+	printk(loglevel, "\tStart bank:       %u\n", reut_seq_addr_start.bank_addr);
+	printk(loglevel, "\tStart rank:       %u\n", reut_seq_addr_start.rank_addr);
+	printk(loglevel, "\n");
+
+	union reut_seq_base_addr_reg reut_seq_addr_stop = {
+		.col_addr  = reut_addr->col.stop / div,
+		.row_addr  = reut_addr->row.stop,
+		.bank_addr = reut_addr->bank.stop,
+		.rank_addr = reut_addr->rank.stop,
+	};
+	mchbar_write64(REUT_ch_SEQ_ADDR_WRAP(channel), reut_seq_addr_stop.raw);
+	reut_seq_addr_stop.raw = mchbar_read64(REUT_ch_SEQ_ADDR_WRAP(channel));
+	printk(loglevel, "\tStop column:      %u\n", reut_seq_addr_stop.col_addr);
+	printk(loglevel, "\tStop row:         %u\n", reut_seq_addr_stop.row_addr);
+	printk(loglevel, "\tStop bank:        %u\n", reut_seq_addr_stop.bank_addr);
+	printk(loglevel, "\tStop rank:        %u\n", reut_seq_addr_stop.rank_addr);
+	printk(loglevel, "\n");
+
+	union reut_seq_misc_ctl_reg reut_seq_misc_ctl = {
+		.col_wrap_trigger_en  = reut_addr->col.wrap_trigger,
+		.row_wrap_trigger_en  = reut_addr->row.wrap_trigger,
+		.bank_wrap_trigger_en = reut_addr->bank.wrap_trigger,
+		.rank_wrap_trigger_en = reut_addr->rank.wrap_trigger,
+	};
+	mchbar_write32(REUT_ch_SEQ_MISC_CTL(channel), reut_seq_misc_ctl.raw);
+	printk(loglevel, "\tWrap column:      %u\n", reut_addr->col.wrap_trigger);
+	printk(loglevel, "\tWrap row:         %u\n", reut_addr->row.wrap_trigger);
+	printk(loglevel, "\tWrap bank:        %u\n", reut_addr->bank.wrap_trigger);
+	printk(loglevel, "\tWrap rank:        %u\n", reut_addr->rank.wrap_trigger);
+	printk(loglevel, "\n");
+
+	union reut_seq_addr_inc_ctl_reg reut_seq_addr_inc_ctl = {
+		.col_addr_update  = calc_rate(reut_addr->col.inc_rate,  31, 7),
+		.row_addr_update  = calc_rate(reut_addr->row.inc_rate,  15, 5),
+		.bank_addr_update = calc_rate(reut_addr->bank.inc_rate, 31, 7),
+		.rank_addr_update = calc_rate(reut_addr->rank.inc_rate, 31, 7),
+		.col_addr_increment  = reut_addr->col.inc_val,
+		.row_addr_increment  = reut_addr->row.inc_val,
+		.bank_addr_increment = reut_addr->bank.inc_val,
+		.rank_addr_increment = reut_addr->rank.inc_val,
+	};
+	printk(loglevel, "\tUpdRate column:   %u\n", reut_addr->col.inc_rate);
+	printk(loglevel, "\tUpdRate row:      %u\n", reut_addr->row.inc_rate);
+	printk(loglevel, "\tUpdRate bank:     %u\n", reut_addr->bank.inc_rate);
+	printk(loglevel, "\tUpdRate rank:     %u\n", reut_addr->rank.inc_rate);
+	printk(loglevel, "\n");
+	printk(loglevel, "\tUpdRateCR column: %u\n", reut_seq_addr_inc_ctl.col_addr_update);
+	printk(loglevel, "\tUpdRateCR row:    %u\n", reut_seq_addr_inc_ctl.row_addr_update);
+	printk(loglevel, "\tUpdRateCR bank:   %u\n", reut_seq_addr_inc_ctl.bank_addr_update);
+	printk(loglevel, "\tUpdRateCR rank:   %u\n", reut_seq_addr_inc_ctl.rank_addr_update);
+	printk(loglevel, "\n");
+	printk(loglevel, "\tUpdInc column:    %u\n", reut_seq_addr_inc_ctl.col_addr_increment);
+	printk(loglevel, "\tUpdInc row:       %u\n", reut_seq_addr_inc_ctl.row_addr_increment);
+	printk(loglevel, "\tUpdInc bank:      %u\n", reut_seq_addr_inc_ctl.bank_addr_increment);
+	printk(loglevel, "\tUpdInc rank:      %u\n", reut_seq_addr_inc_ctl.rank_addr_increment);
+	printk(loglevel, "\n");
+	mchbar_write64(REUT_ch_SEQ_ADDR_INC_CTL(channel), reut_seq_addr_inc_ctl.raw);
+}
+
+/*
+ * Early steppings take exponential (base 2) loopcount values,
+ * but later steppings take linear loopcount values elsewhere.
+ * Address the differences in register offset and format here.
+ */
+void program_loop_count(const struct sysinfo *ctrl, const uint8_t channel, const uint8_t lc_exp)
+{
+	if (ctrl->stepping >= STEPPING_C0) {
+		const uint32_t loopcount = lc_exp >= 32 ? 0 : BIT(lc_exp);
+		mchbar_write32(HSW_REUT_ch_SEQ_LOOP_COUNT(channel), loopcount);
+	} else {
+		const uint8_t loopcount = lc_exp >= 32 ? 0 : lc_exp + 1;
+		union reut_seq_cfg_reg reut_seq_cfg = {
+			.raw = mchbar_read64(REUT_ch_SEQ_CFG(channel)),
+		};
+		reut_seq_cfg.early_steppings_loop_count = loopcount;
+		mchbar_write64(REUT_ch_SEQ_CFG(channel), reut_seq_cfg.raw);
+	}
+}
+
+static inline void write_subseq(const uint8_t channel, const uint8_t idx, const uint32_t ssq)
+{
+	mchbar_write32(REUT_ch_SUBSEQ_x_CTL(channel, idx), ssq);
+}
+
+static void program_subseq(
+	struct sysinfo *const ctrl,
+	const uint8_t channel,
+	const enum reut_cmd_pat cmd_pat,
+	const uint32_t ss_a,
+	const uint32_t ss_b)
+{
+	switch (cmd_pat) {
+	case PAT_WR_RD_TA:
+		write_subseq(channel, 0, ss_a | SUBSEQ_B_WR);
+		for (uint8_t i = 1; i < 7; i++)
+			write_subseq(channel, i, ss_b | SUBSEQ_B_RD_WR);
+
+		write_subseq(channel, 7, ss_a | SUBSEQ_B_RD);
+		break;
+	case PAT_RD_WR_TA:
+		write_subseq(channel, 0, ss_b | SUBSEQ_B_WR_RD);
+		break;
+	case PAT_ODT_TA:
+		write_subseq(channel, 0, ss_a | SUBSEQ_B_WR);
+		write_subseq(channel, 1, ss_b | SUBSEQ_B_RD_WR);
+		write_subseq(channel, 2, ss_a | SUBSEQ_B_RD);
+		write_subseq(channel, 3, ss_b | SUBSEQ_B_WR_RD);
+		break;
+	default:
+		write_subseq(channel, 0, ss_a | SUBSEQ_B_WR);
+		write_subseq(channel, 1, ss_a | SUBSEQ_B_RD);
+		break;
+	}
+}
+
+void setup_io_test(
+	struct sysinfo *ctrl,
+	const uint8_t chanmask,
+	const enum reut_cmd_pat cmd_pat,
+	const uint16_t num_cl,
+	const uint8_t lc,
+	const struct reut_box *const reut_addr,
+	const enum test_stop soe,
+	const struct wdb_pat *const pat,
+	const uint8_t en_cadb,
+	const uint8_t subseq_wait)
+{
+	if (!chanmask) {
+		printk(BIOS_ERR, "\n%s: chanmask is invalid\n", __func__);
+		return;
+	}
+
+	/*
+	 * Prepare variables needed for both channels.
+	 * Check for the cases where this MUST be 1: when
+	 * we manually walk through subseq ODT and TA Wr.
+	 */
+	uint8_t lc_exp = MAX(lc - log2_ceil(num_cl), 0);
+	if (cmd_pat == PAT_WR_RD_TA || cmd_pat == PAT_ODT_TA)
+		lc_exp = 0;
+
+	uint8_t num_clcr;
+	if (num_cl > 127) {
+		/* Assume exponential number */
+		num_clcr = log2_ceil(num_cl);
+	} else {
+		/* Set number of cache lines as linear number */
+		num_clcr = num_cl | BIT(7);
+	}
+
+	const uint16_t num_cl2 = 2 * num_cl;
+	uint8_t num_cl2cr;
+	if (num_cl2 > 127) {
+		/* Assume exponential number */
+		num_cl2cr = log2_ceil(num_cl2);
+	} else {
+		/* Set number of cache lines as linear number */
+		num_cl2cr = num_cl2 | BIT(7);
+	}
+
+	for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
+		if (!(chanmask & BIT(channel))) {
+			union reut_seq_cfg_reg reut_seq_cfg = {
+				.raw = mchbar_read64(REUT_ch_SEQ_CFG(channel)),
+			};
+			reut_seq_cfg.global_control = 0;
+			mchbar_write64(REUT_ch_SEQ_CFG(channel), reut_seq_cfg.raw);
+			continue;
+		}
+
+		/*
+		 * Program CADB
+		 */
+		mchbar_write8(REUT_ch_MISC_PAT_CADB_CTRL(channel), !!en_cadb);
+		if (en_cadb)
+			setup_cadb(ctrl, channel, 7, 8);
+
+		/*
+		 * Program sequence
+		 */
+		uint8_t subseq_start = 0;
+		uint8_t subseq_end   = 0;
+		switch (cmd_pat) {
+		case PAT_WR_RD:
+			subseq_end = 1;
+			break;
+		case PAT_WR:
+			break;
+		case PAT_RD:
+			subseq_start = 1;
+			subseq_end   = 1;
+			break;
+		case PAT_RD_WR_TA:
+			break;
+		case PAT_WR_RD_TA:
+			subseq_end = 7;
+			break;
+		case PAT_ODT_TA:
+			subseq_end = 3;
+			break;
+		default:
+			die("\n%s: Pattern type %u is invalid\n", __func__, cmd_pat);
+		}
+		const union reut_seq_cfg_reg reut_seq_cfg = {
+			.global_control            = 1,
+			.initialization_mode       = REUT_MODE_TEST,
+			.subsequence_start_pointer = subseq_start,
+			.subsequence_end_pointer   = subseq_end,
+			.start_test_delay          = 2,
+		};
+		mchbar_write64(REUT_ch_SEQ_CFG(channel), reut_seq_cfg.raw);
+		program_loop_count(ctrl, channel, lc_exp);
+		mchbar_write32(REUT_ch_SEQ_CTL(channel), (union reut_seq_ctl_reg) {
+			.clear_errors = 1,
+		}.raw);
+
+		/*
+		 * Program subsequences
+		 */
+		uint32_t subseq_a = 0;
+
+		/* Number of cachelines and scale */
+		subseq_a |= (num_clcr    & 0x00ff) << 0;
+		subseq_a |= (subseq_wait & 0x3fff) << 8;
+
+		/* Reset current base address to start */
+		subseq_a |= BIT(27);
+
+		uint32_t subseq_b = 0;
+
+		/* Number of cachelines and scale */
+		subseq_b |= (num_cl2cr   & 0x00ff) << 0;
+		subseq_b |= (subseq_wait & 0x3fff) << 8;
+
+		/* Reset current base address to start */
+		subseq_b |= BIT(27);
+
+		program_subseq(ctrl, channel, cmd_pat, subseq_a, subseq_b);
+
+		/* Program sequence address */
+		program_seq_addr(channel, reut_addr, false);
+
+		/* Program WDB */
+		const bool is_linear = pat->inc_rate < 32;
+		mchbar_write32(REUT_ch_WDB_CL_CTRL(channel), (union reut_pat_wdb_cl_ctrl_reg) {
+			.start_ptr = pat->start_ptr,
+			.end_ptr   = pat->stop_ptr,
+			.inc_rate  = is_linear ? pat->inc_rate : log2_ceil(pat->inc_rate),
+			.inc_scale = is_linear,
+		}.raw);
+
+		/* Enable LMN in LMN or CADB modes, used to create lots of supply noise */
+		const bool use_lmn = pat->dq_pattern == LMN_VA || pat->dq_pattern == CADB;
+		union reut_pat_wdb_cl_mux_cfg_reg pat_wdb_cl_mux_cfg = {
+			.mux_0_control = use_lmn ? REUT_MUX_LMN : REUT_MUX_LFSR,
+			.mux_1_control = REUT_MUX_LFSR,
+			.mux_2_control = REUT_MUX_LFSR,
+			.ecc_data_source_sel = 1,
+		};
+
+		/* Program LFSR save/restore, too complex unless everything is power of 2 */
+		if (cmd_pat == PAT_ODT_TA || cmd_pat == PAT_WR_RD_TA) {
+			pat_wdb_cl_mux_cfg.reload_lfsr_seed_rate = log2_ceil(num_cl) + 1;
+			pat_wdb_cl_mux_cfg.save_lfsr_seed_rate   = 1;
+		}
+		mchbar_write32(REUT_ch_PAT_WDB_CL_MUX_CFG(channel), pat_wdb_cl_mux_cfg.raw);
+
+		/* Inversion mask is not used */
+		mchbar_write32(REUT_ch_PAT_WDB_INV(channel), 0);
+
+		/* Program error checking */
+		const union reut_err_ctl_reg reut_err_ctl = {
+			.selective_err_enable_cacheline = 0xff,
+			.selective_err_enable_chunk     = 0xff,
+			.stop_on_error_control          = soe,
+			.stop_on_nth_error              = 1,
+		};
+		mchbar_write32(REUT_ch_ERR_CONTROL(channel), reut_err_ctl.raw);
+		mchbar_write64(REUT_ch_ERR_DATA_MASK(channel), 0);
+		mchbar_write8(REUT_ch_ERR_ECC_MASK(channel), 0);
+	}
+
+	/* Always do a ZQ short before the beginning of a test */
+	reut_issue_zq(ctrl, chanmask, ZQ_SHORT);
+}
+
+void setup_io_test_cadb(
+	struct sysinfo *ctrl,
+	const uint8_t chanmask,
+	const uint8_t lc,
+	const enum test_stop soe)
+{
+	const struct reut_box reut_addr = {
+		.rank = {
+			.start    = 0,
+			.stop     = 0,
+			.inc_rate = 32,
+			.inc_val  = 1,
+		},
+		.bank = {
+			.start    = 0,
+			.stop     = 7,
+			.inc_rate = 3,
+			.inc_val  = 1,
+		},
+		.row = {
+			.start    = 0,
+			.stop     = 2047,
+			.inc_rate = 3,
+			.inc_val  = 73,
+		},
+		.col = {
+			.start    = 0,
+			.stop     = 1023,
+			.inc_rate = 0,
+			.inc_val  = 53,
+		},
+	};
+	const struct wdb_pat pattern = {
+		.start_ptr  = 0,
+		.stop_ptr   = 9,
+		.inc_rate   = 4,
+		.dq_pattern = CADB,
+	};
+	setup_io_test(
+		ctrl,
+		chanmask,
+		PAT_WR_RD,
+		128,
+		lc,
+		&reut_addr,
+		soe,
+		&pattern,
+		1,
+		0);
+
+	ctrl->dq_pat_lc = MAX(lc - 2 - 3, 0) + 1;
+	ctrl->dq_pat = CADB;
+}
+
+void setup_io_test_basic_va(
+	struct sysinfo *ctrl,
+	const uint8_t chanmask,
+	const uint8_t lc,
+	const enum test_stop soe)
+{
+	const uint32_t spread = 8;
+	const struct reut_box reut_addr = {
+		.rank = {
+			.start    = 0,
+			.stop     = 0,
+			.inc_rate = 32,
+			.inc_val  = 1,
+		},
+		.col = {
+			.start    = 0,
+			.stop     = 1023,
+			.inc_rate = 0,
+			.inc_val  = 1,
+		},
+	};
+	const struct wdb_pat pattern = {
+		.start_ptr  = 0,
+		.stop_ptr   = spread - 1,
+		.inc_rate   = 4,
+		.dq_pattern = BASIC_VA,
+	};
+	setup_io_test(
+		ctrl,
+		chanmask,
+		PAT_WR_RD,
+		128,
+		lc,
+		&reut_addr,
+		soe,
+		&pattern,
+		0,
+		0);
+
+	ctrl->dq_pat_lc = MAX(lc - 8, 0) + 1;
+	ctrl->dq_pat = BASIC_VA;
+}
+
+void setup_io_test_mpr(
+	struct sysinfo *ctrl,
+	const uint8_t chanmask,
+	const uint8_t lc,
+	const enum test_stop soe)
+{
+	const struct reut_box reut_addr_ddr = {
+		.rank = {
+			.start    = 0,
+			.stop     = 0,
+			.inc_rate = 32,
+			.inc_val  = 1,
+		},
+		.col = {
+			.start    = 0,
+			.stop     = 1023,
+			.inc_rate = 0,
+			.inc_val  = 1,
+		},
+	};
+	const struct reut_box reut_addr_lpddr = {
+		.bank = {
+			.start    = 4,
+			.stop     = 4,
+			.inc_rate = 0,
+			.inc_val  = 0,
+		},
+	};
+	const struct wdb_pat pattern = {
+		.start_ptr  = 0,
+		.stop_ptr   = 9,
+		.inc_rate   = 4,
+		.dq_pattern = BASIC_VA,
+	};
+	setup_io_test(
+		ctrl,
+		chanmask,
+		PAT_RD,
+		128,
+		lc,
+		ctrl->lpddr ? &reut_addr_lpddr : &reut_addr_ddr,
+		soe,
+		&pattern,
+		0,
+		0);
+
+	ctrl->dq_pat_lc = 1;
+	ctrl->dq_pat = BASIC_VA;
+}
+
+uint8_t select_reut_ranks(struct sysinfo *ctrl, const uint8_t channel, uint8_t rankmask)
+{
+	rankmask &= ctrl->rankmap[channel];
+
+	uint8_t rank_count = 0;
+	uint32_t rank_log_to_phys = 0;
+	for (uint8_t rank = 0; rank < NUM_SLOTRANKS; rank++) {
+		if (!rank_in_mask(rank, rankmask))
+			continue;
+
+		rank_log_to_phys |= rank << (4 * rank_count);
+		rank_count++;
+	}
+	mchbar_write32(REUT_ch_RANK_LOG_TO_PHYS(channel), rank_log_to_phys);
+
+	union reut_seq_cfg_reg reut_seq_cfg = {
+		.raw = mchbar_read64(REUT_ch_SEQ_CFG(channel)),
+	};
+	if (!rank_count) {
+		reut_seq_cfg.global_control = 0;
+		mchbar_write64(REUT_ch_SEQ_CFG(channel), reut_seq_cfg.raw);
+		return 0;
+	}
+	union reut_seq_base_addr_reg reut_seq_addr_stop = {
+		.raw = mchbar_read64(REUT_ch_SEQ_ADDR_WRAP(channel)),
+	};
+	reut_seq_addr_stop.rank_addr = rank_count - 1;
+	mchbar_write64(REUT_ch_SEQ_ADDR_WRAP(channel), reut_seq_addr_stop.raw);
+
+	reut_seq_cfg.global_control = 1;
+	mchbar_write64(REUT_ch_SEQ_CFG(channel), reut_seq_cfg.raw);
+	return BIT(channel);
+}
+
+void run_mpr_io_test(const bool clear_errors)
+{
+	io_reset();
+	mchbar_write32(REUT_GLOBAL_CTL, (union reut_seq_ctl_reg) {
+		.start_test   = 1,
+		.clear_errors = clear_errors,
+	}.raw);
+	tick_delay(2);
+	io_reset();
+	tick_delay(2);
+	mchbar_write32(REUT_GLOBAL_CTL, (union reut_seq_ctl_reg) {
+		.stop_test = 1,
+	}.raw);
+}
+
+static uint8_t get_num_tests(const uint8_t dq_pat)
+{
+	switch (dq_pat) {
+	case SEGMENT_WDB:	return 4;
+	case CADB:		return 7;
+	case TURN_AROUND_WR:	return 8;
+	case TURN_AROUND_ODT:	return 4;
+	case RD_RD_TA:		return 2;
+	case RD_RD_TA_ALL:	return 8;
+	default:		return 1;
+	}
+}
+
+uint8_t run_io_test(
+	struct sysinfo *const ctrl,
+	const uint8_t chanmask,
+	const uint8_t dq_pat,
+	const bool clear_errors)
+{
+	/* SEGMENT_WDB only runs 4 tests */
+	const uint8_t segment_wdb_lc[4] = { 0, 0, 4, 2 };
+	const union reut_pat_wdb_cl_ctrl_reg pat_wdb_cl[4] = {
+		[0] = {
+			.start_ptr =  0,
+			.end_ptr   =  9,
+			.inc_rate  = 25,
+			.inc_scale = SCALE_LINEAR,
+		},
+		[1] = {
+			.start_ptr =  0,
+			.end_ptr   =  9,
+			.inc_rate  = 25,
+			.inc_scale = SCALE_LINEAR,
+		},
+		[2] = {
+			.start_ptr = 10,
+			.end_ptr   = 63,
+			.inc_rate  = 19,
+			.inc_scale = SCALE_LINEAR,
+		},
+		[3] = {
+			.start_ptr = 10,
+			.end_ptr   = 63,
+			.inc_rate  = 10,
+			.inc_scale = SCALE_LINEAR,
+		},
+	};
+	const bool is_turnaround = dq_pat == RD_RD_TA || dq_pat == RD_RD_TA_ALL;
+	const uint8_t num_tests = get_num_tests(dq_pat);
+	union tc_bank_rank_a_reg tc_bank_rank_a[NUM_CHANNELS] = { 0 };
+	if (is_turnaround) {
+		for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
+			if (!(chanmask & BIT(channel)))
+				continue;
+
+			tc_bank_rank_a[channel].raw = ctrl->tc_bankrank_a[channel].raw;
+		}
+	}
+	for (uint8_t t = 0; t < num_tests; t++) {
+		for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
+			if (!(chanmask & BIT(channel)))
+				continue;
+
+			if (dq_pat == SEGMENT_WDB) {
+				mchbar_write32(REUT_ch_WDB_CL_CTRL(channel), pat_wdb_cl[t].raw);
+				/*
+				 * Skip programming LFSR save/restore. Too complex
+				 * unless power of 2. Program desired loopcount.
+				 */
+				const uint8_t pat_lc = ctrl->dq_pat_lc + segment_wdb_lc[t];
+				program_loop_count(ctrl, channel, pat_lc);
+			} else if (dq_pat == CADB) {
+				setup_cadb(ctrl, channel, num_tests, t);
+			} else if (dq_pat == TURN_AROUND_WR || dq_pat == TURN_AROUND_ODT) {
+				union reut_seq_cfg_reg reut_seq_cfg = {
+					.raw = mchbar_read64(REUT_ch_SEQ_CFG(channel)),
+				};
+				reut_seq_cfg.subsequence_start_pointer = t;
+				reut_seq_cfg.subsequence_end_pointer   = t;
+				mchbar_write64(REUT_ch_SEQ_CFG(channel), reut_seq_cfg.raw);
+				union reut_seq_addr_inc_ctl_reg addr_inc_ctl = {
+					.raw = mchbar_read64(REUT_ch_SEQ_ADDR_INC_CTL(channel)),
+				};
+				uint8_t ta_inc_rate = 1;
+				if (dq_pat == TURN_AROUND_WR && (t == 0 || t == 7))
+					ta_inc_rate = 0;
+				else if (dq_pat == TURN_AROUND_ODT && (t == 0 || t == 2))
+					ta_inc_rate = 0;
+
+				/* Program increment rate as linear value */
+				addr_inc_ctl.rank_addr_update = BIT(7) | ta_inc_rate;
+				addr_inc_ctl.col_addr_update  = BIT(7) | ta_inc_rate;
+				mchbar_write64(REUT_ch_SEQ_ADDR_INC_CTL(channel),
+						addr_inc_ctl.raw);
+			} else if (dq_pat == RD_RD_TA) {
+				tc_bank_rank_a[channel].tRDRD_sr = (t == 0) ? 4 : 5;
+				mchbar_write32(TC_BANK_RANK_A_ch(channel),
+						tc_bank_rank_a[channel].raw);
+			} else if (dq_pat == RD_RD_TA_ALL) {
+				/*
+				 * Program tRDRD for SR and DR. Run 8 tests, covering
+				 * tRDRD_sr = 4, 5, 6, 7 and tRDRD_dr = min, +1, +2, +3
+				 */
+				const uint32_t tRDRD_dr = ctrl->tc_bankrank_a[channel].tRDRD_dr;
+				tc_bank_rank_a[channel].tRDRD_sr = (t % 4) + 4;
+				tc_bank_rank_a[channel].tRDRD_dr = (t % 4) + tRDRD_dr;
+				mchbar_write32(TC_BANK_RANK_A_ch(channel),
+						tc_bank_rank_a[channel].raw);
+
+				/* Program linear rank increment rate */
+				union reut_seq_addr_inc_ctl_reg addr_inc_ctl = {
+					.raw = mchbar_read64(REUT_ch_SEQ_ADDR_INC_CTL(channel)),
+				};
+				addr_inc_ctl.rank_addr_update = BIT(7) | (t / 4) ? 0 : 31;
+				mchbar_write64(REUT_ch_SEQ_ADDR_INC_CTL(channel),
+						addr_inc_ctl.raw);
+			}
+		}
+		bool test_soe = false;
+		for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
+			if (!(chanmask & BIT(channel)))
+				continue;
+
+			const union reut_err_ctl_reg reut_err_ctl = {
+				.raw = mchbar_read32(REUT_ch_ERR_CONTROL(channel)),
+			};
+			const uint8_t soe = reut_err_ctl.stop_on_error_control;
+			if (soe != NSOE) {
+				test_soe = true;
+				break;
+			}
+		}
+		io_reset();
+		mchbar_write32(REUT_GLOBAL_CTL, (union reut_seq_ctl_reg) {
+			.start_test   = 1,
+			.clear_errors = clear_errors && t == 0,
+		}.raw);
+		struct mono_time prev, curr;
+		timer_monotonic_get(&prev);
+		union reut_global_err_reg global_err;
+		do {
+			global_err.raw = mchbar_read32(REUT_GLOBAL_ERR);
+			/** TODO: Clean up this mess **/
+			timer_monotonic_get(&curr);
+			if (mono_time_diff_microseconds(&prev, &curr) > 1000 * 1000) {
+				mchbar_write32(REUT_GLOBAL_CTL, (union reut_seq_ctl_reg) {
+					.stop_test = 1,
+				}.raw);
+				printk(BIOS_ERR, "REUT timed out, ch_done: %x\n",
+					global_err.ch_test_done);
+				break;
+			}
+		} while ((global_err.ch_test_done & chanmask) != chanmask);
+		if (test_soe && global_err.ch_error & chanmask)
+			break;
+	}
+	if (is_turnaround) {
+		for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
+			if (!(chanmask & BIT(channel)))
+				continue;
+
+			mchbar_write32(TC_BANK_RANK_A_ch(channel),
+				ctrl->tc_bankrank_a[channel].raw);
+		}
+	}
+	return ((union reut_global_err_reg)mchbar_read32(REUT_GLOBAL_ERR)).ch_error;
+}
diff --git a/src/northbridge/intel/haswell/registers/mchbar.h b/src/northbridge/intel/haswell/registers/mchbar.h
index f8408e51a0..817a9f8bf8 100644
--- a/src/northbridge/intel/haswell/registers/mchbar.h
+++ b/src/northbridge/intel/haswell/registers/mchbar.h
@@ -94,20 +94,35 @@
 #define TC_BANK_RANK_D_ch(ch)			_MCMAIN_C(0x4014, ch)
 #define SC_ROUNDT_LAT_ch(ch)			_MCMAIN_C(0x4024, ch)
 
+#define REUT_ch_PAT_WDB_CL_MUX_CFG(ch)		_MCMAIN_C(0x4040, ch)
+
 #define REUT_ch_PAT_WDB_CL_MUX_WR_x(ch, x)	_MCMAIN_C_X(0x4048, ch, x) /* x in 0 .. 2 */
 #define REUT_ch_PAT_WDB_CL_MUX_RD_x(ch, x)	_MCMAIN_C_X(0x4054, ch, x) /* x in 0 .. 2 */
 
 #define REUT_ch_PAT_WDB_CL_MUX_LMN(ch)		_MCMAIN_C(0x4078, ch)
 
+#define REUT_ch_PAT_WDB_INV(ch)			_MCMAIN_C(0x4084, ch)
+
+#define REUT_ch_ERR_CONTROL(ch)			_MCMAIN_C(0x4098, ch)
+#define REUT_ch_ERR_ECC_MASK(ch)		_MCMAIN_C(0x409c, ch)
+
 #define SC_WR_ADD_DELAY_ch(ch)			_MCMAIN_C(0x40d0, ch)
 
+#define REUT_ch_ERR_DATA_MASK(ch)		_MCMAIN_C(0x40d8, ch)
+
 #define REUT_ch_MISC_CKE_CTRL(ch)		_MCMAIN_C(0x4190, ch)
 
+#define REUT_ch_MISC_PAT_CADB_CTRL(ch)		_MCMAIN_C(0x4198, ch)
 #define REUT_ch_PAT_CADB_MRS(ch)		_MCMAIN_C(0x419c, ch)
+#define REUT_ch_PAT_CADB_MUX_CTRL(ch)		_MCMAIN_C(0x41a0, ch)
+#define REUT_ch_PAT_CADB_MUX_x(ch, x)		_MCMAIN_C_X(0x41a4, ch, x) /* x in 0 .. 2 */
 
+#define REUT_ch_PAT_CADB_CL_MUX_LMN(ch)		_MCMAIN_C(0x41b0, ch)
 #define REUT_ch_PAT_CADB_WRITE_PTR(ch)		_MCMAIN_C(0x41bc, ch)
 #define REUT_ch_PAT_CADB_PROG(ch)		_MCMAIN_C(0x41c0, ch)
 
+#define REUT_ch_WDB_CL_CTRL(ch)			_MCMAIN_C(0x4200, ch)
+
 #define TC_ZQCAL_ch(ch)				_MCMAIN_C(0x4290, ch)
 #define TC_RFP_ch(ch)				_MCMAIN_C(0x4294, ch)
 #define TC_RFTP_ch(ch)				_MCMAIN_C(0x4298, ch)
@@ -119,12 +134,27 @@
 #define QCLK_ch_LDAT_SDAT(ch)			_MCMAIN_C(0x42d4, ch)
 #define QCLK_ch_LDAT_DATA_IN_x(ch, x)		_MCMAIN_C_X(0x42dc, ch, x) /* x in 0 .. 1 */
 
+#define REUT_GLOBAL_CTL				0x4800
 #define REUT_GLOBAL_ERR				0x4804
 
+#define REUT_ch_SUBSEQ_x_CTL(ch, x)		(0x4808 + 40 * (ch) + 4 * (x))
+
 #define REUT_ch_SEQ_CFG(ch)			(0x48a8 + 8 * (ch))
 
 #define REUT_ch_SEQ_CTL(ch)			(0x48b8 + 4 * (ch))
 
+#define REUT_ch_SEQ_ADDR_START(ch)		(0x48d8 + 8 * (ch))
+
+#define REUT_ch_SEQ_ADDR_WRAP(ch)		(0x48e8 + 8 * (ch))
+
+#define REUT_ch_SEQ_MISC_CTL(ch)		(0x4908 + 4 * (ch))
+
+#define REUT_ch_SEQ_ADDR_INC_CTL(ch)		(0x4910 + 8 * (ch))
+
+#define REUT_ch_RANK_LOG_TO_PHYS(ch)		(0x4930 + 4 * (ch)) /* 4 bits per rank */
+
+#define HSW_REUT_ch_SEQ_LOOP_COUNT(ch)		(0x4980 + 4 * (ch)) /* *** only on C0 *** */
+
 /* MCMAIN broadcast */
 #define MCSCHEDS_CBIT		0x4c20
 

From b1ec1bee7e469eaad764419a781982c0a4e4a68f Mon Sep 17 00:00:00 2001
From: Angel Pons <th3fanbus@gmail.com>
Date: Sun, 8 May 2022 00:56:00 +0200
Subject: [PATCH 0308/3886] haswell NRI: Add range tracking library

Implement a small library used to keep track of passing ranges. This
will be used by 1D training algorithms when margining some parameter.

Change-Id: I8718e85165160afd7c0c8e730b5ce6c9c00f8a60
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64192
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 .../intel/haswell/native_raminit/Makefile.mk  |   1 +
 .../intel/haswell/native_raminit/ranges.c     | 109 ++++++++++++++++++
 .../intel/haswell/native_raminit/ranges.h     |  68 +++++++++++
 3 files changed, 178 insertions(+)
 create mode 100644 src/northbridge/intel/haswell/native_raminit/ranges.c
 create mode 100644 src/northbridge/intel/haswell/native_raminit/ranges.h

diff --git a/src/northbridge/intel/haswell/native_raminit/Makefile.mk b/src/northbridge/intel/haswell/native_raminit/Makefile.mk
index 6e1b365602..2da950771d 100644
--- a/src/northbridge/intel/haswell/native_raminit/Makefile.mk
+++ b/src/northbridge/intel/haswell/native_raminit/Makefile.mk
@@ -9,6 +9,7 @@ romstage-y += io_comp_control.c
 romstage-y += memory_map.c
 romstage-y += raminit_main.c
 romstage-y += raminit_native.c
+romstage-y += ranges.c
 romstage-y += reut.c
 romstage-y += setup_wdb.c
 romstage-y += spd_bitmunching.c
diff --git a/src/northbridge/intel/haswell/native_raminit/ranges.c b/src/northbridge/intel/haswell/native_raminit/ranges.c
new file mode 100644
index 0000000000..cdebc1fa66
--- /dev/null
+++ b/src/northbridge/intel/haswell/native_raminit/ranges.c
@@ -0,0 +1,109 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <types.h>
+
+#include "ranges.h"
+
+void linear_record_pass(
+	struct linear_train_data *const data,
+	const bool pass,
+	const int32_t value,
+	const int32_t start,
+	const int32_t step)
+{
+	/* If this is the first time, initialize all values */
+	if (value == start) {
+		/*
+		 * If value passed, create a zero-length region for the current value,
+		 * which may be extended as long as the successive values are passing.
+		 *
+		 * Otherwise, create a zero-length range for the preceding value. This
+		 * range cannot be extended by other passing values, which is desired.
+		 */
+		data->current.start = start - (pass ? 0 : step);
+		data->current.end   = data->current.start;
+		data->largest       = data->current;
+	} else if (pass) {
+		/* If this pass is not contiguous, it belongs to a new region */
+		if (data->current.end != (value - step))
+			data->current.start = value;
+
+		/* Update end of current region */
+		data->current.end = value;
+
+		/* Update largest region */
+		if (range_width(data->current) > range_width(data->largest))
+			data->largest = data->current;
+	}
+}
+
+void phase_record_pass(
+	struct phase_train_data *const data,
+	const bool pass,
+	const int32_t value,
+	const int32_t start,
+	const int32_t step)
+{
+	/* If this is the first time, initialize all values */
+	if (value == start) {
+		/*
+		 * If value passed, create a zero-length region for the current value,
+		 * which may be extended as long as the successive values are passing.
+		 *
+		 * Otherwise, create a zero-length range for the preceding value. This
+		 * range cannot be extended by other passing values, which is desired.
+		 */
+		data->current.start = start - (pass ? 0 : step);
+		data->current.end   = data->current.start;
+		data->largest       = data->current;
+		data->initial       = data->current;
+		return;
+	}
+	if (!pass)
+		return;
+
+	/* Update initial region */
+	if (data->initial.end == (value - step))
+		data->initial.end = value;
+
+	/* If this pass is not contiguous, it belongs to a new region */
+	if (data->current.end != (value - step))
+		data->current.start = value;
+
+	/* Update end of current region */
+	data->current.end = value;
+
+	/* Update largest region */
+	if (range_width(data->current) > range_width(data->largest))
+		data->largest = data->current;
+}
+
+void phase_append_initial_to_current(
+	struct phase_train_data *const data,
+	const int32_t start,
+	const int32_t step)
+{
+	/* If initial region is valid and does not overlap, append it */
+	if (data->initial.start == start && data->initial.end != data->current.end)
+		data->current.end += step + range_width(data->initial);
+
+	/* Update largest region */
+	if (range_width(data->current) > range_width(data->largest))
+		data->largest = data->current;
+}
+
+void phase_append_current_to_initial(
+	struct phase_train_data *const data,
+	const int32_t start,
+	const int32_t step)
+{
+	/* If initial region is valid and does not overlap, append it */
+	if (data->initial.start == start && data->initial.end != data->current.end) {
+		data->initial.start -= (step + range_width(data->current));
+		data->current = data->initial;
+	}
+
+	/* Update largest region */
+	if (range_width(data->current) > range_width(data->largest))
+		data->largest = data->current;
+}
diff --git a/src/northbridge/intel/haswell/native_raminit/ranges.h b/src/northbridge/intel/haswell/native_raminit/ranges.h
new file mode 100644
index 0000000000..235392df96
--- /dev/null
+++ b/src/northbridge/intel/haswell/native_raminit/ranges.h
@@ -0,0 +1,68 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#ifndef HASWELL_RAMINIT_RANGES_H
+#define HASWELL_RAMINIT_RANGES_H
+
+#include <types.h>
+
+/*
+ * Many algorithms shmoo some parameter to determine the largest passing
+ * range. Provide a common implementation to avoid redundant boilerplate.
+ */
+struct passing_range {
+	int32_t start;
+	int32_t end;
+};
+
+/* Structure for linear parameters, such as roundtrip delays */
+struct linear_train_data {
+	struct passing_range current;
+	struct passing_range largest;
+};
+
+/*
+ * Phase ranges are "circular": the first and last indices are contiguous.
+ * To correctly determine the largest passing range, one has to combine
+ * the initial range and the current range when processing the last index.
+ */
+struct phase_train_data {
+	struct passing_range initial;
+	struct passing_range current;
+	struct passing_range largest;
+};
+
+static inline int32_t range_width(const struct passing_range range)
+{
+	return range.end - range.start;
+}
+
+static inline int32_t range_center(const struct passing_range range)
+{
+	return range.start + range_width(range) / 2;
+}
+
+void linear_record_pass(
+	struct linear_train_data *data,
+	bool pass,
+	int32_t value,
+	int32_t start,
+	int32_t step);
+
+void phase_record_pass(
+	struct phase_train_data *data,
+	bool pass,
+	int32_t value,
+	int32_t start,
+	int32_t step);
+
+void phase_append_initial_to_current(
+	struct phase_train_data *data,
+	int32_t start,
+	int32_t step);
+
+void phase_append_current_to_initial(
+	struct phase_train_data *data,
+	int32_t start,
+	int32_t step);
+
+#endif

From fc72b9f3d93781c5ccb958e870e49773be92b759 Mon Sep 17 00:00:00 2001
From: Angel Pons <th3fanbus@gmail.com>
Date: Sun, 8 May 2022 01:11:03 +0200
Subject: [PATCH 0309/3886] haswell NRI: Add library to change margins

Implement a library to change Rx/Tx margins. It will be expanded later.

Change-Id: I0b55aba428d8b4d4e16d2fbdec57235ce3ce8adf
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64193
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 .../intel/haswell/native_raminit/Makefile.mk  |   1 +
 .../haswell/native_raminit/change_margin.c    | 154 ++++++++++++++++++
 .../haswell/native_raminit/raminit_native.h   |  50 ++++++
 .../intel/haswell/registers/mchbar.h          |   9 +
 4 files changed, 214 insertions(+)
 create mode 100644 src/northbridge/intel/haswell/native_raminit/change_margin.c

diff --git a/src/northbridge/intel/haswell/native_raminit/Makefile.mk b/src/northbridge/intel/haswell/native_raminit/Makefile.mk
index 2da950771d..ebe9e9b762 100644
--- a/src/northbridge/intel/haswell/native_raminit/Makefile.mk
+++ b/src/northbridge/intel/haswell/native_raminit/Makefile.mk
@@ -1,5 +1,6 @@
 ## SPDX-License-Identifier: GPL-2.0-or-later
 
+romstage-y += change_margin.c
 romstage-y += configure_mc.c
 romstage-y += ddr3.c
 romstage-y += jedec_reset.c
diff --git a/src/northbridge/intel/haswell/native_raminit/change_margin.c b/src/northbridge/intel/haswell/native_raminit/change_margin.c
new file mode 100644
index 0000000000..055c666eee
--- /dev/null
+++ b/src/northbridge/intel/haswell/native_raminit/change_margin.c
@@ -0,0 +1,154 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <commonlib/bsd/clamp.h>
+#include <console/console.h>
+#include <delay.h>
+#include <northbridge/intel/haswell/haswell.h>
+#include <timer.h>
+
+#include "raminit_native.h"
+
+void update_rxt(
+	struct sysinfo *ctrl,
+	const uint8_t channel,
+	const uint8_t rank,
+	const uint8_t byte,
+	const enum rxt_subfield subfield,
+	const int32_t value)
+{
+	union ddr_data_rx_train_rank_reg rxt = {
+		.rcven =  ctrl->rcven[channel][rank][byte],
+		.dqs_p = ctrl->rxdqsp[channel][rank][byte],
+		.rx_eq =  ctrl->rx_eq[channel][rank][byte],
+		.dqs_n = ctrl->rxdqsn[channel][rank][byte],
+		.vref  = ctrl->rxvref[channel][rank][byte],
+	};
+	int32_t new_value;
+	switch (subfield) {
+	case RXT_RCVEN:
+		new_value = clamp_s32(0, value, 511);
+		rxt.rcven = new_value;
+		break;
+	case RXT_RXDQS_P:
+		new_value = clamp_s32(0, value, 63);
+		rxt.dqs_p = new_value;
+		break;
+	case RXT_RX_EQ:
+		new_value = clamp_s32(0, value, 31);
+		rxt.rx_eq = new_value;
+		break;
+	case RXT_RXDQS_N:
+		new_value = clamp_s32(0, value, 63);
+		rxt.dqs_n = new_value;
+		break;
+	case RXT_RX_VREF:
+		new_value = clamp_s32(-32, value, 31);
+		rxt.vref = new_value;
+		break;
+	case RXT_RXDQS_BOTH:
+		new_value = clamp_s32(0, value, 63);
+		rxt.dqs_p = new_value;
+		rxt.dqs_n = new_value;
+		break;
+	case RXT_RESTORE:
+		new_value = value;
+		break;
+	default:
+		die("%s: Unhandled subfield index %u\n", __func__, subfield);
+	}
+
+	if (new_value != value) {
+		printk(BIOS_ERR, "%s: Overflow for subfield %u: %d ---> %d\n",
+			__func__, subfield, value, new_value);
+	}
+	mchbar_write32(RX_TRAIN_ch_r_b(channel, rank, byte), rxt.raw);
+	download_regfile(ctrl, channel, false, rank, REG_FILE_USE_RANK, byte, true, false);
+}
+
+void update_txt(
+	struct sysinfo *ctrl,
+	const uint8_t channel,
+	const uint8_t rank,
+	const uint8_t byte,
+	const enum txt_subfield subfield,
+	const int32_t value)
+{
+	union ddr_data_tx_train_rank_reg txt = {
+		.dq_delay  = ctrl->tx_dq[channel][rank][byte],
+		.dqs_delay = ctrl->txdqs[channel][rank][byte],
+		.tx_eq     = ctrl->tx_eq[channel][rank][byte],
+	};
+	int32_t new_value;
+	switch (subfield) {
+	case TXT_TX_DQ:
+		new_value = clamp_s32(0, value, 511);
+		txt.dq_delay = new_value;
+		break;
+	case TXT_TXDQS:
+		new_value = clamp_s32(0, value, 511);
+		txt.dqs_delay = new_value;
+		break;
+	case TXT_TX_EQ:
+		new_value = clamp_s32(0, value, 63);
+		txt.tx_eq = new_value;
+		break;
+	case TXT_DQDQS_OFF:
+		new_value = value;
+		txt.dqs_delay += new_value;
+		txt.dq_delay  += new_value;
+		break;
+	case TXT_RESTORE:
+		new_value = value;
+		break;
+	default:
+		die("%s: Unhandled subfield index %u\n", __func__, subfield);
+	}
+	if (new_value != value) {
+		printk(BIOS_ERR, "%s: Overflow for subfield %u: %d ---> %d\n",
+			__func__, subfield, value, new_value);
+	}
+	mchbar_write32(TX_TRAIN_ch_r_b(channel, rank, byte), txt.raw);
+	download_regfile(ctrl, channel, false, rank, REG_FILE_USE_RANK, byte, false, true);
+}
+
+void download_regfile(
+	struct sysinfo *ctrl,
+	const uint8_t channel,
+	const bool multicast,
+	const uint8_t rank,
+	const enum regfile_mode regfile,
+	const uint8_t byte,
+	const bool read_rf_rd,
+	const bool read_rf_wr)
+{
+	union reut_seq_base_addr_reg reut_seq_base_addr;
+	switch (regfile) {
+	case REG_FILE_USE_START:
+		reut_seq_base_addr.raw = mchbar_read64(REUT_ch_SEQ_ADDR_START(channel));
+		break;
+	case REG_FILE_USE_CURRENT:
+		reut_seq_base_addr.raw = mchbar_read64(REUT_ch_SEQ_ADDR_CURRENT(channel));
+		break;
+	case REG_FILE_USE_RANK:
+		reut_seq_base_addr.raw = 0;
+		if (rank >= NUM_SLOTRANKS)
+			die("%s: bad rank %u\n", __func__, rank);
+		break;
+	default:
+		die("%s: Invalid regfile param %u\n", __func__, regfile);
+	}
+	uint8_t phys_rank = rank;
+	if (reut_seq_base_addr.raw != 0) {
+		/* Map REUT logical rank to physical rank */
+		const uint32_t log_to_phys = mchbar_read32(REUT_ch_RANK_LOG_TO_PHYS(channel));
+		phys_rank = log_to_phys >> (reut_seq_base_addr.rank_addr * 4) & 0x3;
+	}
+	uint32_t reg = multicast ? DDR_DATA_ch_CONTROL_0(channel) : DQ_CONTROL_0(channel, byte);
+	union ddr_data_control_0_reg ddr_data_control_0 = {
+		.raw = mchbar_read32(reg),
+	};
+	ddr_data_control_0.read_rf_rd   = read_rf_rd;
+	ddr_data_control_0.read_rf_wr   = read_rf_wr;
+	ddr_data_control_0.read_rf_rank = phys_rank;
+	mchbar_write32(reg, ddr_data_control_0.raw);
+}
diff --git a/src/northbridge/intel/haswell/native_raminit/raminit_native.h b/src/northbridge/intel/haswell/native_raminit/raminit_native.h
index f029e7f076..8707257b27 100644
--- a/src/northbridge/intel/haswell/native_raminit/raminit_native.h
+++ b/src/northbridge/intel/haswell/native_raminit/raminit_native.h
@@ -118,6 +118,30 @@ enum test_stop {
 	ALSOE  = 3,	/* Stop on all lanes error */
 };
 
+enum rxt_subfield {
+	RXT_RCVEN	= 0,
+	RXT_RXDQS_P	= 1,
+	RXT_RX_EQ	= 2,
+	RXT_RXDQS_N	= 3,
+	RXT_RX_VREF	= 4,
+	RXT_RXDQS_BOTH	= 5,
+	RXT_RESTORE	= 255,
+};
+
+enum txt_subfield {
+	TXT_TX_DQ	= 0,
+	TXT_TXDQS	= 1,
+	TXT_TX_EQ	= 2,
+	TXT_DQDQS_OFF	= 3,
+	TXT_RESTORE	= 255,
+};
+
+enum regfile_mode {
+	REG_FILE_USE_RANK,	/* Used when changing parameters for each rank */
+	REG_FILE_USE_START,	/* Used when changing parameters before the test */
+	REG_FILE_USE_CURRENT,	/* Used when changing parameters after the test */
+};
+
 struct wdb_pat {
 	uint32_t start_ptr;	/* Starting pointer in WDB */
 	uint32_t stop_ptr;	/* Stopping pointer in WDB */
@@ -451,6 +475,32 @@ uint8_t select_reut_ranks(struct sysinfo *ctrl, uint8_t channel, uint8_t rankmas
 void run_mpr_io_test(bool clear_errors);
 uint8_t run_io_test(struct sysinfo *ctrl, uint8_t chanmask, uint8_t dq_pat, bool clear_errors);
 
+void update_rxt(
+	struct sysinfo *ctrl,
+	uint8_t channel,
+	uint8_t rank,
+	uint8_t byte,
+	enum rxt_subfield subfield,
+	int32_t value);
+
+void update_txt(
+	struct sysinfo *ctrl,
+	uint8_t channel,
+	uint8_t rank,
+	uint8_t byte,
+	enum txt_subfield subfield,
+	int32_t value);
+
+void download_regfile(
+	struct sysinfo *ctrl,
+	uint8_t channel,
+	bool multicast,
+	uint8_t rank,
+	enum regfile_mode regfile,
+	uint8_t byte,
+	bool read_rf_rd,
+	bool read_rf_wr);
+
 uint8_t get_rx_bias(const struct sysinfo *ctrl);
 
 uint8_t get_tCWL(uint32_t mem_clock_mhz);
diff --git a/src/northbridge/intel/haswell/registers/mchbar.h b/src/northbridge/intel/haswell/registers/mchbar.h
index 817a9f8bf8..a81559bb1e 100644
--- a/src/northbridge/intel/haswell/registers/mchbar.h
+++ b/src/northbridge/intel/haswell/registers/mchbar.h
@@ -15,7 +15,11 @@
 /* Register definitions */
 
 /* DDR DATA per-channel per-bytelane */
+#define RX_TRAIN_ch_r_b(ch, rank, byte)		_DDRIO_C_R_B(0x0000, ch, rank, byte)
+#define TX_TRAIN_ch_r_b(ch, rank, byte)		_DDRIO_C_R_B(0x0020, ch, rank, byte)
+
 #define DQ_CONTROL_2(ch, byte)			_DDRIO_C_R_B(0x0064, ch, 0, byte)
+#define DQ_CONTROL_0(ch, byte)			_DDRIO_C_R_B(0x0074, ch, 0, byte)
 
 /* DDR CKE per-channel */
 #define DDR_CKE_ch_CMD_COMP_OFFSET(ch)		_DDRIO_C_R_B(0x1204, ch, 0, 0)
@@ -38,6 +42,9 @@
 #define DDR_SCRAMBLE_ch(ch)			(0x2000 + 4 * (ch))
 #define DDR_SCRAM_MISC_CONTROL			0x2008
 
+/* DDR DATA per-channel multicast */
+#define DDR_DATA_ch_CONTROL_0(ch)		_DDRIO_C_R_B(0x3074, ch, 0, 0)
+
 /* DDR CMDN/CMDS per-channel (writes go to both CMDN and CMDS fubs) */
 #define DDR_CMD_ch_COMP_OFFSET(ch)		_DDRIO_C_R_B(0x3204, ch, 0, 0)
 #define DDR_CMD_ch_PI_CODING(ch)		_DDRIO_C_R_B(0x3208, ch, 0, 0)
@@ -147,6 +154,8 @@
 
 #define REUT_ch_SEQ_ADDR_WRAP(ch)		(0x48e8 + 8 * (ch))
 
+#define REUT_ch_SEQ_ADDR_CURRENT(ch)		(0x48f8 + 8 * (ch))
+
 #define REUT_ch_SEQ_MISC_CTL(ch)		(0x4908 + 4 * (ch))
 
 #define REUT_ch_SEQ_ADDR_INC_CTL(ch)		(0x4910 + 8 * (ch))

From d434ec3453b8aca6ac77641d94c164f48a93c99b Mon Sep 17 00:00:00 2001
From: Angel Pons <th3fanbus@gmail.com>
Date: Sun, 8 May 2022 00:05:41 +0200
Subject: [PATCH 0310/3886] haswell NRI: Add RcvEn training

Implement the RcvEn (Receive Enable) calibration procedure.

Change-Id: Ifbfa520f3e0486c56d0988ce67af2ddb9cf29888
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64194
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
---
 .../intel/haswell/native_raminit/Makefile.mk  |   1 +
 .../haswell/native_raminit/raminit_main.c     |   1 +
 .../haswell/native_raminit/raminit_native.h   |  14 +
 .../haswell/native_raminit/reg_structs.h      |  13 +
 .../native_raminit/train_receive_enable.c     | 561 ++++++++++++++++++
 .../intel/haswell/registers/mchbar.h          |   3 +
 6 files changed, 593 insertions(+)
 create mode 100644 src/northbridge/intel/haswell/native_raminit/train_receive_enable.c

diff --git a/src/northbridge/intel/haswell/native_raminit/Makefile.mk b/src/northbridge/intel/haswell/native_raminit/Makefile.mk
index ebe9e9b762..e2fbfb4211 100644
--- a/src/northbridge/intel/haswell/native_raminit/Makefile.mk
+++ b/src/northbridge/intel/haswell/native_raminit/Makefile.mk
@@ -16,3 +16,4 @@ romstage-y += setup_wdb.c
 romstage-y += spd_bitmunching.c
 romstage-y += testing_io.c
 romstage-y += timings_refresh.c
+romstage-y += train_receive_enable.c
diff --git a/src/northbridge/intel/haswell/native_raminit/raminit_main.c b/src/northbridge/intel/haswell/native_raminit/raminit_main.c
index cbc64315cd..97eb957294 100644
--- a/src/northbridge/intel/haswell/native_raminit/raminit_main.c
+++ b/src/northbridge/intel/haswell/native_raminit/raminit_main.c
@@ -61,6 +61,7 @@ static const struct task_entry cold_boot[] = {
 	{ configure_memory_map,                                   true, "MEMMAP",     },
 	{ do_jedec_init,                                          true, "JEDECINIT",  },
 	{ pre_training,                                           true, "PRETRAIN",   },
+	{ train_receive_enable,                                   true, "RCVET",      },
 };
 
 /* Return a generic stepping value to make stepping checks simpler */
diff --git a/src/northbridge/intel/haswell/native_raminit/raminit_native.h b/src/northbridge/intel/haswell/native_raminit/raminit_native.h
index 8707257b27..eaaaedad1e 100644
--- a/src/northbridge/intel/haswell/native_raminit/raminit_native.h
+++ b/src/northbridge/intel/haswell/native_raminit/raminit_native.h
@@ -43,6 +43,9 @@
 #define NUM_WDB_CL_MUX_SEEDS	3
 #define NUM_CADB_MUX_SEEDS	3
 
+/* Specified in PI ticks. 64 PI ticks == 1 qclk */
+#define tDQSCK_DRIFT		64
+
 /* ZQ calibration types */
 enum {
 	ZQ_INIT,	/* DDR3: ZQCL with tZQinit, LPDDR3: ZQ Init  with tZQinit  */
@@ -189,6 +192,7 @@ enum raminit_status {
 	RAMINIT_STATUS_MPLL_INIT_FAILURE,
 	RAMINIT_STATUS_POLL_TIMEOUT,
 	RAMINIT_STATUS_REUT_ERROR,
+	RAMINIT_STATUS_RCVEN_FAILURE,
 	RAMINIT_STATUS_UNSPECIFIED_ERROR, /** TODO: Deprecated in favor of specific values **/
 };
 
@@ -271,6 +275,10 @@ struct sysinfo {
 
 	union ddr_data_vref_adjust_reg dimm_vref;
 
+	uint8_t io_latency[NUM_CHANNELS][NUM_SLOTRANKS];
+	uint8_t rt_latency[NUM_CHANNELS][NUM_SLOTRANKS];
+	uint32_t rt_io_comp[NUM_CHANNELS];
+
 	uint32_t data_offset_train[NUM_CHANNELS][NUM_LANES];
 	uint32_t data_offset_comp[NUM_CHANNELS][NUM_LANES];
 
@@ -345,6 +353,11 @@ static inline void clear_data_offset_train_all(struct sysinfo *ctrl)
 	memset(ctrl->data_offset_train, 0, sizeof(ctrl->data_offset_train));
 }
 
+static inline uint32_t get_data_train_feedback(const uint8_t channel, const uint8_t byte)
+{
+	return mchbar_read32(DDR_DATA_TRAIN_FEEDBACK(channel, byte));
+}
+
 /* Number of ticks to wait in units of 69.841279 ns (citation needed) */
 static inline void tick_delay(const uint32_t delay)
 {
@@ -400,6 +413,7 @@ enum raminit_status convert_timings(struct sysinfo *ctrl);
 enum raminit_status configure_mc(struct sysinfo *ctrl);
 enum raminit_status configure_memory_map(struct sysinfo *ctrl);
 enum raminit_status do_jedec_init(struct sysinfo *ctrl);
+enum raminit_status train_receive_enable(struct sysinfo *ctrl);
 
 void configure_timings(struct sysinfo *ctrl);
 void configure_refresh(struct sysinfo *ctrl);
diff --git a/src/northbridge/intel/haswell/native_raminit/reg_structs.h b/src/northbridge/intel/haswell/native_raminit/reg_structs.h
index b943259b91..b099f4bb82 100644
--- a/src/northbridge/intel/haswell/native_raminit/reg_structs.h
+++ b/src/northbridge/intel/haswell/native_raminit/reg_structs.h
@@ -297,6 +297,19 @@ union ddr_scram_misc_control_reg {
 	uint32_t raw;
 };
 
+union sc_io_latency_reg {
+	struct __packed {
+		uint32_t iolat_rank0     : 4; // Bits  3:0
+		uint32_t iolat_rank1     : 4; // Bits  7:4
+		uint32_t iolat_rank2     : 4; // Bits 11:8
+		uint32_t iolat_rank3     : 4; // Bits 15:12
+		uint32_t rt_iocomp       : 6; // Bits 21:16
+		uint32_t                 : 9; // Bits 30:22
+		uint32_t dis_rt_clk_gate : 1; // Bits 31:31
+	};
+	uint32_t raw;
+};
+
 union mcscheds_cbit_reg {
 	struct __packed {
 		uint32_t dis_opp_cas    : 1; // Bits  0:0
diff --git a/src/northbridge/intel/haswell/native_raminit/train_receive_enable.c b/src/northbridge/intel/haswell/native_raminit/train_receive_enable.c
new file mode 100644
index 0000000000..576c6bc21e
--- /dev/null
+++ b/src/northbridge/intel/haswell/native_raminit/train_receive_enable.c
@@ -0,0 +1,561 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <console/console.h>
+#include <northbridge/intel/haswell/haswell.h>
+#include <types.h>
+
+#include "raminit_native.h"
+#include "ranges.h"
+
+#define RCVEN_PLOT	RAM_DEBUG
+
+static enum raminit_status change_rcven_timing(struct sysinfo *ctrl, const uint8_t channel)
+{
+	int16_t max_rcven = -4096;
+	int16_t min_rcven = 4096;
+	int16_t max_rcven_rank[NUM_SLOTRANKS];
+	int16_t min_rcven_rank[NUM_SLOTRANKS];
+	for (uint8_t rank = 0; rank < NUM_SLOTRANKS; rank++) {
+		max_rcven_rank[rank] = max_rcven;
+		min_rcven_rank[rank] = min_rcven;
+	}
+	for (uint8_t rank = 0; rank < NUM_SLOTRANKS; rank++) {
+		if (!rank_in_ch(ctrl, rank, channel))
+			continue;
+
+		for (uint8_t byte = 0; byte < ctrl->lanes; byte++) {
+			int16_t new_rcven = ctrl->rcven[channel][rank][byte];
+			new_rcven -= ctrl->io_latency[channel][rank] * 64;
+			if (max_rcven_rank[rank] < new_rcven)
+				max_rcven_rank[rank] = new_rcven;
+
+			if (min_rcven_rank[rank] > new_rcven)
+				min_rcven_rank[rank] = new_rcven;
+		}
+		if (max_rcven < max_rcven_rank[rank])
+			max_rcven = max_rcven_rank[rank];
+
+		if (min_rcven > min_rcven_rank[rank])
+			min_rcven = min_rcven_rank[rank];
+	}
+
+	/*
+	 * Determine how far we are from the ideal center point for RcvEn timing.
+	 * (PiIdeal - AveRcvEn) / 64 is the ideal number of cycles we should have
+	 * for IO latency. command training will reduce this by 64, so plan for
+	 * that now in the ideal value. Round to closest integer.
+	 */
+	const int16_t rre_pi_ideal = 256 + 64;
+	const int16_t pi_reserve = 64;
+	const int16_t rcven_center = (max_rcven + min_rcven) / 2;
+	const int8_t iolat_target = DIV_ROUND_CLOSEST(rre_pi_ideal - rcven_center, 64);
+
+	int8_t io_g_offset = 0;
+	int8_t io_lat[NUM_SLOTRANKS] = { 0 };
+	for (uint8_t rank = 0; rank < NUM_SLOTRANKS; rank++) {
+		if (!rank_in_ch(ctrl, rank, channel))
+			continue;
+
+		io_lat[rank] = iolat_target;
+
+		/* Check for RcvEn underflow/overflow */
+		const int16_t rcven_lower = 64 * io_lat[rank] + min_rcven_rank[rank];
+		if (rcven_lower < pi_reserve)
+			io_lat[rank] += DIV_ROUND_UP(pi_reserve - rcven_lower, 64);
+
+		const int16_t rcven_upper = 64 * io_lat[rank] + max_rcven_rank[rank];
+		if (rcven_upper > 511 - pi_reserve)
+			io_lat[rank] -= DIV_ROUND_UP(rcven_upper - (511 - pi_reserve), 64);
+
+		/* Check for IO latency over/underflow */
+		if (io_lat[rank] - io_g_offset > 14)
+			io_g_offset = io_lat[rank] - 14;
+
+		if (io_lat[rank] - io_g_offset < 1)
+			io_g_offset = io_lat[rank] - 1;
+
+		const int8_t cycle_offset = io_lat[rank] - ctrl->io_latency[channel][rank];
+		for (uint8_t byte = 0; byte < ctrl->lanes; byte++) {
+			ctrl->rcven[channel][rank][byte] += 64 * cycle_offset;
+			update_rxt(ctrl, channel, rank, byte, RXT_RESTORE, 0);
+		}
+	}
+
+	/* Calculate new IO comp latency */
+	union sc_io_latency_reg sc_io_lat = {
+		.raw = mchbar_read32(SC_IO_LATENCY_ch(channel)),
+	};
+
+	/* Check if we are underflowing or overflowing this field */
+	if (io_g_offset < 0 && sc_io_lat.rt_iocomp < -io_g_offset) {
+		printk(BIOS_ERR, "%s: IO COMP underflow\n", __func__);
+		printk(BIOS_ERR, "io_g_offset: %d\n", io_g_offset);
+		printk(BIOS_ERR, "rt_iocomp: %u\n", sc_io_lat.rt_iocomp);
+		return RAMINIT_STATUS_RCVEN_FAILURE;
+	}
+	if (io_g_offset > 0 && io_g_offset > 0x3f - sc_io_lat.rt_iocomp) {
+		printk(BIOS_ERR, "%s: IO COMP overflow\n", __func__);
+		printk(BIOS_ERR, "io_g_offset: %d\n", io_g_offset);
+		printk(BIOS_ERR, "rt_iocomp: %u\n", sc_io_lat.rt_iocomp);
+		return RAMINIT_STATUS_RCVEN_FAILURE;
+	}
+	sc_io_lat.rt_iocomp += io_g_offset;
+	ctrl->rt_io_comp[channel] = sc_io_lat.rt_iocomp;
+	for (uint8_t rank = 0; rank < NUM_SLOTRANKS; rank++) {
+		if (ctrl->rankmap[channel] & BIT(rank))
+			ctrl->io_latency[channel][rank] = io_lat[rank] - io_g_offset;
+
+		const uint8_t shift = rank * 4;
+		sc_io_lat.raw &= ~(0xf << shift);
+		sc_io_lat.raw |= ctrl->io_latency[channel][rank] << shift;
+	}
+	mchbar_write32(SC_IO_LATENCY_ch(channel), sc_io_lat.raw);
+	return RAMINIT_STATUS_SUCCESS;
+}
+
+#define RL_START (256 + 24)
+#define RL_STOP  (384 + 24)
+#define RL_STEP  8
+
+#define RE_NUM_SAMPLES	6
+
+static enum raminit_status verify_high_region(const int32_t center, const int32_t lwidth)
+{
+	if (center > RL_STOP) {
+		/* Check if center of high was found where it should be */
+		printk(BIOS_ERR, "RcvEn: Center of high (%d) higher than expected\n", center);
+		return RAMINIT_STATUS_RCVEN_FAILURE;
+	}
+	if (lwidth <= 32) {
+		/* Check if width is large enough */
+		printk(BIOS_ERR, "RcvEn: Width of high region (%d) too small\n", lwidth);
+		return RAMINIT_STATUS_RCVEN_FAILURE;
+	}
+	if (lwidth >= 96) {
+		/* Since we're calibrating a phase, a too large region is a problem */
+		printk(BIOS_ERR, "RcvEn: Width of high region (%d) too large\n", lwidth);
+		return RAMINIT_STATUS_RCVEN_FAILURE;
+	}
+	return RAMINIT_STATUS_SUCCESS;
+}
+
+static void program_io_latency(struct sysinfo *ctrl, const uint8_t channel, const uint8_t rank)
+{
+	const uint8_t shift = rank * 4;
+	const uint8_t iolat = ctrl->io_latency[channel][rank];
+	mchbar_clrsetbits32(SC_IO_LATENCY_ch(channel), 0xf << shift, iolat << shift);
+}
+
+static void program_rl_delays(struct sysinfo *ctrl, const uint8_t rank, const uint16_t rl_delay)
+{
+	for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
+		if (!rank_in_ch(ctrl, rank, channel))
+			continue;
+
+		for (uint8_t byte = 0; byte < ctrl->lanes; byte++)
+			update_rxt(ctrl, channel, rank, byte, RXT_RCVEN, rl_delay);
+	}
+}
+
+static bool sample_dqs(const uint8_t channel, const uint8_t byte)
+{
+	return (get_data_train_feedback(channel, byte) & 0x1ff) >= BIT(RE_NUM_SAMPLES - 1);
+}
+
+enum raminit_status train_receive_enable(struct sysinfo *ctrl)
+{
+	const struct reut_box reut_addr = {
+		.col = {
+			.start    = 0,
+			.stop     = 1023,
+			.inc_rate = 0,
+			.inc_val  = 1,
+		},
+	};
+	const struct wdb_pat wdb_pattern = {
+		.start_ptr  = 0,
+		.stop_ptr   = 9,
+		.inc_rate   = 32,
+		.dq_pattern = BASIC_VA,
+	};
+
+	const uint16_t bytemask = BIT(ctrl->lanes) - 1;
+	const uint8_t fine_step = 1;
+
+	const uint8_t rt_delta = is_hsw_ult() ? 4 : 2;
+	const uint8_t rt_io_comp = 21 + rt_delta;
+	const uint8_t rt_latency = 16 + rt_delta;
+	setup_io_test(
+		ctrl,
+		ctrl->chanmap,
+		PAT_RD,
+		2,
+		RE_NUM_SAMPLES + 1,
+		&reut_addr,
+		0,
+		&wdb_pattern,
+		0,
+		8);
+
+	for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
+		if (!does_ch_exist(ctrl, channel))
+			continue;
+
+		for (uint8_t byte = 0; byte < ctrl->lanes; byte++) {
+			union ddr_data_control_2_reg data_control_2 = {
+				.raw = ctrl->dq_control_2[channel][byte],
+			};
+			data_control_2.force_rx_on = 1;
+			mchbar_write32(DQ_CONTROL_2(channel, byte), data_control_2.raw);
+		}
+		union ddr_data_control_0_reg data_control_0 = {
+			.raw = ctrl->dq_control_0[channel],
+		};
+		if (ctrl->lpddr) {
+			/**
+			 * W/A for b4618574 - @todo: remove for HSW ULT C0
+			 * Can't have force_odt_on together with leaker, disable LPDDR
+			 * mode during this training step. lpddr_mode is restored
+			 * at the end of this function from the host structure.
+			 */
+			data_control_0.lpddr_mode = 0;
+			mchbar_write32(DDR_DATA_ch_CONTROL_0(channel), data_control_0.raw);
+		}
+		data_control_0.force_odt_on     = 1;
+		data_control_0.rl_training_mode = 1;
+		mchbar_write32(DDR_DATA_ch_CONTROL_0(channel), data_control_0.raw);
+		mchbar_write32(SC_IO_LATENCY_ch(channel), (union sc_io_latency_reg) {
+			.rt_iocomp = rt_io_comp,
+		}.raw);
+	}
+	enum raminit_status status = RAMINIT_STATUS_SUCCESS;
+	for (uint8_t rank = 0; rank < NUM_SLOTRANKS; rank++) {
+		if (!does_rank_exist(ctrl, rank))
+			continue;
+
+		/*
+		 * Set initial roundtrip latency values. Assume -4 QCLK for worst board
+		 * layout. This is calculated as HW_ROUNDT_LAT_DEFAULT_VALUE plus:
+		 *
+		 *   DDR3: Default + (2 * tAA) + 4 QCLK + PI_CLK + N-mode value * 2
+		 * LPDDR3: Default + (2 * tAA) + 4 QCLK + PI_CLK + tDQSCK_max
+		 *
+		 * N-mode is 3 during training mode. Both channels use the same timings.
+		 */
+		/** TODO: differs for LPDDR **/
+		const uint32_t tmp = MAX(ctrl->multiplier, 4) + 5 + 2 * ctrl->tAA;
+		const uint32_t initial_rt_latency = MIN(rt_latency + tmp, 0x3f);
+
+		uint8_t chanmask = 0;
+		for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
+			chanmask |= select_reut_ranks(ctrl, channel, BIT(rank));
+			if (!rank_in_ch(ctrl, rank, channel))
+				continue;
+
+			ctrl->io_latency[channel][rank] = 0;
+			mchbar_write8(SC_ROUNDT_LAT_ch(channel) + rank, initial_rt_latency);
+			ctrl->rt_latency[channel][rank] = initial_rt_latency;
+		}
+
+		printk(BIOS_DEBUG, "Rank %u\n", rank);
+		printk(BIOS_DEBUG, "Steps 1 and 2: Find middle of high region\n");
+		printk(RCVEN_PLOT, "Byte");
+		for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
+			if (!rank_in_ch(ctrl, rank, channel))
+				continue;
+
+			printk(RCVEN_PLOT, "\t");
+			for (uint8_t byte = 0; byte < ctrl->lanes; byte++)
+				printk(RCVEN_PLOT, "%u ", byte);
+		}
+		printk(RCVEN_PLOT, "\nRcvEn\n");
+		struct phase_train_data region_data[NUM_CHANNELS][NUM_LANES] = { 0 };
+		for (uint16_t rl_delay = RL_START; rl_delay < RL_STOP; rl_delay += RL_STEP) {
+			printk(RCVEN_PLOT, " % 3d", rl_delay);
+			program_rl_delays(ctrl, rank, rl_delay);
+			run_io_test(ctrl, chanmask, BASIC_VA, true);
+			for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
+				if (!rank_in_ch(ctrl, rank, channel))
+					continue;
+
+				printk(RCVEN_PLOT, "\t");
+				for (uint8_t byte = 0; byte < ctrl->lanes; byte++) {
+					const bool high = sample_dqs(channel, byte);
+					printk(RCVEN_PLOT, high ? ". " : "# ");
+					phase_record_pass(
+						&region_data[channel][byte],
+						high,
+						rl_delay,
+						RL_START,
+						RL_STEP);
+				}
+			}
+			printk(RCVEN_PLOT, "\n");
+		}
+		printk(RCVEN_PLOT, "\n");
+		printk(BIOS_DEBUG, "Update RcvEn timing to be in the center of high region\n");
+		for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
+			if (!rank_in_ch(ctrl, rank, channel))
+				continue;
+
+			printk(BIOS_DEBUG, "C%u.R%u: \tLeft\tRight\tWidth\tCenter\n",
+				channel, rank);
+			for (uint8_t byte = 0; byte < ctrl->lanes; byte++) {
+				struct phase_train_data *const curr_data =
+						&region_data[channel][byte];
+				phase_append_current_to_initial(curr_data, RL_START, RL_STEP);
+				const int32_t lwidth = range_width(curr_data->largest);
+				const int32_t center = range_center(curr_data->largest);
+				printk(BIOS_DEBUG, "   B%u: \t%d\t%d\t%d\t%d\n",
+					byte,
+					curr_data->largest.start,
+					curr_data->largest.end,
+					lwidth,
+					center);
+
+				status = verify_high_region(center, lwidth);
+				if (status) {
+					printk(BIOS_ERR,
+						"RcvEn problems on channel %u, byte %u\n",
+						channel, byte);
+					goto clean_up;
+				}
+				ctrl->rcven[channel][rank][byte] = center;
+				update_rxt(ctrl, channel, rank, byte, RXT_RESTORE, 0);
+			}
+			printk(BIOS_DEBUG, "\n");
+		}
+
+		printk(BIOS_DEBUG, "Step 3: Quarter preamble - Walk backwards\n");
+		printk(RCVEN_PLOT, "Byte");
+		for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
+			if (!rank_in_ch(ctrl, rank, channel))
+				continue;
+
+			printk(RCVEN_PLOT, "\t");
+			for (uint8_t byte = 0; byte < ctrl->lanes; byte++)
+				printk(RCVEN_PLOT, "%u ", byte);
+		}
+		printk(RCVEN_PLOT, "\nIOLAT\n");
+		bool done = false;
+		while (!done) {
+			run_io_test(ctrl, chanmask, BASIC_VA, true);
+			done = true;
+			for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
+				if (!rank_in_ch(ctrl, rank, channel))
+					continue;
+
+				printk(RCVEN_PLOT, "  %2u\t", ctrl->io_latency[channel][rank]);
+				uint16_t highs = 0;
+				for (uint8_t byte = 0; byte < ctrl->lanes; byte++) {
+					const bool high = sample_dqs(channel, byte);
+					printk(RCVEN_PLOT, high ? "H " : "L ");
+					if (high)
+						highs |= BIT(byte);
+				}
+				if (!highs)
+					continue;
+
+				done = false;
+
+				/* If all bytes sample high, adjust timing globally */
+				if (highs == bytemask && ctrl->io_latency[channel][rank] < 14) {
+					ctrl->io_latency[channel][rank] += 2;
+					ctrl->io_latency[channel][rank] %= 16;
+					program_io_latency(ctrl, channel, rank);
+					continue;
+				}
+
+				/* Otherwise, adjust individual bytes */
+				for (uint8_t byte = 0; byte < ctrl->lanes; byte++) {
+					if (!(highs & BIT(byte)))
+						continue;
+
+					if (ctrl->rcven[channel][rank][byte] < 128) {
+						printk(BIOS_ERR,
+							"RcvEn underflow: walking backwards\n");
+						printk(BIOS_ERR,
+							"For channel %u, rank %u, byte %u\n",
+							channel, rank, byte);
+						status = RAMINIT_STATUS_RCVEN_FAILURE;
+						goto clean_up;
+					}
+					ctrl->rcven[channel][rank][byte] -= 128;
+					update_rxt(ctrl, channel, rank, byte, RXT_RESTORE, 0);
+				}
+			}
+			printk(RCVEN_PLOT, "\n");
+		}
+		for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
+			if (!rank_in_ch(ctrl, rank, channel))
+				continue;
+
+			printk(BIOS_DEBUG, "\nC%u:  Preamble\n", channel);
+			for (uint8_t byte = 0; byte < ctrl->lanes; byte++) {
+				printk(BIOS_DEBUG,
+					" B%u: %u\n", byte, ctrl->rcven[channel][rank][byte]);
+			}
+		}
+		printk(BIOS_DEBUG, "\n");
+
+		printk(BIOS_DEBUG, "Step 4: Add 1 qclk\n");
+		for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
+			if (!rank_in_ch(ctrl, rank, channel))
+				continue;
+
+			for (uint8_t byte = 0; byte < ctrl->lanes; byte++) {
+				ctrl->rcven[channel][rank][byte] += 64;
+				update_rxt(ctrl, channel, rank, byte, RXT_RESTORE, 0);
+			}
+		}
+		printk(BIOS_DEBUG, "\n");
+
+		printk(BIOS_DEBUG, "Step 5: Walk forward to find rising edge\n");
+		printk(RCVEN_PLOT, "Byte");
+		for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
+			if (!rank_in_ch(ctrl, rank, channel))
+				continue;
+
+			printk(RCVEN_PLOT, "\t");
+			for (uint8_t byte = 0; byte < ctrl->lanes; byte++)
+				printk(RCVEN_PLOT, "%u ", byte);
+		}
+		printk(RCVEN_PLOT, "\n inc\n");
+		uint16_t ch_result[NUM_CHANNELS] = { 0 };
+		uint8_t inc_preamble[NUM_CHANNELS][NUM_LANES] = { 0 };
+		for (uint8_t inc = 0; inc < 64; inc += fine_step) {
+			printk(RCVEN_PLOT, " %2u\t", inc);
+			run_io_test(ctrl, chanmask, BASIC_VA, true);
+			done = true;
+			for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
+				if (!rank_in_ch(ctrl, rank, channel))
+					continue;
+
+				for (uint8_t byte = 0; byte < ctrl->lanes; byte++) {
+					if (ch_result[channel] & BIT(byte)) {
+						/* Skip bytes that are already done */
+						printk(RCVEN_PLOT, ". ");
+						continue;
+					}
+					const bool pass = sample_dqs(channel, byte);
+					printk(RCVEN_PLOT, pass ? ". " : "# ");
+					if (pass) {
+						ch_result[channel] |= BIT(byte);
+						continue;
+					}
+					ctrl->rcven[channel][rank][byte] += fine_step;
+					update_rxt(ctrl, channel, rank, byte, RXT_RESTORE, 0);
+					inc_preamble[channel][byte] = inc;
+				}
+				printk(RCVEN_PLOT, "\t");
+				if (ch_result[channel] != bytemask)
+					done = false;
+			}
+			printk(RCVEN_PLOT, "\n");
+			if (done)
+				break;
+		}
+		printk(BIOS_DEBUG, "\n");
+		if (!done) {
+			printk(BIOS_ERR, "Error: Preamble edge not found for all bytes\n");
+			printk(BIOS_ERR, "The final RcvEn results are as follows:\n");
+			for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
+				if (!rank_in_ch(ctrl, rank, channel))
+					continue;
+
+				printk(BIOS_ERR, "Channel %u Rank %u:  preamble\n",
+					channel, rank);
+				for (uint8_t byte = 0; byte < ctrl->lanes; byte++) {
+					printk(BIOS_ERR, " Byte %u: %u%s\n", byte,
+						ctrl->rcven[channel][rank][byte],
+						(ch_result[channel] ^ bytemask) & BIT(byte)
+							? ""
+							: " *** Check this byte! ***");
+				}
+			}
+			status = RAMINIT_STATUS_RCVEN_FAILURE;
+			goto clean_up;
+		}
+
+		printk(BIOS_DEBUG, "Step 6: center on preamble and clean up rank\n");
+		for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
+			if (!rank_in_ch(ctrl, rank, channel))
+				continue;
+
+			printk(BIOS_DEBUG, "C%u:  Preamble increment\n", channel);
+			for (uint8_t byte = 0; byte < ctrl->lanes; byte++) {
+				/*
+				 * For Traditional, pull in RcvEn by 64. For ULT, take the DQS
+				 * drift into account to the specified guardband: tDQSCK_DRIFT.
+				 */
+				ctrl->rcven[channel][rank][byte] -= tDQSCK_DRIFT;
+				update_rxt(ctrl, channel, rank, byte, RXT_RESTORE, 0);
+				printk(BIOS_DEBUG, " B%u: %u      %u\n", byte,
+					ctrl->rcven[channel][rank][byte],
+					inc_preamble[channel][byte]);
+			}
+			printk(BIOS_DEBUG, "\n");
+		}
+		printk(BIOS_DEBUG, "\n");
+	}
+
+clean_up:
+	for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
+		if (!does_ch_exist(ctrl, channel))
+			continue;
+
+		if (ctrl->lpddr) {
+			/**
+			 * W/A for b4618574 - @todo: remove for HSW ULT C0
+			 * Can't have force_odt_on together with leaker, disable LPDDR mode for
+			 * this training step. This write will disable force_odt_on while still
+			 * keeping LPDDR mode disabled. Second write will restore LPDDR mode.
+			 */
+			union ddr_data_control_0_reg data_control_0 = {
+				.raw = ctrl->dq_control_0[channel],
+			};
+			data_control_0.lpddr_mode = 0;
+			mchbar_write32(DDR_DATA_ch_CONTROL_0(channel), data_control_0.raw);
+		}
+		mchbar_write32(DDR_DATA_ch_CONTROL_0(channel), ctrl->dq_control_0[channel]);
+		for (uint8_t byte = 0; byte < ctrl->lanes; byte++) {
+			mchbar_write32(DQ_CONTROL_2(channel, byte),
+					ctrl->dq_control_2[channel][byte]);
+		}
+	}
+	io_reset();
+	if (status)
+		return status;
+
+	printk(BIOS_DEBUG, "Step 7: Sync IO latency across all ranks\n");
+	for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
+		if (!does_ch_exist(ctrl, channel))
+			continue;
+
+		status = change_rcven_timing(ctrl, channel);
+		if (status)
+			return status;
+	}
+	printk(BIOS_DEBUG, "\nFinal Receive Enable and IO latency settings:\n");
+	for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
+		if (!does_ch_exist(ctrl, channel))
+			continue;
+
+		for (uint8_t rank = 0; rank < NUM_SLOTRANKS; rank++) {
+			if (!rank_in_ch(ctrl, rank, channel))
+				continue;
+
+			const union sc_io_latency_reg sc_io_latency = {
+				.raw = mchbar_read32(SC_IO_LATENCY_ch(channel)),
+			};
+			printk(BIOS_DEBUG, "  C%u.R%u: IOLAT = %u  rt_iocomp = %u\n", channel,
+				rank, ctrl->io_latency[channel][rank], sc_io_latency.rt_iocomp);
+			for (uint8_t byte = 0; byte < ctrl->lanes; byte++) {
+				printk(BIOS_DEBUG, "   B%u:   %u\n", byte,
+					ctrl->rcven[channel][rank][byte]);
+			}
+			printk(BIOS_DEBUG, "\n");
+		}
+	}
+	return status;
+}
diff --git a/src/northbridge/intel/haswell/registers/mchbar.h b/src/northbridge/intel/haswell/registers/mchbar.h
index a81559bb1e..9172d4f2b0 100644
--- a/src/northbridge/intel/haswell/registers/mchbar.h
+++ b/src/northbridge/intel/haswell/registers/mchbar.h
@@ -18,6 +18,8 @@
 #define RX_TRAIN_ch_r_b(ch, rank, byte)		_DDRIO_C_R_B(0x0000, ch, rank, byte)
 #define TX_TRAIN_ch_r_b(ch, rank, byte)		_DDRIO_C_R_B(0x0020, ch, rank, byte)
 
+#define DDR_DATA_TRAIN_FEEDBACK(ch, byte)	_DDRIO_C_R_B(0x0054, ch, 0, byte)
+
 #define DQ_CONTROL_2(ch, byte)			_DDRIO_C_R_B(0x0064, ch, 0, byte)
 #define DQ_CONTROL_0(ch, byte)			_DDRIO_C_R_B(0x0074, ch, 0, byte)
 
@@ -100,6 +102,7 @@
 #define COMMAND_RATE_LIMIT_ch(ch)		_MCMAIN_C(0x4010, ch)
 #define TC_BANK_RANK_D_ch(ch)			_MCMAIN_C(0x4014, ch)
 #define SC_ROUNDT_LAT_ch(ch)			_MCMAIN_C(0x4024, ch)
+#define SC_IO_LATENCY_ch(ch)			_MCMAIN_C(0x4028, ch)
 
 #define REUT_ch_PAT_WDB_CL_MUX_CFG(ch)		_MCMAIN_C(0x4040, ch)
 

From 47f31f24d4be9ebc56db4bcce28ac2939ebfcabb Mon Sep 17 00:00:00 2001
From: Angel Pons <th3fanbus@gmail.com>
Date: Sun, 8 May 2022 11:58:59 +0200
Subject: [PATCH 0311/3886] haswell NRI: Add function to change margins

Implement a function to change margin parameters. Haswell provides a
register to apply an offset to margin parameters during training, so
make use of it. There are other margin parameters that have not been
implemented yet, as they are not needed for now and special handling
is needed to provide offset training functionality.

Change-Id: I5392380e13de3c44e77b7bc9f3b819e2661d1e2d
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64195
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
---
 .../haswell/native_raminit/change_margin.c    | 136 ++++++++++++++++++
 .../haswell/native_raminit/raminit_native.h   |  39 +++++
 .../haswell/native_raminit/reg_structs.h      |  12 ++
 .../intel/haswell/registers/mchbar.h          |   1 +
 4 files changed, 188 insertions(+)

diff --git a/src/northbridge/intel/haswell/native_raminit/change_margin.c b/src/northbridge/intel/haswell/native_raminit/change_margin.c
index 055c666eee..299c44a6b0 100644
--- a/src/northbridge/intel/haswell/native_raminit/change_margin.c
+++ b/src/northbridge/intel/haswell/native_raminit/change_margin.c
@@ -1,5 +1,6 @@
 /* SPDX-License-Identifier: GPL-2.0-or-later */
 
+#include <assert.h>
 #include <commonlib/bsd/clamp.h>
 #include <console/console.h>
 #include <delay.h>
@@ -152,3 +153,138 @@ void download_regfile(
 	ddr_data_control_0.read_rf_rank = phys_rank;
 	mchbar_write32(reg, ddr_data_control_0.raw);
 }
+
+static void update_data_offset_train(
+	struct sysinfo *ctrl,
+	const uint8_t param,
+	const uint8_t en_multicast,
+	const uint8_t channel_in,
+	const uint8_t rank,
+	const uint8_t byte_in,
+	const bool update_ctrl,
+	const enum regfile_mode regfile,
+	const uint32_t value)
+{
+	bool is_rd = false;
+	bool is_wr = false;
+	switch (param) {
+	case RdT:
+	case RdV:
+	case RcvEna:
+		is_rd = true;
+		break;
+	case WrT:
+	case WrDqsT:
+		is_wr = true;
+		break;
+	default:
+		die("%s: Invalid margin parameter %u\n", __func__, param);
+	}
+	if (en_multicast) {
+		mchbar_write32(DDR_DATA_OFFSET_TRAIN, value);
+		for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
+			if (!does_ch_exist(ctrl, channel))
+				continue;
+
+			download_regfile(ctrl, channel, true, rank, regfile, 0, is_rd, is_wr);
+			if (update_ctrl) {
+				for (uint8_t byte = 0; byte < ctrl->lanes; byte++)
+					ctrl->data_offset_train[channel][byte] = value;
+			}
+		}
+	} else {
+		mchbar_write32(DDR_DATA_OFFSET_TRAIN_ch_b(channel_in, byte_in), value);
+		download_regfile(ctrl, channel_in, false, rank, regfile, byte_in, is_rd, is_wr);
+		if (update_ctrl)
+			ctrl->data_offset_train[channel_in][byte_in] = value;
+	}
+}
+
+static uint32_t get_max_margin(const enum margin_parameter param)
+{
+	switch (param) {
+	case RcvEna:
+	case RdT:
+	case WrT:
+	case WrDqsT:
+		return MAX_POSSIBLE_TIME;
+	case RdV:
+		return MAX_POSSIBLE_VREF;
+	default:
+		die("%s: Invalid margin parameter %u\n", __func__, param);
+	}
+}
+
+void change_margin(
+	struct sysinfo *ctrl,
+	const enum margin_parameter param,
+	const int32_t value0,
+	const bool en_multicast,
+	const uint8_t channel,
+	const uint8_t rank,
+	const uint8_t byte,
+	const bool update_ctrl,
+	const enum regfile_mode regfile)
+{
+	/** FIXME: Remove this **/
+	if (rank == 0xff)
+		die("%s: rank is 0xff\n", __func__);
+
+	if (!en_multicast && !does_ch_exist(ctrl, channel))
+		die("%s: Tried to change margin of empty channel %u\n", __func__, channel);
+
+	const uint32_t max_value = get_max_margin(param);
+	const int32_t v0 = clamp_s32(-max_value, value0, max_value);
+
+	union ddr_data_offset_train_reg ddr_data_offset_train = {
+		.raw = en_multicast ? 0 : ctrl->data_offset_train[channel][byte],
+	};
+	bool update_offset_train = false;
+	switch (param) {
+	case RcvEna:
+		ddr_data_offset_train.rcven = v0;
+		update_offset_train = true;
+		break;
+	case RdT:
+		ddr_data_offset_train.rx_dqs = v0;
+		update_offset_train = true;
+		break;
+	case WrT:
+		ddr_data_offset_train.tx_dq = v0;
+		update_offset_train = true;
+		break;
+	case WrDqsT:
+		ddr_data_offset_train.tx_dqs = v0;
+		update_offset_train = true;
+		break;
+	case RdV:
+		ddr_data_offset_train.vref = v0;
+		update_offset_train = true;
+		break;
+	default:
+		die("%s: Invalid margin parameter %u\n", __func__, param);
+	}
+	if (update_offset_train) {
+		update_data_offset_train(
+			ctrl,
+			param,
+			en_multicast,
+			channel,
+			rank,
+			byte,
+			update_ctrl,
+			regfile,
+			ddr_data_offset_train.raw);
+	}
+}
+
+void change_1d_margin_multicast(
+	struct sysinfo *ctrl,
+	const enum margin_parameter param,
+	const int32_t value0,
+	const uint8_t rank,
+	const bool update_ctrl,
+	const enum regfile_mode regfile)
+{
+	change_margin(ctrl, param, value0, true, 0, rank, 0, update_ctrl, regfile);
+}
diff --git a/src/northbridge/intel/haswell/native_raminit/raminit_native.h b/src/northbridge/intel/haswell/native_raminit/raminit_native.h
index eaaaedad1e..1c8473056b 100644
--- a/src/northbridge/intel/haswell/native_raminit/raminit_native.h
+++ b/src/northbridge/intel/haswell/native_raminit/raminit_native.h
@@ -36,6 +36,18 @@
 
 #define RTTNOM_MASK		(BIT(9) | BIT(6) | BIT(2))
 
+/* Margin parameter limits */
+#define MAX_POSSIBLE_TIME	31
+#define MAX_POSSIBLE_VREF	54
+
+#define MAX_POSSIBLE_BOTH	MAX_POSSIBLE_VREF
+
+#define MIN_TIME		(-MAX_POSSIBLE_TIME)
+#define MAX_TIME		(MAX_POSSIBLE_TIME)
+
+#define MIN_VREF		(-MAX_POSSIBLE_VREF)
+#define MAX_VREF		(MAX_POSSIBLE_VREF)
+
 #define BASIC_VA_PAT_SPREAD_8	0x01010101
 
 #define WDB_CACHE_LINE_SIZE	8
@@ -46,6 +58,14 @@
 /* Specified in PI ticks. 64 PI ticks == 1 qclk */
 #define tDQSCK_DRIFT		64
 
+enum margin_parameter {
+	RcvEna,
+	RdT,
+	WrT,
+	WrDqsT,
+	RdV,
+};
+
 /* ZQ calibration types */
 enum {
 	ZQ_INIT,	/* DDR3: ZQCL with tZQinit, LPDDR3: ZQ Init  with tZQinit  */
@@ -515,6 +535,25 @@ void download_regfile(
 	bool read_rf_rd,
 	bool read_rf_wr);
 
+void change_margin(
+	struct sysinfo *ctrl,
+	const enum margin_parameter param,
+	const int32_t value0,
+	const bool en_multicast,
+	const uint8_t channel,
+	const uint8_t rank,
+	const uint8_t byte,
+	const bool update_ctrl,
+	const enum regfile_mode regfile);
+
+void change_1d_margin_multicast(
+	struct sysinfo *ctrl,
+	const enum margin_parameter param,
+	const int32_t value0,
+	const uint8_t rank,
+	const bool update_ctrl,
+	const enum regfile_mode regfile);
+
 uint8_t get_rx_bias(const struct sysinfo *ctrl);
 
 uint8_t get_tCWL(uint32_t mem_clock_mhz);
diff --git a/src/northbridge/intel/haswell/native_raminit/reg_structs.h b/src/northbridge/intel/haswell/native_raminit/reg_structs.h
index b099f4bb82..a0e36ed082 100644
--- a/src/northbridge/intel/haswell/native_raminit/reg_structs.h
+++ b/src/northbridge/intel/haswell/native_raminit/reg_structs.h
@@ -25,6 +25,18 @@ union ddr_data_tx_train_rank_reg {
 	uint32_t raw;
 };
 
+union ddr_data_offset_train_reg {
+	struct __packed {
+		int32_t rcven  : 6; // Bits  5:0
+		int32_t rx_dqs : 6; // Bits 11:6
+		int32_t tx_dq  : 6; // Bits 17:12
+		int32_t tx_dqs : 6; // Bits 23:18
+		int32_t vref   : 7; // Bits 30:24
+		int32_t        : 1; // Bits 31:31
+	};
+	uint32_t raw;
+};
+
 union ddr_data_control_0_reg {
 	struct __packed {
 		uint32_t rx_training_mode      : 1; // Bits  0:0
diff --git a/src/northbridge/intel/haswell/registers/mchbar.h b/src/northbridge/intel/haswell/registers/mchbar.h
index 9172d4f2b0..0acafbc826 100644
--- a/src/northbridge/intel/haswell/registers/mchbar.h
+++ b/src/northbridge/intel/haswell/registers/mchbar.h
@@ -21,6 +21,7 @@
 #define DDR_DATA_TRAIN_FEEDBACK(ch, byte)	_DDRIO_C_R_B(0x0054, ch, 0, byte)
 
 #define DQ_CONTROL_2(ch, byte)			_DDRIO_C_R_B(0x0064, ch, 0, byte)
+#define DDR_DATA_OFFSET_TRAIN_ch_b(ch, byte)	_DDRIO_C_R_B(0x0070, ch, 0, byte)
 #define DQ_CONTROL_0(ch, byte)			_DDRIO_C_R_B(0x0074, ch, 0, byte)
 
 /* DDR CKE per-channel */

From 7d8f12b5654f0dfdad033552d7a19f90f15789c1 Mon Sep 17 00:00:00 2001
From: Angel Pons <th3fanbus@gmail.com>
Date: Sun, 8 May 2022 11:35:49 +0200
Subject: [PATCH 0312/3886] haswell NRI: Add read MPR training

Implement read training using DDR3 MPR (Multi-Purpose Register).

Change-Id: Id17cb2c4c399ac9bcc937b595b58f863c152461b
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64196
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 .../intel/haswell/native_raminit/Makefile.mk  |   1 +
 .../haswell/native_raminit/raminit_main.c     |   1 +
 .../haswell/native_raminit/raminit_native.h   |   4 +
 .../haswell/native_raminit/train_read_mpr.c   | 241 ++++++++++++++++++
 .../intel/haswell/registers/mchbar.h          |   2 +-
 5 files changed, 248 insertions(+), 1 deletion(-)
 create mode 100644 src/northbridge/intel/haswell/native_raminit/train_read_mpr.c

diff --git a/src/northbridge/intel/haswell/native_raminit/Makefile.mk b/src/northbridge/intel/haswell/native_raminit/Makefile.mk
index e2fbfb4211..c442be0728 100644
--- a/src/northbridge/intel/haswell/native_raminit/Makefile.mk
+++ b/src/northbridge/intel/haswell/native_raminit/Makefile.mk
@@ -16,4 +16,5 @@ romstage-y += setup_wdb.c
 romstage-y += spd_bitmunching.c
 romstage-y += testing_io.c
 romstage-y += timings_refresh.c
+romstage-y += train_read_mpr.c
 romstage-y += train_receive_enable.c
diff --git a/src/northbridge/intel/haswell/native_raminit/raminit_main.c b/src/northbridge/intel/haswell/native_raminit/raminit_main.c
index 97eb957294..82f1b945ba 100644
--- a/src/northbridge/intel/haswell/native_raminit/raminit_main.c
+++ b/src/northbridge/intel/haswell/native_raminit/raminit_main.c
@@ -62,6 +62,7 @@ static const struct task_entry cold_boot[] = {
 	{ do_jedec_init,                                          true, "JEDECINIT",  },
 	{ pre_training,                                           true, "PRETRAIN",   },
 	{ train_receive_enable,                                   true, "RCVET",      },
+	{ train_read_mpr,                                         true, "RDMPRT",     },
 };
 
 /* Return a generic stepping value to make stepping checks simpler */
diff --git a/src/northbridge/intel/haswell/native_raminit/raminit_native.h b/src/northbridge/intel/haswell/native_raminit/raminit_native.h
index 1c8473056b..7a486479ea 100644
--- a/src/northbridge/intel/haswell/native_raminit/raminit_native.h
+++ b/src/northbridge/intel/haswell/native_raminit/raminit_native.h
@@ -28,6 +28,8 @@
 /* Always use 12 legs for emphasis (not trained) */
 #define TXEQFULLDRV		(3 << 4)
 
+#define LOOPCOUNT_INFINITE	0xff
+
 /* DDR3 mode register bits */
 #define MR0_DLL_RESET		BIT(8)
 
@@ -213,6 +215,7 @@ enum raminit_status {
 	RAMINIT_STATUS_POLL_TIMEOUT,
 	RAMINIT_STATUS_REUT_ERROR,
 	RAMINIT_STATUS_RCVEN_FAILURE,
+	RAMINIT_STATUS_RMPR_FAILURE,
 	RAMINIT_STATUS_UNSPECIFIED_ERROR, /** TODO: Deprecated in favor of specific values **/
 };
 
@@ -434,6 +437,7 @@ enum raminit_status configure_mc(struct sysinfo *ctrl);
 enum raminit_status configure_memory_map(struct sysinfo *ctrl);
 enum raminit_status do_jedec_init(struct sysinfo *ctrl);
 enum raminit_status train_receive_enable(struct sysinfo *ctrl);
+enum raminit_status train_read_mpr(struct sysinfo *ctrl);
 
 void configure_timings(struct sysinfo *ctrl);
 void configure_refresh(struct sysinfo *ctrl);
diff --git a/src/northbridge/intel/haswell/native_raminit/train_read_mpr.c b/src/northbridge/intel/haswell/native_raminit/train_read_mpr.c
new file mode 100644
index 0000000000..ade1e36148
--- /dev/null
+++ b/src/northbridge/intel/haswell/native_raminit/train_read_mpr.c
@@ -0,0 +1,241 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <commonlib/bsd/clamp.h>
+#include <console/console.h>
+#include <delay.h>
+#include <northbridge/intel/haswell/haswell.h>
+#include <types.h>
+
+#include "raminit_native.h"
+#include "ranges.h"
+
+#define RMPR_START	(-32)
+#define RMPR_STOP	(32)
+#define RMPR_STEP	1
+
+#define RMPR_MIN_WIDTH	12
+
+#define RMPR_PLOT	RAM_DEBUG
+
+/*
+ * Clear rx_training_mode. For LPDDR, we first need to disable odt_samp_extend_en,
+ * then disable rx_training_mode, and finally re-enable odt_samp_extend_en.
+ */
+static void clear_rx_training_mode(struct sysinfo *ctrl, const uint8_t channel)
+{
+	for (uint8_t byte = 0; byte < ctrl->lanes; byte++)
+		mchbar_write32(DQ_CONTROL_2(channel, byte), ctrl->dq_control_2[channel][byte]);
+
+	if (ctrl->lpddr) {
+		union ddr_data_control_0_reg data_control_0 = {
+			.raw = mchbar_read32(DDR_DATA_ch_CONTROL_0(channel)),
+		};
+		data_control_0.odt_samp_extend_en = 0;
+		mchbar_write32(DDR_DATA_ch_CONTROL_0(channel), data_control_0.raw);
+		tick_delay(1);
+		data_control_0.rx_training_mode = 0;
+		mchbar_write32(DDR_DATA_ch_CONTROL_0(channel), data_control_0.raw);
+		tick_delay(1);
+	}
+	mchbar_write32(DDR_DATA_ch_CONTROL_0(channel), ctrl->dq_control_0[channel]);
+}
+
+static void set_rxdqs_edges_to_midpoint(struct sysinfo *ctrl)
+{
+	for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
+		if (!does_ch_exist(ctrl, channel))
+			continue;
+
+		for (uint8_t rank = 0; rank < NUM_SLOTRANKS; rank++) {
+			if (!rank_in_ch(ctrl, rank, channel))
+				continue;
+
+			for (uint8_t byte = 0; byte < ctrl->lanes; byte++)
+				update_rxt(ctrl, channel, rank, byte, RXT_RXDQS_BOTH, 32);
+		}
+	}
+}
+
+static void enter_mpr_train_ddr_mode(struct sysinfo *ctrl, const uint8_t rank)
+{
+	/* Program MR3 and mask RAS/WE to prevent scheduler from issuing non-read commands */
+	for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
+		if (!rank_in_ch(ctrl, rank, channel))
+			continue;
+
+		if (!ctrl->lpddr)
+			reut_issue_mrs(ctrl, channel, BIT(rank), 3, 1 << 2);
+
+		union reut_misc_odt_ctrl_reg reut_misc_odt_ctrl = {
+			.raw = mchbar_read32(REUT_ch_MISC_ODT_CTRL(channel)),
+		};
+		reut_misc_odt_ctrl.mpr_train_ddr_on = 1;
+		mchbar_write32(REUT_ch_MISC_ODT_CTRL(channel), reut_misc_odt_ctrl.raw);
+	}
+}
+
+static void leave_mpr_train_ddr_mode(struct sysinfo *ctrl, const uint8_t rank)
+{
+	for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
+		if (!rank_in_ch(ctrl, rank, channel))
+			continue;
+
+		/*
+		 * The mpr_train_ddr_on bit will force a special command.
+		 * Therefore, clear it before issuing the MRS command.
+		 */
+		union reut_misc_odt_ctrl_reg reut_misc_odt_ctrl = {
+			.raw = mchbar_read32(REUT_ch_MISC_ODT_CTRL(channel)),
+		};
+		reut_misc_odt_ctrl.mpr_train_ddr_on = 0;
+		mchbar_write32(REUT_ch_MISC_ODT_CTRL(channel), reut_misc_odt_ctrl.raw);
+		if (!ctrl->lpddr)
+			reut_issue_mrs(ctrl, channel, BIT(rank), 3, 0 << 2);
+	}
+}
+
+enum raminit_status train_read_mpr(struct sysinfo *ctrl)
+{
+	set_rxdqs_edges_to_midpoint(ctrl);
+	clear_data_offset_train_all(ctrl);
+	setup_io_test_mpr(ctrl, ctrl->chanmap, LOOPCOUNT_INFINITE, NSOE);
+	enum raminit_status status = RAMINIT_STATUS_SUCCESS;
+	for (uint8_t rank = 0; rank < NUM_SLOTRANKS; rank++) {
+		if (!does_rank_exist(ctrl, rank))
+			continue;
+
+		printk(BIOS_DEBUG, "Rank %u\n", rank);
+		printk(RMPR_PLOT, "Channel");
+		for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
+			if (!rank_in_ch(ctrl, rank, channel))
+				continue;
+
+			printk(RMPR_PLOT, "\t%u\t\t", channel);
+		}
+		printk(RMPR_PLOT, "\nByte");
+		for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
+			if (!rank_in_ch(ctrl, rank, channel))
+				continue;
+
+			printk(RMPR_PLOT, "\t");
+			for (uint8_t byte = 0; byte < ctrl->lanes; byte++)
+				printk(RMPR_PLOT, "%u ", byte);
+		}
+		enter_mpr_train_ddr_mode(ctrl, rank);
+		struct linear_train_data region_data[NUM_CHANNELS][NUM_LANES] = { 0 };
+		for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++)
+			select_reut_ranks(ctrl, channel, BIT(rank));
+
+		printk(RMPR_PLOT, "\nDqsDelay\n");
+		int8_t dqs_delay;
+		for (dqs_delay = RMPR_START; dqs_delay < RMPR_STOP; dqs_delay += RMPR_STEP) {
+			printk(RMPR_PLOT, "% 5d", dqs_delay);
+			const enum regfile_mode regfile = REG_FILE_USE_START;
+			/* Looks like MRC uses rank 0 here, but it feels wrong */
+			change_1d_margin_multicast(ctrl, RdT, dqs_delay, rank, false, regfile);
+			for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
+				if (!rank_in_ch(ctrl, rank, channel))
+					continue;
+
+				for (uint8_t byte = 0; byte < ctrl->lanes; byte++) {
+					union ddr_data_control_2_reg data_control_2 = {
+						.raw = ctrl->dq_control_2[channel][byte],
+					};
+					data_control_2.force_bias_on = 1;
+					data_control_2.force_rx_on   = 1;
+					data_control_2.leaker_comp   = 0;
+					mchbar_write32(DQ_CONTROL_2(channel, byte),
+						data_control_2.raw);
+				}
+				union ddr_data_control_0_reg data_control_0 = {
+					.raw = ctrl->dq_control_0[channel],
+				};
+				data_control_0.rx_training_mode   = 1;
+				data_control_0.force_odt_on       = !ctrl->lpddr;
+				data_control_0.en_read_preamble   = 0;
+				data_control_0.odt_samp_extend_en = ctrl->lpddr;
+				const uint32_t reg_offset = DDR_DATA_ch_CONTROL_0(channel);
+				mchbar_write32(reg_offset, data_control_0.raw);
+			}
+			run_mpr_io_test(false);
+			for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
+				if (!rank_in_ch(ctrl, rank, channel))
+					continue;
+
+				printk(RMPR_PLOT, "\t");
+				for (uint8_t byte = 0; byte < ctrl->lanes; byte++) {
+					uint32_t fb = get_data_train_feedback(channel, byte);
+					const bool pass = fb == 1;
+					printk(RMPR_PLOT, pass ? ". " : "# ");
+					linear_record_pass(
+						&region_data[channel][byte],
+						pass,
+						dqs_delay,
+						RMPR_START,
+						RMPR_STEP);
+				}
+			}
+			printk(RMPR_PLOT, "\n");
+			for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
+				if (!rank_in_ch(ctrl, rank, channel))
+					continue;
+
+				clear_rx_training_mode(ctrl, channel);
+			}
+			io_reset();
+		}
+		printk(RMPR_PLOT, "\n");
+		leave_mpr_train_ddr_mode(ctrl, rank);
+		clear_data_offset_train_all(ctrl);
+		for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
+			if (!rank_in_ch(ctrl, rank, channel))
+				continue;
+
+			printk(BIOS_DEBUG, "C%u.R%u: \tLeft\tRight\tWidth\tCenter\tRxDqsPN\n",
+				channel, rank);
+			for (uint8_t byte = 0; byte < ctrl->lanes; byte++) {
+				struct linear_train_data *data = &region_data[channel][byte];
+				const int32_t lwidth = range_width(data->largest);
+				if (lwidth <= RMPR_MIN_WIDTH) {
+					printk(BIOS_ERR,
+						"Bad eye (lwidth %d <= min %d) for byte %u\n",
+						lwidth, RMPR_MIN_WIDTH, byte);
+					status = RAMINIT_STATUS_RMPR_FAILURE;
+				}
+				/*
+				 * The MPR center may not be ideal on certain platforms for
+				 * unknown reasons. If so, adjust it with a magical number.
+				 * For Haswell, the magical number is zero. Hell knows why.
+				 */
+				const int32_t center = range_center(data->largest);
+				ctrl->rxdqsp[channel][rank][byte] = center - RMPR_START;
+				ctrl->rxdqsn[channel][rank][byte] = center - RMPR_START;
+				printk(BIOS_DEBUG, "  B%u: \t%d\t%d\t%d\t%d\t%u\n", byte,
+					data->largest.start, data->largest.end, lwidth,
+					center, ctrl->rxdqsp[channel][rank][byte]);
+			}
+			printk(BIOS_DEBUG, "\n");
+		}
+	}
+
+	/*
+	 * Now program the DQS center values on populated ranks. data is taken from
+	 * the host struct. We need to do it after all ranks are trained, because we
+	 * need to keep the same DQS value on all ranks during the training procedure.
+	 */
+	for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
+		if (!does_ch_exist(ctrl, channel))
+			continue;
+
+		for (uint8_t rank = 0; rank < NUM_SLOTRANKS; rank++) {
+			if (!rank_in_ch(ctrl, rank, channel))
+				continue;
+
+			for (uint8_t byte = 0; byte < ctrl->lanes; byte++)
+				update_rxt(ctrl, channel, rank, byte, RXT_RESTORE, 0);
+		}
+	}
+	change_1d_margin_multicast(ctrl, RdT, 0, 0, false, REG_FILE_USE_CURRENT);
+	io_reset();
+	return status;
+}
diff --git a/src/northbridge/intel/haswell/registers/mchbar.h b/src/northbridge/intel/haswell/registers/mchbar.h
index 0acafbc826..6a31d3a32c 100644
--- a/src/northbridge/intel/haswell/registers/mchbar.h
+++ b/src/northbridge/intel/haswell/registers/mchbar.h
@@ -122,7 +122,7 @@
 #define REUT_ch_ERR_DATA_MASK(ch)		_MCMAIN_C(0x40d8, ch)
 
 #define REUT_ch_MISC_CKE_CTRL(ch)		_MCMAIN_C(0x4190, ch)
-
+#define REUT_ch_MISC_ODT_CTRL(ch)		_MCMAIN_C(0x4194, ch)
 #define REUT_ch_MISC_PAT_CADB_CTRL(ch)		_MCMAIN_C(0x4198, ch)
 #define REUT_ch_PAT_CADB_MRS(ch)		_MCMAIN_C(0x419c, ch)
 #define REUT_ch_PAT_CADB_MUX_CTRL(ch)		_MCMAIN_C(0x41a0, ch)

From 174380c9046975cef79a7faa2d54e007ca44d2be Mon Sep 17 00:00:00 2001
From: Angel Pons <th3fanbus@gmail.com>
Date: Sun, 8 May 2022 12:56:04 +0200
Subject: [PATCH 0313/3886] haswell NRI: Add write leveling

Implement JEDEC write leveling, which is done in two steps. The first
step uses the JEDEC procedure to do "fine" write leveling, i.e. align
the DQS phase to the clock signal. The second step performs a regular
read-write test to correct "coarse" cycle errors.

Change-Id: I27678523fe22c38173a688e2a4751c259a20f009
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64197
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
---
 .../intel/haswell/native_raminit/Makefile.mk  |   1 +
 .../haswell/native_raminit/raminit_main.c     |   1 +
 .../haswell/native_raminit/raminit_native.h   |  10 +
 .../train_jedec_write_leveling.c              | 581 ++++++++++++++++++
 .../intel/haswell/registers/mchbar.h          |   2 +
 5 files changed, 595 insertions(+)
 create mode 100644 src/northbridge/intel/haswell/native_raminit/train_jedec_write_leveling.c

diff --git a/src/northbridge/intel/haswell/native_raminit/Makefile.mk b/src/northbridge/intel/haswell/native_raminit/Makefile.mk
index c442be0728..40c2f5e014 100644
--- a/src/northbridge/intel/haswell/native_raminit/Makefile.mk
+++ b/src/northbridge/intel/haswell/native_raminit/Makefile.mk
@@ -16,5 +16,6 @@ romstage-y += setup_wdb.c
 romstage-y += spd_bitmunching.c
 romstage-y += testing_io.c
 romstage-y += timings_refresh.c
+romstage-y += train_jedec_write_leveling.c
 romstage-y += train_read_mpr.c
 romstage-y += train_receive_enable.c
diff --git a/src/northbridge/intel/haswell/native_raminit/raminit_main.c b/src/northbridge/intel/haswell/native_raminit/raminit_main.c
index 82f1b945ba..b947ecbd46 100644
--- a/src/northbridge/intel/haswell/native_raminit/raminit_main.c
+++ b/src/northbridge/intel/haswell/native_raminit/raminit_main.c
@@ -63,6 +63,7 @@ static const struct task_entry cold_boot[] = {
 	{ pre_training,                                           true, "PRETRAIN",   },
 	{ train_receive_enable,                                   true, "RCVET",      },
 	{ train_read_mpr,                                         true, "RDMPRT",     },
+	{ train_jedec_write_leveling,                             true, "JWRL",       },
 };
 
 /* Return a generic stepping value to make stepping checks simpler */
diff --git a/src/northbridge/intel/haswell/native_raminit/raminit_native.h b/src/northbridge/intel/haswell/native_raminit/raminit_native.h
index 7a486479ea..d6b11b9d3c 100644
--- a/src/northbridge/intel/haswell/native_raminit/raminit_native.h
+++ b/src/northbridge/intel/haswell/native_raminit/raminit_native.h
@@ -60,6 +60,9 @@
 /* Specified in PI ticks. 64 PI ticks == 1 qclk */
 #define tDQSCK_DRIFT		64
 
+/* Maximum additional latency */
+#define MAX_ADD_DELAY		2
+
 enum margin_parameter {
 	RcvEna,
 	RdT,
@@ -216,6 +219,7 @@ enum raminit_status {
 	RAMINIT_STATUS_REUT_ERROR,
 	RAMINIT_STATUS_RCVEN_FAILURE,
 	RAMINIT_STATUS_RMPR_FAILURE,
+	RAMINIT_STATUS_JWRL_FAILURE,
 	RAMINIT_STATUS_UNSPECIFIED_ERROR, /** TODO: Deprecated in favor of specific values **/
 };
 
@@ -381,6 +385,11 @@ static inline uint32_t get_data_train_feedback(const uint8_t channel, const uint
 	return mchbar_read32(DDR_DATA_TRAIN_FEEDBACK(channel, byte));
 }
 
+static inline uint16_t get_byte_group_errors(const uint8_t channel)
+{
+	return mchbar_read32(4 + REUT_ch_ERR_MISC_STATUS(channel)) & 0x1ff;
+}
+
 /* Number of ticks to wait in units of 69.841279 ns (citation needed) */
 static inline void tick_delay(const uint32_t delay)
 {
@@ -438,6 +447,7 @@ enum raminit_status configure_memory_map(struct sysinfo *ctrl);
 enum raminit_status do_jedec_init(struct sysinfo *ctrl);
 enum raminit_status train_receive_enable(struct sysinfo *ctrl);
 enum raminit_status train_read_mpr(struct sysinfo *ctrl);
+enum raminit_status train_jedec_write_leveling(struct sysinfo *ctrl);
 
 void configure_timings(struct sysinfo *ctrl);
 void configure_refresh(struct sysinfo *ctrl);
diff --git a/src/northbridge/intel/haswell/native_raminit/train_jedec_write_leveling.c b/src/northbridge/intel/haswell/native_raminit/train_jedec_write_leveling.c
new file mode 100644
index 0000000000..ef6483e2bd
--- /dev/null
+++ b/src/northbridge/intel/haswell/native_raminit/train_jedec_write_leveling.c
@@ -0,0 +1,581 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <assert.h>
+#include <console/console.h>
+#include <delay.h>
+#include <northbridge/intel/haswell/haswell.h>
+#include <types.h>
+
+#include "raminit_native.h"
+#include "ranges.h"
+
+#define JWLC_PLOT	RAM_DEBUG
+#define JWRL_PLOT	RAM_DEBUG
+
+static void reset_dram_dll(struct sysinfo *ctrl, const uint8_t channel, const uint8_t rank)
+{
+	const uint16_t mr0reg = ctrl->mr0[channel][rank / 2];
+	reut_issue_mrs(ctrl, channel, BIT(rank), 0, mr0reg | MR0_DLL_RESET);
+}
+
+static void program_wdb_pattern(struct sysinfo *ctrl, const bool invert)
+{
+	/* Pattern to keep DQ-DQS simple but detect any failures. Same as NHM/WSM. */
+	const uint8_t pat[4][2] = {
+		{ 0x00, 0xff },
+		{ 0xff, 0x00 },
+		{ 0xc3, 0x3c },
+		{ 0x3c, 0xc3 },
+	};
+	const uint8_t pmask[2][8] = {
+		{ 0, 0, 1, 1, 1, 1, 0, 0 },
+		{ 1, 1, 0, 0, 0, 0, 1, 1 },
+	};
+	for (uint8_t s = 0; s < ARRAY_SIZE(pat); s++)
+		write_wdb_fixed_pat(ctrl, pat[s], pmask[invert], ARRAY_SIZE(pmask[invert]), s);
+}
+
+static int16_t set_add_delay(uint32_t *add_delay, uint8_t rank, int8_t target_off)
+{
+	const uint8_t shift = rank * 2;
+	if (target_off > MAX_ADD_DELAY) {
+		*add_delay &= ~(3 << shift);
+		*add_delay |= MAX_ADD_DELAY << shift;
+		return 128 * (target_off - MAX_ADD_DELAY);
+	} else if (target_off < 0) {
+		*add_delay &= ~(3 << shift);
+		*add_delay |= 0 << shift;
+		return 128 * target_off;
+	} else {
+		*add_delay &= ~(3 << shift);
+		*add_delay |= target_off << shift;
+		return 0;
+	}
+}
+
+static enum raminit_status train_jedec_write_leveling_cleanup(struct sysinfo *ctrl)
+{
+	const struct reut_box reut_addr = {
+		.col = {
+			.start   = 0,
+			.stop    = 1023,
+			.inc_val = 1,
+		},
+	};
+	const struct wdb_pat wdb_pattern = {
+		.start_ptr  = 0,
+		.stop_ptr   = 3,
+		.inc_rate   = 1,
+		.dq_pattern = BASIC_VA,
+	};
+	const int8_t offsets[] = { 0, 1, -1, 2, 3 };
+	const int8_t dq_offsets[] = { 0, -10, 10, -5, 5, -15, 15 };
+	const uint8_t dq_offset_max = ARRAY_SIZE(dq_offsets);
+
+	/* Set LFSR seeds to be sequential */
+	program_wdb_lfsr(ctrl, true);
+	setup_io_test(
+		ctrl,
+		ctrl->chanmap,
+		PAT_WR_RD,
+		2,
+		4,
+		&reut_addr,
+		NSOE,
+		&wdb_pattern,
+		0,
+		0);
+
+	const union reut_pat_wdb_cl_mux_cfg_reg reut_wdb_cl_mux_cfg = {
+		.mux_0_control       = REUT_MUX_BTBUFFER,
+		.mux_1_control       = REUT_MUX_BTBUFFER,
+		.mux_2_control       = REUT_MUX_BTBUFFER,
+		.ecc_data_source_sel = 1,
+	};
+	for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
+		if (!does_ch_exist(ctrl, channel))
+			continue;
+
+		mchbar_write32(REUT_ch_PAT_WDB_CL_MUX_CFG(channel), reut_wdb_cl_mux_cfg.raw);
+	}
+
+	int8_t byte_off[NUM_CHANNELS][NUM_LANES] = { 0 };
+	uint32_t add_delay[NUM_CHANNELS] = { 0 };
+	enum raminit_status status = RAMINIT_STATUS_SUCCESS;
+	bool invert = false;
+	const uint16_t valid_byte_mask = BIT(ctrl->lanes) - 1;
+	for (uint8_t rank = 0; rank < NUM_SLOTRANKS; rank++) {
+		uint8_t chanmask = 0;
+		for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++)
+			chanmask |= select_reut_ranks(ctrl, channel, BIT(rank));
+
+		if (!chanmask)
+			continue;
+
+		printk(BIOS_DEBUG, "Rank %u\n", rank);
+		printk(JWLC_PLOT, "Channel");
+		for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
+			if (!rank_in_ch(ctrl, rank, channel))
+				continue;
+
+			printk(JWLC_PLOT, "\t\t%u\t", channel);
+		}
+		printk(JWLC_PLOT, "\nByte\t");
+		for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
+			if (!rank_in_ch(ctrl, rank, channel))
+				continue;
+
+			printk(JWLC_PLOT, "\t");
+			for (uint8_t byte = 0; byte < ctrl->lanes; byte++)
+				printk(JWLC_PLOT, "%u ", byte);
+		}
+		printk(JWLC_PLOT, "\nDelay DqOffset");
+		bool done = false;
+		int8_t byte_sum[NUM_CHANNELS] = { 0 };
+		uint16_t byte_pass[NUM_CHANNELS] = { 0 };
+		for (uint8_t off = 0; off < ARRAY_SIZE(offsets); off++) {
+			for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
+				if (!rank_in_ch(ctrl, rank, channel))
+					continue;
+
+				const int16_t global_byte_off =
+					set_add_delay(&add_delay[channel], rank, offsets[off]);
+				for (uint8_t byte = 0; byte < ctrl->lanes; byte++) {
+					update_txt(ctrl, channel, rank, byte, TXT_DQDQS_OFF,
+						global_byte_off);
+				}
+				mchbar_write32(SC_WR_ADD_DELAY_ch(channel),
+						add_delay[channel]);
+			}
+			/* Reset FIFOs and DRAM DLL (Micron workaround) */
+			if (!ctrl->lpddr) {
+				io_reset();
+				for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
+					if (!rank_in_ch(ctrl, rank, channel))
+						continue;
+
+					reset_dram_dll(ctrl, channel, rank);
+				}
+				udelay(1);
+			}
+			for (uint8_t dq_offset = 0; dq_offset < dq_offset_max; dq_offset++) {
+				printk(JWLC_PLOT, "\n% 3d\t% 3d",
+					offsets[off], dq_offsets[dq_offset]);
+				change_1d_margin_multicast(
+					ctrl,
+					WrT,
+					dq_offsets[dq_offset],
+					rank,
+					false,
+					REG_FILE_USE_RANK);
+
+				/*
+				 * Re-program the WDB pattern. Change the pattern
+				 * for the next test to avoid false pass issues.
+				 */
+				program_wdb_pattern(ctrl, invert);
+				invert = !invert;
+				run_io_test(ctrl, chanmask, BASIC_VA, true);
+				done = true;
+				for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
+					if (!rank_in_ch(ctrl, rank, channel))
+						continue;
+
+					printk(JWLC_PLOT, "\t");
+					uint16_t result = get_byte_group_errors(channel);
+					result &= valid_byte_mask;
+
+					/* Skip bytes that have failed or already passed */
+					const uint16_t skip_me = result | byte_pass[channel];
+					for (uint8_t byte = 0; byte < ctrl->lanes; byte++) {
+						const bool pass = result & BIT(byte);
+						printk(JWLC_PLOT, pass ? "# " : ". ");
+						if (skip_me & BIT(byte))
+							continue;
+
+						byte_pass[channel] |= BIT(byte);
+						byte_off[channel][byte] = offsets[off];
+						byte_sum[channel] += offsets[off];
+					}
+					if (byte_pass[channel] != valid_byte_mask)
+						done = false;
+				}
+				if (done)
+					break;
+			}
+			if (done)
+				break;
+		}
+		printk(BIOS_DEBUG, "\n\n");
+		if (!done) {
+			printk(BIOS_ERR, "JWLC: Could not find a pass for all bytes\n");
+			for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
+				if (!rank_in_ch(ctrl, rank, channel))
+					continue;
+
+				printk(BIOS_ERR, "Channel %u, rank %u fail:", channel, rank);
+				const uint16_t passing_mask = byte_pass[channel];
+				for (uint8_t byte = 0; byte < ctrl->lanes; byte++) {
+					if (BIT(byte) & passing_mask)
+						continue;
+
+					printk(BIOS_ERR, " %u", byte);
+				}
+				printk(BIOS_ERR, "\n");
+			}
+			status = RAMINIT_STATUS_JWRL_FAILURE;
+			break;
+		}
+		for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
+			if (!rank_in_ch(ctrl, rank, channel))
+				continue;
+
+			/* Refine target offset to make sure it works for all bytes */
+			int8_t target_off = DIV_ROUND_CLOSEST(byte_sum[channel], ctrl->lanes);
+			int16_t global_byte_off = 0;
+			uint8_t all_good_loops = 0;
+			bool all_good = 0;
+			while (!all_good) {
+				global_byte_off =
+					set_add_delay(&add_delay[channel], rank, target_off);
+				all_good = true;
+				for (uint8_t byte = 0; byte < ctrl->lanes; byte++) {
+					int16_t local_offset;
+					local_offset = byte_off[channel][byte] - target_off;
+					local_offset = local_offset * 128 + global_byte_off;
+					const uint16_t tx_dq = ctrl->tx_dq[channel][rank][byte];
+					if (tx_dq + local_offset >= (512 - 64)) {
+						all_good = false;
+						all_good_loops++;
+						target_off++;
+						break;
+					}
+					const uint16_t txdqs = ctrl->tx_dq[channel][rank][byte];
+					if (txdqs + local_offset < 96) {
+						all_good = false;
+						all_good_loops++;
+						target_off--;
+						break;
+					}
+				}
+				/* Avoid an infinite loop */
+				if (all_good_loops > 3)
+					break;
+			}
+			if (!all_good) {
+				printk(BIOS_ERR, "JWLC: Target offset refining failed\n");
+				status = RAMINIT_STATUS_JWRL_FAILURE;
+				break;
+			}
+			printk(BIOS_DEBUG, "C%u.R%u:  Offset\tFinalEdge\n", channel, rank);
+			for (uint8_t byte = 0; byte < ctrl->lanes; byte++) {
+				int16_t local_offset;
+				local_offset = byte_off[channel][byte] - target_off;
+				local_offset = local_offset * 128 + global_byte_off;
+				ctrl->tx_dq[channel][rank][byte] += local_offset;
+				ctrl->txdqs[channel][rank][byte] += local_offset;
+				update_txt(ctrl, channel, rank, byte, TXT_RESTORE, 0);
+				printk(BIOS_DEBUG, "  B%u:   %d\t%d\n", byte, local_offset,
+					ctrl->txdqs[channel][rank][byte]);
+			}
+			mchbar_write32(SC_WR_ADD_DELAY_ch(channel), add_delay[channel]);
+			if (!ctrl->lpddr) {
+				reset_dram_dll(ctrl, channel, rank);
+				udelay(1);
+			}
+			printk(BIOS_DEBUG, "\n");
+		}
+		printk(BIOS_DEBUG, "\n");
+	}
+
+	/* Restore WDB after test */
+	write_wdb_va_pat(ctrl, 0, BASIC_VA_PAT_SPREAD_8, 8, 0);
+	program_wdb_lfsr(ctrl, false);
+	mchbar_write32(DDR_DATA_OFFSET_TRAIN, 0);
+
+	/** TODO: Do full JEDEC init instead? **/
+	io_reset();
+	return status;
+}
+
+static enum raminit_status verify_wl_width(const int32_t lwidth)
+{
+	if (lwidth <= 32) {
+		/* Check if width is valid */
+		printk(BIOS_ERR, "WrLevel: Width region (%d) too small\n", lwidth);
+		return RAMINIT_STATUS_JWRL_FAILURE;
+	}
+	if (lwidth >= 96) {
+		/* Since we're calibrating a phase, a too large region is a problem */
+		printk(BIOS_ERR, "WrLevel: Width region (%d) too large\n", lwidth);
+		return RAMINIT_STATUS_JWRL_FAILURE;
+	}
+	return 0;
+}
+
+enum raminit_status train_jedec_write_leveling(struct sysinfo *ctrl)
+{
+	/*
+	 * Enabling WL mode causes DQS to toggle for 1024 QCLK.
+	 * Wait for this to stop. Round up to nearest microsecond.
+	 */
+	const bool wl_long_delay = ctrl->lpddr;
+	const uint32_t dqs_toggle_time = wl_long_delay ? 2048 : 1024;
+	const uint32_t wait_time_us = DIV_ROUND_UP(ctrl->qclkps * dqs_toggle_time, 1000 * 1000);
+
+	const uint16_t wl_start = 192;
+	const uint16_t wl_stop  = 192 + 128;
+	const uint16_t wl_step  = 2;
+
+	/* Do not use cached MR values */
+	const bool save_restore_mrs = ctrl->restore_mrs;
+	ctrl->restore_mrs = 0;
+
+	/* Propagate delay values (without a write command) */
+	for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
+		if (!does_ch_exist(ctrl, channel))
+			continue;
+
+		/* Propagate delay values from rank 0 to prevent assertion failures in RTL */
+		union ddr_data_control_0_reg data_control_0 = {
+			.raw = ctrl->dq_control_0[channel],
+		};
+		data_control_0.read_rf_rd   = 0;
+		data_control_0.read_rf_wr   = 1;
+		data_control_0.read_rf_rank = 0;
+		mchbar_write32(DDR_DATA_ch_CONTROL_0(channel), data_control_0.raw);
+		for (uint8_t byte = 0; byte < ctrl->lanes; byte++) {
+			union ddr_data_control_2_reg data_control_2 = {
+				.raw = ctrl->dq_control_2[channel][byte],
+			};
+			data_control_2.force_bias_on = 1;
+			data_control_2.force_rx_on   = 0;
+			data_control_2.wl_long_delay = wl_long_delay;
+			mchbar_write32(DQ_CONTROL_2(channel, byte), data_control_2.raw);
+		}
+	}
+
+	if (ctrl->lpddr)
+		die("%s: Missing LPDDR support\n", __func__);
+
+	if (!ctrl->lpddr)
+		ddr3_program_mr1(ctrl, 0, 1);
+
+	enum raminit_status status = RAMINIT_STATUS_SUCCESS;
+	struct phase_train_data region_data[NUM_CHANNELS][NUM_LANES] = { 0 };
+	for (uint8_t rank = 0; rank < NUM_SLOTRANKS; rank++) {
+		if (!does_rank_exist(ctrl, rank))
+			continue;
+
+		for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
+			if (!rank_in_ch(ctrl, rank, channel))
+				continue;
+
+			/** TODO: Differs for LPDDR **/
+			uint16_t mr1reg = ctrl->mr1[channel][rank / 2];
+			mr1reg &= ~MR1_QOFF_ENABLE;
+			mr1reg |= MR1_WL_ENABLE;
+			if (is_hsw_ult()) {
+				mr1reg &= ~RTTNOM_MASK;
+				mr1reg |= encode_ddr3_rttnom(120);
+			} else if (ctrl->dpc[channel] == 2) {
+				mr1reg &= ~RTTNOM_MASK;
+				mr1reg |= encode_ddr3_rttnom(60);
+			}
+			reut_issue_mrs(ctrl, channel, BIT(rank), 1, mr1reg);
+
+			/* Assert ODT for myself */
+			uint8_t odt_matrix = BIT(rank);
+			if (ctrl->dpc[channel] == 2) {
+				/* Assert ODT for non-target DIMM */
+				const uint8_t other_dimm = ((rank + 2) / 2) & 1;
+				odt_matrix |= BIT(2 * other_dimm);
+			}
+
+			union reut_misc_odt_ctrl_reg reut_misc_odt_ctrl = {
+				.raw = 0,
+			};
+			if (ctrl->lpddr) {
+				/* Only one ODT pin for ULT */
+				reut_misc_odt_ctrl.odt_on       = 1;
+				reut_misc_odt_ctrl.odt_override = 1;
+			} else if (!is_hsw_ult()) {
+				reut_misc_odt_ctrl.odt_on       = odt_matrix;
+				reut_misc_odt_ctrl.odt_override = 0xf;
+			}
+			mchbar_write32(REUT_ch_MISC_ODT_CTRL(channel), reut_misc_odt_ctrl.raw);
+		}
+		for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
+			if (!rank_in_ch(ctrl, rank, channel))
+				continue;
+
+			/*
+			 * Enable write leveling mode in DDR and propagate delay
+			 * values (without a write command). Stay in WL mode.
+			 */
+			union ddr_data_control_0_reg data_control_0 = {
+				.raw = ctrl->dq_control_0[channel],
+			};
+			data_control_0.wl_training_mode = 1;
+			data_control_0.tx_pi_on         = 1;
+			data_control_0.read_rf_rd       = 0;
+			data_control_0.read_rf_wr       = 1;
+			data_control_0.read_rf_rank     = rank;
+			mchbar_write32(DDR_DATA_ch_CONTROL_0(channel), data_control_0.raw);
+		}
+		printk(BIOS_DEBUG, "\nRank %u\n", rank);
+		printk(JWRL_PLOT, "Channel\t");
+		for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
+			if (!rank_in_ch(ctrl, rank, channel))
+				continue;
+
+			printk(JWRL_PLOT, "%u", channel);
+			if (channel > 0)
+				continue;
+
+			for (uint8_t byte = 0; byte < ctrl->lanes; byte++)
+				printk(JWRL_PLOT, "\t");
+		}
+		printk(JWRL_PLOT, "\nByte");
+		for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
+			if (!rank_in_ch(ctrl, rank, channel))
+				continue;
+
+			for (uint8_t byte = 0; byte < ctrl->lanes; byte++)
+				printk(JWRL_PLOT, "\t%u", byte);
+		}
+		printk(JWRL_PLOT, "\nWlDelay");
+		for (uint16_t wl_delay = wl_start; wl_delay < wl_stop; wl_delay += wl_step) {
+			printk(JWRL_PLOT, "\n %3u:", wl_delay);
+			for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
+				if (!rank_in_ch(ctrl, rank, channel))
+					continue;
+
+				for (uint8_t byte = 0; byte < ctrl->lanes; byte++) {
+					update_txt(ctrl, channel, rank, byte, TXT_TXDQS,
+						wl_delay);
+				}
+			}
+			/* Wait for the first burst to finish */
+			if (wl_delay == wl_start)
+				udelay(wait_time_us);
+
+			io_reset();
+			udelay(wait_time_us);
+			for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
+				if (!rank_in_ch(ctrl, rank, channel))
+					continue;
+
+				for (uint8_t byte = 0; byte < ctrl->lanes; byte++) {
+					const uint32_t feedback =
+						get_data_train_feedback(channel, byte);
+					const bool pass = (feedback & 0x1ff) >= 16;
+					printk(JWRL_PLOT, "\t%c%u", pass ? '.' : '#', feedback);
+					phase_record_pass(
+						&region_data[channel][byte],
+						pass,
+						wl_delay,
+						wl_start,
+						wl_step);
+				}
+			}
+		}
+		printk(JWRL_PLOT, "\n");
+		printk(BIOS_DEBUG, "\n\tInitSt\tInitEn\tCurrSt\tCurrEn\tLargSt\tLargEn\n");
+		for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
+			if (!rank_in_ch(ctrl, rank, channel))
+				continue;
+
+			printk(BIOS_DEBUG, "C%u\n", channel);
+			for (uint8_t byte = 0; byte < ctrl->lanes; byte++) {
+				struct phase_train_data *data = &region_data[channel][byte];
+
+				phase_append_initial_to_current(data, wl_start, wl_step);
+				printk(BIOS_DEBUG, "   B%u:\t%d\t%d\t%d\t%d\t%d\t%d\n",
+					byte,
+					data->initial.start,
+					data->initial.end,
+					data->current.start,
+					data->current.end,
+					data->largest.start,
+					data->largest.end);
+			}
+		}
+
+		/*
+		 * Clean up after test. Very coarsely adjust for
+		 * any cycle errors. Program values for TxDQS.
+		 */
+		for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
+			if (!rank_in_ch(ctrl, rank, channel))
+				continue;
+
+			/* Clear ODT before MRS (JEDEC spec) */
+			mchbar_write32(REUT_ch_MISC_ODT_CTRL(channel), 0);
+
+			/** TODO: Differs for LPDDR **/
+			const uint16_t mr1reg = ctrl->mr1[channel][rank / 2] | MR1_QOFF_ENABLE;
+			reut_issue_mrs(ctrl, channel, BIT(rank), 1, mr1reg);
+
+			printk(BIOS_DEBUG, "\nC%u.R%u:  LftEdge Width\n", channel, rank);
+			const bool rank_x16 = ctrl->dimms[channel][rank / 2].data.width == 16;
+			for (uint8_t byte = 0; byte < ctrl->lanes; byte++) {
+				struct phase_train_data *data = &region_data[channel][byte];
+				const int32_t lwidth = range_width(data->largest);
+				int32_t tx_start = data->largest.start;
+				printk(BIOS_DEBUG, "  B%u:   %d\t%d\n", byte, tx_start, lwidth);
+				status = verify_wl_width(lwidth);
+				if (status) {
+					printk(BIOS_ERR,
+						"WrLevel problems on channel %u, byte %u\n",
+						channel, byte);
+					goto clean_up;
+				}
+
+				/* Align byte pairs if DIMM is x16 */
+				if (rank_x16 && (byte & 1)) {
+					const struct phase_train_data *const ref_data =
+							&region_data[channel][byte - 1];
+
+					if (tx_start > ref_data->largest.start + 64)
+						tx_start -= 128;
+
+					if (tx_start < ref_data->largest.start - 64)
+						tx_start += 128;
+				}
+
+				/* Fix for b4618067 - need to add 1 QCLK to DQS PI */
+				if (is_hsw_ult())
+					tx_start += 64;
+
+				assert(tx_start >= 0);
+				ctrl->txdqs[channel][rank][byte] = tx_start;
+				ctrl->tx_dq[channel][rank][byte] = tx_start + 32;
+				update_txt(ctrl, channel, rank, byte, TXT_RESTORE, 0);
+			}
+		}
+		printk(BIOS_DEBUG, "\n");
+	}
+
+clean_up:
+	for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
+		if (!does_ch_exist(ctrl, channel))
+			continue;
+
+		mchbar_write32(DDR_DATA_ch_CONTROL_0(channel), ctrl->dq_control_0[channel]);
+		for (uint8_t byte = 0; byte < ctrl->lanes; byte++) {
+			mchbar_write32(DQ_CONTROL_2(channel, byte),
+				ctrl->dq_control_2[channel][byte]);
+		}
+	}
+	if (!ctrl->lpddr)
+		ddr3_program_mr1(ctrl, 0, 0);
+
+	ctrl->restore_mrs = save_restore_mrs;
+
+	if (status)
+		return status;
+
+	/** TODO: If this step fails and dec_wrd is set, clear it and try again **/
+	return train_jedec_write_leveling_cleanup(ctrl);
+}
diff --git a/src/northbridge/intel/haswell/registers/mchbar.h b/src/northbridge/intel/haswell/registers/mchbar.h
index 6a31d3a32c..7c0b5a49de 100644
--- a/src/northbridge/intel/haswell/registers/mchbar.h
+++ b/src/northbridge/intel/haswell/registers/mchbar.h
@@ -121,6 +121,8 @@
 
 #define REUT_ch_ERR_DATA_MASK(ch)		_MCMAIN_C(0x40d8, ch)
 
+#define REUT_ch_ERR_MISC_STATUS(ch)		_MCMAIN_C(0x40e8, ch)
+
 #define REUT_ch_MISC_CKE_CTRL(ch)		_MCMAIN_C(0x4190, ch)
 #define REUT_ch_MISC_ODT_CTRL(ch)		_MCMAIN_C(0x4194, ch)
 #define REUT_ch_MISC_PAT_CADB_CTRL(ch)		_MCMAIN_C(0x4198, ch)

From a2f059c87e66111b9333e21b205726813a8604c9 Mon Sep 17 00:00:00 2001
From: Angel Pons <th3fanbus@gmail.com>
Date: Sun, 8 May 2022 14:29:05 +0200
Subject: [PATCH 0314/3886] haswell NRI: Add final raminit steps

Implement the remaining raminit steps. Although many training steps are
missing, this is enough to boot on the Asrock B85M Pro4.

Change-Id: I94f3b65f0218d4da4fda4d84592dfd91f77f8f21
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64198
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/northbridge/intel/haswell/Kconfig         |   4 +-
 .../intel/haswell/native_raminit/Makefile.mk  |   1 +
 .../haswell/native_raminit/activate_mc.c      | 388 ++++++++++++++++++
 .../haswell/native_raminit/raminit_main.c     |   5 +-
 .../haswell/native_raminit/raminit_native.c   |   5 +-
 .../haswell/native_raminit/raminit_native.h   |   2 +
 .../haswell/native_raminit/reg_structs.h      |  12 +
 .../intel/haswell/registers/mchbar.h          |   7 +
 8 files changed, 416 insertions(+), 8 deletions(-)
 create mode 100644 src/northbridge/intel/haswell/native_raminit/activate_mc.c

diff --git a/src/northbridge/intel/haswell/Kconfig b/src/northbridge/intel/haswell/Kconfig
index 35403373e7..6191cb6ccf 100644
--- a/src/northbridge/intel/haswell/Kconfig
+++ b/src/northbridge/intel/haswell/Kconfig
@@ -11,12 +11,12 @@ config NORTHBRIDGE_INTEL_HASWELL
 if NORTHBRIDGE_INTEL_HASWELL
 
 config USE_NATIVE_RAMINIT
-	bool "[NOT WORKING] Use native raminit"
+	bool "[NOT COMPLETE] Use native raminit"
 	default n
 	select HAVE_DEBUG_RAM_SETUP
 	help
 	  Select if you want to use coreboot implementation of raminit rather than
-	  MRC.bin. Currently incomplete and does not boot.
+	  MRC.bin. Currently incomplete and does not support S3 resume.
 
 config HASWELL_VBOOT_IN_BOOTBLOCK
 	depends on VBOOT
diff --git a/src/northbridge/intel/haswell/native_raminit/Makefile.mk b/src/northbridge/intel/haswell/native_raminit/Makefile.mk
index 40c2f5e014..d97da72890 100644
--- a/src/northbridge/intel/haswell/native_raminit/Makefile.mk
+++ b/src/northbridge/intel/haswell/native_raminit/Makefile.mk
@@ -1,5 +1,6 @@
 ## SPDX-License-Identifier: GPL-2.0-or-later
 
+romstage-y += activate_mc.c
 romstage-y += change_margin.c
 romstage-y += configure_mc.c
 romstage-y += ddr3.c
diff --git a/src/northbridge/intel/haswell/native_raminit/activate_mc.c b/src/northbridge/intel/haswell/native_raminit/activate_mc.c
new file mode 100644
index 0000000000..78a7ad27ef
--- /dev/null
+++ b/src/northbridge/intel/haswell/native_raminit/activate_mc.c
@@ -0,0 +1,388 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <console/console.h>
+#include <delay.h>
+#include <device/pci_ops.h>
+#include <northbridge/intel/haswell/haswell.h>
+#include <timer.h>
+#include <types.h>
+
+#include "raminit_native.h"
+
+static void update_internal_clocks_on(struct sysinfo *ctrl)
+{
+	for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
+		if (!does_ch_exist(ctrl, channel))
+			continue;
+
+		bool clocks_on = false;
+		for (uint8_t byte = 0; byte < ctrl->lanes; byte++) {
+			const union ddr_data_control_1_reg data_control_1 = {
+				.raw = ctrl->dq_control_1[channel][byte],
+			};
+			const int8_t o_on = data_control_1.odt_delay;
+			const int8_t s_on = data_control_1.sense_amp_delay;
+			const int8_t o_off = data_control_1.odt_duration;
+			const int8_t s_off = data_control_1.sense_amp_duration;
+			if (o_on + o_off >= 7 || s_on + s_off >= 7) {
+				clocks_on = true;
+				break;
+			}
+		}
+		union ddr_data_control_0_reg data_control_0 = {
+			.raw = ctrl->dq_control_0[channel],
+		};
+		data_control_0.internal_clocks_on = clocks_on;
+		ctrl->dq_control_0[channel] = data_control_0.raw;
+		mchbar_write32(DDR_DATA_ch_CONTROL_0(channel), data_control_0.raw);
+	}
+}
+
+/* Switch off unused segments of the SDLL to save power */
+static void update_sdll_length(struct sysinfo *ctrl)
+{
+	for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
+		if (!does_ch_exist(ctrl, channel))
+			continue;
+
+		for (uint8_t byte = 0; byte < ctrl->lanes; byte++) {
+			uint8_t max_pi = 0;
+			for (uint8_t rank = 0; rank < NUM_SLOTRANKS; rank++) {
+				if (!rank_in_ch(ctrl, rank, channel))
+					continue;
+
+				const uint8_t rx_dqs_p = ctrl->rxdqsp[channel][rank][byte];
+				const uint8_t rx_dqs_n = ctrl->rxdqsn[channel][rank][byte];
+				max_pi = MAX(max_pi, MAX(rx_dqs_p, rx_dqs_n));
+			}
+			/* Update SDLL length for power savings */
+			union ddr_data_control_1_reg data_control_1 = {
+				.raw = ctrl->dq_control_1[channel][byte],
+			};
+			/* Calculate which segments to turn off */
+			data_control_1.sdll_segment_disable = (7 - (max_pi >> 3)) & ~1;
+			ctrl->dq_control_1[channel][byte] = data_control_1.raw;
+			mchbar_write32(DQ_CONTROL_1(channel, byte), data_control_1.raw);
+		}
+	}
+}
+
+static void set_rx_clk_stg_num(struct sysinfo *ctrl, const uint8_t channel)
+{
+	const uint8_t rcven_drift = ctrl->lpddr ? DIV_ROUND_UP(tDQSCK_DRIFT, ctrl->qclkps) : 1;
+	uint8_t max_rcven = 0;
+	for (uint8_t rank = 0; rank < NUM_SLOTRANKS; rank++) {
+		if (!rank_in_ch(ctrl, rank, channel))
+			continue;
+
+		for (uint8_t byte = 0; byte < ctrl->lanes; byte++)
+			max_rcven = MAX(max_rcven, ctrl->rcven[channel][rank][byte] / 64);
+	}
+	const union ddr_data_control_1_reg ddr_data_control_1 = {
+		.raw = ctrl->dq_control_1[channel][0],
+	};
+	const bool lpddr_long_odt = ddr_data_control_1.lpddr_long_odt_en;
+	const uint8_t rcven_turnoff = max_rcven + 18 + 2 * rcven_drift + lpddr_long_odt;
+	const union ddr_data_control_0_reg ddr_data_control_0 = {
+		.raw = ctrl->dq_control_0[channel],
+	};
+	for (uint8_t byte = 0; byte < ctrl->lanes; byte++) {
+		union ddr_data_control_2_reg ddr_data_control_2 = {
+			.raw = ctrl->dq_control_2[channel][byte],
+		};
+		if (ddr_data_control_0.odt_samp_extend_en) {
+			if (ddr_data_control_2.rx_clk_stg_num < rcven_turnoff)
+				ddr_data_control_2.rx_clk_stg_num = rcven_turnoff;
+		} else {
+			const int8_t o_on = ddr_data_control_1.odt_delay;
+			const int8_t o_off = ddr_data_control_1.odt_duration;
+			ddr_data_control_2.rx_clk_stg_num = MAX(17, o_on + o_off + 14);
+		}
+		ctrl->dq_control_2[channel][byte] = ddr_data_control_2.raw;
+		mchbar_write32(DQ_CONTROL_2(channel, byte), ddr_data_control_2.raw);
+	}
+}
+
+#define SELF_REFRESH_IDLE_COUNT 0x200
+
+static void enter_sr(void)
+{
+	mchbar_write32(PM_SREF_CONFIG, SELF_REFRESH_IDLE_COUNT | BIT(16));
+	udelay(1);
+}
+
+enum power_down_mode {
+	PDM_NO_PD	= 0,
+	PDM_APD		= 1,
+	PDM_PPD		= 2,
+	PDM_PPD_DLL_OFF	= 6,
+};
+
+static void power_down_config(struct sysinfo *ctrl)
+{
+	const enum power_down_mode pd_mode = ctrl->lpddr ? PDM_PPD : PDM_PPD_DLL_OFF;
+	mchbar_write32(PM_PDWN_CONFIG, pd_mode << 12 | 0x40);
+}
+
+static void train_power_modes_post(struct sysinfo *ctrl)
+{
+	for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
+		if (!does_ch_exist(ctrl, channel))
+			continue;
+
+		/* Adjust tCPDED and tPRPDEN */
+		if (ctrl->mem_clock_mhz >= 933)
+			ctrl->tc_bankrank_d[channel].tCPDED = 2;
+
+		if (ctrl->mem_clock_mhz >= 1066)
+			ctrl->tc_bankrank_d[channel].tPRPDEN = 2;
+
+		mchbar_write32(TC_BANK_RANK_D_ch(channel), ctrl->tc_bankrank_d[channel].raw);
+	}
+	power_down_config(ctrl);
+	mchbar_write32(MCDECS_CBIT, BIT(30));	/* dis_msg_clk_gate */
+}
+
+static uint8_t compute_burst_end_odt_delay(const struct sysinfo *const ctrl)
+{
+	/* Must be disabled for LPDDR */
+	if (ctrl->lpddr)
+		return 0;
+
+	const uint8_t beod = MIN(7, DIV_ROUND_CLOSEST(14300 * 20 / 100, ctrl->qclkps));
+	if (beod < 3)
+		return 0;
+
+	if (beod < 4)
+		return 4;
+
+	return beod;
+}
+
+static void program_burst_end_odt_delay(struct sysinfo *ctrl)
+{
+	/* Program burst_end_odt_delay - it should be zero during training steps */
+	const uint8_t beod = compute_burst_end_odt_delay(ctrl);
+	for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
+		if (!does_ch_exist(ctrl, channel))
+			continue;
+
+		for (uint8_t byte = 0; byte < ctrl->lanes; byte++) {
+			union ddr_data_control_1_reg ddr_data_control_1 = {
+				.raw = ctrl->dq_control_1[channel][byte],
+			};
+			ddr_data_control_1.burst_end_odt_delay = beod;
+			ctrl->dq_control_1[channel][byte] = ddr_data_control_1.raw;
+			mchbar_write32(DQ_CONTROL_1(channel, byte), ddr_data_control_1.raw);
+		}
+	}
+}
+
+/*
+ * Return a random value to use for scrambler seeds. Try to use RDRAND
+ * first and fall back to hardcoded values if RDRAND does not succeed.
+ */
+static uint16_t get_random_number(const uint8_t channel)
+{
+	/* The RDRAND instruction is only available 100k cycles after reset */
+	for (size_t i = 0; i < 100000; i++) {
+		uint32_t status;
+		uint32_t random;
+		/** TODO: Clean up asm **/
+		__asm__ __volatile__(
+			"\n\t .byte 0x0F, 0xC7, 0xF0"
+			"\n\t movl %%eax, %0"
+			"\n\t pushf"
+			"\n\t pop %%eax"
+			"\n\t movl %%eax, %1"
+			: "=m"(random),
+			  "=m"(status)
+			: /* No inputs */
+			: "eax", "cc");
+
+		/* Only consider non-zero random values as valid */
+		if (status & 1 && random)
+			return random;
+	}
+
+	/* https://xkcd.com/221 */
+	if (channel)
+		return 0x28f4;
+	else
+		return 0x893e;
+}
+
+/* Work around "error: 'typeof' applied to a bit-field" */
+static inline uint32_t max(const uint32_t a, const uint32_t b)
+{
+	return MAX(a, b);
+}
+
+enum raminit_status activate_mc(struct sysinfo *ctrl)
+{
+	const bool enable_scrambling = true;
+	const bool enable_cmd_tristate = true;
+	for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
+		if (!does_ch_exist(ctrl, channel))
+			continue;
+
+		if (enable_scrambling && ctrl->stepping < STEPPING_C0) {
+			/* Make sure tRDRD_(sr, dr, dd) are at least 6 for scrambler W/A */
+			union tc_bank_rank_a_reg tc_bank_rank_a = {
+				.raw = mchbar_read32(TC_BANK_RANK_A_ch(channel)),
+			};
+			tc_bank_rank_a.tRDRD_sr = max(tc_bank_rank_a.tRDRD_sr, 6);
+			tc_bank_rank_a.tRDRD_dr = max(tc_bank_rank_a.tRDRD_dr, 6);
+			tc_bank_rank_a.tRDRD_dd = max(tc_bank_rank_a.tRDRD_dd, 6);
+			mchbar_write32(TC_BANK_RANK_A_ch(channel), tc_bank_rank_a.raw);
+		}
+		if (enable_scrambling) {
+			const union ddr_scramble_reg ddr_scramble = {
+				.scram_key = get_random_number(channel),
+				.scram_en  = 1,
+			};
+			mchbar_write32(DDR_SCRAMBLE_ch(channel), ddr_scramble.raw);
+		}
+		if (ctrl->tCMD == 1) {
+			/* If we are in 1N mode, enable and set command rate limit to 3 */
+			union mcmain_command_rate_limit_reg cmd_rate_limit = {
+				.raw = mchbar_read32(COMMAND_RATE_LIMIT_ch(channel)),
+			};
+			cmd_rate_limit.enable_cmd_limit = 1;
+			cmd_rate_limit.cmd_rate_limit   = 3;
+			mchbar_write32(COMMAND_RATE_LIMIT_ch(channel), cmd_rate_limit.raw);
+		}
+		if (enable_cmd_tristate) {
+			/* Enable command tri-state at the end of training */
+			union tc_bank_rank_a_reg tc_bank_rank_a = {
+				.raw = mchbar_read32(TC_BANK_RANK_A_ch(channel)),
+			};
+			tc_bank_rank_a.cmd_3st_dis = 0;
+			mchbar_write32(TC_BANK_RANK_A_ch(channel), tc_bank_rank_a.raw);
+		}
+		/* Set MC to normal mode and clean the ODT and CKE */
+		mchbar_write32(REUT_ch_SEQ_CFG(channel), REUT_MODE_NOP << 12);
+		/* Set again the rank occupancy */
+		mchbar_write8(MC_INIT_STATE_ch(channel), ctrl->rankmap[channel]);
+		if (ctrl->is_ecc) {
+			/* Enable ECC I/O and logic */
+			union mad_dimm_reg mad_dimm = {
+				.raw = mchbar_read32(MAD_DIMM(channel)),
+			};
+			mad_dimm.ecc_mode = 3;
+			mchbar_write32(MAD_DIMM(channel), mad_dimm.raw);
+		}
+	}
+
+	if (!is_hsw_ult())
+		update_internal_clocks_on(ctrl);
+
+	update_sdll_length(ctrl);
+
+	program_burst_end_odt_delay(ctrl);
+
+	if (is_hsw_ult()) {
+		for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
+			if (!does_ch_exist(ctrl, channel))
+				continue;
+
+			set_rx_clk_stg_num(ctrl, channel);
+		}
+		/** TODO: Program DDRPL_CR_DDR_TX_DELAY if Memory Trace is enabled **/
+	}
+
+	/* Enable periodic COMP */
+	mchbar_write32(M_COMP, (union pcu_comp_reg) {
+		.comp_interval = COMP_INT,
+	}.raw);
+
+	/* Enable the power mode before PCU starts working */
+	train_power_modes_post(ctrl);
+
+	/* Set idle timer and self refresh enable bits */
+	enter_sr();
+
+	/** FIXME: Do not hardcode power weights and RAPL settings **/
+	mchbar_write32(0x5888, 0x00000d0d);
+	mchbar_write32(0x5884, 0x00000004);	/* 58.2 pJ */
+
+	mchbar_write32(0x58e0, 0);
+	mchbar_write32(0x58e4, 0);
+
+	mchbar_write32(0x5890, 0xffff);
+	mchbar_write32(0x5894, 0xffff);
+	mchbar_write32(0x5898, 0xffff);
+	mchbar_write32(0x589c, 0xffff);
+	mchbar_write32(0x58d0, 0xffff);
+	mchbar_write32(0x58d4, 0xffff);
+	mchbar_write32(0x58d8, 0xffff);
+	mchbar_write32(0x58dc, 0xffff);
+
+	/* Overwrite thermal parameters */
+	for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
+		mchbar_write32(_MCMAIN_C(0x42ec, channel), 0x0000000f);
+		mchbar_write32(_MCMAIN_C(0x42f0, channel), 0x00000009);
+		mchbar_write32(_MCMAIN_C(0x42f4, channel), 0x00000093);
+		mchbar_write32(_MCMAIN_C(0x42f8, channel), 0x00000087);
+		mchbar_write32(_MCMAIN_C(0x42fc, channel), 0x000000de);
+
+		/** TODO: Differs for LPDDR **/
+		mchbar_write32(PM_THRT_CKE_MIN_ch(channel), 0x30);
+	}
+	mchbar_write32(PCU_DDR_PTM_CTL, 0x40);
+	return RAMINIT_STATUS_SUCCESS;
+}
+
+static void mc_lockdown(void)
+{
+	/* Lock memory controller registers */
+	mchbar_write32(MC_LOCK, 0x8f);
+
+	/* MPCOHTRK_GDXC_OCLA_ADDRESS_HI_LOCK is set when programming the memory map */
+
+	/* Lock memory map registers */
+	pci_or_config16(HOST_BRIDGE, GGC,         1 <<  0);
+	pci_or_config32(HOST_BRIDGE, DPR,         1 <<  0);
+	pci_or_config32(HOST_BRIDGE, MESEG_LIMIT, 1 << 10);
+	pci_or_config32(HOST_BRIDGE, REMAPBASE,   1 <<  0);
+	pci_or_config32(HOST_BRIDGE, REMAPLIMIT,  1 <<  0);
+	pci_or_config32(HOST_BRIDGE, TOM,         1 <<  0);
+	pci_or_config32(HOST_BRIDGE, TOUUD,       1 <<  0);
+	pci_or_config32(HOST_BRIDGE, BDSM,        1 <<  0);
+	pci_or_config32(HOST_BRIDGE, BGSM,        1 <<  0);
+	pci_or_config32(HOST_BRIDGE, TOLUD,       1 <<  0);
+}
+
+enum raminit_status raminit_done(struct sysinfo *ctrl)
+{
+	union mc_init_state_g_reg mc_init_state_g = {
+		.raw = mchbar_read32(MC_INIT_STATE_G),
+	};
+	mc_init_state_g.refresh_enable = 1;
+	mc_init_state_g.pu_mrc_done    = 1;
+	mc_init_state_g.mrc_done       = 1;
+	mchbar_write32(MC_INIT_STATE_G, mc_init_state_g.raw);
+
+	/* Lock the memory controller to enable normal operation */
+	mc_lockdown();
+
+	/* Poll for mc_init_done_ack to make sure memory initialization is complete */
+	printk(BIOS_DEBUG, "Waiting for mc_init_done acknowledgement... ");
+
+	struct stopwatch timer;
+	stopwatch_init_msecs_expire(&timer, 2000);
+	do {
+		mc_init_state_g.raw = mchbar_read32(MC_INIT_STATE_G);
+
+		/* DRAM will NOT work without the acknowledgement. There is no hope. */
+		if (stopwatch_expired(&timer))
+			die("\nTimed out waiting for mc_init_done acknowledgement\n");
+
+	} while (mc_init_state_g.mc_init_done_ack == 0);
+	printk(BIOS_DEBUG, "DONE!\n");
+
+	/* Provide some data for the graphics driver. Yes, it's hardcoded. */
+	mchbar_write32(SSKPD + 0, 0x05a2404f);
+	mchbar_write32(SSKPD + 4, 0x140000a0);
+	return RAMINIT_STATUS_SUCCESS;
+}
diff --git a/src/northbridge/intel/haswell/native_raminit/raminit_main.c b/src/northbridge/intel/haswell/native_raminit/raminit_main.c
index b947ecbd46..2073b54782 100644
--- a/src/northbridge/intel/haswell/native_raminit/raminit_main.c
+++ b/src/northbridge/intel/haswell/native_raminit/raminit_main.c
@@ -64,6 +64,8 @@ static const struct task_entry cold_boot[] = {
 	{ train_receive_enable,                                   true, "RCVET",      },
 	{ train_read_mpr,                                         true, "RDMPRT",     },
 	{ train_jedec_write_leveling,                             true, "JWRL",       },
+	{ activate_mc,                                            true, "ACTIVATE",   },
+	{ raminit_done,                                           true, "RAMINITEND", },
 };
 
 /* Return a generic stepping value to make stepping checks simpler */
@@ -144,7 +146,4 @@ void raminit_main(const enum raminit_boot_mode bootmode)
 
 	if (status != RAMINIT_STATUS_SUCCESS)
 		die("Memory initialization was met with utmost failure and misery\n");
-
-	/** TODO: Implement the required magic **/
-	die("NATIVE RAMINIT: More Magic (tm) required.\n");
 }
diff --git a/src/northbridge/intel/haswell/native_raminit/raminit_native.c b/src/northbridge/intel/haswell/native_raminit/raminit_native.c
index 2fed93de5b..5f7ceec222 100644
--- a/src/northbridge/intel/haswell/native_raminit/raminit_native.c
+++ b/src/northbridge/intel/haswell/native_raminit/raminit_native.c
@@ -199,8 +199,6 @@ void perform_raminit(const int s3resume)
 		else
 			me_status = ME_INIT_STATUS_SUCCESS;
 
-		/** TODO: Remove this once raminit is implemented **/
-		me_status = ME_INIT_STATUS_ERROR;
 		intel_early_me_init_done(me_status);
 	}
 
@@ -214,7 +212,8 @@ void perform_raminit(const int s3resume)
 	}
 
 	/* Save training data on non-S3 resumes */
-	if (!s3resume)
+	/** TODO: Enable this once training data is populated **/
+	if (0 && !s3resume)
 		save_mrc_data(&md);
 
 	/** TODO: setup_sdram_meminfo **/
diff --git a/src/northbridge/intel/haswell/native_raminit/raminit_native.h b/src/northbridge/intel/haswell/native_raminit/raminit_native.h
index d6b11b9d3c..a0a913f926 100644
--- a/src/northbridge/intel/haswell/native_raminit/raminit_native.h
+++ b/src/northbridge/intel/haswell/native_raminit/raminit_native.h
@@ -448,6 +448,8 @@ enum raminit_status do_jedec_init(struct sysinfo *ctrl);
 enum raminit_status train_receive_enable(struct sysinfo *ctrl);
 enum raminit_status train_read_mpr(struct sysinfo *ctrl);
 enum raminit_status train_jedec_write_leveling(struct sysinfo *ctrl);
+enum raminit_status activate_mc(struct sysinfo *ctrl);
+enum raminit_status raminit_done(struct sysinfo *ctrl);
 
 void configure_timings(struct sysinfo *ctrl);
 void configure_refresh(struct sysinfo *ctrl);
diff --git a/src/northbridge/intel/haswell/native_raminit/reg_structs.h b/src/northbridge/intel/haswell/native_raminit/reg_structs.h
index a0e36ed082..0d9aaa1f7c 100644
--- a/src/northbridge/intel/haswell/native_raminit/reg_structs.h
+++ b/src/northbridge/intel/haswell/native_raminit/reg_structs.h
@@ -294,6 +294,18 @@ union ddr_cke_ctl_controls_reg {
 	uint32_t raw;
 };
 
+union ddr_scramble_reg {
+	struct __packed {
+		uint32_t scram_en    :  1; // Bits  0:0
+		uint32_t scram_key   : 16; // Bits 16:1
+		uint32_t clk_gate_ab :  2; // Bits 18:17
+		uint32_t clk_gate_c  :  2; // Bits 20:19
+		uint32_t en_dbi_ab   :  1; // Bits 21:21
+		uint32_t             : 10; // Bits 31:17
+	};
+	uint32_t raw;
+};
+
 union ddr_scram_misc_control_reg {
 	struct __packed {
 		uint32_t wl_wake_cycles       :  2; // Bits  1:0
diff --git a/src/northbridge/intel/haswell/registers/mchbar.h b/src/northbridge/intel/haswell/registers/mchbar.h
index 7c0b5a49de..49a215aa71 100644
--- a/src/northbridge/intel/haswell/registers/mchbar.h
+++ b/src/northbridge/intel/haswell/registers/mchbar.h
@@ -20,6 +20,7 @@
 
 #define DDR_DATA_TRAIN_FEEDBACK(ch, byte)	_DDRIO_C_R_B(0x0054, ch, 0, byte)
 
+#define DQ_CONTROL_1(ch, byte)			_DDRIO_C_R_B(0x0060, ch, 0, byte)
 #define DQ_CONTROL_2(ch, byte)			_DDRIO_C_R_B(0x0064, ch, 0, byte)
 #define DDR_DATA_OFFSET_TRAIN_ch_b(ch, byte)	_DDRIO_C_R_B(0x0070, ch, 0, byte)
 #define DQ_CONTROL_0(ch, byte)			_DDRIO_C_R_B(0x0074, ch, 0, byte)
@@ -147,6 +148,8 @@
 #define QCLK_ch_LDAT_SDAT(ch)			_MCMAIN_C(0x42d4, ch)
 #define QCLK_ch_LDAT_DATA_IN_x(ch, x)		_MCMAIN_C_X(0x42dc, ch, x) /* x in 0 .. 1 */
 
+#define PM_THRT_CKE_MIN_ch(ch)			_MCMAIN_C(0x4328, ch)
+
 #define REUT_GLOBAL_CTL				0x4800
 #define REUT_GLOBAL_ERR				0x4804
 
@@ -175,6 +178,8 @@
 
 #define MCSCHEDS_DFT_MISC	0x4c30
 
+#define PM_PDWN_CONFIG		0x4cb0
+
 #define REUT_ERR_DATA_STATUS	0x4ce0
 
 #define REUT_MISC_CKE_CTRL	0x4d90
@@ -186,8 +191,10 @@
 #define MAD_CHNL		0x5000 /* Address Decoder Channel Configuration */
 #define MAD_DIMM(ch)		(0x5004 + (ch) * 4)
 #define MAD_ZR			0x5014
+#define MCDECS_CBIT		0x501c
 #define MC_INIT_STATE_G		0x5030
 #define MRC_REVISION		0x5034 /* MRC Revision */
+#define PM_SREF_CONFIG		0x5060
 
 #define RCOMP_TIMER		0x5084
 

From b6d3af1361681d91d157ba42cfe25232a267aa0b Mon Sep 17 00:00:00 2001
From: Angel Pons <th3fanbus@gmail.com>
Date: Sat, 13 Apr 2024 01:16:30 +0200
Subject: [PATCH 0315/3886] haswell NRI: Implement fast boot path

When the memory configuration hasn't changed, there is no need to do
full memory training. Instead, boot firmware can use saved training
data to reinitialise the memory controller and memory.

Unlike native RAM init for other platforms, Haswell does not save the
main structure (the "mighty ctrl" struct) to flash. Instead, separate
structures define the data to be saved, which can be smaller than the
main structure.

This makes S3 suspend and resume work: RAM contents MUST be preserved
for a S3 resume to succeed, but RAM training destroys RAM contents.

Change-Id: I06f6cd39ceecdca104fae89159f28e85cf7ff4e6
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81897
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
---
 .../intel/haswell/native_raminit/Makefile.mk  |   1 +
 .../haswell/native_raminit/activate_mc.c      |  17 +
 .../intel/haswell/native_raminit/ddr3.c       |  41 ++
 .../haswell/native_raminit/raminit_main.c     |  34 +-
 .../haswell/native_raminit/raminit_native.c   |  30 +-
 .../haswell/native_raminit/raminit_native.h   |  18 +
 .../haswell/native_raminit/save_restore.c     | 387 ++++++++++++++++++
 7 files changed, 504 insertions(+), 24 deletions(-)
 create mode 100644 src/northbridge/intel/haswell/native_raminit/save_restore.c

diff --git a/src/northbridge/intel/haswell/native_raminit/Makefile.mk b/src/northbridge/intel/haswell/native_raminit/Makefile.mk
index d97da72890..8fdd17c542 100644
--- a/src/northbridge/intel/haswell/native_raminit/Makefile.mk
+++ b/src/northbridge/intel/haswell/native_raminit/Makefile.mk
@@ -13,6 +13,7 @@ romstage-y += raminit_main.c
 romstage-y += raminit_native.c
 romstage-y += ranges.c
 romstage-y += reut.c
+romstage-y += save_restore.c
 romstage-y += setup_wdb.c
 romstage-y += spd_bitmunching.c
 romstage-y += testing_io.c
diff --git a/src/northbridge/intel/haswell/native_raminit/activate_mc.c b/src/northbridge/intel/haswell/native_raminit/activate_mc.c
index 78a7ad27ef..0b3eb917da 100644
--- a/src/northbridge/intel/haswell/native_raminit/activate_mc.c
+++ b/src/northbridge/intel/haswell/native_raminit/activate_mc.c
@@ -333,6 +333,23 @@ enum raminit_status activate_mc(struct sysinfo *ctrl)
 	return RAMINIT_STATUS_SUCCESS;
 }
 
+enum raminit_status normal_state(struct sysinfo *ctrl)
+{
+	/* Enable periodic COMP */
+	mchbar_write32(M_COMP, (union pcu_comp_reg) {
+		.comp_interval = COMP_INT,
+	}.raw);
+	for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
+		if (!does_ch_exist(ctrl, channel))
+			continue;
+
+		/* Set MC to normal mode and clean the ODT and CKE */
+		mchbar_write32(REUT_ch_SEQ_CFG(channel), REUT_MODE_NOP << 12);
+	}
+	power_down_config(ctrl);
+	return RAMINIT_STATUS_SUCCESS;
+}
+
 static void mc_lockdown(void)
 {
 	/* Lock memory controller registers */
diff --git a/src/northbridge/intel/haswell/native_raminit/ddr3.c b/src/northbridge/intel/haswell/native_raminit/ddr3.c
index 6ddb11488b..9b6368edb1 100644
--- a/src/northbridge/intel/haswell/native_raminit/ddr3.c
+++ b/src/northbridge/intel/haswell/native_raminit/ddr3.c
@@ -2,6 +2,7 @@
 
 #include <assert.h>
 #include <console/console.h>
+#include <delay.h>
 #include <northbridge/intel/haswell/haswell.h>
 #include <types.h>
 
@@ -215,3 +216,43 @@ enum raminit_status ddr3_jedec_init(struct sysinfo *ctrl)
 	ddr3_program_mr0(ctrl, 1);
 	return reut_issue_zq(ctrl, ctrl->chanmap, ZQ_INIT);
 }
+
+enum raminit_status exit_selfrefresh(struct sysinfo *ctrl)
+{
+	for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
+		if (!does_ch_exist(ctrl, channel))
+			continue;
+
+		/* Fields in ctrl aren't populated on a warm boot */
+		union ddr_data_control_0_reg data_control_0 = {
+			.raw = mchbar_read32(DQ_CONTROL_0(channel, 0)),
+		};
+		data_control_0.read_rf_rd = 1;
+		for (uint8_t rank = 0; rank < NUM_SLOTRANKS; rank++) {
+			if (!rank_in_ch(ctrl, rank, channel))
+				continue;
+
+			data_control_0.read_rf_rank = rank;
+			mchbar_write32(DDR_DATA_ch_CONTROL_0(channel), data_control_0.raw);
+		}
+	}
+
+	/* Time needed to stabilize the DCLK (~6 us) */
+	udelay(6);
+
+	/* Pull the DIMMs out of self refresh by asserting CKE high */
+	for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
+		const union reut_misc_cke_ctrl_reg reut_misc_cke_ctrl = {
+			.cke_on = ctrl->rankmap[channel],
+		};
+		mchbar_write32(REUT_ch_MISC_CKE_CTRL(channel), reut_misc_cke_ctrl.raw);
+	}
+	mchbar_write32(REUT_MISC_ODT_CTRL, 0);
+
+	const enum raminit_status status = reut_issue_zq(ctrl, ctrl->chanmap, ZQ_LONG);
+	if (status) {
+		/* ZQCL errors don't seem to be a fatal problem here */
+		printk(BIOS_ERR, "ZQ Long failed during S3 resume or warm reset flow\n");
+	}
+	return RAMINIT_STATUS_SUCCESS;
+}
diff --git a/src/northbridge/intel/haswell/native_raminit/raminit_main.c b/src/northbridge/intel/haswell/native_raminit/raminit_main.c
index 2073b54782..b6f3144529 100644
--- a/src/northbridge/intel/haswell/native_raminit/raminit_main.c
+++ b/src/northbridge/intel/haswell/native_raminit/raminit_main.c
@@ -65,6 +65,22 @@ static const struct task_entry cold_boot[] = {
 	{ train_read_mpr,                                         true, "RDMPRT",     },
 	{ train_jedec_write_leveling,                             true, "JWRL",       },
 	{ activate_mc,                                            true, "ACTIVATE",   },
+	{ save_training_values,                                   true, "SAVE_TRAIN", },
+	{ save_non_training,                                      true, "SAVE_NONT",  },
+	{ raminit_done,                                           true, "RAMINITEND", },
+};
+
+static const struct task_entry fast_boot[] = {
+	{ collect_spd_info,                                       true, "PROCSPD",    },
+	{ restore_non_training,                                   true, "RST_NONT",   },
+	{ initialise_mpll,                                        true, "INITMPLL",   },
+	{ configure_mc,                                           true, "CONFMC",     },
+	{ configure_memory_map,                                   true, "MEMMAP",     },
+	{ do_jedec_init,                                          true, "JEDECINIT",  },
+	{ pre_training,                                           true, "PRETRAIN",   },
+	{ restore_training_values,                                true, "RST_TRAIN",  },
+	{ exit_selfrefresh,                                       true, "EXIT_SR",    },
+	{ normal_state,                                           true, "NORMALMODE", },
 	{ raminit_done,                                           true, "RAMINITEND", },
 };
 
@@ -103,11 +119,11 @@ static void initialize_ctrl(struct sysinfo *ctrl)
 	ctrl->bootmode = bootmode;
 }
 
-static enum raminit_status try_raminit(struct sysinfo *ctrl)
+static enum raminit_status try_raminit(
+	struct sysinfo *ctrl,
+	const struct task_entry *const schedule,
+	const size_t length)
 {
-	const struct task_entry *const schedule = cold_boot;
-	const size_t length = ARRAY_SIZE(cold_boot);
-
 	enum raminit_status status = RAMINIT_STATUS_UNSPECIFIED_ERROR;
 
 	for (size_t i = 0; i < length; i++) {
@@ -141,8 +157,16 @@ void raminit_main(const enum raminit_boot_mode bootmode)
 	mighty_ctrl.bootmode = bootmode;
 	initialize_ctrl(&mighty_ctrl);
 
+	enum raminit_status status = RAMINIT_STATUS_UNSPECIFIED_ERROR;
+
+	if (bootmode != BOOTMODE_COLD) {
+		status = try_raminit(&mighty_ctrl, fast_boot, ARRAY_SIZE(fast_boot));
+		if (status == RAMINIT_STATUS_SUCCESS)
+			return;
+	}
+
 	/** TODO: Try more than once **/
-	enum raminit_status status = try_raminit(&mighty_ctrl);
+	status = try_raminit(&mighty_ctrl, cold_boot, ARRAY_SIZE(cold_boot));
 
 	if (status != RAMINIT_STATUS_SUCCESS)
 		die("Memory initialization was met with utmost failure and misery\n");
diff --git a/src/northbridge/intel/haswell/native_raminit/raminit_native.c b/src/northbridge/intel/haswell/native_raminit/raminit_native.c
index 5f7ceec222..3ad8ce29e7 100644
--- a/src/northbridge/intel/haswell/native_raminit/raminit_native.c
+++ b/src/northbridge/intel/haswell/native_raminit/raminit_native.c
@@ -54,23 +54,17 @@ static bool early_init_native(enum raminit_boot_mode bootmode)
 	return cpu_replaced;
 }
 
-#define MRC_CACHE_VERSION 1
-
-struct mrc_data {
-	const void *buffer;
-	size_t buffer_len;
-};
-
-static void save_mrc_data(struct mrc_data *md)
+static void save_mrc_data(void)
 {
-	mrc_cache_stash_data(MRC_TRAINING_DATA, MRC_CACHE_VERSION, md->buffer, md->buffer_len);
+	mrc_cache_stash_data(MRC_TRAINING_DATA, reg_frame_rev(),
+			     reg_frame_ptr(), reg_frame_size());
 }
 
 static struct mrc_data prepare_mrc_cache(void)
 {
 	struct mrc_data md = {0};
 	md.buffer = mrc_cache_current_mmap_leak(MRC_TRAINING_DATA,
-						MRC_CACHE_VERSION,
+						reg_frame_rev(),
 						&md.buffer_len);
 	return md;
 }
@@ -94,14 +88,15 @@ static void raminit_reset(void)
 }
 
 static enum raminit_boot_mode do_actual_raminit(
-	struct mrc_data *md,
 	const bool s3resume,
 	const bool cpu_replaced,
 	const enum raminit_boot_mode orig_bootmode)
 {
+	struct mrc_data md = prepare_mrc_cache();
+
 	enum raminit_boot_mode bootmode = orig_bootmode;
 
-	bool save_data_valid = md->buffer && md->buffer_len == USHRT_MAX; /** TODO: sizeof() **/
+	bool save_data_valid = md.buffer && md.buffer_len == reg_frame_size();
 
 	if (s3resume) {
 		if (bootmode == BOOTMODE_COLD) {
@@ -154,7 +149,7 @@ static enum raminit_boot_mode do_actual_raminit(
 	assert(save_data_valid != (bootmode == BOOTMODE_COLD));
 	if (save_data_valid) {
 		printk(BIOS_INFO, "Using cached memory parameters\n");
-		die("RAMINIT: Fast boot is not yet implemented\n");
+		memcpy(reg_frame_ptr(), md.buffer, reg_frame_size());
 	}
 	printk(RAM_DEBUG, "Initial bootmode: %s\n", bm_names[orig_bootmode]);
 	printk(RAM_DEBUG, "Current bootmode: %s\n", bm_names[bootmode]);
@@ -181,10 +176,8 @@ void perform_raminit(const int s3resume)
 	wait_txt_clear();
 	wrmsr(0x2e6, (msr_t) {.lo = 0, .hi = 0});
 
-	struct mrc_data md = prepare_mrc_cache();
-
 	const enum raminit_boot_mode bootmode =
-			do_actual_raminit(&md, s3resume, cpu_replaced, orig_bootmode);
+			do_actual_raminit(s3resume, cpu_replaced, orig_bootmode);
 
 	/** TODO: report_memory_config **/
 
@@ -212,9 +205,8 @@ void perform_raminit(const int s3resume)
 	}
 
 	/* Save training data on non-S3 resumes */
-	/** TODO: Enable this once training data is populated **/
-	if (0 && !s3resume)
-		save_mrc_data(&md);
+	if (!s3resume)
+		save_mrc_data();
 
 	/** TODO: setup_sdram_meminfo **/
 }
diff --git a/src/northbridge/intel/haswell/native_raminit/raminit_native.h b/src/northbridge/intel/haswell/native_raminit/raminit_native.h
index a0a913f926..2ac16eaad3 100644
--- a/src/northbridge/intel/haswell/native_raminit/raminit_native.h
+++ b/src/northbridge/intel/haswell/native_raminit/raminit_native.h
@@ -170,6 +170,8 @@ enum regfile_mode {
 	REG_FILE_USE_CURRENT,	/* Used when changing parameters after the test */
 };
 
+struct register_save_frame;
+
 struct wdb_pat {
 	uint32_t start_ptr;	/* Starting pointer in WDB */
 	uint32_t stop_ptr;	/* Stopping pointer in WDB */
@@ -220,6 +222,7 @@ enum raminit_status {
 	RAMINIT_STATUS_RCVEN_FAILURE,
 	RAMINIT_STATUS_RMPR_FAILURE,
 	RAMINIT_STATUS_JWRL_FAILURE,
+	RAMINIT_STATUS_INVALID_CACHE,
 	RAMINIT_STATUS_UNSPECIFIED_ERROR, /** TODO: Deprecated in favor of specific values **/
 };
 
@@ -229,6 +232,11 @@ enum generic_stepping {
 	STEPPING_C0 = 3,
 };
 
+struct mrc_data {
+	const void *buffer;
+	size_t buffer_len;
+};
+
 struct raminit_dimm_info {
 	spd_ddr3_raw_data raw_spd;
 	struct dimm_attr_ddr3_st data;
@@ -448,12 +456,22 @@ enum raminit_status do_jedec_init(struct sysinfo *ctrl);
 enum raminit_status train_receive_enable(struct sysinfo *ctrl);
 enum raminit_status train_read_mpr(struct sysinfo *ctrl);
 enum raminit_status train_jedec_write_leveling(struct sysinfo *ctrl);
+enum raminit_status save_training_values(struct sysinfo *ctrl);
+enum raminit_status restore_training_values(struct sysinfo *ctrl);
+enum raminit_status save_non_training(struct sysinfo *ctrl);
+enum raminit_status restore_non_training(struct sysinfo *ctrl);
+enum raminit_status exit_selfrefresh(struct sysinfo *ctrl);
+enum raminit_status normal_state(struct sysinfo *ctrl);
 enum raminit_status activate_mc(struct sysinfo *ctrl);
 enum raminit_status raminit_done(struct sysinfo *ctrl);
 
 void configure_timings(struct sysinfo *ctrl);
 void configure_refresh(struct sysinfo *ctrl);
 
+struct register_save_frame *reg_frame_ptr(void);
+size_t reg_frame_size(void);
+uint32_t reg_frame_rev(void);
+
 uint32_t get_tCKE(uint32_t mem_clock_mhz, bool lpddr);
 uint32_t get_tXPDLL(uint32_t mem_clock_mhz);
 uint32_t get_tAONPD(uint32_t mem_clock_mhz);
diff --git a/src/northbridge/intel/haswell/native_raminit/save_restore.c b/src/northbridge/intel/haswell/native_raminit/save_restore.c
new file mode 100644
index 0000000000..f1f50e3ff8
--- /dev/null
+++ b/src/northbridge/intel/haswell/native_raminit/save_restore.c
@@ -0,0 +1,387 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <assert.h>
+#include <console/console.h>
+#include <northbridge/intel/haswell/haswell.h>
+#include <types.h>
+
+#include "raminit_native.h"
+
+uint32_t reg_frame_rev(void)
+{
+	/*
+	 * Equivalent to MRC_CACHE_REVISION, but hidden via abstraction.
+	 * The structures that get saved to flash are contained within
+	 * this translation unit, so changes outside this file shouldn't
+	 * require invalidating the cache.
+	 */
+	return 1;
+}
+
+struct register_save {
+	uint16_t lower;
+	uint16_t upper;
+};
+
+/** TODO: Haswell DDRIO aliases writes: 0x80 .. 0xff => 0x00 .. 0x7f **/
+static const struct register_save ddrio_per_byte_list[] = {
+	{0x0000, 0x003c}, /* 16 registers */
+//	{0x0048, 0x0084}, /* 16 registers */	/** TODO: BDW support **/
+	{0x0048, 0x004c}, /*  2 registers */
+	{0x005c, 0x0078}, /*  8 registers */
+};
+#define DDRIO_PER_BYTE_REGISTER_COUNT	(16 + 2 + 8)
+
+static const struct register_save ddrio_per_ch_list[] = {
+	/* CKE */
+	{0x1204, 0x1208}, /* 2 registers */
+	{0x1214, 0x121c}, /* 3 registers */
+	/* CMD North */
+	{0x1404, 0x140c}, /* 3 registers */
+	/* CLK */
+	{0x1808, 0x1810}, /* 3 registers */
+	/* CMD South */
+	{0x1a04, 0x1a0c}, /* 3 registers */
+	/* CTL */
+	{0x1c14, 0x1c1c}, /* 3 registers */
+};
+#define DDRIO_PER_CH_REGISTER_COUNT	(2 + 3 * 5)
+
+static const struct register_save ddrio_common_list[] = {
+	{0x2000, 0x2008}, /* 3 registers */
+	{0x3a14, 0x3a1c}, /* 3 registers */
+	{0x3a24, 0x3a24}, /* 1 registers */
+};
+
+#define DDRIO_COMMON_REGISTER_COUNT	(3 + 3 + 1)
+
+static const struct register_save mcmain_per_ch_list[] = {
+	{0x4000, 0x4014}, /* 6 registers */
+	{0x4024, 0x4028}, /* 2 registers */
+	{0x40d0, 0x40d0}, /* 1 registers */
+	{0x4220, 0x4224}, /* 2 registers */
+	{0x4294, 0x4294}, /* 1 registers */
+	{0x429c, 0x42a0}, /* 2 registers */
+	{0x42ec, 0x42fc}, /* 5 registers */
+	{0x4328, 0x4328}, /* 1 registers */
+	{0x438c, 0x4390}, /* 2 registers */
+};
+#define MCMAIN_PER_CH_REGISTER_COUNT	(6 + 2 + 1 + 2 + 1 + 2 + 5 + 1 + 2)
+
+static const struct register_save misc_common_list[] = {
+	{0x5884, 0x5888}, /*  2 registers */
+	{0x5890, 0x589c}, /*  4 registers */
+	{0x58a4, 0x58a4}, /*  1 registers */
+	{0x58d0, 0x58e4}, /*  6 registers */
+	{0x5880, 0x5880}, /*  1 registers */
+	{0x5000, 0x50dc}, /* 56 registers */
+	{0x59b8, 0x59b8}  /*  1 registers */
+};
+#define MISC_COMMON_REGISTER_COUNT	(2 + 4 + 1 + 6 + 1 + 56 + 1)
+
+struct save_params {
+	bool is_initialised;
+
+	/* Memory base frequency, either 100 or 133 MHz */
+	uint8_t base_freq;
+
+	/* Multiplier */
+	uint32_t multiplier;
+
+	/* Memory clock in MHz */
+	uint32_t mem_clock_mhz;
+
+	/* Memory clock in femtoseconds */
+	uint32_t mem_clock_fs;
+
+	/* Quadrature clock in picoseconds */
+	uint16_t qclkps;
+
+	/* Bitfield of supported CAS latencies */
+	uint16_t cas_supported;
+
+	/* CPUID value */
+	uint32_t cpu;
+
+	/* Cached CPU stepping value */
+	uint8_t stepping;
+
+	uint16_t vdd_mv;
+
+	union dimm_flags_ddr3_st flags;
+
+	/* Except for tCK, everything is stored in DCLKs */
+	uint32_t tCK;
+	uint32_t tAA;
+	uint32_t tWR;
+	uint32_t tRCD;
+	uint32_t tRRD;
+	uint32_t tRP;
+	uint32_t tRAS;
+	uint32_t tRC;
+	uint32_t tRFC;
+	uint32_t tWTR;
+	uint32_t tRTP;
+	uint32_t tFAW;
+	uint32_t tCWL;
+	uint32_t tCMD;
+
+	uint32_t tREFI;
+	uint32_t tXP;
+
+	uint8_t lpddr_cke_rank_map[NUM_CHANNELS];
+
+	struct raminit_dimm_info dimms[NUM_CHANNELS][NUM_SLOTS];
+
+	uint8_t chanmap;
+
+	uint32_t channel_size_mb[NUM_CHANNELS];
+
+	/* DIMMs per channel */
+	uint8_t dpc[NUM_CHANNELS];
+
+	uint8_t rankmap[NUM_CHANNELS];
+
+	/* Whether a rank is mirrored or not (only rank 1 of each DIMM can be) */
+	uint8_t rank_mirrored[NUM_CHANNELS];
+
+	/*
+	 * FIXME: LPDDR support is incomplete. The largest chunks are missing,
+	 * but some LPDDR-specific variations in algorithms have been handled.
+	 * LPDDR-specific functions have stubs which will halt upon execution.
+	 */
+	bool lpddr;
+
+	uint8_t lanes;
+
+	/* FIXME: ECC support missing */
+	bool is_ecc;
+};
+
+struct register_save_frame {
+	uint32_t ddrio_per_byte[NUM_CHANNELS][NUM_LANES][DDRIO_PER_BYTE_REGISTER_COUNT];
+	uint32_t ddrio_per_ch[NUM_CHANNELS][DDRIO_PER_CH_REGISTER_COUNT];
+	uint32_t ddrio_common[DDRIO_COMMON_REGISTER_COUNT];
+	uint32_t mcmain_per_ch[NUM_CHANNELS][MCMAIN_PER_CH_REGISTER_COUNT];
+	uint32_t misc_common[MISC_COMMON_REGISTER_COUNT];
+	struct save_params params;
+};
+
+struct register_save_frame *reg_frame_ptr(void)
+{
+	/* The chonky register save frame struct, used for fast boot and S3 resume */
+	static struct register_save_frame register_frame = { 0 };
+	return &register_frame;
+}
+
+size_t reg_frame_size(void)
+{
+	return sizeof(struct register_save_frame);
+}
+
+typedef void (*reg_func_t)(const uint16_t offset, uint32_t *const value);
+
+static void save_value(const uint16_t offset, uint32_t *const value)
+{
+	*value = mchbar_read32(offset);
+}
+
+static void restore_value(const uint16_t offset, uint32_t *const value)
+{
+	mchbar_write32(offset, *value);
+}
+
+static void save_restore(
+	uint32_t *reg_frame,
+	const uint16_t g_offset,
+	const struct register_save *reg_save_list,
+	const size_t reg_save_length,
+	reg_func_t handle_reg)
+{
+	for (size_t i = 0; i < reg_save_length; i++) {
+		const struct register_save *entry = &reg_save_list[i];
+		for (uint16_t offset = entry->lower; offset <= entry->upper; offset += 4) {
+			handle_reg(offset + g_offset, reg_frame++);
+		}
+	}
+}
+
+static void save_restore_all(struct register_save_frame *reg_frame, reg_func_t handle_reg)
+{
+	for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
+		for (uint8_t byte = 0; byte < NUM_LANES; byte++) {
+			const uint16_t g_offset = _DDRIO_C_R_B(0, channel, 0, byte);
+			save_restore(
+				reg_frame->ddrio_per_byte[channel][byte],
+				g_offset,
+				ddrio_per_byte_list,
+				ARRAY_SIZE(ddrio_per_byte_list),
+				handle_reg);
+		}
+	}
+	for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
+		const uint16_t g_offset = _DDRIO_C_R_B(0, channel, 0, 0);
+		save_restore(
+			reg_frame->ddrio_per_ch[channel],
+			g_offset,
+			ddrio_per_ch_list,
+			ARRAY_SIZE(ddrio_per_ch_list),
+			handle_reg);
+	}
+	save_restore(
+		reg_frame->ddrio_common,
+		0,
+		ddrio_common_list,
+		ARRAY_SIZE(ddrio_common_list),
+		handle_reg);
+
+	for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
+		const uint16_t g_offset = _MCMAIN_C(0, channel);
+		save_restore(
+			reg_frame->mcmain_per_ch[channel],
+			g_offset,
+			mcmain_per_ch_list,
+			ARRAY_SIZE(mcmain_per_ch_list),
+			handle_reg);
+	}
+	save_restore(
+		reg_frame->misc_common,
+		0,
+		misc_common_list,
+		ARRAY_SIZE(misc_common_list),
+		handle_reg);
+}
+
+enum raminit_status save_training_values(struct sysinfo *ctrl)
+{
+	save_restore_all(reg_frame_ptr(), save_value);
+	return RAMINIT_STATUS_SUCCESS;
+}
+
+enum raminit_status restore_training_values(struct sysinfo *ctrl)
+{
+	save_restore_all(reg_frame_ptr(), restore_value);
+	return RAMINIT_STATUS_SUCCESS;
+}
+
+enum raminit_status save_non_training(struct sysinfo *ctrl)
+{
+	struct register_save_frame *reg_frame = reg_frame_ptr();
+	struct save_params *params = &reg_frame->params;
+
+	params->is_initialised = true;
+
+	params->base_freq     = ctrl->base_freq;
+	params->multiplier    = ctrl->multiplier;
+	params->mem_clock_mhz = ctrl->mem_clock_mhz;
+	params->mem_clock_fs  = ctrl->mem_clock_fs;
+	params->qclkps        = ctrl->qclkps;
+	params->cas_supported = ctrl->cas_supported;
+	params->cpu           = ctrl->cpu;
+	params->stepping      = ctrl->stepping;
+	params->vdd_mv        = ctrl->vdd_mv;
+	params->flags         = ctrl->flags;
+
+	params->tCK       = ctrl->tCK;
+	params->tAA       = ctrl->tAA;
+	params->tWR       = ctrl->tWR;
+	params->tRCD      = ctrl->tRCD;
+	params->tRRD      = ctrl->tRRD;
+	params->tRP       = ctrl->tRP;
+	params->tRAS      = ctrl->tRAS;
+	params->tRC       = ctrl->tRC;
+	params->tRFC      = ctrl->tRFC;
+	params->tWTR      = ctrl->tWTR;
+	params->tRTP      = ctrl->tRTP;
+	params->tFAW      = ctrl->tFAW;
+	params->tCWL      = ctrl->tCWL;
+	params->tCMD      = ctrl->tCMD;
+	params->tREFI     = ctrl->tREFI;
+	params->tXP       = ctrl->tXP;
+
+	params->chanmap = ctrl->chanmap;
+	for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
+		params->lpddr_cke_rank_map[channel] = ctrl->lpddr_cke_rank_map[channel];
+		for (uint8_t slot = 0; slot < NUM_SLOTS; slot++)
+			params->dimms[channel][slot] = ctrl->dimms[channel][slot];
+	}
+	for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
+		params->dpc[channel] = ctrl->dpc[channel];
+		params->rankmap[channel] = ctrl->rankmap[channel];
+		params->rank_mirrored[channel] = ctrl->rank_mirrored[channel];
+		params->channel_size_mb[channel] = ctrl->channel_size_mb[channel];
+	}
+	params->lpddr = ctrl->lpddr;
+	params->lanes = ctrl->lanes;
+	params->is_ecc = ctrl->is_ecc;
+	return RAMINIT_STATUS_SUCCESS;
+}
+
+#define RAMINIT_COMPARE(_s1, _s2) \
+	((sizeof(_s1) == sizeof(_s2)) && !memcmp(_s1, _s2, sizeof(_s1)))
+
+enum raminit_status restore_non_training(struct sysinfo *ctrl)
+{
+	struct register_save_frame *reg_frame = reg_frame_ptr();
+	struct save_params *params = &reg_frame->params;
+
+	if (!params->is_initialised) {
+		printk(BIOS_WARNING, "Cannot fast boot: saved data is invalid\n");
+		return RAMINIT_STATUS_INVALID_CACHE;
+	}
+
+	if (!RAMINIT_COMPARE(ctrl->dimms, params->dimms)) {
+		printk(BIOS_WARNING, "Cannot fast boot: DIMMs have changed\n");
+		return RAMINIT_STATUS_INVALID_CACHE;
+	}
+
+	if (ctrl->cpu != params->cpu) {
+		printk(BIOS_WARNING, "Cannot fast boot: CPU has changed\n");
+		return RAMINIT_STATUS_INVALID_CACHE;
+	}
+
+	ctrl->base_freq     = params->base_freq;
+	ctrl->multiplier    = params->multiplier;
+	ctrl->mem_clock_mhz = params->mem_clock_mhz;
+	ctrl->mem_clock_fs  = params->mem_clock_fs;
+	ctrl->qclkps        = params->qclkps;
+	ctrl->cas_supported = params->cas_supported;
+	ctrl->cpu           = params->cpu;
+	ctrl->stepping      = params->stepping;
+	ctrl->vdd_mv        = params->vdd_mv;
+	ctrl->flags         = params->flags;
+
+	ctrl->tCK       = params->tCK;
+	ctrl->tAA       = params->tAA;
+	ctrl->tWR       = params->tWR;
+	ctrl->tRCD      = params->tRCD;
+	ctrl->tRRD      = params->tRRD;
+	ctrl->tRP       = params->tRP;
+	ctrl->tRAS      = params->tRAS;
+	ctrl->tRC       = params->tRC;
+	ctrl->tRFC      = params->tRFC;
+	ctrl->tWTR      = params->tWTR;
+	ctrl->tRTP      = params->tRTP;
+	ctrl->tFAW      = params->tFAW;
+	ctrl->tCWL      = params->tCWL;
+	ctrl->tCMD      = params->tCMD;
+	ctrl->tREFI     = params->tREFI;
+	ctrl->tXP       = params->tXP;
+
+	ctrl->chanmap = params->chanmap;
+	for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
+		ctrl->lpddr_cke_rank_map[channel] = params->lpddr_cke_rank_map[channel];
+		for (uint8_t slot = 0; slot < NUM_SLOTS; slot++)
+			ctrl->dimms[channel][slot] = params->dimms[channel][slot];
+	}
+	for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
+		ctrl->dpc[channel] = params->dpc[channel];
+		ctrl->rankmap[channel] = params->rankmap[channel];
+		ctrl->rank_mirrored[channel] = params->rank_mirrored[channel];
+		ctrl->channel_size_mb[channel] = params->channel_size_mb[channel];
+	}
+	ctrl->lpddr = params->lpddr;
+	ctrl->lanes = params->lanes;
+	ctrl->is_ecc = params->is_ecc;
+	return RAMINIT_STATUS_SUCCESS;
+}

From 5d291de6011a56bfd767c4bcdfdc3aa6ee87a2dd Mon Sep 17 00:00:00 2001
From: Angel Pons <th3fanbus@gmail.com>
Date: Wed, 17 Apr 2024 13:20:32 +0200
Subject: [PATCH 0316/3886] haswell NRI: Do sense amplifier offset training

Quoting Wikipedia:

  A sense amplifier is a circuit that is used to amplify and detect
  small signals in electronic systems. It is commonly used in memory
  circuits, such as dynamic random access memory (DRAM), to read and
  amplify the weak signals stored in memory cells.

In this case, we're calibrating the sense amplifiers in the memory
controller. This training procedure uses a magic "sense amp offset
cancel" mode of the DDRIO to observe the sampled logic levels, and
sweeps Vref to find the low-high transition for each bit lane. The
procedure consists of two stages: the first stage centers per-byte
Vref (to ensure per-bit Vref offsets are as small as possible) and
the second stage centers per-bit Vref.

Because this procedure uses the "sense amp offset cancel" mode, it
does not rely on DRAM being trained. It is assumed that the memory
controller simply makes sense amp output levels observable via the
`DDR_DATA_TRAIN_FEEDBACK` register and that the memory bus is idle
during this training step (so the lane voltage is Vdd / 2).

Note: This procedure will need to be adapted for Broadwell because
it has per-rank per-bit RxVref registers, whereas Haswell only has
a single per-bit RxVref register for all ranks.

Change-Id: Ia07db68763f90e9701c8a376e01279ada8dbbe07
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81948
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 .../intel/haswell/native_raminit/Makefile.mk  |   1 +
 .../haswell/native_raminit/raminit_main.c     |   1 +
 .../haswell/native_raminit/raminit_native.h   |  12 +
 .../native_raminit/train_sense_amp_offset.c   | 334 ++++++++++++++++++
 .../intel/haswell/registers/mchbar.h          |   2 +
 5 files changed, 350 insertions(+)
 create mode 100644 src/northbridge/intel/haswell/native_raminit/train_sense_amp_offset.c

diff --git a/src/northbridge/intel/haswell/native_raminit/Makefile.mk b/src/northbridge/intel/haswell/native_raminit/Makefile.mk
index 8fdd17c542..4bd668a2d6 100644
--- a/src/northbridge/intel/haswell/native_raminit/Makefile.mk
+++ b/src/northbridge/intel/haswell/native_raminit/Makefile.mk
@@ -21,3 +21,4 @@ romstage-y += timings_refresh.c
 romstage-y += train_jedec_write_leveling.c
 romstage-y += train_read_mpr.c
 romstage-y += train_receive_enable.c
+romstage-y += train_sense_amp_offset.c
diff --git a/src/northbridge/intel/haswell/native_raminit/raminit_main.c b/src/northbridge/intel/haswell/native_raminit/raminit_main.c
index b6f3144529..21c953b332 100644
--- a/src/northbridge/intel/haswell/native_raminit/raminit_main.c
+++ b/src/northbridge/intel/haswell/native_raminit/raminit_main.c
@@ -61,6 +61,7 @@ static const struct task_entry cold_boot[] = {
 	{ configure_memory_map,                                   true, "MEMMAP",     },
 	{ do_jedec_init,                                          true, "JEDECINIT",  },
 	{ pre_training,                                           true, "PRETRAIN",   },
+	{ train_sense_amp_offset,                                 true, "SOT",        },
 	{ train_receive_enable,                                   true, "RCVET",      },
 	{ train_read_mpr,                                         true, "RDMPRT",     },
 	{ train_jedec_write_leveling,                             true, "JWRL",       },
diff --git a/src/northbridge/intel/haswell/native_raminit/raminit_native.h b/src/northbridge/intel/haswell/native_raminit/raminit_native.h
index 2ac16eaad3..07eea98831 100644
--- a/src/northbridge/intel/haswell/native_raminit/raminit_native.h
+++ b/src/northbridge/intel/haswell/native_raminit/raminit_native.h
@@ -23,6 +23,8 @@
 #define NUM_LANES		9
 #define NUM_LANES_NO_ECC	8
 
+#define NUM_BITS		8
+
 #define COMP_INT		10
 
 /* Always use 12 legs for emphasis (not trained) */
@@ -219,6 +221,7 @@ enum raminit_status {
 	RAMINIT_STATUS_MPLL_INIT_FAILURE,
 	RAMINIT_STATUS_POLL_TIMEOUT,
 	RAMINIT_STATUS_REUT_ERROR,
+	RAMINIT_STATUS_SAMP_OFFSET_FAILURE,
 	RAMINIT_STATUS_RCVEN_FAILURE,
 	RAMINIT_STATUS_RMPR_FAILURE,
 	RAMINIT_STATUS_JWRL_FAILURE,
@@ -244,6 +247,12 @@ struct raminit_dimm_info {
 	bool valid;
 };
 
+struct vref_margin {
+	uint8_t low;
+	uint8_t center;
+	uint8_t high;
+};
+
 struct sysinfo {
 	enum raminit_boot_mode bootmode;
 	enum generic_stepping stepping;
@@ -331,6 +340,8 @@ struct sysinfo {
 	uint8_t rxdqsn[NUM_CHANNELS][NUM_SLOTRANKS][NUM_LANES];
 	int8_t  rxvref[NUM_CHANNELS][NUM_SLOTRANKS][NUM_LANES];
 
+	struct vref_margin rxdqvrefpb[NUM_CHANNELS][NUM_SLOTRANKS][NUM_LANES][NUM_BITS];
+
 	uint8_t clk_pi_code[NUM_CHANNELS][NUM_SLOTRANKS];
 	uint8_t ctl_pi_code[NUM_CHANNELS][NUM_SLOTRANKS];
 	uint8_t cke_pi_code[NUM_CHANNELS][NUM_SLOTRANKS];
@@ -453,6 +464,7 @@ enum raminit_status convert_timings(struct sysinfo *ctrl);
 enum raminit_status configure_mc(struct sysinfo *ctrl);
 enum raminit_status configure_memory_map(struct sysinfo *ctrl);
 enum raminit_status do_jedec_init(struct sysinfo *ctrl);
+enum raminit_status train_sense_amp_offset(struct sysinfo *ctrl);
 enum raminit_status train_receive_enable(struct sysinfo *ctrl);
 enum raminit_status train_read_mpr(struct sysinfo *ctrl);
 enum raminit_status train_jedec_write_leveling(struct sysinfo *ctrl);
diff --git a/src/northbridge/intel/haswell/native_raminit/train_sense_amp_offset.c b/src/northbridge/intel/haswell/native_raminit/train_sense_amp_offset.c
new file mode 100644
index 0000000000..6989dd6318
--- /dev/null
+++ b/src/northbridge/intel/haswell/native_raminit/train_sense_amp_offset.c
@@ -0,0 +1,334 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <assert.h>
+#include <commonlib/bsd/clamp.h>
+#include <console/console.h>
+#include <delay.h>
+#include <lib.h>
+#include <types.h>
+
+#include "raminit_native.h"
+
+#define VREF_OFFSET_PLOT	RAM_DEBUG
+#define SAMP_OFFSET_PLOT	RAM_DEBUG
+
+struct vref_train_data {
+	int8_t best_sum;
+	int8_t best_vref;
+	int8_t sum_bits;
+	uint8_t high_mask;
+	uint8_t low_mask;
+};
+
+static void propagate_delay_values(struct sysinfo *ctrl, uint8_t channel)
+{
+	/* Propagate delay values (without a read command) */
+	union ddr_data_control_0_reg data_control_0 = {
+		.raw = ctrl->dq_control_0[channel],
+	};
+	data_control_0.read_rf_rd      = 1;
+	data_control_0.read_rf_wr      = 0;
+	data_control_0.read_rf_rank    = 0;
+	data_control_0.force_odt_on    = 1;
+	data_control_0.samp_train_mode = 1;
+	mchbar_write32(DDR_DATA_ch_CONTROL_0(channel), data_control_0.raw);
+	udelay(1);
+	data_control_0.samp_train_mode = 0;
+	mchbar_write32(DDR_DATA_ch_CONTROL_0(channel), data_control_0.raw);
+}
+
+static enum raminit_status train_vref_offset(struct sysinfo *ctrl)
+{
+	const int8_t vref_start = -15;
+	const int8_t vref_stop  = 15;
+	const struct vref_train_data initial_vref_values = {
+		.best_sum  = -NUM_LANES,
+		.best_vref = 0,
+		.high_mask = 0,
+		.low_mask  = 0xff,
+	};
+	struct vref_train_data vref_data[NUM_CHANNELS][NUM_LANES];
+
+	printk(VREF_OFFSET_PLOT, "Plot of sum_bits across Vref settings\nChannel");
+	for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
+		if (!does_ch_exist(ctrl, channel))
+			continue;
+
+		printk(VREF_OFFSET_PLOT, "\t%u\t\t", channel);
+	}
+
+	printk(VREF_OFFSET_PLOT, "\nByte");
+	for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
+		if (!does_ch_exist(ctrl, channel))
+			continue;
+
+		printk(VREF_OFFSET_PLOT, "\t");
+		for (uint8_t byte = 0; byte < ctrl->lanes; byte++) {
+			printk(VREF_OFFSET_PLOT, "%u ", byte);
+			vref_data[channel][byte] = initial_vref_values;
+			union ddr_data_control_2_reg data_control_2 = {
+				.raw = ctrl->dq_control_2[channel][byte],
+			};
+			data_control_2.force_bias_on = 1;
+			data_control_2.force_rx_on   = 1;
+			mchbar_write32(DQ_CONTROL_2(channel, byte), data_control_2.raw);
+		}
+	}
+
+	/* Sweep through Vref settings and find point SampOffset of +/- 7 passes */
+	printk(VREF_OFFSET_PLOT, "\n1/2 Vref");
+	for (int8_t vref = vref_start; vref <= vref_stop; vref++) {
+		printk(VREF_OFFSET_PLOT, "\n% 3d", vref);
+
+		/*
+		 * To perform this test, enable offset cancel mode and enable ODT.
+		 * Check results and update variables. Ideal result is all zeroes.
+		 * Clear offset cancel mode at end of test to write RX_OFFSET_VDQ.
+		 */
+		change_1d_margin_multicast(ctrl, RdV, vref, 0, false, REG_FILE_USE_RANK);
+
+		/* Program settings for Vref and SampOffset = 7 (8 + 7) */
+		mchbar_write32(DDR_DATA_RX_OFFSET_VDQ, 0xffffffff);
+		for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
+			if (!does_ch_exist(ctrl, channel))
+				continue;
+
+			propagate_delay_values(ctrl, channel);
+			for (uint8_t byte = 0; byte < ctrl->lanes; byte++) {
+				const uint8_t feedback = get_data_train_feedback(channel, byte);
+				struct vref_train_data *curr_data = &vref_data[channel][byte];
+				curr_data->low_mask &= feedback;
+				curr_data->sum_bits = -popcnt(feedback);
+			}
+		}
+
+		/* Program settings for Vref and SampOffset = -7 (8 - 7) */
+		mchbar_write32(DDR_DATA_RX_OFFSET_VDQ, 0x11111111);
+		for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
+			if (!does_ch_exist(ctrl, channel))
+				continue;
+
+			propagate_delay_values(ctrl, channel);
+			printk(VREF_OFFSET_PLOT, "\t");
+			for (uint8_t byte = 0; byte < ctrl->lanes; byte++) {
+				const uint8_t feedback = get_data_train_feedback(channel, byte);
+				struct vref_train_data *curr_data = &vref_data[channel][byte];
+				curr_data->high_mask |= feedback;
+				curr_data->sum_bits += popcnt(feedback);
+				printk(VREF_OFFSET_PLOT, "%d ", curr_data->sum_bits);
+				if (curr_data->sum_bits > curr_data->best_sum) {
+					curr_data->best_sum  = curr_data->sum_bits;
+					curr_data->best_vref = vref;
+					ctrl->rxvref[channel][0][byte] = vref;
+				} else if (curr_data->sum_bits == curr_data->best_sum) {
+					curr_data->best_vref = vref;
+				}
+			}
+		}
+	}
+	printk(BIOS_DEBUG, "\n\nHi-Lo (XOR):");
+	enum raminit_status status = RAMINIT_STATUS_SUCCESS;
+	for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
+		if (!does_ch_exist(ctrl, channel))
+			continue;
+
+		printk(BIOS_DEBUG, "\n  C%u:", channel);
+		for (uint8_t byte = 0; byte < ctrl->lanes; byte++) {
+			struct vref_train_data *const curr_data = &vref_data[channel][byte];
+			const uint8_t bit_xor = curr_data->high_mask ^ curr_data->low_mask;
+			printk(BIOS_DEBUG, "\t0x%02x", bit_xor);
+			if (bit_xor == 0xff)
+				continue;
+
+			/* Report an error if any bit did not change */
+			status = RAMINIT_STATUS_SAMP_OFFSET_FAILURE;
+		}
+	}
+	if (status)
+		printk(BIOS_ERR, "\nUnexpected bit error in Vref offset training\n");
+
+	printk(BIOS_DEBUG, "\n\nRdVref:");
+	change_1d_margin_multicast(ctrl, RdV, 0, 0, false, REG_FILE_USE_RANK);
+	for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
+		if (!does_ch_exist(ctrl, channel))
+			continue;
+
+		printk(BIOS_DEBUG, "\n  C%u:", channel);
+		for (uint8_t byte = 0; byte < ctrl->lanes; byte++) {
+			struct vref_train_data *const curr_data = &vref_data[channel][byte];
+			const int8_t vref_width =
+				curr_data->best_vref - ctrl->rxvref[channel][0][byte];
+
+			/*
+			 * Step size for Rx Vref in DATA_OFFSET_TRAIN is about 3.9 mV
+			 * whereas Rx Vref step size in RX_TRAIN_RANK is about 7.8 mV
+			 */
+			int8_t vref = ctrl->rxvref[channel][0][byte] + vref_width / 2;
+			if (vref < 0)
+				vref--;
+			else
+				vref++;
+
+			for (uint8_t rank = 0; rank < NUM_SLOTRANKS; rank++) {
+				if (!rank_in_ch(ctrl, rank, channel))
+					continue;
+
+				ctrl->rxvref[channel][rank][byte] = vref / 2;
+				update_rxt(ctrl, channel, rank, byte, RXT_RESTORE, 0);
+			}
+			printk(BIOS_DEBUG, "\t% 4d", ctrl->rxvref[channel][0][byte]);
+		}
+	}
+	printk(BIOS_DEBUG, "\n\n");
+	return status;
+}
+
+/**
+ * LPDDR has an additional bit for DQS per each byte.
+ *
+ * TODO: The DQS value must be written into Data Control 2.
+ */
+#define NUM_OFFSET_TRAIN_BITS	(NUM_BITS + 1)
+
+#define PLOT_CH_SPACE		"  "
+
+struct samp_train_data {
+	uint8_t first_zero;
+	uint8_t last_one;
+};
+
+static void train_samp_offset(struct sysinfo *ctrl)
+{
+	const uint8_t max_train_bits = ctrl->lpddr ? NUM_OFFSET_TRAIN_BITS : NUM_BITS;
+
+	struct samp_train_data samp_data[NUM_CHANNELS][NUM_LANES][NUM_OFFSET_TRAIN_BITS] = {0};
+
+	printk(BIOS_DEBUG, "Channel ");
+	for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
+		if (!does_ch_exist(ctrl, channel))
+			continue;
+
+		printk(BIOS_DEBUG, "%u ", channel); /* Same length as PLOT_CH_SPACE */
+		for (uint8_t byte = 0; byte < ctrl->lanes; byte++)
+			printk(BIOS_DEBUG, "        %s ", ctrl->lpddr ? " " : "");
+	}
+	printk(BIOS_DEBUG, "\nByte    ");
+	for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
+		if (!does_ch_exist(ctrl, channel))
+			continue;
+
+		for (uint8_t byte = 0; byte < ctrl->lanes; byte++)
+			printk(BIOS_DEBUG, "%u       %s ", byte, ctrl->lpddr ? " " : "");
+
+		printk(BIOS_DEBUG, PLOT_CH_SPACE);
+	}
+	printk(SAMP_OFFSET_PLOT, "\nBits    ");
+	for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
+		for (uint8_t byte = 0; byte < ctrl->lanes; byte++)
+			printk(SAMP_OFFSET_PLOT, "01234567%s ", ctrl->lpddr ? "S" : "");
+
+		printk(SAMP_OFFSET_PLOT, PLOT_CH_SPACE);
+	}
+	printk(SAMP_OFFSET_PLOT, "\n SAmp\n");
+	for (uint8_t samp_offset = 1; samp_offset <= 15; samp_offset++) {
+		printk(SAMP_OFFSET_PLOT, "% 5d\t", samp_offset);
+
+		uint32_t rx_offset_vdq = 0;
+		for (uint8_t bit = 0; bit < NUM_BITS; bit++) {
+			rx_offset_vdq += samp_offset << (4 * bit);
+		}
+		mchbar_write32(DDR_DATA_RX_OFFSET_VDQ, rx_offset_vdq);
+		for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
+			if (!does_ch_exist(ctrl, channel))
+				continue;
+
+			/* Propagate delay values (without a read command) */
+			union ddr_data_control_0_reg data_control_0 = {
+				.raw = ctrl->dq_control_0[channel],
+			};
+			data_control_0.read_rf_rd      = 1;
+			data_control_0.read_rf_wr      = 0;
+			data_control_0.read_rf_rank    = 0;
+			data_control_0.force_odt_on    = 1;
+			data_control_0.samp_train_mode = 1;
+			mchbar_write32(DDR_DATA_ch_CONTROL_0(channel), data_control_0.raw);
+			udelay(1);
+			for (uint8_t byte = 0; byte < ctrl->lanes; byte++) {
+				const uint32_t feedback =
+					get_data_train_feedback(channel, byte);
+
+				for (uint8_t bit = 0; bit < max_train_bits; bit++) {
+					struct samp_train_data *const curr_data =
+							&samp_data[channel][byte][bit];
+					const bool result = feedback & BIT(bit);
+					if (result) {
+						curr_data->last_one = samp_offset;
+					} else if (curr_data->first_zero == 0) {
+						curr_data->first_zero = samp_offset;
+					}
+					printk(SAMP_OFFSET_PLOT, result ? "." : "#");
+				}
+				printk(SAMP_OFFSET_PLOT, " ");
+			}
+			printk(SAMP_OFFSET_PLOT, PLOT_CH_SPACE);
+			data_control_0.samp_train_mode = 0;
+			mchbar_write32(DDR_DATA_ch_CONTROL_0(channel), data_control_0.raw);
+		}
+		printk(SAMP_OFFSET_PLOT, "\n");
+	}
+	printk(BIOS_DEBUG, "\nBitSAmp ");
+	for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
+		if (!does_ch_exist(ctrl, channel))
+			continue;
+
+		for (uint8_t byte = 0; byte < ctrl->lanes; byte++) {
+			uint32_t rx_offset_vdq = 0;
+			for (uint8_t bit = 0; bit < max_train_bits; bit++) {
+				struct samp_train_data *const curr_data =
+						&samp_data[channel][byte][bit];
+
+				uint8_t vref = curr_data->first_zero + curr_data->last_one;
+				vref = clamp_u8(0, vref / 2, 15);
+				/*
+				 * Check for saturation conditions to make sure
+				 * we are as close as possible to Vdd/2 (750 mV).
+				 */
+				if (curr_data->first_zero == 0)
+					vref = 15;
+				if (curr_data->last_one == 0)
+					vref = 0;
+
+				ctrl->rxdqvrefpb[channel][0][byte][bit].center = vref;
+				rx_offset_vdq += vref & 0xf << (4 * bit);
+				printk(BIOS_DEBUG, "%x", vref);
+			}
+			mchbar_write32(RX_OFFSET_VDQ(channel, byte), rx_offset_vdq);
+			printk(BIOS_DEBUG, " ");
+			download_regfile(ctrl, channel, 1, 0, REG_FILE_USE_RANK, 0, 1, 0);
+		}
+		printk(BIOS_DEBUG, PLOT_CH_SPACE);
+	}
+	printk(BIOS_DEBUG, "\n");
+}
+
+enum raminit_status train_sense_amp_offset(struct sysinfo *ctrl)
+{
+	printk(BIOS_DEBUG, "Stage 1: Vref offset training\n");
+	const enum raminit_status status = train_vref_offset(ctrl);
+
+	printk(BIOS_DEBUG, "Stage 2: Samp offset training\n");
+	train_samp_offset(ctrl);
+
+	/* Clean up after test */
+	for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
+		if (!does_ch_exist(ctrl, channel))
+			continue;
+
+		mchbar_write32(DDR_DATA_ch_CONTROL_0(channel), ctrl->dq_control_0[channel]);
+		for (uint8_t byte = 0; byte < ctrl->lanes; byte++)
+			mchbar_write32(DQ_CONTROL_2(channel, byte),
+				ctrl->dq_control_2[channel][byte]);
+	}
+	io_reset();
+	return status;
+}
diff --git a/src/northbridge/intel/haswell/registers/mchbar.h b/src/northbridge/intel/haswell/registers/mchbar.h
index 49a215aa71..1a168a3fc8 100644
--- a/src/northbridge/intel/haswell/registers/mchbar.h
+++ b/src/northbridge/intel/haswell/registers/mchbar.h
@@ -18,6 +18,8 @@
 #define RX_TRAIN_ch_r_b(ch, rank, byte)		_DDRIO_C_R_B(0x0000, ch, rank, byte)
 #define TX_TRAIN_ch_r_b(ch, rank, byte)		_DDRIO_C_R_B(0x0020, ch, rank, byte)
 
+#define RX_OFFSET_VDQ(ch, byte)			_DDRIO_C_R_B(0x004c, ch, 0, byte)
+
 #define DDR_DATA_TRAIN_FEEDBACK(ch, byte)	_DDRIO_C_R_B(0x0054, ch, 0, byte)
 
 #define DQ_CONTROL_1(ch, byte)			_DDRIO_C_R_B(0x0060, ch, 0, byte)

From 2b131cc7442c0436e8bea544b4add13bfe9cfb9c Mon Sep 17 00:00:00 2001
From: Yidi Lin <yidilin@chromium.org>
Date: Wed, 22 Jan 2025 09:51:08 +0800
Subject: [PATCH 0317/3886] soc/mediatek/mt8196: Eliminate mt6685_hw.h and
 mt6685_rtc_hw.h

Utilize the constants in rtc_reg_common.h and rtc_common.h.

1. Maintain minimum defines in mt6685_rtc.h.
2. Remove mt6685_hw.h and mt6685_rtc_hw.h.
3. Remove redundant definitions.

The constains in mt6685_rtc.h are determined by below command,

aarch64-cros-linux-gnu-gcc -E src/soc/mediatek/mt8196/mt6685_rtc.c \
-I src/commonlib/bsd/include/ -I src/include/ \
-I src/commonlib/include/ -I src/soc/mediatek/mt8196/include/ \
-I src/soc/mediatek/common/include/ -I src/arch/arm64/include/armv8/ \
-I ./src/arch/arm64/include/

BRANCH=rauru
BUG=b:391067089
TEST=compare macro expansion result before and after applying the patch
TEST=boot to kernel without RTC error

Change-Id: I69ee165df6a1c9ea5853173f46f0aafc382153c1
Signed-off-by: Yidi Lin <yidilin@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86264
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
---
 .../mediatek/mt8196/include/soc/mt6685_hw.h   | 942 ------------------
 .../mediatek/mt8196/include/soc/mt6685_rtc.h  | 180 ++--
 .../mt8196/include/soc/mt6685_rtc_hw.h        | 372 -------
 src/soc/mediatek/mt8196/include/soc/rtc.h     |   1 +
 src/soc/mediatek/mt8196/mt6685_rtc.c          |   4 +-
 5 files changed, 126 insertions(+), 1373 deletions(-)
 delete mode 100644 src/soc/mediatek/mt8196/include/soc/mt6685_hw.h
 delete mode 100644 src/soc/mediatek/mt8196/include/soc/mt6685_rtc_hw.h

diff --git a/src/soc/mediatek/mt8196/include/soc/mt6685_hw.h b/src/soc/mediatek/mt8196/include/soc/mt6685_hw.h
deleted file mode 100644
index dce7a07689..0000000000
--- a/src/soc/mediatek/mt8196/include/soc/mt6685_hw.h
+++ /dev/null
@@ -1,942 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only OR MIT */
-
-/*
- * This file is created based on MT8196 Functional Specification
- * Chapter number: 14.2.4
- */
-
-#ifndef SOC_MEDIATEK_MT8196_MT6685_HW_H
-#define SOC_MEDIATEK_MT8196_MT6685_HW_H
-
-#define MT6685_HWCID_L			0x8
-
-#define MT6685_RG_OCT1_IO_0		0xa7
-#define MT6685_RG_OCT1_IO_1		0xa8
-#define MT6685_TOP_CON			0x18
-#define MT6685_TOP_CKPDN_CON0		0x10b
-#define MT6685_TOP_CKPDN_CON0_SET	0x10c
-#define MT6685_TOP_CKPDN_CON0_CLR	0x10d
-#define MT6685_TOP_CKSEL_CON0		0x111
-#define MT6685_TOP_CKSEL_CON0_SET	0x112
-#define MT6685_TOP_CKSEL_CON0_CLR	0x113
-#define MT6685_TOP_RST_MISC_CLR		0x129
-#define MT6685_RG_SEQ_OFF		0x12f
-#define MT6685_RG_OCTL_SDAT		0x131
-#define MT6685_TOP_TMA_KEY		0x39e
-#define MT6685_TOP_TMA_KEY_H		0x39f
-#define MT6685_TOP_DIG_WPK		0x3a8
-#define MT6685_TOP_DIG_WPK_H		0x3a9
-#define MT6685_SPMI_PWR_CMD		0x408
-#define MT6685_SCK_TOP_CON0_L		0x50c
-#define MT6685_SCK_TOP_CON0_H		0x50d
-#define MT6685_SCK_TOP_CKPDN_CON0_L	0x514
-#define MT6685_SCK_TOP_CKPDN_CON0_L_SET	0x515
-#define MT6685_SCK_TOP_CKPDN_CON0_L_CLR	0x516
-#define MT6685_SCK_TOP_RST_CON0		0x522
-#define MT6685_FQMTR_CON0_L		0x546
-#define MT6685_FQMTR_CON0_H		0x547
-#define MT6685_FQMTR_CON1_L		0x548
-#define MT6685_FQMTR_CON2_L		0x54a
-#define MT6685_SCK_TOP_CKSEL_CON	0x568
-#define MT6685_RTC_SPAR_RELOAD		0x56a
-#define MT6685_RTC_ANA_ID		0x580
-#define MT6685_RTC_DIG_ID		0x581
-#define MT6685_RTC_ANA_REV		0x582
-#define MT6685_RTC_DIG_REV		0x583
-#define MT6685_RTC_DBI			0x584
-#define MT6685_RTC_ESP			0x585
-#define MT6685_RTC_FPI			0x586
-#define MT6685_RTC_DXI			0x587
-#define MT6685_RTC_BBPU_L		0x588
-#define MT6685_RTC_BBPU_H		0x589
-#define MT6685_RTC_IRQ_STA		0x58a
-#define MT6685_RTC_IRQ_EN		0x58c
-#define MT6685_RTC_CII_EN_L		0x58e
-#define MT6685_RTC_CII_EN_H		0x58f
-#define MT6685_RTC_AL_MASK		0x590
-#define MT6685_RTC_TC_SEC		0x592
-#define MT6685_RTC_TC_MIN		0x594
-#define MT6685_RTC_TC_HOU		0x596
-#define MT6685_RTC_TC_DOM		0x598
-#define MT6685_RTC_TC_DOW		0x59a
-#define MT6685_RTC_TC_MTH_L		0x59c
-#define MT6685_RTC_TC_MTH_H		0x59d
-#define MT6685_RTC_TC_YEA		0x59e
-#define MT6685_RTC_AL_SEC_L		0x5a0
-#define MT6685_RTC_AL_SEC_H		0x5a1
-#define MT6685_RTC_AL_MIN		0x5a2
-#define MT6685_RTC_AL_HOU_L		0x5a4
-#define MT6685_RTC_AL_HOU_H		0x5a5
-#define MT6685_RTC_AL_DOM_L		0x5a6
-#define MT6685_RTC_AL_DOM_H		0x5a7
-#define MT6685_RTC_AL_DOW_L		0x5a8
-#define MT6685_RTC_AL_DOW_H		0x5a9
-#define MT6685_RTC_AL_MTH_L		0x5aa
-#define MT6685_RTC_AL_MTH_H		0x5ab
-#define MT6685_RTC_AL_YEA_L		0x5ac
-#define MT6685_RTC_AL_YEA_H		0x5ad
-#define MT6685_RTC_OSC32CON_L		0x5ae
-#define MT6685_RTC_OSC32CON_H		0x5af
-#define MT6685_RTC_POWERKEY1_L		0x5b0
-#define MT6685_RTC_POWERKEY1_H		0x5b1
-#define MT6685_RTC_POWERKEY2_L		0x5b2
-#define MT6685_RTC_POWERKEY2_H		0x5b3
-#define MT6685_RTC_PDN1_L		0x5b4
-#define MT6685_RTC_PDN1_H		0x5b5
-#define MT6685_RTC_PDN2_L		0x5b6
-#define MT6685_RTC_PDN2_H		0x5b7
-#define MT6685_RTC_SPAR0_L		0x5b8
-#define MT6685_RTC_SPAR0_H		0x5b9
-#define MT6685_RTC_SPAR1_L		0x5ba
-#define MT6685_RTC_SPAR1_H		0x5bb
-#define MT6685_RTC_PROT_L		0x5bc
-#define MT6685_RTC_PROT_H		0x5bd
-#define MT6685_RTC_DIFF_L		0x5be
-#define MT6685_RTC_DIFF_H		0x5bf
-#define MT6685_RTC_CALI_L		0x5c0
-#define MT6685_RTC_CALI_H		0x5c1
-#define MT6685_RTC_WRTGR		0x5c2
-#define MT6685_RTC_CON_L		0x5c4
-#define MT6685_RTC_CON_H		0x5c5
-#define MT6685_RTC_SEC_CTRL		0x5c6
-#define MT6685_RTC_INT_CNT_L		0x5c8
-#define MT6685_RTC_INT_CNT_H		0x5c9
-#define MT6685_RTC_SEC_DAT0_L		0x5ca
-#define MT6685_RTC_SEC_DAT0_H		0x5cb
-#define MT6685_RTC_SEC_DAT1_L		0x5cc
-#define MT6685_RTC_SEC_DAT1_H		0x5cd
-#define MT6685_RTC_SEC_DAT2_L		0x5ce
-#define MT6685_RTC_SEC_DAT2_H		0x5cf
-#define MT6685_RTC_RG_FG0		0x5d0
-#define MT6685_RTC_RG_FG1		0x5d2
-#define MT6685_RTC_RG_FG2		0x5d4
-#define MT6685_RTC_RG_FG3		0x5d6
-#define MT6685_RTC_SPAR_MACRO		0x5d8
-#define MT6685_RTC_SPAR_CORE		0x5e0
-#define MT6685_RTC_EOSC_CALI		0x5e2
-#define MT6685_RTC_SEC_ANA_ID		0x600
-#define MT6685_RTC_SEC_DIG_ID		0x601
-#define MT6685_RTC_SEC_ANA_REV		0x602
-#define MT6685_RTC_SEC_DIG_REV		0x603
-#define MT6685_RTC_SEC_DBI		0x604
-#define MT6685_RTC_SEC_ESP		0x605
-#define MT6685_RTC_SEC_FPI		0x606
-#define MT6685_RTC_SEC_DXI		0x607
-#define MT6685_RTC_TC_SEC_SEC		0x608
-#define MT6685_RTC_TC_MIN_SEC		0x60a
-#define MT6685_RTC_TC_HOU_SEC		0x60c
-#define MT6685_RTC_TC_DOM_SEC		0x60e
-#define MT6685_RTC_TC_DOW_SEC		0x610
-#define MT6685_RTC_TC_MTH_SEC		0x612
-#define MT6685_RTC_TC_YEA_SEC		0x614
-#define MT6685_RTC_SEC_CK_PDN		0x616
-#define MT6685_RTC_SEC_WRTGR		0x618
-#define MT6685_DCXO_DIG_MODE_CW0	0x789
-
-#define MT6685_RG_SRCLKEN_IN0_HW_MODE_ADDR	\
-	MT6685_TOP_CON
-#define MT6685_RG_SRCLKEN_IN0_HW_MODE_MASK	0x1
-#define MT6685_RG_SRCLKEN_IN0_HW_MODE_SHIFT	1
-#define MT6685_RG_SRCLKEN_IN1_HW_MODE_ADDR	\
-	MT6685_TOP_CON
-#define MT6685_RG_SRCLKEN_IN1_HW_MODE_MASK	0x1
-#define MT6685_RG_FQMTR_32K_CK_PDN_ADDR		\
-	MT6685_TOP_CKPDN_CON0
-#define MT6685_RG_FQMTR_32K_CK_PDN_MASK		0x1
-#define MT6685_RG_FQMTR_32K_CK_PDN_SHIFT	4
-#define MT6685_RG_SRCLKEN_IN1_HW_MODE_SHIFT	2
-#define MT6685_RG_FQMTR_CK_PDN_ADDR		\
-	MT6685_TOP_CKPDN_CON0
-#define MT6685_RG_FQMTR_CK_PDN_MASK		0x1
-#define MT6685_RG_FQMTR_CK_PDN_SHIFT		5
-#define MT6685_RG_INTRP_CK_PDN_ADDR		\
-	MT6685_TOP_CKPDN_CON0
-#define MT6685_RG_INTRP_CK_PDN_MASK		0x1
-#define MT6685_RG_INTRP_CK_PDN_SHIFT		6
-#define MT6685_TOP_CKPDN_CON0_SET_ADDR		\
-	MT6685_TOP_CKPDN_CON0_SET
-#define MT6685_TOP_CKPDN_CON0_SET_MASK		0xFF
-#define MT6685_TOP_CKPDN_CON0_SET_SHIFT		0
-#define MT6685_TOP_CKPDN_CON0_CLR_ADDR		\
-	MT6685_TOP_CKPDN_CON0_CLR
-#define MT6685_TOP_CKPDN_CON0_CLR_MASK		0xFF
-#define MT6685_TOP_CKPDN_CON0_CLR_SHIFT		0
-#define MT6685_RG_FQMTR_CK_CKSEL_ADDR		\
-	MT6685_TOP_CKSEL_CON0
-#define MT6685_RG_FQMTR_CK_CKSEL_MASK		0x7
-#define MT6685_RG_FQMTR_CK_CKSEL_SHIFT		0
-#define MT6685_RG_PMU32K_CK_CKSEL_ADDR		\
-	MT6685_TOP_CKSEL_CON0
-#define MT6685_RG_PMU32K_CK_CKSEL_MASK		0x1
-#define MT6685_RG_PMU32K_CK_CKSEL_SHIFT		3
-#define MT6685_TOP_CKSEL_CON0_SET_ADDR		\
-	MT6685_TOP_CKSEL_CON0_SET
-#define MT6685_TOP_CKSEL_CON0_SET_MASK		0xFF
-#define MT6685_TOP_CKSEL_CON0_SET_SHIFT		0
-#define MT6685_TOP_CKSEL_CON0_CLR_ADDR		\
-	MT6685_TOP_CKSEL_CON0_CLR
-#define MT6685_TOP_CKSEL_CON0_CLR_MASK		0xFF
-#define MT6685_TOP_CKSEL_CON0_CLR_SHIFT		0
-#define MT6685_TOP_RST_MISC_CLR_ADDR		\
-	MT6685_TOP_RST_MISC_CLR
-#define MT6685_TOP_RST_MISC_CLR_MASK		0xFF
-#define MT6685_TOP_RST_MISC_CLR_SHIFT		0
-
-#define MT6685_RG_SEQ_OFF_ADDR		\
-	MT6685_RG_SEQ_OFF
-#define MT6685_RG_SEQ_OFF_MASK		0x1
-#define MT6685_RG_SEQ_OFF_SHIFT		0
-#define MT6685_TMA_KEY_ADDR		\
-	MT6685_TOP_TMA_KEY
-#define MT6685_TMA_KEY_MASK		0xFF
-#define MT6685_TMA_KEY_SHIFT		0
-#define MT6685_TMA_KEY_H_ADDR		\
-	MT6685_TOP_TMA_KEY_H
-#define MT6685_TMA_KEY_H_MASK		0xFF
-#define MT6685_TMA_KEY_H_SHIFT		0
-#define MT6685_DIG_WPK_KEY_ADDR		\
-	MT6685_TOP_DIG_WPK
-#define MT6685_DIG_WPK_KEY_MASK		0xFF
-#define MT6685_DIG_WPK_KEY_SHIFT	0
-#define MT6685_DIG_WPK_KEY_H_ADDR	\
-	MT6685_TOP_DIG_WPK_H
-#define MT6685_DIG_WPK_KEY_H_MASK	0xFF
-#define MT6685_DIG_WPK_KEY_H_SHIFT	0
-#define MT6685_SCK_TOP_XTAL_SEL_ADDR	\
-	MT6685_SCK_TOP_CON0_L
-#define MT6685_SCK_TOP_XTAL_SEL_MASK		0x1
-#define MT6685_SCK_TOP_XTAL_SEL_SHIFT		0
-#define MT6685_RG_RTC_SEC_MCLK_PDN_ADDR		\
-	MT6685_SCK_TOP_CKPDN_CON0_L
-#define MT6685_RG_RTC_SEC_MCLK_PDN_MASK		0x1
-#define MT6685_RG_RTC_SEC_MCLK_PDN_SHIFT	0
-#define MT6685_RG_RTC_EOSC32_CK_PDN_ADDR	\
-	MT6685_SCK_TOP_CKPDN_CON0_L
-#define MT6685_RG_RTC_EOSC32_CK_PDN_MASK	0x1
-#define MT6685_RG_RTC_EOSC32_CK_PDN_SHIFT	2
-#define MT6685_RG_RTC_SEC_32K_CK_PDN_ADDR	\
-	MT6685_SCK_TOP_CKPDN_CON0_L
-#define MT6685_RG_RTC_SEC_32K_CK_PDN_MASK	0x1
-#define MT6685_RG_RTC_SEC_32K_CK_PDN_SHIFT	3
-#define MT6685_RG_RTC_MCLK_PDN_ADDR		\
-	MT6685_SCK_TOP_CKPDN_CON0_L
-#define MT6685_RG_RTC_MCLK_PDN_MASK		0x1
-#define MT6685_RG_RTC_MCLK_PDN_SHIFT		4
-#define MT6685_RG_SHUTDOWN_SRC_SEL_ADDR		\
-	MT6685_SPMI_PWR_CMD
-#define MT6685_RG_SHUTDOWN_SRC_SEL_MASK		0x1
-#define MT6685_RG_SHUTDOWN_SRC_SEL_SHIFT	1
-#define MT6685_SCK_TOP_CKPDN_CON0_L_SET_ADDR	\
-	MT6685_SCK_TOP_CKPDN_CON0_L_SET
-#define MT6685_SCK_TOP_CKPDN_CON0_L_SET_MASK	0xFF
-#define MT6685_SCK_TOP_CKPDN_CON0_L_SET_SHIFT	0
-#define MT6685_SCK_TOP_CKPDN_CON0_L_CLR_ADDR	\
-	MT6685_SCK_TOP_CKPDN_CON0_L_CLR
-#define MT6685_SCK_TOP_CKPDN_CON0_L_CLR_MASK	0xFF
-#define MT6685_SCK_TOP_CKPDN_CON0_L_CLR_SHIFT	0
-#define MT6685_RG_BANK_FQMTR_RST_ADDR		\
-	MT6685_SCK_TOP_RST_CON0
-#define MT6685_RG_BANK_FQMTR_RST_MASK		0x1
-#define MT6685_RG_BANK_FQMTR_RST_SHIFT		6
-#define MT6685_RG_RTC_DIG_TEST_MODE_ADDR	\
-	MT6685_RTC_DIG_CON0_H
-#define MT6685_RG_RTC_DIG_TEST_MODE_MASK	0x1
-#define MT6685_RG_RTC_DIG_TEST_MODE_SHIFT	7
-#define MT6685_FQMTR_TCKSEL_ADDR		\
-	MT6685_FQMTR_CON0_L
-#define MT6685_FQMTR_TCKSEL_MASK		0x7
-#define MT6685_FQMTR_TCKSEL_SHIFT		0
-#define MT6685_FQMTR_BUSY_ADDR			\
-	MT6685_FQMTR_CON0_L
-#define MT6685_FQMTR_BUSY_MASK			0x1
-#define MT6685_FQMTR_BUSY_SHIFT			3
-#define MT6685_FQMTR_DCXO26M_EN_ADDR		\
-	MT6685_FQMTR_CON0_L
-#define MT6685_FQMTR_DCXO26M_EN_MASK		0x1
-#define MT6685_FQMTR_DCXO26M_EN_SHIFT		4
-#define MT6685_FQMTR_EN_ADDR			\
-	MT6685_FQMTR_CON0_H
-#define MT6685_FQMTR_EN_MASK			0x1
-#define MT6685_FQMTR_EN_SHIFT			7
-#define MT6685_FQMTR_WINSET_L_ADDR		\
-	MT6685_FQMTR_CON1_L
-#define MT6685_FQMTR_WINSET_L_MASK		0xFF
-#define MT6685_FQMTR_WINSET_L_SHIFT		0
-#define MT6685_FQMTR_WINSET_H_ADDR		\
-	MT6685_FQMTR_CON1_H
-#define MT6685_FQMTR_WINSET_H_MASK		0xFF
-#define MT6685_FQMTR_WINSET_H_SHIFT		0
-#define MT6685_FQMTR_DATA_L_ADDR		\
-	MT6685_FQMTR_CON2_L
-#define MT6685_FQMTR_DATA_L_MASK		0xFF
-#define MT6685_FQMTR_DATA_L_SHIFT		0
-#define MT6685_RG_RTC_32K1V8_0_SEL_ADDR		\
-	MT6685_SCK_TOP_CKSEL_CON
-#define MT6685_RG_RTC_32K1V8_0_SEL_MASK		0x3
-#define MT6685_RG_RTC_32K1V8_0_SEL_SHIFT	0
-#define MT6685_SPAR_SW_RELOAD_ADDR		\
-	MT6685_RTC_SPAR_RELOAD
-#define MT6685_SPAR_SW_RELOAD_MASK		0x1
-#define MT6685_SPAR_SW_RELOAD_SHIFT		0
-#define MT6685_RTC_ANA_ID_ADDR			\
-	MT6685_RTC_ANA_ID
-#define MT6685_RTC_ANA_ID_MASK			0xFF
-#define MT6685_RTC_ANA_ID_SHIFT			0
-#define MT6685_RTC_DIG_ID_ADDR			\
-	MT6685_RTC_DIG_ID
-#define MT6685_RTC_DIG_ID_MASK			0xFF
-#define MT6685_RTC_DIG_ID_SHIFT			0
-#define MT6685_RTC_ANA_MINOR_REV_ADDR		\
-	MT6685_RTC_ANA_REV
-#define MT6685_RTC_ANA_MINOR_REV_MASK		0xF
-#define MT6685_RTC_ANA_MINOR_REV_SHIFT		0
-#define MT6685_RTC_ANA_MAJOR_REV_ADDR		\
-	MT6685_RTC_ANA_REV
-#define MT6685_RTC_ANA_MAJOR_REV_MASK		0xF
-#define MT6685_RTC_ANA_MAJOR_REV_SHIFT		4
-#define MT6685_RTC_DIG_MINOR_REV_ADDR		\
-	MT6685_RTC_DIG_REV
-#define MT6685_RTC_DIG_MINOR_REV_MASK		0xF
-#define MT6685_RTC_DIG_MINOR_REV_SHIFT		0
-#define MT6685_RTC_DIG_MAJOR_REV_ADDR		\
-	MT6685_RTC_DIG_REV
-#define MT6685_RTC_DIG_MAJOR_REV_MASK		0xF
-#define MT6685_RTC_DIG_MAJOR_REV_SHIFT		4
-#define MT6685_RTC_CBS_ADDR			\
-	MT6685_RTC_DBI
-#define MT6685_RTC_CBS_MASK			0x3
-#define MT6685_RTC_CBS_SHIFT			0
-#define MT6685_RTC_BIX_ADDR			\
-	MT6685_RTC_DBI
-#define MT6685_RTC_BIX_MASK		0x3
-#define MT6685_RTC_BIX_SHIFT		2
-#define MT6685_RTC_ESP_ADDR		\
-	MT6685_RTC_ESP
-#define MT6685_RTC_ESP_MASK		0xFF
-#define MT6685_RTC_ESP_SHIFT		0
-#define MT6685_RTC_FPI_ADDR		\
-	MT6685_RTC_FPI
-#define MT6685_RTC_FPI_MASK		0xFF
-#define MT6685_RTC_FPI_SHIFT		0
-#define MT6685_RTC_DXI_ADDR		\
-	MT6685_RTC_DXI
-#define MT6685_RTC_DXI_MASK		0xFF
-#define MT6685_RTC_DXI_SHIFT		0
-#define MT6685_BBPU_ADDR		\
-	MT6685_RTC_BBPU_L
-#define MT6685_BBPU_MASK		0xF
-#define MT6685_BBPU_SHIFT		0
-#define MT6685_CLRPKY_ADDR		\
-	MT6685_RTC_BBPU_L
-#define MT6685_CLRPKY_MASK		0x1
-#define MT6685_CLRPKY_SHIFT		4
-#define MT6685_RELOAD_ADDR		\
-	MT6685_RTC_BBPU_L
-#define MT6685_RELOAD_MASK		0x1
-#define MT6685_RELOAD_SHIFT		5
-#define MT6685_CBUSY_ADDR		\
-	MT6685_RTC_BBPU_L
-#define MT6685_CBUSY_MASK		0x1
-#define MT6685_CBUSY_SHIFT		6
-#define MT6685_ALARM_STATUS_ADDR	\
-	MT6685_RTC_BBPU_L
-#define MT6685_ALARM_STATUS_MASK	0x1
-#define MT6685_ALARM_STATUS_SHIFT	7
-#define MT6685_KEY_BBPU_ADDR		\
-	MT6685_RTC_BBPU_H
-#define MT6685_KEY_BBPU_MASK		0xFF
-#define MT6685_KEY_BBPU_SHIFT		0
-#define MT6685_ALSTA_ADDR		\
-	MT6685_RTC_IRQ_STA
-#define MT6685_ALSTA_MASK		0x1
-#define MT6685_ALSTA_SHIFT		0
-#define MT6685_TCSTA_ADDR		\
-	MT6685_RTC_IRQ_STA
-#define MT6685_TCSTA_MASK		0x1
-#define MT6685_TCSTA_SHIFT		1
-#define MT6685_LPSTA_ADDR		\
-	MT6685_RTC_IRQ_STA
-#define MT6685_LPSTA_MASK		0x1
-#define MT6685_LPSTA_SHIFT		3
-#define MT6685_AL_EN_ADDR		\
-	MT6685_RTC_IRQ_EN
-#define MT6685_AL_EN_MASK		0x1
-#define MT6685_AL_EN_SHIFT		0
-#define MT6685_TC_EN_ADDR		\
-	MT6685_RTC_IRQ_EN
-#define MT6685_TC_EN_MASK		0x1
-#define MT6685_TC_EN_SHIFT		1
-#define MT6685_ONESHOT_ADDR		\
-	MT6685_RTC_IRQ_EN
-#define MT6685_ONESHOT_MASK		0x1
-#define MT6685_ONESHOT_SHIFT		2
-#define MT6685_LP_EN_ADDR		\
-	MT6685_RTC_IRQ_EN
-#define MT6685_LP_EN_MASK		0x1
-#define MT6685_LP_EN_SHIFT		3
-#define MT6685_SECCII_ADDR		\
-	MT6685_RTC_CII_EN_L
-#define MT6685_SECCII_MASK		0x1
-#define MT6685_SECCII_SHIFT		0
-#define MT6685_MINCII_ADDR		\
-	MT6685_RTC_CII_EN_L
-#define MT6685_MINCII_MASK		0x1
-#define MT6685_MINCII_SHIFT		1
-#define MT6685_HOUCII_ADDR		\
-	MT6685_RTC_CII_EN_L
-#define MT6685_HOUCII_MASK		0x1
-#define MT6685_HOUCII_SHIFT		2
-#define MT6685_DOMCII_ADDR		\
-	MT6685_RTC_CII_EN_L
-#define MT6685_DOMCII_MASK		0x1
-#define MT6685_DOMCII_SHIFT		3
-#define MT6685_DOWCII_ADDR		\
-	MT6685_RTC_CII_EN_L
-#define MT6685_DOWCII_MASK		0x1
-#define MT6685_DOWCII_SHIFT		4
-#define MT6685_MTHCII_ADDR		\
-	MT6685_RTC_CII_EN_L
-#define MT6685_MTHCII_MASK		0x1
-#define MT6685_MTHCII_SHIFT		5
-#define MT6685_YEACII_ADDR		\
-	MT6685_RTC_CII_EN_L
-#define MT6685_YEACII_MASK		0x1
-#define MT6685_YEACII_SHIFT		6
-#define MT6685_SECCII_1_2_ADDR		\
-	MT6685_RTC_CII_EN_L
-#define MT6685_SECCII_1_2_MASK		0x1
-#define MT6685_SECCII_1_2_SHIFT		7
-#define MT6685_SECCII_1_4_ADDR		\
-	MT6685_RTC_CII_EN_H
-#define MT6685_SECCII_1_4_MASK		0x1
-#define MT6685_SECCII_1_4_SHIFT		0
-#define MT6685_SECCII_1_8_ADDR		\
-	MT6685_RTC_CII_EN_H
-#define MT6685_SECCII_1_8_MASK		0x1
-#define MT6685_SECCII_1_8_SHIFT		1
-#define MT6685_SEC_MSK_ADDR		\
-	MT6685_RTC_AL_MASK
-#define MT6685_SEC_MSK_MASK		0x1
-#define MT6685_SEC_MSK_SHIFT		0
-#define MT6685_MIN_MSK_ADDR		\
-	MT6685_RTC_AL_MASK
-#define MT6685_MIN_MSK_MASK		0x1
-#define MT6685_MIN_MSK_SHIFT		1
-#define MT6685_HOU_MSK_ADDR		\
-	MT6685_RTC_AL_MASK
-#define MT6685_HOU_MSK_MASK		0x1
-#define MT6685_HOU_MSK_SHIFT		2
-#define MT6685_DOM_MSK_ADDR		\
-	MT6685_RTC_AL_MASK
-#define MT6685_DOM_MSK_MASK		0x1
-#define MT6685_DOM_MSK_SHIFT		3
-#define MT6685_DOW_MSK_ADDR		\
-	MT6685_RTC_AL_MASK
-#define MT6685_DOW_MSK_MASK		0x1
-#define MT6685_DOW_MSK_SHIFT		4
-#define MT6685_MTH_MSK_ADDR		\
-	MT6685_RTC_AL_MASK
-#define MT6685_MTH_MSK_MASK		0x1
-#define MT6685_MTH_MSK_SHIFT		5
-#define MT6685_YEA_MSK_ADDR		\
-	MT6685_RTC_AL_MASK
-#define MT6685_YEA_MSK_MASK		0x1
-#define MT6685_YEA_MSK_SHIFT		6
-#define MT6685_TC_SECOND_ADDR		\
-	MT6685_RTC_TC_SEC
-#define MT6685_TC_SECOND_MASK		0x3F
-#define MT6685_TC_SECOND_SHIFT		0
-#define MT6685_TC_MINUTE_ADDR		\
-	MT6685_RTC_TC_MIN
-#define MT6685_TC_MINUTE_MASK		0x3F
-#define MT6685_TC_MINUTE_SHIFT		0
-#define MT6685_TC_HOUR_ADDR		\
-	MT6685_RTC_TC_HOU
-#define MT6685_TC_HOUR_MASK		0x1F
-#define MT6685_TC_HOUR_SHIFT		0
-#define MT6685_TC_DOM_ADDR		\
-	MT6685_RTC_TC_DOM
-#define MT6685_TC_DOM_MASK		0x1F
-#define MT6685_TC_DOM_SHIFT		0
-#define MT6685_TC_DOW_ADDR		\
-	MT6685_RTC_TC_DOW
-#define MT6685_TC_DOW_MASK		0x7
-#define MT6685_TC_DOW_SHIFT		0
-#define MT6685_TC_MONTH_ADDR		\
-	MT6685_RTC_TC_MTH_L
-#define MT6685_TC_MONTH_MASK		0xF
-#define MT6685_TC_MONTH_SHIFT		0
-#define MT6685_RTC_MACRO_ID_L_ADDR	\
-	MT6685_RTC_TC_MTH_L
-#define MT6685_RTC_MACRO_ID_L_MASK	0xF
-#define MT6685_RTC_MACRO_ID_L_SHIFT	4
-#define MT6685_RTC_MACRO_ID_H_ADDR	\
-	MT6685_RTC_TC_MTH_H
-#define MT6685_RTC_MACRO_ID_H_MASK	0xFF
-#define MT6685_RTC_MACRO_ID_H_SHIFT	0
-#define MT6685_TC_YEAR_ADDR		\
-	MT6685_RTC_TC_YEA
-#define MT6685_TC_YEAR_MASK		0x7F
-#define MT6685_TC_YEAR_SHIFT		0
-#define MT6685_AL_SECOND_ADDR		\
-	MT6685_RTC_AL_SEC_L
-#define MT6685_AL_SECOND_MASK		0x3F
-#define MT6685_AL_SECOND_SHIFT		0
-#define MT6685_BBPU_AUTO_PDN_SEL_ADDR	\
-	MT6685_RTC_AL_SEC_L
-#define MT6685_BBPU_AUTO_PDN_SEL_MASK	0x1
-#define MT6685_BBPU_AUTO_PDN_SEL_SHIFT	6
-#define MT6685_BBPU_2SEC_CK_SEL_ADDR	\
-	MT6685_RTC_AL_SEC_L
-#define MT6685_BBPU_2SEC_CK_SEL_MASK	0x1
-#define MT6685_BBPU_2SEC_CK_SEL_SHIFT	7
-#define MT6685_BBPU_2SEC_EN_ADDR	\
-	MT6685_RTC_AL_SEC_H
-#define MT6685_BBPU_2SEC_EN_MASK	0x1
-#define MT6685_BBPU_2SEC_EN_SHIFT	0
-#define MT6685_BBPU_2SEC_MODE_ADDR	\
-	MT6685_RTC_AL_SEC_H
-#define MT6685_BBPU_2SEC_MODE_MASK		0x3
-#define MT6685_BBPU_2SEC_MODE_SHIFT		1
-#define MT6685_BBPU_2SEC_STAT_CLEAR_ADDR	\
-	MT6685_RTC_AL_SEC_H
-#define MT6685_BBPU_2SEC_STAT_CLEAR_MASK	0x1
-#define MT6685_BBPU_2SEC_STAT_CLEAR_SHIFT	3
-#define MT6685_BBPU_2SEC_STAT_STA_ADDR		\
-	MT6685_RTC_AL_SEC_H
-#define MT6685_BBPU_2SEC_STAT_STA_MASK		0x1
-#define MT6685_BBPU_2SEC_STAT_STA_SHIFT		4
-#define MT6685_RTC_LPD_OPT_ADDR			\
-	MT6685_RTC_AL_SEC_H
-#define MT6685_RTC_LPD_OPT_MASK			0x3
-#define MT6685_RTC_LPD_OPT_SHIFT		5
-#define MT6685_K_EOSC32_VTCXO_ON_SEL_ADDR	\
-	MT6685_RTC_AL_SEC_H
-#define MT6685_K_EOSC32_VTCXO_ON_SEL_MASK	0x1
-#define MT6685_K_EOSC32_VTCXO_ON_SEL_SHIFT	7
-
-#define MT6685_AL_MINUTE_ADDR		\
-	MT6685_RTC_AL_MIN
-#define MT6685_AL_MINUTE_MASK		0x3F
-#define MT6685_AL_MINUTE_SHIFT		0
-#define MT6685_AL_HOUR_ADDR		\
-	MT6685_RTC_AL_HOU_L
-#define MT6685_AL_HOUR_MASK		0x1F
-#define MT6685_AL_HOUR_SHIFT		0
-#define MT6685_NEW_SPARE0_ADDR		\
-	MT6685_RTC_AL_HOU_H
-#define MT6685_NEW_SPARE0_MASK		0xFF
-#define MT6685_NEW_SPARE0_SHIFT		0
-#define MT6685_AL_DOM_ADDR		\
-	MT6685_RTC_AL_DOM_L
-#define MT6685_AL_DOM_MASK		0x1F
-#define MT6685_AL_DOM_SHIFT		0
-#define MT6685_NEW_SPARE1_ADDR		\
-	MT6685_RTC_AL_DOM_H
-#define MT6685_NEW_SPARE1_MASK		0xFF
-#define MT6685_NEW_SPARE1_SHIFT		0
-#define MT6685_AL_DOW_ADDR		\
-	MT6685_RTC_AL_DOW_L
-#define MT6685_AL_DOW_MASK		0x7
-#define MT6685_AL_DOW_SHIFT		0
-#define MT6685_RG_EOSC_CALI_TD_ADDR	\
-	MT6685_RTC_AL_DOW_L
-#define MT6685_RG_EOSC_CALI_TD_MASK	0x7
-#define MT6685_RG_EOSC_CALI_TD_SHIFT	5
-#define MT6685_NEW_SPARE2_ADDR		\
-	MT6685_RTC_AL_DOW_H
-#define MT6685_NEW_SPARE2_MASK		0xFF
-#define MT6685_NEW_SPARE2_SHIFT		0
-#define MT6685_AL_MONTH_ADDR		\
-	MT6685_RTC_AL_MTH_L
-#define MT6685_AL_MONTH_MASK		0xF
-#define MT6685_AL_MONTH_SHIFT		0
-#define MT6685_NEW_SPARE3_ADDR		\
-	MT6685_RTC_AL_MTH_H
-#define MT6685_NEW_SPARE3_MASK		0xFF
-#define MT6685_NEW_SPARE3_SHIFT		0
-#define MT6685_AL_YEAR_ADDR		\
-	MT6685_RTC_AL_YEA_L
-#define MT6685_AL_YEAR_MASK		0x7F
-#define MT6685_AL_YEAR_SHIFT		0
-#define MT6685_RTC_K_EOSC_RSV_ADDR	\
-	MT6685_RTC_AL_YEA_H
-#define MT6685_RTC_K_EOSC_RSV_MASK	0xFF
-#define MT6685_RTC_K_EOSC_RSV_SHIFT	0
-#define MT6685_XOSCCALI_ADDR		\
-	MT6685_RTC_OSC32CON_L
-#define MT6685_XOSCCALI_MASK		0x1F
-#define MT6685_XOSCCALI_SHIFT		0
-#define MT6685_RTC_XOSC32_ENB_ADDR	\
-	MT6685_RTC_OSC32CON_L
-#define MT6685_RTC_XOSC32_ENB_MASK	0x1
-#define MT6685_RTC_XOSC32_ENB_SHIFT	5
-#define MT6685_RTC_EMBCK_SEL_MODE_ADDR	\
-	MT6685_RTC_OSC32CON_L
-#define MT6685_RTC_EMBCK_SEL_MODE_MASK	0x3
-#define MT6685_RTC_EMBCK_SEL_MODE_SHIFT	6
-#define MT6685_RTC_EMBCK_SRC_SEL_ADDR	\
-	MT6685_RTC_OSC32CON_H
-
-#define MT6685_RTC_EMBCK_SRC_SEL_MASK		0x1
-#define MT6685_RTC_EMBCK_SRC_SEL_SHIFT		0
-#define MT6685_RTC_EMBCK_SEL_OPTION_ADDR	\
-	MT6685_RTC_OSC32CON_H
-#define MT6685_RTC_EMBCK_SEL_OPTION_MASK	0x1
-#define MT6685_RTC_EMBCK_SEL_OPTION_SHIFT	1
-#define MT6685_RTC_GPS_CKOUT_EN_ADDR		\
-	MT6685_RTC_OSC32CON_H
-#define MT6685_RTC_GPS_CKOUT_EN_MASK		0x1
-#define MT6685_RTC_GPS_CKOUT_EN_SHIFT		2
-#define MT6685_RTC_EOSC32_VCT_EN_ADDR		\
-	MT6685_RTC_OSC32CON_H
-#define MT6685_RTC_EOSC32_VCT_EN_MASK		0x1
-#define MT6685_RTC_EOSC32_VCT_EN_SHIFT		3
-#define MT6685_RTC_EOSC32_CHOP_EN_ADDR		\
-	MT6685_RTC_OSC32CON_H
-#define MT6685_RTC_EOSC32_CHOP_EN_MASK		0x1
-#define MT6685_RTC_EOSC32_CHOP_EN_SHIFT		4
-#define MT6685_RTC_GP_OSC32_CON_ADDR		\
-	MT6685_RTC_OSC32CON_H
-#define MT6685_RTC_GP_OSC32_CON_MASK		0x3
-#define MT6685_RTC_GP_OSC32_CON_SHIFT		5
-#define MT6685_RTC_REG_XOSC32_ENB_ADDR		\
-	MT6685_RTC_OSC32CON_H
-#define MT6685_RTC_REG_XOSC32_ENB_MASK		0x1
-#define MT6685_RTC_REG_XOSC32_ENB_SHIFT		7
-#define MT6685_RTC_POWERKEY1_L_ADDR		\
-	MT6685_RTC_POWERKEY1_L
-#define MT6685_RTC_POWERKEY1_L_MASK		0xFF
-#define MT6685_RTC_POWERKEY1_L_SHIFT		0
-#define MT6685_RTC_POWERKEY1_H_ADDR		\
-	MT6685_RTC_POWERKEY1_H
-#define MT6685_RTC_POWERKEY1_H_MASK		0xFF
-#define MT6685_RTC_POWERKEY1_H_SHIFT		0
-#define MT6685_RTC_POWERKEY2_L_ADDR		\
-	MT6685_RTC_POWERKEY2_L
-#define MT6685_RTC_POWERKEY2_L_MASK		0xFF
-#define MT6685_RTC_POWERKEY2_L_SHIFT		0
-#define MT6685_RTC_POWERKEY2_H_ADDR		\
-	MT6685_RTC_POWERKEY2_H
-#define MT6685_RTC_POWERKEY2_H_MASK		0xFF
-#define MT6685_RTC_POWERKEY2_H_SHIFT		0
-#define MT6685_RTC_PDN1_L_ADDR			\
-	MT6685_RTC_PDN1_L
-#define MT6685_RTC_PDN1_L_MASK			0xFF
-#define MT6685_RTC_PDN1_L_SHIFT			0
-#define MT6685_RTC_PDN1_H_ADDR			\
-	MT6685_RTC_PDN1_H
-#define MT6685_RTC_PDN1_H_MASK			0xFF
-#define MT6685_RTC_PDN1_H_SHIFT			0
-#define MT6685_RTC_PDN2_L_ADDR			\
-	MT6685_RTC_PDN2_L
-#define MT6685_RTC_PDN2_L_MASK			0xFF
-#define MT6685_RTC_PDN2_L_SHIFT			0
-#define MT6685_RTC_PDN2_H_ADDR			\
-	MT6685_RTC_PDN2_H
-#define MT6685_RTC_PDN2_H_MASK			0xFF
-#define MT6685_RTC_PDN2_H_SHIFT			0
-#define MT6685_RTC_SPAR0_L_ADDR			\
-	MT6685_RTC_SPAR0_L
-#define MT6685_RTC_SPAR0_L_MASK			0xFF
-#define MT6685_RTC_SPAR0_L_SHIFT		0
-#define MT6685_RTC_SPAR0_H_ADDR			\
-	MT6685_RTC_SPAR0_H
-#define MT6685_RTC_SPAR0_H_MASK			0xFF
-#define MT6685_RTC_SPAR0_H_SHIFT		0
-#define MT6685_RTC_SPAR1_L_ADDR			\
-	MT6685_RTC_SPAR1_L
-#define MT6685_RTC_SPAR1_L_MASK			0xFF
-#define MT6685_RTC_SPAR1_L_SHIFT		0
-#define MT6685_RTC_SPAR1_H_ADDR			\
-	MT6685_RTC_SPAR1_H
-#define MT6685_RTC_SPAR1_H_MASK			0xFF
-#define MT6685_RTC_SPAR1_H_SHIFT		0
-#define MT6685_RTC_PROT_L_ADDR			\
-	MT6685_RTC_PROT_L
-#define MT6685_RTC_PROT_L_MASK			0xFF
-#define MT6685_RTC_PROT_L_SHIFT			0
-#define MT6685_RTC_PROT_H_ADDR			\
-	MT6685_RTC_PROT_H
-#define MT6685_RTC_PROT_H_MASK			0xFF
-#define MT6685_RTC_PROT_H_SHIFT			0
-#define MT6685_RTC_DIFF_L_ADDR			\
-	MT6685_RTC_DIFF_L
-#define MT6685_RTC_DIFF_L_MASK			0xFF
-#define MT6685_RTC_DIFF_L_SHIFT			0
-#define MT6685_RTC_DIFF_H_ADDR			\
-	MT6685_RTC_DIFF_H
-#define MT6685_RTC_DIFF_H_MASK			0xF
-#define MT6685_RTC_DIFF_H_SHIFT			0
-#define MT6685_POWER_DETECTED_ADDR		\
-	MT6685_RTC_DIFF_H
-#define MT6685_POWER_DETECTED_MASK		0x1
-#define MT6685_POWER_DETECTED_SHIFT		4
-#define MT6685_K_EOSC32_RSV_ADDR		\
-	MT6685_RTC_DIFF_H
-#define MT6685_K_EOSC32_RSV_MASK		0x1
-#define MT6685_K_EOSC32_RSV_SHIFT		6
-#define MT6685_CALI_RD_SEL_ADDR			\
-	MT6685_RTC_DIFF_H
-#define MT6685_CALI_RD_SEL_MASK			0x1
-#define MT6685_CALI_RD_SEL_SHIFT		7
-#define MT6685_RTC_CALI_L_ADDR			\
-	MT6685_RTC_CALI_L
-#define MT6685_RTC_CALI_L_MASK			0xFF
-#define MT6685_RTC_CALI_L_SHIFT			0
-#define MT6685_RTC_CALI_H_ADDR			\
-	MT6685_RTC_CALI_H
-#define MT6685_RTC_CALI_H_MASK			0x3F
-#define MT6685_RTC_CALI_H_SHIFT			0
-#define MT6685_CALI_WR_SEL_ADDR			\
-	MT6685_RTC_CALI_H
-#define MT6685_CALI_WR_SEL_MASK			0x1
-#define MT6685_CALI_WR_SEL_SHIFT		6
-#define MT6685_K_EOSC32_OVERFLOW_ADDR		\
-	MT6685_RTC_CALI_H
-#define MT6685_K_EOSC32_OVERFLOW_MASK		0x1
-#define MT6685_K_EOSC32_OVERFLOW_SHIFT		7
-#define MT6685_WRTGR_ADDR			\
-	MT6685_RTC_WRTGR
-#define MT6685_WRTGR_MASK			0x1
-#define MT6685_WRTGR_SHIFT			0
-#define MT6685_VBAT_LPSTA_RAW_ADDR		\
-	MT6685_RTC_CON_L
-#define MT6685_VBAT_LPSTA_RAW_MASK		0x1
-#define MT6685_VBAT_LPSTA_RAW_SHIFT		0
-#define MT6685_EOSC32_LPEN_ADDR			\
-	MT6685_RTC_CON_L
-#define MT6685_EOSC32_LPEN_MASK			0x1
-#define MT6685_EOSC32_LPEN_SHIFT		1
-#define MT6685_XOSC32_LPEN_ADDR			\
-	MT6685_RTC_CON_L
-#define MT6685_XOSC32_LPEN_MASK			0x1
-#define MT6685_XOSC32_LPEN_SHIFT		2
-#define MT6685_LPRST_ADDR			\
-	MT6685_RTC_CON_L
-#define MT6685_LPRST_MASK			0x1
-#define MT6685_LPRST_SHIFT			3
-#define MT6685_CDBO_ADDR			\
-	MT6685_RTC_CON_L
-
-#define MT6685_CDBO_MASK		0x1
-#define MT6685_CDBO_SHIFT		4
-#define MT6685_F32KOB_ADDR		\
-	MT6685_RTC_CON_L
-#define MT6685_F32KOB_MASK		0x1
-#define MT6685_F32KOB_SHIFT		5
-#define MT6685_GPO_ADDR			\
-	MT6685_RTC_CON_L
-#define MT6685_GPO_MASK			0x1
-#define MT6685_GPO_SHIFT		6
-#define MT6685_GOE_ADDR			\
-	MT6685_RTC_CON_L
-#define MT6685_GOE_MASK			0x1
-#define MT6685_GOE_SHIFT		7
-#define MT6685_GSR_ADDR			\
-	MT6685_RTC_CON_H
-#define MT6685_GSR_MASK			0x1
-#define MT6685_GSR_SHIFT		0
-#define MT6685_GSMT_ADDR		\
-	MT6685_RTC_CON_H
-#define MT6685_GSMT_MASK		0x1
-#define MT6685_GSMT_SHIFT		1
-#define MT6685_GPEN_ADDR		\
-	MT6685_RTC_CON_H
-#define MT6685_GPEN_MASK		0x1
-#define MT6685_GPEN_SHIFT		2
-#define MT6685_GPU_ADDR			\
-	MT6685_RTC_CON_H
-#define MT6685_GPU_MASK			0x1
-#define MT6685_GPU_SHIFT		3
-#define MT6685_GE4_ADDR			\
-	MT6685_RTC_CON_H
-#define MT6685_GE4_MASK			0x1
-#define MT6685_GE4_SHIFT		4
-#define MT6685_GE8_ADDR			\
-	MT6685_RTC_CON_H
-#define MT6685_GE8_MASK			0x1
-#define MT6685_GE8_SHIFT		5
-#define MT6685_GPI_ADDR			\
-	MT6685_RTC_CON_H
-#define MT6685_GPI_MASK			0x1
-#define MT6685_GPI_SHIFT		6
-#define MT6685_LPSTA_RAW_ADDR		\
-	MT6685_RTC_CON_H
-#define MT6685_LPSTA_RAW_MASK		0x1
-#define MT6685_LPSTA_RAW_SHIFT		7
-#define MT6685_DAT0_LOCK_ADDR		\
-	MT6685_RTC_SEC_CTRL
-#define MT6685_DAT0_LOCK_MASK		0x1
-#define MT6685_DAT0_LOCK_SHIFT		0
-#define MT6685_DAT1_LOCK_ADDR		\
-	MT6685_RTC_SEC_CTRL
-#define MT6685_DAT1_LOCK_MASK		0x1
-#define MT6685_DAT1_LOCK_SHIFT		1
-#define MT6685_DAT2_LOCK_ADDR		\
-	MT6685_RTC_SEC_CTRL
-#define MT6685_DAT2_LOCK_MASK		0x1
-#define MT6685_DAT2_LOCK_SHIFT		2
-#define MT6685_RTC_INT_CNT_L_ADDR	\
-	MT6685_RTC_INT_CNT_L
-#define MT6685_RTC_INT_CNT_L_MASK	0xFF
-#define MT6685_RTC_INT_CNT_L_SHIFT	0
-#define MT6685_RTC_INT_CNT_H_ADDR	\
-	MT6685_RTC_INT_CNT_H
-#define MT6685_RTC_INT_CNT_H_MASK	0x7F
-#define MT6685_RTC_INT_CNT_H_SHIFT	0
-#define MT6685_RTC_SEC_DAT0_L_ADDR	\
-	MT6685_RTC_SEC_DAT0_L
-#define MT6685_RTC_SEC_DAT0_L_MASK	0xFF
-#define MT6685_RTC_SEC_DAT0_L_SHIFT	0
-#define MT6685_RTC_SEC_DAT0_H_ADDR	\
-	MT6685_RTC_SEC_DAT0_H
-#define MT6685_RTC_SEC_DAT0_H_MASK	0xFF
-#define MT6685_RTC_SEC_DAT0_H_SHIFT	0
-#define MT6685_RTC_SEC_DAT1_L_ADDR	\
-	MT6685_RTC_SEC_DAT1_L
-#define MT6685_RTC_SEC_DAT1_L_MASK	0xFF
-#define MT6685_RTC_SEC_DAT1_L_SHIFT	0
-#define MT6685_RTC_SEC_DAT1_H_ADDR	\
-	MT6685_RTC_SEC_DAT1_H
-#define MT6685_RTC_SEC_DAT1_H_MASK	0xFF
-#define MT6685_RTC_SEC_DAT1_H_SHIFT	0
-#define MT6685_RTC_SEC_DAT2_L_ADDR	\
-	MT6685_RTC_SEC_DAT2_L
-#define MT6685_RTC_SEC_DAT2_L_MASK	0xFF
-#define MT6685_RTC_SEC_DAT2_L_SHIFT	0
-#define MT6685_RTC_SEC_DAT2_H_ADDR	\
-	MT6685_RTC_SEC_DAT2_H
-#define MT6685_RTC_SEC_DAT2_H_MASK	0xFF
-#define MT6685_RTC_SEC_DAT2_H_SHIFT	0
-#define MT6685_RTC_RG_FG0_ADDR		\
-	MT6685_RTC_RG_FG0
-#define MT6685_RTC_RG_FG0_MASK		0xFF
-#define MT6685_RTC_RG_FG0_SHIFT		0
-#define MT6685_RTC_RG_FG1_ADDR		\
-	MT6685_RTC_RG_FG1
-#define MT6685_RTC_RG_FG1_MASK		0xFF
-#define MT6685_RTC_RG_FG1_SHIFT		0
-#define MT6685_RTC_RG_FG2_ADDR		\
-	MT6685_RTC_RG_FG2
-#define MT6685_RTC_RG_FG2_MASK		0xFF
-#define MT6685_RTC_RG_FG2_SHIFT		0
-#define MT6685_RTC_RG_FG3_ADDR		\
-	MT6685_RTC_RG_FG3
-#define MT6685_RTC_RG_FG3_MASK		0xFF
-#define MT6685_RTC_RG_FG3_SHIFT		a
-
-#define MT6685_RTC_UVLO_WAIT_ADDR		\
-	MT6685_RTC_SPAR_MACRO
-#define MT6685_RTC_UVLO_WAIT_MASK		0x3
-#define MT6685_RTC_UVLO_WAIT_SHIFT		0
-#define MT6685_RTC_SPAR_THRE_SEL_ADDR		\
-	MT6685_RTC_SPAR_MACRO
-#define MT6685_RTC_SPAR_THRE_SEL_MASK		0x1
-#define MT6685_RTC_SPAR_THRE_SEL_SHIFT		2
-#define MT6685_RTC_SPAR_PWRKEY_MATCH_LPD_ADDR	\
-	MT6685_RTC_SPAR_MACRO
-#define MT6685_RTC_SPAR_PWRKEY_MATCH_LPD_MASK	0x1
-#define MT6685_RTC_SPAR_PWRKEY_MATCH_LPD_SHIFT	4
-#define MT6685_RTC_SPAR_PWRKEY_MATCH_ADDR	\
-	MT6685_RTC_SPAR_MACRO
-#define MT6685_RTC_SPAR_PWRKEY_MATCH_MASK	0x1
-#define MT6685_RTC_SPAR_PWRKEY_MATCH_SHIFT	5
-#define MT6685_SPAR_PROT_STAT_ADDR		\
-	MT6685_RTC_SPAR_MACRO
-#define MT6685_RTC_SPAR_PROT_STAT_MASK		0x3
-#define MT6685_RTC_SPAR_PROT_STAT_SHIFT		6
-#define MT6685_RTC_SPAR_CORE_ADDR		\
-	MT6685_RTC_SPAR_CORE
-#define MT6685_RTC_SPAR_CORE_MASK		0xFF
-#define MT6685_RTC_SPAR_CORE_SHIFT		0
-#define MT6685_RTC_RG_EOSC_CALI_ADDR		\
-	MT6685_RTC_EOSC_CALI
-#define MT6685_RTC_RG_EOSC_CALI_MASK		0x1F
-#define MT6685_RTC_RG_EOSC_CALI_SHIFT		0
-#define MT6685_RTC_SEC_ANA_ID_ADDR		\
-	MT6685_RTC_SEC_ANA_ID
-#define MT6685_RTC_SEC_ANA_ID_MASK		0xFF
-#define MT6685_RTC_SEC_ANA_ID_SHIFT		0
-#define MT6685_RTC_SEC_DIG_ID_ADDR		\
-	MT6685_RTC_SEC_DIG_ID
-#define MT6685_RTC_SEC_DIG_ID_MASK		0xFF
-#define MT6685_RTC_SEC_DIG_ID_SHIFT		0
-#define MT6685_RTC_SEC_ANA_MINOR_REV_ADDR	\
-	MT6685_RTC_SEC_ANA_REV
-#define MT6685_RTC_SEC_ANA_MINOR_REV_MASK	0xF
-#define MT6685_RTC_SEC_ANA_MINOR_REV_SHIFT	0
-#define MT6685_RTC_SEC_ANA_MAJOR_REV_ADDR	\
-	MT6685_RTC_SEC_ANA_REV
-#define MT6685_RTC_SEC_ANA_MAJOR_REV_MASK	0xF
-#define MT6685_RTC_SEC_ANA_MAJOR_REV_SHIFT	4
-#define MT6685_RTC_SEC_DIG_MINOR_REV_ADDR	\
-	MT6685_RTC_SEC_DIG_REV
-#define MT6685_RTC_SEC_DIG_MINOR_REV_MASK	0xF
-#define MT6685_RTC_SEC_DIG_MINOR_REV_SHIFT	0
-#define MT6685_RTC_SEC_DIG_MAJOR_REV_ADDR	\
-	MT6685_RTC_SEC_DIG_REV
-#define MT6685_RTC_SEC_DIG_MAJOR_REV_MASK	0xF
-#define MT6685_RTC_SEC_DIG_MAJOR_REV_SHIFT	4
-#define MT6685_RTC_SEC_CBS_ADDR			\
-	MT6685_RTC_SEC_DBI
-#define MT6685_RTC_SEC_CBS_MASK			0x3
-#define MT6685_RTC_SEC_CBS_SHIFT		0
-#define MT6685_RTC_SEC_BIX_ADDR			\
-	MT6685_RTC_SEC_DBI
-#define MT6685_RTC_SEC_BIX_MASK			0x3
-#define MT6685_RTC_SEC_BIX_SHIFT		2
-#define MT6685_RTC_SEC_ESP_ADDR			\
-	MT6685_RTC_SEC_ESP
-#define MT6685_RTC_SEC_ESP_MASK			0xFF
-#define MT6685_RTC_SEC_ESP_SHIFT		0
-#define MT6685_RTC_SEC_FPI_ADDR			\
-	MT6685_RTC_SEC_FPI
-#define MT6685_RTC_SEC_FPI_MASK			0xFF
-#define MT6685_RTC_SEC_FPI_SHIFT		0
-#define MT6685_RTC_SEC_DXI_ADDR			\
-	MT6685_RTC_SEC_DXI
-#define MT6685_RTC_SEC_DXI_MASK			0xFF
-#define MT6685_RTC_SEC_DXI_SHIFT		0
-#define MT6685_TC_SECOND_SEC_ADDR		\
-	MT6685_RTC_TC_SEC_SEC
-#define MT6685_TC_SECOND_SEC_MASK		0x3F
-#define MT6685_TC_SECOND_SEC_SHIFT		0
-#define MT6685_TC_MINUTE_SEC_ADDR		\
-	MT6685_RTC_TC_MIN_SEC
-#define MT6685_TC_MINUTE_SEC_MASK		0x3F
-#define MT6685_TC_MINUTE_SEC_SHIFT		0
-#define MT6685_TC_HOUR_SEC_ADDR			\
-	MT6685_RTC_TC_HOU_SEC
-#define MT6685_TC_HOUR_SEC_MASK			0x1F
-#define MT6685_TC_HOUR_SEC_SHIFT		0
-#define MT6685_TC_DOM_SEC_ADDR			\
-	MT6685_RTC_TC_DOM_SEC
-#define MT6685_TC_DOM_SEC_MASK			0x1F
-#define MT6685_TC_DOM_SEC_SHIFT			0
-#define MT6685_TC_DOW_SEC_ADDR			\
-	MT6685_RTC_TC_DOW_SEC
-#define MT6685_TC_DOW_SEC_MASK			0x7
-#define MT6685_TC_DOW_SEC_SHIFT			0
-#define MT6685_TC_MONTH_SEC_ADDR		\
-	MT6685_RTC_TC_MTH_SEC
-#define MT6685_TC_MONTH_SEC_MASK		0xF
-#define MT6685_TC_MONTH_SEC_SHIFT		0
-#define MT6685_TC_YEAR_SEC_ADDR			\
-	MT6685_RTC_TC_YEA_SEC
-#define MT6685_TC_YEAR_SEC_MASK			0x7F
-#define MT6685_TC_YEAR_SEC_SHIFT		0
-#define MT6685_RTC_SEC_CK_PDN_ADDR		\
-	MT6685_RTC_SEC_CK_PDN
-#define MT6685_RTC_SEC_CK_PDN_MASK		0x1
-#define MT6685_RTC_SEC_CK_PDN_SHIFT		0
-#define MT6685_RTC_SEC_WRTGR_ADDR		\
-	MT6685_RTC_SEC_WRTGR
-#define MT6685_RTC_SEC_WRTGR_MASK		0x1
-#define MT6685_RTC_SEC_WRTGR_SHIFT		0
-#define MT6685_XO_EN32K_MAN_ADDR		\
-	MT6685_DCXO_DIG_MODE_CW0
-#define MT6685_XO_EN32K_MAN_MASK		0x1
-#define MT6685_XO_EN32K_MAN_SHIFT		1
-
-#endif /* SOC_MEDIATEK_MT8196_MT6685_HW_H */
diff --git a/src/soc/mediatek/mt8196/include/soc/mt6685_rtc.h b/src/soc/mediatek/mt8196/include/soc/mt6685_rtc.h
index ddae65ee84..aa576ff38c 100644
--- a/src/soc/mediatek/mt8196/include/soc/mt6685_rtc.h
+++ b/src/soc/mediatek/mt8196/include/soc/mt6685_rtc.h
@@ -8,78 +8,144 @@
 #ifndef SOC_MEDIATEK_MT8196_MT6685_RTC_H
 #define SOC_MEDIATEK_MT8196_MT6685_RTC_H
 
-#include <commonlib/bsd/bcd.h>
-#include <console/console.h>
-#include <rtc.h>
-#include <stdbool.h>
-#include <timer.h>
+#define RG_BANK_FQMTR_RST		0x522
+#define RG_BANK_FQMTR_RST_MASK		0x1
+#define RG_BANK_FQMTR_RST_SHIFT		6
 
-/* frequency meter related */
-#define RG_BANK_FQMTR_RST		MT6685_RG_BANK_FQMTR_RST_ADDR
-#define RG_BANK_FQMTR_RST_MASK		MT6685_RG_BANK_FQMTR_RST_MASK
-#define RG_BANK_FQMTR_RST_SHIFT		MT6685_RG_BANK_FQMTR_RST_SHIFT
-#define RG_FQMTR_TCKSEL			MT6685_FQMTR_TCKSEL_ADDR
-#define RG_FQMTR_WINSET			MT6685_FQMTR_WINSET_L_ADDR
-#define RG_FQMTR_BUSY			MT6685_FQMTR_BUSY_ADDR
-#define RG_FQMTR_DCXO26M_EN		MT6685_FQMTR_DCXO26M_EN_ADDR
-#define RG_FQMTR_DCXO26M_MASK		MT6685_FQMTR_DCXO26M_EN_MASK
-#define RG_FQMTR_DCXO26M_SHIFT		MT6685_FQMTR_DCXO26M_EN_SHIFT
-#define RG_FQMTR_DATA			MT6685_FQMTR_DATA_L_ADDR
-#define RG_FQMTR_EN			MT6685_FQMTR_EN_ADDR
-#define RG_FQMTR_EN_MASK		MT6685_FQMTR_EN_MASK
-#define RG_FQMTR_EN_SHIFT		MT6685_FQMTR_EN_SHIFT
+#define TOP_DIG_WPK			0x3a8
+#define DIG_WPK_KEY_MASK		0xFF
+#define DIG_WPK_KEY_SHIFT		0
 
-#define RG_FQMTR_32K_CK_PDN_SET		MT6685_TOP_CKPDN_CON0_SET_ADDR
-#define RG_FQMTR_32K_CK_PDN_CLR		MT6685_TOP_CKPDN_CON0_CLR_ADDR
-#define RG_FQMTR_32K_CK_PDN_MASK	MT6685_RG_FQMTR_32K_CK_PDN_MASK
-#define RG_FQMTR_32K_CK_PDN_SHIFT	MT6685_RG_FQMTR_32K_CK_PDN_SHIFT
+#define TOP_DIG_WPK_H			0x3a9
+#define DIG_WPK_KEY_H_MASK		0xFF
+#define DIG_WPK_KEY_H_SHIFT		0
 
-#define RG_FQMTR_CLK_CK_PDN_SET		MT6685_TOP_CKPDN_CON0_SET_ADDR
-#define RG_FQMTR_CLK_CK_PDN_CLR		MT6685_TOP_CKPDN_CON0_CLR_ADDR
-#define RG_FQMTR_CLK_CK_PDN_MASK	MT6685_RG_FQMTR_CK_PDN_MASK
-#define RG_FQMTR_CLK_CK_PDN_SHIFT	MT6685_RG_FQMTR_CK_PDN_SHIFT
+#define RG_FQMTR_CLK_CK_PDN_CLR		0x10d
+#define RG_FQMTR_CLK_CK_PDN_MASK	0x1
+#define RG_FQMTR_CLK_CK_PDN_SHIFT	5
 
-#define RG_FQMTR_CKSEL			MT6685_RG_FQMTR_CK_CKSEL_ADDR
-#define RG_FQMTR_CKSEL_SET		MT6685_TOP_CKSEL_CON0_SET_ADDR
-#define RG_FQMTR_CKSEL_CLR		MT6685_TOP_CKSEL_CON0_CLR_ADDR
-#define RG_FQMTR_CKSEL_MASK		MT6685_RG_FQMTR_CK_CKSEL_MASK
-#define RG_FQMTR_CKSEL_SHIFT		MT6685_RG_FQMTR_CK_CKSEL_SHIFT
-#define RG_FQMTR_TCKSEL_MASK		MT6685_FQMTR_TCKSEL_MASK
-#define RG_FQMTR_TCKSEL_SHIFT		MT6685_FQMTR_TCKSEL_SHIFT
+#define RG_FQMTR_32K_CK_PDN_CLR		0x10d
+#define RG_FQMTR_32K_CK_PDN_MASK	0x1
+#define RG_FQMTR_32K_CK_PDN_SHIFT	4
 
-#define FQMTR_FIX_CLK_26M		(0 << RG_FQMTR_CKSEL_SHIFT)
-#define FQMTR_FIX_CLK_XOSC_32K_DET	(1 << RG_FQMTR_CKSEL_SHIFT)
-#define FQMTR_FIX_CLK_EOSC_32K		(2 << RG_FQMTR_CKSEL_SHIFT)
-#define FQMTR_FIX_CLK_RTC_32K		(3 << RG_FQMTR_CKSEL_SHIFT)
-#define FQMTR_FIX_CLK_SMPS_CK		(4 << RG_FQMTR_CKSEL_SHIFT)
-#define FQMTR_FIX_CLK_TCK_SEC		(5 << RG_FQMTR_CKSEL_SHIFT)
-#define FQMTR_FIX_CLK_PMU_75K		(6 << RG_FQMTR_CKSEL_SHIFT)
+#define RG_FQMTR_DCXO26M_EN		0x546
+#define RG_FQMTR_DCXO26M_MASK		0x1
+#define RG_FQMTR_DCXO26M_SHIFT		4
+
+#define RG_FQMTR_WINSET			0x548
+
+#define RG_FQMTR_TCKSEL			0x546
+#define RG_FQMTR_TCKSEL_MASK		0x7
+#define RG_FQMTR_TCKSEL_SHIFT		0
+
+#define FQMTR_DCXO26M_EN		(1 << 4)
+
+#define RG_FQMTR_EN			0x547
+#define RG_FQMTR_EN_MASK		0x1
+#define RG_FQMTR_EN_SHIFT		7
+
+#define RG_FQMTR_BUSY			0x546
+#define FQMTR_BUSY			(1 << 3)
+
+#define RG_FQMTR_DATA			0x54a
+
+#define RG_FQMTR_CLK_CK_PDN_SET		0x10c
+#define RG_FQMTR_CLK_CK_PDN_MASK	0x1
+#define RG_FQMTR_CLK_CK_PDN_SHIFT	5
+
+#define RG_FQMTR_32K_CK_PDN_SET		0x10c
+#define RG_FQMTR_32K_CK_PDN_MASK	0x1
+#define RG_FQMTR_32K_CK_PDN_SHIFT	4
+
+#define RG_FQMTR_CKSEL			0x111
+#define FQMTR_FIX_CLK_26M		0
+#define RG_FQMTR_CKSEL_MASK		0x7
+#define RG_FQMTR_CKSEL_SHIFT		0
 
-#define BANK_FQMTR_RST			BIT(6)
-#define FQMTR_EN			BIT(7)
-#define FQMTR_BUSY			BIT(3)
-#define FQMTR_DCXO26M_EN		BIT(4)
-#define FQMTR_XOSC32_CK			0
-#define FQMTR_DCXO_F32K_CK		1
-#define FQMTR_EOSC32_CK			2
-#define FQMTR_XOSC32_CK_DETECTON	3
 #define FQMTR_FQM26M_CK			4
-#define FQMTR_FQM32K_CK			5
-#define FQMTR_TEST_CK			6
-#define FQMTR_WINSET			0x0000
+#define FQMTR_DCXO_F32K_CK		1
+#define FQMTR_FIX_CLK_EOSC_32K		2
 
-#define RG_75K_32K_SEL			MT6685_TOP_CKSEL_CON0_CLR_ADDR
-#define RTC_75K_TO_32K			BIT(0)
+#define OSC32CON_ANALOG_SETTING		(RTC_GP_OSC32_CON | RTC_EOSC32_CHOP_EN | \
+					 RTC_EOSC32_VCT_EN | RTC_GPS_CKOUT_EN | \
+					 RTC_EMBCK_SEL_OPTION | RTC_EMBCK_SEL_K_EOSC)
+#define RTC_GP_OSC32_CON		(2U << (5 + 8))
+#define RTC_EOSC32_CHOP_EN		(1 << (4 + 8))
+#define RTC_EOSC32_VCT_EN		(1 << (3 + 8))
+#define RTC_EMBCK_SEL_K_EOSC		(1U << 6)
 
-#define RG_OCT1_RTC32K_1V8_0		MT6685_RG_OCT1_IO_0
+#define RTC_XOSC32_LPEN			(1 << 2)
+#define RTC_EOSC32_LPEN			(1 << 1)
+
+#define RTC_BBPU_RESET_ALARM		(1 << 3)
+#define RTC_BBPU_RESET_SPAR		(1 << 2)
+#define RTC_BBPU_SPAR_SW		(1 << 1)
+
+#define RTC_XOSC32_LPEN			(1 << 2)
+
+#define RTC_PDN1_PWRON_TIME		(1 << 7)
+
+#define RTC_WRTGR_SEC			0x618
+
+#define RG_RTC_SEC_MCLK_PDN_MASK	0x1
+#define RG_RTC_SEC_32K_CK_PDN_MASK	0x1
+#define RG_RTC_SEC_32K_CK_PDN_SHIFT	3
+
+#define RTC_SEC_CK_PDN			0x616
+#define SCK_TOP_CKPDN_CON0_L		0x514
+#define RTC_SEC_DSN_ID			0x600
+#define RTC_SEC_DSN_REV0		0x602
+
+#define RTC_TC_YEA_SEC			0x614
+#define RTC_TC_MTH_SEC			0x612
+#define RTC_TC_DOM_SEC			0x60e
+#define RTC_TC_DOW_SEC			0x610
+#define RTC_TC_HOU_SEC			0x60c
+#define RTC_TC_MIN_SEC			0x60a
+#define RTC_TC_SEC_SEC			0x608
+
+#define RTC_K_EOSC32_VTCXO_ON_SEL	(1 << (7 + 8))
+#define RTC_AL_YEA_MASK			(0x7F << 0)
+#define RTC_K_EOSC_RSV_7		(1 << 15)
+#define RTC_K_EOSC_RSV_6		(1 << 14)
+
+#define RTC_POWER_DETECTED		(1 << (4 + 8))
+
+#define RTC_K_EOSC_RSV_0		(1 << 8)
+#define RTC_K_EOSC_RSV_1		(1 << 9)
+#define RTC_K_EOSC_RSV_2		(1 << 10)
+
+#define TMA_KEY				0x39e
+#define TMA_KEY_MASK			0xFF
+#define TMA_KEY_SHIFT			0
+#define TMA_KEY_H			0x39f
+#define	TMA_KEY_H_MASK			0xFF
+#define TMA_KEY_H_SHIFT			0
+
+#define RG_OCT1_RTC32K_1V8_0		0xa7
 #define RG_OCT1_RTC32K_1V8_0_MASK	0x3
 #define RG_OCT1_RTC32K_1V8_0_SHIFT	5
 
-#define RG_OCT1_RTC32K_1V8_F		MT6685_RG_OCT1_IO_1
+#define RG_OCT1_RTC32K_1V8_F		0xa8
 #define RG_OCT1_RTC32K_1V8_F_MASK	0x3
 #define RG_OCT1_RTC32K_1V8_F_SHIFT	1
 
-#define HWCID_L				MT6685_HWCID_L
+#define SCK_TOP_CKSEL_CON		0x568
+#define R_SCK32K_CK_MASK		0x1
+#define R_SCK32K_CK_SHIFT		0
+
+#define SCK_TOP_CKPDN_CON0_L_SET	0x515
+#define RG_RTC_EOSC32_CK_PDN_MASK	0x1
+#define RG_RTC_EOSC32_CK_PDN_SHIFT	2
+
+#define RTC_TC_MTH_MASK			0xF
+
+#define SCK_TOP_CKPDN_CON0_L_CLR	0x516
+#define SCK_TOP_CKPDN_CON0_L_CLR_SHIFT	0
+
+#define SCK_TOP_XTAL_SEL_ADDR		0x50c
+#define SCK_TOP_XTAL_SEL_MASK		0x1
+#define SCK_TOP_XTAL_SEL_SHIFT		0
 
 /* Complete the RTC initialization process and register settings. */
 void rtc_boot(void);
diff --git a/src/soc/mediatek/mt8196/include/soc/mt6685_rtc_hw.h b/src/soc/mediatek/mt8196/include/soc/mt6685_rtc_hw.h
deleted file mode 100644
index d2152c8703..0000000000
--- a/src/soc/mediatek/mt8196/include/soc/mt6685_rtc_hw.h
+++ /dev/null
@@ -1,372 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only OR MIT */
-
-/*
- * This file is created based on MT8196 Functional Specification
- * Chapter number: 14.2.4
- */
-
-#ifndef SOC_MEDIATEK_MT8196_MT6685_RTC_HW_H
-#define SOC_MEDIATEK_MT8196_MT6685_RTC_HW_H
-
-#include <soc/mt6685_hw.h>
-#include <soc/rtc.h>
-
-/* RTC_BBPU bit field */
-#define MT6685_PWREN_SHIFT		0
-#define MT6685_PWREN_MASK		0x1
-#define MT6685_SPAR_SW_SHIFT		1
-#define MT6685_SPAR_SW_MASK		0x1
-#define MT6685_RESET_SPAR_SHIFT		2
-#define MT6685_RESET_SPAR_MASK		0x1
-#define MT6685_RESET_ALARM_SHIFT	3
-#define MT6685_RESET_ALARM_MASK		0x1
-
-/* RTC registers */
-#define RTC_BBPU			MT6685_BBPU_ADDR
-#define RTC_BBPU_PWREN			(MT6685_PWREN_MASK << MT6685_PWREN_SHIFT)
-#define RTC_BBPU_SPAR_SW		(MT6685_SPAR_SW_MASK << MT6685_SPAR_SW_SHIFT)
-#define RTC_BBPU_RESET_SPAR		(MT6685_RESET_SPAR_MASK << MT6685_RESET_SPAR_SHIFT)
-#define RTC_BBPU_RESET_ALARM		(MT6685_RESET_ALARM_MASK << MT6685_RESET_ALARM_SHIFT)
-#define RTC_BBPU_CLRPKY			(MT6685_CLRPKY_MASK << MT6685_CLRPKY_SHIFT)
-#define RTC_BBPU_RELOAD			(MT6685_RELOAD_MASK << MT6685_RELOAD_SHIFT)
-#define RTC_BBPU_CBUSY			(MT6685_CBUSY_MASK << MT6685_CBUSY_SHIFT)
-#define RTC_BBPU_ALARM_STATUS		(MT6685_ALARM_STATUS_MASK << MT6685_ALARM_STATUS_SHIFT)
-#define RTC_BBPU_KEY			(0x43 << (MT6685_KEY_BBPU_SHIFT + 8))
-
-#define RTC_IRQ_STA			MT6685_ALSTA_ADDR
-#define RTC_IRQ_STA_AL			(MT6685_ALSTA_MASK << MT6685_ALSTA_SHIFT)
-#define RTC_IRQ_STA_TC			(MT6685_TCSTA_MASK << MT6685_TCSTA_SHIFT)
-#define RTC_IRQ_STA_LP			(MT6685_LPSTA_MASK << MT6685_LPSTA_SHIFT)
-
-#define RTC_IRQ_EN			MT6685_AL_EN_ADDR
-#define RTC_IRQ_EN_AL			(MT6685_AL_EN_MASK << MT6685_AL_EN_SHIFT)
-#define RTC_IRQ_EN_TC			(MT6685_TC_EN_MASK << MT6685_TC_EN_SHIFT)
-#define RTC_IRQ_EN_ONESHOT		(MT6685_ONESHOT_MASK << MT6685_ONESHOT_SHIFT)
-#define RTC_IRQ_EN_LP			(MT6685_LP_EN_MASK << MT6685_LP_EN_SHIFT)
-#define RTC_IRQ_EN_ONESHOT_AL		(RTC_IRQ_EN_ONESHOT | RTC_IRQ_EN_AL)
-
-#define RTC_CII_EN			MT6685_SECCII_ADDR
-#define RTC_CII_SEC			(MT6685_SECCII_MASK << MT6685_SECCII_SHIFT)
-#define RTC_CII_MIN			(MT6685_MINCII_MASK << MT6685_MINCII_SHIFT)
-#define RTC_CII_HOU			(MT6685_HOUCII_MASK << MT6685_HOUCII_SHIFT)
-#define RTC_CII_DOM			(MT6685_DOMCII_MASK << MT6685_DOMCII_SHIFT)
-#define RTC_CII_DOW			(MT6685_DOWCII_MASK << MT6685_DOWCII_SHIFT)
-#define RTC_CII_MTH			(MT6685_MTHCII_MASK << MT6685_MTHCII_SHIFT)
-#define RTC_CII_YEA			(MT6685_YEACII_MASK << MT6685_YEACII_SHIFT)
-#define RTC_CII_1_2_SEC			(MT6685_SECCII_1_2_MASK << MT6685_SECCII_1_2_SHIFT)
-#define RTC_CII_1_4_SEC			(MT6685_SECCII_1_4_MASK << (MT6685_SECCII_1_4_SHIFT + 8))
-#define RTC_CII_1_8_SEC			(MT6685_SECCII_1_8_MASK << (MT6685_SECCII_1_8_SHIFT + 8))
-
-#define RTC_AL_MASK			MT6685_SEC_MSK_ADDR
-#define RTC_AL_MASK_SEC			(MT6685_SEC_MSK_MASK << MT6685_SEC_MSK_SHIFT)
-#define RTC_AL_MASK_MIN			(MT6685_MIN_MSK_MASK << MT6685_MIN_MSK_SHIFT)
-#define RTC_AL_MASK_HOU			(MT6685_HOU_MSK_MASK << MT6685_HOU_MSK_SHIFT)
-#define RTC_AL_MASK_DOM			(MT6685_DOM_MSK_MASK << MT6685_DOM_MSK_SHIFT)
-#define RTC_AL_MASK_DOW			(MT6685_DOW_MSK_MASK << MT6685_DOW_MSK_SHIFT)
-#define RTC_AL_MASK_MTH			(MT6685_MTH_MSK_MASK << MT6685_MTH_MSK_SHIFT)
-#define RTC_AL_MASK_YEA			(MT6685_YEA_MSK_MASK << MT6685_YEA_MSK_SHIFT)
-
-#define RTC_TC_SEC			MT6685_TC_SECOND_ADDR
-#define RTC_TC_SEC_MASK			MT6685_TC_SECOND_MASK
-#define RTC_TC_MIN			MT6685_TC_MINUTE_ADDR
-#define RTC_TC_MIN_MASK			MT6685_TC_MINUTE_MASK
-#define RTC_TC_HOU			MT6685_TC_HOUR_ADDR
-#define RTC_TC_HOU_MASK			MT6685_TC_HOUR_MASK
-#define RTC_TC_DOM			MT6685_TC_DOM_ADDR
-#define RTC_TC_DOM_MASK			MT6685_TC_DOM_MASK
-#define RTC_TC_DOW			MT6685_TC_DOW_ADDR
-#define RTC_TC_DOW_MASK			MT6685_TC_DOW_MASK
-#define RTC_TC_MTH			MT6685_TC_MONTH_ADDR
-#define RTC_TC_MTH_MASK			MT6685_TC_MONTH_MASK
-#define RTC_TC_YEA			MT6685_TC_YEAR_ADDR
-#define RTC_TC_YEA_MASK			MT6685_TC_YEAR_MASK
-#define RTC_AL_SEC			MT6685_AL_SECOND_ADDR
-#define RTC_AL_SEC_MASK			MT6685_AL_SECOND_MASK
-
-#define RTC_BBPU_AUTO_PDN_SEL		(MT6685_BBPU_AUTO_PDN_SEL_MASK << MT6685_BBPU_AUTO_PDN_SEL_SHIFT)
-#define RTC_BBPU_2SEC_CK_SEL		(MT6685_BBPU_2SEC_CK_SEL_MASK << MT6685_BBPU_2SEC_CK_SEL_SHIFT)
-#define RTC_BBPU_2SEC_EN		(MT6685_BBPU_2SEC_EN_MASK << (MT6685_BBPU_2SEC_EN_SHIFT + 8))
-#define RTC_BBPU_2SEC_MODE		(MT6685_BBPU_2SEC_MODE_MASK << (MT6685_BBPU_2SEC_MODE_SHIFT + 8))
-/* RTC masks include shift */
-#define RTC_BBPU_2SEC_MODE_MSK		(MT6685_BBPU_2SEC_MODE_MASK << (MT6685_BBPU_2SEC_MODE_SHIFT + 8))
-#define RTC_BBPU_2SEC_MODE_SHIFT	(MT6685_BBPU_2SEC_MODE_SHIFT + 8)
-#define RTC_BBPU_2SEC_STAT_CLEAR        (MT6685_BBPU_2SEC_STAT_CLEAR_MASK << (MT6685_BBPU_2SEC_STAT_CLEAR_SHIFT + 8))
-#define RTC_BBPU_2SEC_STAT_STA          (MT6685_BBPU_2SEC_STAT_STA_MASK << (MT6685_BBPU_2SEC_STAT_STA_SHIFT + 8))
-#define RTC_LPD_OPT_SHIFT		(MT6685_RTC_LPD_OPT_SHIFT + 8)
-#define RTC_LPD_OPT_MASK		(MT6685_RTC_LPD_OPT_MASK << (MT6685_RTC_LPD_OPT_SHIFT + 8))
-#define RTC_LPD_OPT_XOSC_AND_EOSC_LPD	(0U << (MT6685_RTC_LPD_OPT_SHIFT + 8))
-#define RTC_LPD_OPT_EOSC_LPD		(1U << (MT6685_RTC_LPD_OPT_SHIFT + 8))
-#define RTC_LPD_OPT_XOSC_LPD		(2U << (MT6685_RTC_LPD_OPT_SHIFT + 8))
-#define RTC_LPD_OPT_F32K_CK_ALIVE	(3U << (MT6685_RTC_LPD_OPT_SHIFT + 8))
-#define RTC_K_EOSC32_VTCXO_ON_SEL	(MT6685_K_EOSC32_VTCXO_ON_SEL_MASK << (MT6685_K_EOSC32_VTCXO_ON_SEL_SHIFT + 8))
-
-#define RTC_AL_MIN			MT6685_AL_MINUTE_ADDR
-#define RTC_AL_MIN_MASK			(MT6685_AL_MINUTE_MASK << MT6685_AL_MINUTE_SHIFT)
-
-/*
- * RTC_NEW_SPARE0: RTC_AL_HOU bit0~4
- * bit 8 ~ 15 : For design used, can't be overwritten.
- */
-#define RTC_AL_HOU			MT6685_AL_HOUR_ADDR
-#define RTC_AL_HOU_MASK			(MT6685_AL_HOUR_MASK << MT6685_AL_HOUR_SHIFT)
-#define RTC_NEW_SPARE0			(MT6685_NEW_SPARE0_MASK << (MT6685_NEW_SPARE0_SHIFT + 8))
-#define RTC_AL_HOU_FG_SHIFT		8
-#define RTC_AL_HOU_FG_MASK		0xff00
-
-/*
- * RTC_NEW_SPARE1: RTC_AL_DOM bit0~4
- * bit 8 ~ 15 : for 2 second reboot desing used,
- *              can't be overwritten.
- */
-#define RTC_AL_DOM			MT6685_AL_DOM_ADDR
-#define RTC_AL_DOM_MASK			(MT6685_AL_DOM_MASK << MT6685_AL_DOM_SHIFT)
-#define RTC_NEW_SPARE1			(MT6685_NEW_SPARE1_MASK << (MT6685_NEW_SPARE1_SHIFT + 8))
-#define RTC_SPAR_CONDITION		BIT(8)	/* by uvlo */
-#define RTC_AUTOMATICALLY_SPAR		BIT(9)	/* clear by sw */
-#define RTC_ALARM_CLEAR_METHOD		BIT(11)	/* by sw */
-
-/*
- * RTC_NEW_SPARE2: RTC_AL_DOW bit0~2
- * bit 8 ~ 15 : reserved bits
- */
-#define RTC_AL_DOW			MT6685_AL_DOW_ADDR
-#define RTC_AL_DOW_MASK			(MT6685_AL_DOW_MASK << MT6685_AL_DOW_SHIFT)
-#define RTC_RG_EOSC_CALI_TD_1SEC	(3 << (MT6685_NEW_SPARE2_SHIFT + 8))
-#define RTC_RG_EOSC_CALI_TD_2SEC	(4 << (MT6685_NEW_SPARE2_SHIFT + 8))
-#define RTC_RG_EOSC_CALI_TD_4SEC	(5 << (MT6685_NEW_SPARE2_SHIFT + 8))
-#define RTC_RG_EOSC_CALI_TD_8SEC	(6 << (MT6685_NEW_SPARE2_SHIFT + 8))
-#define RTC_RG_EOSC_CALI_TD_16SEC	(7 << (MT6685_NEW_SPARE2_SHIFT + 8))
-#define RTC_RG_EOSC_CALI_TD_MASK	(0x7 << (MT6685_NEW_SPARE2_SHIFT + 8))
-#define RTC_NEW_SPARE2			(MT6685_NEW_SPARE2_MASK << (MT6685_NEW_SPARE2_SHIFT + 8))
-
-/*
- * RTC_NEW_SPARE3: RTC_AL_MTH bit0~3
- * bit 8 ~ 15 : Fuel Gauge
- */
-#define RTC_AL_MTH			MT6685_AL_MONTH_ADDR
-#define RTC_AL_MTH_MASK			(MT6685_AL_MONTH_MASK << MT6685_AL_MONTH_SHIFT)
-#define RTC_NEW_SPARE3			(MT6685_NEW_SPARE3_MASK << (MT6685_NEW_SPARE3_SHIFT + 8))
-#define RTC_AL_MTH_FG_SHIFT		8
-#define RTC_AL_MTH_FG_MASK		0xff00
-
-#define RTC_AL_YEA			MT6685_AL_YEAR_ADDR
-#define RTC_AL_YEA_MASK			(MT6685_AL_YEAR_MASK << MT6685_AL_YEAR_SHIFT)
-#define RTC_K_EOSC_RSV_0		BIT(8)
-#define RTC_K_EOSC_RSV_1		BIT(9)
-#define RTC_K_EOSC_RSV_2		BIT(10)
-#define RTC_K_EOSC_RSV_3		BIT(11)
-#define RTC_K_EOSC_RSV_4		BIT(12)
-#define RTC_K_EOSC_RSV_5		BIT(13)
-#define RTC_K_EOSC_RSV_6		BIT(14)
-#define RTC_K_EOSC_RSV_7		BIT(15)
-
-#define RTC_OSC32CON			MT6685_XOSCCALI_ADDR
-#define RTC_OSC32CON_UNLOCK1		0x1a57
-#define RTC_OSC32CON_UNLOCK2		0x2b68
-
-/* Default 4'b0111, 2nd step suggest to set to 4'b0000 EOSC_CALI = charging cap calibration */
-#define RTC_XOSCCALI_MASK		(MT6685_XOSCCALI_MASK << MT6685_XOSCCALI_SHIFT)
-
-/* 0 (32k crystal exist)	1 (32k crystal doesn't exist)*/
-#define RTC_XOSC32_ENB			(MT6685_RTC_XOSC32_ENB_MASK << MT6685_RTC_XOSC32_ENB_SHIFT)
-#define RTC_EMBCK_SEL_MODE		(MT6685_RTC_EMBCK_SEL_MODE_MASK << MT6685_RTC_EMBCK_SEL_MODE_SHIFT)
-#define RTC_EMBCK_SRC_SEL		(MT6685_RTC_EMBCK_SRC_SEL_MASK << (MT6685_RTC_EMBCK_SRC_SEL_SHIFT + 8))
-#define RTC_EMBCK_SEL_OPTION		(MT6685_RTC_EMBCK_SEL_OPTION_MASK << (MT6685_RTC_EMBCK_SEL_OPTION_SHIFT + 8))
-#define RTC_GPS_CKOUT_EN		(MT6685_RTC_GPS_CKOUT_EN_MASK << (MT6685_RTC_GPS_CKOUT_EN_SHIFT + 8))
-#define RTC_EOSC32_VCT_EN		(MT6685_RTC_EOSC32_VCT_EN_MASK << (MT6685_RTC_EOSC32_VCT_EN_SHIFT + 8))
-#define RTC_EOSC32_CHOP_EN		(MT6685_RTC_EOSC32_CHOP_EN_MASK << (MT6685_RTC_EOSC32_CHOP_EN_SHIFT + 8))
-
-/* Keep RG_EOSC_RSV[0] to low for lower EOSC leakage current hardware design change. */
-#define RTC_GP_OSC32_CON		(2U << (MT6685_RTC_GP_OSC32_CON_SHIFT + 8))
-#define RTC_REG_XOSC32_ENB		(MT6685_RTC_REG_XOSC32_ENB_MASK << (MT6685_RTC_REG_XOSC32_ENB_SHIFT + 8))
-
-/* 0: emb_hw	1: emb_k_eosc_32		2:dcxo_ck	3: eosc32_ck*/
-#define RTC_EMBCK_SEL_HW		(0 << MT6685_RTC_EMBCK_SEL_MODE_SHIFT)
-#define RTC_EMBCK_SEL_K_EOSC		(1U << MT6685_RTC_EMBCK_SEL_MODE_SHIFT)
-#define RTC_EMBCK_SEL_DCXO		(2U << MT6685_RTC_EMBCK_SEL_MODE_SHIFT)
-#define RTC_EMBCK_SEL_EOSC		(3U << MT6685_RTC_EMBCK_SEL_MODE_SHIFT)
-
-#define OSC32CON_ANALOG_SETTING		(RTC_GP_OSC32_CON | RTC_EOSC32_CHOP_EN | \
-					RTC_EOSC32_VCT_EN | RTC_GPS_CKOUT_EN | \
-					RTC_EMBCK_SEL_OPTION | RTC_EMBCK_SEL_K_EOSC)
-
-#define RTC_XOSCCALI_START		0x0000
-#define RTC_XOSCCALI_END		0x001f
-
-#define RTC_POWERKEY1			MT6685_RTC_POWERKEY1_L_ADDR
-#define RTC_POWERKEY2			MT6685_RTC_POWERKEY2_L_ADDR
-#define RTC_POWERKEY1_KEY		0xa357
-#define RTC_POWERKEY2_KEY		0x67d2
-
-#define RTC_PDN1			MT6685_RTC_PDN1_L_ADDR
-#define RTC_PDN1_RECOVERY_MASK		0x0030
-#define RTC_PDN1_FAC_RESET		BIT(4)
-#define RTC_PDN1_BYPASS_PWR		BIT(6)
-#define RTC_PDN1_PWRON_TIME		BIT(7)
-#define RTC_PDN1_FAST_BOOT		BIT(13)
-#define RTC_PDN1_KPOC			BIT(14)
-#define RTC_PDN1_DEBUG			BIT(15)
-
-#define RTC_PDN2			MT6685_RTC_PDN2_L_ADDR
-#define RTC_PDN2_PWRON_MTH_MASK		0x000f
-#define RTC_PDN2_PWRON_MTH_SHIFT	0
-#define RTC_PDN2_PWRON_ALARM		BIT(4)
-#define RTC_PDN2_PWRON_YEA_MASK		0x7f00
-#define RTC_PDN2_AUTOBOOT		BIT(7)
-#define RTC_PDN2_PWRON_YEA_SHIFT	8
-#define RTC_PDN2_PWRON_LOGO		BIT(15)
-
-#define RTC_SPAR0			MT6685_RTC_SPAR0_L_ADDR
-#define RTC_SPAR0_PWRON_SEC_MASK	0x003f
-#define RTC_SPAR0_PWRON_SEC_SHIFT	0
-#define RTC_SPAR0_32K_LESS		BIT(6)
-
-#define RTC_SPAR1			MT6685_RTC_SPAR1_L_ADDR
-#define RTC_SPAR1_PWRON_MIN_MASK	0x003f
-#define RTC_SPAR1_PWRON_MIN_SHIFT	0
-#define RTC_SPAR1_PWRON_HOU_MASK	0x07c0
-#define RTC_SPAR1_PWRON_HOU_SHIFT	6
-#define RTC_SPAR1_PWRON_DOM_MASK	0xf800
-#define RTC_SPAR1_PWRON_DOM_SHIFT	11
-
-#define RTC_PROT			MT6685_RTC_PROT_L_ADDR
-#define RTC_PROT_UNLOCK1		0x586a
-#define RTC_PROT_UNLOCK2		0x9136
-#define RTC_PROT_UNLOCK_SUCCESS		0x3
-
-#define RTC_DIFF			MT6685_RTC_DIFF_L_ADDR
-#define RTC_POWER_DETECTED		(MT6685_POWER_DETECTED_MASK << (MT6685_POWER_DETECTED_SHIFT + 8))
-#define RTC_K_EOSC32_RSV		(MT6685_K_EOSC32_RSV_MASK << (MT6685_K_EOSC32_RSV_SHIFT + 8))
-#define RTC_CALI_RD_SEL_SHIFT		(MT6685_CALI_RD_SEL_SHIFT + 8)
-#define RTC_CALI_RD_SEL			(MT6685_CALI_RD_SEL_MASK << (MT6685_CALI_RD_SEL_SHIFT + 8))
-
-#define RTC_CALI			MT6685_RTC_CALI_L_ADDR
-#define RTC_CALI_MASK			(MT6685_RTC_CALI_H_MASK << (MT6685_RTC_CALI_H_SHIFT + 8) | \
-					 MT6685_RTC_CALI_L_MASK << MT6685_RTC_CALI_L_SHIFT)
-
-#define RTC_CALI_WR_SEL			(MT6685_CALI_WR_SEL_MASK << (MT6685_CALI_WR_SEL_SHIFT + 8))
-#define RTC_CALI_WR_SEL_SHIFT		(MT6685_CALI_WR_SEL_SHIFT + 8)
-#define RTC_K_EOSC32_OVERFLOW		(MT6685_K_EOSC32_OVERFLOW_MASK << (MT6685_K_EOSC32_OVERFLOW_SHIFT + 8))
-
-#define RTC_WRTGR			MT6685_WRTGR_ADDR
-
-#define RTC_CON				MT6685_VBAT_LPSTA_RAW_ADDR
-#define RTC_VBAT_LPSTA_RAW		(MT6685_VBAT_LPSTA_RAW_MASK << MT6685_VBAT_LPSTA_RAW_SHIFT)
-#define RTC_EOSC32_LPEN			(MT6685_EOSC32_LPEN_MASK << MT6685_EOSC32_LPEN_SHIFT)
-#define RTC_XOSC32_LPEN			(MT6685_XOSC32_LPEN_MASK << MT6685_XOSC32_LPEN_SHIFT)
-#define RTC_CON_LPRST			(MT6685_LPRST_MASK << MT6685_LPRST_SHIFT)
-#define RTC_CON_CDBO			(MT6685_CDBO_MASK << MT6685_CDBO_SHIFT)
-/* 0: RTC_GPIO exports 32K */
-#define RTC_CON_F32KOB			(MT6685_F32KOB_MASK << MT6685_F32KOB_SHIFT)
-#define RTC_CON_GPO			(MT6685_GPO_MASK << MT6685_GPO_SHIFT)
-/* 1: GPO mode, 0: GPI mode */
-#define RTC_CON_GOE			(MT6685_GOE_MASK << MT6685_GOE_SHIFT)
-#define RTC_CON_GSR			(MT6685_GSR_MASK << (MT6685_GSR_SHIFT + 8))
-#define RTC_CON_GSMT			(MT6685_GSMT_MASK << (MT6685_GSMT_SHIFT + 8))
-#define RTC_CON_GPEN			(MT6685_GPEN_MASK << (MT6685_GPEN_SHIFT + 8))
-#define RTC_CON_GPU			(MT6685_GPU_MASK << (MT6685_GPU_SHIFT + 8))
-#define RTC_CON_GE4			(MT6685_GE4_MASK << (MT6685_GE4_SHIFT + 8))
-#define RTC_CON_GE8			(MT6685_GE8_MASK << (MT6685_GE8_SHIFT + 8))
-#define RTC_CON_GPI			(MT6685_GPI_MASK << (MT6685_GPI_SHIFT + 8))
-/* 32K was stopped */
-#define RTC_CON_LPSTA_RAW		(MT6685_LPSTA_RAW_MASK << (MT6685_LPSTA_RAW_SHIFT + 8))
-
-#define RTC_INT_CNT			MT6685_RTC_INT_CNT_L_ADDR
-
-#define SCK_TOP_CKPDN_CON0_L_SET	MT6685_SCK_TOP_CKPDN_CON0_L_SET_ADDR
-#define RG_RTC_EOSC32_CK_PDN_MASK	MT6685_RG_RTC_EOSC32_CK_PDN_MASK
-#define RG_RTC_EOSC32_CK_PDN_SHIFT	MT6685_RG_RTC_EOSC32_CK_PDN_SHIFT
-
-#define SCK_TOP_CKPDN_CON0_L_CLR	MT6685_SCK_TOP_CKPDN_CON0_L_CLR_ADDR
-#define SCK_TOP_CKPDN_CON0_L_CLR_SHIFT	MT6685_SCK_TOP_CKPDN_CON0_L_CLR_SHIFT
-
-#define SCK_TOP_CKPDN_CON0_L		MT6685_SCK_TOP_CKPDN_CON0_L
-#define RG_RTC_SEC_MCLK_PDN_MASK	MT6685_RG_RTC_SEC_MCLK_PDN_MASK
-#define RG_RTC_SEC_32K_CK_PDN_MASK	MT6685_RG_RTC_SEC_32K_CK_PDN_MASK
-#define RG_RTC_SEC_32K_CK_PDN_SHIFT	MT6685_RG_RTC_SEC_32K_CK_PDN_SHIFT
-
-#define SCK_TOP_XTAL_SEL_ADDR		MT6685_SCK_TOP_XTAL_SEL_ADDR
-#define SCK_TOP_XTAL_SEL_MASK		MT6685_SCK_TOP_XTAL_SEL_MASK
-#define SCK_TOP_XTAL_SEL_SHIFT		MT6685_SCK_TOP_XTAL_SEL_SHIFT
-
-#define TOP_RST_MISC_CLR		MT6685_TOP_RST_MISC_CLR_ADDR
-#define TOP_RST_MISC_CLR_MASK		MT6685_TOP_RST_MISC_CLR_MASK
-#define TOP_RST_MISC_CLR_SHIFT		MT6685_TOP_RST_MISC_CLR_SHIFT
-
-#define TMA_KEY				MT6685_TMA_KEY_ADDR
-#define TMA_KEY_MASK			MT6685_TMA_KEY_MASK
-#define TMA_KEY_SHIFT			MT6685_TMA_KEY_SHIFT
-
-#define TMA_KEY_H			MT6685_TMA_KEY_H_ADDR
-#define TMA_KEY_H_MASK			MT6685_TMA_KEY_H_MASK
-#define TMA_KEY_H_SHIFT			MT6685_TMA_KEY_H_SHIFT
-
-#define TOP_DIG_WPK			MT6685_TOP_DIG_WPK
-#define DIG_WPK_KEY_MASK		MT6685_DIG_WPK_KEY_MASK
-#define DIG_WPK_KEY_SHIFT		MT6685_DIG_WPK_KEY_SHIFT
-
-#define TOP_DIG_WPK_H			MT6685_TOP_DIG_WPK_H
-#define DIG_WPK_KEY_H_MASK		MT6685_DIG_WPK_KEY_H_MASK
-#define DIG_WPK_KEY_H_SHIFT		MT6685_DIG_WPK_KEY_H_SHIFT
-
-#define RG_RTC_MCLK_PDN_SET		MT6685_SCK_TOP_CKPDN_CON0_L_SET
-#define RG_RTC_MCLK_PDN_CLR		MT6685_SCK_TOP_CKPDN_CON0_L_CLR
-#define RG_RTC_MCLK_PDN_MASK		MT6685_RG_RTC_MCLK_PDN_MASK
-#define RG_RTC_MCLK_PDN_SHIFT		MT6685_RG_RTC_MCLK_PDN_SHIFT
-
-#define RG_SHUTDOWN_SRC_SEL		MT6685_RG_SHUTDOWN_SRC_SEL_ADDR
-#define RG_SHUTDOWN_SRC_SEL_MASK	MT6685_RG_SHUTDOWN_SRC_SEL_MASK
-#define RG_SHUTDOWN_SRC_SEL_SHIFT	MT6685_RG_SHUTDOWN_SRC_SEL_SHIFT
-
-#define RG_SRCLKEN_IN0_HW_MODE		MT6685_TOP_CON
-#define RG_SRCLKEN_IN0_HW_MODE_MASK	MT6685_RG_SRCLKEN_IN0_HW_MODE_MASK
-#define RG_SRCLKEN_IN0_HW_MODE_SHIFT	MT6685_RG_SRCLKEN_IN0_HW_MODE_SHIFT
-
-#define RG_SRCLKEN_IN1_HW_MODE		MT6685_TOP_CON
-#define RG_SRCLKEN_IN1_HW_MODE_MASK	MT6685_RG_SRCLKEN_IN1_HW_MODE_MASK
-#define RG_SRCLKEN_IN1_HW_MODE_SHIFT	MT6685_RG_SRCLKEN_IN1_HW_MODE_SHIFT
-
-#define RG_RTC_EOSC32_CK_PDN		MT6685_SCK_TOP_CKPDN_CON0_L
-#define RG_RTC_EOSC32_CK_PDN_MASK	MT6685_RG_RTC_EOSC32_CK_PDN_MASK
-#define RG_RTC_EOSC32_CK_PDN_SHIFT	MT6685_RG_RTC_EOSC32_CK_PDN_SHIFT
-
-#define XO_EN32K_MAN_ADDR		MT6685_DCXO_DIG_MODE_CW0
-#define XO_EN32K_MAN_MASK		MT6685_XO_EN32K_MAN_MASK
-#define XO_EN32K_MAN_SHIFT		MT6685_XO_EN32K_MAN_SHIFT
-
-#define SCK_TOP_CKSEL_CON		MT6685_SCK_TOP_CKSEL_CON
-#define R_SCK32K_CK_MASK		0x1
-#define R_SCK32K_CK_SHIFT		0
-
-#define RTC_SPAR_MACRO			MT6685_RTC_SPAR_MACRO
-#define SPAR_THRE_SEL			(MT6685_RTC_SPAR_THRE_SEL_MASK << MT6685_RTC_SPAR_THRE_SEL_SHIFT)
-#define SPAR_UVLO_WAIT_SHIFT		MT6685_RTC_UVLO_WAIT_SHIFT
-#define SPAR_UVLO_WAIT_1T		0x0
-#define SPAR_UVLO_WAIT_4ms		0x1
-#define SPAR_UVLO_WAIT_16ms		0x2
-#define SPAR_UVLO_WAIT_32ms		0x3
-#define RTC_SPAR_PWRKEY_MATCH_LPD_MASK	0x1
-#define RTC_SPAR_PWRKEY_MATCH_LPD_SHIFT	4
-#define RTC_SPAR_PWRKEY_MATCH_MASK	0x1
-#define RTC_SPAR_PWRKEY_MATCH_SHIFT	5
-#define RTC_SPAR_PROT_STAT_MASK		0x3
-#define RTC_SPAR_PROT_STAT_SHIFT	6
-
-/* Secure RTC */
-#define RTC_TC_SEC_SEC			MT6685_TC_SECOND_SEC_ADDR
-#define RTC_TC_MIN_SEC			MT6685_TC_MINUTE_SEC_ADDR
-#define RTC_TC_HOU_SEC			MT6685_TC_HOUR_SEC_ADDR
-#define RTC_TC_DOM_SEC			MT6685_TC_DOM_SEC_ADDR
-#define RTC_TC_DOW_SEC			MT6685_TC_DOW_SEC_ADDR
-#define RTC_TC_MTH_SEC			MT6685_TC_MONTH_SEC_ADDR
-#define RTC_TC_YEA_SEC			MT6685_TC_YEAR_SEC_ADDR
-
-#define RTC_WRTGR_SEC			MT6685_RTC_SEC_WRTGR_ADDR
-#define RTC_SEC_CK_PDN			MT6685_RTC_SEC_CK_PDN_ADDR
-
-#define RTC_SEC_DSN_REV0		MT6685_RTC_SEC_ANA_REV
-#define RTC_SEC_DSN_ID			MT6685_RTC_SEC_ANA_ID
-
-#define RTC_SEC_BAS			RTC_SEC_DSN_ID
-
-#endif /* SOC_MEDIATEK_MT8196_MT6685_RTC_HW_H */
diff --git a/src/soc/mediatek/mt8196/include/soc/rtc.h b/src/soc/mediatek/mt8196/include/soc/rtc.h
index e48c13e645..ba90669671 100644
--- a/src/soc/mediatek/mt8196/include/soc/rtc.h
+++ b/src/soc/mediatek/mt8196/include/soc/rtc.h
@@ -8,6 +8,7 @@
 #ifndef SOC_MEDIATEK_MT8196_RTC_H
 #define SOC_MEDIATEK_MT8196_RTC_H
 
+#include <soc/mt6685_rtc.h>
 #include <soc/rtc_common.h>
 #include <soc/rtc_reg_common.h>
 #include <stdbool.h>
diff --git a/src/soc/mediatek/mt8196/mt6685_rtc.c b/src/soc/mediatek/mt8196/mt6685_rtc.c
index 4e63f10664..95e8dd6907 100644
--- a/src/soc/mediatek/mt8196/mt6685_rtc.c
+++ b/src/soc/mediatek/mt8196/mt6685_rtc.c
@@ -7,9 +7,9 @@
 #include <commonlib/bsd/bcd.h>
 #include <console/console.h>
 #include <delay.h>
+#include <rtc.h>
 #include <soc/mt6685.h>
-#include <soc/mt6685_rtc.h>
-#include <soc/mt6685_rtc_hw.h>
+#include <soc/rtc.h>
 #include <stdbool.h>
 #include <timer.h>
 

From 98f3cf138e6bfa956ea0f542f8b63e04f1979f6c Mon Sep 17 00:00:00 2001
From: Shuo Liu <shuo.liu@intel.com>
Date: Fri, 28 Feb 2025 20:16:27 +0800
Subject: [PATCH 0318/3886] cbfstool: Fix the help text

The help text of cbfstool's memory map window assignment option
needs to be corrected to [--mmap flash-base:mmio-base:size] from
[--mmio flash-base:mmio-base:size].

P.S. The option --mmap was initially introduced by
commit 34a7e66faa46 ("util/cbfstool: Add a new mechanism to
provide a memory map").

Change-Id: I5f8224c8789e642fc68f6ae2242e8e7a7228c8de
Signed-off-by: Shuo Liu <shuo.liu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86639
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nicholas Chin <nic.c3.14@gmail.com>
---
 util/cbfstool/cbfstool.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/util/cbfstool/cbfstool.c b/util/cbfstool/cbfstool.c
index 783c7d9892..1b9931063e 100644
--- a/util/cbfstool/cbfstool.c
+++ b/util/cbfstool/cbfstool.c
@@ -1975,7 +1975,7 @@ static void usage(char *name)
 	     "        [-c compression] [-b base-address | -a alignment] \\\n"
 	     "        [-p padding size] [-y|--xip if TYPE is FSP]       \\\n"
 	     "        [-j topswap-size] (Intel CPUs only) [--ibb]       \\\n"
-	     "        [--mmio flash-base:mmio-base:size]                    "
+	     "        [--mmap flash-base:mmio-base:size]                    "
 			"Add a component\n"
 	     "                                                         "
 	     "    -j valid size: 0x10000 0x20000 0x40000 0x80000 0x100000 \n"
@@ -1988,7 +1988,7 @@ static void usage(char *name)
 	     "        [-S comma-separated-section(s)-to-ignore] \\\n"
 	     "        [-a alignment] [-Q|--pow2page] \\\n"
 	     "        [-y|--xip] [--ibb]                                \\\n"
-	     "        [--mmio flash-base:mmio-base:size]                    "
+	     "        [--mmap flash-base:mmio-base:size]                    "
 			"Add a stage to the ROM\n"
 	     " add-flat-binary [-r image,regions] -f FILE -n NAME \\\n"
 	     "        [-A hash] -l load-address -e entry-point \\\n"

From c90315276e079141e1fe55759763533c1ae85ac8 Mon Sep 17 00:00:00 2001
From: Sowmya Aralguppe <sowmya.aralguppe@intel.com>
Date: Mon, 9 Dec 2024 07:20:30 +0530
Subject: [PATCH 0319/3886] soc/intel/pantherlake: Decrease
 CRASHLOG_NODES_COUNT to 1

This patch changes child record count to 1 (i.e., compute die). The
number of crashlog agent/SRAM storage count is reduced in Crashlog
Discovery table (CRASHLOG_HEADER) for Panther Lake to 1 aka compute
die compared to MTL where crashlog units were compute die and GT die

source= 733648-LNLFAS-15.3.4,812562 PTL FAS 16.5.2 PTL
Dis-Aggreagation CrashLog

BUG=None
TEST=Build fatcat and verify the child record count

Change-Id: I209366d324c95b7a32afdcfb792c34d927a0508e
Signed-off-by: Sowmya Aralguppe <sowmya.aralguppe@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85531
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
---
 src/soc/intel/pantherlake/crashlog.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/soc/intel/pantherlake/crashlog.c b/src/soc/intel/pantherlake/crashlog.c
index d94f4c5476..0f288efe14 100644
--- a/src/soc/intel/pantherlake/crashlog.c
+++ b/src/soc/intel/pantherlake/crashlog.c
@@ -14,7 +14,7 @@
 #include <string.h>
 
 #define CONTROL_INTERFACE_OFFSET	0x5
-#define CRASHLOG_NODES_COUNT		0x2
+#define CRASHLOG_NODES_COUNT		0x1
 #define CRASHLOG_PUNIT_STORAGE_OFF_MASK	BIT(24)
 #define CRASHLOG_RE_ARM_STATUS_MASK	BIT(25)
 #define CRASHLOG_CONSUMED_MASK		BIT(31)

From c278be512b6e8045446ce80a5fc846dbd52b643f Mon Sep 17 00:00:00 2001
From: jamie_chen <jamie_chen@compal.corp-partner.google.com>
Date: Thu, 6 Mar 2025 09:23:29 +0800
Subject: [PATCH 0320/3886] mb/google/trulo/var/uldrenite: Adjust Touchpad I2C
 timing

Adjust I2C/data fall Time to 13.5 ns and I2C data hold time to 353 ns

BUG=b:397150937
BRANCH=firmware-trulo-15217.771.B
TEST=Confirm the measured waveform of the Touchpad .

Change-Id: I16a9967f7e99892f2aa337ad9290252ab63a5b97
Signed-off-by: jamie_chen <jamie_chen@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86743
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 .../brya/variants/uldrenite/overridetree.cb       | 15 +++++++++------
 1 file changed, 9 insertions(+), 6 deletions(-)

diff --git a/src/mainboard/google/brya/variants/uldrenite/overridetree.cb b/src/mainboard/google/brya/variants/uldrenite/overridetree.cb
index 5571fe7902..e8ffc6072b 100644
--- a/src/mainboard/google/brya/variants/uldrenite/overridetree.cb
+++ b/src/mainboard/google/brya/variants/uldrenite/overridetree.cb
@@ -150,12 +150,15 @@ chip soc/intel/alderlake
 			}
 		},
 		.i2c[1] = {
-			.speed = I2C_SPEED_FAST,
-			.speed_config[0] = {
-				.speed = I2C_SPEED_FAST,
-				.scl_lcnt = 158,
-				.scl_hcnt = 79,
-				.sda_hold = 7,
+    			.speed = I2C_SPEED_FAST,
+    			.rise_time_ns = 200,
+    			.fall_time_ns = 150,
+    			.data_hold_time_ns = 950,
+    			.speed_config[0] = {
+        			.speed = I2C_SPEED_FAST,
+        			.scl_lcnt = 166,
+        			.scl_hcnt = 83,
+        			.sda_hold = 35,
 			}
 		},
 		.i2c[5] = {

From 68367ac69e34baa1b9f475dab9842139120fb806 Mon Sep 17 00:00:00 2001
From: John Su <john_su@compal.corp-partner.google.com>
Date: Tue, 18 Feb 2025 16:44:22 +0800
Subject: [PATCH 0321/3886] mb/google/trulo/var/uldrenite: Support body
 detection to DPTF

Use DPTF_FEATURE_DYNAMIC_THERMAL_TABLE_SWITCH to support
body detection to DPTF on the Uldrenite.

BUG=b:394177292
BRANCH=firmware-trulo-15217.771.B
TEST=emerge-nissa coreboot

Change-Id: I6e98b9c3fd1b38d10a1aa7c30d5d92e1638449f2
Signed-off-by: John Su <john_su@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86494
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
---
 .../google/brya/variants/uldrenite/include/variant/ec.h         | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/src/mainboard/google/brya/variants/uldrenite/include/variant/ec.h b/src/mainboard/google/brya/variants/uldrenite/include/variant/ec.h
index 818cdef7df..c91c99b945 100644
--- a/src/mainboard/google/brya/variants/uldrenite/include/variant/ec.h
+++ b/src/mainboard/google/brya/variants/uldrenite/include/variant/ec.h
@@ -8,4 +8,6 @@
 /* Enable DPTF OEM variable */
 #define DPTF_ENABLE_OEM_VARIABLES
 
+#define DPTF_FEATURE_DYNAMIC_THERMAL_TABLE_SWITCH
+
 #endif

From b78896348d4846db76d394c5d1225e00a08afcad Mon Sep 17 00:00:00 2001
From: John Su <john_su@compal.corp-partner.google.com>
Date: Tue, 4 Mar 2025 18:23:06 +0800
Subject: [PATCH 0322/3886] ec/google/chromeec/acpi: Add support for Body
 Detect

The EC code will monitor Body to choose corresponding DPTF oem variable
table. When it changes, this event will send to the ACPI FW through host
event and then pass onto the DPTF kernel driver.

BUG=b:394177292
BRANCH=firmware-trulo-15217.771.B
TEST=emerge-nissa coreboot

Change-Id: I7ed72157d3480fca5fd1a58b5d9bc3e321f4a628
Signed-off-by: John Su <john_su@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86707
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
---
 src/ec/google/chromeec/acpi/ec.asl | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/src/ec/google/chromeec/acpi/ec.asl b/src/ec/google/chromeec/acpi/ec.asl
index 8e241fcfe1..ebba0faffd 100644
--- a/src/ec/google/chromeec/acpi/ec.asl
+++ b/src/ec/google/chromeec/acpi/ec.asl
@@ -196,6 +196,11 @@ Device (EC0)
 			\_SB.DPTC()
 		}
 #endif
+
+#ifdef DPTF_FEATURE_DYNAMIC_THERMAL_TABLE_SWITCH
+		\_SB.DPTF.ODUP(0, STTB)
+		Notify (\_SB.DPTF, INT3400_ODVP_CHANGED)
+#endif
 	}
 
 	/* Read requested temperature and check against EC error values */
@@ -472,6 +477,11 @@ Device (EC0)
 			\_SB.DPTC()
 		}
 #endif
+
+#ifdef DPTF_FEATURE_DYNAMIC_THERMAL_TABLE_SWITCH
+		\_SB.DPTF.ODUP(0, STTB)
+		Notify (\_SB.DPTF, INT3400_ODVP_CHANGED)
+#endif
 	}
 
 	/*

From 7e8cf42fbba9407985cd54eb14565af53cb2d812 Mon Sep 17 00:00:00 2001
From: Felix Singer <felixsinger@posteo.net>
Date: Thu, 6 Mar 2025 04:57:21 +0000
Subject: [PATCH 0323/3886] 3rdparty/fsp: Update submodule to upstream master

Updating from commit id 15c0f7b3f723:
2025-01-21 12:24:27 +0800 - (ECG ARL-S PV (4400_43) FSP)

to commit id 86c9111639d3:
2025-03-03 16:14:02 +0800 - (Edge Platforms RPL-P IPU 2025.2 (5402_02) FSP)

This brings in 19 new commits:
86c9111639d3 Edge Platforms RPL-P IPU 2025.2 (5402_02) FSP
85a0b8abf54c Edge Platforms RPL-S/RPL-S Refresh IPU 2025.2 (5402_02) FSP
9230a87a24bf Edge Platforms ADL-PS IPU 2025.2 (5402_02) FSP
39a1dab37cfb Edge Platforms ADL-S IPU 2025.2 (5402_01) FSP
c2aa77cde720 Merge branch 'master' of https://github.com/intel/FSP
508d8eb4bde8 Edge Platforms ADL-P IPU 2025.2 (5402_00) FSP
cdb5d570f5d8 Eagle Stream FSP (0115.D.05)
b4202af1b52e NEX TGL IPU 2025.2 (7021_05) FSP
99830941181e Update MemInfoHob.h
590d7f9bd8c7 IoT RPL-PS MR1 (5275_01) FSP
a92562452783 Merge branch 'master' of https://github.com/intel/FSP
6e84fc2ed0f6 IoT ADL-N MR6 (6023_00)
0acc6fac5bcc Update MemInfoHob.h
4b3e936c9701 Merge branch 'master' of https://github.com/intel/FSP
7207bafc8905 Elkhart Lake IPU2025.2 FSP
29e0f7ae5d26 ECG ARL-UH PV (4404_55) FSP
e369d3f2c21b ECG ARL-UH PV (4404_55) FSP
d746b5b93806 ECG ARL-S PV (4400_43) FSP
3ba9ffddac41 NEX AZB IPU 2025.2 (6033_00) FSP

Change-Id: I1e050bea8a8d625cfd842b6f008bf18ce6f66f84
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86744
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 3rdparty/fsp | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/3rdparty/fsp b/3rdparty/fsp
index 15c0f7b3f7..86c9111639 160000
--- a/3rdparty/fsp
+++ b/3rdparty/fsp
@@ -1 +1 @@
-Subproject commit 15c0f7b3f723bcd713e5ab11ebc502f30d9084e7
+Subproject commit 86c9111639d357e0f369c14248097b119112a71c

From b004ee591de55752280c7431b65e89699cdef422 Mon Sep 17 00:00:00 2001
From: Arthur Heymans <arthur@aheymans.xyz>
Date: Wed, 7 Feb 2024 11:27:31 +0100
Subject: [PATCH 0324/3886] soc/intel/xeon-sp/spr: Hook up public FSP bin and
 headers

vendorcode/intel/fsp/fsp2_0/sapphirerapids_sp/ is still needed due to
Intel FSP repo does not ship all header files.

TEST=Build and boot on intel/archercity CRB

Change-Id: I778d3535c273dff653330518653bdefcb45e66f4
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Signed-off-by: Shuo Liu <shuo.liu@intel.com>
Signed-off-by: Jincheng Li <jincheng.li@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80360
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 configs/builder/config.intel.crb.ac           |    6 -
 src/mainboard/bytedance/bd_egs/romstage.c     |    1 +
 .../inventec/transformers/romstage.c          |    1 +
 src/soc/intel/xeon_sp/spr/Kconfig             |    7 +-
 src/soc/intel/xeon_sp/spr/Makefile.mk         |    1 +
 src/soc/intel/xeon_sp/spr/romstage.c          |    1 +
 .../fsp/fsp2_0/sapphirerapids_sp/CxlNodeHob.h |   94 --
 .../fsp/fsp2_0/sapphirerapids_sp/FspEas.h     |   17 -
 .../sapphirerapids_sp/FspErrorInfoHob.h       |   84 --
 .../fsp/fsp2_0/sapphirerapids_sp/FspUpd.h     |   48 -
 .../fsp/fsp2_0/sapphirerapids_sp/FspmUpd.h    | 1308 -----------------
 .../fsp/fsp2_0/sapphirerapids_sp/FspsUpd.h    |  286 ----
 .../fsp/fsp2_0/sapphirerapids_sp/FsptUpd.h    |  109 --
 .../sapphirerapids_sp/IioPcieConfigUpd.h      |  145 --
 .../sapphirerapids_sp/IioUniversalDataHob.h   |  253 ----
 .../sapphirerapids_sp/MemoryMapDataHob.h      |  373 -----
 .../sapphirerapids_sp/PrevBootErrSrcHob.h     |   85 --
 .../fsp2_0/sapphirerapids_sp/SystemInfoHob.h  |  283 ----
 18 files changed, 9 insertions(+), 3093 deletions(-)
 delete mode 100644 src/vendorcode/intel/fsp/fsp2_0/sapphirerapids_sp/CxlNodeHob.h
 delete mode 100644 src/vendorcode/intel/fsp/fsp2_0/sapphirerapids_sp/FspEas.h
 delete mode 100644 src/vendorcode/intel/fsp/fsp2_0/sapphirerapids_sp/FspErrorInfoHob.h
 delete mode 100644 src/vendorcode/intel/fsp/fsp2_0/sapphirerapids_sp/FspUpd.h
 delete mode 100644 src/vendorcode/intel/fsp/fsp2_0/sapphirerapids_sp/FspmUpd.h
 delete mode 100644 src/vendorcode/intel/fsp/fsp2_0/sapphirerapids_sp/FspsUpd.h
 delete mode 100644 src/vendorcode/intel/fsp/fsp2_0/sapphirerapids_sp/FsptUpd.h
 delete mode 100644 src/vendorcode/intel/fsp/fsp2_0/sapphirerapids_sp/IioPcieConfigUpd.h
 delete mode 100644 src/vendorcode/intel/fsp/fsp2_0/sapphirerapids_sp/IioUniversalDataHob.h
 delete mode 100644 src/vendorcode/intel/fsp/fsp2_0/sapphirerapids_sp/MemoryMapDataHob.h
 delete mode 100644 src/vendorcode/intel/fsp/fsp2_0/sapphirerapids_sp/PrevBootErrSrcHob.h
 delete mode 100644 src/vendorcode/intel/fsp/fsp2_0/sapphirerapids_sp/SystemInfoHob.h

diff --git a/configs/builder/config.intel.crb.ac b/configs/builder/config.intel.crb.ac
index 73e2eea06f..df898b0dc0 100644
--- a/configs/builder/config.intel.crb.ac
+++ b/configs/builder/config.intel.crb.ac
@@ -12,13 +12,7 @@ CONFIG_PAYLOAD_LINUX=y
 CONFIG_PAYLOAD_FILE="site-local/archercity/linuxboot_bzImage"
 CONFIG_HAVE_ME_BIN=y
 CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION=y
-CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y
-CONFIG_ADD_FSP_BINARIES=y
-CONFIG_FSP_T_FILE="site-local/archercity/Server_T.fd"
-CONFIG_FSP_M_FILE="site-local/archercity/Server_M.fd"
-CONFIG_FSP_S_FILE="site-local/archercity/Server_S.fd"
 CONFIG_IFD_BIN_PATH="site-local/archercity/descriptor.bin"
 CONFIG_ME_BIN_PATH="site-local/archercity/me.bin"
-CONFIG_CPU_UCODE_BINARIES="site-local/archercity/mbf806f8.mcb"
 CONFIG_VALIDATE_INTEL_DESCRIPTOR=y
 CONFIG_NO_GFX_INIT=y
diff --git a/src/mainboard/bytedance/bd_egs/romstage.c b/src/mainboard/bytedance/bd_egs/romstage.c
index e1e976b7c5..7f20c2a956 100644
--- a/src/mainboard/bytedance/bd_egs/romstage.c
+++ b/src/mainboard/bytedance/bd_egs/romstage.c
@@ -5,6 +5,7 @@
 #include <defs_iio.h>
 #include <sprsp_bd_iio.h>
 #include <stdint.h>
+#include <IioPcieConfigUpd.h>
 
 static void mainboard_config_iio(FSPM_UPD *mupd)
 {
diff --git a/src/mainboard/inventec/transformers/romstage.c b/src/mainboard/inventec/transformers/romstage.c
index 25ff2d6226..2ce90088c5 100644
--- a/src/mainboard/inventec/transformers/romstage.c
+++ b/src/mainboard/inventec/transformers/romstage.c
@@ -12,6 +12,7 @@
 #include <defs_iio.h>
 #include <sprsp_ac_iio.h>
 #include <stdint.h>
+#include <IioPcieConfigUpd.h>
 
 #include "ipmi.h"
 
diff --git a/src/soc/intel/xeon_sp/spr/Kconfig b/src/soc/intel/xeon_sp/spr/Kconfig
index d6c9832f52..e36f684cc6 100644
--- a/src/soc/intel/xeon_sp/spr/Kconfig
+++ b/src/soc/intel/xeon_sp/spr/Kconfig
@@ -16,6 +16,7 @@ config SOC_INTEL_SAPPHIRERAPIDS_SP
 	select UDK_202005_BINDING
 	select SOC_INTEL_HAS_CXL
 	select HAVE_X86_64_SUPPORT
+	select HAVE_INTEL_FSP_REPO
 	help
 	  Intel Sapphire Rapids-SP support
 
@@ -26,8 +27,10 @@ config CHIPSET_DEVICETREE
 	default "soc/intel/xeon_sp/spr/chipset.cb"
 
 config FSP_HEADER_PATH
-	string "Location of FSP headers"
-	default "src/vendorcode/intel/fsp/fsp2_0/sapphirerapids_sp"
+	default "3rdparty/fsp/EagleStreamFspBinPkg/Include"
+
+config FSP_FD_PATH
+	default "3rdparty/fsp/EagleStreamFspBinPkg/Fsp.fd"
 
 config MAX_CPUS
 	int
diff --git a/src/soc/intel/xeon_sp/spr/Makefile.mk b/src/soc/intel/xeon_sp/spr/Makefile.mk
index 39d6a99d28..63bb86611e 100644
--- a/src/soc/intel/xeon_sp/spr/Makefile.mk
+++ b/src/soc/intel/xeon_sp/spr/Makefile.mk
@@ -24,6 +24,7 @@ ramstage-y += ../pcu3.c
 ramstage-y += ../pcu6.c
 
 CPPFLAGS_common += -I$(src)/soc/intel/xeon_sp/spr/include -I$(src)/soc/intel/xeon_sp/spr
+CPPFLAGS_common += -I$(src)/vendorcode/intel/fsp/fsp2_0/sapphirerapids_sp
 
 cpu_microcode_bins += 3rdparty/intel-microcode/intel-ucode/06-8f-08
 cpu_microcode_bins += 3rdparty/intel-microcode/intel-ucode/06-cf-02
diff --git a/src/soc/intel/xeon_sp/spr/romstage.c b/src/soc/intel/xeon_sp/spr/romstage.c
index 43eb187d84..0153485597 100644
--- a/src/soc/intel/xeon_sp/spr/romstage.c
+++ b/src/soc/intel/xeon_sp/spr/romstage.c
@@ -23,6 +23,7 @@
 #include <soc/soc_util.h>
 #include <soc/util.h>
 #include <soc/ddr.h>
+#include <IioPcieConfigUpd.h>
 
 #include "chip.h"
 
diff --git a/src/vendorcode/intel/fsp/fsp2_0/sapphirerapids_sp/CxlNodeHob.h b/src/vendorcode/intel/fsp/fsp2_0/sapphirerapids_sp/CxlNodeHob.h
deleted file mode 100644
index 42b5cc20d5..0000000000
--- a/src/vendorcode/intel/fsp/fsp2_0/sapphirerapids_sp/CxlNodeHob.h
+++ /dev/null
@@ -1,94 +0,0 @@
-/** @file
-
-Copyright (c) 2019-2023, Intel Corporation. All rights reserved.<BR>
-
-Redistribution and use in source and binary forms, with or without modification,
-are permitted provided that the following conditions are met:
-
-* Redistributions of source code must retain the above copyright notice, this
-  list of conditions and the following disclaimer.
-* Redistributions in binary form must reproduce the above copyright notice, this
-  list of conditions and the following disclaimer in the documentation and/or
-  other materials provided with the distribution.
-* Neither the name of Intel Corporation nor the names of its contributors may
-  be used to endorse or promote products derived from this software without
-  specific prior written permission.
-
-  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
-  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
-  THE POSSIBILITY OF SUCH DAMAGE.
-
-**/
-
-#ifndef _CXL_NODE_HOB_
-#define _CXL_NODE_HOB_
-
-#define CXL_NODE_HOB_GUID { 0xdd8ae009, 0xda5a, 0x44a3, { 0xbe, 0x18, 0xda, 0x0c, 0x16, 0xc5, 0xaf, 0x5c } }
-
-#ifndef MAX_CXL_HDM_RANGES
-#define MAX_CXL_HDM_RANGES        0x2        // Maximum number of CXL HDM ranges per CXL end device.
-#endif
-
-#ifndef MAX_CXL_PER_SOCKET
-#define MAX_CXL_PER_SOCKET          8
-#endif
-
-#define CXL_NODE_ATTR_MEM           BIT0
-#define CXL_NODE_ATTR_PERSISTENT    BIT1
-#define CXL_NODE_ATTR_MEM_HW_INIT   BIT2
-#define CXL_NODE_ATTR_ACCELERATOR   BIT3
-
-typedef UINT32 CXL_NODE_ATTR;
-
-#pragma pack(1)
-
-//
-// CDAT DSEMTS EFI Memory Type and Attribute
-//
-typedef enum {
-  CxlEfiConventionalMemory        = 0x0,
-  CxlEfiConventionalMemorySp      = 0x1,
-  CxlEfiReservedMemoryType        = 0x2,
-  MaxCxlEfiMemType
-} CXL_EFI_MEM_TYPE;
-
-typedef struct {
-  UINT32              RdLatency;
-  UINT32              WrLatency;
-  UINT32              RdBandwidth;
-  UINT32              WrBandwidth;
-} CXL_PERF_DATA;
-
-typedef struct {
-  UINT64                       SerialNumber;
-  UINT16                       VendorId;
-  CXL_NODE_ATTR                Attr;
-  UINT32                       Address;
-  UINT32                       Size;
-  UINT8                        Ways;
-  UINT8                        SocketBitmap;
-  CXL_EFI_MEM_TYPE             EfiMemType;
-  CXL_PERF_DATA                InitiatorPerfData;        // Performance data between device egress and initiator.
-  CXL_PERF_DATA                TargetPerfData;           // Performance data of entire target memory region.
-  CXL_PERF_DATA                InitiatorTargetPerfData;  // performance data between initiator and the device memory.
-} CXL_NODE_INFO;
-
-typedef struct {
-  UINT8            CxlNodeCount;
-  //
-  // CXL node info for UEFI memory map and ACPI tables construction
-  //
-  CXL_NODE_INFO    CxlNodeInfo[MAX_CXL_PER_SOCKET * MAX_CXL_HDM_RANGES];
-} CXL_NODE_SOCKET;
-
-#pragma pack()
-
-#endif //#ifndef _CXL_NODE_HOB_
diff --git a/src/vendorcode/intel/fsp/fsp2_0/sapphirerapids_sp/FspEas.h b/src/vendorcode/intel/fsp/fsp2_0/sapphirerapids_sp/FspEas.h
deleted file mode 100644
index f99c3bc36b..0000000000
--- a/src/vendorcode/intel/fsp/fsp2_0/sapphirerapids_sp/FspEas.h
+++ /dev/null
@@ -1,17 +0,0 @@
-/** @file
-  Intel FSP definition from Intel Firmware Support Package External
-  Architecture Specification v2.2.
- @copyright
-  Copyright (c) 2015 - 2021, Intel Corporation. All rights reserved.<BR>
-  SPDX-License-Identifier: BSD-2-Clause-Patent
-**/
-
-#ifndef _FSP_EAS_H_
-#define _FSP_EAS_H_
-
-#include <Uefi.h>
-#include <Guid/GuidHobFspEas.h>
-#include <Guid/FspHeaderFile.h>
-#include <FspEas/FspApi.h>
-
-#endif // _FSP_EAS_H_
\ No newline at end of file
diff --git a/src/vendorcode/intel/fsp/fsp2_0/sapphirerapids_sp/FspErrorInfoHob.h b/src/vendorcode/intel/fsp/fsp2_0/sapphirerapids_sp/FspErrorInfoHob.h
deleted file mode 100644
index ecc2d6fdf7..0000000000
--- a/src/vendorcode/intel/fsp/fsp2_0/sapphirerapids_sp/FspErrorInfoHob.h
+++ /dev/null
@@ -1,84 +0,0 @@
-/** @file
-
-Copyright (c) 2019-2023, Intel Corporation. All rights reserved.<BR>
-
-Redistribution and use in source and binary forms, with or without modification,
-are permitted provided that the following conditions are met:
-
-* Redistributions of source code must retain the above copyright notice, this
-  list of conditions and the following disclaimer.
-* Redistributions in binary form must reproduce the above copyright notice, this
-  list of conditions and the following disclaimer in the documentation and/or
-  other materials provided with the distribution.
-* Neither the name of Intel Corporation nor the names of its contributors may
-  be used to endorse or promote products derived from this software without
-  specific prior written permission.
-
-  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
-  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
-  THE POSSIBILITY OF SUCH DAMAGE.
-
-**/
-
-#ifndef _FSP_ERROR_INFO_HOB_H_
-#define _FSP_ERROR_INFO_HOB_H_
-
-#include <Uefi/UefiMultiPhase.h>
-#include <Pi/PiBootMode.h>
-#include <Pi/PiHob.h>
-#include <Pi/PiStatusCode.h>
-
-#define FSP_ERROR_INFO_HOB_GUID                 { 0x611e6a88, 0xadb7, 0x4301, { 0x93, 0xff, 0xe4, 0x73, 0x04, 0xb4, 0x3d, 0xa6 }}
-
-#pragma pack(1)
-
-typedef struct {
-  ///
-  /// GUID HOB header.
-  ///
-  EFI_HOB_GUID_TYPE     GuidHob;
-
-  ///
-  /// ReportStatusCode () type identifier.
-  ///
-  EFI_STATUS_CODE_TYPE  Type;
-
-  ///
-  /// ReportStatusCode () value.
-  ///
-  EFI_STATUS_CODE_VALUE Value;
-
-  ///
-  /// ReportStatusCode () Instance number.
-  ///
-  UINT32                Instance;
-
-  ///
-  /// Optional GUID which may be used to identify
-  /// which internal component of the FSP was
-  /// executing at the time of the error.
-  ///
-  EFI_GUID              CallerId;
-
-  ///
-  /// GUID identifying the nature of the fatal error.
-  ///
-  EFI_GUID              ErrorType;
-
-  ///
-  /// EFI_STATUS code describing the error encountered.
-  ///
-  UINT32                Status;
-} FSP_ERROR_INFO_HOB;
-
-#pragma pack()
-
-#endif //#ifndef _FSP_ERROR_INFO_HOB_H_
diff --git a/src/vendorcode/intel/fsp/fsp2_0/sapphirerapids_sp/FspUpd.h b/src/vendorcode/intel/fsp/fsp2_0/sapphirerapids_sp/FspUpd.h
deleted file mode 100644
index ce86ce8a9a..0000000000
--- a/src/vendorcode/intel/fsp/fsp2_0/sapphirerapids_sp/FspUpd.h
+++ /dev/null
@@ -1,48 +0,0 @@
-/** @file
-
-Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
-
-Redistribution and use in source and binary forms, with or without modification,
-are permitted provided that the following conditions are met:
-
-* Redistributions of source code must retain the above copyright notice, this
-  list of conditions and the following disclaimer.
-* Redistributions in binary form must reproduce the above copyright notice, this
-  list of conditions and the following disclaimer in the documentation and/or
-  other materials provided with the distribution.
-* Neither the name of Intel Corporation nor the names of its contributors may
-  be used to endorse or promote products derived from this software without
-  specific prior written permission.
-
-  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
-  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
-  THE POSSIBILITY OF SUCH DAMAGE.
-
-  This file is automatically generated. Please do NOT modify !!!
-
-**/
-
-#ifndef __FSPUPD_H__
-#define __FSPUPD_H__
-
-#include <FspEas.h>
-
-#pragma pack(1)
-
-#define FSPT_UPD_SIGNATURE               0x545F445055525053        /* 'SPRUPD_T' */
-
-#define FSPM_UPD_SIGNATURE               0x4D5F445055525053        /* 'SPRUPD_M' */
-
-#define FSPS_UPD_SIGNATURE               0x535F445055525053        /* 'SPRUPD_S' */
-
-#pragma pack()
-
-#endif
diff --git a/src/vendorcode/intel/fsp/fsp2_0/sapphirerapids_sp/FspmUpd.h b/src/vendorcode/intel/fsp/fsp2_0/sapphirerapids_sp/FspmUpd.h
deleted file mode 100644
index bfd8d7dce4..0000000000
--- a/src/vendorcode/intel/fsp/fsp2_0/sapphirerapids_sp/FspmUpd.h
+++ /dev/null
@@ -1,1308 +0,0 @@
-/** @file
-
-Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
-
-Redistribution and use in source and binary forms, with or without modification,
-are permitted provided that the following conditions are met:
-
-* Redistributions of source code must retain the above copyright notice, this
-  list of conditions and the following disclaimer.
-* Redistributions in binary form must reproduce the above copyright notice, this
-  list of conditions and the following disclaimer in the documentation and/or
-  other materials provided with the distribution.
-* Neither the name of Intel Corporation nor the names of its contributors may
-  be used to endorse or promote products derived from this software without
-  specific prior written permission.
-
-  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
-  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
-  THE POSSIBILITY OF SUCH DAMAGE.
-
-  This file is automatically generated. Please do NOT modify !!!
-
-**/
-
-#ifndef __FSPMUPD_H__
-#define __FSPMUPD_H__
-
-#include <FspUpd.h>
-#include <IioPcieConfigUpd.h>
-
-#pragma pack(1)
-
-
-/** FSP-M Configuration
-**/
-typedef struct {
-
-/** Offset 0x0040 - Customer Revision
-  The Customer can set this revision string for their own purpose.
-**/
-  UINT8                       CustomerRevision[32];
-
-/** Offset 0x0060 - Bus Ratio
-  Indicates the ratio of Bus/MMIOL/IO resource to be allocated for each CPU's IIO
-**/
-  UINT8                       BusRatio[8];
-
-/** Offset 0x0068 - D2K Credit Config
-  Set the D2K Credit Config - 1: Min, <b>2: Med(Default)</b>, 3: Max.
-  1:Min, 2:Med, 3:Max
-**/
-  UINT8                       D2KCreditConfig;
-
-/** Offset 0x0069 - Snoop Throttle Config
-  Set the Snoop Throttle Config - <b>0: DIS(Default)</b>, 1: Min, 2: Med, 3: Max.
-  0:DIS, 1:Min, 2:Med, 3:Max
-**/
-  UINT8                       SnoopThrottleConfig;
-
-/** Offset 0x006A - Legacy VGA Soc
-  Socket that claims the legacy VGA range
-**/
-  UINT8                       LegacyVgaSoc;
-
-/** Offset 0x006B - Legacy VGA Stack
-  Stack that claims the legacy VGA range
-**/
-  UINT8                       LegacyVgaStack;
-
-/** Offset 0x006C - Pcie P2P Performance Mode
-  Determine if to enable PCIe P2P Performance Mode - <b>0: Disable(Default)</b>, 1: Enable.
-  0:Disable, 1:Enable
-**/
-  UINT8                       P2pRelaxedOrdering;
-
-/** Offset 0x006D - UPI Debug Print Level
-  UPI Debug Print Level Bitmask - 0: Disable, 1: Fatal, 2: Warning, 4: Summary, 8:
-  Detail, <b>0x0F: All(Default)</b>.
-  1:Fatal, 2:Warning, 4:Summary, 8:Detail, 0x0F:All
-**/
-  UINT8                       DebugPrintLevel;
-
-/** Offset 0x006E - NumaEn
-  NumaEn - <b>1: Enable Numa(Default)</b>, 0: Disable Numa.
-  0:Disable, 1:Enable
-**/
-  UINT8                       NumaEn;
-
-/** Offset 0x006F - SNC
-  Enable or Disable SNC - 0: Disable, 2: Snc2, 4: Snc4, <b>0x0F: Auto(Default)</b>.
-  0: Disable, 2: Snc2, 4: Snc4, 0x0F: Auto
-**/
-  UINT8                       SncEn;
-
-/** Offset 0x0070 - UMA Clustering
-  Set UMA Clusters - 0: Disable, 2: Two Clusters, <b>4: Four Clusters(Default)</b>.
-  0:Disable, 2:Two Clusters, 4:Four Clusters
-**/
-  UINT8                       UmaClustering;
-
-/** Offset 0x0071 - IODC Mode
-  IODC Mode - 0: Disable, <b>1: Auto(Default)</b>, 2: Push, 3: AllocFlow, 4: NonAlloc,
-  5: WCILF.
-  0:Disable, 1:Auto, 2:Push, 3:AllocFlow, 4:NonAlloc, 5:WCILF
-**/
-  UINT8                       IoDcMode;
-
-/** Offset 0x0072 - Degrade Precedence
-  Setup Degrade Precedence - <b>0: Topology(Default)</b>, 1: Feature.
-  0:Topology, 1:Feature
-**/
-  UINT8                       DegradePrecedence;
-
-/** Offset 0x0073 - Degrade 4 Socket Preference
-  Setup Degrade 4 Socket Preference - <b>0: Fully Connect(Default)</b>, 1: Dual Link Ring.
-  0:Fully Connect, 1:Dual Link Ring
-**/
-  UINT8                       Degrade4SPreference;
-
-/** Offset 0x0074 - Directory Mode
-  Enable or Disable Directory Mode - 0: Disable, 1: Enable, <b>2: Auto(Default)</b>.
-  0:Disable, 1:Enable, 2:Auto
-**/
-  UINT8                       DirectoryModeEn;
-
-/** Offset 0x0075 - XPT Prefetch Enable
-  Enable or Disable XPT Prefetch - 0: Disable, 1: Enable, <b>2: Auto(Default)</b>.
-  0:Disable, 1:Enable, 2:Auto
-**/
-  UINT8                       XptPrefetchEn;
-
-/** Offset 0x0076 - KTI Prefetch Enable
-  Enable or Disable KTI Prefetch - 0: Disable, 1: Enable, <b>2: Auto(Default)</b>.
-  0:Disable, 1:Enable, 2:Auto
-**/
-  UINT8                       KtiPrefetchEn;
-
-/** Offset 0x0077 - XPT Remote Prefetch Enable
-  Enable or Disable XPT Remote Prefetch Enable - 0: Disable, 1: Enable, <b>2: Auto(Default)</b>.
-  0:Disable, 1:Enable, 2:Auto
-**/
-  UINT8                       XptRemotePrefetchEn;
-
-/** Offset 0x0078 - KTI FPGA
-  Enable or Disable KTI FPGA
-**/
-  UINT8                       KtiFpgaEnable[8];
-
-/** Offset 0x0080 - DDRT QoS Mode
-  DDRT QoS - <b>0: Mode 0(Default)</b>, 1: Mode 1, 2: Mode 2.
-  0:Mode 0, 1:Mode 1, 2:Mode 2
-**/
-  UINT8                       DdrtQosMode;
-
-/** Offset 0x0081 - KTI Link Speed Mode
-  Choose KTI Link Speed Mode - 0: Slow, <b>1: Full(Default)</b>.
-  0:Slow, 1:Full
-**/
-  UINT8                       KtiLinkSpeedMode;
-
-/** Offset 0x0082 - KTI Link Speed
-  Setup KTI Link Speed - 0: 128GT, 1: 144GT, 2: 160GT, 3: 200GT, <b>0x7F: Max KTI
-  Link Speed (Default)</b>, 0x8F: Frequency Per Link.
-  0:128GT, 1:144GT, 2:160GT, 3:200GT, 0x7F:Max KTI Link Speed, 0x8F:Frequency Per Link
-**/
-  UINT8                       KtiLinkSpeed;
-
-/** Offset 0x0083 - KTI Link L0p
-  Enable or Disable KTI Link L0p - 0: Disable, 1: Enable, <b>2: Auto(Default)</b>.
-  0:Disable, 1:Enable, 2: Auto
-**/
-  UINT8                       KtiLinkL0pEn;
-
-/** Offset 0x0084 - KTI Link L1
-  Enable or Disable KTI Link L1 - 0: Disable, 1: Enable, <b>2: Auto(Default)</b>.
-  0:Disable, 1:Enable, 2: Auto
-**/
-  UINT8                       KtiLinkL1En;
-
-/** Offset 0x0085 - Kti Link Speed Per Port
-  Setup KTI Link Speed to be allocated for each port - 0: 128GT, 1: 144GT, 2: 160GT,
-  3: 200GT, <b>0x7f: Max KTI Link Speed(Default)</b>.
-  0:128GT, 1:144GT, 2:160GT, 3:200GT, 0x7f:Max KTI Link Speed
-**/
-  UINT8                       KtiLinkSpeedPerPort[48];
-
-/** Offset 0x00B5 - DfxL0p Enable
-  Indicates the DfxL0p Enable to be allocated for each port - 0: Disable, <b>1: Enable(Default)</b>.
-  0:Disable, 1:Enable
-**/
-  UINT8                       DfxL0pEnable[48];
-
-/** Offset 0x00E5 - DfxL1 Enable
-  Indicates the DfxL1 Enable to be allocated for each port - 0: Disable, <b>1: Enable(Default)</b>.
-  0:Disable, 1:Enable
-**/
-  UINT8                       DfxL1Enable[48];
-
-/** Offset 0x0115 - KTI Failover
-  Enable or Disable KTI Failover - 0: Disable, 1: Enable, <b>2: Auto(Default)</b>.
-  0:Disable, 1:Enable, 2: Auto
-**/
-  UINT8                       KtiFailoverEn;
-
-/** Offset 0x0116 - KTI LB Enable
-  Enable or Disable KTI LB - <b>0:Disable(Default)</b>, 1:Enable.
-  0:Disable, 1:Enable
-**/
-  UINT8                       KtiLbEn;
-
-/** Offset 0x0117 - KTI CRC Mode
-  Select KTI CRC Mode - <b>0: 16bit(Default)</b>, 1: 32bit, 2: Auto.
-  0:16bit, 1:32bit, 2:Auto
-**/
-  UINT8                       KtiCrcMode;
-
-/** Offset 0x0118 - KTI CPU Socket Hotplug
-  Enable or Disable KTI CPU Socket Hotplug - <b>0: Disable(Default)</b>, 1: Enable.
-  0:Disable, 1:Enable
-**/
-  UINT8                       KtiCpuSktHotPlugEn;
-
-/** Offset 0x0119 - KTI CPU Socket HotPlug Topology
-  Select KTI CPU Socket HotPlug Topology - <b>0: 4Socket(Default)</b>, 1: 8Socket.
-  0:4Socket, 1:8Socket
-**/
-  UINT8                       KtiCpuSktHotPlugTopology;
-
-/** Offset 0x011A - KTI SKU Mismatch Check
-  Enable or Disable KTI SKU Mismatch Check - 0: Disable, <b>1 :Enable(Default)</b>.
-  0:Disable, 1:Enable
-**/
-  UINT8                       KtiSkuMismatchCheck;
-
-/** Offset 0x011B - TOR Threshold - Loctorem threshold Normal
-  Select TOR Threshold - Loctorem threshold Normal - 0: Disable, <b>1: Auto(Default)</b>,
-  2: Low, 3: Medium, 4: High.
-  0:Disable, 1:Auto, 2:Low, 3:Medium, 4:High
-**/
-  UINT8                       TorThresLoctoremNorm;
-
-/** Offset 0x011C - TOR threshold - Loctorem threshold empty
-  Select TOR threshold - Loctorem threshold empty - 0: Disable, <b>1: Auto(Default)</b>,
-  2: Low, 3: Medium, 4:High.
-  0:Disable, 1:Auto, 2:Low, 3:Medium, 4:High
-**/
-  UINT8                       TorThresLoctoremEmpty;
-
-/** Offset 0x011D - TSC Sync in Sockets
-  Enable or Disable TSC Sync in Sockets - 0: Disable, <b>1: Enable(Default)</b>, 2: Auto.
-  0:Disable, 1:Enable, 2:Auto
-**/
-  UINT8                       TscSyncEn;
-
-/** Offset 0x011E - HA A to S directory optimization
-  Enable or Disable HA A to S directory optimization - 0: Disable, 1: Enable, <b>2:
-  Auto(Default)</b>.
-  0:Disable, 1:Enable, 2:Auto
-**/
-  UINT8                       StaleAtoSOptEn;
-
-/** Offset 0x011F - LLC Deadline Allocation
-  Enable or Disable LLC Deadline Allocation - 0: Disable, <b>1: Enable(Default)</b>, 2: Auto.
-  0:Disable, 1:Enable, 2:Auto
-**/
-  UINT8                       LLCDeadLineAlloc;
-
-/** Offset 0x0120 - MBA BW Calibration Profiles
-  Choice of MBA BW throttling curve - 0: Linear BW shaping, 1: Biased BW shaping,
-  2: Legacy BW shaping, <b>3: Auto(Default)</b>.
-  0:Linear BW shaping, 1:Biased BW shaping, 2:Legacy BW shaping, 3:Auto
-**/
-  UINT8                       MbeBWCalChoice;
-
-/** Offset 0x0121 - Split Lock
-  Enable or Disable Split Lock - <b>0: Disable(Default)</b>, 1: Enable, 2: Auto.
-  0:Disable, 1:Enable, 2:Auto
-**/
-  UINT8                       SplitLock;
-
-/** Offset 0x0122 - Affinitize M2Iosf to Upi for 2-Socket
-  Affinitize M2IOSF traffic to proper UPI links to improve 2-Socket P2P perf - 0:
-  Disable, 1: Enable, <b>2: Auto(Default)</b>.
-  0:Disable, 1:Enable, 2:Auto
-**/
-  UINT8                       M2iosfToUpiAffinity;
-
-/** Offset 0x0123 - MMCFG Base Address
-  Setup MMCFG Base Address - 0: 1G, 1: 1.5G, 2: 1.75G, 3: 2G, 4: 2.25G, 5: 3G, <b>6:
-  Auto(Default)</b>.
-  0:1G, 1:1.5G, 2:1.75G, 3:2G, 4:2.25G, 5:3G, 6:Auto
-**/
-  UINT8                       mmCfgBase;
-
-/** Offset 0x0124 - MMCFG Size
-  Select MMCFG Size - 0: 64M, 1: 128M, 2: 256M, 3: 512M, 4: 1G, 5: 2G, <b>6: Auto(Default)</b>.
-  0:64M, 1:128M, 2:256M, 3:512M, 4:1G, 5:2G, 6:Auto
-**/
-  UINT8                       mmCfgSize;
-
-/** Offset 0x0125
-**/
-  UINT8                       UnusedUpdSpace0[3];
-
-/** Offset 0x0128 - MMIO High Base Address
-  MMIO High Base Address, a hex number for Bit[51:32]
-**/
-  UINT32                      mmiohBase;
-
-/** Offset 0x012C - CPU Physical Address Limit
-  CPU Physical Address Limit - <b>0: Disable(Default)</b>, 1: Enable.
-  0:Disable, 1:Enable
-**/
-  UINT8                       CpuPaLimit;
-
-/** Offset 0x012D
-**/
-  UINT8                       UnusedUpdSpace1;
-
-/** Offset 0x012E - MMIO High Size
-  MMIO High Size, Number of 1GB contiguous regions to be assigned for MMIOH space
-  per CPU.  Range 1-1024
-**/
-  UINT16                      mmiohSize;
-
-/** Offset 0x0130 - isocEn
-  Enable or Disable isocEn - <b>0: Disable(Default)</b>, 1: Enable, 2: Auto.
-  0:Disable, 1:Enable, 2:Auto
-**/
-  UINT8                       isocEn;
-
-/** Offset 0x0131 - DCA
-  Enable or Disable DCA - <b>0: Disable(Default)</b>, 1: Enable.
-  0:Disable, 1:Enable
-**/
-  UINT8                       dcaEn;
-
-/** Offset 0x0132
-**/
-  UINT8                       UnusedUpdSpace2[2];
-
-/** Offset 0x0134 - BoardTypeBitmask
-  BoardTypeBitmask
-**/
-  UINT32                      BoardTypeBitmask;
-
-/** Offset 0x0138 - AllLanesPtr
-  Pointer to array of ALL_LANES_EPARAM_LINK_INFO
-**/
-  UINT32                      AllLanesPtr;
-
-/** Offset 0x013C - PerLanePtr
-  Pointer to array of PER_LANE_EPARAM_LINK_INFO
-**/
-  UINT32                      PerLanePtr;
-
-/** Offset 0x0140 - AllLanesSizeOfTable
-  Number of elements in AllLanesPtr array.
-**/
-  UINT32                      AllLanesSizeOfTable;
-
-/** Offset 0x0144 - PerLaneSizeOfTable
-  Number of elements in PerLanePtr array.
-**/
-  UINT32                      PerLaneSizeOfTable;
-
-/** Offset 0x0148 - WaitTimeForPSBP
-  Enable or Disable WaitTimeForPSBP
-**/
-  UINT32                      WaitTimeForPSBP;
-
-/** Offset 0x014C - WaSerializationEn
-  Enable or Disable WaSerializationEn - <b>0: Disable(Default)</b>, 1: Enable.
-  0:Disable, 1:Enable
-**/
-  UINT8                       WaSerializationEn;
-
-/** Offset 0x014D - KtiInEnableMktme
-  Enable or Disable KtiInEnableMktme - <b>0: Disable(Default)</b>, 1: Enable.
-  0:Disable, 1:Enable
-**/
-  UINT8                       KtiInEnableMktme;
-
-/** Offset 0x014E - HIOP STACK DISABLE
-  Enables/Disables given HIOP STACK. Default is AUTO no stack is disabled. 1 - The
-  stacks indicated by the bit locations are disabled. 0 - The stacks indicated by
-  the bit locations are not modified. The stack order is abstracted each bit 0 =
-  stack 0 ... bit n = stack n. The bit setting for each stack can be overriden by
-  BIOS based on part-knob compatibility. The array size must be MAX_SOCKET x UINT32.
-**/
-  UINT8                       StackDisableBitMap[32];
-
-/** Offset 0x016E - CFRS3mProvision
-  Enable or Disable Provision S3M CFR - <b>0: Disable(Default)</b>, 1: Enable.
-  0:Disable, 1:Enable
-**/
-  UINT8                       CFRS3mProvision;
-
-/** Offset 0x016F - CFRS3mManualCommit
-  Enable or Disable Manual Commit S3M FW CFR - <b>0:Disable(Default)</b>, 1:Enable.
-  0:Disable, 1:Enable
-**/
-  UINT8                       CFRS3mManualCommit;
-
-/** Offset 0x0170 - CFRPucodeProvision
-  Enable or Disable Provision PUcode CFR - <b>0:Disable(Default)</b>, 1:Enable.
-  0:Disable, 1:Enable
-**/
-  UINT8                       CFRPucodeProvision;
-
-/** Offset 0x0171 - CFRPucodeManualCommit
-  Enable or Disable Manual Commit PUcode CFR - <b>0:Disable(Default)</b>, 1:Enable.
-  0:Disable, 1:Enable
-**/
-  UINT8                       CFRPucodeManualCommit;
-
-/** Offset 0x0172
-**/
-  UINT8                       UnusedUpdSpace3[2];
-
-/** Offset 0x0174 - CFRImagePtr
-  Pointer to array of CFR Image
-**/
-  UINT32                      CFRImagePtr;
-
-/** Offset 0x0178 - Processor VmxEnable Function
-  Enable(Default) or Disable Processor VmxEnable Function - 0: Disable, <b>1: Enable(Default)</b>.
-  0:Disable, 1:Enable
-**/
-  UINT8                       VmxEnable;
-
-/** Offset 0x0179 - Processor X2apic Function
-  Enable(Default) or Disable Processor X2apic Function - 0: Disable, <b>1: Enable(Default)</b>.
-  0:Disable, 1:Enable
-**/
-  UINT8                       X2apic;
-
-/** Offset 0x017A - Processor HyperThreading Function
-  Enable(Default) or Disable Processor HyperThreading Function - 1: Disable, <b>0:
-  Enable(Default)</b>.
-  1:Disable, 0:Enable
-**/
-  UINT8                       ProcessorHyperThreadingDisable;
-
-/** Offset 0x017B - Processor Dynamic Intel Speed Select (ISS) Function
-  Enable or Disable(Default) Processor Dynamic Intel Speed Select (ISS) Function -
-  <b>0: Disable(Default)</b>, 1: Enable.
-  0:Disable, 1:Enable
-**/
-  UINT8                       ProcessorDynamicIssEnable;
-
-/** Offset 0x017C - Enables Intel(R) TXT
-  Enable or Disable(Default) Enables Intel(R) TXT - <b>0: Disable(Default)</b>, 1: Enable.
-  0:Disable, 1:Enable
-**/
-  UINT8                       ProcessorLtsxEnable;
-
-/** Offset 0x017D - DDR frequency limit
-  Select DDR frequency limit, <b>0x00: Auto(Default)</b>, 0x13:DDR_3200, 0x16:DDR_3600,
-  0x19:DDR_4000, 0x1C:DDR_4400, 0x1D:DDR_4800, 0x1E:DDR_5200, 0x1F:DDR_5600
-**/
-  UINT8                       DdrFreqLimit;
-
-/** Offset 0x017E - Memory Serial Debug Message Level
-  Select Memory Serial Debug Message Level - 0: Disable, 1: Minimum, 2: Normal, <b>3:
-  Maximum(Default)</b>, 4: Auto.
-  0:Disable, 1:Minimum, 2:Normal, 3:Maximum, 4:Auto
-**/
-  UINT8                       serialDebugMsgLvl;
-
-/** Offset 0x017F - IIO ConfigIOU0
-  ConfigIOU[MAX_SOCKET][0]: MAX_SOCKET=8, 0x00:x4x4x4x4, 0x01:x4x4xxx8, 0x02:xxx8x4x4,
-  0x03:xxx8xxx8, 0x04:xxxxxx16, <b>0xFF:AUTO(Default)</b>
-**/
-  UINT8                       IioConfigIOU0[8];
-
-/** Offset 0x0187 - IIO ConfigIOU1
-  ConfigIOU[MAX_SOCKET][1]: MAX_SOCKET=8, 0x00:x4x4x4x4, 0x01:x4x4xxx8, 0x02:xxx8x4x4,
-  0x03:xxx8xxx8, 0x04:xxxxxx16, <b>0xFF:AUTO(Default)</b>
-**/
-  UINT8                       IioConfigIOU1[8];
-
-/** Offset 0x018F - IIO ConfigIOU2
-  ConfigIOU[MAX_SOCKET][2]: MAX_SOCKET=8, 0x00:x4x4x4x4, 0x01:x4x4xxx8, 0x02:xxx8x4x4,
-  0x03:xxx8xxx8, 0x04:xxxxxx16, <b>0xFF:AUTO(Default)</b>
-**/
-  UINT8                       IioConfigIOU2[8];
-
-/** Offset 0x0197 - IIO ConfigIOU3
-  ConfigIOU[MAX_SOCKET][3]: MAX_SOCKET=8, 0x00:x4x4x4x4, 0x01:x4x4xxx8, 0x02:xxx8x4x4,
-  0x03:xxx8xxx8, 0x04:xxxxxx16, <b>0xFF:AUTO(Default)</b>
-**/
-  UINT8                       IioConfigIOU3[8];
-
-/** Offset 0x019F - IIO ConfigIOU4
-  ConfigIOU[MAX_SOCKET][4]: MAX_SOCKET=8, 0x00:x4x4x4x4, 0x01:x4x4xxx8, 0x02:xxx8x4x4,
-  0x03:xxx8xxx8, 0x04:xxxxxx16, <b>0xFF:AUTO(Default)</b>
-**/
-  UINT8                       IioConfigIOU4[8];
-
-/** Offset 0x01A7 - IIO ConfigIOU5
-  ConfigIOU[MAX_SOCKET][5]: MAX_SOCKET=8, 0x00:x4x4x4x4, 0x01:x4x4xxx8, 0x02:xxx8x4x4,
-  0x03:xxx8xxx8, 0x04:xxxxxx16, <b>0xFF:AUTO(Default)</b>
-**/
-  UINT8                       IioConfigIOU5[8];
-
-/** Offset 0x01AF - IIO ConfigIOU6
-  ConfigIOU[MAX_SOCKET][6]: MAX_SOCKET=8, 0x00:x4x4x4x4, 0x01:x4x4xxx8, 0x02:xxx8x4x4,
-  0x03:xxx8xxx8, 0x04:xxxxxx16, <b>0xFF:AUTO(Default)</b>
-**/
-  UINT8                       IioConfigIOU6[8];
-
-/** Offset 0x01B7
-**/
-  UINT8                       UnusedUpdSpace4;
-
-/** Offset 0x01B8 - IIO PCIE Config Table Ptr
-  Pointer to array of UPD_IIO_PCIE_PORT_CONFIG
-**/
-  UINT32                      IioPcieConfigTablePtr;
-
-/** Offset 0x01BC - IIO PCIE Config Table Number
-  Number of elements in IioPcieConfigTablePtr array, socket number as unit.
-**/
-  UINT32                      IioPcieConfigTableNumber;
-
-/** Offset 0x01C0 - IIO DeEmphasis Array Ptr
-  Pointer to array of DeEmphasis
-**/
-  UINT32                      DeEmphasisPtr;
-
-/** Offset 0x01C4 - IIO DeEmphasis Array Number
-  Number of elements in DeEmphasis array.
-**/
-  UINT32                      DeEmphasisNumber;
-
-/** Offset 0x01C8 - IIO PCIe Common Clock Array Ptr
-  Pointer to array of PCIe Common Clock
-**/
-  UINT32                      PcieCommonClockPtr;
-
-/** Offset 0x01CC - IIO PCIe Common Clock Array Number
-  Number of elements in PCIe Common Clock array.
-**/
-  UINT32                      PcieCommonClockNumber;
-
-/** Offset 0x01D0 - VT-d Support
-  Enable or Disable VT-d Support - 0: Disable, <b>1: Enable(Default)</b>.
-  0:Disable, 1:Enable
-**/
-  UINT8                       VtdSupport;
-
-/** Offset 0x01D1 - PCIe ACSCTL
-  Enable/Disable overwrite of PCI Access Control Services Control register in PCI
-  root ports - 0: Disable, <b>1: Enable(Default)</b>.
-  0:Disable, 1:Enable
-**/
-  UINT8                       VtdPciAcsCtlWaEn;
-
-/** Offset 0x01D2
-**/
-  UINT8                       UnusedUpdSpace5[2];
-
-/** Offset 0x01D4 - IIO PCIe Port Hide Array Ptr
-  Pointer to array of Hide or visible for IIO Pcie Port.
-**/
-  UINT32                      PEXPHIDEPtr;
-
-/** Offset 0x01D8 - IIO PCIe Port Hide Array Number
-  Number of elements in IIO PCIe Port Hide Array.
-**/
-  UINT32                      PEXPHIDENumber;
-
-/** Offset 0x01DC - PcieHotPlugEnable
-  Enable or disable Pcie hot plug enable feature - <b>0: Disable(Default)</b>, 1: Enable.
-  0:Disable, 1:Enable
-**/
-  UINT8                       PcieHotPlugEnable;
-
-/** Offset 0x01DD
-**/
-  UINT8                       UnusedUpdSpace6;
-
-/** Offset 0x01DE - DelayAfterPCIeLinkTraining
-  Custom delay after PCI-E link training on IIO ports
-**/
-  UINT16                      DelayAfterPCIeLinkTraining;
-
-/** Offset 0x01E0 - IIO PCI bus resource Ptr
-  Pointer to array of socket PCI bus resource.
-**/
-  UINT32                      PciBusResConfigPtr;
-
-/** Offset 0x01E4 - IIO PCI IO/MMIO base and limits resource Ptr
-  Pointer to array of socket PCI IO/MMIO resource.
-**/
-  UINT32                      PciBaseLimitsResConfigPtr;
-
-/** Offset 0x01E8 - PCH PCIE PLL Ssc
-  Pointer to array of socket PCI IO/MMIO resource.
-**/
-  UINT8                       PchPciePllSsc;
-
-/** Offset 0x01E9 - MeUmaEnable
-  Enable or disable ME UMA feature - <b>0: Disable(Default)</b>, 1: Enable.
-  0:Disable, 1:Enable
-**/
-  UINT8                       MeUmaEnable;
-
-/** Offset 0x01EA - SerialIoUartDebugEnable
-  Enable or Disable SerialIo Uart debug library in FSP - 0: Disable, <b>1: Enable(Default)</b>.
-  0:Disable, 1:Enable
-**/
-  UINT8                       SerialIoUartDebugEnable;
-
-/** Offset 0x01EB
-**/
-  UINT8                       UnusedUpdSpace7;
-
-/** Offset 0x01EC - ISA Serial Base selection
-  Select ISA Serial Base address could be initialized by boot loader - 0x2F8: 0x2F8,
-  <b>0x3F8: 0x3F8(Default)</b>.
-  0x2F8:0x2F8, 0x3F8:0x3F8
-**/
-  UINT16                      SerialIoUartDebugIoBase;
-
-/** Offset 0x01EE - MemRefreshWaterMark
-  Enable or Disable MemRefreshWaterMark in FSP - <b>0: Auto(Default)</b>, 1: Enable,
-  2: Disable.
-  0:Auto, 1:Enable, 2:Disable
-**/
-  UINT8                       PanicWm;
-
-/** Offset 0x01EF - promoteMrcWarnings
-  Enable or Disable MRC promote warning in FSP - 0: Disable, <b>1: Enable(Default)</b>.
-  0:Disable, 1:Enable
-**/
-  UINT8                       promoteMrcWarnings;
-
-/** Offset 0x01F0 - promoteWarnings
-  <b>Enable(Default)</b> or Disable Promote warning in FSP - 0: Disable, <b>1: Enable(Default)</b>.
-  0:Disable, 1:Enable
-**/
-  UINT8                       promoteWarnings;
-
-/** Offset 0x01F1 - serialDebugMsgLvlTrainResults
-  Enable or Disable Promote warning in FSP - <b>0:Disable(Default)</b>, 8:Enable.
-  0:Disable, 8:Enable
-**/
-  UINT8                       serialDebugMsgLvlTrainResults;
-
-/** Offset 0x01F2 - MemTest
-  <b>Enable(Default)</b> or Disable memory test during normal boot in FSP - 0: Disable,
-  <b>1: Enable(Default)</b>.
-  0:Disable, 1:Enable
-**/
-  UINT8                       HwMemTest;
-
-/** Offset 0x01F3
-**/
-  UINT8                       UnusedUpdSpace8;
-
-/** Offset 0x01F4 - MemTest Loops
-  Number of memory test loops during normal boot, set to 0 to run memtest infinitely
-  in FSP - <b> 1 (Default)</b>.
-  minimum = 0, maximum = 65535
-**/
-  UINT16                      MemTestLoops;
-
-/** Offset 0x01F6
-**/
-  UINT8                       UnusedUpdSpace9[2];
-
-/** Offset 0x01F8 - Adv MemTest Options
-  This option is a bit mask[19:0]: All 0 = disabled: bit-0=XMATS8, bit-1=XMATS16,
-  bit-2=Reserved, bit-3=Reserved, bit-4=WCMATS8, bit-5=WCMCH8, bit-6=Reserved, bit-7=MARCHCM64,
-  bit-8=Reserved, bit-9=Reserved, bit-10=Reserved, bit-11=TWR, bit-12=DATARET, bit-13=MATS8TC1,
-  bit-14=MATS8TC2, bit-15=MATS8TC3, bit-16=SK-HYNIX, bit-17=SAMSUNG, bit-18=MICRON-RMW,
-  bit-19=SCRAM_X2 in FSP.
-**/
-  UINT32                      AdvMemTestOptions;
-
-/** Offset 0x01FC - SmartTestKey
-  Number of SmartTest Key
-**/
-  UINT32                      SmartTestKey;
-
-/** Offset 0x0200 - Adv MemTest Pause
-  Specify a pause delay between 0 to 256000 in units of usec. This is a time period
-  where refresh is disabled between write and read sequences in FSP.
-**/
-  UINT32                      AdvMemTestCondPause;
-
-/** Offset 0x0204 - Adv MemTest tREFI
-  Specify tREFI (refresh rate) timing between 1850 to 7800 in nsec.
-**/
-  UINT16                      AdvMemTestCondTrefi;
-
-/** Offset 0x0206 - Adv MemTest tWR
-  Specify tWR timing between 48 to 96 in units of tCK in FSP.
-**/
-  UINT8                       AdvMemTestCondTwr;
-
-/** Offset 0x0207
-**/
-  UINT8                       UnusedUpdSpace10;
-
-/** Offset 0x0208 - Adv MemTest PMIC VDD Level
-  Specify PMIC VDD level in units of mV in FSP.
-**/
-  UINT16                      AdvMemTestCondPmicVdd;
-
-/** Offset 0x020A - Adv MemTest Conditions
-  Auto = set test conditions based on test type; Manual = specify global test conditions;
-  Disable = Do not apply test conditions in FSP - 0: Disable, <b>1: Auto(Default)</b>,
-  2: Manual.
-  0:Disable, 1:Auto, 2:Manual
-**/
-  UINT8                       AdvMemTestCondition;
-
-/** Offset 0x020B - Adv MemTest Reset Failure Tracking List
-  Enable/disable Reset of the Row Failure Tracking List after each Adv MemTest option.
-  Useful for testing performance of multiple options in FSP - <b>0: Disable(Default)</b>,
-  1: Enable.
-  0:Disable, 1:Enable
-**/
-  UINT8                       AdvMemTestResetList;
-
-/** Offset 0x020C - MemTest On Cold Fast Boot
-  Enable - Enables memory test during cold fast boot. Disable - Disables this feature.
-  Auto - Sets it to the MRC default setting; current default is Disable in FSP -
-  <b>0:Disable(Default)</b>, 1:Enable.
-  0:Disable, 1:Enable
-**/
-  UINT8                       MemTestOnColdFastBoot;
-
-/** Offset 0x020D - Attempt Fast Boot
-  Enable - Portions of memory reference code will be skipped when possible to increase
-  boot speed on warm boots. Disable - Disables this feature. Auto - Sets it to the
-  MRC default setting - 0:Disable, <b>1:Enable(Default)</b>.
-  0:Disable, 1:Enable
-**/
-  UINT8                       AttemptFastBoot;
-
-/** Offset 0x020E - MemTest On Cold Fast Boot
-  Enable - Enables memory test during cold fast boot. Disable - Disables this feature.
-  Auto - Sets it to the MRC default setting - 0:Disable, <b>1:Enable(Default)</b>.
-  0:Disable, 1:Enable
-**/
-  UINT8                       AttemptFastBootCold;
-
-/** Offset 0x020F - Multithreaded Memory Training
-  Selects the number of processor sockets to train in parallel. - <b>0: All sockets
-  operate in parallel(Default)</b>. 1: At any time only one socket is executing.
-  2: At any time only two socket are executing. 4: At any time only four socket are
-  executing in FSP.
-  0:All Processor Sockets, 1:One Socket at a Time (No Multithreading), 2:Two Sockets
-  at a Time, 4:Four Sockets at a Time
-**/
-  UINT8                       AllowedSocketsInParallel;
-
-/** Offset 0x0210 - Auto-Reset on mem Training Error
-  Enable/Disable Auto-Reset on mem Training Error in FSP - <b>0:Disable(Default)</b>,
-  1:Enable.
-  0:Disable, 1:Enable
-**/
-  UINT8                       AutoResetOnMemErr;
-
-/** Offset 0x0211 - Rank Margin Tool
-  Enable/Disable the Rank Margin Tool in FSP - <b>0:Disable(Default)</b>, 1:Enable.
-  0:Disable, 1:Enable
-**/
-  UINT8                       EnableRMT;
-
-/** Offset 0x0212 - RMT on Fast Cold Boot
-  Enable/Disable the Rank Margin Tool on a Fast Cold Boot in FSP - <b>0:Disable(Default)</b>,
-  1:Enable.
-  0:Disable, 1:Enable
-**/
-  UINT8                       EnableRMTonFCB;
-
-/** Offset 0x0213 - Execute Jedecinit before RMT
-  Execute Jedecinit before Rank Margin Tool in FSP - <b>0:Disable(Default)</b>, 1:Enable.
-  0:Disable, 1:Enable
-**/
-  UINT8                       JedecInitBeforeRMT;
-
-/** Offset 0x0214 - Backside Margining
-  Enable/Disable margin test on the register or buffer backside in FSP - <b>0:Disable(Default)</b>,
-  1:Enable.
-  0:Disable, 1:Enable
-**/
-  UINT8                       RMTBacksideMargining;
-
-/** Offset 0x0215 - CmdAll
-  Step size of CmdAll. Auto: 1. Supported values: 1,2,4,8 in FSP - <b>1:Auto(Default)</b>,
-  2:2, 4:4, 8:8.
-  1:Auto, 2:2, 4:4, 8:8
-**/
-  UINT8                       RMTCmdAll;
-
-/** Offset 0x0216 - RMT Debug Messages
-  Enable/Disable the RMT debug messages in FSP - <b>2:Disable(Default)</b>, 5:Enable.
-  2:Disable, 5:Enable
-**/
-  UINT8                       RMTDebugMessages;
-
-/** Offset 0x0217 - RMT Display Tables
-  Enable/Disable displaying results as tables in FSP - 0:Disable, <b>1:Enable(Default)</b>.
-  0:Disable, 1:Enable
-**/
-  UINT8                       RMTDisplayTables;
-
-/** Offset 0x0218 - RMT Loop Count
-  Exponential loop count for single rank test in FSP.
-**/
-  UINT8                       RMTLoopCount;
-
-/** Offset 0x0219
-**/
-  UINT8                       UnusedUpdSpace11[3];
-
-/** Offset 0x021C - Test Signal Bit Mask For RMT
-  Test signal bit mask for RMT in FSP.
-**/
-  UINT32                      TestSignalBitMaskRMT;
-
-/** Offset 0x0220 - RMT Per Bit Margining
-  Enable/Disable Per Bit Margining in FSP - 0:Disable, <b>1:Enable(Default)</b>.
-  0:Disable, 1:Enable
-**/
-  UINT8                       RMTPerBitMargining;
-
-/** Offset 0x0221 - RMT Per CA Lane Margining
-  Enable/Disable Per CA Lane Margining in FSP - 0:Disable, <b>1:Enable(Default)</b>.
-  0:Disable, 1:Enable
-**/
-  UINT8                       RMTPerCaLaneMargining;
-
-/** Offset 0x0222 - RMT Display Plots
-  Enable/Disable the display of per-bit results as plots in FSP - 0:Disable, <b>1:Enable(Default)</b>.
-  0:Disable, 1:Enable
-**/
-  UINT8                       RMTPerDisplayPlots;
-
-/** Offset 0x0223 - RMT RxDqs
-  Step size of RxDqs. Auto: 1. Supported values: 1,2,4,8 in FSP - <b>1:Auto,(Default)</b>
-  2:2, 4:4, 8:8.
-  1:Auto, 2:2, 4:4, 8:8
-**/
-  UINT8                       RMTRxDqs;
-
-/** Offset 0x0224 - RMT RxVref
-  Step size of RxVref. Auto: 1. Supported values: 1,2,4,8 in FSP - <b>1:Auto,(Default)</b>
-  2:2, 4:4, 8:8.
-  1:Auto, 2:2, 4:4, 8:8
-**/
-  UINT8                       RMTRxVref;
-
-/** Offset 0x0225 - RMT Scrambler
-  Enable or Disable scrambler during RMT test in FSP - 0:Disable, <b>1:Enable(Default)</b>.
-  0:Disable, 1:Enable
-**/
-  UINT8                       RMTScrambler;
-
-/** Offset 0x0226 - RMT Step Size Override
-  Enable or Disable overriding the default step sizes in FSP - <b>0:Disable(Default)</b>,
-  1:Enable.
-  0:Disable, 1:Enable
-**/
-  UINT8                       RMTStepSizeOverride;
-
-/** Offset 0x0227 - RMT TxDq
-  Step size of TxDq. Auto: 1. Supported values: 1,2,4,8 in FSP - <b>1:Auto(Default)</b>,
-  2:2, 4:4, 8:8.
-  1:Auto, 2:2, 4:4, 8:8
-**/
-  UINT8                       RMTTxDq;
-
-/** Offset 0x0228 - RMT TxVref
-  Step size of TxVref. Auto: 1. Supported values: 1,2,4,8 in FSP - <b>1:Auto(Default)</b>,
-  2:2, 4:4, 8:8.
-  1:Auto, 2:2, 4:4, 8:8
-**/
-  UINT8                       RMTTxVref;
-
-/** Offset 0x0229 - DDR5 ECS
-  Enable/Disable DDR5 Error Check and Scrub (ECS) in FSP - 0:Disable, <b>1:Enable(Default)</b>.
-  0:Disable, 1:Enable
-**/
-  UINT8                       ErrorCheckScrub;
-
-/** Offset 0x022A - Enforce Memory POR
-  0:Enforce POR - Enforces Plan Of Record restrictions for DDR5 frequency and voltage
-  programming. <b>2:Disable  - Disables this feature and user is able to run at higher
-  frequencies, specified in the DDR Frequency Limit field (limited by processor support)(Default)</b>.
-  0:Enforce POR, 2:Disabled
-**/
-  UINT8                       EnforceDdrMemoryFreqPor;
-
-/** Offset 0x022B - Enforce Population POR
-  Enable Memory Population POR Enforcement.  Selecting Enforce Validated Populations
-  will only allow populations that have been validated in FSP - <b>0:Disable(Default)</b>,
-  1:Enable.
-  0:Disable, 1:Enable
-**/
-  UINT8                       EnforcePopulationPor;
-
-/** Offset 0x022C - DDR PPR Type
-  Selects DDR Post Package Repair Type - 2: Hard PPR, <b>1: Soft PPR (Default)</b>,
-  0: Disabled.
-  0:Disabled, 2:Hard PPR, 1:Soft PPR
-**/
-  UINT8                       pprType;
-
-/** Offset 0x022D - Force PPR On All Dram for UCE
-  Force PPR on all dram for UCE in FSP - <b>0:Disable(Default)</b>, 1:Enable.
-  0:Disabled, 1:Enabled
-**/
-  UINT8                       ForcePprOnAllDramUce;
-
-/** Offset 0x022E
-**/
-  UINT8                       UnusedUpdSpace12[2];
-
-/** Offset 0x0230 - pprAddrVariablePtr
-  Pointer to array of PPR_ADDR_VARIABLE
-**/
-  UINT32                      PprAddrVariablePtr;
-
-/** Offset 0x0234 - Allow Memory Test Correctable Error
-  Enable - Logs error and allows correctable errors during memory test(DIMM Rank not
-  removed). Disable - Logs error and removes DIMM Rank. Auto - Sets it to the MRC
-  default setting; current default is Enable in FSP - 0:Disable, <b>1:Enable(Default)</b>.
-  0:Disable, 1:Enable
-**/
-  UINT8                       allowCorrectableMemTestError;
-
-/** Offset 0x0235 - Memory I/O Health Check
-  Memory I/O Health Check - 0: Auto, 1: Manual, <b>2: Disable (Default)</b>. Select
-  option Auto for default values. Manual for new values. Disable for disabling feature
-  in FSP - 0:Auto, 1:Manual, <b>2:Disable(Default)</b>.
-  0:Auto, 1:Manual, 2:Disable
-**/
-  UINT8                       MemIOHealthCheck;
-
-/** Offset 0x0236 - RxDqsDelay Left Edge
-  Offset for RxDqsDelay Left Edge in FSP.
-**/
-  UINT8                       CriticalRxDqsDelayLeftEdge;
-
-/** Offset 0x0237 - RxDqsDelay Right Edge
-  Offset for RxDqsDelay Right in FSP.
-**/
-  UINT8                       CriticalRxDqsDelayRightEdge;
-
-/** Offset 0x0238 - RxVref Left Edge
-  Offset for RxVref Left Edge in FSP.
-**/
-  UINT8                       CriticalRxVrefLeftEdge;
-
-/** Offset 0x0239 - RxVref Right Edge
-  Offset for RxVref Right Edge in FSP.
-**/
-  UINT8                       CriticalRxVrefRightEdge;
-
-/** Offset 0x023A - TxDqDelay Left Edge
-  Offset for TxDqDelay Left Edge in FSP.
-**/
-  UINT8                       CriticalTxDqDelayLeftEdge;
-
-/** Offset 0x023B - TxDqDelay Right Edge
-  Offset for TxDqDelay Right Edge in FSP.
-**/
-  UINT8                       CriticalTxDqDelayRightEdge;
-
-/** Offset 0x023C - TxVref Left Edge
-  Offset for TxDqDelay Left Edge in FSP.
-**/
-  UINT8                       CriticalTxVrefLeftEdge;
-
-/** Offset 0x023D - TxVref Right Edge
-  Offset for TxDqDelay Right Edge in FSP.
-**/
-  UINT8                       CriticalTxVrefRightEdge;
-
-/** Offset 0x023E - Reboot On Critical Failure
-  Reboot System on Critical failure to do Memory Training in FSP - 0:Disable, <b>1:Enable(Default)</b>.
-  0:Disable, 1:Enable
-**/
-  UINT8                       ResetOnCriticalError;
-
-/** Offset 0x023F - Number of Times to Reboot and Retrain
-  Number of times to Reboot System on Critical failure to do Memory Training in FSP.
-**/
-  UINT8                       CriticalRetries;
-
-/** Offset 0x0240 - Memory I/O Health Check Loop Count
-  CPGC Test Loop Count for Memory IO Health Test
-**/
-  UINT8                       MemIOHealthLoopCount;
-
-/** Offset 0x0241 - Telemetry RxDqsDelay Left Edge
-  Offset for Telemetry RxDqsDelay Left Edge in FSP.
-**/
-  UINT8                       TelemetryRxDqsDelayLeftEdge;
-
-/** Offset 0x0242 - Telemetry RxDqsDelay Right Edge
-  Offset for Telemetry RxDqsDelay Right Edge in FSP.
-**/
-  UINT8                       TelemetryRxDqsDelayRightEdge;
-
-/** Offset 0x0243 - Telemetry RxVref Left Edge
-  Offset for Telemetry RxDqsDelay Left Edge in FSP.
-**/
-  UINT8                       TelemetryRxVrefLeftEdge;
-
-/** Offset 0x0244 - Telemetry RxVref Right Edge
-  Offset for Telemetry RxDqsDelay Right Edge in FSP.
-**/
-  UINT8                       TelemetryRxVrefRightEdge;
-
-/** Offset 0x0245 - Telemetry TxDqDelay Left Edge
-  Offset for Telemetry TxDqDelay Left Edge in FSP.
-**/
-  UINT8                       TelemetryTxDqDelayLeftEdge;
-
-/** Offset 0x0246 - Telemetry TxDqDelay Right Edge
-  Offset for Telemetry TxDqDelay Right Edge in FSP.
-**/
-  UINT8                       TelemetryTxDqDelayRightEdge;
-
-/** Offset 0x0247 - Volatile Memory Mode
-  Selects 1LM or 2LM mode for volatile memory. For 2LM memory mode, system will try
-  to configure 2LM but if system is unable to configure 2LM, volatile memory mode
-  will fall back to 1LM in FSP - <b>0: 1LM(Default)</b>, 1: 2LM, 2: MIX 1LM2LM.
-  0: 1LM, 1: 2LM, 2: MIX 1LM2LM
-**/
-  UINT8                       volMemMode;
-
-/** Offset 0x0248 - Dynamic ECC Mode Selection
-  Enable/Disable Dynamic ECC Mode Selection in FSP - 0:Disable, <b>1:Enable(Default)</b>,
-  2:Enable + Allow 128b ECC.
-  0:Disable, 1:Enable, 2:Enable + Allow 128b ECC
-**/
-  UINT8                       DynamicEccModeSel;
-
-/** Offset 0x0249 - Memory Patrol Scrub
-  Memory Patrol Scrub - 0:Disable, 1:Enable during FspMemoryInit(), <b>2:Enable during
-  NotifyPhase(EnumInitPhaseReadyToBoot) (Default)</b>.
-  0:Disable, 1:Enable during FspMemoryInit(), 2:Enable during EnumInitPhaseReadyToBoot
-**/
-  UINT8                       PatrolScrub;
-
-/** Offset 0x024A - Memory Patrol Scrub
-  Memory Patrol Scrub - <b>0:Disable  (Default)</b>, 1:Enable at ReadyToBootFsp().
-  0:Disable, 1:Enable Enable at ReadyToBootFsp()
-**/
-  UINT8                       PatrolScrubNotify;
-
-/** Offset 0x024B - Patrol Scrub Interval
-  Patrol Scrub Interval in FSP.
-**/
-  UINT8                       PatrolScrubDuration;
-
-/** Offset 0x024C - Patrol Scrub Address Mode
-  Selects the address mode between <b>1: System Physical Address (Default)</b>, 0:Reverse
-  Address in FSP.
-  0:Reverse Address, 1:System Physical Address
-**/
-  UINT8                       PatrolScrubAddrMode;
-
-/** Offset 0x024D - Memory Thermal Throttling Mode
-  Memory Configure Memory Thermal Throttling Mode in FSP - 0:Disable, <b>2:CLTT_ENABLE(Default)</b>,
-  3:CLTT_PECI_ENABLE.
-  0:Disable, 2:CLTT_ENABLE, 3:CLTT_PECI_ENABLE
-**/
-  UINT8                       thermalthrottlingsupport;
-
-/** Offset 0x024E - Memory Correctable Error Threshold
-  Memory Correctable Error Threshold (1 - 32767) used for sparing and leaky bucket in FSP.
-**/
-  UINT16                      spareErrTh;
-
-/** Offset 0x0250 - WR CRC feature Control
-  Enable/Disable Write CRC in FSP - <b>0:Disable(Default)</b>, 1:Enable.
-  0:Disable, 1:Enable
-**/
-  UINT8                       WrCRC;
-
-/** Offset 0x0251 - Adaptive Refresh Management Level
-  Selects Adaptive Refresh Management(ARFM) Level when refresh management(RFM) is
-  required. <b>0:Default - RAAIMT, RAAMMT, RAADEC(Default)</b>; 1:Level A - RAAIMT-A,
-  RAAMMT-A, RAADEC-A; 2:Level B - RAAIMT-B, RAAMMT-B, RAADEC-B; 3:Level C - RAAIMT-C,
-  RAAMMT-C, RAADEC-C
-  0:Default - RAAIMT; RAAMMT; RAADEC, 1:Level A - RAAIMT-A; RAAMMT-A; RAADEC-A, 2:Level
-  B - RAAIMT-B; RAAMMT-B; RAADEC-B, 3:Level C - RAAIMT-C; RAAMMT-C; RAADEC-C
-**/
-  UINT8                       AdaptiveRefreshMgmtLevel;
-
-/** Offset 0x0252 - MEMHOT INPUT Control
-  Enable/Disable MEMHOT INPUT in FSP - <b>0:Disable(Default)</b>, 1:Enable.
-  0:Disable, 1:Enable
-**/
-  UINT8                       MemHotIn;
-
-/** Offset 0x0253 - MEMHOT OUTPUT Mode
-  MEMHOT OUTPUT Mode in FSP - 0:Disable, <b>1:Enable only temphi(Default)</b>, 2:Enable
-  temphi & mid, 3:Enable temphi & mid & low.
-  0:Disable, 1:Enable only temphi, 2:Enable temphi & mid, 3:Enable temphi & mid & low
-**/
-  UINT8                       MemhotOutputOnlyOpt;
-
-/** Offset 0x0254 - CxlType3LegacyEn
-  Enable or disable CXL type 3 device using CXL type 2 flow - <b>0:Disable(Default)</b>, 1:Enable.
-  0:Disable, 1:Enable
-**/
-  UINT8                       DfxCxlType3LegacyEn;
-
-/** Offset 0x0255 - DfxPmicSecureMode
-  0:Disable Pmic Secure Mode, 1:Enable Pmic Secure Mode, <b>2:Auto Pmic Secure Mode(Default)</b>.
-  0:Disable Pmic Secure Mode, 1:Enable Pmic Secure Mode, 2:Auto Pmic Secure Mode
-**/
-  UINT8                       DfxPmicSecureMode;
-
-/** Offset 0x0256 - IIO PcieSubSystemMode0
-  PcieSubSystemMode[MAX_SOCKET][0]: MAX_SOCKET=8, 0x00:IIO_MODE_GEN4_ONLY, 0x01:IIO_MODE_GEN5,
-  0x02:IIO_MODE_CXL, 0x03:IIO_MODE_FORCE_CXL, <b>0x01:IIO_MODE_GEN5(Default)</b>
-**/
-  UINT8                       IioPcieSubSystemMode0[8];
-
-/** Offset 0x025E - IIO PcieSubSystemMode1
-  PcieSubSystemMode[MAX_SOCKET][0]: MAX_SOCKET=8, 0x00:IIO_MODE_GEN4_ONLY, 0x01:IIO_MODE_GEN5,
-  0x02:IIO_MODE_CXL, 0x03:IIO_MODE_FORCE_CXL, <b>0x01:IIO_MODE_GEN5(Default)</b>
-**/
-  UINT8                       IioPcieSubSystemMode1[8];
-
-/** Offset 0x0266 - IIO PcieSubSystemMode2
-  PcieSubSystemMode[MAX_SOCKET][0]: MAX_SOCKET=8, 0x00:IIO_MODE_GEN4_ONLY, 0x01:IIO_MODE_GEN5,
-  0x02:IIO_MODE_CXL, 0x03:IIO_MODE_FORCE_CXL, <b>0x01:IIO_MODE_GEN5(Default)</b>
-**/
-  UINT8                       IioPcieSubSystemMode2[8];
-
-/** Offset 0x026E - IIO PcieSubSystemMode3
-  PcieSubSystemMode[MAX_SOCKET][0]: MAX_SOCKET=8, 0x00:IIO_MODE_GEN4_ONLY, 0x01:IIO_MODE_GEN5,
-  0x02:IIO_MODE_CXL, 0x03:IIO_MODE_FORCE_CXL, <b>0x01:IIO_MODE_GEN5(Default)</b>
-**/
-  UINT8                       IioPcieSubSystemMode3[8];
-
-/** Offset 0x0276 - IIO PcieSubSystemMode4
-  PcieSubSystemMode[MAX_SOCKET][0]: MAX_SOCKET=8, 0x00:IIO_MODE_GEN4_ONLY, 0x01:IIO_MODE_GEN5,
-  0x02:IIO_MODE_CXL, 0x03:IIO_MODE_FORCE_CXL, <b>0x01:IIO_MODE_GEN5(Default)</b>
-**/
-  UINT8                       IioPcieSubSystemMode4[8];
-
-/** Offset 0x027E - IIO PcieSubSystemMode5
-  PcieSubSystemMode[MAX_SOCKET][0]: MAX_SOCKET=8, 0x00:IIO_MODE_GEN4_ONLY, 0x01:IIO_MODE_GEN5,
-  0x02:IIO_MODE_CXL, 0x03:IIO_MODE_FORCE_CXL, <b>0x01:IIO_MODE_GEN5(Default)</b>
-**/
-  UINT8                       IioPcieSubSystemMode5[8];
-
-/** Offset 0x0286 - IIO PcieSubSystemMode6
-  PcieSubSystemMode[MAX_SOCKET][0]: MAX_SOCKET=8, 0x00:IIO_MODE_GEN4_ONLY, 0x01:IIO_MODE_GEN5,
-  0x02:IIO_MODE_CXL, 0x03:IIO_MODE_FORCE_CXL, <b>0x01:IIO_MODE_GEN5(Default)</b>
-**/
-  UINT8                       IioPcieSubSystemMode6[8];
-
-/** Offset 0x028E - CXL Header Bypass
-  Enable/Disable the CXL header bypass in FSP - <b>0:Disabled(Default)</b>, 1:Enabled.
-  0:Disable, 1:Enable
-**/
-  UINT8                       DfxCxlHeaderBypass;
-
-/** Offset 0x028F - CXL Security Level
-  CXL Security Level<br>\n
-  0: Fully Trusted - CXL Device can get access on CXL.$ for host-attached and device
-  attached memory ranges in the WB address space.<br>\n
-  1: Partially Trusted - CXL Device can get access on CXL.$ for device attached memory
-  ranges only;<br>\n
-  2: Untrusted - All requests on CXL.$ will be aborted by the Host.<br>\n
-  <b>3: Auto - Currently identical to Fully Trusted. (Default)</b>
-  0:Fully Trusted, 1:Partially Trusted, 2:Untrusted, 3:Auto
-**/
-  UINT8                       DfxCxlSecLvl;
-
-/** Offset 0x0290
-**/
-  UINT32                      DfxCxlDebugModePtr;
-
-/** Offset 0x0294
-**/
-  UINT32                      DfxCxlDebugModeNumber;
-
-/** Offset 0x0298 - Lock Chipset
-  Lock or Unlock chipset in FSP - <b>0:Disabled(Default)</b>, 1:Enabled.
-  0:Disable, 1:Enable
-**/
-  UINT8                       LockChipset;
-
-/** Offset 0x0299 - MSR Lock Control
-  Enable - MSR 3Ah and CSR 80h will be locked in FSP. Power Good reset is needed to
-  remove lock bits - <b>0:Disabled(Default)</b>, 1:Enabled.
-  0:Disable, 1:Enable
-**/
-  UINT8                       ProcessorMsrLockControl;
-
-/** Offset 0x029A - DFX Enable
-  When Enabled, Expose IIO DFX devices and other CPU devices like PMON in FSP - <b>0:Disabled(Default)</b>,
-  1:Enabled.
-  0:Disable, 1:Enable
-**/
-  UINT8                       DFXEnable;
-
-/** Offset 0x029B - DFX Disable Bios Done
-  When Enabled, suppresses notifying processor via MSR 151h that boot initialization
-  is finished in FSP - <b>0:Disabled(Default)</b>, 1:Enabled.
-  0:Disable, 1:Enable
-**/
-  UINT8                       DfxDisableBiosDone;
-
-/** Offset 0x029C - Processor Package C State
-  Package C State - 0: C0/C1 state, 1: C2 state, 2: C6(non Retention) state, 3: C6(Retention)
-  state, 7: No Limit, <b>0xFF: Auto (Default)</b>
-  0: C0/C1 state, 1: C2 state, 2: C6(non Retention) state, 3: C6(Retention) state,
-  7: No Limit, 0xFF: Auto
-**/
-  UINT8                       CpuPmPackageCState;
-
-/** Offset 0x029D - Enhanced Intel SpeedStep(R) Tech
-  Enhanced Intel SpeedStep(R) Tech - <b>1: Enable(Default)</b>, 0: Disable.
-  0:Disabled, 1:Enabled
-**/
-  UINT8                       CpuPmEistEnable;
-
-/** Offset 0x029E - C1E
-  C1E - <b>1: Enable(Default)</b>, 0: Disable.
-**/
-  UINT8                       CpuPmC1eEnable;
-
-/** Offset 0x029F - Intel SST-PP
-  Intel SST-PP Select allows user to choose level - <b>0xFF: Choose lowest level hardware
-  supported(Default)</b>, 0: Level 0, 3: Level 3, 4: Level 4.
-**/
-  UINT8                       CpuPmIssTdpLevel;
-
-/** Offset 0x02A0 - Activate SST-BF
-  SST-BF - <b>0: Disable (Default)</b>, 1: Enabled.
-  0:Disabled, 1:Enabled
-**/
-  UINT8                       CpuPmProcessorActivePbf;
-
-/** Offset 0x02A1
-**/
-  UINT8                       UnusedUpdSpace13[7];
-
-/** Offset 0x02A8 - Socket 0 Core Disable Bitmask
-  Set bit(s) to Disable or clear bit(s) to Enable core(s) on Socket 0. NOTE: Any core
-  disabled by user will force static SST-PP.
-**/
-  UINT64                      CpuPmCoreDisableBitmask0;
-
-/** Offset 0x02B0 - Socket 1 Core Disable Bitmask
-  Set bit(s) to Disable or clear bit(s) to Enable core(s) on Socket 1. NOTE: Any core
-  disabled by user will force static SST-PP.
-**/
-  UINT64                      CpuPmCoreDisableBitmask1;
-
-/** Offset 0x02B8
-**/
-  UINT8                       ReservedMemoryInitUpd[16];
-} FSPM_CONFIG;
-
-/** Fsp M UPD Configuration
-**/
-typedef struct {
-
-/** Offset 0x0000
-**/
-  FSP_UPD_HEADER              FspUpdHeader;
-
-/** Offset 0x0020
-**/
-  FSPM_ARCH_UPD               FspmArchUpd;
-
-/** Offset 0x0040
-**/
-  FSPM_CONFIG                 FspmConfig;
-
-/** Offset 0x02C8
-**/
-  UINT8                       UnusedUpdSpace14[6];
-
-/** Offset 0x02CE
-**/
-  UINT16                      UpdTerminator;
-} FSPM_UPD;
-
-#pragma pack()
-
-#endif
diff --git a/src/vendorcode/intel/fsp/fsp2_0/sapphirerapids_sp/FspsUpd.h b/src/vendorcode/intel/fsp/fsp2_0/sapphirerapids_sp/FspsUpd.h
deleted file mode 100644
index 79e09295af..0000000000
--- a/src/vendorcode/intel/fsp/fsp2_0/sapphirerapids_sp/FspsUpd.h
+++ /dev/null
@@ -1,286 +0,0 @@
-/** @file
-
-Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
-
-Redistribution and use in source and binary forms, with or without modification,
-are permitted provided that the following conditions are met:
-
-* Redistributions of source code must retain the above copyright notice, this
-  list of conditions and the following disclaimer.
-* Redistributions in binary form must reproduce the above copyright notice, this
-  list of conditions and the following disclaimer in the documentation and/or
-  other materials provided with the distribution.
-* Neither the name of Intel Corporation nor the names of its contributors may
-  be used to endorse or promote products derived from this software without
-  specific prior written permission.
-
-  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
-  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
-  THE POSSIBILITY OF SUCH DAMAGE.
-
-  This file is automatically generated. Please do NOT modify !!!
-
-**/
-
-#ifndef __FSPSUPD_H__
-#define __FSPSUPD_H__
-
-#include <FspUpd.h>
-
-#pragma pack(1)
-
-
-/** FSP-S Configuration
-**/
-typedef struct {
-
-/** Offset 0x0020 - Processor VmxEnable Function
-  Processor VmxEnable Function - <b>1: Enable(Default)</b>, 0: Disable Processor VmxEnable Function.
-  0: Disable, 1: Enable
-**/
-  UINT8                       VmxEnable;
-
-/** Offset 0x0021 - Processor TurboMode Function
-  Processor TurboMode Function - <b>1: Enable(Default)</b>, 0: Disable Processor TurboMode Function.
-  0: Disable, 1: Enable
-**/
-  UINT8                       TurboMode;
-
-/** Offset 0x0022 - Processor Safer Mode Extensions Function
-  Processor Safer Mode Extensions Function - <b>0: Disable(Default)</b>, 1: Enable
-  Processor Safer Mode Extensions Function.
-  0: Disable, 1: Enable
-**/
-  UINT8                       ProcessorSmxEnable;
-
-/** Offset 0x0023 - SstCp
-  SstCp - 1: Enable, <b>0: Disable SstCp(Default)</b>.
-  0: Disable, 1: Enable
-**/
-  UINT8                       SstCpSetting;
-
-/** Offset 0x0024 - SstCp Capable Status
-  SST-CP Capable Status in system - <b>0: Disable(Default)</b>, 1: Enable.
-  0: Disable, 1: Enable
-**/
-  UINT8                       SstCpCapableSystem;
-
-/** Offset 0x0025
-**/
-  UINT8                       UnusedUpdSpace0[1];
-
-/** Offset 0x0026 - PCH Protect Range Limit
-  Left shifted address by 12 bits with address bits 11:0 are assumed to be FFFh for
-  limit comparison.
-**/
-  UINT16                      PchProtectedRangeLimit[5];
-
-/** Offset 0x0030 - PCH Protect Range Base
-  Left shifted address by 12 bits with address bits 11:0 are assumed to be 0.
-**/
-  UINT16                      PchProtectedRangeBase[5];
-
-/** Offset 0x003A - PchAdrEn
-  PchAdr - <b>0: PLATFORM POR(Default)</b>, 1: FORCE ENABLE, 2:FORCE DISABLE.
-  0: PLATFORM POR, 1: FORCE ENABLE, 2: FORCE DISABLE
-**/
-  UINT8                       PchAdrEn;
-
-/** Offset 0x003B - EnableTme
-  EnableTme - <b>0: Disabled(Default)</b>, 1: Enabled, 2:Software Controlled.
-  0: Disabled, 1: Enabled, 2:Software Controlled
-**/
-  UINT8                       EnableTme;
-
-/** Offset 0x003C - EnableTmeBypass
-  EnableTmeBypass - <b>0: Disabled(Default)</b>, 1: Enabled.
-  0: Disabled, 1: Enabled
-**/
-  UINT8                       EnableTmeBypass;
-
-/** Offset 0x003D - SgxFactoryReset
-  SgxFactoryReset - <b>0: Disabled(Default)</b>, 1: Enabled.
-  0: Disabled, 1: Enabled
-**/
-  UINT8                       SgxFactoryReset;
-
-/** Offset 0x003E - EnableSgx
-  EnableSgx - <b>0: Disabled(Default)</b>, 1: Enabled.
-  0: Disabled, 1: Enabled
-**/
-  UINT8                       EnableSgx;
-
-/** Offset 0x003F - SgxPackageInfoInBandAccess
-  SgxPackageInfoInBandAccess - <b>0: Disabled(Default)</b>, 1: Enabled.
-  0: Disabled, 1: Enabled
-**/
-  UINT8                       SgxPackageInfoInBandAccess;
-
-/** Offset 0x0040 - SgxQoS
-  SgxQoS - 0: Disabled, <b>1: Enabled(Default)</b>.
-  0: Disabled, 1: Enabled
-**/
-  UINT8                       SgxQoS;
-
-/** Offset 0x0041 - EpochUpdate
-  EpochUpdate - 1: Change to New Random Owner EPOCHs, <b>2: Manual User Defined Owner
-  EPOCHs(Default)</b>.
-  1: Change to New Random Owner EPOCHs, 2: Manual User Defined Owner EPOCHs
-**/
-  UINT8                       EpochUpdate;
-
-/** Offset 0x0042 - SgxLeWr
-  SgxLeWr - <b>0: Disabled(Default)</b>, 1: Enabled.
-  0: Disabled, 1: Enabled
-**/
-  UINT8                       SgxLeWr;
-
-/** Offset 0x0043 - SgxDebugMode
-  SgxDebugMode - <b>0: Disabled(Default)</b>, 1: Enabled.
-  0: Disabled, 1: Enabled
-**/
-  UINT8                       SgxDebugMode;
-
-/** Offset 0x0044 - SgxAutoRegistrationAgent
-  SgxAutoRegistrationAgent - <b>0: Disabled(Default)</b>, 1: Enabled.
-  0: Disabled, 1: Enabled
-**/
-  UINT8                       SgxAutoRegistrationAgent;
-
-/** Offset 0x0045 - DfxSgxRegistrationServerSelect
-  DfxSgxRegistrationServerSelect - <b>0: SBX(Default)</b>, 1: PRX, 2:AUTO, 3:LIV,
-  4:SW Defined Server.
-  0: SBX, 1: PRX, 2:AUTO, 3:LIV, 4:SW Defined Server
-**/
-  UINT8                       DfxSgxRegistrationServerSelect;
-
-/** Offset 0x0046 - Processor Enable Monitor MWAIT
-  Processor Enable Monitor MWAIT - <b>1: Enable(Default)</b>, 0: Disable Processor
-  Monitor MWAIT.
-  0: Disabled, 1: Enabled
-**/
-  UINT8                       CpuPmMonitorMWait;
-
-/** Offset 0x0047 - Processor C6
-  Processor C6 - <b>1: Enable(Default)</b>, 0: Disable Processor C6 (ACPI C3) report to OS.
-  0: Disabled, 1: Enabled
-**/
-  UINT8                       CpuPmC6Enable;
-
-/** Offset 0x0048 - Hardware P-States
-  Hardware P-States - 0:  Disable: Hardware chooses a P-state based on OS Request
-  (Legacy P-States), <b>1:Native Mode:Hardware chooses a P-state based on OS guidance(Default)</b>,
-  2:Out of Band Mode:Hardware autonomously chooses a P-state (no OS guidance), 3:Native
-  Mode with No Legacy Support.
-  0: Disable, 1: Native Mode, 2: Out of Band Mode, 3: Native Mode with No Legacy Support
-**/
-  UINT8                       CpuPmProcessorHWPMEnable;
-
-/** Offset 0x0049 - Power Performance Tuning
-  Power Performance Tuning - <b>0: OS Controls EPB (Default)</b>, 1: BIOS Controls
-  EPB, 2: PECI Controls EPB.
-  0: OS Controls EPB, 1: BIOS Controls EPB, 2: PECI Controls EPB
-**/
-  UINT8                       CpuPmPwrPerfTuning;
-
-/** Offset 0x004A - Configure SST-BF
-  Allow (Default)/Disallow BIOS to configure SST-BF High Priority Cores so that SW
-  does not have to configure - 0:Disable, <b>1:Enable(Default)</b>.
-  0:Disable, 1:Enable
-**/
-  UINT8                       CpuPmProcessorConfigurePbf;
-
-/** Offset 0x004B - CF9 Global Reset Promotion
-  CF9 Global Reset Promotion - 1: Enable promoting CF9 reset to global, <b>0: Disable
-  promoting CF9 reset to global(Default)</b>.
-  0: Disabled, 1: Enabled
-**/
-  UINT8                       MeGrPromotionEnabled;
-
-/** Offset 0x004C - Global Reset Lock
-  Global Reset Lock - <b>1: Enable locking the joint ME and host reset capability(Default)</b>,
-  0: Disable locking the joint ME and host reset capability.
-  0: Disabled, 1: Enabled
-**/
-  UINT8                       MeGrLockEnabled;
-
-/** Offset 0x004D - Delayed Authentication Mode
-  Enable or disable Delayed Authentication Mode - <b>0: Disable(Default)</b>, 1: Enable.
-  0:Disable, 1:Enable
-**/
-  UINT8                       DelayedAuthenticationMode;
-
-/** Offset 0x004E - Delayed Authentication Mode Override
-  Enable or disable Delayed Authentication Mode Override - <b>0: Disable(Default)</b>,
-  1: Enable.
-  0:Disable, 1:Enable
-**/
-  UINT8                       DelayedAuthenticationModeOverride;
-
-/** Offset 0x004F - Core Bios Done Message
-  Enable or disable Core Bios Done message sent to ME - 0: Disable, <b>1: Enable(Default)</b>.
-  0:Disable, 1:Enable
-**/
-  UINT8                       CoreBiosDoneEnabled;
-
-/** Offset 0x0050 - End Of Post Message
-  Enable or disable sending END_OF_POST message to ME - 0: Disable, 1: Send in PEI,
-  <b>2: Send in DXE(Default)</b>.
-  0:Disable, 1:Send in PEI, 2:Send in DXE
-**/
-  UINT8                       EndOfPostMessage;
-
-/** Offset 0x0051 - HMRFPO_LOCK Message
-  Enable or disable sending HMRFPO_LOCK message to ME - 0: Disable, <b>1: Enable(Default)</b>.
-  0:Disable, 1:Enable
-**/
-  UINT8                       MeHmrfpoLockEnabled;
-
-/** Offset 0x0052 - HMRFPO_ENABLE Message
-  Enable or disable sending HMRFPO_ENABLE message to ME - <b>0: Disable(Default)</b>,
-  1: Enable.
-  0:Disable, 1:Enable
-**/
-  UINT8                       MeHmrfpoEnableEnabled;
-
-/** Offset 0x0053
-**/
-  UINT8                       UnusedUpdSpace1[1];
-
-/** Offset 0x0054
-**/
-  UINT8                       ReservedSiliconInitUpd[16];
-} FSPS_CONFIG;
-
-/** Fsp S UPD Configuration
-**/
-typedef struct {
-
-/** Offset 0x0000
-**/
-  FSP_UPD_HEADER              FspUpdHeader;
-
-/** Offset 0x0020
-**/
-  FSPS_CONFIG                 FspsConfig;
-
-/** Offset 0x0064
-**/
-  UINT8                       UnusedUpdSpace2[2];
-
-/** Offset 0x0066
-**/
-  UINT16                      UpdTerminator;
-} FSPS_UPD;
-
-#pragma pack()
-
-#endif
diff --git a/src/vendorcode/intel/fsp/fsp2_0/sapphirerapids_sp/FsptUpd.h b/src/vendorcode/intel/fsp/fsp2_0/sapphirerapids_sp/FsptUpd.h
deleted file mode 100644
index b8874112f8..0000000000
--- a/src/vendorcode/intel/fsp/fsp2_0/sapphirerapids_sp/FsptUpd.h
+++ /dev/null
@@ -1,109 +0,0 @@
-/** @file
-
-Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
-
-Redistribution and use in source and binary forms, with or without modification,
-are permitted provided that the following conditions are met:
-
-* Redistributions of source code must retain the above copyright notice, this
-  list of conditions and the following disclaimer.
-* Redistributions in binary form must reproduce the above copyright notice, this
-  list of conditions and the following disclaimer in the documentation and/or
-  other materials provided with the distribution.
-* Neither the name of Intel Corporation nor the names of its contributors may
-  be used to endorse or promote products derived from this software without
-  specific prior written permission.
-
-  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
-  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
-  THE POSSIBILITY OF SUCH DAMAGE.
-
-  This file is automatically generated. Please do NOT modify !!!
-
-**/
-
-#ifndef __FSPTUPD_H__
-#define __FSPTUPD_H__
-
-#include <FspUpd.h>
-
-#pragma pack(1)
-
-
-/** FSP-T Core UPD
-**/
-typedef struct {
-
-/** Offset 0x0020
-**/
-  UINT32                      MicrocodeRegionBase;
-
-/** Offset 0x0024
-**/
-  UINT32                      MicrocodeRegionLength;
-
-/** Offset 0x0028
-**/
-  UINT32                      CodeRegionBase;
-
-/** Offset 0x002C
-**/
-  UINT32                      CodeRegionLength;
-
-/** Offset 0x0030
-**/
-  UINT8                       Reserved1[16];
-} FSPT_CORE_UPD;
-
-/** FSP-T Configuration
-**/
-typedef struct {
-
-/** Offset 0x0040 - Disable Port80 output in FSP-T
-  Select Port80 Control in FSP-T - 0:VPD-Style, <b>1:Enable Port80 Output (Default)</b>,
-  2:Disable Port80 Output, refer to FSP Integration Guide for details.
-  0:VPD-Style, 1:Enable Port80 Output[Default], 2:Disable Port80 Output
-**/
-  UINT8                       FsptPort80RouteDisable;
-
-/** Offset 0x0041
-**/
-  UINT8                       ReservedTempRamInitUpd[31];
-} FSPT_CONFIG;
-
-/** Fsp T UPD Configuration
-**/
-typedef struct {
-
-/** Offset 0x0000
-**/
-  FSP_UPD_HEADER              FspUpdHeader;
-
-/** Offset 0x0020
-**/
-  FSPT_CORE_UPD               FsptCoreUpd;
-
-/** Offset 0x0040
-**/
-  FSPT_CONFIG                 FsptConfig;
-
-/** Offset 0x0060
-**/
-  UINT8                       UnusedUpdSpace0[6];
-
-/** Offset 0x0066
-**/
-  UINT16                      UpdTerminator;
-} FSPT_UPD;
-
-#pragma pack()
-
-#endif
diff --git a/src/vendorcode/intel/fsp/fsp2_0/sapphirerapids_sp/IioPcieConfigUpd.h b/src/vendorcode/intel/fsp/fsp2_0/sapphirerapids_sp/IioPcieConfigUpd.h
deleted file mode 100644
index 567d934952..0000000000
--- a/src/vendorcode/intel/fsp/fsp2_0/sapphirerapids_sp/IioPcieConfigUpd.h
+++ /dev/null
@@ -1,145 +0,0 @@
-/** @file
-
-Copyright (c) 2019-2023, Intel Corporation. All rights reserved.<BR>
-
-Redistribution and use in source and binary forms, with or without modification,
-are permitted provided that the following conditions are met:
-
-* Redistributions of source code must retain the above copyright notice, this
-  list of conditions and the following disclaimer.
-* Redistributions in binary form must reproduce the above copyright notice, this
-  list of conditions and the following disclaimer in the documentation and/or
-  other materials provided with the distribution.
-* Neither the name of Intel Corporation nor the names of its contributors may
-  be used to endorse or promote products derived from this software without
-  specific prior written permission.
-
-  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
-  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
-  THE POSSIBILITY OF SUCH DAMAGE.
-
-**/
-
-#ifndef _IIO_PCIE_CONFIG_UPD_H_
-#define _IIO_PCIE_CONFIG_UPD_H_
-
-#ifndef MAX_SOCKET
-#define MAX_SOCKET                  4
-#endif
-
-#ifndef MAX_LOGIC_IIO_STACK
-#define MAX_LOGIC_IIO_STACK        14
-#endif
-
-#ifndef MAX_IIO_PORTS_PER_SOCKET
-#define MAX_IIO_PORTS_PER_SOCKET   57
-#endif
-
-#ifndef MAX_IOU_PER_SOCKET
-#define MAX_IOU_PER_SOCKET         7
-#endif
-
-#define MAX_VMD_STACKS_PER_SOCKET          8  // Max number of stacks per socket supported by VMD
-
-#pragma pack(1)
-
-typedef struct {
-  UINT8    SLOTEIP[MAX_IIO_PORTS_PER_SOCKET];          // Electromechanical Interlock Present - Slot Capabilities (D0-10 / F0 / R0xA4 / B17)
-  UINT8    SLOTHPCAP[MAX_IIO_PORTS_PER_SOCKET];        // Slot Hot Plug capable - Slot Capabilities (D0-10 / F0 / R0xA4 / B6)
-  UINT8    SLOTHPSUP[MAX_IIO_PORTS_PER_SOCKET];        // Hot Plug surprise supported - Slot Capabilities (D0-10 / F0 / R0xA4 / B5)
-  UINT8    SLOTPIP[MAX_IIO_PORTS_PER_SOCKET];          // Power Indicator Present - Slot Capabilities (D0-10 / F0 / R0xA4 / B4)
-  UINT8    SLOTAIP[MAX_IIO_PORTS_PER_SOCKET];          // Attention Inductor Present - Slot Capabilities (D0-10 / F0 / R0xA4 / B3)
-  UINT8    SLOTMRLSP[MAX_IIO_PORTS_PER_SOCKET];        // MRL Sensor Present - Slot Capabilities (D0-10 / F0 / R0xA4 / B2)
-  UINT8    SLOTPCP[MAX_IIO_PORTS_PER_SOCKET];          // Power Controller Present - Slot Capabilities (D0-10 / F0 / R0xA4 /B1)
-  UINT8    SLOTABP[MAX_IIO_PORTS_PER_SOCKET];          // Attention Button Present - Slot Capabilities (D0-10 / F0 / R0xA4 / B0)
-  UINT8    SLOTIMP[MAX_IIO_PORTS_PER_SOCKET];
-  UINT8    SLOTSPLS[MAX_IIO_PORTS_PER_SOCKET];
-  UINT8    SLOTSPLV[MAX_IIO_PORTS_PER_SOCKET];
-  UINT16   SLOTPSP[MAX_IIO_PORTS_PER_SOCKET];
-  BOOLEAN  VppEnabled[MAX_IIO_PORTS_PER_SOCKET];        // 00 -- Disable, 01 -- Enable  //no setup option defined- aj
-  UINT8    VppPort[MAX_IIO_PORTS_PER_SOCKET];           // 00 -- Port 0, 01 -- Port 1   //no setup option defined- aj
-  UINT8    VppAddress[MAX_IIO_PORTS_PER_SOCKET];        // 01-07 for SMBUS address of Vpp   //no setup option defined- aj
-  UINT8    MuxAddress[MAX_IIO_PORTS_PER_SOCKET];        // SMBUS address of MUX              //no setup option defined
-  UINT8    ChannelID[MAX_IIO_PORTS_PER_SOCKET];         // 00 -- channel 0, 01 -- channel 1  //no setup option defined
-
-  UINT8    PciePortEnable[MAX_IIO_PORTS_PER_SOCKET];
-  UINT8    PEXPHIDE[MAX_IIO_PORTS_PER_SOCKET];          // Hide any of the DMI or PCIE devices - SKT 0,1,2,3; Device 0-10 PRD
-  UINT8    HidePEXPMenu[MAX_IIO_PORTS_PER_SOCKET];      // to suppress /display the PCIe port menu
-  UINT8    PciePortOwnership[MAX_IIO_PORTS_PER_SOCKET];
-  UINT8    RetimerConnectCount[MAX_IIO_PORTS_PER_SOCKET];
-  UINT8    ConfigIOU[MAX_IOU_PER_SOCKET];               // 00-x4x4x4x4, 01-x4x4x8NA, 02-x8NAx4x4, 03-x8NAx8NA, 04-x16 (P1p2p3p4)
-  UINT8    PcieHotPlugOnPort[MAX_IIO_PORTS_PER_SOCKET]; // Manual override of hotplug for port
-  UINT8    VMDEnabled[MAX_VMD_STACKS_PER_SOCKET];
-  UINT8    VMDPortEnable[MAX_IIO_PORTS_PER_SOCKET];
-  UINT8    VMDHotPlugEnable[MAX_VMD_STACKS_PER_SOCKET];
-  UINT8    PcieMaxPayload[MAX_IIO_PORTS_PER_SOCKET];
-  UINT8    PciePortLinkSpeed[MAX_IIO_PORTS_PER_SOCKET]; // auto - 0(default); gen1 -1; gen2 -2; ... gen5 -5.
-  UINT8    DfxDnTxPresetGen3[MAX_IIO_PORTS_PER_SOCKET]; //auto - 0xFF(default); p0 - 0; p1 -1; ... p9 - 9.
-  UINT8    PcieGlobalAspm;
-  UINT8    PcieMaxReadRequestSize;
-} UPD_IIO_PCIE_PORT_CONFIG;
-
-typedef struct {
-  struct {
-    UINT8  Segment;                                  ///< Remember segment, if it changes reset everything
-    UINT8  StackPciBusPoolSize[MAX_LOGIC_IIO_STACK]; ///< Number of bus numbers needed for IIO stack
-  } Socket[MAX_SOCKET];
-} SYSTEM_PCI_BUS_CONFIGURATION;
-
-typedef struct {
-  UINT64 Base;    ///< Base (starting) address of a range (I/O, 32 and 64-bit mmio regions)
-  UINT64 Limit;   ///< Limit (last valid) address of a range
-} PCIE_BASE_LIMIT;
-
-typedef struct {
-  UINT32 MmioLSize;
-  UINT64 MmioHSize;
-} CXL11_LIMITS;
-
-typedef struct {
-  PCIE_BASE_LIMIT Io;        ///< Base and limit of I/O range assigned to entity
-  PCIE_BASE_LIMIT LowMmio;   ///< Base and limit of low MMIO region for entity
-  PCIE_BASE_LIMIT HighMmio;  ///< Base and limit of high (64-bit) MMIO region for entity
-} PCI_BASE_LIMITS;
-
-typedef struct {
-  PCI_BASE_LIMITS SocketLimits;                     ///< Base and Limit of all PCIe resources for the socket
-  PCI_BASE_LIMITS StackLimits[MAX_LOGIC_IIO_STACK]; ///< Base and Limit of all PCIe resources for each stack of the socket
-  CXL11_LIMITS    CxlStackReq[MAX_LOGIC_IIO_STACK]; ///< Base and Limit of CXL11 resources for each stack of the socket
-} SOCKET_PCI_BASE_LIMITS;
-
-typedef struct {
-  //
-  // Save basic system configuration parameters along with the resource map to detect a change.
-  // Remember low and high I/O memory range when saving recource configuration. It is used to verify
-  // whether system memory map changed. Remember also stacks configured when creating the map.
-  // If anything changed reset the system PCI resource configuration.
-  //
-  UINT64                 MmioHBase;
-  UINT64                 MmioHGranularity;
-  UINT32                 MmioLBase;
-  UINT32                 MmioLLimit;
-  UINT32                 MmioLGranularity;
-  UINT16                 IoBase;
-  UINT16                 IoLimit;
-  UINT16                 IoGranularity;
-  UINT32                 StackPresentBitmap[MAX_SOCKET];
-  //
-  // Used by the PciHostBridge DXE driver, these variables don't need to be exposed through setup options
-  // The variables are used as a communication vehicle from the PciHostBridge DXE driver to an OEM hook
-  // which updates the KTI resource map.
-  //
-  SOCKET_PCI_BASE_LIMITS Socket[MAX_SOCKET];        ///< Base and limit of all PCIe resources for each socket
-} SYSTEM_PCI_BASE_LIMITS;
-
-#pragma pack()
-
-#endif // _IIO_PCIE_CONFIG_UPD_H_
diff --git a/src/vendorcode/intel/fsp/fsp2_0/sapphirerapids_sp/IioUniversalDataHob.h b/src/vendorcode/intel/fsp/fsp2_0/sapphirerapids_sp/IioUniversalDataHob.h
deleted file mode 100644
index 8d4c0192db..0000000000
--- a/src/vendorcode/intel/fsp/fsp2_0/sapphirerapids_sp/IioUniversalDataHob.h
+++ /dev/null
@@ -1,253 +0,0 @@
-/** @file
-
-Copyright (c) 2019-2023, Intel Corporation. All rights reserved.<BR>
-
-Redistribution and use in source and binary forms, with or without modification,
-are permitted provided that the following conditions are met:
-
-* Redistributions of source code must retain the above copyright notice, this
-  list of conditions and the following disclaimer.
-* Redistributions in binary form must reproduce the above copyright notice, this
-  list of conditions and the following disclaimer in the documentation and/or
-  other materials provided with the distribution.
-* Neither the name of Intel Corporation nor the names of its contributors may
-  be used to endorse or promote products derived from this software without
-  specific prior written permission.
-
-  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
-  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
-  THE POSSIBILITY OF SUCH DAMAGE.
-
-**/
-
-#ifndef _IIO_UNIVERSAL_DATA_HOB_H_
-#define _IIO_UNIVERSAL_DATA_HOB_H_
-
-#define IIO_UNIVERSAL_DATA_GUID { \
-  0xa1, 0x96, 0xf3, 0x7f, 0x7d, 0xee, 0x1e, 0x43, \
-  0xba, 0x53, 0x8f, 0xCa, 0x12, 0x7c, 0x44, 0xc0  \
-}
-
-#ifndef MAX_SOCKET
-#define MAX_SOCKET                4
-#endif
-
-#if (MAX_SOCKET == 1)
-  #define MAX_FW_KTI_PORTS        4    // Maximum KTI PORTS to be used in structure definition.
-#else
-  #define MAX_FW_KTI_PORTS        6    // Maximum KTI PORTS to be used in structure definition
-#endif //(MAX_SOCKET == 1)
-
-#ifndef MAX_IMC
-#define MAX_IMC                   4    // Maximum memory controllers per socket
-#endif
-
-#ifndef MAX_MC_CH
-#define MAX_MC_CH                 2    // Max number of channels per MC (3 for EP)
-#endif
-
-#ifndef MAX_CH
-#define MAX_CH                    ((MAX_IMC)*(MAX_MC_CH))     // Max channels per socket (worst case EP * EX combination = 16)
-#endif
-
-#define MC_MAX_NODE               (MAX_SOCKET * MAX_IMC)  // Max number of memory nodes
-
-#ifndef MAX_IIO_PORTS_PER_SOCKET
-#define MAX_IIO_PORTS_PER_SOCKET  57
-#endif
-
-#ifndef MAX_IIO_STACK
-#define MAX_IIO_STACK             12
-#endif
-
-#define MAX_LOGIC_IIO_STACK       14
-
-#define MAX_COMPUTE_DIE           1
-#define MAX_CHA_MAP               (2 * MAX_COMPUTE_DIE)  //for GNR & SRF only, each compute die has its own CAPID6 & CAPID7 (i.e. 2 CAPID registers)
-
-#pragma pack(1)
-
-typedef struct _UINT64_STRUCT {
-  UINT32  lo;
-  UINT32  hi;
-} UINT64_STRUCT, *PUINT64_STRUCT;
-
-#ifndef MMIO_BARS_ENUM
-#define MMIO_BARS_ENUM
-typedef enum {
-  TYPE_SCF_BAR = 0,
-  TYPE_PCU_BAR,
-  TYPE_MEM_BAR0,
-  TYPE_MEM_BAR1,
-  TYPE_MEM_BAR2,
-  TYPE_MEM_BAR3,
-  TYPE_MEM_BAR4,
-  TYPE_MEM_BAR5,
-  TYPE_MEM_BAR6,
-  TYPE_MEM_BAR7,
-  TYPE_SBREG_BAR,
-  TYPE_MAX_MMIO_BAR
-} MMIO_BARS;
-#endif
-
-typedef struct {
-    UINT8       Device;
-    UINT8       Function;
-} IIO_PORT_INFO;
-
-typedef struct {
-  UINT8   Major;
-  UINT8   Minor;
-  UINT8   Revision;
-  UINT16  BuildNumber;
-} RC_VERSION;
-
-//--------------------------------------------------------------------------------------//
-// Structure definitions for Universal Data Store (UDS)
-//--------------------------------------------------------------------------------------//
-typedef struct {
-  UINT8                     Valid;         // TRUE, if the link is valid (i.e reached normal operation)
-  UINT8                     PeerSocId;     // Socket ID
-  UINT8                     PeerSocType;   // Socket Type (0 - CPU; 1 - IIO)
-  UINT8                     PeerPort;      // Port of the peer socket
-} QPI_PEER_DATA;
-
-typedef struct {
-  UINT8                     Valid;
-  UINT32                    MmioBar[TYPE_MAX_MMIO_BAR];
-  UINT8                     PcieSegment;
-  UINT64_STRUCT             SegMmcfgBase;
-  UINT32                    StackPresentBitmap;
-  UINT16                    CxlPresentBitmap;
-  UINT16                    Cxl20CapableBitmap;
-  UINT8                     TotM3Kti;
-  UINT8                     TotCha;
-  UINT32                    ChaList[MAX_CHA_MAP];
-  UINT32                    SocId;
-  QPI_PEER_DATA             PeerInfo[MAX_FW_KTI_PORTS];    // QPI LEP info
-} QPI_CPU_DATA;
-
-typedef struct {
-  UINT8                     Valid;
-  UINT8                     SocId;
-  QPI_PEER_DATA             PeerInfo[MAX_SOCKET];    // QPI LEP info
-} QPI_IIO_DATA;
-
-typedef struct {
-    IIO_PORT_INFO           PortInfo[MAX_IIO_PORTS_PER_SOCKET];
-} IIO_DMI_PCIE_INFO;
-
-typedef struct _STACK_RES {
-  UINT8                   Personality;
-  UINT8                   BusBase;               // Base of Bus configured for this stack
-  UINT8                   BusLimit;              // Limit of Bus configured for this stack
-  UINT16                  IoBase;                // Base of IO configured for this stack
-  UINT16                  IoLimit;               // Limit of IO configured for this stack
-  UINT32                  IoApicBase;
-  UINT32                  IoApicLimit;
-  UINT32                  Mmio32Base;            // Base of low MMIO configured for this stack in memory map
-  UINT32                  Mmio32Limit;           // Limit of low MMIO configured for this stack in memory map
-  UINT64                  Mmio64Base;            // Base of high MMIO configured for this stack in memory map
-  UINT64                  Mmio64Limit;           // Limit of high MMIO configured for this stack in memory map
-  UINT8                   PciResourceBusBase;    // Base of Bus resource available for PCI devices
-  UINT8                   PciResourceBusLimit;   // Limit of Bus resource available for PCI devices
-  UINT16                  PciResourceIoBase;     // Base of IO resource available for PCI devices
-  UINT16                  PciResourceIoLimit;    // Limit of IO resource available for PCI devices
-  UINT32                  PciResourceMem32Base;  // Base of low MMIO resource available for PCI devices
-  UINT32                  PciResourceMem32Limit; // Limit of low MMIO resource available for PCI devices
-  UINT64                  PciResourceMem64Base;  // Base of high MMIO resource available for PCI devices
-  UINT64                  PciResourceMem64Limit; // Limit of high MMIO resource available for PCI devices
-  UINT32                  VtdBarAddress;         // NOTE: Obsolete, not used in next gen platforms
-} STACK_RES;
-
-typedef struct {
-    UINT8                   Valid;
-    UINT8                   SocketID;            // Socket ID of the IIO (0..3)
-    UINT8                   BusBase;
-    UINT8                   BusLimit;
-    UINT16                  PciResourceIoBase;
-    UINT16                  PciResourceIoLimit;
-    UINT32                  IoApicBase;
-    UINT32                  IoApicLimit;
-    UINT32                  Mmio32Base;          // Base of low MMIO configured for this socket in memory map
-    UINT32                  Mmio32Limit;         // Limit of low MMIO configured for this socket in memory map
-    UINT64                  Mmio64Base;          // Base of high MMIO configured for this socket in memory map
-    UINT64                  Mmio64Limit;         // Limit of high MMIO configured for this socket in memory map
-    STACK_RES               StackRes[MAX_LOGIC_IIO_STACK];
-    IIO_DMI_PCIE_INFO       PcieInfo;            // NOTE: Obsolete, not used in next gen platforms
-} IIO_RESOURCE_INSTANCE;
-
-typedef struct {
-    UINT16                  PlatGlobalIoBase;       // Global IO Base
-    UINT16                  PlatGlobalIoLimit;      // Global IO Limit
-    UINT32                  PlatGlobalMmio32Base;   // Global Mmiol base
-    UINT32                  PlatGlobalMmio32Limit;  // Global Mmiol limit
-    UINT64                  PlatGlobalMmio64Base;   // Global Mmioh Base [43:0]
-    UINT64                  PlatGlobalMmio64Limit;  // Global Mmioh Limit [43:0]
-    QPI_CPU_DATA            CpuQpiInfo[MAX_SOCKET]; // QPI related info per CPU
-    QPI_IIO_DATA            IioQpiInfo[MAX_SOCKET]; // QPI related info per IIO
-    UINT32                  MemTsegSize;
-    UINT64                  PciExpressBase;
-    UINT32                  PciExpressSize;
-    UINT32                  MemTolm;
-    IIO_RESOURCE_INSTANCE   IIO_resource[MAX_SOCKET];
-    UINT8                   numofIIO;
-    UINT8                   MaxBusNumber;
-    UINT32                  packageBspApicID[MAX_SOCKET]; // This data array is valid only for SBSP, not for non-SBSP CPUs. <AS> for CpuSv
-    UINT8                   EVMode;
-    UINT8                   SkuPersonality[MAX_SOCKET];
-    UINT16                  IoGranularity;
-    UINT32                  MmiolGranularity;
-    UINT64_STRUCT           MmiohGranularity;
-    UINT8                   RemoteRequestThreshold;  //5370389
-    UINT32                  UboxMmioSize;
-    UINT32                  MaxAddressBits;
-} PLATFORM_DATA;
-
-typedef struct {
-    UINT8                   CurrentUpiiLinkSpeed;// Current programmed UPI Link speed (Slow/Full speed mode)
-    UINT8                   CurrentUpiLinkFrequency; // Current requested UPI Link frequency (in GT)
-    UINT8                   OutKtiCpuSktHotPlugEn;            // 0 - Disabled, 1 - Enabled for PM X2APIC
-    UINT32                  OutKtiPerLinkL1En[MAX_SOCKET];    // output kti link enabled status for PM
-    UINT8                   IsocEnable;
-    UINT32                  meRequestedSize; // Size of the memory range requested by ME FW, in MB
-    UINT8                   DmiVc1;
-    UINT8                   DmiVcm;
-    UINT32                  CpuPCPSInfo;
-    UINT8                   cpuSubType;
-    UINT8                   SystemRasType;
-    UINT8                   numCpus;                                        // 1,..4. Total number of CPU packages installed and detected (1..4)by QPI RC
-    UINT16                  tolmLimit;
-    RC_VERSION              RcVersion;
-    BOOLEAN                 MsrTraceEnable;
-    UINT8                   DdrXoverMode;           // DDR 2.2 Mode
-    // For RAS
-    UINT8                   bootMode;
-    UINT8                   OutClusterOnDieEn; // Whether RC enabled COD support
-    UINT8                   OutSncEn;
-    UINT8                   OutNumOfCluster;
-    UINT8                   imcEnabled[MAX_SOCKET][MAX_IMC];
-    UINT16                  LlcSizeReg;
-    UINT8                   chEnabled[MAX_SOCKET][MAX_CH];
-    UINT8                   memNode[MC_MAX_NODE];
-    UINT8                   IoDcMode;
-    UINT8                   DfxRstCplBitsEn;
-    UINT8                   BitsUsed;    //For 5 Level Paging
-} SYSTEM_STATUS;
-
-typedef struct {
-    PLATFORM_DATA           PlatformData;
-    SYSTEM_STATUS           SystemStatus;
-    UINT32                  OemValue;
-} IIO_UDS;
-#pragma pack()
-
-#endif  //#ifndef _IIO_UNIVERSAL_DATA_HOB_H_
diff --git a/src/vendorcode/intel/fsp/fsp2_0/sapphirerapids_sp/MemoryMapDataHob.h b/src/vendorcode/intel/fsp/fsp2_0/sapphirerapids_sp/MemoryMapDataHob.h
deleted file mode 100644
index 0d1cdb9f0c..0000000000
--- a/src/vendorcode/intel/fsp/fsp2_0/sapphirerapids_sp/MemoryMapDataHob.h
+++ /dev/null
@@ -1,373 +0,0 @@
-/** @file
-
-Copyright (c) 2019-2023, Intel Corporation. All rights reserved.<BR>
-
-Redistribution and use in source and binary forms, with or without modification,
-are permitted provided that the following conditions are met:
-
-* Redistributions of source code must retain the above copyright notice, this
-  list of conditions and the following disclaimer.
-* Redistributions in binary form must reproduce the above copyright notice, this
-  list of conditions and the following disclaimer in the documentation and/or
-  other materials provided with the distribution.
-* Neither the name of Intel Corporation nor the names of its contributors may
-  be used to endorse or promote products derived from this software without
-  specific prior written permission.
-
-  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
-  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
-  THE POSSIBILITY OF SUCH DAMAGE.
-
-**/
-
-#ifndef _MEMORY_MAP_DATA_HOB_H_
-#define _MEMORY_MAP_DATA_HOB_H_
-
-#define MEMORY_MAP_HOB_GUID \
-  { \
-    0xf8870015,0x6994,0x4b98,0x95,0xa2,0xbd,0x56,0xda,0x91,0xc0,0x7f \
-  }
-
-#ifndef MAX_SOCKET
-#define MAX_SOCKET                       4
-#endif
-
-#ifndef MAX_IMC
-#define MAX_IMC                          4                     // Maximum memory controllers per socket
-#endif
-
-#ifndef MAX_MC_CH
-#define MAX_MC_CH                        2                     // Max number of channels per MC (3 for EP)
-#endif
-
-#ifndef MAX_CH
-#define MAX_CH                           ((MAX_IMC)*(MAX_MC_CH))     // Max channels per socket (worst case EP * EX combination = 16)
-#endif
-
-#define MAX_CXL_AMT                       0
-
-#ifndef MAX_UNIQUE_NGN_DIMM_INTERLEAVE
-#define MAX_UNIQUE_NGN_DIMM_INTERLEAVE    2                         // Max number of unique interleaves for NGN DIMM
-#endif
-
-#ifndef MAX_SPARE_RANK
-#define MAX_SPARE_RANK                    2             // Max number of spare ranks in a channel
-#endif
-
-#ifndef MAX_HBM_IO
-#define MAX_HBM_IO                        4
-#endif
-
-#ifndef MAX_DIMM
-#define MAX_DIMM                          2                       // Max DIMM per channel
-#endif
-
-#ifndef MAX_RANK_DIMM
-#define MAX_RANK_DIMM                     2
-#endif
-
-#ifndef MAX_DRAM_CLUSTERS
-#define MAX_DRAM_CLUSTERS                 4
-#endif
-
-#ifndef MAX_SAD_RULES
-#define MAX_SAD_RULES                     16
-#endif
-
-#ifndef MAX_FPGA_REMOTE_SAD_RULES
-#define MAX_FPGA_REMOTE_SAD_RULES         2     // Maximum FPGA sockets exists on ICX platform
-#endif
-
-#define MAX_SI_SOCKET                     8   // Maximum silicon supported socket number
-
-#define MAX_AMT                           (MAX_IMC+MAX_CXL_AMT)      // Max abstract memory target per socket
-#define AMT_MAX_NODE                      ((MAX_AMT)*(MAX_SOCKET))   // Max abstract memory target for all sockets
-
-// NGN
-#define NGN_MAX_SERIALNUMBER_STRLEN       4
-#define NGN_MAX_PARTNUMBER_STRLEN         30
-#define NGN_FW_VER_LEN                    4
-#define NGN_LOG_TYPE_NUM                  2
-#define NGN_LOG_LEVEL_NUM                 2
-
-/**
- * Memory channel index conversion macros.
- *
- * We got two types of memory channel indexes:
- * - socket channel - indexes 0..MAX_CH, used in [socket][channel] indexing
- * - IMC channel    - indexes 0..MAX_MC_CH, used in [socket][IMC][channel] indexing
- * The below defined macros convert one channel index to the other one.
- */
-#define MEM_SKTCH_TO_IMC(SktCh)     ((SktCh) / MAX_MC_CH)
-#define MEM_SKTCH_TO_IMCCH(SktCh)   ((SktCh) % MAX_MC_CH)
-#define MEM_IMCCH_TO_SKTCH(Imc, Ch) ((Imc) * MAX_MC_CH + (Ch))
-
-#define MEM_64MB_TO_BYTES(Size64M)  ((UINT64)(Size64M) << 26)
-#define MEM_64MB_TO_KBYTES(Size64M) ((UINT64)(Size64M) << 16)
-#define MEM_64MB_TO_MBYTES(Size64M) ((UINT64)(Size64M) << 6)
-#define MEM_64MB_TO_GBYTES(Size64M) ((Size64M) >> 4)
-#define MEM_BYTES_TO_64MB(SizeB)    ((SizeB) >> 26)
-#define MEM_KBYTES_TO_64MB(SizeKB)  ((SizeKB) >> 16)
-#define MEM_MBYTES_TO_64MB(SizeMB)  ((SizeMB) >> 6)
-
-typedef UINT8               CXL_INTLV_SET_KEY;
-
-#define FSP_RESERVED1_LEN                 77
-#define FSP_RESERVED2_LEN                 2174
-#define FSP_RESERVED3_LEN                 21
-#define FSP_RESERVED4_LEN                 130
-#define FSP_RESERVED5_LEN                 10
-#define FSP_RESERVED6_LEN                 800
-#pragma pack(1)
-
-typedef enum {
-  DIMM_RANK_MAP_OUT_UNKNOWN = 0,
-  DIMM_RANK_MAP_OUT_MEM_DECODE,
-  DIMM_RANK_MAP_OUT_POP_POR_VIOLATION,
-  DIMM_RANK_MAP_OUT_RANK_DISABLED,
-  DIMM_RANK_MAP_OUT_ADVMEMTEST_FAILURE,
-  DIMM_RANK_MAP_OUT_MAX
-} DIMM_RANK_MAP_OUT_REASON;
-
-struct RankDevice {
-  UINT8   enabled;                // 0 = disabled,  1 = enabled
-  UINT8   logicalRank;            // Logical Rank number (0 - 7)
-  UINT16  rankSize;               // Units of 64 MB
-};
-
-struct PersisentDpaMap
-{
-    UINT32 perRegionDPAOffset;
-    UINT32 SPALimit;
-};
-
-typedef struct firmwareRev {
-  UINT8  majorVersion;
-  UINT8  minorVersion;
-  UINT8  hotfixVersion;
-  UINT16 buildVersion;
-} FIRMWARE_REV;
-
-typedef struct DimmDevice {
-  UINT8                     Present;
-  BOOLEAN                   Enabled;
-  UINT8                     DcpmmPresent;                                 // 1 - This is a DCPMM
-  UINT8                     X4Present;
-  UINT8                     DramIoWidth;                                  // Actual DRAM IO Width (4, 8, 16)
-  UINT8                     NumRanks;
-  UINT8                     keyByte;
-  UINT8                     actKeyByte2;                                  // Actual module type reported by SPD
-  UINT8                     actSPDModuleOrg;                              // Actual number of DRAM ranks and device width
-  UINT8                     dimmTs;                                       // Thermal sensor data.
-  UINT16                    VolCap;                                       // Volatile capacity (AEP DIMM only)
-  UINT16                    nonVolCap;                                    // Non-volatile capacity (AEP DIMM only)
-  UINT16                    DimmSize;
-  UINT32                    NVmemSize;
-  UINT16                    SPDMMfgId;                                    // Module Mfg Id from SPD
-  UINT16                    VendorID;
-  UINT16                    DeviceID;
-  UINT16                    RevisionID;
-  UINT32                    perRegionDPA;                                 // DPA of PMEM that Nfit needs
-  struct  PersisentDpaMap   perDPAMap[MAX_UNIQUE_NGN_DIMM_INTERLEAVE];    // DPA map
-  UINT8                     serialNumber[NGN_MAX_SERIALNUMBER_STRLEN];    // Serial Number
-  UINT8                     PartNumber[NGN_MAX_PARTNUMBER_STRLEN];        // Part Number
-  UINT8                     FirmwareVersionStr[NGN_FW_VER_LEN];           // Used to update the SMBIOS TYPE 17
-  struct  firmwareRev       FirmwareVersion;                              // Firmware revision
-  struct  RankDevice        rankList[MAX_RANK_DIMM];
-  UINT16                    InterfaceFormatCode;
-  UINT16                    SubsystemVendorID;
-  UINT16                    SubsystemDeviceID;
-  UINT16                    SubsystemRevisionID;
-  UINT16                    FisVersion;                                   // Firmware Interface Specification version
-  UINT8                     DimmSku;                                      // Dimm SKU info
-  UINT8                     manufacturingLocation;                        // Manufacturing location for the NVDIMM
-  UINT16                    manufacturingDate;                            // Date the NVDIMM was manufactured
-  INT32                     commonTck;
-  UINT8                     EnergyType;                                   // 0: 12V aux power; 1: dedicated backup energy source; 2: no backup energy source
-  BOOLEAN                   NvDimmNPresent;                               // JEDEC NVDIMM-N Type Memory Present
-  UINT8                     CidBitMap;                                    // SubRankPer CS for DIMM device
-  UINT16                    SPDRegVen;                                    // Register Vendor ID in SPD
-  DIMM_RANK_MAP_OUT_REASON  MapOutReason;
-} MEMMAP_DIMM_DEVICE_INFO_STRUCT;
-
-struct ChannelDevice {
-  UINT8                               Enabled;                            // 0 = channel disabled, 1 = channel enabled
-  UINT8                               Features;                           // Bit mask of features to enable or disable
-  UINT8                               MaxDimm;                            // Number of DIMM
-  UINT8                               NumRanks;                           // Number of ranks on this channel
-  UINT8                               chFailed;
-  UINT8                               ngnChFailed;
-  UINT8                               Is9x4DimmPresent;                   // 9x4 dimm present indicator
-  UINT8                               SpareLogicalRank[MAX_SPARE_RANK];   // Logical rank, selected as Spare
-  UINT8                               SparePhysicalRank[MAX_SPARE_RANK];  // Physical rank, selected as spare
-  UINT16                              SpareRankSize[MAX_SPARE_RANK];      // spare rank size
-  UINT8                               EnabledLogicalRanks;                // Bitmap of Logical ranks that are enabled
-  UINT8                               DdrPopulationMap;                   // Bitmap to indicate location of DDR DIMMs within the channel memory slots (BIT0: Ch.D0, BIT1: CH.D1)
-  UINT8                               PmemPopulationMap;                  // Bitmap to indicate location of PMem modules within the channel memory slots (BIT0: Ch.D0, BIT1: CH.D1)
-  MEMMAP_DIMM_DEVICE_INFO_STRUCT      DimmInfo[MAX_DIMM];
-};
-
-struct memcontroller {
-  UINT32    MemSize;
-};
-
-typedef enum {
-  MemTypeNone = 0,
-  MemType1lmDdr,
-  MemType1lmAppDirect,
-  MemType1lmAppDirectReserved,
-  MemType1lmCtrl,
-  MemType1lmHbm,
-  MemTypeNxm,
-  MemType2lmDdrCacheMemoryMode,
-  MemType2lmDdrWbCacheAppDirect,
-  MemType2lmHbmCacheDdr,
-  MemType2lmHbmCacheMemoryMode,
-  MemTypeCxlAccVolatileMem,
-  MemTypeCxlAccPersistentMem,
-  MemTypeFpga,
-  MemTypeCxlExpVolatileMem,
-  MemTypeCxlExpPersistentMem,
-  MemTypeCxl2lmDdrCacheMem,
-  MemTypeCxlHetero,
-  MemTypeMax
-} MEM_TYPE;
-
-typedef struct SADTable {
-  UINT8    Enable;         // Rule enable
-  MEM_TYPE type;           // Bit map of memory region types, See defines 'MEM_TYPE_???' above for bit definitions of the ranges.
-  UINT8    granularity;    // Interleave granularities for current SAD entry.  Possible interleave granularity options depend on the SAD entry type.  Note that SAD entry type BLK Window and CSR/Mailbox/Ctrl region do not support any granularity options
-  UINT32   Base;           // Base of the current SAD entry
-  UINT32   Limit;          // Limit of the current SAD entry
-  UINT8    ways;           // Interleave ways for SAD
-  UINT8    channelInterBitmap[MAX_AMT];   //Bit map to denote which DDR4/NM channels are interleaved per IMC eg: 111b - Ch 2,1 & 0 are interleaved; 011b denotes Ch1 & 0 are interleaved
-  UINT8    FMchannelInterBitmap[MAX_AMT];   //Bit map to denote which FM channels are interleaved per IMC eg: 111b - Ch 2,1 & 0 are interleaved; 011b denotes Ch1 & 0 are interleaved
-  UINT8    NmChWays;         // Channel Interleave ways for SAD. Represents channelInterBitmap ways for DDR4/NM.
-  UINT8    FmChWays;         // Channel Interleave ways for SAD. Represents FMchannelInterBitmap ways for DDRT.
-  UINT16   imcInterBitmap;   // Bit map to denote which IMCs are interleaved from this socket.
-  UINT16   NmImcInterBitmap; // Bit map to denote which IMCs are interleaved from this socket as NM.
-  BOOLEAN  local;          // 0 - Remote 1- Local
-  UINT8    IotEnabled;     // To indicate if IOT is enabled
-  UINT8    mirrored;       // To Indicate the SAD is mirrored while enabling partial mirroring
-  UINT8    Attr;
-  UINT8    tgtGranularity; // Interleave mode for target list
-  UINT8    Cluster;        // SNC cluster, hemisphere, or quadrant index.
-  UINT8    HostBridgeGran; // Host bridge interleaving granularity.
-  UINT32   HotPlugPadSize; // Memory size padded for CXL hot plug. 0 if it is not a CXL hot plug SAD.
-  CXL_INTLV_SET_KEY   CxlIntlvSetKey;   // The unique key of CXL interleave set. (7nm)
-} SAD_TABLE;
-
-typedef struct socket {
-  UINT8      SocketEnabled;
-  UINT32     IioStackBitmap;
-  BOOLEAN    HbmIoEn[MAX_HBM_IO];                    // Flag indicates if HBM IO is enabled. TRUE: HBM IO is Enabled, FALSE: HBM IO is disabled.
-  UINT8      imcEnabled[MAX_IMC];
-  UINT8      SadIntList[MAX_DRAM_CLUSTERS * MAX_SAD_RULES][AMT_MAX_NODE]; // SAD interleave list
-  UINT32     SktTotMemMapSPA;                        // Total memory mapped to SPA
-  UINT32     SktMemSize2LM;                          // Total memory excluded from Limit
-  SAD_TABLE  SAD[MAX_DRAM_CLUSTERS * MAX_SAD_RULES];                     // SAD table
-  struct     memcontroller imc[MAX_IMC];
-  struct     ChannelDevice ChannelInfo[MAX_CH];
-} MEMMAP_SOCKET;
-
-typedef struct {
-  UINT8  Enabled;           // Indicates if this EDC is enabled
-  UINT32 MemAsCache;        // Memory used as Cache, in 64MB units
-  UINT32 MemAsFlat;         // Memory used as Flat memory, in 64MB units
-} EDC_INFO;
-
-typedef struct SystemMemoryMapElement {
-  UINT16   Type;           // Type of this memory element; Bit0: 1LM  Bit1: 2LM  Bit2: PMEM  Bit3: PMEM-cache  Bit4: BLK Window  Bit5: CSR/Mailbox/Ctrl region
-  UINT8    NodeId;         // Node ID of the HA Owning the memory
-  UINT8    SocketId;       // Socket Id of socket that has his memory - ONLY IN NUMA
-  UINT8    SktInterBitmap; // Socket interleave bitmap, if more that on socket then ImcInterBitmap and ChInterBitmap are identical in all sockets
-  UINT16   ImcInterBitmap; // IMC interleave bitmap for this memory
-  UINT8    ChInterBitmap[MAX_IMC];//Bit map to denote which channels are interleaved per IMC eg: 111b - Ch 2,1 & 0 are interleaved; 011b denotes Ch1 & 0 are interleaved
-  UINT32   BaseAddress;    // Base Address of the element in 64MB chunks
-  UINT32   ElementSize;    // Size of this memory element in 64MB chunks
-} SYSTEM_MEMORY_MAP_ELEMENT;
-
-typedef struct SystemMemoryMapHob {
-  //
-  // Total Clusters. In SNC2 mode there are 2 clusters and SNC4 mode has 4 clusters.
-  // All2All/Quad/Hemi modes can be considered as having only one cluster (i.e SNC1).
-  //
-  UINT8    TotalClusters;
-
-  UINT8    reserved1[FSP_RESERVED1_LEN];          // MEMORY_MAP_BLOCK_DECODER_DATA BlockDecoderData; // block decoder data structure
-  UINT32   lowMemBase;                            // Mem base in 64MB units for below 4GB mem.
-  UINT32   lowMemSize;                            // Mem size in 64MB units for below 4GB mem.
-  UINT32   highMemBase;                           // Mem base in 64MB units for above 4GB mem.
-  UINT32   highMemSize;                           // Mem size in 64MB units for above 4GB mem.
-  UINT32   memSize;                               // Total physical memory size
-  UINT16   memFreq;                               // Mem Frequency
-  UINT16   HbmFreq;                               // HBM Frequency in MHz.
-  UINT8    memMode;                               // 0 - Independent, 1 - Lockstep
-  UINT8    volMemMode;                            // 0 - 1LM, 1 - 2LM
-  UINT8    CacheMemType;                          // 0 - DDR$DDRT, 1 - HBM$DDR. Only valid if volMemMode is 2LM
-  UINT16   DramType;
-  UINT8    DdrVoltage;
-  BOOLEAN  SupportedPMemPresent;                  // TRUE if at least one PMem is present and supported by BIOS
-  BOOLEAN  EkvPresent;                            // Set if EKV controller on system
-  BOOLEAN  BwvPresent;                            // Set if BWV controller on system
-  BOOLEAN  CwvPresent;                            // Set if CWV controller on system
-  UINT8    XMPProfilesSup;
-  UINT8    XMPCapability;
-  //
-  // HBM Specific Info.
-  //
-  UINT16   HbmInstances[MAX_SOCKET];              // Total HBM instances
-  UINT32   HbmFlatMemSize;                        // Total HBM memory size in 64MB units, if HBM used as Flat memory
-  UINT32   HbmCacheMemSize;                       // Total HBM memory used as cache, if HBM used as Cache memory
-  UINT16   HbmSpeed;                              // Configured HBM (i.e OPIO channel) speed in MT/s.
-  UINT16   MaxHbmSpeed;                           // Max HBM (i.e OPIO channel) speed in MT/s.
-  UINT8    SystemRasType;
-  UINT8    RasModesEnabled;                       // RAS modes that are enabled
-  UINT16   ExRasModesEnabled;                     // Extended RAS modes that are enabled
-  UINT8    sncEnabled;                            // 0 - SNC disabled for this configuration, 1 - SNC enabled for this configuration
-  UINT8    NumOfCluster;
-  UINT8    NumChPerMC;
-  UINT8    numberEntries;                         // Number of Memory Map Elements
-  SYSTEM_MEMORY_MAP_ELEMENT Element[(MAX_SOCKET * MAX_DRAM_CLUSTERS * MAX_SAD_RULES) + MAX_FPGA_REMOTE_SAD_RULES];
-  UINT8   reserved2[FSP_RESERVED2_LEN];                // struct   memSetup MemSetup;
-  UINT8   reserved3[FSP_RESERVED3_LEN];                // MEM_DFXMEMVARS    DfxMemVar;
-  MEMMAP_SOCKET Socket[MAX_SOCKET];
-  UINT8   reserved4[FSP_RESERVED4_LEN];                // struct   memTiming  profileMemTime[XMP_MAX_PROFILES];
-
-  UINT8   reserved5[FSP_RESERVED5_LEN];                // RASMEMORYINFO  RasMeminfo;
-  UINT8   LatchSystemShutdownState;
-  BOOLEAN IsWpqFlushSupported;
-  UINT8   EadrSupport;
-  UINT8   EadrCacheFlushMode;
-  UINT8   SetSecureEraseSktChHob[MAX_SOCKET][MAX_CH];  //MAX_CH * MAX_SOCKET * MAX_DCPMM_CH
-  UINT8   reserved6[FSP_RESERVED6_LEN];                // HOST_DDRT_DIMM_DEVICE_INFO_STRUCT HostDdrtDimmInfo[MAX_SOCKET][MAX_CH];
-  UINT32  DdrCacheSize[MAX_SOCKET][MAX_CH];            // Size of DDR memory reserved for 2LM cache (64MB granularity)
-  BOOLEAN AdrStateForPmemModule[MAX_SOCKET][MAX_CH];   // ADR state for Intel PMEM Modules
-  UINT16  BiosFisVersion;                              // Firmware Interface Specification version currently supported by BIOS
-  UINT16  MaxAveragePowerLimit;                        // Max Power limit in mW used for averaged power ( Valid range ends at 15000mW)
-  UINT16  MinAveragePowerLimit;                        // Min Power limit in mW used for averaged power ( Valid range starts from 10000mW)
-  UINT16  CurrAveragePowerLimit;                       // Current Power limit in mW used for average power
-  UINT16  MaxMbbPowerLimit;                            // Max MBB power limit ( Valid range ends at 18000mW).
-  UINT16  MinMbbPowerLimit;                            // Min MBB power limit ( Valid range starts from 15000mW).
-  UINT16  CurrMbbPowerLimit;                           // Current Power limit in mW used for MBB power
-  UINT32  MaxMbbAveragePowerTimeConstant;              // Max MBB Average Power Time Constant
-  UINT32  MinMbbAveragePowerTimeConstant;              // Min MBB Average Power Time Constant
-  UINT32  CurrMbbAveragePowerTimeConstant;             // Current MBB Average Power Time Constant
-  UINT32  MmiohBase;                                   // MMIOH base in 64MB granularity
-  UINT8   MaxSadRules;                                 // Maximum SAD entries supported by silicon (24 for 14nm silicon, 16 for 10nm silicon)
-  UINT8   NumberofChaDramClusters;                     // Number of CHA DRAM decoder clusters
-  BOOLEAN VirtualNumaEnable;                           // Enable or Disable Virtual NUMA
-  UINT8   VirtualNumOfCluster;                         // Number of Virtual NUMA nodes in each physical NUMA node (Socket or SNC cluster)
-} SYSTEM_MEMORY_MAP_HOB;
-
-#pragma pack()
-
-#endif // _MEMORY_MAP_DATA_H_
diff --git a/src/vendorcode/intel/fsp/fsp2_0/sapphirerapids_sp/PrevBootErrSrcHob.h b/src/vendorcode/intel/fsp/fsp2_0/sapphirerapids_sp/PrevBootErrSrcHob.h
deleted file mode 100644
index f1d55542c3..0000000000
--- a/src/vendorcode/intel/fsp/fsp2_0/sapphirerapids_sp/PrevBootErrSrcHob.h
+++ /dev/null
@@ -1,85 +0,0 @@
-/** @file
-
-Copyright (c) 2019-2023, Intel Corporation. All rights reserved.<BR>
-
-Redistribution and use in source and binary forms, with or without modification,
-are permitted provided that the following conditions are met:
-
-* Redistributions of source code must retain the above copyright notice, this
-  list of conditions and the following disclaimer.
-* Redistributions in binary form must reproduce the above copyright notice, this
-  list of conditions and the following disclaimer in the documentation and/or
-  other materials provided with the distribution.
-* Neither the name of Intel Corporation nor the names of its contributors may
-  be used to endorse or promote products derived from this software without
-  specific prior written permission.
-
-  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
-  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
-  THE POSSIBILITY OF SUCH DAMAGE.
-
-**/
-
-#ifndef _PREV_BOOT_ERR_SRC_HOB_H_
-#define _PREV_BOOT_ERR_SRC_HOB_H_
-
-#define FSP_PREV_BOOT_ERR_SRC_HOB_GUID \
-{ 0xc5, 0xb5, 0x38, 0x51, 0x69, 0x93, 0xec, 0x48, 0x5b, 0x97, 0x38, 0xa2, 0xf7, 0x09, 0x66, 0x75 }
-
-#define PREV_BOOT_ERR_SRC_HOB_SIZE  1000
-
-#pragma pack(1)
-
-typedef struct {
-UINT16  Length;    // Actual size of the error sources  used in the HOB
-UINT8  HobData[PREV_BOOT_ERR_SRC_HOB_SIZE -2];  // List of Error source structures of format //MCBANK_ERR_INFO  or CSR_ERR_INFO
-}PREV_BOOT_ERR_SRC_HOB;
-
-typedef struct{
-UINT8  Type;    // McBankType = 1;
-UINT8  Segment;
-UINT8  Socket;
-UINT16  ApicId;    // ApicId  is Needed only if it a core McBank.
-UINT16  McBankNum;
-UINT64  McBankStatus;
-UINT64  McbankAddr;
-UINT64  McBankMisc;
-} MCBANK_ERR_INFO;
-
-typedef struct {
-UINT8  Type;    // PciExType =2 ;
-UINT8  Segment;
-UINT8  Bus;
-UINT8  Device;
-UINT8  Function;
-UINT32  AerUncErrSts;
-UINT8  AerHdrLogData[16];
-} PCI_EX_ERR_INFO;
-
-typedef struct {
-UINT8  Type;    // Other Csr error type =3 ;
-UINT8  Segment;
-UINT8  Bus;
-UINT8  Device;
-UINT8  Function;
-UINT16  offset;
-UINT32  Value;
-} CSR_ERR_INFO;
-
-typedef enum {
-  McBankType = 1,
-  PciExType,
-  CsrOtherType
-} ERROR_ACCESS_TYPE;
-
-#pragma pack()
-
-#endif //_PREV_BOOT_ERR_SRC_HOB_H_
diff --git a/src/vendorcode/intel/fsp/fsp2_0/sapphirerapids_sp/SystemInfoHob.h b/src/vendorcode/intel/fsp/fsp2_0/sapphirerapids_sp/SystemInfoHob.h
deleted file mode 100644
index b6d88f5c30..0000000000
--- a/src/vendorcode/intel/fsp/fsp2_0/sapphirerapids_sp/SystemInfoHob.h
+++ /dev/null
@@ -1,283 +0,0 @@
-/** @file
-
-Copyright (c) 2019-2023, Intel Corporation. All rights reserved.<BR>
-
-Redistribution and use in source and binary forms, with or without modification,
-are permitted provided that the following conditions are met:
-
-* Redistributions of source code must retain the above copyright notice, this
-  list of conditions and the following disclaimer.
-* Redistributions in binary form must reproduce the above copyright notice, this
-  list of conditions and the following disclaimer in the documentation and/or
-  other materials provided with the distribution.
-* Neither the name of Intel Corporation nor the names of its contributors may
-  be used to endorse or promote products derived from this software without
-  specific prior written permission.
-
-  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
-  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
-  THE POSSIBILITY OF SUCH DAMAGE.
-
-**/
-
-#ifndef _SYSTEM_INFO_HOB_H_
-#define _SYSTEM_INFO_HOB_H_
-
-#define SYSTEM_INFO_HOB_GUID          { 0x7650A0F2, 0x0D91, 0x4B0C, { 0x92, 0x3B, 0xBD, 0xCF, 0x22, 0xD1, 0x64, 0x35 }}
-
-#ifndef MAX_SOCKET
-#define MAX_SOCKET                    4
-#endif
-
-#ifndef MAX_IIO_STACK
-#define MAX_IIO_STACK                 12
-#endif
-
-#define MAX_LOGIC_IIO_STACK           14
-
-#ifndef MAX_IMC
-#define MAX_IMC                       4                     // Maximum memory controllers per socket
-#endif
-
-#ifndef MAX_MC_CH
-#define MAX_MC_CH                     2                     // Max number of channels per MC (3 for EP)
-#endif
-
-#ifndef MAX_CH
-#define MAX_CH                        ((MAX_IMC)*(MAX_MC_CH))     // Max channels per socket (worst case EP * EX combination = 16)
-#endif
-
-#define MAX_HPM_PFS_ENTRY_NUM         15      // Number of entries in PFS structure
-#define HPM_PFS_ENTRY_SIZE            2       // Entry size of PFS structure in DWORD
-
-#pragma pack(1)
-
-#ifndef MMIO_BARS_ENUM
-#define MMIO_BARS_ENUM
-typedef enum {
-  TYPE_SCF_BAR = 0,
-  TYPE_PCU_BAR,
-  TYPE_MEM_BAR0,
-  TYPE_MEM_BAR1,
-  TYPE_MEM_BAR2,
-  TYPE_MEM_BAR3,
-  TYPE_MEM_BAR4,
-  TYPE_MEM_BAR5,
-  TYPE_MEM_BAR6,
-  TYPE_MEM_BAR7,
-  TYPE_SBREG_BAR,
-  TYPE_MAX_MMIO_BAR
-} MMIO_BARS;
-#endif
-
-typedef enum {
-  ReservedMemSs,
-  Ddr4MemSs = 1,
-  Ddr5MemSs = 2,
-  LpDdr4MemSs = 3,
-  LpDdr5MemSs = 4,
-  Hbm2MemSs = 5,
-  MrcMstMax,
-  MrcMstDelim = MAX_INT32
-} MRC_MST;
-
-typedef enum BootMode {
-  NormalBoot  = 0,  // Normal path through RC with full init, mem detection, init, training, etc.
-                    //    Some of these MRC specific init routines can be skipped based on MRC input params
-                    //    in addition to the sub-boot type (WarmBoot, WarmBootFast, etc).
-  S3Resume    = 1   // S3 flow through RC. Should do the bare minimum required for S3
-                    //    init and be optimized for speed.
-} BootMode;
-
-//
-// This is used to determine what type of die is connected to a UPI link
-//
-typedef enum {
-  UpiConnectionTypeCpu,
-  UpiConnectionTypePcieGen4,
-  UpiConnectionTypeFpga,
-  UpiConnectionTypeMax
-} UPI_CONNECTION_TYPE;
-
-//
-// VSEC info for HPM
-// The HPM_INFO struct contains info collected from the VSEC structure for the HPM.
-// VSEC Structure is defined as below:
-//
-// ------------------------VSEC Structure------------------------
-// | Next Cap Offset(12b)  | Cap Version(4b) | PCIe Cap ID(16b) |
-// --------------------------------------------------------------
-// |     VSEC_LEN(12b)     |   VSEC_REV(4b)  |   VSEC_ID(16b)   |
-// --------------------------------------------------------------
-// | EntrySize(8b)     |     NumEntries(8b)  |    Rsvd(16b)     |
-// --------------------------------------------------------------
-// |                 Address(29b)                    | tBIR(3b) |
-// --------------------------------------------------------------
-//
-//
-typedef struct {
-  UINT8        NumEntries;  // The number of PM feature interface instances in this VSEC space
-  UINT8        EntrySize;   // The entry size for each PM interface instance in 32-bit DWORDs
-  UINT32       Address;     // The offset from the BAR register which is used for HPM to point to the base of the discovery entry. i.e. the PFS (PM Feature Structure)
-  UINT8        tBIR;        // Which one of he function's BAR is used for the PFS offset
-} HPM_INFO;
-
-//
-//-------------------------------- - PFS Entry--------------------------------
-//|  EntrySize(16b)                     |  NumEntries(8b)  |  VSEC_SubID(8b)  |
-//----------------------------------------------------------------------------
-//| RSVD(14b)                | Attr(2b) |       CapOffset(16b)                |
-//----------------------------------------------------------------------------
-//
-typedef struct {
-  UINT32                TpmiId : 8;
-  UINT32                NumEntries : 8;
-  UINT32                EntrySize : 16;
-  UINT32                CapOffset : 16;
-  UINT32                Attribute : 2;
-  UINT32                EntryBitMap : 8;
-  UINT32                Rsvd : 6;
-} PFS_ENTRY;
-
-//
-// HPM (Hierarchical Power Management) VSEC resource allocation info
-//
-typedef struct {
-  BOOLEAN             HpmEnabled;                   // HPM enabled or not in BIOS knob
-  BOOLEAN             HpmInfraReady;                // All the HPM infrastructure data is buffered
-  UINT32              OobMsmHpmBarBase;               // The base of OOBMSM BAR1 for HPM PFS and LUT tables
-  UINT32              OobMsmHpmBarLimit;              // The limit of OOBMSM BAR1 from where the required size will be allocated
-  UINT32              OobMsmHpmBarMmcfgAddress;       // The OOBMSM BAR1 MMCFG address
-  UINT32              OobMsmHpmBarRequiredSize;       // The required size of OOBMSM BAR1
-
-  HPM_INFO            HpmVsecInfo;                  // For now, single VSEC is assumed
-  PFS_ENTRY           Pfs[MAX_HPM_PFS_ENTRY_NUM];   // The buffered PFS structure
-
-} HPM_VSEC_RESOURCE;
-
-//
-// Stack id swap information, which includes stack swap flag and the new stack id swap array.
-//
-typedef struct {
-  BOOLEAN StackSwapFlag;
-  UINT8   StackIdSwapArray[MAX_IIO_STACK];
-} STACKID_SWAP_INFO;
-
-typedef struct {
-  UINT64  Cxl1p1RcrbBase;
-  BOOLEAN Cxl1p1RcrbValid;
-} CXL_1P1_RCRB;
-
-typedef struct {
-  UINT32 StackPresentBitmap[MAX_SOCKET];           ///< bitmap of present stacks per socket
-  UINT8  StackBus[MAX_SOCKET][MAX_LOGIC_IIO_STACK];///< Bus of each stack
-  UINT32 StackMmiol[MAX_SOCKET][MAX_IIO_STACK];    ///< mmiol of each IIO stack, if it works as CXL, the mmiol base is RCRBBAR
-  UINT8  SocketFirstBus[MAX_SOCKET];
-  UINT8  Socket10nmUboxBus0[MAX_SOCKET];           //10nm CPU use only
-  UINT8  TotIoDie[MAX_SOCKET];                     //GNR & SRF CPU use only
-  UINT8  TotCmpDie[MAX_SOCKET];                    //GNR & SRF CPU use only
-  UINT8  SocketLastBus[MAX_SOCKET];
-  UINT8  segmentSocket[MAX_SOCKET];
-  UINT8  KtiPortCnt;
-  UINT32 socketPresentBitMap;
-  UINT32 SecondaryNodeBitMap;
-  UINT32 FpgaPresentBitMap;
-  UINT32 mmCfgBase;
-  UINT64 SocketMmCfgBase[MAX_SOCKET];
-  UINT8  DdrMaxCh;
-  UINT8  DdrMaxImc;                               ///< Logical number of IMC count, ignoring logical holes
-  UINT8  DdrPhysicalMaxImc;                       ///< Physical number of IMC count from Capid
-  UINT8  DdrNumChPerMc;
-  UINT8  DdrNumPseudoChPerCh;
-  UINT8  imcEnabled[MAX_SOCKET][MAX_IMC];
-  UINT8  mcId[MAX_SOCKET][MAX_CH];
-  MRC_MST MemSsType[MAX_SOCKET];                    ///< MemSsType global identifier for DDR vs. HBM
-  UINT32  MmioBar[MAX_SOCKET][TYPE_MAX_MMIO_BAR];
-  UINT8   HbmMaxCh;
-  UINT8   HbmMaxIoInst;
-  UINT8   HbmNumChPerMc;
-  UINT8   HbmNumChPerIo;
-  UINT32  LastCsrAddress[2];
-  UINT32  LastCsrMmioAddr;
-  UINT8   CsrCachingEnable;
-  UINT32  LastCsrMcAddress[2];
-  UINT32  LastCsrMcMmioPhyAddr;
-  UINT8   CsrPciBarCachingEnable;
-  UINT32  LastCsrPciBarAddr[2];
-  UINT64  LastCsrPciBarPhyAddr;
-  UINT32  LastSBPortId[MAX_SOCKET];
-  UPI_CONNECTION_TYPE         UpiConnectionType[MAX_SOCKET];
-  BOOLEAN PostedCsrAccessAllowed;                   // SW is allowed to use posted CSR writes method when TRUE
-  BOOLEAN PostedWritesEnabled;                      // All CSR writes use posted method when TRUE, non-posted when FALSE
-  BOOLEAN DataPopulated;                            // CPU_CSR_ACCESS_VAR is unavailable when FALSE
-  HPM_VSEC_RESOURCE SocketHpmVsecRes[MAX_SOCKET];   // HPM VSEC info for all sockets
-  BOOLEAN HbmSku;
-  UINT8   HcxType[MAX_SOCKET];
-  STACKID_SWAP_INFO StackIdSwapInfo[MAX_SOCKET];    //StackID sync after do StackId swap,including Stack swap table and whether do stack swap
-  CXL_1P1_RCRB  Cxl1p1Rcrb[MAX_SOCKET][MAX_IIO_STACK];    // CXL 1.1 RCRB, one per PI5 stack
-  UINT32  DmiRcrb[MAX_SOCKET];                      // DMI RCRB region, one per socket
-  UINT8   FabricType;                               //Compute die 10x6, 10x5, and 6x5 type is stored
-  UINT8   ChopType;                                 //Compute Die Chop Type
-  UINT8   MdfInstCount;
-} CPU_CSR_ACCESS_VAR;
-
-typedef struct {
-  UINT32 MeRequestedSizeNv;
-  UINT32 MeRequestedAlignmentNv;
-  UINT8  SbspSocketIdNv;
-} SYS_INFO_VAR_NVRAM;
-
-typedef struct _CPUID_REGISTER_INFO {
-  UINT32 Eax;
-  UINT32 Ebx;
-  UINT32 Ecx;
-  UINT32 Edx;
-} CPUID_REGISTER_INFO;
-
-typedef struct _PROCESSOR_COMMON_INFO {
-  UINT32  capid0;
-  UINT32  capid1;
-  UINT32  capid2;
-  UINT32  capid3;
-  UINT32  capid4;
-  UINT32  capid5;
-  UINT32  capid6lo;
-  UINT32  capid6hi;
-  CPUID_REGISTER_INFO  ExtCpuid7;
-  CPUID_REGISTER_INFO  ExtCpuid1B;
-} PROCESSOR_COMMON_INFO;
-
-typedef struct {
-  UINT32 MeRequestedSize;
-  UINT32 MeRequestedAlignment;
-  UINT32 CheckPoint;
-  UINT8  ResetRequired;
-  UINT8  Emulation;
-  BootMode SysBootMode;
-  CPU_CSR_ACCESS_VAR        CpuCsrAccessVarHost;    // Common resource for CsrAccessRoutines
-  UINT64   CpuFreq;
-  UINT8    SocketId;
-  SYS_INFO_VAR_NVRAM SysInfoVarNvram;
-  BOOLEAN  UsraTraceControl;
-  UINT16   UsraTraceConfiguration;                 // Bit               7       6        5           4                     3:0
-                                                   //               Write, Modify, GetAddr, Long/Short, Trace 0x5 as signature
-                                                   // Bit               15                              14:11   10     9     8
-                                                   // DumpCpuCsrAccessVar,                                TBD, CSR, PCIE, Read
-  BOOLEAN  CpuCsrAccessVarInfoDumped;
-  PROCESSOR_COMMON_INFO          ProcessorCommonInfo[MAX_SOCKET];
-  EFI_PHYSICAL_ADDRESS  SocAddrMapData;
-  UINTN    UsraPpiPtr;
-} SYSTEM_INFO_VAR;
-
-
-#pragma pack ()
-
-#endif //#ifndef _SYSTEM_INFO_HOB_H_

From 89c7a5b766ac08663e38a39cbbd5074ac7092494 Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Thu, 6 Mar 2025 13:48:52 +0000
Subject: [PATCH 0325/3886] mb/starlabs/*: Correct comments/use defs for sleep
 assertion

Correct the comments, and use the definations where available
for the sleep assertion values

Change-Id: Idfd382a166c8101b5d9a79bd18c40d6763c05e7b
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86753
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
---
 .../starlabs/byte_adl/variants/mk_ii/devicetree.cb        | 8 ++++----
 .../starlabs/starbook/variants/adl/devicetree.cb          | 8 ++++----
 .../starlabs/starbook/variants/adl_n/devicetree.cb        | 8 ++++----
 .../starlabs/starbook/variants/cml/devicetree.cb          | 8 ++++----
 .../starlabs/starbook/variants/kbl/devicetree.cb          | 8 ++++----
 .../starlabs/starbook/variants/rpl/devicetree.cb          | 8 ++++----
 .../starlabs/starbook/variants/tgl/devicetree.cb          | 8 ++++----
 .../starlabs/starfighter/variants/rpl/devicetree.cb       | 8 ++++----
 .../starlabs/starlite_adl/variants/mk_v/devicetree.cb     | 8 ++++----
 9 files changed, 36 insertions(+), 36 deletions(-)

diff --git a/src/mainboard/starlabs/byte_adl/variants/mk_ii/devicetree.cb b/src/mainboard/starlabs/byte_adl/variants/mk_ii/devicetree.cb
index df79411fa2..192c8cb216 100644
--- a/src/mainboard/starlabs/byte_adl/variants/mk_ii/devicetree.cb
+++ b/src/mainboard/starlabs/byte_adl/variants/mk_ii/devicetree.cb
@@ -11,10 +11,10 @@ chip soc/intel/alderlake
 	}"
 
 	# Power
-	register "pch_slp_s3_min_assertion_width"	= "2"			# 50ms
-	register "pch_slp_s4_min_assertion_width"	= "3"			# 1s
-	register "pch_slp_sus_min_assertion_width"	= "3"			# 500ms
-	register "pch_slp_a_min_assertion_width"	= "3"			# 2s
+	register "pch_slp_s3_min_assertion_width"	= "SLP_S3_ASSERTION_1_MS"
+	register "pch_slp_s4_min_assertion_width"	= "SLP_S4_ASSERTION_3S"
+	register "pch_slp_sus_min_assertion_width"	= "SLP_SUS_ASSERTION_1_S"
+	register "pch_slp_a_min_assertion_width"	= "SLP_A_ASSERTION_98_MS"
 
 	device domain 0 on
 		device ref igpu		on
diff --git a/src/mainboard/starlabs/starbook/variants/adl/devicetree.cb b/src/mainboard/starlabs/starbook/variants/adl/devicetree.cb
index ccbad90b06..d1e866e1bf 100644
--- a/src/mainboard/starlabs/starbook/variants/adl/devicetree.cb
+++ b/src/mainboard/starlabs/starbook/variants/adl/devicetree.cb
@@ -20,10 +20,10 @@ chip soc/intel/alderlake
 	}"
 
 	# Power
-	register "pch_slp_s3_min_assertion_width"	= "2"			# 50ms
-	register "pch_slp_s4_min_assertion_width"	= "3"			# 1s
-	register "pch_slp_sus_min_assertion_width"	= "3"			# 500ms
-	register "pch_slp_a_min_assertion_width"	= "3"			# 2s
+	register "pch_slp_s3_min_assertion_width"	= "SLP_S3_ASSERTION_1_MS"
+	register "pch_slp_s4_min_assertion_width"	= "SLP_S4_ASSERTION_3S"
+	register "pch_slp_sus_min_assertion_width"	= "SLP_SUS_ASSERTION_1_S"
+	register "pch_slp_a_min_assertion_width"	= "SLP_A_ASSERTION_98_MS"
 
 	# Device Tree
 	device domain 0 on
diff --git a/src/mainboard/starlabs/starbook/variants/adl_n/devicetree.cb b/src/mainboard/starlabs/starbook/variants/adl_n/devicetree.cb
index 5f19e50113..0e19d3df12 100644
--- a/src/mainboard/starlabs/starbook/variants/adl_n/devicetree.cb
+++ b/src/mainboard/starlabs/starbook/variants/adl_n/devicetree.cb
@@ -21,10 +21,10 @@ chip soc/intel/alderlake
 	}"
 
 	# Power
-	register "pch_slp_s3_min_assertion_width"	= "2"			# 50ms
-	register "pch_slp_s4_min_assertion_width"	= "3"			# 1s
-	register "pch_slp_sus_min_assertion_width"	= "3"			# 500ms
-	register "pch_slp_a_min_assertion_width"	= "3"			# 2s
+	register "pch_slp_s3_min_assertion_width"	= "SLP_S3_ASSERTION_1_MS"
+	register "pch_slp_s4_min_assertion_width"	= "SLP_S4_ASSERTION_3S"
+	register "pch_slp_sus_min_assertion_width"	= "SLP_SUS_ASSERTION_1_S"
+	register "pch_slp_a_min_assertion_width"	= "SLP_A_ASSERTION_98_MS"
 
 	# Device Tree
 	device domain 0 on
diff --git a/src/mainboard/starlabs/starbook/variants/cml/devicetree.cb b/src/mainboard/starlabs/starbook/variants/cml/devicetree.cb
index f0398c7d97..d502b2ad53 100644
--- a/src/mainboard/starlabs/starbook/variants/cml/devicetree.cb
+++ b/src/mainboard/starlabs/starbook/variants/cml/devicetree.cb
@@ -29,10 +29,10 @@ chip soc/intel/cannonlake
 	}"
 
 	# Power
-	register "PchPmSlpS3MinAssert"		= "2"				# 50ms
-	register "PchPmSlpS4MinAssert"		= "3"				# 1s
-	register "PchPmSlpSusMinAssert"		= "3"				# 500ms
-	register "PchPmSlpAMinAssert"		= "3"				# 2s
+	register "PchPmSlpS3MinAssert"		= "2"				# 1ms
+	register "PchPmSlpS4MinAssert"		= "3"				# 3s
+	register "PchPmSlpSusMinAssert"		= "3"				# 1s
+	register "PchPmSlpAMinAssert"		= "3"				# 98ms
 
 	# PCIe Clock
 	register "PcieClkSrcClkReq[0]"		= "PCIE_CLK_NOTUSED"
diff --git a/src/mainboard/starlabs/starbook/variants/kbl/devicetree.cb b/src/mainboard/starlabs/starbook/variants/kbl/devicetree.cb
index 3ab819ed56..dd53a01524 100644
--- a/src/mainboard/starlabs/starbook/variants/kbl/devicetree.cb
+++ b/src/mainboard/starlabs/starbook/variants/kbl/devicetree.cb
@@ -27,10 +27,10 @@ chip soc/intel/skylake
 	}"
 
 	# Power
-	register "PmConfigSlpS3MinAssert"	= "2"				# 50ms
-	register "PmConfigSlpS4MinAssert"	= "3"				# 1s
-	register "PmConfigSlpSusMinAssert"	= "3"				# 500ms
-	register "PmConfigSlpAMinAssert"	= "3"				# 2s
+	register "PmConfigSlpS3MinAssert"	= "2"				# 1ms
+	register "PmConfigSlpS4MinAssert"	= "3"				# 3s
+	register "PmConfigSlpSusMinAssert"	= "3"				# 1s
+	register "PmConfigSlpAMinAssert"	= "3"				# 98ms
 
 	# Enable the correct decode ranges on the LPC bus.
 	register "lpc_ioe"			= "LPC_IOE_EC_4E_4F |
diff --git a/src/mainboard/starlabs/starbook/variants/rpl/devicetree.cb b/src/mainboard/starlabs/starbook/variants/rpl/devicetree.cb
index 52e0411406..30c5dfc4b5 100644
--- a/src/mainboard/starlabs/starbook/variants/rpl/devicetree.cb
+++ b/src/mainboard/starlabs/starbook/variants/rpl/devicetree.cb
@@ -22,10 +22,10 @@ chip soc/intel/alderlake
 	}"
 
 	# Power
-	register "pch_slp_s3_min_assertion_width"	= "2"		# 50ms
-	register "pch_slp_s4_min_assertion_width"	= "3"		# 1s
-	register "pch_slp_sus_min_assertion_width"	= "3"		# 500ms
-	register "pch_slp_a_min_assertion_width"	= "3"		# 2s
+	register "pch_slp_s3_min_assertion_width"	= "SLP_S3_ASSERTION_1_MS"
+	register "pch_slp_s4_min_assertion_width"	= "SLP_S4_ASSERTION_3S"
+	register "pch_slp_sus_min_assertion_width"	= "SLP_SUS_ASSERTION_1_S"
+	register "pch_slp_a_min_assertion_width"	= "SLP_A_ASSERTION_98_MS"
 
 	# Device Tree
 	device domain 0 on
diff --git a/src/mainboard/starlabs/starbook/variants/tgl/devicetree.cb b/src/mainboard/starlabs/starbook/variants/tgl/devicetree.cb
index 7a7c386996..69a9c1af33 100644
--- a/src/mainboard/starlabs/starbook/variants/tgl/devicetree.cb
+++ b/src/mainboard/starlabs/starbook/variants/tgl/devicetree.cb
@@ -34,10 +34,10 @@ chip soc/intel/tigerlake
 	}"
 
 	# Power
-	register "PchPmSlpS3MinAssert"		= "2"				# 50ms
-	register "PchPmSlpS4MinAssert"		= "3"				# 1s
-	register "PchPmSlpSusMinAssert"		= "3"				# 500ms
-	register "PchPmSlpAMinAssert"		= "3"				# 2s
+	register "PchPmSlpS3MinAssert"		= "2"				# 1ms
+	register "PchPmSlpS4MinAssert"		= "3"				# 3s
+	register "PchPmSlpSusMinAssert"		= "3"				# 1s
+	register "PchPmSlpAMinAssert"		= "3"				# 98ms
 
 	# Enable the correct decode ranges on the LPC bus.
 	register "lpc_ioe"			= "LPC_IOE_EC_4E_4F |
diff --git a/src/mainboard/starlabs/starfighter/variants/rpl/devicetree.cb b/src/mainboard/starlabs/starfighter/variants/rpl/devicetree.cb
index c37ff7271f..5c85da4a16 100644
--- a/src/mainboard/starlabs/starfighter/variants/rpl/devicetree.cb
+++ b/src/mainboard/starlabs/starfighter/variants/rpl/devicetree.cb
@@ -22,10 +22,10 @@ chip soc/intel/alderlake
 	}"
 
 	# Power
-	register "pch_slp_s3_min_assertion_width"	= "2"		# 50ms
-	register "pch_slp_s4_min_assertion_width"	= "3"		# 1s
-	register "pch_slp_sus_min_assertion_width"	= "3"		# 500ms
-	register "pch_slp_a_min_assertion_width"	= "3"		# 2s
+	register "pch_slp_s3_min_assertion_width"	= "SLP_S3_ASSERTION_1_MS"
+	register "pch_slp_s4_min_assertion_width"	= "SLP_S4_ASSERTION_3S"
+	register "pch_slp_sus_min_assertion_width"	= "SLP_SUS_ASSERTION_1_S"
+	register "pch_slp_a_min_assertion_width"	= "SLP_A_ASSERTION_98_MS"
 
 	device domain 0 on
 		device ref igpu		on
diff --git a/src/mainboard/starlabs/starlite_adl/variants/mk_v/devicetree.cb b/src/mainboard/starlabs/starlite_adl/variants/mk_v/devicetree.cb
index 247c5bcaa7..38fe6d07a4 100644
--- a/src/mainboard/starlabs/starlite_adl/variants/mk_v/devicetree.cb
+++ b/src/mainboard/starlabs/starlite_adl/variants/mk_v/devicetree.cb
@@ -25,10 +25,10 @@ chip soc/intel/alderlake
 	}"
 
 	# Power
-	register "pch_slp_s3_min_assertion_width"	= "2"			# 50ms
-	register "pch_slp_s4_min_assertion_width"	= "3"			# 1s
-	register "pch_slp_sus_min_assertion_width"	= "3"			# 500ms
-	register "pch_slp_a_min_assertion_width"	= "3"			# 2s
+	register "pch_slp_s3_min_assertion_width"	= "SLP_S3_ASSERTION_1_MS"
+	register "pch_slp_s4_min_assertion_width"	= "SLP_S4_ASSERTION_3S"
+	register "pch_slp_sus_min_assertion_width"	= "SLP_SUS_ASSERTION_1_S"
+	register "pch_slp_a_min_assertion_width"	= "SLP_A_ASSERTION_98_MS"
 
 	# PM Util
 	register "pmc_gpe0_dw0"			= "PMC_GPP_F"

From 257375eb2442690df4d9ae604df70adea1f52029 Mon Sep 17 00:00:00 2001
From: Patrick Rudolph <patrick.rudolph@9elements.com>
Date: Wed, 5 Mar 2025 09:50:53 +0100
Subject: [PATCH 0326/3886] device/pci_rom: Update debug message

Do not assume that a VBIOS has been run when loaded below 1MiB.
On recent AMD platforms the VBIOS is loaded into the C/D-segment,
but it's not run as CONFIG_VGA_ROM_RUN is not set.

Since commit 5f5aa79 "device/pci_rom: Move VBIOS checksum fix" the
VBIOS has a valid checksum in ati_rom_acpi_fill_vfct(), thus it's
not possible to tell if it has been run or ATOMBIOS tables have
been modified.

Update the debug message to avoid confusion.

Change-Id: I63289ecf2c212f3d95e022e8c47dcd0ac610d970
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86732
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
---
 src/device/pci_rom.c | 6 +-----
 1 file changed, 1 insertion(+), 5 deletions(-)

diff --git a/src/device/pci_rom.c b/src/device/pci_rom.c
index 0fe94dbb56..229c6fae4a 100644
--- a/src/device/pci_rom.c
+++ b/src/device/pci_rom.c
@@ -226,11 +226,7 @@ ati_rom_acpi_fill_vfct(const struct device *device, acpi_vfct_t *vfct_struct,
 		return current;
 	}
 
-	printk(BIOS_DEBUG, "           Copying %sVBIOS image from %p\n",
-			rom == (struct rom_header *)
-					(uintptr_t)PCI_VGA_RAM_IMAGE_START ?
-			"initialized " : "",
-			rom);
+	printk(BIOS_DEBUG, "           Copying VBIOS image from %p\n", rom);
 
 	header->DeviceID = device->device;
 	header->VendorID = device->vendor;

From 85e503e6416e14e357e021632a6ae48d2cf8b208 Mon Sep 17 00:00:00 2001
From: Patrick Rudolph <patrick.rudolph@9elements.com>
Date: Tue, 11 Feb 2025 14:53:55 +0100
Subject: [PATCH 0327/3886] device/pci_rom: Keep track of VBIOS

Currently the VBIOS is placed somewhere in DRAM when necessary.
While generating ACPI tables the code attempts to find the VBIOS
by looking at "known" places.

Simplify the code and keep track of the VBIOS using a pointer in
struct device by filling it in pci_rom_load().

The following patches will reuse this pointer to generalize the
code even more.

Change-Id: Ib27d30e3b07740d6098d4f7a5c4f5d8bce976f00
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86385
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/device/pci_rom.c        | 101 ++++++++++++++++--------------------
 src/include/device/device.h |  12 +++++
 2 files changed, 56 insertions(+), 57 deletions(-)

diff --git a/src/device/pci_rom.c b/src/device/pci_rom.c
index 229c6fae4a..49b9923d47 100644
--- a/src/device/pci_rom.c
+++ b/src/device/pci_rom.c
@@ -169,12 +169,15 @@ struct rom_header *pci_rom_load(struct device *dev,
 			memcpy((void *)PCI_VGA_RAM_IMAGE_START, rom_header,
 			       rom_size);
 		}
+
+		dev->pci_vga_option_rom = (struct rom_header *)(PCI_VGA_RAM_IMAGE_START);
 		return (struct rom_header *)(PCI_VGA_RAM_IMAGE_START);
 	}
 
 	printk(BIOS_DEBUG, "Copying non-VGA ROM image from %p to %p, 0x%x bytes\n",
 	       rom_header, pci_ram_image_start, rom_size);
 
+	dev->pci_vga_option_rom = (struct rom_header *)pci_ram_image_start;
 	memcpy(pci_ram_image_start, rom_header, rom_size);
 	pci_ram_image_start += rom_size;
 	return (struct rom_header *)(pci_ram_image_start-rom_size);
@@ -183,30 +186,6 @@ struct rom_header *pci_rom_load(struct device *dev,
 /* ACPI */
 #if CONFIG(HAVE_ACPI_TABLES)
 
-/* VBIOS may be modified after oprom init so use the copy if present. */
-static struct rom_header *check_initialized(const struct device *dev)
-{
-	struct rom_header *run_rom;
-	struct pci_data *rom_data;
-
-	if (!CONFIG(VGA_ROM_RUN) && !CONFIG(RUN_FSP_GOP))
-		return NULL;
-
-	run_rom = (struct rom_header *)(uintptr_t)PCI_VGA_RAM_IMAGE_START;
-	if (read_le16(&run_rom->signature) != PCI_ROM_HDR)
-		return NULL;
-
-	rom_data = (struct pci_data *)((u8 *)run_rom
-			+ read_le16(&run_rom->data));
-
-	if (read_le32(&rom_data->signature) == PCI_DATA_HDR
-			&& read_le16(&rom_data->device) == dev->device
-			&& read_le16(&rom_data->vendor) == dev->vendor)
-		return run_rom;
-	else
-		return NULL;
-}
-
 static unsigned long
 ati_rom_acpi_fill_vfct(const struct device *device, acpi_vfct_t *vfct_struct,
 		       unsigned long current)
@@ -214,7 +193,8 @@ ati_rom_acpi_fill_vfct(const struct device *device, acpi_vfct_t *vfct_struct,
 	acpi_vfct_image_hdr_t *header = &vfct_struct->image_hdr;
 	struct rom_header *rom;
 
-	rom = check_initialized(device);
+	/* Already loaded into DRAM? */
+	rom = device->pci_vga_option_rom;
 	if (!rom)
 		rom = pci_rom_probe(device);
 	if (!rom) {
@@ -273,6 +253,7 @@ pci_rom_write_acpi_tables(const struct device *device, unsigned long current,
 
 void pci_rom_ssdt(const struct device *device)
 {
+	const struct rom_header *rom;
 	static size_t ngfx;
 
 	/* Only handle display devices */
@@ -283,12 +264,43 @@ void pci_rom_ssdt(const struct device *device)
 	if (!device->enabled)
 		return;
 
-	/* Probe for option rom */
-	const struct rom_header *rom = pci_rom_probe(device);
-	if (!rom || !rom->size) {
-		printk(BIOS_WARNING, "%s: Missing PCI Option ROM\n",
-		       dev_path(device));
-		return;
+	/* Already loaded into DRAM? */
+	rom = device->pci_vga_option_rom;
+	if (!rom) {
+		/* Probe for option rom */
+		rom = pci_rom_probe(device);
+		if (!rom || !rom->size) {
+			printk(BIOS_WARNING, "%s: Missing PCI Option ROM\n",
+			dev_path(device));
+			return;
+		}
+
+		/* Supports up to four devices. */
+		if ((CBMEM_ID_ROM0 + ngfx) > CBMEM_ID_ROM3) {
+			printk(BIOS_ERR, "%s: Out of CBMEM IDs.\n", dev_path(device));
+			return;
+		}
+
+		/* Prepare memory */
+		const size_t cbrom_length = rom->size * 512;
+		if (!cbrom_length) {
+			printk(BIOS_ERR, "%s: ROM has zero length!\n",
+			dev_path(device));
+			return;
+		}
+
+		void *cbrom = cbmem_add(CBMEM_ID_ROM0 + ngfx, cbrom_length);
+		if (!cbrom) {
+			printk(BIOS_ERR, "%s: Failed to allocate CBMEM.\n",
+			dev_path(device));
+			return;
+		}
+		/* Increment CBMEM id for next device */
+		ngfx++;
+
+		memcpy(cbrom, rom, cbrom_length);
+
+		rom = cbrom;
 	}
 
 	const char *scope = acpi_device_path(device);
@@ -297,34 +309,9 @@ void pci_rom_ssdt(const struct device *device)
 		return;
 	}
 
-	/* Supports up to four devices. */
-	if ((CBMEM_ID_ROM0 + ngfx) > CBMEM_ID_ROM3) {
-		printk(BIOS_ERR, "%s: Out of CBMEM IDs.\n", dev_path(device));
-		return;
-	}
-
-	/* Prepare memory */
-	const size_t cbrom_length = rom->size * 512;
-	if (!cbrom_length) {
-		printk(BIOS_ERR, "%s: ROM has zero length!\n",
-		       dev_path(device));
-		return;
-	}
-
-	void *cbrom = cbmem_add(CBMEM_ID_ROM0 + ngfx, cbrom_length);
-	if (!cbrom) {
-		printk(BIOS_ERR, "%s: Failed to allocate CBMEM.\n",
-		       dev_path(device));
-		return;
-	}
-	/* Increment CBMEM id for next device */
-	ngfx++;
-
-	memcpy(cbrom, rom, cbrom_length);
-
 	/* write _ROM method */
 	acpigen_write_scope(scope);
-	acpigen_write_rom(cbrom, cbrom_length);
+	acpigen_write_rom((void *)rom, rom->size * 512);
 	acpigen_pop_len(); /* pop scope */
 }
 #endif
diff --git a/src/include/device/device.h b/src/include/device/device.h
index 901f717624..ad9d9c5318 100644
--- a/src/include/device/device.h
+++ b/src/include/device/device.h
@@ -36,6 +36,7 @@ struct chip_operations {
 struct bus;
 
 struct acpi_rsdp;
+struct rom_header;
 
 struct device_operations {
 	void (*read_resources)(struct device *dev);
@@ -127,6 +128,17 @@ struct device {
 	struct device_operations *ops;
 	struct chip_operations *chip_ops;
 	const char *name;
+	/*
+	 * A pointer to the corresponding PCI Option ROM.
+	 *
+	 * When set the Option ROM has been placed in usable DRAM in
+	 * an area that is marked as reserved. This can be for example
+	 * the legacy C-segment or a CBMEM area. The Option ROM is
+	 * read writeable and guaranteed to be used by the device.
+	 * The PCIR data header might still have a different vendor and
+	 * device ID.
+	 */
+	struct rom_header *pci_vga_option_rom;
 #if CONFIG(GENERATE_SMBIOS_TABLES)
 	u8 smbios_slot_type;
 	u8 smbios_slot_data_width;

From d541890e7695018cd24640b9ba127e53a0e37e13 Mon Sep 17 00:00:00 2001
From: Patrick Rudolph <patrick.rudolph@9elements.com>
Date: Tue, 11 Feb 2025 13:46:10 +0100
Subject: [PATCH 0328/3886] device/pci_rom: Support non VGA iGPUs

Recent AMD iGPUs are not VGA compatible anymore, thus they don't
identify themself as "VGA compatible" anymore by the PCI class code.
Since the PCI VGA Option ROM code assumes it only runs on VGA
compatible devices, relax the ACPI code part to handle display devices
as well. In order to run a VBIOS in coreboot it still must be VGA
compatible, but for ACPI table generation, where no code is run, it's
not necessary any more.

The new code allows to use Linux's amdgpu driver on AMD/glinda.

TEST: On amd/birman+ the amdgpu kernel drivers starts and dmesg shows:
[    3.010224] [drm] amdgpu kernel modesetting enabled.

The coreboot log shows:

[INFO ]  CBFS: Found 'pci1002,150e.rom' @0x10a40 size 0x4400 in mcache @0x1b7dd184
[DEBUG]  In CBFS, ROM address for PCI: 00:02:00.0 = 0xff012a6c
[DEBUG]  Class Code mismatch ROM 00030000, dev 00038000
[DEBUG]  Copying non-VGA ROM image from 0xff012a6c to 0x000d0000, 0x4400 bytes
[...]
             Copying initialized VBIOS image from 0x000d0000
[DEBUG]  ACPI:    * VFCT at 1b5cb960

Change-Id: I623cd80b45b148b91f2796b22a589bbede0feeeb
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86386
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
---
 src/device/pci_rom.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/device/pci_rom.c b/src/device/pci_rom.c
index 49b9923d47..037f96eb66 100644
--- a/src/device/pci_rom.c
+++ b/src/device/pci_rom.c
@@ -226,8 +226,8 @@ unsigned long
 pci_rom_write_acpi_tables(const struct device *device, unsigned long current,
 			  struct acpi_rsdp *rsdp)
 {
-	/* Only handle VGA devices */
-	if ((device->class >> 8) != PCI_CLASS_DISPLAY_VGA)
+	/* Only handle display devices */
+	if ((device->class >> 16) != PCI_BASE_CLASS_DISPLAY)
 		return current;
 
 	/* Only handle enabled devices */

From dbcfa67c2888666bca5a06b37bdafc585fd5fbf6 Mon Sep 17 00:00:00 2001
From: Patrick Rudolph <patrick.rudolph@9elements.com>
Date: Wed, 5 Mar 2025 11:24:56 +0100
Subject: [PATCH 0329/3886] device/pci_device: Move PCI Option ROM code into
 pci_rom.c

Move PCI Option ROM handling code into device/pci_rom.c as it's
already using a majority of functions within this file.

Change-Id: I50fc3bf45a1ab6572ab031b9e24ca2f882a13aad
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86733
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ana Carolina Cabral <ana.cpmelo95@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
---
 src/device/pci_device.c      | 90 +-------------------------------
 src/device/pci_rom.c         | 99 ++++++++++++++++++++++++++++++++++--
 src/include/device/pci_rom.h |  1 +
 3 files changed, 99 insertions(+), 91 deletions(-)

diff --git a/src/device/pci_device.c b/src/device/pci_device.c
index d03d88df39..29fde7ca6c 100644
--- a/src/device/pci_device.c
+++ b/src/device/pci_device.c
@@ -839,97 +839,11 @@ void pci_dev_set_subsystem(struct device *dev, unsigned int vendor,
 	}
 }
 
-static int should_run_oprom(struct device *dev, struct rom_header *rom)
-{
-	static int should_run = -1;
-
-	if (dev->upstream->segment_group) {
-		printk(BIOS_ERR, "Only option ROMs of devices in first PCI segment group can "
-				 "be run.\n");
-		return 0;
-	}
-
-	if (CONFIG(VENDORCODE_ELTAN_VBOOT))
-		if (rom != NULL)
-			if (!verified_boot_should_run_oprom(rom))
-				return 0;
-
-	if (should_run >= 0)
-		return should_run;
-
-	if (CONFIG(ALWAYS_RUN_OPROM)) {
-		should_run = 1;
-		return should_run;
-	}
-
-	/* Don't run VGA option ROMs, unless we have to print
-	 * something on the screen before the kernel is loaded.
-	 */
-	should_run = display_init_required();
-
-	if (!should_run)
-		printk(BIOS_DEBUG, "Not running VGA Option ROM\n");
-	return should_run;
-}
-
-static int should_load_oprom(struct device *dev)
-{
-	/* If S3_VGA_ROM_RUN is disabled, skip running VGA option
-	 * ROMs when coming out of an S3 resume.
-	 */
-	if (!CONFIG(S3_VGA_ROM_RUN) && acpi_is_wakeup_s3() &&
-		((dev->class >> 8) == PCI_CLASS_DISPLAY_VGA))
-		return 0;
-	if (CONFIG(ALWAYS_LOAD_OPROM))
-		return 1;
-	if (should_run_oprom(dev, NULL))
-		return 1;
-
-	return 0;
-}
-
-static void oprom_pre_graphics_stall(void)
-{
-	if (CONFIG_PRE_GRAPHICS_DELAY_MS)
-		mdelay(CONFIG_PRE_GRAPHICS_DELAY_MS);
-}
-
 /** Default handler: only runs the relevant PCI BIOS. */
 void pci_dev_init(struct device *dev)
 {
-	struct rom_header *rom, *ram;
-
-	if (!CONFIG(VGA_ROM_RUN))
-		return;
-
-	/* Only execute VGA ROMs. */
-	if (((dev->class >> 8) != PCI_CLASS_DISPLAY_VGA))
-		return;
-
-	if (!should_load_oprom(dev))
-		return;
-	timestamp_add_now(TS_OPROM_INITIALIZE);
-
-	rom = pci_rom_probe(dev);
-	if (rom == NULL)
-		return;
-
-	ram = pci_rom_load(dev, rom);
-	if (ram == NULL)
-		return;
-	timestamp_add_now(TS_OPROM_COPY_END);
-
-	if (!should_run_oprom(dev, rom))
-		return;
-
-	/* Wait for any configured pre-graphics delay */
-	oprom_pre_graphics_stall();
-
-	run_bios(dev, (unsigned long)ram);
-
-	gfx_set_init_done(1);
-	printk(BIOS_DEBUG, "VGA Option ROM was run\n");
-	timestamp_add_now(TS_OPROM_END);
+	if (CONFIG(VGA_ROM_RUN))
+		pci_rom_run(dev);
 }
 
 /** Default device operation for PCI devices */
diff --git a/src/device/pci_rom.c b/src/device/pci_rom.c
index 037f96eb66..dc41ef14ce 100644
--- a/src/device/pci_rom.c
+++ b/src/device/pci_rom.c
@@ -1,16 +1,19 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
+#include <acpi/acpigen.h>
+#include <bootmode.h>
+#include <cbfs.h>
+#include <cbmem.h>
 #include <console/console.h>
 #include <commonlib/endian.h>
+#include <delay.h>
 #include <device/device.h>
 #include <device/pci.h>
 #include <device/pci_ids.h>
 #include <device/pci_ops.h>
 #include <stdio.h>
 #include <string.h>
-#include <cbfs.h>
-#include <cbmem.h>
-#include <acpi/acpigen.h>
+#include <timestamp.h>
 
 /* Rmodules don't like weak symbols. */
 u32 __weak map_oprom_vendev(u32 vendev) { return vendev; }
@@ -183,6 +186,96 @@ struct rom_header *pci_rom_load(struct device *dev,
 	return (struct rom_header *)(pci_ram_image_start-rom_size);
 }
 
+static int should_run_oprom(struct device *dev, struct rom_header *rom)
+{
+	static int should_run = -1;
+
+	if (dev->upstream->segment_group) {
+		printk(BIOS_ERR, "Only option ROMs of devices in first PCI segment group can "
+				 "be run.\n");
+		return 0;
+	}
+
+	if (CONFIG(VENDORCODE_ELTAN_VBOOT))
+		if (rom != NULL)
+			if (!verified_boot_should_run_oprom(rom))
+				return 0;
+
+	if (should_run >= 0)
+		return should_run;
+
+	if (CONFIG(ALWAYS_RUN_OPROM)) {
+		should_run = 1;
+		return should_run;
+	}
+
+	/* Don't run VGA option ROMs, unless we have to print
+	 * something on the screen before the kernel is loaded.
+	 */
+	should_run = display_init_required();
+
+	if (!should_run)
+		printk(BIOS_DEBUG, "Not running VGA Option ROM\n");
+	return should_run;
+}
+
+static int should_load_oprom(struct device *dev)
+{
+	/* If S3_VGA_ROM_RUN is disabled, skip running VGA option
+	 * ROMs when coming out of an S3 resume.
+	 */
+	if (!CONFIG(S3_VGA_ROM_RUN) && acpi_is_wakeup_s3() &&
+		((dev->class >> 8) == PCI_CLASS_DISPLAY_VGA))
+		return 0;
+	if (CONFIG(ALWAYS_LOAD_OPROM))
+		return 1;
+	if (should_run_oprom(dev, NULL))
+		return 1;
+
+	return 0;
+}
+
+static void oprom_pre_graphics_stall(void)
+{
+	if (CONFIG_PRE_GRAPHICS_DELAY_MS)
+		mdelay(CONFIG_PRE_GRAPHICS_DELAY_MS);
+}
+
+/** Load an Option ROM into the C-segment and run it if necessary */
+void pci_rom_run(struct device *dev)
+{
+	struct rom_header *rom, *ram;
+
+	/* Only execute VGA ROMs. */
+	if (((dev->class >> 8) != PCI_CLASS_DISPLAY_VGA))
+		return;
+
+	if (!should_load_oprom(dev))
+		return;
+	timestamp_add_now(TS_OPROM_INITIALIZE);
+
+	rom = pci_rom_probe(dev);
+	if (rom == NULL)
+		return;
+
+	ram = pci_rom_load(dev, rom);
+	if (ram == NULL)
+		return;
+	timestamp_add_now(TS_OPROM_COPY_END);
+
+	if (!should_run_oprom(dev, rom))
+		return;
+
+	/* Wait for any configured pre-graphics delay */
+	oprom_pre_graphics_stall();
+
+	run_bios(dev, (unsigned long)ram);
+
+	gfx_set_init_done(1);
+	printk(BIOS_DEBUG, "VGA Option ROM was run\n");
+	timestamp_add_now(TS_OPROM_END);
+}
+
 /* ACPI */
 #if CONFIG(HAVE_ACPI_TABLES)
 
diff --git a/src/include/device/pci_rom.h b/src/include/device/pci_rom.h
index 531ec18ffa..5e4b85e0ad 100644
--- a/src/include/device/pci_rom.h
+++ b/src/include/device/pci_rom.h
@@ -53,6 +53,7 @@ pci_rom_write_acpi_tables(const struct device *device,
 						  unsigned long current,
 						  struct acpi_rsdp *rsdp);
 
+void pci_rom_run(struct device *dev);
 void pci_rom_ssdt(const struct device *device);
 
 u32 map_oprom_vendev(u32 vendev);

From 8fb1f6513e9851f85492fb95d826d20abf678d1a Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Sat, 8 Mar 2025 20:57:50 -0600
Subject: [PATCH 0330/3886] soc/intel/cmn/block/cnvi: Add missing parenthesis
 in ASL code

It was accidentally deleted in a recent commit, but missed in review
since it is in a comment and not the actual acpigen code.

Change-Id: I0d28c2a67579a135e9002eaab9450353e8eec2d5
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86773
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
---
 src/soc/intel/common/block/cnvi/cnvi.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/soc/intel/common/block/cnvi/cnvi.c b/src/soc/intel/common/block/cnvi/cnvi.c
index e23ada8d8a..88225fe1e8 100644
--- a/src/soc/intel/common/block/cnvi/cnvi.c
+++ b/src/soc/intel/common/block/cnvi/cnvi.c
@@ -133,7 +133,7 @@ static void cnvw_fill_ssdt(const struct device *dev)
  *							If ((\_SB.PCI0.GBTR() == One))
  *							{
  *								\_SB.PCI0.BTRK (Zero)
- *								Sleep (160
+ *								Sleep (160)
  *								Local2 = One
  *							}
  *						}

From 30c4e79294fa39c83afc5f41f0b2c9035f3dddd2 Mon Sep 17 00:00:00 2001
From: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Date: Sat, 8 Mar 2025 12:08:01 +0900
Subject: [PATCH 0331/3886] util/lint: Add support for FreeBSD

Change-Id: I9f7ceb2233d5d68b6e6f57faeaa0253390e0e003
Signed-off-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86768
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
---
 util/lint/lint | 11 ++++++-----
 1 file changed, 6 insertions(+), 5 deletions(-)

diff --git a/util/lint/lint b/util/lint/lint
index 56edaa65c4..30109ae0e0 100755
--- a/util/lint/lint
+++ b/util/lint/lint
@@ -30,11 +30,12 @@ junit_write () {
 }
 
 # Look if we have getopt. If not, build it.
-if [ "$(uname)" = "Darwin" ]; then
-  GETOPT="getopt hIJ"
-else
-  GETOPT="getopt -l help,junit,invert -o hIJ"
-fi
+case "$(uname)" in
+Darwin|FreeBSD)
+  GETOPT="getopt hIJ" ;;
+*)
+  GETOPT="getopt -l help,junit,invert -o hIJ" ;;
+esac
 
 if ! cmd_args="$($GETOPT -- "$@")"; then
 	usage

From 5495f7fc153cd6a8d8b86f2820f4fe947c178b86 Mon Sep 17 00:00:00 2001
From: Shuo Liu <shuo.liu@intel.com>
Date: Fri, 7 Mar 2025 22:59:54 +0800
Subject: [PATCH 0332/3886] MAINTAINERS: Add Shuo to x86 maintainer
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Add Shuo to x86 maintainer to focus on x86 arch changes impacting
Xeon-SP.

Change-Id: Ia273f3d6fc1e4b13bd1f695976209a95adc03f60
Signed-off-by: Shuo Liu <shuo.liu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86760
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
---
 MAINTAINERS | 1 +
 1 file changed, 1 insertion(+)

diff --git a/MAINTAINERS b/MAINTAINERS
index 8a2b21f869..d180142cfa 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -704,6 +704,7 @@ F:	util/riscv/
 
 X86 ARCHITECTURE
 M:	Jérémy Compostella <jeremy.compostella@intel.com>
+M:	Shuo Liu <shuo.liu@intel.com>
 S:	MAINTAINED
 F:	src/arch/x86/
 F:	src/cpu/x86/

From c6754fe0af0ef159421d4309e11496d4e506d536 Mon Sep 17 00:00:00 2001
From: Wisley Chen <wisley.chen@quanta.corp-partner.google.com>
Date: Tue, 11 Feb 2025 18:33:32 +0800
Subject: [PATCH 0333/3886] spd/lp4x: Add Nanya memory part

Add Nanya memory part NT6AP512T32BL-J1 in lp4 list.

BUG=b:401424949
TEST=util/spd_tools/bin/spd_gen spd/lp4x/memory_parts.json lp4x

Change-Id: I953c09c7d8d2cdd670187c5285ebedfcc66aa021
Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86761
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
---
 spd/lp4x/memory_parts.json                      | 15 ++++++++++++++-
 spd/lp4x/set-0/parts_spd_manifest.generated.txt |  1 +
 spd/lp4x/set-1/parts_spd_manifest.generated.txt |  1 +
 3 files changed, 16 insertions(+), 1 deletion(-)

diff --git a/spd/lp4x/memory_parts.json b/spd/lp4x/memory_parts.json
index d4e0e9ae8f..a6cee87e10 100644
--- a/spd/lp4x/memory_parts.json
+++ b/spd/lp4x/memory_parts.json
@@ -411,6 +411,19 @@
                 "ranksPerChannel": 1,
                 "speedMbps": 4267
             }
-	}
+	},
+        {
+            "name": "NT6AP512T32BL-J1",
+            "attribs": {
+                "densityPerChannelGb": 8,
+                "banks": 8,
+                "channelsPerDie": 1,
+                "diesPerPackage": 2,
+                "bitWidthPerChannel": 16,
+                "ranksPerChannel": 1,
+                "speedMbps": 4267
+            }
+        }
+
     ]
 }
diff --git a/spd/lp4x/set-0/parts_spd_manifest.generated.txt b/spd/lp4x/set-0/parts_spd_manifest.generated.txt
index 004d1bd86c..8b2eb7bfb0 100644
--- a/spd/lp4x/set-0/parts_spd_manifest.generated.txt
+++ b/spd/lp4x/set-0/parts_spd_manifest.generated.txt
@@ -35,3 +35,4 @@ K4UCE3Q4AB-MGCL,spd-2.hex
 CXDB4ABAM-ML,spd-8.hex
 CXDB4CBAM-ML-A,spd-8.hex
 SDVB8D8A34XGCL3N3T,spd-1.hex
+NT6AP512T32BL-J1,spd-8.hex
diff --git a/spd/lp4x/set-1/parts_spd_manifest.generated.txt b/spd/lp4x/set-1/parts_spd_manifest.generated.txt
index 1604a11196..7dc50f92e6 100644
--- a/spd/lp4x/set-1/parts_spd_manifest.generated.txt
+++ b/spd/lp4x/set-1/parts_spd_manifest.generated.txt
@@ -35,3 +35,4 @@ K4UCE3Q4AB-MGCL,spd-2.hex
 CXDB4ABAM-ML,spd-11.hex
 CXDB4CBAM-ML-A,spd-11.hex
 SDVB8D8A34XGCL3N3T,spd-5.hex
+NT6AP512T32BL-J1,spd-11.hex

From 0349aecda041b088f7ae12517ba849c82adeec94 Mon Sep 17 00:00:00 2001
From: Wisley Chen <wisley.chen@quanta.corp-partner.google.com>
Date: Fri, 7 Mar 2025 15:24:24 +0800
Subject: [PATCH 0334/3886] mb/google/brya/var/redrix: add memory
 NT6AP512T32BL-J1

Generate SPD id for Nanya memory NT6AP512T32BL-J1

BUG=b:401659784
TEST=run part_id_gen to generate SPD id

Change-Id: I655590e43fcd9c3eb704d09edd6dcee51b635256
Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86762
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
---
 src/mainboard/google/brya/variants/redrix/memory/Makefile.mk     | 1 +
 .../google/brya/variants/redrix/memory/dram_id.generated.txt     | 1 +
 .../google/brya/variants/redrix/memory/mem_parts_used.txt        | 1 +
 3 files changed, 3 insertions(+)

diff --git a/src/mainboard/google/brya/variants/redrix/memory/Makefile.mk b/src/mainboard/google/brya/variants/redrix/memory/Makefile.mk
index f0d6e3d30f..7c1a5c5b50 100644
--- a/src/mainboard/google/brya/variants/redrix/memory/Makefile.mk
+++ b/src/mainboard/google/brya/variants/redrix/memory/Makefile.mk
@@ -9,3 +9,4 @@ SPD_SOURCES += spd/lp4x/set-0/spd-1.hex      # ID = 1(0b0001)  Parts = H9HCNNNBK
 SPD_SOURCES += spd/lp4x/set-0/spd-3.hex      # ID = 2(0b0010)  Parts = H9HCNNNCPMMLXR-NEE, K4UBE3D4AA-MGCR, MT53E1G32D2NP-046 WT:B, H54G56CYRBX247, K4UBE3D4AB-MGCL
 SPD_SOURCES += spd/lp4x/set-0/spd-2.hex      # ID = 3(0b0011)  Parts = H9HCNNNFAMMLXR-NEE, H54G68CYRBX248, K4UCE3Q4AB-MGCL
 SPD_SOURCES += spd/lp4x/set-0/spd-7.hex      # ID = 4(0b0100)  Parts = MT53E2G32D4NQ-046 WT:A, MT53E2G32D4NQ-046 WT:C
+SPD_SOURCES += spd/lp4x/set-0/spd-8.hex      # ID = 5(0b0101)  Parts = NT6AP512T32BL-J1
diff --git a/src/mainboard/google/brya/variants/redrix/memory/dram_id.generated.txt b/src/mainboard/google/brya/variants/redrix/memory/dram_id.generated.txt
index 74768aa937..bf352ec950 100644
--- a/src/mainboard/google/brya/variants/redrix/memory/dram_id.generated.txt
+++ b/src/mainboard/google/brya/variants/redrix/memory/dram_id.generated.txt
@@ -21,3 +21,4 @@ K4UBE3D4AB-MGCL                2 (0010)
 MT53E2G32D4NQ-046 WT:C         4 (0100)
 H54G68CYRBX248                 3 (0011)
 K4UCE3Q4AB-MGCL                3 (0011)
+NT6AP512T32BL-J1               5 (0101)
diff --git a/src/mainboard/google/brya/variants/redrix/memory/mem_parts_used.txt b/src/mainboard/google/brya/variants/redrix/memory/mem_parts_used.txt
index 361f875a33..b44b956013 100644
--- a/src/mainboard/google/brya/variants/redrix/memory/mem_parts_used.txt
+++ b/src/mainboard/google/brya/variants/redrix/memory/mem_parts_used.txt
@@ -15,3 +15,4 @@ K4UBE3D4AB-MGCL
 MT53E2G32D4NQ-046 WT:C
 H54G68CYRBX248
 K4UCE3Q4AB-MGCL
+NT6AP512T32BL-J1

From 4a84a1bd61da53fd2cd7ccea66acc2919bcb512e Mon Sep 17 00:00:00 2001
From: Wisley Chen <wisley.chen@quanta.corp-partner.google.com>
Date: Tue, 11 Feb 2025 18:38:03 +0800
Subject: [PATCH 0335/3886] mb/google/brya/var/anahera: add memory
 NT6AP512T32BL-J1

Generate SPD id for Nanya memory NT6AP512T32BL-J1

BUG=b:401424949
TEST=run part_id_gen to generate SPD id

Change-Id: I4b207076b73a03059262e0244f5dd0ea24625ff0
Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86763
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
---
 src/mainboard/google/brya/variants/anahera/memory/Makefile.mk    | 1 +
 .../google/brya/variants/anahera/memory/dram_id.generated.txt    | 1 +
 .../google/brya/variants/anahera/memory/mem_parts_used.txt       | 1 +
 3 files changed, 3 insertions(+)

diff --git a/src/mainboard/google/brya/variants/anahera/memory/Makefile.mk b/src/mainboard/google/brya/variants/anahera/memory/Makefile.mk
index 00fd95a032..ad7f44fa91 100644
--- a/src/mainboard/google/brya/variants/anahera/memory/Makefile.mk
+++ b/src/mainboard/google/brya/variants/anahera/memory/Makefile.mk
@@ -9,3 +9,4 @@ SPD_SOURCES += spd/lp4x/set-0/spd-1.hex      # ID = 1(0b0001)  Parts = H9HCNNNBK
 SPD_SOURCES += spd/lp4x/set-0/spd-3.hex      # ID = 2(0b0010)  Parts = H9HCNNNCPMMLXR-NEE, K4UBE3D4AA-MGCR, MT53E1G32D2NP-046 WT:B, H54G56CYRBX247, K4UBE3D4AB-MGCL
 SPD_SOURCES += spd/lp4x/set-0/spd-2.hex      # ID = 3(0b0011)  Parts = H9HCNNNFAMMLXR-NEE, H54G68CYRBX248, K4UCE3Q4AB-MGCL
 SPD_SOURCES += spd/lp4x/set-0/spd-7.hex      # ID = 4(0b0100)  Parts = MT53E2G32D4NQ-046 WT:A, MT53E2G32D4NQ-046 WT:C
+SPD_SOURCES += spd/lp4x/set-0/spd-8.hex      # ID = 5(0b0101)  Parts = NT6AP512T32BL-J1
diff --git a/src/mainboard/google/brya/variants/anahera/memory/dram_id.generated.txt b/src/mainboard/google/brya/variants/anahera/memory/dram_id.generated.txt
index d162828573..a748eda65c 100644
--- a/src/mainboard/google/brya/variants/anahera/memory/dram_id.generated.txt
+++ b/src/mainboard/google/brya/variants/anahera/memory/dram_id.generated.txt
@@ -21,3 +21,4 @@ K4UBE3D4AB-MGCL                2 (0010)
 MT53E2G32D4NQ-046 WT:C         4 (0100)
 H54G68CYRBX248                 3 (0011)
 K4UCE3Q4AB-MGCL                3 (0011)
+NT6AP512T32BL-J1               5 (0101)
diff --git a/src/mainboard/google/brya/variants/anahera/memory/mem_parts_used.txt b/src/mainboard/google/brya/variants/anahera/memory/mem_parts_used.txt
index 361f875a33..b44b956013 100644
--- a/src/mainboard/google/brya/variants/anahera/memory/mem_parts_used.txt
+++ b/src/mainboard/google/brya/variants/anahera/memory/mem_parts_used.txt
@@ -15,3 +15,4 @@ K4UBE3D4AB-MGCL
 MT53E2G32D4NQ-046 WT:C
 H54G68CYRBX248
 K4UCE3Q4AB-MGCL
+NT6AP512T32BL-J1

From 940d1d0868381b296955d15d80786850bfed8cec Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Micha=C5=82=20=C5=BBygowski?= <michal.zygowski@3mdeb.com>
Date: Thu, 1 Aug 2024 11:46:55 +0200
Subject: [PATCH 0336/3886] soc/intel/cannonlake: Let coreboot lock
 MSR_IA32_DEBUG_INTERFACE
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Intel TXT requires the debug interface to be disabled. There is no
way to program the MSR_IA32_DEBUG_INTERFACE using FSP as needed, so
let coreboot handle it.

TEST=Boot Linux with tboot on Protectli VP4670 with Intel TXT enabled

Change-Id: I7ed4382bbe68f03e8eca151245c13928609f434f
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83730
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
---
 src/include/cpu/intel/msr.h           |  3 +++
 src/soc/intel/cannonlake/fsp_params.c |  9 +++++++++
 src/soc/intel/cannonlake/lockdown.c   | 17 +++++++++++++++++
 3 files changed, 29 insertions(+)

diff --git a/src/include/cpu/intel/msr.h b/src/include/cpu/intel/msr.h
index 75c12a8be9..d3ff86dc32 100644
--- a/src/include/cpu/intel/msr.h
+++ b/src/include/cpu/intel/msr.h
@@ -15,6 +15,9 @@
 #define MSR_BC_PBEC		0x139
 #define  B_STOP_PBET		(1 << 0)
 
+#define MSR_IA32_DEBUG_INTERFACE	0xc80
+#define  MSR_IA32_DEBUG_INTERFACE_EN		(1 << 0)
+#define  MSR_IA32_DEBUG_INTERFACE_LOCK		(1 << 30)
 #define MSR_BOOT_GUARD_SACM_INFO	0x13a
 #define  V_TPM_PRESENT_MASK		0x06
 #define  B_BOOT_GUARD_SACM_INFO_NEM_ENABLED	(1 << 0)
diff --git a/src/soc/intel/cannonlake/fsp_params.c b/src/soc/intel/cannonlake/fsp_params.c
index df5fcee36f..f1db0f7d20 100644
--- a/src/soc/intel/cannonlake/fsp_params.c
+++ b/src/soc/intel/cannonlake/fsp_params.c
@@ -717,6 +717,15 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
 	 */
 	s_cfg->SpiFlashCfgLockDown = lockdown_by_fsp;
 #endif
+	/*
+	 * IA32_DEBUG_INTERFACE_MSR has to be locked by coreboot,
+	 * because FSP does not do it unless DebugInterfaceEnable is 1.
+	 * But to use Intel TXT, the debug interface has to be disabled,
+	 * so let coreboot handle the IA32_DEBUG_INTERFACE_MSR programming.
+	 */
+	supd->FspsConfig.DebugInterfaceEnable = 0;
+	supd->FspsTestConfig.DebugInterfaceEnable = 0;
+	supd->FspsTestConfig.DebugInterfaceLockEnable = 0;
 
 #if !CONFIG(SOC_INTEL_COMETLAKE)
 	s_cfg->VrPowerDeliveryDesign = config->VrPowerDeliveryDesign;
diff --git a/src/soc/intel/cannonlake/lockdown.c b/src/soc/intel/cannonlake/lockdown.c
index 3205c7f303..c255858c57 100644
--- a/src/soc/intel/cannonlake/lockdown.c
+++ b/src/soc/intel/cannonlake/lockdown.c
@@ -1,11 +1,27 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
+#include <cpu/intel/msr.h>
+#include <cpu/x86/msr.h>
 #include <device/mmio.h>
 #include <intelblocks/cfg.h>
 #include <intelblocks/pmclib.h>
 #include <intelpch/lockdown.h>
 #include <soc/pm.h>
 
+static void lock_debug_interface(void)
+{
+	msr_t msr = rdmsr(MSR_IA32_DEBUG_INTERFACE);
+
+	if (msr.lo & MSR_IA32_DEBUG_INTERFACE_LOCK)
+		return;
+
+	if (CONFIG(INTEL_TXT))
+		msr.lo &= ~MSR_IA32_DEBUG_INTERFACE_EN;
+
+	msr.lo |= MSR_IA32_DEBUG_INTERFACE_LOCK;
+	wrmsr(MSR_IA32_DEBUG_INTERFACE, msr);
+}
+
 static void pmc_lock_pmsync(void)
 {
 	uint8_t *pmcbase;
@@ -59,4 +75,5 @@ void soc_lockdown_config(int chipset_lockdown)
 {
 	/* PMC lock down configuration */
 	pmc_lockdown_cfg(chipset_lockdown);
+	lock_debug_interface();
 }

From bfeef0cc455e783a3ed56f40c5f816dfb973d2c4 Mon Sep 17 00:00:00 2001
From: Jeremy Compostella <jeremy.compostella@intel.com>
Date: Tue, 12 Nov 2024 10:32:43 -0800
Subject: [PATCH 0337/3886] soc/intel/pantherlake: Bind SoC config VR settings
 to respective UPD

This commit binds the cep_enable, enable_fast_vmode and
fast_vmode_i_trip voltage regulator SoC settings to the CepEnable,
EnableFastVmode and IccLimit UPDs respectively.

BUG=b:357011633
TEST=CepEnable, EnableFastVmode and IccLimit are set accordingly

Change-Id: Ie72e4725cb97b4af7843a43eeaedd687d28b6752
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85131
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Pranava Y N <pranavayn@google.com>
---
 src/soc/intel/pantherlake/romstage/fsp_params.c | 11 +++++++++--
 1 file changed, 9 insertions(+), 2 deletions(-)

diff --git a/src/soc/intel/pantherlake/romstage/fsp_params.c b/src/soc/intel/pantherlake/romstage/fsp_params.c
index 93c8777d82..b5fc93bc66 100644
--- a/src/soc/intel/pantherlake/romstage/fsp_params.c
+++ b/src/soc/intel/pantherlake/romstage/fsp_params.c
@@ -285,8 +285,15 @@ static void fill_fspm_thermal_params(FSP_M_CONFIG *m_cfg,
 static void fill_fspm_vr_config_params(FSP_M_CONFIG *m_cfg,
 				       const struct soc_intel_pantherlake_config *config)
 {
-	for (size_t i = 0; i < ARRAY_SIZE(m_cfg->EnableFastVmode); i++)
-		m_cfg->EnableFastVmode[i] = 0;
+	for (size_t i = 0; i < ARRAY_SIZE(config->enable_fast_vmode); i++) {
+		if (config->cep_enable[i]) {
+			m_cfg->CepEnable[i] = config->cep_enable[i];
+			if (config->enable_fast_vmode[i]) {
+				m_cfg->EnableFastVmode[i] = config->enable_fast_vmode[i];
+				m_cfg->IccLimit[i] = config->fast_vmode_i_trip[i];
+			}
+		}
+	}
 }
 
 #if CONFIG(PLATFORM_HAS_EARLY_LOW_BATTERY_INDICATOR)

From 97bf77e52eb0b16b6149c6676b992dad127c0872 Mon Sep 17 00:00:00 2001
From: Patrick Rudolph <patrick.rudolph@9elements.com>
Date: Sun, 23 Feb 2025 15:34:17 +0100
Subject: [PATCH 0338/3886] soc/amd/common/block/lpc: Limit ROM2 to 16MiB

Don't map more than 16MiB in ROM2 decode window when the SPI ROM
size is bigger than 16MiB.

TEST: amd/birman+ still boots with bigger SPI flash sizes.

Change-Id: Ie811f6a38363f2e900611b3f3f407a94d8137c89
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86582
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/soc/amd/common/block/lpc/lpc_util.c | 8 +++++---
 1 file changed, 5 insertions(+), 3 deletions(-)

diff --git a/src/soc/amd/common/block/lpc/lpc_util.c b/src/soc/amd/common/block/lpc/lpc_util.c
index 309825a841..4097e6f734 100644
--- a/src/soc/amd/common/block/lpc/lpc_util.c
+++ b/src/soc/amd/common/block/lpc/lpc_util.c
@@ -239,7 +239,7 @@ void lpc_tpm_decode_spi(void)
 }
 
 /*
- * Enable 4MB (LPC) ROM access at 0xFFC00000 - 0xFFFFFFFF.
+ * Enable up to 16MB (LPC) ROM access at 0xFF000000 - 0xFFFFFFFF.
  *
  * Hardware should enable LPC ROM by pin straps. This function does not
  * handle the theoretically possible PCI ROM, FWH, or SPI ROM configurations.
@@ -276,9 +276,11 @@ void lpc_enable_rom(void)
 	 * 0xfff0(0000): 1MB
 	 * 0xffe0(0000): 2MB
 	 * 0xffc0(0000): 4MB
+	 * 0xff00(0000): 16MB
+	 *
 	 */
-	pci_write_config16(_LPCB_DEV, ROM_ADDRESS_RANGE2_START, 0x10000
-					- (CONFIG_COREBOOT_ROMSIZE_KB >> 6));
+	pci_write_config16(_LPCB_DEV, ROM_ADDRESS_RANGE2_START,
+			   0x10000 - (MIN(CONFIG_COREBOOT_ROMSIZE_KB, 16384) >> 6));
 
 	/* Enable LPC ROM range end at 0xffff(ffff). */
 	pci_write_config16(_LPCB_DEV, ROM_ADDRESS_RANGE2_END, 0xffff);

From ae532fe6414a2de079e48d1b83047819241d5e36 Mon Sep 17 00:00:00 2001
From: Masa Nakura <nakura@google.com>
Date: Thu, 27 Feb 2025 10:02:06 +0000
Subject: [PATCH 0339/3886] payloads/libpayload: Add fast data types to types.h

libpayload stdint.h only supports typedefs for datatypes of exact
bits. This makes libpayload less flexible to support libraries
that reference different data types.

Add fast data types in types.h.

BUG=b:386913035

Change-Id: Ie9197866ae9b6c27d3f26c11d8409ecb90321c74
Signed-off-by: Masa Nakura <nakura@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86632
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Hsuan-ting Chen <roccochen@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 payloads/libpayload/include/arm/arch/types.h   | 8 ++++++++
 payloads/libpayload/include/arm64/arch/types.h | 8 ++++++++
 payloads/libpayload/include/mock/arch/types.h  | 8 ++++++++
 payloads/libpayload/include/x86/arch/types.h   | 8 ++++++++
 4 files changed, 32 insertions(+)

diff --git a/payloads/libpayload/include/arm/arch/types.h b/payloads/libpayload/include/arm/arch/types.h
index 3f2eeaa466..43ba84ebf8 100644
--- a/payloads/libpayload/include/arm/arch/types.h
+++ b/payloads/libpayload/include/arm/arch/types.h
@@ -30,23 +30,31 @@
 #define _ARCH_TYPES_H
 
 typedef unsigned char uint8_t;
+typedef unsigned char uint_fast8_t;
 typedef unsigned char u8;
 typedef signed char int8_t;
+typedef signed char int_fast8_t;
 typedef signed char s8;
 
 typedef unsigned short uint16_t;
 typedef unsigned short u16;
+typedef unsigned short uint_fast16_t;
 typedef signed short int16_t;
+typedef signed short int_fast16_t;
 typedef signed short s16;
 
 typedef unsigned int uint32_t;
+typedef unsigned int uint_fast32_t;
 typedef unsigned int u32;
 typedef signed int int32_t;
+typedef signed int int_fast32_t;
 typedef signed int s32;
 
 typedef unsigned long long uint64_t;
+typedef unsigned long long uint_fast64_t;
 typedef unsigned long long u64;
 typedef signed long long int64_t;
+typedef signed long long int_fast64_t;
 typedef signed long long s64;
 
 typedef long time_t;
diff --git a/payloads/libpayload/include/arm64/arch/types.h b/payloads/libpayload/include/arm64/arch/types.h
index 3f2eeaa466..43ba84ebf8 100644
--- a/payloads/libpayload/include/arm64/arch/types.h
+++ b/payloads/libpayload/include/arm64/arch/types.h
@@ -30,23 +30,31 @@
 #define _ARCH_TYPES_H
 
 typedef unsigned char uint8_t;
+typedef unsigned char uint_fast8_t;
 typedef unsigned char u8;
 typedef signed char int8_t;
+typedef signed char int_fast8_t;
 typedef signed char s8;
 
 typedef unsigned short uint16_t;
 typedef unsigned short u16;
+typedef unsigned short uint_fast16_t;
 typedef signed short int16_t;
+typedef signed short int_fast16_t;
 typedef signed short s16;
 
 typedef unsigned int uint32_t;
+typedef unsigned int uint_fast32_t;
 typedef unsigned int u32;
 typedef signed int int32_t;
+typedef signed int int_fast32_t;
 typedef signed int s32;
 
 typedef unsigned long long uint64_t;
+typedef unsigned long long uint_fast64_t;
 typedef unsigned long long u64;
 typedef signed long long int64_t;
+typedef signed long long int_fast64_t;
 typedef signed long long s64;
 
 typedef long time_t;
diff --git a/payloads/libpayload/include/mock/arch/types.h b/payloads/libpayload/include/mock/arch/types.h
index 8f090caa9b..63b0e866bf 100644
--- a/payloads/libpayload/include/mock/arch/types.h
+++ b/payloads/libpayload/include/mock/arch/types.h
@@ -4,23 +4,31 @@
 #define _ARCH_TYPES_H
 
 typedef unsigned char uint8_t;
+typedef unsigned char uint_fast8_t;
 typedef unsigned char u8;
 typedef signed char int8_t;
+typedef signed char int_fast8_t;
 typedef signed char s8;
 
 typedef unsigned short uint16_t;
 typedef unsigned short u16;
+typedef unsigned short uint_fast16_t;
 typedef signed short int16_t;
+typedef signed short int_fast16_t;
 typedef signed short s16;
 
 typedef unsigned int uint32_t;
+typedef unsigned int uint_fast32_t;
 typedef unsigned int u32;
 typedef signed int int32_t;
+typedef signed int int_fast32_t;
 typedef signed int s32;
 
 typedef unsigned long long uint64_t;
+typedef unsigned long long uint_fast64_t;
 typedef unsigned long long u64;
 typedef signed long long int64_t;
+typedef signed long long int_fast64_t;
 typedef signed long long s64;
 
 typedef long time_t;
diff --git a/payloads/libpayload/include/x86/arch/types.h b/payloads/libpayload/include/x86/arch/types.h
index 3f2eeaa466..43ba84ebf8 100644
--- a/payloads/libpayload/include/x86/arch/types.h
+++ b/payloads/libpayload/include/x86/arch/types.h
@@ -30,23 +30,31 @@
 #define _ARCH_TYPES_H
 
 typedef unsigned char uint8_t;
+typedef unsigned char uint_fast8_t;
 typedef unsigned char u8;
 typedef signed char int8_t;
+typedef signed char int_fast8_t;
 typedef signed char s8;
 
 typedef unsigned short uint16_t;
 typedef unsigned short u16;
+typedef unsigned short uint_fast16_t;
 typedef signed short int16_t;
+typedef signed short int_fast16_t;
 typedef signed short s16;
 
 typedef unsigned int uint32_t;
+typedef unsigned int uint_fast32_t;
 typedef unsigned int u32;
 typedef signed int int32_t;
+typedef signed int int_fast32_t;
 typedef signed int s32;
 
 typedef unsigned long long uint64_t;
+typedef unsigned long long uint_fast64_t;
 typedef unsigned long long u64;
 typedef signed long long int64_t;
+typedef signed long long int_fast64_t;
 typedef signed long long s64;
 
 typedef long time_t;

From e30d99f99445769c39d2b94fe882a1cf6fa2b934 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Micha=C5=82=20Kope=C4=87?= <michal.kopec@3mdeb.com>
Date: Mon, 3 Mar 2025 16:07:40 +0100
Subject: [PATCH 0340/3886] mb/novacustom/mtl-h/devicetree.cb: Re-enable
 c-state auto-demotion
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

It was disabled while debugging S0ix issues during development.
Re-enable it now that S0ix is functional.

Change-Id: Ieab5229474ef93e96908b70e5986949b406fc0fa
Signed-off-by: Michał Kopeć <michal.kopec@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86693
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/novacustom/mtl-h/devicetree.cb | 4 ----
 1 file changed, 4 deletions(-)

diff --git a/src/mainboard/novacustom/mtl-h/devicetree.cb b/src/mainboard/novacustom/mtl-h/devicetree.cb
index 663d6940dc..6eeed45d0f 100644
--- a/src/mainboard/novacustom/mtl-h/devicetree.cb
+++ b/src/mainboard/novacustom/mtl-h/devicetree.cb
@@ -18,10 +18,6 @@ chip soc/intel/meteorlake
 	# SaGv configuration
 	register "sagv" = "SAGV_ENABLED"
 
-	# Disable C1 and Package C-state auto-demotion
-	register "disable_c1_state_auto_demotion" = "1"
-	register "disable_package_c_state_demotion" = "1"
-
 	# Enable Energy Reporting
 	register "pch_pm_energy_report_enable" = "1"
 

From 59aa4cab1eeea7cb3d805804e577c98dea4eae61 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Micha=C5=82=20Kope=C4=87?= <michal.kopec@3mdeb.com>
Date: Mon, 3 Mar 2025 17:02:45 +0100
Subject: [PATCH 0341/3886] ec/dasharo/ec: Gate options behind EC_DASHARO_EC
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

In CB:86109 it was reported that some options incorrectly don't depend
on EC_DASHARO_EC. Remove `depends on` from all options and instead put
everything behind an `if EC_DASHARO_EC` to ensure options don't cause
issues with boards not using Dasharo EC.

Change-Id: If6303bf7f155749bfcf9145fb93b018247350009
Signed-off-by: Michał Kopeć <michal.kopec@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86698
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/ec/dasharo/ec/Kconfig | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/src/ec/dasharo/ec/Kconfig b/src/ec/dasharo/ec/Kconfig
index a0691046ff..87c514e459 100644
--- a/src/ec/dasharo/ec/Kconfig
+++ b/src/ec/dasharo/ec/Kconfig
@@ -6,18 +6,17 @@ config EC_DASHARO_EC
 	help
 	  Dasharo EC
 
+if EC_DASHARO_EC
+
 config EC_DASHARO_EC_BAT_THRESHOLDS
-	depends on EC_DASHARO_EC
 	bool
 	default y
 
 config EC_DASHARO_EC_DGPU
-	depends on EC_DASHARO_EC
 	bool
 	default n
 
 config EC_DASHARO_EC_UPDATE
-	depends on EC_DASHARO_EC
 	bool "Update the embedded controller firmware"
 	default n
 
@@ -27,6 +26,7 @@ config EC_DASHARO_EC_UPDATE_FILE
 	default "ec.rom"
 
 config EC_DASHARO_EC_FLASH_SIZE
-	depends on EC_DASHARO_EC
 	hex
 	default 0x20000
+
+endif # EC_DASHARO_EC

From 365947827a9ed935f395675349ea2457c6381e17 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Micha=C5=82=20Kope=C4=87?= <michal.kopec@3mdeb.com>
Date: Mon, 3 Mar 2025 16:16:06 +0100
Subject: [PATCH 0342/3886] mb/novacustom/mtl-h/devicetree.cb: Enable
 pch_hda_audio_link_hda_enable
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Now that pch_hda_audio_link_hda_enable is hooked up in soc code, enable
it in devicetree to enable the HDA audio link.

Change-Id: I3f902d9b994cb0aac75cda69476500ec7c47b763
Signed-off-by: Michał Kopeć <michal.kopec@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86696
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/novacustom/mtl-h/devicetree.cb | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/mainboard/novacustom/mtl-h/devicetree.cb b/src/mainboard/novacustom/mtl-h/devicetree.cb
index 6eeed45d0f..22bf4068aa 100644
--- a/src/mainboard/novacustom/mtl-h/devicetree.cb
+++ b/src/mainboard/novacustom/mtl-h/devicetree.cb
@@ -297,7 +297,7 @@ chip soc/intel/meteorlake
 		end
 		device ref hda on
 			subsystemid 0x1558 0xa763
-			#register "pch_hda_audio_link_hda_enable" = "1"
+			register "pch_hda_audio_link_hda_enable" = "1"
 			register "pch_hda_sdi_enable[0]" = "1"
 			register "pch_hda_dsp_enable" = "1"
 			register "pch_hda_idisp_codec_enable" = "1"

From ba92b664540f6078eaa28e6f7dc98d7783937ae0 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Micha=C5=82=20=C5=BBygowski?= <michal.zygowski@3mdeb.com>
Date: Thu, 6 Mar 2025 12:48:02 +0100
Subject: [PATCH 0343/3886] soc/intel/common/block/graphics: Add missing TWL GT
 SKUs
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

IDs taken from ADL-N and TWL EDS Vol 1 Rev 2.5 doc #645548.

Change-Id: I53c41e17324cbb19c2150d986c538a11eb1140af
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86750
Reviewed-by: Michał Kopeć <michal.kopec@3mdeb.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
---
 src/include/device/pci_ids.h                        | 2 ++
 src/soc/intel/alderlake/bootblock/report_platform.c | 2 ++
 src/soc/intel/common/block/graphics/graphics.c      | 2 ++
 3 files changed, 6 insertions(+)

diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h
index d17dca4f34..7d695b21b7 100644
--- a/src/include/device/pci_ids.h
+++ b/src/include/device/pci_ids.h
@@ -4276,6 +4276,8 @@
 #define PCI_DID_INTEL_ADL_N_GT1				0x46D0
 #define PCI_DID_INTEL_ADL_N_GT2				0x46D1
 #define PCI_DID_INTEL_ADL_N_GT3				0x46D2
+#define PCI_DID_INTEL_ADL_N_GT4				0x46D3
+#define PCI_DID_INTEL_ADL_N_GT5				0x46D4
 #define PCI_DID_INTEL_MTL_M_GT2				0x7d40
 #define PCI_DID_INTEL_MTL_P_GT2_1			0x7d45
 #define PCI_DID_INTEL_MTL_P_GT2_2			0x7d50
diff --git a/src/soc/intel/alderlake/bootblock/report_platform.c b/src/soc/intel/alderlake/bootblock/report_platform.c
index 57e4f522da..0c84d73644 100644
--- a/src/soc/intel/alderlake/bootblock/report_platform.c
+++ b/src/soc/intel/alderlake/bootblock/report_platform.c
@@ -219,6 +219,8 @@ static struct {
 	{ PCI_DID_INTEL_ADL_N_GT1, "Alderlake N GT1" },
 	{ PCI_DID_INTEL_ADL_N_GT2, "Alderlake N GT2" },
 	{ PCI_DID_INTEL_ADL_N_GT3, "Alderlake N GT3" },
+	{ PCI_DID_INTEL_ADL_N_GT4, "Alderlake N GT4" },
+	{ PCI_DID_INTEL_ADL_N_GT5, "Alderlake N GT5" },
 	{ PCI_DID_INTEL_ADL_S_GT1,   "Alderlake S GT1" },
 	{ PCI_DID_INTEL_ADL_S_GT1_1, "Alderlake S GT1" },
 	{ PCI_DID_INTEL_ADL_S_GT2,   "Alderlake S GT2" },
diff --git a/src/soc/intel/common/block/graphics/graphics.c b/src/soc/intel/common/block/graphics/graphics.c
index 144e8c30d6..cf3e7b1b23 100644
--- a/src/soc/intel/common/block/graphics/graphics.c
+++ b/src/soc/intel/common/block/graphics/graphics.c
@@ -459,6 +459,8 @@ static const unsigned short pci_device_ids[] = {
 	PCI_DID_INTEL_ADL_N_GT1,
 	PCI_DID_INTEL_ADL_N_GT2,
 	PCI_DID_INTEL_ADL_N_GT3,
+	PCI_DID_INTEL_ADL_N_GT4,
+	PCI_DID_INTEL_ADL_N_GT5,
 	PCI_DID_INTEL_RPL_S_GT0,
 	PCI_DID_INTEL_RPL_S_GT1_1,
 	PCI_DID_INTEL_RPL_S_GT1_2,

From c53b3efa4e403b9346cb58128f492f3529dbbbab Mon Sep 17 00:00:00 2001
From: Derek Huang <derekhuang@google.com>
Date: Tue, 4 Mar 2025 09:19:37 +0000
Subject: [PATCH 0344/3886] drivers/intel/usb4: Add parameter to explicitly
 define EC Type-C port

This patch adds the parameter which allows for custom port mapping
between CPU Type-C port and EC Type-C port to accommodate the
non-sequential mapping. Mainboard code must configure this parameter
if the CPU Type-C port to EC Type-C port mapping is not sequential.

BUG=b:399032094
TEST=build and verify TCSS port and EC port mapping

Change-Id: Id92f942e5c6b27342777b3e6fd12aff264ccec1b
Signed-off-by: Derek Huang <derekhuang@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86703
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
---
 src/drivers/intel/usb4/retimer/chip.h    | 13 +++++++++++++
 src/drivers/intel/usb4/retimer/retimer.c |  5 ++++-
 2 files changed, 17 insertions(+), 1 deletion(-)

diff --git a/src/drivers/intel/usb4/retimer/chip.h b/src/drivers/intel/usb4/retimer/chip.h
index cb01f18e2c..2b60d50a25 100644
--- a/src/drivers/intel/usb4/retimer/chip.h
+++ b/src/drivers/intel/usb4/retimer/chip.h
@@ -9,6 +9,14 @@
 
 #define DFP_NUM_MAX	2
 
+enum ec_typec_port {
+	UNDEFINED = 0,
+	EC_TYPEC_PORT_0,
+	EC_TYPEC_PORT_1,
+	EC_TYPEC_PORT_2,
+	EC_TYPEC_PORT_3
+};
+
 struct drivers_intel_usb4_retimer_config {
 	/* Downstream facing port(DFP) */
 	struct {
@@ -16,6 +24,11 @@ struct drivers_intel_usb4_retimer_config {
 		struct acpi_gpio power_gpio;
 		/* Type-C port associated with retimer */
 		DEVTREE_CONST struct device *typec_port;
+		/*
+		 * EC Type-C port associated with retimer. This parameter must be configured
+		 * correctly if the CPU Type-C port to EC port mapping is not sequential.
+		 */
+		enum ec_typec_port ec_port;
 	} dfp[DFP_NUM_MAX];
 };
 
diff --git a/src/drivers/intel/usb4/retimer/retimer.c b/src/drivers/intel/usb4/retimer/retimer.c
index 40dd4c114e..e78cd29e29 100644
--- a/src/drivers/intel/usb4/retimer/retimer.c
+++ b/src/drivers/intel/usb4/retimer/retimer.c
@@ -400,7 +400,10 @@ static void usb4_retimer_fill_ssdt(const struct device *dev)
 		usb_device = config->dfp[dfp_port].typec_port;
 		usb_port = usb_device->path.usb.port_id;
 
-		ec_port = retimer_get_index_for_typec(usb_port);
+		/* Map to the EC port number if it is explicitly defined in the device tree */
+		ec_port = (config->dfp[dfp_port].ec_port) ?
+			  config->dfp[dfp_port].ec_port - EC_TYPEC_PORT_0 :
+			  retimer_get_index_for_typec(usb_port);
 		if (ec_port == -1) {
 			printk(BIOS_ERR, "%s: No relative EC port found for TC port %d\n",
 				__func__, usb_port);

From c5db254b122981cde83f83c7ec8583a0420ed12e Mon Sep 17 00:00:00 2001
From: Derek Huang <derekhuang@google.com>
Date: Tue, 4 Mar 2025 09:33:51 +0000
Subject: [PATCH 0345/3886] drivers/intel/usb4: Move log message from SoC code
 to driver code

This patch moves the debug print which prints the mapping between CPU
Type-C port and EC Type-C port from SoC code to generic driver code.

BUG=b:399032094
TEST=Check the Type-C port and EC port mapping in coreboot log

Change-Id: Iaef5813cc825569a53feba975258f7d5fadecfab
Signed-off-by: Derek Huang <derekhuang@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86704
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
---
 src/drivers/intel/usb4/retimer/retimer.c | 1 +
 src/soc/intel/alderlake/retimer.c        | 5 +----
 src/soc/intel/meteorlake/retimer.c       | 5 +----
 src/soc/intel/pantherlake/retimer.c      | 5 +----
 src/soc/intel/tigerlake/retimer.c        | 5 +----
 5 files changed, 5 insertions(+), 16 deletions(-)

diff --git a/src/drivers/intel/usb4/retimer/retimer.c b/src/drivers/intel/usb4/retimer/retimer.c
index e78cd29e29..6c220f2b07 100644
--- a/src/drivers/intel/usb4/retimer/retimer.c
+++ b/src/drivers/intel/usb4/retimer/retimer.c
@@ -409,6 +409,7 @@ static void usb4_retimer_fill_ssdt(const struct device *dev)
 				__func__, usb_port);
 			continue;
 		}
+		printk(BIOS_INFO, "USB Type-C %d mapped to EC port %d\n", usb_port, ec_port);
 		/* DFPx */
 		snprintf(dfp, sizeof(dfp), "DFP%1d", ec_port);
 		acpigen_write_device(dfp);
diff --git a/src/soc/intel/alderlake/retimer.c b/src/soc/intel/alderlake/retimer.c
index fd047dd9f2..6f6b90b7bf 100644
--- a/src/soc/intel/alderlake/retimer.c
+++ b/src/soc/intel/alderlake/retimer.c
@@ -18,11 +18,8 @@ int retimer_get_index_for_typec(uint8_t typec_port)
 	};
 
 	for (uint8_t i = 0; i < MAX_TYPE_C_PORTS; i++) {
-		if (i == typec_port) {
-			printk(BIOS_INFO, "USB Type-C %d mapped to EC port %d\n", typec_port,
-					ec_port);
+		if (i == typec_port)
 			return ec_port;
-		}
 
 		if (is_dev_enabled(tcss_port_arr[i]))
 			ec_port++;
diff --git a/src/soc/intel/meteorlake/retimer.c b/src/soc/intel/meteorlake/retimer.c
index a559cfc5c7..d4affa8558 100644
--- a/src/soc/intel/meteorlake/retimer.c
+++ b/src/soc/intel/meteorlake/retimer.c
@@ -18,11 +18,8 @@ int retimer_get_index_for_typec(uint8_t typec_port)
 	};
 
 	for (uint8_t i = 0; i < MAX_TYPE_C_PORTS; i++) {
-		if (i == typec_port) {
-			printk(BIOS_INFO, "USB Type-C %d mapped to EC port %d\n", typec_port,
-					ec_port);
+		if (i == typec_port)
 			return ec_port;
-		}
 
 		if (is_dev_enabled(tcss_port_arr[i]))
 			ec_port++;
diff --git a/src/soc/intel/pantherlake/retimer.c b/src/soc/intel/pantherlake/retimer.c
index d55cd7de3d..329d9b2ad3 100644
--- a/src/soc/intel/pantherlake/retimer.c
+++ b/src/soc/intel/pantherlake/retimer.c
@@ -16,11 +16,8 @@ int retimer_get_index_for_typec(uint8_t typec_port)
 	};
 
 	for (int i = 0, ec_port = 0; i < MAX_TYPE_C_PORTS; i++) {
-		if (i == typec_port) {
-			printk(BIOS_INFO, "USB Type-C %d mapped to EC port %d\n", typec_port,
-					ec_port);
+		if (i == typec_port)
 			return ec_port;
-		}
 
 		if (is_dev_enabled(tcss_port_arr[i]))
 			ec_port++;
diff --git a/src/soc/intel/tigerlake/retimer.c b/src/soc/intel/tigerlake/retimer.c
index 4a2ed6a0e6..fe9c999e76 100644
--- a/src/soc/intel/tigerlake/retimer.c
+++ b/src/soc/intel/tigerlake/retimer.c
@@ -19,11 +19,8 @@ int retimer_get_index_for_typec(uint8_t typec_port)
 	};
 
 	for (uint8_t i = 0; i < MAX_TYPE_C_PORTS; i++) {
-		if (i == typec_port) {
-			printk(BIOS_ERR, "USB Type-C %d mapped to EC port %d\n", typec_port,
-					ec_port);
+		if (i == typec_port)
 			return ec_port;
-		}
 
 		if (is_dev_enabled(tcss_port_arr[i]))
 			ec_port++;

From 9b4b0eeda1c3971b34851796dd9a1ad3866dd98e Mon Sep 17 00:00:00 2001
From: Derek Huang <derekhuang@google.com>
Date: Tue, 4 Mar 2025 09:44:40 +0000
Subject: [PATCH 0346/3886] mb/google/rex/deku: Define TCSS port and EC port
 mapping

Deku design has a non-sequential mapping between CPU Type-C ports
and EC Typec-C ports. This patch maps the CPU Type-C port to the
correct EC Type-C port for the Intel re-timer driver.

BUG=b:399032094
TEST=Check the Type-C port and EC port mapping in coreboot log

deku-rev1 ~ # cbmem -c |grep "USB Type-C"
[INFO ]  USB Type-C 0 mapped to EC port 0
[INFO ]  USB Type-C 1 mapped to EC port 2
[INFO ]  USB Type-C 2 mapped to EC port 1
[INFO ]  USB Type-C 3 mapped to EC port 3

Change-Id: I80fa45a5f40d15c86087dca98bd0fb80a9121e50
Signed-off-by: Derek Huang <derekhuang@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86705
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
---
 src/mainboard/google/rex/variants/deku/overridetree.cb | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/src/mainboard/google/rex/variants/deku/overridetree.cb b/src/mainboard/google/rex/variants/deku/overridetree.cb
index 3b4dce9d6d..158f3fba6a 100644
--- a/src/mainboard/google/rex/variants/deku/overridetree.cb
+++ b/src/mainboard/google/rex/variants/deku/overridetree.cb
@@ -216,11 +216,13 @@ chip soc/intel/meteorlake
 		device ref tcss_dma0 on
 			chip drivers/intel/usb4/retimer
 				register "dfp[0].power_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B22)"
+				register "dfp[0].ec_port" = "EC_TYPEC_PORT_0"
 				use tcss_usb3_port0 as dfp[0].typec_port
 				device generic 0 on end
 			end
 			chip drivers/intel/usb4/retimer
 				register "dfp[1].power_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B22)"
+				register "dfp[1].ec_port" = "EC_TYPEC_PORT_2"
 				use tcss_usb3_port1 as dfp[1].typec_port
 				device generic 0 on end
 			end
@@ -228,11 +230,13 @@ chip soc/intel/meteorlake
 		device ref tcss_dma1 on
 			chip drivers/intel/usb4/retimer
 				register "dfp[0].power_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B22)"
+				register "dfp[0].ec_port" = "EC_TYPEC_PORT_1"
 				use tcss_usb3_port2 as dfp[0].typec_port
 				device generic 0 on end
 			end
 			chip drivers/intel/usb4/retimer
 				register "dfp[1].power_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B22)"
+				register "dfp[1].ec_port" = "EC_TYPEC_PORT_3"
 				use tcss_usb3_port3 as dfp[1].typec_port
 				device generic 0 on end
 			end

From ec83019b500963ba4ad744f32cf06c1895481082 Mon Sep 17 00:00:00 2001
From: Yuval Peress <peress@google.com>
Date: Fri, 7 Mar 2025 13:39:07 -0700
Subject: [PATCH 0347/3886] mb/google/brya/var/trulo: Update ISH firmware name

Renames ish_fw.bin to trulo_ish.bin to prevent potential conflicts with
other Nissa projects. This aligns with the naming used in the
chromeos-zephyr-ish package.

BUG=b:397821047
TEST=Flash trulo, disassemble SSDT, search for trulo_ish.bin
BRANCH=none

Change-Id: I855ecc87ddb7b69c2c2c8e4287bd9d6ec2e2e991
Signed-off-by: Yuval Peress <peress@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86769
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
---
 .../google/brya/variants/baseboard/trulo/devicetree.cb          | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/mainboard/google/brya/variants/baseboard/trulo/devicetree.cb b/src/mainboard/google/brya/variants/baseboard/trulo/devicetree.cb
index a93c6697fd..8a20256f51 100644
--- a/src/mainboard/google/brya/variants/baseboard/trulo/devicetree.cb
+++ b/src/mainboard/google/brya/variants/baseboard/trulo/devicetree.cb
@@ -91,7 +91,7 @@ chip soc/intel/alderlake
 		device ref tcss_xhci on end
 		device ref ish on
 			chip drivers/intel/ish
-				register "firmware_name" = ""ish_fw.bin""
+				register "firmware_name" = ""trulo_ish.bin""
 				register "add_acpi_dma_property" = "true"
 				device generic 0 on end
 			end

From 27f3427f4a1dfd2b9a681d9a742894c58a8db08d Mon Sep 17 00:00:00 2001
From: Jayvik Desai <jayvik@google.com>
Date: Tue, 4 Mar 2025 14:58:23 +0530
Subject: [PATCH 0348/3886] mb/google/fatcat/var/fatcat: Update GSPI0 CS pin
 for FPS

GPP_F18 is currently shared between the fingerprint sensor GSPI0-CS and
the touchpad THC1-INT.

This commit moves the FPS GSPI0-CS signal to GPP_E17, which is a GSPI-0
CS alternative option and moves the current GSPI0A-CS pin GPP_F18 to
not connected.

Schematic version dated march'25 has the rework details.

BUG=b:395147436
TEST=Build and boot google/fatcat. Able to fetch the FPS version using
`ectool --name=cros_fp version`

Change-Id: I1131962e9b6423bbf68fb92189b8910eab49645e
Signed-off-by: Jayvik Desai <jayvik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86702
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 .../google/fatcat/variants/fatcat/fw_config.c         | 11 +++++++----
 src/mainboard/google/fatcat/variants/fatcat/gpio.c    |  2 --
 2 files changed, 7 insertions(+), 6 deletions(-)

diff --git a/src/mainboard/google/fatcat/variants/fatcat/fw_config.c b/src/mainboard/google/fatcat/variants/fatcat/fw_config.c
index 9419caf709..18163bb63e 100644
--- a/src/mainboard/google/fatcat/variants/fatcat/fw_config.c
+++ b/src/mainboard/google/fatcat/variants/fatcat/fw_config.c
@@ -477,6 +477,7 @@ static const struct pad_config fp_disable_pads[] = {
 	PAD_NC(GPP_C15, NONE),
 	/* GPP_D01:     MOD_TCSS1_TYP_A_VBUS_EN */
 	PAD_CFG_GPO(GPP_D01, 1, DEEP),
+	PAD_NC(GPP_E17, NONE),
 	/* FIXME: b/390031369
 	 * use dedicated GPIO PIN for codec enable
 	 * when FPS is enabled.
@@ -495,6 +496,8 @@ static const struct pad_config fp_enable_pads[] = {
 	PAD_CFG_GPO_LOCK(GPP_C15, 1, LOCK_CONFIG),
 	/* GPP_D01:     FPS_SOC_INT_L */
 	PAD_CFG_GPI_IRQ_WAKE(GPP_D01, NONE, PWROK, LEVEL, INVERT),
+	/* GPP_E17:     GSPI0A_CS0 */
+	PAD_CFG_NF(GPP_E17, NONE, DEEP, NF5),
 	/* GPP_E19:     FPMCU_PWREN */
 	PAD_CFG_GPO(GPP_E19, 1, DEEP),
 	/* GPP_E20:     FPMCU_FW_UPDATE */
@@ -505,8 +508,8 @@ static const struct pad_config fp_enable_pads[] = {
 	PAD_CFG_NF(GPP_F15, NONE, DEEP, NF8),
 	/* GPP_F16:     GPSI0A_CLK */
 	PAD_CFG_NF(GPP_F16, NONE, DEEP, NF8),
-	/* GPP_F18:     GSPI0A_CS0 */
-	PAD_CFG_NF(GPP_F18, NONE, DEEP, NF8),
+	/* GPP_F18:     NC */
+	PAD_NC(GPP_F18, NONE),
 };
 
 static const struct pad_config pre_mem_fp_enable_pads[] = {
@@ -645,7 +648,7 @@ void fw_config_gpio_padbased_override(struct pad_config *padbased_table)
 	GPIO_PADBASED_OVERRIDE(padbased_table, peg_x4slot_wake_disable_pads);
 
 	if (fw_config_probe(FW_CONFIG(FP, FP_PRESENT)))
-		GPIO_CONFIGURE_PADS(fp_enable_pads);
+		GPIO_PADBASED_OVERRIDE(padbased_table, fp_enable_pads);
 	else
-		GPIO_CONFIGURE_PADS(fp_disable_pads);
+		GPIO_PADBASED_OVERRIDE(padbased_table, fp_disable_pads);
 }
diff --git a/src/mainboard/google/fatcat/variants/fatcat/gpio.c b/src/mainboard/google/fatcat/variants/fatcat/gpio.c
index 75c674c70c..b0e08f0859 100644
--- a/src/mainboard/google/fatcat/variants/fatcat/gpio.c
+++ b/src/mainboard/google/fatcat/variants/fatcat/gpio.c
@@ -222,8 +222,6 @@ static const struct pad_config gpio_table[] = {
 	/* GPP_E16:     THC0_SPI1_RST_N_TCH_PNL1 */
 	/* THC NOTE: use GPO instead of GPO for THC0 Rst */
 	PAD_CFG_GPO(GPP_E16, 1, DEEP),
-	/* GPP_E17:     THC0_SPI1_CS0_N_TCH_PNL1 */
-	PAD_CFG_NF(GPP_E17, NONE, DEEP, NF3),
 	/* GPP_E18:     THC0_SPI1_INT_N_TCH_PNL1 */
 	PAD_CFG_NF(GPP_E18, NONE, DEEP, NF3),
 	/* GPP_E21:     I2C_PMC_PD_INT_N */

From 637c35cd6743a072b0ff6184256d7781b7b37465 Mon Sep 17 00:00:00 2001
From: Ana Carolina Cabral <ana.cpmelo95@gmail.com>
Date: Thu, 16 Jan 2025 12:19:44 -0300
Subject: [PATCH 0349/3886] mb/amd/birman_plus/ec: Rectify ECRAM register bits

Rectify wrong EC module RAM register bits
based on PI source code 1.0.0.1b

Change-Id: I1a13d99a55a4aa02a5cb0e67ffa4ed555f91a471
Signed-off-by: Ana Carolina Cabral <ana.cpmelo95@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86084
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
---
 src/mainboard/amd/birman_plus/ec.c | 118 ++++++++++++++++++++---------
 1 file changed, 81 insertions(+), 37 deletions(-)

diff --git a/src/mainboard/amd/birman_plus/ec.c b/src/mainboard/amd/birman_plus/ec.c
index 168da3e829..62a935e53f 100644
--- a/src/mainboard/amd/birman_plus/ec.c
+++ b/src/mainboard/amd/birman_plus/ec.c
@@ -8,6 +8,9 @@
 #define BIRMAN_EC_CMD	0x666
 #define BIRMAN_EC_DATA	0x662
 
+#define EC_GPIO_0_ADDR		0xA0
+#define EC0_EVAL_PRSNTn		BIT(2)
+
 #define EC_GPIO_1_ADDR		0xA1
 #define   EC1_EVAL_PWREN	BIT(1)
 
@@ -23,22 +26,25 @@
 #define   EC3_LOM_RST_AUX	BIT(1)
 #define   EC3_EVAL_RST_AUX	BIT(0)
 
+#define EC_GPIO_6_ADDR		0xA6
+#define   EC6_TPNL_BUF_EN	BIT(1)
+#define   EC6_TPAD_BUF_EN	BIT(0)
+
 #define EC_GPIO_7_ADDR		0xA7
 #define   EC7_WWAN_PWR_OFF_N	BIT(7)
 #define   EC7_BT_RADIO_DIS	BIT(2)
-#define   EC7_WL_RADIO_DIS	BIT(0)
+#define   EC7_WL_RADIO_EN	BIT(0)
 
 #define EC_GPIO_8_ADDR		0xA8
 #define   EC8_ADAPTER_OFF	BIT(5)
 #define   EC8_EVAL_SMBUS1_N_SW	BIT(3)
 #define   EC8_MP2_SEL		BIT(2)
-#define   EC8_DT_N_SSD1_SW	BIT(1)
 
 #define EC_GPIO_9_ADDR		0xA9
 #define   EC9_CAM0_PWR_EN	BIT(7)
 #define   EC9_CAM1_PWR_EN	BIT(6)
-#define   EC9_WWAN_RST		BIT(5)
-#define   EC9_DT_PWREN		BIT(2)
+#define   EC9_WWAN_RST_N	BIT(5)
+#define   EC9_SSD1_PWREN	BIT(2)
 #define   EC9_TPM_PWR_EN	BIT(1)
 #define   EC9_TPM_S0I3_N	BIT(0)
 
@@ -52,15 +58,9 @@
 #define   ECA_SMBUS1_EN		BIT(1)
 #define   ECA_SMBUS0_EN		BIT(0)
 
-#define EC_GPIO_C_ADDR		0xAC
-#define   ECC_TPNL_BUF_EN	BIT(6)
-#define   ECC_TPAD_BUF_EN	BIT(5)
-#define   ECC_NFC_BUF_EN	BIT(4)
-
 #define EC_GPIO_D_ADDR		0xAD
 #define   ECD_TPNL_PWR_EN	BIT(7)
 #define   ECD_TPNL_EN		BIT(6)
-#define   ECD_SSD1_PWR_EN	BIT(5)
 #define   ECD_FPR_PWR_EN	BIT(3)
 #define   ECD_FPR_OFF_N		BIT(2)
 #define   ECD_FPR_LOCK_N	BIT(1)
@@ -73,19 +73,18 @@
 #define   ECE_WLAN_PWR_EN	BIT(4)
 #define   ECE_WWAN_PWR_EN	BIT(3)
 #define   ECE_CAM_PWR_EN	BIT(2)
-#define   ECE_FPR_N_GBE_SEL	BIT(1)
-#define   ECE_BT_N_TPNL_SEL	BIT(0)
+#define   ECE_FPR_N_GBE_SEL	BIT(1) //USB5_MUX_FPR#_GBE_SEL
+#define   ECE_BT_N_TPNL_SEL	BIT(0) //USB6_MUX_BT#_TPNL_SEL
 
 #define EC_GPIO_F_ADDR		0xAF
-#define   ECF_CAM_FW_WP_N	BIT(7)
-#define   ECF_I2C_MUX_OE_N	BIT(4)
-#define   ECF_WLAN0_N_WWAN1_SW	BIT(1)
-#define   ECF_WWAN0_N_WLAN1_SW	BIT(0)
+#define   ECF_SD_MAIN_PWR_EN	BIT(6)
+#define   ECF_SDE_N_WLAN1_SW	BIT(1)
+#define   ECF_GBE_N_WWAN1_SW	BIT(0)
 
 #define EC_GPIO_G_ADDR	0xB0
 #define   ECG_IR_LED_PWR_EN	BIT(7)
 #define   ECG_U0_WLAN_HDR_SEL	BIT(6)
-#define   ECG_DT_SSD1_MUX_OFF	BIT(5)
+#define   ECG_NFC_BUF_EN	BIT(5)
 #define   ECG_WLAN_WWAN_MUX_OFF	BIT(4)
 
 static void configure_ec_gpio(void)
@@ -105,7 +104,10 @@ static void configure_ec_gpio(void)
 	if (CONFIG(ENABLE_EVAL_CARD)) {
 		tmp |= EC2_EVAL_SLOT_PWREN;
 		if (CONFIG(ENABLE_EVAL_19V)) {
-			tmp |= EC2_EVAL_19V_EN;
+			uint8_t eval_present = !(ec_read(EC_GPIO_0_ADDR) & EC0_EVAL_PRSNTn);
+			if (eval_present) {
+				tmp |= EC2_EVAL_19V_EN;
+			}
 		} else {
 			tmp &= ~EC2_EVAL_19V_EN;
 		}
@@ -122,72 +124,114 @@ static void configure_ec_gpio(void)
 	printk(BIOS_SPEW, "Write reg [0x%02x] = 0x%02x\n", EC_GPIO_3_ADDR, tmp);
 	ec_write(EC_GPIO_3_ADDR, tmp);
 
+	tmp = ec_read(EC_GPIO_6_ADDR);
+	tmp |= EC6_TPNL_BUF_EN | EC6_TPAD_BUF_EN;
+	printk(BIOS_SPEW, "Write reg [0x%02x] = 0x%02x\n", EC_GPIO_6_ADDR, tmp);
+	ec_write(EC_GPIO_6_ADDR, tmp);
+
 	tmp = ec_read(EC_GPIO_7_ADDR);
-	tmp &= ~EC7_BT_RADIO_DIS;
-	tmp &= ~EC7_WL_RADIO_DIS;
 	tmp |= EC7_WWAN_PWR_OFF_N;
+	tmp &= ~(EC7_BT_RADIO_DIS | EC7_BT_RADIO_DIS);
 	printk(BIOS_SPEW, "Write reg [0x%02x] = 0x%02x\n", EC_GPIO_7_ADDR, tmp);
 	ec_write(EC_GPIO_7_ADDR, tmp);
 
 	tmp = ec_read(EC_GPIO_8_ADDR);
-	tmp |= EC8_DT_N_SSD1_SW;
+	tmp |= EC8_MP2_SEL;
 	printk(BIOS_SPEW, "Write reg [0x%02x] = 0x%02x\n", EC_GPIO_8_ADDR, tmp);
 	ec_write(EC_GPIO_8_ADDR, tmp);
 
 	tmp = ec_read(EC_GPIO_9_ADDR);
-	tmp |= EC9_CAM0_PWR_EN | EC9_CAM1_PWR_EN | EC9_WWAN_RST | EC9_TPM_PWR_EN | EC9_DT_PWREN;
+	tmp |= EC9_CAM0_PWR_EN | EC9_CAM1_PWR_EN | EC9_TPM_PWR_EN;
+
+	if (CONFIG(DISABLE_WWAN_GBE_BIRMANPLUS)) {
+		tmp &= ~EC9_WWAN_RST_N;
+	} else {
+		tmp |= EC9_WWAN_RST_N;
+	}
+
+	if (CONFIG(ENABLE_SSD1_BIRMANPLUS)) {
+		tmp |= EC9_SSD1_PWREN;
+	} else {
+		tmp &= ~EC9_SSD1_PWREN;
+	}
+
 	printk(BIOS_SPEW, "Write reg [0x%02x] = 0x%02x\n", EC_GPIO_9_ADDR, tmp);
 	ec_write(EC_GPIO_9_ADDR, tmp);
 
+	tmp = ec_read(EC_GPIO_A_ADDR);
 	tmp = ECA_MUX1_S0 | ECA_SMBUS1_EN | ECA_SMBUS0_EN;
+	// Touch Panel under I2C0 bus (default)
+	tmp &= ~(ECA_MUX0_S1 | ECA_MUX0_S0);
+	// Touch Pad Under I2C1 bus (default)
+	tmp |= ECA_MUX1_S0;
+	tmp &= ~ECA_MUX1_S1;
+	// NFC under I2C0 bus (default)
+	tmp &= ~(ECA_MUX2_S0 | ECA_MUX2_S1);
 	printk(BIOS_SPEW, "Write reg [0x%02x] = 0x%02x\n", EC_GPIO_A_ADDR, tmp);
 	ec_write(EC_GPIO_A_ADDR, tmp);
 
-	tmp = ec_read(EC_GPIO_C_ADDR);
-	tmp |= ECC_TPNL_BUF_EN | ECC_TPAD_BUF_EN | ECC_NFC_BUF_EN;
-	printk(BIOS_SPEW, "Write reg [0x%02x] = 0x%02x\n", EC_GPIO_C_ADDR, tmp);
-	ec_write(EC_GPIO_C_ADDR, tmp);
-
 	tmp = ec_read(EC_GPIO_D_ADDR);
-	tmp |= ECD_TPNL_PWR_EN | ECD_TPNL_EN | ECD_TPAD_DISABLE_N | ECD_SSD1_PWR_EN;
+	tmp |= ECD_TPNL_PWR_EN | ECD_TPNL_EN | ECD_TPAD_DISABLE_N;
 	printk(BIOS_SPEW, "Write reg [0x%02x] = 0x%02x\n", EC_GPIO_D_ADDR, tmp);
 	ec_write(EC_GPIO_D_ADDR, tmp);
 
 	tmp = ec_read(EC_GPIO_E_ADDR);
-	tmp |= ECE_LOM_PWR_EN | ECE_SSD0_PWR_EN | ECE_SD_PWR_EN;
-	tmp |= ECE_CAM_PWR_EN | ECE_FPR_N_GBE_SEL;
+	tmp |= ECE_SSD0_PWR_EN | ECE_CAM_PWR_EN | ECE_FPR_N_GBE_SEL;
 	tmp &= ~ECE_BT_N_TPNL_SEL;
+
+	if (CONFIG(ENABLE_SDCARD_BIRMANPLUS)) {
+		tmp |= ECE_SD_PWR_EN;
+	} else {
+		tmp &= ~ECE_SD_PWR_EN;
+	}
+
+	if (CONFIG(ENABLE_GBE_BIRMANPLUS)) {
+		tmp |= ECE_LOM_PWR_EN;
+	} else {
+		tmp &= ~ECE_LOM_PWR_EN;
+	}
+
 	if (CONFIG(DISABLE_WWAN_GBE_BIRMANPLUS)) {	// no WWAN, turn off WWAN power
 		tmp &= ~ECE_WWAN_PWR_EN;
 	} else {
 		tmp |= ECE_WWAN_PWR_EN;
 	}
+
 	if (CONFIG(DISABLE_WLAN_SD_BIRMANPLUS)) {	// no WLAN, turn off WLAN power
 		tmp &= ~ECE_WLAN_PWR_EN;
 	} else {
 		tmp |= ECE_WLAN_PWR_EN;
 	}
+
 	printk(BIOS_SPEW, "Write reg [0x%02x] = 0x%02x\n", EC_GPIO_E_ADDR, tmp);
 	ec_write(EC_GPIO_E_ADDR, tmp);
 
 	tmp = ec_read(EC_GPIO_F_ADDR);
+
+	if (CONFIG(ENABLE_SDCARD_BIRMANPLUS)) {
+		tmp |= ECF_SD_MAIN_PWR_EN;
+	} else {
+		tmp &= ~ECF_SD_MAIN_PWR_EN;
+	}
+
 	if (CONFIG(ENABLE_WLAN02_BIRMANPLUS)) {
-		tmp |= ECF_WWAN0_N_WLAN1_SW;
+		tmp &= ~ECF_GBE_N_WWAN1_SW;  // Enable x2 WLAN, SD disable
 	} else {
-		tmp &= ~ECF_WWAN0_N_WLAN1_SW;
+		tmp |= ECF_GBE_N_WWAN1_SW;  // Default  GBE x1 WWAN x1
 	}
+
 	if (CONFIG(ENABLE_WWAN02_BIRMANPLUS)) {
-		tmp |= ECF_WLAN0_N_WWAN1_SW;
+		tmp &= ~ECF_SDE_N_WLAN1_SW;  // Enable x2 WWAN, GBE disable
 	} else {
-		tmp &= ~ECF_WLAN0_N_WWAN1_SW;
+		tmp |= ECF_SDE_N_WLAN1_SW; // Default SDCard x1 WLAN x1
 	}
+
 	printk(BIOS_SPEW, "Write reg [0x%02x] = 0x%02x\n", EC_GPIO_F_ADDR, tmp);
 	ec_write(EC_GPIO_F_ADDR, tmp);
 
 	tmp = ec_read(EC_GPIO_G_ADDR);
-	tmp &= ~ECG_DT_SSD1_MUX_OFF;
-	tmp &= ~ECG_WLAN_WWAN_MUX_OFF;
-	tmp |= ECG_IR_LED_PWR_EN | ECG_U0_WLAN_HDR_SEL;
+	tmp &= ~ECG_WLAN_WWAN_MUX_OFF; // Keep low to avoid GPP13, GPP14 not work.
+	tmp |= ECG_IR_LED_PWR_EN | ECG_U0_WLAN_HDR_SEL | ECG_NFC_BUF_EN;
 	printk(BIOS_SPEW, "Write reg [0x%02x] = 0x%02x\n", EC_GPIO_G_ADDR, tmp);
 	ec_write(EC_GPIO_G_ADDR, tmp);
 }

From bd453f2b6f6d3cbd12c779250fc55e776984e1c1 Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Wed, 5 Mar 2025 15:35:28 +0000
Subject: [PATCH 0350/3886] mb/starlabs/starlite_adl: Add generic Graphics
 driver config

This provides entries in the SSDT for all display devices, which
allows the kernel to enumerate them.

Change-Id: Ie3fe24be948b256b47eb8d48fd8a84d6daa2702f
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86742
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/starlabs/starlite_adl/Kconfig   |  1 +
 .../starlite_adl/variants/mk_v/devicetree.cb  | 76 +++++++++++++------
 2 files changed, 52 insertions(+), 25 deletions(-)

diff --git a/src/mainboard/starlabs/starlite_adl/Kconfig b/src/mainboard/starlabs/starlite_adl/Kconfig
index 51b762b9e9..6afa6238e7 100644
--- a/src/mainboard/starlabs/starlite_adl/Kconfig
+++ b/src/mainboard/starlabs/starlite_adl/Kconfig
@@ -3,6 +3,7 @@ config BOARD_STARLABS_STARLITE_SERIES
 	select BOARD_ROMSIZE_KB_16384
 	select CRB_TPM
 	select DRIVERS_EFI_VARIABLE_STORE
+	select DRIVERS_GFX_GENERIC
 	select DRIVERS_I2C_HID
 	select DRIVERS_INTEL_PMC
 	select DRIVERS_OPTION_CFR
diff --git a/src/mainboard/starlabs/starlite_adl/variants/mk_v/devicetree.cb b/src/mainboard/starlabs/starlite_adl/variants/mk_v/devicetree.cb
index 38fe6d07a4..86324a8385 100644
--- a/src/mainboard/starlabs/starlite_adl/variants/mk_v/devicetree.cb
+++ b/src/mainboard/starlabs/starlite_adl/variants/mk_v/devicetree.cb
@@ -37,7 +37,28 @@ chip soc/intel/alderlake
 
 	device domain 0 on
 		device ref igpu		on
-			register "gfx"					= "GMA_DEFAULT_PANEL(0)"
+			chip drivers/gfx/generic
+				register "device_count"		= "6"
+				# [DDIA] eDP
+				register "device[0].name"	= ""LCD0""
+				register "device[0].type"	= "panel"
+				# [DDIB] HDMI
+				register "device[1].name"	= ""DD01""
+				# [TCP0] Type-C
+				register "device[2].name"	= ""DD02""
+				register "device[2].use_pld"	= "true"
+				register "device[2].pld"	= "ACPI_PLD_TYPE_C(RIGHT, CENTER, ACPI_PLD_GROUP(0, 0))"
+				# [TCP1] Type-C
+				register "device[3].name"	= ""DD03""
+				register "device[3].use_pld"	= "true"
+				register "device[3].pld"	= "ACPI_PLD_TYPE_C(RIGHT, CENTER, ACPI_PLD_GROUP(0, 1))"
+				# [TCP2] N/A
+				register "device[4].name"	= ""DD04""
+				# [TCP3] N/A
+				register "device[5].name"	= ""DD05""
+				device generic 0 on end
+			end
+
 			register "ddi_portA_config"			= "1"
 			register "ddi_ports_config" = "{
 				[DDI_PORT_A]				= DDI_ENABLE_HPD,
@@ -68,48 +89,53 @@ chip soc/intel/alderlake
 			chip drivers/usb/acpi
 				device ref xhci_root_hub on
 					chip drivers/usb/acpi
-						register "desc"		= ""Bottom USB Type-C""
-						register "type"		= "UPC_TYPE_C_USB2_SS_SWITCH"
-						register "group"	= "ACPI_PLD_GROUP(0, 0)"
+						register "desc"			= ""Bottom USB Type-C""
+						register "type"			= "UPC_TYPE_C_USB2_SS_SWITCH"
+						register "use_custom_pld"	= "true"
+						register "custom_pld"		= "ACPI_PLD_TYPE_C(RIGHT, CENTER, ACPI_PLD_GROUP(0, 0))"
+
 						device ref usb2_port1 on end
 					end
 					chip drivers/usb/acpi
-						register "desc"		= ""Bottom USB Type-C""
-						register "type"		= "UPC_TYPE_C_USB2_SS_SWITCH"
-						register "group"	= "ACPI_PLD_GROUP(0, 0)"
+						register "desc"			= ""Bottom USB Type-C""
+						register "type"			= "UPC_TYPE_C_USB2_SS_SWITCH"
+						register "use_custom_pld"	= "true"
+						register "custom_pld"		= "ACPI_PLD_TYPE_C(RIGHT, CENTER, ACPI_PLD_GROUP(0, 0))"
 						device ref usb3_port3 on end
 					end
 					chip drivers/usb/acpi
-						register "desc"		= ""Top USB Type-C""
-						register "type"		= "UPC_TYPE_C_USB2_SS_SWITCH"
-						register "group"	= "ACPI_PLD_GROUP(0, 1)"
+						register "desc"			= ""Top USB Type-C""
+						register "type"			= "UPC_TYPE_C_USB2_SS_SWITCH"
+						register "use_custom_pld"	= "true"
+						register "custom_pld"		= "ACPI_PLD_TYPE_C(RIGHT, CENTER, ACPI_PLD_GROUP(0, 1))"
 						device ref usb2_port2 on end
 					end
 					chip drivers/usb/acpi
-						register "desc"		= ""Top USB Type-C""
-						register "type"		= "UPC_TYPE_C_USB2_SS_SWITCH"
-						register "group"	= "ACPI_PLD_GROUP(0, 1)"
+						register "desc"			= ""Top USB Type-C""
+						register "type"			= "UPC_TYPE_C_USB2_SS_SWITCH"
+						register "use_custom_pld"	= "true"
+						register "custom_pld"		= "ACPI_PLD_TYPE_C(RIGHT, CENTER, ACPI_PLD_GROUP(0, 1))"
 						device ref usb3_port1 on end
 					end
 					chip drivers/usb/acpi
-						register "desc"		= ""USB 2.0 Hub""
-						register "type"		= "UPC_TYPE_HUB"
-						register "group"	= "ACPI_PLD_GROUP(0, 2)"
+						register "desc"			= ""USB 2.0 Hub""
+						register "type"			= "UPC_TYPE_HUB"
+						register "group"		= "ACPI_PLD_GROUP(0, 2)"
 						device ref usb2_port3 on end
 					end
 					chip drivers/usb/acpi
-						register "desc"		= ""USB 2.0 Hub""
-						register "type"		= "UPC_TYPE_HUB"
-						register "group"	= "ACPI_PLD_GROUP(0, 4)"
+						register "desc"			= ""USB 2.0 Hub""
+						register "type"			= "UPC_TYPE_HUB"
+						register "group"		= "ACPI_PLD_GROUP(0, 4)"
 						device ref usb2_port6 on end
 					end
 					chip drivers/usb/acpi
-						register "desc"		= ""CNVi Bluetooth""
-						register "type"		= "UPC_TYPE_INTERNAL"
-						register "is_intel_bluetooth" = "1"
-						register "enable_gpio"	= "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_VGPIO_0)"
-						register "reset_gpio"	= "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A13)"
-						register "group"	= "ACPI_PLD_GROUP(0, 5)"
+						register "desc"			= ""CNVi Bluetooth""
+						register "type"			= "UPC_TYPE_INTERNAL"
+						register "is_intel_bluetooth"	= "1"
+						register "enable_gpio"		= "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_VGPIO_0)"
+						register "reset_gpio"		= "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A13)"
+						register "group"		= "ACPI_PLD_GROUP(0, 5)"
 						device ref usb2_port10 on end
 					end
 				end

From 296e732e229428f28ca0eb60a14db87dfbf3e029 Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Mon, 10 Mar 2025 15:17:24 +0000
Subject: [PATCH 0351/3886] mb/starlabs/starbook/mtl: Change USB Type-C macro

As the USB-C port on this board is not TBT, change the macro to a
regular port as it is more reliable.

Change-Id: Ibcafae6b9bf495e3d41e3a2c49cda070db1c2e0c
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86791
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
---
 src/mainboard/starlabs/starbook/variants/mtl/devicetree.cb | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/mainboard/starlabs/starbook/variants/mtl/devicetree.cb b/src/mainboard/starlabs/starbook/variants/mtl/devicetree.cb
index ac0195c1f3..19d5d99ef3 100644
--- a/src/mainboard/starlabs/starbook/variants/mtl/devicetree.cb
+++ b/src/mainboard/starlabs/starbook/variants/mtl/devicetree.cb
@@ -76,11 +76,11 @@ chip soc/intel/meteorlake
 		device ref gna		on  end
 		device ref xhci		on
 			# Motherboard USB 3.0 Type-C Back	7893 mil
-			register "usb2_ports[0]"		= "USB2_PORT_TYPE_C(OC_SKIP)"
+			register "usb2_ports[0]"		= "USB2_PORT_MID(OC_SKIP)"
 			register "tcss_ports[0]"		= "TCSS_PORT_DEFAULT(OC_SKIP)"
 
 			# Motherboard USB 3.0 Type-C Front	9557 mil
-			register "usb2_ports[2]"		= "USB2_PORT_TYPE_C(OC_SKIP)"
+			register "usb2_ports[2]"		= "USB2_PORT_MID(OC_SKIP)"
 			register "tcss_ports[1]"		= "TCSS_PORT_DEFAULT(OC_SKIP)"
 
 			# Motherboard USB 3.0 Type-A		8916 mil

From e2ba4330dd3e309137b954a6cd17aaf72c584bf6 Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Mon, 10 Mar 2025 08:54:09 +0000
Subject: [PATCH 0352/3886] mb/starlabs/starbook/adl_n: Adjust the TCC offsets

Commit 3a8835f0e877 ("mb/starlabs/*: Unify tcc_offset settings")
unified the TCC offsets based on:
* 70, 80 and 90 degrees for fanless boards
* 80, 90 and 100 degrees for fanned boards

This board has a fan, so make it follow the above.

Change-Id: Ic40ec1a317c787cf7695b37246b2cb337043af2d
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86782
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
---
 src/mainboard/starlabs/starbook/variants/adl_n/devtree.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/src/mainboard/starlabs/starbook/variants/adl_n/devtree.c b/src/mainboard/starlabs/starbook/variants/adl_n/devtree.c
index 1197f14cc6..8ab1c92834 100644
--- a/src/mainboard/starlabs/starbook/variants/adl_n/devtree.c
+++ b/src/mainboard/starlabs/starbook/variants/adl_n/devtree.c
@@ -33,15 +33,15 @@ void devtree_update(void)
 	switch (get_power_profile(PP_POWER_SAVER)) {
 	case PP_POWER_SAVER:
 		performance_scale			-= 50;
-		cfg->tcc_offset				= TCC(70);
+		cfg->tcc_offset				= TCC(80);
 		break;
 	case PP_BALANCED:
 		performance_scale			-= 25;
-		cfg->tcc_offset				= TCC(80);
+		cfg->tcc_offset				= TCC(90);
 		break;
 	case PP_PERFORMANCE:
 		/* Use the Intel defaults */
-		cfg->tcc_offset				= TCC(90);
+		cfg->tcc_offset				= TCC(100);
 		break;
 	}
 

From e545a233a5cc53577e8a708253994090b3d0f9c9 Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Mon, 10 Mar 2025 08:57:57 +0000
Subject: [PATCH 0353/3886] mb/starlabs/starbook/adl_n: Remove the WiFi Generic
 entry

The entry only provided CNVi configuration, and this board does not
use CNVi, so this entry is not required.

Change-Id: I737bed22f5d1545fe91e37d8e55c7c43d1d841fd
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86783
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
---
 .../starlabs/starbook/variants/adl_n/devicetree.cb          | 6 +-----
 1 file changed, 1 insertion(+), 5 deletions(-)

diff --git a/src/mainboard/starlabs/starbook/variants/adl_n/devicetree.cb b/src/mainboard/starlabs/starbook/variants/adl_n/devicetree.cb
index 0e19d3df12..8c74a06183 100644
--- a/src/mainboard/starlabs/starbook/variants/adl_n/devicetree.cb
+++ b/src/mainboard/starlabs/starbook/variants/adl_n/devicetree.cb
@@ -134,11 +134,7 @@ chip soc/intel/alderlake
 		end
 		device ref shared_sram	on  end
 		device ref pcie_rp7	on				# WiFi
-			chip drivers/wifi/generic
-				register "enable_cnvi_ddr_rfim"		= "true"
-				device generic 0 on end
-			end
-			register "pch_pcie_rp[PCH_RP(7)]" = "{
+				register "pch_pcie_rp[PCH_RP(7)]" = "{
 				.clk_src				= 1,
 				.clk_req				= 1,
 				.flags					= PCIE_RP_LTR | PCIE_RP_AER,

From 1a799eb7ace94616b6c0b0e7107f565cba7acfdf Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Mon, 10 Mar 2025 08:58:49 +0000
Subject: [PATCH 0354/3886] mb/starlabs/starbook/adl_n: Change USB Type-C macro

As the USB-C port on this board is not TBT, change the macro to a
regular port as it is more reliable.

Change-Id: I4dae9ff95d448924f1c2a199053be1ad0ca1cece
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86784
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/starlabs/starbook/variants/adl_n/devicetree.cb | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/mainboard/starlabs/starbook/variants/adl_n/devicetree.cb b/src/mainboard/starlabs/starbook/variants/adl_n/devicetree.cb
index 8c74a06183..903f222479 100644
--- a/src/mainboard/starlabs/starbook/variants/adl_n/devicetree.cb
+++ b/src/mainboard/starlabs/starbook/variants/adl_n/devicetree.cb
@@ -40,7 +40,7 @@ chip soc/intel/alderlake
 		device ref gna	on  end
 		device ref xhci on
 			# Motherboard USB 3.0 Type-C Front	9557 mil
-			register "usb2_ports[2]"		= "USB2_PORT_TYPE_C(OC_SKIP)"
+			register "usb2_ports[2]"		= "USB2_PORT_MID(OC_SKIP)"
 			register "usb3_ports[2]"		= "USB3_PORT_DEFAULT(OC_SKIP)"
 
 			# Motherboard USB 3.0 Type-A		8916 mil

From 4dcaf5a2275dcc2b6e5b93e20dbbcc910600824a Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Mon, 10 Mar 2025 09:01:31 +0000
Subject: [PATCH 0355/3886] mb/starlabs/starbook/adl_n: Add generic Graphics
 driver config

This provides entries in the SSDT for all display devices, which
allows the kernel to enumerate them.

Change-Id: I350af852ffed5afda4bbc5a85f5b9db035a99995
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86785
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/starlabs/starbook/Kconfig       |  1 +
 .../starbook/variants/adl_n/devicetree.cb     | 83 ++++++++++++-------
 2 files changed, 53 insertions(+), 31 deletions(-)

diff --git a/src/mainboard/starlabs/starbook/Kconfig b/src/mainboard/starlabs/starbook/Kconfig
index b8b4da4621..169b983bf8 100644
--- a/src/mainboard/starlabs/starbook/Kconfig
+++ b/src/mainboard/starlabs/starbook/Kconfig
@@ -89,6 +89,7 @@ config BOARD_STARLABS_STARBOOK_ADL
 config BOARD_STARLABS_STARBOOK_ADL_N
 	select BOARD_ROMSIZE_KB_16384
 	select BOARD_STARLABS_STARBOOK_ADL_COMMON
+	select DRIVERS_GFX_GENERIC
 	select SOC_INTEL_ALDERLAKE_PCH_N
 
 config BOARD_STARLABS_STARBOOK_RPL
diff --git a/src/mainboard/starlabs/starbook/variants/adl_n/devicetree.cb b/src/mainboard/starlabs/starbook/variants/adl_n/devicetree.cb
index 903f222479..daf7ecd62a 100644
--- a/src/mainboard/starlabs/starbook/variants/adl_n/devicetree.cb
+++ b/src/mainboard/starlabs/starbook/variants/adl_n/devicetree.cb
@@ -29,7 +29,26 @@ chip soc/intel/alderlake
 	# Device Tree
 	device domain 0 on
 		device ref igpu		on
-			register "gfx"				= "GMA_DEFAULT_PANEL(0)"
+			chip drivers/gfx/generic
+				register "device_count"		= "6"
+				# [DDIA] eDP
+				register "device[0].name"	= ""LCD0""
+				register "device[0].type"	= "panel"
+				# [DDIB] HDMI
+				register "device[1].name"	= ""DD01""
+				# [TCP0] Type-C
+				register "device[2].name"	= ""DD02""
+				register "device[2].use_pld"	= "true"
+				register "device[2].pld"	= "ACPI_PLD_TYPE_C(LEFT, CENTER, ACPI_PLD_GROUP(0, 0))"
+				# [TCP1] Type-C
+				register "device[3].name"	= ""DD03""
+				# [TCP2] N/A
+				register "device[4].name"	= ""DD04""
+				# [TCP3] N/A
+				register "device[5].name"	= ""DD05""
+				device generic 0 on end
+			end
+
 			register "ddi_portA_config"		= "1"
 			register "ddi_ports_config" = "{
 				[DDI_PORT_A]				= DDI_ENABLE_HPD,
@@ -63,60 +82,62 @@ chip soc/intel/alderlake
 			chip drivers/usb/acpi
 				device ref xhci_root_hub on
 					chip drivers/usb/acpi
-						register "desc"		= ""Front USB Type-C""
-						register "type"		= "UPC_TYPE_C_USB2_SS_SWITCH"
-						register "group"	= "ACPI_PLD_GROUP(0, 1)"
+						register "desc"			= ""Front USB Type-C""
+						register "type"			= "UPC_TYPE_C_USB2_SS_SWITCH"
+						register "use_custom_pld"	= "true"
+						register "custom_pld"		= "ACPI_PLD_TYPE_C(LEFT, CENTER, ACPI_PLD_GROUP(0, 0))"
 						device ref usb2_port3 on end
 					end
 					chip drivers/usb/acpi
-						register "desc"		= ""Front USB Type-C""
-						register "type"		= "UPC_TYPE_C_USB2_SS_SWITCH"
-						register "group"	= "ACPI_PLD_GROUP(0, 1)"
+						register "desc"			= ""Front USB Type-C""
+						register "type"			= "UPC_TYPE_C_USB2_SS_SWITCH"
+						register "use_custom_pld"	= "true"
+						register "custom_pld"		= "ACPI_PLD_TYPE_C(LEFT, CENTER, ACPI_PLD_GROUP(0, 0))"
 						device ref usb3_port3 on end
 					end
 					chip drivers/usb/acpi
-						register "desc"		= ""Left USB Type-A""
-						register "type"		= "UPC_TYPE_USB3_A"
-						register "group"	= "ACPI_PLD_GROUP(0, 2)"
+						register "desc"			= ""Left USB Type-A""
+						register "type"			= "UPC_TYPE_USB3_A"
+						register "group"		= "ACPI_PLD_GROUP(0, 2)"
 						device ref usb2_port7 on end
 					end
 					chip drivers/usb/acpi
-						register "desc"		= ""Left USB Type-A""
-						register "type"		= "UPC_TYPE_USB3_A"
-						register "group"	= "ACPI_PLD_GROUP(0, 2)"
+						register "desc"			= ""Left USB Type-A""
+						register "type"			= "UPC_TYPE_USB3_A"
+						register "group"		= "ACPI_PLD_GROUP(0, 2)"
 						device ref usb3_port2 on end
 					end
 					chip drivers/usb/acpi
-						register "desc"		= ""Right USB Type-A""
-						register "type"		= "UPC_TYPE_USB3_A"
-						register "group"	= "ACPI_PLD_GROUP(0, 3)"
+						register "desc"			= ""Right USB Type-A""
+						register "type"			= "UPC_TYPE_USB3_A"
+						register "group"		= "ACPI_PLD_GROUP(0, 3)"
 						device ref usb2_port1 on end
 					end
 					chip drivers/usb/acpi
-						register "desc"		= ""Right USB Type-A""
-						register "type"		= "UPC_TYPE_USB3_A"
-						register "group"	= "ACPI_PLD_GROUP(0, 3)"
+						register "desc"			= ""Right USB Type-A""
+						register "type"			= "UPC_TYPE_USB3_A"
+						register "group"		= "ACPI_PLD_GROUP(0, 3)"
 						device ref usb3_port1 on end
 					end
 					chip drivers/usb/acpi
-						register "desc"		= ""Internal Webcam""
-						register "type"		= "UPC_TYPE_INTERNAL"
-						register "group"	= "ACPI_PLD_GROUP(0, 4)"
+						register "desc"			= ""Internal Webcam""
+						register "type"			= "UPC_TYPE_INTERNAL"
+						register "group"		= "ACPI_PLD_GROUP(0, 4)"
 						device ref usb2_port5 on end
 					end
 					chip drivers/usb/acpi
-						register "desc"		= ""USB 2.0 Hub""
-						register "type"		= "UPC_TYPE_HUB"
-						register "group"	= "ACPI_PLD_GROUP(0, 5)"
+						register "desc"			= ""USB 2.0 Hub""
+						register "type"			= "UPC_TYPE_HUB"
+						register "group"		= "ACPI_PLD_GROUP(0, 5)"
 						device ref usb2_port4 on end
 					end
 					chip drivers/usb/acpi
-						register "desc"		= ""Internal Bluetooth""
-						register "type"		= "UPC_TYPE_INTERNAL"
-						register "group"	= "ACPI_PLD_GROUP(0, 6)"
-						register "is_intel_bluetooth" = "true"
-						register "enable_gpio"	= "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A13)"
-						register "reset_gpio"	= "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A13)"
+						register "desc"			= ""Internal Bluetooth""
+						register "type"			= "UPC_TYPE_INTERNAL"
+						register "group"		= "ACPI_PLD_GROUP(0, 6)"
+						register "is_intel_bluetooth"	= "true"
+						register "enable_gpio"		= "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A13)"
+						register "reset_gpio"		= "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A13)"
 						device ref usb2_port8 on end
 					end
 				end

From 534f9e7514b12eb3a63ddb49b2665a94c30c7a3c Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Mon, 10 Mar 2025 09:01:58 +0000
Subject: [PATCH 0356/3886] mb/starlabs/starbook/adl_n: Correct alignment in
 devicetree

Change-Id: I3a67abc7f8a169fc9484c6dd0efd2ef92404d8f3
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86786
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/starlabs/starbook/variants/adl_n/devicetree.cb | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/mainboard/starlabs/starbook/variants/adl_n/devicetree.cb b/src/mainboard/starlabs/starbook/variants/adl_n/devicetree.cb
index daf7ecd62a..c180de222c 100644
--- a/src/mainboard/starlabs/starbook/variants/adl_n/devicetree.cb
+++ b/src/mainboard/starlabs/starbook/variants/adl_n/devicetree.cb
@@ -155,7 +155,7 @@ chip soc/intel/alderlake
 		end
 		device ref shared_sram	on  end
 		device ref pcie_rp7	on				# WiFi
-				register "pch_pcie_rp[PCH_RP(7)]" = "{
+			register "pch_pcie_rp[PCH_RP(7)]" = "{
 				.clk_src				= 1,
 				.clk_req				= 1,
 				.flags					= PCIE_RP_LTR | PCIE_RP_AER,

From 68b8565fc45e437facba58f67dbd661efb79783a Mon Sep 17 00:00:00 2001
From: Momoko Hattori <momohatt@google.com>
Date: Fri, 7 Mar 2025 12:21:33 +0900
Subject: [PATCH 0357/3886] drivers/i2c/generic: Add option to generate proper
 PowerResource _STA

The _STA method of drivers/i2c/generic PowerResource currently always
returns true. To allow generating _STA that returns the device's actual
power state, this CL adds a new boolean option `use_gpio_for_status` to
the `drivers_i2c_generic_config` struct, and propagates the value to
`acpi_power_res_params` to reuse the feature implemented for acpi/device
in [1].

[1] https://review.coreboot.org/c/coreboot/+/55027

BUG=b:397355818
TEST=Dump SSDT on redrix with CB:86749

Change-Id: I5c0a423730788d634a780d1d1d8c87a7007cc150
Signed-off-by: Momoko Hattori <momohatt@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86759
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Sam McNally <sammc@google.com>
---
 src/drivers/i2c/generic/chip.h    | 6 ++++++
 src/drivers/i2c/generic/generic.c | 3 ++-
 2 files changed, 8 insertions(+), 1 deletion(-)

diff --git a/src/drivers/i2c/generic/chip.h b/src/drivers/i2c/generic/chip.h
index 69ce29dae4..546fcef9b4 100644
--- a/src/drivers/i2c/generic/chip.h
+++ b/src/drivers/i2c/generic/chip.h
@@ -110,6 +110,12 @@ struct drivers_i2c_generic_config {
 	/* Generic properties for exporting device-specific data to the OS */
 	struct acpi_dp property_list[MAX_GENERIC_PROPERTY_LIST];
 	int property_count;
+
+	/* Write a _STA method that uses the state of the GPIOs to determine if
+	 * the PowerResource is ON or OFF. If this is false, the _STA method
+	 * will always return ON.
+	 */
+	bool use_gpio_for_status;
 };
 
 /*
diff --git a/src/drivers/i2c/generic/generic.c b/src/drivers/i2c/generic/generic.c
index 260ea83b10..250a21b248 100644
--- a/src/drivers/i2c/generic/generic.c
+++ b/src/drivers/i2c/generic/generic.c
@@ -141,7 +141,8 @@ void i2c_generic_fill_ssdt(const struct device *dev,
 			config->enable_off_delay_ms,
 			&config->stop_gpio,
 			config->stop_delay_ms,
-			config->stop_off_delay_ms
+			config->stop_off_delay_ms,
+			config->use_gpio_for_status
 		};
 		acpi_device_add_power_res(&power_res_params);
 	}

From d0367e38a9e5d5b86f1a33024077297e6fc55bbc Mon Sep 17 00:00:00 2001
From: Momoko Hattori <momohatt@google.com>
Date: Fri, 7 Mar 2025 12:50:49 +0900
Subject: [PATCH 0358/3886] mb/google/brya/var/redrix: Enable
 use_gpio_for_status for touchscreen

The _STA method of redrix i2c3's power resource currently always returns
true. This causes the device to be powered on by the kernel in a boot
critical path (in acpi_bus_init_power) and blocks it for 300ms due to
the sleep in the _ON method. To prevent this sleep from blocking the
boot, enable use_gpio_for_status so that the implementation of _STA
returns the device's actual power state and the kernel powers on the
device in another place that doesn't block boot.

BUG=b:397355818
TEST=Boot the device, confirm that kernel doesn't sleep for 300ms during
     acpi_bus_init_power and the touchscreen works without any problems.

Change-Id: I517a9477f7b59b621337c56eedbfcf17b82dc39b
Signed-off-by: Momoko Hattori <momohatt@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86749
Reviewed-by: Sam McNally <sammc@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/google/brya/variants/redrix/overridetree.cb | 1 +
 1 file changed, 1 insertion(+)

diff --git a/src/mainboard/google/brya/variants/redrix/overridetree.cb b/src/mainboard/google/brya/variants/redrix/overridetree.cb
index f26d133461..1a9f1d9b17 100644
--- a/src/mainboard/google/brya/variants/redrix/overridetree.cb
+++ b/src/mainboard/google/brya/variants/redrix/overridetree.cb
@@ -514,6 +514,7 @@ chip soc/intel/alderlake
 							"ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C6)"
 				register "generic.stop_off_delay_ms" = "1"
 				register "generic.has_power_resource" = "1"
+				register "generic.use_gpio_for_status" = "true"
 				register "hid_desc_reg_offset" = "0x01"
 				device i2c 0x15 on end
 			end

From dcc6fbb59ad6a8917c862c4cf22f3dba341e7adf Mon Sep 17 00:00:00 2001
From: "Kulkarni, Srinivas" <srinivas.kulkarni@intel.com>
Date: Fri, 28 Feb 2025 14:09:02 +0530
Subject: [PATCH 0359/3886] vc/intel/fsp/ptl: Update header files from 3015_00
 to 3071_00
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Update header files for FSP for Panther Lake platform to version
3071_00, with the previous version being 3015_00.

Changes includes:
FSPM:
- Offset changes
- Added UPD's - TXDQSDCC, WeaklockEn, RxDqsDelayCompEn
FSPS:
- Reserved bit changes

BUG=b:396535191
TEST=Able to build Google/fatcat.

Change-Id: I9657eb2b6db1b05adc721b3ef2cf8661642d91e8
Signed-off-by: Kulkarni, Srinivas <srinivas.kulkarni@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86642
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Jayvik Desai <jayvik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
---
 .../intel/fsp/fsp2_0/pantherlake/FspmUpd.h    | 1052 +++++++++--------
 .../intel/fsp/fsp2_0/pantherlake/FspsUpd.h    |  732 ++++++------
 2 files changed, 911 insertions(+), 873 deletions(-)

diff --git a/src/vendorcode/intel/fsp/fsp2_0/pantherlake/FspmUpd.h b/src/vendorcode/intel/fsp/fsp2_0/pantherlake/FspmUpd.h
index 82a790eec3..55dc43cdfa 100644
--- a/src/vendorcode/intel/fsp/fsp2_0/pantherlake/FspmUpd.h
+++ b/src/vendorcode/intel/fsp/fsp2_0/pantherlake/FspmUpd.h
@@ -662,703 +662,715 @@ typedef struct {
 **/
   UINT8                       SpdProfileSelected;
 
-/** Offset 0x0211
+/** Offset 0x0211 - RxVref Per-Bit Training
+  Enable/Disable RxVref Per-Bit Training
+  $EN_DIS
 **/
   UINT8                       RXVREFPERBIT;
 
-/** Offset 0x0212 - Reserved
+/** Offset 0x0212 - TXDQS DCC Training
+  Enables/Disable TXDQS DCC Training
+  $EN_DIS
+**/
+  UINT8                       TXDQSDCC;
+
+/** Offset 0x0213 - Reserved
 **/
   UINT8                       Reserved12;
 
-/** Offset 0x0213 - Ch Hash Override
+/** Offset 0x0214 - Ch Hash Override
   Select if Channel Hash setting values will be taken from input parameters or automatically
   taken from POR values depending on DRAM type detected. NOTE: ONLY if Memory interleaved Mode
   $EN_DIS
 **/
   UINT8                       ChHashOverride;
 
-/** Offset 0x0214 - Reserved
+/** Offset 0x0215 - Reserved
 **/
   UINT8                       Reserved13[2];
 
-/** Offset 0x0216 - DQS Rise/Fall
+/** Offset 0x0217 - DQS Rise/Fall
   Enables/Disable DQS Rise/Fall
   $EN_DIS
 **/
   UINT8                       RDDQSODTT;
 
-/** Offset 0x0217 - Reserved
+/** Offset 0x0218 - Reserved
 **/
   UINT8                       Reserved14[2];
 
-/** Offset 0x0219 - Functional Duty Cycle Correction for DDR5 CLK
+/** Offset 0x021A - Functional Duty Cycle Correction for DDR5 CLK
   Enable/Disable Functional Duty Cycle Correction for DDR5 CLK
   0:Disable, 1:Enable
 **/
   UINT8                       FUNCDCCCLK;
 
-/** Offset 0x021A - Functional Duty Cycle Correction for DDR5 DQS
+/** Offset 0x021B - Functional Duty Cycle Correction for DDR5 DQS
   Enable/Disable Functional Duty Cycle Correction for DDR5 DQS
   0:Disable, 1:Enable
 **/
   UINT8                       FUNCDCCDQS;
 
-/** Offset 0x021B
+/** Offset 0x021C
 **/
   UINT8                       FUNCDCCWCK;
 
-/** Offset 0x021C - Duty Cycle Correction for LP5 DCA
+/** Offset 0x021D - Duty Cycle Correction for LP5 DCA
   Enable/Disable Duty Cycle Correction for LP5 DCA
   $EN_DIS
 **/
   UINT8                       DCCLP5WCKDCA;
 
-/** Offset 0x021D - DQ/DQS Swizzle Training
+/** Offset 0x021E - DQ/DQS Swizzle Training
   Enable/Disable DQ/DQS Swizzle Training
   $EN_DIS
 **/
   UINT8                       DQDQSSWZ;
 
-/** Offset 0x021E - Reserved
+/** Offset 0x021F - Reserved
 **/
   UINT8                       Reserved15;
 
-/** Offset 0x021F - Functional Duty Cycle Correction for Data DQ
+/** Offset 0x0220 - Functional Duty Cycle Correction for Data DQ
   Enable/Disable Functional Duty Cycle Correction for Data DQ
   0:Disable, 1:Enable
 **/
   UINT8                       FUNCDCCDQ;
 
-/** Offset 0x0220 - Reserved
+/** Offset 0x0221 - Reserved
 **/
   UINT8                       Reserved16[5];
 
-/** Offset 0x0225 - Unmatched Rx Calibration
+/** Offset 0x0226 - Unmatched Rx Calibration
   Enable/Disable Rx Unmatched Calibration
   $EN_DIS
 **/
   UINT8                       RXUNMATCHEDCAL;
 
-/** Offset 0x0226 - Hard Post Package Repair
+/** Offset 0x0227 - Hard Post Package Repair
   Enables/Disable Hard Post Package Repair
   $EN_DIS
 **/
   UINT8                       PPR;
 
-/** Offset 0x0227 - Reserved
+/** Offset 0x0228 - Reserved
 **/
   UINT8                       Reserved17;
 
-/** Offset 0x0228 - PPR Run Once
+/** Offset 0x0229 - PPR Run Once
   When Eanble, PPR will run only once and then is disabled at next training cycle
   $EN_DIS
 **/
   UINT8                       PprRunOnce;
 
-/** Offset 0x0229 - PPR Run During Fastboot
+/** Offset 0x022A - PPR Run During Fastboot
   When Eanble, PPR will run during fastboot
   $EN_DIS
 **/
   UINT8                       PprRunAtFastboot;
 
-/** Offset 0x022A - PPR Repair Type
+/** Offset 0x022B - PPR Repair Type
   PPR Repair Type: 0:Do not Repair (Default), 1:Soft Repair, 2:Hard Repair
   0:Do not Repair (Default), 1:Soft Repair, 2:Hard Repair
 **/
   UINT8                       PprRepairType;
 
-/** Offset 0x022B - PPR Error Injection
+/** Offset 0x022C - PPR Error Injection
   When Eanble, PPR will inject bad rows during testing
   $EN_DIS
 **/
   UINT8                       PprErrorInjection;
 
-/** Offset 0x022C - PPR Repair Controller
+/** Offset 0x022D - PPR Repair Controller
   PPR repair controller: User chooses to force repair specifc address
 **/
   UINT8                       PprRepairController;
 
-/** Offset 0x022D - PPR Repair Channel
+/** Offset 0x022E - PPR Repair Channel
   PPR repair Channel: User chooses to force repair specifc address
 **/
   UINT8                       PprRepairChannel;
 
-/** Offset 0x022E - PPR Repair Dimm
+/** Offset 0x022F - PPR Repair Dimm
   PPR repair Dimm: User chooses to force repair specifc address
 **/
   UINT8                       PprRepairDimm;
 
-/** Offset 0x022F - PPR Repair Rank
+/** Offset 0x0230 - PPR Repair Rank
   PPR repair Rank: User chooses to force repair specifc address
 **/
   UINT8                       PprRepairRank;
 
-/** Offset 0x0230 - PPR Repair Row
+/** Offset 0x0231 - Reserved
+**/
+  UINT8                       Reserved18[3];
+
+/** Offset 0x0234 - PPR Repair Row
   PPR repair Row: User chooses to force repair specifc address
 **/
   UINT32                      PprRepairRow;
 
-/** Offset 0x0234 - Reserved
+/** Offset 0x0238 - Reserved
 **/
-  UINT8                      Reserved18[8];
+  UINT8                      Reserved19[8];
 
-/** Offset 0x023C - PPR Repair BankGroup
+/** Offset 0x0240 - PPR Repair BankGroup
   PPR repair BankGroup: User chooses to force repair specifc address
 **/
   UINT8                       PprRepairBankGroup;
 
-/** Offset 0x023D - LVR Auto Trim
+/** Offset 0x0241 - LVR Auto Trim
   Enable/disable LVR Auto Trim
   $EN_DIS
 **/
   UINT8                       LVRAUTOTRIM;
 
-/** Offset 0x023E - Compensation Optimization
+/** Offset 0x0242 - Compensation Optimization
   Enable/Disable Compensation Optimization
   $EN_DIS
 **/
   UINT8                       OPTIMIZECOMP;
 
-/** Offset 0x023F - Write DQ/DQS Retraining
+/** Offset 0x0243 - Write DQ/DQS Retraining
   Enable/Disable Write DQ/DQS Retraining
   $EN_DIS
 **/
   UINT8                       WRTRETRAIN;
 
-/** Offset 0x0240 - Reserved
+/** Offset 0x0244 - Reserved
 **/
-  UINT8                       Reserved19[3];
+  UINT8                       Reserved20[3];
 
-/** Offset 0x0243 - RDDQODTT
+/** Offset 0x0247 - RDDQODTT
   Enable/disable Read DQ ODT Training
   $EN_DIS
 **/
   UINT8                       RDDQODTT;
 
-/** Offset 0x0244 - RDCTLET
+/** Offset 0x0248 - RDCTLET
   Enable/disable Read CTLE Training
   $EN_DIS
 **/
   UINT8                       RDCTLET;
 
-/** Offset 0x0245 - RxVref Pre EMPHASIS Training
+/** Offset 0x0249 - RxVref Pre EMPHASIS Training
   Enable/Disable Pre EMPHASIS Training
   $EN_DIS
 **/
   UINT8                       EMPHASIS;
 
-/** Offset 0x0246 - RX DQS VOC Centring Training
+/** Offset 0x024A - RX DQS VOC Centring Training
   Enable/Disable RX DQS VOC Centring Training
   $EN_DIS
 **/
   UINT8                       RXDQSVOCC;
 
-/** Offset 0x0247 - NMode
+/** Offset 0x024B - NMode
   System command rate, range 0-2, 0 means auto, 1 = 1N, 2 = 2N
 **/
   UINT8                       NModeSupport;
 
-/** Offset 0x0248 - LPDDR ODT RttWr
+/** Offset 0x024C - LPDDR ODT RttWr
   Initial RttWr for LP4/5 in Ohms. 0x0 - Auto
 **/
   UINT8                       LpddrRttWr;
 
-/** Offset 0x0249 - Retrain on Fast flow Failure
+/** Offset 0x024D - Retrain on Fast flow Failure
   Restart MRC in Cold mode if SW MemTest fails during Fast flow.
   $EN_DIS
 **/
   UINT8                       RetrainOnFastFail;
 
-/** Offset 0x024A - LPDDR ODT RttCa
+/** Offset 0x024E - LPDDR ODT RttCa
   Initial RttCa for LP4/5 in Ohms. 0x0 - Auto
 **/
   UINT8                       LpddrRttCa;
 
-/** Offset 0x024B - DIMM DFE Training
+/** Offset 0x024F - DIMM DFE Training
   Enable/Disable DIMM DFE Training
   $EN_DIS
 **/
   UINT8                       WRTDIMMDFE;
 
-/** Offset 0x024C - DDR5 ODT Timing Config
+/** Offset 0x0250 - DDR5 ODT Timing Config
   Enable/Disable DDR5 ODT TIMING CONFIG
   $EN_DIS
 **/
   UINT8                       DDR5ODTTIMING;
 
-/** Offset 0x024D - HobBufferSize
+/** Offset 0x0251 - HobBufferSize
   Size to set HOB Buffer. 0:Default, 1: 1 Byte, 2: 1 KB, 3: Max value(assuming 63KB
   total HOB size).
   0:Default, 1: 1 Byte, 2: 1 KB, 3: Max value
 **/
   UINT8                       HobBufferSize;
 
-/** Offset 0x024E - Early Command Training
+/** Offset 0x0252 - Early Command Training
   Enables/Disable Early Command Training
   $EN_DIS
 **/
   UINT8                       ECT;
 
-/** Offset 0x024F - SenseAmp Offset Training
+/** Offset 0x0253 - SenseAmp Offset Training
   Enables/Disable SenseAmp Offset Training
   $EN_DIS
 **/
   UINT8                       SOT;
 
-/** Offset 0x0250 - Early ReadMPR Timing Centering 2D
+/** Offset 0x0254 - Early ReadMPR Timing Centering 2D
   Enables/Disable Early ReadMPR Timing Centering 2D
   $EN_DIS
 **/
   UINT8                       ERDMPRTC2D;
 
-/** Offset 0x0251 - Read MPR Training
+/** Offset 0x0255 - Read MPR Training
   Enables/Disable Read MPR Training
   $EN_DIS
 **/
   UINT8                       RDMPRT;
 
-/** Offset 0x0252 - Receive Enable Training
+/** Offset 0x0256 - Receive Enable Training
   Enables/Disable Receive Enable Training
   $EN_DIS
 **/
   UINT8                       RCVET;
 
-/** Offset 0x0253 - Jedec Write Leveling
+/** Offset 0x0257 - Jedec Write Leveling
   Enables/Disable Jedec Write Leveling
   $EN_DIS
 **/
   UINT8                       JWRL;
 
-/** Offset 0x0254 - Early Write Time Centering 2D
+/** Offset 0x0258 - Early Write Time Centering 2D
   Enables/Disable Early Write Time Centering 2D
   $EN_DIS
 **/
   UINT8                       EWRTC2D;
 
-/** Offset 0x0255 - Early Read Time Centering 2D
+/** Offset 0x0259 - Early Read Time Centering 2D
   Enables/Disable Early Read Time Centering 2D
   $EN_DIS
 **/
   UINT8                       ERDTC2D;
 
-/** Offset 0x0256 - Unmatched Write Time Centering 1D
+/** Offset 0x025A - Unmatched Write Time Centering 1D
   Enable/Disable Unmatched Write Time Centering 1D
   $EN_DIS
 **/
   UINT8                       UNMATCHEDWRTC1D;
 
-/** Offset 0x0257 - Write Timing Centering 1D
+/** Offset 0x025B - Write Timing Centering 1D
   Enables/Disable Write Timing Centering 1D
   $EN_DIS
 **/
   UINT8                       WRTC1D;
 
-/** Offset 0x0258 - Write Voltage Centering 1D
+/** Offset 0x025C - Write Voltage Centering 1D
   Enables/Disable Write Voltage Centering 1D
   $EN_DIS
 **/
   UINT8                       WRVC1D;
 
-/** Offset 0x0259 - Read Timing Centering 1D
+/** Offset 0x025D - Read Timing Centering 1D
   Enables/Disable Read Timing Centering 1D
   $EN_DIS
 **/
   UINT8                       RDTC1D;
 
-/** Offset 0x025A - Dimm ODT Training
+/** Offset 0x025E - Dimm ODT Training
   Enables/Disable Dimm ODT Training
   $EN_DIS
 **/
   UINT8                       DIMMODTT;
 
-/** Offset 0x025B - DIMM RON Training
+/** Offset 0x025F - DIMM RON Training
   Enables/Disable DIMM RON Training
   $EN_DIS
 **/
   UINT8                       DIMMRONT;
 
-/** Offset 0x025C - Write Drive Strength/Equalization 2D
+/** Offset 0x0260 - Write Drive Strength/Equalization 2D
   Enables/Disable Write Drive Strength/Equalization 2D
   $EN_DIS
 **/
   UINT8                       WRDSEQT;
 
-/** Offset 0x025D - Read Equalization Training
+/** Offset 0x0261 - Read Equalization Training
   Enables/Disable Read Equalization Training
   $EN_DIS
 **/
   UINT8                       RDEQT;
 
-/** Offset 0x025E - Write Timing Centering 2D
+/** Offset 0x0262 - Write Timing Centering 2D
   Enables/Disable Write Timing Centering 2D
   $EN_DIS
 **/
   UINT8                       WRTC2D;
 
-/** Offset 0x025F - Read Timing Centering 2D
+/** Offset 0x0263 - Read Timing Centering 2D
   Enables/Disable Read Timing Centering 2D
   $EN_DIS
 **/
   UINT8                       RDTC2D;
 
-/** Offset 0x0260 - Write Voltage Centering 2D
+/** Offset 0x0264 - Write Voltage Centering 2D
   Enables/Disable Write Voltage Centering 2D
   $EN_DIS
 **/
   UINT8                       WRVC2D;
 
-/** Offset 0x0261 - Read Voltage Centering 2D
+/** Offset 0x0265 - Read Voltage Centering 2D
   Enables/Disable Read Voltage Centering 2D
   $EN_DIS
 **/
   UINT8                       RDVC2D;
 
-/** Offset 0x0262 - Command Voltage Centering
+/** Offset 0x0266 - Command Voltage Centering
   Enables/Disable Command Voltage Centering
   $EN_DIS
 **/
   UINT8                       CMDVC;
 
-/** Offset 0x0263 - Late Command Training
+/** Offset 0x0267 - Late Command Training
   Enables/Disable Late Command Training
   $EN_DIS
 **/
   UINT8                       LCT;
 
-/** Offset 0x0264 - Round Trip Latency Training
+/** Offset 0x0268 - Round Trip Latency Training
   Enables/Disable Round Trip Latency Training
   $EN_DIS
 **/
   UINT8                       RTL;
 
-/** Offset 0x0265 - Turn Around Timing Training
+/** Offset 0x0269 - Turn Around Timing Training
   Enables/Disable Turn Around Timing Training
   $EN_DIS
 **/
   UINT8                       TAT;
 
-/** Offset 0x0266 - Reserved
+/** Offset 0x026A - Reserved
 **/
-  UINT8                       Reserved20;
+  UINT8                       Reserved21;
 
-/** Offset 0x0267 - DIMM SPD Alias Test
+/** Offset 0x026B - DIMM SPD Alias Test
   Enables/Disable DIMM SPD Alias Test
   $EN_DIS
 **/
   UINT8                       ALIASCHK;
 
-/** Offset 0x0268 - Receive Enable Centering 1D
+/** Offset 0x026C - Receive Enable Centering 1D
   Enables/Disable Receive Enable Centering 1D
   $EN_DIS
 **/
   UINT8                       RCVENC1D;
 
-/** Offset 0x0269 - Retrain Margin Check
+/** Offset 0x026D - Retrain Margin Check
   Enables/Disable Retrain Margin Check
   $EN_DIS
 **/
   UINT8                       RMC;
 
-/** Offset 0x026A - ECC Support
+/** Offset 0x026E - ECC Support
   Enables/Disable ECC Support
   $EN_DIS
 **/
   UINT8                       EccSupport;
 
-/** Offset 0x026B - Reserved
+/** Offset 0x026F - Reserved
 **/
-  UINT8                       Reserved21[2];
+  UINT8                       Reserved22[2];
 
-/** Offset 0x026D - Ibecc
+/** Offset 0x0271 - Ibecc
   In-Band ECC Support
   $EN_DIS
 **/
   UINT8                       Ibecc;
 
-/** Offset 0x026E - IbeccParity
+/** Offset 0x0272 - IbeccParity
   In-Band ECC Parity Control
   $EN_DIS
 **/
   UINT8                       IbeccParity;
 
-/** Offset 0x026F - Reserved
+/** Offset 0x0273 - Reserved
 **/
-  UINT8                       Reserved22;
+  UINT8                       Reserved23;
 
-/** Offset 0x0270 - IbeccOperationMode
+/** Offset 0x0274 - IbeccOperationMode
   In-Band ECC Operation Mode
   0:Protect base on address range, 1: Non-protected, 2: All protected
 **/
   UINT8                       IbeccOperationMode;
 
-/** Offset 0x0271 - IbeccProtectedRegionEnable
+/** Offset 0x0275 - IbeccProtectedRegionEnable
   In-Band ECC Protected Region Enable
   $EN_DIS
 **/
   UINT8                       IbeccProtectedRegionEnable[8];
 
-/** Offset 0x0279 - Reserved
+/** Offset 0x027D - Reserved
 **/
-  UINT8                       Reserved23;
+  UINT8                       Reserved24;
 
-/** Offset 0x027A - IbeccProtectedRegionBases
+/** Offset 0x027E - IbeccProtectedRegionBases
   IBECC Protected Region Bases per IBECC instance
 **/
   UINT16                      IbeccProtectedRegionBase[8];
 
-/** Offset 0x028A - IbeccProtectedRegionMasks
+/** Offset 0x028E - IbeccProtectedRegionMasks
   IBECC Protected Region Masks
 **/
   UINT16                      IbeccProtectedRegionMask[8];
 
-/** Offset 0x029A - Memory Remap
+/** Offset 0x029E - Memory Remap
   Enables/Disable Memory Remap
   $EN_DIS
 **/
   UINT8                       RemapEnable;
 
-/** Offset 0x029B - Rank Interleave support
+/** Offset 0x029F - Rank Interleave support
   Enables/Disable Rank Interleave support. NOTE: RI and HORI can not be enabled at
   the same time.
   $EN_DIS
 **/
   UINT8                       RankInterleave;
 
-/** Offset 0x029C - Enhanced Interleave support
+/** Offset 0x02A0 - Enhanced Interleave support
   Enables/Disable Enhanced Interleave support
   $EN_DIS
 **/
   UINT8                       EnhancedInterleave;
 
-/** Offset 0x029D - Ch Hash Support
+/** Offset 0x02A1 - Ch Hash Support
   Enable/Disable Channel Hash Support. NOTE: ONLY if Memory interleaved Mode
   $EN_DIS
 **/
   UINT8                       ChHashEnable;
 
-/** Offset 0x029E - DDR PowerDown and idle counter
+/** Offset 0x02A2 - DDR PowerDown and idle counter
   Enables/Disable DDR PowerDown and idle counter(For LPDDR Only)
   $EN_DIS
 **/
   UINT8                       EnablePwrDn;
 
-/** Offset 0x029F - DDR PowerDown and idle counter
+/** Offset 0x02A3 - DDR PowerDown and idle counter
   Enables/Disable DDR PowerDown and idle counter(For LPDDR Only)
   $EN_DIS
 **/
   UINT8                       EnablePwrDnLpddr;
 
-/** Offset 0x02A0 - SelfRefresh Enable
+/** Offset 0x02A4 - SelfRefresh Enable
   Enables/Disable SelfRefresh Enable
   $EN_DIS
 **/
   UINT8                       SrefCfgEna;
 
-/** Offset 0x02A1 - Throttler CKEMin Defeature
+/** Offset 0x02A5 - Throttler CKEMin Defeature
   Enables/Disable Throttler CKEMin Defeature(For LPDDR Only)
   $EN_DIS
 **/
   UINT8                       ThrtCkeMinDefeatLpddr;
 
-/** Offset 0x02A2 - Throttler CKEMin Defeature
+/** Offset 0x02A6 - Throttler CKEMin Defeature
   Enables/Disable Throttler CKEMin Defeature
   $EN_DIS
 **/
   UINT8                       ThrtCkeMinDefeat;
 
-/** Offset 0x02A3 - Exit On Failure (MRC)
+/** Offset 0x02A7 - Exit On Failure (MRC)
   Enables/Disable Exit On Failure (MRC)
   $EN_DIS
 **/
   UINT8                       ExitOnFailure;
 
-/** Offset 0x02A4 - Reserved
+/** Offset 0x02A8 - Reserved
 **/
-  UINT8                       Reserved24[2];
+  UINT8                       Reserved25[2];
 
-/** Offset 0x02A6 - Read Voltage Centering 1D
+/** Offset 0x02AA - Read Voltage Centering 1D
   Enable/Disable Read Voltage Centering 1D
   $EN_DIS
 **/
   UINT8                       RDVC1D;
 
-/** Offset 0x02A7 - TxDqTCO Comp Training
+/** Offset 0x02AB - TxDqTCO Comp Training
   Enable/Disable TxDqTCO Comp Training
   $EN_DIS
 **/
   UINT8                       TXTCO;
 
-/** Offset 0x02A8 - ClkTCO Comp Training
+/** Offset 0x02AC - ClkTCO Comp Training
   Enable/Disable ClkTCO Comp Training
   $EN_DIS
 **/
   UINT8                       CLKTCO;
 
-/** Offset 0x02A9 - CMD Slew Rate Training
+/** Offset 0x02AD - CMD Slew Rate Training
   Enable/Disable CMD Slew Rate Training
   $EN_DIS
 **/
   UINT8                       CMDSR;
 
-/** Offset 0x02AA - CMD Drive Strength and Tx Equalization
+/** Offset 0x02AE - CMD Drive Strength and Tx Equalization
   Enable/Disable CMD Drive Strength and Tx Equalization
   $EN_DIS
 **/
   UINT8                       CMDDSEQ;
 
-/** Offset 0x02AB - DIMM CA ODT Training
+/** Offset 0x02AF - DIMM CA ODT Training
   Enable/Disable DIMM CA ODT Training
   $EN_DIS
 **/
   UINT8                       DIMMODTCA;
 
-/** Offset 0x02AC - Read Vref Decap Training*
+/** Offset 0x02B0 - Read Vref Decap Training*
   Enable/Disable Read Vref Decap Training*
   $EN_DIS
 **/
   UINT8                       RDVREFDC;
 
-/** Offset 0x02AD - Rank Margin Tool Per Bit
+/** Offset 0x02B1 - Rank Margin Tool Per Bit
   Enable/Disable Rank Margin Tool Per Bit
   $EN_DIS
 **/
   UINT8                       RMTBIT;
 
-/** Offset 0x02AE - Ref PI Calibration
+/** Offset 0x02B2 - Ref PI Calibration
   Enable/Disable Ref PI Calibration
   $EN_DIS
 **/
   UINT8                       REFPI;
 
-/** Offset 0x02AF - VccClk FF Offset Correction
+/** Offset 0x02B3 - VccClk FF Offset Correction
   Enable/Disable VccClk FF Offset Correction
   0:Disable, 1:Enable
 **/
   UINT8                       VCCCLKFF;
 
-/** Offset 0x02B0 - Data PI Linearity Calibration
+/** Offset 0x02B4 - Data PI Linearity Calibration
   Enable/Disable {Data PI Linearity Calibration
   $EN_DIS
 **/
   UINT8                       DATAPILIN;
 
-/** Offset 0x02B1 - Ddr5 Rx Cross-Talk Cancellation
+/** Offset 0x02B5 - Ddr5 Rx Cross-Talk Cancellation
   Enable/Disable {Ddr5 Rx Cross-Talk Cancellation
   $EN_DIS
 **/
   UINT8                       DDR5XTALK;
 
-/** Offset 0x02B2 - Retrain On Working Channel
+/** Offset 0x02B6 - Retrain On Working Channel
   Enables/Disable Retrain On Working Channel feature
   $EN_DIS
 **/
   UINT8                       RetrainToWorkingChannel;
 
-/** Offset 0x02B3 - Row Press
+/** Offset 0x02B7 - Row Press
   Enables/Disable Row Press feature
   $EN_DIS
 **/
   UINT8                       RowPressEn;
 
-/** Offset 0x02B4 - Reserved
+/** Offset 0x02B8 - Reserved
 **/
-  UINT8                       Reserved25;
+  UINT8                       Reserved26;
 
-/** Offset 0x02B5 - DDR5 MR7 WICA support
+/** Offset 0x02B9 - DDR5 MR7 WICA support
   Enable if DDR5 DRAM Device supports MR7 WICA 0.5 tCK offset alignment
   $EN_DIS
 **/
   UINT8                       IsDdr5MR7WicaSupported;
 
-/** Offset 0x02B6 - Ch Hash Interleaved Bit
+/** Offset 0x02BA - Ch Hash Interleaved Bit
   Select the BIT to be used for Channel Interleaved mode. NOTE: BIT7 will interlave
   the channels at a 2 cacheline granularity, BIT8 at 4 and BIT9 at 8. Default is BIT8
   0:BIT6, 1:BIT7, 2:BIT8, 3:BIT9, 4:BIT10, 5:BIT11, 6:BIT12, 7:BIT13
 **/
   UINT8                       ChHashInterleaveBit;
 
-/** Offset 0x02B7 - Reserved
+/** Offset 0x02BB - Reserved
 **/
-  UINT8                       Reserved26;
+  UINT8                       Reserved27;
 
-/** Offset 0x02B8 - Ch Hash Mask
+/** Offset 0x02BC - Ch Hash Mask
   Set the BIT(s) to be included in the XOR function. NOTE BIT mask corresponds to
   BITS [19:6] Default is 0x30CC
 **/
   UINT16                      ChHashMask;
 
-/** Offset 0x02BA - Reserved
+/** Offset 0x02BE - Reserved
 **/
-  UINT8                       Reserved27;
+  UINT8                       Reserved28;
 
-/** Offset 0x02BB - Throttler CKEMin Timer
+/** Offset 0x02BF - Throttler CKEMin Timer
   Timer value for CKEMin, range[255;0]. Req'd min of SC_ROUND_T + BYTE_LENGTH (4).
   Dfault is 0x00
 **/
   UINT8                       ThrtCkeMinTmr;
 
-/** Offset 0x02BC - Allow Opp Ref Below Write Threhold
+/** Offset 0x02C0 - Allow Opp Ref Below Write Threhold
   Allow opportunistic refreshes while we don't exit power down.
   $EN_DIS
 **/
   UINT8                       AllowOppRefBelowWriteThrehold;
 
-/** Offset 0x02BD - Write Threshold
+/** Offset 0x02C1 - Write Threshold
   Number of writes that can be accumulated while CKE is low before CKE is asserted.
 **/
   UINT8                       WriteThreshold;
 
-/** Offset 0x02BE - MC_REFRESH_RATE
+/** Offset 0x02C2 - MC_REFRESH_RATE
   Type of Refresh Rate used to prevent Row Hammer. Default is NORMAL Refresh
   0:NORMAL Refresh, 1:1x Refresh, 2:2x Refresh, 3:4x Refresh
 **/
   UINT8                       McRefreshRate;
 
-/** Offset 0x02BF - Refresh Watermarks
+/** Offset 0x02C3 - Refresh Watermarks
   Refresh Watermarks: 0-Low, 1-High (default)
   0:Set Refresh Watermarks to Low, 1:Set Refresh Watermarks to High (Default)
 **/
   UINT8                       RefreshWm;
 
-/** Offset 0x02C0 - User Manual Threshold
+/** Offset 0x02C4 - User Manual Threshold
   Disabled: Predefined threshold will be used.\n
   Enabled: User Input will be used.
   $EN_DIS
 **/
   UINT8                       UserThresholdEnable;
 
-/** Offset 0x02C1 - User Manual Budget
+/** Offset 0x02C5 - User Manual Budget
   Disabled: Configuration of memories will defined the Budget value.\n
   Enabled: User Input will be used.
   $EN_DIS
 **/
   UINT8                       UserBudgetEnable;
 
-/** Offset 0x02C2 - Power Down Mode
+/** Offset 0x02C6 - Power Down Mode
   This option controls command bus tristating during idle periods
   0x0:No Power Down, 0x1:APD, 0x6:PPD DLL OFF, 0xFF:Auto
 **/
   UINT8                       PowerDownMode;
 
-/** Offset 0x02C3 - Pwr Down Idle Timer
+/** Offset 0x02C7 - Pwr Down Idle Timer
   The minimum value should = to the worst case Roundtrip delay + Burst_Length. 0 means
   AUTO: 64 for ULX/ULT, 128 for DT/Halo
 **/
   UINT8                       PwdwnIdleCounter;
 
-/** Offset 0x02C4 - Page Close Idle Timeout
+/** Offset 0x02C8 - Page Close Idle Timeout
   This option controls Page Close Idle Timeout
   0:Enabled, 1:Disabled
 **/
   UINT8                       DisPgCloseIdleTimeout;
 
-/** Offset 0x02C5 - Bitmask of ranks that have CA bus terminated
+/** Offset 0x02C9 - Bitmask of ranks that have CA bus terminated
   LPDDR5: Bitmask of ranks that have CA bus terminated. <b>0x01=Default, Rank0 is
   terminating and Rank1 is non-terminating</b>
 **/
   UINT8                       CmdRanksTerminated;
 
-/** Offset 0x02C6 - MRC Safe Mode Override
+/** Offset 0x02CA - MRC Safe Mode Override
   SafeModeOverride[0] Enable DdrSafeMode override, SafeModeOverride[1] Enable McSafeMode
   override, SafeModeOverride[2] Enable MrcSafeMode override, SafeModeOverride[3]
   Enable Training Algorithm (TrainingEnables) safe mode override, SafeModeOverride[4]
@@ -1366,380 +1378,380 @@ typedef struct {
 **/
   UINT8                       SafeModeOverride;
 
-/** Offset 0x02C7 - Reserved
+/** Offset 0x02CB - Reserved
 **/
-  UINT8                       Reserved28[5];
+  UINT8                       Reserved29[5];
 
-/** Offset 0x02CC - DDR Phy Safe Mode Support
+/** Offset 0x02D0 - DDR Phy Safe Mode Support
   DdrSafeMode[0]: Basic PM Features, DdrSafeMode[1]: Spine Gating, DdrSafeMode[2]:
   Advanced DCC, DdrSafeMode[3]: R2R Training, DdrSafeMode[4]: Transformer Mode, DdrSafeMode[5]:
   PLL Operation, DdrSafeMode[6]: Safe ODT
 **/
   UINT32                      DdrSafeMode;
 
-/** Offset 0x02D0 - Mc Safe Mode Support
-  McSafeMode[0]: Clk Gate / BGF, McSafeMode[1]: CKE Pdwn, McSafeMode[2]: Tristate,
-  McSafeMode[3]: PHY Power States / Clock Spine, McSafeMode[4]: Same Rank TA, McSafeMode[5]:
-  Different Rank TA, McSafeMode[6]: MR4_Period / ZQCAL_Period McSafeMode[7]: LP5
-  Wck Mode, SafeMode[8]: Self Refresh, McSafeMode[9]: WR/RD Retraining, McSafeMode[10]:
-  Power Saving
+/** Offset 0x02D4 - Mc Safe Mode Support
+  McSafeMode[0]: Reserved, McSafeMode[1]: OppSR
 **/
   UINT8                       McSafeMode;
 
-/** Offset 0x02D1 - Ask MRC to clear memory content
+/** Offset 0x02D5 - Ask MRC to clear memory content
   Ask MRC to clear memory content <b>0: Do not Clear Memory;</b> 1: Clear Memory.
   $EN_DIS
 **/
   UINT8                       CleanMemory;
 
-/** Offset 0x02D2 - Reserved
+/** Offset 0x02D6 - Reserved
 **/
-  UINT8                       Reserved29[8];
+  UINT8                       Reserved30[8];
 
-/** Offset 0x02DA - RMTLoopCount
+/** Offset 0x02DE - RMTLoopCount
   Specifies the Loop Count to be used during Rank Margin Tool Testing. 0 - AUTO
 **/
   UINT8                       RMTLoopCount;
 
-/** Offset 0x02DB - DdrOneDpc
+/** Offset 0x02DF - DdrOneDpc
   DDR 1DPC performance feature for 2R DIMMs. Can be enabled on DIMM0 or DIMM1 only,
   or on both (default)
   0: Disabled, 1: Enabled on DIMM0 only, 2: Enabled on DIMM1 only, 3: Enabled
 **/
   UINT8                       DdrOneDpc;
 
-/** Offset 0x02DC - Vddq Voltage Override
+/** Offset 0x02E0 - Vddq Voltage Override
   # is multiple of 1mV where 0 means Auto.
 **/
   UINT16                      VddqVoltageOverride;
 
-/** Offset 0x02DE - VccIog Voltage Override
+/** Offset 0x02E2 - VccIog Voltage Override
   # is multiple of 1mV where 0 means Auto.
 **/
   UINT16                      VccIogVoltageOverride;
 
-/** Offset 0x02E0 - VccClk Voltage Override
+/** Offset 0x02E4 - VccClk Voltage Override
   # is multiple of 1mV where 0 means Auto.
 **/
   UINT16                      VccClkVoltageOverride;
 
-/** Offset 0x02E2 - ThrtCkeMinTmrLpddr
+/** Offset 0x02E6 - ThrtCkeMinTmrLpddr
   Throttler CKE min timer for LPDDR: 0=Minimal, 0xFF=Maximum, <b>0x00=Default</b>
 **/
   UINT8                       ThrtCkeMinTmrLpddr;
 
-/** Offset 0x02E3 - Reserved
-**/
-  UINT8                       Reserved30;
-
-/** Offset 0x02E4 - Margin limit check L2
-  Margin limit check L2 threshold: <b>100=Default</b>
-**/
-  UINT16                      MarginLimitL2;
-
-/** Offset 0x02E6 - Extended Bank Hashing
-  Eanble/Disable ExtendedBankHashing
-  $EN_DIS
-**/
-  UINT8                       ExtendedBankHashing;
-
 /** Offset 0x02E7 - Reserved
 **/
   UINT8                       Reserved31;
 
-/** Offset 0x02E8 - LP5 Command Pins Mapping
+/** Offset 0x02E8 - Margin limit check L2
+  Margin limit check L2 threshold: <b>100=Default</b>
+**/
+  UINT16                      MarginLimitL2;
+
+/** Offset 0x02EA - Extended Bank Hashing
+  Eanble/Disable ExtendedBankHashing
+  $EN_DIS
+**/
+  UINT8                       ExtendedBankHashing;
+
+/** Offset 0x02EB - Reserved
+**/
+  UINT8                       Reserved32;
+
+/** Offset 0x02EC - LP5 Command Pins Mapping
   BitMask where bits [3:0] are Controller 0 Channel [3:0] and bits [7:4] are Controller
   1 Channel [3:0]. 0 = CCC pin mapping is Ascending, 1 = CCC pin mapping is Descending.
 **/
   UINT8                       Lp5CccConfig;
 
-/** Offset 0x02E9 - Command Pins Mirrored
+/** Offset 0x02ED - Command Pins Mirrored
   BitMask where bits [3:0] are Controller 0 Channel [3:0] and bits [7:4] are Controller
   1 Channel [3:0]. 0 = No Command Mirror and 1 = Command Mirror.
 **/
   UINT8                       CmdMirror;
 
-/** Offset 0x02EA - Time Measure
+/** Offset 0x02EE - Time Measure
   Time Measure: 0(Default)=Disable, 1=Enable
   $EN_DIS
 **/
   UINT8                       MrcTimeMeasure;
 
-/** Offset 0x02EB - Reserved
+/** Offset 0x02EF - Reserved
 **/
-  UINT8                       Reserved32[66];
+  UINT8                       Reserved33[64];
 
-/** Offset 0x032D - Board Type
+/** Offset 0x032F - Board Type
   MrcBoardType, Options are 0=Mobile/Mobile Halo, 1=Desktop/DT Halo, 5=ULT/ULX/Mobile
   Halo, 7=UP Server
   0:Mobile/Mobile Halo, 1:Desktop/DT Halo, 5:ULT/ULX/Mobile Halo, 7:UP Server
 **/
   UINT8                       UserBd;
 
-/** Offset 0x032E - Spd Address Table
+/** Offset 0x0330 - Spd Address Table
   Specify SPD Address table for CH0D0/CH0D1/CH1D0&CH1D1. MemorySpdPtr will be used
   if SPD Address is 00
 **/
   UINT8                       SpdAddressTable[16];
 
-/** Offset 0x033E - Enable/Disable MRC TXT dependency
+/** Offset 0x0340 - Enable/Disable MRC TXT dependency
   When enabled MRC execution will wait for TXT initialization to be done first. Disabled(0x0)(Default):
   MRC will not wait for TXT initialization, Enabled(0x1): MRC will wait for TXT initialization
   $EN_DIS
 **/
   UINT8                       TxtImplemented;
 
-/** Offset 0x033F - Reserved
+/** Offset 0x0341 - Reserved
 **/
-  UINT8                       Reserved33;
+  UINT8                       Reserved34;
 
-/** Offset 0x0340 - Skip external display device scanning
+/** Offset 0x0342 - Skip external display device scanning
   Enable: Do not scan for external display device, Disable (Default): Scan external
   display devices
   $EN_DIS
 **/
   UINT8                       SkipExtGfxScan;
 
-/** Offset 0x0341 - Generate BIOS Data ACPI Table
+/** Offset 0x0343 - Generate BIOS Data ACPI Table
   Enable: Generate BDAT for MRC RMT or SA PCIe data. Disable (Default): Do not generate it
   $EN_DIS
 **/
   UINT8                       BdatEnable;
 
-/** Offset 0x0342 - BdatTestType
+/** Offset 0x0344 - BdatTestType
   Indicates the type of Memory Training data to populate into the BDAT ACPI table.
   0:RMT per Rank, 1:RMT per Bit, 2:Margin2D
 **/
   UINT8                       BdatTestType;
 
-/** Offset 0x0343 - Enable PCH HSIO PCIE Rx Set Ctle
+/** Offset 0x0345 - Enable PCH HSIO PCIE Rx Set Ctle
   Enable PCH PCIe Gen 3 Set CTLE Value.
 **/
   UINT8                       PchPcieHsioRxSetCtleEnable[28];
 
-/** Offset 0x035F - PCH HSIO PCIE Rx Set Ctle Value
+/** Offset 0x0361 - PCH HSIO PCIE Rx Set Ctle Value
   PCH PCIe Gen 3 Set CTLE Value.
 **/
   UINT8                       PchPcieHsioRxSetCtle[28];
 
-/** Offset 0x037B - Enble PCH HSIO PCIE TX Gen 1 Downscale Amplitude Adjustment value override
+/** Offset 0x037D - Enble PCH HSIO PCIE TX Gen 1 Downscale Amplitude Adjustment value override
   0: Disable; 1: Enable.
 **/
   UINT8                       PchPcieHsioTxGen1DownscaleAmpEnable[28];
 
-/** Offset 0x0397 - PCH HSIO PCIE Gen 2 TX Output Downscale Amplitude Adjustment value
+/** Offset 0x0399 - PCH HSIO PCIE Gen 2 TX Output Downscale Amplitude Adjustment value
   PCH PCIe Gen 2 TX Output Downscale Amplitude Adjustment value.
 **/
   UINT8                       PchPcieHsioTxGen1DownscaleAmp[28];
 
-/** Offset 0x03B3 - Enable PCH HSIO PCIE TX Gen 2 Downscale Amplitude Adjustment value override
+/** Offset 0x03B5 - Enable PCH HSIO PCIE TX Gen 2 Downscale Amplitude Adjustment value override
   0: Disable; 1: Enable.
 **/
   UINT8                       PchPcieHsioTxGen2DownscaleAmpEnable[28];
 
-/** Offset 0x03CF - PCH HSIO PCIE Gen 2 TX Output Downscale Amplitude Adjustment value
+/** Offset 0x03D1 - PCH HSIO PCIE Gen 2 TX Output Downscale Amplitude Adjustment value
   PCH PCIe Gen 2 TX Output Downscale Amplitude Adjustment value.
 **/
   UINT8                       PchPcieHsioTxGen2DownscaleAmp[28];
 
-/** Offset 0x03EB - Enable PCH HSIO PCIE TX Gen 3 Downscale Amplitude Adjustment value override
+/** Offset 0x03ED - Enable PCH HSIO PCIE TX Gen 3 Downscale Amplitude Adjustment value override
   0: Disable; 1: Enable.
 **/
   UINT8                       PchPcieHsioTxGen3DownscaleAmpEnable[28];
 
-/** Offset 0x0407 - PCH HSIO PCIE Gen 3 TX Output Downscale Amplitude Adjustment value
+/** Offset 0x0409 - PCH HSIO PCIE Gen 3 TX Output Downscale Amplitude Adjustment value
   PCH PCIe Gen 3 TX Output Downscale Amplitude Adjustment value.
 **/
   UINT8                       PchPcieHsioTxGen3DownscaleAmp[28];
 
-/** Offset 0x0423 - Enable PCH HSIO PCIE Gen 1 TX Output De-Emphasis Adjustment Setting value override
+/** Offset 0x0425 - Enable PCH HSIO PCIE Gen 1 TX Output De-Emphasis Adjustment Setting value override
   0: Disable; 1: Enable.
 **/
   UINT8                       PchPcieHsioTxGen1DeEmphEnable[28];
 
-/** Offset 0x043F - PCH HSIO PCIE Gen 1 TX Output De-Emphasis Adjustment value
+/** Offset 0x0441 - PCH HSIO PCIE Gen 1 TX Output De-Emphasis Adjustment value
   PCH PCIe Gen 1 TX Output De-Emphasis Adjustment Setting.
 **/
   UINT8                       PchPcieHsioTxGen1DeEmph[28];
 
-/** Offset 0x045B - Enable PCH HSIO PCIE Gen 2 TX Output -3.5dB De-Emphasis Adjustment Setting value override
+/** Offset 0x045D - Enable PCH HSIO PCIE Gen 2 TX Output -3.5dB De-Emphasis Adjustment Setting value override
   0: Disable; 1: Enable.
 **/
   UINT8                       PchPcieHsioTxGen2DeEmph3p5Enable[28];
 
-/** Offset 0x0477 - PCH HSIO PCIE Gen 2 TX Output -3.5dB De-Emphasis Adjustment value
+/** Offset 0x0479 - PCH HSIO PCIE Gen 2 TX Output -3.5dB De-Emphasis Adjustment value
   PCH PCIe Gen 2 TX Output -3.5dB De-Emphasis Adjustment Setting.
 **/
   UINT8                       PchPcieHsioTxGen2DeEmph3p5[28];
 
-/** Offset 0x0493 - Enable PCH HSIO PCIE Gen 2 TX Output -6.0dB De-Emphasis Adjustment Setting value override
+/** Offset 0x0495 - Enable PCH HSIO PCIE Gen 2 TX Output -6.0dB De-Emphasis Adjustment Setting value override
   0: Disable; 1: Enable.
 **/
   UINT8                       PchPcieHsioTxGen2DeEmph6p0Enable[28];
 
-/** Offset 0x04AF - PCH HSIO PCIE Gen 2 TX Output -6.0dB De-Emphasis Adjustment value
+/** Offset 0x04B1 - PCH HSIO PCIE Gen 2 TX Output -6.0dB De-Emphasis Adjustment value
   PCH PCIe Gen 2 TX Output -6.0dB De-Emphasis Adjustment Setting.
 **/
   UINT8                       PchPcieHsioTxGen2DeEmph6p0[28];
 
-/** Offset 0x04CB - HD Audio DMIC Link Clock Select
+/** Offset 0x04CD - HD Audio DMIC Link Clock Select
   Determines DMIC<N> Clock Source. 0: Both, 1: ClkA, 2: ClkB
   0: Both, 1: ClkA, 2: ClkB
 **/
   UINT8                       PchHdaAudioLinkDmicClockSelect[2];
 
-/** Offset 0x04CD - Enable Intel HD Audio (Azalia)
+/** Offset 0x04CF - Enable Intel HD Audio (Azalia)
   0: Disable, 1: Enable (Default) Azalia controller
   $EN_DIS
 **/
   UINT8                       PchHdaEnable;
 
-/** Offset 0x04CE - Universal Audio Architecture compliance for DSP enabled system
+/** Offset 0x04D0 - Universal Audio Architecture compliance for DSP enabled system
   0: Not-UAA Compliant (Intel SST driver supported only), 1: UAA Compliant (HDA Inbox
   driver or SST driver supported).
   $EN_DIS
 **/
   UINT8                       PchHdaDspUaaCompliance;
 
-/** Offset 0x04CF - Enable HD Audio Link
+/** Offset 0x04D1 - Enable HD Audio Link
   Enable/disable HD Audio Link. Muxed with SSP0/SSP1/SNDW1.
   $EN_DIS
 **/
   UINT8                       PchHdaAudioLinkHdaEnable;
 
-/** Offset 0x04D0 - Enable HDA SDI lanes
+/** Offset 0x04D2 - Enable HDA SDI lanes
   Enable/disable HDA SDI lanes.
 **/
   UINT8                       PchHdaSdiEnable[2];
 
-/** Offset 0x04D2 - Enable HD Audio DMIC_N Link
+/** Offset 0x04D4 - Enable HD Audio DMIC_N Link
   Enable/disable HD Audio DMIC1 link. Muxed with SNDW3.
 **/
   UINT8                       PchHdaAudioLinkDmicEnable[2];
 
-/** Offset 0x04D4 - DMIC<N> ClkA Pin Muxing (N - DMIC number)
+/** Offset 0x04D6 - Reserved
+**/
+  UINT8                       Reserved35[2];
+
+/** Offset 0x04D8 - DMIC<N> ClkA Pin Muxing (N - DMIC number)
   Determines DMIC<N> ClkA Pin muxing. See  GPIO_*_MUXING_DMIC<N>_CLKA_*
 **/
   UINT32                      PchHdaAudioLinkDmicClkAPinMux[2];
 
-/** Offset 0x04DC - Enable HD Audio DSP
+/** Offset 0x04E0 - Enable HD Audio DSP
   Enable/disable HD Audio DSP feature.
   $EN_DIS
 **/
   UINT8                       PchHdaDspEnable;
 
-/** Offset 0x04DD - Reserved
+/** Offset 0x04E1 - Reserved
 **/
-  UINT8                       Reserved34[3];
+  UINT8                       Reserved36[3];
 
-/** Offset 0x04E0 - DMIC<N> Data Pin Muxing
+/** Offset 0x04E4 - DMIC<N> Data Pin Muxing
   Determines DMIC<N> Data Pin muxing. See GPIO_*_MUXING_DMIC<N>_DATA_*
 **/
   UINT32                      PchHdaAudioLinkDmicDataPinMux[2];
 
-/** Offset 0x04E8 - Enable HD Audio SSP0 Link
+/** Offset 0x04EC - Enable HD Audio SSP0 Link
   Enable/disable HD Audio SSP_N/I2S link. Muxed with HDA. N-number 0-5
 **/
   UINT8                       PchHdaAudioLinkSspEnable[7];
 
-/** Offset 0x04EF - Reserved
+/** Offset 0x04F3 - Reserved
 **/
-  UINT8                       Reserved35[117];
+  UINT8                       Reserved37[117];
 
-/** Offset 0x0564 - Enable HD Audio SoundWire#N Link
+/** Offset 0x0568 - Enable HD Audio SoundWire#N Link
   Enable/disable HD Audio SNDW#N link. Muxed with HDA.
 **/
   UINT8                       PchHdaAudioLinkSndwEnable[5];
 
-/** Offset 0x0569 - iDisp-Link Frequency
+/** Offset 0x056D - iDisp-Link Frequency
   iDisp-Link Freq (PCH_HDAUDIO_LINK_FREQUENCY enum): 4: 96MHz, 3: 48MHz.
   4: 96MHz, 3: 48MHz
 **/
   UINT8                       PchHdaIDispLinkFrequency;
 
-/** Offset 0x056A - iDisp-Link T-mode
+/** Offset 0x056E - iDisp-Link T-mode
   iDisp-Link T-Mode (PCH_HDAUDIO_IDISP_TMODE enum): 0: 2T, 2: 4T, 3: 8T, 4: 16T
   0: 2T, 2: 4T, 3: 8T, 4: 16T
 **/
   UINT8                       PchHdaIDispLinkTmode;
 
-/** Offset 0x056B - Reserved
+/** Offset 0x056F - Reserved
 **/
-  UINT8                       Reserved36[45];
+  UINT8                       Reserved38[45];
 
-/** Offset 0x0598 - iDisplay Audio Codec disconnection
+/** Offset 0x059C - iDisplay Audio Codec disconnection
   0: Not disconnected, enumerable, 1: Disconnected SDI, not enumerable.
   $EN_DIS
 **/
   UINT8                       PchHdaIDispCodecDisconnect;
 
-/** Offset 0x0599 - Reserved
+/** Offset 0x059D - Reserved
 **/
-  UINT8                       Reserved37[5];
+  UINT8                       Reserved39[5];
 
-/** Offset 0x059E - HDA Power/Clock Gating (PGD/CGD)
+/** Offset 0x05A2 - HDA Power/Clock Gating (PGD/CGD)
   Enable/Disable HD Audio Power and Clock Gating(POR: Enable). 0: PLATFORM_POR, 1:
   FORCE_ENABLE, 2: FORCE_DISABLE.
   0: POR, 1: Force Enable, 2: Force Disable
 **/
   UINT8                       PchHdaTestPowerClockGating;
 
-/** Offset 0x059F - Reserved
+/** Offset 0x05A3 - Reserved
 **/
-  UINT8                       Reserved38;
+  UINT8                       Reserved40;
 
-/** Offset 0x05A0 - Audio Sub System IDs
+/** Offset 0x05A4 - Audio Sub System IDs
   Set default Audio Sub System IDs. If its set to 0 then value from Strap is used.
 **/
   UINT32                      PchHdaSubSystemIds;
 
-/** Offset 0x05A4 - Reserved
+/** Offset 0x05A8 - Reserved
 **/
-  UINT8                       Reserved39;
+  UINT8                       Reserved41;
 
-/** Offset 0x05A5 - PCH LPC Enhance the port 8xh decoding
+/** Offset 0x05A9 - PCH LPC Enhance the port 8xh decoding
   Original LPC only decodes one byte of port 80h.
   $EN_DIS
 **/
   UINT8                       PchLpcEnhancePort8xhDecoding;
 
-/** Offset 0x05A6 - Usage type for ClkSrc
+/** Offset 0x05AA - Usage type for ClkSrc
   0-23: PCH rootport, 0x70:LAN, 0x80: unspecified but in use (free running), 0xFF: not used
 **/
   UINT8                       PcieClkSrcUsage[18];
 
-/** Offset 0x05B8 - ClkReq-to-ClkSrc mapping
+/** Offset 0x05BC - ClkReq-to-ClkSrc mapping
   Number of ClkReq signal assigned to ClkSrc
 **/
   UINT8                       PcieClkSrcClkReq[18];
 
-/** Offset 0x05CA - Reserved
+/** Offset 0x05CE - Reserved
 **/
-  UINT8                       Reserved40[46];
+  UINT8                       Reserved42[46];
 
-/** Offset 0x05F8 - Enable PCIE RP Mask
+/** Offset 0x05FC - Enable PCIE RP Mask
   Enable/disable PCIE Root Ports. 0: disable, 1: enable. One bit for each port, bit0
   for port1, bit1 for port2, and so on.
 **/
   UINT32                      PcieRpEnableMask;
 
-/** Offset 0x05FC - Debug Interfaces
+/** Offset 0x0600 - Debug Interfaces
   Debug Interfaces. BIT0-RAM, BIT1-UART, BIT3-USB3, BIT4-Serial IO, BIT5-TraceHub,
   BIT2 - Not used.
 **/
   UINT8                       PcdDebugInterfaceFlags;
 
-/** Offset 0x05FD - Reserved
+/** Offset 0x0601 - Reserved
 **/
-  UINT8                       Reserved41[3];
+  UINT8                       Reserved43[3];
 
-/** Offset 0x0600 - Serial Io Uart Debug Mmio Base
+/** Offset 0x0604 - Serial Io Uart Debug Mmio Base
   Select SerialIo Uart default MMIO resource in SEC/PEI phase when PcdLpssUartMode
   = SerialIoUartPci.
 **/
   UINT32                      SerialIoUartDebugMmioBase;
 
-/** Offset 0x0604 - PcdSerialDebugLevel
+/** Offset 0x0608 - PcdSerialDebugLevel
   Serial Debug Message Level. 0:Disable, 1:Error Only, 2:Error & Warnings, 3:Load,
   Error, Warnings & Info, 4:Load, Error, Warnings, Info & Event, 5:Load, Error, Warnings,
   Info & Verbose.
@@ -1748,7 +1760,7 @@ typedef struct {
 **/
   UINT8                       PcdSerialDebugLevel;
 
-/** Offset 0x0605 - SerialDebugMrcLevel
+/** Offset 0x0609 - SerialDebugMrcLevel
   MRC Serial Debug Message Level. 0:Disable, 1:Error Only, 2:Error & Warnings, 3:Load,
   Error, Warnings & Info, 4:Load, Error, Warnings, Info & Event, 5:Load, Error, Warnings,
   Info & Verbose.
@@ -1757,318 +1769,318 @@ typedef struct {
 **/
   UINT8                       SerialDebugMrcLevel;
 
-/** Offset 0x0606 - Serial Io Uart Debug Controller Number
+/** Offset 0x060A - Serial Io Uart Debug Controller Number
   Select SerialIo Uart Controller for debug. Note: If UART0 is selected as CNVi BT
   Core interface, it cannot be used for debug purpose.
   0:SerialIoUart0, 1:SerialIoUart1, 2:SerialIoUart2
 **/
   UINT8                       SerialIoUartDebugControllerNumber;
 
-/** Offset 0x0607 - Serial Io Uart Debug Parity
+/** Offset 0x060B - Serial Io Uart Debug Parity
   Set default Parity.
   0: DefaultParity, 1: NoParity, 2: EvenParity, 3: OddParity
 **/
   UINT8                       SerialIoUartDebugParity;
 
-/** Offset 0x0608 - Serial Io Uart Debug BaudRate
+/** Offset 0x060C - Serial Io Uart Debug BaudRate
   Set default BaudRate Supported from 0 - default to 6000000. Recommended values 9600,
   19200, 57600, 115200, 460800, 921600, 1500000, 1843200, 3000000, 3686400, 6000000
 **/
   UINT32                      SerialIoUartDebugBaudRate;
 
-/** Offset 0x060C - Serial Io Uart Debug Stop Bits
+/** Offset 0x0610 - Serial Io Uart Debug Stop Bits
   Set default stop bits.
   0: DefaultStopBits, 1: OneStopBit, 2: OneFiveStopBits, 3: TwoStopBits
 **/
   UINT8                       SerialIoUartDebugStopBits;
 
-/** Offset 0x060D - Serial Io Uart Debug Data Bits
+/** Offset 0x0611 - Serial Io Uart Debug Data Bits
   Set default word length. 0: Default, 5,6,7,8
   5:5BITS, 6:6BITS, 7:7BITS, 8:8BITS
 **/
   UINT8                       SerialIoUartDebugDataBits;
 
-/** Offset 0x060E - IMGU CLKOUT Configuration
+/** Offset 0x0612 - IMGU CLKOUT Configuration
   The configuration of IMGU CLKOUT, 0: Disable;<b>1: Enable</b>.
   $EN_DIS
 **/
   UINT8                       ImguClkOutEn[6];
 
-/** Offset 0x0614 - Enable/Disable SA IPU
+/** Offset 0x0618 - Enable/Disable SA IPU
   Enable(Default): Enable SA IPU, Disable: Disable SA IPU
   $EN_DIS
 **/
   UINT8                       SaIpuEnable;
 
-/** Offset 0x0615 - Disable and Lock Watch Dog Register
+/** Offset 0x0619 - Disable and Lock Watch Dog Register
   Set 1 to clear WDT status, then disable and lock WDT registers.
   $EN_DIS
 **/
   UINT8                       WdtDisableAndLock;
 
-/** Offset 0x0616 - Reserved
+/** Offset 0x061A - Reserved
 **/
-  UINT8                       Reserved42[2];
+  UINT8                       Reserved44[2];
 
-/** Offset 0x0618 - HECI Timeouts
+/** Offset 0x061C - HECI Timeouts
   0: Disable, 1: Enable (Default) timeout check for HECI
   $EN_DIS
 **/
   UINT8                       HeciTimeouts;
 
-/** Offset 0x0619 - HECI2 Interface Communication
+/** Offset 0x061D - HECI2 Interface Communication
   Test, 0: disable, 1: enable, Adds or Removes HECI2 Device from PCI space.
   $EN_DIS
 **/
   UINT8                       HeciCommunication2;
 
-/** Offset 0x061A - Check HECI message before send
+/** Offset 0x061E - Check HECI message before send
   Test, 0: disable, 1: enable, Enable/Disable message check.
   $EN_DIS
 **/
   UINT8                       DisableMessageCheck;
 
-/** Offset 0x061B - Force ME DID Init Status
+/** Offset 0x061F - Force ME DID Init Status
   Test, 0: disable, 1: Success, 2: No Memory in Channels, 3: Memory Init Error, Set
   ME DID init stat value
   $EN_DIS
 **/
   UINT8                       DidInitStat;
 
-/** Offset 0x061C - Enable KT device
+/** Offset 0x0620 - Enable KT device
   Test, 0: POR, 1: enable, 2: disable, Enable or Disable KT device.
   $EN_DIS
 **/
   UINT8                       KtDeviceEnable;
 
-/** Offset 0x061D - CPU Replaced Polling Disable
+/** Offset 0x0621 - CPU Replaced Polling Disable
   Test, 0: disable, 1: enable, Setting this option disables CPU replacement polling loop
   $EN_DIS
 **/
   UINT8                       DisableCpuReplacedPolling;
 
-/** Offset 0x061E - Skip CPU replacement check
+/** Offset 0x0622 - Skip CPU replacement check
   Test, 0: disable, 1: enable, Setting this option to skip CPU replacement check
   $EN_DIS
 **/
   UINT8                       SkipCpuReplacementCheck;
 
-/** Offset 0x061F - Skip MBP HOB
+/** Offset 0x0623 - Skip MBP HOB
   Test, 0: disable, 1: enable, Enable/Disable sending MBP message and creating MBP Hob.
   $EN_DIS
 **/
   UINT8                       SkipMbpHob;
 
-/** Offset 0x0620 - Reserved
+/** Offset 0x0624 - Reserved
 **/
-  UINT8                       Reserved43[2];
+  UINT8                       Reserved45[2];
 
-/** Offset 0x0622 - ISA Serial Base selection
+/** Offset 0x0626 - ISA Serial Base selection
   Select ISA Serial Base address. Default is 0x3F8.
   0:0x3F8, 1:0x2F8
 **/
   UINT8                       PcdIsaSerialUartBase;
 
-/** Offset 0x0623 - PcdSerialDebugBaudRate
+/** Offset 0x0627 - PcdSerialDebugBaudRate
   Baud Rate for Serial Debug Messages. 3:9600, 4:19200, 6:56700, 7:115200.
   3:9600, 4:19200, 6:56700, 7:115200
 **/
   UINT8                       PcdSerialDebugBaudRate;
 
-/** Offset 0x0624 - Post Code Output Port
+/** Offset 0x0628 - Post Code Output Port
   This option configures Post Code Output Port
 **/
   UINT16                      PostCodeOutputPort;
 
-/** Offset 0x0626 - Reserved
+/** Offset 0x062A - Reserved
 **/
-  UINT8                       Reserved44[22];
+  UINT8                       Reserved46[26];
 
-/** Offset 0x063C - Enable SMBus
+/** Offset 0x0644 - Enable SMBus
   Enable/disable SMBus controller.
   $EN_DIS
 **/
   UINT8                       SmbusEnable;
 
-/** Offset 0x063D - Enable SMBus ARP support
+/** Offset 0x0645 - Enable SMBus ARP support
   Enable SMBus ARP support.
   $EN_DIS
 **/
   UINT8                       SmbusArpEnable;
 
-/** Offset 0x063E - Number of RsvdSmbusAddressTable.
+/** Offset 0x0646 - Number of RsvdSmbusAddressTable.
   The number of elements in the RsvdSmbusAddressTable.
 **/
   UINT8                       PchNumRsvdSmbusAddresses;
 
-/** Offset 0x063F - Reserved
+/** Offset 0x0647 - Reserved
 **/
-  UINT8                       Reserved45;
+  UINT8                       Reserved47;
 
-/** Offset 0x0640 - SMBUS Base Address
+/** Offset 0x0648 - SMBUS Base Address
   SMBUS Base Address (IO space).
 **/
   UINT16                      PchSmbusIoBase;
 
-/** Offset 0x0642 - Enable SMBus Alert Pin
+/** Offset 0x064A - Enable SMBus Alert Pin
   Enable SMBus Alert Pin.
   $EN_DIS
 **/
   UINT8                       PchSmbAlertEnable;
 
-/** Offset 0x0643 - Reserved
+/** Offset 0x064B - Reserved
 **/
-  UINT8                       Reserved46[13];
+  UINT8                       Reserved48[13];
 
-/** Offset 0x0650 - Smbus dynamic power gating
+/** Offset 0x0658 - Smbus dynamic power gating
   Disable or Enable Smbus dynamic power gating.
   $EN_DIS
 **/
   UINT8                       SmbusDynamicPowerGating;
 
-/** Offset 0x0651 - SMBUS SPD Write Disable
+/** Offset 0x0659 - SMBUS SPD Write Disable
   Set/Clear Smbus SPD Write Disable. 0: leave SPD Write Disable bit; 1: set SPD Write
   Disable bit. For security recommendations, SPD write disable bit must be set.
   $EN_DIS
 **/
   UINT8                       SmbusSpdWriteDisable;
 
-/** Offset 0x0652 - Enable/Disable SA OcSupport
+/** Offset 0x065A - Enable/Disable SA OcSupport
   Enable: Enable SA OcSupport, Disable(Default): Disable SA OcSupport
   $EN_DIS
 **/
   UINT8                       SaOcSupport;
 
-/** Offset 0x0653 - Reserved
+/** Offset 0x065B - Reserved
 **/
-  UINT8                       Reserved47[18];
+  UINT8                       Reserved49[18];
 
-/** Offset 0x0665 - Over clocking support
+/** Offset 0x066D - Over clocking support
   Over clocking support; <b>0: Disable</b>; 1: Enable
   $EN_DIS
 **/
   UINT8                       OcSupport;
 
-/** Offset 0x0666 - Reserved
+/** Offset 0x066E - Reserved
 **/
-  UINT8                       Reserved48;
+  UINT8                       Reserved50;
 
-/** Offset 0x0667 - Realtime Memory Timing
+/** Offset 0x066F - Realtime Memory Timing
   0(Default): Disabled, 1: Enabled. When enabled, it will allow the system to perform
   realtime memory timing changes after MRC_DONE.
   0: Disabled, 1: Enabled
 **/
   UINT8                       RealtimeMemoryTiming;
 
-/** Offset 0x0668 - core voltage override
+/** Offset 0x0670 - core voltage override
   The core voltage override which is applied to the entire range of cpu core frequencies.
   Valid Range 0 to 2000
 **/
   UINT16                      CoreVoltageOverride;
 
-/** Offset 0x066A - Core Turbo voltage Offset
+/** Offset 0x0672 - Core Turbo voltage Offset
   The voltage offset applied to the core while operating in turbo mode.Valid Range 0 to 1000
 **/
   UINT16                      CoreVoltageOffset;
 
-/** Offset 0x066C - Core PLL voltage offset
+/** Offset 0x0674 - Core PLL voltage offset
   Core PLL voltage offset. <b>0: No offset</b>. Range 0-15
 **/
   UINT8                       CorePllVoltageOffset;
 
-/** Offset 0x066D - AVX2 Ratio Offset
+/** Offset 0x0675 - AVX2 Ratio Offset
   0(Default)= No Offset. Range 0 - 31. Specifies number of bins to decrease AVX ratio
   vs. Core Ratio. Uses Mailbox MSR 0x150, cmd 0x1B.
 **/
   UINT8                       Avx2RatioOffset;
 
-/** Offset 0x066E - BCLK Adaptive Voltage Enable
+/** Offset 0x0676 - BCLK Adaptive Voltage Enable
   When enabled, the CPU V/F curves are aware of BCLK frequency when calculated. </b>0:
   Disable;<b> 1: Enable
   $EN_DIS
 **/
   UINT8                       BclkAdaptiveVoltage;
 
-/** Offset 0x066F - Ring Downbin
+/** Offset 0x0677 - Ring Downbin
   Ring Downbin enable/disable. When enabled, CPU will ensure the ring ratio is always
   lower than the core ratio.0: Disable; <b>1: Enable.</b>
   $EN_DIS
 **/
   UINT8                       RingDownBin;
 
-/** Offset 0x0670 - Row Hammer pTRR LFSR0 Mask
+/** Offset 0x0678 - Row Hammer pTRR LFSR0 Mask
   Row Hammer pTRR LFSR0 Mask, 1/2^(value)
 **/
   UINT8                       Lfsr0Mask;
 
-/** Offset 0x0671 - Margin Limit Check
+/** Offset 0x0679 - Margin Limit Check
   Margin Limit Check. Choose level of margin check
   0:Disable, 1:L1, 2:L2, 3:Both
 **/
   UINT8                       MarginLimitCheck;
 
-/** Offset 0x0672 - Row Hammer pTRR LFSR1 Mask
+/** Offset 0x067A - Row Hammer pTRR LFSR1 Mask
   Row Hammer pTRR LFSR1 Mask, 1/2^(value)
 **/
   UINT8                       Lfsr1Mask;
 
-/** Offset 0x0673 - Reserved
+/** Offset 0x067B - Reserved
 **/
-  UINT8                       Reserved49[2];
+  UINT8                       Reserved51[2];
 
-/** Offset 0x0675 - TjMax Offset
+/** Offset 0x067D - TjMax Offset
   TjMax offset.Specified value here is clipped by pCode (125 - TjMax Offset) to support
   TjMax in the range of 62 to 115 deg Celsius. Valid Range 10 - 63
 **/
   UINT8                       TjMaxOffset;
 
-/** Offset 0x0676 - Reserved
+/** Offset 0x067E - Reserved
 **/
-  UINT8                      Reserved50[48];
+  UINT8                      Reserved52[48];
 
-/** Offset 0x06A6 - Core VF Point Offset
+/** Offset 0x06AE - Core VF Point Offset
   Array used to specifies the Core Voltage Offset applied to the each selected VF
   Point. This voltage is specified in millivolts.
 **/
   UINT16                      CoreVfPointOffset[15];
 
-/** Offset 0x06C4 - Core VF Point Offset Prefix
+/** Offset 0x06CC - Core VF Point Offset Prefix
   Sets the CoreVfPointOffset value as positive or negative for corresponding core
   VF Point; <b>0: Positive </b>; 1: Negative.
   0:Positive, 1:Negative
 **/
   UINT8                       CoreVfPointOffsetPrefix[15];
 
-/** Offset 0x06D3 - Core VF Point Ratio
+/** Offset 0x06DB - Core VF Point Ratio
   Array for the each selected Core VF Point to display the ration.
 **/
   UINT8                       CoreVfPointRatio[15];
 
-/** Offset 0x06E2 - Reserved
+/** Offset 0x06EA - Reserved
 **/
-  UINT8                       Reserved51[26];
+  UINT8                       Reserved53[26];
 
-/** Offset 0x06FC - Per Core Max Ratio override
+/** Offset 0x0704 - Per Core Max Ratio override
   Enable or disable Per Core PState OC supported by writing OCMB 0x1D to program new
   favored core ratio to each Core. <b>0: Disable</b>, 1: enable
   $EN_DIS
 **/
   UINT8                       PerCoreRatioOverride;
 
-/** Offset 0x06FD - Reserved
+/** Offset 0x0705 - Reserved
 **/
-  UINT8                       Reserved52[25];
+  UINT8                       Reserved54[25];
 
-/** Offset 0x0716 - Per Core Current Max Ratio
+/** Offset 0x071E - Per Core Current Max Ratio
   Array for the Per Core Max Ratio
 **/
   UINT8                       PerCoreRatio[8];
 
-/** Offset 0x071E - Reserved
+/** Offset 0x0726 - Reserved
 **/
-  UINT8                       Reserved53[8];
+  UINT8                       Reserved55[8];
 
-/** Offset 0x0726 - Pvd Ratio Threshold for SOC/CPU die
+/** Offset 0x072E - Pvd Ratio Threshold for SOC/CPU die
   Array of Pvd Ratio Threshold for SOC/CPU die is the threshold value for input ratio
   (P0 to Pn) to select the multiplier so that the output is within the DCO frequency
   range. As per the die selected, this threshold is applied to SA and MC/CMI PLL
@@ -2077,63 +2089,63 @@ typedef struct {
 **/
   UINT8                       PvdRatioThreshold;
 
-/** Offset 0x0727 - Reserved
+/** Offset 0x072F - Reserved
 **/
-  UINT8                       Reserved54[65];
+  UINT8                       Reserved56[65];
 
-/** Offset 0x0768 - CPU BCLK OC Frequency
+/** Offset 0x0770 - CPU BCLK OC Frequency
   CPU BCLK OC Frequency in KHz units. 98000000Hz = 98MHz <b>0 - Auto</b>. Range is
   40Mhz-1000Mhz.
 **/
   UINT32                      CpuBclkOcFrequency;
 
-/** Offset 0x076C - Reserved
+/** Offset 0x0774 - Reserved
 **/
-  UINT8                      Reserved55[13];
+  UINT8                      Reserved57[13];
 
-/** Offset 0x0779 - Avx2 Voltage Guardband Scaling Factor
+/** Offset 0x0781 - Avx2 Voltage Guardband Scaling Factor
   AVX2 Voltage Guardband Scale factor applied to AVX2 workloads. Range is 0-200 in
   1/100 units, where a value of 125 would apply a 1.25 scale factor.
 **/
   UINT8                       Avx2VoltageScaleFactor;
 
-/** Offset 0x077A - Ring PLL voltage offset
+/** Offset 0x0782 - Ring PLL voltage offset
   Core PLL voltage offset. <b>0: No offset</b>. Range 0-15
 **/
   UINT8                       RingPllVoltageOffset;
 
-/** Offset 0x077B - Reserved
+/** Offset 0x0783 - Reserved
 **/
-  UINT8                       Reserved56[5];
+  UINT8                       Reserved58[5];
 
-/** Offset 0x0780 - Enable PCH ISH Controller
+/** Offset 0x0788 - Enable PCH ISH Controller
   0: Disable, 1: Enable (Default) ISH Controller
   $EN_DIS
 **/
   UINT8                       PchIshEnable;
 
-/** Offset 0x0781 - Reserved
+/** Offset 0x0789 - Reserved
 **/
-  UINT8                       Reserved57;
+  UINT8                       Reserved59;
 
-/** Offset 0x0782 - BiosSize
+/** Offset 0x078A - BiosSize
   The size of the BIOS region of the IFWI. Used if FspmUpd->FspmConfig.BiosGuard !=
   0. If BiosGuard is enabled, MRC will increase the size of the DPR (DMA Protected
   Range) so that a BIOS Update Script can be stored in the DPR.
 **/
   UINT16                      BiosSize;
 
-/** Offset 0x0784 - BiosGuard
+/** Offset 0x078C - BiosGuard
   Enable/Disable. 0: Disable, Enable/Disable BIOS Guard feature, 1: enable
   $EN_DIS
 **/
   UINT8                       BiosGuard;
 
-/** Offset 0x0785
+/** Offset 0x078D
 **/
   UINT8                       BiosGuardToolsInterface;
 
-/** Offset 0x0786 - Txt
+/** Offset 0x078E - Txt
   Enables utilization of additional hardware capabilities provided by Intel (R) Trusted
   Execution Technology. Changes require a full power cycle to take effect. <b>0:
   Disable</b>, 1: Enable
@@ -2141,255 +2153,255 @@ typedef struct {
 **/
   UINT8                       Txt;
 
-/** Offset 0x0787 - Skip Stop PBET Timer Enable/Disable
+/** Offset 0x078F - Skip Stop PBET Timer Enable/Disable
   Skip Stop PBET Timer; <b>0: Disable</b>; 1: Enable
   $EN_DIS
 **/
   UINT8                       SkipStopPbet;
 
-/** Offset 0x0788 - Reserved
+/** Offset 0x0790 - Reserved
 **/
-  UINT8                       Reserved58[3];
+  UINT8                       Reserved60[3];
 
-/** Offset 0x078B - MKTME Key-Id Bits Override Enable
+/** Offset 0x0793 - MKTME Key-Id Bits Override Enable
   Configure Trust Domain Extension (TDX) to isolate VMs from Virtual-Machine Manager
   (VMM)/hypervisor <b>0: Disable</b>; 1: Enable.
   $EN_DIS
 **/
   UINT8                       GenerateNewTmeKey;
 
-/** Offset 0x078C - Reserved
+/** Offset 0x0794 - Reserved
 **/
-  UINT8                       Reserved59[4];
+  UINT8                       Reserved61[4];
 
-/** Offset 0x0790 - TME Exclude Base Address
+/** Offset 0x0798 - TME Exclude Base Address
   TME Exclude Base Address.
 **/
   UINT64                      TmeExcludeBase;
 
-/** Offset 0x0798 - TME Exclude Size Value
+/** Offset 0x07A0 - TME Exclude Size Value
   TME Exclude Size Value.
 **/
   UINT64                      TmeExcludeSize;
 
-/** Offset 0x07A0 - Reserved
+/** Offset 0x07A8 - Reserved
 **/
-  UINT8                      Reserved60[14];
+  UINT8                      Reserved62[14];
 
-/** Offset 0x07AE - BIST on Reset
+/** Offset 0x07B6 - BIST on Reset
   Enable/Disable BIST (Built-In Self Test) on reset. <b>0: Disable</b>; 1: Enable.
   $EN_DIS
 **/
   UINT8                       BistOnReset;
 
-/** Offset 0x07AF - Reserved
+/** Offset 0x07B7 - Reserved
 **/
-  UINT8                       Reserved61;
+  UINT8                       Reserved63;
 
-/** Offset 0x07B0 - Enable or Disable VMX
+/** Offset 0x07B8 - Enable or Disable VMX
   Enable or Disable VMX, When enabled, a VMM can utilize the additional hardware capabilities
   provided by Vanderpool Technology. 0: Disable; <b>1: Enable</b>.
   $EN_DIS
 **/
   UINT8                       VmxEnable;
 
-/** Offset 0x07B1 - Processor Early Power On Configuration FCLK setting
+/** Offset 0x07B9 - Processor Early Power On Configuration FCLK setting
   FCLK frequency can take values of 400MHz, 800MHz and 1GHz. <b>0: 800 MHz (ULT/ULX)</b>.
   <b>1: 1 GHz (DT/Halo)</b>. Not supported on ULT/ULX.- 2: 400 MHz. - 3: Reserved
   0:800 MHz, 1: 1 GHz, 2: 400 MHz, 3: Reserved
 **/
   UINT8                       FClkFrequency;
 
-/** Offset 0x07B2 - Enable CPU CrashLog
+/** Offset 0x07BA - Enable CPU CrashLog
   Enable or Disable CPU CrashLog; 0: Disable; <b>1: Enable</b>.
   $EN_DIS
 **/
   UINT8                       CpuCrashLogEnable;
 
-/** Offset 0x07B3 - Enable or Disable TME
+/** Offset 0x07BB - Enable or Disable TME
   Configure Total Memory Encryption (TME) to protect DRAM data from physical attacks.
   <b>0: Disable</b>; 1: Enable.
   $EN_DIS
 **/
   UINT8                       TmeEnable;
 
-/** Offset 0x07B4 - CPU Run Control
+/** Offset 0x07BC - CPU Run Control
   Enable, Disable or Do not configure CPU Run Control; 0: Disable; 1: Enable ; <b>2:
   No Change</b>
   0:Disabled, 1:Enabled, 2:No Change
 **/
   UINT8                       DebugInterfaceEnable;
 
-/** Offset 0x07B5 - CPU Run Control Lock
+/** Offset 0x07BD - CPU Run Control Lock
   Lock or Unlock CPU Run Control; 0: Disable; <b>1: Enable</b>.
   $EN_DIS
 **/
   UINT8                       DebugInterfaceLockEnable;
 
-/** Offset 0x07B6 - Enable CPU CrashLog GPRs dump
+/** Offset 0x07BE - Enable CPU CrashLog GPRs dump
   Enable or Disable CPU CrashLog GPRs dump; <b>0: Disable</b>; 1: Enable; 2: Only
   disable Smm GPRs dump
   0:Disabled, 1:Enabled, 2:Only Smm GPRs Disabled
 **/
   UINT8                       CrashLogGprs;
 
-/** Offset 0x07B7 - Over clocking Lock
+/** Offset 0x07BF - Over clocking Lock
   Lock Overclocking. 0: Disable; <b>1: Enable</b>
   $EN_DIS
 **/
   UINT8                       OcLock;
 
-/** Offset 0x07B8 - CPU ratio value
+/** Offset 0x07C0 - CPU ratio value
   This value must be between Max Efficiency Ratio (LFM) and Maximum non-turbo ratio
   set by Hardware (HFM). Valid Range 0 to 63.
 **/
   UINT8                       CpuRatio;
 
-/** Offset 0x07B9 - Number of active big cores
+/** Offset 0x07C1 - Number of active big cores
   Number of P-cores to enable in each processor package. Note: Number of P-Cores and
   E-Cores are looked at together. When both are {0,0
   0:Disable all big cores, 1:1, 2:2, 3:3, 0xFF:Active all big cores
 **/
   UINT8                       ActiveCoreCount;
 
-/** Offset 0x07BA - Reserved
+/** Offset 0x07C2 - Reserved
 **/
-  UINT8                       Reserved62[6];
+  UINT8                       Reserved64[6];
 
-/** Offset 0x07C0 - PrmrrSize
+/** Offset 0x07C8 - PrmrrSize
   Enable/Disable. 0: Disable, define default value of PrmrrSize , 1: enable
 **/
   UINT32                      PrmrrSize;
 
-/** Offset 0x07C4 - Tseg Size
+/** Offset 0x07CC - Tseg Size
   Size of SMRAM memory reserved. 0x400000 for Release build and 0x1000000 for Debug build
   0x0400000:4MB, 0x01000000:16MB
 **/
   UINT32                      TsegSize;
 
-/** Offset 0x07C8 - SmmRelocationEnable Enable
+/** Offset 0x07D0 - SmmRelocationEnable Enable
   Enable or Disable SmmRelocationEnable. <b>0: Disable</b>, 1:Enable
   $EN_DIS
 **/
   UINT8                       SmmRelocationEnable;
 
-/** Offset 0x07C9 - TCC Activation Offset
+/** Offset 0x07D1 - TCC Activation Offset
   TCC Activation Offset. Offset from factory set TCC activation temperature at which
   the Thermal Control Circuit must be activated. TCC will be activated at TCC Activation
   Temperature, in volts. <b>Default = 0h</b>.
 **/
   UINT8                       TccActivationOffset;
 
-/** Offset 0x07CA - Reserved
+/** Offset 0x07D2 - Reserved
 **/
-  UINT8                       Reserved63[98];
+  UINT8                       Reserved65[98];
 
-/** Offset 0x082C - SinitMemorySize
+/** Offset 0x0834 - SinitMemorySize
   Enable/Disable. 0: Disable, define default value of SinitMemorySize , 1: enable
 **/
   UINT32                      SinitMemorySize;
 
-/** Offset 0x0830 - TxtDprMemoryBase
+/** Offset 0x0838 - TxtDprMemoryBase
   Enable/Disable. 0: Disable, define default value of TxtDprMemoryBase , 1: enable
 **/
   UINT64                      TxtDprMemoryBase;
 
-/** Offset 0x0838 - TxtHeapMemorySize
+/** Offset 0x0840 - TxtHeapMemorySize
   Enable/Disable. 0: Disable, define default value of TxtHeapMemorySize , 1: enable
 **/
   UINT32                      TxtHeapMemorySize;
 
-/** Offset 0x083C - TxtDprMemorySize
+/** Offset 0x0844 - TxtDprMemorySize
   Reserve DPR memory size (0-255) MB. 0: Disable, define default value of TxtDprMemorySize
   , 1: enable
 **/
   UINT32                      TxtDprMemorySize;
 
-/** Offset 0x0840 - TxtLcpPdBase
+/** Offset 0x0848 - TxtLcpPdBase
   Enable/Disable. 0: Disable, define default value of TxtLcpPdBase , 1: enable
 **/
   UINT64                      TxtLcpPdBase;
 
-/** Offset 0x0848 - TxtLcpPdSize
+/** Offset 0x0850 - TxtLcpPdSize
   Enable/Disable. 0: Disable, define default value of TxtLcpPdSize , 1: enable
 **/
   UINT64                      TxtLcpPdSize;
 
-/** Offset 0x0850 - BiosAcmBase
+/** Offset 0x0858 - BiosAcmBase
   Enable/Disable. 0: Disable, define default value of BiosAcmBase , 1: enable
 **/
   UINT64                      BiosAcmBase;
 
-/** Offset 0x0858 - BiosAcmSize
+/** Offset 0x0860 - BiosAcmSize
   Enable/Disable. 0: Disable, define default value of BiosAcmSize , 1: enable
 **/
   UINT32                      BiosAcmSize;
 
-/** Offset 0x085C - ApStartupBase
+/** Offset 0x0864 - ApStartupBase
   Enable/Disable. 0: Disable, define default value of BiosAcmBase , 1: enable
 **/
   UINT32                      ApStartupBase;
 
-/** Offset 0x0860 - TgaSize
+/** Offset 0x0868 - TgaSize
   Enable/Disable. 0: Disable, define default value of TgaSize , 1: enable
 **/
   UINT32                      TgaSize;
 
-/** Offset 0x0864 - IsTPMPresence
+/** Offset 0x086C - IsTPMPresence
   IsTPMPresence default values
 **/
   UINT8                       IsTPMPresence;
 
-/** Offset 0x0865 - Acoustic Noise Mitigation feature
+/** Offset 0x086D - Acoustic Noise Mitigation feature
   Enabling this option will help mitigate acoustic noise on certain SKUs when the
   CPU is in deeper C state. <b>0: Disabled</b>; 1: Enabled
   $EN_DIS
 **/
   UINT8                       AcousticNoiseMitigation;
 
-/** Offset 0x0866 - Reserved
+/** Offset 0x086E - Reserved
 **/
-  UINT8                       Reserved64[2];
+  UINT8                       Reserved66[2];
 
-/** Offset 0x0868 - Platform Power Pmax
+/** Offset 0x0870 - Platform Power Pmax
   PSYS PMax power, defined in 1/8 Watt increments. <b>0 - Auto</b> Specified in 1/8
   Watt increments. Range 0-1024 Watts(0-8191). Value of 800 = 100W
 **/
   UINT16                      PsysPmax;
 
-/** Offset 0x086A - Reserved
+/** Offset 0x0872 - Reserved
 **/
-  UINT8                      Reserved65[12];
+  UINT8                      Reserved67[12];
 
-/** Offset 0x0876 - AcLoadline
+/** Offset 0x087E - AcLoadline
   AC Loadline defined in 1/100 mOhms. A value of 100 = 1.00 mOhm, and 1255 = 12.55
   mOhm. Range is 0-6249 (0-62.49 mOhms). 0 = AUTO/HW default. [0] for IA, [1] for
   GT, [2] for SA, [3] through [5] are Reserved.
 **/
   UINT16                      AcLoadline[6];
 
-/** Offset 0x0882 - DcLoadline
+/** Offset 0x088A - DcLoadline
   DC Loadline defined in 1/100 mOhms. A value of 100 = 1.00 mOhm, and 1255 = 12.55
   mOhm. Range is 0-6249 (0-62.49 mOhms). 0 = AUTO/HW default. [0] for IA, [1] for
   GT, [2] for SA, [3] through [5] are Reserved.
 **/
   UINT16                      DcLoadline[6];
 
-/** Offset 0x088E - Reserved
+/** Offset 0x0896 - Reserved
 **/
-  UINT8                      Reserved66[116];
+  UINT8                      Reserved68[116];
 
-/** Offset 0x0902 - Thermal Design Current enable/disable
+/** Offset 0x090A - Thermal Design Current enable/disable
   Thermal Design Current enable/disable; <b>0: Disable</b>; 1: Enable. [0] for IA,
   [1] for GT, [2] for SA, [3] for atom, [4]-[5] are Reserved.
 **/
   UINT8                       TdcEnable[6];
 
-/** Offset 0x0908 - Reserved
+/** Offset 0x0910 - Reserved
 **/
-  UINT8                       Reserved67[6];
+  UINT8                       Reserved69[6];
 
-/** Offset 0x090E - Disable Fast Slew Rate for Deep Package C States for VR domains
+/** Offset 0x0916 - Disable Fast Slew Rate for Deep Package C States for VR domains
   This option needs to be configured to reduce acoustic noise during deeper C states.
   False: Don't disable Fast ramp during deeper C states; True: Disable Fast ramp
   during deeper C state. [0] for IA, [1] for GT, [2] for SA, [3] through [5] are
@@ -2398,7 +2410,7 @@ typedef struct {
 **/
   UINT8                       FastPkgCRampDisable[6];
 
-/** Offset 0x0914 - Slew Rate configuration for Deep Package C States for VR domains
+/** Offset 0x091C - Slew Rate configuration for Deep Package C States for VR domains
   Set VR IA/GT/SA Slow Slew Rate for Deep Package C State ramp time; Slow slew rate
   equals to Fast divided by number, the number is 2, 4, 8, 16 to slow down the slew
   rate to help minimize acoustic noise; divide by 16 is disabled for GT/SA. <b>0:
@@ -2407,31 +2419,31 @@ typedef struct {
 **/
   UINT8                       SlowSlewRate[6];
 
-/** Offset 0x091A - Reserved
+/** Offset 0x0922 - Reserved
 **/
-  UINT8                       Reserved68[6];
+  UINT8                       Reserved70[6];
 
-/** Offset 0x0920 - Thermal Design Current time window
+/** Offset 0x0928 - Thermal Design Current time window
   Auto = 0 is default. Range is from 1ms to 448s. <b>0: Auto</b>. [0] for IA, [1]
   for GT, [2] for SA, [3] for atom, [4]-[5] are Reserved.
 **/
   UINT32                      TdcTimeWindow[6];
 
-/** Offset 0x0938 - Reserved
+/** Offset 0x0940 - Reserved
 **/
-  UINT8                       Reserved69[8];
+  UINT8                       Reserved71[8];
 
-/** Offset 0x0940 - DLVR RFI Enable
+/** Offset 0x0948 - DLVR RFI Enable
   Enable/Disable DLVR RFI frequency hopping. 0: Disable; <b>1: Enable</b>.
   $EN_DIS
 **/
   UINT8                       DlvrRfiEnable;
 
-/** Offset 0x0941 - Reserved
+/** Offset 0x0949 - Reserved
 **/
-  UINT8                       Reserved70[13];
+  UINT8                       Reserved72[13];
 
-/** Offset 0x094E - VR Fast Vmode ICC Limit support
+/** Offset 0x0956 - VR Fast Vmode ICC Limit support
   Voltage Regulator Fast Vmode ICC Limit. A value of 400 = 100A. A value of 0 corresponds
   to feature disabled (no reactive protection). This value represents the current
   threshold where the VR would initiate reactive protection if Fast Vmode is enabled.
@@ -2440,116 +2452,116 @@ typedef struct {
 **/
   UINT16                      IccLimit[6];
 
-/** Offset 0x095A - Enable/Disable VR FastVmode. The VR will initiate reactive protection if Fast Vmode is enabled.
+/** Offset 0x0962 - Enable/Disable VR FastVmode. The VR will initiate reactive protection if Fast Vmode is enabled.
   Enable/Disable VR FastVmode; <b>0: Disable</b>; 1: Enable.For all VR by domain
   0: Disable, 1: Enable
 **/
   UINT8                       EnableFastVmode[6];
 
-/** Offset 0x0960 - Enable/Disable CEP
+/** Offset 0x0968 - Enable/Disable CEP
   Control for enabling/disabling CEP (Current Excursion Protection). <b>0: Disable</b>; 1: Enable
   0: Disable, 1: Enable
 **/
   UINT8                       CepEnable[6];
 
-/** Offset 0x0966 - Reserved
+/** Offset 0x096E - Reserved
 **/
-  UINT8                       Reserved71[28];
+  UINT8                       Reserved73[28];
 
-/** Offset 0x0982 - PCH Port80 Route
+/** Offset 0x098A - PCH Port80 Route
   Control where the Port 80h cycles are sent, 0: LPC; 1: PCI.
   $EN_DIS
 **/
   UINT8                       PchPort80Route;
 
-/** Offset 0x0983 - GPIO Override
+/** Offset 0x098B - GPIO Override
   Gpio Override Level - FSP will not configure any GPIOs and rely on GPIO setings
   before moved to FSP. Available configurations 0: Disable; 1: Level 1 - Skips GPIO
   configuration in PEI/FSPM/FSPT phase;2: Level 2 - Reserved for future use
 **/
   UINT8                       GpioOverride;
 
-/** Offset 0x0984 - Reserved
+/** Offset 0x098C - Reserved
 **/
-  UINT8                       Reserved72[4];
+  UINT8                       Reserved74[4];
 
-/** Offset 0x0988 - PMR Size
+/** Offset 0x0990 - PMR Size
   Size of PMR memory buffer. 0x400000 for normal boot and 0x200000 for S3 boot
 **/
   UINT32                      DmaBufferSize;
 
-/** Offset 0x098C - The policy for VTd driver behavior
+/** Offset 0x0994 - The policy for VTd driver behavior
   BIT0: Enable IOMMU during boot, BIT1: Enable IOMMU when transfer control to OS
 **/
   UINT8                       PreBootDmaMask;
 
-/** Offset 0x098D - State of DMA_CONTROL_GUARANTEE bit in the DMAR table
+/** Offset 0x0995 - State of DMA_CONTROL_GUARANTEE bit in the DMAR table
   0=Disable/Clear, 1=Enable/Set
   $EN_DIS
 **/
   UINT8                       DmaControlGuarantee;
 
-/** Offset 0x098E - Disable VT-d
+/** Offset 0x0996 - Disable VT-d
   0=Enable/FALSE(VT-d enabled), 1=Disable/TRUE (VT-d disabled)
   $EN_DIS
 **/
   UINT8                       VtdDisable;
 
-/** Offset 0x098F - Reserved
+/** Offset 0x0997 - Reserved
 **/
-  UINT8                       Reserved73;
+  UINT8                       Reserved75;
 
-/** Offset 0x0990 - Base addresses for VT-d function MMIO access
+/** Offset 0x0998 - Base addresses for VT-d function MMIO access
   Base addresses for VT-d MMIO access per VT-d engine
 **/
   UINT32                      VtdBaseAddress[9];
 
-/** Offset 0x09B4 - Reserved
+/** Offset 0x09BC - Reserved
 **/
-  UINT8                       Reserved74[20];
+  UINT8                       Reserved76[20];
 
-/** Offset 0x09C8 - MMIO Size
+/** Offset 0x09D0 - MMIO Size
   Size of MMIO space reserved for devices. 0(Default)=Auto, non-Zero=size in MB
 **/
   UINT16                      MmioSize;
 
-/** Offset 0x09CA - MMIO size adjustment for AUTO mode
+/** Offset 0x09D2 - MMIO size adjustment for AUTO mode
   Positive number means increasing MMIO size, Negative value means decreasing MMIO
   size: 0 (Default)=no change to AUTO mode MMIO size
 **/
   UINT16                      MmioSizeAdjustment;
 
-/** Offset 0x09CC - Reserved
+/** Offset 0x09D4 - Reserved
 **/
-  UINT8                      Reserved75[36];
+  UINT8                      Reserved77[36];
 
-/** Offset 0x09F0 - Enable above 4GB MMIO resource support
+/** Offset 0x09F8 - Enable above 4GB MMIO resource support
   Enable/disable above 4GB MMIO resource support
   $EN_DIS
 **/
   UINT8                       EnableAbove4GBMmio;
 
-/** Offset 0x09F1 - Enable/Disable SA CRID
+/** Offset 0x09F9 - Enable/Disable SA CRID
   Enable: SA CRID, Disable (Default): SA CRID
   $EN_DIS
 **/
   UINT8                       CridEnable;
 
-/** Offset 0x09F2 - Reserved
+/** Offset 0x09FA - Reserved
 **/
-  UINT8                       Reserved76[10];
+  UINT8                       Reserved78[10];
 
-/** Offset 0x09FC - Enable/Disable CrashLog Device
+/** Offset 0x0A04 - Enable/Disable CrashLog Device
   Enable or Disable CrashLog/Telemetry Device  0- Disable, <b>1- Enable</b>
   $EN_DIS
 **/
   UINT32                      CpuCrashLogDevice;
 
-/** Offset 0x0A00 - Reserved
+/** Offset 0x0A08 - Reserved
 **/
-  UINT8                      Reserved77[20];
+  UINT8                      Reserved79[20];
 
-/** Offset 0x0A14 - Platform Debug Option
+/** Offset 0x0A1C - Platform Debug Option
   Enabled Trace active: TraceHub is enabled and trace is active, blocks s0ix.\n
   \n
   Enabled Trace ready: TraceHub is enabled and allowed S0ix.\n
@@ -2562,122 +2574,122 @@ typedef struct {
 **/
   UINT8                       PlatformDebugOption;
 
-/** Offset 0x0A15 - Reserved
+/** Offset 0x0A1D - Reserved
 **/
-  UINT8                       Reserved78[14];
+  UINT8                       Reserved80[14];
 
-/** Offset 0x0A23 - Program GPIOs for LFP on DDI port-A device
+/** Offset 0x0A2B - Program GPIOs for LFP on DDI port-A device
   0=Disabled,1(Default)=eDP, 2=MIPI DSI
   0:Disabled, 1:eDP, 2:MIPI DSI
 **/
   UINT8                       DdiPortAConfig;
 
-/** Offset 0x0A24 - Reserved
+/** Offset 0x0A2C - Reserved
 **/
-  UINT8                      Reserved79[2];
+  UINT8                      Reserved81[2];
 
-/** Offset 0x0A26 - Program GPIOs for LFP on DDI port-B device
+/** Offset 0x0A2E - Program GPIOs for LFP on DDI port-B device
   0(Default)=Disabled,1=eDP, 2=MIPI DSI
   0:Disabled, 1:eDP, 2:MIPI DSI
 **/
   UINT8                       DdiPortBConfig;
 
-/** Offset 0x0A27 - Enable or disable HPD of DDI port A
+/** Offset 0x0A2F - Enable or disable HPD of DDI port A
   0(Default)=Disable, 1=Enable
   $EN_DIS
 **/
   UINT8                       DdiPortAHpd;
 
-/** Offset 0x0A28 - Enable or disable HPD of DDI port B
+/** Offset 0x0A30 - Enable or disable HPD of DDI port B
   0=Disable, 1(Default)=Enable
   $EN_DIS
 **/
   UINT8                       DdiPortBHpd;
 
-/** Offset 0x0A29 - Enable or disable HPD of DDI port C
+/** Offset 0x0A31 - Enable or disable HPD of DDI port C
   0(Default)=Disable, 1=Enable
   $EN_DIS
 **/
   UINT8                       DdiPortCHpd;
 
-/** Offset 0x0A2A - Enable or disable HPD of DDI port 1
+/** Offset 0x0A32 - Enable or disable HPD of DDI port 1
   0=Disable, 1(Default)=Enable
   $EN_DIS
 **/
   UINT8                       DdiPort1Hpd;
 
-/** Offset 0x0A2B - Enable or disable HPD of DDI port 2
+/** Offset 0x0A33 - Enable or disable HPD of DDI port 2
   0(Default)=Disable, 1=Enable
   $EN_DIS
 **/
   UINT8                       DdiPort2Hpd;
 
-/** Offset 0x0A2C - Enable or disable HPD of DDI port 3
+/** Offset 0x0A34 - Enable or disable HPD of DDI port 3
   0(Default)=Disable, 1=Enable
   $EN_DIS
 **/
   UINT8                       DdiPort3Hpd;
 
-/** Offset 0x0A2D - Enable or disable HPD of DDI port 4
+/** Offset 0x0A35 - Enable or disable HPD of DDI port 4
   0(Default)=Disable, 1=Enable
   $EN_DIS
 **/
   UINT8                       DdiPort4Hpd;
 
-/** Offset 0x0A2E - Enable or disable DDC of DDI port A
+/** Offset 0x0A36 - Enable or disable DDC of DDI port A
   0(Default)=Disable, 1=Enable
   $EN_DIS
 **/
   UINT8                       DdiPortADdc;
 
-/** Offset 0x0A2F - Enable or disable DDC of DDI port B
+/** Offset 0x0A37 - Enable or disable DDC of DDI port B
   0=Disable, 1(Default)=Enable
   $EN_DIS
 **/
   UINT8                       DdiPortBDdc;
 
-/** Offset 0x0A30 - Enable or disable DDC of DDI port C
+/** Offset 0x0A38 - Enable or disable DDC of DDI port C
   0(Default)=Disable, 1=Enable
   $EN_DIS
 **/
   UINT8                       DdiPortCDdc;
 
-/** Offset 0x0A31 - Enable DDC setting of DDI Port 1
+/** Offset 0x0A39 - Enable DDC setting of DDI Port 1
   0(Default)=Disable, 1=Enable
   $EN_DIS
 **/
   UINT8                       DdiPort1Ddc;
 
-/** Offset 0x0A32 - Enable DDC setting of DDI Port 2
+/** Offset 0x0A3A - Enable DDC setting of DDI Port 2
   0(Default)=Disable, 1=Enable
   $EN_DIS
 **/
   UINT8                       DdiPort2Ddc;
 
-/** Offset 0x0A33 - Enable DDC setting of DDI Port 3
+/** Offset 0x0A3B - Enable DDC setting of DDI Port 3
   0(Default)=Disable, 1=Enable
   $EN_DIS
 **/
   UINT8                       DdiPort3Ddc;
 
-/** Offset 0x0A34 - Enable DDC setting of DDI Port 4
+/** Offset 0x0A3C - Enable DDC setting of DDI Port 4
   0(Default)=Disable, 1=Enable
   $EN_DIS
 **/
   UINT8                       DdiPort4Ddc;
 
-/** Offset 0x0A35 - Reserved
+/** Offset 0x0A3D - Reserved
 **/
-  UINT8                       Reserved80[3];
+  UINT8                       Reserved82[3];
 
-/** Offset 0x0A38 - Temporary MMIO address for GMADR
+/** Offset 0x0A40 - Temporary MMIO address for GMADR
   The reference code will use this as Temporary MMIO address space to access GMADR
   Registers.Platform should provide conflict free Temporary MMIO Range: GmAdr to
   (GmAdr + 256MB). Default is (PciExpressBaseAddress - 256MB) to (PciExpressBaseAddress - 0x1)
 **/
   UINT64                      LMemBar;
 
-/** Offset 0x0A40 - Temporary MMIO address for GTTMMADR
+/** Offset 0x0A48 - Temporary MMIO address for GTTMMADR
   The reference code will use this as Temporary MMIO address space to access GTTMMADR
   Registers.Platform should provide conflict free Temporary MMIO Range: GttMmAdr
   to (GttMmAdr + 2MB MMIO + 6MB Reserved + GttSize). Default is (GmAdr - (2MB MMIO
@@ -2685,142 +2697,148 @@ typedef struct {
 **/
   UINT64                      GttMmAdr;
 
-/** Offset 0x0A48 - Reserved
+/** Offset 0x0A50 - Reserved
 **/
-  UINT8                      Reserved81[2];
+  UINT8                      Reserved83[2];
 
-/** Offset 0x0A4A - Enable/Disable Memory Bandwidth Compression
+/** Offset 0x0A52 - Enable/Disable Memory Bandwidth Compression
   0=Disable, 1(Default)=Enable
   $EN_DIS
 **/
   UINT8                       MemoryBandwidthCompression;
 
-/** Offset 0x0A4B - Panel Power Enable
+/** Offset 0x0A53 - Panel Power Enable
   Control for enabling/disabling VDD force bit (Required only for early enabling of
   eDP panel). 0=Disable, 1(Default)=Enable
   $EN_DIS
 **/
   UINT8                       PanelPowerEnable;
 
-/** Offset 0x0A4C - Selection of the primary display device
+/** Offset 0x0A54 - Selection of the primary display device
   3(Default)=AUTO, 0=IGFX, 4=Hybrid Graphics
   3:AUTO, 0:IGFX, 4:HG
 **/
   UINT8                       PrimaryDisplay;
 
-/** Offset 0x0A4D - Internal Graphics Data Stolen Memory GSM2
+/** Offset 0x0A55 - Internal Graphics Data Stolen Memory GSM2
   Size of memory preallocated for internal graphics GSM2.
   0:2GB, 1:4GB, 2:6GB, 3:8GB, 4:10GB, 5:12GB, 6:14GB, 7:16GB, 8:18GB, 9:20GB, 10:22GB,
   11:24GB, 12:26GB, 13:28GB, 14:30GB, 15:32GB, 0xFF:No Allocation
 **/
   UINT8                       IGpuGsm2Size;
 
-/** Offset 0x0A4E - Reserved
+/** Offset 0x0A56 - Reserved
 **/
-  UINT8                       Reserved82[2];
+  UINT8                       Reserved84[2];
 
-/** Offset 0x0A50 - Intel Graphics VBT (Video BIOS Table) Size
+/** Offset 0x0A58 - Intel Graphics VBT (Video BIOS Table) Size
   Size of Internal Graphics VBT Image
 **/
   UINT32                      VbtSize;
 
-/** Offset 0x0A54 - Reserved
+/** Offset 0x0A5C - Reserved
 **/
-  UINT8                       Reserved83[4];
+  UINT8                       Reserved85[4];
 
-/** Offset 0x0A58 - Graphics Configuration Ptr
+/** Offset 0x0A60 - Graphics Configuration Ptr
   Points to VBT
 **/
   UINT64                      VbtPtr;
 
-/** Offset 0x0A60 - SOL Training Message Pointer
+/** Offset 0x0A68 - SOL Training Message Pointer
   Points to SOL Message String
 **/
   UINT64                      VgaMessage;
 
-/** Offset 0x0A68 - Platform LID Status for LFP Displays.
+/** Offset 0x0A70 - Platform LID Status for LFP Displays.
   LFP Display Lid Status (LID_STATUS enum): 0 (Default): LidClosed, 1: LidOpen.
   0: LidClosed, 1: LidOpen
 **/
   UINT8                       LidStatus;
 
-/** Offset 0x0A69 - Control SOL VGA Initialition sequence
-  Initialise SOL Init
-  0x0: NO SOL VGA Init, 0x1: SOL VGA Init
+/** Offset 0x0A71 - Control SOL VGA Initialition sequence
+  Initialise SOL Init, BIT0 - (0 : Disable VGA Support, 1 : Enable VGA Support),,
+  BIT1 - (0 : VGA Text Mode 3, 1 : VGA Graphics Mode 12), BIT2 - (0 : VGA Exit Supported,
+  1: NO VGA Exit)
+  0:VGA Disable, 1:Mode 3 VGA, 2:Mode 12 VGA
 **/
   UINT8                       VgaInitControl;
 
-/** Offset 0x0A6A - TCSS USB HOST (xHCI) Enable
+/** Offset 0x0A72 - Reserved
+**/
+  UINT8                      Reserved86[16];
+
+/** Offset 0x0A82 - TCSS USB HOST (xHCI) Enable
   Set TCSS XHCI. 0:Disabled  1:Enabled - Must be enabled if xDCI is enabled below
   $EN_DIS
 **/
   UINT8                       TcssXhciEn;
 
-/** Offset 0x0A6B - Reserved
+/** Offset 0x0A83 - Reserved
 **/
-  UINT8                       Reserved84[4];
+  UINT8                       Reserved87[4];
 
-/** Offset 0x0A6F - TCSS Type C Port 0
+/** Offset 0x0A87 - TCSS Type C Port 0
   Set TCSS Type C Port 0 Type, Options are 0=DISABLE, 1=DP_ONLY, 2=NO_TBT, 3=NO_PCIE,
   7=FULL_FUN
   0:DISABLE, 1:DP_ONLY, 2:NO_TBT, 3: NO_PCIE, 7:FULL_FUN
 **/
   UINT8                       TcssPort0;
 
-/** Offset 0x0A70 - TCSS Type C Port 1
+/** Offset 0x0A88 - TCSS Type C Port 1
   Set TCSS Type C Port 1 Type, Options are 0=DISABLE, 1=DP_ONLY, 2=NO_TBT, 3=NO_PCIE,
   7=FULL_FUN
   0:DISABLE, 1:DP_ONLY, 2:NO_TBT, 3: NO_PCIE, 7:FULL_FUN
 **/
   UINT8                       TcssPort1;
 
-/** Offset 0x0A71 - TCSS Type C Port 2
+/** Offset 0x0A89 - TCSS Type C Port 2
   Set TCSS Type C Port 2 Type, Options are 0=DISABLE, 1=DP_ONLY, 2=NO_TBT, 3=NO_PCIE,
   7=FULL_FUN
   0:DISABLE, 1:DP_ONLY, 2:NO_TBT, 3: NO_PCIE, 7:FULL_FUN
 **/
   UINT8                       TcssPort2;
 
-/** Offset 0x0A72 - TCSS Type C Port 3
+/** Offset 0x0A8A - TCSS Type C Port 3
   Set TCSS Type C Port 3 Type, Options are 0=DISABLE, 1=DP_ONLY, 2=NO_TBT, 3=NO_PCIE,
   7=FULL_FUN
   0:DISABLE, 1:DP_ONLY, 2:NO_TBT, 3: NO_PCIE, 7:FULL_FUN
 **/
   UINT8                       TcssPort3;
 
-/** Offset 0x0A73 - Reserved
+/** Offset 0x0A8B - Reserved
 **/
-  UINT8                       Reserved85;
+  UINT8                       Reserved88;
 
-/** Offset 0x0A74 - TypeC port GPIO setting
+/** Offset 0x0A8C - TypeC port GPIO setting
   GPIO Pin number for Type C Aux orientation setting, use the GpioPad that is defined
   in GpioPinsXXX.h as argument.(XXX is platform name, Ex: Ptl = PantherLake)
 **/
   UINT32                      IomTypeCPortPadCfg[12];
 
-/** Offset 0x0AA4 - TCSS Aux Orientation Override Enable
+/** Offset 0x0ABC - TCSS Aux Orientation Override Enable
   Bits 0, 2, ... 10 control override enables, bits 1, 3, ... 11 control overrides
 **/
   UINT16                      TcssAuxOri;
 
-/** Offset 0x0AA6 - TCSS HSL Orientation Override Enable
+/** Offset 0x0ABE - TCSS HSL Orientation Override Enable
   Bits 0, 2, ... 10 control override enables, bits 1, 3, ... 11 control overrides
 **/
   UINT16                      TcssHslOri;
 
-/** Offset 0x0AA8 - CNVi DDR RFI Mitigation
+/** Offset 0x0AC0 - CNVi DDR RFI Mitigation
   Enable/Disable DDR RFI Mitigation. Default is ENABLE. 0: DISABLE, 1: ENABLE
   $EN_DIS
 **/
   UINT8                       CnviDdrRfim;
 
-/** Offset 0x0AA9 - SOC Trace Hub Mode
+/** Offset 0x0AC1 - SOC Trace Hub Mode
   Enable/Disable SOC TraceHub
   $EN_DIS
 **/
   UINT8                       SocTraceHubMode;
 
-/** Offset 0x0AAA - SOC Trace Hub Memory Region 0 buffer Size
+/** Offset 0x0AC2 - SOC Trace Hub Memory Region 0 buffer Size
   Select size of memory region 0 buffer. Memory allocated by BIOS only applies to
   ITH tool running on the host. For ITH tool running on the target, choose None/OS,
   memory shall be allocated by tool. User should be cautious to choose the amount
@@ -2831,7 +2849,7 @@ typedef struct {
 **/
   UINT16                      SocTraceHubMemReg0Size;
 
-/** Offset 0x0AAC - SOC Trace Hub Memory Region 0 buffer Size
+/** Offset 0x0AC4 - SOC Trace Hub Memory Region 0 buffer Size
   Select size of memory region 1 buffer. Memory allocated by BIOS only applies to
   ITH tool running on the host. For ITH tool running on the target, choose None/OS,
   memory shall be allocated by tool. User should be cautious to choose the amount
@@ -2842,7 +2860,7 @@ typedef struct {
 **/
   UINT16                      SocTraceHubMemReg1Size;
 
-/** Offset 0x0AAE - Internal Graphics Pre-allocated Memory
+/** Offset 0x0AC6 - Internal Graphics Pre-allocated Memory
   Size of memory preallocated for internal graphics.
   0x00:0MB, 0x01:32MB, 0x02:64MB, 0x03:96MB, 0x04:128MB, 0xF0:4MB, 0xF1:8MB, 0xF2:12MB,
   0xF3:16MB, 0xF4:20MB, 0xF5:24MB, 0xF6:28MB, 0xF7:32MB, 0xF8:36MB, 0xF9:40MB, 0xFA:44MB,
@@ -2850,175 +2868,195 @@ typedef struct {
 **/
   UINT16                      IgdDvmt50PreAlloc;
 
-/** Offset 0x0AB0 - Internal Graphics
+/** Offset 0x0AC8 - Internal Graphics
   Enable/disable internal graphics.
   $EN_DIS
 **/
   UINT8                       InternalGraphics;
 
-/** Offset 0x0AB1 - Reserved
+/** Offset 0x0AC9 - Reserved
 **/
-  UINT8                       Reserved86[7];
+  UINT8                       Reserved89;
 
-/** Offset 0x0AB8 - DynamicMemoryBoost
+/** Offset 0x0ACA - DLL Weak Lock Support
+  Enables/Disable DLL Weak Lock Support
+  $EN_DIS
+**/
+  UINT8                       WeaklockEn;
+
+/** Offset 0x0ACB - Reserved
+**/
+  UINT8                       Reserved90;
+
+/** Offset 0x0ACC - Rx DQS Delay Comp Support
+  Enables/Disable Rx DQS Delay Comp Support
+  $EN_DIS
+**/
+  UINT8                       RxDqsDelayCompEn;
+
+/** Offset 0x0ACD - Reserved
+**/
+  UINT8                       Reserved91[7];
+
+/** Offset 0x0AD4 - DynamicMemoryBoost
   Enable/Disable Dynamic Memory Boost Feature. Only valid if SpdProfileSelected is
   an XMP Profile; otherwise ignored. <b>0=Disabled</b>, 1=Enabled.
   $EN_DIS
 **/
   UINT32                      DynamicMemoryBoost;
 
-/** Offset 0x0ABC - RealtimeMemoryFrequency
+/** Offset 0x0AD8 - RealtimeMemoryFrequency
   Enable/Disable Realtime Memory Frequency feature. Only valid if SpdProfileSelected
   is an XMP Profile; otherwise ignored. <b>0=Disabled</b>, 1=Enabled.
   $EN_DIS
 **/
   UINT32                      RealtimeMemoryFrequency;
 
-/** Offset 0x0AC0 - Reserved
+/** Offset 0x0ADC - Reserved
 **/
-  UINT8                      Reserved87[9];
+  UINT8                      Reserved92[9];
 
-/** Offset 0x0AC9 - Vref Offset
+/** Offset 0x0AE5 - Vref Offset
   Offset to be applied to DDRDATACH0_CR_DDRCRDATAOFFSETTRAIN.VrefOffset
   0xFA:-6, 0xFB:-5, 0xFC:-4, 0xFD:-3, 0xFE:-2, 0xFF:-1, 0:0, 1:+1, 2:+2, 3:+3, 4:+4,
   5:+5, 6:+6
 **/
   UINT8                       VrefOffset;
 
-/** Offset 0x0ACA - Reserved
+/** Offset 0x0AE6 - Reserved
 **/
-  UINT8                       Reserved88[2];
+  UINT8                       Reserved93[2];
 
-/** Offset 0x0ACC - tRRSG Delta
+/** Offset 0x0AE8 - tRRSG Delta
   Delay between Read-to-Read commands in the same Bank Group. 0 - Auto. Signed TAT
   delta is (Value - 128). Input value range of [1..255] will give a TAT delta range
   of [-127..127]
 **/
   UINT8                       tRRSG;
 
-/** Offset 0x0ACD - tRRDG Delta
+/** Offset 0x0AE9 - tRRDG Delta
   Delay between Read-to-Read commands in different Bank Group. 0 - Auto. Signed TAT
   delta is (Value - 128). Input value range of [1..255] will give a TAT delta range
   of [-127..127]
 **/
   UINT8                       tRRDG;
 
-/** Offset 0x0ACE - tRRDR Delta
+/** Offset 0x0AEA - tRRDR Delta
   Delay between Read-to-Read commands in different Ranks. 0 - Auto. Signed TAT delta
   is (Value - 128). Input value range of [1..255] will give a TAT delta range of
   [-127..127]
 **/
   UINT8                       tRRDR;
 
-/** Offset 0x0ACF - tRRDD Delta
+/** Offset 0x0AEB - tRRDD Delta
   Delay between Read-to-Read commands in different DIMMs. 0 - Auto. Signed TAT delta
   is (Value - 128). Input value range of [1..255] will give a TAT delta range of
   [-127..127]
 **/
   UINT8                       tRRDD;
 
-/** Offset 0x0AD0 - tWRSG Delta
+/** Offset 0x0AEC - tWRSG Delta
   Delay between Write-to-Read commands in the same Bank Group. 0 - Auto. Signed TAT
   delta is (Value - 128). Input value range of [1..255] will give a TAT delta range
   of [-127..127]
 **/
   UINT8                       tWRSG;
 
-/** Offset 0x0AD1 - tWRDG Delta
+/** Offset 0x0AED - tWRDG Delta
   Delay between Write-to-Read commands in different Bank Group. 0 - Auto. Signed TAT
   delta is (Value - 128). Input value range of [1..255] will give a TAT delta range
   of [-127..127]
 **/
   UINT8                       tWRDG;
 
-/** Offset 0x0AD2 - tWRDR Delta
+/** Offset 0x0AEE - tWRDR Delta
   Delay between Write-to-Read commands in different Ranks. 0 - Auto. Signed TAT delta
   is (Value - 128). Input value range of [1..255] will give a TAT delta range of
   [-127..127]
 **/
   UINT8                       tWRDR;
 
-/** Offset 0x0AD3 - tWRDD Delta
+/** Offset 0x0AEF - tWRDD Delta
   Delay between Write-to-Read commands in different DIMMs. 0 - Auto. Signed TAT delta
   is (Value - 128). Input value range of [1..255] will give a TAT delta range of
   [-127..127]
 **/
   UINT8                       tWRDD;
 
-/** Offset 0x0AD4 - tWWSG Delta
+/** Offset 0x0AF0 - tWWSG Delta
   Delay between Write-to-Write commands in the same Bank Group. 0 - Auto. Signed TAT
   delta is (Value - 128). Input value range of [1..255] will give a TAT delta range
   of [-127..127]
 **/
   UINT8                       tWWSG;
 
-/** Offset 0x0AD5 - tWWDG Delta
+/** Offset 0x0AF1 - tWWDG Delta
   Delay between Write-to-Write commands in different Bank Group. 0 - Auto. Signed
   TAT delta is (Value - 128). Input value range of [1..255] will give a TAT delta
   range of [-127..127]
 **/
   UINT8                       tWWDG;
 
-/** Offset 0x0AD6 - tWWDR Delta
+/** Offset 0x0AF2 - tWWDR Delta
   Delay between Write-to-Write commands in different Ranks. 0 - Auto. Signed TAT delta
   is (Value - 128). Input value range of [1..255] will give a TAT delta range of
   [-127..127]
 **/
   UINT8                       tWWDR;
 
-/** Offset 0x0AD7 - tWWDD Delta
+/** Offset 0x0AF3 - tWWDD Delta
   Delay between Write-to-Write commands in different DIMMs. 0 - Auto. Signed TAT delta
   is (Value - 128). Input value range of [1..255] will give a TAT delta range of
   [-127..127]
 **/
   UINT8                       tWWDD;
 
-/** Offset 0x0AD8 - tRWSG Delta
+/** Offset 0x0AF4 - tRWSG Delta
   Delay between Read-to-Write commands in the same Bank Group. 0 - Auto. Signed TAT
   delta is (Value - 128). Input value range of [1..255] will give a TAT delta range
   of [-127..127]
 **/
   UINT8                       tRWSG;
 
-/** Offset 0x0AD9 - tRWDG Delta
+/** Offset 0x0AF5 - tRWDG Delta
   Delay between Read-to-Write commands in different Bank Group. 0 - Auto. Signed TAT
   delta is (Value - 128). Input value range of [1..255] will give a TAT delta range
   of [-127..127]
 **/
   UINT8                       tRWDG;
 
-/** Offset 0x0ADA - tRWDR Delta
+/** Offset 0x0AF6 - tRWDR Delta
   Delay between Read-to-Write commands in different Ranks. 0 - Auto. Signed TAT delta
   is (Value - 128). Input value range of [1..255] will give a TAT delta range of
   [-127..127]
 **/
   UINT8                       tRWDR;
 
-/** Offset 0x0ADB - tRWDD Delta
+/** Offset 0x0AF7 - tRWDD Delta
   Delay between Read-to-Write commands in different DIMMs. 0 - Auto. Signed TAT delta
   is (Value - 128). Input value range of [1..255] will give a TAT delta range of
   [-127..127]
 **/
   UINT8                       tRWDD;
 
-/** Offset 0x0ADC - Reserved
+/** Offset 0x0AF8 - Reserved
 **/
-  UINT8                       Reserved89[13];
+  UINT8                       Reserved94[13];
 
-/** Offset 0x0AE9 - PPR ForceRepair
+/** Offset 0x0B05 - PPR ForceRepair
   When Eanble, PPR will force repair some rows many times (90)
   $EN_DIS
 **/
   UINT8                       PprForceRepair;
 
-/** Offset 0x0AEA - PPR Repair Bank
+/** Offset 0x0B06 - PPR Repair Bank
   PPR repair Bank: User chooses to force repair specifc address
 **/
   UINT8                       PprRepairBank;
 
-/** Offset 0x0AEB - Reserved
+/** Offset 0x0B07 - Reserved
 **/
-  UINT8                       Reserved90[53];
+  UINT8                       Reserved95[49];
 } FSP_M_CONFIG;
 
 /** Fsp M UPD Configuration
@@ -3037,11 +3075,11 @@ typedef struct {
 **/
   FSP_M_CONFIG                FspmConfig;
 
-/** Offset 0x0B20
+/** Offset 0x0B38
 **/
-  UINT8                       UnusedUpdSpace0[6];
+  UINT8                       FspmRsvd3834[6];
 
-/** Offset 0x0B26
+/** Offset 0x0B3E
 **/
   UINT16                      UpdTerminator;
 } FSPM_UPD;
diff --git a/src/vendorcode/intel/fsp/fsp2_0/pantherlake/FspsUpd.h b/src/vendorcode/intel/fsp/fsp2_0/pantherlake/FspsUpd.h
index a6dde65ef9..3dd46ff5c2 100644
--- a/src/vendorcode/intel/fsp/fsp2_0/pantherlake/FspsUpd.h
+++ b/src/vendorcode/intel/fsp/fsp2_0/pantherlake/FspsUpd.h
@@ -408,212 +408,212 @@ typedef struct {
 
 /** Offset 0x013D - Reserved
 **/
-  UINT8                       Reserved10[4];
+  UINT8                       Reserved10[5];
 
-/** Offset 0x0141 - Enable or Disable MLC Streamer Prefetcher
+/** Offset 0x0142 - Enable or Disable MLC Streamer Prefetcher
   Enable or Disable MLC Streamer Prefetcher; 0: Disable; <b>1: Enable</b>.
   $EN_DIS
 **/
   UINT8                       MlcStreamerPrefetcher;
 
-/** Offset 0x0142 - Enable or Disable MLC Spatial Prefetcher
+/** Offset 0x0143 - Enable or Disable MLC Spatial Prefetcher
   Enable or Disable MLC Spatial Prefetcher; 0: Disable; <b>1: Enable</b>
   $EN_DIS
 **/
   UINT8                       MlcSpatialPrefetcher;
 
-/** Offset 0x0143 - Enable or Disable Monitor /MWAIT instructions
+/** Offset 0x0144 - Enable or Disable Monitor /MWAIT instructions
   Enable/Disable MonitorMWait, if Disable MonitorMwait, the AP threads Idle Manner
   should not set in MWAIT Loop. 0: Disable; <b>1: Enable</b>.
   $EN_DIS
 **/
   UINT8                       MonitorMwaitEnable;
 
-/** Offset 0x0144 - Enable or Disable initialization of machine check registers
+/** Offset 0x0145 - Enable or Disable initialization of machine check registers
   Enable or Disable initialization of machine check registers; 0: Disable; <b>1: Enable</b>.
   $EN_DIS
 **/
   UINT8                       MachineCheckEnable;
 
-/** Offset 0x0145 - Control on Processor Trace output scheme
+/** Offset 0x0146 - Control on Processor Trace output scheme
   Control on Processor Trace output scheme; <b>0: Single Range Output</b>; 1: ToPA Output.
   0: Single Range Output, 1: ToPA Output
 **/
   UINT8                       ProcessorTraceOutputScheme;
 
-/** Offset 0x0146 - Enable or Disable Processor Trace feature
+/** Offset 0x0147 - Enable or Disable Processor Trace feature
   Enable or Disable Processor Trace feature; <b>0: Disable</b>; 1: Enable.
   $EN_DIS
 **/
   UINT8                       ProcessorTraceEnable;
 
-/** Offset 0x0147 - Reserved
+/** Offset 0x0148 - Reserved
 **/
   UINT8                       Reserved11[3];
 
-/** Offset 0x014A - UFS enable/disable
+/** Offset 0x014B - UFS enable/disable
   Enable/Disable UFS controller, One byte for each Controller - (1,0) to enable controller
   0 and (0,1) to enable controller 1
   $EN_DIS
 **/
   UINT8                       UfsEnable[2];
 
-/** Offset 0x014C - Reserved
+/** Offset 0x014D - Reserved
 **/
-  UINT8                       Reserved12[2];
+  UINT8                       Reserved12[4];
 
-/** Offset 0x014E - Enable/Disable PCIe tunneling for USB4
+/** Offset 0x0151 - Enable/Disable PCIe tunneling for USB4
   Enable/Disable PCIe tunneling for USB4, default is enable
   $EN_DIS
 **/
   UINT8                       ITbtPcieTunnelingForUsb4;
 
-/** Offset 0x014F - Reserved
+/** Offset 0x0152 - Reserved
 **/
-  UINT8                       Reserved13;
+  UINT8                       Reserved13[2];
 
-/** Offset 0x0150 - ITBTForcePowerOn Timeout value
+/** Offset 0x0154 - ITBTForcePowerOn Timeout value
   ITBTForcePowerOn value. Specified increment values in miliseconds. Range is 0-1000.
   100 = 100 ms.
 **/
   UINT16                      ITbtForcePowerOnTimeoutInMs;
 
-/** Offset 0x0152 - ITbtConnectTopology Timeout value
+/** Offset 0x0156 - ITbtConnectTopology Timeout value
   ITbtConnectTopologyTimeout value. Specified increment values in miliseconds. Range
   is 0-10000. 100 = 100 ms.
 **/
   UINT16                      ITbtConnectTopologyTimeoutInMs;
 
-/** Offset 0x0154 - ITBT DMA LTR
+/** Offset 0x0158 - ITBT DMA LTR
   TCSS DMA1, DMA2 LTR value
 **/
   UINT16                      ITbtDmaLtr[2];
 
-/** Offset 0x0158 - ITbt Usb4CmMode value
+/** Offset 0x015C - ITbt Usb4CmMode value
   ITbt Usb4CmMode value. 0:Firmware CM, 1:Software CM
 **/
   UINT8                       Usb4CmMode;
 
-/** Offset 0x0159 - Reserved
+/** Offset 0x015D - Reserved
 **/
-  UINT8                       Reserved14[15];
+  UINT8                       Reserved14[19];
 
-/** Offset 0x0168 - IEH Mode
+/** Offset 0x0170 - IEH Mode
   Integrated Error Handler Mode, 0: Bypass, 1: Enable
   0: Bypass, 1:Enable
 **/
   UINT8                       IehMode;
 
-/** Offset 0x0169 - RTC BIOS Interface Lock
+/** Offset 0x0171 - RTC BIOS Interface Lock
   Enable RTC BIOS interface lock. When set, prevents RTC TS (BUC.TS) from being changed.
   $EN_DIS
 **/
   UINT8                       RtcBiosInterfaceLock;
 
-/** Offset 0x016A - RTC Cmos Memory Lock
+/** Offset 0x0172 - RTC Cmos Memory Lock
   Enable RTC lower and upper 128 byte Lock bits to lock Bytes 38h-3Fh in the upper
   and and lower 128-byte bank of RTC RAM.
   $EN_DIS
 **/
   UINT8                       RtcMemoryLock;
 
-/** Offset 0x016B - AMT Switch
+/** Offset 0x0173 - AMT Switch
   Enable/Disable. 0: Disable, 1: enable, Enable or disable AMT functionality.
   $EN_DIS
 **/
   UINT8                       AmtEnabled;
 
-/** Offset 0x016C - SOL Switch
+/** Offset 0x0174 - SOL Switch
   Enable/Disable. 0: Disable, 1: enable, Serial Over Lan enable/disable state by Mebx.
   Setting is invalid if AmtEnabled is 0.
   $EN_DIS
 **/
   UINT8                       AmtSolEnabled;
 
-/** Offset 0x016D - WatchDog Timer Switch
+/** Offset 0x0175 - WatchDog Timer Switch
   Enable/Disable. 0: Disable, 1: enable, Enable or disable WatchDog timer. Setting
   is invalid if AmtEnabled is 0.
   $EN_DIS
 **/
   UINT8                       WatchDogEnabled;
 
-/** Offset 0x016E - OS Timer
+/** Offset 0x0176 - OS Timer
   16 bits Value, Set OS watchdog timer. Setting is invalid if AmtEnabled is 0.
 **/
   UINT16                      WatchDogTimerOs;
 
-/** Offset 0x0170 - BIOS Timer
+/** Offset 0x0178 - BIOS Timer
   16 bits Value, Set BIOS watchdog timer. Setting is invalid if AmtEnabled is 0.
 **/
   UINT16                      WatchDogTimerBios;
 
-/** Offset 0x0172 - Iax Switch
+/** Offset 0x017A - Iax Switch
   Enable/Disable. 0: Disable, 1: enable, Enable or disable Iax functionality.
   $EN_DIS
 **/
   UINT8                       IaxEnable;
 
-/** Offset 0x0173 - Reserved
+/** Offset 0x017B - Reserved
 **/
   UINT8                       Reserved15;
 
-/** Offset 0x0174 - ISH GP GPIO Pin Muxing
+/** Offset 0x017C - ISH GP GPIO Pin Muxing
   Determines ISH GP GPIO Pin muxing. See GPIO_*_MUXING_ISH_GP_x_GPIO_*. 'x' are GP_NUMBER
 **/
   UINT32                      IshGpGpioPinMuxing[12];
 
-/** Offset 0x01A4 - ISH UART Rx Pin Muxing
+/** Offset 0x01AC - ISH UART Rx Pin Muxing
   Determines ISH UART Rx Pin muxing. See GPIO_*_MUXING_ISH_UARTx_TXD_*
 **/
   UINT32                      IshUartRxPinMuxing[3];
 
-/** Offset 0x01B0 - ISH UART Tx Pin Muxing
+/** Offset 0x01B8 - ISH UART Tx Pin Muxing
   Determines ISH UART Tx Pin muxing. See GPIO_*_MUXING_ISH_UARTx_RXD_*
 **/
   UINT32                      IshUartTxPinMuxing[3];
 
-/** Offset 0x01BC - ISH UART Rts Pin Muxing
+/** Offset 0x01C4 - ISH UART Rts Pin Muxing
   Select ISH UART Rts Pin muxing. Refer to GPIO_*_MUXING_ISH_UARTx_RTS_* for possible values.
 **/
   UINT32                      IshUartRtsPinMuxing[3];
 
-/** Offset 0x01C8 - ISH UART Rts Pin Muxing
+/** Offset 0x01D0 - ISH UART Rts Pin Muxing
   Select ISH UART Cts Pin muxing. Refer to GPIO_*_MUXING_ISH_UARTx_CTS_* for possible values.
 **/
   UINT32                      IshUartCtsPinMuxing[3];
 
-/** Offset 0x01D4 - ISH I2C SDA Pin Muxing
+/** Offset 0x01DC - ISH I2C SDA Pin Muxing
   Select ISH I2C SDA Pin muxing. Refer to GPIO_*_MUXING_ISH_I2Cx_SDA_* for possible values.
 **/
   UINT32                      IshI2cSdaPinMuxing[3];
 
-/** Offset 0x01E0 - ISH I2C SCL Pin Muxing
+/** Offset 0x01E8 - ISH I2C SCL Pin Muxing
   Select ISH I2C SCL Pin muxing. Refer to GPIO_*_MUXING_ISH_I2Cx_SCL_* for possible values.
 **/
   UINT32                      IshI2cSclPinMuxing[3];
 
-/** Offset 0x01EC - ISH SPI MOSI Pin Muxing
+/** Offset 0x01F4 - ISH SPI MOSI Pin Muxing
   Select ISH SPI MOSI Pin muxing. Refer to GPIO_*_MUXING_ISH_SPIx_MOSI_* for possible values.
 **/
   UINT32                      IshSpiMosiPinMuxing[2];
 
-/** Offset 0x01F4 - ISH SPI MISO Pin Muxing
+/** Offset 0x01FC - ISH SPI MISO Pin Muxing
   Select ISH SPI MISO Pin muxing. Refer to GPIO_*_MUXING_ISH_SPIx_MISO_* for possible values.
 **/
   UINT32                      IshSpiMisoPinMuxing[2];
 
-/** Offset 0x01FC - ISH SPI CLK Pin Muxing
+/** Offset 0x0204 - ISH SPI CLK Pin Muxing
   Select ISH SPI CLK Pin muxing. Refer to GPIO_*_MUXING_ISH_SPIx_CLK_* for possible values.
 **/
   UINT32                      IshSpiClkPinMuxing[2];
 
-/** Offset 0x0204 - ISH SPI CS#N Pin Muxing
+/** Offset 0x020C - ISH SPI CS#N Pin Muxing
   Select ISH SPI CS#N Pin muxing. Refer to GPIO_*_MUXING_ISH_SPIx_CS<N>_* for possible
   values. N-SPI number, 0-1.
 **/
   UINT32                      IshSpiCsPinMuxing[4];
 
-/** Offset 0x0214 - ISH GP GPIO Pad termination
+/** Offset 0x021C - ISH GP GPIO Pad termination
   0x0: Hardware default, 0x1: None, 0x13: 1kOhm weak pull-up, 0x15: 5kOhm weak pull-up,
   0x19: 20kOhm weak pull-up - Enable/disable SerialIo GP#N GPIO pads termination
   respectively. #N are GP_NUMBER, not strictly relate to indexes of this table. Index
@@ -621,7 +621,7 @@ typedef struct {
 **/
   UINT8                       IshGpGpioPadTermination[12];
 
-/** Offset 0x0220 - ISH UART Rx Pad termination
+/** Offset 0x0228 - ISH UART Rx Pad termination
   0x0: Hardware default, 0x1: None, 0x13: 1kOhm weak pull-up, 0x15: 5kOhm weak pull-up,
   0x19: 20kOhm weak pull-up - Enable/disable SerialIo UART#N Rx pads termination
   respectively. #N-byte for each controller, byte0 for UART0 Rx, byte1 for UART1
@@ -629,7 +629,7 @@ typedef struct {
 **/
   UINT8                       IshUartRxPadTermination[3];
 
-/** Offset 0x0223 - ISH UART Tx Pad termination
+/** Offset 0x022B - ISH UART Tx Pad termination
   0x0: Hardware default, 0x1: None, 0x13: 1kOhm weak pull-up, 0x15: 5kOhm weak pull-up,
   0x19: 20kOhm weak pull-up - Enable/disable SerialIo UART#N Tx pads termination
   respectively. #N-byte for each controller, byte0 for UART0 Tx, byte1 for UART1
@@ -637,7 +637,7 @@ typedef struct {
 **/
   UINT8                       IshUartTxPadTermination[3];
 
-/** Offset 0x0226 - ISH UART Rts Pad termination
+/** Offset 0x022E - ISH UART Rts Pad termination
   0x0: Hardware default, 0x1: None, 0x13: 1kOhm weak pull-up, 0x15: 5kOhm weak pull-up,
   0x19: 20kOhm weak pull-up - Enable/disable SerialIo UART#N Rts pads termination
   respectively. #N-byte for each controller, byte0 for UART0 Rts, byte1 for UART1
@@ -645,7 +645,7 @@ typedef struct {
 **/
   UINT8                       IshUartRtsPadTermination[3];
 
-/** Offset 0x0229 - ISH UART Rts Pad termination
+/** Offset 0x0231 - ISH UART Rts Pad termination
   0x0: Hardware default, 0x1: None, 0x13: 1kOhm weak pull-up, 0x15: 5kOhm weak pull-up,
   0x19: 20kOhm weak pull-up - Enable/disable SerialIo UART#N Cts pads termination
   respectively. #N-byte for each controller, byte0 for UART0 Cts, byte1 for UART1
@@ -653,7 +653,7 @@ typedef struct {
 **/
   UINT8                       IshUartCtsPadTermination[3];
 
-/** Offset 0x022C - ISH I2C SDA Pad termination
+/** Offset 0x0234 - ISH I2C SDA Pad termination
   0x0: Hardware default, 0x1: None, 0x13: 1kOhm weak pull-up, 0x15: 5kOhm weak pull-up,
   0x19: 20kOhm weak pull-up - Enable/disable SerialIo I2C#N Sda pads termination
   respectively. #N-byte for each controller, byte0 for I2C0 Sda, byte1 for I2C1 Sda,
@@ -661,7 +661,7 @@ typedef struct {
 **/
   UINT8                       IshI2cSdaPadTermination[3];
 
-/** Offset 0x022F - ISH I2C SCL Pad termination
+/** Offset 0x0237 - ISH I2C SCL Pad termination
   0x0: Hardware default, 0x1: None, 0x13: 1kOhm weak pull-up, 0x15: 5kOhm weak pull-up,
   0x19: 20kOhm weak pull-up - Enable/disable SerialIo I2C#N Scl pads termination
   respectively. #N-byte for each controller, byte0 for I2C0 Scl, byte1 for I2C1 Scl,
@@ -669,7 +669,7 @@ typedef struct {
 **/
   UINT8                       IshI2cSclPadTermination[3];
 
-/** Offset 0x0232 - ISH SPI MOSI Pad termination
+/** Offset 0x023A - ISH SPI MOSI Pad termination
   0x0: Hardware default, 0x1: None, 0x13: 1kOhm weak pull-up, 0x15: 5kOhm weak pull-up,
   0x19: 20kOhm weak pull-up - Enable/disable SerialIo SPI#N Mosi pads termination
   respectively. #N-byte for each controller, byte0 for SPI0 Mosi, byte1 for SPI1
@@ -677,7 +677,7 @@ typedef struct {
 **/
   UINT8                       IshSpiMosiPadTermination[2];
 
-/** Offset 0x0234 - ISH SPI MISO Pad termination
+/** Offset 0x023C - ISH SPI MISO Pad termination
   0x0: Hardware default, 0x1: None, 0x13: 1kOhm weak pull-up, 0x15: 5kOhm weak pull-up,
   0x19: 20kOhm weak pull-up - Enable/disable SerialIo SPI#N Miso pads termination
   respectively. #N-byte for each controller, byte0 for SPI0 Miso, byte1 for SPI1
@@ -685,7 +685,7 @@ typedef struct {
 **/
   UINT8                       IshSpiMisoPadTermination[2];
 
-/** Offset 0x0236 - ISH SPI CLK Pad termination
+/** Offset 0x023E - ISH SPI CLK Pad termination
   0x0: Hardware default, 0x1: None, 0x13: 1kOhm weak pull-up, 0x15: 5kOhm weak pull-up,
   0x19: 20kOhm weak pull-up - Enable/disable SerialIo SPI#N Clk pads termination
   respectively. #N-byte for each controller, byte0 for SPI0 Clk, byte1 for SPI1 Clk,
@@ -693,7 +693,7 @@ typedef struct {
 **/
   UINT8                       IshSpiClkPadTermination[2];
 
-/** Offset 0x0238 - ISH SPI CS#N Pad termination
+/** Offset 0x0240 - ISH SPI CS#N Pad termination
   0x0: Hardware default, 0x1: None, 0x13: 1kOhm weak pull-up, 0x15: 5kOhm weak pull-up,
   0x19: 20kOhm weak pull-up - Enable/disable SerialIo SPI#N Cs#M pads termination
   respectively. N*M-byte for each controller, byte0 for SPI0 Cs0, byte1 for SPI1
@@ -701,68 +701,68 @@ typedef struct {
 **/
   UINT8                       IshSpiCsPadTermination[4];
 
-/** Offset 0x023C - Enable PCH ISH SPI Cs#N pins assigned
+/** Offset 0x0244 - Enable PCH ISH SPI Cs#N pins assigned
   Set if ISH SPI Cs#N pins are to be enabled by BIOS. 0: Disable; 1: Enable. N-Cs
   number: 0-1
 **/
   UINT8                       PchIshSpiCsEnable[4];
 
-/** Offset 0x0240 - Enable PCH ISH SPI Cs0 pins assigned
+/** Offset 0x0248 - Enable PCH ISH SPI Cs0 pins assigned
   Set if ISH SPI Cs0 pins are to be enabled by BIOS. 0: Disable; 1: Enable.
 **/
   UINT8                       PchIshSpiCs0Enable[1];
 
-/** Offset 0x0241 - Enable PCH ISH SPI pins assigned
+/** Offset 0x0249 - Enable PCH ISH SPI pins assigned
   Set if ISH SPI native pins are to be enabled by BIOS. 0: Disable; 1: Enable.
 **/
   UINT8                       PchIshSpiEnable[1];
 
-/** Offset 0x0242 - Enable PCH ISH UART pins assigned
+/** Offset 0x024A - Enable PCH ISH UART pins assigned
   Set if ISH UART native pins are to be enabled by BIOS. 0: Disable; 1: Enable.
 **/
   UINT8                       PchIshUartEnable[2];
 
-/** Offset 0x0244 - Enable PCH ISH I2C pins assigned
+/** Offset 0x024C - Enable PCH ISH I2C pins assigned
   Set if ISH I2C native pins are to be enabled by BIOS. 0: Disable; 1: Enable.
 **/
   UINT8                       PchIshI2cEnable[3];
 
-/** Offset 0x0247 - Enable PCH ISH GP pins assigned
+/** Offset 0x024F - Enable PCH ISH GP pins assigned
   Set if ISH GP native pins are to be enabled by BIOS. 0: Disable; 1: Enable.
 **/
   UINT8                       PchIshGpEnable[12];
 
-/** Offset 0x0253 - PCH ISH PDT Unlock Msg
+/** Offset 0x025B - PCH ISH PDT Unlock Msg
   0: False; 1: True.
   $EN_DIS
 **/
   UINT8                       PchIshPdtUnlock;
 
-/** Offset 0x0254 - Reserved
+/** Offset 0x025C - Reserved
 **/
   UINT8                       Reserved16;
 
-/** Offset 0x0255 - End of Post message
+/** Offset 0x025D - End of Post message
   Test, Send End of Post message. Disable(0x0): Disable EOP message, Send in PEI(0x1):
   EOP send in PEI, Send in DXE(0x2)(Default): EOP send in DXE
   0:Disable, 1:Send in PEI, 2:Send in DXE, 3:Reserved
 **/
   UINT8                       EndOfPostMessage;
 
-/** Offset 0x0256 - D0I3 Setting for HECI Disable
+/** Offset 0x025E - D0I3 Setting for HECI Disable
   Test, 0: disable, 1: enable, Setting this option disables setting D0I3 bit for all
   HECI devices
   $EN_DIS
 **/
   UINT8                       DisableD0I3SettingForHeci;
 
-/** Offset 0x0257 - Mctp Broadcast Cycle
+/** Offset 0x025F - Mctp Broadcast Cycle
   Test, Determine if MCTP Broadcast is enabled <b>0: Disable</b>; 1: Enable.
   $EN_DIS
 **/
   UINT8                       MctpBroadcastCycle;
 
-/** Offset 0x0258 - ME Unconfig on RTC clear
+/** Offset 0x0260 - ME Unconfig on RTC clear
   0: Disable ME Unconfig On Rtc Clear. <b>1: Enable ME Unconfig On Rtc Clear</b>.
   2: Cmos is clear, status unkonwn. 3: Reserved
   0: Disable ME Unconfig On Rtc Clear, 1: Enable ME Unconfig On Rtc Clear, 2: Cmos
@@ -770,146 +770,146 @@ typedef struct {
 **/
   UINT8                       MeUnconfigOnRtcClear;
 
-/** Offset 0x0259 - Reserved
+/** Offset 0x0261 - Reserved
 **/
   UINT8                       Reserved17[22];
 
-/** Offset 0x026F - Enable PCH ISH I3C pins assigned
+/** Offset 0x0277 - Enable PCH ISH I3C pins assigned
   Set if ISH I3C native pins are to be enabled by BIOS. 0: Disable; 1: Enable.
 **/
   UINT8                       PchIshI3cEnable[2];
 
-/** Offset 0x0271 - Reserved
+/** Offset 0x0279 - Reserved
 **/
   UINT8                       Reserved18[3];
 
-/** Offset 0x0274 - Power button debounce configuration
+/** Offset 0x027C - Power button debounce configuration
   Debounce time for PWRBTN in microseconds. For values not supported by HW, they will
   be rounded down to closest supported on. 0: disable, 250-1024000us: supported range
 **/
   UINT32                      PmcPowerButtonDebounce;
 
-/** Offset 0x0278 - PCH USB2 PHY Power Gating enable
+/** Offset 0x0280 - PCH USB2 PHY Power Gating enable
   1: Will enable USB2 PHY SUS Well Power Gating, 0: Will not enable PG of USB2 PHY
   Sus Well PG
   $EN_DIS
 **/
   UINT8                       PmcUsb2PhySusPgEnable;
 
-/** Offset 0x0279 - VRAlert# Pin
+/** Offset 0x0281 - VRAlert# Pin
   When VRAlert# feature pin is enabled and its state is '0', the PMC requests throttling
   to a T3 Tstate to the PCH throttling unit.. 0: disable, 1: enable
   $EN_DIS
 **/
   UINT8                       PchPmVrAlert;
 
-/** Offset 0x027A - ModPHY SUS Power Domain Dynamic Gating
+/** Offset 0x0282 - ModPHY SUS Power Domain Dynamic Gating
   Enable/Disable ModPHY SUS Power Domain Dynamic Gating. Setting not supported on
   PCH-H. 0: disable, 1: enable
   $EN_DIS
 **/
   UINT8                       PmcModPhySusPgEnable;
 
-/** Offset 0x027B - V1p05-PHY supply external FET control
+/** Offset 0x0283 - V1p05-PHY supply external FET control
   Enable/Disable control using EXT_PWR_GATE# pin of external FET to power gate v1p05-PHY
   supply. 0: disable, 1: enable
   $EN_DIS
 **/
   UINT8                       PmcV1p05PhyExtFetControlEn;
 
-/** Offset 0x027C - V1p05-IS supply external FET control
+/** Offset 0x0284 - V1p05-IS supply external FET control
   Enable/Disable control using EXT_PWR_GATE2# pin of external FET to power gate v1p05-IS
   supply. 0: disable, 1: enable
   $EN_DIS
 **/
   UINT8                       PmcV1p05IsExtFetControlEn;
 
-/** Offset 0x027D - PCH Pm PME_B0_S5_DIS
+/** Offset 0x0285 - PCH Pm PME_B0_S5_DIS
   When cleared (default), wake events from PME_B0_STS are allowed in S5 if PME_B0_EN = 1.
   $EN_DIS
 **/
   UINT8                       PchPmPmeB0S5Dis;
 
-/** Offset 0x027E - PCH Pm Wol Enable Override
+/** Offset 0x0286 - PCH Pm Wol Enable Override
   Corresponds to the WOL Enable Override bit in the General PM Configuration B (GEN_PMCON_B) register.
   $EN_DIS
 **/
   UINT8                       PchPmWolEnableOverride;
 
-/** Offset 0x027F - PCH Pm WoW lan Enable
+/** Offset 0x0287 - PCH Pm WoW lan Enable
   Determine if WLAN wake from Sx, corresponds to the HOST_WLAN_PP_EN bit in the PWRM_CFG3 register.
   $EN_DIS
 **/
   UINT8                       PchPmWoWlanEnable;
 
-/** Offset 0x0280 - PCH Pm Slp S3 Min Assert
+/** Offset 0x0288 - PCH Pm Slp S3 Min Assert
   SLP_S3 Minimum Assertion Width Policy. Default is PchSlpS350ms.
 **/
   UINT8                       PchPmSlpS3MinAssert;
 
-/** Offset 0x0281 - PCH Pm Slp S4 Min Assert
+/** Offset 0x0289 - PCH Pm Slp S4 Min Assert
   SLP_S4 Minimum Assertion Width Policy. Default is PchSlpS44s.
 **/
   UINT8                       PchPmSlpS4MinAssert;
 
-/** Offset 0x0282 - PCH Pm Slp Sus Min Assert
+/** Offset 0x028A - PCH Pm Slp Sus Min Assert
   SLP_SUS Minimum Assertion Width Policy. Default is PchSlpSus4s.
 **/
   UINT8                       PchPmSlpSusMinAssert;
 
-/** Offset 0x0283 - PCH Pm Slp A Min Assert
+/** Offset 0x028B - PCH Pm Slp A Min Assert
   SLP_A Minimum Assertion Width Policy. Default is PchSlpA2s.
 **/
   UINT8                       PchPmSlpAMinAssert;
 
-/** Offset 0x0284 - PCH Pm Slp Strch Sus Up
+/** Offset 0x028C - PCH Pm Slp Strch Sus Up
   Enable SLP_X Stretching After SUS Well Power Up.
   $EN_DIS
 **/
   UINT8                       PchPmSlpStrchSusUp;
 
-/** Offset 0x0285 - PCH Pm Slp Lan Low Dc
+/** Offset 0x028D - PCH Pm Slp Lan Low Dc
   Enable/Disable SLP_LAN# Low on DC Power.
   $EN_DIS
 **/
   UINT8                       PchPmSlpLanLowDc;
 
-/** Offset 0x0286 - PCH Pm Pwr Btn Override Period
+/** Offset 0x028E - PCH Pm Pwr Btn Override Period
   PCH power button override period. 000b-4s, 001b-6s, 010b-8s, 011b-10s, 100b-12s, 101b-14s.
 **/
   UINT8                       PchPmPwrBtnOverridePeriod;
 
-/** Offset 0x0287 - PCH Pm Disable Native Power Button
+/** Offset 0x028F - PCH Pm Disable Native Power Button
   Power button native mode disable.
   $EN_DIS
 **/
   UINT8                       PchPmDisableNativePowerButton;
 
-/** Offset 0x0288 - PCH Pm ME_WAKE_STS
+/** Offset 0x0290 - PCH Pm ME_WAKE_STS
   Clear the ME_WAKE_STS bit in the Power and Reset Status (PRSTS) register.
   $EN_DIS
 **/
   UINT8                       PchPmMeWakeSts;
 
-/** Offset 0x0289 - PCH Pm WOL_OVR_WK_STS
+/** Offset 0x0291 - PCH Pm WOL_OVR_WK_STS
   Clear the WOL_OVR_WK_STS bit in the Power and Reset Status (PRSTS) register.
   $EN_DIS
 **/
   UINT8                       PchPmWolOvrWkSts;
 
-/** Offset 0x028A - PCH Pm Reset Power Cycle Duration
+/** Offset 0x0292 - PCH Pm Reset Power Cycle Duration
   Could be customized in the unit of second. Please refer to EDS for all support settings.
   0 is default, 1 is 1 second, 2 is 2 seconds, ...
 **/
   UINT8                       PchPmPwrCycDur;
 
-/** Offset 0x028B - PCH Pm Pcie Pll Ssc
+/** Offset 0x0293 - PCH Pm Pcie Pll Ssc
   Specifies the Pcie Pll Spread Spectrum Percentage. The default is 0xFF: AUTO - No
   BIOS override.
 **/
   UINT8                       PchPmPciePllSsc;
 
-/** Offset 0x028C - Enable TCO timer.
+/** Offset 0x0294 - Enable TCO timer.
   When FALSE, it disables PCH ACPI timer, and stops TCO timer. NOTE: This will have
   huge power impact when it's enabled. If TCO timer is disabled, uCode ACPI timer
   emulation must be enabled, and WDAT table must not be exposed to the OS.
@@ -917,7 +917,7 @@ typedef struct {
 **/
   UINT8                       EnableTcoTimer;
 
-/** Offset 0x028D - Enable PS_ON.
+/** Offset 0x0295 - Enable PS_ON.
   PS_ON is a new C10 state from the CPU on desktop SKUs that enables a lower power
   target that will be required by the California Energy Commission (CEC). When FALSE,
   PS_ON is to be disabled.
@@ -925,1290 +925,1290 @@ typedef struct {
 **/
   UINT8                       PsOnEnable;
 
-/** Offset 0x028E - Pmc Cpu C10 Gate Pin Enable
+/** Offset 0x0296 - Pmc Cpu C10 Gate Pin Enable
   Enable/Disable platform support for CPU_C10_GATE# pin to control gating of CPU VccIO
   and VccSTG rails instead of SLP_S0# pin.
   $EN_DIS
 **/
   UINT8                       PmcCpuC10GatePinEnable;
 
-/** Offset 0x028F - OS IDLE Mode Enable
+/** Offset 0x0297 - OS IDLE Mode Enable
   Enable/Disable OS Idle Mode
   $EN_DIS
 **/
   UINT8                       PmcOsIdleEnable;
 
-/** Offset 0x0290 - S0ix Auto-Demotion
+/** Offset 0x0298 - S0ix Auto-Demotion
   Enable/Disable the Low Power Mode Auto-Demotion Host Control feature.
   $EN_DIS
 **/
   UINT8                       PchS0ixAutoDemotion;
 
-/** Offset 0x0291 - Latch Events C10 Exit
+/** Offset 0x0299 - Latch Events C10 Exit
   When this bit is set to 1, SLP_S0# entry events in SLP_S0_DEBUG_REGx registers are
   captured on C10 exit (instead of C10 entry which is default)
   $EN_DIS
 **/
   UINT8                       PchPmLatchEventsC10Exit;
 
-/** Offset 0x0292 - PCH Energy Reporting
+/** Offset 0x029A - PCH Energy Reporting
   Disable/Enable PCH to CPU energy report feature.
   $EN_DIS
 **/
   UINT8                       PchPmDisableEnergyReport;
 
-/** Offset 0x0293 - Low Power Mode Enable/Disable config mask
+/** Offset 0x029B - Low Power Mode Enable/Disable config mask
   Configure if respective S0i2/3 sub-states are to be supported. Each bit corresponds
   to one sub-state (LPMx - BITx): LPM0-s0i2.0, LPM1-s0i2.1, LPM2-s0i2.2, LPM3-s0i3.0,
   LPM4-s0i3.1, LPM5-s0i3.2, LPM6-s0i3.3, LPM7-s0i3.4.
 **/
   UINT8                       PmcLpmS0ixSubStateEnableMask;
 
-/** Offset 0x0294 - Reserved
+/** Offset 0x029C - Reserved
 **/
   UINT8                       Reserved19;
 
-/** Offset 0x0295 - PMC C10 dynamic threshold dajustment enable
+/** Offset 0x029D - PMC C10 dynamic threshold dajustment enable
   Set if you want to enable PMC C10 dynamic threshold adjustment. Only works on supported SKUs
   $EN_DIS
 **/
   UINT8                       PmcC10DynamicThresholdAdjustment;
 
-/** Offset 0x0296 - Enable LOCKDOWN BIOS LOCK
+/** Offset 0x029E - Enable LOCKDOWN BIOS LOCK
   Enable the BIOS Lock feature and set EISS bit (D31:F5:RegDCh[5]) for the BIOS region
   protection.
   $EN_DIS
 **/
   UINT8                       PchLockDownBiosLock;
 
-/** Offset 0x0297 - Enable LOCKDOWN SMI
+/** Offset 0x029F - Enable LOCKDOWN SMI
   Enable SMI_LOCK bit to prevent writes to the Global SMI Enable bit.
   $EN_DIS
 **/
   UINT8                       PchLockDownGlobalSmi;
 
-/** Offset 0x0298 - Enable LOCKDOWN BIOS Interface
+/** Offset 0x02A0 - Enable LOCKDOWN BIOS Interface
   Enable BIOS Interface Lock Down bit to prevent writes to the Backup Control Register.
   $EN_DIS
 **/
   UINT8                       PchLockDownBiosInterface;
 
-/** Offset 0x0299 - Unlock all GPIO pads
+/** Offset 0x02A1 - Unlock all GPIO pads
   Force all GPIO pads to be unlocked for debug purpose.
   $EN_DIS
 **/
   UINT8                       PchUnlockGpioPads;
 
-/** Offset 0x029A - PCH Flash Protection Ranges Write Enble
+/** Offset 0x02A2 - PCH Flash Protection Ranges Write Enble
   Write or erase is blocked by hardware.
 **/
   UINT8                       PchWriteProtectionEnable[5];
 
-/** Offset 0x029F - PCH Flash Protection Ranges Read Enble
+/** Offset 0x02A7 - PCH Flash Protection Ranges Read Enble
   Read is blocked by hardware.
 **/
   UINT8                       PchReadProtectionEnable[5];
 
-/** Offset 0x02A4 - PCH Protect Range Limit
+/** Offset 0x02AC - PCH Protect Range Limit
   Left shifted address by 12 bits with address bits 11:0 are assumed to be FFFh for
   limit comparison.
 **/
   UINT16                      PchProtectedRangeLimit[5];
 
-/** Offset 0x02AE - PCH Protect Range Base
+/** Offset 0x02B6 - PCH Protect Range Base
   Left shifted address by 12 bits with address bits 11:0 are assumed to be 0.
 **/
   UINT16                      PchProtectedRangeBase[5];
 
-/** Offset 0x02B8 - PCIe PTM enable/disable
+/** Offset 0x02C0 - PCIe PTM enable/disable
   Enable/disable Precision Time Measurement for PCIE Root Ports.
 **/
   UINT8                       PciePtm[28];
 
-/** Offset 0x02D4 - PCH PCIe root port connection type
+/** Offset 0x02DC - PCH PCIe root port connection type
   0: built-in device, 1:slot
 **/
   UINT8                       PcieRpSlotImplemented[28];
 
-/** Offset 0x02F0 - PCIE RP Access Control Services Extended Capability
+/** Offset 0x02F8 - PCIE RP Access Control Services Extended Capability
   Enable/Disable PCIE RP Access Control Services Extended Capability
 **/
   UINT8                       PcieRpAcsEnabled[28];
 
-/** Offset 0x030C - PCIE RP Clock Power Management
+/** Offset 0x0314 - PCIE RP Clock Power Management
   Enable/Disable PCIE RP Clock Power Management, even if disabled, CLKREQ# signal
   can still be controlled by L1 PM substates mechanism
 **/
   UINT8                       PcieRpEnableCpm[28];
 
-/** Offset 0x0328 - PCIE RP Detect Timeout Ms
+/** Offset 0x0330 - PCIE RP Detect Timeout Ms
   The number of milliseconds within 0~65535 in reference code will wait for link to
   exit Detect state for enabled ports before assuming there is no device and potentially
   disabling the port.
 **/
   UINT16                      PcieRpDetectTimeoutMs[24];
 
-/** Offset 0x0358 - Enable PCIE RP HotPlug
+/** Offset 0x0360 - Enable PCIE RP HotPlug
   Indicate whether the root port is hot plug available.
 **/
   UINT8                       PcieRpHotPlug[28];
 
-/** Offset 0x0374 - Enable PCIE RP Pm Sci
+/** Offset 0x037C - Enable PCIE RP Pm Sci
   Indicate whether the root port power manager SCI is enabled.
 **/
   UINT8                       PcieRpPmSci[28];
 
-/** Offset 0x0390 - Enable PCIE RP Transmitter Half Swing
+/** Offset 0x0398 - Enable PCIE RP Transmitter Half Swing
   Indicate whether the Transmitter Half Swing is enabled.
 **/
   UINT8                       PcieRpTransmitterHalfSwing[28];
 
-/** Offset 0x03AC - Enable PCIE RP Clk Req Detect
+/** Offset 0x03B4 - Enable PCIE RP Clk Req Detect
   Probe CLKREQ# signal before enabling CLKREQ# based power management.
 **/
   UINT8                       PcieRpClkReqDetect[28];
 
-/** Offset 0x03C8 - PCIE RP Advanced Error Report
+/** Offset 0x03D0 - PCIE RP Advanced Error Report
   Indicate whether the Advanced Error Reporting is enabled.
 **/
   UINT8                       PcieRpAdvancedErrorReporting[28];
 
-/** Offset 0x03E4 - PCIE RP Unsupported Request Report
+/** Offset 0x03EC - PCIE RP Unsupported Request Report
   Indicate whether the Unsupported Request Report is enabled.
 **/
   UINT8                       PcieRpUnsupportedRequestReport[28];
 
-/** Offset 0x0400 - PCIE RP Fatal Error Report
+/** Offset 0x0408 - PCIE RP Fatal Error Report
   Indicate whether the Fatal Error Report is enabled.
 **/
   UINT8                       PcieRpFatalErrorReport[28];
 
-/** Offset 0x041C - PCIE RP No Fatal Error Report
+/** Offset 0x0424 - PCIE RP No Fatal Error Report
   Indicate whether the No Fatal Error Report is enabled.
 **/
   UINT8                       PcieRpNoFatalErrorReport[28];
 
-/** Offset 0x0438 - PCIE RP Correctable Error Report
+/** Offset 0x0440 - PCIE RP Correctable Error Report
   Indicate whether the Correctable Error Report is enabled.
 **/
   UINT8                       PcieRpCorrectableErrorReport[28];
 
-/** Offset 0x0454 - PCIE RP System Error On Fatal Error
+/** Offset 0x045C - PCIE RP System Error On Fatal Error
   Indicate whether the System Error on Fatal Error is enabled.
 **/
   UINT8                       PcieRpSystemErrorOnFatalError[28];
 
-/** Offset 0x0470 - PCIE RP System Error On Non Fatal Error
+/** Offset 0x0478 - PCIE RP System Error On Non Fatal Error
   Indicate whether the System Error on Non Fatal Error is enabled.
 **/
   UINT8                       PcieRpSystemErrorOnNonFatalError[28];
 
-/** Offset 0x048C - PCIE RP System Error On Correctable Error
+/** Offset 0x0494 - PCIE RP System Error On Correctable Error
   Indicate whether the System Error on Correctable Error is enabled.
 **/
   UINT8                       PcieRpSystemErrorOnCorrectableError[28];
 
-/** Offset 0x04A8 - PCIE RP Max Payload
+/** Offset 0x04B0 - PCIE RP Max Payload
   Max Payload Size supported, Default 256B, see enum PCH_PCIE_MAX_PAYLOAD.
 **/
   UINT8                       PcieRpMaxPayload[28];
 
-/** Offset 0x04C4 - PCIE RP Pcie Speed
+/** Offset 0x04CC - PCIE RP Pcie Speed
   Determines each PCIE Port speed capability. 0: Auto; 1: Gen1; 2: Gen2; 3: Gen3 (see:
   PCIE_SPEED).
 **/
   UINT8                       PcieRpPcieSpeed[28];
 
-/** Offset 0x04E0 - PCIE RP Physical Slot Number
+/** Offset 0x04E8 - PCIE RP Physical Slot Number
   Indicates the slot number for the root port. Default is the value as root port index.
 **/
   UINT8                       PcieRpPhysicalSlotNumber[28];
 
-/** Offset 0x04FC - PCIE RP Completion Timeout
+/** Offset 0x0504 - PCIE RP Completion Timeout
   The root port completion timeout(see: PCIE_COMPLETION_TIMEOUT). Default is PchPcieCompletionTO_Default.
 **/
   UINT8                       PcieRpCompletionTimeout[28];
 
-/** Offset 0x0518 - PCIE RP Aspm
+/** Offset 0x0520 - PCIE RP Aspm
   The ASPM configuration of the root port (see: PCH_PCIE_ASPM_CONTROL). Default is
   PchPcieAspmAutoConfig.
 **/
   UINT8                       PcieRpAspm[28];
 
-/** Offset 0x0534 - Reserved
+/** Offset 0x053C - Reserved
 **/
   UINT8                       Reserved20[28];
 
-/** Offset 0x0550 - PCIE RP L1 Substates
+/** Offset 0x0558 - PCIE RP L1 Substates
   The L1 Substates configuration of the root port (see: PCH_PCIE_L1SUBSTATES_CONTROL).
   Default is PchPcieL1SubstatesL1_1_2.
 **/
   UINT8                       PcieRpL1Substates[28];
 
-/** Offset 0x056C - PCIE RP Ltr Enable
+/** Offset 0x0574 - PCIE RP Ltr Enable
   Latency Tolerance Reporting Mechanism.
 **/
   UINT8                       PcieRpLtrEnable[28];
 
-/** Offset 0x0588 - PCIE RP Ltr Config Lock
+/** Offset 0x0590 - PCIE RP Ltr Config Lock
   0: Disable; 1: Enable.
 **/
   UINT8                       PcieRpLtrConfigLock[28];
 
-/** Offset 0x05A4 - PCIE RP override default settings for EQ
+/** Offset 0x05AC - PCIE RP override default settings for EQ
   Choose PCIe EQ method
   $EN_DIS
 **/
   UINT8                       PcieEqOverrideDefault[12];
 
-/** Offset 0x05B0 - Reserved
+/** Offset 0x05B8 - Reserved
 **/
   UINT8                       Reserved21[1525];
 
-/** Offset 0x0BA5 - PCIE RP Enable Peer Memory Write
+/** Offset 0x0BAD - PCIE RP Enable Peer Memory Write
   This member describes whether Peer Memory Writes are enabled on the platform.
   $EN_DIS
 **/
   UINT8                       PcieEnablePeerMemoryWrite[12];
 
-/** Offset 0x0BB1 - Assertion on Link Down GPIOs
+/** Offset 0x0BB9 - Assertion on Link Down GPIOs
   GPIO Assertion on Link Down. Disabled(0x0)(Default): Disable assertion on Link Down
   GPIOs, Enabled(0x1): Enable assertion on Link Down GPIOs
   0:Disable, 1:Enable
 **/
   UINT8                       PcieRpLinkDownGpios[12];
 
-/** Offset 0x0BBD - PCIE Compliance Test Mode
+/** Offset 0x0BC5 - PCIE Compliance Test Mode
   Compliance Test Mode shall be enabled when using Compliance Load Board.
   $EN_DIS
 **/
   UINT8                       PcieComplianceTestMode;
 
-/** Offset 0x0BBE - PCIE Rp Function Swap
+/** Offset 0x0BC6 - PCIE Rp Function Swap
   Allows BIOS to use root port function number swapping when root port of function
   0 is disabled.
   $EN_DIS
 **/
   UINT8                       PcieRpFunctionSwap;
 
-/** Offset 0x0BBF - Reserved
+/** Offset 0x0BC7 - Reserved
 **/
   UINT8                       Reserved22[12];
 
-/** Offset 0x0BCB - PCIe RootPort Power Gating
+/** Offset 0x0BD3 - PCIe RootPort Power Gating
   Describes whether the PCI Express Power Gating for each root port is enabled by
   platform modules. 0: Disable; 1: Enable(Default).
   $EN_DIS
 **/
   UINT8                       PciePowerGating[12];
 
-/** Offset 0x0BD7 - Reserved
+/** Offset 0x0BDF - Reserved
 **/
   UINT8                       Reserved23[49];
 
-/** Offset 0x0C08 - PCIE RP Ltr Max Snoop Latency
+/** Offset 0x0C10 - PCIE RP Ltr Max Snoop Latency
   Latency Tolerance Reporting, Max Snoop Latency.
 **/
   UINT16                      PcieRpLtrMaxSnoopLatency[24];
 
-/** Offset 0x0C38 - PCIE RP Ltr Max No Snoop Latency
+/** Offset 0x0C40 - PCIE RP Ltr Max No Snoop Latency
   Latency Tolerance Reporting, Max Non-Snoop Latency.
 **/
   UINT16                      PcieRpLtrMaxNoSnoopLatency[24];
 
-/** Offset 0x0C68 - PCIE RP Snoop Latency Override Mode
+/** Offset 0x0C70 - PCIE RP Snoop Latency Override Mode
   Latency Tolerance Reporting, Snoop Latency Override Mode.
 **/
   UINT8                       PcieRpSnoopLatencyOverrideMode[28];
 
-/** Offset 0x0C84 - PCIE RP Snoop Latency Override Multiplier
+/** Offset 0x0C8C - PCIE RP Snoop Latency Override Multiplier
   Latency Tolerance Reporting, Snoop Latency Override Multiplier.
 **/
   UINT8                       PcieRpSnoopLatencyOverrideMultiplier[28];
 
-/** Offset 0x0CA0 - PCIE RP Snoop Latency Override Value
+/** Offset 0x0CA8 - PCIE RP Snoop Latency Override Value
   Latency Tolerance Reporting, Snoop Latency Override Value.
 **/
   UINT16                      PcieRpSnoopLatencyOverrideValue[24];
 
-/** Offset 0x0CD0 - PCIE RP Non Snoop Latency Override Mode
+/** Offset 0x0CD8 - PCIE RP Non Snoop Latency Override Mode
   Latency Tolerance Reporting, Non-Snoop Latency Override Mode.
 **/
   UINT8                       PcieRpNonSnoopLatencyOverrideMode[28];
 
-/** Offset 0x0CEC - PCIE RP Non Snoop Latency Override Multiplier
+/** Offset 0x0CF4 - PCIE RP Non Snoop Latency Override Multiplier
   Latency Tolerance Reporting, Non-Snoop Latency Override Multiplier.
 **/
   UINT8                       PcieRpNonSnoopLatencyOverrideMultiplier[28];
 
-/** Offset 0x0D08 - PCIE RP Non Snoop Latency Override Value
+/** Offset 0x0D10 - PCIE RP Non Snoop Latency Override Value
   Latency Tolerance Reporting, Non-Snoop Latency Override Value.
 **/
   UINT16                      PcieRpNonSnoopLatencyOverrideValue[24];
 
-/** Offset 0x0D38 - PCIE RP Slot Power Limit Scale
+/** Offset 0x0D40 - PCIE RP Slot Power Limit Scale
   Specifies scale used for slot power limit value. Leave as 0 to set to default.
 **/
   UINT8                       PcieRpSlotPowerLimitScale[28];
 
-/** Offset 0x0D54 - PCIE RP Slot Power Limit Value
+/** Offset 0x0D5C - PCIE RP Slot Power Limit Value
   Specifies upper limit on power supplie by slot. Leave as 0 to set to default.
 **/
   UINT16                      PcieRpSlotPowerLimitValue[24];
 
-/** Offset 0x0D84 - PCIE RP Enable Port8xh Decode
+/** Offset 0x0D8C - PCIE RP Enable Port8xh Decode
   This member describes whether PCIE root port Port 8xh Decode is enabled. 0: Disable;
   1: Enable.
   $EN_DIS
 **/
   UINT8                       PcieEnablePort8xhDecode;
 
-/** Offset 0x0D85 - PCIE Port8xh Decode Port Index
+/** Offset 0x0D8D - PCIE Port8xh Decode Port Index
   The Index of PCIe Port that is selected for Port8xh Decode (1 Based).
 **/
   UINT8                       PchPciePort8xhDecodePortIndex;
 
-/** Offset 0x0D86 - Reserved
+/** Offset 0x0D8E - Reserved
 **/
   UINT8                       Reserved24[114];
 
-/** Offset 0x0DF8 - SPIn Device Mode
+/** Offset 0x0E00 - SPIn Device Mode
   Selects SPI operation mode. N represents controller index: SPI0, SPI1, ... Available
   modes: 0:LpssSpiDisabled, 1:LpssSpiPci, 2:LpssSpiHidden
 **/
   UINT8                       SerialIoLpssSpiMode[7];
 
-/** Offset 0x0DFF - Reserved
+/** Offset 0x0E07 - Reserved
 **/
   UINT8                       Reserved25[85];
 
-/** Offset 0x0E54 - SPIn Default Chip Select Mode HW/SW
+/** Offset 0x0E5C - SPIn Default Chip Select Mode HW/SW
   Sets Default CS Mode Hardware or Software. N represents controller index: SPI0,
   SPI1, ... Available options: 0:HW, 1:SW
 **/
   UINT8                       SerialIoLpssSpiCsMode[7];
 
-/** Offset 0x0E5B - SPIn Default Chip Select State Low/High
+/** Offset 0x0E63 - SPIn Default Chip Select State Low/High
   Sets Default CS State Low or High. N represents controller index: SPI0, SPI1, ...
   Available options: 0:Low, 1:High
 **/
   UINT8                       SerialIoLpssSpiCsState[7];
 
-/** Offset 0x0E62 - UARTn Device Mode
+/** Offset 0x0E6A - UARTn Device Mode
   Selects Uart operation mode. N represents controller index: Uart0, Uart1, ... Available
   modes: 0:SerialIoUartDisabled, 1:SerialIoUartPci, 2:SerialIoUartHidden, 3:SerialIoUartCom,
   4:SerialIoUartSkipInit
 **/
   UINT8                       SerialIoUartMode[7];
 
-/** Offset 0x0E69 - Reserved
+/** Offset 0x0E71 - Reserved
 **/
   UINT8                       Reserved26[3];
 
-/** Offset 0x0E6C - Default BaudRate for each Serial IO UART
+/** Offset 0x0E74 - Default BaudRate for each Serial IO UART
   Set default BaudRate Supported from 0 - default to 6000000
 **/
   UINT32                      SerialIoUartBaudRate[7];
 
-/** Offset 0x0E88 - Default ParityType for each Serial IO UART
+/** Offset 0x0E90 - Default ParityType for each Serial IO UART
   Set default Parity. 0: DefaultParity, 1: NoParity, 2: EvenParity, 3: OddParity
 **/
   UINT8                       SerialIoUartParity[7];
 
-/** Offset 0x0E8F - Default DataBits for each Serial IO UART
+/** Offset 0x0E97 - Default DataBits for each Serial IO UART
   Set default word length. 0: Default, 5,6,7,8
 **/
   UINT8                       SerialIoUartDataBits[7];
 
-/** Offset 0x0E96 - Default StopBits for each Serial IO UART
+/** Offset 0x0E9E - Default StopBits for each Serial IO UART
   Set default stop bits. 0: DefaultStopBits, 1: OneStopBit, 2: OneFiveStopBits, 3:
   TwoStopBits
 **/
   UINT8                       SerialIoUartStopBits[7];
 
-/** Offset 0x0E9D - Power Gating mode for each Serial IO UART that works in COM mode
+/** Offset 0x0EA5 - Power Gating mode for each Serial IO UART that works in COM mode
   Set Power Gating. 0: Disabled, 1: Enabled, 2: Auto
 **/
   UINT8                       SerialIoUartPowerGating[7];
 
-/** Offset 0x0EA4 - Enable Dma for each Serial IO UART that supports it
+/** Offset 0x0EAC - Enable Dma for each Serial IO UART that supports it
   Set DMA/PIO mode. 0: Disabled, 1: Enabled
 **/
   UINT8                       SerialIoUartDmaEnable[7];
 
-/** Offset 0x0EAB - Enables UART hardware flow control, CTS and RTS lines
+/** Offset 0x0EB3 - Enables UART hardware flow control, CTS and RTS lines
   Enables UART hardware flow control, CTS and RTS lines.
 **/
   UINT8                       SerialIoUartAutoFlow[7];
 
-/** Offset 0x0EB2 - Reserved
+/** Offset 0x0EBA - Reserved
 **/
   UINT8                       Reserved27[2];
 
-/** Offset 0x0EB4 - SerialIoUartRtsPinMuxPolicy
+/** Offset 0x0EBC - SerialIoUartRtsPinMuxPolicy
   Select SerialIo Uart Rts pin muxing. Refer to GPIO_*_MUXING_SERIALIO_UARTx_RTS*
   for possible values.
 **/
   UINT32                      SerialIoUartRtsPinMuxPolicy[7];
 
-/** Offset 0x0ED0 - SerialIoUartRxPinMuxPolicy
+/** Offset 0x0ED8 - SerialIoUartRxPinMuxPolicy
   Select SerialIo Uart Rx pin muxing. Refer to GPIO_*_MUXING_SERIALIO_UARTx_RX* for
   possible values.
 **/
   UINT32                      SerialIoUartRxPinMuxPolicy[7];
 
-/** Offset 0x0EEC - SerialIoUartTxPinMuxPolicy
+/** Offset 0x0EF4 - SerialIoUartTxPinMuxPolicy
   Select SerialIo Uart Tx pin muxing. Refer to GPIO_*_MUXING_SERIALIO_UARTx_TX* for
   possible values.
 **/
   UINT32                      SerialIoUartTxPinMuxPolicy[7];
 
-/** Offset 0x0F08 - Serial IO UART DBG2 table
+/** Offset 0x0F10 - Serial IO UART DBG2 table
   Enable or disable Serial Io UART DBG2 table, default is Disable; <b>0: Disable;</b>
   1: Enable.
 **/
   UINT8                       SerialIoUartDbg2[7];
 
-/** Offset 0x0F0F - Reserved
+/** Offset 0x0F17 - Reserved
 **/
   UINT8                       Reserved28[7];
 
-/** Offset 0x0F16 - I2Cn Device Mode
+/** Offset 0x0F1E - I2Cn Device Mode
   Selects I2c operation mode. N represents controller index: I2c0, I2c1, ... Available
   modes: 0:SerialIoI2cDisabled, 1:SerialIoI2cPci, 2:SerialIoI2cHidden
 **/
   UINT8                       SerialIoI2cMode[8];
 
-/** Offset 0x0F1E - Reserved
+/** Offset 0x0F26 - Reserved
 **/
   UINT8                       Reserved29[2];
 
-/** Offset 0x0F20 - Serial IO I2C SDA Pin Muxing
+/** Offset 0x0F28 - Serial IO I2C SDA Pin Muxing
   Select SerialIo I2c Sda pin muxing. Refer to GPIO_*_MUXING_SERIALIO_I2Cx_SDA* for
   possible values.
 **/
   UINT32                      PchSerialIoI2cSdaPinMux[8];
 
-/** Offset 0x0F40 - Serial IO I2C SCL Pin Muxing
+/** Offset 0x0F48 - Serial IO I2C SCL Pin Muxing
   Select SerialIo I2c Scl pin muxing. Refer to GPIO_*_MUXING_SERIALIO_I2Cx_SCL* for
   possible values.
 **/
   UINT32                      PchSerialIoI2cSclPinMux[8];
 
-/** Offset 0x0F60 - PCH SerialIo I2C Pads Termination
+/** Offset 0x0F68 - PCH SerialIo I2C Pads Termination
   0x0: Hardware default, 0x1: None, 0x13: 1kOhm weak pull-up, 0x15: 5kOhm weak pull-up,
   0x19: 20kOhm weak pull-up - Enable/disable SerialIo I2C0,I2C1,... pads termination
   respectively. One byte for each controller, byte0 for I2C0, byte1 for I2C1, and so on.
 **/
   UINT8                       PchSerialIoI2cPadsTermination[8];
 
-/** Offset 0x0F68 - I3C Device Mode
+/** Offset 0x0F70 - I3C Device Mode
   Selects I3c operation mode. Available modes: 0:SerialIoI3cDisabled, 1:SerialIoI3cPci,
   2:SerialIoI3cPhantom (only applicable to I3C1, controlls GPIO enabling)
 **/
   UINT8                       SerialIoI3cMode[3];
 
-/** Offset 0x0F6B - Reserved
+/** Offset 0x0F73 - Reserved
 **/
   UINT8                       Reserved30[48];
 
-/** Offset 0x0F9B - Enable VMD controller
+/** Offset 0x0FA3 - Enable VMD controller
   Enable/disable to VMD controller.0: Disable; 1: Enable(Default)
   $EN_DIS
 **/
   UINT8                       VmdEnable;
 
-/** Offset 0x0F9C - Enable VMD Global Mapping
+/** Offset 0x0FA4 - Enable VMD Global Mapping
   Enable/disable to VMD controller.0: Disable(Default); 1: Enable
   $EN_DIS
 **/
   UINT8                       VmdGlobalMapping;
 
-/** Offset 0x0F9D - Map port under VMD
+/** Offset 0x0FA5 - Map port under VMD
   Map/UnMap port under VMD
   $EN_DIS
 **/
   UINT8                       VmdPort[31];
 
-/** Offset 0x0FBC - Reserved
+/** Offset 0x0FC4 - Reserved
 **/
   UINT8                       Reserved31[31];
 
-/** Offset 0x0FDB - VMD Port Device
+/** Offset 0x0FE3 - VMD Port Device
   VMD Root port device number.
 **/
   UINT8                       VmdPortDev[31];
 
-/** Offset 0x0FFA - VMD Port Func
+/** Offset 0x1002 - VMD Port Func
   VMD Root port function number.
 **/
   UINT8                       VmdPortFunc[31];
 
-/** Offset 0x1019 - Reserved
+/** Offset 0x1021 - Reserved
 **/
   UINT8                       Reserved32[7];
 
-/** Offset 0x1020 - VMD Variable
+/** Offset 0x1028 - VMD Variable
   VMD Variable Pointer.
 **/
   UINT64                      VmdVariablePtr;
 
-/** Offset 0x1028 - Reserved
+/** Offset 0x1030 - Reserved
 **/
   UINT8                      Reserved33[4];
 
-/** Offset 0x102C - Temporary MemBar1 address for VMD
+/** Offset 0x1034 - Temporary MemBar1 address for VMD
   VMD Variable Pointer.
 **/
   UINT32                      VmdMemBar1Base;
 
-/** Offset 0x1030 - Temporary MemBar2 address for VMD
+/** Offset 0x1038 - Temporary MemBar2 address for VMD
   VMD Variable Pointer.
 **/
   UINT32                      VmdMemBar2Base;
 
-/** Offset 0x1034 - Enable D3 Hot in TCSS
+/** Offset 0x103C - Enable D3 Hot in TCSS
   This policy will enable/disable D3 hot support in IOM
   $EN_DIS
 **/
   UINT8                       D3HotEnable;
 
-/** Offset 0x1035 - Reserved
+/** Offset 0x103D - Reserved
 **/
   UINT8                       Reserved34[3];
 
-/** Offset 0x1038 - TypeC port GPIO setting
+/** Offset 0x1040 - TypeC port GPIO setting
   GPIO Ping number for Type C Aux orientation setting, use the GpioPad that is defined
   in GpioPinsXXXH.h and GpioPinsXXXLp.h as argument.(XXX is platform name, Ex: Lnl
   = LunarLake)
 **/
   UINT32                      IomTypeCPortPadCfg[12];
 
-/** Offset 0x1068 - CPU USB3 Port Over Current Pin
+/** Offset 0x1070 - CPU USB3 Port Over Current Pin
   Describe the specific over current pin number of USBC Port N.
 **/
   UINT8                       CpuUsb3OverCurrentPin[10];
 
-/** Offset 0x1072 - Enable D3 Cold in TCSS
+/** Offset 0x107A - Enable D3 Cold in TCSS
   This policy will enable/disable D3 cold support in IOM
   $EN_DIS
 **/
   UINT8                       D3ColdEnable;
 
-/** Offset 0x1073 - TC State in TCSS
+/** Offset 0x107B - TC State in TCSS
   This TC C-State Limit in IOM
 **/
   UINT8                       TcCstateLimit;
 
-/** Offset 0x1074 - Reserved
+/** Offset 0x107C - Reserved
 **/
   UINT8                       Reserved35[2];
 
-/** Offset 0x1076 - Enable/Disable PMC-PD Solution
+/** Offset 0x107E - Enable/Disable PMC-PD Solution
   This policy will enable/disable PMC-PD Solution vs EC-TCPC Solution
   $EN_DIS
 **/
   UINT8                       PmcPdEnable;
 
-/** Offset 0x1077 - Reserved
+/** Offset 0x107F - Reserved
 **/
   UINT8                       Reserved36;
 
-/** Offset 0x1078 - TCSS Aux Orientation Override Enable
+/** Offset 0x1080 - TCSS Aux Orientation Override Enable
   Bits 0, 2, ... 10 control override enables, bits 1, 3, ... 11 control overrides
 **/
   UINT16                      TcssAuxOri;
 
-/** Offset 0x107A - TCSS HSL Orientation Override Enable
+/** Offset 0x1082 - TCSS HSL Orientation Override Enable
   Bits 0, 2, ... 10 control override enables, bits 1, 3, ... 11 control overrides
 **/
   UINT16                      TcssHslOri;
 
-/** Offset 0x107C - TCSS USB Port Enable
+/** Offset 0x1084 - TCSS USB Port Enable
   Bits 0, 1, ... max Type C port control enables
 **/
   UINT8                       UsbTcPortEn;
 
-/** Offset 0x107D - VCCST request for IOM
+/** Offset 0x1085 - VCCST request for IOM
   This policy will enable/disable VCCST and also decides if message would be replayed in S4/S5
   $EN_DIS
 **/
   UINT8                       VccSt;
 
-/** Offset 0x107E - Enable/Disable PTM
+/** Offset 0x1086 - Enable/Disable PTM
   This policy will enable/disable Precision Time Measurement for TCSS PCIe Root Ports
   $EN_DIS
 **/
   UINT8                       PtmEnabled[4];
 
-/** Offset 0x1082 - PCIE RP Ltr Enable
+/** Offset 0x108A - PCIE RP Ltr Enable
   Latency Tolerance Reporting Mechanism.
 **/
   UINT8                       SaPcieItbtRpLtrEnable[4];
 
-/** Offset 0x1086 - PCIE RP Snoop Latency Override Mode
+/** Offset 0x108E - PCIE RP Snoop Latency Override Mode
   Latency Tolerance Reporting, Snoop Latency Override Mode.
 **/
   UINT8                       SaPcieItbtRpSnoopLatencyOverrideMode[4];
 
-/** Offset 0x108A - PCIE RP Snoop Latency Override Multiplier
+/** Offset 0x1092 - PCIE RP Snoop Latency Override Multiplier
   Latency Tolerance Reporting, Snoop Latency Override Multiplier.
 **/
   UINT8                       SaPcieItbtRpSnoopLatencyOverrideMultiplier[4];
 
-/** Offset 0x108E - PCIE RP Snoop Latency Override Value
+/** Offset 0x1096 - PCIE RP Snoop Latency Override Value
   Latency Tolerance Reporting, Snoop Latency Override Value.
 **/
   UINT16                      SaPcieItbtRpSnoopLatencyOverrideValue[4];
 
-/** Offset 0x1096 - PCIE RP Non Snoop Latency Override Mode
+/** Offset 0x109E - PCIE RP Non Snoop Latency Override Mode
   Latency Tolerance Reporting, Non-Snoop Latency Override Mode.
 **/
   UINT8                       SaPcieItbtRpNonSnoopLatencyOverrideMode[4];
 
-/** Offset 0x109A - PCIE RP Non Snoop Latency Override Multiplier
+/** Offset 0x10A2 - PCIE RP Non Snoop Latency Override Multiplier
   Latency Tolerance Reporting, Non-Snoop Latency Override Multiplier.
 **/
   UINT8                       SaPcieItbtRpNonSnoopLatencyOverrideMultiplier[4];
 
-/** Offset 0x109E - PCIE RP Non Snoop Latency Override Value
+/** Offset 0x10A6 - PCIE RP Non Snoop Latency Override Value
   Latency Tolerance Reporting, Non-Snoop Latency Override Value.
 **/
   UINT16                      SaPcieItbtRpNonSnoopLatencyOverrideValue[4];
 
-/** Offset 0x10A6 - Force LTR Override
+/** Offset 0x10AE - Force LTR Override
   Force LTR Override.
 **/
   UINT8                       SaPcieItbtRpForceLtrOverride[4];
 
-/** Offset 0x10AA - PCIE RP Ltr Config Lock
+/** Offset 0x10B2 - PCIE RP Ltr Config Lock
   0: Disable; 1: Enable.
 **/
   UINT8                       SaPcieItbtRpLtrConfigLock[4];
 
-/** Offset 0x10AE - Reserved
+/** Offset 0x10B6 - Reserved
 **/
   UINT8                       Reserved37[4];
 
-/** Offset 0x10B2 - Touch Host Controller Assignment
+/** Offset 0x10BA - Touch Host Controller Assignment
   Assign THC 0x0:ThcAssignmentNone, 0x1:ThcAssignmentThc0, 0x2:ThcAssignmentThc1
 **/
   UINT8                       ThcAssignment[2];
 
-/** Offset 0x10B4 - Touch Host Controller Interrupt Pin Mux
+/** Offset 0x10BC - Touch Host Controller Interrupt Pin Mux
   Set THC Pin Muxing Value if signal can be enabled on multiple pads. Refer to GPIO_*_MUXING_THC_SPIx_INTB_*
   for possible values.
 **/
   UINT8                       ThcInterruptPinMuxing[8];
 
-/** Offset 0x10BC - Touch Host Controller Mode
+/** Offset 0x10C4 - Touch Host Controller Mode
   Switch between Intel THC protocol and Industry standard HID Over SPI protocol. 0x0:Thc, 0x1:Hid
 **/
   UINT8                       ThcMode[2];
 
-/** Offset 0x10BE - Touch Host Controller Wake On Touch
+/** Offset 0x10C6 - Touch Host Controller Wake On Touch
   Based on this setting vGPIO for given THC will be in native mode, and additional
   _CRS for wake will be exposed in ACPI
 **/
   UINT8                       ThcWakeOnTouch[2];
 
-/** Offset 0x10C0 - Reserved
+/** Offset 0x10C8 - Reserved
 **/
   UINT8                      Reserved38[337];
 
-/** Offset 0x1211 - PCHHOT# pin
+/** Offset 0x1219 - PCHHOT# pin
   Enable PCHHOT# pin assertion when temperature is higher than PchHotLevel. 0: disable, 1: enable
   $EN_DIS
 **/
   UINT8                       PchHotEnable;
 
-/** Offset 0x1212 - Thermal Throttling Custimized T0Level Value
+/** Offset 0x121A - Thermal Throttling Custimized T0Level Value
   Custimized T0Level value.
 **/
   UINT16                      PchT0Level;
 
-/** Offset 0x1214 - Thermal Throttling Custimized T1Level Value
+/** Offset 0x121C - Thermal Throttling Custimized T1Level Value
   Custimized T1Level value.
 **/
   UINT16                      PchT1Level;
 
-/** Offset 0x1216 - Thermal Throttling Custimized T2Level Value
+/** Offset 0x121E - Thermal Throttling Custimized T2Level Value
   Custimized T2Level value.
 **/
   UINT16                      PchT2Level;
 
-/** Offset 0x1218 - Enable The Thermal Throttle
+/** Offset 0x1220 - Enable The Thermal Throttle
   Enable the thermal throttle function.
   $EN_DIS
 **/
   UINT8                       PchTTEnable;
 
-/** Offset 0x1219 - PMSync State 13
+/** Offset 0x1221 - PMSync State 13
   When set to 1 and the programmed GPIO pin is a 1, then PMSync state 13 will force
   at least T2 state.
   $EN_DIS
 **/
   UINT8                       PchTTState13Enable;
 
-/** Offset 0x121A - Thermal Throttle Lock
+/** Offset 0x1222 - Thermal Throttle Lock
   Thermal Throttle Lock.
   $EN_DIS
 **/
   UINT8                       PchTTLock;
 
-/** Offset 0x121B - Thermal Throttling Suggested Setting
+/** Offset 0x1223 - Thermal Throttling Suggested Setting
   Thermal Throttling Suggested Setting.
   $EN_DIS
 **/
   UINT8                       TTSuggestedSetting;
 
-/** Offset 0x121C - Thermal Device Temperature
+/** Offset 0x1224 - Thermal Device Temperature
   Decides the temperature.
 **/
   UINT16                      PchTemperatureHotLevel;
 
-/** Offset 0x121E
+/** Offset 0x1226
 **/
   UINT8                       PchTsnEnable[4];
 
-/** Offset 0x1222 - Reserved
+/** Offset 0x122A - Reserved
 **/
   UINT8                      Reserved39[34];
 
-/** Offset 0x1244 - Enable USB2 ports
+/** Offset 0x124C - Enable USB2 ports
   Enable/disable per USB2 ports. One byte for each port, byte0 for port0, byte1 for
   port1, and so on.
 **/
   UINT8                       PortUsb20Enable[16];
 
-/** Offset 0x1254 - Enable USB3 ports
+/** Offset 0x125C - Enable USB3 ports
   Enable/disable per USB3 ports. One byte for each port, byte0 for port0, byte1 for
   port1, and so on.
 **/
   UINT8                       PortUsb30Enable[10];
 
-/** Offset 0x125E - Enable xDCI controller
+/** Offset 0x1266 - Enable xDCI controller
   Enable/disable to xDCI controller.
   $EN_DIS
 **/
   UINT8                       XdciEnable;
 
-/** Offset 0x125F - USB PDO Programming
+/** Offset 0x1267 - USB PDO Programming
   Enable/disable PDO programming for USB in PEI phase. Disabling will allow for programming
   during later phase. 1: enable, 0: disable
   $EN_DIS
 **/
   UINT8                       UsbPdoProgramming;
 
-/** Offset 0x1260 - Reserved
+/** Offset 0x1268 - Reserved
 **/
   UINT8                       Reserved40;
 
-/** Offset 0x1261 - PCH USB OverCurrent mapping enable
+/** Offset 0x1269 - PCH USB OverCurrent mapping enable
   1: Will program USB OC pin mapping in xHCI controller memory, 0: Will clear OC pin
   mapping allow for NOA usage of OC pins
   $EN_DIS
 **/
   UINT8                       PchUsbOverCurrentEnable;
 
-/** Offset 0x1262 - USB2 Port Over Current Pin
+/** Offset 0x126A - USB2 Port Over Current Pin
   Describe the specific over current pin number of USB 2.0 Port N.
 **/
   UINT8                       Usb2OverCurrentPin[16];
 
-/** Offset 0x1272 - USB3 Port Over Current Pin
+/** Offset 0x127A - USB3 Port Over Current Pin
   Describe the specific over current pin number of USB 3.0 Port N.
 **/
   UINT8                       Usb3OverCurrentPin[10];
 
-/** Offset 0x127C - Enable xHCI LTR override
+/** Offset 0x1284 - Enable xHCI LTR override
   Enables override of recommended LTR values for xHCI
   $EN_DIS
 **/
   UINT8                       PchUsbLtrOverrideEnable;
 
-/** Offset 0x127D - Reserved
+/** Offset 0x1285 - Reserved
 **/
   UINT8                       Reserved41[3];
 
-/** Offset 0x1280 - xHCI High Idle Time LTR override
+/** Offset 0x1288 - xHCI High Idle Time LTR override
   Value used for overriding LTR recommendation for xHCI High Idle Time LTR setting
 **/
   UINT32                      PchUsbLtrHighIdleTimeOverride;
 
-/** Offset 0x1284 - xHCI Medium Idle Time LTR override
+/** Offset 0x128C - xHCI Medium Idle Time LTR override
   Value used for overriding LTR recommendation for xHCI Medium Idle Time LTR setting
 **/
   UINT32                      PchUsbLtrMediumIdleTimeOverride;
 
-/** Offset 0x1288 - xHCI Low Idle Time LTR override
+/** Offset 0x1290 - xHCI Low Idle Time LTR override
   Value used for overriding LTR recommendation for xHCI Low Idle Time LTR setting
 **/
   UINT32                      PchUsbLtrLowIdleTimeOverride;
 
-/** Offset 0x128C - USB2 Port Reset Message Enable
+/** Offset 0x1294 - USB2 Port Reset Message Enable
   0: Disable USB2 Port Reset Message; 1: Enable USB2 Port Reset Message; This must
   be enable for USB2 Port those are paired with CPU XHCI Port
 **/
   UINT8                       PortResetMessageEnable[16];
 
-/** Offset 0x129C - PCH USB OverCurrent mapping lock enable
+/** Offset 0x12A4 - PCH USB OverCurrent mapping lock enable
   If this policy option is enabled then BIOS will program OCCFDONE bit in xHCI meaning
   that OC mapping data will be consumed by xHCI and OC mapping registers will be locked.
   $EN_DIS
 **/
   UINT8                       PchXhciOcLock;
 
-/** Offset 0x129D - USB Per Port HS Preemphasis Bias
+/** Offset 0x12A5 - USB Per Port HS Preemphasis Bias
   USB Per Port HS Preemphasis Bias. 000b-0mV, 001b-11.25mV, 010b-16.9mV, 011b-28.15mV,
   100b-28.15mV, 101b-39.35mV, 110b-45mV, 111b-56.3mV. One byte for each port.
 **/
   UINT8                       Usb2PhyPetxiset[16];
 
-/** Offset 0x12AD - USB Per Port HS Transmitter Bias
+/** Offset 0x12B5 - USB Per Port HS Transmitter Bias
   USB Per Port HS Transmitter Bias. 000b-0mV, 001b-11.25mV, 010b-16.9mV, 011b-28.15mV,
   100b-28.15mV, 101b-39.35mV, 110b-45mV, 111b-56.3mV, One byte for each port.
 **/
   UINT8                       Usb2PhyTxiset[16];
 
-/** Offset 0x12BD - USB Per Port HS Transmitter Emphasis
+/** Offset 0x12C5 - USB Per Port HS Transmitter Emphasis
   USB Per Port HS Transmitter Emphasis. 00b - Emphasis OFF, 01b - De-emphasis ON,
   10b - Pre-emphasis ON, 11b - Pre-emphasis & De-emphasis ON. One byte for each port.
 **/
   UINT8                       Usb2PhyPredeemp[16];
 
-/** Offset 0x12CD - USB Per Port Half Bit Pre-emphasis
+/** Offset 0x12D5 - USB Per Port Half Bit Pre-emphasis
   USB Per Port Half Bit Pre-emphasis. 1b - half-bit pre-emphasis, 0b - full-bit pre-emphasis.
   One byte for each port.
 **/
   UINT8                       Usb2PhyPehalfbit[16];
 
-/** Offset 0x12DD - Enable the write to USB 3.0 TX Output -3.5dB De-Emphasis Adjustment
+/** Offset 0x12E5 - Enable the write to USB 3.0 TX Output -3.5dB De-Emphasis Adjustment
   Enable the write to USB 3.0 TX Output -3.5dB De-Emphasis Adjustment. Each value
   in arrary can be between 0-1. One byte for each port.
 **/
   UINT8                       Usb3HsioTxDeEmphEnable[10];
 
-/** Offset 0x12E7 - USB 3.0 TX Output -3.5dB De-Emphasis Adjustment Setting
+/** Offset 0x12EF - USB 3.0 TX Output -3.5dB De-Emphasis Adjustment Setting
   USB 3.0 TX Output -3.5dB De-Emphasis Adjustment Setting, HSIO_TX_DWORD5[21:16],
   <b>Default = 29h</b> (approximately -3.5dB De-Emphasis). One byte for each port.
 **/
   UINT8                       Usb3HsioTxDeEmph[10];
 
-/** Offset 0x12F1 - Enable the write to USB 3.0 TX Output Downscale Amplitude Adjustment
+/** Offset 0x12F9 - Enable the write to USB 3.0 TX Output Downscale Amplitude Adjustment
   Enable the write to USB 3.0 TX Output Downscale Amplitude Adjustment, Each value
   in arrary can be between 0-1. One byte for each port.
 **/
   UINT8                       Usb3HsioTxDownscaleAmpEnable[10];
 
-/** Offset 0x12FB - USB 3.0 TX Output Downscale Amplitude Adjustment
+/** Offset 0x1303 - USB 3.0 TX Output Downscale Amplitude Adjustment
   USB 3.0 TX Output Downscale Amplitude Adjustment, HSIO_TX_DWORD8[21:16], <b>Default
   = 00h</b>. One byte for each port.
 **/
   UINT8                       Usb3HsioTxDownscaleAmp[10];
 
-/** Offset 0x1305
+/** Offset 0x130D
 **/
   UINT8                       PchUsb3HsioCtrlAdaptOffsetCfgEnable[10];
 
-/** Offset 0x130F
+/** Offset 0x1317
 **/
   UINT8                       PchUsb3HsioFilterSelNEnable[10];
 
-/** Offset 0x1319
+/** Offset 0x1321
 **/
   UINT8                       PchUsb3HsioFilterSelPEnable[10];
 
-/** Offset 0x1323
+/** Offset 0x132B
 **/
   UINT8                       PchUsb3HsioOlfpsCfgPullUpDwnResEnable[10];
 
-/** Offset 0x132D
+/** Offset 0x1335
 **/
   UINT8                       PchUsb3HsioCtrlAdaptOffsetCfg[10];
 
-/** Offset 0x1337
+/** Offset 0x133F
 **/
   UINT8                       PchUsb3HsioOlfpsCfgPullUpDwnRes[10];
 
-/** Offset 0x1341
+/** Offset 0x1349
 **/
   UINT8                       PchUsb3HsioFilterSelN[10];
 
-/** Offset 0x134B
+/** Offset 0x1353
 **/
   UINT8                       PchUsb3HsioFilterSelP[10];
 
-/** Offset 0x1355 - Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 3
+/** Offset 0x135D - Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 3
   Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 3, Each
   value in array can be between 0-1. One byte for each port.
 **/
   UINT8                       Usb3HsioTxRate3UniqTranEnable[10];
 
-/** Offset 0x135F - USB 3.0 TX Output Unique Transition Bit Scale for rate 3
+/** Offset 0x1367 - USB 3.0 TX Output Unique Transition Bit Scale for rate 3
   USB 3.0 TX Output Unique Transition Bit Scale for rate 3, HSIO_TX_DWORD9[6:0], <b>Default
   = 4Ch</b>. One byte for each port.
 **/
   UINT8                       Usb3HsioTxRate3UniqTran[10];
 
-/** Offset 0x1369 - Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 2
+/** Offset 0x1371 - Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 2
   Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 2, Each
   value in array can be between 0-1. One byte for each port.
 **/
   UINT8                       Usb3HsioTxRate2UniqTranEnable[10];
 
-/** Offset 0x1373 - USB 3.0 TX Output Unique Transition Bit Scale for rate 2
+/** Offset 0x137B - USB 3.0 TX Output Unique Transition Bit Scale for rate 2
   USB 3.0 TX Output Unique Transition Bit Scale for rate 2, HSIO_TX_DWORD9[14:8],
   <b>Default = 4Ch</b>. One byte for each port.
 **/
   UINT8                       Usb3HsioTxRate2UniqTran[10];
 
-/** Offset 0x137D - Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 1
+/** Offset 0x1385 - Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 1
   Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 1, Each
   value in array can be between 0-1. One byte for each port.
 **/
   UINT8                       Usb3HsioTxRate1UniqTranEnable[10];
 
-/** Offset 0x1387 - USB 3.0 TX Output Unique Transition Bit Scale for rate 1
+/** Offset 0x138F - USB 3.0 TX Output Unique Transition Bit Scale for rate 1
   USB 3.0 TX Output Unique Transition Bit Scale for rate 1, HSIO_TX_DWORD9[22:16],
   <b>Default = 4Ch</b>. One byte for each port.
 **/
   UINT8                       Usb3HsioTxRate1UniqTran[10];
 
-/** Offset 0x1391 - Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 0
+/** Offset 0x1399 - Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 0
   Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 0, Each
   value in array can be between 0-1. One byte for each port.
 **/
   UINT8                       Usb3HsioTxRate0UniqTranEnable[10];
 
-/** Offset 0x139B - USB 3.0 TX Output Unique Transition Bit Scale for rate 0
+/** Offset 0x13A3 - USB 3.0 TX Output Unique Transition Bit Scale for rate 0
   USB 3.0 TX Output Unique Transition Bit Scale for rate 0, HSIO_TX_DWORD9[30:24],
   <b>Default = 4Ch</b>. One byte for each port.
 **/
   UINT8                       Usb3HsioTxRate0UniqTran[10];
 
-/** Offset 0x13A5 - Reserved
+/** Offset 0x13AD - Reserved
 **/
   UINT8                       Reserved42[4];
 
-/** Offset 0x13A9 - Enable/Disable NPU Device
+/** Offset 0x13B1 - Enable/Disable NPU Device
   Enable(Default): Enable NPU Device, Disable: Disable NPU Device
   $EN_DIS
 **/
   UINT8                       NpuEnable;
 
-/** Offset 0x13AA - Enable LAN
+/** Offset 0x13B2 - Enable LAN
   Enable/disable LAN controller.
   $EN_DIS
 **/
   UINT8                       PchLanEnable;
 
-/** Offset 0x13AB - Enable PCH Lan LTR capabilty of PCH internal LAN
+/** Offset 0x13B3 - Enable PCH Lan LTR capabilty of PCH internal LAN
   0: Disable; 1: Enable.
   $EN_DIS
 **/
   UINT8                       PchLanLtrEnable;
 
-/** Offset 0x13AC - Reserved
+/** Offset 0x13B4 - Reserved
 **/
   UINT8                       Reserved43;
 
-/** Offset 0x13AD - Skip Ssid Programming.
+/** Offset 0x13B5 - Skip Ssid Programming.
   When set to TRUE, silicon code will not do any SSID programming and platform code
   needs to handle that by itself properly.
   $EN_DIS
 **/
   UINT8                       SiSkipSsidProgramming;
 
-/** Offset 0x13AE - Change Default SVID
+/** Offset 0x13B6 - Change Default SVID
   Change the default SVID used in FSP to programming internal devices. This is only
   valid when SkipSsidProgramming is FALSE.
 **/
   UINT16                      SiCustomizedSvid;
 
-/** Offset 0x13B0 - Change Default SSID
+/** Offset 0x13B8 - Change Default SSID
   Change the default SSID used in FSP to programming internal devices. This is only
   valid when SkipSsidProgramming is FALSE.
 **/
   UINT16                      SiCustomizedSsid;
 
-/** Offset 0x13B2 - Reserved
+/** Offset 0x13BA - Reserved
 **/
   UINT8                       Reserved44[6];
 
-/** Offset 0x13B8 - SVID SDID table Poniter.
+/** Offset 0x13C0 - SVID SDID table Poniter.
   The address of the table of SVID SDID to customize each SVID SDID entry. This is
   only valid when SkipSsidProgramming is FALSE.
 **/
   UINT64                      SiSsidTablePtr;
 
-/** Offset 0x13C0 - Number of ssid table.
+/** Offset 0x13C8 - Number of ssid table.
   SiNumberOfSsidTableEntry should match the table entries created in SiSsidTablePtr.
   This is only valid when SkipSsidProgramming is FALSE.
 **/
   UINT16                      SiNumberOfSsidTableEntry;
 
-/** Offset 0x13C2 - Reserved
+/** Offset 0x13CA - Reserved
 **/
   UINT8                       Reserved45[10];
 
-/** Offset 0x13CC - LogoPixelHeight Address
+/** Offset 0x13D4 - LogoPixelHeight Address
   Address of LogoPixelHeight
 **/
   UINT32                      LogoPixelHeight;
 
-/** Offset 0x13D0 - LogoPixelWidth Address
+/** Offset 0x13D8 - LogoPixelWidth Address
   Address of LogoPixelWidth
 **/
   UINT32                      LogoPixelWidth;
 
-/** Offset 0x13D4 - Reserved
+/** Offset 0x13DC - Reserved
 **/
   UINT8                       Reserved46[4];
 
-/** Offset 0x13D8 - Blt Buffer Address
+/** Offset 0x13E0 - Blt Buffer Address
   Address of Blt buffer
 **/
   UINT64                      BltBufferAddress;
 
-/** Offset 0x13E0 - Graphics Configuration Ptr
+/** Offset 0x13E8 - Graphics Configuration Ptr
   Points to VBT
 **/
   UINT64                      GraphicsConfigPtr;
 
-/** Offset 0x13E8 - Enable/Disable SkipFspGop
+/** Offset 0x13F0 - Enable/Disable SkipFspGop
   Enable: Skip FSP provided GOP driver, Disable(Default): Use FSP provided GOP driver
   $EN_DIS
 **/
   UINT8                       SkipFspGop;
 
-/** Offset 0x13E9 - Reserved
+/** Offset 0x13F1 - Reserved
 **/
   UINT8                       Reserved47;
 
-/** Offset 0x13EA - Enable/Disable IGFX RenderStandby
+/** Offset 0x13F2 - Enable/Disable IGFX RenderStandby
   Enable(Default): Enable IGFX RenderStandby, Disable: Disable IGFX RenderStandby
   $EN_DIS
 **/
   UINT8                       RenderStandby;
 
-/** Offset 0x13EB - Reserved
+/** Offset 0x13F3 - Reserved
 **/
   UINT8                       Reserved48[3];
 
-/** Offset 0x13EE - Enable/Disable PavpEnable
+/** Offset 0x13F6 - Enable/Disable PavpEnable
   Enable(Default): Enable PavpEnable, Disable: Disable PavpEnable
   $EN_DIS
 **/
   UINT8                       PavpEnable;
 
-/** Offset 0x13EF - Enable/Disable PeiGraphicsPeimInit
+/** Offset 0x13F7 - Enable/Disable PeiGraphicsPeimInit
   <b>Enable(Default):</b> FSP will initialize the framebuffer and provide it via EFI_PEI_GRAPHICS_INFO_HOB.
   Disable: FSP will NOT initialize the framebuffer.
   $EN_DIS
 **/
   UINT8                       PeiGraphicsPeimInit;
 
-/** Offset 0x13F0 - Reserved
+/** Offset 0x13F8 - Reserved
 **/
   UINT8                       Reserved49[4];
 
-/** Offset 0x13F4 - Intel Graphics VBT (Video BIOS Table) Size
+/** Offset 0x13FC - Intel Graphics VBT (Video BIOS Table) Size
   Size of Internal Graphics VBT Image
 **/
   UINT32                      VbtSize;
 
-/** Offset 0x13F8 - Platform LID Status for LFP Displays.
+/** Offset 0x1400 - Platform LID Status for LFP Displays.
   LFP Display Lid Status (LID_STATUS enum): 0 (Default): LidClosed, 1: LidOpen.
   0: LidClosed, 1: LidOpen
 **/
   UINT8                       LidStatus;
 
-/** Offset 0x13F9 - Reserved
+/** Offset 0x1401 - Reserved
 **/
   UINT8                       Reserved50[11];
 
-/** Offset 0x1404 - Address of PCH_DEVICE_INTERRUPT_CONFIG table.
+/** Offset 0x140C - Address of PCH_DEVICE_INTERRUPT_CONFIG table.
   The address of the table of PCH_DEVICE_INTERRUPT_CONFIG.
 **/
   UINT32                      DevIntConfigPtr;
 
-/** Offset 0x1408 - Number of DevIntConfig Entry
+/** Offset 0x1410 - Number of DevIntConfig Entry
   Number of Device Interrupt Configuration Entry. If this is not zero, the DevIntConfigPtr
   must not be NULL.
 **/
   UINT8                       NumOfDevIntConfig;
 
-/** Offset 0x1409 - Select GPIO IRQ Route
+/** Offset 0x1411 - Select GPIO IRQ Route
   GPIO IRQ Select. The valid value is 14 or 15.
 **/
   UINT8                       GpioIrqRoute;
 
-/** Offset 0x140A - Select SciIrqSelect
+/** Offset 0x1412 - Select SciIrqSelect
   SCI IRQ Select. The valid value is 9, 10, 11, and 20, 21, 22, 23 for APIC only.
 **/
   UINT8                       SciIrqSelect;
 
-/** Offset 0x140B - Select TcoIrqSelect
+/** Offset 0x1413 - Select TcoIrqSelect
   TCO IRQ Select. The valid value is 9, 10, 11, 20, 21, 22, 23.
 **/
   UINT8                       TcoIrqSelect;
 
-/** Offset 0x140C - Enable/Disable Tco IRQ
+/** Offset 0x1414 - Enable/Disable Tco IRQ
   Enable/disable TCO IRQ
   $EN_DIS
 **/
   UINT8                       TcoIrqEnable;
 
-/** Offset 0x140D - Reserved
+/** Offset 0x1415 - Reserved
 **/
   UINT8                       Reserved51[5];
 
-/** Offset 0x1412 - Mask to enable the usage of external V1p05 VR rail in specific S0ix or Sx states
+/** Offset 0x141A - Mask to enable the usage of external V1p05 VR rail in specific S0ix or Sx states
   Enable External V1P05 Rail in: BIT0:S0i1/S0i2, BIT1:S0i3, BIT2:S3, BIT3:S4, BIT5:S5
 **/
   UINT8                       PchFivrExtV1p05RailEnabledStates;
 
-/** Offset 0x1413 - Mask to enable the platform configuration of external V1p05 VR rail
+/** Offset 0x141B - Mask to enable the platform configuration of external V1p05 VR rail
   External V1P05 Rail Supported Configuration
 **/
   UINT8                       PchFivrExtV1p05RailSupportedVoltageStates;
 
-/** Offset 0x1414 - External V1P05 Voltage Value that will be used in S0i2/S0i3 states
+/** Offset 0x141C - External V1P05 Voltage Value that will be used in S0i2/S0i3 states
   Value is given in 2.5mV increments (0=0mV, 1=2.5mV, 2=5mV...)
 **/
   UINT16                      PchFivrExtV1p05RailVoltage;
 
-/** Offset 0x1416 - External V1P05 Icc Max Value
+/** Offset 0x141E - External V1P05 Icc Max Value
   Granularity of this setting is 1mA and maximal possible value is 200mA
 **/
   UINT8                       PchFivrExtV1p05RailIccMax;
 
-/** Offset 0x1417 - Mask to enable the usage of external Vnn VR rail in specific S0ix or Sx states
+/** Offset 0x141F - Mask to enable the usage of external Vnn VR rail in specific S0ix or Sx states
   Enable External Vnn Rail in: BIT0:S0i1/S0i2, BIT1:S0i3, BIT2:S3, BIT3:S4, BIT5:S5
 **/
   UINT8                       PchFivrExtVnnRailEnabledStates;
 
-/** Offset 0x1418 - Mask to enable the platform configuration of external Vnn VR rail
+/** Offset 0x1420 - Mask to enable the platform configuration of external Vnn VR rail
   External Vnn Rail Supported Configuration
 **/
   UINT8                       PchFivrExtVnnRailSupportedVoltageStates;
 
-/** Offset 0x1419 - Reserved
+/** Offset 0x1421 - Reserved
 **/
   UINT8                       Reserved52;
 
-/** Offset 0x141A - External Vnn Voltage Value that will be used in S0ix/Sx states
+/** Offset 0x1422 - External Vnn Voltage Value that will be used in S0ix/Sx states
   Value is given in 2.5mV increments (0=0mV, 1=2.5mV, 2=5mV...), Default is set to 420
 **/
   UINT16                      PchFivrExtVnnRailVoltage;
 
-/** Offset 0x141C - External Vnn Icc Max Value that will be used in S0ix/Sx states
+/** Offset 0x1424 - External Vnn Icc Max Value that will be used in S0ix/Sx states
   Granularity of this setting is 1mA and maximal possible value is 200mA
 **/
   UINT8                       PchFivrExtVnnRailIccMax;
 
-/** Offset 0x141D - Mask to enable the usage of external Vnn VR rail in Sx states
+/** Offset 0x1425 - Mask to enable the usage of external Vnn VR rail in Sx states
   Use only if Ext Vnn Rail config is different in Sx. Enable External Vnn Rail in
   Sx: BIT0-1:Reserved, BIT2:S3, BIT3:S4, BIT5:S5
 **/
   UINT8                       PchFivrExtVnnRailSxEnabledStates;
 
-/** Offset 0x141E - External Vnn Voltage Value that will be used in Sx states
+/** Offset 0x1426 - External Vnn Voltage Value that will be used in Sx states
   Use only if Ext Vnn Rail config is different in Sx. Value is given in 2.5mV increments
   (0=0mV, 1=2.5mV, 2=5mV...)
 **/
   UINT16                      PchFivrExtVnnRailSxVoltage;
 
-/** Offset 0x1420 - External Vnn Icc Max Value that will be used in Sx states
+/** Offset 0x1428 - External Vnn Icc Max Value that will be used in Sx states
   Use only if Ext Vnn Rail config is different in Sx. Granularity of this setting
   is 1mA and maximal possible value is 200mA
 **/
   UINT8                       PchFivrExtVnnRailSxIccMax;
 
-/** Offset 0x1421 - Transition time in microseconds from Low Current Mode Voltage to High Current Mode Voltage
+/** Offset 0x1429 - Transition time in microseconds from Low Current Mode Voltage to High Current Mode Voltage
   This field has 1us resolution. When value is 0 PCH will not transition VCCIN_AUX
   to low current mode voltage.
 **/
   UINT8                       PchFivrVccinAuxLowToHighCurModeVolTranTime;
 
-/** Offset 0x1422 - Transition time in microseconds from Retention Mode Voltage to High Current Mode Voltage
+/** Offset 0x142A - Transition time in microseconds from Retention Mode Voltage to High Current Mode Voltage
   This field has 1us resolution. When value is 0 PCH will not transition VCCIN_AUX
   to retention mode voltage.
 **/
   UINT8                       PchFivrVccinAuxRetToHighCurModeVolTranTime;
 
-/** Offset 0x1423 - Transition time in microseconds from Retention Mode Voltage to Low Current Mode Voltage
+/** Offset 0x142B - Transition time in microseconds from Retention Mode Voltage to Low Current Mode Voltage
   This field has 1us resolution. When value is 0 PCH will not transition VCCIN_AUX
   to retention mode voltage.
 **/
   UINT8                       PchFivrVccinAuxRetToLowCurModeVolTranTime;
 
-/** Offset 0x1424 - Transition time in microseconds from Off (0V) to High Current Mode Voltage
+/** Offset 0x142C - Transition time in microseconds from Off (0V) to High Current Mode Voltage
   This field has 1us resolution. When value is 0 Transition to 0V is disabled.
 **/
   UINT16                      PchFivrVccinAuxOffToHighCurModeVolTranTime;
 
-/** Offset 0x1426 - FIVR Dynamic Power Management
+/** Offset 0x142E - FIVR Dynamic Power Management
   Enable/Disable FIVR Dynamic Power Management.
   $EN_DIS
 **/
   UINT8                       PchFivrDynPm;
 
-/** Offset 0x1427 - Reserved
+/** Offset 0x142F - Reserved
 **/
   UINT8                       Reserved53;
 
-/** Offset 0x1428 - External V1P05 Icc Max Value
+/** Offset 0x1430 - External V1P05 Icc Max Value
   Granularity of this setting is 1mA and maximal possible value is 500mA
 **/
   UINT16                      PchFivrExtV1p05RailIccMaximum;
 
-/** Offset 0x142A - External Vnn Icc Max Value that will be used in S0ix/Sx states
+/** Offset 0x1432 - External Vnn Icc Max Value that will be used in S0ix/Sx states
   Granularity of this setting is 1mA and maximal possible value is 500mA
 **/
   UINT16                      PchFivrExtVnnRailIccMaximum;
 
-/** Offset 0x142C - External Vnn Icc Max Value that will be used in Sx states
+/** Offset 0x1434 - External Vnn Icc Max Value that will be used in Sx states
   Use only if Ext Vnn Rail config is different in Sx. Granularity of this setting
   is 1mA and maximal possible value is 500mA
 **/
   UINT16                      PchFivrExtVnnRailSxIccMaximum;
 
-/** Offset 0x142E - External V1P05 Control Ramp Timer value
+/** Offset 0x1436 - External V1P05 Control Ramp Timer value
   Hold off time to be used when changing the v1p05_ctrl for external bypass value in us
 **/
   UINT8                       PchFivrExtV1p05RailCtrlRampTmr;
 
-/** Offset 0x142F - External VNN Control Ramp Timer value
+/** Offset 0x1437 - External VNN Control Ramp Timer value
   Hold off time to be used when changing the vnn_ctrl for external bypass value in us
 **/
   UINT8                       PchFivrExtVnnRailCtrlRampTmr;
 
-/** Offset 0x1430 - PCH Compatibility Revision ID
+/** Offset 0x1438 - PCH Compatibility Revision ID
   This member describes whether or not the CRID feature of PCH should be enabled.
   $EN_DIS
 **/
   UINT8                       PchCrid;
 
-/** Offset 0x1431 - PCH Legacy IO Low Latency Enable
+/** Offset 0x1439 - PCH Legacy IO Low Latency Enable
   Set to enable low latency of legacy IO. <b>0: Disable</b>, 1: Enable
   $EN_DIS
 **/
   UINT8                       PchLegacyIoLowLatency;
 
-/** Offset 0x1432 - Reserved
+/** Offset 0x143A - Reserved
 **/
   UINT8                       Reserved54;
 
-/** Offset 0x1433 - PCH Unlock SideBand access
+/** Offset 0x143B - PCH Unlock SideBand access
   The SideBand PortID mask for certain end point (e.g. PSFx) will be locked before
   3rd party code execution. 0: Lock SideBand access; 1: Unlock SideBand access.
   $EN_DIS
 **/
   UINT8                       PchSbAccessUnlock;
 
-/** Offset 0x1434 - Enable 8254 Static Clock Gating
+/** Offset 0x143C - Enable 8254 Static Clock Gating
   Set 8254CGE=1 is required for SLP_S0 support. However, set 8254CGE=1 in POST time
   might fail to boot legacy OS using 8254 timer. Make sure it is disabled to support
   legacy OS using 8254 timer. Also enable this while S0ix is enabled.
@@ -2216,7 +2216,7 @@ typedef struct {
 **/
   UINT8                       Enable8254ClockGating;
 
-/** Offset 0x1435 - Enable 8254 Static Clock Gating On S3
+/** Offset 0x143D - Enable 8254 Static Clock Gating On S3
   This is only applicable when Enable8254ClockGating is disabled. FSP will do the
   8254 CGE programming on S3 resume when Enable8254ClockGatingOnS3 is enabled. This
   avoids the SMI requirement for the programming.
@@ -2224,172 +2224,172 @@ typedef struct {
 **/
   UINT8                       Enable8254ClockGatingOnS3;
 
-/** Offset 0x1436 - Enable PCH Io Apic Entry 24-119
+/** Offset 0x143E - Enable PCH Io Apic Entry 24-119
   0: Disable; 1: Enable.
   $EN_DIS
 **/
   UINT8                       PchIoApicEntry24_119;
 
-/** Offset 0x1437 - PCH Io Apic ID
+/** Offset 0x143F - PCH Io Apic ID
   This member determines IOAPIC ID. Default is 0x02.
 **/
   UINT8                       PchIoApicId;
 
-/** Offset 0x1438 - CNVi Configuration
+/** Offset 0x1440 - CNVi Configuration
   This option allows for automatic detection of Connectivity Solution. [Auto Detection]
   assumes that CNVi will be enabled when available, [Disable] allows for disabling CNVi.
   0:Disable, 1:Auto
 **/
   UINT8                       CnviMode;
 
-/** Offset 0x1439 - CNVi Wi-Fi Core
+/** Offset 0x1441 - CNVi Wi-Fi Core
   Enable/Disable CNVi Wi-Fi Core, Default is ENABLE. 0: DISABLE, 1: ENABLE
   $EN_DIS
 **/
   UINT8                       CnviWifiCore;
 
-/** Offset 0x143A - CNVi BT Core
+/** Offset 0x1442 - CNVi BT Core
   Enable/Disable CNVi BT Core, Default is ENABLE. 0: DISABLE, 1: ENABLE
   $EN_DIS
 **/
   UINT8                       CnviBtCore;
 
-/** Offset 0x143B - CNVi BT Interface
+/** Offset 0x1443 - CNVi BT Interface
   This option configures BT device interface to either USB/PCI
   1:USB, 2:PCI
 **/
   UINT8                       CnviBtInterface;
 
-/** Offset 0x143C - CNVi BT Audio Offload
+/** Offset 0x1444 - CNVi BT Audio Offload
   Enable/Disable BT Audio Offload, Default is ENABLE. 0: DISABLE, 1: ENABLE
   $EN_DIS
 **/
   UINT8                       CnviBtAudioOffload;
 
-/** Offset 0x143D - Reserved
+/** Offset 0x1445 - Reserved
 **/
   UINT8                       Reserved55[3];
 
-/** Offset 0x1440 - CNVi RF_RESET pin muxing
+/** Offset 0x1448 - CNVi RF_RESET pin muxing
   Select CNVi RF_RESET# pin depending on board routing. LP/P/M: GPP_A8 = 0x2942E408(default)
   or GPP_F4 = 0x194CE404. H/S: 0. Refer to GPIO_*_MUXING_CNVI_RF_RESET_* in GpioPins*.h.
 **/
   UINT32                      CnviRfResetPinMux;
 
-/** Offset 0x1444 - CNVi CLKREQ pin muxing
+/** Offset 0x144C - CNVi CLKREQ pin muxing
   Select CNVi CLKREQ pin depending on board routing. LP/P/M: GPP_A9 = 0x3942E609(default)
   or GPP_F5 = 0x394CE605. H/S: 0. Refer to GPIO_*_MUXING_CNVI_CRF_XTAL_CLKREQ_* in
   GpioPins*.h.
 **/
   UINT32                      CnviClkreqPinMux;
 
-/** Offset 0x1448 - Reserved
+/** Offset 0x1450 - Reserved
 **/
   UINT8                       Reserved56;
 
-/** Offset 0x1449 - Enable Device 4
+/** Offset 0x1451 - Enable Device 4
   Enable/disable Device 4
   $EN_DIS
 **/
   UINT8                       Device4Enable;
 
-/** Offset 0x144A - Skip PAM regsiter lock
+/** Offset 0x1452 - Skip PAM regsiter lock
   Enable: PAM register will not be locked by RC, platform code should lock it, Disable(Default):
   PAM registers will be locked by RC
   $EN_DIS
 **/
   UINT8                       SkipPamLock;
 
-/** Offset 0x144B - Reserved
+/** Offset 0x1453 - Reserved
 **/
   UINT8                       Reserved57;
 
-/** Offset 0x144C - PCH HDA Verb Table Entry Number
+/** Offset 0x1454 - PCH HDA Verb Table Entry Number
   Number of Entries in Verb Table.
 **/
   UINT8                       PchHdaVerbTableEntryNum;
 
-/** Offset 0x144D - Reserved
+/** Offset 0x1455 - Reserved
 **/
   UINT8                       Reserved58[3];
 
-/** Offset 0x1450 - PCH HDA Verb Table Pointer
+/** Offset 0x1458 - PCH HDA Verb Table Pointer
   Pointer to Array of pointers to Verb Table.
 **/
   UINT64                      PchHdaVerbTablePtr;
 
-/** Offset 0x1458 - PCH HDA Codec Sx Wake Capability
+/** Offset 0x1460 - PCH HDA Codec Sx Wake Capability
   Capability to detect wake initiated by a codec in Sx
 **/
   UINT8                       PchHdaCodecSxWakeCapability;
 
-/** Offset 0x1459 - Enable Pme
+/** Offset 0x1461 - Enable Pme
   Enable Azalia wake-on-ring.
   $EN_DIS
 **/
   UINT8                       PchHdaPme;
 
-/** Offset 0x145A - HD Audio Link Frequency
+/** Offset 0x1462 - HD Audio Link Frequency
   HDA Link Freq (PCH_HDAUDIO_LINK_FREQUENCY enum): 0: 6MHz, 1: 12MHz, 2: 24MHz.
   0: 6MHz, 1: 12MHz, 2: 24MHz
 **/
   UINT8                       PchHdaLinkFrequency;
 
-/** Offset 0x145B - Reserved
+/** Offset 0x1463 - Reserved
 **/
   UINT8                       Reserved59[2];
 
-/** Offset 0x145D - HD Audio Microphone Privacy applied for SoundWire Link number 0 in HW Mode
+/** Offset 0x1465 - HD Audio Microphone Privacy applied for SoundWire Link number 0 in HW Mode
   HD Audio Microphone Privacy applied for SoundWire Link number 0 in HW Mode: 0: Disable, 1: Enable
   $EN_DIS
 **/
   UINT8                       PchHdaMicPrivacyHwModeSoundWire0;
 
-/** Offset 0x145E - HD Audio Microphone Privacy applied for SoundWire Link number 1 in HW Mode
+/** Offset 0x1466 - HD Audio Microphone Privacy applied for SoundWire Link number 1 in HW Mode
   HD Audio Microphone Privacy applied for SoundWire Link number 1 in HW Mode: 0: Disable, 1: Enable
   $EN_DIS
 **/
   UINT8                       PchHdaMicPrivacyHwModeSoundWire1;
 
-/** Offset 0x145F - HD Audio Microphone Privacy applied for SoundWire Link number 2 in HW Mode
+/** Offset 0x1467 - HD Audio Microphone Privacy applied for SoundWire Link number 2 in HW Mode
   HD Audio Microphone Privacy applied for SoundWire Link number 2 in HW Mode: 0: Disable, 1: Enable
   $EN_DIS
 **/
   UINT8                       PchHdaMicPrivacyHwModeSoundWire2;
 
-/** Offset 0x1460 - HD Audio Microphone Privacy applied for SoundWire Link number 3 in HW Mode
+/** Offset 0x1468 - HD Audio Microphone Privacy applied for SoundWire Link number 3 in HW Mode
   HD Audio Microphone Privacy applied for SoundWire Link number 3 in HW Mode: 0: Disable, 1: Enable
   $EN_DIS
 **/
   UINT8                       PchHdaMicPrivacyHwModeSoundWire3;
 
-/** Offset 0x1461 - HD Audio Microphone Privacy applied for SoundWire Link number 4 in HW Mode
+/** Offset 0x1469 - HD Audio Microphone Privacy applied for SoundWire Link number 4 in HW Mode
   HD Audio Microphone Privacy applied for SoundWire Link number 4 in HW Mode: 0: Disable, 1: Enable
   $EN_DIS
 **/
   UINT8                       PchHdaMicPrivacyHwModeSoundWire4;
 
-/** Offset 0x1462 - HD Audio Microphone Privacy applied for Dmic in HW Mode
+/** Offset 0x146A - HD Audio Microphone Privacy applied for Dmic in HW Mode
   HD Audio Microphone Privacy applied for Dmic in HW Mode: 0: Disable, 1: Enable
   $EN_DIS
 **/
   UINT8                       PchHdaMicPrivacyHwModeDmic;
 
-/** Offset 0x1463 - Reserved
+/** Offset 0x146B - Reserved
 **/
   UINT8                       Reserved60[13];
 
-/** Offset 0x1470 - Pointer to ChipsetInit Binary
+/** Offset 0x1478 - Pointer to ChipsetInit Binary
   ChipsetInit Binary Pointer.
 **/
   UINT64                      ChipsetInitBinPtr;
 
-/** Offset 0x1478 - Length of ChipsetInit Binary
+/** Offset 0x1480 - Length of ChipsetInit Binary
   ChipsetInit Binary Length.
 **/
   UINT32                      ChipsetInitBinLen;
 
-/** Offset 0x147C - Reserved
+/** Offset 0x1484 - Reserved
 **/
   UINT8                       Reserved61[36];
 } FSP_S_CONFIG;
@@ -2410,11 +2410,11 @@ typedef struct {
 **/
   FSP_S_CONFIG                FspsConfig;
 
-/** Offset 0x14A0
+/** Offset 0x14A8
 **/
   UINT8                       FspsUpdRsvd36[6];
 
-/** Offset 0x14A6
+/** Offset 0x14AE
 **/
   UINT16                      UpdTerminator;
 } FSPS_UPD;

From 6f35296975ee7b3822bafb7bfcc06c0525de47dc Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Mon, 10 Mar 2025 20:43:27 +0000
Subject: [PATCH 0360/3886] Update intel-microcode submodule to upstream main
 branch

Updating from commit id 8ac9378a8487 (2024-11-12):
  microcode-20241112 Release

to commit id 8a62de41c011 (2025-02-11):
  microcode-20250211 Release

This brings in 1 new commit:
8a62de41c0 microcode-20250211 Release

Change-Id: I3ba126335e4dc3deb93ea8e362ea354f18bbbf38
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86799
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
---
 3rdparty/intel-microcode | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/3rdparty/intel-microcode b/3rdparty/intel-microcode
index 8ac9378a84..8a62de41c0 160000
--- a/3rdparty/intel-microcode
+++ b/3rdparty/intel-microcode
@@ -1 +1 @@
-Subproject commit 8ac9378a84879e81c503e09f344560b3dd7f72df
+Subproject commit 8a62de41c011615d749f8e72bb906dddc72e56a8

From c93ac71883f623f8ba4f42a29fa44a417fc2bb6d Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Tue, 11 Mar 2025 20:23:58 +0000
Subject: [PATCH 0361/3886] mb/starlabs/lite/glk: Disable PMC device

These boards use BootGuard, which isn't fully working in coreboot as
it requires the bootblock to be relocatable.

Turn off the PMC to workaround the missing BootGuard requirements, so
that they will turn on when pressing the power button.

Change-Id: Idd03684d9fb4573fc160e17ac2c28c39bc8b2ddd
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86830
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
---
 src/mainboard/starlabs/lite/variants/glk/devicetree.cb | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/mainboard/starlabs/lite/variants/glk/devicetree.cb b/src/mainboard/starlabs/lite/variants/glk/devicetree.cb
index a8962af514..8de2d68622 100644
--- a/src/mainboard/starlabs/lite/variants/glk/devicetree.cb
+++ b/src/mainboard/starlabs/lite/variants/glk/devicetree.cb
@@ -65,7 +65,7 @@ chip soc/intel/apollolake
 				device generic 0 on end
 			end
 		end
-		device ref pmc		on  end
+		device ref pmc		off end
 		device ref p2sb		on  end
 		device ref fast_spi	on  end
 		device ref sram		on  end

From 53b53ddd1cb917c86dd68f5716ec00f6a0349192 Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Sun, 9 Mar 2025 20:49:27 -0500
Subject: [PATCH 0362/3886] util/chromeos/crosfirmware: Increase lookahead when
 parsing bios_image

Newer recovery images change the manifest format yet again, so increase
the lookhead when parsing the bios_image field to ensure we can find it.

TEST=run `./crosfirmware.sh craaskbowl` without erroring out

Change-Id: Idb1862e38a82f3cec8db55993ccf421cf3572c6f
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86777
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
---
 util/chromeos/crosfirmware.sh | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/util/chromeos/crosfirmware.sh b/util/chromeos/crosfirmware.sh
index 22fd6117ab..6dbac40394 100755
--- a/util/chromeos/crosfirmware.sh
+++ b/util/chromeos/crosfirmware.sh
@@ -116,8 +116,8 @@ extract_coreboot() {
 	elif [ -f "$_unpacked/manifest.json" ]; then
 		_version=$(grep -m1 -A4 "$BOARD\":" "$_unpacked/manifest.json" | grep -m1 "rw" |
 				sed 's/.*\(rw.*\)/\1/' | sed 's/.*\("Google.*\)/\1/' | cut -f2 -d'"')
-		_bios_image=$(grep -m1 -A7 "$BOARD\":" "$_unpacked/manifest.json" | grep -m1 "image" |
-				sed 's/.*"image": //' | cut -f2 -d'"')
+		_bios_image=$(grep -m1 -A10 "$BOARD\":" "$_unpacked/manifest.json" |
+				grep -m1 "image" | sed 's/.*"image": //' | cut -f2 -d'"')
 	else
 		_version=$(cat $_unpacked/VERSION | grep BIOS\ version: |
 			cut -f2 -d: | tr -d \ )

From 07d5f56db9519fd37610a03ce116714c578bd400 Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Mon, 10 Mar 2025 13:54:13 -0500
Subject: [PATCH 0363/3886] drivers/intel/mipi_camera: Add more platform_type
 enums

Add more platform type values. Values sourced from Slimbootloader and
various DSDT dumps on github.

Change-Id: If7ea46aad76dfedf89f764e60d9bf6061f53cbe1
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86794
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/drivers/intel/mipi_camera/chip.h | 7 ++++++-
 1 file changed, 6 insertions(+), 1 deletion(-)

diff --git a/src/drivers/intel/mipi_camera/chip.h b/src/drivers/intel/mipi_camera/chip.h
index 9aba729b32..92e66fd580 100644
--- a/src/drivers/intel/mipi_camera/chip.h
+++ b/src/drivers/intel/mipi_camera/chip.h
@@ -40,8 +40,13 @@ enum camera_device_type {
 };
 
 enum intel_camera_platform_type {
+	PLATFORM_BXT = 8,
 	PLATFORM_SKC = 9,
-	PLATFORM_CNL = 10
+	PLATFORM_CNL = 10,
+	PLATFORM_TGL = 12,
+	PLATFORM_ADL = 15,
+	PLATFORM_MTL = 16,
+	PLATFORM_LNL = 17
 };
 
 enum intel_camera_flash_type {

From f50be824a2ca7d05f44623bfe9ce415f611bc761 Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Mon, 10 Mar 2025 14:09:56 -0500
Subject: [PATCH 0364/3886] drivers/intel/mipi_camera: Fix size of SSDB struct

Drop duplicate/unused `mclk` field, which corrects the size of the SSDB
struct to 108 bytes. Size/fields confirmed by comparing to DSDT
dumps of UEFI firmware and SSDB struct in linux MIPI driver (ref:
/include/media/ipu-bridge.h).

Change-Id: Iea5b2138d2396e32bcecb3a48ab2b159a9b33345
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86795
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
---
 src/drivers/intel/mipi_camera/chip.h | 1 -
 1 file changed, 1 deletion(-)

diff --git a/src/drivers/intel/mipi_camera/chip.h b/src/drivers/intel/mipi_camera/chip.h
index 92e66fd580..d28a848eeb 100644
--- a/src/drivers/intel/mipi_camera/chip.h
+++ b/src/drivers/intel/mipi_camera/chip.h
@@ -190,7 +190,6 @@ struct intel_ssdb {
 	uint8_t mipi_define;			/* MIPI info defined in ACPI or
 						sensor driver */
 	uint32_t mclk_speed;			/* Clock info for sensor */
-	uint32_t mclk;				/* Clock info for sensor */
 	uint8_t control_logic_id;		/* PMIC device node used for
 						the camera sensor */
 	uint8_t mipi_data_format;		/* MIPI data format */

From ac3cb3189c156eba338341337588a9f979885f04 Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Sun, 25 Aug 2024 10:30:58 -0500
Subject: [PATCH 0365/3886] mb/google/brya/var/nissa: Select FSP_TYPE_IOT for
 non-ChromeOS builds

Select FSP_TYPE_IOT, so that Nissa-baseboard boards can be built using
FSP binaries from 3rdparty/fsp.

TEST=build/boot google/craask

Change-Id: I0ba45205e3af9daf7c41d393689d8f14d847a446
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86801
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
---
 src/mainboard/google/brya/Kconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/src/mainboard/google/brya/Kconfig b/src/mainboard/google/brya/Kconfig
index a630323984..9b730aeedf 100644
--- a/src/mainboard/google/brya/Kconfig
+++ b/src/mainboard/google/brya/Kconfig
@@ -90,6 +90,7 @@ config BOARD_GOOGLE_BASEBOARD_NISSA
 	select CHROMEOS_DRAM_PART_NUMBER_IN_CBI if CHROMEOS
 	select DRIVERS_AUDIO_SOF
 	select DRIVERS_INTEL_ISH
+	select FSP_TYPE_IOT if !CHROMEOS
 	select MAINBOARD_DISABLE_STAGE_CACHE
 	select MAINBOARD_HAS_EARLY_LIBGFXINIT
 	select MEMORY_SOLDERDOWN

From 4c2a4cd925e872971074bf433cbd6f5a02c2e41a Mon Sep 17 00:00:00 2001
From: Wisley Chen <wisley.chen@quanta.corp-partner.google.com>
Date: Tue, 11 Mar 2025 08:42:07 +0800
Subject: [PATCH 0366/3886] mb/google/brya/var/anahera: Disable smart card
 reader power saving

Disable smart card reader power saving as W/A to avoid detect issue

BUG=b:383375529
TEST=Check whether the smart card reader exists without a card inserted

localhost~# lsusb
Bus 004 Device 009: ID 2cb7:0007 Fibocom Wireless Inc. L850-GL
Bus 004 Device 001: ID 1d6b:0003 Linux Foundation 3.0 root hub
Bus 003 Device 010: ID 058f:9540 Alcor Micro Corp. AU9540 Smartcard Reader
Bus 003 Device 002: ID 0408:5479 Quanta Computer, Inc. HP 5M Camera
Bus 003 Device 012: ID 0bda:8153 Realtek Semiconductor Corp. USB 10/100/1000 LAN
Bus 003 Device 004: ID 8087:0033 Intel Corp.
Bus 003 Device 001: ID 1d6b:0002 Linux Foundation 2.0 root hub
Bus 002 Device 001: ID 1d6b:0003 Linux Foundation 3.0 root hub
Bus 001 Device 001: ID 1d6b:0002 Linux Foundation 2.0 root hub

Change-Id: Idfff67b8fadd2ca07572fb3dad8bdffbbf7acad0
Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86805
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
---
 src/mainboard/google/brya/variants/anahera/gpio.c | 7 +++++--
 1 file changed, 5 insertions(+), 2 deletions(-)

diff --git a/src/mainboard/google/brya/variants/anahera/gpio.c b/src/mainboard/google/brya/variants/anahera/gpio.c
index 9c7332011a..90b0bf8e52 100644
--- a/src/mainboard/google/brya/variants/anahera/gpio.c
+++ b/src/mainboard/google/brya/variants/anahera/gpio.c
@@ -61,8 +61,11 @@ static const struct pad_config override_gpio_table[] = {
 	PAD_CFG_GPO(GPP_E16, 1, DEEP),
 	/* E20 : USB_C1_LSX_SOC_TX ==> EN_PP3300_eMMC */
 	PAD_CFG_GPO(GPP_E20, 1, DEEP),
-	/* E22 : DDPA_CTRLCLK ==> SC_PWR_SV */
-	PAD_CFG_GPO(GPP_E22, 1, DEEP),
+	/*
+	 * E22 : DDPA_CTRLCLK ==> SC_PWR_SV
+	 * 0: normal mode; 1: power saving mode
+	 */
+	PAD_CFG_GPO(GPP_E22, 0, DEEP),
 	/* E23 : DDPA_CTRLDATA ==> NC */
 	PAD_NC(GPP_E23, NONE),
 

From 526af8030846ff7f8ff5a0a56a641118e4abb711 Mon Sep 17 00:00:00 2001
From: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com>
Date: Tue, 11 Mar 2025 10:46:12 +0900
Subject: [PATCH 0367/3886] mb/nissa/var/meliks: Support x32 memory
 configuration

Use GPP_E7 level to determine whether x32 memory configuration is
supported.

BUG=None
BRANCH=nissa
TEST=FW_NAME=meliks emerge-nissa coreboot

Change-Id: Iedaf3c4ff1b025a4d69eca1db32ef743066a4478
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86804
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/google/brya/Kconfig                  |  1 +
 src/mainboard/google/brya/variants/meliks/gpio.c   |  2 ++
 src/mainboard/google/brya/variants/meliks/memory.c | 14 ++++++++++++++
 3 files changed, 17 insertions(+)

diff --git a/src/mainboard/google/brya/Kconfig b/src/mainboard/google/brya/Kconfig
index 9b730aeedf..91d77ab2b9 100644
--- a/src/mainboard/google/brya/Kconfig
+++ b/src/mainboard/google/brya/Kconfig
@@ -363,6 +363,7 @@ config BOARD_GOOGLE_MELIKS
 	select BOARD_GOOGLE_BASEBOARD_NISSA
 	select DRIVERS_I2C_DA7219
 	select DRIVERS_INTEL_MIPI_CAMERA
+	select ENFORCE_MEM_CHANNEL_DISABLE
 	select SOC_INTEL_TWINLAKE
 
 config BOARD_GOOGLE_MITHRAX
diff --git a/src/mainboard/google/brya/variants/meliks/gpio.c b/src/mainboard/google/brya/variants/meliks/gpio.c
index 431b613c0a..6e11263075 100644
--- a/src/mainboard/google/brya/variants/meliks/gpio.c
+++ b/src/mainboard/google/brya/variants/meliks/gpio.c
@@ -22,6 +22,8 @@ static const struct pad_config override_gpio_table[] = {
 	/* D8  : SD_CLKREQ_ODL ==> NC */
 	PAD_NC(GPP_D8, NONE),
 
+	/* E7 : NC ==> GPP_E7_STRAP */
+	PAD_CFG_GPI_LOCK(GPP_E7, NONE, LOCK_CONFIG),
 	/* E14 : EDP_HPD ==> NC */
 	PAD_NC(GPP_E14, NONE),
 	/* E20 : HDMI_DDC_SCL ==> NC */
diff --git a/src/mainboard/google/brya/variants/meliks/memory.c b/src/mainboard/google/brya/variants/meliks/memory.c
index d7f73fb9a0..7fa58ae21f 100644
--- a/src/mainboard/google/brya/variants/meliks/memory.c
+++ b/src/mainboard/google/brya/variants/meliks/memory.c
@@ -95,3 +95,17 @@ int variant_memory_sku(void)
 
 	return gpio_base2_value(spd_gpios, ARRAY_SIZE(spd_gpios));
 }
+
+uint8_t mb_get_channel_disable_mask(void)
+{
+	/*
+	 * GPP_E7 High -> One RAM Chip
+	 * GPP_E7 Low  -> Two RAM Chip
+	 */
+	if (gpio_get(GPP_E7)) {
+		/* Disable all other channels except first two on each controller */
+		return (BIT(2) | BIT(3));
+	}
+
+	return 0;
+}

From c41af2d43c49b376d417232b5cb40e1fcff87ebe Mon Sep 17 00:00:00 2001
From: Jayvik Desai <jayvik@google.com>
Date: Mon, 10 Feb 2025 23:58:34 +0530
Subject: [PATCH 0368/3886] mb/google/fatcat/var/fatcat: Update THC Interrupt
 for Touchpad Development

This patch updates the TCH_PAD_INT_N GPP from A13 to F18

The Touch Pad's interrupt line (TCH_PAD_INT_N) was previously connected
to GPP_A13, This patch moves the interrupt line to GPP_F18, aligning it
with the THC1-i2c interface.

Both LPSS-i2c and THC1-i2c share SCL/SDA signals, with the exception of
the interrupt pin. This change ensures the interrupt pin shared between
both the interface.

The Tier-1 PMC GPE programming specifications limit us to configuring
three GPIO banks. Currently, GPP_A, GPP_D, and GPP_E are utilized, as
demonstrated in
[https://github.com/coreboot/coreboot/blob/main/src/mainboard/google/
fatcat/variants/baseboard/fatcat/devicetree.cb#L3]

We encounter a constraint when attempting to add GPP_F as an additional
Tier-1 GPIO due to the exhaustion of available PMC configuration
registers. However, the THC touchpad requires wake-capable registration,
necessitating a PMC GPE entry.

To resolve this, we have opted to configure GPP_F18 as an IOAPIC
interrupt. This solution provides a dedicated pin, avoiding the
complexities of GPIO shared IRQ masking. Furthermore, GPP_F18 supports
both interrupt (IRQ) and wake functionality, as defined by the ACPI
ACPI_IRQ_WAKE_LEVEL_LOW entry.

Snippet of change in runtime ASL code:
w/o cl:
`Name (_S0W, 0x03)  // _S0W: S0 Device Wake State
Name (_PRW, Package (0x02)  // _PRW: Power Resources for Wake
{
     0x0D,
     0x03
})`

w/ cl: no such entry

This patch also removed the GPP_F18 entry from the finger print sensor
config to avoid conflicts.

BUG=b:395160736
TEST=able to build google/fatcat. Verfied touchpad functionality

Change-Id: Ied917427225035a484a5873fa734f4c9f14277c0
Signed-off-by: Jayvik Desai <jayvik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86479
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
---
 .../google/fatcat/variants/fatcat/fw_config.c   | 17 ++++++++---------
 .../fatcat/variants/fatcat/overridetree.cb      |  3 +--
 2 files changed, 9 insertions(+), 11 deletions(-)

diff --git a/src/mainboard/google/fatcat/variants/fatcat/fw_config.c b/src/mainboard/google/fatcat/variants/fatcat/fw_config.c
index 18163bb63e..668950cde5 100644
--- a/src/mainboard/google/fatcat/variants/fatcat/fw_config.c
+++ b/src/mainboard/google/fatcat/variants/fatcat/fw_config.c
@@ -431,10 +431,12 @@ static const struct pad_config touchscreen_thc_spi_enable_pads[] = {
 };
 
 static const struct pad_config touchpad_thc_i2c_enable_pads[] = {
-	/* GPP_F12:     NF1: thc_i2c1_scl */
+	/* GPP_F12:     NF1: THC_I2C1_SCL */
 	PAD_CFG_NF(GPP_F12, NONE, DEEP, NF1),
-	/* GPP_F13:     NF1: thc_i2c1_sda */
+	/* GPP_F13:     NF1: THC_I2C1_SDA */
 	PAD_CFG_NF(GPP_F13, NONE, DEEP, NF1),
+	/* GPP_F18:     NF3: THC1_INT_N */
+	PAD_CFG_NF(GPP_F18, NONE, DEEP, NF3)
 };
 
 static const struct pad_config touchpad_lpss_i2c_enable_pads[] = {
@@ -442,8 +444,8 @@ static const struct pad_config touchpad_lpss_i2c_enable_pads[] = {
 	PAD_CFG_NF(GPP_F12, NONE, DEEP, NF8),
 	/* GPP_F13:     THC_I2C1_SDA_TCH_PAD */
 	PAD_CFG_NF(GPP_F13, NONE, DEEP, NF8),
-	/* GPP_A13:     TCH_PAD_INT_N */
-	PAD_CFG_GPI_IRQ_WAKE(GPP_A13, NONE, PWROK, EDGE_SINGLE, INVERT),
+	/* GPP_F18:     TCH_PAD_INT_N */
+	PAD_CFG_GPI_APIC(GPP_F18, NONE, PWROK, LEVEL, INVERT),
 };
 
 static const struct pad_config touchpad_i2c_disable_pads[] = {
@@ -451,8 +453,8 @@ static const struct pad_config touchpad_i2c_disable_pads[] = {
 	PAD_NC(GPP_F12, NONE),
 	/* GPP_F13:     THC_I2C1_SDA_TCH_PAD */
 	PAD_NC(GPP_F13, NONE),
-	/* GPP_A13:     TCH_PAD_INT_N */
-	PAD_NC(GPP_A13, NONE),
+	/* GPP_F18:     TCH_PAD_INT_N */
+	PAD_NC(GPP_F18, NONE),
 };
 
 static const struct pad_config ish_disable_pads[] = {
@@ -488,7 +490,6 @@ static const struct pad_config fp_disable_pads[] = {
 	PAD_NC(GPP_F14, NONE),
 	PAD_NC(GPP_F15, NONE),
 	PAD_NC(GPP_F16, NONE),
-	PAD_NC(GPP_F18, NONE),
 };
 
 static const struct pad_config fp_enable_pads[] = {
@@ -508,8 +509,6 @@ static const struct pad_config fp_enable_pads[] = {
 	PAD_CFG_NF(GPP_F15, NONE, DEEP, NF8),
 	/* GPP_F16:     GPSI0A_CLK */
 	PAD_CFG_NF(GPP_F16, NONE, DEEP, NF8),
-	/* GPP_F18:     NC */
-	PAD_NC(GPP_F18, NONE),
 };
 
 static const struct pad_config pre_mem_fp_enable_pads[] = {
diff --git a/src/mainboard/google/fatcat/variants/fatcat/overridetree.cb b/src/mainboard/google/fatcat/variants/fatcat/overridetree.cb
index cb4c21a1f7..bc0b9e26a3 100644
--- a/src/mainboard/google/fatcat/variants/fatcat/overridetree.cb
+++ b/src/mainboard/google/fatcat/variants/fatcat/overridetree.cb
@@ -821,8 +821,7 @@ chip soc/intel/pantherlake
 			chip drivers/i2c/hid
 				register "generic.hid" = ""HFW68H""
 				register "generic.desc" = ""Hynitron TOUCHPAD""
-				register "generic.irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_A13_IRQ)"
-				register "generic.wake" = "GPE0_DW0_13"
+				register "generic.irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_F18_IRQ)"
 				register "generic.uid" = "5"
 				register "generic.detect" = "1"
 				register "hid_desc_reg_offset" = "0x20"

From 58f162b07e0689cf516633e5496da0f5e880b122 Mon Sep 17 00:00:00 2001
From: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Date: Tue, 11 Mar 2025 15:06:18 +0800
Subject: [PATCH 0369/3886] mb/google/nissa/var/yavilla: Update eMMC DLL
 settings

Update eMMC DLL settings to prevent Ramaxel eMMC initialization error.

BUG=b:402260689
TEST=Verify on Ramaxel emmc warm/cold reboot stress test pass
     Verify on current emmc warm/cold reboot stress test pass

Change-Id: I2c560d63de7b596ee05ceb95726e4cb8001cf730
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86812
Reviewed-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
---
 src/mainboard/google/brya/variants/yavilla/overridetree.cb | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/mainboard/google/brya/variants/yavilla/overridetree.cb b/src/mainboard/google/brya/variants/yavilla/overridetree.cb
index be926179dc..015228e2c1 100644
--- a/src/mainboard/google/brya/variants/yavilla/overridetree.cb
+++ b/src/mainboard/google/brya/variants/yavilla/overridetree.cb
@@ -76,7 +76,7 @@ chip soc/intel/alderlake
 	# [22:16] steps of delay for DDR50, each 125ps, range: 0 - 78.
 	# [14:8] steps of delay for SDR25/HS50, each 125ps, range: 0 - 119.
 	# [6:0] steps of delay for SDR12, each 125ps, range: 0 - 119.
-	register "common_soc_config.emmc_dll.emmc_rx_cmd_data_cntl1" = "0x1C171733"
+	register "common_soc_config.emmc_dll.emmc_rx_cmd_data_cntl1" = "0x1C17171B"
 
 	# EMMC RX CMD/DATA Delay 2
 	# Refer to EDS-Vol2-42.3.12.

From ad4c2b3282632b66a8c87e567099741003e13740 Mon Sep 17 00:00:00 2001
From: Patrick Rudolph <patrick.rudolph@9elements.com>
Date: Wed, 26 Feb 2025 13:00:40 +0100
Subject: [PATCH 0370/3886] soc/intel/xeon_sp/spr: Use default turbo ratio

Allow a board to use the default turbo ratio by not specifying
turbo_ratio_limit and turbo_ratio_limit_cores in the devicetree.cb.

TEST: Intel PTAT tool no longer complains about 0Mhz turbo frequency.

Change-Id: Ib8fbc78997fc7f8e6c80b2029d63b70f6117542e
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86604
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
---
 src/soc/intel/xeon_sp/spr/cpu.c | 16 ++++++++++------
 1 file changed, 10 insertions(+), 6 deletions(-)

diff --git a/src/soc/intel/xeon_sp/spr/cpu.c b/src/soc/intel/xeon_sp/spr/cpu.c
index febc72b8bf..383bf5f512 100644
--- a/src/soc/intel/xeon_sp/spr/cpu.c
+++ b/src/soc/intel/xeon_sp/spr/cpu.c
@@ -95,14 +95,18 @@ static void each_cpu_init(struct device *cpu)
 	wrmsr(MSR_VR_CURRENT_CONFIG, msr);
 
 	/* Set Turbo Ratio Limits */
-	msr.lo = chip_config->turbo_ratio_limit & 0xffffffff;
-	msr.hi = (chip_config->turbo_ratio_limit >> 32) & 0xffffffff;
-	wrmsr(MSR_TURBO_RATIO_LIMIT, msr);
+	if (chip_config->turbo_ratio_limit) {
+		msr.lo = chip_config->turbo_ratio_limit & 0xffffffff;
+		msr.hi = (chip_config->turbo_ratio_limit >> 32) & 0xffffffff;
+		wrmsr(MSR_TURBO_RATIO_LIMIT, msr);
+	}
 
 	/* Set Turbo Ratio Limit Cores */
-	msr.lo = chip_config->turbo_ratio_limit_cores & 0xffffffff;
-	msr.hi = (chip_config->turbo_ratio_limit_cores >> 32) & 0xffffffff;
-	wrmsr(MSR_TURBO_RATIO_LIMIT_CORES, msr);
+	if (chip_config->turbo_ratio_limit_cores) {
+		msr.lo = chip_config->turbo_ratio_limit_cores & 0xffffffff;
+		msr.hi = (chip_config->turbo_ratio_limit_cores >> 32) & 0xffffffff;
+		wrmsr(MSR_TURBO_RATIO_LIMIT_CORES, msr);
+	}
 
 	/* Set energy policy */
 	msr = rdmsr(MSR_ENERGY_PERF_BIAS_CONFIG);

From 339d1a26ad9f1e1599a8da74060f04d0ff3dd414 Mon Sep 17 00:00:00 2001
From: Yidi Lin <yidilin@chromium.org>
Date: Wed, 5 Mar 2025 17:03:45 +0800
Subject: [PATCH 0371/3886] lib/edid: Update the condition check for extension
 block count

According to E-EDID A.2_revised_2020.pdf, block maps are optional in
EDID 1.4. If block maps are used then 254 is the maximum number.
Otherwise, 255 is the maximum number. For now, we simply print the
number of extension blocks.

BUG=b:392040003
BRANCH=rauru
TEST=Verify with the panel containing two EDID extension blocks

Change-Id: I2458e3493e74f91af6422b36285bb95e438a29f1
Signed-off-by: Yidi Lin <yidilin@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86723
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
---
 src/lib/edid.c | 20 ++++++--------------
 1 file changed, 6 insertions(+), 14 deletions(-)

diff --git a/src/lib/edid.c b/src/lib/edid.c
index c294a3f055..7de2788a86 100644
--- a/src/lib/edid.c
+++ b/src/lib/edid.c
@@ -32,7 +32,6 @@ struct edid_context {
 	int has_valid_week;
 	int has_valid_year;
 	int has_valid_detailed_blocks;
-	int has_valid_extension_count;
 	int has_valid_descriptor_ordering;
 	int has_valid_descriptor_pad;
 	int has_valid_range_descriptor;
@@ -1444,15 +1443,12 @@ int decode_edid(unsigned char *edid, int size, struct edid *out)
 		}
 	}
 
-	/* check this, 1.4 verification guide says otherwise */
-	if (edid[0x7e]) {
-		printk(BIOS_SPEW, "Has %d extension blocks\n", edid[0x7e]);
-		/* 2 is impossible because of the block map */
-		if (edid[0x7e] != 2)
-			c.has_valid_extension_count = 1;
-	} else {
-		c.has_valid_extension_count = 1;
-	}
+	/* According to E-EDID A.2_revised_2020.pdf, block maps are optional
+	 * in EDID 1.4. If block maps are used then 254 is the maximum number.
+	 * Otherwise, 255 is the maximum number. For now, we simply print the
+	 * number of extension blocks.
+	 */
+	printk(BIOS_SPEW, "Has %d extension blocks\n", edid[0x7e]);
 
 	printk(BIOS_SPEW, "Checksum\n");
 	c.has_valid_checksum = do_checksum(edid);
@@ -1558,7 +1554,6 @@ int decode_edid(unsigned char *edid, int size, struct edid *out)
 	    !c.has_valid_week ||
 	    !c.has_valid_detailed_blocks ||
 	    !c.has_valid_dummy_block ||
-	    !c.has_valid_extension_count ||
 	    !c.has_valid_descriptor_ordering ||
 	    !c.has_valid_range_descriptor ||
 	    !c.manufacturer_name_well_formed) {
@@ -1581,9 +1576,6 @@ int decode_edid(unsigned char *edid, int size, struct edid *out)
 				"\tDetailed blocks filled with garbage\n");
 		if (!c.has_valid_dummy_block)
 			printk(BIOS_ERR, "\tDummy block filled with garbage\n");
-		if (!c.has_valid_extension_count)
-			printk(BIOS_ERR,
-				"\tImpossible extension block count\n");
 		if (!c.manufacturer_name_well_formed)
 			printk(BIOS_ERR,
 				"\tManufacturer name field contains garbage\n");

From abec7ab276dab6375efe628fdb5f754c2c79d337 Mon Sep 17 00:00:00 2001
From: Yidi Lin <yidilin@chromium.org>
Date: Wed, 19 Feb 2025 18:27:26 +0800
Subject: [PATCH 0372/3886] lib/edid: Support DisplayID 2.0 extension
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Add support for DisplayID 2.0 extension. Right now, the implementation
only supports 'Type VII – Detailed timing' data block decoding.

Reference: 'DisplayID v2.1a.pdf'

BUG=b:392040003
BRANCH=rauru
TEST=Check FW screen on a panel than supports Display ID 2.0

Change-Id: I1b8a5ab3ada5c8eacc7b6dde3d33ec72b3790960
Signed-off-by: Yidi Lin <yidilin@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86724
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
---
 src/lib/edid.c           | 175 +++++++++++++++++++++++++++++++++++++++
 src/lib/edid_displayid.h |  56 +++++++++++++
 2 files changed, 231 insertions(+)
 create mode 100644 src/lib/edid_displayid.h

diff --git a/src/lib/edid.c b/src/lib/edid.c
index 7de2788a86..aa474a6dd7 100644
--- a/src/lib/edid.c
+++ b/src/lib/edid.c
@@ -10,11 +10,14 @@
 #include <commonlib/helpers.h>
 #include <console/console.h>
 #include <ctype.h>
+#include <stdbool.h>
 #include <stdint.h>
 #include <string.h>
 #include <edid.h>
 #include <vbe.h>
 
+#include "edid_displayid.h"
+
 struct edid_context {
 	int claims_one_point_oh;
 	int claims_one_point_two;
@@ -941,6 +944,173 @@ parse_cea(struct edid *out, unsigned char *x, struct edid_context *c)
 	return ret;
 }
 
+/* DisplayID extension code */
+static const char * const displayid_aspect[] = {
+	"1:1",
+	"5:4",
+	"4:3",
+	"15:9",
+	"16:9",
+	"16:10",
+	"64:27",
+	"256:135",
+};
+
+static void displayid_detailed_timing(
+	struct displayid_type_7_detailed_timing_desc *desc,
+	struct edid *out)
+{
+	unsigned int pixel_clock = (desc->pixel_clock[0] |
+				    (desc->pixel_clock[1] << 8) |
+				    (desc->pixel_clock[2] << 16)) + 1;
+
+	unsigned int hactive = (desc->hactive[0] | desc->hactive[1] << 8) + 1;
+	unsigned int hblank = (desc->hblank[0] | desc->hblank[1] << 8) + 1;
+	unsigned int hsync = (desc->hfront_porch[0] | (desc->hfront_porch[1] & 0x7f) << 8) + 1;
+	unsigned int hsync_width = (desc->hsync_width[0] | desc->hsync_width[1] << 8) + 1;
+
+	unsigned int vactive = (desc->vactive[0] | desc->vactive[1] << 8) + 1;
+	unsigned int vblank = (desc->vblank[0] | desc->vblank[1] << 8) + 1;
+	unsigned int vsync = (desc->vfront_porch[0] | (desc->vfront_porch[1] & 0x7f) << 8) + 1;
+	unsigned int vsync_width = (desc->vsync_width[0] | desc->vsync_width[1] << 8) + 1;
+
+	bool hsync_positive = (desc->hfront_porch[1] >> 7) & 0x1;
+	bool vsync_positive = (desc->vfront_porch[1] >> 7) & 0x1;
+
+	unsigned int aspect = desc->flags & 0xF;
+	bool is_preferred = desc->flags & 0x80;
+
+	out->mode.pixel_clock = pixel_clock;
+	out->mode.lvds_dual_channel = (out->mode.pixel_clock >= 95000);
+	out->mode.ha = hactive;
+	out->mode.hbl = hblank;
+	out->mode.hso = hsync;
+	out->mode.hspw = hsync_width;
+
+	out->mode.va = vactive;
+	out->mode.vbl = vblank;
+	out->mode.vso = vsync;
+	out->mode.vspw = vsync_width;
+
+	out->mode.phsync = hsync_positive ? '+' : '-';
+	out->mode.pvsync = vsync_positive ? '+' : '-';
+
+	printk(BIOS_SPEW,
+	       "Detailed mode: clock %d KHz,\n"
+	       "               ha: %u hso: %u hspw: %u hbl: %u\n"
+	       "               va: %u vso: %u vspw: %u vbl: %u\n"
+	       "               %chsync %cvsync (aspect %s%s)\n",
+	       out->mode.pixel_clock,
+	       out->mode.ha, out->mode.hso, out->mode.hspw, out->mode.hbl,
+	       out->mode.va, out->mode.vso, out->mode.vspw, out->mode.vbl,
+	       out->mode.phsync, out->mode.pvsync,
+	       (aspect >= ARRAY_SIZE(displayid_aspect)) ? "undefined" : displayid_aspect[aspect],
+	       is_preferred ? ", preferred" : "");
+}
+
+static int displayid_type_7_timing_block(
+	struct edid *result_edid,
+	unsigned char *x,
+	struct edid_context *c,
+	int index)
+{
+	struct edid tmp;
+
+	struct displayid_type_7_detailed_timing_block *block;
+	struct displayid_type_7_detailed_timing_desc *desc;
+	int desc_count;
+
+	block = (struct displayid_type_7_detailed_timing_block *)&x[index];
+	desc_count = block->header.length / sizeof(*desc);
+
+	if (block->header.length % sizeof(*desc)) {
+		printk(BIOS_ERR, "%s: the length is not a multiple of %zu\n",
+		       __func__, sizeof(*desc));
+		return 1;
+	}
+
+	tmp = *result_edid;
+
+	for (int i = 0; i < desc_count; i++) {
+		desc = &block->descs[i];
+		displayid_detailed_timing(desc, &tmp);
+
+		c->did_detailed_timing = 1;
+		if ((desc->flags & 0x80) && !c->has_preferred_timing) {
+			c->has_preferred_timing = 1;
+			*result_edid = tmp;
+		}
+	}
+
+	return 0;
+}
+
+static int validate_section_header(unsigned char *x, int index)
+{
+	int i;
+	size_t section_length;
+	struct displayid_section_header *sh = (struct displayid_section_header *)&x[index];
+
+	unsigned char sum = 0;
+
+	/* +1 for the Display ID section checksum */
+	section_length = sizeof(*sh) + sh->length + 1;
+
+	/* Reserve 1 byte for extension block checksum */
+	if (section_length > 128 - 1 - index)
+		return 1;
+
+	for (i = 0; i < section_length; i++)
+		sum += x[i + index];
+
+	if (sum) {
+		printk(BIOS_ERR, "%s: checksum invalid\n", __func__);
+		return 1;
+	}
+
+	return 0;
+}
+
+static int parse_displayid(
+	struct edid *result_edid,
+	unsigned char *x,
+	struct edid_context *c)
+{
+	int ret = 0;
+	int index = 1;
+
+	struct displayid_section_header *sh = (struct displayid_section_header *)&x[index];
+	struct displayid_block_header *bh;
+
+	if (validate_section_header(x, index))
+		return 1;
+
+	/* Support Display ID structure 2.0 only */
+	if (sh->revision != DISPLAY_ID_STRUCTURE_VERSION_20) {
+		printk(BIOS_SPEW, "Unsupported Display ID revison: %x\n", sh->revision);
+		goto validate_checksum;
+	}
+
+	index += sizeof(*sh);
+	while (index < 1 + sh->length + sizeof(*sh)) {
+		bh = (struct displayid_block_header *)&x[index];
+		if (index + sizeof(*bh) > sh->length ||
+		    index + sizeof(*bh) + bh->length > sh->length)
+			break;
+
+		if (bh->tag == DATA_BLOCK_V2_TYPE_7_DETAILED_TIMING)
+			displayid_type_7_timing_block(result_edid, x, c, index);
+		else
+			printk(BIOS_SPEW, "%s: Unsupported data block tag %x\n",
+			       __func__, bh->tag);
+		index += sizeof(*bh) + bh->length;
+	}
+
+validate_checksum:
+	c->has_valid_checksum &= do_checksum(x);
+	return ret;
+}
+
 /* generic extension code */
 
 static void
@@ -973,6 +1143,11 @@ parse_extension(struct edid *out, unsigned char *x, struct edid_context *c)
 	case 0x60:
 		printk(BIOS_SPEW, "DPVL extension block\n");
 		break;
+	case 0x70:
+		printk(BIOS_SPEW, "DisplayID extension block\n");
+		extension_version(out, x);
+		conformant_extension = parse_displayid(out, x, c);
+		break;
 	case 0xF0:
 		printk(BIOS_SPEW, "Block map\n");
 		break;
diff --git a/src/lib/edid_displayid.h b/src/lib/edid_displayid.h
new file mode 100644
index 0000000000..bfa8fa042e
--- /dev/null
+++ b/src/lib/edid_displayid.h
@@ -0,0 +1,56 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef __EDID_DISPLAYID_H__
+#define __EDID_DISPLAYID_H__
+
+/* DisplayID section structure, version 2.0 */
+#define DISPLAY_ID_STRUCTURE_VERSION_20		0x20
+
+/* Data block types */
+#define DATA_BLOCK_V2_PRODUCT_ID			0x20
+#define DATA_BLOCK_V2_DISPLAY_PARAMETERS		0x21
+#define DATA_BLOCK_V2_TYPE_7_DETAILED_TIMING		0x22
+#define DATA_BLOCK_V2_TYPE_8_ENUMERATED_TIMING		0x23
+#define DATA_BLOCK_V2_TYPE_9_FORMULA_TIMING		0x24
+#define DATA_BLOCK_V2_DYNAMIC_VIDEO_TIMING		0x25
+#define DATA_BLOCK_V2_DISPLAY_INTERFACE_FEATURES	0x26
+#define DATA_BLOCK_V2_STEREO_DISPLAY_INTERFACE		0x27
+#define DATA_BLOCK_V2_TILED_DISPLAY_TOPOLOGY		0x28
+#define DATA_BLOCK_V2_CONTAINER_ID			0x29
+#define DATA_BLOCK_V2_VENDOR_SPECIFIC			0x7E
+#define DATA_BLOCK_V2_CTA_DISPLAY_ID			0x81
+
+struct displayid_section_header {
+	u8 revision;
+	u8 length;
+	u8 product_type;
+	u8 extension_count;
+} __packed;
+
+struct displayid_block_header {
+	u8 tag;
+	u8 revison;
+	u8 length;
+} ___packed;
+
+struct displayid_type_7_detailed_timing_desc {
+	u8 pixel_clock[3];
+	u8 flags;
+	u8 hactive[2];
+	u8 hblank[2];
+	u8 hfront_porch[2];
+	u8 hsync_width[2];
+	u8 vactive[2];
+	u8 vblank[2];
+	u8 vfront_porch[2];
+	u8 vsync_width[2];
+} __packed;
+_Static_assert(sizeof(struct displayid_type_7_detailed_timing_desc) == 20,
+	       "The size does not meet spec");
+
+struct displayid_type_7_detailed_timing_block {
+	struct displayid_block_header header;
+	struct displayid_type_7_detailed_timing_desc descs[];
+};
+
+#endif /* __EDID_DISPLAYID_H__ */

From f864a192e3de07c246c1f595085b657e825742bc Mon Sep 17 00:00:00 2001
From: Bincai Liu <bincai.liu@mediatek.corp-partner.google.com>
Date: Thu, 13 Feb 2025 23:19:44 +0800
Subject: [PATCH 0373/3886] soc/mediatek/mt8196: Support 512 bytes EDID

Refine dptx_get_edid function to read extension edid to bring up 2.8k
120hz OLED panel.

BRANCH=rauru
BUG=b:392040003
TEST=check edp training pass and show log:
EQ training pass

Change-Id: If35782950ae02d892ea697580fa4991595c21533
Signed-off-by: Bincai Liu <bincai.liu@mediatek.corp-partner.google.com>
Signed-off-by: Yidi Lin <yidilin@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86779
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/soc/mediatek/common/dp/dptx_common.c      | 29 ++++++++++++++++---
 .../common/dp/include/soc/dptx_common.h       |  4 ++-
 2 files changed, 28 insertions(+), 5 deletions(-)

diff --git a/src/soc/mediatek/common/dp/dptx_common.c b/src/soc/mediatek/common/dp/dptx_common.c
index b43bf51ae1..ac8f4527c2 100644
--- a/src/soc/mediatek/common/dp/dptx_common.c
+++ b/src/soc/mediatek/common/dp/dptx_common.c
@@ -73,17 +73,38 @@ bool dptx_auxread_dpcd(struct mtk_dp *mtk_dp, u8 cmd, u32 dpcd_addr,
 int dptx_get_edid(struct mtk_dp *mtk_dp, struct edid *out)
 {
 	int ret;
-	u8 edid[ONE_BLOCK_SIZE];
+	u8 edid[EDID_BUF_SIZE];
 	u8 tmp = 0;
+	u8 extblock = 0;
+	size_t total_size;
 
 	dptx_auxwrite_dpcd(mtk_dp, DP_AUX_I2C_WRITE, 0x50, 0x1, &tmp);
 
-	for (tmp = 0; tmp < ONE_BLOCK_SIZE / DP_AUX_MAX_PAYLOAD_BYTES; tmp++)
+	/* Read 1st block */
+	for (tmp = 0; tmp < EDID_BLOCK_SIZE / DP_AUX_MAX_PAYLOAD_BYTES; tmp++)
 		dptx_auxread_dpcd(mtk_dp, DP_AUX_I2C_READ,
 				  0x50, DP_AUX_MAX_PAYLOAD_BYTES,
-				  edid + tmp * 16);
+				  edid + tmp * DP_AUX_MAX_PAYLOAD_BYTES);
 
-	ret = decode_edid(edid, ONE_BLOCK_SIZE, out);
+	extblock = edid[EDID_EXT_BLOCK_COUNT];
+	total_size = EDID_BLOCK_SIZE * (1 + extblock);
+
+	if (total_size > EDID_BUF_SIZE) {
+		printk(BIOS_WARNING, "The edid block size(%zu) is larger than %u bytes\n",
+		       total_size, EDID_BUF_SIZE);
+		printk(BIOS_WARNING, "Read first %u bytes only\n", EDID_BUF_SIZE);
+		total_size = EDID_BUF_SIZE;
+	}
+
+	if (total_size > EDID_BLOCK_SIZE) {
+		for (tmp = EDID_BLOCK_SIZE / DP_AUX_MAX_PAYLOAD_BYTES;
+		     tmp < total_size / DP_AUX_MAX_PAYLOAD_BYTES; tmp++)
+			dptx_auxread_dpcd(mtk_dp, DP_AUX_I2C_READ,
+					  0x50, DP_AUX_MAX_PAYLOAD_BYTES,
+					  edid + tmp * DP_AUX_MAX_PAYLOAD_BYTES);
+	}
+
+	ret = decode_edid(edid, total_size, out);
 	if (ret != EDID_CONFORMANT) {
 		printk(BIOS_ERR, "failed to decode edid(%d).\n", ret);
 		return -1;
diff --git a/src/soc/mediatek/common/dp/include/soc/dptx_common.h b/src/soc/mediatek/common/dp/include/soc/dptx_common.h
index d3f799187a..2ea070eca7 100644
--- a/src/soc/mediatek/common/dp/include/soc/dptx_common.h
+++ b/src/soc/mediatek/common/dp/include/soc/dptx_common.h
@@ -8,7 +8,8 @@
 #define ENABLE_DPTX_EF_MODE		0x1
 #define DPTX_AUX_SET_ENAHNCED_FRAME	0x80
 
-#define ONE_BLOCK_SIZE			128
+#define EDID_BLOCK_SIZE			128
+#define EDID_BUF_SIZE			(EDID_BLOCK_SIZE * 4)
 
 #define DP_LINK_CONSTANT_N_VALUE	0x8000
 #define DP_LINK_STATUS_SIZE		6
@@ -38,6 +39,7 @@
 #define DP_EDP_14		0x03
 #define DP_EDP_14a		0x04
 #define DP_EDP_14b		0x05
+#define EDID_EXT_BLOCK_COUNT	0x7E
 
 /* Receiver Capability */
 #define DP_DPCD_REV		0x000

From e91e0d0ea428c69f4c67a635b92c7801f06d7377 Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Tue, 4 Mar 2025 09:19:39 -0600
Subject: [PATCH 0374/3886] Revert "mb/starlabs/byte: Update the VBT from 249
 to 251"

This reverts commit aeb04808c74eaab799b65c64eb30ff39aab1dbcc.

This fixes HDMI output with FSP MR5.

Change-Id: I277c802544b78677cce2e059286feba79bb8bf5c
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86827
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
---
 .../starlabs/byte_adl/variants/mk_ii/data.vbt | Bin 9216 -> 9216 bytes
 1 file changed, 0 insertions(+), 0 deletions(-)

diff --git a/src/mainboard/starlabs/byte_adl/variants/mk_ii/data.vbt b/src/mainboard/starlabs/byte_adl/variants/mk_ii/data.vbt
index 6eca303fbc8e5718e226d2830851118d2b7e675b..aa4ea41575c2d078c54535db011da581d6f931e0 100644
GIT binary patch
delta 71
zcmZqhXz-XI#r&ATVDd*M;f)5OjN%Rq3=Awl%m}6(fNVwv2L{H;iENsaTNw?R7#Jq+
VU{qzglrZ@|qbMW8=C6$0N&p%84>|w<

delta 106
zcmZqhXz-XI#k`-vU~(d(@J0hsMmr9M1_llW79e&2Vg(=;0AeN}W&~o87z0q20mxzi
p$}#|D8Gy13Kv@tmxtY<JiA`ei4n|d=;N<&^qKpEYzcO+w0RZb<4XpqG


From 05ad11216c5c79f637462bc6206df757524e9186 Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Wed, 12 Mar 2025 10:59:15 +0000
Subject: [PATCH 0375/3886] mb/starlabs/starbook/mtl: Correct comments for UART
 GPIOs

Change-Id: I894d871acfb3f21114d18b26c3897a17358d3822
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86842
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
---
 src/mainboard/starlabs/starbook/variants/mtl/gpio.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/mainboard/starlabs/starbook/variants/mtl/gpio.c b/src/mainboard/starlabs/starbook/variants/mtl/gpio.c
index d330400fc2..48b4276079 100644
--- a/src/mainboard/starlabs/starbook/variants/mtl/gpio.c
+++ b/src/mainboard/starlabs/starbook/variants/mtl/gpio.c
@@ -4,9 +4,9 @@
 
 /* Early pad configuration in bootblock */
 const struct pad_config early_gpio_table[] = {
-	/* H10:	UART0 RXD			*/
+	/* H08:	UART0 RXD			*/
 	PAD_CFG_NF(GPP_H08, NONE, DEEP, NF1),
-	/* H11:	UART0 TXD			*/
+	/* H09:	UART0 TXD			*/
 	PAD_CFG_NF(GPP_H09, NONE, DEEP, NF1),
 
 	/* C00:	SMB_CLK				*/

From d6caf33c6f3654b633af1af5a20ebf25108cccf4 Mon Sep 17 00:00:00 2001
From: Felix Singer <felixsinger@posteo.net>
Date: Tue, 11 Mar 2025 01:36:09 +0100
Subject: [PATCH 0376/3886] util/scripts/update_submodules: Rework default
 branch detection

Instead of guessing the default branch by iterating over a list of
branch names, use the branch that is configured as default by upstream.

Change-Id: I628b5a4e5228870c54719577e32dae169b0ceb2e
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86803
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
---
 util/scripts/update_submodules | 8 +-------
 1 file changed, 1 insertion(+), 7 deletions(-)

diff --git a/util/scripts/update_submodules b/util/scripts/update_submodules
index 48bb7f71bb..cbf2364ebe 100755
--- a/util/scripts/update_submodules
+++ b/util/scripts/update_submodules
@@ -108,13 +108,7 @@ main() {
 			git fetch 2>/dev/null
 		fi
 
-		declare -a branches=("origin/main" "origin/master" "origin/trunk")
-		for branch in "${branches[@]}"; do
-			if git branch -a | grep "${branch}" > /dev/null; then
-				branch_name="${branch}"
-				break
-			fi
-		done
+		branch_name="$(git symbolic-ref refs/remotes/origin/HEAD --short)"
 
 		updated_commit_id="$(git log --pretty='%h' -n 1 --abbrev=12 "${branch_name}" -- )"
 		updated_commit_description="$(git log --pretty='%ci - (%s)' -n 1 "${updated_commit_id}")"

From 151e9910652aeceb829c217f01f2d16d69d2a530 Mon Sep 17 00:00:00 2001
From: Robert Chen <robert.chen@quanta.corp-partner.google.com>
Date: Fri, 7 Mar 2025 06:01:55 -0500
Subject: [PATCH 0377/3886] mb/google/dedede/var/drawcia: add memory
 NT6AP512T32BL-J1

Generate SPD id for Nanya memory NT6AP512T32BL-J1

BUG=b:401424949
TEST=go run ./util/spd_tools/src/part_id_gen/part_id_gen.go JSL lp4x \
src/mainboard/google/dedede/variants/drawcia/memory/ \
src/mainboard/google/dedede/variants/drawcia/memory/mem_parts_used.txt

Change-Id: Icb1a6894307bd27c7d5ea25adb6cf0c8514c661c
Signed-off-by: Robert Chen <robert.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86764
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 .../google/dedede/variants/drawcia/memory/Makefile.mk          | 3 ++-
 .../dedede/variants/drawcia/memory/dram_id.generated.txt       | 3 ++-
 .../google/dedede/variants/drawcia/memory/mem_parts_used.txt   | 1 +
 3 files changed, 5 insertions(+), 2 deletions(-)

diff --git a/src/mainboard/google/dedede/variants/drawcia/memory/Makefile.mk b/src/mainboard/google/dedede/variants/drawcia/memory/Makefile.mk
index f975bfb463..cf6e6b1756 100644
--- a/src/mainboard/google/dedede/variants/drawcia/memory/Makefile.mk
+++ b/src/mainboard/google/dedede/variants/drawcia/memory/Makefile.mk
@@ -1,7 +1,8 @@
 # SPDX-License-Identifier: GPL-2.0-or-later
 # This is an auto-generated file. Do not edit!!
 # Generated by:
-# ./util/spd_tools/bin/part_id_gen JSL lp4x src/mainboard/google/dedede/variants/drawcia/memory src/mainboard/google/dedede/variants/drawcia/memory/mem_parts_used.txt
+# /tmp/go-build2022533761/b001/exe/part_id_gen JSL lp4x src/mainboard/google/dedede/variants/drawcia/memory/ src/mainboard/google/dedede/variants/drawcia/memory/mem_parts_used.txt
 
 SPD_SOURCES =
 SPD_SOURCES += spd/lp4x/set-1/spd-1.hex      # ID = 0(0b0000)  Parts = MT53E512M32D2NP-046 WT:E, H9HCNNNBKMMLXR-NEE, K4U6E3S4AA-MGCR, MT53E512M32D1NP-046 WT:B, H54G46CYRBX267, K4U6E3S4AB-MGCL, K4U6E3S4AA-MGCL
+SPD_SOURCES += spd/lp4x/set-1/spd-11.hex      # ID = 1(0b0001)  Parts = NT6AP512T32BL-J1
diff --git a/src/mainboard/google/dedede/variants/drawcia/memory/dram_id.generated.txt b/src/mainboard/google/dedede/variants/drawcia/memory/dram_id.generated.txt
index 8a3c5c8703..98ff75c305 100644
--- a/src/mainboard/google/dedede/variants/drawcia/memory/dram_id.generated.txt
+++ b/src/mainboard/google/dedede/variants/drawcia/memory/dram_id.generated.txt
@@ -1,7 +1,7 @@
 # SPDX-License-Identifier: GPL-2.0-or-later
 # This is an auto-generated file. Do not edit!!
 # Generated by:
-# ./util/spd_tools/bin/part_id_gen JSL lp4x src/mainboard/google/dedede/variants/drawcia/memory src/mainboard/google/dedede/variants/drawcia/memory/mem_parts_used.txt
+# /tmp/go-build2022533761/b001/exe/part_id_gen JSL lp4x src/mainboard/google/dedede/variants/drawcia/memory/ src/mainboard/google/dedede/variants/drawcia/memory/mem_parts_used.txt
 
 DRAM Part Name                 ID to assign
 MT53E512M32D2NP-046 WT:E       0 (0000)
@@ -11,3 +11,4 @@ MT53E512M32D1NP-046 WT:B       0 (0000)
 H54G46CYRBX267                 0 (0000)
 K4U6E3S4AB-MGCL                0 (0000)
 K4U6E3S4AA-MGCL                0 (0000)
+NT6AP512T32BL-J1               1 (0001)
diff --git a/src/mainboard/google/dedede/variants/drawcia/memory/mem_parts_used.txt b/src/mainboard/google/dedede/variants/drawcia/memory/mem_parts_used.txt
index 4a3e217521..af500eeaaa 100644
--- a/src/mainboard/google/dedede/variants/drawcia/memory/mem_parts_used.txt
+++ b/src/mainboard/google/dedede/variants/drawcia/memory/mem_parts_used.txt
@@ -5,3 +5,4 @@ MT53E512M32D1NP-046 WT:B
 H54G46CYRBX267
 K4U6E3S4AB-MGCL
 K4U6E3S4AA-MGCL
+NT6AP512T32BL-J1

From 6d669659951bba7a3320f56dc6952b71dbb93fea Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Tue, 11 Mar 2025 17:57:13 -0500
Subject: [PATCH 0378/3886] soc/intel/meteorlake: Condition
 DISPLAY_FSP_VERSION_INFO_2 on !FSP_USE_REPO

The MTL FSP headers in github do not include FirmwareVersionInfo.h, so
DISPLAY_FSP_VERSION_INFO_2 needs to be deselected when using FSP
binaries from the repo.

TEST=tested with subsequent patch

Change-Id: I53dae842f545b3d4fe34ded57916f33716777a7d
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86835
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/soc/intel/meteorlake/Kconfig | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/soc/intel/meteorlake/Kconfig b/src/soc/intel/meteorlake/Kconfig
index 2a692740c3..5d1b3fe6d1 100644
--- a/src/soc/intel/meteorlake/Kconfig
+++ b/src/soc/intel/meteorlake/Kconfig
@@ -13,7 +13,7 @@ config SOC_INTEL_METEORLAKE
 	select CPU_SUPPORTS_PM_TIMER_EMULATION
 	select DEFAULT_SOFTWARE_CONNECTION_MANAGER if MAINBOARD_HAS_CHROMEOS
 	select DEFAULT_X2APIC_LATE_WORKAROUND
-	select DISPLAY_FSP_VERSION_INFO_2
+	select DISPLAY_FSP_VERSION_INFO_2 if !FSP_USE_REPO
 	select DRIVERS_USB_ACPI
 	select EDK2_CPU_TIMER_LIB if PAYLOAD_EDK2
 	select FSP_COMPRESS_FSP_S_LZ4

From 51d7881dd5e6e695dd1a1c0bf10cc2c69658ea62 Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Tue, 11 Mar 2025 20:25:52 +0000
Subject: [PATCH 0379/3886] mb/starlabs/starbook/mtl: Select FSP Type IOT

Select FSP Type IOT so that the FSP blobs from the Intel repo are
used, as the client ones are not available.

Change-Id: I95ab68d1b5bb73738b5b6f9461d2b7771e75f17a
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86831
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
---
 src/mainboard/starlabs/starbook/Kconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/src/mainboard/starlabs/starbook/Kconfig b/src/mainboard/starlabs/starbook/Kconfig
index 169b983bf8..e8154fec50 100644
--- a/src/mainboard/starlabs/starbook/Kconfig
+++ b/src/mainboard/starlabs/starbook/Kconfig
@@ -111,6 +111,7 @@ config BOARD_STARLABS_STARBOOK_MTL
 	select EC_STARLABS_MAX_CHARGE
 	select EC_STARLABS_MERLIN
 	select EC_STARLABS_NEED_ITE_BIN
+	select FSP_TYPE_IOT
 	select MAINBOARD_HAS_TPM2
 	select MEMORY_MAPPED_TPM
 	select SOC_INTEL_COMMON_BLOCK_VTD

From b9759ba5500562c218fa4160821b3eea87c2b441 Mon Sep 17 00:00:00 2001
From: David Wu <david_wu@quanta.corp-partner.google.com>
Date: Mon, 10 Mar 2025 10:03:11 +0800
Subject: [PATCH 0380/3886] mb/google/nissa/var/riven: Modify eMMC DLL tuning
 value

Riven cannot boot into OS from 2nd source eMMC, show message
"Something went wrong booting from internal disk" and stop in depthcharge.
According to Intel provides eMMC DLL delay patch that tuning on each
riven different eMMC system to modify eMMC DLL tuning value to improve initialization reliability.

BUG=b:401663746
TEST=Cold reboot stress test over 2500 cycles

Change-Id: Ib36650f2a8fca486c8c89fb9f2ef42452b7a4cfa
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86778
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Simon Yang <simon1.yang@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/google/brya/variants/riven/overridetree.cb | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/mainboard/google/brya/variants/riven/overridetree.cb b/src/mainboard/google/brya/variants/riven/overridetree.cb
index 9e5fa3cd2e..1cb63134db 100644
--- a/src/mainboard/google/brya/variants/riven/overridetree.cb
+++ b/src/mainboard/google/brya/variants/riven/overridetree.cb
@@ -62,7 +62,7 @@ chip soc/intel/alderlake
 	# [22:16] steps of delay for DDR50, each 125ps, range: 0 - 78.
 	# [14:8] steps of delay for SDR25/HS50, each 125ps, range: 0 - 119.
 	# [6:0] steps of delay for SDR12, each 125ps, range: 0 - 119.
-	register "common_soc_config.emmc_dll.emmc_rx_cmd_data_cntl1" = "0x1C1B4F3C"
+	register "common_soc_config.emmc_dll.emmc_rx_cmd_data_cntl1" = "0x1C1B4F1B"
 
 	# EMMC RX CMD/DATA Delay 2
 	# Refer to EDS-Vol2-42.3.12.

From e63e54e0e956c549c2a3e422b1f406c56210ff8e Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Micha=C5=82=20Kope=C4=87?= <michal.kopec@3mdeb.com>
Date: Mon, 3 Mar 2025 16:11:00 +0100
Subject: [PATCH 0381/3886] mb/novacustom/mtl-h/devicetree.cb: Disable detect
 flag on PCIe CLKREQs
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Probing the clock request signal is not required on this board and with
the SSD models the board is sold with.

Change-Id: I51b0d0f2b390912cf8fff45d736e317de31863ed
Signed-off-by: Michał Kopeć <michal.kopec@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86694
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
---
 src/mainboard/novacustom/mtl-h/devicetree.cb | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/mainboard/novacustom/mtl-h/devicetree.cb b/src/mainboard/novacustom/mtl-h/devicetree.cb
index 22bf4068aa..ef29ec18ce 100644
--- a/src/mainboard/novacustom/mtl-h/devicetree.cb
+++ b/src/mainboard/novacustom/mtl-h/devicetree.cb
@@ -78,7 +78,7 @@ chip soc/intel/meteorlake
 			register "pcie_rp[PCH_RP(10)]" = "{
 				.clk_src = 8,
 				.clk_req = 8,
-				.flags = PCIE_RP_LTR | PCIE_RP_AER | PCIE_RP_CLK_REQ_DETECT,
+				.flags = PCIE_RP_LTR | PCIE_RP_AER,
 			}"
 			chip soc/intel/common/block/pcie/rtd3
 				register "is_storage" = "true"
@@ -93,7 +93,7 @@ chip soc/intel/meteorlake
 			register "pcie_rp[PCH_RP(11)]" = "{
 				.clk_src = 7,
 				.clk_req = 7,
-				.flags = PCIE_RP_LTR | PCIE_RP_AER | PCIE_RP_CLK_REQ_DETECT,
+				.flags = PCIE_RP_LTR | PCIE_RP_AER,
 			}"
 			chip soc/intel/common/block/pcie/rtd3
 				register "is_storage" = "true"

From 1f430614fd74b1053acecb551b22bc29f0f45b96 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Micha=C5=82=20Kope=C4=87?= <michal.kopec@3mdeb.com>
Date: Tue, 4 Mar 2025 12:34:40 +0100
Subject: [PATCH 0382/3886] mb/novacustom/mtl-h/devicetree.cb: Move USB cfg to
 xhci device nodes
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Move all USB configuration from the parent SOC node to the appropriate
XHCI controller device nodes in the devicetree.

Change-Id: Ib702b132698bcb71b4e7b6fa51c6a428bfe77252
Signed-off-by: Michał Kopeć <michal.kopec@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86708
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
---
 src/mainboard/novacustom/mtl-h/devicetree.cb | 37 ++++++++++----------
 1 file changed, 18 insertions(+), 19 deletions(-)

diff --git a/src/mainboard/novacustom/mtl-h/devicetree.cb b/src/mainboard/novacustom/mtl-h/devicetree.cb
index ef29ec18ce..22eceacb1a 100644
--- a/src/mainboard/novacustom/mtl-h/devicetree.cb
+++ b/src/mainboard/novacustom/mtl-h/devicetree.cb
@@ -24,25 +24,6 @@ chip soc/intel/meteorlake
 	# Thermal
 	register "tcc_offset" = "10" # TCC of 100C
 
-	register "usb2_ports" = "{
-		[0] = USB2_PORT_LONG(OC_SKIP),	 /* USB Type-A Port 1 (Left) */
-		[1] = USB2_PORT_TYPE_C(OC_SKIP), /* USB Type-C Port 1 (Non-TBT) */
-		[2] = USB2_PORT_MID(OC_SKIP),	 /* USB Type-A Port 2 (Right) */
-		[5] = USB2_PORT_TYPE_C(OC_SKIP), /* USB Type-C Port 2 (TBT) */
-		[6] = USB2_PORT_LONG(OC_SKIP),	 /* Integrated Camera */
-		[9] = USB2_PORT_MID(OC_SKIP),	 /* Bluetooth on M.2 2230 */
-	}"
-
-	register "usb3_ports" = "{
-		[0] = USB3_PORT_DEFAULT(OC_SKIP), /* USB Type-A Port 1 (Left) */
-		[1] = USB3_PORT_DEFAULT(OC_SKIP), /* USB Type-A Port 2 (Right) */
-	}"
-
-	register "tcss_ports" = "{
-		[0] = TCSS_PORT_DEFAULT(OC_SKIP), /* USB Type-C Port 1 (TBT) */
-		[1] = TCSS_PORT_DEFAULT(OC_SKIP), /* USB Type-C Port 2 (Non-TBT) */
-	}"
-
 	device cpu_cluster 0 on end
 	device domain 0 on
 		subsystemid 0x1558 0xa743 inherit
@@ -109,6 +90,11 @@ chip soc/intel/meteorlake
 		device ref crashlog on end
 		device ref vpu on end
 		device ref tcss_xhci on
+			register "tcss_ports" = "{
+				[0] = TCSS_PORT_DEFAULT(OC_SKIP), /* USB Type-C Port 1 (TBT) */
+				[1] = TCSS_PORT_DEFAULT(OC_SKIP), /* USB Type-C Port 2 (Non-TBT) */
+			}"
+
 			chip drivers/usb/acpi
 				device ref tcss_root_hub on
 					chip drivers/usb/acpi
@@ -137,6 +123,19 @@ chip soc/intel/meteorlake
 		end
 		device ref ioe_shared_sram on end
 		device ref xhci on
+			register "usb2_ports" = "{
+				[0] = USB2_PORT_LONG(OC_SKIP),   /* USB Type-A Port 1 (Left) */
+				[1] = USB2_PORT_TYPE_C(OC_SKIP),    /* USB Type-C Port 1 (Non-TBT) */
+				[2] = USB2_PORT_MID(OC_SKIP),    /* USB Type-A Port 2 (Right) */
+				[5] = USB2_PORT_TYPE_C(OC_SKIP), /* USB Type-C Port 2 (TBT) */
+				[6] = USB2_PORT_LONG(OC_SKIP),   /* Integrated Camera */
+				[9] = USB2_PORT_MID(OC_SKIP),    /* Bluetooth on M.2 2230 */
+			}"
+
+			register "usb3_ports" = "{
+				[0] = USB3_PORT_DEFAULT(OC_SKIP), /* USB Type-A Port 1 (Left) */
+				[1] = USB3_PORT_DEFAULT(OC_SKIP), /* USB Type-A Port 2 (Right) */
+			}"
 			chip drivers/usb/acpi
 				device ref xhci_root_hub on
 					chip drivers/usb/acpi

From cc29db483fde05d4d90b80fd3877a338748c5980 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Micha=C5=82=20Kope=C4=87?= <michal.kopec@3mdeb.com>
Date: Mon, 3 Mar 2025 16:18:39 +0100
Subject: [PATCH 0383/3886] mb/novacustom/mtl-h/devicetree.cb: Set SOC aux
 override
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Set TCSS SOC Aux orientation override as per the mainboard schematic.

Change-Id: I45903f26a3f724e6bd82645b0fe3d1e919a84833
Signed-off-by: Michał Kopeć <michal.kopec@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86697
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/novacustom/mtl-h/devicetree.cb | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/src/mainboard/novacustom/mtl-h/devicetree.cb b/src/mainboard/novacustom/mtl-h/devicetree.cb
index 22eceacb1a..046b7a7599 100644
--- a/src/mainboard/novacustom/mtl-h/devicetree.cb
+++ b/src/mainboard/novacustom/mtl-h/devicetree.cb
@@ -90,6 +90,15 @@ chip soc/intel/meteorlake
 		device ref crashlog on end
 		device ref vpu on end
 		device ref tcss_xhci on
+			# SOC Aux orientation override:
+			# This is a bitfield that corresponds to up to 4 TCSS ports.
+			# Bits (0,1) allocated for TCSS Port1 configuration and Bits (2,3)for TCSS Port2.
+			# Bits (4,5) allocated for TCSS Port3 configuration and Bits (6,7)for TCSS Port4.
+			# Bit0,Bit2,Bit4,Bit6 set to "1" indicates no retimer on USBC Ports
+			# Bit1,Bit3,Bit5,Bit7 set to "0" indicates Aux lines are not swapped on the
+			# motherboard to USBC connector
+			register "tcss_aux_ori" = "0x54"
+
 			register "tcss_ports" = "{
 				[0] = TCSS_PORT_DEFAULT(OC_SKIP), /* USB Type-C Port 1 (TBT) */
 				[1] = TCSS_PORT_DEFAULT(OC_SKIP), /* USB Type-C Port 2 (Non-TBT) */

From 466696bfb0b76427149c1bf2997351e76398c542 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Micha=C5=82=20Kope=C4=87?= <michal.kopec@3mdeb.com>
Date: Tue, 4 Mar 2025 12:14:53 +0100
Subject: [PATCH 0384/3886] mb/novacustom/mtl-h: Add iGPU variant
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Split V5x0TU into a separate variant of the mtl-h baseboard. This is in
preparation to add support for the V5x0TNx variants, which is a
different variant of the board, with a discrete NVIDIA GPU.

Change-Id: I4f8215ace6b7a394f8d196be3f81c33b2cb4e9ec
Signed-off-by: Michał Kopeć <michal.kopec@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86709
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/novacustom/mtl-h/Kconfig        |   6 ++
 src/mainboard/novacustom/mtl-h/Makefile.mk    |   5 +-
 src/mainboard/novacustom/mtl-h/devicetree.cb  |  51 ---------------
 .../mtl-h/{ => variants/igpu}/data.vbt        | Bin
 .../mtl-h/{ => variants/igpu}/gpio.c          |   0
 .../mtl-h/{ => variants/igpu}/hda_verb.c      |   0
 .../mtl-h/variants/igpu/overridetree.cb       |  58 ++++++++++++++++++
 7 files changed, 67 insertions(+), 53 deletions(-)
 rename src/mainboard/novacustom/mtl-h/{ => variants/igpu}/data.vbt (100%)
 rename src/mainboard/novacustom/mtl-h/{ => variants/igpu}/gpio.c (100%)
 rename src/mainboard/novacustom/mtl-h/{ => variants/igpu}/hda_verb.c (100%)
 create mode 100644 src/mainboard/novacustom/mtl-h/variants/igpu/overridetree.cb

diff --git a/src/mainboard/novacustom/mtl-h/Kconfig b/src/mainboard/novacustom/mtl-h/Kconfig
index 5d608b40ac..813a558085 100644
--- a/src/mainboard/novacustom/mtl-h/Kconfig
+++ b/src/mainboard/novacustom/mtl-h/Kconfig
@@ -41,6 +41,12 @@ if BOARD_NOVACUSTOM_MTLH_COMMON
 config MAINBOARD_DIR
 	default "novacustom/mtl-h"
 
+config VARIANT_DIR
+	default "igpu" if BOARD_NOVACUSTOM_V5X0TU_BASE
+
+config OVERRIDE_DEVICETREE
+	default "variants/\$(CONFIG_VARIANT_DIR)/overridetree.cb"
+
 config MAINBOARD_PART_NUMBER
 	default "V54x_6x_TU" if BOARD_NOVACUSTOM_V5X0TU_BASE
 
diff --git a/src/mainboard/novacustom/mtl-h/Makefile.mk b/src/mainboard/novacustom/mtl-h/Makefile.mk
index 9a35f5a80b..e4841b26c3 100644
--- a/src/mainboard/novacustom/mtl-h/Makefile.mk
+++ b/src/mainboard/novacustom/mtl-h/Makefile.mk
@@ -6,9 +6,10 @@ bootblock-y += bootblock.c
 bootblock-y += gpio_early.c
 
 romstage-y += romstage.c
+romstage-y += variants/$(VARIANT_DIR)/gpio.c
 
 ramstage-y += ramstage.c
-ramstage-y += hda_verb.c
-ramstage-y += gpio.c
+ramstage-y += variants/${VARIANT_DIR}/hda_verb.c
+ramstage-y += variants/$(VARIANT_DIR)/gpio.c
 
 ramstage-$(CONFIG_HAVE_ACPI_TABLES) += fadt.c
diff --git a/src/mainboard/novacustom/mtl-h/devicetree.cb b/src/mainboard/novacustom/mtl-h/devicetree.cb
index 046b7a7599..76548bb292 100644
--- a/src/mainboard/novacustom/mtl-h/devicetree.cb
+++ b/src/mainboard/novacustom/mtl-h/devicetree.cb
@@ -26,33 +26,9 @@ chip soc/intel/meteorlake
 
 	device cpu_cluster 0 on end
 	device domain 0 on
-		subsystemid 0x1558 0xa743 inherit
 		device ref system_agent on end
 		device ref igpu on
 			register "ddi_port_A_config" = "1"
-			register "ddi_ports_config" = "{
-				[DDI_PORT_A] = DDI_ENABLE_HPD, 			/* eDP */
-				[DDI_PORT_2] = DDI_ENABLE_DDC | DDI_ENABLE_HPD,	/* HDMI 2.1 */
-			}"
-			chip drivers/gfx/generic
-				register "device_count" = "6"
-				# DDIA for eDP
-				register "device[0].name" = ""LCD0""
-				register "device[0].type" = "panel"
-				# DDIB unused
-				register "device[1].name" = ""DD01""
-				# TCP0 for Thunderbolt 4
-				register "device[2].name" = ""DD02""
-				register "device[2].use_pld" = "true"
-				register "device[2].pld" = "ACPI_PLD_TYPE_C(RIGHT, CENTER, ACPI_PLD_GROUP(1, 1))"
-				# TCP1 unused
-				register "device[3].name" = ""DD03""
-				# TCP2 for HDMI 2.1
-				register "device[4].name" = ""DD04""
-				# TCP3 unused
-				register "device[5].name" = ""DD05""
-				device generic 0 on end
-			end
 		end
 		device ref dtt on end
 		device ref pcie_rp10 on # M.2 2280 #2
@@ -214,39 +190,12 @@ chip soc/intel/meteorlake
 				device generic 0 on end
 			end
 		end
-		device ref i2c0 on # Touchpad
-			register "serial_io_i2c_mode[PchSerialIoIndexI2C0]" = "PchSerialIoPci"
-			chip drivers/i2c/hid
-				register "generic.hid" = ""ELAN0412""
-				register "generic.desc" = ""ELAN Touchpad""
-				register "generic.irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPP_B00)"
-				register "generic.detect" = "1"
-				register "hid_desc_reg_offset" = "0x01"
-				device i2c 15 on end
-			end
-			chip drivers/i2c/hid
-				register "generic.hid" = ""FTCS1000""
-				register "generic.desc" = ""FocalTech Touchpad""
-				register "generic.irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPP_B00)"
-				register "generic.detect" = "1"
-				register "hid_desc_reg_offset" = "0x01"
-				device i2c 38 on end
-			end
-		end
 		device ref i2c1 on # USB-PD EEPROM
 			register "serial_io_i2c_mode[PchSerialIoIndexI2C1]" = "PchSerialIoPci"
 		end
 		device ref i2c3 on # Pantone ROM
 			register "serial_io_i2c_mode[PchSerialIoIndexI2C3]" = "PchSerialIoPci"
 		end
-		device ref pcie_rp5 on # GLAN
-			register "pcie_rp[PCH_RP(5)]" = "{
-				.clk_src = 2,
-				.clk_req = 2,
-				.flags = PCIE_RP_LTR | PCIE_RP_CLK_SRC_UNUSED,
-			}"
-			register "pcie_clk_config_flag[2]" = "PCIE_CLK_LAN"
-		end
 		device ref pcie_rp6 on # SD Card Reader
 			register "pcie_rp[PCH_RP(6)]" = "{
 				.clk_src = 3,
diff --git a/src/mainboard/novacustom/mtl-h/data.vbt b/src/mainboard/novacustom/mtl-h/variants/igpu/data.vbt
similarity index 100%
rename from src/mainboard/novacustom/mtl-h/data.vbt
rename to src/mainboard/novacustom/mtl-h/variants/igpu/data.vbt
diff --git a/src/mainboard/novacustom/mtl-h/gpio.c b/src/mainboard/novacustom/mtl-h/variants/igpu/gpio.c
similarity index 100%
rename from src/mainboard/novacustom/mtl-h/gpio.c
rename to src/mainboard/novacustom/mtl-h/variants/igpu/gpio.c
diff --git a/src/mainboard/novacustom/mtl-h/hda_verb.c b/src/mainboard/novacustom/mtl-h/variants/igpu/hda_verb.c
similarity index 100%
rename from src/mainboard/novacustom/mtl-h/hda_verb.c
rename to src/mainboard/novacustom/mtl-h/variants/igpu/hda_verb.c
diff --git a/src/mainboard/novacustom/mtl-h/variants/igpu/overridetree.cb b/src/mainboard/novacustom/mtl-h/variants/igpu/overridetree.cb
new file mode 100644
index 0000000000..b38660a053
--- /dev/null
+++ b/src/mainboard/novacustom/mtl-h/variants/igpu/overridetree.cb
@@ -0,0 +1,58 @@
+chip soc/intel/meteorlake
+	device domain 0 on
+		subsystemid 0x1558 0xa743 inherit
+		device ref igpu on
+			register "ddi_ports_config" = "{
+				[DDI_PORT_A] = DDI_ENABLE_HPD, 			/* eDP */
+				[DDI_PORT_2] = DDI_ENABLE_DDC | DDI_ENABLE_HPD,	/* HDMI 2.1 */
+			}"
+			chip drivers/gfx/generic
+				register "device_count" = "6"
+				# DDIA for eDP
+				register "device[0].name" = ""LCD0""
+				register "device[0].type" = "panel"
+				# DDIB unused
+				register "device[1].name" = ""DD01""
+				# TCP0 for Thunderbolt 4
+				register "device[2].name" = ""DD02""
+				register "device[2].use_pld" = "true"
+				register "device[2].pld" = "ACPI_PLD_TYPE_C(RIGHT, CENTER, ACPI_PLD_GROUP(1, 1))"
+				# TCP1 unused
+				register "device[3].name" = ""DD03""
+				# TCP2 for HDMI 2.1
+				register "device[4].name" = ""DD04""
+				# TCP3 unused
+				register "device[5].name" = ""DD05""
+				device generic 0 on end
+			end
+		end
+		device ref i2c0 on # Touchpad
+			register "serial_io_i2c_mode[PchSerialIoIndexI2C0]" = "PchSerialIoPci"
+			chip drivers/i2c/hid
+				register "generic.hid" = ""ELAN0412""
+				register "generic.desc" = ""ELAN Touchpad""
+				register "generic.irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPP_B00)"
+				register "generic.detect" = "1"
+				register "hid_desc_reg_offset" = "0x01"
+				device i2c 15 on end
+			end
+			chip drivers/i2c/hid
+				register "generic.hid" = ""FTCS1000""
+				register "generic.desc" = ""FocalTech Touchpad""
+				register "generic.irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPP_B00)"
+				register "generic.detect" = "1"
+				register "hid_desc_reg_offset" = "0x01"
+				device i2c 38 on end
+			end
+		end
+		device ref pcie_rp5 on # GLAN
+			register "pcie_rp[PCH_RP(5)]" = "{
+				.clk_src = 2,
+				.clk_req = 2,
+				.flags = PCIE_RP_LTR | PCIE_RP_CLK_SRC_UNUSED,
+			}"
+			register "pcie_clk_config_flag[2]" = "PCIE_CLK_LAN"
+		end
+		device ref gbe on end
+	end
+end

From b2ffe5ee6888340a9b34fb132a33ab63f541a379 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Micha=C5=82=20Kope=C4=87?= <michal.kopec@3mdeb.com>
Date: Tue, 4 Mar 2025 16:23:28 +0100
Subject: [PATCH 0385/3886] mb/novacustom/mtl-h/var/igpu/data.vbt: Disable
 secondary display feature
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Currently, to make sure that the UEFI setup menu stays legible on HiDPI
displays, the VBT has the Fixed Display feature enabled with the
resolution set to 1920x1200.

If the secondary display feature is also enabled, and a monitor with
resolution lower than 1920x1200 is connected, the result is that neither
the internal nor external display is initialized.

Disable the secondary display feature to ensure that the internal
display keeps working regardless of any connected external displays.

Change-Id: I47630f5ce9573ed0ae86621252a04d41a92d40cc
Signed-off-by: Michał Kopeć <michal.kopec@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86713
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 .../novacustom/mtl-h/variants/igpu/data.vbt   | Bin 7680 -> 7680 bytes
 1 file changed, 0 insertions(+), 0 deletions(-)

diff --git a/src/mainboard/novacustom/mtl-h/variants/igpu/data.vbt b/src/mainboard/novacustom/mtl-h/variants/igpu/data.vbt
index 59c3c783a59dbc11cd961b3de3b40557542db287..4151d024a9a9fade7a8dfce32ff3c6c7ea26ce93 100644
GIT binary patch
delta 448
zcmZ9HF-yZh6vyAY<kC>vCT&!z))I9vIu!*SOrZ`g#YM!S;*f5R_7fOEa0*x-PJRM6
zA&Zl`D1u876dfJ?0xn|WT{r~$AMWlwe*gb_7y6-pTIE}{6KGHmoqogSfaBoyH@=XO
zkIhjALMRUac8*L3@F>E0o`hgj=^E#D6CIudux;o~*%?;>;No!yA-c*c`$-F4GcHnG
z5kSkhKyk7XoC^>8GVhW`SbZt6Re7&$<>7c`V~YEr4y!LG*<_LOqik8W-0I-}wCs0+
zo2bzdo5qB?hDVOJ;Jj#$%JX;8w${XNinJ~bG;XFs`6tNJx_(TDdIvFn*V{<9+!QH`
zv}3g6*4QND-YlePd}F?G3QC+VN_&`|S*v7O1zNK<XJk+cf|05WN%rMZ@xWTa9ELf7
KD?KijKMTKAo?(dq

delta 398
zcmY*Uu}T9$5S`h*J@1Z~Tkb*>k~@PIQL7XZn?ytqK@cr06pI)U^)C_-Bp^cKlokO?
z3oWh^3sXtZ&cfK*r8kI$vTi~U@&?|_8|Do&)k3vUpA>89XUGw9zmb#T7m|={tbQR-
z0gEJg%wp%r41g?MVAiMt0Nvw^ZNSqBND0RjXQ913RHu|@VJ-u&`>-RSnUavu1`j~!
z)PgEzP#3`a1afG4pfeUaY|xU>Nl}Ld&R|aO{~Smg`dUku-dIRSW|jgzH}S&Teb)%~
zghRW$$m~OE@gm*vDI1s$rPL##@nL~#CT_q?(~{WM5025e*q}>sW%cmKs`)ja%H}+k
z%ypy7yF4nJNhW5eLGh?<y$e=Hx{jA{i{kDg1+IlIt+<;(Md<+0tW?Dtg&*Cz2N?T5
Ub0N<o>2;B$*NeV=%h6{zfACaVwg3PC


From d0a28d4c97bedb7affdd5262084a3cb623a8b271 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Micha=C5=82=20Kope=C4=87?= <michal.kopec@3mdeb.com>
Date: Thu, 6 Mar 2025 12:56:56 +0100
Subject: [PATCH 0386/3886] mb/novacustom/mtl-h/var/igpu: Fix HDMI DDI lane
 index
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

The DDI lane number in `enum ddi_ports` is 1-based, while the TCPx
display link numbers from the SoC are 0 based. Fix the off-by-one error
and set the HDMI DDI lane index to the correct value of 3.

Change-Id: I861e58150ebe8b97cf3e9be81c2bd5494eff600b
Signed-off-by: Michał Kopeć <michal.kopec@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86751
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/novacustom/mtl-h/variants/igpu/overridetree.cb | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/mainboard/novacustom/mtl-h/variants/igpu/overridetree.cb b/src/mainboard/novacustom/mtl-h/variants/igpu/overridetree.cb
index b38660a053..f6a32c05cc 100644
--- a/src/mainboard/novacustom/mtl-h/variants/igpu/overridetree.cb
+++ b/src/mainboard/novacustom/mtl-h/variants/igpu/overridetree.cb
@@ -4,7 +4,7 @@ chip soc/intel/meteorlake
 		device ref igpu on
 			register "ddi_ports_config" = "{
 				[DDI_PORT_A] = DDI_ENABLE_HPD, 			/* eDP */
-				[DDI_PORT_2] = DDI_ENABLE_DDC | DDI_ENABLE_HPD,	/* HDMI 2.1 */
+				[DDI_PORT_3] = DDI_ENABLE_DDC | DDI_ENABLE_HPD,	/* HDMI 2.1 */
 			}"
 			chip drivers/gfx/generic
 				register "device_count" = "6"

From 3dae427ac51a97f76874335d56a1a751f8f29177 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Micha=C5=82=20Kope=C4=87?= <michal.kopec@3mdeb.com>
Date: Thu, 6 Mar 2025 13:04:32 +0100
Subject: [PATCH 0387/3886] mb/novacustom/mtl-h/var/igpu: Add power limits
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Set PL4 to the wattage of the included AC adapter. The EC will override
this limit at runtime, if necessary (for example, if a weaker USB-PD
power supply is connected).

PsysPmax is set according to the board schematics (RPsys resistor),
which ensures that the Psys signal generated by the battery charger and
interpreted by SOC VRs is interpreted correctly and that Psys power
limits applied by the EC work as expected.

Change-Id: I56e9c20556553940c308150f7e470628f56c3991
Signed-off-by: Michał Kopeć <michal.kopec@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86752
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
---
 .../novacustom/mtl-h/variants/igpu/overridetree.cb   | 12 ++++++++++++
 1 file changed, 12 insertions(+)

diff --git a/src/mainboard/novacustom/mtl-h/variants/igpu/overridetree.cb b/src/mainboard/novacustom/mtl-h/variants/igpu/overridetree.cb
index f6a32c05cc..1f78915e0c 100644
--- a/src/mainboard/novacustom/mtl-h/variants/igpu/overridetree.cb
+++ b/src/mainboard/novacustom/mtl-h/variants/igpu/overridetree.cb
@@ -1,4 +1,16 @@
 chip soc/intel/meteorlake
+	# Power limits,
+	# PsysPL2, PsysPL3, PL4 are configured by EC at runtime
+	register "power_limits_config[MTL_P_682_482_CORE]" = "{
+		.tdp_pl1_override = 35,
+		.tdp_pl2_override = 64,
+		.tdp_pl4 = 90,
+		.psys_pmax = 99,
+	}"
+
+	# MTL SOC has additional setting for PsysPmax
+	register "psys_pmax_watts" = "99"
+
 	device domain 0 on
 		subsystemid 0x1558 0xa743 inherit
 		device ref igpu on

From 042e3ebd3494974f7d32ba52a9111c3f8cac2f70 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Micha=C5=82=20Kope=C4=87?= <michal.kopec@3mdeb.com>
Date: Mon, 10 Mar 2025 14:54:28 +0100
Subject: [PATCH 0388/3886] mb/novacustom/mtl-h/variants/igpu/hda_verb.c: Add
 all HDA verbs from stock FW
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Add remaining HDA verbs from stock Clevo firmware 1.07.02.

Change-Id: Ibd6db007f40670825f652066fc2fba6978f6a73b
Signed-off-by: Michał Kopeć <michal.kopec@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86789
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 .../novacustom/mtl-h/variants/igpu/hda_verb.c | 30 ++++++++++++++++++-
 1 file changed, 29 insertions(+), 1 deletion(-)

diff --git a/src/mainboard/novacustom/mtl-h/variants/igpu/hda_verb.c b/src/mainboard/novacustom/mtl-h/variants/igpu/hda_verb.c
index cd7493e6d3..b94a194737 100644
--- a/src/mainboard/novacustom/mtl-h/variants/igpu/hda_verb.c
+++ b/src/mainboard/novacustom/mtl-h/variants/igpu/hda_verb.c
@@ -6,7 +6,7 @@ const u32 cim_verb_data[] = {
 	/* Realtek, ALC245 */
 	0x10ec0245, /* Vendor ID */
 	0x1558a763, /* Subsystem ID */
-	13, /* Number of entries */
+	40, /* Number of entries */
 	AZALIA_SUBVENDOR(0, 0x1558a763),
 	AZALIA_RESET(1),
 	AZALIA_PIN_CFG(0, 0x12, 0x90a60130),
@@ -21,6 +21,34 @@ const u32 cim_verb_data[] = {
 	AZALIA_PIN_CFG(0, 0x1e, 0x411111f0),
 	AZALIA_PIN_CFG(0, 0x21, 0x04211020),
 
+	0x5B50006,	0x5B40011,	0x205001A,	0x204810B,
+	0x205004A,	0x2042010,	0x2050038,	0x2047909,
+	0x5C50000,	0x5C43D82,	0x5C50000,	0x5C43D82,
+	0x5350000,	0x534201A,	0x5350000,	0x534201A,
+	0x535001D,	0x5340800,	0x535001E,	0x5340800,
+	0x5350003,	0x5341EC4,	0x5350004,	0x5340000,
+	0x5450000,	0x5442000,	0x545001D,	0x5440800,
+	0x545001E,	0x5440800,	0x5450003,	0x5441EC4,
+	0x5450004,	0x5440000,	0x5350000,	0x534A01A,
+	0x205003C,	0x204F175,	0x205003C,	0x204F135,
+	0x2050040,	0x2048800,	0x5A50001,	0x5A4001F,
+	0x2050010,	0x2040020,	0x2050010,	0x2040020,
+	0x205006B,	0x204A390,	0x205006B,	0x204A390,
+	0x205006C,	0x2040C9E,	0x205006D,	0x2040C00,
+	0x170500,	0x170500,	0x5A50004,	0x5A40113,
+	0x2050008,	0x2046A8C,	0x2050076,	0x204F000,
+	0x205000E,	0x20465C0,	0x2050033,	0x2048580,
+	0x2050069,	0x204FDA8,	0x2050068,	0x2040000,
+	0x2050003,	0x2040002,	0x2050069,	0x2040000,
+	0x2050068,	0x2040001,	0x205002E,	0x204290E,
+	0x2236100,	0x2235100,	0x920011,	0x970610,
+	0x936000,	0x935000,	0x205000D,	0x204A020,
+	0x220011,	0x270610,	0x23A046,	0x239046,
+	0x173B000,	0x1770740,	0x5A50001,	0x5A4001F,
+	0x5C5000F,	0x5C40003,	0x2050036,	0x20437D7,
+	0x143B000,	0x1470740,	0x2050010,	0x2040020,
+	0x1470C02,	0x1470C02,	0x1470C02,	0x1470C02,
+
 	/* Intel Meteor Lake HDMI */
 	0x8086281d, /* Vendor ID */
 	0x80860101, /* Subsystem ID */

From d9d06f7d79fcd5b5b0638cfb18a67aab4c77fab6 Mon Sep 17 00:00:00 2001
From: Subrata Banik <subratabanik@google.com>
Date: Sun, 9 Mar 2025 15:42:27 +0530
Subject: [PATCH 0389/3886] soc/qualcomm/cmn/qclib: Replace magic number with
 BIT() macro

Replace the magic number 0x00000001 with the BIT(0) macro for
QCLIB_GA_ENABLE_UART_LOGGING. This improves readability and
maintainability by clearly indicating that a specific bit is being set.

TEST=Able to build google/herobrine.

Change-Id: Ie425a68c6721343ca53eb883d6278decca92bcad
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86774
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
---
 src/soc/qualcomm/common/include/soc/qclib_common.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/soc/qualcomm/common/include/soc/qclib_common.h b/src/soc/qualcomm/common/include/soc/qclib_common.h
index 792b743f40..850202a490 100644
--- a/src/soc/qualcomm/common/include/soc/qclib_common.h
+++ b/src/soc/qualcomm/common/include/soc/qclib_common.h
@@ -43,7 +43,7 @@ struct qclib_cb_if_table_entry {
 };
 
 /* GA_BMASK_VALUES (global_attributes bit mask values) */
-#define QCLIB_GA_ENABLE_UART_LOGGING   0x00000001
+#define QCLIB_GA_ENABLE_UART_LOGGING   BIT(0)
 #define QCLIB_GA_FORCE_COLD_REBOOT BIT(3)
 #define QCLIB_GA_DDR_FMAX_LIMIT_HYNIX8GB BIT(5)
 

From e6a89935e96d5277a6ca315b2089e4616e885a6c Mon Sep 17 00:00:00 2001
From: Subrata Banik <subratabanik@google.com>
Date: Tue, 11 Mar 2025 03:58:50 +0000
Subject: [PATCH 0390/3886] ec/google/chromeec: Override Lid State for Factory
 Netboot

This patch modifies the get_lid_switch() function to allow faking the
lid switch state when the GBB_FLAG_DISABLE_LID_SHUTDOWN Kconfig option
is enabled.

When GBB_FLAG_DISABLE_LID_SHUTDOWN is enabled, the function will
always return 1 (lid open), bypassing the actual lid switch state
retrieval from the Embedded Controller (EC).

This functionality is specifically designed to facilitate factory
processes, such as netboot image downloads, where devices need to
remain operational regardless of the lid's closed state. This prevents
intended shutdowns triggered by a closed lid during manufacturing and
testing.

By setting GBB_FLAG_DISABLE_LID_SHUTDOWN, we override the actual
lid status with a simulated LID status is open, which is a
prerequisite for display initialization.

w/o this patch:

```
[ALERT]  Graphics hand-off block not found
...
[INFO ]              NAME |       PORT | POLARITY |     VALUE
[INFO ]               lid |  undefined |     high |       low
```

w/ this patch:

```
[INFO ]              NAME |       PORT | POLARITY |     VALUE
[INFO ]               lid |  undefined |     high |      high
...
[INFO ]  framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
[INFO ]    x_res x y_res: 1920 x 1200, size: 9216000 at 0xd0000000
```

BUG=b:333982806
TEST=Verified lid switch behavior with and without
`GBB_FLAG_DISABLE_LID_SHUTDOWN` enabled.

Change-Id: I89d506ab50b421b93be13b0e5e36a7ef1247e2b9
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86807
Reviewed-by: Jayvik Desai <jayvik@google.com>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Reviewed-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/ec/google/chromeec/switches.c | 20 ++++++++++++++++++++
 1 file changed, 20 insertions(+)

diff --git a/src/ec/google/chromeec/switches.c b/src/ec/google/chromeec/switches.c
index 15f4208c32..e35e7722ea 100644
--- a/src/ec/google/chromeec/switches.c
+++ b/src/ec/google/chromeec/switches.c
@@ -3,13 +3,33 @@
 #include <bootmode.h>
 #include <ec/google/chromeec/ec.h>
 #include <elog.h>
+#include <security/vboot/misc.h>
 
 #if CONFIG(EC_GOOGLE_CHROMEEC_LPC)
+/*
+ * Retrieves the state of the lid switch.
+ *
+ * The get_lid_switch() function checks if lid switch functionality is enabled
+ * in the coreboot configuration. If the VBOOT_LID_SWITCH Kconfig option is
+ * enabled, it retrieves the lid switch state from the Embedded Controller (EC).
+ *
+ * If the GBB_FLAG_DISABLE_LID_SHUTDOWN Kconfig option is enabled, this function
+ * will always return 1 (lid open), effectively faking the lid status. This is
+ * intended for stages post-romstage, particularly during display-related
+ * initialization, where lid-based shutdown should be suppressed.
+ *
+ * @return 1 if the lid is open, 0 if the lid is closed, or -1 if the lid switch
+ * functionality is not configured (VBOOT_LID_SWITCH is disabled).
+ */
 int get_lid_switch(void)
 {
 	if (!CONFIG(VBOOT_LID_SWITCH))
 		return -1;
 
+	/* If GBB_FLAG_DISABLE_LID_SHUTDOWN is enabled, fake the lid status as always open. */
+	if (!ENV_ROMSTAGE_OR_BEFORE && vboot_is_gbb_flag_set(VB2_GBB_FLAG_DISABLE_LID_SHUTDOWN))
+		return 1; /* Always return 1 (lid open) */
+
 	return !!(google_chromeec_get_switches() & EC_SWITCH_LID_OPEN);
 }
 #endif

From 4988f447d766a8cd54ead513f449bfe915a7305d Mon Sep 17 00:00:00 2001
From: Subrata Banik <subratabanik@google.com>
Date: Tue, 11 Mar 2025 23:23:43 +0530
Subject: [PATCH 0391/3886] soc/intel/pantherlake: Correct GPIO Community 3 PIN
 mapping

This commit rectifies a PIN mapping error in GPIO Community 3,
introduced by the removal of CPUJTAG PADs from the static ACPI entry.

CPUJTAG PADs are reserved for SoC debugging and should not be
configured by kernel drivers. To ensure accurate PIN mapping for
subsequent GPIO banks, this patch designates the CPUJTAG PAD range as
"RSVD" (Reserved) and exposes the corresponding GPIO PIN numbers. This
allows other GPIO banks within Community 3 to correctly adjust their
offsets.

Problem:

Prior to this fix, GPP_H0 was incorrectly assigned PIN 0 within GPIO
Community 3, deviating from the EDS.

Solution:

By marking the CPUJTAG range as RSVD, GPP_H0 is now correctly mapped
to PIN 15, aligning with the EDS definition.

Changes in details:

- Corrected the GPI3 to accurately calculate the GPIO PINs.
- Renamed CPUJTAG to RSVD (Reserved) and adjusted related definitions.
- Updated GPI3 device to reflect the RSVD group, including adding
  subproperties and correcting group counts.
- Modified gpio_defs.h and gpio_soc_defs.h to reflect the RSVD name
  change and pad count.

Change-Id: I9f32b54a8a0218cd993f01ccf5f0bb158877766a
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86825
Reviewed-by: Cliff Huang <cliff.huang@intel.com>
Reviewed-by: Pranava Y N <pranavayn@google.com>
Reviewed-by: Jayvik Desai <jayvik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/soc/intel/pantherlake/acpi/gpio.asl       | 43 +++++++++++++++----
 .../intel/pantherlake/include/soc/gpio_defs.h |  2 +-
 .../pantherlake/include/soc/gpio_soc_defs.h   |  2 +-
 3 files changed, 37 insertions(+), 10 deletions(-)

diff --git a/src/soc/intel/pantherlake/acpi/gpio.asl b/src/soc/intel/pantherlake/acpi/gpio.asl
index 653f00b72b..fe73b13b78 100644
--- a/src/soc/intel/pantherlake/acpi/gpio.asl
+++ b/src/soc/intel/pantherlake/acpi/gpio.asl
@@ -27,10 +27,10 @@ Method (GADD, 1, NotSerialized)
 		Local1 = Arg0 - COM1_GRP_PAD_START
 	}
 	/* GPIO Community 3 */
-	If (Arg0 >= GPP_H00 && Arg0 <= COM3_GRP_PAD_END)
+	If (Arg0 >= COM3_GRP_PAD_START && Arg0 <= COM3_GRP_PAD_END)
 	{
 		Local0 = PID_GPIOCOM3
-		Local1 = Arg0 - GPP_H00
+		Local1 = Arg0 - COM3_GRP_PAD_START
 	}
 	/* GPIO Community 4 */
 	If (Arg0 >= COM4_GRP_PAD_START && Arg0 <= COM4_GRP_PAD_END)
@@ -438,7 +438,7 @@ Device (GPI1)
 	}
 }
 
-/* GPIO Community 3: GPP_H, GPP_A, VGPIO3 */
+/* GPIO Community 3: CPUJTAG (reserved), GPP_H, GPP_A, VGPIO3 */
 Device (GPI3)
 {
 	Name (_HID, ACPI_GPIO_HID)
@@ -471,7 +471,7 @@ Device (GPI3)
 			Package (0x02)
 			{
 				"intc-gpio-group-count",
-				NUM_COM3_GROUPS - 1 /* Skip CPUJTAG */
+				NUM_COM3_GROUPS
 			},
 
 			Package (0x02)
@@ -508,6 +508,12 @@ Device (GPI3)
 		ToUUID ("dbb8e3e6-5886-4ba6-8795-1319f52a966b"),
 		Package (0x04)
 		{
+			Package (0x02)
+			{
+				"intc-gpio-group-0-subproperties",
+				RSVD
+			},
+
 			Package (0x02)
 			{
 				"intc-gpio-group-1-subproperties",
@@ -527,10 +533,31 @@ Device (GPI3)
 			}
 		}
 	})
-	/*
-	 * Don't expose first bank/group in community 3: CPUJTAG because
-	 * CPUJTAG doesn't required to be controlled by kernel pinctrl driver.
-	 */
+	/* first bank/group in community 3: RSVD */
+	Name (RSVD, Package (0x02)
+	{
+		ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+		Package (0x03)
+		{
+			Package (0x02)
+			{
+				"intc-gpio-group-name",
+				"RSVD"
+			},
+
+			Package (0x02)
+			{
+				"intc-gpio-pad-count",
+				NUM_GRP_RSVD_PADS
+			},
+
+			Package (0x02)
+			{
+				"intc-gpio-group-offset",
+				GPP_RSVD_START_OFFSET
+			}
+		}
+	})
 	/* 2nd bank/group in community 3: GPP_H */
 	Name (GPPH, Package (0x02)
 	{
diff --git a/src/soc/intel/pantherlake/include/soc/gpio_defs.h b/src/soc/intel/pantherlake/include/soc/gpio_defs.h
index e9fdc46a2c..2c6a8101d6 100644
--- a/src/soc/intel/pantherlake/include/soc/gpio_defs.h
+++ b/src/soc/intel/pantherlake/include/soc/gpio_defs.h
@@ -265,7 +265,7 @@
  * ref doc: Panther Lake H GPIO Implementation Summary (#817954)
  */
 #define GPP_E_START_OFFSET		0x9a0
-#define GPP_CPUJTAG_START_OFFSET	0x800
+#define GPP_RSVD_START_OFFSET	0x800
 #define GPP_H_START_OFFSET		0x8f0
 #define GPP_A_START_OFFSET		0xab0
 #define GPP_VGPIO3_START_OFFSET		0xc70
diff --git a/src/soc/intel/pantherlake/include/soc/gpio_soc_defs.h b/src/soc/intel/pantherlake/include/soc/gpio_soc_defs.h
index 69f2f7e4ac..49e34e0460 100644
--- a/src/soc/intel/pantherlake/include/soc/gpio_soc_defs.h
+++ b/src/soc/intel/pantherlake/include/soc/gpio_soc_defs.h
@@ -279,7 +279,7 @@
 #define GPP_JTAG_TRST_B		INC(GPP_DBG_PMODE)
 #define GPP_DDSP_HPDALV		INC(GPP_JTAG_TRST_B)
 
-#define NUM_GRP_CPUJTAG_PADS	(GPP_DDSP_HPDALV - GPP_EPD_ON + 1)
+#define NUM_GRP_RSVD_PADS	(GPP_DDSP_HPDALV - GPP_EPD_ON + 1)
 
 /*
  * +----------------------------+

From 73a3d621c0ad86b56c3ad1c5e33ff03c6e1eb60e Mon Sep 17 00:00:00 2001
From: Tim Crawford <tcrawford@system76.com>
Date: Fri, 12 Jul 2024 12:41:36 -0600
Subject: [PATCH 0392/3886] mb/system76/rpl: bonw15: Update GPIOs

Go through the schematics and update GPIOs for the unit. In particular,
explicitly mark unconnected pins and pins without placed components as
not connected.

Change-Id: I5a81115850d7bf3ecabeae29058e86cea51ac390
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84149
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
---
 .../system76/rpl/variants/bonw15/gpio.c       | 346 +++++++++---------
 1 file changed, 173 insertions(+), 173 deletions(-)

diff --git a/src/mainboard/system76/rpl/variants/bonw15/gpio.c b/src/mainboard/system76/rpl/variants/bonw15/gpio.c
index d38666e955..d0685d5dc4 100644
--- a/src/mainboard/system76/rpl/variants/bonw15/gpio.c
+++ b/src/mainboard/system76/rpl/variants/bonw15/gpio.c
@@ -11,13 +11,13 @@ static const struct pad_config gpio_table[] = {
 	PAD_CFG_NF(GPD3, UP_20K, PWROK, NF1), // PWR_BTN#
 	PAD_CFG_NF(GPD4, NONE, PWROK, NF1), // SUSB#_PCH
 	PAD_CFG_NF(GPD5, NONE, PWROK, NF1), // SUSC#_PCH
-	PAD_CFG_NF(GPD6, NONE, PWROK, NF1), // SLP_A#_N
+	PAD_NC(GPD6, NONE),
 	PAD_CFG_GPI(GPD7, NONE, PWROK), // GPD_7
 	PAD_CFG_NF(GPD8, NONE, PWROK, NF1), // CNVI_SUSCLK
 	PAD_CFG_GPO(GPD9, 0, PWROK), // SLP_WLAN_N
-	PAD_CFG_NF(GPD10, NONE, PWROK, NF1), // SLP_S5#
+	PAD_NC(GPD10, NONE),
 	PAD_CFG_GPO(GPD11, 0, DEEP), // LANPHYPC
-	PAD_CFG_GPO(GPD12, 0, DEEP), // TP_GPD_12
+	PAD_NC(GPD12, NONE),
 
 	/* ------- GPIO Group GPP_A ------- */
 	PAD_CFG_NF(GPP_A0, UP_20K, DEEP, NF1), // ESPI_IO0_EC
@@ -27,157 +27,157 @@ static const struct pad_config gpio_table[] = {
 	PAD_CFG_NF(GPP_A4, UP_20K, DEEP, NF1), // ESPI_CS_EC#
 	PAD_CFG_NF(GPP_A5, DN_20K, DEEP, NF1), // ESPI_CLK_EC
 	PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1), // ESPI_RESET_N
-	PAD_CFG_GPO(GPP_A7, 0, DEEP),
-	PAD_CFG_GPO(GPP_A8, 0, DEEP),
-	PAD_CFG_GPO(GPP_A9, 0, DEEP),
+	PAD_NC(GPP_A7, NONE),
+	PAD_NC(GPP_A8, NONE),
+	PAD_NC(GPP_A9, NONE),
 	PAD_CFG_NF(GPP_A10, NONE, DEEP, NF1), // ESPI_ALERT0#
-	PAD_CFG_GPI(GPP_A11, UP_20K, DEEP), // GPIO4_GC6_NVDD_EN_R
-	PAD_CFG_GPO(GPP_A12, 0, DEEP),
-	PAD_CFG_GPO(GPP_A13, 0, DEEP),
-	PAD_CFG_GPO(GPP_A14, 0, DEEP),
+	PAD_NC(GPP_A11, NONE),
+	PAD_NC(GPP_A12, NONE),
+	PAD_NC(GPP_A13, NONE),
+	PAD_NC(GPP_A14, NONE),
 
 	/* ------- GPIO Group GPP_B ------- */
 	_PAD_CFG_STRUCT(GPP_B0, 0x82900100, 0x0000), // TPM_PIRQ#
-	PAD_CFG_GPO(GPP_B1, 0, DEEP),
+	PAD_NC(GPP_B1, NONE),
 	PAD_CFG_GPI(GPP_B2, NONE, DEEP), // CNVI_WAKE#
 	PAD_CFG_GPO(GPP_B3, 1, DEEP), // PCH_BT_EN
-	PAD_CFG_GPO(GPP_B4, 0, DEEP),
-	PAD_CFG_GPO(GPP_B5, 0, DEEP),
-	PAD_CFG_GPO(GPP_B6, 0, DEEP),
-	PAD_CFG_GPO(GPP_B7, 0, DEEP),
-	PAD_CFG_GPO(GPP_B8, 0, DEEP),
-	PAD_CFG_GPO(GPP_B9, 0, DEEP),
-	PAD_CFG_GPO(GPP_B10, 0, DEEP),
-	PAD_CFG_GPO(GPP_B11, 0, DEEP),
-	PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), // SLP_S0#
+	PAD_NC(GPP_B4, NONE),
+	PAD_NC(GPP_B5, NONE),
+	PAD_NC(GPP_B6, NONE),
+	PAD_NC(GPP_B7, NONE),
+	PAD_NC(GPP_B8, NONE),
+	PAD_NC(GPP_B9, NONE),
+	PAD_NC(GPP_B10, NONE),
+	PAD_NC(GPP_B11, NONE),
+	PAD_NC(GPP_B12, NONE),
 	PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), // PLT_RST#
 	PAD_CFG_NF(GPP_B14, NONE, DEEP, NF1), // HDA_SPKR
-	PAD_CFG_GPO(GPP_B15, 0, DEEP), // PS8461_SW
-	PAD_CFG_GPO(GPP_B16, 0, DEEP),
-	PAD_CFG_GPO(GPP_B17, 1, RSMRST), // 2.5G_LAN_EN
-	PAD_CFG_NF(GPP_B18, NONE, RSMRST, NF1), // PMCALERT#
+	PAD_NC(GPP_B15, NONE), // PS8461_SW
+	PAD_NC(GPP_B16, NONE),
+	PAD_NC(GPP_B17, NONE), // 2.5G_LAN_EN
+	PAD_CFG_NF(GPP_B18, NONE, RSMRST, NF1), // PMCALERT# (tied high)
 	PAD_CFG_GPO(GPP_B19, 1, DEEP), // PCH_WLAN_EN
-	PAD_CFG_GPO(GPP_B20, 0, DEEP),
-	PAD_CFG_GPO(GPP_B21, 0, DEEP), // GPP_B21
+	PAD_NC(GPP_B20, NONE),
+	PAD_NC(GPP_B21, NONE),
 	PAD_CFG_GPO(GPP_B22, 1, DEEP), // LAN_RST#
-	PAD_CFG_GPI(GPP_B23, NONE, DEEP), // GPP_B23
+	PAD_CFG_GPI(GPP_B23, NONE, RSMRST), // GPP_B23 (XTAL FREQ SEL1)
 
 	/* ------- GPIO Group GPP_C ------- */
 	PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), // SMB_CLK
 	PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), // SMB_DATA
-	PAD_CFG_GPI(GPP_C2, NONE, PLTRST), // PCH_PORT80_LED
-	PAD_CFG_GPO(GPP_C3, 0, DEEP), // GPPC_I2C2_SDA
-	PAD_CFG_GPO(GPP_C4, 0, DEEP), // GPPC_I2C2_SCL
-	PAD_CFG_NF(GPP_C5, NONE, DEEP, NF1), // GPP_C_5_SML0ALERT_N
-	PAD_CFG_GPO(GPP_C6, 0, DEEP),
-	PAD_CFG_GPO(GPP_C7, 0, DEEP),
+	PAD_CFG_GPI(GPP_C2, NONE, PLTRST), // TLS confidentiality strap
+	PAD_CFG_GPO(GPP_C3, 0, DEEP), // GPPC_I2C2_SDA (Pantone)
+	PAD_CFG_GPO(GPP_C4, 0, DEEP), // GPPC_I2C2_SCL (Pantone)
+	PAD_NC(GPP_C5, NONE), // eSPI disable strap
+	PAD_NC(GPP_C6, NONE),
+	PAD_NC(GPP_C7, NONE),
 	PAD_CFG_GPI(GPP_C8, NONE, DEEP), // TPM_DET
-	PAD_CFG_GPO(GPP_C9, 0, DEEP),
-	PAD_CFG_GPO(GPP_C10, 0, DEEP),
-	PAD_CFG_GPO(GPP_C11, 0, DEEP),
-	PAD_CFG_GPO(GPP_C12, 0, DEEP),
-	PAD_CFG_GPO(GPP_C13, 0, DEEP),
-	PAD_CFG_GPO(GPP_C14, 0, DEEP),
-	PAD_CFG_GPO(GPP_C15, 0, DEEP),
+	PAD_NC(GPP_C9, NONE),
+	PAD_NC(GPP_C10, NONE),
+	PAD_NC(GPP_C11, NONE),
+	PAD_NC(GPP_C12, NONE),
+	PAD_NC(GPP_C13, NONE),
+	PAD_NC(GPP_C14, NONE),
+	PAD_NC(GPP_C15, NONE),
 	PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1), // I2C_SDA_TP
 	PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1), // I2C_SCL_TP
-	PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1), // PCH_I2C_SDA
-	PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1), // PCH_I2C_SCL
+	PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1), // PCH_I2C_SDA (TPS65994)
+	PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1), // PCH_I2C_SCL (TPS65994)
 	// GPP_C20 (UART2_RXD) configured in bootblock
 	// GPP_C21 (UART2_TXD) configured in bootblock
-	PAD_CFG_GPO(GPP_C22, 0, DEEP), // ROM_I2C_EN
-	PAD_CFG_GPO(GPP_C23, 0, DEEP),
+	PAD_CFG_GPO(GPP_C22, 0, DEEP), // ROM_I2C_EN (TPS65994)
+	PAD_NC(GPP_C23, NONE),
 
 	/* ------- GPIO Group GPP_D ------- */
-	PAD_CFG_GPO(GPP_D0, 0, DEEP),
-	PAD_CFG_GPO(GPP_D1, 0, DEEP),
-	PAD_CFG_GPO(GPP_D2, 0, DEEP),
-	PAD_CFG_GPO(GPP_D3, 0, DEEP), // GFX_DETECT_STRAP
-	PAD_CFG_GPO(GPP_D4, 0, DEEP), // GPP_D4_SML1CLK
+	PAD_NC(GPP_D0, NONE),
+	PAD_NC(GPP_D1, NONE),
+	PAD_NC(GPP_D2, NONE),
+	PAD_NC(GPP_D3, NONE), // GFX_DETECT_STRAP
+	PAD_NC(GPP_D4, NONE),
 	PAD_CFG_GPO(GPP_D5, 1, DEEP), // M.2_BT_PCMFRM_CRF_RST_N
 	// GPP_D6 (M.2_BT_PCMOUT_CLKREQ0) configured by FSP
-	PAD_CFG_GPO(GPP_D7, 0, DEEP), // GPP_D7
-	PAD_NC(GPP_D8, NONE), // GPP_D8
-	PAD_CFG_NF(GPP_D9, NATIVE, DEEP, NF1), // GPP_D9_SML0CLK
-	PAD_CFG_NF(GPP_D10, NATIVE, DEEP, NF1), // GPP_D10_SML0DATA
-	PAD_CFG_NF(GPP_D11, NATIVE, DEEP, NF1),
-	PAD_CFG_NF(GPP_D12, NATIVE, DEEP, NF1),
-	PAD_CFG_NF(GPP_D13, NATIVE, DEEP, NF1),
-	PAD_CFG_NF(GPP_D14, NATIVE, DEEP, NF1),
-	PAD_CFG_NF(GPP_D15, NATIVE, DEEP, NF1), // GPP_D15_SML1DATA
-	PAD_CFG_NF(GPP_D16, NATIVE, DEEP, NF1),
-	PAD_CFG_NF(GPP_D17, NATIVE, DEEP, NF1),
-	PAD_CFG_NF(GPP_D18, NATIVE, DEEP, NF1),
-	PAD_CFG_NF(GPP_D19, NATIVE, DEEP, NF1),
-	PAD_CFG_NF(GPP_D20, NONE, DEEP, NF1),
-	PAD_CFG_NF(GPP_D21, NONE, DEEP, NF1),
-	PAD_CFG_NF(GPP_D22, NONE, DEEP, NF1),
-	PAD_CFG_NF(GPP_D23, NONE, DEEP, NF1),
+	PAD_NC(GPP_D7, NONE),
+	PAD_NC(GPP_D8, NONE),
+	PAD_NC(GPP_D9, NONE),
+	PAD_NC(GPP_D10, NONE),
+	PAD_NC(GPP_D11, NONE),
+	PAD_NC(GPP_D12, NONE),
+	PAD_NC(GPP_D13, NONE),
+	PAD_NC(GPP_D14, NONE),
+	PAD_NC(GPP_D15, NONE),
+	PAD_NC(GPP_D16, NONE),
+	PAD_NC(GPP_D17, NONE),
+	PAD_NC(GPP_D18, NONE),
+	PAD_NC(GPP_D19, NONE),
+	PAD_NC(GPP_D20, NONE),
+	PAD_NC(GPP_D21, NONE),
+	PAD_NC(GPP_D22, NONE),
+	PAD_NC(GPP_D23, NONE),
 
 	/* ------- GPIO Group GPP_E ------- */
-	PAD_CFG_GPO(GPP_E0, 0, DEEP),
-	PAD_CFG_GPO(GPP_E1, 0, DEEP),
-	PAD_CFG_GPO(GPP_E2, 0, DEEP),
-	PAD_CFG_GPO(GPP_E3, 0, DEEP),
-	PAD_CFG_GPO(GPP_E4, 0, DEEP),
-	PAD_CFG_GPO(GPP_E5, 0, DEEP),
-	PAD_CFG_GPO(GPP_E6, 0, DEEP),
+	PAD_NC(GPP_E0, NONE),
+	PAD_NC(GPP_E1, NONE),
+	PAD_NC(GPP_E2, NONE),
+	PAD_NC(GPP_E3, NONE),
+	PAD_NC(GPP_E4, NONE),
+	PAD_NC(GPP_E5, NONE),
+	PAD_NC(GPP_E6, NONE),
 	PAD_CFG_GPI_INT(GPP_E7, NONE, PLTRST, LEVEL), // TP_ATTN#
 	PAD_CFG_NF(GPP_E8, NONE, DEEP, NF1), // SATA_LED#
-	PAD_NC(GPP_E9, NONE), // GPP_E_9_USB_OC0_N
-	PAD_NC(GPP_E10, NONE), // GPP_E_10_USB_OC1_N
-	PAD_NC(GPP_E11, NONE), // GPP_E_11_USB_OC2_N
-	PAD_NC(GPP_E12, NONE), // GPP_E_12_USB_OC3_N
-	PAD_CFG_GPO(GPP_E13, 0, DEEP),
-	PAD_CFG_GPO(GPP_E14, 0, DEEP),
-	PAD_CFG_GPO(GPP_E15, 0, DEEP),
-	PAD_CFG_GPO(GPP_E16, 0, DEEP),
-	PAD_CFG_GPO(GPP_E17, 0, DEEP),
+	PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1), // GPP_E_9_USB_OC0_N
+	PAD_CFG_NF(GPP_E10, NONE, DEEP, NF1), // GPP_E_10_USB_OC1_N
+	PAD_CFG_NF(GPP_E11, NONE, DEEP, NF1), // GPP_E_11_USB_OC2_N
+	PAD_CFG_NF(GPP_E12, NONE, DEEP, NF1), // GPP_E_12_USB_OC3_N
+	PAD_NC(GPP_E13, NONE),
+	PAD_NC(GPP_E14, NONE),
+	PAD_NC(GPP_E15, NONE),
+	PAD_NC(GPP_E16, NONE),
+	PAD_NC(GPP_E17, NONE),
 	PAD_CFG_GPO(GPP_E18, 1, DEEP), // SB_BLON
-	PAD_CFG_GPO(GPP_E19, 0, DEEP),
-	PAD_CFG_GPO(GPP_E20, 0, DEEP),
-	PAD_CFG_GPO(GPP_E21, 0, DEEP),
+	PAD_NC(GPP_E19, NONE),
+	PAD_NC(GPP_E20, NONE),
+	PAD_NC(GPP_E21, NONE),
 
 	/* ------- GPIO Group GPP_F ------- */
-	PAD_CFG_GPO(GPP_F0, 0, DEEP),
-	PAD_CFG_GPO(GPP_F1, 0, DEEP),
-	PAD_CFG_GPO(GPP_F2, 0, DEEP),
-	PAD_CFG_GPO(GPP_F3, 0, DEEP),
-	PAD_CFG_GPO(GPP_F4, 0, DEEP),
+	PAD_NC(GPP_F0, NONE),
+	PAD_NC(GPP_F1, NONE),
+	PAD_NC(GPP_F2, NONE),
+	PAD_NC(GPP_F3, NONE),
+	PAD_NC(GPP_F4, NONE),
 	PAD_CFG_GPO(GPP_F5, 1, PLTRST), // GPP_F5_TBT_RTD3
-	PAD_CFG_GPO(GPP_F6, 0, DEEP),
-	PAD_CFG_GPO(GPP_F7, 0, DEEP),
+	PAD_NC(GPP_F6, NONE),
+	PAD_NC(GPP_F7, NONE),
 	PAD_CFG_GPI(GPP_F8, NONE, DEEP), // GC6_FB_EN_PCH
 	_PAD_CFG_STRUCT(GPP_F9, 0x42880100, 0x0000), // GPP_F9_TBT_WAKE#
-	PAD_CFG_GPO(GPP_F10, 0, DEEP),
-	PAD_CFG_GPO(GPP_F11, 0, DEEP),
-	PAD_CFG_GPO(GPP_F12, 0, DEEP),
-	PAD_CFG_GPO(GPP_F13, 0, DEEP),
-	PAD_CFG_GPO(GPP_F14, 0, DEEP), // PS_ON#
+	PAD_NC(GPP_F10, NONE),
+	PAD_NC(GPP_F11, NONE),
+	PAD_NC(GPP_F12, NONE),
+	PAD_NC(GPP_F13, NONE),
+	PAD_NC(GPP_F14, NONE),
 	PAD_CFG_GPI(GPP_F15, NONE, DEEP), // H_SKTOCC_N
 	PAD_CFG_GPO(GPP_F16, 1, DEEP), // GPP_F16_TBT_RST#
-	PAD_CFG_GPO(GPP_F17, 0, DEEP),
+	PAD_NC(GPP_F17, NONE),
 	PAD_CFG_GPO(GPP_F18, 0, DEEP), // CCD_FW_WP#
 	PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1), // NB_ENAVDD
 	PAD_CFG_NF(GPP_F20, NONE, DEEP, NF1), // BLON
 	PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1), // EDP_BRIGHTNESS
 	// GPP_F22 (DGPU_PWR_EN) configured in bootblock
-	PAD_CFG_GPO(GPP_F23, 0, DEEP),
+	PAD_NC(GPP_F23, NONE),
 
 	/* ------- GPIO Group GPP_G ------- */
-	PAD_CFG_GPO(GPP_G0, 0, RSMRST), // TBT_USB_FORCE_PWR
-	PAD_CFG_GPI(GPP_G1, NONE, DEEP), // GPP_G1
-	PAD_CFG_GPI(GPP_G2, DN_20K, DEEP), // DNX_FORCE_RELOAD
-	PAD_CFG_GPI(GPP_G3, NONE, DEEP), // GPP_G3
-	PAD_CFG_GPI(GPP_G4, NONE, DEEP), // GPP_G4
+	PAD_NC(GPP_G0, NONE),
+	PAD_CFG_GPI(GPP_G1, NONE, DEEP), // GPU SKU strap (L: X9, H: X11)
+	PAD_NC(GPP_G2, NONE),
+	PAD_CFG_GPI(GPP_G3, NONE, DEEP), // DDS strap (L: Non-DDS, H: DDS)
+	PAD_CFG_GPI(GPP_G4, NONE, DEEP), // Unused strap
 	PAD_CFG_NF(GPP_G5, NONE, DEEP, NF1), // SLP_DRAM_N
-	PAD_CFG_GPI(GPP_G6, NONE, DEEP), // GPP_G6
+	PAD_CFG_GPI(GPP_G6, NONE, DEEP), // Pantone (L: W/O, H: W)
 	_PAD_CFG_STRUCT(GPP_G7, 0x42800100, 0x0000), // TBCIO_PLUG_EVENT#
 
 	/* ------- GPIO Group GPP_H ------- */
 	PAD_CFG_GPI(GPP_H0, NONE, DEEP), // VAL_SV_ADVANCE_STRAP
-	PAD_CFG_GPO(GPP_H1, 0, DEEP),
-	PAD_CFG_GPI(GPP_H2, NONE, DEEP), // WLAN_WAKE_N
+	PAD_NC(GPP_H1, NONE),
+	PAD_NC(GPP_H2, NONE), // WLAN_WAKE_N
 	// GPP_H3 (WLAN_CLKREQ9#) configured by FSP
 	// GPP_H4 (SSD1_CLKREQ10#) configured by FSP
 	// GPP_H5 (SSD2_CLKREQ11#) configured by FSP
@@ -185,45 +185,45 @@ static const struct pad_config gpio_table[] = {
 	// GPP_H7 (GLAN_CLKREQ13#) configured by FSP
 	// GPP_H8 (GPU_PCIE_CLKREQ14#) configured by FSP
 	// GPP_H9 (TBT_CLKREQ15#) configured by FSP
-	PAD_CFG_NF(GPP_H10, NONE, DEEP, NF1), // GPP_H10_SML2CLK
-	PAD_CFG_NF(GPP_H11, NONE, DEEP, NF1), // GPP_H11_SML2DATA
-	PAD_CFG_GPI(GPP_H12, NONE, DEEP), // GPP_H12
-	PAD_CFG_NF(GPP_H13, NONE, DEEP, NF1), // GPP_H13_SML3CLK
-	PAD_CFG_NF(GPP_H14, NONE, DEEP, NF1), // GPP_H14_SML3DATA
-	PAD_CFG_GPI(GPP_H15, NONE, DEEP), // GPP_H_15_SML3ALERT_N
-	PAD_CFG_GPI(GPP_H16, NONE, DEEP),
+	PAD_NC(GPP_H10, NONE),
+	PAD_NC(GPP_H11, NONE),
+	PAD_CFG_GPI(GPP_H12, NONE, RSMRST), // eSPI flash sharing mode strap (L: MAF, H: SAF)
+	PAD_NC(GPP_H13, NONE),
+	PAD_NC(GPP_H14, NONE),
+	PAD_CFG_GPI(GPP_H15, NONE, RSMRST), // JTAG ODT disable strap (L: Disable, H: Enable)
+	PAD_NC(GPP_H16, NONE),
 	PAD_CFG_GPO(GPP_H17, 1, DEEP), // M.2_PLT_RST_CNTRL3#
-	PAD_CFG_GPI(GPP_H18, NONE, DEEP), // GPP_H18
-	PAD_CFG_GPO(GPP_H19, 0, DEEP),
-	PAD_CFG_GPO(GPP_H20, 0, DEEP),
-	PAD_CFG_GPO(GPP_H21, 1, DEEP), // TBT_MRESET_PCH
-	PAD_CFG_GPO(GPP_H22, 0, DEEP),
-	PAD_CFG_GPI(GPP_H23, NONE, DEEP), // TIME_SYNC0
+	PAD_CFG_GPI(GPP_H18, NONE, RSMRST), // VCCPSPI strap (L: 3.3V, H: 1.8V)
+	PAD_NC(GPP_H19, NONE),
+	PAD_NC(GPP_H20, NONE),
+	PAD_NC(GPP_H21, NONE), // TBT_MRESET_PCH
+	PAD_NC(GPP_H22, NONE),
+	PAD_NC(GPP_H23, NONE),
 
 	/* ------- GPIO Group GPP_I ------- */
-	PAD_CFG_GPO(GPP_I0, 0, DEEP),
+	PAD_NC(GPP_I0, NONE),
 	_PAD_CFG_STRUCT(GPP_I1, 0x86880100, 0x0000), // G_DP_DHPD_E
 	_PAD_CFG_STRUCT(GPP_I2, 0x86880100, 0x0000), // DP_D_HPD
 	_PAD_CFG_STRUCT(GPP_I3, 0x86880100, 0x0000), // HDMI_HPD
 	_PAD_CFG_STRUCT(GPP_I4, 0x86880100, 0x0000), // DP_A_HPD
-	PAD_CFG_GPO(GPP_I5, 0, DEEP),
-	PAD_CFG_GPO(GPP_I6, 0, DEEP),
-	PAD_CFG_GPO(GPP_I7, 0, DEEP),
-	PAD_CFG_GPO(GPP_I8, 0, DEEP),
-	PAD_CFG_GPO(GPP_I9, 0, DEEP),
-	PAD_CFG_GPO(GPP_I10, 0, DEEP),
-	PAD_NC(GPP_I11, NONE), // GPP_I_11_USB_OC4_N
-	PAD_NC(GPP_I12, NONE), // GPP_I_12_USB_OC5_N
-	PAD_NC(GPP_I13, NONE), // GPP_I_13_USB_OC6_N
-	PAD_NC(GPP_I14, NONE), // GPP_I_14_USB_OC7_N
-	PAD_CFG_GPO(GPP_I15, 0, DEEP),
-	PAD_CFG_GPO(GPP_I16, 0, DEEP),
-	PAD_CFG_GPO(GPP_I17, 0, DEEP),
-	PAD_CFG_GPI(GPP_I18, NONE, DEEP), // GPP_I18
-	PAD_CFG_GPO(GPP_I19, 0, DEEP),
-	PAD_CFG_GPO(GPP_I20, 0, DEEP),
-	PAD_CFG_GPO(GPP_I21, 0, DEEP),
-	PAD_CFG_GPI(GPP_I22, NONE, DEEP), // GPP_I22
+	PAD_NC(GPP_I5, NONE),
+	PAD_NC(GPP_I6, NONE),
+	PAD_NC(GPP_I7, NONE),
+	PAD_NC(GPP_I8, NONE),
+	PAD_NC(GPP_I9, NONE),
+	PAD_NC(GPP_I10, NONE),
+	PAD_CFG_NF(GPP_I11, NONE, DEEP, NF1), // GPP_I_11_USB_OC4_N
+	PAD_CFG_NF(GPP_I12, NONE, DEEP, NF1), // GPP_I_12_USB_OC5_N
+	PAD_CFG_NF(GPP_I13, NONE, DEEP, NF1), // GPP_I_13_USB_OC6_N
+	PAD_CFG_NF(GPP_I14, NONE, DEEP, NF1), // GPP_I_14_USB_OC7_N
+	PAD_NC(GPP_I15, NONE),
+	PAD_NC(GPP_I16, NONE),
+	PAD_NC(GPP_I17, NONE),
+	PAD_CFG_GPI(GPP_I18, NONE, PWROK), // No reboot strap (L: Disable, H: Enable)
+	PAD_NC(GPP_I19, NONE),
+	PAD_NC(GPP_I20, NONE),
+	PAD_NC(GPP_I21, NONE),
+	PAD_CFG_GPI(GPP_I22, NONE, PWROK), // Boot BIOS strap (L: MAF or SAF, H: eSPI)
 
 	/* ------- GPIO Group GPP_J ------- */
 	PAD_CFG_NF(GPP_J0, NONE, DEEP, NF1), // CNVI_GNSS_PA_BLANKING
@@ -235,23 +235,23 @@ static const struct pad_config gpio_table[] = {
 	PAD_CFG_NF(GPP_J6, NONE, DEEP, NF1), // CNVI_MFUART2_RXD
 	PAD_CFG_NF(GPP_J7, NONE, DEEP, NF1), // CNVI_MFUART2_TXD
 	PAD_CFG_GPI(GPP_J8, NONE, DEEP), // VAL_TEST_SETUP_MENU
-	PAD_CFG_GPO(GPP_J9, 0, DEEP),
-	PAD_CFG_GPO(GPP_J10, 0, DEEP),
-	PAD_CFG_GPO(GPP_J11, 0, DEEP),
+	PAD_NC(GPP_J9, NONE),
+	PAD_NC(GPP_J10, NONE),
+	PAD_NC(GPP_J11, NONE),
 
 	/* ------- GPIO Group GPP_K ------- */
-	PAD_CFG_GPO(GPP_K0, 0, DEEP),
-	PAD_CFG_GPO(GPP_K1, 0, DEEP),
-	PAD_CFG_GPO(GPP_K2, 0, DEEP),
-	PAD_CFG_GPO(GPP_K3, 0, DEEP),
-	PAD_CFG_GPO(GPP_K4, 0, DEEP),
-	PAD_CFG_GPO(GPP_K5, 0, DEEP),
-	PAD_CFG_NF(GPP_K6, NONE, DEEP, NF2),
-	PAD_CFG_NF(GPP_K7, NONE, DEEP, NF2),
+	PAD_NC(GPP_K0, NONE),
+	PAD_NC(GPP_K1, NONE),
+	PAD_NC(GPP_K2, NONE),
+	PAD_NC(GPP_K3, NONE),
+	PAD_NC(GPP_K4, NONE),
+	PAD_NC(GPP_K5, NONE),
+	// GPP_K6 missing
+	// GPP_K7 missing
 	PAD_CFG_NF(GPP_K8, NONE, DEEP, NF1), // GPP_K_8_CORE_VID_0
 	PAD_CFG_NF(GPP_K9, NONE, DEEP, NF1), // GPP_K_9_CORE_VID_1
 	PAD_CFG_NF(GPP_K10, NONE, DEEP, NF2),
-	PAD_CFG_GPO(GPP_K11, 0, DEEP),
+	PAD_NC(GPP_K11, NONE),
 
 	/* ------- GPIO Group GPP_R ------- */
 	PAD_CFG_NF(GPP_R0, NONE, DEEP, NF1), // HDA_BITCLK
@@ -259,33 +259,33 @@ static const struct pad_config gpio_table[] = {
 	PAD_CFG_NF(GPP_R2, NATIVE, DEEP, NF1), // HDA_SDOUT
 	PAD_CFG_NF(GPP_R3, NATIVE, DEEP, NF1), // HDA_SDIN0
 	PAD_CFG_NF(GPP_R4, NONE, DEEP, NF1), // HDA_RST#
-	PAD_CFG_GPO(GPP_R5, 0, DEEP),
-	PAD_CFG_GPO(GPP_R6, 0, DEEP),
-	PAD_CFG_GPO(GPP_R7, 0, DEEP),
+	PAD_NC(GPP_R5, NONE),
+	PAD_NC(GPP_R6, NONE),
+	PAD_NC(GPP_R7, NONE),
 	PAD_CFG_GPI(GPP_R8, NONE, DEEP), // DGPU_PWRGD
 	PAD_CFG_NF(GPP_R9, NONE, DEEP, NF1), // EDP_HPD
-	PAD_CFG_GPO(GPP_R10, 0, DEEP),
-	PAD_CFG_GPO(GPP_R11, 0, DEEP),
-	PAD_CFG_GPO(GPP_R12, 0, DEEP),
-	PAD_CFG_GPO(GPP_R13, 0, DEEP),
-	PAD_CFG_GPO(GPP_R14, 0, DEEP),
-	PAD_CFG_GPO(GPP_R15, 0, DEEP),
+	PAD_NC(GPP_R10, NONE),
+	PAD_NC(GPP_R11, NONE),
+	PAD_NC(GPP_R12, NONE),
+	PAD_NC(GPP_R13, NONE),
+	PAD_NC(GPP_R14, NONE),
+	PAD_NC(GPP_R15, NONE),
 	// GPP_R16 (DGPU_RST#_PCH) configured in bootblock
-	PAD_CFG_GPO(GPP_R17, 0, DEEP),
-	PAD_CFG_GPO(GPP_R18, 0, DEEP),
-	PAD_CFG_GPO(GPP_R19, 0, DEEP),
-	PAD_CFG_GPO(GPP_R20, 0, DEEP),
-	PAD_CFG_GPO(GPP_R21, 0, DEEP),
+	PAD_NC(GPP_R17, NONE),
+	PAD_NC(GPP_R18, NONE),
+	PAD_NC(GPP_R19, NONE),
+	PAD_NC(GPP_R20, NONE),
+	PAD_NC(GPP_R21, NONE),
 
 	/* ------- GPIO Group GPP_S ------- */
-	PAD_CFG_GPO(GPP_S0, 0, DEEP),
-	PAD_CFG_GPO(GPP_S1, 0, DEEP),
-	PAD_CFG_GPO(GPP_S2, 0, DEEP),
-	PAD_CFG_GPO(GPP_S3, 0, DEEP),
-	PAD_CFG_GPO(GPP_S4, 0, DEEP), // GPPS_DMIC_CLK
-	PAD_CFG_GPO(GPP_S5, 0, DEEP), // GPPS_DMIC_DATA
-	PAD_CFG_GPO(GPP_S6, 0, DEEP),
-	PAD_CFG_GPO(GPP_S7, 0, DEEP),
+	PAD_NC(GPP_S0, NONE),
+	PAD_NC(GPP_S1, NONE),
+	PAD_NC(GPP_S2, NONE),
+	PAD_NC(GPP_S3, NONE),
+	PAD_NC(GPP_S4, NONE), // GPPS_DMIC_CLK
+	PAD_NC(GPP_S5, NONE), // GPPS_DMIC_DATA
+	PAD_NC(GPP_S6, NONE),
+	PAD_NC(GPP_S7, NONE),
 };
 
 void mainboard_configure_gpios(void)

From 06b818aa48f67cee11706f2950e6667b8eb112f0 Mon Sep 17 00:00:00 2001
From: Tongtong Pan <pantongtong@huaqin.corp-partner.google.com>
Date: Mon, 10 Mar 2025 15:24:20 +0800
Subject: [PATCH 0393/3886] mb/google/fatcat/var/felino: Add fw_config probe
 for felino

Use fw_config to probe WIFI,AUDIO,STORAGE and PDC_CONTROL Type.

BUG=b:388982526
TEST=emerge-fatcat coreboot

Change-Id: I97edbb2d9b8fb29a18a3f701d16d3a7818716581
Signed-off-by: Tongtong Pan <pantongtong@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86780
Reviewed-by: YH Lin <yueherngl@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jayvik Desai <jayvik@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
---
 .../google/fatcat/variants/felino/Makefile.mk |  2 +
 .../google/fatcat/variants/felino/fw_config.c |  9 ++++
 .../fatcat/variants/felino/overridetree.cb    | 47 +++++++++++++++++--
 3 files changed, 53 insertions(+), 5 deletions(-)
 create mode 100644 src/mainboard/google/fatcat/variants/felino/fw_config.c

diff --git a/src/mainboard/google/fatcat/variants/felino/Makefile.mk b/src/mainboard/google/fatcat/variants/felino/Makefile.mk
index 4c33dad4db..dcd5ec7202 100644
--- a/src/mainboard/google/fatcat/variants/felino/Makefile.mk
+++ b/src/mainboard/google/fatcat/variants/felino/Makefile.mk
@@ -4,3 +4,5 @@ bootblock-y += gpio.c
 romstage-y += gpio.c
 romstage-y += memory.c
 ramstage-y += gpio.c
+romstage-$(CONFIG_FW_CONFIG) += fw_config.c
+ramstage-$(CONFIG_FW_CONFIG) += fw_config.c
diff --git a/src/mainboard/google/fatcat/variants/felino/fw_config.c b/src/mainboard/google/fatcat/variants/felino/fw_config.c
new file mode 100644
index 0000000000..4221a5bf8e
--- /dev/null
+++ b/src/mainboard/google/fatcat/variants/felino/fw_config.c
@@ -0,0 +1,9 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <fw_config.h>
+#include <sar.h>
+
+const char *get_wifi_sar_cbfs_filename(void)
+{
+	return get_wifi_sar_fw_config_filename(FW_CONFIG_FIELD(WIFI));
+}
diff --git a/src/mainboard/google/fatcat/variants/felino/overridetree.cb b/src/mainboard/google/fatcat/variants/felino/overridetree.cb
index c13aa43a91..10dce4bcb0 100644
--- a/src/mainboard/google/fatcat/variants/felino/overridetree.cb
+++ b/src/mainboard/google/fatcat/variants/felino/overridetree.cb
@@ -1,14 +1,44 @@
 fw_config
-	field PDC_CONTROL 0 1
-		option PDC_RTS			0
-		option PDC_TI			1
+	field AUDIO 0 1
+		option AUDIO_UNKNOWN		0
+		option AUDIO_ALC712_SNDW	1
 	end
-	field STORAGE 15 16
+	field WIFI 2 3
+		option WIFI_CNVI_6			0
+		option WIFI_CNVI_7			1
+		option WIFI_PCIE_6			2
+		option WIFI_PCIE_7			3
+	end
+	field TOUCHSCREEN 4 4
+		option NONE_TOUCH		0
+	end
+	field TOUCHPAD 5 6
+		option TOUCHPAD_UNKNOWN		0
+		option TOUCHPAD_LPSS_I2C	1
+		option TOUCHPAD_THC_I2C		2
+	end
+	field SD 7 7
+		option SD_UNKNOWN		0
+		option SD_GENSYS		1
+	end
+	field STORAGE 8 9
 		option STORAGE_UNKNOWN		0
 		option STORAGE_NVME_GEN4	1
 		option STORAGE_NVME_GEN5	2
 		option STORAGE_UFS		3
 	end
+	field KB 10 11
+		option KB_UNKNOWN		0
+		option KB_NO_BL			1
+	end
+	field UFC 12 12
+		option UFC_UNKNOWN		0
+		option UFC_1080P		1
+	end
+	field PDC_CONTROL 13 13
+		option PDC_RTS			0
+		option PDC_TI			1
+	end
 end
 
 chip soc/intel/pantherlake
@@ -180,7 +210,9 @@ device ref tbt_pcie_rp0 on end
 			end
 		end # SD Card
 
-		device ref pcie_rp3 on
+		device ref pcie_rp4 on
+			probe WIFI WIFI_PCIE_6
+			probe WIFI WIFI_PCIE_7
 			register "pcie_rp[PCH_RP(4)]" = "{
 				.clk_src = 4,
 				.clk_req = 4,
@@ -200,6 +232,8 @@ device ref tbt_pcie_rp0 on end
 		end #  WLAN
 
 		device ref pcie_rp9 on
+			probe STORAGE STORAGE_UNKNOWN
+			probe STORAGE STORAGE_NVME_GEN5
 			register "pcie_rp[PCIE_RP(9)]" = "{
 			.clk_src = 0,
 			.clk_req = 0,
@@ -213,6 +247,7 @@ device ref tbt_pcie_rp0 on end
 		end # Gen5 SSD
 
 		device ref hda on
+			probe AUDIO AUDIO_ALC712_SNDW
 			chip drivers/intel/soundwire
 				device generic 0 on
 					chip drivers/soundwire/alc711
@@ -226,6 +261,8 @@ device ref tbt_pcie_rp0 on end
 		end
 
 		device ref cnvi_wifi on
+			probe WIFI WIFI_CNVI_6
+			probe WIFI WIFI_CNVI_7
 			chip drivers/wifi/generic
 				register "wake" = "GPE0_PME_B0"
 				register "add_acpi_dma_property" = "true"

From 925eacb50faa324d1187b3332df4ce2172650a03 Mon Sep 17 00:00:00 2001
From: Tongtong Pan <pantongtong@huaqin.corp-partner.google.com>
Date: Tue, 11 Mar 2025 14:00:08 +0800
Subject: [PATCH 0394/3886] mb/google/fatcat/var/felino: Modify the gpio.c to
 poweroff

Modify the config for GPP_F09 to poweroff successfully.

BUG=b:388202483
TEST=Build felino and poweroff under the OS and the dut can poweroff successfully.

Change-Id: I1c83d230be7dbce9f9ad0b55f86d748e2de3565e
Signed-off-by: Tongtong Pan <pantongtong@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86808
Reviewed-by: Jayvik Desai <jayvik@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com>
---
 src/mainboard/google/fatcat/variants/felino/gpio.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/mainboard/google/fatcat/variants/felino/gpio.c b/src/mainboard/google/fatcat/variants/felino/gpio.c
index a32d44b7d5..7f67a40ae6 100644
--- a/src/mainboard/google/fatcat/variants/felino/gpio.c
+++ b/src/mainboard/google/fatcat/variants/felino/gpio.c
@@ -265,8 +265,8 @@ static const struct pad_config gpio_table[] = {
 	PAD_NC(GPP_F07, NONE),
 	/* GPP_F08:     NC */
 	PAD_NC(GPP_F08, NONE),
-	/* GPP_F09:     NC */
-	PAD_NC(GPP_F09, NONE),
+	/* GPP_F09:     SX_EXIT_HOLDOFF# */
+	PAD_CFG_NF(GPP_F09, NONE, DEEP, NF2),
 	/* GPP_F10:     HW_ID7 */
 	PAD_CFG_GPO(GPP_F10, 0, PLTRST),
 	/* GPP_F11:     TC_RETIMER_FORCE_PWR */

From e6c66068848e33ed29cc8d2c056703c2b7445d68 Mon Sep 17 00:00:00 2001
From: Filip Brozovic <fbrozovic@gmail.com>
Date: Sat, 1 Mar 2025 23:34:18 +0100
Subject: [PATCH 0395/3886] Revert "soc/intel/alderlake: Guard
 PchPcieClockGating & PchPciePowerGating UPDs"
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

This reverts commit 491afc3cc778ba82154f405061922da5024357c5.

Reason for revert: Starting with FSP MR6, the 'PchPcieClockGating' and
'PchPciePowerGating' UPDs are also available on ADL-N.

Change-Id: I0134737cfb956163ea6e722cd0a3f39dffbaa13b
Signed-off-by: Filip Brozovic <fbrozovic@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86680
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-by: Jayvik Desai <jayvik@google.com>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
---
 src/soc/intel/alderlake/fsp_params.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/soc/intel/alderlake/fsp_params.c b/src/soc/intel/alderlake/fsp_params.c
index cbfd223d6a..d9204b4097 100644
--- a/src/soc/intel/alderlake/fsp_params.c
+++ b/src/soc/intel/alderlake/fsp_params.c
@@ -922,7 +922,7 @@ static void fill_fsps_pcie_params(FSP_S_CONFIG *s_cfg,
 	}
 	s_cfg->PcieComplianceTestMode = CONFIG(SOC_INTEL_COMPLIANCE_TEST_MODE);
 
-#if CONFIG(FSP_TYPE_IOT) && !CONFIG(SOC_INTEL_ALDERLAKE_PCH_N)
+#if CONFIG(FSP_TYPE_IOT)
 	/*
 	 * Intel requires that all enabled PCH PCIe ports have a CLK_REQ signal connected.
 	 * The CLK_REQ is used to wake the silicon when link entered L1 link-state. L1

From ef855f19f057c1a46d25dfc34e8539ad1d4f7043 Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Wed, 12 Mar 2025 14:48:06 -0500
Subject: [PATCH 0396/3886] soc/intel/meteorlake: Fix logic for FSP repo use

Commit a7a76b0deea3 ("soc/intel/meteorlake: Hook up FSP repo for IOT")
added logic to use the FSP repo for IOT boards, but in doing so
broke the automatic selection of FSP_USE_REPO when HAVE_INTEL_FSP_REPO
was selected. Fix this by removing the override for FSP_USE_REPO and
selecting HAVE_INTEL_FSP_REPO when FSP_TYPE_IOT is selected.

TEST=build/boot starlabs/starbook_mtl with IOT FSP binaries/headers

Change-Id: Iad946a23c569e27cafa35ce2e6fefd6be1d90666
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86845
Reviewed-by: Zhixing Ma <zhixing.ma@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
---
 src/soc/intel/meteorlake/Kconfig | 6 +-----
 1 file changed, 1 insertion(+), 5 deletions(-)

diff --git a/src/soc/intel/meteorlake/Kconfig b/src/soc/intel/meteorlake/Kconfig
index 5d1b3fe6d1..8a51abd496 100644
--- a/src/soc/intel/meteorlake/Kconfig
+++ b/src/soc/intel/meteorlake/Kconfig
@@ -25,6 +25,7 @@ config SOC_INTEL_METEORLAKE
 	select GENERIC_GPIO_LIB
 	select HAVE_DEBUG_RAM_SETUP
 	select HAVE_FSP_GOP
+	select HAVE_INTEL_FSP_REPO if FSP_TYPE_IOT
 	select HAVE_HYPERTHREADING
 	select HAVE_INTEL_COMPLIANCE_TEST_MODE
 	select HAVE_SMI_HANDLER
@@ -346,15 +347,10 @@ config CONSOLE_CBMEM_BUFFER_SIZE
 
 config FSP_TYPE_IOT
 	bool
-	select HAVE_INTEL_FSP_REPO
 	default n
 	help
 	  This option allows to select FSP IOT type from 3rdparty/fsp repo
 
-config FSP_USE_REPO
-	default y if FSP_TYPE_IOT
-	default n
-
 config FSP_HEADER_PATH
 	string "Location of FSP headers"
 	default "3rdparty/fsp/MeteorLakeFspBinPkg/IoT/MeteorLake/Include" if FSP_USE_REPO && FSP_TYPE_IOT

From 7322906feda83ab5518d89bbfba57b42eb4faca1 Mon Sep 17 00:00:00 2001
From: Cliff Huang <cliff.huang@intel.com>
Date: Tue, 19 Nov 2024 14:57:43 -0800
Subject: [PATCH 0397/3886] drivers/intel/touch: Add Intel Touch Controller
 driver

This commit introduces a driver for the Intel Touch Controller (THC),
which supports HID-over-I2C and HID-over-SPI protocols, as well as
touch devices. The driver generates ACPI objects and publishes data
into the Secondary System Descriptor Table (SSDT) to facilitate
interaction with the touch hardware.

The driver implementation covers the following ACPI objects:
- _DSM (Device Specific Method)
- _CRS (Current Resource Settings)
- _STA (Power resource with Status), including _ON and _OFF methods
- _DSD (Device Specific Data) for THC-I2C
- _RST (Device Reset) for THC-SPI

Template device configuration for the following supported devices:
- Wacom: SPI touchscreen only
- Elan: both SPI and I2C touchscreen
- Hynitron: I2C touchpad only

It also includes template configurations for supported devices such as
Wacom (SPI touchscreen), Elan (SPI and I2C touchscreen), and Hynitron
(I2C touchpad). These configurations are divided into device-specific,
SoC-specific, and motherboard (MB)-specific details.

For SoC-specific configuration, the driver implements functions like
`soc_get_thc_hidi2c_info` and `soc_get_thc_hidspi_info`, which should
be defined in the SoC's `chip.c` file. Device-specific configurations
are provided by the driver for supported devices. For unsupported or
generic devices, the required information is expected to be provided
via the device tree. MB-specific information, such as LTR (Latency
Tolerance Reporting) values and speed, must be provided in the device
tree.

BUG=none
TEST=Configure the DRIVERS_INTEL_TOUCH option on a motherboard that has
the necessary touch configurations. Verify that the THC ACPI tables are
correctly generated in the SSDT.

Signed-off-by: Cliff Huang <cliff.huang@intel.com>
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Change-Id: Ibcd2a75a41460dee67aebdc61ee9e85fa98b71bf
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85198
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/drivers/intel/touch/Kconfig     |   7 +
 src/drivers/intel/touch/Makefile.mk |   3 +
 src/drivers/intel/touch/chip.h      | 256 ++++++++++++
 src/drivers/intel/touch/elan.h      |  32 ++
 src/drivers/intel/touch/hynitron.h  |  18 +
 src/drivers/intel/touch/touch.c     | 591 ++++++++++++++++++++++++++++
 src/drivers/intel/touch/wacom.h     |  21 +
 7 files changed, 928 insertions(+)
 create mode 100644 src/drivers/intel/touch/Kconfig
 create mode 100644 src/drivers/intel/touch/Makefile.mk
 create mode 100644 src/drivers/intel/touch/chip.h
 create mode 100644 src/drivers/intel/touch/elan.h
 create mode 100644 src/drivers/intel/touch/hynitron.h
 create mode 100644 src/drivers/intel/touch/touch.c
 create mode 100644 src/drivers/intel/touch/wacom.h

diff --git a/src/drivers/intel/touch/Kconfig b/src/drivers/intel/touch/Kconfig
new file mode 100644
index 0000000000..81bca4aa15
--- /dev/null
+++ b/src/drivers/intel/touch/Kconfig
@@ -0,0 +1,7 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
+config DRIVERS_INTEL_TOUCH
+	bool
+	help
+	  If selected, chip drivers/intel/touch publishes data into the SSDT (Secondary System
+	  Description Table) for both the touch controller and the sensor device.
diff --git a/src/drivers/intel/touch/Makefile.mk b/src/drivers/intel/touch/Makefile.mk
new file mode 100644
index 0000000000..c28092e238
--- /dev/null
+++ b/src/drivers/intel/touch/Makefile.mk
@@ -0,0 +1,3 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+ramstage-$(CONFIG_DRIVERS_INTEL_TOUCH) += touch.c
diff --git a/src/drivers/intel/touch/chip.h b/src/drivers/intel/touch/chip.h
new file mode 100644
index 0000000000..e0c78648ba
--- /dev/null
+++ b/src/drivers/intel/touch/chip.h
@@ -0,0 +1,256 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef __DRIVERS_INTEL_TOUCH_CHIP_H__
+#define __DRIVERS_INTEL_TOUCH_CHIP_H__
+
+#include <acpi/acpi_device.h>
+
+#define INTEL_THC0_NAME "THC0"
+#define INTEL_THC1_NAME "THC1"
+
+struct intel_thc_hidi2c_dev_info {
+	/* Device I2C address */
+	uint64_t addr;
+	/* Used in THC_HID_I2C mode */
+	uint32_t descriptor_address;
+};
+
+struct intel_thc_hidspi_dev_info {
+	/* Touch Host Controller HID Over SPI Input Report Header Address */
+	uint32_t input_report_header_address;
+
+	/* Touch Host Controller HID Over SPI Input Report Body Address */
+	uint32_t input_report_body_address;
+
+	/* Touch Host Controller HID Over SPI Output Report Address */
+	uint32_t output_report_address;
+
+	/* Touch Host Controller HID Over SPI Read Opcode */
+	uint32_t read_opcode;
+
+	/* Touch Host Controller HID Over SPI Write Opcode */
+	uint32_t write_opcode;
+
+};
+
+union intel_thc_dev_intf_info {
+	struct intel_thc_hidi2c_dev_info hidi2c;
+	struct intel_thc_hidspi_dev_info hidspi;
+};
+
+struct intel_thc_dev_info {
+	/* Device ACPI _HID */
+	const char *hid;
+	/* Device ACPI _CID */
+	const char *cid;
+	union intel_thc_dev_intf_info intf;
+};
+
+struct intel_thc_hidi2c_info {
+	/* Device connection speed in Hz */
+	uint64_t connection_speed;
+	/* Device address mode */
+	uint64_t addr_mode;
+	/* Standard Mode (100 kbit/s) Serial Clock Line HIGH Period */
+	/* NOTE: unit for period: # of reference clock count */
+	uint64_t sm_scl_high_period;
+	/* Standard Mode (100 kbit/s) Serial Clock Line LOW Period */
+	uint64_t sm_scl_low_period;
+	/* Standard Mode (100 kbit/s) Serial Data Line Transmit Hold Period */
+	uint64_t sm_sda_hold_tx_period;
+	/* Standard Mode (100 kbit/s) Serial Data Receive Hold Period */
+	uint64_t sm_sda_hold_rx_period;
+	/* Fast Mode (400 kbit/s) Serial Clock Line HIGH Period */
+	uint64_t fm_scl_high_period;
+	/* Fast Mode (400 kbit/s) Serial Clock Line LOW Period */
+	uint64_t fm_scl_low_period;
+	/* Fast Mode (400 kbit/s) Serial Data Line Transmit Hold Period */
+	uint64_t fm_sda_hold_tx_period;
+	/* Fast Mode (400 kbit/s) Serial Data Line Receive Hold Period */
+	uint64_t fm_sda_hold_rx_period;
+	/*
+	 * Maximum length (in ic_clk_cycles) of suppressed spikes in Std Mode, Fast Mode, and
+	 * Fast Mode Plus.
+	 */
+	uint64_t suppressed_spikes_s_f_fp;
+	/* Fast Mode Plus (1Mbit/sec) Serial Clock Line HIGH Period */
+	uint64_t fmp_scl_high_period;
+	/* Fast Mode Plus (1Mbit/sec) Serial Clock Line LOW Period */
+	uint64_t fmp_scl_low_period;
+	/* Fast Mode Plus (1Mbit/sec) Serial Data Line Transmit HOLD Period */
+	uint64_t fmp_sda_hold_tx_period;
+	/* Fast Mode Plus (1Mbit/sec) Serial Data Line Receive HOLD Period */
+	uint64_t fmp_sda_hold_rx_period;
+	/* High Speed Mode Plus (3.4Mbits/sec) Serial Clock Line HIGH Period */
+	uint64_t hm_scl_high_period;
+	/* High Speed Mode Plus (3.4Mbits/sec) Serial Clock Line LOW Period */
+	uint64_t hm_scl_low_period;
+	/* High Speed Mode Plus (3.4Mbits/sec) Serial Data Line Transmit HOLD Period */
+	uint64_t hm_sda_hold_tx_period;
+	/* High Speed Mode Plus (3.4Mbits/sec) Serial Data Line Receive HOLD Period */
+	uint64_t hm_sda_hold_rx_period;
+	/* Maximum length (in ic_clk_cycles) of suppressed spikes in High Speed Mode */
+	uint64_t suppressed_spikes_h_fp;
+};
+
+struct intel_thc_hidspi_info {
+	/*
+	 * Touch Host Controller HID Over SPI Connection Speed
+	 *
+	 * HID Over SPI Connection Speed - SPI Frequency
+	 */
+	uint32_t connection_speed;
+
+	/*
+	 * Touch Host Controller HID Over SPI Limit PacketSize
+	 *
+	 * When set, limits SPI read & write packet size to 64B. Otherwise, THC uses Max Soc
+	 * packet size for SPI Read and Write 0x0- Max Soc Packet Size, 0x11 - 64 Bytes
+	 */
+	uint32_t limit_packet_size;
+
+	/*
+	 * Touch Host Controller HID Over SPI Flags
+	 *
+	 * HID Over SPI Flags 0x0:Single SPI Mode, 0x4000:Dual SPI Mode, 0x8000:Quad SPI Mode
+	 *  Bit 0-12: Reserved
+	 *  Bit 13: SPI Write Mode.
+	 *    0b0 - Writes are carried in single SPI mode
+	 *    0b1 - Writes are carried out in Multi-SPI mode as specified by bit 14-15
+	 *  Bit 14-15: Multi-SPI Mode
+	 *    0b00 - Single SPI Mode
+	 *    0b01 - Dual SPI Mode
+	 *    0b10 - Quad SPI Mode
+	 *    0b11 - Reserved
+	 */
+	enum {
+		HIDSPI_WRITE_MODE_SINGLE = 0x0,
+		HIDSPI_WRITE_MODE_MULTI_SINGLE_SPI = 0x2000,
+		HIDSPI_WRITE_MODE_MULTI_DUAL_SPI = 0x6000,
+		HIDSPI_WRITE_MODE_MULTI_QUAD_SPI = 0xa000
+	} write_mode;
+
+	/* Touch Host Controller HID Over SPI ResetPad */
+	/* NOTE: This could be the same pad as reset_gpio */
+	struct acpi_gpio reset_gpio;
+	/* Delay to be inserted after device is taken out of reset */
+	unsigned int reset_delay_ms;
+	/* Delay to be inserted after device is put into reset */
+	unsigned int reset_off_delay_ms;
+
+	/*
+	 * Touch Host Controller HID Over SPI Limit PacketSize
+	 *
+	 * Minimum amount of delay the THC/QUICKSPI driver must wait between end of write
+	 * operation and begin of read operation. This value shall be in 10us multiples 0x0:
+	 * Disabled, 1-65535 (0xFFFF) - up to 655350 us
+	 */
+	uint32_t performance_limit;
+
+	/*
+	 * Touch Host Controller HID Over SPI Reset Sequencing Delay [ms]
+	 * Policy control for reset sequencing delay (ACPI _INI, _RST) default 300ms
+	 */
+	uint16_t reset_sequencing_delay;
+};
+
+enum intel_touch_device {
+	TH_SENSOR_NONE,
+	TH_SENSOR_WACOM,    /* BOM22 for SPI only */
+	TH_SENSOR_ELAN,     /* BOM36 for SPI and BOM37 for I2C */
+	TH_SENSOR_HYNITRON, /* NYITRON for I2C only  */
+	TH_SENSOR_GENERIC,  /* for device properity thru devicetree */
+	TH_SENSOR_MAX
+};
+
+/*
+ * Intel Touch Controller (THC) & sensor device
+ * Reference document: Meteor Lake UH type4 EDS vol1 640228
+ */
+struct drivers_intel_touch_config {
+	const char *name;
+	const char *desc;
+
+	/*
+	 * Touch Host Controller's (THC) 3 protocol modes:
+	 *     0x0: THC IPTS (not supported at this time)
+	 *     0x1: THC HID SPI (for MTL or later)
+	 *     0x2: THC HID I2C (for PTL or later)
+	 */
+	enum {
+		THC_IPTS_MODE,
+		THC_HID_SPI_MODE,
+		THC_HID_I2C_MODE,
+	} mode;
+
+	/* GPIO used to enable device. */
+	struct acpi_gpio enable_gpio;
+	/* Delay to be inserted after device is enabled. */
+	unsigned int enable_delay_ms;
+	/* Delay to be inserted after device is disabled. */
+	unsigned int enable_off_delay_ms;
+
+	/* GPIO used to take device out of reset or to put it into reset. */
+	struct acpi_gpio reset_gpio;
+	/* Delay to be inserted after device is taken out of reset. */
+	unsigned int reset_delay_ms;
+	/* Delay to be inserted after device is put into reset. */
+	unsigned int reset_off_delay_ms;
+
+	/* GPIO used for report enabling */
+	struct acpi_gpio report_gpio;
+	/* Delay to be inserted after device is taken out of reset. */
+	unsigned int report_delay_ms;
+	/* Delay to be inserted after device is put into reset. */
+	unsigned int report_off_delay_ms;
+
+	/*
+	 * Touch Host Controller Wake On Touch
+	 *
+	 * Based on this setting vGPIO for given THC will be in native mode, and additional _CRS
+	 * for wake will be exposed in ACPI
+	*/
+	uint8_t wake_on_touch;
+
+	/*
+	 * Either acpi_irq wake_irq or wake_gpio is needed for wake but not both use acpi_irq
+	 * for Interrupt() and wake_gpio for GpioInt().
+	 */
+	struct acpi_irq wake_irq;
+	struct acpi_gpio wake_gpio;
+	unsigned int wake_gpe; /* mapped GPE number for wake */
+	/* sensor-specific */
+	const char *sensor_dev_name;
+	const char *sensor_dev_desc;
+
+	enum intel_touch_device connected_device;
+
+	/*
+	 * Touch Host Controller HID Over SPI Limit PacketSize
+	 *
+	 * When set, limits SPI read & write packet size to 64B. Otherwise, THC uses Max Soc
+	 * packet size for SPI Read and Write 0x0- Max Soc Packet Size, 0x11 - 64 Bytes
+	 */
+	uint32_t limit_packet_size;
+
+	struct intel_thc_dev_info dev_hidi2c;
+	struct intel_thc_dev_info dev_hidspi;
+
+	struct intel_thc_hidspi_info soc_hidspi;
+	struct intel_thc_hidi2c_info soc_hidi2c;
+
+	/* Touch Host Controller Active Ltr */
+	uint32_t active_ltr;
+
+	/* Touch Host Controller Idle Ltr */
+	uint32_t idle_ltr;
+
+	/* Add `DmaProperty` in _DSD */
+	bool add_acpi_dma_property;
+};
+
+/* These functions are weak and need to be overridden by a SoC */
+const struct intel_thc_hidi2c_info *soc_get_thc_hidi2c_info(void);
+const struct intel_thc_hidspi_info *soc_get_thc_hidspi_info(void);
+
+#endif /* __DRIVERS_INTEL_TOUCH_CHIP_H__ */
diff --git a/src/drivers/intel/touch/elan.h b/src/drivers/intel/touch/elan.h
new file mode 100644
index 0000000000..b1f3ea615d
--- /dev/null
+++ b/src/drivers/intel/touch/elan.h
@@ -0,0 +1,32 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef __DRIVERS_TOUCH_DEV_ELAN_H__
+#define __DRIVERS_TOUCH_DEV_ELAN_H__
+
+#include "chip.h"
+
+/*
+ * BOM36 is used for HID-SPI interface, while BOM37A is used for HID-I2C
+ * interface.
+ */
+
+static const struct drivers_intel_touch_config elan_touch_config = {
+	.sensor_dev_name = "ELAN Touch Sensor Device",
+	.dev_hidi2c = {	/* BOM37A */
+		.hid				= "ELAN9048",
+		.cid				= "PNP0C50",
+		.intf.hidi2c.addr		= 0x16,
+		.intf.hidi2c.descriptor_address	= 0x1
+	},
+	.dev_hidspi = { /* BOM36 */
+		.hid						= "ELAN904A",
+		.cid						= "PNP0C51",
+		.intf.hidspi.input_report_header_address	= 0x1000,
+		.intf.hidspi.input_report_body_address		= 0x1100,
+		.intf.hidspi.output_report_address		= 0x2000,
+		.intf.hidspi.read_opcode			= 0xb,
+		.intf.hidspi.write_opcode			= 0x2,
+	},
+};
+
+#endif /* __DRIVERS_TOUCH_DEV_ELAN_H__ */
diff --git a/src/drivers/intel/touch/hynitron.h b/src/drivers/intel/touch/hynitron.h
new file mode 100644
index 0000000000..6e34d712f2
--- /dev/null
+++ b/src/drivers/intel/touch/hynitron.h
@@ -0,0 +1,18 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef __DRIVERS_TOUCH_DEV_HYNITRON_H__
+#define __DRIVERS_TOUCH_DEV_HYNITRON_H__
+
+#include "chip.h"
+
+static const struct drivers_intel_touch_config hynitron_touch_config = {
+	.sensor_dev_name = "Hynitron HFW68H Touch Pad Device",
+	.dev_hidi2c = {
+		.hid					= "HFW68H",
+		.cid					= "PNP0C50",
+		.intf.hidi2c.addr			= 0x2c,
+		.intf.hidi2c.descriptor_address		=  0x20
+	},
+};
+
+#endif /* __DRIVERS_TOUCH_DEV_HYNITRON_H__ */
diff --git a/src/drivers/intel/touch/touch.c b/src/drivers/intel/touch/touch.c
new file mode 100644
index 0000000000..02833124e6
--- /dev/null
+++ b/src/drivers/intel/touch/touch.c
@@ -0,0 +1,591 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <acpi/acpi_device.h>
+#include <acpi/acpigen.h>
+#include <acpi/acpigen_pci.h>
+#include <console/console.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+
+#include "chip.h"
+#include "elan.h"
+#include "hynitron.h"
+#include "wacom.h"
+
+/* _DSM Method UUIDs */
+#define TOUCH_HIDI2C_UUID		"3cdff6f7-4267-4555-ad05-b30a3d8938de"
+#define TOUCH_HID_UUID			"6e2ac436-0fcf-41af-a265-b32a220dcfab"
+#define TOUCH_INTF_UUID			"300d35b7-ac20-413e-8e9c-92e4dafd0afe"
+#define TOUCH_LTR_UUID			"84005682-5b71-41a4-8d66-8130f787a138"
+
+/* _DSD UUIDs */
+#define ACPI_DP_UUID			"daffd814-6eba-4d8c-8a91-bc9bbf4aa301"
+#define ACPI_DP_CHILD_UUID		"dbb8e3e6-5886-4ba6-8795-1319f52a966b"
+#define ACPI_DSD_DMA_PROPERTY_UUID	"70d24161-6dd5-4c9e-8070-705531292865"
+#define ACPI_DSD_DMA_PROPERTY_NAME	"DmaProperty"
+
+#define TOUCH_MUTEX			"THMX"
+
+static const struct intel_thc_hidi2c_info *_soc_hidi2c_info;
+static const struct intel_thc_hidspi_info *_soc_hidspi_info;
+
+__weak const struct intel_thc_hidi2c_info *soc_get_thc_hidi2c_info(void) { return NULL; }
+__weak const struct intel_thc_hidspi_info *soc_get_thc_hidspi_info(void) { return NULL; }
+
+/*
+ * This function returns a pointer to the correct drivers_intel_touch_config structure based on
+ * the device tree configuration and the connected device type.
+ */
+static const struct drivers_intel_touch_config *get_driver_config(const struct device *dev)
+
+{
+	const struct drivers_intel_touch_config none_driver_config;
+	const struct drivers_intel_touch_config *config = dev->chip_info;
+	const struct drivers_intel_touch_config *devices[TH_SENSOR_MAX] = {
+		[TH_SENSOR_NONE] = &none_driver_config,
+		[TH_SENSOR_WACOM] = &wacom_touch_config,
+		[TH_SENSOR_ELAN] = &elan_touch_config,
+		[TH_SENSOR_HYNITRON] = &hynitron_touch_config,
+		[TH_SENSOR_GENERIC] = config
+	};
+	return devices[config->connected_device];
+}
+
+/* Use only Device-tree definition. */
+#define touch_config_get(device, field)							\
+	(((const struct drivers_intel_touch_config *)(device)->chip_info)->field)
+
+/* Device-tree definition takes precedence over static drivers definition. */
+#define touch_get(device, field)							\
+	((((const struct drivers_intel_touch_config *)(device)->chip_info)->field) ?	\
+	 (((const struct drivers_intel_touch_config *)(device)->chip_info)->field) :	\
+	 get_driver_config(dev)->field)
+
+/* Device-tree definition takes precedence over static drivers SoC-specific definition. */
+#define touch_soc_get(device, intf, field)								\
+	((((const struct drivers_intel_touch_config *)(device)->chip_info)->soc_## intf .field) ?	\
+	 (((const struct drivers_intel_touch_config *)(device)->chip_info)->soc_## intf .field) :	\
+	 (_soc_## intf ##_info->field))
+
+static const char *touch_acpi_name(const struct device *dev)
+{
+	return touch_get(dev, name) ? : INTEL_THC0_NAME;
+}
+
+/*
+ * Functions prefixed with touch_acpigen_ are utilized within the Device Specific Method (DSM)
+ * ACPI code generation framework.
+ */
+
+#define touch_config_acpigen(field, fmt)					\
+	static void touch_acpigen_##field(void *arg)				\
+	{									\
+		const struct device *dev = (const struct device *)arg;		\
+		uint32_t value = touch_config_get(dev, field);			\
+		acpigen_write_debug_sprintf(fmt, touch_acpi_name(dev), value);	\
+		acpigen_write_return_integer(value);				\
+	}
+
+#define touch_dev_acpigen(field, interface, type, fmt)				\
+	static void touch_acpigen_## interface ## _ ## field(void *arg)		\
+	{									\
+		const struct device *dev = (const struct device *)arg;		\
+		uint32_t value = touch_get(dev, dev_##interface.intf.interface.field);		\
+		acpigen_write_debug_sprintf(fmt, touch_acpi_name(dev), value);	\
+		acpigen_write_return_ ## type(value);				\
+	}
+
+#define touch_soc_acpigen(field, intf, type, fmt)				\
+	static void touch_acpigen_## intf ## _ ## field(void *arg)		\
+	{									\
+		const struct device *dev = (const struct device *)arg;		\
+		uint32_t value = touch_soc_get(dev, intf, field);		\
+		acpigen_write_debug_sprintf(fmt, touch_acpi_name(dev), value);	\
+		acpigen_write_return_ ## type(value);				\
+	}
+
+touch_soc_acpigen(connection_speed, hidspi, integer, "%s: connection speed = %d\n");
+touch_soc_acpigen(limit_packet_size, hidspi, integer, "%s: limit packet size = %d\n");
+touch_soc_acpigen(performance_limit, hidspi, integer, "%s: performance limit = %d\n");
+
+static void (*touch_intf[])(void *) = {
+	NULL, /* Enumerate functions (auto-generated) */
+	touch_acpigen_hidspi_connection_speed,
+	touch_acpigen_hidspi_limit_packet_size,
+	touch_acpigen_hidspi_performance_limit
+};
+
+touch_config_acpigen(idle_ltr, "%s: Idle LTR = %d\n");
+touch_config_acpigen(active_ltr, "%s: Active LTR = %d\n");
+
+static void (*touch_ltr[])(void *) = {
+	NULL, /* Enumerate functions (auto-generated) */
+	touch_acpigen_active_ltr,
+	touch_acpigen_idle_ltr
+};
+
+touch_dev_acpigen(input_report_header_address, hidspi, integer,
+	"%s: HID SPI Input Report Header Address = %d\n");
+touch_dev_acpigen(input_report_body_address, hidspi, integer,
+	"%s: HID SPI Input Report Body Address = %d\n");
+touch_dev_acpigen(output_report_address, hidspi, integer,
+	"%s: HID SPI Output Report Address = %d\n");
+touch_dev_acpigen(read_opcode, hidspi, singleton_buffer, "%s: HID SPI Read Opcode = %d\n");
+touch_dev_acpigen(write_opcode, hidspi, singleton_buffer, "%s: HID SPI Write Opcode = %d\n");
+
+touch_soc_acpigen(write_mode, hidspi, integer, "%s: HID SPI Write Mode (flags) = 0x%x\n");
+
+static void (*touch_hidspi[])(void *) = {
+	NULL, /* Enumerate functions (auto-generated) */
+	touch_acpigen_hidspi_input_report_header_address,
+	touch_acpigen_hidspi_input_report_body_address,
+	touch_acpigen_hidspi_output_report_address,
+	touch_acpigen_hidspi_read_opcode,
+	touch_acpigen_hidspi_write_opcode,
+	touch_acpigen_hidspi_write_mode
+};
+
+touch_dev_acpigen(descriptor_address, hidi2c, integer,
+	"%s: HID I2C device descriptor address = 0x%x\n");
+
+static void (*touch_hidi2c[])(void *) = {
+	NULL, /* Enumerate functions (auto-generated) */
+	touch_acpigen_hidi2c_descriptor_address
+};
+
+static void touch_generate_acpi_dsm(const struct drivers_intel_touch_config *config,
+				    const struct device *dev)
+{
+	struct dsm_uuid spi_dsm_uuids[] = {
+		DSM_UUID(TOUCH_INTF_UUID, touch_intf, ARRAY_SIZE(touch_intf), (void *)dev),
+		DSM_UUID(TOUCH_LTR_UUID, touch_ltr, ARRAY_SIZE(touch_ltr), (void *)dev),
+		DSM_UUID(TOUCH_HID_UUID, touch_hidspi, ARRAY_SIZE(touch_hidspi), (void *)dev)
+	};
+	struct dsm_uuid i2c_dsm_uuids[] = {
+		DSM_UUID(TOUCH_LTR_UUID, touch_ltr, ARRAY_SIZE(touch_ltr), (void *)dev),
+		DSM_UUID(TOUCH_HIDI2C_UUID, touch_hidi2c, ARRAY_SIZE(touch_hidi2c), (void *)dev)
+	};
+
+	if (config->connected_device == TH_SENSOR_NONE || config->mode == THC_IPTS_MODE)
+		return;
+
+	if (config->mode == THC_HID_SPI_MODE)
+		acpigen_write_dsm_uuid_arr(spi_dsm_uuids, ARRAY_SIZE(spi_dsm_uuids));
+	else if (config->mode == THC_HID_I2C_MODE)
+		acpigen_write_dsm_uuid_arr(i2c_dsm_uuids, ARRAY_SIZE(i2c_dsm_uuids));
+}
+
+static void touch_generate_acpi_ini(const struct device *dev)
+{
+	acpigen_write_method_serialized("_INI", 0);
+	{
+		acpigen_write_debug_sprintf("%s: _INI()\n", touch_acpi_name(dev));
+	}
+	acpigen_write_method_end(); /* Method */
+}
+
+static void touch_generate_acpi_crs(const struct drivers_intel_touch_config *config,
+				    const struct device *dev)
+{
+	if (config->mode == THC_IPTS_MODE || !config->wake_on_touch)
+		return;
+
+	printk(BIOS_DEBUG, "%s Creating _CRS for HID SPI/I2C touch wake\n",
+	       touch_acpi_name(dev));
+	acpigen_write_name("_CRS");
+	acpigen_write_resourcetemplate_header();
+	if (config->wake_gpio.pin_count)
+		acpi_device_write_gpio(&config->wake_gpio);
+	else if (config->wake_irq.pin)
+		acpi_device_write_interrupt(&config->wake_irq);
+	acpigen_write_resourcetemplate_footer();
+
+	acpigen_write_name_integer("_S0W", ACPI_DEVICE_SLEEP_D3_HOT);
+	acpigen_write_PRW(config->wake_gpe, 3);
+}
+
+static void touch_generate_acpi_i2cdev_dsd(const struct device *dev)
+{
+	int dsd_pkg_cnt;
+
+	acpigen_write_name("ICRS");
+	acpigen_emit_byte(BUFFER_OP);
+	acpigen_write_len_f();
+	acpigen_write_integer(12);
+	acpigen_pop_len(); /* Name */
+	acpigen_write_create_buffer_word_field("ICRS", 0x00, "DADR");
+	acpigen_write_create_buffer_qword_field("ICRS", 0x02, "DSPD");
+	acpigen_write_create_buffer_byte_field("ICRS", 0x0a, "DADM");
+
+	acpigen_write_name("ISUB");
+	acpigen_emit_byte(BUFFER_OP);
+	acpigen_write_len_f();
+	acpigen_write_integer(145);
+	acpigen_pop_len();
+	acpigen_write_create_buffer_qword_field("ISUB", 0x00, "SMHX");
+	acpigen_write_create_buffer_qword_field("ISUB", 0x08, "SMLX");
+	acpigen_write_create_buffer_qword_field("ISUB", 0x10, "SMTD");
+	acpigen_write_create_buffer_qword_field("ISUB", 0x18, "SMRD");
+	acpigen_write_create_buffer_qword_field("ISUB", 0x20, "FMHX");
+	acpigen_write_create_buffer_qword_field("ISUB", 0x28, "FMLX");
+	acpigen_write_create_buffer_qword_field("ISUB", 0x30, "FMTD");
+	acpigen_write_create_buffer_qword_field("ISUB", 0x38, "FMRD");
+	acpigen_write_create_buffer_qword_field("ISUB", 0x40, "FMSL");
+	acpigen_write_create_buffer_qword_field("ISUB", 0x48, "FPHX");
+	acpigen_write_create_buffer_qword_field("ISUB", 0x50, "FPLX");
+	acpigen_write_create_buffer_qword_field("ISUB", 0x58, "FPTD");
+	acpigen_write_create_buffer_qword_field("ISUB", 0x60, "FPRD");
+	acpigen_write_create_buffer_qword_field("ISUB", 0x68, "HMHX");
+	acpigen_write_create_buffer_qword_field("ISUB", 0x70, "HMLX");
+	acpigen_write_create_buffer_qword_field("ISUB", 0x78, "HMTD");
+	acpigen_write_create_buffer_qword_field("ISUB", 0x80, "HMRD");
+	acpigen_write_create_buffer_qword_field("ISUB", 0x88, "HMSL");
+
+	acpigen_write_store_int_to_namestr(touch_get(dev, dev_hidi2c.intf.hidi2c.addr), "DADR");
+	acpigen_write_store_int_to_namestr(touch_soc_get(dev, hidi2c, connection_speed), "DSPD");
+	acpigen_write_store_int_to_namestr(touch_soc_get(dev, hidi2c, addr_mode), "DADM");
+	acpigen_write_store_int_to_namestr(touch_soc_get(dev, hidi2c, sm_scl_high_period), "SMHX");
+	acpigen_write_store_int_to_namestr(touch_soc_get(dev, hidi2c, sm_scl_low_period), "SMLX");
+	acpigen_write_store_int_to_namestr(touch_soc_get(dev, hidi2c, sm_sda_hold_tx_period), "SMTD");
+	acpigen_write_store_int_to_namestr(touch_soc_get(dev, hidi2c, sm_sda_hold_rx_period), "SMRD");
+	acpigen_write_store_int_to_namestr(touch_soc_get(dev, hidi2c, fm_scl_high_period), "FMHX");
+	acpigen_write_store_int_to_namestr(touch_soc_get(dev, hidi2c, fm_scl_low_period), "FMLX");
+	acpigen_write_store_int_to_namestr(touch_soc_get(dev, hidi2c, fm_sda_hold_tx_period), "FMTD");
+	acpigen_write_store_int_to_namestr(touch_soc_get(dev, hidi2c, fm_sda_hold_rx_period), "FMRD");
+	acpigen_write_store_int_to_namestr(touch_soc_get(dev, hidi2c, suppressed_spikes_s_f_fp), "FMSL");
+	acpigen_write_store_int_to_namestr(touch_soc_get(dev, hidi2c, fmp_scl_high_period), "FPHX");
+	acpigen_write_store_int_to_namestr(touch_soc_get(dev, hidi2c, fmp_scl_low_period), "FPLX");
+	acpigen_write_store_int_to_namestr(touch_soc_get(dev, hidi2c, fmp_sda_hold_tx_period), "FPTD");
+	acpigen_write_store_int_to_namestr(touch_soc_get(dev, hidi2c, fmp_sda_hold_rx_period), "FPRD");
+	acpigen_write_store_int_to_namestr(touch_soc_get(dev, hidi2c, hm_scl_high_period), "HMHX");
+	acpigen_write_store_int_to_namestr(touch_soc_get(dev, hidi2c, hm_scl_low_period), "HMLX");
+	acpigen_write_store_int_to_namestr(touch_soc_get(dev, hidi2c, hm_sda_hold_tx_period), "HMTD");
+	acpigen_write_store_int_to_namestr(touch_soc_get(dev, hidi2c, hm_sda_hold_rx_period), "HMRD");
+	acpigen_write_store_int_to_namestr(touch_soc_get(dev, hidi2c, suppressed_spikes_h_fp), "HMSL");
+
+	dsd_pkg_cnt = 4;
+	if (touch_get(dev, add_acpi_dma_property))
+		dsd_pkg_cnt += 2;
+
+	acpigen_write_name("_DSD");
+	acpigen_write_package(dsd_pkg_cnt);
+	{
+		acpigen_write_uuid(ACPI_DP_UUID);
+		acpigen_write_package(1);
+		{
+			acpigen_write_package(2);
+			{
+				acpigen_write_string("ICRS");
+				acpigen_emit_namestring("ICRS");
+			}
+			acpigen_pop_len();
+		}
+		acpigen_pop_len();
+		if (touch_get(dev, add_acpi_dma_property)) {
+			acpigen_write_uuid(ACPI_DSD_DMA_PROPERTY_UUID);
+			acpigen_write_package(1);
+			{
+				acpigen_write_package(2);
+				{
+					acpigen_write_string(ACPI_DSD_DMA_PROPERTY_NAME);
+					acpigen_write_integer(1);
+				}
+				acpigen_pop_len();
+			}
+			acpigen_pop_len();
+		}
+		acpigen_write_uuid(ACPI_DP_CHILD_UUID);
+		acpigen_write_package(1);
+		{
+			acpigen_write_package(2);
+			{
+				acpigen_write_string("ISUB");
+				acpigen_emit_namestring("ISUB");
+			}
+			acpigen_pop_len();
+		}
+		acpigen_pop_len();
+	}
+	acpigen_pop_len(); /* Name */
+}
+
+static void touch_generate_acpi_method_status(const struct drivers_intel_touch_config *config,
+					      const struct device *dev)
+{
+	const struct acpi_gpio *gpio;
+
+	acpigen_write_method("_STA", 0);
+	{
+		if (config->connected_device != TH_SENSOR_NONE) {
+			/* Use enable GPIO for status if provided, otherwise use reset GPIO. */
+			if (config->enable_gpio.pin_count) {
+				gpio = &config->enable_gpio;
+				/* Read current GPIO state into Local0. */
+				acpigen_get_tx_gpio(gpio);
+			} else {
+				gpio = &config->reset_gpio;
+				/* Read current GPIO state into Local0. */
+				acpigen_get_tx_gpio(gpio);
+				acpigen_write_not(LOCAL0_OP, LOCAL0_OP);
+			}
+			acpigen_write_return_op(LOCAL0_OP);
+		} else {
+			acpigen_write_integer(0);
+		}
+	}
+	acpigen_write_method_end(); /* Method */
+}
+
+static void touch_generate_acpi_method_on(const struct drivers_intel_touch_config *config,
+					  const struct device *dev)
+{
+	const struct device *parent_dev = dev->upstream->dev;
+	const char *mutex_path = acpi_device_path_join(parent_dev, TOUCH_MUTEX);
+
+	printk(BIOS_DEBUG, "%s: generating _ON() mutex = %s\n", touch_acpi_name(dev),
+		mutex_path);
+	acpigen_write_method_serialized("_ON", 0);
+	{
+		acpigen_write_debug_sprintf("%s: _ON()\n", touch_acpi_name(dev));
+		if (config->connected_device != TH_SENSOR_GENERIC) {
+			/* if wake is enabled, we don't manage power enabling and reset */
+			if (config->wake_on_touch) {
+				acpigen_write_debug_sprintf("%s: empty _ON() since wake is enabled.\n",
+					touch_acpi_name(dev));
+			} else {
+				acpigen_write_acquire(mutex_path, ACPI_MUTEX_NO_TIMEOUT);
+				acpigen_write_debug_sprintf("%s: _ON() mutex acquired.\n",
+					touch_acpi_name(dev));
+				/* ex: SOC_TCHSCR_RST_R_L */
+				if (config->reset_gpio.pin_count) {
+					acpigen_enable_tx_gpio(&config->reset_gpio);
+				}
+				/* ex: EN_TCHSCR_PWR */
+				if (config->enable_gpio.pin_count) {
+					acpigen_enable_tx_gpio(&config->enable_gpio);
+					if (config->enable_delay_ms)
+						acpigen_write_sleep(config->enable_delay_ms);
+				}
+				/* ex: SOC_TCHSCR_RST_R_L */
+				if (config->reset_gpio.pin_count) {
+					acpigen_disable_tx_gpio(&config->reset_gpio);
+					if (config->reset_delay_ms)
+						acpigen_write_sleep(config->reset_delay_ms);
+				}
+				/* ex: SOC_TCHSCR_RPT_EN */
+				if (config->report_gpio.pin_count) {
+					acpigen_enable_tx_gpio(&config->report_gpio);
+					if (config->report_delay_ms)
+						acpigen_write_sleep(config->report_delay_ms);
+				}
+				acpigen_write_release(mutex_path);
+			}
+		}
+		acpigen_write_debug_sprintf("%s: _ON() completed\n", touch_acpi_name(dev));
+	}
+	acpigen_write_method_end();
+}
+
+static void touch_generate_acpi_method_off(const struct drivers_intel_touch_config *config,
+					   const struct device *dev)
+{
+	const struct device *parent_dev = dev->upstream->dev;
+	const char *mutex_path = acpi_device_path_join(parent_dev, TOUCH_MUTEX);
+
+	acpigen_write_method_serialized("_OFF", 0);
+	{
+		acpigen_write_debug_sprintf("%s: _OFF()\n", touch_acpi_name(dev));
+		if (config->connected_device != TH_SENSOR_GENERIC) {
+			/* if wake is enabled, we don't manage power enabling and reset */
+			if (config->wake_on_touch) {
+				acpigen_write_debug_sprintf("%s: empty _OFF() since wake is enabled.\n",
+					touch_acpi_name(dev));
+			} else {
+				acpigen_write_acquire(mutex_path, ACPI_MUTEX_NO_TIMEOUT);
+				acpigen_write_debug_sprintf("%s: _OFF() mutex acquired.\n",
+					touch_acpi_name(dev));
+				/* ex: SOC_TCHSCR_RPT_EN */
+				if (config->report_gpio.pin_count) {
+					acpigen_disable_tx_gpio(&config->report_gpio);
+					if (config->report_off_delay_ms)
+						acpigen_write_sleep(config->report_off_delay_ms);
+				}
+				/* ex: SOC_TCHSCR_RST_R_L */
+				if (config->reset_gpio.pin_count) {
+					acpigen_enable_tx_gpio(&config->reset_gpio);
+					if (config->reset_off_delay_ms)
+						acpigen_write_sleep(config->reset_off_delay_ms);
+				}
+				/* ex: ==>  EN_TCHSCR_PWR */
+				if (config->enable_gpio.pin_count) {
+					acpigen_disable_tx_gpio(&config->enable_gpio);
+					if (config->enable_off_delay_ms)
+						acpigen_write_sleep(config->enable_off_delay_ms);
+				}
+				acpigen_write_release(mutex_path);
+			}
+		}
+		acpigen_write_debug_sprintf("%s: _OFF() completed\n", touch_acpi_name(dev));
+	}
+	acpigen_write_method_end();
+}
+
+static void touch_generate_acpi_spidev_rst(const struct drivers_intel_touch_config *config,
+					   const struct device *dev)
+{
+	acpigen_write_method_serialized("_RST", 0);
+	{
+		acpigen_write_debug_sprintf("%s: _RST()\n", touch_acpi_name(dev));
+		if (config->soc_hidspi.reset_gpio.pin_count) {
+			acpigen_write_acquire(TOUCH_MUTEX, ACPI_MUTEX_NO_TIMEOUT);
+			acpigen_write_debug_sprintf("%s: _RST() mutex acquired.\n",
+						    touch_acpi_name(dev));
+			/* Assert RESET# GPIO. */
+			acpigen_enable_tx_gpio(&config->soc_hidspi.reset_gpio);
+			/* Note: use 300 for debug */
+			acpigen_write_sleep(touch_soc_get(dev, hidspi, reset_sequencing_delay));
+			/* De-assert RESET# GPIO. */
+			acpigen_disable_tx_gpio(&config->soc_hidspi.reset_gpio);
+			acpigen_write_sleep(100); /* Note: use 100 for now */
+			acpigen_write_release(TOUCH_MUTEX);
+		} else
+			acpigen_write_debug_sprintf("%s: _RST() empty method\n",
+						    touch_acpi_name(dev));
+		acpigen_write_debug_sprintf("%s: _RST() completed\n", touch_acpi_name(dev));
+	}
+	acpigen_write_method_end(); /* Method */
+}
+
+static void touch_dev_fill_ssdt_generator(const struct device *dev)
+{
+	_soc_hidi2c_info = soc_get_thc_hidi2c_info();
+	_soc_hidspi_info = soc_get_thc_hidspi_info();
+
+	const struct drivers_intel_touch_config *config = dev->chip_info;
+	const struct device *parent = dev->upstream->dev;
+	DEVTREE_CONST struct device *domain = dev_find_path(NULL, DEVICE_PATH_DOMAIN);
+	const char *scope = acpi_device_path(parent);
+	const char *domain_scope = acpi_device_path(domain);
+
+	static const char *const power_res_states[] = {"_PR0", "_PR3"};
+
+	if (!config)
+		return;
+
+	if (!is_dev_enabled(parent)) {
+		printk(BIOS_ERR, "%s: touch controller is not enabled\n", __func__);
+		return;
+	}
+	if (!scope) {
+		printk(BIOS_ERR, "%s: touch controller scope not found\n", __func__);
+		return;
+	}
+	if (config->mode == THC_HID_I2C_MODE && !_soc_hidi2c_info) {
+		printk(BIOS_ERR, "%s: %s Missing THC SoC-specific config for HID-I2C.\n",
+			__func__, touch_acpi_name(dev));
+		return;
+	}
+	if (config->mode == THC_HID_SPI_MODE && !_soc_hidspi_info) {
+		printk(BIOS_ERR, "%s: %s Missing THC SoC-specific config for HID-SPI.\n",
+			__func__, touch_acpi_name(dev));
+		return;
+	}
+	printk(BIOS_DEBUG, "Fill touch ACPIs: domain scope=%s scope=%s touch dev=%s type=%d\n",
+	       domain_scope, scope, touch_acpi_name(dev), dev->path.type);
+
+	acpigen_write_scope(domain_scope);
+	{
+		acpigen_write_device(touch_acpi_name(dev));
+		{
+			acpigen_write_ADR_pci_device(parent);
+			acpigen_write_mutex(TOUCH_MUTEX, 0);
+
+			if (config->connected_device != TH_SENSOR_NONE)
+				touch_generate_acpi_crs(config, dev);
+			touch_generate_acpi_ini(dev);
+			touch_generate_acpi_dsm(config, dev);
+			/* When only THC1 is used, both THC0/1 need to be enabled since THC0's
+			 * device function is '0'. In this case, THC0 should set
+			 * connected_device to TH_SENSOR_NONE so that when the driver detects
+			 * THC0, the _DSM will be available for it to check and exit without
+			 * error.
+			 */
+			if (config->connected_device == TH_SENSOR_NONE)
+				return;
+
+			if (config->mode == THC_HID_I2C_MODE) {
+				touch_generate_acpi_i2cdev_dsd(dev);
+			} else {
+				/* Create _DSD with only DmaProperty */
+				if (touch_get(dev, add_acpi_dma_property))
+					acpi_device_add_dma_property(NULL);
+			}
+			if (config->enable_gpio.pin_count || config->reset_gpio.pin_count) {
+				printk(BIOS_DEBUG, "%s generating ACPI power resource.\n",
+				       touch_acpi_name(dev));
+				/* ACPI Power Resource for controlling the attached device
+				   power. */
+				acpigen_write_power_res("THPR", 0, 0, power_res_states,
+							ARRAY_SIZE(power_res_states));
+				{
+					touch_generate_acpi_method_status(config, dev);
+					touch_generate_acpi_method_on(config, dev);
+					touch_generate_acpi_method_off(config, dev);
+				}
+				acpigen_write_power_res_end(); /* PowerResource */
+			}
+			if (config->mode == THC_HID_SPI_MODE)
+				touch_generate_acpi_spidev_rst(config, dev);
+		}
+		acpigen_write_device_end(); /* Device */
+	}
+	acpigen_write_scope_end(); /* Scope */
+}
+
+static struct device_operations touch_dev_ops = {
+	.read_resources		= noop_read_resources,
+	.set_resources		= noop_set_resources,
+	.acpi_fill_ssdt		= touch_dev_fill_ssdt_generator,
+	.acpi_name		= touch_acpi_name
+};
+
+static void touch_dev_enable(struct device *dev)
+{
+	/* This dev is a generic device that is a child to the THC device */
+	dev->ops = &touch_dev_ops;
+}
+
+/* Copy of default_pci_ops_dev with scan_bus addition */
+static const struct device_operations pci_thc_device_ops = {
+	.read_resources		= pci_dev_read_resources,
+	.set_resources		= pci_dev_set_resources,
+	.enable_resources	= pci_dev_enable_resources,
+	.init			= pci_dev_init,
+	.scan_bus		= scan_generic_bus, /* Non-default */
+	.ops_pci		= &pci_dev_ops_pci
+};
+
+static const unsigned short pci_device_ids[] = {
+	PCI_DID_INTEL_MTL_THC0_SPI,
+	PCI_DID_INTEL_MTL_THC1_SPI,
+	PCI_DID_INTEL_PTL_U_H_THC0_I2C,
+	PCI_DID_INTEL_PTL_U_H_THC0_SPI,
+	PCI_DID_INTEL_PTL_U_H_THC1_I2C,
+	PCI_DID_INTEL_PTL_U_H_THC1_SPI,
+	PCI_DID_INTEL_PTL_H_THC0_I2C,
+	PCI_DID_INTEL_PTL_H_THC0_SPI,
+	PCI_DID_INTEL_PTL_H_THC1_I2C,
+	PCI_DID_INTEL_PTL_H_THC1_SPI,
+	0
+};
+
+static const struct pci_driver intel_touch_driver __pci_driver = {
+	.ops		= &pci_thc_device_ops,
+	.vendor		= PCI_VID_INTEL,
+	.devices	= pci_device_ids
+};
+
+struct chip_operations drivers_intel_touch_ops = {
+	.name		= "Intel Touch Controller & Sensor Device",
+	.enable_dev	= touch_dev_enable
+};
diff --git a/src/drivers/intel/touch/wacom.h b/src/drivers/intel/touch/wacom.h
new file mode 100644
index 0000000000..17aef0eba0
--- /dev/null
+++ b/src/drivers/intel/touch/wacom.h
@@ -0,0 +1,21 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef __DRIVERS_TOUCH_DEV_WACOM_H__
+#define __DRIVERS_TOUCH_DEV_WACOM_H__
+
+#include "chip.h"
+
+static const struct drivers_intel_touch_config wacom_touch_config = {
+	.sensor_dev_name = "Wacom Touch Sensor Device",
+	.dev_hidspi = {
+		.hid						= "WACOM530D",
+		.cid						= "PNP0C51",
+		.intf.hidspi.input_report_header_address	= 0x0,
+		.intf.hidspi.input_report_body_address		= 0x1000,
+		.intf.hidspi.output_report_address		= 0x1000,
+		.intf.hidspi.read_opcode			= 0xb,
+		.intf.hidspi.write_opcode			= 0x2
+	},
+};
+
+#endif /* __DRIVERS_TOUCH_DEV_WACOM_H__ */

From 49a547365697d00a305f08a00bb7c116e5a67ccc Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Tue, 11 Mar 2025 10:47:50 -0500
Subject: [PATCH 0398/3886] soc/intel/alderlake/acpi: Fix scope of IOM ACPI
 device

Since the IOM region is outside of the PCH MMIO address space, Windows
will report a device error for the IOM since the ACPI scope
is under PCI0, but the assigned resource range is not inside an
address range for any of PCI0's resources.

Correct this by setting the scope of the IOM device to just _SB.

TEST=build/boot Win11 on google/banshee, verify USB-C ports functional
and coolstar's IOM/TCSS drivers loaded without error.

Change-Id: I7e61341dd9b7548a079a1ce3b88025f6391f3203
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86818
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
---
 src/soc/intel/alderlake/acpi/tcss.asl | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/src/soc/intel/alderlake/acpi/tcss.asl b/src/soc/intel/alderlake/acpi/tcss.asl
index 2d09c6438a..8dfa8750c0 100644
--- a/src/soc/intel/alderlake/acpi/tcss.asl
+++ b/src/soc/intel/alderlake/acpi/tcss.asl
@@ -321,7 +321,7 @@ Scope (_GPE)
 	}
 }
 
-Scope (\_SB.PCI0)
+Scope (\_SB)
 {
 	Device (IOM)
 	{
@@ -334,7 +334,10 @@ Scope (\_SB.PCI0)
 		/* ACPI_STATUS_DEVICE_HIDDEN_ON */
 		Name (_STA, 0xB)
 	}
+}
 
+Scope (\_SB.PCI0)
+{
 	/*
 	 * Operation region defined to access the TCSS_DEVEN. Get the MCHBAR in offset
 	 * 0x48 in B0:D0:F0. TCSS device enable base address is in offset 0x7090 of MCHBAR.

From a98514188b265a79318db9b72b0fd047e3e393aa Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Tue, 11 Mar 2025 10:52:13 -0500
Subject: [PATCH 0399/3886] soc/intel/tigerlake/acpi: Fix scope of IOM ACPI
 device

Since the IOM region is outside of the PCH MMIO address space, Windows
will report a device error for the IOM since the ACPI scope
is under PCI0, but the assigned resource range is not inside an
address range for any of PCI0's resources.

Correct this by setting the scope of the IOM device to just _SB.

TEST=build/boot Win11 on google/drobit, verify USB-C ports functional
and coolstar's IOM/TCSS drivers loaded without error.

Change-Id: Ia089e723ccac5508cfaffc0204815b80bb209dd0
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86819
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/soc/intel/tigerlake/acpi/tcss.asl | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/src/soc/intel/tigerlake/acpi/tcss.asl b/src/soc/intel/tigerlake/acpi/tcss.asl
index f02a4a37b7..2a7e674973 100644
--- a/src/soc/intel/tigerlake/acpi/tcss.asl
+++ b/src/soc/intel/tigerlake/acpi/tcss.asl
@@ -321,7 +321,7 @@ Scope (_GPE)
 	}
 }
 
-Scope (\_SB.PCI0)
+Scope (\_SB)
 {
 	Device (IOM)
 	{
@@ -334,7 +334,10 @@ Scope (\_SB.PCI0)
 		/* ACPI_STATUS_DEVICE_HIDDEN_ON */
 		Name (_STA, 0xB)
 	}
+}
 
+Scope (\_SB.PCI0)
+{
 	/*
 	 * Operation region defined to access the TCSS_DEVEN. Get the MCHBAR in offset
 	 * 0x48 in B0:D0:F0. TCSS device enable base address is in offset 0x7090 of MCHBAR.

From 55f4f86f0c9635559a17ab8d624d40ac7976544f Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Mon, 10 Mar 2025 19:04:09 -0500
Subject: [PATCH 0400/3886] soc/intel/cmn/blk/acpi: Add ASL stubs for HECI and
 SRAM devices
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

These can be used by most/all client SoCs

Change-Id: I6622fa34f014bbe9fdd95a996332dfe5a07a92fb
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86802
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
---
 src/soc/intel/common/block/acpi/acpi/heci.asl | 7 +++++++
 src/soc/intel/common/block/acpi/acpi/sram.asl | 7 +++++++
 2 files changed, 14 insertions(+)
 create mode 100644 src/soc/intel/common/block/acpi/acpi/heci.asl
 create mode 100644 src/soc/intel/common/block/acpi/acpi/sram.asl

diff --git a/src/soc/intel/common/block/acpi/acpi/heci.asl b/src/soc/intel/common/block/acpi/acpi/heci.asl
new file mode 100644
index 0000000000..9b7f2d0118
--- /dev/null
+++ b/src/soc/intel/common/block/acpi/acpi/heci.asl
@@ -0,0 +1,7 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+/* CSE/HECI interface - Device 16, Function 0 */
+Device (HECI)
+{
+	Name (_ADR, 0x00160000)
+}
diff --git a/src/soc/intel/common/block/acpi/acpi/sram.asl b/src/soc/intel/common/block/acpi/acpi/sram.asl
new file mode 100644
index 0000000000..ec306f4f55
--- /dev/null
+++ b/src/soc/intel/common/block/acpi/acpi/sram.asl
@@ -0,0 +1,7 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+/* PMC Shared SRAM - Device 14, Function 2 */
+Device (SRAM)
+{
+	Name (_ADR, 0x00140002)
+}

From 8daa9eed866d9c0853b3bc927612681da83a8ef1 Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Fri, 7 Mar 2025 18:17:13 -0600
Subject: [PATCH 0401/3886] soc/intel/meteorlake: Add missing ACPI device path
 name
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

The ACPI device path name handler for the fast SPI device is missing,
so add it to ensure that the names is returned from  acpi_device_path()
calls.

TEST=Build/boot Win11 on screebo

Change-Id: Ibf5ab3bf6694875c357b999fe871a5b16f89ec62
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86796
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
---
 src/soc/intel/meteorlake/chip.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/src/soc/intel/meteorlake/chip.c b/src/soc/intel/meteorlake/chip.c
index a0a13997cb..79ef178dcc 100644
--- a/src/soc/intel/meteorlake/chip.c
+++ b/src/soc/intel/meteorlake/chip.c
@@ -116,6 +116,7 @@ const char *soc_acpi_name(const struct device *dev)
 	case PCI_DEVFN_HDA:	return "HDAS";
 	case PCI_DEVFN_SMBUS:	return "SBUS";
 	case PCI_DEVFN_GBE:	return "GLAN";
+	case PCI_DEVFN_SPI:	return "FSPI";
 	}
 	printk(BIOS_DEBUG, "Missing ACPI Name for PCI: 00:%02x.%01x\n",
 			PCI_SLOT(dev->path.pci.devfn), PCI_FUNC(dev->path.pci.devfn));

From e22ff257d6bbcfe7497e705bc21c146bdddab4a9 Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Fri, 7 Mar 2025 18:18:53 -0600
Subject: [PATCH 0402/3886] soc/intel/mtl/acpi: add entries for HEC1 and SRAM
 to DSDT
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

HEC1 and SRAM are defined in src/soc/intel/meteorlake/chipset.cb:

device pci 16.0 alias heci1 on  end
device pci 14.2 alias pmc_shared_sram off end

Add entries for these devices in DSDT to prevent "AE_NOT_FOUND" errors
in the kernel dmesg log, and add entries to soc_acpi_name() to ensure
that these names are returned during acpi_device_path() calls.

TEST=Build/boot Linux 6.x on screebo to confirm errors are not seen.

Change-Id: Id79054d2cb56daae238ac562b7b6c204926cdced
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86797
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
---
 src/soc/intel/meteorlake/acpi/southbridge.asl | 6 ++++++
 src/soc/intel/meteorlake/chip.c               | 2 ++
 2 files changed, 8 insertions(+)

diff --git a/src/soc/intel/meteorlake/acpi/southbridge.asl b/src/soc/intel/meteorlake/acpi/southbridge.asl
index 5e8042e5b2..b205aff568 100644
--- a/src/soc/intel/meteorlake/acpi/southbridge.asl
+++ b/src/soc/intel/meteorlake/acpi/southbridge.asl
@@ -43,6 +43,12 @@
 /* USB XHCI 0:14.0 */
 #include "xhci.asl"
 
+/* PMC Shared SRAM 0:14.2 */
+#include <soc/intel/common/block/acpi/acpi/sram.asl>
+
+/* CSE/HECI #1 0:16.0 */
+#include <soc/intel/common/block/acpi/acpi/heci.asl>
+
 /* PCI _OSC */
 #include <soc/intel/common/acpi/pci_osc.asl>
 
diff --git a/src/soc/intel/meteorlake/chip.c b/src/soc/intel/meteorlake/chip.c
index 79ef178dcc..a44a9b36cf 100644
--- a/src/soc/intel/meteorlake/chip.c
+++ b/src/soc/intel/meteorlake/chip.c
@@ -116,7 +116,9 @@ const char *soc_acpi_name(const struct device *dev)
 	case PCI_DEVFN_HDA:	return "HDAS";
 	case PCI_DEVFN_SMBUS:	return "SBUS";
 	case PCI_DEVFN_GBE:	return "GLAN";
+	case PCI_DEVFN_SRAM:	return "SRAM";
 	case PCI_DEVFN_SPI:	return "FSPI";
+	case PCI_DEVFN_CSE:	return "HECI";
 	}
 	printk(BIOS_DEBUG, "Missing ACPI Name for PCI: 00:%02x.%01x\n",
 			PCI_SLOT(dev->path.pci.devfn), PCI_FUNC(dev->path.pci.devfn));

From 0586e0eb0fbc68a68df413b286f961aee5be845d Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Tue, 11 Mar 2025 09:57:22 -0500
Subject: [PATCH 0403/3886] soc/intel/alderlake: Use common ACPI code for SRAM
 and HECI

Use the newly-created ACPI devices in common/acpi, and adjust the
SoC ACPI name for the CSE/HECI device to match.

Change-Id: Iabd9dec2f6838c1dc4b1cad924ceb62c992f89c0
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86813
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
---
 src/soc/intel/alderlake/acpi/pcie.asl        | 10 ----------
 src/soc/intel/alderlake/acpi/southbridge.asl |  6 ++++++
 src/soc/intel/alderlake/chip.c               |  2 +-
 3 files changed, 7 insertions(+), 11 deletions(-)

diff --git a/src/soc/intel/alderlake/acpi/pcie.asl b/src/soc/intel/alderlake/acpi/pcie.asl
index 50d9464169..607a861717 100644
--- a/src/soc/intel/alderlake/acpi/pcie.asl
+++ b/src/soc/intel/alderlake/acpi/pcie.asl
@@ -357,13 +357,3 @@ Device (PEG2)
 	}
 }
 #endif
-
-Device (SRAM)
-{
-	Name (_ADR, 0x00140002)
-}
-
-Device (HEC1)
-{
-	Name (_ADR, 0x00160000)
-}
diff --git a/src/soc/intel/alderlake/acpi/southbridge.asl b/src/soc/intel/alderlake/acpi/southbridge.asl
index 651d26c4ef..6de08fc13b 100644
--- a/src/soc/intel/alderlake/acpi/southbridge.asl
+++ b/src/soc/intel/alderlake/acpi/southbridge.asl
@@ -42,6 +42,12 @@
 /* USB XHCI 0:14.0 */
 #include "xhci.asl"
 
+/* PMC Shared SRAM 0:14.2 */
+#include <soc/intel/common/block/acpi/acpi/sram.asl>
+
+/* CSE/HECI #1 0:16.0 */
+#include <soc/intel/common/block/acpi/acpi/heci.asl>
+
 /* PCI _OSC */
 #include <soc/intel/common/acpi/pci_osc.asl>
 
diff --git a/src/soc/intel/alderlake/chip.c b/src/soc/intel/alderlake/chip.c
index 0256de4f82..418c6ff7be 100644
--- a/src/soc/intel/alderlake/chip.c
+++ b/src/soc/intel/alderlake/chip.c
@@ -153,7 +153,7 @@ const char *soc_acpi_name(const struct device *dev)
 	case PCH_DEVFN_GBE:		return "GLAN";
 	case PCH_DEVFN_SRAM:		return "SRAM";
 	case PCH_DEVFN_SPI:		return "FSPI";
-	case PCH_DEVFN_CSE:		return "HEC1";
+	case PCH_DEVFN_CSE:		return "HECI";
 #if CONFIG(SOC_INTEL_ALDERLAKE_PCH_N)
 	case PCH_DEVFN_EMMC:		return "EMMC";
 #endif

From 95829131c7b00cda1e340d860b8623414417f6ab Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Tue, 11 Mar 2025 10:07:10 -0500
Subject: [PATCH 0404/3886] soc/intel/pantherlake: Use common ACPI code for
 SRAM and HECI
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Use the newly-created ACPI devices in common/acpi, to align with other
client SoCs.

Change-Id: Icc5da0b820101b3c651ed59a47aeab37440a6996
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86816
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
---
 src/soc/intel/pantherlake/acpi/southbridge.asl | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/src/soc/intel/pantherlake/acpi/southbridge.asl b/src/soc/intel/pantherlake/acpi/southbridge.asl
index a6cdda3076..20e23122fb 100644
--- a/src/soc/intel/pantherlake/acpi/southbridge.asl
+++ b/src/soc/intel/pantherlake/acpi/southbridge.asl
@@ -41,6 +41,12 @@
 /* USB XHCI 0:14.0 */
 #include "xhci.asl"
 
+/* PMC Shared SRAM 0:14.2 */
+#include <soc/intel/common/block/acpi/acpi/sram.asl>
+
+/* CSE/HECI #1 0:16.0 */
+#include <soc/intel/common/block/acpi/acpi/heci.asl>
+
 /* PCI _OSC */
 #include <soc/intel/common/acpi/pci_osc.asl>
 

From 19deb5e5f8c7c3ac139dfb9f3f1eef6df0fe9b04 Mon Sep 17 00:00:00 2001
From: Lawrence <lawrence.chang@intel.corp-partner.google.com>
Date: Mon, 10 Mar 2025 16:53:21 +0800
Subject: [PATCH 0405/3886] src/soc/intel/adl: Add EnableTcssCovTypeA and
 MappingPchXhciUsbA
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Add EnableTcssCovTypeA and MappingPchXhciUsbA to repurpose the
integrated USB Type-C subsystem (TCSS) ports to USB3.2 Gen2x1 Type-A.
For example, to enable port 1 to be configured as USB Type-A, add the
following code in overridetree.cb:
register "enabletcsscovtypea[1]" = "true"
register "mappingpchxhciusba[1]" = "2"
AP log:
[SPEW ]  EnableTcssCovTypeA[0]= 0x00000000
[SPEW ]  MappingPchXhciUsbA[0]= 0x00000000
[SPEW ]  EnableTcssCovTypeA[1]= 0x00000001
[SPEW ]  MappingPchXhciUsbA[1]= 0x00000002
Reference document:
742076_ADL_TypeA_Repurpose_TCSS_Ports_USB3p2_Gen2x1_TWP_Rev1p2.pdf

BUG=b:400809281
TEST=Able to build and boot google/Riven

Change-Id: I3684fdf23706cec86c6da2b409aa4fbb33f4ec2e
Signed-off-by: Lawrence <lawrence.chang@intel.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86781
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/soc/intel/alderlake/chip.h       | 9 +++++++++
 src/soc/intel/alderlake/fsp_params.c | 7 +++++++
 2 files changed, 16 insertions(+)

diff --git a/src/soc/intel/alderlake/chip.h b/src/soc/intel/alderlake/chip.h
index 040b3d131d..5b1dabb1a0 100644
--- a/src/soc/intel/alderlake/chip.h
+++ b/src/soc/intel/alderlake/chip.h
@@ -799,6 +799,15 @@ struct soc_intel_alderlake_config {
 		PD_TIER_PREMIUM = 25000,
 		PD_TIER_VOLUME  = 27000
 	} vccin_aux_imon_iccmax;
+
+	/* Enable / Disable(default) Type C Port x Convert to TypeA */
+	bool enabletcsscovtypea[4];
+
+	/*
+	 * PCH xhci port x for Type C Port x mapping.
+	 * Input PCH xhci port x for Type C Port 0 mapping.
+	 */
+	uint8_t mappingpchxhciusba[4];
 };
 
 typedef struct soc_intel_alderlake_config config_t;
diff --git a/src/soc/intel/alderlake/fsp_params.c b/src/soc/intel/alderlake/fsp_params.c
index d9204b4097..0de9fe4f66 100644
--- a/src/soc/intel/alderlake/fsp_params.c
+++ b/src/soc/intel/alderlake/fsp_params.c
@@ -650,6 +650,13 @@ static void fill_fsps_tcss_params(FSP_S_CONFIG *s_cfg,
 			s_cfg->UsbTcPortEn |= BIT(i);
 	}
 
+	for (int i = 0; i < MAX_TYPE_C_PORTS; i++) {
+		if (config->enabletcsscovtypea[i]) {
+			s_cfg->EnableTcssCovTypeA[i] = config->enabletcsscovtypea[i];
+			s_cfg->MappingPchXhciUsbA[i] = config->mappingpchxhciusba[i];
+		}
+	}
+
 	s_cfg->Usb4CmMode = CONFIG(SOFTWARE_CONNECTION_MANAGER);
 }
 

From f3e78b076de43021f96ee06f7d91b125032313a2 Mon Sep 17 00:00:00 2001
From: melongmelong <knw0507@naver.com>
Date: Sat, 11 Jan 2025 16:17:56 +0900
Subject: [PATCH 0406/3886] Makefile: Add ctags target in Makefile

Add 'ctags' target.
we can see that 'make help' says
...
  ctags / ctags-project ...
...
but, Makefile have only 'ctags-project' target.

Change-Id: Ie554892bcb072d773babf745d7756630327d2975
Signed-off-by: melongmelong <knw0507@naver.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85936
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 Makefile | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/Makefile b/Makefile
index 5e45e16300..49c19cbc39 100644
--- a/Makefile
+++ b/Makefile
@@ -486,6 +486,9 @@ ctags-project: clean-ctags $(obj)/project_filelist.txt
 	cat $(obj)/project_filelist.txt | \
 	  xargs ctags -o tags
 
+ctags:
+	ctags -R
+
 cscope-project: clean-cscope $(obj)/project_filelist.txt
 	cat $(obj)/project_filelist.txt | xargs cscope -b
 

From 92d77dd2e385c9b347f3901ff62f619562738f66 Mon Sep 17 00:00:00 2001
From: Elyes Haouas <ehaouas@noos.fr>
Date: Sun, 12 May 2024 17:39:48 +0200
Subject: [PATCH 0407/3886] spd_bin.h: Deduplicate SPD definitions

Use already defined macros in `spd.h`, ddr3.h`and `ddr4.h`.

TEST=Built google/cyan (Cyan) with BUILD_TIMELESS=1, no change in output
ROM.

Change-Id: I727aa38236ad97f9c529389fdb7d7d11c1db08d0
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82314
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/include/spd_bin.h                       | 20 ------
 src/lib/spd_bin.c                           | 71 ++++++++++-----------
 src/lib/spd_cache.c                         | 11 ++--
 src/mainboard/google/cyan/spd/spd.c         | 13 ++--
 src/soc/intel/common/block/smbus/smbuslib.c | 33 +++++-----
 5 files changed, 67 insertions(+), 81 deletions(-)

diff --git a/src/include/spd_bin.h b/src/include/spd_bin.h
index 434d674755..bf72b2d122 100644
--- a/src/include/spd_bin.h
+++ b/src/include/spd_bin.h
@@ -3,24 +3,11 @@
 #ifndef SPD_BIN_H
 #define SPD_BIN_H
 
-#include <device/dram/ddr3.h>
 #include <stdint.h>
 #include <commonlib/region.h>
 
-#define SPD_PAGE_LEN		256
-#define SPD_PAGE_LEN_DDR4	512
 #define SPD_PAGE_0		(0x6C >> 1)
 #define SPD_PAGE_1		(0x6E >> 1)
-#define SPD_DRAM_TYPE		2
-#define  SPD_DRAM_DDR3		0x0B
-#define  SPD_DRAM_LPDDR3_INTEL	0xF1
-#define  SPD_DRAM_LPDDR3_JEDEC	0x0F
-#define  SPD_DRAM_DDR4		0x0C
-#define  SPD_DRAM_LPDDR4	0x10
-#define  SPD_DRAM_LPDDR4X	0x11
-#define  SPD_DRAM_DDR5		0x12
-#define  SPD_DRAM_LPDDR5	0x13
-#define  SPD_DRAM_LPDDR5X	0x15
 #define SPD_DENSITY_BANKS	4
 #define SPD_ADDRESSING		5
 #define SPD_SN_LEN		4
@@ -28,13 +15,6 @@
 #define DDR3_BUS_DEV_WIDTH	8
 #define DDR4_ORGANIZATION	12
 #define DDR4_BUS_DEV_WIDTH	13
-#define DDR3_SPD_PART_OFF	SPD_DDR3_PART_NUM
-#define DDR3_SPD_PART_LEN	SPD_DDR3_PART_LEN
-#define DDR3_SPD_SN_OFF		122
-#define LPDDR3_SPD_PART_OFF	SPD_DDR3_PART_NUM
-#define LPDDR3_SPD_PART_LEN	SPD_DDR3_PART_LEN
-#define DDR4_SPD_PART_OFF	329
-#define DDR4_SPD_PART_LEN	20
 #define DDR4_SPD_SN_OFF		325
 
 struct spd_block {
diff --git a/src/lib/spd_bin.c b/src/lib/spd_bin.c
index 01f451da65..e3108cbcfd 100644
--- a/src/lib/spd_bin.c
+++ b/src/lib/spd_bin.c
@@ -2,10 +2,12 @@
 
 #include <cbfs.h>
 #include <console/console.h>
+#include <device/dram/ddr3.h>
+#include <device/dram/ddr4.h>
 #include <memory_info.h>
+#include <spd.h>
 #include <spd_bin.h>
 #include <string.h>
-#include <device/dram/ddr3.h>
 
 void dump_spd_info(struct spd_block *blk)
 {
@@ -27,17 +29,17 @@ const char * __weak mainboard_get_dram_part_num(void)
 static bool use_ddr4_params(int dram_type)
 {
 	switch (dram_type) {
-	case SPD_DRAM_DDR3:
-	case SPD_DRAM_LPDDR3_INTEL:
+	case SPD_MEMORY_TYPE_SDRAM_DDR3:
+	case SPD_MEMORY_TYPE_LPDDR3_INTEL:
 		return false;
 	/* Below DDR type share the same attributes */
-	case SPD_DRAM_LPDDR3_JEDEC:
-	case SPD_DRAM_DDR4:
-	case SPD_DRAM_DDR5:
-	case SPD_DRAM_LPDDR5:
-	case SPD_DRAM_LPDDR5X:
-	case SPD_DRAM_LPDDR4:
-	case SPD_DRAM_LPDDR4X:
+	case SPD_MEMORY_TYPE_LPDDR3_SDRAM:
+	case SPD_MEMORY_TYPE_DDR4_SDRAM:
+	case SPD_MEMORY_TYPE_DDR5_SDRAM:
+	case SPD_MEMORY_TYPE_LPDDR5_SDRAM:
+	case SPD_MEMORY_TYPE_LPDDR5X_SDRAM:
+	case SPD_MEMORY_TYPE_LPDDR4_SDRAM:
+	case SPD_MEMORY_TYPE_LPDDR4X_SDRAM:
 		return true;
 	default:
 		printk(BIOS_NOTICE, "Defaulting to using DDR4 params. Please add dram_type check for %d to %s\n",
@@ -49,22 +51,22 @@ static bool use_ddr4_params(int dram_type)
 static const char *spd_get_module_type_string(int dram_type)
 {
 	switch (dram_type) {
-	case SPD_DRAM_DDR3:
+	case SPD_MEMORY_TYPE_SDRAM_DDR3:
 		return "DDR3";
-	case SPD_DRAM_LPDDR3_INTEL:
-	case SPD_DRAM_LPDDR3_JEDEC:
+	case SPD_MEMORY_TYPE_LPDDR3_INTEL:
+	case SPD_MEMORY_TYPE_LPDDR3_SDRAM:
 		return "LPDDR3";
-	case SPD_DRAM_DDR4:
+	case SPD_MEMORY_TYPE_DDR4_SDRAM:
 		return "DDR4";
-	case SPD_DRAM_LPDDR4:
+	case SPD_MEMORY_TYPE_LPDDR4_SDRAM:
 		return "LPDDR4";
-	case SPD_DRAM_LPDDR4X:
+	case SPD_MEMORY_TYPE_LPDDR4X_SDRAM:
 		return "LPDDR4X";
-	case SPD_DRAM_DDR5:
+	case SPD_MEMORY_TYPE_DDR5_SDRAM:
 		return "DDR5";
-	case SPD_DRAM_LPDDR5:
+	case SPD_MEMORY_TYPE_LPDDR5_SDRAM:
 		return "LPDDR5";
-	case SPD_DRAM_LPDDR5X:
+	case SPD_MEMORY_TYPE_LPDDR5X_SDRAM:
 		return "LPDDR5X";
 	}
 	return "UNKNOWN";
@@ -157,24 +159,21 @@ static void spd_get_name(const uint8_t spd[], int type, const char **spd_name, s
 	}
 
 	switch (type) {
-	case SPD_DRAM_DDR3:
-		*spd_name = (const char *) &spd[DDR3_SPD_PART_OFF];
-		*len = DDR3_SPD_PART_LEN;
-		break;
-	case SPD_DRAM_LPDDR3_INTEL:
-		*spd_name = (const char *) &spd[LPDDR3_SPD_PART_OFF];
-		*len = LPDDR3_SPD_PART_LEN;
+	case SPD_MEMORY_TYPE_SDRAM_DDR3:
+	case SPD_MEMORY_TYPE_LPDDR3_INTEL:
+		*spd_name = (const char *) &spd[SPD_DDR3_PART_NUM];
+		*len = SPD_DDR3_PART_LEN;
 		break;
 	/* LPDDR3, LPDDR4 and DDR4 have same part number offset and length */
-	case SPD_DRAM_LPDDR3_JEDEC:
-	case SPD_DRAM_DDR4:
-	case SPD_DRAM_DDR5:
-	case SPD_DRAM_LPDDR5:
-	case SPD_DRAM_LPDDR4:
-	case SPD_DRAM_LPDDR4X:
-		if (spd[DDR4_SPD_PART_OFF]) {
-			*spd_name = (const char *) &spd[DDR4_SPD_PART_OFF];
-			*len = DDR4_SPD_PART_LEN;
+	case SPD_MEMORY_TYPE_LPDDR3_SDRAM:
+	case SPD_MEMORY_TYPE_DDR4_SDRAM:
+	case SPD_MEMORY_TYPE_DDR5_SDRAM:
+	case SPD_MEMORY_TYPE_LPDDR5_SDRAM:
+	case SPD_MEMORY_TYPE_LPDDR4_SDRAM:
+	case SPD_MEMORY_TYPE_LPDDR4X_SDRAM:
+		if (spd[SPD_DDR4_PART_OFF]) {
+			*spd_name = (const char *) &spd[SPD_DDR4_PART_OFF];
+			*len = SPD_DDR4_PART_LEN;
 		}
 		break;
 	default:
@@ -187,7 +186,7 @@ void print_spd_info(uint8_t spd[])
 {
 	const char *nameptr = NULL;
 	size_t len;
-	int type  = spd[SPD_DRAM_TYPE];
+	int type  = spd[SPD_MEMORY_TYPE];
 	int banks = spd_get_banks(spd, type);
 	int capmb = spd_get_capmb(spd);
 	int rows  = spd_get_rows(spd);
diff --git a/src/lib/spd_cache.c b/src/lib/spd_cache.c
index dff6ede860..9a84906bc3 100644
--- a/src/lib/spd_cache.c
+++ b/src/lib/spd_cache.c
@@ -3,8 +3,11 @@
 #include <assert.h>
 #include <console/console.h>
 #include <crc_byte.h>
+#include <device/dram/ddr3.h>
+#include <device/dram/ddr4.h>
 #include <fmap.h>
 #include <spd_cache.h>
+#include <spd.h>
 #include <spd_bin.h>
 #include <string.h>
 
@@ -207,12 +210,12 @@ enum cb_err spd_fill_from_cache(uint8_t *spd_cache, struct spd_block *blk)
 		return CB_ERR;
 	}
 
-	dram_type = *(spd_cache + SC_SPD_OFFSET(i) + SPD_DRAM_TYPE);
+	dram_type = *(spd_cache + SC_SPD_OFFSET(i) + SPD_MEMORY_TYPE);
 
-	if (dram_type == SPD_DRAM_DDR4)
-		blk->len = SPD_PAGE_LEN_DDR4;
+	if (dram_type == SPD_MEMORY_TYPE_DDR4_SDRAM)
+		blk->len = SPD_SIZE_MAX_DDR4;
 	else
-		blk->len = SPD_PAGE_LEN;
+		blk->len = SPD_SIZE_MAX_DDR3;
 
 	for (i = 0; i < SC_SPD_NUMS; i++)
 		if (get_cached_dimm_present(spd_cache, i))
diff --git a/src/mainboard/google/cyan/spd/spd.c b/src/mainboard/google/cyan/spd/spd.c
index bd08b8257c..edd10bdf21 100644
--- a/src/mainboard/google/cyan/spd/spd.c
+++ b/src/mainboard/google/cyan/spd/spd.c
@@ -3,6 +3,7 @@
 #include <cbfs.h>
 #include <cbmem.h>
 #include <console/console.h>
+#include <device/dram/ddr3.h>
 #include <gpio.h>
 #include <lib.h>
 #include <memory_info.h>
@@ -38,9 +39,9 @@ static void *get_spd_pointer(int *dual)
 	if (!spd_file)
 		die("SPD data not found.");
 
-	if (spd_file_len < SPD_PAGE_LEN)
+	if (spd_file_len < SPD_SIZE_MAX_DDR3)
 		die("Missing SPD data.");
-	total_spds = spd_file_len / SPD_PAGE_LEN;
+	total_spds = spd_file_len / SPD_SIZE_MAX_DDR3;
 
 	ram_id = get_ramid();
 	printk(BIOS_DEBUG, "ram_id=%d, total_spds: %d\n", ram_id, total_spds);
@@ -51,7 +52,7 @@ static void *get_spd_pointer(int *dual)
 		return NULL;
 	}
 	/* Return the serial product data for the RAM */
-	return &spd_file[SPD_PAGE_LEN * spd_index];
+	return &spd_file[SPD_SIZE_MAX_DDR3 * spd_index];
 }
 
 /* Copy SPD data for on-board memory */
@@ -67,7 +68,7 @@ void spd_memory_init_params(MEMORY_INIT_UPD *memory_params)
 	spd_content = get_spd_pointer(&dual_channel);
 	if (CONFIG(DISPLAY_SPD_DATA) && spd_content != NULL) {
 		printk(BIOS_DEBUG, "SPD Data:\n");
-		hexdump(spd_content, SPD_PAGE_LEN);
+		hexdump(spd_content, SPD_SIZE_MAX_DDR3);
 		printk(BIOS_DEBUG, "\n");
 	}
 
@@ -135,8 +136,8 @@ static void set_dimm_info(const uint8_t *spd, struct dimm_info *dimm)
 	dimm->dimm_size = capmb / 8 * busw / devw * ranks;  /* MiB */
 	dimm->mod_type = spd[3] & 0xf;
 	strncpy((char *)&dimm->module_part_number[0], (char *)&spd[0x80],
-		LPDDR3_SPD_PART_LEN);
-	dimm->module_part_number[LPDDR3_SPD_PART_LEN] = 0;
+		SPD_DDR3_PART_LEN);
+	dimm->module_part_number[SPD_DDR3_PART_LEN] = 0;
 	dimm->mod_id = *(uint16_t *)&spd[0x94];
 
 	switch (busw) {
diff --git a/src/soc/intel/common/block/smbus/smbuslib.c b/src/soc/intel/common/block/smbus/smbuslib.c
index cf60e64c1d..2bf33f4370 100644
--- a/src/soc/intel/common/block/smbus/smbuslib.c
+++ b/src/soc/intel/common/block/smbus/smbuslib.c
@@ -1,6 +1,9 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
 #include <console/console.h>
+#include <device/dram/ddr3.h>
+#include <device/dram/ddr4.h>
+#include <spd.h>
 #include <spd_bin.h>
 #include <device/smbus_def.h>
 #include <device/smbus_host.h>
@@ -11,13 +14,13 @@ static void update_spd_len(struct spd_block *blk)
 	u8 i, j = 0;
 	for (i = 0 ; i < CONFIG_DIMM_MAX; i++)
 		if (blk->spd_array[i] != NULL)
-			j |= blk->spd_array[i][SPD_DRAM_TYPE];
+			j |= blk->spd_array[i][SPD_MEMORY_TYPE];
 
 	/* If spd used is DDR4, then its length is 512 byte. */
-	if (j == SPD_DRAM_DDR4)
-		blk->len = SPD_PAGE_LEN_DDR4;
+	if (j == SPD_MEMORY_TYPE_DDR4_SDRAM)
+		blk->len = SPD_SIZE_MAX_DDR4;
 	else
-		blk->len = SPD_PAGE_LEN;
+		blk->len = SPD_SIZE_MAX_DDR3;
 }
 
 static void spd_read(u8 *spd, u8 addr)
@@ -28,7 +31,7 @@ static void spd_read(u8 *spd, u8 addr)
 	if (CONFIG(SPD_READ_BY_WORD))
 		step = sizeof(uint16_t);
 
-	for (i = 0; i < SPD_PAGE_LEN; i += step) {
+	for (i = 0; i < SPD_SIZE_MAX_DDR3; i += step) {
 		if (CONFIG(SPD_READ_BY_WORD))
 			((u16*)spd)[i / sizeof(uint16_t)] =
 				 spd_read_word(addr, i);
@@ -40,7 +43,7 @@ static void spd_read(u8 *spd, u8 addr)
 /* return -1 if SMBus errors otherwise return 0 */
 static int get_spd(u8 *spd, u8 addr)
 {
-	if (CONFIG_DIMM_SPD_SIZE > SPD_PAGE_LEN) {
+	if (CONFIG_DIMM_SPD_SIZE > SPD_SIZE_MAX_DDR3) {
 		/* Restore to page 0 before reading */
 		spd_write_byte(SPD_PAGE_0, 0, 0);
 	}
@@ -54,21 +57,21 @@ static int get_spd(u8 *spd, u8 addr)
 
 	/* IMC doesn't support i2c eeprom read. */
 	if (CONFIG(SOC_INTEL_COMMON_BLOCK_IMC) ||
-	    i2c_eeprom_read(addr, 0, SPD_PAGE_LEN, spd) < 0) {
+	    i2c_eeprom_read(addr, 0, SPD_SIZE_MAX_DDR3, spd) < 0) {
 		printk(BIOS_INFO, "do_i2c_eeprom_read failed, using fallback\n");
 		spd_read(spd, addr);
 	}
 
 	/* Check if module is DDR4, DDR4 spd is 512 byte. */
-	if (spd[SPD_DRAM_TYPE] == SPD_DRAM_DDR4 && CONFIG_DIMM_SPD_SIZE > SPD_PAGE_LEN) {
+	if (spd[SPD_MEMORY_TYPE] == SPD_MEMORY_TYPE_DDR4_SDRAM && CONFIG_DIMM_SPD_SIZE > SPD_SIZE_MAX_DDR3) {
 		/* Switch to page 1 */
 		spd_write_byte(SPD_PAGE_1, 0, 0);
 
 		/* IMC doesn't support i2c eeprom read. */
 		if (CONFIG(SOC_INTEL_COMMON_BLOCK_IMC) ||
-		    i2c_eeprom_read(addr, 0, SPD_PAGE_LEN, spd + SPD_PAGE_LEN) < 0) {
+		    i2c_eeprom_read(addr, 0, SPD_SIZE_MAX_DDR3, spd + SPD_SIZE_MAX_DDR3) < 0) {
 			printk(BIOS_INFO, "do_i2c_eeprom_read failed, using fallback\n");
-			spd_read(spd + SPD_PAGE_LEN, addr);
+			spd_read(spd + SPD_SIZE_MAX_DDR3, addr);
 		}
 		/* Restore to page 0 */
 		spd_write_byte(SPD_PAGE_0, 0, 0);
@@ -114,13 +117,13 @@ enum cb_err get_spd_sn(u8 addr, u32 *sn)
 	if (addr == 0x0)
 		return CB_ERR;
 
-	if (CONFIG_DIMM_SPD_SIZE > SPD_PAGE_LEN) {
+	if (CONFIG_DIMM_SPD_SIZE > SPD_SIZE_MAX_DDR3) {
 		/* Restore to page 0 before reading */
 		spd_write_byte(SPD_PAGE_0, 0, 0);
 	}
 
 	/* If dimm is not present, set sn to 0xff. */
-	smbus_ret = spd_read_byte(addr, SPD_DRAM_TYPE);
+	smbus_ret = spd_read_byte(addr, SPD_MEMORY_TYPE);
 	if (smbus_ret < 0) {
 		printk(BIOS_INFO, "No memory dimm at address %02X\n", addr << 1);
 		*sn = 0xffffffff;
@@ -130,7 +133,7 @@ enum cb_err get_spd_sn(u8 addr, u32 *sn)
 	dram_type = smbus_ret & 0xff;
 
 	/* Check if module is DDR4, DDR4 spd is 512 byte. */
-	if (dram_type == SPD_DRAM_DDR4 && CONFIG_DIMM_SPD_SIZE > SPD_PAGE_LEN) {
+	if (dram_type == SPD_MEMORY_TYPE_DDR4_SDRAM && CONFIG_DIMM_SPD_SIZE > SPD_SIZE_MAX_DDR3) {
 		/* Switch to page 1 */
 		spd_write_byte(SPD_PAGE_1, 0, 0);
 
@@ -140,10 +143,10 @@ enum cb_err get_spd_sn(u8 addr, u32 *sn)
 
 		/* Restore to page 0 */
 		spd_write_byte(SPD_PAGE_0, 0, 0);
-	} else if (dram_type == SPD_DRAM_DDR3) {
+	} else if (dram_type == SPD_MEMORY_TYPE_SDRAM_DDR3) {
 		for (i = 0; i < SPD_SN_LEN; i++)
 			*((u8 *)sn + i) = spd_read_byte(addr,
-							i + DDR3_SPD_SN_OFF);
+							i + SPD_DDR3_SERIAL_NUM);
 	} else {
 		printk(BIOS_ERR, "Unsupported dram_type\n");
 		return CB_ERR;

From 3dd72a36e89df730abccb6a2ee9d53eddc34c1ce Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Sat, 8 Mar 2025 09:24:26 -0600
Subject: [PATCH 0408/3886] soc/intel/{adl,mtl,ptl,tgl}: Make IOM ACPI device
 visibility configurable

Coolstar's Windows drivers require the IOM device to be visible to the
OS, so add a Kconfig to control this, which mainboards will select in
subsequent patches.

TEST=build/boot Win11 on rex/screebo, verify USB4 drivers functional.

Change-Id: I00ef9703179d87b7b476ef18d8d02fcafa9e14ab
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86792
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
---
 src/soc/intel/alderlake/acpi/tcss.asl   |  5 +++++
 src/soc/intel/common/block/usb4/Kconfig | 10 ++++++++++
 src/soc/intel/meteorlake/acpi/tcss.asl  |  7 ++++++-
 src/soc/intel/pantherlake/acpi/tcss.asl |  7 ++++++-
 src/soc/intel/tigerlake/acpi/tcss.asl   |  5 +++++
 5 files changed, 32 insertions(+), 2 deletions(-)

diff --git a/src/soc/intel/alderlake/acpi/tcss.asl b/src/soc/intel/alderlake/acpi/tcss.asl
index 8dfa8750c0..b8b9fa4175 100644
--- a/src/soc/intel/alderlake/acpi/tcss.asl
+++ b/src/soc/intel/alderlake/acpi/tcss.asl
@@ -331,8 +331,13 @@ Scope (\_SB)
 		Name (_CRS, ResourceTemplate () {
 			Memory32Fixed (ReadWrite, IOM_BASE_ADDRESS, IOM_BASE_SIZE)
 		})
+#if CONFIG(IOM_ACPI_DEVICE_VISIBLE)
+		/* ACPI_STATUS_DEVICE_ALL_ON */
+		Name (_STA, 0xF)
+#else
 		/* ACPI_STATUS_DEVICE_HIDDEN_ON */
 		Name (_STA, 0xB)
+#endif
 	}
 }
 
diff --git a/src/soc/intel/common/block/usb4/Kconfig b/src/soc/intel/common/block/usb4/Kconfig
index 1ae570c2bf..557f199cc1 100644
--- a/src/soc/intel/common/block/usb4/Kconfig
+++ b/src/soc/intel/common/block/usb4/Kconfig
@@ -58,3 +58,13 @@ config SOFTWARE_CONNECTION_MANAGER
 	help
 	  Enable SCM so it's used instead of FCM.
 endchoice
+
+config IOM_ACPI_DEVICE_VISIBLE
+	bool
+	depends on SOC_INTEL_COMMON_BLOCK_USB4
+	default n
+	help
+	  Select this config if the mainboard needs the IOM ACPI device
+	  visible to the OS. This is needed for ChromeOS devices for
+	  which ChromeEC acts as the TCPC, otherwise should be left
+	  unselected.
diff --git a/src/soc/intel/meteorlake/acpi/tcss.asl b/src/soc/intel/meteorlake/acpi/tcss.asl
index 24d28f3b63..b765f0c738 100644
--- a/src/soc/intel/meteorlake/acpi/tcss.asl
+++ b/src/soc/intel/meteorlake/acpi/tcss.asl
@@ -334,8 +334,13 @@ Scope (\_SB.PCI0)
 				IOM_BASE_ADDR, IOM_BASE_ADDR_MAX, 0x0,
 				IOM_BASE_SIZE,,,)
 		})
-		/* Hide the device so that Windows does not complain on missing driver */
+#if CONFIG(IOM_ACPI_DEVICE_VISIBLE)
+		/* ACPI_STATUS_DEVICE_ALL_ON */
+		Name (_STA, 0xF)
+#else
+		/* ACPI_STATUS_DEVICE_HIDDEN_ON */
 		Name (_STA, 0xB)
+#endif
 	}
 
 	/*
diff --git a/src/soc/intel/pantherlake/acpi/tcss.asl b/src/soc/intel/pantherlake/acpi/tcss.asl
index 1743b1e454..a89d26fb25 100644
--- a/src/soc/intel/pantherlake/acpi/tcss.asl
+++ b/src/soc/intel/pantherlake/acpi/tcss.asl
@@ -334,8 +334,13 @@ Scope (\_SB.PCI0)
 				IOM_BASE_ADDR, IOM_BASE_ADDR_MAX, 0x0,
 				IOM_BASE_SIZE,,,)
 		})
-		/* Hide the device so that Windows does not complain on missing driver */
+#if CONFIG(IOM_ACPI_DEVICE_VISIBLE)
+		/* ACPI_STATUS_DEVICE_ALL_ON */
+		Name (_STA, 0xF)
+#else
+		/* ACPI_STATUS_DEVICE_HIDDEN_ON */
 		Name (_STA, 0xB)
+#endif
 	}
 
 	/*
diff --git a/src/soc/intel/tigerlake/acpi/tcss.asl b/src/soc/intel/tigerlake/acpi/tcss.asl
index 2a7e674973..d01cf250aa 100644
--- a/src/soc/intel/tigerlake/acpi/tcss.asl
+++ b/src/soc/intel/tigerlake/acpi/tcss.asl
@@ -331,8 +331,13 @@ Scope (\_SB)
 		Name (_CRS, ResourceTemplate () {
 			Memory32Fixed (ReadWrite, IOM_BASE_ADDRESS, IOM_BASE_SIZE)
 		})
+#if CONFIG(IOM_ACPI_DEVICE_VISIBLE)
+		/* ACPI_STATUS_DEVICE_ALL_ON */
+		Name (_STA, 0xF)
+#else
 		/* ACPI_STATUS_DEVICE_HIDDEN_ON */
 		Name (_STA, 0xB)
+#endif
 	}
 }
 

From 7708a9470961fd312b097b4a16b9c7b773d46652 Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Tue, 11 Mar 2025 11:50:11 -0500
Subject: [PATCH 0409/3886] mb/google/brya: Select IOM_ACPI_DEVICE_VISIBLE

Needed for coolstar's IOM/TCSS drivers under Windows.

TEST=build/boot Win11 on google/banshee

Change-Id: I682362290fa90274d06a6541211f5a22e8115503
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86821
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/google/brya/Kconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/src/mainboard/google/brya/Kconfig b/src/mainboard/google/brya/Kconfig
index 91d77ab2b9..6dc6bb4697 100644
--- a/src/mainboard/google/brya/Kconfig
+++ b/src/mainboard/google/brya/Kconfig
@@ -31,6 +31,7 @@ config BOARD_GOOGLE_BRYA_COMMON
 	select HAVE_ACPI_TABLES
 	select I2C_TPM
 	select INTEL_LPSS_UART_FOR_CONSOLE
+	select IOM_ACPI_DEVICE_VISIBLE
 	select MAINBOARD_HAS_CHROMEOS
 	select MAINBOARD_HAS_TPM2
 	select PMC_IPC_ACPI_INTERFACE

From cfad6abdc62234e1d37faa13a4a8214650adc756 Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Tue, 11 Mar 2025 11:55:36 -0500
Subject: [PATCH 0410/3886] mb/google/volteer: Select IOM_ACPI_DEVICE_VISIBLE

Needed for coolstar's IOM/TCSS drivers under Windows.

TEST=build/boot Win11 on google/drobit

Change-Id: I136ced08f977289a41ba424d5379984d4bf6038c
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86823
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
---
 src/mainboard/google/volteer/Kconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/src/mainboard/google/volteer/Kconfig b/src/mainboard/google/volteer/Kconfig
index bc5ee6c10e..15a8ece8f9 100644
--- a/src/mainboard/google/volteer/Kconfig
+++ b/src/mainboard/google/volteer/Kconfig
@@ -33,6 +33,7 @@ config BOARD_GOOGLE_BASEBOARD_VOLTEER
 	select HAVE_SPD_IN_CBFS
 	select I2C_TPM if BOARD_GOOGLE_VOLTEER2_TI50
 	select INTEL_LPSS_UART_FOR_CONSOLE
+	select IOM_ACPI_DEVICE_VISIBLE
 	select MAINBOARD_HAS_CHROMEOS
 	select MAINBOARD_HAS_TPM2
 	select SOC_INTEL_COMMON_BLOCK_TCSS

From cab1670728f3f747e1a28a1f0eb3af34de7c7d2c Mon Sep 17 00:00:00 2001
From: Martin Roth <gaumless@gmail.com>
Date: Mon, 10 Mar 2025 15:04:47 -0600
Subject: [PATCH 0411/3886] Docs: Add 25.03 release notes template

Change-Id: I513f58c15f7fa34658d6571a6f55852c60331b81
Signed-off-by: Martin Roth <gaumless@gmail.com>
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86800
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nicholas Chin <nic.c3.14@gmail.com>
---
 .../releases/coreboot-25.03-relnotes.md       | 96 +++++++++++++++++++
 Documentation/releases/index.md               |  3 +-
 2 files changed, 98 insertions(+), 1 deletion(-)
 create mode 100644 Documentation/releases/coreboot-25.03-relnotes.md

diff --git a/Documentation/releases/coreboot-25.03-relnotes.md b/Documentation/releases/coreboot-25.03-relnotes.md
new file mode 100644
index 0000000000..4b579fe084
--- /dev/null
+++ b/Documentation/releases/coreboot-25.03-relnotes.md
@@ -0,0 +1,96 @@
+Upcoming release - coreboot 25.03
+========================================================================
+
+The 25.03 release is scheduled for the end of March, 2025
+
+
+Update this document with changes that should be in the release notes.
+
+* Please use Markdown.
+* See the past few release notes for the general format.
+* The chip and board additions and removals will be updated right
+  before the release, so those do not need to be added.
+* Note that all changes before the release are done are marked upcoming.
+  A final version of the notes are done after the release.
+
+
+
+Significant or interesting changes
+----------------------------------
+
+* Add changes that need a full description here
+
+* This section should have full descriptions and can or should have
+  a link to the referenced commits.
+
+
+
+Additional coreboot changes
+---------------------------
+
+The following are changes across a number of patches, or changes worth
+noting, but not needing a full description.
+
+* Changes that only need a line or two of description go here.
+
+
+
+Changes to external resources
+-----------------------------
+
+### Toolchain updates
+
+
+
+### Git submodule pointers
+
+
+### External payloads
+
+
+
+Platform Updates
+----------------
+
+### Added mainboards:
+* To be filled in immediately before the release by the release team
+
+
+### Removed Mainboards
+* To be filled in immediately before the release by the release team
+
+
+### Updated SoCs
+* To be filled in immediately before the release by the release team
+
+
+
+Plans to move platform support to a branch
+------------------------------------------
+* To be filled in immediately before the release by the release team
+
+
+
+Statistics from the 24.12 to the 25.03 release
+--------------------------------------------
+* To be filled in immediately before the release by the release team
+
+
+
+Significant Known and Open Issues
+---------------------------------
+
+Issues from the coreboot bugtracker: <https://ticket.coreboot.org/>
+* To be filled in immediately before the release by the release team
+
+
+
+coreboot Links and Contact Information
+--------------------------------------
+
+* Main Web site: <https://www.coreboot.org>
+* Downloads: <https://coreboot.org/downloads.html>
+* Source control: <https://review.coreboot.org>
+* Documentation: <https://doc.coreboot.org>
+* Issue tracker: <https://ticket.coreboot.org/projects/coreboot>
+* Donations: <https://coreboot.org/donate.html>
diff --git a/Documentation/releases/index.md b/Documentation/releases/index.md
index 29ba2d4684..0fe44e0f6d 100644
--- a/Documentation/releases/index.md
+++ b/Documentation/releases/index.md
@@ -6,7 +6,7 @@ Please add to the release notes as changes are added:
 ```{toctree}
 :maxdepth: 1
 
-24.12 - December 2024 <coreboot-24.12-relnotes.md>
+25.03  - March 2025 <coreboot-25.03-relnotes.md>
 ```
 
 The [checklist] contains instructions to ensure that a release covers all
@@ -22,6 +22,7 @@ important is taken care of.
 ```{toctree}
 :maxdepth: 1
 
+24.12  - December 2024 <coreboot-24.12-relnotes.md>
 24.08  - August 2024 <coreboot-24.08-relnotes.md>
 24.05  - May 2024 <coreboot-24.05-relnotes.md>
 24.02  - February 2024 <coreboot-24.02-relnotes.md>

From 89cdd8d4919b043369eab34e36174b3f9259ee8c Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Micha=C5=82=20Kope=C4=87?= <michal.kopec@3mdeb.com>
Date: Sun, 20 Oct 2024 18:10:14 +0200
Subject: [PATCH 0412/3886] mb/lenovo/m900_tiny: disable CLKREQ for SSD and
 Wi-Fi slots
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

It's been observed that at least on some M700 Tiny boards, CLKREQ
signals aren't wired as per the schematic. Disable them and configure
their pads as per original Lenovo UEFI.

This change fixes Wi-Fi card detection on M700 Tiny.

TEST=Boot M700 Tiny with AX200 card in Wi-Fi card slot and boot to
Windows 10. Check that Wi-Fi works correctly.

Change-Id: I5b26937cd4a6937b516304fefad9186b9e1cdc76
Signed-off-by: Michał Kopeć <michal.kopec@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84813
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/lenovo/m900_tiny/devicetree.cb | 4 ----
 src/mainboard/lenovo/m900_tiny/gpio.c        | 4 ++--
 2 files changed, 2 insertions(+), 6 deletions(-)

diff --git a/src/mainboard/lenovo/m900_tiny/devicetree.cb b/src/mainboard/lenovo/m900_tiny/devicetree.cb
index c2ac2ba780..88245c3c1d 100644
--- a/src/mainboard/lenovo/m900_tiny/devicetree.cb
+++ b/src/mainboard/lenovo/m900_tiny/devicetree.cb
@@ -162,8 +162,6 @@ chip soc/intel/skylake
 		end
 		device ref pcie_rp17 on # M.2 2280 / 2242 - SSD
 			register "PcieRpEnable[16]"			= "1"
-			register "PcieRpClkReqSupport[16]"		= "1"
-			register "PcieRpClkReqNumber[16]"		= "1"
 			register "PcieRpAdvancedErrorReporting[16]"	= "1"
 			register "PcieRpLtrEnable[16]"			= "true"
 			register "PcieRpClkSrcNumber[16]"		= "7"
@@ -171,8 +169,6 @@ chip soc/intel/skylake
 		end
 		device ref pcie_rp7 on # M.2 2230 - WLAN
 			register "PcieRpEnable[6]"			= "1"
-			register "PcieRpClkReqSupport[6]"		= "1"
-			register "PcieRpClkReqNumber[6]"		= "11"
 			register "PcieRpAdvancedErrorReporting[6]"	= "1"
 			register "PcieRpLtrEnable[6]"			= "true"
 			register "PcieRpClkSrcNumber[6]"		= "1"
diff --git a/src/mainboard/lenovo/m900_tiny/gpio.c b/src/mainboard/lenovo/m900_tiny/gpio.c
index aecea414a2..4c4bac4b8e 100644
--- a/src/mainboard/lenovo/m900_tiny/gpio.c
+++ b/src/mainboard/lenovo/m900_tiny/gpio.c
@@ -42,7 +42,7 @@ static const struct pad_config gpio_table[] = {
 	PAD_CFG_GPI_TRIG_OWN(GPP_B3, NONE, PLTRST, OFF, ACPI),
 	PAD_CFG_GPI_TRIG_OWN(GPP_B4, NONE, PLTRST, OFF, ACPI),
 	PAD_NC(GPP_B5, NONE),
-	PAD_CFG_NF(GPP_B6, NONE, DEEP, NF1),
+	PAD_CFG_GPI_TRIG_OWN(GPP_B6, NONE, PLTRST, OFF, ACPI),
 	PAD_NC(GPP_B7, NONE),
 	PAD_NC(GPP_B8, NONE),
 	PAD_NC(GPP_B9, NONE),
@@ -192,7 +192,7 @@ static const struct pad_config gpio_table[] = {
 	PAD_NC(GPP_H2, NONE),
 	PAD_NC(GPP_H3, NONE),
 	PAD_CFG_GPI_TRIG_OWN(GPP_H4, NONE, PLTRST, OFF, ACPI),
-	PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1),
+	PAD_NC(GPP_H5, NONE),
 	PAD_CFG_GPI_TRIG_OWN(GPP_H6, NONE, PLTRST, OFF, ACPI),
 	PAD_NC(GPP_H7, NONE),
 	PAD_NC(GPP_H8, NONE),

From 9a4c6710abd7f66bcd8efc3dbc85dae8483c85a4 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Micha=C5=82=20Kope=C4=87?= <michal.kopec@3mdeb.com>
Date: Sun, 20 Oct 2024 19:22:54 +0200
Subject: [PATCH 0413/3886] soc/intel/cmn/blk: cse_enable_ptt: Wait up to 5 s
 for FW Init Complete
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

FW Init Complete is a prerequisite for sending the FW FEATURE SHIPMENT
TIME STATE OVERRIDE message. Unfortunately, on some platforms such as
Lenovo ThinkCentre M700 Tiny, it takes too long for the flag to be set,
so enabling PTT fails.

Wait up to 5 seconds for the FW Init Complete to be set instead of
failing immediately.

On M700 Tiny with debug level set to ERROR, we have to wait nearly 2
seconds:

    [EMERG]  HECI: CSE took 1900 ms to complete FW init

Because FW Init Complete is not required for getting the current feature
enablement state, only for setting, move the FW Init Complete check to
after we've determined if we actually need to change the state. This
avoids needlessly increasing boot time.

Reference: Intel ME 11.x BIOS Specification, #549522, section 6.3.15

Change-Id: Ib6de170f3f998273bec437848faa49652f013f45
Signed-off-by: Michał Kopeć <michal.kopec@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84862
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/soc/intel/common/block/cse/cse.c | 16 ++++++++++++----
 1 file changed, 12 insertions(+), 4 deletions(-)

diff --git a/src/soc/intel/common/block/cse/cse.c b/src/soc/intel/common/block/cse/cse.c
index 53c5fe1471..2e0f2dbbbd 100644
--- a/src/soc/intel/common/block/cse/cse.c
+++ b/src/soc/intel/common/block/cse/cse.c
@@ -40,6 +40,8 @@
 #define HECI_CIP_TIMEOUT_US	1000
 /* Wait up to 5 seconds for CSE to boot from RO(BP1) */
 #define CSE_DELAY_BOOT_TO_RO_MS	(5 * 1000)
+/* Wait up to 5 sec for CSE FW init to complete */
+#define CSE_FW_INIT_TIMEOUT_MS	(5 * 1000)
 
 #define SLOT_SIZE		sizeof(uint32_t)
 
@@ -1193,10 +1195,8 @@ void cse_enable_ptt(bool state)
 	 * 4) HFSTS1 FW Init Complete is set
 	 * 5) Before EOP issued to CSE
 	 */
-	if (!cse_is_hfs1_cws_normal() || !cse_is_hfs1_com_normal() ||
-	    !cse_is_hfs1_fw_init_complete() || !ENV_RAMSTAGE) {
-		printk(BIOS_ERR, "HECI: Unmet prerequisites for"
-				 "FW FEATURE SHIPMENT TIME STATE OVERRIDE\n");
+	if (!cse_is_hfs1_cws_normal() || !cse_is_hfs1_com_normal() || !ENV_RAMSTAGE) {
+		printk(BIOS_ERR, "HECI: Could not set PTT state because ME is not ready\n");
 		return;
 	}
 
@@ -1210,6 +1210,14 @@ void cse_enable_ptt(bool state)
 		return;
 	}
 
+	int elapsed = wait_ms(CSE_FW_INIT_TIMEOUT_MS, cse_is_hfs1_fw_init_complete());
+	if (!elapsed) {
+		printk(BIOS_ERR, "HECI: Could not set PTT state because ME is not ready\n");
+		return;
+	}
+
+	printk(BIOS_DEBUG, "HECI: CSE took %d ms to become ready\n", elapsed);
+
 	printk(BIOS_DEBUG, "HECI: Send FW FEATURE SHIPMENT TIME STATE OVERRIDE Command\n");
 
 	if (state)

From b4d311df6dccb367678ce18f02d68724fd2e3c4f Mon Sep 17 00:00:00 2001
From: Filip Brozovic <fbrozovic@gmail.com>
Date: Sat, 26 Oct 2024 19:26:41 +0200
Subject: [PATCH 0414/3886] soc/intel/cmn/block/smbus: Keep TCO WDT timeout
 flag if ACPI_WDAT_WDT=y
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

The TCO SMI handler clears the watchdog timeout flag unconditionally.
Since the system is only rebooted if the flag is already set and the
watchdog timer expires again, this means that the reboot never occurs.
This change preserves the timeout flag if CONFIG_ACPI_WDAT_WDT is
enabled, otherwise the behavior remains unchanged.

TEST=Build CB with CONFIG_ACPI_WDAT_WDT=y and
CONFIG_USE_PM_ACPI_TIMER=y, trigger the watchdog under Linux
with "wdctl -s 5 && cat > /dev/watchdog" and wait approximately 10
seconds (two watchdog periods) for the watchdog to reboot the system.

Change-Id: I2d35a8f8bcbcc3aaaadcc936fab028641dfd6e2c
Signed-off-by: Filip Brozovic <fbrozovic@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84875
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
---
 src/soc/intel/common/block/smbus/tco.c | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/src/soc/intel/common/block/smbus/tco.c b/src/soc/intel/common/block/smbus/tco.c
index ef7ef07d3f..b7c9922590 100644
--- a/src/soc/intel/common/block/smbus/tco.c
+++ b/src/soc/intel/common/block/smbus/tco.c
@@ -70,6 +70,15 @@ uint32_t tco_reset_status(void)
 
 	/* TCO Status 1 register */
 	tco1_sts = tco_read_reg(TCO1_STS);
+
+	/*
+	 * Don't reset the TIMEOUT status bit in case the WDAT
+	 * table is enabled, otherwise the watchdog will never
+	 * reboot the system.
+	 */
+	if (CONFIG(ACPI_WDAT_WDT))
+		tco1_sts &= ~TCO1_STS_TIMEOUT;
+
 	tco_write_reg(TCO1_STS, tco1_sts);
 
 	/* TCO Status 2 register */

From 06f3c07a25d9bd5064bbaf22bff15bba5bf4422c Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Fri, 14 Mar 2025 08:32:06 +0000
Subject: [PATCH 0415/3886] soc/intel/alderlake: Correct setting of
 PchUnlockGpioPads

This should be set to the opposite of lockdown_by_fsp.

Change-Id: I9e3c8f03ca14d2cb28c3f2f9bd74618d81e53d2c
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86854
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/soc/intel/alderlake/fsp_params.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/soc/intel/alderlake/fsp_params.c b/src/soc/intel/alderlake/fsp_params.c
index 0de9fe4f66..6b652f65fd 100644
--- a/src/soc/intel/alderlake/fsp_params.c
+++ b/src/soc/intel/alderlake/fsp_params.c
@@ -667,7 +667,7 @@ static void fill_fsps_chipset_lockdown_params(FSP_S_CONFIG *s_cfg,
 	const bool lockdown_by_fsp = get_lockdown_config() == CHIPSET_LOCKDOWN_FSP;
 	s_cfg->PchLockDownGlobalSmi = lockdown_by_fsp;
 	s_cfg->PchLockDownBiosInterface = lockdown_by_fsp;
-	s_cfg->PchUnlockGpioPads = lockdown_by_fsp;
+	s_cfg->PchUnlockGpioPads = !lockdown_by_fsp;
 	s_cfg->RtcMemoryLock = lockdown_by_fsp;
 	s_cfg->SkipPamLock = !lockdown_by_fsp;
 

From 3ff85e5dcd23ec7c77b9338fb59102d85942a933 Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Fri, 14 Mar 2025 08:44:23 +0000
Subject: [PATCH 0416/3886] soc/intel/alderlake: Make Energy Efficient Turbo
 configurable

Hook up Energy Efficient Turbo to devicetree so it can be configured.
The default value of 0 will ensure this doesn't change existing boards.

Change-Id: I58a9877371ec66e71cee15aced2413a282416b5c
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86855
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/soc/intel/alderlake/chip.h       | 3 +++
 src/soc/intel/alderlake/fsp_params.c | 2 +-
 2 files changed, 4 insertions(+), 1 deletion(-)

diff --git a/src/soc/intel/alderlake/chip.h b/src/soc/intel/alderlake/chip.h
index 5b1dabb1a0..6a95918d54 100644
--- a/src/soc/intel/alderlake/chip.h
+++ b/src/soc/intel/alderlake/chip.h
@@ -596,6 +596,9 @@ struct soc_intel_alderlake_config {
 	 */
 	bool dmi_power_optimize_disable;
 
+	/* Enable/Disable Energy Efficient Turbo */
+	bool energy_efficient_turbo;
+
 	/*
 	 * Used to communicate the power delivery design capability of the board. This
 	 * value is an enum of the available power delivery segments that are defined in
diff --git a/src/soc/intel/alderlake/fsp_params.c b/src/soc/intel/alderlake/fsp_params.c
index 6b652f65fd..caa4b98807 100644
--- a/src/soc/intel/alderlake/fsp_params.c
+++ b/src/soc/intel/alderlake/fsp_params.c
@@ -1011,7 +1011,7 @@ static void fill_fsps_misc_power_params(FSP_S_CONFIG *s_cfg,
 	s_cfg->PkgCStateLimit = LIMIT_AUTO;
 
 	/* Disable Energy Efficient Turbo mode */
-	s_cfg->EnergyEfficientTurbo = 0;
+	s_cfg->EnergyEfficientTurbo = config->energy_efficient_turbo;
 
 	/* VccIn Aux Imon IccMax. Values are in 1/4 Amp increments and range is 0-512. */
 	s_cfg->VccInAuxImonIccImax =

From 264134840c0b9f752486282cb41ece8587a4b72a Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Sun, 16 Mar 2025 20:50:21 +0000
Subject: [PATCH 0417/3886] mb/starlabs/*: Enable Energy Efficient Turbo for
 all ADL boards

This reduces power consumption so enable it. For example,
`starbook/adl_n` idles at 5.16W with this disabled, but 4.6W with
it enabled.

Change-Id: I5b6fd4853aba0dd4e9f9f45be4b43efff375dfad
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86867
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
---
 src/mainboard/starlabs/byte_adl/variants/mk_ii/devicetree.cb    | 1 +
 src/mainboard/starlabs/starbook/variants/adl/devicetree.cb      | 1 +
 src/mainboard/starlabs/starbook/variants/adl_n/devicetree.cb    | 1 +
 src/mainboard/starlabs/starbook/variants/rpl/devicetree.cb      | 1 +
 src/mainboard/starlabs/starfighter/variants/rpl/devicetree.cb   | 1 +
 src/mainboard/starlabs/starlite_adl/variants/mk_v/devicetree.cb | 1 +
 6 files changed, 6 insertions(+)

diff --git a/src/mainboard/starlabs/byte_adl/variants/mk_ii/devicetree.cb b/src/mainboard/starlabs/byte_adl/variants/mk_ii/devicetree.cb
index 192c8cb216..4ff591d5f9 100644
--- a/src/mainboard/starlabs/byte_adl/variants/mk_ii/devicetree.cb
+++ b/src/mainboard/starlabs/byte_adl/variants/mk_ii/devicetree.cb
@@ -2,6 +2,7 @@ chip soc/intel/alderlake
 	# FSP UPDs
 	register "enable_c6dram"		= "true"
 	register "eist_enable"			= "true"
+	register "energy_efficient_turbo"	= "true"
 	register "cnvi_bt_core"			= "true"
 	register "sagv"				= "SaGv_Enabled"
 
diff --git a/src/mainboard/starlabs/starbook/variants/adl/devicetree.cb b/src/mainboard/starlabs/starbook/variants/adl/devicetree.cb
index d1e866e1bf..e63d0f8558 100644
--- a/src/mainboard/starlabs/starbook/variants/adl/devicetree.cb
+++ b/src/mainboard/starlabs/starbook/variants/adl/devicetree.cb
@@ -2,6 +2,7 @@ chip soc/intel/alderlake
 	# FSP UPDs
 	register "eist_enable"			= "true"
 	register "enable_c6dram"		= "1"
+	register "energy_efficient_turbo"	= "true"
 	register "sagv"				= "SaGv_Enabled"
 
 	# Serial I/O
diff --git a/src/mainboard/starlabs/starbook/variants/adl_n/devicetree.cb b/src/mainboard/starlabs/starbook/variants/adl_n/devicetree.cb
index c180de222c..0140f252de 100644
--- a/src/mainboard/starlabs/starbook/variants/adl_n/devicetree.cb
+++ b/src/mainboard/starlabs/starbook/variants/adl_n/devicetree.cb
@@ -2,6 +2,7 @@ chip soc/intel/alderlake
 	# FSP UPDs
 	register "eist_enable"			= "true"
 	register "enable_c6dram"		= "true"
+	register "energy_efficient_turbo"	= "true"
 	register "sagv"				= "SaGv_Enabled"
 
 	# Serial I/O
diff --git a/src/mainboard/starlabs/starbook/variants/rpl/devicetree.cb b/src/mainboard/starlabs/starbook/variants/rpl/devicetree.cb
index 30c5dfc4b5..abf9802122 100644
--- a/src/mainboard/starlabs/starbook/variants/rpl/devicetree.cb
+++ b/src/mainboard/starlabs/starbook/variants/rpl/devicetree.cb
@@ -4,6 +4,7 @@ chip soc/intel/alderlake
 	register "eist_enable"				= "true"
 	register "enable_c1e"				= "true"
 	register "enable_c6dram"			= "true"
+	register "energy_efficient_turbo"		= "true"
 	register "sagv"					= "SaGv_Enabled"
 
 	# Serial I/O
diff --git a/src/mainboard/starlabs/starfighter/variants/rpl/devicetree.cb b/src/mainboard/starlabs/starfighter/variants/rpl/devicetree.cb
index 5c85da4a16..cb5c8767d3 100644
--- a/src/mainboard/starlabs/starfighter/variants/rpl/devicetree.cb
+++ b/src/mainboard/starlabs/starfighter/variants/rpl/devicetree.cb
@@ -4,6 +4,7 @@ chip soc/intel/alderlake
 	register "eist_enable"				= "true"
 	register "enable_c1e"				= "true"
 	register "enable_c6dram"			= "true"
+	register "energy_efficient_turbo"		= "true"
 	register "sagv"					= "SaGv_Enabled"
 
 	# Serial I/O
diff --git a/src/mainboard/starlabs/starlite_adl/variants/mk_v/devicetree.cb b/src/mainboard/starlabs/starlite_adl/variants/mk_v/devicetree.cb
index 86324a8385..52bd80b030 100644
--- a/src/mainboard/starlabs/starlite_adl/variants/mk_v/devicetree.cb
+++ b/src/mainboard/starlabs/starlite_adl/variants/mk_v/devicetree.cb
@@ -2,6 +2,7 @@ chip soc/intel/alderlake
 	# FSP UPDs
 	register "cnvi_bt_core"			= "true"
 	register "enable_c6dram"		= "true"
+	register "energy_efficient_turbo"	= "true"
 	register "eist_enable"			= "true"
 	register "sagv"				= "SaGv_Enabled"
 

From f160b6f66ec3ba2719033e8a35193bae31957780 Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Tue, 11 Mar 2025 10:03:03 -0500
Subject: [PATCH 0418/3886] soc/intel/tigerlake: Use common ACPI code for SRAM
 and HECI

Use the newly-created ACPI devices in common/acpi, and adjust the
SoC ACPI name for the CSE/HECI device to match.

Change-Id: I3a4b122b206cb1fc98e693973f2aeb28e8b2ff22
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86814
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/soc/intel/tigerlake/acpi/pcie.asl        | 10 ----------
 src/soc/intel/tigerlake/acpi/southbridge.asl |  7 +++++++
 src/soc/intel/tigerlake/chip.c               |  2 +-
 3 files changed, 8 insertions(+), 11 deletions(-)

diff --git a/src/soc/intel/tigerlake/acpi/pcie.asl b/src/soc/intel/tigerlake/acpi/pcie.asl
index 86d53fe2b7..e61d140898 100644
--- a/src/soc/intel/tigerlake/acpi/pcie.asl
+++ b/src/soc/intel/tigerlake/acpi/pcie.asl
@@ -523,13 +523,3 @@ Device (RP24)
 	}
 }
 #endif /* CONFIG(SOC_INTEL_TIGERLAKE_PCH_H) */
-
-Device (SRAM)
-{
-	Name (_ADR, 0x00140002)
-}
-
-Device (HEC1)
-{
-	Name (_ADR, 0x00160000)
-}
diff --git a/src/soc/intel/tigerlake/acpi/southbridge.asl b/src/soc/intel/tigerlake/acpi/southbridge.asl
index 23536b3861..19fa050da4 100644
--- a/src/soc/intel/tigerlake/acpi/southbridge.asl
+++ b/src/soc/intel/tigerlake/acpi/southbridge.asl
@@ -38,6 +38,13 @@
 /* USB XHCI 0:14.0 */
 #include "xhci.asl"
 
+/* PMC Shared SRAM 0:14.2 */
+#include <soc/intel/common/block/acpi/acpi/sram.asl>
+
+/* CSE/HECI #1 0:16.0 */
+#include <soc/intel/common/block/acpi/acpi/heci.asl>
+
+
 /* PCI _OSC */
 #include <soc/intel/common/acpi/pci_osc.asl>
 
diff --git a/src/soc/intel/tigerlake/chip.c b/src/soc/intel/tigerlake/chip.c
index f2ccb48c08..7535983e36 100644
--- a/src/soc/intel/tigerlake/chip.c
+++ b/src/soc/intel/tigerlake/chip.c
@@ -136,7 +136,7 @@ const char *soc_acpi_name(const struct device *dev)
 	case PCH_DEVFN_GBE:		return "GLAN";
 	case PCH_DEVFN_SRAM:		return "SRAM";
 	case PCH_DEVFN_SPI:		return "FSPI";
-	case PCH_DEVFN_CSE:		return "HEC1";
+	case PCH_DEVFN_CSE:		return "HECI";
 	}
 
 	return NULL;

From 7b4110b1bf476adddbec71b7bfa9da8d8d8401a3 Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Tue, 11 Mar 2025 10:05:05 -0500
Subject: [PATCH 0419/3886] soc/intel/cannonlake: Use common ACPI code for SRAM
 and HECI

Use the newly-created ACPI devices in common/acpi, and adjust the
SoC ACPI name for the CSE/HECI device to match.

Change-Id: Id7b68e7c5ed554639dc14e837e311552c3ff92f0
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86815
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
---
 src/soc/intel/cannonlake/acpi/pcie.asl        | 10 ----------
 src/soc/intel/cannonlake/acpi/southbridge.asl |  6 ++++++
 src/soc/intel/cannonlake/chip.c               |  2 +-
 3 files changed, 7 insertions(+), 11 deletions(-)

diff --git a/src/soc/intel/cannonlake/acpi/pcie.asl b/src/soc/intel/cannonlake/acpi/pcie.asl
index 21e7925cc0..302863baba 100644
--- a/src/soc/intel/cannonlake/acpi/pcie.asl
+++ b/src/soc/intel/cannonlake/acpi/pcie.asl
@@ -521,13 +521,3 @@ Device (RP24)
 	}
 }
 #endif
-
-Device (SRAM)
-{
-	Name (_ADR, 0x00140002)
-}
-
-Device (CSE1)
-{
-	Name (_ADR, 0x00160000)
-}
diff --git a/src/soc/intel/cannonlake/acpi/southbridge.asl b/src/soc/intel/cannonlake/acpi/southbridge.asl
index 20d4bfd897..322c8ff7a3 100644
--- a/src/soc/intel/cannonlake/acpi/southbridge.asl
+++ b/src/soc/intel/cannonlake/acpi/southbridge.asl
@@ -34,6 +34,12 @@
 /* USB XHCI 0:14.0 */
 #include "xhci.asl"
 
+/* PMC Shared SRAM 0:14.2 */
+#include <soc/intel/common/block/acpi/acpi/sram.asl>
+
+/* CSE/HECI #1 0:16.0 */
+#include <soc/intel/common/block/acpi/acpi/heci.asl>
+
 /* PCI _OSC */
 #include <soc/intel/common/acpi/pci_osc.asl>
 
diff --git a/src/soc/intel/cannonlake/chip.c b/src/soc/intel/cannonlake/chip.c
index e2e4a6bda5..11bd9b6148 100644
--- a/src/soc/intel/cannonlake/chip.c
+++ b/src/soc/intel/cannonlake/chip.c
@@ -90,7 +90,7 @@ const char *soc_acpi_name(const struct device *dev)
 	case PCH_DEVFN_I2C1:	return "I2C1";
 	case PCH_DEVFN_I2C2:	return "I2C2";
 	case PCH_DEVFN_I2C3:	return "I2C3";
-	case PCH_DEVFN_CSE:	return "CSE1";
+	case PCH_DEVFN_CSE:	return "HECI";
 	case PCH_DEVFN_CSE_2:	return "CSE2";
 	case PCH_DEVFN_CSE_IDER:	return "CSED";
 	case PCH_DEVFN_CSE_KT:	return "CSKT";

From ba42b42cda69374654e79af9a3f439818a81d2ed Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Tue, 11 Mar 2025 10:18:22 -0500
Subject: [PATCH 0420/3886] soc/intel/skylake: Use common ACPI code for HECI

Use the newly-created ACPI device in common/acpi, and adjust the
SoC ACPI name for the CSE/HECI device to match.

Change-Id: Ie4d9a480152fabb93d784b338c2846feba874f4b
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86817
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
---
 src/soc/intel/skylake/acpi/pch.asl | 3 +++
 src/soc/intel/skylake/chip.c       | 2 +-
 2 files changed, 4 insertions(+), 1 deletion(-)

diff --git a/src/soc/intel/skylake/acpi/pch.asl b/src/soc/intel/skylake/acpi/pch.asl
index 832663315d..ba9780881c 100644
--- a/src/soc/intel/skylake/acpi/pch.asl
+++ b/src/soc/intel/skylake/acpi/pch.asl
@@ -43,6 +43,9 @@
 /* USB XHCI 0:14.0 */
 #include "xhci.asl"
 
+/* CSE/HECI #1 0:16.0 */
+#include <soc/intel/common/block/acpi/acpi/heci.asl>
+
 Method (_OSC, 4)
 {
 	/* Check for proper GUID */
diff --git a/src/soc/intel/skylake/chip.c b/src/soc/intel/skylake/chip.c
index a6844e068a..d7364fdca2 100644
--- a/src/soc/intel/skylake/chip.c
+++ b/src/soc/intel/skylake/chip.c
@@ -116,7 +116,7 @@ const char *soc_acpi_name(const struct device *dev)
 	case PCH_DEVFN_I2C1:	return "I2C1";
 	case PCH_DEVFN_I2C2:	return "I2C2";
 	case PCH_DEVFN_I2C3:	return "I2C3";
-	case PCH_DEVFN_CSE:	return "CSE1";
+	case PCH_DEVFN_CSE:	return "HECI";
 	case PCH_DEVFN_CSE_2:	return "CSE2";
 	case PCH_DEVFN_CSE_IDER:	return "CSED";
 	case PCH_DEVFN_CSE_KT:	return "CSKT";

From 0c60652a5137e25f3cacddc79dee13936be26325 Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Sat, 14 Sep 2024 15:15:50 -0500
Subject: [PATCH 0421/3886] mb/google/dedede: Deselect INTEL_CRASHLOG

Jasperlake FSP does not properly support the crashlog fearture, and
selecting this option significantly impacts boot time negatively by an
order of magnitude (~10s vs ~1s) and breaks USB detection in edk2
payload; inability to properly enumerate USB devices is almost
certainly the cause of the increased boot time.

TEST=build/boot google/maglia, verify boot time normal (~1s) and USB
detection working as expected with multiple USB devices connected.

Change-Id: I53be4befe9a04bdaece21f40f93af6599baa7e0b
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84359
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sowmya Aralguppe <sowmya.aralguppe@intel.com>
---
 src/mainboard/google/dedede/Kconfig | 1 -
 1 file changed, 1 deletion(-)

diff --git a/src/mainboard/google/dedede/Kconfig b/src/mainboard/google/dedede/Kconfig
index d6d41368c8..cb61eccb39 100644
--- a/src/mainboard/google/dedede/Kconfig
+++ b/src/mainboard/google/dedede/Kconfig
@@ -33,7 +33,6 @@ config BOARD_GOOGLE_BASEBOARD_DEDEDE
 	select SOC_INTEL_COMMON_BLOCK_IPU
 	select SOC_INTEL_CSE_LITE_SKU
 	select SOC_INTEL_JASPERLAKE
-	select SOC_INTEL_CRASHLOG
 	select SPI_FLASH_SMM
 
 config BOARD_GOOGLE_AWASUKI

From 35933e40be83667bb2d1e1de9e9618cd690c6124 Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Wed, 12 Mar 2025 12:05:26 -0500
Subject: [PATCH 0422/3886] Revert "soc/intel/jasperlake: Add CrashLog
 implementation for Intel JSL"

This reverts commit 07dd73c9214b766762a89ffe51f27c77799293be.

Jasperlake FSP does not properly support the crashlog feature, and
enabling it results in several issues (increased boot time, issues
with USB device detection).

Change-Id: I5598b40321b3ca15a48ac6eff64a85323d55939d
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86844
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-by: Sowmya Aralguppe <sowmya.aralguppe@intel.com>
---
 src/soc/intel/jasperlake/Makefile.mk          |   1 -
 src/soc/intel/jasperlake/crashlog_lib.c       | 306 ------------------
 .../intel/jasperlake/include/soc/crashlog.h   |  23 --
 .../intel/jasperlake/include/soc/pci_devs.h   |   7 -
 .../intel/jasperlake/romstage/fsp_params.c    |   6 -
 .../intel/fsp/fsp2_0/jasperlake/FspmUpd.h     |   6 +-
 6 files changed, 2 insertions(+), 347 deletions(-)
 delete mode 100644 src/soc/intel/jasperlake/crashlog_lib.c
 delete mode 100644 src/soc/intel/jasperlake/include/soc/crashlog.h

diff --git a/src/soc/intel/jasperlake/Makefile.mk b/src/soc/intel/jasperlake/Makefile.mk
index 2763d71ae6..1377fff9e0 100644
--- a/src/soc/intel/jasperlake/Makefile.mk
+++ b/src/soc/intel/jasperlake/Makefile.mk
@@ -42,7 +42,6 @@ ramstage-y += reset.c
 ramstage-y += systemagent.c
 ramstage-y += sd.c
 ramstage-y += xhci.c
-ramstage-$(CONFIG_SOC_INTEL_CRASHLOG) += crashlog_lib.c
 
 smm-y += gpio.c
 smm-y += p2sb.c
diff --git a/src/soc/intel/jasperlake/crashlog_lib.c b/src/soc/intel/jasperlake/crashlog_lib.c
deleted file mode 100644
index abe448f9e6..0000000000
--- a/src/soc/intel/jasperlake/crashlog_lib.c
+++ /dev/null
@@ -1,306 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <arch/bert_storage.h>
-#include <console/console.h>
-#include <device/pci_ops.h>
-#include <intelblocks/crashlog.h>
-#include <intelblocks/pmc_ipc.h>
-#include <soc/crashlog.h>
-#include <soc/iomap.h>
-#include <soc/pci_devs.h>
-#include <string.h>
-
-/* global crashLog info */
-static bool m_pmc_crashLog_support;
-static bool m_pmc_crashLog_present;
-static bool m_cpu_crashLog_support;
-static bool m_cpu_crashLog_present;
-static u32 m_pmc_crashLog_size;
-static u32 m_cpu_crashLog_size;
-static u32 cpu_crash_version;
-static pmc_ipc_discovery_buf_t discovery_buf;
-static pmc_crashlog_desc_table_t descriptor_table;
-static tel_crashlog_devsc_cap_t cpu_cl_devsc_cap;
-static cpu_crashlog_discovery_table_t cpu_cl_disc_tab;
-
-uintptr_t __weak cl_get_cpu_mb_int_addr(void)
-{
-	return CRASHLOG_MAILBOX_INTF_ADDRESS;
-}
-
-bool pmc_cl_discovery(void)
-{
-	u32 tmp_bar_addr = 0, desc_table_addr = 0;
-
-	const struct pmc_ipc_buffer *req = { 0 };
-	struct pmc_ipc_buffer *res = NULL;
-	uint32_t cmd_reg;
-	int r;
-
-	cmd_reg = pmc_make_ipc_cmd(PMC_IPC_CMD_CRASHLOG,
-				PMC_IPC_CMD_ID_CRASHLOG_DISCOVERY,
-				PMC_IPC_CMD_SIZE_SHIFT);
-	printk(BIOS_DEBUG, "cmd_reg from pmc_make_ipc_cmd %d\n", cmd_reg);
-
-	r = pmc_send_ipc_cmd(cmd_reg, req, res);
-
-	if (r < 0) {
-		printk(BIOS_ERR, "pmc_send_ipc_cmd failed in %s\n", __func__);
-		return false;
-	}
-	discovery_buf.val_64_bits = ((u64)res->buf[1] << 32) | res->buf[0];
-
-
-	if (discovery_buf.bits.supported != 1) {
-		printk(BIOS_DEBUG, "PCH crashlog feature not supported.\n");
-		m_pmc_crashLog_support = false;
-		return false;
-	}
-	m_pmc_crashLog_support = true;
-
-	/* Program BAR 0 and enable command register memory space decoding */
-	tmp_bar_addr = SPI_BASE_ADDRESS;
-	pci_write_config32(PCH_DEV_SRAM, PCI_BASE_ADDRESS_0, tmp_bar_addr);
-	pci_or_config16(PCH_DEV_SRAM, PCI_COMMAND, PCI_COMMAND_MEMORY);
-
-	if (discovery_buf.bits.discov_mechanism == 1) {
-		/* discovery mode */
-		if (discovery_buf.bits.base_offset & BIT(31)) {
-			printk(BIOS_DEBUG, "PCH discovery to be used is disabled.\n");
-			m_pmc_crashLog_present = false;
-			m_pmc_crashLog_size = 0;
-			return false;
-		}
-		desc_table_addr = tmp_bar_addr + discovery_buf.bits.desc_tabl_offset;
-		m_pmc_crashLog_size = pmc_cl_gen_descriptor_table(desc_table_addr,
-								  &descriptor_table);
-		printk(BIOS_DEBUG, "PMC crashLog size in discovery mode : 0x%X\n",
-		       m_pmc_crashLog_size);
-	} else {
-		/* legacy mode */
-		if (discovery_buf.bits.dis) {
-			printk(BIOS_DEBUG, "PCH crashlog is disabled in legacy mode.\n");
-			m_pmc_crashLog_present = false;
-			return false;
-		}
-		m_pmc_crashLog_size = (discovery_buf.bits.size != 0) ?
-					(discovery_buf.bits.size * sizeof(u32)) : 0xC00;
-		printk(BIOS_DEBUG, "PMC crashlog size in legacy mode = 0x%x\n",
-			m_pmc_crashLog_size);
-	}
-	m_pmc_crashLog_present = true;
-
-	return true;
-}
-
-uintptr_t cl_get_cpu_bar_addr(void)
-{
-	u32 base_addr = 0;
-	if (cpu_cl_devsc_cap.discovery_data.fields.t_bir_q == TEL_DVSEC_TBIR_BAR0) {
-		base_addr = pci_read_config32(SA_DEV_TMT, PCI_BASE_ADDRESS_0) &
-				~PCI_BASE_ADDRESS_MEM_ATTR_MASK;
-	} else if (cpu_cl_devsc_cap.discovery_data.fields.t_bir_q == TEL_DVSEC_TBIR_BAR1) {
-		base_addr = pci_read_config32(SA_DEV_TMT, PCI_BASE_ADDRESS_1) &
-				~PCI_BASE_ADDRESS_MEM_ATTR_MASK;
-	} else {
-		printk(BIOS_ERR, "Invalid TEL_CFG_BAR value %d:\n",
-			cpu_cl_devsc_cap.discovery_data.fields.t_bir_q);
-	}
-
-	return base_addr;
-}
-
-uintptr_t cl_get_cpu_tmp_bar(void)
-{
-	return SPI_BASE_ADDRESS;
-}
-
-bool cl_pmc_sram_has_mmio_access(void)
-{
-	if (pci_read_config16(PCH_DEV_SRAM, PCI_VENDOR_ID) == 0xFFFF) {
-		printk(BIOS_ERR, "PMC SSRAM PCI device is disabled.\n");
-		return false;
-	}
-
-	return true;
-}
-
-static bool cpu_cl_get_capability(tel_crashlog_devsc_cap_t *cl_devsc_cap)
-{
-	cl_devsc_cap->cap_data.data = pci_read_config32(SA_DEV_TMT,
-						TEL_DVSEC_OFFSET + TEL_DVSEC_PCIE_CAP_ID);
-	if (cl_devsc_cap->cap_data.fields.pcie_cap_id != TELEMETRY_EXTENDED_CAP_ID) {
-		printk(BIOS_DEBUG, "Read ID for Telemetry: 0x%x differs from expected: 0x%x\n",
-		       cl_devsc_cap->cap_data.fields.pcie_cap_id, TELEMETRY_EXTENDED_CAP_ID);
-		return false;
-	}
-
-	/* walk through the entries until crashLog entry */
-	cl_devsc_cap->devsc_data.data_32[1] = pci_read_config32(SA_DEV_TMT, TEL_DVSEV_ID);
-	int new_offset = 0;
-	while (cl_devsc_cap->devsc_data.fields.devsc_id != CRASHLOG_DVSEC_ID) {
-		if (cl_devsc_cap->cap_data.fields.next_cap_offset == 0
-		     || cl_devsc_cap->cap_data.fields.next_cap_offset == 0xFFFF) {
-			printk(BIOS_DEBUG, "Read invalid pcie_cap_id value: : 0x%x\n",
-			       cl_devsc_cap->cap_data.fields.pcie_cap_id);
-			return false;
-		}
-		new_offset = cl_devsc_cap->cap_data.fields.next_cap_offset;
-		cl_devsc_cap->cap_data.data = pci_read_config32(SA_DEV_TMT,
-						new_offset + TEL_DVSEC_PCIE_CAP_ID);
-		cl_devsc_cap->devsc_data.data_32[1] = pci_read_config32(SA_DEV_TMT,
-							new_offset + TEL_DVSEV_ID);
-	}
-	cpu_crash_version = cl_devsc_cap->devsc_data.fields.devsc_ver;
-
-	cl_devsc_cap->discovery_data.data = pci_read_config32(SA_DEV_TMT, new_offset
-						+ TEL_DVSEV_DISCOVERY_TABLE_OFFSET);
-
-	return true;
-}
-
-static bool cpu_cl_gen_discovery_table(void)
-{
-	uintptr_t bar_addr = 0, disc_tab_addr = 0;
-	bar_addr = cl_get_cpu_bar_addr();
-	disc_tab_addr = bar_addr +
-			cpu_cl_devsc_cap.discovery_data.fields.discovery_table_offset;
-	memset(&cpu_cl_disc_tab, 0, sizeof(cpu_crashlog_discovery_table_t));
-
-	cpu_cl_disc_tab.header.data = ((u64)read32((u32 *)disc_tab_addr) +
-				     ((u64)read32((u32 *)(disc_tab_addr + 4)) << 32));
-
-	cpu_cl_disc_tab.cmd_mailbox.data = read32((u32 *)(disc_tab_addr + 8));
-	cpu_cl_disc_tab.mailbox_data = read32((u32 *)(disc_tab_addr + 12));
-
-	printk(BIOS_DEBUG, "cpu_crashlog_discovery_table buffer count: 0x%x\n",
-		cpu_cl_disc_tab.header.fields.count);
-
-	if (cpu_cl_disc_tab.header.fields.guid != CPU_CRASHLOG_DISC_TAB_GUID_VALID) {
-		printk(BIOS_ERR, "Invalid CPU crashlog discovery table GUID, expected = 0x%X ,"
-			"actual = 0x%X\n", CPU_CRASHLOG_DISC_TAB_GUID_VALID,
-			cpu_cl_disc_tab.header.fields.guid);
-		return false;
-	}
-
-	int cur_offset = 0;
-	for (int i = 0; i <  cpu_cl_disc_tab.header.fields.count ; i++) {
-		cur_offset = 16 + 8*i;
-		cpu_cl_disc_tab.buffers[i].data = ((u64)read32((u32 *)(disc_tab_addr +
-						cur_offset)) + ((u64)read32((u32 *)
-						(disc_tab_addr + cur_offset + 4)) << 32));
-		printk(BIOS_DEBUG, "cpu_crashlog_discovery_table buffer: 0x%x size:"
-			"0x%x offset: 0x%x\n", i,  cpu_cl_disc_tab.buffers[i].fields.size,
-			cpu_cl_disc_tab.buffers[i].fields.offset);
-		m_cpu_crashLog_size += cpu_cl_disc_tab.buffers[i].fields.size * sizeof(u32);
-	}
-
-	m_cpu_crashLog_present = m_cpu_crashLog_size > 0;
-
-	return true;
-}
-
-bool cpu_cl_discovery(void)
-{
-	memset(&cpu_cl_devsc_cap, 0, sizeof(tel_crashlog_devsc_cap_t));
-
-	if (!cpu_cl_get_capability(&cpu_cl_devsc_cap)) {
-		printk(BIOS_ERR, "CPU crashlog capability  not found.\n");
-		m_cpu_crashLog_support = false;
-		return false;
-	}
-
-	m_cpu_crashLog_support = true;
-
-	/* Program BAR address and enable command register memory space decoding */
-	u32 tmp_bar_addr = PCH_PWRM_BASE_ADDRESS;
-	printk(BIOS_DEBUG, "tmp_bar_addr: 0x%X\n", tmp_bar_addr);
-
-	if (cpu_cl_devsc_cap.discovery_data.fields.t_bir_q == TEL_DVSEC_TBIR_BAR0) {
-		pci_write_config32(SA_DEV_TMT, PCI_BASE_ADDRESS_0, tmp_bar_addr);
-	} else if (cpu_cl_devsc_cap.discovery_data.fields.t_bir_q == TEL_DVSEC_TBIR_BAR1) {
-		pci_write_config32(SA_DEV_TMT, PCI_BASE_ADDRESS_1, tmp_bar_addr);
-	} else {
-		printk(BIOS_DEBUG, "invalid discovery data t_bir_q: 0x%x\n",
-			cpu_cl_devsc_cap.discovery_data.fields.t_bir_q);
-		return false;
-	}
-	pci_or_config16(SA_DEV_TMT, PCI_COMMAND, PCI_COMMAND_MEMORY);
-
-	if (!cpu_cl_gen_discovery_table()) {
-		printk(BIOS_ERR, "CPU crashlog discovery table not valid.\n");
-		m_cpu_crashLog_present = false;
-		return false;
-	}
-	m_cpu_crashLog_present = true;
-
-	return true;
-}
-
-void reset_discovery_buffers(void)
-{
-	memset(&discovery_buf, 0, sizeof(pmc_ipc_discovery_buf_t));
-	memset(&descriptor_table, 0, sizeof(pmc_crashlog_desc_table_t));
-	memset(&cpu_cl_devsc_cap, 0, sizeof(tel_crashlog_devsc_cap_t));
-}
-
-
-int cl_get_total_data_size(void)
-{
-	return m_pmc_crashLog_size + m_cpu_crashLog_size;
-}
-
-pmc_ipc_discovery_buf_t cl_get_pmc_discovery_buf(void)
-{
-	return discovery_buf;
-}
-
-pmc_crashlog_desc_table_t cl_get_pmc_descriptor_table(void)
-{
-	return descriptor_table;
-}
-
-int cl_get_pmc_record_size(void)
-{
-	return m_pmc_crashLog_size;
-}
-
-int cl_get_cpu_record_size(void)
-{
-	return m_cpu_crashLog_size;
-}
-
-bool cl_cpu_data_present(void)
-{
-	return m_cpu_crashLog_present;
-}
-
-bool cl_pmc_data_present(void)
-{
-	return m_pmc_crashLog_present;
-}
-
-bool cpu_crashlog_support(void)
-{
-	return m_cpu_crashLog_support;
-}
-
-bool pmc_crashlog_support(void)
-{
-	return m_pmc_crashLog_support;
-}
-
-void update_new_pmc_crashlog_size(u32 *pmc_crash_size)
-{
-	m_pmc_crashLog_size = *pmc_crash_size;
-}
-
-cpu_crashlog_discovery_table_t cl_get_cpu_discovery_table(void)
-{
-	return cpu_cl_disc_tab;
-}
-
-void update_new_cpu_crashlog_size(u32 *cpu_crash_size)
-{
-	m_cpu_crashLog_size = *cpu_crash_size;
-}
diff --git a/src/soc/intel/jasperlake/include/soc/crashlog.h b/src/soc/intel/jasperlake/include/soc/crashlog.h
deleted file mode 100644
index e8ba0aaa10..0000000000
--- a/src/soc/intel/jasperlake/include/soc/crashlog.h
+++ /dev/null
@@ -1,23 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#ifndef _SOC_JASPERLAKE_BLOCK_CRASHLOG_LIB_H_
-#define _SOC_JASPERLAKE_BLOCK_CRASHLOG_LIB_H_
-
-#include <types.h>
-
-/* DVSEC capability Registers */
-#define TEL_DVSEC_OFFSET			0x100
-#define TEL_DVSEC_PCIE_CAP_ID			0x0
-#define TEL_DVSEC_NEXT_CAP			0x2
-#define TEL_DVSEV_ID				0x8
-#define TEL_DVSEV_DISCOVERY_TABLE_OFFSET	0xC
-#define TELEMETRY_EXTENDED_CAP_ID		0x23
-#define CRASHLOG_DVSEC_ID			0x04
-#define TEL_DVSEC_TBIR_BAR0			0
-#define TEL_DVSEC_TBIR_BAR1			1
-
-/* CPU CrashLog MMIO Registers */
-#define CRASHLOG_MAILBOX_INTF_ADDRESS		0x6038
-#define CRASHLOG_POINTER_SIZE_FIELD_OFFSET	0x04
-
-#endif /* _SOC_JASPERLAKE_BLOCK_CRASHLOG_LIB_H_ */
diff --git a/src/soc/intel/jasperlake/include/soc/pci_devs.h b/src/soc/intel/jasperlake/include/soc/pci_devs.h
index b8cc067a36..e3276458bf 100644
--- a/src/soc/intel/jasperlake/include/soc/pci_devs.h
+++ b/src/soc/intel/jasperlake/include/soc/pci_devs.h
@@ -5,15 +5,12 @@
 
 #include <device/pci_def.h>
 
-#define _SA_DEVFN(slot, func)	PCI_DEVFN(SA_DEV_SLOT_ ## slot, func)
 #define _PCH_DEVFN(slot, func)	PCI_DEVFN(PCH_DEV_SLOT_ ## slot, func)
 
 #if !defined(__SIMPLE_DEVICE__)
 #include <device/device.h>
-#define _SA_DEV(slot, func)	pcidev_path_on_root(_SA_DEVFN(slot, func))
 #define _PCH_DEV(slot, func)	pcidev_path_on_root_debug(_PCH_DEVFN(slot, func), __func__)
 #else
-#define _SA_DEV(slot, func)	PCI_DEV(0, SA_DEV_SLOT_ ## slot, func)
 #define _PCH_DEV(slot, func)	PCI_DEV(0, PCH_DEV_SLOT_ ## slot, func)
 #endif
 
@@ -51,10 +48,6 @@
 #define  SA_DEVFN_GNA		PCI_DEVFN(SA_DEV_SLOT_GNA, 0)
 #define  SA_DEV_GNA		PCI_DEV(0, SA_DEV_SLOT_GNA, 0)
 
-#define SA_DEV_SLOT_TMT		0x14
-#define SA_DEVFN_TMT		_SA_DEVFN(TMT, 2)
-#define SA_DEV_TMT		_SA_DEV(TMT, 2)
-
 /* PCH Devices */
 #define PCH_DEV_SLOT_SIO0	0x10
 #define  PCH_DEVFN_CNVI_BT	_PCH_DEVFN(SIO0, 2)
diff --git a/src/soc/intel/jasperlake/romstage/fsp_params.c b/src/soc/intel/jasperlake/romstage/fsp_params.c
index 0d9710eb79..5a06e12347 100644
--- a/src/soc/intel/jasperlake/romstage/fsp_params.c
+++ b/src/soc/intel/jasperlake/romstage/fsp_params.c
@@ -143,12 +143,6 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg,
 	 * and rely on GPIO settings programmed before moved to FSP.
 	 */
 	m_cfg->GpioOverride = 1;
-
-	/* crashLog config */
-	if (CONFIG(SOC_INTEL_CRASHLOG)) {
-		m_cfg->CpuCrashLogDevice = 1;
-		m_cfg->CpuCrashLogEnable = 1;
-	}
 }
 
 void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version)
diff --git a/src/vendorcode/intel/fsp/fsp2_0/jasperlake/FspmUpd.h b/src/vendorcode/intel/fsp/fsp2_0/jasperlake/FspmUpd.h
index db7679e36c..55f841835e 100644
--- a/src/vendorcode/intel/fsp/fsp2_0/jasperlake/FspmUpd.h
+++ b/src/vendorcode/intel/fsp/fsp2_0/jasperlake/FspmUpd.h
@@ -72,11 +72,9 @@ typedef struct {
 **/
   UINT8                       EnableAbove4GBMmio;
 
-/** Offset 0x004B - Enable/Disable CrashLog Device 10
-  Enable(Default): Enable CPU CrashLog Device 10, Disable: Disable CPU CrashLog
-  $EN_DIS
+/** Offset 0x004B - Reserved
 **/
-  UINT8                       CpuCrashLogDevice;
+  UINT8                       Reserved0;
 
 /** Offset 0x004C - Memory SPD Pointer Channel 0 Dimm 0
   Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00

From fb52bc8b5050e0b802ddd63dd4af4b9cbd0d0cf7 Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Mon, 17 Mar 2025 15:03:15 +0000
Subject: [PATCH 0423/3886] mb/starlabs/starbook/mtl: Correct GPIO references

The table included 3 entries for GPP_F00, so adjust them to the
correct pads.

Change-Id: Ic8d3a2e742f01231d1a4b777879da0b310085efe
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86894
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/starlabs/starbook/variants/mtl/gpio.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/mainboard/starlabs/starbook/variants/mtl/gpio.c b/src/mainboard/starlabs/starbook/variants/mtl/gpio.c
index 48b4276079..946cff0a64 100644
--- a/src/mainboard/starlabs/starbook/variants/mtl/gpio.c
+++ b/src/mainboard/starlabs/starbook/variants/mtl/gpio.c
@@ -310,9 +310,9 @@ const struct pad_config gpio_table[] = {
 	/* F03:	CNV_RGI_RSP			*/
 	PAD_NC(GPP_F03, NONE),
 	/* F04:	CNVI_RF_RESET_N			*/
-	PAD_NC(GPP_F00, NONE),
+	PAD_NC(GPP_F04, NONE),
 	/* F05:	MODEM_CLKREQ			*/
-	PAD_NC(GPP_F00, NONE),
+	PAD_NC(GPP_F05, NONE),
 	/* F06:					*/
 	PAD_NC(GPP_F06, NONE),
 	/* F07:					*/

From ebe350182878affd6ab8b7fa4e5fe27966bb9821 Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Mon, 17 Mar 2025 15:05:40 +0000
Subject: [PATCH 0424/3886] mb/starlabs/starbook/mtl: Enable DDC for DDIA

Enable DDC so that GOP can read the backlight brightness from EDID. This
avoids FSP repeatedly trying and failing to read it, and also stops the
backlight brightness not being restored correctly in Linux.

Change-Id: Icd292ee175a14799fe08c0989ca3fdccd5ccc123
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86895
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
---
 src/mainboard/starlabs/starbook/variants/mtl/devicetree.cb | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/mainboard/starlabs/starbook/variants/mtl/devicetree.cb b/src/mainboard/starlabs/starbook/variants/mtl/devicetree.cb
index 19d5d99ef3..544df456d5 100644
--- a/src/mainboard/starlabs/starbook/variants/mtl/devicetree.cb
+++ b/src/mainboard/starlabs/starbook/variants/mtl/devicetree.cb
@@ -45,7 +45,7 @@ chip soc/intel/meteorlake
 
 			register "ddi_port_A_config"		= "1"
 			register "ddi_ports_config" = "{
-				[DDI_PORT_A]			= DDI_ENABLE_HPD,
+				[DDI_PORT_A]			= DDI_ENABLE_HPD | DDI_ENABLE_DDC,
 				[DDI_PORT_B]			= DDI_ENABLE_HPD | DDI_ENABLE_DDC,
 				[DDI_PORT_1]			= DDI_ENABLE_HPD,
 				[DDI_PORT_2]			= DDI_ENABLE_HPD,

From f6220f72cf2eade1a24fe1bb74133ddf4d832ed7 Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Mon, 17 Mar 2025 15:07:37 +0000
Subject: [PATCH 0425/3886] mb/starlabs/starbook/mtl: Disable HPD for USB
 Type-C ports

Display-Alt Mode doesn't require HPD to be set here, so remove it.

Change-Id: I2a22519dcf87e77fabefe0d2a392808d9b449872
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86896
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/starlabs/starbook/variants/mtl/devicetree.cb | 2 --
 1 file changed, 2 deletions(-)

diff --git a/src/mainboard/starlabs/starbook/variants/mtl/devicetree.cb b/src/mainboard/starlabs/starbook/variants/mtl/devicetree.cb
index 544df456d5..93c9b1ec91 100644
--- a/src/mainboard/starlabs/starbook/variants/mtl/devicetree.cb
+++ b/src/mainboard/starlabs/starbook/variants/mtl/devicetree.cb
@@ -47,8 +47,6 @@ chip soc/intel/meteorlake
 			register "ddi_ports_config" = "{
 				[DDI_PORT_A]			= DDI_ENABLE_HPD | DDI_ENABLE_DDC,
 				[DDI_PORT_B]			= DDI_ENABLE_HPD | DDI_ENABLE_DDC,
-				[DDI_PORT_1]			= DDI_ENABLE_HPD,
-				[DDI_PORT_2]			= DDI_ENABLE_HPD,
 			}"
 		end
 		device ref tcss_xhci	on

From cba1aeae71c8da3e5b014fd4ab146659f3626c68 Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Mon, 17 Mar 2025 15:15:03 +0000
Subject: [PATCH 0426/3886] mb/starlabs/starbook/mtl: Disconnect unused GPIOs

GPP_C03 and GPP_C04 are not used for the StarBook, so disconnect them.

Change-Id: I5e2c3da1198f064800f6f897583e507b6ae8a656
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86897
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/starlabs/starbook/variants/mtl/gpio.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/mainboard/starlabs/starbook/variants/mtl/gpio.c b/src/mainboard/starlabs/starbook/variants/mtl/gpio.c
index 946cff0a64..3d6212f293 100644
--- a/src/mainboard/starlabs/starbook/variants/mtl/gpio.c
+++ b/src/mainboard/starlabs/starbook/variants/mtl/gpio.c
@@ -88,9 +88,9 @@ const struct pad_config gpio_table[] = {
 	 *		WEAK INTERNAL PD 20K	*/
 	PAD_CFG_GPO(GPP_C02, 1, DEEP),
 	/* C03:	SML0_CLK			*/
-	PAD_CFG_NF(GPP_C03, NONE, DEEP, NF1),
+	PAD_NC(GPP_C03, NONE),
 	/* C04:	SML0_DATA			*/
-	PAD_CFG_NF(GPP_C04, NONE, DEEP, NF1),
+	PAD_NC(GPP_C04, NONE),
 	/* C05:	ESPI
 	 *		HIGH:	ENABLED
 	 *		LOW:	DISABLED

From cc6c6e10d373c4908f34ac8a16573f22610b9801 Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Mon, 17 Mar 2025 15:18:16 +0000
Subject: [PATCH 0427/3886] mb/starlabs/starbook/mtl: Set Power Delivery GPIOs
 to ignore standby

Set the PMC alert and SML Clock/Data pins to IOSTANDBY_IGNORE to ensure
that they're still operational in S3.

Change-Id: I1dd7a9410211c50cc171645f6db82b15c52ff7ce
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86898
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
---
 src/mainboard/starlabs/starbook/variants/mtl/gpio.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/src/mainboard/starlabs/starbook/variants/mtl/gpio.c b/src/mainboard/starlabs/starbook/variants/mtl/gpio.c
index 3d6212f293..b6ec3cd139 100644
--- a/src/mainboard/starlabs/starbook/variants/mtl/gpio.c
+++ b/src/mainboard/starlabs/starbook/variants/mtl/gpio.c
@@ -97,9 +97,9 @@ const struct pad_config gpio_table[] = {
 	 *		WEAK INTERNAL PD 20K	*/
 	PAD_CFG_GPO(GPP_C05, 1, DEEP),
 	/* C06:	SML1_CLK_USBC_PD_N		*/
-	PAD_CFG_NF(GPP_C06, NONE, DEEP, NF1),
+	PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_C06, NONE, DEEP, NF1),
 	/* C07:	SML1_DATA_USBC_PD_N		*/
-	PAD_CFG_NF(GPP_C07, NONE, DEEP, NF1),
+	PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_C07, NONE, DEEP, NF1),
 	/* C08:	SML1ALERT			*/
 	PAD_NC(GPP_C08, NONE),
 	/* C09:					*/
@@ -182,7 +182,7 @@ const struct pad_config gpio_table[] = {
 	/* A20:	M.2_CPU_SSD_RESET_N		*/
 	PAD_CFG_GPO(GPP_A20, 1, PLTRST),
 	/* A21:	I2C_PMC_PD_INT_N		*/
-	PAD_CFG_NF(GPP_A21, NONE, DEEP, NF1),
+	PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_A21, NONE, DEEP, NF1),
 	/* A22:					*/
 	PAD_NC(GPP_A22, NONE),
 	/* A23:					*/

From a6758353269464b52817ac38febc45c4cfb5a887 Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Mon, 17 Mar 2025 15:23:47 +0000
Subject: [PATCH 0428/3886] mb/starlabs/starbook/mtl: Adjust eSPI GPIO

Set the GPIO that enables eSPI to PLTRST to ensure that eSPI works
in S3.

Change-Id: Ibee64ccd9f21f33b764aacc4f97404ba56e5102e
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86899
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
---
 src/mainboard/starlabs/starbook/variants/mtl/gpio.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/mainboard/starlabs/starbook/variants/mtl/gpio.c b/src/mainboard/starlabs/starbook/variants/mtl/gpio.c
index b6ec3cd139..61e1c83d00 100644
--- a/src/mainboard/starlabs/starbook/variants/mtl/gpio.c
+++ b/src/mainboard/starlabs/starbook/variants/mtl/gpio.c
@@ -95,7 +95,7 @@ const struct pad_config gpio_table[] = {
 	 *		HIGH:	ENABLED
 	 *		LOW:	DISABLED
 	 *		WEAK INTERNAL PD 20K	*/
-	PAD_CFG_GPO(GPP_C05, 1, DEEP),
+	PAD_CFG_GPO(GPP_C05, 1, PLTRST),
 	/* C06:	SML1_CLK_USBC_PD_N		*/
 	PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_C06, NONE, DEEP, NF1),
 	/* C07:	SML1_DATA_USBC_PD_N		*/

From f811b1bb0e7745f7166f21eb485464b85a831a4d Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Mon, 17 Mar 2025 15:25:15 +0000
Subject: [PATCH 0429/3886] mb/starlabs/starbook/mtl: Don't configure eSPI
 GPIOs

Don't configure the eSPI GPIOs as they are configured automatically on
reset.

Change-Id: Icdd6e916571bad33404fa91a1e288e0a18d7778b
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86900
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
---
 src/mainboard/starlabs/starbook/variants/mtl/gpio.c | 7 -------
 1 file changed, 7 deletions(-)

diff --git a/src/mainboard/starlabs/starbook/variants/mtl/gpio.c b/src/mainboard/starlabs/starbook/variants/mtl/gpio.c
index 61e1c83d00..f45d7e2c20 100644
--- a/src/mainboard/starlabs/starbook/variants/mtl/gpio.c
+++ b/src/mainboard/starlabs/starbook/variants/mtl/gpio.c
@@ -140,19 +140,12 @@ const struct pad_config gpio_table[] = {
 	 * End:		GPP_A23
 	 */
 	/* A00:	ESPI_IO0_EC_R			*/
-	PAD_CFG_NF(GPP_A00, UP_20K, DEEP, NF1),
 	/* A01:	ESPI_IO1_EC_R			*/
-	PAD_CFG_NF(GPP_A01, UP_20K, DEEP, NF1),
 	/* A02:	ESPI_IO2_EC_R			*/
-	PAD_CFG_NF(GPP_A02, UP_20K, DEEP, NF1),
 	/* A03:	ESPI_IO3_EC_R			*/
-	PAD_CFG_NF(GPP_A03, UP_20K, DEEP, NF1),
 	/* A04:	ESPI_CS0_N			*/
-	PAD_CFG_NF(GPP_A04, UP_20K, DEEP, NF1),
 	/* A05:	ESPI_CLK_EC_R			*/
-	PAD_CFG_NF(GPP_A05, UP_20K, DEEP, NF1),
 	/* A06:	ESPI_RESET_N			*/
-	PAD_CFG_NF(GPP_A06, NONE, DEEP, NF1),
 	/* A07:					*/
 	PAD_NC(GPP_A07, NONE),
 	/* A08:					*/

From d6a4f4fb80a56b90b3fd47fd070b186214327879 Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Mon, 17 Mar 2025 15:26:08 +0000
Subject: [PATCH 0430/3886] mb/starlabs/starbook/mtl: Configure V GPIOs to work
 in S3

Configure all the controlling GPIOs to IOSTANDBY_IGNORE to
ensure they work in S3.

Change-Id: I1b34793a6437d2e489fca90be1f5d3e13ec7d559
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86901
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
---
 src/mainboard/starlabs/starbook/variants/mtl/gpio.c | 10 +++++-----
 1 file changed, 5 insertions(+), 5 deletions(-)

diff --git a/src/mainboard/starlabs/starbook/variants/mtl/gpio.c b/src/mainboard/starlabs/starbook/variants/mtl/gpio.c
index f45d7e2c20..f9efc62d50 100644
--- a/src/mainboard/starlabs/starbook/variants/mtl/gpio.c
+++ b/src/mainboard/starlabs/starbook/variants/mtl/gpio.c
@@ -29,17 +29,17 @@ const struct pad_config gpio_table[] = {
 	 * End:		GPP_V22
 	 */
 	/* V00:	PM_BATLOW_N			*/
-	PAD_CFG_NF(GPP_V00, NONE, DEEP, NF1),
+	PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_V00, NONE, DEEP, NF1),
 	/* V01:	CHG_ACOK			*/
-	PAD_CFG_NF(GPP_V01, NONE, DEEP, NF1),
+	PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_V01, NONE, DEEP, NF1),
 	/* V02:	PCIE_WAKE_LAN			*/
 	PAD_NC(GPP_V02, NONE),
 	/* V03:	EC_PWRBTN_N			*/
-	PAD_CFG_NF(GPP_V03, UP_20K, DEEP, NF1),
+	PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_V03, UP_20K, DEEP, NF1),
 	/* V04:	PM_SLP_S3_N			*/
-	PAD_NC(GPP_V04, NONE),
+	PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_V04, NONE, DEEP, NF1),
 	/* V05:	SLP S4#				*/
-	PAD_NC(GPP_V05, NONE),
+	PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_V05, NONE, DEEP, NF1),
 	/* V06:	GPD_6_SLP_A_N			*/
 	PAD_NC(GPP_V06, NONE),
 	/* V07:					*/

From fad6772611c25a714c718318270a3cc6c6a311ae Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Mon, 17 Mar 2025 15:30:33 +0000
Subject: [PATCH 0431/3886] mb/starlabs/starbook/mtl: Enable PMC IPC Mailbox

Introduce support for an IPC mailbox interface that lets the OS
exchange commands and responses with the Power Management Controller
(PMC) when needed.

Change-Id: I31ba44dc6fb848dda94321e1c17e64ddf6abe637
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86902
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/starlabs/starbook/Kconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/src/mainboard/starlabs/starbook/Kconfig b/src/mainboard/starlabs/starbook/Kconfig
index e8154fec50..d874e10aff 100644
--- a/src/mainboard/starlabs/starbook/Kconfig
+++ b/src/mainboard/starlabs/starbook/Kconfig
@@ -114,6 +114,7 @@ config BOARD_STARLABS_STARBOOK_MTL
 	select FSP_TYPE_IOT
 	select MAINBOARD_HAS_TPM2
 	select MEMORY_MAPPED_TPM
+	select PMC_IPC_ACPI_INTERFACE
 	select SOC_INTEL_COMMON_BLOCK_VTD
 	select SOC_INTEL_METEORLAKE
 	select SOC_INTEL_METEORLAKE_U_H

From c12c0232490349d83ba79ac2edf25b4885e55e19 Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Mon, 17 Mar 2025 15:31:13 +0000
Subject: [PATCH 0432/3886] mb/starlabs/starbook/mtl: Enable HDA DSP

Enable the  High Definition Audio Digital Signal Processor (HDA DSP)
to improve audio processing capabilities.

Change-Id: Ifcd107f0c889fc5210bdb8578d1df27b9e4414ff
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86903
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/starlabs/starbook/variants/mtl/devicetree.cb | 1 +
 1 file changed, 1 insertion(+)

diff --git a/src/mainboard/starlabs/starbook/variants/mtl/devicetree.cb b/src/mainboard/starlabs/starbook/variants/mtl/devicetree.cb
index 93c9b1ec91..cbda85d152 100644
--- a/src/mainboard/starlabs/starbook/variants/mtl/devicetree.cb
+++ b/src/mainboard/starlabs/starbook/variants/mtl/devicetree.cb
@@ -275,6 +275,7 @@ chip soc/intel/meteorlake
 		device ref hda		on
 			subsystemid 0x1e50 0x7038
 			register "pch_hda_sdi_enable[0]"		= "true"
+			register "pch_hda_dsp_enable"			= "true"
 			register "pch_hda_audio_link_hda_enable"	= "true"
 			register "pch_hda_idisp_codec_enable"		= "true"
 			register "pch_hda_idisp_link_frequency"		= "HDA_LINKFREQ_96MHZ"

From 025a5e86292795994ae755c9e72fdef6137fa778 Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Mon, 17 Mar 2025 15:45:17 +0000
Subject: [PATCH 0433/3886] mb/starlabs/starbook/mtl: Don't configure the MMIO
 size

Don't set this, so FSP will use the default auto setting, which
behaves better with various memory sizes.

Change-Id: I4d0bfd19af08ec127065f7ad5aaa51cb7e0ca2ac
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86905
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/starlabs/starbook/variants/mtl/romstage.c | 1 -
 1 file changed, 1 deletion(-)

diff --git a/src/mainboard/starlabs/starbook/variants/mtl/romstage.c b/src/mainboard/starlabs/starbook/variants/mtl/romstage.c
index addcae5915..7d9b9ae4fd 100644
--- a/src/mainboard/starlabs/starbook/variants/mtl/romstage.c
+++ b/src/mainboard/starlabs/starbook/variants/mtl/romstage.c
@@ -44,5 +44,4 @@ void mainboard_memory_init_params(FSPM_UPD *mupd)
 		mupd->FspmConfig.PcieRpEnableMask &= ~(1 << 8);
 
 	mupd->FspmConfig.PchHdaSubSystemIds = 0x70381e50;
-	mupd->FspmConfig.MmioSize = 0xb00;
 };

From 286eff6833b7ba0b75d34777de40430d1e6fd6b7 Mon Sep 17 00:00:00 2001
From: Yunlong Jia <yunlong.jia@ecs.corp-partner.google.com>
Date: Mon, 17 Mar 2025 08:58:13 +0000
Subject: [PATCH 0434/3886] mb/google/nissa/var/gothrax: Tune SX9324 P-sensor
 configuration
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Update SX9324 register settings based on tuning value from SEMTECH.
－　Adjust register reg_prox_ctrl0/reg_prox_ctrl6/ph01_proxraw_strength/ph23_proxraw_strength

BUG=b:295109511
BRANCH=None
TEST=Check register settings and confirm P-sensor function can work.

Signed-off-by: Yunlong Jia <yunlong.jia@ecs.corp-partner.google.com>
Change-Id: I1c27360de2d711810abdfd4ec95629ec7bba969b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86878
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Jayvik Desai <jayvik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 .../google/brya/variants/gothrax/overridetree.cb          | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/src/mainboard/google/brya/variants/gothrax/overridetree.cb b/src/mainboard/google/brya/variants/gothrax/overridetree.cb
index 32b5d348f9..e611b17315 100644
--- a/src/mainboard/google/brya/variants/gothrax/overridetree.cb
+++ b/src/mainboard/google/brya/variants/gothrax/overridetree.cb
@@ -287,13 +287,13 @@ chip soc/intel/alderlake
 				register "reg_afe_ctrl7" = "0x07"
 				register "reg_afe_ctrl8" = "0x12"
 				register "reg_afe_ctrl9" = "0x0f"
-				register "reg_prox_ctrl0" = "0x12"
+				register "reg_prox_ctrl0" = "0x09"
 				register "reg_prox_ctrl1" = "0x12"
 				register "reg_prox_ctrl2" = "0x90"
 				register "reg_prox_ctrl3" = "0x60"
 				register "reg_prox_ctrl4" = "0x0c"
 				register "reg_prox_ctrl5" = "0x12"
-				register "reg_prox_ctrl6" = "0x3c"
+				register "reg_prox_ctrl6" = "0x1e"
 				register "reg_prox_ctrl7" = "0x58"
 				register "reg_adv_ctrl0" = "0x00"
 				register "reg_adv_ctrl1" = "0x00"
@@ -324,8 +324,8 @@ chip soc/intel/alderlake
 				register "ph01_resolution" = "512"
 				register "ph23_resolution" = "1024"
 				register "startup_sensor" = "1"
-				register "ph01_proxraw_strength" = "2"
-				register "ph23_proxraw_strength" = "2"
+				register "ph01_proxraw_strength" = "1"
+				register "ph23_proxraw_strength" = "1"
 				register "avg_pos_strength" = "256"
 				register "cs_idle_sleep" = ""gnd""
 				register "int_comp_resistor" = ""lowest""

From 0b03ecbc44610398576c39ee8b86ea4647b7782b Mon Sep 17 00:00:00 2001
From: Patrick Rudolph <patrick.rudolph@9elements.com>
Date: Wed, 12 Mar 2025 08:31:56 +0100
Subject: [PATCH 0435/3886] soc/amd/glinda: Fix PSP_SOFTFUSE_BITS

The PSP_SOFTFUSE_BITs were probably copy&pasted during initial
SoC bringup and need to be adjusted:

* Drop PSP_SOFTFUSE_BIT BIT28 as it causes PSP to hang.
* Drop PSP_SOFTFUSE_BIT BIT34 as it's not required.

This also moves coreboot closer to the UEFI reference firmware.

Document #55758 Rev. 2.04
TEST: Booted on amd/birman_plus with default PSP_SOFTFUSE_BITS.

Change-Id: Ic7b2b0ac01fe0ac0ed2535254f242a8068f9b02a
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86840
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ana Carolina Cabral <ana.cpmelo95@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Andy Ebrahiem <ahmet.ebrahiem@9elements.com>
---
 src/soc/amd/glinda/Kconfig | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/soc/amd/glinda/Kconfig b/src/soc/amd/glinda/Kconfig
index 1bd5b2f179..a0d64c62d7 100644
--- a/src/soc/amd/glinda/Kconfig
+++ b/src/soc/amd/glinda/Kconfig
@@ -356,7 +356,7 @@ config PSP_WHITELIST_FILE
 
 config PSP_SOFTFUSE_BITS
 	string "PSP Soft Fuse bits to enable"
-	default "34 28 6"
+	default "6"
 	help
 	  Space separated list of Soft Fuse bits to enable.
 	  Bit 0:  Enable secure debug (Set by PSP_UNLOCK_SECURE_DEBUG)

From 05aa75bd3d2744205d0b9658d2b5dede3b19f631 Mon Sep 17 00:00:00 2001
From: Bora Guvendik <bora.guvendik@intel.com>
Date: Tue, 11 Mar 2025 14:46:39 -0700
Subject: [PATCH 0436/3886] mb/intel/ptlrvp: Add PTL-P RVP and GCS board IDs
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

This commit introduces new board ID definitions for PTL-P and GCS in the
PTLRVP mainboard code. The changes involve updating the `romstage.c` and
`memory.c` files to handle these new board IDs, ensuring that memory
configuration is correctly initialized based on the detected board
type.

Change-Id: Ia354db27a0124dcde2825e7a05a59ef5d539c4ef
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86833
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
---
 src/mainboard/intel/ptlrvp/romstage.c              | 14 +++++++++++++-
 .../baseboard/include/baseboard/variants.h         |  7 +++++++
 .../intel/ptlrvp/variants/ptlrvp/memory.c          | 14 +++++++++++++-
 3 files changed, 33 insertions(+), 2 deletions(-)

diff --git a/src/mainboard/intel/ptlrvp/romstage.c b/src/mainboard/intel/ptlrvp/romstage.c
index 7b56e28e3c..b6e3681891 100644
--- a/src/mainboard/intel/ptlrvp/romstage.c
+++ b/src/mainboard/intel/ptlrvp/romstage.c
@@ -1,6 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0-or-later */
 
 #include <baseboard/variants.h>
+#include <ec/intel/board_id.h>
 #include <fsp/api.h>
 #include <soc/romstage.h>
 #include <string.h>
@@ -20,6 +21,7 @@ void mainboard_memory_init_params(FSPM_UPD *memupd)
 {
 	const struct pad_config *pads;
 	size_t pads_num;
+	int board_id = get_rvp_board_id();
 	const struct mb_cfg *mem_config = variant_memory_params();
 	bool half_populated = variant_is_half_populated();
 	struct mem_spd spd_info;
@@ -32,5 +34,15 @@ void mainboard_memory_init_params(FSPM_UPD *memupd)
 	memset(&spd_info, 0, sizeof(spd_info));
 	variant_get_spd_info(&spd_info);
 
-	memcfg_init(memupd, mem_config, &spd_info, half_populated);
+	switch (board_id) {
+	case PTLP_LP5_T3_RVP:
+	case PTLP_LP5_T4_RVP:
+	case GCS_32GB:
+	case GCS_64GB:
+		memcfg_init(memupd, mem_config, &spd_info, half_populated);
+		break;
+	default:
+		die("Unknown board id = 0x%x\n", board_id);
+		break;
+	}
 }
diff --git a/src/mainboard/intel/ptlrvp/variants/baseboard/include/baseboard/variants.h b/src/mainboard/intel/ptlrvp/variants/baseboard/include/baseboard/variants.h
index 2a70408e0d..5a59f1ff7c 100644
--- a/src/mainboard/intel/ptlrvp/variants/baseboard/include/baseboard/variants.h
+++ b/src/mainboard/intel/ptlrvp/variants/baseboard/include/baseboard/variants.h
@@ -9,6 +9,13 @@
 #include <stdint.h>
 #include <vendorcode/google/chromeos/chromeos.h>
 
+enum ptl_boardid {
+	PTLP_LP5_T3_RVP = 0x01,
+	PTLP_LP5_T4_RVP = 0x03,
+	GCS_32GB = 0x11,
+	GCS_64GB = 0x12,
+};
+
 /* The next set of functions return the gpio table and fill in the number of entries for
  * each table.
  */
diff --git a/src/mainboard/intel/ptlrvp/variants/ptlrvp/memory.c b/src/mainboard/intel/ptlrvp/variants/ptlrvp/memory.c
index e0908adabd..7fe2fcbe95 100644
--- a/src/mainboard/intel/ptlrvp/variants/ptlrvp/memory.c
+++ b/src/mainboard/intel/ptlrvp/variants/ptlrvp/memory.c
@@ -1,6 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0-or-later */
 
 #include <baseboard/variants.h>
+#include <ec/intel/board_id.h>
 #include <soc/romstage.h>
 #include <soc/meminit.h>
 
@@ -66,7 +67,18 @@ static const struct mb_cfg lp5_mem_config = {
 
 const struct mb_cfg *variant_memory_params(void)
 {
-	return &lp5_mem_config;
+	int board_id = get_rvp_board_id();
+
+	switch (board_id) {
+	case PTLP_LP5_T3_RVP:
+	case PTLP_LP5_T4_RVP:
+	case GCS_32GB:
+	case GCS_64GB:
+		return &lp5_mem_config;
+	default:
+		die("Unknown board id = 0x%x\n", board_id);
+		break;
+	}
 }
 
 void variant_get_spd_info(struct mem_spd *spd_info)

From af26e5e24e428bfa9b62da7d5ea17fbecb973d13 Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Tue, 9 Apr 2024 10:38:36 -0500
Subject: [PATCH 0437/3886] mb/google/guybrush/var/nipperkin: Mark fingerprint
 reader as hidden

Windows doesn't have / will likely never have a signed driver for the
FPR, so set the device status as hidden so it will not appear as an
unknown device in Windows Device Manager. Linux does not check/care
about the ACPI device status.

TEST=build/boot Win11 on google/guybrush (nipperkin), verify FPR does
not show up as unknown device under Device Manager.

Change-Id: I3eac631aebb26ec1c375b436e088be522d659338
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86847
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 .../google/guybrush/variants/nipperkin/overridetree.cb          | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/mainboard/google/guybrush/variants/nipperkin/overridetree.cb b/src/mainboard/google/guybrush/variants/nipperkin/overridetree.cb
index 02444aa59a..f9845b701b 100644
--- a/src/mainboard/google/guybrush/variants/nipperkin/overridetree.cb
+++ b/src/mainboard/google/guybrush/variants/nipperkin/overridetree.cb
@@ -351,7 +351,7 @@ chip soc/amd/cezanne
 			register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPIO_11)"
 			register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_3)"
 			register "enable_delay_ms" = "3"
-			device generic 0 alias fpmcu on
+			device generic 0 alias fpmcu hidden
 				probe FP FP_PRESENT
 			end
 		end

From 86baf7aee68c387ca7dc8770c857a215aceaf92c Mon Sep 17 00:00:00 2001
From: Subrata Banik <subratabanik@google.com>
Date: Sat, 15 Mar 2025 19:08:02 +0530
Subject: [PATCH 0438/3886] drivers/intel/fsp2_0: Use consistent spacing in BMP
 color translation
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

This patch corrects spacing around assignment operators in the
`fill_blt_buffer` to comply with coding style guidelines, specifically
within the BMP color translation logic for 1/4/8/24/32-bit images.

Change-Id: Ia243d11568ec4c3d1108ff60289743919394aa32
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86860
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/drivers/intel/fsp2_0/fsp_gop_blt.c | 29 ++++++++++++++------------
 1 file changed, 16 insertions(+), 13 deletions(-)

diff --git a/src/drivers/intel/fsp2_0/fsp_gop_blt.c b/src/drivers/intel/fsp2_0/fsp_gop_blt.c
index 8292b3b68d..bbeece4e97 100644
--- a/src/drivers/intel/fsp2_0/fsp_gop_blt.c
+++ b/src/drivers/intel/fsp2_0/fsp_gop_blt.c
@@ -166,9 +166,12 @@ static void *fill_blt_buffer(efi_bmp_image_header *header,
 			/* Translate 1-bit (2 colors) BMP to 24-bit color */
 			case 1:
 				for (index = 0; index < 8 && width < header->PixelWidth; index++) {
-					gop_blt->Red   = bmp_color_map[((*bmp_image) >> (7 - index)) & 0x1].Red;
-					gop_blt->Green = bmp_color_map[((*bmp_image) >> (7 - index)) & 0x1].Green;
-					gop_blt->Blue  = bmp_color_map[((*bmp_image) >> (7 - index)) & 0x1].Blue;
+					gop_blt->Red = bmp_color_map[((*bmp_image) >> (7 - index))
+									 & 0x1].Red;
+					gop_blt->Green = bmp_color_map[((*bmp_image) >> (7 - index))
+									 & 0x1].Green;
+					gop_blt->Blue = bmp_color_map[((*bmp_image) >> (7 - index))
+									 & 0x1].Blue;
 					gop_blt++;
 					width++;
 				}
@@ -179,38 +182,38 @@ static void *fill_blt_buffer(efi_bmp_image_header *header,
 			/* Translate 4-bit (16 colors) BMP Palette to 24-bit color */
 			case 4:
 				index = (*bmp_image) >> 4;
-				gop_blt->Red   = bmp_color_map[index].Red;
+				gop_blt->Red = bmp_color_map[index].Red;
 				gop_blt->Green = bmp_color_map[index].Green;
-				gop_blt->Blue  = bmp_color_map[index].Blue;
+				gop_blt->Blue = bmp_color_map[index].Blue;
 				if (width < (header->PixelWidth - 1)) {
 					gop_blt++;
 					width++;
 					index = (*bmp_image) & 0x0f;
-					gop_blt->Red   = bmp_color_map[index].Red;
+					gop_blt->Red = bmp_color_map[index].Red;
 					gop_blt->Green = bmp_color_map[index].Green;
-					gop_blt->Blue  = bmp_color_map[index].Blue;
+					gop_blt->Blue = bmp_color_map[index].Blue;
 				}
 				break;
 
 			/* Translate 8-bit (256 colors) BMP Palette to 24-bit color */
 			case 8:
-				gop_blt->Red   = bmp_color_map[*bmp_image].Red;
+				gop_blt->Red = bmp_color_map[*bmp_image].Red;
 				gop_blt->Green = bmp_color_map[*bmp_image].Green;
-				gop_blt->Blue  = bmp_color_map[*bmp_image].Blue;
+				gop_blt->Blue = bmp_color_map[*bmp_image].Blue;
 				break;
 
 			/* For 24-bit BMP */
 			case 24:
-				gop_blt->Blue  = *bmp_image++;
+				gop_blt->Blue = *bmp_image++;
 				gop_blt->Green = *bmp_image++;
-				gop_blt->Red   = *bmp_image;
+				gop_blt->Red = *bmp_image;
 				break;
 
 			/* Convert 32 bit to 24bit bmp - just ignore the final byte of each pixel */
 			case 32:
-				gop_blt->Blue  = *bmp_image++;
+				gop_blt->Blue = *bmp_image++;
 				gop_blt->Green = *bmp_image++;
-				gop_blt->Red   = *bmp_image++;
+				gop_blt->Red = *bmp_image++;
 				break;
 
 			/* Other bit format of BMP is not supported. */

From cadfb07dbecffb9b1808d313902d291f8326d9f8 Mon Sep 17 00:00:00 2001
From: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com>
Date: Tue, 18 Mar 2025 10:00:17 +0900
Subject: [PATCH 0439/3886] mb/nissa/var/meliks: Update GPP_E7 strap
 configuration

Meliks uses GPP_E7 to determine the channel count of the RAM chip in
romstage, move its configuration to early_gpio_table from
override_gpio_table to be ready to use at that moment.

And early stage meliks boards didn't implement the GPP_E7 strap but
leaved it as NC. All of them used two channel ram chip, so add DN_20K
for them not to disable any memory channel. Otherwise, they might not
be able to boot since memory training will be failed due to the
incorrect memory channel information.

BUG=None
BRANCH=nissa
TEST=FW_NAME=meliks emerge-nissa coreboot

Change-Id: Icf71c3a1f24d3dcbff6ba5e646e9f805144add71
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86908
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Jayvik Desai <jayvik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
---
 src/mainboard/google/brya/variants/meliks/gpio.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/mainboard/google/brya/variants/meliks/gpio.c b/src/mainboard/google/brya/variants/meliks/gpio.c
index 6e11263075..d13ac2de9f 100644
--- a/src/mainboard/google/brya/variants/meliks/gpio.c
+++ b/src/mainboard/google/brya/variants/meliks/gpio.c
@@ -22,8 +22,6 @@ static const struct pad_config override_gpio_table[] = {
 	/* D8  : SD_CLKREQ_ODL ==> NC */
 	PAD_NC(GPP_D8, NONE),
 
-	/* E7 : NC ==> GPP_E7_STRAP */
-	PAD_CFG_GPI_LOCK(GPP_E7, NONE, LOCK_CONFIG),
 	/* E14 : EDP_HPD ==> NC */
 	PAD_NC(GPP_E14, NONE),
 	/* E20 : HDMI_DDC_SCL ==> NC */
@@ -82,6 +80,8 @@ static const struct pad_config override_gpio_table[] = {
 static const struct pad_config early_gpio_table[] = {
 	/* A13 : GPP_A13 ==> GSC_SOC_INT_ODL */
 	PAD_CFG_GPI_APIC(GPP_A13, NONE, PLTRST, LEVEL, INVERT),
+	/* E7 : NC ==> GPP_E7_STRAP */
+	PAD_CFG_GPI_LOCK(GPP_E7, DN_20K, LOCK_CONFIG),
 	/* E12 : THC0_SPI1_IO1 ==> SOC_WP_OD */
 	PAD_CFG_GPI_GPIO_DRIVER(GPP_E12, NONE, DEEP),
 	/* F18 : THC1_SPI2_INT# ==> EC_IN_RW_OD */

From 0b53a60d4d87d2b16066b8bb8de0c83580346316 Mon Sep 17 00:00:00 2001
From: Lu Tang <lu.tang@mediatek.corp-partner.google.com>
Date: Wed, 12 Mar 2025 20:57:42 +0800
Subject: [PATCH 0440/3886] soc/mediatek/mt8196: Disable PMIF reset after
 enable

Currently, we don't explicitly disable the PMIF and SPMI resets after
the reset is completed, causing them to remain asserted for
approximately 0.5ms. That would cause the DUT to hang during PMIF
initialization (pmif_spmi_init) when using non-serial firmware.

To fix this issue, explicitly disable the PMIF and SPMI resets
immediately after the reset.

BRANCH=rauru
BUG=b:341054056
TEST=Build pass, non-serial firmware boot ok.

Signed-off-by: Lu Tang <lu.tang@mediatek.corp-partner.google.com>
Change-Id: Ic903ddd893470cd46dbfed9c3faa9c2a9e50c904
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86859
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/soc/mediatek/mt8196/pmif_clk.c | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/src/soc/mediatek/mt8196/pmif_clk.c b/src/soc/mediatek/mt8196/pmif_clk.c
index 2c59dc5221..cf41219ee0 100644
--- a/src/soc/mediatek/mt8196/pmif_clk.c
+++ b/src/soc/mediatek/mt8196/pmif_clk.c
@@ -239,11 +239,12 @@ int pmif_clk_init(void)
 	/* [12]: pmifspi_m_rst_b [13]: pmifspi_p_rst_b*/
 	SET32_BITFIELDS(&mtk_rug->wdt_vlp_swsysrst0, UNLOCK_KEY, 0x88, PMIFSPMI_RST_B, 0x3,
 			PMIF_RST_B, 0x3);
-	SET32_BITFIELDS(&mtk_rug->wdt_vlp_swsysrst0, UNLOCK_KEY, 0x88);
+	SET32_BITFIELDS(&mtk_rug->wdt_vlp_swsysrst0, UNLOCK_KEY, 0x88, PMIFSPMI_RST_B, 0x0,
+			PMIF_RST_B, 0x0);
 
 	/* [0]: tia_grst_b */
 	SET32_BITFIELDS(&mtk_rug->wdt_vlp_swsysrst1, UNLOCK_KEY, 0x88, TIA_GRST_B, 0x1);
-	SET32_BITFIELDS(&mtk_rug->wdt_vlp_swsysrst1, UNLOCK_KEY, 0x88);
+	SET32_BITFIELDS(&mtk_rug->wdt_vlp_swsysrst1, UNLOCK_KEY, 0x88, TIA_GRST_B, 0x0);
 
 	printk(BIOS_INFO, "%s: done\n", __func__);
 

From 0f1a18999c8dedf9f9ca2121a4bbb902ad5feee7 Mon Sep 17 00:00:00 2001
From: Jarried Lin <jarried.lin@mediatek.corp-partner.google.com>
Date: Mon, 17 Mar 2025 16:42:22 +0800
Subject: [PATCH 0441/3886] Revert "soc/mediatek/mt8196: Delay 0.5ms after
 enabling PMIF SPMI SW interface"

This reverts commit c476c4d5b9f53f01c0f0b9673d3b9f0a29a6ae64.

Reason for revert: Previously in CB:85799, we added a 0.5ms delay as a
workaround to solve the boot hang issue of non-serial firmware. Now that
the root cause has been identified and fixed in CB:86859, we can revert
the workaround.

Original change's description:
CB:85799, commit c476c4d5b9f5 ("soc/mediatek/mt8196: Delay 0.5ms after
enabling PMIF SPMI SW interface")

BRANCH=rauru
BUG=b:341054056
TEST=Build pass.

Change-Id: I0abdcae95924c4d3197496c14d20502b08938d76
Signed-off-by: Jarried Lin <jarried.lin@mediatek.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86858
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
---
 src/soc/mediatek/mt8196/pmif_spmi.c | 2 --
 1 file changed, 2 deletions(-)

diff --git a/src/soc/mediatek/mt8196/pmif_spmi.c b/src/soc/mediatek/mt8196/pmif_spmi.c
index cb78249662..665c64c7f6 100644
--- a/src/soc/mediatek/mt8196/pmif_spmi.c
+++ b/src/soc/mediatek/mt8196/pmif_spmi.c
@@ -1,7 +1,6 @@
 /* SPDX-License-Identifier: GPL-2.0-only OR MIT */
 
 #include <console/console.h>
-#include <delay.h>
 #include <device/mmio.h>
 #include <gpio.h>
 #include <soc/addressmap.h>
@@ -286,7 +285,6 @@ static void pmif_spmi_enable_swinf(struct pmif *arb)
 {
 	write32(&arb->mtk_pmif->inf_en, PMIF_SPMI_SW_CHAN);
 	write32(&arb->mtk_pmif->arb_en, PMIF_SPMI_SW_CHAN);
-	udelay(500);
 	printk(BIOS_INFO, "%s done\n", __func__);
 }
 

From b9565f7817f76fca0f409f82015006c400bbac8d Mon Sep 17 00:00:00 2001
From: David Wu <david_wu@quanta.corp-partner.google.com>
Date: Wed, 19 Mar 2025 18:32:07 +0800
Subject: [PATCH 0442/3886] mb/google/nissa/var/dirks: Enable PCIE port 7 for
 Ethernet

Enable PCIE port 7 using clk 3 for RTL8111H Ethernet.

BUG=b:388117663
TEST=build pass and insure LAN function work properly

Change-Id: I60c30f207aa92ba9f52da0b95b647307a73e9d13
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86930
Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
---
 src/mainboard/google/brya/Kconfig                  |  3 +++
 .../google/brya/variants/dirks/overridetree.cb     | 14 ++++++++++++++
 2 files changed, 17 insertions(+)

diff --git a/src/mainboard/google/brya/Kconfig b/src/mainboard/google/brya/Kconfig
index 6dc6bb4697..9808a327b5 100644
--- a/src/mainboard/google/brya/Kconfig
+++ b/src/mainboard/google/brya/Kconfig
@@ -223,6 +223,9 @@ config BOARD_GOOGLE_CROTA
 
 config BOARD_GOOGLE_DIRKS
 	select BOARD_GOOGLE_BASEBOARD_NISSA
+	select RT8168_GEN_ACPI_POWER_RESOURCE
+	select RT8168_GET_MAC_FROM_VPD
+	select RT8168_SET_LED_MODE
 	select SOC_INTEL_TWINLAKE
 	select SYSTEM_TYPE_MINIPC
 
diff --git a/src/mainboard/google/brya/variants/dirks/overridetree.cb b/src/mainboard/google/brya/variants/dirks/overridetree.cb
index 8b7bc438fe..e1f6a4bd58 100644
--- a/src/mainboard/google/brya/variants/dirks/overridetree.cb
+++ b/src/mainboard/google/brya/variants/dirks/overridetree.cb
@@ -222,6 +222,20 @@ chip soc/intel/alderlake
 				device generic 0 on end
 			end
 		end
+		device ref pcie_rp7 on
+			# Enable PCIE 7 using clk 3
+			register "pch_pcie_rp[PCH_RP(7)]" = "{
+				.clk_src = 3,
+				.clk_req = 3,
+				.flags = PCIE_RP_LTR | PCIE_RP_AER,
+			}"
+			chip drivers/net
+				register "customized_leds" = "0x05af"
+				register "wake" = "GPE0_DW2_14"	# GPP_F14
+				register "device_index" = "0"
+				device pci 00.0 on end
+			end
+		end # RTL8111H Ethernet NIC
 		device ref pcie_rp11 on
 			# Enable wlan PCIe 11 using clk 2
 			probe WIFI_TYPE WIFI_PCIE

From 5ac7f635a5cf0609d47090a534a1f951e58f7da6 Mon Sep 17 00:00:00 2001
From: David Wu <david_wu@quanta.corp-partner.google.com>
Date: Thu, 20 Mar 2025 09:17:09 +0800
Subject: [PATCH 0443/3886] mb/google/nissa/var/dirks: Correct PCIe RP 11 for
 WIFI7

According the schematic to correct PCIe RP 11 for WIFI7.

BUG=b:388117663
TEST=build pass and insure WLAN function work properly

Change-Id: I84e9fc707c23099d7cd7ea2d8acde1043325f06b
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86934
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
---
 src/mainboard/google/brya/variants/dirks/overridetree.cb | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/mainboard/google/brya/variants/dirks/overridetree.cb b/src/mainboard/google/brya/variants/dirks/overridetree.cb
index e1f6a4bd58..94c2457b65 100644
--- a/src/mainboard/google/brya/variants/dirks/overridetree.cb
+++ b/src/mainboard/google/brya/variants/dirks/overridetree.cb
@@ -240,7 +240,7 @@ chip soc/intel/alderlake
 			# Enable wlan PCIe 11 using clk 2
 			probe WIFI_TYPE WIFI_PCIE
 			probe WIFI_TYPE WIFI_ALL
-			register "pch_pcie_rp[PCH_RP(10)]" = "{
+			register "pch_pcie_rp[PCH_RP(11)]" = "{
 				.clk_src = 2,
 				.clk_req = 2,
 				.flags = PCIE_RP_LTR | PCIE_RP_AER,

From b5dea9fa999ac9f01b15cf2bc5a9ee05695d5ee1 Mon Sep 17 00:00:00 2001
From: Ian Feng <ian_feng@compal.corp-partner.google.com>
Date: Wed, 19 Mar 2025 15:39:24 +0800
Subject: [PATCH 0444/3886] mb/google/fatcat/var/francka: Add Write Protect
 GPIO to cros_gpios

This enables the utility crossystem to access WP GPIO.

BUG=b:399511940
TEST= wpsw_cur in crossystem reads the correct gpio

Change-Id: Ided919920dff74c49ce2f718f845ae5a1117a89b
Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86923
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Pranava Y N <pranavayn@google.com>
---
 src/mainboard/google/fatcat/variants/francka/gpio.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/src/mainboard/google/fatcat/variants/francka/gpio.c b/src/mainboard/google/fatcat/variants/francka/gpio.c
index f2868fc638..73898dcff7 100644
--- a/src/mainboard/google/fatcat/variants/francka/gpio.c
+++ b/src/mainboard/google/fatcat/variants/francka/gpio.c
@@ -454,6 +454,7 @@ static const struct cros_gpio cros_gpios[] = {
 	CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE1_NAME),
 	CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE2_NAME),
 	CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE3_NAME),
+	CROS_GPIO_WP_AH(GPIO_PCH_WP, CROS_GPIO_DEVICE1_NAME),
 };
 
 DECLARE_CROS_GPIOS(cros_gpios);

From 57a3d2d183bcb526ee23d4e56b744c2ff29ec7bb Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Mon, 17 Mar 2025 15:44:08 +0000
Subject: [PATCH 0445/3886] mb/starlabs/starbook/mtl: Rename memory struct

`ddr5_spd_info` is a better name for DDR5 memory parameters.

Change-Id: If54718592950164569fccee6e8b7d53803310de0
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86904
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
---
 src/mainboard/starlabs/starbook/variants/mtl/romstage.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/mainboard/starlabs/starbook/variants/mtl/romstage.c b/src/mainboard/starlabs/starbook/variants/mtl/romstage.c
index 7d9b9ae4fd..3e5291f86d 100644
--- a/src/mainboard/starlabs/starbook/variants/mtl/romstage.c
+++ b/src/mainboard/starlabs/starbook/variants/mtl/romstage.c
@@ -22,7 +22,7 @@ void mainboard_memory_init_params(FSPM_UPD *mupd)
 
 	const bool half_populated = false;
 
-	const struct mem_spd ddr4_spd_info = {
+	const struct mem_spd ddr5_spd_info = {
 		.topo = MEM_TOPO_DIMM_MODULE,
 		.smbus = {
 			[0] = {
@@ -34,7 +34,7 @@ void mainboard_memory_init_params(FSPM_UPD *mupd)
 		},
 	};
 
-	memcfg_init(mupd, &mem_config, &ddr4_spd_info, half_populated);
+	memcfg_init(mupd, &mem_config, &ddr5_spd_info, half_populated);
 
 	const uint8_t vtd = get_uint_option("vtd", 1);
 	mupd->FspmConfig.VtdDisable = !vtd;

From b2a0347cf4d475c08a10865103f8df9eb1ab03af Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Tue, 18 Mar 2025 13:15:04 +0000
Subject: [PATCH 0446/3886] mb/starlabs/starbook/mtl: Remove unnecessary op

The default for DQS interleaving is 0, so don't set it to 0.

Change-Id: I5f828aa3a28947c2f88eaf36cc7bc8ad68812cb2
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86911
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
---
 src/mainboard/starlabs/starbook/variants/mtl/romstage.c | 3 ---
 1 file changed, 3 deletions(-)

diff --git a/src/mainboard/starlabs/starbook/variants/mtl/romstage.c b/src/mainboard/starlabs/starbook/variants/mtl/romstage.c
index 3e5291f86d..b593a8cf63 100644
--- a/src/mainboard/starlabs/starbook/variants/mtl/romstage.c
+++ b/src/mainboard/starlabs/starbook/variants/mtl/romstage.c
@@ -11,9 +11,6 @@ void mainboard_memory_init_params(FSPM_UPD *mupd)
 		.type = MEM_TYPE_DDR5,
 		.ect = true,
 		.UserBd = BOARD_TYPE_ULT_ULX,
-		.ddr_config = {
-			.dq_pins_interleaved = false,
-		},
 		.rcomp = {
 			.resistor = 100,
 			.targets = {70, 30, 25, 25, 25},

From 2337ec2b57cd63e6b48904d662528e6ab3bdd580 Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Tue, 18 Mar 2025 13:16:03 +0000
Subject: [PATCH 0447/3886] mb/starlabs/starbook/mtl: Don't set rcomp config

Leave the rcomp config empty so that 0's are passed to FSP; this
allows FSP to figure out the correct settings to use.

Change-Id: Id7d44984c5ecfd0307d207d997248e88e1bd6eb4
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86912
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
---
 src/mainboard/starlabs/starbook/variants/mtl/romstage.c | 4 ----
 1 file changed, 4 deletions(-)

diff --git a/src/mainboard/starlabs/starbook/variants/mtl/romstage.c b/src/mainboard/starlabs/starbook/variants/mtl/romstage.c
index b593a8cf63..acd384e62c 100644
--- a/src/mainboard/starlabs/starbook/variants/mtl/romstage.c
+++ b/src/mainboard/starlabs/starbook/variants/mtl/romstage.c
@@ -11,10 +11,6 @@ void mainboard_memory_init_params(FSPM_UPD *mupd)
 		.type = MEM_TYPE_DDR5,
 		.ect = true,
 		.UserBd = BOARD_TYPE_ULT_ULX,
-		.rcomp = {
-			.resistor = 100,
-			.targets = {70, 30, 25, 25, 25},
-		}
 	};
 
 	const bool half_populated = false;

From 3848debd52f5e88f14f4c41c0a25c87f09f8e747 Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Tue, 18 Mar 2025 13:17:34 +0000
Subject: [PATCH 0448/3886] mb/starlabs/starbook/mtl: Deselect FSP_TYPE_IOT

Deselect this so that a local copy of PR3 can be used.

Change-Id: I7efe35457186bca43af3e5b7557cbd3be6cecbb7
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86913
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/starlabs/starbook/Kconfig | 1 -
 1 file changed, 1 deletion(-)

diff --git a/src/mainboard/starlabs/starbook/Kconfig b/src/mainboard/starlabs/starbook/Kconfig
index d874e10aff..44e2355b32 100644
--- a/src/mainboard/starlabs/starbook/Kconfig
+++ b/src/mainboard/starlabs/starbook/Kconfig
@@ -111,7 +111,6 @@ config BOARD_STARLABS_STARBOOK_MTL
 	select EC_STARLABS_MAX_CHARGE
 	select EC_STARLABS_MERLIN
 	select EC_STARLABS_NEED_ITE_BIN
-	select FSP_TYPE_IOT
 	select MAINBOARD_HAS_TPM2
 	select MEMORY_MAPPED_TPM
 	select PMC_IPC_ACPI_INTERFACE

From c8e6ca1d812d9039f8c44830dd1ecc5693a9d1bf Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Tue, 18 Mar 2025 13:30:37 +0000
Subject: [PATCH 0449/3886] mb/starlabs/*: Disable HPD for USB Type-C ports

Display-Alt Mode doesn't require HPD to be set here, so remove it.

Change-Id: I6e03c481584ff2b0bbb06d1d21f31fd0db4ecb27
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86915
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/starlabs/byte_adl/variants/mk_ii/devicetree.cb    | 1 -
 src/mainboard/starlabs/starbook/variants/adl/devicetree.cb      | 1 -
 src/mainboard/starlabs/starbook/variants/adl_n/devicetree.cb    | 1 -
 src/mainboard/starlabs/starbook/variants/rpl/devicetree.cb      | 1 -
 src/mainboard/starlabs/starfighter/variants/rpl/devicetree.cb   | 1 -
 src/mainboard/starlabs/starlite_adl/variants/mk_v/devicetree.cb | 2 --
 6 files changed, 7 deletions(-)

diff --git a/src/mainboard/starlabs/byte_adl/variants/mk_ii/devicetree.cb b/src/mainboard/starlabs/byte_adl/variants/mk_ii/devicetree.cb
index 4ff591d5f9..25ae635491 100644
--- a/src/mainboard/starlabs/byte_adl/variants/mk_ii/devicetree.cb
+++ b/src/mainboard/starlabs/byte_adl/variants/mk_ii/devicetree.cb
@@ -22,7 +22,6 @@ chip soc/intel/alderlake
 			register "ddi_ports_config" = "{
 				[DDI_PORT_A]			= DDI_ENABLE_HPD,
 				[DDI_PORT_B]			= DDI_ENABLE_HPD | DDI_ENABLE_DDC,
-				[DDI_PORT_1]			= DDI_ENABLE_HPD,
 			}"
 		end
 		device ref tcss_xhci	on
diff --git a/src/mainboard/starlabs/starbook/variants/adl/devicetree.cb b/src/mainboard/starlabs/starbook/variants/adl/devicetree.cb
index e63d0f8558..dd6500ef73 100644
--- a/src/mainboard/starlabs/starbook/variants/adl/devicetree.cb
+++ b/src/mainboard/starlabs/starbook/variants/adl/devicetree.cb
@@ -34,7 +34,6 @@ chip soc/intel/alderlake
 			register "ddi_ports_config" = "{
 				[DDI_PORT_A]				= DDI_ENABLE_HPD,
 				[DDI_PORT_B]				= DDI_ENABLE_HPD | DDI_ENABLE_DDC,
-				[DDI_PORT_1]				= DDI_ENABLE_HPD,
 			}"
 		end
 		device ref gna		on  end
diff --git a/src/mainboard/starlabs/starbook/variants/adl_n/devicetree.cb b/src/mainboard/starlabs/starbook/variants/adl_n/devicetree.cb
index 0140f252de..4f6368a428 100644
--- a/src/mainboard/starlabs/starbook/variants/adl_n/devicetree.cb
+++ b/src/mainboard/starlabs/starbook/variants/adl_n/devicetree.cb
@@ -54,7 +54,6 @@ chip soc/intel/alderlake
 			register "ddi_ports_config" = "{
 				[DDI_PORT_A]				= DDI_ENABLE_HPD,
 				[DDI_PORT_B]				= DDI_ENABLE_HPD | DDI_ENABLE_DDC,
-				[DDI_PORT_1]				= DDI_ENABLE_HPD,
 			}"
 		end
 		device ref gna	on  end
diff --git a/src/mainboard/starlabs/starbook/variants/rpl/devicetree.cb b/src/mainboard/starlabs/starbook/variants/rpl/devicetree.cb
index abf9802122..bd22901f01 100644
--- a/src/mainboard/starlabs/starbook/variants/rpl/devicetree.cb
+++ b/src/mainboard/starlabs/starbook/variants/rpl/devicetree.cb
@@ -36,7 +36,6 @@ chip soc/intel/alderlake
 			register "ddi_ports_config" = "{
 				[DDI_PORT_A]				= DDI_ENABLE_HPD,
 				[DDI_PORT_B]				= DDI_ENABLE_HPD | DDI_ENABLE_DDC,
-				[DDI_PORT_1]				= DDI_ENABLE_HPD,
 			}"
 		end
 		device ref pcie4_0	on				# SSD x4
diff --git a/src/mainboard/starlabs/starfighter/variants/rpl/devicetree.cb b/src/mainboard/starlabs/starfighter/variants/rpl/devicetree.cb
index cb5c8767d3..479e05e4f8 100644
--- a/src/mainboard/starlabs/starfighter/variants/rpl/devicetree.cb
+++ b/src/mainboard/starlabs/starfighter/variants/rpl/devicetree.cb
@@ -35,7 +35,6 @@ chip soc/intel/alderlake
 			register "ddi_ports_config" = "{
 				[DDI_PORT_A]				= DDI_ENABLE_HPD,
 				[DDI_PORT_B]				= DDI_ENABLE_HPD | DDI_ENABLE_DDC,
-				[DDI_PORT_1]				= DDI_ENABLE_HPD,
 			}"
 		end
 		device ref pcie4_0	on				# SSD x4
diff --git a/src/mainboard/starlabs/starlite_adl/variants/mk_v/devicetree.cb b/src/mainboard/starlabs/starlite_adl/variants/mk_v/devicetree.cb
index 52bd80b030..f27e41bf32 100644
--- a/src/mainboard/starlabs/starlite_adl/variants/mk_v/devicetree.cb
+++ b/src/mainboard/starlabs/starlite_adl/variants/mk_v/devicetree.cb
@@ -64,8 +64,6 @@ chip soc/intel/alderlake
 			register "ddi_ports_config" = "{
 				[DDI_PORT_A]				= DDI_ENABLE_HPD,
 				[DDI_PORT_B]				= DDI_ENABLE_HPD | DDI_ENABLE_DDC,
-				[DDI_PORT_1]				= DDI_ENABLE_HPD,
-				[DDI_PORT_2]				= DDI_ENABLE_HPD,
 			}"
 		end
 		device ref gna		on  end

From 80b597ed8243926c2faf7125502a00644290e059 Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Tue, 18 Mar 2025 13:34:15 +0000
Subject: [PATCH 0450/3886] mb/starlabs/*: Enable HDA DSP

Enable the  High Definition Audio Digital Signal Processor (HDA DSP)
to improve audio processing capabilities.

Change-Id: I6fd44b40a635bc6bb9404978493761823088b0fa
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86917
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/starlabs/byte_adl/variants/mk_ii/devicetree.cb    | 1 +
 src/mainboard/starlabs/starbook/variants/adl/devicetree.cb      | 1 +
 src/mainboard/starlabs/starbook/variants/adl_n/devicetree.cb    | 1 +
 src/mainboard/starlabs/starbook/variants/rpl/devicetree.cb      | 1 +
 src/mainboard/starlabs/starfighter/variants/rpl/devicetree.cb   | 1 +
 src/mainboard/starlabs/starlite_adl/variants/mk_v/devicetree.cb | 1 +
 6 files changed, 6 insertions(+)

diff --git a/src/mainboard/starlabs/byte_adl/variants/mk_ii/devicetree.cb b/src/mainboard/starlabs/byte_adl/variants/mk_ii/devicetree.cb
index 25ae635491..99e89aeee9 100644
--- a/src/mainboard/starlabs/byte_adl/variants/mk_ii/devicetree.cb
+++ b/src/mainboard/starlabs/byte_adl/variants/mk_ii/devicetree.cb
@@ -236,6 +236,7 @@ chip soc/intel/alderlake
 		device ref hda		on
 			subsystemid 0x14f1 0x035e
 			register "pch_hda_sdi_enable[0]"		= "1"
+			register "pch_hda_dsp_enable"			= "true"
 			register "pch_hda_audio_link_hda_enable"	= "1"
 			register "pch_hda_idisp_codec_enable"		= "1"
 			register "pch_hda_idisp_link_frequency"		= "HDA_LINKFREQ_96MHZ"
diff --git a/src/mainboard/starlabs/starbook/variants/adl/devicetree.cb b/src/mainboard/starlabs/starbook/variants/adl/devicetree.cb
index dd6500ef73..7588e93181 100644
--- a/src/mainboard/starlabs/starbook/variants/adl/devicetree.cb
+++ b/src/mainboard/starlabs/starbook/variants/adl/devicetree.cb
@@ -245,6 +245,7 @@ chip soc/intel/alderlake
 		device ref hda		on
 			subsystemid 0x1e50 0x7007
 			register "pch_hda_sdi_enable[0]"		= "true"
+			register "pch_hda_dsp_enable"			= "true"
 			register "pch_hda_audio_link_hda_enable"	= "1"
 			register "pch_hda_idisp_codec_enable"		= "1"
 			register "pch_hda_idisp_link_frequency"		= "HDA_LINKFREQ_96MHZ"
diff --git a/src/mainboard/starlabs/starbook/variants/adl_n/devicetree.cb b/src/mainboard/starlabs/starbook/variants/adl_n/devicetree.cb
index 4f6368a428..73708f50d7 100644
--- a/src/mainboard/starlabs/starbook/variants/adl_n/devicetree.cb
+++ b/src/mainboard/starlabs/starbook/variants/adl_n/devicetree.cb
@@ -250,6 +250,7 @@ chip soc/intel/alderlake
 		device ref hda		on
 			subsystemid 0x1e50 0x7038
 			register "pch_hda_sdi_enable[0]"		= "true"
+			register "pch_hda_dsp_enable"			= "true"
 			register "pch_hda_audio_link_hda_enable"	= "true"
 			register "pch_hda_idisp_codec_enable"		= "true"
 			register "pch_hda_idisp_link_frequency"		= "HDA_LINKFREQ_96MHZ"
diff --git a/src/mainboard/starlabs/starbook/variants/rpl/devicetree.cb b/src/mainboard/starlabs/starbook/variants/rpl/devicetree.cb
index bd22901f01..1905e3ef1a 100644
--- a/src/mainboard/starlabs/starbook/variants/rpl/devicetree.cb
+++ b/src/mainboard/starlabs/starbook/variants/rpl/devicetree.cb
@@ -256,6 +256,7 @@ chip soc/intel/alderlake
 		device ref hda		on
 			subsystemid 0x1e50 0x7007
 			register "pch_hda_sdi_enable[0]"		= "true"
+			register "pch_hda_dsp_enable"			= "true"
 			register "pch_hda_audio_link_hda_enable"	= "1"
 			register "pch_hda_idisp_codec_enable"		= "1"
 			register "pch_hda_idisp_link_frequency"		= "HDA_LINKFREQ_96MHZ"
diff --git a/src/mainboard/starlabs/starfighter/variants/rpl/devicetree.cb b/src/mainboard/starlabs/starfighter/variants/rpl/devicetree.cb
index 479e05e4f8..e75df6f9ff 100644
--- a/src/mainboard/starlabs/starfighter/variants/rpl/devicetree.cb
+++ b/src/mainboard/starlabs/starfighter/variants/rpl/devicetree.cb
@@ -288,6 +288,7 @@ chip soc/intel/alderlake
 		device ref hda		on
 			subsystemid 0x10ec 0x1200
 			register "pch_hda_sdi_enable[0]"		= "1"
+			register "pch_hda_dsp_enable"			= "true"
 			register "pch_hda_audio_link_hda_enable"	= "1"
 			register "pch_hda_idisp_codec_enable"		= "1"
 			register "pch_hda_idisp_link_frequency"		= "HDA_LINKFREQ_96MHZ"
diff --git a/src/mainboard/starlabs/starlite_adl/variants/mk_v/devicetree.cb b/src/mainboard/starlabs/starlite_adl/variants/mk_v/devicetree.cb
index f27e41bf32..eb711a0745 100644
--- a/src/mainboard/starlabs/starlite_adl/variants/mk_v/devicetree.cb
+++ b/src/mainboard/starlabs/starlite_adl/variants/mk_v/devicetree.cb
@@ -247,6 +247,7 @@ chip soc/intel/alderlake
 		device ref hda		on
 			subsystemid 0x1e50 0x7038
 			register "pch_hda_sdi_enable[0]"		= "true"
+			register "pch_hda_dsp_enable"			= "true"
 			register "pch_hda_audio_link_hda_enable"	= "1"
 			register "pch_hda_idisp_codec_enable"		= "1"
 			register "pch_hda_idisp_link_frequency"		= "HDA_LINKFREQ_96MHZ"

From 2f65153602f24c3e3e61f3077d1a19680d41b9a6 Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Tue, 18 Mar 2025 13:44:49 +0000
Subject: [PATCH 0451/3886] mb/starlabs/starbook/adl_n: Disconnected unused
 GPIOs

This pins aren't connected to anything so adjust them accordingly.

Change-Id: I906e3b555e7ae802f6c14285ad8a5b98f43b2f36
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86918
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
---
 src/mainboard/starlabs/starbook/variants/adl_n/gpio.c | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/src/mainboard/starlabs/starbook/variants/adl_n/gpio.c b/src/mainboard/starlabs/starbook/variants/adl_n/gpio.c
index 3c5c7d0b97..1c17b974e4 100644
--- a/src/mainboard/starlabs/starbook/variants/adl_n/gpio.c
+++ b/src/mainboard/starlabs/starbook/variants/adl_n/gpio.c
@@ -151,17 +151,17 @@ const struct pad_config gpio_table[] = {
 				High:	Enabled				*/
 	PAD_CFG_GPO(GPP_C2, 1, PLTRST),
 	/* C3:		SML 0 Clock					*/
-	PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1),
+	PAD_NC(GPP_C3, NONE),
 	/* C4:		SML 0 Data					*/
-	PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1),
+	PAD_NC(GPP_C4, NONE),
 	/* C5:		Boot Strap		Weak Internal PD 20K
 				Low:	ESPI
 				High:	Disabled			*/
 	PAD_CFG_GPO(GPP_C5, 0, DEEP),
 	/* C6:		SML 1 Clock					*/
-	PAD_CFG_NF(GPP_C6, NONE, DEEP, NF1),
+	PAD_NC(GPP_C6, NONE),
 	/* C7:		SML 1 Data					*/
-	PAD_CFG_NF(GPP_C7, NONE, DEEP, NF1),
+	PAD_NC(GPP_C7, NONE),
 	/* C8:		Not Connected					*/
 	PAD_NC(GPP_C8, NONE),
 	/* C9:		Not Connected					*/

From 653f191de96bb8ebc063ab32cc3f2e09a71e129e Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Tue, 18 Mar 2025 13:45:50 +0000
Subject: [PATCH 0452/3886] mb/starlabs/starbook/adl_n: Adjust eSPI GPIO

Set the GPIO that enables eSPI to PLTRST to ensure that eSPI works
in S3.

Change-Id: I7da5cf493a676ea106ab94fcb377bc8a29b72990
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86919
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
---
 src/mainboard/starlabs/starbook/variants/adl_n/gpio.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/mainboard/starlabs/starbook/variants/adl_n/gpio.c b/src/mainboard/starlabs/starbook/variants/adl_n/gpio.c
index 1c17b974e4..54f597112a 100644
--- a/src/mainboard/starlabs/starbook/variants/adl_n/gpio.c
+++ b/src/mainboard/starlabs/starbook/variants/adl_n/gpio.c
@@ -157,7 +157,7 @@ const struct pad_config gpio_table[] = {
 	/* C5:		Boot Strap		Weak Internal PD 20K
 				Low:	ESPI
 				High:	Disabled			*/
-	PAD_CFG_GPO(GPP_C5, 0, DEEP),
+	PAD_CFG_GPO(GPP_C5, 0, PLTRST),
 	/* C6:		SML 1 Clock					*/
 	PAD_NC(GPP_C6, NONE),
 	/* C7:		SML 1 Data					*/

From 7a0db71f354077f94de14f3ea1187f7aa442c11b Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Tue, 18 Mar 2025 13:32:51 +0000
Subject: [PATCH 0453/3886] mb/starlabs/*: Enable PMC IPC Mailbox for Alder
 Lake onwards

Introduce support for an IPC mailbox interface that lets the OS
exchange commands and responses with the Power Management Controller
(PMC) when needed.

Change-Id: Id6748b410b96dcf2a6e681c39dad2173be9bde3c
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86916
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/starlabs/byte_adl/Kconfig     | 1 +
 src/mainboard/starlabs/starbook/Kconfig     | 1 +
 src/mainboard/starlabs/starfighter/Kconfig  | 1 +
 src/mainboard/starlabs/starlite_adl/Kconfig | 1 +
 4 files changed, 4 insertions(+)

diff --git a/src/mainboard/starlabs/byte_adl/Kconfig b/src/mainboard/starlabs/byte_adl/Kconfig
index 51fa7aa77a..9b06ea43fa 100644
--- a/src/mainboard/starlabs/byte_adl/Kconfig
+++ b/src/mainboard/starlabs/byte_adl/Kconfig
@@ -9,6 +9,7 @@ config BOARD_STARLABS_BYTE_SERIES
 	select INTEL_GMA_HAVE_VBT
 	select INTEL_LPSS_UART_FOR_CONSOLE
 	select NO_UART_ON_SUPERIO
+	select PMC_IPC_ACPI_INTERFACE
 	select SOC_INTEL_COMMON_BLOCK_HDA_VERB
 	select SYSTEM_TYPE_MINIPC
 	select VALIDATE_INTEL_DESCRIPTOR
diff --git a/src/mainboard/starlabs/starbook/Kconfig b/src/mainboard/starlabs/starbook/Kconfig
index 44e2355b32..dbe9e88470 100644
--- a/src/mainboard/starlabs/starbook/Kconfig
+++ b/src/mainboard/starlabs/starbook/Kconfig
@@ -75,6 +75,7 @@ config BOARD_STARLABS_STARBOOK_ADL_COMMON
 	select EC_STARLABS_NEED_ITE_BIN
 	select MAINBOARD_HAS_TPM2
 	select MEMORY_MAPPED_TPM
+	select PMC_IPC_ACPI_INTERFACE
 	select SOC_INTEL_ALDERLAKE
 	select SOC_INTEL_COMMON_BLOCK_TCSS
 	select SOC_INTEL_CRASHLOG
diff --git a/src/mainboard/starlabs/starfighter/Kconfig b/src/mainboard/starlabs/starfighter/Kconfig
index fbddb45c0a..a030d5ed02 100644
--- a/src/mainboard/starlabs/starfighter/Kconfig
+++ b/src/mainboard/starlabs/starfighter/Kconfig
@@ -26,6 +26,7 @@ config BOARD_STARLABS_STARFIGHTER_SERIES
 	select MAINBOARD_HAS_TPM2
 	select MEMORY_MAPPED_TPM
 	select NO_UART_ON_SUPERIO
+	select PMC_IPC_ACPI_INTERFACE
 	select SOC_INTEL_ALDERLAKE
 	select SOC_INTEL_ALDERLAKE_PCH_P
 	select SOC_INTEL_COMMON_BLOCK_HDA_VERB
diff --git a/src/mainboard/starlabs/starlite_adl/Kconfig b/src/mainboard/starlabs/starlite_adl/Kconfig
index 6afa6238e7..e9516a9c5f 100644
--- a/src/mainboard/starlabs/starlite_adl/Kconfig
+++ b/src/mainboard/starlabs/starlite_adl/Kconfig
@@ -22,6 +22,7 @@ config BOARD_STARLABS_STARLITE_SERIES
 	select INTEL_GMA_HAVE_VBT
 	select INTEL_LPSS_UART_FOR_CONSOLE
 	select NO_UART_ON_SUPERIO
+	select PMC_IPC_ACPI_INTERFACE
 	select SOC_INTEL_ALDERLAKE
 	select SOC_INTEL_ALDERLAKE_PCH_N
 	select SOC_INTEL_COMMON_BLOCK_HDA_VERB

From a47aa776a7545018496e39fbf86b2ce3339887bb Mon Sep 17 00:00:00 2001
From: Monika A <monika.a@intel.com>
Date: Tue, 18 Mar 2025 16:22:20 +0530
Subject: [PATCH 0454/3886] mb/google/brya/variants/trulo: Enable BT audio
 offload

vGPIO configs are configured to enable SSP2 for BT audio offload.

BUG=b:404741604
Test=Verified BT offload with HDA configuration

Change-Id: Ibce828e32f4640cb234591392bb6ebf0662105fc
Signed-off-by: Monika A <monika.a@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86929
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
---
 .../google/brya/variants/trulo/gpio.c          | 18 ++++++++++++++++++
 .../google/brya/variants/trulo/overridetree.cb |  3 +++
 2 files changed, 21 insertions(+)

diff --git a/src/mainboard/google/brya/variants/trulo/gpio.c b/src/mainboard/google/brya/variants/trulo/gpio.c
index fb805d6f28..c9852f592a 100644
--- a/src/mainboard/google/brya/variants/trulo/gpio.c
+++ b/src/mainboard/google/brya/variants/trulo/gpio.c
@@ -410,6 +410,24 @@ static const struct pad_config gpio_table[] = {
 	PAD_NC(GPP_VGPIO_20, NONE),
 	/* vUART0_RTS_B */
 	PAD_NC(GPP_VGPIO_21, NONE),
+
+	/* Configure the virtual CNVi Bluetooth I2S GPIO Pads.*/
+	/* BT_I2S_BCLK */
+	PAD_CFG_NF(GPP_VGPIO_30, NONE, DEEP, NF3),
+	/* BT_I2S_SYNC */
+	PAD_CFG_NF(GPP_VGPIO_31, NONE, DEEP, NF3),
+	/* BT_I2S_SDO */
+	PAD_CFG_NF(GPP_VGPIO_32, NONE, DEEP, NF3),
+	/* BT_I2S_SDI */
+	PAD_CFG_NF(GPP_VGPIO_33, NONE, DEEP, NF3),
+	/* SSP2_SCLK */
+	PAD_CFG_NF(GPP_VGPIO_34, NONE, DEEP, NF1),
+	/* SSP2_SFRM */
+	PAD_CFG_NF(GPP_VGPIO_35, NONE, DEEP, NF1),
+	/* SSP_TXD */
+	PAD_CFG_NF(GPP_VGPIO_36, NONE, DEEP, NF1),
+	/* SSP_RXD */
+	PAD_CFG_NF(GPP_VGPIO_37, NONE, DEEP, NF1),
 };
 
 /* Early pad configuration in bootblock */
diff --git a/src/mainboard/google/brya/variants/trulo/overridetree.cb b/src/mainboard/google/brya/variants/trulo/overridetree.cb
index 4c21173a76..3f0801e8bb 100644
--- a/src/mainboard/google/brya/variants/trulo/overridetree.cb
+++ b/src/mainboard/google/brya/variants/trulo/overridetree.cb
@@ -116,6 +116,9 @@ chip soc/intel/alderlake
 		.vnn_icc_max_ma = 500,
 	}"
 
+	# Enable CNVi BT Audio offload
+	register "cnvi_bt_audio_offload" = "1"
+
 	register "serial_io_i2c_mode" = "{
 		[PchSerialIoIndexI2C0] = PchSerialIoPci,
 		[PchSerialIoIndexI2C1] = PchSerialIoPci,

From 2cb0b3d5909db303c521fe63ca3344d4ed3abee5 Mon Sep 17 00:00:00 2001
From: Kenneth Chan <kenneth.chan@quanta.corp-partner.google.com>
Date: Wed, 19 Mar 2025 19:45:07 +0800
Subject: [PATCH 0455/3886] mb/google/rex/var/kanix: Add WIFI SAR table

Add WIFI SAR table for kanix.

BUG=b:399484050
BRANCH=firmware-rex-15709.B
TEST=emerge-rex coreboot chromeos-bootimage

Change-Id: Ie4c549ea507b2f823ce54a0e4476f4f82a037865
Signed-off-by: Kenneth Chan <kenneth.chan@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86931
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 .../google/rex/variants/kanix/Makefile.mk        |  1 +
 .../google/rex/variants/kanix/variant.c          | 16 ++++++++++++++++
 2 files changed, 17 insertions(+)
 create mode 100644 src/mainboard/google/rex/variants/kanix/variant.c

diff --git a/src/mainboard/google/rex/variants/kanix/Makefile.mk b/src/mainboard/google/rex/variants/kanix/Makefile.mk
index 03a18360cd..3588744300 100644
--- a/src/mainboard/google/rex/variants/kanix/Makefile.mk
+++ b/src/mainboard/google/rex/variants/kanix/Makefile.mk
@@ -5,3 +5,4 @@ romstage-y += gpio.c
 ramstage-$(CONFIG_FW_CONFIG) += fw_config.c
 ramstage-y += gpio.c
 ramstage-y += ramstage.c
+ramstage-y += variant.c
diff --git a/src/mainboard/google/rex/variants/kanix/variant.c b/src/mainboard/google/rex/variants/kanix/variant.c
new file mode 100644
index 0000000000..85a908a846
--- /dev/null
+++ b/src/mainboard/google/rex/variants/kanix/variant.c
@@ -0,0 +1,16 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <baseboard/variants.h>
+#include <chip.h>
+#include <fw_config.h>
+#include <sar.h>
+
+const char *get_wifi_sar_cbfs_filename(void)
+{
+	return get_wifi_sar_fw_config_filename(FW_CONFIG_FIELD(WIFI_TYPE));
+}
+
+void variant_update_soc_chip_config(struct soc_intel_meteorlake_config *config)
+{
+	config->cnvi_bt_audio_offload = true;
+}

From f37f67f532c31ac9bd59bf4aa5c9838a4a84ddad Mon Sep 17 00:00:00 2001
From: Johannes Hahn <johannes-hahn@siemens.com>
Date: Thu, 13 Feb 2025 11:41:58 +0100
Subject: [PATCH 0456/3886] mb/siemens/fa_ehl/variants/fa_ehl: Remove I210
 driver

Intel I210 Ethernet Transceiver is not used on the platform.
As there are dependencies in the mainboard code that references
functions defined by I210 code a new header (tsn_gbe.h) was added as it
contains the dependent function definitions. The corresponding TSN_GBE
driver will be used anyway on the platform. Thereby dependencies that
lead to a failed build should be resolved with this commit.

Change-Id: I413cb334ee06e3fc7183dc2621b6091f0d0b602b
Signed-off-by: Johannes Hahn <johannes-hahn@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86425
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
---
 src/mainboard/siemens/fa_ehl/mainboard.c             | 2 +-
 src/mainboard/siemens/fa_ehl/variants/fa_ehl/Kconfig | 1 -
 2 files changed, 1 insertion(+), 2 deletions(-)

diff --git a/src/mainboard/siemens/fa_ehl/mainboard.c b/src/mainboard/siemens/fa_ehl/mainboard.c
index ac16346f2a..31f4dd78ec 100644
--- a/src/mainboard/siemens/fa_ehl/mainboard.c
+++ b/src/mainboard/siemens/fa_ehl/mainboard.c
@@ -8,9 +8,9 @@
 #include <device/pci_ops.h>
 #include <device/pci_ids.h>
 #include <hwilib.h>
-#include <i210.h>
 #include <soc/gpio.h>
 #include <soc/ramstage.h>
+#include <soc/tsn_gbe.h>
 #include <string.h>
 #include <timer.h>
 #include <timestamp.h>
diff --git a/src/mainboard/siemens/fa_ehl/variants/fa_ehl/Kconfig b/src/mainboard/siemens/fa_ehl/variants/fa_ehl/Kconfig
index 0f3544c966..76096a4e68 100644
--- a/src/mainboard/siemens/fa_ehl/variants/fa_ehl/Kconfig
+++ b/src/mainboard/siemens/fa_ehl/variants/fa_ehl/Kconfig
@@ -4,7 +4,6 @@ if BOARD_SIEMENS_FA_EHL
 
 config BOARD_SPECIFIC_OPTIONS
 	def_bool y
-	select DRIVER_INTEL_I210
 	select EHL_TSN_DRIVER
 	select DRIVERS_ETH_PHY_M88E1512
 

From 696391a76339b9fa4f2214ef003c73a4a8ac542c Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Micha=C5=82=20Kope=C4=87?= <michal.kopec@3mdeb.com>
Date: Wed, 12 Mar 2025 12:01:16 +0100
Subject: [PATCH 0457/3886] mb/novacustom/mtl-h/ramstage.c: Set Port Reset FSP
 UPDs
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Enable Port Reset on USB lanes corresponding to Type-C ports on the
mainboard.

Change-Id: Id9adc8827f3393e419118efda91c06c43ebb2ccb
Signed-off-by: Michał Kopeć <michal.kopec@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86843
Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/novacustom/mtl-h/ramstage.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/src/mainboard/novacustom/mtl-h/ramstage.c b/src/mainboard/novacustom/mtl-h/ramstage.c
index cd7031ba01..19d14a6e1a 100644
--- a/src/mainboard/novacustom/mtl-h/ramstage.c
+++ b/src/mainboard/novacustom/mtl-h/ramstage.c
@@ -39,4 +39,7 @@ void mainboard_silicon_init_params(FSP_S_CONFIG *params)
 	params->CnviClkreqPinMux = 0x394CE605;  // GPP_F05
 
 	params->LidStatus = dasharo_ec_get_lid_state();
+
+	params->PortResetMessageEnable[1] = 1;
+	params->PortResetMessageEnable[5] = 1;
 }

From 55faa2532fe56f504526d742e95da776ae6456ad Mon Sep 17 00:00:00 2001
From: Yidi Lin <yidilin@chromium.org>
Date: Fri, 14 Mar 2025 14:36:35 +0800
Subject: [PATCH 0458/3886] soc/mediatek: Change rtc_bbpu_power_on to static
 function

BUG=b:388796896
TEST=compiled on kukui/asurada/cherry/corsola/geralt

Change-Id: Iea9a1aa5e19887513c537d0787f0434b51736c08
Signed-off-by: Yidi Lin <yidilin@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86924
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/soc/mediatek/common/rtc_mt6359p.c     | 2 +-
 src/soc/mediatek/mt8183/include/soc/rtc.h | 1 -
 src/soc/mediatek/mt8183/rtc.c             | 2 +-
 src/soc/mediatek/mt8186/include/soc/rtc.h | 1 -
 src/soc/mediatek/mt8186/rtc.c             | 2 +-
 src/soc/mediatek/mt8188/include/soc/rtc.h | 1 -
 src/soc/mediatek/mt8192/include/soc/rtc.h | 1 -
 src/soc/mediatek/mt8195/include/soc/rtc.h | 1 -
 8 files changed, 3 insertions(+), 8 deletions(-)

diff --git a/src/soc/mediatek/common/rtc_mt6359p.c b/src/soc/mediatek/common/rtc_mt6359p.c
index a930aacb87..6e8a3a0931 100644
--- a/src/soc/mediatek/common/rtc_mt6359p.c
+++ b/src/soc/mediatek/common/rtc_mt6359p.c
@@ -283,7 +283,7 @@ err:
 }
 
 /* enable rtc bbpu */
-void rtc_bbpu_power_on(void)
+static void rtc_bbpu_power_on(void)
 {
 	u16 bbpu;
 	int ret;
diff --git a/src/soc/mediatek/mt8183/include/soc/rtc.h b/src/soc/mediatek/mt8183/include/soc/rtc.h
index eb166a32a2..93fd29bf68 100644
--- a/src/soc/mediatek/mt8183/include/soc/rtc.h
+++ b/src/soc/mediatek/mt8183/include/soc/rtc.h
@@ -80,7 +80,6 @@ enum {
 
 
 /* external API */
-void rtc_bbpu_power_on(void);
 int rtc_init(int recover);
 bool rtc_gpio_init(void);
 void rtc_boot(void);
diff --git a/src/soc/mediatek/mt8183/rtc.c b/src/soc/mediatek/mt8183/rtc.c
index 40830b033f..23a3ea3d5c 100644
--- a/src/soc/mediatek/mt8183/rtc.c
+++ b/src/soc/mediatek/mt8183/rtc.c
@@ -263,7 +263,7 @@ err:
 }
 
 /* enable rtc bbpu */
-void rtc_bbpu_power_on(void)
+static void rtc_bbpu_power_on(void)
 {
 	u16 bbpu;
 	int ret;
diff --git a/src/soc/mediatek/mt8186/include/soc/rtc.h b/src/soc/mediatek/mt8186/include/soc/rtc.h
index 914da6ac83..fcd2f69b34 100644
--- a/src/soc/mediatek/mt8186/include/soc/rtc.h
+++ b/src/soc/mediatek/mt8186/include/soc/rtc.h
@@ -85,7 +85,6 @@ enum {
 
 
 /* external API */
-void rtc_bbpu_power_on(void);
 int rtc_init(int recover);
 bool rtc_gpio_init(void);
 void rtc_boot(void);
diff --git a/src/soc/mediatek/mt8186/rtc.c b/src/soc/mediatek/mt8186/rtc.c
index 7bf5bc8c0f..d3b148f824 100644
--- a/src/soc/mediatek/mt8186/rtc.c
+++ b/src/soc/mediatek/mt8186/rtc.c
@@ -301,7 +301,7 @@ err:
 }
 
 /* Enable RTC bbpu */
-void rtc_bbpu_power_on(void)
+static void rtc_bbpu_power_on(void)
 {
 	u16 bbpu;
 	int ret;
diff --git a/src/soc/mediatek/mt8188/include/soc/rtc.h b/src/soc/mediatek/mt8188/include/soc/rtc.h
index b2eb3f1f39..67a67017d9 100644
--- a/src/soc/mediatek/mt8188/include/soc/rtc.h
+++ b/src/soc/mediatek/mt8188/include/soc/rtc.h
@@ -84,7 +84,6 @@ enum {
 
 void rtc_read(u16 addr, u16 *rdata);
 void rtc_write(u16 addr, u16 wdata);
-void rtc_bbpu_power_on(void);
 int rtc_init(int recover);
 bool rtc_gpio_init(void);
 void rtc_boot(void);
diff --git a/src/soc/mediatek/mt8192/include/soc/rtc.h b/src/soc/mediatek/mt8192/include/soc/rtc.h
index f8543ab45d..10a529ad4b 100644
--- a/src/soc/mediatek/mt8192/include/soc/rtc.h
+++ b/src/soc/mediatek/mt8192/include/soc/rtc.h
@@ -85,7 +85,6 @@ enum {
 
 void rtc_read(u16 addr, u16 *rdata);
 void rtc_write(u16 addr, u16 wdata);
-void rtc_bbpu_power_on(void);
 int rtc_init(int recover);
 bool rtc_gpio_init(void);
 void rtc_boot(void);
diff --git a/src/soc/mediatek/mt8195/include/soc/rtc.h b/src/soc/mediatek/mt8195/include/soc/rtc.h
index 3dcb0ea968..342aadf776 100644
--- a/src/soc/mediatek/mt8195/include/soc/rtc.h
+++ b/src/soc/mediatek/mt8195/include/soc/rtc.h
@@ -85,7 +85,6 @@ enum {
 
 void rtc_read(u16 addr, u16 *rdata);
 void rtc_write(u16 addr, u16 wdata);
-void rtc_bbpu_power_on(void);
 int rtc_init(int recover);
 bool rtc_gpio_init(void);
 void rtc_boot(void);

From 114af7f95f504ed4779603cfbbc18b54d2cc38b8 Mon Sep 17 00:00:00 2001
From: Yidi Lin <yidilin@chromium.org>
Date: Wed, 19 Mar 2025 15:19:42 +0800
Subject: [PATCH 0459/3886] soc/mediatek: Refactor rtc_{read, write} for
 mt8173, mt8183 and mt8186

MT8173, MT8183 and MT8186 read and write RTC register via pwrap
interface. Since the implementations are the same, move those APIs to a
common file.

BUG=b:388796896
TEST=build coreboot for elm, kukui and corsola

Change-Id: I6c177e8c1b5dee72c18d765f19a48eb38db121f1
Signed-off-by: Yidi Lin <yidilin@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86925
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
---
 src/soc/mediatek/common/rtc_pwrap_ops.c   | 26 +++++++++++++++++++++++
 src/soc/mediatek/mt8173/Makefile.mk       |  4 ++--
 src/soc/mediatek/mt8173/include/soc/rtc.h | 24 ++-------------------
 src/soc/mediatek/mt8183/Makefile.mk       |  4 ++--
 src/soc/mediatek/mt8183/include/soc/rtc.h | 24 ++-------------------
 src/soc/mediatek/mt8186/Makefile.mk       |  4 ++--
 src/soc/mediatek/mt8186/include/soc/rtc.h | 24 ++-------------------
 7 files changed, 38 insertions(+), 72 deletions(-)
 create mode 100644 src/soc/mediatek/common/rtc_pwrap_ops.c

diff --git a/src/soc/mediatek/common/rtc_pwrap_ops.c b/src/soc/mediatek/common/rtc_pwrap_ops.c
new file mode 100644
index 0000000000..7675e0ede0
--- /dev/null
+++ b/src/soc/mediatek/common/rtc_pwrap_ops.c
@@ -0,0 +1,26 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <soc/pmic_wrap_common.h>
+#include <soc/rtc.h>
+
+s32 rtc_read(u16 addr, u16 *rdata)
+{
+	s32 ret;
+
+	ret = pwrap_read(addr, rdata);
+	if (ret < 0)
+		rtc_info("pwrap_read failed: ret=%d\n", ret);
+
+	return ret;
+}
+
+s32 rtc_write(u16 addr, u16 wdata)
+{
+	s32 ret;
+
+	ret = pwrap_write(addr, wdata);
+	if (ret < 0)
+		rtc_info("pwrap_write failed: ret=%d\n", ret);
+
+	return ret;
+}
diff --git a/src/soc/mediatek/mt8173/Makefile.mk b/src/soc/mediatek/mt8173/Makefile.mk
index 7688ecfd45..ee698b72ff 100644
--- a/src/soc/mediatek/mt8173/Makefile.mk
+++ b/src/soc/mediatek/mt8173/Makefile.mk
@@ -48,7 +48,7 @@ romstage-y += emi.c dramc_pi_basic_api.c dramc_pi_calibration_api.c
 romstage-$(CONFIG_MEMORY_TEST) += ../common/memory_test.c
 romstage-y += ../common/wdt.c ../common/reset.c
 romstage-y += ../common/mmu_operations.c mmu_operations.c
-romstage-y += ../common/rtc.c rtc.c
+romstage-y += ../common/rtc.c ../common/rtc_pwrap_ops.c rtc.c
 
 ################################################################################
 
@@ -66,7 +66,7 @@ ramstage-y += da9212.c
 ramstage-y += ../common/gpio.c gpio.c
 ramstage-y += ../common/wdt.c ../common/reset.c
 ramstage-y += ../common/pll.c pll.c
-ramstage-y += ../common/rtc.c rtc.c
+ramstage-y += ../common/rtc.c ../common/rtc_pwrap_ops.c rtc.c
 
 ramstage-y += ../common/usb.c usb.c
 
diff --git a/src/soc/mediatek/mt8173/include/soc/rtc.h b/src/soc/mediatek/mt8173/include/soc/rtc.h
index e82d514e86..e1f84ada10 100644
--- a/src/soc/mediatek/mt8173/include/soc/rtc.h
+++ b/src/soc/mediatek/mt8173/include/soc/rtc.h
@@ -102,27 +102,7 @@ enum {
 /* external API */
 int rtc_init(int recover);
 void rtc_boot(void);
-
-static inline s32 rtc_read(u16 addr, u16 *rdata)
-{
-	s32 ret;
-
-	ret = pwrap_read(addr, rdata);
-	if (ret < 0)
-		rtc_info("pwrap_read failed: ret=%d\n", ret);
-
-	return ret;
-}
-
-static inline s32 rtc_write(u16 addr, u16 wdata)
-{
-	s32 ret;
-
-	ret = pwrap_write(addr, wdata);
-	if (ret < 0)
-		rtc_info("pwrap_write failed: ret=%d\n", ret);
-
-	return ret;
-}
+s32 rtc_read(u16 addr, u16 *rdata);
+s32 rtc_write(u16 addr, u16 wdata);
 
 #endif /* SOC_MEDIATEK_MT8173_RTC_H */
diff --git a/src/soc/mediatek/mt8183/Makefile.mk b/src/soc/mediatek/mt8183/Makefile.mk
index c346d176cc..bd50780045 100644
--- a/src/soc/mediatek/mt8183/Makefile.mk
+++ b/src/soc/mediatek/mt8183/Makefile.mk
@@ -38,7 +38,7 @@ romstage-y += ../common/gpio_eint_v1.c ../common/gpio.c gpio.c
 romstage-y += ../common/mmu_operations.c mmu_operations.c
 romstage-y += ../common/pll.c pll.c
 romstage-y += ../common/pmic_wrap.c pmic_wrap.c mt6358.c
-romstage-y += ../common/rtc.c ../common/rtc_osc_init.c rtc.c
+romstage-y += ../common/rtc.c ../common/rtc_pwrap_ops.c ../common/rtc_osc_init.c rtc.c
 romstage-$(CONFIG_SPI_FLASH) += ../common/spi.c spi.c
 romstage-y += ../common/i2c.c i2c.c
 romstage-y += ../common/timer.c
@@ -56,7 +56,7 @@ ramstage-y += ../common/mcu.c
 ramstage-y += ../common/mmu_operations.c mmu_operations.c
 ramstage-y += ../common/mtcmos.c mtcmos.c
 ramstage-y += ../common/pmic_wrap.c
-ramstage-y += ../common/rtc.c ../common/rtc_osc_init.c rtc.c
+ramstage-y += ../common/rtc.c ../common/rtc_pwrap_ops.c ../common/rtc_osc_init.c rtc.c
 ramstage-y += soc.c
 ramstage-$(CONFIG_SPI_FLASH) += ../common/spi.c spi.c
 ramstage-y += spm.c
diff --git a/src/soc/mediatek/mt8183/include/soc/rtc.h b/src/soc/mediatek/mt8183/include/soc/rtc.h
index 93fd29bf68..4c59ee2573 100644
--- a/src/soc/mediatek/mt8183/include/soc/rtc.h
+++ b/src/soc/mediatek/mt8183/include/soc/rtc.h
@@ -85,27 +85,7 @@ bool rtc_gpio_init(void);
 void rtc_boot(void);
 u16 rtc_get_frequency_meter(u16 val, u16 measure_src, u16 window_size);
 void mt6358_dcxo_disable_unused(void);
-
-static inline s32 rtc_read(u16 addr, u16 *rdata)
-{
-	s32 ret;
-
-	ret = pwrap_read(addr, rdata);
-	if (ret < 0)
-		rtc_info("pwrap_read failed: ret=%d\n", ret);
-
-	return ret;
-}
-
-static inline s32 rtc_write(u16 addr, u16 wdata)
-{
-	s32 ret;
-
-	ret = pwrap_write(addr, wdata);
-	if (ret < 0)
-		rtc_info("pwrap_write failed: ret=%d\n", ret);
-
-	return ret;
-}
+s32 rtc_read(u16 addr, u16 *rdata);
+s32 rtc_write(u16 addr, u16 wdata);
 
 #endif /* SOC_MEDIATEK_MT8183_RTC_H */
diff --git a/src/soc/mediatek/mt8186/Makefile.mk b/src/soc/mediatek/mt8186/Makefile.mk
index c4a3f21fbb..ea4bcfc25a 100644
--- a/src/soc/mediatek/mt8186/Makefile.mk
+++ b/src/soc/mediatek/mt8186/Makefile.mk
@@ -31,7 +31,7 @@ romstage-y += ../common/mt6315.c mt6315.c
 romstage-y += ../common/pmic_wrap.c pmic_wrap.c pmif.c mt6366.c
 romstage-y += ../common/pmif.c ../common/pmif_clk.c ../common/pmif_init.c pmif_clk.c
 romstage-y += ../common/pmif_spmi.c pmif_spmi.c
-romstage-y += ../common/rtc.c ../common/rtc_osc_init.c rtc.c
+romstage-y += ../common/rtc.c ../common/rtc_pwrap_ops.c ../common/rtc_osc_init.c rtc.c
 
 ramstage-y += adsp.c
 ramstage-y += ../common/auxadc.c
@@ -48,7 +48,7 @@ ramstage-y += ../common/mmu_operations.c ../common/mmu_cmops.c
 ramstage-$(CONFIG_COMMONLIB_STORAGE_MMC) += ../common/msdc.c msdc.c
 ramstage-y += ../common/mtcmos.c mtcmos.c
 ramstage-y += ../common/pmic_wrap.c pmic_wrap.c pmif.c mt6366.c
-ramstage-y += ../common/rtc.c ../common/rtc_osc_init.c rtc.c
+ramstage-y += ../common/rtc.c ../common/rtc_pwrap_ops.c ../common/rtc_osc_init.c rtc.c
 ramstage-y += soc.c
 ramstage-y += ../common/spm.c ../common/spm_v1.c spm.c
 ramstage-y += ../common/sspm.c
diff --git a/src/soc/mediatek/mt8186/include/soc/rtc.h b/src/soc/mediatek/mt8186/include/soc/rtc.h
index fcd2f69b34..bbb6b86e25 100644
--- a/src/soc/mediatek/mt8186/include/soc/rtc.h
+++ b/src/soc/mediatek/mt8186/include/soc/rtc.h
@@ -89,27 +89,7 @@ int rtc_init(int recover);
 bool rtc_gpio_init(void);
 void rtc_boot(void);
 u16 rtc_get_frequency_meter(u16 val, u16 measure_src, u16 window_size);
-
-static inline s32 rtc_read(u16 addr, u16 *rdata)
-{
-	s32 ret;
-
-	ret = pwrap_read(addr, rdata);
-	if (ret)
-		rtc_info("pwrap_read failed: ret=%d\n", ret);
-
-	return ret;
-}
-
-static inline s32 rtc_write(u16 addr, u16 wdata)
-{
-	s32 ret;
-
-	ret = pwrap_write(addr, wdata);
-	if (ret)
-		rtc_info("pwrap_write failed: ret=%d\n", ret);
-
-	return ret;
-}
+s32 rtc_read(u16 addr, u16 *rdata);
+s32 rtc_write(u16 addr, u16 wdata);
 
 #endif /* SOC_MEDIATEK_MT8186_RTC_H */

From a384d6e1223b5a65ea65aa7af7064eeae13e16f6 Mon Sep 17 00:00:00 2001
From: Yidi Lin <yidilin@chromium.org>
Date: Wed, 19 Mar 2025 16:02:42 +0800
Subject: [PATCH 0460/3886] soc/mediatek/common: Change return type to void for
 all rtc_{read, write} APIs

The MediaTek RTC driver does not check the return value of rtc_read()
and rtc_write(). Additionally, the RTC driver of recent platforms uses
void for rtc_read() and rtc_write(). Therefore, change the return type
of all rtc_{read, write} APIs to void and add assert for debugging.

BUG=b:388796896
TEST=build coreboot for elm, kukui and corsola

Change-Id: Ie5168db0abd479e63279ac4c8d6f2c668d6234f0
Signed-off-by: Yidi Lin <yidilin@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86926
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
---
 src/soc/mediatek/common/rtc_pwrap_ops.c   | 16 ++++++----------
 src/soc/mediatek/mt8173/include/soc/rtc.h |  4 ++--
 src/soc/mediatek/mt8183/include/soc/rtc.h |  4 ++--
 src/soc/mediatek/mt8186/include/soc/rtc.h |  4 ++--
 src/soc/mediatek/mt8186/rtc.c             |  4 ++--
 5 files changed, 14 insertions(+), 18 deletions(-)

diff --git a/src/soc/mediatek/common/rtc_pwrap_ops.c b/src/soc/mediatek/common/rtc_pwrap_ops.c
index 7675e0ede0..b32c90d6b8 100644
--- a/src/soc/mediatek/common/rtc_pwrap_ops.c
+++ b/src/soc/mediatek/common/rtc_pwrap_ops.c
@@ -1,26 +1,22 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
+#include <assert.h>
 #include <soc/pmic_wrap_common.h>
 #include <soc/rtc.h>
 
-s32 rtc_read(u16 addr, u16 *rdata)
+void rtc_read(u16 addr, u16 *rdata)
 {
 	s32 ret;
 
+	*rdata = 0;
 	ret = pwrap_read(addr, rdata);
-	if (ret < 0)
-		rtc_info("pwrap_read failed: ret=%d\n", ret);
-
-	return ret;
+	assert(ret == 0);
 }
 
-s32 rtc_write(u16 addr, u16 wdata)
+void rtc_write(u16 addr, u16 wdata)
 {
 	s32 ret;
 
 	ret = pwrap_write(addr, wdata);
-	if (ret < 0)
-		rtc_info("pwrap_write failed: ret=%d\n", ret);
-
-	return ret;
+	assert(ret == 0);
 }
diff --git a/src/soc/mediatek/mt8173/include/soc/rtc.h b/src/soc/mediatek/mt8173/include/soc/rtc.h
index e1f84ada10..6956931a0a 100644
--- a/src/soc/mediatek/mt8173/include/soc/rtc.h
+++ b/src/soc/mediatek/mt8173/include/soc/rtc.h
@@ -102,7 +102,7 @@ enum {
 /* external API */
 int rtc_init(int recover);
 void rtc_boot(void);
-s32 rtc_read(u16 addr, u16 *rdata);
-s32 rtc_write(u16 addr, u16 wdata);
+void rtc_read(u16 addr, u16 *rdata);
+void rtc_write(u16 addr, u16 wdata);
 
 #endif /* SOC_MEDIATEK_MT8173_RTC_H */
diff --git a/src/soc/mediatek/mt8183/include/soc/rtc.h b/src/soc/mediatek/mt8183/include/soc/rtc.h
index 4c59ee2573..8c8ed096bb 100644
--- a/src/soc/mediatek/mt8183/include/soc/rtc.h
+++ b/src/soc/mediatek/mt8183/include/soc/rtc.h
@@ -85,7 +85,7 @@ bool rtc_gpio_init(void);
 void rtc_boot(void);
 u16 rtc_get_frequency_meter(u16 val, u16 measure_src, u16 window_size);
 void mt6358_dcxo_disable_unused(void);
-s32 rtc_read(u16 addr, u16 *rdata);
-s32 rtc_write(u16 addr, u16 wdata);
+void rtc_read(u16 addr, u16 *rdata);
+void rtc_write(u16 addr, u16 wdata);
 
 #endif /* SOC_MEDIATEK_MT8183_RTC_H */
diff --git a/src/soc/mediatek/mt8186/include/soc/rtc.h b/src/soc/mediatek/mt8186/include/soc/rtc.h
index bbb6b86e25..bf357d15bb 100644
--- a/src/soc/mediatek/mt8186/include/soc/rtc.h
+++ b/src/soc/mediatek/mt8186/include/soc/rtc.h
@@ -89,7 +89,7 @@ int rtc_init(int recover);
 bool rtc_gpio_init(void);
 void rtc_boot(void);
 u16 rtc_get_frequency_meter(u16 val, u16 measure_src, u16 window_size);
-s32 rtc_read(u16 addr, u16 *rdata);
-s32 rtc_write(u16 addr, u16 wdata);
+void rtc_read(u16 addr, u16 *rdata);
+void rtc_write(u16 addr, u16 wdata);
 
 #endif /* SOC_MEDIATEK_MT8186_RTC_H */
diff --git a/src/soc/mediatek/mt8186/rtc.c b/src/soc/mediatek/mt8186/rtc.c
index d3b148f824..54b2f2d5a3 100644
--- a/src/soc/mediatek/mt8186/rtc.c
+++ b/src/soc/mediatek/mt8186/rtc.c
@@ -121,8 +121,8 @@ u16 rtc_get_frequency_meter(u16 val, u16 measure_src, u16 window_size)
 
 	/* FQMTR read until ready */
 	if (!wait_us(FQMTR_TIMEOUT_US,
-		     rtc_read(PMIC_RG_FQMTR_CON0, &fqmtr_busy) == 0 &&
-		     !(fqmtr_busy & PMIC_FQMTR_CON0_BUSY))) {
+		     !((rtc_read(PMIC_RG_FQMTR_CON0, &fqmtr_busy),
+			fqmtr_busy) & PMIC_FQMTR_CON0_BUSY))) {
 		rtc_info("get frequency time out: %#x\n", fqmtr_busy);
 		return false;
 	}

From e5e0621273992d836e2dff396ef0e7cfc1f77424 Mon Sep 17 00:00:00 2001
From: Yidi Lin <yidilin@chromium.org>
Date: Fri, 14 Mar 2025 16:23:01 +0800
Subject: [PATCH 0461/3886] soc/mediatek/common: Move common API declarations
 to rtc_common.h

Move following function declarations to rtc_common.h.
- rtc_init()
- rtc_boot()
- rtc_get_frequency_meter()
- rtc_gpio_init()
- rtc_read()
- rtc_write()

BUG=b:388796896
TEST=build coreboot for all MediaTek platforms

Change-Id: I6210251a5cf3f80836d5f8a09c9ecfd133677b35
Signed-off-by: Yidi Lin <yidilin@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86927
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
---
 src/mainboard/google/rauru/romstage.c            | 2 +-
 src/soc/mediatek/common/include/soc/rtc_common.h | 7 +++++++
 src/soc/mediatek/mt8173/include/soc/rtc.h        | 6 ------
 src/soc/mediatek/mt8173/rtc.c                    | 2 +-
 src/soc/mediatek/mt8183/include/soc/rtc.h        | 6 ------
 src/soc/mediatek/mt8186/include/soc/rtc.h        | 9 ---------
 src/soc/mediatek/mt8188/include/soc/rtc.h        | 8 +-------
 src/soc/mediatek/mt8192/include/soc/rtc.h        | 7 +------
 src/soc/mediatek/mt8195/include/soc/rtc.h        | 7 +------
 src/soc/mediatek/mt8196/include/soc/mt6685_rtc.h | 3 ---
 src/soc/mediatek/mt8196/include/soc/rtc.h        | 5 -----
 11 files changed, 12 insertions(+), 50 deletions(-)

diff --git a/src/mainboard/google/rauru/romstage.c b/src/mainboard/google/rauru/romstage.c
index 584af61d0f..89602532d7 100644
--- a/src/mainboard/google/rauru/romstage.c
+++ b/src/mainboard/google/rauru/romstage.c
@@ -11,12 +11,12 @@
 #include <soc/mt6363.h>
 #include <soc/mt6373.h>
 #include <soc/mt6685.h>
-#include <soc/mt6685_rtc.h>
 #include <soc/mtk_fsp.h>
 #include <soc/pcie.h>
 #include <soc/pll.h>
 #include <soc/pmif.h>
 #include <soc/pwrsel.h>
+#include <soc/rtc.h>
 #include <soc/srclken_rc.h>
 #include <soc/thermal.h>
 
diff --git a/src/soc/mediatek/common/include/soc/rtc_common.h b/src/soc/mediatek/common/include/soc/rtc_common.h
index 7a22a01544..4e3d7110ef 100644
--- a/src/soc/mediatek/common/include/soc/rtc_common.h
+++ b/src/soc/mediatek/common/include/soc/rtc_common.h
@@ -104,5 +104,12 @@ void rtc_osc_init(void);
 bool rtc_powerkey_init(void);
 void rtc_boot_common(void);
 u16 rtc_eosc_cali(void);
+/* Complete the RTC initialization process and register settings. */
+int rtc_init(int recover);
+void rtc_boot(void);
+u16 rtc_get_frequency_meter(u16 val, u16 measure_src, u16 window_size);
+bool rtc_gpio_init(void);
+void rtc_read(u16 addr, u16 *rdata);
+void rtc_write(u16 addr, u16 wdata);
 
 #endif /* SOC_MEDIATEK_RTC_COMMON_H */
diff --git a/src/soc/mediatek/mt8173/include/soc/rtc.h b/src/soc/mediatek/mt8173/include/soc/rtc.h
index 6956931a0a..aef108ed72 100644
--- a/src/soc/mediatek/mt8173/include/soc/rtc.h
+++ b/src/soc/mediatek/mt8173/include/soc/rtc.h
@@ -99,10 +99,4 @@ enum {
 	RTC_CALI_BBPU_2SEC_STAT		= 1U << 11
 };
 
-/* external API */
-int rtc_init(int recover);
-void rtc_boot(void);
-void rtc_read(u16 addr, u16 *rdata);
-void rtc_write(u16 addr, u16 wdata);
-
 #endif /* SOC_MEDIATEK_MT8173_RTC_H */
diff --git a/src/soc/mediatek/mt8173/rtc.c b/src/soc/mediatek/mt8173/rtc.c
index 326a951096..8d86e1520a 100644
--- a/src/soc/mediatek/mt8173/rtc.c
+++ b/src/soc/mediatek/mt8173/rtc.c
@@ -8,7 +8,7 @@
 #include <types.h>
 
 /* initialize rtc related gpio */
-static bool rtc_gpio_init(void)
+bool rtc_gpio_init(void)
 {
 	u16 con;
 
diff --git a/src/soc/mediatek/mt8183/include/soc/rtc.h b/src/soc/mediatek/mt8183/include/soc/rtc.h
index 8c8ed096bb..835cdda878 100644
--- a/src/soc/mediatek/mt8183/include/soc/rtc.h
+++ b/src/soc/mediatek/mt8183/include/soc/rtc.h
@@ -80,12 +80,6 @@ enum {
 
 
 /* external API */
-int rtc_init(int recover);
-bool rtc_gpio_init(void);
-void rtc_boot(void);
-u16 rtc_get_frequency_meter(u16 val, u16 measure_src, u16 window_size);
 void mt6358_dcxo_disable_unused(void);
-void rtc_read(u16 addr, u16 *rdata);
-void rtc_write(u16 addr, u16 wdata);
 
 #endif /* SOC_MEDIATEK_MT8183_RTC_H */
diff --git a/src/soc/mediatek/mt8186/include/soc/rtc.h b/src/soc/mediatek/mt8186/include/soc/rtc.h
index bf357d15bb..75b68540ad 100644
--- a/src/soc/mediatek/mt8186/include/soc/rtc.h
+++ b/src/soc/mediatek/mt8186/include/soc/rtc.h
@@ -83,13 +83,4 @@ enum {
 	PMIC_FQMTR_CKSEL_MASK		= 7U << 0,
 };
 
-
-/* external API */
-int rtc_init(int recover);
-bool rtc_gpio_init(void);
-void rtc_boot(void);
-u16 rtc_get_frequency_meter(u16 val, u16 measure_src, u16 window_size);
-void rtc_read(u16 addr, u16 *rdata);
-void rtc_write(u16 addr, u16 wdata);
-
 #endif /* SOC_MEDIATEK_MT8186_RTC_H */
diff --git a/src/soc/mediatek/mt8188/include/soc/rtc.h b/src/soc/mediatek/mt8188/include/soc/rtc.h
index 67a67017d9..7947f346cf 100644
--- a/src/soc/mediatek/mt8188/include/soc/rtc.h
+++ b/src/soc/mediatek/mt8188/include/soc/rtc.h
@@ -4,6 +4,7 @@
 #define SOC_MEDIATEK_MT8188_RTC_H
 
 #include <soc/pmif.h>
+#include <soc/rtc_common.h>
 #include <soc/rtc_reg_common.h>
 #include <stdbool.h>
 
@@ -82,11 +83,4 @@ enum {
 	RTC_K_EOSC_RSV_2	= 1 << 10,
 };
 
-void rtc_read(u16 addr, u16 *rdata);
-void rtc_write(u16 addr, u16 wdata);
-int rtc_init(int recover);
-bool rtc_gpio_init(void);
-void rtc_boot(void);
-u16 rtc_get_frequency_meter(u16 val, u16 measure_src, u16 window_size);
-
 #endif /* SOC_MEDIATEK_MT8188_RTC_H */
diff --git a/src/soc/mediatek/mt8192/include/soc/rtc.h b/src/soc/mediatek/mt8192/include/soc/rtc.h
index 10a529ad4b..0df519f15f 100644
--- a/src/soc/mediatek/mt8192/include/soc/rtc.h
+++ b/src/soc/mediatek/mt8192/include/soc/rtc.h
@@ -4,6 +4,7 @@
 #define SOC_MEDIATEK_MT8192_RTC_H
 
 #include <soc/pmif.h>
+#include <soc/rtc_common.h>
 #include <soc/rtc_reg_common.h>
 #include <stdbool.h>
 
@@ -83,10 +84,4 @@ enum {
 	RTC_K_EOSC_RSV_2	= 1 << 10,
 };
 
-void rtc_read(u16 addr, u16 *rdata);
-void rtc_write(u16 addr, u16 wdata);
-int rtc_init(int recover);
-bool rtc_gpio_init(void);
-void rtc_boot(void);
-u16 rtc_get_frequency_meter(u16 val, u16 measure_src, u16 window_size);
 #endif /* SOC_MEDIATEK_MT8192_RTC_H */
diff --git a/src/soc/mediatek/mt8195/include/soc/rtc.h b/src/soc/mediatek/mt8195/include/soc/rtc.h
index 342aadf776..3210ac1be2 100644
--- a/src/soc/mediatek/mt8195/include/soc/rtc.h
+++ b/src/soc/mediatek/mt8195/include/soc/rtc.h
@@ -4,6 +4,7 @@
 #define SOC_MEDIATEK_MT8195_RTC_H
 
 #include <soc/pmif.h>
+#include <soc/rtc_common.h>
 #include <soc/rtc_reg_common.h>
 #include <stdbool.h>
 
@@ -83,10 +84,4 @@ enum {
 	RTC_K_EOSC_RSV_2	= 1 << 10,
 };
 
-void rtc_read(u16 addr, u16 *rdata);
-void rtc_write(u16 addr, u16 wdata);
-int rtc_init(int recover);
-bool rtc_gpio_init(void);
-void rtc_boot(void);
-u16 rtc_get_frequency_meter(u16 val, u16 measure_src, u16 window_size);
 #endif /* SOC_MEDIATEK_MT8195_RTC_H */
diff --git a/src/soc/mediatek/mt8196/include/soc/mt6685_rtc.h b/src/soc/mediatek/mt8196/include/soc/mt6685_rtc.h
index aa576ff38c..e46fd90ff6 100644
--- a/src/soc/mediatek/mt8196/include/soc/mt6685_rtc.h
+++ b/src/soc/mediatek/mt8196/include/soc/mt6685_rtc.h
@@ -147,7 +147,4 @@
 #define SCK_TOP_XTAL_SEL_MASK		0x1
 #define SCK_TOP_XTAL_SEL_SHIFT		0
 
-/* Complete the RTC initialization process and register settings. */
-void rtc_boot(void);
-
 #endif /* SOC_MEDIATEK_MT8196_MT6685_RTC_H */
diff --git a/src/soc/mediatek/mt8196/include/soc/rtc.h b/src/soc/mediatek/mt8196/include/soc/rtc.h
index ba90669671..b315998713 100644
--- a/src/soc/mediatek/mt8196/include/soc/rtc.h
+++ b/src/soc/mediatek/mt8196/include/soc/rtc.h
@@ -66,11 +66,6 @@ struct rtc_clk_freq {
 	u16 fqm26m_target_ck;
 };
 
-int rtc_init(int recover);
-bool rtc_gpio_init(void);
-u16 rtc_get_frequency_meter(u16 val, u16 measure_src, u16 window_size);
 void rtc_get_time(struct rtc_time *tm);
-void rtc_read(u16 addr, u16 *rdata);
-void rtc_write(u16 addr, u16 wdata);
 
 #endif /* SOC_MEDIATEK_MT8196_RTC_H */

From abd0f60298cff49a68492f3c4e6304ae6159d0f9 Mon Sep 17 00:00:00 2001
From: Yidi Lin <yidilin@chromium.org>
Date: Wed, 19 Mar 2025 17:59:36 +0800
Subject: [PATCH 0462/3886] soc/mediatek/common: Add rtc_mt6359p.h for SoCs
 using mt6359p RTC

MT8188, MT8192 and MT8195 use mt6359p RTC and share the same RTC
definitions. Move the definitions to rtc_mt6359p.h and remove duplicate
definitions.

BUG=b:391067089
TEST=build coreboot for asurada, cherry and geralt

Change-Id: I6e60148e1847171c6ab6b6dbee2fd706f3c3a47f
Signed-off-by: Yidi Lin <yidilin@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86928
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
---
 .../mediatek/common/include/soc/rtc_mt6359p.h | 81 +++++++++++++++++++
 src/soc/mediatek/mt8188/include/soc/rtc.h     | 76 +----------------
 src/soc/mediatek/mt8192/include/soc/rtc.h     | 77 +-----------------
 src/soc/mediatek/mt8195/include/soc/rtc.h     | 77 +-----------------
 4 files changed, 84 insertions(+), 227 deletions(-)
 create mode 100644 src/soc/mediatek/common/include/soc/rtc_mt6359p.h

diff --git a/src/soc/mediatek/common/include/soc/rtc_mt6359p.h b/src/soc/mediatek/common/include/soc/rtc_mt6359p.h
new file mode 100644
index 0000000000..fcae61e914
--- /dev/null
+++ b/src/soc/mediatek/common/include/soc/rtc_mt6359p.h
@@ -0,0 +1,81 @@
+/* SPDX-License-Identifier: GPL-2.0-only OR MIT */
+
+#ifndef SOC_MEDIATEK_RTC_MT6359P_H
+#define SOC_MEDIATEK_RTC_MT6359P_H
+
+/* RTC registers */
+enum {
+	RTC_BBPU_ENABLE_ALARM	= 1U << 0,
+	RTC_BBPU_SPAR_SW	= 1U << 1,
+	RTC_BBPU_RESET_SPAR	= 1U << 2,
+	RTC_BBPU_RESET_ALARM	= 1U << 3,
+	RTC_BBPU_CLRPKY	= 1U << 4,
+	RTC_BBPU_RELOAD	= 1U << 5,
+	RTC_BBPU_CBUSY	= 1U << 6,
+	RTC_CBUSY_TIMEOUT_US = 1000000,
+};
+
+enum {
+	RTC_XOSCCALI_MASK	= 0x1F << 0,
+	RTC_XOSC32_ENB		= 1U << 5,
+	RTC_EMB_HW_MODE		= 0U << 6,
+	RTC_EMB_K_EOSC32_MODE	= 1U << 6,
+	RTC_EMB_SW_DCXO_MODE	= 2U << 6,
+	RTC_EMB_SW_EOSC32_MODE	= 3U << 6,
+	RTC_EMBCK_SEL_MODE_MASK	= 3U << 6,
+	RTC_EMBCK_SRC_SEL	= 1U << 8,
+	RTC_EMBCK_SEL_OPTION	= 1U << 9,
+	RTC_GPS_CKOUT_EN	= 1U << 10,
+	RTC_EOSC32_VCT_EN	= 1U << 11,
+	RTC_EOSC32_CHOP_EN	= 1U << 12,
+	RTC_GP_OSC32_CON	= 2U << 13,
+	RTC_REG_XOSC32_ENB	= 1U << 15,
+};
+
+enum {
+	OSC32CON_ANALOG_SETTING = RTC_GP_OSC32_CON | RTC_EOSC32_CHOP_EN |
+		RTC_EOSC32_VCT_EN | RTC_GPS_CKOUT_EN | RTC_EMBCK_SEL_OPTION |
+		RTC_EMB_K_EOSC32_MODE,
+};
+
+enum {
+	PMIC_RG_BANK_FQMTR_RST = 0x522,
+};
+
+enum {
+	PMIC_RG_FQMTR_DCXO26M_EN_SHIFT = 4,
+	PMIC_RG_BANK_FQMTR_RST_SHIFT = 6,
+};
+
+/* PMIC frequency meter definition */
+enum {
+	PMIC_RG_FQMTR_CKSEL	= 0x0118,
+	PMIC_RG_FQMTR_RST	= 0x013A,
+	PMIC_RG_FQMTR_CON0	= 0x0546,
+	PMIC_RG_FQMTR_WINSET	= 0x0548,
+	PMIC_RG_FQMTR_DATA	= 0x054A,
+	FQMTR_TIMEOUT_US	= 8000,
+};
+
+enum {
+	PMIC_FQMTR_FIX_CLK_26M		= 0U << 0,
+	PMIC_FQMTR_FIX_CLK_XOSC_32K_DET	= 1U << 0,
+	PMIC_FQMTR_FIX_CLK_EOSC_32K	= 2U << 0,
+	PMIC_FQMTR_FIX_CLK_RTC_32K	= 3U << 0,
+	PMIC_FQMTR_FIX_CLK_DCXO1M_CK	= 4U << 0,
+	PMIC_FQMTR_FIX_CLK_TCK_SEC	= 5U << 0,
+	PMIC_FQMTR_FIX_CLK_PMU_32K	= 6U << 0,
+	PMIC_FQMTR_CKSEL_MASK		= 7U << 0,
+};
+
+enum {
+	RTC_TC_MTH_MASK = 0xf,
+};
+
+enum {
+	RTC_K_EOSC_RSV_0	= 1 << 8,
+	RTC_K_EOSC_RSV_1	= 1 << 9,
+	RTC_K_EOSC_RSV_2	= 1 << 10,
+};
+
+#endif /* SOC_MEDIATEK_RTC_MT6359P_H */
diff --git a/src/soc/mediatek/mt8188/include/soc/rtc.h b/src/soc/mediatek/mt8188/include/soc/rtc.h
index 7947f346cf..5278aff5e4 100644
--- a/src/soc/mediatek/mt8188/include/soc/rtc.h
+++ b/src/soc/mediatek/mt8188/include/soc/rtc.h
@@ -5,82 +5,8 @@
 
 #include <soc/pmif.h>
 #include <soc/rtc_common.h>
+#include <soc/rtc_mt6359p.h>
 #include <soc/rtc_reg_common.h>
 #include <stdbool.h>
 
-/* RTC registers */
-enum {
-	RTC_BBPU_ENABLE_ALARM	= 1U << 0,
-	RTC_BBPU_SPAR_SW	= 1U << 1,
-	RTC_BBPU_RESET_SPAR	= 1U << 2,
-	RTC_BBPU_RESET_ALARM	= 1U << 3,
-	RTC_BBPU_CLRPKY	= 1U << 4,
-	RTC_BBPU_RELOAD	= 1U << 5,
-	RTC_BBPU_CBUSY	= 1U << 6,
-	RTC_CBUSY_TIMEOUT_US = 1000000,
-};
-
-enum {
-	RTC_XOSCCALI_MASK	= 0x1F << 0,
-	RTC_XOSC32_ENB		= 1U << 5,
-	RTC_EMB_HW_MODE		= 0U << 6,
-	RTC_EMB_K_EOSC32_MODE	= 1U << 6,
-	RTC_EMB_SW_DCXO_MODE	= 2U << 6,
-	RTC_EMB_SW_EOSC32_MODE	= 3U << 6,
-	RTC_EMBCK_SEL_MODE_MASK	= 3U << 6,
-	RTC_EMBCK_SRC_SEL	= 1U << 8,
-	RTC_EMBCK_SEL_OPTION	= 1U << 9,
-	RTC_GPS_CKOUT_EN	= 1U << 10,
-	RTC_EOSC32_VCT_EN	= 1U << 11,
-	RTC_EOSC32_CHOP_EN	= 1U << 12,
-	RTC_GP_OSC32_CON	= 2U << 13,
-	RTC_REG_XOSC32_ENB	= 1U << 15,
-};
-
-enum {
-	OSC32CON_ANALOG_SETTING = RTC_GP_OSC32_CON | RTC_EOSC32_CHOP_EN |
-		RTC_EOSC32_VCT_EN | RTC_GPS_CKOUT_EN | RTC_EMBCK_SEL_OPTION |
-		RTC_EMB_K_EOSC32_MODE,
-};
-
-enum {
-	PMIC_RG_BANK_FQMTR_RST = 0x522,
-};
-
-enum {
-	PMIC_RG_FQMTR_DCXO26M_EN_SHIFT = 4,
-	PMIC_RG_BANK_FQMTR_RST_SHIFT = 6,
-};
-
-/* PMIC frequency meter definition */
-enum {
-	PMIC_RG_FQMTR_CKSEL	= 0x0118,
-	PMIC_RG_FQMTR_RST	= 0x013A,
-	PMIC_RG_FQMTR_CON0	= 0x0546,
-	PMIC_RG_FQMTR_WINSET	= 0x0548,
-	PMIC_RG_FQMTR_DATA	= 0x054A,
-	FQMTR_TIMEOUT_US	= 8000,
-};
-
-enum {
-	PMIC_FQMTR_FIX_CLK_26M		= 0U << 0,
-	PMIC_FQMTR_FIX_CLK_XOSC_32K_DET	= 1U << 0,
-	PMIC_FQMTR_FIX_CLK_EOSC_32K	= 2U << 0,
-	PMIC_FQMTR_FIX_CLK_RTC_32K	= 3U << 0,
-	PMIC_FQMTR_FIX_CLK_DCXO1M_CK	= 4U << 0,
-	PMIC_FQMTR_FIX_CLK_TCK_SEC	= 5U << 0,
-	PMIC_FQMTR_FIX_CLK_PMU_32K	= 6U << 0,
-	PMIC_FQMTR_CKSEL_MASK		= 7U << 0,
-};
-
-enum {
-	RTC_TC_MTH_MASK = 0xf,
-};
-
-enum {
-	RTC_K_EOSC_RSV_0	= 1 << 8,
-	RTC_K_EOSC_RSV_1	= 1 << 9,
-	RTC_K_EOSC_RSV_2	= 1 << 10,
-};
-
 #endif /* SOC_MEDIATEK_MT8188_RTC_H */
diff --git a/src/soc/mediatek/mt8192/include/soc/rtc.h b/src/soc/mediatek/mt8192/include/soc/rtc.h
index 0df519f15f..ee06801869 100644
--- a/src/soc/mediatek/mt8192/include/soc/rtc.h
+++ b/src/soc/mediatek/mt8192/include/soc/rtc.h
@@ -5,83 +5,8 @@
 
 #include <soc/pmif.h>
 #include <soc/rtc_common.h>
+#include <soc/rtc_mt6359p.h>
 #include <soc/rtc_reg_common.h>
 #include <stdbool.h>
 
-/* RTC registers */
-enum {
-	RTC_BBPU_ENABLE_ALARM	= 1U << 0,
-	RTC_BBPU_SPAR_SW	= 1U << 1,
-	RTC_BBPU_RESET_SPAR	= 1U << 2,
-	RTC_BBPU_RESET_ALARM	= 1U << 3,
-	RTC_BBPU_CLRPKY	= 1U << 4,
-	RTC_BBPU_RELOAD	= 1U << 5,
-	RTC_BBPU_CBUSY	= 1U << 6,
-	RTC_CBUSY_TIMEOUT_US = 1000000,
-};
-
-enum {
-	RTC_XOSCCALI_MASK	= 0x1F << 0,
-	RTC_XOSC32_ENB		= 1U << 5,
-	RTC_EMB_HW_MODE		= 0U << 6,
-	RTC_EMB_K_EOSC32_MODE	= 1U << 6,
-	RTC_EMB_SW_DCXO_MODE	= 2U << 6,
-	RTC_EMB_SW_EOSC32_MODE	= 3U << 6,
-	RTC_EMBCK_SEL_MODE_MASK	= 3U << 6,
-	RTC_EMBCK_SRC_SEL	= 1U << 8,
-	RTC_EMBCK_SEL_OPTION	= 1U << 9,
-	RTC_GPS_CKOUT_EN	= 1U << 10,
-	RTC_EOSC32_VCT_EN	= 1U << 11,
-	RTC_EOSC32_CHOP_EN	= 1U << 12,
-	RTC_GP_OSC32_CON	= 2U << 13,
-	RTC_REG_XOSC32_ENB	= 1U << 15,
-};
-
-enum {
-	OSC32CON_ANALOG_SETTING = RTC_GP_OSC32_CON | RTC_EOSC32_CHOP_EN |
-		RTC_EOSC32_VCT_EN | RTC_GPS_CKOUT_EN | RTC_EMBCK_SEL_OPTION |
-		RTC_EMB_K_EOSC32_MODE,
-};
-
-enum {
-	PMIC_RG_BANK_FQMTR_RST = 0x522,
-};
-
-enum {
-	PMIC_RG_FQMTR_DCXO26M_EN_SHIFT = 4,
-	PMIC_RG_BANK_FQMTR_RST_SHIFT = 6,
-};
-
-/* PMIC Frequency Meter Definition */
-enum {
-	PMIC_RG_FQMTR_CKSEL	= 0x0118,
-	PMIC_RG_FQMTR_RST	= 0x013A,
-	PMIC_RG_FQMTR_CON0	= 0x0546,
-	PMIC_RG_FQMTR_WINSET	= 0x0548,
-	PMIC_RG_FQMTR_DATA	= 0x054A,
-	FQMTR_TIMEOUT_US	= 8000,
-};
-
-enum {
-	PMIC_FQMTR_FIX_CLK_26M		= 0U << 0,
-	PMIC_FQMTR_FIX_CLK_XOSC_32K_DET	= 1U << 0,
-	PMIC_FQMTR_FIX_CLK_EOSC_32K	= 2U << 0,
-	PMIC_FQMTR_FIX_CLK_RTC_32K	= 3U << 0,
-	PMIC_FQMTR_FIX_CLK_DCXO1M_CK	= 4U << 0,
-	PMIC_FQMTR_FIX_CLK_TCK_SEC	= 5U << 0,
-	PMIC_FQMTR_FIX_CLK_PMU_32K	= 6U << 0,
-	PMIC_FQMTR_CKSEL_MASK		= 7U << 0,
-};
-
-
-enum {
-	RTC_TC_MTH_MASK = 0xf,
-};
-
-enum {
-	RTC_K_EOSC_RSV_0	= 1 << 8,
-	RTC_K_EOSC_RSV_1	= 1 << 9,
-	RTC_K_EOSC_RSV_2	= 1 << 10,
-};
-
 #endif /* SOC_MEDIATEK_MT8192_RTC_H */
diff --git a/src/soc/mediatek/mt8195/include/soc/rtc.h b/src/soc/mediatek/mt8195/include/soc/rtc.h
index 3210ac1be2..a2c066d481 100644
--- a/src/soc/mediatek/mt8195/include/soc/rtc.h
+++ b/src/soc/mediatek/mt8195/include/soc/rtc.h
@@ -5,83 +5,8 @@
 
 #include <soc/pmif.h>
 #include <soc/rtc_common.h>
+#include <soc/rtc_mt6359p.h>
 #include <soc/rtc_reg_common.h>
 #include <stdbool.h>
 
-/* RTC registers */
-enum {
-	RTC_BBPU_ENABLE_ALARM	= 1U << 0,
-	RTC_BBPU_SPAR_SW	= 1U << 1,
-	RTC_BBPU_RESET_SPAR	= 1U << 2,
-	RTC_BBPU_RESET_ALARM	= 1U << 3,
-	RTC_BBPU_CLRPKY	= 1U << 4,
-	RTC_BBPU_RELOAD	= 1U << 5,
-	RTC_BBPU_CBUSY	= 1U << 6,
-	RTC_CBUSY_TIMEOUT_US = 1000000,
-};
-
-enum {
-	RTC_XOSCCALI_MASK	= 0x1F << 0,
-	RTC_XOSC32_ENB		= 1U << 5,
-	RTC_EMB_HW_MODE		= 0U << 6,
-	RTC_EMB_K_EOSC32_MODE	= 1U << 6,
-	RTC_EMB_SW_DCXO_MODE	= 2U << 6,
-	RTC_EMB_SW_EOSC32_MODE	= 3U << 6,
-	RTC_EMBCK_SEL_MODE_MASK	= 3U << 6,
-	RTC_EMBCK_SRC_SEL	= 1U << 8,
-	RTC_EMBCK_SEL_OPTION	= 1U << 9,
-	RTC_GPS_CKOUT_EN	= 1U << 10,
-	RTC_EOSC32_VCT_EN	= 1U << 11,
-	RTC_EOSC32_CHOP_EN	= 1U << 12,
-	RTC_GP_OSC32_CON	= 2U << 13,
-	RTC_REG_XOSC32_ENB	= 1U << 15,
-};
-
-enum {
-	OSC32CON_ANALOG_SETTING = RTC_GP_OSC32_CON | RTC_EOSC32_CHOP_EN |
-		RTC_EOSC32_VCT_EN | RTC_GPS_CKOUT_EN | RTC_EMBCK_SEL_OPTION |
-		RTC_EMB_K_EOSC32_MODE,
-};
-
-enum {
-	PMIC_RG_BANK_FQMTR_RST = 0x522,
-};
-
-enum {
-	PMIC_RG_FQMTR_DCXO26M_EN_SHIFT = 4,
-	PMIC_RG_BANK_FQMTR_RST_SHIFT = 6,
-};
-
-/* PMIC Frequency Meter Definition */
-enum {
-	PMIC_RG_FQMTR_CKSEL	= 0x0118,
-	PMIC_RG_FQMTR_RST	= 0x013A,
-	PMIC_RG_FQMTR_CON0	= 0x0546,
-	PMIC_RG_FQMTR_WINSET	= 0x0548,
-	PMIC_RG_FQMTR_DATA	= 0x054A,
-	FQMTR_TIMEOUT_US	= 8000,
-};
-
-enum {
-	PMIC_FQMTR_FIX_CLK_26M		= 0U << 0,
-	PMIC_FQMTR_FIX_CLK_XOSC_32K_DET	= 1U << 0,
-	PMIC_FQMTR_FIX_CLK_EOSC_32K	= 2U << 0,
-	PMIC_FQMTR_FIX_CLK_RTC_32K	= 3U << 0,
-	PMIC_FQMTR_FIX_CLK_DCXO1M_CK	= 4U << 0,
-	PMIC_FQMTR_FIX_CLK_TCK_SEC	= 5U << 0,
-	PMIC_FQMTR_FIX_CLK_PMU_32K	= 6U << 0,
-	PMIC_FQMTR_CKSEL_MASK		= 7U << 0,
-};
-
-
-enum {
-	RTC_TC_MTH_MASK = 0xf,
-};
-
-enum {
-	RTC_K_EOSC_RSV_0	= 1 << 8,
-	RTC_K_EOSC_RSV_1	= 1 << 9,
-	RTC_K_EOSC_RSV_2	= 1 << 10,
-};
-
 #endif /* SOC_MEDIATEK_MT8195_RTC_H */

From b033367e61a8526e0581140929c61d09600c582f Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Thu, 27 Feb 2025 19:57:53 +0000
Subject: [PATCH 0463/3886] soc/intel/meteorlake: Add support for USB wake up

Add the same wakeup method that Alder Lake uses to Meteor Lake.

Test=boot `starlabs/starbook/mtl` and check USB devices can wake.

Change-Id: I67da6af619db947ab4830fa2d9904f3e70fbfd21
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86628
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
---
 src/soc/intel/meteorlake/acpi/xhci.asl | 17 +++++++++++++++++
 1 file changed, 17 insertions(+)

diff --git a/src/soc/intel/meteorlake/acpi/xhci.asl b/src/soc/intel/meteorlake/acpi/xhci.asl
index 38850508cb..022fbd1430 100644
--- a/src/soc/intel/meteorlake/acpi/xhci.asl
+++ b/src/soc/intel/meteorlake/acpi/xhci.asl
@@ -2,6 +2,9 @@
 
 #include <soc/gpe.h>
 
+/* Include UWES method for enabling USB wake */
+#include <soc/intel/common/acpi/xhci_wake.asl>
+
 /* XHCI Controller 0:14.0 */
 
 Device (XHCI)
@@ -10,6 +13,20 @@ Device (XHCI)
 
 	Name (_PRW, Package () { GPE0_PME_B0, 3 })
 
+	OperationRegion (XPRT, PCI_Config, 0x00, 0x100)
+	Field (XPRT, AnyAcc, NoLock, Preserve)
+	{
+		Offset (0x10),
+		, 16,
+		XMEM, 16,	/* MEM_BASE */
+	}
+
+	Method (_DSW, 3)
+	{
+		UWES ((\U2WE & 0xFFF), PORTSCN_OFFSET, XMEM)
+		UWES ((\U3WE & 0x3F ), PORTSCXUSB3_OFFSET, XMEM)
+	}
+
 	Name (_S3D, 3)	/* D3 supported in S3 */
 	Name (_S0W, 3)	/* D3 can wake device in S0 */
 	Name (_S3W, 3)	/* D3 can wake system from S3 */

From 5c35db4324e01a80a7edfa4ee4b77da83ee7d5d1 Mon Sep 17 00:00:00 2001
From: Naresh Solanki <naresh.solanki@9elements.com>
Date: Thu, 6 Mar 2025 23:22:28 +0530
Subject: [PATCH 0464/3886] arch/x86/smbios: Enhance processor characteristics
 detection

Improve SMBIOS Type 4 table processor characteristic detection for
following:
PROCESSOR_MULTI_CORE
PROCESSOR_64BIT_CAPABLE
PROCESSOR_ENHANCED_VIRTUALIZATION
PROCESSOR_POWER_PERFORMANCE_CONTROL

Based on following reference:
1. AMD APM 24594 Appendix E (Obtaining Processor Information Via
the CPUID Instruction)
2. Intel SDM 325462 Table 3-17(Information Returned by CPUID
Instruction)

TEST=Build for Glinda SoC & Intel SPR & verified in 'dmidecode -t 4' output.
Sample output:
        Characteristics:
                64-bit capable
                Multi-Core
                Hardware Thread
                Execute Protection
                Enhanced Virtualization
                Power/Performance Control

Change-Id: I2a05724a791ef1df55aa3a759a2dc4b2c69222b3
Signed-off-by: Naresh Solanki <naresh.solanki@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86755
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
---
 src/arch/x86/smbios.c | 29 ++++++++++++++++++++++++++---
 src/include/smbios.h  |  3 +++
 2 files changed, 29 insertions(+), 3 deletions(-)

diff --git a/src/arch/x86/smbios.c b/src/arch/x86/smbios.c
index 97d5f24256..a59998e3c0 100644
--- a/src/arch/x86/smbios.c
+++ b/src/arch/x86/smbios.c
@@ -176,17 +176,40 @@ int smbios_write_type4(unsigned long *current, int handle)
 	if (cpu_have_cpuid()) {
 		res = cpuid(1);
 
+		if (((res.ebx >> 16) & 0xff) > 1)
+			characteristics |= PROCESSOR_MULTI_CORE;
+
 		if ((res.ecx) & BIT(5))
-			characteristics |= BIT(6); /* BIT6: Enhanced Virtualization */
+			characteristics |= PROCESSOR_ENHANCED_VIRTUALIZATION;
 
 		if ((res.edx) & BIT(28))
-			characteristics |= BIT(4); /* BIT4: Hardware Thread */
+			characteristics |= PROCESSOR_HARDWARE_THREAD;
+
+		if (CONFIG(SOC_INTEL_COMMON) && cpu_cpuid_extended_level() >= 6) {
+			res = cpuid(6);
+			if ((res.eax) & BIT(7)) /* Intel HWP*/
+				characteristics |= PROCESSOR_POWER_PERFORMANCE_CONTROL;
+		}
 
 		if (cpu_cpuid_extended_level() >= 0x80000001) {
 			res = cpuid(0x80000001);
 
 			if ((res.edx) & BIT(20))
-				characteristics |= BIT(5); /* BIT5: Execute Protection */
+				characteristics |= PROCESSOR_EXECUTE_PROTECTION;
+
+			if ((res.edx) & BIT(29))
+				characteristics |= PROCESSOR_64BIT_CAPABLE;
+
+			/* AMD SVM */
+			if (CONFIG(SOC_AMD_COMMON) && (res.ecx) & BIT(2))
+				characteristics |= PROCESSOR_ENHANCED_VIRTUALIZATION;
+		}
+
+		if (CONFIG(SOC_AMD_COMMON) && cpu_cpuid_extended_level() >= 0x80000007) {
+			res = cpuid(0x80000007);
+
+			if ((res.edx) & BIT(7)) /* Hardware P-state control */
+				characteristics |= PROCESSOR_POWER_PERFORMANCE_CONTROL;
 		}
 	}
 	t->processor_characteristics = characteristics | smbios_processor_characteristics();
diff --git a/src/include/smbios.h b/src/include/smbios.h
index fd44e098d4..353c3cf40b 100644
--- a/src/include/smbios.h
+++ b/src/include/smbios.h
@@ -597,6 +597,9 @@ enum smbios_processor_upgrade_field {
 /* defines for processor characteristics */
 #define PROCESSOR_64BIT_CAPABLE				(1 << 2)
 #define PROCESSOR_MULTI_CORE				(1 << 3)
+#define PROCESSOR_HARDWARE_THREAD			(1 << 4)
+#define PROCESSOR_EXECUTE_PROTECTION			(1 << 5)
+#define PROCESSOR_ENHANCED_VIRTUALIZATION		(1 << 6)
 #define PROCESSOR_POWER_PERFORMANCE_CONTROL		(1 << 7)
 
 /* defines for supported_sram_type/current_sram_type */

From a4e771a836c4de425f4a67df6fbe7595b88fba75 Mon Sep 17 00:00:00 2001
From: Derek Huang <derekhuang@google.com>
Date: Fri, 14 Mar 2025 05:09:17 +0000
Subject: [PATCH 0465/3886] mb/google/rex/var/deku: Set FORCE_PWR pin high by
 default

The Intel Hayden Bridge Re-timer drives I2C SDA low unexpectedly
which breaks the I2C communication between EC and TCPC and causes
multiple USB-C issues. This patch sets HBR FORCE_PWR pin high by
default to prevent the HBR from entering low power state to work
around the I2C issue.

BUG=b:386019934,b:380947618
TEST=Verify basic USB-C functions on Deku

Change-Id: I6eae8ad4ae1b22446b903fad276a3fbcd57ca865
Signed-off-by: Derek Huang <derekhuang@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86852
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
---
 src/mainboard/google/rex/variants/deku/gpio.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/src/mainboard/google/rex/variants/deku/gpio.c b/src/mainboard/google/rex/variants/deku/gpio.c
index 55464dd468..77e7cecdff 100644
--- a/src/mainboard/google/rex/variants/deku/gpio.c
+++ b/src/mainboard/google/rex/variants/deku/gpio.c
@@ -86,7 +86,8 @@ static const struct pad_config gpio_table[] = {
 	/* GPP_B21 : net NC is not present in the given design */
 	PAD_NC(GPP_B21, NONE),
 	/* GPP_B22 : [] ==> USB_C_FORCE_PWR */
-	PAD_CFG_GPO(GPP_B22, 0, DEEP),
+	/* TODO: Set back to 0 when the Hayden Bridge Re-timer issue is fixed (b/386019934) */
+	PAD_CFG_GPO(GPP_B22, 1, DEEP),
 	/* GPP_B23 : net NC is not present in the given design */
 	PAD_NC(GPP_B23, NONE),
 

From a3862fa8c30ed0d998f6759fe12a9682591276d9 Mon Sep 17 00:00:00 2001
From: Mark Hsieh <mark_hsieh@wistron.corp-partner.google.com>
Date: Thu, 20 Mar 2025 10:09:27 +0800
Subject: [PATCH 0466/3886] mb/google/nissa/var/joxer: Include SPD for Hynix
 H58G56CK8BX146

Add joxer new supported memory part in mem_parts_used.txt.

DRAM Part Name                 ID to assign
H58G56CK8BX146                 5 (0101)

BUG=b:236576115
TEST=USE="project_joxer emerge-nissa coreboot"

Change-Id: I4045e895694b940748b5f221ebcabaa4be064b95
Signed-off-by: Mark Hsieh <mark_hsieh@wistron.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86933
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
---
 src/mainboard/google/brya/variants/joxer/memory/Makefile.mk      | 1 +
 .../google/brya/variants/joxer/memory/dram_id.generated.txt      | 1 +
 .../google/brya/variants/joxer/memory/mem_parts_used.txt         | 1 +
 3 files changed, 3 insertions(+)

diff --git a/src/mainboard/google/brya/variants/joxer/memory/Makefile.mk b/src/mainboard/google/brya/variants/joxer/memory/Makefile.mk
index e0bd4b8e68..c99f458814 100644
--- a/src/mainboard/google/brya/variants/joxer/memory/Makefile.mk
+++ b/src/mainboard/google/brya/variants/joxer/memory/Makefile.mk
@@ -9,3 +9,4 @@ SPD_SOURCES += spd/lp5/set-0/spd-2.hex      # ID = 1(0b0001)  Parts = MT62F1G32D
 SPD_SOURCES += spd/lp5/set-0/spd-3.hex      # ID = 2(0b0010)  Parts = H58G56AK6BX069, K3LKBKB0BM-MGCP
 SPD_SOURCES += spd/lp5/set-0/spd-9.hex      # ID = 3(0b0011)  Parts = K3KL6L60GM-MGCT
 SPD_SOURCES += spd/lp5/set-0/spd-7.hex      # ID = 4(0b0100)  Parts = H58G56BK7BX068, MT62F1G32D2DS-026 WT:B, K3KL8L80CM-MGCT
+SPD_SOURCES += spd/lp5/set-0/spd-11.hex      # ID = 5(0b0101)  Parts = H58G56CK8BX146
diff --git a/src/mainboard/google/brya/variants/joxer/memory/dram_id.generated.txt b/src/mainboard/google/brya/variants/joxer/memory/dram_id.generated.txt
index 2814eed7f1..eba8b458dc 100644
--- a/src/mainboard/google/brya/variants/joxer/memory/dram_id.generated.txt
+++ b/src/mainboard/google/brya/variants/joxer/memory/dram_id.generated.txt
@@ -13,3 +13,4 @@ K3KL6L60GM-MGCT                3 (0011)
 H58G56BK7BX068                 4 (0100)
 MT62F1G32D2DS-026 WT:B         4 (0100)
 K3KL8L80CM-MGCT                4 (0100)
+H58G56CK8BX146                 5 (0101)
diff --git a/src/mainboard/google/brya/variants/joxer/memory/mem_parts_used.txt b/src/mainboard/google/brya/variants/joxer/memory/mem_parts_used.txt
index 96fbc5c01b..08f849e4f8 100644
--- a/src/mainboard/google/brya/variants/joxer/memory/mem_parts_used.txt
+++ b/src/mainboard/google/brya/variants/joxer/memory/mem_parts_used.txt
@@ -18,3 +18,4 @@ K3KL6L60GM-MGCT
 H58G56BK7BX068
 MT62F1G32D2DS-026 WT:B
 K3KL8L80CM-MGCT
+H58G56CK8BX146

From e364d32667b7b74fcc628d6d53ef38dfe33c0398 Mon Sep 17 00:00:00 2001
From: Johannes Hahn <johannes-hahn@siemens.com>
Date: Thu, 13 Feb 2025 08:56:13 +0100
Subject: [PATCH 0467/3886] mb/siemens/fa_ehl/variants/fa_ehl/spd: Add Nanya
 remove Micron SPD data

Micron SPD file was removed and Nanya-NT6AP512T32BV-J1I.spd was added
as it will be used for the final product.

Change-Id: Icbfb3a51fcb7c09bad9b70861fa58f5c957ce1ae
Signed-off-by: Johannes Hahn <johannes-hahn@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86423
Reviewed-by: Uwe Poeche <uwe.poeche@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
---
 ...-046WTB.spd.hex => Nanya_NT6AP512T32BV-J1I.spd.hex} | 10 +++++-----
 1 file changed, 5 insertions(+), 5 deletions(-)
 rename src/mainboard/siemens/fa_ehl/variants/fa_ehl/spd/{Micron_MT53E512M32D1NP-046WTB.spd.hex => Nanya_NT6AP512T32BV-J1I.spd.hex} (84%)

diff --git a/src/mainboard/siemens/fa_ehl/variants/fa_ehl/spd/Micron_MT53E512M32D1NP-046WTB.spd.hex b/src/mainboard/siemens/fa_ehl/variants/fa_ehl/spd/Nanya_NT6AP512T32BV-J1I.spd.hex
similarity index 84%
rename from src/mainboard/siemens/fa_ehl/variants/fa_ehl/spd/Micron_MT53E512M32D1NP-046WTB.spd.hex
rename to src/mainboard/siemens/fa_ehl/variants/fa_ehl/spd/Nanya_NT6AP512T32BV-J1I.spd.hex
index 79548b6f5d..6f29d359d9 100644
--- a/src/mainboard/siemens/fa_ehl/variants/fa_ehl/spd/Micron_MT53E512M32D1NP-046WTB.spd.hex
+++ b/src/mainboard/siemens/fa_ehl/variants/fa_ehl/spd/Nanya_NT6AP512T32BV-J1I.spd.hex
@@ -1,11 +1,11 @@
-23 11 11 0E 16 21 04 08 00 40 00 00 02 22 00 00
-00 00 04 0F 92 54 05 00 87 00 90 A8 90 C0 08 60
+23 11 11 0E 15 21 90 08 00 40 00 00 02 22 00 00
+00 00 05 0A 80 5D 01 00 8C 00 90 A8 90 C0 08 60
 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 E5 00 E0 4F AC
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 B7 F4
 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
@@ -18,8 +18,8 @@
 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 4D 54 35 33 45 35 31
-32 4D 33 32 44 31 4E 50 2D 30 34 36 20 00 00 00
+83 0B 00 00 00 00 00 00 00 4E 54 36 41 50 35 31
+32 54 33 32 42 56 2D 4A 31 49 20 20 20 00 83 0B
 FF 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00

From d19dd192dbe31b49df71e9afb4abaf708b2d9f78 Mon Sep 17 00:00:00 2001
From: Jeremy Compostella <jeremy.compostella@intel.com>
Date: Thu, 27 Feb 2025 09:20:34 -0800
Subject: [PATCH 0468/3886] mb/google/fatcat: Add PTL-U Fast VMode Voltage
 Regulator settings

This commit introduces the missing Fast Voltage Mode settings for the
Voltage Regulator (VR) applicable to the Intel Panther Lake (PTL)-U 15W
System on Chip (SoC) on the Google Fatcat mainboard. The configurations
have been populated in accordance with the specifications outlined in
Intel's Panther Lake Power Map document (reference number 813278). These
settings leverage the Fast Voltage Mode capabilities of the CPU cores
(IA), Graphics (GT), and System Agent (SA).

The voltage regulator settings are for PTL-U; therefore, when the
coreboot image is used on a Panther Lake H SKU, some lower performance
could be observed due to the I_TRIP value being lower than what the
device could actually use.

BUG=b:357011633

TEST=As no Panther Lake-U (PTL-U) SKUs were available, smoke tests have
     been performed on Panther Lake-H (PTL-H). We verified that the
     Firmware Support Package (FSP) successfully submitted requests to
     the pcode firmware and that once the operating system was running,
     S0iX entry and exit were operational.

Change-Id: If98edb88d7488c0b863a8f1a9654d0273de567c6
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86622
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
---
 .../variants/baseboard/fatcat/devicetree.cb     | 17 +++++++++++++++++
 1 file changed, 17 insertions(+)

diff --git a/src/mainboard/google/fatcat/variants/baseboard/fatcat/devicetree.cb b/src/mainboard/google/fatcat/variants/baseboard/fatcat/devicetree.cb
index b09f9e324b..f9c79adc8f 100644
--- a/src/mainboard/google/fatcat/variants/baseboard/fatcat/devicetree.cb
+++ b/src/mainboard/google/fatcat/variants/baseboard/fatcat/devicetree.cb
@@ -62,6 +62,23 @@ chip soc/intel/pantherlake
 	# Enable Energy Reporting
 	register "pch_pm_energy_report_enable" = "true"
 
+	# As per document 813278, the Intel PTL-U 15W SoC supports
+	# Fast V-Mode (FVM) on cores (IA), Graphics (GT), and System
+	# Agent (SA). The ICC Limit is represented in 1/4 A
+	# increments, i.e., a value of 400 = 100A.
+	# IA VR configuration
+	register "enable_fast_vmode[VR_DOMAIN_IA]" = "true"
+	register "cep_enable[VR_DOMAIN_IA]" = "true"
+	register "fast_vmode_i_trip[VR_DOMAIN_IA]" = "252" # 63A
+	# GT VR configuration
+	register "enable_fast_vmode[VR_DOMAIN_GT]" = "true"
+	register "cep_enable[VR_DOMAIN_GT]" = "true"
+	register "fast_vmode_i_trip[VR_DOMAIN_GT]" = "152" # 38A
+	# SA VR configuration
+	register "enable_fast_vmode[VR_DOMAIN_SA]" = "true"
+	register "cep_enable[VR_DOMAIN_SA]" = "true"
+	register "fast_vmode_i_trip[VR_DOMAIN_SA]" = "152" # 38A
+
 	# Enable CNVi BT
 	register "cnvi_bt_core" = "true"
 

From 3c7a984e6be3446e063063a06f3fafe09b0137fa Mon Sep 17 00:00:00 2001
From: Jeremy Compostella <jeremy.compostella@intel.com>
Date: Wed, 19 Mar 2025 12:08:26 -0700
Subject: [PATCH 0469/3886] soc/intel/adl: Correct comment on Energy Efficient
 Turbo setting

Commit 3ff85e5dcd23ec7c77b9338fb59102d85942a933 ("soc/intel/alderlake:
Make Energy Efficient Turbo configurable") made the EnergyEfficientTurbo
User Product Data (UPD) adjustable, but it did not update the comment.

Change-Id: I34b8829efcfa3210950051e9b6d4d5a3c289ec93
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86932
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
---
 src/soc/intel/alderlake/fsp_params.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/soc/intel/alderlake/fsp_params.c b/src/soc/intel/alderlake/fsp_params.c
index caa4b98807..39582b5ec6 100644
--- a/src/soc/intel/alderlake/fsp_params.c
+++ b/src/soc/intel/alderlake/fsp_params.c
@@ -1010,7 +1010,7 @@ static void fill_fsps_misc_power_params(FSP_S_CONFIG *s_cfg,
 	s_cfg->PsOnEnable = 1;
 	s_cfg->PkgCStateLimit = LIMIT_AUTO;
 
-	/* Disable Energy Efficient Turbo mode */
+	/* Set Energy Efficient Turbo mode */
 	s_cfg->EnergyEfficientTurbo = config->energy_efficient_turbo;
 
 	/* VccIn Aux Imon IccMax. Values are in 1/4 Amp increments and range is 0-512. */

From f56beb734c5a42f6a8b51f20bafc7dceeb8aae09 Mon Sep 17 00:00:00 2001
From: Bora Guvendik <bora.guvendik@intel.com>
Date: Tue, 11 Mar 2025 14:45:58 -0700
Subject: [PATCH 0470/3886] mb/intel/ptlrvp: Add DQ mapping and SPD for GCS
 board

This patch adds initial dq mapping and spd data for LP5 memory
parts for GCS board. This also configures memory based on the board id.

Memory - LPDDR5x
Vendor/Model - H58G66BK8BX067

BUG=b:398880064
TEST=Boot to OS on GCS board.

Change-Id: I268ddf2d4b6361d9dabb217c4246cb6cc0e2144c
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86834
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
---
 .../ptlrvp/variants/baseboard/ptlrvp/memory.c | 10 ++-
 .../intel/ptlrvp/variants/ptlrvp/memory.c     | 65 ++++++++++++++++++-
 .../ptlrvp/variants/ptlrvp/memory/Makefile.mk |  1 +
 .../ptlrvp/memory/dram_id.generated.txt       |  1 +
 .../variants/ptlrvp/memory/mem_parts_used.txt |  1 +
 5 files changed, 75 insertions(+), 3 deletions(-)

diff --git a/src/mainboard/intel/ptlrvp/variants/baseboard/ptlrvp/memory.c b/src/mainboard/intel/ptlrvp/variants/baseboard/ptlrvp/memory.c
index 4f621f38ce..757aafd46e 100644
--- a/src/mainboard/intel/ptlrvp/variants/baseboard/ptlrvp/memory.c
+++ b/src/mainboard/intel/ptlrvp/variants/baseboard/ptlrvp/memory.c
@@ -1,6 +1,7 @@
 /* SPDX-License-Identifier: GPL-3.0-or-later */
 
 #include <baseboard/variants.h>
+#include <ec/intel/board_id.h>
 
 static const struct mb_cfg baseboard_memcfg = {
 	.type = MEM_TYPE_LP5X,
@@ -16,7 +17,14 @@ const struct mb_cfg *__weak variant_memory_params(void)
 
 int __weak variant_memory_sku(void)
 {
-	return 0;
+	uint8_t board_id = get_rvp_board_id();
+	size_t spd_index;
+
+	printk(BIOS_INFO, "Board ID is 0x%x\n", board_id);
+
+	spd_index = (board_id == GCS_32GB || board_id == GCS_64GB) ? 1 : 0;
+
+	return spd_index;
 }
 
 bool __weak variant_is_half_populated(void)
diff --git a/src/mainboard/intel/ptlrvp/variants/ptlrvp/memory.c b/src/mainboard/intel/ptlrvp/variants/ptlrvp/memory.c
index 7fe2fcbe95..3a223e46a7 100644
--- a/src/mainboard/intel/ptlrvp/variants/ptlrvp/memory.c
+++ b/src/mainboard/intel/ptlrvp/variants/ptlrvp/memory.c
@@ -5,6 +5,66 @@
 #include <soc/romstage.h>
 #include <soc/meminit.h>
 
+static const struct mb_cfg gcs_mem_config = {
+	.type = MEM_TYPE_LP5X,
+
+	.lpx_dq_map = {
+		.ddr0 = {
+			.dq0 = {  14,  8,  15,  9,  10,  12,  11,  13, },
+			.dq1 = {  6,  7,  5,  4,  1,  3,  0,  2, },
+		},
+		.ddr1 = {
+			.dq0 = {  0,  1,  3,  4,  2,  5,  6,  7, },
+			.dq1 = {  12,  13,  14,  15,  10,  11,  8,  9, },
+		},
+		.ddr2 = {
+			.dq0 = {  10,  9,  8,  11,  12,  15,  14,  13, },
+			.dq1 = {  1,  3,  0,  2,  6,  7,  5,  4, },
+		},
+		.ddr3 = {
+			.dq0 = {  5,  6,  7,  4,  2,  3,  1,  0,},
+			.dq1 = {  15,  14,  10,  11,  12,  13,  9,  8, },
+		},
+		.ddr4 = {
+			.dq0 = {  8,  10,  9,  11,  13,  12,  14,  15, },
+			.dq1 = {  4,  5,  1,  3,  7,  0,  2,  6, },
+		},
+		.ddr5 = {
+			.dq0 = {  1,  0,  3,  2,  6,  7,  4,  5, },
+			.dq1 = {  11,  14,  10,  13,  9,  12,  8,  15, },
+		},
+		.ddr6 = {
+			.dq0 = {  10,  8,  15,  9,  13,  12,  14,  11, },
+			.dq1 = {  3,  4,  7,  0,  2,  5,  6,  1, },
+		},
+		.ddr7 = {
+			.dq0 = {  0,  1,  2,  7,  3,  6,  5,  4,  },
+			.dq1 = {  11,  15,  10,  8,  13,  9,  12,  14, },
+		},
+	},
+
+	.lpx_dqs_map = {
+		.ddr0 = { .dqs0 = 1, .dqs1 = 0 },
+		.ddr1 = { .dqs0 = 0, .dqs1 = 1 },
+		.ddr2 = { .dqs0 = 1, .dqs1 = 0 },
+		.ddr3 = { .dqs0 = 0, .dqs1 = 1 },
+		.ddr4 = { .dqs0 = 1, .dqs1 = 0 },
+		.ddr5 = { .dqs0 = 0, .dqs1 = 1 },
+		.ddr6 = { .dqs0 = 1, .dqs1 = 0 },
+		.ddr7 = { .dqs0 = 0, .dqs1 = 1 }
+	},
+
+	.ect = true, /* Early Command Training */
+
+	.lp_ddr_dq_dqs_re_training = 1,
+
+	.user_bd = BOARD_TYPE_ULT_ULX,
+
+	.lp5x_config = {
+		.ccc_config = 0xFF,
+	},
+};
+
 static const struct mb_cfg lp5_mem_config = {
 	.type = MEM_TYPE_LP5X,
 
@@ -72,9 +132,10 @@ const struct mb_cfg *variant_memory_params(void)
 	switch (board_id) {
 	case PTLP_LP5_T3_RVP:
 	case PTLP_LP5_T4_RVP:
+		return &lp5_mem_config;
 	case GCS_32GB:
 	case GCS_64GB:
-		return &lp5_mem_config;
+		return &gcs_mem_config;
 	default:
 		die("Unknown board id = 0x%x\n", board_id);
 		break;
@@ -84,5 +145,5 @@ const struct mb_cfg *variant_memory_params(void)
 void variant_get_spd_info(struct mem_spd *spd_info)
 {
 	spd_info->topo = MEM_TOPO_MEMORY_DOWN;
-	spd_info->cbfs_index = 0;
+	spd_info->cbfs_index = variant_memory_sku();
 }
diff --git a/src/mainboard/intel/ptlrvp/variants/ptlrvp/memory/Makefile.mk b/src/mainboard/intel/ptlrvp/variants/ptlrvp/memory/Makefile.mk
index 14126ce67d..1a93597f4e 100644
--- a/src/mainboard/intel/ptlrvp/variants/ptlrvp/memory/Makefile.mk
+++ b/src/mainboard/intel/ptlrvp/variants/ptlrvp/memory/Makefile.mk
@@ -5,3 +5,4 @@
 
 SPD_SOURCES =
 SPD_SOURCES += spd/lp5/set-0/spd-7.hex      # ID = 0(0b0000)  Parts = H58G56BK7BX068
+SPD_SOURCES += spd/lp5/set-0/spd-10.hex      # ID = 1(0b0001)  Parts = H58G66BK8BX067
diff --git a/src/mainboard/intel/ptlrvp/variants/ptlrvp/memory/dram_id.generated.txt b/src/mainboard/intel/ptlrvp/variants/ptlrvp/memory/dram_id.generated.txt
index 21082111da..7f7236d0ec 100644
--- a/src/mainboard/intel/ptlrvp/variants/ptlrvp/memory/dram_id.generated.txt
+++ b/src/mainboard/intel/ptlrvp/variants/ptlrvp/memory/dram_id.generated.txt
@@ -5,3 +5,4 @@
 
 DRAM Part Name                 ID to assign
 H58G56BK7BX068                 0 (0000)
+H58G66BK8BX067                 1 (0001)
diff --git a/src/mainboard/intel/ptlrvp/variants/ptlrvp/memory/mem_parts_used.txt b/src/mainboard/intel/ptlrvp/variants/ptlrvp/memory/mem_parts_used.txt
index 17ee7efc60..86a6e201d7 100644
--- a/src/mainboard/intel/ptlrvp/variants/ptlrvp/memory/mem_parts_used.txt
+++ b/src/mainboard/intel/ptlrvp/variants/ptlrvp/memory/mem_parts_used.txt
@@ -10,3 +10,4 @@
 
 # Part Name
 H58G56BK7BX068
+H58G66BK8BX067

From 18136e6e2cf25c1ed6240614e301daf107a45b08 Mon Sep 17 00:00:00 2001
From: Patrick Rudolph <patrick.rudolph@9elements.com>
Date: Tue, 4 Mar 2025 11:31:21 +0100
Subject: [PATCH 0471/3886] soc/amd/genoa_poc: Add LPC device

Add the LPC PCI device to make sure common code builds.

Document ID: 55898

Change-Id: I52b129b47f98d88cad1d656dab4d4562c7ce3394
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86706
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/soc/amd/genoa_poc/include/soc/pci_devs.h | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/src/soc/amd/genoa_poc/include/soc/pci_devs.h b/src/soc/amd/genoa_poc/include/soc/pci_devs.h
index 6f0b15aa43..ede2dc583d 100644
--- a/src/soc/amd/genoa_poc/include/soc/pci_devs.h
+++ b/src/soc/amd/genoa_poc/include/soc/pci_devs.h
@@ -18,6 +18,12 @@
 #define SMBUS_DEVFN		PCI_DEVFN(SMBUS_DEV, SMBUS_FUNC)
 #define SOC_SMBUS_DEV		_SOC_DEV(SMBUS_DEV, SMBUS_FUNC)
 
+/* LPC BUS */
+#define PCU_DEV			0x14
+#define LPC_FUNC		3
+#define LPC_DEVFN		PCI_DEVFN(PCU_DEV, LPC_FUNC)
+#define SOC_LPC_DEV		_SOC_DEV(PCU_DEV, LPC_FUNC)
+
 /* Data Fabric functions */
 #define DF_DEV			0x18
 

From 0f06d8e158e90836a640bd67791562d8e38e5f37 Mon Sep 17 00:00:00 2001
From: Patrick Rudolph <patrick.rudolph@9elements.com>
Date: Sun, 23 Feb 2025 15:34:55 +0100
Subject: [PATCH 0472/3886] soc/amd/common/block/lpc: Add ROM2 and ROM3 helper
 functions

Add functions to return the position and size of the ROM2 and ROM3
MMIO windows that mmap the SPI flash. Starting from AMD Family 17h
Model 30h (Zen 2) the ROM3 BAR is available.

ROM3 is not supported on picasso or stoneyridge.

Document ID: 56780

TEST: Verified that both functions return sane values.

Change-Id: I10d4f0fe8a38e0ba2784a9839270d5dd3398d47a
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86583
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
---
 .../amd/common/block/include/amdblocks/lpc.h  |  5 ++
 src/soc/amd/common/block/lpc/lpc_util.c       | 46 +++++++++++++++++++
 2 files changed, 51 insertions(+)

diff --git a/src/soc/amd/common/block/include/amdblocks/lpc.h b/src/soc/amd/common/block/include/amdblocks/lpc.h
index 558b608743..f85c4676cc 100644
--- a/src/soc/amd/common/block/include/amdblocks/lpc.h
+++ b/src/soc/amd/common/block/include/amdblocks/lpc.h
@@ -105,6 +105,8 @@
 
 #define LPC_WIDEIO2_GENERIC_PORT	0x90
 
+#define ROM_ADDRESS_RANGE3_START	0xa8
+
 #define LPC_ROM_DMA_SRC_ADDR		0xb0
 #define LPC_ROM_DMA_DST_ADDR		0xb4
 /* LPC register 0xb8 is DWORD, here there are definitions for byte
@@ -140,6 +142,9 @@ void lpc_tpm_decode(void);
 void lpc_tpm_decode_spi(void);
 void lpc_enable_rom(void);
 void lpc_enable_spi_prefetch(void);
+uint32_t lpc_get_rom2_region(size_t *bios_size);
+uint64_t lpc_get_rom3_region(size_t *bios_size);
+
 void lpc_disable_spi_rom_sharing(void);
 
 /**
diff --git a/src/soc/amd/common/block/lpc/lpc_util.c b/src/soc/amd/common/block/lpc/lpc_util.c
index 4097e6f734..b796f3faa4 100644
--- a/src/soc/amd/common/block/lpc/lpc_util.c
+++ b/src/soc/amd/common/block/lpc/lpc_util.c
@@ -286,6 +286,52 @@ void lpc_enable_rom(void)
 	pci_write_config16(_LPCB_DEV, ROM_ADDRESS_RANGE2_END, 0xffff);
 }
 
+/**
+ * Returns ROM2 MMIO SPI flash region in the lower MMIO space.
+ * The maximum window size is 16 MiB. It always resides in the 32-bit
+ * address space.
+ *
+ * @param bios_size Pointer where to store the ROM2 region size in bytes
+ * @return 32-bit base address of the ROM2 region.
+ */
+uint32_t lpc_get_rom2_region(size_t *bios_size)
+{
+	uint16_t start = pci_read_config16(_LPCB_DEV, ROM_ADDRESS_RANGE2_START);
+	uint16_t end = pci_read_config16(_LPCB_DEV, ROM_ADDRESS_RANGE2_END);
+
+	uint32_t rom2_start = start << 16;
+	uint32_t rom2_end = (end << 16) | 0xffff;
+
+	if (rom2_end <= rom2_start) {
+		*bios_size = 0;
+		return 0;
+	}
+
+	*bios_size = rom2_end - rom2_start + 1;
+
+	return rom2_start;
+}
+
+/**
+ * Returns ROM3 MMIO SPI flash region in the high MMIO space.
+ * Default at 0xfd00000000. The maximum window size is 64 MiB.
+ *
+ * @param bios_size Pointer where to store the ROM3 region size in bytes
+ * @return 64-bit base address of the ROM3 region.
+ */
+uint64_t lpc_get_rom3_region(size_t *bios_size)
+{
+	uint32_t lower = pci_read_config32(_LPCB_DEV, ROM_ADDRESS_RANGE3_START);
+	uint32_t upper = pci_read_config32(_LPCB_DEV, ROM_ADDRESS_RANGE3_START + 4);
+
+	if (lower || upper)
+		*bios_size = MIN(CONFIG_ROM_SIZE, 64 * MiB);
+	else
+		*bios_size = 0;
+
+	return ((uint64_t)upper << 32) | lower;
+}
+
 void lpc_enable_spi_prefetch(void)
 {
 	uint32_t dword;

From bb66d07d410139d6b2fe07ff5a39bd0c5a3e682a Mon Sep 17 00:00:00 2001
From: Patrick Rudolph <patrick.rudolph@9elements.com>
Date: Thu, 27 Feb 2025 12:52:25 +0100
Subject: [PATCH 0473/3886] soc/amd/common: Always use genoa SPI MMAP driver

Currently the generic x86 SPI flash mmap driver is being used when not
using DMA and when not on GENOA. It only works for ROM_SIZE of 16 MiB
or less and prevents boot when the ROM is bigger than that.

Use the genoa_poc SPI MMAP driver on all platforms by default as it
allows to use a ROM_SIZE greater than 16MiB. The newly introduced
Kconfig SOC_AMD_COMMON_BLOCK_SPI_MMAP is used for all platforms when
the SPI DMA driver is not in use.

This doesn't allow to access the whole SPI flash using the ROM2 MMIO
window, but it no longer prevents boot when the mainboard specifies
the correct SPI flash size in Kconfig.

TEST: Booted an AMD/birman+ with 64MiB ROM specified in Kconfig.
TEST: Booted on AMD/onyx with 32MiB ROM specified in Kconfig.

Change-Id: I39e33c71d27179212ddb1f5bcca4c5d4a39d47e4
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86618
Reviewed-by: Andy Ebrahiem <ahmet.ebrahiem@9elements.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/soc/amd/common/block/spi/Kconfig                 | 12 ++++++++++++
 src/soc/amd/common/block/spi/Makefile.mk             |  3 +++
 .../amd/{genoa_poc => common/block/spi}/mmap_boot.c  |  0
 src/soc/amd/genoa_poc/Kconfig                        |  2 +-
 src/soc/amd/genoa_poc/Makefile.mk                    |  1 -
 5 files changed, 16 insertions(+), 2 deletions(-)
 rename src/soc/amd/{genoa_poc => common/block/spi}/mmap_boot.c (100%)

diff --git a/src/soc/amd/common/block/spi/Kconfig b/src/soc/amd/common/block/spi/Kconfig
index e5f68578b0..88b118276c 100644
--- a/src/soc/amd/common/block/spi/Kconfig
+++ b/src/soc/amd/common/block/spi/Kconfig
@@ -16,6 +16,18 @@ config SOC_AMD_COMMON_BLOCK_SPI_4DW_BURST
 	help
 	  Select this option to keep the 4 DWORD burst support enabled.
 
+config SOC_AMD_COMMON_BLOCK_SPI_MMAP
+	def_bool y
+	select X86_CUSTOM_BOOTMEDIA
+	depends on SOC_AMD_COMMON_BLOCK_SPI
+	depends on !SOC_AMD_COMMON_BLOCK_LPC_SPI_DMA
+	help
+	  This option is required when CONFIG_ROM_SIZE is greater than 16 MiB.
+	  This flash driver still only mmaps 16 MiB of the flash (depending
+	  on SPI straps either the upper or lower part, by default the lower).
+	  Developers must take care to place all x86 accessible firmware
+	  components in the mmap area.
+
 config EFS_SPI_READ_MODE
 	int
 	range 0 7
diff --git a/src/soc/amd/common/block/spi/Makefile.mk b/src/soc/amd/common/block/spi/Makefile.mk
index 55ca308c02..b80e204ec3 100644
--- a/src/soc/amd/common/block/spi/Makefile.mk
+++ b/src/soc/amd/common/block/spi/Makefile.mk
@@ -1,6 +1,9 @@
 ## SPDX-License-Identifier: GPL-2.0-only
 ifeq ($(CONFIG_SOC_AMD_COMMON_BLOCK_SPI),y)
 
+all_x86-$(CONFIG_SOC_AMD_COMMON_BLOCK_SPI_MMAP) += mmap_boot.c
+smm-$(CONFIG_SOC_AMD_COMMON_BLOCK_SPI_MMAP) += mmap_boot.c
+
 bootblock-y += fch_spi_ctrl.c
 romstage-y += fch_spi_ctrl.c
 verstage-y += fch_spi_ctrl.c
diff --git a/src/soc/amd/genoa_poc/mmap_boot.c b/src/soc/amd/common/block/spi/mmap_boot.c
similarity index 100%
rename from src/soc/amd/genoa_poc/mmap_boot.c
rename to src/soc/amd/common/block/spi/mmap_boot.c
diff --git a/src/soc/amd/genoa_poc/Kconfig b/src/soc/amd/genoa_poc/Kconfig
index 25dd914bcf..3e7246b679 100644
--- a/src/soc/amd/genoa_poc/Kconfig
+++ b/src/soc/amd/genoa_poc/Kconfig
@@ -41,6 +41,7 @@ config SOC_SPECIFIC_OPTIONS
 	select SOC_AMD_COMMON_BLOCK_SMM
 	select SOC_AMD_COMMON_BLOCK_SMU
 	select SOC_AMD_COMMON_BLOCK_SMU_SX_ENTRY
+	select SOC_AMD_COMMON_BLOCK_SPI
 	select SOC_AMD_COMMON_BLOCK_SVI3
 	select SOC_AMD_COMMON_BLOCK_TSC
 	select SOC_AMD_COMMON_BLOCK_UART
@@ -49,7 +50,6 @@ config SOC_SPECIFIC_OPTIONS
 	select SOC_AMD_OPENSIL
 	select SOC_AMD_OPENSIL_GENOA_POC
 	select OPENSIL_DRIVER
-	select X86_CUSTOM_BOOTMEDIA
 
 config USE_X86_64_SUPPORT
 	default y
diff --git a/src/soc/amd/genoa_poc/Makefile.mk b/src/soc/amd/genoa_poc/Makefile.mk
index bde8b1843f..73f10a8a44 100644
--- a/src/soc/amd/genoa_poc/Makefile.mk
+++ b/src/soc/amd/genoa_poc/Makefile.mk
@@ -1,7 +1,6 @@
 ## SPDX-License-Identifier: GPL-2.0-only
 ifeq ($(CONFIG_SOC_AMD_GENOA_POC),y)
 
-all-y		+= mmap_boot.c
 all-y		+= reset.c
 all-y		+= config.c
 all-y		+= gpio.c

From e3c74ccd773133247a36ae299ca3ca3b1c059130 Mon Sep 17 00:00:00 2001
From: Naresh Solanki <naresh.solanki@9elements.com>
Date: Fri, 7 Mar 2025 00:55:54 +0530
Subject: [PATCH 0474/3886] soc/amd/common/cpu: smbios: CPU frequency & voltage

Determine CPU frequency & voltage for use in smbios type 4 table.

Reference:
AMD PPR 57254 v1.59 Section 2.1.15 CPUID Instruction

TEST=Build for glinda SoC & verify output to reflect CPU frequency
& voltage.

Sample Output:
dmidecode -t
...
        Voltage: 1.2 V
...
        Current Speed: 2600 MHz
...

Change-Id: Ibd7c7f1e299a0a8d294e7e30ae3130faae16ae22
Signed-off-by: Naresh Solanki <naresh.solanki@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86757
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/soc/amd/common/block/cpu/noncar/cpu.c | 51 +++++++++++++++++++++++
 1 file changed, 51 insertions(+)

diff --git a/src/soc/amd/common/block/cpu/noncar/cpu.c b/src/soc/amd/common/block/cpu/noncar/cpu.c
index 74b29cdb66..e67d669bb6 100644
--- a/src/soc/amd/common/block/cpu/noncar/cpu.c
+++ b/src/soc/amd/common/block/cpu/noncar/cpu.c
@@ -9,8 +9,59 @@
 #include <cpu/amd/mtrr.h>
 #include <smbios.h>
 #include <soc/iomap.h>
+#include <soc/msr.h>
 #include <types.h>
 
+#define UNSUPPORTED 0
+
+#define UNINITIALIZED ((uint64_t)-1)
+
+static union pstate_msr get_pstate0_msr(void)
+{
+	static union pstate_msr pstate_reg = { .raw = UNINITIALIZED };
+
+	struct cpuid_result res;
+
+	/* Check if we have already determined P-state support */
+	if (pstate_reg.raw == UNINITIALIZED) {
+		if (cpu_cpuid_extended_level() < CPUID_EXT_PM) {
+			pstate_reg.pstate_en = UNSUPPORTED;
+			return pstate_reg;
+		}
+
+		res = cpuid(CPUID_EXT_PM);
+
+		if (!(res.edx & BIT(7))) { /* Hardware P-state control */
+			pstate_reg.pstate_en = UNSUPPORTED;
+			return pstate_reg;
+		}
+
+		pstate_reg.raw = rdmsr(PSTATE_MSR(get_pstate_0_reg())).raw;
+	}
+
+	return pstate_reg;
+}
+
+unsigned int smbios_cpu_get_current_speed_mhz(void)
+{
+	union pstate_msr pstate_reg = get_pstate0_msr();
+
+	if (!pstate_reg.pstate_en)
+		return 0;
+
+	return get_pstate_core_freq(pstate_reg);
+}
+
+unsigned int smbios_cpu_get_voltage(void)
+{
+	union pstate_msr pstate_reg = get_pstate0_msr();
+
+	if (!pstate_reg.pstate_en)
+		return 0;
+
+	return get_pstate_core_uvolts(pstate_reg) / 100000; /* uV to (10 * V) */
+}
+
 uint32_t get_pstate_0_reg(void)
 {
 	return 0;

From 7945a31e9172ec2939cc1abc6036962a6efb601b Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Tue, 18 Mar 2025 13:49:21 +0000
Subject: [PATCH 0475/3886] mb/starlabs/starbook/adl_n: Enable S3 and S4 GPIOs

These are used to control the rails, so enable them.

Change-Id: I3607dad4e57b99048aa7669c826fed046554333a
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86920
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
---
 src/mainboard/starlabs/starbook/variants/adl_n/gpio.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/mainboard/starlabs/starbook/variants/adl_n/gpio.c b/src/mainboard/starlabs/starbook/variants/adl_n/gpio.c
index 54f597112a..a985809e0e 100644
--- a/src/mainboard/starlabs/starbook/variants/adl_n/gpio.c
+++ b/src/mainboard/starlabs/starbook/variants/adl_n/gpio.c
@@ -27,9 +27,9 @@ const struct pad_config gpio_table[] = {
 	/* GPD3:	Power Button					*/
 	PAD_CFG_NF(GPD3, UP_20K, DEEP, NF1),
 	/* GPD4:	Sleep S3					*/
-	PAD_NC(GPD4, NONE),
+	PAD_CFG_NF(GPD4, NONE, DEEP, NF1),
 	/* GPD5:	Sleep S4					*/
-	PAD_NC(GPD5, NONE),
+	PAD_CFG_NF(GPD5, NONE, DEEP, NF1),
 	/* GPD6:	Sleep A						*/
 	PAD_NC(GPD6, NONE),
 	/* GPD7:	Power Adapter Disable				*/

From 5e2448bbda75a585884e3ffcea8e0bb0d5520b4b Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Thu, 31 Aug 2023 10:13:56 -0500
Subject: [PATCH 0476/3886] mb/google/dedede: Enable GNA scoring accelerator

Enable the GNA PCI device, and include the ACPI stub so the OS driver
can attach.

TEST=build/boot Win10 on google/dedede (magpie)

Change-Id: I928bfe710e69bb43f177e3ce0c0077638233d44d
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Signed-off-by: CoolStar <coolstarorganization@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77579
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/google/dedede/dsdt.asl                         | 1 +
 src/mainboard/google/dedede/variants/baseboard/devicetree.cb | 1 +
 2 files changed, 2 insertions(+)

diff --git a/src/mainboard/google/dedede/dsdt.asl b/src/mainboard/google/dedede/dsdt.asl
index c99f4c76c3..1b67f7d394 100644
--- a/src/mainboard/google/dedede/dsdt.asl
+++ b/src/mainboard/google/dedede/dsdt.asl
@@ -24,6 +24,7 @@ DefinitionBlock(
 			#include <soc/intel/common/block/acpi/acpi/northbridge.asl>
 			#include <soc/intel/jasperlake/acpi/southbridge.asl>
 			#include <drivers/intel/gma/acpi/default_brightness_levels.asl>
+			#include <soc/intel/common/block/acpi/acpi/gna.asl>
 		}
 	}
 
diff --git a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb
index 879f4d07cb..be057ea57d 100644
--- a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb
+++ b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb
@@ -285,6 +285,7 @@ chip soc/intel/jasperlake
 			end
 		end # SA Thermal device
 		device pci 05.0 off end # IPU
+		device pci 08.0 on  end # GNA
 		device pci 09.0 off end # Intel Trace Hub
 		device pci 12.6 off end # GSPI 2
 		device pci 14.0 on

From 95cc23be9c09793bec8d1e1c072a7305204435c6 Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Wed, 12 Mar 2025 15:43:30 -0500
Subject: [PATCH 0477/3886] mb/google/volteer: Mark fingerprint reader as
 hidden

Windows doesn't have / will likely never have a signed driver for the
FPR, so set the device status as hidden so it will not appear as an
unknown device in Windows Device Manager. Linux does not check/care
about the ACPI device status.

TEST=build/boot Win11 on google/volteer (drobit), verify FPR does not
show up as unknown device under Device Manager.

Change-Id: I4b5962638128c73e1e752cf8c5f40e12deb9d96c
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86846
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
---
 src/mainboard/google/volteer/variants/baseboard/devicetree.cb | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb
index 9c7b592162..132d7cec6b 100644
--- a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb
+++ b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb
@@ -491,7 +491,7 @@ chip soc/intel/tigerlake
 				register "uid" = "1"
 				register "compat_string" = ""google,cros-ec-spi""
 				register "irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW_WAKE(GPP_C20)"
-				device spi 0 on end
+				device spi 0 hidden end
 			end # FPMCU
 		end
 		device ref pch_espi on

From 28bb7657262befa064d6b74c86c9c32912a25313 Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Sat, 15 Mar 2025 09:52:10 -0500
Subject: [PATCH 0478/3886] drivers/intel/mipi_camera: Add platform_type enum
 for JSL

Taken from an ACPI dump from a Windows JSL device with MIPI camera.

Change-Id: Ibdb2b148ebfa85c3d4f5af2594b9b8847215e726
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86863
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
---
 src/drivers/intel/mipi_camera/chip.h | 1 +
 1 file changed, 1 insertion(+)

diff --git a/src/drivers/intel/mipi_camera/chip.h b/src/drivers/intel/mipi_camera/chip.h
index d28a848eeb..696f52cc3a 100644
--- a/src/drivers/intel/mipi_camera/chip.h
+++ b/src/drivers/intel/mipi_camera/chip.h
@@ -44,6 +44,7 @@ enum intel_camera_platform_type {
 	PLATFORM_SKC = 9,
 	PLATFORM_CNL = 10,
 	PLATFORM_TGL = 12,
+	PLATFORM_JSL = 14,
 	PLATFORM_ADL = 15,
 	PLATFORM_MTL = 16,
 	PLATFORM_LNL = 17

From 6364bd827c4f982b46720ba9debe15947ccf862d Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Sun, 16 Mar 2025 15:42:40 -0500
Subject: [PATCH 0479/3886] mb/google/sarien: Update VBT for both variants

Arcada and Sarien use different VBTs in the current stock ChromeOS
firmware, so use the correct VBT for each. Files taken from images
Google_Sarien.12200.222.0.bin and Google_Arcada.12200.103.0.bin.

Change-Id: I0b07fadd34f84889c8bb186a9a22ed1bce36d6b1
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86906
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
---
 src/mainboard/google/sarien/Kconfig           |   5 -----
 .../google/sarien/variants/arcada/data.vbt    | Bin 0 -> 4608 bytes
 .../sarien/{ => variants/sarien}/data.vbt     | Bin 6144 -> 4608 bytes
 3 files changed, 5 deletions(-)
 create mode 100644 src/mainboard/google/sarien/variants/arcada/data.vbt
 rename src/mainboard/google/sarien/{ => variants/sarien}/data.vbt (75%)

diff --git a/src/mainboard/google/sarien/Kconfig b/src/mainboard/google/sarien/Kconfig
index 8dab0e0a82..c0c5e02387 100644
--- a/src/mainboard/google/sarien/Kconfig
+++ b/src/mainboard/google/sarien/Kconfig
@@ -103,11 +103,6 @@ config VBOOT
 	select HAS_RECOVERY_MRC_CACHE
 	select VBOOT_LID_SWITCH
 
-# Override the default variant behavior, since the data.vbt is the same
-# for all variants.
-config INTEL_GMA_VBT_FILE
-	default "src/mainboard/\$(MAINBOARDDIR)/data.vbt"
-
 config FMDFILE
 	default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/default.fmd" if !CHROMEOS
 
diff --git a/src/mainboard/google/sarien/variants/arcada/data.vbt b/src/mainboard/google/sarien/variants/arcada/data.vbt
new file mode 100644
index 0000000000000000000000000000000000000000..99968705ee185afa191c9b8d65bf794b04eaaaad
GIT binary patch
literal 4608
zcmeHKZERCz6h61NpYOf5y}cvQRh);9KsVWTJ7C~4!tL6Pm33>oj%AA`>!4K^3me-o
zLrExc8WKO!1T|<-_tW4X5`P*K5@RGWDv1&QNaT;v5KYwJFFxwIA6sD)S4luIoc6ru
zyyu=i?>X<seNWd9b_`&qXE+h*=|qcipu(vC2Wpp6M?9GsiA4q?BOQrkv<EN3N>Keb
zE(7E^u2u}IYB+viI$sF&*Ar|4d&l>V74pro{M0kk;}e*Q#xb&QU%rr^9G%YRFf+I-
zf;y(eIu4B$a@coh|K9v$8xoL8-WcA}w0R3+xVeSCYIrNDYFoIqZR=wai*-hmy{UL2
zG7wMpVX_}%@k}I>>Fn)D3}dQ4*&XkQ4|K*Pwva}2eB$ur*i%nWV<=jWEi^`>0cwPd
z(ecTNCX5sc*suFcVSj!qKlyAv*Ca6=<Se-D902D4p9UOUZvirZTLU+OTL!xZb_BZ&
z8iFPR%HRgD184vUAnQTMVB5jj$hOf9&VX*2CxYh<UDKT{A~d*=1zC3gPEb1O!yAgs
zp{Y=hhO^x49^;`tu+7vsG!)$z>0_d;wA@ITgQ^^wis5F4DnrO}6HF*VxW#SWdQT-!
znOu90hSW1M1g8^#ms8<@rw)>Q2#)YJc!}Q*4fb;&dk{8zWauIuCjQ#N;3Dyl#J>?=
zC3ZL&_=szX*AX`oZzGNn_Ym(P9w8nhb{>LjWm^$k#_&bXl73TyY=_tCp?J!&pR(+p
zUun^am?Z^E8pbM`a@pmA8|5zpP%gW7=n-gyKxuO^3#r?Z2}AOH%IXi0)aPo*>X*x&
zEOl+h2Dw`;`y6OPn^Z2}@0wTxyXhqI?)KT$MlO2*uD&PnFaykQ9Za$-;{2vGoL0OG
z&Y+pPtKF1K+kf*(P=7N#^t0`}i@|x<74CS=&DwX4rMAEFyZbhM*5qYA=FHMovtA2k
z|3Uj;25y~!)!lHxQ!L@7hh=wmt@*6(&Mc2Sp<m~2dNF8#q>9iDAqYSW*24<OLdvM0
z-18T4C64M$h~P7>?#d4rYoQ>4Pc62>X(E97*MW~R9AnD!jJ?S41Eze;*k=rXVM>`X
zkATgB5)oLBfCmNT1%bUP;D>_psldJx@DD+8iOetJHc^R-EF<D!QF&QpZ;1GjsC*%^
zZ$-Q=Dn5zTO1M)}(h_@I!ef$hLSpYo_=%)^BeCx#ba<6jUbe=IyS&P<m+kXP4T_^^
zyTld!UZeJKPm1*J8M29nyu!&O9lnip%Pn1$)}x$xyhY@PY|A6e`4GZGt1(nuVa`!q
z>rwN<qqU;f`SJ+4TF@e}K@A*lH4y@>M|rbkqA<a(BeYZDbo(sS1~{1pRZ}Nw7Gj_u
z>bf}N2v&tKgXy5G$u}WzCC5KNc)xk(QaZRn8#-Bufh#!;1kHJ-iWs_gYU<uIEt+<=
zg5WeOAaT%9%}hSIX7F?x>eQ~1wHEqJmW;cTLaAmRjx?3#vcWn{MQbf+HSHy%LKTay
zYO)Bm7w0C<tRsX5J$C>?aFmQXMVxcYR<R%6uAe)fo?WY^-deSQz=Kg9i<+|<1hqjs
zmz~Y2fwWl<>M`)N9f|IAPZ|i4iQvF0vbY?CxfHHaMKxN<qD1GBVko+{8~Z`u<hS3|
zwzgv6;PysssIjsZJowBQ=%3B<=b~PNY!Pa*vh1(KKrc}}hD29tBsF><U+5d%pZ_0p
z%mn|gee@VOcb}sg{q)^y%Ztdih&HW+SGp+3I92X@=<>?JChkr6iH9bYgX0Tyf2ihU
V&;Rkb=W?@$E-L+i(<%Co)1Sn2%O3y$

literal 0
HcmV?d00001

diff --git a/src/mainboard/google/sarien/data.vbt b/src/mainboard/google/sarien/variants/sarien/data.vbt
similarity index 75%
rename from src/mainboard/google/sarien/data.vbt
rename to src/mainboard/google/sarien/variants/sarien/data.vbt
index f9c498e45c3e31f24dac26e43a3f8e653826ba8c..0fb57722a22d10198bc05e4fc2cc6c831b582723 100644
GIT binary patch
delta 6
NcmZoLXi!-o1ONxL0tWy9

delta 21
WcmZorX)stIwD|!WKNF02#0UUZGY8iI


From a11a61907f7a2cd026fb362b7fe888ea40011e10 Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Sun, 16 Mar 2025 15:24:11 -0500
Subject: [PATCH 0480/3886] mb/google/sarien: Add ACPI brighness controls

Add display panel info and ACPI includes to enable display backlight
control under Windows and MacOS.

TEST=build/boot Win11 on sarien, verify brightness controls functional.

Change-Id: Ic0595c8c977f1203424ab9d91343b8e98414f594
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86907
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/google/sarien/Kconfig                      | 1 +
 src/mainboard/google/sarien/dsdt.asl                     | 1 +
 .../google/sarien/variants/sarien/devicetree.cb          | 9 ++++++++-
 3 files changed, 10 insertions(+), 1 deletion(-)

diff --git a/src/mainboard/google/sarien/Kconfig b/src/mainboard/google/sarien/Kconfig
index c0c5e02387..5f678aa4be 100644
--- a/src/mainboard/google/sarien/Kconfig
+++ b/src/mainboard/google/sarien/Kconfig
@@ -4,6 +4,7 @@ config BOARD_GOOGLE_BASEBOARD_SARIEN
 	def_bool n
 	select BOARD_ROMSIZE_KB_32768
 	select DRIVERS_GENERIC_BH720
+	select DRIVERS_GFX_GENERIC
 	select DRIVERS_I2C_GENERIC
 	select DRIVERS_I2C_HID
 	select DRIVERS_SPI_ACPI
diff --git a/src/mainboard/google/sarien/dsdt.asl b/src/mainboard/google/sarien/dsdt.asl
index 27c9be98ca..e9bac016a4 100644
--- a/src/mainboard/google/sarien/dsdt.asl
+++ b/src/mainboard/google/sarien/dsdt.asl
@@ -22,6 +22,7 @@ DefinitionBlock(
 		{
 			#include <soc/intel/common/block/acpi/acpi/northbridge.asl>
 			#include <soc/intel/cannonlake/acpi/southbridge.asl>
+			#include <drivers/intel/gma/acpi/default_brightness_levels.asl>
 		}
 		/* Per board variant mainboard hooks. */
 		#include <variant/acpi/mainboard.asl>
diff --git a/src/mainboard/google/sarien/variants/sarien/devicetree.cb b/src/mainboard/google/sarien/variants/sarien/devicetree.cb
index d47e18349f..7445bbc16b 100644
--- a/src/mainboard/google/sarien/variants/sarien/devicetree.cb
+++ b/src/mainboard/google/sarien/variants/sarien/devicetree.cb
@@ -214,7 +214,14 @@ chip soc/intel/cannonlake
 	register "gpio_pm[COMM_4]" = "MISCCFG_GPIO_PM_CONFIG_BITS"
 
 	device domain 0 on
-		device ref igpu on  end
+		device ref igpu on
+			chip drivers/gfx/generic
+				register "device_count" = "1"
+				register "device[0].name" = ""LCD0""
+				register "device[0].type" = "panel"
+				device generic 0 on end
+			end
+		end
 		device ref dptf on  end
 		device ref thermal on  end
 		device ref xhci on

From b1f0ee2c92d9858f0d27038be84cdeb3a3727719 Mon Sep 17 00:00:00 2001
From: Hualin Wei <weihualin@huaqin.corp-partner.google.com>
Date: Mon, 17 Mar 2025 09:30:33 +0800
Subject: [PATCH 0481/3886] mb/google/nissa/var/pujjoniru: Add SLP_S0_GATE_R to
 control fp feature

According to the circuit schematic diagram, FPR feature need add
SLP_S0_GATE_R with or gate to control. Use gpp_a7 as SLP_S0_GATE_R
and add a variant specific S0ix hook to fill the SSDT table to control
FPR feature during suspend and resume respectively.

BUG=b:402629294
TEST=emerge-nissa coreboot. Test by EE, GPP_A7 pull down when do suspend
and pull high when resume.

Change-Id: I2334ef1e91776b292639f56b931f650f0661a69d
Signed-off-by: Hualin Wei <weihualin@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86873
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: wen zhang <zhangwen6@huaqin.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
---
 src/mainboard/google/brya/variants/pujjoniru/gpio.c   |  2 +-
 .../brya/variants/pujjoniru/include/variant/gpio.h    |  7 +++++++
 .../google/brya/variants/pujjoniru/variant.c          | 11 +++++++++++
 3 files changed, 19 insertions(+), 1 deletion(-)

diff --git a/src/mainboard/google/brya/variants/pujjoniru/gpio.c b/src/mainboard/google/brya/variants/pujjoniru/gpio.c
index 60cf8f2889..6845a6e9fd 100644
--- a/src/mainboard/google/brya/variants/pujjoniru/gpio.c
+++ b/src/mainboard/google/brya/variants/pujjoniru/gpio.c
@@ -9,7 +9,7 @@
 /* Pad configuration in ramstage */
 static const struct pad_config override_gpio_table[] = {
 	/* A7  : NC ==> SLP_S0_GATE_R */
-	PAD_CFG_GPI(GPP_A7, NONE, DEEP),
+	PAD_CFG_GPO(GPP_A7, 1, DEEP),
 	/* A8  : GPP_A8 ==> NC */
 	PAD_NC_LOCK(GPP_A8, NONE, LOCK_CONFIG),
 	/* A11 : GPP_A11 ==> EN_SPK_PA */
diff --git a/src/mainboard/google/brya/variants/pujjoniru/include/variant/gpio.h b/src/mainboard/google/brya/variants/pujjoniru/include/variant/gpio.h
index 2bfb4bfdab..bed32dae6e 100644
--- a/src/mainboard/google/brya/variants/pujjoniru/include/variant/gpio.h
+++ b/src/mainboard/google/brya/variants/pujjoniru/include/variant/gpio.h
@@ -6,4 +6,11 @@
 #undef GPIO_PCH_WP
 /* WP signal to PCH */
 #define GPIO_PCH_WP		GPP_E17
+
+/* FPR feature need add SLP_S0_GATE_R to control.
+Pujjoniru reference baord did not have HAVE_SLP_S0_GATE.
+So we add a variant specific S0ix hook to fill the SSDT
+table to control FPR feature. GPP_A7 pull down when do
+suspend and pull high when resume. */
+#define SLP_S0_FP_EN	GPP_A7
 #endif
diff --git a/src/mainboard/google/brya/variants/pujjoniru/variant.c b/src/mainboard/google/brya/variants/pujjoniru/variant.c
index 37f4defe33..cc996d9bb5 100644
--- a/src/mainboard/google/brya/variants/pujjoniru/variant.c
+++ b/src/mainboard/google/brya/variants/pujjoniru/variant.c
@@ -6,6 +6,9 @@
 #include <sar.h>
 #include <soc/gpio_soc_defs.h>
 #include <intelblocks/graphics.h>
+#include <acpi/acpi.h>
+#include <acpi/acpigen.h>
+#include <variant/gpio.h>
 
 const char *get_wifi_sar_cbfs_filename(void)
 {
@@ -25,3 +28,11 @@ void variant_update_soc_chip_config(struct soc_intel_alderlake_config *config)
 		config->cnvi_bt_audio_offload = false;
 	}
 }
+
+void variant_generate_s0ix_hook(enum s0ix_entry entry)
+{
+	if (entry == S0IX_ENTRY)
+		acpigen_soc_clear_tx_gpio(SLP_S0_FP_EN);
+	else if (entry == S0IX_EXIT)
+		acpigen_soc_set_tx_gpio(SLP_S0_FP_EN);
+}

From c8069bc53f534865d1edb9403349d827ebf2df92 Mon Sep 17 00:00:00 2001
From: Dolan Liu <liuyong5@huaqin.corp-partner.google.com>
Date: Fri, 21 Mar 2025 10:55:06 +0800
Subject: [PATCH 0482/3886] mb/google/fatcat/var/felino: Enable SD Function

Enable SD function based on SCH_MB_V3_A
RTD3 configured by HW design,PERST# and WAKE# pin connected to PCH
PLT_RST_N and Wake_PCH_N.

BUG=b:404409600
TEST=Boot OS from SD card and card detected works on OS

Change-Id: Ib7cb09edc3f07559f0013a3c554c97349e60f117
Signed-off-by: Dolan Liu <liuyong5@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86945
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 .../fatcat/variants/felino/overridetree.cb      | 17 +++++++----------
 1 file changed, 7 insertions(+), 10 deletions(-)

diff --git a/src/mainboard/google/fatcat/variants/felino/overridetree.cb b/src/mainboard/google/fatcat/variants/felino/overridetree.cb
index 10dce4bcb0..baad62038e 100644
--- a/src/mainboard/google/fatcat/variants/felino/overridetree.cb
+++ b/src/mainboard/google/fatcat/variants/felino/overridetree.cb
@@ -197,17 +197,14 @@ device ref tbt_pcie_rp0 on end
 			end
 		end
 
-		device ref pcie_rp1 on
-			# Enable PCH PCIE x1 slot using CLK 2
-			register "pcie_rp[PCIE_RP(3)]" = "{
-				.clk_src = 2,
-				.clk_req = 2,
-				.flags = PCIE_RP_CLK_REQ_DETECT | PCIE_RP_LTR | PCIE_RP_AER,
+		device ref pcie_rp2 on
+			# Enable PCH PCIE x1 slot using CLK 6
+			register "pcie_rp[PCIE_RP(2)]" = "{
+				.clk_src = 6,
+				.clk_req = 6,
+				.flags = PCIE_RP_HOTPLUG | PCIE_RP_CLK_REQ_DETECT | PCIE_RP_LTR | PCIE_RP_AER,
+				.pcie_rp_aspm = ASPM_L1,
 			}"
-			chip soc/intel/common/block/pcie/rtd3
-				register "srcclk_pin" = "2"
-				device generic 0 on end
-			end
 		end # SD Card
 
 		device ref pcie_rp4 on

From 8da0d01ba03b666333181352e6a8a8754d892cc2 Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Thu, 20 Mar 2025 13:37:32 -0500
Subject: [PATCH 0483/3886] cpu/x86/mtrr: Make 'above4gb' variable a bool
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

No need for this to be a signed or unsigned int.

TEST=tested with rest of patch train.

Change-Id: I409c04b928211e0e89eec324fdf3fa3997c73576
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86942
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/cpu/x86/mtrr/mtrr.c    | 25 +++++++++++++------------
 src/include/cpu/x86/mtrr.h |  4 ++--
 2 files changed, 15 insertions(+), 14 deletions(-)

diff --git a/src/cpu/x86/mtrr/mtrr.c b/src/cpu/x86/mtrr/mtrr.c
index 64ab8294f5..edc6fc602e 100644
--- a/src/cpu/x86/mtrr/mtrr.c
+++ b/src/cpu/x86/mtrr/mtrr.c
@@ -361,7 +361,7 @@ static struct var_mtrr_solution mtrr_global_solution;
 
 struct var_mtrr_state {
 	struct memranges *addr_space;
-	int above4gb;
+	bool above4gb;
 	int address_bits;
 	int prepare_msrs;
 	int mtrr_index;
@@ -607,7 +607,7 @@ static void calc_var_mtrrs_with_hole(struct var_mtrr_state *var_state,
 }
 
 static void __calc_var_mtrrs(struct memranges *addr_space,
-			     int above4gb, int address_bits,
+			     bool above4gb, int address_bits,
 			     int *num_def_wb_mtrrs, int *num_def_uc_mtrrs)
 {
 	int wb_deftype_count;
@@ -661,7 +661,7 @@ static void __calc_var_mtrrs(struct memranges *addr_space,
 }
 
 static int calc_var_mtrrs(struct memranges *addr_space,
-			  int above4gb, int address_bits)
+			  bool above4gb, int address_bits)
 {
 	int wb_deftype_count = 0;
 	int uc_deftype_count = 0;
@@ -692,7 +692,7 @@ static int calc_var_mtrrs(struct memranges *addr_space,
 }
 
 static void prepare_var_mtrrs(struct memranges *addr_space, int def_type,
-				int above4gb, int address_bits,
+				bool above4gb, int address_bits,
 				struct var_mtrr_solution *sol)
 {
 	struct range_entry *r;
@@ -742,7 +742,7 @@ static int commit_var_mtrrs(const struct var_mtrr_solution *sol)
 	return 0;
 }
 
-void x86_setup_var_mtrrs(unsigned int address_bits, unsigned int above4gb)
+void x86_setup_var_mtrrs(unsigned int address_bits, bool above4gb)
 {
 	static struct var_mtrr_solution *sol = NULL;
 	struct memranges *addr_space;
@@ -752,15 +752,15 @@ void x86_setup_var_mtrrs(unsigned int address_bits, unsigned int above4gb)
 	if (sol == NULL) {
 		sol = &mtrr_global_solution;
 		sol->mtrr_default_type =
-			calc_var_mtrrs(addr_space, !!above4gb, address_bits);
+			calc_var_mtrrs(addr_space, above4gb, address_bits);
 		prepare_var_mtrrs(addr_space, sol->mtrr_default_type,
-				  !!above4gb, address_bits, sol);
+				  above4gb, address_bits, sol);
 	}
 
 	commit_var_mtrrs(sol);
 }
 
-static void _x86_setup_mtrrs(unsigned int above4gb)
+static void _x86_setup_mtrrs(bool above4gb)
 {
 	int address_size;
 
@@ -778,20 +778,21 @@ void x86_setup_mtrrs(void)
 	/* Without detect, assume the minimum */
 	total_mtrrs = MIN_MTRRS;
 	/* Always handle addresses above 4GiB. */
-	_x86_setup_mtrrs(1);
+	_x86_setup_mtrrs(true);
 }
 
 void x86_setup_mtrrs_with_detect(void)
 {
 	detect_var_mtrrs();
 	/* Always handle addresses above 4GiB. */
-	_x86_setup_mtrrs(1);
+	_x86_setup_mtrrs(true);
 }
 
 void x86_setup_mtrrs_with_detect_no_above_4gb(void)
 {
 	detect_var_mtrrs();
-	_x86_setup_mtrrs(0);
+	/* Ignore addresses above 4GiB. */
+	_x86_setup_mtrrs(false);
 }
 
 void x86_mtrr_check(void)
@@ -827,7 +828,7 @@ void mtrr_use_temp_range(uintptr_t begin, size_t size, int type)
 	const struct memranges *orig;
 	struct var_mtrr_solution sol;
 	struct memranges addr_space;
-	const int above4gb = 1; /* Cover above 4GiB by default. */
+	const bool above4gb = true; /* Cover above 4GiB by default. */
 	int address_bits;
 	static struct temp_range {
 		uintptr_t begin;
diff --git a/src/include/cpu/x86/mtrr.h b/src/include/cpu/x86/mtrr.h
index 16efbb6eef..930edfdef7 100644
--- a/src/include/cpu/x86/mtrr.h
+++ b/src/include/cpu/x86/mtrr.h
@@ -103,10 +103,10 @@ void x86_setup_mtrrs_with_detect_no_above_4gb(void);
 /*
  * x86_setup_var_mtrrs() parameters:
  * address_bits - number of physical address bits supported by cpu
- * above4gb - if set setup MTRRs for addresses above 4GiB else ignore
+ * above4gb - if true, set setup MTRRs for addresses above 4GiB else ignore
  *            memory ranges above 4GiB
  */
-void x86_setup_var_mtrrs(unsigned int address_bits, unsigned int above4gb);
+void x86_setup_var_mtrrs(unsigned int address_bits, bool above4gb);
 void enable_fixed_mtrr(void);
 /* Unhide Rd/WrDram bits and allow modification for AMD. */
 void fixed_mtrrs_expose_amd_rwdram(void);

From cff3efa1e35c8edaceca4ff5d76d28f597b6b27c Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Thu, 20 Mar 2025 13:54:32 -0500
Subject: [PATCH 0484/3886] cpu/x86/mtrr: Return number of MTRRs used via
 calc_var_mtrrs()
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

calc_var_mtrrs() calculates the number of MTRRs needed for both WB and
UC default memory types, and returns the type that uses fewer MTRRs.
Modify it to return the number of MTRRs used as well, and if that
count exceeeds the number available on the system, throw an error
and skip calling prepare_var_mtrrs() as we know it will fail.

TEST=tested with rest of patch train

Change-Id: I2be7c5b3385731f4dc9ef62de15dcf6d4cceb5d3
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86955
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/cpu/x86/mtrr/mtrr.c | 26 ++++++++++++++++----------
 1 file changed, 16 insertions(+), 10 deletions(-)

diff --git a/src/cpu/x86/mtrr/mtrr.c b/src/cpu/x86/mtrr/mtrr.c
index edc6fc602e..f5a0547e09 100644
--- a/src/cpu/x86/mtrr/mtrr.c
+++ b/src/cpu/x86/mtrr/mtrr.c
@@ -660,8 +660,8 @@ static void __calc_var_mtrrs(struct memranges *addr_space,
 	*num_def_uc_mtrrs = uc_deftype_count;
 }
 
-static int calc_var_mtrrs(struct memranges *addr_space,
-			  bool above4gb, int address_bits)
+static int calc_var_mtrrs(struct memranges *addr_space, bool above4gb, int address_bits,
+			  int *num_mtrrs_used)
 {
 	int wb_deftype_count = 0;
 	int uc_deftype_count = 0;
@@ -685,9 +685,11 @@ static int calc_var_mtrrs(struct memranges *addr_space,
 
 	if (wb_deftype_count < uc_deftype_count) {
 		printk(BIOS_DEBUG, "MTRR: WB selected as default type.\n");
+		*num_mtrrs_used = wb_deftype_count;
 		return MTRR_TYPE_WRBACK;
 	}
 	printk(BIOS_DEBUG, "MTRR: UC selected as default type.\n");
+	*num_mtrrs_used = uc_deftype_count;
 	return MTRR_TYPE_UNCACHEABLE;
 }
 
@@ -746,13 +748,14 @@ void x86_setup_var_mtrrs(unsigned int address_bits, bool above4gb)
 {
 	static struct var_mtrr_solution *sol = NULL;
 	struct memranges *addr_space;
+	int num_mtrrs_used;
 
 	addr_space = get_physical_address_space();
 
 	if (sol == NULL) {
 		sol = &mtrr_global_solution;
 		sol->mtrr_default_type =
-			calc_var_mtrrs(addr_space, above4gb, address_bits);
+			calc_var_mtrrs(addr_space, above4gb, address_bits, &num_mtrrs_used);
 		prepare_var_mtrrs(addr_space, sol->mtrr_default_type,
 				  above4gb, address_bits, sol);
 	}
@@ -830,6 +833,7 @@ void mtrr_use_temp_range(uintptr_t begin, size_t size, int type)
 	struct memranges addr_space;
 	const bool above4gb = true; /* Cover above 4GiB by default. */
 	int address_bits;
+	int num_mtrrs_used;
 	static struct temp_range {
 		uintptr_t begin;
 		size_t size;
@@ -882,14 +886,16 @@ void mtrr_use_temp_range(uintptr_t begin, size_t size, int type)
 	address_bits = cpu_phys_address_size();
 	memset(&sol, 0, sizeof(sol));
 	sol.mtrr_default_type =
-		calc_var_mtrrs(&addr_space, above4gb, address_bits);
-	prepare_var_mtrrs(&addr_space, sol.mtrr_default_type,
-				above4gb, address_bits, &sol);
+		calc_var_mtrrs(&addr_space, above4gb, address_bits, &num_mtrrs_used);
 
-	if (commit_var_mtrrs(&sol) < 0)
-		printk(BIOS_WARNING, "Unable to insert temporary MTRR range: 0x%016llx - 0x%016llx size 0x%08llx type %d\n",
-			(long long)begin, (long long)begin + size - 1,
-			(long long)size, type);
+	if (num_mtrrs_used <= total_mtrrs)
+		prepare_var_mtrrs(&addr_space, sol.mtrr_default_type, above4gb, address_bits, &sol);
+	else
+		printk(BIOS_ERR, "Not enough MTRRs: %d needed vs %d available\n", num_mtrrs_used, total_mtrrs);
+
+	if (num_mtrrs_used > total_mtrrs || commit_var_mtrrs(&sol) < 0)
+		printk(BIOS_ERR, "Unable to insert temporary MTRR range: 0x%016llx - 0x%016llx size 0x%08llx type %d\n",
+				(long long)begin, (long long)begin + size - 1, (long long)size, type);
 	else
 		put_back_original_solution = true;
 

From 2da8d8affcb3d8cb1e8b9a39b5e4657d2d6f55bf Mon Sep 17 00:00:00 2001
From: Kapil Porwal <kapilporwal@google.com>
Date: Sat, 22 Mar 2025 02:33:22 +0530
Subject: [PATCH 0485/3886] mb/google/var/trulo: Fix ISH firmare name

Use the ISH firmware file name as in rootfs.

BUG=b:401138236
TEST=suspend_stress_test is successful.

Change-Id: I29fbb4d9f04c23c1499dff5ffeab93e70675ae51
Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86974
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
---
 .../google/brya/variants/baseboard/trulo/devicetree.cb          | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/mainboard/google/brya/variants/baseboard/trulo/devicetree.cb b/src/mainboard/google/brya/variants/baseboard/trulo/devicetree.cb
index 8a20256f51..3d0b9d7d3a 100644
--- a/src/mainboard/google/brya/variants/baseboard/trulo/devicetree.cb
+++ b/src/mainboard/google/brya/variants/baseboard/trulo/devicetree.cb
@@ -91,7 +91,7 @@ chip soc/intel/alderlake
 		device ref tcss_xhci on end
 		device ref ish on
 			chip drivers/intel/ish
-				register "firmware_name" = ""trulo_ish.bin""
+				register "firmware_name" = ""trulo-ish.bin""
 				register "add_acpi_dma_property" = "true"
 				device generic 0 on end
 			end

From cd5e6ef3dfb09f99cad722cfd55e6c61d94dad00 Mon Sep 17 00:00:00 2001
From: Subrata Banik <subratabanik@google.com>
Date: Thu, 20 Mar 2025 14:58:12 +0530
Subject: [PATCH 0486/3886] mb/google/fatcat/var/fatcat: Add Write Protect GPIO
 to cros_gpios

This enables the crossystem utility to access WP GPIO.

TEST= wpsw_cur in crossystem reads the correct gpio

Change-Id: Iedf4d73a85e4159b4236e13d6aa8ff5e6fe2fcb1
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86938
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Pranava Y N <pranavayn@google.com>
---
 src/mainboard/google/fatcat/variants/fatcat/gpio.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/src/mainboard/google/fatcat/variants/fatcat/gpio.c b/src/mainboard/google/fatcat/variants/fatcat/gpio.c
index b0e08f0859..5214359c53 100644
--- a/src/mainboard/google/fatcat/variants/fatcat/gpio.c
+++ b/src/mainboard/google/fatcat/variants/fatcat/gpio.c
@@ -417,6 +417,7 @@ static const struct cros_gpio cros_gpios[] = {
 	CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE1_NAME),
 	CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE2_NAME),
 	CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE3_NAME),
+	CROS_GPIO_WP_AH(GPIO_PCH_WP, CROS_GPIO_DEVICE4_NAME),
 };
 
 DECLARE_CROS_GPIOS(cros_gpios);

From 2d03c4c3c3d413d956a2799e1ad83f12fec5a030 Mon Sep 17 00:00:00 2001
From: Kapil Porwal <kapilporwal@google.com>
Date: Sun, 23 Mar 2025 23:03:34 +0530
Subject: [PATCH 0487/3886] Revert "mb/google/var/trulo: Fix ISH firmare name"

This reverts commit 2da8d8affcb3d8cb1e8b9a39b5e4657d2d6f55bf.

Reason: The ISH firmware is renamed to trulo_ish.bin in the rootfs
itself hence this change is not required.

BUG=b:401138236
TEST=S0ix on Trulo and Truloti.

Change-Id: Ic21c9e2a28113dbd58ac992a380df601d058b16c
Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86976
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
Reviewed-by: Jayvik Desai <jayvik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 .../google/brya/variants/baseboard/trulo/devicetree.cb          | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/mainboard/google/brya/variants/baseboard/trulo/devicetree.cb b/src/mainboard/google/brya/variants/baseboard/trulo/devicetree.cb
index 3d0b9d7d3a..8a20256f51 100644
--- a/src/mainboard/google/brya/variants/baseboard/trulo/devicetree.cb
+++ b/src/mainboard/google/brya/variants/baseboard/trulo/devicetree.cb
@@ -91,7 +91,7 @@ chip soc/intel/alderlake
 		device ref tcss_xhci on end
 		device ref ish on
 			chip drivers/intel/ish
-				register "firmware_name" = ""trulo-ish.bin""
+				register "firmware_name" = ""trulo_ish.bin""
 				register "add_acpi_dma_property" = "true"
 				device generic 0 on end
 			end

From 4ca566343d1eae006338ea5caee271e506df222f Mon Sep 17 00:00:00 2001
From: Dolan Liu <liuyong5@huaqin.corp-partner.google.com>
Date: Fri, 21 Mar 2025 10:43:00 +0800
Subject: [PATCH 0488/3886] mb/google/fatcat/var/felino: Remove BT offload and
 Keep PMC Pin NC

Since CNVI BT Offload is not yet ready on Pantherlake and HW already
soldered these 4 pads connection onto the board, therefore keep
Pad Config NC_LOCK and BT offload disable.

BUG=b:397578690
Test=emerge-fatcat coreboot and make sure WIFI/BT works

Change-Id: I2d84e8cff499d462133143b12fa6335e76323926
Signed-off-by: Dolan Liu <liuyong5@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86944
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Pranava Y N <pranavayn@google.com>
Reviewed-by: Jayvik Desai <jayvik@google.com>
---
 .../google/fatcat/variants/felino/gpio.c      | 24 +++++++++----------
 .../fatcat/variants/felino/overridetree.cb    |  2 ++
 2 files changed, 14 insertions(+), 12 deletions(-)

diff --git a/src/mainboard/google/fatcat/variants/felino/gpio.c b/src/mainboard/google/fatcat/variants/felino/gpio.c
index 7f67a40ae6..3b2a6934e2 100644
--- a/src/mainboard/google/fatcat/variants/felino/gpio.c
+++ b/src/mainboard/google/fatcat/variants/felino/gpio.c
@@ -169,14 +169,14 @@ static const struct pad_config gpio_table[] = {
 	PAD_NC(GPP_D08, NONE),
 	/* GPP_D09:     USB_MUX_SEL */
 	PAD_CFG_GPO(GPP_D09, 1, PLTRST),
-	/* GPP_D10:     PMC_WLAN_CLK */
-	PAD_CFG_NF(GPP_D10, NONE, DEEP, NF1),
-	/* GPP_D11:     CNV_PCM_SYNC */
-	PAD_CFG_NF(GPP_D11, NONE, DEEP, NF1),
-	/* GPP_D12:     PMC_SOC_OUT */
-	PAD_CFG_NF(GPP_D12, NONE, DEEP, NF1),
-	/* GPP_D13:     PMC_SOC_IN */
-	PAD_CFG_NF(GPP_D13, NONE, DEEP, NF1),
+	/* GPP_D10:     PMC_WLAN_CLK ==> NC */
+	PAD_NC_LOCK(GPP_D10, NONE, LOCK_CONFIG),
+	/* GPP_D11:     CNV_PCM_SYNC ==> NC */
+	PAD_NC_LOCK(GPP_D11, NATIVE, LOCK_CONFIG),
+	/* GPP_D12:     PMC_SOC_OUT ==> NC */
+	PAD_NC_LOCK(GPP_D12, NATIVE, LOCK_CONFIG),
+	/* GPP_D13:     PMC_SOC_IN ==> NC */
+	PAD_NC_LOCK(GPP_D13, NATIVE, LOCK_CONFIG),
 	/* GPP_D14:     NC */
 	PAD_NC(GPP_D14, NONE),
 	/* GPP_D15:     NC */
@@ -358,8 +358,8 @@ static const struct pad_config gpio_table[] = {
 	PAD_CFG_NF(GPP_V00, NONE, DEEP, NF1),
 	/* GPP_V01:     BC_ACOK_MCP */
 	PAD_CFG_NF(GPP_V01, NONE, DEEP, NF1),
-	/* GPP_V02:     NC */
-	PAD_NC(GPP_V02, NONE),
+	/* GPP_V02:     LAN_WAKE# */
+	PAD_CFG_NF(GPP_V02, NONE, DEEP, NF1),
 	/* GPP_V03:     PWRBTN_MCP_N */
 	PAD_CFG_NF(GPP_V03, NONE, DEEP, NF1),
 	/* GPP_V04:     PM_SLP_S3_N */
@@ -378,8 +378,8 @@ static const struct pad_config gpio_table[] = {
 	PAD_NC(GPP_V10, NONE),
 	/* GPP_V11:     NC */
 	PAD_NC(GPP_V11, NONE),
-	/* GPP_V12:     NC */
-	PAD_NC(GPP_V12, NONE),
+	/* GPP_V12:     WAKE# */
+	PAD_CFG_NF(GPP_V12, NONE, DEEP, NF1),
 	/* GPP_V13:     NC */
 	PAD_NC(GPP_V13, NONE),
 	/* GPP_V14:     NC */
diff --git a/src/mainboard/google/fatcat/variants/felino/overridetree.cb b/src/mainboard/google/fatcat/variants/felino/overridetree.cb
index baad62038e..819bbaa43b 100644
--- a/src/mainboard/google/fatcat/variants/felino/overridetree.cb
+++ b/src/mainboard/google/fatcat/variants/felino/overridetree.cb
@@ -60,6 +60,8 @@ chip soc/intel/pantherlake
 
 	# Enable CNVi WiFi
 	register "cnvi_wifi_core" = "true"
+	# Disable CNVi BT Offload
+	register "cnvi_bt_audio_offload" = "false"
 
 	register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC_SKIP)" # USB2_C0
 	register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC_SKIP)" # USB2_C1

From 1518b29e229d554381580ae706c77cf9710ee6fd Mon Sep 17 00:00:00 2001
From: Keith Hui <buurin@gmail.com>
Date: Mon, 17 Mar 2025 23:50:22 -0400
Subject: [PATCH 0489/3886] Documentation/mb/hp: Revise compaq_8300_sff
 flashing verbiage

Cleans up a nit identified by Martin when adding a very similar
variant.

Change-Id: Id19054c08643cf03b2afbfe4c8929ce9dacaea5c
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86910
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nicholas Chin <nic.c3.14@gmail.com>
---
 Documentation/mainboard/hp/compaq_8300_sff.md | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/Documentation/mainboard/hp/compaq_8300_sff.md b/Documentation/mainboard/hp/compaq_8300_sff.md
index 03ee88c2f1..3d1ae444e9 100644
--- a/Documentation/mainboard/hp/compaq_8300_sff.md
+++ b/Documentation/mainboard/hp/compaq_8300_sff.md
@@ -39,8 +39,8 @@ The following things are still missing from this coreboot port:
 
 Internal flashing is possible. The SPI flash can be accessed using [flashrom],
 but you have to short the FDO pins located near the rear USB3 ports on the
-motherboard using a jumper, to temporarily disable write protections while on the
-stock firmware. Once the coreboot rom is flashed, one should remove the jumper.
+motherboard using a jumper to temporarily disable write protections while on the
+stock firmware. Remove the jumper once coreboot is installed.
 
 ### External programming
 

From 5dd0181f7b9733837331ef6ca37eb8f4db37693b Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Thu, 20 Mar 2025 13:54:32 -0500
Subject: [PATCH 0490/3886] cpu/x86/mtrr: Exclude ranges above 4G if temporary
 MTRRs exhausted

mtrr_use_temp_range() is used to temporarily cache the area(s) of RAM
to which the SPI flash is mapped, in order to speed up reading the
payload out of flash in preparation for execution. On systems with more
than 32GiB of RAM, there are not enough MTRRs available to map the
"permanent" regions below 4GiB, these temporary regions below 4GiB, and
any RAM above 4GiB due to fragmentation in the various ranges, as well
as limitations on the area covered by a single MTRR due to how they
are stored in the CPU registers.

As a workaround, if the number of MTRRs needed for the temporary map
exceeds the maximum available for  the system, retry calc_var-mtrrs()
with `above4gb` set to false.

TEST=build/boot starlabs/starbook_mtl with > 32GB RAM, verify temporary
MTRRs are able to be assigned via cbmem console log, and no boot delays
in payload loading/decompression due to the SPI flash not being cached.

Change-Id: Ia9f9a1537e7e0c2f7ce21067eceb1549d0f9ea5b
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86941
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
---
 src/cpu/x86/mtrr/mtrr.c | 8 +++++++-
 1 file changed, 7 insertions(+), 1 deletion(-)

diff --git a/src/cpu/x86/mtrr/mtrr.c b/src/cpu/x86/mtrr/mtrr.c
index f5a0547e09..0d31cab769 100644
--- a/src/cpu/x86/mtrr/mtrr.c
+++ b/src/cpu/x86/mtrr/mtrr.c
@@ -831,7 +831,7 @@ void mtrr_use_temp_range(uintptr_t begin, size_t size, int type)
 	const struct memranges *orig;
 	struct var_mtrr_solution sol;
 	struct memranges addr_space;
-	const bool above4gb = true; /* Cover above 4GiB by default. */
+	bool above4gb = true; /* Cover above 4GiB by default. */
 	int address_bits;
 	int num_mtrrs_used;
 	static struct temp_range {
@@ -888,6 +888,12 @@ void mtrr_use_temp_range(uintptr_t begin, size_t size, int type)
 	sol.mtrr_default_type =
 		calc_var_mtrrs(&addr_space, above4gb, address_bits, &num_mtrrs_used);
 
+	/* If we ran out of MTRRs, retry excluding ranges above 4GiB */
+	if (above4gb && num_mtrrs_used > total_mtrrs) {
+		printk(BIOS_WARNING, "MTRR: Ran out of variable MTRRs; retrying excluding ranges above 4GiB.\n");
+		above4gb = false;
+		sol.mtrr_default_type = calc_var_mtrrs(&addr_space, above4gb, address_bits, &num_mtrrs_used);
+	}
 	if (num_mtrrs_used <= total_mtrrs)
 		prepare_var_mtrrs(&addr_space, sol.mtrr_default_type, above4gb, address_bits, &sol);
 	else

From 6c728ba10d412cb79d910e38603f2a385cbb4674 Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Wed, 26 Feb 2025 09:16:36 +0000
Subject: [PATCH 0491/3886] mb/starlabs/{starlite,starbook}_adl: Select FSP
 Type IOT

Select FSP Type IOT so that the FSP blobs from the Intel repo are
used, as the client ones are not available.

Change-Id: Iefe8abc9741f9a77b7d55168a0ac42bf607fdb7c
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86832
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
---
 src/mainboard/starlabs/starbook/Kconfig     | 1 +
 src/mainboard/starlabs/starlite_adl/Kconfig | 1 +
 2 files changed, 2 insertions(+)

diff --git a/src/mainboard/starlabs/starbook/Kconfig b/src/mainboard/starlabs/starbook/Kconfig
index dbe9e88470..f902f96ade 100644
--- a/src/mainboard/starlabs/starbook/Kconfig
+++ b/src/mainboard/starlabs/starbook/Kconfig
@@ -91,6 +91,7 @@ config BOARD_STARLABS_STARBOOK_ADL_N
 	select BOARD_ROMSIZE_KB_16384
 	select BOARD_STARLABS_STARBOOK_ADL_COMMON
 	select DRIVERS_GFX_GENERIC
+	select FSP_TYPE_IOT
 	select SOC_INTEL_ALDERLAKE_PCH_N
 
 config BOARD_STARLABS_STARBOOK_RPL
diff --git a/src/mainboard/starlabs/starlite_adl/Kconfig b/src/mainboard/starlabs/starlite_adl/Kconfig
index e9516a9c5f..359fc9de8e 100644
--- a/src/mainboard/starlabs/starlite_adl/Kconfig
+++ b/src/mainboard/starlabs/starlite_adl/Kconfig
@@ -14,6 +14,7 @@ config BOARD_STARLABS_STARLITE_SERIES
 	select EC_STARLABS_MERLIN
 	select EC_STARLABS_NEED_ITE_BIN
 	select EC_STARLABS_POWER_LED
+	select FSP_TYPE_IOT
 	select HAVE_ACPI_RESUME
 	select HAVE_ACPI_TABLES
 	select HAVE_INTEL_PTT

From b8dced3f637935877c8cab228637db801fa228b2 Mon Sep 17 00:00:00 2001
From: David Li <David_Li@pegatron.corp-partner.google.com>
Date: Fri, 14 Mar 2025 13:46:01 +0800
Subject: [PATCH 0492/3886] mb/google/nissa/var/guren: Add new DB config HDMI
 and HDMI+1A

1. Add DB_HDMI 6 on DB_USB fw_config
2. Add DB_HDMI_1A 7 on DB_USB fw_config

BUG=b:405229505
BRANCH=firmware-nissa-15217.B
TEST=emerge-nissa coreboot chromeos-bootimage

Change-Id: I0757a87eeb97e6fcf7fbf79392786ed69e4563bb
Signed-off-by: David Li <David_Li@pegatron.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86853
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
Reviewed-by: Jayvik Desai <jayvik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
---
 src/mainboard/google/brya/variants/guren/fw_config.c     | 4 +++-
 src/mainboard/google/brya/variants/guren/overridetree.cb | 4 ++++
 src/mainboard/google/brya/variants/guren/variant.c       | 4 +++-
 3 files changed, 10 insertions(+), 2 deletions(-)

diff --git a/src/mainboard/google/brya/variants/guren/fw_config.c b/src/mainboard/google/brya/variants/guren/fw_config.c
index 52dff5c3ad..efebee2f20 100644
--- a/src/mainboard/google/brya/variants/guren/fw_config.c
+++ b/src/mainboard/google/brya/variants/guren/fw_config.c
@@ -29,7 +29,9 @@ static const struct pad_config lte_disable_pads[] = {
 
 void fw_config_gpio_padbased_override(struct pad_config *padbased_table)
 {
-	if (!fw_config_probe(FW_CONFIG(DB_USB, DB_HDMI_LTE))) {
+	if (!fw_config_probe(FW_CONFIG(DB_USB, DB_HDMI_LTE))
+		&& !fw_config_probe(FW_CONFIG(DB_USB, DB_HDMI))
+		&& !fw_config_probe(FW_CONFIG(DB_USB, DB_HDMI_1A))) {
 		printk(BIOS_INFO, "Disable HDMI GPIO pins.\n");
 		gpio_padbased_override(padbased_table, hdmi_disable_pads,
 						ARRAY_SIZE(hdmi_disable_pads));
diff --git a/src/mainboard/google/brya/variants/guren/overridetree.cb b/src/mainboard/google/brya/variants/guren/overridetree.cb
index 95c4b58307..0a62ca59b0 100644
--- a/src/mainboard/google/brya/variants/guren/overridetree.cb
+++ b/src/mainboard/google/brya/variants/guren/overridetree.cb
@@ -10,6 +10,8 @@ fw_config
 		option DB_1C_1A			3
 		option DB_1C_LTE		4
 		option DB_HDMI_LTE		5
+		option DB_HDMI			6
+		option DB_HDMI_1A		7
 	end
 	field SD_CARD 9
 		option SD_ABSENT		 0
@@ -575,6 +577,7 @@ chip soc/intel/alderlake
 						device ref usb2_port4 on
 							probe DB_USB DB_1A
 							probe DB_USB DB_1C_1A
+							probe DB_USB DB_HDMI_1A
 						end
 					end
 					chip drivers/usb/acpi
@@ -617,6 +620,7 @@ chip soc/intel/alderlake
 						device ref usb3_port2 on
 							probe DB_USB DB_1A
 							probe DB_USB DB_1C_1A
+							probe DB_USB DB_HDMI_1A
 						end
 					end
 					chip drivers/usb/acpi
diff --git a/src/mainboard/google/brya/variants/guren/variant.c b/src/mainboard/google/brya/variants/guren/variant.c
index ff71b6415e..c2c49f824e 100644
--- a/src/mainboard/google/brya/variants/guren/variant.c
+++ b/src/mainboard/google/brya/variants/guren/variant.c
@@ -12,7 +12,9 @@ const char *get_wifi_sar_cbfs_filename(void)
 
 void variant_update_soc_chip_config(struct soc_intel_alderlake_config *config)
 {
-	if (fw_config_probe(FW_CONFIG(DB_USB, DB_HDMI_LTE))) {
+	if (fw_config_probe(FW_CONFIG(DB_USB, DB_HDMI_LTE))
+		|| fw_config_probe(FW_CONFIG(DB_USB, DB_HDMI))
+		|| fw_config_probe(FW_CONFIG(DB_USB, DB_HDMI_1A))) {
 		printk(BIOS_INFO, "Enable DDI PORT 2 for HPD and DDC.\n");
 		config->ddi_ports_config[DDI_PORT_2] = DDI_ENABLE_HPD | DDI_ENABLE_DDC;
 	}

From ef80ccbc4364b6e564ec68b810f1b20512dc5feb Mon Sep 17 00:00:00 2001
From: Subrata Banik <subratabanik@google.com>
Date: Mon, 24 Mar 2025 18:22:58 +0530
Subject: [PATCH 0493/3886] mb/google/fatcat: Disable EC software sync for
 Microchip EC

This patch disables EC software sync specifically for the Microchip EC
on the fatcat/fatcat-ish board. This change selects
`GBB_FLAG_DISABLE_EC_SOFTWARE_SYNC` for boards w/ microchip EC
(EC_GOOGLE_CHROMEEC_MEC) like fatcat and fatcat-ish.

This allows other fatcat variants (Nuvoton, ITE EC AIC) to potentially
enable EC software sync, which is not compatible with the Microchip EC.

BUG=b:368278795
TEST=Verified EC software sync functionality on a Nuvoton AIC fatcat
variant.

Change-Id: I33c82c05a810c0328de5513f452505f2d560cf91
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86982
Reviewed-by: Jayvik Desai <jayvik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
---
 src/mainboard/google/fatcat/Kconfig | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/mainboard/google/fatcat/Kconfig b/src/mainboard/google/fatcat/Kconfig
index a425d7ee66..2139194839 100644
--- a/src/mainboard/google/fatcat/Kconfig
+++ b/src/mainboard/google/fatcat/Kconfig
@@ -93,7 +93,7 @@ config BASEBOARD_DIR
 
 config CHROMEOS
 	select EC_GOOGLE_CHROMEEC_SWITCHES
-	select GBB_FLAG_DISABLE_EC_SOFTWARE_SYNC
+	select GBB_FLAG_DISABLE_EC_SOFTWARE_SYNC if EC_GOOGLE_CHROMEEC_MEC
 	select GBB_FLAG_FORCE_DEV_BOOT_USB
 	select GBB_FLAG_FORCE_MANUAL_RECOVERY
 	select HAS_RECOVERY_MRC_CACHE

From 9f39d6ec5e9f24199501aa6d9b15395b7cd6c77f Mon Sep 17 00:00:00 2001
From: Subrata Banik <subratabanik@google.com>
Date: Mon, 24 Mar 2025 18:09:16 +0530
Subject: [PATCH 0494/3886] mb/google/fatcat: Enable HAVE_SLP_S0_GATE for
 felino and francka

The fatcat variant now handles SLP_S0 pin functionality natively,
removing the need for HAVE_SLP_S0_GATE. However, other variants like
felino and francka boards still rely on this Kconfig option for proper
sleep state gating. This commit re-enables it for these specific boards.

TEST=Able to build and boot google/fatcat.

Change-Id: Ib7e683c3fee575245e8796638260f1fd8e6e5c34
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86983
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/google/fatcat/Kconfig | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/src/mainboard/google/fatcat/Kconfig b/src/mainboard/google/fatcat/Kconfig
index 2139194839..6bdf3333eb 100644
--- a/src/mainboard/google/fatcat/Kconfig
+++ b/src/mainboard/google/fatcat/Kconfig
@@ -47,7 +47,6 @@ config BOARD_GOOGLE_BASEBOARD_FATCAT
 	select DRIVERS_INTEL_ISH
 	select DRIVER_INTEL_ISH_HAS_MAIN_FW
 	select DRIVERS_INTEL_USB4_RETIMER
-	select HAVE_SLP_S0_GATE
 	select MAINBOARD_HAS_CHROMEOS
 	select MEMORY_SOLDERDOWN
 	select SOC_INTEL_COMMON_BLOCK_HDA_VERB
@@ -80,10 +79,12 @@ config BOARD_GOOGLE_FATCATITE
 
 config BOARD_GOOGLE_FELINO
 	select BOARD_GOOGLE_BASEBOARD_FATCAT
+	select HAVE_SLP_S0_GATE
 	select MAINBOARD_HAS_GOOGLE_STRAUSS_KEYBOARD
 
 config BOARD_GOOGLE_FRANCKA
 	select BOARD_GOOGLE_BASEBOARD_FATCAT
+	select HAVE_SLP_S0_GATE
 
 if BOARD_GOOGLE_FATCAT_COMMON
 

From eb85dfae1f2377176f13492f524d927d9a206da0 Mon Sep 17 00:00:00 2001
From: Subrata Banik <subratabanik@google.com>
Date: Mon, 24 Mar 2025 18:36:58 +0530
Subject: [PATCH 0495/3886] mb/google/fatcat: Configure GPIO_SLP_S0_GATE for
 francka and felino

This commit configures the GPIO_SLP_S0_GATE pin for the francka and
felino mainboards, which are used to gate the SoC's SLP_S0# signal
for proper sleep state management.

- For francka, GPIO_SLP_S0_GATE is set to GPP_F23.
- For felino, GPIO_SLP_S0_GATE is set to GPP_D03.

The base fatcat board and its variants (fatcatnuvo, fatcatite,
fatcatish) do not utilize this pin, therefore it is defined as 0
(Not Connected).

Change-Id: I3150d4e60e4886fb7df7229eaf9efed59a69a707
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86984
Reviewed-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
---
 .../variants/baseboard/fatcat/include/baseboard/gpio.h      | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/src/mainboard/google/fatcat/variants/baseboard/fatcat/include/baseboard/gpio.h b/src/mainboard/google/fatcat/variants/baseboard/fatcat/include/baseboard/gpio.h
index 47b0e3d487..dc4ce13185 100644
--- a/src/mainboard/google/fatcat/variants/baseboard/fatcat/include/baseboard/gpio.h
+++ b/src/mainboard/google/fatcat/variants/baseboard/fatcat/include/baseboard/gpio.h
@@ -15,15 +15,21 @@
 #if CONFIG(BOARD_GOOGLE_FATCATNUVO) || CONFIG(BOARD_GOOGLE_FATCATITE)
  #define EC_SYNC_IRQ	GPP_E07_IRQ
  #define GPIO_PCH_WP	GPP_D02
+#define GPIO_SLP_S0_GATE	0 /* Not Connected */
 #elif CONFIG(BOARD_GOOGLE_FATCAT) || CONFIG(BOARD_GOOGLE_FATCATISH)
  #define EC_SYNC_IRQ	0 /* Not Connected */
  #define GPIO_PCH_WP	GPP_D02
+#define GPIO_SLP_S0_GATE	0 /* Not Connected */
 #elif CONFIG(BOARD_GOOGLE_FRANCKA)
  #define EC_SYNC_IRQ	GPP_B05_IRQ
  #define GPIO_PCH_WP	GPP_E22
+/* Used to gate SoC's SLP_S0# signal */
+#define GPIO_SLP_S0_GATE	GPP_F23
 #elif CONFIG(BOARD_GOOGLE_FELINO)
  #define EC_SYNC_IRQ	0 /* TODO */
  #define GPIO_PCH_WP	0 /* TODO */
+/* Used to gate SoC's SLP_S0# signal */
+#define GPIO_SLP_S0_GATE	GPP_D03
 #endif
 
 #endif /* __BASEBOARD_GPIO_H__ */

From 0fc2422e88dc34883dac523191d8c1a3a7fd8306 Mon Sep 17 00:00:00 2001
From: Ian Feng <ian_feng@compal.corp-partner.google.com>
Date: Mon, 24 Mar 2025 15:36:32 +0800
Subject: [PATCH 0496/3886] mb/google/fatcat: Implement S0ix hooks aka `MS0X`
 method

Implemented runtime ASL method (MS0X) being called by PEPD device
_DSM to configure `GPIO_SLP_S0_GATE` PIN at S0ix entry/exit.

Test on francka: GPIO_SLP_S0_GATE (GPP_F23)
Scope (\_SB)
{
    Method (MS0X, 1, Serialized)
    {
        If ((Arg0 == One))
        {
            \_SB.PCI0.CTXS (0x47)
        }
        Else
        {
            \_SB.PCI0.STXS (0x47)
        }
    }
}

BUG=b:399264399
TEST=Run suspend_stress_test on francka and verify that the device can
suspend.

Change-Id: Idd9fcd07ab09f4dc905e4fa029b9b2f897ad015c
Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86981
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
---
 src/mainboard/google/fatcat/mainboard.c | 27 +++++++++++++++++++++++++
 1 file changed, 27 insertions(+)

diff --git a/src/mainboard/google/fatcat/mainboard.c b/src/mainboard/google/fatcat/mainboard.c
index f514eb96d1..e14c5ace79 100644
--- a/src/mainboard/google/fatcat/mainboard.c
+++ b/src/mainboard/google/fatcat/mainboard.c
@@ -58,6 +58,32 @@ void __weak variant_generate_s0ix_hook(enum s0ix_entry entry)
 	 */
 }
 
+static void mainboard_generate_s0ix_hook(void)
+{
+	acpigen_write_if_lequal_op_int(ARG0_OP, 1);
+	{
+		if (CONFIG(HAVE_SLP_S0_GATE))
+			acpigen_soc_clear_tx_gpio(GPIO_SLP_S0_GATE);
+		variant_generate_s0ix_hook(S0IX_ENTRY);
+	}
+	acpigen_write_else();
+	{
+		if (CONFIG(HAVE_SLP_S0_GATE))
+			acpigen_soc_set_tx_gpio(GPIO_SLP_S0_GATE);
+		variant_generate_s0ix_hook(S0IX_EXIT);
+	}
+	acpigen_write_if_end();
+}
+
+static void mainboard_fill_ssdt(const struct device *dev)
+{
+	acpigen_write_scope("\\_SB");
+	acpigen_write_method_serialized("MS0X", 1);
+	mainboard_generate_s0ix_hook();
+	acpigen_write_method_end(); /* Method */
+	acpigen_write_scope_end(); /* Scope */
+}
+
 static void mainboard_dev_init(struct device *dev)
 {
 	mainboard_ec_init();
@@ -66,6 +92,7 @@ static void mainboard_dev_init(struct device *dev)
 static void mainboard_enable(struct device *dev)
 {
 	dev->ops->init = mainboard_dev_init;
+	dev->ops->acpi_fill_ssdt = mainboard_fill_ssdt;
 }
 
 struct chip_operations mainboard_ops = {

From 9102bcca41f58b70c81c40ef80eaec109ec6b454 Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Mon, 24 Mar 2025 13:56:14 +0000
Subject: [PATCH 0497/3886] mb/starlabs/starbook/adl_n: Fix spacing in comments

Change-Id: I9d81ae0b81b4c58adaf99e8cbfae6795310554f4
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86986
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 .../starlabs/starbook/variants/adl_n/gpio.c      | 16 ++++++++--------
 1 file changed, 8 insertions(+), 8 deletions(-)

diff --git a/src/mainboard/starlabs/starbook/variants/adl_n/gpio.c b/src/mainboard/starlabs/starbook/variants/adl_n/gpio.c
index a985809e0e..11cab703e7 100644
--- a/src/mainboard/starlabs/starbook/variants/adl_n/gpio.c
+++ b/src/mainboard/starlabs/starbook/variants/adl_n/gpio.c
@@ -433,21 +433,21 @@ const struct pad_config gpio_table[] = {
 	/* T15:		 Not Connected					*/
 	PAD_NC(GPP_T15, NONE),
 
-	/* R0:		HDA BCLK				*/
+	/* R0:		HDA BCLK					*/
 	PAD_CFG_NF(GPP_R0, NATIVE, DEEP, NF1),
-	/* R1:		HDA SYNC				*/
+	/* R1:		HDA SYNC					*/
 	PAD_CFG_NF(GPP_R1, NATIVE, DEEP, NF1),
-	/* R2:		HDA SDO					*/
+	/* R2:		HDA SDO						*/
 	PAD_CFG_NF(GPP_R2, NATIVE, DEEP, NF1),
-	/* R3:		HDA SDI					*/
+	/* R3:		HDA SDI						*/
 	PAD_CFG_NF(GPP_R3, NATIVE, DEEP, NF1),
-	/* R4:		HDA Reset				*/
+	/* R4:		HDA Reset					*/
 	PAD_CFG_NF(GPP_R4, NATIVE, DEEP, NF1),
-	/* R5:		MiPi Cam Reset				*/
+	/* R5:		MiPi Cam Reset					*/
 	PAD_NC(GPP_R5, NONE),
-	/* R6:		Not Connected				*/
+	/* R6:		Not Connected					*/
 	PAD_NC(GPP_R6, NONE),
-	/* R7:		Not Connected				*/
+	/* R7:		Not Connected					*/
 	PAD_NC(GPP_R7, NONE),
 };
 

From 31c4bdcba22e70cf3523106d734a8f5ce154cd54 Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Mon, 24 Mar 2025 13:59:11 +0000
Subject: [PATCH 0498/3886] mb/starlabs/starbook/mtl: Fix duplicate GPP_F21
 comment

Change-Id: Ic5d1ac1044aa3e54d7d0494fc19fc238f3d87065
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86987
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/starlabs/starbook/variants/mtl/gpio.c | 1 -
 1 file changed, 1 deletion(-)

diff --git a/src/mainboard/starlabs/starbook/variants/mtl/gpio.c b/src/mainboard/starlabs/starbook/variants/mtl/gpio.c
index f9efc62d50..4da1a53115 100644
--- a/src/mainboard/starlabs/starbook/variants/mtl/gpio.c
+++ b/src/mainboard/starlabs/starbook/variants/mtl/gpio.c
@@ -346,7 +346,6 @@ const struct pad_config gpio_table[] = {
 	 *		HIGH:	BALTIC PEAK
 	 *		LOW:	BSSB-LS
 	 *		WEAK INTERNAL PU 20K	*/
-	/* F21:					*/
 	PAD_NC(GPP_F21, NONE),
 	/* F22:					*/
 	PAD_NC(GPP_F22, NONE),

From 96ec1f7c1f43a57cbdf1ad3e554a7609fdcff738 Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Mon, 24 Mar 2025 14:00:18 +0000
Subject: [PATCH 0499/3886] mb/starlabs/starbook/mtl: Add missing config for
 GPP_E09

This pad isn't used, so set it to not connected.

Change-Id: Ic7174457f56e64751718dc10227ec07b793559eb
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86988
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/starlabs/starbook/variants/mtl/gpio.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/src/mainboard/starlabs/starbook/variants/mtl/gpio.c b/src/mainboard/starlabs/starbook/variants/mtl/gpio.c
index 4da1a53115..7a7ee1e73a 100644
--- a/src/mainboard/starlabs/starbook/variants/mtl/gpio.c
+++ b/src/mainboard/starlabs/starbook/variants/mtl/gpio.c
@@ -207,6 +207,7 @@ const struct pad_config gpio_table[] = {
 	/* E08:					*/
 	PAD_NC(GPP_E08, NONE),
 	/* E09:	USB2_OC0			*/
+	PAD_NC(GPP_E09, NONE),
 	/* E10:					*/
 	PAD_NC(GPP_E10, NONE),
 	/* E11:					*/

From a8f52bdc9c169dea93b5de9f3cc1af813fd454cb Mon Sep 17 00:00:00 2001
From: Momoko Hattori <momohatt@google.com>
Date: Tue, 18 Mar 2025 16:13:42 +0900
Subject: [PATCH 0500/3886] mb/google/brox/var/jubilant: Enable
 use_gpio_for_status for touchscreen

Apply the change made to brya/redrix in CB:86749 to all applicable brox
variants, which is currently jubilant only.

BUG=b:397355818
TEST=Dump SSDT on jubilant

Change-Id: Ie0fc00e511b8efd5bae29cc089a24f7b0128d77e
Signed-off-by: Momoko Hattori <momohatt@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86954
Reviewed-by: Sam McNally <sammc@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/google/brox/variants/jubilant/overridetree.cb | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/src/mainboard/google/brox/variants/jubilant/overridetree.cb b/src/mainboard/google/brox/variants/jubilant/overridetree.cb
index 13e3fb65da..25bedf870e 100644
--- a/src/mainboard/google/brox/variants/jubilant/overridetree.cb
+++ b/src/mainboard/google/brox/variants/jubilant/overridetree.cb
@@ -380,6 +380,7 @@ chip soc/intel/alderlake
 				register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_F7)"
 				register "generic.enable_delay_ms" = "12"
 				register "generic.has_power_resource" = "1"
+				register "generic.use_gpio_for_status" = "true"
 				register "hid_desc_reg_offset" = "0x01"
 				device i2c 41 on end
 			end
@@ -397,6 +398,7 @@ chip soc/intel/alderlake
 				register "generic.stop_delay_ms" = "150"
 				register "generic.stop_off_delay_ms" = "2"
 				register "generic.has_power_resource" = "1"
+				register "generic.use_gpio_for_status" = "true"
 				register "hid_desc_reg_offset" = "0x01"
 				device i2c 10 on end
 			end

From a129f85b7f44e3722c5a7bde0345d545eb0f443a Mon Sep 17 00:00:00 2001
From: Tongtong Pan <pantongtong@huaqin.corp-partner.google.com>
Date: Mon, 24 Mar 2025 11:54:04 +0800
Subject: [PATCH 0501/3886] mb/google/fatcat/var/felino: Add Focal touchpad to
 devicetree

Update device tree to support Focal touchpad.

BUG=b:404363997
TEST=emerge-fatcat coreboot and Focal touchpad can work well.

Change-Id: I515eb63a9e5b8e4ebc7d6828ae3da47caa997ea3
Signed-off-by: Tongtong Pan <pantongtong@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86979
Reviewed-by: Pranava Y N <pranavayn@google.com>
Reviewed-by: Jayvik Desai <jayvik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 .../google/fatcat/variants/felino/overridetree.cb      | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/src/mainboard/google/fatcat/variants/felino/overridetree.cb b/src/mainboard/google/fatcat/variants/felino/overridetree.cb
index 819bbaa43b..aa8c16b949 100644
--- a/src/mainboard/google/fatcat/variants/felino/overridetree.cb
+++ b/src/mainboard/google/fatcat/variants/felino/overridetree.cb
@@ -289,6 +289,16 @@ device ref tbt_pcie_rp0 on end
 				register "detect" = "1"
 				device i2c 0x15 on end
 			end
+			chip drivers/i2c/hid
+				register "generic.hid" = ""FTCS0038""
+				register "generic.cid" = ""PNP0C50""
+				register "generic.desc" = ""Focal Touchpad""
+				register "generic.irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_E18_IRQ)"
+				register "generic.wake" = "GPE0_DW2_18"
+				register "generic.detect" = "1"
+				register "hid_desc_reg_offset" = "0x20"
+				device i2c 0x38 on end
+			end
 		end # I2C4
 
 	end

From 231296b6384a5c53c656f8e397945f664d634dc8 Mon Sep 17 00:00:00 2001
From: Ian Feng <ian_feng@compal.corp-partner.google.com>
Date: Mon, 24 Mar 2025 11:13:36 +0800
Subject: [PATCH 0502/3886] mb/google/fatcat/var/francka: Disable RTD3 for SD
 card

BUG=b:399264399
TEST= Run suspend_stress_test on francka and verify that the device can
suspend.

Change-Id: Icccf1bf181495171449f1c1335902fef2614d04c
Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86978
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Jayvik Desai <jayvik@google.com>
---
 .../google/fatcat/variants/francka/overridetree.cb          | 6 ------
 1 file changed, 6 deletions(-)

diff --git a/src/mainboard/google/fatcat/variants/francka/overridetree.cb b/src/mainboard/google/fatcat/variants/francka/overridetree.cb
index 580e96fb3a..f9ae720e0f 100644
--- a/src/mainboard/google/fatcat/variants/francka/overridetree.cb
+++ b/src/mainboard/google/fatcat/variants/francka/overridetree.cb
@@ -258,12 +258,6 @@ chip soc/intel/pantherlake
 				.clk_req = 2,
 				.flags = PCIE_RP_CLK_REQ_DETECT | PCIE_RP_LTR | PCIE_RP_AER,
 			}"
-			chip soc/intel/common/block/pcie/rtd3
-				register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A08)"
-				register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D19)"
-				register "srcclk_pin" = "2"
-				device generic 0 on end
-			end
 		end # SD Card
 		device ref pcie_rp9 on
 			register "pcie_rp[PCIE_RP(9)]" = "{

From aa3da6e785ad731eacb8ad6da5f2ca4631658df8 Mon Sep 17 00:00:00 2001
From: Wonkyu Kim <wonkyu.kim@intel.corp-partner.google.com>
Date: Thu, 20 Mar 2025 15:23:43 -0700
Subject: [PATCH 0503/3886] src/lib: use RO CBFS file as fw_config source
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

The FW_CONFIG_SOURCE_CBFS option serves as a backup for
FW_CONFIG_SOURCE_CHROMEEC_CBI, utilizing variables stored in CBFS.
When using ChromeEC CBI as the firmware configuration source,
changes to fw_config values can be made without updating the firmware
image. However, using CBFS as the configuration source requires
resigning the firmware because the current implementation reads from
the RW firmware region (FW_MAIN_A/B), necessitating resigning for
updates.  To avoid this step, the code should be modified to use the
RO CBFS for fw_config values instead of the RW (Read-Write) CBFS.

TEST:
1. Add FW_CONFIG_SOURCE_CBFS in board Kconfig and build image
2. Modify fw_config value by cbfstool with built image
3. flash and boot up system
4. Check updated fw_config value

Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com>
Change-Id: I4710a1043fe75888d2dcaee98c6957e6bd639be9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86943
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Cliff Huang <cliff.huang@intel.com>
Reviewed-by: Jamie Ryu <jamie.m.ryu@intel.com>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
---
 src/lib/fw_config.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/lib/fw_config.c b/src/lib/fw_config.c
index e03256764b..74f3f8bc41 100644
--- a/src/lib/fw_config.c
+++ b/src/lib/fw_config.c
@@ -34,8 +34,8 @@ uint64_t fw_config_get(void)
 
 	/* Look in CBFS to allow override of value. */
 	if (CONFIG(FW_CONFIG_SOURCE_CBFS) && fw_config_value == UNDEFINED_FW_CONFIG) {
-		if (cbfs_load(CONFIG_CBFS_PREFIX "/fw_config", &fw_config_value,
-			      sizeof(fw_config_value)) != sizeof(fw_config_value))
+		if (cbfs_ro_load(CONFIG_CBFS_PREFIX "/fw_config", &fw_config_value,
+				 sizeof(fw_config_value)) != sizeof(fw_config_value))
 			printk(BIOS_WARNING, "%s: Could not get fw_config from CBFS\n",
 				__func__);
 		else

From 470e459c4dc3b80bc1548c824bab1294834953e3 Mon Sep 17 00:00:00 2001
From: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com>
Date: Tue, 25 Mar 2025 10:59:12 +0900
Subject: [PATCH 0504/3886] mb/google/nissa/var/meliks: Disable external FIVR

Disable external FIVR in overridetree.cb since meliks will remove
external FIVR in next phase.

BUG=b:402647064
BRANCH=nissa
TEST=FW_NAME=meliks emerge-nissa coreboot

Change-Id: If1584da51976fb682733b246ce7af3786ae55947
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86992
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Jayvik Desai <jayvik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 .../google/brya/variants/meliks/overridetree.cb   | 15 ---------------
 1 file changed, 15 deletions(-)

diff --git a/src/mainboard/google/brya/variants/meliks/overridetree.cb b/src/mainboard/google/brya/variants/meliks/overridetree.cb
index 1d9ced5eb8..eefa40b001 100644
--- a/src/mainboard/google/brya/variants/meliks/overridetree.cb
+++ b/src/mainboard/google/brya/variants/meliks/overridetree.cb
@@ -77,21 +77,6 @@ chip soc/intel/alderlake
 		[PchSerialIoIndexI2C5] = PchSerialIoPci,
 	}"
 
-	# Configure external V1P05/Vnn/VnnSx Rails
-	register "ext_fivr_settings" = "{
-		.configure_ext_fivr = 1,
-		.v1p05_enable_bitmap = FIVR_ENABLE_ALL_SX & ~FIVR_ENABLE_S0,
-		.vnn_enable_bitmap = FIVR_ENABLE_ALL_SX ,
-		.vnn_sx_enable_bitmap = FIVR_ENABLE_ALL_SX ,
-		.v1p05_supported_voltage_bitmap = FIVR_VOLTAGE_NORMAL,
-		.vnn_supported_voltage_bitmap = FIVR_VOLTAGE_MIN_RETENTION,
-		.v1p05_voltage_mv = 1050,
-		.vnn_voltage_mv = 780,
-		.vnn_sx_voltage_mv = 1050,
-		.v1p05_icc_max_ma = 500,
-		.vnn_icc_max_ma = 500,
-	}"
-
 	# VR Settings
 	register "domain_vr_config[VR_DOMAIN_IA]" = "{
 		.vr_config_enable = 1,

From e64a5c4d49dfba5307279bee2de9681bea5f9e26 Mon Sep 17 00:00:00 2001
From: Subrata Banik <subratabanik@google.com>
Date: Fri, 14 Mar 2025 01:34:50 +0530
Subject: [PATCH 0505/3886] drivers/intel/fsp2_0: Enable panel-orientation
 aware bitmap rotation

Implement logo bitmap rotation within fsp_convert_bmp_to_gop_blt() to
support devices with portrait-oriented displays. The rotation is driven
by the panel framebuffer orientation, allowing the logo to be displayed
correctly regardless of physical panel orientation.

This resolves issues where the logo was displayed incorrectly on
portrait-oriented displays.

Additionally, discard the display orientation change if the LID is
closed aka built-in display is not active. This will ensure that
display orientation is proper when extended display is attached w/o
any display rotation.

BUG=b:396580135
TEST=Verified BMP logo display in landscape mode on a portrait panel
with rotation enabled. Also verified portrait logo display in landscape
mode with rotation enabled.

Change-Id: I110bd67331f01e523c227e1a4bdb0484f0157a60
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86850
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/drivers/intel/fsp2_0/fsp_gop_blt.c        | 230 ++++++++++++++++--
 .../intel/fsp2_0/include/fsp/fsp_gop_blt.h    |   4 +-
 src/soc/intel/alderlake/fsp_params.c          |  18 +-
 src/soc/intel/meteorlake/fsp_params.c         |  18 +-
 src/soc/intel/pantherlake/fsp_params.c        |  17 +-
 5 files changed, 262 insertions(+), 25 deletions(-)

diff --git a/src/drivers/intel/fsp2_0/fsp_gop_blt.c b/src/drivers/intel/fsp2_0/fsp_gop_blt.c
index bbeece4e97..087fb02df0 100644
--- a/src/drivers/intel/fsp2_0/fsp_gop_blt.c
+++ b/src/drivers/intel/fsp2_0/fsp_gop_blt.c
@@ -1,5 +1,6 @@
 /* SPDX-License-Identifier: GPL-2.0-or-later */
 
+#include <boot/coreboot_tables.h>
 #include <bootsplash.h>
 #include <console/console.h>
 #include <fsp/api.h>
@@ -131,9 +132,184 @@ static uint32_t get_color_map_num(efi_bmp_image_header *header)
 	return col_map_number;
 }
 
-/* Fill BMP image into BLT buffer format */
+/*
+ * Visual Representation of the Flipping:
+ *
+ * Original BMP Image:
+ *
+ *      0 -----------------------------------------PixelWidth-1
+ *      |                                          |
+ *      |                                          |
+ *      |                                          |
+ *      PixelHeight-1------------------------------|
+ *
+ * Blitting Region:
+ *
+ *      (x, y) ----------------------------------- (x + blt_width, y)
+ *      |                                          |
+ *      |                                          |
+ *      (x, y + blt_height) -------------------- --(x + blt_width, y + blt_height)
+ *
+ * Flipped Coordinates:
+ *
+ * flipped_x:  Represents the horizontal coordinate from the `right` edge of the BMP,
+ *             accounting for the blit width.
+ *
+ * flipped_y:  Represents the vertical coordinate from the `bottom` edge of the BMP,
+ *             accounting for the blit height.
+ *
+ * Example (Orientation: LB_FB_ORIENTATION_BOTTOM_UP):
+ *
+ * If blt_width is small, flipped_x will be near PixelWidth.
+ * If blt_height is small, flipped_y will be near PixelHeight.
+ *
+ * The blit then starts at (flipped_x, blt_height), effectively flipping the
+ * horizontal position and using the original blit height.
+ *
+ * This allows for blitting from the bottom-left corner of the display panel.
+ */
+static bool calculate_adj_height_width(const efi_bmp_image_header *header, size_t *adjusted_x,
+	 size_t *adjusted_y, enum lb_fb_orientation orientation, int blt_width, int blt_height)
+{
+	if (!header || !adjusted_x || !adjusted_y)
+		return false;
+
+	size_t flipped_x = header->PixelWidth - blt_width - 1;
+	size_t flipped_y = header->PixelHeight - blt_height - 1;
+
+	switch (orientation) {
+	case LB_FB_ORIENTATION_LEFT_UP:
+		*adjusted_x = flipped_y;
+		*adjusted_y = flipped_x;
+		break;
+
+	case LB_FB_ORIENTATION_BOTTOM_UP:
+		*adjusted_x = flipped_x;
+		*adjusted_y = blt_height;
+		break;
+
+	case LB_FB_ORIENTATION_RIGHT_UP:
+		*adjusted_x = blt_height;
+		*adjusted_y = blt_width;
+		break;
+
+	case LB_FB_ORIENTATION_NORMAL:
+	default:
+		*adjusted_x = blt_width;
+		*adjusted_y = flipped_y;
+		break;
+	}
+
+	return true;
+}
+
+/*
+ * Visual Representation of gop_width and calculate linear offset into the GOP buffer:
+ *
+ * GOP Display Buffer:
+ *
+ *      +------------------------------------------------+
+ *      | 0                                              |
+ *      | |--> gop_width pixels in this row              |
+ *      +------------------------------------------------+
+ *      | gop_width                                      |
+ *      |                                                |
+ *      | gop_width                                      |
+ *      | ...                                            |
+ *      +------------------------------------------------+
+ *      | gop_width                                      |
+ *      +------------------------------------------------+
+ *
+ * gop_width: Represents the width of a row in the GOP buffer.
+ * - It is determined by the `orientation` of the image.
+ * - For `LEFT_UP` and `RIGHT_UP`, the GOP width is the BMP image's `PixelHeight`.
+ * - For `BOTTOM_UP` and `NORMAL`, the GOP width is the BMP image's `PixelWidth`.
+ *
+ * gop_x, gop_y: Coordinates within the GOP buffer where the blit will start.
+ * - These are calculated by `calculate_adj_height_width` based on the `orientation`,
+ * `blt_width`, and `blt_height`.
+ *
+ * Pointer to the calculated pixel in the GOP blit buffer, or NULL on error.
+ * - Calculate `gop_blt_offset`as `gop_y * gop_width + gop_x` to determine the offset
+ *   to access the correct pixel within `gop_blt_buffer`.
+ * - `gop_y * gop_width` calculates the offset of the row.
+ * - `gop_x` calculates the offset within that row.
+ */
+static efi_graphics_output_blt_pixel *get_gop_blt_pixel(
+	efi_graphics_output_blt_pixel *gop_blt_buffer, const efi_bmp_image_header *header,
+	 int blt_width, int blt_height, enum lb_fb_orientation orientation)
+{
+	size_t gop_x;
+	size_t gop_y;
+	size_t gop_width;
+
+	if (!header || !gop_blt_buffer)
+		return NULL;
+
+	switch (orientation) {
+	case LB_FB_ORIENTATION_LEFT_UP:
+	case LB_FB_ORIENTATION_RIGHT_UP:
+		gop_width = header->PixelHeight;
+		break;
+
+	case LB_FB_ORIENTATION_BOTTOM_UP:
+	case LB_FB_ORIENTATION_NORMAL:
+	default:
+		gop_width = header->PixelWidth;
+		break;
+	}
+
+	if (!calculate_adj_height_width(header, &gop_x, &gop_y, orientation,
+			 blt_width, blt_height))
+		return NULL;
+
+	/*
+	 * Calculated pixel in the Graphics Output Protocol (GOP) blit buffer.
+	 * This offset represents the starting position where the blitted region will be placed
+	 * in the framebuffer.
+	 */
+	return &gop_blt_buffer[gop_y * gop_width + gop_x];
+}
+
+/*
+ * Fill BMP image into BLT buffer format with optional orientation
+ *
+ * +------------------------------------------------------------------+
+ * |  BMP Image (header: efi_bmp_image_header)                        |
+ * |  (PixelWidth, PixelHeight)                                       |
+ * +------------------------------------------------------------------+
+ *        |
+ *        | (blt_width, blt_height) : Region to blit
+ *        V
+ * +------------------------------------------------------------------+
+ * |  calculate_adj_height_width(header, adjusted_x, adjusted_y,      |
+ * |                               orientation, blt_width, blt_height)|
+ * +------------------------------------------------------------------+
+ *        |
+ *        | Calculates adjusted coordinates based on orientation:
+ *        |   - flipped_x = header->PixelWidth - blt_width - 1
+ *        |   - flipped_y = header->PixelHeight - blt_height - 1
+ *        |   - Depending on 'orientation', adjusted_x and adjusted_y are set.
+ *        V
+ * +-------------------------------------------------------------------+
+ * |  get_gop_blt_pixel(gop_blt_buffer, header, blt_width, blt_height, |
+ * |                                                  orientation)     |
+ * +-------------------------------------------------------------------+
+ *        |
+ *        | 1. Determines gop_width based on orientation:
+ *        |    - LEFT_UP/RIGHT_UP: gop_width = header->PixelHeight,
+ *        |    - BOTTOM_UP/NORMAL: gop_width = header->PixelWidth,
+ *        | 2. Calls calculate_adj_height_width to get gop_x and gop_y.
+ *        | 3. GOP BLT offset: calculates linear offset into the GOP buffer
+ *        |    - gop_blt_offset = gop_y * gop_width + gop_x
+ *        | 4. GOP BLT offset is used to access the correct regions in:
+ *        V
+ * +------------------------------------------------------------------+
+ * |  GOP Blit Buffer (Framebuffer)                                   |
+ * +------------------------------------------------------------------+
+ */
 static void *fill_blt_buffer(efi_bmp_image_header *header,
-	uintptr_t logo_ptr, size_t blt_buffer_size)
+	uintptr_t logo_ptr, size_t blt_buffer_size, enum lb_fb_orientation orientation)
 {
 	efi_graphics_output_blt_pixel *gop_blt_buffer;
 	efi_graphics_output_blt_pixel *gop_blt_ptr;
@@ -157,25 +333,32 @@ static void *fill_blt_buffer(efi_bmp_image_header *header,
 	bmp_color_map = (efi_bmp_color_map *)(logo_ptr + sizeof(efi_bmp_image_header));
 
 	for (size_t height = 0; height < header->PixelHeight; height++) {
-		gop_blt = &gop_blt_buffer[(header->PixelHeight - height - 1) *
-				 header->PixelWidth];
-		for (size_t width = 0; width < header->PixelWidth; width++, bmp_image++,
-			 gop_blt++) {
+		for (size_t width = 0; width < header->PixelWidth; width++, bmp_image++) {
 			size_t index = 0;
+
+			gop_blt = get_gop_blt_pixel(gop_blt_buffer, header, width, height,
+							 orientation);
+			if (!gop_blt) {
+				free(gop_blt_ptr);
+				return NULL;
+			}
+
 			switch (header->BitPerPixel) {
 			/* Translate 1-bit (2 colors) BMP to 24-bit color */
 			case 1:
 				for (index = 0; index < 8 && width < header->PixelWidth; index++) {
-					gop_blt->Red = bmp_color_map[((*bmp_image) >> (7 - index))
-									 & 0x1].Red;
-					gop_blt->Green = bmp_color_map[((*bmp_image) >> (7 - index))
-									 & 0x1].Green;
-					gop_blt->Blue = bmp_color_map[((*bmp_image) >> (7 - index))
-									 & 0x1].Blue;
-					gop_blt++;
+					uint8_t bit = ((*bmp_image) >> (7 - index)) & 0x1;
+					gop_blt->Red = bmp_color_map[bit].Red;
+					gop_blt->Green = bmp_color_map[bit].Green;
+					gop_blt->Blue = bmp_color_map[bit].Blue;
 					width++;
+					gop_blt = get_gop_blt_pixel(gop_blt_buffer, header, width, height,
+								 orientation);
+					if (!gop_blt) {
+						free(gop_blt_ptr);
+						return NULL;
+					}
 				}
-				gop_blt--;
 				width--;
 				break;
 
@@ -186,8 +369,13 @@ static void *fill_blt_buffer(efi_bmp_image_header *header,
 				gop_blt->Green = bmp_color_map[index].Green;
 				gop_blt->Blue = bmp_color_map[index].Blue;
 				if (width < (header->PixelWidth - 1)) {
-					gop_blt++;
 					width++;
+					gop_blt = get_gop_blt_pixel(gop_blt_buffer, header, width, height,
+								 orientation);
+					if (!gop_blt) {
+						free(gop_blt_ptr);
+						return NULL;
+					}
 					index = (*bmp_image) & 0x0f;
 					gop_blt->Red = bmp_color_map[index].Red;
 					gop_blt->Green = bmp_color_map[index].Green;
@@ -237,8 +425,8 @@ static void *fill_blt_buffer(efi_bmp_image_header *header,
 
 /* Convert a *.BMP graphics image to a GOP blt buffer */
 void fsp_convert_bmp_to_gop_blt(efi_uintn_t *logo, uint32_t *logo_size,
-	efi_uintn_t *blt_ptr, efi_uintn_t *blt_size,
-	uint32_t *pixel_height, uint32_t *pixel_width)
+	efi_uintn_t *blt_ptr, efi_uintn_t *blt_size, uint32_t *pixel_height, uint32_t *pixel_width,
+	enum lb_fb_orientation orientation)
 {
 	uintptr_t logo_ptr;
 	size_t logo_ptr_size, blt_buffer_size;
@@ -265,10 +453,12 @@ void fsp_convert_bmp_to_gop_blt(efi_uintn_t *logo, uint32_t *logo_size,
 	if (!get_color_map_num(bmp_header))
 		return;
 
+	bool is_standard_orientation = (orientation == LB_FB_ORIENTATION_NORMAL ||
+			orientation == LB_FB_ORIENTATION_BOTTOM_UP);
 	*logo = logo_ptr;
 	*logo_size = logo_ptr_size;
 	*blt_size = blt_buffer_size;
-	*pixel_height = bmp_header->PixelHeight;
-	*pixel_width = bmp_header->PixelWidth;
-	*blt_ptr = (uintptr_t)fill_blt_buffer(bmp_header, logo_ptr, blt_buffer_size);
+	*pixel_height = is_standard_orientation ? bmp_header->PixelHeight : bmp_header->PixelWidth;
+	*pixel_width = is_standard_orientation ? bmp_header->PixelWidth : bmp_header->PixelHeight;
+	*blt_ptr = (uintptr_t)fill_blt_buffer(bmp_header, logo_ptr, blt_buffer_size, orientation);
 }
diff --git a/src/drivers/intel/fsp2_0/include/fsp/fsp_gop_blt.h b/src/drivers/intel/fsp2_0/include/fsp/fsp_gop_blt.h
index ff1548328e..4e1f68952e 100644
--- a/src/drivers/intel/fsp2_0/include/fsp/fsp_gop_blt.h
+++ b/src/drivers/intel/fsp2_0/include/fsp/fsp_gop_blt.h
@@ -8,7 +8,7 @@
 
 /* Convert a *.BMP graphics image to a GOP blt buffer */
 void fsp_convert_bmp_to_gop_blt(efi_uintn_t *logo, uint32_t *logo_size,
-	efi_uintn_t *blt_ptr, efi_uintn_t *blt_size,
-	uint32_t *pixel_height, uint32_t *pixel_width);
+	efi_uintn_t *blt_ptr, efi_uintn_t *blt_size, uint32_t *pixel_height, uint32_t *pixel_width,
+	enum lb_fb_orientation orientation);
 
 #endif	/* FSP_GOP_BLT_H */
diff --git a/src/soc/intel/alderlake/fsp_params.c b/src/soc/intel/alderlake/fsp_params.c
index 39582b5ec6..28c9169529 100644
--- a/src/soc/intel/alderlake/fsp_params.c
+++ b/src/soc/intel/alderlake/fsp_params.c
@@ -1,6 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
 #include <assert.h>
+#include <boot/coreboot_tables.h>
 #include <bootmode.h>
 #include <bootsplash.h>
 #include <console/console.h>
@@ -1376,10 +1377,25 @@ __weak void mainboard_silicon_init_params(FSP_S_CONFIG *s_cfg)
 /* Handle FSP logo params */
 void soc_load_logo(FSPS_UPD *supd)
 {
+	struct soc_intel_common_config *config = chip_get_common_soc_structure();
+	FSP_S_CONFIG *s_cfg = &supd->FspsConfig;
+
+	/*
+	 * Adjusts panel orientation for external display when the lid is closed.
+	 *
+	 * When the lid is closed (LidStatus == 0), indicating the onboard display is inactive,
+	 * this function forces the panel orientation to normal. This ensures proper display
+	 * on an external monitor, as rotated orientations are typically not suitable in
+	 * such state.
+	 */
+	if (s_cfg->LidStatus == 0)
+		config->panel_orientation = LB_FB_ORIENTATION_NORMAL;
+
 	fsp_convert_bmp_to_gop_blt(&supd->FspsConfig.LogoPtr,
 			 &supd->FspsConfig.LogoSize,
 			 &supd->FspsConfig.BltBufferAddress,
 			 &supd->FspsConfig.BltBufferSize,
 			 &supd->FspsConfig.LogoPixelHeight,
-			 &supd->FspsConfig.LogoPixelWidth);
+			 &supd->FspsConfig.LogoPixelWidth,
+			 config->panel_orientation);
 }
diff --git a/src/soc/intel/meteorlake/fsp_params.c b/src/soc/intel/meteorlake/fsp_params.c
index f3fec481b4..ad85702dbe 100644
--- a/src/soc/intel/meteorlake/fsp_params.c
+++ b/src/soc/intel/meteorlake/fsp_params.c
@@ -1,6 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
 #include <assert.h>
+#include <boot/coreboot_tables.h>
 #include <bootmode.h>
 #include <bootsplash.h>
 #include <cbfs.h>
@@ -869,10 +870,25 @@ __weak void mainboard_silicon_init_params(FSP_S_CONFIG *s_cfg)
 /* Handle FSP logo params */
 void soc_load_logo(FSPS_UPD *supd)
 {
+	struct soc_intel_common_config *config = chip_get_common_soc_structure();
+	FSP_S_CONFIG *s_cfg = &supd->FspsConfig;
+
+	/*
+	 * Adjusts panel orientation for external display when the lid is closed.
+	 *
+	 * When the lid is closed (LidStatus == 0), indicating the onboard display is inactive,
+	 * this function forces the panel orientation to normal. This ensures proper display
+	 * on an external monitor, as rotated orientations are typically not suitable in
+	 * such state.
+	 */
+	if (s_cfg->LidStatus == 0)
+		config->panel_orientation = LB_FB_ORIENTATION_NORMAL;
+
 	fsp_convert_bmp_to_gop_blt(&supd->FspsConfig.LogoPtr,
 			 &supd->FspsConfig.LogoSize,
 			 &supd->FspsConfig.BltBufferAddress,
 			 &supd->FspsConfig.BltBufferSize,
 			 &supd->FspsConfig.LogoPixelHeight,
-			 &supd->FspsConfig.LogoPixelWidth);
+			 &supd->FspsConfig.LogoPixelWidth,
+			 config->panel_orientation);
 }
diff --git a/src/soc/intel/pantherlake/fsp_params.c b/src/soc/intel/pantherlake/fsp_params.c
index fefd3e0890..7544894b75 100644
--- a/src/soc/intel/pantherlake/fsp_params.c
+++ b/src/soc/intel/pantherlake/fsp_params.c
@@ -1,5 +1,6 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
+#include <boot/coreboot_tables.h>
 #include <bootmode.h>
 #include <cpu/intel/microcode.h>
 #include <fsp/api.h>
@@ -785,10 +786,24 @@ void soc_load_logo(FSPS_UPD *supd)
 {
 	efi_uintn_t logo, blt_size;
 	uint32_t logo_size;
+	struct soc_intel_common_config *config = chip_get_common_soc_structure();
+	FSP_S_CONFIG *s_cfg = &supd->FspsConfig;
+
+	/*
+	 * Adjusts panel orientation for external display when the lid is closed.
+	 *
+	 * When the lid is closed (LidStatus == 0), indicating the onboard display is inactive,
+	 * this function forces the panel orientation to normal. This ensures proper display
+	 * on an external monitor, as rotated orientations are typically not suitable in
+	 * such state.
+	 */
+	if (s_cfg->LidStatus == 0)
+		config->panel_orientation = LB_FB_ORIENTATION_NORMAL;
 
 	fsp_convert_bmp_to_gop_blt(&logo, &logo_size,
 				   &supd->FspsConfig.BltBufferAddress,
 				   &blt_size,
 				   &supd->FspsConfig.LogoPixelHeight,
-				   &supd->FspsConfig.LogoPixelWidth);
+				   &supd->FspsConfig.LogoPixelWidth,
+				   config->panel_orientation);
 }

From 91e2e3b5c030c95f3d7f8afbefbf33b487513ac9 Mon Sep 17 00:00:00 2001
From: Keith Hui <buurin@gmail.com>
Date: Mon, 17 Mar 2025 23:25:45 -0400
Subject: [PATCH 0506/3886] mb/hp/compaq_8300_elite_sff: Replace broken USB
 port config

This board has an effectively broken USB configuration, which made
itself known during testing on a Pro 6300 SFF, that could run an
unmodified build for this variant and actually share the same vendor
BIOS update file (sp95971 v3.08 rev A).

Further examination of the BIOS update reveals five possible sets
of USB port configurations for all models covered by that update,
selected by PCH GPIOs 38 & 49, none of which matches what was currently
coded.

Then I received the autoport log from hardware with vendor BIOS that
confirmed my theory. Therefore apply the USB port config found therein.

While I'm at it, remove xhci_overcurrent_mapping, made obsolete by
commit a3d1e6c4806e (sb/intel/bd82x6x: Apply EHCI mapping to
xhci_overcurrent_mapping).

Change-Id: Idc469b1aedcad2978247b9f6efbc7f55964e9ed1
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86909
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
---
 .../compaq_8300_elite_sff/overridetree.cb     | 29 +++++++++----------
 1 file changed, 14 insertions(+), 15 deletions(-)

diff --git a/src/mainboard/hp/snb_ivb_desktops/variants/compaq_8300_elite_sff/overridetree.cb b/src/mainboard/hp/snb_ivb_desktops/variants/compaq_8300_elite_sff/overridetree.cb
index eb296f3dac..9a4e9eb3af 100644
--- a/src/mainboard/hp/snb_ivb_desktops/variants/compaq_8300_elite_sff/overridetree.cb
+++ b/src/mainboard/hp/snb_ivb_desktops/variants/compaq_8300_elite_sff/overridetree.cb
@@ -8,22 +8,21 @@ chip northbridge/intel/sandybridge
 			register "sata_port_map" = "0xf"
 			register "superspeed_capable_ports" = "0x0000000f"
 			register "xhci_switchable_ports"    = "0x0000000f"
-			register "xhci_overcurrent_mapping" = "0x0000000f"
 			register "usb_port_config" = "{
-				{ 1, 0, 0 },
-				{ 1, 0, 0 },
-				{ 1, 0, 1 },
-				{ 1, 0, 1 },
-				{ 1, 0, 2 },
-				{ 1, 0, 2 },
-				{ 1, 0, 3 },
-				{ 1, 0, 3 },
-				{ 1, 1, 4 },
-				{ 1, 0, 4 },
-				{ 1, 0, 6 },
-				{ 1, 0, 5 },
-				{ 1, 0, 5 },
-				{ 1, 0, 6 },
+				{1, 0x84b, 0},
+				{1, 0x84b, 0},
+				{1, 0xa4b, 1},
+				{1, 0xa4b, 1},
+				{1, 0xb43, 2},
+				{1, 0x94b, 2},
+				{1, 0x94f, 3},
+				{1, 0xb53, 3},
+				{1, 1, 4},
+				{1, 5, 4},
+				{1, 0x65b, 6},
+				{1, 0x65f, 5},
+				{1, 0x84b, 5},
+				{1, 0x94b, 6},
 			}"
 
 			device ref xhci on  end

From 91a8a5603f17847ebe32d4d9d939fe1c0f95725c Mon Sep 17 00:00:00 2001
From: Keith Hui <buurin@gmail.com>
Date: Thu, 9 Jan 2025 11:52:27 -0500
Subject: [PATCH 0507/3886] mb/dell/snb_ivb_workstations: Drop
 xhci_overcurrent_mapping

As of commit a3d1e6c4806e ("sb/intel/bd82x6x: Apply EHCI mapping to
xhci_overcurrent_mapping"), this is now linked to main USB port config
and is no longer referenced separately.

This board is the last unresolved mismatching xhci_overcurrent_mapping
and there is no reports whether it is working or broken. Since the
value is no longer used anyway, remove it and put a FIXME in its place.

Change-Id: Ie60d34cae5ae94d148854b42f77ab4c02e8f49ef
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85924
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
---
 .../dell/snb_ivb_workstations/variants/baseboard/devicetree.cb  | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/mainboard/dell/snb_ivb_workstations/variants/baseboard/devicetree.cb b/src/mainboard/dell/snb_ivb_workstations/variants/baseboard/devicetree.cb
index 2ba11b436c..235a90e1fd 100644
--- a/src/mainboard/dell/snb_ivb_workstations/variants/baseboard/devicetree.cb
+++ b/src/mainboard/dell/snb_ivb_workstations/variants/baseboard/devicetree.cb
@@ -28,8 +28,8 @@ chip northbridge/intel/sandybridge
 			register "spi_lvscc" = "0x2005"
 			register "spi_uvscc" = "0x2005"
 			register "superspeed_capable_ports" = "0x0000000f"
-			register "xhci_overcurrent_mapping" = "0x08040201"
 			register "xhci_switchable_ports" = "0x0000000f"
+			# FIXME: Double check USBOCM1 and XOCM
 			register "usb_port_config" = "{
 				{ 1, 6, 0 },
 				{ 1, 6, 0 },

From cd0c7c64665e84f032143e29b729503f87a0175a Mon Sep 17 00:00:00 2001
From: Keith Hui <buurin@gmail.com>
Date: Thu, 9 Jan 2025 13:15:23 -0500
Subject: [PATCH 0508/3886] sb/intel/bd82x6x: Drop xhci_overcurrent_mapping

This is now drawn (indirectly) from main usb_port_config.

Also drop it from autoport.

Change-Id: I8c5e9b2016cf56538de06575181a0a6b738c6a28
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85925
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/southbridge/intel/bd82x6x/chip.h | 2 --
 util/autoport/bd82x6x.go             | 1 -
 2 files changed, 3 deletions(-)

diff --git a/src/southbridge/intel/bd82x6x/chip.h b/src/southbridge/intel/bd82x6x/chip.h
index 188595a89b..b4b6ea33e7 100644
--- a/src/southbridge/intel/bd82x6x/chip.h
+++ b/src/southbridge/intel/bd82x6x/chip.h
@@ -72,8 +72,6 @@ struct southbridge_intel_bd82x6x_config {
 	uint32_t xhci_switchable_ports;
 	/* Ports which support SuperSpeed (USB 3.0 additional lanes).  */
 	uint32_t superspeed_capable_ports;
-	/* Overcurrent Mapping for USB 3.0 Ports */
-	uint32_t xhci_overcurrent_mapping;
 
 	uint32_t spi_uvscc;
 	uint32_t spi_lvscc;
diff --git a/util/autoport/bd82x6x.go b/util/autoport/bd82x6x.go
index fefddbcf1d..a94b359b51 100644
--- a/util/autoport/bd82x6x.go
+++ b/util/autoport/bd82x6x.go
@@ -164,7 +164,6 @@ func (b bd82x6x) Scan(ctx Context, addr PCIDevData) {
 	if ok {
 		cur.Registers["xhci_switchable_ports"] = FormatHexLE32(xhciDev.ConfigDump[0xd4:0xd8])
 		cur.Registers["superspeed_capable_ports"] = FormatHexLE32(xhciDev.ConfigDump[0xdc:0xe0])
-		cur.Registers["xhci_overcurrent_mapping"] = FormatHexLE32(xhciDev.ConfigDump[0xc0:0xc4])
 	}
 
 	PutPCIChip(addr, cur)

From 61249065f530cb32b1a09a0aac224ebf2f6a87db Mon Sep 17 00:00:00 2001
From: Zheng Bao <fishbaozi@gmail.com>
Date: Sat, 21 Sep 2024 13:50:37 +0800
Subject: [PATCH 0509/3886] amdfwtool: Move L1 before L2

It is more reasonable. And, in later change, the Level 1 should be
split with Level 2 and combined with EFS.

Change locate_bdt2_bios to locate_bdt_bios. This function is more
flexibile and covers both L1 and L2 BIOS directory table.

Change-Id: I74605013cf53a38686f4e1e5a89a4e6a870f1f4b
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84532
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 util/amdfwtool/amdfwtool.c | 33 +++++++++++++++++----------------
 1 file changed, 17 insertions(+), 16 deletions(-)

diff --git a/util/amdfwtool/amdfwtool.c b/util/amdfwtool/amdfwtool.c
index 7b5e70e3c3..b59c10f21a 100644
--- a/util/amdfwtool/amdfwtool.c
+++ b/util/amdfwtool/amdfwtool.c
@@ -1162,20 +1162,20 @@ static void *new_bios_dir(context *ctx, bool multi, uint32_t cookie)
 	return ptr;
 }
 
-static int locate_bdt2_bios(bios_directory_table *level2,
+static int locate_bdt_bios(bios_directory_table *level,
 					uint64_t *source, uint32_t *size)
 {
 	uint32_t i;
 
 	*source = 0;
 	*size = 0;
-	if (!level2)
+	if (!level)
 		return 0;
 
-	for (i = 0 ; i < level2->header.num_entries ; i++) {
-		if (level2->entries[i].type == AMD_BIOS_BIN) {
-			*source = level2->entries[i].source;
-			*size = level2->entries[i].size;
+	for (i = 0 ; i < level->header.num_entries ; i++) {
+		if (level->entries[i].type == AMD_BIOS_BIN) {
+			*source = level->entries[i].source;
+			*size = level->entries[i].size;
 			return 1;
 		}
 	}
@@ -1426,7 +1426,8 @@ static void integrate_bios_firmwares(context *ctx,
 			break;
 		case AMD_BIOS_BIN:
 			/* Don't make a 2nd copy, point to the same one */
-			if (level == BDT_LVL1 && locate_bdt2_bios(ctx->biosdir2, &source, &size)) {
+			if ((level == BDT_LVL1 && locate_bdt_bios(ctx->biosdir2, &source, &size)) ||
+				(level == BDT_LVL2 && locate_bdt_bios(ctx->biosdir, &source, &size))) {
 				biosdir->entries[count].source = source;
 				biosdir->entries[count].address_mode =
 						SET_ADDR_MODE(biosdir, AMD_ADDR_REL_BIOS);
@@ -1434,7 +1435,7 @@ static void integrate_bios_firmwares(context *ctx,
 				break;
 			}
 
-			/* level 2, or level 1 and no copy found in level 2 */
+			/* Level 2 and no copy found in level 1, or level 1 and no copy found in level 2 */
 			biosdir->entries[count].source = fw_table[i].src;
 			biosdir->entries[count].address_mode =
 						SET_ADDR_MODE(biosdir, AMD_ADDR_REL_BIOS);
@@ -1766,7 +1767,11 @@ int main(int argc, char **argv)
 		}
 
 		if (cb_config.multi_level) {
-			/* Do 2nd PSP directory followed by 1st */
+			/* PSP L1 */
+			if (!cb_config.combo_new_rab || ctx.combo_index == 0)
+				integrate_psp_firmwares(&ctx,
+					amd_psp_fw_table, PSP_COOKIE, &cb_config);
+			/* PSP L2 & BIOS L2 (if AB recovery) */
 			integrate_psp_firmwares(&ctx,
 						amd_psp_fw_table, PSPL2_COOKIE, &cb_config);
 			if (cb_config.recovery_ab) {
@@ -1780,9 +1785,6 @@ int main(int argc, char **argv)
 				}
 				integrate_bios_levels(&ctx, &cb_config);
 			}
-			if (!cb_config.combo_new_rab || ctx.combo_index == 0)
-				integrate_psp_firmwares(&ctx,
-					amd_psp_fw_table, PSP_COOKIE, &cb_config);
 			integrate_psp_levels(&ctx, &cb_config);
 		} else {
 			/* flat: PSP 1 cookie and no pointer to 2nd table */
@@ -1801,16 +1803,15 @@ int main(int argc, char **argv)
 
 		if (have_bios_tables(amd_bios_table) && !cb_config.recovery_ab) {
 			if (cb_config.multi_level) {
-				/* Do 2nd level BIOS directory followed by 1st */
+				integrate_bios_firmwares(&ctx,
+						amd_bios_table, BHD_COOKIE, &cb_config);
 				integrate_bios_firmwares(&ctx,
 						amd_bios_table, BHDL2_COOKIE, &cb_config);
-				integrate_bios_firmwares(&ctx,
-							amd_bios_table, BHD_COOKIE, &cb_config);
 				integrate_bios_levels(&ctx, &cb_config);
 			} else {
 				/* flat: BHD1 cookie and no pointer to 2nd table */
 				integrate_bios_firmwares(&ctx,
-							amd_bios_table, BHD_COOKIE, &cb_config);
+						amd_bios_table, BHD_COOKIE, &cb_config);
 			}
 			if (!cb_config.use_combo) {
 				fill_bios_directory_to_efs(ctx.amd_romsig_ptr, ctx.biosdir,

From 28e8e22215125910becd9e92da953258e25c766a Mon Sep 17 00:00:00 2001
From: Weimin Wu <wuweimin@huaqin.corp-partner.google.com>
Date: Thu, 6 Mar 2025 15:57:08 +0800
Subject: [PATCH 0510/3886] drivers/soundwire: Support Realtek ALC1320 codec

Add SoundWire driver to support ALC1320 audio codec.

reference datasheet: Realtek ALC1320-CG Rev. 0.21

BUG=b:378629979
TEST=emerge-fatcat coreboot.
check ssdt dump has 0x000331025D132001.

Change-Id: I8f100d63a6470b36d4b1a245fa6098362205728e
Signed-off-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86746
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jayvik Desai <jayvik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
---
 src/drivers/soundwire/alc1320/Kconfig     |   8 ++
 src/drivers/soundwire/alc1320/Makefile.mk |   3 +
 src/drivers/soundwire/alc1320/alc1320.c   | 150 ++++++++++++++++++++++
 src/drivers/soundwire/alc1320/chip.h      |  11 ++
 src/include/mipi/ids.h                    |   2 +
 5 files changed, 174 insertions(+)
 create mode 100644 src/drivers/soundwire/alc1320/Kconfig
 create mode 100644 src/drivers/soundwire/alc1320/Makefile.mk
 create mode 100644 src/drivers/soundwire/alc1320/alc1320.c
 create mode 100644 src/drivers/soundwire/alc1320/chip.h

diff --git a/src/drivers/soundwire/alc1320/Kconfig b/src/drivers/soundwire/alc1320/Kconfig
new file mode 100644
index 0000000000..6173e621b0
--- /dev/null
+++ b/src/drivers/soundwire/alc1320/Kconfig
@@ -0,0 +1,8 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
+config DRIVERS_SOUNDWIRE_ALC1320
+	bool
+	depends on HAVE_ACPI_TABLES
+	default n
+	help
+	  SoundWire ALC1320 speaker amplifier SSDT generator.
diff --git a/src/drivers/soundwire/alc1320/Makefile.mk b/src/drivers/soundwire/alc1320/Makefile.mk
new file mode 100644
index 0000000000..520ec9893d
--- /dev/null
+++ b/src/drivers/soundwire/alc1320/Makefile.mk
@@ -0,0 +1,3 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
+ramstage-$(CONFIG_DRIVERS_SOUNDWIRE_ALC1320) += alc1320.c
diff --git a/src/drivers/soundwire/alc1320/alc1320.c b/src/drivers/soundwire/alc1320/alc1320.c
new file mode 100644
index 0000000000..1362675f54
--- /dev/null
+++ b/src/drivers/soundwire/alc1320/alc1320.c
@@ -0,0 +1,150 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <acpi/acpigen.h>
+#include <acpi/acpi_device.h>
+#include <acpi/acpi_soundwire.h>
+#include <device/device.h>
+#include <device/soundwire.h>
+#include <mipi/ids.h>
+#include <stdio.h>
+
+#include "chip.h"
+
+static struct soundwire_address alc1320_address = {
+	.version = SOUNDWIRE_VERSION_1_2,
+	.manufacturer_id = MIPI_MFG_ID_REALTEK,
+	.part_id = MIPI_DEV_ID_REALTEK_ALC1320,
+	.class = MIPI_CLASS_NONE
+};
+
+static struct soundwire_slave alc1320_slave = {
+	.wake_up_unavailable = false,
+	.test_mode_supported = false,
+	.clock_stop_mode1_supported = true,
+	.simplified_clockstopprepare_sm_supported = true,
+	.clockstopprepare_hard_reset_behavior = false,
+	.highPHY_capable = false,
+	.paging_supported = false,
+	.bank_delay_supported = false,
+	.port15_read_behavior = false,
+	.source_port_list = SOUNDWIRE_PORT(2) | SOUNDWIRE_PORT(4),
+	.sink_port_list = SOUNDWIRE_PORT(1)
+};
+
+static struct soundwire_audio_mode alc1320_audio_mode = {
+	/* Bus frequency must be 1/2/4/8 divider of supported input frequencies. */
+	.bus_frequency_configs_count = 20,
+	.bus_frequency_configs = {
+		9600 * KHz,  4800 * KHz, 2400 * KHz, 1200 * KHz,	/* 19.2 MHz */
+		11289600,    5644800,    2822400,    1411200,		/* 22.5792 MHz */
+		12000 * KHz, 6000 * KHz, 3000 * KHz, 1500 * KHz,	/* 24 MHz */
+		12288 * KHz, 6144 * KHz, 3072 * KHz, 1536 * KHz,	/* 24.576 MHz */
+		16000 * KHz, 8000 * KHz, 4000 * KHz, 2000 * KHz,	/* 32 MHz */
+	},
+	/* Support 16 KHz to 192 KHz sampling frequency */
+	.sampling_frequency_configs_count = 6,
+	.sampling_frequency_configs = {
+		16 * KHz,
+		32 * KHz,
+		44.1 * KHz,
+		48 * KHz,
+		96 * KHz,
+		192 * KHz,
+	},
+	.prepare_channel_behavior = CHANNEL_PREPARE_ANY_FREQUENCY
+};
+
+static struct soundwire_dpn alc1320_dp1 = {
+	.port_wordlength_configs_count = 1,
+	.port_wordlength_configs = { 32 },
+	.data_port_type = FULL_DATA_PORT,
+	.max_grouping_supported = BLOCK_GROUP_COUNT_1,
+	.simplified_channelprepare_sm = false,
+	.imp_def_dpn_interrupts_supported = 0,
+	.min_channel_number = 1,
+	.max_channel_number = 2,
+	.modes_supported = MODE_ISOCHRONOUS | MODE_TX_CONTROLLED |
+			   MODE_RX_CONTROLLED | MODE_FULL_ASYNCHRONOUS,
+	.block_packing_mode = true,
+	.port_audio_mode_count = 1,
+	.port_audio_mode_list = { 0 }
+};
+
+static const struct soundwire_codec alc1320_codec = {
+	.slave = &alc1320_slave,
+	.audio_mode = { &alc1320_audio_mode },
+	.dpn = {
+		{
+			/* Data Input for Speaker Path */
+			.port = 1,
+			.sink = &alc1320_dp1
+		},
+		{
+			/* Data out for I.V sensing */
+			.port = 2,
+			.source = &alc1320_dp1
+		},
+		{
+			/* Data out for I.V sensing */
+			.port = 4,
+			.source = &alc1320_dp1
+		}
+	}
+
+};
+
+static void soundwire_alc1320_fill_ssdt(const struct device *dev)
+{
+	struct drivers_soundwire_alc1320_config *config = dev->chip_info;
+	const char *scope = acpi_device_scope(dev);
+	struct acpi_dp *dsd;
+
+	if (!dev->enabled || !scope)
+		return;
+
+	acpigen_write_scope(scope);
+	acpigen_write_device(acpi_device_name(dev));
+
+	/* Set codec address IDs. */
+	alc1320_address.link_id = dev->path.generic.id;
+	alc1320_address.unique_id = dev->path.generic.subid;
+
+	acpigen_write_ADR_soundwire_device(&alc1320_address);
+	acpigen_write_name_string("_DDN", config->desc ? : dev->chip_ops->name);
+	acpigen_write_STA(acpi_device_status(dev));
+
+	dsd = acpi_dp_new_table("_DSD");
+	soundwire_gen_codec(dsd, &alc1320_codec, NULL);
+	acpi_dp_write(dsd);
+
+	acpigen_pop_len(); /* Device */
+	acpigen_pop_len(); /* Scope */
+}
+
+static const char *soundwire_alc1320_acpi_name(const struct device *dev)
+{
+	struct drivers_soundwire_alc1320_config *config = dev->chip_info;
+	static char name[5];
+
+	if (config->name)
+		return config->name;
+	snprintf(name, sizeof(name), "SW%1X%1X", dev->path.generic.id, dev->path.generic.subid);
+	return name;
+}
+
+static struct device_operations soundwire_alc1320_ops = {
+	.read_resources		= noop_read_resources,
+	.set_resources		= noop_set_resources,
+	.acpi_name		= soundwire_alc1320_acpi_name,
+	.acpi_fill_ssdt		= soundwire_alc1320_fill_ssdt,
+};
+
+static void soundwire_alc1320_enable(struct device *dev)
+{
+	dev->ops = &soundwire_alc1320_ops;
+}
+
+struct chip_operations drivers_soundwire_alc1320_ops = {
+	.name = "Realtek ALC1320 SoundWire Codec",
+	.enable_dev = soundwire_alc1320_enable
+};
diff --git a/src/drivers/soundwire/alc1320/chip.h b/src/drivers/soundwire/alc1320/chip.h
new file mode 100644
index 0000000000..028c200219
--- /dev/null
+++ b/src/drivers/soundwire/alc1320/chip.h
@@ -0,0 +1,11 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef __DRIVERS_SOUNDWIRE_ALC1320_CHIP_H__
+#define __DRIVERS_SOUNDWIRE_ALC1320_CHIP_H__
+
+struct drivers_soundwire_alc1320_config {
+	const char *name;
+	const char *desc;
+};
+
+#endif /* __DRIVERS_SOUNDWIRE_ALC1320_CHIP_H__ */
diff --git a/src/include/mipi/ids.h b/src/include/mipi/ids.h
index a194de1938..c5d19ba22d 100644
--- a/src/include/mipi/ids.h
+++ b/src/include/mipi/ids.h
@@ -24,6 +24,8 @@
 #define MIPI_DEV_ID_REALTEK_ALC721		0x0721
 #define MIPI_DEV_ID_REALTEK_ALC722		0x0722
 #define MIPI_DEV_ID_REALTEK_ALC1308             0x1308
+#define MIPI_DEV_ID_REALTEK_ALC1320             0x1320
+
 
 #define MIPI_MFG_ID_MAXIM			0x019f
 #define MIPI_DEV_ID_MAXIM_MAX98373		0x8373

From 50178229ff307a0504452d99e94cb752aba8efa7 Mon Sep 17 00:00:00 2001
From: Johannes Hahn <johannes-hahn@siemens.com>
Date: Thu, 13 Feb 2025 10:14:12 +0100
Subject: [PATCH 0511/3886] mb/siemens/fa_ehl: Configure LPDDR4 from CBFS

Process the single SPD data file which resides in cbfs. Add Kconfig
switch for SPD data in cbfs and include Nanya_NT6AP512T32BV-J1I.spd.hex
into the build by adding a correspondig Makefile.mk in the spd folder.
Additionally to load the memory configuration FSP-M parameters for the
romstage are set.
Loading SPD data from HWILIB was the technique applied by mainboard
siemens/mc_ehl2 from which this mainboard was copied. On fa_ehl
SPD data is stored in CBFS and gets loaded from there.

Change-Id: If84373dfbc1ecbf916489af6e964f8a7541f5e7b
Signed-off-by: Johannes Hahn <johannes-hahn@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86424
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
---
 src/mainboard/siemens/fa_ehl/Kconfig          |  3 ++-
 src/mainboard/siemens/fa_ehl/Makefile.mk      |  2 ++
 .../siemens/fa_ehl/romstage_fsp_params.c      | 23 ++++---------------
 src/mainboard/siemens/fa_ehl/spd/Makefile.mk  |  3 +++
 .../spd/Nanya_NT6AP512T32BV-J1I.spd.hex       |  0
 src/mainboard/siemens/fa_ehl/spd/spd.h        | 14 +++++++++++
 .../fa_ehl/variants/fa_ehl/Makefile.mk        |  4 ----
 .../siemens/fa_ehl/variants/fa_ehl/memory.c   |  1 -
 8 files changed, 26 insertions(+), 24 deletions(-)
 create mode 100644 src/mainboard/siemens/fa_ehl/spd/Makefile.mk
 rename src/mainboard/siemens/fa_ehl/{variants/fa_ehl => }/spd/Nanya_NT6AP512T32BV-J1I.spd.hex (100%)
 create mode 100644 src/mainboard/siemens/fa_ehl/spd/spd.h

diff --git a/src/mainboard/siemens/fa_ehl/Kconfig b/src/mainboard/siemens/fa_ehl/Kconfig
index d15bda1b59..3821142ccb 100644
--- a/src/mainboard/siemens/fa_ehl/Kconfig
+++ b/src/mainboard/siemens/fa_ehl/Kconfig
@@ -6,8 +6,9 @@ config BOARD_SIEMENS_BASEBOARD_FA_EHL
 	select BOARD_ROMSIZE_KB_16384
 	select DRIVERS_I2C_GENERIC
 	select HAVE_ACPI_TABLES
-	select USE_SIEMENS_HWILIB
+	select HAVE_SPD_IN_CBFS
 	select SOC_INTEL_DISABLE_POWER_LIMITS
+	select USE_SIEMENS_HWILIB
 
 config BOARD_SIEMENS_FA_EHL
 	select BOARD_SIEMENS_BASEBOARD_FA_EHL
diff --git a/src/mainboard/siemens/fa_ehl/Makefile.mk b/src/mainboard/siemens/fa_ehl/Makefile.mk
index 574d595079..e34eddb9f1 100644
--- a/src/mainboard/siemens/fa_ehl/Makefile.mk
+++ b/src/mainboard/siemens/fa_ehl/Makefile.mk
@@ -1,5 +1,7 @@
 ## SPDX-License-Identifier: GPL-2.0-only
 
+subdirs-y += spd
+
 bootblock-y += bootblock.c
 
 romstage-y += romstage_fsp_params.c
diff --git a/src/mainboard/siemens/fa_ehl/romstage_fsp_params.c b/src/mainboard/siemens/fa_ehl/romstage_fsp_params.c
index 506bcc6824..926b202bc6 100644
--- a/src/mainboard/siemens/fa_ehl/romstage_fsp_params.c
+++ b/src/mainboard/siemens/fa_ehl/romstage_fsp_params.c
@@ -1,10 +1,8 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
 #include <baseboard/variants.h>
-#include <console/console.h>
 #include <device/dram/common.h>
 #include <device/mmio.h>
-#include <hwilib.h>
 #include <soc/meminit.h>
 #include <soc/romstage.h>
 #include <string.h>
@@ -14,23 +12,12 @@ void mainboard_memory_init_params(FSPM_UPD *memupd)
 {
 	static struct spd_info spd_info;
 	const struct mb_cfg *board_cfg = variant_memcfg_config();
-	static uint8_t spd_data[CONFIG_DIMM_SPD_SIZE];
-	const char *cbfs_hwi_name = "hwinfo.hex";
 
-	/* Initialize SPD information for LPDDR4x from HW-Info primarily with a fallback to
-	   spd.bin in the case where the SPD data in HW-Info is not available or invalid. */
-	memset(spd_data, 0, sizeof(spd_data));
-	if ((hwilib_find_blocks(cbfs_hwi_name) == CB_SUCCESS) &&
-	    (hwilib_get_field(SPD, spd_data, 0x80) == 0x80) &&
-	    (ddr_crc16(spd_data, 126) == read16((void *)&spd_data[126]))) {
-		spd_info.spd_spec.spd_data_ptr_info.spd_data_ptr = (uintptr_t)spd_data;
-		spd_info.spd_spec.spd_data_ptr_info.spd_data_len = CONFIG_DIMM_SPD_SIZE;
-		spd_info.read_type = READ_SPD_MEMPTR;
-	} else {
-		die("SPD in HW-Info not valid!\n");
-	}
-	/* Initialize variant specific configurations */
-	memcfg_init(&memupd->FspmConfig, board_cfg, &spd_info, false);
+	bool half_populated = false;
+	spd_info.read_type = READ_SPD_CBFS;
+	spd_info.spd_spec.spd_index = 0x00;
+
+	memcfg_init(&memupd->FspmConfig, board_cfg, &spd_info, half_populated);
 
 	/* Enable Row-Hammer prevention */
 	memupd->FspmConfig.RhPrevention = 1;
diff --git a/src/mainboard/siemens/fa_ehl/spd/Makefile.mk b/src/mainboard/siemens/fa_ehl/spd/Makefile.mk
new file mode 100644
index 0000000000..5b98d884d4
--- /dev/null
+++ b/src/mainboard/siemens/fa_ehl/spd/Makefile.mk
@@ -0,0 +1,3 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
+SPD_SOURCES = Nanya_NT6AP512T32BV-J1I	# 0b000
diff --git a/src/mainboard/siemens/fa_ehl/variants/fa_ehl/spd/Nanya_NT6AP512T32BV-J1I.spd.hex b/src/mainboard/siemens/fa_ehl/spd/Nanya_NT6AP512T32BV-J1I.spd.hex
similarity index 100%
rename from src/mainboard/siemens/fa_ehl/variants/fa_ehl/spd/Nanya_NT6AP512T32BV-J1I.spd.hex
rename to src/mainboard/siemens/fa_ehl/spd/Nanya_NT6AP512T32BV-J1I.spd.hex
diff --git a/src/mainboard/siemens/fa_ehl/spd/spd.h b/src/mainboard/siemens/fa_ehl/spd/spd.h
new file mode 100644
index 0000000000..e2fe0f3e6f
--- /dev/null
+++ b/src/mainboard/siemens/fa_ehl/spd/spd.h
@@ -0,0 +1,14 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef MAINBOARD_SPD_H
+#define MAINBOARD_SPD_H
+
+#include <stdint.h>
+
+void mainboard_fill_dq_map_ch0(u8 *dq_map_ptr);
+void mainboard_fill_dq_map_ch1(u8 *dq_map_ptr);
+void mainboard_fill_dqs_map_ch0(u8 *dqs_map_ptr);
+void mainboard_fill_dqs_map_ch1(u8 *dqs_map_ptr);
+void mainboard_fill_rcomp_res_data(u16 *rcomp_ptr);
+void mainboard_fill_rcomp_strength_data(u16 *rcomp_strength_ptr);
+#endif
diff --git a/src/mainboard/siemens/fa_ehl/variants/fa_ehl/Makefile.mk b/src/mainboard/siemens/fa_ehl/variants/fa_ehl/Makefile.mk
index d49412eba2..6e87f9fc1a 100644
--- a/src/mainboard/siemens/fa_ehl/variants/fa_ehl/Makefile.mk
+++ b/src/mainboard/siemens/fa_ehl/variants/fa_ehl/Makefile.mk
@@ -4,7 +4,3 @@ bootblock-y += gpio.c
 romstage-y += memory.c
 ramstage-y += gpio.c
 ramstage-y += mainboard.c
-
-SPD_SOURCES = Micron_MT53E512M32D1NP-046WTB.spd.hex
-LIB_SPD_CBFS := $(foreach f, $(SPD_SOURCES), \
-		src/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/spd/$(f).spd.hex)
diff --git a/src/mainboard/siemens/fa_ehl/variants/fa_ehl/memory.c b/src/mainboard/siemens/fa_ehl/variants/fa_ehl/memory.c
index 8088857b28..31d0a08399 100644
--- a/src/mainboard/siemens/fa_ehl/variants/fa_ehl/memory.c
+++ b/src/mainboard/siemens/fa_ehl/variants/fa_ehl/memory.c
@@ -1,7 +1,6 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
 #include <baseboard/variants.h>
-#include <gpio.h>
 #include <soc/meminit.h>
 #include <soc/romstage.h>
 

From 3856d0fa907c7b9c7e4ddc555d68843ca7978827 Mon Sep 17 00:00:00 2001
From: Zheng Bao <fishbaozi@gmail.com>
Date: Fri, 4 Oct 2024 22:38:22 +0800
Subject: [PATCH 0512/3886] amdfwtool: Set address mode of BIOS binary as
 context defines

Other types of FWs in the BIOS table are defined by context. So the
BIOS binary should follow that.
TEST=Binary identical test on platforms before mendocino
Tested on Skyrim

Change-Id: I9c2f2983d03c913b28fbd87aa0925a32a4649d62
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85466
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 util/amdfwtool/amdfwtool.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/util/amdfwtool/amdfwtool.c b/util/amdfwtool/amdfwtool.c
index b59c10f21a..c2a83ea637 100644
--- a/util/amdfwtool/amdfwtool.c
+++ b/util/amdfwtool/amdfwtool.c
@@ -1453,9 +1453,9 @@ static void integrate_bios_firmwares(context *ctx,
 			}
 
 			biosdir->entries[count].source =
-				RUN_CURRENT_MODE(*ctx, AMD_ADDR_REL_BIOS);
+				RUN_CURRENT(*ctx);
 			biosdir->entries[count].address_mode =
-				SET_ADDR_MODE(biosdir, AMD_ADDR_REL_BIOS);
+				SET_ADDR_MODE_BY_TABLE(biosdir);
 
 			adjust_current_pointer(ctx, bytes, 0x100U);
 			break;

From 1fa5ab805bb180e29e872c655d93c9c439d063e9 Mon Sep 17 00:00:00 2001
From: Jeremy Compostella <jeremy.compostella@intel.com>
Date: Tue, 25 Mar 2025 10:00:01 -0700
Subject: [PATCH 0513/3886] mb/google/fatcat: Remove unnecessary CNVi core
 variables settings

config->cnvi_wifi_core and config->cnvi_bt_core are false by
default. This commit suppresses the acpi/acpigen.h inclusion, which is
unnecessary as well.

Change-Id: I2e171d6388b472f4cb877fdd93771142f9a3f2de
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86994
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Pranava Y N <pranavayn@google.com>
Reviewed-by: Jayvik Desai <jayvik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
---
 src/mainboard/google/fatcat/variants/fatcat/variant.c | 3 ---
 1 file changed, 3 deletions(-)

diff --git a/src/mainboard/google/fatcat/variants/fatcat/variant.c b/src/mainboard/google/fatcat/variants/fatcat/variant.c
index c7aa7aa605..85c92430f7 100644
--- a/src/mainboard/google/fatcat/variants/fatcat/variant.c
+++ b/src/mainboard/google/fatcat/variants/fatcat/variant.c
@@ -1,6 +1,5 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
-#include <acpi/acpigen.h>
 #include <baseboard/variants.h>
 #include <fw_config.h>
 #include <sar.h>
@@ -12,8 +11,6 @@ const char *get_wifi_sar_cbfs_filename(void)
 
 void variant_update_soc_chip_config(struct soc_intel_pantherlake_config *config)
 {
-	config->cnvi_wifi_core = false;
-	config->cnvi_bt_core = false;
 	/* CNVi */
 	if (fw_config_probe(FW_CONFIG(WIFI, WIFI_CNVI_6)) ||
 		fw_config_probe(FW_CONFIG(WIFI, WIFI_CNVI_7))) {

From cb956861a181499ac65c236602af95f4b1bb802e Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Wed, 26 Mar 2025 20:59:14 +0000
Subject: [PATCH 0514/3886] mb/starlabs/starbook/mtl: Correct the config for
 eSPI strap

The comment was reversed for the eSPI strap, so the GPIO was
misconfigured. Correct the comment and config accordingly.

Change-Id: I494d247ea4625fa1633ffa6d073b48f1dbf8432f
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87007
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
---
 src/mainboard/starlabs/starbook/variants/mtl/gpio.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/src/mainboard/starlabs/starbook/variants/mtl/gpio.c b/src/mainboard/starlabs/starbook/variants/mtl/gpio.c
index 7a7ee1e73a..a12b1b0cbd 100644
--- a/src/mainboard/starlabs/starbook/variants/mtl/gpio.c
+++ b/src/mainboard/starlabs/starbook/variants/mtl/gpio.c
@@ -92,10 +92,10 @@ const struct pad_config gpio_table[] = {
 	/* C04:	SML0_DATA			*/
 	PAD_NC(GPP_C04, NONE),
 	/* C05:	ESPI
-	 *		HIGH:	ENABLED
-	 *		LOW:	DISABLED
+	 *		HIGH:	DISABLED
+	 *		LOW:	ENABLED
 	 *		WEAK INTERNAL PD 20K	*/
-	PAD_CFG_GPO(GPP_C05, 1, PLTRST),
+	PAD_CFG_GPO(GPP_C05, 0, PLTRST),
 	/* C06:	SML1_CLK_USBC_PD_N		*/
 	PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_C06, NONE, DEEP, NF1),
 	/* C07:	SML1_DATA_USBC_PD_N		*/

From bb70c757006c7732510fc85468742af7b88f8ea9 Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Wed, 26 Mar 2025 21:00:37 +0000
Subject: [PATCH 0515/3886] mb/starlabs/starbook/mtl: Configure eSPI GPIOs

Meteor Lake doesn't seem to configure the eSPI GPIOs for S3 on
reset, so add configuration from them so coreboot can configure
them correctly.

Change-Id: I4b74d320977faa60441e3d8b12980ef6ec41549d
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87008
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/starlabs/starbook/variants/mtl/gpio.c | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/src/mainboard/starlabs/starbook/variants/mtl/gpio.c b/src/mainboard/starlabs/starbook/variants/mtl/gpio.c
index a12b1b0cbd..7255e9061f 100644
--- a/src/mainboard/starlabs/starbook/variants/mtl/gpio.c
+++ b/src/mainboard/starlabs/starbook/variants/mtl/gpio.c
@@ -140,12 +140,19 @@ const struct pad_config gpio_table[] = {
 	 * End:		GPP_A23
 	 */
 	/* A00:	ESPI_IO0_EC_R			*/
+	PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_A00, UP_20K, DEEP, NF1),
 	/* A01:	ESPI_IO1_EC_R			*/
+	PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_A01, UP_20K, DEEP, NF1),
 	/* A02:	ESPI_IO2_EC_R			*/
+	PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_A02, UP_20K, DEEP, NF1),
 	/* A03:	ESPI_IO3_EC_R			*/
+	PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_A03, UP_20K, DEEP, NF1),
 	/* A04:	ESPI_CS0_N			*/
+	PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_A04, UP_20K, DEEP, NF1),
 	/* A05:	ESPI_CLK_EC_R			*/
+	PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_A05, UP_20K, DEEP, NF1),
 	/* A06:	ESPI_RESET_N			*/
+	PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_A06, NONE, DEEP, NF1),
 	/* A07:					*/
 	PAD_NC(GPP_A07, NONE),
 	/* A08:					*/

From 811ab788d11cc017f775e0f5f0ead2079d1ab936 Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Wed, 26 Mar 2025 21:01:47 +0000
Subject: [PATCH 0516/3886] mb/starlabs/starbook/mtl: Disconnect WLAN PEWAKE
 GPIO

This GPIO isn't conencted, so configure it accordingly.

Change-Id: I2b027a1181de67e9a33bbb2062573c071827134a
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87009
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
---
 src/mainboard/starlabs/starbook/variants/mtl/gpio.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/mainboard/starlabs/starbook/variants/mtl/gpio.c b/src/mainboard/starlabs/starbook/variants/mtl/gpio.c
index 7255e9061f..8bfad056a0 100644
--- a/src/mainboard/starlabs/starbook/variants/mtl/gpio.c
+++ b/src/mainboard/starlabs/starbook/variants/mtl/gpio.c
@@ -164,7 +164,7 @@ const struct pad_config gpio_table[] = {
 	/* A11:					*/
 	PAD_NC(GPP_A11, NONE),
 	/* A12:	WLAN_PEWAKE			*/
-	PAD_CFG_GPI(GPP_A12, NONE, DEEP),
+	PAD_NC(GPP_A12, NONE),
 	/* A13:					*/
 	PAD_NC(GPP_A13, NONE),
 	/* A14:					*/

From 5d5a06a71f93f444aa4e923f671dc3bc766e59fc Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Wed, 26 Mar 2025 21:03:12 +0000
Subject: [PATCH 0517/3886] mb/starlabs/starbook/mtl: Add comments for Top Swap
 Override GPIO

This GPIO is conected to the Top Swap Override strap, so add comments
to that effect, and an explicit config to disable it.

Change-Id: I183fc60c61ec82f0d27a0d3726f0d3c37ddee04a
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87010
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/starlabs/starbook/variants/mtl/gpio.c | 7 +++++--
 1 file changed, 5 insertions(+), 2 deletions(-)

diff --git a/src/mainboard/starlabs/starbook/variants/mtl/gpio.c b/src/mainboard/starlabs/starbook/variants/mtl/gpio.c
index 8bfad056a0..c71a23eafc 100644
--- a/src/mainboard/starlabs/starbook/variants/mtl/gpio.c
+++ b/src/mainboard/starlabs/starbook/variants/mtl/gpio.c
@@ -419,8 +419,11 @@ const struct pad_config gpio_table[] = {
 	PAD_NC(GPP_B12, NONE),
 	/* B13:	PLT_RST_N			*/
 	PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1),
-	/* B14:					*/
-	PAD_NC(GPP_B14, NONE),
+	/* B14:	Top Swap Override
+	 *		HIGH:	EMABLED
+	 *		LOW:	DISABLED
+	 *		WEAK INTERNAL PD 20K	*/
+	PAD_CFG_GPO(GPP_B14, 0, PLTRST),
 	/* B15:					*/
 	PAD_NC(GPP_B15, NONE),
 	/* B16:	DDIB_DP_HPD			*/

From 69a3af77a0c238cb3e634d6dc297acc50fbe9d3b Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Wed, 26 Mar 2025 21:04:53 +0000
Subject: [PATCH 0518/3886] mb/starlabs/starbook/mtl: Add explicit configs for
 strap GPIOs

Rather than setting the pads to Not Connected for low, configure
them as output GPIOs driven low; this isn't a functional change,
but just makes it easier to read.

Change-Id: Ia8fa495ff9a7b25195fbf39b4090bc57a48bf4e8
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87011
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
---
 src/mainboard/starlabs/starbook/variants/mtl/gpio.c | 11 ++++++-----
 1 file changed, 6 insertions(+), 5 deletions(-)

diff --git a/src/mainboard/starlabs/starbook/variants/mtl/gpio.c b/src/mainboard/starlabs/starbook/variants/mtl/gpio.c
index c71a23eafc..e658cdec7a 100644
--- a/src/mainboard/starlabs/starbook/variants/mtl/gpio.c
+++ b/src/mainboard/starlabs/starbook/variants/mtl/gpio.c
@@ -116,7 +116,7 @@ const struct pad_config gpio_table[] = {
 	PAD_NC(GPP_C14, NONE),
 	/* C15:	RESERVED
 	 *		WEAK INTERNAL PD 20K	*/
-	PAD_NC(GPP_C15, NONE),
+	PAD_CFG_GPO(GPP_C15, 0, DEEP),
 	/* C16:					*/
 	PAD_NC(GPP_C16, NONE),
 	/* C17:					*/
@@ -209,6 +209,7 @@ const struct pad_config gpio_table[] = {
 	 *		HIGH:	ENABLED
 	 *		LOW:	DISABLED
 	 *		20K INTERNAL PU		*/
+	PAD_CFG_GPO(GPP_E06, 0, DEEP),
 	/* E07:					*/
 	PAD_NC(GPP_E07, NONE),
 	/* E08:					*/
@@ -255,7 +256,7 @@ const struct pad_config gpio_table[] = {
 	 *		HIGH:	ENABLED
 	 *		LOW:	DISABLED
 	 *		WEAK INTERNAL PD 20K	*/
-	PAD_NC(GPP_H01, NONE),
+	PAD_CFG_GPO(GPP_H01, 0, DEEP),
 	/* H02:	WLAN_RST_N			*/
 	PAD_CFG_GPO(GPP_H02, 1, PLTRST),
 	/* H03:					*/
@@ -344,17 +345,17 @@ const struct pad_config gpio_table[] = {
 	 *		HIGH:	MASTER
 	 *		LOW:	SLAVE
 	 *		WEAK INTERNAL PD 20K	*/
-	PAD_NC(GPP_F19, NONE),
+	PAD_CFG_GPO(GPP_F19, 0, DEEP),
 	/* F20:	SVID
 	 *		HIGH:	PRESENT
 	 *		LOW:	NOT PRESENT
 	 *		WEAK INTERNAL PD 20K	*/
-	PAD_NC(GPP_F20, NONE),
+	PAD_CFG_GPO(GPP_F20, 0, DEEP),
 	/* F21:	CCD
 	 *		HIGH:	BALTIC PEAK
 	 *		LOW:	BSSB-LS
 	 *		WEAK INTERNAL PU 20K	*/
-	PAD_NC(GPP_F21, NONE),
+	PAD_CFG_GPO(GPP_F21, 0, DEEP),
 	/* F22:					*/
 	PAD_NC(GPP_F22, NONE),
 	/* F23:					*/

From 30af663a0a98a97b7ce33af1b43f40a9f0bd0d03 Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Wed, 26 Mar 2025 21:06:22 +0000
Subject: [PATCH 0519/3886] mb/starlabs/starbook/mtl: Configure the Boot Halt
 GPIO

This pin is connected, so configure it to NF2 accordingly.

Change-Id: Iae8730a875fa0b2f4036f278591ece5a5fa5c5d1
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87012
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/starlabs/starbook/variants/mtl/gpio.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/mainboard/starlabs/starbook/variants/mtl/gpio.c b/src/mainboard/starlabs/starbook/variants/mtl/gpio.c
index e658cdec7a..94896962f9 100644
--- a/src/mainboard/starlabs/starbook/variants/mtl/gpio.c
+++ b/src/mainboard/starlabs/starbook/variants/mtl/gpio.c
@@ -227,7 +227,7 @@ const struct pad_config gpio_table[] = {
 	/* E14:	EDP_HPD_N			*/
 	PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1),
 	/* E15:	BOOTHALT_N			*/
-	PAD_NC(GPP_E15, NONE),
+	PAD_CFG_NF(GPP_E15, NONE, DEEP, NF2),
 	/* E16:	BC_PROCHOT_N			*/
 	PAD_CFG_GPI_SCI(GPP_E16, NONE, PLTRST, EDGE_SINGLE, INVERT),
 	/* E17:					*/

From 7eb97dfda18b0983643beaea01849c56eb8eefaa Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Wed, 26 Mar 2025 21:10:17 +0000
Subject: [PATCH 0520/3886] mb/starlabs/starbook/mtl: Configure SML1ALERT GPIO

This pad is connected, so configure it accordingly.

Change-Id: I3ef2fd3793c31a6e2f62ff621ab0ed9bb4595b79
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87014
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/starlabs/starbook/variants/mtl/gpio.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/mainboard/starlabs/starbook/variants/mtl/gpio.c b/src/mainboard/starlabs/starbook/variants/mtl/gpio.c
index 94896962f9..8619f24c25 100644
--- a/src/mainboard/starlabs/starbook/variants/mtl/gpio.c
+++ b/src/mainboard/starlabs/starbook/variants/mtl/gpio.c
@@ -101,7 +101,7 @@ const struct pad_config gpio_table[] = {
 	/* C07:	SML1_DATA_USBC_PD_N		*/
 	PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_C07, NONE, DEEP, NF1),
 	/* C08:	SML1ALERT			*/
-	PAD_NC(GPP_C08, NONE),
+	PAD_CFG_NF(GPP_C08, NONE, DEEP, NF1),
 	/* C09:					*/
 	PAD_NC(GPP_C09, NONE),
 	/* C10:					*/

From ea6441b1d3ef095930f9e524d130c19046c55f52 Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Wed, 26 Mar 2025 16:22:05 +0000
Subject: [PATCH 0521/3886] soc/intel/common/cnvi: Add missing PRRS name
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Add the PRRS object that is used in the _RST method.

Change-Id: I935fae3c215e48288d8856d7be5cacc4e261d86f
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87005
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
---
 src/soc/intel/common/block/cnvi/cnvi.c | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/src/soc/intel/common/block/cnvi/cnvi.c b/src/soc/intel/common/block/cnvi/cnvi.c
index 88225fe1e8..1c668ba736 100644
--- a/src/soc/intel/common/block/cnvi/cnvi.c
+++ b/src/soc/intel/common/block/cnvi/cnvi.c
@@ -86,6 +86,11 @@ static void cnvw_fill_ssdt(const struct device *dev)
 	acpigen_write_field("CWAR", fields2, ARRAY_SIZE(fields2),
 		FIELD_BYTEACC | FIELD_NOLOCK | FIELD_PRESERVE);
 
+/*
+ *	Name (PRRS, Zero)
+ */
+	acpigen_write_name_integer("PRRS", 0);
+
 /*
  *	Name (RSTT, Zero)
  */

From 4dffa65d7e65e20ccc6c5fd290fbf1ffaa557a1c Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Wed, 26 Mar 2025 21:15:41 +0000
Subject: [PATCH 0522/3886] mb/starlabs/starbook/mtl: Enable Port Reset Message

Enable the Port Reset Message for the two USB Type-C ports.

Change-Id: I181db4cfd3a50915337816c91f1b2feb3f874b06
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87018
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/starlabs/starbook/variants/mtl/devicetree.cb | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/mainboard/starlabs/starbook/variants/mtl/devicetree.cb b/src/mainboard/starlabs/starbook/variants/mtl/devicetree.cb
index cbda85d152..43bcd0fbae 100644
--- a/src/mainboard/starlabs/starbook/variants/mtl/devicetree.cb
+++ b/src/mainboard/starlabs/starbook/variants/mtl/devicetree.cb
@@ -74,11 +74,11 @@ chip soc/intel/meteorlake
 		device ref gna		on  end
 		device ref xhci		on
 			# Motherboard USB 3.0 Type-C Back	7893 mil
-			register "usb2_ports[0]"		= "USB2_PORT_MID(OC_SKIP)"
+			register "usb2_ports[0]"		= "USB2_PORT_TYPE_C(OC_SKIP)"
 			register "tcss_ports[0]"		= "TCSS_PORT_DEFAULT(OC_SKIP)"
 
 			# Motherboard USB 3.0 Type-C Front	9557 mil
-			register "usb2_ports[2]"		= "USB2_PORT_MID(OC_SKIP)"
+			register "usb2_ports[2]"		= "USB2_PORT_TYPE_C(OC_SKIP)"
 			register "tcss_ports[1]"		= "TCSS_PORT_DEFAULT(OC_SKIP)"
 
 			# Motherboard USB 3.0 Type-A		8916 mil

From 37c968d89913f9cbf9b9d3476eec48806416a5d2 Mon Sep 17 00:00:00 2001
From: Maximilian Brune <maximilian.brune@9elements.com>
Date: Sat, 15 Mar 2025 14:38:29 +0100
Subject: [PATCH 0523/3886] Revert "soc/amd/glinda/Kconfig: Increase APOB NV
 size"

This reverts commit 362232d2365064286c4202ff2d2777fd8e855c24.

Reason for revert:
This introduced an overlap between APOB DRAM region and SHAREDMEM
region used for PSP verstage. Our linker scripts would have caught that,
but we don't have any glinda based mainboards using VBOOT in the tree
at the moment so there is no actual overlap on any upstream mainboards
at the moment. Still if VBOOT based mainboards are added in the future
it would cause a build error for them.

The next patch in the train will increase the APOB NV size properly by
increasing all the other addresses in the chain too.

Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: I4b4cb4104a59f72491a941dc1d13018f2389bb03
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86861
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/amd/birman/board_glinda.fmd         | 2 +-
 src/mainboard/amd/birman/chromeos_glinda.fmd      | 2 +-
 src/mainboard/amd/birman_plus/board_glinda.fmd    | 2 +-
 src/mainboard/amd/birman_plus/chromeos_glinda.fmd | 2 +-
 src/soc/amd/glinda/Kconfig                        | 2 +-
 5 files changed, 5 insertions(+), 5 deletions(-)

diff --git a/src/mainboard/amd/birman/board_glinda.fmd b/src/mainboard/amd/birman/board_glinda.fmd
index bc09fe75d5..756709044e 100644
--- a/src/mainboard/amd/birman/board_glinda.fmd
+++ b/src/mainboard/amd/birman/board_glinda.fmd
@@ -4,6 +4,6 @@ FLASH@0xFF000000 16M {
 		FMAP 4K
 		COREBOOT(CBFS)
 		EC_BODY@15872K 256K
-		RW_MRC_CACHE 256K
+		RW_MRC_CACHE 120K
 	}
 }
diff --git a/src/mainboard/amd/birman/chromeos_glinda.fmd b/src/mainboard/amd/birman/chromeos_glinda.fmd
index 420ed6e6d4..66227c2778 100644
--- a/src/mainboard/amd/birman/chromeos_glinda.fmd
+++ b/src/mainboard/amd/birman/chromeos_glinda.fmd
@@ -30,6 +30,6 @@ FLASH@0xFF000000 16M {
 		SMMSTORE(PRESERVE) 256K
 		RW_LEGACY(CBFS)
 		EC_BODY@15872K 256K
-		RW_MRC_CACHE(PRESERVE) 256K
+		RW_MRC_CACHE(PRESERVE) 120K
 	}
 }
diff --git a/src/mainboard/amd/birman_plus/board_glinda.fmd b/src/mainboard/amd/birman_plus/board_glinda.fmd
index 96e1e8d8f0..b9465768be 100644
--- a/src/mainboard/amd/birman_plus/board_glinda.fmd
+++ b/src/mainboard/amd/birman_plus/board_glinda.fmd
@@ -5,6 +5,6 @@ FLASH 64M {
 		COREBOOT(CBFS)
 		SMMSTORE(PRESERVE) 256K
 		EC_BODY@15872K 256K
-		RW_MRC_CACHE 256K
+		RW_MRC_CACHE 120K
 	}
 }
diff --git a/src/mainboard/amd/birman_plus/chromeos_glinda.fmd b/src/mainboard/amd/birman_plus/chromeos_glinda.fmd
index 420ed6e6d4..66227c2778 100644
--- a/src/mainboard/amd/birman_plus/chromeos_glinda.fmd
+++ b/src/mainboard/amd/birman_plus/chromeos_glinda.fmd
@@ -30,6 +30,6 @@ FLASH@0xFF000000 16M {
 		SMMSTORE(PRESERVE) 256K
 		RW_LEGACY(CBFS)
 		EC_BODY@15872K 256K
-		RW_MRC_CACHE(PRESERVE) 256K
+		RW_MRC_CACHE(PRESERVE) 120K
 	}
 }
diff --git a/src/soc/amd/glinda/Kconfig b/src/soc/amd/glinda/Kconfig
index a0d64c62d7..2e9381d57a 100644
--- a/src/soc/amd/glinda/Kconfig
+++ b/src/soc/amd/glinda/Kconfig
@@ -123,7 +123,7 @@ config PSP_APOB_DRAM_ADDRESS
 
 config PSP_APOB_DRAM_SIZE
 	hex
-	default 0x40000
+	default 0x1E000
 
 config PSP_SHAREDMEM_BASE
 	hex

From a38cb1bd4315adb1aa187134cd7d6f57c8e08f19 Mon Sep 17 00:00:00 2001
From: Maximilian Brune <maximilian.brune@9elements.com>
Date: Wed, 12 Mar 2025 22:48:14 +0100
Subject: [PATCH 0524/3886] soc/amd/glinda/Kconfig: Increase APOB NV size

A glinda based platform reports:
[WARN] RAM APOB data is too large (3b3b0 + 8) > 1e000

APOB NV size is not enough on recent platforms to cache memory training,
which causes the same amount of boot time on subsequent boots as on the
first boot.

This time increase the size properly by adjusting the base address of
the components that come after the APOB region.

Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: I070cf766b98825cd5ff37674e1f9651fa71159c4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86849
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
---
 src/mainboard/amd/birman/board_glinda.fmd         |  2 +-
 src/mainboard/amd/birman/chromeos_glinda.fmd      |  2 +-
 src/mainboard/amd/birman_plus/board_glinda.fmd    |  2 +-
 src/mainboard/amd/birman_plus/chromeos_glinda.fmd |  2 +-
 src/soc/amd/glinda/Kconfig                        | 10 +++++-----
 5 files changed, 9 insertions(+), 9 deletions(-)

diff --git a/src/mainboard/amd/birman/board_glinda.fmd b/src/mainboard/amd/birman/board_glinda.fmd
index 756709044e..bc09fe75d5 100644
--- a/src/mainboard/amd/birman/board_glinda.fmd
+++ b/src/mainboard/amd/birman/board_glinda.fmd
@@ -4,6 +4,6 @@ FLASH@0xFF000000 16M {
 		FMAP 4K
 		COREBOOT(CBFS)
 		EC_BODY@15872K 256K
-		RW_MRC_CACHE 120K
+		RW_MRC_CACHE 256K
 	}
 }
diff --git a/src/mainboard/amd/birman/chromeos_glinda.fmd b/src/mainboard/amd/birman/chromeos_glinda.fmd
index 66227c2778..420ed6e6d4 100644
--- a/src/mainboard/amd/birman/chromeos_glinda.fmd
+++ b/src/mainboard/amd/birman/chromeos_glinda.fmd
@@ -30,6 +30,6 @@ FLASH@0xFF000000 16M {
 		SMMSTORE(PRESERVE) 256K
 		RW_LEGACY(CBFS)
 		EC_BODY@15872K 256K
-		RW_MRC_CACHE(PRESERVE) 120K
+		RW_MRC_CACHE(PRESERVE) 256K
 	}
 }
diff --git a/src/mainboard/amd/birman_plus/board_glinda.fmd b/src/mainboard/amd/birman_plus/board_glinda.fmd
index b9465768be..96e1e8d8f0 100644
--- a/src/mainboard/amd/birman_plus/board_glinda.fmd
+++ b/src/mainboard/amd/birman_plus/board_glinda.fmd
@@ -5,6 +5,6 @@ FLASH 64M {
 		COREBOOT(CBFS)
 		SMMSTORE(PRESERVE) 256K
 		EC_BODY@15872K 256K
-		RW_MRC_CACHE 120K
+		RW_MRC_CACHE 256K
 	}
 }
diff --git a/src/mainboard/amd/birman_plus/chromeos_glinda.fmd b/src/mainboard/amd/birman_plus/chromeos_glinda.fmd
index 66227c2778..420ed6e6d4 100644
--- a/src/mainboard/amd/birman_plus/chromeos_glinda.fmd
+++ b/src/mainboard/amd/birman_plus/chromeos_glinda.fmd
@@ -30,6 +30,6 @@ FLASH@0xFF000000 16M {
 		SMMSTORE(PRESERVE) 256K
 		RW_LEGACY(CBFS)
 		EC_BODY@15872K 256K
-		RW_MRC_CACHE(PRESERVE) 120K
+		RW_MRC_CACHE(PRESERVE) 256K
 	}
 }
diff --git a/src/soc/amd/glinda/Kconfig b/src/soc/amd/glinda/Kconfig
index 2e9381d57a..a02492cb8c 100644
--- a/src/soc/amd/glinda/Kconfig
+++ b/src/soc/amd/glinda/Kconfig
@@ -123,11 +123,11 @@ config PSP_APOB_DRAM_ADDRESS
 
 config PSP_APOB_DRAM_SIZE
 	hex
-	default 0x1E000
+	default 0x40000
 
 config PSP_SHAREDMEM_BASE
 	hex
-	default 0x201F000 if VBOOT
+	default 0x2041000 if VBOOT
 	default 0x0
 	help
 	  This variable defines the base address in DRAM memory where PSP copies
@@ -172,7 +172,7 @@ config C_ENV_BOOTBLOCK_SIZE
 
 config ROMSTAGE_ADDR
 	hex
-	default 0x2050000
+	default 0x2070000
 	help
 	  Sets the address in DRAM where romstage should be loaded.
 
@@ -184,7 +184,7 @@ config ROMSTAGE_SIZE
 
 config FSP_M_ADDR
 	hex
-	default 0x20C0000
+	default 0x20E0000
 	help
 	  Sets the address in DRAM where FSP-M should be loaded. cbfstool
 	  performs relocation of FSP-M to this address.
@@ -204,7 +204,7 @@ config FSP_TEMP_RAM_SIZE
 config VERSTAGE_ADDR
 	hex
 	depends on VBOOT_SEPARATE_VERSTAGE
-	default 0x2180000
+	default 0x21A0000
 	help
 	  Sets the address in DRAM where verstage should be loaded if running
 	  as a separate stage on x86.

From 3356bf0d683d86192f1442912834fcd5a621050a Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Thu, 31 Aug 2023 10:12:15 -0500
Subject: [PATCH 0525/3886] mb/google/volteer: Include ACPI for GNA scoring
 accelerator

Since the PCI device is already enabled, include the ACPI stub so the
OS driver can attach.

TEST=build/boot Win10 on google/volteer (drobit)

Change-Id: I9f9edcdd3c32d66af64878b6d8735019bccddd26
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Signed-off-by: CoolStar <coolstarorganization@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77578
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
---
 src/mainboard/google/volteer/dsdt.asl | 1 +
 1 file changed, 1 insertion(+)

diff --git a/src/mainboard/google/volteer/dsdt.asl b/src/mainboard/google/volteer/dsdt.asl
index eeaf61379f..c200294e74 100644
--- a/src/mainboard/google/volteer/dsdt.asl
+++ b/src/mainboard/google/volteer/dsdt.asl
@@ -28,6 +28,7 @@ DefinitionBlock(
 			#include <soc/intel/common/block/acpi/acpi/northbridge.asl>
 			#include <soc/intel/tigerlake/acpi/southbridge.asl>
 			#include <soc/intel/tigerlake/acpi/tcss.asl>
+			#include <soc/intel/common/block/acpi/acpi/gna.asl>
 			#include <drivers/intel/gma/acpi/default_brightness_levels.asl>
 #if CONFIG(VARIANT_HAS_MIPI_CAMERA)
 			#include <soc/intel/common/block/acpi/acpi/ipu.asl>

From 0f38b6b1ba2bdea26c2b8988195fc2c5e57b50a4 Mon Sep 17 00:00:00 2001
From: Keith Hui <buurin@gmail.com>
Date: Thu, 28 Nov 2024 15:05:58 -0500
Subject: [PATCH 0526/3886] mb/asus/p8x7x-series: Mark variants using GPIO8 for
 power LED

All boards in the family have the negative leg of power LED linked
to a PCH GPIO pin, either GPIO 27 or 8.

After examining their boardviews, mark p8h77-v and p8z77-v_lx2
variants through Kconfig as using GPIO8 for power LED.

Change-Id: I4d42cd9ac497a4200ab5c90d09eb4dbab8917b30
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82556
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/asus/p8x7x-series/Kconfig | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/src/mainboard/asus/p8x7x-series/Kconfig b/src/mainboard/asus/p8x7x-series/Kconfig
index 133bd94ca9..d555cc67a7 100644
--- a/src/mainboard/asus/p8x7x-series/Kconfig
+++ b/src/mainboard/asus/p8x7x-series/Kconfig
@@ -25,6 +25,7 @@ config BOARD_ASUS_P8H77_V
 	select BOARD_ROMSIZE_KB_8192
 	select SUPERIO_NUVOTON_NCT6779D
 	select USE_NATIVE_RAMINIT
+	select POWER_LED_USES_GPIO8
 
 config BOARD_ASUS_P8Z77_M_PRO
 	select BOARD_ASUS_P8X7X_SERIES
@@ -39,6 +40,7 @@ config BOARD_ASUS_P8Z77_V_LX2
 	select REALTEK_8168_RESET
 	select SUPERIO_NUVOTON_NCT6779D
 	select USE_NATIVE_RAMINIT
+	select POWER_LED_USES_GPIO8
 
 config BOARD_ASUS_P8Z77_V
 	select BOARD_ASUS_P8X7X_SERIES
@@ -58,6 +60,11 @@ config BOARD_ASUS_P8Z77_M
 
 if BOARD_ASUS_P8X7X_SERIES
 
+config POWER_LED_USES_GPIO8
+	bool
+	help
+	  If power LED doesn't blink when entering S3 suspend, try setting this.
+
 config MAINBOARD_DIR
 	default "asus/p8x7x-series"
 

From 2ac0a7feeb532ca4f137ce305bbb83edb91c3126 Mon Sep 17 00:00:00 2001
From: Keith Hui <buurin@gmail.com>
Date: Thu, 28 Nov 2024 14:47:40 -0500
Subject: [PATCH 0527/3886] mb/asus/p8x7x-series: Blink power LED during
 suspend

Extends commit 57946ad8174a ("mb/asus/p8z77-m[_pro]: Blink power
LED during suspend") to the entire family.

Also, we don't need the 0x for Arg0; it can't go larger than 5.

Applied this patch and CB:82556 while developing a port for
P8Z77-V LE PLUS variant (which uses GPIO8 for power LED). Its
power LED does blink during suspend.

Change-Id: Ie30e5ef79a87a3dca6875b0a6e07ae99d0d79e6e
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82557
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
---
 src/mainboard/asus/p8x7x-series/acpi/platform.asl | 15 ++++++++-------
 1 file changed, 8 insertions(+), 7 deletions(-)

diff --git a/src/mainboard/asus/p8x7x-series/acpi/platform.asl b/src/mainboard/asus/p8x7x-series/acpi/platform.asl
index b16ced504c..b5c3fc333a 100644
--- a/src/mainboard/asus/p8x7x-series/acpi/platform.asl
+++ b/src/mainboard/asus/p8x7x-series/acpi/platform.asl
@@ -1,20 +1,21 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
+#if CONFIG(POWER_LED_USES_GPIO8)
+#define BLINK_POWER_LED GB08
+#else
+#define BLINK_POWER_LED GB27
+#endif
 
 Method(_PTS, 1)
 {
-#if (CONFIG(BOARD_ASUS_P8Z77_M) || CONFIG(BOARD_ASUS_P8Z77_M_PRO))
 	/* blink power LED if not turning off */
-	If (Arg0 != 0x05)
+	If (Arg0 != 5)
 	{
-	    GB27 = 1
+	    BLINK_POWER_LED = 1
 	}
-#endif
 }
 
 Method(_WAK, 1)
 {
-#if (CONFIG(BOARD_ASUS_P8Z77_M) || CONFIG(BOARD_ASUS_P8Z77_M_PRO))
-	GB27 = 0
-#endif
+	BLINK_POWER_LED = 0
 	Return(Package(){0, 0})
 }

From 692ed637ba3b36521ce9981ee89b1ea79971ddf7 Mon Sep 17 00:00:00 2001
From: Keith Hui <buurin@gmail.com>
Date: Fri, 17 Jan 2025 21:47:27 -0500
Subject: [PATCH 0528/3886] mb/asus/p8x7x-series: Add P8Z77-V LE PLUS variant

Based on a mix of existing P8x7x series boards, boardview, vendor
firmware dumps, and hardware testing.

Working:
- SeaBIOS 1.16.3 and edk2/mrchromebox/uefipayload_2501
- Serial port
- All USB2 & USB3 ports
- Z77 SATA ports
- Integrated graphics thru all ports with libgfxinit
- RTL8111F LAN (MAC address doesn't stick)
- Analog 7.1 audio out the back panel jacks
- Digital audio
- Front HDA audio panel
- PCIe x16 slot with nVidia 8800GT GPU
- PCIe x1 slots
- PCIe x4 slot with Intel Octane H10 1TB NVMe
- PCI slots
- Hardware monitoring and fan control
- S3 suspend

Untested:
- Hotplugging Z77 SATA ports
- EHCI debug

Not working:
- PS/2 mouse
- Wake on LAN
- Marvell SATA ports

Change-Id: Id9eef8b3426daecce0c95f56bfcd4caae2d52e50
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86172
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 .../mainboard/asus/p8z77-v_le_plus.md         | 260 ++++++++++++++++++
 Documentation/mainboard/index.md              |   1 +
 src/mainboard/asus/p8x7x-series/Kconfig       |  11 +
 src/mainboard/asus/p8x7x-series/Kconfig.name  |   3 +
 .../variants/p8z77-v_le_plus/board_info.txt   |   7 +
 .../variants/p8z77-v_le_plus/cmos.default     |  12 +
 .../variants/p8z77-v_le_plus/cmos.layout      | 102 +++++++
 .../variants/p8z77-v_le_plus/data.vbt         | Bin 0 -> 3902 bytes
 .../variants/p8z77-v_le_plus/early_init.c     | 126 +++++++++
 .../p8z77-v_le_plus/gma-mainboard.ads         |  19 ++
 .../variants/p8z77-v_le_plus/gpio.c           | 206 ++++++++++++++
 .../variants/p8z77-v_le_plus/hda_verb.c       | 154 +++++++++++
 .../variants/p8z77-v_le_plus/overridetree.cb  | 100 +++++++
 13 files changed, 1001 insertions(+)
 create mode 100644 Documentation/mainboard/asus/p8z77-v_le_plus.md
 create mode 100644 src/mainboard/asus/p8x7x-series/variants/p8z77-v_le_plus/board_info.txt
 create mode 100644 src/mainboard/asus/p8x7x-series/variants/p8z77-v_le_plus/cmos.default
 create mode 100644 src/mainboard/asus/p8x7x-series/variants/p8z77-v_le_plus/cmos.layout
 create mode 100644 src/mainboard/asus/p8x7x-series/variants/p8z77-v_le_plus/data.vbt
 create mode 100644 src/mainboard/asus/p8x7x-series/variants/p8z77-v_le_plus/early_init.c
 create mode 100644 src/mainboard/asus/p8x7x-series/variants/p8z77-v_le_plus/gma-mainboard.ads
 create mode 100644 src/mainboard/asus/p8x7x-series/variants/p8z77-v_le_plus/gpio.c
 create mode 100644 src/mainboard/asus/p8x7x-series/variants/p8z77-v_le_plus/hda_verb.c
 create mode 100644 src/mainboard/asus/p8x7x-series/variants/p8z77-v_le_plus/overridetree.cb

diff --git a/Documentation/mainboard/asus/p8z77-v_le_plus.md b/Documentation/mainboard/asus/p8z77-v_le_plus.md
new file mode 100644
index 0000000000..2664127a4e
--- /dev/null
+++ b/Documentation/mainboard/asus/p8z77-v_le_plus.md
@@ -0,0 +1,260 @@
+# ASUS P8Z77-V LE PLUS
+
+This page describes how to run coreboot on the [ASUS P8Z77-V LE PLUS].
+
+## Flashing coreboot
+
+```{eval-rst}
++---------------------+----------------+
+| Type                | Value          |
++=====================+================+
+| Socketed flash      | yes            |
++---------------------+----------------+
+| Model               | W25Q64FVA1Q    |
++---------------------+----------------+
+| Size                | 8 MiB          |
++---------------------+----------------+
+| Package             | DIP-8          |
++---------------------+----------------+
+| Write protection    | yes            |
++---------------------+----------------+
+| Dual BIOS feature   | no             |
++---------------------+----------------+
+| Internal flashing   | yes            |
++---------------------+----------------+
+```
+
+### How to flash
+
+The main SPI flash cannot be written because the vendor firmware disables BIOSWE
+and enables BLE/SMM_BWP flags in BIOS_CNTL for their latest BIOSes. An external
+programmer is required. You must flash standalone, flashing in-circuit doesn't
+work. The flash chip is socketed, so it's easy to remove and reflash.
+
+See page 2-2 of user's manual for flash chip location.
+
+### Extra preparations for changing PCIe slot configuration
+
+On vendor firmware, the black PCIEX16_3 slot can be configured as x2 or x4.
+If set for x4, PCIEX1_1 and PCIEX1_2 are disabled.
+
+Before flashing coreboot for the first time, decide how you want to use the PCIe slots.
+If you want to be able to choose between using the two PCIEX1 slots and the PCIEX16_3 slot at
+x4 bandwidth, you need to do some preparation, namely make two backups of the whole flash
+chip, specifically the flash descriptor under both configurations.
+
+Enter vendor UEFI setup and check the PCIEX16_3 (black) slot bandwidth setting. You'll back up
+under this setting first. Once one backup is made, come back and change the setting
+from x2 to x4 (or vice versa) and reboot once, then make the other backup.
+
+With PCIEX16_3 (black) slot bandwidth at x2, run these commands:
+```bash
+flashrom -p internal -r pciex163_x2.bin
+dd if=pciex163_x2.bin of=ifd-pciex163_x2.bin bs=4096 count=1
+```
+
+With PCIEX16_3 (black) slot bandwidth at x4, run these commands:
+```bash
+flashrom -p internal -r pciex163_x4.bin
+dd if=pciex163_x4.bin of=ifd-pciex163_x4.bin bs=4096 count=1
+```
+(`dd` needs not be run as root.)
+
+Save the shortened `ifd-pciex163_*.bin` files for when you want to change the configuration.
+Keep one of the full backups as well.
+
+See "PCIe config" section below for more details.
+
+## Working
+
+- Core i5-3570K and i7-3770K CPUs
+- Corsair CMZ16GX3M2A1600C10 2x8GB memory kit
+- SeaBIOS 1.16.3
+- edk2 mrchromebox fork uefipayload_2501
+- Kernel 6.12.7
+- All USB2 ports (mouse, keyboard)
+- All USB3 ports
+- Z77 SATA ports (WD Blue SA510, Liteon LH-20A1L)
+- nVidia 8800GT GPU in PCIEX16_1 slot running x16
+- PCI slots (Sound Blaster Live! Value)
+- RTL8111F LAN
+- CPU temperature sensors and hardware monitor
+  (see [below](#hardware-monitoring-and-fan-speed-control))
+- Integrated graphics with libgfxinit and VBT
+  (all ports tested and working)
+- Both PCIe x1 slots when properly configured
+  (see [How to flash](#how-to-flash) above and [PCIe config](#pcie-config);
+  Atheros 928x miniPCIe Wifi on adapter & MSI Herald-BE Wifi7 adapter)
+- PCIe x4 slot with Intel Octane H10 1TB NVMe at x2 mode
+- Serial port
+- PS/2 keyboard
+- Analog 7.1 audio out the 3.5mm jacks on rear panel
+- Front HDA audio panel
+- Digital audio out (Optical, internal SPDIF header, HDMI, DisplayPort)
+
+  Although a `spdif_dest` option is provided for feature parity with vendor firmware,
+  it doesn't seem to matter and digital audio out is available through all ports.
+  It does, however, change how the ports are presented to the OS.
+
+- S3 suspend from Linux
+
+## Known issues
+
+- RTL8111F here has no EEPROM for vital product data such as MAC address, which is also not
+  being properly programmed. You may need to fuse your MAC address with [rtnicpg] instead.
+- For 7.1 analog audio to work, at least the front channel (green jack) must be connected.
+
+## Untested
+
+- Hotplug of Z77 SATA ports
+- EHCI debugging
+
+## Not working
+
+- Wake-on-LAN
+- PS/2 mouse (requires a patch currently under review)
+- Asmedia USB 3.0 battery charging support (for USB 3 ports on the LAN stack)
+- USB Charger+ (When the bottom USB 3 port on the eSATA stack, also used for BIOS flashback,
+  remains powered while the rest of the system is off. Both features are controlled by the same
+  AI1314 controller.)
+- Marvell SATA ports are brought up in IDE mode, pata_marvell driver is loaded,
+  but are effectively unusable.
+
+## PCIe config
+See [Extra preparations](#extra-preparations-for-changing-pcie-slot-configuration) section above.
+
+Changing the PCIe slot configuration requires manipulating a PCH GPIO line and a soft strap in
+the flash chip's descriptor section, which is read-only at runtime. coreboot programs the GPIO
+to match the soft strap, but how it can update the soft strap itself is to be determined. Until
+then, to make this change you have to re-flash the descriptor yourself, with one of the two
+copies you previously saved per above:
+```bash
+flashrom -p internal --ifd -i fd -w ifd-pciex163_x2.bin
+```
+
+## Hardware monitoring and fan speed control
+
+Although all fan ports are 4-pin for PWM fans, only CPU_FAN has actual PWM control;
+all other fan speed control is by voltage only.
+
+Write 1 into `/sys/class/hwmon/hwmon1/pwm1_mode` to enable CHA_FAN1 control, otherwise it
+runs at full speed.
+
+`fan5`/`pwm5` is not implemented and should be ignored.
+
+These are the sensors.conf settings for this board:
+
+```
+label fan1 "CHA_FAN1"
+label fan2 "CPU_FAN"
+label fan3 "CHA_FAN2"
+label fan4 "CHA_FAN3"
+ignore fan5
+label in1 "+12V"
+label in4 "+5V"
+compute in1 @*12, @/12
+compute in4 @*5, @/5
+set temp1_type 4
+set temp2_type 4
+```
+
+## Extra onboard switches and LEDs
+
+- `BIOS_FLBK`:
+  Vendor firmware uses this button to facilitate a simple update mechanism
+  via a USB drive plugged into the bottom USB port of the USB/ESATA6G stack.
+  It connects to the proprietary AI1314 controller, along with `FLBK_LED`.
+
+- `MemOK!`:
+  OEM firmware uses this button for memory tuning related to overclocking.
+  It connects to pin 74 of super I/O.
+
+- `DRAM_LED` lights up when there is a memory problem or when vendor MemOK! feature is
+  operating. Connects to GP07 line of super I/O. coreboot lights it up during memory init
+  similar to vendor firmware.
+
+- `EPU`: When enabled, lights up `EPU_LED` and takes PCH GPIO44 low.
+- `TPU`: When enabled, lights up `TPU_LED` and takes PCH GPIO45 low.
+
+  `EPU` and `TPU` are cues to vendor firmware to enable two embedded controllers for
+  overclocking features. coreboot is not yet able to make use of these two signals.
+
+- `SB_PWR` lights up whenever board is receiving power. It's all hardware
+  and does not concern coreboot.
+
+- `DRCT` is an undocumented 2-pin header next to the front panel connector block. It
+  connects to both the power button circuit and Z77's intruder detection input. Shorting this
+  header triggers both. With coreboot it currently works the same as the power button.
+
+## Extra exposed GPIOs at `TB_HEADER`
+
+A number of GPIO lines are broken out to `TB_HEADER` to support the ThunderboltEX adapter,
+which never took off. Now they're yours to play with. Additional programming may be required such
+as enabling GPIO by I/O for maximum effect.
+
+This may be safely ignored for most normal uses.
+
+**Be careful not to apply more than 3.3v to these pins!** And do not touch the two pins
+labeled "NOT A GPIO".
+
+Pinout:
+```
+ +---+---+---+---+---+
+ | 2 | 4 | 5 | 7 | 9 |
+ +---+---+---+---+---+
+ | 1 | 3 |   | 6 | 8 |
+ +---+---+---+---+---+
+```
+
+```{eval-rst}
++-----+-----------------------+----------+--------+
+| Pin | Name                  | Source   | GPIO # |
++=====+=======================+==========+========+
+|  1  | S_DP_DDC_CLK_TO_TB    | **NOT A GPIO**    |
++-----+-----------------------+----------+--------+
+|  2  | TB_GPIO_6             | NCT6779D |   14   |
++-----+-----------------------+----------+--------+
+|  3  | S_DP_DDC_DATA_TO_TB   | **NOT A GPIO**    |
++-----+-----------------------+----------+--------+
+|  4  | TB_GPIO_7             | NCT6779D |   13   |
++-----+-----------------------+----------+--------+
+|  5  | TB_FWUPDATE           | NCT6779D |   11   |
++-----+-----------------------+----------+--------+
+|  6  | TB_DEV_HPD            | Z77      |    0   |
++-----+-----------------------+----------+--------+
+|  7  | TB_GO2SX              | NCT6779D |   17   |
++-----+-----------------------+----------+--------+
+|  8  | TB_GO2SX#_ACK         | NCT6779D |   16   |
++-----+-----------------------+----------+--------+
+|  9  | Not connected                             |
++-----+-------------------------------------------+
+```
+
+Pins 2, 4, 6, 8 have 1M ohm pulldowns.
+
+## Technology
+
+```{eval-rst}
++------------------+--------------------------------------------------+
+| Northbridge      | :doc:`../../northbridge/intel/sandybridge/index` |
++------------------+--------------------------------------------------+
+| Southbridge      | bd82x6x                                          |
++------------------+--------------------------------------------------+
+| CPU              | model_206ax                                      |
++------------------+--------------------------------------------------+
+| Super I/O        | Nuvoton NCT6779D                                 |
++------------------+--------------------------------------------------+
+| EC               | TPU (ENE KB3722), AI1314                         |
++------------------+--------------------------------------------------+
+| Coprocessor      | Intel Management Engine                          |
++------------------+--------------------------------------------------+
+```
+
+## Extra resources
+
+- [Flash chip datasheet][W25Q64FVA1Q]
+
+[ASUS P8Z77-V LE PLUS]: https://www.asus.com/supportonly/p8z77-v%20le%20plus/helpdesk_manual/
+[W25Q64FVA1Q]: https://www.winbond.com/resource-files/w25q64fv%20revs%2007182017.pdf
+[flashrom]: https://flashrom.org/Flashrom
+[rtnicpg]: https://github.com/redchenjs/rtnicpg
diff --git a/Documentation/mainboard/index.md b/Documentation/mainboard/index.md
index f2be295f1f..870f0c625c 100644
--- a/Documentation/mainboard/index.md
+++ b/Documentation/mainboard/index.md
@@ -53,6 +53,7 @@ P8H77-V <asus/p8h77-v.md>
 P8Z77-M <asus/p8z77-m.md>
 P8Z77-M Pro <asus/p8z77-m_pro.md>
 P8Z77-V <asus/p8z77-v.md>
+P8Z77-V LE PLUS <asus/p8z77-v_le_plus.md>
 wifigo_v1 <asus/wifigo_v1.md>
 ```
 
diff --git a/src/mainboard/asus/p8x7x-series/Kconfig b/src/mainboard/asus/p8x7x-series/Kconfig
index d555cc67a7..9dc227f8e1 100644
--- a/src/mainboard/asus/p8x7x-series/Kconfig
+++ b/src/mainboard/asus/p8x7x-series/Kconfig
@@ -58,6 +58,15 @@ config BOARD_ASUS_P8Z77_M
 	select SUPERIO_NUVOTON_NCT6779D
 	select SUPERIO_NUVOTON_COMMON_COM_A
 
+config BOARD_ASUS_P8Z77_V_LE_PLUS
+	select BOARD_ASUS_P8X7X_SERIES
+	select BOARD_ROMSIZE_KB_8192
+	select RT8168_SET_LED_MODE
+	select SUPERIO_NUVOTON_NCT6779D
+	select USE_NATIVE_RAMINIT
+	select POWER_LED_USES_GPIO8
+	select HAVE_SHARED_PS2_PORT
+
 if BOARD_ASUS_P8X7X_SERIES
 
 config POWER_LED_USES_GPIO8
@@ -75,6 +84,7 @@ config VARIANT_DIR
 	default "p8z77-v_lx2" if BOARD_ASUS_P8Z77_V_LX2
 	default "p8z77-v"     if BOARD_ASUS_P8Z77_V
 	default "p8z77-m"     if BOARD_ASUS_P8Z77_M
+	default "p8z77-v_le_plus" if BOARD_ASUS_P8Z77_V_LE_PLUS
 
 config MAINBOARD_PART_NUMBER
 	default "P8C WS"      if BOARD_ASUS_P8C_WS
@@ -83,6 +93,7 @@ config MAINBOARD_PART_NUMBER
 	default "P8Z77-V LX2" if BOARD_ASUS_P8Z77_V_LX2
 	default "P8Z77-V"     if BOARD_ASUS_P8Z77_V
 	default "P8Z77-M"     if BOARD_ASUS_P8Z77_M
+	default "P8Z77-V LE PLUS" if BOARD_ASUS_P8Z77_V_LE_PLUS
 
 config OVERRIDE_DEVICETREE
 	default "variants/\$(CONFIG_VARIANT_DIR)/overridetree.cb"
diff --git a/src/mainboard/asus/p8x7x-series/Kconfig.name b/src/mainboard/asus/p8x7x-series/Kconfig.name
index a5598caeed..c27e008f8c 100644
--- a/src/mainboard/asus/p8x7x-series/Kconfig.name
+++ b/src/mainboard/asus/p8x7x-series/Kconfig.name
@@ -17,3 +17,6 @@ config BOARD_ASUS_P8Z77_V
 
 config BOARD_ASUS_P8Z77_M
 	bool "P8Z77-M"
+
+config BOARD_ASUS_P8Z77_V_LE_PLUS
+	bool "P8Z77-V LE PLUS"
diff --git a/src/mainboard/asus/p8x7x-series/variants/p8z77-v_le_plus/board_info.txt b/src/mainboard/asus/p8x7x-series/variants/p8z77-v_le_plus/board_info.txt
new file mode 100644
index 0000000000..53bbee1644
--- /dev/null
+++ b/src/mainboard/asus/p8x7x-series/variants/p8z77-v_le_plus/board_info.txt
@@ -0,0 +1,7 @@
+Category: desktop
+Board URL: https://www.asus.com/supportonly/p8z77-v%20le%20plus/helpdesk_manual/
+ROM package: DIP-8
+ROM protocol: SPI
+ROM socketed: y
+Flashrom support: y
+Release year: 2012
diff --git a/src/mainboard/asus/p8x7x-series/variants/p8z77-v_le_plus/cmos.default b/src/mainboard/asus/p8x7x-series/variants/p8z77-v_le_plus/cmos.default
new file mode 100644
index 0000000000..ae789bb470
--- /dev/null
+++ b/src/mainboard/asus/p8x7x-series/variants/p8z77-v_le_plus/cmos.default
@@ -0,0 +1,12 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
+boot_option=Fallback
+gfx_uma_size=64M
+debug_level=Debug
+nmi=Disable
+power_on_after_fail=Disable
+sata_mode=AHCI
+gfx_uma_size=64M
+audio_panel_type=HDA
+spdif_dest=SPDIF_OUT
+pciex16_3_bandwidth=x2
diff --git a/src/mainboard/asus/p8x7x-series/variants/p8z77-v_le_plus/cmos.layout b/src/mainboard/asus/p8x7x-series/variants/p8z77-v_le_plus/cmos.layout
new file mode 100644
index 0000000000..07b2a8c0bb
--- /dev/null
+++ b/src/mainboard/asus/p8x7x-series/variants/p8z77-v_le_plus/cmos.layout
@@ -0,0 +1,102 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
+# -----------------------------------------------------------------
+entries
+
+# -----------------------------------------------------------------
+0	120	r	0	reserved_memory
+
+# -----------------------------------------------------------------
+# RTC_BOOT_BYTE (coreboot hardcoded)
+384	1	e	2	boot_option
+388	4	h	0	reboot_counter
+
+# -----------------------------------------------------------------
+# coreboot config options: console
+395	4	e	3	debug_level
+
+# coreboot config options: southbridge
+408	1	e	1	nmi
+
+409	2	e	4	power_on_after_fail
+411	2	e	5	sata_mode
+
+# coreboot config options: northbridge
+416	5	e	6	gfx_uma_size
+
+# coreboot config options: mainboard
+425	1	e	9	audio_panel_type
+426	1	e	10	spdif_dest
+427	1	e	11	pciex16_3_bandwidth
+# coreboot config options: check sums
+984	16	h	0	check_sum
+
+# -----------------------------------------------------------------
+
+enumerations
+#ID	value	text
+
+# Generic on/off enum
+1	0	Disable
+1	1	Enable
+
+# boot_option
+2	0	Fallback
+2	1	Normal
+
+# debug_level
+3	0	Emergency
+3	1	Alert
+3	2	Critical
+3	3	Error
+3	4	Warning
+3	5	Notice
+3	6	Info
+3	7	Debug
+3	8	Spew
+
+# power_on_after_fail
+4	0	Disable
+4	1	Enable
+4	2	Keep
+
+# sata_mode
+5	0	AHCI
+5	1	Compatible
+5	2	Legacy
+
+# gfx_uma_size (Intel IGP Video RAM size)
+6	0	32M
+6	1	64M
+6	2	96M
+6	3	128M
+6	4	160M
+6	5	192M
+6	6	224M
+6	7	256M
+6	8	288M
+6	9	320M
+6	10	352M
+6	11	384M
+6	12	416M
+6	13	448M
+6	14	480M
+6	15	512M
+6	16	1024M
+
+# audio_panel_type
+9     0     HDA
+9     1     AC97
+
+# spdif_dest
+10    0     SPDIF_OUT
+10    1     HDMI
+
+# pciex16_3_bandwidth
+11	0	x2
+11	1	x4
+
+# -----------------------------------------------------------------
+checksums
+
+checksum 392 423 984
diff --git a/src/mainboard/asus/p8x7x-series/variants/p8z77-v_le_plus/data.vbt b/src/mainboard/asus/p8x7x-series/variants/p8z77-v_le_plus/data.vbt
new file mode 100644
index 0000000000000000000000000000000000000000..a89353ded3945d0e5eccd39f79ef6ec9608e1e83
GIT binary patch
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diff --git a/src/mainboard/asus/p8x7x-series/variants/p8z77-v_le_plus/early_init.c b/src/mainboard/asus/p8x7x-series/variants/p8z77-v_le_plus/early_init.c
new file mode 100644
index 0000000000..024f8e9d81
--- /dev/null
+++ b/src/mainboard/asus/p8x7x-series/variants/p8z77-v_le_plus/early_init.c
@@ -0,0 +1,126 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <bootblock_common.h>
+#include <cf9_reset.h>
+#include <device/pnp_ops.h>
+#include <device/pci_ops.h>
+#include <device/pci.h>
+#include <superio/nuvoton/common/nuvoton.h>
+#include <superio/nuvoton/nct6779d/nct6779d.h>
+#include <southbridge/intel/common/rcba.h>
+#include <southbridge/intel/common/gpio.h>
+#include <southbridge/intel/bd82x6x/pch.h>
+#include <console/console.h>
+#include <option.h>
+
+#define GLOBAL_DEV PNP_DEV(0x2e, 0)
+#define SERIAL_DEV PNP_DEV(0x2e, NCT6779D_SP1)
+#define ACPI_DEV   PNP_DEV(0x2e, NCT6779D_ACPI)
+#define GPIO0_DEV  PNP_DEV(0x2e, NCT6779D_WDT1_GPIO01_V)
+
+enum pciex16_3_bandwidth {
+	PCIEX16_3_X2 = 0,
+	PCIEX16_3_X4 = 1
+};
+
+void mainboard_late_rcba_config(void)
+{
+	/* This is called after raminit. We turn off DRAM_LED here. */
+	nuvoton_pnp_enter_conf_state(GPIO0_DEV);
+	pnp_set_logical_device(GPIO0_DEV);
+	pnp_write_config(GPIO0_DEV, 0xe1, 0x80);
+	nuvoton_pnp_exit_conf_state(GPIO0_DEV);
+
+	DIR_ROUTE(D31IR, PIRQA, PIRQD, PIRQC, PIRQA);
+	DIR_ROUTE(D29IR, PIRQH, PIRQD, PIRQA, PIRQC);
+	DIR_ROUTE(D27IR, PIRQG, PIRQB, PIRQC, PIRQD);
+	DIR_ROUTE(D26IR, PIRQH, PIRQF, PIRQC, PIRQD);
+	DIR_ROUTE(D25IR, PIRQE, PIRQF, PIRQG, PIRQH);
+	DIR_ROUTE(D22IR, PIRQF, PIRQD, PIRQC, PIRQB);
+}
+
+void bootblock_mainboard_init(void)
+{
+	int gp46 = 0;
+
+	/*
+	 * PCHSTRP9[PCIEPCS1] soft strap (reflected here) tells us how PCIe lanes 1-4 are
+	 * configured.
+	 *
+	 * GPIO46 controls one ASM1440 switch that routes PCH PCIe lanes 3 & 4 as follows:
+	 * 0 = PCIEX1_1 and PCIEX1_2 respectively (pulled low on board)
+	 * 1 = PCIEX16_3
+	 */
+	u8 pciepcs1 = RCBA32(RPC) & 0x3;
+	/*
+	unsigned int pciex16_bandwidth = get_uint_option("pciex16_3_bandwidth", PCIEX16_3_X2);
+	u8 new_pciepcs1 = (pciex16_bandwidth == PCIEX16_3_X4) ? 3 : 1;
+
+	if (pciepcs1 != new_pciepcs1) {
+		printk(BIOS_INFO, "Updating PCHSTRP9[PCIEPCS1] to 0x%x... ", new_pciepcs1);
+		if (write_pchstrp9(new_pciepcs1)) {
+			printk(BIOS_INFO, "done.\n");
+			full_reset();
+		} else {
+		*/
+			/* Strap update failed.
+			 * If halting, blink PCH GPIO8 for power LED so that this condition
+			 * can be indicated by DRAM_LED lit and power LED blinking.
+			 * If not, need a way to let user know to restore
+			 * the flash descriptor with flashrom. System may be unstable.
+			 */
+			/*printk(BIOS_ERR, "PCH soft strap update failed!\n");
+		}
+	}
+	*/
+
+	switch (pciepcs1) {
+	case 1: /* 1 x2, 3/4 x1 */
+		break;
+	case 3: /* 1 x4 */
+		gp46 = 1;
+		break;
+	default:
+		printk(BIOS_ERR, "PCH PCIe lane configuration 0x%x is invalid!\n", pciepcs1);
+	}
+
+	/* Match GPIO to soft strap. */
+	set_gpio(46, gp46);
+}
+
+void bootblock_mainboard_early_init(void)
+{
+	nuvoton_pnp_enter_conf_state(GLOBAL_DEV);
+
+	/* Select SIO pin states */
+	pnp_write_config(GLOBAL_DEV, 0x1a, 0x02);
+	pnp_write_config(GLOBAL_DEV, 0x27, 0x10);
+	pnp_write_config(GLOBAL_DEV, 0x2a, 0x48);
+	pnp_write_config(GLOBAL_DEV, 0x2c, 0x00);
+
+	/* Power RAM in S3 */
+	pnp_set_logical_device(ACPI_DEV);
+	pnp_write_config(ACPI_DEV, 0xe4, 0x10);
+
+	/* Turn on DRAM_LED. If raminit dies, this would remain on and we know
+	 * we have a problem. We turn it off after raminit. */
+	pnp_set_logical_device(GPIO0_DEV);
+	pnp_write_config(GPIO0_DEV, 0x30, 0x02);
+	pnp_write_config(GPIO0_DEV, 0xe0, 0x7f);
+	pnp_write_config(GPIO0_DEV, 0xe1, 0x00);
+
+	nuvoton_pnp_exit_conf_state(GLOBAL_DEV);
+
+	/* Enable UART */
+	nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
+
+	/* Put PCIe root port 6 into subtractive decode. This should allow a POST card in
+	 * the PCI slot to receive POST codes via a connected ASM1083 bridge.
+	 *
+	 * TODO: Also needs to set up early PCI bridge.
+	 */
+	if (CONFIG(POST_DEVICE_PCI_PCIE)) {
+		pci_or_config32(PCI_DEV(0, 30, 0), 0x4c, 1 << 28); /* pci_bridge[BPC] |= SDE */
+		pci_write_config32(PCH_PCIE_DEV(5), 0xec, 1); /* pcie_rp6[PECR3] |= SDE */
+	}
+}
diff --git a/src/mainboard/asus/p8x7x-series/variants/p8z77-v_le_plus/gma-mainboard.ads b/src/mainboard/asus/p8x7x-series/variants/p8z77-v_le_plus/gma-mainboard.ads
new file mode 100644
index 0000000000..e6b0407446
--- /dev/null
+++ b/src/mainboard/asus/p8x7x-series/variants/p8z77-v_le_plus/gma-mainboard.ads
@@ -0,0 +1,19 @@
+-- SPDX-License-Identifier: GPL-2.0-or-later
+
+with HW.GFX.GMA;
+with HW.GFX.GMA.Display_Probing;
+
+use HW.GFX.GMA;
+use HW.GFX.GMA.Display_Probing;
+
+private package GMA.Mainboard is
+
+   ports : constant Port_List :=
+     (DP1,
+      HDMI1,
+      HDMI2,
+      HDMI3,
+      Analog,
+      others => Disabled);
+
+end GMA.Mainboard;
diff --git a/src/mainboard/asus/p8x7x-series/variants/p8z77-v_le_plus/gpio.c b/src/mainboard/asus/p8x7x-series/variants/p8z77-v_le_plus/gpio.c
new file mode 100644
index 0000000000..b7b6ab244e
--- /dev/null
+++ b/src/mainboard/asus/p8x7x-series/variants/p8z77-v_le_plus/gpio.c
@@ -0,0 +1,206 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <southbridge/intel/common/gpio.h>
+
+static const struct pch_gpio_set1 pch_gpio_set1_mode = {
+	.gpio0 = GPIO_MODE_GPIO,
+	.gpio1 = GPIO_MODE_GPIO, /* SMI# of ASM1042 USB3 */
+	.gpio2 = GPIO_MODE_GPIO,
+	.gpio3 = GPIO_MODE_GPIO,
+	.gpio4 = GPIO_MODE_GPIO,
+	.gpio5 = GPIO_MODE_GPIO,
+	.gpio6 = GPIO_MODE_GPIO,
+	.gpio7 = GPIO_MODE_GPIO, /* PCIEX16_3 card presence, active low */
+	.gpio8 = GPIO_MODE_GPIO, /* Power LED */
+	.gpio9 = GPIO_MODE_NATIVE,
+	.gpio10 = GPIO_MODE_NATIVE,
+	.gpio11 = GPIO_MODE_GPIO,
+	.gpio12 = GPIO_MODE_GPIO,
+	.gpio13 = GPIO_MODE_GPIO,
+	.gpio14 = GPIO_MODE_GPIO,
+	.gpio15 = GPIO_MODE_GPIO,
+	.gpio16 = GPIO_MODE_GPIO,
+	.gpio17 = GPIO_MODE_GPIO,
+	.gpio19 = GPIO_MODE_GPIO,
+	.gpio20 = GPIO_MODE_GPIO,
+	.gpio21 = GPIO_MODE_GPIO,
+	.gpio22 = GPIO_MODE_GPIO,
+	.gpio23 = GPIO_MODE_GPIO,
+	.gpio24 = GPIO_MODE_GPIO,
+	.gpio27 = GPIO_MODE_GPIO, /* ME_UNLOCK (Set high to unlock SPI descriptor) */
+	.gpio28 = GPIO_MODE_GPIO, /* S_IVR_EN */
+	.gpio29 = GPIO_MODE_GPIO, /* EC_SPI_WP# */
+	.gpio30 = GPIO_MODE_NATIVE,
+	.gpio31 = GPIO_MODE_GPIO, /* AI1314 BCS1 */
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_direction = {
+	.gpio0 = GPIO_DIR_INPUT,
+	.gpio1 = GPIO_DIR_INPUT,
+	.gpio2 = GPIO_DIR_INPUT,
+	.gpio3 = GPIO_DIR_INPUT,
+	.gpio4 = GPIO_DIR_INPUT,
+	.gpio5 = GPIO_DIR_INPUT,
+	.gpio6 = GPIO_DIR_INPUT,
+	.gpio7 = GPIO_DIR_INPUT,
+	.gpio8 = GPIO_DIR_OUTPUT,
+	.gpio11 = GPIO_DIR_INPUT,
+	.gpio12 = GPIO_DIR_INPUT,
+	.gpio13 = GPIO_DIR_INPUT,
+	.gpio14 = GPIO_DIR_INPUT,
+	.gpio15 = GPIO_DIR_INPUT,
+	.gpio16 = GPIO_DIR_INPUT,
+	.gpio17 = GPIO_DIR_INPUT,
+	.gpio19 = GPIO_DIR_INPUT,
+	.gpio20 = GPIO_DIR_INPUT,
+	.gpio21 = GPIO_DIR_INPUT,
+	.gpio22 = GPIO_DIR_INPUT,
+	.gpio23 = GPIO_DIR_INPUT,
+	.gpio24 = GPIO_DIR_INPUT,
+	.gpio27 = GPIO_DIR_INPUT,
+	.gpio28 = GPIO_DIR_OUTPUT,
+	.gpio29 = GPIO_DIR_OUTPUT,
+	.gpio31 = GPIO_DIR_OUTPUT,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_level = {
+	.gpio8 = GPIO_LEVEL_HIGH,
+	.gpio28 = GPIO_LEVEL_LOW,
+	.gpio29 = GPIO_LEVEL_HIGH,
+	.gpio31 = GPIO_LEVEL_LOW,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_reset = {
+	.gpio27 = GPIO_RESET_RSMRST
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_invert = {
+	.gpio1 = GPIO_INVERT,
+	.gpio11 = GPIO_INVERT,
+	.gpio13 = GPIO_INVERT,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_blink = {};
+
+static const struct pch_gpio_set2 pch_gpio_set2_mode = {
+	.gpio32 = GPIO_MODE_GPIO,
+	.gpio33 = GPIO_MODE_GPIO,
+	.gpio34 = GPIO_MODE_GPIO,
+	.gpio35 = GPIO_MODE_GPIO,
+	.gpio36 = GPIO_MODE_GPIO,
+	.gpio37 = GPIO_MODE_GPIO,
+	.gpio38 = GPIO_MODE_GPIO,
+	.gpio39 = GPIO_MODE_GPIO,
+	.gpio40 = GPIO_MODE_NATIVE,
+	.gpio41 = GPIO_MODE_NATIVE,
+	.gpio42 = GPIO_MODE_NATIVE,
+	.gpio43 = GPIO_MODE_NATIVE,
+	.gpio44 = GPIO_MODE_GPIO, /* EPU switch, active low */
+	.gpio45 = GPIO_MODE_GPIO, /* TPU switch, active low */
+	.gpio46 = GPIO_MODE_GPIO, /* QSWU1 (High = PCH PCIe lanes 3/4 goes to PCIEX16_3) */
+	.gpio48 = GPIO_MODE_GPIO,
+	.gpio49 = GPIO_MODE_GPIO,
+	.gpio50 = GPIO_MODE_GPIO,
+	.gpio51 = GPIO_MODE_GPIO,
+	.gpio52 = GPIO_MODE_GPIO,
+	.gpio53 = GPIO_MODE_GPIO,
+	.gpio54 = GPIO_MODE_GPIO,
+	.gpio55 = GPIO_MODE_GPIO,
+	.gpio57 = GPIO_MODE_GPIO, /* AI1314 BCS0 */
+	.gpio58 = GPIO_MODE_GPIO,
+	.gpio59 = GPIO_MODE_NATIVE,
+	.gpio60 = GPIO_MODE_GPIO,
+	.gpio61 = GPIO_MODE_GPIO,
+	.gpio62 = GPIO_MODE_GPIO,
+	.gpio63 = GPIO_MODE_GPIO,
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_direction = {
+	.gpio32 = GPIO_DIR_INPUT,
+	.gpio33 = GPIO_DIR_INPUT,
+	.gpio34 = GPIO_DIR_INPUT,
+	.gpio35 = GPIO_DIR_INPUT,
+	.gpio36 = GPIO_DIR_INPUT,
+	.gpio37 = GPIO_DIR_INPUT,
+	.gpio38 = GPIO_DIR_INPUT,
+	.gpio39 = GPIO_DIR_INPUT,
+	.gpio44 = GPIO_DIR_INPUT,
+	.gpio45 = GPIO_DIR_INPUT,
+	.gpio46 = GPIO_DIR_OUTPUT,
+	.gpio48 = GPIO_DIR_INPUT,
+	.gpio49 = GPIO_DIR_INPUT,
+	.gpio50 = GPIO_DIR_INPUT,
+	.gpio51 = GPIO_DIR_INPUT,
+	.gpio52 = GPIO_DIR_INPUT,
+	.gpio53 = GPIO_DIR_INPUT,
+	.gpio54 = GPIO_DIR_INPUT,
+	.gpio55 = GPIO_DIR_INPUT,
+	.gpio57 = GPIO_DIR_OUTPUT,
+	.gpio58 = GPIO_DIR_INPUT,
+	.gpio60 = GPIO_DIR_INPUT,
+	.gpio61 = GPIO_DIR_INPUT,
+	.gpio62 = GPIO_DIR_INPUT,
+	.gpio63 = GPIO_DIR_INPUT,
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_level = {
+	.gpio46 = GPIO_LEVEL_LOW, /* Needs to be set at runtime */
+	.gpio57 = GPIO_LEVEL_LOW,
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_reset = {
+	.gpio46 = GPIO_RESET_RSMRST,
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_mode = {
+	.gpio64 = GPIO_MODE_GPIO,
+	.gpio65 = GPIO_MODE_GPIO,
+	.gpio66 = GPIO_MODE_NATIVE,
+	.gpio67 = GPIO_MODE_NATIVE,
+	.gpio68 = GPIO_MODE_GPIO, /* RTL8111 ISOLATE# */
+	.gpio69 = GPIO_MODE_GPIO, /* A BIOS flashback signal */
+	.gpio70 = GPIO_MODE_GPIO,
+	.gpio71 = GPIO_MODE_GPIO,
+	.gpio72 = GPIO_MODE_GPIO, /* WP# of main SPI flash chip */
+	.gpio74 = GPIO_MODE_GPIO,
+	.gpio75 = GPIO_MODE_GPIO,
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_direction = {
+	.gpio64 = GPIO_DIR_INPUT,
+	.gpio65 = GPIO_DIR_INPUT,
+	.gpio68 = GPIO_DIR_OUTPUT,
+	.gpio69 = GPIO_DIR_INPUT,
+	.gpio70 = GPIO_DIR_INPUT,
+	.gpio71 = GPIO_DIR_INPUT,
+	.gpio72 = GPIO_DIR_OUTPUT,
+	.gpio74 = GPIO_DIR_INPUT,
+	.gpio75 = GPIO_DIR_INPUT,
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_level = {
+	.gpio68 = GPIO_LEVEL_HIGH,
+	.gpio72 = GPIO_LEVEL_HIGH,
+};
+
+const struct pch_gpio_map mainboard_gpio_map = {
+	.set1 = {
+		.mode		= &pch_gpio_set1_mode,
+		.direction	= &pch_gpio_set1_direction,
+		.level		= &pch_gpio_set1_level,
+		.blink		= &pch_gpio_set1_blink,
+		.invert		= &pch_gpio_set1_invert,
+		.reset		= &pch_gpio_set1_reset,
+	},
+	.set2 = {
+		.mode		= &pch_gpio_set2_mode,
+		.direction	= &pch_gpio_set2_direction,
+		.level		= &pch_gpio_set2_level,
+		.reset		= &pch_gpio_set2_reset,
+	},
+	.set3 = {
+		.mode		= &pch_gpio_set3_mode,
+		.direction	= &pch_gpio_set3_direction,
+		.level		= &pch_gpio_set3_level,
+	},
+};
diff --git a/src/mainboard/asus/p8x7x-series/variants/p8z77-v_le_plus/hda_verb.c b/src/mainboard/asus/p8x7x-series/variants/p8z77-v_le_plus/hda_verb.c
new file mode 100644
index 0000000000..5bfa977a98
--- /dev/null
+++ b/src/mainboard/asus/p8x7x-series/variants/p8z77-v_le_plus/hda_verb.c
@@ -0,0 +1,154 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <device/azalia_device.h>
+#include <option.h>
+
+/* Shorthands */
+#define AZALIA_PIN_REAR(dev, color, misc, association, sequence) \
+AZALIA_PIN_DESC(AZALIA_JACK, AZALIA_REAR, dev, AZALIA_STEREO_MONO_1_8, \
+		color, misc, association, sequence)
+#define AZALIA_PIN_FRONT(dev, color, misc, association, sequence) \
+AZALIA_PIN_DESC(AZALIA_JACK, AZALIA_FRONT, dev, AZALIA_STEREO_MONO_1_8, \
+		color, misc, association, sequence)
+
+const u32 cim_verb_data[] = {
+	0x10ec0889,	/* Realtek ALC889 */
+	0x1043841a,	/* Subsystem ID */
+	15,		/* Number of 4 dword sets */
+	AZALIA_SUBVENDOR(0, 0x1043841a),
+	AZALIA_PIN_CFG(0, 0x11, AZALIA_PIN_DESC(
+				AZALIA_INTEGRATED,
+				AZALIA_ATAPI,
+				AZALIA_SPDIF_OUT,
+				AZALIA_ATAPI_INTERNAL,
+				AZALIA_COLOR_UNKNOWN,
+				AZALIA_NO_JACK_PRESENCE_DETECT,
+				3, 0)), /* SPDIF out 2, 0x99430130 */
+	AZALIA_PIN_CFG(0, 0x12, AZALIA_PIN_CFG_NC(0)),
+	AZALIA_PIN_CFG(0, 0x14, AZALIA_PIN_REAR(
+				AZALIA_LINE_OUT,
+				AZALIA_GREEN,
+				0,
+				1, 0)), /* 0x01014010 */
+	AZALIA_PIN_CFG(0, 0x15, AZALIA_PIN_REAR(
+				AZALIA_LINE_OUT,
+				AZALIA_BLACK,
+				0,
+				1, 2)), /* 0x01011012 */
+	AZALIA_PIN_CFG(0, 0x16, AZALIA_PIN_REAR(
+				AZALIA_LINE_OUT,
+				AZALIA_ORANGE,
+				0,
+				1, 1)), /* 0x01016011 */
+	AZALIA_PIN_CFG(0, 0x17, AZALIA_PIN_REAR(
+				AZALIA_LINE_OUT,
+				AZALIA_GREY,
+				0,
+				1, 4)), /* 0x01012014 */
+	AZALIA_PIN_CFG(0, 0x18, AZALIA_PIN_REAR(
+				AZALIA_MIC_IN,
+				AZALIA_PINK,
+				8,
+				5, 0)), /* 0x01a19850 */
+	AZALIA_PIN_CFG(0, 0x19, AZALIA_PIN_FRONT(
+				AZALIA_MIC_IN,
+				AZALIA_PINK,
+				0xc,
+				6, 0)), /* 0x02a19c60 */
+	AZALIA_PIN_CFG(0, 0x1a, AZALIA_PIN_REAR(
+				AZALIA_LINE_IN,
+				AZALIA_BLUE,
+				0,
+				5, 15)), /* 0x0181305f */
+	AZALIA_PIN_CFG(0, 0x1b, AZALIA_PIN_FRONT(
+				AZALIA_HP_OUT,
+				AZALIA_GREEN,
+				0xc,
+				2, 0)), /* 0x02214c20),*/
+	AZALIA_PIN_CFG(0, 0x1c, AZALIA_PIN_CFG_NC(0)),
+	AZALIA_PIN_CFG(0, 0x1d, 0x4005e601), /* Beep */
+	AZALIA_PIN_CFG(0, 0x1e, AZALIA_PIN_DESC(
+				AZALIA_JACK,
+				AZALIA_REAR,
+				AZALIA_SPDIF_OUT,
+				AZALIA_OPTICAL,
+				AZALIA_ORANGE,
+				AZALIA_NO_JACK_PRESENCE_DETECT,
+				4, 0)), /* 0x01456140 */
+	AZALIA_PIN_CFG(0, 0x1f, AZALIA_PIN_CFG_NC(0)),
+
+	0x80862806,	/* Intel */
+	0x80860101,	/* Subsystem ID */
+	4,		/* Number of 4 dword sets */
+	AZALIA_SUBVENDOR(3, 0x80860101),
+	AZALIA_PIN_CFG(3, 0x05, 0x18560010),
+	AZALIA_PIN_CFG(3, 0x06, 0x58560020),
+	AZALIA_PIN_CFG(3, 0x07, 0x18560030),
+
+};
+
+const u32 pc_beep_verbs[0] = {};
+
+AZALIA_ARRAY_SIZES;
+
+enum e_spdif2_dest {
+	SPDIF2_SPDIF_OUT = 0,
+	SPDIF2_HDMI
+};
+
+enum e_aafp {
+	AAFP_HDA = 0,
+	AAFP_AC97
+};
+
+void mainboard_azalia_program_runtime_verbs(u8 *base, u32 viddid)
+{
+	/*
+	 * With vendor firmware, if audio front panel type is set as AC97, line out 2
+	 * (0x1b) and mic 2 (0x19) pins of ALC889 are configured differently.
+	 *
+	 * The differences are all in the "Misc" fields of configuration defaults (in byte 2)
+	 * as shown below. Datasheet did not offer details on what those bits
+	 * (listed as reserved in HDA spec) are, so we'll have to take their word for it.
+	 *
+	 * Pin  | 0x19 | 0x1b
+	 * -----+------+-----
+	 * HDA  | 1100 | 1100
+	 * AC97 | 1001 | 0001
+	 */
+	const u32 front_aafp_verbs[] = {
+		AZALIA_VERB_12B(0, 0x19, 0x71d, 0x99),
+		AZALIA_VERB_12B(0, 0x1b, 0x71d, 0x41)
+	};
+
+	/* If user chooses to have digital audio out 2 to go on the HDMI port,
+	 * reprogram this pin as such:
+	 *
+	 *	AZALIA_PIN_CFG(0, 0x11, AZALIA_PIN_DESC(
+	 *				AZALIA_JACK,
+	 *				AZALIA_DIGITAL_DISPLAY,
+	 *				AZALIA_DIGITAL_OTHER_OUT,
+	 *				AZALIA_OTHER_DIGITAL,
+	 *				AZALIA_BLACK,
+	 *				AZALIA_NO_JACK_PRESENCE_DETECT,
+	 *				3, 0))
+	 *
+	 * Coded this way because we don't need to reprogram byte 0.
+	 */
+	const u32 spdif_to_hdmi_verbs[] = {
+		AZALIA_VERB_12B(0, 0x11, 0x71f, 0x18),
+		AZALIA_VERB_12B(0, 0x11, 0x71e, 0x56),
+		AZALIA_VERB_12B(0, 0x11, 0x71d, 0x11)
+	};
+
+	if (viddid == 0x10ec0889) {
+		if (get_uint_option("audio_panel_type", AAFP_HDA) == AAFP_AC97) {
+			azalia_program_verb_table(base, front_aafp_verbs,
+			ARRAY_SIZE(front_aafp_verbs));
+		}
+		if (get_uint_option("spdif_dest", SPDIF2_SPDIF_OUT) == SPDIF2_HDMI) {
+			azalia_program_verb_table(base, spdif_to_hdmi_verbs,
+			ARRAY_SIZE(spdif_to_hdmi_verbs));
+		}
+	}
+}
diff --git a/src/mainboard/asus/p8x7x-series/variants/p8z77-v_le_plus/overridetree.cb b/src/mainboard/asus/p8x7x-series/variants/p8z77-v_le_plus/overridetree.cb
new file mode 100644
index 0000000000..66c8467935
--- /dev/null
+++ b/src/mainboard/asus/p8x7x-series/variants/p8z77-v_le_plus/overridetree.cb
@@ -0,0 +1,100 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
+chip northbridge/intel/sandybridge
+	device domain 0 on
+		subsystemid 0x1043 0x84ca inherit
+		device ref peg11 on	# PCIEX_16_2
+			smbios_slot_desc "SlotTypePciExpressGen3X8" "SlotLengthLong" "PCIEX16_2" "SlotDataBusWidth8X"
+		end
+		chip southbridge/intel/bd82x6x
+			register "usb_port_config" = "{
+				{ 1, 2, 0 },
+				{ 1, 8, 0 },
+				{ 1, 8, 1 },
+				{ 1, 8, 1 },
+				{ 1, 9, 2 },
+				{ 1, 9, 2 },
+				{ 1, 0xa53, 3 },
+				{ 1, 0xa53, 3 },
+				{ 1, 0xa53, 4 },
+				{ 1, 0xa53, 4 },
+				{ 1, 0xa53, 6 },
+				{ 1, 0xa53, 5 },
+				{ 1, 0xa53, 5 },
+				{ 1, 0xa53, 6 }
+			}"
+			register "gen1_dec" = "0x000c0291" # NCT6779 HWM
+			register "gen4_dec" = "0x0000ff29" # Could be for KB3722 EC
+
+			device ref pcie_rp1 on	# PCIEX_16_3 (electrical x2 or x4)
+				smbios_slot_desc "SlotTypePciExpressGen2X4" "SlotLengthLong" "PCIEX16_3" "SlotDataBusWidth4X"
+			end
+			device ref pcie_rp3 on
+				smbios_slot_desc "SlotTypePciExpressGen2X1" "SlotLengthShort" "PCIEX1_1" "SlotDataBusWidth1X"
+			end
+			device ref pcie_rp4 on
+				smbios_slot_desc "SlotTypePciExpressGen2X1" "SlotLengthShort" "PCIEX1_2" "SlotDataBusWidth1X"
+			end
+			device ref pcie_rp5 on		# RTL8111F LAN
+				chip drivers/net
+					register "customized_leds" = "0x482"
+					device pci 00.0 on
+						subsystemid 0x1043 0x8505
+					end
+				end
+			end
+			device ref pcie_rp6 on		# ASM1083 PCI bridge
+				subsystemid 0x1043 0x8489
+				smbios_slot_desc "SlotTypePci" "SlotLengthLong" "PCI1" "SlotDataBusWidth32Bit"
+			end
+			device ref pcie_rp7 on		# Marvell 88SE9120 ESATA6G
+				subsystemid 0x1043 0x83ba
+			end
+			device ref pcie_rp8 on		# ASM1042 USB3
+				subsystemid 0x1043 0x8488
+			end
+			device ref hda on
+				subsystemid 0x1043 0x841a
+			end
+			device ref lpc on
+				chip superio/nuvoton/nct6779d
+					device pnp 2e.1 off end		# Parallel
+					device pnp 2e.2 on		# UART A
+						io  0x60 = 0x3f8
+						irq 0x70 = 4
+					end
+					device pnp 2e.3 off end		# UART B, IR
+					device pnp 2e.5 on		# PS2 KBC
+						io  0x60 = 0x0060	# KBC1 base
+						io  0x62 = 0x0064	# KBC2 base
+						irq 0x70 = 1		# Keyboard IRQ
+						irq 0x72 = 12		# Mouse IRQ
+						# KBC 12Mhz/A20 speed/sw KBRST
+						drq 0xf0 = 0x82
+					end
+					device pnp 2e.6 off  end	# CIR
+					device pnp 2e.7 off  end	# GPIOs 6-8
+					device pnp 2e.8 off  end	# WDT1 GPIO 0-1
+					device pnp 2e.108 on end	# GPIO0
+					device pnp 2e.109 on end	# GPIO1
+					device pnp 2e.509 on end 	# GPIO5 all in
+					device pnp 2e.a on		# ACPI
+						drq 0xe7 = 0x11
+						drq 0xf2 = 0x5d		# Enable PME
+					end
+					device pnp 2e.b   on		# H/W Monitor, FP LED
+						io  0x60 = 0x290
+						io  0x62 = 0
+						irq 0x70 = 0
+						drq 0xe4 = 0xf9		# Use GP50/52/55
+					end
+					device pnp 2e.d off end		# WDT1
+					device pnp 2e.e off end		# CIR wake-up
+					device pnp 2e.f off end
+					device pnp 2e.14 on  end	# Port 80 UART
+					device pnp 2e.16 off end	# Deep sleep
+				end
+			end
+		end
+	end
+end

From e7f4a2c0d65917be5603b13b83a6d237093f40ae Mon Sep 17 00:00:00 2001
From: Keith Hui <buurin@gmail.com>
Date: Sun, 16 Jun 2024 22:55:29 -0400
Subject: [PATCH 0529/3886] mb/asus/p8x7x-series: Move Super I/O base port to
 Kconfig

By doing this the base port is now #defined as CONFIG_SUPERIO_PNP_BASE,
available to both C and ASL code, the latter will soon start to make
use of this as well. This will be gradually expanded to all boards using
superio/nuvoton/{nct5572d,nct6776,nct6779d,nct6791d}.

Change early_init.c of all variants to use this new #define.

Change-Id: I6e2851db68f4867be8fa4ef0d8bd8d1b9b8bf92a
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86635
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/asus/p8x7x-series/Kconfig                     | 4 ++++
 .../asus/p8x7x-series/variants/p8c_ws/early_init.c          | 6 +++---
 .../asus/p8x7x-series/variants/p8h77-v/early_init.c         | 6 +++---
 .../asus/p8x7x-series/variants/p8z77-m/early_init.c         | 4 ++--
 .../asus/p8x7x-series/variants/p8z77-m_pro/early_init.c     | 2 +-
 .../asus/p8x7x-series/variants/p8z77-v/early_init.c         | 6 +++---
 .../asus/p8x7x-series/variants/p8z77-v_lx2/early_init.c     | 6 +++---
 7 files changed, 19 insertions(+), 15 deletions(-)

diff --git a/src/mainboard/asus/p8x7x-series/Kconfig b/src/mainboard/asus/p8x7x-series/Kconfig
index 9dc227f8e1..e3e977f00e 100644
--- a/src/mainboard/asus/p8x7x-series/Kconfig
+++ b/src/mainboard/asus/p8x7x-series/Kconfig
@@ -104,4 +104,8 @@ config CMOS_DEFAULT_FILE
 config CMOS_LAYOUT_FILE
 	default "src/mainboard/\$(MAINBOARDDIR)/variants/\$(CONFIG_VARIANT_DIR)/cmos.layout"
 
+config SUPERIO_PNP_BASE
+	hex
+	default 0x2e
+
 endif
diff --git a/src/mainboard/asus/p8x7x-series/variants/p8c_ws/early_init.c b/src/mainboard/asus/p8x7x-series/variants/p8c_ws/early_init.c
index ad240c1616..f192e22f3c 100644
--- a/src/mainboard/asus/p8x7x-series/variants/p8c_ws/early_init.c
+++ b/src/mainboard/asus/p8x7x-series/variants/p8c_ws/early_init.c
@@ -5,9 +5,9 @@
 #include <superio/nuvoton/common/nuvoton.h>
 #include <superio/nuvoton/nct6776/nct6776.h>
 
-#define GLOBAL_DEV PNP_DEV(0x2e, 0)
-#define SERIAL_DEV PNP_DEV(0x2e, NCT6776_SP1)
-#define ACPI_DEV   PNP_DEV(0x2e, NCT6776_ACPI)
+#define GLOBAL_DEV PNP_DEV(CONFIG_SUPERIO_PNP_BASE, 0)
+#define SERIAL_DEV PNP_DEV(CONFIG_SUPERIO_PNP_BASE, NCT6776_SP1)
+#define ACPI_DEV   PNP_DEV(CONFIG_SUPERIO_PNP_BASE, NCT6776_ACPI)
 
 void bootblock_mainboard_early_init(void)
 {
diff --git a/src/mainboard/asus/p8x7x-series/variants/p8h77-v/early_init.c b/src/mainboard/asus/p8x7x-series/variants/p8h77-v/early_init.c
index 6d68c17ae1..a7f7e9f077 100644
--- a/src/mainboard/asus/p8x7x-series/variants/p8h77-v/early_init.c
+++ b/src/mainboard/asus/p8x7x-series/variants/p8h77-v/early_init.c
@@ -5,9 +5,9 @@
 #include <superio/nuvoton/common/nuvoton.h>
 #include <superio/nuvoton/nct6779d/nct6779d.h>
 
-#define GLOBAL_DEV PNP_DEV(0x2e, 0)
-#define SERIAL_DEV PNP_DEV(0x2e, NCT6779D_SP1)
-#define ACPI_DEV   PNP_DEV(0x2e, NCT6779D_ACPI)
+#define GLOBAL_DEV PNP_DEV(CONFIG_SUPERIO_PNP_BASE, 0)
+#define SERIAL_DEV PNP_DEV(CONFIG_SUPERIO_PNP_BASE, NCT6779D_SP1)
+#define ACPI_DEV   PNP_DEV(CONFIG_SUPERIO_PNP_BASE, NCT6779D_ACPI)
 
 void bootblock_mainboard_early_init(void)
 {
diff --git a/src/mainboard/asus/p8x7x-series/variants/p8z77-m/early_init.c b/src/mainboard/asus/p8x7x-series/variants/p8z77-m/early_init.c
index 9ae7e1d16d..76eba43020 100644
--- a/src/mainboard/asus/p8x7x-series/variants/p8z77-m/early_init.c
+++ b/src/mainboard/asus/p8x7x-series/variants/p8z77-m/early_init.c
@@ -10,8 +10,8 @@
 
 #include <option.h>
 
-#define SERIAL_DEV PNP_DEV(0x2e, NCT6779D_SP1)
-#define GPIO0_DEV  PNP_DEV(0x2e, NCT6779D_WDT1_GPIO01_V)
+#define SERIAL_DEV PNP_DEV(CONFIG_SUPERIO_PNP_BASE, NCT6779D_SP1)
+#define GPIO0_DEV  PNP_DEV(CONFIG_SUPERIO_PNP_BASE, NCT6779D_WDT1_GPIO01_V)
 
 void bootblock_mainboard_early_init(void)
 {
diff --git a/src/mainboard/asus/p8x7x-series/variants/p8z77-m_pro/early_init.c b/src/mainboard/asus/p8x7x-series/variants/p8z77-m_pro/early_init.c
index 40be9133dc..73a4c80628 100644
--- a/src/mainboard/asus/p8x7x-series/variants/p8z77-m_pro/early_init.c
+++ b/src/mainboard/asus/p8x7x-series/variants/p8z77-m_pro/early_init.c
@@ -11,7 +11,7 @@
 #include <northbridge/intel/sandybridge/raminit.h>
 #include <northbridge/intel/sandybridge/pei_data.h>
 
-#define SERIAL_DEV PNP_DEV(0x2e, NCT6779D_SP2)
+#define SERIAL_DEV PNP_DEV(CONFIG_SUPERIO_PNP_BASE, NCT6779D_SP2)
 
 void bootblock_mainboard_early_init(void)
 {
diff --git a/src/mainboard/asus/p8x7x-series/variants/p8z77-v/early_init.c b/src/mainboard/asus/p8x7x-series/variants/p8z77-v/early_init.c
index bf0ba6795f..f693fbcb18 100644
--- a/src/mainboard/asus/p8x7x-series/variants/p8z77-v/early_init.c
+++ b/src/mainboard/asus/p8x7x-series/variants/p8z77-v/early_init.c
@@ -5,9 +5,9 @@
 #include <superio/nuvoton/common/nuvoton.h>
 #include <superio/nuvoton/nct6779d/nct6779d.h>
 
-#define GLOBAL_DEV PNP_DEV(0x2e, 0)
-#define SERIAL_DEV PNP_DEV(0x2e, NCT6779D_SP1)
-#define ACPI_DEV   PNP_DEV(0x2e, NCT6779D_ACPI)
+#define GLOBAL_DEV PNP_DEV(CONFIG_SUPERIO_PNP_BASE, 0)
+#define SERIAL_DEV PNP_DEV(CONFIG_SUPERIO_PNP_BASE, NCT6779D_SP1)
+#define ACPI_DEV   PNP_DEV(CONFIG_SUPERIO_PNP_BASE, NCT6779D_ACPI)
 
 void bootblock_mainboard_early_init(void)
 {
diff --git a/src/mainboard/asus/p8x7x-series/variants/p8z77-v_lx2/early_init.c b/src/mainboard/asus/p8x7x-series/variants/p8z77-v_lx2/early_init.c
index 6d68c17ae1..a7f7e9f077 100644
--- a/src/mainboard/asus/p8x7x-series/variants/p8z77-v_lx2/early_init.c
+++ b/src/mainboard/asus/p8x7x-series/variants/p8z77-v_lx2/early_init.c
@@ -5,9 +5,9 @@
 #include <superio/nuvoton/common/nuvoton.h>
 #include <superio/nuvoton/nct6779d/nct6779d.h>
 
-#define GLOBAL_DEV PNP_DEV(0x2e, 0)
-#define SERIAL_DEV PNP_DEV(0x2e, NCT6779D_SP1)
-#define ACPI_DEV   PNP_DEV(0x2e, NCT6779D_ACPI)
+#define GLOBAL_DEV PNP_DEV(CONFIG_SUPERIO_PNP_BASE, 0)
+#define SERIAL_DEV PNP_DEV(CONFIG_SUPERIO_PNP_BASE, NCT6779D_SP1)
+#define ACPI_DEV   PNP_DEV(CONFIG_SUPERIO_PNP_BASE, NCT6779D_ACPI)
 
 void bootblock_mainboard_early_init(void)
 {

From 4c016e28f71728334a51e1fc94935e5db0073bab Mon Sep 17 00:00:00 2001
From: Keith Hui <buurin@gmail.com>
Date: Thu, 27 Feb 2025 23:58:19 -0500
Subject: [PATCH 0530/3886] mb/asus/p8z77-m: Move SIO ACPI device config to
 bootblock

ACPI S3 suspend has been failing on this mainboard for about 5 months
as of this writing. This move fixes the regression. The removal of
these three settings from devicetree also realized a small image
size reduction.

TEST=Now again able to enter S3 suspend and return to where I was.

Change-Id: I35189b7977c83b3a2666dded8267b9021f0ea3f3
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86636
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
---
 .../asus/p8x7x-series/variants/p8z77-m/early_init.c         | 6 ++++++
 .../asus/p8x7x-series/variants/p8z77-m/overridetree.cb      | 6 +-----
 2 files changed, 7 insertions(+), 5 deletions(-)

diff --git a/src/mainboard/asus/p8x7x-series/variants/p8z77-m/early_init.c b/src/mainboard/asus/p8x7x-series/variants/p8z77-m/early_init.c
index 76eba43020..7e4647c6e2 100644
--- a/src/mainboard/asus/p8x7x-series/variants/p8z77-m/early_init.c
+++ b/src/mainboard/asus/p8x7x-series/variants/p8z77-m/early_init.c
@@ -12,6 +12,7 @@
 
 #define SERIAL_DEV PNP_DEV(CONFIG_SUPERIO_PNP_BASE, NCT6779D_SP1)
 #define GPIO0_DEV  PNP_DEV(CONFIG_SUPERIO_PNP_BASE, NCT6779D_WDT1_GPIO01_V)
+#define ACPI_DEV   PNP_DEV(CONFIG_SUPERIO_PNP_BASE, NCT6779D_ACPI)
 
 void bootblock_mainboard_early_init(void)
 {
@@ -26,6 +27,11 @@ void bootblock_mainboard_early_init(void)
 	pnp_write_config(GPIO0_DEV, 0xe0, 0x7f);
 	pnp_write_config(GPIO0_DEV, 0xe1, 0x00);
 
+	pnp_set_logical_device(ACPI_DEV);
+	pnp_write_config(ACPI_DEV, 0xe4, 0x10); /* Enable 3VSBSW#, needed for S3 suspend */
+	pnp_write_config(ACPI_DEV, 0xe7, 0x11); /* HWM reset by LRESET#, 0.5s S3 delay */
+	pnp_write_config(ACPI_DEV, 0xf2, 0x5d); /* Enable RSTOUT[0-2]# and PME */
+
 	nuvoton_pnp_exit_conf_state(GPIO0_DEV);
 
 	/*
diff --git a/src/mainboard/asus/p8x7x-series/variants/p8z77-m/overridetree.cb b/src/mainboard/asus/p8x7x-series/variants/p8z77-m/overridetree.cb
index e84125b720..058ce7644b 100644
--- a/src/mainboard/asus/p8x7x-series/variants/p8z77-m/overridetree.cb
+++ b/src/mainboard/asus/p8x7x-series/variants/p8z77-m/overridetree.cb
@@ -56,11 +56,7 @@ chip northbridge/intel/sandybridge
 					device pnp 2e.108 on		# GPIO 0
 						drq 0xe1 = 0x80		# GP07 high turns DRAM_LED off
 					end
-					device pnp 2e.a on		# ACPI
-						drq 0xe4 = 0x10 	# Enable 3VSBSW#, needed for S3 suspend
-						drq 0xe7 = 0x11		# HWM reset by LRESET#, 0.5s S3 delay for compatibility
-						drq 0xf2 = 0x5d		# Enable RSTOUT[0-2]# and PME
-					end
+					device pnp 2e.a on end		# ACPI
 					device pnp 2e.b on		# HWM, front panel LED
 						io 0x60 = 0x290		# HWM address
 						io 0x62 = 0		# SB-TSI address (not used)

From c0c9fc30845dbdc16c10e8e50b5940e5e4251859 Mon Sep 17 00:00:00 2001
From: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com>
Date: Mon, 24 Mar 2025 14:55:26 +0900
Subject: [PATCH 0531/3886] mb/nissa/var/meliks: Choose active storage by using
 FW_CONFIG

Select UFS or eMMC as the active storage of meliks boards by using
`STORAGE` field in `FW_CONFIG`.

BUG=none
BRANCH=nissa
TEST=FW_NAME=meliks emerge-nissa coreboot

Change-Id: Ifcc917ad1231fa68ce4caf6f0d67fa75b16a3085
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86980
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 .../google/brya/variants/meliks/Makefile.mk   |  1 +
 .../google/brya/variants/meliks/fw_config.c   | 46 +++++++++++++++++++
 .../brya/variants/meliks/overridetree.cb      |  7 ++-
 3 files changed, 53 insertions(+), 1 deletion(-)
 create mode 100644 src/mainboard/google/brya/variants/meliks/fw_config.c

diff --git a/src/mainboard/google/brya/variants/meliks/Makefile.mk b/src/mainboard/google/brya/variants/meliks/Makefile.mk
index 227b163fc8..bc560b8f1d 100644
--- a/src/mainboard/google/brya/variants/meliks/Makefile.mk
+++ b/src/mainboard/google/brya/variants/meliks/Makefile.mk
@@ -3,4 +3,5 @@ bootblock-y += gpio.c
 
 romstage-y += memory.c
 
+ramstage-$(CONFIG_FW_CONFIG) += fw_config.c
 ramstage-y += gpio.c
diff --git a/src/mainboard/google/brya/variants/meliks/fw_config.c b/src/mainboard/google/brya/variants/meliks/fw_config.c
new file mode 100644
index 0000000000..c4e6a1b09f
--- /dev/null
+++ b/src/mainboard/google/brya/variants/meliks/fw_config.c
@@ -0,0 +1,46 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <baseboard/gpio.h>
+#include <baseboard/variants.h>
+#include <console/console.h>
+#include <fw_config.h>
+
+static const struct pad_config emmc_disable_pads[] = {
+	/* I7  : EMMC_CMD */
+	PAD_NC(GPP_I7, NONE),
+	/* I8  : EMMC_D0 */
+	PAD_NC(GPP_I8, NONE),
+	/* I9  : EMMC_D1 */
+	PAD_NC(GPP_I9, NONE),
+	/* I10 : EMMC_D2 */
+	PAD_NC(GPP_I10, NONE),
+	/* I11 : EMMC_D3 */
+	PAD_NC(GPP_I11, NONE),
+	/* I12 : EMMC_D4 */
+	PAD_NC(GPP_I12, NONE),
+	/* I13 : EMMC_D5 */
+	PAD_NC(GPP_I13, NONE),
+	/* I14 : EMMC_D6 */
+	PAD_NC(GPP_I14, NONE),
+	/* I15 : EMMC_D7 */
+	PAD_NC(GPP_I15, NONE),
+	/* I16 : EMMC_RCLK */
+	PAD_NC(GPP_I16, NONE),
+	/* I17 : EMMC_CLK */
+	PAD_NC(GPP_I17, NONE),
+	/* I18 : EMMC_RST_L */
+	PAD_NC(GPP_I18, NONE),
+};
+
+void fw_config_gpio_padbased_override(struct pad_config *padbased_table)
+{
+	// Check if FW_CONFIG is provisioned
+	if (!fw_config_is_provisioned())
+		return;
+
+	if (!fw_config_probe(FW_CONFIG(STORAGE, STORAGE_EMMC))) {
+		printk(BIOS_INFO, "Disable eMMC SSD GPIO pins.\n");
+		gpio_padbased_override(padbased_table, emmc_disable_pads,
+						ARRAY_SIZE(emmc_disable_pads));
+	}
+}
diff --git a/src/mainboard/google/brya/variants/meliks/overridetree.cb b/src/mainboard/google/brya/variants/meliks/overridetree.cb
index eefa40b001..f522ed3211 100644
--- a/src/mainboard/google/brya/variants/meliks/overridetree.cb
+++ b/src/mainboard/google/brya/variants/meliks/overridetree.cb
@@ -392,13 +392,18 @@ chip soc/intel/alderlake
 		end
 		device ref pcie_rp7 off end
 		device ref pcie_rp9 off end
+		device ref emmc on
+			probe STORAGE STORAGE_EMMC
+		end
 		device ref ish on
 			chip drivers/intel/ish
 				register "add_acpi_dma_property" = "true"
 				device generic 0 on end
 			end
 		end
-		device ref ufs on end
+		device ref ufs on
+			probe STORAGE STORAGE_UFS
+		end
 		device ref pch_espi on
 			chip ec/google/chromeec
 				use conn0 as mux_conn[0]

From a9391060168e6947ca1821c104ef46d26ba9168e Mon Sep 17 00:00:00 2001
From: Martin Roth <gaumless@gmail.com>
Date: Thu, 27 Mar 2025 11:18:53 -0600
Subject: [PATCH 0532/3886] Documentation: Add coreboot release 25.06 template

This adds the release notes template for the upcoming June release of
coreboot.

Change-Id: Ia8aa266973181be12620343eb58bb9ba8f0ccc79
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87030
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 .../releases/coreboot-25.06-relnotes.md       | 96 +++++++++++++++++++
 Documentation/releases/index.md               |  3 +-
 2 files changed, 98 insertions(+), 1 deletion(-)
 create mode 100644 Documentation/releases/coreboot-25.06-relnotes.md

diff --git a/Documentation/releases/coreboot-25.06-relnotes.md b/Documentation/releases/coreboot-25.06-relnotes.md
new file mode 100644
index 0000000000..585af8bcf2
--- /dev/null
+++ b/Documentation/releases/coreboot-25.06-relnotes.md
@@ -0,0 +1,96 @@
+Upcoming release - coreboot 25.06
+========================================================================
+
+The 25.06 release is scheduled for the end of June, 2025
+
+
+Update this document with changes that should be in the release notes.
+
+* Please use Markdown.
+* See the past few release notes for the general format.
+* The chip and board additions and removals will be updated right
+  before the release, so those do not need to be added.
+* Note that all changes before the release are done are marked upcoming.
+  A final version of the notes are done after the release.
+
+
+
+Significant or interesting changes
+----------------------------------
+
+* Add changes that need a full description here
+
+* This section should have full descriptions and can or should have
+  a link to the referenced commits.
+
+
+
+Additional coreboot changes
+---------------------------
+
+The following are changes across a number of patches, or changes worth
+noting, but not needing a full description.
+
+* Changes that only need a line or two of description go here.
+
+
+
+Changes to external resources
+-----------------------------
+
+### Toolchain updates
+
+
+
+### Git submodule pointers
+
+
+### External payloads
+
+
+
+Platform Updates
+----------------
+
+### Added mainboards:
+* To be filled in immediately before the release by the release team
+
+
+### Removed Mainboards
+* To be filled in immediately before the release by the release team
+
+
+### Updated SoCs
+* To be filled in immediately before the release by the release team
+
+
+
+Plans to move platform support to a branch
+------------------------------------------
+* To be filled in immediately before the release by the release team
+
+
+
+Statistics from the 24.12 to the 25.03 release
+--------------------------------------------
+* To be filled in immediately before the release by the release team
+
+
+
+Significant Known and Open Issues
+---------------------------------
+
+Issues from the coreboot bugtracker: <https://ticket.coreboot.org/>
+* To be filled in immediately before the release by the release team
+
+
+
+coreboot Links and Contact Information
+--------------------------------------
+
+* Main Web site: <https://www.coreboot.org>
+* Downloads: <https://coreboot.org/downloads.html>
+* Source control: <https://review.coreboot.org>
+* Documentation: <https://doc.coreboot.org>
+* Issue tracker: <https://ticket.coreboot.org/projects/coreboot>
+* Donations: <https://coreboot.org/donate.html>
diff --git a/Documentation/releases/index.md b/Documentation/releases/index.md
index 0fe44e0f6d..aec897eaf5 100644
--- a/Documentation/releases/index.md
+++ b/Documentation/releases/index.md
@@ -6,7 +6,7 @@ Please add to the release notes as changes are added:
 ```{toctree}
 :maxdepth: 1
 
-25.03  - March 2025 <coreboot-25.03-relnotes.md>
+25.06  - June 2025 <coreboot-25.06-relnotes.md>
 ```
 
 The [checklist] contains instructions to ensure that a release covers all
@@ -22,6 +22,7 @@ important is taken care of.
 ```{toctree}
 :maxdepth: 1
 
+25.03  - March 2025 <coreboot-25.03-relnotes.md>
 24.12  - December 2024 <coreboot-24.12-relnotes.md>
 24.08  - August 2024 <coreboot-24.08-relnotes.md>
 24.05  - May 2024 <coreboot-24.05-relnotes.md>

From 28d4a35fd0263b1b2eec53f39e7005a829a1c2e1 Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Wed, 26 Mar 2025 20:56:00 +0000
Subject: [PATCH 0533/3886] mb/starlabs/starbook/mtl: Set PsysPmax to auto

Set PsysPmax to 0, which is auto instead of the FSP default
which is 21.5W (0xac).

Change-Id: Ia2503077067fa719a09f9877d7fe0bedf2a662f1
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87006
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
---
 src/mainboard/starlabs/starbook/variants/mtl/romstage.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/src/mainboard/starlabs/starbook/variants/mtl/romstage.c b/src/mainboard/starlabs/starbook/variants/mtl/romstage.c
index acd384e62c..6f553a2885 100644
--- a/src/mainboard/starlabs/starbook/variants/mtl/romstage.c
+++ b/src/mainboard/starlabs/starbook/variants/mtl/romstage.c
@@ -37,4 +37,5 @@ void mainboard_memory_init_params(FSPM_UPD *mupd)
 		mupd->FspmConfig.PcieRpEnableMask &= ~(1 << 8);
 
 	mupd->FspmConfig.PchHdaSubSystemIds = 0x70381e50;
+	mupd->FspmConfig.PsysPmax = 0;
 };

From 1467e5fbd3160aae5a82e678e24b5785e76b6d25 Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Wed, 26 Mar 2025 21:09:13 +0000
Subject: [PATCH 0534/3886] mb/starlabs/starbook/mtl: Don't configure GPIOs to
 IOSTANDBY_IGNORE

This is just simply incorrect, as these signals are used to
pull various devices into low power states during S3.

Change-Id: Ic2950cc43fd17dda4205964c851b09cfd86d90d9
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87013
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
---
 .../starlabs/starbook/variants/mtl/gpio.c        | 16 ++++++++--------
 1 file changed, 8 insertions(+), 8 deletions(-)

diff --git a/src/mainboard/starlabs/starbook/variants/mtl/gpio.c b/src/mainboard/starlabs/starbook/variants/mtl/gpio.c
index 8619f24c25..d1b915ab9e 100644
--- a/src/mainboard/starlabs/starbook/variants/mtl/gpio.c
+++ b/src/mainboard/starlabs/starbook/variants/mtl/gpio.c
@@ -29,17 +29,17 @@ const struct pad_config gpio_table[] = {
 	 * End:		GPP_V22
 	 */
 	/* V00:	PM_BATLOW_N			*/
-	PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_V00, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_V00, NONE, DEEP, NF1),
 	/* V01:	CHG_ACOK			*/
-	PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_V01, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_V01, NONE, DEEP, NF1),
 	/* V02:	PCIE_WAKE_LAN			*/
 	PAD_NC(GPP_V02, NONE),
 	/* V03:	EC_PWRBTN_N			*/
-	PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_V03, UP_20K, DEEP, NF1),
+	PAD_CFG_NF(GPP_V03, UP_20K, DEEP, NF1),
 	/* V04:	PM_SLP_S3_N			*/
-	PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_V04, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_V04, NONE, DEEP, NF1),
 	/* V05:	SLP S4#				*/
-	PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_V05, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_V05, NONE, DEEP, NF1),
 	/* V06:	GPD_6_SLP_A_N			*/
 	PAD_NC(GPP_V06, NONE),
 	/* V07:					*/
@@ -97,9 +97,9 @@ const struct pad_config gpio_table[] = {
 	 *		WEAK INTERNAL PD 20K	*/
 	PAD_CFG_GPO(GPP_C05, 0, PLTRST),
 	/* C06:	SML1_CLK_USBC_PD_N		*/
-	PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_C06, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_C06, NONE, DEEP, NF1),
 	/* C07:	SML1_DATA_USBC_PD_N		*/
-	PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_C07, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_C07, NONE, DEEP, NF1),
 	/* C08:	SML1ALERT			*/
 	PAD_CFG_NF(GPP_C08, NONE, DEEP, NF1),
 	/* C09:					*/
@@ -182,7 +182,7 @@ const struct pad_config gpio_table[] = {
 	/* A20:	M.2_CPU_SSD_RESET_N		*/
 	PAD_CFG_GPO(GPP_A20, 1, PLTRST),
 	/* A21:	I2C_PMC_PD_INT_N		*/
-	PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_A21, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_A21, NONE, DEEP, NF1),
 	/* A22:					*/
 	PAD_NC(GPP_A22, NONE),
 	/* A23:					*/

From cdd60238e433ac30b38d9975b1a81b173307e4ae Mon Sep 17 00:00:00 2001
From: Maximilian Brune <maximilian.brune@9elements.com>
Date: Sun, 16 Mar 2025 23:08:07 +0100
Subject: [PATCH 0535/3886] Makefile: Add build/3rdparty as an exception for
 project_filelist.txt

The ctags tool (called by ctags-project target) currently complains
about not finding certain files:
```
ctags: Warning: cannot open input file "bl31/aarch64/bl31_entrypoint.S" : No such file or directory
ctags: Warning: cannot open input file "bl31/aarch64/crash_reporting.S" : No such file or directory
ctags: Warning: cannot open input file "bl31/aarch64/runtime_exceptions.S" : No such file or directory
ctags: Warning: cannot open input file "bl31/bl31.ld.S" : No such file or directory
ctags: Warning: cannot open input file "bl31/bl31_context_mgmt.c" : No such file or directory
ctags: Warning: cannot open input file "bl31/bl31_main.c" : No such file or directory
ctags: Warning: cannot open input file "bl31/bl31_traps.c" : No such file or directory
ctags: Warning: cannot open input file "bl31/interrupt_mgmt.c" : No such file or directory
ctags: Warning: cannot open input file "common/aarch64/debug.S" : No such file or directory
ctags: Warning: cannot open input file "common/bl_common.c" : No such file or directory
ctags: Warning: cannot open input file "common/fdt_fixup.c" : No such file or directory
...
```

The project_filelist.txt generation includes the compiler
generated "*.d" files, except for files found in build/util. Most file
paths in these "*.d" files are file paths relative to the root
directory of coreboot. Some projects though are compiled separately from
coreboot (e.g. payload, vboot, util). Some of these (e.g. util, vboot)
are also put into the build directory of coreboot and relative file
paths are relative to these projects instead of coreboot. This has the
uncanning side effect that the ctags Makefile target can't find these
files, since they are not relative to the coreboot root directory.

This patch excludes the build/3rdparty directory from those files, since
they contain 'separately' compiled projects like
3rdparty/arm-trusted-firmware.

Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: I18d0377e327530d9ef9382c324a305d156c5c681
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86868
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
---
 Makefile | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/Makefile b/Makefile
index 49c19cbc39..24b7c9624b 100644
--- a/Makefile
+++ b/Makefile
@@ -473,7 +473,7 @@ $(obj)/project_filelist.txt:
 		echo "*** Error: Project must be built before generating file list ***"; \
 		exit 1; \
 	fi
-	find $(obj) -path "$(obj)/util" -prune -o -path "$(obj)/external" -prune -o -name "*.d" -exec cat {} \; | \
+	find $(obj) -path "$(obj)/util" -prune -o -path "$(obj)/external" -prune -o -path "$(obj)/3rdparty" -prune -o -name "*.d" -exec cat {} \; | \
 	  sed "s|$(top)/||" | sed 's/[:\\]/ /g' | sed 's/ /\n/g' | sort | uniq | \
 	  grep -v '\.o$$' > $(obj)/project_filelist.txt
 

From 2c623c17fbbc1a68531ab6349d99c708f532357f Mon Sep 17 00:00:00 2001
From: Mac Chiang <mac.chiang@intel.com>
Date: Thu, 27 Mar 2025 17:40:06 +0800
Subject: [PATCH 0536/3886] mb/google/fatcat/var/francka: Add
 audio_disable_pins

disable audio-related pins when the CBI FW_Config is not defined.

BUG=b:392007428
TEST=emerge-fatcat coreboot

Signed-off-by: Mac Chiang <mac.chiang@intel.com>
Change-Id: I278106df53635adf2bb9f2eb787231724ad4b372
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87023
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jayvik Desai <jayvik@google.com>
Reviewed-by: Pranava Y N <pranavayn@google.com>
---
 .../fatcat/variants/francka/fw_config.c       | 22 ++++++++++++++++++-
 1 file changed, 21 insertions(+), 1 deletion(-)

diff --git a/src/mainboard/google/fatcat/variants/francka/fw_config.c b/src/mainboard/google/fatcat/variants/francka/fw_config.c
index b087e27df6..91aa20083c 100644
--- a/src/mainboard/google/fatcat/variants/francka/fw_config.c
+++ b/src/mainboard/google/fatcat/variants/francka/fw_config.c
@@ -43,6 +43,23 @@ static const struct pad_config hda_enable_pads[] = {
 	PAD_NC(GPP_S05, NONE),
 };
 
+static const struct pad_config audio_disable_pads[] = {
+	PAD_NC(GPP_D09, NONE),
+	PAD_NC(GPP_D10, NONE),
+	PAD_NC(GPP_D11, NONE),
+	PAD_NC(GPP_D12, NONE),
+	PAD_NC(GPP_D13, NONE),
+	PAD_NC(GPP_D16, NONE),
+	PAD_NC(GPP_S00, NONE),
+	PAD_NC(GPP_S01, NONE),
+	PAD_NC(GPP_S02, NONE),
+	PAD_NC(GPP_S03, NONE),
+	PAD_NC(GPP_S04, NONE),
+	PAD_NC(GPP_S05, NONE),
+	PAD_NC(GPP_S06, NONE),
+	PAD_NC(GPP_S07, NONE),
+};
+
 /*
  * WWAN: power sequence requires three stages:
  * step 1: 3.3V power, FCP# (Full Card Power), RST#, and PERST# off
@@ -123,8 +140,11 @@ void fw_config_gpio_padbased_override(struct pad_config *padbased_table)
 		return;
 	}
 
-	if (fw_config_probe(FW_CONFIG(AUDIO, AUDIO_ALC256M_CG_HDA)))
+	if (fw_config_probe(FW_CONFIG(AUDIO, AUDIO_ALC256M_CG_HDA))) {
 		GPIO_PADBASED_OVERRIDE(padbased_table, hda_enable_pads);
+	} else {
+		GPIO_PADBASED_OVERRIDE(padbased_table, audio_disable_pads);
+	}
 
 	if (fw_config_probe(FW_CONFIG(WWAN, WWAN_PRESENT))) {
 		GPIO_PADBASED_OVERRIDE(padbased_table, wwan_pwr_seq3_pads);

From dcd07b37d53ddac2708cf8519b78c010e7891559 Mon Sep 17 00:00:00 2001
From: Maximilian Brune <maximilian.brune@9elements.com>
Date: Mon, 17 Mar 2025 02:23:23 +0100
Subject: [PATCH 0537/3886] mb/emulation/qemu-aarch64/include: Update ECAM
 comment

Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: I5864cb742ba8e7be54f67c234766cd8a5272f8e2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86872
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
---
 .../emulation/qemu-aarch64/include/mainboard/addressmap.h    | 5 +++--
 src/mainboard/emulation/qemu-aarch64/mainboard.c             | 2 +-
 2 files changed, 4 insertions(+), 3 deletions(-)

diff --git a/src/mainboard/emulation/qemu-aarch64/include/mainboard/addressmap.h b/src/mainboard/emulation/qemu-aarch64/include/mainboard/addressmap.h
index 70acac8519..f3ca0e1d39 100644
--- a/src/mainboard/emulation/qemu-aarch64/include/mainboard/addressmap.h
+++ b/src/mainboard/emulation/qemu-aarch64/include/mainboard/addressmap.h
@@ -41,7 +41,8 @@
  * base_memmap entries (VIRT_HIGH_GIC_REDIST2 index is greater than the last
  * index of base_memmap).
  */
-#define VIRT_PCIE_ECAM_BASE 0x4010000000 /* The one in lower memory does not seem to work */
+#define VIRT_PCIE_LOW_ECAM_BASE    0x3f000000 /* only used if highmem-ecam=off (QEMU cmdline) */
+#define VIRT_PCIE_HIGH_ECAM_BASE 0x4010000000 /* only used if highmem-ecam=on  (default) */
 #define VIRT_PCIE_ECAM_SIZE (256 * MiB)
-#define VIRT_PCIE_HIGH_MMIO_BASE 0x8000000000ULL
+#define VIRT_PCIE_HIGH_MMIO_BASE  0x8000000000ULL
 #define VIRT_PCIE_HIGH_MMIO_LIMIT 0xffffffffffULL
diff --git a/src/mainboard/emulation/qemu-aarch64/mainboard.c b/src/mainboard/emulation/qemu-aarch64/mainboard.c
index 2701072d66..ac6b46d4fb 100644
--- a/src/mainboard/emulation/qemu-aarch64/mainboard.c
+++ b/src/mainboard/emulation/qemu-aarch64/mainboard.c
@@ -41,7 +41,7 @@ static void qemu_aarch64_domain_read_resources(struct device *dev)
 	res->limit = VIRT_PCIE_HIGH_MMIO_LIMIT;
 	res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED;
 
-	mmio_range(dev, index++, VIRT_PCIE_ECAM_BASE, VIRT_PCIE_ECAM_SIZE);
+	mmio_range(dev, index++, VIRT_PCIE_HIGH_ECAM_BASE, VIRT_PCIE_ECAM_SIZE);
 
 	ram_from_to(dev, index++, (uintptr_t)_dram, cbmem_top());
 }

From c444d166f3b7c0593be4bbd901b72c3bf3d7fc0e Mon Sep 17 00:00:00 2001
From: Maximilian Brune <maximilian.brune@9elements.com>
Date: Wed, 26 Feb 2025 17:19:03 +0100
Subject: [PATCH 0538/3886] include/endian.h: Add 'always aligned access'
 support

RISC-V doesn't support unaligned access, so check for that before
decoding and encoding. It is not perfectly performant, but still much
better then invoking the misaligned exception handler every time there
is a misaligned access. We can't modify our whole codebase to always do
aligned access, because it is neither feasible in long term nor is fair
to add that performance penalty onto other architectures that do support
unaligned access. So this is the next best thing.

On architectures that do support unaligned access the compiler will just
optimize the RISCV_ENV part out and should result in the exact same
binary.

tested: identical binary on QEMU-aarch64 and QEMU-q35.

Change-Id: I4dfccfdc2b302dd30b7ce5a29520c86add13169d
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86609
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
---
 src/include/endian.h | 28 ++++++++++++++++++++++++----
 1 file changed, 24 insertions(+), 4 deletions(-)

diff --git a/src/include/endian.h b/src/include/endian.h
index 552ce0025e..5cdcb2db54 100644
--- a/src/include/endian.h
+++ b/src/include/endian.h
@@ -5,6 +5,7 @@
 
 #include <arch/byteorder.h>
 #include <stdint.h>
+#include <string.h>
 #include <swab.h>
 
 #if defined(__LITTLE_ENDIAN)
@@ -67,12 +68,22 @@
 #define clrsetbits_le16(addr, clear, set) __clrsetbits(le, 16, addr, clear, set)
 #define clrsetbits_be16(addr, clear, set) __clrsetbits(be, 16, addr, clear, set)
 
-/* be16dec/be32dec/be64dec/le16dec/le32dec/le64dec family of functions. */
+/*
+ * be16dec/be32dec/be64dec/le16dec/le32dec/le64dec family of functions.
+ * RISC-V doesn't support misaligned access so decode it byte by byte.
+ */
 #define DEFINE_ENDIAN_DEC(endian, width) \
 	static inline uint##width##_t endian##width##dec(const void *p) \
 	{ \
-		return endian##width##_to_cpu(*(uint##width##_t *)p); \
+		if (ENV_RISCV) { \
+			uint##width##_t val; \
+			memcpy(&val, p, sizeof(val)); \
+			return endian##width##_to_cpu(val); \
+		} else { \
+			return endian##width##_to_cpu(*(uint##width##_t *)p); \
+		} \
 	}
+
 DEFINE_ENDIAN_DEC(be, 16)
 DEFINE_ENDIAN_DEC(be, 32)
 DEFINE_ENDIAN_DEC(be, 64)
@@ -80,12 +91,21 @@ DEFINE_ENDIAN_DEC(le, 16)
 DEFINE_ENDIAN_DEC(le, 32)
 DEFINE_ENDIAN_DEC(le, 64)
 
-/* be16enc/be32enc/be64enc/le16enc/le32enc/le64enc family of functions. */
+/*
+ * be16enc/be32enc/be64enc/le16enc/le32enc/le64enc family of functions.
+ * RISC-V doesn't support misaligned access so encode it byte by byte.
+ */
 #define DEFINE_ENDIAN_ENC(endian, width) \
 	static inline void endian##width##enc(void *p, uint##width##_t u) \
 	{ \
-		*(uint##width##_t *)p = cpu_to_##endian##width(u); \
+		if (ENV_RISCV) { \
+			uint##width##_t val = cpu_to_##endian##width(u); \
+			memcpy(p, &val, sizeof(val)); \
+		} else { \
+			*(uint##width##_t *)p = cpu_to_##endian##width(u); \
+		} \
 	}
+
 DEFINE_ENDIAN_ENC(be, 16)
 DEFINE_ENDIAN_ENC(be, 32)
 DEFINE_ENDIAN_ENC(be, 64)

From 38f5f7c48024d9fca4b6bbd88914423c34da709c Mon Sep 17 00:00:00 2001
From: Martin Roth <gaumless@gmail.com>
Date: Fri, 28 Mar 2025 15:18:50 -0600
Subject: [PATCH 0539/3886] Docs: Update 25.03 release notes

These are the release notes for the 25.03 release.

We will update again after the release is done with the final statistics
and information.

Change-Id: I4a3894fd617e95b8014c3cf1afe6472994e3fb16
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87042
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
---
 .../releases/coreboot-25.03-relnotes.md       | 321 ++++++++++++++++--
 1 file changed, 285 insertions(+), 36 deletions(-)

diff --git a/Documentation/releases/coreboot-25.03-relnotes.md b/Documentation/releases/coreboot-25.03-relnotes.md
index 4b579fe084..125437b395 100644
--- a/Documentation/releases/coreboot-25.03-relnotes.md
+++ b/Documentation/releases/coreboot-25.03-relnotes.md
@@ -1,37 +1,172 @@
 Upcoming release - coreboot 25.03
 ========================================================================
 
-The 25.03 release is scheduled for the end of March, 2025
+The coreboot project is pleased to announce the release of coreboot
+25.03, marking another milestone in our ongoing work to delivering
+open-source firmware. This release brings important improvements to
+display handling, USB debugging capabilities, and CPU topology
+management, along with various other enhancements that further improve
+the reliability and performance of coreboot across supported platforms.
 
-
-Update this document with changes that should be in the release notes.
-
-* Please use Markdown.
-* See the past few release notes for the general format.
-* The chip and board additions and removals will be updated right
-  before the release, so those do not need to be added.
-* Note that all changes before the release are done are marked upcoming.
-  A final version of the notes are done after the release.
+We extend our sincere thanks to all contributors who have made this
+release possible. Your expertise and collaborative efforts continue to
+propel the coreboot project forward. As always, we value the
+participation of everyone in the community, from long-time developers to
+those new to the project. The next coreboot release, 25.06, is scheduled
+for the end of June 2025.
 
 
 
 Significant or interesting changes
 ----------------------------------
 
-* Add changes that need a full description here
+### drivers/intel/fsp2_0: Enable panel-orientation aware bitmap rotation
 
-* This section should have full descriptions and can or should have
-  a link to the referenced commits.
+Implement logo bitmap rotation within fsp_convert_bmp_to_gop_blt() to
+support devices with portrait-oriented displays. The rotation is driven
+by the panel framebuffer orientation, allowing the logo to be displayed
+correctly regardless of physical panel orientation.
+
+This resolves issues where the logo was displayed incorrectly on
+portrait-oriented displays.
+
+Additionally, discard the display orientation change if the LID is
+closed aka built-in display is not active. This will ensure that display
+orientation is proper when extended display is attached w/o any display
+rotation.
+
+
+### util/find_usbdebug: Fix lsusb -t parsing for usbutils v016 and newer
+
+Commit e24294ff9ade ("lsusb -t: print ports and buses and devices with
+same width") [1] in the usbutils repository changed the format of the
+lsusb -t output, breaking the find_usbdebug.sh script. This commit is
+present in usbutils version 016 and later.
+
+Use the output of lsusb -V to set the parsing patterns based on the
+version in order to maintain compatibility with older versions of
+usbutils. A simple integer comparison of the version number is used for
+this, which will not work with versions older than v001 as those use a
+0.nn version number format. However, since v001 was released in late
+2010, it is probably safe to assume that no one will be using a version
+of usbutils older than that. Usbutils v016 was released in late 2023 so
+there could still conceivably be systems using older versions, such as
+Ubuntu 22.04 LTS which is on v014.
+
+[1] https://github.com/gregkh/usbutils/commit/e24294ff9ade6dafcd1909763e888d97b377c841
+
+
+### cpu/x86/topology: Fix FSP-S crash caused by shared core ID
+
+This resolves a crash issue observed on Meteor Lake and introduced by
+commit 70bdd2e1fad9fe89835aab240ed4b41a02f15078 ("cpu/x86/topology:
+Simplify CPU topology initialization"). This commit simplifies the code
+and provides more detailed CPU topology information by generalizing the
+use of the Extended Topology Enumeration Leaves 0x1f. As a result, the
+coreboot APIC core_id field does not provide the fully detailed path
+information.
+
+It turns out that the topology core identifier is used by the coreboot
+MP service mp_get_processor_info() implementation. But the MP Service
+EFI_CPU_PHYSICAL_LOCATION data structure only captures information about
+the package, core, and thread. The core identifier returned to the MP
+service caller must incorporate the full hierarchical path (die group,
+die, module, tile, module and core).
+
+This commit adds a new field to the cpu topology structure to represent
+the core ID within the package.
+
+For reference, here is that signature of the crash:
+
+   LAPIC 0x40 in X2APIC mode.
+   CPU Index 2 - APIC 64 Unexpected Exception:13 @ 10:69f3d1e4 - Halting
+   Code: 0 eflags: 00010046 cr2: 00000000
+   eax: 00000001 ebx: 69f313e8 ecx: 0000004e edx: 00000000
+   edi: 69f38018 esi: 00000029 ebp: 69aeee0c esp: 69aeedc0
+   [...]
+
+The crash occurred when FSP attempted to lock the Protected
+Processor Inventory Number Enable Control MSR (IA32_PPIN_CTL
+0x4e).
+
+   69f3d1d3:	8b 43 f4            	mov	-0xc(%ebx),%eax
+   69f3d1d6:	89 4d c4            	mov	%ecx,-0x3c(%ebp)
+   69f3d1d9:	89 45 dc            	mov	%eax,-0x24(%ebp)
+   69f3d1dc:	8b 55 c4            	mov	-0x3c(%ebp),%edx
+   69f3d1df:	8b 45 c0            	mov	-0x40(%ebp),%eax
+   69f3d1e2:	8b 4d dc            	mov	-0x24(%ebp),%ecx
+   69f3d1e5:	0f 30               	wrmsr
+   69f3d1e7:	e9 ee fd ff ff      	jmp	0xfffffe39
+
+FSP experiences issues due to attempting to lock the same register
+multiple times for a single core. This is caused by an inconsistency in
+the processor information data structure, where multiple cores share the
+same identifier. This is not permitted and triggers a General Protection
+Fault Exception.
+
+
+### {drivers, lib}: Move low-battery user notification logic outside FSP
+
+This patch refactors low-battery user notification logic (Kconfig, APIs
+to check if low-battery rendering is required, low-battery shutdown is
+required) outside FSP driver code to ensure in future non-FSP platforms
+might still be able to leverage this feature/logics to render the
+low-battery indicator icon during boot.
+
+Specifically, it:
+
+- Moves Kconfig options related to low-battery notifications from
+  drivers/intel/fsp to lib/
+- Relocates the low-battery check and shutdown APIs drivers/intel/fsp
+  to bootsplash.h
+* Adjusts the vendor driver to utilize the new APIs for low-battery
+  rendering decisions.
+* Drop the unwanted header file "fsp/api.h" from bmp_logo.c
+
+This change avoids tight coupling of low-battery functionality to FSP,
+promoting code reusability across platforms.
+
+
+### soc/intel/cannonlake: Use common ACPI code for SRAM and HECI
+
+Use the newly-created ACPI devices in common/acpi, and adjust the SoC
+ACPI name for the CSE/HECI device to match.
+
+
+### lib: Introduce early power off support Kconfig option
+
+This commit introduces the `HAVE_EARLY_POWEROFF_SUPPORT` Kconfig option
+and the `platform_do_early_poweroff()` API.
+
+The Kconfig option enables platform-specific early power off support,
+which is often required on Intel platforms. The corresponding API allows
+platforms to implement the necessary hardware operations for early power
+off, typically before memory initialization.
 
 
 
 Additional coreboot changes
 ---------------------------
 
-The following are changes across a number of patches, or changes worth
-noting, but not needing a full description.
-
-* Changes that only need a line or two of description go here.
+* Numerous changes to Haswell open source ram init
+* Numerous additions to intelp2m tool
+* Enhanced power management and thermal control across multiple platforms
+* Improved USB Type-C and Thunderbolt support
+* Added support for early power off and low battery detection
+* Enhanced display and graphics support across multiple platforms
+* Improved memory initialization and training
+* Added support for various new memory parts and configurations
+* Enhanced ACPI support and device handling
+* Improved security features and TPM support
+* Enhanced EC (Embedded Controller) support across platforms
+* Added support for various new touch panels and input devices
+* Refactored and improved code organization across multiple subsystems
+* Enhanced build system and toolchain support
+* Improved documentation and testing infrastructure
+* Added support for RISC-V architecture improvements
+* Enhanced debugging and logging capabilities
+* Improved error handling and recovery mechanisms
+* Added 7500 MT/s support for DDR5
 
 
 
@@ -40,12 +175,17 @@ Changes to external resources
 
 ### Toolchain updates
 
+* Update CMake from 3.30.2 to 3.31.3
+* Update ACPICA from 20230628 to 20241212
 
 
 ### Git submodule pointers
 
-
-### External payloads
+* arm-trusted-firmware: Update from commit id 15e5c6c91d to e5a1f4abee (608 commits)
+* blobs: Update from commit id 14f8fcc1b4 to a0726508b8 (10 commits)
+* fsp: Update from commit id 851f7105d8 to 86c9111639 (30 commits)
+* intel-microcode: Update from commit id 8ac9378a84 to 8a62de41c0 (1 commits)
+* vboot: Update from commit id f1f70f46dc to 3f94e2c7ed (49 commits)
 
 
 
@@ -53,35 +193,143 @@ Platform Updates
 ----------------
 
 ### Added mainboards:
-* To be filled in immediately before the release by the release team
-
-
-### Removed Mainboards
-* To be filled in immediately before the release by the release team
-
+* AMD Crater for Renoir SoC
+* ASROCK Z87 Extreme3
+* ASROCK Z87 Extreme4
+* ASROCK Z87M Extreme4
+* ASROCK Z87 Pro4
+* ASUS P8H67-I DELUXE
+* Google Dirks
+* Google Guren
+* Google Meliks
+* Google Moxie
+* Google Ocelot
+* Google Pujjoniru
+* Google Quandiso2
+* Google Wyrdeer
+* HP Pro 3400 Series
+* Intel Ptlrvp
+* Lenovo ThinkCentre M900
+* NovaCustom V540TU (14")
+* NovaCustom V560TU (16")
+* StarLabs StarLite Mk V Smart Battery (N200)
+* StarLabs StarBook Mk VII (165H)
+* StarLabs StarBook Mk VII (N200)
 
 ### Updated SoCs
-* To be filled in immediately before the release by the release team
-
-
-
-Plans to move platform support to a branch
-------------------------------------------
-* To be filled in immediately before the release by the release team
+* Added src/soc/xilinx/zynq7000
 
 
 
 Statistics from the 24.12 to the 25.03 release
---------------------------------------------
-* To be filled in immediately before the release by the release team
+----------------------------------------------
+
+* Total Commits: 992
+* Average Commits per day: 10.09
+* Total lines added: 87471
+* Average lines added per commit: 88.18
+* Number of patches adding more than 100 lines: 95
+* Average lines added per small commit: 40.50
+* Total lines removed: 22845
+* Average lines removed per commit: 23.03
+* Total difference between added and removed: 64626
+* Total authors: 129
+* New authors: 28
 
 
 
 Significant Known and Open Issues
 ---------------------------------
 
-Issues from the coreboot bugtracker: <https://ticket.coreboot.org/>
-* To be filled in immediately before the release by the release team
+### coreboot-wide or architecture-wide issues
+
++-----+-----------------------------------------------------------------+
+| #   | Subject                                                         |
++=====+=================================================================+
+| 519 | make gconfig - could not find glade file                        |
++-----+-----------------------------------------------------------------+
+| 518 | make xconfig - g++: fatal error: no input files                 |
++-----+-----------------------------------------------------------------+
+
+
+### Payload-specific issues
+
++-----+-----------------------------------------------------------------+
+| #   | Subject                                                         |
++=====+=================================================================+
+| 577 |  SeaBIOS/EDK2 Windows 10 BSOD "UNSUPPORTED PROCESSOR"           |
++-----+-----------------------------------------------------------------+
+| 552 |  X201 not booting with edk2 payload                             |
++-----+-----------------------------------------------------------------+
+| 549 | SeaBIOS Windows 10/11 BSOD "ACPI BIOS ERROR" (Thinkpad W530)    |
++-----+-----------------------------------------------------------------+
+| 499 | edk2 boot fails with RESOURCE_ALLOCATION_TOP_DOWN enabled       |
++-----+-----------------------------------------------------------------+
+| 496 | Missing malloc check in libpayload                              |
++-----+-----------------------------------------------------------------+
+| 484 | No USB keyboard support with secondary payloads                 |
++-----+-----------------------------------------------------------------+
+| 414 | X9SAE-V: No USB keyboard init on SeaBIOS using Radeon RX 6800XT |
++-----+-----------------------------------------------------------------+
+
+
+### Platform-specific issues
+
++-----+-----------------------------------------------------------------+
+| #   | Subject                                                         |
++=====+=================================================================+
+| 579 | MAC address set by coreboot to RTL8111F does not persist        |
++-----+-----------------------------------------------------------------+
+| 565 | Wifi card not recognized on Lenovo M700 tiny                    |
++-----+-----------------------------------------------------------------+
+| 563 | tty doesn't show on external display using edk2 on W530         |
++-----+-----------------------------------------------------------------+
+| 548 | Lenovo X201 Fails To Recognize Upgraded WiFi Card               |
++-----+-----------------------------------------------------------------+
+| 538 | x230: Dock Causes Internal Display to "Permanently" Malfunction |
++-----+-----------------------------------------------------------------+
+| 535 | T420: Power light stays off after reboot                        |
++-----+-----------------------------------------------------------------+
+| 528 | Building qemu-i440fx with CONFIG_CBFS_VERIFICATION fails        |
++-----+-----------------------------------------------------------------+
+| 524 | X2APIC Options cause Linux to crash on emulation/qemu-i440fx    |
++-----+-----------------------------------------------------------------+
+| 517 | lenovo x230 boot stuck with connected external monitor          |
++-----+-----------------------------------------------------------------+
+| 509 | SD Card hotplug not working on Apollo Lake                      |
++-----+-----------------------------------------------------------------+
+| 506 | APL/GML don't boot OS when CPU microcode included "from tree"   |
++-----+-----------------------------------------------------------------+
+| 505 | Harcuvar CRB - 15 of 16 cores present in the operating system   |
++-----+-----------------------------------------------------------------+
+| 499 | T440p - EDK2 fails with RESOURCE_ALLOCATION_TOP_DOWN enabled    |
++-----+-----------------------------------------------------------------+
+| 495 | Stoney Chromebooks not booting PSPSecureOS                      |
++-----+-----------------------------------------------------------------+
+| 478 | X200 booting Linux takes a long time with TSC                   |
++-----+-----------------------------------------------------------------+
+| 474 | X200s crashes after graphic init with 8GB RAM                   |
++-----+-----------------------------------------------------------------+
+| 457 | Haswell (t440p): CAR mem region conflicts with CBFS_SIZE > 8mb  |
++-----+-----------------------------------------------------------------+
+| 453 | Intel HDMI / DP Audio not present in Windows after libgfxinit   |
++-----+-----------------------------------------------------------------+
+| 449 | ThinkPad T440p fail to start, continuous beeping & LED blinking |
++-----+-----------------------------------------------------------------+
+| 448 | Thinkpad T440P ACPI Battery Value Issues                        |
++-----+-----------------------------------------------------------------+
+| 446 | Optiplex 9010 No Post                                           |
++-----+-----------------------------------------------------------------+
+| 439 | Lenovo X201 Turbo Boost not working (stuck on 2,4GHz)           |
++-----+-----------------------------------------------------------------+
+| 427 | x200: Two battery charging issues                               |
++-----+-----------------------------------------------------------------+
+| 412 | x230 reboots on suspend                                         |
++-----+-----------------------------------------------------------------+
+| 393 | T500 restarts rather than waking up from suspend                |
++-----+-----------------------------------------------------------------+
+| 350 | I225 PCIe device not detected on Harcuvar                       |
++-----+-----------------------------------------------------------------+
 
 
 
@@ -94,3 +342,4 @@ coreboot Links and Contact Information
 * Documentation: <https://doc.coreboot.org>
 * Issue tracker: <https://ticket.coreboot.org/projects/coreboot>
 * Donations: <https://coreboot.org/donate.html>
+

From 51130ebc646b4a91f0a6cd42fa9ba046a8f8bf43 Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Sat, 29 Mar 2025 20:13:28 +0000
Subject: [PATCH 0540/3886] mb/starlabs/starbook/mtl: Add the option to enable
 the VPU

Enable the VPU, and add a CFR option to enable or disable it.

Change-Id: I747d85c6764e5affcc202e063abe7ec786d04e39
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87046
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
---
 src/mainboard/starlabs/starbook/cfr.c                | 12 ++++++++++++
 .../starlabs/starbook/variants/mtl/devicetree.cb     |  1 +
 .../starlabs/starbook/variants/mtl/devtree.c         |  5 +++++
 3 files changed, 18 insertions(+)

diff --git a/src/mainboard/starlabs/starbook/cfr.c b/src/mainboard/starlabs/starbook/cfr.c
index 1e08ba1c12..ac34906656 100644
--- a/src/mainboard/starlabs/starbook/cfr.c
+++ b/src/mainboard/starlabs/starbook/cfr.c
@@ -185,6 +185,15 @@ static const struct sm_object thunderbolt = SM_DECLARE_BOOL({
 });
 #endif
 
+#if CONFIG(SOC_INTEL_METEORLAKE)
+static const struct sm_object vpu = SM_DECLARE_BOOL({
+	.opt_name	= "vpu",
+	.ui_name	= "VPU",
+	.ui_helptext	= "Enable or disable VPU",
+	.default_value	= true,
+});
+#endif
+
 static const struct sm_object webcam = SM_DECLARE_BOOL({
 	.opt_name	= "webcam",
 	.ui_name	= "Webcam",
@@ -266,6 +275,9 @@ static struct sm_obj_form devices = {
 		#if CONFIG(DRIVERS_INTEL_USB4_RETIMER)
 		&thunderbolt,
 		#endif
+		#if CONFIG(SOC_INTEL_METEORLAKE)
+		&vpu,
+		#endif
 		&webcam,
 		&wireless,
 		NULL
diff --git a/src/mainboard/starlabs/starbook/variants/mtl/devicetree.cb b/src/mainboard/starlabs/starbook/variants/mtl/devicetree.cb
index 43bcd0fbae..9cd7831814 100644
--- a/src/mainboard/starlabs/starbook/variants/mtl/devicetree.cb
+++ b/src/mainboard/starlabs/starbook/variants/mtl/devicetree.cb
@@ -171,6 +171,7 @@ chip soc/intel/meteorlake
 				device i2c 2c on end
 			end
 		end
+		device ref vpu on end
 		device ref ioe_shared_sram	on  end
 		device ref pmc_shared_sram	on  end
 		device ref pcie_rp9	on				# WiFi
diff --git a/src/mainboard/starlabs/starbook/variants/mtl/devtree.c b/src/mainboard/starlabs/starbook/variants/mtl/devtree.c
index c329bacffa..69406c7e78 100644
--- a/src/mainboard/starlabs/starbook/variants/mtl/devtree.c
+++ b/src/mainboard/starlabs/starbook/variants/mtl/devtree.c
@@ -20,6 +20,7 @@ void devtree_update(void)
 		&cfg->power_limits_config[MTL_P_682_482_CORE];
 
 	struct device *gna_dev = pcidev_on_root(0x08, 0);
+	struct device *vpu_dev = pcidev_on_root(0x0b, 0);
 
 	uint8_t performance_scale = 100;
 
@@ -63,4 +64,8 @@ void devtree_update(void)
 	/* Enable/Disable GNA based on CMOS settings */
 	if (get_uint_option("gna", 0) == 0)
 		gna_dev->enabled = 0;
+
+	/* Enable/Disable VPU based on CMOS settings */
+	if (get_uint_option("vpu", 0) == 0)
+		vpu_dev->enabled = 0;
 }

From 5c0340349ecb26948bf64d6e784de3d8c86e1ef6 Mon Sep 17 00:00:00 2001
From: Jeremy Compostella <jeremy.compostella@intel.com>
Date: Fri, 21 Mar 2025 15:51:32 -0700
Subject: [PATCH 0541/3886] mb/google/fatcat: Rationalize Wi-Fi and Bluetooth
 combinations

We aim to support only two Wi-Fi and Bluetooth combinations:
- CNVi Wi-Fi paired with CNVi Bluetooth
- Discrete Wi-Fi paired with USB Bluetooth

The CNVi core settings are configured at runtime based on the firmware
configuration for Fatcat and Felino variants. Since Francka only
supports CNVi configuration, settings are enforced in the override
device tree.

Change-Id: Ida95d1898d24898880de567db7c0ac8ac053eeaa
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85662
Reviewed-by: Ben Kao <ben.kao@intel.com>
Reviewed-by: Jayvik Desai <jayvik@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
---
 .../google/fatcat/variants/fatcat/overridetree.cb  | 14 ++++++++++++--
 .../google/fatcat/variants/felino/Makefile.mk      |  1 +
 .../google/fatcat/variants/felino/overridetree.cb  | 13 +++++++++++--
 .../google/fatcat/variants/felino/variant.c        | 13 +++++++++++++
 .../google/fatcat/variants/francka/overridetree.cb | 14 ++++++--------
 5 files changed, 43 insertions(+), 12 deletions(-)
 create mode 100644 src/mainboard/google/fatcat/variants/felino/variant.c

diff --git a/src/mainboard/google/fatcat/variants/fatcat/overridetree.cb b/src/mainboard/google/fatcat/variants/fatcat/overridetree.cb
index bc0b9e26a3..741b5a46c8 100644
--- a/src/mainboard/google/fatcat/variants/fatcat/overridetree.cb
+++ b/src/mainboard/google/fatcat/variants/fatcat/overridetree.cb
@@ -77,7 +77,7 @@ chip soc/intel/pantherlake
 	register "usb2_ports[3]" = "USB2_PORT_TYPE_C(OC_SKIP)" # USB2_C3
 	register "usb2_ports[4]" = "USB2_PORT_MID(OC0)" # Type-A Port A0
 	register "usb2_ports[5]" = "USB2_PORT_MID(OC0)" # Type-A Port A1 / WWAN with rework
-	register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # CNVi BT or discrete BT
+	register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # Discrete Bluetooth
 
 	register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)" # USB3.2 x1 Type-A Con #1
 	register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC0)" # USB3.2 x1 Type-A Con #2 / M.2 WWAN with rework
@@ -444,7 +444,10 @@ chip soc/intel/pantherlake
 						register "desc" = ""USB2 Bluetooth""
 						register "type" = "UPC_TYPE_INTERNAL"
 						register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A16)"
-						device ref usb2_port8 on end
+						device ref usb2_port8 on
+							probe WIFI WIFI_PCIE_6
+							probe WIFI WIFI_PCIE_7
+						end
 					end
 					chip drivers/usb/acpi
 						register "desc" = ""USB3 Type-A Port 1""
@@ -570,9 +573,16 @@ chip soc/intel/pantherlake
 				register "wake" = "GPE0_PME_B0"
 				register "add_acpi_dma_property" = "true"
 				register "enable_cnvi_ddr_rfim" = "true"
+				use cnvi_bluetooth as bluetooth_companion
 				device generic 0 on end
 			end
 		end # CNVi
+
+		device ref cnvi_bluetooth on
+			probe WIFI WIFI_CNVI_6
+			probe WIFI WIFI_CNVI_7
+		end
+
 		# NOTE: i2c0 is function 0; hence it needs to be enabled when any of i2c1-5 is enabled.
 		# TPM device is under i2c3. Therefore, i2c0 needs to be enabled anyways.
 		device ref i2c0 on end
diff --git a/src/mainboard/google/fatcat/variants/felino/Makefile.mk b/src/mainboard/google/fatcat/variants/felino/Makefile.mk
index dcd5ec7202..80d4f6236b 100644
--- a/src/mainboard/google/fatcat/variants/felino/Makefile.mk
+++ b/src/mainboard/google/fatcat/variants/felino/Makefile.mk
@@ -6,3 +6,4 @@ romstage-y += memory.c
 ramstage-y += gpio.c
 romstage-$(CONFIG_FW_CONFIG) += fw_config.c
 ramstage-$(CONFIG_FW_CONFIG) += fw_config.c
+ramstage-$(CONFIG_FW_CONFIG) += variant.c
diff --git a/src/mainboard/google/fatcat/variants/felino/overridetree.cb b/src/mainboard/google/fatcat/variants/felino/overridetree.cb
index aa8c16b949..b3b63e7b5c 100644
--- a/src/mainboard/google/fatcat/variants/felino/overridetree.cb
+++ b/src/mainboard/google/fatcat/variants/felino/overridetree.cb
@@ -67,7 +67,7 @@ chip soc/intel/pantherlake
 	register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC_SKIP)" # USB2_C1
 	register "usb2_ports[4]" = "USB2_PORT_MID(OC_SKIP)" # Type-A Port A0  # USB HUB (USB2 Camera)
 	register "usb2_ports[5]" = "USB2_PORT_LONG(OC3)" # Type-A Port A1 /
-	register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # CNVi BT or discrete BT
+	register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # Discrete Bluetooth
 
 	register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB3.2 x1 Type-A Con #2 /
 
@@ -187,7 +187,10 @@ device ref tbt_pcie_rp0 on end
 						register "desc" = ""USB2 Bluetooth""
 						register "type" = "UPC_TYPE_INTERNAL"
 						register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A16)"
-						device ref usb2_port8 on end
+						device ref usb2_port8 on
+							probe WIFI WIFI_PCIE_6
+							probe WIFI WIFI_PCIE_7
+						end
 					end
 					chip drivers/usb/acpi
 						register "desc" = ""USB3 Type-A Port 1""
@@ -266,10 +269,16 @@ device ref tbt_pcie_rp0 on end
 				register "wake" = "GPE0_PME_B0"
 				register "add_acpi_dma_property" = "true"
 				register "enable_cnvi_ddr_rfim" = "true"
+				use cnvi_bluetooth as bluetooth_companion
 				device generic 0 on end
 			end
 		end # CNVi
 
+		device ref cnvi_bluetooth on
+			probe WIFI WIFI_CNVI_6
+			probe WIFI WIFI_CNVI_7
+		end
+
 		device ref i2c0 on end
 
 		device ref i2c1 on
diff --git a/src/mainboard/google/fatcat/variants/felino/variant.c b/src/mainboard/google/fatcat/variants/felino/variant.c
new file mode 100644
index 0000000000..76089ed577
--- /dev/null
+++ b/src/mainboard/google/fatcat/variants/felino/variant.c
@@ -0,0 +1,13 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <baseboard/variants.h>
+#include <fw_config.h>
+
+void variant_update_soc_chip_config(struct soc_intel_pantherlake_config *config)
+{
+	if (fw_config_probe(FW_CONFIG(WIFI, WIFI_CNVI_6)) || /* CNVi Wi-Fi */
+	    fw_config_probe(FW_CONFIG(WIFI, WIFI_CNVI_7))) {
+		config->cnvi_wifi_core = true;
+		config->cnvi_bt_core = true;
+	}
+}
diff --git a/src/mainboard/google/fatcat/variants/francka/overridetree.cb b/src/mainboard/google/fatcat/variants/francka/overridetree.cb
index f9ae720e0f..f9e172c8cf 100644
--- a/src/mainboard/google/fatcat/variants/francka/overridetree.cb
+++ b/src/mainboard/google/fatcat/variants/francka/overridetree.cb
@@ -33,7 +33,6 @@ chip soc/intel/pantherlake
 	register "usb2_ports[4]" = "USB2_PORT_SHORT(OC0)" # Type-A Port A1
 	register "usb2_ports[5]" = "USB2_PORT_TYPE_C(OC_SKIP)" # USB2_C1
 	register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" # USB HUB (USB2 Camera)
-	register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # CNVi BT or discrete BT
 
 	register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)" # USB3.2 x1 Type-A Con #0
 	register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC0)" # USB3.2 x1 Type-A Con #1
@@ -53,8 +52,9 @@ chip soc/intel/pantherlake
 	# TCSS USB3
 	register "tcss_aux_ori" = "1"
 
-	# Enable CNVi WiFi
+	# Enable CNVi Wi-Fi and Bluetooth
 	register "cnvi_wifi_core" = "true"
+	register "cnvi_bt_core" = "true"
 
 	register "serial_io_i2c_mode" = "{
 		[PchSerialIoIndexI2C0]  = PchSerialIoPci,
@@ -161,12 +161,6 @@ chip soc/intel/pantherlake
 						register "group" = "ACPI_PLD_GROUP(5, 1)"
 						device ref usb2_port7 on end
 					end
-					chip drivers/usb/acpi
-						register "desc" = ""USB2 Bluetooth""
-						register "type" = "UPC_TYPE_INTERNAL"
-						register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A16)"
-						device ref usb2_port8 on end
-					end
 					chip drivers/usb/acpi
 						register "desc" = ""USB3 Type-A Port 0""
 						register "type" = "UPC_TYPE_USB3_A"
@@ -188,9 +182,13 @@ chip soc/intel/pantherlake
 				register "wake" = "GPE0_PME_B0"
 				register "add_acpi_dma_property" = "true"
 				register "enable_cnvi_ddr_rfim" = "true"
+				use cnvi_bluetooth as bluetooth_companion
 				device generic 0 on end
 			end
 		end # CNVi
+
+		device ref cnvi_bluetooth on end
+
 		# NOTE: i2c0 is function 0; hence it needs to be enabled when any of i2c1-5 is enabled.
 		# TPM device is under i2c1. Therefore, i2c0 needs to be enabled anyways.
 		device ref i2c0 on end

From 9927094ef05d1248788f1c6f86dc11a32a9e990a Mon Sep 17 00:00:00 2001
From: Momoko Hattori <momohatt@google.com>
Date: Thu, 13 Mar 2025 22:14:06 +0900
Subject: [PATCH 0542/3886] mb/google/brya: Enable use_gpio_for_status for
 touchscreen

The _STA method of touchscreen's power resource currently always returns
true. This causes the touchscreen to be powered on by the kernel in a
boot critical path (in acpi_bus_init_power) and block the boot for a
while due to the long (~300ms depending on variants) sleeps in the _ON
method of the power resource. To prevent it, enable use_gpio_for_status
so that the implementation of _STA returns the touchscreen's actual
power state and the kernel powers it on in another place that doesn't
block boot.

The similar change has already been made to mb/google/brya/var/redrix in
commit d0367e38a9e5 ("mb/google/brya/var/redrix: Enable
use_gpio_for_status for touchscreen") (CB:86749). This change applies it
to all the other non-4es brya variants with touchscreen.

BUG=b:397355818
TEST=Dump SSDT and check that the _STA method of touchscreen (i2c3)
     PowerResource doesn't always return true.
TEST=Check that touchscreen works with the change.
TEST=Check that kernel sleep during ACPI initialization is removed by
     checking the timestamps of 'New power resource' logs from ACPI in
     /var/log/messages.
TEST=(Tested above on crota)

Change-Id: I068faa97089ce0011727325ffc868450572bdf58
Signed-off-by: Momoko Hattori <momohatt@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86876
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Sam McNally <sammc@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/google/brya/variants/anahera/overridetree.cb   | 2 ++
 src/mainboard/google/brya/variants/brya0/overridetree.cb     | 3 +++
 src/mainboard/google/brya/variants/crota/overridetree.cb     | 1 +
 src/mainboard/google/brya/variants/dochi/overridetree.cb     | 2 ++
 src/mainboard/google/brya/variants/felwinter/overridetree.cb | 1 +
 src/mainboard/google/brya/variants/gaelin/overridetree.cb    | 1 +
 src/mainboard/google/brya/variants/gimble/overridetree.cb    | 1 +
 src/mainboard/google/brya/variants/kano/overridetree.cb      | 1 +
 src/mainboard/google/brya/variants/marasov/overridetree.cb   | 1 +
 src/mainboard/google/brya/variants/mithrax/overridetree.cb   | 1 +
 src/mainboard/google/brya/variants/nova/overridetree.cb      | 1 +
 src/mainboard/google/brya/variants/omnigul/overridetree.cb   | 2 ++
 src/mainboard/google/brya/variants/primus/overridetree.cb    | 2 ++
 src/mainboard/google/brya/variants/skolas/overridetree.cb    | 3 +++
 src/mainboard/google/brya/variants/taeko/overridetree.cb     | 2 ++
 src/mainboard/google/brya/variants/taniks/overridetree.cb    | 2 ++
 src/mainboard/google/brya/variants/vell/overridetree.cb      | 1 +
 src/mainboard/google/brya/variants/volmar/overridetree.cb    | 1 +
 src/mainboard/google/brya/variants/zydron/overridetree.cb    | 1 +
 19 files changed, 29 insertions(+)

diff --git a/src/mainboard/google/brya/variants/anahera/overridetree.cb b/src/mainboard/google/brya/variants/anahera/overridetree.cb
index 95787eec85..2670e11a8e 100644
--- a/src/mainboard/google/brya/variants/anahera/overridetree.cb
+++ b/src/mainboard/google/brya/variants/anahera/overridetree.cb
@@ -281,6 +281,7 @@ chip soc/intel/alderlake
 				register "stop_gpio" =
 							"ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C6)"
 				register "has_power_resource" = "true"
+				register "use_gpio_for_status" = "true"
 				device i2c 10 on end
 			end
 			chip drivers/i2c/hid
@@ -295,6 +296,7 @@ chip soc/intel/alderlake
 							"ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C0)"
 				register "generic.enable_delay_ms" = "1"
 				register "generic.has_power_resource" = "1"
+				register "generic.use_gpio_for_status" = "true"
 				register "hid_desc_reg_offset" = "0x01"
 				device i2c 40 on end
 			end
diff --git a/src/mainboard/google/brya/variants/brya0/overridetree.cb b/src/mainboard/google/brya/variants/brya0/overridetree.cb
index 3212a5b663..24612c10de 100644
--- a/src/mainboard/google/brya/variants/brya0/overridetree.cb
+++ b/src/mainboard/google/brya/variants/brya0/overridetree.cb
@@ -955,6 +955,7 @@ chip soc/intel/alderlake
 						"ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C6)"
 				register "generic.stop_off_delay_ms" = "1"
 				register "generic.has_power_resource" = "1"
+				register "generic.use_gpio_for_status" = "true"
 				register "hid_desc_reg_offset" = "0x01"
 				device i2c 0x10 on end
 			end
@@ -974,6 +975,7 @@ chip soc/intel/alderlake
 						"ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C6)"
 				register "generic.stop_off_delay_ms" = "1"
 				register "generic.has_power_resource" = "1"
+				register "generic.use_gpio_for_status" = "true"
 				register "hid_desc_reg_offset" = "0x01"
 				device i2c 0x5d on end
 			end
@@ -991,6 +993,7 @@ chip soc/intel/alderlake
 						"ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C0)"
 				register "generic.enable_delay_ms" = "7"
 				register "generic.has_power_resource" = "1"
+				register "generic.use_gpio_for_status" = "true"
 				register "hid_desc_reg_offset" = "0x00"
 				device i2c 5c on end
 			end
diff --git a/src/mainboard/google/brya/variants/crota/overridetree.cb b/src/mainboard/google/brya/variants/crota/overridetree.cb
index 7b0fd59676..a55c68c98e 100644
--- a/src/mainboard/google/brya/variants/crota/overridetree.cb
+++ b/src/mainboard/google/brya/variants/crota/overridetree.cb
@@ -280,6 +280,7 @@ chip soc/intel/alderlake
 							"ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C6)"
 				register "generic.stop_off_delay_ms" = "1"
 				register "generic.has_power_resource" = "1"
+				register "generic.use_gpio_for_status" = "true"
 				register "hid_desc_reg_offset" = "0x01"
 				device i2c 0x16 on end
 			end
diff --git a/src/mainboard/google/brya/variants/dochi/overridetree.cb b/src/mainboard/google/brya/variants/dochi/overridetree.cb
index f74db6e9ac..8a10a7e88d 100644
--- a/src/mainboard/google/brya/variants/dochi/overridetree.cb
+++ b/src/mainboard/google/brya/variants/dochi/overridetree.cb
@@ -259,6 +259,7 @@ chip soc/intel/alderlake
 				register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C0)"
 				register "generic.enable_delay_ms" = "12"
 				register "generic.has_power_resource" = "1"
+				register "generic.use_gpio_for_status" = "true"
 				register "hid_desc_reg_offset" = "0x01"
 				device i2c 41 on end
 			end
@@ -276,6 +277,7 @@ chip soc/intel/alderlake
 				register "generic.stop_delay_ms" = "150"
 				register "generic.stop_off_delay_ms" = "2"
 				register "generic.has_power_resource" = "1"
+				register "generic.use_gpio_for_status" = "true"
 				register "hid_desc_reg_offset" = "0x01"
 				device i2c 10 on end
 			end
diff --git a/src/mainboard/google/brya/variants/felwinter/overridetree.cb b/src/mainboard/google/brya/variants/felwinter/overridetree.cb
index ee8b584e7c..1865ac6966 100644
--- a/src/mainboard/google/brya/variants/felwinter/overridetree.cb
+++ b/src/mainboard/google/brya/variants/felwinter/overridetree.cb
@@ -304,6 +304,7 @@ chip soc/intel/alderlake
 							"ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C6)"
 				register "generic.stop_off_delay_ms" = "1"
 				register "generic.has_power_resource" = "1"
+				register "generic.use_gpio_for_status" = "true"
 				register "hid_desc_reg_offset" = "0x01"
 				device i2c 10 on end
 			end
diff --git a/src/mainboard/google/brya/variants/gaelin/overridetree.cb b/src/mainboard/google/brya/variants/gaelin/overridetree.cb
index 014be974b2..b7bd9f0942 100644
--- a/src/mainboard/google/brya/variants/gaelin/overridetree.cb
+++ b/src/mainboard/google/brya/variants/gaelin/overridetree.cb
@@ -209,6 +209,7 @@ chip soc/intel/alderlake
 				register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C6)"
 				register "generic.enable_delay_ms" = "6"
 				register "generic.has_power_resource" = "1"
+				register "generic.use_gpio_for_status" = "true"
 				device i2c 34 on end
 			end
 		end # I2C3
diff --git a/src/mainboard/google/brya/variants/gimble/overridetree.cb b/src/mainboard/google/brya/variants/gimble/overridetree.cb
index 314899675b..4f1bcdcfb9 100644
--- a/src/mainboard/google/brya/variants/gimble/overridetree.cb
+++ b/src/mainboard/google/brya/variants/gimble/overridetree.cb
@@ -237,6 +237,7 @@ chip soc/intel/alderlake
 							"ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C6)"
 				register "generic.stop_off_delay_ms" = "1"
 				register "generic.has_power_resource" = "1"
+				register "generic.use_gpio_for_status" = "true"
 				register "hid_desc_reg_offset" = "0x01"
 				device i2c 0x15 on end
 			end
diff --git a/src/mainboard/google/brya/variants/kano/overridetree.cb b/src/mainboard/google/brya/variants/kano/overridetree.cb
index 6e3383eaea..c832f96301 100644
--- a/src/mainboard/google/brya/variants/kano/overridetree.cb
+++ b/src/mainboard/google/brya/variants/kano/overridetree.cb
@@ -434,6 +434,7 @@ chip soc/intel/alderlake
 							"ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C6)"
 				register "generic.stop_off_delay_ms" = "1"
 				register "generic.has_power_resource" = "1"
+				register "generic.use_gpio_for_status" = "true"
 				register "hid_desc_reg_offset" = "0x01"
 				device i2c 0x10 on end
 			end
diff --git a/src/mainboard/google/brya/variants/marasov/overridetree.cb b/src/mainboard/google/brya/variants/marasov/overridetree.cb
index add5181b2f..392fbdd715 100644
--- a/src/mainboard/google/brya/variants/marasov/overridetree.cb
+++ b/src/mainboard/google/brya/variants/marasov/overridetree.cb
@@ -306,6 +306,7 @@ chip soc/intel/alderlake
 				register "stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C6)"
 				register "stop_off_delay_ms" = "1"
 				register "has_power_resource" = "true"
+				register "use_gpio_for_status" = "true"
 				device i2c 10 on
 					probe TOUCH TOUCH_ELAN0001
 				end
diff --git a/src/mainboard/google/brya/variants/mithrax/overridetree.cb b/src/mainboard/google/brya/variants/mithrax/overridetree.cb
index 0e1ba0b736..15bebe2a1a 100644
--- a/src/mainboard/google/brya/variants/mithrax/overridetree.cb
+++ b/src/mainboard/google/brya/variants/mithrax/overridetree.cb
@@ -258,6 +258,7 @@ chip soc/intel/alderlake
 							"ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C6)"
 				register "generic.stop_off_delay_ms" = "1"
 				register "generic.has_power_resource" = "1"
+				register "generic.use_gpio_for_status" = "true"
 				register "hid_desc_reg_offset" = "0x01"
 				device i2c 10 on end
 			end
diff --git a/src/mainboard/google/brya/variants/nova/overridetree.cb b/src/mainboard/google/brya/variants/nova/overridetree.cb
index a615fdd70b..091edd52c0 100644
--- a/src/mainboard/google/brya/variants/nova/overridetree.cb
+++ b/src/mainboard/google/brya/variants/nova/overridetree.cb
@@ -218,6 +218,7 @@ chip soc/intel/alderlake
                                 register "generic.reset_delay_ms" = "200"
                                 register "generic.enable_delay_ms" = "12"
                                 register "generic.has_power_resource" = "1"
+                                register "generic.use_gpio_for_status" = "true"
                                 register "hid_desc_reg_offset" = "0x01"
                                 device i2c 41 on end
 			end
diff --git a/src/mainboard/google/brya/variants/omnigul/overridetree.cb b/src/mainboard/google/brya/variants/omnigul/overridetree.cb
index a6c5eccf2c..20e3d41064 100644
--- a/src/mainboard/google/brya/variants/omnigul/overridetree.cb
+++ b/src/mainboard/google/brya/variants/omnigul/overridetree.cb
@@ -287,6 +287,7 @@ chip soc/intel/alderlake
 				register "generic.stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C6)"
 				register "generic.stop_off_delay_ms" = "2"
 				register "generic.has_power_resource" = "1"
+				register "generic.use_gpio_for_status" = "true"
 				register "hid_desc_reg_offset" = "0x01"
 				device i2c 40 on end
 			end
@@ -304,6 +305,7 @@ chip soc/intel/alderlake
 				register "generic.stop_delay_ms" = "150"
 				register "generic.stop_off_delay_ms" = "2"
 				register "generic.has_power_resource" = "1"
+				register "generic.use_gpio_for_status" = "true"
 				register "hid_desc_reg_offset" = "0x01"
 				device i2c 10 on end
 			end
diff --git a/src/mainboard/google/brya/variants/primus/overridetree.cb b/src/mainboard/google/brya/variants/primus/overridetree.cb
index 893b3cf062..b2619ee67d 100644
--- a/src/mainboard/google/brya/variants/primus/overridetree.cb
+++ b/src/mainboard/google/brya/variants/primus/overridetree.cb
@@ -258,6 +258,7 @@ chip soc/intel/alderlake
 							"ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C6)"
 				register "generic.stop_off_delay_ms" = "1"
 				register "generic.has_power_resource" = "1"
+				register "generic.use_gpio_for_status" = "true"
 				register "hid_desc_reg_offset" = "0x01"
 				device i2c 0x10 on end
 			end
@@ -273,6 +274,7 @@ chip soc/intel/alderlake
 							"ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C0)"
 				register "generic.enable_delay_ms" = "1"
 				register "generic.has_power_resource" = "1"
+				register "generic.use_gpio_for_status" = "true"
 				register "hid_desc_reg_offset" = "0x01"
 				device i2c 0x40 on end
 			end
diff --git a/src/mainboard/google/brya/variants/skolas/overridetree.cb b/src/mainboard/google/brya/variants/skolas/overridetree.cb
index c87690c66a..dc3ef3d34f 100644
--- a/src/mainboard/google/brya/variants/skolas/overridetree.cb
+++ b/src/mainboard/google/brya/variants/skolas/overridetree.cb
@@ -954,6 +954,7 @@ chip soc/intel/alderlake
 						"ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C6)"
 				register "generic.stop_off_delay_ms" = "1"
 				register "generic.has_power_resource" = "1"
+				register "generic.use_gpio_for_status" = "true"
 				register "hid_desc_reg_offset" = "0x01"
 				device i2c 0x10 on end
 			end
@@ -973,6 +974,7 @@ chip soc/intel/alderlake
 						"ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C6)"
 				register "generic.stop_off_delay_ms" = "1"
 				register "generic.has_power_resource" = "1"
+				register "generic.use_gpio_for_status" = "true"
 				register "hid_desc_reg_offset" = "0x01"
 				device i2c 0x5d on end
 			end
@@ -990,6 +992,7 @@ chip soc/intel/alderlake
 						"ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C0)"
 				register "generic.enable_delay_ms" = "7"
 				register "generic.has_power_resource" = "1"
+				register "generic.use_gpio_for_status" = "true"
 				register "hid_desc_reg_offset" = "0x00"
 				device i2c 5c on end
 			end
diff --git a/src/mainboard/google/brya/variants/taeko/overridetree.cb b/src/mainboard/google/brya/variants/taeko/overridetree.cb
index 964d83309b..ff25f7b638 100644
--- a/src/mainboard/google/brya/variants/taeko/overridetree.cb
+++ b/src/mainboard/google/brya/variants/taeko/overridetree.cb
@@ -478,6 +478,7 @@ chip soc/intel/alderlake
 				# Parameter T4 >= 1ms
 				register "generic.stop_off_delay_ms" = "1"
 				register "generic.has_power_resource" = "1"
+				register "generic.use_gpio_for_status" = "true"
 				register "hid_desc_reg_offset" = "0x01"
 				device i2c 5d on end
 			end
@@ -493,6 +494,7 @@ chip soc/intel/alderlake
 						"ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C0)"
 				register "enable_delay_ms" = "1"
 				register "has_power_resource" = "true"
+				register "use_gpio_for_status" = "true"
 				device i2c 10 on end
 			end
 		end
diff --git a/src/mainboard/google/brya/variants/taniks/overridetree.cb b/src/mainboard/google/brya/variants/taniks/overridetree.cb
index ebe5853283..e11793ae4e 100644
--- a/src/mainboard/google/brya/variants/taniks/overridetree.cb
+++ b/src/mainboard/google/brya/variants/taniks/overridetree.cb
@@ -295,6 +295,7 @@ chip soc/intel/alderlake
 				# Parameter T4 >= 1ms
 				register "generic.stop_off_delay_ms" = "1"
 				register "generic.has_power_resource" = "1"
+				register "generic.use_gpio_for_status" = "true"
 				register "hid_desc_reg_offset" = "0x01"
 				device i2c 5d on end
 			end
@@ -310,6 +311,7 @@ chip soc/intel/alderlake
 						"ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C0)"
 				register "enable_delay_ms" = "1"
 				register "has_power_resource" = "true"
+				register "use_gpio_for_status" = "true"
 				device i2c 10 on end
 			end
 		end
diff --git a/src/mainboard/google/brya/variants/vell/overridetree.cb b/src/mainboard/google/brya/variants/vell/overridetree.cb
index 6f9b325a19..273fb0e3ab 100644
--- a/src/mainboard/google/brya/variants/vell/overridetree.cb
+++ b/src/mainboard/google/brya/variants/vell/overridetree.cb
@@ -330,6 +330,7 @@ chip soc/intel/alderlake
 							"ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C6)"
 				register "generic.stop_off_delay_ms" = "1"
 				register "generic.has_power_resource" = "1"
+				register "generic.use_gpio_for_status" = "true"
 				register "hid_desc_reg_offset" = "0x01"
 				device i2c 0x10 on end
 			end
diff --git a/src/mainboard/google/brya/variants/volmar/overridetree.cb b/src/mainboard/google/brya/variants/volmar/overridetree.cb
index 96935170f1..f57b733931 100644
--- a/src/mainboard/google/brya/variants/volmar/overridetree.cb
+++ b/src/mainboard/google/brya/variants/volmar/overridetree.cb
@@ -295,6 +295,7 @@ chip soc/intel/alderlake
 							"ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C6)"
 				register "generic.stop_off_delay_ms" = "1"
 				register "generic.has_power_resource" = "1"
+				register "generic.use_gpio_for_status" = "true"
 				register "hid_desc_reg_offset" = "0x01"
 				device i2c 0x10 on end
 			end
diff --git a/src/mainboard/google/brya/variants/zydron/overridetree.cb b/src/mainboard/google/brya/variants/zydron/overridetree.cb
index 0acf4906c8..a3c4f34f6c 100644
--- a/src/mainboard/google/brya/variants/zydron/overridetree.cb
+++ b/src/mainboard/google/brya/variants/zydron/overridetree.cb
@@ -410,6 +410,7 @@ chip soc/intel/alderlake
 							"ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C6)"
 				register "generic.stop_off_delay_ms" = "1"
 				register "generic.has_power_resource" = "1"
+				register "generic.use_gpio_for_status" = "true"
 				register "hid_desc_reg_offset" = "0x01"
 				device i2c 0x10 on end
 			end

From 0afe12b60631f2746773592eac31d61e08154087 Mon Sep 17 00:00:00 2001
From: Momoko Hattori <momohatt@google.com>
Date: Thu, 13 Mar 2025 22:15:05 +0900
Subject: [PATCH 0543/3886] mb/google/nissa: Enable use_gpio_for_status for
 touchscreen

The _STA method of touchscreen's power resource currently always returns
true. This causes the touchscreen to be powered on by the kernel in a
boot critical path (in acpi_bus_init_power) and block the boot for a
while due to the long (~300ms depending on variants) sleeps in the _ON
method of the power resource. To prevent it, enable use_gpio_for_status
so that the implementation of _STA returns the touchscreen's actual
power state and the kernel powers it on in another place that doesn't
block boot.

The similar change has already been made to mb/google/brya/var/redrix in
commit d0367e38a9e5 ("mb/google/brya/var/redrix: Enable
use_gpio_for_status for touchscreen") (CB:86749). This change applies it
to all nissa variants with touchscreen except for pujjoniru, whose
touchscreen does not have has_power_resource option enabled.

BUG=b:397355818
TEST=Dump SSDT and check that the _STA method of touchscreen (i2c1)
     PowerResource doesn't always return true.
TEST=Check that touchscreen works with the change.
TEST=Check that kernel sleep during ACPI initialization is removed by
     checking the timestamps of 'New power resource' logs from ACPI in
     /var/log/messages and/or getting perfetto boot-time trace.
TEST=(Tested the above on gothrax and riven)

Change-Id: I126e0b2cece6b3fb9a750a908e6cc9663b7f37c9
Signed-off-by: Momoko Hattori <momohatt@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86877
Reviewed-by: Sam McNally <sammc@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jayvik Desai <jayvik@google.com>
---
 src/mainboard/google/brya/variants/anraggar/overridetree.cb | 1 +
 src/mainboard/google/brya/variants/craask/overridetree.cb   | 4 ++++
 src/mainboard/google/brya/variants/craaskov/overridetree.cb | 1 +
 src/mainboard/google/brya/variants/glassway/overridetree.cb | 4 ++++
 src/mainboard/google/brya/variants/gothrax/overridetree.cb  | 3 +++
 src/mainboard/google/brya/variants/guren/overridetree.cb    | 1 +
 src/mainboard/google/brya/variants/joxer/overridetree.cb    | 4 ++++
 src/mainboard/google/brya/variants/meliks/overridetree.cb   | 1 +
 src/mainboard/google/brya/variants/nereid/overridetree.cb   | 1 +
 src/mainboard/google/brya/variants/nivviks/overridetree.cb  | 1 +
 src/mainboard/google/brya/variants/orisa/overridetree.cb    | 1 +
 src/mainboard/google/brya/variants/pirrha/overridetree.cb   | 1 +
 src/mainboard/google/brya/variants/pujjo/overridetree.cb    | 3 +++
 src/mainboard/google/brya/variants/pujjoga/overridetree.cb  | 1 +
 src/mainboard/google/brya/variants/quandiso/overridetree.cb | 3 +++
 src/mainboard/google/brya/variants/riven/overridetree.cb    | 3 +++
 src/mainboard/google/brya/variants/rull/overridetree.cb     | 2 ++
 src/mainboard/google/brya/variants/sundance/overridetree.cb | 1 +
 src/mainboard/google/brya/variants/teliks/overridetree.cb   | 1 +
 src/mainboard/google/brya/variants/telith/overridetree.cb   | 1 +
 src/mainboard/google/brya/variants/uldren/overridetree.cb   | 6 ++++++
 src/mainboard/google/brya/variants/xivu/overridetree.cb     | 1 +
 src/mainboard/google/brya/variants/yaviks/overridetree.cb   | 4 ++++
 src/mainboard/google/brya/variants/yavilla/overridetree.cb  | 5 +++++
 24 files changed, 54 insertions(+)

diff --git a/src/mainboard/google/brya/variants/anraggar/overridetree.cb b/src/mainboard/google/brya/variants/anraggar/overridetree.cb
index d64063afe7..d102021488 100644
--- a/src/mainboard/google/brya/variants/anraggar/overridetree.cb
+++ b/src/mainboard/google/brya/variants/anraggar/overridetree.cb
@@ -244,6 +244,7 @@ chip soc/intel/alderlake
 				register "generic.stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C6)"
 				register "generic.stop_off_delay_ms" = "200"
 				register "generic.has_power_resource" = "1"
+				register "generic.use_gpio_for_status" = "true"
 				register "hid_desc_reg_offset" = "0x01"
 				device i2c 41 on end
 			end
diff --git a/src/mainboard/google/brya/variants/craask/overridetree.cb b/src/mainboard/google/brya/variants/craask/overridetree.cb
index ee8a63dd18..576d9f1f4d 100644
--- a/src/mainboard/google/brya/variants/craask/overridetree.cb
+++ b/src/mainboard/google/brya/variants/craask/overridetree.cb
@@ -337,6 +337,7 @@ chip soc/intel/alderlake
 				register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C0)"
 				register "generic.enable_delay_ms" = "12"
 				register "generic.has_power_resource" = "1"
+				register "generic.use_gpio_for_status" = "true"
 				register "hid_desc_reg_offset" = "0x01"
 				device i2c 0x40 on
 					probe TS_SOURCE TS_UNPROVISIONED
@@ -353,6 +354,7 @@ chip soc/intel/alderlake
 				register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C0)"
 				register "generic.enable_delay_ms" = "12"
 				register "generic.has_power_resource" = "1"
+				register "generic.use_gpio_for_status" = "true"
 				register "hid_desc_reg_offset" = "0x01"
 				device i2c 0x40 on
 					probe TS_SOURCE TS_GTCH7503
@@ -386,6 +388,7 @@ chip soc/intel/alderlake
 				register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C0)"
 				register "generic.enable_delay_ms" = "1"
 				register "generic.has_power_resource" = "1"
+				register "generic.use_gpio_for_status" = "true"
 				register "hid_desc_reg_offset" = "0x01"
 				device i2c 10 on
 					probe TS_SOURCE TS_UNPROVISIONED
@@ -403,6 +406,7 @@ chip soc/intel/alderlake
 				register "generic.stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C6)"
 				register "generic.stop_off_delay_ms" = "200"
 				register "generic.has_power_resource" = "1"
+				register "generic.use_gpio_for_status" = "true"
 				register "hid_desc_reg_offset" = "0x01"
 				device i2c 41 on
 					probe TS_SOURCE TS_ILTK0001
diff --git a/src/mainboard/google/brya/variants/craaskov/overridetree.cb b/src/mainboard/google/brya/variants/craaskov/overridetree.cb
index eabf155883..68ea9e9afa 100644
--- a/src/mainboard/google/brya/variants/craaskov/overridetree.cb
+++ b/src/mainboard/google/brya/variants/craaskov/overridetree.cb
@@ -350,6 +350,7 @@ chip soc/intel/alderlake
 				register "generic.stop_delay_ms" = "150"
 				register "generic.stop_off_delay_ms" = "2"
 				register "generic.has_power_resource" = "1"
+				register "generic.use_gpio_for_status" = "true"
 				register "hid_desc_reg_offset" = "0x01"
 				device i2c 10 on end
 			end
diff --git a/src/mainboard/google/brya/variants/glassway/overridetree.cb b/src/mainboard/google/brya/variants/glassway/overridetree.cb
index 684fd83db1..9d84273eac 100644
--- a/src/mainboard/google/brya/variants/glassway/overridetree.cb
+++ b/src/mainboard/google/brya/variants/glassway/overridetree.cb
@@ -354,6 +354,7 @@ chip soc/intel/alderlake
 				register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C0)"
 				register "enable_delay_ms" = "25"
 				register "has_power_resource" = "true"
+				register "use_gpio_for_status" = "true"
 				device i2c 10 on
 					probe TOUCHSCREEN_SOURCE TOUCHSCREEN_UNPROVISIONED
 					probe TOUCHSCREEN_SOURCE TOUCHSCREEN_ELAN0001
@@ -373,6 +374,7 @@ chip soc/intel/alderlake
 				register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C0)"
 				register "generic.enable_delay_ms" = "5"
 				register "generic.has_power_resource" = "1"
+				register "generic.use_gpio_for_status" = "true"
 				register "hid_desc_reg_offset" = "0x01"
 				device i2c 40  on
 					probe TOUCHSCREEN_SOURCE TOUCHSCREEN_GTCH7503
@@ -392,6 +394,7 @@ chip soc/intel/alderlake
 				register "generic.stop_delay_ms" = "150"
 				register "generic.stop_off_delay_ms" = "2"
 				register "generic.has_power_resource" = "1"
+				register "generic.use_gpio_for_status" = "true"
 				register "hid_desc_reg_offset" = "0x01"
 				device i2c 10 on
 					probe TOUCHSCREEN_SOURCE TOUCHSCREEN_ELAN9004
@@ -411,6 +414,7 @@ chip soc/intel/alderlake
 				register "generic.stop_delay_ms" = "105"
 				register "generic.stop_off_delay_ms" = "5"
 				register "generic.has_power_resource" = "1"
+				register "generic.use_gpio_for_status" = "true"
 				register "hid_desc_reg_offset" = "0x01"
 				device i2c 41 on
 					probe TOUCHSCREEN_SOURCE TOUCHSCREEN_ILIT2901
diff --git a/src/mainboard/google/brya/variants/gothrax/overridetree.cb b/src/mainboard/google/brya/variants/gothrax/overridetree.cb
index e611b17315..41f836673f 100644
--- a/src/mainboard/google/brya/variants/gothrax/overridetree.cb
+++ b/src/mainboard/google/brya/variants/gothrax/overridetree.cb
@@ -229,6 +229,7 @@ chip soc/intel/alderlake
 					"ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C0)"
 				register "generic.enable_delay_ms" = "6"
 				register "generic.has_power_resource" = "1"
+				register "generic.use_gpio_for_status" = "true"
 				register "hid_desc_reg_offset" = "0x01"
 				device i2c 0x10 on
 					probe TOUCH_PANEL TOUCH_PANEL_I2C_HID
@@ -247,6 +248,7 @@ chip soc/intel/alderlake
 					"ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C0)"
 				register "generic.enable_delay_ms" = "6"
 				register "generic.has_power_resource" = "1"
+				register "generic.use_gpio_for_status" = "true"
 				register "hid_desc_reg_offset" = "0x01"
 				device i2c 0x41 on
 					probe TOUCH_PANEL TOUCH_PANEL_I2C_HID
@@ -264,6 +266,7 @@ chip soc/intel/alderlake
 							"ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C0)"
 				register "enable_delay_ms" = "6"
 				register "has_power_resource" = "true"
+				register "use_gpio_for_status" = "true"
 				device i2c 10 on
 					probe TOUCH_PANEL TOUCH_PANEL_I2C_GENERIC
 				end
diff --git a/src/mainboard/google/brya/variants/guren/overridetree.cb b/src/mainboard/google/brya/variants/guren/overridetree.cb
index 0a62ca59b0..77ec260074 100644
--- a/src/mainboard/google/brya/variants/guren/overridetree.cb
+++ b/src/mainboard/google/brya/variants/guren/overridetree.cb
@@ -338,6 +338,7 @@ chip soc/intel/alderlake
 				register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C0)"
 				register "enable_delay_ms" = "25"
 				register "has_power_resource" = "true"
+				register "use_gpio_for_status" = "true"
 				device i2c 10 on
 					probe TOUCHSCREEN_SOURCE TOUCHSCREEN_ELAN0001
 				end
diff --git a/src/mainboard/google/brya/variants/joxer/overridetree.cb b/src/mainboard/google/brya/variants/joxer/overridetree.cb
index c7849d22cd..e5f4cce56a 100644
--- a/src/mainboard/google/brya/variants/joxer/overridetree.cb
+++ b/src/mainboard/google/brya/variants/joxer/overridetree.cb
@@ -227,6 +227,7 @@ chip soc/intel/alderlake
 				register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C0)"
 				register "enable_delay_ms" = "1"
 				register "has_power_resource" = "true"
+				register "use_gpio_for_status" = "true"
 				device i2c 10 on end
 			end
 			chip drivers/i2c/hid
@@ -243,6 +244,7 @@ chip soc/intel/alderlake
 				register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C0)"
 				register "generic.enable_delay_ms" = "1"
 				register "generic.has_power_resource" = "1"
+				register "generic.use_gpio_for_status" = "true"
 				register "hid_desc_reg_offset" = "0x01"
 				device i2c 15 on end
 			end
@@ -258,6 +260,7 @@ chip soc/intel/alderlake
 				register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C0)"
 				register "generic.enable_delay_ms" = "1"
 				register "generic.has_power_resource" = "1"
+				register "generic.use_gpio_for_status" = "true"
 				register "hid_desc_reg_offset" = "0x01"
 				device i2c 40 on end
 			end
@@ -274,6 +277,7 @@ chip soc/intel/alderlake
 				register "generic.stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C6)"
 				register "generic.stop_off_delay_ms" = "1"
 				register "generic.has_power_resource" = "1"
+				register "generic.use_gpio_for_status" = "true"
 				register "hid_desc_reg_offset" = "0x01"
 				device i2c 0x14 on end
 			end
diff --git a/src/mainboard/google/brya/variants/meliks/overridetree.cb b/src/mainboard/google/brya/variants/meliks/overridetree.cb
index f522ed3211..913ccb8897 100644
--- a/src/mainboard/google/brya/variants/meliks/overridetree.cb
+++ b/src/mainboard/google/brya/variants/meliks/overridetree.cb
@@ -256,6 +256,7 @@ chip soc/intel/alderlake
 				register "generic.reset_delay_ms" = "200"
 				register "generic.reset_off_delay_ms" = "2"
 				register "generic.has_power_resource" = "1"
+				register "generic.use_gpio_for_status" = "true"
 				register "hid_desc_reg_offset" = "0x1"
 				device i2c 4F on end
 			end
diff --git a/src/mainboard/google/brya/variants/nereid/overridetree.cb b/src/mainboard/google/brya/variants/nereid/overridetree.cb
index 9d9b871d0a..61c2749821 100644
--- a/src/mainboard/google/brya/variants/nereid/overridetree.cb
+++ b/src/mainboard/google/brya/variants/nereid/overridetree.cb
@@ -154,6 +154,7 @@ chip soc/intel/alderlake
 				register "generic.stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C6)"
 				register "generic.stop_off_delay_ms" = "1"
 				register "generic.has_power_resource" = "1"
+				register "generic.use_gpio_for_status" = "true"
 				register "hid_desc_reg_offset" = "0x01"
 				device i2c 5d on end
 			end
diff --git a/src/mainboard/google/brya/variants/nivviks/overridetree.cb b/src/mainboard/google/brya/variants/nivviks/overridetree.cb
index 610752438e..088459b6f4 100644
--- a/src/mainboard/google/brya/variants/nivviks/overridetree.cb
+++ b/src/mainboard/google/brya/variants/nivviks/overridetree.cb
@@ -311,6 +311,7 @@ chip soc/intel/alderlake
 				register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C0)"
 				register "generic.enable_delay_ms" = "1"
 				register "generic.has_power_resource" = "1"
+				register "generic.use_gpio_for_status" = "true"
 				register "hid_desc_reg_offset" = "0x01"
 				device i2c 15 on end
 			end
diff --git a/src/mainboard/google/brya/variants/orisa/overridetree.cb b/src/mainboard/google/brya/variants/orisa/overridetree.cb
index 4e21cde4ef..eb5515d739 100644
--- a/src/mainboard/google/brya/variants/orisa/overridetree.cb
+++ b/src/mainboard/google/brya/variants/orisa/overridetree.cb
@@ -497,6 +497,7 @@ chip soc/intel/alderlake
 				register "generic.stop_delay_ms" = "150"
 				register "generic.stop_off_delay_ms" = "2"
 				register "generic.has_power_resource" = "1"
+				register "generic.use_gpio_for_status" = "true"
 				register "hid_desc_reg_offset" = "0x01"
 				device i2c 10 on end
 			end
diff --git a/src/mainboard/google/brya/variants/pirrha/overridetree.cb b/src/mainboard/google/brya/variants/pirrha/overridetree.cb
index 7d143e456d..9050462390 100644
--- a/src/mainboard/google/brya/variants/pirrha/overridetree.cb
+++ b/src/mainboard/google/brya/variants/pirrha/overridetree.cb
@@ -289,6 +289,7 @@ chip soc/intel/alderlake
 				register "generic.reset_delay_ms" = "200"
 				register "generic.reset_off_delay_ms" = "2"
 				register "generic.has_power_resource" = "1"
+				register "generic.use_gpio_for_status" = "true"
 				register "hid_desc_reg_offset" = "0x1"
 				device i2c 0x4F on end
 			end
diff --git a/src/mainboard/google/brya/variants/pujjo/overridetree.cb b/src/mainboard/google/brya/variants/pujjo/overridetree.cb
index 60b35d79a3..f5a9bd38b2 100644
--- a/src/mainboard/google/brya/variants/pujjo/overridetree.cb
+++ b/src/mainboard/google/brya/variants/pujjo/overridetree.cb
@@ -368,6 +368,7 @@ chip soc/intel/alderlake
 				register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C0)"
 				register "generic.enable_delay_ms" = "1"
 				register "generic.has_power_resource" = "1"
+				register "generic.use_gpio_for_status" = "true"
 				register "hid_desc_reg_offset" = "0x01"
 				device i2c 10 on end
 			end
@@ -385,6 +386,7 @@ chip soc/intel/alderlake
 				register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C0)"
 				register "generic.enable_delay_ms" = "1"
 				register "generic.has_power_resource" = "1"
+				register "generic.use_gpio_for_status" = "true"
 				register "hid_desc_reg_offset" = "0x01"
 				device i2c 24 on end
 			end
@@ -400,6 +402,7 @@ chip soc/intel/alderlake
 							"ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C0)"
 				register "generic.enable_delay_ms" = "1"
 				register "generic.has_power_resource" = "1"
+				register "generic.use_gpio_for_status" = "true"
 				register "hid_desc_reg_offset" = "0x01"
 				device i2c 40 on end
 			end
diff --git a/src/mainboard/google/brya/variants/pujjoga/overridetree.cb b/src/mainboard/google/brya/variants/pujjoga/overridetree.cb
index e1ac962c9f..a63833caba 100644
--- a/src/mainboard/google/brya/variants/pujjoga/overridetree.cb
+++ b/src/mainboard/google/brya/variants/pujjoga/overridetree.cb
@@ -221,6 +221,7 @@ chip soc/intel/alderlake
 				register "generic.stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C6)"
 				register "generic.stop_off_delay_ms" = "1"
 				register "generic.has_power_resource" = "1"
+				register "generic.use_gpio_for_status" = "true"
 				register "hid_desc_reg_offset" = "0x01"
 				device i2c 5d on end
 			end
diff --git a/src/mainboard/google/brya/variants/quandiso/overridetree.cb b/src/mainboard/google/brya/variants/quandiso/overridetree.cb
index 5e0c5a34e2..72b9a77dd0 100644
--- a/src/mainboard/google/brya/variants/quandiso/overridetree.cb
+++ b/src/mainboard/google/brya/variants/quandiso/overridetree.cb
@@ -238,6 +238,7 @@ chip soc/intel/alderlake
 				register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C0)"
 				register "enable_delay_ms" = "1"
 				register "has_power_resource" = "true"
+				register "use_gpio_for_status" = "true"
 				device i2c 10 on end
 			end
 			chip drivers/i2c/hid
@@ -254,6 +255,7 @@ chip soc/intel/alderlake
 				register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C0)"
 				register "generic.enable_delay_ms" = "1"
 				register "generic.has_power_resource" = "1"
+				register "generic.use_gpio_for_status" = "true"
 				register "hid_desc_reg_offset" = "0x01"
 				device i2c 15 on end
 			end
@@ -270,6 +272,7 @@ chip soc/intel/alderlake
 				register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C0)"
 				register "generic.enable_delay_ms" = "1"
 				register "generic.has_power_resource" = "1"
+				register "generic.use_gpio_for_status" = "true"
 				register "hid_desc_reg_offset" = "0x01"
 				device i2c 40 on end
 			end
diff --git a/src/mainboard/google/brya/variants/riven/overridetree.cb b/src/mainboard/google/brya/variants/riven/overridetree.cb
index 1cb63134db..842074c9eb 100644
--- a/src/mainboard/google/brya/variants/riven/overridetree.cb
+++ b/src/mainboard/google/brya/variants/riven/overridetree.cb
@@ -252,6 +252,7 @@ chip soc/intel/alderlake
 				register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C0)"
 				register "generic.enable_delay_ms" = "1"
 				register "generic.has_power_resource" = "1"
+				register "generic.use_gpio_for_status" = "true"
 				register "hid_desc_reg_offset" = "0x01"
 				device i2c 10 on end
 			end
@@ -269,6 +270,7 @@ chip soc/intel/alderlake
 				register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C0)"
 				register "generic.enable_delay_ms" = "1"
 				register "generic.has_power_resource" = "1"
+				register "generic.use_gpio_for_status" = "true"
 				register "hid_desc_reg_offset" = "0x01"
 				device i2c 16 on end
 			end
@@ -283,6 +285,7 @@ chip soc/intel/alderlake
 				register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C0)"
 				register "generic.enable_delay_ms" = "12"
 				register "generic.has_power_resource" = "1"
+				register "generic.use_gpio_for_status" = "true"
 				register "hid_desc_reg_offset" = "0x01"
 				device i2c 40 on end
 			end
diff --git a/src/mainboard/google/brya/variants/rull/overridetree.cb b/src/mainboard/google/brya/variants/rull/overridetree.cb
index e1d94f9b73..0e502f4fe6 100644
--- a/src/mainboard/google/brya/variants/rull/overridetree.cb
+++ b/src/mainboard/google/brya/variants/rull/overridetree.cb
@@ -362,6 +362,7 @@ chip soc/intel/alderlake
 				register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C0)"
 				register "generic.enable_delay_ms" = "1"
 				register "generic.has_power_resource" = "1"
+				register "generic.use_gpio_for_status" = "true"
 				register "hid_desc_reg_offset" = "0x01"
 				device i2c 10 on end
 			end
@@ -376,6 +377,7 @@ chip soc/intel/alderlake
 				register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C0)"
 				register "generic.enable_delay_ms" = "12"
 				register "generic.has_power_resource" = "1"
+				register "generic.use_gpio_for_status" = "true"
 				register "hid_desc_reg_offset" = "0x01"
 				device i2c 40 on end
 			end
diff --git a/src/mainboard/google/brya/variants/sundance/overridetree.cb b/src/mainboard/google/brya/variants/sundance/overridetree.cb
index 8782f5d225..74e7b28960 100644
--- a/src/mainboard/google/brya/variants/sundance/overridetree.cb
+++ b/src/mainboard/google/brya/variants/sundance/overridetree.cb
@@ -217,6 +217,7 @@ chip soc/intel/alderlake
 				register "generic.stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C6)"
 				register "generic.stop_off_delay_ms" = "1"
 				register "generic.has_power_resource" = "1"
+				register "generic.use_gpio_for_status" = "true"
 				register "hid_desc_reg_offset" = "0x01"
 				device i2c 5d on end
 			end
diff --git a/src/mainboard/google/brya/variants/teliks/overridetree.cb b/src/mainboard/google/brya/variants/teliks/overridetree.cb
index 8bff4b6fcf..2010866b0f 100644
--- a/src/mainboard/google/brya/variants/teliks/overridetree.cb
+++ b/src/mainboard/google/brya/variants/teliks/overridetree.cb
@@ -261,6 +261,7 @@ chip soc/intel/alderlake
 				register "generic.stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C6)"
 				register "generic.stop_off_delay_ms" = "200"
 				register "generic.has_power_resource" = "1"
+				register "generic.use_gpio_for_status" = "true"
 				register "hid_desc_reg_offset" = "0x01"
 				device i2c 41 on end
 			end
diff --git a/src/mainboard/google/brya/variants/telith/overridetree.cb b/src/mainboard/google/brya/variants/telith/overridetree.cb
index 202b0ed554..86c4bc43e6 100644
--- a/src/mainboard/google/brya/variants/telith/overridetree.cb
+++ b/src/mainboard/google/brya/variants/telith/overridetree.cb
@@ -381,6 +381,7 @@ chip soc/intel/alderlake
 				register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C0)"
 				register "enable_delay_ms" = "25"
 				register "has_power_resource" = "true"
+				register "use_gpio_for_status" = "true"
 				device i2c 10 on end
 			end
 		end
diff --git a/src/mainboard/google/brya/variants/uldren/overridetree.cb b/src/mainboard/google/brya/variants/uldren/overridetree.cb
index ff440d9202..a2a0e26b81 100644
--- a/src/mainboard/google/brya/variants/uldren/overridetree.cb
+++ b/src/mainboard/google/brya/variants/uldren/overridetree.cb
@@ -221,6 +221,7 @@ chip soc/intel/alderlake
 				register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C0)"
 				register "generic.enable_delay_ms" = "1"
 				register "generic.has_power_resource" = "1"
+				register "generic.use_gpio_for_status" = "true"
 				register "hid_desc_reg_offset" = "0x20"
 				device i2c 2c on
 					probe TOUCHSCREEN TOUCHSCREEN_UNKNOWN
@@ -240,6 +241,7 @@ chip soc/intel/alderlake
 				register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C0)"
 				register "enable_delay_ms" = "1"
 				register "has_power_resource" = "true"
+				register "use_gpio_for_status" = "true"
 				device i2c 10 on
 					probe TOUCHSCREEN TOUCHSCREEN_UNKNOWN
 				end
@@ -257,6 +259,7 @@ chip soc/intel/alderlake
 				register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C0)"
 				register "generic.enable_delay_ms" = "6"
 				register "generic.has_power_resource" = "1"
+				register "generic.use_gpio_for_status" = "true"
 				register "hid_desc_reg_offset" = "0x01"
 				device i2c 16 on
 					probe TOUCHSCREEN TOUCHSCREEN_UNKNOWN
@@ -274,6 +277,7 @@ chip soc/intel/alderlake
 				register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C0)"
 				register "generic.enable_delay_ms" = "10"
 				register "generic.has_power_resource" = "1"
+				register "generic.use_gpio_for_status" = "true"
 				register "hid_desc_reg_offset" = "0x01"
 				device i2c 5d on
 					probe TOUCHSCREEN TOUCHSCREEN_UNKNOWN
@@ -291,6 +295,7 @@ chip soc/intel/alderlake
 				register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C0)"
 				register "generic.enable_delay_ms" = "30"
 				register "generic.has_power_resource" = "1"
+				register "generic.use_gpio_for_status" = "true"
 				register "hid_desc_reg_offset" = "0x01"
 				device i2c 40 on
 					probe TOUCHSCREEN TOUCHSCREEN_UNKNOWN
@@ -308,6 +313,7 @@ chip soc/intel/alderlake
 				register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C0)"
 				register "generic.enable_delay_ms" = "1"
 				register "generic.has_power_resource" = "1"
+				register "generic.use_gpio_for_status" = "true"
 				register "hid_desc_reg_offset" = "0x20"
 				device i2c 3c on
 					probe TOUCHSCREEN TOUCHSCREEN_UNKNOWN
diff --git a/src/mainboard/google/brya/variants/xivu/overridetree.cb b/src/mainboard/google/brya/variants/xivu/overridetree.cb
index 36eea074b4..da7405b204 100644
--- a/src/mainboard/google/brya/variants/xivu/overridetree.cb
+++ b/src/mainboard/google/brya/variants/xivu/overridetree.cb
@@ -225,6 +225,7 @@ chip soc/intel/alderlake
 							"ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C6)"
 				register "generic.stop_off_delay_ms" = "1"
 				register "generic.has_power_resource" = "1"
+				register "generic.use_gpio_for_status" = "true"
 				register "hid_desc_reg_offset" = "0x01"
 				device i2c 10 on end
 			end
diff --git a/src/mainboard/google/brya/variants/yaviks/overridetree.cb b/src/mainboard/google/brya/variants/yaviks/overridetree.cb
index 2c7ae20ec8..d1b49489c9 100644
--- a/src/mainboard/google/brya/variants/yaviks/overridetree.cb
+++ b/src/mainboard/google/brya/variants/yaviks/overridetree.cb
@@ -245,6 +245,7 @@ chip soc/intel/alderlake
 				register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C0)"
 				register "enable_delay_ms" = "5"
 				register "has_power_resource" = "true"
+				register "use_gpio_for_status" = "true"
 				device i2c 10 on
 					probe TOUCH_PANEL TOUCH_I2C
 				end
@@ -262,6 +263,7 @@ chip soc/intel/alderlake
 				register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C0)"
 				register "generic.enable_delay_ms" = "1"
 				register "generic.has_power_resource" = "1"
+				register "generic.use_gpio_for_status" = "true"
 				register "hid_desc_reg_offset" = "0x01"
 				device i2c 10 on
 					probe TOUCH_PANEL TOUCH_HID_I2C
@@ -281,6 +283,7 @@ chip soc/intel/alderlake
 				register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C0)"
 				register "generic.enable_delay_ms" = "1"
 				register "generic.has_power_resource" = "1"
+				register "generic.use_gpio_for_status" = "true"
 				register "hid_desc_reg_offset" = "0x01"
 				device i2c 15 on end
 			end
@@ -299,6 +302,7 @@ chip soc/intel/alderlake
 							"ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C0)"
 				register "generic.enable_delay_ms" = "1"
 				register "generic.has_power_resource" = "1"
+				register "generic.use_gpio_for_status" = "true"
 				register "hid_desc_reg_offset" = "0x01"
 				device i2c 40 on end
 			end
diff --git a/src/mainboard/google/brya/variants/yavilla/overridetree.cb b/src/mainboard/google/brya/variants/yavilla/overridetree.cb
index 015228e2c1..4935a3a65d 100644
--- a/src/mainboard/google/brya/variants/yavilla/overridetree.cb
+++ b/src/mainboard/google/brya/variants/yavilla/overridetree.cb
@@ -262,6 +262,7 @@ chip soc/intel/alderlake
 				register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C0)"
 				register "enable_delay_ms" = "1"
 				register "has_power_resource" = "true"
+				register "use_gpio_for_status" = "true"
 				device i2c 10 on
 					probe TOUCH_PANEL TOUCH_ELAN_I2C
 				end
@@ -280,6 +281,7 @@ chip soc/intel/alderlake
 				register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C0)"
 				register "generic.enable_delay_ms" = "1"
 				register "generic.has_power_resource" = "1"
+				register "generic.use_gpio_for_status" = "true"
 				register "hid_desc_reg_offset" = "0x01"
 				device i2c 10 on
 					probe TOUCH_PANEL TOUCH_ELAN_HID_I2C
@@ -299,6 +301,7 @@ chip soc/intel/alderlake
 				register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C0)"
 				register "generic.enable_delay_ms" = "1"
 				register "generic.has_power_resource" = "1"
+				register "generic.use_gpio_for_status" = "true"
 				register "hid_desc_reg_offset" = "0x01"
 				device i2c 15 on end
 			end
@@ -314,6 +317,7 @@ chip soc/intel/alderlake
 				register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C0)"
 				register "generic.enable_delay_ms" = "1"
 				register "generic.has_power_resource" = "1"
+				register "generic.use_gpio_for_status" = "true"
 				register "hid_desc_reg_offset" = "0x01"
 				device i2c 10 on
 					probe TOUCH_PANEL TOUCH_G2_HID_I2c
@@ -329,6 +333,7 @@ chip soc/intel/alderlake
 				register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C0)"
 				register "generic.enable_delay_ms" = "1"
 				register "generic.has_power_resource" = "1"
+				register "generic.use_gpio_for_status" = "true"
 				register "hid_desc_reg_offset" = "0x01"
 				device i2c 40 on end
 			end

From a6b2cf1531a18fbab7fab83c1e48ae430f44579d Mon Sep 17 00:00:00 2001
From: Cliff Huang <cliff.huang@intel.com>
Date: Tue, 19 Nov 2024 15:05:02 -0800
Subject: [PATCH 0544/3886] soc/intel/pantherlake: Add Touch Controller UPD and
 SoC config
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

This commit introduces the necessary changes to configure the Touch
Host Controller User Platform Data (UPD) fields such as ThcAssignment,
ThcMode, and ThcWakeOnTouch according to the specific SoC chip
configuration derived from the devicetree.

Key changes include:
- Creation of override functions to supply SoC-specific configurations
  for the Touch Host Controller (THC).
- Addition of a new SoC-specific THC header file.
- Inclusion of a motherboard (MB)-specific THC header file.
- Establishment of a build path to allow devicetree to leverage
  variant-specific defines.

BUG=none
TEST=Add CONFIG_DRIVERS_INTEL_TOUCH to fatcat board with the devicetree
changes for touchscreen and/or touchpad, as well as proper CBI settings.
Boot the board to OS and check that the THC SoC-specific info is
generated in the SSDT.

Signed-off-by: Cliff Huang <cliff.huang@intel.com>
Change-Id: I15fb62eaadc03b9a17e94609b97c686518150e2e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85199
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/soc/intel/pantherlake/Makefile.mk         |  1 +
 src/soc/intel/pantherlake/chip.h              | 15 +++++
 src/soc/intel/pantherlake/fsp_params.c        | 11 +++-
 src/soc/intel/pantherlake/include/soc/touch.h | 64 +++++++++++++++++++
 src/soc/intel/pantherlake/touch.c             | 45 +++++++++++++
 5 files changed, 134 insertions(+), 2 deletions(-)
 create mode 100644 src/soc/intel/pantherlake/include/soc/touch.h
 create mode 100644 src/soc/intel/pantherlake/touch.c

diff --git a/src/soc/intel/pantherlake/Makefile.mk b/src/soc/intel/pantherlake/Makefile.mk
index f3403b5143..e2f8dd7c6c 100644
--- a/src/soc/intel/pantherlake/Makefile.mk
+++ b/src/soc/intel/pantherlake/Makefile.mk
@@ -43,6 +43,7 @@ ramstage-y += soundwire.c
 ramstage-y += systemagent.c
 ramstage-y += tcss.c
 ramstage-y += xhci.c
+ramstage-$(CONFIG_DRIVERS_INTEL_TOUCH) += touch.c
 
 smm-y += elog.c
 smm-y += gpio.c
diff --git a/src/soc/intel/pantherlake/chip.h b/src/soc/intel/pantherlake/chip.h
index cd91e31dd0..eb702b7eca 100644
--- a/src/soc/intel/pantherlake/chip.h
+++ b/src/soc/intel/pantherlake/chip.h
@@ -26,6 +26,8 @@
 #define MAX_SAGV_POINTS 4
 #define MAX_HD_AUDIO_SDI_LINKS 2
 
+#define NUM_THC 2
+
 /* In-Band ECC Operation Mode */
 enum ibecc_mode {
 	IBECC_MODE_PER_REGION,
@@ -539,6 +541,19 @@ struct soc_intel_pantherlake_config {
 
 	uint16_t max_dram_speed_mts;
 
+	/*
+	 * Touch Host Controller Mode
+	 * Switch between Intel THC protocol and Industry standard HID protocols.
+	 * 0x0:Thc, 0x1:HID over SPI, 0x2:HID over I2C
+	 */
+	uint8_t thc_mode[NUM_THC];
+
+	/*
+	 * Touch Host Controller Wake On Touch
+	 * Based on this setting vGPIO for given THC will be in native mode, and additional _CRS
+	 * for wake will be exposed in ACPI
+	 */
+	bool thc_wake_on_touch[NUM_THC];
 };
 
 typedef struct soc_intel_pantherlake_config config_t;
diff --git a/src/soc/intel/pantherlake/fsp_params.c b/src/soc/intel/pantherlake/fsp_params.c
index 7544894b75..cac866f39a 100644
--- a/src/soc/intel/pantherlake/fsp_params.c
+++ b/src/soc/intel/pantherlake/fsp_params.c
@@ -576,8 +576,15 @@ static void fill_fsps_pmcpd_params(FSP_S_CONFIG *s_cfg,
 static void fill_fsps_thc_params(FSP_S_CONFIG *s_cfg,
 				 const struct soc_intel_pantherlake_config *config)
 {
-	s_cfg->ThcAssignment[0] = is_devfn_enabled(PCI_DEVFN_THC0) ? THC_0 : THC_NONE;
-	s_cfg->ThcAssignment[1] = is_devfn_enabled(PCI_DEVFN_THC1) ? THC_1 : THC_NONE;
+	for (size_t i = 0; i < NUM_THC; i++) {
+		if (!is_devfn_enabled(_PCI_DEVFN(THC, i))) {
+			s_cfg->ThcAssignment[i] = THC_NONE;
+			continue;
+		}
+		s_cfg->ThcAssignment[i] = THC_0 + i;
+		s_cfg->ThcMode[i] = config->thc_mode[i];
+		s_cfg->ThcWakeOnTouch[i] = config->thc_wake_on_touch[i];
+	}
 }
 
 static void fill_fsps_8254_params(FSP_S_CONFIG *s_cfg,
diff --git a/src/soc/intel/pantherlake/include/soc/touch.h b/src/soc/intel/pantherlake/include/soc/touch.h
new file mode 100644
index 0000000000..33b3d1db2e
--- /dev/null
+++ b/src/soc/intel/pantherlake/include/soc/touch.h
@@ -0,0 +1,64 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef _SOC_PANTHERLAKE_TOUCH_H_
+#define _SOC_PANTHERLAKE_TOUCH_H_
+
+/* For THC-I2C: */
+
+/*
+ * I2C Standard Mode (100Kbps):
+ * Requested Connection Speed: 186A0
+ * I2C Speed Mode: Standard (100Kbps) = 0x186A0
+ *
+ * I2C Fast Mode (400Kbps):
+ * Requested Connection Speed: 61A80
+ * I2C Speed Mode: Fast (400Kbps) = 0x612B0
+ *
+ * I2C Fast-Plus Mode (1Mbps):
+ * Requested Connection Speed: F4240
+ * I2C Speed Mode: Fast-Plus (1Mbps) = 0xF4240
+ * FM SCL HIGH Period: 34 Fast Mode (FM) CLK Signal HIGH Period
+ * FM SCL LOW Period: 3E Fast Mode (FM) CLK Signal LOW Period
+ */
+#define SOC_PTL_THC_I2C_CONNECTION_SPEED_SM   0x186a0
+#define SOC_PTL_THC_I2C_CONNECTION_SPEED_FM   0x61a80
+#define SOC_PTL_THC_I2C_CONNECTION_SPEED_FMP  0xf4240
+
+/*
+ * 0 = 7-bit Addressing Mode for HID-I2C (Default)
+ * 1 = 10-bit Addressing Mode for HID-I2C
+ */
+#define SOC_PTL_THC_I2C_ADDR_MODE                   0
+#define SOC_PTL_THC_I2C_SM_SCL_HIGH_PERIOD      0x267
+#define SOC_PTL_THC_I2C_SM_SCL_LOW_PERIOD       0x271
+#define SOC_PTL_THC_I2C_SM_SDA_HOLD_TX_PERIOD       0
+#define SOC_PTL_THC_I2C_SM_SDA_HOLD_RX_PERIOD       0
+#define SOC_PTL_THC_I2C_FM_SCL_HIGH_PERIOD       0x92
+#define SOC_PTL_THC_I2C_FM_SCL_LOW_PERIOD        0x9c
+#define SOC_PTL_THC_I2C_FM_SDA_HOLD_TX_PERIOD       0
+#define SOC_PTL_THC_I2C_FM_SDA_HOLD_RX_PERIOD       0
+#define SOC_PTL_THC_I2C_SUPPRESSED_SPIKES_S_F_FP    0
+#define SOC_PTL_THC_I2C_FMP_SCL_HIGH_PERIOD      0x34
+#define SOC_PTL_THC_I2C_FMP_SCL_LOW_PERIOD       0x3e
+#define SOC_PTL_THC_I2C_FMP_SDA_HOLD_TX_PERIOD      0
+#define SOC_PTL_THC_I2C_FMP_SDA_HOLD_RX_PERIOD      0
+#define SOC_PTL_THC_I2C_HM_SCL_HIGH_PERIOD          0
+#define SOC_PTL_THC_I2C_HM_SCL_LOW_PERIOD           0
+#define SOC_PTL_THC_I2C_HM_SDA_HOLD_TX_PERIOD       0
+#define SOC_PTL_THC_I2C_HM_SDA_HOLD_RX_PERIOD       0
+#define SOC_PTL_THC_I2C_SUPPRESSED_SPIKES_H_FP      0
+
+
+/* For THC-SPI: */
+
+/* unit: ms */
+#define SOC_PTL_THC_RST_SEQ_DLY                   300
+
+/* The initial default speed is 17000000 Hz. */
+#define SOC_PTL_THC_CONNECTION_SPEED         17000000
+
+/* 0 = no limit */
+#define SOC_PTL_THC_HIDSPI_LIMIT_PKT_SZ             0
+#define SOC_PTL_THC_PERFORMANCE_LIMIT               0
+
+#endif /* _SOC_PANTHERLAKE_TOUCH_H_ */
diff --git a/src/soc/intel/pantherlake/touch.c b/src/soc/intel/pantherlake/touch.c
new file mode 100644
index 0000000000..ed475fe837
--- /dev/null
+++ b/src/soc/intel/pantherlake/touch.c
@@ -0,0 +1,45 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <drivers/intel/touch/chip.h>
+#include <soc/touch.h>
+
+/* SoC-specific THC-I2C config */
+const struct intel_thc_hidi2c_info *soc_get_thc_hidi2c_info(void)
+{
+	static const struct intel_thc_hidi2c_info soc_thc_hidi2c_info = {
+		.connection_speed		= SOC_PTL_THC_I2C_CONNECTION_SPEED_FM,
+		.addr_mode			= SOC_PTL_THC_I2C_ADDR_MODE,
+		.sm_scl_high_period		= SOC_PTL_THC_I2C_SM_SCL_HIGH_PERIOD,
+		.sm_scl_low_period		= SOC_PTL_THC_I2C_SM_SCL_LOW_PERIOD,
+		.sm_sda_hold_tx_period		= SOC_PTL_THC_I2C_SM_SDA_HOLD_TX_PERIOD,
+		.sm_sda_hold_rx_period		= SOC_PTL_THC_I2C_SM_SDA_HOLD_RX_PERIOD,
+		.fm_scl_high_period		= SOC_PTL_THC_I2C_FM_SCL_HIGH_PERIOD,
+		.fm_scl_low_period		= SOC_PTL_THC_I2C_FM_SCL_LOW_PERIOD,
+		.fm_sda_hold_tx_period		= SOC_PTL_THC_I2C_FM_SDA_HOLD_TX_PERIOD,
+		.fm_sda_hold_rx_period		= SOC_PTL_THC_I2C_FM_SDA_HOLD_RX_PERIOD,
+		.suppressed_spikes_s_f_fp	= SOC_PTL_THC_I2C_SUPPRESSED_SPIKES_S_F_FP,
+		.fmp_scl_high_period		= SOC_PTL_THC_I2C_FMP_SCL_HIGH_PERIOD,
+		.fmp_scl_low_period		= SOC_PTL_THC_I2C_FMP_SCL_LOW_PERIOD,
+		.fmp_sda_hold_tx_period		= SOC_PTL_THC_I2C_FMP_SDA_HOLD_TX_PERIOD,
+		.fmp_sda_hold_rx_period		= SOC_PTL_THC_I2C_FMP_SDA_HOLD_RX_PERIOD,
+		.hm_scl_high_period		= SOC_PTL_THC_I2C_HM_SCL_HIGH_PERIOD,
+		.hm_scl_low_period		= SOC_PTL_THC_I2C_HM_SCL_LOW_PERIOD,
+		.hm_sda_hold_tx_period		= SOC_PTL_THC_I2C_HM_SDA_HOLD_TX_PERIOD,
+		.hm_sda_hold_rx_period		= SOC_PTL_THC_I2C_HM_SDA_HOLD_RX_PERIOD,
+		.suppressed_spikes_h_fp		= SOC_PTL_THC_I2C_SUPPRESSED_SPIKES_H_FP,
+	};
+	return &soc_thc_hidi2c_info;
+}
+
+/* SoC-specific THC-SPI config */
+const struct intel_thc_hidspi_info *soc_get_thc_hidspi_info(void)
+{
+	static const struct intel_thc_hidspi_info soc_thc_hidspi_info = {
+		.connection_speed	= SOC_PTL_THC_CONNECTION_SPEED,
+		.write_mode		= HIDSPI_WRITE_MODE_MULTI_SINGLE_SPI,
+		.limit_packet_size	= SOC_PTL_THC_HIDSPI_LIMIT_PKT_SZ,
+		.performance_limit	= SOC_PTL_THC_PERFORMANCE_LIMIT,
+		.reset_sequencing_delay	= SOC_PTL_THC_RST_SEQ_DLY,
+	};
+	return &soc_thc_hidspi_info;
+}

From 81f396ec2faefeda33b7e23d9cef380fce11a22c Mon Sep 17 00:00:00 2001
From: Momoko Hattori <momohatt@google.com>
Date: Fri, 21 Mar 2025 18:34:40 +0900
Subject: [PATCH 0545/3886] mb/google/rex: Enable use_gpio_for_status for
 touchscreen

The _STA method of touchscreen's power resource currently always returns
true. This causes the touchscreen to be powered on by the kernel in a
boot critical path (in acpi_bus_init_power) and block the boot for a
while due to the long (~300ms depending on variants) sleeps in the _ON
method of the power resource. To prevent it, enable use_gpio_for_status
so that the implementation of _STA returns the touchscreen's actual
power state and the kernel powers it on in another place that doesn't
block boot.

The similar change has already been made to mb/google/brya/var/redrix in
commit d0367e38a9e5 ("mb/google/brya/var/redrix: Enable
use_gpio_for_status for touchscreen") (CB:86749). This change applies it
to all rex variants with touchscreen.

BUG=b:397355818
TEST=Dump SSDT and check that the _STA method of touchscreen (i2c1)
     PowerResource doesn't always return true.
TEST=Check that touchscreen works with the change.
TEST=Check that kernel sleep during ACPI initialization is removed by
     checking the timestamps of 'New power resource' logs from ACPI in
     /var/log/messages.
TEST=(Tested above on karis)

Change-Id: Ibe7681884dc3edfb98c7c179b1af2063e35c4b46
Signed-off-by: Momoko Hattori <momohatt@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87001
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Sam McNally <sammc@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/google/rex/variants/kanix/overridetree.cb   | 1 +
 src/mainboard/google/rex/variants/karis/overridetree.cb   | 1 +
 src/mainboard/google/rex/variants/rex0/overridetree.cb    | 1 +
 src/mainboard/google/rex/variants/screebo/overridetree.cb | 2 ++
 4 files changed, 5 insertions(+)

diff --git a/src/mainboard/google/rex/variants/kanix/overridetree.cb b/src/mainboard/google/rex/variants/kanix/overridetree.cb
index 83663e8fbe..8f2aed31bf 100644
--- a/src/mainboard/google/rex/variants/kanix/overridetree.cb
+++ b/src/mainboard/google/rex/variants/kanix/overridetree.cb
@@ -444,6 +444,7 @@ chip soc/intel/meteorlake
 				register "generic.stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C06)"
 				register "generic.stop_off_delay_ms" = "1"
 				register "generic.has_power_resource" = "1"
+				register "generic.use_gpio_for_status" = "true"
 				register "hid_desc_reg_offset" = "0x01"
 				device i2c 0x10 on end
 			end
diff --git a/src/mainboard/google/rex/variants/karis/overridetree.cb b/src/mainboard/google/rex/variants/karis/overridetree.cb
index ea45d61981..2607ad776f 100644
--- a/src/mainboard/google/rex/variants/karis/overridetree.cb
+++ b/src/mainboard/google/rex/variants/karis/overridetree.cb
@@ -404,6 +404,7 @@ chip soc/intel/meteorlake
 				register "generic.stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C06)"
 				register "generic.stop_off_delay_ms" = "1"
 				register "generic.has_power_resource" = "1"
+				register "generic.use_gpio_for_status" = "true"
 				register "hid_desc_reg_offset" = "0x01"
 				device i2c 0x10 on end
 			end
diff --git a/src/mainboard/google/rex/variants/rex0/overridetree.cb b/src/mainboard/google/rex/variants/rex0/overridetree.cb
index 66b2bc9528..177e88781c 100644
--- a/src/mainboard/google/rex/variants/rex0/overridetree.cb
+++ b/src/mainboard/google/rex/variants/rex0/overridetree.cb
@@ -579,6 +579,7 @@ chip soc/intel/meteorlake
 				register "generic.stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C06)"
 				register "generic.stop_off_delay_ms" = "2"
 				register "generic.has_power_resource" = "1"
+				register "generic.use_gpio_for_status" = "true"
 				register "hid_desc_reg_offset" = "0x01"
 				device i2c 10 on
 					probe TOUCHSCREEN TOUCHSCREEN_I2C
diff --git a/src/mainboard/google/rex/variants/screebo/overridetree.cb b/src/mainboard/google/rex/variants/screebo/overridetree.cb
index d46d7c91ef..6e8f5fc028 100644
--- a/src/mainboard/google/rex/variants/screebo/overridetree.cb
+++ b/src/mainboard/google/rex/variants/screebo/overridetree.cb
@@ -451,6 +451,7 @@ chip soc/intel/meteorlake
 				register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B17)"
 				register "generic.enable_delay_ms" = "12"
 				register "generic.has_power_resource" = "1"
+				register "generic.use_gpio_for_status" = "true"
 				register "hid_desc_reg_offset" = "0x01"
 				device i2c 41 on
 					probe TOUCHSCREEN TOUCHSCREEN_ILITEK
@@ -467,6 +468,7 @@ chip soc/intel/meteorlake
 				register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B17)"
 				register "generic.enable_delay_ms" = "1"
 				register "generic.has_power_resource" = "1"
+				register "generic.use_gpio_for_status" = "true"
 				register "hid_desc_reg_offset" = "0x01"
 				device i2c 10 on
 					probe TOUCHSCREEN TOUCHSCREEN_ELAN

From 9faec116caa6f79121833b9e2c353fe987fd9811 Mon Sep 17 00:00:00 2001
From: Yidi Lin <yidilin@chromium.org>
Date: Fri, 28 Mar 2025 14:43:11 +0800
Subject: [PATCH 0546/3886] MAINTAINERS: Add google/skywalker to GOOGLE
 MEDIATEK-BASED MAINBOARDS

Change-Id: I234dfc2a64be88e274af57ea489d5775347ac913
Signed-off-by: Yidi Lin <yidilin@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87040
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
---
 MAINTAINERS | 1 +
 1 file changed, 1 insertion(+)

diff --git a/MAINTAINERS b/MAINTAINERS
index d180142cfa..a786879b2e 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -408,6 +408,7 @@ F:	src/mainboard/google/geralt/
 F:	src/mainboard/google/kukui/
 F:	src/mainboard/google/oak/
 F:	src/mainboard/google/rauru/
+F:	src/mainboard/google/skywalker/
 
 
 

From af1f198678d92290d52f9fc9a621978daf4a748c Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Tue, 1 Apr 2025 10:40:10 -0500
Subject: [PATCH 0547/3886] mb/starlabs/byte_adl/cfr: Drop CONFIG guards for
 CFR elements

The byte_adl is an Alderlake board, so we don't need to do any SoC
checks to determine which CFR elements to include.

TEST=build/boot starlabs/byte_adl, verify CFR options unchanged.

Change-Id: Ie21a873ad7af1504f46db769c3abba00c0e61008
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87067
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/starlabs/byte_adl/cfr.c | 8 --------
 1 file changed, 8 deletions(-)

diff --git a/src/mainboard/starlabs/byte_adl/cfr.c b/src/mainboard/starlabs/byte_adl/cfr.c
index 81d74b94dd..442326f41c 100644
--- a/src/mainboard/starlabs/byte_adl/cfr.c
+++ b/src/mainboard/starlabs/byte_adl/cfr.c
@@ -38,14 +38,12 @@ static const struct sm_object debug_level = SM_DECLARE_ENUM({
 				SM_ENUM_VALUE_END			},
 });
 
-#if CONFIG(SOC_INTEL_TIGERLAKE) || CONFIG(SOC_INTEL_ALDERLAKE) || CONFIG(SOC_INTEL_RAPTORLAKE)
 static const struct sm_object gna = SM_DECLARE_BOOL({
 	.opt_name	= "gna",
 	.ui_name	= "Gaussian & Neural Accelerator",
 	.ui_helptext	= "Enable or Disable the Gaussian & Neural Accelerator",
 	.default_value	= false,
 });
-#endif
 
 static const struct sm_object me_state = SM_DECLARE_ENUM({
 	.opt_name	= "me_state",
@@ -84,7 +82,6 @@ static const struct sm_object power_profile = SM_DECLARE_ENUM({
 				SM_ENUM_VALUE_END			},
 });
 
-#if CONFIG(SOC_INTEL_ALDERLAKE)
 static const struct sm_object pciexp_aspm = SM_DECLARE_ENUM({
 	.opt_name	= "pciexp_aspm",
 	.ui_name	= "PCI ASPM",
@@ -124,7 +121,6 @@ static const struct sm_object pciexp_l1ss = SM_DECLARE_ENUM({
 				{ "L1.2",		L1_SS_L1_2	},
 				SM_ENUM_VALUE_END			},
 });
-#endif
 
 static const struct sm_object reboot_counter = SM_DECLARE_NUMBER({
 	.opt_name	= "reboot_counter",
@@ -169,9 +165,7 @@ static struct sm_obj_form power = {
 static struct sm_obj_form devices = {
 	.ui_name = "Devices",
 	.obj_list = (const struct sm_object *[]) {
-		#if CONFIG(SOC_INTEL_TIGERLAKE) || CONFIG(SOC_INTEL_ALDERLAKE) || CONFIG(SOC_INTEL_RAPTORLAKE)
 		&gna,
-		#endif
 		NULL
 	},
 };
@@ -179,11 +173,9 @@ static struct sm_obj_form devices = {
 static struct sm_obj_form pci = {
 	.ui_name = "PCI",
 	.obj_list = (const struct sm_object *[]) {
-		#if CONFIG(SOC_INTEL_ALDERLAKE)
 		&pciexp_clk_pm,
 		&pciexp_aspm,
 		&pciexp_l1ss,
-		#endif
 		NULL
 	},
 };

From 3e0de0de8308f6434bbfb8bd2ccd24dffb3c55e5 Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Tue, 1 Apr 2025 21:08:08 +0100
Subject: [PATCH 0548/3886] mb/starlabs/starbook/adl_n: Tidy GPIO comments for
 debug connector

This is a non-functional change, and only makes the GPIOs easier to read.

Change-Id: I1284e9947edca20d113ca2e810963fcfffb92831
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87069
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/starlabs/starbook/variants/adl_n/gpio.c | 7 +++----
 1 file changed, 3 insertions(+), 4 deletions(-)

diff --git a/src/mainboard/starlabs/starbook/variants/adl_n/gpio.c b/src/mainboard/starlabs/starbook/variants/adl_n/gpio.c
index 11cab703e7..5f98b2b28a 100644
--- a/src/mainboard/starlabs/starbook/variants/adl_n/gpio.c
+++ b/src/mainboard/starlabs/starbook/variants/adl_n/gpio.c
@@ -4,10 +4,9 @@
 
 /* Early pad configuration in bootblock */
 const struct pad_config early_gpio_table[] = {
-	/* H10:		UART0 RXD		Debug Connector		*/
-	PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2),
-	/* H11:		UART0 TXD		Debug Connector		*/
-	PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2),
+	/* Debug Connector */
+	PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2),				/* RXD */
+	PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2),				/* TXD */
 };
 
 const struct pad_config *variant_early_gpio_table(size_t *num)

From d476f72b75eaaea4ebace35f3b612f76d46b53fa Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Tue, 1 Apr 2025 21:11:18 +0100
Subject: [PATCH 0549/3886] mb/starlabs/starbook/adl_n: Tidy GPIO comments for
 deep GPIOs

This is a non-functional change, and only makes the GPIOs easier to read.

Change-Id: Ic69920c052707a44ecdd44c5879bbbf612cc03f8
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87070
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
---
 .../starlabs/starbook/variants/adl_n/gpio.c   | 25 ++++++-------------
 1 file changed, 8 insertions(+), 17 deletions(-)

diff --git a/src/mainboard/starlabs/starbook/variants/adl_n/gpio.c b/src/mainboard/starlabs/starbook/variants/adl_n/gpio.c
index 5f98b2b28a..705f6ee691 100644
--- a/src/mainboard/starlabs/starbook/variants/adl_n/gpio.c
+++ b/src/mainboard/starlabs/starbook/variants/adl_n/gpio.c
@@ -17,29 +17,20 @@ const struct pad_config *variant_early_gpio_table(size_t *num)
 
 /* Pad configuration in ramstage. */
 const struct pad_config gpio_table[] = {
-	/* GPD0:	Battery Low					*/
-	PAD_CFG_NF(GPD0, NONE, DEEP, NF1),
-	/* GPD1:	Charger Connected				*/
-	PAD_CFG_NF(GPD1, NONE, DEEP, NF1),
-	/* GPD2:	LAN Wake					*/
+	/* General Purpose I/O Deep */
+	PAD_CFG_NF(GPD0, NONE, DEEP, NF1),				/* Battery Low */
+	PAD_CFG_NF(GPD1, NONE, DEEP, NF1),				/* Charger Connected */
+	PAD_CFG_NF(GPD3, UP_20K, DEEP, NF1),				/* Power Button */
+	PAD_CFG_NF(GPD4, NONE, DEEP, NF1),				/* Sleep S3 */
+	PAD_CFG_NF(GPD5, NONE, DEEP, NF1),				/* Sleep S4 */
+	PAD_CFG_NF(GPD8, NONE, DEEP, NF1),				/* Bluetooth Suspend */
+
 	PAD_NC(GPD2, NONE),
-	/* GPD3:	Power Button					*/
-	PAD_CFG_NF(GPD3, UP_20K, DEEP, NF1),
-	/* GPD4:	Sleep S3					*/
-	PAD_CFG_NF(GPD4, NONE, DEEP, NF1),
-	/* GPD5:	Sleep S4					*/
-	PAD_CFG_NF(GPD5, NONE, DEEP, NF1),
-	/* GPD6:	Sleep A						*/
 	PAD_NC(GPD6, NONE),
 	/* GPD7:	Power Adapter Disable				*/
 	PAD_CFG_GPO(GPD7, 0, PWROK),
-	/* GPD8:	Suspend Clock					*/
-	PAD_CFG_NF(GPD8, NONE, DEEP, NF1),
-	/* GPD9:	Wireless LAN Sleep				*/
 	PAD_NC(GPD9, NONE),
-	/* GPD10:	Sleep S5					*/
 	PAD_NC(GPD10, NONE),
-	/* GPD11:	LAN PHY Enable					*/
 	PAD_NC(GPD11, NONE),
 
 	/* A0:		ESPI IO 0					*/

From 26484b0b6333de074aa57bf8e8dec09f050558e0 Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Tue, 1 Apr 2025 21:12:07 +0100
Subject: [PATCH 0550/3886] mb/starlabs/starbook/adl_n: Tidy GPIO comments for
 eSPI

This is a non-functional change, and only makes the GPIOs easier to read.

Change-Id: I8cf7342e6442d283c5ba4b7ee545aa8ac524e365
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87071
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 .../starlabs/starbook/variants/adl_n/gpio.c      | 16 +++++++++-------
 1 file changed, 9 insertions(+), 7 deletions(-)

diff --git a/src/mainboard/starlabs/starbook/variants/adl_n/gpio.c b/src/mainboard/starlabs/starbook/variants/adl_n/gpio.c
index 705f6ee691..3994818f55 100644
--- a/src/mainboard/starlabs/starbook/variants/adl_n/gpio.c
+++ b/src/mainboard/starlabs/starbook/variants/adl_n/gpio.c
@@ -25,6 +25,15 @@ const struct pad_config gpio_table[] = {
 	PAD_CFG_NF(GPD5, NONE, DEEP, NF1),				/* Sleep S4 */
 	PAD_CFG_NF(GPD8, NONE, DEEP, NF1),				/* Bluetooth Suspend */
 
+	/* eSPI */
+	// PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_A0, UP_20K, DEEP, NF1),	/* eSPI IO 0 */
+	// PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_A1, UP_20K, DEEP, NF1),	/* eSPI IO 1 */
+	// PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_A2, UP_20K, DEEP, NF1),	/* eSPI IO 2 */
+	// PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_A3, UP_20K, DEEP, NF1),	/* eSPI IO 3 */
+	// PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_A4, UP_20K, DEEP, NF1),	/* eSPI CS 0 */
+	// PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_A9, UP_20K, DEEP, NF1),	/* eSPI Clk */
+	// PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_A10, NONE, DEEP, NF1),	/* eSPI Reset */
+
 	PAD_NC(GPD2, NONE),
 	PAD_NC(GPD6, NONE),
 	/* GPD7:	Power Adapter Disable				*/
@@ -33,11 +42,6 @@ const struct pad_config gpio_table[] = {
 	PAD_NC(GPD10, NONE),
 	PAD_NC(GPD11, NONE),
 
-	/* A0:		ESPI IO 0					*/
-	/* A1:		ESPI IO 1					*/
-	/* A2:		ESPI IO 2					*/
-	/* A3:		ESPI IO 3					*/
-	/* A4:		ESPI CS 0					*/
 	/* A5:		Not Connected					*/
 	PAD_NC(GPP_A5, NONE),
 	/* A6:		Not Connected					*/
@@ -46,8 +50,6 @@ const struct pad_config gpio_table[] = {
 	PAD_NC(GPP_A7, NONE),
 	/* A8:		Not Connected					*/
 	PAD_NC(GPP_A8, NONE),
-	/* A9:		ESPI Clock					*/
-	/* A10:		ESPI Reset					*/
 	/* A11:		Not Connected					*/
 	PAD_NC(GPP_A11, NONE),
 	/* A12:		Not Connected					*/

From c98d58ac8364e9a9d546b4a667ea05bde8610c69 Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Tue, 1 Apr 2025 21:12:59 +0100
Subject: [PATCH 0551/3886] mb/starlabs/starbook/adl_n: Tidy GPIO comments for
 the touchpad

This is a non-functional change, and only makes the GPIOs easier to read.

Change-Id: I65d055955c0abf04b597e6972ef95f5c2983563e
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87072
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/starlabs/starbook/variants/adl_n/gpio.c | 11 +++++------
 1 file changed, 5 insertions(+), 6 deletions(-)

diff --git a/src/mainboard/starlabs/starbook/variants/adl_n/gpio.c b/src/mainboard/starlabs/starbook/variants/adl_n/gpio.c
index 3994818f55..f89cabc666 100644
--- a/src/mainboard/starlabs/starbook/variants/adl_n/gpio.c
+++ b/src/mainboard/starlabs/starbook/variants/adl_n/gpio.c
@@ -34,6 +34,11 @@ const struct pad_config gpio_table[] = {
 	// PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_A9, UP_20K, DEEP, NF1),	/* eSPI Clk */
 	// PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_A10, NONE, DEEP, NF1),	/* eSPI Reset */
 
+	/* Touchpad */
+	PAD_CFG_NF(GPP_B7, NONE, DEEP, NF2),				/* Data */
+	PAD_CFG_NF(GPP_B8, NONE, DEEP, NF2),				/* Clock */
+	PAD_CFG_GPI_APIC_LOW(GPP_E12, NONE, PLTRST),			/* Interrupt */
+
 	PAD_NC(GPD2, NONE),
 	PAD_NC(GPD6, NONE),
 	/* GPD7:	Power Adapter Disable				*/
@@ -91,10 +96,6 @@ const struct pad_config gpio_table[] = {
 	PAD_NC(GPP_B5, NONE),
 	/* B6:		I2C 2 SCL		Touch Panel Clock	*/
 	PAD_NC(GPP_B6, NONE),
-	/* B7:		I2C 3 SDA		Test Point 15		*/
-	PAD_CFG_NF(GPP_B7, NONE, DEEP, NF2),
-	/* B8:		I2C 3 SCL		Test Point 16		*/
-	PAD_CFG_NF(GPP_B8, NONE, DEEP, NF2),
 	/* B9:		Not Connected					*/
 	PAD_NC(GPP_B9, NONE),
 	/* B10:		Not Connected					*/
@@ -254,8 +255,6 @@ const struct pad_config gpio_table[] = {
 	PAD_NC(GPP_E10, NONE),
 	/* E11:		TPM IRQ						*/
 	PAD_CFG_GPI_APIC_LOW(GPP_E11, NONE, PLTRST),
-	/* E12:		Touchpad Interrupt				*/
-	PAD_CFG_GPI_APIC_LOW(GPP_E12, NONE, PLTRST),
 	/* E13:		Not connected					*/
 	PAD_NC(GPP_E13, NONE),
 	/* E14:		EDP HPD						*/

From ec87f050991290371e82001151aa41811d1aba77 Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Tue, 1 Apr 2025 21:14:32 +0100
Subject: [PATCH 0552/3886] mb/starlabs/starbook/adl_n: Tidy GPIO comments for
 the SSD

This is a non-functional change, and only makes the GPIOs easier to read.

Change-Id: Ief80e0527c9e1bfdc31ce9a28fb0bd997ba4493e
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87073
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
---
 src/mainboard/starlabs/starbook/variants/adl_n/gpio.c | 11 +++++------
 1 file changed, 5 insertions(+), 6 deletions(-)

diff --git a/src/mainboard/starlabs/starbook/variants/adl_n/gpio.c b/src/mainboard/starlabs/starbook/variants/adl_n/gpio.c
index f89cabc666..7cf23e8d4a 100644
--- a/src/mainboard/starlabs/starbook/variants/adl_n/gpio.c
+++ b/src/mainboard/starlabs/starbook/variants/adl_n/gpio.c
@@ -39,6 +39,11 @@ const struct pad_config gpio_table[] = {
 	PAD_CFG_NF(GPP_B8, NONE, DEEP, NF2),				/* Clock */
 	PAD_CFG_GPI_APIC_LOW(GPP_E12, NONE, PLTRST),			/* Interrupt */
 
+	/* SSD */
+	PAD_CFG_NF(GPP_D5, NONE, DEEP, NF1),				/* Clock Request 0 */
+	PAD_CFG_GPO(GPP_H0, 1, PLTRST),					/* Reset */
+	PAD_CFG_GPO(GPP_D16, 1, DEEP),					/* Enable */
+
 	PAD_NC(GPD2, NONE),
 	PAD_NC(GPD6, NONE),
 	/* GPD7:	Power Adapter Disable				*/
@@ -198,8 +203,6 @@ const struct pad_config gpio_table[] = {
 	PAD_NC(GPP_D3, NONE),
 	/* D4:		Not Connected					*/
 	PAD_NC(GPP_D4, NONE),
-	/* D5:		Clock Request 0		PCH M.2 SSD		*/
-	PAD_CFG_NF(GPP_D5, NONE, DEEP, NF1),
 	/* D6:		Clock Request 1		Wireless LAN		*/
 	PAD_CFG_NF(GPP_D6, NONE, DEEP, NF1),
 	/* D7:		Clock Request 2					*/
@@ -220,8 +223,6 @@ const struct pad_config gpio_table[] = {
 	PAD_NC(GPP_D14, NONE),
 	/* D15:		Not Connected					*/
 	PAD_NC(GPP_D15, NONE),
-	/* D16:		PCH M.2 SSD Power Enable			*/
-	PAD_CFG_GPO(GPP_D16, 1, DEEP),
 	/* D17:		Not used		Fingerprint ID		*/
 	PAD_NC(GPP_D17, NONE),
 	/* D18:		Not Connected					*/
@@ -329,8 +330,6 @@ const struct pad_config gpio_table[] = {
 	/* F23:		Not Connected					*/
 	PAD_NC(GPP_F23, NONE),
 
-	/* H0:		PCH M.2 SSD Reset				*/
-	PAD_CFG_GPO(GPP_H0, 1, PLTRST),
 	/* H1:		BFX Strap 2 Bit 3	Weak Internal PD 20K	*/
 	PAD_CFG_GPO(GPP_H1, 0, DEEP),
 	/* H2:		Wireless LAN Reset				*/

From 087acda5ce8e485028316546cd144247c1e44aa4 Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Tue, 1 Apr 2025 21:15:29 +0100
Subject: [PATCH 0553/3886] mb/starlabs/starbook/adl_n: Tidy GPIO comments for
 the wireless

This is a non-functional change, and only makes the GPIOs easier to read.

Change-Id: Ie93658cc4f8f17be1ff59244c038f53095751be7
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87074
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 .../starlabs/starbook/variants/adl_n/gpio.c        | 14 ++++++--------
 1 file changed, 6 insertions(+), 8 deletions(-)

diff --git a/src/mainboard/starlabs/starbook/variants/adl_n/gpio.c b/src/mainboard/starlabs/starbook/variants/adl_n/gpio.c
index 7cf23e8d4a..43ef9f23ab 100644
--- a/src/mainboard/starlabs/starbook/variants/adl_n/gpio.c
+++ b/src/mainboard/starlabs/starbook/variants/adl_n/gpio.c
@@ -44,6 +44,12 @@ const struct pad_config gpio_table[] = {
 	PAD_CFG_GPO(GPP_H0, 1, PLTRST),					/* Reset */
 	PAD_CFG_GPO(GPP_D16, 1, DEEP),					/* Enable */
 
+	/* Wireless */
+	PAD_CFG_NF(GPP_D6, NONE, DEEP, NF1),				/* Clock Request 1 */
+	PAD_CFG_GPO(GPP_H2, 1, PLTRST),					/* Reset */
+	PAD_CFG_GPO(GPP_E3, 1, DEEP),					/* WiFi RF Kill */
+	PAD_CFG_GPO(GPP_A13, 1, DEEP),					/* Bluetooth RF Kill */
+
 	PAD_NC(GPD2, NONE),
 	PAD_NC(GPD6, NONE),
 	/* GPD7:	Power Adapter Disable				*/
@@ -64,8 +70,6 @@ const struct pad_config gpio_table[] = {
 	PAD_NC(GPP_A11, NONE),
 	/* A12:		Not Connected					*/
 	PAD_NC(GPP_A12, NONE),
-	/* A13:		BlueTooth RF Kill				*/
-	PAD_CFG_GPO(GPP_A13, 1, DEEP),
 	/* A14:		Test Point 45					*/
 	PAD_NC(GPP_A14, NONE),
 	/* A15:		Test Point 52					*/
@@ -203,8 +207,6 @@ const struct pad_config gpio_table[] = {
 	PAD_NC(GPP_D3, NONE),
 	/* D4:		Not Connected					*/
 	PAD_NC(GPP_D4, NONE),
-	/* D6:		Clock Request 1		Wireless LAN		*/
-	PAD_CFG_NF(GPP_D6, NONE, DEEP, NF1),
 	/* D7:		Clock Request 2					*/
 	PAD_NC(GPP_D7, NONE),
 	/* D8:		Clock Request 3					*/
@@ -236,8 +238,6 @@ const struct pad_config gpio_table[] = {
 	PAD_NC(GPP_E1, NONE),
 	/* E2:		Not Connected					*/
 	PAD_NC(GPP_E2, NONE),
-	/* E3:		WiFi RF Kill					*/
-	PAD_CFG_GPO(GPP_E3, 1, DEEP),
 	/* E4:		Test Point 14					*/
 	PAD_NC(GPP_E4, NONE),
 	/* E5:		Not Connected					*/
@@ -332,8 +332,6 @@ const struct pad_config gpio_table[] = {
 
 	/* H1:		BFX Strap 2 Bit 3	Weak Internal PD 20K	*/
 	PAD_CFG_GPO(GPP_H1, 0, DEEP),
-	/* H2:		Wireless LAN Reset				*/
-	PAD_CFG_GPO(GPP_H2, 1, PLTRST),
 	/* H3:		Not Connected					*/
 	PAD_NC(GPP_H3, NONE),
 	/* H4:		I2C 0 SDA		Touchpad		*/

From e94c2459d5f8d9a5ff19cb1a807affc9bb00c8b2 Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Tue, 1 Apr 2025 21:17:05 +0100
Subject: [PATCH 0554/3886] mb/starlabs/starbook/adl_n: Tidy GPIO comments for
 display outputs

This is a non-functional change, and only makes the GPIOs easier to read.

Change-Id: Iaac4672fec3e282ffc3ea6acf07cfb56072ad850
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87075
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 .../starlabs/starbook/variants/adl_n/gpio.c     | 17 +++++++----------
 1 file changed, 7 insertions(+), 10 deletions(-)

diff --git a/src/mainboard/starlabs/starbook/variants/adl_n/gpio.c b/src/mainboard/starlabs/starbook/variants/adl_n/gpio.c
index 43ef9f23ab..2bcc4acc94 100644
--- a/src/mainboard/starlabs/starbook/variants/adl_n/gpio.c
+++ b/src/mainboard/starlabs/starbook/variants/adl_n/gpio.c
@@ -50,6 +50,13 @@ const struct pad_config gpio_table[] = {
 	PAD_CFG_GPO(GPP_E3, 1, DEEP),					/* WiFi RF Kill */
 	PAD_CFG_GPO(GPP_A13, 1, DEEP),					/* Bluetooth RF Kill */
 
+	/* Display */
+	PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1),				/* eDP Hot Plug */
+	PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1),				/* HDMI Hot Plug */
+	PAD_CFG_NF(GPP_H15, NONE, DEEP, NF1),				/* HDMI Clock */
+	PAD_CFG_NF(GPP_H17, NONE, DEEP, NF1),				/* HDMI Data */
+	PAD_CFG_NF(GPP_A19, NONE, DEEP, NF1),				/* TCP0 Hot Plug */
+
 	PAD_NC(GPD2, NONE),
 	PAD_NC(GPD6, NONE),
 	/* GPD7:	Power Adapter Disable				*/
@@ -78,10 +85,6 @@ const struct pad_config gpio_table[] = {
 	PAD_NC(GPP_A16, NONE),
 	/* A17:		Not Connected					*/
 	PAD_NC(GPP_A17, NONE),
-	/* A18:		DDI B DP HPD					*/
-	PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1),
-	/* A19:		TCP0 HPD					*/
-	PAD_CFG_NF(GPP_A19, NONE, DEEP, NF1),
 	/* A20:		Test Point 44					*/
 	PAD_NC(GPP_A20, NONE),
 	/* A21:		Fingerprint Reader Interrupt			*/
@@ -258,8 +261,6 @@ const struct pad_config gpio_table[] = {
 	PAD_CFG_GPI_APIC_LOW(GPP_E11, NONE, PLTRST),
 	/* E13:		Not connected					*/
 	PAD_NC(GPP_E13, NONE),
-	/* E14:		EDP HPD						*/
-	PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1),
 	/* E15:		Not Connected					*/
 	PAD_NC(GPP_E15, NONE),
 	/* E16:		Not Connected					*/
@@ -352,12 +353,8 @@ const struct pad_config gpio_table[] = {
 	PAD_NC(GPP_H13, NONE),
 	/* H14:		Not Connected					*/
 	PAD_NC(GPP_H14, NONE),
-	/* H15:		DDPB Control Clock				*/
-	PAD_CFG_NF(GPP_H15, NONE, DEEP, NF1),
 	/* H16:		Not Connected					*/
 	PAD_NC(GPP_H16, NONE),
-	/* H17:		DDPB Control Data				*/
-	PAD_CFG_NF(GPP_H17, NONE, DEEP, NF1),
 	/* H18:		CPI C10 Gate					*/
 	PAD_CFG_NF(GPP_H18, NONE, DEEP, NF1),
 	/* H19:		Clock Request 4		CPU M.2 SSD		*/

From 41a99f014ed8fd0113af6729a5da7c45dd2daac6 Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Tue, 1 Apr 2025 21:17:49 +0100
Subject: [PATCH 0555/3886] mb/starlabs/starbook/adl_n: Tidy GPIO comments for
 HDA

This is a non-functional change, and only makes the GPIOs easier to read.

Change-Id: Ib40431a24037535e7c4d1bc49a5ae50576b62e33
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87076
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 .../starlabs/starbook/variants/adl_n/gpio.c    | 18 +++++++-----------
 1 file changed, 7 insertions(+), 11 deletions(-)

diff --git a/src/mainboard/starlabs/starbook/variants/adl_n/gpio.c b/src/mainboard/starlabs/starbook/variants/adl_n/gpio.c
index 2bcc4acc94..4fdabc5be4 100644
--- a/src/mainboard/starlabs/starbook/variants/adl_n/gpio.c
+++ b/src/mainboard/starlabs/starbook/variants/adl_n/gpio.c
@@ -57,6 +57,13 @@ const struct pad_config gpio_table[] = {
 	PAD_CFG_NF(GPP_H17, NONE, DEEP, NF1),				/* HDMI Data */
 	PAD_CFG_NF(GPP_A19, NONE, DEEP, NF1),				/* TCP0 Hot Plug */
 
+	/* High-Definition Audio */
+	PAD_CFG_NF(GPP_R0, NATIVE, DEEP, NF1),				/* Clock */
+	PAD_CFG_NF(GPP_R1, NATIVE, DEEP, NF1),				/* Sync */
+	PAD_CFG_NF(GPP_R2, NATIVE, DEEP, NF1),				/* Data Output */
+	PAD_CFG_NF(GPP_R3, NATIVE, DEEP, NF1),				/* Data Input */
+	PAD_CFG_NF(GPP_R4, NATIVE, DEEP, NF1),				/* Reset */
+
 	PAD_NC(GPD2, NONE),
 	PAD_NC(GPD6, NONE),
 	/* GPD7:	Power Adapter Disable				*/
@@ -418,17 +425,6 @@ const struct pad_config gpio_table[] = {
 	/* T15:		 Not Connected					*/
 	PAD_NC(GPP_T15, NONE),
 
-	/* R0:		HDA BCLK					*/
-	PAD_CFG_NF(GPP_R0, NATIVE, DEEP, NF1),
-	/* R1:		HDA SYNC					*/
-	PAD_CFG_NF(GPP_R1, NATIVE, DEEP, NF1),
-	/* R2:		HDA SDO						*/
-	PAD_CFG_NF(GPP_R2, NATIVE, DEEP, NF1),
-	/* R3:		HDA SDI						*/
-	PAD_CFG_NF(GPP_R3, NATIVE, DEEP, NF1),
-	/* R4:		HDA Reset					*/
-	PAD_CFG_NF(GPP_R4, NATIVE, DEEP, NF1),
-	/* R5:		MiPi Cam Reset					*/
 	PAD_NC(GPP_R5, NONE),
 	/* R6:		Not Connected					*/
 	PAD_NC(GPP_R6, NONE),

From bd07bb450af776a84715e24c846182c5b16ab9c9 Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Tue, 1 Apr 2025 21:20:16 +0100
Subject: [PATCH 0556/3886] mb/starlabs/starbook/adl_n: Tidy GPIO comments for
 PCH

This is a non-functional change, and only makes the GPIOs easier to read.

Change-Id: I710f3ab84a4c6d76941a2a7dc3d41f87ba0c0415
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87077
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
---
 .../starlabs/starbook/variants/adl_n/gpio.c    | 18 ++++++++----------
 1 file changed, 8 insertions(+), 10 deletions(-)

diff --git a/src/mainboard/starlabs/starbook/variants/adl_n/gpio.c b/src/mainboard/starlabs/starbook/variants/adl_n/gpio.c
index 4fdabc5be4..782538a293 100644
--- a/src/mainboard/starlabs/starbook/variants/adl_n/gpio.c
+++ b/src/mainboard/starlabs/starbook/variants/adl_n/gpio.c
@@ -64,6 +64,13 @@ const struct pad_config gpio_table[] = {
 	PAD_CFG_NF(GPP_R3, NATIVE, DEEP, NF1),				/* Data Input */
 	PAD_CFG_NF(GPP_R4, NATIVE, DEEP, NF1),				/* Reset */
 
+	/* PCH */
+	PAD_CFG_NF(GPP_H18, NONE, DEEP, NF1),				/* C10 Gate */
+	PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1),				/* Platform Reset */
+	PAD_CFG_NF(GPP_B0, NONE, DEEP, NF1),				/* Vendor ID 0 */
+	PAD_CFG_NF(GPP_B1, NONE, DEEP, NF1),				/* Vendor ID 1 */
+	PAD_CFG_GPI_SCI(GPP_B2, NONE, PLTRST, EDGE_SINGLE, INVERT),	/* Processor Hot */
+
 	PAD_NC(GPD2, NONE),
 	PAD_NC(GPD6, NONE),
 	/* GPD7:	Power Adapter Disable				*/
@@ -101,12 +108,7 @@ const struct pad_config gpio_table[] = {
 	/* A23:		Not Connected					*/
 	PAD_NC(GPP_A23, NONE),
 
-	/* B0:		Core Vendor ID 0				*/
-	PAD_CFG_NF(GPP_B0, NONE, DEEP, NF1),
-	/* B1:		Core Vendor ID 1				*/
-	PAD_CFG_NF(GPP_B1, NONE, DEEP, NF1),
-	/* B2:		BC PROCHOT					*/
-	PAD_CFG_GPI_SCI(GPP_B2, NONE, PLTRST, EDGE_SINGLE, INVERT),
+
 	/* B3:		Not Connected					*/
 	PAD_NC(GPP_B3, NONE),
 	/* B4:		Not Connected					*/
@@ -123,8 +125,6 @@ const struct pad_config gpio_table[] = {
 	PAD_NC(GPP_B11, NONE),
 	/* B12:		PM SLP S0					*/
 	PAD_NC(GPP_B12, NONE),
-	/* B13:		PLT RST						*/
-	PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1),
 	/* B14:		Top Swap Override	Weak Internal PD 20K
 				High:	Enabled
 				Low:	Disabled			*/
@@ -362,8 +362,6 @@ const struct pad_config gpio_table[] = {
 	PAD_NC(GPP_H14, NONE),
 	/* H16:		Not Connected					*/
 	PAD_NC(GPP_H16, NONE),
-	/* H18:		CPI C10 Gate					*/
-	PAD_CFG_NF(GPP_H18, NONE, DEEP, NF1),
 	/* H19:		Clock Request 4		CPU M.2 SSD		*/
 	PAD_NC(GPP_H19, NONE),
 	/* H20:		Not Connected					*/

From b2e832748049c1f3c7ddb14d4dea606c6731dbd9 Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Tue, 1 Apr 2025 21:20:58 +0100
Subject: [PATCH 0557/3886] mb/starlabs/starbook/adl_n: Tidy GPIO comments for
 the TPM

This is a non-functional change, and only makes the GPIOs easier to read.

Change-Id: I147d0b9770c6a1d10b4e8996591508a42805a18c
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87078
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
---
 src/mainboard/starlabs/starbook/variants/adl_n/gpio.c | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/src/mainboard/starlabs/starbook/variants/adl_n/gpio.c b/src/mainboard/starlabs/starbook/variants/adl_n/gpio.c
index 782538a293..514d2d84c7 100644
--- a/src/mainboard/starlabs/starbook/variants/adl_n/gpio.c
+++ b/src/mainboard/starlabs/starbook/variants/adl_n/gpio.c
@@ -71,6 +71,9 @@ const struct pad_config gpio_table[] = {
 	PAD_CFG_NF(GPP_B1, NONE, DEEP, NF1),				/* Vendor ID 1 */
 	PAD_CFG_GPI_SCI(GPP_B2, NONE, PLTRST, EDGE_SINGLE, INVERT),	/* Processor Hot */
 
+	/* TPM */
+	PAD_CFG_GPI_APIC_LOW(GPP_E11, NONE, PLTRST),			/* Interrupt */
+
 	PAD_NC(GPD2, NONE),
 	PAD_NC(GPD6, NONE),
 	/* GPD7:	Power Adapter Disable				*/
@@ -264,8 +267,6 @@ const struct pad_config gpio_table[] = {
 	PAD_NC(GPP_E9, NONE),
 	/* E10:		PWD Amplifier Input				*/
 	PAD_NC(GPP_E10, NONE),
-	/* E11:		TPM IRQ						*/
-	PAD_CFG_GPI_APIC_LOW(GPP_E11, NONE, PLTRST),
 	/* E13:		Not connected					*/
 	PAD_NC(GPP_E13, NONE),
 	/* E15:		Not Connected					*/

From 070447049a9f5ac06781cf8e924e75ec30e43790 Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Tue, 1 Apr 2025 21:21:39 +0100
Subject: [PATCH 0558/3886] mb/starlabs/starbook/adl_n: Tidy GPIO comments for
 the SMBUS

This is a non-functional change, and only makes the GPIOs easier to read.

Change-Id: I8456c5fa72d0c8620469e9c9ea260c60100db40e
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87079
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/starlabs/starbook/variants/adl_n/gpio.c | 11 +++++------
 1 file changed, 5 insertions(+), 6 deletions(-)

diff --git a/src/mainboard/starlabs/starbook/variants/adl_n/gpio.c b/src/mainboard/starlabs/starbook/variants/adl_n/gpio.c
index 514d2d84c7..e7a68c2758 100644
--- a/src/mainboard/starlabs/starbook/variants/adl_n/gpio.c
+++ b/src/mainboard/starlabs/starbook/variants/adl_n/gpio.c
@@ -74,6 +74,11 @@ const struct pad_config gpio_table[] = {
 	/* TPM */
 	PAD_CFG_GPI_APIC_LOW(GPP_E11, NONE, PLTRST),			/* Interrupt */
 
+	/* SMBus */
+	PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1),				/* Clock */
+	PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1),				/* Data */
+	PAD_CFG_GPO(GPP_E8, 1, DEEP),					/* DRAM Sleep */
+
 	PAD_NC(GPD2, NONE),
 	PAD_NC(GPD6, NONE),
 	/* GPD7:	Power Adapter Disable				*/
@@ -157,10 +162,6 @@ const struct pad_config gpio_table[] = {
 	/* B25:		Not Connected					*/
 	PAD_NC(GPP_B25, NONE),
 
-	/* C0:		SMB Clock					*/
-	PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1),
-	/* C1:		SMB Data					*/
-	PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1),
 	/* C2:		TLS Confidentiality	Weak Internal PD 20K
 				Low:	Disabled
 				High:	Enabled				*/
@@ -261,8 +262,6 @@ const struct pad_config gpio_table[] = {
 	PAD_CFG_GPO(GPP_E6, 0, DEEP),
 	/* E7:		Embedded Controller SMI				*/
 	PAD_NC(GPP_E7, NONE),
-	/* E8:		DRAM Sleep					*/
-	PAD_CFG_GPO(GPP_E8, 1, DEEP),
 	/* E9:		USB OverCurrent 0				*/
 	PAD_NC(GPP_E9, NONE),
 	/* E10:		PWD Amplifier Input				*/

From 1c8717613096981891122941b7cda86c31f254e7 Mon Sep 17 00:00:00 2001
From: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Date: Tue, 1 Apr 2025 09:30:48 +0800
Subject: [PATCH 0559/3886] mb/google/nissa/var/dirks: Disable TCSS
 D3COLD_SUPPORT

In dirks, we re-purpose a TCSS USB port into a Type-A port.
In this case, D3COLD in tcss_xhci is not supported, so we override
dirks settings. This is a W/A until we root cause why PMC is unable
to handle PM for this migrated port.

BUG=b:400809281
TEST= Confirm that when connecting only the Type-A0 port, it can
recognize USB3 speed.

Change-Id: I35ae587e02d794352ffc9d18a4c18868d23366f3
Signed-off-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87053
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Jayvik Desai <jayvik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com>
---
 src/mainboard/google/brya/Kconfig | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/src/mainboard/google/brya/Kconfig b/src/mainboard/google/brya/Kconfig
index 9808a327b5..f7f8bf9a22 100644
--- a/src/mainboard/google/brya/Kconfig
+++ b/src/mainboard/google/brya/Kconfig
@@ -1178,4 +1178,8 @@ config SKIP_RAM_ID_STRAPS
 
 	  If unsure, leave this option disabled.
 
+config D3COLD_SUPPORT
+	bool
+	default n if BOARD_GOOGLE_DIRKS
+
 endif # BOARD_GOOGLE_BRYA_COMMON

From e3173ddbaed43b5db28c926950560d2f631a9727 Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Thu, 27 Mar 2025 11:11:23 -0500
Subject: [PATCH 0560/3886] docs/security/vboot: Update supported board list

Generated by util/vboot_list/vboot_list.sh.

Change-Id: I079e02d24671a76520587b03a9d83fdc9f33e55b
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87029
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
---
 Documentation/security/vboot/list_vboot.md | 27 ++++++++++++++++++----
 1 file changed, 22 insertions(+), 5 deletions(-)

diff --git a/Documentation/security/vboot/list_vboot.md b/Documentation/security/vboot/list_vboot.md
index bf6fcc08ba..14a6a2348c 100644
--- a/Documentation/security/vboot/list_vboot.md
+++ b/Documentation/security/vboot/list_vboot.md
@@ -7,6 +7,7 @@
 - BirmanPlus for Phoenix SoC
 - BirmanPlus for Glinda SoC
 - Chausie
+- Crater for Renoir SoC
 - Majolica
 - Mayan for Phoenix SoC
 
@@ -54,6 +55,7 @@
 - Craaskov
 - Constitution
 - Crota
+- Dirks
 - Dochi
 - Domika
 - Felwinter
@@ -63,6 +65,7 @@
 - Gladios
 - Glassway
 - Gothrax
+- Guren
 - Hades
 - Kano
 - Kinox
@@ -72,6 +75,7 @@
 - Marasov
 - Mithrax
 - Moli
+- Moxie
 - Nivviks
 - Nereid
 - Nokris
@@ -80,7 +84,9 @@
 - Pirrha
 - Primus
 - Pujjo
+- Pujjoniru
 - Quandiso
+- Quandiso2
 - Redrix
 - Redrix4ES
 - Riven
@@ -111,6 +117,7 @@
 - Pujjogatwin
 - Orisa
 - Telith
+- Meliks
 - Butterfly (HP Pavilion Chromebook 14)
 - Cherry
 - Dojo
@@ -129,6 +136,7 @@
 - Veluza
 - Starmie
 - Wugtrio
+- Wyrdeer
 - Banon (Acer Chromebook 15 (CB3-532))
 - Celes (Samsung Chromebook 3)
 - Cyan (Acer Chromebook R11 (C738T))
@@ -230,6 +238,7 @@
 - Oak
 - Elm (Acer Chromebook R13)
 - Hana (Lenovo N23 Yoga Chromebook)
+- Ocelot
 - Parrot (Acer C7/C710 Chromebook)
 - Atlas (Google Pixelbook Go)
 - Poppy
@@ -238,18 +247,18 @@
 - Nocturne (Google Pixel Slate)
 - Rammus
 - Soraka (HP Chromebook x2)
-- Ambassador
-- Dooly
+- Ambassador (Meet Compute System [Intel 10th Gen])
+- Dooly (HP Chromebase 21.5)
 - Duffy Legacy (32MB)
 - Duffy (ASUS Chromebox 4)
 - Faffy (ASUS Fanless Chromebox)
-- Genesis
+- Genesis (Meet Compute System - Series One [Intel 10th Gen])
 - Kaisa Legacy (32MB)
 - Kaisa (Acer Chromebox CXI4)
-- Moonbuggy
+- Moonbuggy (Series One Board 65)
 - Noibat (HP Chromebox G3)
 - Puff
-- Scout
+- Scout (Series One Desk 27)
 - Wyvern (CTL Chromebox CBx2)
 - Hylia
 - Navi
@@ -373,6 +382,7 @@
 - Meteorlake-P RVP with Chrome EC for Prod Silicon
 - Meteorlake-P RVP with Chrome EC for non-Prod Silicon
 - Meteorlake-P RVP with Microchip EC
+- Ptlrvp
 - shadowmountain
 - Strago
 - Tigerlake UP3 RVP
@@ -417,6 +427,10 @@
 - PRO Z790-P (WIFI) DDR4
 - PRO Z790-P (WIFI)
 
+## NovaCustom
+- V540TU (14\")
+- V560TU (16\")
+
 ## OpenCellular
 - Elgon (GBCv2)
 
@@ -447,8 +461,11 @@
 - Star Labs StarBook Mk V (i3-1115G4 and i7-1165G7)
 - Star Labs StarBook Mk VI (i3-1220P and i7-1260P)
 - Star Labs StarBook Mk VI (i3-1315U and i7-1360P)
+- Star Labs StarBook Mk VII (N200)
+- Star Labs StarBook Mk VII (165H)
 - Star Labs StarFighter Mk I (i3-1315U, i7-13700H and i9-13900H)
 - Star Labs Lite Mk V (N200)
+- Star Labs Lite Mk V Smart Battery (N200)
 
 ## Supermicro
 - X11SSH-TF

From 730b2b506b8ce5f2aa98739128d05ae826e5657b Mon Sep 17 00:00:00 2001
From: Gareth Yu <gareth.yu@intel.com>
Date: Thu, 27 Mar 2025 16:21:09 +0800
Subject: [PATCH 0561/3886] mb/google/brya/var/meliks: reset
 DPHY_CLOCK_LANE_TIMING

According to the analysis results, resetting the DSI DPHY to default
during a warm boot is needed if 'You are in developer mode' needs to be
displayed on the screen in a system using the MIPI-DSI panel.

DPHY_0_CLOCK_LANE_TIMING -- address:0x162180, size: 32 bits
[31]: CLK_PREPARE Override. 0:HW maintains, 1:SW overrides
[30..28]: CLK_PREPARE
[27]: CLK_ZERO Override. 0:HW maintains, 1:SW overrides
[23..20]: CLK_ZERO
[19]: CLK_PRE Override. 0:HW maintains, 1:SW overrides
[17..16]: CLK_PRE
[15]: CLK_POST Override. 0:HW maintains, 1:SW overrides
[10..8]: CLK_POST
[7]: CLK_TRAIL Override. 0:HW maintains, 1:SW overrides
[2..0]: CLK_TRAIL

BUG=b:397805262
TEST=Able to show 'You are in developer mode'

Change-Id: I7857c4f71fc7d1d0c5069a462bdd70c8dbb78179
Signed-off-by: Gareth Yu <gareth.yu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86838
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jayvik Desai <jayvik@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
---
 .../google/brya/variants/meliks/Makefile.mk   |  1 +
 .../google/brya/variants/meliks/ramstage.c    | 56 +++++++++++++++++++
 2 files changed, 57 insertions(+)
 create mode 100644 src/mainboard/google/brya/variants/meliks/ramstage.c

diff --git a/src/mainboard/google/brya/variants/meliks/Makefile.mk b/src/mainboard/google/brya/variants/meliks/Makefile.mk
index bc560b8f1d..30365181de 100644
--- a/src/mainboard/google/brya/variants/meliks/Makefile.mk
+++ b/src/mainboard/google/brya/variants/meliks/Makefile.mk
@@ -5,3 +5,4 @@ romstage-y += memory.c
 
 ramstage-$(CONFIG_FW_CONFIG) += fw_config.c
 ramstage-y += gpio.c
+ramstage-y += ramstage.c
diff --git a/src/mainboard/google/brya/variants/meliks/ramstage.c b/src/mainboard/google/brya/variants/meliks/ramstage.c
new file mode 100644
index 0000000000..d2a9b5c667
--- /dev/null
+++ b/src/mainboard/google/brya/variants/meliks/ramstage.c
@@ -0,0 +1,56 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#define __SIMPLE_DEVICE__
+
+#include <soc/ramstage.h>
+#include <device/pci_def.h>
+#include <device/pci_ops.h>
+#include <device/mmio.h>
+
+#define DPHY_0_CLOCK_LANE_TIMING	0x162180
+#define RESET_DPHY_0_CLOCK_LANE_TIMING	0
+
+static uint32_t igd_mem_base(void)
+{
+	uint32_t igd_bar = pci_read_config32(SA_DEVFN_IGD, PCI_BASE_ADDRESS_0);
+
+	/* Check if the controller is disabled or not present */
+	if (igd_bar == 0 || igd_bar == 0xffffffff)
+		return 0;
+
+	return (igd_bar & ~PCI_BASE_ADDRESS_MEM_ATTR_MASK);
+}
+
+static void igd_set_mem_base(uint32_t base)
+{
+	uint16_t igd_cmd;
+
+	pci_write_config32(SA_DEVFN_IGD, PCI_BASE_ADDRESS_0, base);
+	igd_cmd = pci_read_config16(SA_DEVFN_IGD, PCI_COMMAND);
+	pci_write_config16(SA_DEVFN_IGD, PCI_COMMAND, igd_cmd | PCI_COMMAND_MEMORY);
+}
+
+static void reset_display_dphy_clock(void)
+{
+	uint32_t igd_base = igd_mem_base();
+	bool need_temp_bar = false;
+
+	if (!igd_base) {
+		need_temp_bar = true;
+		igd_base = CONFIG_GFX_GMA_DEFAULT_MMIO;
+		igd_set_mem_base(igd_base);
+	}
+
+	write32p(igd_base + DPHY_0_CLOCK_LANE_TIMING, RESET_DPHY_0_CLOCK_LANE_TIMING);
+
+	if (need_temp_bar)
+		igd_set_mem_base(0);
+}
+
+void mainboard_silicon_init_params(FSP_S_CONFIG *params)
+{
+	/* DPHY CLK timing is not reset if the boot reason is warm boot. Hence to make
+	   the function consistent relies on software forcing the DPHY CLK timing to
+	   the HW default */
+	reset_display_dphy_clock();
+}

From fe344ea5079810cffcf2aa294a574359e538fd93 Mon Sep 17 00:00:00 2001
From: Felix Held <felix-coreboot@felixheld.de>
Date: Thu, 20 Mar 2025 17:27:37 +0100
Subject: [PATCH 0562/3886] util/amdfwtool: add PLATFORM_FAEGAN

Add the PLATFORM_FAEGAN element to the 'platform' enum and use it in the
code. The Faegan SoC is similar to the Glinda SoC, but has a different
PSP ID.

Change-Id: I40a3e9981696fc02a44fbf300d1b47060a4a398b
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86940
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ana Carolina Cabral <ana.cpmelo95@gmail.com>
---
 util/amdfwtool/amdfwtool.c  | 7 +++++++
 util/amdfwtool/amdfwtool.h  | 1 +
 util/amdfwtool/data_parse.c | 6 +++++-
 util/amdfwtool/signed_psp.c | 1 +
 4 files changed, 14 insertions(+), 1 deletion(-)

diff --git a/util/amdfwtool/amdfwtool.c b/util/amdfwtool/amdfwtool.c
index c2a83ea637..73a13c3a8a 100644
--- a/util/amdfwtool/amdfwtool.c
+++ b/util/amdfwtool/amdfwtool.c
@@ -631,6 +631,7 @@ static void fill_psp_directory_to_efs(embedded_firmware *amd_romsig, void *pspdi
 	case PLATFORM_LUCIENNE:
 	case PLATFORM_RENOIR:
 	case PLATFORM_GENOA:
+	case PLATFORM_FAEGAN:
 	default:
 		/* for combo, it is also combo_psp_directory */
 		amd_romsig->new_psp_directory =
@@ -662,6 +663,7 @@ static void fill_bios_directory_to_efs(embedded_firmware *amd_romsig, void *bios
 	case PLATFORM_MENDOCINO:
 	case PLATFORM_PHOENIX:
 	case PLATFORM_GLINDA:
+	case PLATFORM_FAEGAN:
 		break;
 	case PLATFORM_CARRIZO:
 	case PLATFORM_STONEYRIDGE:
@@ -704,6 +706,9 @@ static uint32_t get_psp_id(enum platform soc_id)
 	case PLATFORM_GENOA:
 		psp_id = 0xBC0C0111;
 		break;
+	case PLATFORM_FAEGAN:
+		psp_id = 0xbc0e1000;
+		break;
 	case PLATFORM_CARRIZO:
 	default:
 		psp_id = 0;
@@ -1557,6 +1562,7 @@ static int set_efs_table(uint8_t soc_id, amd_cb_config *cb_config,
 	case PLATFORM_PHOENIX:
 	case PLATFORM_GLINDA:
 	case PLATFORM_GENOA:
+	case PLATFORM_FAEGAN:
 		amd_romsig->spi_readmode_f17_mod_30_3f = cb_config->efs_spi_readmode;
 		amd_romsig->spi_fastspeed_f17_mod_30_3f = cb_config->efs_spi_speed;
 		switch (cb_config->efs_spi_micron_flag) {
@@ -1615,6 +1621,7 @@ static bool is_initial_alignment_required(enum platform soc_id)
 	case PLATFORM_MENDOCINO:
 	case PLATFORM_PHOENIX:
 	case PLATFORM_GLINDA:
+	case PLATFORM_FAEGAN:
 		return false;
 	default:
 		return true;
diff --git a/util/amdfwtool/amdfwtool.h b/util/amdfwtool/amdfwtool.h
index 3c773f70d5..24a7dd3bf0 100644
--- a/util/amdfwtool/amdfwtool.h
+++ b/util/amdfwtool/amdfwtool.h
@@ -29,6 +29,7 @@ enum platform {
 	PLATFORM_PHOENIX,
 	PLATFORM_GLINDA,
 	PLATFORM_GENOA,
+	PLATFORM_FAEGAN,
 };
 
 typedef enum _amd_fw_type {
diff --git a/util/amdfwtool/data_parse.c b/util/amdfwtool/data_parse.c
index 64ec4d7e33..154d34dc6a 100644
--- a/util/amdfwtool/data_parse.c
+++ b/util/amdfwtool/data_parse.c
@@ -117,6 +117,8 @@ static enum platform identify_platform(char *soc_name)
 		return PLATFORM_GLINDA;
 	else if (!strcasecmp(soc_name, "Genoa"))
 		return PLATFORM_GENOA;
+	else if (!strcasecmp(soc_name, "Faegan"))
+		return PLATFORM_FAEGAN;
 	else
 		return PLATFORM_UNKNOWN;
 }
@@ -725,7 +727,8 @@ static uint8_t process_one_line(char *oneline, regmatch_t *match, char *dir,
 
 bool needs_ish(enum platform platform_type)
 {
-	if (platform_type == PLATFORM_MENDOCINO || platform_type == PLATFORM_PHOENIX || platform_type == PLATFORM_GLINDA)
+	if (platform_type == PLATFORM_MENDOCINO || platform_type == PLATFORM_PHOENIX ||
+		platform_type == PLATFORM_GLINDA || platform_type == PLATFORM_FAEGAN)
 		return true;
 	else
 		return false;
@@ -746,6 +749,7 @@ static bool is_second_gen(enum platform platform_type)
 	case PLATFORM_PHOENIX:
 	case PLATFORM_GLINDA:
 	case PLATFORM_GENOA:
+	case PLATFORM_FAEGAN:
 		return true;
 	case PLATFORM_UNKNOWN:
 	default:
diff --git a/util/amdfwtool/signed_psp.c b/util/amdfwtool/signed_psp.c
index 24f76e8762..18215a04c2 100644
--- a/util/amdfwtool/signed_psp.c
+++ b/util/amdfwtool/signed_psp.c
@@ -40,6 +40,7 @@ static uint16_t get_psp_fw_type(enum platform soc_id, struct amd_fw_header *head
 	case PLATFORM_MENDOCINO:
 	case PLATFORM_PHOENIX:
 	case PLATFORM_GLINDA:
+	case PLATFORM_FAEGAN:
 		/* Fallback to fw_type if fw_id is not populated, which serves the same
 		   purpose on older SoCs. */
 		return header->fw_id ? header->fw_id : header->fw_type;

From 02fa23724f6e6633148f9f7b1a6a40d2f644a532 Mon Sep 17 00:00:00 2001
From: Maximilian Brune <maximilian.brune@9elements.com>
Date: Fri, 28 Feb 2025 22:54:10 +0100
Subject: [PATCH 0563/3886] Documentation/lib/rmodules.md: Update simple binary
 explanation

Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: I9cf21b4258758b18f0d3c9316c9aa32cc0d9c44f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86656
Reviewed-by: Nicholas Chin <nic.c3.14@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 Documentation/lib/rmodules.md | 20 ++++++++++++++++++--
 1 file changed, 18 insertions(+), 2 deletions(-)

diff --git a/Documentation/lib/rmodules.md b/Documentation/lib/rmodules.md
index 8a707b8a54..440274213d 100644
--- a/Documentation/lib/rmodules.md
+++ b/Documentation/lib/rmodules.md
@@ -35,8 +35,24 @@ One can split the rmodules in two different kinds:
 1. coreboot stages (postcar, ramstage)
 2. simple binaries (smm, smmstub, sipi\_vector)
 
-They are actually handled the same by the build system and only differ
-in the fact, that they are either coreboot stages or they are not.
+There is one important difference in how they are handled:
+The simple binaries are compiled into rmodules the same as coreboot
+stages are, but the simple binaries are always directly linked to a
+stage. Since rmodules are ELF files as well, we can easily link them
+to the stages in which we need them (usually postcar or ramstage).
+So they are not really separate modules anymore, but still retain
+the ability to accept rmodule\_parameters.
+Since the simple binaries are usually very small, linking them directly
+into the stage (e.g. ramstage or postcar) avoids having to fetch them
+from CBFS and running all that code to fetch a few hundred bytes of
+code. So the build system handles them as follows:
+1. create rmodule (which is an ELF file) from source files
+2. remove all the ELF headers and sections that are not loadable using
+`objcopy -O binary`
+3. from this, create an object file, which usually has the self invented
+.manual file extension, which can be linked to the appropriate stage
+4. add the generated .manual file as "source" file to the stage we want
+to link it to
 
 In the end the ELF files will have three different ELF sections,
 which are all created by the rmodtool.

From 22fd605d23901bfeec135daeb2a4ca27145cc2eb Mon Sep 17 00:00:00 2001
From: Maximilian Brune <maximilian.brune@9elements.com>
Date: Mon, 17 Mar 2025 02:50:10 +0100
Subject: [PATCH 0564/3886] soc/amd/common/psp_verstage: Remove arch/io.h

The arch include files are overshadowed by PSP verstage include files.
The reason is that psp_verstage implements its own set of inb() and
outb() functions, which use a runtime configurable IO base address
instead of a built time constant.

But this works at the moment only because of the order in which the
include files are added. Since that is very error prone, this patch
introduces another solution to the problem.

Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: I16fa4a4cb5168024aaef30119e9aa8a34dbaacbe
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86874
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
---
 src/device/Kconfig                            |  6 ------
 src/include/arch-generic/io.h                 |  7 ++++++-
 src/lib/Makefile.mk                           |  4 ++++
 src/lib/io.c                                  |  5 +++++
 src/mainboard/emulation/qemu-aarch64/Kconfig  |  3 ---
 src/mainboard/emulation/qemu-aarch64/mmio.c   |  2 ++
 src/soc/amd/common/psp_verstage/fch.c         | 14 ++-----------
 .../amd/common/psp_verstage/include/arch/io.h | 21 -------------------
 8 files changed, 19 insertions(+), 43 deletions(-)
 create mode 100644 src/lib/io.c
 delete mode 100644 src/soc/amd/common/psp_verstage/include/arch/io.h

diff --git a/src/device/Kconfig b/src/device/Kconfig
index bcff6fd8b0..af3fe80a59 100644
--- a/src/device/Kconfig
+++ b/src/device/Kconfig
@@ -558,12 +558,6 @@ config PCI
 	bool
 	default n
 
-config PCI_IOBASE
-	hex
-	help
-	  The memory address of a memory-mapped translator that lets the
-	  CPU communicate with peripheral devices over PCI I/O space.
-
 if PCI
 
 config DOMAIN_RESOURCE_32BIT_LIMIT
diff --git a/src/include/arch-generic/io.h b/src/include/arch-generic/io.h
index 5874fc8425..30f331ec99 100644
--- a/src/include/arch-generic/io.h
+++ b/src/include/arch-generic/io.h
@@ -19,7 +19,12 @@
 #include <endian.h>
 #include <arch/mmio.h>
 
-#define __io(a)	(void *)(uintptr_t)(CONFIG_PCI_IOBASE + a)
+/*
+ * The memory address of a memory-mapped translator that lets the
+ * CPU communicate with peripheral devices over PCI I/O space.
+ */
+extern uintptr_t io_port_mmio_base;
+#define __io(a) (void *)(io_port_mmio_base + a)
 
 static inline void outb(uint8_t value, uint16_t port)
 {
diff --git a/src/lib/Makefile.mk b/src/lib/Makefile.mk
index 84b982dbf6..e0bec03427 100644
--- a/src/lib/Makefile.mk
+++ b/src/lib/Makefile.mk
@@ -291,6 +291,10 @@ postcar-y += rmodule.c
 postcar-$(CONFIG_COLLECT_TIMESTAMPS) += timestamp.c
 postcar-$(CONFIG_GENERIC_UDELAY) += timer.c
 
+all-$(CONFIG_ARCH_ARM) += io.c
+all-$(CONFIG_ARCH_ARM64) += io.c
+all-$(CONFIG_ARCH_RISCV) += io.c
+
 # Use program.ld for all the platforms which use C fo the bootblock.
 bootblock-y += program.ld
 
diff --git a/src/lib/io.c b/src/lib/io.c
new file mode 100644
index 0000000000..a5808d6029
--- /dev/null
+++ b/src/lib/io.c
@@ -0,0 +1,5 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <stdint.h>
+
+uintptr_t __weak io_port_mmio_base = 0;
diff --git a/src/mainboard/emulation/qemu-aarch64/Kconfig b/src/mainboard/emulation/qemu-aarch64/Kconfig
index 42f9110df4..c0f579e799 100644
--- a/src/mainboard/emulation/qemu-aarch64/Kconfig
+++ b/src/mainboard/emulation/qemu-aarch64/Kconfig
@@ -30,9 +30,6 @@ config ECAM_MMCONF_BASE_ADDRESS
 config ECAM_MMCONF_BUS_NUMBER
 	default 256
 
-config PCI_IOBASE
-	default 0x3eff0000
-
 config MEMLAYOUT_LD_FILE
 	string
 	default "src/mainboard/emulation/qemu-aarch64/memlayout.ld"
diff --git a/src/mainboard/emulation/qemu-aarch64/mmio.c b/src/mainboard/emulation/qemu-aarch64/mmio.c
index 0fac64d234..a1dca5a6dc 100644
--- a/src/mainboard/emulation/qemu-aarch64/mmio.c
+++ b/src/mainboard/emulation/qemu-aarch64/mmio.c
@@ -3,6 +3,8 @@
 #include <console/uart.h>
 #include <mainboard/addressmap.h>
 
+uintptr_t io_port_mmio_base = 0x3eff0000;
+
 uintptr_t uart_platform_base(unsigned int idx)
 {
 	return VIRT_UART_BASE;
diff --git a/src/soc/amd/common/psp_verstage/fch.c b/src/soc/amd/common/psp_verstage/fch.c
index 5e46e68b65..45ba2f7e25 100644
--- a/src/soc/amd/common/psp_verstage/fch.c
+++ b/src/soc/amd/common/psp_verstage/fch.c
@@ -48,21 +48,11 @@ static void gpio_set_bar(void *bar)
 	acpimmio_gpio0 = bar;
 }
 
-static uintptr_t io_bar;
+uintptr_t io_port_mmio_base;
 
 static void io_set_bar(void *bar)
 {
-	io_bar = (uintptr_t)bar;
-}
-
-u8 io_read8(u16 reg)
-{
-	return read8p(io_bar + reg);
-}
-
-void io_write8(u16 reg, u8 value)
-{
-	write8p(io_bar + reg, value);
+	io_port_mmio_base = (uintptr_t)bar;
 }
 
 static void aoac_set_bar(void *bar)
diff --git a/src/soc/amd/common/psp_verstage/include/arch/io.h b/src/soc/amd/common/psp_verstage/include/arch/io.h
deleted file mode 100644
index efa128b25c..0000000000
--- a/src/soc/amd/common/psp_verstage/include/arch/io.h
+++ /dev/null
@@ -1,21 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#ifndef __ARCH_IO_H__
-#define __ARCH_IO_H__
-
-#include <stdint.h>
-
-u8 io_read8(u16 reg);
-void io_write8(u16 reg, u8 value);
-
-static inline void outb(uint8_t value, uint16_t port)
-{
-	io_write8(port, value);
-}
-
-static inline uint8_t inb(uint16_t port)
-{
-	return io_read8(port);
-}
-
-#endif

From 275beb93db804c9d2ef05e2eb599537d20ef9409 Mon Sep 17 00:00:00 2001
From: Subrata Banik <subratabanik@google.com>
Date: Tue, 1 Apr 2025 19:14:20 +0530
Subject: [PATCH 0565/3886] mb/google/fatcat: Conditionally check for barrel
 charger

The barrel charger check in `baseboard_devtree_update` was
unconditional, increasing boot time on platforms without it.

This commit conditions the check on `CONFIG(BOARD_GOOGLE_MODEL_FATCAT)`,
making it specific to the fatcat board.

This avoids unnecessary delay on platforms like francka and felino.

BUG=b:328770565
TEST=Boot time reduced by 56ms.

Change-Id: Id7a26b634a1a310f714fbf4b4a2accd75665bc28
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87064
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Pranava Y N <pranavayn@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jayvik Desai <jayvik@google.com>
---
 .../google/fatcat/variants/baseboard/fatcat/ramstage.c          | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/mainboard/google/fatcat/variants/baseboard/fatcat/ramstage.c b/src/mainboard/google/fatcat/variants/baseboard/fatcat/ramstage.c
index 030b587579..21f8ccda98 100644
--- a/src/mainboard/google/fatcat/variants/baseboard/fatcat/ramstage.c
+++ b/src/mainboard/google/fatcat/variants/baseboard/fatcat/ramstage.c
@@ -53,7 +53,7 @@ const struct cpu_tdp_power_limits power_optimized_limits[] = {
 void baseboard_devtree_update(void)
 {
 	/* Don't optimize the power limit if booting with barrel attached */
-	if (google_chromeec_is_barrel_charger_present())
+	if (CONFIG(BOARD_GOOGLE_MODEL_FATCAT) && google_chromeec_is_barrel_charger_present())
 		return;
 
 	if (!google_chromeec_is_battery_present())

From 2a7638480492164274c12ddd7235d6529a8e2012 Mon Sep 17 00:00:00 2001
From: Subrata Banik <subratabanik@google.com>
Date: Wed, 2 Apr 2025 17:48:48 +0530
Subject: [PATCH 0566/3886] soc/intel/pantherlake: Directly assign HDA SDI
 enable
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

The double negation (`!!`) was unnecessarily used when assigning the
`pch_hda_sdi_enable` type boolean from the SOC config to the FSP M
config.

This commit removes the redundant `!!` operator, directly assigning
the boolean value of `config->pch_hda_sdi_enable[i]` to
`m_cfg->PchHdaSdiEnable[i]`.

TEST=Able to build and boot google/fatcat.

Change-Id: I9233116ca2bfaeac2f685d464a1cb261f067db6a
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87109
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
---
 src/soc/intel/pantherlake/romstage/fsp_params.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/soc/intel/pantherlake/romstage/fsp_params.c b/src/soc/intel/pantherlake/romstage/fsp_params.c
index b5fc93bc66..521d2f2f09 100644
--- a/src/soc/intel/pantherlake/romstage/fsp_params.c
+++ b/src/soc/intel/pantherlake/romstage/fsp_params.c
@@ -162,7 +162,7 @@ static void fill_fspm_audio_params(FSP_M_CONFIG *m_cfg,
 	m_cfg->PchHdaIDispCodecDisconnect = !config->pch_hda_idisp_codec_enable;
 
 	for (int i = 0; i < MAX_HD_AUDIO_SDI_LINKS; i++)
-		m_cfg->PchHdaSdiEnable[i] = !!config->pch_hda_sdi_enable[i];
+		m_cfg->PchHdaSdiEnable[i] = config->pch_hda_sdi_enable[i];
 
 	/*
 	 * All the PchHdaAudioLink{Hda|Dmic|Ssp|Sndw}Enable UPDs are used by FSP

From cab89f7d111344ebd9a4e3e379131c071e41b397 Mon Sep 17 00:00:00 2001
From: Subrata Banik <subratabanik@google.com>
Date: Wed, 2 Apr 2025 16:05:23 +0000
Subject: [PATCH 0567/3886] commonlib/storage: Avoid build error when
 CONFIG_PCI is disabled

When CONFIG_PCI is disabled, but COMMONLIB_STORAGE and
COMMONLIB_STORAGE_SD are enabled, the compilation of
pci_sdhci.c fails. This is because the code attempts to use
pci_s_read_config32() with the PCI_BASE_ADDRESS_0 macro, which
are only defined when CONFIG_PCI is enabled.

Add an early return NULL check based on !CONFIG(PCI) at the
beginning of new_pci_sdhci_controller(). This prevents the
compiler from attempting to process the PCI-specific code path
when PCI support is not configured, resolving the build failure
in this specific Kconfig scenario.

TEST=Able to build herobrine.

Change-Id: I5c70d9b9ebcac13b47bba2c260fdf2ad7d56d4d7
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87092
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
---
 src/commonlib/storage/pci_sdhci.c | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/src/commonlib/storage/pci_sdhci.c b/src/commonlib/storage/pci_sdhci.c
index f7922d42ea..51b44deabb 100644
--- a/src/commonlib/storage/pci_sdhci.c
+++ b/src/commonlib/storage/pci_sdhci.c
@@ -2,6 +2,7 @@
 
 #include <commonlib/sdhci.h>
 #include <device/pci.h>
+#include <device/pci_def.h>
 #include <device/pci_ops.h>
 #include <stdint.h>
 
@@ -42,6 +43,9 @@ struct sd_mmc_ctrlr *new_pci_sdhci_controller(pci_devfn_t dev)
 {
 	uintptr_t addr;
 
+	if (!CONFIG(PCI))
+		return NULL;
+
 	addr = pci_s_read_config32(dev, PCI_BASE_ADDRESS_0);
 	if (addr == ((uint32_t)~0)) {
 		sdhc_error("Error: PCI SDHCI not found\n");

From 175a37059b4333651a6e1687273049809b1883b2 Mon Sep 17 00:00:00 2001
From: Mac Chiang <mac.chiang@intel.com>
Date: Tue, 1 Apr 2025 19:43:16 +0800
Subject: [PATCH 0568/3886] mb/google/fatcat/var/francka: move NC pin to
 default

Relocate the NC pins configuration to gpio.c, enabling it once needed.

BUG=b:392007428
TEST=emerge-fatcat coreboot

Signed-off-by: Mac Chiang <mac.chiang@intel.com>
Change-Id: I5c594f68b151f8c8c58e35a0590be15456f54b32
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87062
Reviewed-by: Jayvik Desai <jayvik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Pranava Y N <pranavayn@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
---
 .../fatcat/variants/francka/fw_config.c       | 17 ----------
 .../google/fatcat/variants/francka/gpio.c     | 32 +++++++++----------
 2 files changed, 16 insertions(+), 33 deletions(-)

diff --git a/src/mainboard/google/fatcat/variants/francka/fw_config.c b/src/mainboard/google/fatcat/variants/francka/fw_config.c
index 91aa20083c..f9049742e1 100644
--- a/src/mainboard/google/fatcat/variants/francka/fw_config.c
+++ b/src/mainboard/google/fatcat/variants/francka/fw_config.c
@@ -24,23 +24,6 @@ static const struct pad_config hda_enable_pads[] = {
 	PAD_CFG_NF(GPP_S06, NONE, DEEP, NF5),
 	/* SOC_DMIC_DATA1 */
 	PAD_CFG_NF(GPP_S07, NONE, DEEP, NF5),
-
-	/* GPP_D09:     PCH_DGPU_HOLD_RST#_R */
-	PAD_NC(GPP_D09, NONE),
-	/* GPP_D16:     HDA_RST# */
-	PAD_NC(GPP_D16, NONE),
-	/* GPP_S00:     SNDW_3_SCL */
-	PAD_NC(GPP_S00, NONE),
-	/* GPP_S01:     SNDW_3_SDA */
-	PAD_NC(GPP_S01, NONE),
-	/* GPP_S02:     SOC_DMIC_CLK0 */
-	PAD_NC(GPP_S02, NONE),
-	/* GPP_S03:     SOC_DMIC_DATA0 */
-	PAD_NC(GPP_S03, NONE),
-	/* GPP_S04:     SNDW2_CLK */
-	PAD_NC(GPP_S04, NONE),
-	/* GPP_S05:     SNDW2_DATA0 */
-	PAD_NC(GPP_S05, NONE),
 };
 
 static const struct pad_config audio_disable_pads[] = {
diff --git a/src/mainboard/google/fatcat/variants/francka/gpio.c b/src/mainboard/google/fatcat/variants/francka/gpio.c
index 73898dcff7..baf272e3e3 100644
--- a/src/mainboard/google/fatcat/variants/francka/gpio.c
+++ b/src/mainboard/google/fatcat/variants/francka/gpio.c
@@ -344,22 +344,22 @@ static const struct pad_config gpio_table[] = {
 	/* GPP_H22:     SOC_I2C_1_SCL */
 	PAD_CFG_NF(GPP_H22, NONE, DEEP, NF1),
 
-	/* GPP_S00:     SNDW_3_SCL */
-	PAD_CFG_NF(GPP_S00, NONE, DEEP, NF1),
-	/* GPP_S01:     SNDW_3_SDA */
-	PAD_CFG_NF(GPP_S01, NONE, DEEP, NF1),
-	/* GPP_S02:     SOC_DMIC_CLK0 */
-	PAD_CFG_NF(GPP_S02, NONE, DEEP, NF1),
-	/* GPP_S03:     SOC_DMIC_DATA0 */
-	PAD_CFG_NF(GPP_S03, NONE, DEEP, NF1),
-	/* GPP_S04:     SNDW2_CLK */
-	PAD_CFG_NF(GPP_S04, NONE, DEEP, NF2),
-	/* GPP_S05:     SNDW2_DATA0 */
-	PAD_CFG_NF(GPP_S05, NONE, DEEP, NF2),
-	/* GPP_S06:     SOC_DMIC_CLK1 */
-	PAD_CFG_NF(GPP_S06, NONE, DEEP, NF5),
-	/* GPP_S07:     SOC_DMIC_DATA1 */
-	PAD_CFG_NF(GPP_S07, NONE, DEEP, NF5),
+	/* GPP_S00:     Not used */
+	PAD_NC(GPP_S00, NONE),
+	/* GPP_S01:     Not used */
+	PAD_NC(GPP_S01, NONE),
+	/* GPP_S02:     Not used */
+	PAD_NC(GPP_S02, NONE),
+	/* GPP_S03:     Not used */
+	PAD_NC(GPP_S03, NONE),
+	/* GPP_S04:     Not used */
+	PAD_NC(GPP_S04, NONE),
+	/* GPP_S05:     Not used */
+	PAD_NC(GPP_S05, NONE),
+	/* GPP_S06:     Not used */
+	PAD_NC(GPP_S06, NONE),
+	/* GPP_S07:     Not used */
+	PAD_NC(GPP_S07, NONE),
 
 	/* GPP_V00:     PM_BATLOW# */
 	PAD_CFG_NF(GPP_V00, NONE, DEEP, NF1),

From 30ecc1c9ce887ed3c8825e4757d27d761a738c21 Mon Sep 17 00:00:00 2001
From: Subrata Banik <subratabanik@google.com>
Date: Wed, 2 Apr 2025 17:44:43 +0530
Subject: [PATCH 0569/3886] soc/intel/pantherlake: Increase CBFS mcache size

This patch overrides `CONFIG_CBFS_MCACHE_SIZE` Kconfig option with
updated size of the CBFS memory cache to 0x8000 bytes.

TEST=Able to build and boot google/fatcat w/o any error.

w/o this patch:

```
[ERROR]  CBFS ERROR: mcache overflow, should increase CBFS_MCACHE size!
```

Change-Id: Ib6f046c7211a020c15d89a02348ea89f095273ed
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87108
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Reviewed-by: Jayvik Desai <jayvik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Pranava Y N <pranavayn@google.com>
---
 src/soc/intel/pantherlake/Kconfig | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/src/soc/intel/pantherlake/Kconfig b/src/soc/intel/pantherlake/Kconfig
index d372a6fdd7..a884631e53 100644
--- a/src/soc/intel/pantherlake/Kconfig
+++ b/src/soc/intel/pantherlake/Kconfig
@@ -319,6 +319,10 @@ config CBFS_SIZE
 	hex
 	default 0x200000
 
+config CBFS_MCACHE_SIZE
+	hex
+	default 0x8000
+
 config PRERAM_CBMEM_CONSOLE_SIZE
 	hex
 	default 0x2000

From 57f7e2182ec62a92dfcd6f154b47c8760e784d27 Mon Sep 17 00:00:00 2001
From: Pranava Y N <pranavayn@google.com>
Date: Tue, 1 Apr 2025 15:51:10 +0530
Subject: [PATCH 0570/3886] Revert "mb/google/brya: Enable RTD3 for SSD to
 resolve S0ix issue"

This reverts commit 08076240bdc10894b8e790e4b52adf4344fff261.

Reason for revert: Unable to boot to OS on taniks. Enabling RTD3 for
pcie_rp9 in the brya baseboard enables it for all variants. pcie_rp9
is being used for eMMC in taniks, taeko and few other variants. This
is causing boot failure in these devices.

Change-Id: I72270812312db5b2505046f32466cbb4c200947f
Signed-off-by: Pranava Y N <pranavayn@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87056
Reviewed-by: Jayvik Desai <jayvik@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 .../google/brya/variants/baseboard/brya/devicetree.cb      | 7 -------
 1 file changed, 7 deletions(-)

diff --git a/src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb b/src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb
index 3a748ea0f1..6160ebf084 100644
--- a/src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb
+++ b/src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb
@@ -192,13 +192,6 @@ chip soc/intel/alderlake
 				.clk_req = 1,
 				.flags = PCIE_RP_LTR | PCIE_RP_AER,
 			}"
-			chip soc/intel/common/block/pcie/rtd3
-				register "is_storage" = "true"
-				register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D11)"
-				register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B4)"
-				register "srcclk_pin" = "1"
-				device generic 0 on end
-			end
 		end	#PCIE9-12 SSD
 		device ref uart0 on end
 		device ref gspi1 on end

From 8b55ee05dc957bfb5b2a1122c9093059cb9115b3 Mon Sep 17 00:00:00 2001
From: Pranava Y N <pranavayn@google.com>
Date: Tue, 1 Apr 2025 16:24:27 +0530
Subject: [PATCH 0571/3886] mb/google/brya/var/anahera: Enable RTD3 for SSD to
 resolve S0ix issue

Some SSDs block the CPU from reaching C10 during the S0ix suspend
without the RTD3 configuration. Add PCIe RTD3 support so NVMe gets
placed into D3 state when entering S0ix.

Enable and reset GPIOs are configured as per pin mapping in gpio.c.

BUG=b:391612392
TEST=Run suspend_stress_test on anahera device and verify that the
device suspends to S0ix.

Change-Id: I43a1277efabf8b1ca265e9aca65878da60275b38
Signed-off-by: Pranava Y N <pranavayn@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87057
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jayvik Desai <jayvik@google.com>
---
 .../google/brya/variants/anahera/overridetree.cb         | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/src/mainboard/google/brya/variants/anahera/overridetree.cb b/src/mainboard/google/brya/variants/anahera/overridetree.cb
index 2670e11a8e..12566087db 100644
--- a/src/mainboard/google/brya/variants/anahera/overridetree.cb
+++ b/src/mainboard/google/brya/variants/anahera/overridetree.cb
@@ -227,6 +227,15 @@ chip soc/intel/alderlake
 				device generic 0 on end
 			end
 		end	#PCIE8 SD card
+		device ref pcie_rp9 on
+			chip soc/intel/common/block/pcie/rtd3
+				register "is_storage" = "true"
+				register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D11)"
+				register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B4)"
+				register "srcclk_pin" = "1"
+				device generic 0 on end
+			end
+		end	#PCIE9-12 SSD
 		device ref i2c0 on
 			chip drivers/i2c/generic
 				register "hid" = ""10EC5682""

From 807c9d0840acbc7ad0c1ee865fefc8ee10183c72 Mon Sep 17 00:00:00 2001
From: Pranava Y N <pranavayn@google.com>
Date: Tue, 1 Apr 2025 17:27:32 +0530
Subject: [PATCH 0572/3886] mb/google/brya/var/mithrax: Enable RTD3 for SSD to
 resolve S0ix issue

Some SSDs block the CPU from reaching C10 during the S0ix suspend
without the RTD3 configuration. Add PCIe RTD3 support so NVMe gets
placed into D3 state when entering S0ix.

Enable and reset GPIOs are configured as per pin mapping in gpio.c.

BUG=b:391612392
TEST=Run suspend_stress_test on mithrax device and verify that the
device suspends to S0ix.

Change-Id: I5008ec5e153c3695b1d6aa1183515eba192deaa2
Signed-off-by: Pranava Y N <pranavayn@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87060
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Jayvik Desai <jayvik@google.com>
---
 .../google/brya/variants/mithrax/overridetree.cb         | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/src/mainboard/google/brya/variants/mithrax/overridetree.cb b/src/mainboard/google/brya/variants/mithrax/overridetree.cb
index 15bebe2a1a..6a85edf658 100644
--- a/src/mainboard/google/brya/variants/mithrax/overridetree.cb
+++ b/src/mainboard/google/brya/variants/mithrax/overridetree.cb
@@ -218,6 +218,15 @@ chip soc/intel/alderlake
 				device generic 0 on end
 			end
 		end	#PCIE8 SD card
+		device ref pcie_rp9 on
+			chip soc/intel/common/block/pcie/rtd3
+				register "is_storage" = "true"
+				register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D11)"
+				register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B4)"
+				register "srcclk_pin" = "1"
+				device generic 0 on end
+			end
+		end	#PCIE9-12 SSD
 		device ref i2c0 on
 			chip drivers/i2c/generic
 				register "hid" = ""RTL5682""

From 2077d0d79d84bfaede58d81e12639be47a8d33e7 Mon Sep 17 00:00:00 2001
From: Pranava Y N <pranavayn@google.com>
Date: Tue, 1 Apr 2025 17:08:52 +0530
Subject: [PATCH 0573/3886] mb/google/brya/var/redrix: Enable RTD3 for SSD to
 resolve S0ix issue

Some SSDs block the CPU from reaching C10 during the S0ix suspend
without the RTD3 configuration. Add PCIe RTD3 support so NVMe gets
placed into D3 state when entering S0ix.

Enable and reset GPIOs are configured as per pin mapping in gpio.c.

BUG=b:391612392
TEST=Run suspend_stress_test on redrix device and verify that the
device suspends to S0ix.

Change-Id: I9d8bd6bb2c5aecf2fa67486cc81935d2ac7cd5ce
Signed-off-by: Pranava Y N <pranavayn@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87058
Reviewed-by: Jayvik Desai <jayvik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 .../google/brya/variants/redrix/overridetree.cb          | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/src/mainboard/google/brya/variants/redrix/overridetree.cb b/src/mainboard/google/brya/variants/redrix/overridetree.cb
index 1a9f1d9b17..4b486977c8 100644
--- a/src/mainboard/google/brya/variants/redrix/overridetree.cb
+++ b/src/mainboard/google/brya/variants/redrix/overridetree.cb
@@ -327,6 +327,15 @@ chip soc/intel/alderlake
 				device generic 0 on end
 			end
 		end	#PCIE8 SD card
+		device ref pcie_rp9 on
+			chip soc/intel/common/block/pcie/rtd3
+				register "is_storage" = "true"
+				register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D11)"
+				register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B4)"
+				register "srcclk_pin" = "1"
+				device generic 0 on end
+			end
+		end	#PCIE9-12 SSD
 		device ref i2c0 on
 			chip drivers/i2c/generic
 				register "hid" = ""RTL5682""

From 590f6b9b79f256ff17225dfc446e7afb27797c16 Mon Sep 17 00:00:00 2001
From: Pranava Y N <pranavayn@google.com>
Date: Tue, 1 Apr 2025 17:53:40 +0530
Subject: [PATCH 0574/3886] mb/google/brya/var/gimble: Enable RTD3 for SSD to
 resolve S0ix issue

Some SSDs block the CPU from reaching C10 during the S0ix suspend
without the RTD3 configuration. Add PCIe RTD3 support so NVMe gets
placed into D3 state when entering S0ix.

Enable and reset GPIOs are configured as per pin mapping in gpio.c.

BUG=b:391612392
TEST=Run suspend_stress_test on gimble device and verify that the
device suspends to S0ix.

Change-Id: Iac9eb63639cbb0c7708d5b2bb30aca20e09db3e7
Signed-off-by: Pranava Y N <pranavayn@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87061
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jayvik Desai <jayvik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
---
 .../google/brya/variants/gimble/overridetree.cb          | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/src/mainboard/google/brya/variants/gimble/overridetree.cb b/src/mainboard/google/brya/variants/gimble/overridetree.cb
index 4f1bcdcfb9..762c3ffa4a 100644
--- a/src/mainboard/google/brya/variants/gimble/overridetree.cb
+++ b/src/mainboard/google/brya/variants/gimble/overridetree.cb
@@ -159,6 +159,15 @@ chip soc/intel/alderlake
 				device generic 0 on end
 			end
 		end	#PCIE8 SD card
+		device ref pcie_rp9 on
+			chip soc/intel/common/block/pcie/rtd3
+				register "is_storage" = "true"
+				register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D11)"
+				register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B4)"
+				register "srcclk_pin" = "1"
+				device generic 0 on end
+			end
+		end	#PCIE9-12 SSD
 		device ref i2c0 on
 			chip drivers/i2c/generic
 				register "hid" = ""10EC5682""

From d27e7d7233cd5421d3bc305e3bd840eb750bc9b1 Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Tue, 1 Apr 2025 21:24:55 +0100
Subject: [PATCH 0575/3886] mb/starlabs/starbook/adl_n: Tidy GPIO comments for
 the PCH Straps

This is a non-functional change, and only makes the GPIOs easier to read.

Change-Id: I658cd6ddf2d418da0e36a8e1969041a696a10d87
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87080
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
---
 .../starlabs/starbook/variants/adl_n/gpio.c   | 50 ++++++-------------
 1 file changed, 14 insertions(+), 36 deletions(-)

diff --git a/src/mainboard/starlabs/starbook/variants/adl_n/gpio.c b/src/mainboard/starlabs/starbook/variants/adl_n/gpio.c
index e7a68c2758..680126dce8 100644
--- a/src/mainboard/starlabs/starbook/variants/adl_n/gpio.c
+++ b/src/mainboard/starlabs/starbook/variants/adl_n/gpio.c
@@ -79,10 +79,22 @@ const struct pad_config gpio_table[] = {
 	PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1),				/* Data */
 	PAD_CFG_GPO(GPP_E8, 1, DEEP),					/* DRAM Sleep */
 
+	/* Config Straps 									[ Low      / High     ] */
+	PAD_CFG_GPO(GPP_B14, 0, RSMRST),				/* Top Swap		[ Disabled / Enabled  ] */
+	PAD_NC(GPP_B18, NONE),						/* Reboot Support	[ Enabled  / Disabled ] */
+	PAD_CFG_GPO(GPP_C2, 1, PLTRST),					/* TLS Confidentiality	[ Disabled / Enabled  ] */
+	PAD_CFG_GPO(GPP_C5, 0, PLTRST),					/* eSPI			[ Enabled  / Disabled ] */
+	PAD_CFG_GPO(GPP_E6, 0, DEEP),					/* JTAG ODT		[ Disabled / Enabled  ] */
+	PAD_CFG_GPO(GPP_H1, 0, DEEP),					/* BFX Strap 2 Bit 3	[ Disabled / Enabled  ] */
+	PAD_NC(GPP_F2, NONE),						/* M.2 CNVi		[ Enabled  / Disabled ] */
+	PAD_NC(GPP_E19, NONE),						/* TBT LSX #0		[ 1.8V     / 3.3V     ] */
+	PAD_NC(GPP_E21, NONE),						/* TBT LSX #1           [ 1.8V     / 3.3V     ] */
+	PAD_NC(GPP_D12, NONE),						/* TBT LSX #3		[ 1.8V     / 3.3V     ] */
+	PAD_CFG_GPO(GPP_F7, 0, DEEP),					/* MCRO LDO		[ Disabled / Bypass   ] */
+	PAD_CFG_GPO(GPD7, 0, PWROK),					/* RTC Clock Delay	[ Disabled / 95ms     ] */
+
 	PAD_NC(GPD2, NONE),
 	PAD_NC(GPD6, NONE),
-	/* GPD7:	Power Adapter Disable				*/
-	PAD_CFG_GPO(GPD7, 0, PWROK),
 	PAD_NC(GPD9, NONE),
 	PAD_NC(GPD10, NONE),
 	PAD_NC(GPD11, NONE),
@@ -133,20 +145,12 @@ const struct pad_config gpio_table[] = {
 	PAD_NC(GPP_B11, NONE),
 	/* B12:		PM SLP S0					*/
 	PAD_NC(GPP_B12, NONE),
-	/* B14:		Top Swap Override	Weak Internal PD 20K
-				High:	Enabled
-				Low:	Disabled			*/
-	PAD_CFG_GPO(GPP_B14, 0, PLTRST),
 	/* B15:		Not Connected					*/
 	PAD_NC(GPP_B15, NONE),
 	/* B16:		Not Connected					*/
 	PAD_NC(GPP_B16, NONE),
 	/* B17:		Not Connected					*/
 	PAD_NC(GPP_B17, NONE),
-	/* B18:		Reboot Support		Weak Internal PD 20K
-				High:	Disabled
-				Low:	Enabled				*/
-	PAD_NC(GPP_B18, NONE),
 	/* B19:		Not Connected					*/
 	PAD_NC(GPP_B19, NONE),
 	/* B20:		Not Connected					*/
@@ -162,18 +166,10 @@ const struct pad_config gpio_table[] = {
 	/* B25:		Not Connected					*/
 	PAD_NC(GPP_B25, NONE),
 
-	/* C2:		TLS Confidentiality	Weak Internal PD 20K
-				Low:	Disabled
-				High:	Enabled				*/
-	PAD_CFG_GPO(GPP_C2, 1, PLTRST),
 	/* C3:		SML 0 Clock					*/
 	PAD_NC(GPP_C3, NONE),
 	/* C4:		SML 0 Data					*/
 	PAD_NC(GPP_C4, NONE),
-	/* C5:		Boot Strap		Weak Internal PD 20K
-				Low:	ESPI
-				High:	Disabled			*/
-	PAD_CFG_GPO(GPP_C5, 0, PLTRST),
 	/* C6:		SML 1 Clock					*/
 	PAD_NC(GPP_C6, NONE),
 	/* C7:		SML 1 Data					*/
@@ -231,8 +227,6 @@ const struct pad_config gpio_table[] = {
 	PAD_NC(GPP_D10, NONE),
 	/* D11:		GSPI 2 MISO FPS					*/
 	PAD_NC(GPP_D11, NONE),
-	/* D12:		GSPI 2 MOSI FPS					*/
-	PAD_NC(GPP_D12, NONE),
 	/* D13:		Wireless LAN Wake				*/
 	PAD_NC(GPP_D13, NONE),
 	/* D14:		CPU M.2 SSD Power Enable			*/
@@ -256,10 +250,6 @@ const struct pad_config gpio_table[] = {
 	PAD_NC(GPP_E4, NONE),
 	/* E5:		Not Connected					*/
 	PAD_NC(GPP_E5, NONE),
-	/* E6:		JTAG ODT		No internal PD
-				Low:	Disabled
-				High:	Enabled				*/
-	PAD_CFG_GPO(GPP_E6, 0, DEEP),
 	/* E7:		Embedded Controller SMI				*/
 	PAD_NC(GPP_E7, NONE),
 	/* E9:		USB OverCurrent 0				*/
@@ -276,12 +266,8 @@ const struct pad_config gpio_table[] = {
 	PAD_NC(GPP_E17, NONE),
 	/* E18:		Not Connected					*/
 	PAD_NC(GPP_E18, NONE),
-	/* E19:		Thunderbolt LSX RXD				*/
-	PAD_NC(GPP_E19, NONE),
 	/* E20:		Not Connected					*/
 	PAD_NC(GPP_E20, NONE),
-	/* E21:		Not Connected					*/
-	PAD_NC(GPP_E21, NONE),
 	/* E22:		Not Connected					*/
 	PAD_NC(GPP_E22, NONE),
 	/* E23:		Not Connected					*/
@@ -291,8 +277,6 @@ const struct pad_config gpio_table[] = {
 	PAD_NC(GPP_F0, NONE),
 	/* F1:		CNV BRI Response				*/
 	PAD_NC(GPP_F1, NONE),
-	/* F2:		CNV RGI Data					*/
-	PAD_NC(GPP_F2, NONE),
 	/* F3:		CNV RGI Response				*/
 	PAD_NC(GPP_F3, NONE),
 	/* F4:		CNV RF Reset					*/
@@ -301,10 +285,6 @@ const struct pad_config gpio_table[] = {
 	PAD_NC(GPP_F5, NONE),
 	/* F6:		CNV PA Blanking					*/
 	PAD_NC(GPP_F6, NONE),
-	/* F7:		TBT LSX VCCIO		Weak Internal PD 20K
-				Low:	1.8V
-				High:	3.3V				*/
-	PAD_CFG_GPO(GPP_F7, 0, DEEP),
 	/* F8:		Not Connected					*/
 	PAD_NC(GPP_F8, NONE),
 	/* F9:								*/
@@ -338,8 +318,6 @@ const struct pad_config gpio_table[] = {
 	/* F23:		Not Connected					*/
 	PAD_NC(GPP_F23, NONE),
 
-	/* H1:		BFX Strap 2 Bit 3	Weak Internal PD 20K	*/
-	PAD_CFG_GPO(GPP_H1, 0, DEEP),
 	/* H3:		Not Connected					*/
 	PAD_NC(GPP_H3, NONE),
 	/* H4:		I2C 0 SDA		Touchpad		*/

From 87395f6d5586a9d12d2b5b31e315c0c22f1003bc Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Tue, 1 Apr 2025 21:26:48 +0100
Subject: [PATCH 0576/3886] mb/starlabs/starbook/adl_n: Disconnect GPP_F10

This GPIO is not connected so configure it accordingly.

Change-Id: Ie85d69e0a2a423261038688c176b32abe7bd8134
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87081
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
---
 src/mainboard/starlabs/starbook/variants/adl_n/gpio.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/mainboard/starlabs/starbook/variants/adl_n/gpio.c b/src/mainboard/starlabs/starbook/variants/adl_n/gpio.c
index 680126dce8..19b3cc8b71 100644
--- a/src/mainboard/starlabs/starbook/variants/adl_n/gpio.c
+++ b/src/mainboard/starlabs/starbook/variants/adl_n/gpio.c
@@ -289,8 +289,8 @@ const struct pad_config gpio_table[] = {
 	PAD_NC(GPP_F8, NONE),
 	/* F9:								*/
 	PAD_NC(GPP_F9, NONE),
-	/* F10:		Weak Internal PD 20K				*/
-	PAD_CFG_GPO(GPP_F10, 0, DEEP),
+	/* F10:		Not Connected					*/
+	PAD_NC(GPP_F10, NONE),
 	/* F11:		TPM ID						*/
 	PAD_NC(GPP_F11, NONE),
 	/* F12:		Not Connected					*/

From 4ac75ed1b3aa7a76aab8c4f7b42eb02c98204c1e Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Tue, 1 Apr 2025 21:29:28 +0100
Subject: [PATCH 0577/3886] mb/starlabs/starbook/adl_n: Remove comments for
 GPIOs that aren't connected

This is a non-functional change; it just makes it easier to read.

Change-Id: Ib3f87c6e3e83d57c4e6969c3aac7cae02d750a5c
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87082
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
---
 .../starlabs/starbook/variants/adl_n/gpio.c   | 149 ------------------
 1 file changed, 149 deletions(-)

diff --git a/src/mainboard/starlabs/starbook/variants/adl_n/gpio.c b/src/mainboard/starlabs/starbook/variants/adl_n/gpio.c
index 19b3cc8b71..43f2213fae 100644
--- a/src/mainboard/starlabs/starbook/variants/adl_n/gpio.c
+++ b/src/mainboard/starlabs/starbook/variants/adl_n/gpio.c
@@ -99,312 +99,163 @@ const struct pad_config gpio_table[] = {
 	PAD_NC(GPD10, NONE),
 	PAD_NC(GPD11, NONE),
 
-	/* A5:		Not Connected					*/
 	PAD_NC(GPP_A5, NONE),
-	/* A6:		Not Connected					*/
 	PAD_NC(GPP_A6, NONE),
-	/* A7:		Embedded Controller SCI				*/
 	PAD_NC(GPP_A7, NONE),
-	/* A8:		Not Connected					*/
 	PAD_NC(GPP_A8, NONE),
-	/* A11:		Not Connected					*/
 	PAD_NC(GPP_A11, NONE),
-	/* A12:		Not Connected					*/
 	PAD_NC(GPP_A12, NONE),
-	/* A14:		Test Point 45					*/
 	PAD_NC(GPP_A14, NONE),
-	/* A15:		Test Point 52					*/
 	PAD_NC(GPP_A15, NONE),
-	/* A16:		USB OverCurrent 3				*/
 	PAD_NC(GPP_A16, NONE),
-	/* A17:		Not Connected					*/
 	PAD_NC(GPP_A17, NONE),
-	/* A20:		Test Point 44					*/
 	PAD_NC(GPP_A20, NONE),
-	/* A21:		Fingerprint Reader Interrupt			*/
 	PAD_NC(GPP_A21, NONE),
-	/* A22:		Fingerprint Reader Reset			*/
 	PAD_NC(GPP_A22, NONE),
-	/* A23:		Not Connected					*/
 	PAD_NC(GPP_A23, NONE),
 
-
-	/* B3:		Not Connected					*/
 	PAD_NC(GPP_B3, NONE),
-	/* B4:		Not Connected					*/
 	PAD_NC(GPP_B4, NONE),
-	/* B5:		I2C 2 SDA		Touch Panel SDA		*/
 	PAD_NC(GPP_B5, NONE),
-	/* B6:		I2C 2 SCL		Touch Panel Clock	*/
 	PAD_NC(GPP_B6, NONE),
-	/* B9:		Not Connected					*/
 	PAD_NC(GPP_B9, NONE),
-	/* B10:		Not Connected					*/
 	PAD_NC(GPP_B10, NONE),
-	/* B11:		Not Connected					*/
 	PAD_NC(GPP_B11, NONE),
-	/* B12:		PM SLP S0					*/
 	PAD_NC(GPP_B12, NONE),
-	/* B15:		Not Connected					*/
 	PAD_NC(GPP_B15, NONE),
-	/* B16:		Not Connected					*/
 	PAD_NC(GPP_B16, NONE),
-	/* B17:		Not Connected					*/
 	PAD_NC(GPP_B17, NONE),
-	/* B19:		Not Connected					*/
 	PAD_NC(GPP_B19, NONE),
-	/* B20:		Not Connected					*/
 	PAD_NC(GPP_B20, NONE),
-	/* B21:		Not Connected					*/
 	PAD_NC(GPP_B21, NONE),
-	/* B22:		Not Connected					*/
 	PAD_NC(GPP_B22, NONE),
-	/* B23:		Not used	MiPi Camera			*/
 	PAD_NC(GPP_B23, NONE),
-	/* B24:		Not Connected					*/
 	PAD_NC(GPP_B24, NONE),
-	/* B25:		Not Connected					*/
 	PAD_NC(GPP_B25, NONE),
 
-	/* C3:		SML 0 Clock					*/
 	PAD_NC(GPP_C3, NONE),
-	/* C4:		SML 0 Data					*/
 	PAD_NC(GPP_C4, NONE),
-	/* C6:		SML 1 Clock					*/
 	PAD_NC(GPP_C6, NONE),
-	/* C7:		SML 1 Data					*/
 	PAD_NC(GPP_C7, NONE),
-	/* C8:		Not Connected					*/
 	PAD_NC(GPP_C8, NONE),
-	/* C9:		Not Connected					*/
 	PAD_NC(GPP_C9, NONE),
-	/* C10:		Not Connected					*/
 	PAD_NC(GPP_C10, NONE),
-	/* C11:		Not Connected					*/
 	PAD_NC(GPP_C11, NONE),
-	/* C12:		Not Connected					*/
 	PAD_NC(GPP_C12, NONE),
-	/* C13:		Not Connected					*/
 	PAD_NC(GPP_C13, NONE),
-	/* C14:		Not Connected					*/
 	PAD_NC(GPP_C14, NONE),
-	/* C15:		Not Connected					*/
 	PAD_NC(GPP_C15, NONE),
-	/* C16:		Not Connected					*/
 	PAD_NC(GPP_C16, NONE),
-	/* C17:		Not Connected					*/
 	PAD_NC(GPP_C17, NONE),
-	/* C18:		Not Connected					*/
 	PAD_NC(GPP_C18, NONE),
-	/* C19:		Not Connected					*/
 	PAD_NC(GPP_C19, NONE),
-	/* C20:		Not Connected					*/
 	PAD_NC(GPP_C20, NONE),
-	/* C21:		Not Connected					*/
 	PAD_NC(GPP_C21, NONE),
-	/* C22:		Not Connected					*/
 	PAD_NC(GPP_C22, NONE),
-	/* C23:		Not Connected					*/
 	PAD_NC(GPP_C23, NONE),
 
-	/* D0:		Not used		Audio ID 0		*/
 	PAD_NC(GPP_D0, NONE),
-	/* D1:		Not used		Audio ID 1		*/
 	PAD_NC(GPP_D1, NONE),
-	/* D2:		Not used		Audio ID 2		*/
 	PAD_NC(GPP_D2, NONE),
-	/* D3:		Not Connected					*/
 	PAD_NC(GPP_D3, NONE),
-	/* D4:		Not Connected					*/
 	PAD_NC(GPP_D4, NONE),
-	/* D7:		Clock Request 2					*/
 	PAD_NC(GPP_D7, NONE),
-	/* D8:		Clock Request 3					*/
 	PAD_NC(GPP_D8, NONE),
-	/* D9:		GSPI 2 FPS					*/
 	PAD_NC(GPP_D9, NONE),
-	/* D10:		GSPI 2 Clock					*/
 	PAD_NC(GPP_D10, NONE),
-	/* D11:		GSPI 2 MISO FPS					*/
 	PAD_NC(GPP_D11, NONE),
-	/* D13:		Wireless LAN Wake				*/
 	PAD_NC(GPP_D13, NONE),
-	/* D14:		CPU M.2 SSD Power Enable			*/
 	PAD_NC(GPP_D14, NONE),
-	/* D15:		Not Connected					*/
 	PAD_NC(GPP_D15, NONE),
-	/* D17:		Not used		Fingerprint ID		*/
 	PAD_NC(GPP_D17, NONE),
-	/* D18:		Not Connected					*/
 	PAD_NC(GPP_D18, NONE),
-	/* D19:		Test Point 21					*/
 	PAD_NC(GPP_D19, NONE),
 
-	/* E0:		SATA x PCIe					*/
 	PAD_NC(GPP_E0, NONE),
-	/* E1:		Not used		Accelerometer Interrupt	*/
 	PAD_NC(GPP_E1, NONE),
-	/* E2:		Not Connected					*/
 	PAD_NC(GPP_E2, NONE),
-	/* E4:		Test Point 14					*/
 	PAD_NC(GPP_E4, NONE),
-	/* E5:		Not Connected					*/
 	PAD_NC(GPP_E5, NONE),
-	/* E7:		Embedded Controller SMI				*/
 	PAD_NC(GPP_E7, NONE),
-	/* E9:		USB OverCurrent 0				*/
 	PAD_NC(GPP_E9, NONE),
-	/* E10:		PWD Amplifier Input				*/
 	PAD_NC(GPP_E10, NONE),
-	/* E13:		Not connected					*/
 	PAD_NC(GPP_E13, NONE),
-	/* E15:		Not Connected					*/
 	PAD_NC(GPP_E15, NONE),
-	/* E16:		Not Connected					*/
 	PAD_NC(GPP_E16, NONE),
-	/* E17:		Not Connected					*/
 	PAD_NC(GPP_E17, NONE),
-	/* E18:		Not Connected					*/
 	PAD_NC(GPP_E18, NONE),
-	/* E20:		Not Connected					*/
 	PAD_NC(GPP_E20, NONE),
-	/* E22:		Not Connected					*/
 	PAD_NC(GPP_E22, NONE),
-	/* E23:		Not Connected					*/
 	PAD_NC(GPP_E23, NONE),
 
-	/* F0:		CNV BRI Data					*/
 	PAD_NC(GPP_F0, NONE),
-	/* F1:		CNV BRI Response				*/
 	PAD_NC(GPP_F1, NONE),
-	/* F3:		CNV RGI Response				*/
 	PAD_NC(GPP_F3, NONE),
-	/* F4:		CNV RF Reset					*/
 	PAD_NC(GPP_F4, NONE),
-	/* F5:		Not used		MODEM_CLKREQ		*/
 	PAD_NC(GPP_F5, NONE),
-	/* F6:		CNV PA Blanking					*/
 	PAD_NC(GPP_F6, NONE),
-	/* F8:		Not Connected					*/
 	PAD_NC(GPP_F8, NONE),
-	/* F9:								*/
 	PAD_NC(GPP_F9, NONE),
-	/* F10:		Not Connected					*/
 	PAD_NC(GPP_F10, NONE),
-	/* F11:		TPM ID						*/
 	PAD_NC(GPP_F11, NONE),
-	/* F12:		Not Connected					*/
 	PAD_NC(GPP_F12, NONE),
-	/* F13:		Not Connected					*/
 	PAD_NC(GPP_F13, NONE),
-	/* F14:		Not Connected					*/
 	PAD_NC(GPP_F14, NONE),
-	/* F15:		Not used					*/
 	PAD_NC(GPP_F15, NONE),
-	/* F16:		Not Connected					*/
 	PAD_NC(GPP_F16, NONE),
-	/* F17:		Not used					*/
 	PAD_NC(GPP_F17, NONE),
-	/* F18:		Not used					*/
 	PAD_NC(GPP_F18, NONE),
-	/* F19:		Not Connected					*/
 	PAD_NC(GPP_F19, NONE),
-	/* F20:		Not Connected					*/
 	PAD_NC(GPP_F20, NONE),
-	/* F21:		Not Connected					*/
 	PAD_NC(GPP_F21, NONE),
-	/* F22:		Not Connected					*/
 	PAD_NC(GPP_F22, NONE),
-	/* F23:		Not Connected					*/
 	PAD_NC(GPP_F23, NONE),
 
-	/* H3:		Not Connected					*/
 	PAD_NC(GPP_H3, NONE),
-	/* H4:		I2C 0 SDA		Touchpad		*/
 	PAD_NC(GPP_H4, NONE),
-	/* H5:		I2C 0 SCL		Touchpad		*/
 	PAD_NC(GPP_H5, NONE),
-	/* H6:		Not Connected					*/
 	PAD_NC(GPP_H6, NONE),
-	/* H7:		Not Connected					*/
 	PAD_NC(GPP_H7, NONE),
-	/* H8:		I2C 4 SDA		GSensor			*/
 	PAD_NC(GPP_H8, NONE),
-	/* H9:		I2C 4 SDL		GSensor			*/
 	PAD_NC(GPP_H9, NONE),
-	/* H12:		Not Connected					*/
 	PAD_NC(GPP_H12, NONE),
-	/* H13:		PCH M.2 SSD Device Sleep			*/
 	PAD_NC(GPP_H13, NONE),
-	/* H14:		Not Connected					*/
 	PAD_NC(GPP_H14, NONE),
-	/* H16:		Not Connected					*/
 	PAD_NC(GPP_H16, NONE),
-	/* H19:		Clock Request 4		CPU M.2 SSD		*/
 	PAD_NC(GPP_H19, NONE),
-	/* H20:		Not Connected					*/
 	PAD_NC(GPP_H20, NONE),
-	/* H21:		Not Connected					*/
 	PAD_NC(GPP_H21, NONE),
-	/* H22:		Not Connected					*/
 	PAD_NC(GPP_H22, NONE),
-	/* H23:		Clock Request 5					*/
 	PAD_NC(GPP_H23, NONE),
 
-	/* S0:		Not Connected					*/
 	PAD_NC(GPP_S0, NONE),
-	/* S1:		Not Connected					*/
 	PAD_NC(GPP_S1, NONE),
-	/* S2:		DMIC Clock					*/
 	PAD_NC(GPP_S2, NONE),
-	/* S3:		DMIC Data					*/
 	PAD_NC(GPP_S3, NONE),
-	/* S4:		Not Connected					*/
 	PAD_NC(GPP_S4, NONE),
-	/* S5:		Not Connected					*/
 	PAD_NC(GPP_S5, NONE),
-	/* S6:		Not Connected					*/
 	PAD_NC(GPP_S6, NONE),
-	/* S7:		Not Connected					*/
 	PAD_NC(GPP_S7, NONE),
 
-	/* T0:		 Not Connected					*/
 	PAD_NC(GPP_T0, NONE),
-	/* T1:		 Not Connected					*/
 	PAD_NC(GPP_T1, NONE),
-	/* T2:		 Not Connected					*/
 	PAD_NC(GPP_T2, NONE),
-	/* T3:		 Not Connected					*/
 	PAD_NC(GPP_T3, NONE),
-	/* T4:		 Not Connected					*/
 	PAD_NC(GPP_T4, NONE),
-	/* T5:		 Not Connected					*/
 	PAD_NC(GPP_T5, NONE),
-	/* T6:		 Not Connected					*/
 	PAD_NC(GPP_T6, NONE),
-	/* T7:		 Not Connected					*/
 	PAD_NC(GPP_T7, NONE),
-	/* T8:		 Not Connected					*/
 	PAD_NC(GPP_T8, NONE),
-	/* T9:		 Not Connected					*/
 	PAD_NC(GPP_T9, NONE),
-	/* T10:		 Not Connected					*/
 	PAD_NC(GPP_T10, NONE),
-	/* T11:		 Not Connected					*/
 	PAD_NC(GPP_T11, NONE),
-	/* T12:		 Not Connected					*/
 	PAD_NC(GPP_T12, NONE),
-	/* T13:		 Not Connected					*/
 	PAD_NC(GPP_T13, NONE),
-	/* T14:		 Not Connected					*/
 	PAD_NC(GPP_T14, NONE),
-	/* T15:		 Not Connected					*/
 	PAD_NC(GPP_T15, NONE),
 
 	PAD_NC(GPP_R5, NONE),
-	/* R6:		Not Connected					*/
 	PAD_NC(GPP_R6, NONE),
-	/* R7:		Not Connected					*/
 	PAD_NC(GPP_R7, NONE),
 };
 

From eaae0ce699105151485e729bca8fce50e9610fdd Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Tue, 1 Apr 2025 21:32:27 +0100
Subject: [PATCH 0578/3886] mb/starlabs/starbook/adl_n: Reconfigure PCH Strap
 GPIOs

Configure all strap GPIOs as outputs, rather than some being not
connected. This doesn't change anything, but is more explicit.

Set these all to sample on RSMRST.

Change-Id: I779b6bc486b68e8df50347540364901507a7102c
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87083
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
---
 .../starlabs/starbook/variants/adl_n/gpio.c   | 22 +++++++++----------
 1 file changed, 11 insertions(+), 11 deletions(-)

diff --git a/src/mainboard/starlabs/starbook/variants/adl_n/gpio.c b/src/mainboard/starlabs/starbook/variants/adl_n/gpio.c
index 43f2213fae..9edd864ffb 100644
--- a/src/mainboard/starlabs/starbook/variants/adl_n/gpio.c
+++ b/src/mainboard/starlabs/starbook/variants/adl_n/gpio.c
@@ -81,17 +81,17 @@ const struct pad_config gpio_table[] = {
 
 	/* Config Straps 									[ Low      / High     ] */
 	PAD_CFG_GPO(GPP_B14, 0, RSMRST),				/* Top Swap		[ Disabled / Enabled  ] */
-	PAD_NC(GPP_B18, NONE),						/* Reboot Support	[ Enabled  / Disabled ] */
-	PAD_CFG_GPO(GPP_C2, 1, PLTRST),					/* TLS Confidentiality	[ Disabled / Enabled  ] */
-	PAD_CFG_GPO(GPP_C5, 0, PLTRST),					/* eSPI			[ Enabled  / Disabled ] */
-	PAD_CFG_GPO(GPP_E6, 0, DEEP),					/* JTAG ODT		[ Disabled / Enabled  ] */
-	PAD_CFG_GPO(GPP_H1, 0, DEEP),					/* BFX Strap 2 Bit 3	[ Disabled / Enabled  ] */
-	PAD_NC(GPP_F2, NONE),						/* M.2 CNVi		[ Enabled  / Disabled ] */
-	PAD_NC(GPP_E19, NONE),						/* TBT LSX #0		[ 1.8V     / 3.3V     ] */
-	PAD_NC(GPP_E21, NONE),						/* TBT LSX #1           [ 1.8V     / 3.3V     ] */
-	PAD_NC(GPP_D12, NONE),						/* TBT LSX #3		[ 1.8V     / 3.3V     ] */
-	PAD_CFG_GPO(GPP_F7, 0, DEEP),					/* MCRO LDO		[ Disabled / Bypass   ] */
-	PAD_CFG_GPO(GPD7, 0, PWROK),					/* RTC Clock Delay	[ Disabled / 95ms     ] */
+	PAD_CFG_GPO(GPP_B18, 0, RSMRST),				/* Reboot Support	[ Enabled  / Disabled ] */
+	PAD_CFG_GPO(GPP_C2, 1, RSMRST),					/* TLS Confidentiality	[ Disabled / Enabled  ] */
+	PAD_CFG_GPO(GPP_C5, 0, RSMRST),					/* eSPI			[ Enabled  / Disabled ] */
+	PAD_CFG_GPO(GPP_E6, 0, RSMRST),					/* JTAG ODT		[ Disabled / Enabled  ] */
+	PAD_CFG_GPO(GPP_H1, 0, RSMRST),					/* BFX Strap 2 Bit 3	[ Disabled / Enabled  ] */
+	PAD_CFG_GPO(GPP_F2, 0, RSMRST),					/* M.2 CNVi		[ Enabled  / Disabled ] */
+	PAD_CFG_GPO(GPP_E19, 0, RSMRST),				/* TBT LSX #0		[ 1.8V     / 3.3V     ] */
+	PAD_CFG_GPO(GPP_E21, 0, RSMRST),				/* TBT LSX #1           [ 1.8V     / 3.3V     ] */
+	PAD_CFG_GPO(GPP_D12, 0, RSMRST),				/* TBT LSX #3		[ 1.8V     / 3.3V     ] */
+	PAD_CFG_GPO(GPP_F7, 0, RSMRST),					/* MCRO LDO		[ Disabled / Bypass   ] */
+	PAD_CFG_GPO(GPD7, 0, RSMRST),					/* RTC Clock Delay	[ Disabled / 95ms     ] */
 
 	PAD_NC(GPD2, NONE),
 	PAD_NC(GPD6, NONE),

From b1e95af172db095fab26e213e7cfc87638de3105 Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Tue, 1 Apr 2025 21:34:35 +0100
Subject: [PATCH 0579/3886] mb/starlabs/starbook/adl_n: Set CNVi strap to
 disabled

Set GPP_F2 to output high, to indicate that CNVi is disabled.

Change-Id: I82f3ce699d5e823e1ce942acb7a0ba1bd548d9a0
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87084
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
---
 src/mainboard/starlabs/starbook/variants/adl_n/gpio.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/mainboard/starlabs/starbook/variants/adl_n/gpio.c b/src/mainboard/starlabs/starbook/variants/adl_n/gpio.c
index 9edd864ffb..7d15cb969d 100644
--- a/src/mainboard/starlabs/starbook/variants/adl_n/gpio.c
+++ b/src/mainboard/starlabs/starbook/variants/adl_n/gpio.c
@@ -86,7 +86,7 @@ const struct pad_config gpio_table[] = {
 	PAD_CFG_GPO(GPP_C5, 0, RSMRST),					/* eSPI			[ Enabled  / Disabled ] */
 	PAD_CFG_GPO(GPP_E6, 0, RSMRST),					/* JTAG ODT		[ Disabled / Enabled  ] */
 	PAD_CFG_GPO(GPP_H1, 0, RSMRST),					/* BFX Strap 2 Bit 3	[ Disabled / Enabled  ] */
-	PAD_CFG_GPO(GPP_F2, 0, RSMRST),					/* M.2 CNVi		[ Enabled  / Disabled ] */
+	PAD_CFG_GPO(GPP_F2, 1, RSMRST),					/* M.2 CNVi		[ Enabled  / Disabled ] */
 	PAD_CFG_GPO(GPP_E19, 0, RSMRST),				/* TBT LSX #0		[ 1.8V     / 3.3V     ] */
 	PAD_CFG_GPO(GPP_E21, 0, RSMRST),				/* TBT LSX #1           [ 1.8V     / 3.3V     ] */
 	PAD_CFG_GPO(GPP_D12, 0, RSMRST),				/* TBT LSX #3		[ 1.8V     / 3.3V     ] */

From 156c05d25516446fba87305cf44cde0663f572d3 Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Wed, 2 Apr 2025 10:37:49 +0100
Subject: [PATCH 0580/3886] mb/starlabs/starlite_adl: Remove the VGPIO config

These aren't required, so remove the config and let FSP handle it.

Change-Id: I143a779950773823746e838cf29209b6e3bb87ad
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87097
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 .../starlite_adl/variants/mk_v/gpio.c         | 31 -------------------
 1 file changed, 31 deletions(-)

diff --git a/src/mainboard/starlabs/starlite_adl/variants/mk_v/gpio.c b/src/mainboard/starlabs/starlite_adl/variants/mk_v/gpio.c
index 8a0b804904..67f9e407ce 100644
--- a/src/mainboard/starlabs/starlite_adl/variants/mk_v/gpio.c
+++ b/src/mainboard/starlabs/starlite_adl/variants/mk_v/gpio.c
@@ -448,37 +448,6 @@ const struct pad_config gpio_table[] = {
 	PAD_NC(GPP_R6, NONE),
 	/* R7:		Not Connected					*/
 	PAD_NC(GPP_R7, NONE),
-
-	/* CNV_BTEN */
-	PAD_CFG_GPO(GPP_VGPIO_0, 1, DEEP),
-	/* CNV_BT_HOST_WAKEB */
-	PAD_NC(GPP_VGPIO_4, NONE),
-	/* CNV_BT_IF_SELECT */
-	PAD_CFG_GPO(GPP_VGPIO_5, 1, DEEP),
-	/* vCNV_BT_UART_TXD */
-	PAD_NC(GPP_VGPIO_6, NONE),
-	/* vCNV_BT_UART_RXD */
-	PAD_NC(GPP_VGPIO_7, NONE),
-	/* vCNV_BT_UART_CTS_B */
-	PAD_NC(GPP_VGPIO_8, NONE),
-	/* vCNV_BT_UART_RTS_B */
-	PAD_NC(GPP_VGPIO_9, NONE),
-	/* vUART0_TXD */
-	PAD_NC(GPP_VGPIO_18, NONE),
-	/* vUART0_RXD */
-	PAD_NC(GPP_VGPIO_19, NONE),
-	/* vUART0_CTS_B */
-	PAD_NC(GPP_VGPIO_20, NONE),
-	/* vUART0_RTS_B */
-	PAD_NC(GPP_VGPIO_21, NONE),
-	/* BT_I2S_BCLK */
-	PAD_NC(GPP_VGPIO_30, NONE),
-	/* BT_I2S_SYNC */
-	PAD_NC(GPP_VGPIO_31, NONE),
-	/* BT_I2S_SDO */
-	PAD_NC(GPP_VGPIO_32, NONE),
-	/* BT_I2S_SDI */
-	PAD_NC(GPP_VGPIO_33, NONE),
 };
 
 const struct pad_config *variant_gpio_table(size_t *num)

From a22bfba5cf2c1e0b7116f34872a9e3d02e14fe3c Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Wed, 2 Apr 2025 10:43:35 +0100
Subject: [PATCH 0581/3886] mb/starlabs/starbook/*: Tidy GPIO comments for
 debug connector

This is a non-functional change, and only makes the GPIOs easier to read.

Change-Id: I5e271508fcd99c01f7de4e5dad7a1941ba1968ec
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87098
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
---
 src/mainboard/starlabs/byte_adl/variants/mk_ii/gpio.c    | 7 +++----
 src/mainboard/starlabs/starbook/variants/adl/gpio.c      | 7 +++----
 src/mainboard/starlabs/starbook/variants/cml/gpio.c      | 8 ++++----
 src/mainboard/starlabs/starbook/variants/kbl/gpio.c      | 7 +++----
 src/mainboard/starlabs/starbook/variants/mtl/gpio.c      | 7 +++----
 src/mainboard/starlabs/starbook/variants/rpl/gpio.c      | 7 +++----
 src/mainboard/starlabs/starbook/variants/tgl/gpio.c      | 7 +++----
 src/mainboard/starlabs/starfighter/variants/rpl/gpio.c   | 8 ++++----
 src/mainboard/starlabs/starlite_adl/variants/mk_v/gpio.c | 7 +++----
 9 files changed, 29 insertions(+), 36 deletions(-)

diff --git a/src/mainboard/starlabs/byte_adl/variants/mk_ii/gpio.c b/src/mainboard/starlabs/byte_adl/variants/mk_ii/gpio.c
index 71b706d270..d3fa51be0a 100644
--- a/src/mainboard/starlabs/byte_adl/variants/mk_ii/gpio.c
+++ b/src/mainboard/starlabs/byte_adl/variants/mk_ii/gpio.c
@@ -4,10 +4,9 @@
 
 /* Early pad configuration in bootblock */
 const struct pad_config early_gpio_table[] = {
-	/* H10:		UART0 RXD		Debug Connector		*/
-	PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2),
-	/* H11:		UART0 TXD		Debug Connector		*/
-	PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2),
+	/* Debug Connector */
+	PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2),				/* RXD */
+	PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2),				/* TXD */
 };
 
 const struct pad_config *variant_early_gpio_table(size_t *num)
diff --git a/src/mainboard/starlabs/starbook/variants/adl/gpio.c b/src/mainboard/starlabs/starbook/variants/adl/gpio.c
index 4cc9888040..493ec7b595 100644
--- a/src/mainboard/starlabs/starbook/variants/adl/gpio.c
+++ b/src/mainboard/starlabs/starbook/variants/adl/gpio.c
@@ -4,10 +4,9 @@
 
 /* Early pad configuration in bootblock */
 const struct pad_config early_gpio_table[] = {
-	/* H10:		UART0 RXD		Debug Connector		*/
-	PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2),
-	/* H11:		UART0 TXD		Debug Connector		*/
-	PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2),
+	/* Debug Connector */
+	PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2),				/* RXD */
+	PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2),				/* TXD */
 };
 
 const struct pad_config *variant_early_gpio_table(size_t *num)
diff --git a/src/mainboard/starlabs/starbook/variants/cml/gpio.c b/src/mainboard/starlabs/starbook/variants/cml/gpio.c
index e29cd8199b..3ef15068e4 100644
--- a/src/mainboard/starlabs/starbook/variants/cml/gpio.c
+++ b/src/mainboard/starlabs/starbook/variants/cml/gpio.c
@@ -9,10 +9,10 @@
 
 /* Early pad configuration in bootblock */
 const struct pad_config early_gpio_table[] = {
-	/* C20:	 UART2_RXD			*/
-	PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1),
-	/* C21:	 UART2_TXD			*/
-	PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1),
+	/* Debug Connector */
+	PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1),				/* RXD */
+	PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1),				/* TXD */
+
 	/* E22:	BRD_ID0				*/
 	PAD_CFG_GPO(GPP_E22, 1, PLTRST),
 	/* E23:	BRD_ID1				*/
diff --git a/src/mainboard/starlabs/starbook/variants/kbl/gpio.c b/src/mainboard/starlabs/starbook/variants/kbl/gpio.c
index 9ab74148da..ae01749e20 100644
--- a/src/mainboard/starlabs/starbook/variants/kbl/gpio.c
+++ b/src/mainboard/starlabs/starbook/variants/kbl/gpio.c
@@ -9,10 +9,9 @@
 
 /* Early pad configuration in bootblock. */
 const struct pad_config early_gpio_table[] = {
-	/* C20:	 UART2_RXD			*/
-	PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1),
-	/* C21:	 UART2_TXD			*/
-	PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1),
+	/* Debug Connector */
+	PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1),				/* RXD */
+	PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1),				/* TXD */
 };
 
 const struct pad_config *variant_early_gpio_table(size_t *num)
diff --git a/src/mainboard/starlabs/starbook/variants/mtl/gpio.c b/src/mainboard/starlabs/starbook/variants/mtl/gpio.c
index d1b915ab9e..e7f66ff026 100644
--- a/src/mainboard/starlabs/starbook/variants/mtl/gpio.c
+++ b/src/mainboard/starlabs/starbook/variants/mtl/gpio.c
@@ -4,10 +4,9 @@
 
 /* Early pad configuration in bootblock */
 const struct pad_config early_gpio_table[] = {
-	/* H08:	UART0 RXD			*/
-	PAD_CFG_NF(GPP_H08, NONE, DEEP, NF1),
-	/* H09:	UART0 TXD			*/
-	PAD_CFG_NF(GPP_H09, NONE, DEEP, NF1),
+	/* Debug Connector */
+	PAD_CFG_NF(GPP_H08, NONE, DEEP, NF1),				/* RXD */
+	PAD_CFG_NF(GPP_H09, NONE, DEEP, NF1),				/* TXD */
 
 	/* C00:	SMB_CLK				*/
 	PAD_CFG_NF(GPP_C00, NONE, DEEP, NF1),
diff --git a/src/mainboard/starlabs/starbook/variants/rpl/gpio.c b/src/mainboard/starlabs/starbook/variants/rpl/gpio.c
index 542aa32b71..bae3564a05 100644
--- a/src/mainboard/starlabs/starbook/variants/rpl/gpio.c
+++ b/src/mainboard/starlabs/starbook/variants/rpl/gpio.c
@@ -4,10 +4,9 @@
 
 /* Early pad configuration in bootblock */
 const struct pad_config early_gpio_table[] = {
-	/* H10:		UART0 RXD		Debug Connector		*/
-	PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2),
-	/* H11:		UART0 TXD		Debug Connector		*/
-	PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2),
+	/* Debug Connector */
+	PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2),				/* RXD */
+	PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2),				/* TXD */
 };
 
 const struct pad_config *variant_early_gpio_table(size_t *num)
diff --git a/src/mainboard/starlabs/starbook/variants/tgl/gpio.c b/src/mainboard/starlabs/starbook/variants/tgl/gpio.c
index 2526f7fa68..7e30109351 100644
--- a/src/mainboard/starlabs/starbook/variants/tgl/gpio.c
+++ b/src/mainboard/starlabs/starbook/variants/tgl/gpio.c
@@ -9,10 +9,9 @@
 
 /* Early pad configuration in bootblock */
 const struct pad_config early_gpio_table[] = {
-	/* C20:	UART2_RXD_R			*/
-	PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1),
-	/* C21:	UART2_TXD_R			*/
-	PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1),
+	/* Debug Connector */
+	PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1),				/* RXD */
+	PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1),				/* TXD */
 };
 
 const struct pad_config *variant_early_gpio_table(size_t *num)
diff --git a/src/mainboard/starlabs/starfighter/variants/rpl/gpio.c b/src/mainboard/starlabs/starfighter/variants/rpl/gpio.c
index bfd06741d1..6890c273ea 100644
--- a/src/mainboard/starlabs/starfighter/variants/rpl/gpio.c
+++ b/src/mainboard/starlabs/starfighter/variants/rpl/gpio.c
@@ -4,10 +4,10 @@
 
 /* Early pad configuration in bootblock */
 const struct pad_config early_gpio_table[] = {
-	/* H10:		UART0 RXD		Debug Connector		*/
-	PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2),
-	/* H11:		UART0 TXD		Debug Connector		*/
-	PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2),
+	/* Debug Connector */
+	PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2),				/* RXD */
+	PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2),				/* TXD */
+
 	/* F12:		Board ID 0					*/
 	PAD_CFG_GPI_LOCK(GPP_F12, NONE, LOCK_CONFIG),
 	/* F13:		Board ID 1					*/
diff --git a/src/mainboard/starlabs/starlite_adl/variants/mk_v/gpio.c b/src/mainboard/starlabs/starlite_adl/variants/mk_v/gpio.c
index 67f9e407ce..8dea7a51cd 100644
--- a/src/mainboard/starlabs/starlite_adl/variants/mk_v/gpio.c
+++ b/src/mainboard/starlabs/starlite_adl/variants/mk_v/gpio.c
@@ -4,10 +4,9 @@
 
 /* Early pad configuration in bootblock */
 const struct pad_config early_gpio_table[] = {
-	/* H10:		UART0 RXD		Debug Connector		*/
-	PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2),
-	/* H11:		UART0 TXD		Debug Connector		*/
-	PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2),
+	/* Debug Connector */
+	PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2),				/* RXD */
+	PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2),				/* TXD */
 };
 
 const struct pad_config *variant_early_gpio_table(size_t *num)

From 03a0171475eec25998b459aa58e6584abf8da573 Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Wed, 2 Apr 2025 10:47:48 +0100
Subject: [PATCH 0582/3886] mb/starlabs/*: Remove old incorrect comment

Change-Id: Ia3919bd2c41272bca03b464d31ed227c7579cb20
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87099
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/starlabs/starbook/variants/cml/gpio.c | 5 -----
 src/mainboard/starlabs/starbook/variants/kbl/gpio.c | 5 -----
 src/mainboard/starlabs/starbook/variants/tgl/gpio.c | 5 -----
 3 files changed, 15 deletions(-)

diff --git a/src/mainboard/starlabs/starbook/variants/cml/gpio.c b/src/mainboard/starlabs/starbook/variants/cml/gpio.c
index 3ef15068e4..acdeeb468a 100644
--- a/src/mainboard/starlabs/starbook/variants/cml/gpio.c
+++ b/src/mainboard/starlabs/starbook/variants/cml/gpio.c
@@ -2,11 +2,6 @@
 
 #include <variants.h>
 
-/*
- * All definitions are taken from a comparison of the output of "inteltool -a"
- * using the stock BIOS and with coreboot.
- */
-
 /* Early pad configuration in bootblock */
 const struct pad_config early_gpio_table[] = {
 	/* Debug Connector */
diff --git a/src/mainboard/starlabs/starbook/variants/kbl/gpio.c b/src/mainboard/starlabs/starbook/variants/kbl/gpio.c
index ae01749e20..71fc2dc381 100644
--- a/src/mainboard/starlabs/starbook/variants/kbl/gpio.c
+++ b/src/mainboard/starlabs/starbook/variants/kbl/gpio.c
@@ -2,11 +2,6 @@
 
 #include <variants.h>
 
-/*
- * All definitions are taken from a comparison of the output of "inteltool -a"
- * using the stock BIOS and with coreboot.
- */
-
 /* Early pad configuration in bootblock. */
 const struct pad_config early_gpio_table[] = {
 	/* Debug Connector */
diff --git a/src/mainboard/starlabs/starbook/variants/tgl/gpio.c b/src/mainboard/starlabs/starbook/variants/tgl/gpio.c
index 7e30109351..2a0a5382cd 100644
--- a/src/mainboard/starlabs/starbook/variants/tgl/gpio.c
+++ b/src/mainboard/starlabs/starbook/variants/tgl/gpio.c
@@ -2,11 +2,6 @@
 
 #include <variants.h>
 
-/*
- * All definitions are taken from a comparison of the output of "inteltool -a"
- * using the stock BIOS and with coreboot.
- */
-
 /* Early pad configuration in bootblock */
 const struct pad_config early_gpio_table[] = {
 	/* Debug Connector */

From 9e6800c98b161f64c4a0c1bedf533b67d2424f72 Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Wed, 2 Apr 2025 11:17:22 +0100
Subject: [PATCH 0583/3886] mb/starlabs/starbook/*: Tidy GPIO comments for deep
 GPIOs

This is a non-functional change, and only makes the GPIOs easier to read.

Change-Id: Ic5c541a44ac9b34dad5430c994b1fa28e96d67f4
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87100
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 .../starlabs/byte_adl/variants/mk_ii/gpio.c   | 20 ++++++---------
 .../starlabs/starbook/variants/adl/gpio.c     | 20 ++++++---------
 .../starlabs/starbook/variants/cml/gpio.c     | 20 ++++++---------
 .../starlabs/starbook/variants/kbl/gpio.c     | 20 ++++++---------
 .../starlabs/starbook/variants/mtl/gpio.c     | 25 ++++++-------------
 .../starlabs/starbook/variants/rpl/gpio.c     | 21 +++++++---------
 .../starlabs/starbook/variants/tgl/gpio.c     | 20 ++++++---------
 .../starlabs/starfighter/variants/rpl/gpio.c  | 20 ++++++---------
 .../starlite_adl/variants/mk_v/gpio.c         | 20 ++++++---------
 9 files changed, 71 insertions(+), 115 deletions(-)

diff --git a/src/mainboard/starlabs/byte_adl/variants/mk_ii/gpio.c b/src/mainboard/starlabs/byte_adl/variants/mk_ii/gpio.c
index d3fa51be0a..3814debf22 100644
--- a/src/mainboard/starlabs/byte_adl/variants/mk_ii/gpio.c
+++ b/src/mainboard/starlabs/byte_adl/variants/mk_ii/gpio.c
@@ -17,24 +17,20 @@ const struct pad_config *variant_early_gpio_table(size_t *num)
 
 /* Pad configuration in ramstage. */
 const struct pad_config gpio_table[] = {
-	/* GPD0:	Battery Low					*/
-	PAD_CFG_NF(GPD0, NONE, DEEP, NF1),
-	/* GPD1:	Charger Connected				*/
-	PAD_CFG_NF(GPD1, NONE, DEEP, NF1),
+	/* General Purpose I/O Deep */
+	PAD_CFG_NF(GPD0, NONE, DEEP, NF1),				/* Battery Low */
+	PAD_CFG_NF(GPD1, NONE, DEEP, NF1),				/* Charger Connected */
+	PAD_CFG_NF(GPD3, UP_20K, DEEP, NF1),				/* Power Button */
+	PAD_NC(GPD4, NONE),						/* Sleep S3 */
+	PAD_NC(GPD5, NONE),						/* Sleep S4 */
+	PAD_CFG_NF(GPD8, NONE, DEEP, NF1),				/* Bluetooth Suspend */
+
 	/* GPD2:	LAN Wake					*/
 	PAD_NC(GPD2, NONE),
-	/* GPD3:	Power Button					*/
-	PAD_CFG_NF(GPD3, UP_20K, DEEP, NF1),
-	/* GPD4:	Sleep S3					*/
-	PAD_NC(GPD4, NONE),
-	/* GPD5:	Sleep S4					*/
-	PAD_NC(GPD5, NONE),
 	/* GPD6:	Sleep A						*/
 	PAD_NC(GPD6, NONE),
 	/* GPD7:	Power Adapter Disable				*/
 	PAD_CFG_GPO(GPD7, 0, PWROK),
-	/* GPD8:	Suspend Clock					*/
-	PAD_CFG_NF(GPD8, NONE, DEEP, NF1),
 	/* GPD9:	Wireless LAN Sleep				*/
 	PAD_NC(GPD9, NONE),
 	/* GPD10:	Sleep S5					*/
diff --git a/src/mainboard/starlabs/starbook/variants/adl/gpio.c b/src/mainboard/starlabs/starbook/variants/adl/gpio.c
index 493ec7b595..619b3154fc 100644
--- a/src/mainboard/starlabs/starbook/variants/adl/gpio.c
+++ b/src/mainboard/starlabs/starbook/variants/adl/gpio.c
@@ -17,24 +17,20 @@ const struct pad_config *variant_early_gpio_table(size_t *num)
 
 /* Pad configuration in ramstage. */
 const struct pad_config gpio_table[] = {
-	/* GPD0:	Battery Low					*/
-	PAD_CFG_NF(GPD0, NONE, DEEP, NF1),
-	/* GPD1:	Charger Connected				*/
-	PAD_CFG_NF(GPD1, NONE, DEEP, NF1),
+	/* General Purpose I/O Deep */
+	PAD_CFG_NF(GPD0, NONE, DEEP, NF1),				/* Battery Low */
+	PAD_CFG_NF(GPD1, NONE, DEEP, NF1),				/* Charger Connected */
+	PAD_CFG_NF(GPD3, UP_20K, DEEP, NF1),				/* Power Button */
+	PAD_NC(GPD4, NONE),						/* Sleep S3 */
+	PAD_NC(GPD5, NONE),						/* Sleep S4 */
+	PAD_CFG_NF(GPD8, NONE, DEEP, NF1),				/* Bluetooth Suspend */
+
 	/* GPD2:	LAN Wake					*/
 	PAD_NC(GPD2, NONE),
-	/* GPD3:	Power Button					*/
-	PAD_CFG_NF(GPD3, UP_20K, DEEP, NF1),
-	/* GPD4:	Sleep S3					*/
-	PAD_NC(GPD4, NONE),
-	/* GPD5:	Sleep S4					*/
-	PAD_NC(GPD5, NONE),
 	/* GPD6:	Sleep A						*/
 	PAD_NC(GPD6, NONE),
 	/* GPD7:	Power Adapter Disable				*/
 	PAD_CFG_GPO(GPD7, 0, PWROK),
-	/* GPD8:	Suspend Clock					*/
-	PAD_CFG_NF(GPD8, NONE, DEEP, NF1),
 	/* GPD9:	Wireless LAN Sleep				*/
 	PAD_NC(GPD9, NONE),
 	/* GPD10:	Sleep S5					*/
diff --git a/src/mainboard/starlabs/starbook/variants/cml/gpio.c b/src/mainboard/starlabs/starbook/variants/cml/gpio.c
index acdeeb468a..da734839d7 100644
--- a/src/mainboard/starlabs/starbook/variants/cml/gpio.c
+++ b/src/mainboard/starlabs/starbook/variants/cml/gpio.c
@@ -26,26 +26,20 @@ const struct pad_config *variant_early_gpio_table(size_t *num)
 
 /* Pad configuration in ramstage. */
 const struct pad_config gpio_table[] = {
-	/* REFERENCE:	EP PER SCHEMATIC	*/
+	/* General Purpose I/O Deep */
+	PAD_CFG_NF(GPD0, NONE, DEEP, NF1),				/* Battery Low */
+	PAD_CFG_NF(GPD1, NONE, DEEP, NF1),				/* Charger Connected */
+	PAD_CFG_NF(GPD3, UP_20K, DEEP, NF1),				/* Power Button */
+	PAD_CFG_NF(GPD4, NONE, DEEP, NF1),				/* Sleep S3 */
+	PAD_CFG_NF(GPD5, NONE, DEEP, NF1),				/* Sleep S4 */
+	PAD_CFG_NF(GPD8, NONE, DEEP, NF1),				/* Bluetooth Suspend */
 
-	/* GPD0:	PCH_BATLOW#		*/
-	PAD_CFG_NF(GPD0, NONE, DEEP, NF1),
-	/* GPD1:	AC_PRESENT		*/
-	PAD_CFG_NF(GPD1, NONE, DEEP, NF1),
 	/* GPD2:	LAN_WAKE#		*/
 	PAD_NC(GPD2, NONE),
-	/* GPD3:	SIO_PWRBTN#		*/
-	PAD_CFG_NF(GPD3, UP_20K, DEEP, NF1),
-	/* GPD4:	SIO_SLP_S3#		*/
-	PAD_CFG_NF(GPD4, NONE, DEEP, NF1),
-	/* GPD5:	SIO_SLP_S4#		*/
-	PAD_CFG_NF(GPD5, NONE, DEEP, NF1),
 	/* GPD6:	SIO_SLP_A#		*/
 	PAD_CFG_NF(GPD6, NONE, DEEP, NF1),
 	/* GPD7:	PCH_TBT_PERST#		*/
 	PAD_CFG_GPO(GPD7, 0, PLTRST),
-	/* GPD8:	SUSCLK			*/
-	PAD_CFG_NF(GPD8, NONE, DEEP, NF1),
 	/* GPD9:	SIO_SLP_WLAN#		*/
 	PAD_CFG_NF(GPD9, NONE, DEEP, NF1),
 	/* GPD10:	SIO_SLP_S5#		*/
diff --git a/src/mainboard/starlabs/starbook/variants/kbl/gpio.c b/src/mainboard/starlabs/starbook/variants/kbl/gpio.c
index 71fc2dc381..6cffc5fdad 100644
--- a/src/mainboard/starlabs/starbook/variants/kbl/gpio.c
+++ b/src/mainboard/starlabs/starbook/variants/kbl/gpio.c
@@ -17,24 +17,20 @@ const struct pad_config *variant_early_gpio_table(size_t *num)
 
 /* Pad configuration in ramstage. */
 const struct pad_config gpio_table[] = {
-	/* GPD0:	PM_BATLOW_N		*/
-	PAD_CFG_NF(GPD0, UP_20K, PWROK, NF1),
-	/* GPD1:	AC_PRESENT		*/
-	PAD_CFG_NF(GPD1, NATIVE, PWROK, NF1),
+	/* General Purpose I/O Deep */
+	PAD_CFG_NF(GPD0, UP_20K, PWROK, NF1),				/* Battery Low */
+	PAD_CFG_NF(GPD1, NATIVE, PWROK, NF1),				/* Charger Connected */
+	PAD_CFG_NF(GPD3, UP_20K, PWROK, NF1),				/* Power Button */
+	PAD_CFG_NF(GPD4, NONE, PWROK, NF1),				/* Sleep S3 */
+	PAD_CFG_NF(GPD5, NONE, PWROK, NF1),				/* Sleep S4 */
+	PAD_CFG_NF(GPD8, NONE, PWROK, NF1),				/* Bluetooth Suspend */
+
 	/* GPD2:	Not Connected		*/
 	PAD_NC(GPD2, NONE),
-	/* GPD3:	SOC_PWRBTN_N		*/
-	PAD_CFG_NF(GPD3, UP_20K, PWROK, NF1),
-	/* GPD4:	SLP_S3_N		*/
-	PAD_CFG_NF(GPD4, NONE, PWROK, NF1),
-	/* GPD5:	SLP_S4_N		*/
-	PAD_CFG_NF(GPD5, NONE, PWROK, NF1),
 	/* GPD6:	Not Connected		*/
 	PAD_NC(GPD6, NONE),
 	/* GPD7:	Not Connected		*/
 	PAD_NC(GPD7, NONE),
-	/* GPD8:	SUS_CLK			*/
-	PAD_CFG_NF(GPD8, NONE, PWROK, NF1),
 	/* GPD9:	Not Connected		*/
 	PAD_NC(GPD9, NONE),
 	/* GPD10:	Not Connected		*/
diff --git a/src/mainboard/starlabs/starbook/variants/mtl/gpio.c b/src/mainboard/starlabs/starbook/variants/mtl/gpio.c
index e7f66ff026..c3b4c6db2d 100644
--- a/src/mainboard/starlabs/starbook/variants/mtl/gpio.c
+++ b/src/mainboard/starlabs/starbook/variants/mtl/gpio.c
@@ -22,29 +22,20 @@ const struct pad_config *variant_early_gpio_table(size_t *num)
 
 /* Pad configuration in ramstage. */
 const struct pad_config gpio_table[] = {
-	/*
-	 * GPP_V
-	 * Start:	GPP_V00
-	 * End:		GPP_V22
-	 */
-	/* V00:	PM_BATLOW_N			*/
-	PAD_CFG_NF(GPP_V00, NONE, DEEP, NF1),
-	/* V01:	CHG_ACOK			*/
-	PAD_CFG_NF(GPP_V01, NONE, DEEP, NF1),
+	/* General Purpose I/O Deep */
+	PAD_CFG_NF(GPP_V00, NONE, DEEP, NF1),				/* Battery Low */
+	PAD_CFG_NF(GPP_V01, NONE, DEEP, NF1),				/* Charger Connected */
+	PAD_CFG_NF(GPP_V03, UP_20K, DEEP, NF1),				/* Power Button */
+	PAD_CFG_NF(GPP_V04, NONE, DEEP, NF1),				/* Sleep S3 */
+	PAD_CFG_NF(GPP_V05, NONE, DEEP, NF1),				/* Sleep S4 */
+	PAD_CFG_NF(GPP_V08, NONE, DEEP, NF1),				/* Bluetooth Suspend */
+
 	/* V02:	PCIE_WAKE_LAN			*/
 	PAD_NC(GPP_V02, NONE),
-	/* V03:	EC_PWRBTN_N			*/
-	PAD_CFG_NF(GPP_V03, UP_20K, DEEP, NF1),
-	/* V04:	PM_SLP_S3_N			*/
-	PAD_CFG_NF(GPP_V04, NONE, DEEP, NF1),
-	/* V05:	SLP S4#				*/
-	PAD_CFG_NF(GPP_V05, NONE, DEEP, NF1),
 	/* V06:	GPD_6_SLP_A_N			*/
 	PAD_NC(GPP_V06, NONE),
 	/* V07:					*/
 	PAD_NC(GPP_V07, NONE),
-	/* V08:	M.2_BTWIFI_SUS_CLK		*/
-	PAD_CFG_NF(GPP_V08, NONE, DEEP, NF1),
 	/* V09:	GPD_9_SLP_WLAN_N		*/
 	PAD_NC(GPP_V09, NONE),
 	/* V10:	PM_SLP_S5_N			*/
diff --git a/src/mainboard/starlabs/starbook/variants/rpl/gpio.c b/src/mainboard/starlabs/starbook/variants/rpl/gpio.c
index bae3564a05..1aeb866bda 100644
--- a/src/mainboard/starlabs/starbook/variants/rpl/gpio.c
+++ b/src/mainboard/starlabs/starbook/variants/rpl/gpio.c
@@ -17,26 +17,23 @@ const struct pad_config *variant_early_gpio_table(size_t *num)
 
 /* Pad configuration in ramstage. */
 const struct pad_config gpio_table[] = {
-	/* GPD0:	Battery Low					*/
-	PAD_CFG_NF(GPD0, NONE, DEEP, NF1),
-	/* GPD1:	Charger Connected				*/
-	PAD_CFG_NF(GPD1, NONE, DEEP, NF1),
+	/* General Purpose I/O Deep */
+	PAD_CFG_NF(GPD0, NONE, DEEP, NF1),				/* Battery Low */
+	PAD_CFG_NF(GPD1, NONE, DEEP, NF1),				/* Charger Connected */
+	PAD_CFG_NF(GPD3, UP_20K, DEEP, NF1),				/* Power Button */
+	PAD_NC(GPD4, NONE),						/* Sleep S3 */
+	PAD_NC(GPD5, NONE),						/* Sleep S4 */
+	PAD_CFG_NF(GPD8, NONE, DEEP, NF1),				/* Bluetooth Suspend */
+
 	/* GPD2:	LAN Wake					*/
 	PAD_NC(GPD2, NONE),
-	/* GPD3:	Power Button					*/
-	PAD_CFG_NF(GPD3, UP_20K, DEEP, NF1),
-	/* GPD4:	Sleep S3					*/
-	PAD_NC(GPD4, NONE),
-	/* GPD5:	Sleep S4					*/
-	PAD_NC(GPD5, NONE),
 	/* GPD6:	Sleep A						*/
 	PAD_NC(GPD6, NONE),
 	/* GPD7:	Power Adapter Disable				*/
 	PAD_CFG_GPO(GPD7, 0, PWROK),
-	/* GPD8:	Suspend Clock					*/
-	PAD_CFG_NF(GPD8, NONE, DEEP, NF1),
 	/* GPD9:	Wireless LAN Sleep				*/
 	PAD_CFG_NF(GPD9, NONE, DEEP, NF1),
+
 	/* GPD10:	Sleep S5					*/
 	PAD_NC(GPD10, NONE),
 	/* GPD11:	LAN PHY Enable					*/
diff --git a/src/mainboard/starlabs/starbook/variants/tgl/gpio.c b/src/mainboard/starlabs/starbook/variants/tgl/gpio.c
index 2a0a5382cd..08e256302f 100644
--- a/src/mainboard/starlabs/starbook/variants/tgl/gpio.c
+++ b/src/mainboard/starlabs/starbook/variants/tgl/gpio.c
@@ -17,26 +17,20 @@ const struct pad_config *variant_early_gpio_table(size_t *num)
 
 /* Pad configuration in ramstage. */
 const struct pad_config gpio_table[] = {
-	/* REFERENCE:	EP PER SCHEMATIC	*/
+	/* General Purpose I/O Deep */
+	PAD_CFG_NF(GPD0, NONE, DEEP, NF1),				/* Battery Low */
+	PAD_CFG_NF(GPD1, NONE, DEEP, NF1),				/* Charger Connected */
+	PAD_CFG_NF(GPD3, UP_20K, DEEP, NF1),				/* Power Button */
+	PAD_CFG_NF(GPD4, NONE, DEEP, NF1),				/* Sleep S3 */
+	PAD_CFG_NF(GPD5, NONE, DEEP, NF1),				/* Sleep S4 */
+	PAD_CFG_NF(GPD8, NONE, DEEP, NF1),				/* Bluetooth Suspend */
 
-	/* GPD0:	PCH_BATLOW#		*/
-	PAD_CFG_NF(GPD0, NONE, DEEP, NF1),
-	/* GPD1:	AC_PRESENT		*/
-	PAD_CFG_NF(GPD1, NONE, DEEP, NF1),
 	/* GPD2:	LAN_WAKE#		*/
 	PAD_NC(GPD2, NONE),
-	/* GPD3:	SIO_PWRBTN#		*/
-	PAD_CFG_NF(GPD3, UP_20K, DEEP, NF1),
-	/* GPD4:	SIO_SLP_S3#		*/
-	PAD_CFG_NF(GPD4, NONE, DEEP, NF1),
-	/* GPD5:	SIO_SLP_S4#		*/
-	PAD_CFG_NF(GPD5, NONE, DEEP, NF1),
 	/* GPD6:	SIO_SLP_A#		*/
 	PAD_CFG_NF(GPD6, NONE, DEEP, NF1),
 	/* GPD7:	PCH_TBT_PERST#		*/
 	PAD_CFG_GPO(GPD7, 0, PLTRST),
-	/* GPD8:	SUSCLK			*/
-	PAD_CFG_NF(GPD8, NONE, DEEP, NF1),
 	/* GPD9:	SIO_SLP_WLAN#		*/
 	PAD_CFG_NF(GPD9, NONE, DEEP, NF1),
 	/* GPD10:	SIO_SLP_S5#		*/
diff --git a/src/mainboard/starlabs/starfighter/variants/rpl/gpio.c b/src/mainboard/starlabs/starfighter/variants/rpl/gpio.c
index 6890c273ea..3ffa198653 100644
--- a/src/mainboard/starlabs/starfighter/variants/rpl/gpio.c
+++ b/src/mainboard/starlabs/starfighter/variants/rpl/gpio.c
@@ -27,24 +27,20 @@ const struct pad_config *variant_early_gpio_table(size_t *num)
 
 /* Pad configuration in ramstage. */
 const struct pad_config gpio_table[] = {
-	/* GPD0:	Battery Low					*/
-	PAD_CFG_NF(GPD0, NONE, DEEP, NF1),
-	/* GPD1:	Charger Connected				*/
-	PAD_CFG_NF(GPD1, NONE, DEEP, NF1),
+	/* General Purpose I/O Deep */
+	PAD_CFG_NF(GPD0, NONE, DEEP, NF1),				/* Battery Low */
+	PAD_CFG_NF(GPD1, NONE, DEEP, NF1),				/* Charger Connected */
+	PAD_CFG_NF(GPD3, UP_20K, DEEP, NF1),				/* Power Button */
+	PAD_NC(GPD4, NONE),						/* Sleep S3 */
+	PAD_NC(GPD5, NONE),						/* Sleep S4 */
+	PAD_CFG_NF(GPD8, NONE, DEEP, NF1),				/* Bluetooth Suspend */
+
 	/* GPD2:	LAN Wake					*/
 	PAD_NC(GPD2, NONE),
-	/* GPD3:	Power Button					*/
-	PAD_CFG_NF(GPD3, UP_20K, DEEP, NF1),
-	/* GPD4:	Sleep S3					*/
-	PAD_NC(GPD4, NONE),
-	/* GPD5:	Sleep S4					*/
-	PAD_NC(GPD5, NONE),
 	/* GPD6:	Sleep A						*/
 	PAD_NC(GPD6, NONE),
 	/* GPD7:	Power Adapter Disable				*/
 	PAD_CFG_GPO(GPD7, 0, PWROK),
-	/* GPD8:	Suspend Clock					*/
-	PAD_CFG_NF(GPD8, NONE, DEEP, NF1),
 	/* GPD9:	Wireless LAN Sleep				*/
 	PAD_CFG_NF(GPD9, NONE, DEEP, NF1),
 	/* GPD10:	Sleep S5					*/
diff --git a/src/mainboard/starlabs/starlite_adl/variants/mk_v/gpio.c b/src/mainboard/starlabs/starlite_adl/variants/mk_v/gpio.c
index 8dea7a51cd..4e96453403 100644
--- a/src/mainboard/starlabs/starlite_adl/variants/mk_v/gpio.c
+++ b/src/mainboard/starlabs/starlite_adl/variants/mk_v/gpio.c
@@ -17,24 +17,20 @@ const struct pad_config *variant_early_gpio_table(size_t *num)
 
 /* Pad configuration in ramstage. */
 const struct pad_config gpio_table[] = {
-	/* GPD0:	Battery Low					*/
-	PAD_CFG_NF(GPD0, NONE, DEEP, NF1),
-	/* GPD1:	Charger Connected				*/
-	PAD_CFG_NF(GPD1, NONE, DEEP, NF1),
+	/* General Purpose I/O Deep */
+	PAD_CFG_NF(GPD0, NONE, DEEP, NF1),				/* Battery Low */
+	PAD_CFG_NF(GPD1, NONE, DEEP, NF1),				/* Charger Connected */
+	PAD_CFG_NF(GPD3, UP_20K, DEEP, NF1),				/* Power Button */
+	PAD_NC(GPD4, NONE),						/* Sleep S3 */
+	PAD_NC(GPD5, NONE),						/* Sleep S4 */
+	PAD_CFG_NF(GPD8, NONE, DEEP, NF1),				/* Bluetooth Suspend */
+
 	/* GPD2:	LAN Wake					*/
 	PAD_NC(GPD2, NONE),
-	/* GPD3:	Power Button					*/
-	PAD_CFG_NF(GPD3, UP_20K, DEEP, NF1),
-	/* GPD4:	Sleep S3					*/
-	PAD_NC(GPD4, NONE),
-	/* GPD5:	Sleep S4					*/
-	PAD_NC(GPD5, NONE),
 	/* GPD6:	Sleep A						*/
 	PAD_NC(GPD6, NONE),
 	/* GPD7:	Power Adapter Disable				*/
 	PAD_CFG_GPO(GPD7, 0, PWROK),
-	/* GPD8:	Suspend Clock					*/
-	PAD_CFG_NF(GPD8, NONE, DEEP, NF1),
 	/* GPD9:	Wireless LAN Sleep				*/
 	PAD_NC(GPD9, NONE),
 	/* GPD10:	Sleep S5					*/

From d2fa941e496c23717c0e298339d2def88f14e7aa Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Wed, 2 Apr 2025 11:23:31 +0100
Subject: [PATCH 0584/3886] mb/starlabs/starbook/*: Tidy GPIO comments for eSPI

This is a non-functional change, and only makes the GPIOs easier to
read.

Change-Id: Id6a30adbc434c975cda1cdcffd164650910e1da3
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87101
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
---
 .../starlabs/byte_adl/variants/mk_ii/gpio.c   | 16 +++++++------
 .../starlabs/starbook/variants/adl/gpio.c     | 16 +++++++------
 .../starlabs/starbook/variants/mtl/gpio.c     | 23 ++++++++-----------
 .../starlabs/starbook/variants/rpl/gpio.c     | 16 +++++++------
 .../starlabs/starbook/variants/tgl/gpio.c     |  6 -----
 .../starlabs/starfighter/variants/rpl/gpio.c  | 16 +++++++------
 .../starlite_adl/variants/mk_v/gpio.c         | 16 +++++++------
 7 files changed, 54 insertions(+), 55 deletions(-)

diff --git a/src/mainboard/starlabs/byte_adl/variants/mk_ii/gpio.c b/src/mainboard/starlabs/byte_adl/variants/mk_ii/gpio.c
index 3814debf22..dbbd7da87c 100644
--- a/src/mainboard/starlabs/byte_adl/variants/mk_ii/gpio.c
+++ b/src/mainboard/starlabs/byte_adl/variants/mk_ii/gpio.c
@@ -25,6 +25,15 @@ const struct pad_config gpio_table[] = {
 	PAD_NC(GPD5, NONE),						/* Sleep S4 */
 	PAD_CFG_NF(GPD8, NONE, DEEP, NF1),				/* Bluetooth Suspend */
 
+	/* eSPI */
+	// PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_A0, UP_20K, DEEP, NF1),	/* eSPI IO 0 */
+	// PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_A1, UP_20K, DEEP, NF1),	/* eSPI IO 1 */
+	// PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_A2, UP_20K, DEEP, NF1),	/* eSPI IO 2 */
+	// PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_A3, UP_20K, DEEP, NF1),	/* eSPI IO 3 */
+	// PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_A4, UP_20K, DEEP, NF1),	/* eSPI CS 0 */
+	// PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_A9, UP_20K, DEEP, NF1),	/* eSPI Clk */
+	// PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_A10, NONE, DEEP, NF1),	/* eSPI Reset */
+
 	/* GPD2:	LAN Wake					*/
 	PAD_NC(GPD2, NONE),
 	/* GPD6:	Sleep A						*/
@@ -38,11 +47,6 @@ const struct pad_config gpio_table[] = {
 	/* GPD11:	LAN PHY Enable					*/
 	PAD_NC(GPD11, NONE),
 
-	/* A0:		ESPI IO 0					*/
-	/* A1:		ESPI IO 1					*/
-	/* A2:		ESPI IO 2					*/
-	/* A3:		ESPI IO 3					*/
-	/* A4:		ESPI CS 0					*/
 	/* A5:		Not Connected					*/
 	PAD_NC(GPP_A5, NONE),
 	/* A6:		Not Connected					*/
@@ -51,8 +55,6 @@ const struct pad_config gpio_table[] = {
 	PAD_NC(GPP_A7, NONE),
 	/* A8:		Not Connected					*/
 	PAD_NC(GPP_A8, NONE),
-	/* A9:		ESPI Clock					*/
-	/* A10:		ESPI Reset					*/
 	/* A11:		Webcam Camera Reset				*/
 	PAD_NC(GPP_A11, NONE),
 	/* A12:		PCH M.2 SSD PEDET				*/
diff --git a/src/mainboard/starlabs/starbook/variants/adl/gpio.c b/src/mainboard/starlabs/starbook/variants/adl/gpio.c
index 619b3154fc..0e6816dd10 100644
--- a/src/mainboard/starlabs/starbook/variants/adl/gpio.c
+++ b/src/mainboard/starlabs/starbook/variants/adl/gpio.c
@@ -25,6 +25,15 @@ const struct pad_config gpio_table[] = {
 	PAD_NC(GPD5, NONE),						/* Sleep S4 */
 	PAD_CFG_NF(GPD8, NONE, DEEP, NF1),				/* Bluetooth Suspend */
 
+	/* eSPI */
+	// PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_A0, UP_20K, DEEP, NF1),	/* eSPI IO 0 */
+	// PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_A1, UP_20K, DEEP, NF1),	/* eSPI IO 1 */
+	// PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_A2, UP_20K, DEEP, NF1),	/* eSPI IO 2 */
+	// PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_A3, UP_20K, DEEP, NF1),	/* eSPI IO 3 */
+	// PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_A4, UP_20K, DEEP, NF1),	/* eSPI CS 0 */
+	// PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_A9, UP_20K, DEEP, NF1),	/* eSPI Clk */
+	// PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_A10, NONE, DEEP, NF1),	/* eSPI Reset */
+
 	/* GPD2:	LAN Wake					*/
 	PAD_NC(GPD2, NONE),
 	/* GPD6:	Sleep A						*/
@@ -38,11 +47,6 @@ const struct pad_config gpio_table[] = {
 	/* GPD11:	LAN PHY Enable					*/
 	PAD_NC(GPD11, NONE),
 
-	/* A0:		ESPI IO 0					*/
-	/* A1:		ESPI IO 1					*/
-	/* A2:		ESPI IO 2					*/
-	/* A3:		ESPI IO 3					*/
-	/* A4:		ESPI CS 0					*/
 	/* A5:		Not Connected					*/
 	PAD_NC(GPP_A5, NONE),
 	/* A6:		Not Connected					*/
@@ -51,8 +55,6 @@ const struct pad_config gpio_table[] = {
 	PAD_NC(GPP_A7, NONE),
 	/* A8:		Not Connected					*/
 	PAD_NC(GPP_A8, NONE),
-	/* A9:		ESPI Clock					*/
-	/* A10:		ESPI Reset					*/
 	/* A11:		Not Connected					*/
 	PAD_NC(GPP_A11, NONE),
 	/* A12:		PCH M.2 SSD PEDET				*/
diff --git a/src/mainboard/starlabs/starbook/variants/mtl/gpio.c b/src/mainboard/starlabs/starbook/variants/mtl/gpio.c
index c3b4c6db2d..c5e3c263f4 100644
--- a/src/mainboard/starlabs/starbook/variants/mtl/gpio.c
+++ b/src/mainboard/starlabs/starbook/variants/mtl/gpio.c
@@ -30,6 +30,15 @@ const struct pad_config gpio_table[] = {
 	PAD_CFG_NF(GPP_V05, NONE, DEEP, NF1),				/* Sleep S4 */
 	PAD_CFG_NF(GPP_V08, NONE, DEEP, NF1),				/* Bluetooth Suspend */
 
+	/* eSPI */
+	// PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_A00, UP_20K, DEEP, NF1),	/* eSPI IO 0 */
+	// PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_A01, UP_20K, DEEP, NF1),	/* eSPI IO 1 */
+	// PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_A02, UP_20K, DEEP, NF1),	/* eSPI IO 2 */
+	// PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_A03, UP_20K, DEEP, NF1),	/* eSPI IO 3 */
+	// PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_A04, UP_20K, DEEP, NF1),	/* eSPI CS 0 */
+	// PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_A05, UP_20K, DEEP, NF1),	/* eSPI Clk */
+	// PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_A06, NONE, DEEP, NF1),	/* eSPI Reset */
+
 	/* V02:	PCIE_WAKE_LAN			*/
 	PAD_NC(GPP_V02, NONE),
 	/* V06:	GPD_6_SLP_A_N			*/
@@ -129,20 +138,6 @@ const struct pad_config gpio_table[] = {
 	 * Start:	GPP_A00
 	 * End:		GPP_A23
 	 */
-	/* A00:	ESPI_IO0_EC_R			*/
-	PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_A00, UP_20K, DEEP, NF1),
-	/* A01:	ESPI_IO1_EC_R			*/
-	PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_A01, UP_20K, DEEP, NF1),
-	/* A02:	ESPI_IO2_EC_R			*/
-	PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_A02, UP_20K, DEEP, NF1),
-	/* A03:	ESPI_IO3_EC_R			*/
-	PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_A03, UP_20K, DEEP, NF1),
-	/* A04:	ESPI_CS0_N			*/
-	PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_A04, UP_20K, DEEP, NF1),
-	/* A05:	ESPI_CLK_EC_R			*/
-	PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_A05, UP_20K, DEEP, NF1),
-	/* A06:	ESPI_RESET_N			*/
-	PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_A06, NONE, DEEP, NF1),
 	/* A07:					*/
 	PAD_NC(GPP_A07, NONE),
 	/* A08:					*/
diff --git a/src/mainboard/starlabs/starbook/variants/rpl/gpio.c b/src/mainboard/starlabs/starbook/variants/rpl/gpio.c
index 1aeb866bda..817230ae0b 100644
--- a/src/mainboard/starlabs/starbook/variants/rpl/gpio.c
+++ b/src/mainboard/starlabs/starbook/variants/rpl/gpio.c
@@ -25,6 +25,15 @@ const struct pad_config gpio_table[] = {
 	PAD_NC(GPD5, NONE),						/* Sleep S4 */
 	PAD_CFG_NF(GPD8, NONE, DEEP, NF1),				/* Bluetooth Suspend */
 
+	/* eSPI */
+	// PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_A0, UP_20K, DEEP, NF1),	/* eSPI IO 0 */
+	// PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_A1, UP_20K, DEEP, NF1),	/* eSPI IO 1 */
+	// PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_A2, UP_20K, DEEP, NF1),	/* eSPI IO 2 */
+	// PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_A3, UP_20K, DEEP, NF1),	/* eSPI IO 3 */
+	// PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_A4, UP_20K, DEEP, NF1),	/* eSPI CS 0 */
+	// PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_A9, UP_20K, DEEP, NF1),	/* eSPI Clk */
+	// PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_A10, NONE, DEEP, NF1),	/* eSPI Reset */
+
 	/* GPD2:	LAN Wake					*/
 	PAD_NC(GPD2, NONE),
 	/* GPD6:	Sleep A						*/
@@ -39,11 +48,6 @@ const struct pad_config gpio_table[] = {
 	/* GPD11:	LAN PHY Enable					*/
 	PAD_NC(GPD11, NONE),
 
-	/* A0:		ESPI IO 0					*/
-	/* A1:		ESPI IO 1					*/
-	/* A2:		ESPI IO 2					*/
-	/* A3:		ESPI IO 3					*/
-	/* A4:		ESPI CS 0					*/
 	/* A5:		Not Connected					*/
 	PAD_NC(GPP_A5, NONE),
 	/* A6:		Not Connected					*/
@@ -52,8 +56,6 @@ const struct pad_config gpio_table[] = {
 	PAD_NC(GPP_A7, NONE),
 	/* A8:		Not Connected					*/
 	PAD_NC(GPP_A8, NONE),
-	/* A9:		ESPI Clock					*/
-	/* A10:		ESPI Reset					*/
 	/* A11:		Not Connected					*/
 	PAD_NC(GPP_A11, NONE),
 	/* A12:		PCH M.2 SSD PEDET				*/
diff --git a/src/mainboard/starlabs/starbook/variants/tgl/gpio.c b/src/mainboard/starlabs/starbook/variants/tgl/gpio.c
index 08e256302f..3c1997056e 100644
--- a/src/mainboard/starlabs/starbook/variants/tgl/gpio.c
+++ b/src/mainboard/starlabs/starbook/variants/tgl/gpio.c
@@ -38,12 +38,6 @@ const struct pad_config gpio_table[] = {
 	/* GPD11:	PM_LANPHY_EN		*/
 	PAD_CFG_NF(GPD11, NONE, DEEP, NF1),
 
-	/* A0:	ESPI_IO_0			*/
-	/* A1:	ESPI_IO_1			*/
-	/* A2:	ESPI_IO_2			*/
-	/* A3:	ESPI_IO_3			*/
-	/* A4:	ESPI_CS_L			*/
-	/* A5:	ESPI_CLK			*/
 	/* A6:	Not Connected(TP764)		*/
 	/* A7:	WLAN_PCM_CLK			*/
 	PAD_NC(GPP_A7, NONE),
diff --git a/src/mainboard/starlabs/starfighter/variants/rpl/gpio.c b/src/mainboard/starlabs/starfighter/variants/rpl/gpio.c
index 3ffa198653..4f464675b7 100644
--- a/src/mainboard/starlabs/starfighter/variants/rpl/gpio.c
+++ b/src/mainboard/starlabs/starfighter/variants/rpl/gpio.c
@@ -35,6 +35,15 @@ const struct pad_config gpio_table[] = {
 	PAD_NC(GPD5, NONE),						/* Sleep S4 */
 	PAD_CFG_NF(GPD8, NONE, DEEP, NF1),				/* Bluetooth Suspend */
 
+	/* eSPI */
+	// PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_A0, UP_20K, DEEP, NF1),	/* eSPI IO 0 */
+	// PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_A1, UP_20K, DEEP, NF1),	/* eSPI IO 1 */
+	// PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_A2, UP_20K, DEEP, NF1),	/* eSPI IO 2 */
+	// PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_A3, UP_20K, DEEP, NF1),	/* eSPI IO 3 */
+	// PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_A4, UP_20K, DEEP, NF1),	/* eSPI CS 0 */
+	// PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_A9, UP_20K, DEEP, NF1),	/* eSPI Clk */
+	// PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_A10, NONE, DEEP, NF1),	/* eSPI Reset */
+
 	/* GPD2:	LAN Wake					*/
 	PAD_NC(GPD2, NONE),
 	/* GPD6:	Sleep A						*/
@@ -48,11 +57,6 @@ const struct pad_config gpio_table[] = {
 	/* GPD11:	LAN PHY Enable					*/
 	PAD_NC(GPD11, NONE),
 
-	/* A0:		ESPI IO 0					*/
-	/* A1:		ESPI IO 1					*/
-	/* A2:		ESPI IO 2					*/
-	/* A3:		ESPI IO 3					*/
-	/* A4:		ESPI CS 0					*/
 	/* A5:		Not Connected					*/
 	PAD_NC(GPP_A5, NONE),
 	/* A6:		Not Connected					*/
@@ -61,8 +65,6 @@ const struct pad_config gpio_table[] = {
 	PAD_NC(GPP_A7, NONE),
 	/* A8:		Not Connected					*/
 	PAD_NC(GPP_A8, NONE),
-	/* A9:		ESPI Clock					*/
-	/* A10:		ESPI Reset					*/
 	/* A11:		Not Connected					*/
 	PAD_NC(GPP_A11, NONE),
 	/* A12:		PCH M.2 SSD PEDET				*/
diff --git a/src/mainboard/starlabs/starlite_adl/variants/mk_v/gpio.c b/src/mainboard/starlabs/starlite_adl/variants/mk_v/gpio.c
index 4e96453403..64e7b834ec 100644
--- a/src/mainboard/starlabs/starlite_adl/variants/mk_v/gpio.c
+++ b/src/mainboard/starlabs/starlite_adl/variants/mk_v/gpio.c
@@ -25,6 +25,15 @@ const struct pad_config gpio_table[] = {
 	PAD_NC(GPD5, NONE),						/* Sleep S4 */
 	PAD_CFG_NF(GPD8, NONE, DEEP, NF1),				/* Bluetooth Suspend */
 
+	/* eSPI */
+	// PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_A0, UP_20K, DEEP, NF1),	/* eSPI IO 0 */
+	// PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_A1, UP_20K, DEEP, NF1),	/* eSPI IO 1 */
+	// PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_A2, UP_20K, DEEP, NF1),	/* eSPI IO 2 */
+	// PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_A3, UP_20K, DEEP, NF1),	/* eSPI IO 3 */
+	// PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_A4, UP_20K, DEEP, NF1),	/* eSPI CS 0 */
+	// PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_A9, UP_20K, DEEP, NF1),	/* eSPI Clk */
+	// PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_A10, NONE, DEEP, NF1),	/* eSPI Reset */
+
 	/* GPD2:	LAN Wake					*/
 	PAD_NC(GPD2, NONE),
 	/* GPD6:	Sleep A						*/
@@ -38,11 +47,6 @@ const struct pad_config gpio_table[] = {
 	/* GPD11:	LAN PHY Enable					*/
 	PAD_NC(GPD11, NONE),
 
-	/* A0:		ESPI IO 0					*/
-	/* A1:		ESPI IO 1					*/
-	/* A2:		ESPI IO 2					*/
-	/* A3:		ESPI IO 3					*/
-	/* A4:		ESPI CS 0					*/
 	/* A5:		Not Connected					*/
 	PAD_NC(GPP_A5, NONE),
 	/* A6:		Not Connected					*/
@@ -51,8 +55,6 @@ const struct pad_config gpio_table[] = {
 	PAD_NC(GPP_A7, NONE),
 	/* A8:		Not Connected					*/
 	PAD_NC(GPP_A8, NONE),
-	/* A9:		ESPI Clock					*/
-	/* A10:		ESPI Reset					*/
 	/* A11:		Webcam Camera Reset				*/
 	PAD_NC(GPP_A11, NONE),
 	/* A12:		Not Connected					*/

From e7de832d12d72ae43b73e6927cb5ebf31fb72b89 Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Wed, 2 Apr 2025 11:34:46 +0100
Subject: [PATCH 0585/3886] mb/starlabs/starbook/*: Tidy GPIO comments for the
 touchpad

This is a non-functional change, and only makes the GPIOs easier to read.

Change-Id: I9563f1d3f464b3be35d18d6cd6fbbcee314fce28
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87102
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/starlabs/starbook/variants/adl/gpio.c   | 11 +++++------
 src/mainboard/starlabs/starbook/variants/cml/gpio.c   | 11 +++++------
 src/mainboard/starlabs/starbook/variants/kbl/gpio.c   | 11 +++++------
 src/mainboard/starlabs/starbook/variants/mtl/gpio.c   | 11 +++++------
 src/mainboard/starlabs/starbook/variants/rpl/gpio.c   | 11 +++++------
 src/mainboard/starlabs/starbook/variants/tgl/gpio.c   | 11 +++++------
 .../starlabs/starfighter/variants/rpl/gpio.c          | 11 +++++------
 7 files changed, 35 insertions(+), 42 deletions(-)

diff --git a/src/mainboard/starlabs/starbook/variants/adl/gpio.c b/src/mainboard/starlabs/starbook/variants/adl/gpio.c
index 0e6816dd10..38aefd0e73 100644
--- a/src/mainboard/starlabs/starbook/variants/adl/gpio.c
+++ b/src/mainboard/starlabs/starbook/variants/adl/gpio.c
@@ -34,6 +34,11 @@ const struct pad_config gpio_table[] = {
 	// PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_A9, UP_20K, DEEP, NF1),	/* eSPI Clk */
 	// PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_A10, NONE, DEEP, NF1),	/* eSPI Reset */
 
+	/* Touchpad */
+	PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1),				/* Data */
+	PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1),				/* Clock */
+	PAD_CFG_GPI_APIC_LOW(GPP_E12, NONE, PLTRST),			/* Interrupt */
+
 	/* GPD2:	LAN Wake					*/
 	PAD_NC(GPD2, NONE),
 	/* GPD6:	Sleep A						*/
@@ -259,8 +264,6 @@ const struct pad_config gpio_table[] = {
 	PAD_NC(GPP_E10, NONE),
 	/* E11:		TPM IRQ						*/
 	PAD_CFG_GPI_APIC_LOW(GPP_E11, NONE, PLTRST),
-	/* E12:		Touchpad Interrupt				*/
-	PAD_CFG_GPI_APIC_LOW(GPP_E12, NONE, PLTRST),
 	/* E13:		Not connected					*/
 	PAD_NC(GPP_E13, NONE),
 	/* E14:		EDP HPD						*/
@@ -343,10 +346,6 @@ const struct pad_config gpio_table[] = {
 	PAD_CFG_GPO(GPP_H2, 1, PLTRST),
 	/* H3:		Not Connected					*/
 	PAD_NC(GPP_H3, NONE),
-	/* H4:		I2C 0 SDA		Touchpad		*/
-	PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1),
-	/* H5:		I2C 0 SDL		Touchpad		*/
-	PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1),
 	/* H6:		Not Connected					*/
 	PAD_NC(GPP_H6, NONE),
 	/* H7:		Not Connected					*/
diff --git a/src/mainboard/starlabs/starbook/variants/cml/gpio.c b/src/mainboard/starlabs/starbook/variants/cml/gpio.c
index da734839d7..7958b40818 100644
--- a/src/mainboard/starlabs/starbook/variants/cml/gpio.c
+++ b/src/mainboard/starlabs/starbook/variants/cml/gpio.c
@@ -34,6 +34,11 @@ const struct pad_config gpio_table[] = {
 	PAD_CFG_NF(GPD5, NONE, DEEP, NF1),				/* Sleep S4 */
 	PAD_CFG_NF(GPD8, NONE, DEEP, NF1),				/* Bluetooth Suspend */
 
+	/* Touchpad */
+	PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1),				/* Data */
+	PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1),				/* Clock */
+	PAD_CFG_GPI_APIC_LOW(GPP_B3, NONE, PLTRST),			/* Interrupt */
+
 	/* GPD2:	LAN_WAKE#		*/
 	PAD_NC(GPD2, NONE),
 	/* GPD6:	SIO_SLP_A#		*/
@@ -102,8 +107,6 @@ const struct pad_config gpio_table[] = {
 	PAD_NC(GPP_B1, NONE),
 	/* B2:	Not Connected			*/
 	PAD_NC(GPP_B2, NONE),
-	/* B3:	CLICK_PAD_INT_R_N		*/
-	PAD_CFG_GPI_APIC_LOW(GPP_B3, NONE, PLTRST),
 	/* B4:	BT_RF_KILL_N			*/
 	PAD_CFG_GPO(GPP_B4, 1, DEEP),
 	/* B5:	 WLAN_CLKREQ#			*/
@@ -177,10 +180,6 @@ const struct pad_config gpio_table[] = {
 	PAD_NC(GPP_C14, NONE),
 	/* C15:	 TBT_RST_N			*/
 	PAD_NC(GPP_C15, NONE),
-	/* C16:	 I2C0_SDA			*/
-	PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1),
-	/* C17:	 I2C0_SCL			*/
-	PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1),
 	/* C18:	 TOUCH_I2C_SDA			*/
 	PAD_NC(GPP_C18, NONE),
 	/* C19:	 TOUCH_I2C_SDL			*/
diff --git a/src/mainboard/starlabs/starbook/variants/kbl/gpio.c b/src/mainboard/starlabs/starbook/variants/kbl/gpio.c
index 6cffc5fdad..d9a075b25b 100644
--- a/src/mainboard/starlabs/starbook/variants/kbl/gpio.c
+++ b/src/mainboard/starlabs/starbook/variants/kbl/gpio.c
@@ -25,6 +25,11 @@ const struct pad_config gpio_table[] = {
 	PAD_CFG_NF(GPD5, NONE, PWROK, NF1),				/* Sleep S4 */
 	PAD_CFG_NF(GPD8, NONE, PWROK, NF1),				/* Bluetooth Suspend */
 
+	/* Touchpad */
+	PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1),				/* Data */
+	PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1),				/* Clock */
+	PAD_CFG_GPI_APIC_LOW(GPP_C23, NONE, PLTRST),			/* Interrupt */
+
 	/* GPD2:	Not Connected		*/
 	PAD_NC(GPD2, NONE),
 	/* GPD6:	Not Connected		*/
@@ -165,18 +170,12 @@ const struct pad_config gpio_table[] = {
 	PAD_NC(GPP_C14, UP_20K),
 	/* GPP_C15:	Not Connected		*/
 	PAD_NC(GPP_C15, UP_20K),
-	/* GPP_C16:	DAT_I2C_TP		*/
-	PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1),
-	/* GPP_C17:	CLK_I2C_TP		*/
-	PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1),
 	/* GPP_C18:	TOUCH_I2C_SDA		*/
 	PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1),
 	/* GPP_C19:	TOUCH_I2C_CLK		*/
 	PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1),
 	/* GPP_C22:	Not Connected		*/
 	PAD_NC(GPP_C22, NONE),
-	/* GPP_C23:	TOUCHPAD_INT		*/
-	PAD_CFG_GPI_APIC_LOW(GPP_C23, NONE, PLTRST),
 	/* GPP_D0:	Not Connected		*/
 	PAD_NC(GPP_D0, DN_20K),
 	/* GPP_D1:	Not Connected		*/
diff --git a/src/mainboard/starlabs/starbook/variants/mtl/gpio.c b/src/mainboard/starlabs/starbook/variants/mtl/gpio.c
index c5e3c263f4..468b4a719c 100644
--- a/src/mainboard/starlabs/starbook/variants/mtl/gpio.c
+++ b/src/mainboard/starlabs/starbook/variants/mtl/gpio.c
@@ -39,6 +39,11 @@ const struct pad_config gpio_table[] = {
 	// PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_A05, UP_20K, DEEP, NF1),	/* eSPI Clk */
 	// PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_A06, NONE, DEEP, NF1),	/* eSPI Reset */
 
+	/* Touchpad */
+	PAD_CFG_NF(GPP_H19, NONE, DEEP, NF1),				/* Data */
+	PAD_CFG_NF(GPP_H20, NONE, DEEP, NF1),				/* Clock */
+	PAD_CFG_GPI_APIC(GPP_B00, NONE, DEEP, LEVEL, INVERT),		/* Interrupt */
+
 	/* V02:	PCIE_WAKE_LAN			*/
 	PAD_NC(GPP_V02, NONE),
 	/* V06:	GPD_6_SLP_A_N			*/
@@ -272,10 +277,6 @@ const struct pad_config gpio_table[] = {
 	PAD_CFG_NF(GPP_H17, NONE, DEEP, NF1),
 	/* H18:					*/
 	PAD_NC(GPP_H18, NONE),
-	/* H19:	TCHPAD_I2C0_SDA_N		*/
-	PAD_CFG_NF(GPP_H19, NONE, DEEP, NF1),
-	/* H20:	TCHPAD_I2C0_SCL_N		*/
-	PAD_CFG_NF(GPP_H20, NONE, DEEP, NF1),
 	/* H21:					*/
 	PAD_NC(GPP_H21, NONE),
 	/* H22:					*/
@@ -373,8 +374,6 @@ const struct pad_config gpio_table[] = {
 	 * Start:	GPP_B00
 	 * End:		GPP_B23
 	 */
-	/* B00:	TCHPAD_INT_N			*/
-	PAD_CFG_GPI_APIC(GPP_B00, NONE, DEEP, LEVEL, INVERT),
 	/* B01:					*/
 	PAD_NC(GPP_B01, NONE),
 	/* B02:					*/
diff --git a/src/mainboard/starlabs/starbook/variants/rpl/gpio.c b/src/mainboard/starlabs/starbook/variants/rpl/gpio.c
index 817230ae0b..96e9797c47 100644
--- a/src/mainboard/starlabs/starbook/variants/rpl/gpio.c
+++ b/src/mainboard/starlabs/starbook/variants/rpl/gpio.c
@@ -34,6 +34,11 @@ const struct pad_config gpio_table[] = {
 	// PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_A9, UP_20K, DEEP, NF1),	/* eSPI Clk */
 	// PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_A10, NONE, DEEP, NF1),	/* eSPI Reset */
 
+	/* Touchpad */
+	PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1),				/* Data */
+	PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1),				/* Clock */
+	PAD_CFG_GPI_APIC_LOW(GPP_E12, NONE, PLTRST),			/* Interrupt */
+
 	/* GPD2:	LAN Wake					*/
 	PAD_NC(GPD2, NONE),
 	/* GPD6:	Sleep A						*/
@@ -260,8 +265,6 @@ const struct pad_config gpio_table[] = {
 	PAD_NC(GPP_E10, NONE),
 	/* E11:		TPM IRQ						*/
 	PAD_CFG_GPI_APIC_LOW(GPP_E11, NONE, PLTRST),
-	/* E12:		Touchpad Interrupt				*/
-	PAD_CFG_GPI_APIC_LOW(GPP_E12, NONE, PLTRST),
 	/* E13:		Not connected					*/
 	PAD_NC(GPP_E13, NONE),
 	/* E14:		EDP HPD						*/
@@ -344,10 +347,6 @@ const struct pad_config gpio_table[] = {
 	PAD_CFG_GPO(GPP_H2, 1, PLTRST),
 	/* H3:		Not Connected					*/
 	PAD_NC(GPP_H3, NONE),
-	/* H4:		I2C 0 SDA		Touchpad		*/
-	PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1),
-	/* H5:		I2C 0 SDL		Touchpad		*/
-	PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1),
 	/* H6:		Not Connected					*/
 	PAD_NC(GPP_H6, NONE),
 	/* H7:		Not Connected					*/
diff --git a/src/mainboard/starlabs/starbook/variants/tgl/gpio.c b/src/mainboard/starlabs/starbook/variants/tgl/gpio.c
index 3c1997056e..f8e178d80e 100644
--- a/src/mainboard/starlabs/starbook/variants/tgl/gpio.c
+++ b/src/mainboard/starlabs/starbook/variants/tgl/gpio.c
@@ -25,6 +25,11 @@ const struct pad_config gpio_table[] = {
 	PAD_CFG_NF(GPD5, NONE, DEEP, NF1),				/* Sleep S4 */
 	PAD_CFG_NF(GPD8, NONE, DEEP, NF1),				/* Bluetooth Suspend */
 
+	/* Touchpad */
+	PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1),				/* Data */
+	PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1),				/* Clock */
+	PAD_CFG_GPI_APIC_LOW(GPP_C8, NONE, PLTRST),			/* Interrupt */
+
 	/* GPD2:	LAN_WAKE#		*/
 	PAD_NC(GPD2, NONE),
 	/* GPD6:	SIO_SLP_A#		*/
@@ -139,8 +144,6 @@ const struct pad_config gpio_table[] = {
 	PAD_CFG_NF(GPP_C6, NONE, PWROK, NF1),
 	/* C7:	SML1_DATA			*/
 	PAD_CFG_NF(GPP_C7, NONE, PWROK, NF1),
-	/* C8:	CLICK_PAD_INT_N			*/
-	PAD_CFG_GPI_APIC_LOW(GPP_C8, NONE, PLTRST),
 	/* C9:	Not Connected			*/
 	PAD_NC(GPP_C9, NONE),
 	/* C10:	Not Connected			*/
@@ -155,10 +158,6 @@ const struct pad_config gpio_table[] = {
 	PAD_CFG_NF(GPP_C14, NONE, DEEP, NF1),
 	/* C15:	TPM_RST				*/
 	PAD_NC(GPP_C15, NONE),
-	/* C16:	I2C0_SDA			*/
-	PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1),
-	/* C17:	I2C0_SCL			*/
-	PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1),
 	/* C18:	TOUCH_I2C_SDA			*/
 	PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1),
 	/* C19:	TOUCH_I2C_CLK			*/
diff --git a/src/mainboard/starlabs/starfighter/variants/rpl/gpio.c b/src/mainboard/starlabs/starfighter/variants/rpl/gpio.c
index 4f464675b7..5cb167a9a8 100644
--- a/src/mainboard/starlabs/starfighter/variants/rpl/gpio.c
+++ b/src/mainboard/starlabs/starfighter/variants/rpl/gpio.c
@@ -44,6 +44,11 @@ const struct pad_config gpio_table[] = {
 	// PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_A9, UP_20K, DEEP, NF1),	/* eSPI Clk */
 	// PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_A10, NONE, DEEP, NF1),	/* eSPI Reset */
 
+	/* Touchpad */
+	PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1),				/* Data */
+	PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1),				/* Clock */
+	PAD_CFG_GPI_APIC_LOW(GPP_D11, NONE, PLTRST),			/* Interrupt */
+
 	/* GPD2:	LAN Wake					*/
 	PAD_NC(GPD2, NONE),
 	/* GPD6:	Sleep A						*/
@@ -220,8 +225,6 @@ const struct pad_config gpio_table[] = {
 	PAD_NC(GPP_D9, NONE),
 	/* D10:		TPM_IRQ						*/
 	PAD_CFG_GPI_APIC_LOW(GPP_D10, NONE, PLTRST),
-	/* D11:		TCHPAD_INT_N					*/
-	PAD_CFG_GPI_APIC_LOW(GPP_D11, NONE, PLTRST),
 	/* D12:		ES8336_INT_N					*/
 	PAD_NC(GPP_D12, NONE),
 	/* D13:		Wireless LAN Wake				*/
@@ -341,10 +344,6 @@ const struct pad_config gpio_table[] = {
 	PAD_CFG_GPO(GPP_H2, 1, PLTRST),
 	/* H3:		Not Connected					*/
 	PAD_NC(GPP_H3, NONE),
-	/* H4:		I2C 0 SDA		Touchpad		*/
-	PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1),
-	/* H5:		I2C 0 SDL		Touchpad		*/
-	PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1),
 	/* H6:		Not Connected					*/
 	PAD_NC(GPP_H6, NONE),
 	/* H7:		Not Connected					*/

From fa598433fc5ee9946a6eae7c36974d51320bd7a8 Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Wed, 2 Apr 2025 11:59:25 +0100
Subject: [PATCH 0586/3886] mb/starlabs/starbook/*: Tidy GPIO comments for the
 SSD

This is a non-functional change, and only makes the GPIOs easier to read.

Change-Id: Ifd24ca28d66e5e987129a44b6682efab9b64049b
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87103
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 .../starlabs/byte_adl/variants/mk_ii/gpio.c          | 11 +++++------
 src/mainboard/starlabs/starbook/variants/adl/gpio.c  | 11 +++++------
 src/mainboard/starlabs/starbook/variants/cml/gpio.c  |  5 +++--
 src/mainboard/starlabs/starbook/variants/kbl/gpio.c  |  5 +++--
 src/mainboard/starlabs/starbook/variants/mtl/gpio.c  | 12 +++++-------
 src/mainboard/starlabs/starbook/variants/rpl/gpio.c  | 11 +++++------
 src/mainboard/starlabs/starbook/variants/tgl/gpio.c  | 11 +++++------
 .../starlabs/starfighter/variants/rpl/gpio.c         | 11 +++++------
 .../starlabs/starlite_adl/variants/mk_v/gpio.c       | 11 +++++------
 9 files changed, 41 insertions(+), 47 deletions(-)

diff --git a/src/mainboard/starlabs/byte_adl/variants/mk_ii/gpio.c b/src/mainboard/starlabs/byte_adl/variants/mk_ii/gpio.c
index dbbd7da87c..c71a3908eb 100644
--- a/src/mainboard/starlabs/byte_adl/variants/mk_ii/gpio.c
+++ b/src/mainboard/starlabs/byte_adl/variants/mk_ii/gpio.c
@@ -34,6 +34,11 @@ const struct pad_config gpio_table[] = {
 	// PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_A9, UP_20K, DEEP, NF1),	/* eSPI Clk */
 	// PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_A10, NONE, DEEP, NF1),	/* eSPI Reset */
 
+	/* SSD */
+	PAD_CFG_NF(GPP_D5, NONE, DEEP, NF1),				/* Clock Request 0 */
+	PAD_CFG_GPO(GPP_H0, 1, PLTRST),					/* Reset */
+	PAD_CFG_GPO(GPP_D16, 1, DEEP),					/* Enable */
+
 	/* GPD2:	LAN Wake					*/
 	PAD_NC(GPD2, NONE),
 	/* GPD6:	Sleep A						*/
@@ -203,8 +208,6 @@ const struct pad_config gpio_table[] = {
 	PAD_NC(GPP_D3, NONE),
 	/* D4:		Not Connected					*/
 	PAD_NC(GPP_D4, NONE),
-	/* D5:		Clock Request 0		PCH M.2 SSD		*/
-	PAD_CFG_NF(GPP_D5, NONE, DEEP, NF1),
 	/* D6:		Clock Request 1		Wireless LAN		*/
 	PAD_NC(GPP_D6, NONE),
 	/* D7:		Clock Request 2		LAN 1			*/
@@ -225,8 +228,6 @@ const struct pad_config gpio_table[] = {
 	PAD_NC(GPP_D14, NONE),
 	/* D15:		Not Connected					*/
 	PAD_NC(GPP_D15, NONE),
-	/* D16:		PCH M.2 SSD Power Enable			*/
-	PAD_CFG_GPO(GPP_D16, 1, DEEP),
 	/* D17:		Not Connected					*/
 	PAD_NC(GPP_D17, NONE),
 	/* D18:		Not Connected					*/
@@ -336,8 +337,6 @@ const struct pad_config gpio_table[] = {
 	/* F23:		Not Connected					*/
 	PAD_NC(GPP_F23, NONE),
 
-	/* H0:		PCH M.2 SSD Reset				*/
-	PAD_CFG_GPO(GPP_H0, 1, PLTRST),
 	/* H1:		BFX Strap 2 Bit 3	Weak Internal PD 20K	*/
 	PAD_CFG_GPO(GPP_H1, 0, DEEP),
 	/* H2:		Wireless LAN Reset				*/
diff --git a/src/mainboard/starlabs/starbook/variants/adl/gpio.c b/src/mainboard/starlabs/starbook/variants/adl/gpio.c
index 38aefd0e73..4e067de05a 100644
--- a/src/mainboard/starlabs/starbook/variants/adl/gpio.c
+++ b/src/mainboard/starlabs/starbook/variants/adl/gpio.c
@@ -39,6 +39,11 @@ const struct pad_config gpio_table[] = {
 	PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1),				/* Clock */
 	PAD_CFG_GPI_APIC_LOW(GPP_E12, NONE, PLTRST),			/* Interrupt */
 
+	/* SSD */
+	PAD_CFG_NF(GPP_D6, NONE, DEEP, NF1),				/* Clock Request 1 */
+	PAD_CFG_GPO(GPP_D16, 1, DEEP),					/* Enable */
+	PAD_CFG_GPO(GPP_H0, 1, PLTRST),					/* Reset */
+
 	/* GPD2:	LAN Wake					*/
 	PAD_NC(GPD2, NONE),
 	/* GPD6:	Sleep A						*/
@@ -209,8 +214,6 @@ const struct pad_config gpio_table[] = {
 	PAD_NC(GPP_D4, NONE),
 	/* D5:		Clock Request 0					*/
 	PAD_NC(GPP_D5, NONE),
-	/* D6:		Clock Request 1		PCH M.2 SSD		*/
-	PAD_CFG_NF(GPP_D6, NONE, DEEP, NF1),
 	/* D7:		Clock Request 2		Wireless LAN		*/
 	PAD_CFG_NF(GPP_D7, NONE, DEEP, NF1),
 	/* D8:		Clock Request 3		LAN			*/
@@ -229,8 +232,6 @@ const struct pad_config gpio_table[] = {
 	PAD_NC(GPP_D14, NONE),
 	/* D15:		Not Connected					*/
 	PAD_NC(GPP_D15, NONE),
-	/* D16:		PCH M.2 SSD Power Enable			*/
-	PAD_CFG_GPO(GPP_D16, 1, DEEP),
 	/* D17:		Not used		Fingerprint ID		*/
 	PAD_NC(GPP_D17, NONE),
 	/* D18:		Not Connected					*/
@@ -338,8 +339,6 @@ const struct pad_config gpio_table[] = {
 	/* F23:		Not Connected					*/
 	PAD_NC(GPP_F23, NONE),
 
-	/* H0:		PCH M.2 SSD Reset				*/
-	PAD_CFG_GPO(GPP_H0, 1, PLTRST),
 	/* H1:		BFX Strap 2 Bit 3	Weak Internal PD 20K	*/
 	PAD_CFG_GPO(GPP_H1, 0, DEEP),
 	/* H2:		Wireless LAN Reset				*/
diff --git a/src/mainboard/starlabs/starbook/variants/cml/gpio.c b/src/mainboard/starlabs/starbook/variants/cml/gpio.c
index 7958b40818..18fdbe0cf0 100644
--- a/src/mainboard/starlabs/starbook/variants/cml/gpio.c
+++ b/src/mainboard/starlabs/starbook/variants/cml/gpio.c
@@ -39,6 +39,9 @@ const struct pad_config gpio_table[] = {
 	PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1),				/* Clock */
 	PAD_CFG_GPI_APIC_LOW(GPP_B3, NONE, PLTRST),			/* Interrupt */
 
+	/* SSD */
+	PAD_CFG_NF(GPP_B6, NONE, DEEP, NF1),				/* Clock Request 1 */
+
 	/* GPD2:	LAN_WAKE#		*/
 	PAD_NC(GPD2, NONE),
 	/* GPD6:	SIO_SLP_A#		*/
@@ -111,8 +114,6 @@ const struct pad_config gpio_table[] = {
 	PAD_CFG_GPO(GPP_B4, 1, DEEP),
 	/* B5:	 WLAN_CLKREQ#			*/
 	PAD_CFG_NF(GPP_B5, NONE, DEEP, NF1),
-	/* B6:	 CLKREQ1_SSD_N			*/
-	PAD_CFG_NF(GPP_B6, NONE, DEEP, NF1),
 	/* B7:	 LAN_CLKREQ#			*/
 	PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1),
 	/* B8:	Not Connected			*/
diff --git a/src/mainboard/starlabs/starbook/variants/kbl/gpio.c b/src/mainboard/starlabs/starbook/variants/kbl/gpio.c
index d9a075b25b..957ca9a721 100644
--- a/src/mainboard/starlabs/starbook/variants/kbl/gpio.c
+++ b/src/mainboard/starlabs/starbook/variants/kbl/gpio.c
@@ -30,6 +30,9 @@ const struct pad_config gpio_table[] = {
 	PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1),				/* Clock */
 	PAD_CFG_GPI_APIC_LOW(GPP_C23, NONE, PLTRST),			/* Interrupt */
 
+	/* SSD */
+	PAD_CFG_NF(GPP_B10, DN_20K, DEEP, NF1),				/* Clock Request 5 */
+
 	/* GPD2:	Not Connected		*/
 	PAD_NC(GPD2, NONE),
 	/* GPD6:	Not Connected		*/
@@ -110,8 +113,6 @@ const struct pad_config gpio_table[] = {
 	PAD_CFG_NF(GPP_B8, DN_20K, DEEP, NF1),
 	/* GPP_B9:	WLAN_CLKREQ#		*/
 	PAD_CFG_NF(GPP_B9, NONE, DEEP, NF1),
-	/* GPP_B10:	CLKREQ5#		*/
-	PAD_CFG_NF(GPP_B10, DN_20K, DEEP, NF1),
 	/* GPP_B11:	Not Connected		*/
 	PAD_NC(GPP_B11, DN_20K),
 	/* GPP_B12	SLP_S0_N		*/
diff --git a/src/mainboard/starlabs/starbook/variants/mtl/gpio.c b/src/mainboard/starlabs/starbook/variants/mtl/gpio.c
index 468b4a719c..3b15bb8aba 100644
--- a/src/mainboard/starlabs/starbook/variants/mtl/gpio.c
+++ b/src/mainboard/starlabs/starbook/variants/mtl/gpio.c
@@ -44,6 +44,11 @@ const struct pad_config gpio_table[] = {
 	PAD_CFG_NF(GPP_H20, NONE, DEEP, NF1),				/* Clock */
 	PAD_CFG_GPI_APIC(GPP_B00, NONE, DEEP, LEVEL, INVERT),		/* Interrupt */
 
+	/* SSD */
+	PAD_CFG_NF(GPP_D20, NONE, DEEP, NF1),				/* Clock Request 8 */
+	PAD_CFG_GPO(GPP_H00, 1, PLTRST),				/* Reset */
+	PAD_CFG_GPO(GPP_H07, 1, PLTRST),				/* Enable */
+
 	/* V02:	PCIE_WAKE_LAN			*/
 	PAD_NC(GPP_V02, NONE),
 	/* V06:	GPD_6_SLP_A_N			*/
@@ -240,8 +245,6 @@ const struct pad_config gpio_table[] = {
 	 * Start:	GPP_H00
 	 * End:		GPP_H23
 	 */
-	/* H00:	M.2_PCH_SSD_RESET_N		*/
-	PAD_CFG_GPO(GPP_H00, 1, PLTRST),
 	/* H01:	FLASH RECOVERY
 	 *		HIGH:	ENABLED
 	 *		LOW:	DISABLED
@@ -257,8 +260,6 @@ const struct pad_config gpio_table[] = {
 	PAD_NC(GPP_H05, NONE),
 	/* H06:					*/
 	PAD_NC(GPP_H06, NONE),
-	/* H07:	M.2_CPU_SSD_PWREN		*/
-	PAD_CFG_GPO(GPP_H07, 1, DEEP),
 	/* H10:					*/
 	PAD_NC(GPP_H10, NONE),
 	/* H11:					*/
@@ -473,9 +474,6 @@ const struct pad_config gpio_table[] = {
 	PAD_NC(GPP_D18, NONE),
 	/* D19:					*/
 	PAD_NC(GPP_D19, NONE),
-	/* D20: CLKREQ8
-	 *			SSD		*/
-	PAD_CFG_NF(GPP_D20, NONE, DEEP, NF1),
 	/* D21:	CLKREQ5
 	 *			WLAN		*/
 	PAD_CFG_NF(GPP_D21, NONE, DEEP, NF2),
diff --git a/src/mainboard/starlabs/starbook/variants/rpl/gpio.c b/src/mainboard/starlabs/starbook/variants/rpl/gpio.c
index 96e9797c47..309da16446 100644
--- a/src/mainboard/starlabs/starbook/variants/rpl/gpio.c
+++ b/src/mainboard/starlabs/starbook/variants/rpl/gpio.c
@@ -39,6 +39,11 @@ const struct pad_config gpio_table[] = {
 	PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1),				/* Clock */
 	PAD_CFG_GPI_APIC_LOW(GPP_E12, NONE, PLTRST),			/* Interrupt */
 
+	/* SSD */
+	PAD_CFG_NF(GPP_H19, NONE, DEEP, NF1),				/* Clock Request 4 */
+	PAD_CFG_GPO(GPP_F20, 1, PLTRST),				/* Reset */
+	PAD_CFG_GPO(GPP_D14, 1, DEEP),					/* Enable */
+
 	/* GPD2:	LAN Wake					*/
 	PAD_NC(GPD2, NONE),
 	/* GPD6:	Sleep A						*/
@@ -226,8 +231,6 @@ const struct pad_config gpio_table[] = {
 	PAD_NC(GPP_D12, NONE),
 	/* D13:		Wireless LAN Wake				*/
 	PAD_NC(GPP_D13, NONE),
-	/* D14:		CPU M.2 SSD Power Enable			*/
-	PAD_CFG_GPO(GPP_D14, 1, DEEP),
 	/* D15:		Not Connected					*/
 	PAD_NC(GPP_D15, NONE),
 	/* D16:		PCH M.2 SSD Power Enable			*/
@@ -330,8 +333,6 @@ const struct pad_config gpio_table[] = {
 	PAD_NC(GPP_F18, NONE),
 	/* F19:		Not Connected					*/
 	PAD_NC(GPP_F19, NONE),
-	/* F20:		CPU M.2 SSD Reset				*/
-	PAD_CFG_GPO(GPP_F20, 1, PLTRST),
 	/* F21:		GPPC_F21					*/
 	PAD_NC(GPP_F21, NONE),
 	/* F22:		Not Connected					*/
@@ -369,8 +370,6 @@ const struct pad_config gpio_table[] = {
 	PAD_CFG_NF(GPP_H17, NONE, DEEP, NF1),
 	/* H18:		CPI C10 Gate					*/
 	PAD_CFG_NF(GPP_H18, NONE, DEEP, NF1),
-	/* H19:		Clock Request 4		CPU M.2 SSD		*/
-	PAD_CFG_NF(GPP_H19, NONE, DEEP, NF1),
 	/* H20:		Not Connected					*/
 	PAD_NC(GPP_H20, NONE),
 	/* H21:		Not Connected					*/
diff --git a/src/mainboard/starlabs/starbook/variants/tgl/gpio.c b/src/mainboard/starlabs/starbook/variants/tgl/gpio.c
index f8e178d80e..ca081ff641 100644
--- a/src/mainboard/starlabs/starbook/variants/tgl/gpio.c
+++ b/src/mainboard/starlabs/starbook/variants/tgl/gpio.c
@@ -30,6 +30,11 @@ const struct pad_config gpio_table[] = {
 	PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1),				/* Clock */
 	PAD_CFG_GPI_APIC_LOW(GPP_C8, NONE, PLTRST),			/* Interrupt */
 
+	/* SSD */
+	PAD_NC(GPP_D8, NONE),						/* Clock Request 3 */
+	PAD_CFG_GPO(GPP_A11, 1, PLTRST),				/* Reset */
+	PAD_CFG_GPO(GPP_D16, 1, DEEP),					/* Enable */
+
 	/* GPD2:	LAN_WAKE#		*/
 	PAD_NC(GPD2, NONE),
 	/* GPD6:	SIO_SLP_A#		*/
@@ -52,8 +57,6 @@ const struct pad_config gpio_table[] = {
 	PAD_CFG_NF(GPP_A9, NONE, DEEP, NF2),
 	/* A10:	WLAN_PCM_IN			*/
 	PAD_NC(GPP_A10, NONE),
-	/* A11:	M2_CPU_SSD_RST_N		*/
-	PAD_CFG_GPO(GPP_A11, 1, PLTRST),
 	/* A12:	SATAGP_1			*/
 	PAD_CFG_NF(GPP_A12, UP_20K, DEEP, NF1),
 	/* A13:	Not Connected			*/
@@ -183,8 +186,6 @@ const struct pad_config gpio_table[] = {
 	PAD_NC(GPP_D6, NONE),
 	/* D7:	LAN_CLKREQ#			*/
 	PAD_NC(GPP_D7, NONE),
-	/* D8:	Not Connected			*/
-	PAD_NC(GPP_D8, NONE),
 	/* D9:	Not Connected			*/
 	PAD_NC(GPP_D9, NONE),
 	/* D10:	Not Connected			*/
@@ -199,8 +200,6 @@ const struct pad_config gpio_table[] = {
 	PAD_NC(GPP_D14, NONE),
 	/* D15:	Not Connected			*/
 	PAD_NC(GPP_D15, NONE),
-	/* D16:	CPU_SSD_PWREN			*/
-	PAD_CFG_GPO(GPP_D16, 1, DEEP),
 	/* D17:	Not Connected			*/
 	PAD_NC(GPP_D17, NONE),
 	/* D18:	Not Connected			*/
diff --git a/src/mainboard/starlabs/starfighter/variants/rpl/gpio.c b/src/mainboard/starlabs/starfighter/variants/rpl/gpio.c
index 5cb167a9a8..080f95d127 100644
--- a/src/mainboard/starlabs/starfighter/variants/rpl/gpio.c
+++ b/src/mainboard/starlabs/starfighter/variants/rpl/gpio.c
@@ -49,6 +49,11 @@ const struct pad_config gpio_table[] = {
 	PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1),				/* Clock */
 	PAD_CFG_GPI_APIC_LOW(GPP_D11, NONE, PLTRST),			/* Interrupt */
 
+	/* SSD */
+	PAD_CFG_NF(GPP_D6, NONE, DEEP, NF1),				/* Clock Request 5 */
+	PAD_CFG_GPO(GPP_F20, 1, PLTRST),				/* Reset */
+	PAD_CFG_GPO(GPP_D14, 1, DEEP),					/* Enable */
+
 	/* GPD2:	LAN Wake					*/
 	PAD_NC(GPD2, NONE),
 	/* GPD6:	Sleep A						*/
@@ -215,8 +220,6 @@ const struct pad_config gpio_table[] = {
 	PAD_NC(GPP_D4, NONE),
 	/* D5:		Clock Request 0					*/
 	PAD_NC(GPP_D5, NONE),
-	/* D6:		Clock Request 1		PCH M.2 SSD		*/
-	PAD_CFG_NF(GPP_D6, NONE, DEEP, NF1),
 	/* D7:		Clock Request 2		Wireless LAN		*/
 	PAD_CFG_NF(GPP_D7, NONE, DEEP, NF1),
 	/* D8:		Clock Request 3		LAN			*/
@@ -229,8 +232,6 @@ const struct pad_config gpio_table[] = {
 	PAD_NC(GPP_D12, NONE),
 	/* D13:		Wireless LAN Wake				*/
 	PAD_NC(GPP_D13, NONE),
-	/* D14:		CPU M.2 SSD Power Enable			*/
-	PAD_CFG_GPO(GPP_D14, 1, DEEP),
 	/* D15:		Not Connected					*/
 	PAD_NC(GPP_D15, NONE),
 	/* D16:		PCH M.2 SSD Power Enable			*/
@@ -327,8 +328,6 @@ const struct pad_config gpio_table[] = {
 	PAD_NC(GPP_F18, NONE),
 	/* F19:		Not Connected					*/
 	PAD_NC(GPP_F19, NONE),
-	/* F20:		CPU M.2 SSD Reset				*/
-	PAD_CFG_GPO(GPP_F20, 1, PLTRST),
 	/* F21:		GPPC_F21					*/
 	PAD_NC(GPP_F21, NONE),
 	/* F22:		Not Connected					*/
diff --git a/src/mainboard/starlabs/starlite_adl/variants/mk_v/gpio.c b/src/mainboard/starlabs/starlite_adl/variants/mk_v/gpio.c
index 64e7b834ec..6a0db68a74 100644
--- a/src/mainboard/starlabs/starlite_adl/variants/mk_v/gpio.c
+++ b/src/mainboard/starlabs/starlite_adl/variants/mk_v/gpio.c
@@ -34,6 +34,11 @@ const struct pad_config gpio_table[] = {
 	// PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_A9, UP_20K, DEEP, NF1),	/* eSPI Clk */
 	// PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_A10, NONE, DEEP, NF1),	/* eSPI Reset */
 
+	/* SSD */
+	PAD_CFG_NF(GPP_D5, NONE, DEEP, NF1),				/* Clock Request 0 */
+	PAD_CFG_GPO(GPP_H0, 1, PLTRST),					/* Reset */
+	PAD_CFG_GPO(GPP_D16, 1, DEEP),					/* Enable */
+
 	/* GPD2:	LAN Wake					*/
 	PAD_NC(GPD2, NONE),
 	/* GPD6:	Sleep A						*/
@@ -201,8 +206,6 @@ const struct pad_config gpio_table[] = {
 	PAD_NC(GPP_D3, NONE),
 	/* D4:		Camera Image Clock Output			*/
 	PAD_NC(GPP_D4, NONE),
-	/* D5:		Clock Request 0		PCH M.2 SSD		*/
-	PAD_CFG_NF(GPP_D5, NONE, DEEP, NF1),
 	/* D6:		Clock Request 1		Wireless LAN		*/
 	PAD_NC(GPP_D6, NONE),
 	/* D7:		Clock Request 2					*/
@@ -223,8 +226,6 @@ const struct pad_config gpio_table[] = {
 	PAD_NC(GPP_D14, NONE),
 	/* D15:		Not Connected					*/
 	PAD_NC(GPP_D15, NONE),
-	/* D16:		PCH M.2 SSD Power Enable			*/
-	PAD_CFG_GPO(GPP_D16, 1, DEEP),
 	/* D17:		Not used		Fingerprint ID		*/
 	PAD_NC(GPP_D17, NONE),
 	/* D18:		Bluetooth Wake					*/
@@ -334,8 +335,6 @@ const struct pad_config gpio_table[] = {
 	/* F23:		Not Connected					*/
 	PAD_NC(GPP_F23, NONE),
 
-	/* H0:		PCH M.2 SSD Reset				*/
-	PAD_CFG_GPO(GPP_H0, 1, PLTRST),
 	/* H1:		BFX Strap 2 Bit 3	Weak Internal PD 20K	*/
 	PAD_CFG_GPO(GPP_H1, 0, DEEP),
 	/* H2:		Wireless LAN Reset				*/

From ddb09fce6e828c681cfee13479ef45fd41de131c Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Wed, 2 Apr 2025 12:56:13 +0100
Subject: [PATCH 0587/3886] mb/starlabs/starbook/*: Tidy GPIO comments for the
 wireless

This is a non-functional change, and only makes the GPIOs easier to read.

Change-Id: I5643fe19f349facffab218e0e8da02d88f192e73
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87105
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
---
 .../starlabs/byte_adl/variants/mk_ii/gpio.c   | 26 +++++++----------
 .../starlabs/starbook/variants/adl/gpio.c     | 14 ++++------
 .../starlabs/starbook/variants/cml/gpio.c     | 28 ++++++++-----------
 .../starlabs/starbook/variants/kbl/gpio.c     |  8 +++---
 .../starlabs/starbook/variants/mtl/gpio.c     | 15 ++++------
 .../starlabs/starbook/variants/rpl/gpio.c     | 14 ++++------
 .../starlabs/starbook/variants/tgl/gpio.c     | 17 +++++------
 .../starlabs/starfighter/variants/rpl/gpio.c  | 14 ++++------
 .../starlite_adl/variants/mk_v/gpio.c         | 26 +++++++----------
 9 files changed, 66 insertions(+), 96 deletions(-)

diff --git a/src/mainboard/starlabs/byte_adl/variants/mk_ii/gpio.c b/src/mainboard/starlabs/byte_adl/variants/mk_ii/gpio.c
index c71a3908eb..8653f4b015 100644
--- a/src/mainboard/starlabs/byte_adl/variants/mk_ii/gpio.c
+++ b/src/mainboard/starlabs/byte_adl/variants/mk_ii/gpio.c
@@ -39,6 +39,16 @@ const struct pad_config gpio_table[] = {
 	PAD_CFG_GPO(GPP_H0, 1, PLTRST),					/* Reset */
 	PAD_CFG_GPO(GPP_D16, 1, DEEP),					/* Enable */
 
+	/* Wireless */
+	PAD_CFG_NF(GPP_F0, NONE, DEEP, NF1),				/* BRI Data */
+	PAD_CFG_NF(GPP_F1, UP_20K, DEEP, NF1),				/* BRI Response */
+	PAD_CFG_NF(GPP_F2, NONE, DEEP, NF1),				/* RGI Data */
+	PAD_CFG_NF(GPP_F3, UP_20K, DEEP, NF1),				/* RGI Response */
+	PAD_CFG_NF(GPP_F4, NONE, DEEP, NF1),				/* RF Reset */
+	PAD_CFG_NF(GPP_F5, NONE, DEEP, NF2),				/* Modem Clock Request */
+	PAD_CFG_GPO(GPP_E3, 1, DEEP),					/* WiFi RF Kill */
+	PAD_CFG_GPO(GPP_A13, 1, DEEP),					/* Bluetooth RF Kill */
+
 	/* GPD2:	LAN Wake					*/
 	PAD_NC(GPD2, NONE),
 	/* GPD6:	Sleep A						*/
@@ -64,8 +74,6 @@ const struct pad_config gpio_table[] = {
 	PAD_NC(GPP_A11, NONE),
 	/* A12:		PCH M.2 SSD PEDET				*/
 	PAD_CFG_NF(GPP_A12, NONE, DEEP, NF1),
-	/* A13:		BlueTooth RF Kill				*/
-	PAD_CFG_GPO(GPP_A13, 1, DEEP),
 	/* A14:		Type C VBUS OverCurrent				*/
 	PAD_CFG_NF(GPP_A14, NONE, DEEP, NF1),
 	/* A15:		Test Point 3					*/
@@ -241,8 +249,6 @@ const struct pad_config gpio_table[] = {
 	PAD_NC(GPP_E1, NONE),
 	/* E2:		Not Connected					*/
 	PAD_NC(GPP_E2, NONE),
-	/* E3:		WiFi RF Kill					*/
-	PAD_CFG_GPO(GPP_E3, 1, DEEP),
 	/* E4:		Test Point 7					*/
 	PAD_NC(GPP_E4, NONE),
 	/* E5:		Not Connected					*/
@@ -286,18 +292,6 @@ const struct pad_config gpio_table[] = {
 	/* E23:		Not Connected					*/
 	PAD_NC(GPP_E23, NONE),
 
-	/* F0:		CNV BRI Data					*/
-	PAD_CFG_NF(GPP_F0, NONE, DEEP, NF1),
-	/* F1:		CNV BRI Response				*/
-	PAD_CFG_NF(GPP_F1, UP_20K, DEEP, NF1),
-	/* F2:		CNV RGI Data					*/
-	PAD_CFG_NF(GPP_F2, NONE, DEEP, NF1),
-	/* F3:		CNV RGI Response				*/
-	PAD_CFG_NF(GPP_F3, UP_20K, DEEP, NF1),
-	/* F4:		CNV RF Reset					*/
-	PAD_CFG_NF(GPP_F4, NONE, DEEP, NF1),
-	/* F5:		Not used		MODEM_CLKREQ		*/
-	PAD_CFG_NF(GPP_F5, NONE, DEEP, NF2),
 	/* F6:		CNV PA Blanking					*/
 	PAD_NC(GPP_F6, NONE),
 	/* F7:		TBT LSX VCCIO		Weak Internal PD 20K
diff --git a/src/mainboard/starlabs/starbook/variants/adl/gpio.c b/src/mainboard/starlabs/starbook/variants/adl/gpio.c
index 4e067de05a..60786b5230 100644
--- a/src/mainboard/starlabs/starbook/variants/adl/gpio.c
+++ b/src/mainboard/starlabs/starbook/variants/adl/gpio.c
@@ -44,6 +44,12 @@ const struct pad_config gpio_table[] = {
 	PAD_CFG_GPO(GPP_D16, 1, DEEP),					/* Enable */
 	PAD_CFG_GPO(GPP_H0, 1, PLTRST),					/* Reset */
 
+	/* Wireless */
+	PAD_CFG_NF(GPP_D7, NONE, DEEP, NF1),				/* Clock Request 1 */
+	PAD_CFG_GPO(GPP_H2, 1, PLTRST),					/* Reset */
+	PAD_CFG_GPO(GPP_E3, 1, DEEP),					/* WiFi RF Kill */
+	PAD_CFG_GPO(GPP_A13, 1, DEEP),					/* Bluetooth RF Kill */
+
 	/* GPD2:	LAN Wake					*/
 	PAD_NC(GPD2, NONE),
 	/* GPD6:	Sleep A						*/
@@ -69,8 +75,6 @@ const struct pad_config gpio_table[] = {
 	PAD_NC(GPP_A11, NONE),
 	/* A12:		PCH M.2 SSD PEDET				*/
 	PAD_CFG_NF(GPP_A12, NONE, DEEP, NF1),
-	/* A13:		BlueTooth RF Kill				*/
-	PAD_CFG_GPO(GPP_A13, 1, DEEP),
 	/* A14:		Test Point 45					*/
 	PAD_NC(GPP_A14, NONE),
 	/* A15:		Test Point 52					*/
@@ -214,8 +218,6 @@ const struct pad_config gpio_table[] = {
 	PAD_NC(GPP_D4, NONE),
 	/* D5:		Clock Request 0					*/
 	PAD_NC(GPP_D5, NONE),
-	/* D7:		Clock Request 2		Wireless LAN		*/
-	PAD_CFG_NF(GPP_D7, NONE, DEEP, NF1),
 	/* D8:		Clock Request 3		LAN			*/
 	PAD_NC(GPP_D8, NONE),
 	/* D9:		GSPI 2 FPS					*/
@@ -245,8 +247,6 @@ const struct pad_config gpio_table[] = {
 	PAD_NC(GPP_E1, NONE),
 	/* E2:		Not Connected					*/
 	PAD_NC(GPP_E2, NONE),
-	/* E3:		WiFi RF Kill					*/
-	PAD_CFG_GPO(GPP_E3, 1, DEEP),
 	/* E4:		Test Point 14					*/
 	PAD_NC(GPP_E4, NONE),
 	/* E5:		Not Connected					*/
@@ -341,8 +341,6 @@ const struct pad_config gpio_table[] = {
 
 	/* H1:		BFX Strap 2 Bit 3	Weak Internal PD 20K	*/
 	PAD_CFG_GPO(GPP_H1, 0, DEEP),
-	/* H2:		Wireless LAN Reset				*/
-	PAD_CFG_GPO(GPP_H2, 1, PLTRST),
 	/* H3:		Not Connected					*/
 	PAD_NC(GPP_H3, NONE),
 	/* H6:		Not Connected					*/
diff --git a/src/mainboard/starlabs/starbook/variants/cml/gpio.c b/src/mainboard/starlabs/starbook/variants/cml/gpio.c
index 18fdbe0cf0..8f2ca8223d 100644
--- a/src/mainboard/starlabs/starbook/variants/cml/gpio.c
+++ b/src/mainboard/starlabs/starbook/variants/cml/gpio.c
@@ -42,6 +42,16 @@ const struct pad_config gpio_table[] = {
 	/* SSD */
 	PAD_CFG_NF(GPP_B6, NONE, DEEP, NF1),				/* Clock Request 1 */
 
+	/* Wireless */
+	PAD_CFG_NF(GPP_F4, UP_20K, DEEP, NF1),				/* BRI Data */
+	PAD_CFG_NF(GPP_F5, UP_20K, DEEP, NF1),				/* BRI Response */
+	PAD_CFG_NF(GPP_F6, UP_20K, DEEP, NF1),				/* RGI Data */
+	PAD_CFG_NF(GPP_F7, UP_20K, DEEP, NF1),				/* RGI Response */
+	PAD_CFG_NF(GPP_H1, UP_20K, DEEP, NF3),				/* RF Reset */
+	PAD_CFG_NF(GPP_H2, UP_20K, DEEP, NF3),				/* Modem Clock Request */
+	PAD_CFG_GPO(GPP_C2, 1, DEEP),					/* WiFi RF Kill */
+	PAD_CFG_GPO(GPP_B4, 1, DEEP),					/* Bluetooth RF Kill */
+
 	/* GPD2:	LAN_WAKE#		*/
 	PAD_NC(GPD2, NONE),
 	/* GPD6:	SIO_SLP_A#		*/
@@ -110,9 +120,7 @@ const struct pad_config gpio_table[] = {
 	PAD_NC(GPP_B1, NONE),
 	/* B2:	Not Connected			*/
 	PAD_NC(GPP_B2, NONE),
-	/* B4:	BT_RF_KILL_N			*/
-	PAD_CFG_GPO(GPP_B4, 1, DEEP),
-	/* B5:	 WLAN_CLKREQ#			*/
+	/* B5:	WLAN_CLKREQ#			*/
 	PAD_CFG_NF(GPP_B5, NONE, DEEP, NF1),
 	/* B7:	 LAN_CLKREQ#			*/
 	PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1),
@@ -153,8 +161,6 @@ const struct pad_config gpio_table[] = {
 	PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1),
 	/* C1:	 SMB_DATA			*/
 	PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1),
-	/* C2:	 WIFI_RF_KILL_N			*/
-	PAD_CFG_GPO(GPP_C2, 1, DEEP),
 	/* C3:	Not Connected			*/
 	PAD_NC(GPP_C3, NONE),
 	/* C4:	Not Connected			*/
@@ -292,14 +298,6 @@ const struct pad_config gpio_table[] = {
 	PAD_NC(GPP_F2, NONE),
 	/* F3:	Not Connected			*/
 	PAD_NC(GPP_F3, NONE),
-	/* F4:	CNV_BRI_DT_R			*/
-	PAD_CFG_NF(GPP_F4, UP_20K, DEEP, NF1),
-	/* F5:	CNV_BRI_RSP			*/
-	PAD_CFG_NF(GPP_F5, UP_20K, DEEP, NF1),
-	/* F6:	CNV_RGI_DT_R			*/
-	PAD_CFG_NF(GPP_F6, UP_20K, DEEP, NF1),
-	/* F7:	CNV_RGI_RSP			*/
-	PAD_CFG_NF(GPP_F7, UP_20K, DEEP, NF1),
 	/* F8:	Not Connected			*/
 	PAD_NC(GPP_F8, NONE),
 	/* F9:	Not Connected			*/
@@ -352,10 +350,6 @@ const struct pad_config gpio_table[] = {
 
 	/* H0:	Not Connected			*/
 	PAD_NC(GPP_H0, NONE),
-	/* H1:	 GPPC_H1_SSP2_SFRM		*/
-	PAD_CFG_NF(GPP_H1, UP_20K, DEEP, NF3),
-	/* H2:	 GPPC_H2_SSP2_TXD		*/
-	PAD_CFG_NF(GPP_H2, UP_20K, DEEP, NF3),
 	/* H3:	Not Connected			*/
 	PAD_NC(GPP_H3, UP_20K),
 	/* H4:	 GSENSOR_I2C_SDA		*/
diff --git a/src/mainboard/starlabs/starbook/variants/kbl/gpio.c b/src/mainboard/starlabs/starbook/variants/kbl/gpio.c
index 957ca9a721..47864e84be 100644
--- a/src/mainboard/starlabs/starbook/variants/kbl/gpio.c
+++ b/src/mainboard/starlabs/starbook/variants/kbl/gpio.c
@@ -33,6 +33,10 @@ const struct pad_config gpio_table[] = {
 	/* SSD */
 	PAD_CFG_NF(GPP_B10, DN_20K, DEEP, NF1),				/* Clock Request 5 */
 
+	/* Wireless */
+	// PAD_CFG_GPO(GPP_D20, 1, DEEP),				/* WiFi RF Kill */
+	PAD_CFG_TERM_GPO(GPP_B4, 1, UP_20K, DEEP),			/* Bluetooth RF Kill */
+
 	/* GPD2:	Not Connected		*/
 	PAD_NC(GPD2, NONE),
 	/* GPD6:	Not Connected		*/
@@ -101,8 +105,6 @@ const struct pad_config gpio_table[] = {
 	PAD_NC(GPP_B2, DN_20K),
 	/* GPP_B3:	Not Connected		*/
 	PAD_NC(GPP_B3, DN_20K),
-	/* GPP_B4:	BT_OFF_N_MCP		*/
-	PAD_CFG_TERM_GPO(GPP_B4, 1, UP_20K, DEEP),
 	/* GPP_B5:	SRCCLKREQ0#		*/
 	PAD_CFG_NF(GPP_B5, NONE, DEEP, NF1),
 	/* GPP_B6:	CLKREQ1#		*/
@@ -217,8 +219,6 @@ const struct pad_config gpio_table[] = {
 	PAD_NC(GPP_D18, DN_20K),
 	/* GPP_D19:	Not Connected		*/
 	PAD_NC(GPP_D19, DN_20K),
-	/* GPP_D20:	WIFI_OFF_N_MCP		*/
-	PAD_CFG_TERM_GPO(GPP_D20, 1, UP_20K, DEEP),
 	/* GPP_D21:	Not Connected		*/
 	PAD_NC(GPP_D21, DN_20K),
 	/* GPP_D22:	Not Connected		*/
diff --git a/src/mainboard/starlabs/starbook/variants/mtl/gpio.c b/src/mainboard/starlabs/starbook/variants/mtl/gpio.c
index 3b15bb8aba..89670dd4eb 100644
--- a/src/mainboard/starlabs/starbook/variants/mtl/gpio.c
+++ b/src/mainboard/starlabs/starbook/variants/mtl/gpio.c
@@ -49,6 +49,12 @@ const struct pad_config gpio_table[] = {
 	PAD_CFG_GPO(GPP_H00, 1, PLTRST),				/* Reset */
 	PAD_CFG_GPO(GPP_H07, 1, PLTRST),				/* Enable */
 
+	/* Wireless */
+	PAD_CFG_NF(GPP_D21, NONE, DEEP, NF2),				/* Clock Request 5 */
+	PAD_CFG_GPO(GPP_H02, 1, PLTRST),				/* Reset */
+	PAD_CFG_GPO(GPP_B19, 1, DEEP),					/* WiFi RF Kill */
+	PAD_CFG_GPO(GPP_B18, 1, DEEP),					/* Bluetooth RF Kill */
+
 	/* V02:	PCIE_WAKE_LAN			*/
 	PAD_NC(GPP_V02, NONE),
 	/* V06:	GPD_6_SLP_A_N			*/
@@ -250,8 +256,6 @@ const struct pad_config gpio_table[] = {
 	 *		LOW:	DISABLED
 	 *		WEAK INTERNAL PD 20K	*/
 	PAD_CFG_GPO(GPP_H01, 0, DEEP),
-	/* H02:	WLAN_RST_N			*/
-	PAD_CFG_GPO(GPP_H02, 1, PLTRST),
 	/* H03:					*/
 	PAD_NC(GPP_H03, NONE),
 	/* H04:					*/
@@ -416,10 +420,6 @@ const struct pad_config gpio_table[] = {
 	PAD_CFG_NF(GPP_B16, NONE, DEEP, NF2),
 	/* B17:					*/
 	PAD_NC(GPP_B17, NONE),
-	/* B18:	BT_RF_KILL_N			*/
-	PAD_CFG_GPO(GPP_B18, 1, DEEP),
-	/* B19:	WIFI_RF_KILL_N			*/
-	PAD_CFG_GPO(GPP_B19, 1, DEEP),
 	/* B20:					*/
 	PAD_NC(GPP_B20, NONE),
 	/* B21:					*/
@@ -474,9 +474,6 @@ const struct pad_config gpio_table[] = {
 	PAD_NC(GPP_D18, NONE),
 	/* D19:					*/
 	PAD_NC(GPP_D19, NONE),
-	/* D21:	CLKREQ5
-	 *			WLAN		*/
-	PAD_CFG_NF(GPP_D21, NONE, DEEP, NF2),
 	/* D22:					*/
 	PAD_NC(GPP_D22, NONE),
 	/* D23:					*/
diff --git a/src/mainboard/starlabs/starbook/variants/rpl/gpio.c b/src/mainboard/starlabs/starbook/variants/rpl/gpio.c
index 309da16446..6e90173e51 100644
--- a/src/mainboard/starlabs/starbook/variants/rpl/gpio.c
+++ b/src/mainboard/starlabs/starbook/variants/rpl/gpio.c
@@ -44,6 +44,12 @@ const struct pad_config gpio_table[] = {
 	PAD_CFG_GPO(GPP_F20, 1, PLTRST),				/* Reset */
 	PAD_CFG_GPO(GPP_D14, 1, DEEP),					/* Enable */
 
+	/* Wireless */
+	PAD_CFG_NF(GPP_D7, NONE, DEEP, NF1),				/* Clock Request 2 */
+	PAD_CFG_GPO(GPP_H2, 1, PLTRST),					/* Reset */
+	PAD_CFG_GPO(GPP_E3, 1, DEEP),					/* WiFi RF Kill */
+	PAD_CFG_GPO(GPP_A13, 1, DEEP),					/* Bluetooth RF Kill */
+
 	/* GPD2:	LAN Wake					*/
 	PAD_NC(GPD2, NONE),
 	/* GPD6:	Sleep A						*/
@@ -70,8 +76,6 @@ const struct pad_config gpio_table[] = {
 	PAD_NC(GPP_A11, NONE),
 	/* A12:		PCH M.2 SSD PEDET				*/
 	PAD_NC(GPP_A12, NONE),
-	/* A13:		BlueTooth RF Kill				*/
-	PAD_CFG_GPO(GPP_A13, 1, DEEP),
 	/* A14:		Test Point 45					*/
 	PAD_NC(GPP_A14, NONE),
 	/* A15:		Test Point 52					*/
@@ -217,8 +221,6 @@ const struct pad_config gpio_table[] = {
 	PAD_NC(GPP_D5, NONE),
 	/* D6:		Clock Request 1		PCH M.2 SSD		*/
 	PAD_NC(GPP_D6, NONE),
-	/* D7:		Clock Request 2		Wireless LAN		*/
-	PAD_CFG_NF(GPP_D7, NONE, DEEP, NF1),
 	/* D8:		Clock Request 3		LAN			*/
 	PAD_NC(GPP_D8, NONE),
 	/* D9:		GSPI 2 FPS					*/
@@ -248,8 +250,6 @@ const struct pad_config gpio_table[] = {
 	PAD_NC(GPP_E1, NONE),
 	/* E2:		Not Connected					*/
 	PAD_NC(GPP_E2, NONE),
-	/* E3:		WiFi RF Kill					*/
-	PAD_CFG_GPO(GPP_E3, 1, DEEP),
 	/* E4:		Retimer Force Power				*/
 	PAD_CFG_GPO(GPP_E4, 0, DEEP),
 	/* E5:		Not Connected					*/
@@ -344,8 +344,6 @@ const struct pad_config gpio_table[] = {
 	PAD_NC(GPP_H0, NONE),
 	/* H1:		BFX Strap 2 Bit 3	Weak Internal PD 20K	*/
 	PAD_CFG_GPO(GPP_H1, 0, DEEP),
-	/* H2:		Wireless LAN Reset				*/
-	PAD_CFG_GPO(GPP_H2, 1, PLTRST),
 	/* H3:		Not Connected					*/
 	PAD_NC(GPP_H3, NONE),
 	/* H6:		Not Connected					*/
diff --git a/src/mainboard/starlabs/starbook/variants/tgl/gpio.c b/src/mainboard/starlabs/starbook/variants/tgl/gpio.c
index ca081ff641..89985412c1 100644
--- a/src/mainboard/starlabs/starbook/variants/tgl/gpio.c
+++ b/src/mainboard/starlabs/starbook/variants/tgl/gpio.c
@@ -35,6 +35,13 @@ const struct pad_config gpio_table[] = {
 	PAD_CFG_GPO(GPP_A11, 1, PLTRST),				/* Reset */
 	PAD_CFG_GPO(GPP_D16, 1, DEEP),					/* Enable */
 
+	/* Wireless */
+	PAD_CFG_NF(GPP_F0, NONE, DEEP, NF1),				/* BRI Data */
+	PAD_CFG_NF(GPP_F1, NONE, DEEP, NF1),				/* BRI Response */
+	PAD_CFG_NF(GPP_F2, NONE, DEEP, NF1),				/* RGI Data */
+	PAD_CFG_NF(GPP_F3, NONE, DEEP, NF1),				/* RGI Response */
+	PAD_NC(GPP_F6, NONE),						/* Modem Clock Request */
+
 	/* GPD2:	LAN_WAKE#		*/
 	PAD_NC(GPD2, NONE),
 	/* GPD6:	SIO_SLP_A#		*/
@@ -256,20 +263,10 @@ const struct pad_config gpio_table[] = {
 	/* E23:	Not Connected			*/
 	PAD_NC(GPP_E23, NONE),
 
-	/* F0:	CNV_BRI_DT_BT_UART0_RTS_R	*/
-	PAD_CFG_NF(GPP_F0, NONE, DEEP, NF1),
-	/* F1:	CNV_BRI_RSP_BT_UART0_RX_R	*/
-	PAD_CFG_NF(GPP_F1, NONE, DEEP, NF1),
-	/* F2:	CNV_RGI_DT_BT_UART0_TX_R	*/
-	PAD_CFG_NF(GPP_F2, NONE, DEEP, NF1),
-	/* F3:	CNV_RGI_RSP_BT_UART0_CTS	*/
-	PAD_CFG_NF(GPP_F3, NONE, DEEP, NF1),
 	/* F4:	Not Connected			*/
 	PAD_NC(GPP_F4, NONE),
 	/* F5:	GPPC_F5_MODEM_CLKREQ		*/
 	PAD_NC(GPP_F5, NONE),
-	/* F6:	Not Connected			*/
-	PAD_NC(GPP_F6, NONE),
 	/* F7:	BIOS_REC			*/
 	PAD_CFG_GPO(GPP_F7, 1, PLTRST),
 	/* F8:	Not Connected			*/
diff --git a/src/mainboard/starlabs/starfighter/variants/rpl/gpio.c b/src/mainboard/starlabs/starfighter/variants/rpl/gpio.c
index 080f95d127..0bf4412862 100644
--- a/src/mainboard/starlabs/starfighter/variants/rpl/gpio.c
+++ b/src/mainboard/starlabs/starfighter/variants/rpl/gpio.c
@@ -54,6 +54,12 @@ const struct pad_config gpio_table[] = {
 	PAD_CFG_GPO(GPP_F20, 1, PLTRST),				/* Reset */
 	PAD_CFG_GPO(GPP_D14, 1, DEEP),					/* Enable */
 
+	/* Wireless */
+	PAD_CFG_NF(GPP_D7, NONE, DEEP, NF1),				/* Clock Request 1 */
+	PAD_CFG_GPO(GPP_H2, 1, PLTRST),					/* Reset */
+	PAD_CFG_GPO(GPP_E3, 1, DEEP),					/* WiFi RF Kill */
+	PAD_CFG_GPO(GPP_A13, 1, DEEP),					/* Bluetooth RF Kill */
+
 	/* GPD2:	LAN Wake					*/
 	PAD_NC(GPD2, NONE),
 	/* GPD6:	Sleep A						*/
@@ -79,8 +85,6 @@ const struct pad_config gpio_table[] = {
 	PAD_NC(GPP_A11, NONE),
 	/* A12:		PCH M.2 SSD PEDET				*/
 	PAD_CFG_NF(GPP_A12, NONE, DEEP, NF1),
-	/* A13:		BlueTooth RF Kill				*/
-	PAD_CFG_GPO(GPP_A13, 1, DEEP),
 	/* A14:		Test Point 45					*/
 	PAD_NC(GPP_A14, NONE),
 	/* A15:		Test Point 52					*/
@@ -220,8 +224,6 @@ const struct pad_config gpio_table[] = {
 	PAD_NC(GPP_D4, NONE),
 	/* D5:		Clock Request 0					*/
 	PAD_NC(GPP_D5, NONE),
-	/* D7:		Clock Request 2		Wireless LAN		*/
-	PAD_CFG_NF(GPP_D7, NONE, DEEP, NF1),
 	/* D8:		Clock Request 3		LAN			*/
 	PAD_NC(GPP_D8, NONE),
 	/* D9:		PWD_AMP_IN					*/
@@ -249,8 +251,6 @@ const struct pad_config gpio_table[] = {
 	PAD_NC(GPP_E1, NONE),
 	/* E2:		Not Connected					*/
 	PAD_NC(GPP_E2, NONE),
-	/* E3:		WiFi RF Kill					*/
-	PAD_CFG_GPO(GPP_E3, 1, DEEP),
 	/* E4:		Retimer Force Power				*/
 	PAD_CFG_GPO(GPP_E4, 0, DEEP),
 	/* E5:		Not Connected					*/
@@ -339,8 +339,6 @@ const struct pad_config gpio_table[] = {
 	PAD_CFG_GPO(GPP_H0, 1, PLTRST),
 	/* H1:		BFX Strap 2 Bit 3	Weak Internal PD 20K	*/
 	PAD_CFG_GPO(GPP_H1, 0, DEEP),
-	/* H2:		Wireless LAN Reset				*/
-	PAD_CFG_GPO(GPP_H2, 1, PLTRST),
 	/* H3:		Not Connected					*/
 	PAD_NC(GPP_H3, NONE),
 	/* H6:		Not Connected					*/
diff --git a/src/mainboard/starlabs/starlite_adl/variants/mk_v/gpio.c b/src/mainboard/starlabs/starlite_adl/variants/mk_v/gpio.c
index 6a0db68a74..63bda1d78a 100644
--- a/src/mainboard/starlabs/starlite_adl/variants/mk_v/gpio.c
+++ b/src/mainboard/starlabs/starlite_adl/variants/mk_v/gpio.c
@@ -39,6 +39,16 @@ const struct pad_config gpio_table[] = {
 	PAD_CFG_GPO(GPP_H0, 1, PLTRST),					/* Reset */
 	PAD_CFG_GPO(GPP_D16, 1, DEEP),					/* Enable */
 
+	/* Wireless */
+	PAD_CFG_NF(GPP_F0, NONE, DEEP, NF1),				/* BRI Data */
+	PAD_CFG_NF(GPP_F1, UP_20K, DEEP, NF1),				/* BRI Response */
+	PAD_CFG_NF(GPP_F2, NONE, DEEP, NF1),				/* RGI Data */
+	PAD_CFG_NF(GPP_F3, UP_20K, DEEP, NF1),				/* RGI Response */
+	PAD_CFG_NF(GPP_F4, NONE, DEEP, NF1),				/* RF Reset */
+	PAD_CFG_NF(GPP_F5, NONE, DEEP, NF2),				/* Modem Clock Request */
+	PAD_CFG_GPO(GPP_E3, 1, DEEP),					/* WiFi RF Kill */
+	PAD_CFG_GPO(GPP_A13, 1, DEEP),					/* Bluetooth RF Kill */
+
 	/* GPD2:	LAN Wake					*/
 	PAD_NC(GPD2, NONE),
 	/* GPD6:	Sleep A						*/
@@ -64,8 +74,6 @@ const struct pad_config gpio_table[] = {
 	PAD_NC(GPP_A11, NONE),
 	/* A12:		Not Connected					*/
 	PAD_NC(GPP_A12, NONE),
-	/* A13:		BlueTooth RF Kill				*/
-	PAD_CFG_GPO(GPP_A13, 1, DEEP),
 	/* A14:		Camera Power Enable				*/
 	PAD_NC(GPP_A14, NONE),
 	/* A15:		Camera Reset					*/
@@ -239,8 +247,6 @@ const struct pad_config gpio_table[] = {
 	PAD_NC(GPP_E1, NONE),
 	/* E2:		Not Connected					*/
 	PAD_NC(GPP_E2, NONE),
-	/* E3:		WiFi RF Kill					*/
-	PAD_CFG_GPO(GPP_E3, 1, DEEP),
 	/* E4:		P Offset					*/
 	PAD_NC(GPP_E4, NONE),
 	/* E5:		P Out						*/
@@ -284,18 +290,6 @@ const struct pad_config gpio_table[] = {
 	/* E23:		Not Connected					*/
 	PAD_NC(GPP_E23, NONE),
 
-	/* F0:		CNV BRI Data					*/
-	PAD_CFG_NF(GPP_F0, NONE, DEEP, NF1),
-	/* F1:		CNV BRI Response				*/
-	PAD_CFG_NF(GPP_F1, UP_20K, DEEP, NF1),
-	/* F2:		CNV RGI Data					*/
-	PAD_CFG_NF(GPP_F2, NONE, DEEP, NF1),
-	/* F3:		CNV RGI Response				*/
-	PAD_CFG_NF(GPP_F3, UP_20K, DEEP, NF1),
-	/* F4:		CNV RF Reset					*/
-	PAD_CFG_NF(GPP_F4, NONE, DEEP, NF1),
-	/* F5:		Not used		MODEM_CLKREQ		*/
-	PAD_CFG_NF(GPP_F5, NONE, DEEP, NF2),
 	/* F6:		CNV PA Blanking					*/
 	PAD_NC(GPP_F6, NONE),
 	/* F7:		TBT LSX VCCIO		Weak Internal PD 20K

From 1e53a973bc89195090e773aabe24a5e19361c4f1 Mon Sep 17 00:00:00 2001
From: Martin Roth <gaumless@gmail.com>
Date: Thu, 3 Apr 2025 15:19:48 -0600
Subject: [PATCH 0588/3886] Documentation: Update 25.03 release notes

These are the final notes for the release.

Change-Id: I5daaae609b9271c543009c303db948fa7aa24b6d
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87134
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 .../releases/coreboot-25.03-relnotes.md       | 160 +++++++-----------
 1 file changed, 62 insertions(+), 98 deletions(-)

diff --git a/Documentation/releases/coreboot-25.03-relnotes.md b/Documentation/releases/coreboot-25.03-relnotes.md
index 125437b395..edf9f241fe 100644
--- a/Documentation/releases/coreboot-25.03-relnotes.md
+++ b/Documentation/releases/coreboot-25.03-relnotes.md
@@ -1,4 +1,4 @@
-Upcoming release - coreboot 25.03
+coreboot 25.03
 ========================================================================
 
 The coreboot project is pleased to announce the release of coreboot
@@ -12,8 +12,9 @@ We extend our sincere thanks to all contributors who have made this
 release possible. Your expertise and collaborative efforts continue to
 propel the coreboot project forward. As always, we value the
 participation of everyone in the community, from long-time developers to
-those new to the project. The next coreboot release, 25.06, is scheduled
-for the end of June 2025.
+those new to the project.
+
+The next coreboot release, 25.06, is scheduled for the end of June 2025.
 
 
 
@@ -77,18 +78,19 @@ This commit adds a new field to the cpu topology structure to represent
 the core ID within the package.
 
 For reference, here is that signature of the crash:
-
+```
    LAPIC 0x40 in X2APIC mode.
    CPU Index 2 - APIC 64 Unexpected Exception:13 @ 10:69f3d1e4 - Halting
    Code: 0 eflags: 00010046 cr2: 00000000
    eax: 00000001 ebx: 69f313e8 ecx: 0000004e edx: 00000000
    edi: 69f38018 esi: 00000029 ebp: 69aeee0c esp: 69aeedc0
    [...]
-
+```
 The crash occurred when FSP attempted to lock the Protected
 Processor Inventory Number Enable Control MSR (IA32_PPIN_CTL
 0x4e).
 
+```
    69f3d1d3:	8b 43 f4            	mov	-0xc(%ebx),%eax
    69f3d1d6:	89 4d c4            	mov	%ecx,-0x3c(%ebp)
    69f3d1d9:	89 45 dc            	mov	%eax,-0x24(%ebp)
@@ -97,7 +99,7 @@ Processor Inventory Number Enable Control MSR (IA32_PPIN_CTL
    69f3d1e2:	8b 4d dc            	mov	-0x24(%ebp),%ecx
    69f3d1e5:	0f 30               	wrmsr
    69f3d1e7:	e9 ee fd ff ff      	jmp	0xfffffe39
-
+```
 FSP experiences issues due to attempting to lock the same register
 multiple times for a single core. This is caused by an inconsistency in
 the processor information data structure, where multiple cores share the
@@ -115,9 +117,9 @@ low-battery indicator icon during boot.
 
 Specifically, it:
 
-- Moves Kconfig options related to low-battery notifications from
+* Moves Kconfig options related to low-battery notifications from
   drivers/intel/fsp to lib/
-- Relocates the low-battery check and shutdown APIs drivers/intel/fsp
+* Relocates the low-battery check and shutdown APIs drivers/intel/fsp
   to bootsplash.h
 * Adjusts the vendor driver to utilize the new APIs for low-battery
   rendering decisions.
@@ -224,17 +226,17 @@ Platform Updates
 Statistics from the 24.12 to the 25.03 release
 ----------------------------------------------
 
-* Total Commits: 992
-* Average Commits per day: 10.09
-* Total lines added: 87471
-* Average lines added per commit: 88.18
-* Number of patches adding more than 100 lines: 95
-* Average lines added per small commit: 40.50
-* Total lines removed: 22845
-* Average lines removed per commit: 23.03
-* Total difference between added and removed: 64626
-* Total authors: 129
-* New authors: 28
+* Total Commits: 1001
+* Average Commits per day: 10.05
+* Total lines added: 88158
+* Average lines added per commit: 88.07
+* Number of patches adding more than 100 lines: 97
+* Average lines added per small commit: 40.48
+* Total lines removed: 22900
+* Average lines removed per commit: 22.88
+* Total difference between added and removed: 65258
+* Total authors: 131
+* New authors: 29
 
 
 
@@ -243,93 +245,55 @@ Significant Known and Open Issues
 
 ### coreboot-wide or architecture-wide issues
 
-+-----+-----------------------------------------------------------------+
-| #   | Subject                                                         |
-+=====+=================================================================+
-| 519 | make gconfig - could not find glade file                        |
-+-----+-----------------------------------------------------------------+
-| 518 | make xconfig - g++: fatal error: no input files                 |
-+-----+-----------------------------------------------------------------+
+
+* 519: make gconfig - could not find glade file
+* 518: make xconfig - g++: fatal error: no input files
+
 
 
 ### Payload-specific issues
 
-+-----+-----------------------------------------------------------------+
-| #   | Subject                                                         |
-+=====+=================================================================+
-| 577 |  SeaBIOS/EDK2 Windows 10 BSOD "UNSUPPORTED PROCESSOR"           |
-+-----+-----------------------------------------------------------------+
-| 552 |  X201 not booting with edk2 payload                             |
-+-----+-----------------------------------------------------------------+
-| 549 | SeaBIOS Windows 10/11 BSOD "ACPI BIOS ERROR" (Thinkpad W530)    |
-+-----+-----------------------------------------------------------------+
-| 499 | edk2 boot fails with RESOURCE_ALLOCATION_TOP_DOWN enabled       |
-+-----+-----------------------------------------------------------------+
-| 496 | Missing malloc check in libpayload                              |
-+-----+-----------------------------------------------------------------+
-| 484 | No USB keyboard support with secondary payloads                 |
-+-----+-----------------------------------------------------------------+
-| 414 | X9SAE-V: No USB keyboard init on SeaBIOS using Radeon RX 6800XT |
-+-----+-----------------------------------------------------------------+
+
+* 577:  SeaBIOS/EDK2 Windows 10 BSOD "UNSUPPORTED PROCESSOR"
+* 552:  X201 not booting with edk2 payload
+* 549: SeaBIOS Windows 10/11 BSOD "ACPI BIOS ERROR" (Thinkpad W530)
+* 499: edk2 boot fails with RESOURCE_ALLOCATION_TOP_DOWN enabled
+* 496: Missing malloc check in libpayload
+* 484: No USB keyboard support with secondary payloads
+* 414: X9SAE-V: No USB keyboard init on SeaBIOS using Radeon RX 6800XT
+
 
 
 ### Platform-specific issues
 
-+-----+-----------------------------------------------------------------+
-| #   | Subject                                                         |
-+=====+=================================================================+
-| 579 | MAC address set by coreboot to RTL8111F does not persist        |
-+-----+-----------------------------------------------------------------+
-| 565 | Wifi card not recognized on Lenovo M700 tiny                    |
-+-----+-----------------------------------------------------------------+
-| 563 | tty doesn't show on external display using edk2 on W530         |
-+-----+-----------------------------------------------------------------+
-| 548 | Lenovo X201 Fails To Recognize Upgraded WiFi Card               |
-+-----+-----------------------------------------------------------------+
-| 538 | x230: Dock Causes Internal Display to "Permanently" Malfunction |
-+-----+-----------------------------------------------------------------+
-| 535 | T420: Power light stays off after reboot                        |
-+-----+-----------------------------------------------------------------+
-| 528 | Building qemu-i440fx with CONFIG_CBFS_VERIFICATION fails        |
-+-----+-----------------------------------------------------------------+
-| 524 | X2APIC Options cause Linux to crash on emulation/qemu-i440fx    |
-+-----+-----------------------------------------------------------------+
-| 517 | lenovo x230 boot stuck with connected external monitor          |
-+-----+-----------------------------------------------------------------+
-| 509 | SD Card hotplug not working on Apollo Lake                      |
-+-----+-----------------------------------------------------------------+
-| 506 | APL/GML don't boot OS when CPU microcode included "from tree"   |
-+-----+-----------------------------------------------------------------+
-| 505 | Harcuvar CRB - 15 of 16 cores present in the operating system   |
-+-----+-----------------------------------------------------------------+
-| 499 | T440p - EDK2 fails with RESOURCE_ALLOCATION_TOP_DOWN enabled    |
-+-----+-----------------------------------------------------------------+
-| 495 | Stoney Chromebooks not booting PSPSecureOS                      |
-+-----+-----------------------------------------------------------------+
-| 478 | X200 booting Linux takes a long time with TSC                   |
-+-----+-----------------------------------------------------------------+
-| 474 | X200s crashes after graphic init with 8GB RAM                   |
-+-----+-----------------------------------------------------------------+
-| 457 | Haswell (t440p): CAR mem region conflicts with CBFS_SIZE > 8mb  |
-+-----+-----------------------------------------------------------------+
-| 453 | Intel HDMI / DP Audio not present in Windows after libgfxinit   |
-+-----+-----------------------------------------------------------------+
-| 449 | ThinkPad T440p fail to start, continuous beeping & LED blinking |
-+-----+-----------------------------------------------------------------+
-| 448 | Thinkpad T440P ACPI Battery Value Issues                        |
-+-----+-----------------------------------------------------------------+
-| 446 | Optiplex 9010 No Post                                           |
-+-----+-----------------------------------------------------------------+
-| 439 | Lenovo X201 Turbo Boost not working (stuck on 2,4GHz)           |
-+-----+-----------------------------------------------------------------+
-| 427 | x200: Two battery charging issues                               |
-+-----+-----------------------------------------------------------------+
-| 412 | x230 reboots on suspend                                         |
-+-----+-----------------------------------------------------------------+
-| 393 | T500 restarts rather than waking up from suspend                |
-+-----+-----------------------------------------------------------------+
-| 350 | I225 PCIe device not detected on Harcuvar                       |
-+-----+-----------------------------------------------------------------+
+
+* 579: MAC address set by coreboot to RTL8111F does not persist
+* 565: Wifi card not recognized on Lenovo M700 tiny
+* 563: tty doesn't show on external display using edk2 on W530
+* 548: Lenovo X201 Fails To Recognize Upgraded WiFi Card
+* 538: x230: Dock Causes Internal Display to "Permanently" Malfunction
+* 535: T420: Power light stays off after reboot
+* 528: Building qemu-i440fx with CONFIG_CBFS_VERIFICATION fails
+* 524: X2APIC Options cause Linux to crash on emulation/qemu-i440fx
+* 517: lenovo x230 boot stuck with connected external monitor
+* 509: SD Card hotplug not working on Apollo Lake
+* 506: APL/GML don't boot OS when CPU microcode included "from tree"
+* 505: Harcuvar CRB - 15 of 16 cores present in the operating system
+* 499: T440p - EDK2 fails with RESOURCE_ALLOCATION_TOP_DOWN enabled
+* 495: Stoney Chromebooks not booting PSPSecureOS
+* 478: X200 booting Linux takes a long time with TSC
+* 474: X200s crashes after graphic init with 8GB RAM
+* 457: Haswell (t440p): CAR mem region conflicts with CBFS_SIZE > 8mb
+* 453: Intel HDMI / DP Audio not present in Windows after libgfxinit
+* 449: ThinkPad T440p fail to start, continuous beeping & LED blinking
+* 448: Thinkpad T440P ACPI Battery Value Issues
+* 446: Optiplex 9010 No Post
+* 439: Lenovo X201 Turbo Boost not working (stuck on 2,4GHz)
+* 427: x200: Two battery charging issues
+* 412: x230 reboots on suspend
+* 393: T500 restarts rather than waking up from suspend
+* 350: I225 PCIe device not detected on Harcuvar
+
 
 
 

From e9b020f02e3a481f4e0856ed549d2bafcfe03309 Mon Sep 17 00:00:00 2001
From: Subrata Banik <subratabanik@google.com>
Date: Wed, 2 Apr 2025 10:00:15 +0530
Subject: [PATCH 0589/3886] mb/google/fatcat: Allow board-specific FSP-M UPD
 override

This commit introduces a mechanism to allow mainboards to override
the default FSP-M UPDs for Panther Lake.

- Adds `variant_update_soc_memory_init_params` as a weak function
  in `variants.h` and `romstage.c` for board-specific implementations.
- In `romstage.c`, `mainboard_memory_init_params` now calls
  `variant_update_soc_memory_init_params` to apply board-specific
  overrides to the FSP-M UPDs.

This enables finer-grained control over memory initialization parameters
at the variant level.

BUG=b:328770565
TEST=Able to build and boot google/fatcat.

Change-Id: I403bc4270ef526363defa6cd7d22741ad42a8a76
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87089
Reviewed-by: Sowmya Aralguppe <sowmya.aralguppe@intel.com>
Reviewed-by: Jayvik Desai <jayvik@google.com>
Reviewed-by: Pranava Y N <pranavayn@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/google/fatcat/romstage.c                   | 9 +++++++++
 .../variants/baseboard/include/baseboard/variants.h      | 2 ++
 2 files changed, 11 insertions(+)

diff --git a/src/mainboard/google/fatcat/romstage.c b/src/mainboard/google/fatcat/romstage.c
index 7b56e28e3c..8f0000c2ce 100644
--- a/src/mainboard/google/fatcat/romstage.c
+++ b/src/mainboard/google/fatcat/romstage.c
@@ -3,6 +3,7 @@
 #include <baseboard/variants.h>
 #include <fsp/api.h>
 #include <soc/romstage.h>
+#include <soc/soc_chip.h>
 #include <string.h>
 
 /*
@@ -16,6 +17,11 @@ __weak void fw_config_configure_pre_mem_gpio(void)
 	/* Nothing to do */
 }
 
+__weak void variant_update_soc_memory_init_params(FSPM_UPD *memupd)
+{
+	/* Nothing to do */
+}
+
 void mainboard_memory_init_params(FSPM_UPD *memupd)
 {
 	const struct pad_config *pads;
@@ -33,4 +39,7 @@ void mainboard_memory_init_params(FSPM_UPD *memupd)
 	variant_get_spd_info(&spd_info);
 
 	memcfg_init(memupd, mem_config, &spd_info, half_populated);
+
+	/* Override FSP-M UPD per board if required. */
+	variant_update_soc_memory_init_params(memupd);
 }
diff --git a/src/mainboard/google/fatcat/variants/baseboard/include/baseboard/variants.h b/src/mainboard/google/fatcat/variants/baseboard/include/baseboard/variants.h
index 2a70408e0d..c080dd3572 100644
--- a/src/mainboard/google/fatcat/variants/baseboard/include/baseboard/variants.h
+++ b/src/mainboard/google/fatcat/variants/baseboard/include/baseboard/variants.h
@@ -4,6 +4,7 @@
 #define __BASEBOARD_VARIANTS_H__
 
 #include <chip.h>
+#include <fsp/api.h>
 #include <soc/gpio.h>
 #include <soc/meminit.h>
 #include <stdint.h>
@@ -23,6 +24,7 @@ const struct mb_cfg *variant_memory_params(void);
 void variant_get_spd_info(struct mem_spd *spd_info);
 int variant_memory_sku(void);
 bool variant_is_half_populated(void);
+void variant_update_soc_memory_init_params(FSPM_UPD *memupd);
 void variant_update_soc_chip_config(struct soc_intel_pantherlake_config *config);
 
 enum s0ix_entry {

From 3a88eb8cb6c6449dc622e2122abac7ae96879e7d Mon Sep 17 00:00:00 2001
From: Subrata Banik <subratabanik@google.com>
Date: Wed, 2 Apr 2025 18:14:07 +0530
Subject: [PATCH 0590/3886] mb/google/fatcat: Enable HDA SDI based on FW config
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

This commit modifies the handling of PCH High Definition Audio (HDA)
Serial Digital Interface (SDI) enablement.

- In `devicetree.cb`, the static `pch_hda_sdi_enable` property is
  removed to allow varaints to override if needed.
- In `variant.c`, `variant_update_soc_memory_init_params` is
  introduced to dynamically configure `PchHdaSdiEnable` UPD based on
  the firmware configuration (for example: `AUDIO_ALC256_HDA` or
  `AUDIO_ALC256M_CG_HDA`).
  SDI is enabled if this FW config option is present. Otherwise, it
  defaults to disabled.
- `variant.c` is now added for romstage as well because the SDI
  configuration needs to happen earlier in the boot process.

BUG=b:328770565, b:407876136
TEST=Able to reduce the boot time by 18ms for SKUs w/o HDA audio.

Change-Id: Ice28ea7445a5cb32fe8263ada363d4f45c3152f5
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87090
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
---
 .../variants/baseboard/fatcat/devicetree.cb     |  1 -
 .../google/fatcat/variants/fatcat/Makefile.mk   |  2 +-
 .../google/fatcat/variants/fatcat/variant.c     | 13 +++++++++++++
 .../google/fatcat/variants/francka/Makefile.mk  |  2 +-
 .../google/fatcat/variants/francka/variant.c    | 17 +++++++++++++++++
 5 files changed, 32 insertions(+), 3 deletions(-)
 create mode 100644 src/mainboard/google/fatcat/variants/francka/variant.c

diff --git a/src/mainboard/google/fatcat/variants/baseboard/fatcat/devicetree.cb b/src/mainboard/google/fatcat/variants/baseboard/fatcat/devicetree.cb
index f9c79adc8f..aa297b1a91 100644
--- a/src/mainboard/google/fatcat/variants/baseboard/fatcat/devicetree.cb
+++ b/src/mainboard/google/fatcat/variants/baseboard/fatcat/devicetree.cb
@@ -98,7 +98,6 @@ chip soc/intel/pantherlake
 	register "pch_hda_idisp_link_tmode" = "HDA_TMODE_8T"
 	register "pch_hda_idisp_link_frequency" = "HDA_LINKFREQ_96MHZ"
 	register "pch_hda_idisp_codec_enable" = "true"
-	register "pch_hda_sdi_enable" = "{ true, false }"
 
 	device domain 0 on
 		device ref dtt on end
diff --git a/src/mainboard/google/fatcat/variants/fatcat/Makefile.mk b/src/mainboard/google/fatcat/variants/fatcat/Makefile.mk
index eb361dfe89..b9f1fd15dd 100644
--- a/src/mainboard/google/fatcat/variants/fatcat/Makefile.mk
+++ b/src/mainboard/google/fatcat/variants/fatcat/Makefile.mk
@@ -5,5 +5,5 @@ romstage-y += gpio.c
 romstage-y += memory.c
 romstage-$(CONFIG_FW_CONFIG) += fw_config.c
 ramstage-y += gpio.c
-ramstage-$(CONFIG_FW_CONFIG) += variant.c
+romstage-$(CONFIG_FW_CONFIG) += variant.c
 ramstage-$(CONFIG_FW_CONFIG) += fw_config.c
diff --git a/src/mainboard/google/fatcat/variants/fatcat/variant.c b/src/mainboard/google/fatcat/variants/fatcat/variant.c
index 85c92430f7..66c86cf161 100644
--- a/src/mainboard/google/fatcat/variants/fatcat/variant.c
+++ b/src/mainboard/google/fatcat/variants/fatcat/variant.c
@@ -1,6 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
 #include <baseboard/variants.h>
+#include <fsp/api.h>
 #include <fw_config.h>
 #include <sar.h>
 
@@ -25,3 +26,15 @@ void variant_update_soc_chip_config(struct soc_intel_pantherlake_config *config)
 		}
 	}
 }
+
+void variant_update_soc_memory_init_params(FSPM_UPD *memupd)
+{
+	FSP_M_CONFIG *m_cfg = &memupd->FspmConfig;
+
+	/* HDA Audio */
+	if (fw_config_probe(FW_CONFIG(AUDIO, AUDIO_ALC256_HDA))) {
+		printk(BIOS_INFO, "Overriding HDA SDI lanes.\n");
+		m_cfg->PchHdaSdiEnable[0] = true;
+		m_cfg->PchHdaSdiEnable[1] = false;
+	}
+}
diff --git a/src/mainboard/google/fatcat/variants/francka/Makefile.mk b/src/mainboard/google/fatcat/variants/francka/Makefile.mk
index f4b5d45f77..59936d98b2 100644
--- a/src/mainboard/google/fatcat/variants/francka/Makefile.mk
+++ b/src/mainboard/google/fatcat/variants/francka/Makefile.mk
@@ -5,6 +5,6 @@ bootblock-y += gpio.c
 romstage-y += gpio.c
 romstage-y += memory.c
 romstage-$(CONFIG_FW_CONFIG) += fw_config.c
-
+romstage-$(CONFIG_FW_CONFIG) += variant.c
 ramstage-y += gpio.c
 ramstage-$(CONFIG_FW_CONFIG) += fw_config.c
diff --git a/src/mainboard/google/fatcat/variants/francka/variant.c b/src/mainboard/google/fatcat/variants/francka/variant.c
new file mode 100644
index 0000000000..0943ee18be
--- /dev/null
+++ b/src/mainboard/google/fatcat/variants/francka/variant.c
@@ -0,0 +1,17 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <baseboard/variants.h>
+#include <fsp/api.h>
+#include <fw_config.h>
+
+void variant_update_soc_memory_init_params(FSPM_UPD *memupd)
+{
+	FSP_M_CONFIG *m_cfg = &memupd->FspmConfig;
+
+	/* HDA Audio */
+	if (fw_config_probe(FW_CONFIG(AUDIO, AUDIO_ALC256M_CG_HDA))) {
+		printk(BIOS_INFO, "Overriding HDA SDI lanes.\n");
+		m_cfg->PchHdaSdiEnable[0] = true;
+		m_cfg->PchHdaSdiEnable[1] = false;
+	}
+}

From 566f87a24972837419ec789164200445167d6e95 Mon Sep 17 00:00:00 2001
From: David Wu <david_wu@quanta.corp-partner.google.com>
Date: Thu, 27 Mar 2025 11:57:34 +0800
Subject: [PATCH 0591/3886] mb/google/nissa/var/dirks: Add romstage early
 graphics for dirks

Dirks is chromebox, enable early graphics support for HDMI.

BUG=b:399236160
TEST=On-screen text message seen during MRC training on dirks

Change-Id: I8ab2c3a2cc72059facbbc0bba59cc480a5081a9e
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87020
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Reviewed-by: Jayvik Desai <jayvik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
---
 .../baseboard/nissa/gma-mainboard.ads         |  2 ++
 .../google/brya/variants/dirks/gpio.c         | 30 +++++++++++++++++++
 2 files changed, 32 insertions(+)

diff --git a/src/mainboard/google/brya/variants/baseboard/nissa/gma-mainboard.ads b/src/mainboard/google/brya/variants/baseboard/nissa/gma-mainboard.ads
index 3b02f14d95..bb28ffdf1f 100644
--- a/src/mainboard/google/brya/variants/baseboard/nissa/gma-mainboard.ads
+++ b/src/mainboard/google/brya/variants/baseboard/nissa/gma-mainboard.ads
@@ -9,5 +9,7 @@ use HW.GFX.GMA.Display_Probing;
 private package GMA.Mainboard is
    ports : constant Port_List :=
      (eDP,
+      HDMI1,
+      HDMI2,
       others => Disabled);
 end GMA.Mainboard;
diff --git a/src/mainboard/google/brya/variants/dirks/gpio.c b/src/mainboard/google/brya/variants/dirks/gpio.c
index 209ca047dc..19e540a682 100644
--- a/src/mainboard/google/brya/variants/dirks/gpio.c
+++ b/src/mainboard/google/brya/variants/dirks/gpio.c
@@ -2,6 +2,7 @@
 
 #include <baseboard/gpio.h>
 #include <baseboard/variants.h>
+#include <intelblocks/early_graphics.h>
 #include <soc/gpio.h>
 
 /* Pad configuration in ramstage for dirks */
@@ -146,6 +147,35 @@ static const struct pad_config romstage_gpio_table[] = {
 	PAD_CFG_GPO(GPP_H20, 1, DEEP),
 };
 
+const struct pad_config early_graphics_gpio_table[] = {
+	/* A18 : NC ==> HDMI2_HPD*/
+	PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1),
+	/* A20 : DDSP_HPD2 ==> EC_SOC_HDMI_HPD */
+	PAD_CFG_NF(GPP_A20, NONE, DEEP, NF1),
+
+	/* E14 : DDSP_HPDA ==> HDMI1_HPD */
+	PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1),
+	/* E20 : DDP2_CTRLCLK ==> HDMI_DDC_SCL */
+	PAD_CFG_NF(GPP_E20, NONE, DEEP, NF1),
+	/* E21 : DDP2_CTRLDATA ==> HDMI_DDC_SDA_STRAP */
+	PAD_CFG_NF(GPP_E21, NONE, DEEP, NF1),
+	/* E22 : DDPA_CTRLCLK ==> DDPA_CTRLCLK */
+	PAD_CFG_NF(GPP_E22, NONE, DEEP, NF1),
+	/* E23 : DDPA_CTRLDATA ==> DDPA_CTRLDATA */
+	PAD_CFG_NF(GPP_E23, NONE, DEEP, NF1),
+
+	/* H15 : HDMI_SRC_DDC_SCL */
+	PAD_CFG_NF(GPP_H15, NONE, DEEP, NF1),
+	/* H17 : HDMI_SRC_DDC_SDA */
+	PAD_CFG_NF(GPP_H17, NONE, DEEP, NF1),
+};
+
+const struct pad_config *variant_early_graphics_gpio_table(size_t *num)
+{
+	*num = ARRAY_SIZE(early_graphics_gpio_table);
+	return early_graphics_gpio_table;
+}
+
 const struct pad_config *variant_gpio_override_table(size_t *num)
 {
 	*num = ARRAY_SIZE(override_gpio_table);

From 3a43968a82655d2e91dade3cd73b03a86d931893 Mon Sep 17 00:00:00 2001
From: Lucas Chen <lucas.chen@quanta.corp-partner.google.com>
Date: Tue, 25 Mar 2025 13:54:15 +0800
Subject: [PATCH 0592/3886] mb/google/brask/var/moxie: Remove wifi sar table
 for moxie

The parent project kuldax had support wifi sar switch.
But moxie does not support Wifi sar. Remove wifi sar table.

BUG=b:248367859
TEST=build pass

Change-Id: I012ff2d9c8c4d6d4480cae7166bf8e633bcaa752
Signed-off-by: Lucas Chen <lucas.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87004
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Jayvik Desai <jayvik@google.com>
---
 src/mainboard/google/brya/Kconfig                  | 1 -
 src/mainboard/google/brya/variants/moxie/variant.c | 6 ------
 2 files changed, 7 deletions(-)

diff --git a/src/mainboard/google/brya/Kconfig b/src/mainboard/google/brya/Kconfig
index f7f8bf9a22..378e7cd9bb 100644
--- a/src/mainboard/google/brya/Kconfig
+++ b/src/mainboard/google/brya/Kconfig
@@ -383,7 +383,6 @@ config BOARD_GOOGLE_MOLI
 
 config BOARD_GOOGLE_MOXIE
 	select BOARD_GOOGLE_BASEBOARD_BRASK
-	select CHROMEOS_WIFI_SAR if CHROMEOS
 	select DRIVERS_GENESYSLOGIC_GL9755
 	select EC_GOOGLE_CHROMEEC_INCLUDE_SSFC_IN_FW_CONFIG
 	select INTEL_GMA_HAVE_VBT
diff --git a/src/mainboard/google/brya/variants/moxie/variant.c b/src/mainboard/google/brya/variants/moxie/variant.c
index b7cba968a5..e1266c7ec8 100644
--- a/src/mainboard/google/brya/variants/moxie/variant.c
+++ b/src/mainboard/google/brya/variants/moxie/variant.c
@@ -3,12 +3,6 @@
 #include <baseboard/variants.h>
 #include <chip.h>
 #include <fw_config.h>
-#include <sar.h>
-
-const char *get_wifi_sar_cbfs_filename(void)
-{
-	return "wifi_sar_0.hex";
-}
 
 void variant_update_soc_chip_config(struct soc_intel_alderlake_config *config)
 {

From 91dbadf677aaeb34153a34992db35c3246b1c611 Mon Sep 17 00:00:00 2001
From: Pranava Y N <pranavayn@google.com>
Date: Wed, 2 Apr 2025 16:47:35 +0530
Subject: [PATCH 0593/3886] mb/google/nissa/var/rull: Enable early EC software
 sync for Rull

Enable `VBOOT_EARLY_EC_SYNC` for rull device. This enables EC software
sync in romstage. This is useful to achieve full USB-PD negotiation
early in the boot flow. It eliminates a problem seen in rull devices
where PMC is wrongly configured in depthcharge during the EC-sync
scenario which prevents USB devices from getting detected when
connected via a self-powered USB hub.

BUG=b:386920751
TEST=Verify detection and booting to OS from USB drive connected to the
Servo v4 debugger (self-powered hub) during the EC-sync scenario.

Change-Id: Ie36794a8a2c0bcd4ba77f3ad844a30f28f59403f
Signed-off-by: Pranava Y N <pranavayn@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87104
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Jayvik Desai <jayvik@google.com>
---
 src/mainboard/google/brya/Kconfig | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/mainboard/google/brya/Kconfig b/src/mainboard/google/brya/Kconfig
index 378e7cd9bb..9aaf789c2c 100644
--- a/src/mainboard/google/brya/Kconfig
+++ b/src/mainboard/google/brya/Kconfig
@@ -1100,7 +1100,7 @@ config VARIANT_DIR
 	default "meliks" if BOARD_GOOGLE_MELIKS
 
 config VBOOT
-	select VBOOT_EARLY_EC_SYNC if !(BOARD_GOOGLE_BASEBOARD_NISSA || BOARD_GOOGLE_BASEBOARD_TRULO)
+	select VBOOT_EARLY_EC_SYNC if !(BOARD_GOOGLE_BASEBOARD_NISSA || BOARD_GOOGLE_BASEBOARD_TRULO) || BOARD_GOOGLE_RULL
 	select VBOOT_LID_SWITCH
 
 config UART_FOR_CONSOLE

From f895289a368f63c31df58219f7f3312cbb98f467 Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Wed, 2 Apr 2025 13:29:45 +0100
Subject: [PATCH 0594/3886] mb/starlabs/starbook/*: Tidy GPIO comments for
 display outputs

This is a non-functional change, and only makes the GPIOs easier to read.

Change-Id: Ib86d4b0193fc78123ab3451e92865bff2bab5bd6
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87106
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 .../starlabs/byte_adl/variants/mk_ii/gpio.c   | 17 ++++++--------
 .../starlabs/starbook/variants/adl/gpio.c     | 17 ++++++--------
 .../starlabs/starbook/variants/cml/gpio.c     | 17 ++++++--------
 .../starlabs/starbook/variants/kbl/gpio.c     | 17 ++++++--------
 .../starlabs/starbook/variants/mtl/gpio.c     | 23 ++++++++-----------
 .../starlabs/starbook/variants/rpl/gpio.c     | 23 ++++++++-----------
 .../starlabs/starbook/variants/tgl/gpio.c     | 23 ++++++++-----------
 .../starlabs/starfighter/variants/rpl/gpio.c  | 23 ++++++++-----------
 .../starlite_adl/variants/mk_v/gpio.c         | 20 +++++++---------
 9 files changed, 72 insertions(+), 108 deletions(-)

diff --git a/src/mainboard/starlabs/byte_adl/variants/mk_ii/gpio.c b/src/mainboard/starlabs/byte_adl/variants/mk_ii/gpio.c
index 8653f4b015..f60a42d602 100644
--- a/src/mainboard/starlabs/byte_adl/variants/mk_ii/gpio.c
+++ b/src/mainboard/starlabs/byte_adl/variants/mk_ii/gpio.c
@@ -49,6 +49,13 @@ const struct pad_config gpio_table[] = {
 	PAD_CFG_GPO(GPP_E3, 1, DEEP),					/* WiFi RF Kill */
 	PAD_CFG_GPO(GPP_A13, 1, DEEP),					/* Bluetooth RF Kill */
 
+	/* Display */
+	PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1),				/* eDP Hot Plug */
+	PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1),				/* HDMI Hot Plug */
+	PAD_CFG_NF(GPP_H15, NONE, DEEP, NF1),				/* HDMI Clock */
+	PAD_CFG_NF(GPP_H17, NONE, DEEP, NF1),				/* HDMI Data */
+	PAD_CFG_NF(GPP_A19, NONE, DEEP, NF1),				/* TCP0 Hot Plug */
+
 	/* GPD2:	LAN Wake					*/
 	PAD_NC(GPD2, NONE),
 	/* GPD6:	Sleep A						*/
@@ -82,10 +89,6 @@ const struct pad_config gpio_table[] = {
 	PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1),
 	/* A17:		Not Connected					*/
 	PAD_NC(GPP_A17, NONE),
-	/* A18:		DDI B DP HPD					*/
-	PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1),
-	/* A19:		TCP0 HPD					*/
-	PAD_CFG_NF(GPP_A19, NONE, DEEP, NF1),
 	/* A20:		Test Point 2					*/
 	PAD_NC(GPP_A20, NONE),
 	/* A21:		Fingerprint Reader Interrupt			*/
@@ -271,8 +274,6 @@ const struct pad_config gpio_table[] = {
 	PAD_NC(GPP_E12, NONE),
 	/* E13:		Not connected					*/
 	PAD_NC(GPP_E13, NONE),
-	/* E14:		EDP HPD						*/
-	PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1),
 	/* E15:		Not Connected		LAN RESET		*/
 	PAD_NC(GPP_E15, NONE),
 	/* E16:		Not Connected					*/
@@ -355,12 +356,8 @@ const struct pad_config gpio_table[] = {
 	PAD_NC(GPP_H13, NONE),
 	/* H14:		Not Connected					*/
 	PAD_NC(GPP_H14, NONE),
-	/* H15:		DDPB Control Clock				*/
-	PAD_CFG_NF(GPP_H15, NONE, DEEP, NF1),
 	/* H16:		Not Connected					*/
 	PAD_NC(GPP_H16, NONE),
-	/* H17:		DDPB Control Data				*/
-	PAD_CFG_NF(GPP_H17, NONE, DEEP, NF1),
 	/* H18:		CPI C10 Gate					*/
 	PAD_CFG_NF(GPP_H18, NONE, DEEP, NF1),
 	/* H19:		Clock Request 4					*/
diff --git a/src/mainboard/starlabs/starbook/variants/adl/gpio.c b/src/mainboard/starlabs/starbook/variants/adl/gpio.c
index 60786b5230..f98a8990ee 100644
--- a/src/mainboard/starlabs/starbook/variants/adl/gpio.c
+++ b/src/mainboard/starlabs/starbook/variants/adl/gpio.c
@@ -50,6 +50,13 @@ const struct pad_config gpio_table[] = {
 	PAD_CFG_GPO(GPP_E3, 1, DEEP),					/* WiFi RF Kill */
 	PAD_CFG_GPO(GPP_A13, 1, DEEP),					/* Bluetooth RF Kill */
 
+	/* Display */
+	PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1),				/* eDP Hot Plug */
+	PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1),				/* HDMI Hot Plug */
+	PAD_CFG_NF(GPP_H15, NONE, DEEP, NF1),				/* HDMI Clock */
+	PAD_CFG_NF(GPP_H17, NONE, DEEP, NF1),				/* HDMI Data */
+	PAD_CFG_NF(GPP_A19, NONE, DEEP, NF1),				/* TCP0 Hot Plug */
+
 	/* GPD2:	LAN Wake					*/
 	PAD_NC(GPD2, NONE),
 	/* GPD6:	Sleep A						*/
@@ -83,10 +90,6 @@ const struct pad_config gpio_table[] = {
 	PAD_NC(GPP_A16, NONE),
 	/* A17:		Not Connected					*/
 	PAD_NC(GPP_A17, NONE),
-	/* A18:		DDI B DP HPD					*/
-	PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1),
-	/* A19:		TCP0 HPD					*/
-	PAD_CFG_NF(GPP_A19, NONE, DEEP, NF1),
 	/* A20:		Test Point 44					*/
 	PAD_NC(GPP_A20, NONE),
 	/* A21:		Fingerprint Reader Interrupt			*/
@@ -267,8 +270,6 @@ const struct pad_config gpio_table[] = {
 	PAD_CFG_GPI_APIC_LOW(GPP_E11, NONE, PLTRST),
 	/* E13:		Not connected					*/
 	PAD_NC(GPP_E13, NONE),
-	/* E14:		EDP HPD						*/
-	PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1),
 	/* E15:		Not Connected					*/
 	PAD_NC(GPP_E15, NONE),
 	/* E16:		Not Connected					*/
@@ -357,12 +358,8 @@ const struct pad_config gpio_table[] = {
 	PAD_CFG_NF(GPP_H13, NONE, DEEP, NF5),
 	/* H14:		Not Connected					*/
 	PAD_NC(GPP_H14, NONE),
-	/* H15:		DDPB Control Clock				*/
-	PAD_CFG_NF(GPP_H15, NONE, DEEP, NF1),
 	/* H16:		Not Connected					*/
 	PAD_NC(GPP_H16, NONE),
-	/* H17:		DDPB Control Data				*/
-	PAD_CFG_NF(GPP_H17, NONE, DEEP, NF1),
 	/* H18:		CPI C10 Gate					*/
 	PAD_CFG_NF(GPP_H18, NONE, DEEP, NF1),
 	/* H19:		Clock Request 4		CPU M.2 SSD		*/
diff --git a/src/mainboard/starlabs/starbook/variants/cml/gpio.c b/src/mainboard/starlabs/starbook/variants/cml/gpio.c
index 8f2ca8223d..4159f258a6 100644
--- a/src/mainboard/starlabs/starbook/variants/cml/gpio.c
+++ b/src/mainboard/starlabs/starbook/variants/cml/gpio.c
@@ -52,6 +52,13 @@ const struct pad_config gpio_table[] = {
 	PAD_CFG_GPO(GPP_C2, 1, DEEP),					/* WiFi RF Kill */
 	PAD_CFG_GPO(GPP_B4, 1, DEEP),					/* Bluetooth RF Kill */
 
+	/* Display */
+	PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1),				/* eDP Hot Plug */
+	PAD_CFG_NF(GPP_E13, NONE, DEEP, NF1),				/* HDMI Hot Plug */
+	PAD_CFG_NF(GPP_E18, NONE, DEEP, NF1),				/* HDMI Clock */
+	PAD_CFG_NF(GPP_E19, NONE, DEEP, NF1),				/* HDMI Data */
+	PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1),				/* TCP0 Hot Plug */
+
 	/* GPD2:	LAN_WAKE#		*/
 	PAD_NC(GPD2, NONE),
 	/* GPD6:	SIO_SLP_A#		*/
@@ -271,20 +278,10 @@ const struct pad_config gpio_table[] = {
 	PAD_CFG_NF(GPP_E11, NONE, DEEP, NF1),
 	/* E12:	 GPPC_E12_USB2_OCB_3		*/
 	PAD_CFG_NF(GPP_E12, NONE, DEEP, NF1),
-	/* E13:	 DDI1_HPD			*/
-	PAD_CFG_NF(GPP_E13, NONE, DEEP, NF1),
-	/* E14:	 DDI2_HPD			*/
-	PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1),
 	/* E15:	 SMC_SMI_N			*/
 	PAD_CFG_GPI_SMI_LOW(GPP_E15, NONE, DEEP, EDGE_SINGLE),
 	/* E16:	 SMC_SCI_N			*/
 	PAD_CFG_GPI_SCI_LOW(GPP_E16, NONE, PLTRST, LEVEL),
-	/* E17:	 EDP_HPD			*/
-	PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1),
-	/* E18:	 DDI1_DDC_SCL			*/
-	PAD_CFG_NF(GPP_E18, NONE, DEEP, NF1),
-	/* E19:	 DDI1_DDC_SDA			*/
-	PAD_CFG_NF(GPP_E19, NONE, DEEP, NF1),
 	/* E20:	 DDI2_CTRL_CLK			*/
 	PAD_CFG_NF(GPP_E20, NONE, DEEP, NF1),
 	/* E21:	 DDI2_CTRL_DATA			*/
diff --git a/src/mainboard/starlabs/starbook/variants/kbl/gpio.c b/src/mainboard/starlabs/starbook/variants/kbl/gpio.c
index 47864e84be..b96476d1b0 100644
--- a/src/mainboard/starlabs/starbook/variants/kbl/gpio.c
+++ b/src/mainboard/starlabs/starbook/variants/kbl/gpio.c
@@ -37,6 +37,13 @@ const struct pad_config gpio_table[] = {
 	// PAD_CFG_GPO(GPP_D20, 1, DEEP),				/* WiFi RF Kill */
 	PAD_CFG_TERM_GPO(GPP_B4, 1, UP_20K, DEEP),			/* Bluetooth RF Kill */
 
+	/* Display */
+	PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1),				/* eDP Hot Plug */
+	PAD_CFG_NF(GPP_E13, NONE, DEEP, NF1),				/* HDMI Hot Plug */
+	PAD_CFG_NF(GPP_E18, NONE, DEEP, NF1),				/* HDMI Clock */
+	PAD_CFG_NF(GPP_E19, DN_20K, DEEP, NF1),				/* HDMI Data */
+	PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1),				/* TCP0 Hot Plug */
+
 	/* GPD2:	Not Connected		*/
 	PAD_NC(GPD2, NONE),
 	/* GPD6:	Not Connected		*/
@@ -251,20 +258,10 @@ const struct pad_config gpio_table[] = {
 	PAD_CFG_NF(GPP_E11, NONE, DEEP, NF1),
 	/* GPP_E12:	Not Connected		*/
 	PAD_NC(GPP_E12, DN_20K),
-	/* GPP_E13:	DDI1_HPD		*/
-	PAD_CFG_NF(GPP_E13, NONE, DEEP, NF1),
-	/* GPP_E14:	DDI2_HPD		*/
-	PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1),
 	/* E15:  SMC_SMI_N                      */
 	PAD_CFG_GPI_SMI_LOW(GPP_E15, NONE, DEEP, EDGE_SINGLE),
 	/* E16:  SMC_SCI_N                      */
 	PAD_CFG_GPI_SCI_LOW(GPP_E16, NONE, PLTRST, LEVEL),
-	/* GPP_E17:	EDP_HPD			*/
-	PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1),
-	/* GPP_E18:	DDI1_DDC_SCL		*/
-	PAD_CFG_NF(GPP_E18, NONE, DEEP, NF1),
-	/* GPP_E19:	DDI1_DDC_SDA		*/
-	PAD_CFG_NF(GPP_E19, DN_20K, DEEP, NF1),
 	/* GPP_E20:	Not Connected		*/
 	PAD_NC(GPP_E20, DN_20K),
 	/* GPP_E21:	DDI2_DDC_SDA		*/
diff --git a/src/mainboard/starlabs/starbook/variants/mtl/gpio.c b/src/mainboard/starlabs/starbook/variants/mtl/gpio.c
index 89670dd4eb..2eb823095f 100644
--- a/src/mainboard/starlabs/starbook/variants/mtl/gpio.c
+++ b/src/mainboard/starlabs/starbook/variants/mtl/gpio.c
@@ -55,6 +55,15 @@ const struct pad_config gpio_table[] = {
 	PAD_CFG_GPO(GPP_B19, 1, DEEP),					/* WiFi RF Kill */
 	PAD_CFG_GPO(GPP_B18, 1, DEEP),					/* Bluetooth RF Kill */
 
+	/* Display */
+	PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1),				/* eDP Hot Plug */
+	PAD_CFG_NF(GPP_B16, NONE, DEEP, NF2),				/* HDMI Hot Plug */
+	PAD_CFG_NF(GPP_H16, NONE, DEEP, NF1),				/* HDMI Clock */
+	PAD_CFG_NF(GPP_H17, NONE, DEEP, NF1),				/* HDMI Data */
+	PAD_CFG_NF(GPP_A21, NONE, DEEP, NF1),				/* PMC Interrupt */
+	PAD_CFG_NF(GPP_C06, NONE, DEEP, NF1),				/* SML Clock */
+	PAD_CFG_NF(GPP_C07, NONE, DEEP, NF1),				/* SML Data */
+
 	/* V02:	PCIE_WAKE_LAN			*/
 	PAD_NC(GPP_V02, NONE),
 	/* V06:	GPD_6_SLP_A_N			*/
@@ -111,10 +120,6 @@ const struct pad_config gpio_table[] = {
 	 *		LOW:	ENABLED
 	 *		WEAK INTERNAL PD 20K	*/
 	PAD_CFG_GPO(GPP_C05, 0, PLTRST),
-	/* C06:	SML1_CLK_USBC_PD_N		*/
-	PAD_CFG_NF(GPP_C06, NONE, DEEP, NF1),
-	/* C07:	SML1_DATA_USBC_PD_N		*/
-	PAD_CFG_NF(GPP_C07, NONE, DEEP, NF1),
 	/* C08:	SML1ALERT			*/
 	PAD_CFG_NF(GPP_C08, NONE, DEEP, NF1),
 	/* C09:					*/
@@ -182,8 +187,6 @@ const struct pad_config gpio_table[] = {
 	PAD_NC(GPP_A19, NONE),
 	/* A20:	M.2_CPU_SSD_RESET_N		*/
 	PAD_CFG_GPO(GPP_A20, 1, PLTRST),
-	/* A21:	I2C_PMC_PD_INT_N		*/
-	PAD_CFG_NF(GPP_A21, NONE, DEEP, NF1),
 	/* A22:					*/
 	PAD_NC(GPP_A22, NONE),
 	/* A23:					*/
@@ -225,8 +228,6 @@ const struct pad_config gpio_table[] = {
 	PAD_NC(GPP_E12, NONE),
 	/* E13:					*/
 	PAD_NC(GPP_E13, NONE),
-	/* E14:	EDP_HPD_N			*/
-	PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1),
 	/* E15:	BOOTHALT_N			*/
 	PAD_CFG_NF(GPP_E15, NONE, DEEP, NF2),
 	/* E16:	BC_PROCHOT_N			*/
@@ -276,10 +277,6 @@ const struct pad_config gpio_table[] = {
 	PAD_NC(GPP_H14, NONE),
 	/* H15:					*/
 	PAD_NC(GPP_H15, NONE),
-	/* H16:	DDPB_CTRLCLK			*/
-	PAD_CFG_NF(GPP_H16, NONE, DEEP, NF1),
-	/* H17:	DDPB_CTRLDATA			*/
-	PAD_CFG_NF(GPP_H17, NONE, DEEP, NF1),
 	/* H18:					*/
 	PAD_NC(GPP_H18, NONE),
 	/* H21:					*/
@@ -416,8 +413,6 @@ const struct pad_config gpio_table[] = {
 	PAD_CFG_GPO(GPP_B14, 0, PLTRST),
 	/* B15:					*/
 	PAD_NC(GPP_B15, NONE),
-	/* B16:	DDIB_DP_HPD			*/
-	PAD_CFG_NF(GPP_B16, NONE, DEEP, NF2),
 	/* B17:					*/
 	PAD_NC(GPP_B17, NONE),
 	/* B20:					*/
diff --git a/src/mainboard/starlabs/starbook/variants/rpl/gpio.c b/src/mainboard/starlabs/starbook/variants/rpl/gpio.c
index 6e90173e51..1dd2897c71 100644
--- a/src/mainboard/starlabs/starbook/variants/rpl/gpio.c
+++ b/src/mainboard/starlabs/starbook/variants/rpl/gpio.c
@@ -50,6 +50,15 @@ const struct pad_config gpio_table[] = {
 	PAD_CFG_GPO(GPP_E3, 1, DEEP),					/* WiFi RF Kill */
 	PAD_CFG_GPO(GPP_A13, 1, DEEP),					/* Bluetooth RF Kill */
 
+	/* Display */
+	PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1),				/* eDP Hot Plug */
+	PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1),				/* HDMI Hot Plug */
+	PAD_CFG_NF(GPP_H15, NONE, DEEP, NF1),				/* HDMI Clock */
+	PAD_CFG_NF(GPP_H17, NONE, DEEP, NF1),				/* HDMI Data */
+	PAD_CFG_NF(GPP_B11, NONE, DEEP, NF1),				/* PMC Interrupt */
+	PAD_CFG_NF(GPP_C6, NONE, DEEP, NF1),				/* SML Clock */
+	PAD_CFG_NF(GPP_C7, NONE, DEEP, NF1),				/* SML Data */
+
 	/* GPD2:	LAN Wake					*/
 	PAD_NC(GPD2, NONE),
 	/* GPD6:	Sleep A						*/
@@ -84,8 +93,6 @@ const struct pad_config gpio_table[] = {
 	PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1),
 	/* A17:		Not Connected					*/
 	PAD_NC(GPP_A17, NONE),
-	/* A18:		DDI B DP HPD					*/
-	PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1),
 	/* A19:		Not Connected					*/
 	PAD_NC(GPP_A19, NONE),
 	/* A20:		Test Point 44					*/
@@ -119,8 +126,6 @@ const struct pad_config gpio_table[] = {
 	PAD_NC(GPP_B9, NONE),
 	/* B10:		Not Connected					*/
 	PAD_NC(GPP_B10, NONE),
-	/* B11:		I2C PMC PD Interrupt				*/
-	PAD_CFG_NF(GPP_B11, NONE, DEEP, NF1),
 	/* B12:		PM SLP S0					*/
 	PAD_NC(GPP_B12, NONE),
 	/* B13:		PLT RST						*/
@@ -170,10 +175,6 @@ const struct pad_config gpio_table[] = {
 				Low:	ESPI
 				High:	Disabled			*/
 	PAD_CFG_GPO(GPP_C5, 0, DEEP),
-	/* C6:		SML 1 Clock					*/
-	PAD_CFG_NF(GPP_C6, NONE, DEEP, NF1),
-	/* C7:		SML 1 Data					*/
-	PAD_CFG_NF(GPP_C7, NONE, DEEP, NF1),
 	/* C8:		Not Connected					*/
 	PAD_NC(GPP_C8, NONE),
 	/* C9:		Not Connected					*/
@@ -270,8 +271,6 @@ const struct pad_config gpio_table[] = {
 	PAD_CFG_GPI_APIC_LOW(GPP_E11, NONE, PLTRST),
 	/* E13:		Not connected					*/
 	PAD_NC(GPP_E13, NONE),
-	/* E14:		EDP HPD						*/
-	PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1),
 	/* E15:		Not Connected					*/
 	PAD_NC(GPP_E15, NONE),
 	/* E16:		Not Connected					*/
@@ -360,12 +359,8 @@ const struct pad_config gpio_table[] = {
 	PAD_NC(GPP_H13, NONE),
 	/* H14:		Not Connected					*/
 	PAD_NC(GPP_H14, NONE),
-	/* H15:		DDPB Control Clock				*/
-	PAD_CFG_NF(GPP_H15, NONE, DEEP, NF1),
 	/* H16:		Not Connected					*/
 	PAD_NC(GPP_H16, NONE),
-	/* H17:		DDPB Control Data				*/
-	PAD_CFG_NF(GPP_H17, NONE, DEEP, NF1),
 	/* H18:		CPI C10 Gate					*/
 	PAD_CFG_NF(GPP_H18, NONE, DEEP, NF1),
 	/* H20:		Not Connected					*/
diff --git a/src/mainboard/starlabs/starbook/variants/tgl/gpio.c b/src/mainboard/starlabs/starbook/variants/tgl/gpio.c
index 89985412c1..11b52ceb9a 100644
--- a/src/mainboard/starlabs/starbook/variants/tgl/gpio.c
+++ b/src/mainboard/starlabs/starbook/variants/tgl/gpio.c
@@ -42,6 +42,15 @@ const struct pad_config gpio_table[] = {
 	PAD_CFG_NF(GPP_F3, NONE, DEEP, NF1),				/* RGI Response */
 	PAD_NC(GPP_F6, NONE),						/* Modem Clock Request */
 
+	/* Display */
+	PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1),				/* eDP Hot Plug */
+	PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1),				/* HDMI Hot Plug */
+	PAD_CFG_NF(GPP_H16, NONE, DEEP, NF1),				/* HDMI Clock */
+	PAD_CFG_NF(GPP_H17, NONE, DEEP, NF1),				/* HDMI Data */
+	PAD_CFG_NF(GPP_B11, NONE, DEEP, NF1),				/* PMC Interrupt */
+	PAD_CFG_NF(GPP_C6, NONE, PWROK, NF1),				/* SML Clock */
+	PAD_CFG_NF(GPP_C7, NONE, PWROK, NF1),				/* SML Data */
+
 	/* GPD2:	LAN_WAKE#		*/
 	PAD_NC(GPD2, NONE),
 	/* GPD6:	SIO_SLP_A#		*/
@@ -76,8 +85,6 @@ const struct pad_config gpio_table[] = {
 	PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1),
 	/* A17:	Not Connected			*/
 	PAD_NC(GPP_A17, NONE),
-	/* A18:	DDIB_HPD			*/
-	PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1),
 	/* A19	Not Connected			*/
 	PAD_NC(GPP_A19, NONE),
 	/* A20:	Not Connected			*/
@@ -111,8 +118,6 @@ const struct pad_config gpio_table[] = {
 	PAD_CFG_NF(GPP_B9, NONE, DEEP, NF1),
 	/* B10:	PWR_MON_I2C_SCL_R		*/
 	PAD_CFG_NF(GPP_B10, NONE, DEEP, NF1),
-	/* B11:	I2C_PMC_PD_INT_N		*/
-	PAD_CFG_NF(GPP_B11, NONE, DEEP, NF1),
 	/* B12:	PM_SLP_S0_N			*/
 	PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1),
 	/* B13:	PLT_RST_N			*/
@@ -150,10 +155,6 @@ const struct pad_config gpio_table[] = {
 	PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1),
 	/* C5:	SML0ALERT_IN			*/
 	PAD_CFG_GPO(GPP_C5, 0, DEEP),
-	/* C6:	SML1_CLK			*/
-	PAD_CFG_NF(GPP_C6, NONE, PWROK, NF1),
-	/* C7:	SML1_DATA			*/
-	PAD_CFG_NF(GPP_C7, NONE, PWROK, NF1),
 	/* C9:	Not Connected			*/
 	PAD_NC(GPP_C9, NONE),
 	/* C10:	Not Connected			*/
@@ -242,8 +243,6 @@ const struct pad_config gpio_table[] = {
 	PAD_NC(GPP_E12, NONE),
 	/* E13:	Not Connected			*/
 	PAD_NC(GPP_E13, NONE),
-	/* E14:	EDP_HPD				*/
-	PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1),
 	/* E15:	Not Connected			*/
 	PAD_NC(GPP_E15, NONE),
 	/* E16:	Not Connected			*/
@@ -334,10 +333,6 @@ const struct pad_config gpio_table[] = {
 	PAD_NC(GPP_H14, NONE),
 	/* H15:	Not Connected			*/
 	PAD_NC(GPP_H15, NONE),
-	/* H16:	DDIB_DDC_SCL			*/
-	PAD_CFG_NF(GPP_H16, NONE, DEEP, NF1),
-	/* H17:	DDIB_DDC_SDA			*/
-	PAD_CFG_NF(GPP_H17, NONE, DEEP, NF1),
 	/* H18:	CPU_C10_GATE_N			*/
 	PAD_CFG_NF(GPP_H18, NONE, DEEP, NF1),
 	/* H19:	UART_BT_WAKE_N			*/
diff --git a/src/mainboard/starlabs/starfighter/variants/rpl/gpio.c b/src/mainboard/starlabs/starfighter/variants/rpl/gpio.c
index 0bf4412862..6b47970c32 100644
--- a/src/mainboard/starlabs/starfighter/variants/rpl/gpio.c
+++ b/src/mainboard/starlabs/starfighter/variants/rpl/gpio.c
@@ -60,6 +60,15 @@ const struct pad_config gpio_table[] = {
 	PAD_CFG_GPO(GPP_E3, 1, DEEP),					/* WiFi RF Kill */
 	PAD_CFG_GPO(GPP_A13, 1, DEEP),					/* Bluetooth RF Kill */
 
+	/* Display */
+	PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1),				/* eDP Hot Plug */
+	PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1),				/* HDMI Hot Plug */
+	PAD_CFG_NF(GPP_H15, NONE, DEEP, NF1),				/* HDMI Clock */
+	PAD_CFG_NF(GPP_H17, NONE, DEEP, NF1),				/* HDMI Data */
+	PAD_CFG_NF(GPP_B11, NONE, DEEP, NF1),				/* PMC Interrupt */
+	PAD_CFG_NF(GPP_C6, NONE, DEEP, NF1),				/* SML Clock */
+	PAD_CFG_NF(GPP_C7, NONE, DEEP, NF1),				/* SML Data */
+
 	/* GPD2:	LAN Wake					*/
 	PAD_NC(GPD2, NONE),
 	/* GPD6:	Sleep A						*/
@@ -93,8 +102,6 @@ const struct pad_config gpio_table[] = {
 	PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1),
 	/* A17:		Not Connected					*/
 	PAD_NC(GPP_A17, NONE),
-	/* A18:		DDI B DP HPD					*/
-	PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1),
 	/* A19:		Not Connected					*/
 	PAD_NC(GPP_A19, NONE),
 	/* A20:		Test Point 44					*/
@@ -128,8 +135,6 @@ const struct pad_config gpio_table[] = {
 	PAD_NC(GPP_B9, NONE),
 	/* B10:		Not Connected					*/
 	PAD_NC(GPP_B10, NONE),
-	/* B11:		I2C PMC PD Interrupt				*/
-	PAD_CFG_NF(GPP_B11, NONE, DEEP, NF1),
 	/* B12:		PM SLP S0					*/
 	PAD_NC(GPP_B12, NONE),
 	/* B13:		PLT RST						*/
@@ -175,10 +180,6 @@ const struct pad_config gpio_table[] = {
 				Low:	ESPI
 				High:	Disabled			*/
 	PAD_CFG_GPO(GPP_C5, 0, DEEP),
-	/* C6:		SML 1 Clock					*/
-	PAD_CFG_NF(GPP_C6, NONE, DEEP, NF1),
-	/* C7:		SML 1 Data					*/
-	PAD_CFG_NF(GPP_C7, NONE, DEEP, NF1),
 	/* C8:		Not Connected					*/
 	PAD_NC(GPP_C8, NONE),
 	/* C9:		Not Connected					*/
@@ -273,8 +274,6 @@ const struct pad_config gpio_table[] = {
 	PAD_NC(GPP_E12, NONE),
 	/* E13:		Not connected					*/
 	PAD_NC(GPP_E13, NONE),
-	/* E14:		EDP HPD						*/
-	PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1),
 	/* E15:		Not Connected					*/
 	PAD_NC(GPP_E15, NONE),
 	/* E16:		Not Connected					*/
@@ -355,12 +354,8 @@ const struct pad_config gpio_table[] = {
 	PAD_NC(GPP_H13, NONE),
 	/* H14:		Not Connected					*/
 	PAD_NC(GPP_H14, NONE),
-	/* H15:		DDPB Control Clock				*/
-	PAD_CFG_NF(GPP_H15, NONE, DEEP, NF1),
 	/* H16:		Not Connected					*/
 	PAD_NC(GPP_H16, NONE),
-	/* H17:		DDPB Control Data				*/
-	PAD_CFG_NF(GPP_H17, NONE, DEEP, NF1),
 	/* H18:		CPI C10 Gate					*/
 	PAD_CFG_NF(GPP_H18, NONE, DEEP, NF1),
 	/* H19:		Clock Request 4		CPU M.2 SSD		*/
diff --git a/src/mainboard/starlabs/starlite_adl/variants/mk_v/gpio.c b/src/mainboard/starlabs/starlite_adl/variants/mk_v/gpio.c
index 63bda1d78a..0e65185c46 100644
--- a/src/mainboard/starlabs/starlite_adl/variants/mk_v/gpio.c
+++ b/src/mainboard/starlabs/starlite_adl/variants/mk_v/gpio.c
@@ -49,6 +49,14 @@ const struct pad_config gpio_table[] = {
 	PAD_CFG_GPO(GPP_E3, 1, DEEP),					/* WiFi RF Kill */
 	PAD_CFG_GPO(GPP_A13, 1, DEEP),					/* Bluetooth RF Kill */
 
+	/* Display */
+	PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1),				/* eDP Hot Plug */
+	PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1),				/* HDMI Hot Plug */
+	PAD_CFG_NF(GPP_H15, NONE, DEEP, NF1),				/* HDMI Clock */
+	PAD_CFG_NF(GPP_H17, NONE, DEEP, NF1),				/* HDMI Data */
+	PAD_CFG_NF(GPP_A19, NONE, DEEP, NF1),				/* TCP0 Hot Plug */
+	PAD_CFG_NF(GPP_A20, NONE, DEEP, NF1),				/* TCP0 Hot Plug */
+
 	/* GPD2:	LAN Wake					*/
 	PAD_NC(GPD2, NONE),
 	/* GPD6:	Sleep A						*/
@@ -82,12 +90,6 @@ const struct pad_config gpio_table[] = {
 	PAD_NC(GPP_A16, NONE),
 	/* A17:		Not Connected					*/
 	PAD_NC(GPP_A17, NONE),
-	/* A18:		DDI B DP HPD					*/
-	PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1),
-	/* A19:		TCP0 HPD					*/
-	PAD_CFG_NF(GPP_A19, NONE, DEEP, NF1),
-	/* A20:		TCP1 HPD					*/
-	PAD_CFG_NF(GPP_A20, NONE, DEEP, NF1),
 	/* A21:		Fingerprint Reader Interrupt			*/
 	PAD_NC(GPP_A21, NONE),
 	/* A22:		Fingerprint Reader Reset			*/
@@ -269,8 +271,6 @@ const struct pad_config gpio_table[] = {
 	PAD_NC(GPP_E12, NONE),
 	/* E13:		Not connected					*/
 	PAD_NC(GPP_E13, NONE),
-	/* E14:		EDP HPD						*/
-	PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1),
 	/* E15:		Webcam Power Enable				*/
 	PAD_NC(GPP_E15, NONE),
 	/* E16:		Not Connected					*/
@@ -353,12 +353,8 @@ const struct pad_config gpio_table[] = {
 	PAD_NC(GPP_H13, NONE),
 	/* H14:		Not Connected					*/
 	PAD_NC(GPP_H14, NONE),
-	/* H15:		DDPB Control Clock				*/
-	PAD_CFG_NF(GPP_H15, NONE, DEEP, NF1),
 	/* H16:		Not Connected					*/
 	PAD_NC(GPP_H16, NONE),
-	/* H17:		DDPB Control Data				*/
-	PAD_CFG_NF(GPP_H17, NONE, DEEP, NF1),
 	/* H18:		CPI C10 Gate					*/
 	PAD_CFG_NF(GPP_H18, NONE, DEEP, NF1),
 	/* H19:		Clock Request 4					*/

From 6dd323e1598f3d575e475396e023cb371528a8ff Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Wed, 2 Apr 2025 13:50:31 +0100
Subject: [PATCH 0595/3886] mb/starlabs/starbook/*: Tidy GPIO comments for HDA

This is a non-functional change, and only makes the GPIOs easier to read.

Change-Id: I5ba2e400ec57a0c52523ea360bee17d9517454b5
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87110
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 .../starlabs/byte_adl/variants/mk_ii/gpio.c     | 17 +++++++----------
 .../starlabs/starbook/variants/adl/gpio.c       | 17 +++++++----------
 .../starlabs/starbook/variants/mtl/gpio.c       | 17 +++++++----------
 .../starlabs/starbook/variants/rpl/gpio.c       | 17 +++++++----------
 .../starlabs/starbook/variants/tgl/gpio.c       | 17 +++++++----------
 .../starlabs/starfighter/variants/rpl/gpio.c    | 17 +++++++----------
 .../starlabs/starlite_adl/variants/mk_v/gpio.c  | 17 +++++++----------
 7 files changed, 49 insertions(+), 70 deletions(-)

diff --git a/src/mainboard/starlabs/byte_adl/variants/mk_ii/gpio.c b/src/mainboard/starlabs/byte_adl/variants/mk_ii/gpio.c
index f60a42d602..ba3b233eaa 100644
--- a/src/mainboard/starlabs/byte_adl/variants/mk_ii/gpio.c
+++ b/src/mainboard/starlabs/byte_adl/variants/mk_ii/gpio.c
@@ -56,6 +56,13 @@ const struct pad_config gpio_table[] = {
 	PAD_CFG_NF(GPP_H17, NONE, DEEP, NF1),				/* HDMI Data */
 	PAD_CFG_NF(GPP_A19, NONE, DEEP, NF1),				/* TCP0 Hot Plug */
 
+	/* High-Definition Audio */
+	PAD_CFG_NF(GPP_R0, NATIVE, DEEP, NF1),				/* Clock */
+	PAD_CFG_NF(GPP_R1, NATIVE, DEEP, NF1),				/* Sync */
+	PAD_CFG_NF(GPP_R2, NATIVE, DEEP, NF1),				/* Data Output */
+	PAD_CFG_NF(GPP_R3, NATIVE, DEEP, NF1),				/* Data Input */
+	PAD_CFG_NF(GPP_R4, NATIVE, DEEP, NF1),				/* Reset */
+
 	/* GPD2:	LAN Wake					*/
 	PAD_NC(GPD2, NONE),
 	/* GPD6:	Sleep A						*/
@@ -421,16 +428,6 @@ const struct pad_config gpio_table[] = {
 	/* T15:		 Not Connected					*/
 	PAD_NC(GPP_T15, NONE),
 
-	/* R0:		HDA BCLK					*/
-	PAD_CFG_NF(GPP_R0, NATIVE, DEEP, NF1),
-	/* R1:		HDA SYNC					*/
-	PAD_CFG_NF(GPP_R1, NATIVE, DEEP, NF1),
-	/* R2:		HDA SDO						*/
-	PAD_CFG_NF(GPP_R2, NATIVE, DEEP, NF1),
-	/* R3:		HDA SDI						*/
-	PAD_CFG_NF(GPP_R3, NATIVE, DEEP, NF1),
-	/* R4:		HDA Reset					*/
-	PAD_CFG_NF(GPP_R4, NATIVE, DEEP, NF1),
 	/* R5:		Not Connected					*/
 	PAD_NC(GPP_R5, NONE),
 	/* R6:		Not Connected					*/
diff --git a/src/mainboard/starlabs/starbook/variants/adl/gpio.c b/src/mainboard/starlabs/starbook/variants/adl/gpio.c
index f98a8990ee..58fd8d8dc6 100644
--- a/src/mainboard/starlabs/starbook/variants/adl/gpio.c
+++ b/src/mainboard/starlabs/starbook/variants/adl/gpio.c
@@ -57,6 +57,13 @@ const struct pad_config gpio_table[] = {
 	PAD_CFG_NF(GPP_H17, NONE, DEEP, NF1),				/* HDMI Data */
 	PAD_CFG_NF(GPP_A19, NONE, DEEP, NF1),				/* TCP0 Hot Plug */
 
+	/* High-Definition Audio */
+	PAD_CFG_NF(GPP_R0, NATIVE, DEEP, NF1),				/* Clock */
+	PAD_CFG_NF(GPP_R1, NATIVE, DEEP, NF1),				/* Sync */
+	PAD_CFG_NF(GPP_R2, NATIVE, DEEP, NF1),				/* Data Output */
+	PAD_CFG_NF(GPP_R3, NATIVE, DEEP, NF1),				/* Data Input */
+	PAD_CFG_NF(GPP_R4, NATIVE, DEEP, NF1),				/* Reset */
+
 	/* GPD2:	LAN Wake					*/
 	PAD_NC(GPD2, NONE),
 	/* GPD6:	Sleep A						*/
@@ -423,16 +430,6 @@ const struct pad_config gpio_table[] = {
 	/* T15:		 Not Connected					*/
 	PAD_NC(GPP_T15, NONE),
 
-	/* R0:		HDA BCLK				*/
-	PAD_CFG_NF(GPP_R0, NATIVE, DEEP, NF1),
-	/* R1:		HDA SYNC				*/
-	PAD_CFG_NF(GPP_R1, NATIVE, DEEP, NF1),
-	/* R2:		HDA SDO					*/
-	PAD_CFG_NF(GPP_R2, NATIVE, DEEP, NF1),
-	/* R3:		HDA SDI					*/
-	PAD_CFG_NF(GPP_R3, NATIVE, DEEP, NF1),
-	/* R4:		HDA Reset				*/
-	PAD_CFG_NF(GPP_R4, NATIVE, DEEP, NF1),
 	/* R5:		MiPi Cam Reset				*/
 	PAD_NC(GPP_R5, NONE),
 	/* R6:		Not Connected				*/
diff --git a/src/mainboard/starlabs/starbook/variants/mtl/gpio.c b/src/mainboard/starlabs/starbook/variants/mtl/gpio.c
index 2eb823095f..5d95d61a89 100644
--- a/src/mainboard/starlabs/starbook/variants/mtl/gpio.c
+++ b/src/mainboard/starlabs/starbook/variants/mtl/gpio.c
@@ -64,6 +64,13 @@ const struct pad_config gpio_table[] = {
 	PAD_CFG_NF(GPP_C06, NONE, DEEP, NF1),				/* SML Clock */
 	PAD_CFG_NF(GPP_C07, NONE, DEEP, NF1),				/* SML Data */
 
+	/* High-Definition Audio */
+	PAD_CFG_NF(GPP_D10, NATIVE, DEEP, NF1),				/* Clock */
+	PAD_CFG_NF(GPP_D11, NATIVE, DEEP, NF1),				/* Sync */
+	PAD_CFG_NF(GPP_D12, NATIVE, DEEP, NF1),				/* Data Output */
+	PAD_CFG_NF(GPP_D13, NATIVE, DEEP, NF1),				/* Data Input */
+	PAD_CFG_NF(GPP_D17, NATIVE, DEEP, NF1),				/* Reset */
+
 	/* V02:	PCIE_WAKE_LAN			*/
 	PAD_NC(GPP_V02, NONE),
 	/* V06:	GPD_6_SLP_A_N			*/
@@ -449,22 +456,12 @@ const struct pad_config gpio_table[] = {
 	PAD_NC(GPP_D08, NONE),
 	/* D09:					*/
 	PAD_NC(GPP_D09, NONE),
-	/* D10:	HDA_CODEC_BCLK			*/
-	PAD_CFG_NF(GPP_D10, NATIVE, DEEP, NF1),
-	/* D11:	HDA_CODEC_SYNC			*/
-	PAD_CFG_NF(GPP_D11, NATIVE, DEEP, NF1),
-	/* D12:	HDA_CODEC_SDO			*/
-	PAD_CFG_NF(GPP_D12, NATIVE, DEEP, NF1),
-	/* D13:	HDA_CODEC_SDI			*/
-	PAD_CFG_NF(GPP_D13, NATIVE, DEEP, NF1),
 	/* D14:					*/
 	PAD_NC(GPP_D14, NONE),
 	/* D15:					*/
 	PAD_NC(GPP_D15, NONE),
 	/* D16:					*/
 	PAD_NC(GPP_D16, NONE),
-	/* D17:	HDA_CODEC_RESET0_N		*/
-	PAD_CFG_NF(GPP_D17, NATIVE, DEEP, NF1),
 	/* D18:					*/
 	PAD_NC(GPP_D18, NONE),
 	/* D19:					*/
diff --git a/src/mainboard/starlabs/starbook/variants/rpl/gpio.c b/src/mainboard/starlabs/starbook/variants/rpl/gpio.c
index 1dd2897c71..0fed120f9a 100644
--- a/src/mainboard/starlabs/starbook/variants/rpl/gpio.c
+++ b/src/mainboard/starlabs/starbook/variants/rpl/gpio.c
@@ -59,6 +59,13 @@ const struct pad_config gpio_table[] = {
 	PAD_CFG_NF(GPP_C6, NONE, DEEP, NF1),				/* SML Clock */
 	PAD_CFG_NF(GPP_C7, NONE, DEEP, NF1),				/* SML Data */
 
+	/* High-Definition Audio */
+	PAD_CFG_NF(GPP_R0, NATIVE, DEEP, NF1),				/* Clock */
+	PAD_CFG_NF(GPP_R1, NATIVE, DEEP, NF1),				/* Sync */
+	PAD_CFG_NF(GPP_R2, NATIVE, DEEP, NF1),				/* Data Output */
+	PAD_CFG_NF(GPP_R3, NATIVE, DEEP, NF1),				/* Data Input */
+	PAD_CFG_NF(GPP_R4, NATIVE, DEEP, NF1),				/* Reset */
+
 	/* GPD2:	LAN Wake					*/
 	PAD_NC(GPD2, NONE),
 	/* GPD6:	Sleep A						*/
@@ -422,16 +429,6 @@ const struct pad_config gpio_table[] = {
 	/* T15:		 Not Connected					*/
 	PAD_NC(GPP_T15, NONE),
 
-	/* R0:		HDA BCLK				*/
-	PAD_CFG_NF(GPP_R0, NATIVE, DEEP, NF1),
-	/* R1:		HDA SYNC				*/
-	PAD_CFG_NF(GPP_R1, NATIVE, DEEP, NF1),
-	/* R2:		HDA SDO					*/
-	PAD_CFG_NF(GPP_R2, NATIVE, DEEP, NF1),
-	/* R3:		HDA SDI					*/
-	PAD_CFG_NF(GPP_R3, NATIVE, DEEP, NF1),
-	/* R4:		HDA Reset				*/
-	PAD_CFG_NF(GPP_R4, NATIVE, DEEP, NF1),
 	/* R5:		MiPi Cam Reset				*/
 	PAD_NC(GPP_R5, NONE),
 	/* R6:		Not Connected				*/
diff --git a/src/mainboard/starlabs/starbook/variants/tgl/gpio.c b/src/mainboard/starlabs/starbook/variants/tgl/gpio.c
index 11b52ceb9a..6dae00171f 100644
--- a/src/mainboard/starlabs/starbook/variants/tgl/gpio.c
+++ b/src/mainboard/starlabs/starbook/variants/tgl/gpio.c
@@ -51,6 +51,13 @@ const struct pad_config gpio_table[] = {
 	PAD_CFG_NF(GPP_C6, NONE, PWROK, NF1),				/* SML Clock */
 	PAD_CFG_NF(GPP_C7, NONE, PWROK, NF1),				/* SML Data */
 
+	/* High-Definition Audio */
+	PAD_CFG_NF(GPP_R0, NATIVE, DEEP, NF1),				/* Clock */
+	PAD_CFG_NF(GPP_R1, NATIVE, DEEP, NF1),				/* Sync */
+	PAD_CFG_NF(GPP_R2, NATIVE, DEEP, NF1),				/* Data Output */
+	PAD_CFG_NF(GPP_R3, NATIVE, DEEP, NF1),				/* Data Input */
+	PAD_NC(GPP_R4, NONE),						/* Reset */
+
 	/* GPD2:	LAN_WAKE#		*/
 	PAD_NC(GPD2, NONE),
 	/* GPD6:	SIO_SLP_A#		*/
@@ -346,16 +353,6 @@ const struct pad_config gpio_table[] = {
 	/* H23:	Not Connected			*/
 	PAD_NC(GPP_H23, NONE),
 
-	/* R0:	HDA_BCLK			*/
-	PAD_CFG_NF(GPP_R0, NONE, DEEP, NF1),
-	/* R1:	HDA_SYNC			*/
-	PAD_CFG_NF(GPP_R1, NATIVE, DEEP, NF1),
-	/* R2:	HDA_SDO				*/
-	PAD_CFG_NF(GPP_R2, NATIVE, DEEP, NF1),
-	/* R3:	HDA_SDI_0_SSP0_RXD		*/
-	PAD_CFG_NF(GPP_R3, NATIVE, DEEP, NF1),
-	/* R4:	Not Connected			*/
-	PAD_NC(GPP_R4, NONE),
 	/* R5:	Not Connected			*/
 	PAD_NC(GPP_R5, NONE),
 	/* R6:	Not Connected			*/
diff --git a/src/mainboard/starlabs/starfighter/variants/rpl/gpio.c b/src/mainboard/starlabs/starfighter/variants/rpl/gpio.c
index 6b47970c32..3b0fd464dc 100644
--- a/src/mainboard/starlabs/starfighter/variants/rpl/gpio.c
+++ b/src/mainboard/starlabs/starfighter/variants/rpl/gpio.c
@@ -69,6 +69,13 @@ const struct pad_config gpio_table[] = {
 	PAD_CFG_NF(GPP_C6, NONE, DEEP, NF1),				/* SML Clock */
 	PAD_CFG_NF(GPP_C7, NONE, DEEP, NF1),				/* SML Data */
 
+	/* High-Definition Audio */
+	PAD_CFG_NF(GPP_R0, NATIVE, DEEP, NF1),				/* Clock */
+	PAD_CFG_NF(GPP_R1, NATIVE, DEEP, NF1),				/* Sync */
+	PAD_CFG_NF(GPP_R2, NATIVE, DEEP, NF1),				/* Data Output */
+	PAD_CFG_NF(GPP_R3, NATIVE, DEEP, NF1),				/* Data Input */
+	PAD_CFG_NF(GPP_R4, NATIVE, DEEP, NF1),				/* Reset */
+
 	/* GPD2:	LAN Wake					*/
 	PAD_NC(GPD2, NONE),
 	/* GPD6:	Sleep A						*/
@@ -419,16 +426,6 @@ const struct pad_config gpio_table[] = {
 	/* T15:		 Not Connected					*/
 	PAD_NC(GPP_T15, NONE),
 
-	/* R0:		HDA BCLK					*/
-	PAD_CFG_NF(GPP_R0, NATIVE, DEEP, NF1),
-	/* R1:		HDA SYNC					*/
-	PAD_CFG_NF(GPP_R1, NATIVE, DEEP, NF1),
-	/* R2:		HDA SDO						*/
-	PAD_CFG_NF(GPP_R2, NATIVE, DEEP, NF1),
-	/* R3:		HDA SDI						*/
-	PAD_CFG_NF(GPP_R3, NATIVE, DEEP, NF1),
-	/* R4:		HDA Reset					*/
-	PAD_CFG_NF(GPP_R4, NATIVE, DEEP, NF1),
 	/* R5:		MiPi Cam Reset					*/
 	PAD_NC(GPP_R5, NONE),
 	/* R6:		Not Connected					*/
diff --git a/src/mainboard/starlabs/starlite_adl/variants/mk_v/gpio.c b/src/mainboard/starlabs/starlite_adl/variants/mk_v/gpio.c
index 0e65185c46..edb2cbcf9f 100644
--- a/src/mainboard/starlabs/starlite_adl/variants/mk_v/gpio.c
+++ b/src/mainboard/starlabs/starlite_adl/variants/mk_v/gpio.c
@@ -57,6 +57,13 @@ const struct pad_config gpio_table[] = {
 	PAD_CFG_NF(GPP_A19, NONE, DEEP, NF1),				/* TCP0 Hot Plug */
 	PAD_CFG_NF(GPP_A20, NONE, DEEP, NF1),				/* TCP0 Hot Plug */
 
+	/* High-Definition Audio */
+	PAD_CFG_NF(GPP_R0, NATIVE, DEEP, NF1),				/* Clock */
+	PAD_CFG_NF(GPP_R1, NATIVE, DEEP, NF1),				/* Sync */
+	PAD_CFG_NF(GPP_R2, NATIVE, DEEP, NF1),				/* Data Output */
+	PAD_CFG_NF(GPP_R3, NATIVE, DEEP, NF1),				/* Data Input */
+	PAD_CFG_NF(GPP_R4, NATIVE, DEEP, NF1),				/* Reset */
+
 	/* GPD2:	LAN Wake					*/
 	PAD_NC(GPD2, NONE),
 	/* GPD6:	Sleep A						*/
@@ -418,16 +425,6 @@ const struct pad_config gpio_table[] = {
 	/* T15:		 Not Connected					*/
 	PAD_NC(GPP_T15, NONE),
 
-	/* R0:		HDA BCLK					*/
-	PAD_CFG_NF(GPP_R0, NATIVE, DEEP, NF1),
-	/* R1:		HDA SYNC					*/
-	PAD_CFG_NF(GPP_R1, NATIVE, DEEP, NF1),
-	/* R2:		HDA SDO						*/
-	PAD_CFG_NF(GPP_R2, NATIVE, DEEP, NF1),
-	/* R3:		HDA SDI						*/
-	PAD_CFG_NF(GPP_R3, NATIVE, DEEP, NF1),
-	/* R4:		HDA Reset					*/
-	PAD_CFG_NF(GPP_R4, NATIVE, DEEP, NF1),
 	/* R5:		Not Connected					*/
 	PAD_NC(GPP_R5, NONE),
 	/* R6:		Not Connected					*/

From 4290340ae5d8e1bf708be191048951b8b4e3591f Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Wed, 2 Apr 2025 13:57:07 +0100
Subject: [PATCH 0596/3886] mb/starlabs/starbook/*: Tidy GPIO comments for PCH

This is a non-functional change, and only makes the GPIOs easier to read.

Change-Id: I8dd5fade69b9e1c2b24b8ffaeac7f72e72894b9c
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87111
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 .../starlabs/byte_adl/variants/mk_ii/gpio.c     | 17 +++++++----------
 .../starlabs/starbook/variants/adl/gpio.c       | 17 +++++++----------
 .../starlabs/starbook/variants/cml/gpio.c       |  8 ++++----
 .../starlabs/starbook/variants/kbl/gpio.c       |  5 +++--
 .../starlabs/starbook/variants/mtl/gpio.c       | 11 +++++------
 .../starlabs/starbook/variants/rpl/gpio.c       | 17 +++++++----------
 .../starlabs/starbook/variants/tgl/gpio.c       |  8 ++++----
 .../starlabs/starfighter/variants/rpl/gpio.c    | 15 +++++++--------
 .../starlabs/starlite_adl/variants/mk_v/gpio.c  | 17 +++++++----------
 9 files changed, 51 insertions(+), 64 deletions(-)

diff --git a/src/mainboard/starlabs/byte_adl/variants/mk_ii/gpio.c b/src/mainboard/starlabs/byte_adl/variants/mk_ii/gpio.c
index ba3b233eaa..a7a7fdf132 100644
--- a/src/mainboard/starlabs/byte_adl/variants/mk_ii/gpio.c
+++ b/src/mainboard/starlabs/byte_adl/variants/mk_ii/gpio.c
@@ -63,6 +63,13 @@ const struct pad_config gpio_table[] = {
 	PAD_CFG_NF(GPP_R3, NATIVE, DEEP, NF1),				/* Data Input */
 	PAD_CFG_NF(GPP_R4, NATIVE, DEEP, NF1),				/* Reset */
 
+	/* PCH */
+	PAD_CFG_NF(GPP_H18, NONE, DEEP, NF1),				/* C10 Gate */
+	PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1),				/* Platform Reset */
+	PAD_CFG_NF(GPP_B0, NONE, DEEP, NF1),				/* Vendor ID 0 */
+	PAD_CFG_NF(GPP_B1, NONE, DEEP, NF1),				/* Vendor ID 1 */
+	PAD_CFG_GPI_SCI(GPP_B2, NONE, PLTRST, EDGE_SINGLE, INVERT),	/* Processor Hot */
+
 	/* GPD2:	LAN Wake					*/
 	PAD_NC(GPD2, NONE),
 	/* GPD6:	Sleep A						*/
@@ -106,12 +113,6 @@ const struct pad_config gpio_table[] = {
 	PAD_NC(GPP_A23, NONE),
 
 
-	/* B0:		Core Vendor ID 0				*/
-	PAD_CFG_NF(GPP_B0, NONE, DEEP, NF1),
-	/* B1:		Core Vendor ID 1				*/
-	PAD_CFG_NF(GPP_B1, NONE, DEEP, NF1),
-	/* B2:		BC PROCHOT					*/
-	PAD_CFG_GPI_SCI(GPP_B2, NONE, PLTRST, EDGE_SINGLE, INVERT),
 	/* B3:		Not Connected					*/
 	PAD_NC(GPP_B3, NONE),
 	/* B4:		Not Connected					*/
@@ -132,8 +133,6 @@ const struct pad_config gpio_table[] = {
 	PAD_CFG_NF(GPP_B11, NONE, DEEP, NF1),
 	/* B12:		PM SLP S0					*/
 	PAD_NC(GPP_B12, NONE),
-	/* B13:		PLT RST						*/
-	PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1),
 	/* B14:		Top Swap Override	Weak Internal PD 20K
 				High:	Enabled
 				Low:	Disabled			*/
@@ -365,8 +364,6 @@ const struct pad_config gpio_table[] = {
 	PAD_NC(GPP_H14, NONE),
 	/* H16:		Not Connected					*/
 	PAD_NC(GPP_H16, NONE),
-	/* H18:		CPI C10 Gate					*/
-	PAD_CFG_NF(GPP_H18, NONE, DEEP, NF1),
 	/* H19:		Clock Request 4					*/
 	PAD_NC(GPP_H19, NONE),
 	/* H20:		Not Connected					*/
diff --git a/src/mainboard/starlabs/starbook/variants/adl/gpio.c b/src/mainboard/starlabs/starbook/variants/adl/gpio.c
index 58fd8d8dc6..da27f69bd4 100644
--- a/src/mainboard/starlabs/starbook/variants/adl/gpio.c
+++ b/src/mainboard/starlabs/starbook/variants/adl/gpio.c
@@ -64,6 +64,13 @@ const struct pad_config gpio_table[] = {
 	PAD_CFG_NF(GPP_R3, NATIVE, DEEP, NF1),				/* Data Input */
 	PAD_CFG_NF(GPP_R4, NATIVE, DEEP, NF1),				/* Reset */
 
+	/* PCH */
+	PAD_CFG_NF(GPP_H18, NONE, DEEP, NF1),				/* C10 Gate */
+	PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1),				/* Platform Reset */
+	PAD_CFG_NF(GPP_B0, NONE, DEEP, NF1),				/* Vendor ID 0 */
+	PAD_CFG_NF(GPP_B1, NONE, DEEP, NF1),				/* Vendor ID 1 */
+	PAD_CFG_GPI_SCI(GPP_B2, NONE, PLTRST, EDGE_SINGLE, INVERT),	/* Processor Hot */
+
 	/* GPD2:	LAN Wake					*/
 	PAD_NC(GPD2, NONE),
 	/* GPD6:	Sleep A						*/
@@ -106,12 +113,6 @@ const struct pad_config gpio_table[] = {
 	/* A23:		Not Connected					*/
 	PAD_NC(GPP_A23, NONE),
 
-	/* B0:		Core Vendor ID 0				*/
-	PAD_CFG_NF(GPP_B0, NONE, DEEP, NF1),
-	/* B1:		Core Vendor ID 1				*/
-	PAD_CFG_NF(GPP_B1, NONE, DEEP, NF1),
-	/* B2:		BC PROCHOT					*/
-	PAD_CFG_GPI_SCI(GPP_B2, NONE, PLTRST, EDGE_SINGLE, INVERT),
 	/* B3:		Not Connected					*/
 	PAD_NC(GPP_B3, NONE),
 	/* B4:		Not Connected					*/
@@ -132,8 +133,6 @@ const struct pad_config gpio_table[] = {
 	PAD_NC(GPP_B11, NONE),
 	/* B12:		PM SLP S0					*/
 	PAD_NC(GPP_B12, NONE),
-	/* B13:		PLT RST						*/
-	PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1),
 	/* B14:		Top Swap Override	Weak Internal PD 20K
 				High:	Enabled
 				Low:	Disabled			*/
@@ -367,8 +366,6 @@ const struct pad_config gpio_table[] = {
 	PAD_NC(GPP_H14, NONE),
 	/* H16:		Not Connected					*/
 	PAD_NC(GPP_H16, NONE),
-	/* H18:		CPI C10 Gate					*/
-	PAD_CFG_NF(GPP_H18, NONE, DEEP, NF1),
 	/* H19:		Clock Request 4		CPU M.2 SSD		*/
 	PAD_NC(GPP_H19, NONE),
 	/* H20:		Not Connected					*/
diff --git a/src/mainboard/starlabs/starbook/variants/cml/gpio.c b/src/mainboard/starlabs/starbook/variants/cml/gpio.c
index 4159f258a6..e916a9ff42 100644
--- a/src/mainboard/starlabs/starbook/variants/cml/gpio.c
+++ b/src/mainboard/starlabs/starbook/variants/cml/gpio.c
@@ -59,6 +59,10 @@ const struct pad_config gpio_table[] = {
 	PAD_CFG_NF(GPP_E19, NONE, DEEP, NF1),				/* HDMI Data */
 	PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1),				/* TCP0 Hot Plug */
 
+	/* PCH */
+	PAD_CFG_NF(GPP_H18, NONE, DEEP, NF1),				/* C10 Gate */
+	PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1),				/* Platform Reset */
+
 	/* GPD2:	LAN_WAKE#		*/
 	PAD_NC(GPD2, NONE),
 	/* GPD6:	SIO_SLP_A#		*/
@@ -141,8 +145,6 @@ const struct pad_config gpio_table[] = {
 	PAD_CFG_GPO(GPP_B11, 1, PLTRST),
 	/* B12:	 PM_SLP_S0_N			*/
 	PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1),
-	/* B13:	 PLT_RST_N			*/
-	PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1),
 	/* B14:	 TCH_PNL_PWR_EN			*/
 	PAD_CFG_GPO(GPP_B14, 1, PLTRST),
 	/* B15:	Not Connected			*/
@@ -373,8 +375,6 @@ const struct pad_config gpio_table[] = {
 	PAD_NC(GPP_H16, NONE),
 	/* H17:	 GPPC_H_17_WWAN_DISABLE_N	*/
 	PAD_CFG_GPO(GPP_H17, 0, DEEP),
-	/* H18:	 GPPC_H_18_CPU_C10		*/
-	PAD_CFG_NF(GPP_H18, NONE, DEEP, NF1),
 	/* H19:	Not Connected			*/
 	PAD_NC(GPP_H19, NONE),
 	/* H20:	Not Connected			*/
diff --git a/src/mainboard/starlabs/starbook/variants/kbl/gpio.c b/src/mainboard/starlabs/starbook/variants/kbl/gpio.c
index b96476d1b0..9c195957d3 100644
--- a/src/mainboard/starlabs/starbook/variants/kbl/gpio.c
+++ b/src/mainboard/starlabs/starbook/variants/kbl/gpio.c
@@ -44,6 +44,9 @@ const struct pad_config gpio_table[] = {
 	PAD_CFG_NF(GPP_E19, DN_20K, DEEP, NF1),				/* HDMI Data */
 	PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1),				/* TCP0 Hot Plug */
 
+	/* PCH */
+	PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1),				/* Platform Reset */
+
 	/* GPD2:	Not Connected		*/
 	PAD_NC(GPD2, NONE),
 	/* GPD6:	Not Connected		*/
@@ -126,8 +129,6 @@ const struct pad_config gpio_table[] = {
 	PAD_NC(GPP_B11, DN_20K),
 	/* GPP_B12	SLP_S0_N		*/
 	PAD_NC(GPP_B12, DN_20K),
-	/* GPP_B13:	SYS_RESET#		*/
-	PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1),
 	/* GPP_B14:	HDA_SPKR		*/
 	PAD_NC(GPP_B14, DN_20K),
 	/* GPP_B15:	Not Connected		*/
diff --git a/src/mainboard/starlabs/starbook/variants/mtl/gpio.c b/src/mainboard/starlabs/starbook/variants/mtl/gpio.c
index 5d95d61a89..0339413c02 100644
--- a/src/mainboard/starlabs/starbook/variants/mtl/gpio.c
+++ b/src/mainboard/starlabs/starbook/variants/mtl/gpio.c
@@ -71,6 +71,11 @@ const struct pad_config gpio_table[] = {
 	PAD_CFG_NF(GPP_D13, NATIVE, DEEP, NF1),				/* Data Input */
 	PAD_CFG_NF(GPP_D17, NATIVE, DEEP, NF1),				/* Reset */
 
+	/* PCH */
+	PAD_CFG_NF(GPP_H13, NONE, DEEP, NF1),				/* C10 Gate */
+	PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1),				/* Platform Reset */
+	PAD_CFG_GPI_SCI(GPP_E16, NONE, PLTRST, EDGE_SINGLE, INVERT),	/* Processor Hot */
+
 	/* V02:	PCIE_WAKE_LAN			*/
 	PAD_NC(GPP_V02, NONE),
 	/* V06:	GPD_6_SLP_A_N			*/
@@ -237,8 +242,6 @@ const struct pad_config gpio_table[] = {
 	PAD_NC(GPP_E13, NONE),
 	/* E15:	BOOTHALT_N			*/
 	PAD_CFG_NF(GPP_E15, NONE, DEEP, NF2),
-	/* E16:	BC_PROCHOT_N			*/
-	PAD_CFG_GPI_SCI(GPP_E16, NONE, PLTRST, EDGE_SINGLE, INVERT),
 	/* E17:					*/
 	PAD_NC(GPP_E17, NONE),
 	/* E18:					*/
@@ -278,8 +281,6 @@ const struct pad_config gpio_table[] = {
 	PAD_NC(GPP_H11, NONE),
 	/* H12:					*/
 	PAD_NC(GPP_H12, NONE),
-	/* H13:	CPU_C10_GATE_N_R		*/
-	PAD_CFG_NF(GPP_H13, NONE, DEEP, NF1),
 	/* H14:					*/
 	PAD_NC(GPP_H14, NONE),
 	/* H15:					*/
@@ -411,8 +412,6 @@ const struct pad_config gpio_table[] = {
 	PAD_NC(GPP_B11, NONE),
 	/* B12:					*/
 	PAD_NC(GPP_B12, NONE),
-	/* B13:	PLT_RST_N			*/
-	PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1),
 	/* B14:	Top Swap Override
 	 *		HIGH:	EMABLED
 	 *		LOW:	DISABLED
diff --git a/src/mainboard/starlabs/starbook/variants/rpl/gpio.c b/src/mainboard/starlabs/starbook/variants/rpl/gpio.c
index 0fed120f9a..4a328e6f66 100644
--- a/src/mainboard/starlabs/starbook/variants/rpl/gpio.c
+++ b/src/mainboard/starlabs/starbook/variants/rpl/gpio.c
@@ -66,6 +66,13 @@ const struct pad_config gpio_table[] = {
 	PAD_CFG_NF(GPP_R3, NATIVE, DEEP, NF1),				/* Data Input */
 	PAD_CFG_NF(GPP_R4, NATIVE, DEEP, NF1),				/* Reset */
 
+	/* PCH */
+	PAD_CFG_NF(GPP_H18, NONE, DEEP, NF1),				/* C10 Gate */
+	PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1),				/* Platform Reset */
+	PAD_CFG_NF(GPP_B0, NONE, DEEP, NF1),				/* Vendor ID 0 */
+	PAD_CFG_NF(GPP_B1, NONE, DEEP, NF1),				/* Vendor ID 1 */
+	PAD_CFG_GPI_SCI(GPP_B2, NONE, PLTRST, EDGE_SINGLE, INVERT),	/* Processor Hot */
+
 	/* GPD2:	LAN Wake					*/
 	PAD_NC(GPD2, NONE),
 	/* GPD6:	Sleep A						*/
@@ -111,12 +118,6 @@ const struct pad_config gpio_table[] = {
 	/* A23:		Not Connected					*/
 	PAD_NC(GPP_A23, NONE),
 
-	/* B0:		Core Vendor ID 0				*/
-	PAD_CFG_NF(GPP_B0, NONE, DEEP, NF1),
-	/* B1:		Core Vendor ID 1				*/
-	PAD_CFG_NF(GPP_B1, NONE, DEEP, NF1),
-	/* B2:		BC PROCHOT					*/
-	PAD_CFG_GPI_SCI(GPP_B2, NONE, PLTRST, EDGE_SINGLE, INVERT),
 	/* B3:		Not Connected					*/
 	PAD_NC(GPP_B3, NONE),
 	/* B4:		Not Connected					*/
@@ -135,8 +136,6 @@ const struct pad_config gpio_table[] = {
 	PAD_NC(GPP_B10, NONE),
 	/* B12:		PM SLP S0					*/
 	PAD_NC(GPP_B12, NONE),
-	/* B13:		PLT RST						*/
-	PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1),
 	/* B14:		Top Swap Override	Weak Internal PD 20K
 				High:	Enabled
 				Low:	Disabled			*/
@@ -368,8 +367,6 @@ const struct pad_config gpio_table[] = {
 	PAD_NC(GPP_H14, NONE),
 	/* H16:		Not Connected					*/
 	PAD_NC(GPP_H16, NONE),
-	/* H18:		CPI C10 Gate					*/
-	PAD_CFG_NF(GPP_H18, NONE, DEEP, NF1),
 	/* H20:		Not Connected					*/
 	PAD_NC(GPP_H20, NONE),
 	/* H21:		Not Connected					*/
diff --git a/src/mainboard/starlabs/starbook/variants/tgl/gpio.c b/src/mainboard/starlabs/starbook/variants/tgl/gpio.c
index 6dae00171f..eb75e31af2 100644
--- a/src/mainboard/starlabs/starbook/variants/tgl/gpio.c
+++ b/src/mainboard/starlabs/starbook/variants/tgl/gpio.c
@@ -58,6 +58,10 @@ const struct pad_config gpio_table[] = {
 	PAD_CFG_NF(GPP_R3, NATIVE, DEEP, NF1),				/* Data Input */
 	PAD_NC(GPP_R4, NONE),						/* Reset */
 
+	/* PCH */
+	PAD_CFG_NF(GPP_H18, NONE, DEEP, NF1),				/* C10 Gate */
+	PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1),				/* Platform Reset */
+
 	/* GPD2:	LAN_WAKE#		*/
 	PAD_NC(GPD2, NONE),
 	/* GPD6:	SIO_SLP_A#		*/
@@ -127,8 +131,6 @@ const struct pad_config gpio_table[] = {
 	PAD_CFG_NF(GPP_B10, NONE, DEEP, NF1),
 	/* B12:	PM_SLP_S0_N			*/
 	PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1),
-	/* B13:	PLT_RST_N			*/
-	PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1),
 	/* B14:	FPS_RST_N			*/
 	PAD_CFG_GPO(GPP_B14, 1, PLTRST),
 	/* B15:	Not Connected			*/
@@ -340,8 +342,6 @@ const struct pad_config gpio_table[] = {
 	PAD_NC(GPP_H14, NONE),
 	/* H15:	Not Connected			*/
 	PAD_NC(GPP_H15, NONE),
-	/* H18:	CPU_C10_GATE_N			*/
-	PAD_CFG_NF(GPP_H18, NONE, DEEP, NF1),
 	/* H19:	UART_BT_WAKE_N			*/
 	PAD_NC(GPP_H19, NONE),
 	/* H20:	Not Connected			*/
diff --git a/src/mainboard/starlabs/starfighter/variants/rpl/gpio.c b/src/mainboard/starlabs/starfighter/variants/rpl/gpio.c
index 3b0fd464dc..b9b08919ce 100644
--- a/src/mainboard/starlabs/starfighter/variants/rpl/gpio.c
+++ b/src/mainboard/starlabs/starfighter/variants/rpl/gpio.c
@@ -76,6 +76,13 @@ const struct pad_config gpio_table[] = {
 	PAD_CFG_NF(GPP_R3, NATIVE, DEEP, NF1),				/* Data Input */
 	PAD_CFG_NF(GPP_R4, NATIVE, DEEP, NF1),				/* Reset */
 
+	/* PCH */
+	PAD_CFG_NF(GPP_H18, NONE, DEEP, NF1),				/* C10 Gate */
+	PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1),				/* Platform Reset */
+	PAD_CFG_NF(GPP_B0, NONE, DEEP, NF1),				/* Vendor ID 0 */
+	PAD_CFG_NF(GPP_B1, NONE, DEEP, NF1),				/* Vendor ID 1 */
+	PAD_CFG_GPI_SCI(GPP_B2, NONE, PLTRST, EDGE_SINGLE, INVERT),	/* Processor Hot */
+
 	/* GPD2:	LAN Wake					*/
 	PAD_NC(GPD2, NONE),
 	/* GPD6:	Sleep A						*/
@@ -120,12 +127,6 @@ const struct pad_config gpio_table[] = {
 	/* A23:		Not Connected					*/
 	PAD_NC(GPP_A23, NONE),
 
-	/* B0:		Core Vendor ID 0				*/
-	PAD_CFG_NF(GPP_B0, NONE, DEEP, NF1),
-	/* B1:		Core Vendor ID 1				*/
-	PAD_CFG_NF(GPP_B1, NONE, DEEP, NF1),
-	/* B2:		BC PROCHOT					*/
-	PAD_CFG_GPI_SCI(GPP_B2, NONE, PLTRST, EDGE_SINGLE, INVERT),
 	/* B3:		Not Connected					*/
 	PAD_NC(GPP_B3, NONE),
 	/* B4:		Not Connected					*/
@@ -363,8 +364,6 @@ const struct pad_config gpio_table[] = {
 	PAD_NC(GPP_H14, NONE),
 	/* H16:		Not Connected					*/
 	PAD_NC(GPP_H16, NONE),
-	/* H18:		CPI C10 Gate					*/
-	PAD_CFG_NF(GPP_H18, NONE, DEEP, NF1),
 	/* H19:		Clock Request 4		CPU M.2 SSD		*/
 	PAD_CFG_NF(GPP_H19, NONE, DEEP, NF1),
 	/* H20:		Not Connected					*/
diff --git a/src/mainboard/starlabs/starlite_adl/variants/mk_v/gpio.c b/src/mainboard/starlabs/starlite_adl/variants/mk_v/gpio.c
index edb2cbcf9f..58e3d12f08 100644
--- a/src/mainboard/starlabs/starlite_adl/variants/mk_v/gpio.c
+++ b/src/mainboard/starlabs/starlite_adl/variants/mk_v/gpio.c
@@ -64,6 +64,13 @@ const struct pad_config gpio_table[] = {
 	PAD_CFG_NF(GPP_R3, NATIVE, DEEP, NF1),				/* Data Input */
 	PAD_CFG_NF(GPP_R4, NATIVE, DEEP, NF1),				/* Reset */
 
+	/* PCH */
+	PAD_CFG_NF(GPP_H18, NONE, DEEP, NF1),				/* C10 Gate */
+	PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1),				/* Platform Reset */
+	PAD_CFG_NF(GPP_B0, NONE, DEEP, NF1),				/* Vendor ID 0 */
+	PAD_CFG_NF(GPP_B1, NONE, DEEP, NF1),				/* Vendor ID 1 */
+	PAD_CFG_GPI_SCI(GPP_B2, NONE, PLTRST, EDGE_SINGLE, INVERT),	/* Processor Hot */
+
 	/* GPD2:	LAN Wake					*/
 	PAD_NC(GPD2, NONE),
 	/* GPD6:	Sleep A						*/
@@ -105,12 +112,6 @@ const struct pad_config gpio_table[] = {
 	PAD_NC(GPP_A23, NONE),
 
 
-	/* B0:		Core Vendor ID 0				*/
-	PAD_CFG_NF(GPP_B0, NONE, DEEP, NF1),
-	/* B1:		Core Vendor ID 1				*/
-	PAD_CFG_NF(GPP_B1, NONE, DEEP, NF1),
-	/* B2:		BC PROCHOT					*/
-	PAD_CFG_GPI_SCI(GPP_B2, NONE, PLTRST, EDGE_SINGLE, INVERT),
 	/* B3:		Not Connected					*/
 	PAD_NC(GPP_B3, NONE),
 	/* B4:		Not Connected					*/
@@ -131,8 +132,6 @@ const struct pad_config gpio_table[] = {
 	PAD_NC(GPP_B11, NONE),
 	/* B12:		PM SLP S0					*/
 	PAD_NC(GPP_B12, NONE),
-	/* B13:		PLT RST						*/
-	PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1),
 	/* B14:		Webcam Privacy LED				*/
 	PAD_NC(GPP_B14, NONE),
 	/* B15:		Not Connected					*/
@@ -362,8 +361,6 @@ const struct pad_config gpio_table[] = {
 	PAD_NC(GPP_H14, NONE),
 	/* H16:		Not Connected					*/
 	PAD_NC(GPP_H16, NONE),
-	/* H18:		CPI C10 Gate					*/
-	PAD_CFG_NF(GPP_H18, NONE, DEEP, NF1),
 	/* H19:		Clock Request 4					*/
 	PAD_NC(GPP_H19, NONE),
 	/* H20:		Webcam Clock					*/

From f1115883779eb0a2c8394bfcf8838800c111243e Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Wed, 2 Apr 2025 13:59:28 +0100
Subject: [PATCH 0597/3886] mb/starlabs/starbook/*: Tidy GPIO comments for the
 TPM

This is a non-functional change, and only makes the GPIOs easier to read.

Change-Id: Ibd60b124efa4f5cb0688ee097574884b9912fb66
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87112
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/starlabs/starbook/variants/adl/gpio.c    | 5 +++--
 src/mainboard/starlabs/starbook/variants/mtl/gpio.c    | 5 +++--
 src/mainboard/starlabs/starbook/variants/rpl/gpio.c    | 5 +++--
 src/mainboard/starlabs/starbook/variants/tgl/gpio.c    | 5 +++--
 src/mainboard/starlabs/starfighter/variants/rpl/gpio.c | 5 +++--
 5 files changed, 15 insertions(+), 10 deletions(-)

diff --git a/src/mainboard/starlabs/starbook/variants/adl/gpio.c b/src/mainboard/starlabs/starbook/variants/adl/gpio.c
index da27f69bd4..774440b044 100644
--- a/src/mainboard/starlabs/starbook/variants/adl/gpio.c
+++ b/src/mainboard/starlabs/starbook/variants/adl/gpio.c
@@ -71,6 +71,9 @@ const struct pad_config gpio_table[] = {
 	PAD_CFG_NF(GPP_B1, NONE, DEEP, NF1),				/* Vendor ID 1 */
 	PAD_CFG_GPI_SCI(GPP_B2, NONE, PLTRST, EDGE_SINGLE, INVERT),	/* Processor Hot */
 
+	/* TPM */
+	PAD_CFG_GPI_APIC_LOW(GPP_E11, NONE, PLTRST),			/* Interrupt */
+
 	/* GPD2:	LAN Wake					*/
 	PAD_NC(GPD2, NONE),
 	/* GPD6:	Sleep A						*/
@@ -272,8 +275,6 @@ const struct pad_config gpio_table[] = {
 	PAD_NC(GPP_E9, NONE),
 	/* E10:		PWD Amplifier Input				*/
 	PAD_NC(GPP_E10, NONE),
-	/* E11:		TPM IRQ						*/
-	PAD_CFG_GPI_APIC_LOW(GPP_E11, NONE, PLTRST),
 	/* E13:		Not connected					*/
 	PAD_NC(GPP_E13, NONE),
 	/* E15:		Not Connected					*/
diff --git a/src/mainboard/starlabs/starbook/variants/mtl/gpio.c b/src/mainboard/starlabs/starbook/variants/mtl/gpio.c
index 0339413c02..efe8de2325 100644
--- a/src/mainboard/starlabs/starbook/variants/mtl/gpio.c
+++ b/src/mainboard/starlabs/starbook/variants/mtl/gpio.c
@@ -76,6 +76,9 @@ const struct pad_config gpio_table[] = {
 	PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1),				/* Platform Reset */
 	PAD_CFG_GPI_SCI(GPP_E16, NONE, PLTRST, EDGE_SINGLE, INVERT),	/* Processor Hot */
 
+	/* TPM */
+	PAD_CFG_GPI_APIC_LOW(GPP_F13, NONE, PLTRST),			/* Interrupt */
+
 	/* V02:	PCIE_WAKE_LAN			*/
 	PAD_NC(GPP_V02, NONE),
 	/* V06:	GPD_6_SLP_A_N			*/
@@ -325,8 +328,6 @@ const struct pad_config gpio_table[] = {
 	PAD_NC(GPP_F11, NONE),
 	/* F12:					*/
 	PAD_NC(GPP_F12, NONE),
-	/* F13:	TPM_IRQ				*/
-	PAD_CFG_GPI_APIC_LOW(GPP_F13, NONE, PLTRST),
 	/* F14:					*/
 	PAD_NC(GPP_F14, NONE),
 	/* F15:					*/
diff --git a/src/mainboard/starlabs/starbook/variants/rpl/gpio.c b/src/mainboard/starlabs/starbook/variants/rpl/gpio.c
index 4a328e6f66..042a24d0be 100644
--- a/src/mainboard/starlabs/starbook/variants/rpl/gpio.c
+++ b/src/mainboard/starlabs/starbook/variants/rpl/gpio.c
@@ -73,6 +73,9 @@ const struct pad_config gpio_table[] = {
 	PAD_CFG_NF(GPP_B1, NONE, DEEP, NF1),				/* Vendor ID 1 */
 	PAD_CFG_GPI_SCI(GPP_B2, NONE, PLTRST, EDGE_SINGLE, INVERT),	/* Processor Hot */
 
+	/* TPM */
+	PAD_CFG_GPI_APIC_LOW(GPP_E11, NONE, PLTRST),			/* Interrupt */
+
 	/* GPD2:	LAN Wake					*/
 	PAD_NC(GPD2, NONE),
 	/* GPD6:	Sleep A						*/
@@ -273,8 +276,6 @@ const struct pad_config gpio_table[] = {
 	PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1),
 	/* E10:		PWD Amplifier Input				*/
 	PAD_NC(GPP_E10, NONE),
-	/* E11:		TPM IRQ						*/
-	PAD_CFG_GPI_APIC_LOW(GPP_E11, NONE, PLTRST),
 	/* E13:		Not connected					*/
 	PAD_NC(GPP_E13, NONE),
 	/* E15:		Not Connected					*/
diff --git a/src/mainboard/starlabs/starbook/variants/tgl/gpio.c b/src/mainboard/starlabs/starbook/variants/tgl/gpio.c
index eb75e31af2..fab78cbafa 100644
--- a/src/mainboard/starlabs/starbook/variants/tgl/gpio.c
+++ b/src/mainboard/starlabs/starbook/variants/tgl/gpio.c
@@ -62,6 +62,9 @@ const struct pad_config gpio_table[] = {
 	PAD_CFG_NF(GPP_H18, NONE, DEEP, NF1),				/* C10 Gate */
 	PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1),				/* Platform Reset */
 
+	/* TPM */
+	PAD_CFG_GPI_APIC_LOW(GPP_C14, NONE, PLTRST),			/* Interrupt */
+
 	/* GPD2:	LAN_WAKE#		*/
 	PAD_NC(GPD2, NONE),
 	/* GPD6:	SIO_SLP_A#		*/
@@ -174,8 +177,6 @@ const struct pad_config gpio_table[] = {
 	PAD_NC(GPP_C12, NONE),
 	/* C13:	Not Connected			*/
 	PAD_NC(GPP_C13, NONE),
-	/* C14:	TPM_IRQ				*/
-	PAD_CFG_NF(GPP_C14, NONE, DEEP, NF1),
 	/* C15:	TPM_RST				*/
 	PAD_NC(GPP_C15, NONE),
 	/* C18:	TOUCH_I2C_SDA			*/
diff --git a/src/mainboard/starlabs/starfighter/variants/rpl/gpio.c b/src/mainboard/starlabs/starfighter/variants/rpl/gpio.c
index b9b08919ce..3f26ff7e19 100644
--- a/src/mainboard/starlabs/starfighter/variants/rpl/gpio.c
+++ b/src/mainboard/starlabs/starfighter/variants/rpl/gpio.c
@@ -83,6 +83,9 @@ const struct pad_config gpio_table[] = {
 	PAD_CFG_NF(GPP_B1, NONE, DEEP, NF1),				/* Vendor ID 1 */
 	PAD_CFG_GPI_SCI(GPP_B2, NONE, PLTRST, EDGE_SINGLE, INVERT),	/* Processor Hot */
 
+	/* TPM */
+	PAD_CFG_GPI_APIC_LOW(GPP_D10, NONE, PLTRST),			/* Interrupt */
+
 	/* GPD2:	LAN Wake					*/
 	PAD_NC(GPD2, NONE),
 	/* GPD6:	Sleep A						*/
@@ -237,8 +240,6 @@ const struct pad_config gpio_table[] = {
 	PAD_NC(GPP_D8, NONE),
 	/* D9:		PWD_AMP_IN					*/
 	PAD_NC(GPP_D9, NONE),
-	/* D10:		TPM_IRQ						*/
-	PAD_CFG_GPI_APIC_LOW(GPP_D10, NONE, PLTRST),
 	/* D12:		ES8336_INT_N					*/
 	PAD_NC(GPP_D12, NONE),
 	/* D13:		Wireless LAN Wake				*/

From 2d3c3c03f739a3945101df7923897cc1bc06fb45 Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Wed, 2 Apr 2025 14:03:09 +0100
Subject: [PATCH 0598/3886] mb/starlabs/starbook/*: Tidy GPIO comments for the
 SMBUS

This is a non-functional change, and only makes the GPIOs easier to read.

Change-Id: Ia8a2ff8f370fef6249b1edbb08e00a01dedc3a07
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87113
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/starlabs/byte_adl/variants/mk_ii/gpio.c | 11 +++++------
 src/mainboard/starlabs/starbook/variants/adl/gpio.c   | 11 +++++------
 src/mainboard/starlabs/starbook/variants/cml/gpio.c   |  8 ++++----
 src/mainboard/starlabs/starbook/variants/kbl/gpio.c   |  8 ++++----
 src/mainboard/starlabs/starbook/variants/mtl/gpio.c   |  7 +++----
 src/mainboard/starlabs/starbook/variants/rpl/gpio.c   | 11 +++++------
 src/mainboard/starlabs/starbook/variants/tgl/gpio.c   |  8 ++++----
 .../starlabs/starfighter/variants/rpl/gpio.c          | 11 +++++------
 .../starlabs/starlite_adl/variants/mk_v/gpio.c        | 11 +++++------
 9 files changed, 40 insertions(+), 46 deletions(-)

diff --git a/src/mainboard/starlabs/byte_adl/variants/mk_ii/gpio.c b/src/mainboard/starlabs/byte_adl/variants/mk_ii/gpio.c
index a7a7fdf132..242124c415 100644
--- a/src/mainboard/starlabs/byte_adl/variants/mk_ii/gpio.c
+++ b/src/mainboard/starlabs/byte_adl/variants/mk_ii/gpio.c
@@ -70,6 +70,11 @@ const struct pad_config gpio_table[] = {
 	PAD_CFG_NF(GPP_B1, NONE, DEEP, NF1),				/* Vendor ID 1 */
 	PAD_CFG_GPI_SCI(GPP_B2, NONE, PLTRST, EDGE_SINGLE, INVERT),	/* Processor Hot */
 
+	/* SMBus */
+	PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1),				/* Clock */
+	PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1),				/* Data */
+	PAD_CFG_GPO(GPP_E8, 1, DEEP),					/* DRAM Sleep */
+
 	/* GPD2:	LAN Wake					*/
 	PAD_NC(GPD2, NONE),
 	/* GPD6:	Sleep A						*/
@@ -162,10 +167,6 @@ const struct pad_config gpio_table[] = {
 	/* B25:		Not Connected					*/
 	PAD_NC(GPP_B25, NONE),
 
-	/* C0:		SMB Clock					*/
-	PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1),
-	/* C1:		SMB Data					*/
-	PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1),
 	/* C2:		TLS Confidentiality	Weak Internal PD 20K
 				Low:	Disabled
 				High:	Enabled				*/
@@ -268,8 +269,6 @@ const struct pad_config gpio_table[] = {
 	PAD_CFG_GPO(GPP_E6, 0, DEEP),
 	/* E7:		Embedded Controller SMI				*/
 	PAD_NC(GPP_E7, NONE),
-	/* E8:		DRAM Sleep					*/
-	PAD_CFG_GPO(GPP_E8, 1, DEEP),
 	/* E9:		USB OverCurrent 0				*/
 	PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1),
 	/* E10:		Not Connected					*/
diff --git a/src/mainboard/starlabs/starbook/variants/adl/gpio.c b/src/mainboard/starlabs/starbook/variants/adl/gpio.c
index 774440b044..3ddf06c7fb 100644
--- a/src/mainboard/starlabs/starbook/variants/adl/gpio.c
+++ b/src/mainboard/starlabs/starbook/variants/adl/gpio.c
@@ -74,6 +74,11 @@ const struct pad_config gpio_table[] = {
 	/* TPM */
 	PAD_CFG_GPI_APIC_LOW(GPP_E11, NONE, PLTRST),			/* Interrupt */
 
+	/* SMBus */
+	PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1),				/* Clock */
+	PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1),				/* Data */
+	PAD_CFG_GPO(GPP_E8, 1, DEEP),					/* DRAM Sleep */
+
 	/* GPD2:	LAN Wake					*/
 	PAD_NC(GPD2, NONE),
 	/* GPD6:	Sleep A						*/
@@ -165,10 +170,6 @@ const struct pad_config gpio_table[] = {
 	/* B25:		Not Connected					*/
 	PAD_NC(GPP_B25, NONE),
 
-	/* C0:		SMB Clock					*/
-	PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1),
-	/* C1:		SMB Data					*/
-	PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1),
 	/* C2:		TLS Confidentiality	Weak Internal PD 20K
 				Low:	Disabled
 				High:	Enabled				*/
@@ -269,8 +270,6 @@ const struct pad_config gpio_table[] = {
 	PAD_CFG_GPO(GPP_E6, 0, DEEP),
 	/* E7:		Embedded Controller SMI				*/
 	PAD_NC(GPP_E7, NONE),
-	/* E8:		DRAM Sleep					*/
-	PAD_CFG_GPO(GPP_E8, 1, DEEP),
 	/* E9:		USB OverCurrent 0				*/
 	PAD_NC(GPP_E9, NONE),
 	/* E10:		PWD Amplifier Input				*/
diff --git a/src/mainboard/starlabs/starbook/variants/cml/gpio.c b/src/mainboard/starlabs/starbook/variants/cml/gpio.c
index e916a9ff42..a844562817 100644
--- a/src/mainboard/starlabs/starbook/variants/cml/gpio.c
+++ b/src/mainboard/starlabs/starbook/variants/cml/gpio.c
@@ -63,6 +63,10 @@ const struct pad_config gpio_table[] = {
 	PAD_CFG_NF(GPP_H18, NONE, DEEP, NF1),				/* C10 Gate */
 	PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1),				/* Platform Reset */
 
+	/* SMBus */
+	PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1),				/* Clock */
+	PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1),				/* Data */
+
 	/* GPD2:	LAN_WAKE#		*/
 	PAD_NC(GPD2, NONE),
 	/* GPD6:	SIO_SLP_A#		*/
@@ -166,10 +170,6 @@ const struct pad_config gpio_table[] = {
 	/* B23:	 EC_SLP_S0IX_N			*/
 	PAD_NC(GPP_B23, NONE),
 
-	/* C0:	 SMB_CLK			*/
-	PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1),
-	/* C1:	 SMB_DATA			*/
-	PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1),
 	/* C3:	Not Connected			*/
 	PAD_NC(GPP_C3, NONE),
 	/* C4:	Not Connected			*/
diff --git a/src/mainboard/starlabs/starbook/variants/kbl/gpio.c b/src/mainboard/starlabs/starbook/variants/kbl/gpio.c
index 9c195957d3..cdc34ae46f 100644
--- a/src/mainboard/starlabs/starbook/variants/kbl/gpio.c
+++ b/src/mainboard/starlabs/starbook/variants/kbl/gpio.c
@@ -47,6 +47,10 @@ const struct pad_config gpio_table[] = {
 	/* PCH */
 	PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1),				/* Platform Reset */
 
+	/* SMBus */
+	PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1),				/* Clock */
+	PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1),				/* Data */
+
 	/* GPD2:	Not Connected		*/
 	PAD_NC(GPD2, NONE),
 	/* GPD6:	Not Connected		*/
@@ -149,10 +153,6 @@ const struct pad_config gpio_table[] = {
 	PAD_NC(GPP_B22, DN_20K),
 	/* GPP_B23:	SML1ALERT#/PCHHOT#	*/
 	PAD_NC(GPP_B23, DN_20K),
-	/*GPP_C0:	SMBCLK			*/
-	PAD_CFG_NF(GPP_C0, UP_20K, DEEP, NF1),
-	/* GPP_C1:	SMBDATA			*/
-	PAD_CFG_NF(GPP_C1, UP_20K, DEEP, NF1),
 	/* GPP_C2:	SMBALERT#		*/
 	PAD_NC(GPP_C2, DN_20K),
 	/* GPP_C3:	SML0CLK			*/
diff --git a/src/mainboard/starlabs/starbook/variants/mtl/gpio.c b/src/mainboard/starlabs/starbook/variants/mtl/gpio.c
index efe8de2325..25c3b0bc53 100644
--- a/src/mainboard/starlabs/starbook/variants/mtl/gpio.c
+++ b/src/mainboard/starlabs/starbook/variants/mtl/gpio.c
@@ -8,10 +8,9 @@ const struct pad_config early_gpio_table[] = {
 	PAD_CFG_NF(GPP_H08, NONE, DEEP, NF1),				/* RXD */
 	PAD_CFG_NF(GPP_H09, NONE, DEEP, NF1),				/* TXD */
 
-	/* C00:	SMB_CLK				*/
-	PAD_CFG_NF(GPP_C00, NONE, DEEP, NF1),
-	/* C01:	SMB_DATA			*/
-	PAD_CFG_NF(GPP_C01, NONE, DEEP, NF1),
+	/* SMBus */
+	PAD_CFG_NF(GPP_C00, NONE, DEEP, NF1),				/* Clock */
+	PAD_CFG_NF(GPP_C01, NONE, DEEP, NF1),				/* Data */
 };
 
 const struct pad_config *variant_early_gpio_table(size_t *num)
diff --git a/src/mainboard/starlabs/starbook/variants/rpl/gpio.c b/src/mainboard/starlabs/starbook/variants/rpl/gpio.c
index 042a24d0be..6682a39cd4 100644
--- a/src/mainboard/starlabs/starbook/variants/rpl/gpio.c
+++ b/src/mainboard/starlabs/starbook/variants/rpl/gpio.c
@@ -76,6 +76,11 @@ const struct pad_config gpio_table[] = {
 	/* TPM */
 	PAD_CFG_GPI_APIC_LOW(GPP_E11, NONE, PLTRST),			/* Interrupt */
 
+	/* SMBus */
+	PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1),				/* Clock */
+	PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1),				/* Data */
+	PAD_CFG_GPO(GPP_E8, 1, DEEP),					/* DRAM Sleep */
+
 	/* GPD2:	LAN Wake					*/
 	PAD_NC(GPD2, NONE),
 	/* GPD6:	Sleep A						*/
@@ -168,10 +173,6 @@ const struct pad_config gpio_table[] = {
 	/* B25:		Not Connected					*/
 	PAD_NC(GPP_B25, NONE),
 
-	/* C0:		SMB Clock					*/
-	PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1),
-	/* C1:		SMB Data					*/
-	PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1),
 	/* C2:		TLS Confidentiality	Weak Internal PD 20K
 				Low:	Disabled
 				High:	Enabled				*/
@@ -270,8 +271,6 @@ const struct pad_config gpio_table[] = {
 	PAD_CFG_GPO(GPP_E6, 0, DEEP),
 	/* E7:		Embedded Controller SMI				*/
 	PAD_NC(GPP_E7, NONE),
-	/* E8:		DRAM Sleep					*/
-	PAD_CFG_GPO(GPP_E8, 1, DEEP),
 	/* E9:		USB OverCurrent 0				*/
 	PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1),
 	/* E10:		PWD Amplifier Input				*/
diff --git a/src/mainboard/starlabs/starbook/variants/tgl/gpio.c b/src/mainboard/starlabs/starbook/variants/tgl/gpio.c
index fab78cbafa..f4d4db05b5 100644
--- a/src/mainboard/starlabs/starbook/variants/tgl/gpio.c
+++ b/src/mainboard/starlabs/starbook/variants/tgl/gpio.c
@@ -65,6 +65,10 @@ const struct pad_config gpio_table[] = {
 	/* TPM */
 	PAD_CFG_GPI_APIC_LOW(GPP_C14, NONE, PLTRST),			/* Interrupt */
 
+	/* SMBus */
+	PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1),				/* Clock */
+	PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1),				/* Data */
+
 	/* GPD2:	LAN_WAKE#		*/
 	PAD_NC(GPD2, NONE),
 	/* GPD6:	SIO_SLP_A#		*/
@@ -155,10 +159,6 @@ const struct pad_config gpio_table[] = {
 	/* B23:	CPU_CLKFREQ			*/
 	PAD_CFG_GPO(GPP_B23, 0, DEEP),
 
-	/* C0:	SMBCLK				*/
-	PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1),
-	/* C1:	SMBDATA				*/
-	PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1),
 	/* C2:	SMBALERT_N			*/
 	PAD_CFG_GPO(GPP_C2, 0, DEEP),
 	/* C3:	SML0_CLK			*/
diff --git a/src/mainboard/starlabs/starfighter/variants/rpl/gpio.c b/src/mainboard/starlabs/starfighter/variants/rpl/gpio.c
index 3f26ff7e19..30c13a6fb3 100644
--- a/src/mainboard/starlabs/starfighter/variants/rpl/gpio.c
+++ b/src/mainboard/starlabs/starfighter/variants/rpl/gpio.c
@@ -86,6 +86,11 @@ const struct pad_config gpio_table[] = {
 	/* TPM */
 	PAD_CFG_GPI_APIC_LOW(GPP_D10, NONE, PLTRST),			/* Interrupt */
 
+	/* SMBus */
+	PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1),				/* Clock */
+	PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1),				/* Data */
+	PAD_CFG_GPO(GPP_E8, 1, DEEP),					/* DRAM Sleep */
+
 	/* GPD2:	LAN Wake					*/
 	PAD_NC(GPD2, NONE),
 	/* GPD6:	Sleep A						*/
@@ -175,10 +180,6 @@ const struct pad_config gpio_table[] = {
 	/* B25:		Not Connected					*/
 	PAD_NC(GPP_B25, NONE),
 
-	/* C0:		SMB Clock					*/
-	PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1),
-	/* C1:		SMB Data					*/
-	PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1),
 	/* C2:		TLS Confidentiality	Weak Internal PD 20K
 				Low:	Disabled
 				High:	Enabled				*/
@@ -271,8 +272,6 @@ const struct pad_config gpio_table[] = {
 	PAD_CFG_GPO(GPP_E6, 0, DEEP),
 	/* E7:		Embedded Controller SMI				*/
 	PAD_NC(GPP_E7, NONE),
-	/* E8:		DRAM Sleep					*/
-	PAD_CFG_GPO(GPP_E8, 1, DEEP),
 	/* E9:		USB OverCurrent 0				*/
 	PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1),
 	/* E10:		Not Connected					*/
diff --git a/src/mainboard/starlabs/starlite_adl/variants/mk_v/gpio.c b/src/mainboard/starlabs/starlite_adl/variants/mk_v/gpio.c
index 58e3d12f08..53ebb43f27 100644
--- a/src/mainboard/starlabs/starlite_adl/variants/mk_v/gpio.c
+++ b/src/mainboard/starlabs/starlite_adl/variants/mk_v/gpio.c
@@ -71,6 +71,11 @@ const struct pad_config gpio_table[] = {
 	PAD_CFG_NF(GPP_B1, NONE, DEEP, NF1),				/* Vendor ID 1 */
 	PAD_CFG_GPI_SCI(GPP_B2, NONE, PLTRST, EDGE_SINGLE, INVERT),	/* Processor Hot */
 
+	/* SMBus */
+	PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1),				/* Clock */
+	PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1),				/* Data */
+	PAD_CFG_GPO(GPP_E8, 1, DEEP),					/* DRAM Sleep */
+
 	/* GPD2:	LAN Wake					*/
 	PAD_NC(GPD2, NONE),
 	/* GPD6:	Sleep A						*/
@@ -159,10 +164,6 @@ const struct pad_config gpio_table[] = {
 	/* B25:		Not Connected					*/
 	PAD_NC(GPP_B25, NONE),
 
-	/* C0:		SMB Clock					*/
-	PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1),
-	/* C1:		SMB Data					*/
-	PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1),
 	/* C2:		TLS Confidentiality	Weak Internal PD 20K
 				Low:	Disabled
 				High:	Enabled				*/
@@ -265,8 +266,6 @@ const struct pad_config gpio_table[] = {
 	PAD_CFG_GPO(GPP_E6, 0, DEEP),
 	/* E7:		Embedded Controller SMI				*/
 	PAD_NC(GPP_E7, NONE),
-	/* E8:		DRAM Sleep					*/
-	PAD_CFG_GPO(GPP_E8, 1, DEEP),
 	/* E9:		USB OverCurrent 0				*/
 	PAD_NC(GPP_E9, NONE),
 	/* E10:		PWD Amplifier Input				*/

From ba0a5f14d42ac8fd5da439b1b9c766d703293f8c Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Wed, 2 Apr 2025 14:23:16 +0100
Subject: [PATCH 0599/3886] mb/starlabs/starlite_adl: Tidy GPIO comments for
 the Touchpanel

This is a non-functional change, and only makes the GPIOs easier to read.

Change-Id: If1c102ecf9982dce1bd79175266451ed80da09f3
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87115
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 .../starlabs/starlite_adl/variants/mk_v/gpio.c    | 15 +++++++--------
 1 file changed, 7 insertions(+), 8 deletions(-)

diff --git a/src/mainboard/starlabs/starlite_adl/variants/mk_v/gpio.c b/src/mainboard/starlabs/starlite_adl/variants/mk_v/gpio.c
index 53ebb43f27..8ece4b42ce 100644
--- a/src/mainboard/starlabs/starlite_adl/variants/mk_v/gpio.c
+++ b/src/mainboard/starlabs/starlite_adl/variants/mk_v/gpio.c
@@ -34,6 +34,13 @@ const struct pad_config gpio_table[] = {
 	// PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_A9, UP_20K, DEEP, NF1),	/* eSPI Clk */
 	// PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_A10, NONE, DEEP, NF1),	/* eSPI Reset */
 
+	/* Touchpanel */
+	PAD_CFG_NF(GPP_B5, NONE, DEEP, NF2),				/* Data */
+	PAD_CFG_NF(GPP_B6, NONE, DEEP, NF2),				/* Clock */
+	PAD_CFG_GPI_APIC_LOW(GPP_E12, NONE, PLTRST),			/* Interrupt */
+	PAD_CFG_GPO(GPP_F17, 1, PLTRST),				/* Reset */
+	PAD_CFG_GPI_APIC(GPP_F18, NONE, PLTRST, LEVEL, INVERT),		/* Interrupt */
+
 	/* SSD */
 	PAD_CFG_NF(GPP_D5, NONE, DEEP, NF1),				/* Clock Request 0 */
 	PAD_CFG_GPO(GPP_H0, 1, PLTRST),					/* Reset */
@@ -121,10 +128,6 @@ const struct pad_config gpio_table[] = {
 	PAD_NC(GPP_B3, NONE),
 	/* B4:		Not Connected					*/
 	PAD_NC(GPP_B4, NONE),
-	/* B5:		I2C 2 SDA		Touch Panel SDA		*/
-	PAD_CFG_NF(GPP_B5, NONE, DEEP, NF2),
-	/* B6:		I2C 2 SCL		Touch Panel Clock	*/
-	PAD_CFG_NF(GPP_B6, NONE, DEEP, NF2),
 	/* B7:		I2C 3 SDA		ALS SDA			*/
 	PAD_NC(GPP_B7, NONE),
 	/* B8:		I2C 3 SCL		ALS Clock		*/
@@ -319,10 +322,6 @@ const struct pad_config gpio_table[] = {
 	PAD_CFG_GPI_SMI_LOW(GPP_F15, NONE, DEEP, EDGE_BOTH),
 	/* F16:		Not Connected					*/
 	PAD_NC(GPP_F16, NONE),
-	/* F17:		Touch Panel Reset				*/
-	PAD_CFG_GPO(GPP_F17, 1, PLTRST),
-	/* F18:		Touch Panel Interrupt				*/
-	PAD_CFG_GPI_APIC(GPP_F18, NONE, PLTRST, LEVEL, INVERT),
 	/* F19:		Not Connected					*/
 	PAD_NC(GPP_F19, NONE),
 	/* F20:		Not Connected					*/

From 2c891311608bab1d89e7dc5d747f505dcc0ce8e3 Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Wed, 2 Apr 2025 14:24:58 +0100
Subject: [PATCH 0600/3886] mb/starlabs/starlite_adl: Tidy GPIO comments for
 the Accelerometer

This is a non-functional change, and only makes the GPIOs easier to read.

Change-Id: Id0f00b9b4be06da1d58cfb4491eb7606cc968459
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87116
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/starlabs/starlite_adl/variants/mk_v/gpio.c | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/src/mainboard/starlabs/starlite_adl/variants/mk_v/gpio.c b/src/mainboard/starlabs/starlite_adl/variants/mk_v/gpio.c
index 8ece4b42ce..6705d13de7 100644
--- a/src/mainboard/starlabs/starlite_adl/variants/mk_v/gpio.c
+++ b/src/mainboard/starlabs/starlite_adl/variants/mk_v/gpio.c
@@ -41,6 +41,10 @@ const struct pad_config gpio_table[] = {
 	PAD_CFG_GPO(GPP_F17, 1, PLTRST),				/* Reset */
 	PAD_CFG_GPI_APIC(GPP_F18, NONE, PLTRST, LEVEL, INVERT),		/* Interrupt */
 
+	/* Accelerometer */
+	PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1),				/* Data */
+	PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1),				/* Clock */
+
 	/* SSD */
 	PAD_CFG_NF(GPP_D5, NONE, DEEP, NF1),				/* Clock Request 0 */
 	PAD_CFG_GPO(GPP_H0, 1, PLTRST),					/* Reset */
@@ -339,10 +343,6 @@ const struct pad_config gpio_table[] = {
 	PAD_CFG_GPO(GPP_H2, 1, PLTRST),
 	/* H3:		Not Connected					*/
 	PAD_NC(GPP_H3, NONE),
-	/* H4:		I2C 0 SDA		G Sensor SDA		*/
-	PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1),
-	/* H5:		I2C 0 SCL		G Sensor Clock		*/
-	PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1),
 	/* H6:		I2C 1 SDC		Camera SDA		*/
 	PAD_NC(GPP_H6, NONE),
 	/* H7:		I2C 2 SCL		Camera Clock		*/

From 2b30f4a14b21d55e18400ca4d4f2746df9fdcc12 Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Wed, 2 Apr 2025 14:30:39 +0100
Subject: [PATCH 0601/3886] mb/starlabs/starlite_adl: Reconfigure PCH Strap
 GPIOs

Configure all strap GPIOs as outputs, rather than some being not
connected. This doesn't change anything, but is more explicit.

Set these all to sample on RSMRST.

Change-Id: I0b0eb72c68d2fbe7920db798c2a625d7cc7e8063
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87117
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
---
 .../starlite_adl/variants/mk_v/gpio.c         | 45 ++++++-------------
 1 file changed, 13 insertions(+), 32 deletions(-)

diff --git a/src/mainboard/starlabs/starlite_adl/variants/mk_v/gpio.c b/src/mainboard/starlabs/starlite_adl/variants/mk_v/gpio.c
index 6705d13de7..5025dbf4aa 100644
--- a/src/mainboard/starlabs/starlite_adl/variants/mk_v/gpio.c
+++ b/src/mainboard/starlabs/starlite_adl/variants/mk_v/gpio.c
@@ -87,12 +87,23 @@ const struct pad_config gpio_table[] = {
 	PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1),				/* Data */
 	PAD_CFG_GPO(GPP_E8, 1, DEEP),					/* DRAM Sleep */
 
+	/* Config Straps 									[ Low      / High     ] */
+	PAD_CFG_GPO(GPP_B14, 0, RSMRST),				/* Top Swap		[ Disabled / Enabled  ] */
+	PAD_CFG_GPO(GPP_B18, 0, RSMRST),				/* Reboot Support	[ Enabled  / Disabled ] */
+	PAD_CFG_GPO(GPP_C2, 1, RSMRST),					/* TLS Confidentiality	[ Disabled / Enabled  ] */
+	PAD_CFG_GPO(GPP_C5, 0, RSMRST),					/* eSPI			[ Enabled  / Disabled ] */
+	PAD_CFG_GPO(GPP_E6, 0, RSMRST),					/* JTAG ODT		[ Disabled / Enabled  ] */
+	PAD_CFG_GPO(GPP_H1, 0, RSMRST),					/* BFX Strap 2 Bit 3	[ Disabled / Enabled  ] */
+	PAD_CFG_GPO(GPP_E19, 0, RSMRST),				/* TBT LSX #0		[ 1.8V     / 3.3V     ] */
+	PAD_CFG_GPO(GPP_E21, 0, RSMRST),				/* TBT LSX #1           [ 1.8V     / 3.3V     ] */
+	PAD_CFG_GPO(GPP_D12, 0, RSMRST),				/* TBT LSX #3		[ 1.8V     / 3.3V     ] */
+	PAD_CFG_GPO(GPP_F7, 0, RSMRST),					/* MCRO LDO		[ Disabled / Bypass   ] */
+	PAD_CFG_GPO(GPD7, 0, RSMRST),					/* RTC Clock Delay	[ Disabled / 95ms     ] */
+
 	/* GPD2:	LAN Wake					*/
 	PAD_NC(GPD2, NONE),
 	/* GPD6:	Sleep A						*/
 	PAD_NC(GPD6, NONE),
-	/* GPD7:	Power Adapter Disable				*/
-	PAD_CFG_GPO(GPD7, 0, PWROK),
 	/* GPD9:	Wireless LAN Sleep				*/
 	PAD_NC(GPD9, NONE),
 	/* GPD10:	Sleep S5					*/
@@ -144,18 +155,12 @@ const struct pad_config gpio_table[] = {
 	PAD_NC(GPP_B11, NONE),
 	/* B12:		PM SLP S0					*/
 	PAD_NC(GPP_B12, NONE),
-	/* B14:		Webcam Privacy LED				*/
-	PAD_NC(GPP_B14, NONE),
 	/* B15:		Not Connected					*/
 	PAD_NC(GPP_B15, NONE),
 	/* B16:		I2C 5 SDA		Webcam SDA		*/
 	PAD_NC(GPP_B16, NONE),
 	/* B17:		I2C 5 SDL		Webcam Clock		*/
 	PAD_NC(GPP_B17, NONE),
-	/* B18:		Reboot Support		Weak Internal PD 20K
-				High:	Disabled
-				Low:	Enabled				*/
-	PAD_NC(GPP_B18, NONE),
 	/* B19:		Not Connected					*/
 	PAD_NC(GPP_B19, NONE),
 	/* B20:		Not Connected					*/
@@ -171,18 +176,10 @@ const struct pad_config gpio_table[] = {
 	/* B25:		Not Connected					*/
 	PAD_NC(GPP_B25, NONE),
 
-	/* C2:		TLS Confidentiality	Weak Internal PD 20K
-				Low:	Disabled
-				High:	Enabled				*/
-	PAD_CFG_GPO(GPP_C2, 1, PLTRST),
 	/* C3:		SML 0 Clock					*/
 	PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1),
 	/* C4:		SML 0 Data					*/
 	PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1),
-	/* C5:		Boot Strap		Weak Internal PD 20K
-				Low:	ESPI
-				High:	Disabled			*/
-	PAD_CFG_GPO(GPP_C5, 0, DEEP),
 	/* C6:		SML 1 Clock					*/
 	PAD_CFG_NF(GPP_C6, NONE, DEEP, NF1),
 	/* C7:		SML 1 Data					*/
@@ -242,8 +239,6 @@ const struct pad_config gpio_table[] = {
 	PAD_NC(GPP_D10, NONE),
 	/* D11:		GSPI 2 MISO FPS					*/
 	PAD_NC(GPP_D11, NONE),
-	/* D12:		GSPI 2 MOSI FPS					*/
-	PAD_NC(GPP_D12, NONE),
 	/* D13:		Wireless LAN Wake				*/
 	PAD_NC(GPP_D13, NONE),
 	/* D14:		ALS Interrupt					*/
@@ -267,10 +262,6 @@ const struct pad_config gpio_table[] = {
 	PAD_NC(GPP_E4, NONE),
 	/* E5:		P Out						*/
 	PAD_NC(GPP_E5, NONE),
-	/* E6:		JTAG ODT		No internal PD
-				Low:	Disabled
-				High:	Enabled				*/
-	PAD_CFG_GPO(GPP_E6, 0, DEEP),
 	/* E7:		Embedded Controller SMI				*/
 	PAD_NC(GPP_E7, NONE),
 	/* E9:		USB OverCurrent 0				*/
@@ -291,12 +282,8 @@ const struct pad_config gpio_table[] = {
 	PAD_NC(GPP_E17, NONE),
 	/* E18:		Gyroscope Interrupt				*/
 	PAD_NC(GPP_E18, NONE),
-	/* E19:		Thunderbolt LSX RXD				*/
-	PAD_NC(GPP_E19, NONE),
 	/* E20:		Not Connected					*/
 	PAD_NC(GPP_E20, NONE),
-	/* E21:		Not Connected					*/
-	PAD_NC(GPP_E21, NONE),
 	/* E22:		Not Connected					*/
 	PAD_NC(GPP_E22, NONE),
 	/* E23:		Not Connected					*/
@@ -304,10 +291,6 @@ const struct pad_config gpio_table[] = {
 
 	/* F6:		CNV PA Blanking					*/
 	PAD_NC(GPP_F6, NONE),
-	/* F7:		TBT LSX VCCIO		Weak Internal PD 20K
-				Low:	1.8V
-				High:	3.3V				*/
-	PAD_CFG_GPO(GPP_F7, 0, DEEP),
 	/* F8:		Not Connected					*/
 	PAD_NC(GPP_F8, NONE),
 	/* F9:								*/
@@ -337,8 +320,6 @@ const struct pad_config gpio_table[] = {
 	/* F23:		Not Connected					*/
 	PAD_NC(GPP_F23, NONE),
 
-	/* H1:		BFX Strap 2 Bit 3	Weak Internal PD 20K	*/
-	PAD_CFG_GPO(GPP_H1, 0, DEEP),
 	/* H2:		Wireless LAN Reset				*/
 	PAD_CFG_GPO(GPP_H2, 1, PLTRST),
 	/* H3:		Not Connected					*/

From 3601f213c76db9ceb1b3f46d25d08a4b969989d6 Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Wed, 2 Apr 2025 14:34:51 +0100
Subject: [PATCH 0602/3886] mb/starlabs/starlite_adl: Remove comments for
 disconnected GPIOs

Change-Id: Ifc52668826820a244b346c011f70081b5bc97f12
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87118
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
---
 .../starlite_adl/variants/mk_v/gpio.c         | 141 ------------------
 1 file changed, 141 deletions(-)

diff --git a/src/mainboard/starlabs/starlite_adl/variants/mk_v/gpio.c b/src/mainboard/starlabs/starlite_adl/variants/mk_v/gpio.c
index 5025dbf4aa..dbdd99c475 100644
--- a/src/mainboard/starlabs/starlite_adl/variants/mk_v/gpio.c
+++ b/src/mainboard/starlabs/starlite_adl/variants/mk_v/gpio.c
@@ -100,80 +100,44 @@ const struct pad_config gpio_table[] = {
 	PAD_CFG_GPO(GPP_F7, 0, RSMRST),					/* MCRO LDO		[ Disabled / Bypass   ] */
 	PAD_CFG_GPO(GPD7, 0, RSMRST),					/* RTC Clock Delay	[ Disabled / 95ms     ] */
 
-	/* GPD2:	LAN Wake					*/
 	PAD_NC(GPD2, NONE),
-	/* GPD6:	Sleep A						*/
 	PAD_NC(GPD6, NONE),
-	/* GPD9:	Wireless LAN Sleep				*/
 	PAD_NC(GPD9, NONE),
-	/* GPD10:	Sleep S5					*/
 	PAD_NC(GPD10, NONE),
-	/* GPD11:	LAN PHY Enable					*/
 	PAD_NC(GPD11, NONE),
 
-	/* A5:		Not Connected					*/
 	PAD_NC(GPP_A5, NONE),
-	/* A6:		Not Connected					*/
 	PAD_NC(GPP_A6, NONE),
-	/* A7:		Embedded Controller SCI				*/
 	PAD_NC(GPP_A7, NONE),
-	/* A8:		Not Connected					*/
 	PAD_NC(GPP_A8, NONE),
-	/* A11:		Webcam Camera Reset				*/
 	PAD_NC(GPP_A11, NONE),
-	/* A12:		Not Connected					*/
 	PAD_NC(GPP_A12, NONE),
-	/* A14:		Camera Power Enable				*/
 	PAD_NC(GPP_A14, NONE),
-	/* A15:		Camera Reset					*/
 	PAD_NC(GPP_A15, NONE),
-	/* A16:		USB OverCurrent 3				*/
 	PAD_NC(GPP_A16, NONE),
-	/* A17:		Not Connected					*/
 	PAD_NC(GPP_A17, NONE),
-	/* A21:		Fingerprint Reader Interrupt			*/
 	PAD_NC(GPP_A21, NONE),
-	/* A22:		Fingerprint Reader Reset			*/
 	PAD_NC(GPP_A22, NONE),
-	/* A23:		Not Connected					*/
 	PAD_NC(GPP_A23, NONE),
 
 
-	/* B3:		Not Connected					*/
 	PAD_NC(GPP_B3, NONE),
-	/* B4:		Not Connected					*/
 	PAD_NC(GPP_B4, NONE),
-	/* B7:		I2C 3 SDA		ALS SDA			*/
 	PAD_NC(GPP_B7, NONE),
-	/* B8:		I2C 3 SCL		ALS Clock		*/
 	PAD_NC(GPP_B8, NONE),
-	/* B9:		Not Connected					*/
 	PAD_NC(GPP_B9, NONE),
-	/* B10:		Not Connected					*/
 	PAD_NC(GPP_B10, NONE),
-	/* B11:		I2C PMC PD Interrupt	Test Point 28		*/
 	PAD_NC(GPP_B11, NONE),
-	/* B12:		PM SLP S0					*/
 	PAD_NC(GPP_B12, NONE),
-	/* B15:		Not Connected					*/
 	PAD_NC(GPP_B15, NONE),
-	/* B16:		I2C 5 SDA		Webcam SDA		*/
 	PAD_NC(GPP_B16, NONE),
-	/* B17:		I2C 5 SDL		Webcam Clock		*/
 	PAD_NC(GPP_B17, NONE),
-	/* B19:		Not Connected					*/
 	PAD_NC(GPP_B19, NONE),
-	/* B20:		Not Connected					*/
 	PAD_NC(GPP_B20, NONE),
-	/* B21:		Not Connected					*/
 	PAD_NC(GPP_B21, NONE),
-	/* B22:		Not Connected					*/
 	PAD_NC(GPP_B22, NONE),
-	/* B23:		Front Camera LDO				*/
 	PAD_NC(GPP_B23, NONE),
-	/* B24:		Not Connected					*/
 	PAD_NC(GPP_B24, NONE),
-	/* B25:		Not Connected					*/
 	PAD_NC(GPP_B25, NONE),
 
 	/* C3:		SML 0 Clock					*/
@@ -184,228 +148,123 @@ const struct pad_config gpio_table[] = {
 	PAD_CFG_NF(GPP_C6, NONE, DEEP, NF1),
 	/* C7:		SML 1 Data					*/
 	PAD_CFG_NF(GPP_C7, NONE, DEEP, NF1),
-	/* C8:		Not Connected					*/
 	PAD_NC(GPP_C8, NONE),
-	/* C9:		Not Connected					*/
 	PAD_NC(GPP_C9, NONE),
-	/* C10:		Not Connected					*/
 	PAD_NC(GPP_C10, NONE),
-	/* C11:		Not Connected					*/
 	PAD_NC(GPP_C11, NONE),
-	/* C12:		Not Connected					*/
 	PAD_NC(GPP_C12, NONE),
-	/* C13:		Not Connected					*/
 	PAD_NC(GPP_C13, NONE),
-	/* C14:		Not Connected					*/
 	PAD_NC(GPP_C14, NONE),
-	/* C15:		Not Connected					*/
 	PAD_NC(GPP_C15, NONE),
-	/* C16:		Not Connected					*/
 	PAD_NC(GPP_C16, NONE),
-	/* C17:		Not Connected					*/
 	PAD_NC(GPP_C17, NONE),
-	/* C18:		Not Connected					*/
 	PAD_NC(GPP_C18, NONE),
-	/* C19:		Not Connected					*/
 	PAD_NC(GPP_C19, NONE),
-	/* C20:		Not Connected					*/
 	PAD_NC(GPP_C20, NONE),
-	/* C21:		Not Connected					*/
 	PAD_NC(GPP_C21, NONE),
-	/* C22:		Not Connected					*/
 	PAD_NC(GPP_C22, NONE),
-	/* C23:		Not Connected					*/
 	PAD_NC(GPP_C23, NONE),
 
-	/* D0:		Not used		Audio ID 0		*/
 	PAD_NC(GPP_D0, NONE),
-	/* D1:		Not used		Audio ID 1		*/
 	PAD_NC(GPP_D1, NONE),
-	/* D2:		Not used		Audio ID 2		*/
 	PAD_NC(GPP_D2, NONE),
-	/* D3:		Not Connected					*/
 	PAD_NC(GPP_D3, NONE),
-	/* D4:		Camera Image Clock Output			*/
 	PAD_NC(GPP_D4, NONE),
-	/* D6:		Clock Request 1		Wireless LAN		*/
 	PAD_NC(GPP_D6, NONE),
-	/* D7:		Clock Request 2					*/
 	PAD_NC(GPP_D7, NONE),
-	/* D8:		Clock Request 3					*/
 	PAD_NC(GPP_D8, NONE),
-	/* D9:		GSPI 2 FPS					*/
 	PAD_NC(GPP_D9, NONE),
-	/* D10:		GSPI 2 Clock					*/
 	PAD_NC(GPP_D10, NONE),
-	/* D11:		GSPI 2 MISO FPS					*/
 	PAD_NC(GPP_D11, NONE),
-	/* D13:		Wireless LAN Wake				*/
 	PAD_NC(GPP_D13, NONE),
-	/* D14:		ALS Interrupt					*/
 	PAD_NC(GPP_D14, NONE),
-	/* D15:		Not Connected					*/
 	PAD_NC(GPP_D15, NONE),
-	/* D17:		Not used		Fingerprint ID		*/
 	PAD_NC(GPP_D17, NONE),
-	/* D18:		Bluetooth Wake					*/
 	PAD_NC(GPP_D18, NONE),
-	/* D19:		Test Point 21					*/
 	PAD_NC(GPP_D19, NONE),
 
-	/* E0:		SATA x PCIe					*/
 	PAD_NC(GPP_E0, NONE),
-	/* E1:		Accelerometer Interrupt				*/
 	PAD_NC(GPP_E1, NONE),
-	/* E2:		Not Connected					*/
 	PAD_NC(GPP_E2, NONE),
-	/* E4:		P Offset					*/
 	PAD_NC(GPP_E4, NONE),
-	/* E5:		P Out						*/
 	PAD_NC(GPP_E5, NONE),
-	/* E7:		Embedded Controller SMI				*/
 	PAD_NC(GPP_E7, NONE),
-	/* E9:		USB OverCurrent 0				*/
 	PAD_NC(GPP_E9, NONE),
-	/* E10:		PWD Amplifier Input				*/
 	PAD_NC(GPP_E10, NONE),
-	/* E11:		TPM IRQ						*/
 	PAD_NC(GPP_E11, NONE),
-	/* E12:		Touchpad Interrupt				*/
 	PAD_NC(GPP_E12, NONE),
-	/* E13:		Not connected					*/
 	PAD_NC(GPP_E13, NONE),
-	/* E15:		Webcam Power Enable				*/
 	PAD_NC(GPP_E15, NONE),
-	/* E16:		Not Connected					*/
 	PAD_NC(GPP_E16, NONE),
-	/* E17:		Not Connected					*/
 	PAD_NC(GPP_E17, NONE),
-	/* E18:		Gyroscope Interrupt				*/
 	PAD_NC(GPP_E18, NONE),
-	/* E20:		Not Connected					*/
 	PAD_NC(GPP_E20, NONE),
-	/* E22:		Not Connected					*/
 	PAD_NC(GPP_E22, NONE),
-	/* E23:		Not Connected					*/
 	PAD_NC(GPP_E23, NONE),
 
-	/* F6:		CNV PA Blanking					*/
 	PAD_NC(GPP_F6, NONE),
-	/* F8:		Not Connected					*/
 	PAD_NC(GPP_F8, NONE),
-	/* F9:								*/
 	PAD_NC(GPP_F9, NONE),
 	/* F10:		Weak Internal PD 20K				*/
 	PAD_CFG_GPO(GPP_F10, 0, DEEP),
-	/* F11:		TPM ID						*/
 	PAD_NC(GPP_F11, NONE),
-	/* F12:		Not Connected					*/
 	PAD_NC(GPP_F12, NONE),
-	/* F13:		Not Connected					*/
 	PAD_NC(GPP_F13, NONE),
-	/* F14:		Not Connected					*/
 	PAD_NC(GPP_F14, NONE),
 	/* F15:		Keyboard Detect					*/
 	PAD_CFG_GPI_SMI_LOW(GPP_F15, NONE, DEEP, EDGE_BOTH),
-	/* F16:		Not Connected					*/
 	PAD_NC(GPP_F16, NONE),
-	/* F19:		Not Connected					*/
 	PAD_NC(GPP_F19, NONE),
-	/* F20:		Not Connected					*/
 	PAD_NC(GPP_F20, NONE),
-	/* F21:		Not Connected					*/
 	PAD_NC(GPP_F21, NONE),
-	/* F22:		Not Connected					*/
 	PAD_NC(GPP_F22, NONE),
-	/* F23:		Not Connected					*/
 	PAD_NC(GPP_F23, NONE),
 
 	/* H2:		Wireless LAN Reset				*/
 	PAD_CFG_GPO(GPP_H2, 1, PLTRST),
-	/* H3:		Not Connected					*/
 	PAD_NC(GPP_H3, NONE),
-	/* H6:		I2C 1 SDC		Camera SDA		*/
 	PAD_NC(GPP_H6, NONE),
-	/* H7:		I2C 2 SCL		Camera Clock		*/
 	PAD_NC(GPP_H7, NONE),
-	/* H8:		Not Connected					*/
 	PAD_NC(GPP_H8, NONE),
-	/* H9:		Camera LDO Enable				*/
 	PAD_NC(GPP_H9, NONE),
-	/* H12:		Not Connected					*/
 	PAD_NC(GPP_H12, NONE),
-	/* H13:		PCH M.2 SSD Device Sleep			*/
 	PAD_NC(GPP_H13, NONE),
-	/* H14:		Not Connected					*/
 	PAD_NC(GPP_H14, NONE),
-	/* H16:		Not Connected					*/
 	PAD_NC(GPP_H16, NONE),
-	/* H19:		Clock Request 4					*/
 	PAD_NC(GPP_H19, NONE),
-	/* H20:		Webcam Clock					*/
 	PAD_NC(GPP_H20, NONE),
-	/* H21:		Not Connected					*/
 	PAD_NC(GPP_H21, NONE),
-	/* H22:		Not Connected					*/
 	PAD_NC(GPP_H22, NONE),
-	/* H23:		MIPI Camera Power Enable			*/
 	PAD_NC(GPP_H23, NONE),
 
-	/* S0:		Not Connected					*/
 	PAD_NC(GPP_S0, NONE),
-	/* S1:		Not Connected					*/
 	PAD_NC(GPP_S1, NONE),
-	/* S2:		DMIC Clock					*/
 	PAD_NC(GPP_S2, NONE),
-	/* S3:		DMIC Data					*/
 	PAD_NC(GPP_S3, NONE),
-	/* S4:		Not Connected					*/
 	PAD_NC(GPP_S4, NONE),
-	/* S5:		Not Connected					*/
 	PAD_NC(GPP_S5, NONE),
-	/* S6:		Not Connected					*/
 	PAD_NC(GPP_S6, NONE),
-	/* S7:		Not Connected					*/
 	PAD_NC(GPP_S7, NONE),
 
-	/* T0:		 Not Connected					*/
 	PAD_NC(GPP_T0, NONE),
-	/* T1:		 Not Connected					*/
 	PAD_NC(GPP_T1, NONE),
-	/* T2:		 Not Connected					*/
 	PAD_NC(GPP_T2, NONE),
-	/* T3:		 Not Connected					*/
 	PAD_NC(GPP_T3, NONE),
-	/* T4:		 Not Connected					*/
 	PAD_NC(GPP_T4, NONE),
-	/* T5:		 Not Connected					*/
 	PAD_NC(GPP_T5, NONE),
-	/* T6:		 Not Connected					*/
 	PAD_NC(GPP_T6, NONE),
-	/* T7:		 Not Connected					*/
 	PAD_NC(GPP_T7, NONE),
-	/* T8:		 Not Connected					*/
 	PAD_NC(GPP_T8, NONE),
-	/* T9:		 Not Connected					*/
 	PAD_NC(GPP_T9, NONE),
-	/* T10:		 Not Connected					*/
 	PAD_NC(GPP_T10, NONE),
-	/* T11:		 Not Connected					*/
 	PAD_NC(GPP_T11, NONE),
-	/* T12:		 Not Connected					*/
 	PAD_NC(GPP_T12, NONE),
-	/* T13:		 Not Connected					*/
 	PAD_NC(GPP_T13, NONE),
-	/* T14:		 Not Connected					*/
 	PAD_NC(GPP_T14, NONE),
-	/* T15:		 Not Connected					*/
 	PAD_NC(GPP_T15, NONE),
 
-	/* R5:		Not Connected					*/
 	PAD_NC(GPP_R5, NONE),
-	/* R6:		Not Connected					*/
 	PAD_NC(GPP_R6, NONE),
-	/* R7:		Not Connected					*/
 	PAD_NC(GPP_R7, NONE),
 };
 

From 8093d0e482c84485b7cfec688831462f60dbf9cf Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Wed, 2 Apr 2025 14:35:39 +0100
Subject: [PATCH 0603/3886] mb/starlabs/starlite_adl: Disconnect WiFi Reset
 GPIO

This GPIO is only used for full PCI wireless, and these boards use
CNVi so disconnect it.

Change-Id: Ie7be00543b5c99814204265157eeab654492724f
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87119
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/starlabs/starlite_adl/variants/mk_v/gpio.c | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/src/mainboard/starlabs/starlite_adl/variants/mk_v/gpio.c b/src/mainboard/starlabs/starlite_adl/variants/mk_v/gpio.c
index dbdd99c475..7bb2c7fbb7 100644
--- a/src/mainboard/starlabs/starlite_adl/variants/mk_v/gpio.c
+++ b/src/mainboard/starlabs/starlite_adl/variants/mk_v/gpio.c
@@ -220,8 +220,7 @@ const struct pad_config gpio_table[] = {
 	PAD_NC(GPP_F22, NONE),
 	PAD_NC(GPP_F23, NONE),
 
-	/* H2:		Wireless LAN Reset				*/
-	PAD_CFG_GPO(GPP_H2, 1, PLTRST),
+	PAD_NC(GPP_H2, NONE),
 	PAD_NC(GPP_H3, NONE),
 	PAD_NC(GPP_H6, NONE),
 	PAD_NC(GPP_H7, NONE),

From 28f1c5ad8092a43683235217939c1457546cef65 Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Wed, 2 Apr 2025 14:37:31 +0100
Subject: [PATCH 0604/3886] mb/starlabs/starlite_adl: Disconnect the SML 0 and
 1 GPIOs

These are not connected to anything, so configure them accordingly.

Change-Id: Ia3a528faf74c23d0b78210b22c6e8d3f69de8184
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87120
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
---
 .../starlabs/starlite_adl/variants/mk_v/gpio.c       | 12 ++++--------
 1 file changed, 4 insertions(+), 8 deletions(-)

diff --git a/src/mainboard/starlabs/starlite_adl/variants/mk_v/gpio.c b/src/mainboard/starlabs/starlite_adl/variants/mk_v/gpio.c
index 7bb2c7fbb7..75c1d43e76 100644
--- a/src/mainboard/starlabs/starlite_adl/variants/mk_v/gpio.c
+++ b/src/mainboard/starlabs/starlite_adl/variants/mk_v/gpio.c
@@ -140,14 +140,10 @@ const struct pad_config gpio_table[] = {
 	PAD_NC(GPP_B24, NONE),
 	PAD_NC(GPP_B25, NONE),
 
-	/* C3:		SML 0 Clock					*/
-	PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1),
-	/* C4:		SML 0 Data					*/
-	PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1),
-	/* C6:		SML 1 Clock					*/
-	PAD_CFG_NF(GPP_C6, NONE, DEEP, NF1),
-	/* C7:		SML 1 Data					*/
-	PAD_CFG_NF(GPP_C7, NONE, DEEP, NF1),
+	PAD_NC(GPP_C3, NONE),
+	PAD_NC(GPP_C4, NONE),
+	PAD_NC(GPP_C6, NONE),
+	PAD_NC(GPP_C7, NONE),
 	PAD_NC(GPP_C8, NONE),
 	PAD_NC(GPP_C9, NONE),
 	PAD_NC(GPP_C10, NONE),

From a1bd7900579e3b9d470a286d5ce2f0c3fbf8753d Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Wed, 2 Apr 2025 14:38:15 +0100
Subject: [PATCH 0605/3886] mb/starlabs/starlite_adl: Disconnect unused GPIO

GPP_F10 is not connected, so configure it accordingly.

Change-Id: I5a8fb34837b1b3f2f066ccc260f0ab749d7782c0
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87121
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/starlabs/starlite_adl/variants/mk_v/gpio.c | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/src/mainboard/starlabs/starlite_adl/variants/mk_v/gpio.c b/src/mainboard/starlabs/starlite_adl/variants/mk_v/gpio.c
index 75c1d43e76..dcac519872 100644
--- a/src/mainboard/starlabs/starlite_adl/variants/mk_v/gpio.c
+++ b/src/mainboard/starlabs/starlite_adl/variants/mk_v/gpio.c
@@ -201,8 +201,7 @@ const struct pad_config gpio_table[] = {
 	PAD_NC(GPP_F6, NONE),
 	PAD_NC(GPP_F8, NONE),
 	PAD_NC(GPP_F9, NONE),
-	/* F10:		Weak Internal PD 20K				*/
-	PAD_CFG_GPO(GPP_F10, 0, DEEP),
+	PAD_NC(GPP_F10, NONE),
 	PAD_NC(GPP_F11, NONE),
 	PAD_NC(GPP_F12, NONE),
 	PAD_NC(GPP_F13, NONE),

From a2d5efeb1e1e94fdfea5ec3d77f006c0735c1f0c Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Wed, 2 Apr 2025 14:39:24 +0100
Subject: [PATCH 0606/3886] mb/starlabs/starlite_adl: Tidy GPIO comments for
 the Keyboard

This is a non-functional change, and only makes the GPIOs easier to read.

Change-Id: Icfb80295ba0c55184b174a63756e8779111d9b76
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87122
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/starlabs/starlite_adl/variants/mk_v/gpio.c | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/src/mainboard/starlabs/starlite_adl/variants/mk_v/gpio.c b/src/mainboard/starlabs/starlite_adl/variants/mk_v/gpio.c
index dcac519872..bd22c927ce 100644
--- a/src/mainboard/starlabs/starlite_adl/variants/mk_v/gpio.c
+++ b/src/mainboard/starlabs/starlite_adl/variants/mk_v/gpio.c
@@ -45,6 +45,9 @@ const struct pad_config gpio_table[] = {
 	PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1),				/* Data */
 	PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1),				/* Clock */
 
+	/* Keyboard */
+	PAD_CFG_GPI_SMI_LOW(GPP_F15, NONE, DEEP, EDGE_BOTH),		/* Detect */
+
 	/* SSD */
 	PAD_CFG_NF(GPP_D5, NONE, DEEP, NF1),				/* Clock Request 0 */
 	PAD_CFG_GPO(GPP_H0, 1, PLTRST),					/* Reset */
@@ -206,8 +209,6 @@ const struct pad_config gpio_table[] = {
 	PAD_NC(GPP_F12, NONE),
 	PAD_NC(GPP_F13, NONE),
 	PAD_NC(GPP_F14, NONE),
-	/* F15:		Keyboard Detect					*/
-	PAD_CFG_GPI_SMI_LOW(GPP_F15, NONE, DEEP, EDGE_BOTH),
 	PAD_NC(GPP_F16, NONE),
 	PAD_NC(GPP_F19, NONE),
 	PAD_NC(GPP_F20, NONE),

From 6f01685f5d7293407452e31f8829636a29ecd1d4 Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Wed, 2 Apr 2025 10:12:02 +0100
Subject: [PATCH 0607/3886] mb/starlabs/byte_adl: Remove the override verb
 function

This board does not have a DMIC, so don't try to disable.

Change-Id: Ic47f9c3b40dd76a78325b024ba8f93a117f7d031
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87095
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/starlabs/byte_adl/Makefile.mk |  1 -
 src/mainboard/starlabs/byte_adl/hda_verb.c  | 26 ---------------------
 2 files changed, 27 deletions(-)
 delete mode 100644 src/mainboard/starlabs/byte_adl/hda_verb.c

diff --git a/src/mainboard/starlabs/byte_adl/Makefile.mk b/src/mainboard/starlabs/byte_adl/Makefile.mk
index 84b693e702..677db61b19 100644
--- a/src/mainboard/starlabs/byte_adl/Makefile.mk
+++ b/src/mainboard/starlabs/byte_adl/Makefile.mk
@@ -10,6 +10,5 @@ verstage-$(CONFIG_VBOOT) += vboot.c
 romstage-$(CONFIG_VBOOT) += vboot.c
 
 ramstage-$(CONFIG_DRIVERS_OPTION_CFR) += cfr.c
-ramstage-y += hda_verb.c
 ramstage-y += mainboard.c
 ramstage-y += smbios.c
diff --git a/src/mainboard/starlabs/byte_adl/hda_verb.c b/src/mainboard/starlabs/byte_adl/hda_verb.c
deleted file mode 100644
index ca69ef9f7d..0000000000
--- a/src/mainboard/starlabs/byte_adl/hda_verb.c
+++ /dev/null
@@ -1,26 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <console/console.h>
-#include <device/azalia_device.h>
-#include <option.h>
-#include <types.h>
-
-#define AZALIA_CODEC_SN6140	0x14f11f87
-
-static const u32 override_verb[] = {
-	AZALIA_PIN_CFG(0, 0x1a, 0x00000000),
-};
-
-static void disable_microphone(u8 *base)
-{
-	azalia_program_verb_table(base, override_verb, ARRAY_SIZE(override_verb));
-}
-
-void mainboard_azalia_program_runtime_verbs(u8 *base, u32 viddid)
-{
-	if (viddid == AZALIA_CODEC_SN6140) {
-		printk(BIOS_DEBUG, "CMOS: viddid = %08x\n", viddid);
-		if (get_uint_option("microphone", 1) == 0)
-			disable_microphone(base);
-	}
-}

From 504cfaa41bcc0bba7af64f0ca99c410404e85354 Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Tue, 1 Apr 2025 09:06:41 +0100
Subject: [PATCH 0608/3886] mb/starlabs/starbook/mtl: Show the option to enable
 the GNA

Change-Id: I568cb169f5266703e4422d77c0e0546a6d245ee2
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87055
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
---
 src/mainboard/starlabs/starbook/cfr.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/mainboard/starlabs/starbook/cfr.c b/src/mainboard/starlabs/starbook/cfr.c
index ac34906656..33d4b64727 100644
--- a/src/mainboard/starlabs/starbook/cfr.c
+++ b/src/mainboard/starlabs/starbook/cfr.c
@@ -55,7 +55,7 @@ static const struct sm_object fingerprint_reader = SM_DECLARE_BOOL({
 });
 #endif
 
-#if CONFIG(SOC_INTEL_TIGERLAKE) || CONFIG(SOC_INTEL_ALDERLAKE) || CONFIG(SOC_INTEL_RAPTORLAKE)
+#if CONFIG(SOC_INTEL_TIGERLAKE) || CONFIG(SOC_INTEL_ALDERLAKE) || CONFIG(SOC_INTEL_RAPTORLAKE) || CONFIG(SOC_INTEL_METEORLAKE)
 static const struct sm_object gna = SM_DECLARE_BOOL({
 	.opt_name	= "gna",
 	.ui_name	= "Gaussian & Neural Accelerator",
@@ -265,7 +265,7 @@ static struct sm_obj_form devices = {
 		#if CONFIG(BOARD_STARLABS_STARBOOK_ADL) || CONFIG(BOARD_STARLABS_STARBOOK_RPL)
 		&fingerprint_reader,
 		#endif
-		#if CONFIG(SOC_INTEL_TIGERLAKE) || CONFIG(SOC_INTEL_ALDERLAKE) || CONFIG(SOC_INTEL_RAPTORLAKE)
+		#if CONFIG(SOC_INTEL_TIGERLAKE) || CONFIG(SOC_INTEL_ALDERLAKE) || CONFIG(SOC_INTEL_RAPTORLAKE) || CONFIG(SOC_INTEL_METEORLAKE)
 		&gna,
 		#endif
 		#if CONFIG(EC_STARLABS_LID_SWITCH)

From 4c967ea16748a8bb207ccdc8644b4a87a2e672bc Mon Sep 17 00:00:00 2001
From: Vince Liu <vince-wl.liu@mediatek.corp-partner.google.com>
Date: Tue, 10 Dec 2024 15:32:15 +0800
Subject: [PATCH 0609/3886] soc/mediatek/mt8189: Add NOR-Flash support

Add NOR-Flash drivers for flash read/write.

BUG=b:379008996
BRANCH=none
TEST=Read NOR flash data successfully.

Signed-off-by: Noah Shen <noah.shen@mediatek.corp-partner.google.com>
Change-Id: I3a5b7682e4093f9eddf825bc57267b0180cf8b3c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86997
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/soc/mediatek/mt8189/Kconfig           |  1 +
 src/soc/mediatek/mt8189/Makefile.mk       |  1 +
 src/soc/mediatek/mt8189/include/soc/spi.h |  5 +++--
 src/soc/mediatek/mt8189/spi.c             | 21 +++++++++++++++++++--
 4 files changed, 24 insertions(+), 4 deletions(-)

diff --git a/src/soc/mediatek/mt8189/Kconfig b/src/soc/mediatek/mt8189/Kconfig
index d0395c29cd..512ae54d9e 100644
--- a/src/soc/mediatek/mt8189/Kconfig
+++ b/src/soc/mediatek/mt8189/Kconfig
@@ -9,6 +9,7 @@ config SOC_MEDIATEK_MT8189
 	select ARCH_RAMSTAGE_ARMV8_64
 	select HAVE_UART_SPECIAL
 	select SOC_MEDIATEK_COMMON
+	select FLASH_DUAL_IO_READ
 	select ARM64_USE_ARCH_TIMER
 
 if SOC_MEDIATEK_MT8189
diff --git a/src/soc/mediatek/mt8189/Makefile.mk b/src/soc/mediatek/mt8189/Makefile.mk
index a121413cc1..00489c02a4 100644
--- a/src/soc/mediatek/mt8189/Makefile.mk
+++ b/src/soc/mediatek/mt8189/Makefile.mk
@@ -2,6 +2,7 @@
 
 ifeq ($(CONFIG_SOC_MEDIATEK_MT8189),y)
 
+all-y += ../common/flash_controller.c
 all-y += ../common/gpio.c ../common/gpio_op.c gpio.c
 all-$(CONFIG_SPI_FLASH) += spi.c
 all-y += ../common/timer_prepare.c timer.c
diff --git a/src/soc/mediatek/mt8189/include/soc/spi.h b/src/soc/mediatek/mt8189/include/soc/spi.h
index 8c66e4a882..01e866bbd7 100644
--- a/src/soc/mediatek/mt8189/include/soc/spi.h
+++ b/src/soc/mediatek/mt8189/include/soc/spi.h
@@ -8,6 +8,7 @@
 #ifndef __SOC_MEDIATEK_MT8189_INCLUDE_SOC_SPI_H__
 #define __SOC_MEDIATEK_MT8189_INCLUDE_SOC_SPI_H__
 
-#include <spi-generic.h>
+/* Initialize SPI NOR Flash Controller */
+void mtk_snfc_init(void);
 
-#endif /* __SOC_MEDIATEK_MT8189_INCLUDE_SOC_SPI_H__ */
+#endif
diff --git a/src/soc/mediatek/mt8189/spi.c b/src/soc/mediatek/mt8189/spi.c
index da40fc57a5..410b53eb8a 100644
--- a/src/soc/mediatek/mt8189/spi.c
+++ b/src/soc/mediatek/mt8189/spi.c
@@ -5,17 +5,34 @@
  * Chapter number: 9.17
  */
 
-#include <device/mmio.h>
-#include <soc/addressmap.h>
+#include <gpio.h>
+#include <soc/flash_controller_common.h>
 #include <soc/spi.h>
+#include <spi_flash.h>
+
+static const struct pad_func nor_pinmux[4] = {
+	PAD_FUNC(SPINOR_CK, SPINOR_CK, GPIO_PULL_DOWN),
+	PAD_FUNC(SPINOR_CS, SPINOR_CS, GPIO_PULL_UP),
+	PAD_FUNC(SPINOR_IO0, SPINOR_IO0, GPIO_PULL_DOWN),
+	PAD_FUNC(SPINOR_IO1, SPINOR_IO1, GPIO_PULL_DOWN),
+};
+
+void mtk_snfc_init(void)
+{
+	for (size_t i = 0; i < ARRAY_SIZE(nor_pinmux); i++)
+		mtk_snfc_init_pad_func(&nor_pinmux[i], GPIO_DRV_8_MA);
+}
 
 static const struct spi_ctrlr spi_flash_ctrlr = {
 	.max_xfer_size = 65535,
+	.flash_probe = mtk_spi_flash_probe,
 };
 
 const struct spi_ctrlr_buses spi_ctrlr_bus_map[] = {
 	{
 		.ctrlr = &spi_flash_ctrlr,
+		.bus_start = CONFIG_BOOT_DEVICE_SPI_FLASH_BUS,
+		.bus_end = CONFIG_BOOT_DEVICE_SPI_FLASH_BUS,
 	},
 };
 

From 40717046ea15c203c724229afd64e6e7a7af927c Mon Sep 17 00:00:00 2001
From: Vince Liu <vince-wl.liu@mediatek.corp-partner.google.com>
Date: Tue, 10 Dec 2024 15:32:47 +0800
Subject: [PATCH 0610/3886] mb/google/skywalker: Initialize flash controller in
 bootblock

Initialize SPI NOR Flash Controller (SNFC) in the bootblock to
enable CBFS and execute other stages such as verstage, romstage,
ramstage, etc.

BUG=b:379008996
BRANCH=none
TEST=Read NOR flash data successfully.

Signed-off-by: Noah Shen <noah.shen@mediatek.corp-partner.google.com>
Change-Id: Icf4af32dd9d8c704fd7246adda94dfa3350bb672
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86998
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
---
 src/mainboard/google/skywalker/Kconfig     | 4 ++++
 src/mainboard/google/skywalker/bootblock.c | 3 ++-
 2 files changed, 6 insertions(+), 1 deletion(-)

diff --git a/src/mainboard/google/skywalker/Kconfig b/src/mainboard/google/skywalker/Kconfig
index a3bed903b2..b3da5482b2 100644
--- a/src/mainboard/google/skywalker/Kconfig
+++ b/src/mainboard/google/skywalker/Kconfig
@@ -27,4 +27,8 @@ config MAINBOARD_DIR
 config MAINBOARD_PART_NUMBER
 	string
 	default "Skywalker" if BOARD_GOOGLE_SKYWALKER
+
+config BOOT_DEVICE_SPI_FLASH_BUS
+	int
+	default 7
 endif
diff --git a/src/mainboard/google/skywalker/bootblock.c b/src/mainboard/google/skywalker/bootblock.c
index af9934e07e..1062d9bbe5 100644
--- a/src/mainboard/google/skywalker/bootblock.c
+++ b/src/mainboard/google/skywalker/bootblock.c
@@ -1,8 +1,9 @@
 /* SPDX-License-Identifier: GPL-2.0-only OR MIT */
 
 #include <bootblock_common.h>
+#include <soc/spi.h>
 
 void bootblock_mainboard_init(void)
 {
-	/* TODO: add mainboard init for bootblock */
+	mtk_snfc_init();
 }

From f485c69d18f3f2bc6df0fa6f695d0506a03d8da2 Mon Sep 17 00:00:00 2001
From: Liu Liu <ot_liu.liu@mediatek.corp-partner.google.com>
Date: Tue, 10 Dec 2024 17:10:53 +0800
Subject: [PATCH 0611/3886] soc/mediatek/mt8189: Add USB host support

Correct XHCI and PHY register addresses and enable USB port 3 VBUS
to support USB host functionality.

BUG=b:379008996
BRANCH=none
TEST=build pass

Signed-off-by: Liu Liu <ot_liu.liu@mediatek.corp-partner.google.com>
Change-Id: I5f1b4b3eb178cb9a110b97a2763c8cff5cdf0ddd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87021
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/soc/mediatek/mt8189/Makefile.mk           |  1 +
 .../mediatek/mt8189/include/soc/addressmap.h  |  4 +--
 src/soc/mediatek/mt8189/include/soc/usb.h     | 29 +++++++++++++++++++
 src/soc/mediatek/mt8189/usb.c                 | 17 +++++++++++
 4 files changed, 49 insertions(+), 2 deletions(-)
 create mode 100644 src/soc/mediatek/mt8189/include/soc/usb.h
 create mode 100644 src/soc/mediatek/mt8189/usb.c

diff --git a/src/soc/mediatek/mt8189/Makefile.mk b/src/soc/mediatek/mt8189/Makefile.mk
index 00489c02a4..6774f52cde 100644
--- a/src/soc/mediatek/mt8189/Makefile.mk
+++ b/src/soc/mediatek/mt8189/Makefile.mk
@@ -17,6 +17,7 @@ romstage-y += emi.c
 
 ramstage-y += emi.c
 ramstage-y += soc.c
+ramstage-y += ../common/usb.c usb.c
 
 CPPFLAGS_common += -Isrc/soc/mediatek/mt8189/include
 CPPFLAGS_common += -Isrc/soc/mediatek/common/include
diff --git a/src/soc/mediatek/mt8189/include/soc/addressmap.h b/src/soc/mediatek/mt8189/include/soc/addressmap.h
index c0c78b1879..5d997283d0 100644
--- a/src/soc/mediatek/mt8189/include/soc/addressmap.h
+++ b/src/soc/mediatek/mt8189/include/soc/addressmap.h
@@ -30,8 +30,9 @@ enum {
 	SFLASH_REG_BASE			= IO_PHYS + 0x01018000,
 	PERICFG_AO_BASE			= IO_PHYS + 0x01036000,
 	DEVAPC_PERI_PAR_AO_BASE		= IO_PHYS + 0x0103C000,
-	SSUSB_IPPC_BASE			= IO_PHYS + 0x01203E00,
+	SSUSB_IPPC_BASE			= IO_PHYS + 0x01263E00,
 	UFSHCI_BASE			= IO_PHYS + 0x012B0000,
+	SSUSB_SIF_BASE			= IO_PHYS + 0x01B00300,
 	MIPITX0_BASE			= IO_PHYS + 0x01B40000,
 	IOCFG_LM_BASE			= IO_PHYS + 0x01B50000,
 	EDP_BASE			= IO_PHYS + 0x01B70000,
@@ -42,7 +43,6 @@ enum {
 	IOCFG_BM2_BASE			= IO_PHYS + 0x01D40000,
 	IOCFG_LT0_BASE			= IO_PHYS + 0x01E20000,
 	IOCFG_LT1_BASE			= IO_PHYS + 0x01E30000,
-	SSUSB_SIF_BASE			= IO_PHYS + 0x01E80300,
 	IOCFG_RT_BASE			= IO_PHYS + 0x01F20000,
 	DSI0_BASE			= IO_PHYS + 0x04016000,
 	DISP_DVO0			= IO_PHYS + 0x04019000,
diff --git a/src/soc/mediatek/mt8189/include/soc/usb.h b/src/soc/mediatek/mt8189/include/soc/usb.h
new file mode 100644
index 0000000000..eba4d62dd4
--- /dev/null
+++ b/src/soc/mediatek/mt8189/include/soc/usb.h
@@ -0,0 +1,29 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+/*
+ * This file is created based on MT8189 Functional Specification
+ * Chapter number: 9.5
+ */
+
+#ifndef SOC_MEDIATEK_MT8189_INCLUDE_SOC_USB_H
+#define SOC_MEDIATEK_MT8189_INCLUDE_SOC_USB_H
+
+#include <soc/usb_common.h>
+
+struct ssusb_sif_port {
+	struct sif_u2_phy_com u2phy;
+	u32 reserved0[64 * 5];
+	struct sif_u3phyd u3phyd;
+	u32 reserved1[64];
+	struct sif_u3phya u3phya;
+	struct sif_u3phya_da u3phya_da;
+	u32 reserved2[64 * 3];
+};
+check_member(ssusb_sif_port, u3phyd, 0x600);
+check_member(ssusb_sif_port, u3phya, 0x800);
+check_member(ssusb_sif_port, u3phya_da, 0x900);
+check_member(ssusb_sif_port, reserved2, 0xa00);
+
+#define USB_PORT_NUMBER		1
+
+#endif
diff --git a/src/soc/mediatek/mt8189/usb.c b/src/soc/mediatek/mt8189/usb.c
new file mode 100644
index 0000000000..4dde3dea3c
--- /dev/null
+++ b/src/soc/mediatek/mt8189/usb.c
@@ -0,0 +1,17 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+/*
+ * This file is created based on MT8189 Functional Specification
+ * Chapter number: 9.5
+ */
+
+#include <device/mmio.h>
+#include <gpio.h>
+#include <soc/pll_common.h>
+#include <soc/usb.h>
+
+void mtk_usb_prepare(void)
+{
+	/* enable P3 VBUS */
+	gpio_output(GPIO(USB3_DRV_VBUS), 1);
+}

From 0ac2058dbee67f5d2a4039395d38ce7d238fbfa5 Mon Sep 17 00:00:00 2001
From: Subrata Banik <subratabanik@google.com>
Date: Wed, 2 Apr 2025 08:07:56 +0530
Subject: [PATCH 0612/3886] mb/google/fatcat: Increase sagv_freq_mhz for work
 point #1 to #3

Update the SaGV frequency registers
- (`sagv_freq_mhz[1]`) in the devicetree from "3200" to "4800".
- (`sagv_freq_mhz[2]`) in the devicetree from "6000" to "6400".
- (`sagv_freq_mhz[3]`) in the devicetree from "6400" to "6800".

This change likely to improve the device performance.

BUG=b:328770565, b:407862619
TEST=Able to reduce the boot time by 18ms.

Change-Id: Id0b25adeed4b3f3e1c37d17901006a2db2d21223
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87087
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Bora Guvendik <bora.guvendik@intel.corp-partner.google.com>
Reviewed-by: Pranava Y N <pranavayn@google.com>
---
 .../google/fatcat/variants/baseboard/fatcat/devicetree.cb   | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/src/mainboard/google/fatcat/variants/baseboard/fatcat/devicetree.cb b/src/mainboard/google/fatcat/variants/baseboard/fatcat/devicetree.cb
index aa297b1a91..6f04713ae3 100644
--- a/src/mainboard/google/fatcat/variants/baseboard/fatcat/devicetree.cb
+++ b/src/mainboard/google/fatcat/variants/baseboard/fatcat/devicetree.cb
@@ -36,13 +36,13 @@ chip soc/intel/pantherlake
 	register "sagv_freq_mhz[0]" = "2400"
 	register "sagv_gear[0]" = "GEAR_4"
 
-	register "sagv_freq_mhz[1]" = "3200"
+	register "sagv_freq_mhz[1]" = "4800"
 	register "sagv_gear[1]" = "GEAR_4"
 
-	register "sagv_freq_mhz[2]" = "6000"
+	register "sagv_freq_mhz[2]" = "6400"
 	register "sagv_gear[2]" = "GEAR_4"
 
-	register "sagv_freq_mhz[3]" = "6400"
+	register "sagv_freq_mhz[3]" = "6800"
 	register "sagv_gear[3]" = "GEAR_4"
 
 	# Enable s0ix

From 584f9bcc3f96565c92bb4a6513a90da4fb56fb66 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Bart=C5=82omiej=20Grzesik?= <bgrzesik@google.com>
Date: Tue, 21 Jan 2025 17:02:39 +0100
Subject: [PATCH 0613/3886] Add allocation of a buffer for pvmfw within cbmem
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Add an allocation of an empty buffer for the Android protected virtual
machine firmware within cbmem. The buffer will be filled by the payload
and the purpose is to just reserve the memory. cbmem is used to make
sure that the region won't overlap with other reserved regions
or device regions.

BUG=b:354045389
BUG=b:359340876
TEST=depthcharge receives the buffer through lib_sysinfo
BRANCH=main

Change-Id: I48efc033ac0f5fbfcf3a52fabf40be016cd4c6f7
Signed-off-by: Bartłomiej Grzesik <bgrzesik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87107
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jakub "Kuba" Czapiga <czapiga@google.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
---
 payloads/libpayload/include/sysinfo.h           |  4 ++++
 payloads/libpayload/libc/coreboot.c             |  4 ++++
 .../bsd/include/commonlib/bsd/cbmem_id.h        |  4 +++-
 src/vendorcode/google/Kconfig                   | 15 +++++++++++++++
 src/vendorcode/google/Makefile.mk               |  1 +
 src/vendorcode/google/pvmfw_cbmem.c             | 17 +++++++++++++++++
 6 files changed, 44 insertions(+), 1 deletion(-)
 create mode 100644 src/vendorcode/google/pvmfw_cbmem.c

diff --git a/payloads/libpayload/include/sysinfo.h b/payloads/libpayload/include/sysinfo.h
index cbfc7bf91b..2eb0da32dd 100644
--- a/payloads/libpayload/include/sysinfo.h
+++ b/payloads/libpayload/include/sysinfo.h
@@ -162,6 +162,10 @@ struct sysinfo_t {
 	uint32_t cbfs_ro_mcache_size;
 	uintptr_t cbfs_rw_mcache_offset;
 	uint32_t cbfs_rw_mcache_size;
+
+	/* pvmfw buffer location */
+	uintptr_t pvmfw;
+	uint32_t pvmfw_size;
 };
 
 extern struct sysinfo_t lib_sysinfo;
diff --git a/payloads/libpayload/libc/coreboot.c b/payloads/libpayload/libc/coreboot.c
index 7873426473..7a9f997054 100644
--- a/payloads/libpayload/libc/coreboot.c
+++ b/payloads/libpayload/libc/coreboot.c
@@ -268,6 +268,10 @@ static void cb_parse_cbmem_entry(void *ptr, struct sysinfo_t *info)
 	case CBMEM_ID_CSE_INFO:
 		info->cse_info = cbmem_entry->address;
 		break;
+	case CBMEM_ID_PVMFW:
+		info->pvmfw = cbmem_entry->address;
+		info->pvmfw_size = cbmem_entry->entry_size;
+		break;
 	default:
 		break;
 	}
diff --git a/src/commonlib/bsd/include/commonlib/bsd/cbmem_id.h b/src/commonlib/bsd/include/commonlib/bsd/cbmem_id.h
index 7873d5856f..4cf1f09a84 100644
--- a/src/commonlib/bsd/include/commonlib/bsd/cbmem_id.h
+++ b/src/commonlib/bsd/include/commonlib/bsd/cbmem_id.h
@@ -90,6 +90,7 @@
 #define CBMEM_ID_CSE_INFO	0x4553435F
 #define CBMEM_ID_CSE_BP_INFO	0x42455343
 #define CBMEM_ID_AMD_OPENSIL	0x4153494C
+#define CBMEM_ID_PVMFW		0x666d7670
 
 #define CBMEM_ID_TO_NAME_TABLE				 \
 	{ CBMEM_ID_ACPI,		"ACPI       " }, \
@@ -172,5 +173,6 @@
 	{ CBMEM_ID_AMD_MP2,		"AMD MP2 BUFFER"},\
 	{ CBMEM_ID_CSE_INFO,		"CSE SPECIFIC INFO"},\
 	{ CBMEM_ID_CSE_BP_INFO,		"CSE BP INFO"}, \
-	{ CBMEM_ID_AMD_OPENSIL,		"OPENSIL DATA"}
+	{ CBMEM_ID_AMD_OPENSIL,		"OPENSIL DATA"}, \
+	{ CBMEM_ID_PVMFW,		"PVMFW      "}
 #endif /* _CBMEM_ID_H_ */
diff --git a/src/vendorcode/google/Kconfig b/src/vendorcode/google/Kconfig
index b24c554147..a846336c0b 100644
--- a/src/vendorcode/google/Kconfig
+++ b/src/vendorcode/google/Kconfig
@@ -37,3 +37,18 @@ config MAINBOARD_HAS_GOOGLE_STRAUSS_KEYBOARD
 
 config ACPI_FNKEY_GEN_SCANCODE
 	default 94 if MAINBOARD_HAS_GOOGLE_STRAUSS_KEYBOARD
+
+config GOOGLE_PVMFW_CBMEM
+	bool "Enable reserving memory for pvmfw using cbmem"
+	default n
+	help
+	  Select this config to enable allocating a region for Android protected
+	  virtual machine firmware within cbmem. The region shall be filled by
+	  the payload and the purpose is to just reserve the memory.
+	  cbmem is used to make sure that the region won't overlap with other
+	  reserved regions or device regions.
+
+config GOOGLE_PVMFW_CBMEM_SIZE
+	hex "Size of the pvmfw buffer to be reserved using cbmem"
+	depends on GOOGLE_PVMFW_CBMEM
+	default 0x400000
diff --git a/src/vendorcode/google/Makefile.mk b/src/vendorcode/google/Makefile.mk
index c9e83897ff..32bb90ff74 100644
--- a/src/vendorcode/google/Makefile.mk
+++ b/src/vendorcode/google/Makefile.mk
@@ -4,3 +4,4 @@ subdirs-$(CONFIG_CHROMEOS) += chromeos
 
 ramstage-$(CONFIG_GOOGLE_DSM_CALIB) += dsm_calib.c
 ramstage-$(CONFIG_GOOGLE_SMBIOS_MAINBOARD_VERSION) += smbios.c
+ramstage-$(CONFIG_GOOGLE_PVMFW_CBMEM) += pvmfw_cbmem.c
diff --git a/src/vendorcode/google/pvmfw_cbmem.c b/src/vendorcode/google/pvmfw_cbmem.c
new file mode 100644
index 0000000000..15b0710645
--- /dev/null
+++ b/src/vendorcode/google/pvmfw_cbmem.c
@@ -0,0 +1,17 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <console/console.h>
+#include <bootstate.h>
+#include <cbmem.h>
+
+static void add_pvmfw_cbmem(void *unused)
+{
+	(void)unused;
+	void *pvmfw;
+
+	pvmfw = cbmem_add(CBMEM_ID_PVMFW, CONFIG_GOOGLE_PVMFW_CBMEM_SIZE);
+	if (!pvmfw)
+		printk(BIOS_ERR, "Failed to add pvmfw info to CBMEM\n");
+}
+
+BOOT_STATE_INIT_ENTRY(BS_WRITE_TABLES, BS_ON_ENTRY, add_pvmfw_cbmem, NULL);

From 883b3971b56676a56448674e24604edb64f16d5d Mon Sep 17 00:00:00 2001
From: Maximilian Brune <maximilian.brune@9elements.com>
Date: Sat, 1 Mar 2025 23:09:10 +0100
Subject: [PATCH 0614/3886] cpu/x86: Replace LAPIC_DM_* with LAPIC_MT_*
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

AMD64 spec refers to the field as MT (Message Type), but the IA64 spec
refers to it as DM (Delivery Mode). The problem is that there is another
field abbreviated as DM (Destination Mode) right next to it. So for
better readability, just stick to the AMD64 terminology.

Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: I25cf69d555fe22526f128ff7ed41f82b71f2acf2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86683
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Andy Ebrahiem <ahmet.ebrahiem@9elements.com>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
---
 src/cpu/intel/car/p4-netburst/cache_as_ram.S |  4 ++--
 src/cpu/x86/lapic/lapic_cpu_stop.c           |  4 ++--
 src/cpu/x86/mp_init.c                        |  6 +++---
 src/include/cpu/x86/lapic_def.h              | 17 +++++++++--------
 4 files changed, 16 insertions(+), 15 deletions(-)

diff --git a/src/cpu/intel/car/p4-netburst/cache_as_ram.S b/src/cpu/intel/car/p4-netburst/cache_as_ram.S
index 1843954539..1ce28a4765 100644
--- a/src/cpu/intel/car/p4-netburst/cache_as_ram.S
+++ b/src/cpu/intel/car/p4-netburst/cache_as_ram.S
@@ -111,7 +111,7 @@ bsp_init:
 
 	/* Send INIT IPI to all excluding ourself. */
 	movl	LAPIC(ICR), %edi
-	movl	$(LAPIC_DEST_ALLBUT | LAPIC_INT_ASSERT | LAPIC_DM_INIT), %eax
+	movl	$(LAPIC_DEST_ALLBUT | LAPIC_INT_ASSERT | LAPIC_MT_INIT), %eax
 1:	movl	%eax, (%edi)
 	movl	$0x30, %ecx
 2:	pause
@@ -160,7 +160,7 @@ hyper_threading_cpu:
 
 	/* Send Start IPI to all excluding ourself. */
 	movl	LAPIC(ICR), %edi
-	movl	$(LAPIC_DEST_ALLBUT | LAPIC_DM_STARTUP), %eax
+	movl	$(LAPIC_DEST_ALLBUT | LAPIC_MT_STARTUP), %eax
 	orl	$ap_sipi_vector_in_rom, %eax
 1:	movl	%eax, (%edi)
 	movl	$0x30, %ecx
diff --git a/src/cpu/x86/lapic/lapic_cpu_stop.c b/src/cpu/x86/lapic/lapic_cpu_stop.c
index 6eacba6c21..1709b951c7 100644
--- a/src/cpu/x86/lapic/lapic_cpu_stop.c
+++ b/src/cpu/x86/lapic/lapic_cpu_stop.c
@@ -56,7 +56,7 @@ void stop_this_cpu(void)
 	printk(BIOS_DEBUG, "CPU %ld going down...\n", id);
 
 	/* send an LAPIC INIT to myself */
-	lapic_send_ipi_self(LAPIC_INT_LEVELTRIG | LAPIC_INT_ASSERT | LAPIC_DM_INIT);
+	lapic_send_ipi_self(LAPIC_INT_LEVELTRIG | LAPIC_INT_ASSERT | LAPIC_MT_INIT);
 	wait_for_ipi_completion_without_printk(timeout_100ms);
 
 	mdelay(10);
@@ -64,7 +64,7 @@ void stop_this_cpu(void)
 	dprintk(BIOS_SPEW, "Deasserting INIT.\n");
 
 	/* Deassert the LAPIC INIT */
-	lapic_send_ipi_self(LAPIC_INT_LEVELTRIG | LAPIC_DM_INIT);
+	lapic_send_ipi_self(LAPIC_INT_LEVELTRIG | LAPIC_MT_INIT);
 	wait_for_ipi_completion_without_printk(timeout_100ms);
 
 	halt();
diff --git a/src/cpu/x86/mp_init.c b/src/cpu/x86/mp_init.c
index 47b3a9ef84..574f28e379 100644
--- a/src/cpu/x86/mp_init.c
+++ b/src/cpu/x86/mp_init.c
@@ -434,7 +434,7 @@ static enum cb_err send_sipi_to_aps(int ap_count, atomic_t *num_aps, int sipi_ve
 		printk(BIOS_DEBUG, "done.\n");
 	}
 
-	lapic_send_ipi_others(LAPIC_INT_ASSERT | LAPIC_DM_STARTUP | sipi_vector);
+	lapic_send_ipi_others(LAPIC_INT_ASSERT | LAPIC_MT_STARTUP | sipi_vector);
 	printk(BIOS_DEBUG, "Waiting for SIPI to complete...\n");
 	if (apic_wait_timeout(10000 /* 10 ms */, 50 /* us */) != CB_SUCCESS) {
 		printk(BIOS_ERR, "timed out.\n");
@@ -474,7 +474,7 @@ static enum cb_err start_aps(struct bus *cpu_bus, int ap_count, atomic_t *num_ap
 	}
 
 	/* Send INIT IPI to all but self. */
-	lapic_send_ipi_others(LAPIC_INT_ASSERT | LAPIC_DM_INIT);
+	lapic_send_ipi_others(LAPIC_INT_ASSERT | LAPIC_MT_INIT);
 
 	if (!CONFIG(X86_INIT_NEED_1_SIPI)) {
 		printk(BIOS_DEBUG, "Waiting for 10ms after sending INIT.\n");
@@ -658,7 +658,7 @@ void smm_initiate_relocation_parallel(void)
 		printk(BIOS_DEBUG, "done.\n");
 	}
 
-	lapic_send_ipi_self(LAPIC_INT_ASSERT | LAPIC_DM_SMI);
+	lapic_send_ipi_self(LAPIC_INT_ASSERT | LAPIC_MT_SMI);
 
 	if (lapic_busy()) {
 		if (apic_wait_timeout(1000 /* 1 ms */, 100 /* us */) != CB_SUCCESS) {
diff --git a/src/include/cpu/x86/lapic_def.h b/src/include/cpu/x86/lapic_def.h
index e118b6b427..cb5482c3c9 100644
--- a/src/include/cpu/x86/lapic_def.h
+++ b/src/include/cpu/x86/lapic_def.h
@@ -42,14 +42,15 @@
 #define		LAPIC_INT_ASSERT		0x04000
 #define		LAPIC_ICR_BUSY		0x01000
 #define		LAPIC_DEST_LOGICAL	0x00800
-#define		LAPIC_DM_FIXED		0x00000
-#define		LAPIC_DM_LOWEST		0x00100
-#define		LAPIC_DM_SMI		0x00200
-#define		LAPIC_DM_REMRD		0x00300
-#define		LAPIC_DM_NMI		0x00400
-#define		LAPIC_DM_INIT		0x00500
-#define		LAPIC_DM_STARTUP		0x00600
-#define		LAPIC_DM_EXTINT		0x00700
+// AMD64 refers to it as MT (Message Type), but IA-64 refers to it as DM (Delivery Mode)
+#define		LAPIC_MT_FIXED		0x00000
+#define		LAPIC_MT_LOWEST		0x00100
+#define		LAPIC_MT_SMI		0x00200
+#define		LAPIC_MT_REMRD		0x00300
+#define		LAPIC_MT_NMI		0x00400
+#define		LAPIC_MT_INIT		0x00500
+#define		LAPIC_MT_STARTUP		0x00600
+#define		LAPIC_MT_EXTINT		0x00700
 #define		LAPIC_VECTOR_MASK	0x000FF
 #define LAPIC_ICR2	0x310
 #define		GET_LAPIC_DEST_FIELD(x)	(((x)>>24)&0xFF)

From 8bc848abd0d6d52d4ec2fe4e5e97a7c8acee1068 Mon Sep 17 00:00:00 2001
From: Ian Feng <ian_feng@compal.corp-partner.google.com>
Date: Fri, 28 Mar 2025 11:35:32 +0800
Subject: [PATCH 0615/3886] mb/google/fatcat/var/francka: Update HDA verb
 tables

Enable internal DMIC for francka.
Camera's DMIC is connected to the ALC256's DMIC pin.

BUG=b:396558772
TEST=Camera's DMIC works on francka.

Change-Id: Ie2b9fbd3d95cac145a4c64d9f07001d81880a0e5
Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87034
Reviewed-by: Terry Cheong <htcheong@chromium.org>
Reviewed-by: Jayvik Desai <jayvik@google.com>
Reviewed-by: Pranava Y N <pranavayn@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/google/fatcat/variants/francka/hda_verb.c | 9 ++++-----
 1 file changed, 4 insertions(+), 5 deletions(-)

diff --git a/src/mainboard/google/fatcat/variants/francka/hda_verb.c b/src/mainboard/google/fatcat/variants/francka/hda_verb.c
index 2f703b78ee..2f49bf2255 100644
--- a/src/mainboard/google/fatcat/variants/francka/hda_verb.c
+++ b/src/mainboard/google/fatcat/variants/francka/hda_verb.c
@@ -6,7 +6,7 @@ const u32 cim_verb_data[] = {
 	/* coreboot specific header */
 	0x10ec0256,	/* Codec Vendor / Device ID: Realtek ALC256 */
 	0x10ec12ac,	/* Subsystem ID */
-	0x00000013,	/* Number of jacks (NID entries) */
+	0x00000015,	/* Number of jacks (NID entries) */
 
 	AZALIA_RESET(0x1),
 	/* NID 0x01, HDA Codec Subsystem ID Verb Table */
@@ -15,11 +15,10 @@ const u32 cim_verb_data[] = {
 	/* Pin Widget Verb Table */
 	/*
 	 * DMIC
-	 * Requirement is to use PCH DMIC. Hence,
-	 * commented out codec's Internal DMIC.
-	 * AZALIA_PIN_CFG(0, 0x12, 0x90A60130),
-	 * AZALIA_PIN_CFG(0, 0x13, 0x40000000),
+	 * Internal DMIC.
 	 */
+	AZALIA_PIN_CFG(0, 0x12, 0x90A60130),
+	AZALIA_PIN_CFG(0, 0x13, 0x90A60140),
 	/* Pin widget 0x14 - Front (Port-D) */
 	AZALIA_PIN_CFG(0, 0x14, 0x90170110),
 	/* Pin widget 0x18 - NPC */

From a65e94d6a178958454c7795e8a89a7ac09ec0290 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Micha=C5=82=20Kope=C4=87?= <michal.kopec@3mdeb.com>
Date: Mon, 10 Mar 2025 14:37:49 +0100
Subject: [PATCH 0616/3886] mb/novacustom/mtl-h/romstage.c: Set Loadline FSP
 UPDs
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Set AC / DC Load Line params. The values were dumped from original Clevo
Insyde UEFI firmware, version 1.07.02

Change-Id: I4cf729fc55ed6f2722606f393b6aa45afe396a6e
Signed-off-by: Michał Kopeć <michal.kopec@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86787
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/novacustom/mtl-h/romstage.c | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/src/mainboard/novacustom/mtl-h/romstage.c b/src/mainboard/novacustom/mtl-h/romstage.c
index 8fdd9eca61..3eb1dca329 100644
--- a/src/mainboard/novacustom/mtl-h/romstage.c
+++ b/src/mainboard/novacustom/mtl-h/romstage.c
@@ -27,5 +27,12 @@ void mainboard_memory_init_params(FSPM_UPD *mupd)
 		},
 	};
 
+	mupd->FspmConfig.AcLoadline[0] = 190;
+	mupd->FspmConfig.AcLoadline[1] = 310;
+	mupd->FspmConfig.AcLoadline[2] = 490;
+	mupd->FspmConfig.DcLoadline[0] = 190;
+	mupd->FspmConfig.DcLoadline[1] = 310;
+	mupd->FspmConfig.DcLoadline[2] = 490;
+
 	memcfg_init(mupd, &mem_config, &dimm_module_spd_info, half_populated);
 }

From cbafdf6d005abc49b30d04deb6f40e03a70299ea Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Micha=C5=82=20Kope=C4=87?= <michal.kopec@3mdeb.com>
Date: Mon, 10 Mar 2025 14:40:38 +0100
Subject: [PATCH 0617/3886] mb/novacustom/mtl-h/ramstage.c: Set Pinmux FSP UPDs
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Set Pin Mux FSP UPDs as per mainboard schematic.

Change-Id: Id075e236cee64527aab644616186a3e223c1bfc3
Signed-off-by: Michał Kopeć <michal.kopec@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86788
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
---
 src/mainboard/novacustom/mtl-h/ramstage.c | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/src/mainboard/novacustom/mtl-h/ramstage.c b/src/mainboard/novacustom/mtl-h/ramstage.c
index 19d14a6e1a..637257a016 100644
--- a/src/mainboard/novacustom/mtl-h/ramstage.c
+++ b/src/mainboard/novacustom/mtl-h/ramstage.c
@@ -35,6 +35,15 @@ void mainboard_silicon_init_params(FSP_S_CONFIG *params)
 	params->PchEspiHostC10ReportEnable = 1;
 
 	// Pinmux configuration
+	params->PchSerialIoI2cSdaPinMux[3] = 0x1A45CA06; // GPP_H6
+	params->PchSerialIoI2cSclPinMux[3] = 0x1A45AA07; // GPP_H7
+
+	params->PchSerialIoI2cSdaPinMux[4] = 0x8A44CC0C; // GPP_E12
+	params->PchSerialIoI2cSclPinMux[4] = 0x8A44AC0D; // GPP_E13
+
+	params->PchSerialIoI2cSdaPinMux[5] = 0x8A46CE0D; // GPP_F13
+	params->PchSerialIoI2cSclPinMux[5] = 0x8A46AE0C; // GPP_F12
+
 	params->CnviRfResetPinMux = 0x194CE404; // GPP_F04
 	params->CnviClkreqPinMux = 0x394CE605;  // GPP_F05
 

From 66d119480c208f734089b283a3c69e49a744f116 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Micha=C5=82=20Kope=C4=87?= <michal.kopec@3mdeb.com>
Date: Mon, 10 Mar 2025 15:07:54 +0100
Subject: [PATCH 0618/3886] mb/novacustom/mtl-h: Add discrete graphics variant
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Add NovaCustom V540TNx and V560TNx, which are variants of the mtl-h
baseboard, but with discrete graphics, compared to the igpu variant.
Other notable differences:

- 16" models come with TAS5825 Smart Amp
- Realtek RTL8111 network adapter
- 14" models have only one SSD slot
- The non-Thunderbolt USB-C port has DP Alt mode with displayport lanes
  sourced from the discrete graphics
- HDMI port is wired to discrete graphics

NVIDIA dGPU ASL code will be added in subsequent patches.

TEST=Build V560TNx with UEFIPayload and boot to payload

Change-Id: I2b8194c486de1ba3e04aa74ed63caa7a151fbb8b
Signed-off-by: Michał Kopeć <michal.kopec@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86790
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
---
 src/mainboard/novacustom/mtl-h/Kconfig        |   19 +
 src/mainboard/novacustom/mtl-h/Kconfig.name   |   10 +-
 src/mainboard/novacustom/mtl-h/Makefile.mk    |    1 +
 .../novacustom/mtl-h/include/mainboard/gpio.h |    2 +-
 .../mtl-h/include/mainboard/variants.h        |    8 +
 src/mainboard/novacustom/mtl-h/ramstage.c     |    9 +-
 .../novacustom/mtl-h/variants/dgpu/data.vbt   |  Bin 0 -> 7680 bytes
 .../novacustom/mtl-h/variants/dgpu/gpio.c     |  329 +++
 .../novacustom/mtl-h/variants/dgpu/hda_verb.c |   87 +
 .../mtl-h/variants/dgpu/overridetree.cb       |   75 +
 .../novacustom/mtl-h/variants/dgpu/ramstage.c |   11 +
 .../novacustom/mtl-h/variants/dgpu/tas5825m.c | 2396 +++++++++++++++++
 .../novacustom/mtl-h/variants/igpu/gpio.c     |    2 +-
 .../novacustom/mtl-h/variants/igpu/ramstage.c |    8 +
 14 files changed, 2952 insertions(+), 5 deletions(-)
 create mode 100644 src/mainboard/novacustom/mtl-h/include/mainboard/variants.h
 create mode 100644 src/mainboard/novacustom/mtl-h/variants/dgpu/data.vbt
 create mode 100644 src/mainboard/novacustom/mtl-h/variants/dgpu/gpio.c
 create mode 100644 src/mainboard/novacustom/mtl-h/variants/dgpu/hda_verb.c
 create mode 100644 src/mainboard/novacustom/mtl-h/variants/dgpu/overridetree.cb
 create mode 100644 src/mainboard/novacustom/mtl-h/variants/dgpu/ramstage.c
 create mode 100644 src/mainboard/novacustom/mtl-h/variants/dgpu/tas5825m.c
 create mode 100644 src/mainboard/novacustom/mtl-h/variants/igpu/ramstage.c

diff --git a/src/mainboard/novacustom/mtl-h/Kconfig b/src/mainboard/novacustom/mtl-h/Kconfig
index 813a558085..f08ce25c18 100644
--- a/src/mainboard/novacustom/mtl-h/Kconfig
+++ b/src/mainboard/novacustom/mtl-h/Kconfig
@@ -23,6 +23,20 @@ config BOARD_NOVACUSTOM_MTLH_COMMON
 	select SPD_READ_BY_WORD
 	select SYSTEM_TYPE_LAPTOP
 
+config BOARD_NOVACUSTOM_V5X0TNX_BASE
+	bool
+	select EC_DASHARO_EC_DGPU
+	select BOARD_NOVACUSTOM_MTLH_COMMON
+	select DRIVERS_I2C_TAS5825M
+
+config BOARD_NOVACUSTOM_V540TNX
+	bool
+	select BOARD_NOVACUSTOM_V5X0TNX_BASE
+
+config BOARD_NOVACUSTOM_V560TNX
+	bool
+	select BOARD_NOVACUSTOM_V5X0TNX_BASE
+
 config BOARD_NOVACUSTOM_V5X0TU_BASE
 	bool
 	select BOARD_NOVACUSTOM_MTLH_COMMON
@@ -43,15 +57,18 @@ config MAINBOARD_DIR
 
 config VARIANT_DIR
 	default "igpu" if BOARD_NOVACUSTOM_V5X0TU_BASE
+	default "dgpu" if BOARD_NOVACUSTOM_V5X0TNX_BASE
 
 config OVERRIDE_DEVICETREE
 	default "variants/\$(CONFIG_VARIANT_DIR)/overridetree.cb"
 
 config MAINBOARD_PART_NUMBER
 	default "V54x_6x_TU" if BOARD_NOVACUSTOM_V5X0TU_BASE
+	default "V5xTNC_TND_TNE" if BOARD_NOVACUSTOM_V5X0TNX_BASE
 
 config MAINBOARD_SMBIOS_PRODUCT_NAME
 	default "V54x_6x_TU" if BOARD_NOVACUSTOM_V5X0TU_BASE
+	default "V5xTNC_TND_TNE" if BOARD_NOVACUSTOM_V5X0TNX_BASE
 
 config MAINBOARD_SMBIOS_MANUFACTURER
 	default "Notebook"
@@ -59,6 +76,8 @@ config MAINBOARD_SMBIOS_MANUFACTURER
 config MAINBOARD_VERSION
 	default "V540TU" if BOARD_NOVACUSTOM_V540TU
 	default "V560TU" if BOARD_NOVACUSTOM_V560TU
+	default "V540TNx" if BOARD_NOVACUSTOM_V540TNX
+	default "V560TNx" if BOARD_NOVACUSTOM_V560TNX
 
 config MAINBOARD_FAMILY
 	string
diff --git a/src/mainboard/novacustom/mtl-h/Kconfig.name b/src/mainboard/novacustom/mtl-h/Kconfig.name
index ff079a0f52..2ad7489def 100644
--- a/src/mainboard/novacustom/mtl-h/Kconfig.name
+++ b/src/mainboard/novacustom/mtl-h/Kconfig.name
@@ -1,7 +1,13 @@
 comment "Meteor Lake H"
 
+config BOARD_NOVACUSTOM_V540TNX
+	bool "V540TNx (14\", discrete graphics)"
+
+config BOARD_NOVACUSTOM_V560TNX
+	bool "V560TNx (16\", discrete graphics)"
+
 config BOARD_NOVACUSTOM_V540TU
-	bool "V540TU (14\")"
+	bool "V540TU (14\", integrated graphics)"
 
 config BOARD_NOVACUSTOM_V560TU
-	bool "V560TU (16\")"
+	bool "V560TU (16\", integrated graphics)"
diff --git a/src/mainboard/novacustom/mtl-h/Makefile.mk b/src/mainboard/novacustom/mtl-h/Makefile.mk
index e4841b26c3..2607864470 100644
--- a/src/mainboard/novacustom/mtl-h/Makefile.mk
+++ b/src/mainboard/novacustom/mtl-h/Makefile.mk
@@ -11,5 +11,6 @@ romstage-y += variants/$(VARIANT_DIR)/gpio.c
 ramstage-y += ramstage.c
 ramstage-y += variants/${VARIANT_DIR}/hda_verb.c
 ramstage-y += variants/$(VARIANT_DIR)/gpio.c
+ramstage-y += variants/$(VARIANT_DIR)/ramstage.c
 
 ramstage-$(CONFIG_HAVE_ACPI_TABLES) += fadt.c
diff --git a/src/mainboard/novacustom/mtl-h/include/mainboard/gpio.h b/src/mainboard/novacustom/mtl-h/include/mainboard/gpio.h
index 57924a615f..eb6998851f 100644
--- a/src/mainboard/novacustom/mtl-h/include/mainboard/gpio.h
+++ b/src/mainboard/novacustom/mtl-h/include/mainboard/gpio.h
@@ -12,6 +12,6 @@
 #endif
 
 void mainboard_configure_early_gpios(void);
-void mainboard_configure_gpios(void);
+void variant_configure_gpios(void);
 
 #endif
diff --git a/src/mainboard/novacustom/mtl-h/include/mainboard/variants.h b/src/mainboard/novacustom/mtl-h/include/mainboard/variants.h
new file mode 100644
index 0000000000..09d2a5b068
--- /dev/null
+++ b/src/mainboard/novacustom/mtl-h/include/mainboard/variants.h
@@ -0,0 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef MAINBOARD_VARIANTS_H
+#define MAINBOARD_VARIANTS_H
+
+void variant_devtree_update(void);
+
+#endif
diff --git a/src/mainboard/novacustom/mtl-h/ramstage.c b/src/mainboard/novacustom/mtl-h/ramstage.c
index 637257a016..4d42fa9a8d 100644
--- a/src/mainboard/novacustom/mtl-h/ramstage.c
+++ b/src/mainboard/novacustom/mtl-h/ramstage.c
@@ -2,6 +2,7 @@
 
 #include <ec/dasharo/ec/acpi.h>
 #include <mainboard/gpio.h>
+#include <mainboard/variants.h>
 #include <smbios.h>
 #include <soc/ramstage.h>
 
@@ -20,9 +21,15 @@ smbios_wakeup_type smbios_system_wakeup_type(void)
 	return SMBIOS_WAKEUP_TYPE_POWER_SWITCH;
 }
 
+void __weak variant_devtree_update(void)
+{
+	/* Override dev tree settings per board */
+}
+
 static void mainboard_init(void *chip_info)
 {
-	mainboard_configure_gpios();
+	variant_configure_gpios();
+	variant_devtree_update();
 }
 
 struct chip_operations mainboard_ops = {
diff --git a/src/mainboard/novacustom/mtl-h/variants/dgpu/data.vbt b/src/mainboard/novacustom/mtl-h/variants/dgpu/data.vbt
new file mode 100644
index 0000000000000000000000000000000000000000..add19e3e7ff160fd869a64deaf186a06ae7c5ba2
GIT binary patch
literal 7680
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ztK)&hnA|62i^-~qiNP0MeDc9Q8O&aYChCJGytypC7<t^RzjJPBS2mz7PRH!meD|Jn
zzTf%I_kHKwbH8(YV5ohN_jV0-_4W7oPjzuYQPSvm`CVKeruIPJz;LI3&_CSX)7No|
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zt5!m%m6HjX@K1Lvk(WY{MFkp6o5m#p`GF!4mpD>DSflPnuS{G@JB2M?_+CdXwz@1k
jZ@!B;aYpbj4Dv@u32c$ykK}lp&EK;iL)h}P9V74;TZVZG

literal 0
HcmV?d00001

diff --git a/src/mainboard/novacustom/mtl-h/variants/dgpu/gpio.c b/src/mainboard/novacustom/mtl-h/variants/dgpu/gpio.c
new file mode 100644
index 0000000000..83829a4d4a
--- /dev/null
+++ b/src/mainboard/novacustom/mtl-h/variants/dgpu/gpio.c
@@ -0,0 +1,329 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <mainboard/gpio.h>
+#include <soc/gpio.h>
+#include <gpio.h>
+#include <timer.h>
+#include <delay.h>
+
+static const struct pad_config gpio_table[] = {
+
+	/* ------- GPIO Community 0 ------- */
+
+	/* ------- GPIO Group CPU ------- */
+
+	/* ------- GPIO Group V ------- */
+	PAD_CFG_NF(GPP_V00, UP_20K, DEEP, NF1),	/* BATLOW# */
+	PAD_CFG_NF(GPP_V01, NATIVE, DEEP, NF1),	/* ACPRESENT */
+	PAD_CFG_GPI_TRIG_OWN(GPP_V02, NATIVE, DEEP, OFF, ACPI),	/* GPIO - CPU_LAN_WAKEUP# */
+	PAD_CFG_NF(GPP_V03, UP_20K, DEEP, NF1),	/* PWRBTN# */
+	PAD_CFG_NF(GPP_V04, NONE, DEEP, NF1),	/* SLP_S3# */
+	PAD_CFG_NF(GPP_V05, NONE, DEEP, NF1),	/* SLP_S4# */
+	PAD_CFG_NF(GPP_V06, NONE, DEEP, NF1),	/* SLP_A# */
+	PAD_CFG_GPO(GPP_V07, 0, DEEP),	/* GPIO */
+	PAD_CFG_NF(GPP_V08, NONE, DEEP, NF1),	/* SUSCLK */
+	PAD_CFG_NF(GPP_V09, NONE, DEEP, NF1),	/* SLP_WLAN# */
+	PAD_CFG_NF(GPP_V10, NONE, DEEP, NF1),	/* SLP_S5# */
+	PAD_CFG_GPO(GPP_V11, 1, DEEP),	/* GPIO - GPIO_LAN_EN */
+	PAD_CFG_NF(GPP_V12, NONE, DEEP, NF1),	/* SLP_LAN# */
+	PAD_CFG_GPO(GPP_V13, 0, DEEP),	/* GPIO */
+	PAD_CFG_NF(GPP_V14, NONE, DEEP, NF1),	/* WAKE# */
+	PAD_CFG_GPO(GPP_V15, 0, DEEP),	/* GPIO */
+	PAD_CFG_GPO(GPP_V16, 0, DEEP),	/* GPIO */
+	PAD_CFG_GPO(GPP_V17, 0, DEEP),	/* GPIO */
+	PAD_CFG_GPO(GPP_V18, 0, DEEP),	/* GPIO */
+	PAD_CFG_NF(GPP_V19, NONE, DEEP, NF1),	/* n/a */
+	PAD_CFG_NF(GPP_V20, NONE, DEEP, NF1),	/* n/a */
+	PAD_CFG_NF(GPP_V21, NONE, DEEP, NF1),	/* n/a */
+	PAD_CFG_GPO(GPP_V22, 0, DEEP),	/* GPIO */
+	PAD_CFG_GPO(GPP_V23, 0, DEEP),	/* GPIO */
+
+	/* ------- GPIO Group GPP_C ------- */
+	PAD_CFG_NF(GPP_C00, UP_20K, DEEP, NF1),	/* SMBCLK */
+	PAD_CFG_NF(GPP_C01, UP_20K, DEEP, NF1),	/* SMBDATA */
+	PAD_CFG_GPI_TRIG_OWN(GPP_C02, NONE, DEEP, OFF, ACPI),	/* GPIO */
+	PAD_CFG_NF(GPP_C03, NONE, DEEP, NF1),	/* SML0CLK */
+	PAD_CFG_NF(GPP_C04, NONE, DEEP, NF1),	/* SML0DATA */
+	PAD_CFG_GPO(GPP_C05, 0, DEEP),	/* GPIO */
+	PAD_CFG_NF(GPP_C06, NONE, RSMRST, NF1),	/* SML1CLK */
+	PAD_CFG_NF(GPP_C07, NONE, RSMRST, NF1),	/* SML1DATA */
+	PAD_CFG_GPO(GPP_C08, 0, DEEP),	/* GPIO */
+	PAD_CFG_GPO(GPP_C09, 0, DEEP),	/* GPIO */
+	PAD_CFG_GPO(GPP_C10, 0, DEEP),	/* GPIO */
+	PAD_CFG_NF(GPP_C11, NONE, DEEP, NF1),	/* SRCCLKREQ2# */
+	PAD_CFG_NF(GPP_C12, NONE, DEEP, NF1),	/* SRCCLKREQ3# */
+	PAD_CFG_GPO(GPP_C13, 0, DEEP),	/* GPIO */
+	PAD_CFG_GPO(GPP_C14, 0, DEEP),	/* GPIO */
+	PAD_CFG_GPI_TRIG_OWN(GPP_C15, NONE, DEEP, OFF, ACPI),	/* GPIO - CPU_DGPU_PWRGD */
+	PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1),	/* TBT_LSX0_TXD */
+	PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1),	/* TBT_LSX0_RXD */
+	PAD_CFG_GPO(GPP_C18, 0, DEEP),	/* GPIO */
+	PAD_CFG_GPO(GPP_C19, 0, DEEP),	/* GPIO */
+	PAD_CFG_GPO(GPP_C20, 0, DEEP),	/* GPIO */
+	PAD_CFG_GPO(GPP_C21, 0, DEEP),	/* GPIO */
+	PAD_CFG_GPO(GPP_C22, 0, DEEP),	/* GPIO */
+	PAD_CFG_GPO(GPP_C23, 0, DEEP),	/* GPIO */
+
+	/* ------- GPIO Community 1 ------- */
+
+	/* ------- GPIO Group GPP_A ------- */
+	PAD_CFG_NF(GPP_A00, UP_20K, DEEP, NF1),	/* ESPI_IO0 */
+	PAD_CFG_NF(GPP_A01, UP_20K, DEEP, NF1),	/* ESPI_IO1 */
+	PAD_CFG_NF(GPP_A02, UP_20K, DEEP, NF1),	/* ESPI_IO2 */
+	PAD_CFG_NF(GPP_A03, UP_20K, DEEP, NF1),	/* ESPI_IO3 */
+	PAD_CFG_NF(GPP_A04, UP_20K, DEEP, NF1),	/* ESPI_CS0# */
+	PAD_CFG_NF(GPP_A05, UP_20K, DEEP, NF1),	/* ESPI_CLK */
+	PAD_CFG_NF(GPP_A06, NONE, DEEP, NF1),	/* ESPI_RESET# */
+	PAD_CFG_GPO(GPP_A07, 0, DEEP),	/* GPIO */
+	PAD_CFG_GPO(GPP_A08, 0, DEEP),	/* GPIO */
+	PAD_CFG_GPO(GPP_A09, 0, DEEP),	/* GPIO */
+	PAD_CFG_GPO(GPP_A10, 0, DEEP),	/* GPIO */
+	PAD_CFG_GPO(GPP_A11, 0, DEEP),	/* GPIO - ADDS_CODE */
+	PAD_CFG_GPI_TRIG_OWN(GPP_A12, NONE, DEEP, OFF, ACPI),	/* GPIO - WLAN_WAKEUP# */
+	PAD_CFG_TERM_GPO(GPP_A13, 1, UP_20K, PLTRST),	/* GPIO - M2_SSD2_RST# */
+	PAD_CFG_GPI_TRIG_OWN(GPP_A14, UP_20K, DEEP, OFF, ACPI),	/* GPIO - NVVDD_ALERT# */
+	PAD_CFG_GPO(GPP_A15, 0, DEEP),	/* GPIO - CPU_SWI# */
+	PAD_CFG_NF(GPP_A16, UP_20K, DEEP, NF1),	/* RSVD - ESPI_ALERT0# */
+	PAD_CFG_GPI_INT(GPP_A17, NONE, PLTRST, LEVEL),	/* GPIO - TP_ATTN# */
+	PAD_CFG_GPO(GPP_A18, 0, DEEP),	/* GPIO - TEST_R (ANX7411) */
+	PAD_CFG_GPI_APIC(GPP_A19, NONE, DEEP, LEVEL, NONE),	/* GPIO - INTP_OUT (ANX7411) */
+	PAD_CFG_GPO(GPP_A20, 1, DEEP),	/* GPIO - LAN_PLT_RST# */
+	PAD_CFG_NF(GPP_A21, NATIVE, DEEP, NF1),	/* PMCALERT# */
+	PAD_NC(GPP_A22, NATIVE),	/* GPIO */
+	PAD_NC(GPP_A23, NATIVE),	/* GPIO */
+
+	/* ------- GPIO Group GPP_E ------- */
+	PAD_CFG_GPI_TRIG_OWN(GPP_E00, NONE, DEEP, OFF, ACPI),	/* GPIO - BOARD_ID7 */
+	PAD_CFG_GPI_APIC(GPP_E01, UP_20K, DEEP, LEVEL, NONE),	/* GPIO - TPM_PIRQ# */
+	PAD_CFG_GPI_TRIG_OWN(GPP_E02, NONE, DEEP, OFF, ACPI),	/* GPIO - BOARD_ID4 */
+	PAD_CFG_GPI_TRIG_OWN(GPP_E03, NONE, DEEP, OFF, ACPI),	/* GPIO - CPU_CNVI_WAKE# */
+	PAD_CFG_GPO(GPP_E04, 0, DEEP),	/* GPIO */
+	PAD_CFG_GPO(GPP_E05, 0, DEEP),	/* GPIO */
+	PAD_CFG_GPI_TRIG_OWN(GPP_E06, NONE, DEEP, OFF, ACPI),	/* GPIO */
+	PAD_CFG_GPO(GPP_E07, 0, DEEP),	/* GPIO - CPU_SMI# */
+	PAD_CFG_GPO(GPP_E08, 0, DEEP),	/* GPIO */
+	PAD_CFG_GPO(GPP_E09, 1, DEEP),	/* GPIO */
+	PAD_CFG_GPO(GPP_E10, 0, DEEP),	/* GPIO */
+	PAD_CFG_GPI_TRIG_OWN(GPP_E11, NONE, DEEP, OFF, ACPI),	/* GPIO - BOARD_ID6 */
+	PAD_CFG_NF(GPP_E12, NONE, DEEP, NF8),	/* I2C4_SDA - ANX7411 */
+	PAD_CFG_NF(GPP_E13, NONE, DEEP, NF8),	/* I2C4_SCL - ANX7411 */
+	PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1),	/* DDSP_HPDA */
+	PAD_CFG_GPO(GPP_E15, 0, DEEP),	/* GPIO - CPU_SCI# */
+	PAD_CFG_NF(GPP_E16, NONE, DEEP, NF2),	/* VRALERT# */
+	PAD_CFG_GPI_TRIG_OWN(GPP_E17, NONE, DEEP, OFF, ACPI),	/* GPIO - BOARD_ID5 */
+	PAD_CFG_GPO(GPP_E18, 0, DEEP),	/* GPIO */
+	PAD_CFG_GPO(GPP_E19, 0, DEEP),	/* GPIO */
+	PAD_CFG_GPO(GPP_E20, 0, DEEP),	/* GPIO */
+	PAD_CFG_GPO(GPP_E21, 0, DEEP),	/* GPIO */
+	PAD_CFG_GPO(GPP_E22, 0, DEEP),	/* GPIO */
+	PAD_NC(GPP_E23, NONE),	/* GPIO */
+	PAD_NC(GPP_THC0_GSPI_CLK_LPBK, NONE),	/* GPIO */
+
+	/* ------- GPIO Community 3 ------- */
+
+	/* ------- GPIO Group GPP_H ------- */
+	PAD_CFG_GPO(GPP_H00, 0, DEEP),	/* GPIO */
+	PAD_CFG_GPO(GPP_H01, 0, DEEP),	/* GPIO */
+	PAD_CFG_GPO(GPP_H02, 0, DEEP),	/* GPIO */
+	PAD_CFG_GPO(GPP_H03, 0, DEEP),	/* GPIO */
+	PAD_CFG_NF(GPP_H04, NONE, DEEP, NF2),	/* CNV_MFUART2_RXD */
+	PAD_CFG_NF(GPP_H05, NONE, DEEP, NF2),	/* CNV_MFUART2_TXD */
+	PAD_CFG_NF(GPP_H06, NONE, DEEP, NF1),	/* I2C3_SDA */
+	PAD_CFG_NF(GPP_H07, NONE, DEEP, NF1),	/* I2C3_SCL */
+	PAD_CFG_NF(GPP_H08, NONE, DEEP, NF1),	/* UART0_RXD */
+	PAD_CFG_NF(GPP_H09, NONE, DEEP, NF1),	/* UART0_TXD */
+	PAD_CFG_GPO(GPP_H10, 0, DEEP),	/* GPIO */
+	PAD_CFG_GPO(GPP_H11, 0, DEEP),	/* GPIO */
+	PAD_CFG_GPO(GPP_H12, 0, DEEP),	/* GPIO */
+	PAD_CFG_NF(GPP_H13, NONE, DEEP, NF1),	/* PROC_C10_GATE# */
+	PAD_CFG_GPO(GPP_H14, 0, DEEP),	/* GPIO */
+	PAD_CFG_GPO(GPP_H15, 0, DEEP),	/* GPIO */
+	PAD_CFG_GPO(GPP_H16, 0, DEEP),	/* GPIO */
+	PAD_CFG_GPO(GPP_H17, 0, DEEP),	/* GPIO */
+	PAD_CFG_GPO(GPP_H18, 0, DEEP),	/* GPIO */
+	PAD_CFG_NF(GPP_H19, NONE, DEEP, NF1),	/* I2C0_SDA */
+	PAD_CFG_NF(GPP_H20, NONE, DEEP, NF1),	/* I2C0_SCL */
+	PAD_CFG_NF(GPP_H21, NONE, DEEP, NF1),	/* I2C1_SDA */
+	PAD_CFG_NF(GPP_H22, NONE, DEEP, NF1),	/* I2C1_SCL */
+	PAD_NC(GPP_H23, NONE),	/* GPIO */
+	PAD_NC(GPP_LPI3C1_CLK_LPBK, NATIVE),	/* GPIO */
+	PAD_CFG_NF(GPP_LPI3C0_CLK_LPBK, NATIVE, DEEP, NF2),	/* n/a */
+
+	/* ------- GPIO Group GPP_F ------- */
+	PAD_CFG_NF(GPP_F00, NONE, DEEP, NF1),	/* CNV_BRI_DT */
+	PAD_CFG_NF(GPP_F01, UP_20K, DEEP, NF1),	/* CNV_BRI_RSP */
+	PAD_CFG_NF(GPP_F02, NONE, DEEP, NF1),	/* CNV_RGI_DT */
+	PAD_CFG_NF(GPP_F03, UP_20K, DEEP, NF1),	/* CNV_RGI_RSP */
+	PAD_CFG_NF(GPP_F04, NONE, DEEP, NF1),	/* CNV_RF_RESET# */
+	PAD_CFG_NF(GPP_F05, NONE, DEEP, NF3),	/* MODEM_CLKREQ */
+	PAD_CFG_NF(GPP_F06, NONE, DEEP, NF1),	/* CNVI_GNSS_PA_BLANKING */
+	PAD_CFG_GPO(GPP_F07, 0, DEEP),	/* GPIO */
+	PAD_CFG_GPO(GPP_F08, 0, DEEP),	/* GPIO */
+	PAD_CFG_GPI_TRIG_OWN(GPP_F09, NONE, DEEP, OFF, ACPI),	/* GPIO - TPM_DET */
+	PAD_CFG_GPO(GPP_F10, 0, DEEP),	/* GPIO */
+	PAD_CFG_GPI_TRIG_OWN(GPP_F11, NONE, DEEP, OFF, ACPI),	/* GPIO - BOARD_ID3 */
+	PAD_CFG_NF(GPP_F12, NONE, DEEP, NF8),	/* I2C5_SCL - Smart AMP */
+	PAD_CFG_NF(GPP_F13, NONE, DEEP, NF8),	/* I2C5_SDA - Smart AMP */
+	PAD_CFG_GPI_TRIG_OWN(GPP_F14, NONE, DEEP, OFF, ACPI),	/* GPIO - BOARD_ID1 */
+	PAD_CFG_GPI_TRIG_OWN(GPP_F15, NONE, DEEP, OFF, ACPI),	/* GPIO - BOARD_ID2 */
+	PAD_CFG_GPI_TRIG_OWN(GPP_F16, NONE, DEEP, OFF, ACPI),	/* GPIO - GPIO4_GC6_NVVDD_EN */
+	PAD_CFG_GPI_TRIG_OWN(GPP_F17, NONE, PLTRST, OFF, ACPI),	/* GPIO - CPU_GC6_FB_EN */
+	PAD_CFG_GPO(GPP_F18, 0, DEEP),	/* GPIO -CCD_WP# */
+	PAD_CFG_GPO(GPP_F19, 0, DEEP),	/* GPIO */
+	PAD_CFG_GPO(GPP_F20, 0, DEEP),	/* GPIO */
+	PAD_CFG_GPO(GPP_F21, 0, DEEP),	/* GPIO */
+	PAD_CFG_GPO(GPP_F22, 0, DEEP),	/* GPIO */
+	PAD_CFG_GPO(GPP_F23, 0, DEEP),	/* GPIO */
+	PAD_NC(GPP_THC1_GSPI1_CLK_LPBK, NONE),	/* GPIO */
+	PAD_NC(GPP_GSPI0A_CLK_LOOPBK, NONE),	/* GPIO */
+
+	/* ------- GPIO Group SPI ------- */
+
+	/* ------- GPIO Group VGPIO3 ------- */
+	PAD_CFG_NF(GPP_VGPIO3_USB0, NONE, DEEP, NF1),	/* GPP_VGPIO3_USB0 */
+	PAD_CFG_NF(GPP_VGPIO3_USB1, NONE, DEEP, NF1),	/* GPP_VGPIO3_USB1 */
+	PAD_CFG_NF(GPP_VGPIO3_USB2, NONE, DEEP, NF1),	/* GPP_VGPIO3_USB2 */
+	PAD_CFG_NF(GPP_VGPIO3_USB3, NONE, DEEP, NF1),	/* GPP_VGPIO3_USB3 */
+	PAD_CFG_NF(GPP_VGPIO3_USB4, NONE, DEEP, NF1),	/* GPP_VGPIO3_USB4 */
+	PAD_CFG_NF(GPP_VGPIO3_USB5, NONE, DEEP, NF1),	/* GPP_VGPIO3_USB5 */
+	PAD_CFG_NF(GPP_VGPIO3_USB6, NONE, DEEP, NF1),	/* GPP_VGPIO3_USB6 */
+	PAD_CFG_NF(GPP_VGPIO3_USB7, NONE, DEEP, NF1),	/* GPP_VGPIO3_USB7 */
+	PAD_CFG_GPI_TRIG_OWN(GPP_VGPIO3_TS0, NONE, DEEP, OFF, ACPI),	/* GPIO */
+	PAD_CFG_GPI_TRIG_OWN(GPP_VGPIO3_TS1, NONE, DEEP, OFF, ACPI),	/* GPIO */
+	PAD_CFG_GPI_TRIG_OWN(GPP_VGPIO3_THC0, NONE, DEEP, OFF, ACPI),	/* GPIO */
+	PAD_CFG_GPI_TRIG_OWN(GPP_VGPIO3_THC1, NONE, DEEP, OFF, ACPI),	/* GPIO */
+	PAD_CFG_GPI_TRIG_OWN(GPP_VGPIO3_THC2, NONE, DEEP, OFF, ACPI),	/* GPIO */
+	PAD_CFG_GPI_TRIG_OWN(GPP_VGPIO3_THC3, NONE, DEEP, OFF, ACPI),	/* GPIO */
+
+	/* ------- GPIO Community 4 ------- */
+
+	/* ------- GPIO Group GPP_S ------- */
+	PAD_CFG_GPO(GPP_S00, 0, DEEP),	/* GPIO */
+	PAD_CFG_GPO(GPP_S01, 0, DEEP),	/* GPIO */
+	PAD_CFG_GPO(GPP_S02, 0, DEEP),	/* GPIO */
+	PAD_CFG_GPO(GPP_S03, 0, DEEP),	/* GPIO */
+	PAD_CFG_GPO(GPP_S04, 0, DEEP),	/* GPIO */
+	PAD_CFG_GPO(GPP_S05, 0, DEEP),	/* GPIO */
+	PAD_CFG_GPO(GPP_S06, 0, DEEP),	/* GPIO */
+	PAD_CFG_GPO(GPP_S07, 0, DEEP),	/* GPIO */
+
+	/* ------- GPIO Group JTAG ------- */
+
+	/* ------- GPIO Community 5 ------- */
+
+	/* ------- GPIO Group GPP_B ------- */
+	PAD_CFG_GPO(GPP_B00, 0, DEEP),	/* GPIO */
+	PAD_CFG_GPO(GPP_B01, 0, DEEP),	/* GPIO */
+	PAD_CFG_GPO(GPP_B02, 0, DEEP),	/* GPIO */
+	PAD_CFG_GPO(GPP_B03, 0, DEEP),	/* GPIO */
+	PAD_CFG_GPO(GPP_B04, 0, DEEP),	/* GPIO */
+	PAD_CFG_GPO(GPP_B05, 0, DEEP),	/* GPIO - CPU_KBCRST# */
+	PAD_CFG_GPO(GPP_B06, 0, DEEP),	/* GPIO - ROM_I2C_EN */
+	PAD_CFG_GPO(GPP_B07, 0, DEEP),	/* GPIO - PANTONE_WP# */
+	PAD_CFG_GPO(GPP_B08, 0, DEEP),	/* GPIO - PS8461_SW (DDS for eDP) */
+	PAD_CFG_GPO(GPP_B09, 0, DEEP),	/* GPIO - DGPU_RST#_PCH */
+	PAD_CFG_GPI_SCI(GPP_B10, NONE, PLTRST, EDGE_BOTH, INVERT),	/* GPIO - NV Type-C DP HPD */
+	PAD_CFG_GPI_SCI(GPP_B11, NONE, PLTRST, EDGE_BOTH, INVERT),	/* GPIO - NV HDMI HPD */
+	PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1),	/* SLP_S0# */
+	PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1),	/* PLTRST# */
+	PAD_CFG_GPO(GPP_B14, 0, DEEP),	/* GPIO */
+	PAD_CFG_GPI_TRIG_OWN(GPP_B15, NONE, DEEP, OFF, ACPI),	/* GPIO */
+	PAD_CFG_GPO(GPP_B16, 0, DEEP),	/* GPIO */
+	PAD_CFG_GPO(GPP_B17, 1, DEEP),	/* GPIO - CPU_GPIO_LANRTD3 */
+	PAD_CFG_GPO(GPP_B18, 1, DEEP),	/* GPIO - PCH_BT_EN */
+	PAD_CFG_GPO(GPP_B19, 1, DEEP),	/* GPIO - WIFI_RF_EN */
+	PAD_CFG_GPO(GPP_B20, 0, DEEP),	/* GPIO */
+	PAD_CFG_GPO(GPP_B21, 0, PLTRST),	/* GPIO - TBT_FORCE_PWR */
+	PAD_CFG_GPO(GPP_B22, 0, DEEP),	/* GPIO */
+	PAD_CFG_TERM_GPO(GPP_B23, 0, DN_20K, DEEP),	/* GPIO */
+	PAD_CFG_NF(GPP_ACI3C0_CLK_LPBK, NATIVE, DEEP, NF4),	/* n/a */
+
+	/* ------- GPIO Group GPP_D ------- */
+	PAD_CFG_GPO(GPP_D00, 1, DEEP),	/* GPIO - SB_BLON */
+	PAD_CFG_GPO(GPP_D01, 1, DEEP),	/* GPIO - SSD2_PWR_EN */
+	PAD_CFG_GPO(GPP_D02, 1, DEEP),	/* GPIO - M2_SSD1_RST# */
+	PAD_CFG_GPO(GPP_D03, 0, DEEP),	/* GPIO - CPU_DGPU_PWR_EN */
+	PAD_CFG_GPO(GPP_D04, 0, DEEP),	/* GPIO */
+	PAD_CFG_GPO(GPP_D05, 1, DEEP),	/* GPIO - SSD1_PWR_EN */
+	PAD_CFG_GPO(GPP_D06, 0, DEEP),	/* GPIO */
+	PAD_CFG_GPO(GPP_D07, 0, DEEP),	/* GPIO */
+	PAD_CFG_GPO(GPP_D08, 0, DEEP),	/* GPIO */
+	PAD_CFG_GPO(GPP_D09, 0, DEEP),	/* GPIO */
+	PAD_CFG_NF(GPP_D10, NONE, DEEP, NF1),	/* HDA_BCLK */
+	PAD_CFG_NF(GPP_D11, NATIVE, DEEP, NF1),	/* HDA_SYNC */
+	PAD_CFG_NF(GPP_D12, NATIVE, DEEP, NF1),	/* HDA_SDO */
+	PAD_CFG_NF(GPP_D13, NATIVE, DEEP, NF1),	/* HDA_SDI0 */
+	PAD_CFG_GPO(GPP_D14, 0, DEEP),	/* GPIO */
+	PAD_CFG_GPO(GPP_D15, 0, DEEP),	/* GPIO */
+	PAD_CFG_GPO(GPP_D16, 0, DEEP),	/* GPIO - GPIO_SPK_MUTE */
+	PAD_CFG_NF(GPP_D17, NONE, DEEP, NF1),	/* HDA_RST# */
+	PAD_CFG_NF(GPP_D18, NONE, DEEP, NF1),	/* SRCCLKREQ6# */
+	PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1),	/* SRCCLKREQ7# */
+	PAD_CFG_NF(GPP_D20, NONE, DEEP, NF1),	/* SRCCLKREQ8# */
+	PAD_CFG_NF(GPP_D21, NONE, DEEP, NF2),	/* SRCCLKREQ5# */
+	PAD_CFG_NF(GPP_D22, NATIVE, DEEP, NF1),	/* n/a */
+	PAD_CFG_NF(GPP_D23, NATIVE, DEEP, NF1),	/* n/a */
+	PAD_CFG_NF(GPP_BOOTHALT_B, UP_20K, DEEP, NF1),	/* GPP_BOOTHALT_B */
+
+	/* ------- GPIO Group VGPIO ------- */
+	PAD_CFG_GPO(GPP_VGPIO00, 1, DEEP),	/* GPIO */
+	PAD_CFG_GPI_TRIG_OWN(GPP_VGPIO04, NONE, DEEP, OFF, ACPI),	/* GPIO */
+	PAD_CFG_GPO(GPP_VGPIO05, 1, DEEP),	/* GPIO */
+	PAD_CFG_GPIO_BIDIRECT(GPP_VGPIO06, 0, NONE, DEEP, LEVEL, ACPI),	/* GPIO */
+	PAD_CFG_GPIO_BIDIRECT(GPP_VGPIO07, 0, NONE, DEEP, LEVEL, ACPI),	/* GPIO */
+	PAD_CFG_GPIO_BIDIRECT(GPP_VGPIO08, 0, NONE, DEEP, LEVEL, ACPI),	/* GPIO */
+	PAD_CFG_GPIO_BIDIRECT(GPP_VGPIO09, 0, NONE, DEEP, LEVEL, ACPI),	/* GPIO */
+	PAD_CFG_NF(GPP_VGPIO10, NONE, DEEP, NF1),	/* GPP_VGPIO10 */
+	PAD_CFG_NF(GPP_VGPIO11, NONE, DEEP, NF1),	/* GPP_VGPIO11 */
+	PAD_CFG_NF(GPP_VGPIO12, NONE, DEEP, NF1),	/* GPP_VGPIO12 */
+	PAD_CFG_NF(GPP_VGPIO13, NONE, DEEP, NF1),	/* GPP_VGPIO13 */
+	PAD_CFG_GPIO_BIDIRECT(GPP_VGPIO18, 0, NONE, DEEP, LEVEL, ACPI),	/* GPIO */
+	PAD_CFG_GPIO_BIDIRECT(GPP_VGPIO19, 0, NONE, DEEP, LEVEL, ACPI),	/* GPIO */
+	PAD_CFG_GPIO_BIDIRECT(GPP_VGPIO20, 0, NONE, DEEP, LEVEL, ACPI),	/* GPIO */
+	PAD_CFG_GPIO_BIDIRECT(GPP_VGPIO21, 0, NONE, DEEP, LEVEL, ACPI),	/* GPIO */
+	PAD_CFG_NF(GPP_VGPIO22, NONE, DEEP, NF1),	/* GPP_VGPIO22 */
+	PAD_CFG_NF(GPP_VGPIO23, NONE, DEEP, NF1),	/* GPP_VGPIO23 */
+	PAD_CFG_NF(GPP_VGPIO24, NONE, DEEP, NF1),	/* GPP_VGPIO24 */
+	PAD_CFG_NF(GPP_VGPIO25, NONE, DEEP, NF1),	/* GPP_VGPIO25 */
+	PAD_CFG_NF(GPP_VGPIO30, NONE, DEEP, NF3),	/* RESERVED */
+	PAD_CFG_NF(GPP_VGPIO31, NONE, DEEP, NF3),	/* RESERVED */
+	PAD_CFG_NF(GPP_VGPIO32, NONE, DEEP, NF3),	/* RESERVED */
+	PAD_CFG_NF(GPP_VGPIO33, NONE, DEEP, NF3),	/* RESERVED */
+	PAD_CFG_NF(GPP_VGPIO34, NONE, DEEP, NF1),	/* GPP_VGPIO34 */
+	PAD_CFG_NF(GPP_VGPIO35, NONE, DEEP, NF1),	/* GPP_VGPIO35 */
+	PAD_CFG_NF(GPP_VGPIO36, NONE, DEEP, NF1),	/* GPP_VGPIO36 */
+	PAD_CFG_NF(GPP_VGPIO37, NONE, DEEP, NF1),	/* GPP_VGPIO37 */
+	PAD_CFG_NF(GPP_VGPIO40, NONE, DEEP, NF2),	/* RESERVED */
+	PAD_CFG_NF(GPP_VGPIO41, NONE, DEEP, NF2),	/* RESERVED */
+	PAD_CFG_NF(GPP_VGPIO42, NONE, DEEP, NF2),	/* RESERVED */
+	PAD_CFG_NF(GPP_VGPIO43, NONE, DEEP, NF2),	/* RESERVED */
+	PAD_CFG_NF(GPP_VGPIO44, NONE, DEEP, NF1),	/* GPP_VGPIO44 */
+	PAD_CFG_NF(GPP_VGPIO45, NONE, DEEP, NF1),	/* GPP_VGPIO45 */
+	PAD_CFG_NF(GPP_VGPIO46, NONE, DEEP, NF1),	/* GPP_VGPIO46 */
+	PAD_CFG_NF(GPP_VGPIO47, NONE, DEEP, NF1),	/* GPP_VGPIO47 */
+};
+
+#define DGPU_RST_N GPP_B09
+#define DGPU_PWR_EN GPP_D03
+#define DGPU_PWRGD GPP_C15
+
+/* Pad configuration was generated automatically using intelp2m utility */
+void variant_configure_gpios(void)
+{
+	bool result;
+
+	gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table));
+
+	/* dGPU power on sequence */
+	mdelay(4);
+	gpio_set(DGPU_PWR_EN, 1);
+	result = wait_ms(200, gpio_get(DGPU_PWRGD) == 1);
+	if (result) {
+		printk(BIOS_INFO, "dGPU powered on\n");
+		gpio_set(DGPU_RST_N, 1);
+	} else {
+		printk(BIOS_ERR, "dGPU failed to power on, turning off\n");
+		gpio_set(DGPU_PWR_EN, 0);
+	}
+	mdelay(50);
+}
diff --git a/src/mainboard/novacustom/mtl-h/variants/dgpu/hda_verb.c b/src/mainboard/novacustom/mtl-h/variants/dgpu/hda_verb.c
new file mode 100644
index 0000000000..376ed9dc5b
--- /dev/null
+++ b/src/mainboard/novacustom/mtl-h/variants/dgpu/hda_verb.c
@@ -0,0 +1,87 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <console/console.h>
+#include <device/azalia_device.h>
+#include <gpio.h>
+
+const u32 cim_verb_data[] = {
+	/* Realtek, ALC245 */
+	0x10ec0245, /* Vendor ID */
+	0x1558a741, /* Subsystem ID */
+	30, /* Number of entries */
+	AZALIA_SUBVENDOR(0, 0x1558a741),
+	AZALIA_RESET(1),
+
+	0x1271C30,     0x1271D01,     0x1271EA6,     0x1271F90,
+	0x1371C00,     0x1371D00,     0x1371E00,     0x1371F40,
+	0x1871CF0,     0x1871D11,     0x1871E11,     0x1871F41,
+	0x1971CF0,     0x1971D11,     0x1971E11,     0x1971F41,
+	0x1A71CF0,     0x1A71D11,     0x1A71E11,     0x1A71F41,
+	0x1B71CF0,     0x1B71D11,     0x1B71E11,     0x1B71F41,
+	0x1D71C2D,     0x1D71D9B,     0x1D71E68,     0x1D71F40,
+	0x1E71CF0,     0x1E71D11,     0x1E71E11,     0x1E71F41,
+	0x2171C20,     0x2171D10,     0x2171E21,     0x2171F04,
+	0x5B50006,     0x5B40011,     0x205001A,     0x204810B,
+	0x205004A,     0x2042010,     0x2050038,     0x2044909,
+	0x5C50000,     0x5C43D82,     0x5C50000,     0x5C43D82,
+	0x5350000,     0x534201A,     0x5350000,     0x534201A,
+	0x535001D,     0x5340800,     0x535001E,     0x5340800,
+	0x5350003,     0x5341EC4,     0x5350004,     0x5340000,
+	0x5450000,     0x5442000,     0x545001D,     0x5440800,
+	0x545001E,     0x5440800,     0x5450003,     0x5441EC4,
+	0x5450004,     0x5440000,     0x5350000,     0x534A01A,
+	0x205003C,     0x204F175,     0x205003C,     0x204F135,
+	0x2050040,     0x2048800,     0x5A50001,     0x5A4001F,
+	0x2050010,     0x2040020,     0x2050010,     0x2040020,
+	0x170500,      0x170500,      0x5A50004,     0x5A40113,
+	0x2050008,     0x2046A8C,     0x2050076,     0x204F000,
+	0x205000E,     0x20465C0,     0x2050033,     0x2048580,
+	0x2050069,     0x204FDA8,     0x2050068,     0x2040000,
+	0x2050003,     0x2040002,     0x2050069,     0x2040000,
+	0x2050068,     0x2040001,     0x205002E,     0x204290E,
+	0x2050010,     0x2040020,     0x2050010,     0x2040020,
+
+	/* Intel Meteor Lake HDMI */
+	0x8086281d, /* Vendor ID */
+	0x80860101, /* Subsystem ID */
+	10, /* Number of entries */
+	AZALIA_SUBVENDOR(2, 0x80860101),
+	AZALIA_PIN_CFG(2, 0x04, 0x18560010),
+	AZALIA_PIN_CFG(2, 0x06, 0x18560010),
+	AZALIA_PIN_CFG(2, 0x08, 0x18560010),
+	AZALIA_PIN_CFG(2, 0x0a, 0x18560010),
+	AZALIA_PIN_CFG(2, 0x0b, 0x18560010),
+	AZALIA_PIN_CFG(2, 0x0c, 0x18560010),
+	AZALIA_PIN_CFG(2, 0x0d, 0x18560010),
+	AZALIA_PIN_CFG(2, 0x0e, 0x18560010),
+	AZALIA_PIN_CFG(2, 0x0f, 0x18560010),
+};
+
+const u32 pc_beep_verbs[] = {};
+
+AZALIA_ARRAY_SIZES;
+
+static const u32 smartamp_verbs[] = {
+	0x1471CF0,     0x1471D11,     0x1471E11,     0x1471F41,
+	0x1771C10,     0x1771D01,     0x1771E17,     0x1771F90,
+};
+
+static const u32 no_smartamp_verbs[] = {
+	0x1471C10,     0x1471D01,     0x1471E17,     0x1471F90,
+	0x1771C11,     0x1771D01,     0x1771E17,     0x1771F90,
+	0x205006B,     0x204A390,     0x205006B,     0x204A390,
+	0x205006C,     0x2040C9E,     0x205006D,     0x2040C00,
+};
+
+void mainboard_azalia_program_runtime_verbs(u8 *base, u32 viddid)
+{
+	if (gpio_get(GPP_E00)) {
+		printk(BIOS_INFO, "Normal amp detected\n");
+		azalia_program_verb_table(base, no_smartamp_verbs,
+			ARRAY_SIZE(no_smartamp_verbs));
+	} else {
+		printk(BIOS_INFO, "Smart amp detected\n");
+		azalia_program_verb_table(base, smartamp_verbs,
+			ARRAY_SIZE(smartamp_verbs));
+	}
+}
diff --git a/src/mainboard/novacustom/mtl-h/variants/dgpu/overridetree.cb b/src/mainboard/novacustom/mtl-h/variants/dgpu/overridetree.cb
new file mode 100644
index 0000000000..3c60a20405
--- /dev/null
+++ b/src/mainboard/novacustom/mtl-h/variants/dgpu/overridetree.cb
@@ -0,0 +1,75 @@
+chip soc/intel/meteorlake
+	# Power limits,
+	# PsysPL2, PsysPL3, PL4 are configured by EC at runtime
+	register "power_limits_config[MTL_P_682_482_CORE]" = "{
+		.tdp_pl1_override = 35,
+		.tdp_pl2_override = 64,
+		.tdp_pl4 = 120,
+		.psys_pmax = 180,
+	}"
+
+	# MTL SOC has additional setting for PsysPmax
+	register "psys_pmax_watts" = "180"
+
+	device domain 0 on
+		subsystemid 0x1558 0xa741 inherit
+		device ref pcie_rp12 on # PEG
+			register "pcie_rp[PCH_RP(12)]" = "{
+				.clk_src = 6,
+				.clk_req = 6,
+				.flags = PCIE_RP_LTR | PCIE_RP_AER | PCIE_RP_CLK_REQ_DETECT,
+			}"
+			device pci 00.0 on
+				subsystemid 0x1558 0xa761
+			end
+		end
+		device ref igpu on
+			register "ddi_port_A_config" = "1"
+			register "ddi_ports_config" = "{
+				[DDI_PORT_A] = DDI_ENABLE_HPD, 	/* eDP */
+			}"
+		end
+		device ref i2c0 on # Touchpad
+			register "serial_io_i2c_mode[PchSerialIoIndexI2C0]" = "PchSerialIoPci"
+			chip drivers/i2c/hid
+				register "generic.hid" = ""ELAN0412""
+				register "generic.desc" = ""ELAN Touchpad""
+				register "generic.irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPP_A17)"
+				register "generic.detect" = "1"
+				register "hid_desc_reg_offset" = "0x01"
+				device i2c 15 on end
+			end
+			chip drivers/i2c/hid
+				register "generic.hid" = ""FTCS1000""
+				register "generic.desc" = ""FocalTech Touchpad""
+				register "generic.irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPP_A17)"
+				register "generic.detect" = "1"
+				register "hid_desc_reg_offset" = "0x01"
+				device i2c 38 on end
+			end
+		end
+		device ref i2c4 on # ANX7443 USB-C Retimer
+			register "serial_io_i2c_mode[PchSerialIoIndexI2C4]" = "PchSerialIoPci"
+		end
+		device ref i2c5 on # TAS5825M SmartAmp
+			register "serial_io_i2c_mode[PchSerialIoIndexI2C5]" = "PchSerialIoPci"
+			chip drivers/i2c/tas5825m
+				register "id" = "0"
+				device i2c 4e on end
+			end
+		end
+		device ref pcie_rp5 on # GLAN
+			register "pcie_rp[PCH_RP(5)]" = "{
+				.clk_src = 2,
+				.clk_req = 2,
+				.flags = PCIE_RP_LTR | PCIE_RP_AER,
+			}"
+			chip soc/intel/common/block/pcie/rtd3
+				register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_V11)"
+				register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A20)"
+				register "srcclk_pin" = "2"
+				device generic 0 on end
+			end
+		end
+	end
+end
diff --git a/src/mainboard/novacustom/mtl-h/variants/dgpu/ramstage.c b/src/mainboard/novacustom/mtl-h/variants/dgpu/ramstage.c
new file mode 100644
index 0000000000..adff672a40
--- /dev/null
+++ b/src/mainboard/novacustom/mtl-h/variants/dgpu/ramstage.c
@@ -0,0 +1,11 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <mainboard/variants.h>
+#include <gpio.h>
+
+void variant_devtree_update(void)
+{
+	struct device *i2c_amp_dev = pcidev_on_root(0x19, 1);
+	if (i2c_amp_dev)
+		i2c_amp_dev->enabled = !gpio_get(GPP_E00);
+}
diff --git a/src/mainboard/novacustom/mtl-h/variants/dgpu/tas5825m.c b/src/mainboard/novacustom/mtl-h/variants/dgpu/tas5825m.c
new file mode 100644
index 0000000000..5e95c4b13c
--- /dev/null
+++ b/src/mainboard/novacustom/mtl-h/variants/dgpu/tas5825m.c
@@ -0,0 +1,2396 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <delay.h>
+#include <drivers/i2c/tas5825m/tas5825m.h>
+
+/*
+ * This code was auto-generated using extract.rs from
+ * https://github.com/system76/smart-amp
+ */
+
+int tas5825m_setup(struct device *dev, int id)
+{
+	int res;
+
+	res = tas5825m_set_book(dev, 0x00);
+	if (res < 0)
+		return res;
+
+	res = tas5825m_write_at(dev, 0x03, 0x02);
+	if (res < 0)
+		return res;
+
+	res = tas5825m_write_at(dev, 0x01, 0x11);
+	if (res < 0)
+		return res;
+
+	res = tas5825m_set_page(dev, 0x00);
+	if (res < 0)
+		return res;
+
+	res = tas5825m_set_page(dev, 0x00);
+	if (res < 0)
+		return res;
+
+	res = tas5825m_set_page(dev, 0x00);
+	if (res < 0)
+		return res;
+
+	res = tas5825m_set_page(dev, 0x00);
+	if (res < 0)
+		return res;
+
+	res = tas5825m_set_book(dev, 0x00);
+	if (res < 0)
+		return res;
+
+	res = tas5825m_write_at(dev, 0x03, 0x02);
+	if (res < 0)
+		return res;
+
+	mdelay(5);
+
+	res = tas5825m_set_page(dev, 0x00);
+	if (res < 0)
+		return res;
+
+	res = tas5825m_set_page(dev, 0x00);
+	if (res < 0)
+		return res;
+
+	res = tas5825m_set_page(dev, 0x00);
+	if (res < 0)
+		return res;
+
+	res = tas5825m_set_page(dev, 0x00);
+	if (res < 0)
+		return res;
+
+	res = tas5825m_set_book(dev, 0x00);
+	if (res < 0)
+		return res;
+
+	res = tas5825m_write_at(dev, 0x03, 0x12);
+	if (res < 0)
+		return res;
+
+	res = tas5825m_set_page(dev, 0x00);
+	if (res < 0)
+		return res;
+
+	res = tas5825m_set_page(dev, 0x00);
+	if (res < 0)
+		return res;
+
+	res = tas5825m_set_page(dev, 0x00);
+	if (res < 0)
+		return res;
+
+	res = tas5825m_set_page(dev, 0x00);
+	if (res < 0)
+		return res;
+
+	res = tas5825m_set_book(dev, 0x00);
+	if (res < 0)
+		return res;
+
+	res = tas5825m_write_at(dev, 0x48, 0x0C);
+	if (res < 0)
+		return res;
+
+	res = tas5825m_set_book(dev, 0x64);
+	if (res < 0)
+		return res;
+
+	res = tas5825m_set_page(dev, 0x01);
+	if (res < 0)
+		return res;
+
+	{
+		const uint8_t values[] = {
+			0x00, 0xFE, 0x00, 0x40, 0x00, 0xFC, 0x00, 0x00,
+			0x00, 0xFC, 0x00, 0x00, 0x00, 0xFC, 0x00, 0x00,
+			0x00, 0xFC, 0x00, 0x00, 0x00, 0xFC, 0x00, 0x00,
+			0x00, 0xFC, 0x00, 0x00, 0x00, 0xFC, 0x00, 0x00,
+			0x00, 0xFC, 0x50, 0x00, 0x00, 0xFC, 0x00, 0x00,
+			0x00, 0xFC, 0x00, 0x00, 0x00, 0xFC, 0x00, 0x00,
+			0x00, 0xFC, 0x00, 0x00, 0x00, 0xFC, 0x00, 0x00,
+			0x00, 0xFC, 0x00, 0x00, 0x00, 0xFC, 0x00, 0x00,
+			0x00, 0xFC, 0x00, 0x00, 0x00, 0xFC, 0x00, 0x00,
+			0x00, 0xFC, 0x00, 0x00, 0x00, 0xFC, 0x00, 0x00,
+			0x00, 0xFC, 0x00, 0x00, 0x00, 0xFC, 0x00, 0x00,
+			0x00, 0xFC, 0x00, 0x00, 0x00, 0xFC, 0x00, 0x00,
+			0x00, 0x82, 0x00, 0x93, 0x00, 0xFC, 0x00, 0x00,
+			0x8F, 0x00, 0xFF, 0xEF, 0x84, 0x49, 0x03, 0x27,
+			0x84, 0x02, 0x04, 0x06, 0x02, 0x60, 0x00, 0x01,
+			0x00
+		};
+		res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values));
+		if (res < 0)
+			return res;
+	}
+
+	res = tas5825m_set_page(dev, 0x02);
+	if (res < 0)
+		return res;
+
+	{
+		const uint8_t values[] = {
+			0x02, 0x70, 0x00, 0x06, 0x02, 0x78, 0x00, 0x05,
+			0x02, 0x68, 0x00, 0x02, 0x02, 0x28, 0x03, 0x4D,
+			0x84, 0x2A, 0x04, 0x00, 0xE2, 0x57, 0x91, 0x9F,
+			0x84, 0x82, 0x20, 0xE0, 0x84, 0x82, 0x04, 0x01,
+			0xF0, 0x1C, 0x31, 0xA0, 0xF0, 0x1C, 0x31, 0xA1,
+			0xF0, 0x1C, 0x31, 0xA2, 0xF0, 0x1F, 0x31, 0xA3,
+			0xE4, 0x00, 0x11, 0xA6, 0x80, 0x27, 0x80, 0xE1,
+			0xF4, 0x00, 0x11, 0xA4, 0xF4, 0x1D, 0x31, 0xA5,
+			0xF4, 0x1C, 0x31, 0xA7, 0xF4, 0x1F, 0x31, 0xA8,
+			0x02, 0x78, 0x00, 0x03, 0xE2, 0x68, 0xF1, 0xC3,
+			0x80, 0x67, 0x80, 0xE9, 0x84, 0x4B, 0x03, 0x27,
+			0x02, 0x70, 0x00, 0x04, 0x84, 0x41, 0x03, 0x37,
+			0x80, 0x07, 0x00, 0x80, 0xE0, 0x00, 0x11, 0xA9,
+			0x84, 0x82, 0x00, 0xE0, 0x8E, 0xFC, 0x04, 0x10,
+			0xF0, 0x1C, 0x11, 0xAA, 0xF0, 0x1C, 0x11, 0xAB,
+			0x00
+		};
+		res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values));
+		if (res < 0)
+			return res;
+	}
+
+	res = tas5825m_set_page(dev, 0x03);
+	if (res < 0)
+		return res;
+
+	{
+		const uint8_t values[] = {
+			0xF0, 0x1C, 0x11, 0xAC, 0xF0, 0x1F, 0x11, 0xAD,
+			0x86, 0xA1, 0x01, 0xC2, 0x80, 0x27, 0x80, 0xE8,
+			0x60, 0x00, 0x00, 0x00, 0x84, 0x43, 0x03, 0x37,
+			0x80, 0x00, 0x00, 0x81, 0x0D, 0x00, 0x10, 0x20,
+			0x84, 0x51, 0x03, 0x3E, 0x08, 0x44, 0x26, 0x30,
+			0x84, 0xC3, 0x03, 0x47, 0x84, 0xC2, 0x40, 0xE0,
+			0x8C, 0xFF, 0x03, 0x23, 0xE0, 0x10, 0x11, 0xB3,
+			0xF0, 0x1C, 0x51, 0xB4, 0xF0, 0x1C, 0x51, 0xB5,
+			0xF0, 0x1C, 0x51, 0xB6, 0xF0, 0x1F, 0x51, 0xB7,
+			0x86, 0xA1, 0x01, 0xC6, 0x80, 0x27, 0x80, 0xEA,
+			0x84, 0x53, 0x03, 0x3E, 0x84, 0x82, 0x04, 0x05,
+			0x84, 0x51, 0x03, 0x75, 0xE2, 0x6B, 0xC0, 0x00,
+			0x80, 0x07, 0x00, 0x80, 0xE0, 0x80, 0x31, 0xB8,
+			0x84, 0x82, 0x40, 0xE0, 0xF0, 0x1C, 0x51, 0xB9,
+			0xF0, 0x1C, 0x51, 0xBA, 0xF0, 0x1C, 0x51, 0xBB,
+			0x00
+		};
+		res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values));
+		if (res < 0)
+			return res;
+	}
+
+	res = tas5825m_set_page(dev, 0x04);
+	if (res < 0)
+		return res;
+
+	{
+		const uint8_t values[] = {
+			0xF0, 0x1F, 0x51, 0xBC, 0x86, 0xA1, 0x01, 0xC5,
+			0x80, 0x27, 0x80, 0xEA, 0x60, 0x00, 0x00, 0x00,
+			0x80, 0x00, 0x00, 0x81, 0x84, 0xA1, 0x03, 0x4F,
+			0xE0, 0x80, 0xA0, 0x00, 0x01, 0x07, 0x11, 0x20,
+			0x08, 0x44, 0x26, 0x30, 0x08, 0x00, 0x98, 0x4A,
+			0x84, 0x53, 0x03, 0x75, 0x08, 0x00, 0x30, 0x48,
+			0x02, 0xCA, 0x00, 0x01, 0x08, 0x60, 0x26, 0x32,
+			0x84, 0x51, 0x03, 0x45, 0xE4, 0x10, 0x40, 0x00,
+			0x80, 0x40, 0xC0, 0x82, 0x84, 0xC2, 0x40, 0xE0,
+			0x84, 0xC3, 0x03, 0x5E, 0x08, 0x00, 0x50, 0x48,
+			0xE0, 0x10, 0x11, 0xBD, 0x02, 0xC2, 0x00, 0x02,
+			0x08, 0x60, 0x06, 0x12, 0x84, 0xD3, 0x03, 0x4F,
+			0xF0, 0x1C, 0x51, 0xBE, 0xF0, 0x1C, 0x51, 0xBF,
+			0xF0, 0x1C, 0x51, 0xC0, 0xF0, 0x1F, 0x51, 0xC1,
+			0x84, 0xA1, 0x03, 0x65, 0x80, 0x27, 0x80, 0xEA,
+			0x00
+		};
+		res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values));
+		if (res < 0)
+			return res;
+	}
+
+	res = tas5825m_set_page(dev, 0x05);
+	if (res < 0)
+		return res;
+
+	{
+		const uint8_t values[] = {
+			0xE0, 0x00, 0x00, 0x00, 0x80, 0x07, 0x00, 0x83,
+			0x08, 0x00, 0x98, 0x6B, 0x08, 0x00, 0x30, 0x68,
+			0x84, 0x53, 0x03, 0x45, 0x08, 0x60, 0x26, 0x33,
+			0x84, 0x51, 0x03, 0x25, 0xE4, 0x10, 0x60, 0x00,
+			0x80, 0x40, 0xC0, 0x81, 0x02, 0x70, 0x00, 0x7F,
+			0x08, 0x00, 0x50, 0x28, 0x08, 0x60, 0x06, 0x11,
+			0x84, 0xCB, 0x03, 0x65, 0xE0, 0x10, 0x51, 0xC4,
+			0x84, 0x80, 0x41, 0x00, 0x02, 0xA3, 0x00, 0x10,
+			0xE4, 0x00, 0x00, 0x00, 0x84, 0xD0, 0x04, 0x01,
+			0x84, 0xA2, 0x04, 0x03, 0x84, 0xD2, 0x50, 0x01,
+			0x84, 0x53, 0x03, 0x25, 0x80, 0x00, 0xC4, 0x04,
+			0x8F, 0x30, 0x00, 0x00, 0x88, 0x67, 0x03, 0x00,
+			0xE4, 0x00, 0x11, 0x9B, 0xEE, 0x64, 0x60, 0x00,
+			0x02, 0xD3, 0x00, 0x10, 0x88, 0x47, 0x00, 0x80,
+			0x10, 0x00, 0x18, 0x02, 0x86, 0xC1, 0x01, 0x9D,
+			0x00
+		};
+		res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values));
+		if (res < 0)
+			return res;
+	}
+
+	res = tas5825m_set_page(dev, 0x06);
+	if (res < 0)
+		return res;
+
+	{
+		const uint8_t values[] = {
+			0xE0, 0x10, 0x31, 0xC7, 0x86, 0xC9, 0x01, 0x9E,
+			0x80, 0x00, 0xC4, 0x02, 0x02, 0x50, 0x01, 0x9C,
+			0x00, 0xFF, 0x21, 0x65, 0x00, 0xFC, 0x00, 0x00,
+			0x02, 0x60, 0x00, 0x01, 0x02, 0x70, 0x00, 0x04,
+			0x84, 0xC8, 0x04, 0x10, 0x84, 0x41, 0x03, 0x67,
+			0x84, 0x51, 0x03, 0x6D, 0x84, 0xC0, 0x04, 0x02,
+			0x04, 0x80, 0x91, 0x20, 0x08, 0x60, 0x26, 0x30,
+			0x02, 0x78, 0x00, 0x03, 0x02, 0x68, 0x00, 0x02,
+			0x0D, 0x00, 0x10, 0x10, 0x08, 0x60, 0x06, 0x12,
+			0x84, 0x49, 0x03, 0x2F, 0xE0, 0x80, 0x71, 0xA9,
+			0x02, 0x28, 0x03, 0x55, 0x84, 0x82, 0x00, 0xE0,
+			0x84, 0x2A, 0x04, 0x00, 0xF0, 0x1C, 0x11, 0xAA,
+			0xF0, 0x1C, 0x11, 0xAB, 0xF0, 0x1C, 0x11, 0xAC,
+			0xF0, 0x1F, 0x11, 0xAD, 0x86, 0xA1, 0x01, 0xAE,
+			0x80, 0x27, 0x80, 0xE8, 0x84, 0x82, 0x04, 0x07,
+			0x00
+		};
+		res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values));
+		if (res < 0)
+			return res;
+	}
+
+	res = tas5825m_set_page(dev, 0x07);
+	if (res < 0)
+		return res;
+
+	{
+		const uint8_t values[] = {
+			0xE0, 0x80, 0x60, 0x00, 0x84, 0x82, 0x40, 0xE0,
+			0x84, 0x43, 0x03, 0x67, 0xF0, 0x1C, 0x51, 0xAF,
+			0xF0, 0x1C, 0x51, 0xB0, 0xF0, 0x1C, 0x51, 0xB1,
+			0xF0, 0x1F, 0x51, 0xB2, 0x02, 0x78, 0x00, 0x05,
+			0x80, 0x27, 0x80, 0xEA, 0x84, 0x82, 0x04, 0x08,
+			0x02, 0x70, 0x00, 0x06, 0x84, 0x53, 0x03, 0x6D,
+			0x84, 0x80, 0x04, 0x07, 0xE0, 0x00, 0x00, 0x82,
+			0xF0, 0x81, 0x00, 0x80, 0x80, 0x07, 0x12, 0xBC,
+			0x86, 0xA1, 0x01, 0x9F, 0xE2, 0x57, 0xA0, 0x00,
+			0x84, 0x82, 0x04, 0x09, 0x84, 0x82, 0x20, 0xE0,
+			0xF0, 0x1C, 0x31, 0xA0, 0xF0, 0x1C, 0x31, 0xA1,
+			0xF0, 0x1C, 0x31, 0xA2, 0xF0, 0x1F, 0x31, 0xA3,
+			0xE4, 0x00, 0x11, 0xA6, 0x80, 0x27, 0x80, 0xE1,
+			0xF4, 0x00, 0x11, 0xA4, 0xF4, 0x1D, 0x31, 0xA5,
+			0xF4, 0x1C, 0x31, 0xA7, 0xF4, 0x1F, 0x31, 0xA8,
+			0x00
+		};
+		res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values));
+		if (res < 0)
+			return res;
+	}
+
+	res = tas5825m_set_page(dev, 0x08);
+	if (res < 0)
+		return res;
+
+	{
+		const uint8_t values[] = {
+			0x02, 0x78, 0x00, 0x03, 0xE2, 0x6A, 0xF1, 0xC3,
+			0x80, 0x67, 0x80, 0xE9, 0x84, 0x4B, 0x03, 0x2F,
+			0x02, 0x70, 0x00, 0x04, 0x84, 0x59, 0x03, 0x3D,
+			0x80, 0x07, 0x00, 0x80, 0xE0, 0x00, 0x11, 0xA9,
+			0x84, 0x82, 0x60, 0xE0, 0x8E, 0xFC, 0x04, 0x10,
+			0xF0, 0x1C, 0x71, 0xAA, 0xF0, 0x1C, 0x71, 0xAB,
+			0xF0, 0x1C, 0x71, 0xAC, 0xF0, 0x1F, 0x71, 0xAD,
+			0x86, 0xA1, 0x01, 0xC2, 0x80, 0x27, 0x80, 0xEB,
+			0x60, 0x00, 0x00, 0x00, 0x84, 0x5B, 0x03, 0x3D,
+			0x80, 0x00, 0x00, 0x81, 0x0D, 0x00, 0x10, 0x20,
+			0x84, 0x59, 0x03, 0x3F, 0x08, 0x44, 0x26, 0x30,
+			0x84, 0xC3, 0x03, 0x57, 0x84, 0xC2, 0x60, 0xE0,
+			0xE0, 0x10, 0x11, 0xB3, 0xF0, 0x1C, 0x71, 0xB4,
+			0xF0, 0x1C, 0x71, 0xB5, 0xF0, 0x1C, 0x71, 0xB6,
+			0xF0, 0x1F, 0x71, 0xB7, 0x86, 0xA1, 0x01, 0xC6,
+			0x00
+		};
+		res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values));
+		if (res < 0)
+			return res;
+	}
+
+	res = tas5825m_set_page(dev, 0x09);
+	if (res < 0)
+		return res;
+
+	{
+		const uint8_t values[] = {
+			0x80, 0x27, 0x80, 0xEB, 0x84, 0x5B, 0x03, 0x3F,
+			0x84, 0x82, 0x04, 0x0D, 0x84, 0x41, 0x03, 0x76,
+			0xE2, 0x6B, 0xE0, 0x00, 0x80, 0x07, 0x00, 0x80,
+			0xE0, 0x81, 0x31, 0xB8, 0x84, 0x82, 0x00, 0xE0,
+			0xF0, 0x1C, 0x11, 0xB9, 0xF0, 0x1C, 0x11, 0xBA,
+			0xF0, 0x1C, 0x11, 0xBB, 0xF0, 0x1F, 0x11, 0xBC,
+			0x86, 0xA1, 0x01, 0xC5, 0x80, 0x27, 0x80, 0xE8,
+			0x60, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x81,
+			0x84, 0xA1, 0x03, 0x5D, 0xE0, 0x81, 0xA0, 0x00,
+			0x01, 0x07, 0x11, 0x20, 0x08, 0x44, 0x26, 0x30,
+			0x08, 0x00, 0x98, 0x4A, 0x84, 0x43, 0x03, 0x76,
+			0x08, 0x00, 0x30, 0x48, 0x02, 0xCA, 0x00, 0x01,
+			0x08, 0x60, 0x26, 0x32, 0x84, 0x41, 0x03, 0x46,
+			0xE4, 0x10, 0x40, 0x00, 0x80, 0x40, 0xC0, 0x82,
+			0x84, 0xC2, 0x00, 0xE0, 0x84, 0xC3, 0x03, 0x5F,
+			0x00
+		};
+		res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values));
+		if (res < 0)
+			return res;
+	}
+
+	res = tas5825m_set_page(dev, 0x0A);
+	if (res < 0)
+		return res;
+
+	{
+		const uint8_t values[] = {
+			0x08, 0x00, 0x50, 0x48, 0xE0, 0x10, 0x11, 0xBD,
+			0x02, 0xC2, 0x00, 0x02, 0x08, 0x60, 0x06, 0x12,
+			0x84, 0xD3, 0x03, 0x5D, 0xF0, 0x1C, 0x11, 0xBE,
+			0xF0, 0x1C, 0x11, 0xBF, 0xF0, 0x1C, 0x11, 0xC0,
+			0xF0, 0x1F, 0x11, 0xC1, 0x84, 0xA1, 0x03, 0x66,
+			0x80, 0x27, 0x80, 0xE8, 0xE0, 0x00, 0x00, 0x00,
+			0x80, 0x07, 0x00, 0x83, 0x08, 0x00, 0x98, 0x6B,
+			0x08, 0x00, 0x30, 0x68, 0x84, 0x43, 0x03, 0x46,
+			0x08, 0x60, 0x26, 0x33, 0x84, 0x51, 0x03, 0x26,
+			0xE4, 0x10, 0x60, 0x00, 0x80, 0x40, 0xC0, 0x81,
+			0x02, 0x70, 0x00, 0x7F, 0x08, 0x00, 0x50, 0x28,
+			0x08, 0x60, 0x06, 0x11, 0x8C, 0xFF, 0x03, 0x24,
+			0x84, 0xCB, 0x03, 0x66, 0xE0, 0x10, 0x51, 0xC4,
+			0x84, 0x80, 0x41, 0x00, 0x02, 0xA3, 0x00, 0x10,
+			0xE4, 0x00, 0x00, 0x00, 0x84, 0xD0, 0x04, 0x09,
+			0x00
+		};
+		res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values));
+		if (res < 0)
+			return res;
+	}
+
+	res = tas5825m_set_page(dev, 0x0B);
+	if (res < 0)
+		return res;
+
+	{
+		const uint8_t values[] = {
+			0x84, 0xA2, 0x04, 0x0B, 0x84, 0xD2, 0x50, 0x01,
+			0x84, 0x53, 0x03, 0x26, 0x80, 0x00, 0xC4, 0x0C,
+			0x8F, 0x30, 0x00, 0x00, 0x88, 0x67, 0x03, 0x00,
+			0xE4, 0x00, 0x11, 0x9B, 0xEE, 0x64, 0x80, 0x00,
+			0x02, 0xD3, 0x00, 0x10, 0x88, 0x47, 0x00, 0x80,
+			0x10, 0x00, 0x18, 0x02, 0x86, 0xC1, 0x01, 0x9D,
+			0xE0, 0x10, 0x31, 0xC7, 0x86, 0xC9, 0x01, 0x9E,
+			0x80, 0x00, 0xC4, 0x0A, 0x02, 0x50, 0x01, 0x9C,
+			0x00, 0xFF, 0x21, 0x65, 0x00, 0xFC, 0x00, 0x00,
+			0x02, 0x70, 0x00, 0x04, 0x02, 0x68, 0x00, 0x01,
+			0x02, 0x60, 0x00, 0x03, 0x02, 0x78, 0x00, 0x02,
+			0x84, 0x49, 0x03, 0x6E, 0x84, 0x41, 0x03, 0x6F,
+			0x84, 0xC8, 0x04, 0x10, 0x84, 0xC0, 0x04, 0x0A,
+			0x04, 0x81, 0x91, 0x20, 0x08, 0x60, 0x26, 0x30,
+			0x0D, 0x00, 0x10, 0x10, 0x08, 0x60, 0x06, 0x12,
+			0x00
+		};
+		res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values));
+		if (res < 0)
+			return res;
+	}
+
+	res = tas5825m_set_page(dev, 0x0C);
+	if (res < 0)
+		return res;
+
+	{
+		const uint8_t values[] = {
+			0x84, 0x00, 0x04, 0x06, 0xE0, 0x81, 0x71, 0xA9,
+			0x84, 0x82, 0x20, 0xE8, 0xF0, 0x1D, 0x31, 0xAA,
+			0xF0, 0x1D, 0x31, 0xAB, 0xF0, 0x1D, 0x31, 0xAC,
+			0xF0, 0x1C, 0x31, 0xAD, 0x86, 0xA1, 0x01, 0xAE,
+			0x80, 0x27, 0x80, 0xF9, 0x84, 0x82, 0x04, 0x0E,
+			0xE0, 0x81, 0x60, 0x00, 0x84, 0x82, 0x00, 0xE8,
+			0x84, 0x4B, 0x03, 0x6E, 0xF0, 0x1D, 0x11, 0xAF,
+			0xF0, 0x1D, 0x11, 0xB0, 0xF0, 0x1D, 0x11, 0xB1,
+			0xF0, 0x1C, 0x11, 0xB2, 0x02, 0xA3, 0x00, 0x1A,
+			0x80, 0x27, 0x80, 0xF8, 0x84, 0x82, 0x04, 0x0F,
+			0xE0, 0x81, 0xC0, 0x00, 0xF0, 0x81, 0xE0, 0x80,
+			0x84, 0x43, 0x03, 0x6F, 0x80, 0x07, 0x12, 0xBD,
+			0x02, 0xC0, 0x00, 0x00, 0x00, 0xFC, 0x50, 0x00,
+			0x8F, 0x00, 0x00, 0x11, 0x8F, 0x00, 0xFF, 0xFF,
+			0x84, 0x58, 0x04, 0x01, 0x84, 0xC2, 0x04, 0x00,
+			0x00
+		};
+		res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values));
+		if (res < 0)
+			return res;
+	}
+
+	res = tas5825m_set_page(dev, 0x0D);
+	if (res < 0)
+		return res;
+
+	{
+		const uint8_t values[] = {
+			0x02, 0xC2, 0x60, 0x00, 0x84, 0xA0, 0x61, 0x00,
+			0xE0, 0x20, 0x00, 0x00, 0x00, 0xFC, 0x00, 0x00,
+			0x40, 0x40, 0xA0, 0x00, 0x80, 0x00, 0xC0, 0x82,
+			0x08, 0xFC, 0x48, 0x3A, 0x08, 0xFC, 0x18, 0x50,
+			0x00, 0xFC, 0x00, 0x00, 0xE0, 0x10, 0x00, 0x00,
+			0x86, 0xA0, 0x41, 0x00, 0x40, 0x47, 0x20, 0x00,
+			0x80, 0x00, 0xC0, 0x83, 0x04, 0xE0, 0x3D, 0x1E,
+			0x04, 0x80, 0x11, 0xE0, 0x08, 0x44, 0x26, 0x33,
+			0x02, 0xCB, 0x00, 0x10, 0xE0, 0x10, 0x40, 0x83,
+			0x08, 0x00, 0x28, 0x21, 0x84, 0xCA, 0x61, 0x00,
+			0x80, 0x07, 0x00, 0x81, 0x0C, 0xE0, 0x2C, 0x09,
+			0x84, 0xCA, 0x21, 0x00, 0x00, 0xFC, 0x50, 0x00,
+			0x8F, 0x00, 0x00, 0x01, 0x00
+		};
+		res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values));
+		if (res < 0)
+			return res;
+	}
+
+	res = tas5825m_set_book(dev, 0x78);
+	if (res < 0)
+		return res;
+
+	res = tas5825m_set_page(dev, 0x18);
+	if (res < 0)
+		return res;
+
+	{
+		const uint8_t values[] = {
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00
+		};
+		res = tas5825m_write_block_at(dev, 0x30, values, ARRAY_SIZE(values));
+		if (res < 0)
+			return res;
+	}
+
+	res = tas5825m_set_book(dev, 0x78);
+	if (res < 0)
+		return res;
+
+	res = tas5825m_set_page(dev, 0x1B);
+	if (res < 0)
+		return res;
+
+	{
+		const uint8_t values[] = {
+			0x00, 0x00, 0x03, 0x80, 0x00, 0x00, 0x04, 0x00,
+			0x00, 0x00, 0x03, 0x28, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00
+		};
+		res = tas5825m_write_block_at(dev, 0x6C, values, ARRAY_SIZE(values));
+		if (res < 0)
+			return res;
+	}
+
+	res = tas5825m_set_page(dev, 0x1C);
+	if (res < 0)
+		return res;
+
+	{
+		const uint8_t values[] = {
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00
+		};
+		res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values));
+		if (res < 0)
+			return res;
+	}
+
+	res = tas5825m_set_book(dev, 0x78);
+	if (res < 0)
+		return res;
+
+	res = tas5825m_set_page(dev, 0x1C);
+	if (res < 0)
+		return res;
+
+	{
+		const uint8_t values[] = {
+			0x00, 0x00, 0x03, 0x30, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00
+		};
+		res = tas5825m_write_block_at(dev, 0x1C, values, ARRAY_SIZE(values));
+		if (res < 0)
+			return res;
+	}
+
+	res = tas5825m_set_book(dev, 0x78);
+	if (res < 0)
+		return res;
+
+	res = tas5825m_set_page(dev, 0x1C);
+	if (res < 0)
+		return res;
+
+	{
+		const uint8_t values[] = {
+			0x00, 0x00, 0x03, 0x38, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00
+		};
+		res = tas5825m_write_block_at(dev, 0x3C, values, ARRAY_SIZE(values));
+		if (res < 0)
+			return res;
+	}
+
+	res = tas5825m_set_book(dev, 0x78);
+	if (res < 0)
+		return res;
+
+	res = tas5825m_set_page(dev, 0x1C);
+	if (res < 0)
+		return res;
+
+	{
+		const uint8_t values[] = {
+			0x00, 0x00, 0x03, 0x40, 0x00, 0x00, 0x03, 0x48,
+			0x00, 0x00, 0x03, 0x50, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00
+		};
+		res = tas5825m_write_block_at(dev, 0x54, values, ARRAY_SIZE(values));
+		if (res < 0)
+			return res;
+	}
+
+	res = tas5825m_set_book(dev, 0x78);
+	if (res < 0)
+		return res;
+
+	res = tas5825m_set_page(dev, 0x1C);
+	if (res < 0)
+		return res;
+
+	{
+		const uint8_t values[] = {
+			0x00, 0x00, 0x03, 0x58, 0x00, 0x00, 0x03, 0x60,
+			0x00, 0x00, 0x00, 0x00, 0x00
+		};
+		res = tas5825m_write_block_at(dev, 0x74, values, ARRAY_SIZE(values));
+		if (res < 0)
+			return res;
+	}
+
+	res = tas5825m_set_page(dev, 0x1D);
+	if (res < 0)
+		return res;
+
+	{
+		const uint8_t values[] = {
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00
+		};
+		res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values));
+		if (res < 0)
+			return res;
+	}
+
+	res = tas5825m_set_book(dev, 0x78);
+	if (res < 0)
+		return res;
+
+	res = tas5825m_set_page(dev, 0x1D);
+	if (res < 0)
+		return res;
+
+	{
+		const uint8_t values[] = {
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00
+		};
+		res = tas5825m_write_block_at(dev, 0x1C, values, ARRAY_SIZE(values));
+		if (res < 0)
+			return res;
+	}
+
+	res = tas5825m_set_book(dev, 0x78);
+	if (res < 0)
+		return res;
+
+	res = tas5825m_set_page(dev, 0x1D);
+	if (res < 0)
+		return res;
+
+	{
+		const uint8_t values[] = {
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00
+		};
+		res = tas5825m_write_block_at(dev, 0x3C, values, ARRAY_SIZE(values));
+		if (res < 0)
+			return res;
+	}
+
+	res = tas5825m_set_page(dev, 0x1E);
+	if (res < 0)
+		return res;
+
+	{
+		const uint8_t values[] = {
+			0x00, 0x00, 0x00, 0x00, 0x00
+		};
+		res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values));
+		if (res < 0)
+			return res;
+	}
+
+	res = tas5825m_set_book(dev, 0x78);
+	if (res < 0)
+		return res;
+
+	res = tas5825m_set_page(dev, 0x1E);
+	if (res < 0)
+		return res;
+
+	{
+		const uint8_t values[] = {
+			0x00, 0x00, 0x03, 0x68, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00
+		};
+		res = tas5825m_write_block_at(dev, 0x0C, values, ARRAY_SIZE(values));
+		if (res < 0)
+			return res;
+	}
+
+	res = tas5825m_set_book(dev, 0x78);
+	if (res < 0)
+		return res;
+
+	res = tas5825m_set_page(dev, 0x1E);
+	if (res < 0)
+		return res;
+
+	{
+		const uint8_t values[] = {
+			0x00, 0x00, 0x03, 0x70, 0x00, 0x00, 0x03, 0x78,
+			0x00, 0x00, 0x04, 0x80, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00
+		};
+		res = tas5825m_write_block_at(dev, 0x24, values, ARRAY_SIZE(values));
+		if (res < 0)
+			return res;
+	}
+
+	res = tas5825m_set_book(dev, 0x78);
+	if (res < 0)
+		return res;
+
+	res = tas5825m_set_page(dev, 0x1E);
+	if (res < 0)
+		return res;
+
+	{
+		const uint8_t values[] = {
+			0x00, 0x00, 0x04, 0x88, 0x00, 0x00, 0x04, 0x90,
+			0x00
+		};
+		res = tas5825m_write_block_at(dev, 0x44, values, ARRAY_SIZE(values));
+		if (res < 0)
+			return res;
+	}
+
+	res = tas5825m_set_book(dev, 0x8C);
+	if (res < 0)
+		return res;
+
+	res = tas5825m_set_page(dev, 0x0E);
+	if (res < 0)
+		return res;
+
+	{
+		const uint8_t values[] = {
+			0x00, 0xA7, 0x26, 0x4A, 0x7F, 0xFF, 0xFF, 0xFF,
+			0x00, 0x20, 0xC4, 0x9C, 0x00, 0x20, 0xC4, 0x9C,
+			0x00, 0x00, 0x68, 0xDB, 0x00, 0x00, 0xD1, 0xB7,
+			0x00, 0x00, 0x68, 0xDB, 0x0F, 0xA4, 0xA8, 0xC1,
+			0xF8, 0x59, 0x7F, 0x63, 0x00
+		};
+		res = tas5825m_write_block_at(dev, 0x5C, values, ARRAY_SIZE(values));
+		if (res < 0)
+			return res;
+	}
+
+	res = tas5825m_set_page(dev, 0x0F);
+	if (res < 0)
+		return res;
+
+	{
+		const uint8_t values[] = {
+			0x07, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x2F, 0xB7, 0xE9,
+			0x00, 0x5F, 0x6F, 0xD2, 0x00, 0x2F, 0xB7, 0xE9,
+			0x0B, 0x1E, 0x4F, 0x76, 0xFC, 0x23, 0x05, 0x54,
+			0xFA, 0x41, 0x20, 0x5C, 0x0B, 0x7D, 0xBF, 0x48,
+			0xFA, 0x41, 0x20, 0x5C, 0x0B, 0x1E, 0x4F, 0x76,
+			0xFC, 0x23, 0x05, 0x54, 0x00, 0x04, 0x81, 0x6F,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x0F, 0x3F, 0xE5, 0xC9, 0xF8, 0xBB, 0x98, 0xC8,
+			0x07, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x04, 0x81, 0x6F,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x0F, 0x3F, 0xE5, 0xC9, 0xF8, 0xBB, 0x98, 0xC8,
+			0x00
+		};
+		res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values));
+		if (res < 0)
+			return res;
+	}
+
+	res = tas5825m_set_page(dev, 0x10);
+	if (res < 0)
+		return res;
+
+	{
+		const uint8_t values[] = {
+			0x00, 0x89, 0xA0, 0x27, 0x7F, 0xEC, 0x56, 0xD5,
+			0x7F, 0xFC, 0xB9, 0x23, 0x00, 0x89, 0xA0, 0x27,
+			0x7F, 0xEC, 0x56, 0xD5, 0x7F, 0xFC, 0xB9, 0x23,
+			0x00
+		};
+		res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values));
+		if (res < 0)
+			return res;
+	}
+
+	res = tas5825m_set_book(dev, 0x00);
+	if (res < 0)
+		return res;
+
+	res = tas5825m_write_at(dev, 0x40, 0x00);
+	if (res < 0)
+		return res;
+
+	res = tas5825m_set_book(dev, 0x00);
+	if (res < 0)
+		return res;
+
+	{
+		const uint8_t values[] = {
+			0x11, 0xFF, 0x00
+		};
+		res = tas5825m_write_block_at(dev, 0x7D, values, ARRAY_SIZE(values));
+		if (res < 0)
+			return res;
+	}
+
+	res = tas5825m_set_page(dev, 0x01);
+	if (res < 0)
+		return res;
+
+	res = tas5825m_write_at(dev, 0x51, 0x05);
+	if (res < 0)
+		return res;
+
+	res = tas5825m_set_page(dev, 0x02);
+	if (res < 0)
+		return res;
+
+	res = tas5825m_write_at(dev, 0x19, 0xDF);
+	if (res < 0)
+		return res;
+
+	res = tas5825m_set_book(dev, 0x00);
+	if (res < 0)
+		return res;
+
+	res = tas5825m_write_at(dev, 0x46, 0x11);
+	if (res < 0)
+		return res;
+
+	res = tas5825m_set_page(dev, 0x00);
+	if (res < 0)
+		return res;
+
+	res = tas5825m_write_at(dev, 0x02, 0x00);
+	if (res < 0)
+		return res;
+
+	res = tas5825m_write_at(dev, 0x53, 0x01);
+	if (res < 0)
+		return res;
+
+	res = tas5825m_write_at(dev, 0x54, 0x00);
+	if (res < 0)
+		return res;
+
+	res = tas5825m_set_book(dev, 0x00);
+	if (res < 0)
+		return res;
+
+	res = tas5825m_write_at(dev, 0x03, 0x02);
+	if (res < 0)
+		return res;
+
+	res = tas5825m_set_book(dev, 0x8C);
+	if (res < 0)
+		return res;
+
+	res = tas5825m_set_page(dev, 0x01);
+	if (res < 0)
+		return res;
+
+	{
+		const uint8_t values[] = {
+			0x00, 0x71, 0x94, 0x9A, 0x00
+		};
+		res = tas5825m_write_block_at(dev, 0x2C, values, ARRAY_SIZE(values));
+		if (res < 0)
+			return res;
+	}
+
+	res = tas5825m_set_page(dev, 0x0A);
+	if (res < 0)
+		return res;
+
+	{
+		const uint8_t values[] = {
+			0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00,
+			0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00
+		};
+		res = tas5825m_write_block_at(dev, 0x64, values, ARRAY_SIZE(values));
+		if (res < 0)
+			return res;
+	}
+
+	res = tas5825m_set_page(dev, 0x0B);
+	if (res < 0)
+		return res;
+
+	{
+		const uint8_t values[] = {
+			0x00, 0x80, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00,
+			0x00, 0x80, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x80, 0x00, 0x00, 0x00
+		};
+		res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values));
+		if (res < 0)
+			return res;
+	}
+
+	{
+		const uint8_t values[] = {
+			0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x57, 0x62, 0x00, 0x00, 0x00, 0x00,
+			0x00
+		};
+		res = tas5825m_write_block_at(dev, 0x28, values, ARRAY_SIZE(values));
+		if (res < 0)
+			return res;
+	}
+
+	res = tas5825m_set_page(dev, 0x0E);
+	if (res < 0)
+		return res;
+
+	{
+		const uint8_t values[] = {
+			0x00, 0x03, 0x69, 0xC5, 0x00, 0xFE, 0x16, 0xD5,
+			0x00, 0x22, 0x1D, 0x95, 0x00, 0x03, 0x69, 0xC5,
+			0x00
+		};
+		res = tas5825m_write_block_at(dev, 0x5C, values, ARRAY_SIZE(values));
+		if (res < 0)
+			return res;
+	}
+
+	res = tas5825m_set_page(dev, 0x0F);
+	if (res < 0)
+		return res;
+
+	{
+		const uint8_t values[] = {
+			0x7F, 0xF9, 0x2C, 0x60, 0x04, 0x90, 0xB5, 0x11,
+			0x00
+		};
+		res = tas5825m_write_block_at(dev, 0x5C, values, ARRAY_SIZE(values));
+		if (res < 0)
+			return res;
+	}
+
+	res = tas5825m_set_page(dev, 0x07);
+	if (res < 0)
+		return res;
+
+	{
+		const uint8_t values[] = {
+			0x00, 0x80, 0x00, 0x00, 0x00
+		};
+		res = tas5825m_write_block_at(dev, 0x64, values, ARRAY_SIZE(values));
+		if (res < 0)
+			return res;
+	}
+
+	{
+		const uint8_t values[] = {
+			0x40, 0x00, 0x00, 0x00, 0x40, 0x00, 0x00, 0x00,
+			0x00
+		};
+		res = tas5825m_write_block_at(dev, 0x6C, values, ARRAY_SIZE(values));
+		if (res < 0)
+			return res;
+	}
+
+	res = tas5825m_set_book(dev, 0xAA);
+	if (res < 0)
+		return res;
+
+	res = tas5825m_set_page(dev, 0x01);
+	if (res < 0)
+		return res;
+
+	{
+		const uint8_t values[] = {
+			0x07, 0xF6, 0x71, 0xFB, 0xF0, 0x5E, 0x48, 0xD6,
+			0x07, 0xAC, 0xA4, 0x5B, 0x0F, 0xA1, 0xB7, 0x2A,
+			0xF8, 0x5C, 0xE9, 0xAA, 0x08, 0x00, 0x00, 0x00,
+			0xF0, 0xBC, 0xDB, 0x13, 0x07, 0x4B, 0x87, 0x16,
+			0x0F, 0x43, 0x24, 0xED, 0xF8, 0xB4, 0x78, 0xEA,
+			0x08, 0x00, 0x00, 0x00, 0xF1, 0x2E, 0x37, 0x44,
+			0x06, 0xE6, 0xAE, 0x6C, 0x0E, 0xD1, 0xC8, 0xBC,
+			0xF9, 0x19, 0x51, 0x94, 0x08, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00
+		};
+		res = tas5825m_write_block_at(dev, 0x30, values, ARRAY_SIZE(values));
+		if (res < 0)
+			return res;
+	}
+
+	res = tas5825m_set_page(dev, 0x02);
+	if (res < 0)
+		return res;
+
+	{
+		const uint8_t values[] = {
+			0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x07, 0xE3, 0xB6, 0x0E,
+			0xF0, 0x38, 0x93, 0xE5, 0x07, 0xE3, 0xB6, 0x0E,
+			0x0F, 0xC7, 0x37, 0xC3, 0xF8, 0x38, 0x5F, 0x8D,
+			0x00
+		};
+		res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values));
+		if (res < 0)
+			return res;
+	}
+
+	res = tas5825m_set_page(dev, 0x03);
+	if (res < 0)
+		return res;
+
+	{
+		const uint8_t values[] = {
+			0x07, 0xE7, 0xF3, 0x30, 0xF0, 0x30, 0x19, 0xA1,
+			0x07, 0xE7, 0xF3, 0x30, 0x0F, 0xCF, 0xB1, 0xEB,
+			0xF8, 0x2F, 0xE5, 0x2D, 0x07, 0xEF, 0xD5, 0xCD,
+			0xF0, 0x20, 0x54, 0x66, 0x07, 0xEF, 0xD5, 0xCD,
+			0x0F, 0xDF, 0x76, 0xF1, 0xF8, 0x20, 0x1F, 0xBE,
+			0x07, 0xF8, 0xC3, 0x5E, 0xF0, 0x17, 0xB1, 0xEA,
+			0x07, 0xEF, 0xAD, 0x9B, 0x0F, 0xE8, 0x4E, 0x16,
+			0xF8, 0x17, 0x8F, 0x07, 0x08, 0x06, 0x13, 0x6A,
+			0xF0, 0x0B, 0x9D, 0x15, 0x07, 0xEE, 0x72, 0x7F,
+			0x0F, 0xF4, 0x3F, 0x7D, 0xF8, 0x0B, 0x56, 0xA9,
+			0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00
+		};
+		res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values));
+		if (res < 0)
+			return res;
+	}
+
+	res = tas5825m_set_page(dev, 0x04);
+	if (res < 0)
+		return res;
+
+	{
+		const uint8_t values[] = {
+			0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00
+		};
+		res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values));
+		if (res < 0)
+			return res;
+	}
+
+	res = tas5825m_set_page(dev, 0x05);
+	if (res < 0)
+		return res;
+
+	{
+		const uint8_t values[] = {
+			0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x07, 0xE3, 0xB6, 0x0E, 0xF0, 0x38, 0x93, 0xE5,
+			0x07, 0xE3, 0xB6, 0x0E, 0x0F, 0xC7, 0x37, 0xC3,
+			0xF8, 0x38, 0x5F, 0x8D, 0x07, 0xE7, 0xF3, 0x30,
+			0xF0, 0x30, 0x19, 0xA1, 0x07, 0xE7, 0xF3, 0x30,
+			0x0F, 0xCF, 0xB1, 0xEB, 0xF8, 0x2F, 0xE5, 0x2D,
+			0x07, 0xEF, 0xD5, 0xCD, 0xF0, 0x20, 0x54, 0x66,
+			0x07, 0xEF, 0xD5, 0xCD, 0x0F, 0xDF, 0x76, 0xF1,
+			0xF8, 0x20, 0x1F, 0xBE, 0x07, 0xF8, 0xC3, 0x5E,
+			0xF0, 0x17, 0xB1, 0xEA, 0x07, 0xEF, 0xAD, 0x9B,
+			0x0F, 0xE8, 0x4E, 0x16, 0xF8, 0x17, 0x8F, 0x07,
+			0x00
+		};
+		res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values));
+		if (res < 0)
+			return res;
+	}
+
+	res = tas5825m_set_page(dev, 0x06);
+	if (res < 0)
+		return res;
+
+	{
+		const uint8_t values[] = {
+			0x08, 0x06, 0x13, 0x6A, 0xF0, 0x0B, 0x9D, 0x15,
+			0x07, 0xEE, 0x72, 0x7F, 0x0F, 0xF4, 0x3F, 0x7D,
+			0xF8, 0x0B, 0x56, 0xA9, 0x08, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00
+		};
+		res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values));
+		if (res < 0)
+			return res;
+	}
+
+	res = tas5825m_set_page(dev, 0x0E);
+	if (res < 0)
+		return res;
+
+	{
+		const uint8_t values[] = {
+			0x00, 0x82, 0xB3, 0xD2, 0xFF, 0x00, 0xA4, 0x7A,
+			0x00, 0x7C, 0xCA, 0xB8, 0x0F, 0xF6, 0xBE, 0xFB,
+			0xF8, 0x09, 0x1E, 0x02, 0x00
+		};
+		res = tas5825m_write_block_at(dev, 0x6C, values, ARRAY_SIZE(values));
+		if (res < 0)
+			return res;
+	}
+
+	res = tas5825m_set_page(dev, 0x0F);
+	if (res < 0)
+		return res;
+
+	{
+		const uint8_t values[] = {
+			0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0xFF, 0xF4, 0x49, 0x81,
+			0xFF, 0xE8, 0x93, 0x02, 0xFF, 0xF4, 0x49, 0x81,
+			0x0D, 0x94, 0x7A, 0x64, 0xFA, 0x3C, 0xAB, 0xA1,
+			0x06, 0xD5, 0xF3, 0xB1, 0xF2, 0x54, 0x18, 0x9F,
+			0x06, 0xD5, 0xF3, 0xB1, 0x0D, 0x94, 0x7A, 0x64,
+			0xFA, 0x3C, 0xAB, 0xA1, 0x00, 0x00, 0x38, 0xE4,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x0F, 0xD5, 0x55, 0x55, 0xF8, 0x2A, 0x71, 0xC7,
+			0x00
+		};
+		res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values));
+		if (res < 0)
+			return res;
+	}
+
+	res = tas5825m_set_book(dev, 0x00);
+	if (res < 0)
+		return res;
+
+	res = tas5825m_write_at(dev, 0x30, 0x00);
+	if (res < 0)
+		return res;
+
+	res = tas5825m_write_at(dev, 0x60, 0x02);
+	if (res < 0)
+		return res;
+
+	res = tas5825m_write_at(dev, 0x62, 0x09);
+	if (res < 0)
+		return res;
+
+	res = tas5825m_write_at(dev, 0x4C, 0x40);
+	if (res < 0)
+		return res;
+
+	res = tas5825m_write_at(dev, 0x03, 0x03);
+	if (res < 0)
+		return res;
+
+	res = tas5825m_set_book(dev, 0x00);
+	if (res < 0)
+		return res;
+
+	res = tas5825m_write_at(dev, 0x78, 0x80);
+	if (res < 0)
+		return res;
+
+	res = tas5825m_set_book(dev, 0x00);
+	if (res < 0)
+		return res;
+
+	res = tas5825m_write_at(dev, 0x03, 0x02);
+	if (res < 0)
+		return res;
+
+	res = tas5825m_write_at(dev, 0x01, 0x11);
+	if (res < 0)
+		return res;
+
+	res = tas5825m_set_page(dev, 0x00);
+	if (res < 0)
+		return res;
+
+	res = tas5825m_set_page(dev, 0x00);
+	if (res < 0)
+		return res;
+
+	res = tas5825m_set_page(dev, 0x00);
+	if (res < 0)
+		return res;
+
+	res = tas5825m_set_page(dev, 0x00);
+	if (res < 0)
+		return res;
+
+	res = tas5825m_set_book(dev, 0x00);
+	if (res < 0)
+		return res;
+
+	res = tas5825m_write_at(dev, 0x03, 0x02);
+	if (res < 0)
+		return res;
+
+	mdelay(5);
+
+	res = tas5825m_set_page(dev, 0x00);
+	if (res < 0)
+		return res;
+
+	res = tas5825m_set_page(dev, 0x00);
+	if (res < 0)
+		return res;
+
+	res = tas5825m_set_page(dev, 0x00);
+	if (res < 0)
+		return res;
+
+	res = tas5825m_set_page(dev, 0x00);
+	if (res < 0)
+		return res;
+
+	res = tas5825m_set_book(dev, 0x00);
+	if (res < 0)
+		return res;
+
+	res = tas5825m_write_at(dev, 0x03, 0x12);
+	if (res < 0)
+		return res;
+
+	res = tas5825m_set_page(dev, 0x00);
+	if (res < 0)
+		return res;
+
+	res = tas5825m_set_page(dev, 0x00);
+	if (res < 0)
+		return res;
+
+	res = tas5825m_set_page(dev, 0x00);
+	if (res < 0)
+		return res;
+
+	res = tas5825m_set_page(dev, 0x00);
+	if (res < 0)
+		return res;
+
+	res = tas5825m_set_book(dev, 0x00);
+	if (res < 0)
+		return res;
+
+	res = tas5825m_write_at(dev, 0x48, 0x0C);
+	if (res < 0)
+		return res;
+
+	res = tas5825m_set_book(dev, 0x64);
+	if (res < 0)
+		return res;
+
+	res = tas5825m_set_page(dev, 0x01);
+	if (res < 0)
+		return res;
+
+	{
+		const uint8_t values[] = {
+			0x00, 0xFE, 0x00, 0x40, 0x00, 0xFC, 0x00, 0x00,
+			0x00, 0xFC, 0x00, 0x00, 0x00, 0xFC, 0x00, 0x00,
+			0x00, 0xFC, 0x00, 0x00, 0x00, 0xFC, 0x00, 0x00,
+			0x00, 0xFC, 0x00, 0x00, 0x00, 0xFC, 0x00, 0x00,
+			0x00, 0xFC, 0x50, 0x00, 0x00, 0xFC, 0x00, 0x00,
+			0x00, 0xFC, 0x00, 0x00, 0x00, 0xFC, 0x00, 0x00,
+			0x00, 0xFC, 0x00, 0x00, 0x00, 0xFC, 0x00, 0x00,
+			0x00, 0xFC, 0x00, 0x00, 0x00, 0xFC, 0x00, 0x00,
+			0x00, 0xFC, 0x00, 0x00, 0x00, 0xFC, 0x00, 0x00,
+			0x00, 0xFC, 0x00, 0x00, 0x00, 0xFC, 0x00, 0x00,
+			0x00, 0xFC, 0x00, 0x00, 0x00, 0xFC, 0x00, 0x00,
+			0x00, 0xFC, 0x00, 0x00, 0x00, 0xFC, 0x00, 0x00,
+			0x00, 0x82, 0x00, 0x93, 0x00, 0xFC, 0x00, 0x00,
+			0x8F, 0x00, 0xFF, 0xEF, 0x84, 0x49, 0x03, 0x27,
+			0x84, 0x02, 0x04, 0x06, 0x02, 0x60, 0x00, 0x01,
+			0x00
+		};
+		res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values));
+		if (res < 0)
+			return res;
+	}
+
+	res = tas5825m_set_page(dev, 0x02);
+	if (res < 0)
+		return res;
+
+	{
+		const uint8_t values[] = {
+			0x02, 0x70, 0x00, 0x06, 0x02, 0x78, 0x00, 0x05,
+			0x02, 0x68, 0x00, 0x02, 0x02, 0x28, 0x03, 0x4D,
+			0x84, 0x2A, 0x04, 0x00, 0xE2, 0x57, 0x91, 0x9F,
+			0x84, 0x82, 0x20, 0xE0, 0x84, 0x82, 0x04, 0x01,
+			0xF0, 0x1C, 0x31, 0xA0, 0xF0, 0x1C, 0x31, 0xA1,
+			0xF0, 0x1C, 0x31, 0xA2, 0xF0, 0x1F, 0x31, 0xA3,
+			0xE4, 0x00, 0x11, 0xA6, 0x80, 0x27, 0x80, 0xE1,
+			0xF4, 0x00, 0x11, 0xA4, 0xF4, 0x1D, 0x31, 0xA5,
+			0xF4, 0x1C, 0x31, 0xA7, 0xF4, 0x1F, 0x31, 0xA8,
+			0x02, 0x78, 0x00, 0x03, 0xE2, 0x68, 0xF1, 0xC3,
+			0x80, 0x67, 0x80, 0xE9, 0x84, 0x4B, 0x03, 0x27,
+			0x02, 0x70, 0x00, 0x04, 0x84, 0x41, 0x03, 0x37,
+			0x80, 0x07, 0x00, 0x80, 0xE0, 0x00, 0x11, 0xA9,
+			0x84, 0x82, 0x00, 0xE0, 0x8E, 0xFC, 0x04, 0x10,
+			0xF0, 0x1C, 0x11, 0xAA, 0xF0, 0x1C, 0x11, 0xAB,
+			0x00
+		};
+		res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values));
+		if (res < 0)
+			return res;
+	}
+
+	res = tas5825m_set_page(dev, 0x03);
+	if (res < 0)
+		return res;
+
+	{
+		const uint8_t values[] = {
+			0xF0, 0x1C, 0x11, 0xAC, 0xF0, 0x1F, 0x11, 0xAD,
+			0x86, 0xA1, 0x01, 0xC2, 0x80, 0x27, 0x80, 0xE8,
+			0x60, 0x00, 0x00, 0x00, 0x84, 0x43, 0x03, 0x37,
+			0x80, 0x00, 0x00, 0x81, 0x0D, 0x00, 0x10, 0x20,
+			0x84, 0x51, 0x03, 0x3E, 0x08, 0x44, 0x26, 0x30,
+			0x84, 0xC3, 0x03, 0x47, 0x84, 0xC2, 0x40, 0xE0,
+			0x8C, 0xFF, 0x03, 0x23, 0xE0, 0x10, 0x11, 0xB3,
+			0xF0, 0x1C, 0x51, 0xB4, 0xF0, 0x1C, 0x51, 0xB5,
+			0xF0, 0x1C, 0x51, 0xB6, 0xF0, 0x1F, 0x51, 0xB7,
+			0x86, 0xA1, 0x01, 0xC6, 0x80, 0x27, 0x80, 0xEA,
+			0x84, 0x53, 0x03, 0x3E, 0x84, 0x82, 0x04, 0x05,
+			0x84, 0x51, 0x03, 0x75, 0xE2, 0x6B, 0xC0, 0x00,
+			0x80, 0x07, 0x00, 0x80, 0xE0, 0x80, 0x31, 0xB8,
+			0x84, 0x82, 0x40, 0xE0, 0xF0, 0x1C, 0x51, 0xB9,
+			0xF0, 0x1C, 0x51, 0xBA, 0xF0, 0x1C, 0x51, 0xBB,
+			0x00
+		};
+		res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values));
+		if (res < 0)
+			return res;
+	}
+
+	res = tas5825m_set_page(dev, 0x04);
+	if (res < 0)
+		return res;
+
+	{
+		const uint8_t values[] = {
+			0xF0, 0x1F, 0x51, 0xBC, 0x86, 0xA1, 0x01, 0xC5,
+			0x80, 0x27, 0x80, 0xEA, 0x60, 0x00, 0x00, 0x00,
+			0x80, 0x00, 0x00, 0x81, 0x84, 0xA1, 0x03, 0x4F,
+			0xE0, 0x80, 0xA0, 0x00, 0x01, 0x07, 0x11, 0x20,
+			0x08, 0x44, 0x26, 0x30, 0x08, 0x00, 0x98, 0x4A,
+			0x84, 0x53, 0x03, 0x75, 0x08, 0x00, 0x30, 0x48,
+			0x02, 0xCA, 0x00, 0x01, 0x08, 0x60, 0x26, 0x32,
+			0x84, 0x51, 0x03, 0x45, 0xE4, 0x10, 0x40, 0x00,
+			0x80, 0x40, 0xC0, 0x82, 0x84, 0xC2, 0x40, 0xE0,
+			0x84, 0xC3, 0x03, 0x5E, 0x08, 0x00, 0x50, 0x48,
+			0xE0, 0x10, 0x11, 0xBD, 0x02, 0xC2, 0x00, 0x02,
+			0x08, 0x60, 0x06, 0x12, 0x84, 0xD3, 0x03, 0x4F,
+			0xF0, 0x1C, 0x51, 0xBE, 0xF0, 0x1C, 0x51, 0xBF,
+			0xF0, 0x1C, 0x51, 0xC0, 0xF0, 0x1F, 0x51, 0xC1,
+			0x84, 0xA1, 0x03, 0x65, 0x80, 0x27, 0x80, 0xEA,
+			0x00
+		};
+		res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values));
+		if (res < 0)
+			return res;
+	}
+
+	res = tas5825m_set_page(dev, 0x05);
+	if (res < 0)
+		return res;
+
+	{
+		const uint8_t values[] = {
+			0xE0, 0x00, 0x00, 0x00, 0x80, 0x07, 0x00, 0x83,
+			0x08, 0x00, 0x98, 0x6B, 0x08, 0x00, 0x30, 0x68,
+			0x84, 0x53, 0x03, 0x45, 0x08, 0x60, 0x26, 0x33,
+			0x84, 0x51, 0x03, 0x25, 0xE4, 0x10, 0x60, 0x00,
+			0x80, 0x40, 0xC0, 0x81, 0x02, 0x70, 0x00, 0x7F,
+			0x08, 0x00, 0x50, 0x28, 0x08, 0x60, 0x06, 0x11,
+			0x84, 0xCB, 0x03, 0x65, 0xE0, 0x10, 0x51, 0xC4,
+			0x84, 0x80, 0x41, 0x00, 0x02, 0xA3, 0x00, 0x10,
+			0xE4, 0x00, 0x00, 0x00, 0x84, 0xD0, 0x04, 0x01,
+			0x84, 0xA2, 0x04, 0x03, 0x84, 0xD2, 0x50, 0x01,
+			0x84, 0x53, 0x03, 0x25, 0x80, 0x00, 0xC4, 0x04,
+			0x8F, 0x30, 0x00, 0x00, 0x88, 0x67, 0x03, 0x00,
+			0xE4, 0x00, 0x11, 0x9B, 0xEE, 0x64, 0x60, 0x00,
+			0x02, 0xD3, 0x00, 0x10, 0x88, 0x47, 0x00, 0x80,
+			0x10, 0x00, 0x18, 0x02, 0x86, 0xC1, 0x01, 0x9D,
+			0x00
+		};
+		res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values));
+		if (res < 0)
+			return res;
+	}
+
+	res = tas5825m_set_page(dev, 0x06);
+	if (res < 0)
+		return res;
+
+	{
+		const uint8_t values[] = {
+			0xE0, 0x10, 0x31, 0xC7, 0x86, 0xC9, 0x01, 0x9E,
+			0x80, 0x00, 0xC4, 0x02, 0x02, 0x50, 0x01, 0x9C,
+			0x00, 0xFF, 0x21, 0x65, 0x00, 0xFC, 0x00, 0x00,
+			0x02, 0x60, 0x00, 0x01, 0x02, 0x70, 0x00, 0x04,
+			0x84, 0xC8, 0x04, 0x10, 0x84, 0x41, 0x03, 0x67,
+			0x84, 0x51, 0x03, 0x6D, 0x84, 0xC0, 0x04, 0x02,
+			0x04, 0x80, 0x91, 0x20, 0x08, 0x60, 0x26, 0x30,
+			0x02, 0x78, 0x00, 0x03, 0x02, 0x68, 0x00, 0x02,
+			0x0D, 0x00, 0x10, 0x10, 0x08, 0x60, 0x06, 0x12,
+			0x84, 0x49, 0x03, 0x2F, 0xE0, 0x80, 0x71, 0xA9,
+			0x02, 0x28, 0x03, 0x55, 0x84, 0x82, 0x00, 0xE0,
+			0x84, 0x2A, 0x04, 0x00, 0xF0, 0x1C, 0x11, 0xAA,
+			0xF0, 0x1C, 0x11, 0xAB, 0xF0, 0x1C, 0x11, 0xAC,
+			0xF0, 0x1F, 0x11, 0xAD, 0x86, 0xA1, 0x01, 0xAE,
+			0x80, 0x27, 0x80, 0xE8, 0x84, 0x82, 0x04, 0x07,
+			0x00
+		};
+		res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values));
+		if (res < 0)
+			return res;
+	}
+
+	res = tas5825m_set_page(dev, 0x07);
+	if (res < 0)
+		return res;
+
+	{
+		const uint8_t values[] = {
+			0xE0, 0x80, 0x60, 0x00, 0x84, 0x82, 0x40, 0xE0,
+			0x84, 0x43, 0x03, 0x67, 0xF0, 0x1C, 0x51, 0xAF,
+			0xF0, 0x1C, 0x51, 0xB0, 0xF0, 0x1C, 0x51, 0xB1,
+			0xF0, 0x1F, 0x51, 0xB2, 0x02, 0x78, 0x00, 0x05,
+			0x80, 0x27, 0x80, 0xEA, 0x84, 0x82, 0x04, 0x08,
+			0x02, 0x70, 0x00, 0x06, 0x84, 0x53, 0x03, 0x6D,
+			0x84, 0x80, 0x04, 0x07, 0xE0, 0x00, 0x00, 0x82,
+			0xF0, 0x81, 0x00, 0x80, 0x80, 0x07, 0x12, 0xBC,
+			0x86, 0xA1, 0x01, 0x9F, 0xE2, 0x57, 0xA0, 0x00,
+			0x84, 0x82, 0x04, 0x09, 0x84, 0x82, 0x20, 0xE0,
+			0xF0, 0x1C, 0x31, 0xA0, 0xF0, 0x1C, 0x31, 0xA1,
+			0xF0, 0x1C, 0x31, 0xA2, 0xF0, 0x1F, 0x31, 0xA3,
+			0xE4, 0x00, 0x11, 0xA6, 0x80, 0x27, 0x80, 0xE1,
+			0xF4, 0x00, 0x11, 0xA4, 0xF4, 0x1D, 0x31, 0xA5,
+			0xF4, 0x1C, 0x31, 0xA7, 0xF4, 0x1F, 0x31, 0xA8,
+			0x00
+		};
+		res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values));
+		if (res < 0)
+			return res;
+	}
+
+	res = tas5825m_set_page(dev, 0x08);
+	if (res < 0)
+		return res;
+
+	{
+		const uint8_t values[] = {
+			0x02, 0x78, 0x00, 0x03, 0xE2, 0x6A, 0xF1, 0xC3,
+			0x80, 0x67, 0x80, 0xE9, 0x84, 0x4B, 0x03, 0x2F,
+			0x02, 0x70, 0x00, 0x04, 0x84, 0x59, 0x03, 0x3D,
+			0x80, 0x07, 0x00, 0x80, 0xE0, 0x00, 0x11, 0xA9,
+			0x84, 0x82, 0x60, 0xE0, 0x8E, 0xFC, 0x04, 0x10,
+			0xF0, 0x1C, 0x71, 0xAA, 0xF0, 0x1C, 0x71, 0xAB,
+			0xF0, 0x1C, 0x71, 0xAC, 0xF0, 0x1F, 0x71, 0xAD,
+			0x86, 0xA1, 0x01, 0xC2, 0x80, 0x27, 0x80, 0xEB,
+			0x60, 0x00, 0x00, 0x00, 0x84, 0x5B, 0x03, 0x3D,
+			0x80, 0x00, 0x00, 0x81, 0x0D, 0x00, 0x10, 0x20,
+			0x84, 0x59, 0x03, 0x3F, 0x08, 0x44, 0x26, 0x30,
+			0x84, 0xC3, 0x03, 0x57, 0x84, 0xC2, 0x60, 0xE0,
+			0xE0, 0x10, 0x11, 0xB3, 0xF0, 0x1C, 0x71, 0xB4,
+			0xF0, 0x1C, 0x71, 0xB5, 0xF0, 0x1C, 0x71, 0xB6,
+			0xF0, 0x1F, 0x71, 0xB7, 0x86, 0xA1, 0x01, 0xC6,
+			0x00
+		};
+		res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values));
+		if (res < 0)
+			return res;
+	}
+
+	res = tas5825m_set_page(dev, 0x09);
+	if (res < 0)
+		return res;
+
+	{
+		const uint8_t values[] = {
+			0x80, 0x27, 0x80, 0xEB, 0x84, 0x5B, 0x03, 0x3F,
+			0x84, 0x82, 0x04, 0x0D, 0x84, 0x41, 0x03, 0x76,
+			0xE2, 0x6B, 0xE0, 0x00, 0x80, 0x07, 0x00, 0x80,
+			0xE0, 0x81, 0x31, 0xB8, 0x84, 0x82, 0x00, 0xE0,
+			0xF0, 0x1C, 0x11, 0xB9, 0xF0, 0x1C, 0x11, 0xBA,
+			0xF0, 0x1C, 0x11, 0xBB, 0xF0, 0x1F, 0x11, 0xBC,
+			0x86, 0xA1, 0x01, 0xC5, 0x80, 0x27, 0x80, 0xE8,
+			0x60, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x81,
+			0x84, 0xA1, 0x03, 0x5D, 0xE0, 0x81, 0xA0, 0x00,
+			0x01, 0x07, 0x11, 0x20, 0x08, 0x44, 0x26, 0x30,
+			0x08, 0x00, 0x98, 0x4A, 0x84, 0x43, 0x03, 0x76,
+			0x08, 0x00, 0x30, 0x48, 0x02, 0xCA, 0x00, 0x01,
+			0x08, 0x60, 0x26, 0x32, 0x84, 0x41, 0x03, 0x46,
+			0xE4, 0x10, 0x40, 0x00, 0x80, 0x40, 0xC0, 0x82,
+			0x84, 0xC2, 0x00, 0xE0, 0x84, 0xC3, 0x03, 0x5F,
+			0x00
+		};
+		res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values));
+		if (res < 0)
+			return res;
+	}
+
+	res = tas5825m_set_page(dev, 0x0A);
+	if (res < 0)
+		return res;
+
+	{
+		const uint8_t values[] = {
+			0x08, 0x00, 0x50, 0x48, 0xE0, 0x10, 0x11, 0xBD,
+			0x02, 0xC2, 0x00, 0x02, 0x08, 0x60, 0x06, 0x12,
+			0x84, 0xD3, 0x03, 0x5D, 0xF0, 0x1C, 0x11, 0xBE,
+			0xF0, 0x1C, 0x11, 0xBF, 0xF0, 0x1C, 0x11, 0xC0,
+			0xF0, 0x1F, 0x11, 0xC1, 0x84, 0xA1, 0x03, 0x66,
+			0x80, 0x27, 0x80, 0xE8, 0xE0, 0x00, 0x00, 0x00,
+			0x80, 0x07, 0x00, 0x83, 0x08, 0x00, 0x98, 0x6B,
+			0x08, 0x00, 0x30, 0x68, 0x84, 0x43, 0x03, 0x46,
+			0x08, 0x60, 0x26, 0x33, 0x84, 0x51, 0x03, 0x26,
+			0xE4, 0x10, 0x60, 0x00, 0x80, 0x40, 0xC0, 0x81,
+			0x02, 0x70, 0x00, 0x7F, 0x08, 0x00, 0x50, 0x28,
+			0x08, 0x60, 0x06, 0x11, 0x8C, 0xFF, 0x03, 0x24,
+			0x84, 0xCB, 0x03, 0x66, 0xE0, 0x10, 0x51, 0xC4,
+			0x84, 0x80, 0x41, 0x00, 0x02, 0xA3, 0x00, 0x10,
+			0xE4, 0x00, 0x00, 0x00, 0x84, 0xD0, 0x04, 0x09,
+			0x00
+		};
+		res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values));
+		if (res < 0)
+			return res;
+	}
+
+	res = tas5825m_set_page(dev, 0x0B);
+	if (res < 0)
+		return res;
+
+	{
+		const uint8_t values[] = {
+			0x84, 0xA2, 0x04, 0x0B, 0x84, 0xD2, 0x50, 0x01,
+			0x84, 0x53, 0x03, 0x26, 0x80, 0x00, 0xC4, 0x0C,
+			0x8F, 0x30, 0x00, 0x00, 0x88, 0x67, 0x03, 0x00,
+			0xE4, 0x00, 0x11, 0x9B, 0xEE, 0x64, 0x80, 0x00,
+			0x02, 0xD3, 0x00, 0x10, 0x88, 0x47, 0x00, 0x80,
+			0x10, 0x00, 0x18, 0x02, 0x86, 0xC1, 0x01, 0x9D,
+			0xE0, 0x10, 0x31, 0xC7, 0x86, 0xC9, 0x01, 0x9E,
+			0x80, 0x00, 0xC4, 0x0A, 0x02, 0x50, 0x01, 0x9C,
+			0x00, 0xFF, 0x21, 0x65, 0x00, 0xFC, 0x00, 0x00,
+			0x02, 0x70, 0x00, 0x04, 0x02, 0x68, 0x00, 0x01,
+			0x02, 0x60, 0x00, 0x03, 0x02, 0x78, 0x00, 0x02,
+			0x84, 0x49, 0x03, 0x6E, 0x84, 0x41, 0x03, 0x6F,
+			0x84, 0xC8, 0x04, 0x10, 0x84, 0xC0, 0x04, 0x0A,
+			0x04, 0x81, 0x91, 0x20, 0x08, 0x60, 0x26, 0x30,
+			0x0D, 0x00, 0x10, 0x10, 0x08, 0x60, 0x06, 0x12,
+			0x00
+		};
+		res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values));
+		if (res < 0)
+			return res;
+	}
+
+	res = tas5825m_set_page(dev, 0x0C);
+	if (res < 0)
+		return res;
+
+	{
+		const uint8_t values[] = {
+			0x84, 0x00, 0x04, 0x06, 0xE0, 0x81, 0x71, 0xA9,
+			0x84, 0x82, 0x20, 0xE8, 0xF0, 0x1D, 0x31, 0xAA,
+			0xF0, 0x1D, 0x31, 0xAB, 0xF0, 0x1D, 0x31, 0xAC,
+			0xF0, 0x1C, 0x31, 0xAD, 0x86, 0xA1, 0x01, 0xAE,
+			0x80, 0x27, 0x80, 0xF9, 0x84, 0x82, 0x04, 0x0E,
+			0xE0, 0x81, 0x60, 0x00, 0x84, 0x82, 0x00, 0xE8,
+			0x84, 0x4B, 0x03, 0x6E, 0xF0, 0x1D, 0x11, 0xAF,
+			0xF0, 0x1D, 0x11, 0xB0, 0xF0, 0x1D, 0x11, 0xB1,
+			0xF0, 0x1C, 0x11, 0xB2, 0x02, 0xA3, 0x00, 0x1A,
+			0x80, 0x27, 0x80, 0xF8, 0x84, 0x82, 0x04, 0x0F,
+			0xE0, 0x81, 0xC0, 0x00, 0xF0, 0x81, 0xE0, 0x80,
+			0x84, 0x43, 0x03, 0x6F, 0x80, 0x07, 0x12, 0xBD,
+			0x02, 0xC0, 0x00, 0x00, 0x00, 0xFC, 0x50, 0x00,
+			0x8F, 0x00, 0x00, 0x11, 0x8F, 0x00, 0xFF, 0xFF,
+			0x84, 0x58, 0x04, 0x01, 0x84, 0xC2, 0x04, 0x00,
+			0x00
+		};
+		res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values));
+		if (res < 0)
+			return res;
+	}
+
+	res = tas5825m_set_page(dev, 0x0D);
+	if (res < 0)
+		return res;
+
+	{
+		const uint8_t values[] = {
+			0x02, 0xC2, 0x60, 0x00, 0x84, 0xA0, 0x61, 0x00,
+			0xE0, 0x20, 0x00, 0x00, 0x00, 0xFC, 0x00, 0x00,
+			0x40, 0x40, 0xA0, 0x00, 0x80, 0x00, 0xC0, 0x82,
+			0x08, 0xFC, 0x48, 0x3A, 0x08, 0xFC, 0x18, 0x50,
+			0x00, 0xFC, 0x00, 0x00, 0xE0, 0x10, 0x00, 0x00,
+			0x86, 0xA0, 0x41, 0x00, 0x40, 0x47, 0x20, 0x00,
+			0x80, 0x00, 0xC0, 0x83, 0x04, 0xE0, 0x3D, 0x1E,
+			0x04, 0x80, 0x11, 0xE0, 0x08, 0x44, 0x26, 0x33,
+			0x02, 0xCB, 0x00, 0x10, 0xE0, 0x10, 0x40, 0x83,
+			0x08, 0x00, 0x28, 0x21, 0x84, 0xCA, 0x61, 0x00,
+			0x80, 0x07, 0x00, 0x81, 0x0C, 0xE0, 0x2C, 0x09,
+			0x84, 0xCA, 0x21, 0x00, 0x00, 0xFC, 0x50, 0x00,
+			0x8F, 0x00, 0x00, 0x01, 0x00
+		};
+		res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values));
+		if (res < 0)
+			return res;
+	}
+
+	res = tas5825m_set_book(dev, 0x78);
+	if (res < 0)
+		return res;
+
+	res = tas5825m_set_page(dev, 0x18);
+	if (res < 0)
+		return res;
+
+	{
+		const uint8_t values[] = {
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00
+		};
+		res = tas5825m_write_block_at(dev, 0x30, values, ARRAY_SIZE(values));
+		if (res < 0)
+			return res;
+	}
+
+	res = tas5825m_set_book(dev, 0x78);
+	if (res < 0)
+		return res;
+
+	res = tas5825m_set_page(dev, 0x1B);
+	if (res < 0)
+		return res;
+
+	{
+		const uint8_t values[] = {
+			0x00, 0x00, 0x03, 0x80, 0x00, 0x00, 0x04, 0x00,
+			0x00, 0x00, 0x03, 0x28, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00
+		};
+		res = tas5825m_write_block_at(dev, 0x6C, values, ARRAY_SIZE(values));
+		if (res < 0)
+			return res;
+	}
+
+	res = tas5825m_set_page(dev, 0x1C);
+	if (res < 0)
+		return res;
+
+	{
+		const uint8_t values[] = {
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00
+		};
+		res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values));
+		if (res < 0)
+			return res;
+	}
+
+	res = tas5825m_set_book(dev, 0x78);
+	if (res < 0)
+		return res;
+
+	res = tas5825m_set_page(dev, 0x1C);
+	if (res < 0)
+		return res;
+
+	{
+		const uint8_t values[] = {
+			0x00, 0x00, 0x03, 0x30, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00
+		};
+		res = tas5825m_write_block_at(dev, 0x1C, values, ARRAY_SIZE(values));
+		if (res < 0)
+			return res;
+	}
+
+	res = tas5825m_set_book(dev, 0x78);
+	if (res < 0)
+		return res;
+
+	res = tas5825m_set_page(dev, 0x1C);
+	if (res < 0)
+		return res;
+
+	{
+		const uint8_t values[] = {
+			0x00, 0x00, 0x03, 0x38, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00
+		};
+		res = tas5825m_write_block_at(dev, 0x3C, values, ARRAY_SIZE(values));
+		if (res < 0)
+			return res;
+	}
+
+	res = tas5825m_set_book(dev, 0x78);
+	if (res < 0)
+		return res;
+
+	res = tas5825m_set_page(dev, 0x1C);
+	if (res < 0)
+		return res;
+
+	{
+		const uint8_t values[] = {
+			0x00, 0x00, 0x03, 0x40, 0x00, 0x00, 0x03, 0x48,
+			0x00, 0x00, 0x03, 0x50, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00
+		};
+		res = tas5825m_write_block_at(dev, 0x54, values, ARRAY_SIZE(values));
+		if (res < 0)
+			return res;
+	}
+
+	res = tas5825m_set_book(dev, 0x78);
+	if (res < 0)
+		return res;
+
+	res = tas5825m_set_page(dev, 0x1C);
+	if (res < 0)
+		return res;
+
+	{
+		const uint8_t values[] = {
+			0x00, 0x00, 0x03, 0x58, 0x00, 0x00, 0x03, 0x60,
+			0x00, 0x00, 0x00, 0x00, 0x00
+		};
+		res = tas5825m_write_block_at(dev, 0x74, values, ARRAY_SIZE(values));
+		if (res < 0)
+			return res;
+	}
+
+	res = tas5825m_set_page(dev, 0x1D);
+	if (res < 0)
+		return res;
+
+	{
+		const uint8_t values[] = {
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00
+		};
+		res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values));
+		if (res < 0)
+			return res;
+	}
+
+	res = tas5825m_set_book(dev, 0x78);
+	if (res < 0)
+		return res;
+
+	res = tas5825m_set_page(dev, 0x1D);
+	if (res < 0)
+		return res;
+
+	{
+		const uint8_t values[] = {
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00
+		};
+		res = tas5825m_write_block_at(dev, 0x1C, values, ARRAY_SIZE(values));
+		if (res < 0)
+			return res;
+	}
+
+	res = tas5825m_set_book(dev, 0x78);
+	if (res < 0)
+		return res;
+
+	res = tas5825m_set_page(dev, 0x1D);
+	if (res < 0)
+		return res;
+
+	{
+		const uint8_t values[] = {
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00
+		};
+		res = tas5825m_write_block_at(dev, 0x3C, values, ARRAY_SIZE(values));
+		if (res < 0)
+			return res;
+	}
+
+	res = tas5825m_set_page(dev, 0x1E);
+	if (res < 0)
+		return res;
+
+	{
+		const uint8_t values[] = {
+			0x00, 0x00, 0x00, 0x00, 0x00
+		};
+		res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values));
+		if (res < 0)
+			return res;
+	}
+
+	res = tas5825m_set_book(dev, 0x78);
+	if (res < 0)
+		return res;
+
+	res = tas5825m_set_page(dev, 0x1E);
+	if (res < 0)
+		return res;
+
+	{
+		const uint8_t values[] = {
+			0x00, 0x00, 0x03, 0x68, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00
+		};
+		res = tas5825m_write_block_at(dev, 0x0C, values, ARRAY_SIZE(values));
+		if (res < 0)
+			return res;
+	}
+
+	res = tas5825m_set_book(dev, 0x78);
+	if (res < 0)
+		return res;
+
+	res = tas5825m_set_page(dev, 0x1E);
+	if (res < 0)
+		return res;
+
+	{
+		const uint8_t values[] = {
+			0x00, 0x00, 0x03, 0x70, 0x00, 0x00, 0x03, 0x78,
+			0x00, 0x00, 0x04, 0x80, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00
+		};
+		res = tas5825m_write_block_at(dev, 0x24, values, ARRAY_SIZE(values));
+		if (res < 0)
+			return res;
+	}
+
+	res = tas5825m_set_book(dev, 0x78);
+	if (res < 0)
+		return res;
+
+	res = tas5825m_set_page(dev, 0x1E);
+	if (res < 0)
+		return res;
+
+	{
+		const uint8_t values[] = {
+			0x00, 0x00, 0x04, 0x88, 0x00, 0x00, 0x04, 0x90,
+			0x00
+		};
+		res = tas5825m_write_block_at(dev, 0x44, values, ARRAY_SIZE(values));
+		if (res < 0)
+			return res;
+	}
+
+	res = tas5825m_set_book(dev, 0x8C);
+	if (res < 0)
+		return res;
+
+	res = tas5825m_set_page(dev, 0x0E);
+	if (res < 0)
+		return res;
+
+	{
+		const uint8_t values[] = {
+			0x00, 0xA7, 0x26, 0x4A, 0x7F, 0xFF, 0xFF, 0xFF,
+			0x00, 0x20, 0xC4, 0x9C, 0x00, 0x20, 0xC4, 0x9C,
+			0x00, 0x00, 0x68, 0xDB, 0x00, 0x00, 0xD1, 0xB7,
+			0x00, 0x00, 0x68, 0xDB, 0x0F, 0xA4, 0xA8, 0xC1,
+			0xF8, 0x59, 0x7F, 0x63, 0x00
+		};
+		res = tas5825m_write_block_at(dev, 0x5C, values, ARRAY_SIZE(values));
+		if (res < 0)
+			return res;
+	}
+
+	res = tas5825m_set_page(dev, 0x0F);
+	if (res < 0)
+		return res;
+
+	{
+		const uint8_t values[] = {
+			0x07, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x2F, 0xB7, 0xE9,
+			0x00, 0x5F, 0x6F, 0xD2, 0x00, 0x2F, 0xB7, 0xE9,
+			0x0B, 0x1E, 0x4F, 0x76, 0xFC, 0x23, 0x05, 0x54,
+			0xFA, 0x41, 0x20, 0x5C, 0x0B, 0x7D, 0xBF, 0x48,
+			0xFA, 0x41, 0x20, 0x5C, 0x0B, 0x1E, 0x4F, 0x76,
+			0xFC, 0x23, 0x05, 0x54, 0x00, 0x04, 0x81, 0x6F,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x0F, 0x3F, 0xE5, 0xC9, 0xF8, 0xBB, 0x98, 0xC8,
+			0x07, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x04, 0x81, 0x6F,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x0F, 0x3F, 0xE5, 0xC9, 0xF8, 0xBB, 0x98, 0xC8,
+			0x00
+		};
+		res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values));
+		if (res < 0)
+			return res;
+	}
+
+	res = tas5825m_set_page(dev, 0x10);
+	if (res < 0)
+		return res;
+
+	{
+		const uint8_t values[] = {
+			0x00, 0x89, 0xA0, 0x27, 0x7F, 0xEC, 0x56, 0xD5,
+			0x7F, 0xFC, 0xB9, 0x23, 0x00, 0x89, 0xA0, 0x27,
+			0x7F, 0xEC, 0x56, 0xD5, 0x7F, 0xFC, 0xB9, 0x23,
+			0x00
+		};
+		res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values));
+		if (res < 0)
+			return res;
+	}
+
+	res = tas5825m_set_book(dev, 0x00);
+	if (res < 0)
+		return res;
+
+	res = tas5825m_write_at(dev, 0x40, 0x00);
+	if (res < 0)
+		return res;
+
+	res = tas5825m_set_book(dev, 0x00);
+	if (res < 0)
+		return res;
+
+	{
+		const uint8_t values[] = {
+			0x11, 0xFF, 0x00
+		};
+		res = tas5825m_write_block_at(dev, 0x7D, values, ARRAY_SIZE(values));
+		if (res < 0)
+			return res;
+	}
+
+	res = tas5825m_set_page(dev, 0x01);
+	if (res < 0)
+		return res;
+
+	res = tas5825m_write_at(dev, 0x51, 0x05);
+	if (res < 0)
+		return res;
+
+	res = tas5825m_set_page(dev, 0x02);
+	if (res < 0)
+		return res;
+
+	res = tas5825m_write_at(dev, 0x19, 0xDF);
+	if (res < 0)
+		return res;
+
+	res = tas5825m_set_book(dev, 0x00);
+	if (res < 0)
+		return res;
+
+	res = tas5825m_write_at(dev, 0x46, 0x11);
+	if (res < 0)
+		return res;
+
+	res = tas5825m_set_page(dev, 0x00);
+	if (res < 0)
+		return res;
+
+	res = tas5825m_write_at(dev, 0x02, 0x00);
+	if (res < 0)
+		return res;
+
+	res = tas5825m_write_at(dev, 0x53, 0x01);
+	if (res < 0)
+		return res;
+
+	res = tas5825m_write_at(dev, 0x54, 0x00);
+	if (res < 0)
+		return res;
+
+	res = tas5825m_set_book(dev, 0x00);
+	if (res < 0)
+		return res;
+
+	res = tas5825m_write_at(dev, 0x03, 0x02);
+	if (res < 0)
+		return res;
+
+	res = tas5825m_set_book(dev, 0x8C);
+	if (res < 0)
+		return res;
+
+	res = tas5825m_set_page(dev, 0x01);
+	if (res < 0)
+		return res;
+
+	{
+		const uint8_t values[] = {
+			0x00, 0x71, 0x94, 0x9A, 0x00
+		};
+		res = tas5825m_write_block_at(dev, 0x2C, values, ARRAY_SIZE(values));
+		if (res < 0)
+			return res;
+	}
+
+	res = tas5825m_set_page(dev, 0x0A);
+	if (res < 0)
+		return res;
+
+	{
+		const uint8_t values[] = {
+			0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00,
+			0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00
+		};
+		res = tas5825m_write_block_at(dev, 0x64, values, ARRAY_SIZE(values));
+		if (res < 0)
+			return res;
+	}
+
+	res = tas5825m_set_page(dev, 0x0B);
+	if (res < 0)
+		return res;
+
+	{
+		const uint8_t values[] = {
+			0x00, 0x80, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00,
+			0x00, 0x80, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x80, 0x00, 0x00, 0x00
+		};
+		res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values));
+		if (res < 0)
+			return res;
+	}
+
+	{
+		const uint8_t values[] = {
+			0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x57, 0x62, 0x00, 0x00, 0x00, 0x00,
+			0x00
+		};
+		res = tas5825m_write_block_at(dev, 0x28, values, ARRAY_SIZE(values));
+		if (res < 0)
+			return res;
+	}
+
+	res = tas5825m_set_page(dev, 0x0E);
+	if (res < 0)
+		return res;
+
+	{
+		const uint8_t values[] = {
+			0x00, 0x03, 0x69, 0xC5, 0x00, 0xFE, 0x16, 0xD5,
+			0x00, 0x22, 0x1D, 0x95, 0x00, 0x03, 0x69, 0xC5,
+			0x00
+		};
+		res = tas5825m_write_block_at(dev, 0x5C, values, ARRAY_SIZE(values));
+		if (res < 0)
+			return res;
+	}
+
+	res = tas5825m_set_page(dev, 0x0F);
+	if (res < 0)
+		return res;
+
+	{
+		const uint8_t values[] = {
+			0x7F, 0xF9, 0x2C, 0x60, 0x04, 0x90, 0xB5, 0x11,
+			0x00
+		};
+		res = tas5825m_write_block_at(dev, 0x5C, values, ARRAY_SIZE(values));
+		if (res < 0)
+			return res;
+	}
+
+	res = tas5825m_set_page(dev, 0x07);
+	if (res < 0)
+		return res;
+
+	{
+		const uint8_t values[] = {
+			0x00, 0x80, 0x00, 0x00, 0x00
+		};
+		res = tas5825m_write_block_at(dev, 0x64, values, ARRAY_SIZE(values));
+		if (res < 0)
+			return res;
+	}
+
+	{
+		const uint8_t values[] = {
+			0x40, 0x00, 0x00, 0x00, 0x40, 0x00, 0x00, 0x00,
+			0x00
+		};
+		res = tas5825m_write_block_at(dev, 0x6C, values, ARRAY_SIZE(values));
+		if (res < 0)
+			return res;
+	}
+
+	res = tas5825m_set_book(dev, 0xAA);
+	if (res < 0)
+		return res;
+
+	res = tas5825m_set_page(dev, 0x01);
+	if (res < 0)
+		return res;
+
+	{
+		const uint8_t values[] = {
+			0x07, 0xF6, 0x71, 0xFB, 0xF0, 0x5E, 0x48, 0xD6,
+			0x07, 0xAC, 0xA4, 0x5B, 0x0F, 0xA1, 0xB7, 0x2A,
+			0xF8, 0x5C, 0xE9, 0xAA, 0x08, 0x00, 0x00, 0x00,
+			0xF0, 0xBC, 0xDB, 0x13, 0x07, 0x4B, 0x87, 0x16,
+			0x0F, 0x43, 0x24, 0xED, 0xF8, 0xB4, 0x78, 0xEA,
+			0x08, 0x00, 0x00, 0x00, 0xF1, 0x2E, 0x37, 0x44,
+			0x06, 0xE6, 0xAE, 0x6C, 0x0E, 0xD1, 0xC8, 0xBC,
+			0xF9, 0x19, 0x51, 0x94, 0x08, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00
+		};
+		res = tas5825m_write_block_at(dev, 0x30, values, ARRAY_SIZE(values));
+		if (res < 0)
+			return res;
+	}
+
+	res = tas5825m_set_page(dev, 0x02);
+	if (res < 0)
+		return res;
+
+	{
+		const uint8_t values[] = {
+			0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x07, 0xE3, 0xB6, 0x0E,
+			0xF0, 0x38, 0x93, 0xE5, 0x07, 0xE3, 0xB6, 0x0E,
+			0x0F, 0xC7, 0x37, 0xC3, 0xF8, 0x38, 0x5F, 0x8D,
+			0x00
+		};
+		res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values));
+		if (res < 0)
+			return res;
+	}
+
+	res = tas5825m_set_page(dev, 0x03);
+	if (res < 0)
+		return res;
+
+	{
+		const uint8_t values[] = {
+			0x07, 0xE7, 0xF3, 0x30, 0xF0, 0x30, 0x19, 0xA1,
+			0x07, 0xE7, 0xF3, 0x30, 0x0F, 0xCF, 0xB1, 0xEB,
+			0xF8, 0x2F, 0xE5, 0x2D, 0x07, 0xEF, 0xD5, 0xCD,
+			0xF0, 0x20, 0x54, 0x66, 0x07, 0xEF, 0xD5, 0xCD,
+			0x0F, 0xDF, 0x76, 0xF1, 0xF8, 0x20, 0x1F, 0xBE,
+			0x07, 0xF8, 0xC3, 0x5E, 0xF0, 0x17, 0xB1, 0xEA,
+			0x07, 0xEF, 0xAD, 0x9B, 0x0F, 0xE8, 0x4E, 0x16,
+			0xF8, 0x17, 0x8F, 0x07, 0x08, 0x06, 0x13, 0x6A,
+			0xF0, 0x0B, 0x9D, 0x15, 0x07, 0xEE, 0x72, 0x7F,
+			0x0F, 0xF4, 0x3F, 0x7D, 0xF8, 0x0B, 0x56, 0xA9,
+			0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00
+		};
+		res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values));
+		if (res < 0)
+			return res;
+	}
+
+	res = tas5825m_set_page(dev, 0x04);
+	if (res < 0)
+		return res;
+
+	{
+		const uint8_t values[] = {
+			0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00
+		};
+		res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values));
+		if (res < 0)
+			return res;
+	}
+
+	res = tas5825m_set_page(dev, 0x05);
+	if (res < 0)
+		return res;
+
+	{
+		const uint8_t values[] = {
+			0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x07, 0xE3, 0xB6, 0x0E, 0xF0, 0x38, 0x93, 0xE5,
+			0x07, 0xE3, 0xB6, 0x0E, 0x0F, 0xC7, 0x37, 0xC3,
+			0xF8, 0x38, 0x5F, 0x8D, 0x07, 0xE7, 0xF3, 0x30,
+			0xF0, 0x30, 0x19, 0xA1, 0x07, 0xE7, 0xF3, 0x30,
+			0x0F, 0xCF, 0xB1, 0xEB, 0xF8, 0x2F, 0xE5, 0x2D,
+			0x07, 0xEF, 0xD5, 0xCD, 0xF0, 0x20, 0x54, 0x66,
+			0x07, 0xEF, 0xD5, 0xCD, 0x0F, 0xDF, 0x76, 0xF1,
+			0xF8, 0x20, 0x1F, 0xBE, 0x07, 0xF8, 0xC3, 0x5E,
+			0xF0, 0x17, 0xB1, 0xEA, 0x07, 0xEF, 0xAD, 0x9B,
+			0x0F, 0xE8, 0x4E, 0x16, 0xF8, 0x17, 0x8F, 0x07,
+			0x00
+		};
+		res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values));
+		if (res < 0)
+			return res;
+	}
+
+	res = tas5825m_set_page(dev, 0x06);
+	if (res < 0)
+		return res;
+
+	{
+		const uint8_t values[] = {
+			0x08, 0x06, 0x13, 0x6A, 0xF0, 0x0B, 0x9D, 0x15,
+			0x07, 0xEE, 0x72, 0x7F, 0x0F, 0xF4, 0x3F, 0x7D,
+			0xF8, 0x0B, 0x56, 0xA9, 0x08, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00
+		};
+		res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values));
+		if (res < 0)
+			return res;
+	}
+
+	res = tas5825m_set_page(dev, 0x0E);
+	if (res < 0)
+		return res;
+
+	{
+		const uint8_t values[] = {
+			0x00, 0x82, 0xB3, 0xD2, 0xFF, 0x00, 0xA4, 0x7A,
+			0x00, 0x7C, 0xCA, 0xB8, 0x0F, 0xF6, 0xBE, 0xFB,
+			0xF8, 0x09, 0x1E, 0x02, 0x00
+		};
+		res = tas5825m_write_block_at(dev, 0x6C, values, ARRAY_SIZE(values));
+		if (res < 0)
+			return res;
+	}
+
+	res = tas5825m_set_page(dev, 0x0F);
+	if (res < 0)
+		return res;
+
+	{
+		const uint8_t values[] = {
+			0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0xFF, 0xF4, 0x49, 0x81,
+			0xFF, 0xE8, 0x93, 0x02, 0xFF, 0xF4, 0x49, 0x81,
+			0x0D, 0x94, 0x7A, 0x64, 0xFA, 0x3C, 0xAB, 0xA1,
+			0x06, 0xD5, 0xF3, 0xB1, 0xF2, 0x54, 0x18, 0x9F,
+			0x06, 0xD5, 0xF3, 0xB1, 0x0D, 0x94, 0x7A, 0x64,
+			0xFA, 0x3C, 0xAB, 0xA1, 0x00, 0x00, 0x38, 0xE4,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x0F, 0xD5, 0x55, 0x55, 0xF8, 0x2A, 0x71, 0xC7,
+			0x00
+		};
+		res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values));
+		if (res < 0)
+			return res;
+	}
+
+	res = tas5825m_set_book(dev, 0x00);
+	if (res < 0)
+		return res;
+
+	res = tas5825m_write_at(dev, 0x30, 0x00);
+	if (res < 0)
+		return res;
+
+	res = tas5825m_write_at(dev, 0x60, 0x02);
+	if (res < 0)
+		return res;
+
+	res = tas5825m_write_at(dev, 0x62, 0x09);
+	if (res < 0)
+		return res;
+
+	res = tas5825m_write_at(dev, 0x4C, 0x40);
+	if (res < 0)
+		return res;
+
+	res = tas5825m_write_at(dev, 0x03, 0x03);
+	if (res < 0)
+		return res;
+
+	res = tas5825m_set_book(dev, 0x00);
+	if (res < 0)
+		return res;
+
+	res = tas5825m_write_at(dev, 0x78, 0x80);
+	if (res < 0)
+		return res;
+
+	return 0;
+}
diff --git a/src/mainboard/novacustom/mtl-h/variants/igpu/gpio.c b/src/mainboard/novacustom/mtl-h/variants/igpu/gpio.c
index f52b044a9e..29a0ccc4c0 100644
--- a/src/mainboard/novacustom/mtl-h/variants/igpu/gpio.c
+++ b/src/mainboard/novacustom/mtl-h/variants/igpu/gpio.c
@@ -568,7 +568,7 @@ static const struct pad_config gpio_table[] = {
 	PAD_CFG_NF(GPP_VGPIO47, NONE, DEEP, NF1),
 };
 
-void mainboard_configure_gpios(void)
+void variant_configure_gpios(void)
 {
 	gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table));
 }
diff --git a/src/mainboard/novacustom/mtl-h/variants/igpu/ramstage.c b/src/mainboard/novacustom/mtl-h/variants/igpu/ramstage.c
new file mode 100644
index 0000000000..4d559dea53
--- /dev/null
+++ b/src/mainboard/novacustom/mtl-h/variants/igpu/ramstage.c
@@ -0,0 +1,8 @@
+/* SPDX-License-Identifier: CC-PDDC */
+
+/* Please update the license if adding licensable material. */
+
+/*
+ * This is a placeholder, if there ever is something variant specific to
+ * add to ramstage, do it here.
+ */

From 2b847cfd683f0cb120db9a0093c56b66be79e17e Mon Sep 17 00:00:00 2001
From: Maximilian Brune <maximilian.brune@9elements.com>
Date: Sat, 15 Mar 2025 16:10:15 +0100
Subject: [PATCH 0619/3886] soc/amd/*/psp_verstage: Remove duplicate
 verstage-generic-ccopts

Also remove include folders that don't even exist.

Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: Ic64f5187e50b903af5461bfa4d57bb4951d3b501
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86864
Reviewed-by: Ana Carolina Cabral <ana.cpmelo95@gmail.com>
Reviewed-by: Andy Ebrahiem <ahmet.ebrahiem@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
---
 src/soc/amd/cezanne/psp_verstage/Makefile.mk   | 2 --
 src/soc/amd/glinda/psp_verstage/Makefile.mk    | 2 --
 src/soc/amd/mendocino/psp_verstage/Makefile.mk | 2 --
 src/soc/amd/phoenix/psp_verstage/Makefile.mk   | 1 -
 4 files changed, 7 deletions(-)

diff --git a/src/soc/amd/cezanne/psp_verstage/Makefile.mk b/src/soc/amd/cezanne/psp_verstage/Makefile.mk
index bb9cc4740d..36cffdf84f 100644
--- a/src/soc/amd/cezanne/psp_verstage/Makefile.mk
+++ b/src/soc/amd/cezanne/psp_verstage/Makefile.mk
@@ -2,8 +2,6 @@
 
 verstage-generic-ccopts += -I$(src)/vendorcode/amd/psp_verstage/cezanne/include
 
-verstage-generic-ccopts += -I$(src)/soc/amd/common/psp_verstage/include
-
 subdirs-$(CONFIG_VBOOT_STARTS_BEFORE_BOOTBLOCK) += ../../common/psp_verstage
 
 verstage-y += svc.c
diff --git a/src/soc/amd/glinda/psp_verstage/Makefile.mk b/src/soc/amd/glinda/psp_verstage/Makefile.mk
index f8ad7366c5..a11f053300 100644
--- a/src/soc/amd/glinda/psp_verstage/Makefile.mk
+++ b/src/soc/amd/glinda/psp_verstage/Makefile.mk
@@ -4,8 +4,6 @@ ifeq $($(CONFIG_VBOOT_STARTS_BEFORE_BOOTBLOCK),y)
 
 subdirs-y += ../../common/psp_verstage
 
-verstage-generic-ccopts += -I$(src)/soc/amd/glinda/psp_verstage/include
-verstage-generic-ccopts += -I$(src)/soc/amd/common/psp_verstage/include
 verstage-generic-ccopts += -Isrc/vendorcode/amd/psp_verstage/glinda/include
 verstage-generic-ccopts += -Isrc/vendorcode/amd/psp_verstage/common/include
 
diff --git a/src/soc/amd/mendocino/psp_verstage/Makefile.mk b/src/soc/amd/mendocino/psp_verstage/Makefile.mk
index 347f26af6f..cc197094be 100644
--- a/src/soc/amd/mendocino/psp_verstage/Makefile.mk
+++ b/src/soc/amd/mendocino/psp_verstage/Makefile.mk
@@ -2,8 +2,6 @@
 
 verstage-generic-ccopts += -I$(src)/vendorcode/amd/psp_verstage/mendocino/include
 
-verstage-generic-ccopts += -I$(src)/soc/amd/common/psp_verstage/include
-
 subdirs-$(CONFIG_VBOOT_STARTS_BEFORE_BOOTBLOCK) += ../../common/psp_verstage
 
 verstage-y += svc.c
diff --git a/src/soc/amd/phoenix/psp_verstage/Makefile.mk b/src/soc/amd/phoenix/psp_verstage/Makefile.mk
index fc9f413bc7..7571b1d489 100644
--- a/src/soc/amd/phoenix/psp_verstage/Makefile.mk
+++ b/src/soc/amd/phoenix/psp_verstage/Makefile.mk
@@ -2,7 +2,6 @@
 
 subdirs-$(CONFIG_VBOOT_STARTS_BEFORE_BOOTBLOCK) += ../../common/psp_verstage
 
-verstage-generic-ccopts += -I$(src)/soc/amd/common/psp_verstage/include
 verstage-generic-ccopts += -Isrc/vendorcode/amd/psp_verstage/phoenix/include
 verstage-generic-ccopts += -Isrc/vendorcode/amd/psp_verstage/common/include
 

From 1afa28813239a37d0ed97d94aa9852ff9c018c0c Mon Sep 17 00:00:00 2001
From: Werner Zeh <werner.zeh@siemens.com>
Date: Tue, 11 Mar 2025 07:32:26 +0100
Subject: [PATCH 0620/3886] doc/community: Add a section on cross-project
 collaboration

This patch adds a section to the chapter 'Community' to clarify
coreboot's policy in regard to collaboration with other open-source
projects in the firmware space. It especially clarifies how coreboot
owned resources like servers and services the run can be shared with
partner projects and what the benefits and rules are for this
collaboration.

Change-Id: Ib9fbf91866192523d1a4914ff87e06f941f47d9f
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86809
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
---
 .../community/cross_project_collaboration.md  | 56 +++++++++++++++++++
 Documentation/community/index.md              |  1 +
 2 files changed, 57 insertions(+)
 create mode 100644 Documentation/community/cross_project_collaboration.md

diff --git a/Documentation/community/cross_project_collaboration.md b/Documentation/community/cross_project_collaboration.md
new file mode 100644
index 0000000000..9a4d0aa879
--- /dev/null
+++ b/Documentation/community/cross_project_collaboration.md
@@ -0,0 +1,56 @@
+# Cross-Project Collaboration
+
+Open source firmware has become popular and important over the last several
+decades and is currently anchored in multiple key applications like industry,
+automotive, infrastructure and commodity PC systems. coreboot has a
+long-reaching history in all these applications and has become a vital
+alternative to proprietary firmware solutions. Since coreboot itself is
+minimalistic, other open source projects like SeaBIOS and flashrom help complete
+the overall user experience by providing a well established way to boot into an
+OS and easily reprogram the firmware on demand.
+
+Open source projects often lack funds and are heavily dependent on volunteer
+work by enthusiasts. coreboot has made its way over the many years it’s been
+running and is now able to operate its own paid infrastructure for various
+services like git, Gerrit and Jenkins, all of them are key factors for a
+worldwide collaboration and project success. Other small but still important
+projects do not have such resources and face infrastructure issues more often.
+
+Furthermore, often the same people do work for different open source projects.
+Therefore, it is important to support such projects where feasible.
+For instance, sharing the IT infrastructure can leverage quite some synergies
+as the tasks for different projects are quite similar, e.g. push code to public,
+review it in Gerrit, let Jenkins do a build and report back to Gerrit or provide
+a bug tracker platform where users and developers can report bugs and issues.
+The coreboot project already has servers providing such services and these have
+a huge amount of headroom to execute such tasks for other projects.
+Additionally, the developers working on multiple projects are supported as they
+can do their work with the same mindset while interfacing with common services
+among different projects. This not only improves cross-project collaboration but
+also does improve code quality because the developers do not have to switch
+between different project setups.
+
+Therefore, the coreboot project explicitly encourages collaboration with other
+open source projects in the firmware domain. Especially the already well
+established partnership with flashrom, SeaBIOS, and EM100 should continue to be
+maintained further on. This includes:
+
+* Sharing of the IT infrastructure
+* Sharing the critical services like git, Gerrit, Jenkins and the bugtracker
+* Sharing of the established communication methods via mailing list, Slack, IRC
+  or Discord
+* Sharing web services for web page or wikis and blog posts
+
+If there is interest in a collaboration, please reach out to
+coreboot@coreboot.org.
+
+The coreboot project is still responsible and in charge of its offered services
+to partner projects. The technical details of the collaboration will be
+discussed on a case-by-case basis with affected parties where coreboot project
+infrastructure maintainers have the lead.
+
+Note that it is expected that everyone using the coreboot services is expected
+to follow coreboot code-of-conduct policies at all times. In cases where the
+coreboot CoC is broken by someone working only on other projects in the coreboot
+infrastructure, the coreboot leadership will work with the leadership of the
+other project on the issue.
diff --git a/Documentation/community/index.md b/Documentation/community/index.md
index 92bf6e50d4..49e85dccfd 100644
--- a/Documentation/community/index.md
+++ b/Documentation/community/index.md
@@ -7,4 +7,5 @@ Code of Conduct <code_of_conduct.md>
 Language style <language_style.md>
 Community forums <forums.md>
 coreboot at conferences <conferences.md>
+Cross-Project Collaboration <cross_project_collaboration.md>
 ```

From e91d9ea7210af041b6184a31f57dc2585e721406 Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Wed, 2 Apr 2025 20:52:59 +0100
Subject: [PATCH 0621/3886] mb/starlabs/starbook/mtl: Reconfigure PCH Strap
 GPIOs

Configure all strap GPIOs as outputs, rather than some being not
connected. This doesn't change anything, but is more explicit.

Set these all to sample on RSMRST.

Change-Id: I53415716364222de713b3bf967419e5a45322e69
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87125
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 .../starlabs/starbook/variants/mtl/gpio.c     | 54 ++++---------------
 1 file changed, 11 insertions(+), 43 deletions(-)

diff --git a/src/mainboard/starlabs/starbook/variants/mtl/gpio.c b/src/mainboard/starlabs/starbook/variants/mtl/gpio.c
index 25c3b0bc53..cd46edb151 100644
--- a/src/mainboard/starlabs/starbook/variants/mtl/gpio.c
+++ b/src/mainboard/starlabs/starbook/variants/mtl/gpio.c
@@ -78,6 +78,17 @@ const struct pad_config gpio_table[] = {
 	/* TPM */
 	PAD_CFG_GPI_APIC_LOW(GPP_F13, NONE, PLTRST),			/* Interrupt */
 
+	/* Config Straps									[ Low      / High     ] */
+	PAD_CFG_GPO(GPP_B14, 0, RSMRST),				/* Top Swap		[ Disabled / Enabled  ] */
+	PAD_CFG_GPO(GPP_B04, 0, RSMRST),				/* Reboot Support	[ Enabled  / Disabled ] */
+	PAD_CFG_GPO(GPP_C02, 1, RSMRST),				/* TLS Confidentiality	[ Disabled / Enabled  ] */
+	PAD_CFG_GPO(GPP_C05, 0, RSMRST),				/* eSPI			[ Enabled  / Disabled ] */
+	PAD_CFG_GPO(GPP_E06, 0, RSMRST),				/* JTAG ODT		[ Disabled / Enabled  ] */
+	PAD_CFG_GPO(GPP_F02, 0, RSMRST),				/* M.2 CNVi		[ Enabled  / Disabled ] */
+	PAD_CFG_GPO(GPP_H01, 0, RSMRST),				/* Flash Recovery	[ Disabled / Enabled  ] */
+	PAD_CFG_GPO(GPP_F20, 0, RSMRST),				/* SVID			[ Present  / Disabled ] */
+	PAD_CFG_GPO(GPP_F21, 0, RSMRST),				/* CCD			[ BSSB-LS  / BALTIC   ] */
+
 	/* V02:	PCIE_WAKE_LAN			*/
 	PAD_NC(GPP_V02, NONE),
 	/* V06:	GPD_6_SLP_A_N			*/
@@ -120,20 +131,10 @@ const struct pad_config gpio_table[] = {
 	 * Start:	GPP_C00
 	 * End:		GPP_C23
 	 */
-	/* C02:	TLS CONFIDENTIALITY
-	 *		HIGH:	ENABLED
-	 *		LOW:	DISABLED
-	 *		WEAK INTERNAL PD 20K	*/
-	PAD_CFG_GPO(GPP_C02, 1, DEEP),
 	/* C03:	SML0_CLK			*/
 	PAD_NC(GPP_C03, NONE),
 	/* C04:	SML0_DATA			*/
 	PAD_NC(GPP_C04, NONE),
-	/* C05:	ESPI
-	 *		HIGH:	DISABLED
-	 *		LOW:	ENABLED
-	 *		WEAK INTERNAL PD 20K	*/
-	PAD_CFG_GPO(GPP_C05, 0, PLTRST),
 	/* C08:	SML1ALERT			*/
 	PAD_CFG_NF(GPP_C08, NONE, DEEP, NF1),
 	/* C09:					*/
@@ -223,11 +224,6 @@ const struct pad_config gpio_table[] = {
 	PAD_NC(GPP_E04, NONE),
 	/* E05:					*/
 	PAD_NC(GPP_E05, NONE),
-	/* E06:	JTAG ODT
-	 *		HIGH:	ENABLED
-	 *		LOW:	DISABLED
-	 *		20K INTERNAL PU		*/
-	PAD_CFG_GPO(GPP_E06, 0, DEEP),
 	/* E07:					*/
 	PAD_NC(GPP_E07, NONE),
 	/* E08:					*/
@@ -264,11 +260,6 @@ const struct pad_config gpio_table[] = {
 	 * Start:	GPP_H00
 	 * End:		GPP_H23
 	 */
-	/* H01:	FLASH RECOVERY
-	 *		HIGH:	ENABLED
-	 *		LOW:	DISABLED
-	 *		WEAK INTERNAL PD 20K	*/
-	PAD_CFG_GPO(GPP_H01, 0, DEEP),
 	/* H03:					*/
 	PAD_NC(GPP_H03, NONE),
 	/* H04:					*/
@@ -305,8 +296,6 @@ const struct pad_config gpio_table[] = {
 	PAD_NC(GPP_F00, NONE),
 	/* F01:	CNV_BRI_RSP			*/
 	PAD_NC(GPP_F01, NONE),
-	/* F02:	CNV_RGI_DT			*/
-	PAD_NC(GPP_F02, NONE),
 	/* F03:	CNV_RGI_RSP			*/
 	PAD_NC(GPP_F03, NONE),
 	/* F04:	CNVI_RF_RESET_N			*/
@@ -342,16 +331,6 @@ const struct pad_config gpio_table[] = {
 	 *		LOW:	SLAVE
 	 *		WEAK INTERNAL PD 20K	*/
 	PAD_CFG_GPO(GPP_F19, 0, DEEP),
-	/* F20:	SVID
-	 *		HIGH:	PRESENT
-	 *		LOW:	NOT PRESENT
-	 *		WEAK INTERNAL PD 20K	*/
-	PAD_CFG_GPO(GPP_F20, 0, DEEP),
-	/* F21:	CCD
-	 *		HIGH:	BALTIC PEAK
-	 *		LOW:	BSSB-LS
-	 *		WEAK INTERNAL PU 20K	*/
-	PAD_CFG_GPO(GPP_F21, 0, DEEP),
 	/* F22:					*/
 	PAD_NC(GPP_F22, NONE),
 	/* F23:					*/
@@ -390,12 +369,6 @@ const struct pad_config gpio_table[] = {
 	PAD_NC(GPP_B02, NONE),
 	/* B03:					*/
 	PAD_NC(GPP_B03, NONE),
-	/* B04:	REBOOT CONTROL
-	 *		HIGH:	NO REBOOT
-	 *		LOW:	REBOOT ENABLED
-	 *		WEAK INTERNAL PD 20K
-	 */
-	PAD_CFG_GPO(GPP_B04, 0, DEEP),
 	/* B05:					*/
 	PAD_NC(GPP_B05, NONE),
 	/* B06:					*/
@@ -412,11 +385,6 @@ const struct pad_config gpio_table[] = {
 	PAD_NC(GPP_B11, NONE),
 	/* B12:					*/
 	PAD_NC(GPP_B12, NONE),
-	/* B14:	Top Swap Override
-	 *		HIGH:	EMABLED
-	 *		LOW:	DISABLED
-	 *		WEAK INTERNAL PD 20K	*/
-	PAD_CFG_GPO(GPP_B14, 0, PLTRST),
 	/* B15:					*/
 	PAD_NC(GPP_B15, NONE),
 	/* B17:					*/

From 752e49c35210cfd52cada7d0a72b9c95d3321d0c Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Wed, 2 Apr 2025 20:54:31 +0100
Subject: [PATCH 0622/3886] mb/starlabs/starbook/mtl: Disconnect SML1ALERT

This GPIO is not connected, so configure it accordingly.

Change-Id: Idafd6fa727f6b3a9fbfe6543c53abeb736aa9f11
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87126
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/starlabs/starbook/variants/mtl/gpio.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/mainboard/starlabs/starbook/variants/mtl/gpio.c b/src/mainboard/starlabs/starbook/variants/mtl/gpio.c
index cd46edb151..fc03329baa 100644
--- a/src/mainboard/starlabs/starbook/variants/mtl/gpio.c
+++ b/src/mainboard/starlabs/starbook/variants/mtl/gpio.c
@@ -136,7 +136,7 @@ const struct pad_config gpio_table[] = {
 	/* C04:	SML0_DATA			*/
 	PAD_NC(GPP_C04, NONE),
 	/* C08:	SML1ALERT			*/
-	PAD_CFG_NF(GPP_C08, NONE, DEEP, NF1),
+	PAD_NC(GPP_C08, NONE),
 	/* C09:					*/
 	PAD_NC(GPP_C09, NONE),
 	/* C10:					*/

From 470660d44e613016ebb4fb2ff43274087274524c Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Wed, 2 Apr 2025 20:55:15 +0100
Subject: [PATCH 0623/3886] mb/starlabs/starbook/mtl: Correct SSD GPIO config

The SSD uses GPP_A20 for reset, and GPP_H07 for enable. Correct the GPIO
configuration and corresponding entry in the devicetree.

Change-Id: I71196f65883803ba9bfc8228bb74f25795bb3a6c
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87127
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/starlabs/starbook/variants/mtl/devicetree.cb | 2 +-
 src/mainboard/starlabs/starbook/variants/mtl/gpio.c        | 6 +++---
 2 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/src/mainboard/starlabs/starbook/variants/mtl/devicetree.cb b/src/mainboard/starlabs/starbook/variants/mtl/devicetree.cb
index 9cd7831814..b86e01bc15 100644
--- a/src/mainboard/starlabs/starbook/variants/mtl/devicetree.cb
+++ b/src/mainboard/starlabs/starbook/variants/mtl/devicetree.cb
@@ -214,7 +214,7 @@ chip soc/intel/meteorlake
 
 			chip soc/intel/common/block/pcie/rtd3
 				register "enable_gpio"			= "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_H07)"
-				register "reset_gpio"			= "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_H00)"
+				register "reset_gpio"			= "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A20)"
 				register "srcclk_pin"			= "8"
 				register "is_storage"			= "true"
 				register "add_acpi_dma_property"	= "true"
diff --git a/src/mainboard/starlabs/starbook/variants/mtl/gpio.c b/src/mainboard/starlabs/starbook/variants/mtl/gpio.c
index fc03329baa..333d555e6b 100644
--- a/src/mainboard/starlabs/starbook/variants/mtl/gpio.c
+++ b/src/mainboard/starlabs/starbook/variants/mtl/gpio.c
@@ -45,7 +45,7 @@ const struct pad_config gpio_table[] = {
 
 	/* SSD */
 	PAD_CFG_NF(GPP_D20, NONE, DEEP, NF1),				/* Clock Request 8 */
-	PAD_CFG_GPO(GPP_H00, 1, PLTRST),				/* Reset */
+	PAD_CFG_GPO(GPP_A20, 1, PLTRST),				/* Reset */
 	PAD_CFG_GPO(GPP_H07, 1, PLTRST),				/* Enable */
 
 	/* Wireless */
@@ -200,8 +200,6 @@ const struct pad_config gpio_table[] = {
 	PAD_NC(GPP_A18, NONE),
 	/* A19:					*/
 	PAD_NC(GPP_A19, NONE),
-	/* A20:	M.2_CPU_SSD_RESET_N		*/
-	PAD_CFG_GPO(GPP_A20, 1, PLTRST),
 	/* A22:					*/
 	PAD_NC(GPP_A22, NONE),
 	/* A23:					*/
@@ -260,6 +258,8 @@ const struct pad_config gpio_table[] = {
 	 * Start:	GPP_H00
 	 * End:		GPP_H23
 	 */
+	/* H00:					*/
+	PAD_NC(GPP_H00, NONE),
 	/* H03:					*/
 	PAD_NC(GPP_H03, NONE),
 	/* H04:					*/

From 511f7c3d6aa07f943bf32ac8ca42d1ce302eec7a Mon Sep 17 00:00:00 2001
From: Cliff Huang <cliff.huang@intel.com>
Date: Tue, 1 Apr 2025 12:33:54 -0700
Subject: [PATCH 0624/3886] drivers/intel/touch: Conditionally add ACPI _PRW
 based on wake source

This change addresses an issue in the touch driver where the ACPI _PRW
method was added unconditionally. The ACPI _PRW method should only be
generated when an Interrupt() resource is used in the _CRS method.
When a GpioInt() resource is used instead, the _PRW method is not
required.

The ACPI generation code has been updated to conditionally add the
_PRW method based on whether the wake source is a GPIO interrupt or
an IRQ interrupt. Now, the _PRW method is only added when an IRQ pin
is specified, which is consistent with ACPI requirements.

BUG=none
TEST=Configure the DRIVERS_INTEL_TOUCH option on a motherboard that
has the necessary touch configurations with wake support. Verify that
the THC ACPI tables are correctly generated in the SSDT. If wake_gpio
(i.e. GpioInt()) is used for wake, no _PRW is generated for the device.

Signed-off-by: Cliff Huang <cliff.huang@intel.com>
Change-Id: I56fc8486c7494ff37c1d580d57838fee286128a6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87085
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/drivers/intel/touch/touch.c | 7 ++++++-
 1 file changed, 6 insertions(+), 1 deletion(-)

diff --git a/src/drivers/intel/touch/touch.c b/src/drivers/intel/touch/touch.c
index 02833124e6..a89d2e61ab 100644
--- a/src/drivers/intel/touch/touch.c
+++ b/src/drivers/intel/touch/touch.c
@@ -194,6 +194,10 @@ static void touch_generate_acpi_crs(const struct drivers_intel_touch_config *con
 	       touch_acpi_name(dev));
 	acpigen_write_name("_CRS");
 	acpigen_write_resourcetemplate_header();
+	/*
+	 * NOTE: config->wake_gpio: uses GpioInt() in _CRS; PAD needs to be Driver Mode
+	 *       config->wake_irq:  uses Interrupt() in _CRS; use GPE; PAD needs to be ACPI Mode
+	 */
 	if (config->wake_gpio.pin_count)
 		acpi_device_write_gpio(&config->wake_gpio);
 	else if (config->wake_irq.pin)
@@ -201,7 +205,8 @@ static void touch_generate_acpi_crs(const struct drivers_intel_touch_config *con
 	acpigen_write_resourcetemplate_footer();
 
 	acpigen_write_name_integer("_S0W", ACPI_DEVICE_SLEEP_D3_HOT);
-	acpigen_write_PRW(config->wake_gpe, 3);
+	if (config->wake_irq.pin)
+		acpigen_write_PRW(config->wake_gpe, 3);
 }
 
 static void touch_generate_acpi_i2cdev_dsd(const struct device *dev)

From 6e529e7c0611dbad3e4c737b16cd796c20b62f0a Mon Sep 17 00:00:00 2001
From: Cliff Huang <cliff.huang@intel.com>
Date: Tue, 19 Nov 2024 15:17:17 -0800
Subject: [PATCH 0625/3886] mb/google/fatcat: Add Intel Touch support for
 touchscreen and touchpad

This commit introduces support for touch functionalities on the
Google Fatcat board( Please see docu # 818597). Changes include:

- Configuration for building with the THC driver
- Support for touchscreen devices in both THC-I2C and THC-SPI modes
  - Rework is necessary for touchscreen use in THC-SPI mode on Fatcat
    board
  - The ELAN BOM37A device is supported in THC-I2C mode
  - The ELAN BOM36 device is supported in THC-SPI mode
- Support for the HYNITRON HFW68H touchpad device in THC-I2C mode
  - A rework is required to switch the interrupt pad from GPP_A13 to
    GPP_F18 for touchpad use in THC-I2C mode
- Introduction of variant-specific touch.h header file
- Wake support from S0ix state for both touchscreen and touchpad
  across multiple modes: LPSS-I2C, THC-I2C, and THC-SPI
- PMC GPE DW0 is reconfigured to GPP_F for Touchpad in LPSS mode in
  variant.c for wake support

BUG=none
TEST=
1. Set the CBI firmware configuration for touchscreen to
   TOUCHSCREEN_LPSS_I2C and/or TOUCHPAD to TOUCHPAD_LPSS_I2C
2. Check the ACPI objects are generated in SSDT
3. The devices should be enumerated under the /sys/class/hidraw
   directory
4. The Touchscreen and/or touchpad should function properly
   The cursor on the screen should move accordingly
5. Test wake from S0ix state via touchscreen and touchpad inputs
6. Repeat the above for the THC CBI configurations:
   touchscreen: TOUCHSCREEN_THC_I2C
   touchpad: TOUCHPAD_THC_I2C

Signed-off-by: Cliff Huang <cliff.huang@intel.com>
Change-Id: I865dbb9eed648c8f35c7f469b27a13be993ff479
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85200
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/google/fatcat/Kconfig           |  1 +
 .../google/fatcat/variants/fatcat/fw_config.c | 89 +++++++++++++++----
 .../google/fatcat/variants/fatcat/gpio.c      |  3 +
 .../fatcat/variants/fatcat/overridetree.cb    | 59 +++++++++++-
 .../google/fatcat/variants/fatcat/variant.c   | 46 ++++++++++
 5 files changed, 182 insertions(+), 16 deletions(-)

diff --git a/src/mainboard/google/fatcat/Kconfig b/src/mainboard/google/fatcat/Kconfig
index 6bdf3333eb..5773029772 100644
--- a/src/mainboard/google/fatcat/Kconfig
+++ b/src/mainboard/google/fatcat/Kconfig
@@ -60,6 +60,7 @@ config BOARD_GOOGLE_MODEL_FATCAT
 	select BOARD_GOOGLE_BASEBOARD_FATCAT
 	select DRIVERS_GENERIC_BAYHUB_LV2
 	select DRIVERS_GENERIC_MAX98357A
+	select DRIVERS_INTEL_TOUCH
 
 config BOARD_GOOGLE_FATCAT
 	select BOARD_GOOGLE_MODEL_FATCAT
diff --git a/src/mainboard/google/fatcat/variants/fatcat/fw_config.c b/src/mainboard/google/fatcat/variants/fatcat/fw_config.c
index 668950cde5..afd8a63084 100644
--- a/src/mainboard/google/fatcat/variants/fatcat/fw_config.c
+++ b/src/mainboard/google/fatcat/variants/fatcat/fw_config.c
@@ -351,6 +351,8 @@ static const struct pad_config touchscreen_disable_pads[] = {
 	PAD_NC(GPP_E17, NONE),
 	/* GPP_E18:     THC0_SPI1_INT_N_TCH_PNL1 */
 	PAD_NC(GPP_E18, NONE),
+	/* GPP_VGPIO3_THC0: THC0_WOT */
+	PAD_NC(GPP_VGPIO3_THC0, NONE),
 };
 
 static const struct pad_config touchscreen_lpss_i2c_enable_pads[] = {
@@ -370,6 +372,8 @@ static const struct pad_config touchscreen_lpss_i2c_enable_pads[] = {
 	PAD_NC(GPP_E17, NONE),
 	/* GPP_E18:     THC0_SPI1_INT_N_TCH_PNL1 */
 	PAD_CFG_GPI_APIC(GPP_E18, NONE, PLTRST, LEVEL, NONE),
+	/* GPP_VGPIO3_THC0: THC0_WOT */
+	PAD_NC(GPP_VGPIO3_THC0, NONE),
 };
 
 static const struct pad_config touchscreen_thc_i2c_enable_pads[] = {
@@ -388,7 +392,10 @@ static const struct pad_config touchscreen_thc_i2c_enable_pads[] = {
 	/* GPP_E17:     THC0_SPI1_CS0_N_TCH_PNL1 */
 	PAD_NC(GPP_E17, NONE),
 	/* GPP_E18:     THC0_SPI1_INT_N_TCH_PNL1 */
-	PAD_CFG_GPI_APIC(GPP_E18, NONE, PLTRST, LEVEL, NONE),
+	/* NOTE: this SPI INT NF is also used in THC-I2C mode */
+	PAD_CFG_NF(GPP_E18, NONE, DEEP, NF3),
+	/* GPP_VGPIO3_THC0: THC0_WOT */
+	PAD_NC(GPP_VGPIO3_THC0, NONE),
 };
 
 static const struct pad_config touchscreen_gspi_enable_pads[] = {
@@ -407,7 +414,9 @@ static const struct pad_config touchscreen_gspi_enable_pads[] = {
 	/* GPP_E17:     THC0_SPI1_CS0_N_TCH_PNL1 NF5: GSPI0 */
 	PAD_CFG_NF(GPP_E17, NONE, DEEP, NF5),
 	/* GPP_E18:     THC0_SPI1_INT_N_TCH_PNL1 */
-	PAD_CFG_GPI_APIC(GPP_E18, NONE, PLTRST, EDGE_SINGLE, INVERT)
+	PAD_CFG_GPI_APIC(GPP_E18, NONE, PLTRST, EDGE_SINGLE, INVERT),
+	/* GPP_VGPIO3_THC0: THC0_WOT */
+	PAD_NC(GPP_VGPIO3_THC0, NONE),
 };
 
 static const struct pad_config touchscreen_thc_spi_enable_pads[] = {
@@ -428,6 +437,8 @@ static const struct pad_config touchscreen_thc_spi_enable_pads[] = {
 	PAD_CFG_NF(GPP_E17, NONE, DEEP, NF3),
 	/* GPP_E18:     THC0_SPI1_INT_N_TCH_PNL1 NF3: THC HID-SPI */
 	PAD_CFG_NF(GPP_E18, NONE, DEEP, NF3),
+	/* GPP_VGPIO3_THC0: THC0_WOT */
+	PAD_NC(GPP_VGPIO3_THC0, NONE),
 };
 
 static const struct pad_config touchpad_thc_i2c_enable_pads[] = {
@@ -435,8 +446,12 @@ static const struct pad_config touchpad_thc_i2c_enable_pads[] = {
 	PAD_CFG_NF(GPP_F12, NONE, DEEP, NF1),
 	/* GPP_F13:     NF1: THC_I2C1_SDA */
 	PAD_CFG_NF(GPP_F13, NONE, DEEP, NF1),
-	/* GPP_F18:     NF3: THC1_INT_N */
-	PAD_CFG_NF(GPP_F18, NONE, DEEP, NF3)
+	/* GPP_F18:     TCH_PAD_INT_N */
+	/* NOTE: this SPI INT NF is also used in THC-I2C mode */
+	/* NOTE: require rework to switch from GPP_A13 to GPP_F18 */
+	PAD_CFG_NF(GPP_F18, NONE, DEEP, NF3),
+	/* GPP_VGPIO3_THC1: THC1_WOT */
+	PAD_NC(GPP_VGPIO3_THC1, NONE),
 };
 
 static const struct pad_config touchpad_lpss_i2c_enable_pads[] = {
@@ -445,7 +460,10 @@ static const struct pad_config touchpad_lpss_i2c_enable_pads[] = {
 	/* GPP_F13:     THC_I2C1_SDA_TCH_PAD */
 	PAD_CFG_NF(GPP_F13, NONE, DEEP, NF8),
 	/* GPP_F18:     TCH_PAD_INT_N */
-	PAD_CFG_GPI_APIC(GPP_F18, NONE, PWROK, LEVEL, INVERT),
+	/* NOTE: require rework to switch from GPP_A13 to GPP_F18 */
+	PAD_CFG_GPI_APIC(GPP_F18, NONE, PLTRST, LEVEL, INVERT),
+	/* GPP_VGPIO3_THC1: THC1_WOT */
+	PAD_NC(GPP_VGPIO3_THC1, NONE),
 };
 
 static const struct pad_config touchpad_i2c_disable_pads[] = {
@@ -454,7 +472,20 @@ static const struct pad_config touchpad_i2c_disable_pads[] = {
 	/* GPP_F13:     THC_I2C1_SDA_TCH_PAD */
 	PAD_NC(GPP_F13, NONE),
 	/* GPP_F18:     TCH_PAD_INT_N */
+	/* NOTE: require rework to switch from GPP_A13 to GPP_F18 */
 	PAD_NC(GPP_F18, NONE),
+	/* GPP_VGPIO3_THC1: THC1_WOT */
+	PAD_NC(GPP_VGPIO3_THC1, NONE),
+};
+
+static const struct pad_config thc0_enable_wake[] = {
+	/* GPP_VGPIO3_THC0: THC0_WOT */
+	PAD_CFG_GPI_APIC_DRIVER(GPP_VGPIO3_THC0, NONE, PLTRST, LEVEL, NONE),
+};
+
+static const struct pad_config thc1_enable_wake[] = {
+	/* GPP_VGPIO3_THC1: THC1_WOT */
+	PAD_CFG_GPI_APIC_DRIVER(GPP_VGPIO3_THC1, NONE, PLTRST, LEVEL, NONE),
 };
 
 static const struct pad_config ish_disable_pads[] = {
@@ -558,6 +589,8 @@ void fw_config_configure_pre_mem_gpio(void)
 
 void fw_config_gpio_padbased_override(struct pad_config *padbased_table)
 {
+	const struct soc_intel_pantherlake_config *config = config_of_soc();
+
 	if (!fw_config_is_provisioned()) {
 		printk(BIOS_WARNING, "FW_CONFIG is not provisioned, Exiting\n");
 		return;
@@ -620,23 +653,31 @@ void fw_config_gpio_padbased_override(struct pad_config *padbased_table)
 	else
 		GPIO_PADBASED_OVERRIDE(padbased_table, x1slot_pads);
 
-	if (fw_config_probe(FW_CONFIG(TOUCHPAD, TOUCHPAD_LPSS_I2C)))
+	if (fw_config_probe(FW_CONFIG(TOUCHPAD, TOUCHPAD_LPSS_I2C))) {
 		GPIO_PADBASED_OVERRIDE(padbased_table, touchpad_lpss_i2c_enable_pads);
-	else if (fw_config_probe(FW_CONFIG(TOUCHPAD, TOUCHPAD_THC_I2C)))
+	} else if (fw_config_probe(FW_CONFIG(TOUCHPAD, TOUCHPAD_THC_I2C))) {
 		GPIO_PADBASED_OVERRIDE(padbased_table, touchpad_thc_i2c_enable_pads);
-	else
+		if (config->thc_wake_on_touch[1])
+			GPIO_PADBASED_OVERRIDE(padbased_table, thc1_enable_wake);
+	} else {
 		GPIO_PADBASED_OVERRIDE(padbased_table, touchpad_i2c_disable_pads);
+	}
 
-	if (fw_config_probe(FW_CONFIG(TOUCHSCREEN, TOUCHSCREEN_LPSS_I2C)))
+	if (fw_config_probe(FW_CONFIG(TOUCHSCREEN, TOUCHSCREEN_LPSS_I2C))) {
 		GPIO_PADBASED_OVERRIDE(padbased_table, touchscreen_lpss_i2c_enable_pads);
-	else if (fw_config_probe(FW_CONFIG(TOUCHSCREEN, TOUCHSCREEN_THC_I2C)))
+	} else if (fw_config_probe(FW_CONFIG(TOUCHSCREEN, TOUCHSCREEN_THC_I2C))) {
 		GPIO_PADBASED_OVERRIDE(padbased_table, touchscreen_thc_i2c_enable_pads);
-	else if (fw_config_probe(FW_CONFIG(TOUCHSCREEN, TOUCHSCREEN_GSPI)))
+		if (config->thc_wake_on_touch[0])
+			GPIO_PADBASED_OVERRIDE(padbased_table, thc0_enable_wake);
+	} else if (fw_config_probe(FW_CONFIG(TOUCHSCREEN, TOUCHSCREEN_GSPI))) {
 		GPIO_PADBASED_OVERRIDE(padbased_table, touchscreen_gspi_enable_pads);
-	else if (fw_config_probe(FW_CONFIG(TOUCHSCREEN, TOUCHSCREEN_THC_SPI)))
+	} else if (fw_config_probe(FW_CONFIG(TOUCHSCREEN, TOUCHSCREEN_THC_SPI))) {
 		GPIO_PADBASED_OVERRIDE(padbased_table, touchscreen_thc_spi_enable_pads);
-	else
+		if (config->thc_wake_on_touch[0])
+			GPIO_PADBASED_OVERRIDE(padbased_table, thc0_enable_wake);
+	} else {
 		GPIO_PADBASED_OVERRIDE(padbased_table, touchscreen_disable_pads);
+	}
 
 	if (fw_config_probe(FW_CONFIG(ISH, ISH_DISABLE)))
 		GPIO_PADBASED_OVERRIDE(padbased_table, ish_disable_pads);
@@ -646,8 +687,26 @@ void fw_config_gpio_padbased_override(struct pad_config *padbased_table)
 	/* NOTE: disable PEG (x8 slot) and x4 slot wake for now */
 	GPIO_PADBASED_OVERRIDE(padbased_table, peg_x4slot_wake_disable_pads);
 
-	if (fw_config_probe(FW_CONFIG(FP, FP_PRESENT)))
+	/*
+	 * *=========================================================================*
+	 * |             userage                   |           GPP_E17               |
+	 * *=========================================================================*
+	 * | touchscreen in THC-SPI (with rework)  | NF3: THC HID-SPI CS0            |
+	 * *---------------------------------------*---------------------------------*
+	 * | touchscreen in gSPI    (with rework)  | NF5: GSPI0 CS0                  |
+	 * *---------------------------------------*---------------------------------*
+	 * | FPS present         (without rework)  | NF5: GSPI0 CS0                  |
+	 * *---------------------------------------*---------------------------------*
+	 *
+	 * NOTE: 1. CBI selecting TS THC-SPI or GSPI mode implies TS rework is applied for the board.
+	 *       2. CBI selecting TS THC-SPI or TS GSPI with FSP present is invalid case.
+	 */
+	if (fw_config_probe(FW_CONFIG(TOUCHSCREEN, TOUCHSCREEN_GSPI)) ||
+		fw_config_probe(FW_CONFIG(TOUCHSCREEN, TOUCHSCREEN_THC_SPI))) {
+		/*  board has TS SPI rework and not FPS support */
+	} else if (fw_config_probe(FW_CONFIG(FP, FP_PRESENT))) {
 		GPIO_PADBASED_OVERRIDE(padbased_table, fp_enable_pads);
-	else
+	} else {
 		GPIO_PADBASED_OVERRIDE(padbased_table, fp_disable_pads);
+	}
 }
diff --git a/src/mainboard/google/fatcat/variants/fatcat/gpio.c b/src/mainboard/google/fatcat/variants/fatcat/gpio.c
index 5214359c53..b1e77ec028 100644
--- a/src/mainboard/google/fatcat/variants/fatcat/gpio.c
+++ b/src/mainboard/google/fatcat/variants/fatcat/gpio.c
@@ -265,6 +265,9 @@ static const struct pad_config gpio_table[] = {
 	PAD_CFG_NF(GPP_F13, NONE, DEEP, NF8),
 	/* GPP_F17:     Not used */
 	PAD_CFG_GPI_INT(GPP_F17, NONE, PLTRST, EDGE_BOTH),
+	/* GPP_F18:     TCH_PAD_INT_N */
+	/* NOTE: require rework to switch from GPP_A13 to GPP_F18 */
+	PAD_CFG_GPI_APIC(GPP_F18, NONE, PLTRST, LEVEL, INVERT),
 	/* GPP_F19:     GPP_PRIVACY_LED_CAM2 */
 	PAD_CFG_GPO(GPP_F19, 0, PLTRST),
 	/* GPP_F20:     GPP_PRIVACY_LED_CAM1_CVS_HST_WAKE */
diff --git a/src/mainboard/google/fatcat/variants/fatcat/overridetree.cb b/src/mainboard/google/fatcat/variants/fatcat/overridetree.cb
index 741b5a46c8..c6a63c3fcb 100644
--- a/src/mainboard/google/fatcat/variants/fatcat/overridetree.cb
+++ b/src/mainboard/google/fatcat/variants/fatcat/overridetree.cb
@@ -317,13 +317,66 @@ chip soc/intel/pantherlake
 		device ref iaa off end
 
 		device ref thc0 on
+			register "thc_wake_on_touch[0]" = "true"
 			probe TOUCHSCREEN TOUCHSCREEN_THC_SPI
 			probe TOUCHSCREEN TOUCHSCREEN_THC_I2C
 			# THC0 is function 0; hence it needs to be enabled when THC1 is to be enabled.
 			probe TOUCHPAD TOUCHPAD_THC_I2C
+			chip drivers/intel/touch
+				register "name" = "INTEL_THC0_NAME"
+				register "mode" = "THC_HID_I2C_MODE"
+				register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_F08)"
+				register "enable_delay_ms" = "2"
+				register "enable_off_delay_ms" = "2"
+				register "wake_on_touch" = "true"
+				# NOTE: Use GpioInt() in _CRS and does not use GPE.
+				register "wake_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW_WAKE(GPP_VGPIO3_THC0)"
+				register "active_ltr" = "1"
+				register "idle_ltr" = "0"
+				register "connected_device" = "TH_SENSOR_ELAN"
+				register "add_acpi_dma_property" = "true"
+				device generic 0 alias touch_0_i2c_elan on
+					probe TOUCHSCREEN TOUCHSCREEN_THC_I2C
+				end
+			end
+			chip drivers/intel/touch
+				register "name" = "INTEL_THC0_NAME"
+				register "mode" = "THC_HID_SPI_MODE"
+				register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_F08)"
+				register "enable_delay_ms" = "2"
+				register "enable_off_delay_ms" = "2"
+				register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_E16)"
+				register "reset_delay_ms" = "10"
+				register "reset_off_delay_ms" = "2"
+				register "wake_on_touch" = "true"
+				# NOTE: Use GpioInt() in _CRS and does not use GPE.
+				register "wake_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW_WAKE(GPP_VGPIO3_THC0)"
+				register "active_ltr" = "1"
+				register "idle_ltr" = "0"
+				register "connected_device" = "TH_SENSOR_ELAN"
+				register "soc_hidspi.write_mode" = "HIDSPI_WRITE_MODE_MULTI_SINGLE_SPI"
+				register "soc_hidspi.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_E16)"
+				register "add_acpi_dma_property" = "true"
+				device generic 0 alias touch_0_spi_elan on
+					probe TOUCHSCREEN TOUCHSCREEN_THC_SPI
+				end
+			end
 		end
 		device ref thc1 on
+			register "thc_wake_on_touch[1]" = "true"
 			probe TOUCHPAD TOUCHPAD_THC_I2C
+			chip drivers/intel/touch
+				register "name" = "INTEL_THC1_NAME"
+				register "mode" = "THC_HID_I2C_MODE"
+				register "wake_on_touch" = "true"
+				# NOTE: Use GpioInt() in _CRS and does not use GPE.
+				register "wake_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW_WAKE(GPP_VGPIO3_THC1)"
+				register "active_ltr" = "1"
+				register "idle_ltr" = "0"
+				register "connected_device" = "TH_SENSOR_HYNITRON"
+				register "add_acpi_dma_property" = "true"
+				device generic 0 alias touch_1_i2c_hynitron on end
+			end
 		end
 
 		device ref tbt_pcie_rp0 on end
@@ -811,9 +864,11 @@ chip soc/intel/pantherlake
 		end # I2C3
 		device ref i2c4 on
 			chip drivers/i2c/hid
-				register "generic.hid" = ""ELAN6918""
+				register "generic.hid" = ""ELAN9048""
 				register "generic.desc" = ""ELAN Touchscreen""
 				register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_E18_IRQ)"
+				# NOTE: pmc_gpe0_dw2 is GPP_E in baseboard devicetree.cb.
+				register "generic.wake" = "GPE0_DW2_18"
 				register "generic.probed" = "1"
 				register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_E16)"
 				register "generic.reset_delay_ms" = "20"
@@ -832,6 +887,8 @@ chip soc/intel/pantherlake
 				register "generic.hid" = ""HFW68H""
 				register "generic.desc" = ""Hynitron TOUCHPAD""
 				register "generic.irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_F18_IRQ)"
+				# NOTE: pmc_gpe0_dw0 will be overridden to GPP_F in variant.c.
+				register "generic.wake" = "GPE0_DW0_18"
 				register "generic.uid" = "5"
 				register "generic.detect" = "1"
 				register "hid_desc_reg_offset" = "0x20"
diff --git a/src/mainboard/google/fatcat/variants/fatcat/variant.c b/src/mainboard/google/fatcat/variants/fatcat/variant.c
index 66c86cf161..5ba7683640 100644
--- a/src/mainboard/google/fatcat/variants/fatcat/variant.c
+++ b/src/mainboard/google/fatcat/variants/fatcat/variant.c
@@ -4,6 +4,8 @@
 #include <fsp/api.h>
 #include <fw_config.h>
 #include <sar.h>
+#include <soc/gpio_soc_defs.h>
+#include <drivers/intel/touch/chip.h>
 
 const char *get_wifi_sar_cbfs_filename(void)
 {
@@ -25,6 +27,50 @@ void variant_update_soc_chip_config(struct soc_intel_pantherlake_config *config)
 			config->cnvi_bt_audio_offload = true;
 		}
 	}
+
+    /* Touchscreen and touchpad WOT support:
+     * +===================+==================+=================+============================+
+     * | touchsreen        | touchpad         | PMC_GPE0_DW0    | WOT                        |
+     * +===================+==================+==============================================+
+     * | THC-SPI/THC-I2C   | LPSS-I2C         | GPP_F           | TS, TP                     |
+     * +-------------------+------------------+----------------------------------------------+
+     * | THC-SPI/THC-I2C   | not used or      | GPP_A (default) | TS                         |
+     * |                   | with WOT disabled|                 |                            |
+     * +-------------------+------------------+----------------------------------------------+
+     * | THC-SPI/THC-I2C   | THC-I2C          | GPP_A (default) | TS, TP                     |
+     * +-------------------+------------------+----------------------------------------------+
+     * | LPSS-SPI/LPSS-I2C | LPSS-I2C         | GPP_F           | TS via PMC_GPE0_DW2: GPP_E,|
+     * |                   |                  |                 | TP                         |
+     * +-------------------+------------------+----------------------------------------------+
+     * | LPSS-SPI/LPSS-I2C | not used or      | GPP_A (default) | TS via PMC_GPE0_DW2: GPP_E |
+     * |                   | with WOT disabled|                 |                            |
+     * +-------------------+------------------+----------------------------------------------+
+     * | not used          | not used or      | GPP_A (default) | NA                         |
+     * | with WOT disabled | with WOT disabled|                 |                            |
+     * +===================+==================+=================+============================+
+     */
+	if (fw_config_probe(FW_CONFIG(TOUCHSCREEN, TOUCHSCREEN_THC_I2C))) {
+		config->thc_mode[0] = THC_HID_I2C_MODE;
+	} else if (fw_config_probe(FW_CONFIG(TOUCHSCREEN, TOUCHSCREEN_THC_SPI))) {
+		config->thc_mode[0] = THC_HID_SPI_MODE;
+	} else if (fw_config_probe(FW_CONFIG(TOUCHSCREEN, TOUCHSCREEN_GSPI))) {
+		config->serial_io_gspi_mode[PchSerialIoIndexGSPI0] = PchSerialIoPci;
+	}
+
+	if (fw_config_probe(FW_CONFIG(TOUCHPAD, TOUCHPAD_LPSS_I2C))) {
+		/* touchpad: GPP_F18: GPE0_DW0_18 */
+		if (config->thc_wake_on_touch[1])
+			config->pmc_gpe0_dw0 = GPP_F;
+	} else if (fw_config_probe(FW_CONFIG(TOUCHPAD, TOUCHPAD_THC_I2C))) {
+		config->thc_mode[1] = THC_HID_I2C_MODE;
+
+		if (fw_config_probe(FW_CONFIG(TOUCHSCREEN, TOUCHSCREEN_NONE)))
+			/* When THC0 is only enabled due to THC1 is enabled, we force THC0
+			 * to I2C mode so that kernel THC I2C driver will find it and put
+			 * THC0 to low power state because no connected device is found.
+			 */
+			config->thc_mode[0] = THC_HID_I2C_MODE;
+	}
 }
 
 void variant_update_soc_memory_init_params(FSPM_UPD *memupd)

From 5c9a3c89ec1205612801b982c21d45eabc081918 Mon Sep 17 00:00:00 2001
From: Naresh Solanki <naresh.solanki@9elements.com>
Date: Fri, 13 Dec 2024 15:00:42 +0530
Subject: [PATCH 0626/3886] arch/x86/cpu: Add helper function to compute cache

Consider special requirements for computing cache size in certain SoCs,
such as `soc/amd/glinda`.

Use the helper function to implement SoC-specific logic for computing
cache size.

Change-Id: I60707de4c8242a8fbda8cb5b791a1db762d94449
Signed-off-by: Naresh Solanki <naresh.solanki@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85638
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
---
 src/arch/x86/Kconfig            |  6 ++++++
 src/arch/x86/cpu_common.c       | 15 +++++++++++----
 src/arch/x86/include/arch/cpu.h | 12 ++++++++++++
 3 files changed, 29 insertions(+), 4 deletions(-)

diff --git a/src/arch/x86/Kconfig b/src/arch/x86/Kconfig
index 7ef1a6d5c4..d78aa8fa30 100644
--- a/src/arch/x86/Kconfig
+++ b/src/arch/x86/Kconfig
@@ -453,4 +453,10 @@ config SHADOW_ROM_TABLE_TO_EBDA
 	help
 	  For platforms without writable PAM-F segment support. Put ROM table
 	  pointers (e.g. ACPI/SMBIOS low pointers) into EBDA.
+
+config SOC_FILL_CPU_CACHE_INFO
+	bool
+	default n
+	help
+	  SoC selects this if it implements soc_fill_cpu_cache_info.
 endif
diff --git a/src/arch/x86/cpu_common.c b/src/arch/x86/cpu_common.c
index 5f7cd5dddf..d7d701d016 100644
--- a/src/arch/x86/cpu_common.c
+++ b/src/arch/x86/cpu_common.c
@@ -212,11 +212,8 @@ uint8_t cpu_get_c_substate_support(const int state)
 	return (cpuid_edx(5) >> (state * 4)) & 0xf;
 }
 
-bool fill_cpu_cache_info(uint8_t level, struct cpu_cache_info *info)
+bool x86_get_cpu_cache_info(uint8_t level, struct cpu_cache_info *info)
 {
-	if (!info)
-		return false;
-
 	uint32_t leaf = cpu_get_cache_info_leaf();
 	if (!leaf)
 		return false;
@@ -235,6 +232,16 @@ bool fill_cpu_cache_info(uint8_t level, struct cpu_cache_info *info)
 
 	return true;
 }
+bool fill_cpu_cache_info(uint8_t level, struct cpu_cache_info *info)
+{
+	if (!info)
+		return false;
+
+	if (CONFIG(SOC_FILL_CPU_CACHE_INFO))
+		return soc_fill_cpu_cache_info(level, info);
+
+	return x86_get_cpu_cache_info(level, info);
+}
 
 bool is_cache_sets_power_of_two(void)
 {
diff --git a/src/arch/x86/include/arch/cpu.h b/src/arch/x86/include/arch/cpu.h
index 8bc6a182af..3685561d75 100644
--- a/src/arch/x86/include/arch/cpu.h
+++ b/src/arch/x86/include/arch/cpu.h
@@ -330,6 +330,18 @@ uint8_t cpu_get_c_substate_support(const int state);
  */
 bool fill_cpu_cache_info(uint8_t level, struct cpu_cache_info *info);
 
+/*
+ * soc_fill_cpu_cache_info is SoC specific implementation for fill_cpu_cache_info.
+ * This is intended to compute cache size for a particular level when generic
+ * implementation isn't accurate.
+ * Returns True if SoC handler was success else return False.
+ */
+bool soc_fill_cpu_cache_info(uint8_t level, struct cpu_cache_info *info);
+
+/*
+ * x86_get_cpu_cache_info is generic x86 implementation.
+ */
+bool x86_get_cpu_cache_info(uint8_t level, struct cpu_cache_info *info);
 /*
  * Determines whether the number of cache sets is a power of two.
  *

From 63318ac093e666840a454ab49324f84797d0c8df Mon Sep 17 00:00:00 2001
From: Aamir Bohra <aamirbohra@google.com>
Date: Mon, 24 Mar 2025 21:15:17 +0000
Subject: [PATCH 0627/3886] ec/google/chromeec: Add Kconfig for ChromeEC SMBIOS
 APIs

ChromeEC support information for SKU, OEM name and manufacturer name
using EC host commands. Instead of tying it up with SKU ID Kconfig
define a new Kconfig that clearly describes and allow adding support
for SMBIOS APIs based on ChromeEC host command.

BUG=b:396366352
TEST=Verify ec_smbios still compiles for required boards.

Change-Id: I665a3276aa6dc01571657359d17f292efc601d63
Signed-off-by: Aamir Bohra <aamirbohra@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86993
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/ec/google/chromeec/Kconfig             | 6 ++++++
 src/ec/google/chromeec/Makefile.mk         | 4 ++--
 src/mainboard/google/brox/Kconfig          | 1 +
 src/mainboard/google/brya/Kconfig          | 1 +
 src/mainboard/google/dedede/Kconfig        | 1 +
 src/mainboard/google/fatcat/Kconfig        | 1 +
 src/mainboard/google/guybrush/Kconfig      | 1 +
 src/mainboard/google/hatch/Kconfig         | 1 +
 src/mainboard/google/myst/Kconfig          | 1 +
 src/mainboard/google/ocelot/Kconfig        | 1 +
 src/mainboard/google/octopus/Kconfig       | 1 +
 src/mainboard/google/puff/Kconfig          | 1 +
 src/mainboard/google/rex/Kconfig           | 1 +
 src/mainboard/google/skyrim/Kconfig        | 1 +
 src/mainboard/google/volteer/Kconfig       | 1 +
 src/mainboard/google/zork/Kconfig          | 1 +
 src/mainboard/intel/ptlrvp/Kconfig         | 1 +
 src/mainboard/intel/shadowmountain/Kconfig | 1 +
 18 files changed, 24 insertions(+), 2 deletions(-)

diff --git a/src/ec/google/chromeec/Kconfig b/src/ec/google/chromeec/Kconfig
index 851ebb9352..bcd2b13351 100644
--- a/src/ec/google/chromeec/Kconfig
+++ b/src/ec/google/chromeec/Kconfig
@@ -136,6 +136,12 @@ config EC_GOOGLE_CHROMEEC_SKUID
 	help
 	  Provides common routine for reporting the skuid to ChromeOS.
 
+config EC_GOOGLE_CHROMEEC_SMBIOS
+	def_bool n
+	help
+	  Enable support to get SKU and board information for SMBIOS table
+	  using Chrome EC host commands.
+
 config EC_GOOGLE_CHROMEEC_RTC
 	bool "Enable ChromeOS EC RTC"
 	help
diff --git a/src/ec/google/chromeec/Makefile.mk b/src/ec/google/chromeec/Makefile.mk
index 6465c2cd6d..54d404003e 100644
--- a/src/ec/google/chromeec/Makefile.mk
+++ b/src/ec/google/chromeec/Makefile.mk
@@ -16,8 +16,8 @@ romstage-$(CONFIG_EC_GOOGLE_CHROMEEC_SKUID) += ec_skuid.c
 ramstage-$(CONFIG_EC_GOOGLE_CHROMEEC_SKUID) += ec_skuid.c
 
 ifeq ($(CONFIG_GENERATE_SMBIOS_TABLES),y)
-romstage-$(CONFIG_EC_GOOGLE_CHROMEEC_SKUID) += ec_smbios.c
-ramstage-$(CONFIG_EC_GOOGLE_CHROMEEC_SKUID) += ec_smbios.c
+romstage-$(CONFIG_EC_GOOGLE_CHROMEEC_SMBIOS) += ec_smbios.c
+ramstage-$(CONFIG_EC_GOOGLE_CHROMEEC_SMBIOS) += ec_smbios.c
 endif
 
 bootblock-y += ec.c
diff --git a/src/mainboard/google/brox/Kconfig b/src/mainboard/google/brox/Kconfig
index 6f50880e2e..3b5d335935 100644
--- a/src/mainboard/google/brox/Kconfig
+++ b/src/mainboard/google/brox/Kconfig
@@ -16,6 +16,7 @@ config BOARD_GOOGLE_BROX_COMMON
 	select EC_GOOGLE_CHROMEEC_BOARDID
 	select EC_GOOGLE_CHROMEEC_ESPI
 	select EC_GOOGLE_CHROMEEC_SKUID
+	select EC_GOOGLE_CHROMEEC_SMBIOS
 	select ENABLE_TCSS_USB_DETECTION if !(SOC_INTEL_TCSS_USE_PDC_PMC_USBC_MUX_CONFIGURATION || CHROMEOS)
 	select FW_CONFIG
 	select FW_CONFIG_SOURCE_CHROMEEC_CBI
diff --git a/src/mainboard/google/brya/Kconfig b/src/mainboard/google/brya/Kconfig
index 9aaf789c2c..88869018a4 100644
--- a/src/mainboard/google/brya/Kconfig
+++ b/src/mainboard/google/brya/Kconfig
@@ -23,6 +23,7 @@ config BOARD_GOOGLE_BRYA_COMMON
 	select EC_GOOGLE_CHROMEEC_BOARDID
 	select EC_GOOGLE_CHROMEEC_ESPI
 	select EC_GOOGLE_CHROMEEC_SKUID
+	select EC_GOOGLE_CHROMEEC_SMBIOS
 	select EDK2_UFS_ENABLE if EDK2_REPO_MRCHROMEBOX
 	select ENABLE_TCSS_USB_DETECTION if !(SOC_INTEL_TCSS_USE_PDC_PMC_USBC_MUX_CONFIGURATION || CHROMEOS)
 	select FW_CONFIG
diff --git a/src/mainboard/google/dedede/Kconfig b/src/mainboard/google/dedede/Kconfig
index cb61eccb39..2f94fa65d2 100644
--- a/src/mainboard/google/dedede/Kconfig
+++ b/src/mainboard/google/dedede/Kconfig
@@ -21,6 +21,7 @@ config BOARD_GOOGLE_BASEBOARD_DEDEDE
 	select EC_GOOGLE_CHROMEEC_ESPI
 	select EC_GOOGLE_CHROMEEC_INCLUDE_SSFC_IN_FW_CONFIG
 	select EC_GOOGLE_CHROMEEC_SKUID
+	select EC_GOOGLE_CHROMEEC_SMBIOS
 	select FW_CONFIG
 	select FW_CONFIG_SOURCE_CHROMEEC_CBI
 	select GOOGLE_SMBIOS_MAINBOARD_VERSION
diff --git a/src/mainboard/google/fatcat/Kconfig b/src/mainboard/google/fatcat/Kconfig
index 5773029772..2679b143d5 100644
--- a/src/mainboard/google/fatcat/Kconfig
+++ b/src/mainboard/google/fatcat/Kconfig
@@ -21,6 +21,7 @@ config BOARD_GOOGLE_FATCAT_COMMON
 	select EC_GOOGLE_CHROMEEC_BOARDID
 	select EC_GOOGLE_CHROMEEC_ESPI
 	select EC_GOOGLE_CHROMEEC_SKUID
+	select EC_GOOGLE_CHROMEEC_SMBIOS
 	select FW_CONFIG
 	select FW_CONFIG_SOURCE_CHROMEEC_CBI
 	select GENERATE_SMBIOS_TABLES
diff --git a/src/mainboard/google/guybrush/Kconfig b/src/mainboard/google/guybrush/Kconfig
index 92a5e00d90..7ca4bcbee1 100644
--- a/src/mainboard/google/guybrush/Kconfig
+++ b/src/mainboard/google/guybrush/Kconfig
@@ -22,6 +22,7 @@ config BOARD_GOOGLE_BASEBOARD_GUYBRUSH
 	select EC_GOOGLE_CHROMEEC_BOARDID
 	select EC_GOOGLE_CHROMEEC_ESPI
 	select EC_GOOGLE_CHROMEEC_SKUID
+	select EC_GOOGLE_CHROMEEC_SMBIOS
 	select ELOG
 	select ELOG_GSMI
 	select FW_CONFIG
diff --git a/src/mainboard/google/hatch/Kconfig b/src/mainboard/google/hatch/Kconfig
index 493db33902..e04ca94c49 100644
--- a/src/mainboard/google/hatch/Kconfig
+++ b/src/mainboard/google/hatch/Kconfig
@@ -17,6 +17,7 @@ config BOARD_GOOGLE_BASEBOARD_HATCH
 	select EC_GOOGLE_CHROMEEC_ESPI
 	select EC_GOOGLE_CHROMEEC_I2C_TUNNEL
 	select EC_GOOGLE_CHROMEEC_SKUID
+	select EC_GOOGLE_CHROMEEC_SMBIOS
 	select GOOGLE_SMBIOS_MAINBOARD_VERSION
 	select HAVE_ACPI_RESUME
 	select HAVE_ACPI_TABLES
diff --git a/src/mainboard/google/myst/Kconfig b/src/mainboard/google/myst/Kconfig
index c5077776b9..7e882b71e0 100644
--- a/src/mainboard/google/myst/Kconfig
+++ b/src/mainboard/google/myst/Kconfig
@@ -21,6 +21,7 @@ config BOARD_SPECIFIC_OPTIONS
 	select EC_GOOGLE_CHROMEEC
 	select EC_GOOGLE_CHROMEEC_ESPI
 	select EC_GOOGLE_CHROMEEC_SKUID
+	select EC_GOOGLE_CHROMEEC_SMBIOS
 	select EC_GOOGLE_CHROMEEC_BOARDID
 	select ELOG
 	select ELOG_GSMI
diff --git a/src/mainboard/google/ocelot/Kconfig b/src/mainboard/google/ocelot/Kconfig
index b4adda22d7..16dcdcbcea 100644
--- a/src/mainboard/google/ocelot/Kconfig
+++ b/src/mainboard/google/ocelot/Kconfig
@@ -21,6 +21,7 @@ config BOARD_GOOGLE_OCELOT_COMMON
 	select EC_GOOGLE_CHROMEEC_BOARDID
 	select EC_GOOGLE_CHROMEEC_ESPI
 	select EC_GOOGLE_CHROMEEC_SKUID
+	select EC_GOOGLE_CHROMEEC_SMBIOS
 	select FW_CONFIG
 	select FW_CONFIG_SOURCE_CHROMEEC_CBI
 	select GENERATE_SMBIOS_TABLES
diff --git a/src/mainboard/google/octopus/Kconfig b/src/mainboard/google/octopus/Kconfig
index 2676039e01..d8ac777b79 100644
--- a/src/mainboard/google/octopus/Kconfig
+++ b/src/mainboard/google/octopus/Kconfig
@@ -16,6 +16,7 @@ config BOARD_GOOGLE_BASEBOARD_OCTOPUS
 	select EC_GOOGLE_CHROMEEC_BOARDID
 	select EC_GOOGLE_CHROMEEC_ESPI
 	select EC_GOOGLE_CHROMEEC_SKUID
+	select EC_GOOGLE_CHROMEEC_SMBIOS
 	select GOOGLE_SMBIOS_MAINBOARD_VERSION
 	select HAVE_ACPI_RESUME
 	select HAVE_ACPI_TABLES
diff --git a/src/mainboard/google/puff/Kconfig b/src/mainboard/google/puff/Kconfig
index 3e64f05388..8ef3231e54 100644
--- a/src/mainboard/google/puff/Kconfig
+++ b/src/mainboard/google/puff/Kconfig
@@ -18,6 +18,7 @@ config BOARD_GOOGLE_BASEBOARD_PUFF
 	select EC_GOOGLE_CHROMEEC_ESPI
 	select EC_GOOGLE_CHROMEEC_I2C_TUNNEL
 	select EC_GOOGLE_CHROMEEC_SKUID
+	select EC_GOOGLE_CHROMEEC_SMBIOS
 	select FW_CONFIG
 	select FW_CONFIG_SOURCE_CHROMEEC_CBI
 	select GOOGLE_SMBIOS_MAINBOARD_VERSION
diff --git a/src/mainboard/google/rex/Kconfig b/src/mainboard/google/rex/Kconfig
index 8dcd5cc957..42e551253f 100644
--- a/src/mainboard/google/rex/Kconfig
+++ b/src/mainboard/google/rex/Kconfig
@@ -16,6 +16,7 @@ config BOARD_GOOGLE_REX_COMMON
 	select EC_GOOGLE_CHROMEEC_BOARDID
 	select EC_GOOGLE_CHROMEEC_ESPI
 	select EC_GOOGLE_CHROMEEC_SKUID
+	select EC_GOOGLE_CHROMEEC_SMBIOS
 	select FW_CONFIG
 	select FW_CONFIG_SOURCE_CHROMEEC_CBI
 	select GOOGLE_SMBIOS_MAINBOARD_VERSION
diff --git a/src/mainboard/google/skyrim/Kconfig b/src/mainboard/google/skyrim/Kconfig
index 756db5f69a..ebbc0afd57 100644
--- a/src/mainboard/google/skyrim/Kconfig
+++ b/src/mainboard/google/skyrim/Kconfig
@@ -50,6 +50,7 @@ config BOARD_SPECIFIC_OPTIONS
 	select EC_GOOGLE_CHROMEEC_BOARDID
 	select EC_GOOGLE_CHROMEEC_ESPI
 	select EC_GOOGLE_CHROMEEC_SKUID
+	select EC_GOOGLE_CHROMEEC_SMBIOS
 	select ELOG
 	select ELOG_GSMI
 	select FW_CONFIG
diff --git a/src/mainboard/google/volteer/Kconfig b/src/mainboard/google/volteer/Kconfig
index 15a8ece8f9..f708327eba 100644
--- a/src/mainboard/google/volteer/Kconfig
+++ b/src/mainboard/google/volteer/Kconfig
@@ -24,6 +24,7 @@ config BOARD_GOOGLE_BASEBOARD_VOLTEER
 	select EC_GOOGLE_CHROMEEC_INCLUDE_SSFC_IN_FW_CONFIG
 	select EC_GOOGLE_CHROMEEC_LPC
 	select EC_GOOGLE_CHROMEEC_SKUID
+	select EC_GOOGLE_CHROMEEC_SMBIOS
 	select ENABLE_TCSS_USB_DETECTION if !CHROMEOS
 	select FW_CONFIG
 	select FW_CONFIG_SOURCE_CHROMEEC_CBI
diff --git a/src/mainboard/google/zork/Kconfig b/src/mainboard/google/zork/Kconfig
index 1b38d270ee..2cb296408c 100644
--- a/src/mainboard/google/zork/Kconfig
+++ b/src/mainboard/google/zork/Kconfig
@@ -62,6 +62,7 @@ config BOARD_SPECIFIC_OPTIONS
 	select EC_GOOGLE_CHROMEEC_I2C_TUNNEL
 	select EC_GOOGLE_CHROMEEC_INCLUDE_SSFC_IN_FW_CONFIG
 	select EC_GOOGLE_CHROMEEC_SKUID
+	select EC_GOOGLE_CHROMEEC_SMBIOS
 	select EDK2_PCO_MMIO_EMMC if EDK2_REPO_MRCHROMEBOX
 	select ELOG
 	select ELOG_BOOT_COUNT
diff --git a/src/mainboard/intel/ptlrvp/Kconfig b/src/mainboard/intel/ptlrvp/Kconfig
index dd60855d3c..eed44e768b 100644
--- a/src/mainboard/intel/ptlrvp/Kconfig
+++ b/src/mainboard/intel/ptlrvp/Kconfig
@@ -20,6 +20,7 @@ config BOARD_INTEL_PTLRVP_COMMON
 	select EC_GOOGLE_CHROMEEC_BOARDID
 	select EC_GOOGLE_CHROMEEC_ESPI
 	select EC_GOOGLE_CHROMEEC_SKUID
+	select EC_GOOGLE_CHROMEEC_SMBIOS
 	select FW_CONFIG
 	select FW_CONFIG_SOURCE_CHROMEEC_CBI
 	select GENERATE_SMBIOS_TABLES
diff --git a/src/mainboard/intel/shadowmountain/Kconfig b/src/mainboard/intel/shadowmountain/Kconfig
index f01479bcaa..8c26e44bec 100644
--- a/src/mainboard/intel/shadowmountain/Kconfig
+++ b/src/mainboard/intel/shadowmountain/Kconfig
@@ -16,6 +16,7 @@ config BOARD_SPECIFIC_OPTIONS
 	select EC_GOOGLE_CHROMEEC
 	select EC_GOOGLE_CHROMEEC_BOARDID
 	select EC_GOOGLE_CHROMEEC_SKUID
+	select EC_GOOGLE_CHROMEEC_SMBIOS
 	select EC_GOOGLE_CHROMEEC_LPC
 	select HAVE_ACPI_RESUME
 	select HAVE_ACPI_TABLES

From f2a6a5c7fac835bae293010538bb6c39e1d74931 Mon Sep 17 00:00:00 2001
From: Aamir Bohra <aamirbohra@google.com>
Date: Tue, 25 Mar 2025 15:30:34 +0000
Subject: [PATCH 0628/3886] google/chromeec: Add function to report the SKU ID

Add implementation of sku_id function that reports the SKU ID
information by making use of ChromeOS EC host command. This function
can replace redundant sku_id function definitions across boards that
rely on ChromeOS EC host command to report the SKU ID information.

The boards that relying on ChromeOS EC host command for SKU information
without any board specific quirks can select EC_GOOGLE_CHROMEEC_SKUID
to make use of common sku_id function.

Brya, zork, rex, fatcat, brox and dedede boards select
EC_GOOGLE_CHROMEEC_SKUID to use ChromeOS EC sku_id function.

BUG=b:396366352
TEST=Verify zork and brya boot log reports the correct the SKU ID
     information

Change-Id: I958cc88bf316dd2327b6545c5a37e8010e96c5d7
Signed-off-by: Aamir Bohra <aamirbohra@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86810
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
---
 src/ec/google/chromeec/ec.c                | 13 +++++++++++++
 src/ec/google/chromeec/ec_skuid.c          | 13 +++----------
 src/mainboard/google/cherry/Kconfig        |  1 -
 src/mainboard/google/corsola/Kconfig       |  1 -
 src/mainboard/google/geralt/Kconfig        |  1 -
 src/mainboard/google/guybrush/Kconfig      |  1 -
 src/mainboard/google/hatch/Kconfig         |  1 -
 src/mainboard/google/herobrine/Kconfig     |  1 -
 src/mainboard/google/myst/Kconfig          |  1 -
 src/mainboard/google/ocelot/Kconfig        |  1 -
 src/mainboard/google/octopus/Kconfig       |  1 -
 src/mainboard/google/puff/Kconfig          |  1 -
 src/mainboard/google/rauru/Kconfig         |  1 -
 src/mainboard/google/skyrim/Kconfig        |  1 -
 src/mainboard/google/volteer/Kconfig       |  1 -
 src/mainboard/google/zork/sku_id.c         |  5 -----
 src/mainboard/intel/ptlrvp/Kconfig         |  1 -
 src/mainboard/intel/shadowmountain/Kconfig |  1 -
 18 files changed, 16 insertions(+), 30 deletions(-)

diff --git a/src/ec/google/chromeec/ec.c b/src/ec/google/chromeec/ec.c
index 5844071a1e..993bddf6ae 100644
--- a/src/ec/google/chromeec/ec.c
+++ b/src/ec/google/chromeec/ec.c
@@ -689,6 +689,19 @@ int google_chromeec_cbi_get_sku_id(uint32_t *id)
 	return cbi_get_uint32(id, CBI_TAG_SKU_ID);
 }
 
+uint32_t google_chromeec_get_board_sku(void)
+{
+	static uint32_t sku_id = CROS_SKU_UNKNOWN;
+
+	if (sku_id != CROS_SKU_UNKNOWN)
+		return sku_id;
+
+	if (google_chromeec_cbi_get_sku_id(&sku_id))
+		sku_id = CROS_SKU_UNKNOWN;
+
+	return sku_id;
+}
+
 int google_chromeec_cbi_get_fw_config(uint64_t *fw_config)
 {
 	uint32_t config;
diff --git a/src/ec/google/chromeec/ec_skuid.c b/src/ec/google/chromeec/ec_skuid.c
index c0e079c5f0..7acf0c47d4 100644
--- a/src/ec/google/chromeec/ec_skuid.c
+++ b/src/ec/google/chromeec/ec_skuid.c
@@ -1,16 +1,9 @@
 /* SPDX-License-Identifier: GPL-2.0-or-later */
 
+#include <boardid.h>
 #include <ec/google/chromeec/ec.h>
 
-uint32_t google_chromeec_get_board_sku(void)
+uint32_t sku_id(void)
 {
-	static uint32_t sku_id = CROS_SKU_UNKNOWN;
-
-	if (sku_id != CROS_SKU_UNKNOWN)
-		return sku_id;
-
-	if (google_chromeec_cbi_get_sku_id(&sku_id))
-		sku_id = CROS_SKU_UNKNOWN;
-
-	return sku_id;
+	return google_chromeec_get_board_sku();
 }
diff --git a/src/mainboard/google/cherry/Kconfig b/src/mainboard/google/cherry/Kconfig
index e3011859b4..2e4b3d3431 100644
--- a/src/mainboard/google/cherry/Kconfig
+++ b/src/mainboard/google/cherry/Kconfig
@@ -19,7 +19,6 @@ config BOARD_SPECIFIC_OPTIONS
 	select SPI_FLASH_INCLUDE_ALL_DRIVERS
 	select EC_GOOGLE_CHROMEEC
 	select EC_GOOGLE_CHROMEEC_BOARDID
-	select EC_GOOGLE_CHROMEEC_SKUID
 	select EC_GOOGLE_CHROMEEC_SPI
 	select I2C_TPM if VBOOT
 	select TPM_GOOGLE_CR50 if VBOOT
diff --git a/src/mainboard/google/corsola/Kconfig b/src/mainboard/google/corsola/Kconfig
index d8643fdb3e..1f249ac1a1 100644
--- a/src/mainboard/google/corsola/Kconfig
+++ b/src/mainboard/google/corsola/Kconfig
@@ -48,7 +48,6 @@ config BOARD_SPECIFIC_OPTIONS
 	select COMMONLIB_STORAGE_MMC
 	select EC_GOOGLE_CHROMEEC
 	select EC_GOOGLE_CHROMEEC_BOARDID
-	select EC_GOOGLE_CHROMEEC_SKUID
 	select EC_GOOGLE_CHROMEEC_SPI
 	select SPI_TPM if VBOOT
 	select TPM_GOOGLE_TI50 if VBOOT
diff --git a/src/mainboard/google/geralt/Kconfig b/src/mainboard/google/geralt/Kconfig
index dbc155c0b2..80975addd5 100644
--- a/src/mainboard/google/geralt/Kconfig
+++ b/src/mainboard/google/geralt/Kconfig
@@ -29,7 +29,6 @@ config BOARD_SPECIFIC_OPTIONS
 	select COMMONLIB_STORAGE_MMC
 	select EC_GOOGLE_CHROMEEC
 	select EC_GOOGLE_CHROMEEC_BOARDID
-	select EC_GOOGLE_CHROMEEC_SKUID
 	select EC_GOOGLE_CHROMEEC_SPI
 	select I2C_TPM if VBOOT
 	select MAINBOARD_HAS_TPM2 if VBOOT
diff --git a/src/mainboard/google/guybrush/Kconfig b/src/mainboard/google/guybrush/Kconfig
index 7ca4bcbee1..8c85f9723f 100644
--- a/src/mainboard/google/guybrush/Kconfig
+++ b/src/mainboard/google/guybrush/Kconfig
@@ -21,7 +21,6 @@ config BOARD_GOOGLE_BASEBOARD_GUYBRUSH
 	select EC_GOOGLE_CHROMEEC
 	select EC_GOOGLE_CHROMEEC_BOARDID
 	select EC_GOOGLE_CHROMEEC_ESPI
-	select EC_GOOGLE_CHROMEEC_SKUID
 	select EC_GOOGLE_CHROMEEC_SMBIOS
 	select ELOG
 	select ELOG_GSMI
diff --git a/src/mainboard/google/hatch/Kconfig b/src/mainboard/google/hatch/Kconfig
index e04ca94c49..82a632692a 100644
--- a/src/mainboard/google/hatch/Kconfig
+++ b/src/mainboard/google/hatch/Kconfig
@@ -16,7 +16,6 @@ config BOARD_GOOGLE_BASEBOARD_HATCH
 	select EC_GOOGLE_CHROMEEC_BOARDID
 	select EC_GOOGLE_CHROMEEC_ESPI
 	select EC_GOOGLE_CHROMEEC_I2C_TUNNEL
-	select EC_GOOGLE_CHROMEEC_SKUID
 	select EC_GOOGLE_CHROMEEC_SMBIOS
 	select GOOGLE_SMBIOS_MAINBOARD_VERSION
 	select HAVE_ACPI_RESUME
diff --git a/src/mainboard/google/herobrine/Kconfig b/src/mainboard/google/herobrine/Kconfig
index 8758fb9c4f..af56814bd9 100644
--- a/src/mainboard/google/herobrine/Kconfig
+++ b/src/mainboard/google/herobrine/Kconfig
@@ -24,7 +24,6 @@ config BOARD_SPECIFIC_OPTIONS
 	select COMMON_CBFS_SPI_WRAPPER
 	select EC_GOOGLE_CHROMEEC if !BOARD_GOOGLE_SENOR
 	select EC_GOOGLE_CHROMEEC_RTC if !BOARD_GOOGLE_SENOR
-	select EC_GOOGLE_CHROMEEC_SKUID if !BOARD_GOOGLE_SENOR
 	select EC_GOOGLE_CHROMEEC_SPI if !BOARD_GOOGLE_SENOR
 	select RTC if !BOARD_GOOGLE_SENOR
 	select MISSING_BOARD_RESET if BOARD_GOOGLE_SENOR
diff --git a/src/mainboard/google/myst/Kconfig b/src/mainboard/google/myst/Kconfig
index 7e882b71e0..e40531610b 100644
--- a/src/mainboard/google/myst/Kconfig
+++ b/src/mainboard/google/myst/Kconfig
@@ -20,7 +20,6 @@ config BOARD_SPECIFIC_OPTIONS
 	select DRIVERS_UART_ACPI
 	select EC_GOOGLE_CHROMEEC
 	select EC_GOOGLE_CHROMEEC_ESPI
-	select EC_GOOGLE_CHROMEEC_SKUID
 	select EC_GOOGLE_CHROMEEC_SMBIOS
 	select EC_GOOGLE_CHROMEEC_BOARDID
 	select ELOG
diff --git a/src/mainboard/google/ocelot/Kconfig b/src/mainboard/google/ocelot/Kconfig
index 16dcdcbcea..8383c8fb3e 100644
--- a/src/mainboard/google/ocelot/Kconfig
+++ b/src/mainboard/google/ocelot/Kconfig
@@ -20,7 +20,6 @@ config BOARD_GOOGLE_OCELOT_COMMON
 	select EC_GOOGLE_CHROMEEC
 	select EC_GOOGLE_CHROMEEC_BOARDID
 	select EC_GOOGLE_CHROMEEC_ESPI
-	select EC_GOOGLE_CHROMEEC_SKUID
 	select EC_GOOGLE_CHROMEEC_SMBIOS
 	select FW_CONFIG
 	select FW_CONFIG_SOURCE_CHROMEEC_CBI
diff --git a/src/mainboard/google/octopus/Kconfig b/src/mainboard/google/octopus/Kconfig
index d8ac777b79..9ae9e4c8e5 100644
--- a/src/mainboard/google/octopus/Kconfig
+++ b/src/mainboard/google/octopus/Kconfig
@@ -15,7 +15,6 @@ config BOARD_GOOGLE_BASEBOARD_OCTOPUS
 	select EC_GOOGLE_CHROMEEC
 	select EC_GOOGLE_CHROMEEC_BOARDID
 	select EC_GOOGLE_CHROMEEC_ESPI
-	select EC_GOOGLE_CHROMEEC_SKUID
 	select EC_GOOGLE_CHROMEEC_SMBIOS
 	select GOOGLE_SMBIOS_MAINBOARD_VERSION
 	select HAVE_ACPI_RESUME
diff --git a/src/mainboard/google/puff/Kconfig b/src/mainboard/google/puff/Kconfig
index 8ef3231e54..d5786a5e62 100644
--- a/src/mainboard/google/puff/Kconfig
+++ b/src/mainboard/google/puff/Kconfig
@@ -17,7 +17,6 @@ config BOARD_GOOGLE_BASEBOARD_PUFF
 	select EC_GOOGLE_CHROMEEC_BOARDID
 	select EC_GOOGLE_CHROMEEC_ESPI
 	select EC_GOOGLE_CHROMEEC_I2C_TUNNEL
-	select EC_GOOGLE_CHROMEEC_SKUID
 	select EC_GOOGLE_CHROMEEC_SMBIOS
 	select FW_CONFIG
 	select FW_CONFIG_SOURCE_CHROMEEC_CBI
diff --git a/src/mainboard/google/rauru/Kconfig b/src/mainboard/google/rauru/Kconfig
index 06d8546661..b32923dd23 100644
--- a/src/mainboard/google/rauru/Kconfig
+++ b/src/mainboard/google/rauru/Kconfig
@@ -28,7 +28,6 @@ config BOARD_SPECIFIC_OPTIONS
 	select CHROMEOS_USE_EC_WATCHDOG_FLAG if CHROMEOS
 	select EC_GOOGLE_CHROMEEC
 	select EC_GOOGLE_CHROMEEC_BOARDID
-	select EC_GOOGLE_CHROMEEC_SKUID
 	select EC_GOOGLE_CHROMEEC_SPI
 	select I2C_TPM if VBOOT
 	select MAINBOARD_HAS_TPM2 if VBOOT
diff --git a/src/mainboard/google/skyrim/Kconfig b/src/mainboard/google/skyrim/Kconfig
index ebbc0afd57..e1718bb2fd 100644
--- a/src/mainboard/google/skyrim/Kconfig
+++ b/src/mainboard/google/skyrim/Kconfig
@@ -49,7 +49,6 @@ config BOARD_SPECIFIC_OPTIONS
 	select EC_GOOGLE_CHROMEEC
 	select EC_GOOGLE_CHROMEEC_BOARDID
 	select EC_GOOGLE_CHROMEEC_ESPI
-	select EC_GOOGLE_CHROMEEC_SKUID
 	select EC_GOOGLE_CHROMEEC_SMBIOS
 	select ELOG
 	select ELOG_GSMI
diff --git a/src/mainboard/google/volteer/Kconfig b/src/mainboard/google/volteer/Kconfig
index f708327eba..fdda53b48b 100644
--- a/src/mainboard/google/volteer/Kconfig
+++ b/src/mainboard/google/volteer/Kconfig
@@ -23,7 +23,6 @@ config BOARD_GOOGLE_BASEBOARD_VOLTEER
 	select EC_GOOGLE_CHROMEEC_BOARDID
 	select EC_GOOGLE_CHROMEEC_INCLUDE_SSFC_IN_FW_CONFIG
 	select EC_GOOGLE_CHROMEEC_LPC
-	select EC_GOOGLE_CHROMEEC_SKUID
 	select EC_GOOGLE_CHROMEEC_SMBIOS
 	select ENABLE_TCSS_USB_DETECTION if !CHROMEOS
 	select FW_CONFIG
diff --git a/src/mainboard/google/zork/sku_id.c b/src/mainboard/google/zork/sku_id.c
index 82ee355084..34f7d98d46 100644
--- a/src/mainboard/google/zork/sku_id.c
+++ b/src/mainboard/google/zork/sku_id.c
@@ -4,11 +4,6 @@
 #include <baseboard/variants.h>
 #include <ec/google/chromeec/ec.h>
 
-uint32_t sku_id(void)
-{
-	return google_chromeec_get_board_sku();
-}
-
 /* An unprovisioned SKU ID indicates we're in the factory booting prior to
    proper SKU ID provisioning. */
 int boot_is_factory_unprovisioned(void)
diff --git a/src/mainboard/intel/ptlrvp/Kconfig b/src/mainboard/intel/ptlrvp/Kconfig
index eed44e768b..73e170d610 100644
--- a/src/mainboard/intel/ptlrvp/Kconfig
+++ b/src/mainboard/intel/ptlrvp/Kconfig
@@ -19,7 +19,6 @@ config BOARD_INTEL_PTLRVP_COMMON
 	select EC_GOOGLE_CHROMEEC
 	select EC_GOOGLE_CHROMEEC_BOARDID
 	select EC_GOOGLE_CHROMEEC_ESPI
-	select EC_GOOGLE_CHROMEEC_SKUID
 	select EC_GOOGLE_CHROMEEC_SMBIOS
 	select FW_CONFIG
 	select FW_CONFIG_SOURCE_CHROMEEC_CBI
diff --git a/src/mainboard/intel/shadowmountain/Kconfig b/src/mainboard/intel/shadowmountain/Kconfig
index 8c26e44bec..1dfca4b0dc 100644
--- a/src/mainboard/intel/shadowmountain/Kconfig
+++ b/src/mainboard/intel/shadowmountain/Kconfig
@@ -15,7 +15,6 @@ config BOARD_SPECIFIC_OPTIONS
 	select DRIVERS_USB_ACPI
 	select EC_GOOGLE_CHROMEEC
 	select EC_GOOGLE_CHROMEEC_BOARDID
-	select EC_GOOGLE_CHROMEEC_SKUID
 	select EC_GOOGLE_CHROMEEC_SMBIOS
 	select EC_GOOGLE_CHROMEEC_LPC
 	select HAVE_ACPI_RESUME

From 3bd2fc7a819d0105b8c4bbd31f08150cbf75fffd Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Wed, 2 Apr 2025 20:58:14 +0100
Subject: [PATCH 0629/3886] mb/starlabs/starbook/mtl: Disconnect unused GPIOs

These pins are not connected, so configure them accordingly.

Change-Id: I3cf06a0945a7793592e6599dfd4048a6114d1563
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87128
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
---
 .../starlabs/starbook/variants/mtl/gpio.c          | 14 +++++---------
 1 file changed, 5 insertions(+), 9 deletions(-)

diff --git a/src/mainboard/starlabs/starbook/variants/mtl/gpio.c b/src/mainboard/starlabs/starbook/variants/mtl/gpio.c
index 333d555e6b..63fd7f52d8 100644
--- a/src/mainboard/starlabs/starbook/variants/mtl/gpio.c
+++ b/src/mainboard/starlabs/starbook/variants/mtl/gpio.c
@@ -149,9 +149,8 @@ const struct pad_config gpio_table[] = {
 	PAD_NC(GPP_C13, NONE),
 	/* C14:					*/
 	PAD_NC(GPP_C14, NONE),
-	/* C15:	RESERVED
-	 *		WEAK INTERNAL PD 20K	*/
-	PAD_CFG_GPO(GPP_C15, 0, DEEP),
+	/* C15:					*/
+	PAD_NC(GPP_C15, NONE),
 	/* C16:					*/
 	PAD_NC(GPP_C16, NONE),
 	/* C17:					*/
@@ -237,7 +236,7 @@ const struct pad_config gpio_table[] = {
 	/* E13:					*/
 	PAD_NC(GPP_E13, NONE),
 	/* E15:	BOOTHALT_N			*/
-	PAD_CFG_NF(GPP_E15, NONE, DEEP, NF2),
+	PAD_NC(GPP_E15, NONE),
 	/* E17:					*/
 	PAD_NC(GPP_E17, NONE),
 	/* E18:					*/
@@ -326,11 +325,8 @@ const struct pad_config gpio_table[] = {
 	PAD_NC(GPP_F17, NONE),
 	/* F18:					*/
 	PAD_NC(GPP_F18, NONE),
-	/* F19:	ESPI FLASH SHARING
-	 *		HIGH:	MASTER
-	 *		LOW:	SLAVE
-	 *		WEAK INTERNAL PD 20K	*/
-	PAD_CFG_GPO(GPP_F19, 0, DEEP),
+	/* F19:					*/
+	PAD_NC(GPP_F19, NONE),
 	/* F22:					*/
 	PAD_NC(GPP_F22, NONE),
 	/* F23:					*/

From 7355b27070545297aee7a74968a169873218f3d9 Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Fri, 4 Apr 2025 11:00:30 +0100
Subject: [PATCH 0630/3886] mb/starlabs/starbook/tgl: Move Core Vendor GPIOs to
 PCH group

Change-Id: Icb3f83c9a308a7a097be1858d6db53faa1d6e1b5
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87155
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
---
 src/mainboard/starlabs/starbook/variants/tgl/gpio.c | 6 ++----
 1 file changed, 2 insertions(+), 4 deletions(-)

diff --git a/src/mainboard/starlabs/starbook/variants/tgl/gpio.c b/src/mainboard/starlabs/starbook/variants/tgl/gpio.c
index f4d4db05b5..8705b131b8 100644
--- a/src/mainboard/starlabs/starbook/variants/tgl/gpio.c
+++ b/src/mainboard/starlabs/starbook/variants/tgl/gpio.c
@@ -61,6 +61,8 @@ const struct pad_config gpio_table[] = {
 	/* PCH */
 	PAD_CFG_NF(GPP_H18, NONE, DEEP, NF1),				/* C10 Gate */
 	PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1),				/* Platform Reset */
+	PAD_CFG_NF(GPP_B0, NONE, DEEP, NF1),				/* Vendor ID 0 */
+	PAD_CFG_NF(GPP_B1, NONE, DEEP, NF1),				/* Vendor ID 1 */
 
 	/* TPM */
 	PAD_CFG_GPI_APIC_LOW(GPP_C14, NONE, PLTRST),			/* Interrupt */
@@ -114,10 +116,6 @@ const struct pad_config gpio_table[] = {
 	/* A23:	TC_RETIMER_FORCE_PWR		*/
 	PAD_CFG_GPO(GPP_A23, 0, DEEP),
 
-	/* B0:	CORE_VID_0			*/
-	PAD_CFG_NF(GPP_B0, NONE, DEEP, NF1),
-	/* B1:	CORE_VID_1			*/
-	PAD_CFG_NF(GPP_B1, NONE, DEEP, NF1),
 	/* B2:	VRALERT_N			*/
 	PAD_NC(GPP_B2, NONE),
 	/* B3:	Not Connected			*/

From aba6eceafd84b2ff369939bdf0e91c73645a6c38 Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Fri, 4 Apr 2025 11:12:49 +0100
Subject: [PATCH 0631/3886] mb/starlabs/starfighter: Disconnect USB OverCurrent
 GPIOs

These are not used so configure them accordingly.

Change-Id: I6c4d793210e3c869e4f500b18a1229c5c4d40f60
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87156
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
---
 src/mainboard/starlabs/starfighter/variants/rpl/gpio.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/mainboard/starlabs/starfighter/variants/rpl/gpio.c b/src/mainboard/starlabs/starfighter/variants/rpl/gpio.c
index 30c13a6fb3..0b02a72fb3 100644
--- a/src/mainboard/starlabs/starfighter/variants/rpl/gpio.c
+++ b/src/mainboard/starlabs/starfighter/variants/rpl/gpio.c
@@ -121,7 +121,7 @@ const struct pad_config gpio_table[] = {
 	/* A15:		Test Point 52					*/
 	PAD_NC(GPP_A15, NONE),
 	/* A16:		USB OverCurrent 3				*/
-	PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1),
+	PAD_NC(GPP_A16, NONE),
 	/* A17:		Not Connected					*/
 	PAD_NC(GPP_A17, NONE),
 	/* A19:		Not Connected					*/
@@ -273,7 +273,7 @@ const struct pad_config gpio_table[] = {
 	/* E7:		Embedded Controller SMI				*/
 	PAD_NC(GPP_E7, NONE),
 	/* E9:		USB OverCurrent 0				*/
-	PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1),
+	PAD_NC(GPP_E9, NONE),
 	/* E10:		Not Connected					*/
 	PAD_NC(GPP_E10, NONE),
 	/* E11:		Not Connected					*/

From 3af3b85fc29416488e2b65adc2917989ba64cdbd Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Fri, 4 Apr 2025 11:16:04 +0100
Subject: [PATCH 0632/3886] mb/starlabs/starfighter: Tidy GPIO comments for the
 second SSD

This is a non-functional change, and only makes the GPIOs easier to read.

Change-Id: I879819e028b71137010a21ddcc0ee6b1dafb7936
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87157
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
---
 .../starlabs/starfighter/variants/rpl/gpio.c          | 11 +++++------
 1 file changed, 5 insertions(+), 6 deletions(-)

diff --git a/src/mainboard/starlabs/starfighter/variants/rpl/gpio.c b/src/mainboard/starlabs/starfighter/variants/rpl/gpio.c
index 0b02a72fb3..ed9c94de1f 100644
--- a/src/mainboard/starlabs/starfighter/variants/rpl/gpio.c
+++ b/src/mainboard/starlabs/starfighter/variants/rpl/gpio.c
@@ -54,6 +54,11 @@ const struct pad_config gpio_table[] = {
 	PAD_CFG_GPO(GPP_F20, 1, PLTRST),				/* Reset */
 	PAD_CFG_GPO(GPP_D14, 1, DEEP),					/* Enable */
 
+	/* SSD 2 */
+	PAD_CFG_NF(GPP_H19, NONE, DEEP, NF1),				/* Clock Request 2 */
+	PAD_CFG_GPO(GPP_H0, 1, PLTRST),					/* Reset */
+	PAD_CFG_GPO(GPP_D16, 1, PLTRST),				/* Enable */
+
 	/* Wireless */
 	PAD_CFG_NF(GPP_D7, NONE, DEEP, NF1),				/* Clock Request 1 */
 	PAD_CFG_GPO(GPP_H2, 1, PLTRST),					/* Reset */
@@ -247,8 +252,6 @@ const struct pad_config gpio_table[] = {
 	PAD_NC(GPP_D13, NONE),
 	/* D15:		Not Connected					*/
 	PAD_NC(GPP_D15, NONE),
-	/* D16:		PCH M.2 SSD Power Enable			*/
-	PAD_CFG_GPO(GPP_D16, 1, PLTRST),
 	/* D17:		Not used		Fingerprint ID		*/
 	PAD_NC(GPP_D17, NONE),
 	/* D18:		Trackpad reset					*/
@@ -342,8 +345,6 @@ const struct pad_config gpio_table[] = {
 	/* F23:		Not Connected					*/
 	PAD_NC(GPP_F23, NONE),
 
-	/* H0:		PCH M.2 SSD Reset				*/
-	PAD_CFG_GPO(GPP_H0, 1, PLTRST),
 	/* H1:		BFX Strap 2 Bit 3	Weak Internal PD 20K	*/
 	PAD_CFG_GPO(GPP_H1, 0, DEEP),
 	/* H3:		Not Connected					*/
@@ -364,8 +365,6 @@ const struct pad_config gpio_table[] = {
 	PAD_NC(GPP_H14, NONE),
 	/* H16:		Not Connected					*/
 	PAD_NC(GPP_H16, NONE),
-	/* H19:		Clock Request 4		CPU M.2 SSD		*/
-	PAD_CFG_NF(GPP_H19, NONE, DEEP, NF1),
 	/* H20:		Not Connected					*/
 	PAD_NC(GPP_H20, NONE),
 	/* H21:		Not Connected					*/

From 8dabd0c14ea2537d170a2c391f00234bb83c5682 Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Fri, 4 Apr 2025 11:16:58 +0100
Subject: [PATCH 0633/3886] mb/starlabs/starfighter: Disconnect PEDET GPIO

These boards do not support SATA, so this is not needed.

Change-Id: Iff9a30cf2e8b65649440b33f850f07d499baa073
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87158
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
---
 src/mainboard/starlabs/starfighter/variants/rpl/gpio.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/mainboard/starlabs/starfighter/variants/rpl/gpio.c b/src/mainboard/starlabs/starfighter/variants/rpl/gpio.c
index ed9c94de1f..249114046e 100644
--- a/src/mainboard/starlabs/starfighter/variants/rpl/gpio.c
+++ b/src/mainboard/starlabs/starfighter/variants/rpl/gpio.c
@@ -120,7 +120,7 @@ const struct pad_config gpio_table[] = {
 	/* A11:		Not Connected					*/
 	PAD_NC(GPP_A11, NONE),
 	/* A12:		PCH M.2 SSD PEDET				*/
-	PAD_CFG_NF(GPP_A12, NONE, DEEP, NF1),
+	PAD_NC(GPP_A12, NONE),
 	/* A14:		Test Point 45					*/
 	PAD_NC(GPP_A14, NONE),
 	/* A15:		Test Point 52					*/

From c7fe1ce0e4cef8cd13793ca9da1f1aa20f716d10 Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Fri, 4 Apr 2025 11:19:56 +0100
Subject: [PATCH 0634/3886] mb/starlabs/starfighter: Tidy GPIO comments for the
 retimers

This is a non-functional change, and only makes the GPIOs easier to read.

Change-Id: Ia724e342651e064ca095f9f3f1153d86f0a73a46
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87159
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 .../starlabs/starfighter/variants/rpl/gpio.c    | 17 +++++++----------
 1 file changed, 7 insertions(+), 10 deletions(-)

diff --git a/src/mainboard/starlabs/starfighter/variants/rpl/gpio.c b/src/mainboard/starlabs/starfighter/variants/rpl/gpio.c
index 249114046e..e1445fcfa9 100644
--- a/src/mainboard/starlabs/starfighter/variants/rpl/gpio.c
+++ b/src/mainboard/starlabs/starfighter/variants/rpl/gpio.c
@@ -74,6 +74,13 @@ const struct pad_config gpio_table[] = {
 	PAD_CFG_NF(GPP_C6, NONE, DEEP, NF1),				/* SML Clock */
 	PAD_CFG_NF(GPP_C7, NONE, DEEP, NF1),				/* SML Data */
 
+	/* Retimer */
+	PAD_CFG_NF(GPP_E18, NONE, DEEP, NF2),				/* TBT0 TXD */
+	PAD_CFG_NF(GPP_E19, NONE, DEEP, NF2),				/* TBT0 RXD */
+	PAD_CFG_NF(GPP_E20, NONE, DEEP, NF4),				/* TBT1 TXD */
+	PAD_CFG_NF(GPP_E21, NONE, DEEP, NF4),				/* TBT1 RXD */
+	PAD_CFG_GPO(GPP_E4, 0, DEEP),					/* Force Power */
+
 	/* High-Definition Audio */
 	PAD_CFG_NF(GPP_R0, NATIVE, DEEP, NF1),				/* Clock */
 	PAD_CFG_NF(GPP_R1, NATIVE, DEEP, NF1),				/* Sync */
@@ -265,8 +272,6 @@ const struct pad_config gpio_table[] = {
 	PAD_NC(GPP_E1, NONE),
 	/* E2:		Not Connected					*/
 	PAD_NC(GPP_E2, NONE),
-	/* E4:		Retimer Force Power				*/
-	PAD_CFG_GPO(GPP_E4, 0, DEEP),
 	/* E5:		Not Connected					*/
 	PAD_NC(GPP_E5, NONE),
 	/* E6:		JTAG ODT		No internal PD
@@ -291,14 +296,6 @@ const struct pad_config gpio_table[] = {
 	PAD_NC(GPP_E16, NONE),
 	/* E17:		Not Connected					*/
 	PAD_NC(GPP_E17, NONE),
-	/* E18:		TBT_LSX0_TXD					*/
-	PAD_CFG_NF(GPP_E18, NONE, DEEP, NF2),
-	/* E19:		TBT_LSX0_RXD					*/
-	PAD_CFG_NF(GPP_E19, NONE, DEEP, NF2),
-	/* E20:		TBT_LSX1_TXD					*/
-	PAD_CFG_NF(GPP_E20, NONE, DEEP, NF4),
-	/* E21:		TBT_LSX1_RXD					*/
-	PAD_CFG_NF(GPP_E21, NONE, DEEP, NF4),
 	/* E22:		Not Connected					*/
 	PAD_NC(GPP_E22, NONE),
 	/* E23:		Not Connected					*/

From e0ee300dc9944139a1c02136c0e223ab0b9e5757 Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Fri, 4 Apr 2025 11:24:26 +0100
Subject: [PATCH 0635/3886] mb/starlabs/starfighter: Remove duplicate entry for
 GPP_B13

Change-Id: I8ed1ee8389e5e32ec9ddcefeb2c146281de50adb
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87160
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
---
 src/mainboard/starlabs/starfighter/variants/rpl/gpio.c | 2 --
 1 file changed, 2 deletions(-)

diff --git a/src/mainboard/starlabs/starfighter/variants/rpl/gpio.c b/src/mainboard/starlabs/starfighter/variants/rpl/gpio.c
index e1445fcfa9..85970a16b3 100644
--- a/src/mainboard/starlabs/starfighter/variants/rpl/gpio.c
+++ b/src/mainboard/starlabs/starfighter/variants/rpl/gpio.c
@@ -165,8 +165,6 @@ const struct pad_config gpio_table[] = {
 	PAD_NC(GPP_B10, NONE),
 	/* B12:		PM SLP S0					*/
 	PAD_NC(GPP_B12, NONE),
-	/* B13:		PLT RST						*/
-	PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1),
 	/* B14:		Not Connected					*/
 	PAD_NC(GPP_B14, NONE),
 	/* B15:		Not Connected					*/

From df75ed084f515691092168a337c155adac10454a Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Fri, 4 Apr 2025 11:41:15 +0100
Subject: [PATCH 0636/3886] mb/starlabs/{starbook/adl_n,starlite_adl}: Add
 missing config for TBT LSX 2

Change-Id: Id7cf723e354a98a760b9535309d1d9a8189d21ad
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87163
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/starlabs/starbook/variants/adl_n/gpio.c    | 2 +-
 src/mainboard/starlabs/starlite_adl/variants/mk_v/gpio.c | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/mainboard/starlabs/starbook/variants/adl_n/gpio.c b/src/mainboard/starlabs/starbook/variants/adl_n/gpio.c
index 7d15cb969d..1e4899b59a 100644
--- a/src/mainboard/starlabs/starbook/variants/adl_n/gpio.c
+++ b/src/mainboard/starlabs/starbook/variants/adl_n/gpio.c
@@ -89,6 +89,7 @@ const struct pad_config gpio_table[] = {
 	PAD_CFG_GPO(GPP_F2, 1, RSMRST),					/* M.2 CNVi		[ Enabled  / Disabled ] */
 	PAD_CFG_GPO(GPP_E19, 0, RSMRST),				/* TBT LSX #0		[ 1.8V     / 3.3V     ] */
 	PAD_CFG_GPO(GPP_E21, 0, RSMRST),				/* TBT LSX #1           [ 1.8V     / 3.3V     ] */
+	PAD_CFG_GPO(GPP_D10, 0, RSMRST),				/* TBT LSX #2		[ 1.8V     / 3.3V     ] */
 	PAD_CFG_GPO(GPP_D12, 0, RSMRST),				/* TBT LSX #3		[ 1.8V     / 3.3V     ] */
 	PAD_CFG_GPO(GPP_F7, 0, RSMRST),					/* MCRO LDO		[ Disabled / Bypass   ] */
 	PAD_CFG_GPO(GPD7, 0, RSMRST),					/* RTC Clock Delay	[ Disabled / 95ms     ] */
@@ -162,7 +163,6 @@ const struct pad_config gpio_table[] = {
 	PAD_NC(GPP_D7, NONE),
 	PAD_NC(GPP_D8, NONE),
 	PAD_NC(GPP_D9, NONE),
-	PAD_NC(GPP_D10, NONE),
 	PAD_NC(GPP_D11, NONE),
 	PAD_NC(GPP_D13, NONE),
 	PAD_NC(GPP_D14, NONE),
diff --git a/src/mainboard/starlabs/starlite_adl/variants/mk_v/gpio.c b/src/mainboard/starlabs/starlite_adl/variants/mk_v/gpio.c
index bd22c927ce..2b0e710d29 100644
--- a/src/mainboard/starlabs/starlite_adl/variants/mk_v/gpio.c
+++ b/src/mainboard/starlabs/starlite_adl/variants/mk_v/gpio.c
@@ -99,6 +99,7 @@ const struct pad_config gpio_table[] = {
 	PAD_CFG_GPO(GPP_H1, 0, RSMRST),					/* BFX Strap 2 Bit 3	[ Disabled / Enabled  ] */
 	PAD_CFG_GPO(GPP_E19, 0, RSMRST),				/* TBT LSX #0		[ 1.8V     / 3.3V     ] */
 	PAD_CFG_GPO(GPP_E21, 0, RSMRST),				/* TBT LSX #1           [ 1.8V     / 3.3V     ] */
+	PAD_CFG_GPO(GPP_D10, 0, RSMRST),				/* TBT LSX #2		[ 1.8V     / 3.3V     ] */
 	PAD_CFG_GPO(GPP_D12, 0, RSMRST),				/* TBT LSX #3		[ 1.8V     / 3.3V     ] */
 	PAD_CFG_GPO(GPP_F7, 0, RSMRST),					/* MCRO LDO		[ Disabled / Bypass   ] */
 	PAD_CFG_GPO(GPD7, 0, RSMRST),					/* RTC Clock Delay	[ Disabled / 95ms     ] */
@@ -173,7 +174,6 @@ const struct pad_config gpio_table[] = {
 	PAD_NC(GPP_D7, NONE),
 	PAD_NC(GPP_D8, NONE),
 	PAD_NC(GPP_D9, NONE),
-	PAD_NC(GPP_D10, NONE),
 	PAD_NC(GPP_D11, NONE),
 	PAD_NC(GPP_D13, NONE),
 	PAD_NC(GPP_D14, NONE),

From 337fc4230c686ca8a53b7c1e1b6823d4ce01532a Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Wed, 2 Apr 2025 21:00:55 +0100
Subject: [PATCH 0637/3886] mb/starlabs/starbook/mtl: Remove comments for
 disconnected GPIOs

Change-Id: I24c7529fdf606268d1ed1b838912b6448520d816
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87129
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
---
 .../starlabs/starbook/variants/mtl/gpio.c     | 188 ------------------
 1 file changed, 188 deletions(-)

diff --git a/src/mainboard/starlabs/starbook/variants/mtl/gpio.c b/src/mainboard/starlabs/starbook/variants/mtl/gpio.c
index 63fd7f52d8..c8ca8380cf 100644
--- a/src/mainboard/starlabs/starbook/variants/mtl/gpio.c
+++ b/src/mainboard/starlabs/starbook/variants/mtl/gpio.c
@@ -89,349 +89,161 @@ const struct pad_config gpio_table[] = {
 	PAD_CFG_GPO(GPP_F20, 0, RSMRST),				/* SVID			[ Present  / Disabled ] */
 	PAD_CFG_GPO(GPP_F21, 0, RSMRST),				/* CCD			[ BSSB-LS  / BALTIC   ] */
 
-	/* V02:	PCIE_WAKE_LAN			*/
 	PAD_NC(GPP_V02, NONE),
-	/* V06:	GPD_6_SLP_A_N			*/
 	PAD_NC(GPP_V06, NONE),
-	/* V07:					*/
 	PAD_NC(GPP_V07, NONE),
-	/* V09:	GPD_9_SLP_WLAN_N		*/
 	PAD_NC(GPP_V09, NONE),
-	/* V10:	PM_SLP_S5_N			*/
 	PAD_NC(GPP_V10, NONE),
-	/* V11:	LANPHY_ENABLE			*/
 	PAD_NC(GPP_V11, NONE),
-	/* V12:	SLP_LAN_N			*/
 	PAD_NC(GPP_V12, NONE),
-	/* V13					*/
 	PAD_NC(GPP_V13, NONE),
-	/* V14:	WAKE_N				*/
 	PAD_NC(GPP_V14, NONE),
-	/* V15:					*/
 	PAD_NC(GPP_V15, NONE),
-	/* V16:					*/
 	PAD_NC(GPP_V16, NONE),
-	/* V17:					*/
 	PAD_NC(GPP_V17, NONE),
-	/* V18:					*/
 	PAD_NC(GPP_V18, NONE),
-	/* V19:					*/
 	PAD_NC(GPP_V19, NONE),
-	/* V20:					*/
 	PAD_NC(GPP_V20, NONE),
-	/* V21:					*/
 	PAD_NC(GPP_V21, NONE),
-	/* V22:					*/
 	PAD_NC(GPP_V22, NONE),
-	/* V23:					*/
 	PAD_NC(GPP_V23, NONE),
 
-	/*
-	 * GPP_C
-	 * Start:	GPP_C00
-	 * End:		GPP_C23
-	 */
-	/* C03:	SML0_CLK			*/
 	PAD_NC(GPP_C03, NONE),
-	/* C04:	SML0_DATA			*/
 	PAD_NC(GPP_C04, NONE),
-	/* C08:	SML1ALERT			*/
 	PAD_NC(GPP_C08, NONE),
-	/* C09:					*/
 	PAD_NC(GPP_C09, NONE),
-	/* C10:					*/
 	PAD_NC(GPP_C10, NONE),
-	/* C11:					*/
 	PAD_NC(GPP_C11, NONE),
-	/* C12:	CLKREQ3				*/
 	PAD_NC(GPP_C12, NONE),
-	/* C13:					*/
 	PAD_NC(GPP_C13, NONE),
-	/* C14:					*/
 	PAD_NC(GPP_C14, NONE),
-	/* C15:					*/
 	PAD_NC(GPP_C15, NONE),
-	/* C16:					*/
 	PAD_NC(GPP_C16, NONE),
-	/* C17:					*/
 	PAD_NC(GPP_C17, NONE),
-	/* C18:					*/
 	PAD_NC(GPP_C18, NONE),
-	/* C19:					*/
 	PAD_NC(GPP_C19, NONE),
-	/* C20:					*/
 	PAD_NC(GPP_C20, NONE),
-	/* C21:					*/
 	PAD_NC(GPP_C21, NONE),
-	/* C22:					*/
 	PAD_NC(GPP_C22, NONE),
-	/* C23:					*/
 	PAD_NC(GPP_C23, NONE),
 
-	/*
-	 * GPP_A
-	 * Start:	GPP_A00
-	 * End:		GPP_A23
-	 */
-	/* A07:					*/
 	PAD_NC(GPP_A07, NONE),
-	/* A08:					*/
 	PAD_NC(GPP_A08, NONE),
-	/* A09:					*/
 	PAD_NC(GPP_A09, NONE),
-	/* A10:					*/
 	PAD_NC(GPP_A10, NONE),
-	/* A11:					*/
 	PAD_NC(GPP_A11, NONE),
-	/* A12:	WLAN_PEWAKE			*/
 	PAD_NC(GPP_A12, NONE),
-	/* A13:					*/
 	PAD_NC(GPP_A13, NONE),
-	/* A14:					*/
 	PAD_NC(GPP_A14, NONE),
-	/* A15:					*/
 	PAD_NC(GPP_A15, NONE),
-	/* A16:					*/
 	PAD_NC(GPP_A16, NONE),
-	/* A17:	EC_SLP_S0_CS_N			*/
 	PAD_NC(GPP_A17, NONE),
-	/* A18:					*/
 	PAD_NC(GPP_A18, NONE),
-	/* A19:					*/
 	PAD_NC(GPP_A19, NONE),
-	/* A22:					*/
 	PAD_NC(GPP_A22, NONE),
-	/* A23:					*/
 	PAD_NC(GPP_A23, NONE),
 
-	/*
-	 * GPP_E
-	 * Start:	GPP_E00
-	 * End:		GPP_E23
-	 */
-	/* E00:					*/
 	PAD_NC(GPP_E00, NONE),
-	/* E01:					*/
 	PAD_NC(GPP_E01, NONE),
-	/* E02:					*/
 	PAD_NC(GPP_E02, NONE),
-	/* E03:					*/
 	PAD_NC(GPP_E03, NONE),
-	/* E04:	M.2_SSD_DEVSLP0			*/
 	PAD_NC(GPP_E04, NONE),
-	/* E05:					*/
 	PAD_NC(GPP_E05, NONE),
-	/* E07:					*/
 	PAD_NC(GPP_E07, NONE),
-	/* E08:					*/
 	PAD_NC(GPP_E08, NONE),
-	/* E09:	USB2_OC0			*/
 	PAD_NC(GPP_E09, NONE),
-	/* E10:					*/
 	PAD_NC(GPP_E10, NONE),
-	/* E11:					*/
 	PAD_NC(GPP_E11, NONE),
-	/* E12:					*/
 	PAD_NC(GPP_E12, NONE),
-	/* E13:					*/
 	PAD_NC(GPP_E13, NONE),
-	/* E15:	BOOTHALT_N			*/
 	PAD_NC(GPP_E15, NONE),
-	/* E17:					*/
 	PAD_NC(GPP_E17, NONE),
-	/* E18:					*/
 	PAD_NC(GPP_E18, NONE),
-	/* E19:					*/
 	PAD_NC(GPP_E19, NONE),
-	/* E20:					*/
 	PAD_NC(GPP_E20, NONE),
-	/* E21:					*/
 	PAD_NC(GPP_E21, NONE),
-	/* E22:					*/
 	PAD_NC(GPP_E22, NONE),
-	/* E23:					*/
 	PAD_NC(GPP_E23, NONE),
 
-	/*
-	 * GPP_H
-	 * Start:	GPP_H00
-	 * End:		GPP_H23
-	 */
-	/* H00:					*/
 	PAD_NC(GPP_H00, NONE),
-	/* H03:					*/
 	PAD_NC(GPP_H03, NONE),
-	/* H04:					*/
 	PAD_NC(GPP_H04, NONE),
-	/* H05:					*/
 	PAD_NC(GPP_H05, NONE),
-	/* H06:					*/
 	PAD_NC(GPP_H06, NONE),
-	/* H10:					*/
 	PAD_NC(GPP_H10, NONE),
-	/* H11:					*/
 	PAD_NC(GPP_H11, NONE),
-	/* H12:					*/
 	PAD_NC(GPP_H12, NONE),
-	/* H14:					*/
 	PAD_NC(GPP_H14, NONE),
-	/* H15:					*/
 	PAD_NC(GPP_H15, NONE),
-	/* H18:					*/
 	PAD_NC(GPP_H18, NONE),
-	/* H21:					*/
 	PAD_NC(GPP_H21, NONE),
-	/* H22:					*/
 	PAD_NC(GPP_H22, NONE),
-	/* H23:					*/
 	PAD_NC(GPP_H23, NONE),
 
-	/*
-	 * GPP_F
-	 * Start:	GPP_F00
-	 * End:		GPP_F23
-	 */
-	/* F00:	CNV_BRI_DT			*/
 	PAD_NC(GPP_F00, NONE),
-	/* F01:	CNV_BRI_RSP			*/
 	PAD_NC(GPP_F01, NONE),
-	/* F03:	CNV_RGI_RSP			*/
 	PAD_NC(GPP_F03, NONE),
-	/* F04:	CNVI_RF_RESET_N			*/
 	PAD_NC(GPP_F04, NONE),
-	/* F05:	MODEM_CLKREQ			*/
 	PAD_NC(GPP_F05, NONE),
-	/* F06:					*/
 	PAD_NC(GPP_F06, NONE),
-	/* F07:					*/
 	PAD_NC(GPP_F07, NONE),
-	/* F08:					*/
 	PAD_NC(GPP_F08, NONE),
-	/* F09:					*/
 	PAD_NC(GPP_F09, NONE),
-	/* F10:	SATAXPCIE_1_SATAGP_1		*/
 	PAD_NC(GPP_F10, NONE),
-	/* F11:					*/
 	PAD_NC(GPP_F11, NONE),
-	/* F12:					*/
 	PAD_NC(GPP_F12, NONE),
-	/* F14:					*/
 	PAD_NC(GPP_F14, NONE),
-	/* F15:					*/
 	PAD_NC(GPP_F15, NONE),
-	/* F16:					*/
 	PAD_NC(GPP_F16, NONE),
-	/* F17:					*/
 	PAD_NC(GPP_F17, NONE),
-	/* F18:					*/
 	PAD_NC(GPP_F18, NONE),
-	/* F19:					*/
 	PAD_NC(GPP_F19, NONE),
-	/* F22:					*/
 	PAD_NC(GPP_F22, NONE),
-	/* F23:					*/
 	PAD_NC(GPP_F23, NONE),
 
-	/*
-	 * GPP_S
-	 * Start:	GPP_S00
-	 * End:		GPP_S07
-	 */
-	/* S00:					*/
 	PAD_NC(GPP_S00, NONE),
-	/* S01:					*/
 	PAD_NC(GPP_S01, NONE),
-	/* S02:					*/
 	PAD_NC(GPP_S02, NONE),
-	/* S03:					*/
 	PAD_NC(GPP_S03, NONE),
-	/* S04:					*/
 	PAD_NC(GPP_S04, NONE),
-	/* S05:					*/
 	PAD_NC(GPP_S05, NONE),
-	/* S06:					*/
 	PAD_NC(GPP_S06, NONE),
-	/* S07:					*/
 	PAD_NC(GPP_S07, NONE),
 
-	/*
-	 * GPP_B
-	 * Start:	GPP_B00
-	 * End:		GPP_B23
-	 */
-	/* B01:					*/
 	PAD_NC(GPP_B01, NONE),
-	/* B02:					*/
 	PAD_NC(GPP_B02, NONE),
-	/* B03:					*/
 	PAD_NC(GPP_B03, NONE),
-	/* B05:					*/
 	PAD_NC(GPP_B05, NONE),
-	/* B06:					*/
 	PAD_NC(GPP_B06, NONE),
-	/* B07:					*/
 	PAD_NC(GPP_B07, NONE),
-	/* B08:					*/
 	PAD_NC(GPP_B08, NONE),
-	/* B09:					*/
 	PAD_NC(GPP_B09, NONE),
-	/* B10:					*/
 	PAD_NC(GPP_B10, NONE),
-	/* B11:					*/
 	PAD_NC(GPP_B11, NONE),
-	/* B12:					*/
 	PAD_NC(GPP_B12, NONE),
-	/* B15:					*/
 	PAD_NC(GPP_B15, NONE),
-	/* B17:					*/
 	PAD_NC(GPP_B17, NONE),
-	/* B20:					*/
 	PAD_NC(GPP_B20, NONE),
-	/* B21:					*/
 	PAD_NC(GPP_B21, NONE),
-	/* B22:					*/
 	PAD_NC(GPP_B22, NONE),
-	/* B23:					*/
 	PAD_NC(GPP_B23, NONE),
 
-	/*
-	 * GPP_D
-	 * Start:	GPP_D00
-	 * End:		GPP_D23
-	 */
-	/* D00:					*/
 	PAD_NC(GPP_D00, NONE),
-	/* D01:					*/
 	PAD_NC(GPP_D01, NONE),
-	/* D02:					*/
 	PAD_NC(GPP_D02, NONE),
-	/* D03:					*/
 	PAD_NC(GPP_D03, NONE),
-	/* D04:					*/
 	PAD_NC(GPP_D04, NONE),
-	/* D05:					*/
 	PAD_NC(GPP_D05, NONE),
-	/* D06:	SML0BALERT#			*/
 	PAD_NC(GPP_D06, NONE),
-	/* D07:					*/
 	PAD_NC(GPP_D07, NONE),
-	/* D08:					*/
 	PAD_NC(GPP_D08, NONE),
-	/* D09:					*/
 	PAD_NC(GPP_D09, NONE),
-	/* D14:					*/
 	PAD_NC(GPP_D14, NONE),
-	/* D15:					*/
 	PAD_NC(GPP_D15, NONE),
-	/* D16:					*/
 	PAD_NC(GPP_D16, NONE),
-	/* D18:					*/
 	PAD_NC(GPP_D18, NONE),
-	/* D19:					*/
 	PAD_NC(GPP_D19, NONE),
-	/* D22:					*/
 	PAD_NC(GPP_D22, NONE),
-	/* D23:					*/
 	PAD_NC(GPP_D23, NONE),
 };
 

From 8db4be1fe95f8e042152d8418c24b56040f5bf40 Mon Sep 17 00:00:00 2001
From: Maximilian Brune <maximilian.brune@9elements.com>
Date: Tue, 1 Apr 2025 15:15:05 +0200
Subject: [PATCH 0638/3886] doc/contributing/gerrit_guidelines.md: Update
 reference to rebase.sh

Since commit cd48d198367b ("Rename and move util/gitconfig/rebase.sh"),
the script util/gitconfig/rebase.sh was moved to
util/scripts/cross-repo-cherrypick.

Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: Ibecafd6cca9d312c48cfc8c38ff11e686ee184d4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87063
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
---
 Documentation/contributing/gerrit_guidelines.md | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/Documentation/contributing/gerrit_guidelines.md b/Documentation/contributing/gerrit_guidelines.md
index 3b92d08282..04fb34f042 100644
--- a/Documentation/contributing/gerrit_guidelines.md
+++ b/Documentation/contributing/gerrit_guidelines.md
@@ -348,8 +348,8 @@ commit message itself:
 	* Tested-by:
 	* Reviewed-by:
 
-The script `util/gitconfig/rebase.sh` can be used to help automate this.
-Other tags such as 'Commit-Queue' can simply be removed.
+The script `util/scripts/cross-repo-cherrypick` can be used to help
+automate this. Other tags such as 'Commit-Queue' can simply be removed.
 
 * Check if there's documentation that needs to be updated to remain current
 after your change. If there's no documentation for the part of coreboot

From 0ffded54ddfb651f1f0fc71cddbcdf129d324946 Mon Sep 17 00:00:00 2001
From: Martin Roth <gaumless@gmail.com>
Date: Mon, 29 May 2023 21:52:11 -0600
Subject: [PATCH 0639/3886] Documentation: Write down coreboot's git commit
 message rules

This mostly lists things that long-time coreboot contributors already
do. Some of these rules were captured on the wiki. Others were adopted
from other git commit message guideline documents long ago.

Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: Ic2ba681193e302318934cc2f7f30659eac73d099
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75495
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
---
 .../contributing/git_commit_messages.md       | 78 +++++++++++++++++++
 Documentation/contributing/index.md           |  1 +
 2 files changed, 79 insertions(+)
 create mode 100644 Documentation/contributing/git_commit_messages.md

diff --git a/Documentation/contributing/git_commit_messages.md b/Documentation/contributing/git_commit_messages.md
new file mode 100644
index 0000000000..4addf4cfe3
--- /dev/null
+++ b/Documentation/contributing/git_commit_messages.md
@@ -0,0 +1,78 @@
+# Git Commit messages
+
+There are a number of different recommendations for git commit
+messages, so this is another one.
+
+It's expected that coreboot contributors already generally understand
+the idea of writing good git commit messages, so this is not trying
+to go over everything again. There are other tutorials that cover that.
+
+- [Linux Kernel tip tree Handbook](https://www.kernel.org/doc/html/latest/process/maintainer-tip.html#patch-subject)
+- [How to write a Git Commit Message](https://cbea.ms/git-commit/)
+
+## Line length
+
+- The subject line should be <= 65 characters, with an absolute maximum
+  of 75 characters
+- Prose in the commit message should be <= 75 characters
+- If reflowing prose to 75 characters can reduce the length of the
+  commit message by 2 or more lines, please reflow it. Using the entire
+  75 characters on a line when reasonable is recommended, but not
+  required.
+- Non-prose text in the body in the commit message does not need to be
+  wrapped at 75 characters. Examples: URLs, compiler output, or poetry.
+
+## Both Subject & body
+
+- Use the present tense. (The for loop exits too early, so ...", not
+ "The for loop exited too early, so ...").
+- When using acronyms, make sure they're explained in the commit
+  message itself or in the [acronyms list](https://doc.coreboot.org/acronyms.html).
+
+## Commit message Subject Line
+
+- Start the subject line with a prefix denoting the area of the change.
+  Often part of the path can be used by that. Looking through existing
+  commit messages summaries with `git log --oneline ...` gives a good
+  idea. Because this prefix takes space used by the rest of the subject,
+  it should be kept short while still uniquely describing the area.
+  - Don't include `src/`
+  - Use abbreviations where possible:
+    - mb: mainboard
+    - vc: vendorcode
+- Don't end the subject line with a period.
+- Use the imperative mood. ("Fix whitespace", not "whitespace fixes").
+
+## Commit Message Body
+
+- Make sure the problem being solved by the commit is described. While
+  it may be obvious to the committer, it may not be obvious to others.
+- Reference other commits with either CB:XXXXX or a 10 character hash
+  and the subject.
+- When using a URL in a commit message, use archive.org when possible.
+  URLs often get changed or go stale, so this keeps them stable.
+- Make sure that all changes in a patch are addressed in the commit
+  message.
+- A TEST= tag is highly recommended, but not required. This lets people
+  know whether you tested it by booting the board or just by compiling.
+- All but the most trivial of patches should generally have a body.
+- A BUG= tag can be added when the author wants to indicate that the
+  patch is or is not related to a bug. This can be either in coreboot's
+  issue tracker, or a private issue tracker.
+    - `BUG=b:####` is used by the Google internal issue tracker.
+    - `BUG=chromium:####` indicates the Chromium public tracker at
+      https://issues.chromium.org/
+    - `BUG=CID ####` can be used to indicate coverity error fixes.
+    - `BUG=https://...` can be used to link directly to a public
+      tracker.
+- The BRANCH= tag is used in cases where a patch needs to be added to a
+  specific downstream branch. This is never required by the coreboot
+  project.
+
+## Footers
+
+- The Signed-off-by line is required (Jenkins forces this).
+- The Change ID is required (Gerrit forces this.)
+- When adding a patch that has already gone through another git or
+  gerrit, the footers from those previous commits may be added, but
+  keep the list reasonable.
diff --git a/Documentation/contributing/index.md b/Documentation/contributing/index.md
index 38a67c069d..1f9e9e5e91 100644
--- a/Documentation/contributing/index.md
+++ b/Documentation/contributing/index.md
@@ -5,6 +5,7 @@
 
 Coding Style <coding_style.md>
 Gerrit Guidelines <gerrit_guidelines.md>
+Commit Message Guidelines <git_commit_messages.md>
 Project Ideas <project_ideas.md>
 Documentation Ideas <documentation_ideas.md>
 Google Summer of Code <gsoc.md>

From b9de64a0562118ff3a536e288d70cef252b7df83 Mon Sep 17 00:00:00 2001
From: Martin Roth <gaumless@gmail.com>
Date: Tue, 7 Jan 2025 12:23:17 -0700
Subject: [PATCH 0640/3886] Update Maintainers file

- Update AMD maintainers lists to reflect current situation
- Remove Ron Minnich as maintainer (at his request)
- Update the Infrastructure owners to reflect the current situation.

Change-Id: I2feac94595081fcea9becd9d8067ddd99a50123c
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85883
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
---
 MAINTAINERS | 96 ++++++++++++++++++++++-------------------------------
 1 file changed, 39 insertions(+), 57 deletions(-)

diff --git a/MAINTAINERS b/MAINTAINERS
index a786879b2e..cf6c04fa3e 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -137,12 +137,12 @@ F:	src/mainboard/acer/
 
 AMD non-server family 17h and 19h reference boards
 M:	Felix Held <felix-coreboot@felixheld.de>
-M:	Jason Glenesk <jason.glenesk@gmail.com>
+M:	Nick Kochlowski <nickkochlowski@gmail.com>
 M:	Fred Reitberger <reitbergerfred@gmail.com>
-L:	amd_coreboot_org_changes@googlegroups.com
 S:	Maintained
 F:	src/mainboard/amd/bilby/
 F:	src/mainboard/amd/birman/
+F:	src/mainboard/amd/birman_plus/
 F:	src/mainboard/amd/chausie/
 F:	src/mainboard/amd/majolica/
 F:	src/mainboard/amd/mandolin/
@@ -150,14 +150,11 @@ F:	src/mainboard/amd/mayan/
 
 AMD server family 19h reference boards
 M:	Felix Held <felix-coreboot@felixheld.de>
-M:	Martin Roth <gaumless@gmail.com>
-M:	Varshit Pandya <pandyavarshit@gmail.com>
 S:	Maintained
 F:	src/mainboard/amd/onyx_poc/
 
 AMD reference boards outside of family 17h and 19h
-S:	Odd Fixes
-L:	amd_coreboot_org_changes@googlegroups.com
+S:	Orphan
 F:	src/mainboard/amd/gardenia/
 F:	src/mainboard/amd/pademelon/
 
@@ -387,9 +384,9 @@ F:	src/mainboard/google/slippy/
 F:	src/mainboard/google/stout/
 
 GOOGLE AMD-BASED MAINBOARDS
-M:	Martin Roth <martin.roth@amd.corp-partner.google.com>
+M:	Martin Roth <gaumless@gmail.com>
 M:	Jason Nien <jason.nien@amd.corp-partner.google.com>
-L:	amd_coreboot_org_changes@googlegroups.com
+M:	Matt DeVillier <matt.devillier@gmail.com>
 S:	Supported
 F:	src/mainboard/google/kahlee/
 F:	src/mainboard/google/zork/
@@ -684,7 +681,6 @@ F:	util/nvidia/
 F:	util/rockchip/
 
 PPC64 ARCHITECTURE
-M:	Ronald Minnich <rminnich@gmail.com>
 M:	Timothy Pearson <tpearson@raptorengineeringinc.com>
 S:	Maintained
 F:	src/arch/ppc64/
@@ -692,7 +688,6 @@ F:	src/cpu/qemu-power8/
 F:	src/mainboard/emulation/qemu-power8/
 
 RISC-V ARCHITECTURE
-M:	Ronald Minnich <rminnich@gmail.com>
 M:	Maximilian Brune <maximilian.brune@9elements.com>
 R:	Philipp Hug <philipp@hug.cx>
 S:	Maintained
@@ -787,14 +782,24 @@ F:	src/northbridge/intel/x4x/
 ################################################################################
 
 AMD SUPPORT
-L:	amd_coreboot_org_changes@googlegroups.com
+M:	Felix Held <felix-coreboot@felixheld.de>
+M:	Martin Roth <gaumless@gmail.com>
+M:	Nick Kochlowski <nickkochlowski@gmail.com>
+M:	Ana Carolina Cabral <ana.cpmelo95@gmail.com>
 S:	Odd Fixes
-F:	src/vendorcode/amd/
 F:	src/cpu/amd/
 F:	src/northbridge/amd/
 F:	src/southbridge/amd/
 F:	src/include/cpu/amd/
 
+AMD VENDORCODE-SUPPORT
+M:	Felix Held <felix-coreboot@felixheld.de>
+M:	Martin Roth <gaumless@gmail.com>
+M:	Nick Kochlowski <nickkochlowski@gmail.com>
+M:	Ana Carolina Cabral <ana.cpmelo95@gmail.com>
+S:	Maintained
+F:	src/vendorcode/amd/
+
 INTEL SUPPORT
 R:	Intel_Coreboot_Reviewers <intel_coreboot_reviewers@intel.com>
 S:	Maintained
@@ -828,64 +833,41 @@ F:	src/drivers/intel/dptf/
 
 AMD Cezanne
 M:	Felix Held <felix-coreboot@felixheld.de>
-M:	Jason Glenesk <jason.glenesk@gmail.com>
-M:	Fred Reitberger <reitbergerfred@gmail.com>
-M:	Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
-L:	amd_coreboot_org_changes@googlegroups.com
 S:	Maintained
 F:	src/soc/amd/cezanne/
 F:	src/vendorcode/amd/fsp/cezanne/
 
 AMD common SoC code
 M:	Felix Held <felix-coreboot@felixheld.de>
-M:	Jason Glenesk <jason.glenesk@gmail.com>
-M:	Fred Reitberger <reitbergerfred@gmail.com>
-M:	Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
-L:	amd_coreboot_org_changes@googlegroups.com
 S:	Maintained
 F:	src/soc/amd/common/
 
 AMD Genoa Proof of Concept
 M:	Felix Held <felix-coreboot@felixheld.de>
 M:	Martin Roth <gaumless@gmail.com>
-M:	Varshit Pandya <pandyavarshit@gmail.com>
 S:	Maintained
 F:	src/soc/amd/genoa_poc/
 
 AMD Mendocino
 M:	Felix Held <felix-coreboot@felixheld.de>
-M:	Jason Glenesk <jason.glenesk@gmail.com>
-M:	Fred Reitberger <reitbergerfred@gmail.com>
-M:	Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
-L:	amd_coreboot_org_changes@googlegroups.com
-S:	Supported
+S:	Maintained
 F:	src/soc/amd/mendocino/
 F:	src/vendorcode/amd/fsp/mendocino/
 
 AMD Picasso
 M:	Felix Held <felix-coreboot@felixheld.de>
-M:	Jason Glenesk <jason.glenesk@gmail.com>
-M:	Fred Reitberger <reitbergerfred@gmail.com>
-M:	Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
-L:	amd_coreboot_org_changes@googlegroups.com
 S:	Maintained
 F:	src/soc/amd/picasso/
 F:	src/vendorcode/amd/fsp/picasso/
 
 AMD Phoenix
 M:	Felix Held <felix-coreboot@felixheld.de>
-M:	Jason Glenesk <jason.glenesk@gmail.com>
-M:	Fred Reitberger <reitbergerfred@gmail.com>
-M:	Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
-L:	amd_coreboot_org_changes@googlegroups.com
-S:	Supported
+S:	Maintained
 F:	src/soc/amd/phoenix/
 F:	src/vendorcode/amd/fsp/phoenix/
 
 AMD Stoneyridge
 M:	Felix Held <felix-coreboot@felixheld.de>
-M:	Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
-L:	amd_coreboot_org_changes@googlegroups.com
 S:	Odd Fixes
 F:	src/soc/amd/stoneyridge/
 
@@ -1246,47 +1228,47 @@ MISSING: SPI
 # *** Infrastructure Owners ***
 # This is intended to let people know who they should contact for issues with various infrastructure pieces.
 # Hardware
-#	Owners: Patrick
-#	Backups:
+#	Owners: Felix Singer <felixsinger@posteo.net>
+#		David Hendricks <dhendrix@coreboot.org>
+#	Backups: Martin Roth <gaumless@gmail.com>
 
 # Web Server
-#	Owners: Patrick
-#	Backups:
+#	Owners: Felix Singer <felixsinger@posteo.net>
+#		David Hendricks <dhendrix@coreboot.org>
+#	Backups: Martin Roth <gaumless@gmail.com>
 
 # Website
-#	Owners: Martin
-#	Backups: Patrick
+#	Owners: Martin Roth <gaumless@gmail.com>
+#	Backups:
 
 # Documentation Website
-#	Owners: Patrick
+#	Owners: Felix Singer <felixsinger@posteo.net>
 #	Backups:
 
 CODE OF CONDUCT
-M:	Ronald Minnich <rminnich@gmail.com>
-M:	Martin Roth <martin@coreboot.org>
+M:	Martin Roth <gaumless@gmail.com>
+M:	David Hendricks <dhendrix@coreboot.org>
 S:	Maintained
 F:	Documentation/community/code_of_conduct.md
 
-# Wiki
-#	Owners: Patrick
-#	Backups:
-
 # Gerrit
-#	Owners: Patrick
-#	Backups: Martin
+#	Owners: Felix Singer <felixsinger@posteo.net>
+#		David Hendricks <dhendrix@coreboot.org>
+#	Backups: Martin Roth <gaumless@gmail.com>
 
 # Jenkins
-#	Owners: Patrick, Martin
+#	Owners: Felix Singer <felixsinger@posteo.net>
 #	Backups:
 
 # Bug Tracker
 #	Owners: Lynxis,
-#	Backups: Martin,
+#	Backups: Felix Singer <felixsinger@posteo.net>
 
 # Mailing List
 #	Owners: Patrick
-#	Backups: Martin
+#	Backups: Martin Roth <gaumless@gmail.com>
 
 # Software Freedom Conservancy
-#	Main contact: Martin
-#	“Official” contact: David, Matt, Werner
+#	Main contact: Martin Roth <gaumless@gmail.com>
+#	Backup: Matt DeVillier <mrchromeboox@coreboot.org>
+#		Werner Zeh <mrchromebox@coreboot.org>

From 9ddc9cbfc99a0225d40350e3101c7c292a8556c8 Mon Sep 17 00:00:00 2001
From: Martin Roth <gaumless@gmail.com>
Date: Wed, 8 Jan 2025 11:53:17 -0700
Subject: [PATCH 0641/3886] Documentation: Add a statement about committer
 responsibilities

This statement clarifies committer responsibilities, including using
generative AI.

Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: Ibfc92fc76149f96bd8e65befce99f3a2ddc3d847
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85898
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
---
 Documentation/contributing/index.md | 17 +++++++++++++++++
 1 file changed, 17 insertions(+)

diff --git a/Documentation/contributing/index.md b/Documentation/contributing/index.md
index 1f9e9e5e91..a230f964d1 100644
--- a/Documentation/contributing/index.md
+++ b/Documentation/contributing/index.md
@@ -10,3 +10,20 @@ Project Ideas <project_ideas.md>
 Documentation Ideas <documentation_ideas.md>
 Google Summer of Code <gsoc.md>
 ```
+
+The coreboot project uses the Developer Certificate of Origin as its
+policy of accepting contributions. As such, a submitter bears the burden
+that they have all necessary rights to submit their contribution to the
+project under the project's licenses as appropriate. Violations of third
+party rights will lead to the code's removal or replacement as suitable
+to bring the project back into compliance.
+
+This applies no matter under which circumstances a contribution has been
+created: legal frameworks, work contracts, Generative Artificial
+Intelligence ("AI") tooling, or other aspects that may affect the
+ownership and copyright status of a contribution are outside the
+project's control.
+
+See the [Sign-off procedure] for more information.
+
+[Sign-off procedure]: gerrit_guidelines.md#sign-off-procedure

From 64931a3d658b90d383ab9d65f05d9f2adbe4d653 Mon Sep 17 00:00:00 2001
From: Nicolas Kochlowski <nickkochlowski@gmail.com>
Date: Mon, 14 Oct 2024 11:57:01 -0300
Subject: [PATCH 0642/3886] Documentation/getting_started/cbmem.md: Add cbmem
 documentation

Change-Id: I514cfbd6df85f332419444c35d066a518d5044f3
Signed-off-by: Nicolas Kochlowski <nickkochlowski@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84761
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ana Carolina Cabral <ana.cpmelo95@gmail.com>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
---
 Documentation/getting_started/cbmem.md | 41 ++++++++++++++++++++++++++
 Documentation/getting_started/index.md |  1 +
 2 files changed, 42 insertions(+)
 create mode 100644 Documentation/getting_started/cbmem.md

diff --git a/Documentation/getting_started/cbmem.md b/Documentation/getting_started/cbmem.md
new file mode 100644
index 0000000000..13e6cf807e
--- /dev/null
+++ b/Documentation/getting_started/cbmem.md
@@ -0,0 +1,41 @@
+# CBMEM high table memory manager
+
+## Introduction
+CBMEM (coreboot memory) is a dynamic memory infrastructure used in
+coreboot to store runtime data structures, logs, and other information
+that needs to persist across different boot stages. CBMEM is crucial
+for maintaining state and logging information across different stages
+of the coreboot boot process.
+
+## Creation and Placement
+CBMEM is initialized by coreboot during romstage, but is used mainly in
+ramstage for storing data such as coreboot and ACPI tables, SMBIOS,
+timestamps, stage information, vendor-specific data structures, etc.
+
+For 32-bit builds, CBMEM is typically located at the highest usable
+DRAM address below the 4GiB boundary. For 64-bit builds, while there
+is no strict upper limit, it is advisable to follow the same guidelines
+to prevent access or addressing issues. Regardless of the build type,
+the CBMEM address must remain consistent between romstage and ramstage.
+
+Each platform may need to implement its own method for determining the
+`cbmem_top` address, as this can depend on specific hardware
+configurations and memory layouts.
+
+## Usage
+Each CBMEM region is identified by a unique ID, allowing different
+components to store and retrieve their data during runtime. The ID is a
+32-bit value that optionally encodes characters to indicate the type or
+source of the data.
+
+Upon creating an entry, a block of memory is allocated of the requested
+size from the reserved CBMEM region. This region persists across warm
+reboots, making it useful for debugging and passing information to
+payloads.
+
+Note that CBMEM is implemented as imd (in-memory database), meaning
+it grows downwards in memory from the provided upper limit, and only
+the latest added entry may be removed.
+
+The `cbmem` tool in `/util` can be used to list and access entries
+using their ID.
diff --git a/Documentation/getting_started/index.md b/Documentation/getting_started/index.md
index 7180c9615a..8b2ce3a31c 100644
--- a/Documentation/getting_started/index.md
+++ b/Documentation/getting_started/index.md
@@ -10,5 +10,6 @@ Kconfig <kconfig.md>
 Writing Documentation <writing_documentation.md>
 Setting up GPIOs <gpio.md>
 Adding devices to a device tree <devicetree.md>
+CBMEM <cbmem.md>
 Frequently Asked Questions <faq.md>
 ```

From a0562266e48f95694f90150cd385cd029e004cb0 Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Fri, 4 Apr 2025 12:11:06 +0100
Subject: [PATCH 0643/3886] mb/starlabs/starbook/tgl: Remove SSD GPIO quirk

This quirk was added to turn of the SSD in S3. This is now handled by
the RTD3 driver, so it can be removed.

Change-Id: Iaf6364a0957f95411c11e31c8317e1c4ec5c769f
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87166
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/starlabs/starbook/acpi/sleep.asl | 6 ------
 1 file changed, 6 deletions(-)

diff --git a/src/mainboard/starlabs/starbook/acpi/sleep.asl b/src/mainboard/starlabs/starbook/acpi/sleep.asl
index 78a2d290db..7ed74e3514 100644
--- a/src/mainboard/starlabs/starbook/acpi/sleep.asl
+++ b/src/mainboard/starlabs/starbook/acpi/sleep.asl
@@ -2,12 +2,6 @@
 
 Method (MPTS, 1, NotSerialized)
 {
-#if CONFIG(BOARD_STARLABS_STARBOOK_TGL)
-	If (Arg0 == 0x03) {
-		\_SB.PCI0.CTXS (GPP_D16)
-	}
-#endif
-
 	RPTS (Arg0)
 }
 

From 6b75f09b23c64c89f786b2fef37d881bebc34d9d Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Fri, 4 Apr 2025 21:21:23 +0100
Subject: [PATCH 0644/3886] mb/starlabs/starbook/mtl: Uncomment eSPI GPIOs

These, unlike almost all other Intel platforms, are not configured
automatically on reset, so coreboot needs to handle it.

Change-Id: Ie013ce1769e61fae1622a9cc1a048229fd9d6944
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87178
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
---
 .../starlabs/starbook/variants/mtl/gpio.c          | 14 +++++++-------
 1 file changed, 7 insertions(+), 7 deletions(-)

diff --git a/src/mainboard/starlabs/starbook/variants/mtl/gpio.c b/src/mainboard/starlabs/starbook/variants/mtl/gpio.c
index c8ca8380cf..bb976a8431 100644
--- a/src/mainboard/starlabs/starbook/variants/mtl/gpio.c
+++ b/src/mainboard/starlabs/starbook/variants/mtl/gpio.c
@@ -30,13 +30,13 @@ const struct pad_config gpio_table[] = {
 	PAD_CFG_NF(GPP_V08, NONE, DEEP, NF1),				/* Bluetooth Suspend */
 
 	/* eSPI */
-	// PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_A00, UP_20K, DEEP, NF1),	/* eSPI IO 0 */
-	// PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_A01, UP_20K, DEEP, NF1),	/* eSPI IO 1 */
-	// PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_A02, UP_20K, DEEP, NF1),	/* eSPI IO 2 */
-	// PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_A03, UP_20K, DEEP, NF1),	/* eSPI IO 3 */
-	// PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_A04, UP_20K, DEEP, NF1),	/* eSPI CS 0 */
-	// PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_A05, UP_20K, DEEP, NF1),	/* eSPI Clk */
-	// PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_A06, NONE, DEEP, NF1),	/* eSPI Reset */
+	PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_A00, UP_20K, DEEP, NF1),	/* eSPI IO 0 */
+	PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_A01, UP_20K, DEEP, NF1),	/* eSPI IO 1 */
+	PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_A02, UP_20K, DEEP, NF1),	/* eSPI IO 2 */
+	PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_A03, UP_20K, DEEP, NF1),	/* eSPI IO 3 */
+	PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_A04, UP_20K, DEEP, NF1),	/* eSPI CS 0 */
+	PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_A05, UP_20K, DEEP, NF1),	/* eSPI Clk */
+	PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_A06, NONE, DEEP, NF1),		/* eSPI Reset */
 
 	/* Touchpad */
 	PAD_CFG_NF(GPP_H19, NONE, DEEP, NF1),				/* Data */

From 56575d41135507b63ba75c023374778e7ff779a4 Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Fri, 4 Apr 2025 12:19:10 +0100
Subject: [PATCH 0645/3886] mb/starlabs/starbook/tgl: Tidy GPIO comments for
 the retimers

This is a non-functional change, and only makes the GPIOs easier to read.

Change-Id: I237824415c99bf57e9617a37001383cdda4a38e6
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87167
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
---
 src/mainboard/starlabs/starbook/variants/tgl/gpio.c | 11 +++++------
 1 file changed, 5 insertions(+), 6 deletions(-)

diff --git a/src/mainboard/starlabs/starbook/variants/tgl/gpio.c b/src/mainboard/starlabs/starbook/variants/tgl/gpio.c
index 8705b131b8..28b3388532 100644
--- a/src/mainboard/starlabs/starbook/variants/tgl/gpio.c
+++ b/src/mainboard/starlabs/starbook/variants/tgl/gpio.c
@@ -51,6 +51,11 @@ const struct pad_config gpio_table[] = {
 	PAD_CFG_NF(GPP_C6, NONE, PWROK, NF1),				/* SML Clock */
 	PAD_CFG_NF(GPP_C7, NONE, PWROK, NF1),				/* SML Data */
 
+	/* Retimer */
+	PAD_NC(GPP_E18, NATIVE),					/* TBT0 TXD */
+	PAD_NC(GPP_E19, NATIVE),					/* TBT0 RXD */
+	PAD_CFG_GPO(GPP_A23, 0, DEEP),					/* Force Power */
+
 	/* High-Definition Audio */
 	PAD_CFG_NF(GPP_R0, NATIVE, DEEP, NF1),				/* Clock */
 	PAD_CFG_NF(GPP_R1, NATIVE, DEEP, NF1),				/* Sync */
@@ -113,8 +118,6 @@ const struct pad_config gpio_table[] = {
 	PAD_NC(GPP_A21, NONE),
 	/* A22:	Not Connected			*/
 	PAD_NC(GPP_A22, NONE),
-	/* A23:	TC_RETIMER_FORCE_PWR		*/
-	PAD_CFG_GPO(GPP_A23, 0, DEEP),
 
 	/* B2:	VRALERT_N			*/
 	PAD_NC(GPP_B2, NONE),
@@ -257,10 +260,6 @@ const struct pad_config gpio_table[] = {
 	PAD_NC(GPP_E16, NONE),
 	/* E17:	Not Connected			*/
 	PAD_NC(GPP_E17, NONE),
-	/* E18:	TBT_LSX0_TXD			*/
-	PAD_NC(GPP_E18, NATIVE),
-	/* E19:	TBT_LSX0_RXD			*/
-	PAD_NC(GPP_E19, NATIVE),
 	/* E20:	Not Connected			*/
 	PAD_NC(GPP_E20, NONE),
 	/* E21:	TBT_LSX1_RXD			*/

From c42e645d9952bdd91fd3f113c3a6cf6e12895234 Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Fri, 4 Apr 2025 12:20:58 +0100
Subject: [PATCH 0646/3886] mb/starlabs/starbook/tgl: Move PROCHOT GPIO to PCH
 group

Change-Id: I3fb4421698df9ca3e9a6067d9054ef10ec103f25
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87168
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
---
 src/mainboard/starlabs/starbook/variants/tgl/gpio.c | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/src/mainboard/starlabs/starbook/variants/tgl/gpio.c b/src/mainboard/starlabs/starbook/variants/tgl/gpio.c
index 28b3388532..07b455f449 100644
--- a/src/mainboard/starlabs/starbook/variants/tgl/gpio.c
+++ b/src/mainboard/starlabs/starbook/variants/tgl/gpio.c
@@ -68,6 +68,7 @@ const struct pad_config gpio_table[] = {
 	PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1),				/* Platform Reset */
 	PAD_CFG_NF(GPP_B0, NONE, DEEP, NF1),				/* Vendor ID 0 */
 	PAD_CFG_NF(GPP_B1, NONE, DEEP, NF1),				/* Vendor ID 1 */
+	PAD_NC(GPP_B2, NONE),						/* Processor Hot */
 
 	/* TPM */
 	PAD_CFG_GPI_APIC_LOW(GPP_C14, NONE, PLTRST),			/* Interrupt */
@@ -119,8 +120,6 @@ const struct pad_config gpio_table[] = {
 	/* A22:	Not Connected			*/
 	PAD_NC(GPP_A22, NONE),
 
-	/* B2:	VRALERT_N			*/
-	PAD_NC(GPP_B2, NONE),
 	/* B3:	Not Connected			*/
 	PAD_NC(GPP_B3, NONE),
 	/* B4:	Not Connected			*/

From 8860dd9a42161c61fe736809e0c39c81dfb4b4b4 Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Fri, 4 Apr 2025 12:34:39 +0100
Subject: [PATCH 0647/3886] mb/starlabs/starbook/tgl: Disconnect unused GPIOs

These pins are not used, so configure them accordingly.

Change-Id: If82741382c113b2f05078e0d24690943c9053421
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87169
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
---
 .../starlabs/starbook/variants/tgl/gpio.c     | 28 +++++++++----------
 1 file changed, 14 insertions(+), 14 deletions(-)

diff --git a/src/mainboard/starlabs/starbook/variants/tgl/gpio.c b/src/mainboard/starlabs/starbook/variants/tgl/gpio.c
index 07b455f449..ddf7db78a6 100644
--- a/src/mainboard/starlabs/starbook/variants/tgl/gpio.c
+++ b/src/mainboard/starlabs/starbook/variants/tgl/gpio.c
@@ -80,15 +80,15 @@ const struct pad_config gpio_table[] = {
 	/* GPD2:	LAN_WAKE#		*/
 	PAD_NC(GPD2, NONE),
 	/* GPD6:	SIO_SLP_A#		*/
-	PAD_CFG_NF(GPD6, NONE, DEEP, NF1),
+	PAD_NC(GPD6, NONE),
 	/* GPD7:	PCH_TBT_PERST#		*/
 	PAD_CFG_GPO(GPD7, 0, PLTRST),
 	/* GPD9:	SIO_SLP_WLAN#		*/
-	PAD_CFG_NF(GPD9, NONE, DEEP, NF1),
+	PAD_NC(GPD9, NONE),
 	/* GPD10:	SIO_SLP_S5#		*/
-	PAD_CFG_NF(GPD10, NONE, DEEP, NF1),
+	PAD_NC(GPD10, NONE),
 	/* GPD11:	PM_LANPHY_EN		*/
-	PAD_CFG_NF(GPD11, NONE, DEEP, NF1),
+	PAD_NC(GPD11, NONE),
 
 	/* A6:	Not Connected(TP764)		*/
 	/* A7:	WLAN_PCM_CLK			*/
@@ -108,7 +108,7 @@ const struct pad_config gpio_table[] = {
 	/* A15	Not Connected			*/
 	PAD_NC(GPP_A15, NONE),
 	/* A16:	USB2_OCB_3			*/
-	PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1),
+	PAD_NC(GPP_A16, NONE),
 	/* A17:	Not Connected			*/
 	PAD_NC(GPP_A17, NONE),
 	/* A19	Not Connected			*/
@@ -133,11 +133,11 @@ const struct pad_config gpio_table[] = {
 	/* B8:	Not Connected			*/
 	PAD_NC(GPP_B8, NONE),
 	/* B9:	PWR_MON_I2C_SDA_R		*/
-	PAD_CFG_NF(GPP_B9, NONE, DEEP, NF1),
+	PAD_NC(GPP_B9, NONE),
 	/* B10:	PWR_MON_I2C_SCL_R		*/
-	PAD_CFG_NF(GPP_B10, NONE, DEEP, NF1),
+	PAD_NC(GPP_B10, NONE),
 	/* B12:	PM_SLP_S0_N			*/
-	PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1),
+	PAD_NC(GPP_B12, NONE),
 	/* B14:	FPS_RST_N			*/
 	PAD_CFG_GPO(GPP_B14, 1, PLTRST),
 	/* B15:	Not Connected			*/
@@ -162,9 +162,9 @@ const struct pad_config gpio_table[] = {
 	/* C2:	SMBALERT_N			*/
 	PAD_CFG_GPO(GPP_C2, 0, DEEP),
 	/* C3:	SML0_CLK			*/
-	PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1),
+	PAD_NC(GPP_C3, NONE),
 	/* C4:	SML0_DATA			*/
-	PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1),
+	PAD_NC(GPP_C4, NONE),
 	/* C5:	SML0ALERT_IN			*/
 	PAD_CFG_GPO(GPP_C5, 0, DEEP),
 	/* C9:	Not Connected			*/
@@ -180,9 +180,9 @@ const struct pad_config gpio_table[] = {
 	/* C15:	TPM_RST				*/
 	PAD_NC(GPP_C15, NONE),
 	/* C18:	TOUCH_I2C_SDA			*/
-	PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1),
+	PAD_NC(GPP_C18, NONE),
 	/* C19:	TOUCH_I2C_CLK			*/
-	PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1),
+	PAD_NC(GPP_C19, NONE),
 	/* C22:	Not Connected			*/
 	PAD_NC(GPP_C22, NONE),
 	/* C23:	WLAN_WAKE_N			*/
@@ -232,7 +232,7 @@ const struct pad_config gpio_table[] = {
 	/* E2:	Not Connected			*/
 	PAD_NC(GPP_E2, NONE),
 	/* E3:	FPS_INT				*/
-	PAD_CFG_NF(GPP_E3, NONE, DEEP, NF1),
+	PAD_NC(GPP_E3, NONE),
 	/* E4:	Not Connected			*/
 	PAD_NC(GPP_E4, NONE),
 	/* E5:	Not Connected			*/
@@ -244,7 +244,7 @@ const struct pad_config gpio_table[] = {
 	/* E8:	EC_SLP_S0IX_N			*/
 	PAD_NC(GPP_E8, NONE),
 	/* E9:	USB2_TCP01_OC_N			*/
-	PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1),
+	PAD_NC(GPP_E9, NONE),
 	/* E10:	SPI1_TCH_PNL_CS_N		*/
 	PAD_NC(GPP_E10, NONE),
 	/* E11:	SPI1_CLK			*/

From 37846c7cc701d136c9888143d2a58ee2cbb97705 Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Fri, 4 Apr 2025 12:38:11 +0100
Subject: [PATCH 0648/3886] mb/starlabs/starbook/tgl: Add comments for eSPI
 GPIO

This is a non-functional change, and just makes it easier to read.

Change-Id: I89028c87eeab95bf4e7a35471072bb41d02b4e6c
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87170
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
---
 src/mainboard/starlabs/starbook/variants/tgl/gpio.c | 10 +++++++++-
 1 file changed, 9 insertions(+), 1 deletion(-)

diff --git a/src/mainboard/starlabs/starbook/variants/tgl/gpio.c b/src/mainboard/starlabs/starbook/variants/tgl/gpio.c
index ddf7db78a6..3c5158d6ef 100644
--- a/src/mainboard/starlabs/starbook/variants/tgl/gpio.c
+++ b/src/mainboard/starlabs/starbook/variants/tgl/gpio.c
@@ -25,6 +25,15 @@ const struct pad_config gpio_table[] = {
 	PAD_CFG_NF(GPD5, NONE, DEEP, NF1),				/* Sleep S4 */
 	PAD_CFG_NF(GPD8, NONE, DEEP, NF1),				/* Bluetooth Suspend */
 
+	/* eSPI */
+	// PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_A0, UP_20K, DEEP, NF1),	/* eSPI IO 0 */
+	// PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_A1, UP_20K, DEEP, NF1),	/* eSPI IO 1 */
+	// PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_A2, UP_20K, DEEP, NF1),	/* eSPI IO 2 */
+	// PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_A3, UP_20K, DEEP, NF1),	/* eSPI IO 3 */
+	// PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_A4, UP_20K, DEEP, NF1),	/* eSPI CS 0 */
+	// PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_A5, UP_20K, DEEP, NF1),	/* eSPI Clk */
+	// PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_A6, NONE, DEEP, NF1),	/* eSPI Reset */
+
 	/* Touchpad */
 	PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1),				/* Data */
 	PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1),				/* Clock */
@@ -90,7 +99,6 @@ const struct pad_config gpio_table[] = {
 	/* GPD11:	PM_LANPHY_EN		*/
 	PAD_NC(GPD11, NONE),
 
-	/* A6:	Not Connected(TP764)		*/
 	/* A7:	WLAN_PCM_CLK			*/
 	PAD_NC(GPP_A7, NONE),
 	/* A8:	WLAN_PCM_RST			*/

From 2df3218da81bdacbcf2869a4a7d23410131e3d16 Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Fri, 4 Apr 2025 12:41:27 +0100
Subject: [PATCH 0649/3886] mb/starlabs/starbook/tgl: Correct wireless GPIO
 group

Change-Id: I6565c3fa3d171625b0d3e538371d53d6449db180
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87171
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
---
 src/mainboard/starlabs/starbook/variants/tgl/gpio.c | 9 ++++-----
 1 file changed, 4 insertions(+), 5 deletions(-)

diff --git a/src/mainboard/starlabs/starbook/variants/tgl/gpio.c b/src/mainboard/starlabs/starbook/variants/tgl/gpio.c
index 3c5158d6ef..6cf5fabb57 100644
--- a/src/mainboard/starlabs/starbook/variants/tgl/gpio.c
+++ b/src/mainboard/starlabs/starbook/variants/tgl/gpio.c
@@ -49,7 +49,8 @@ const struct pad_config gpio_table[] = {
 	PAD_CFG_NF(GPP_F1, NONE, DEEP, NF1),				/* BRI Response */
 	PAD_CFG_NF(GPP_F2, NONE, DEEP, NF1),				/* RGI Data */
 	PAD_CFG_NF(GPP_F3, NONE, DEEP, NF1),				/* RGI Response */
-	PAD_NC(GPP_F6, NONE),						/* Modem Clock Request */
+	PAD_CFG_NF(GPP_A8, NONE, DEEP, NF2),				/* RF Reset */
+	PAD_CFG_NF(GPP_A9, NONE, DEEP, NF2),				/* Modem Clock Request */
 
 	/* Display */
 	PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1),				/* eDP Hot Plug */
@@ -101,10 +102,6 @@ const struct pad_config gpio_table[] = {
 
 	/* A7:	WLAN_PCM_CLK			*/
 	PAD_NC(GPP_A7, NONE),
-	/* A8:	WLAN_PCM_RST			*/
-	PAD_CFG_NF(GPP_A8, NONE, DEEP, NF2),
-	/* A9:	WLAN_PCM_CLKREQ0		*/
-	PAD_CFG_NF(GPP_A9, NONE, DEEP, NF2),
 	/* A10:	WLAN_PCM_IN			*/
 	PAD_NC(GPP_A10, NONE),
 	/* A12:	SATAGP_1			*/
@@ -280,6 +277,8 @@ const struct pad_config gpio_table[] = {
 	PAD_NC(GPP_F4, NONE),
 	/* F5:	GPPC_F5_MODEM_CLKREQ		*/
 	PAD_NC(GPP_F5, NONE),
+	/* F6:					*/
+	PAD_NC(GPP_F6, NONE),
 	/* F7:	BIOS_REC			*/
 	PAD_CFG_GPO(GPP_F7, 1, PLTRST),
 	/* F8:	Not Connected			*/

From 95512e1fb223cf37f56acf5201b68a04042a3274 Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Fri, 4 Apr 2025 13:06:11 +0100
Subject: [PATCH 0650/3886] mb/starlabs/starbook/tgl: Tidy GPIO comments for
 SATA

This is a non-functional change, and only makes the GPIOs easier to read.

Change-Id: Iee7121aef28618c0877c97cf454dc1a279758c21
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87173
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
---
 src/mainboard/starlabs/starbook/variants/tgl/gpio.c | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/src/mainboard/starlabs/starbook/variants/tgl/gpio.c b/src/mainboard/starlabs/starbook/variants/tgl/gpio.c
index 6cf5fabb57..b6f152681b 100644
--- a/src/mainboard/starlabs/starbook/variants/tgl/gpio.c
+++ b/src/mainboard/starlabs/starbook/variants/tgl/gpio.c
@@ -44,6 +44,9 @@ const struct pad_config gpio_table[] = {
 	PAD_CFG_GPO(GPP_A11, 1, PLTRST),				/* Reset */
 	PAD_CFG_GPO(GPP_D16, 1, DEEP),					/* Enable */
 
+	/* SATA */
+	PAD_CFG_NF(GPP_A12, UP_20K, DEEP, NF1),				/* PEDET */
+
 	/* Wireless */
 	PAD_CFG_NF(GPP_F0, NONE, DEEP, NF1),				/* BRI Data */
 	PAD_CFG_NF(GPP_F1, NONE, DEEP, NF1),				/* BRI Response */
@@ -104,8 +107,6 @@ const struct pad_config gpio_table[] = {
 	PAD_NC(GPP_A7, NONE),
 	/* A10:	WLAN_PCM_IN			*/
 	PAD_NC(GPP_A10, NONE),
-	/* A12:	SATAGP_1			*/
-	PAD_CFG_NF(GPP_A12, UP_20K, DEEP, NF1),
 	/* A13:	Not Connected			*/
 	PAD_NC(GPP_A13, NONE),
 	/* A14:	Not Connected			*/

From 9c05e9900e4415a69615cb81779902a770738fb7 Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Tue, 18 Mar 2025 13:29:25 +0000
Subject: [PATCH 0651/3886] mb/starlabs/*: Enable DDC for DDIA

Enable DDC so that GOP can read the backlight brightness from EDID. This
avoids FSP repeatedly trying and failing to read it, and also stops the
backlight brightness not being restored correctly in Linux.

Change-Id: Ic05ec3cece911f61347bceb82e5798729dcaecfe
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86914
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
---
 src/mainboard/starlabs/byte_adl/variants/mk_ii/devicetree.cb    | 2 +-
 src/mainboard/starlabs/starbook/variants/adl/devicetree.cb      | 2 +-
 src/mainboard/starlabs/starbook/variants/adl_n/devicetree.cb    | 2 +-
 src/mainboard/starlabs/starbook/variants/rpl/devicetree.cb      | 2 +-
 src/mainboard/starlabs/starfighter/variants/rpl/devicetree.cb   | 2 +-
 src/mainboard/starlabs/starlite_adl/variants/mk_v/devicetree.cb | 2 +-
 6 files changed, 6 insertions(+), 6 deletions(-)

diff --git a/src/mainboard/starlabs/byte_adl/variants/mk_ii/devicetree.cb b/src/mainboard/starlabs/byte_adl/variants/mk_ii/devicetree.cb
index 99e89aeee9..a85936813c 100644
--- a/src/mainboard/starlabs/byte_adl/variants/mk_ii/devicetree.cb
+++ b/src/mainboard/starlabs/byte_adl/variants/mk_ii/devicetree.cb
@@ -20,7 +20,7 @@ chip soc/intel/alderlake
 	device domain 0 on
 		device ref igpu		on
 			register "ddi_ports_config" = "{
-				[DDI_PORT_A]			= DDI_ENABLE_HPD,
+				[DDI_PORT_A]			= DDI_ENABLE_HPD | DDI_ENABLE_DDC,
 				[DDI_PORT_B]			= DDI_ENABLE_HPD | DDI_ENABLE_DDC,
 			}"
 		end
diff --git a/src/mainboard/starlabs/starbook/variants/adl/devicetree.cb b/src/mainboard/starlabs/starbook/variants/adl/devicetree.cb
index 7588e93181..c11cc71789 100644
--- a/src/mainboard/starlabs/starbook/variants/adl/devicetree.cb
+++ b/src/mainboard/starlabs/starbook/variants/adl/devicetree.cb
@@ -32,7 +32,7 @@ chip soc/intel/alderlake
 			register "gfx"				= "GMA_DEFAULT_PANEL(0)"
 			register "ddi_portA_config"		= "1"
 			register "ddi_ports_config" = "{
-				[DDI_PORT_A]				= DDI_ENABLE_HPD,
+				[DDI_PORT_A]				= DDI_ENABLE_HPD | DDI_ENABLE_DDC,
 				[DDI_PORT_B]				= DDI_ENABLE_HPD | DDI_ENABLE_DDC,
 			}"
 		end
diff --git a/src/mainboard/starlabs/starbook/variants/adl_n/devicetree.cb b/src/mainboard/starlabs/starbook/variants/adl_n/devicetree.cb
index 73708f50d7..f0f16c4337 100644
--- a/src/mainboard/starlabs/starbook/variants/adl_n/devicetree.cb
+++ b/src/mainboard/starlabs/starbook/variants/adl_n/devicetree.cb
@@ -52,7 +52,7 @@ chip soc/intel/alderlake
 
 			register "ddi_portA_config"		= "1"
 			register "ddi_ports_config" = "{
-				[DDI_PORT_A]				= DDI_ENABLE_HPD,
+				[DDI_PORT_A]				= DDI_ENABLE_HPD | DDI_ENABLE_DDC,
 				[DDI_PORT_B]				= DDI_ENABLE_HPD | DDI_ENABLE_DDC,
 			}"
 		end
diff --git a/src/mainboard/starlabs/starbook/variants/rpl/devicetree.cb b/src/mainboard/starlabs/starbook/variants/rpl/devicetree.cb
index 1905e3ef1a..645bd5009e 100644
--- a/src/mainboard/starlabs/starbook/variants/rpl/devicetree.cb
+++ b/src/mainboard/starlabs/starbook/variants/rpl/devicetree.cb
@@ -34,7 +34,7 @@ chip soc/intel/alderlake
 			register "gfx"					= "GMA_DEFAULT_PANEL(0)"
 			register "ddi_portA_config"			= "1"
 			register "ddi_ports_config" = "{
-				[DDI_PORT_A]				= DDI_ENABLE_HPD,
+				[DDI_PORT_A]				= DDI_ENABLE_HPD | DDI_ENABLE_DDC,
 				[DDI_PORT_B]				= DDI_ENABLE_HPD | DDI_ENABLE_DDC,
 			}"
 		end
diff --git a/src/mainboard/starlabs/starfighter/variants/rpl/devicetree.cb b/src/mainboard/starlabs/starfighter/variants/rpl/devicetree.cb
index e75df6f9ff..a73c4f69f2 100644
--- a/src/mainboard/starlabs/starfighter/variants/rpl/devicetree.cb
+++ b/src/mainboard/starlabs/starfighter/variants/rpl/devicetree.cb
@@ -33,7 +33,7 @@ chip soc/intel/alderlake
 			register "gfx"				= "GMA_DEFAULT_PANEL(0)"
 			register "ddi_portA_config"		= "1"
 			register "ddi_ports_config" = "{
-				[DDI_PORT_A]				= DDI_ENABLE_HPD,
+				[DDI_PORT_A]				= DDI_ENABLE_HPD | DDI_ENABLE_DDC,
 				[DDI_PORT_B]				= DDI_ENABLE_HPD | DDI_ENABLE_DDC,
 			}"
 		end
diff --git a/src/mainboard/starlabs/starlite_adl/variants/mk_v/devicetree.cb b/src/mainboard/starlabs/starlite_adl/variants/mk_v/devicetree.cb
index eb711a0745..d9996caf29 100644
--- a/src/mainboard/starlabs/starlite_adl/variants/mk_v/devicetree.cb
+++ b/src/mainboard/starlabs/starlite_adl/variants/mk_v/devicetree.cb
@@ -62,7 +62,7 @@ chip soc/intel/alderlake
 
 			register "ddi_portA_config"			= "1"
 			register "ddi_ports_config" = "{
-				[DDI_PORT_A]				= DDI_ENABLE_HPD,
+				[DDI_PORT_A]				= DDI_ENABLE_HPD | DDI_ENABLE_DDC,
 				[DDI_PORT_B]				= DDI_ENABLE_HPD | DDI_ENABLE_DDC,
 			}"
 		end

From 44921d386c6b08746afa735fbab2844a81c16e5e Mon Sep 17 00:00:00 2001
From: Martin Roth <gaumless@gmail.com>
Date: Sun, 1 May 2022 20:29:51 -0600
Subject: [PATCH 0652/3886] Documentation/internals: Add devicetree
 documentation

Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I2a43a96911844bd2b682004d5423126ad00a4bf3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84709
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nicholas Chin <nic.c3.14@gmail.com>
---
 Documentation/index.md                |   1 +
 Documentation/internals/devicetree.md | 684 ++++++++++++++++++++++++++
 Documentation/internals/index.md      |  13 +
 3 files changed, 698 insertions(+)
 create mode 100644 Documentation/internals/devicetree.md
 create mode 100644 Documentation/internals/index.md

diff --git a/Documentation/index.md b/Documentation/index.md
index 7ba88f30ef..b564c5c71d 100644
--- a/Documentation/index.md
+++ b/Documentation/index.md
@@ -219,6 +219,7 @@ Community <community/index.md>
 Payloads <payloads.md>
 Distributions <distributions.md>
 Technotes <technotes/index.md>
+Internal APIs & Configuration <internals/index.md>
 ACPI <acpi/index.md>
 Native Graphics Initialization with libgfxinit <gfx/libgfxinit.md>
 Display panel <gfx/display-panel.md>
diff --git a/Documentation/internals/devicetree.md b/Documentation/internals/devicetree.md
new file mode 100644
index 0000000000..c6f5c4cc68
--- /dev/null
+++ b/Documentation/internals/devicetree.md
@@ -0,0 +1,684 @@
+# Devicetree
+
+## Introduction to the coreboot devicetree
+
+The first thing that may come to mind when one hears "DeviceTree" is a
+different sort of description file that is generally passed to the Linux
+kernel to describe a system's components. Both that devicetree and
+coreboot's devicetree serve fundamentally the same purpose, but are
+otherwise unrelated and have completely different syntax. The term
+devicetree was used long before either version was created, and was
+initially used in coreboot as a generic term.
+
+coreboot's devicetree's main use is to define and describe the runtime
+configuration and settings of the hardware on a board, chip or device
+level. It defines which of the functions of the chips on the board are
+enabled, and how they're configured.
+
+The devicetree file is parsed during the build process by a utility
+named `sconfig`, which translates the devicetree into a tree of C
+structures containing the included devices. This code is placed in the
+file `static.c` and a couple of header files, all under the `build`
+directory. This file is then built into the binaries for the various
+coreboot stages and is referred to during the coreboot boot process.
+
+For the early stages of the coreboot boot process, the data that is
+generated by `sconfig` is a useful resource, but this structure is the
+critical architectural glue of ramstage. This structure gets filled in
+with pointers to every chip's initialization code, allowing ramstage to
+find and initialize those devices through the `chip_operations`
+structures.
+
+
+### History of coreboot's devicetree
+
+The initial devicetree in coreboot was introduced in 2003 by Ron Minnich
+as a part of the linuxbios config file, 'config.lb'. At this point both
+the devicetree and config options were in the same file. In 2009,
+when Kconfig was added into the coreboot build, devicetree was split
+out into its own file for each mainboard in a commit with this message:
+
+```text
+devicetree.cb
+
+The devicetree that formerly resided in src/mainboard/*/*/Config.lb.
+
+Just without the build system crap
+```
+
+The devicetree structure was initially mainly used only in ramstage for
+PCI device enumeration, configuration and resource allocation. It has
+since expanded for use in the pre-ram stages as a read-only structure.
+
+The language used in the devicetree has been expanded greatly since it
+was first introduced as well, adding new features every year or so.
+
+
+### Devicetree Registers
+
+In coreboot, the devicetree register setting is one of the two main
+methods used to configure a board's properties. In this way, devicetree
+is similar in function to Kconfig. It's more flexible in many ways as
+it can specify not only single values, but also arrays or structures.
+It's also even more static than Kconfig because there's no update
+mechanism for it other than editing the devicetree files.
+
+Chip-specific configuration values are often set using `register`
+definitions within a `chip` block, corresponding to a `struct` defined
+in the chip's `chip.h` file.
+
+For example, in a `chip drivers/gpio/acpi` block, you might set a GPE:
+
+```text
+register "gpe0_sts" = "0x42"
+```
+
+
+### Adding new static configuration options: Devicetree or Kconfig
+
+When adding options for a new board or chip, there is frequently a
+decision that needs to be made about how the option should be added.
+Using the devicetree or Kconfig are the two typical methods of
+build-time configuration. Below are some general guidelines on when to
+use each.
+
+Kconfig should be used if the option configures the build in a Makefile,
+or if the option is something that should be user selectable. Kconfig
+is also preferred if the configuration is a global option and not limited
+to a single chip. Another thing Kconfig excels at is handling decisions
+based on other configuration options, which devicetree cannot do.
+
+Devicetree should obviously be used to define the hardware hierarchy.
+It's also preferred if the option is only used in C code and is static
+for a mainboard, or if the option is chip-specific. As mentioned
+earlier, devicetree registers can also define structures or arrays,
+which Kconfig cannot.
+
+Both Kconfig and devicetree can be used in C code for runtime
+configuration, but there's a significant difference in how they are
+handled. Because Kconfig generates a `#define` for the choice, the
+compiler can eliminate code paths not used by the option. Devicetree
+options, however, are actual runtime selections, and the code for all
+choices remains in the final build.
+
+
+## Basic Devicetree Syntax
+
+The coreboot devicetree uses a custom language parsed by the `sconfig`
+utility. Here's a brief overview of the main keywords and concepts:
+
+*   **`chip <directory>`**: Defines a collection of devices associated
+    with the code in the specified directory. `sconfig` may also parse a
+    `chip.h` file within this directory for register definitions.
+*   **`device <type> <id> [on|off] [alias <name>] ... end`**: Defines a
+    specific hardware device.
+    *   `<type>`: Specifies the device type (e.g., `pci`, `cpu_cluster`,
+        `i2c`).
+    *   `<id>`: A unique identifier for the device within its type/bus
+        (e.g., PCI BDF `17.0`, I2C address `0x50`).
+    *   `on`/`off`: Enables or disables the device definition.
+    *   `alias <name>`: Assigns a human-readable alias for referencing
+        this device elsewhere (often used in `chipset.cb`).
+    *   `end`: Marks the end of the device definition block. Registers
+        and other properties are defined between `device` and `end`.
+*   **`register "<name>" = <value>`**: Sets the value of a configuration
+    register defined in the corresponding `chip.h` structure. The value
+    can be a number, string, or complex structure initialization.
+*   **`probe <field> <option>`**: Used for firmware configuration
+    (`fw_config`), indicating a setting should be probed at runtime.
+*   **`ops "<identifier>"`**: Associates a `chip_operations` structure
+    with the device, used primarily in ramstage for device initialization.
+*   **`fw_config field <name> size <bits> ... end`**: Defines a firmware
+    configuration field, often used for passing board-specific data to
+    payloads. Options within the field are defined using `option`.
+*   **`ref <alias>`**: Used within `device` definitions in `devicetree.cb`
+    or `overridetree.cb` to refer to a device defined (usually via an
+    `alias`) in a lower-level file like `chipset.cb`.
+*   **`# <comment text>`**: Single-line comments.
+
+Device definitions can be nested within `chip` blocks. `end` keywords
+close the current block (`device` or `chip`).
+
+
+## Three levels of devicetree files
+
+There are currently three different levels of devicetrees used to build
+up the structure of components and register values in coreboot. From
+the lowest, most general level to the highest and most specific, they
+are `chipset.cb`, `devicetree.cb`, and `overridetree.cb`.
+
+Unless there's a specific reason to name them something other than these
+names, they should be used.
+
+For newer SoCs and chipsets, there will generally be a `chipset.cb` file.
+Every mainboard requires a `devicetree.cb` file, although it can be empty
+if everything is inherited from the `chipset.cb`. An `overridetree.cb`
+file is only required if variants have differences from the primary
+mainboard's `devicetree.cb`.
+
+
+### SoC / chipset level, `chipset.cb`
+
+The `chipset.cb` file was added in October 2020, allowing a single
+chipset or SoC to provide a "base level" devicetree, reducing
+duplication between mainboards.
+
+The `chipset.cb` file also typically defines human-readable "aliases"
+for particular devices so that mainboards can use those instead of PCI
+device/function numbers or other hardware identifiers.
+
+The use of the `chipset.cb` file is specified in Kconfig by the
+`CHIPSET_DEVICETREE` symbol, which provides the path to the file.
+
+In a `chipset.cb` file, you might see lines like this:
+
+```text
+# Chip definition for the SoC/chipset itself
+chip soc/intel/common/block
+
+    # Define PCI device 17.0, alias it to "sata", and default it off
+    device pci 17.0 alias sata off end
+
+    # Define PCI device 1e.0, alias it to "uart0", and default it off
+    device pci 1e.0 alias uart0 off end
+
+end # chip soc/intel/common/block
+```
+
+This defines the devices, assigns aliases, and sets their default state.
+
+
+### Primary mainboard level, `devicetree.cb`
+
+Each mainboard must have a `devicetree.cb` file. The filename and path are
+typically set by the `DEVICETREE` Kconfig symbol, defaulting to
+`src/mainboard/<VENDOR>/<BOARD>/devicetree.cb`.
+
+If a mainboard using the above `chipset.cb` wanted both devices enabled,
+its `devicetree.cb` might contain:
+
+```text
+# Reference the SATA device by its alias and enable it
+device ref sata on end
+
+# Reference the UART0 device by its alias and enable it
+device ref uart0 on end
+```
+
+The `ref` keyword looks up the device (usually by alias) defined in a
+lower-level file (`chipset.cb` in this case) and modifies its properties.
+
+
+### Mainboard variant level, `overridetree.cb`
+
+Introduced in 2018 to reduce duplication and maintenance for board
+variants, the `overridetree.cb` file is the most specific level.
+
+This allows a base `devicetree.cb` at the top mainboard level shared by
+all variants. Each variant then only needs an `overridetree.cb` to
+specify its differences.
+
+The override tree filename is set in Kconfig with the
+`OVERRIDE_DEVICETREE` symbol and is typically named `overridetree.cb`.
+
+Finally, if one variant of the mainboard lacked a SATA connector, it
+could disable the SATA device again using the following in its specific
+`overridetree.cb`:
+
+```text
+# Reference the SATA device by alias and disable it for this variant
+device ref sata off end
+```
+
+
+## Additional files
+
+
+### `chip.h` files
+
+coreboot looks at a "chip" as a collection of devices. This collection
+can be a single logical device or multiple different ones. The `chip`
+keyword starts this collection. Following the `chip` keyword is a
+directory path (relative to `src/`) containing the code for that chip
+or logical block of hardware.
+
+There may optionally be a `chip.h` file in that directory. If present,
+`sconfig` parses this file to define a C structure containing the
+"register definitions" for the chip. The values for this structure's
+members are set using the `register` keyword in one of the devicetree
+files (`chipset.cb`, `devicetree.cb`, `overridetree.cb`). If not
+explicitly set, members typically default to 0 or follow standard C
+initialization rules. The `chip.h` file frequently also contains C
+macros, enums, and sub-structures used for setting the members of the
+main register structure.
+
+The C structure for the chip's register definition is named after the
+directory containing the `chip.h` file, with slashes (`/`) changed to
+underscores (`_`), and `_config` appended. The leading `src/` is omitted.
+
+This means that a line in a devicetree file like:
+`chip drivers/i2c/hid`
+would cause `sconfig` to look for `src/drivers/i2c/hid/chip.h`. If found,
+the register definition structure it contains would be named
+`drivers_i2c_hid_config`.
+
+Here is the content of `src/drivers/i2c/hid/chip.h`:
+
+```c
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef __DRIVERS_I2C_HID_CHIP_H__
+#define __DRIVERS_I2C_HID_CHIP_H__
+#include <drivers/i2c/generic/chip.h>
+#define I2C_HID_CID         "PNP0C50"
+
+struct drivers_i2c_hid_config {
+        struct drivers_i2c_generic_config generic;
+        uint8_t hid_desc_reg_offset;
+};
+
+#endif /* __I2C_HID_CHIP_H__ */
+```
+
+In a devicetree, you could set `hid_desc_reg_offset` like this:
+
+```text
+chip drivers/i2c/hid
+    device i2c 0x2c on
+        # Set the HID descriptor register offset
+        register "hid_desc_reg_offset" = "0x01"
+    end
+end
+```
+
+
+## The `sconfig` utility and generated files
+
+
+### `util/sconfig`
+
+`sconfig` is the tool that parses the coreboot devicetrees and turns
+them into a collection of C structures. This is a coreboot-specific
+tool, built using flex & bison to define and parse the domain-specific
+language used by coreboot's devicetree.
+
+`sconfig` is called by the makefiles during the build process and doesn't
+generally need to be run directly. If run manually (e.g.,
+`build/util/sconfig/sconfig --help`), it shows its command-line options.
+The exact options might vary slightly, but typically include:
+
+```text
+usage: sconfig <options>
+
+ -c | --output_c          : Path to output static.c file (required)
+ -r | --output_h          : Path to header static.h file (required)
+ -d | --output_d          : Path to header static_devices.h file (required)
+ -f | --output_f          : Path to header static_fw_config.h file (required)
+ -m | --mainboard_devtree : Path to mainboard devicetree file (required)
+ -o | --override_devtree  : Path to override devicetree file (optional)
+ -p | --chipset_devtree   : Path to chipset/SOC devicetree file (optional)
+```
+
+
+### `sconfig` inputs
+
+The `sconfig` input files `chip.h`, `chipset.cb`, `devicetree.cb`, and
+`overridetree.cb` were discussed previously. As the usage above shows,
+the only required input file is the mainboard devicetree (`-m`). The
+additional devicetree files, `chipset.cb` (`-p`) and `overridetree.cb`
+(`-o`), are optional. The `chip.h` files do not need to be specified on
+the command line; their locations are determined by the `chip` directory
+paths within the `.cb` files.
+
+Constructing the devicetree input files will be discussed later.
+
+
+### `sconfig` outputs
+
+#### `static.c`
+
+This is the primary C file generated by `sconfig`. It contains the static
+definitions of the device tree structures, including device nodes, bus
+links, and register configuration data.
+
+For historic reasons, `static.c` is generated in the
+`build/mainboard/<VENDOR>/<BOARD>` directory.
+
+
+#### `static.h`
+
+The `static.h` file is the main header file included by most coreboot C
+files that need access to the devicetree data. It is included by
+`src/include/device/device.h`, which provides the primary API
+(definitions, structures, function prototypes) for interacting with the
+devicetree-generated output.
+
+`static.h` used to contain all generated declarations directly. As of
+October 2020, it simply includes the other two generated header files
+(`static_devices.h` and `static_fw_config.h`). This separation allows
+the firmware config options (`fw_config`) to be used independently, for
+example, by a payload.
+
+
+#### `static_devices.h`
+
+The file `static_devices.h` contains `extern` declarations for all the
+device structures (`struct device`) defined in `static.c`. This allows
+other C files to reference the generated device tree nodes.
+
+
+#### `static_fw_config.h`
+
+`static_fw_config.h` contains only the `FW_CONFIG_FIELD_*` macro results,
+derived from `fw_config` entries in the devicetree. This makes it easily
+consumable by payloads or other components needing platform `FW_CONFIG`
+data without pulling in the full device tree structure.
+
+
+## Devicetree Example
+
+
+### A very simple devicetree
+
+This is the `devicetree.cb` file from
+`src/mainboard/sifive/hifive-unleashed`, with line numbers added for
+reference. Non-x86 devicetree files are often simpler than their x86
+counterparts.
+
+```text
+    1  # SPDX-License-Identifier: GPL-2.0-only
+    2  chip soc/sifive/fu540
+    3          device cpu_cluster 0 on  end
+    4  end
+```
+
+This can be broken down as follows:
+
+Line 1: Comments start with `#`. This line is the SPDX license
+identifier for the file.
+
+Line 2: `chip soc/sifive/fu540` starts a block for the SiFive FU540 SoC.
+`sconfig` will look for code and potentially a `chip.h` in
+`src/soc/sifive/fu540/`.
+
+Line 3: `device cpu_cluster 0 on end` defines a device of type
+`cpu_cluster` with ID `0`. It's marked as enabled (`on`). Since there are
+no registers or other properties defined between `device` and `end`, this
+is a simple enablement entry.
+
+Line 4: `end` closes the block started by the `chip` keyword on line 2.
+
+
+### Generated files
+
+Continuing with the simple `sifive/hifive-unleashed` mainboard example,
+these are the files generated by `sconfig` from the devicetree above (as
+of mid-2022; exact output can change). Because the input devicetree is
+minimal, the generated files are also quite sparse.
+
+
+#### `build/static.h`
+
+```c
+#ifndef __STATIC_DEVICE_TREE_H
+#define __STATIC_DEVICE_TREE_H
+
+#include <static_fw_config.h>
+#include <static_devices.h>
+
+#endif /* __STATIC_DEVICE_TREE_H */
+```
+(Includes the other generated headers.)
+
+
+#### `build/static_devices.h`
+
+```c
+#ifndef __STATIC_DEVICES_H
+#define __STATIC_DEVICES_H
+#include <device/device.h>
+/* expose_device_names */
+#endif /* __STATIC_DEVICE_NAMES_H */
+```
+(Includes `device/device.h` but contains no actual device externs beyond
+the implicit root device, as the simple example didn't define complex
+devices requiring separate structs.)
+
+
+#### `build/static_fw_config.h`
+
+```c
+#ifndef __STATIC_FW_CONFIG_H
+#define __STATIC_FW_CONFIG_H
+#endif /* __STATIC_FW_CONFIG_H */
+```
+(Empty because the example `devicetree.cb` did not use `fw_config`.)
+
+
+#### `build/mainboard/sifive/hifive-unleashed/static.c`
+
+##### Includes
+
+```text
+1  #include <boot/coreboot_tables.h>
+2  #include <device/device.h>
+3  #include <device/pci.h>
+4  #include <fw_config.h>
+5  #include <static.h>
+```
+
+Lines 1-5: Includes header files required for the following structure
+definitions and macros.
+
+
+##### Declarations for chip-ops
+
+```text
+6
+7   #if !DEVTREE_EARLY
+8   __attribute__((weak)) struct chip_operations mainboard_ops = {};
+9   extern struct chip_operations soc_sifive_fu540_ops;
+10  #endif
+```
+
+Lines 7 & 10: The `ops` structures inside this `#if !DEVTREE_EARLY` block
+are only relevant and linked in ramstage.
+
+Lines 8-9: Declarations for `chip_operations` structures. This section
+expands as more chips are added to the devicetree.
+*   Line 8: `mainboard_ops` is always present. It's defined as `weak`
+    because the mainboard C code may or may not provide this structure.
+*   Line 9: This `extern` is generated by the `chip soc/sifive/fu540`
+    declaration in the `devicetree.cb`. There will be a similar line for
+    every `chip` declared.
+
+##### `STORAGE` definition
+
+```text
+11
+12  #define STORAGE static __unused DEVTREE_CONST
+```
+
+Line 12: This macro conditionally adds `const` based on the build stage.
+It resolves to `static __unused const` in early stages (pre-RAM) and
+`static __unused` in ramstage, where the structures might be modified.
+
+##### Structure definitions
+
+```text
+13
+14
+15  /* pass 0 */
+16  STORAGE struct bus dev_root_links[];
+17  STORAGE struct device _dev_0;
+18  DEVTREE_CONST struct device * DEVTREE_CONST last_dev = &_dev_0;
+```
+
+Lines 16-18: Forward declarations of the static structures generated by
+`sconfig` based on the devicetree input. `_dev_0` corresponds to the
+`cpu_cluster 0` device.
+
+##### Register Structures
+
+```text
+19
+20  /* chip configs */
+```
+
+Line 20: This section is empty for this mainboard because the
+`soc/sifive/fu540/chip.h` file (if it exists) does not define a register
+structure, or the devicetree did not instantiate it using `register`.
+Otherwise, this section would contain the static initialization of chip
+configuration structures based on `register` entries.
+
+##### `dev_root` structure
+
+Lines 21-44: `dev_root`. This structure represents the root of the
+coreboot device tree. It is always generated, regardless of the content
+of the `devicetree.cb` file. It serves as the entry point for traversing
+the tree.
+
+```text
+21
+22  /* pass 1 */
+23  DEVTREE_CONST struct device dev_root = {
+24          #if !DEVTREE_EARLY
+25                  .ops = &default_dev_ops_root,
+26          #endif
+27                  .bus = &dev_root_links[0],
+28                  .path = { .type = DEVICE_PATH_ROOT },
+29                  .enabled = 1,
+30                  .hidden = 0,
+31                  .mandatory = 0,
+32                  .on_mainboard = 1,
+33                  .link_list = &dev_root_links[0],
+34                  .sibling = NULL,
+35          #if !DEVTREE_EARLY
+36                  .chip_ops = &mainboard_ops,
+37                  .name = mainboard_name,
+38          #endif
+39                  .next=&_dev_0,
+40          #if !DEVTREE_EARLY
+41          #if CONFIG(GENERATE_SMBIOS_TABLES)
+42          #endif
+43          #endif
+44  };
+```
+
+*   Lines 24-26: Points to a default ramstage `device_operation`
+    structure (`default_dev_ops_root`) found in
+    `src/device/root_device.c`. This structure typically does little by
+    default but can be overridden or utilized by mainboard code via the
+    `chip_operations->enable_dev()` hook for tasks like ACPI table
+    generation.
+*   Line 27: `.bus`: Pointer to the bus structure associated with this
+    device. For the root device, this points to its own bus structure.
+*   Line 28: `.path`: The unique path identifier for this device. The type
+    is `DEVICE_PATH_ROOT`.
+*   Lines 29-32: Device status flags.
+    *   `enabled`: Set based on `on`/`off` in the devicetree (always on
+        for `dev_root`). Can be modified later (e.g., during enumeration
+        in ramstage).
+    *   `hidden`, `mandatory`: Set only by corresponding keywords in the
+        devicetree (not used here).
+    *   `on_mainboard`: Indicates the device was defined in the static
+        devicetree, as opposed to being discovered dynamically (e.g., via
+        PCI enumeration). Always true for `dev_root`.
+*   Line 33: `.link_list`: Pointer to the list of child buses attached to
+    this device.
+*   Line 34: `.sibling`: Pointer to the next device at the same level in
+    the tree. Should always be `NULL` for `dev_root`.
+*   Line 36: `.chip_ops`: Pointer to the mainboard's `chip_operations`
+    structure (the `weak` `mainboard_ops`). Although not a physical
+    chip, the mainboard gets this to hook into the boot process like
+    other chips.
+*   Line 37: `.name`: A string identifier, typically the mainboard name,
+    set at build time (from `src/device/root_device.c`).
+*   Line 39: `.next`: Pointer used internally by `sconfig` during tree
+    construction. Points to the next device structure processed (`_dev_0`).
+
+##### `dev_root_links`
+
+Lines 45-52: The `dev_root` bus structure array.
+
+This array (`struct bus`) holds pointers defining the bus topology. Each
+element represents a link on a bus. `dev_root` acts as the bridge for the
+top-level bus.
+
+A new bus structure array is typically created for each distinct bus type
+or domain originating from a bridge device in the devicetree (e.g., PCI
+domain 0, LPC bus).
+
+```text
+45  STORAGE struct bus dev_root_links[] = {
+46          [0] = {
+47                  .link_num = 0,
+48                  .dev = &dev_root,
+49                  .children = &_dev_0,
+50                  .next = NULL,
+51          },
+52  };
+```
+
+*   Line 47: `.link_num`: Index of this link within the bus array.
+*   Line 48: `.dev`: Pointer back to the bridge device structure for this
+    bus (`dev_root`).
+*   Line 49: `.children`: Pointer to the first child device structure on
+    this bus (`_dev_0`).
+*   Line 50: `.next`: Pointer to the next bridge device on the *parent*
+    bus. Since `dev_root` has no parent bus, this is `NULL`.
+
+##### `_dev_0`
+
+Lines 53-72: The `cpu_cluster` device structure (`_dev_0`).
+
+This structure corresponds directly to the
+`device cpu_cluster 0 on end` line in the `devicetree.cb`.
+
+```text
+53  STORAGE struct device _dev_0 = {
+54          #if !DEVTREE_EARLY
+55                  .ops = NULL,
+56          #endif
+57                  .bus = &dev_root_links[0],
+58                  .path = {.type=DEVICE_PATH_CPU_CLUSTER,{.cpu_cluster={ .cluster = 0x0 }}},
+59                  .enabled = 1,
+60                  .hidden = 0,
+61                  .mandatory = 0,
+62                  .on_mainboard = 1,
+63                  .link_list = NULL,
+64                  .sibling = NULL,
+65          #if !DEVTREE_EARLY
+66                  .chip_ops = &soc_sifive_fu540_ops,
+67          #endif
+68          #if !DEVTREE_EARLY
+69          #if CONFIG(GENERATE_SMBIOS_TABLES)
+70          #endif
+71          #endif
+72  };
+```
+
+*   Lines 54-56: `.ops`: Pointer to a `device_operations` structure. This
+    is `NULL` because this entry represents the `chip` itself, not a
+    specific functional sub-device requiring device-level operations. The
+    chip-level operations are handled by `chip_ops`.
+*   Line 57: `.bus`: Pointer to the bus structure this device resides on.
+    Since it's directly under `dev_root`, it points to `dev_root_links[0]`.
+*   Line 58: `.path`: The unique device path structure (defined in
+    `src/include/device/path.h`). Type is `DEVICE_PATH_CPU_CLUSTER`,
+    and the cluster ID is `0`, matching the devicetree entry. This path
+    is used when searching the tree (e.g., with `dev_find_path()`).
+*   Lines 59-62: Enumeration Status. Similar to `dev_root`. `enabled = 1`
+    comes from the `on` keyword.
+*   Line 63: `.link_list`: Pointer to child buses. `NULL` because this
+    `cpu_cluster` device doesn't bridge to any further buses in this
+    simple example.
+*   Line 64: `.sibling`: Pointer to the next device at the same level
+    (i.e., another device directly under `dev_root`). `NULL` as it's the
+    only child.
+*   Lines 65-67: `.chip_ops`: Pointer to the processor's `chip_operations`
+    structure (`soc_sifive_fu540_ops`), used in ramstage for SoC/CPU
+    initialization steps. This link comes from the `chip soc/sifive/fu540`
+    declaration.
+*   Lines 68-71: Placeholder for SMBIOS information, enabled by Kconfig.
+    Not used in this example.
diff --git a/Documentation/internals/index.md b/Documentation/internals/index.md
new file mode 100644
index 0000000000..01d56967fb
--- /dev/null
+++ b/Documentation/internals/index.md
@@ -0,0 +1,13 @@
+# coreboot internals
+
+This section contains documentation about the configuration and
+programming APIs internal to coreboot
+
+## Configuration
+
+```{toctree}
+:maxdepth: 1
+
+coreboot devicetree <devicetree.md>
+
+```

From 712dfc175979a85a9075e971b4674cce3e19d8d9 Mon Sep 17 00:00:00 2001
From: Martin Roth <gaumless@gmail.com>
Date: Sun, 1 May 2022 20:31:47 -0600
Subject: [PATCH 0653/3886] Documentation/internals: Add devicetree language
 documentation

Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: If868ad9a87cb2903bf144996fe3b87d29d4fc755
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84710
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nicholas Chin <nic.c3.14@gmail.com>
---
 .../internals/devicetree_language.md          | 1309 +++++++++++++++++
 Documentation/internals/index.md              |    1 +
 2 files changed, 1310 insertions(+)
 create mode 100644 Documentation/internals/devicetree_language.md

diff --git a/Documentation/internals/devicetree_language.md b/Documentation/internals/devicetree_language.md
new file mode 100644
index 0000000000..0609559ee9
--- /dev/null
+++ b/Documentation/internals/devicetree_language.md
@@ -0,0 +1,1309 @@
+# Devicetree Language
+
+Devicetrees use what's called a Domain Specific Language, so you need to
+follow the rules of the language when you're writing a devicetree.
+Fortunately, it's a relatively simple language, and because its use is
+so limited, it can frequently be learned just by following existing
+examples.
+
+
+## Comments
+
+Comments in the devicetree are all single line style. They use the '#'
+character to start the comment, and go to the end of the line.
+
+
+### Comment Style
+
+*   Put a space between the pound sign and the comment.
+    *   \# Good
+    *   \#Bad
+*   Sentence fragments are fine, but don't end them with a period.
+
+
+### When to use comments
+
+There are standard locations where comments are typically used and
+expected.
+
+
+#### Starting a group of settings
+
+Similar to commenting a function with the intent of the function, it can
+be useful to describe at the top of a block of settings with what's
+being configured.
+
+Below is a good example.
+
+```text
+# VR Settings Configuration for 4 Domains
+# +----------------+-----------+-----------+-------------+----------+
+# | Domain/Setting |    SA     |    IA     | GT Unsliced |    GT    |
+# +----------------+-----------+-----------+-------------+----------+
+# | Psi1Threshold  | 20A       | 20A       | 20A         | 20A      |
+# | Psi2Threshold  | 4A        | 5A        | 5A          | 5A       |
+# | Psi3Threshold  | 1A        | 1A        | 1A          | 1A       |
+# | Psi3Enable     | 1         | 1         | 1           | 1        |
+# | Psi4Enable     | 1         | 1         | 1           | 1        |
+# | ImonSlope      | 0         | 0         | 0           | 0        |
+# | ImonOffset     | 0         | 0         | 0           | 0        |
+# | IccMax         | 7A        | 34A       | 35A         | 35A      |
+# | VrVoltageLimit | 1.52V     | 1.52V     | 1.52V       | 1.52V    |
+# | AC LoadLine    | 15 mOhm   | 5.7 mOhm  | 5.2 mOhm    | 5.2 mOhm |
+# | DC LoadLine    | 14.3 mOhm | 4.83 mOhm | 4.2 mOhm    | 4.2 mOhm |
+# +----------------+-----------+-----------+-------------+----------+
+```
+
+
+#### End of keyword blocks
+
+If there are multiple end statements in a row, and it's not instantly
+obvious which end statement closes which keyword block, It's useful to
+add a comment to say what's being ended.
+
+Below, we have three end statements in a row and the start of these
+blocks are probably close to the top of the file. Identifying what the
+'end' statement is closing can be determined by the spacing, but it's
+still useful to note it with a comment.
+
+```text
+        end # agesa northbridge
+    end # domain
+end # northbridge/amd/agesa/family14/root_complex
+```
+
+
+#### Identifying the reason for a setting
+
+Registers which don't have a name that makes it obvious what is being
+set, or don't have a macro that identifies what it's being set to should
+be commented.
+
+The register setting and macro below both describe what the setting is,
+but don't describe what they're being used for. Adding the comment of
+"Camera", gives the reader the extra information to know what's on that
+USB port, and understand that you (generally) don't need overcurrent
+protection for an internal camera.
+
+```text
+register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # Camera
+```
+
+This below register is well named and tells you that there's going to be
+a delay of 12ms, but without the comment, you don't know why.
+
+```text
+register "stop_delay_ms" = "12" # NIC needs time to quiesce
+```
+
+
+#### Devices without aliases
+
+It's been common in the past to comment device identifiers with what the
+device is, but this may be less needed now with aliases, which allow
+devices to be named in a meaningful way.
+
+For older platforms which don't have aliases set in the chipset.cb file,
+or for non chipset devices, it's still useful to add a comment after the
+device is set.
+
+
+### When not to use comments
+
+#### Magic numbers
+
+This overlaps somewhat with the next section, but if you find yourself
+having to put in a comment to explain what's being set, evaluate whether
+it can be expressed as a macro instead.
+
+```
+register "PmConfigSlpS3MinAssert" = "2"    # 50ms
+```
+
+Instead of using the magic number 2, use a macro, just as you'd be
+expected to do in your code. It's not obvious without the comment what
+2 means, so use a macro instead.
+
+If there's some reason that a macro cannot be used, then sure, add a
+comment, but this should be very unusual.
+
+#### Redundant comments
+
+With good naming, comments may not be needed.
+
+Example of redundant comments:
+
+```text
+register "ipc1" = "0x00000000" # IPC1
+```
+
+```text
+register "link_freq[0]" = "360 * MHz" # 360 MHz
+```
+
+#### Devices with aliases
+
+For older chipset or SoC devices, or for non chipset devices that don't
+have a chipset.cb file, it's still desirable to use comments on the
+'device' line, but if the device has an alias, it should be used.
+
+
+## Registers
+
+### Register Names
+
+Any registers which encode a value that has any sort of unit should
+include the unit in the name instead of in a comment.
+
+The name "tFAW" in the register below is taken directly from the name in
+the spec, but adding the units makes it a lot easier to understand.
+
+```text
+register "tFAW" = "40000"                   # picoseconds
+```
+
+### Use Macros for encoded values
+
+If the value associated with the register encodes the unit, instead of
+entering the value directly, add a macro for the value.
+
+```text
+register "PchPmSlpS3MinAssert" = "3" # 50ms
+```
+
+This would be easier to understand if it had a macro, not just a magic
+number, as seen below.
+
+```text
+register "PchPmSlpS3MinAssert" = "ASSERT_50_MILLISEC"
+```
+
+## Devicetree Keywords
+
+alias, as, chip, cpu, cpu_cluster, device, domain, drq, end, field,
+fw_config, generic, gpio, hidden, i2c, inherit, io, ioapic, ioapic_irq,
+lapic, mandatory, mmio, off, on, option, pci, pnp, probe, ref, register,
+smbios_dev_info, smbios_slot_desc, spi, subsystemid, usb, use
+
+
+## Keyword Types
+
+The keywords are divided into a number of different categories. A few
+keywords fall into more than one of these categories.
+
+
+### Alias Types
+
+The alias type keywords are used to give human readable names to
+devices, then later update that name for a specific usage.
+
+* alias, as, use
+
+
+### Containers
+
+These keywords act to group information into logical units of different
+sorts.
+
+* chip, device, domain, field, fw_config, end
+
+
+### Device/Bus Types
+
+These keywords are used to identify the type of device being configured
+and select the appropriate structure for configuration.
+
+* cpu, cpu_cluster, domain, generic, gpio, i2c, ioapic, lapic, mmio,
+  pci, pnp, ref, spi, usb
+
+
+### Enumeration Status Modifiers
+
+The status modifiers determine how a device should be treated during
+enumeration.
+
+* on, off, hidden, mandatory
+
+
+### Firmware configuration
+
+* field, fw_config, option, probe, ref
+
+
+### Resource allocation
+
+* drq, io, irq
+
+
+### SMBIOS
+
+* smbios_dev_info, smbios_slot_desc
+
+
+### Subsystem
+
+* inherit, subsystemid
+
+
+### Register
+
+* register
+
+
+### MPTABLE
+
+* ioapic_irq
+
+
+## Keyword Definitions
+
+### alias
+
+* Keyword type: Alias
+* Introduced in June of 2020, coreboot version 4.12
+* Usage: `device <device type> <device address> **alias** <ALIAS ID> <status modifier> ... end`
+
+Sometimes, the driver of one device needs to know about another device
+that can be anywhere in the device hierarchy. Current applications boil
+down to EEPROMs that store information that is consumed by some code
+(e.g. MAC address).
+
+The idea is to give device nodes in the `devicetree.cb` an alias that
+can later be used to link it to a device driver's `config` structure.
+The driver has to declare a field of type `struct device *`, e.g.
+
+Override devices can add an alias if it does not exist, but cannot
+change the alias for a device that already exists.
+
+Alias names are checked for conflicts both in the base tree and in the
+override tree.
+
+References are resolved after the tree is parsed so aliases and
+references do not need to be in a specific order in the tree.
+
+Example:
+```text
+device i2c 0x50 alias my_eeprom on end
+```
+
+static.c:
+
+```C
+struct some_chip_driver_config {
+        DEVTREE_CONST struct device *needed_eeprom;
+};
+```
+
+### as
+
+* Keyword type: Alias
+* Introduced in June of 2020, coreboot version 4.12
+* Usage: `use <Alias ID> as <Alias ID 2>`
+
+This keyword is used along with the 'use' keyword to give a more
+specific name to a generic alias.
+
+The author of the devicetree is free to choose any alias name that is
+unique in the devicetree. Later, when configuring the driver the alias
+can be used to link the device with the field of a driver's config as in
+the following example.
+
+
+Example:
+
+```text
+chip some/chip/driver
+        use my_eeprom as needed_eeprom
+end
+```
+
+
+### chip
+
+* Keyword type: Component type
+* Introduced in initial sconfig implementation, pre coreboot 4.0
+* Usage: `**chip** <path to chip.h file> ... end`
+
+The chip keyword defines a section for a device inside a hierarchy of
+devices.
+
+Following the chip keyword is a path to an optional chip.h file. If
+this file exists, it should contain a structure of all register settings
+available for this device.
+
+The section started with "chip" is closed with the "end" keyword.
+
+Note that register commands are chip based, not device based.
+
+Example:
+```text
+chip some/chip/driver # comment as desired
+    # A chip section must have at least one device inside it
+    ...
+end # some/chip/driver
+```
+
+
+### cpu
+
+* Keyword type: Device type
+* Introduced in October of 2014, coreboot version 4.0
+* Usage: `device **cpu** <Identifier> [alias <alias ID>] <status modifier> ... end`
+
+The cpu device type was introduced In order to enumerate CPU devices
+that are non-x86 (read: no lapic).
+
+This device type is not used very much, as most non-x86 platforms just
+handle all the CPU configuration at the cpu_cluster level.
+
+Example:
+
+```text
+device cpu 0 on end
+```
+
+
+### cpu_cluster
+
+* Keyword type: Device type
+* Introduced in initial sconfig implementation, pre coreboot 4.0 as apic_cluster
+* Updated in May of 2010 - renamed from apic_cluster to lapic_cluster
+* Updated in February of 2013 - Renamed from from lapic_cluster to cpu_cluster
+* Usage: `device cpu_cluster <Identifier> [alias <alias ID>] <status modifier> …. end`
+
+The CPU Cluster is typically one of the two top-level devices in a
+devicetree, with the other being the PCI Domain. Like the domain
+keyword, the cpu_cluster acts as a bridge device to contain any CPU and
+lapic devices.
+
+On x86 type devices, the CPU Cluster contains CPU chip entries for each
+socket which then contain any lapics on the system.
+
+On ARM or other non-x86 devices, the CPU Cluster can either contain
+multiple CPUs or it can just be marked 'on', leaving all CPU
+configuration to be handled at the CPU Cluster level.
+
+Example:
+
+```text
+device cpu_cluster 0 on
+    device lapic 0 on end
+end
+```
+
+### device
+
+* Keyword type: Component type
+* Introduced in: Initial sconfig implementation, pre coreboot 4.0
+* Usage: `device <device type> <Identifier> [alias <alias ID>]  <status modifier>…. end`
+
+A chip defines a collection of one or more devices, and as such, the
+device is the fundamental building block of devicetree.
+
+The device block tells coreboot that a device is present on the
+mainboard, gives some information on how to find, access, and work with
+the device based on the device type.
+
+Examples:
+
+```text
+device cpu_cluster 0 on
+    device lapic 0 on end
+end
+```
+
+### domain
+
+* Keyword type: Device type
+* Introduced in: Initial sconfig implementation, pre coreboot 4.0
+* Updated in: February of 2013: Renamed pci_domain to domain
+* Usage: `device domain <identifier> [alias <alias ID>]  <status modifier> ... end`
+
+The domain type device acts as a container for one or more chips,
+defining a logical bus segment.
+
+As of 2022-04-29, the domain keyword is still used exclusively to define
+PCI bus segments.
+
+Example:
+
+```text
+device domain 0 on
+    device generic 0 alias dptf_policy on end
+        device pci 1f.0 on                      # 8086 229c - LPC bridge
+            device pnp 2e.209 off end           # GPIO 4
+    end
+end
+```
+
+
+### drq
+
+* Keyword type: Resource type
+* Introduced in: Initial sconfig implementation, pre coreboot 4.0
+* Usage: `drq 0x<register #> = <drq line>`
+
+Drq is used to configure a legacy DMA Request line register for a device
+on a legacy bus - ISA/LPC/eSPI.
+
+The drq configuration is only allowed inside a pnp block.
+
+Example:
+
+```text
+device pnp 2e.1 on              # Parallel port
+    io 0x60 = 0x378
+    irq 0x70 = 7
+    drq 0x74 = 3
+end
+```
+
+### end
+
+* Keyword type: Component type
+* Introduced in: Initial sconfig implementation, pre coreboot 4.0
+* Usage: `<device | chip | domain | field | fw_config> ... end`
+
+End is used to close a chip, device, field, or fw_config block.
+
+Example:
+
+```text
+chip northbridge/intel/x4x
+    device domain 0 on
+        chip southbridge/intel/i82801gx
+            device pci 1f.0 on                 # ISA bridge
+                chip superio/winbond/w83627dhg
+                    device pnp 2e.1 on         # LPT
+                        io 0x60 = 0x378
+                        irq 0x70 = 7
+                        drq 0x74 = 3
+                    end # LPT
+                end # superio/winbond/w83627dhg
+            end # ISA Bridge
+        end # Southbridge
+    end # domain 0
+end # Northbridge
+```
+
+### field
+
+* Keyword type: Firmware config
+* Introduced in: May of 2020, coreboot version 4.12
+* Usage: `field <Identifier string> <low bit> <high bit> [ | <low bit> <high bit> …] ... end`
+
+Fields define the bits used in the Firmware config runtime options.
+Note that the bits in a field can be discontiguous.
+
+All field definitions must be inside a fw_config block.
+
+Example:
+
+```text
+field AUDIO 8 10 | 29 29
+    option NONE 0
+    option MAX98357_ALC5682I_I2S 1
+    option MAX98373_ALC5682I_I2S 2
+    option MAX98373_ALC5682_SNDW 3
+    option MAX98373_ALC5682I_I2S_UP4 4
+    option MAX98360_ALC5682I_I2S 5
+    option RT1011_ALC5682I_I2S 6
+    option AUDIO_FOO 7
+    option AUDIO_BAR 8
+    option AUDIO_QUUX 9
+    option AUDIO_BLAH1 10
+    option AUDIO_BLAH2 15
+end
+```
+
+static_fw_config.h:
+
+```C
+ FW_CONFIG_FIELD_AUDIO_MASK 0x20000700
+ FW_CONFIG_FIELD_AUDIO_OPTION_NONE_VALUE 0x0
+ FW_CONFIG_FIELD_AUDIO_OPTION_MAX98357_ALC5682I_I2S_VALUE 0x100
+ FW_CONFIG_FIELD_AUDIO_OPTION_MAX98373_ALC5682I_I2S_VALUE 0x200
+ FW_CONFIG_FIELD_AUDIO_OPTION_MAX98373_ALC5682_SNDW_VALUE 0x300
+ FW_CONFIG_FIELD_AUDIO_OPTION_MAX98373_ALC5682I_I2S_UP4_VALUE 0x400
+ FW_CONFIG_FIELD_AUDIO_OPTION_MAX98360_ALC5682I_I2S_VALUE 0x500
+ FW_CONFIG_FIELD_AUDIO_OPTION_RT1011_ALC5682I_I2S_VALUE 0x600
+ FW_CONFIG_FIELD_AUDIO_OPTION_AUDIO_FOO_VALUE 0x700
+ FW_CONFIG_FIELD_AUDIO_OPTION_AUDIO_BAR_VALUE 0x20000000
+ FW_CONFIG_FIELD_AUDIO_OPTION_AUDIO_QUUX_VALUE 0x20000100
+ FW_CONFIG_FIELD_AUDIO_OPTION_AUDIO_BLAH1_VALUE 0x20000200
+ FW_CONFIG_FIELD_AUDIO_OPTION_AUDIO_BLAH2_VALUE 0x20000700
+```
+
+### fw_config
+
+* Keyword type: Firmware config
+* Introduced in: May of 2020, coreboot version 4.12
+* Usage: fw_config
+
+Fw_config is the top level token for defining firmware config fields.
+All field and option definitions must be inside the fw_config block.
+Note that the table can be defined before any chips are configured.
+
+Example:
+```text
+fw_config
+    field USB_DB 0 1
+        option USB_DB_A1_PS8811_C1_PS8818 0
+        option USB_DB_A1_ANX7491_C1_ANX7451 1
+    end
+    field FORM_FACTOR 2
+        option FORM_FACTOR_CLAMSHELL 0
+        option FORM_FACTOR_CONVERTIBLE 1
+    end
+end
+```
+
+
+### generic
+
+* Keyword type: Device type
+* Introduced in: May of 2016, coreboot version 4.4
+* Usage: `device generic <identifier> [alias <alias ID>] <status modifier> ... end`
+
+This allows the devicetree to describe a device that does not have a
+specific bus, but may need to be described in tables for the operating
+system. For instance some chips may have various GPIO connections that
+need to be described but do not fall under any other device.
+
+Example:
+```text
+device pci 0c.0 on                        # CNVi
+    chip drivers/wifi/generic
+        register "wake" = "GPE0A_CNVI_PME_STS"
+        device generic 0 on end
+    end
+end
+```
+
+
+### gpio
+
+* Keyword type: Device type
+* Introduced in: December 2020, coreboot version 4.13
+* Usage: `device **gpio** <identifier> [alias <alias ID>] <status modifier> ... end`
+
+The general idea behind this is that every chip can have gpios that
+shall be accessible in a very generic way by any driver through the
+devicetree.
+
+The chip that implements the chip-specific gpio operations has to assign
+them to the generic device operations struct, which then gets assigned
+to the gpio device during device probing. See CB:48583 for how this gets
+done for the SoCs using intel/blocks/gpio.
+
+The gpio device then can be added to the devicetree with an alias name
+like in the following example:
+
+```text
+chip soc/whateverlake
+    device gpio 0 alias soc_gpio on end
+    ...
+end
+```
+
+Any driver that requires access to this gpio device needs to have a
+device pointer (or multiple) and an option for specifying the gpio to be
+used in its chip config like this:
+
+```C
+struct drivers_ipmi_config {
+    ...
+    DEVTREE_CONST struct device *gpio_dev;
+    u16 post_complete_gpio;
+    ...
+};
+```
+
+The device `soc_gpio` can then be linked to the chip driver's `gpio_dev`
+above by using the syntax `use ... as ...`, which was introduced in
+commit 8e1ea52:
+
+```text
+chip drivers/ipmi
+    use soc_gpio as gpio_dev
+    register "bmc_jumper_gpio" = "GPP_D22"
+    ...
+end
+```
+
+The IPMI driver can then use the generic gpio operations without any
+knowlege of the chip's specifics:
+
+```C
+unsigned int gpio_val;
+const struct gpio_operations *gpio_ops;
+gpio_ops = dev_get_gpio_ops(conf->gpio_dev);
+gpio_val = gpio_ops->get(conf->bmc_jumper_gpio);
+```
+
+For a full example have a look at CB:48096 and CB:48095.
+
+
+### hidden
+
+* Keyword type: Enumeration Status Modifier
+* Introduced in: September 2018, coreboot version 4.8
+* Updated in: February of 2020, coreboot version 4.11
+* Usage: `device <device type> <identifier> [alias <alias ID>] hidden ... end`
+
+The "Hidden" keyword was added to support devices sharing the same
+driver to update their ACPI status with different values. If a device
+is marked as Hidden, it omits the "SHOW_IN_UI" field, which prevents the
+device from showing up in the OSPM user interface. This was added to
+prevent ChromeOS specific devices from showing up in Windows, for
+example. It does not look like this keyword was ever actually used in
+this capacity, but the code for this is still present.
+
+In 2020, the "Hidden" keyword's use was expanded to fix the problem of
+PCI devices which have been hidden by disabling access to the config
+space. Because the Device/Vendor IDs read back as 0xffffffff from the
+hidden device, it appears that there is no PCI device located at that
+Bus/Device/Function. This causes coreboot to remove the device at the
+end of PCI enumeration. To fix this, if a device uses 'hidden' instead
+of 'on', then it will be assumed during PCI enumeration that the device
+indeed does exist, and it will not be removed. This allows coreboot to
+manually assign resources to the device even though it doesn't appear to
+exist.
+
+Example:
+```text
+device pci 1f.2 alias pmc hidden end
+```
+
+static.c:
+
+```C
+.enabled = 1,
+.hidden = 1,
+.mandatory = 0,
+```
+
+
+### i2c
+
+* Keyword type: Device type
+* Introduced in: Initial sconfig implementation, pre coreboot 4.0
+* Usage: `device I2c <identifier> [alias <alias ID>] <status modifier> ... end`
+
+Example:
+
+```text
+device i2c 2c on end
+chip drivers/i2c/generic
+    register "hid" = ""ELAN0000""
+    register "desc" = ""ELAN Touchpad""
+    register "irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPIO_9)"
+    register "wake" = "GEVENT_22"
+    register "probed" = "1"
+    device i2c 15 on end
+end
+```
+
+### inherit
+
+* Keyword type: subsystem
+* Introduced in: March of 2011, coreboot version 4.0
+* Usage: `subsystemid beee c001 inherit`
+
+Used to modify the subsystemid keyword, inherit makes the ID apply to
+all subdevices and functions.
+
+Example:
+```text
+device pci 00.0 on
+    subsystemid 0xdead 0xbeef inherit
+end
+```
+
+
+### io
+
+* Keyword type: Resource
+* Introduced in: Initial sconfig implementation, pre coreboot 4.0
+* Usage: `io 0x<address> = 0x<value>`
+
+The io command is used to set an legacy device's io register to a value.
+
+Example:
+
+```text
+device pnp 4e.06 on                # Keyboard
+    io 0x60            = 0x0060
+    io 0x62            = 0x0064
+    irq 0x70        = 1
+end
+```
+
+### ioapic
+
+* Keyword type: Device type
+
+* Usage: `device ioapic <identifier> [alias <alias ID>] <status modifier> ... end`
+
+
+### ioapic_irq
+
+* Keyword type: Mpinit type
+* Introduced in: June of 2012, coreboot version 4.0
+* Usage: `ioapic_irq <APICID> <INTA|INTB|INTC|INTD> <INTPIN>`
+
+This keyword is used to support autogeneration of the MPTABLE from
+devicetree.cb. This is done by a write_smp_table() declared weak in
+mpspec.c. If the mainboard doesn't provide its own function, this
+generic implementation is called.
+
+The ioapic_irq directive can be used in pci and pci_domain devices. If
+there's no directive, the autogen code traverses the tree back to the
+pci_domain and stops at the first device which sets such a directive,
+and uses that information to generate the entry according to PCI IRQ
+routing rules.
+
+```text
+```
+
+
+### irq
+
+* Keyword type: Resource type
+* Introduced in initial sconfig implementation, pre coreboot 4.0
+* Usage: `irq 0x<address> = 0x<value>`
+
+Irq is used to configure a legacy interrupt Request line register for a
+device on a legacy bus - ISA/LPC/eSPI.
+
+The irq configuration is only allowed inside a pnp block.
+
+Example:
+
+```text
+irq 0xc5 = 0x1f
+```
+
+```text
+chip superio/fintek/f71808a
+    device pnp 4e.4 on    # Hardware monitor
+        io 0x60 = 0x295
+        irq 0x70 = 0
+    end
+end
+```
+
+### lapic
+
+* Keyword type: Device type
+* Introduced in initial sconfig implementation, pre coreboot 4.0
+* Updated in May of 2010 - Renamed apic to lapic
+* Usage: `device lapic <identifier> [alias <alias ID>] <status modifier> ... end`
+
+Defines an lapic device on an x86 mainboard.
+
+Example:
+
+```text
+device cpu_cluster 0 on          # (L)APIC cluster
+    chip cpu/intel/slot_1        # CPU socket 0
+        device lapic 0 on end    # Local APIC of CPU 0
+    end
+    chip cpu/intel/slot_1        # CPU socket 1
+        device lapic 1 on end    # Local APIC of CPU 1
+    end
+end
+```
+
+### mandatory
+
+* Keyword type: Enumeration Status Modifier
+* Introduced in: February of 2020, coreboot version 4.11
+* Usage: `device <device type> <identifier> [alias <alias ID>] mandatory ... end`
+
+The Mandatory keyword allows for minimal PCI scanning which speeds up the
+boot process. Only devices marked "mandatory" get enabled and scanned
+during PCI enumeration when the MINIMAL_PCI_SCANNING Kconfig option is
+enabled.
+
+If MINIMAL_PCI_SCANNING is not enabled, this means the same as 'on'.
+
+static.c:
+
+```C
+.enabled = 1,
+.hidden = 0,
+.mandatory = 1,
+```
+
+example:
+
+```text
+device pci 1f.0 mandatory  # LPC
+    chip drivers/pc80/tpm
+        device pnp 0c31.0 on end
+    end # tpm
+end # LPC
+```
+
+
+### mmio
+
+* Keyword type: Device type
+* Introduced in January of 2018, coreboot version 4.7
+* Usage: `device mmio 0x<address> [alias <alias ID>] <status modifier> ... end`
+
+The mmio keyword allows fixed memory-mapped IO addressed devices to be
+assigned to given values.
+
+AMD platforms perform a significant amount of configuration through these
+MMIO addresses, including I2C bus configuration.
+
+example:
+
+```text
+device mmio 0xfedc9000 alias uart_0 off end
+device mmio 0xfedca000 alias uart_1 off end
+device mmio 0xfedc2000 on                      # I2C 0
+
+    chip drivers/generic/adau7002
+        device generic 0.0 on end
+    end
+
+    chip drivers/i2c/da7219
+        register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_LOW(GPIO_14)"
+    end
+
+    chip drivers/generic/max98357a
+        register "hid" = ""MX98357A""
+        register "sdmode_delay" = "5"
+        device generic 0.1 on end
+    end
+
+end # I2C 0
+```
+
+
+### off
+
+* Keyword type: Enumeration Status Modifier
+* Introduced in: Initial sconfig implementation, pre coreboot 4.0
+* Usage: `device <device type> <identifier> [alias <alias ID>] off ... end`
+
+Indicates that the device should be disabled if possible and should not
+be enumerated or configured. To disable a device, the code to disable it
+must be present in the chipset/SoC code, though it isn't always possible
+to actually disable the device.
+
+Note that If a device (especially PCI devices) is marked as 'off', but
+does not get disabled, the OS or a driver may discover the device during
+its enumeration sequence and assign it resources anyway.
+
+static.c:
+
+```C
+.enabled = 0
+.hidden = 0,
+.mandatory = 0,
+```
+
+example:
+
+```text
+device usb 2.6 off end
+device pnp 2e.0 off end # FDC
+device pci 15.2 off end
+```
+
+### on
+
+* Keyword type: Enumeration Status Modifier
+* Introduced in: Initial sconfig implementation, pre coreboot 4.0
+* Usage: `device <device type> <identifier> [alias <alias ID>] on ... end`
+
+Marks a device as present and enabled. This indicates that the device
+should be enumerated and configured.
+
+static.c:
+
+```C
+.enabled = 1
+.hidden = 0,
+.mandatory = 0,
+```
+
+Example:
+
+```text
+device lapic 0 on end
+device pci 00.0 on  end # Host Bridge
+device pnp 0c31.0 on end
+```
+
+### option
+
+* Keyword type: Firmware config
+* Usage: `option <name> <value>`
+
+Options define the values which may be used in a firmware config field.
+The option keyword may only be used inside a field, which may only be
+used inside an fw_config block.
+
+Example:
+
+```text
+fw_config
+    field OLED_SCREEN 28
+        option OLED_NOT_PRESENT 0
+        option OLED_PRESENT 1
+    end
+end
+```
+
+### pci
+
+* Keyword type: Device type
+* Introduced in: Initial sconfig implementation, pre coreboot 4.0
+* Usage: `device pci <dev.func> [alias <alias ID>]  <status modifier> …. end`
+
+The pci device type defines a PCI or PCIe device on the PCI logical bus.
+
+Resources for all PCI devices are assigned automatically, or must be
+assigned in code if they're non-standard.
+
+Currently, only a single segment is supported, but there is work to make
+multiple different segments supported, each with a bus 0. Because the
+bus is not specified, It's assumed that all pci devices that are not
+behind a pci bridge device are on bus 0. If there are additional pci
+busses in a chip, they can be added behind their bridge device.
+
+Examples:
+
+```text
+device pci 1a.0 on end # USB2 EHCI #2
+device pci 1b.0 on # High Definition Audio
+    subsystemid 0x1a86 0x4352
+end
+```
+
+Example - ISA bus under PCI to ISA bridge:
+
+```text
+device pci 4.0 on                        # ISA bridge
+    chip superio/winbond/w83977tf        # Super I/O
+        device pnp 3f0.2 on              # COM1
+            io 0x60 = 0x3f8
+            irq 0x70 = 4
+        end
+    end
+end
+```
+
+Example - PCI Bus under a PCI to PCI bridge:
+
+```text
+device pci 08.0 on end                    # Dummy Host Bridge, do not disable
+device pci 08.1 alias gpp_bridge_a off    # Internal GPP Bridge 0 to Bus A
+    device pci 0.0 alias gfx off end            # Internal GPU (GFX)
+    device pci 0.1 alias gfx_hda off end        # Display HDA (GFXAZ)
+end
+```
+
+
+### pnp
+
+* Keyword type: Device type
+* Introduced in: Initial sconfig implementation, pre coreboot 4.0
+* Usage: `device pnp <Identifier> [alias <alias ID>]  <status modifier>…. end`
+
+pnp is used to define an IO addressed device within a chip on a legacy
+bus - ISA, LPC, or eSPI. The identifier is the IO address used to
+access the chip, followed by the identifier for the device within the
+chip.
+
+The io, irq, and drq resource identifiers are allowed only inside a pnp
+device.
+
+Example:
+
+```text
+chip superio/ite/it8783ef
+    device pnp 2e.0 off end    # Floppy
+    device pnp 2e.1 on    # COM 1
+        io 0x60 = 0x3f8
+        irq 0x70 = 4
+    end
+end
+```
+
+### probe
+
+* Keyword type: Firmware config
+* Introduced in May of 2020, coreboot version 4.12
+* Usage: `probe <Field Name> <Option Name>`
+
+The fields and options can be used to probe for a device and have that
+device be disabled if it is not found at boot time.
+
+Example:
+
+```text
+fw_config
+    field FEATURE 0 0
+        option DISABLE 0
+        option ENABLE 1
+    end
+end
+
+chip drivers/generic/feature
+    device generic 0 on
+        probe FEATURE ENABLE
+    end
+end
+```
+
+
+### ref
+
+* Keyword type: Device type (alias)
+* Introduced in July of 2020, coreboot version 4.12
+* Usage: `device REF <Identifier> <status modifier>…. end`
+
+This allows the chipset to assign alias names to devices as well as set
+default register values. This works for both the baseboard devicetree.cb
+as well as variant overridetree.cb.
+
+Example:
+
+chipset.cb:
+
+```text
+device pci 15.0 alias i2c0 off end
+```
+
+devicetree.cb:
+
+```text
+device ref i2c0 on end
+```
+
+### register
+
+* Keyword type: Register
+* Introduced in: Initial sconfig implementation, pre coreboot 4.0
+* Usage: `register "name" = "value"`
+
+The register keyword was initially intended to supply just that -
+information for device register values. Over the years, its use has been
+expanded to much more than this, becoming a general configuration
+mechanism.
+
+All values set by the register keyword MUST be defined in the chip.h
+file. The register keyword only works at the chip level, not at the
+device level.
+
+Any register defined in the chip.h file that is not set in the
+devicetree file gets set to zero.
+
+To double quote a value, use two sets of quotes: `register "name" = ""string""`
+
+Examples:
+
+```text
+register "desc" = ""USB2 Type-A Rear Lower""
+register "pcie_power_limits" = "{ { 10, 0 }, { 0, 0 }, { 0, 0 },
+                                  { 0, 0 }, { 10, 0 }, { 0, 0 } }"
+register "SataPortsEnable[0]" = "1"
+register "generic.irq"              = "ACPI_IRQ_LEVEL_LOW(GPP_B3_IRQ)"
+register "common_soc_config" = "{
+                                    // Touchpad I2C bus
+                                    .i2c[0] = {
+                                        .speed = I2C_SPEED_FAST,
+                                        .rise_time_ns = 80,
+                                        .fall_time_ns = 110,
+                                    },
+                                }"
+```
+
+
+### smbios_dev_info
+
+* Keyword type: smbios
+* Introduced in: May of 2019, coreboot version 4.9
+* Usage: `smbios_dev_info <Identifier>`
+
+Specify the instance ID and RefDes (Reference Designation) of onboard
+devices.
+
+The `SMBIOS_TYPE41_PROVIDED_BY_DEVTREE` Kconfig option enables using
+this syntax to control the generated Type 41 entries (Onboard Devices
+Extended Information). When this option is enabled, Type 41 entries are
+only autogenerated for devices with a defined instance ID. This avoids
+having to keep track of which instance IDs have been used for every
+device class.
+
+Using `smbios_dev_info` when `SMBIOS_TYPE41_PROVIDED_BY_DEVTREE` is not
+enabled will result in a build-time error, as the syntax is meaningless
+in this case. This is done with preprocessor guards around the Type 41
+members in `struct device` and the code which uses the guarded members.
+Although the preprocessor usage isn't particularly elegant, adjusting the
+devicetree syntax and/or grammar depending on a Kconfig option is
+probably even worse.
+
+Example:
+
+```text
+device pci 1c.0 on        # PCIe Port #1
+    device pci 00.0 on
+        smbios_dev_info 6
+    end
+end
+device pci 1c.1 on        # PCIe Port #2
+    device pci 00.0 on
+        smbios_dev_info 42 "PCIe-PCI Time Machine"
+    end
+end
+```
+
+### smbios_slot_desc
+
+* Keyword type: smbios
+* Introduced in: May of 2019, coreboot version 4.9
+* Usage: `smbios_slot_desc** <type> <length> [designation] [data width]`
+
+Add the new field 'smbios_slot_desc', which takes 2 to 4 arguments.
+The field is only valid for PCI devices and only compiled if SMBIOS
+table generation is enabled.
+
+smbios_slot_desc arguments - described in src/include/smbios.h:
+
+1.  slot type: enum misc_slot_type
+2.  slot length: enum misc_slot_length
+3.  slot designation (optional): text string
+4.  slot data width (optional): enum slot_data_bus_bandwidth
+
+Example:
+
+```text
+device pci 1c.1 on
+    smbios_slot_desc "SlotTypePciExpressGen3X16" "SlotLengthOther" "SLOT2" "SlotDataBusWidth8X"
+end # PCIe Port #2 Integrated Wireless LAN
+```
+
+### spi
+
+* Keyword type: Device type
+* Introduced in: February of 2017, coreboot version 4.5
+* Usage: device **SPI** <Identifier> [alias <alias ID>]  <status modifier>…. end
+
+The SPI device takes only one parameter, the chip-select for the device
+on the SPI bus.
+
+Example:
+
+```text
+device spi 0 alias spi_tpm on end
+```
+
+
+### subsystemid
+
+* Keyword type: Subsystem
+* Introduced in: March of 2011, coreboot version 4.0
+* Usage: `subsystemid <vendor> <device> [inherit]`
+
+Sets a PCI subsystem ID.
+
+If the user wants to have this ID inherited to all subdevices/functions,
+they can add the keyword 'inherit' after the ID.
+
+If the user doesn't want to inherit the subsystem value for a single
+device, they can specify 'subsystemid 0 0' on this particular device.
+
+Example:
+
+```text
+device pci 00.0 on
+    subsystemid 0xdead 0xbeef
+end
+```
+
+or
+
+```text
+device pci 00.0 on
+    subsystemid 0xdead 0xbeef inherit
+end
+```
+
+### usb
+
+* Keyword type: Device type
+* Introduced in: May of 2018, coreboot version 4.7
+* Usage: `device usb <Identifier> [alias <alias ID>]  <status modifier> ... end`
+
+This supports describing USB ports in the devicetree. It allows a USB
+port location to be described in the tree with configuration
+information, and ACPI code to be generated that provides this
+information to the OS.
+
+The usb symbol works with the scan_usb_bus() operation to scan bridges
+for devices so a tree of ports and hubs can be created.
+
+The device address is computed with a 'port type' and a 'port id' which
+is flexible for the SOC to handle depending on their specific USB setup
+This also allows USB2 and USB3 ports to be described separately.
+
+For example a board may have devices on two ports, one with a USB2
+device and one with a USB3 device, both of which are connected to an
+xHCI controller with a root hub:
+
+```text
+             xHCI
+               |
+            RootHub
+            |     |
+        USB2[0]  USB3[2]
+```
+
+This is described by the following example:
+
+```text
+device pci 14.0 on
+    chip drivers/usb/acpi
+        register "name" = ""Root Hub""
+        device usb 0.0 on
+
+            chip drivers/usb/acpi
+                register "name" = ""USB 2.0 Port 0""
+                device usb 2.0 on end
+            end
+
+            chip drivers/usb/acpi
+                register "name" = ""USB 3.0 Port 2""
+                device usb 3.2 on end
+            end
+
+        end # device usb 0.0
+    end # chip drivers/usb/acpi
+end # device pci 14.0
+```
+
+### use
+
+* Keyword type: Alias
+* Introduced in September of 2020, coreboot version 4.12
+* Usage: `use <Alias ID> as <Alias ID2>`
+
+The author of the devicetree is free to choose any alias name that is
+unique in the devicetree. Later, when configuring the driver for a
+board, the alias can be used to link the device with the field of a
+driver's config, giving it a specific name.
+
+Example:
+
+```text
+chip some/chip/driver
+    use my_eeprom as needed_eeprom
+end
+```
diff --git a/Documentation/internals/index.md b/Documentation/internals/index.md
index 01d56967fb..17dee55ada 100644
--- a/Documentation/internals/index.md
+++ b/Documentation/internals/index.md
@@ -9,5 +9,6 @@ programming APIs internal to coreboot
 :maxdepth: 1
 
 coreboot devicetree <devicetree.md>
+coreboot devicetree language <devicetree_language.md>
 
 ```

From 0ae3b534e1a775cce179d56f213686adfba9ca58 Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Fri, 4 Apr 2025 10:42:04 +0100
Subject: [PATCH 0654/3886] mb/starlabs/starbook/mtl: Change SSD enable GPIO to
 DEEP

Set the SSD enable GPIO to DEEP reset, so that the SSD is powered
down in S3.

Change-Id: I6cc247e04974d293dfc157a3b459a3fb61e43a7f
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87153
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
---
 src/mainboard/starlabs/starbook/variants/mtl/gpio.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/mainboard/starlabs/starbook/variants/mtl/gpio.c b/src/mainboard/starlabs/starbook/variants/mtl/gpio.c
index bb976a8431..618df01b19 100644
--- a/src/mainboard/starlabs/starbook/variants/mtl/gpio.c
+++ b/src/mainboard/starlabs/starbook/variants/mtl/gpio.c
@@ -46,7 +46,7 @@ const struct pad_config gpio_table[] = {
 	/* SSD */
 	PAD_CFG_NF(GPP_D20, NONE, DEEP, NF1),				/* Clock Request 8 */
 	PAD_CFG_GPO(GPP_A20, 1, PLTRST),				/* Reset */
-	PAD_CFG_GPO(GPP_H07, 1, PLTRST),				/* Enable */
+	PAD_CFG_GPO(GPP_H07, 1, DEEP),					/* Enable */
 
 	/* Wireless */
 	PAD_CFG_NF(GPP_D21, NONE, DEEP, NF2),				/* Clock Request 5 */

From e5ade7cfb1eca79704b9ef7ab6dc9a2bce7eef62 Mon Sep 17 00:00:00 2001
From: Naresh Solanki <naresh.solanki@9elements.com>
Date: Wed, 2 Apr 2025 23:49:13 +0530
Subject: [PATCH 0655/3886] soc/amd/*/include/soc/msr.h: Move MSR to common
 location

MSR definition in soc/amd/*/include/soc/msr.h are the same & hence move
them to common header src/include/cpu/amd/msr.h

Change-Id: Ic0cb54b13320f8a38e70c0a76d9b9a51ba0ea01d
Signed-off-by: Naresh Solanki <naresh.solanki@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87124
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
---
 src/include/cpu/amd/msr.h               | 19 +++++++++++++++++++
 src/soc/amd/cezanne/include/soc/msr.h   | 20 ++------------------
 src/soc/amd/genoa_poc/include/soc/msr.h | 22 ++--------------------
 src/soc/amd/glinda/include/soc/msr.h    | 20 ++------------------
 src/soc/amd/mendocino/include/soc/msr.h | 20 ++------------------
 src/soc/amd/phoenix/include/soc/msr.h   | 20 ++------------------
 6 files changed, 29 insertions(+), 92 deletions(-)

diff --git a/src/include/cpu/amd/msr.h b/src/include/cpu/amd/msr.h
index 3f7febc462..69425c5cca 100644
--- a/src/include/cpu/amd/msr.h
+++ b/src/include/cpu/amd/msr.h
@@ -78,4 +78,23 @@
 
 #define CORE_PERF_BOOST_CTRL		0x15c
 
+/* Value defined in Serial VID Interface 3.0 spec (#56413, NDA only) */
+#define MSR_CPPC_CAPABILITY_1				0xc00102b0
+#define SHIFT_CPPC_CAPABILITY_1_HIGHEST_PERF		24
+#define SHIFT_CPPC_CAPABILITY_1_NOMINAL_PERF		16
+#define SHIFT_CPPC_CAPABILITY_1_LOW_NON_LIN_PERF	8
+#define SHIFT_CPPC_CAPABILITY_1_LOWEST_PERF		0
+
+#define MSR_CPPC_ENABLE				0xc00102b1
+#define MSR_CPPC_REQUEST			0xc00102b3
+#define SHIFT_CPPC_REQUEST_ENERGY_PERF_PREF	24
+#define SHIFT_CPPC_REQUEST_DES_PERF		16
+#define SHIFT_CPPC_REQUEST_MIN_PERF		8
+#define SHIFT_CPPC_REQUEST_MAX_PERF		0
+
+#define MSR_CPPC_STATUS		0xc00102b4
+
+#define MSR_MAX_PERFORMANCE_FREQUENCY_CLOCK_COUNT	0xe7
+#define MSR_ACTUAL_PERFORMANCE_FREQUENCY_CLOCK_COUNT	0xe8
+
 #endif /* CPU_AMD_MSR_H */
diff --git a/src/soc/amd/cezanne/include/soc/msr.h b/src/soc/amd/cezanne/include/soc/msr.h
index 0fba3e6d83..1b7c98c1d2 100644
--- a/src/soc/amd/cezanne/include/soc/msr.h
+++ b/src/soc/amd/cezanne/include/soc/msr.h
@@ -3,6 +3,8 @@
 #ifndef AMD_CEZANNE_MSR_H
 #define AMD_CEZANNE_MSR_H
 
+#include <cpu/amd/msr.h>
+
 /* MSRC001_00[6B:64] P-state [7:0] bit definitions */
 union pstate_msr {
 	struct {
@@ -17,22 +19,4 @@ union pstate_msr {
 	uint64_t raw;
 };
 
-#define MSR_CPPC_CAPABILITY_1				0xc00102b0
-#define SHIFT_CPPC_CAPABILITY_1_HIGHEST_PERF		24
-#define SHIFT_CPPC_CAPABILITY_1_NOMINAL_PERF		16
-#define SHIFT_CPPC_CAPABILITY_1_LOW_NON_LIN_PERF	8
-#define SHIFT_CPPC_CAPABILITY_1_LOWEST_PERF		0
-
-#define MSR_CPPC_ENABLE				0xc00102b1
-#define MSR_CPPC_REQUEST			0xc00102b3
-#define SHIFT_CPPC_REQUEST_ENERGY_PERF_PREF	24
-#define SHIFT_CPPC_REQUEST_DES_PERF		16
-#define SHIFT_CPPC_REQUEST_MIN_PERF		8
-#define SHIFT_CPPC_REQUEST_MAX_PERF		0
-
-#define MSR_CPPC_STATUS		0xc00102b4
-
-#define MSR_MAX_PERFORMANCE_FREQUENCY_CLOCK_COUNT	0xe7
-#define MSR_ACTUAL_PERFORMANCE_FREQUENCY_CLOCK_COUNT	0xe8
-
 #endif /* AMD_CEZANNE_MSR_H */
diff --git a/src/soc/amd/genoa_poc/include/soc/msr.h b/src/soc/amd/genoa_poc/include/soc/msr.h
index 31328ea994..6b0d0a8d34 100644
--- a/src/soc/amd/genoa_poc/include/soc/msr.h
+++ b/src/soc/amd/genoa_poc/include/soc/msr.h
@@ -3,6 +3,8 @@
 #ifndef AMD_GENOA_POC_MSR_H
 #define AMD_GENOA_POC_MSR_H
 
+#include <cpu/amd/msr.h>
+
 /* MSRC001_00[6B:64] P-state [7:0] bit definitions */
 union pstate_msr {
 	struct {
@@ -18,24 +20,4 @@ union pstate_msr {
 	uint64_t raw;
 };
 
-
-/* Value defined in Serial VID Interface 3.0 spec (#56413, NDA only) */
-#define MSR_CPPC_CAPABILITY_1				0xc00102b0
-#define SHIFT_CPPC_CAPABILITY_1_HIGHEST_PERF		24
-#define SHIFT_CPPC_CAPABILITY_1_NOMINAL_PERF		16
-#define SHIFT_CPPC_CAPABILITY_1_LOW_NON_LIN_PERF	8
-#define SHIFT_CPPC_CAPABILITY_1_LOWEST_PERF		0
-
-#define MSR_CPPC_ENABLE				0xc00102b1
-#define MSR_CPPC_REQUEST			0xc00102b3
-#define SHIFT_CPPC_REQUEST_ENERGY_PERF_PREF	24
-#define SHIFT_CPPC_REQUEST_DES_PERF		16
-#define SHIFT_CPPC_REQUEST_MIN_PERF		8
-#define SHIFT_CPPC_REQUEST_MAX_PERF		0
-
-#define MSR_CPPC_STATUS		0xc00102b4
-
-#define MSR_MAX_PERFORMANCE_FREQUENCY_CLOCK_COUNT	0xe7
-#define MSR_ACTUAL_PERFORMANCE_FREQUENCY_CLOCK_COUNT	0xe8
-
 #endif /* AMD_GENOA_POC_MSR_H */
diff --git a/src/soc/amd/glinda/include/soc/msr.h b/src/soc/amd/glinda/include/soc/msr.h
index 2f40d395f3..1c2a3c0be5 100644
--- a/src/soc/amd/glinda/include/soc/msr.h
+++ b/src/soc/amd/glinda/include/soc/msr.h
@@ -5,6 +5,8 @@
 #ifndef AMD_GLINDA_MSR_H
 #define AMD_GLINDA_MSR_H
 
+#include <cpu/amd/msr.h>
+
 /* MSRC001_00[6B:64] P-state [7:0] bit definitions */
 union pstate_msr {
 	struct {
@@ -20,22 +22,4 @@ union pstate_msr {
 	uint64_t raw;
 };
 
-#define MSR_CPPC_CAPABILITY_1				0xc00102b0
-#define SHIFT_CPPC_CAPABILITY_1_HIGHEST_PERF		24
-#define SHIFT_CPPC_CAPABILITY_1_NOMINAL_PERF		16
-#define SHIFT_CPPC_CAPABILITY_1_LOW_NON_LIN_PERF	8
-#define SHIFT_CPPC_CAPABILITY_1_LOWEST_PERF		0
-
-#define MSR_CPPC_ENABLE				0xc00102b1
-#define MSR_CPPC_REQUEST			0xc00102b3
-#define SHIFT_CPPC_REQUEST_ENERGY_PERF_PREF	24
-#define SHIFT_CPPC_REQUEST_DES_PERF		16
-#define SHIFT_CPPC_REQUEST_MIN_PERF		8
-#define SHIFT_CPPC_REQUEST_MAX_PERF		0
-
-#define MSR_CPPC_STATUS		0xc00102b4
-
-#define MSR_MAX_PERFORMANCE_FREQUENCY_CLOCK_COUNT	0xe7
-#define MSR_ACTUAL_PERFORMANCE_FREQUENCY_CLOCK_COUNT	0xe8
-
 #endif /* AMD_GLINDA_MSR_H */
diff --git a/src/soc/amd/mendocino/include/soc/msr.h b/src/soc/amd/mendocino/include/soc/msr.h
index cfc7702c9f..ceb9bd9a6a 100644
--- a/src/soc/amd/mendocino/include/soc/msr.h
+++ b/src/soc/amd/mendocino/include/soc/msr.h
@@ -3,6 +3,8 @@
 #ifndef AMD_MENDOCINO_MSR_H
 #define AMD_MENDOCINO_MSR_H
 
+#include <cpu/amd/msr.h>
+
 /* MSRC001_00[6B:64] P-state [7:0] bit definitions */
 union pstate_msr {
 	struct {
@@ -18,22 +20,4 @@ union pstate_msr {
 	uint64_t raw;
 };
 
-#define MSR_CPPC_CAPABILITY_1				0xc00102b0
-#define SHIFT_CPPC_CAPABILITY_1_HIGHEST_PERF		24
-#define SHIFT_CPPC_CAPABILITY_1_NOMINAL_PERF		16
-#define SHIFT_CPPC_CAPABILITY_1_LOW_NON_LIN_PERF	8
-#define SHIFT_CPPC_CAPABILITY_1_LOWEST_PERF		0
-
-#define MSR_CPPC_ENABLE				0xc00102b1
-#define MSR_CPPC_REQUEST			0xc00102b3
-#define SHIFT_CPPC_REQUEST_ENERGY_PERF_PREF	24
-#define SHIFT_CPPC_REQUEST_DES_PERF		16
-#define SHIFT_CPPC_REQUEST_MIN_PERF		8
-#define SHIFT_CPPC_REQUEST_MAX_PERF		0
-
-#define MSR_CPPC_STATUS		0xc00102b4
-
-#define MSR_MAX_PERFORMANCE_FREQUENCY_CLOCK_COUNT	0xe7
-#define MSR_ACTUAL_PERFORMANCE_FREQUENCY_CLOCK_COUNT	0xe8
-
 #endif /* AMD_MENDOCINO_MSR_H */
diff --git a/src/soc/amd/phoenix/include/soc/msr.h b/src/soc/amd/phoenix/include/soc/msr.h
index 7acf3219b8..c81cdd289b 100644
--- a/src/soc/amd/phoenix/include/soc/msr.h
+++ b/src/soc/amd/phoenix/include/soc/msr.h
@@ -5,6 +5,8 @@
 #ifndef AMD_PHOENIX_MSR_H
 #define AMD_PHOENIX_MSR_H
 
+#include <cpu/amd/msr.h>
+
 /* MSRC001_00[6B:64] P-state [7:0] bit definitions */
 union pstate_msr {
 	struct {
@@ -20,22 +22,4 @@ union pstate_msr {
 	uint64_t raw;
 };
 
-#define MSR_CPPC_CAPABILITY_1				0xc00102b0
-#define SHIFT_CPPC_CAPABILITY_1_HIGHEST_PERF		24
-#define SHIFT_CPPC_CAPABILITY_1_NOMINAL_PERF		16
-#define SHIFT_CPPC_CAPABILITY_1_LOW_NON_LIN_PERF	8
-#define SHIFT_CPPC_CAPABILITY_1_LOWEST_PERF		0
-
-#define MSR_CPPC_ENABLE				0xc00102b1
-#define MSR_CPPC_REQUEST			0xc00102b3
-#define SHIFT_CPPC_REQUEST_ENERGY_PERF_PREF	24
-#define SHIFT_CPPC_REQUEST_DES_PERF		16
-#define SHIFT_CPPC_REQUEST_MIN_PERF		8
-#define SHIFT_CPPC_REQUEST_MAX_PERF		0
-
-#define MSR_CPPC_STATUS		0xc00102b4
-
-#define MSR_MAX_PERFORMANCE_FREQUENCY_CLOCK_COUNT	0xe7
-#define MSR_ACTUAL_PERFORMANCE_FREQUENCY_CLOCK_COUNT	0xe8
-
 #endif /* AMD_PHOENIX_MSR_H */

From 29a837bd5aeab3da69b3b6cc7c6619b99831b751 Mon Sep 17 00:00:00 2001
From: Julian Intronati <julian.intronati@gmail.com>
Date: Thu, 27 Mar 2025 14:13:50 +0000
Subject: [PATCH 0656/3886] mb/cwwk: Add CWWK CW-ADLNTB-1C2L-V3.0 board as an
 adl variants

This board is the CWWK variant based upon Alder Lake with 2 2.5 GbE
ports. The variants files structure is inspired by
system76/adl/variants structure, adapted for cw-adl-4l-v1.0 board
and the new cw-adlnth-1c2l-v3.0 (named according to original bios
naming).

CPU: Intel N100 or N305
Memory: 1x DDR5-4800 SODIMM (max 16 GB)
NIC: 2x Intel I226-V 2.5 GbE
Expansion:
- M.2 2230 E key
- M.2 2280 M key
- USB 2.0 header
- Fan header
External ports:
- DC power
- 2x Ethernet
- 2x HDMI
- 2x USB 2.0

Working:
- Boots Debian 12 with SeaBIOS and EDK II payloads
- Serial port
- External USB ports
- 1x HDMI
- 2x Intel I226 2.5 GbE NICs
- M.2 ports
- ACPI S3
- Fan (ITE IT8613E) driver IT87 (frankcrawford github fork)

Not tested:
- The second HDMI
- Audio
- S0ix (cw-adl-4l-v1.0 said it's not working)
- Internal USB ports

VBT extracted from vendor UEFI firmware
version F2 (2024-06-26 10:26:38)
was 100% matching the cw-adl-4l-v1.0,
so we kept only one in the tree.

Change-Id: Ia0553141b41717b560042de1136d53b9c3cf7a69
Signed-off-by: Julian Intronati <julian.intronati@eho.link>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87027
Reviewed-by: Julian Intronati <julian.intronati@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
---
 src/mainboard/cwwk/adl/Kconfig                |  31 +-
 src/mainboard/cwwk/adl/Kconfig.name           |   5 +-
 src/mainboard/cwwk/adl/Makefile.mk            |   7 +-
 src/mainboard/cwwk/adl/board_info.txt         |   2 +-
 .../cwwk/adl/include/mainboard/gpio.h         |   8 +
 .../cwwk/adl/{mainboard.c => ramstage.c}      |   4 +-
 .../variants/cw-adl-4l-v1.0/board_info.txt    |   2 +
 .../cw-adl-4l-v1.0/gpio.c}                    |   9 +-
 .../cw-adl-4l-v1.0/romstage.c}                |   0
 .../cw-adlntb-1c2l-v3.0/board_info.txt        |   2 +
 .../adl/variants/cw-adlntb-1c2l-v3.0/gpio.c   | 298 ++++++++++++++++++
 .../variants/cw-adlntb-1c2l-v3.0/romstage.c   |  28 ++
 12 files changed, 382 insertions(+), 14 deletions(-)
 create mode 100644 src/mainboard/cwwk/adl/include/mainboard/gpio.h
 rename src/mainboard/cwwk/adl/{mainboard.c => ramstage.c} (71%)
 create mode 100644 src/mainboard/cwwk/adl/variants/cw-adl-4l-v1.0/board_info.txt
 rename src/mainboard/cwwk/adl/{gpio.h => variants/cw-adl-4l-v1.0/gpio.c} (98%)
 rename src/mainboard/cwwk/adl/{romstage_fsp_params.c => variants/cw-adl-4l-v1.0/romstage.c} (100%)
 create mode 100644 src/mainboard/cwwk/adl/variants/cw-adlntb-1c2l-v3.0/board_info.txt
 create mode 100644 src/mainboard/cwwk/adl/variants/cw-adlntb-1c2l-v3.0/gpio.c
 create mode 100644 src/mainboard/cwwk/adl/variants/cw-adlntb-1c2l-v3.0/romstage.c

diff --git a/src/mainboard/cwwk/adl/Kconfig b/src/mainboard/cwwk/adl/Kconfig
index c8dbd04dd7..11b8e3c9c4 100644
--- a/src/mainboard/cwwk/adl/Kconfig
+++ b/src/mainboard/cwwk/adl/Kconfig
@@ -1,8 +1,6 @@
 ## SPDX-License-Identifier: GPL-2.0-or-later
 
-if BOARD_CWWK_ADL_N
-
-config BOARD_SPECIFIC_OPTIONS
+config BOARD_CWWK_ADL_N_COMMON
 	def_bool y
 	select BOARD_ROMSIZE_KB_16384
 	select CRB_TPM
@@ -15,11 +13,36 @@ config BOARD_SPECIFIC_OPTIONS
 	select SOC_INTEL_ALDERLAKE_PCH_N
 	select SUPERIO_ITE_IT8613E
 
+config BOARD_CWWK_CW_ADL_4L_V1
+	select BOARD_CWWK_ADL_N_COMMON
+
+config BOARD_CWWK_CW_ADLNTB_1C2L_V3
+	select BOARD_CWWK_ADL_N_COMMON
+
+if BOARD_CWWK_ADL_N_COMMON
+
 config MAINBOARD_DIR
 	default "cwwk/adl"
 
+config VARIANT_DIR
+	default "cw-adl-4l-v1.0"      if BOARD_CWWK_CW_ADL_4L_V1
+	default "cw-adlntb-1c2l-v3.0" if BOARD_CWWK_CW_ADLNTB_1C2L_V3
+
 config MAINBOARD_PART_NUMBER
-	default "CW-AL-4L-V1.0"
+	default "CW-ADL-4L-V1.0"      if BOARD_CWWK_CW_ADL_4L_V1
+	default "CW-ADLNTB-1C2L-V3.0" if BOARD_CWWK_CW_ADLNTB_1C2L_V3
+
+config MAINBOARD_SMBIOS_PRODUCT_NAME
+	default "CW-ADL-4L-V1.0"      if BOARD_CWWK_CW_ADL_4L_V1
+	default "CW-X86-P5-V3"        if BOARD_CWWK_CW_ADLNTB_1C2L_V3
+
+config MAINBOARD_VERSION
+	default "CW-ADL-4L-V1.0"      if BOARD_CWWK_CW_ADL_4L_V1
+	default "CW-ADLNTB-1C2L-V3.0" if BOARD_CWWK_CW_ADLNTB_1C2L_V3
+
+# Override the default variant behavior, since the data.vbt is the same
+config INTEL_GMA_VBT_FILE
+	default "src/mainboard/\$(MAINBOARDDIR)/data.vbt"
 
 config NO_POST
 	default y
diff --git a/src/mainboard/cwwk/adl/Kconfig.name b/src/mainboard/cwwk/adl/Kconfig.name
index 7faa8e4831..d102e3249f 100644
--- a/src/mainboard/cwwk/adl/Kconfig.name
+++ b/src/mainboard/cwwk/adl/Kconfig.name
@@ -1,4 +1,7 @@
 ## SPDX-License-Identifier: GPL-2.0-or-later
 
-config BOARD_CWWK_ADL_N
+config BOARD_CWWK_CW_ADL_4L_V1
 	bool "CW-ADL-4L-V1.0"
+
+config BOARD_CWWK_CW_ADLNTB_1C2L_V3
+	bool "CW-ADLNTB-1C2L-V3.0"
diff --git a/src/mainboard/cwwk/adl/Makefile.mk b/src/mainboard/cwwk/adl/Makefile.mk
index 89eb072db2..432208bf6c 100644
--- a/src/mainboard/cwwk/adl/Makefile.mk
+++ b/src/mainboard/cwwk/adl/Makefile.mk
@@ -1,7 +1,10 @@
 /* SPDX-License-Identifier: GPL-2.0-or-later */
 
+CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/include
+
 bootblock-y += bootblock.c
 
-romstage-y += romstage_fsp_params.c
+romstage-y += variants/$(VARIANT_DIR)/romstage.c
 
-ramstage-y += mainboard.c
+ramstage-y += ramstage.c
+ramstage-y += variants/$(VARIANT_DIR)/gpio.c
diff --git a/src/mainboard/cwwk/adl/board_info.txt b/src/mainboard/cwwk/adl/board_info.txt
index b53863c87c..7166620e9b 100644
--- a/src/mainboard/cwwk/adl/board_info.txt
+++ b/src/mainboard/cwwk/adl/board_info.txt
@@ -1,6 +1,6 @@
 Vendor name: CWWK
-Board name: CW-ADL-4L-V1.0
 Category: eval
+ROM package: SOIC-8
 ROM protocol: SPI
 ROM socketed: n
 Flashrom support: y
diff --git a/src/mainboard/cwwk/adl/include/mainboard/gpio.h b/src/mainboard/cwwk/adl/include/mainboard/gpio.h
new file mode 100644
index 0000000000..ef2a21c418
--- /dev/null
+++ b/src/mainboard/cwwk/adl/include/mainboard/gpio.h
@@ -0,0 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef MAINBOARD_GPIO_H
+#define MAINBOARD_GPIO_H
+
+void mainboard_configure_gpios(void);
+
+#endif
diff --git a/src/mainboard/cwwk/adl/mainboard.c b/src/mainboard/cwwk/adl/ramstage.c
similarity index 71%
rename from src/mainboard/cwwk/adl/mainboard.c
rename to src/mainboard/cwwk/adl/ramstage.c
index b15d01728b..fb968e1026 100644
--- a/src/mainboard/cwwk/adl/mainboard.c
+++ b/src/mainboard/cwwk/adl/ramstage.c
@@ -1,11 +1,11 @@
 /* SPDX-License-Identifier: GPL-2.0-or-later */
 
+#include <mainboard/gpio.h>
 #include <soc/ramstage.h>
-#include "gpio.h"
 
 static void mainboard_init(void *chip_info)
 {
-	gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table));
+	mainboard_configure_gpios();
 }
 
 struct chip_operations mainboard_ops = {
diff --git a/src/mainboard/cwwk/adl/variants/cw-adl-4l-v1.0/board_info.txt b/src/mainboard/cwwk/adl/variants/cw-adl-4l-v1.0/board_info.txt
new file mode 100644
index 0000000000..5eba41ce2b
--- /dev/null
+++ b/src/mainboard/cwwk/adl/variants/cw-adl-4l-v1.0/board_info.txt
@@ -0,0 +1,2 @@
+Board name: CW-ADL-4L-V1.0
+Release year: 2024
diff --git a/src/mainboard/cwwk/adl/gpio.h b/src/mainboard/cwwk/adl/variants/cw-adl-4l-v1.0/gpio.c
similarity index 98%
rename from src/mainboard/cwwk/adl/gpio.h
rename to src/mainboard/cwwk/adl/variants/cw-adl-4l-v1.0/gpio.c
index fc3d7ead15..0223539cbb 100644
--- a/src/mainboard/cwwk/adl/gpio.h
+++ b/src/mainboard/cwwk/adl/variants/cw-adl-4l-v1.0/gpio.c
@@ -1,8 +1,6 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
-#ifndef CFG_GPIO_H
-#define CFG_GPIO_H
-
+#include <mainboard/gpio.h>
 #include <soc/gpio.h>
 
 /* Pad configuration was generated automatically using intelp2m utility */
@@ -294,4 +292,7 @@ static const struct pad_config gpio_table[] = {
 	PAD_NC(GPP_R7, NONE),	/* GPIO */
 };
 
-#endif /* CFG_GPIO_H */
+void mainboard_configure_gpios(void)
+{
+	gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table));
+}
diff --git a/src/mainboard/cwwk/adl/romstage_fsp_params.c b/src/mainboard/cwwk/adl/variants/cw-adl-4l-v1.0/romstage.c
similarity index 100%
rename from src/mainboard/cwwk/adl/romstage_fsp_params.c
rename to src/mainboard/cwwk/adl/variants/cw-adl-4l-v1.0/romstage.c
diff --git a/src/mainboard/cwwk/adl/variants/cw-adlntb-1c2l-v3.0/board_info.txt b/src/mainboard/cwwk/adl/variants/cw-adlntb-1c2l-v3.0/board_info.txt
new file mode 100644
index 0000000000..e466a7a513
--- /dev/null
+++ b/src/mainboard/cwwk/adl/variants/cw-adlntb-1c2l-v3.0/board_info.txt
@@ -0,0 +1,2 @@
+Board name: CW-X86-P5-V3
+Release year: 2024
diff --git a/src/mainboard/cwwk/adl/variants/cw-adlntb-1c2l-v3.0/gpio.c b/src/mainboard/cwwk/adl/variants/cw-adlntb-1c2l-v3.0/gpio.c
new file mode 100644
index 0000000000..ab16207ea0
--- /dev/null
+++ b/src/mainboard/cwwk/adl/variants/cw-adlntb-1c2l-v3.0/gpio.c
@@ -0,0 +1,298 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <mainboard/gpio.h>
+#include <soc/gpio.h>
+
+/* Pad configuration was generated automatically using intelp2m utility */
+static const struct pad_config gpio_table[] = {
+
+	/* ------- GPIO Community 0 ------- */
+
+	/* ------- GPIO Group GPP_B ------- */
+	PAD_CFG_NF(GPP_B0, NONE, DEEP, NF1),	/* CORE_VID0 */
+	PAD_CFG_NF(GPP_B1, NONE, DEEP, NF1),	/* CORE_VID1 */
+	PAD_CFG_NF(GPP_B2, NONE, DEEP, NF1),	/* VRALERT# */
+	PAD_NC(GPP_B3, NONE),	/* GPIO */
+	PAD_NC(GPP_B4, NONE),	/* GPIO */
+	PAD_NC(GPP_B5, NONE),	/* GPIO */
+	PAD_NC(GPP_B6, NONE),	/* GPIO */
+	PAD_NC(GPP_B7, NONE),	/* GPIO */
+	PAD_NC(GPP_B8, NONE),	/* GPIO */
+	PAD_NC(GPP_B9, NONE),	/* GPIO */
+	PAD_NC(GPP_B10, NONE),	/* GPIO */
+	//PAD_CFG_NF(GPP_B11, NONE, RSMRST, NF1),	/* PMCALERT# */
+	PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1),	/* SLP_S0# */
+	PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1),	/* PLTRST# */
+	PAD_CFG_NF(GPP_B14, NONE, PLTRST, NF1),	/* SPKR */
+	PAD_NC(GPP_B15, NONE),	/* GPIO */
+	PAD_NC(GPP_B16, NONE),	/* GPIO */
+	PAD_NC(GPP_B17, NONE),	/* GPIO */
+	PAD_CFG_GPO(GPP_B18, 0, PLTRST),	/* GPIO */
+	PAD_NC(GPP_B19, NONE),	/* GPIO */
+	PAD_NC(GPP_B20, NONE),	/* GPIO */
+	PAD_NC(GPP_B21, NONE),	/* GPIO */
+	PAD_NC(GPP_B22, NONE),	/* GPIO */
+	PAD_CFG_GPO(GPP_B23, 1, PLTRST),	/* GPIO */
+	PAD_CFG_NF(GPP_B24, NONE, DEEP, NF1),	/* GSPI0_CLK_LOOPBK */
+	PAD_CFG_NF(GPP_B25, NONE, DEEP, NF1),	/* GSPI1_CLK_LOOPBK */
+
+	/* ------- GPIO Group GPP_T ------- */
+	PAD_NC(GPP_T0, NONE),	/* GPIO */
+	PAD_NC(GPP_T1, NONE),	/* GPIO */
+	PAD_CFG_NF(GPP_T2, DN_20K, DEEP, NF2),	/* FUSA_DIAGTEST_EN */
+	PAD_CFG_NF(GPP_T3, DN_20K, DEEP, NF2),	/* FUSA_DIAGTEST_MODE */
+	PAD_NC(GPP_T4, NONE),	/* GPIO */
+	PAD_NC(GPP_T5, NONE),	/* GPIO */
+	PAD_NC(GPP_T6, NONE),	/* GPIO */
+	PAD_NC(GPP_T7, NONE),	/* GPIO */
+	PAD_NC(GPP_T8, NONE),	/* GPIO */
+	PAD_NC(GPP_T9, NONE),	/* GPIO */
+	PAD_NC(GPP_T10, NONE),	/* GPIO */
+	PAD_NC(GPP_T11, NONE),	/* GPIO */
+	PAD_NC(GPP_T12, NONE),	/* GPIO */
+	PAD_NC(GPP_T13, NONE),	/* GPIO */
+	PAD_NC(GPP_T14, NONE),	/* GPIO */
+	PAD_NC(GPP_T15, NONE),	/* GPIO */
+
+	/* ------- GPIO Group GPP_A ------- */
+	PAD_CFG_NF(GPP_A0, UP_20K, DEEP, NF1),	/* ESPI_IO0 */
+	PAD_CFG_NF(GPP_A1, UP_20K, DEEP, NF1),	/* ESPI_IO1 */
+	PAD_CFG_NF(GPP_A2, UP_20K, DEEP, NF1),	/* ESPI_IO2 */
+	PAD_CFG_NF(GPP_A3, UP_20K, DEEP, NF1),	/* ESPI_IO3 */
+	PAD_CFG_NF(GPP_A4, UP_20K, DEEP, NF1),	/* ESPI_CS0# */
+	PAD_CFG_NF(GPP_A5, UP_20K, DEEP, NF1),	/* ESPI_ALERT0# */
+	PAD_CFG_NF(GPP_A6, UP_20K, DEEP, NF1),	/* ESPI_ALERT1# */
+	PAD_CFG_GPO(GPP_A7, 1, PLTRST),	/* GPIO */
+	PAD_CFG_GPO(GPP_A8, 0, PLTRST),	/* GPIO */
+	PAD_CFG_NF(GPP_A9, DN_20K, DEEP, NF1),	/* ESPI_CLK */
+	PAD_CFG_NF(GPP_A10, NONE, DEEP, NF1),	/* ESPI_RESET# */
+	PAD_CFG_GPO(GPP_A11, 1, PLTRST),	/* GPIO */
+	PAD_NC(GPP_A12, NONE),	/* GPIO */
+	PAD_CFG_GPO(GPP_A13, 1, DEEP),	/* GPIO */
+	PAD_NC(GPP_A14, NONE),	/* GPIO */
+	PAD_CFG_GPO(GPP_A15, 1, DEEP),	/* GPIO */
+	PAD_NC(GPP_A16, NONE),	/* GPIO */
+	PAD_CFG_GPO(GPP_A17, 1, PLTRST),	/* GPIO */
+	PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1),	/* DDSP_HPDB */
+	PAD_CFG_NF(GPP_A19, NONE, DEEP, NF1),	/* DDSP_HPD1 */
+	PAD_NC(GPP_A20, NONE),	/* GPIO */
+	PAD_CFG_GPO(GPP_A21, 1, PLTRST),	/* GPIO */
+	PAD_NC(GPP_A22, NONE),	/* GPIO */
+	PAD_CFG_NF(GPP_A23, UP_20K, DEEP, NF1),	/* ESPI_CS1# */
+	PAD_CFG_NF(GPP_ESPI_CLK_LOOPBK, NONE, DEEP, NF1),	/* GPP_ESPI_CLK_LOOPBK */
+
+	/* ------- GPIO Community 1 ------- */
+
+	/* ------- GPIO Group GPP_S ------- */
+	PAD_NC(GPP_S0, NONE),	/* GPIO */
+	PAD_NC(GPP_S1, NONE),	/* GPIO */
+	PAD_NC(GPP_S2, NONE),	/* GPIO */
+	PAD_NC(GPP_S3, NONE),	/* GPIO */
+	PAD_NC(GPP_S4, NONE),	/* GPIO */
+	PAD_NC(GPP_S5, NONE),	/* GPIO */
+	PAD_NC(GPP_S6, NONE),	/* GPIO */
+	PAD_NC(GPP_S7, NONE),	/* GPIO */
+
+	/* ------- GPIO Group GPP_I ------- */
+	PAD_NC(GPP_I0, NONE),	/* GPIO */
+	PAD_NC(GPP_I1, NONE),	/* GPIO */
+	PAD_NC(GPP_I2, NONE),	/* GPIO */
+	PAD_NC(GPP_I3, NONE),	/* GPIO */
+	PAD_NC(GPP_I4, NONE),	/* GPIO */
+	PAD_NC(GPP_I5, NONE),	/* GPIO */
+	PAD_NC(GPP_I6, NONE),	/* GPIO */
+	PAD_CFG_NF(GPP_I7, NONE, DEEP, NF1),	/* EMMC_CMD */
+	PAD_CFG_NF(GPP_I8, NONE, DEEP, NF1),	/* EMMC_DATA0 */
+	PAD_CFG_NF(GPP_I9, NONE, DEEP, NF1),	/* EMMC_DATA1 */
+	PAD_CFG_NF(GPP_I10, NONE, DEEP, NF1),	/* EMMC_DATA2 */
+	PAD_CFG_NF(GPP_I11, NONE, DEEP, NF1),	/* EMMC_DATA3 */
+	PAD_CFG_NF(GPP_I12, NONE, DEEP, NF1),	/* EMMC_DATA4 */
+	PAD_CFG_NF(GPP_I13, NONE, DEEP, NF1),	/* EMMC_DATA5 */
+	PAD_CFG_NF(GPP_I14, NONE, DEEP, NF1),	/* EMMC_DATA6 */
+	PAD_CFG_NF(GPP_I15, NONE, DEEP, NF1),	/* EMMC_DATA7 */
+	PAD_CFG_NF(GPP_I16, NONE, DEEP, NF1),	/* EMMC_RCLK */
+	PAD_CFG_NF(GPP_I17, NONE, DEEP, NF1),	/* EMMC_CLK */
+	PAD_CFG_NF(GPP_I18, NONE, DEEP, NF1),	/* EMMC_RESET# */
+	PAD_NC(GPP_I19, NONE),	/* GPIO */
+
+	/* ------- GPIO Group GPP_H ------- */
+	PAD_CFG_GPO(GPP_H0, 1, PLTRST),	/* GPIO */
+	PAD_CFG_GPO(GPP_H1, 1, PLTRST),	/* GPIO */
+	PAD_CFG_GPO(GPP_H2, 1, RSMRST),	/* GPIO */
+	PAD_CFG_GPO(GPP_H3, 1, PLTRST),	/* GPIO */
+	PAD_NC(GPP_H4, NONE),	/* GPIO */
+	PAD_NC(GPP_H5, NONE),	/* GPIO */
+	PAD_NC(GPP_H6, NONE),	/* GPIO */
+	PAD_NC(GPP_H7, NONE),	/* GPIO */
+	PAD_NC(GPP_H8, NONE),	/* GPIO */
+	PAD_NC(GPP_H9, NONE),	/* GPIO */
+	PAD_NC(GPP_H10, NONE),	/* GPIO */
+	PAD_NC(GPP_H11, NONE),	/* GPIO */
+	PAD_NC(GPP_H12, NONE),	/* GPIO */
+	PAD_NC(GPP_H13, NONE),	/* GPIO */
+	PAD_NC(GPP_H14, NONE),	/* GPIO */
+	PAD_CFG_NF(GPP_H15, NONE, DEEP, NF1),	/* DDPB_CTRLCLK */
+	PAD_NC(GPP_H16, NONE),	/* GPIO */
+	PAD_CFG_NF(GPP_H17, NONE, DEEP, NF1),	/* DDPB_CTRLDATA */
+	PAD_CFG_NF(GPP_H18, NONE, DEEP, NF1),	/* PROC_C10_GATE# */
+	PAD_NC(GPP_H19, NONE),	/* GPIO */
+	PAD_NC(GPP_H20, NONE),	/* GPIO */
+	PAD_NC(GPP_H21, NONE),	/* GPIO */
+	PAD_NC(GPP_H22, NONE),	/* GPIO */
+	PAD_NC(GPP_H23, NONE),	/* GPIO */
+
+	/* ------- GPIO Group GPP_D ------- */
+	PAD_NC(GPP_D0, NONE),	/* GPIO */
+	PAD_NC(GPP_D1, NONE),	/* GPIO */
+	PAD_NC(GPP_D2, NONE),	/* GPIO */
+	PAD_NC(GPP_D3, NONE),	/* GPIO */
+	PAD_NC(GPP_D4, NONE),	/* GPIO */
+	PAD_CFG_NF(GPP_D5, NONE, DEEP, NF1),	/* SRCCLKREQ0# */
+	PAD_CFG_NF(GPP_D6, NONE, DEEP, NF1),	/* SRCCLKREQ1# */
+	PAD_CFG_NF(GPP_D7, NONE, DEEP, NF1),	/* SRCCLKREQ2# */
+	PAD_CFG_NF(GPP_D8, NONE, DEEP, NF1),	/* SRCCLKREQ3# */
+	PAD_CFG_NF(GPP_D9, NATIVE, DEEP, NF5),	/* BSSB_LS2_RX */
+	PAD_CFG_NF(GPP_D10, NATIVE, DEEP, NF5),	/* BSSB_LS2_TX */
+	PAD_CFG_GPO(GPP_D11, 1, DEEP),	/* GPIO */
+	PAD_CFG_NF(GPP_D12, NATIVE, DEEP, NF5),	/* BSSB_LS3_TX */
+	PAD_CFG_GPO(GPP_D13, 1, DEEP),	/* GPIO */
+	PAD_CFG_GPO(GPP_D14, 1, DEEP),	/* GPIO */
+	PAD_NC(GPP_D15, NONE),	/* GPIO */
+	PAD_CFG_GPO(GPP_D16, 1, PLTRST),	/* GPIO */
+	PAD_NC(GPP_D17, NONE),	/* GPIO */
+	PAD_NC(GPP_D18, NONE),	/* GPIO */
+	PAD_NC(GPP_D19, NONE),	/* GPIO */
+	PAD_CFG_NF(GPP_GSPI2_CLK_LOOPBK, NONE, DEEP, NF1),	/* GPP_GSPI2_CLK_LOOPBK */
+
+	/* ------- GPIO Group vGPIO ------- */
+
+	/* ------- GPIO Community 2 ------- */
+
+	/* ------- GPIO Group GPP_GPD ------- */
+	PAD_CFG_NF(GPD0, UP_20K, PWROK, NF1),	/* BATLOW# */
+	PAD_CFG_NF(GPD1, NATIVE, PWROK, NF1),	/* ACPRESENT */
+	PAD_CFG_GPO(GPD2, 1, DEEP),	/* GPIO */
+	PAD_CFG_NF(GPD3, UP_20K, PWROK, NF1),	/* PWRBTN# */
+	PAD_CFG_NF(GPD4, NONE, PWROK, NF1),	/* SLP_S3# */
+	PAD_CFG_NF(GPD5, NONE, PWROK, NF1),	/* SLP_S4# */
+	PAD_CFG_NF(GPD6, NONE, PWROK, NF1),	/* SLP_A# */
+	PAD_CFG_GPO(GPD7, 1, PLTRST),	/* GPIO */
+	PAD_CFG_NF(GPD8, NONE, PWROK, NF1),	/* SUSCLK */
+	PAD_CFG_NF(GPD9, NONE, PWROK, NF1),	/* SLP_WLAN# */
+	PAD_CFG_NF(GPD10, NONE, PWROK, NF1),	/* SLP_S5# */
+	PAD_CFG_GPO(GPD11, 0, PWROK),	/* GPIO */
+	PAD_CFG_NF(GPD_INPUT3VSEL, NONE, PWROK, NF1),	/* GPD_INPUT3VSEL */
+	PAD_CFG_NF(GPD_SLP_LANB, NONE, PWROK, NF1),	/* GPD_SLP_LANB */
+	PAD_CFG_NF(GPD_SLP_SUSB, NONE, PWROK, NF1),	/* GPD_SLP_SUSB */
+	PAD_CFG_NF(GPD_WAKEB, NONE, PWROK, NF1),	/* GPD_WAKEB */
+	PAD_CFG_NF(GPD_DRAM_RESETB, NONE, PWROK, NF1),	/* GPD_DRAM_RESETB */
+
+	/* ------- GPIO Group PCIe vGPIO ------- */
+
+	/* ------- GPIO Community 4 ------- */
+
+	/* ------- GPIO Group GPP_C ------- */
+	PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1),	/* SMBCLK */
+	PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1),	/* SMBDATA */
+	PAD_CFG_GPO(GPP_C2, 0, DEEP),	/* GPIO */
+	PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1),	/* SML0CLK */
+	PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1),	/* SML0DATA */
+	PAD_CFG_GPO(GPP_C5, 0, DEEP),	/* GPIO */
+	PAD_CFG_NF(GPP_C6, NONE, RSMRST, NF1),	/* SML1CLK */
+	PAD_CFG_NF(GPP_C7, NONE, RSMRST, NF1),	/* SML1DATA */
+	PAD_NC(GPP_C8, NONE),	/* GPIO */
+	PAD_NC(GPP_C9, NONE),	/* GPIO */
+	PAD_NC(GPP_C10, NONE),	/* GPIO */
+	PAD_NC(GPP_C11, NONE),	/* GPIO */
+	PAD_NC(GPP_C12, NONE),	/* GPIO */
+	PAD_NC(GPP_C13, NONE),	/* GPIO */
+	PAD_NC(GPP_C14, NONE),	/* GPIO */
+	PAD_NC(GPP_C15, NONE),	/* GPIO */
+	PAD_NC(GPP_C16, NONE),	/* GPIO */
+	PAD_NC(GPP_C17, NONE),	/* GPIO */
+	PAD_NC(GPP_C18, NONE),	/* GPIO */
+	PAD_NC(GPP_C19, NONE),	/* GPIO */
+	PAD_NC(GPP_C20, NONE),	/* GPIO */
+	PAD_NC(GPP_C21, NONE),	/* GPIO */
+	PAD_NC(GPP_C22, NONE),	/* GPIO */
+	PAD_NC(GPP_C23, NONE),	/* GPIO */
+
+	/* ------- GPIO Group GPP_F ------- */
+	PAD_CFG_NF(GPP_F0, NONE, DEEP, NF1),	/* CNV_BRI_DT */
+	PAD_CFG_NF(GPP_F1, UP_20K, DEEP, NF1),	/* CNV_BRI_RSP */
+	PAD_CFG_NF(GPP_F2, NONE, DEEP, NF1),	/* CNV_RGI_DT */
+	PAD_CFG_NF(GPP_F3, UP_20K, DEEP, NF1),	/* CNV_RGI_RSP */
+	PAD_CFG_NF(GPP_F4, NONE, DEEP, NF1),	/* CNV_RF_RESET# */
+	PAD_CFG_NF(GPP_F5, NONE, DEEP, NF2),	/* MODEM_CLKREQ */
+	PAD_NC(GPP_F6, NONE),	/* GPIO */
+	PAD_CFG_GPO(GPP_F7, 0, DEEP),	/* GPIO */
+	PAD_NC(GPP_F8, NONE),	/* GPIO */
+	PAD_CFG_NF(GPP_F9, NONE, DEEP, NF1),	/* BOOTMPC */
+	PAD_CFG_GPO(GPP_F10, 1, PLTRST),	/* GPIO */
+	PAD_NC(GPP_F11, NONE),	/* GPIO */
+	PAD_NC(GPP_F12, NONE),	/* GPIO */
+	PAD_NC(GPP_F13, NONE),	/* GPIO */
+	PAD_NC(GPP_F14, NONE),	/* GPIO */
+	PAD_NC(GPP_F15, NONE),	/* GPIO */
+	PAD_NC(GPP_F16, NONE),	/* GPIO */
+	PAD_NC(GPP_F17, NONE),	/* GPIO */
+	PAD_NC(GPP_F18, NONE),	/* GPIO */
+	PAD_NC(GPP_F19, NONE),	/* GPIO */
+	PAD_CFG_NF(GPP_F20, NONE, DEEP, NF1),	/* Reserved */
+	PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1),	/* Reserved */
+	PAD_NC(GPP_F22, NONE),	/* GPIO */
+	PAD_NC(GPP_F23, NONE),	/* GPIO */
+	PAD_NC(GPP_F_CLK_LOOPBK, NONE),	/* GPIO */
+
+	/* ------- GPIO Group GPP_HVCMOS ------- */
+	PAD_CFG_NF(GPP_L_BKLTEN, NONE, DEEP, NF1),	/* n/a */
+	PAD_CFG_NF(GPP_L_BKLTCTL, NONE, DEEP, NF1),	/* n/a */
+	PAD_CFG_NF(GPP_L_VDDEN, NONE, DEEP, NF1),	/* n/a */
+	PAD_CFG_NF(GPP_SYS_PWROK, NONE, DEEP, NF1),	/* n/a */
+	PAD_CFG_NF(GPP_SYS_RESETB, NONE, DEEP, NF1),	/* n/a */
+	PAD_CFG_NF(GPP_MLK_RSTB, NONE, DEEP, NF1),	/* n/a */
+
+	/* ------- GPIO Group GPP_E ------- */
+	PAD_CFG_GPO(GPP_E0, 1, DEEP),	/* GPIO */
+	PAD_NC(GPP_E1, NONE),	/* GPIO */
+	PAD_NC(GPP_E2, NONE),	/* GPIO */
+	PAD_CFG_GPO(GPP_E3, 1, DEEP),	/* GPIO */
+	PAD_CFG_GPO(GPP_E4, 1, PLTRST),	/* GPIO */
+	PAD_NC(GPP_E5, NONE),	/* GPIO */
+	PAD_CFG_GPO(GPP_E6, 0, DEEP),	/* GPIO */
+	PAD_CFG_GPI_TRIG_OWN(GPP_E7, NONE, PLTRST, OFF, ACPI),	/* GPIO */
+	PAD_NC(GPP_E8, NONE),	/* GPIO */
+	PAD_NC(GPP_E9, NONE),	/* GPIO */
+	PAD_NC(GPP_E10, NONE),	/* GPIO */
+	PAD_NC(GPP_E11, NONE),	/* GPIO */
+	PAD_NC(GPP_E12, NONE),	/* GPIO */
+	PAD_NC(GPP_E13, NONE),	/* GPIO */
+	PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1),	/* DDSP_HPDA */
+	PAD_CFG_GPO(GPP_E15, 1, PLTRST),	/* GPIO */
+	PAD_CFG_GPO(GPP_E16, 0, PLTRST),	/* GPIO */
+	PAD_NC(GPP_E17, NONE),	/* GPIO */
+	PAD_NC(GPP_E18, NATIVE),	/* GPIO */
+	PAD_NC(GPP_E19, NATIVE),	/* GPIO */
+	PAD_NC(GPP_E20, NONE),	/* GPIO */
+	PAD_NC(GPP_E21, NONE),	/* GPIO */
+	PAD_CFG_NF(GPP_E22, DN_20K, DEEP, NF1),	/* DDPA_CTRLCLK */
+	PAD_CFG_NF(GPP_E23, NONE, DEEP, NF1),	/* DDPA_CTRLDATA */
+	PAD_NC(GPP_E_CLK_LOOPBK, NONE),	/* GPIO */
+
+	/* ------- GPIO Community 5 ------- */
+
+	/* ------- GPIO Group GPP_R ------- */
+	PAD_CFG_NF(GPP_R0, NONE, DEEP, NF1),	/* HDA_BCLK */
+	PAD_CFG_NF(GPP_R1, NATIVE, DEEP, NF1),	/* HDA_SYNC */
+	PAD_CFG_NF(GPP_R2, NATIVE, DEEP, NF1),	/* HDA_SDO */
+	PAD_CFG_NF(GPP_R3, NATIVE, DEEP, NF1),	/* HDA_SDI0 */
+	PAD_CFG_NF(GPP_R4, NONE, DEEP, NF1),	/* HDA_RST# */
+	PAD_NC(GPP_R5, NONE),	/* GPIO */
+	PAD_NC(GPP_R6, NONE),	/* GPIO */
+	PAD_NC(GPP_R7, NONE),	/* GPIO */
+};
+
+void mainboard_configure_gpios(void)
+{
+	gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table));
+}
diff --git a/src/mainboard/cwwk/adl/variants/cw-adlntb-1c2l-v3.0/romstage.c b/src/mainboard/cwwk/adl/variants/cw-adlntb-1c2l-v3.0/romstage.c
new file mode 100644
index 0000000000..cd32138416
--- /dev/null
+++ b/src/mainboard/cwwk/adl/variants/cw-adlntb-1c2l-v3.0/romstage.c
@@ -0,0 +1,28 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <fsp/api.h>
+#include <soc/meminit.h>
+#include <soc/romstage.h>
+
+void mainboard_memory_init_params(FSPM_UPD *memupd)
+{
+	static const struct mb_cfg ddr5_mem_config = {
+		.type = MEM_TYPE_DDR5,
+
+		.ect = true, /* Early Command Training */
+
+		.UserBd = BOARD_TYPE_MOBILE,
+
+		.LpDdrDqDqsReTraining = 1,
+	};
+
+	const struct mem_spd dimm_module_spd_info = {
+		.topo = MEM_TOPO_DIMM_MODULE,
+		.smbus = {
+			[0] = { .addr_dimm[0] = 0x52, },
+		},
+	};
+
+	const bool half_populated = false;
+	memcfg_init(memupd, &ddr5_mem_config, &dimm_module_spd_info, half_populated);
+}

From 3c0fe9ef3b6f212b1ac666a182c957a15f0fa2b6 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Micha=C5=82=20=C5=BBygowski?= <michal.zygowski@3mdeb.com>
Date: Mon, 31 Mar 2025 15:31:57 +0200
Subject: [PATCH 0657/3886] mb/protectli/vault_ehl/devicetree.cb: Fix assertion
 in soc/pmutil
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

The SoC code requires for GPE DW config values to be different.
Assign the default values of PMC GPIO_CONF register as GPIO GPEs
are not used on this platform. Fixes the assertion in
soc/intel/elkhartalke/pmutil.

TEST=Boot Protectli VP2420 to Ubuntu 24.04.

Change-Id: Ibf4a1f52bf970c27d0ca8dd1b1377d6a5e6477f9
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87049
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
---
 src/mainboard/protectli/vault_ehl/devicetree.cb | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/src/mainboard/protectli/vault_ehl/devicetree.cb b/src/mainboard/protectli/vault_ehl/devicetree.cb
index 10782b265d..0db005f1e8 100644
--- a/src/mainboard/protectli/vault_ehl/devicetree.cb
+++ b/src/mainboard/protectli/vault_ehl/devicetree.cb
@@ -18,9 +18,9 @@ chip soc/intel/elkhartlake
 	# route, i.e., if this route changes then the affected GPE
 	# offset bits also need to be changed. This sets the PMC register
 	# GPE_CFG fields.
-	#register "pmc_gpe0_dw1" = "PMC_GPE_SCC_63_32"
-	#register "pmc_gpe0_dw2" = "PMC_GPE_N_31_0"
-	#register "pmc_gpe0_dw3" = "PMC_GPE_SCC_31_0"
+	register "pmc_gpe0_dw0" = "PMC_GPP_A"
+	register "pmc_gpe0_dw1" = "PMC_GPP_R"
+	register "pmc_gpe0_dw2" = "PMC_GPD"
 
 	register "tcc_offset" = "5" # TCC of 95C
 

From 0b7b68389a9f77ec85277a3c350a49c0ff056a3f Mon Sep 17 00:00:00 2001
From: Daniel Peng <Daniel_Peng@pegatron.corp-partner.google.com>
Date: Tue, 1 Apr 2025 16:01:14 +0800
Subject: [PATCH 0658/3886] mb/google/nissa/var/guren: Add WFC for
 AZWAVE/AM-3BA5533-B module

New WFC function for Guren360 project.
ID of Vendor and Product for AZWAVE/AM-3BA5533-B module are 13d3:5533.
1. Add WFC fw_config setting
2. Used USB2 Port7 for WFC

BUG=b:406164678
BRANCH=firmware-nissa-15217.B
TEST=1. emerge-nissa coreboot chromeos-bootimage
     2. Verified with local build bios via command lsusb
        for 13d3:5533 and SSFC WFC enable

Change-Id: Ia2ab019fe76c503cc669ebf4aa8b3d7ae72269c1
Signed-off-by: Daniel Peng <Daniel_Peng@pegatron.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87054
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Jayvik Desai <jayvik@google.com>
Reviewed-by: Daniel Peng <daniel_peng@pegatron.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
---
 .../google/brya/variants/guren/overridetree.cb        | 11 +++++++++--
 src/mainboard/google/brya/variants/guren/variant.c    |  5 +++++
 2 files changed, 14 insertions(+), 2 deletions(-)

diff --git a/src/mainboard/google/brya/variants/guren/overridetree.cb b/src/mainboard/google/brya/variants/guren/overridetree.cb
index 77ec260074..8b1adb14f9 100644
--- a/src/mainboard/google/brya/variants/guren/overridetree.cb
+++ b/src/mainboard/google/brya/variants/guren/overridetree.cb
@@ -21,6 +21,10 @@ fw_config
 		option WIFI_SAR_ID_INTEL_CONVERTIBLE		 0
 		option WIFI_SAR_ID_INTEL_CLAMSHELL		 1
 	end
+	field WFC 17 18
+		option WFC_ABSENT		0
+		option WFC_PRESENT		1
+	end
 	field TOUCHSCREEN_SOURCE 32 34
 		option TOUCHSCREEN_UNPROVISIONED	0
 		option TOUCHSCREEN_ELAN0001		1
@@ -87,6 +91,7 @@ chip soc/intel/alderlake
 	register "typec_aux_bias_pads[0]" = "{.pad_auxp_dc = GPP_E22, .pad_auxn_dc = GPP_E23}"
 	register "typec_aux_bias_pads[1]" = "{.pad_auxp_dc = GPP_A21, .pad_auxn_dc = GPP_A22}"
 
+	register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)"     # WFC
 	register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)"	# Bluetooth port for CNVi WLAN
 
 	# Configure external V1P05/Vnn/VnnSx Rails
@@ -595,9 +600,11 @@ chip soc/intel/alderlake
 						device ref usb2_port6 on end
 					end
 					chip drivers/usb/acpi
-						register "desc" = ""USB2 Camera""
+						register "desc" = ""USB2 WFC""
 						register "type" = "UPC_TYPE_INTERNAL"
-						device ref usb2_port7 on end
+						device ref usb2_port7 on
+							probe WFC WFC_PRESENT
+						end
 					end
 					chip drivers/usb/acpi
 						register "desc" = ""USB2 Bluetooth""
diff --git a/src/mainboard/google/brya/variants/guren/variant.c b/src/mainboard/google/brya/variants/guren/variant.c
index c2c49f824e..4949083fd7 100644
--- a/src/mainboard/google/brya/variants/guren/variant.c
+++ b/src/mainboard/google/brya/variants/guren/variant.c
@@ -18,4 +18,9 @@ void variant_update_soc_chip_config(struct soc_intel_alderlake_config *config)
 		printk(BIOS_INFO, "Enable DDI PORT 2 for HPD and DDC.\n");
 		config->ddi_ports_config[DDI_PORT_2] = DDI_ENABLE_HPD | DDI_ENABLE_DDC;
 	}
+
+	if (!fw_config_probe(FW_CONFIG(WFC, WFC_PRESENT))) {
+		printk(BIOS_INFO, "Disable usb2_port7 of WFC.\n");
+		config->usb2_ports[6] = (struct usb2_port_config) USB2_PORT_EMPTY;
+	}
 }

From 77d0313358de7996985340a7aff26ac8039619f5 Mon Sep 17 00:00:00 2001
From: Subrata Banik <subratabanik@google.com>
Date: Fri, 4 Apr 2025 13:06:58 +0530
Subject: [PATCH 0659/3886] {commonlib, lib}: Add timestamp for early chip
 initialization

This commit introduces a new timestamp `TS_DEVICE_INIT_CHIPS` to
specifically mark the start of the `dev_initialize_chips()` function.

Previously, the `TS_DEVICE_ENUMERATE` timestamp was incorrectly
associated with the `bs_dev_init_chips` function.

This patch corrects this by:

- Adding the `TS_DEVICE_INIT_CHIPS` enum and name definition.
- Updating `bs_dev_init_chips` in `src/lib/hardwaremain.c` to use
  `TS_DEVICE_INIT_CHIPS`.
- Moving the `TS_DEVICE_ENUMERATE` timestamp addition to the
  `bs_dev_enumerate` function where device enumeration actually begins.

This change provides a more accurate and meaningful timestamp for the
early chipset initialization phase.

TEST=Able to build and boot google/fatcat.

```
971:loading FSP-S                                     836,277 (10,658)
  17:starting LZ4 decompress (ignore for x86)          847,297 (11,019)
  18:finished LZ4 decompress (ignore for x86)          847,376 (79)
  30:early chipset initialization                      854,579 (7,203)
  17:starting LZ4 decompress (ignore for x86)          863,483 (8,903)
  18:finished LZ4 decompress (ignore for x86)          863,490 (6)
  17:starting LZ4 decompress (ignore for x86)          875,196 (11,705)
  18:finished LZ4 decompress (ignore for x86)          875,237 (41)
 954:calling FspSiliconInit                            875,344 (107)
 955:returning from FspSiliconInit                     942,740 (67,396)
 962:calling FspMultiPhaseSiInit                       942,744 (4)
 963:returning from FspMultiPhaseSiInit                1,081,355 (138,610)
  31:device enumeration                                1,081,708 (352)
  40:device configuration                              1,085,721 (4,013)
  50:device enable                                     1,091,517 (5,795)
```

Change-Id: Ib6860901c6b1528ec5098fc93240c6e65777642b
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87152
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Jayvik Desai <jayvik@google.com>
---
 src/commonlib/include/commonlib/timestamp_serialized.h | 4 +++-
 src/lib/hardwaremain.c                                 | 4 +++-
 2 files changed, 6 insertions(+), 2 deletions(-)

diff --git a/src/commonlib/include/commonlib/timestamp_serialized.h b/src/commonlib/include/commonlib/timestamp_serialized.h
index f60e040c3b..6bcbabc890 100644
--- a/src/commonlib/include/commonlib/timestamp_serialized.h
+++ b/src/commonlib/include/commonlib/timestamp_serialized.h
@@ -37,7 +37,8 @@ enum timestamp_id {
 	TS_ULZMA_END = 16,
 	TS_ULZ4F_START = 17,
 	TS_ULZ4F_END = 18,
-	TS_DEVICE_ENUMERATE = 30,
+	TS_DEVICE_INIT_CHIPS = 30,
+	TS_DEVICE_ENUMERATE = 31,
 	TS_DEVICE_CONFIGURE = 40,
 	TS_DEVICE_ENABLE = 50,
 	TS_DEVICE_INITIALIZE = 60,
@@ -218,6 +219,7 @@ static const struct timestamp_id_to_name {
 	TS_NAME_DEF(TS_ULZMA_END, 0, "finished LZMA decompress (ignore for x86)"),
 	TS_NAME_DEF(TS_ULZ4F_START, TS_ULZ4F_END, "starting LZ4 decompress (ignore for x86)"),
 	TS_NAME_DEF(TS_ULZ4F_END, 0, "finished LZ4 decompress (ignore for x86)"),
+	TS_NAME_DEF(TS_DEVICE_INIT_CHIPS, TS_DEVICE_ENUMERATE, "early chipset initialization"),
 	TS_NAME_DEF(TS_DEVICE_ENUMERATE, TS_DEVICE_CONFIGURE, "device enumeration"),
 	TS_NAME_DEF(TS_DEVICE_CONFIGURE, TS_DEVICE_ENABLE,  "device configuration"),
 	TS_NAME_DEF(TS_DEVICE_ENABLE, TS_DEVICE_INITIALIZE, "device enable"),
diff --git a/src/lib/hardwaremain.c b/src/lib/hardwaremain.c
index fda6c62d2e..7e5d848af9 100644
--- a/src/lib/hardwaremain.c
+++ b/src/lib/hardwaremain.c
@@ -93,7 +93,7 @@ static boot_state_t bs_pre_device(void *arg)
 
 static boot_state_t bs_dev_init_chips(void *arg)
 {
-	timestamp_add_now(TS_DEVICE_ENUMERATE);
+	timestamp_add_now(TS_DEVICE_INIT_CHIPS);
 
 	/* Initialize chips early, they might disable unused devices. */
 	dev_initialize_chips();
@@ -103,6 +103,8 @@ static boot_state_t bs_dev_init_chips(void *arg)
 
 static boot_state_t bs_dev_enumerate(void *arg)
 {
+	timestamp_add_now(TS_DEVICE_ENUMERATE);
+
 	/* Find the devices we don't have hard coded knowledge about. */
 	dev_enumerate();
 

From 862d4811da3551a2d06dcc67f11d930ae457c8ae Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Mon, 7 Apr 2025 16:17:44 +0100
Subject: [PATCH 0660/3886] mb/starlabs/starbook/cml: Re-add the GPE
 configuration

These were previously removed, but doing so, slowed down the
brightness keys to approx. 3 seconds.

Re-add them to make them instant.

Change-Id: I3af197cd995bd947c6e72bf5593fc966c85c3e3a
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87199
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
---
 src/mainboard/starlabs/starbook/variants/cml/devicetree.cb | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/src/mainboard/starlabs/starbook/variants/cml/devicetree.cb b/src/mainboard/starlabs/starbook/variants/cml/devicetree.cb
index d502b2ad53..7a659ce214 100644
--- a/src/mainboard/starlabs/starbook/variants/cml/devicetree.cb
+++ b/src/mainboard/starlabs/starbook/variants/cml/devicetree.cb
@@ -34,6 +34,11 @@ chip soc/intel/cannonlake
 	register "PchPmSlpSusMinAssert"		= "3"				# 1s
 	register "PchPmSlpAMinAssert"		= "3"				# 98ms
 
+	# GPE configuration
+	register "gpe0_dw0"			= "PMC_GPP_B"
+	register "gpe0_dw1"			= "PMC_GPP_C"
+	register "gpe0_dw2"			= "PMC_GPP_E"
+
 	# PCIe Clock
 	register "PcieClkSrcClkReq[0]"		= "PCIE_CLK_NOTUSED"
 	register "PcieClkSrcClkReq[2]"		= "PCIE_CLK_NOTUSED"

From ec49a5556e572990f552fe98c84f55f8e4ddcc63 Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Mon, 7 Apr 2025 16:37:33 +0100
Subject: [PATCH 0661/3886] mb/starlabs/starbook/kbl: Re-add the GPE
 configuration

These were previously removed, but doing so, slowed down the
brightness keys to approx. 3 seconds.

Re-add them to make them instant.

Change-Id: I1256b57192d2f8987bb476cbcc7fd7e81f314d6d
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87200
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/starlabs/starbook/variants/kbl/devicetree.cb | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/src/mainboard/starlabs/starbook/variants/kbl/devicetree.cb b/src/mainboard/starlabs/starbook/variants/kbl/devicetree.cb
index dd53a01524..a9ac9c1554 100644
--- a/src/mainboard/starlabs/starbook/variants/kbl/devicetree.cb
+++ b/src/mainboard/starlabs/starbook/variants/kbl/devicetree.cb
@@ -32,6 +32,11 @@ chip soc/intel/skylake
 	register "PmConfigSlpSusMinAssert"	= "3"				# 1s
 	register "PmConfigSlpAMinAssert"	= "3"				# 98ms
 
+	# GPE configuration
+	register "gpe0_dw0"			= "GPP_B"
+	register "gpe0_dw1"			= "GPP_C"
+	register "gpe0_dw2"			= "GPP_E"
+
 	# Enable the correct decode ranges on the LPC bus.
 	register "lpc_ioe"			= "LPC_IOE_EC_4E_4F |
 						   LPC_IOE_KBC_60_64 |

From b465c99905c2e5b6e8f8c4cf0ffbcf2bf01e0a27 Mon Sep 17 00:00:00 2001
From: John Su <john_su@compal.corp-partner.google.com>
Date: Wed, 2 Apr 2025 14:09:26 +0800
Subject: [PATCH 0662/3886] soc/intel/alderlake: Fix incompatible
 pointer-to-integer conversion
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Call update_descriptor, but the builder detected an incompatible pointer
to integer conversion error, so upload CL to fix.

BUG=b:404126972
TEST=boot to ChromeOS

Change-Id: I1f8f19c6bb4636729ffe7be836c21db9a68d63d0
Signed-off-by: John Su <john_su@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87091
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Jayvik Desai <jayvik@google.com>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
---
 src/soc/intel/alderlake/bootblock/update_descriptor.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/soc/intel/alderlake/bootblock/update_descriptor.c b/src/soc/intel/alderlake/bootblock/update_descriptor.c
index 42c4ee21cc..ee948942d8 100644
--- a/src/soc/intel/alderlake/bootblock/update_descriptor.c
+++ b/src/soc/intel/alderlake/bootblock/update_descriptor.c
@@ -23,13 +23,13 @@
 static bool is_descriptor_writeable(uint8_t *desc)
 {
 	/* Check flash has valid signature */
-	if (read32p(desc + FLASH_SIGN_OFFSET) != FLASH_VAL_SIGN) {
+	if (read32p((uintptr_t)(desc + FLASH_SIGN_OFFSET)) != FLASH_VAL_SIGN) {
 		printk(BIOS_ERR, "Flash Descriptor is not valid\n");
 		return false;
 	}
 
 	/* Check host has write access to the Descriptor Region */
-	if (!((read32p(desc + FLMSTR1) >> FLMSTR_WR_SHIFT_V2) & BIT(0))) {
+	if (!((read32p((uintptr_t)(desc + FLMSTR1)) >> FLMSTR_WR_SHIFT_V2) & BIT(0))) {
 		printk(BIOS_ERR, "Host doesn't have write access to Descriptor Region\n");
 		return false;
 	}

From 05ec649338f73b1a5f8588028ea60515d2083e2d Mon Sep 17 00:00:00 2001
From: John Su <john_su@compal.corp-partner.google.com>
Date: Fri, 28 Mar 2025 10:21:49 +0800
Subject: [PATCH 0663/3886] mb/var/uldrenite: Configure descriptor for either
 MBVR or FIVR
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Since we need to support both MBVR (MotherBoard Voltage Regulator) and
FIVR (Fully Integrated Voltage Regulator) in this phase, the FIT
setting is initially set to FIVR. This causes MBVR boards to have two
voltage sources, potentially triggering OVP and leading to reboots
during the boot process.

The current build's main source is MBVR, so we want to use fw_config
to dynamically adjust MFIT and MBVR with the current phase devices to
ensure consistency in client devices settings.

Refer to Intel#822618 and set PMC Descriptor Record 7, bit 30
(VCCANA VR Location) accordingly. And then CONFIGURE_DESCRIPTOR is a
temporary workaround for the current phase. In the next phase, we will
choose a specific setting for implementation. If there are any concerns,
we use the board ID to restrict it.

BUG=b:404126972
TEST=boot to ChromeOS

Change-Id: I337574c8c55889ceb49b9f33625feadb48bd8890
Signed-off-by: John Su <john_su@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87033
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
---
 src/mainboard/google/brya/Kconfig             |  1 +
 .../brya/variants/uldrenite/Makefile.mk       |  1 +
 .../google/brya/variants/uldrenite/variant.c  | 29 +++++++++++++++++++
 3 files changed, 31 insertions(+)

diff --git a/src/mainboard/google/brya/Kconfig b/src/mainboard/google/brya/Kconfig
index 88869018a4..5331f0e42f 100644
--- a/src/mainboard/google/brya/Kconfig
+++ b/src/mainboard/google/brya/Kconfig
@@ -669,6 +669,7 @@ config BOARD_GOOGLE_ULDREN
 	select INTEL_GMA_HAVE_VBT
 
 config BOARD_GOOGLE_ULDRENITE
+	select ALDERLAKE_CONFIGURE_DESCRIPTOR
 	select BOARD_GOOGLE_BASEBOARD_TRULO
 	select CHROMEOS_WIFI_SAR if CHROMEOS
 	select DRIVERS_WWAN_FM350GL
diff --git a/src/mainboard/google/brya/variants/uldrenite/Makefile.mk b/src/mainboard/google/brya/variants/uldrenite/Makefile.mk
index c31fa307d0..0f152afe62 100644
--- a/src/mainboard/google/brya/variants/uldrenite/Makefile.mk
+++ b/src/mainboard/google/brya/variants/uldrenite/Makefile.mk
@@ -1,6 +1,7 @@
 ## SPDX-License-Identifier: GPL-2.0-only
 
 bootblock-y += gpio.c
+bootblock-y += variant.c
 romstage-y += gpio.c
 romstage-y += memory.c
 ramstage-y += gpio.c
diff --git a/src/mainboard/google/brya/variants/uldrenite/variant.c b/src/mainboard/google/brya/variants/uldrenite/variant.c
index 421799694a..cbaf20bac8 100644
--- a/src/mainboard/google/brya/variants/uldrenite/variant.c
+++ b/src/mainboard/google/brya/variants/uldrenite/variant.c
@@ -2,10 +2,12 @@
 
 #include <baseboard/gpio.h>
 #include <baseboard/variants.h>
+#include <boardid.h>
 #include <console/console.h>
 #include <delay.h>
 #include <fw_config.h>
 #include <sar.h>
+#include <soc/bootblock.h>
 
 const char *get_wifi_sar_cbfs_filename(void)
 {
@@ -75,3 +77,30 @@ void variant_update_soc_chip_config(struct soc_intel_alderlake_config *config)
 		printk(BIOS_INFO, "Configured External FIVR\n");
 	}
 }
+
+void variant_update_descriptor(void)
+{
+	uint32_t board_version = board_id();
+
+	/* b/404126972: Only this phase has M/B with both FIVR and MBVR. */
+	if (board_version != 1)
+		return;
+
+	/* VccanaVrLocation = "VCCANA is CPU FIVR" */
+	struct descriptor_byte fivr_bytes[] = {
+		{ 0xc33,  0x32 }
+	};
+
+	/* VccanaVrLocation = "VCCANA is Platform VR" */
+	struct descriptor_byte mbvr_bytes[] = {
+		{ 0xc33,  0x72 }
+	};
+
+	if (fw_config_probe(FW_CONFIG(EXT_VR, EXT_VR_PRESENT))) {
+		printk(BIOS_INFO, "Configuring descriptor for MBVR\n");
+		configure_descriptor(mbvr_bytes, ARRAY_SIZE(mbvr_bytes));
+	} else {
+		printk(BIOS_INFO, "Configuring descriptor for FIVR\n");
+		configure_descriptor(fivr_bytes, ARRAY_SIZE(fivr_bytes));
+	}
+}

From f2b9374a99a41d9d929fbbbae677a97832f2bc9f Mon Sep 17 00:00:00 2001
From: Felix Held <felix-coreboot@felixheld.de>
Date: Mon, 7 Apr 2025 22:48:25 +0200
Subject: [PATCH 0664/3886] doc/contributing/git_commit_messages: fix line
 length

The line length limit in the commit messages is 72 characters, not 75,
so fix the value in the documentation. The 72 characters also matches
what checkpatch checks for.

Change-Id: I2ec0fbd78fd0b054eae7bf9d6bd30580f47deb8f
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87203
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
---
 Documentation/contributing/git_commit_messages.md | 10 +++++-----
 1 file changed, 5 insertions(+), 5 deletions(-)

diff --git a/Documentation/contributing/git_commit_messages.md b/Documentation/contributing/git_commit_messages.md
index 4addf4cfe3..a007b2a20c 100644
--- a/Documentation/contributing/git_commit_messages.md
+++ b/Documentation/contributing/git_commit_messages.md
@@ -13,14 +13,14 @@ to go over everything again. There are other tutorials that cover that.
 ## Line length
 
 - The subject line should be <= 65 characters, with an absolute maximum
-  of 75 characters
-- Prose in the commit message should be <= 75 characters
-- If reflowing prose to 75 characters can reduce the length of the
+  of 72 characters
+- Prose in the commit message should be <= 72 characters
+- If reflowing prose to 72 characters can reduce the length of the
   commit message by 2 or more lines, please reflow it. Using the entire
-  75 characters on a line when reasonable is recommended, but not
+  72 characters on a line when reasonable is recommended, but not
   required.
 - Non-prose text in the body in the commit message does not need to be
-  wrapped at 75 characters. Examples: URLs, compiler output, or poetry.
+  wrapped at 72 characters. Examples: URLs, compiler output, or poetry.
 
 ## Both Subject & body
 

From 3c7f78e1e7e0229a9b114e28a33768a83d15d447 Mon Sep 17 00:00:00 2001
From: Felix Held <felix-coreboot@felixheld.de>
Date: Mon, 7 Apr 2025 22:54:15 +0200
Subject: [PATCH 0665/3886] doc/internals/devicetree_language: eSPI doesn't
 support legacy DRQ

In contracts to the ISA and LPC bus, eSPI doesn't support legacy
ISA-style DMA any more, so don't list eSPI as interface in the 'drq'
chapter.

The Intel document #841685 "Enhanced Serial Peripheral Interface (eSPI)
Interface Base Specification (for Client and Server Platforms)" revision
1.6 says this about the eSPI interface: "However, 8237 DMA and Firmware
Hub (FWH) are not supported over this interface."

Change-Id: I69d4b09688699dfc984a42671abfe3804d30ade9
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87204
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
---
 Documentation/internals/devicetree_language.md | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/Documentation/internals/devicetree_language.md b/Documentation/internals/devicetree_language.md
index 0609559ee9..d189844b4f 100644
--- a/Documentation/internals/devicetree_language.md
+++ b/Documentation/internals/devicetree_language.md
@@ -444,7 +444,7 @@ end
 * Usage: `drq 0x<register #> = <drq line>`
 
 Drq is used to configure a legacy DMA Request line register for a device
-on a legacy bus - ISA/LPC/eSPI.
+on a legacy bus - ISA/LPC.
 
 The drq configuration is only allowed inside a pnp block.
 

From b8ea245e12dcd9c39f3a9ad6e93a476fd80aabb3 Mon Sep 17 00:00:00 2001
From: Felix Held <felix-coreboot@felixheld.de>
Date: Mon, 7 Apr 2025 23:14:11 +0200
Subject: [PATCH 0666/3886] doc/internals/devicetree_language: describe I2C
 identifier

Even when the identifier of an I2C device doesn't have a '0x' prefix,
it's still interpreted as a hexadecimal number.

Change-Id: I0e5a7e39ac56e25499493a16eefa49e4f8d79337
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87205
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
---
 Documentation/internals/devicetree_language.md | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/Documentation/internals/devicetree_language.md b/Documentation/internals/devicetree_language.md
index d189844b4f..ab1b646c29 100644
--- a/Documentation/internals/devicetree_language.md
+++ b/Documentation/internals/devicetree_language.md
@@ -690,6 +690,8 @@ static.c:
 * Introduced in: Initial sconfig implementation, pre coreboot 4.0
 * Usage: `device I2c <identifier> [alias <alias ID>] <status modifier> ... end`
 
+The identifier is the device's address encoded as hexadecimal number.
+
 Example:
 
 ```text

From 010cfa28421bd52f1f16798ddf5b2116ea3f7f7a Mon Sep 17 00:00:00 2001
From: Felix Held <felix-coreboot@felixheld.de>
Date: Mon, 7 Apr 2025 23:22:34 +0200
Subject: [PATCH 0667/3886] doc/internals/devicetree_language: multiple segment
 groups supported

coreboot supports more than just one PCI segment group by having more
than one domain in the devicetree, so update the PCI device description.

Change-Id: I9911b5e43732dd32638d540fcec6ca57b34d4fbc
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87206
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
---
 Documentation/internals/devicetree_language.md | 10 +++++-----
 1 file changed, 5 insertions(+), 5 deletions(-)

diff --git a/Documentation/internals/devicetree_language.md b/Documentation/internals/devicetree_language.md
index ab1b646c29..43a22337d0 100644
--- a/Documentation/internals/devicetree_language.md
+++ b/Documentation/internals/devicetree_language.md
@@ -973,11 +973,11 @@ The pci device type defines a PCI or PCIe device on the PCI logical bus.
 Resources for all PCI devices are assigned automatically, or must be
 assigned in code if they're non-standard.
 
-Currently, only a single segment is supported, but there is work to make
-multiple different segments supported, each with a bus 0. Because the
-bus is not specified, It's assumed that all pci devices that are not
-behind a pci bridge device are on bus 0. If there are additional pci
-busses in a chip, they can be added behind their bridge device.
+Only a single segment group is supported per domain, but there can be multiple
+domains to support the case of multiple segment groups, each with a bus 0.
+Because the bus is not specified, It's assumed that all pci devices that are
+not behind a pci bridge device are on bus 0. If there are additional pci busses
+in a chip, they can be added behind their bridge device.
 
 Examples:
 

From 29cc24f0a3449446e22b1ca01f71d8d09608d5c0 Mon Sep 17 00:00:00 2001
From: Subrata Banik <subratabanik@google.com>
Date: Fri, 4 Apr 2025 15:52:25 +0530
Subject: [PATCH 0668/3886] soc/intel/cmn/cpu: Refactor USE_INTEL_FSP_MP_INIT
 enablement logic
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

The Kconfig options `USE_INTEL_FSP_MP_INIT` and
`USE_INTEL_FSP_TO_CALL_COREBOOT_PUBLISH_MP_PPI` are mutually
exclusive ways for the FSP to handle MP initialization.

This commit updates the `default` condition for
`USE_INTEL_FSP_TO_CALL_COREBOOT_PUBLISH_MP_PPI` to `y if
!USE_INTEL_FSP_MP_INIT`. This ensures that if
`USE_INTEL_FSP_MP_INIT` is enabled,
`USE_INTEL_FSP_TO_CALL_COREBOOT_PUBLISH_MP_PPI` will default
to disabled, preventing potential conflicts in MP initialization.

The explicit `depends on
!USE_INTEL_FSP_TO_CALL_COREBOOT_PUBLISH_MP_PPI`
on `USE_INTEL_FSP_MP_INIT` is no longer strictly necessary due to
this change in the default value, but it is kept for clarity and
to explicitly state the mutual exclusivity.

TEST=Able to choose USE_INTEL_FSP_MP_INIT Kconfig for
google/fatcat.

Change-Id: I9ecc7b50ed6a6b13c4ccde0a49f50a40b606a848
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87161
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
---
 src/soc/intel/common/block/cpu/Kconfig | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/src/soc/intel/common/block/cpu/Kconfig b/src/soc/intel/common/block/cpu/Kconfig
index 0184452def..e51110e1e9 100644
--- a/src/soc/intel/common/block/cpu/Kconfig
+++ b/src/soc/intel/common/block/cpu/Kconfig
@@ -124,13 +124,12 @@ config CAR_HAS_L3_PROTECTED_WAYS
 config USE_INTEL_FSP_MP_INIT
 	bool "Perform MP Initialization by FSP"
 	default n
-	depends on !USE_INTEL_FSP_TO_CALL_COREBOOT_PUBLISH_MP_PPI
 	help
 	  This option allows FSP to perform multiprocessor initialization.
 
 config USE_INTEL_FSP_TO_CALL_COREBOOT_PUBLISH_MP_PPI
 	bool "Perform MP Initialization by FSP using coreboot MP PPI service"
-	default y
+	default y if !USE_INTEL_FSP_MP_INIT
 	depends on MP_SERVICES_PPI
 	help
 	  This option allows FSP to make use of MP services PPI published by

From 7887417b4e74c6d10613e25dfeec9234b31dfa6f Mon Sep 17 00:00:00 2001
From: Subrata Banik <subratabanik@google.com>
Date: Fri, 4 Apr 2025 15:20:26 +0530
Subject: [PATCH 0669/3886] mb/google/fatcat/variants/fatcat: Refactor X1 PCIe
 power enable GPIO

The system was failing to boot to the OS when the SD FW config was
set to NONE. This was because the X1 PCIe slot power enable (GPP_A08)
was being configured in `pre_mem_x1slot_pads` only if the SD FW config
was not NONE.

This commit moves the configuration of GPP_A08 to the
`romstage_gpio_table` and sets it to an initial low state. This ensures
that the X1 PCIe slot power is correctly initialized early in the boot
process, regardless of the SD FW config.

The `pre_mem_x1slot_pads` array and its conditional configuration in
`fw_config_configure_pre_mem_gpio` have been removed as they are no
longer needed.

TEST=Able to boot google/fatcat w/ CBI 0x5c9014 (i.e. SD_NONE)

Change-Id: I0f2a2540de30294c30c4f5182dab326a54b4583e
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87154
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Reviewed-by: Pranava Y N <pranavayn@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/google/fatcat/variants/fatcat/fw_config.c | 7 -------
 src/mainboard/google/fatcat/variants/fatcat/gpio.c      | 2 ++
 2 files changed, 2 insertions(+), 7 deletions(-)

diff --git a/src/mainboard/google/fatcat/variants/fatcat/fw_config.c b/src/mainboard/google/fatcat/variants/fatcat/fw_config.c
index afd8a63084..b02878b1b6 100644
--- a/src/mainboard/google/fatcat/variants/fatcat/fw_config.c
+++ b/src/mainboard/google/fatcat/variants/fatcat/fw_config.c
@@ -165,10 +165,6 @@ static const struct pad_config audio_disable_pads[] = {
 	PAD_NC(GPP_D17, NONE),
 };
 
-static const struct pad_config pre_mem_x1slot_pads[] = {
-	/* GPP_A08:     X1_PCIE_SLOT_PWR_EN */
-	PAD_CFG_GPO(GPP_A08, 0, PLTRST),
-};
 static const struct pad_config x1slot_pads[] = {
 	/* GPP_A08:     X1_PCIE_SLOT_PWR_EN */
 	PAD_CFG_GPO(GPP_A08, 1, PLTRST),
@@ -566,9 +562,6 @@ void fw_config_configure_pre_mem_gpio(void)
 		GPIO_CONFIGURE_PADS(pre_mem_gen5_ssd_pwr_pads);
 	}
 
-	if (!fw_config_probe(FW_CONFIG(SD, SD_NONE)))
-		GPIO_CONFIGURE_PADS(pre_mem_x1slot_pads);
-
 	/*
 	 * NOTE: We place WWAN sequence 2 here. According to the WWAN FIBOCOM
 	 * FM350-GL datasheet, the minimum time requirement (Tpr: time between 3.3V
diff --git a/src/mainboard/google/fatcat/variants/fatcat/gpio.c b/src/mainboard/google/fatcat/variants/fatcat/gpio.c
index b1e77ec028..6b71c65c5c 100644
--- a/src/mainboard/google/fatcat/variants/fatcat/gpio.c
+++ b/src/mainboard/google/fatcat/variants/fatcat/gpio.c
@@ -390,6 +390,8 @@ static const struct pad_config early_gpio_table[] = {
 
 /* Pad configuration in romstage */
 static const struct pad_config romstage_gpio_table[] = {
+	/* GPP_A08:     X1_PCIE_SLOT_PWR_EN */
+	PAD_CFG_GPO(GPP_A08, 0, PLTRST),
 	/* GPP_C00:     GPP_C0_SMBCLK */
 	PAD_CFG_NF(GPP_C00, NONE, DEEP, NF1),
 	/* GPP_C01:     GPP_C1_SMBDATA */

From ee9b0fa199a25838e08a0c7ce351af3e88bda9b0 Mon Sep 17 00:00:00 2001
From: Subrata Banik <subratabanik@google.com>
Date: Sat, 5 Apr 2025 08:08:52 +0000
Subject: [PATCH 0670/3886] cpu/x86: Conditionally invalidate caches based on
 self-snooping support
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

The code currently unconditionally flushes or invalidates the entire
cache (using `clflush_region` or `wbinvd`) after loading the SIPI vector
for APs and after loading SMM handlers.

This commit modifies this behavior to only perform these cache
operations if the CPU does *not* support self-snooping.

Self-snooping CPUs can maintain cache coherency within the core/
complex more efficiently. CPU with self-snoop enabled does not
necessarily need to perform wbinvd to ensure data written to the
cache is reflected in main memory. Self-snooping CPUs employ a
write-back caching policy, combined with a cache coherence protocol,
to manage data writes and ensure consistency between cache and main
memory.

When the BSP writes the SIPI vector or SMM handlers to memory, other
units within the same CPU that might be caching these regions should
be aware of the updates through the self-snooping mechanism. A full
cache flush or invalidate to ensure cache contains reaches to main
memory might be unnecessary and could negatively impact performance.

By conditionally performing these cache operations based on
`self_snooping_supported()`, we can optimize the boot process for CPUs
that have advanced cache coherency features while maintaining correct
behavior on older or simpler CPUs.

TEST=Boot google/rex, brox and fatcat with this patch. Able to reduce
boot time by ~19-25ms.

Change-Id: If32439752d0ceaa03b1d81873ea0bc562092e9d5
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87182
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/cpu/x86/cache/cache.c | 10 ++++++----
 src/cpu/x86/mp_init.c     | 20 ++++++++++++--------
 2 files changed, 18 insertions(+), 12 deletions(-)

diff --git a/src/cpu/x86/cache/cache.c b/src/cpu/x86/cache/cache.c
index 11524e65db..48718d2ae4 100644
--- a/src/cpu/x86/cache/cache.c
+++ b/src/cpu/x86/cache/cache.c
@@ -49,8 +49,10 @@ void arch_segment_loaded(uintptr_t start, size_t size, int flags)
 	if (!cbmem_online())
 		return;
 
-	if (clflush_supported())
-		clflush_region(start, size);
-	else
-		printk(BIOS_DEBUG, "Not flushing cache to RAM, CLFLUSH not supported\n");
+	if (!self_snooping_supported()) {
+		if (clflush_supported())
+			clflush_region(start, size);
+		else
+			printk(BIOS_DEBUG, "Not flushing cache to RAM, CLFLUSH not supported\n");
+	}
 }
diff --git a/src/cpu/x86/mp_init.c b/src/cpu/x86/mp_init.c
index 574f28e379..f223ccc6e5 100644
--- a/src/cpu/x86/mp_init.c
+++ b/src/cpu/x86/mp_init.c
@@ -365,12 +365,14 @@ static atomic_t *load_sipi_vector(struct mp_params *mp_params)
 	ap_count = &sp->ap_count;
 	atomic_set(ap_count, 0);
 
-	/* Make sure SIPI data hits RAM so the APs that come up will see the
-	   startup code even if the caches are disabled. */
-	if (clflush_supported())
-		clflush_region((uintptr_t)mod_loc, module_size);
-	else
-		wbinvd();
+	if (!self_snooping_supported()) {
+		/* Make sure SIPI data hits RAM so the APs that come up will see the
+		   startup code even if the caches are disabled. */
+		if (clflush_supported())
+			clflush_region((uintptr_t)mod_loc, module_size);
+		else
+			wbinvd();
+	}
 
 	return ap_count;
 }
@@ -826,8 +828,10 @@ static void load_smm_handlers(void)
 		smm_disable();
 	}
 
-	/* Ensure the SMM handlers hit DRAM before performing first SMI. */
-	wbinvd();
+	if (!self_snooping_supported()) {
+		/* Ensure the SMM handlers hit DRAM before performing first SMI. */
+		wbinvd();
+	}
 
 	/*
 	 * Indicate that the SMM handlers have been loaded and MP

From 1d6ee80e37c8923adb5309ab4d82a4d99f6e891c Mon Sep 17 00:00:00 2001
From: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Date: Mon, 7 Apr 2025 17:29:07 +0800
Subject: [PATCH 0671/3886] mb/google/nissa/var/dirks: Add ACPI DmaProperty for
 Ethernet device

Add ACPI DmaProperty for Ethernet device to support untrusted PCIe
port verification.

BUG=b:398872682
TEST=cat /sys/devices/pci0000:00/0000:00:1c.0/0000:01:00.0/untrusted
     returned 1

Change-Id: I24d5f637f1349aace0fba0640c8e72ffc3401de9
Signed-off-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87197
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Derek Huang <derekhuang@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com>
---
 src/mainboard/google/brya/variants/dirks/overridetree.cb | 1 +
 1 file changed, 1 insertion(+)

diff --git a/src/mainboard/google/brya/variants/dirks/overridetree.cb b/src/mainboard/google/brya/variants/dirks/overridetree.cb
index 94c2457b65..27de59cc50 100644
--- a/src/mainboard/google/brya/variants/dirks/overridetree.cb
+++ b/src/mainboard/google/brya/variants/dirks/overridetree.cb
@@ -233,6 +233,7 @@ chip soc/intel/alderlake
 				register "customized_leds" = "0x05af"
 				register "wake" = "GPE0_DW2_14"	# GPP_F14
 				register "device_index" = "0"
+				register "add_acpi_dma_property" = "true"
 				device pci 00.0 on end
 			end
 		end # RTL8111H Ethernet NIC

From d701a218c2d4f126d2e29f092225cd0b5ff3df76 Mon Sep 17 00:00:00 2001
From: Daniel Peng <Daniel_Peng@pegatron.corp-partner.google.com>
Date: Mon, 7 Apr 2025 17:12:39 +0800
Subject: [PATCH 0672/3886] mb/google/nissa/var/guren: Add touch screen
 ILIT2901 support

New Touchscreen function for Guren360 project.
Touchscreen panel of MUTTO A153728S1Y(11')
/K&D KD116N37-30TE-A002(11')/MUTTO B153797S1Y(12') are the
same IC controller for ILITEK device, and set TOUCHSCREEN_ILIT2901
to value "2".

BUG=b:406168542
BRANCH=firmware-nissa-15217.B
TEST=1. emerge-nissa coreboot chromeos-bootimage
     2. Confirm command evtest and touchscreen function is workable.

Change-Id: I3435a8852b1fdb897d5f89c580b5f9bfca03dd8e
Signed-off-by: Daniel Peng <Daniel_Peng@pegatron.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87196
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Daniel Peng <daniel_peng@pegatron.corp-partner.google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
---
 .../brya/variants/guren/overridetree.cb       | 20 +++++++++++++++++++
 1 file changed, 20 insertions(+)

diff --git a/src/mainboard/google/brya/variants/guren/overridetree.cb b/src/mainboard/google/brya/variants/guren/overridetree.cb
index 8b1adb14f9..0e106895be 100644
--- a/src/mainboard/google/brya/variants/guren/overridetree.cb
+++ b/src/mainboard/google/brya/variants/guren/overridetree.cb
@@ -28,6 +28,7 @@ fw_config
 	field TOUCHSCREEN_SOURCE 32 34
 		option TOUCHSCREEN_UNPROVISIONED	0
 		option TOUCHSCREEN_ELAN0001		1
+		option TOUCHSCREEN_ILIT2901		2
 	end
 end
 
@@ -349,6 +350,25 @@ chip soc/intel/alderlake
 				end
 			end
 
+			chip drivers/i2c/hid
+				register "generic.hid" = ""ILIT2901""
+				register "generic.desc" = ""ILI Touchscreen""
+				register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_C7_IRQ)"
+				register "generic.detect" = "1"
+				register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C1)"
+				register "generic.reset_delay_ms" = "10"
+				register "generic.reset_off_delay_ms" = "4"
+				register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C0)"
+				register "generic.enable_delay_ms" = "12"
+				register "generic.stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C6)"
+				register "generic.stop_delay_ms" = "105"
+				register "generic.stop_off_delay_ms" = "5"
+				register "generic.has_power_resource" = "1"
+				register "hid_desc_reg_offset" = "0x01"
+				device i2c 41 on
+					probe TOUCHSCREEN_SOURCE TOUCHSCREEN_ILIT2901
+				end
+			end
 		end #I2C1
 		device ref i2c2 on
 			chip drivers/i2c/sx9324

From c8a7422de72ab3572dac33dff35a839533fa8d57 Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Tue, 8 Apr 2025 17:00:54 +0100
Subject: [PATCH 0673/3886] mb/starlabs/starbook/tgl: Change SSD Enable GPIO to
 PLTRST

Change the SSD Enable GPIO to PLTRST, as having it configure to DEEP,
renders the SSD inaccessible on S3 exit as it conflicts with the RTD3
driver.

Change-Id: If4a406af13005ba4532091d0c5c75f5198e04ff4
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87213
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/starlabs/starbook/variants/tgl/gpio.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/mainboard/starlabs/starbook/variants/tgl/gpio.c b/src/mainboard/starlabs/starbook/variants/tgl/gpio.c
index b6f152681b..2794ea4c55 100644
--- a/src/mainboard/starlabs/starbook/variants/tgl/gpio.c
+++ b/src/mainboard/starlabs/starbook/variants/tgl/gpio.c
@@ -42,7 +42,7 @@ const struct pad_config gpio_table[] = {
 	/* SSD */
 	PAD_NC(GPP_D8, NONE),						/* Clock Request 3 */
 	PAD_CFG_GPO(GPP_A11, 1, PLTRST),				/* Reset */
-	PAD_CFG_GPO(GPP_D16, 1, DEEP),					/* Enable */
+	PAD_CFG_GPO(GPP_D16, 1, PLTRST),				/* Enable */
 
 	/* SATA */
 	PAD_CFG_NF(GPP_A12, UP_20K, DEEP, NF1),				/* PEDET */

From 8c10359377330923d6d505d29780461a2d623d77 Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Wed, 26 Feb 2025 14:05:56 +0000
Subject: [PATCH 0674/3886] soc/intel/meteorlake: Add missing minimum D-state
 for SMBUS
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Fixes:
Unknown min d_state for PCI: 00:1f.4

Change-Id: I73f84c09bece297194813202f17666741ad33d3a
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86605
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
---
 src/soc/intel/meteorlake/acpi.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/src/soc/intel/meteorlake/acpi.c b/src/soc/intel/meteorlake/acpi.c
index f32ba56be7..22dbce4079 100644
--- a/src/soc/intel/meteorlake/acpi.c
+++ b/src/soc/intel/meteorlake/acpi.c
@@ -211,6 +211,7 @@ static struct min_sleep_state min_pci_sleep_states[] = {
 	{ PCI_DEVFN_ESPI,	ACPI_DEVICE_SLEEP_D0 },
 	{ PCH_DEVFN_PMC,	ACPI_DEVICE_SLEEP_D0 },
 	{ PCI_DEVFN_HDA,	ACPI_DEVICE_SLEEP_D0 },
+	{ PCI_DEVFN_SMBUS,	ACPI_DEVICE_SLEEP_D0 },
 	{ PCI_DEVFN_SPI,	ACPI_DEVICE_SLEEP_D3 },
 	{ PCI_DEVFN_GBE,	ACPI_DEVICE_SLEEP_D3 },
 };

From 28fafc0f23e7db846798737a354f847ec4dea0a7 Mon Sep 17 00:00:00 2001
From: Maximilian Brune <maximilian.brune@9elements.com>
Date: Sat, 15 Mar 2025 16:12:45 +0100
Subject: [PATCH 0675/3886] soc/amd/glinda/psp_verstage/Makefile.mk: Fix
 incorrect syntax

Must have been accidentally happened when copying phoenix to glinda.

Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: I78996cd35085c7649c4952d9b121957c8cedd84b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86865
Reviewed-by: Andy Ebrahiem <ahmet.ebrahiem@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
---
 src/soc/amd/glinda/psp_verstage/Makefile.mk | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/soc/amd/glinda/psp_verstage/Makefile.mk b/src/soc/amd/glinda/psp_verstage/Makefile.mk
index a11f053300..add7e07361 100644
--- a/src/soc/amd/glinda/psp_verstage/Makefile.mk
+++ b/src/soc/amd/glinda/psp_verstage/Makefile.mk
@@ -1,6 +1,6 @@
 # SPDX-License-Identifier: GPL-2.0-only
 
-ifeq $($(CONFIG_VBOOT_STARTS_BEFORE_BOOTBLOCK),y)
+ifeq ($(CONFIG_VBOOT_STARTS_BEFORE_BOOTBLOCK),y)
 
 subdirs-y += ../../common/psp_verstage
 

From 7f6e43851eb8efda31818bf313ece47e1436f483 Mon Sep 17 00:00:00 2001
From: Subrata Banik <subratabanik@google.com>
Date: Mon, 7 Apr 2025 17:43:08 +0530
Subject: [PATCH 0676/3886] mb/google/fatcat: Perform early post-memory GPIO
 configuration

This commit restructures the GPIO configuration for google/fatcat
devices as below.

- Phase 1: GPIO configuration at pre-memory phase. This phase
  configures essential GPIOs like WWAN and storage power sequencing,
  This aligns with the initial power-up requirements of
  these critical components.

- Phase 2: This phase handles GPIO configurations for various
  peripherals like storage type, audio codec, WiFi, cellular interface
  (post initial power sequence), SD card slot, touchpad, touchscreen,
  ISH, PEG/x4 slot wake disable, and fingerprint enable/disable based
  early in post-memory phase (before MPInit).

This phased approach:

- Improves power sequencing by ordering GPIO configuration for proper
  IP power enablement.
- Optimizes boot time by performing more GPIO configuration before
  MPInit and FSP-S, allowing earlier IP stabilization and potentially
  saving ~20ms during device setup and PCIe scan.

`baseboard_devtree_update` remains in `mainboard_init` for baseboard-
specific device tree updates.

TEST=Boot time improved by ~20ms on google/fatcat.

Before:
  70:device setup done      1,339,599 (95,023)

After:
  70:device setup done      1,319,613 (72,381)

Change-Id: I9c2e58ae012cad06f8e498c75745efaa9bad4a25
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87191
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jayvik Desai <jayvik@google.com>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
---
 src/mainboard/google/fatcat/mainboard.c | 10 +++++++++-
 1 file changed, 9 insertions(+), 1 deletion(-)

diff --git a/src/mainboard/google/fatcat/mainboard.c b/src/mainboard/google/fatcat/mainboard.c
index e14c5ace79..5bd9892480 100644
--- a/src/mainboard/google/fatcat/mainboard.c
+++ b/src/mainboard/google/fatcat/mainboard.c
@@ -4,6 +4,7 @@
 #include <acpi/acpigen.h>
 #include <baseboard/gpio.h>
 #include <baseboard/variants.h>
+#include <bootstate.h>
 #include <device/device.h>
 #include <ec/ec.h>
 #include <soc/ramstage.h>
@@ -26,6 +27,12 @@ void __weak variant_update_soc_chip_config(struct soc_intel_pantherlake_config *
 }
 
 static void mainboard_init(void *chip_info)
+{
+	baseboard_devtree_update();
+}
+
+/* Must happen before MPinit */
+static void mainboard_early(void *unused)
 {
 	struct pad_config *padbased_table;
 	const struct pad_config *base_pads;
@@ -37,9 +44,10 @@ static void mainboard_init(void *chip_info)
 	fw_config_gpio_padbased_override(padbased_table);
 	gpio_configure_pads_with_padbased(padbased_table);
 	free(padbased_table);
-	baseboard_devtree_update();
 }
 
+BOOT_STATE_INIT_ENTRY(BS_PRE_DEVICE, BS_ON_EXIT, mainboard_early, NULL);
+
 void __weak baseboard_devtree_update(void)
 {
 	/* Override dev tree settings per baseboard */

From 479a271cf3215b3e89e8182bcccbbdd1a291e83c Mon Sep 17 00:00:00 2001
From: Subrata Banik <subratabanik@google.com>
Date: Tue, 8 Apr 2025 10:54:29 +0530
Subject: [PATCH 0677/3886] mb/google/fatcat: Introduce variant-specific barrel
 jack presence check

This commit introduces a weak function
`variant_is_barrel_charger_present()` to allow individual Fatcat
variants to specify if they support power-on via a barrel jack.

The default implementation of this function returns `false`,
reflecting the fact that most Chromebook devices within the Fatcat
family primarily use USB-C for power.

The `baseboard_devtree_update()` function is updated to use this
variant-specific check instead of directly calling
`google_chromeec_is_barrel_charger_present()` and checking the board
model. This allows for more flexibility in handling barrel jack
presence across different Fatcat variants.

This change enables specific variants that do support barrel jack
power to override the weak function and return `true`, allowing the
system to behave accordingly (e.g., skipping power optimization when
booting with a barrel charger).

TEST=Able to build and boot google/fatcat.

Change-Id: I613417be5a59790b8a5e6055957a2f518f4c42df
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87183
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Pranava Y N <pranavayn@google.com>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Jayvik Desai <jayvik@google.com>
---
 .../fatcat/variants/baseboard/fatcat/ramstage.c    | 14 +++++++++++++-
 .../baseboard/include/baseboard/variants.h         |  1 +
 2 files changed, 14 insertions(+), 1 deletion(-)

diff --git a/src/mainboard/google/fatcat/variants/baseboard/fatcat/ramstage.c b/src/mainboard/google/fatcat/variants/baseboard/fatcat/ramstage.c
index 21f8ccda98..69d0d67cd0 100644
--- a/src/mainboard/google/fatcat/variants/baseboard/fatcat/ramstage.c
+++ b/src/mainboard/google/fatcat/variants/baseboard/fatcat/ramstage.c
@@ -50,10 +50,22 @@ const struct cpu_tdp_power_limits power_optimized_limits[] = {
 	},
 };
 
+/*
+ * Placeholder to check if variant has support for barrel jack for powering
+ * on the device.
+ *
+ * Most of the chromebook device is powering on with USB-C hence, unless overridden
+ * by some variant, assume barrel jack not present.
+ */
+__weak bool variant_is_barrel_charger_present(void)
+{
+	return false;
+}
+
 void baseboard_devtree_update(void)
 {
 	/* Don't optimize the power limit if booting with barrel attached */
-	if (CONFIG(BOARD_GOOGLE_MODEL_FATCAT) && google_chromeec_is_barrel_charger_present())
+	if (variant_is_barrel_charger_present())
 		return;
 
 	if (!google_chromeec_is_battery_present())
diff --git a/src/mainboard/google/fatcat/variants/baseboard/include/baseboard/variants.h b/src/mainboard/google/fatcat/variants/baseboard/include/baseboard/variants.h
index c080dd3572..ad26ab8a67 100644
--- a/src/mainboard/google/fatcat/variants/baseboard/include/baseboard/variants.h
+++ b/src/mainboard/google/fatcat/variants/baseboard/include/baseboard/variants.h
@@ -26,6 +26,7 @@ int variant_memory_sku(void);
 bool variant_is_half_populated(void);
 void variant_update_soc_memory_init_params(FSPM_UPD *memupd);
 void variant_update_soc_chip_config(struct soc_intel_pantherlake_config *config);
+bool variant_is_barrel_charger_present(void);
 
 enum s0ix_entry {
 	S0IX_EXIT,

From bde1ac579420de4869340685d7d7e1c122926508 Mon Sep 17 00:00:00 2001
From: Subrata Banik <subratabanik@google.com>
Date: Tue, 8 Apr 2025 11:42:47 +0530
Subject: [PATCH 0678/3886] mb/google/fatcat/var/fatcat: Implement barrel jack
 presence check

Uses fw_config to check if barrel jack PSU is configured. If
`PSU_BJ` is selected, checks hardware presence via
`google_chromeec_is_barrel_charger_present()`.

Allows 'fatcat' to adapt based on configured power source.

Includes:
- Adds `variant.c` to ramstage build in `Makefile.mk`.
- Adds `PSU` field (`PSU_USBC`: 0, `PSU_BJ`: 1) to `overridetree.cb`.
- Includes `ec.h` in `variant.c`.

TEST=Boot time savings ~62ms on google/fatcat with PSU=0 (USB-C).

Change-Id: I68507034cfbf4caa8e5c2ac9c7bebf758a5a5439
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87207
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: YH Lin <yueherngl@google.com>
Reviewed-by: Jayvik Desai <jayvik@google.com>
Reviewed-by: Pranava Y N <pranavayn@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
---
 src/mainboard/google/fatcat/variants/fatcat/Makefile.mk  | 1 +
 .../google/fatcat/variants/fatcat/overridetree.cb        | 4 ++++
 src/mainboard/google/fatcat/variants/fatcat/variant.c    | 9 +++++++++
 3 files changed, 14 insertions(+)

diff --git a/src/mainboard/google/fatcat/variants/fatcat/Makefile.mk b/src/mainboard/google/fatcat/variants/fatcat/Makefile.mk
index b9f1fd15dd..3fdd4642c0 100644
--- a/src/mainboard/google/fatcat/variants/fatcat/Makefile.mk
+++ b/src/mainboard/google/fatcat/variants/fatcat/Makefile.mk
@@ -6,4 +6,5 @@ romstage-y += memory.c
 romstage-$(CONFIG_FW_CONFIG) += fw_config.c
 ramstage-y += gpio.c
 romstage-$(CONFIG_FW_CONFIG) += variant.c
+ramstage-$(CONFIG_FW_CONFIG) += variant.c
 ramstage-$(CONFIG_FW_CONFIG) += fw_config.c
diff --git a/src/mainboard/google/fatcat/variants/fatcat/overridetree.cb b/src/mainboard/google/fatcat/variants/fatcat/overridetree.cb
index c6a63c3fcb..e154ffc46c 100644
--- a/src/mainboard/google/fatcat/variants/fatcat/overridetree.cb
+++ b/src/mainboard/google/fatcat/variants/fatcat/overridetree.cb
@@ -67,6 +67,10 @@ fw_config
 		option ISH_DISABLE		0
 		option ISH_ENABLE		1
 	end
+	field PSU 25
+		option PSU_USBC			0
+		option PSU_BJ			1
+	end
 end
 
 chip soc/intel/pantherlake
diff --git a/src/mainboard/google/fatcat/variants/fatcat/variant.c b/src/mainboard/google/fatcat/variants/fatcat/variant.c
index 5ba7683640..3e0ee54505 100644
--- a/src/mainboard/google/fatcat/variants/fatcat/variant.c
+++ b/src/mainboard/google/fatcat/variants/fatcat/variant.c
@@ -1,6 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
 #include <baseboard/variants.h>
+#include <ec/google/chromeec/ec.h>
 #include <fsp/api.h>
 #include <fw_config.h>
 #include <sar.h>
@@ -84,3 +85,11 @@ void variant_update_soc_memory_init_params(FSPM_UPD *memupd)
 		m_cfg->PchHdaSdiEnable[1] = false;
 	}
 }
+
+bool variant_is_barrel_charger_present(void)
+{
+	if (fw_config_probe(FW_CONFIG(PSU, PSU_BJ)))
+		return google_chromeec_is_barrel_charger_present();
+	else
+		return false;
+}

From 9fb57d969969de976b832962b59b66a9182334a8 Mon Sep 17 00:00:00 2001
From: Subrata Banik <subratabanik@google.com>
Date: Wed, 9 Apr 2025 09:48:39 +0530
Subject: [PATCH 0679/3886] mb/google/fatcat: Enable
 FSP_UGOP_EARLY_SIGN_OF_LIFE

This patch moves eSOL enablement from the SoC level to the mainboard level. This gives the mainboard the option to not use eSOL if it's not supported.

The FSP_UGOP_EARLY_SIGN_OF_LIFE Kconfig option is now enabled for the Fatcat and Felino boards.

This option was previously enabled at the SoC level for Pantherlake,
but is now being enabled specifically for these mainboards.

BUG=b:400550435
TEST=Build the Fatcat and Felino targets. Verify that the eSOL works
fine.

Change-Id: Ie0cf5b00f75071640475d61420824cb2b89b4103
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87236
Reviewed-by: Pranava Y N <pranavayn@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Jayvik Desai <jayvik@google.com>
---
 src/mainboard/google/fatcat/Kconfig | 2 ++
 src/soc/intel/pantherlake/Kconfig   | 1 -
 2 files changed, 2 insertions(+), 1 deletion(-)

diff --git a/src/mainboard/google/fatcat/Kconfig b/src/mainboard/google/fatcat/Kconfig
index 2679b143d5..08a5eba912 100644
--- a/src/mainboard/google/fatcat/Kconfig
+++ b/src/mainboard/google/fatcat/Kconfig
@@ -62,6 +62,7 @@ config BOARD_GOOGLE_MODEL_FATCAT
 	select DRIVERS_GENERIC_BAYHUB_LV2
 	select DRIVERS_GENERIC_MAX98357A
 	select DRIVERS_INTEL_TOUCH
+	select FSP_UGOP_EARLY_SIGN_OF_LIFE
 
 config BOARD_GOOGLE_FATCAT
 	select BOARD_GOOGLE_MODEL_FATCAT
@@ -81,6 +82,7 @@ config BOARD_GOOGLE_FATCATITE
 
 config BOARD_GOOGLE_FELINO
 	select BOARD_GOOGLE_BASEBOARD_FATCAT
+	select FSP_UGOP_EARLY_SIGN_OF_LIFE
 	select HAVE_SLP_S0_GATE
 	select MAINBOARD_HAS_GOOGLE_STRAUSS_KEYBOARD
 
diff --git a/src/soc/intel/pantherlake/Kconfig b/src/soc/intel/pantherlake/Kconfig
index a884631e53..36417db7c3 100644
--- a/src/soc/intel/pantherlake/Kconfig
+++ b/src/soc/intel/pantherlake/Kconfig
@@ -17,7 +17,6 @@ config SOC_INTEL_PANTHERLAKE_BASE
 	select FAST_SPI_SUPPORTS_EXT_BIOS_WINDOW
 	select FSP_COMPRESS_FSP_S_LZ4
 	select FSP_M_XIP
-	select FSP_UGOP_EARLY_SIGN_OF_LIFE
 	select FSP_USES_CB_DEBUG_EVENT_HANDLER
 	select FSPS_HAS_ARCH_UPD
 	select GENERIC_GPIO_LIB

From a7eb390796ef4ba7baaffca741664b816de12256 Mon Sep 17 00:00:00 2001
From: Arthur Heymans <arthur@aheymans.xyz>
Date: Fri, 22 Apr 2022 02:01:42 +0200
Subject: [PATCH 0680/3886] mb/*/*/*.fmd: Start flash at 0

FMAP should not contain information about the memory map.

Done with the following command:
"find -name \*.fmd -exec sed -i 's/\(FLASH\).* \(.*\) /\1 \2 /' {} \;"

for AMD:
All addresses that amdfwtool expects as command line parameter have the
ADDR_REL_BIOS (flash address) address_mode setting. One exception is
the *_FW_A_POSITION and *_FW_B_POSITION addresses. But amdfwtool checks
if memory or flash addresses are passed and converts accordingly. So
changing the address from memory -> flash doesn't matter for the
resulting binary.
Since commit 41a162b7a8e4 ("soc/amd/phoenix/Makefile.inc: Pass APOB_NV
address as offset") and therefore since phoenix SOC, APOB_NV is passed
as flash offset. But before that the memory ABL always assumed a MMIO
address (no matter the address_mode) so we need to add a little quirk
for that.

tested: boot glinda based mainboard and also check that memory training
is still cached successfully in APOB_NV.

Change-Id: Iac86ef9be6b14817a65bf3a7ccb624d205ca3f99
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63771
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
---
 Makefile.mk                                   |  5 +--
 src/arch/x86/walkcbfs.S                       |  2 +-
 src/mainboard/amd/bilby/board.fmd             |  2 +-
 src/mainboard/amd/birman/board_glinda.fmd     |  2 +-
 src/mainboard/amd/birman/board_phoenix.fmd    |  2 +-
 src/mainboard/amd/birman/chromeos_glinda.fmd  |  2 +-
 src/mainboard/amd/birman/chromeos_phoenix.fmd |  2 +-
 .../amd/birman_plus/board_phoenix.fmd         |  2 +-
 .../amd/birman_plus/chromeos_glinda.fmd       |  2 +-
 .../amd/birman_plus/chromeos_phoenix.fmd      |  2 +-
 src/mainboard/amd/chausie/board.fmd           |  2 +-
 src/mainboard/amd/chausie/chromeos.fmd        |  2 +-
 src/mainboard/amd/crater/board_renoir.fmd     |  2 +-
 src/mainboard/amd/crater/chromeos_renoir.fmd  |  2 +-
 src/mainboard/amd/majolica/board.fmd          |  2 +-
 src/mainboard/amd/majolica/chromeos.fmd       |  2 +-
 .../amd/mandolin/variants/cereme/board.fmd    |  2 +-
 .../amd/mandolin/variants/mandolin/board.fmd  |  2 +-
 src/mainboard/amd/mayan/board.fmd             |  2 +-
 src/mainboard/amd/mayan/chromeos.fmd          |  2 +-
 src/mainboard/arm/rdn2/flash.fmd              |  2 +-
 src/mainboard/bytedance/bd_egs/board.fmd      |  2 +-
 src/mainboard/cavium/cn8100_sff_evb/board.fmd |  2 +-
 .../emulation/qemu-i440fx/vboot-rwa-8M.fmd    |  2 +-
 .../emulation/qemu-q35/vboot-rwa-8M.fmd       |  2 +-
 .../emulation/qemu-q35/vboot-rwab-8M.fmd      |  2 +-
 src/mainboard/emulation/qemu-sbsa/flash.fmd   |  2 +-
 src/mainboard/facebook/fbg1701/vboot-rw.fmd   |  2 +-
 src/mainboard/framework/azalea/coreboot.fmd   |  2 +-
 src/mainboard/google/asurada/chromeos.fmd     |  2 +-
 src/mainboard/google/auron/chromeos.fmd       |  2 +-
 src/mainboard/google/beltino/chromeos.fmd     |  2 +-
 src/mainboard/google/butterfly/chromeos.fmd   |  2 +-
 src/mainboard/google/cherry/chromeos.fmd      |  2 +-
 src/mainboard/google/corsola/chromeos.fmd     |  2 +-
 src/mainboard/google/cyan/chromeos.fmd        |  2 +-
 src/mainboard/google/daisy/chromeos.fmd       |  2 +-
 .../google/dedede/chromeos-dedede-16MiB.fmd   |  2 +-
 .../google/dedede/chromeos-dedede-32MiB.fmd   |  2 +-
 src/mainboard/google/drallion/chromeos.fmd    |  2 +-
 src/mainboard/google/drallion/default.fmd     |  2 +-
 src/mainboard/google/eve/chromeos.fmd         |  2 +-
 src/mainboard/google/fizz/chromeos.fmd        |  2 +-
 src/mainboard/google/foster/chromeos.fmd      |  2 +-
 src/mainboard/google/gale/chromeos.fmd        |  2 +-
 src/mainboard/google/geralt/chromeos.fmd      |  2 +-
 src/mainboard/google/glados/chromeos.fmd      |  2 +-
 src/mainboard/google/gru/chromeos.fmd         |  2 +-
 src/mainboard/google/guybrush/chromeos.fmd    |  2 +-
 src/mainboard/google/hatch/chromeos-16MiB.fmd |  2 +-
 src/mainboard/google/hatch/chromeos-32MiB.fmd |  2 +-
 src/mainboard/google/herobrine/chromeos.fmd   |  4 +--
 src/mainboard/google/jecht/chromeos.fmd       |  2 +-
 .../kahlee/variants/baseboard/chromeos.fmd    |  2 +-
 src/mainboard/google/kukui/chromeos.fmd       |  2 +-
 src/mainboard/google/link/chromeos.fmd        |  2 +-
 src/mainboard/google/mistral/chromeos.fmd     |  2 +-
 src/mainboard/google/myst/chromeos.fmd        |  2 +-
 src/mainboard/google/nyan/chromeos.fmd        |  2 +-
 src/mainboard/google/nyan_big/chromeos.fmd    |  2 +-
 src/mainboard/google/nyan_blaze/chromeos.fmd  |  2 +-
 src/mainboard/google/oak/chromeos.fmd         |  2 +-
 src/mainboard/google/parrot/chromeos.fmd      |  2 +-
 src/mainboard/google/peach_pit/chromeos.fmd   |  2 +-
 src/mainboard/google/poppy/chromeos.fmd       |  2 +-
 src/mainboard/google/puff/chromeos-16MiB.fmd  |  2 +-
 src/mainboard/google/puff/chromeos-32MiB.fmd  |  2 +-
 src/mainboard/google/rambi/chromeos.fmd       |  2 +-
 src/mainboard/google/rauru/chromeos.fmd       |  2 +-
 src/mainboard/google/sarien/chromeos.fmd      |  2 +-
 src/mainboard/google/sarien/default.fmd       |  2 +-
 src/mainboard/google/skyrim/chromeos.fmd      |  2 +-
 src/mainboard/google/skywalker/chromeos.fmd   |  2 +-
 src/mainboard/google/slippy/chromeos.fmd      |  2 +-
 src/mainboard/google/smaug/chromeos.fmd       |  2 +-
 src/mainboard/google/storm/chromeos.fmd       |  2 +-
 src/mainboard/google/stout/chromeos.fmd       |  2 +-
 src/mainboard/google/trogdor/chromeos.fmd     |  2 +-
 src/mainboard/google/veyron/chromeos.fmd      |  2 +-
 .../google/veyron_mickey/chromeos.fmd         |  2 +-
 .../google/veyron_rialto/chromeos.fmd         |  2 +-
 src/mainboard/google/zork/chromeos.fmd        |  2 +-
 src/mainboard/ibm/sbp1/board.fmd              |  2 +-
 src/mainboard/intel/avenuecity_crb/board.fmd  |  2 +-
 src/mainboard/intel/baskingridge/chromeos.fmd |  2 +-
 .../intel/beechnutcity_crb/board.fmd          |  2 +-
 src/mainboard/intel/cedarisland_crb/board.fmd |  2 +-
 .../intel/coffeelake_rvp/chromeos.fmd         |  2 +-
 .../intel/coffeelake_rvp/chromeos_32MB.fmd    |  2 +-
 src/mainboard/intel/frost_creek/board.fmd     |  2 +-
 .../intel/jasperlake_rvp/chromeos.fmd         |  2 +-
 src/mainboard/intel/kblrvp/chromeos.fmd       |  2 +-
 src/mainboard/intel/kunimitsu/chromeos.fmd    |  2 +-
 .../intel/shadowmountain/chromeos.fmd         |  2 +-
 src/mainboard/intel/strago/chromeos.fmd       |  2 +-
 src/mainboard/intel/tglrvp/chromeos.fmd       |  2 +-
 src/mainboard/intel/wtm2/chromeos.fmd         |  2 +-
 .../lenovo/haswell/vboot-ro-me_clean.fmd      |  2 +-
 src/mainboard/lenovo/haswell/vboot-ro.fmd     |  2 +-
 src/mainboard/lenovo/haswell/vboot-rwab.fmd   |  2 +-
 src/mainboard/lenovo/t400/vboot-rwa.fmd       |  2 +-
 src/mainboard/lenovo/t410/vboot-rwa.fmd       |  2 +-
 .../lenovo/t420/vboot-ro-me_clean.fmd         |  2 +-
 src/mainboard/lenovo/t420/vboot-ro.fmd        |  2 +-
 src/mainboard/lenovo/t420/vboot-rwa.fmd       |  2 +-
 .../lenovo/t420s/vboot-ro-me_clean.fmd        |  2 +-
 src/mainboard/lenovo/t420s/vboot-ro.fmd       |  2 +-
 src/mainboard/lenovo/t420s/vboot-rwa.fmd      |  2 +-
 .../lenovo/t430/vboot-ro-me_clean.fmd         |  2 +-
 src/mainboard/lenovo/t430/vboot-ro.fmd        |  2 +-
 src/mainboard/lenovo/t430/vboot-rwab.fmd      |  2 +-
 .../lenovo/t430s/vboot-ro-me_clean.fmd        |  2 +-
 src/mainboard/lenovo/t430s/vboot-ro.fmd       |  2 +-
 src/mainboard/lenovo/t430s/vboot-rwab.fmd     |  2 +-
 .../lenovo/t520/vboot-ro-me_clean.fmd         |  2 +-
 src/mainboard/lenovo/t520/vboot-ro.fmd        |  2 +-
 src/mainboard/lenovo/t520/vboot-rwa.fmd       |  2 +-
 .../lenovo/t530/vboot-ro-me_clean.fmd         |  2 +-
 src/mainboard/lenovo/t530/vboot-ro.fmd        |  2 +-
 src/mainboard/lenovo/t530/vboot-rwab.fmd      |  2 +-
 .../lenovo/x131e/vboot-ro-me_clean.fmd        |  2 +-
 src/mainboard/lenovo/x131e/vboot-ro.fmd       |  2 +-
 src/mainboard/lenovo/x131e/vboot-rwab.fmd     |  2 +-
 .../x1_carbon_gen1/vboot-ro-me_clean.fmd      |  2 +-
 .../lenovo/x1_carbon_gen1/vboot-ro.fmd        |  2 +-
 .../lenovo/x1_carbon_gen1/vboot-rwab.fmd      |  2 +-
 src/mainboard/lenovo/x200/vboot-rwa.fmd       |  2 +-
 src/mainboard/lenovo/x201/vboot-rwa.fmd       |  2 +-
 .../lenovo/x220/vboot-ro-me_clean.fmd         |  2 +-
 src/mainboard/lenovo/x220/vboot-ro.fmd        |  2 +-
 src/mainboard/lenovo/x220/vboot-rwa.fmd       |  2 +-
 .../lenovo/x230/vboot-ro-me_clean.fmd         |  2 +-
 src/mainboard/lenovo/x230/vboot-ro.fmd        |  2 +-
 src/mainboard/lenovo/x230/vboot-rwab.fmd      |  2 +-
 src/mainboard/lenovo/x60/vboot-rwa.fmd        |  2 +-
 src/mainboard/opencellular/elgon/board.fmd    |  2 +-
 src/mainboard/opencellular/elgon/vboot.fmd    |  2 +-
 .../protectli/vault_adl_p/vboot-rwa.fmd       |  2 +-
 src/mainboard/protectli/vault_cml/board.fmd   |  2 +-
 .../protectli/vault_cml/vboot-rwa.fmd         |  2 +-
 src/mainboard/samsung/lumpy/chromeos.fmd      |  2 +-
 src/mainboard/samsung/stumpy/chromeos.fmd     |  2 +-
 src/mainboard/siemens/fa_ehl/fa_ehl.fmd       |  2 +-
 src/mainboard/siemens/mc_ehl/mc_ehl.fmd       |  2 +-
 src/mainboard/ti/beaglebone/board.fmd         |  2 +-
 src/soc/amd/glinda/Makefile.mk                |  9 ++---
 src/soc/amd/mendocino/Makefile.mk             | 12 +++----
 src/soc/amd/phoenix/Makefile.mk               | 14 +++-----
 util/amdfwtool/amdfwread.c                    |  4 ---
 util/amdfwtool/amdfwtool.h                    |  5 +++
 util/amdfwtool/data_parse.c                   | 34 +++++++++++++++++++
 util/amdfwtool/opts.c                         |  2 +-
 util/cbfstool/default-x86.fmd                 |  2 +-
 util/cbfstool/default.fmd                     |  2 +-
 154 files changed, 199 insertions(+), 180 deletions(-)

diff --git a/Makefile.mk b/Makefile.mk
index bc547dec13..19bac29060 100644
--- a/Makefile.mk
+++ b/Makefile.mk
@@ -1096,7 +1096,6 @@ endif # ifeq($(CONFIG_HAVE_IFD_BIN),y)
 endif # ifneq($(CONFIG_IFD_CHIPSET),)
 
 # entire flash
-FMAP_ROM_ADDR := $(call int-subtract, 0x100000000 $(CONFIG_ROM_SIZE))
 FMAP_ROM_SIZE := $(CONFIG_ROM_SIZE)
 # entire "BIOS" region (everything directly of concern to the host system)
 # relative to ROM_BASE
@@ -1185,7 +1184,6 @@ else # ifeq ($(CONFIG_ARCH_X86),y)
 
 DEFAULT_FLASHMAP:=$(top)/util/cbfstool/default.fmd
 # entire flash
-FMAP_ROM_ADDR := 0
 FMAP_ROM_SIZE := $(CONFIG_ROM_SIZE)
 # entire "BIOS" region (everything directly of concern to the host system)
 # relative to ROM_BASE
@@ -1233,8 +1231,7 @@ FMAP_CBFS_SIZE := $(call int-subtract,$(FMAP_BIOS_SIZE) $(FMAP_CBFS_BASE))
 endif # ifeq ($(CONFIG_ARCH_X86),y)
 
 $(obj)/fmap.fmd: $(top)/Makefile.mk $(DEFAULT_FLASHMAP) $(obj)/config.h
-	sed -e "s,##ROM_BASE##,$(FMAP_ROM_ADDR)," \
-	    -e "s,##ROM_SIZE##,$(FMAP_ROM_SIZE)," \
+	sed -e "s,##ROM_SIZE##,$(FMAP_ROM_SIZE)," \
 	    -e "s,##BIOS_BASE##,$(FMAP_BIOS_BASE)," \
 	    -e "s,##BIOS_SIZE##,$(FMAP_BIOS_SIZE)," \
 	    -e "s,##FMAP_BASE##,$(FMAP_FMAP_BASE)," \
diff --git a/src/arch/x86/walkcbfs.S b/src/arch/x86/walkcbfs.S
index f4b8d2541d..a017ee1e5c 100644
--- a/src/arch/x86/walkcbfs.S
+++ b/src/arch/x86/walkcbfs.S
@@ -93,7 +93,7 @@ tryharder:
 
 check_for_exit:
 	/* if addr <= COREBOOT_END - 1, continue */
-#define FMAP_SECTION_COREBOOT_END (FMAP_SECTION_COREBOOT_START - 1 + FMAP_SECTION_COREBOOT_SIZE)
+#define FMAP_SECTION_COREBOOT_END (COREBOOT_CBFS_START - 1 + FMAP_SECTION_COREBOOT_SIZE)
 
 	movl $FMAP_SECTION_COREBOOT_END, %ecx
 	cmp %ecx, %ebx
diff --git a/src/mainboard/amd/bilby/board.fmd b/src/mainboard/amd/bilby/board.fmd
index b27d9d3bae..e05642321a 100644
--- a/src/mainboard/amd/bilby/board.fmd
+++ b/src/mainboard/amd/bilby/board.fmd
@@ -1,4 +1,4 @@
-FLASH@0xFF000000 16M {
+FLASH 16M {
 	BIOS {
 		RW_MRC_CACHE 64K
 		COREBOOT(CBFS)
diff --git a/src/mainboard/amd/birman/board_glinda.fmd b/src/mainboard/amd/birman/board_glinda.fmd
index bc09fe75d5..4f5598cd77 100644
--- a/src/mainboard/amd/birman/board_glinda.fmd
+++ b/src/mainboard/amd/birman/board_glinda.fmd
@@ -1,4 +1,4 @@
-FLASH@0xFF000000 16M {
+FLASH 16M {
 	BIOS {
 		EC_SIG 4K
 		FMAP 4K
diff --git a/src/mainboard/amd/birman/board_phoenix.fmd b/src/mainboard/amd/birman/board_phoenix.fmd
index bc09fe75d5..4f5598cd77 100644
--- a/src/mainboard/amd/birman/board_phoenix.fmd
+++ b/src/mainboard/amd/birman/board_phoenix.fmd
@@ -1,4 +1,4 @@
-FLASH@0xFF000000 16M {
+FLASH 16M {
 	BIOS {
 		EC_SIG 4K
 		FMAP 4K
diff --git a/src/mainboard/amd/birman/chromeos_glinda.fmd b/src/mainboard/amd/birman/chromeos_glinda.fmd
index 420ed6e6d4..9cc4fbd050 100644
--- a/src/mainboard/amd/birman/chromeos_glinda.fmd
+++ b/src/mainboard/amd/birman/chromeos_glinda.fmd
@@ -1,4 +1,4 @@
-FLASH@0xFF000000 16M {
+FLASH 16M {
 	SI_BIOS {
 		WP_RO 8M {
 			EC_SIG 4K
diff --git a/src/mainboard/amd/birman/chromeos_phoenix.fmd b/src/mainboard/amd/birman/chromeos_phoenix.fmd
index 420ed6e6d4..9cc4fbd050 100644
--- a/src/mainboard/amd/birman/chromeos_phoenix.fmd
+++ b/src/mainboard/amd/birman/chromeos_phoenix.fmd
@@ -1,4 +1,4 @@
-FLASH@0xFF000000 16M {
+FLASH 16M {
 	SI_BIOS {
 		WP_RO 8M {
 			EC_SIG 4K
diff --git a/src/mainboard/amd/birman_plus/board_phoenix.fmd b/src/mainboard/amd/birman_plus/board_phoenix.fmd
index bc09fe75d5..4f5598cd77 100644
--- a/src/mainboard/amd/birman_plus/board_phoenix.fmd
+++ b/src/mainboard/amd/birman_plus/board_phoenix.fmd
@@ -1,4 +1,4 @@
-FLASH@0xFF000000 16M {
+FLASH 16M {
 	BIOS {
 		EC_SIG 4K
 		FMAP 4K
diff --git a/src/mainboard/amd/birman_plus/chromeos_glinda.fmd b/src/mainboard/amd/birman_plus/chromeos_glinda.fmd
index 420ed6e6d4..9cc4fbd050 100644
--- a/src/mainboard/amd/birman_plus/chromeos_glinda.fmd
+++ b/src/mainboard/amd/birman_plus/chromeos_glinda.fmd
@@ -1,4 +1,4 @@
-FLASH@0xFF000000 16M {
+FLASH 16M {
 	SI_BIOS {
 		WP_RO 8M {
 			EC_SIG 4K
diff --git a/src/mainboard/amd/birman_plus/chromeos_phoenix.fmd b/src/mainboard/amd/birman_plus/chromeos_phoenix.fmd
index 420ed6e6d4..9cc4fbd050 100644
--- a/src/mainboard/amd/birman_plus/chromeos_phoenix.fmd
+++ b/src/mainboard/amd/birman_plus/chromeos_phoenix.fmd
@@ -1,4 +1,4 @@
-FLASH@0xFF000000 16M {
+FLASH 16M {
 	SI_BIOS {
 		WP_RO 8M {
 			EC_SIG 4K
diff --git a/src/mainboard/amd/chausie/board.fmd b/src/mainboard/amd/chausie/board.fmd
index 6c6ad92a28..eace04152f 100644
--- a/src/mainboard/amd/chausie/board.fmd
+++ b/src/mainboard/amd/chausie/board.fmd
@@ -1,4 +1,4 @@
-FLASH@0xFF000000 16M {
+FLASH 16M {
 	BIOS {
 		EC 4K
 		RW_MRC_CACHE 120K
diff --git a/src/mainboard/amd/chausie/chromeos.fmd b/src/mainboard/amd/chausie/chromeos.fmd
index c0e02dd5b8..96cc1dc4de 100644
--- a/src/mainboard/amd/chausie/chromeos.fmd
+++ b/src/mainboard/amd/chausie/chromeos.fmd
@@ -1,4 +1,4 @@
-FLASH@0xFF000000 16M {
+FLASH 16M {
 	SI_BIOS {
 		EC 4K
 		RW_MRC_CACHE(PRESERVE) 120K
diff --git a/src/mainboard/amd/crater/board_renoir.fmd b/src/mainboard/amd/crater/board_renoir.fmd
index 556e295a11..b5a4e73a00 100644
--- a/src/mainboard/amd/crater/board_renoir.fmd
+++ b/src/mainboard/amd/crater/board_renoir.fmd
@@ -1,4 +1,4 @@
-FLASH@0xFF000000 16M {
+FLASH 16M {
 	BIOS {
 		EC_SIG 4K
 		FMAP 4K
diff --git a/src/mainboard/amd/crater/chromeos_renoir.fmd b/src/mainboard/amd/crater/chromeos_renoir.fmd
index 76a21f6635..12b472774e 100644
--- a/src/mainboard/amd/crater/chromeos_renoir.fmd
+++ b/src/mainboard/amd/crater/chromeos_renoir.fmd
@@ -1,4 +1,4 @@
-FLASH@0xFF000000 16M {
+FLASH 16M {
 	SI_BIOS {
 		WP_RO 8M {
 			EC_SIG 4K
diff --git a/src/mainboard/amd/majolica/board.fmd b/src/mainboard/amd/majolica/board.fmd
index 442d80f341..fc7108b77c 100644
--- a/src/mainboard/amd/majolica/board.fmd
+++ b/src/mainboard/amd/majolica/board.fmd
@@ -1,4 +1,4 @@
-FLASH@0xFF000000 16M {
+FLASH 16M {
 	BIOS {
 		EC 128K
 		RW_MRC_CACHE 64K
diff --git a/src/mainboard/amd/majolica/chromeos.fmd b/src/mainboard/amd/majolica/chromeos.fmd
index 1a1d96bbb3..eecbbb1d43 100644
--- a/src/mainboard/amd/majolica/chromeos.fmd
+++ b/src/mainboard/amd/majolica/chromeos.fmd
@@ -1,4 +1,4 @@
-FLASH@0xFF000000 16M {
+FLASH 16M {
 	SI_BIOS {
 		EC 128K
 		RW_MRC_CACHE(PRESERVE) 64K
diff --git a/src/mainboard/amd/mandolin/variants/cereme/board.fmd b/src/mainboard/amd/mandolin/variants/cereme/board.fmd
index 442d80f341..fc7108b77c 100644
--- a/src/mainboard/amd/mandolin/variants/cereme/board.fmd
+++ b/src/mainboard/amd/mandolin/variants/cereme/board.fmd
@@ -1,4 +1,4 @@
-FLASH@0xFF000000 16M {
+FLASH 16M {
 	BIOS {
 		EC 128K
 		RW_MRC_CACHE 64K
diff --git a/src/mainboard/amd/mandolin/variants/mandolin/board.fmd b/src/mainboard/amd/mandolin/variants/mandolin/board.fmd
index 33b281d37f..522330c1f4 100644
--- a/src/mainboard/amd/mandolin/variants/mandolin/board.fmd
+++ b/src/mainboard/amd/mandolin/variants/mandolin/board.fmd
@@ -1,4 +1,4 @@
-FLASH@0xFF800000 8M {
+FLASH 8M {
 	BIOS {
 		EC 128K
 		RW_MRC_CACHE 64K
diff --git a/src/mainboard/amd/mayan/board.fmd b/src/mainboard/amd/mayan/board.fmd
index 6f7af56ecb..2600ec75a2 100644
--- a/src/mainboard/amd/mayan/board.fmd
+++ b/src/mainboard/amd/mayan/board.fmd
@@ -1,4 +1,4 @@
-FLASH@0xFF000000 16M {
+FLASH 16M {
 	BIOS {
 		EC 4K
 		FMAP 4K
diff --git a/src/mainboard/amd/mayan/chromeos.fmd b/src/mainboard/amd/mayan/chromeos.fmd
index b70d561826..b77203f589 100644
--- a/src/mainboard/amd/mayan/chromeos.fmd
+++ b/src/mainboard/amd/mayan/chromeos.fmd
@@ -1,4 +1,4 @@
-FLASH@0xFF000000 16M {
+FLASH 16M {
 	SI_BIOS {
 		WP_RO 8M {
 			EC 4K
diff --git a/src/mainboard/arm/rdn2/flash.fmd b/src/mainboard/arm/rdn2/flash.fmd
index 2b75d355d1..dc7e866301 100644
--- a/src/mainboard/arm/rdn2/flash.fmd
+++ b/src/mainboard/arm/rdn2/flash.fmd
@@ -1,4 +1,4 @@
-FLASH@0x08000000 CONFIG_ROM_SIZE {
+FLASH CONFIG_ROM_SIZE {
 
 	BIOS@0x0 CONFIG_ROM_SIZE {
 
diff --git a/src/mainboard/bytedance/bd_egs/board.fmd b/src/mainboard/bytedance/bd_egs/board.fmd
index 1a58bb196b..2c5ddd286b 100644
--- a/src/mainboard/bytedance/bd_egs/board.fmd
+++ b/src/mainboard/bytedance/bd_egs/board.fmd
@@ -1,4 +1,4 @@
-FLASH@0xfc000000 64M {
+FLASH 64M {
 	SI_ALL@0x0 0x03000000 {
 		SI_DESC@0x0 0x1000
 		SI_GBE@0x1000 0x2000
diff --git a/src/mainboard/cavium/cn8100_sff_evb/board.fmd b/src/mainboard/cavium/cn8100_sff_evb/board.fmd
index 011d0701aa..bfab2eb4e3 100644
--- a/src/mainboard/cavium/cn8100_sff_evb/board.fmd
+++ b/src/mainboard/cavium/cn8100_sff_evb/board.fmd
@@ -1,4 +1,4 @@
-FLASH@0x0 8M {
+FLASH 8M {
 	WP_RO@0x0 0x800000 {
 		RO_SECTION@0x0 0x7fc000 {
 			# 0 - 0x10000 is free for firmware usage.
diff --git a/src/mainboard/emulation/qemu-i440fx/vboot-rwa-8M.fmd b/src/mainboard/emulation/qemu-i440fx/vboot-rwa-8M.fmd
index 55a38b79a9..159a5e3f41 100644
--- a/src/mainboard/emulation/qemu-i440fx/vboot-rwa-8M.fmd
+++ b/src/mainboard/emulation/qemu-i440fx/vboot-rwa-8M.fmd
@@ -1,4 +1,4 @@
-FLASH@0xff800000 0x800000 {
+FLASH 0x800000 {
 	SI_BIOS 0x800000 {
 		RW_SECTION_A 0x3c0000 {
 			VBLOCK_A 0x10000
diff --git a/src/mainboard/emulation/qemu-q35/vboot-rwa-8M.fmd b/src/mainboard/emulation/qemu-q35/vboot-rwa-8M.fmd
index 55a38b79a9..159a5e3f41 100644
--- a/src/mainboard/emulation/qemu-q35/vboot-rwa-8M.fmd
+++ b/src/mainboard/emulation/qemu-q35/vboot-rwa-8M.fmd
@@ -1,4 +1,4 @@
-FLASH@0xff800000 0x800000 {
+FLASH 0x800000 {
 	SI_BIOS 0x800000 {
 		RW_SECTION_A 0x3c0000 {
 			VBLOCK_A 0x10000
diff --git a/src/mainboard/emulation/qemu-q35/vboot-rwab-8M.fmd b/src/mainboard/emulation/qemu-q35/vboot-rwab-8M.fmd
index 8064fdfeaf..8bc95f846c 100644
--- a/src/mainboard/emulation/qemu-q35/vboot-rwab-8M.fmd
+++ b/src/mainboard/emulation/qemu-q35/vboot-rwab-8M.fmd
@@ -1,4 +1,4 @@
-FLASH@0xff800000 0x800000 {
+FLASH 0x800000 {
 	SI_BIOS 0x800000 {
 		RW_SECTION_A 0x1c0000 {
 			VBLOCK_A 0x10000
diff --git a/src/mainboard/emulation/qemu-sbsa/flash.fmd b/src/mainboard/emulation/qemu-sbsa/flash.fmd
index fcc6e19a99..e91034eb51 100644
--- a/src/mainboard/emulation/qemu-sbsa/flash.fmd
+++ b/src/mainboard/emulation/qemu-sbsa/flash.fmd
@@ -12,7 +12,7 @@
 # +-------------+ <-- ROM_SIZE
 #
 
-FLASH@0x10000000 CONFIG_ROM_SIZE {
+FLASH CONFIG_ROM_SIZE {
 
 	BIOS {
 
diff --git a/src/mainboard/facebook/fbg1701/vboot-rw.fmd b/src/mainboard/facebook/fbg1701/vboot-rw.fmd
index a00c0c9d92..baaacc0309 100644
--- a/src/mainboard/facebook/fbg1701/vboot-rw.fmd
+++ b/src/mainboard/facebook/fbg1701/vboot-rw.fmd
@@ -1,4 +1,4 @@
-FLASH@0xff800000 8M {
+FLASH 8M {
 	SI_BIOS@0x200000 0x600000 {
 		MISC_RW@0x0 0x0a000 {
 			RW_MRC_CACHE@0x0 0x08000
diff --git a/src/mainboard/framework/azalea/coreboot.fmd b/src/mainboard/framework/azalea/coreboot.fmd
index 8f47443c1d..f9cc100826 100644
--- a/src/mainboard/framework/azalea/coreboot.fmd
+++ b/src/mainboard/framework/azalea/coreboot.fmd
@@ -1,4 +1,4 @@
-FLASH@0xFF000000 32M {
+FLASH 32M {
 	BIOS_PAGE_1 16M {
 		FMAP 4K
 		COREBOOT(CBFS)
diff --git a/src/mainboard/google/asurada/chromeos.fmd b/src/mainboard/google/asurada/chromeos.fmd
index bb2a95cd0f..5716251d63 100644
--- a/src/mainboard/google/asurada/chromeos.fmd
+++ b/src/mainboard/google/asurada/chromeos.fmd
@@ -10,7 +10,7 @@
 # instead of a group section; otherwise the preserved data may be wrong if you
 # resize or reorder sections inside a group.
 
-FLASH@0x0 8M {
+FLASH 8M {
 	WP_RO@0x0 4M {
 		RO_SECTION {
 			BOOTBLOCK 128K
diff --git a/src/mainboard/google/auron/chromeos.fmd b/src/mainboard/google/auron/chromeos.fmd
index 923c8ee18a..dae8796a27 100644
--- a/src/mainboard/google/auron/chromeos.fmd
+++ b/src/mainboard/google/auron/chromeos.fmd
@@ -1,4 +1,4 @@
-FLASH@0xff800000 0x800000 {
+FLASH 0x800000 {
 	SI_ALL@0x0 0x200000 {
 		SI_DESC@0x0 0x1000
 		SI_ME@0x1000 0x1ff000
diff --git a/src/mainboard/google/beltino/chromeos.fmd b/src/mainboard/google/beltino/chromeos.fmd
index 923c8ee18a..dae8796a27 100644
--- a/src/mainboard/google/beltino/chromeos.fmd
+++ b/src/mainboard/google/beltino/chromeos.fmd
@@ -1,4 +1,4 @@
-FLASH@0xff800000 0x800000 {
+FLASH 0x800000 {
 	SI_ALL@0x0 0x200000 {
 		SI_DESC@0x0 0x1000
 		SI_ME@0x1000 0x1ff000
diff --git a/src/mainboard/google/butterfly/chromeos.fmd b/src/mainboard/google/butterfly/chromeos.fmd
index 93048a37ec..ef8ca78ff9 100644
--- a/src/mainboard/google/butterfly/chromeos.fmd
+++ b/src/mainboard/google/butterfly/chromeos.fmd
@@ -1,4 +1,4 @@
-FLASH@0xff800000 0x800000 {
+FLASH 0x800000 {
 	SI_ALL@0x0 0x200000 {
 		SI_DESC@0x0 0x1000
 		SI_ME@0x1000 0x1ff000
diff --git a/src/mainboard/google/cherry/chromeos.fmd b/src/mainboard/google/cherry/chromeos.fmd
index bb2a95cd0f..5716251d63 100644
--- a/src/mainboard/google/cherry/chromeos.fmd
+++ b/src/mainboard/google/cherry/chromeos.fmd
@@ -10,7 +10,7 @@
 # instead of a group section; otherwise the preserved data may be wrong if you
 # resize or reorder sections inside a group.
 
-FLASH@0x0 8M {
+FLASH 8M {
 	WP_RO@0x0 4M {
 		RO_SECTION {
 			BOOTBLOCK 128K
diff --git a/src/mainboard/google/corsola/chromeos.fmd b/src/mainboard/google/corsola/chromeos.fmd
index 5b2234d39e..6b3cecbee5 100644
--- a/src/mainboard/google/corsola/chromeos.fmd
+++ b/src/mainboard/google/corsola/chromeos.fmd
@@ -10,7 +10,7 @@
 # instead of a group section; otherwise the preserved data may be wrong if you
 # resize or reorder sections inside a group.
 
-FLASH@0x0 8M {
+FLASH 8M {
 	WP_RO@0x0 4M {
 		RO_SECTION {
 			BOOTBLOCK 128K
diff --git a/src/mainboard/google/cyan/chromeos.fmd b/src/mainboard/google/cyan/chromeos.fmd
index bc9bac3344..a41a8c1a41 100644
--- a/src/mainboard/google/cyan/chromeos.fmd
+++ b/src/mainboard/google/cyan/chromeos.fmd
@@ -1,4 +1,4 @@
-FLASH@0xff800000 0x800000 {
+FLASH 0x800000 {
 	SI_ALL@0x0 0x200000 {
 		SI_DESC@0x0 0x1000
 		SI_ME@0x1000 0x1ff000
diff --git a/src/mainboard/google/daisy/chromeos.fmd b/src/mainboard/google/daisy/chromeos.fmd
index 63bde335cb..60794a8a50 100644
--- a/src/mainboard/google/daisy/chromeos.fmd
+++ b/src/mainboard/google/daisy/chromeos.fmd
@@ -1,4 +1,4 @@
-FLASH@0x0 0x400000 {
+FLASH 0x400000 {
 	WP_RO@0x0 0x200000 {
 		RO_SECTION@0x0 0x1f0000 {
 			BOOTBLOCK@0 128K
diff --git a/src/mainboard/google/dedede/chromeos-dedede-16MiB.fmd b/src/mainboard/google/dedede/chromeos-dedede-16MiB.fmd
index 0e21c4c91b..5c80e6df49 100644
--- a/src/mainboard/google/dedede/chromeos-dedede-16MiB.fmd
+++ b/src/mainboard/google/dedede/chromeos-dedede-16MiB.fmd
@@ -1,4 +1,4 @@
-FLASH@0xff000000 0x1000000 {
+FLASH 0x1000000 {
 	SI_ALL@0x0 0x381000 {
 		SI_DESC@0x0 0x1000
 		SI_ME@0x1000 0x380000
diff --git a/src/mainboard/google/dedede/chromeos-dedede-32MiB.fmd b/src/mainboard/google/dedede/chromeos-dedede-32MiB.fmd
index 60ea3ded64..ece712d7e1 100644
--- a/src/mainboard/google/dedede/chromeos-dedede-32MiB.fmd
+++ b/src/mainboard/google/dedede/chromeos-dedede-32MiB.fmd
@@ -1,4 +1,4 @@
-FLASH@0xfe000000 0x2000000 {
+FLASH 0x2000000 {
 	SI_ALL@0x0 0x500000 {
 		SI_DESC@0x0 0x1000
 		SI_ME@0x1000 0x4ff000
diff --git a/src/mainboard/google/drallion/chromeos.fmd b/src/mainboard/google/drallion/chromeos.fmd
index 6e9170ed41..6923886a50 100644
--- a/src/mainboard/google/drallion/chromeos.fmd
+++ b/src/mainboard/google/drallion/chromeos.fmd
@@ -1,4 +1,4 @@
-FLASH@0xfe000000 0x2000000 {
+FLASH 0x2000000 {
 	SI_ALL@0x0 0x438000 {
 		SI_DESC@0x0 0x1000
 		SI_EC@0x1000 0x100000
diff --git a/src/mainboard/google/drallion/default.fmd b/src/mainboard/google/drallion/default.fmd
index 4f2bedf9c2..9d1216b009 100644
--- a/src/mainboard/google/drallion/default.fmd
+++ b/src/mainboard/google/drallion/default.fmd
@@ -1,4 +1,4 @@
-FLASH@0xfe000000 0x2000000 {
+FLASH 0x2000000 {
 	SI_BIOS@0x400000 {
 		MEMORY_MAPPED@0xc00000 { /* 16MiB total */
 			RW_MRC_CACHE 0x10000
diff --git a/src/mainboard/google/eve/chromeos.fmd b/src/mainboard/google/eve/chromeos.fmd
index 1cc4a61ae2..92bca1b4ca 100644
--- a/src/mainboard/google/eve/chromeos.fmd
+++ b/src/mainboard/google/eve/chromeos.fmd
@@ -1,4 +1,4 @@
-FLASH@0xff000000 0x1000000 {
+FLASH 0x1000000 {
 	SI_ALL@0x0 0x200000 {
 		SI_DESC@0x0 0x1000
 		SI_ME@0x1000 0x1ff000
diff --git a/src/mainboard/google/fizz/chromeos.fmd b/src/mainboard/google/fizz/chromeos.fmd
index 1cc4a61ae2..92bca1b4ca 100644
--- a/src/mainboard/google/fizz/chromeos.fmd
+++ b/src/mainboard/google/fizz/chromeos.fmd
@@ -1,4 +1,4 @@
-FLASH@0xff000000 0x1000000 {
+FLASH 0x1000000 {
 	SI_ALL@0x0 0x200000 {
 		SI_DESC@0x0 0x1000
 		SI_ME@0x1000 0x1ff000
diff --git a/src/mainboard/google/foster/chromeos.fmd b/src/mainboard/google/foster/chromeos.fmd
index f9a531cc4b..5a5f903969 100644
--- a/src/mainboard/google/foster/chromeos.fmd
+++ b/src/mainboard/google/foster/chromeos.fmd
@@ -1,4 +1,4 @@
-FLASH@0x0 0x400000 {
+FLASH 0x400000 {
 	WP_RO@0x0 0x300000 {
 		RO_SECTION@0x0 0x2f0000 {
 			BOOTBLOCK@0 128K
diff --git a/src/mainboard/google/gale/chromeos.fmd b/src/mainboard/google/gale/chromeos.fmd
index 3a55bdcae4..4d3c91344a 100644
--- a/src/mainboard/google/gale/chromeos.fmd
+++ b/src/mainboard/google/gale/chromeos.fmd
@@ -1,4 +1,4 @@
-FLASH@0x0 0x800000 {
+FLASH 0x800000 {
 	WP_RO@0x0 0x400000 {
 		RO_SECTION@0x0 0x3e0000 {
 			BOOTBLOCK@0 128K
diff --git a/src/mainboard/google/geralt/chromeos.fmd b/src/mainboard/google/geralt/chromeos.fmd
index a8c4dfe0af..f3302996dd 100644
--- a/src/mainboard/google/geralt/chromeos.fmd
+++ b/src/mainboard/google/geralt/chromeos.fmd
@@ -10,7 +10,7 @@
 # instead of a group section; otherwise the preserved data may be wrong if you
 # resize or reorder sections inside a group.
 
-FLASH@0x0 8M {
+FLASH 8M {
 	WP_RO@0x0 4M {
 		RO_SECTION {
 			BOOTBLOCK 128K
diff --git a/src/mainboard/google/glados/chromeos.fmd b/src/mainboard/google/glados/chromeos.fmd
index 9ba1bf7275..813271259a 100644
--- a/src/mainboard/google/glados/chromeos.fmd
+++ b/src/mainboard/google/glados/chromeos.fmd
@@ -1,4 +1,4 @@
-FLASH@0xff000000 0x1000000 {
+FLASH 0x1000000 {
 	SI_ALL@0x0 0x200000 {
 		SI_DESC@0x0 0x1000
 		SI_ME@0x1000 0x1ff000
diff --git a/src/mainboard/google/gru/chromeos.fmd b/src/mainboard/google/gru/chromeos.fmd
index 032f472463..f569c3075c 100644
--- a/src/mainboard/google/gru/chromeos.fmd
+++ b/src/mainboard/google/gru/chromeos.fmd
@@ -1,4 +1,4 @@
-FLASH@0x0 0x800000 {
+FLASH 0x800000 {
 	WP_RO@0x0 0x400000 {
 		RO_SECTION@0x0 0x3e0000 {
 			BOOTBLOCK@0 128K
diff --git a/src/mainboard/google/guybrush/chromeos.fmd b/src/mainboard/google/guybrush/chromeos.fmd
index c4c90a13fe..922ed6f4c8 100644
--- a/src/mainboard/google/guybrush/chromeos.fmd
+++ b/src/mainboard/google/guybrush/chromeos.fmd
@@ -1,4 +1,4 @@
-FLASH@0xFF000000 16M {
+FLASH 16M {
 	SI_BIOS {
 		RW_MRC_CACHE(PRESERVE) 64K
 		RW_SECTION_A 3M {
diff --git a/src/mainboard/google/hatch/chromeos-16MiB.fmd b/src/mainboard/google/hatch/chromeos-16MiB.fmd
index 8880a4f9fe..83a828e4ba 100644
--- a/src/mainboard/google/hatch/chromeos-16MiB.fmd
+++ b/src/mainboard/google/hatch/chromeos-16MiB.fmd
@@ -1,4 +1,4 @@
-FLASH@0xff000000 0x1000000 {
+FLASH 0x1000000 {
 	SI_ALL@0x0 0x400000 {
 		SI_DESC@0x0 0x1000
 		SI_ME@0x1000 0x3ff000
diff --git a/src/mainboard/google/hatch/chromeos-32MiB.fmd b/src/mainboard/google/hatch/chromeos-32MiB.fmd
index 8368b0a44b..2161ed5f82 100644
--- a/src/mainboard/google/hatch/chromeos-32MiB.fmd
+++ b/src/mainboard/google/hatch/chromeos-32MiB.fmd
@@ -1,4 +1,4 @@
-FLASH@0xfe000000 0x2000000 {
+FLASH 0x2000000 {
 	SI_ALL@0x0 0x400000 {
 		SI_DESC@0x0 0x1000
 		SI_ME@0x1000 0x3ff000
diff --git a/src/mainboard/google/herobrine/chromeos.fmd b/src/mainboard/google/herobrine/chromeos.fmd
index b7633a497e..5642fab509 100644
--- a/src/mainboard/google/herobrine/chromeos.fmd
+++ b/src/mainboard/google/herobrine/chromeos.fmd
@@ -3,9 +3,9 @@
 # TODO: update for Herobrine
 
 #if CONFIG_BOARD_GOOGLE_PIGLIN || CONFIG_BOARD_GOOGLE_HOGLIN
-FLASH@0x0 CONFIG_ROM_SIZE {
+FLASH CONFIG_ROM_SIZE {
 #else
-FLASH@0x0 8M {
+FLASH 8M {
 #endif
 	WP_RO 4M {
 		RO_SECTION 0x3c4000 {
diff --git a/src/mainboard/google/jecht/chromeos.fmd b/src/mainboard/google/jecht/chromeos.fmd
index 923c8ee18a..dae8796a27 100644
--- a/src/mainboard/google/jecht/chromeos.fmd
+++ b/src/mainboard/google/jecht/chromeos.fmd
@@ -1,4 +1,4 @@
-FLASH@0xff800000 0x800000 {
+FLASH 0x800000 {
 	SI_ALL@0x0 0x200000 {
 		SI_DESC@0x0 0x1000
 		SI_ME@0x1000 0x1ff000
diff --git a/src/mainboard/google/kahlee/variants/baseboard/chromeos.fmd b/src/mainboard/google/kahlee/variants/baseboard/chromeos.fmd
index d7d0a886d3..faabc0b1b1 100644
--- a/src/mainboard/google/kahlee/variants/baseboard/chromeos.fmd
+++ b/src/mainboard/google/kahlee/variants/baseboard/chromeos.fmd
@@ -1,4 +1,4 @@
-FLASH@0xFF000000 0x1000000 {
+FLASH 0x1000000 {
 	SI_BIOS@0x0 0x1000000 {
 		UNIFIED_MRC_CACHE@0x0 0x21000 {
 			RW_MRC_CACHE@0x0 0x10000
diff --git a/src/mainboard/google/kukui/chromeos.fmd b/src/mainboard/google/kukui/chromeos.fmd
index 61d45b0816..8158ad2f2c 100644
--- a/src/mainboard/google/kukui/chromeos.fmd
+++ b/src/mainboard/google/kukui/chromeos.fmd
@@ -10,7 +10,7 @@
 # instead of a group section; otherwise the preserved data may be wrong if you
 # resize or reorder sections inside a group.
 
-FLASH@0x0 8M {
+FLASH 8M {
 	WP_RO@0x0 4M {
 		RO_SECTION {
 			BOOTBLOCK 128K
diff --git a/src/mainboard/google/link/chromeos.fmd b/src/mainboard/google/link/chromeos.fmd
index 3841445eec..986e0a3c3e 100644
--- a/src/mainboard/google/link/chromeos.fmd
+++ b/src/mainboard/google/link/chromeos.fmd
@@ -1,4 +1,4 @@
-FLASH@0xff800000 0x800000 {
+FLASH 0x800000 {
 	SI_ALL@0x0 0x200000 {
 		SI_DESC@0x0 0x1000
 		SI_ME@0x1000 0x1ff000
diff --git a/src/mainboard/google/mistral/chromeos.fmd b/src/mainboard/google/mistral/chromeos.fmd
index ccdfbde006..e412c97456 100644
--- a/src/mainboard/google/mistral/chromeos.fmd
+++ b/src/mainboard/google/mistral/chromeos.fmd
@@ -1,6 +1,6 @@
 ## SPDX-License-Identifier: GPL-2.0-only
 
-FLASH@0x0 8M {
+FLASH 8M {
 	WP_RO 4M {
 		RO_SECTION 0x204000 {
 			BOOTBLOCK 128K
diff --git a/src/mainboard/google/myst/chromeos.fmd b/src/mainboard/google/myst/chromeos.fmd
index 2bfa260e71..81fcbe3360 100644
--- a/src/mainboard/google/myst/chromeos.fmd
+++ b/src/mainboard/google/myst/chromeos.fmd
@@ -1,5 +1,5 @@
 # TODO(b/276944900): Update for 32 MB support, evaluate WP_RO size
-FLASH@0xFF000000 16M {
+FLASH 16M {
 	SI_BIOS {
 		WP_RO 4M {
 			RO_GSCVD 8K
diff --git a/src/mainboard/google/nyan/chromeos.fmd b/src/mainboard/google/nyan/chromeos.fmd
index bca13463cb..206326169d 100644
--- a/src/mainboard/google/nyan/chromeos.fmd
+++ b/src/mainboard/google/nyan/chromeos.fmd
@@ -1,4 +1,4 @@
-FLASH@0x0 0x400000 {
+FLASH 0x400000 {
 	WP_RO@0x0 0x200000 {
 		RO_SECTION@0x0 0x1f0000 {
 			BOOTBLOCK@0 128K
diff --git a/src/mainboard/google/nyan_big/chromeos.fmd b/src/mainboard/google/nyan_big/chromeos.fmd
index bca13463cb..206326169d 100644
--- a/src/mainboard/google/nyan_big/chromeos.fmd
+++ b/src/mainboard/google/nyan_big/chromeos.fmd
@@ -1,4 +1,4 @@
-FLASH@0x0 0x400000 {
+FLASH 0x400000 {
 	WP_RO@0x0 0x200000 {
 		RO_SECTION@0x0 0x1f0000 {
 			BOOTBLOCK@0 128K
diff --git a/src/mainboard/google/nyan_blaze/chromeos.fmd b/src/mainboard/google/nyan_blaze/chromeos.fmd
index bca13463cb..206326169d 100644
--- a/src/mainboard/google/nyan_blaze/chromeos.fmd
+++ b/src/mainboard/google/nyan_blaze/chromeos.fmd
@@ -1,4 +1,4 @@
-FLASH@0x0 0x400000 {
+FLASH 0x400000 {
 	WP_RO@0x0 0x200000 {
 		RO_SECTION@0x0 0x1f0000 {
 			BOOTBLOCK@0 128K
diff --git a/src/mainboard/google/oak/chromeos.fmd b/src/mainboard/google/oak/chromeos.fmd
index df35976d00..9df6494e4c 100644
--- a/src/mainboard/google/oak/chromeos.fmd
+++ b/src/mainboard/google/oak/chromeos.fmd
@@ -1,4 +1,4 @@
-FLASH@0x0 0x400000 {
+FLASH 0x400000 {
 	WP_RO@0x0 0x200000 {
 		RO_SECTION@0x0 0x1f0000 {
 			BOOTBLOCK@0 128K
diff --git a/src/mainboard/google/parrot/chromeos.fmd b/src/mainboard/google/parrot/chromeos.fmd
index 6752888f03..90e59dec05 100644
--- a/src/mainboard/google/parrot/chromeos.fmd
+++ b/src/mainboard/google/parrot/chromeos.fmd
@@ -1,4 +1,4 @@
-FLASH@0xff800000 0x800000 {
+FLASH 0x800000 {
 	SI_ALL@0x0 0x200000 {
 		SI_DESC@0x0 0x1000
 		SI_ME@0x1000 0x1ff000
diff --git a/src/mainboard/google/peach_pit/chromeos.fmd b/src/mainboard/google/peach_pit/chromeos.fmd
index 63bde335cb..60794a8a50 100644
--- a/src/mainboard/google/peach_pit/chromeos.fmd
+++ b/src/mainboard/google/peach_pit/chromeos.fmd
@@ -1,4 +1,4 @@
-FLASH@0x0 0x400000 {
+FLASH 0x400000 {
 	WP_RO@0x0 0x200000 {
 		RO_SECTION@0x0 0x1f0000 {
 			BOOTBLOCK@0 128K
diff --git a/src/mainboard/google/poppy/chromeos.fmd b/src/mainboard/google/poppy/chromeos.fmd
index 1cc4a61ae2..92bca1b4ca 100644
--- a/src/mainboard/google/poppy/chromeos.fmd
+++ b/src/mainboard/google/poppy/chromeos.fmd
@@ -1,4 +1,4 @@
-FLASH@0xff000000 0x1000000 {
+FLASH 0x1000000 {
 	SI_ALL@0x0 0x200000 {
 		SI_DESC@0x0 0x1000
 		SI_ME@0x1000 0x1ff000
diff --git a/src/mainboard/google/puff/chromeos-16MiB.fmd b/src/mainboard/google/puff/chromeos-16MiB.fmd
index 61a0b0fbb4..457c2c9c60 100644
--- a/src/mainboard/google/puff/chromeos-16MiB.fmd
+++ b/src/mainboard/google/puff/chromeos-16MiB.fmd
@@ -1,4 +1,4 @@
-FLASH@0xff000000 0x1000000 {
+FLASH 0x1000000 {
 	SI_ALL@0x0 0x300000 {
 		SI_DESC@0x0 0x1000
 		SI_ME@0x1000 0x2ff000
diff --git a/src/mainboard/google/puff/chromeos-32MiB.fmd b/src/mainboard/google/puff/chromeos-32MiB.fmd
index 81840b1e60..caa9636c6a 100644
--- a/src/mainboard/google/puff/chromeos-32MiB.fmd
+++ b/src/mainboard/google/puff/chromeos-32MiB.fmd
@@ -1,4 +1,4 @@
-FLASH@0xfe000000 0x2000000 {
+FLASH 0x2000000 {
 	SI_ALL@0x0 0x300000 {
 		SI_DESC@0x0 0x1000
 		SI_ME@0x1000 0x2ff000
diff --git a/src/mainboard/google/rambi/chromeos.fmd b/src/mainboard/google/rambi/chromeos.fmd
index 923c8ee18a..dae8796a27 100644
--- a/src/mainboard/google/rambi/chromeos.fmd
+++ b/src/mainboard/google/rambi/chromeos.fmd
@@ -1,4 +1,4 @@
-FLASH@0xff800000 0x800000 {
+FLASH 0x800000 {
 	SI_ALL@0x0 0x200000 {
 		SI_DESC@0x0 0x1000
 		SI_ME@0x1000 0x1ff000
diff --git a/src/mainboard/google/rauru/chromeos.fmd b/src/mainboard/google/rauru/chromeos.fmd
index a1595df6f4..abf673fa03 100644
--- a/src/mainboard/google/rauru/chromeos.fmd
+++ b/src/mainboard/google/rauru/chromeos.fmd
@@ -10,7 +10,7 @@
 # instead of a group section; otherwise the preserved data may be wrong if you
 # resize or reorder sections inside a group.
 
-FLASH@0x0 8M {
+FLASH 8M {
 	WP_RO@0x0 4M {
 		RO_SECTION {
 			BOOTBLOCK 128K
diff --git a/src/mainboard/google/sarien/chromeos.fmd b/src/mainboard/google/sarien/chromeos.fmd
index 65a915a2c0..18d3cf1e53 100644
--- a/src/mainboard/google/sarien/chromeos.fmd
+++ b/src/mainboard/google/sarien/chromeos.fmd
@@ -1,4 +1,4 @@
-FLASH@0xfe000000 0x2000000 {
+FLASH 0x2000000 {
 	SI_ALL@0x0 0x400000 {
 		SI_DESC@0x0 0x1000
 		SI_EC@0x1000 0x100000
diff --git a/src/mainboard/google/sarien/default.fmd b/src/mainboard/google/sarien/default.fmd
index 4f2bedf9c2..9d1216b009 100644
--- a/src/mainboard/google/sarien/default.fmd
+++ b/src/mainboard/google/sarien/default.fmd
@@ -1,4 +1,4 @@
-FLASH@0xfe000000 0x2000000 {
+FLASH 0x2000000 {
 	SI_BIOS@0x400000 {
 		MEMORY_MAPPED@0xc00000 { /* 16MiB total */
 			RW_MRC_CACHE 0x10000
diff --git a/src/mainboard/google/skyrim/chromeos.fmd b/src/mainboard/google/skyrim/chromeos.fmd
index afc6ce13b4..12ad05f5ee 100644
--- a/src/mainboard/google/skyrim/chromeos.fmd
+++ b/src/mainboard/google/skyrim/chromeos.fmd
@@ -1,4 +1,4 @@
-FLASH@0xFF000000 16M {
+FLASH 16M {
 	SI_BIOS {
 		RW_MRC_CACHE(PRESERVE) 120K
 		RW_SECTION_A 3M {
diff --git a/src/mainboard/google/skywalker/chromeos.fmd b/src/mainboard/google/skywalker/chromeos.fmd
index 5b2234d39e..6b3cecbee5 100644
--- a/src/mainboard/google/skywalker/chromeos.fmd
+++ b/src/mainboard/google/skywalker/chromeos.fmd
@@ -10,7 +10,7 @@
 # instead of a group section; otherwise the preserved data may be wrong if you
 # resize or reorder sections inside a group.
 
-FLASH@0x0 8M {
+FLASH 8M {
 	WP_RO@0x0 4M {
 		RO_SECTION {
 			BOOTBLOCK 128K
diff --git a/src/mainboard/google/slippy/chromeos.fmd b/src/mainboard/google/slippy/chromeos.fmd
index 923c8ee18a..dae8796a27 100644
--- a/src/mainboard/google/slippy/chromeos.fmd
+++ b/src/mainboard/google/slippy/chromeos.fmd
@@ -1,4 +1,4 @@
-FLASH@0xff800000 0x800000 {
+FLASH 0x800000 {
 	SI_ALL@0x0 0x200000 {
 		SI_DESC@0x0 0x1000
 		SI_ME@0x1000 0x1ff000
diff --git a/src/mainboard/google/smaug/chromeos.fmd b/src/mainboard/google/smaug/chromeos.fmd
index 4b1ba1951b..545949b5a9 100644
--- a/src/mainboard/google/smaug/chromeos.fmd
+++ b/src/mainboard/google/smaug/chromeos.fmd
@@ -1,4 +1,4 @@
-FLASH@0x0 0x1000000 {
+FLASH 0x1000000 {
 	WP_RO@0x0 0x500000 {
 		RO_SECTION@0x0 0x4f0000 {
 			BOOTBLOCK@0 128K
diff --git a/src/mainboard/google/storm/chromeos.fmd b/src/mainboard/google/storm/chromeos.fmd
index 3a55bdcae4..4d3c91344a 100644
--- a/src/mainboard/google/storm/chromeos.fmd
+++ b/src/mainboard/google/storm/chromeos.fmd
@@ -1,4 +1,4 @@
-FLASH@0x0 0x800000 {
+FLASH 0x800000 {
 	WP_RO@0x0 0x400000 {
 		RO_SECTION@0x0 0x3e0000 {
 			BOOTBLOCK@0 128K
diff --git a/src/mainboard/google/stout/chromeos.fmd b/src/mainboard/google/stout/chromeos.fmd
index 93048a37ec..ef8ca78ff9 100644
--- a/src/mainboard/google/stout/chromeos.fmd
+++ b/src/mainboard/google/stout/chromeos.fmd
@@ -1,4 +1,4 @@
-FLASH@0xff800000 0x800000 {
+FLASH 0x800000 {
 	SI_ALL@0x0 0x200000 {
 		SI_DESC@0x0 0x1000
 		SI_ME@0x1000 0x1ff000
diff --git a/src/mainboard/google/trogdor/chromeos.fmd b/src/mainboard/google/trogdor/chromeos.fmd
index f6960761ef..aa311df65f 100644
--- a/src/mainboard/google/trogdor/chromeos.fmd
+++ b/src/mainboard/google/trogdor/chromeos.fmd
@@ -1,6 +1,6 @@
 ## SPDX-License-Identifier: GPL-2.0-only
 
-FLASH@0x0 8M {
+FLASH 8M {
 	WP_RO 4M {
 		RO_SECTION 0x3e4000 {
 			BOOTBLOCK 96K
diff --git a/src/mainboard/google/veyron/chromeos.fmd b/src/mainboard/google/veyron/chromeos.fmd
index df35976d00..9df6494e4c 100644
--- a/src/mainboard/google/veyron/chromeos.fmd
+++ b/src/mainboard/google/veyron/chromeos.fmd
@@ -1,4 +1,4 @@
-FLASH@0x0 0x400000 {
+FLASH 0x400000 {
 	WP_RO@0x0 0x200000 {
 		RO_SECTION@0x0 0x1f0000 {
 			BOOTBLOCK@0 128K
diff --git a/src/mainboard/google/veyron_mickey/chromeos.fmd b/src/mainboard/google/veyron_mickey/chromeos.fmd
index 76ab2c321f..882d098307 100644
--- a/src/mainboard/google/veyron_mickey/chromeos.fmd
+++ b/src/mainboard/google/veyron_mickey/chromeos.fmd
@@ -1,4 +1,4 @@
-FLASH@0x0 0x400000 {
+FLASH 0x400000 {
 	WP_RO@0x0 0x200000 {
 		RO_SECTION@0x0 0x1f0000 {
 			BOOTBLOCK@0 128K
diff --git a/src/mainboard/google/veyron_rialto/chromeos.fmd b/src/mainboard/google/veyron_rialto/chromeos.fmd
index df35976d00..9df6494e4c 100644
--- a/src/mainboard/google/veyron_rialto/chromeos.fmd
+++ b/src/mainboard/google/veyron_rialto/chromeos.fmd
@@ -1,4 +1,4 @@
-FLASH@0x0 0x400000 {
+FLASH 0x400000 {
 	WP_RO@0x0 0x200000 {
 		RO_SECTION@0x0 0x1f0000 {
 			BOOTBLOCK@0 128K
diff --git a/src/mainboard/google/zork/chromeos.fmd b/src/mainboard/google/zork/chromeos.fmd
index b405b2f4c7..c874c5657e 100644
--- a/src/mainboard/google/zork/chromeos.fmd
+++ b/src/mainboard/google/zork/chromeos.fmd
@@ -1,4 +1,4 @@
-FLASH@0xFF000000 16M {
+FLASH 16M {
 	SI_BIOS {
 		RW_MRC_CACHE(PRESERVE) 64K
 		RW_SECTION_A 3M {
diff --git a/src/mainboard/ibm/sbp1/board.fmd b/src/mainboard/ibm/sbp1/board.fmd
index 9f51f01272..904a7f4f50 100644
--- a/src/mainboard/ibm/sbp1/board.fmd
+++ b/src/mainboard/ibm/sbp1/board.fmd
@@ -1,4 +1,4 @@
-FLASH@0xfc000000 64M {
+FLASH 64M {
 	SI_ALL@0x0 0x03000000 {
 		SI_DESC@0x0 0x1000
 		SI_ME@0x1000 0x2fff000
diff --git a/src/mainboard/intel/avenuecity_crb/board.fmd b/src/mainboard/intel/avenuecity_crb/board.fmd
index df5bc059f4..d5a34a2b04 100644
--- a/src/mainboard/intel/avenuecity_crb/board.fmd
+++ b/src/mainboard/intel/avenuecity_crb/board.fmd
@@ -1,4 +1,4 @@
-FLASH@0xfc000000 64M {
+FLASH 64M {
 	SI_ALL 48M {
 		SI_DESC@0x0 0x1000
 	}
diff --git a/src/mainboard/intel/baskingridge/chromeos.fmd b/src/mainboard/intel/baskingridge/chromeos.fmd
index 9852a2209c..32e2ab1ff5 100644
--- a/src/mainboard/intel/baskingridge/chromeos.fmd
+++ b/src/mainboard/intel/baskingridge/chromeos.fmd
@@ -1,4 +1,4 @@
-FLASH@0xff800000 0x800000 {
+FLASH 0x800000 {
 	SI_ALL@0x0 0x180000 {
 		SI_DESC@0x0 0x1000
 		SI_ME@0x1000 0x17f000
diff --git a/src/mainboard/intel/beechnutcity_crb/board.fmd b/src/mainboard/intel/beechnutcity_crb/board.fmd
index df5bc059f4..d5a34a2b04 100644
--- a/src/mainboard/intel/beechnutcity_crb/board.fmd
+++ b/src/mainboard/intel/beechnutcity_crb/board.fmd
@@ -1,4 +1,4 @@
-FLASH@0xfc000000 64M {
+FLASH 64M {
 	SI_ALL 48M {
 		SI_DESC@0x0 0x1000
 	}
diff --git a/src/mainboard/intel/cedarisland_crb/board.fmd b/src/mainboard/intel/cedarisland_crb/board.fmd
index 2002f6e313..0b4c21a31f 100644
--- a/src/mainboard/intel/cedarisland_crb/board.fmd
+++ b/src/mainboard/intel/cedarisland_crb/board.fmd
@@ -1,4 +1,4 @@
-FLASH@0xfc000000 64M {
+FLASH 64M {
 	SI_ALL@0x0 0x2fe8000 {
 		SI_DESC@0x0 0x1000
 		SI_GBE@0x1000 0x2000
diff --git a/src/mainboard/intel/coffeelake_rvp/chromeos.fmd b/src/mainboard/intel/coffeelake_rvp/chromeos.fmd
index 39bd6c5237..da4e70e3ff 100644
--- a/src/mainboard/intel/coffeelake_rvp/chromeos.fmd
+++ b/src/mainboard/intel/coffeelake_rvp/chromeos.fmd
@@ -1,4 +1,4 @@
-FLASH@0xff000000 0x1000000 {
+FLASH 0x1000000 {
 	SI_ALL@0x0 0x380000 {
 		SI_DESC@0x0 0x1000
 		SI_EC@0x01000 0x80000
diff --git a/src/mainboard/intel/coffeelake_rvp/chromeos_32MB.fmd b/src/mainboard/intel/coffeelake_rvp/chromeos_32MB.fmd
index 62e0f5d6d1..d6977c1164 100644
--- a/src/mainboard/intel/coffeelake_rvp/chromeos_32MB.fmd
+++ b/src/mainboard/intel/coffeelake_rvp/chromeos_32MB.fmd
@@ -1,4 +1,4 @@
-FLASH@0xfe000000 0x2000000 {
+FLASH 0x2000000 {
 	SI_ALL@0x0 0x1081000 {
 		SI_DESC@0x0 0x1000
 		SI_EC@0x1000 0x80000
diff --git a/src/mainboard/intel/frost_creek/board.fmd b/src/mainboard/intel/frost_creek/board.fmd
index 5c22e12d52..a229b4a65b 100644
--- a/src/mainboard/intel/frost_creek/board.fmd
+++ b/src/mainboard/intel/frost_creek/board.fmd
@@ -1,4 +1,4 @@
-FLASH@0xfe000000 0x02000000 {
+FLASH 0x02000000 {
 	BIOS@0x01400000 0x00C00000 {
 		RW_MRC_CACHE 0x10000
 		SMMSTORE 0x40000
diff --git a/src/mainboard/intel/jasperlake_rvp/chromeos.fmd b/src/mainboard/intel/jasperlake_rvp/chromeos.fmd
index 4fe11debf2..ac5967ce7a 100644
--- a/src/mainboard/intel/jasperlake_rvp/chromeos.fmd
+++ b/src/mainboard/intel/jasperlake_rvp/chromeos.fmd
@@ -1,4 +1,4 @@
-FLASH@0xff000000 0x1000000 {
+FLASH 0x1000000 {
 	SI_ALL@0x0 0x381000 {
 		SI_DESC@0x0 0x1000
 		SI_EC@0x1000 0x80000
diff --git a/src/mainboard/intel/kblrvp/chromeos.fmd b/src/mainboard/intel/kblrvp/chromeos.fmd
index 9ba1bf7275..813271259a 100644
--- a/src/mainboard/intel/kblrvp/chromeos.fmd
+++ b/src/mainboard/intel/kblrvp/chromeos.fmd
@@ -1,4 +1,4 @@
-FLASH@0xff000000 0x1000000 {
+FLASH 0x1000000 {
 	SI_ALL@0x0 0x200000 {
 		SI_DESC@0x0 0x1000
 		SI_ME@0x1000 0x1ff000
diff --git a/src/mainboard/intel/kunimitsu/chromeos.fmd b/src/mainboard/intel/kunimitsu/chromeos.fmd
index 9ba1bf7275..813271259a 100644
--- a/src/mainboard/intel/kunimitsu/chromeos.fmd
+++ b/src/mainboard/intel/kunimitsu/chromeos.fmd
@@ -1,4 +1,4 @@
-FLASH@0xff000000 0x1000000 {
+FLASH 0x1000000 {
 	SI_ALL@0x0 0x200000 {
 		SI_DESC@0x0 0x1000
 		SI_ME@0x1000 0x1ff000
diff --git a/src/mainboard/intel/shadowmountain/chromeos.fmd b/src/mainboard/intel/shadowmountain/chromeos.fmd
index a4b8643874..6560d22276 100644
--- a/src/mainboard/intel/shadowmountain/chromeos.fmd
+++ b/src/mainboard/intel/shadowmountain/chromeos.fmd
@@ -1,4 +1,4 @@
-FLASH@0xfe000000 0x2000000 {
+FLASH 0x2000000 {
 	SI_ALL@0x0 0x1000000 {
 		SI_DESC@0x0 0x1000
 		SI_ME@0x1000 0xfff000
diff --git a/src/mainboard/intel/strago/chromeos.fmd b/src/mainboard/intel/strago/chromeos.fmd
index bc9bac3344..a41a8c1a41 100644
--- a/src/mainboard/intel/strago/chromeos.fmd
+++ b/src/mainboard/intel/strago/chromeos.fmd
@@ -1,4 +1,4 @@
-FLASH@0xff800000 0x800000 {
+FLASH 0x800000 {
 	SI_ALL@0x0 0x200000 {
 		SI_DESC@0x0 0x1000
 		SI_ME@0x1000 0x1ff000
diff --git a/src/mainboard/intel/tglrvp/chromeos.fmd b/src/mainboard/intel/tglrvp/chromeos.fmd
index 1e2e7920cf..78a825eccf 100644
--- a/src/mainboard/intel/tglrvp/chromeos.fmd
+++ b/src/mainboard/intel/tglrvp/chromeos.fmd
@@ -1,4 +1,4 @@
-FLASH@0xfe000000 0x2000000 {
+FLASH 0x2000000 {
 	SI_ALL@0x0 0x1000000 {
 		SI_DESC@0x0 0x1000
 		SI_EC@0x1000 0x80000
diff --git a/src/mainboard/intel/wtm2/chromeos.fmd b/src/mainboard/intel/wtm2/chromeos.fmd
index 9852a2209c..32e2ab1ff5 100644
--- a/src/mainboard/intel/wtm2/chromeos.fmd
+++ b/src/mainboard/intel/wtm2/chromeos.fmd
@@ -1,4 +1,4 @@
-FLASH@0xff800000 0x800000 {
+FLASH 0x800000 {
 	SI_ALL@0x0 0x180000 {
 		SI_DESC@0x0 0x1000
 		SI_ME@0x1000 0x17f000
diff --git a/src/mainboard/lenovo/haswell/vboot-ro-me_clean.fmd b/src/mainboard/lenovo/haswell/vboot-ro-me_clean.fmd
index 565cacd3a8..5101caa59c 100644
--- a/src/mainboard/lenovo/haswell/vboot-ro-me_clean.fmd
+++ b/src/mainboard/lenovo/haswell/vboot-ro-me_clean.fmd
@@ -1,4 +1,4 @@
-FLASH@0xff400000 0xc00000 {
+FLASH 0xc00000 {
 	SI_ALL 0x20000 {
 		SI_DESC 0x1000
 		SI_GBE 0x2000
diff --git a/src/mainboard/lenovo/haswell/vboot-ro.fmd b/src/mainboard/lenovo/haswell/vboot-ro.fmd
index 6bdd4cc458..027849bfe9 100644
--- a/src/mainboard/lenovo/haswell/vboot-ro.fmd
+++ b/src/mainboard/lenovo/haswell/vboot-ro.fmd
@@ -1,4 +1,4 @@
-FLASH@0xff400000 0xc00000 {
+FLASH 0xc00000 {
 	SI_ALL 0x500000 {
 		SI_DESC 0x1000
 		SI_GBE 0x2000
diff --git a/src/mainboard/lenovo/haswell/vboot-rwab.fmd b/src/mainboard/lenovo/haswell/vboot-rwab.fmd
index e38cd60c28..220d324c0c 100644
--- a/src/mainboard/lenovo/haswell/vboot-rwab.fmd
+++ b/src/mainboard/lenovo/haswell/vboot-rwab.fmd
@@ -1,4 +1,4 @@
-FLASH@0xff400000 0xc00000 {
+FLASH 0xc00000 {
 	SI_ALL@0x0 0x500000 {
 		SI_DESC@0x0 0x1000
 		SI_GBE@0x1000 0x2000
diff --git a/src/mainboard/lenovo/t400/vboot-rwa.fmd b/src/mainboard/lenovo/t400/vboot-rwa.fmd
index 4acae85e4c..c97c812032 100644
--- a/src/mainboard/lenovo/t400/vboot-rwa.fmd
+++ b/src/mainboard/lenovo/t400/vboot-rwa.fmd
@@ -1,4 +1,4 @@
-FLASH@0xff800000 0x800000 {
+FLASH 0x800000 {
 	SI_ALL@0x0 0x600000 {
 		SI_DESC@0x0 0x1000
 		SI_ME@0x1000 0x5f5000
diff --git a/src/mainboard/lenovo/t410/vboot-rwa.fmd b/src/mainboard/lenovo/t410/vboot-rwa.fmd
index b7d75c0910..bdb5c5822f 100644
--- a/src/mainboard/lenovo/t410/vboot-rwa.fmd
+++ b/src/mainboard/lenovo/t410/vboot-rwa.fmd
@@ -1,4 +1,4 @@
-FLASH@0xff800000 0x800000 {
+FLASH 0x800000 {
 	SI_ALL@0x0 0x500000 {
 		SI_DESC@0x0 0x1000
 		SI_GBE@0x1000 0x2000
diff --git a/src/mainboard/lenovo/t420/vboot-ro-me_clean.fmd b/src/mainboard/lenovo/t420/vboot-ro-me_clean.fmd
index d1cbff7a1b..5f490f8b2c 100644
--- a/src/mainboard/lenovo/t420/vboot-ro-me_clean.fmd
+++ b/src/mainboard/lenovo/t420/vboot-ro-me_clean.fmd
@@ -1,4 +1,4 @@
-FLASH@0xff800000 0x800000 {
+FLASH 0x800000 {
 	SI_ALL 0x20000 {
 		SI_DESC 0x1000
 		SI_GBE 0x2000
diff --git a/src/mainboard/lenovo/t420/vboot-ro.fmd b/src/mainboard/lenovo/t420/vboot-ro.fmd
index 51df8a5322..bbcbba57f6 100644
--- a/src/mainboard/lenovo/t420/vboot-ro.fmd
+++ b/src/mainboard/lenovo/t420/vboot-ro.fmd
@@ -1,4 +1,4 @@
-FLASH@0xff800000 0x800000 {
+FLASH 0x800000 {
 	SI_ALL 0x500000 {
 		SI_DESC 0x1000
 		SI_GBE 0x2000
diff --git a/src/mainboard/lenovo/t420/vboot-rwa.fmd b/src/mainboard/lenovo/t420/vboot-rwa.fmd
index 4bd4b86528..e951c83816 100644
--- a/src/mainboard/lenovo/t420/vboot-rwa.fmd
+++ b/src/mainboard/lenovo/t420/vboot-rwa.fmd
@@ -1,4 +1,4 @@
-FLASH@0xff800000 0x800000 {
+FLASH 0x800000 {
 	SI_ALL@0x0 0x500000 {
 		SI_DESC@0x0 0x1000
 		SI_GBE@0x1000 0x2000
diff --git a/src/mainboard/lenovo/t420s/vboot-ro-me_clean.fmd b/src/mainboard/lenovo/t420s/vboot-ro-me_clean.fmd
index d1cbff7a1b..5f490f8b2c 100644
--- a/src/mainboard/lenovo/t420s/vboot-ro-me_clean.fmd
+++ b/src/mainboard/lenovo/t420s/vboot-ro-me_clean.fmd
@@ -1,4 +1,4 @@
-FLASH@0xff800000 0x800000 {
+FLASH 0x800000 {
 	SI_ALL 0x20000 {
 		SI_DESC 0x1000
 		SI_GBE 0x2000
diff --git a/src/mainboard/lenovo/t420s/vboot-ro.fmd b/src/mainboard/lenovo/t420s/vboot-ro.fmd
index 51df8a5322..bbcbba57f6 100644
--- a/src/mainboard/lenovo/t420s/vboot-ro.fmd
+++ b/src/mainboard/lenovo/t420s/vboot-ro.fmd
@@ -1,4 +1,4 @@
-FLASH@0xff800000 0x800000 {
+FLASH 0x800000 {
 	SI_ALL 0x500000 {
 		SI_DESC 0x1000
 		SI_GBE 0x2000
diff --git a/src/mainboard/lenovo/t420s/vboot-rwa.fmd b/src/mainboard/lenovo/t420s/vboot-rwa.fmd
index 4bd4b86528..e951c83816 100644
--- a/src/mainboard/lenovo/t420s/vboot-rwa.fmd
+++ b/src/mainboard/lenovo/t420s/vboot-rwa.fmd
@@ -1,4 +1,4 @@
-FLASH@0xff800000 0x800000 {
+FLASH 0x800000 {
 	SI_ALL@0x0 0x500000 {
 		SI_DESC@0x0 0x1000
 		SI_GBE@0x1000 0x2000
diff --git a/src/mainboard/lenovo/t430/vboot-ro-me_clean.fmd b/src/mainboard/lenovo/t430/vboot-ro-me_clean.fmd
index 565cacd3a8..5101caa59c 100644
--- a/src/mainboard/lenovo/t430/vboot-ro-me_clean.fmd
+++ b/src/mainboard/lenovo/t430/vboot-ro-me_clean.fmd
@@ -1,4 +1,4 @@
-FLASH@0xff400000 0xc00000 {
+FLASH 0xc00000 {
 	SI_ALL 0x20000 {
 		SI_DESC 0x1000
 		SI_GBE 0x2000
diff --git a/src/mainboard/lenovo/t430/vboot-ro.fmd b/src/mainboard/lenovo/t430/vboot-ro.fmd
index 6bdd4cc458..027849bfe9 100644
--- a/src/mainboard/lenovo/t430/vboot-ro.fmd
+++ b/src/mainboard/lenovo/t430/vboot-ro.fmd
@@ -1,4 +1,4 @@
-FLASH@0xff400000 0xc00000 {
+FLASH 0xc00000 {
 	SI_ALL 0x500000 {
 		SI_DESC 0x1000
 		SI_GBE 0x2000
diff --git a/src/mainboard/lenovo/t430/vboot-rwab.fmd b/src/mainboard/lenovo/t430/vboot-rwab.fmd
index 13df4f6c67..8819959dfe 100644
--- a/src/mainboard/lenovo/t430/vboot-rwab.fmd
+++ b/src/mainboard/lenovo/t430/vboot-rwab.fmd
@@ -1,4 +1,4 @@
-FLASH@0xff400000 0xc00000 {
+FLASH 0xc00000 {
 	SI_ALL@0x0 0x500000 {
 		SI_DESC@0x0 0x1000
 		SI_GBE@0x1000 0x2000
diff --git a/src/mainboard/lenovo/t430s/vboot-ro-me_clean.fmd b/src/mainboard/lenovo/t430s/vboot-ro-me_clean.fmd
index 565cacd3a8..5101caa59c 100644
--- a/src/mainboard/lenovo/t430s/vboot-ro-me_clean.fmd
+++ b/src/mainboard/lenovo/t430s/vboot-ro-me_clean.fmd
@@ -1,4 +1,4 @@
-FLASH@0xff400000 0xc00000 {
+FLASH 0xc00000 {
 	SI_ALL 0x20000 {
 		SI_DESC 0x1000
 		SI_GBE 0x2000
diff --git a/src/mainboard/lenovo/t430s/vboot-ro.fmd b/src/mainboard/lenovo/t430s/vboot-ro.fmd
index 6bdd4cc458..027849bfe9 100644
--- a/src/mainboard/lenovo/t430s/vboot-ro.fmd
+++ b/src/mainboard/lenovo/t430s/vboot-ro.fmd
@@ -1,4 +1,4 @@
-FLASH@0xff400000 0xc00000 {
+FLASH 0xc00000 {
 	SI_ALL 0x500000 {
 		SI_DESC 0x1000
 		SI_GBE 0x2000
diff --git a/src/mainboard/lenovo/t430s/vboot-rwab.fmd b/src/mainboard/lenovo/t430s/vboot-rwab.fmd
index 13df4f6c67..8819959dfe 100644
--- a/src/mainboard/lenovo/t430s/vboot-rwab.fmd
+++ b/src/mainboard/lenovo/t430s/vboot-rwab.fmd
@@ -1,4 +1,4 @@
-FLASH@0xff400000 0xc00000 {
+FLASH 0xc00000 {
 	SI_ALL@0x0 0x500000 {
 		SI_DESC@0x0 0x1000
 		SI_GBE@0x1000 0x2000
diff --git a/src/mainboard/lenovo/t520/vboot-ro-me_clean.fmd b/src/mainboard/lenovo/t520/vboot-ro-me_clean.fmd
index d1cbff7a1b..5f490f8b2c 100644
--- a/src/mainboard/lenovo/t520/vboot-ro-me_clean.fmd
+++ b/src/mainboard/lenovo/t520/vboot-ro-me_clean.fmd
@@ -1,4 +1,4 @@
-FLASH@0xff800000 0x800000 {
+FLASH 0x800000 {
 	SI_ALL 0x20000 {
 		SI_DESC 0x1000
 		SI_GBE 0x2000
diff --git a/src/mainboard/lenovo/t520/vboot-ro.fmd b/src/mainboard/lenovo/t520/vboot-ro.fmd
index 51df8a5322..bbcbba57f6 100644
--- a/src/mainboard/lenovo/t520/vboot-ro.fmd
+++ b/src/mainboard/lenovo/t520/vboot-ro.fmd
@@ -1,4 +1,4 @@
-FLASH@0xff800000 0x800000 {
+FLASH 0x800000 {
 	SI_ALL 0x500000 {
 		SI_DESC 0x1000
 		SI_GBE 0x2000
diff --git a/src/mainboard/lenovo/t520/vboot-rwa.fmd b/src/mainboard/lenovo/t520/vboot-rwa.fmd
index 4bd4b86528..e951c83816 100644
--- a/src/mainboard/lenovo/t520/vboot-rwa.fmd
+++ b/src/mainboard/lenovo/t520/vboot-rwa.fmd
@@ -1,4 +1,4 @@
-FLASH@0xff800000 0x800000 {
+FLASH 0x800000 {
 	SI_ALL@0x0 0x500000 {
 		SI_DESC@0x0 0x1000
 		SI_GBE@0x1000 0x2000
diff --git a/src/mainboard/lenovo/t530/vboot-ro-me_clean.fmd b/src/mainboard/lenovo/t530/vboot-ro-me_clean.fmd
index 565cacd3a8..5101caa59c 100644
--- a/src/mainboard/lenovo/t530/vboot-ro-me_clean.fmd
+++ b/src/mainboard/lenovo/t530/vboot-ro-me_clean.fmd
@@ -1,4 +1,4 @@
-FLASH@0xff400000 0xc00000 {
+FLASH 0xc00000 {
 	SI_ALL 0x20000 {
 		SI_DESC 0x1000
 		SI_GBE 0x2000
diff --git a/src/mainboard/lenovo/t530/vboot-ro.fmd b/src/mainboard/lenovo/t530/vboot-ro.fmd
index 6bdd4cc458..027849bfe9 100644
--- a/src/mainboard/lenovo/t530/vboot-ro.fmd
+++ b/src/mainboard/lenovo/t530/vboot-ro.fmd
@@ -1,4 +1,4 @@
-FLASH@0xff400000 0xc00000 {
+FLASH 0xc00000 {
 	SI_ALL 0x500000 {
 		SI_DESC 0x1000
 		SI_GBE 0x2000
diff --git a/src/mainboard/lenovo/t530/vboot-rwab.fmd b/src/mainboard/lenovo/t530/vboot-rwab.fmd
index 13df4f6c67..8819959dfe 100644
--- a/src/mainboard/lenovo/t530/vboot-rwab.fmd
+++ b/src/mainboard/lenovo/t530/vboot-rwab.fmd
@@ -1,4 +1,4 @@
-FLASH@0xff400000 0xc00000 {
+FLASH 0xc00000 {
 	SI_ALL@0x0 0x500000 {
 		SI_DESC@0x0 0x1000
 		SI_GBE@0x1000 0x2000
diff --git a/src/mainboard/lenovo/x131e/vboot-ro-me_clean.fmd b/src/mainboard/lenovo/x131e/vboot-ro-me_clean.fmd
index 565cacd3a8..5101caa59c 100644
--- a/src/mainboard/lenovo/x131e/vboot-ro-me_clean.fmd
+++ b/src/mainboard/lenovo/x131e/vboot-ro-me_clean.fmd
@@ -1,4 +1,4 @@
-FLASH@0xff400000 0xc00000 {
+FLASH 0xc00000 {
 	SI_ALL 0x20000 {
 		SI_DESC 0x1000
 		SI_GBE 0x2000
diff --git a/src/mainboard/lenovo/x131e/vboot-ro.fmd b/src/mainboard/lenovo/x131e/vboot-ro.fmd
index 6bdd4cc458..027849bfe9 100644
--- a/src/mainboard/lenovo/x131e/vboot-ro.fmd
+++ b/src/mainboard/lenovo/x131e/vboot-ro.fmd
@@ -1,4 +1,4 @@
-FLASH@0xff400000 0xc00000 {
+FLASH 0xc00000 {
 	SI_ALL 0x500000 {
 		SI_DESC 0x1000
 		SI_GBE 0x2000
diff --git a/src/mainboard/lenovo/x131e/vboot-rwab.fmd b/src/mainboard/lenovo/x131e/vboot-rwab.fmd
index 13df4f6c67..8819959dfe 100644
--- a/src/mainboard/lenovo/x131e/vboot-rwab.fmd
+++ b/src/mainboard/lenovo/x131e/vboot-rwab.fmd
@@ -1,4 +1,4 @@
-FLASH@0xff400000 0xc00000 {
+FLASH 0xc00000 {
 	SI_ALL@0x0 0x500000 {
 		SI_DESC@0x0 0x1000
 		SI_GBE@0x1000 0x2000
diff --git a/src/mainboard/lenovo/x1_carbon_gen1/vboot-ro-me_clean.fmd b/src/mainboard/lenovo/x1_carbon_gen1/vboot-ro-me_clean.fmd
index 565cacd3a8..5101caa59c 100644
--- a/src/mainboard/lenovo/x1_carbon_gen1/vboot-ro-me_clean.fmd
+++ b/src/mainboard/lenovo/x1_carbon_gen1/vboot-ro-me_clean.fmd
@@ -1,4 +1,4 @@
-FLASH@0xff400000 0xc00000 {
+FLASH 0xc00000 {
 	SI_ALL 0x20000 {
 		SI_DESC 0x1000
 		SI_GBE 0x2000
diff --git a/src/mainboard/lenovo/x1_carbon_gen1/vboot-ro.fmd b/src/mainboard/lenovo/x1_carbon_gen1/vboot-ro.fmd
index 6bdd4cc458..027849bfe9 100644
--- a/src/mainboard/lenovo/x1_carbon_gen1/vboot-ro.fmd
+++ b/src/mainboard/lenovo/x1_carbon_gen1/vboot-ro.fmd
@@ -1,4 +1,4 @@
-FLASH@0xff400000 0xc00000 {
+FLASH 0xc00000 {
 	SI_ALL 0x500000 {
 		SI_DESC 0x1000
 		SI_GBE 0x2000
diff --git a/src/mainboard/lenovo/x1_carbon_gen1/vboot-rwab.fmd b/src/mainboard/lenovo/x1_carbon_gen1/vboot-rwab.fmd
index 13df4f6c67..8819959dfe 100644
--- a/src/mainboard/lenovo/x1_carbon_gen1/vboot-rwab.fmd
+++ b/src/mainboard/lenovo/x1_carbon_gen1/vboot-rwab.fmd
@@ -1,4 +1,4 @@
-FLASH@0xff400000 0xc00000 {
+FLASH 0xc00000 {
 	SI_ALL@0x0 0x500000 {
 		SI_DESC@0x0 0x1000
 		SI_GBE@0x1000 0x2000
diff --git a/src/mainboard/lenovo/x200/vboot-rwa.fmd b/src/mainboard/lenovo/x200/vboot-rwa.fmd
index 4acae85e4c..c97c812032 100644
--- a/src/mainboard/lenovo/x200/vboot-rwa.fmd
+++ b/src/mainboard/lenovo/x200/vboot-rwa.fmd
@@ -1,4 +1,4 @@
-FLASH@0xff800000 0x800000 {
+FLASH 0x800000 {
 	SI_ALL@0x0 0x600000 {
 		SI_DESC@0x0 0x1000
 		SI_ME@0x1000 0x5f5000
diff --git a/src/mainboard/lenovo/x201/vboot-rwa.fmd b/src/mainboard/lenovo/x201/vboot-rwa.fmd
index f3c0042418..d7982a0156 100644
--- a/src/mainboard/lenovo/x201/vboot-rwa.fmd
+++ b/src/mainboard/lenovo/x201/vboot-rwa.fmd
@@ -1,4 +1,4 @@
-FLASH@0xff800000 0x800000 {
+FLASH 0x800000 {
 	SI_ALL@0x0 0x500000 {
 		SI_DESC@0x0 0x1000
 		SI_GBE@0x1000 0x2000
diff --git a/src/mainboard/lenovo/x220/vboot-ro-me_clean.fmd b/src/mainboard/lenovo/x220/vboot-ro-me_clean.fmd
index d1cbff7a1b..5f490f8b2c 100644
--- a/src/mainboard/lenovo/x220/vboot-ro-me_clean.fmd
+++ b/src/mainboard/lenovo/x220/vboot-ro-me_clean.fmd
@@ -1,4 +1,4 @@
-FLASH@0xff800000 0x800000 {
+FLASH 0x800000 {
 	SI_ALL 0x20000 {
 		SI_DESC 0x1000
 		SI_GBE 0x2000
diff --git a/src/mainboard/lenovo/x220/vboot-ro.fmd b/src/mainboard/lenovo/x220/vboot-ro.fmd
index 51df8a5322..bbcbba57f6 100644
--- a/src/mainboard/lenovo/x220/vboot-ro.fmd
+++ b/src/mainboard/lenovo/x220/vboot-ro.fmd
@@ -1,4 +1,4 @@
-FLASH@0xff800000 0x800000 {
+FLASH 0x800000 {
 	SI_ALL 0x500000 {
 		SI_DESC 0x1000
 		SI_GBE 0x2000
diff --git a/src/mainboard/lenovo/x220/vboot-rwa.fmd b/src/mainboard/lenovo/x220/vboot-rwa.fmd
index 4bd4b86528..e951c83816 100644
--- a/src/mainboard/lenovo/x220/vboot-rwa.fmd
+++ b/src/mainboard/lenovo/x220/vboot-rwa.fmd
@@ -1,4 +1,4 @@
-FLASH@0xff800000 0x800000 {
+FLASH 0x800000 {
 	SI_ALL@0x0 0x500000 {
 		SI_DESC@0x0 0x1000
 		SI_GBE@0x1000 0x2000
diff --git a/src/mainboard/lenovo/x230/vboot-ro-me_clean.fmd b/src/mainboard/lenovo/x230/vboot-ro-me_clean.fmd
index 565cacd3a8..5101caa59c 100644
--- a/src/mainboard/lenovo/x230/vboot-ro-me_clean.fmd
+++ b/src/mainboard/lenovo/x230/vboot-ro-me_clean.fmd
@@ -1,4 +1,4 @@
-FLASH@0xff400000 0xc00000 {
+FLASH 0xc00000 {
 	SI_ALL 0x20000 {
 		SI_DESC 0x1000
 		SI_GBE 0x2000
diff --git a/src/mainboard/lenovo/x230/vboot-ro.fmd b/src/mainboard/lenovo/x230/vboot-ro.fmd
index 6bdd4cc458..027849bfe9 100644
--- a/src/mainboard/lenovo/x230/vboot-ro.fmd
+++ b/src/mainboard/lenovo/x230/vboot-ro.fmd
@@ -1,4 +1,4 @@
-FLASH@0xff400000 0xc00000 {
+FLASH 0xc00000 {
 	SI_ALL 0x500000 {
 		SI_DESC 0x1000
 		SI_GBE 0x2000
diff --git a/src/mainboard/lenovo/x230/vboot-rwab.fmd b/src/mainboard/lenovo/x230/vboot-rwab.fmd
index 13df4f6c67..8819959dfe 100644
--- a/src/mainboard/lenovo/x230/vboot-rwab.fmd
+++ b/src/mainboard/lenovo/x230/vboot-rwab.fmd
@@ -1,4 +1,4 @@
-FLASH@0xff400000 0xc00000 {
+FLASH 0xc00000 {
 	SI_ALL@0x0 0x500000 {
 		SI_DESC@0x0 0x1000
 		SI_GBE@0x1000 0x2000
diff --git a/src/mainboard/lenovo/x60/vboot-rwa.fmd b/src/mainboard/lenovo/x60/vboot-rwa.fmd
index eabae66908..47424d500f 100644
--- a/src/mainboard/lenovo/x60/vboot-rwa.fmd
+++ b/src/mainboard/lenovo/x60/vboot-rwa.fmd
@@ -1,4 +1,4 @@
-FLASH@0xffe00000 0x200000 {
+FLASH 0x200000 {
 	BIOS {
 		RW_SECTION_A 0x100000 {
 			VBLOCK_A 0x10000
diff --git a/src/mainboard/opencellular/elgon/board.fmd b/src/mainboard/opencellular/elgon/board.fmd
index 222490c0e3..1f411aae2f 100644
--- a/src/mainboard/opencellular/elgon/board.fmd
+++ b/src/mainboard/opencellular/elgon/board.fmd
@@ -1,4 +1,4 @@
-FLASH@0x0 16M {
+FLASH 16M {
 	WP_RO@0x0 0x1000000 {
 		RO_SECTION@0x0 0xffc000 {
 			# 0 - 0x10000 is free for firmware usage.
diff --git a/src/mainboard/opencellular/elgon/vboot.fmd b/src/mainboard/opencellular/elgon/vboot.fmd
index 77ef10d046..f270b90c0b 100644
--- a/src/mainboard/opencellular/elgon/vboot.fmd
+++ b/src/mainboard/opencellular/elgon/vboot.fmd
@@ -1,4 +1,4 @@
-FLASH@0x0 16M {
+FLASH 16M {
 	# must use a power of two in MiB for WP_RO
 	WP_RO@0x0 0x400000 {
 		RO_SECTION@0x0 0x3fc000 {
diff --git a/src/mainboard/protectli/vault_adl_p/vboot-rwa.fmd b/src/mainboard/protectli/vault_adl_p/vboot-rwa.fmd
index 65b52d97f5..00b34b1c25 100644
--- a/src/mainboard/protectli/vault_adl_p/vboot-rwa.fmd
+++ b/src/mainboard/protectli/vault_adl_p/vboot-rwa.fmd
@@ -1,4 +1,4 @@
-FLASH@0xff000000 16M {
+FLASH 16M {
 	SI_ALL@0x0 {
 		SI_DESC 4K
 		SI_ME 0x4c0000
diff --git a/src/mainboard/protectli/vault_cml/board.fmd b/src/mainboard/protectli/vault_cml/board.fmd
index 37ec01e6ef..e7f40917ac 100644
--- a/src/mainboard/protectli/vault_cml/board.fmd
+++ b/src/mainboard/protectli/vault_cml/board.fmd
@@ -1,4 +1,4 @@
-FLASH@0xff000000 0x1000000 {
+FLASH 0x1000000 {
 	SI_ALL 6M {
 		SI_DESC 4K
 		SI_ME
diff --git a/src/mainboard/protectli/vault_cml/vboot-rwa.fmd b/src/mainboard/protectli/vault_cml/vboot-rwa.fmd
index b5c233f383..39a497e424 100644
--- a/src/mainboard/protectli/vault_cml/vboot-rwa.fmd
+++ b/src/mainboard/protectli/vault_cml/vboot-rwa.fmd
@@ -1,4 +1,4 @@
-FLASH@0xff000000 0x1000000 {
+FLASH 0x1000000 {
 	SI_ALL 6M {
 		SI_DESC 4K
 		SI_ME
diff --git a/src/mainboard/samsung/lumpy/chromeos.fmd b/src/mainboard/samsung/lumpy/chromeos.fmd
index 051cfd1a2e..32dfae948c 100644
--- a/src/mainboard/samsung/lumpy/chromeos.fmd
+++ b/src/mainboard/samsung/lumpy/chromeos.fmd
@@ -1,4 +1,4 @@
-FLASH@0xff800000 0x800000 {
+FLASH 0x800000 {
 	SI_ALL@0x0 0x180000 {
 		SI_DESC@0x0 0x1000
 		SI_ME@0x1000 0x17f000
diff --git a/src/mainboard/samsung/stumpy/chromeos.fmd b/src/mainboard/samsung/stumpy/chromeos.fmd
index 051cfd1a2e..32dfae948c 100644
--- a/src/mainboard/samsung/stumpy/chromeos.fmd
+++ b/src/mainboard/samsung/stumpy/chromeos.fmd
@@ -1,4 +1,4 @@
-FLASH@0xff800000 0x800000 {
+FLASH 0x800000 {
 	SI_ALL@0x0 0x180000 {
 		SI_DESC@0x0 0x1000
 		SI_ME@0x1000 0x17f000
diff --git a/src/mainboard/siemens/fa_ehl/fa_ehl.fmd b/src/mainboard/siemens/fa_ehl/fa_ehl.fmd
index 78faf2b107..8196ece26d 100644
--- a/src/mainboard/siemens/fa_ehl/fa_ehl.fmd
+++ b/src/mainboard/siemens/fa_ehl/fa_ehl.fmd
@@ -1,4 +1,4 @@
-FLASH @0xff000000 CONFIG_ROM_SIZE {
+FLASH CONFIG_ROM_SIZE {
 	SI_ALL 0x400000 {
 		SI_DESC 0x1000
 		SI_ME 0x3ff000
diff --git a/src/mainboard/siemens/mc_ehl/mc_ehl.fmd b/src/mainboard/siemens/mc_ehl/mc_ehl.fmd
index 78faf2b107..8196ece26d 100644
--- a/src/mainboard/siemens/mc_ehl/mc_ehl.fmd
+++ b/src/mainboard/siemens/mc_ehl/mc_ehl.fmd
@@ -1,4 +1,4 @@
-FLASH @0xff000000 CONFIG_ROM_SIZE {
+FLASH CONFIG_ROM_SIZE {
 	SI_ALL 0x400000 {
 		SI_DESC 0x1000
 		SI_ME 0x3ff000
diff --git a/src/mainboard/ti/beaglebone/board.fmd b/src/mainboard/ti/beaglebone/board.fmd
index 26a210f62d..42a9214f61 100644
--- a/src/mainboard/ti/beaglebone/board.fmd
+++ b/src/mainboard/ti/beaglebone/board.fmd
@@ -1,4 +1,4 @@
-FLASH@0x000 32M {
+FLASH 32M {
     BIOS@0x0 109K {
         BOOTBLOCK@0x0 22K
     }
diff --git a/src/soc/amd/glinda/Makefile.mk b/src/soc/amd/glinda/Makefile.mk
index 7f48581fec..d451199219 100644
--- a/src/soc/amd/glinda/Makefile.mk
+++ b/src/soc/amd/glinda/Makefile.mk
@@ -57,6 +57,7 @@ GLINDA_FW_A_POSITION=$(call int-add, \
 
 GLINDA_FW_B_POSITION=$(call int-add, \
 	$(call get_fmap_value,FMAP_SECTION_FW_MAIN_B_START) $(AMD_FW_AB_POSITION))
+
 #
 # PSP Directory Table items
 #
@@ -144,12 +145,8 @@ PSP_VERSTAGE_SIG_FILE=$(call strip_quotes,$(CONFIG_PSP_VERSTAGE_SIGNING_TOKEN))
 endif # CONFIG_VBOOT_STARTS_BEFORE_BOOTBLOCK
 
 ifeq ($(CONFIG_SEPARATE_SIGNED_PSPFW),y)
-SIGNED_AMDFW_A_POSITION=$(call int-subtract, \
-	$(call get_fmap_value,FMAP_SECTION_SIGNED_AMDFW_A_START) \
-	$(call get_fmap_value,FMAP_SECTION_FLASH_START))
-SIGNED_AMDFW_B_POSITION=$(call int-subtract, \
-	$(call get_fmap_value,FMAP_SECTION_SIGNED_AMDFW_B_START) \
-	$(call get_fmap_value,FMAP_SECTION_FLASH_START))
+SIGNED_AMDFW_A_POSITION=$(call get_fmap_value,FMAP_SECTION_SIGNED_AMDFW_A_START)
+SIGNED_AMDFW_B_POSITION=$(call get_fmap_value,FMAP_SECTION_SIGNED_AMDFW_B_START)
 SIGNED_AMDFW_A_FILE=$(obj)/amdfw_a.rom.signed
 SIGNED_AMDFW_B_FILE=$(obj)/amdfw_b.rom.signed
 endif # CONFIG_SEPARATE_SIGNED_PSPFW
diff --git a/src/soc/amd/mendocino/Makefile.mk b/src/soc/amd/mendocino/Makefile.mk
index 4236894af9..69578d11f9 100644
--- a/src/soc/amd/mendocino/Makefile.mk
+++ b/src/soc/amd/mendocino/Makefile.mk
@@ -52,10 +52,10 @@ AMD_FW_AB_POSITION := 0x40
 endif # ($(CONFIG_CBFS_VERIFICATION), y)
 
 MENDOCINO_FW_A_POSITION=$(call int-add, \
-	$(call get_fmap_value,FMAP_SECTION_FW_MAIN_A_START) $(AMD_FW_AB_POSITION))
+	$(call get_fmap_value,FMAP_SECTION_FW_MAIN_A_START) $(AMD_FW_AB_POSITION)) \
 
 MENDOCINO_FW_B_POSITION=$(call int-add, \
-	$(call get_fmap_value,FMAP_SECTION_FW_MAIN_B_START) $(AMD_FW_AB_POSITION))
+	$(call get_fmap_value,FMAP_SECTION_FW_MAIN_B_START) $(AMD_FW_AB_POSITION)) \
 
 MENDOCINO_FW_BODY_OFFSET := 0x100
 
@@ -157,12 +157,8 @@ PSP_VERSTAGE_SIG_FILE=$(call strip_quotes,$(CONFIG_PSP_VERSTAGE_SIGNING_TOKEN))
 endif # CONFIG_VBOOT_STARTS_BEFORE_BOOTBLOCK
 
 ifeq ($(CONFIG_SEPARATE_SIGNED_PSPFW),y)
-SIGNED_AMDFW_A_POSITION=$(call int-subtract, \
-	$(call get_fmap_value,FMAP_SECTION_SIGNED_AMDFW_A_START) \
-	$(call get_fmap_value,FMAP_SECTION_FLASH_START))
-SIGNED_AMDFW_B_POSITION=$(call int-subtract, \
-	$(call get_fmap_value,FMAP_SECTION_SIGNED_AMDFW_B_START) \
-	$(call get_fmap_value,FMAP_SECTION_FLASH_START))
+SIGNED_AMDFW_A_POSITION=$(call get_fmap_value,FMAP_SECTION_SIGNED_AMDFW_A_START)
+SIGNED_AMDFW_B_POSITION=$(call get_fmap_value,FMAP_SECTION_SIGNED_AMDFW_B_START)
 SIGNED_AMDFW_A_FILE=$(obj)/amdfw_a.rom.body.signed
 SIGNED_AMDFW_B_FILE=$(obj)/amdfw_b.rom.body.signed
 endif # CONFIG_SEPARATE_SIGNED_PSPFW
diff --git a/src/soc/amd/phoenix/Makefile.mk b/src/soc/amd/phoenix/Makefile.mk
index 7713fad5d5..2766e0eb53 100644
--- a/src/soc/amd/phoenix/Makefile.mk
+++ b/src/soc/amd/phoenix/Makefile.mk
@@ -65,8 +65,6 @@ PHOENIX_FW_A_POSITION=$(call int-add, \
 PHOENIX_FW_B_POSITION=$(call int-add, \
 	$(call get_fmap_value,FMAP_SECTION_FW_MAIN_B_START) $(AMD_FW_AB_POSITION))
 
-FMAP_FLASH_START=$(call get_fmap_value,FMAP_SECTION_FLASH_START)
-
 #
 # PSP Directory Table items
 #
@@ -138,15 +136,13 @@ ifneq ($(CONFIG_SOC_AMD_COMMON_BLOCK_APOB_NV_DISABLE),y)
 # type = 0x63 - construct APOB NV base/size from flash map
 # The flashmap section used for this is expected to be named RW_MRC_CACHE
 APOB_NV_SIZE=$(call get_fmap_value,FMAP_SECTION_RW_MRC_CACHE_SIZE)
-APOB_NV_BASE=$(call _tohex,$(call int-subtract, \
-	$(call get_fmap_value,FMAP_SECTION_RW_MRC_CACHE_START) $(FMAP_FLASH_START)))
+APOB_NV_BASE=$(call get_fmap_value,FMAP_SECTION_RW_MRC_CACHE_START)
 
 ifeq ($(CONFIG_HAS_RECOVERY_MRC_CACHE)$(CONFIG_VBOOT),yy)
 # On boards with recovery MRC cache, point type 0x63 entry to RECOVERY_MRC_CACHE.
 # Else use RW_MRC_CACHE. This entry will be added in the RO section.
 APOB_NV_RO_SIZE=$(call get_fmap_value,FMAP_SECTION_RECOVERY_MRC_CACHE_SIZE)
-APOB_NV_RO_BASE=$(call _tohex,$(call int-subtract, \
-	$(call get_fmap_value,FMAP_SECTION_RECOVERY_MRC_CACHE_START) $(FMAP_FLASH_START)))
+APOB_NV_RO_BASE=$(call get_fmap_value,FMAP_SECTION_RECOVERY_MRC_CACHE_START)
 else
 APOB_NV_RO_SIZE=$(APOB_NV_SIZE)
 APOB_NV_RO_BASE=$(APOB_NV_BASE)
@@ -170,10 +166,8 @@ PSP_VERSTAGE_SIG_FILE=$(call strip_quotes,$(CONFIG_PSP_VERSTAGE_SIGNING_TOKEN))
 endif # CONFIG_VBOOT_STARTS_BEFORE_BOOTBLOCK
 
 ifeq ($(CONFIG_SEPARATE_SIGNED_PSPFW),y)
-SIGNED_AMDFW_A_POSITION=$(call int-subtract, \
-	$(call get_fmap_value,FMAP_SECTION_SIGNED_AMDFW_A_START) $(FMAP_FLASH_START))
-SIGNED_AMDFW_B_POSITION=$(call int-subtract, \
-	$(call get_fmap_value,FMAP_SECTION_SIGNED_AMDFW_B_START) $(FMAP_FLASH_START))
+SIGNED_AMDFW_A_POSITION=$(call get_fmap_value,FMAP_SECTION_SIGNED_AMDFW_A_START)
+SIGNED_AMDFW_B_POSITION=$(call get_fmap_value,FMAP_SECTION_SIGNED_AMDFW_B_START)
 SIGNED_AMDFW_A_FILE=$(obj)/amdfw_a.rom.signed
 SIGNED_AMDFW_B_FILE=$(obj)/amdfw_b.rom.signed
 endif # CONFIG_SEPARATE_SIGNED_PSPFW
diff --git a/util/amdfwtool/amdfwread.c b/util/amdfwtool/amdfwread.c
index 711b1582fd..ca61571602 100644
--- a/util/amdfwtool/amdfwread.c
+++ b/util/amdfwtool/amdfwread.c
@@ -8,10 +8,6 @@
 #include <unistd.h>
 #include "amdfwtool.h"
 
-/* An address can be relative to the image/file start but it can also be the address when
- * the image is mapped at 0xff000000. Used to ensure that we only attempt to read within
- * the limits of the file. */
-#define SPI_ROM_BASE 0xff000000
 #define FILE_REL_MASK 0xffffff
 
 #define ERR(...) fprintf(stderr, __VA_ARGS__)
diff --git a/util/amdfwtool/amdfwtool.h b/util/amdfwtool/amdfwtool.h
index 24a7dd3bf0..70b2600f5c 100644
--- a/util/amdfwtool/amdfwtool.h
+++ b/util/amdfwtool/amdfwtool.h
@@ -9,6 +9,11 @@
 #include <stdint.h>
 #include <stdbool.h>
 
+/* An address can be relative to the image/file start but it can also be the address when
+ * the image is mapped at 0xff000000. Used to ensure that we only attempt to read within
+ * the limits of the file. */
+#define SPI_ROM_BASE 0xff000000
+
 #define ERASE_ALIGNMENT 0x1000U
 #define TABLE_ALIGNMENT 0x1000U
 #define TABLE_L2_SIZE_MAX 0x400U
diff --git a/util/amdfwtool/data_parse.c b/util/amdfwtool/data_parse.c
index 154d34dc6a..4a368f8b3c 100644
--- a/util/amdfwtool/data_parse.c
+++ b/util/amdfwtool/data_parse.c
@@ -734,6 +734,30 @@ bool needs_ish(enum platform platform_type)
 		return false;
 }
 
+/*
+ * For some SOC generations the APOB_NV binary seems to be treated special regarding the
+ * interpretaion of the source address. No matter the address_mode specified for the address
+ * the memory ABL always seems to the interpret the source address as MMIO address even if
+ * AMD_ADDR_REL_BIOS is specified. So for them we need to always use an MMIO address.
+ * This seems to be a bug which affects all SOCs before phoenix generation.
+ */
+static bool has_apob_nv_quirk(enum platform platform_type)
+{
+	switch (platform_type) {
+	case PLATFORM_CARRIZO:
+	case PLATFORM_STONEYRIDGE:
+	case PLATFORM_RAVEN:
+	case PLATFORM_PICASSO:
+	case PLATFORM_RENOIR:
+	case PLATFORM_CEZANNE:
+	case PLATFORM_MENDOCINO:
+	case PLATFORM_LUCIENNE:
+		return true;
+	default:
+		return false;
+	}
+}
+
 static bool is_second_gen(enum platform platform_type)
 {
 	switch (platform_type) {
@@ -804,6 +828,16 @@ uint8_t process_config(FILE *config, amd_cb_config *cb_config)
 
 	cb_config->second_gen = is_second_gen(cb_config->soc_id);
 
+	if (has_apob_nv_quirk(cb_config->soc_id)) {
+		for (int i = 0; amd_bios_table[i].type != AMD_BIOS_INVALID; i++) {
+			amd_bios_entry *entry = &amd_bios_table[i];
+			//TODO once ROM3 mapping (>16MiB) is possible, this needs to be updated.
+			if (entry->type == AMD_BIOS_APOB_NV && entry->size > 0) {
+				entry->src += SPI_ROM_BASE; // convert to MMIO address
+			}
+		}
+	}
+
 	if (needs_ish(cb_config->soc_id))
 		cb_config->need_ish = true;
 
diff --git a/util/amdfwtool/opts.c b/util/amdfwtool/opts.c
index 62bbc97ae5..5d1ee6754d 100644
--- a/util/amdfwtool/opts.c
+++ b/util/amdfwtool/opts.c
@@ -524,7 +524,7 @@ int amdfwtool_getopt(int argc, char *argv[], amd_cb_config *cb_config, context *
 			sub = instance = 0;
 			break;
 		case AMDFW_OPT_SIGNED_ADDR:
-			cb_config->signed_start_addr = strtoull(optarg, NULL, 10);
+			cb_config->signed_start_addr = strtoull(optarg, NULL, 16);
 			sub = instance = 0;
 			break;
 		case LONGOPT_SPI_READ_MODE:
diff --git a/util/cbfstool/default-x86.fmd b/util/cbfstool/default-x86.fmd
index f008889fef..795e025f9f 100644
--- a/util/cbfstool/default-x86.fmd
+++ b/util/cbfstool/default-x86.fmd
@@ -7,7 +7,7 @@
 # | CBFS        |
 # +-------------+ <-- 4GB / end of flash
 
-FLASH@##ROM_BASE## ##ROM_SIZE## {
+FLASH ##ROM_SIZE## {
 	BIOS@##BIOS_BASE## ##BIOS_SIZE## {
 		##CONSOLE_ENTRY##
 		##MRC_CACHE_ENTRY##
diff --git a/util/cbfstool/default.fmd b/util/cbfstool/default.fmd
index 8f4819ebf9..d20789f404 100644
--- a/util/cbfstool/default.fmd
+++ b/util/cbfstool/default.fmd
@@ -9,7 +9,7 @@
 # | CBFS        |
 # +-------------+ <-- ROM_SIZE
 
-FLASH@##ROM_BASE## ##ROM_SIZE## {
+FLASH ##ROM_SIZE## {
 	BIOS@##BIOS_BASE## ##BIOS_SIZE## {
 		BOOTBLOCK 128K
 		FMAP@##FMAP_BASE## ##FMAP_SIZE##

From da5f4de090a5384111f7489b8968abbfab1c303a Mon Sep 17 00:00:00 2001
From: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com>
Date: Wed, 26 Mar 2025 14:31:54 +0900
Subject: [PATCH 0681/3886] mb/google/nissa/var/meliks: Replace SPD for RAMID 2
 with Samsung K3KL8L80CM-MGCT

Meliks cannot use Samsung K3KL8L80DM-MGCU memory part since Twin Lake
platform can only support memory parts that support 8B mode but this
part doesn't support it.

So we would replace the usage of RAMID 2 (b'0010) with the SPD for this
part which supports 8B mode.

- Samsung K3KL8L80CM-MGCT

BUG=b:402600450
BRANCH=nissa
TEST=FW_NAME=meliks emerge-nissa coreboot

Change-Id: I7c05b79ca018f68260e71d4f749ecb8573987358
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87002
Reviewed-by: NyeonWoo Kim
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Jayvik Desai <jayvik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
---
 src/mainboard/google/brya/variants/meliks/memory/Makefile.mk    | 2 +-
 .../google/brya/variants/meliks/memory/dram_id.generated.txt    | 2 +-
 .../google/brya/variants/meliks/memory/mem_parts_used.txt       | 2 +-
 3 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/src/mainboard/google/brya/variants/meliks/memory/Makefile.mk b/src/mainboard/google/brya/variants/meliks/memory/Makefile.mk
index 1f7a706678..fcf05a1bee 100644
--- a/src/mainboard/google/brya/variants/meliks/memory/Makefile.mk
+++ b/src/mainboard/google/brya/variants/meliks/memory/Makefile.mk
@@ -6,4 +6,4 @@
 SPD_SOURCES =
 SPD_SOURCES += spd/lp5/set-0/spd-9.hex      # ID = 0(0b0000)  Parts = K3KL6L60GM-MGCT
 SPD_SOURCES += spd/lp5/set-0/spd-1.hex      # ID = 1(0b0001)  Parts = MT62F512M32D2DR-031 WT:B
-SPD_SOURCES += spd/lp5/set-0/spd-11.hex      # ID = 2(0b0010)  Parts = K3KL8L80DM-MGCU
+SPD_SOURCES += spd/lp5/set-0/spd-7.hex      # ID = 2(0b0010)  Parts = K3KL8L80CM-MGCT
diff --git a/src/mainboard/google/brya/variants/meliks/memory/dram_id.generated.txt b/src/mainboard/google/brya/variants/meliks/memory/dram_id.generated.txt
index 5ca8b34c83..06108bd87a 100644
--- a/src/mainboard/google/brya/variants/meliks/memory/dram_id.generated.txt
+++ b/src/mainboard/google/brya/variants/meliks/memory/dram_id.generated.txt
@@ -6,4 +6,4 @@
 DRAM Part Name                 ID to assign
 K3KL6L60GM-MGCT                0 (0000)
 MT62F512M32D2DR-031 WT:B       1 (0001)
-K3KL8L80DM-MGCU                2 (0010)
+K3KL8L80CM-MGCT                2 (0010)
diff --git a/src/mainboard/google/brya/variants/meliks/memory/mem_parts_used.txt b/src/mainboard/google/brya/variants/meliks/memory/mem_parts_used.txt
index cb07b5236e..7566a29fda 100644
--- a/src/mainboard/google/brya/variants/meliks/memory/mem_parts_used.txt
+++ b/src/mainboard/google/brya/variants/meliks/memory/mem_parts_used.txt
@@ -11,4 +11,4 @@
 # Part Name
 K3KL6L60GM-MGCT
 MT62F512M32D2DR-031 WT:B
-K3KL8L80DM-MGCU
+K3KL8L80CM-MGCT

From ec65e34332032a232d1b2d774e85e18a9a460ab7 Mon Sep 17 00:00:00 2001
From: Mike Lin <mike.lin@mediatek.corp-partner.google.com>
Date: Tue, 22 Oct 2024 17:49:12 +0800
Subject: [PATCH 0682/3886] soc/mediatek/mt8189: Add DRAM calibration support

Add DRAM calibration support for mt8189. DRAM parameters and related
constants are added in dramc_param.h and dramc_soc.h.

The common emi.c can be reused for MT8189 as well, so remove the
duplicate mt8189/emi.{c,h}.

Enable MEDIATEK_DRAM_BLOB_FAST_INIT to allow running DRAM fast
calibration via the DRAM blob.

BUG=b:379008996
BRANCH=none
TEST=Boot up pass and see log
3200 LPDDR5 chan0(x16) rank0: memory test pass
3200 LPDDR5 chan0(x16) rank1: memory test pass
3200 LPDDR5 chan1(x16) rank0: memory test pass
3200 LPDDR5 chan1(x16) rank1: memory test pass

Signed-off-by: Mike Lin <mike.lin@mediatek.corp-partner.google.com>
Change-Id: Ia6f6e5afc1f4a2e919243bda0799712cd7b4d01f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87037
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
---
 src/soc/mediatek/mt8189/Kconfig               |   3 +
 src/soc/mediatek/mt8189/Makefile.mk           |  19 ++-
 src/soc/mediatek/mt8189/emi.c                 |   8 --
 .../mediatek/mt8189/include/soc/dramc_param.h | 116 ++++++++++++++++++
 .../mediatek/mt8189/include/soc/dramc_soc.h   |  60 +++++++++
 src/soc/mediatek/mt8189/include/soc/emi.h     |  10 --
 6 files changed, 196 insertions(+), 20 deletions(-)
 delete mode 100644 src/soc/mediatek/mt8189/emi.c
 create mode 100644 src/soc/mediatek/mt8189/include/soc/dramc_param.h
 create mode 100644 src/soc/mediatek/mt8189/include/soc/dramc_soc.h
 delete mode 100644 src/soc/mediatek/mt8189/include/soc/emi.h

diff --git a/src/soc/mediatek/mt8189/Kconfig b/src/soc/mediatek/mt8189/Kconfig
index 512ae54d9e..bf55327a78 100644
--- a/src/soc/mediatek/mt8189/Kconfig
+++ b/src/soc/mediatek/mt8189/Kconfig
@@ -8,6 +8,9 @@ config SOC_MEDIATEK_MT8189
 	select ARCH_ROMSTAGE_ARMV8_64
 	select ARCH_RAMSTAGE_ARMV8_64
 	select HAVE_UART_SPECIAL
+	select CACHE_MRC_SETTINGS
+	select MEDIATEK_DRAM_BLOB_FAST_INIT
+	select USE_CBMEM_DRAM_INFO
 	select SOC_MEDIATEK_COMMON
 	select FLASH_DUAL_IO_READ
 	select ARM64_USE_ARCH_TIMER
diff --git a/src/soc/mediatek/mt8189/Makefile.mk b/src/soc/mediatek/mt8189/Makefile.mk
index 6774f52cde..bdee1fb33e 100644
--- a/src/soc/mediatek/mt8189/Makefile.mk
+++ b/src/soc/mediatek/mt8189/Makefile.mk
@@ -13,15 +13,30 @@ bootblock-y += ../common/mmu_operations.c
 bootblock-y += ../common/wdt.c ../common/wdt_req.c wdt.c
 
 romstage-y += ../common/cbmem.c
-romstage-y += emi.c
+romstage-y += ../common/dram_init.c
+romstage-y += ../common/dramc_param.c
+romstage-y += ../common/emi.c
+romstage-y += ../common/memory.c ../common/memory_test.c
+romstage-y += ../common/mmu_operations.c ../common/mmu_cmops.c
 
-ramstage-y += emi.c
+ramstage-y += ../common/emi.c
+ramstage-y += ../common/memory.c
+ramstage-y += ../common/mmu_operations.c ../common/mmu_cmops.c
 ramstage-y += soc.c
 ramstage-y += ../common/usb.c usb.c
 
 CPPFLAGS_common += -Isrc/soc/mediatek/mt8189/include
 CPPFLAGS_common += -Isrc/soc/mediatek/common/include
 
+MT8189_BLOB_DIR := 3rdparty/blobs/soc/mediatek/mt8189
+
+DRAM_CBFS := $(CONFIG_CBFS_PREFIX)/dram
+$(DRAM_CBFS)-file := $(MT8189_BLOB_DIR)/dram.elf
+$(DRAM_CBFS)-type := stage
+$(DRAM_CBFS)-compression := $(CBFS_PRERAM_COMPRESS_FLAG)
+ifneq ($(wildcard $($(DRAM_CBFS)-file)),)
+	cbfs-files-y += $(DRAM_CBFS)
+endif
 $(objcbfs)/bootblock.bin: $(objcbfs)/bootblock.raw.bin
 	./util/mtkheader/gen-bl-img.py mt8189 sf $< $@
 
diff --git a/src/soc/mediatek/mt8189/emi.c b/src/soc/mediatek/mt8189/emi.c
deleted file mode 100644
index 8b933e870d..0000000000
--- a/src/soc/mediatek/mt8189/emi.c
+++ /dev/null
@@ -1,8 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only OR MIT */
-
-#include <soc/emi.h>
-
-size_t sdram_size(void)
-{
-	return (size_t)4 * GiB;
-}
diff --git a/src/soc/mediatek/mt8189/include/soc/dramc_param.h b/src/soc/mediatek/mt8189/include/soc/dramc_param.h
new file mode 100644
index 0000000000..719c893a73
--- /dev/null
+++ b/src/soc/mediatek/mt8189/include/soc/dramc_param.h
@@ -0,0 +1,116 @@
+/* SPDX-License-Identifier: GPL-2.0-only OR MIT */
+
+#ifndef __SOC_MEDIATEK_MT8189_DRAMC_PARAM_H__
+#define __SOC_MEDIATEK_MT8189_DRAMC_PARAM_H__
+
+/*
+ * NOTE: This file is shared between coreboot and dram blob. Any change in this
+ * file should be synced to the other repository.
+ */
+
+#include <soc/dramc_param_common.h>
+#include <soc/dramc_soc.h>
+#include <stdint.h>
+#include <sys/types.h>
+
+#define DRAMC_PARAM_HEADER_VERSION 1
+#define CATRAINING_NUM_LP5 7
+
+struct sdram_params {
+	/* rank, cbt */
+	u32 rank_num;
+	u32 dram_cbt_mode;
+
+	u16 delay_cell_timex100;
+	u8 u18ph_dly[CHANNEL_MAX];
+
+	/* duty */
+	s8 duty_clk_delay[CHANNEL_MAX][RANK_MAX];
+	s8 duty_dqs_delay[CHANNEL_MAX][DQS_NUMBER_LP5];
+	s8 duty_wck_delay[CHANNEL_MAX][DQS_NUMBER_LP5];
+	s8 duty_mck16x_delay[CHANNEL_MAX][DQS_NUMBER_LP5 + 1];
+	s8 duty_dq_delay[CHANNEL_MAX][DQS_NUMBER_LP5];
+	s8 duty_dqm_delay[CHANNEL_MAX][DQS_NUMBER_LP5];
+
+	/* cbt */
+	u8 cbt_final_vref[CHANNEL_MAX][RANK_MAX];
+	u8 cbt_final_range[CHANNEL_MAX][RANK_MAX];
+	s16 s2CBTCAWindow_first_pass_Save[CHANNEL_MAX][RANK_MAX][CATRAINING_NUM_LP5];
+	s16 s2CBTCAWindow_last_pass_Save[CHANNEL_MAX][RANK_MAX][CATRAINING_NUM_LP5];
+	s16 cbt_cmd_dly[CHANNEL_MAX];
+	u16 cbt_cs_dly[CHANNEL_MAX];
+	u8 cbt_ca_prebit_dly[CHANNEL_MAX][DQS_BIT_NUMBER];
+
+	/* write leveling */
+	u8 wr_level_pi[CHANNEL_MAX][RANK_MAX][DQS_NUMBER_LP5];
+	u8 wr_level_dly[CHANNEL_MAX][RANK_MAX][DQS_NUMBER_LP5];
+
+	/* gating */
+	u8 gating_UI[CHANNEL_MAX][RANK_MAX][DQS_NUMBER_LP5];
+	u8 gating_PI[CHANNEL_MAX][RANK_MAX][DQS_NUMBER_LP5];
+	u8 gating_pass_count[CHANNEL_MAX][RANK_MAX][DQS_NUMBER_LP5];
+	u16 wck2dqo_cnt[CHANNEL_MAX][RANK_MAX][DQS_NUMBER_LP5];
+
+	/* rx input buffer */
+	s8 dq_offc[CHANNEL_MAX][DQ_DATA_WIDTH_LP5];
+	s8 dqm_offc[CHANNEL_MAX][DQS_NUMBER_LP5];
+
+	/* tx perbit */
+	u16 tx_window_vref[CHANNEL_MAX][RANK_MAX];
+	u16 tx_window_vref_range[CHANNEL_MAX][RANK_MAX];
+	s16 u1Txfirst_pass_Save[CHANNEL_MAX][RANK_MAX][DQ_DATA_WIDTH_LP5];
+	s16 u1Txlast_pass_Save[CHANNEL_MAX][RANK_MAX][DQ_DATA_WIDTH_LP5];
+	u16 tx_dq[CHANNEL_MAX][RANK_MAX][DQS_NUMBER_LP5];
+	u16 tx_dqm[CHANNEL_MAX][RANK_MAX][DQS_NUMBER_LP5];
+	u16 tx_dqm_only[CHANNEL_MAX][RANK_MAX][DQS_NUMBER_LP5];
+	u8 tx_perbit_dlyline[CHANNEL_MAX][RANK_MAX][EXT_DQ_DATA_WIDTH];
+	u16 wck2dqi_cnt0[CHANNEL_MAX][RANK_MAX];
+	u16 wck2dqi_cnt1[CHANNEL_MAX][RANK_MAX];
+
+	/* rx datlat */
+	u8 rx_datlat[CHANNEL_MAX];
+
+	/* rx perbit */
+	u8 rx_best_vref_perbyte[CHANNEL_MAX][RANK_MAX][DQS_NUMBER_LP5];
+	//u8 rx_best_vref_perbit[CHANNEL_MAX][RANK_MAX][DQ_DATA_WIDTH_LP5];
+	s16 u1Rxfirst_pass_Save[CHANNEL_MAX][RANK_MAX][DQ_DATA_WIDTH_LP5];
+	s16 u1Rxlast_pass_Save[CHANNEL_MAX][RANK_MAX][DQ_DATA_WIDTH_LP5];
+	u16 rx_perbit_dqs[CHANNEL_MAX][RANK_MAX][DQS_NUMBER_LP5];
+	u16 rx_perbit_dqm[CHANNEL_MAX][RANK_MAX][DQS_NUMBER_LP5];
+	u16 rx_perbit_dq[CHANNEL_MAX][RANK_MAX][DQ_DATA_WIDTH_LP5];
+	s16 rx_perbit_begin;
+
+	/* dvs */
+	u8 dvs_delay[CHANNEL_MAX][DQS_NUMBER_LP5];
+
+	u8 perbit_dcc[CHANNEL_MAX][RANK_MAX][DQ_DATA_WIDTH_LP5];
+
+	/* dcm */
+	u8 best_u[CHANNEL_MAX][RANK_MAX];
+	u8 best_l[CHANNEL_MAX][RANK_MAX];
+
+	/* Read DCA */
+	s8 rdca_u[CHANNEL_MAX][RANK_MAX];
+	s8 rdca_l[CHANNEL_MAX][RANK_MAX];
+
+	/* RDCC */
+	s8 rdcc[CHANNEL_MAX][RANK_MAX][DQS_NUMBER_LP5];
+
+	/* tx oe */
+	u8 tx_oe_dq_mck[CHANNEL_MAX][RANK_MAX][DQS_NUMBER_LP5];
+	u8 tx_oe_dq_ui[CHANNEL_MAX][RANK_MAX][DQS_NUMBER_LP5];
+	u16 tx_oe_offset[CHANNEL_MAX][RANK_MAX];
+};
+
+struct dramc_data {
+	struct ddr_base_info ddr_info;
+	struct sdram_params freq_params[DRAM_DFS_SHU_MAX];
+};
+
+struct dramc_param {
+	struct dramc_param_header header;
+	void (*do_putc)(unsigned char c);
+	struct dramc_data dramc_datas;
+};
+
+#endif  /* __SOC_MEDIATEK_MT8189_DRAMC_PARAM_H__ */
diff --git a/src/soc/mediatek/mt8189/include/soc/dramc_soc.h b/src/soc/mediatek/mt8189/include/soc/dramc_soc.h
new file mode 100644
index 0000000000..0035a9065a
--- /dev/null
+++ b/src/soc/mediatek/mt8189/include/soc/dramc_soc.h
@@ -0,0 +1,60 @@
+/* SPDX-License-Identifier: GPL-2.0-only OR MIT */
+
+#ifndef __SOC_MEDIATEK_MT8189_INCLUDE_SOC_DRAMC_SOC_H__
+#define __SOC_MEDIATEK_MT8189_INCLUDE_SOC_DRAMC_SOC_H__
+
+#include <soc/dramc_soc_common.h>
+#include <stdint.h>
+
+typedef enum {
+	CHANNEL_A = 0,
+	CHANNEL_B,
+	CHANNEL_MAX,
+} DRAM_CHANNEL_T;
+
+typedef enum {
+	RANK_0 = 0,
+	RANK_1,
+	RANK_MAX,
+} DRAM_RANK_T;
+
+typedef enum {
+	SRAM_SHU0 = 0,
+	SRAM_SHU1,
+	SRAM_SHU2,
+	SRAM_SHU3,
+	SRAM_SHU4,
+	DRAM_DFS_SRAM_MAX
+} DRAM_DFS_SRAM_SHU_T; /* DRAM SRAM RG type */
+
+typedef enum {
+	DRVP = 0,
+	DRVN,
+	ODTN,
+	IMP_DRV_MAX,
+} DRAM_IMP_DRV_T;
+
+typedef enum {
+	TYPE_INVALID = 0,
+	TYPE_DDR1,
+	TYPE_DDR2,
+	TYPE_DDR3,
+	TYPE_DDR4,
+	TYPE_DDR5,
+	TYPE_LPDDR2,
+	TYPE_LPDDR3,
+	TYPE_PCDDR3,
+	TYPE_LPDDR4,
+	TYPE_LPDDR4X,
+	TYPE_LPDDR4P,
+	TYPE_LPDDR5,
+	TYPE_LPDDR5X,
+	TYPE_MAX,
+} DRAM_DRAM_TYPE_T;
+
+#define DRAM_DFS_SHU_MAX	DRAM_DFS_SRAM_MAX
+#define DQS_NUMBER_LP5		2
+#define DQ_DATA_WIDTH_LP5	16
+#define EXT_DQ_DATA_WIDTH	18
+
+#endif	/* __SOC_MEDIATEK_MT8189_INCLUDE_SOC_DRAMC_SOC_H__ */
diff --git a/src/soc/mediatek/mt8189/include/soc/emi.h b/src/soc/mediatek/mt8189/include/soc/emi.h
deleted file mode 100644
index 9f66a7f790..0000000000
--- a/src/soc/mediatek/mt8189/include/soc/emi.h
+++ /dev/null
@@ -1,10 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only OR MIT */
-
-#ifndef __SOC_MEDIATEK_MT8189_INCLUDE_SOC_EMI_H__
-#define __SOC_MEDIATEK_MT8189_INCLUDE_SOC_EMI_H__
-
-#include <stddef.h>
-
-size_t sdram_size(void);
-
-#endif /* __SOC_MEDIATEK_MT8189_INCLUDE_SOC_EMI_H__ */

From af3076b1f923a1defba52bd8bf173079e5074f9a Mon Sep 17 00:00:00 2001
From: Mike Lin <mike.lin@mediatek.corp-partner.google.com>
Date: Tue, 24 Dec 2024 15:44:27 +0800
Subject: [PATCH 0683/3886] soc/mediatek/mt8196: Move TX TRACKING from MT8196
 to common folder

The configuration method of the reserved DRAM buffer used for HW TX
TRACING on MT8196 is also applicable to other SoCs, such as MT8189.

To facilitate reuse, we move the relevant files to the common directory.

BUG=b:379008996
BRANCH=none
TEST=Reserve memory ok
Firmware shows the following log with 12GB DDR board:
00000001ffff0000-00000001ffffffff: RESERVED
000000037fff0000-000000037fffffff: RESERVED

Change-Id: I3fdd9d2f7ab1bbdcc097510556929da2134f7d95
Signed-off-by: Mike Lin <mike.lin@mediatek.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87036
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
---
 src/soc/mediatek/{mt8196 => common}/dramc_info.c | 0
 src/soc/mediatek/common/include/soc/dramc_info.h | 8 ++++++++
 src/soc/mediatek/mt8196/Makefile.mk              | 2 +-
 src/soc/mediatek/mt8196/include/soc/dramc_info.h | 8 --------
 4 files changed, 9 insertions(+), 9 deletions(-)
 rename src/soc/mediatek/{mt8196 => common}/dramc_info.c (100%)
 create mode 100644 src/soc/mediatek/common/include/soc/dramc_info.h
 delete mode 100644 src/soc/mediatek/mt8196/include/soc/dramc_info.h

diff --git a/src/soc/mediatek/mt8196/dramc_info.c b/src/soc/mediatek/common/dramc_info.c
similarity index 100%
rename from src/soc/mediatek/mt8196/dramc_info.c
rename to src/soc/mediatek/common/dramc_info.c
diff --git a/src/soc/mediatek/common/include/soc/dramc_info.h b/src/soc/mediatek/common/include/soc/dramc_info.h
new file mode 100644
index 0000000000..a0be6403e5
--- /dev/null
+++ b/src/soc/mediatek/common/include/soc/dramc_info.h
@@ -0,0 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef __SOC_MEDIATEK_COMMON_DRAMC_INFO_H__
+#define __SOC_MEDIATEK_COMMON_DRAMC_INFO_H__
+
+void reserve_buffer_for_dramc(void);
+
+#endif	/* __SOC_MEDIATEK_COMMON_DRAMC_INFO_H__ */
diff --git a/src/soc/mediatek/mt8196/Makefile.mk b/src/soc/mediatek/mt8196/Makefile.mk
index 1793104d42..fa0e3fe0be 100644
--- a/src/soc/mediatek/mt8196/Makefile.mk
+++ b/src/soc/mediatek/mt8196/Makefile.mk
@@ -60,7 +60,7 @@ ramstage-y += ../common/display.c
 ramstage-y += ../common/dpm_v2.c
 ramstage-y += ../common/dp/dptx_common.c ../common/dp/dptx_hal_common.c
 ramstage-y += dptx.c dptx_hal.c dp_intf.c
-ramstage-y += dramc_info.c
+ramstage-y += ../common/dramc_info.c
 ramstage-y += ../common/early_init.c
 ramstage-y += ../common/emi.c
 ramstage-y += gpueb.c
diff --git a/src/soc/mediatek/mt8196/include/soc/dramc_info.h b/src/soc/mediatek/mt8196/include/soc/dramc_info.h
deleted file mode 100644
index ccc7ff9b97..0000000000
--- a/src/soc/mediatek/mt8196/include/soc/dramc_info.h
+++ /dev/null
@@ -1,8 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#ifndef __SOC_MEDIATEK_MT8196_DRAMC_INFO_H__
-#define __SOC_MEDIATEK_MT8196_DRAMC_INFO_H__
-
-void reserve_buffer_for_dramc(void);
-
-#endif	/* __SOC_MEDIATEK_MT8196_DRAMC_INFO_H__ */

From ccb987fa66457a8cfcfd74e715363b85280f4580 Mon Sep 17 00:00:00 2001
From: Vince Liu <vince-wl.liu@mediatek.corp-partner.google.com>
Date: Tue, 8 Apr 2025 09:25:51 +0800
Subject: [PATCH 0684/3886] soc/mediatek/common: Move DRAMC function
 declarations to common header

To promote code reuse and maintainability, this commit moves the DRAMC
parameter function declarations to the common folder.

BUG=b:379008996
BRANCH=none
TEST=build passed

Signed-off-by: Vince Liu <vince-wl.liu@mediatek.corp-partner.google.com>
Change-Id: Iab24f07b4c02da22779ea1c76f3237c144d92b98
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87209
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
---
 src/soc/mediatek/common/include/soc/dramc_param_common.h | 5 +++++
 src/soc/mediatek/mt8186/include/soc/dramc_param.h        | 4 ----
 src/soc/mediatek/mt8188/include/soc/dramc_param.h        | 6 ------
 src/soc/mediatek/mt8192/include/soc/dramc_param.h        | 5 -----
 src/soc/mediatek/mt8195/include/soc/dramc_param.h        | 5 -----
 src/soc/mediatek/mt8196/include/soc/dramc_param.h        | 6 ------
 6 files changed, 5 insertions(+), 26 deletions(-)

diff --git a/src/soc/mediatek/common/include/soc/dramc_param_common.h b/src/soc/mediatek/common/include/soc/dramc_param_common.h
index a1fac9af85..f7cf83abae 100644
--- a/src/soc/mediatek/common/include/soc/dramc_param_common.h
+++ b/src/soc/mediatek/common/include/soc/dramc_param_common.h
@@ -103,5 +103,10 @@ struct ddr_base_info {
 };
 
 const struct sdram_info *get_sdram_config(void);
+struct dramc_param *get_dramc_param_from_blob(void *blob);
+void dump_param_header(const void *blob);
+int validate_dramc_param(const void *blob);
+int is_valid_dramc_param(const void *blob);
+int initialize_dramc_param(void *blob);
 
 #endif
diff --git a/src/soc/mediatek/mt8186/include/soc/dramc_param.h b/src/soc/mediatek/mt8186/include/soc/dramc_param.h
index 29380c2127..773d6af5b0 100644
--- a/src/soc/mediatek/mt8186/include/soc/dramc_param.h
+++ b/src/soc/mediatek/mt8186/include/soc/dramc_param.h
@@ -78,8 +78,4 @@ struct dramc_param {
 	struct dramc_data dramc_datas;
 };
 
-struct dramc_param *get_dramc_param_from_blob(void *blob);
-void dump_param_header(const void *blob);
-int initialize_dramc_param(void *blob);
-
 #endif  /* __SOC_MEDIATEK_MT8186_DRAMC_PARAM_H__ */
diff --git a/src/soc/mediatek/mt8188/include/soc/dramc_param.h b/src/soc/mediatek/mt8188/include/soc/dramc_param.h
index 740e27b6f7..58241f478e 100644
--- a/src/soc/mediatek/mt8188/include/soc/dramc_param.h
+++ b/src/soc/mediatek/mt8188/include/soc/dramc_param.h
@@ -98,10 +98,4 @@ struct dramc_param {
 	struct dramc_data dramc_datas;
 };
 
-struct dramc_param *get_dramc_param_from_blob(void *blob);
-void dump_param_header(const void *blob);
-int validate_dramc_param(const void *blob);
-int is_valid_dramc_param(const void *blob);
-int initialize_dramc_param(void *blob);
-
 #endif  /* __SOC_MEDIATEK_MT8188_DRAMC_PARAM_H__ */
diff --git a/src/soc/mediatek/mt8192/include/soc/dramc_param.h b/src/soc/mediatek/mt8192/include/soc/dramc_param.h
index fca82bee62..b0f9f45e67 100644
--- a/src/soc/mediatek/mt8192/include/soc/dramc_param.h
+++ b/src/soc/mediatek/mt8192/include/soc/dramc_param.h
@@ -73,9 +73,4 @@ struct dramc_param {
 	struct dramc_data dramc_datas;
 };
 
-struct dramc_param *get_dramc_param_from_blob(void *blob);
-void dump_param_header(const void *blob);
-int validate_dramc_param(const void *blob);
-int is_valid_dramc_param(const void *blob);
-int initialize_dramc_param(void *blob);
 #endif  /* __SOC_MEDIATEK_MT8192_DRAMC_PARAM_H__ */
diff --git a/src/soc/mediatek/mt8195/include/soc/dramc_param.h b/src/soc/mediatek/mt8195/include/soc/dramc_param.h
index 0885ee0651..3ca7d81f25 100644
--- a/src/soc/mediatek/mt8195/include/soc/dramc_param.h
+++ b/src/soc/mediatek/mt8195/include/soc/dramc_param.h
@@ -73,9 +73,4 @@ struct dramc_param {
 	struct dramc_data dramc_datas;
 };
 
-struct dramc_param *get_dramc_param_from_blob(void *blob);
-void dump_param_header(const void *blob);
-int validate_dramc_param(const void *blob);
-int is_valid_dramc_param(const void *blob);
-int initialize_dramc_param(void *blob);
 #endif  /* __SOC_MEDIATEK_MT8195_DRAMC_PARAM_H__ */
diff --git a/src/soc/mediatek/mt8196/include/soc/dramc_param.h b/src/soc/mediatek/mt8196/include/soc/dramc_param.h
index 13a4dff095..819b1af6ce 100644
--- a/src/soc/mediatek/mt8196/include/soc/dramc_param.h
+++ b/src/soc/mediatek/mt8196/include/soc/dramc_param.h
@@ -105,10 +105,4 @@ struct dramc_param {
 	struct dramc_data dramc_datas;
 };
 
-struct dramc_param *get_dramc_param_from_blob(void *blob);
-void dump_param_header(const void *blob);
-int validate_dramc_param(const void *blob);
-int is_valid_dramc_param(const void *blob);
-int initialize_dramc_param(void *blob);
-
 #endif  /* __SOC_MEDIATEK_MT8196_DRAMC_PARAM_H__ */

From 006ed0043c35a07afff3db90305d6b0f1981ecf0 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Micha=C5=82=20Kope=C4=87?= <michal.kopec@3mdeb.com>
Date: Sat, 29 Mar 2025 20:38:06 +0100
Subject: [PATCH 0685/3886] Documentation/mainboard/lenovo: Add ThinkCentre
 M700/M900 Tiny
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Heavily based on M710s documentation.

Change-Id: I8c3860ba6254919769082c9ed749f8bb287a5f5e
Signed-off-by: Michał Kopeć <michal.kopec@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87044
Reviewed-by: Nicholas Chin <nic.c3.14@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 Documentation/mainboard/index.md              |   1 +
 .../mainboard/lenovo/thinkcentre_m900_tiny.md |  88 ++++++++++++++++++
 .../thinkcentre_m900_tiny_spi_location.jpg    | Bin 0 -> 208483 bytes
 3 files changed, 89 insertions(+)
 create mode 100644 Documentation/mainboard/lenovo/thinkcentre_m900_tiny.md
 create mode 100644 Documentation/mainboard/lenovo/thinkcentre_m900_tiny_spi_location.jpg

diff --git a/Documentation/mainboard/index.md b/Documentation/mainboard/index.md
index 870f0c625c..c66b119302 100644
--- a/Documentation/mainboard/index.md
+++ b/Documentation/mainboard/index.md
@@ -186,6 +186,7 @@ Mainboard codenames <lenovo/codenames.md>
 Hardware Maintenance Manual of ThinkPads <lenovo/thinkpad_hmm.md>
 R60 <lenovo/r60.md>
 ThinkCentre M710s <lenovo/thinkcentre_m710s.md>
+ThinkCentre M700 / M900 Tiny <lenovo/thinkcentre_m900_tiny.md>
 T4xx common <lenovo/t4xx_series.md>
 X2xx common <lenovo/x2xx_series.md>
 M920 Tiny <lenovo/m920q.md>
diff --git a/Documentation/mainboard/lenovo/thinkcentre_m900_tiny.md b/Documentation/mainboard/lenovo/thinkcentre_m900_tiny.md
new file mode 100644
index 0000000000..7c9f41c90a
--- /dev/null
+++ b/Documentation/mainboard/lenovo/thinkcentre_m900_tiny.md
@@ -0,0 +1,88 @@
+# Lenovo ThinkCentre M700 / M900 Tiny
+
+This page provides technical documentation on [Lenovo ThinkCentre M700 / M900 Tiny].
+
+M700 Tiny and M900 Tiny are twin designs using the same exact mainboard, with
+the following differences:
+
+```{eval-rst}
++------------------------+------+------+
+|        Feature         | M700 | M900 |
++========================+======+======+
+| Chipset                | B150 | Q170 |
++------------------------+------+------+
+| Intel AMT              | No   | Yes  |
++------------------------+------+------+
+| Intel TXT              | No   | Yes  |
++------------------------+------+------+
+| PCIe lanes in M.2 slot | No   | Yes  |
++------------------------+------+------+
+```
+
+## Flash chip
+
+```{eval-rst}
++----------+--------------------------+
+|   Type   |          Value           |
++==========+==========================+
+| Socketed | no                       |
++----------+--------------------------+
+| Model    | W25Q128.V or MX25L12873F |
++----------+--------------------------+
+| Size     | 16MiB                    |
++----------+--------------------------+
+| Package  | SOIC-8                   |
++----------+--------------------------+
+```
+
+The flash chip is divided into the following regions.
+
+	00000000:00000fff fd
+	00001000:00002fff gbe
+	00003000:007fffff me
+	00800000:00ffffff bios
+
+## Flashing
+
+The flash chip cannot be flashed internally when running vendor firmware, and must
+be flashed externally using a programmer of your choice.
+
+Steps on how to open the chassis and get access to the mainboard are described
+in the [hardware maintenance manual]. Follow the steps shown from
+"[Removing the computer cover]" until "[Replacing the M.2 storage drive]".
+
+The SPI flash should be easy to identify and the location is shown in the image
+below. See the [datasheet] and [flashing firmware tutorial] for more information.
+
+![](thinkcentre_m900_tiny_spi_location.jpg)
+
+## Status
+
+### Working
+
+ * Debian 12 (Linux 6.1.0) using MrChromebox' EDK II fork (uefipayload_2502)
+ * M.2 SATA + NVMe slot
+ * M.2 Wi-Fi slot
+ * Display ports
+ * USB
+ * Audio
+ * LAN
+ * CPU fan
+ * Discrete TPM 1.2
+ * Internal flashing (from coreboot)
+ * COM1 header
+ * DisplayPort header
+ * Power LED
+ * S3 Suspend
+
+### Untested
+
+ * PS/2 header
+ * PCIe + SATA "2L" expansion header
+
+[Lenovo ThinkCentre M700 / M900 Tiny]: https://psref.lenovo.com/syspool/Sys/PDF/ThinkCentre/ThinkCentre_M900_Tiny/ThinkCentre_M900_Tiny_Spec.PDF
+[hardware maintenance manual]: https://download.lenovo.com/pccbbs/thinkcentre_pdf/m700_m900_m900x_tiny_hmm.pdf
+[Removing the computer cover]: https://download.lenovo.com/pccbbs/thinkcentre_pdf/m700_m900_m900x_tiny_hmm.pdf#page=119
+[Replacing the M.2 storage drive]: https://download.lenovo.com/pccbbs/thinkcentre_pdf/m700_m900_m900x_tiny_hmm.pdf#page=134
+[datasheet]: https://www.mouser.com/datasheet/2/949/w25q128jv_revf_03272018_plus-1489608.pdf
+[flashing firmware tutorial]: ../../tutorial/flashing_firmware/index.md
diff --git a/Documentation/mainboard/lenovo/thinkcentre_m900_tiny_spi_location.jpg b/Documentation/mainboard/lenovo/thinkcentre_m900_tiny_spi_location.jpg
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literal 0
HcmV?d00001


From 2dec38c92c049c0a71d09b08808ff9ff24320c47 Mon Sep 17 00:00:00 2001
From: Liu Liu <ot_liu.liu@mediatek.corp-partner.google.com>
Date: Tue, 10 Dec 2024 17:23:26 +0800
Subject: [PATCH 0686/3886] mb/google/skywalker: Set up USB host in ramstage

Add USB host function support.

BUG=b:379008996
BRANCH=none
TEST=boot to kernel successfully from USB drive

Signed-off-by: Liu Liu <ot_liu.liu@mediatek.corp-partner.google.com>
Change-Id: I3f77d116033338f979d14ce34ddf03e00d024e5d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87022
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
---
 src/mainboard/google/skywalker/mainboard.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/src/mainboard/google/skywalker/mainboard.c b/src/mainboard/google/skywalker/mainboard.c
index 9ab352c269..257faa1f10 100644
--- a/src/mainboard/google/skywalker/mainboard.c
+++ b/src/mainboard/google/skywalker/mainboard.c
@@ -1,10 +1,11 @@
 /* SPDX-License-Identifier: GPL-2.0-only OR MIT */
 
 #include <device/device.h>
+#include <soc/usb.h>
 
 static void mainboard_init(struct device *dev)
 {
-	/* TODO: add mainboard init */
+	setup_usb_host();
 }
 
 static void mainboard_enable(struct device *dev)

From 1662396037320f00293c716fb5f9eeac0a09740c Mon Sep 17 00:00:00 2001
From: Martin Roth <gaumless@gmail.com>
Date: Sat, 5 Apr 2025 21:03:34 -0600
Subject: [PATCH 0687/3886] Documentation: Reformat fw_config.md

This doesn't change any text - it just reformats the existing document.
- reflow paragraphs to 72 characters
- Put examples inside pre-formatted text blocks
- Adds spacing before section markers

Change-Id: I83925a4469e264da5887334e2584466cef089503
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87190
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nicholas Chin <nic.c3.14@gmail.com>
---
 Documentation/lib/fw_config.md | 488 +++++++++++++++++++--------------
 1 file changed, 288 insertions(+), 200 deletions(-)

diff --git a/Documentation/lib/fw_config.md b/Documentation/lib/fw_config.md
index 884ba3f237..bb7f4fbac4 100644
--- a/Documentation/lib/fw_config.md
+++ b/Documentation/lib/fw_config.md
@@ -2,225 +2,284 @@
 
 ## Motivation
 
-The firmware configuration interface in coreboot is designed to support a wide variety of
-configuration options in that are dictated by the hardware at runtime.  This allows a single
-BIOS image to be used across a wide variety of devices which may have key differences but are
-otherwise similar enough to use the same coreboot build target.
+The firmware configuration interface in coreboot is designed to support
+a wide variety of configuration options in that are dictated by the
+hardware at runtime. This allows a single BIOS image to be used across a
+wide variety of devices which may have key differences but are otherwise
+similar enough to use the same coreboot build target.
 
-The initial implementation is designed to take advantage of a bitmask returned by the Embedded
-Controller on Google ChromeOS devices which allows the manufacturer to use the same firmware
-image across multiple devices by selecting various options at runtime.  See the ChromiumOS
+The initial implementation is designed to take advantage of a bitmask
+returned by the Embedded Controller on Google ChromeOS devices which
+allows the manufacturer to use the same firmware image across multiple
+devices by selecting various options at runtime. See the ChromiumOS
 [Firmware Config][1] documentation for more information.
 
-This firmware configuration interface differs from the CMOS option interface in that this
-bitmask value is not intended as a user-configurable setting as the configuration values must
-match the actual hardware.  In the case where a user was to swap their hardware this value
-would need to be updated or overridden.
+This firmware configuration interface differs from the CMOS option
+interface in that this bitmask value is not intended as a
+user-configurable setting as the configuration values must match the
+actual hardware. In the case where a user was to swap their hardware
+this value would need to be updated or overridden.
+
 
 ## Device Presence
 
-One common example of why a firmware configuration interface is important is determining if a
-device is present in the system.  With some bus topologies and hardware mechanisms it is
-possible to probe and enumerate this at runtime:
+One common example of why a firmware configuration interface is
+important is determining if a device is present in the system. With some
+bus topologies and hardware mechanisms it is possible to probe and
+enumerate this at runtime:
 
 - PCI is a self-discoverable bus and is very easy to handle.
 - I2C devices can often be probed with a combination of bus and address.
-- The use of GPIOs with external strap to ground or different voltages can be used to detect
-presence of a device.
+- The use of GPIOs with external strap to ground or different voltages
+  can be used to detect presence of a device.
 
 However there are several cases where this is insufficient:
 
-- I2C peripherals that require different drivers but have the same bus address cannot be
-uniquely identified at runtime.
-- A mainboard may be designed with multiple daughter board combinations which contain devices
-and configurations that cannot be detected.
-- While presence detect GPIOs are a convenient way for a single device presence, they are
-unable to distinguish between different devices so it can require a large number of GPIOs to
-support relatively few options.
+- I2C peripherals that require different drivers but have the same bus
+  address cannot be uniquely identified at runtime.
+- A mainboard may be designed with multiple daughter board combinations
+  which contain devices and configurations that cannot be detected.
+- While presence detect GPIOs are a convenient way for a single device
+  presence, they are unable to distinguish between different devices so
+  it can require a large number of GPIOs to support relatively few
+  options.
 
 This presence detection can impact different stages of boot:
 
+
 ### ACPI
 
-Devices that are not present should not provide an ACPI device indicating that they are
-present or the operating system may not be able to handle it correctly.
+Devices that are not present should not provide an ACPI device
+indicating that they are present or the operating system may not be able
+to handle it correctly.
+
+The ACPI devices are largely driven by chips defined in the mainboard
+`devicetree.cb` and the variant overridetree.cb. This means it is
+important to be able to specify when a device is present or not directly
+in `devicetree.cb` itself. Otherwise each mainboard needs custom code to
+parse the tree and disable unused devices.
 
-The ACPI devices are largely driven by chips defined in the mainboard `devicetree.cb` and
-the variant overridetree.cb.  This means it is important to be able to specify when a device
-is present or not directly in `devicetree.cb` itself.  Otherwise each mainboard needs custom
-code to parse the tree and disable unused devices.
 
 ### GPIO
 
-GPIOs with multiple functions may need to be configured correctly depending on the attached
-device.  Given the wide variety of GPIO configuration possibilities it is not feasible to
-specify all combinations directly in `devicetree.cb` and it is best left to code provided by
-the mainboard.
+GPIOs with multiple functions may need to be configured correctly
+depending on the attached device. Given the wide variety of GPIO
+configuration possibilities it is not feasible to specify all
+combinations directly in `devicetree.cb` and it is best left to code
+provided by the mainboard.
+
 
 ### FSP UPD
 
-Enabling and disabling devices may require altering FSP UPD values that are provided to the
-various stages of FSP.  These options are also not easy to specify multiple times for
-different configurations in `devicetree.cb` and can be provided by the mainboard as code.
+Enabling and disabling devices may require altering FSP UPD values that
+are provided to the various stages of FSP. These options are also not
+easy to specify multiple times for different configurations in
+`devicetree.cb` and can be provided by the mainboard as code.
+
 
 ## Firmware Configuration Interface
 
-The firmware configuration interface can be enabled by selecting `CONFIG_FW_CONFIG` and also
-providing a source for the value by defining an additional Kconfig option defined below.
+The firmware configuration interface can be enabled by selecting
+`CONFIG_FW_CONFIG` and also providing a source for the value by defining
+an additional Kconfig option defined below.
+
+If the firmware configuration interface is disabled via Kconfig then all
+probe attempts will return true.
 
-If the firmware configuration interface is disabled via Kconfig then all probe attempts will
-return true.
 
 ## Firmware Configuration Value
 
-The 64-bit value used as the firmware configuration bitmask is meant to be determined at runtime
-but could also be defined at compile time if needed.
+The 64-bit value used as the firmware configuration bitmask is meant to
+be determined at runtime but could also be defined at compile time if
+needed.
+
+There are two supported sources for providing this information to
+coreboot.
 
-There are two supported sources for providing this information to coreboot.
 
 ### CBFS
 
-The value can be provided with a 64-bit raw value in CBFS that is read by coreboot.  The value
-can be set at build time but also adjusted in an existing image with `cbfstool`.
+The value can be provided with a 64-bit raw value in CBFS that is read
+by coreboot. The value can be set at build time but also adjusted in an
+existing image with `cbfstool`.
 
-To enable this select the `CONFIG_FW_CONFIG_CBFS` option in the build configuration and add a
-raw 64-bit value to CBFS with the name of the current prefix at `CONFIG_FW_PREFIX/fw_config`.
+To enable this select the `CONFIG_FW_CONFIG_CBFS` option in the build
+configuration and add a raw 64-bit value to CBFS with the name of the
+current prefix at `CONFIG_FW_PREFIX/fw_config`.
+
+When `fw_config_probe_device()` or `fw_config_probe()` is called it will
+look for the specified file in CBFS use the value it contains when
+matching fields and options.
 
-When `fw_config_probe_device()` or `fw_config_probe()` is called it will look for the specified
-file in CBFS use the value it contains when matching fields and options.
 
 ### Embedded Controller
 
-Google ChromeOS devices support an Embedded Controller interface for reading and writing the
-firmware configuration value, along with other board-specific information.  It is possible for
-coreboot to read this value at boot on systems that support this feature.
+Google ChromeOS devices support an Embedded Controller interface for
+reading and writing the firmware configuration value, along with other
+board-specific information. It is possible for coreboot to read this
+value at boot on systems that support this feature.
 
 This option is selected by default for the mainboards that use it with
-`CONFIG_FW_CONFIG_CHROME_EC_CBI` and it is not typically necessary to adjust the value.  It is
-possible by enabling the CBFS source and coreboot will look in CBFS first for a valid value
-before asking the embedded controller.
+`CONFIG_FW_CONFIG_CHROME_EC_CBI` and it is not typically necessary to
+adjust the value. It is possible by enabling the CBFS source and
+coreboot will look in CBFS first for a valid value before asking the
+embedded controller.
 
-It is also possible to adjust the value in the embedded controller *(after disabling write
-protection)* with the `ectool` command in a ChromeOS environment.
+It is also possible to adjust the value in the embedded controller
+*(after disabling write protection)* with the `ectool` command in a
+ChromeOS environment.
 
-For more information on the firmware configuration field on ChromeOS devices see the Chromium
-documentation for [Firmware Config][1] and [Board Info][2].
+For more information on the firmware configuration field on ChromeOS
+devices see the Chromium documentation for [Firmware Config][1] and
+[Board Info][2].
 
 [1]: http://chromium.googlesource.com/chromiumos/docs/+/HEAD/design_docs/firmware_config.md
 [2]: http://chromium.googlesource.com/chromiumos/docs/+/HEAD/design_docs/cros_board_info.md
 
+
 ## Firmware Configuration Table
 
-The firmware configuration table itself is defined in the mainboard `devicetree.cb` with
-special tokens for defining fields and options.
+The firmware configuration table itself is defined in the mainboard
+`devicetree.cb` with special tokens for defining fields and options.
 
-The table itself is enclosed in a `fw_config` token and terminated with `end` and it contains
-a mix of field and option definitions.
+The table itself is enclosed in a `fw_config` token and terminated with
+`end` and it contains a mix of field and option definitions.
 
-Each field is defined by providing the field name and the start and end bit marking the exact
-location in the bitmask.  Field names must be at least three characters long in order to
-satisfy the sconfig parser requirements and they must be unique with non-overlapping masks.
+Each field is defined by providing the field name and the start and end
+bit marking the exact location in the bitmask. Field names must be at
+least three characters long in order to satisfy the sconfig parser
+requirements and they must be unique with non-overlapping masks.
 
-	field <name> <start-bit> <end-bit> [option...] end
+```text
+field <name> <start-bit> <end-bit> [option...] end
+```
 
 For single-bit fields only one number is needed:
 
-	field <name> <bit> [option...] end
+```text
+field <name> <bit> [option...] end
+```
 
-A field definition can also contain multiple sets of bit masks, which can be dis-contiguous.
-They are treated as if they are contiguous when defining option values.  This allows for
-extending fields even after the bits after its current masks are occupied.
+A field definition can also contain multiple sets of bit masks, which
+can be dis-contiguous. They are treated as if they are contiguous when
+defining option values. This allows for extending fields even after the
+bits after its current masks are occupied.
 
-	field <name> <start-bit0> <end-bit0> | <start-bit1> <end-bit1> | ...
+```text
+field <name> <start-bit0> <end-bit0> | <start-bit1> <end-bit1> | ...
+```
 
 For example, if more audio options need to be supported:
 
-	field AUDIO 3 3
-		option AUDIO_0  0
-		option AUDIO_1  1
-	end
-	field OTHER 4 4
-		...
-	end
+```text
+field AUDIO 3 3
+    option AUDIO_0  0
+    option AUDIO_1  1
+end
+field OTHER 4 4
+    ...
+end
+```
 
 the following can be done:
 
-	field AUDIO 3 3 | 5 5
-		option AUDIO_FOO   0
-		option AUDIO_BLAH  1
-		option AUDIO_BAR   2
-		option AUDIO_BAZ   3
-	end
-	field OTHER 4 4
-		...
-	end
+```text
+field AUDIO 3 3 | 5 5
+   option AUDIO_FOO   0
+    option AUDIO_BLAH  1
+    option AUDIO_BAR   2
+    option AUDIO_BAZ   3
+end
+field OTHER 4 4
+    ...
+end
+```
 
 In that case, the AUDIO masks are extended like so:
 
-	#define FW_CONFIG_FIELD_AUDIO_MASK						0x28
-	#define FW_CONFIG_FIELD_AUDIO_OPTION_AUDIO_FOO_VALUE	0x0
-	#define FW_CONFIG_FIELD_AUDIO_OPTION_AUDIO_BLAH_VALUE	0x8
-	#define FW_CONFIG_FIELD_AUDIO_OPTION_AUDIO_BAR_VALUE	0x20
-	#define FW_CONFIG_FIELD_AUDIO_OPTION_AUDIO_BAz_VALUE	0x28
+```c
+#define FW_CONFIG_FIELD_AUDIO_MASK                      0x28
+#define FW_CONFIG_FIELD_AUDIO_OPTION_AUDIO_FOO_VALUE    0x0
+#define FW_CONFIG_FIELD_AUDIO_OPTION_AUDIO_BLAH_VALUE   0x8
+#define FW_CONFIG_FIELD_AUDIO_OPTION_AUDIO_BAR_VALUE    0x20
+#define FW_CONFIG_FIELD_AUDIO_OPTION_AUDIO_BAz_VALUE    0x28
+```
 
-Each `field` definition starts a new block that can be composed of zero or more field options,
-and it is terminated with `end`.
+Each `field` definition starts a new block that can be composed of zero
+or more field options, and it is terminated with `end`.
 
-Inside the field block the options can be defined by providing the option name and the field
-value that this option represents when the bit offsets are used to apply a mask and shift.
-Option names must also be at least three characters for the sconfig parser.
+Inside the field block the options can be defined by providing the
+option name and the field value that this option represents when the bit
+offsets are used to apply a mask and shift. Option names must also be at
+least three characters for the sconfig parser.
 
-	option <name> <value>
+```text
+option <name> <value>
+```
 
-It is possible for there to be multiple `fw_config` blocks and for subsequent `field` blocks
-to add additional `option` definitions to the existing field.  These subsequent definitions
-should not provide the field bitmask as it has already been defined earlier in the file and
+It is possible for there to be multiple `fw_config` blocks and for
+subsequent `field` blocks to add additional `option` definitions to the
+existing field. These subsequent definitions should not provide the
+field bitmask as it has already been defined earlier in the file and
 this is just matching an existing field by name.
 
-	field <name> [option...] end
+```text
+field <name> [option...] end
+```
 
-This allows a baseboard to define the major fields and options in `devicetree.cb` and a board
-variant to add specific options to fields in or define new fields in the unused bitmask in
-`overridetree.cb`.
+This allows a baseboard to define the major fields and options in
+`devicetree.cb` and a board variant to add specific options to fields in
+or define new fields in the unused bitmask in `overridetree.cb`.
+
+It is not possible to redefine a field mask or override the value of an
+existing option this way, only to add new options to a field or new
+fields to the table.
 
-It is not possible to redefine a field mask or override the value of an existing option this
-way, only to add new options to a field or new fields to the table.
 
 ### Firmware Configuration Table Example
 
-In this example a baseboard defines a simple boolean feature that is enabled or disabled
-depending on the value of bit 0, and a field at bits 1-2 that indicates which daughter board
-is attached.
+In this example a baseboard defines a simple boolean feature that is
+enabled or disabled depending on the value of bit 0, and a field at bits
+1-2 that indicates which daughter board is attached.
+
+The baseboard itself defines one daughter board and the variant adds two
+more possibilities. This way each variant can support multiple possible
+daughter boards in addition to the one that was defined by the
+baseboard.
 
-The baseboard itself defines one daughter board and the variant adds two more possibilities.
-This way each variant can support multiple possible daughter boards in addition to the one
-that was defined by the baseboard.
 
 #### devicetree.cb
 
-    fw_config
-        field FEATURE 0
-            option DISABLED 0
-            option ENABLED 1
-        end
-        field DAUGHTER_BOARD 1 2
-            option NONE 0
-            option REFERENCE_DB 1
-        end
+```text
+fw_config
+    field FEATURE 0
+        option DISABLED 0
+        option ENABLED 1
     end
+    field DAUGHTER_BOARD 1 2
+        option NONE 0
+        option REFERENCE_DB 1
+    end
+end
+```
+
 
 #### overridetree.cb
 
-    fw_config
-        field DAUGHTER_BOARD
-            option VARIANT_DB_ONE 2
-            option VARIANT_DB_TWO 3
-        end
+```text
+fw_config
+    field DAUGHTER_BOARD
+        option VARIANT_DB_ONE 2
+        option VARIANT_DB_TWO 3
     end
+end
+```
+
+The result of this table defined in `devicetree.cb` is a list of
+constants that can be used to check if fields match the firmware
+configuration options determined at runtime with a simple check of the
+field mask and the option value.
 
-The result of this table defined in `devicetree.cb` is a list of constants that can be used
-to check if fields match the firmware configuration options determined at runtime with a
-simple check of the field mask and the option value.
 
 #### static.h
 
@@ -246,73 +305,96 @@ simple check of the field mask and the option value.
 #define FW_CONFIG_FIELD_DAUGHTER_BOARD_OPTION_VARIANT_DB_TWO_VALUE 0x00000006
 ```
 
+
 ## Device Probing
 
-One use of the firmware configuration interface in devicetree is to allow device probing to be
-specified directly with the devices themselves.  A new `probe` token is introduced to allow a
-device to be probed by field and option name.  Multiple `probe` entries may be present for
-each device and any successful probe will consider the device to be present.
+One use of the firmware configuration interface in devicetree is to
+allow device probing to be specified directly with the devices
+themselves. A new `probe` token is introduced to allow a device to be
+probed by field and option name. Multiple `probe` entries may be present
+for each device and any successful probe will consider the device to be
+present.
+
 
 ### Probing Example
 
-Continuing with the previous example this device would be considered present if the field
-`DAUGHTER_BOARD` was set to either `VARIANT_DB_ONE` or `VARIANT_DB_TWO`:
+Continuing with the previous example this device would be considered
+present if the field `DAUGHTER_BOARD` was set to either `VARIANT_DB_ONE`
+or `VARIANT_DB_TWO`:
+
 
 #### overridetree.cb
 
-    chip drivers/generic/example
-        device generic 0 on
-            probe DAUGHTER_BOARD VARIANT_DB_ONE
-            probe DAUGHTER_BOARD VARIANT_DB_TWO
-        end
+```text
+chip drivers/generic/example
+    device generic 0 on
+        probe DAUGHTER_BOARD VARIANT_DB_ONE
+        probe DAUGHTER_BOARD VARIANT_DB_TWO
     end
+end
+```
+
+If the field were set to any other option, including `NONE` and
+`REFERENCE_DB` and any undefined value then the device would be
+disabled.
 
-If the field were set to any other option, including `NONE` and `REFERENCE_DB` and any
-undefined value then the device would be disabled.
 
 ### Probe Overrides
 
-When a device is declared with a probe in the baseboard `devicetree.cb` and the same device
-is also present in the `overridetree.cb` then the probing information from the baseboard
-is discarded and the override device must provide all necessary probing information.
+When a device is declared with a probe in the baseboard `devicetree.cb`
+and the same device is also present in the `overridetree.cb` then the
+probing information from the baseboard is discarded and the override
+device must provide all necessary probing information.
 
-In this example a device is listed in the baseboard with `DAUGHTER_BOARD` field probing for
-`REFERENCE_DB` as a field option,  It is also defined as an override device with the field
-probing for the `VARIANT_DB_ONE` option instead.
+In this example a device is listed in the baseboard with
+`DAUGHTER_BOARD` field probing for `REFERENCE_DB` as a field option, It
+is also defined as an override device with the field probing for the
+`VARIANT_DB_ONE` option instead.
+
+In this case only the probe listed in the override is checked and a
+field option of `REFERENCE_DB` will not mark this device present. If
+both options are desired then the override device must list both. This
+allows an override device to remove a probe entry that was defined in
+the baseboard.
 
-In this case only the probe listed in the override is checked and a field option of
-`REFERENCE_DB` will not mark this device present.  If both options are desired then the
-override device must list both.  This allows an override device to remove a probe entry that
-was defined in the baseboard.
 
 #### devicetree.cb
 
-    chip drivers/generic/example
-	    device generic 0 on
-		    probe DAUGHTER_BOARD REFERENCE_DB
-	    end
-	end
+```text
+chip drivers/generic/example
+    device generic 0 on
+        probe DAUGHTER_BOARD REFERENCE_DB
+    end
+end
+```
+
 
 #### overridetree.cb
 
-    chip drivers/generic/example
-	    device generic 0 on
-		    probe DAUGHTER_BOARD VARIANT_DB_ONE
-	    end
-	end
+```text
+chip drivers/generic/example
+    device generic 0 on
+        probe DAUGHTER_BOARD VARIANT_DB_ONE
+    end
+end
+```
+
 
 ### Automatic Device Probing
 
-At boot time the firmware configuration interface will walk the device tree and apply any
-probe entries that were defined in `devicetree.cb`.  This probing takes effect before the
-`BS_DEV_ENUMERATE` step during the boot state machine in ramstage.
+At boot time the firmware configuration interface will walk the device
+tree and apply any probe entries that were defined in `devicetree.cb`.
+This probing takes effect before the `BS_DEV_ENUMERATE` step during the
+boot state machine in ramstage.
 
-Devices that have a probe list but do do not find a match are disabled by setting
-`dev->enabled = 0` but the chip `enable_dev()` and device `enable()` handlers will still
-be executed to allow any device disable code to execute.
+Devices that have a probe list but do do not find a match are disabled
+by setting `dev->enabled = 0` but the chip `enable_dev()` and device
+`enable()` handlers will still be executed to allow any device disable
+code to execute.
+
+The result of this probe definition is to provide an array of structures
+describing each field and option to check.
 
-The result of this probe definition is to provide an array of structures describing each
-field and option to check.
 
 #### fw_config.h
 
@@ -325,40 +407,43 @@ field and option to check.
  * @value: Value of the option within the mask.
  */
 struct fw_config {
-	const char *field_name;
-	const char *option_name;
-	uint64_t mask;
-	uint64_t value;
+    const char *field_name;
+    const char *option_name;
+    uint64_t mask;
+    uint64_t value;
 };
 ```
 
+
 #### static.c
 
 ```c
 STORAGE struct fw_config __devN_probe_list[] = {
-	{
-		.field_name = FW_CONFIG_FIELD_DAUGHTER_BOARD_NAME,
-		.option_name = FW_CONFIG_FIELD_DAUGHTER_BOARD_OPTION_VARIANT_DB_ONE_NAME,
-		.mask = FW_CONFIG_FIELD_DAUGHTER_BOARD_MASK,
-		.value = FW_CONFIG_FIELD_DAUGHTER_BOARD_OPTION_VARIANT_DB_ONE_VALUE
-	},
-	{
-		.field_name = FW_CONFIG_FIELD_DAUGHTER_BOARD_NAME,
-		.option_name = FW_CONFIG_FIELD_DAUGHTER_BOARD_OPTION_VARIANT_DB_TWO_NAME,
-		.mask = FW_CONFIG_FIELD_DAUGHTER_BOARD_MASK,
-		.value = FW_CONFIG_FIELD_DAUGHTER_BOARD_OPTION_VARIANT_DB_TWO_VALUE
-	},
-	{ }
+    {
+        .field_name = FW_CONFIG_FIELD_DAUGHTER_BOARD_NAME,
+        .option_name = FW_CONFIG_FIELD_DAUGHTER_BOARD_OPTION_VARIANT_DB_ONE_NAME,
+        .mask = FW_CONFIG_FIELD_DAUGHTER_BOARD_MASK,
+        .value = FW_CONFIG_FIELD_DAUGHTER_BOARD_OPTION_VARIANT_DB_ONE_VALUE
+    },
+    {
+        .field_name = FW_CONFIG_FIELD_DAUGHTER_BOARD_NAME,
+        .option_name = FW_CONFIG_FIELD_DAUGHTER_BOARD_OPTION_VARIANT_DB_TWO_NAME,
+        .mask = FW_CONFIG_FIELD_DAUGHTER_BOARD_MASK,
+        .value = FW_CONFIG_FIELD_DAUGHTER_BOARD_OPTION_VARIANT_DB_TWO_VALUE
+    },
+    { }
 };
 ```
 
+
 ### Runtime Probing
 
-The device driver probing allows for seamless integration with the mainboard but it is only
-effective in ramstage and for specific devices declared in devicetree.cb.  There are other
-situations where code may need to probe or check the value of a field in romstage or at other
-points in ramstage.  For this reason it is also possible to use the firmware configuration
-interface directly.
+The device driver probing allows for seamless integration with the
+mainboard but it is only effective in ramstage and for specific devices
+declared in devicetree.cb. There are other situations where code may
+need to probe or check the value of a field in romstage or at other
+points in ramstage. For this reason it is also possible to use the
+firmware configuration interface directly.
 
 ```c
 /**
@@ -372,18 +457,21 @@ bool fw_config_probe(const struct fw_config *match);
 
 The argument provided to this function can be created from a macro for easy use:
 
-	FW_CONFIG(field, option)
+```text
+    FW_CONFIG(field, option)
+```
 
-This example has a mainboard check if a feature is disabled and set an FSP UPD before memory
-training.  This example expects that the default value of this `register` is set to `true` in
-`devicetree.cb` and this code is disabling that feature before FSP is executed.
+This example has a mainboard check if a feature is disabled and set an
+FSP UPD before memory training. This example expects that the default
+value of this `register` is set to `true` in `devicetree.cb` and this
+code is disabling that feature before FSP is executed.
 
 ```c
 #include <fw_config.h>
 
 void mainboard_memory_init_params(FSPM_UPD *mupd)
 {
-	if (fw_config_probe(FW_CONFIG(FEATURE, DISABLED))
-		mupd->ExampleFeature = false;
+    if (fw_config_probe(FW_CONFIG(FEATURE, DISABLED))
+        mupd->ExampleFeature = false;
 }
 ```

From b4f6e9a2ec1e3302c50d633970769c6a2de41b4f Mon Sep 17 00:00:00 2001
From: Mike Lin <mike.lin@mediatek.corp-partner.google.com>
Date: Fri, 29 Nov 2024 15:21:23 +0800
Subject: [PATCH 0688/3886] mb/google/skywalker: Add DRAM calibration init
 entry

Add DRAM calibration entry in romstage.

BUG=b:379008996
BRANCH=none
TEST=Boot up pass
3200 LPDDR5 chan0(x16) rank0: memory test pass
3200 LPDDR5 chan0(x16) rank1: memory test pass
3200 LPDDR5 chan1(x16) rank0: memory test pass
3200 LPDDR5 chan1(x16) rank1: memory test pass

Signed-off-by: Mike Lin <mike.lin@mediatek.corp-partner.google.com>
Change-Id: Iabdcabefc77a262c548019e801daf5b269eaa97a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87038
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/google/skywalker/romstage.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/src/mainboard/google/skywalker/romstage.c b/src/mainboard/google/skywalker/romstage.c
index 7758dfaaf8..74cfb1bbd6 100644
--- a/src/mainboard/google/skywalker/romstage.c
+++ b/src/mainboard/google/skywalker/romstage.c
@@ -1,8 +1,9 @@
 /* SPDX-License-Identifier: GPL-2.0-only OR MIT */
 
 #include <arch/stages.h>
+#include <soc/emi.h>
 
 void platform_romstage_main(void)
 {
-	/* TODO: add romstage main function */
+	mtk_dram_init();
 }

From d921e873b848e6b140a1793960c0e31dc08fc0d2 Mon Sep 17 00:00:00 2001
From: Mike Lin <mike.lin@mediatek.corp-partner.google.com>
Date: Wed, 25 Dec 2024 17:52:17 +0800
Subject: [PATCH 0689/3886] soc/mediatek/mt8189: Reserve DRAM buffers for HW TX
 TRACKING

HW TX tracking works by writing a pattern to the designated DRAM buffer
and then reading it back automatically to calculate the appropriate TX
time delay. To avoid writing the pattern to system-used memory, we need
to permanently reserve last 64KB memory on each rank for the HW TX
tracking feature.

BUG=b:379008996
BRANCH=none
TEST=Reserve memory ok
Firmware shows the following log :
000000013fff0000-000000013fffffff: RESERVED
000000023fff0000-000000023fffffff: RESERVED

Signed-off-by: Mike Lin <mike.lin@mediatek.corp-partner.google.com>
Change-Id: I2ecfe42dc9f1882163d03f50cf9b5ff8e98c2972
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87039
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
---
 src/soc/mediatek/mt8189/Makefile.mk | 1 +
 src/soc/mediatek/mt8189/soc.c       | 7 +++++++
 2 files changed, 8 insertions(+)

diff --git a/src/soc/mediatek/mt8189/Makefile.mk b/src/soc/mediatek/mt8189/Makefile.mk
index bdee1fb33e..7631bc6118 100644
--- a/src/soc/mediatek/mt8189/Makefile.mk
+++ b/src/soc/mediatek/mt8189/Makefile.mk
@@ -19,6 +19,7 @@ romstage-y += ../common/emi.c
 romstage-y += ../common/memory.c ../common/memory_test.c
 romstage-y += ../common/mmu_operations.c ../common/mmu_cmops.c
 
+ramstage-y += ../common/dramc_info.c
 ramstage-y += ../common/emi.c
 ramstage-y += ../common/memory.c
 ramstage-y += ../common/mmu_operations.c ../common/mmu_cmops.c
diff --git a/src/soc/mediatek/mt8189/soc.c b/src/soc/mediatek/mt8189/soc.c
index e4dfc2312a..e53136d16b 100644
--- a/src/soc/mediatek/mt8189/soc.c
+++ b/src/soc/mediatek/mt8189/soc.c
@@ -1,9 +1,16 @@
 /* SPDX-License-Identifier: GPL-2.0-only OR MIT */
 
+#include <bootmem.h>
 #include <device/device.h>
+#include <soc/dramc_info.h>
 #include <soc/emi.h>
 #include <symbols.h>
 
+void bootmem_platform_add_ranges(void)
+{
+	reserve_buffer_for_dramc();
+}
+
 static void soc_read_resources(struct device *dev)
 {
 	ram_range(dev, 0, (uintptr_t)_dram, sdram_size());

From aff5ddc3610bbd13006a3689559382be11be33b3 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Micha=C5=82=20=C5=BBygowski?= <michal.zygowski@3mdeb.com>
Date: Mon, 31 Mar 2025 15:47:26 +0200
Subject: [PATCH 0690/3886] mainboard/protectli/vault_ehl/Kconfig: Configure
 TPM PIRQ
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

The board uses GPP_G19 as GPIO interrupt for SPI dTPM. The pad
is already configured as APIC interrupt, so simply define the
TPM_PIRQ to GPP_G19_IRQ, which is 0x6B for Elkhart Lake.

TEST=Boot Ubuntu 24.04 and check dmesg that Linux does not
complain on TPM interrupt not working. Check Windows Device
Manager does not report any problem with TPM and its resources.

Change-Id: Ia23319680cff927f10b44d7a5d07928cc30dbc9d
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87051
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/protectli/vault_ehl/Kconfig | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/src/mainboard/protectli/vault_ehl/Kconfig b/src/mainboard/protectli/vault_ehl/Kconfig
index 5f283eed32..c9d4d18d1b 100644
--- a/src/mainboard/protectli/vault_ehl/Kconfig
+++ b/src/mainboard/protectli/vault_ehl/Kconfig
@@ -49,4 +49,7 @@ config VBOOT_SLOTS_RW_A
 config FMDFILE
 	default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/vboot-rwa.fmd" if VBOOT && VBOOT_SLOTS_RW_A
 
+config TPM_PIRQ
+	default 0x6B # GPP_G19_IRQ
+
 endif # BOARD_PROTECTLI_VP2420

From 3e0f35b23a132e51bb37c81b60f5aa2bb576ec1d Mon Sep 17 00:00:00 2001
From: Alicja Michalska <alicja.michalska@9elements.com>
Date: Thu, 23 Jan 2025 19:41:32 +0100
Subject: [PATCH 0691/3886] device/Kconfig: Make option to allocate above 4G
 appear in Kconfig

Previously only tested on server platforms - it wasn't working correctly
on consumer platforms due to missing boolean.

This patch fixes it, which makes resource allocator use uint64 instead
of uint32. Thanks to that, modern GPUs like Intel Arc or Radeon RX now
work correctly with ReBAR enabled, and correctly initialize the
framebuffer in payload (i.e EDK2) after initializing the OpROMs.

Example of issue caused by resource allocator using uint32 (Intel Arc
A580):
[ERROR]  Resource didn't fit!!!
[ERROR]  PCI: 00:01:00.0 10 prefmem64 size: 0x0000800000 not assigned
[ERROR]  PCI: 00:03:00.0 18 prefmem64 size: 0x0200000000 not assigned

(Followed by Linux reporting that BAR space was limited to 256MB, which
severely hindered the performance).

TESTed on Intel Tiger Lake-H (mb/erying/tgl) with Intel Arc A580 and AMD
Radeon RX7800XT.

Change-Id: Ia17b3312016409d8fd6bcce4321481a7b7e35ce5
Signed-off-by: Alicja Michalska <alicja.michalska@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86131
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
---
 src/device/Kconfig | 7 ++++++-
 1 file changed, 6 insertions(+), 1 deletion(-)

diff --git a/src/device/Kconfig b/src/device/Kconfig
index af3fe80a59..bfb38b442f 100644
--- a/src/device/Kconfig
+++ b/src/device/Kconfig
@@ -1005,10 +1005,15 @@ config RESOURCE_ALLOCATION_TOP_DOWN
 
 config ALWAYS_ALLOW_ABOVE_4G_ALLOCATION
 	bool
+	prompt "Extend resource window for PCIe devices above 4G" if ARCH_X86
 	default n if ARCH_X86
 	default y
 	help
-	  Don't limit mem resources to 4G, but to their actual limit.
+	  This option extends PCIe resource allocation beyond the 4G limit.
+	  Required for modern graphics cards that support resizable BAR, such as
+	  Intel Arc or AMD RX series.
+	  Please keep in mind that not all payloads support it
+	  (i.e: LinuxBoot and EDK2 do, GRUB doesn't).
 
 config XHCI_UTILS
 	def_bool n

From 68da65b2a5a06a475587ad62d905ac9e24a316d9 Mon Sep 17 00:00:00 2001
From: Weimin Wu <wuweimin@huaqin.corp-partner.google.com>
Date: Thu, 12 Dec 2024 20:58:17 +0800
Subject: [PATCH 0692/3886] drivers/soundwire: Support Realtek ALC712 codec

Update SoundWire driver to support ALC712 audio codec.

reference datasheet: Realtek ALC712-VB-CG Rev. 0.24

BUG=b:378629979
TEST=emerge-fatcat coreboot
A sound can be heard from the speaker,
the test instructions are as follows:

amixer -c 0 cset name='rt712 OT23 L Switch' on
amixer -c 0 cset name=''rt712 OT23 R Switch' on
amixer -c 0 cset name='rt1320-1 OT23 L Switch' on
amixer -c 0 cset name='rt1320-1 OT23 R Switch' on
amixer -c 0 cset name='Speaker Switch' on

speaker-test -D hw:0,2 -c 2 -t sine -f 440

Change-Id: Ib79896a9fe23f2f66d6ee3a24f5a62bfa0f7a649
Signed-off-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85571
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Mac Chiang <mac.chiang@intel.com>
---
 src/drivers/soundwire/alc711/alc711.c | 21 ++++++++++++++++++++-
 src/drivers/soundwire/alc711/chip.h   |  2 ++
 src/include/mipi/ids.h                |  1 +
 3 files changed, 23 insertions(+), 1 deletion(-)

diff --git a/src/drivers/soundwire/alc711/alc711.c b/src/drivers/soundwire/alc711/alc711.c
index 83552c4ea1..c698000266 100644
--- a/src/drivers/soundwire/alc711/alc711.c
+++ b/src/drivers/soundwire/alc711/alc711.c
@@ -10,6 +10,9 @@
 
 #include "chip.h"
 
+static struct soundwire_multilane alc711_multilane = {
+};
+
 static struct soundwire_slave alc711_slave = {
 	.wake_up_unavailable = false,
 	.test_mode_supported = false,
@@ -87,7 +90,8 @@ static const struct soundwire_codec alc711_codec = {
 			.port = 2,
 			.source = &alc711_dp
 		}
-	}
+	},
+	.multilane = &alc711_multilane
 
 };
 
@@ -96,6 +100,7 @@ static void soundwire_alc711_fill_ssdt(const struct device *dev)
 	struct drivers_soundwire_alc711_config *config = dev->chip_info;
 	const char *scope = acpi_device_scope(dev);
 	struct acpi_dp *dsd;
+	size_t lane_mapping_count, audio_mode_count;
 
 	if (!scope)
 		return;
@@ -112,6 +117,20 @@ static void soundwire_alc711_fill_ssdt(const struct device *dev)
 	acpigen_write_name_string("_DDN", config->desc ? : dev->chip_ops->name);
 	acpigen_write_STA(acpi_device_status(dev));
 
+	/* Overlay multilane config, if provided. */
+	lane_mapping_count = MIN(ARRAY_SIZE(config->multilane.lane_mapping), SOUNDWIRE_MAX_LANE);
+	if (lane_mapping_count > 0) {
+		alc711_multilane.lane_mapping_count = lane_mapping_count;
+		memcpy(&alc711_multilane.lane_mapping, &config->multilane.lane_mapping,
+			sizeof(struct soundwire_multilane_map) * lane_mapping_count);
+	}
+
+	/* Overlay Audio Mode config, if provided. */
+	audio_mode_count = MIN(ARRAY_SIZE(config->audio_mode), SOUNDWIRE_MAX_MODE);
+	if (audio_mode_count > 0)
+		/* Currently only 1 audio mode is supported. */
+		memcpy(&alc711_audio_mode, &config->audio_mode, sizeof(struct soundwire_audio_mode));
+
 	dsd = acpi_dp_new_table("_DSD");
 	soundwire_gen_codec(dsd, &alc711_codec, NULL);
 	acpi_dp_write(dsd);
diff --git a/src/drivers/soundwire/alc711/chip.h b/src/drivers/soundwire/alc711/chip.h
index c6282092cd..8b0230e6d1 100644
--- a/src/drivers/soundwire/alc711/chip.h
+++ b/src/drivers/soundwire/alc711/chip.h
@@ -10,6 +10,8 @@ struct drivers_soundwire_alc711_config {
 	const char *name;
 	const char *desc;
 	struct soundwire_address alc711_address;
+	struct soundwire_audio_mode audio_mode[SOUNDWIRE_MAX_MODE];
+	struct soundwire_multilane multilane;
 };
 
 #endif /* __DRIVERS_SOUNDWIRE_ALC711_CHIP_H__ */
diff --git a/src/include/mipi/ids.h b/src/include/mipi/ids.h
index c5d19ba22d..5118a13cf0 100644
--- a/src/include/mipi/ids.h
+++ b/src/include/mipi/ids.h
@@ -21,6 +21,7 @@
 #define MIPI_MFG_ID_REALTEK			0x025d
 #define MIPI_DEV_ID_REALTEK_ALC5682		0x5682
 #define MIPI_DEV_ID_REALTEK_ALC711		0x0711
+#define MIPI_DEV_ID_REALTEK_ALC712		0x0712
 #define MIPI_DEV_ID_REALTEK_ALC721		0x0721
 #define MIPI_DEV_ID_REALTEK_ALC722		0x0722
 #define MIPI_DEV_ID_REALTEK_ALC1308             0x1308

From 9e757b33967fe3626333613daab039f58103e53d Mon Sep 17 00:00:00 2001
From: Weimin Wu <wuweimin@huaqin.corp-partner.google.com>
Date: Thu, 12 Dec 2024 21:09:18 +0800
Subject: [PATCH 0693/3886] mb/google/fatcat/var/felino: Add ALC712 codec to
 devicetree

Update device tree to support Realtek ALC712 codec.

reference datasheet: Realtek ALC712-VB-CG Rev. 0.24

BUG=b:378629979
TEST=emerge-fatcat coreboot
check the ssdt dump PCI0.HDAS.SNDW has address: 0x000330025d071201

Change-Id: Ic5c38462cd1ab39d4aebc324d5151cb4337051df
Signed-off-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85572
Reviewed-by: Jayvik Desai <jayvik@google.com>
Reviewed-by: Pranava Y N <pranavayn@google.com>
Reviewed-by: Mac Chiang <mac.chiang@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 .../fatcat/variants/felino/overridetree.cb    | 45 +++++++++++++++++--
 1 file changed, 42 insertions(+), 3 deletions(-)

diff --git a/src/mainboard/google/fatcat/variants/felino/overridetree.cb b/src/mainboard/google/fatcat/variants/felino/overridetree.cb
index b3b63e7b5c..29a178dc7f 100644
--- a/src/mainboard/google/fatcat/variants/felino/overridetree.cb
+++ b/src/mainboard/google/fatcat/variants/felino/overridetree.cb
@@ -253,10 +253,49 @@ device ref tbt_pcie_rp0 on end
 			chip drivers/intel/soundwire
 				device generic 0 on
 					chip drivers/soundwire/alc711
-						# SoundWire Link 3 ID 1
+						register "multilane.lane_mapping" = "{
+							{
+								.lane = 1,
+								.direction = MASTER_LANE,
+								.connection.master_lane = 1
+							},
+							{
+								.lane = 2,
+								.direction = MASTER_LANE,
+								.connection.master_lane = 2
+							},
+						}"
+						register "audio_mode" = "{
+							{
+								.bus_frequency_configs_count = 9,
+								.bus_frequency_configs = {
+									9600 * KHz,
+									4800 * KHz,
+									2400 * KHz,
+									12000 * KHz,
+									6000 * KHz,
+									3000 * KHz,
+									12288 * KHz,
+									6144 * KHz,
+									3072 * KHz,
+								},
+								/* Support 16 KHz to 192 KHz sampling frequency */
+								.sampling_frequency_configs_count = 6,
+								.sampling_frequency_configs = {
+									16 * KHz,
+									32 * KHz,
+									44.1 * KHz,
+									48 * KHz,
+									96 * KHz,
+									192 * KHz
+								},
+							},
+						}"
 						register "desc" = ""Headset Codec""
-						device generic 3.1 on
-						end
+						register "alc711_address.version" = "SOUNDWIRE_VERSION_1_2"
+						register "alc711_address.class" = "MIPI_CLASS_SDCA"
+						register "alc711_address.part_id" = "MIPI_DEV_ID_REALTEK_ALC712"
+						device generic 3.0 on end # SoundWire Link 3 ID 0
 					end
 				end
 			end

From b6051e5648bab05efe7cfc5abf1c360b3b01ce1c Mon Sep 17 00:00:00 2001
From: Mac Chiang <mac.chiang@intel.com>
Date: Thu, 20 Mar 2025 17:19:02 +0800
Subject: [PATCH 0694/3886] drivers/soundwire/alc1320: use common struct to set
 soundwire ADDR_

Add common soundwire address struct for acpi table configuration
over overridetree.

refer to:
commit 2411942a0518 ("drivers/soundwire/alc711: Add common Kconfig
for ALC7xx soundwire codecs")

BUG=b:378629979
TEST=emerge-fatcat coreboot
check the ssdt dump PCI0.HDAS.SNDW has address: 0x000331025D132001

Change-Id: I2d3531eef6adf21a28a26dcc3ac1bb7830877905
Signed-off-by: Mac Chiang <mac.chiang@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86939
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com>
Reviewed-by: Pranava Y N <pranavayn@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
---
 src/drivers/soundwire/alc1320/alc1320.c | 14 ++++----------
 src/drivers/soundwire/alc1320/chip.h    |  4 ++++
 2 files changed, 8 insertions(+), 10 deletions(-)

diff --git a/src/drivers/soundwire/alc1320/alc1320.c b/src/drivers/soundwire/alc1320/alc1320.c
index 1362675f54..10c58e1ecb 100644
--- a/src/drivers/soundwire/alc1320/alc1320.c
+++ b/src/drivers/soundwire/alc1320/alc1320.c
@@ -10,13 +10,6 @@
 
 #include "chip.h"
 
-static struct soundwire_address alc1320_address = {
-	.version = SOUNDWIRE_VERSION_1_2,
-	.manufacturer_id = MIPI_MFG_ID_REALTEK,
-	.part_id = MIPI_DEV_ID_REALTEK_ALC1320,
-	.class = MIPI_CLASS_NONE
-};
-
 static struct soundwire_slave alc1320_slave = {
 	.wake_up_unavailable = false,
 	.test_mode_supported = false,
@@ -106,10 +99,11 @@ static void soundwire_alc1320_fill_ssdt(const struct device *dev)
 	acpigen_write_device(acpi_device_name(dev));
 
 	/* Set codec address IDs. */
-	alc1320_address.link_id = dev->path.generic.id;
-	alc1320_address.unique_id = dev->path.generic.subid;
+	config->alc1320_address.link_id = dev->path.generic.id;
+	config->alc1320_address.unique_id = dev->path.generic.subid;
+	config->alc1320_address.manufacturer_id = MIPI_MFG_ID_REALTEK;
 
-	acpigen_write_ADR_soundwire_device(&alc1320_address);
+	acpigen_write_ADR_soundwire_device(&config->alc1320_address);
 	acpigen_write_name_string("_DDN", config->desc ? : dev->chip_ops->name);
 	acpigen_write_STA(acpi_device_status(dev));
 
diff --git a/src/drivers/soundwire/alc1320/chip.h b/src/drivers/soundwire/alc1320/chip.h
index 028c200219..4278aef0ba 100644
--- a/src/drivers/soundwire/alc1320/chip.h
+++ b/src/drivers/soundwire/alc1320/chip.h
@@ -3,9 +3,13 @@
 #ifndef __DRIVERS_SOUNDWIRE_ALC1320_CHIP_H__
 #define __DRIVERS_SOUNDWIRE_ALC1320_CHIP_H__
 
+#include <device/soundwire.h>
+#include <mipi/ids.h>
+
 struct drivers_soundwire_alc1320_config {
 	const char *name;
 	const char *desc;
+	struct soundwire_address alc1320_address;
 };
 
 #endif /* __DRIVERS_SOUNDWIRE_ALC1320_CHIP_H__ */

From 9ee23a1b1011f82c58dc294de732fdecb6ed04ca Mon Sep 17 00:00:00 2001
From: Weimin Wu <wuweimin@huaqin.corp-partner.google.com>
Date: Thu, 6 Mar 2025 16:23:48 +0800
Subject: [PATCH 0695/3886] mb/google/fatcat/var/felino: Add ALC1320 codec to
 devicetree

Update devicetree to support Realtek ALC1320 codec.
The ALC1320 soundwire class_id is MIPI_CLASS_SDCA(1).

BUG=b:378629979
TEST=emerge-fatcat coreboot
check the ssdt dump PCI0.HDAS.SNDW including 0x000331025D132001

Change-Id: Ie8763888810f56eb45523e3bcf7ef082900b1225
Signed-off-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86747
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Mac Chiang <mac.chiang@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jayvik Desai <jayvik@google.com>
Reviewed-by: Pranava Y N <pranavayn@google.com>
---
 src/mainboard/google/fatcat/Kconfig                        | 1 +
 .../google/fatcat/variants/felino/overridetree.cb          | 7 +++++++
 2 files changed, 8 insertions(+)

diff --git a/src/mainboard/google/fatcat/Kconfig b/src/mainboard/google/fatcat/Kconfig
index 08a5eba912..d24f3c0294 100644
--- a/src/mainboard/google/fatcat/Kconfig
+++ b/src/mainboard/google/fatcat/Kconfig
@@ -84,6 +84,7 @@ config BOARD_GOOGLE_FELINO
 	select BOARD_GOOGLE_BASEBOARD_FATCAT
 	select FSP_UGOP_EARLY_SIGN_OF_LIFE
 	select HAVE_SLP_S0_GATE
+	select DRIVERS_SOUNDWIRE_ALC1320
 	select MAINBOARD_HAS_GOOGLE_STRAUSS_KEYBOARD
 
 config BOARD_GOOGLE_FRANCKA
diff --git a/src/mainboard/google/fatcat/variants/felino/overridetree.cb b/src/mainboard/google/fatcat/variants/felino/overridetree.cb
index 29a178dc7f..ff7d07a2c2 100644
--- a/src/mainboard/google/fatcat/variants/felino/overridetree.cb
+++ b/src/mainboard/google/fatcat/variants/felino/overridetree.cb
@@ -297,6 +297,13 @@ device ref tbt_pcie_rp0 on end
 						register "alc711_address.part_id" = "MIPI_DEV_ID_REALTEK_ALC712"
 						device generic 3.0 on end # SoundWire Link 3 ID 0
 					end
+					chip drivers/soundwire/alc1320
+						register "desc" = ""Speaker Amp""
+						register "alc1320_address.version" = "SOUNDWIRE_VERSION_1_2"
+						register "alc1320_address.class" = "MIPI_CLASS_SDCA"
+						register "alc1320_address.part_id" = "MIPI_DEV_ID_REALTEK_ALC1320"
+						device generic 3.1 on end # SoundWire Link 3 ID 1
+					end
 				end
 			end
 		end

From 149f0c750c6bc448c4858370c5a3cc2bb1b9d0f0 Mon Sep 17 00:00:00 2001
From: Yu-Ping Wu <yupingso@chromium.org>
Date: Wed, 9 Apr 2025 07:44:23 +0800
Subject: [PATCH 0696/3886] Documentation,util: Run util_readme.sh to regen
 *.md

As CB:71757 [1] updates Documentation/util.md and util/README.md
manually without modifying util/intelp2m/description.md, we port the
description changes back to that file.

[1] commit da54bd60af60 ("Documentation: Update information about
    intelp2m")

Change-Id: I3d3f87517c445d650e9cea61448b28d005d46737
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87224
Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
---
 Documentation/util.md        | 4 ++--
 util/README.md               | 4 ++--
 util/intelp2m/description.md | 4 ++--
 3 files changed, 6 insertions(+), 6 deletions(-)

diff --git a/Documentation/util.md b/Documentation/util.md
index e6d1402c8a..341a4c5751 100644
--- a/Documentation/util.md
+++ b/Documentation/util.md
@@ -70,8 +70,8 @@ into a format which can be used in coreboot's verb table `Go`
 `C`
 * __intelmetool__ - Dump interesting things about Management Engine
 even if hidden `C`
-* __intelp2m__ - Convert the inteltool register dump to gpio.h with GPIO
-configuration for porting coreboot to your motherboard. `Go`
+* __intelp2m__ - Convert the inteltool register dump to gpio.h with
+GPIO configuration for porting coreboot to your motherboard. `Go`
 * __inteltool__ - Provides information about the Intel CPU/chipset
 hardware configuration (register contents, MSRs, etc). `C`
 * __intelvbttool__ - Parse VBT from VGA BIOS `C`
diff --git a/util/README.md b/util/README.md
index 6d58d7a71b..f40036babf 100644
--- a/util/README.md
+++ b/util/README.md
@@ -61,8 +61,8 @@ into a format which can be used in coreboot's verb table `Go`
 `C`
 * __intelmetool__ - Dump interesting things about Management Engine
 even if hidden `C`
-* __intelp2m__ - Generate a GPIO configuration based on a register dump
-obtained using inteltool. `Go`
+* __intelp2m__ - Convert the inteltool register dump to gpio.h with
+GPIO configuration for porting coreboot to your motherboard. `Go`
 * __inteltool__ - Provides information about the Intel CPU/chipset
 hardware configuration (register contents, MSRs, etc). `C`
 * __intelvbttool__ - Parse VBT from VGA BIOS `C`
diff --git a/util/intelp2m/description.md b/util/intelp2m/description.md
index 5d718b02d9..b6cf527404 100644
--- a/util/intelp2m/description.md
+++ b/util/intelp2m/description.md
@@ -1,2 +1,2 @@
-convert the configuration DW0/1 registers value from an inteltool dump
-to coreboot macros. `go`
+Convert the inteltool register dump to gpio.h with GPIO configuration
+for porting coreboot to your motherboard. `Go`

From 38f1e758ffa159449a540ee89c54f771d566c787 Mon Sep 17 00:00:00 2001
From: Yu-Ping Wu <yupingso@chromium.org>
Date: Wed, 9 Apr 2025 07:39:39 +0800
Subject: [PATCH 0697/3886] util/mtkheader: Rename to util/mediatek

To allow adding more scripts to the util/mtkheader folder, rename it to
util/mediatek. Also update description.md and regenerate
Documentation/util.md and util/README.md by util_readme.sh.

Change-Id: Ibc6ef9dddc541d2dd471898af431cadde231edca
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87225
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
---
 Documentation/util.md                      | 4 +++-
 src/soc/mediatek/mt8173/Makefile.mk        | 2 +-
 src/soc/mediatek/mt8183/Makefile.mk        | 2 +-
 src/soc/mediatek/mt8186/Makefile.mk        | 2 +-
 src/soc/mediatek/mt8188/Makefile.mk        | 2 +-
 src/soc/mediatek/mt8189/Makefile.mk        | 2 +-
 src/soc/mediatek/mt8192/Makefile.mk        | 2 +-
 src/soc/mediatek/mt8195/Makefile.mk        | 2 +-
 src/soc/mediatek/mt8196/Makefile.mk        | 2 +-
 util/README.md                             | 4 +++-
 util/cbfstool/platform_fixups.c            | 2 +-
 util/mediatek/description.md               | 2 ++
 util/{mtkheader => mediatek}/gen-bl-img.py | 0
 util/mtkheader/description.md              | 1 -
 14 files changed, 17 insertions(+), 12 deletions(-)
 create mode 100644 util/mediatek/description.md
 rename util/{mtkheader => mediatek}/gen-bl-img.py (100%)
 delete mode 100644 util/mtkheader/description.md

diff --git a/Documentation/util.md b/Documentation/util.md
index 341a4c5751..ba4618fa69 100644
--- a/Documentation/util.md
+++ b/Documentation/util.md
@@ -87,9 +87,11 @@ image for testing purposes and for working on firmware. `Bash`
 * __marvell__ - Add U-Boot boot loader for Marvell ARMADA38X `C`
 * __[me_cleaner](https://github.com/corna/me_cleaner)__ - Tool for
 partial deblobbing of Intel ME/TXE firmware images `Python`
+* __mediatek__
+	* gen-bl-img.py - Generate MediaTek bootloader header.
+`Python3`
 * __mma__ - Memory Margin Analysis automation tests `Bash`
 * __msrtool__ - Dumps chipset-specific MSR registers. `C`
-* __mtkheader__ - Generate MediaTek bootload header. `Python3`
 * __nvidia__ - nvidia blob parsers
 * __nvramtool__ - Reads and writes coreboot parameters and displaying
 information from the coreboot table in CMOS/NVRAM. `C`
diff --git a/src/soc/mediatek/mt8173/Makefile.mk b/src/soc/mediatek/mt8173/Makefile.mk
index ee698b72ff..49861a71ac 100644
--- a/src/soc/mediatek/mt8173/Makefile.mk
+++ b/src/soc/mediatek/mt8173/Makefile.mk
@@ -79,7 +79,7 @@ BL31_MAKEARGS += PLAT=mt8173
 
 # Generate the actual coreboot bootblock code
 $(objcbfs)/bootblock.bin: $(objcbfs)/bootblock.raw.bin
-	./util/mtkheader/gen-bl-img.py mt8173 sf $< $@
+	./util/mediatek/gen-bl-img.py mt8173 sf $< $@
 
 CPPFLAGS_common += -Isrc/soc/mediatek/mt8173/include
 CPPFLAGS_common += -Isrc/soc/mediatek/common/include
diff --git a/src/soc/mediatek/mt8183/Makefile.mk b/src/soc/mediatek/mt8183/Makefile.mk
index bd50780045..c1fd3b8a7a 100644
--- a/src/soc/mediatek/mt8183/Makefile.mk
+++ b/src/soc/mediatek/mt8183/Makefile.mk
@@ -96,6 +96,6 @@ CPPFLAGS_common += -Isrc/soc/mediatek/mt8183/include
 CPPFLAGS_common += -Isrc/soc/mediatek/common/include
 
 $(objcbfs)/bootblock.bin: $(objcbfs)/bootblock.raw.bin
-	./util/mtkheader/gen-bl-img.py mt8183 emmc $< $@
+	./util/mediatek/gen-bl-img.py mt8183 emmc $< $@
 
 endif
diff --git a/src/soc/mediatek/mt8186/Makefile.mk b/src/soc/mediatek/mt8186/Makefile.mk
index ea4bcfc25a..c6c47fdd92 100644
--- a/src/soc/mediatek/mt8186/Makefile.mk
+++ b/src/soc/mediatek/mt8186/Makefile.mk
@@ -81,6 +81,6 @@ $(DRAM_CBFS)-compression := $(CBFS_PRERAM_COMPRESS_FLAG)
 cbfs-files-y += $(DRAM_CBFS)
 
 $(objcbfs)/bootblock.bin: $(objcbfs)/bootblock.raw.bin
-	./util/mtkheader/gen-bl-img.py mt8183 sf $< $@
+	./util/mediatek/gen-bl-img.py mt8183 sf $< $@
 
 endif
diff --git a/src/soc/mediatek/mt8188/Makefile.mk b/src/soc/mediatek/mt8188/Makefile.mk
index 2c8379ec57..dc6b649299 100644
--- a/src/soc/mediatek/mt8188/Makefile.mk
+++ b/src/soc/mediatek/mt8188/Makefile.mk
@@ -91,6 +91,6 @@ $(DRAM_CBFS)-compression := $(CBFS_PRERAM_COMPRESS_FLAG)
 cbfs-files-y += $(DRAM_CBFS)
 
 $(objcbfs)/bootblock.bin: $(objcbfs)/bootblock.raw.bin
-	./util/mtkheader/gen-bl-img.py mt8183 sf $< $@
+	./util/mediatek/gen-bl-img.py mt8183 sf $< $@
 
 endif
diff --git a/src/soc/mediatek/mt8189/Makefile.mk b/src/soc/mediatek/mt8189/Makefile.mk
index 7631bc6118..592734f9e4 100644
--- a/src/soc/mediatek/mt8189/Makefile.mk
+++ b/src/soc/mediatek/mt8189/Makefile.mk
@@ -39,6 +39,6 @@ ifneq ($(wildcard $($(DRAM_CBFS)-file)),)
 	cbfs-files-y += $(DRAM_CBFS)
 endif
 $(objcbfs)/bootblock.bin: $(objcbfs)/bootblock.raw.bin
-	./util/mtkheader/gen-bl-img.py mt8189 sf $< $@
+	./util/mediatek/gen-bl-img.py mt8189 sf $< $@
 
 endif
diff --git a/src/soc/mediatek/mt8192/Makefile.mk b/src/soc/mediatek/mt8192/Makefile.mk
index b2c3ced1ad..90a4e6d807 100644
--- a/src/soc/mediatek/mt8192/Makefile.mk
+++ b/src/soc/mediatek/mt8192/Makefile.mk
@@ -83,6 +83,6 @@ $(DRAM_CBFS)-compression := $(CBFS_PRERAM_COMPRESS_FLAG)
 cbfs-files-y += $(DRAM_CBFS)
 
 $(objcbfs)/bootblock.bin: $(objcbfs)/bootblock.raw.bin
-	./util/mtkheader/gen-bl-img.py mt8183 sf $< $@
+	./util/mediatek/gen-bl-img.py mt8183 sf $< $@
 
 endif
diff --git a/src/soc/mediatek/mt8195/Makefile.mk b/src/soc/mediatek/mt8195/Makefile.mk
index ecc69657f9..c460d5894f 100644
--- a/src/soc/mediatek/mt8195/Makefile.mk
+++ b/src/soc/mediatek/mt8195/Makefile.mk
@@ -101,6 +101,6 @@ $(DRAM_CBFS)-compression := $(CBFS_PRERAM_COMPRESS_FLAG)
 cbfs-files-y += $(DRAM_CBFS)
 
 $(objcbfs)/bootblock.bin: $(objcbfs)/bootblock.raw.bin
-	./util/mtkheader/gen-bl-img.py mt8183 sf $< $@
+	./util/mediatek/gen-bl-img.py mt8183 sf $< $@
 
 endif
diff --git a/src/soc/mediatek/mt8196/Makefile.mk b/src/soc/mediatek/mt8196/Makefile.mk
index fa0e3fe0be..903f57b01b 100644
--- a/src/soc/mediatek/mt8196/Makefile.mk
+++ b/src/soc/mediatek/mt8196/Makefile.mk
@@ -135,6 +135,6 @@ $(FSP_RAMSTAGE_CBFS)-compression := $(CBFS_COMPRESS_FLAG)
 cbfs-files-y += $(FSP_RAMSTAGE_CBFS)
 
 $(objcbfs)/bootblock.bin: $(objcbfs)/bootblock.raw.bin
-	./util/mtkheader/gen-bl-img.py mt8196 sf $< $@
+	./util/mediatek/gen-bl-img.py mt8196 sf $< $@
 
 endif
diff --git a/util/README.md b/util/README.md
index f40036babf..7c9394794a 100644
--- a/util/README.md
+++ b/util/README.md
@@ -78,9 +78,11 @@ image for testing purposes and for working on firmware. `Bash`
 * __marvell__ - Add U-Boot boot loader for Marvell ARMADA38X `C`
 * __[me_cleaner](https://github.com/corna/me_cleaner)__ - Tool for
 partial deblobbing of Intel ME/TXE firmware images `Python`
+* __mediatek__
+	* gen-bl-img.py - Generate MediaTek bootloader header.
+`Python3`
 * __mma__ - Memory Margin Analysis automation tests `Bash`
 * __msrtool__ - Dumps chipset-specific MSR registers. `C`
-* __mtkheader__ - Generate MediaTek bootload header. `Python3`
 * __nvidia__ - nvidia blob parsers
 * __nvramtool__ - Reads and writes coreboot parameters and displaying
 information from the coreboot table in CMOS/NVRAM. `C`
diff --git a/util/cbfstool/platform_fixups.c b/util/cbfstool/platform_fixups.c
index 12a5ad7371..74035bbcd8 100644
--- a/util/cbfstool/platform_fixups.c
+++ b/util/cbfstool/platform_fixups.c
@@ -109,7 +109,7 @@ static int qualcomm_fixup(struct buffer *buffer, size_t offset)
 }
 
 /*
- * MediaTek bootblock.bin layout (see util/mtkheader/gen-bl-img.py):
+ * MediaTek bootblock.bin layout (see util/mediatek/gen-bl-img.py):
  *	header		2048 bytes
  *	gfh info	176 bytes, where bytes 32-35 (in little endian) is the
  *			total size excluding the header (gfh info + data + hash)
diff --git a/util/mediatek/description.md b/util/mediatek/description.md
new file mode 100644
index 0000000000..67ff39022b
--- /dev/null
+++ b/util/mediatek/description.md
@@ -0,0 +1,2 @@
+__mediatek__
+  * gen-bl-img.py - Generate MediaTek bootloader header. `Python3`
diff --git a/util/mtkheader/gen-bl-img.py b/util/mediatek/gen-bl-img.py
similarity index 100%
rename from util/mtkheader/gen-bl-img.py
rename to util/mediatek/gen-bl-img.py
diff --git a/util/mtkheader/description.md b/util/mtkheader/description.md
deleted file mode 100644
index 01c0776c3c..0000000000
--- a/util/mtkheader/description.md
+++ /dev/null
@@ -1 +0,0 @@
-Generate MediaTek bootload header. `Python3`

From 940c97e46cec70accd3bc212cfdfb2748b7a1d8e Mon Sep 17 00:00:00 2001
From: Naresh Solanki <naresh.solanki@9elements.com>
Date: Tue, 8 Apr 2025 23:48:12 +0530
Subject: [PATCH 0698/3886] src/soc/amd/* : Move CPU init in common code

AMD SoC from family 17h share common cpu init code.
Move those to common/block/cpu/noncar/cpu.c

TEST=Build for glinda SoC & check for boot.

Change-Id: If53455f359302f368f7c979defa2c1088c5c2f16
Signed-off-by: Naresh Solanki <naresh.solanki@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87214
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
---
 src/soc/amd/cezanne/cpu.c                        | 12 +-----------
 src/soc/amd/common/block/cpu/noncar/cpu.c        | 13 +++++++++++++
 src/soc/amd/common/block/include/amdblocks/cpu.h |  1 +
 src/soc/amd/genoa_poc/cpu.c                      | 12 +-----------
 src/soc/amd/glinda/cpu.c                         | 12 +-----------
 src/soc/amd/mendocino/cpu.c                      | 12 +-----------
 src/soc/amd/phoenix/cpu.c                        | 12 +-----------
 src/soc/amd/picasso/cpu.c                        | 12 +-----------
 8 files changed, 20 insertions(+), 66 deletions(-)

diff --git a/src/soc/amd/cezanne/cpu.c b/src/soc/amd/cezanne/cpu.c
index 4f39aefc75..52d2e2b704 100644
--- a/src/soc/amd/cezanne/cpu.c
+++ b/src/soc/amd/cezanne/cpu.c
@@ -1,8 +1,6 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
 #include <amdblocks/cpu.h>
-#include <amdblocks/mca.h>
-#include <cpu/amd/microcode.h>
 #include <cpu/cpu.h>
 #include <device/device.h>
 #include <soc/cpu.h>
@@ -10,16 +8,8 @@
 _Static_assert(CONFIG_MAX_CPUS == 16, "Do not override MAX_CPUS. To reduce the number of "
 	"available cores, use the downcore_mode and disable_smt devicetree settings instead.");
 
-static void zen_2_3_init(struct device *dev)
-{
-	check_mca();
-	set_cstate_io_addr();
-
-	amd_apply_microcode_patch();
-}
-
 static struct device_operations cpu_dev_ops = {
-	.init = zen_2_3_init,
+	.init = amd_cpu_init,
 };
 
 static struct cpu_device_id cpu_table[] = {
diff --git a/src/soc/amd/common/block/cpu/noncar/cpu.c b/src/soc/amd/common/block/cpu/noncar/cpu.c
index e67d669bb6..c97e2f4f44 100644
--- a/src/soc/amd/common/block/cpu/noncar/cpu.c
+++ b/src/soc/amd/common/block/cpu/noncar/cpu.c
@@ -1,10 +1,12 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
 #include <amdblocks/cpu.h>
+#include <amdblocks/mca.h>
 #include <arch/cpuid.h>
 #include <cpu/cpu.h>
 #include <cpu/x86/msr.h>
 #include <cpu/amd/cpuid.h>
+#include <cpu/amd/microcode.h>
 #include <cpu/amd/msr.h>
 #include <cpu/amd/mtrr.h>
 #include <smbios.h>
@@ -100,3 +102,14 @@ unsigned int get_reserved_phys_addr_bits(void)
 	return (cpuid_ebx(CPUID_EBX_MEM_ENCRYPT) & CPUID_EBX_MEM_ENCRYPT_ADDR_BITS_MASK) >>
 			CPUID_EBX_MEM_ENCRYPT_ADDR_BITS_SHIFT;
 }
+
+void amd_cpu_init(struct device *dev)
+{
+	if (CONFIG(SOC_AMD_COMMON_BLOCK_MCA_COMMON))
+		check_mca();
+
+	set_cstate_io_addr();
+
+	if (CONFIG(SOC_AMD_COMMON_BLOCK_UCODE))
+		amd_apply_microcode_patch();
+}
diff --git a/src/soc/amd/common/block/include/amdblocks/cpu.h b/src/soc/amd/common/block/include/amdblocks/cpu.h
index 4aa225bda3..ce0b2da816 100644
--- a/src/soc/amd/common/block/include/amdblocks/cpu.h
+++ b/src/soc/amd/common/block/include/amdblocks/cpu.h
@@ -22,5 +22,6 @@ uint32_t get_pstate_latency(void);
 uint32_t get_pstate_core_freq(union pstate_msr pstate_reg);
 uint32_t get_pstate_core_uvolts(union pstate_msr pstate_reg);
 const acpi_cstate_t *get_cstate_config_data(size_t *size);
+void amd_cpu_init(struct device *dev);
 
 #endif /* AMD_BLOCK_CPU_H */
diff --git a/src/soc/amd/genoa_poc/cpu.c b/src/soc/amd/genoa_poc/cpu.c
index 241bec21fd..a91720a842 100644
--- a/src/soc/amd/genoa_poc/cpu.c
+++ b/src/soc/amd/genoa_poc/cpu.c
@@ -1,22 +1,12 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
 #include <amdblocks/cpu.h>
-#include <amdblocks/mca.h>
-#include <cpu/amd/microcode.h>
 #include <cpu/cpu.h>
 #include <device/device.h>
 #include <soc/cpu.h>
 
-static void model_19_init(struct device *dev)
-{
-	check_mca();
-	set_cstate_io_addr();
-
-	amd_apply_microcode_patch();
-}
-
 static struct device_operations cpu_dev_ops = {
-	.init = model_19_init,
+	.init = amd_cpu_init,
 };
 
 static struct cpu_device_id cpu_table[] = {
diff --git a/src/soc/amd/glinda/cpu.c b/src/soc/amd/glinda/cpu.c
index a7161270d2..2dcc3c5d21 100644
--- a/src/soc/amd/glinda/cpu.c
+++ b/src/soc/amd/glinda/cpu.c
@@ -3,8 +3,6 @@
 /* TODO: Update for Glinda */
 
 #include <amdblocks/cpu.h>
-#include <amdblocks/mca.h>
-#include <cpu/amd/microcode.h>
 #include <cpu/cpu.h>
 #include <device/device.h>
 #include <soc/cpu.h>
@@ -12,16 +10,8 @@
 _Static_assert(CONFIG_MAX_CPUS == 24, "Do not override MAX_CPUS. To reduce the number of "
 	"available cores, use the downcore_mode and disable_smt devicetree settings instead.");
 
-static void zen_2_3_init(struct device *dev)
-{
-	check_mca();
-	set_cstate_io_addr();
-
-	amd_apply_microcode_patch();
-}
-
 static struct device_operations cpu_dev_ops = {
-	.init = zen_2_3_init,
+	.init = amd_cpu_init,
 };
 
 static struct cpu_device_id cpu_table[] = {
diff --git a/src/soc/amd/mendocino/cpu.c b/src/soc/amd/mendocino/cpu.c
index 842b04fb25..e2e1f53773 100644
--- a/src/soc/amd/mendocino/cpu.c
+++ b/src/soc/amd/mendocino/cpu.c
@@ -1,8 +1,6 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
 #include <amdblocks/cpu.h>
-#include <amdblocks/mca.h>
-#include <cpu/amd/microcode.h>
 #include <cpu/cpu.h>
 #include <device/device.h>
 #include <soc/cpu.h>
@@ -10,16 +8,8 @@
 _Static_assert(CONFIG_MAX_CPUS == 8, "Do not override MAX_CPUS. To reduce the number of "
 	"available cores, use the downcore_mode and disable_smt devicetree settings instead.");
 
-static void zen_2_3_init(struct device *dev)
-{
-	check_mca();
-	set_cstate_io_addr();
-
-	amd_apply_microcode_patch();
-}
-
 static struct device_operations cpu_dev_ops = {
-	.init = zen_2_3_init,
+	.init = amd_cpu_init,
 };
 
 static struct cpu_device_id cpu_table[] = {
diff --git a/src/soc/amd/phoenix/cpu.c b/src/soc/amd/phoenix/cpu.c
index 05dac9a032..5d15b1dd83 100644
--- a/src/soc/amd/phoenix/cpu.c
+++ b/src/soc/amd/phoenix/cpu.c
@@ -3,8 +3,6 @@
 /* TODO: Update for Phoenix */
 
 #include <amdblocks/cpu.h>
-#include <amdblocks/mca.h>
-#include <cpu/amd/microcode.h>
 #include <cpu/cpu.h>
 #include <device/device.h>
 #include <soc/cpu.h>
@@ -12,16 +10,8 @@
 _Static_assert(CONFIG_MAX_CPUS == 16, "Do not override MAX_CPUS. To reduce the number of "
 	"available cores, use the downcore_mode and disable_smt devicetree settings instead.");
 
-static void zen_2_3_init(struct device *dev)
-{
-	check_mca();
-	set_cstate_io_addr();
-
-	amd_apply_microcode_patch();
-}
-
 static struct device_operations cpu_dev_ops = {
-	.init = zen_2_3_init,
+	.init = amd_cpu_init,
 };
 
 static struct cpu_device_id cpu_table[] = {
diff --git a/src/soc/amd/picasso/cpu.c b/src/soc/amd/picasso/cpu.c
index 4f846293a8..702f626e0a 100644
--- a/src/soc/amd/picasso/cpu.c
+++ b/src/soc/amd/picasso/cpu.c
@@ -1,8 +1,6 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
 #include <amdblocks/cpu.h>
-#include <amdblocks/mca.h>
-#include <cpu/amd/microcode.h>
 #include <cpu/cpu.h>
 #include <device/device.h>
 #include <soc/cpu.h>
@@ -10,16 +8,8 @@
 _Static_assert(CONFIG_MAX_CPUS == 8, "Do not override MAX_CPUS. To reduce the number of "
 	"available cores, use the downcore_mode and disable_smt devicetree settings instead.");
 
-static void model_17_init(struct device *dev)
-{
-	check_mca();
-	set_cstate_io_addr();
-
-	amd_apply_microcode_patch();
-}
-
 static struct device_operations cpu_dev_ops = {
-	.init = model_17_init,
+	.init = amd_cpu_init,
 };
 
 static struct cpu_device_id cpu_table[] = {

From 1158e26a2665b02ccd1a3cef5daeba0dc0dbfcae Mon Sep 17 00:00:00 2001
From: Maximilian Brune <maximilian.brune@9elements.com>
Date: Tue, 4 Feb 2025 15:53:18 +0100
Subject: [PATCH 0699/3886] soc/amd/cezanne/chipset.cb: Enable
 gpp_bridge_[a/b/c] by default

Since FSP doesn't support disabling bridges and has no UPDs for that,
they must be enabled in DT to make sure they are properly initialized
during PCI enumeration as expected by the payload (EDK2 for example).
It might be OK to have them set to off when all devices behind the
bridge are also off and FSP disables those secondary devices.

In general something that cannot be hidden/shut off shouldn't be marked
as such, as later stages (payload/OS) might find it active, but
unconfigured.

Change-Id: Ie34bb2abc0211963b2613d1b50b1767df31c1062
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86272
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
---
 .../google/guybrush/variants/baseboard/devicetree.cb        | 2 ++
 src/soc/amd/cezanne/chipset.cb                              | 6 +++---
 2 files changed, 5 insertions(+), 3 deletions(-)

diff --git a/src/mainboard/google/guybrush/variants/baseboard/devicetree.cb b/src/mainboard/google/guybrush/variants/baseboard/devicetree.cb
index b58dc2ce8d..147112ae00 100644
--- a/src/mainboard/google/guybrush/variants/baseboard/devicetree.cb
+++ b/src/mainboard/google/guybrush/variants/baseboard/devicetree.cb
@@ -350,6 +350,8 @@ chip soc/amd/cezanne
 				end
 			end # Audio
 		end
+		device ref gpp_bridge_b off end  # Internal GPP Bridge 1 to Bus B
+		device ref gpp_bridge_c off end  # Internal GPP Bridge 2 to Bus C
 
 		device ref lpc_bridge on
 			chip ec/google/chromeec
diff --git a/src/soc/amd/cezanne/chipset.cb b/src/soc/amd/cezanne/chipset.cb
index ccce4859d8..14dba64fa7 100644
--- a/src/soc/amd/cezanne/chipset.cb
+++ b/src/soc/amd/cezanne/chipset.cb
@@ -22,7 +22,7 @@ chip soc/amd/cezanne
 		device pci 02.7 alias gpp_bridge_6 off ops amd_external_pcie_gpp_ops end
 
 		device pci 08.0 on end # Dummy device function, do not disable
-		device pci 08.1 alias gpp_bridge_a off  # Internal GPP Bridge 0 to Bus A
+		device pci 08.1 alias gpp_bridge_a on  # Internal GPP Bridge 0 to Bus A
 			ops amd_internal_pcie_gpp_ops
 			device pci 0.0 alias gfx off ops amd_graphics_ops end # Internal GPU (GFX)
 			device pci 0.1 alias gfx_hda off end # Display HD Audio Controller (GFXAZ)
@@ -83,14 +83,14 @@ chip soc/amd/cezanne
 			device pci 0.6 alias hda off end # Audio Processor HD Audio Controller (main AZ)
 			device pci 0.7 alias mp2 off end # Sensor Fusion Hub (MP2)
 		end
-		device pci 08.2 alias gpp_bridge_b off # Internal GPP Bridge 1 to Bus B
+		device pci 08.2 alias gpp_bridge_b on # Internal GPP Bridge 1 to Bus B
 			ops amd_internal_pcie_gpp_ops
 			device pci 0.0 alias sata_0 off end # first SATA controller; AHCI Mode
 			device pci 0.1 alias sata_1 off end # second SATA Controller; SATA Raid/AHCI Mode
 			device pci 0.2 alias xgbe_0 off end # 10 GbE Controller Port 0 (XGBE0)
 			device pci 0.3 alias xgbe_1 off end # 10 GbE Controller Port 1 (XGBE1)
 		end
-		device pci 08.3 alias gpp_bridge_c off # Internal GPP Bridge 2 to Bus C
+		device pci 08.3 alias gpp_bridge_c on # Internal GPP Bridge 2 to Bus C
 			ops amd_internal_pcie_gpp_ops
 			device pci 0.0 alias dummy_function_c off end # PCIe Dummy Function
 			device pci 0.2 alias i2s_ac97 off end # I2S/AC'97 Audio

From f6d40a95644bdb5df8043ba94888d1c29f738731 Mon Sep 17 00:00:00 2001
From: Maximilian Brune <maximilian.brune@9elements.com>
Date: Tue, 25 Feb 2025 16:56:12 +0100
Subject: [PATCH 0700/3886] soc/amd/picasso/chipset.cb: Enable gpp_bridge_[a/b]
 by default

Since FSP doesn't support disabling bridges and has no UPDs for that,
they must be enabled in DT to make sure they are properly initialized
during PCI enumeration as expected by the payload (EDK2 for example).
It might be OK to have them set to off when all devices behind the
bridge are also off and FSP disables those secondary devices.

In general something that cannot be hidden/shut off shouldn't be marked
as such, as later stages (payload/OS) might find it active, but
unconfigured.

Change-Id: I4104a6af00304b0a7c50ba0e09ad19a0ed9d2733
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86598
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 .../google/zork/variants/baseboard/dalboz/devicetree.cb       | 1 +
 .../google/zork/variants/baseboard/trembyle/devicetree.cb     | 1 +
 src/soc/amd/picasso/chipset.cb                                | 4 ++--
 3 files changed, 4 insertions(+), 2 deletions(-)

diff --git a/src/mainboard/google/zork/variants/baseboard/dalboz/devicetree.cb b/src/mainboard/google/zork/variants/baseboard/dalboz/devicetree.cb
index e8b73ca900..4af7231eb9 100644
--- a/src/mainboard/google/zork/variants/baseboard/dalboz/devicetree.cb
+++ b/src/mainboard/google/zork/variants/baseboard/dalboz/devicetree.cb
@@ -344,6 +344,7 @@ chip soc/amd/picasso
 			device ref hda off end # HDA
 			device ref mp2 on end # non-Sensor Fusion Hub device
 		end
+		device ref internal_bridge_b off end # internal bridge to bus B
 		device ref lpc_bridge on
 			chip ec/google/chromeec
 				device pnp 0c09.0 alias cros_ec on
diff --git a/src/mainboard/google/zork/variants/baseboard/trembyle/devicetree.cb b/src/mainboard/google/zork/variants/baseboard/trembyle/devicetree.cb
index d6f2136c81..9b5a4c05db 100644
--- a/src/mainboard/google/zork/variants/baseboard/trembyle/devicetree.cb
+++ b/src/mainboard/google/zork/variants/baseboard/trembyle/devicetree.cb
@@ -370,6 +370,7 @@ chip soc/amd/picasso
 			device ref hda off end # HDA
 			device ref mp2 on end # non-Sensor Fusion Hub device
 		end
+		device ref internal_bridge_b off end # internal bridge to bus B
 		device ref lpc_bridge on
 			chip ec/google/chromeec
 				device pnp 0c09.0 alias cros_ec on
diff --git a/src/soc/amd/picasso/chipset.cb b/src/soc/amd/picasso/chipset.cb
index c11d502f16..a254ceacb5 100644
--- a/src/soc/amd/picasso/chipset.cb
+++ b/src/soc/amd/picasso/chipset.cb
@@ -17,7 +17,7 @@ chip soc/amd/picasso
 		device pci 01.6 alias gpp_bridge_5 off ops amd_external_pcie_gpp_ops end
 		device pci 01.7 alias gpp_bridge_6 off ops amd_external_pcie_gpp_ops end
 		device pci 08.0 on end # Dummy device function, do not disable
-		device pci 08.1 alias internal_bridge_a off  # internal bridge to bus A
+		device pci 08.1 alias internal_bridge_a on  # internal bridge to bus A
 			ops amd_internal_pcie_gpp_ops
 			device pci 0.0 alias gfx off ops amd_graphics_ops end # internal GPU
 			device pci 0.1 alias gfx_hda off end # display HD Audio controller
@@ -32,7 +32,7 @@ chip soc/amd/picasso
 			device pci 0.6 alias hda off end # main HD Audio Controller
 			device pci 0.7 alias mp2 off end # sensor fusion hub (MP2)
 		end
-		device pci 08.2 alias internal_bridge_b off # internal bridge to bus B
+		device pci 08.2 alias internal_bridge_b on # internal bridge to bus B
 			ops amd_internal_pcie_gpp_ops
 			device pci 0.0 alias sata off ops amd_sata_ops end
 			device pci 0.1 alias xgbe_0 off end

From 19b4057f1bf6ff12055fb8710f4ef1dd4b097344 Mon Sep 17 00:00:00 2001
From: Subrata Banik <subratabanik@google.com>
Date: Thu, 10 Apr 2025 22:13:41 +0530
Subject: [PATCH 0701/3886] soc/intel/pantherlake: Increase heap size for
 high-quality FW splash

This patch increases the default heap size from 1MB to 2MB (0x200000) to
accommodate rendering high-quality firmware splash BMP logos.

The previous 1MB heap size might be insufficient for larger, more
detailed OEM logos, potentially leading to memory exhaustion during the
splash screen display.

TEST=Able to render an OEM logo size ~512KB w/o any corruption.

Change-Id: I850247befc3904b6dc52e9872e8b99d53c2c9564
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87265
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Jayvik Desai <jayvik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/soc/intel/pantherlake/Kconfig | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/src/soc/intel/pantherlake/Kconfig b/src/soc/intel/pantherlake/Kconfig
index 36417db7c3..6e7cc3f1cc 100644
--- a/src/soc/intel/pantherlake/Kconfig
+++ b/src/soc/intel/pantherlake/Kconfig
@@ -174,6 +174,10 @@ config FSP_TEMP_RAM_SIZE
 	  Refer to Platform FSP integration guide document to know
 	  the exact FSP requirement for Heap setup.
 
+config HEAP_SIZE
+	hex
+	default 0x200000
+
 config CHIPSET_DEVICETREE
 	string
 	default "soc/intel/pantherlake/chipset.cb"

From b75669038a459a2c388f9f9e3c7d00dd98128707 Mon Sep 17 00:00:00 2001
From: Subrata Banik <subratabanik@google.com>
Date: Thu, 10 Apr 2025 22:22:05 +0530
Subject: [PATCH 0702/3886] soc/intel/common/cse: Skip CSE state setting with
 LITE_SYNC_BY_PAYLOAD
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

This commit introduces a conditional bypass for ME state setting,
potentially reducing CBFS traversal time when searching for the
`option/me_state` file.

TEST=Able to build and boot google/fatcat.

Change-Id: I43f5daab450989307d9b3529949e9f03cba4404d
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87266
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/soc/intel/common/block/cse/cse.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/src/soc/intel/common/block/cse/cse.c b/src/soc/intel/common/block/cse/cse.c
index 2e0f2dbbbd..68d0c21342 100644
--- a/src/soc/intel/common/block/cse/cse.c
+++ b/src/soc/intel/common/block/cse/cse.c
@@ -1298,6 +1298,9 @@ static void me_reset_with_count(void)
 
 static void cse_set_state(struct device *dev)
 {
+	if (CONFIG(SOC_INTEL_CSE_LITE_SYNC_BY_PAYLOAD))
+		return;
+
 	/* (CS)ME Disable Command */
 	struct me_disable_command {
 		struct mkhi_hdr hdr;

From 78f95fc12c7e099ab61c99a3281d429226fda67a Mon Sep 17 00:00:00 2001
From: Subrata Banik <subratabanik@google.com>
Date: Fri, 11 Apr 2025 02:18:24 +0000
Subject: [PATCH 0703/3886] soc/qualcomm: Use runtime check for QUP wrapper 2
 init

Refactor the initialization logic for the optional QUPv3 wrapper 2.
Add a runtime check of the `QUP_WRAP2_BASE` macro's value within
`qupv3_fw_init`.

This approach simplifies the QUP wrapper 2 initialization, making the
code flow depend directly on whether a valid base address is defined
for the target SoC.

To facilitate this, explicitly define `QUP_WRAP2_BASE` as 0 (acting as
a dummy entry) for SoCs like sc7180 and sc7280 which do not include
this hardware block. The `if (QUP_WRAP2_BASE)` check will correctly
evaluate to false for these platforms, skipping the initialization.
Platforms that do have QUP wrapper 2 should define its non-zero base
address.

TEST=Able to build google/herobine.

Change-Id: I553ee4891abc5dd744b69bcbee1cca2efd993ef3
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87271
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
---
 src/soc/qualcomm/common/qupv3_config.c           | 2 ++
 src/soc/qualcomm/sc7180/include/soc/addressmap.h | 3 +++
 src/soc/qualcomm/sc7280/include/soc/addressmap.h | 3 +++
 3 files changed, 8 insertions(+)

diff --git a/src/soc/qualcomm/common/qupv3_config.c b/src/soc/qualcomm/common/qupv3_config.c
index 636f9b2fab..0b4d17ceb1 100644
--- a/src/soc/qualcomm/common/qupv3_config.c
+++ b/src/soc/qualcomm/common/qupv3_config.c
@@ -262,4 +262,6 @@ void qupv3_fw_init(void)
 
 	qup_common_init(QUP_WRAP0_BASE);
 	qup_common_init(QUP_WRAP1_BASE);
+	if (QUP_WRAP2_BASE)
+		qup_common_init(QUP_WRAP2_BASE);
 }
diff --git a/src/soc/qualcomm/sc7180/include/soc/addressmap.h b/src/soc/qualcomm/sc7180/include/soc/addressmap.h
index f295ceea22..e445392274 100644
--- a/src/soc/qualcomm/sc7180/include/soc/addressmap.h
+++ b/src/soc/qualcomm/sc7180/include/soc/addressmap.h
@@ -34,6 +34,9 @@
 #define QUP_SERIAL11_BASE		0x00A94000
 #define QUP_WRAP1_BASE			0x00AC0000
 
+/* QUPV3_2 - Dummy Entry */
+#define QUP_WRAP2_BASE			0x00000000
+
 /*
  * USB BASE ADDRESSES
  */
diff --git a/src/soc/qualcomm/sc7280/include/soc/addressmap.h b/src/soc/qualcomm/sc7280/include/soc/addressmap.h
index 342de9f9a4..fb5bf6f0d5 100644
--- a/src/soc/qualcomm/sc7280/include/soc/addressmap.h
+++ b/src/soc/qualcomm/sc7280/include/soc/addressmap.h
@@ -55,6 +55,9 @@
 #define QUP_WRAP1_BASE			0x00AC0000
 #define QUP_1_GSI_BASE			0x00A04000
 
+/* QUPV3_2 - Dummy Entry */
+#define QUP_WRAP2_BASE			0x00000000
+
 #define EPSSTOP_EPSS_TOP		0x18598000
 #define EPSSFAST_BASE_ADDR		0x18580000
 

From 9dd96f58f3a81a04f8b39f8675a50de32b6d932d Mon Sep 17 00:00:00 2001
From: Subrata Banik <subratabanik@google.com>
Date: Fri, 11 Apr 2025 22:59:02 +0530
Subject: [PATCH 0704/3886] lib/bootmode: Enforce display init requirement for
 vboot

The `display_init_required` function for vboot now mandates that either
`CONFIG_VBOOT_MUST_REQUEST_DISPLAY` or
`CONFIG_VBOOT_ALWAYS_ENABLE_DISPLAY` must be enabled.

If neither of these Kconfig options is set when `CONFIG_VBOOT` is
enabled, the code will now trigger `dead_code()`. This enforces the
requirement that display initialization is explicitly requested or
always enabled when vboot is active, aligning with the intended usage
of `VB2_CONTEXT_DISPLAY_INIT`.

TEST=Able to build google/fatcat.

Change-Id: I371c0533057fb088ea15a5da6bd76173cea525aa
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87283
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
---
 src/lib/bootmode.c | 8 +++++---
 1 file changed, 5 insertions(+), 3 deletions(-)

diff --git a/src/lib/bootmode.c b/src/lib/bootmode.c
index 3cf77d6fd8..dbfeb32a63 100644
--- a/src/lib/bootmode.c
+++ b/src/lib/bootmode.c
@@ -23,9 +23,11 @@ int display_init_required(void)
 {
 	/* For vboot, honor VB2_CONTEXT_DISPLAY_INIT. */
 	if (CONFIG(VBOOT)) {
-		/* Must always select MUST_REQUEST_DISPLAY when using this
-		   function. */
-		if (!CONFIG(VBOOT_MUST_REQUEST_DISPLAY))
+		/*
+		 * Display init requires VBOOT_MUST_REQUEST_DISPLAY || VBOOT_ALWAYS_ENABLE_DISPLAY;
+		 * else assert build.
+		 */
+		if (!CONFIG(VBOOT_MUST_REQUEST_DISPLAY) && !CONFIG(VBOOT_ALWAYS_ENABLE_DISPLAY))
 			dead_code();
 		return vboot_get_context()->flags & VB2_CONTEXT_DISPLAY_INIT;
 	}

From e5af2c6585114cba66fa039d8a7f69c4679d12af Mon Sep 17 00:00:00 2001
From: Subrata Banik <subratabanik@google.com>
Date: Fri, 11 Apr 2025 23:07:52 +0530
Subject: [PATCH 0705/3886] soc/intel/pantherlake: Remove implicit
 VBOOT_MUST_REQUEST_DISPLAY selection

The explicit selection of `CONFIG_VBOOT_MUST_REQUEST_DISPLAY` for
Panther Lake SoC has been removed.

Panther Lake platforms inherently enable display across all boot
modes (normal, developer, recovery) when vboot is active.
Therefore, explicitly selecting `VBOOT_MUST_REQUEST_DISPLAY`
becomes redundant, especially when `VBOOT_ALWAYS_ENABLE_DISPLAY`
is enabled due to the selection of `BMP_LOGO` for ChromeOS
devices.

TEST=Able to perform ec sync without any additional reboots.

Change-Id: Ifa222d6910664a22eacdb6fea54e73b099ca96d1
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87284
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/soc/intel/pantherlake/Kconfig | 1 -
 1 file changed, 1 deletion(-)

diff --git a/src/soc/intel/pantherlake/Kconfig b/src/soc/intel/pantherlake/Kconfig
index 6e7cc3f1cc..b325aaf4c7 100644
--- a/src/soc/intel/pantherlake/Kconfig
+++ b/src/soc/intel/pantherlake/Kconfig
@@ -304,7 +304,6 @@ config SOC_INTEL_COMMON_LPSS_UART_CLK_N_VAL
 	default 0x7fff
 
 config VBOOT
-	select VBOOT_MUST_REQUEST_DISPLAY
 	select VBOOT_SEPARATE_VERSTAGE
 	select VBOOT_STARTS_IN_BOOTBLOCK
 	select VBOOT_VBNV_CMOS

From 1b27f39025d643b208ce0e27216ede323f8b6545 Mon Sep 17 00:00:00 2001
From: Brian Hsu <Brian_Hsu@pegatron.corp-partner.google.com>
Date: Wed, 9 Apr 2025 14:31:31 +0800
Subject: [PATCH 0706/3886] mb/google/nissa/var/guren: Add touch screen
 FTSC1000 support

New Touchscreen function for Guren project.
Touchscreen panel: HKO RB116AS01-2,
and set TOUCHSCREEN_FTSC1000 to value "3".

BUG=b:391281767
BRANCH=firmware-nissa-15217.B
TEST=1. emerge-nissa coreboot chromeos-bootimage
     2. Confirm command evtest and touchscreen function is workable.

Change-Id: Icfe5f57c69d1bd98e0852a1aa3baed8c1444e4d9
Signed-off-by: Brian Hsu <Brian_Hsu@pegatron.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87238
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Daniel Peng <daniel_peng@pegatron.corp-partner.google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 .../brya/variants/guren/overridetree.cb       | 20 +++++++++++++++++++
 1 file changed, 20 insertions(+)

diff --git a/src/mainboard/google/brya/variants/guren/overridetree.cb b/src/mainboard/google/brya/variants/guren/overridetree.cb
index 0e106895be..3306e8a7f3 100644
--- a/src/mainboard/google/brya/variants/guren/overridetree.cb
+++ b/src/mainboard/google/brya/variants/guren/overridetree.cb
@@ -29,6 +29,7 @@ fw_config
 		option TOUCHSCREEN_UNPROVISIONED	0
 		option TOUCHSCREEN_ELAN0001		1
 		option TOUCHSCREEN_ILIT2901		2
+		option TOUCHSCREEN_FTSC1000		3
 	end
 end
 
@@ -369,6 +370,25 @@ chip soc/intel/alderlake
 					probe TOUCHSCREEN_SOURCE TOUCHSCREEN_ILIT2901
 				end
 			end
+
+			chip drivers/i2c/hid
+				register "generic.hid" = ""FTSC1000""
+				register "generic.desc" = ""G2TOUCH Touchscreen""
+				register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_C7_IRQ)"
+				register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C1)"
+				register "generic.reset_delay_ms" = "150"
+				register "generic.reset_off_delay_ms" = "5"
+				register "generic.stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C6)"
+				register "generic.stop_delay_ms" = "30"
+				register "generic.stop_off_delay_ms" = "10"
+				register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C0)"
+				register "generic.enable_delay_ms" = "45"
+				register "generic.has_power_resource" = "1"
+				register "hid_desc_reg_offset" = "0x01"
+				device i2c 38 on
+					probe TOUCHSCREEN_SOURCE TOUCHSCREEN_FTSC1000
+				end
+			end
 		end #I2C1
 		device ref i2c2 on
 			chip drivers/i2c/sx9324

From cdfd2104bd4d4fe1b74871932bc81e4a0751c7fb Mon Sep 17 00:00:00 2001
From: Daniel Peng <Daniel_Peng@pegatron.corp-partner.google.com>
Date: Wed, 9 Apr 2025 11:48:31 +0800
Subject: [PATCH 0707/3886] mb/google/brya/var/guren: Add Stylus Pen Function

New Stylus Pen for MAXEYE/0585501490 module for Guren360 project.
1. Add STYLUS fw_config setting
2. Enable stylus device settings
3. Disable the stylus GPIO pins based on fw_config

BUG=b:406168542
BRANCH=firmware-nissa-15217.B
TEST=1. emerge-nissa coreboot
     2. Confirm command evtest for stylus PRP0001:00 and workable.

Change-Id: I46d679d29b35d0f4fc70d63b74975d3bdfc40b7b
Signed-off-by: Daniel Peng <Daniel_Peng@pegatron.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87235
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Daniel Peng <daniel_peng@pegatron.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 .../google/brya/variants/guren/fw_config.c    | 13 +++++++++++++
 .../google/brya/variants/guren/gpio.c         |  4 ----
 .../brya/variants/guren/overridetree.cb       | 19 +++++++++++++++++++
 3 files changed, 32 insertions(+), 4 deletions(-)

diff --git a/src/mainboard/google/brya/variants/guren/fw_config.c b/src/mainboard/google/brya/variants/guren/fw_config.c
index efebee2f20..63e55a3b40 100644
--- a/src/mainboard/google/brya/variants/guren/fw_config.c
+++ b/src/mainboard/google/brya/variants/guren/fw_config.c
@@ -27,6 +27,13 @@ static const struct pad_config lte_disable_pads[] = {
 	PAD_NC(GPP_H23, NONE),
 };
 
+static const struct pad_config stylus_disable_pads[] = {
+	/* F13 : SOC_PEN_DETECT_R_ODL */
+	PAD_NC_LOCK(GPP_F13, NONE, LOCK_CONFIG),
+	/* F15 : SOC_PEN_DETECT_ODL */
+	PAD_NC_LOCK(GPP_F15, NONE, LOCK_CONFIG),
+};
+
 void fw_config_gpio_padbased_override(struct pad_config *padbased_table)
 {
 	if (!fw_config_probe(FW_CONFIG(DB_USB, DB_HDMI_LTE))
@@ -44,4 +51,10 @@ void fw_config_gpio_padbased_override(struct pad_config *padbased_table)
 		gpio_padbased_override(padbased_table, lte_disable_pads,
 						ARRAY_SIZE(lte_disable_pads));
 	}
+
+	if (fw_config_probe(FW_CONFIG(STYLUS, STYLUS_ABSENT))) {
+		printk(BIOS_INFO, "Disable Stylus GPIO pins.\n");
+		gpio_padbased_override(padbased_table, stylus_disable_pads,
+						ARRAY_SIZE(stylus_disable_pads));
+	}
 }
diff --git a/src/mainboard/google/brya/variants/guren/gpio.c b/src/mainboard/google/brya/variants/guren/gpio.c
index 0c462659c9..b5017c679b 100644
--- a/src/mainboard/google/brya/variants/guren/gpio.c
+++ b/src/mainboard/google/brya/variants/guren/gpio.c
@@ -26,10 +26,6 @@ static const struct pad_config override_gpio_table[] = {
 	PAD_CFG_GPI(GPP_E5, NONE, DEEP),
 	/* F12 : WWAN_RST_L */
 	PAD_CFG_GPO_LOCK(GPP_F12, 1, LOCK_CONFIG),
-	/* F13 : GSXSLOAD ==> NC */
-	PAD_NC_LOCK(GPP_F13, NONE, LOCK_CONFIG),
-	/* F15 : GSXSRESET# ==> NC */
-	PAD_NC_LOCK(GPP_F15, NONE, LOCK_CONFIG),
 	/* H19 : SOC_I2C_SUB_INT_ODL */
 	PAD_CFG_GPI_APIC(GPP_H19, NONE, PLTRST, LEVEL, NONE),
 	/* H22 : IMGCLKOUT3 ==> NC */
diff --git a/src/mainboard/google/brya/variants/guren/overridetree.cb b/src/mainboard/google/brya/variants/guren/overridetree.cb
index 3306e8a7f3..8c50fd76d8 100644
--- a/src/mainboard/google/brya/variants/guren/overridetree.cb
+++ b/src/mainboard/google/brya/variants/guren/overridetree.cb
@@ -21,6 +21,10 @@ fw_config
 		option WIFI_SAR_ID_INTEL_CONVERTIBLE		 0
 		option WIFI_SAR_ID_INTEL_CLAMSHELL		 1
 	end
+	field STYLUS 15
+		option STYLUS_ABSENT		0
+		option STYLUS_PRESENT		1
+	end
 	field WFC 17 18
 		option WFC_ABSENT		0
 		option WFC_PRESENT		1
@@ -389,6 +393,21 @@ chip soc/intel/alderlake
 					probe TOUCHSCREEN_SOURCE TOUCHSCREEN_FTSC1000
 				end
 			end
+
+			chip drivers/generic/gpio_keys
+				register "name" = ""PENH""
+				register "gpio" = "ACPI_GPIO_INPUT_ACTIVE_LOW(GPP_F13)"
+				register "key.wake_gpe" = "GPE0_DW2_15"
+				register "key.wakeup_route" = "WAKEUP_ROUTE_SCI"
+				register "key.wakeup_event_action" = "EV_ACT_DEASSERTED"
+				register "key.dev_name" = ""EJCT""
+				register "key.linux_code" = "SW_PEN_INSERTED"
+				register "key.linux_input_type" = "EV_SW"
+				register "key.label" = ""pen_eject""
+				device generic 0 on
+					probe STYLUS STYLUS_PRESENT
+				end
+			end
 		end #I2C1
 		device ref i2c2 on
 			chip drivers/i2c/sx9324

From ff9e06911cf096e996bf20afd0a8ac7b2f61b362 Mon Sep 17 00:00:00 2001
From: Daniel Peng <Daniel_Peng@pegatron.corp-partner.google.com>
Date: Thu, 10 Apr 2025 16:03:33 +0800
Subject: [PATCH 0708/3886] mb/google/nissa/var/glassway: Support Memory Hynix
 H58G56CK8BX146

Add the new memory support: Hynix H58G56CK8BX146

BUG=b:404452285
BRANCH=firmware-nissa-15217.B
TEST=Run command "go run ./util/spd_tools/src/part_id_gen/\
     part_id_gen.go ADL lp5 \
     src/mainboard/google/brya/variants/glassway/memory/ \
     src/mainboard/google/brya/variants/glassway/memory/\
     mem_parts_used.txt"

Change-Id: I1d6bbb778e75f6f32012e0cf6f427101d3616246
Signed-off-by: Daniel Peng <Daniel_Peng@pegatron.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87252
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Daniel Peng <daniel_peng@pegatron.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Jayvik Desai <jayvik@google.com>
---
 src/mainboard/google/brya/variants/glassway/memory/Makefile.mk | 3 ++-
 .../google/brya/variants/glassway/memory/dram_id.generated.txt | 3 ++-
 .../google/brya/variants/glassway/memory/mem_parts_used.txt    | 1 +
 3 files changed, 5 insertions(+), 2 deletions(-)

diff --git a/src/mainboard/google/brya/variants/glassway/memory/Makefile.mk b/src/mainboard/google/brya/variants/glassway/memory/Makefile.mk
index c3f12fb907..63f419cd62 100644
--- a/src/mainboard/google/brya/variants/glassway/memory/Makefile.mk
+++ b/src/mainboard/google/brya/variants/glassway/memory/Makefile.mk
@@ -1,7 +1,7 @@
 # SPDX-License-Identifier: GPL-2.0-or-later
 # This is an auto-generated file. Do not edit!!
 # Generated by:
-# /tmp/go-build4204010061/b001/exe/part_id_gen ADL lp5 src/mainboard/google/brya/variants/glassway/memory/ src/mainboard/google/brya/variants/glassway/memory/mem_parts_used.txt
+# /tmp/go-build4146048213/b001/exe/part_id_gen ADL lp5 src/mainboard/google/brya/variants/glassway/memory/ src/mainboard/google/brya/variants/glassway/memory/mem_parts_used.txt
 
 SPD_SOURCES =
 SPD_SOURCES += spd/lp5/set-0/spd-7.hex      # ID = 0(0b0000)  Parts = K3KL8L80CM-MGCT
@@ -10,3 +10,4 @@ SPD_SOURCES += spd/lp5/set-0/spd-3.hex      # ID = 2(0b0010)  Parts = H58G56AK6B
 SPD_SOURCES += spd/lp5/set-0/spd-1.hex      # ID = 3(0b0011)  Parts = H9JCNNNBK3MLYR-N6E
 SPD_SOURCES += spd/lp5/set-0/spd-6.hex      # ID = 4(0b0100)  Parts = H58G66AK6BX070
 SPD_SOURCES += spd/lp5/set-0/spd-8.hex      # ID = 5(0b0101)  Parts = K3KL9L90CM-MGCT
+SPD_SOURCES += spd/lp5/set-0/spd-11.hex      # ID = 6(0b0110)  Parts = H58G56CK8BX146
diff --git a/src/mainboard/google/brya/variants/glassway/memory/dram_id.generated.txt b/src/mainboard/google/brya/variants/glassway/memory/dram_id.generated.txt
index 424f320e93..7f1ca2ba39 100644
--- a/src/mainboard/google/brya/variants/glassway/memory/dram_id.generated.txt
+++ b/src/mainboard/google/brya/variants/glassway/memory/dram_id.generated.txt
@@ -1,7 +1,7 @@
 # SPDX-License-Identifier: GPL-2.0-or-later
 # This is an auto-generated file. Do not edit!!
 # Generated by:
-# /tmp/go-build4204010061/b001/exe/part_id_gen ADL lp5 src/mainboard/google/brya/variants/glassway/memory/ src/mainboard/google/brya/variants/glassway/memory/mem_parts_used.txt
+# /tmp/go-build4146048213/b001/exe/part_id_gen ADL lp5 src/mainboard/google/brya/variants/glassway/memory/ src/mainboard/google/brya/variants/glassway/memory/mem_parts_used.txt
 
 DRAM Part Name                 ID to assign
 K3KL8L80CM-MGCT                0 (0000)
@@ -11,3 +11,4 @@ H9JCNNNBK3MLYR-N6E             3 (0011)
 H58G66AK6BX070                 4 (0100)
 K3KL9L90CM-MGCT                5 (0101)
 K3LKBKB0BM-MGCP                2 (0010)
+H58G56CK8BX146                 6 (0110)
diff --git a/src/mainboard/google/brya/variants/glassway/memory/mem_parts_used.txt b/src/mainboard/google/brya/variants/glassway/memory/mem_parts_used.txt
index a7e81204ae..796d10a21c 100644
--- a/src/mainboard/google/brya/variants/glassway/memory/mem_parts_used.txt
+++ b/src/mainboard/google/brya/variants/glassway/memory/mem_parts_used.txt
@@ -16,3 +16,4 @@ H9JCNNNBK3MLYR-N6E
 H58G66AK6BX070
 K3KL9L90CM-MGCT
 K3LKBKB0BM-MGCP
+H58G56CK8BX146

From ef61d4d9254e9b9733933a124012e853cc56864d Mon Sep 17 00:00:00 2001
From: Kun Liu <liukun11@huaqin.corp-partner.google.com>
Date: Tue, 8 Apr 2025 20:58:51 +0800
Subject: [PATCH 0709/3886] mb/google/nissa/var/telith: Support x32 memory
 configuration

Use GPP_E19 level to determine whether x32 memory configuration is
supported.

BUG=b:405303038
TEST=emerge-nissa coreboot chromeos-bootimage

Change-Id: I969fea2aba858f76870c1a31ad4bd884ec9b6ff3
Signed-off-by: Kun Liu <liukun11@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87212
Reviewed-by: Jayvik Desai <jayvik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Qinghong Zeng <zengqinghong@huaqin.corp-partner.google.com>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
---
 src/mainboard/google/brya/Kconfig             |  1 +
 .../google/brya/variants/telith/Makefile.mk   |  1 +
 .../google/brya/variants/telith/gpio.c        |  5 +++++
 .../google/brya/variants/telith/memory.c      | 20 +++++++++++++++++++
 4 files changed, 27 insertions(+)
 create mode 100644 src/mainboard/google/brya/variants/telith/memory.c

diff --git a/src/mainboard/google/brya/Kconfig b/src/mainboard/google/brya/Kconfig
index 5331f0e42f..50a2959022 100644
--- a/src/mainboard/google/brya/Kconfig
+++ b/src/mainboard/google/brya/Kconfig
@@ -631,6 +631,7 @@ config BOARD_GOOGLE_TELITH
 	select DRIVERS_INTEL_MIPI_CAMERA
 	select MAINBOARD_HAS_GOOGLE_STRAUSS_KEYBOARD
 	select SOC_INTEL_TWINLAKE
+	select ENFORCE_MEM_CHANNEL_DISABLE
 
 config BOARD_GOOGLE_TEREID
 	select BOARD_GOOGLE_BASEBOARD_NISSA
diff --git a/src/mainboard/google/brya/variants/telith/Makefile.mk b/src/mainboard/google/brya/variants/telith/Makefile.mk
index e7ef021a8d..b67f3087de 100644
--- a/src/mainboard/google/brya/variants/telith/Makefile.mk
+++ b/src/mainboard/google/brya/variants/telith/Makefile.mk
@@ -1,6 +1,7 @@
 # SPDX-License-Identifier: GPL-2.0-only
 bootblock-y += gpio.c
 
+romstage-y += memory.c
 romstage-y += gpio.c
 
 ramstage-y += gpio.c
diff --git a/src/mainboard/google/brya/variants/telith/gpio.c b/src/mainboard/google/brya/variants/telith/gpio.c
index 0043111d74..75f7617655 100644
--- a/src/mainboard/google/brya/variants/telith/gpio.c
+++ b/src/mainboard/google/brya/variants/telith/gpio.c
@@ -69,6 +69,9 @@ static const struct pad_config override_gpio_table[] = {
 	/* R7 : DMIC_DATA_1A ==> NC */
 	PAD_NC_LOCK(GPP_R7, NONE, LOCK_CONFIG),
 
+	/* E19 : DDP1_CTRLDATA ==> GPP_E19_STRAP */
+	PAD_CFG_GPI_LOCK(GPP_E19, DN_20K, LOCK_CONFIG),
+
 	/* Configure the virtual CNVi Bluetooth I2S GPIO pads */
 	/* BT_I2S_BCLK */
 	PAD_CFG_NF(GPP_VGPIO_30, NONE, DEEP, NF3),
@@ -112,6 +115,8 @@ static const struct pad_config early_gpio_table[] = {
 	PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2),
 	/* H11 : UART0_TXD ==> UART_SOC_TX_DBG_RX */
 	PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2),
+	/* E19 : DDP1_CTRLDATA ==> GPP_E19_STRAP */
+	PAD_CFG_GPI_LOCK(GPP_E19, DN_20K, LOCK_CONFIG),
 };
 
 const struct pad_config *variant_gpio_override_table(size_t *num)
diff --git a/src/mainboard/google/brya/variants/telith/memory.c b/src/mainboard/google/brya/variants/telith/memory.c
new file mode 100644
index 0000000000..51a7ff504c
--- /dev/null
+++ b/src/mainboard/google/brya/variants/telith/memory.c
@@ -0,0 +1,20 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <baseboard/gpio.h>
+#include <baseboard/variants.h>
+#include <gpio.h>
+#include <soc/romstage.h>
+
+uint8_t mb_get_channel_disable_mask(void)
+{
+	/*
+	 * GPP_E19 High -> One RAM Chip
+	 * GPP_E19 Low  -> Two RAM Chip
+	 */
+	if (gpio_get(GPP_E19)) {
+		/* Disable all other channels except first two on each controller */
+		return (BIT(2) | BIT(3));
+	}
+
+	return 0;
+}

From 7a58cfff897ada03b4c3e9996d14881b3c623fc4 Mon Sep 17 00:00:00 2001
From: Yidi Lin <yidilin@chromium.org>
Date: Fri, 11 Apr 2025 10:38:36 +0800
Subject: [PATCH 0710/3886] util/scripts/update_submodules: Fix "branch:
 unbound variable" error

After CB:86803, ${branch} variable is no longer valid. Use
${branch_name} instead ${branch} for generating the commit message.

TEST=./util/scripts/update_submodules -R 3rdparty/arm-trusted-firmware/
     The script generates the new commit successfully.

Change-Id: Ia528379b8721e6d419984bab28de7cf427e42423
Signed-off-by: Yidi Lin <yidilin@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87268
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 util/scripts/update_submodules | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/util/scripts/update_submodules b/util/scripts/update_submodules
index cbf2364ebe..9eeb3836e6 100755
--- a/util/scripts/update_submodules
+++ b/util/scripts/update_submodules
@@ -132,7 +132,7 @@ main() {
 			cd "${TOP}" || exit 1
 			git add "${submodule}" > /dev/null 2>&1 || exit 1
 			git commit -s -F- > /dev/null 2>&1 <<-EOF
-	Update ${submodule##*/} submodule to upstream ${branch##*/}
+	Update ${submodule##*/} submodule to upstream ${branch_name##*/}
 
 	Updating from commit id ${initial_commit_id}:
 	$initial_commit_description

From b1cad555124a23252fec24cdb1c988f83733906d Mon Sep 17 00:00:00 2001
From: Yidi Lin <yidilin@chromium.org>
Date: Fri, 11 Apr 2025 02:49:19 +0000
Subject: [PATCH 0711/3886] Update arm-trusted-firmware submodule to upstream
 master

Updating from commit id e5a1f4abeec3:
2025-03-03 16:21:54 +0100 - (Merge "feat(mt8196): fix MT8196 gpio driver" into integration)

to commit id 57ac3f74b34a:
2025-04-09 20:07:35 +0200 - (Merge "feat(stm32mp15-fdts): add Linux Automation GmbH TAC" into integration)

This brings in 244 new commits.

Change-Id: I22ec128c99e84fd80fbc7de06f2791c627ae790a
Signed-off-by: Yidi Lin <yidilin@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87269
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
---
 3rdparty/arm-trusted-firmware | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/3rdparty/arm-trusted-firmware b/3rdparty/arm-trusted-firmware
index e5a1f4abee..57ac3f74b3 160000
--- a/3rdparty/arm-trusted-firmware
+++ b/3rdparty/arm-trusted-firmware
@@ -1 +1 @@
-Subproject commit e5a1f4abeec3311e65412a2905873a110a9abdd1
+Subproject commit 57ac3f74b34a3303f03deee264a1f2247c68008d

From 695976f65f40d26f7cdcd73caac241904b467fbb Mon Sep 17 00:00:00 2001
From: Qinghong Zeng <zengqinghong@huaqin.corp-partner.google.com>
Date: Wed, 9 Apr 2025 11:34:49 +0800
Subject: [PATCH 0712/3886] mb/google/nissa/var/teliks: Support x32 memory
 configuration

Use GPP_E19 level to determine whether x32 memory configuration is
supported.

BUG=b:409212347
TEST=emerge-nissa coreboot chromeos-bootimage

Change-Id: I152501858069b5164e8ea602373ed27a5288acb1
Signed-off-by: Qinghong Zeng <zengqinghong@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87233
Reviewed-by: Jayvik Desai <jayvik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
---
 src/mainboard/google/brya/Kconfig             |  1 +
 .../google/brya/variants/teliks/Makefile.mk   |  1 +
 .../google/brya/variants/teliks/gpio.c        |  5 +++++
 .../google/brya/variants/teliks/memory.c      | 20 +++++++++++++++++++
 4 files changed, 27 insertions(+)
 create mode 100644 src/mainboard/google/brya/variants/teliks/memory.c

diff --git a/src/mainboard/google/brya/Kconfig b/src/mainboard/google/brya/Kconfig
index 50a2959022..fd1cf58e22 100644
--- a/src/mainboard/google/brya/Kconfig
+++ b/src/mainboard/google/brya/Kconfig
@@ -620,6 +620,7 @@ config BOARD_GOOGLE_TELIKS
 	select DRIVERS_INTEL_MIPI_CAMERA
 	select HAVE_WWAN_POWER_SEQUENCE
 	select SOC_INTEL_TWINLAKE
+	select ENFORCE_MEM_CHANNEL_DISABLE
 
 config BOARD_GOOGLE_TELITH
 	select BOARD_GOOGLE_BASEBOARD_NISSA
diff --git a/src/mainboard/google/brya/variants/teliks/Makefile.mk b/src/mainboard/google/brya/variants/teliks/Makefile.mk
index f41cdfdb8a..efe5002383 100644
--- a/src/mainboard/google/brya/variants/teliks/Makefile.mk
+++ b/src/mainboard/google/brya/variants/teliks/Makefile.mk
@@ -1,6 +1,7 @@
 # SPDX-License-Identifier: GPL-2.0-only
 bootblock-y += gpio.c
 
+romstage-y += memory.c
 romstage-y += gpio.c
 
 ramstage-y += gpio.c
diff --git a/src/mainboard/google/brya/variants/teliks/gpio.c b/src/mainboard/google/brya/variants/teliks/gpio.c
index 0f33c2db6e..ef50145e38 100644
--- a/src/mainboard/google/brya/variants/teliks/gpio.c
+++ b/src/mainboard/google/brya/variants/teliks/gpio.c
@@ -74,6 +74,9 @@ static const struct pad_config override_gpio_table[] = {
 	/* R7 : DMIC_DATA_1A ==> NC */
 	PAD_NC_LOCK(GPP_R7, NONE, LOCK_CONFIG),
 
+	/* E19 : DDP1_CTRLDATA ==> GPP_E19_STRAP */
+	PAD_CFG_GPI_LOCK(GPP_E19, DN_20K, LOCK_CONFIG),
+
 	/* Configure the virtual CNVi Bluetooth I2S GPIO pads */
 	/* BT_I2S_BCLK */
 	PAD_CFG_NF(GPP_VGPIO_30, NONE, DEEP, NF3),
@@ -123,6 +126,8 @@ static const struct pad_config early_gpio_table[] = {
 	PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2),
 	/* H11 : UART0_TXD ==> UART_SOC_TX_DBG_RX */
 	PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2),
+	/* E19 : DDP1_CTRLDATA ==> GPP_E19_STRAP */
+	PAD_CFG_GPI_LOCK(GPP_E19, DN_20K, LOCK_CONFIG),
 };
 
 static const struct pad_config romstage_gpio_table[] = {
diff --git a/src/mainboard/google/brya/variants/teliks/memory.c b/src/mainboard/google/brya/variants/teliks/memory.c
new file mode 100644
index 0000000000..51a7ff504c
--- /dev/null
+++ b/src/mainboard/google/brya/variants/teliks/memory.c
@@ -0,0 +1,20 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <baseboard/gpio.h>
+#include <baseboard/variants.h>
+#include <gpio.h>
+#include <soc/romstage.h>
+
+uint8_t mb_get_channel_disable_mask(void)
+{
+	/*
+	 * GPP_E19 High -> One RAM Chip
+	 * GPP_E19 Low  -> Two RAM Chip
+	 */
+	if (gpio_get(GPP_E19)) {
+		/* Disable all other channels except first two on each controller */
+		return (BIT(2) | BIT(3));
+	}
+
+	return 0;
+}

From 402419c3b314e60854113b6d05ff4f74f823f68a Mon Sep 17 00:00:00 2001
From: Qinghong Zeng <zengqinghong@huaqin.corp-partner.google.com>
Date: Wed, 9 Apr 2025 11:42:42 +0800
Subject: [PATCH 0713/3886] mb/google/nissa/var/anraggar: Support x32 memory
 configuration

Use GPP_E19 level to determine whether x32 memory configuration is
supported.

BUG=b:409212348
TEST=emerge-nissa coreboot chromeos-bootimage

Change-Id: Ic401d3db57659c6ced13c123591c1fd82fa9a721
Signed-off-by: Qinghong Zeng <zengqinghong@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87234
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jayvik Desai <jayvik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com>
---
 src/mainboard/google/brya/Kconfig             |  1 +
 .../google/brya/variants/anraggar/Makefile.mk |  1 +
 .../google/brya/variants/anraggar/gpio.c      |  5 +++++
 .../google/brya/variants/anraggar/memory.c    | 20 +++++++++++++++++++
 4 files changed, 27 insertions(+)
 create mode 100644 src/mainboard/google/brya/variants/anraggar/memory.c

diff --git a/src/mainboard/google/brya/Kconfig b/src/mainboard/google/brya/Kconfig
index fd1cf58e22..c60f22a7f9 100644
--- a/src/mainboard/google/brya/Kconfig
+++ b/src/mainboard/google/brya/Kconfig
@@ -157,6 +157,7 @@ config BOARD_GOOGLE_ANRAGGAR
 	select HAVE_WWAN_POWER_SEQUENCE
 	select INTEL_GMA_HAVE_VBT
 	select CHROMEOS_WIFI_SAR if CHROMEOS
+	select ENFORCE_MEM_CHANNEL_DISABLE
 
 config BOARD_GOOGLE_AURASH
 	select BOARD_GOOGLE_BASEBOARD_BRASK
diff --git a/src/mainboard/google/brya/variants/anraggar/Makefile.mk b/src/mainboard/google/brya/variants/anraggar/Makefile.mk
index f41cdfdb8a..efe5002383 100644
--- a/src/mainboard/google/brya/variants/anraggar/Makefile.mk
+++ b/src/mainboard/google/brya/variants/anraggar/Makefile.mk
@@ -1,6 +1,7 @@
 # SPDX-License-Identifier: GPL-2.0-only
 bootblock-y += gpio.c
 
+romstage-y += memory.c
 romstage-y += gpio.c
 
 ramstage-y += gpio.c
diff --git a/src/mainboard/google/brya/variants/anraggar/gpio.c b/src/mainboard/google/brya/variants/anraggar/gpio.c
index 03507b01e1..cf16091db0 100644
--- a/src/mainboard/google/brya/variants/anraggar/gpio.c
+++ b/src/mainboard/google/brya/variants/anraggar/gpio.c
@@ -74,6 +74,9 @@ static const struct pad_config override_gpio_table[] = {
 	/* R7 : DMIC_DATA_1A ==> NC */
 	PAD_NC_LOCK(GPP_R7, NONE, LOCK_CONFIG),
 
+	/* E19 : DDP1_CTRLDATA ==> GPP_E19_STRAP */
+	PAD_CFG_GPI_LOCK(GPP_E19, DN_20K, LOCK_CONFIG),
+
 	/* Configure the virtual CNVi Bluetooth I2S GPIO pads */
 	/* BT_I2S_BCLK */
 	PAD_CFG_NF(GPP_VGPIO_30, NONE, DEEP, NF3),
@@ -123,6 +126,8 @@ static const struct pad_config early_gpio_table[] = {
 	PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2),
 	/* H11 : UART0_TXD ==> UART_SOC_TX_DBG_RX */
 	PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2),
+	/* E19 : DDP1_CTRLDATA ==> GPP_E19_STRAP */
+	PAD_CFG_GPI_LOCK(GPP_E19, DN_20K, LOCK_CONFIG),
 };
 
 static const struct pad_config romstage_gpio_table[] = {
diff --git a/src/mainboard/google/brya/variants/anraggar/memory.c b/src/mainboard/google/brya/variants/anraggar/memory.c
new file mode 100644
index 0000000000..51a7ff504c
--- /dev/null
+++ b/src/mainboard/google/brya/variants/anraggar/memory.c
@@ -0,0 +1,20 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <baseboard/gpio.h>
+#include <baseboard/variants.h>
+#include <gpio.h>
+#include <soc/romstage.h>
+
+uint8_t mb_get_channel_disable_mask(void)
+{
+	/*
+	 * GPP_E19 High -> One RAM Chip
+	 * GPP_E19 Low  -> Two RAM Chip
+	 */
+	if (gpio_get(GPP_E19)) {
+		/* Disable all other channels except first two on each controller */
+		return (BIT(2) | BIT(3));
+	}
+
+	return 0;
+}

From f76270882211714db1d1a010c5ad294ad3e556de Mon Sep 17 00:00:00 2001
From: Yu-Ping Wu <yupingso@chromium.org>
Date: Wed, 9 Apr 2025 07:50:09 +0800
Subject: [PATCH 0714/3886] util/mediatek: Add check-pi-img.py

According to MediaTek's proprietary PI_IMG parser, two cookies (one
header and one footer) are expected. Therefore, add a script to perform
validity check of the PI_IMG firmware, so that format errors could be
caught in build time.

Change-Id: I27011492c7fab747aa3ee12d514d20a6a52d0a4d
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87226
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 Documentation/util.md         |  1 +
 util/README.md                |  1 +
 util/mediatek/check-pi-img.py | 35 +++++++++++++++++++++++++++++++++++
 util/mediatek/description.md  |  1 +
 4 files changed, 38 insertions(+)
 create mode 100755 util/mediatek/check-pi-img.py

diff --git a/Documentation/util.md b/Documentation/util.md
index ba4618fa69..2ba5fc1878 100644
--- a/Documentation/util.md
+++ b/Documentation/util.md
@@ -88,6 +88,7 @@ image for testing purposes and for working on firmware. `Bash`
 * __[me_cleaner](https://github.com/corna/me_cleaner)__ - Tool for
 partial deblobbing of Intel ME/TXE firmware images `Python`
 * __mediatek__
+	* check-pi-img.py - Check `PI_IMG` firmware. `Python3`
 	* gen-bl-img.py - Generate MediaTek bootloader header.
 `Python3`
 * __mma__ - Memory Margin Analysis automation tests `Bash`
diff --git a/util/README.md b/util/README.md
index 7c9394794a..dbb31110d9 100644
--- a/util/README.md
+++ b/util/README.md
@@ -79,6 +79,7 @@ image for testing purposes and for working on firmware. `Bash`
 * __[me_cleaner](https://github.com/corna/me_cleaner)__ - Tool for
 partial deblobbing of Intel ME/TXE firmware images `Python`
 * __mediatek__
+	* check-pi-img.py - Check `PI_IMG` firmware. `Python3`
 	* gen-bl-img.py - Generate MediaTek bootloader header.
 `Python3`
 * __mma__ - Memory Margin Analysis automation tests `Bash`
diff --git a/util/mediatek/check-pi-img.py b/util/mediatek/check-pi-img.py
new file mode 100755
index 0000000000..af15ee3a1f
--- /dev/null
+++ b/util/mediatek/check-pi-img.py
@@ -0,0 +1,35 @@
+#!/usr/bin/env python3
+#
+# SPDX-License-Identifier: GPL-2.0-only
+
+import argparse
+
+
+HEADER_OFFSET = 0x200
+COOKIE = 0x17C3A6B4
+
+
+def check_pi_img(pi_img):
+    cookie_count = 0
+    with open(pi_img, "rb") as f:
+        f.seek(HEADER_OFFSET)
+        while True:
+            data = f.read(4)
+            if not data:
+                break
+            value = int.from_bytes(data, byteorder="little", signed=False)
+            if value == COOKIE:
+                cookie_count += 1
+    if cookie_count != 2:
+        raise ValueError("Invalid PI_IMG {} (expected 2 cookies; found {})"
+                         .format(pi_img, cookie_count))
+
+
+def main():
+    parser = argparse.ArgumentParser()
+    parser.add_argument("pi_img")
+    args = parser.parse_args()
+    check_pi_img(args.pi_img)
+
+if __name__ == '__main__':
+    main()
diff --git a/util/mediatek/description.md b/util/mediatek/description.md
index 67ff39022b..568c8bbb1e 100644
--- a/util/mediatek/description.md
+++ b/util/mediatek/description.md
@@ -1,2 +1,3 @@
 __mediatek__
+  * check-pi-img.py - Check `PI_IMG` firmware. `Python3`
   * gen-bl-img.py - Generate MediaTek bootloader header. `Python3`

From a479f11ecc791a563466e9587205f435158209f2 Mon Sep 17 00:00:00 2001
From: Yu-Ping Wu <yupingso@chromium.org>
Date: Mon, 10 Feb 2025 18:38:28 +0800
Subject: [PATCH 0715/3886] soc/mediatek/mt8196: Add validity check for PI_IMG

Call check-pi-img.py to perform validity check for the PI_IMG firmware
file.

BUG=none
TEST=emerge-rauru coreboot
TEST=cbfstool coreboot.rom print | grep pi_img
BRANCH=rauru

Change-Id: I7b8085c1229c1a7a8cad904e166471ff8bda5cfb
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86352
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/soc/mediatek/mt8196/Makefile.mk | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/src/soc/mediatek/mt8196/Makefile.mk b/src/soc/mediatek/mt8196/Makefile.mk
index 903f57b01b..9d05ee46ea 100644
--- a/src/soc/mediatek/mt8196/Makefile.mk
+++ b/src/soc/mediatek/mt8196/Makefile.mk
@@ -100,6 +100,15 @@ ifneq ($(wildcard $(BL31_LIB)),)
 BL31_MAKEARGS += MTKLIB_PATH=$(BL31_LIB)
 endif
 
+PI_IMG := $(MT8196_BLOB_DIR)/$(call strip_quotes,$(CONFIG_PI_IMG_FIRMWARE))
+
+.PHONY: check_pi_img
+check_pi_img: $(PI_IMG)
+	./util/mediatek/check-pi-img.py $<
+
+# Make sure check_pi_img is always run.
+$(obj)/coreboot.pre: | check_pi_img
+
 mcu-firmware-files := \
 	$(CONFIG_DPM_DM_FIRMWARE) \
 	$(CONFIG_DPM_PM_FIRMWARE) \

From e6358d98c4691bd967d268033918c6d212b17994 Mon Sep 17 00:00:00 2001
From: Patrick Rudolph <patrick.rudolph@9elements.com>
Date: Thu, 3 Apr 2025 08:17:24 +0200
Subject: [PATCH 0716/3886] soc/amd/common/block: Read SPI rom remapping

When a SPI ROM greater than 16MByte is being used it will be split
into 16MByte chunks that can be remapped in HW as an automatic recovery
mechanism. As an example when the EFS in the first 16MByte is corrupted
and the second 16MByte EFS is valid the HW will switch pages. The automatic
address translation of the MMIO ROM needs to be accounted when accessing
the ROM2/ROM3 BAR.

Add a function to retrieve the current address remapping and print it in
show_spi_speeds_and_modes() for debugging purposes.

Document 56780

Change-Id: I046e029e6135ab57f79b675c62b233203f00d705
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87175
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/soc/amd/common/block/include/amdblocks/spi.h |  4 ++++
 src/soc/amd/common/block/spi/fch_spi.c           | 14 ++++++++++++++
 2 files changed, 18 insertions(+)

diff --git a/src/soc/amd/common/block/include/amdblocks/spi.h b/src/soc/amd/common/block/include/amdblocks/spi.h
index eafc2c2f3b..4fefc2f536 100644
--- a/src/soc/amd/common/block/include/amdblocks/spi.h
+++ b/src/soc/amd/common/block/include/amdblocks/spi.h
@@ -71,6 +71,7 @@ enum spi100_speed {
 #define   SPI_RD4DW_EN_HOST		BIT(15)
 
 #define SPI_ROM_PAGE			0x5c
+#define   SPI_ROM_PAGE_SEL		(BIT(0) | BIT(1))
 
 #define SPI_FIFO			0x80
 #define SPI_FIFO_LAST_BYTE		0xc6 /* 0xc7 for Cezanne */
@@ -124,6 +125,9 @@ void spi_write8(uint8_t reg, uint8_t val);
 void spi_write16(uint8_t reg, uint16_t val);
 void spi_write32(uint8_t reg, uint32_t val);
 
+/* Returns the active SPI ROM remapping */
+uint8_t fch_spi_rom_remapping(void);
+
 void fch_spi_config_modes(void);
 void mainboard_spi_cfg_override(uint8_t *fast_speed, uint8_t *read_mode);
 
diff --git a/src/soc/amd/common/block/spi/fch_spi.c b/src/soc/amd/common/block/spi/fch_spi.c
index d9708b1eb0..fc182fca5f 100644
--- a/src/soc/amd/common/block/spi/fch_spi.c
+++ b/src/soc/amd/common/block/spi/fch_spi.c
@@ -32,10 +32,18 @@ static const char *read_mode_str[8] = {
 	"Fast Read"
 };
 
+static const char *remapping[8] = {
+	"0-1-2-3",
+	"1-0-3-2",
+	"2-3-0-1",
+	"3-2-1-0",
+};
+
 void show_spi_speeds_and_modes(void)
 {
 	uint16_t val16 = spi_read16(SPI100_SPEED_CONFIG);
 	uint32_t val32 = spi_read32(SPI_CNTRL0);
+	uint8_t val8 = fch_spi_rom_remapping();
 
 	printk(BIOS_DEBUG, "SPI normal read speed: %s\n",
 	       spi_speed_str[DECODE_SPI_NORMAL_SPEED(val16)]);
@@ -48,6 +56,7 @@ void show_spi_speeds_and_modes(void)
 	printk(BIOS_DEBUG, "SPI100: %s\n",
 	       spi_read16(SPI100_ENABLE) & SPI_USE_SPI100 ? "Enabled" : "Disabled");
 	printk(BIOS_DEBUG, "SPI Read Mode: %s\n", read_mode_str[DECODE_SPI_READ_MODE(val32)]);
+	printk(BIOS_DEBUG, "SPI ROM mapping: %s\n", remapping[val8]);
 }
 
 void __weak mainboard_spi_cfg_override(uint8_t *fast_speed, uint8_t *read_mode)
@@ -96,6 +105,11 @@ static void fch_spi_set_read_mode(u32 mode)
 	spi_write32(SPI_CNTRL0, val | SPI_READ_MODE(mode));
 }
 
+uint8_t fch_spi_rom_remapping(void)
+{
+	return spi_read8(SPI_ROM_PAGE) & SPI_ROM_PAGE_SEL;
+}
+
 void fch_spi_config_modes(void)
 {
 	uint8_t read_mode, fast_speed;

From fdb0701336e35f45c00beef43df5d41777231f3a Mon Sep 17 00:00:00 2001
From: Patrick Rudolph <patrick.rudolph@9elements.com>
Date: Thu, 3 Apr 2025 08:36:54 +0200
Subject: [PATCH 0717/3886] soc/amd/common/block/spi: Enforce default ROM
 mapping

Make sure that the ROM2 MMIO area starts at flash address 0.

Document 56780

Change-Id: I1fc06517ea496441147375579800f7349e39facc
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87176
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
---
 src/soc/amd/common/block/spi/mmap_boot.c | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/src/soc/amd/common/block/spi/mmap_boot.c b/src/soc/amd/common/block/spi/mmap_boot.c
index d29af41636..6a917195ce 100644
--- a/src/soc/amd/common/block/spi/mmap_boot.c
+++ b/src/soc/amd/common/block/spi/mmap_boot.c
@@ -3,6 +3,7 @@
 #include <boot_device.h>
 #include <endian.h>
 #include <spi_flash.h>
+#include <amdblocks/spi.h>
 
 #if CONFIG_ROM_SIZE >= (16 * MiB)
 #define ROM_SIZE (16 * MiB)
@@ -18,6 +19,13 @@ static const struct mem_region_device boot_dev =
 
 const struct region_device *boot_device_ro(void)
 {
+	/*
+	 * The following code assumes that ROM2 is mapped at flash offset 0. This is the default
+	 * configuration currently enforced by soft-straps.
+	 */
+	if (fch_spi_rom_remapping() != 0)
+		die("Non default SPI ROM remapping is not supported!");
+
 	return &boot_dev.rdev;
 }
 

From bdbf345eb81bec1f25e3c490f99981623e200210 Mon Sep 17 00:00:00 2001
From: Anand Vaikar <a.vaikar2021@gmail.com>
Date: Sat, 12 Apr 2025 13:16:28 +0530
Subject: [PATCH 0718/3886] soc/amd/cezanne: Enable system wake up from ACPI S3
 using USB keyboard

TEST: Tested by entering ACPI S3 sleep state and pressing any key
on USB keyboard wakes up the system.

Change-Id: Ieed635a7199f53c2e7c69c8f17b3ef50b76b8d91
Signed-off-by: Anand Vaikar <a.vaikar2021@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87287
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/soc/amd/cezanne/include/soc/smu.h | 1 +
 src/soc/amd/cezanne/smihandler.c      | 6 +++++-
 2 files changed, 6 insertions(+), 1 deletion(-)

diff --git a/src/soc/amd/cezanne/include/soc/smu.h b/src/soc/amd/cezanne/include/soc/smu.h
index 9216a38e8b..36b1969d31 100644
--- a/src/soc/amd/cezanne/include/soc/smu.h
+++ b/src/soc/amd/cezanne/include/soc/smu.h
@@ -12,6 +12,7 @@
 
 enum smu_message_id {
 	SMC_MSG_S3ENTRY = 0x0b,
+	SMC_MSG_USBS3ENTRY = 0x27,
 };
 
 /*
diff --git a/src/soc/amd/cezanne/smihandler.c b/src/soc/amd/cezanne/smihandler.c
index 8b8382cf89..1b6e91cb4c 100644
--- a/src/soc/amd/cezanne/smihandler.c
+++ b/src/soc/amd/cezanne/smihandler.c
@@ -6,6 +6,7 @@
 #include <amdblocks/psp.h>
 #include <amdblocks/smi.h>
 #include <amdblocks/smm.h>
+#include <amdblocks/smu.h>
 #include <arch/hlt.h>
 #include <arch/io.h>
 #include <console/console.h>
@@ -29,6 +30,7 @@ static void fch_slp_typ_handler(void)
 	uint32_t pci_ctrl, reg32;
 	uint16_t pm1cnt, reg16;
 	uint8_t slp_typ, rst_ctrl;
+	struct smu_payload msg = { 0 };
 
 	/* Figure out SLP_TYP */
 	pm1cnt = acpi_read16(MMIO_ACPI_PM1_CNT_BLK);
@@ -96,8 +98,10 @@ static void fch_slp_typ_handler(void)
 						reg32);
 		} /* if (CONFIG(ELOG_GSMI)) */
 
-		if (slp_typ == ACPI_S3)
+		if (slp_typ == ACPI_S3) {
 			psp_notify_sx_info(ACPI_S3);
+			send_smu_message(SMC_MSG_USBS3ENTRY, &msg);
+		}
 
 		smu_sx_entry(); /* Leave SlpTypeEn clear, SMU will set */
 		printk(BIOS_ERR, "System did not go to sleep\n");

From caf96774237e37069d0402247b6ae100f1e7f1d7 Mon Sep 17 00:00:00 2001
From: Felix Held <felix-coreboot@felixheld.de>
Date: Fri, 11 Apr 2025 14:46:01 +0200
Subject: [PATCH 0719/3886] soc/amd: add I3C controller base addresses and
 devicetree entries

Add the base addresses of the I3C controllers and the mmio devices to
the devicetree for the SoCs that have I3C controllers. The following
documentation was used to verify this:

Mendocino: #57243 Rev 3.08
Rembrandt: #56558 Rev 3.09 (in Mendocino directory)
Phoenix: #57019 Rev 3.09
Glinda: #57254 Rev 3.00
Faegan: #57928 Rev 1.51 (in Glinda directory)

For Genoa, those entries already existed in both its iomap.h and its
devicetree. Cezanne and Picasso don't have I3C controllers.

Change-Id: I6e8073e6498266b909b6cc5f589353f2ed23a62f
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87276
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/soc/amd/glinda/chipset.cb              | 4 ++++
 src/soc/amd/glinda/include/soc/iomap.h     | 5 +++++
 src/soc/amd/mendocino/chipset_mendocino.cb | 4 ++++
 src/soc/amd/mendocino/chipset_rembrandt.cb | 4 ++++
 src/soc/amd/mendocino/include/soc/iomap.h  | 5 +++++
 src/soc/amd/phoenix/chipset_fsp.cb         | 4 ++++
 src/soc/amd/phoenix/chipset_opensil.cb     | 4 ++++
 src/soc/amd/phoenix/include/soc/iomap.h    | 5 +++++
 8 files changed, 35 insertions(+)

diff --git a/src/soc/amd/glinda/chipset.cb b/src/soc/amd/glinda/chipset.cb
index a76be1ad31..321ecb75af 100644
--- a/src/soc/amd/glinda/chipset.cb
+++ b/src/soc/amd/glinda/chipset.cb
@@ -148,4 +148,8 @@ chip soc/amd/glinda
 	device mmio 0xfedce000 alias uart_2 off ops amd_uart_mmio_ops end
 	device mmio 0xfedcf000 alias uart_3 off ops amd_uart_mmio_ops end
 	device mmio 0xfedd1000 alias uart_4 off ops amd_uart_mmio_ops end
+	device mmio 0xfedd2000 alias i3c_0 off end
+	device mmio 0xfedd3000 alias i3c_1 off end
+	device mmio 0xfedd4000 alias i3c_2 off end
+	device mmio 0xfedd6000 alias i3c_3 off end
 end
diff --git a/src/soc/amd/glinda/include/soc/iomap.h b/src/soc/amd/glinda/include/soc/iomap.h
index eb4b58100b..bb68e17ed4 100644
--- a/src/soc/amd/glinda/include/soc/iomap.h
+++ b/src/soc/amd/glinda/include/soc/iomap.h
@@ -33,6 +33,11 @@
 #define APU_DMAC4_BASE			0xfedd0000
 #define APU_UART4_BASE			0xfedd1000
 
+#define APU_I3C0_BASE			0xfedd2000
+#define APU_I3C1_BASE			0xfedd3000
+#define APU_I3C2_BASE			0xfedd4000
+#define APU_I3C3_BASE			0xfedd6000
+
 #endif /* ENV_X86 */
 
 #define FLASH_BASE_ADDR			((0xffffffff - CONFIG_ROM_SIZE) + 1)
diff --git a/src/soc/amd/mendocino/chipset_mendocino.cb b/src/soc/amd/mendocino/chipset_mendocino.cb
index 3458caed06..81a7932e4a 100644
--- a/src/soc/amd/mendocino/chipset_mendocino.cb
+++ b/src/soc/amd/mendocino/chipset_mendocino.cb
@@ -93,4 +93,8 @@ chip soc/amd/mendocino
 	device mmio 0xfedce000 alias uart_2 off ops amd_uart_mmio_ops end
 	device mmio 0xfedcf000 alias uart_3 off ops amd_uart_mmio_ops end
 	device mmio 0xfedd1000 alias uart_4 off ops amd_uart_mmio_ops end
+	device mmio 0xfedd2000 alias i3c_0 off end
+	device mmio 0xfedd3000 alias i3c_1 off end
+	device mmio 0xfedd4000 alias i3c_2 off end
+	device mmio 0xfedd6000 alias i3c_3 off end
 end
diff --git a/src/soc/amd/mendocino/chipset_rembrandt.cb b/src/soc/amd/mendocino/chipset_rembrandt.cb
index aef0a8978b..cb549cf03a 100644
--- a/src/soc/amd/mendocino/chipset_rembrandt.cb
+++ b/src/soc/amd/mendocino/chipset_rembrandt.cb
@@ -96,4 +96,8 @@ chip soc/amd/mendocino
 	device mmio 0xfedce000 alias uart_2 off ops amd_uart_mmio_ops end
 	device mmio 0xfedcf000 alias uart_3 off ops amd_uart_mmio_ops end
 	device mmio 0xfedd1000 alias uart_4 off ops amd_uart_mmio_ops end
+	device mmio 0xfedd2000 alias i3c_0 off end
+	device mmio 0xfedd3000 alias i3c_1 off end
+	device mmio 0xfedd4000 alias i3c_2 off end
+	device mmio 0xfedd6000 alias i3c_3 off end
 end
diff --git a/src/soc/amd/mendocino/include/soc/iomap.h b/src/soc/amd/mendocino/include/soc/iomap.h
index d70773dfce..bffdb5f6a9 100644
--- a/src/soc/amd/mendocino/include/soc/iomap.h
+++ b/src/soc/amd/mendocino/include/soc/iomap.h
@@ -33,6 +33,11 @@
 #define APU_DMAC4_BASE			0xfedd0000
 #define APU_UART4_BASE			0xfedd1000
 
+#define APU_I3C0_BASE			0xfedd2000
+#define APU_I3C1_BASE			0xfedd3000
+#define APU_I3C2_BASE			0xfedd4000
+#define APU_I3C3_BASE			0xfedd6000
+
 #endif /* ENV_X86 */
 
 #define FLASH_BASE_ADDR			((0xffffffff - CONFIG_ROM_SIZE) + 1)
diff --git a/src/soc/amd/phoenix/chipset_fsp.cb b/src/soc/amd/phoenix/chipset_fsp.cb
index d461ac5d49..de05cbf794 100644
--- a/src/soc/amd/phoenix/chipset_fsp.cb
+++ b/src/soc/amd/phoenix/chipset_fsp.cb
@@ -145,4 +145,8 @@ chip soc/amd/phoenix
 	device mmio 0xfedce000 alias uart_2 off ops amd_uart_mmio_ops end
 	device mmio 0xfedcf000 alias uart_3 off ops amd_uart_mmio_ops end
 	device mmio 0xfedd1000 alias uart_4 off ops amd_uart_mmio_ops end
+	device mmio 0xfedd2000 alias i3c_0 off end
+	device mmio 0xfedd3000 alias i3c_1 off end
+	device mmio 0xfedd4000 alias i3c_2 off end
+	device mmio 0xfedd6000 alias i3c_3 off end
 end
diff --git a/src/soc/amd/phoenix/chipset_opensil.cb b/src/soc/amd/phoenix/chipset_opensil.cb
index fd1563b670..c2ea6c0680 100644
--- a/src/soc/amd/phoenix/chipset_opensil.cb
+++ b/src/soc/amd/phoenix/chipset_opensil.cb
@@ -165,4 +165,8 @@ chip soc/amd/phoenix
 	device mmio 0xfedce000 alias uart_2 off ops amd_uart_mmio_ops end
 	device mmio 0xfedcf000 alias uart_3 off ops amd_uart_mmio_ops end
 	device mmio 0xfedd1000 alias uart_4 off ops amd_uart_mmio_ops end
+	device mmio 0xfedd2000 alias i3c_0 off end
+	device mmio 0xfedd3000 alias i3c_1 off end
+	device mmio 0xfedd4000 alias i3c_2 off end
+	device mmio 0xfedd6000 alias i3c_3 off end
 end
diff --git a/src/soc/amd/phoenix/include/soc/iomap.h b/src/soc/amd/phoenix/include/soc/iomap.h
index 0b93057ce7..63d8b08a7a 100644
--- a/src/soc/amd/phoenix/include/soc/iomap.h
+++ b/src/soc/amd/phoenix/include/soc/iomap.h
@@ -33,6 +33,11 @@
 #define APU_DMAC4_BASE			0xfedd0000
 #define APU_UART4_BASE			0xfedd1000
 
+#define APU_I3C0_BASE			0xfedd2000
+#define APU_I3C1_BASE			0xfedd3000
+#define APU_I3C2_BASE			0xfedd4000
+#define APU_I3C3_BASE			0xfedd6000
+
 #endif /* ENV_X86 */
 
 #define FLASH_BASE_ADDR			((0xffffffff - CONFIG_ROM_SIZE) + 1)

From a527d13080bc7a7f606ae3a37e2ef35dc63df763 Mon Sep 17 00:00:00 2001
From: Felix Held <felix-coreboot@felixheld.de>
Date: Fri, 11 Apr 2025 15:00:24 +0200
Subject: [PATCH 0720/3886] soc/amd: report I3C controller MMIO to resource
 allocator

Add minimal common AMD I3C controller code that reports the MMIO region
used by the different I3C controllers to the resource allocator. For
this to work, select the introduced SOC_AMD_COMMON_BLOCK_I3C Kconfig
option and add the 'soc_amd_i3c_mmio_ops' device operations to the I3C
device devicetree entries on all SoCs that include I3C controllers.

Change-Id: Iebf709d2548f2535b2a2a03a4f6da9531559c238
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87277
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
---
 src/soc/amd/common/block/i2c/Kconfig       |  5 +++++
 src/soc/amd/common/block/i2c/Makefile.mk   |  1 +
 src/soc/amd/common/block/i2c/i3c.c         | 13 +++++++++++++
 src/soc/amd/genoa_poc/Kconfig              |  1 +
 src/soc/amd/genoa_poc/chipset.cb           |  8 ++++----
 src/soc/amd/glinda/Kconfig                 |  1 +
 src/soc/amd/glinda/chipset.cb              |  8 ++++----
 src/soc/amd/mendocino/Kconfig              |  1 +
 src/soc/amd/mendocino/chipset_mendocino.cb |  8 ++++----
 src/soc/amd/mendocino/chipset_rembrandt.cb |  8 ++++----
 src/soc/amd/phoenix/Kconfig                |  1 +
 src/soc/amd/phoenix/chipset_fsp.cb         |  8 ++++----
 src/soc/amd/phoenix/chipset_opensil.cb     |  8 ++++----
 13 files changed, 47 insertions(+), 24 deletions(-)
 create mode 100644 src/soc/amd/common/block/i2c/i3c.c

diff --git a/src/soc/amd/common/block/i2c/Kconfig b/src/soc/amd/common/block/i2c/Kconfig
index 9cdf8f517f..91f69078c8 100644
--- a/src/soc/amd/common/block/i2c/Kconfig
+++ b/src/soc/amd/common/block/i2c/Kconfig
@@ -27,3 +27,8 @@ config SOC_AMD_COMMON_BLOCK_I2C3_TPM_SHARED_WITH_PSP
 	  connected, which is shared between x86 and PSP. This is necessary to
 	  ensure proper communication with I2C peripherals connected to such
 	  bus.
+
+config SOC_AMD_COMMON_BLOCK_I3C
+	bool
+	help
+	  Select this option to add FCH I3C controller functions to the build.
diff --git a/src/soc/amd/common/block/i2c/Makefile.mk b/src/soc/amd/common/block/i2c/Makefile.mk
index 2812fb311d..793016dd7e 100644
--- a/src/soc/amd/common/block/i2c/Makefile.mk
+++ b/src/soc/amd/common/block/i2c/Makefile.mk
@@ -2,3 +2,4 @@
 all-$(CONFIG_SOC_AMD_COMMON_BLOCK_I2C) += i2c.c
 all-$(CONFIG_SOC_AMD_COMMON_BLOCK_I2C_PAD_CTRL) += i2c_pad_ctrl.c
 all-$(CONFIG_SOC_AMD_COMMON_BLOCK_I23C_PAD_CTRL) += i23c_pad_ctrl.c
+all_x86-$(CONFIG_SOC_AMD_COMMON_BLOCK_I3C) += i3c.c
diff --git a/src/soc/amd/common/block/i2c/i3c.c b/src/soc/amd/common/block/i2c/i3c.c
new file mode 100644
index 0000000000..9fb75d9e10
--- /dev/null
+++ b/src/soc/amd/common/block/i2c/i3c.c
@@ -0,0 +1,13 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <device/device.h>
+
+static void i3c_read_resources(struct device *dev)
+{
+	mmio_range(dev, 0, dev->path.mmio.addr, 4 * KiB);
+}
+
+struct device_operations soc_amd_i3c_mmio_ops = {
+	.read_resources = i3c_read_resources,
+	.set_resources = noop_set_resources,
+};
diff --git a/src/soc/amd/genoa_poc/Kconfig b/src/soc/amd/genoa_poc/Kconfig
index 3e7246b679..503b9fd999 100644
--- a/src/soc/amd/genoa_poc/Kconfig
+++ b/src/soc/amd/genoa_poc/Kconfig
@@ -29,6 +29,7 @@ config SOC_SPECIFIC_OPTIONS
 	select SOC_AMD_COMMON_BLOCK_DATA_FABRIC_EXTENDED_MMIO
 	select SOC_AMD_COMMON_BLOCK_HAS_ESPI
 	select SOC_AMD_COMMON_BLOCK_I2C
+	select SOC_AMD_COMMON_BLOCK_I3C
 	select SOC_AMD_COMMON_BLOCK_IOMMU
 	select SOC_AMD_COMMON_BLOCK_LPC
 	select SOC_AMD_COMMON_BLOCK_MCAX
diff --git a/src/soc/amd/genoa_poc/chipset.cb b/src/soc/amd/genoa_poc/chipset.cb
index 60eea56b2c..b22c1869ac 100644
--- a/src/soc/amd/genoa_poc/chipset.cb
+++ b/src/soc/amd/genoa_poc/chipset.cb
@@ -386,9 +386,9 @@ chip soc/amd/genoa_poc
 	device mmio 0xfedc9000 alias uart_0 off ops amd_uart_mmio_ops end
 	device mmio 0xfedca000 alias uart_1 off ops amd_uart_mmio_ops end
 	device mmio 0xfedce000 alias uart_2 off ops amd_uart_mmio_ops end
-	device mmio 0xfedd2000 alias i3c_0 off end
-	device mmio 0xfedd3000 alias i3c_1 off end
-	device mmio 0xfedd4000 alias i3c_2 off end
-	device mmio 0xfedd6000 alias i3c_3 off end
+	device mmio 0xfedd2000 alias i3c_0 off ops soc_amd_i3c_mmio_ops end
+	device mmio 0xfedd3000 alias i3c_1 off ops soc_amd_i3c_mmio_ops end
+	device mmio 0xfedd4000 alias i3c_2 off ops soc_amd_i3c_mmio_ops end
+	device mmio 0xfedd6000 alias i3c_3 off ops soc_amd_i3c_mmio_ops end
 
 end
diff --git a/src/soc/amd/glinda/Kconfig b/src/soc/amd/glinda/Kconfig
index a02492cb8c..17b349f071 100644
--- a/src/soc/amd/glinda/Kconfig
+++ b/src/soc/amd/glinda/Kconfig
@@ -53,6 +53,7 @@ config SOC_AMD_GLINDA
 	select SOC_AMD_COMMON_BLOCK_HAS_ESPI_ALERT_ENABLE # TODO: Check if this is still correct
 	select SOC_AMD_COMMON_BLOCK_I2C			# TODO: Check if this is still correct
 	select SOC_AMD_COMMON_BLOCK_I23C_PAD_CTRL	# TODO: Check if this is still correct
+	select SOC_AMD_COMMON_BLOCK_I3C
 	select SOC_AMD_COMMON_BLOCK_IOMMU		# TODO: Check if this is still correct
 	select SOC_AMD_COMMON_BLOCK_LPC			# TODO: Check if this is still correct
 	select SOC_AMD_COMMON_BLOCK_MCAX		# TODO: Check if this is still correct
diff --git a/src/soc/amd/glinda/chipset.cb b/src/soc/amd/glinda/chipset.cb
index 321ecb75af..853e05250f 100644
--- a/src/soc/amd/glinda/chipset.cb
+++ b/src/soc/amd/glinda/chipset.cb
@@ -148,8 +148,8 @@ chip soc/amd/glinda
 	device mmio 0xfedce000 alias uart_2 off ops amd_uart_mmio_ops end
 	device mmio 0xfedcf000 alias uart_3 off ops amd_uart_mmio_ops end
 	device mmio 0xfedd1000 alias uart_4 off ops amd_uart_mmio_ops end
-	device mmio 0xfedd2000 alias i3c_0 off end
-	device mmio 0xfedd3000 alias i3c_1 off end
-	device mmio 0xfedd4000 alias i3c_2 off end
-	device mmio 0xfedd6000 alias i3c_3 off end
+	device mmio 0xfedd2000 alias i3c_0 off ops soc_amd_i3c_mmio_ops end
+	device mmio 0xfedd3000 alias i3c_1 off ops soc_amd_i3c_mmio_ops end
+	device mmio 0xfedd4000 alias i3c_2 off ops soc_amd_i3c_mmio_ops end
+	device mmio 0xfedd6000 alias i3c_3 off ops soc_amd_i3c_mmio_ops end
 end
diff --git a/src/soc/amd/mendocino/Kconfig b/src/soc/amd/mendocino/Kconfig
index f67ecb27ef..b51e9e9f54 100644
--- a/src/soc/amd/mendocino/Kconfig
+++ b/src/soc/amd/mendocino/Kconfig
@@ -53,6 +53,7 @@ config SOC_AMD_REMBRANDT_BASE
 	select SOC_AMD_COMMON_BLOCK_HAS_ESPI_ALERT_ENABLE
 	select SOC_AMD_COMMON_BLOCK_I2C
 	select SOC_AMD_COMMON_BLOCK_I23C_PAD_CTRL
+	select SOC_AMD_COMMON_BLOCK_I3C
 	select SOC_AMD_COMMON_BLOCK_IOMMU
 	select SOC_AMD_COMMON_BLOCK_LPC
 	select SOC_AMD_COMMON_BLOCK_LPC_SPI_DMA
diff --git a/src/soc/amd/mendocino/chipset_mendocino.cb b/src/soc/amd/mendocino/chipset_mendocino.cb
index 81a7932e4a..5ab6a9cd88 100644
--- a/src/soc/amd/mendocino/chipset_mendocino.cb
+++ b/src/soc/amd/mendocino/chipset_mendocino.cb
@@ -93,8 +93,8 @@ chip soc/amd/mendocino
 	device mmio 0xfedce000 alias uart_2 off ops amd_uart_mmio_ops end
 	device mmio 0xfedcf000 alias uart_3 off ops amd_uart_mmio_ops end
 	device mmio 0xfedd1000 alias uart_4 off ops amd_uart_mmio_ops end
-	device mmio 0xfedd2000 alias i3c_0 off end
-	device mmio 0xfedd3000 alias i3c_1 off end
-	device mmio 0xfedd4000 alias i3c_2 off end
-	device mmio 0xfedd6000 alias i3c_3 off end
+	device mmio 0xfedd2000 alias i3c_0 off ops soc_amd_i3c_mmio_ops end
+	device mmio 0xfedd3000 alias i3c_1 off ops soc_amd_i3c_mmio_ops end
+	device mmio 0xfedd4000 alias i3c_2 off ops soc_amd_i3c_mmio_ops end
+	device mmio 0xfedd6000 alias i3c_3 off ops soc_amd_i3c_mmio_ops end
 end
diff --git a/src/soc/amd/mendocino/chipset_rembrandt.cb b/src/soc/amd/mendocino/chipset_rembrandt.cb
index cb549cf03a..0783b2ff7a 100644
--- a/src/soc/amd/mendocino/chipset_rembrandt.cb
+++ b/src/soc/amd/mendocino/chipset_rembrandt.cb
@@ -96,8 +96,8 @@ chip soc/amd/mendocino
 	device mmio 0xfedce000 alias uart_2 off ops amd_uart_mmio_ops end
 	device mmio 0xfedcf000 alias uart_3 off ops amd_uart_mmio_ops end
 	device mmio 0xfedd1000 alias uart_4 off ops amd_uart_mmio_ops end
-	device mmio 0xfedd2000 alias i3c_0 off end
-	device mmio 0xfedd3000 alias i3c_1 off end
-	device mmio 0xfedd4000 alias i3c_2 off end
-	device mmio 0xfedd6000 alias i3c_3 off end
+	device mmio 0xfedd2000 alias i3c_0 off ops soc_amd_i3c_mmio_ops end
+	device mmio 0xfedd3000 alias i3c_1 off ops soc_amd_i3c_mmio_ops end
+	device mmio 0xfedd4000 alias i3c_2 off ops soc_amd_i3c_mmio_ops end
+	device mmio 0xfedd6000 alias i3c_3 off ops soc_amd_i3c_mmio_ops end
 end
diff --git a/src/soc/amd/phoenix/Kconfig b/src/soc/amd/phoenix/Kconfig
index b15c12d44d..07b1bc0b83 100644
--- a/src/soc/amd/phoenix/Kconfig
+++ b/src/soc/amd/phoenix/Kconfig
@@ -49,6 +49,7 @@ config SOC_AMD_PHOENIX_BASE
 	select SOC_AMD_COMMON_BLOCK_HAS_ESPI_ALERT_ENABLE
 	select SOC_AMD_COMMON_BLOCK_I2C
 	select SOC_AMD_COMMON_BLOCK_I23C_PAD_CTRL
+	select SOC_AMD_COMMON_BLOCK_I3C
 	select SOC_AMD_COMMON_BLOCK_IOMMU
 	select SOC_AMD_COMMON_BLOCK_LPC
 	select SOC_AMD_COMMON_BLOCK_MCAX
diff --git a/src/soc/amd/phoenix/chipset_fsp.cb b/src/soc/amd/phoenix/chipset_fsp.cb
index de05cbf794..dcd51f55c8 100644
--- a/src/soc/amd/phoenix/chipset_fsp.cb
+++ b/src/soc/amd/phoenix/chipset_fsp.cb
@@ -145,8 +145,8 @@ chip soc/amd/phoenix
 	device mmio 0xfedce000 alias uart_2 off ops amd_uart_mmio_ops end
 	device mmio 0xfedcf000 alias uart_3 off ops amd_uart_mmio_ops end
 	device mmio 0xfedd1000 alias uart_4 off ops amd_uart_mmio_ops end
-	device mmio 0xfedd2000 alias i3c_0 off end
-	device mmio 0xfedd3000 alias i3c_1 off end
-	device mmio 0xfedd4000 alias i3c_2 off end
-	device mmio 0xfedd6000 alias i3c_3 off end
+	device mmio 0xfedd2000 alias i3c_0 off ops soc_amd_i3c_mmio_ops end
+	device mmio 0xfedd3000 alias i3c_1 off ops soc_amd_i3c_mmio_ops end
+	device mmio 0xfedd4000 alias i3c_2 off ops soc_amd_i3c_mmio_ops end
+	device mmio 0xfedd6000 alias i3c_3 off ops soc_amd_i3c_mmio_ops end
 end
diff --git a/src/soc/amd/phoenix/chipset_opensil.cb b/src/soc/amd/phoenix/chipset_opensil.cb
index c2ea6c0680..157daf7f9d 100644
--- a/src/soc/amd/phoenix/chipset_opensil.cb
+++ b/src/soc/amd/phoenix/chipset_opensil.cb
@@ -165,8 +165,8 @@ chip soc/amd/phoenix
 	device mmio 0xfedce000 alias uart_2 off ops amd_uart_mmio_ops end
 	device mmio 0xfedcf000 alias uart_3 off ops amd_uart_mmio_ops end
 	device mmio 0xfedd1000 alias uart_4 off ops amd_uart_mmio_ops end
-	device mmio 0xfedd2000 alias i3c_0 off end
-	device mmio 0xfedd3000 alias i3c_1 off end
-	device mmio 0xfedd4000 alias i3c_2 off end
-	device mmio 0xfedd6000 alias i3c_3 off end
+	device mmio 0xfedd2000 alias i3c_0 off ops soc_amd_i3c_mmio_ops end
+	device mmio 0xfedd3000 alias i3c_1 off ops soc_amd_i3c_mmio_ops end
+	device mmio 0xfedd4000 alias i3c_2 off ops soc_amd_i3c_mmio_ops end
+	device mmio 0xfedd6000 alias i3c_3 off ops soc_amd_i3c_mmio_ops end
 end

From 5441f57830def07aae439e26ada3568b9b9e351f Mon Sep 17 00:00:00 2001
From: Felix Held <felix-coreboot@felixheld.de>
Date: Fri, 11 Apr 2025 15:46:29 +0200
Subject: [PATCH 0721/3886] soc/amd/*/include/aoac_defs.h: add I3C controller
 AOAC IDs

Add the AOAC IDs of the I3C controllers. The following documentation was
used to verify this:

Genoa: #55901 Rev 0.40
Mendocino: #57243 Rev 3.08
Rembrandt: #56558 Rev 3.09 (in Mendocino directory)
Phoenix: #57019 Rev 3.09
Glinda: #57254 Rev 3.00
Faegan: #57928 Rev 1.51 (in Glinda directory)

Change-Id: I54d049c58756251506f94d220e1970ccec170918
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87279
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/soc/amd/genoa_poc/include/soc/aoac_defs.h | 4 ++++
 src/soc/amd/glinda/include/soc/aoac_defs.h    | 4 ++++
 src/soc/amd/mendocino/include/soc/aoac_defs.h | 4 ++++
 src/soc/amd/phoenix/include/soc/aoac_defs.h   | 4 ++++
 4 files changed, 16 insertions(+)

diff --git a/src/soc/amd/genoa_poc/include/soc/aoac_defs.h b/src/soc/amd/genoa_poc/include/soc/aoac_defs.h
index c5c11bb3bf..6225399a06 100644
--- a/src/soc/amd/genoa_poc/include/soc/aoac_defs.h
+++ b/src/soc/amd/genoa_poc/include/soc/aoac_defs.h
@@ -13,8 +13,12 @@
 #define FCH_AOAC_DEV_I2C5		10
 #define FCH_AOAC_DEV_UART0		11
 #define FCH_AOAC_DEV_UART1		12
+#define FCH_AOAC_DEV_I3C1		13
+#define FCH_AOAC_DEV_I3C2		14
+#define FCH_AOAC_DEV_I3C3		15
 #define FCH_AOAC_DEV_UART2		16
 #define FCH_AOAC_DEV_AMBA		17
+#define FCH_AOAC_DEV_I3C0		21
 #define FCH_AOAC_DEV_ESPI		27
 
 #endif /* AMD_GENOA_POC_AOAC_DEFS_H */
diff --git a/src/soc/amd/glinda/include/soc/aoac_defs.h b/src/soc/amd/glinda/include/soc/aoac_defs.h
index 98fb4cebfa..8704d9c7cb 100644
--- a/src/soc/amd/glinda/include/soc/aoac_defs.h
+++ b/src/soc/amd/glinda/include/soc/aoac_defs.h
@@ -13,9 +13,13 @@
 #define FCH_AOAC_DEV_I2C3		8
 #define FCH_AOAC_DEV_UART0		11
 #define FCH_AOAC_DEV_UART1		12
+#define FCH_AOAC_DEV_I3C1		13
+#define FCH_AOAC_DEV_I3C2		14
+#define FCH_AOAC_DEV_I3C3		15
 #define FCH_AOAC_DEV_UART2		16
 #define FCH_AOAC_DEV_AMBA		17
 #define FCH_AOAC_DEV_UART4		20
+#define FCH_AOAC_DEV_I3C0		21
 #define FCH_AOAC_DEV_UART3		26
 #define FCH_AOAC_DEV_ESPI		27
 
diff --git a/src/soc/amd/mendocino/include/soc/aoac_defs.h b/src/soc/amd/mendocino/include/soc/aoac_defs.h
index 5dcca03abf..e81b610e2f 100644
--- a/src/soc/amd/mendocino/include/soc/aoac_defs.h
+++ b/src/soc/amd/mendocino/include/soc/aoac_defs.h
@@ -13,9 +13,13 @@
 #define FCH_AOAC_DEV_I2C5		10
 #define FCH_AOAC_DEV_UART0		11
 #define FCH_AOAC_DEV_UART1		12
+#define FCH_AOAC_DEV_I3C1		13
+#define FCH_AOAC_DEV_I3C2		14
+#define FCH_AOAC_DEV_I3C3		15
 #define FCH_AOAC_DEV_UART2		16
 #define FCH_AOAC_DEV_AMBA		17
 #define FCH_AOAC_DEV_UART4		20
+#define FCH_AOAC_DEV_I3C0		21
 #define FCH_AOAC_DEV_UART3		26
 #define FCH_AOAC_DEV_ESPI		27
 
diff --git a/src/soc/amd/phoenix/include/soc/aoac_defs.h b/src/soc/amd/phoenix/include/soc/aoac_defs.h
index 96df50bace..2fe0cb726b 100644
--- a/src/soc/amd/phoenix/include/soc/aoac_defs.h
+++ b/src/soc/amd/phoenix/include/soc/aoac_defs.h
@@ -13,9 +13,13 @@
 #define FCH_AOAC_DEV_I2C5		10
 #define FCH_AOAC_DEV_UART0		11
 #define FCH_AOAC_DEV_UART1		12
+#define FCH_AOAC_DEV_I3C1		13
+#define FCH_AOAC_DEV_I3C2		14
+#define FCH_AOAC_DEV_I3C3		15
 #define FCH_AOAC_DEV_UART2		16
 #define FCH_AOAC_DEV_AMBA		17
 #define FCH_AOAC_DEV_UART4		20
+#define FCH_AOAC_DEV_I3C0		21
 #define FCH_AOAC_DEV_UART3		26
 #define FCH_AOAC_DEV_ESPI		27
 

From d65bb0b9fc3775c7bdcbebf4ee1317ddc2335425 Mon Sep 17 00:00:00 2001
From: Maximilian Brune <maximilian.brune@9elements.com>
Date: Sat, 12 Apr 2025 14:11:09 +0200
Subject: [PATCH 0722/3886] treewide: Remove remainders of ROM_BASE

commit a7eb390796ef ("mb/*/*/*.fmd: Start flash at 0")
caused a build failure for all mainboards that generate their FMAP
from the IFD (so intel only) instead of providing one themselves.
Jenkins didn't catch that, because apparently all mainboards that have
the IFD in the 3rdparty/blobs repository provide a custom FMAP.
So there was no defconfig that jenkins tested that would come across
this issue.

Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: Ia9852e8ef48148264d2d3f73eb667f3eb8b85005
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87288
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Erik van den Bogaert <ebogaert@eltan.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
---
 Makefile.mk            | 2 --
 util/ifdtool/ifdtool.c | 2 +-
 2 files changed, 1 insertion(+), 3 deletions(-)

diff --git a/Makefile.mk b/Makefile.mk
index 19bac29060..576cebd904 100644
--- a/Makefile.mk
+++ b/Makefile.mk
@@ -1098,7 +1098,6 @@ endif # ifneq($(CONFIG_IFD_CHIPSET),)
 # entire flash
 FMAP_ROM_SIZE := $(CONFIG_ROM_SIZE)
 # entire "BIOS" region (everything directly of concern to the host system)
-# relative to ROM_BASE
 FMAP_BIOS_BASE := $(call int-align, $(call int-subtract, $(CONFIG_ROM_SIZE) $(CONFIG_CBFS_SIZE)), 0x10000)
 FMAP_BIOS_SIZE := $(call int-align-down, $(shell echo $(CONFIG_CBFS_SIZE) | tr A-F a-f), 0x10000)
 # position and size of flashmap, relative to BIOS_BASE
@@ -1186,7 +1185,6 @@ DEFAULT_FLASHMAP:=$(top)/util/cbfstool/default.fmd
 # entire flash
 FMAP_ROM_SIZE := $(CONFIG_ROM_SIZE)
 # entire "BIOS" region (everything directly of concern to the host system)
-# relative to ROM_BASE
 FMAP_BIOS_BASE := 0
 FMAP_BIOS_SIZE := $(CONFIG_CBFS_SIZE)
 # position and size of flashmap, relative to BIOS_BASE
diff --git a/util/ifdtool/ifdtool.c b/util/ifdtool/ifdtool.c
index 94105efe52..b21a89c0e1 100644
--- a/util/ifdtool/ifdtool.c
+++ b/util/ifdtool/ifdtool.c
@@ -1094,7 +1094,7 @@ static void create_fmap_template(char *image, int size, const char *layout_fname
 		exit(EXIT_FAILURE);
 	}
 
-	char *bbuf = "FLASH@##ROM_BASE## ##ROM_SIZE## {\n";
+	char *bbuf = "FLASH ##ROM_SIZE## {\n";
 	if (write(layout_fd, bbuf, strlen(bbuf)) < 0) {
 		perror("Could not write to file");
 		exit(EXIT_FAILURE);

From 36805eedcaabd7e7707b4dc34d7a91d31c993163 Mon Sep 17 00:00:00 2001
From: Maxim Polyakov <max.senia.poliak@gmail.com>
Date: Fri, 11 Apr 2025 09:22:34 +0300
Subject: [PATCH 0723/3886] superio/fintek/f81866d: Fix HWM port address

The HWM port is +5 to the base address stored in LDN 0x4 at index
0x60/0x61. Take this rule into account when configuring the monitor,
as it was done for Fintek SIO chips in the superiotool utility [1].

[1] commit d92745b

TEST=Run coreboot on the motherboard with the Fintek F81966 chip (which
is architecturally compatible) with pnp_write_hwm5_index() in the HWM
initialization code:
- the fans are regulated correctly;
- superiotool prints the values of the configuration registers updated
  during initialization.

Change-Id: If39400e56a7d0792a5bc8f312c29dd5e98a0b2d3
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87273
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Harrie Paijmans <hpaijmans@eltan.com>
---
 src/superio/fintek/f81866d/f81866d_hwm.c | 32 ++++++++++++------------
 1 file changed, 16 insertions(+), 16 deletions(-)

diff --git a/src/superio/fintek/f81866d/f81866d_hwm.c b/src/superio/fintek/f81866d/f81866d_hwm.c
index a82adb3472..2883c02e96 100644
--- a/src/superio/fintek/f81866d/f81866d_hwm.c
+++ b/src/superio/fintek/f81866d/f81866d_hwm.c
@@ -51,34 +51,34 @@ void f81866d_hwm_init(struct device *dev)
 	pnp_enter_conf_mode(dev);
 
 	/* Use AMD TSI */
-	pnp_write_index(port, HWM_AMD_TSI_ADDR, reg->hwm_amd_tsi_addr);
-	pnp_write_index(port, HWM_AMD_TSI_CONTROL_REG, reg->hwm_amd_tsi_control);
+	pnp_write_hwm5_index(port, HWM_AMD_TSI_ADDR, reg->hwm_amd_tsi_addr);
+	pnp_write_hwm5_index(port, HWM_AMD_TSI_CONTROL_REG, reg->hwm_amd_tsi_control);
 
 	/* Set temp1 sensor to thermistor */
-	pnp_write_index(port, TEMP_SENS_TYPE_REG, reg->hwm_temp_sens_type);
+	pnp_write_hwm5_index(port, TEMP_SENS_TYPE_REG, reg->hwm_temp_sens_type);
 
 	/* Select FAN Type */
-	pnp_write_index(port, HWM_FAN_SEL, reg->hwm_fan_select);
+	pnp_write_hwm5_index(port, HWM_FAN_SEL, reg->hwm_fan_select);
 
 	/* Select FAN Mode*/
-	pnp_write_index(port, HWM_FAN_MODE, reg->hwm_fan_mode);
+	pnp_write_hwm5_index(port, HWM_FAN_MODE, reg->hwm_fan_mode);
 
 	/* Set Boundaries */
-	pnp_write_index(port, HWM_FAN2_BOUND1, reg->hwm_fan2_bound1);
-	pnp_write_index(port, HWM_FAN2_BOUND2, reg->hwm_fan2_bound2);
-	pnp_write_index(port, HWM_FAN2_BOUND3, reg->hwm_fan2_bound3);
-	pnp_write_index(port, HWM_FAN2_BOUND4, reg->hwm_fan2_bound4);
+	pnp_write_hwm5_index(port, HWM_FAN2_BOUND1, reg->hwm_fan2_bound1);
+	pnp_write_hwm5_index(port, HWM_FAN2_BOUND2, reg->hwm_fan2_bound2);
+	pnp_write_hwm5_index(port, HWM_FAN2_BOUND3, reg->hwm_fan2_bound3);
+	pnp_write_hwm5_index(port, HWM_FAN2_BOUND4, reg->hwm_fan2_bound4);
 
 	/* Set Speed */
-	pnp_write_index(port, HWM_FAN2_SEG1_SPEED_COUNT, reg->hwm_fan2_seg1_speed);
-	pnp_write_index(port, HWM_FAN2_SEG2_SPEED_COUNT, reg->hwm_fan2_seg2_speed);
-	pnp_write_index(port, HWM_FAN2_SEG3_SPEED_COUNT, reg->hwm_fan2_seg3_speed);
-	pnp_write_index(port, HWM_FAN2_SEG4_SPEED_COUNT, reg->hwm_fan2_seg4_speed);
-	pnp_write_index(port, HWM_FAN2_SEG5_SPEED_COUNT, reg->hwm_fan2_seg5_speed);
+	pnp_write_hwm5_index(port, HWM_FAN2_SEG1_SPEED_COUNT, reg->hwm_fan2_seg1_speed);
+	pnp_write_hwm5_index(port, HWM_FAN2_SEG2_SPEED_COUNT, reg->hwm_fan2_seg2_speed);
+	pnp_write_hwm5_index(port, HWM_FAN2_SEG3_SPEED_COUNT, reg->hwm_fan2_seg3_speed);
+	pnp_write_hwm5_index(port, HWM_FAN2_SEG4_SPEED_COUNT, reg->hwm_fan2_seg4_speed);
+	pnp_write_hwm5_index(port, HWM_FAN2_SEG5_SPEED_COUNT, reg->hwm_fan2_seg5_speed);
 
 	/* Set Fan control freq */
-	pnp_write_index(port, HWM_FAN3_CONTROL, reg->hwm_fan3_control);
-	pnp_write_index(port, HWM_FAN2_TEMP_MAP_SEL, reg->hwm_fan2_temp_map_select);
+	pnp_write_hwm5_index(port, HWM_FAN3_CONTROL, reg->hwm_fan3_control);
+	pnp_write_hwm5_index(port, HWM_FAN2_TEMP_MAP_SEL, reg->hwm_fan2_temp_map_select);
 
 	pnp_exit_conf_mode(dev);
 }

From ace8bb45f764f2143ff10cb3c37022810a04c146 Mon Sep 17 00:00:00 2001
From: Maxim Polyakov <max.senia.poliak@gmail.com>
Date: Fri, 11 Apr 2025 09:47:52 +0300
Subject: [PATCH 0724/3886] superio/fintek/f81866d: Undo set config mode for
 HWM

The hardware monitor provides access to its address space via the base
address stored in LDN 0x4 at index 0x60/0x61. There is no need to set
the configuration mode here, since the registers in the LDN are not
programmed.

Change-Id: Ic27c9eee5a58727a70fc0ebe60a643f45a418d36
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87274
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
---
 src/superio/fintek/f81866d/f81866d_hwm.c | 4 ----
 1 file changed, 4 deletions(-)

diff --git a/src/superio/fintek/f81866d/f81866d_hwm.c b/src/superio/fintek/f81866d/f81866d_hwm.c
index 2883c02e96..9862e14ed4 100644
--- a/src/superio/fintek/f81866d/f81866d_hwm.c
+++ b/src/superio/fintek/f81866d/f81866d_hwm.c
@@ -48,8 +48,6 @@ void f81866d_hwm_init(struct device *dev)
 	const struct superio_fintek_f81866d_config *reg = dev->chip_info;
 	u16 port = res->base;
 
-	pnp_enter_conf_mode(dev);
-
 	/* Use AMD TSI */
 	pnp_write_hwm5_index(port, HWM_AMD_TSI_ADDR, reg->hwm_amd_tsi_addr);
 	pnp_write_hwm5_index(port, HWM_AMD_TSI_CONTROL_REG, reg->hwm_amd_tsi_control);
@@ -79,6 +77,4 @@ void f81866d_hwm_init(struct device *dev)
 	/* Set Fan control freq */
 	pnp_write_hwm5_index(port, HWM_FAN3_CONTROL, reg->hwm_fan3_control);
 	pnp_write_hwm5_index(port, HWM_FAN2_TEMP_MAP_SEL, reg->hwm_fan2_temp_map_select);
-
-	pnp_exit_conf_mode(dev);
 }

From 2057751509c37f2c9fca9790986e41a370cf374f Mon Sep 17 00:00:00 2001
From: Harrie Paijmans <hpaijmans@eltan.com>
Date: Mon, 7 Apr 2025 16:12:03 +0200
Subject: [PATCH 0725/3886] superio/fintek: Add support for f81966d

This patch adds support for the Fintek f81966d SuperIO,
which is very similar to the fintek/f81866d.

Datasheet:
	- Name: F81966D/A, Release Date: Oct 2023, Version: V0.21P

BUG=NA
TEST=Customer platform with F81966D, verified with 'superiotool -de'

Change-Id: Ibe3987b6e15eb07b92d7f5a7de2bd511de85e2f7
Signed-off-by: Harrie Paijmans <hpaijmans@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87198
Reviewed-by: Erik van den Bogaert <ebogaert@eltan.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
---
 src/superio/fintek/Makefile.mk               |   1 +
 src/superio/fintek/f81966d/Kconfig           |   5 +
 src/superio/fintek/f81966d/Makefile.mk       |   4 +
 src/superio/fintek/f81966d/chip.h            |  83 +++++++++
 src/superio/fintek/f81966d/f81966d.h         |  92 ++++++++++
 src/superio/fintek/f81966d/f81966d_gpio.c    | 182 +++++++++++++++++++
 src/superio/fintek/f81966d/f81966d_hwm.c     |  56 ++++++
 src/superio/fintek/f81966d/f81966d_uart.c    |  55 ++++++
 src/superio/fintek/f81966d/fintek_internal.h |  15 ++
 src/superio/fintek/f81966d/superio.c         |  82 +++++++++
 10 files changed, 575 insertions(+)
 create mode 100644 src/superio/fintek/f81966d/Kconfig
 create mode 100644 src/superio/fintek/f81966d/Makefile.mk
 create mode 100644 src/superio/fintek/f81966d/chip.h
 create mode 100644 src/superio/fintek/f81966d/f81966d.h
 create mode 100644 src/superio/fintek/f81966d/f81966d_gpio.c
 create mode 100644 src/superio/fintek/f81966d/f81966d_hwm.c
 create mode 100644 src/superio/fintek/f81966d/f81966d_uart.c
 create mode 100644 src/superio/fintek/f81966d/fintek_internal.h
 create mode 100644 src/superio/fintek/f81966d/superio.c

diff --git a/src/superio/fintek/Makefile.mk b/src/superio/fintek/Makefile.mk
index b9cfe4da5a..5e9708f9a9 100644
--- a/src/superio/fintek/Makefile.mk
+++ b/src/superio/fintek/Makefile.mk
@@ -11,3 +11,4 @@ subdirs-y += f71869ad
 subdirs-y += f81865f
 subdirs-y += f81866d
 subdirs-y += f81803a
+subdirs-y += f81966d
diff --git a/src/superio/fintek/f81966d/Kconfig b/src/superio/fintek/f81966d/Kconfig
new file mode 100644
index 0000000000..3f66f466da
--- /dev/null
+++ b/src/superio/fintek/f81966d/Kconfig
@@ -0,0 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
+config SUPERIO_FINTEK_F81966D
+	bool
+	select SUPERIO_FINTEK_COMMON_PRE_RAM
diff --git a/src/superio/fintek/f81966d/Makefile.mk b/src/superio/fintek/f81966d/Makefile.mk
new file mode 100644
index 0000000000..7016b0c83b
--- /dev/null
+++ b/src/superio/fintek/f81966d/Makefile.mk
@@ -0,0 +1,4 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+ramstage-$(CONFIG_SUPERIO_FINTEK_F81966D) += f81966d_hwm.c f81966d_uart.c f81966d_gpio.c
+ramstage-$(CONFIG_SUPERIO_FINTEK_F81966D) += superio.c
diff --git a/src/superio/fintek/f81966d/chip.h b/src/superio/fintek/f81966d/chip.h
new file mode 100644
index 0000000000..2e75e2434d
--- /dev/null
+++ b/src/superio/fintek/f81966d/chip.h
@@ -0,0 +1,83 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#ifndef SUPERIO_FINTEK_F81966D_CHIP_H
+#define SUPERIO_FINTEK_F81966D_CHIP_H
+
+#include <stdint.h>
+
+struct superio_fintek_f81966d_config {
+	/* AMD TSI */
+	uint8_t hwm_amd_tsi_addr;
+	uint8_t hwm_amd_tsi_control;
+
+	/* Fan control */
+	uint8_t hwm_fan_select;
+	uint8_t hwm_fan_mode;
+	uint8_t hwm_fan3_control;
+	uint8_t hwm_fan2_temp_map_select;
+
+	uint8_t hwm_fan2_bound1;
+	uint8_t hwm_fan2_bound2;
+	uint8_t hwm_fan2_bound3;
+	uint8_t hwm_fan2_bound4;
+	uint8_t hwm_fan2_seg1_speed;
+	uint8_t hwm_fan2_seg2_speed;
+	uint8_t hwm_fan2_seg3_speed;
+	uint8_t hwm_fan2_seg4_speed;
+	uint8_t hwm_fan2_seg5_speed;
+
+	/* Temp sensor type */
+	uint8_t hwm_temp_sens_type;
+
+	/* gpio control, range bits [0:7] map to GPIOx0:GPIOx7 */
+	uint8_t use_gpio0;
+	uint8_t gpio0_enable;
+	uint8_t gpio0_data;
+	uint8_t gpio0_drive;
+
+	uint8_t use_gpio1;
+	uint8_t gpio1_enable;
+	uint8_t gpio1_data;
+	uint8_t gpio1_drive;
+
+	uint8_t use_gpio2;
+	uint8_t gpio2_enable;
+	uint8_t gpio2_data;
+
+	uint8_t use_gpio3;
+	uint8_t gpio3_enable;
+	uint8_t gpio3_data;
+	uint8_t gpio3_drive;
+
+	uint8_t use_gpio4;
+	uint8_t gpio4_enable;
+	uint8_t gpio4_data;
+	uint8_t gpio4_drive;
+
+	uint8_t use_gpio5;
+	uint8_t gpio5_enable;
+	uint8_t gpio5_data;
+	uint8_t gpio5_drive;
+
+	uint8_t use_gpio6;
+	uint8_t gpio6_enable;
+	uint8_t gpio6_data;
+	uint8_t gpio6_drive;
+
+	uint8_t use_gpio7;
+	uint8_t gpio7_enable;
+	uint8_t gpio7_data;
+	uint8_t gpio7_drive;
+
+	uint8_t use_gpio8;
+	uint8_t gpio8_enable;
+	uint8_t gpio8_data;
+	uint8_t gpio8_drive;
+
+	uint8_t use_gpio9;
+	uint8_t gpio9_enable;
+	uint8_t gpio9_data;
+	uint8_t gpio9_drive;
+};
+
+#endif /* SUPERIO_FINTEK_F81966D_CHIP_H */
diff --git a/src/superio/fintek/f81966d/f81966d.h b/src/superio/fintek/f81966d/f81966d.h
new file mode 100644
index 0000000000..871ce853b7
--- /dev/null
+++ b/src/superio/fintek/f81966d/f81966d.h
@@ -0,0 +1,92 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#ifndef SUPERIO_FINTEK_F81966_H
+#define SUPERIO_FINTEK_F81966_H
+
+/*
+ * Datasheet:
+ *		- Name: F81966D/A, Release Date: Oct 2023, Version: V0.21P
+ */
+
+/* General registers */
+#define LDN_REG					0x07
+#define PORT_SELECT_REGISTER	0x27
+#define MULTI_FUNC_SEL1_REG		0x28
+#define MULTI_FUNC_SEL3_REG		0x29
+#define GPIO_FUNC_SEL_REG		0x2A /* differs on bank: 0=11/10 1=13/12 2=15/14 3=17/16 */
+#define MULTI_FUNC_SEL4_REG		0x2B
+#define MULTI_FUNC_SEL5_REG		0x2C
+#define IRQ_SHARE_REGISTER	0xF0
+#define FIFO_SEL_MODE		0xF6
+
+/* Logical Device Numbers (LDN) */
+#define F81966D_SP1	0x10	/* UART1 */
+#define F81966D_SP2	0x11	/* UART2 */
+#define F81966D_SP3	0x12	/* UART3 */
+#define F81966D_SP4	0x13	/* UART4 */
+#define F81966D_SP5	0x14	/* UART5 */
+#define F81966D_SP6	0x15	/* UART6 */
+#define F81966D_PP	0x03	/* Parallel Port */
+#define F81966D_HWM	0x04	/* Hardware Monitor */
+#define F81966D_KBC	0x05	/* Keyboard/Mouse */
+#define F81966D_GPIO	0x06	/* General Purpose I/O (GPIO) */
+#define F81966D_WDT	0x07	/* Watchdog */
+#define F81966D_PME	0x0A	/* Power Management Events (PME) */
+#define F81966D_SPI	0x0F	/* SPI */
+
+/* Register addresses for HWM */
+/* Choose between AMD and Intel */
+#define HWM_AMD_TSI_ADDR		0x08
+#define HWM_AMD_TSI_CONTROL_REG		0x0A
+/* Set temp sensors type */
+#define TEMP_SENS_TYPE_REG		0x6B
+/* FAN prog sel */
+#define HWM_FAN3_CONTROL		0x9A
+#define HWM_FAN_SEL			0x94
+#define HWM_FAN_MODE			0x96
+#define HWM_FAN2_TEMP_MAP_SEL		0xBF
+/* Fan 2 - 4 Boundaries */
+#define HWM_FAN2_BOUND1			0xB6
+#define HWM_FAN2_BOUND2			0xB7
+#define HWM_FAN2_BOUND3			0xB8
+#define HWM_FAN2_BOUND4			0xB9
+/* Fan 2 - 5 Segment speeds */
+#define HWM_FAN2_SEG1_SPEED_COUNT	0xBA
+#define HWM_FAN2_SEG2_SPEED_COUNT	0xBB
+#define HWM_FAN2_SEG3_SPEED_COUNT	0xBC
+#define HWM_FAN2_SEG4_SPEED_COUNT	0xBD
+#define HWM_FAN2_SEG5_SPEED_COUNT	0xBE
+
+/* Register addresses for GPIO */
+/* GPIO registers */
+#define GPIO0X_OUTPUT_ENABLE_REGISTER	0xF0
+#define GPIO1X_OUTPUT_ENABLE_REGISTER	0xE0
+#define GPIO2X_OUTPUT_ENABLE_REGISTER	0xD0
+#define GPIO3X_OUTPUT_ENABLE_REGISTER	0xC0
+#define GPIO4X_OUTPUT_ENABLE_REGISTER	0xB0
+#define GPIO5X_OUTPUT_ENABLE_REGISTER	0xA0
+#define GPIO6X_OUTPUT_ENABLE_REGISTER	0x90
+#define GPIO7X_OUTPUT_ENABLE_REGISTER	0x80
+#define GPIO8X_OUTPUT_ENABLE_REGISTER	0x88
+#define GPIO9X_OUTPUT_ENABLE_REGISTER	0x98
+#define GPIO0X_OUTPUT_DATA_REGISTER		0xF1
+#define GPIO1X_OUTPUT_DATA_REGISTER		0xE1
+#define GPIO2X_OUTPUT_DATA_REGISTER		0xD1
+#define GPIO3X_OUTPUT_DATA_REGISTER		0xC1
+#define GPIO4X_OUTPUT_DATA_REGISTER		0xB1
+#define GPIO5X_OUTPUT_DATA_REGISTER		0xA1
+#define GPIO6X_OUTPUT_DATA_REGISTER		0x91
+#define GPIO7X_OUTPUT_DATA_REGISTER		0x81
+#define GPIO8X_OUTPUT_DATA_REGISTER		0x89
+#define GPIO9X_OUTPUT_DATA_REGISTER		0x99
+#define GPIO0X_DRIVE_ENABLE_REGISTER	0xF3
+#define GPIO1X_DRIVE_ENABLE_REGISTER	0xE3
+#define GPIO3X_DRIVE_ENABLE_REGISTER	0xC3
+#define GPIO4X_DRIVE_ENABLE_REGISTER	0xB3
+#define GPIO5X_DRIVE_ENABLE_REGISTER	0xA3
+#define GPIO6X_DRIVE_ENABLE_REGISTER	0x93
+#define GPIO7X_DRIVE_ENABLE_REGISTER	0x83
+#define GPIO8X_DRIVE_ENABLE_REGISTER	0x8B
+#define GPIO9X_DRIVE_ENABLE_REGISTER	0x9B
+
+#endif /* SUPERIO_FINTEK_F81966_H */
diff --git a/src/superio/fintek/f81966d/f81966d_gpio.c b/src/superio/fintek/f81966d/f81966d_gpio.c
new file mode 100644
index 0000000000..32180c5963
--- /dev/null
+++ b/src/superio/fintek/f81966d/f81966d_gpio.c
@@ -0,0 +1,182 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pnp.h>
+#include "fintek_internal.h"
+#include "chip.h"
+#include "f81966d.h"
+
+/*
+ * Set the values for the register using the mask
+ * The mask has the writable bits high so the write the bits [3:2] & [0] the mask would be
+ * 0xd = 0b00001101.
+ */
+void set_reg(struct device *dev, u8 port, u8 mask, u8 val)
+{
+	u8 tmp = pnp_read_config(dev, port);
+	pnp_write_config(dev, port, (tmp & ~mask) | (val & mask));
+}
+
+/*
+ * Select a bank as indicated by the spec.
+ * Write the BANKID and 0 registers in the same call.
+ */
+u8 select_bank(struct device *dev, u8 bank)
+{
+	if (bank > 3) {
+		printk(BIOS_WARNING, "%s: GPIO Bank not in range.\n", __func__);
+		return -1;
+	}
+	/* write 0x27[3:2] = BANKID, 0x27[0] = 0 */
+	set_reg(dev, PORT_SELECT_REGISTER, 0x0D, (bank << 2));
+	return 0;
+}
+
+/*
+ * F81966D_gpio_init enables all necessary registers for GPIO
+ * Fintek needs to know if pins are used as GPIO or UART pins
+ * Share interrupt usage needs to be enabled
+ */
+void f81966d_gpio_init(struct device *dev)
+{
+	struct superio_fintek_f81966d_config *conf = dev->chip_info;
+	struct resource *res = probe_resource(dev, PNP_IDX_IO0);
+	u8 tmp;
+
+	if (!res) {
+		printk(BIOS_WARNING, "%s: No GPIO resource found.\n", __func__);
+		return;
+	}
+
+	pnp_enter_conf_mode(dev);
+
+	if (conf->use_gpio0) {
+		select_bank(dev, 0);
+		set_reg(dev, MULTI_FUNC_SEL5_REG, 0x1F, 0x1F);
+		set_reg(dev, MULTI_FUNC_SEL1_REG, 0x0C, 0x00);
+
+		select_bank(dev, 1);
+		set_reg(dev, MULTI_FUNC_SEL5_REG, 0x44, 0x0);
+
+		set_reg(dev, GPIO0X_OUTPUT_ENABLE_REGISTER, 0xFF, conf->gpio0_enable);
+		set_reg(dev, GPIO0X_OUTPUT_DATA_REGISTER, 0xFF, conf->gpio0_data);
+		set_reg(dev, GPIO0X_DRIVE_ENABLE_REGISTER, 0xFF, conf->gpio0_drive);
+	}
+
+	if (conf->use_gpio1) {
+		select_bank(dev, 0);
+		set_reg(dev, GPIO_FUNC_SEL_REG, 0x77, 0x000);
+		set_reg(dev, MULTI_FUNC_SEL1_REG, 0x8C, 0x00);
+		set_reg(dev, MULTI_FUNC_SEL5_REG, 0x10, 0x0);
+
+		select_bank(dev, 1);
+		set_reg(dev, MULTI_FUNC_SEL5_REG, 0x21, 0x0);
+		set_reg(dev, MULTI_FUNC_SEL1_REG, 0x0C, 0x00);
+		set_reg(dev, GPIO_FUNC_SEL_REG, 0x77, 0x000);
+
+		select_bank(dev, 2);
+		set_reg(dev, GPIO_FUNC_SEL_REG, 0x77, 0x000);
+
+		select_bank(dev, 3);
+		set_reg(dev, GPIO_FUNC_SEL_REG, 0x77, 0x000);
+
+		set_reg(dev, GPIO1X_OUTPUT_ENABLE_REGISTER, 0xFF, conf->gpio1_enable);
+		set_reg(dev, GPIO1X_OUTPUT_DATA_REGISTER, 0xFF, conf->gpio1_data);
+		set_reg(dev, GPIO1X_DRIVE_ENABLE_REGISTER, 0xFF, conf->gpio1_drive);
+	}
+
+	if (conf->use_gpio2) {
+		select_bank(dev, 2);
+		set_reg(dev, MULTI_FUNC_SEL5_REG, 0xFF, 0xFF);
+		select_bank(dev, 1);
+		set_reg(dev, MULTI_FUNC_SEL5_REG, 0x02, 0x0);
+
+		set_reg(dev, GPIO2X_OUTPUT_ENABLE_REGISTER, 0xFF, conf->gpio2_enable);
+		set_reg(dev, GPIO2X_OUTPUT_DATA_REGISTER, 0xFF, conf->gpio2_data);
+	}
+
+	if (conf->use_gpio3) {
+		select_bank(dev, 0);
+		set_reg(dev, MULTI_FUNC_SEL3_REG, 0x30, 0x00);
+
+		set_reg(dev, GPIO3X_OUTPUT_ENABLE_REGISTER, 0xFF, conf->gpio3_enable);
+		set_reg(dev, GPIO3X_OUTPUT_DATA_REGISTER, 0xFF, conf->gpio3_data);
+		set_reg(dev, GPIO3X_DRIVE_ENABLE_REGISTER, 0xFF, conf->gpio3_drive);
+	}
+
+	if (conf->use_gpio4) {
+		select_bank(dev, 0);
+		set_reg(dev, MULTI_FUNC_SEL3_REG, 0xC0, 0x00);
+
+		set_reg(dev, GPIO4X_OUTPUT_ENABLE_REGISTER, 0xFF, conf->gpio4_enable);
+		set_reg(dev, GPIO4X_OUTPUT_DATA_REGISTER, 0xFF, conf->gpio4_data);
+		set_reg(dev, GPIO4X_DRIVE_ENABLE_REGISTER, 0xFF, conf->gpio4_drive);
+	}
+
+	if (conf->use_gpio5) {
+		set_reg(dev, PORT_SELECT_REGISTER, 0x02, 0x00);
+
+		select_bank(dev, 0);
+		set_reg(dev, MULTI_FUNC_SEL1_REG, 0x03, 0x00);
+		select_bank(dev, 1);
+		set_reg(dev, MULTI_FUNC_SEL1_REG, 0x10, 0x00);
+
+		/* set in/output pins */
+		set_reg(dev, GPIO5X_OUTPUT_ENABLE_REGISTER, 0xFF, conf->gpio5_enable);
+		set_reg(dev, GPIO5X_OUTPUT_DATA_REGISTER, 0xFF, conf->gpio5_data);
+		set_reg(dev, GPIO5X_DRIVE_ENABLE_REGISTER, 0xFF, conf->gpio5_drive);
+	}
+
+	if (conf->use_gpio6) {
+		select_bank(dev, 0);
+		set_reg(dev, MULTI_FUNC_SEL1_REG, 0x0C, 0x00);
+		set_reg(dev, MULTI_FUNC_SEL4_REG, 0xE0, 0xE0);
+
+		set_reg(dev, GPIO6X_OUTPUT_ENABLE_REGISTER, 0xFF, conf->gpio6_enable);
+		set_reg(dev, GPIO6X_OUTPUT_DATA_REGISTER, 0xFF, conf->gpio6_data);
+		set_reg(dev, GPIO6X_DRIVE_ENABLE_REGISTER, 0xFF, conf->gpio6_drive);
+	}
+
+	if (conf->use_gpio7) {
+		select_bank(dev, 0);
+		set_reg(dev, MULTI_FUNC_SEL1_REG, 0x20, 0x20);
+		set_reg(dev, MULTI_FUNC_SEL4_REG, 0x01, 0x00);
+
+		set_reg(dev, GPIO7X_OUTPUT_ENABLE_REGISTER, 0xFF, conf->gpio7_enable);
+		set_reg(dev, GPIO7X_OUTPUT_DATA_REGISTER, 0xFF, conf->gpio7_data);
+		set_reg(dev, GPIO7X_DRIVE_ENABLE_REGISTER, 0xFF, conf->gpio7_drive);
+	}
+
+	if (conf->use_gpio8) {
+		select_bank(dev, 0);
+		set_reg(dev, MULTI_FUNC_SEL1_REG, 0x60, 0x20);
+
+		set_reg(dev, GPIO8X_OUTPUT_ENABLE_REGISTER, 0xFF, conf->gpio8_enable);
+		set_reg(dev, GPIO8X_OUTPUT_DATA_REGISTER, 0xFF, conf->gpio8_data);
+		set_reg(dev, GPIO8X_DRIVE_ENABLE_REGISTER, 0xFF, conf->gpio8_drive);
+	}
+
+	if (conf->use_gpio9) {
+		select_bank(dev, 0);
+		set_reg(dev, MULTI_FUNC_SEL4_REG, 0x02, 0x00);
+		select_bank(dev, 1);
+		set_reg(dev, MULTI_FUNC_SEL5_REG, 0x80, 0x00);
+		select_bank(dev, 3);
+		set_reg(dev, MULTI_FUNC_SEL4_REG, 0xFF, 0xFF);
+
+		set_reg(dev, GPIO9X_OUTPUT_ENABLE_REGISTER, 0xFF, conf->gpio8_enable);
+		set_reg(dev, GPIO9X_OUTPUT_DATA_REGISTER, 0xFF, conf->gpio8_data);
+		set_reg(dev, GPIO9X_DRIVE_ENABLE_REGISTER, 0xFF, conf->gpio8_drive);
+	}
+
+	/* Select GPIO in LDN register */
+	pnp_write_config(dev, LDN_REG, dev->path.pnp.device & 0xFF);
+	/* Set IRQ trigger mode from active low to high (Bit 3) */
+	tmp = pnp_read_config(dev, FIFO_SEL_MODE);
+	pnp_write_config(dev, FIFO_SEL_MODE, tmp | 0x8);
+	/* Enable share interrupt (Bit 0) */
+	pnp_write_config(dev, IRQ_SHARE_REGISTER, 0x01);
+
+	pnp_exit_conf_mode(dev);
+}
diff --git a/src/superio/fintek/f81966d/f81966d_hwm.c b/src/superio/fintek/f81966d/f81966d_hwm.c
new file mode 100644
index 0000000000..1e995a92ac
--- /dev/null
+++ b/src/superio/fintek/f81966d/f81966d_hwm.c
@@ -0,0 +1,56 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+/* Setup only for Fan2
+ * TODO: Add support for Fan1 and Fan3
+ */
+
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pnp.h>
+#include <superio/hwm5_conf.h>
+#include "fintek_internal.h"
+#include "chip.h"
+#include "f81966d.h"
+
+void f81966d_hwm_init(struct device *dev)
+{
+	struct resource *res = probe_resource(dev, PNP_IDX_IO0);
+
+	if (!res) {
+		printk(BIOS_WARNING, "Super I/O HWM: No HWM resource found.\n");
+		return;
+	}
+
+	const struct superio_fintek_f81966d_config *reg = dev->chip_info;
+	u16 port = res->base;
+
+	/* Use AMD TSI */
+	pnp_write_hwm5_index(port, HWM_AMD_TSI_ADDR, reg->hwm_amd_tsi_addr);
+	pnp_write_hwm5_index(port, HWM_AMD_TSI_CONTROL_REG, reg->hwm_amd_tsi_control);
+
+	/* Set temp1 sensor to thermistor */
+	pnp_write_hwm5_index(port, TEMP_SENS_TYPE_REG, reg->hwm_temp_sens_type);
+
+	/* Select FAN Type */
+	pnp_write_hwm5_index(port, HWM_FAN_SEL, reg->hwm_fan_select);
+
+	/* Select FAN Mode*/
+	pnp_write_hwm5_index(port, HWM_FAN_MODE, reg->hwm_fan_mode);
+
+	/* Set Boundaries */
+	pnp_write_hwm5_index(port, HWM_FAN2_BOUND1, reg->hwm_fan2_bound1);
+	pnp_write_hwm5_index(port, HWM_FAN2_BOUND2, reg->hwm_fan2_bound2);
+	pnp_write_hwm5_index(port, HWM_FAN2_BOUND3, reg->hwm_fan2_bound3);
+	pnp_write_hwm5_index(port, HWM_FAN2_BOUND4, reg->hwm_fan2_bound4);
+
+	/* Set Speed */
+	pnp_write_hwm5_index(port, HWM_FAN2_SEG1_SPEED_COUNT, reg->hwm_fan2_seg1_speed);
+	pnp_write_hwm5_index(port, HWM_FAN2_SEG2_SPEED_COUNT, reg->hwm_fan2_seg2_speed);
+	pnp_write_hwm5_index(port, HWM_FAN2_SEG3_SPEED_COUNT, reg->hwm_fan2_seg3_speed);
+	pnp_write_hwm5_index(port, HWM_FAN2_SEG4_SPEED_COUNT, reg->hwm_fan2_seg4_speed);
+	pnp_write_hwm5_index(port, HWM_FAN2_SEG5_SPEED_COUNT, reg->hwm_fan2_seg5_speed);
+
+	/* Set Fan control freq */
+	pnp_write_hwm5_index(port, HWM_FAN3_CONTROL, reg->hwm_fan3_control);
+	pnp_write_hwm5_index(port, HWM_FAN2_TEMP_MAP_SEL, reg->hwm_fan2_temp_map_select);
+}
diff --git a/src/superio/fintek/f81966d/f81966d_uart.c b/src/superio/fintek/f81966d/f81966d_uart.c
new file mode 100644
index 0000000000..8c2b69722d
--- /dev/null
+++ b/src/superio/fintek/f81966d/f81966d_uart.c
@@ -0,0 +1,55 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pnp.h>
+#include "fintek_internal.h"
+#include "chip.h"
+#include "f81966d.h"
+
+/*
+ * F81966D_uart_init enables all necessary registers for UART 3/4
+ * Fintek needs to know if pins are used as GPIO or UART pins
+ * Share interrupt usage needs to be enabled
+ */
+void f81966d_uart_init(struct device *dev)
+{
+	struct resource *res = probe_resource(dev, PNP_IDX_IO0);
+	u8 tmp;
+
+	if (!res) {
+		printk(BIOS_WARNING, "%s: No UART resource found.\n", __func__);
+		return;
+	}
+
+	pnp_enter_conf_mode(dev);
+
+	/*
+	 * Set Port Select Register (Bit 0) = 0
+	 * before accessing Multi Function Select 3 Register
+	 */
+	tmp = pnp_read_config(dev, PORT_SELECT_REGISTER);
+	pnp_write_config(dev, PORT_SELECT_REGISTER, tmp & 0xFE);
+
+	/* Set UART 3 function (Bit 4/5), otherwise pin 36-43 are GPIO */
+	if (dev->path.pnp.device == F81966D_SP3) {
+		tmp = pnp_read_config(dev, MULTI_FUNC_SEL3_REG);
+		pnp_write_config(dev, MULTI_FUNC_SEL3_REG, tmp | 0x30);
+	}
+
+	/* Set UART 4 function (Bit 6/7), otherwise pin 44-51 are GPIO */
+	if (dev->path.pnp.device == F81966D_SP4) {
+		tmp = pnp_read_config(dev, MULTI_FUNC_SEL3_REG);
+		pnp_write_config(dev, MULTI_FUNC_SEL3_REG, tmp | 0xC0);
+	}
+
+	/* Select UART X in LDN register */
+	pnp_write_config(dev, LDN_REG, dev->path.pnp.device & 0xff);
+	/* Set IRQ trigger mode from active low to high (Bit 3) */
+	tmp = pnp_read_config(dev, FIFO_SEL_MODE);
+	pnp_write_config(dev, FIFO_SEL_MODE, tmp | 0x8);
+	/* Enable share interrupt (Bit 0) */
+	pnp_write_config(dev, IRQ_SHARE_REGISTER, 0x01);
+
+	pnp_exit_conf_mode(dev);
+}
diff --git a/src/superio/fintek/f81966d/fintek_internal.h b/src/superio/fintek/f81966d/fintek_internal.h
new file mode 100644
index 0000000000..0e2142f925
--- /dev/null
+++ b/src/superio/fintek/f81966d/fintek_internal.h
@@ -0,0 +1,15 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#ifndef SUPERIO_FINTEK_F81966D_INTERNAL_H
+#define SUPERIO_FINTEK_F81966D_INTERNAL_H
+
+#include <device/pnp.h>
+
+void f81966d_hwm_init(struct device *dev);
+void f81966d_uart_init(struct device *dev);
+void f81966d_gpio_init(struct device *dev);
+
+void set_reg(struct device *dev, u8 port, u8 mask, u8 val);
+u8 select_bank(struct device *dev, u8 bank);
+
+#endif /* SUPERIO_FINTEK_F81966D_INTERNAL_H */
diff --git a/src/superio/fintek/f81966d/superio.c b/src/superio/fintek/f81966d/superio.c
new file mode 100644
index 0000000000..a3b5527c85
--- /dev/null
+++ b/src/superio/fintek/f81966d/superio.c
@@ -0,0 +1,82 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <device/device.h>
+#include <device/pnp.h>
+#include <superio/conf_mode.h>
+#include <pc80/keyboard.h>
+
+#include "chip.h"
+#include "fintek_internal.h"
+#include "f81966d.h"
+
+static void f81966d_init(struct device *dev)
+{
+	if (!dev->enabled)
+		return;
+
+	switch (dev->path.pnp.device) {
+	case F81966D_KBC:
+		pc_keyboard_init(NO_AUX_DEVICE);
+		break;
+	case F81966D_HWM:
+		/* Fixing temp sensor read out and init Fan control */
+		f81966d_hwm_init(dev);
+		break;
+	case F81966D_SP1:
+		/* Enable Uart1 and IRQ share register */
+		f81966d_uart_init(dev);
+		break;
+	case F81966D_SP2:
+		/* Enable Uart2 and IRQ share register */
+		f81966d_uart_init(dev);
+		break;
+	case F81966D_SP3:
+		/* Enable Uart3 and IRQ share register */
+		f81966d_uart_init(dev);
+		break;
+	case F81966D_SP4:
+		/* Enable Uart4 and IRQ share register */
+		f81966d_uart_init(dev);
+		break;
+	case F81966D_GPIO:
+		/* Enable GPIO */
+		f81966d_gpio_init(dev);
+		break;
+	}
+}
+
+static struct device_operations ops = {
+	.read_resources   = pnp_read_resources,
+	.set_resources    = pnp_set_resources,
+	.enable_resources = pnp_enable_resources,
+	.enable           = pnp_alt_enable,
+	.init             = f81966d_init,
+	.ops_pnp_mode     = &pnp_conf_mode_8787_aa,
+};
+
+static struct pnp_info pnp_dev_info[] = {
+	/* TODO: some of the 0x7f8 values may need to be corrected. */
+	{ NULL, F81966D_SP1,  PNP_IO0 | PNP_IRQ0, 0x7f8, },
+	{ NULL, F81966D_SP2,  PNP_IO0 | PNP_IRQ0, 0x7f8, },
+	{ NULL, F81966D_SP3,  PNP_IO0 | PNP_IRQ0, 0x7f8, },
+	{ NULL, F81966D_SP4,  PNP_IO0 | PNP_IRQ0, 0x7f8, },
+	{ NULL, F81966D_SP5,  PNP_IO0 | PNP_IRQ0, 0x7f8, },
+	{ NULL, F81966D_SP6,  PNP_IO0 | PNP_IRQ0, 0x7f8, },
+	{ NULL, F81966D_KBC,  PNP_IO0 | PNP_IRQ0 | PNP_IRQ1, 0x07ff, },
+	{ NULL, F81966D_PP,   PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x07f8, },
+	{ NULL, F81966D_HWM,  PNP_IO0 | PNP_IRQ0, 0xff8, },
+	{ NULL, F81966D_GPIO, PNP_IO0, 0xff8, },
+	{ NULL, F81966D_PME, },
+	{ NULL, F81966D_WDT, },
+	{ NULL, F81966D_SPI, },
+};
+
+static void enable_dev(struct device *dev)
+{
+	pnp_enable_devices(dev, &ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info);
+}
+
+struct chip_operations superio_fintek_f81966d_ops = {
+	.name = "Fintek F81966D-I Super I/O",
+	.enable_dev = enable_dev
+};

From 0b22edb1fdce84bcea784058dd4716a4b0fc4340 Mon Sep 17 00:00:00 2001
From: Maxim Polyakov <max.senia.poliak@gmail.com>
Date: Sat, 28 Dec 2024 12:43:11 +0300
Subject: [PATCH 0726/3886] Documentation/util/intelp2m: Add info for
 developers

Change-Id: I9cc886e607c1aba92b94e06419d45d9581371065
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85791
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 Documentation/util/intelp2m/index.md | 110 ++++++++++++++++++++++++++-
 1 file changed, 108 insertions(+), 2 deletions(-)

diff --git a/Documentation/util/intelp2m/index.md b/Documentation/util/intelp2m/index.md
index 758f8c4d72..851d5c528a 100644
--- a/Documentation/util/intelp2m/index.md
+++ b/Documentation/util/intelp2m/index.md
@@ -28,7 +28,6 @@ image.
 ```bash
 cd util/intelp2m
 make
-./intelp2m -version
 ```
 
 Set automatic argument completion:
@@ -263,7 +262,114 @@ Show more details:
 ./intelp2m -fields ?
 ```
 
-## Unit testing
+## For developers
+
+### Version
+
+```bash
+./intelp2m -version
+```
+
+The version string includes several parts:
+
+```text
+{major}.{minor}-{last commit in the intelp2m directory}-{?dirty}
+```
+
+`major` - incompatible API changes (e.g. remove or update a command line option);
+`minor` - new platform, new feature or adding a new command line option.
+
+The version is added to the generated `gpio.h` file and it is necessary to support the project.
+
+```c
+/* Pad configuration was generated automatically using intelp2m 2.5-870c694 */
+static const struct pad_config gpio_table[] = {
+...
+```
+
+Please do not remove this information, as it makes support easier!
+
+### Adding support for new platforms
+
+The platform-dependent code is located in `./platforms/`. Each PCH and SoC is in a separate
+package with a name corresponding to this platform (adl, apl, snr, ...). The macro generation
+code for all platforms is in the `common` directory.
+
+The package file must contain the structure `BasePlatform struct{}` with methods for the
+`PlatformIf interface{}` from the `common` package:
+
+```Go
+type PlatformIf interface {
+	RemapResetSource(*Macro)
+	Pull(*Macro)
+	AddGpiMacro(*Macro)
+	AddGpoMacro(*Macro)
+	AddNativeFunctionMacro(*Macro)
+	AddNoConnMacro(*Macro)
+	GetRegisterDW0() *register.DW0
+	GetRegisterDW1() *register.DW1
+}
+```
+
+Some methods (for example, register access methods: `GetRegisterDW0()` and `GetRegisterDW1()`)
+are already defined in the base platform from `common`. Therefore, embedding should be used in
+the basic platform structure to avoid code duplication:
+
+```Go
+type BasePlatform struct {
+	common.BasePlatform
+}
+```
+
+Since GPIO controllers are similar across intel platforms, the macro generation code can also be
+reused. You can use any platform instead of `common.BasePlatform` from the catalog to reuse its
+methods and redefine those that differ in logic.
+
+The platform file should also contain the slice `GPPGroups[]` with templates for pad names from
+`inteltool.log`, register masks `DW0` and `DW1` (the analysis will be only for the bits in these
+masks), the base platform constructor - `InitBasePlatform()`, and `GetPlatform()` that provides
+the platform interface.
+
+```Go
+const (
+	DW0Mask = (0b1 << 27) | (0b1 << 18) | (0b00111111 << 11) | (0b00111111 << 2) | (0b1 << 1)
+	DW1Mask = 0b11111101111111111100001111111111
+)
+
+// "GPP_A", "GPP_B", "GPP_C", "GPP_D", "GPP_E", "GPP_F", "GPP_G", "GPP_H", "GPP_R", "GPP_S",
+// "GPP_T", "GPD", "HVMOS", "VGPIO5"
+var GPPGroups = []string{"GPP_", "GPD", "VGPIO"}
+
+type BasePlatform struct {
+	// based on the Cannon Lake platform
+	cnl.BasePlatform
+}
+
+func InitBasePlatform(dw0, dw0mask uint32, dw1, dw1mask uint32) BasePlatform {
+	return BasePlatform{cnl.InitBasePlatform(dw0, dw0mask, dw1, dw1mask)}
+}
+
+func GetPlatform(dw0, dw1 uint32) common.PlatformIf {
+	p := InitBasePlatform(dw0, DW0Mask, dw1, DW1Mask)
+	return &p
+}
+
+// Override BasePlatform.RemapResetSource()
+func (p *BasePlatform) RemapResetSource(m *common.Macro) {
+    // Some code is here
+}
+```
+
+- Use `GetPlatform()` and `GPPGroups[]` in the file `./platform/platform.go` to define the
+  resources for the parser.
+- Add the platform argument for the options `-p` (`-platform`) to `cli/options.go`.
+- Update the documentation in `Documentation/util/intelp2m/index.md`.
+- Add unit tests.
+
+[Here](https://review.coreboot.org/c/coreboot/+/84191) is an example of porting the Intel
+Jasper lake platform.
+
+### Unit testing
 
 Please run the tests before creating a new commit:
 

From 22ee635d0f5c3d05654a0c02ae71ab70656564d9 Mon Sep 17 00:00:00 2001
From: Harrie Paijmans <hpaijmans@eltan.com>
Date: Wed, 9 Apr 2025 14:19:14 +0200
Subject: [PATCH 0727/3886] device/pci_ids: Add Amston Lake CPU IDs

Intel processor number X7433RE.
Based on docs 721616 rev 2.3.

BUG=NA
TEST=Boots on Intel Alder Lake CRB with X7433RE processor

Change-Id: Ia43945887e7d536b5b7387a4dda4e245973c27ee
Signed-off-by: Harrie Paijmans <hpaijmans@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87243
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Erik van den Bogaert <ebogaert@eltan.com>
---
 src/include/device/pci_ids.h                         |  3 +++
 src/soc/intel/alderlake/bootblock/report_platform.c  |  4 ++++
 src/soc/intel/alderlake/cpu.c                        | 12 ++++++++++++
 src/soc/intel/alderlake/fsp_params.c                 |  3 +++
 src/soc/intel/alderlake/include/soc/cpu.h            |  1 +
 src/soc/intel/common/block/systemagent/systemagent.c |  3 +++
 6 files changed, 26 insertions(+)

diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h
index 7d695b21b7..6a45fbb4a8 100644
--- a/src/include/device/pci_ids.h
+++ b/src/include/device/pci_ids.h
@@ -4427,6 +4427,9 @@
 #define PCI_DID_INTEL_ADL_N_ID_7		0x4679
 #define PCI_DID_INTEL_ADL_N_ID_8		0x467C
 #define PCI_DID_INTEL_ADL_N_ID_9		0x4677
+#define PCI_DID_INTEL_ASL_ID_1			0x4632
+#define PCI_DID_INTEL_ASL_ID_2			0x4674
+#define PCI_DID_INTEL_ASL_ID_3			0x4675
 #define PCI_DID_INTEL_MTL_M_ID			0x7D00
 #define PCI_DID_INTEL_MTL_P_ID_1		0x7D01
 #define PCI_DID_INTEL_MTL_P_ID_2		0x7D02
diff --git a/src/soc/intel/alderlake/bootblock/report_platform.c b/src/soc/intel/alderlake/bootblock/report_platform.c
index 0c84d73644..9b684d185e 100644
--- a/src/soc/intel/alderlake/bootblock/report_platform.c
+++ b/src/soc/intel/alderlake/bootblock/report_platform.c
@@ -81,6 +81,9 @@ static struct {
 	{ PCI_DID_INTEL_ADL_S_ID_12, "Alderlake-S (2+0)" },
 	{ PCI_DID_INTEL_ADL_S_ID_13, "Alderlake-S" },
 	{ PCI_DID_INTEL_ADL_S_ID_14, "Alderlake-S" },
+	{ PCI_DID_INTEL_ASL_ID_1, "Amstonlake" },
+	{ PCI_DID_INTEL_ASL_ID_2, "Amstonlake" },
+	{ PCI_DID_INTEL_ASL_ID_3, "Amstonlake" },
 	{ PCI_DID_INTEL_RPL_HX_ID_1, "Raptorlake-HX (8+16)" },
 	{ PCI_DID_INTEL_RPL_HX_ID_2, "Raptorlake-HX (8+12)" },
 	{ PCI_DID_INTEL_RPL_HX_ID_3, "Raptorlake-HX (8+8)" },
@@ -110,6 +113,7 @@ static struct {
 } pch_table[] = {
 	{ PCI_DID_INTEL_ADP_M_N_ESPI_1, "Alderlake-N SKU" },
 	{ PCI_DID_INTEL_ADP_M_N_ESPI_2, "Alderlake-N SKU" },
+	{ PCI_DID_INTEL_ADP_M_N_ESPI_10, "Amstonlake SKU" },
 	{ PCI_DID_INTEL_ADP_S_ESPI_H610E, "AlderLake-S H610E" },
 	{ PCI_DID_INTEL_ADP_S_ESPI_Q670E, "AlderLake-S Q670E" },
 	{ PCI_DID_INTEL_ADP_S_ESPI_R680E, "AlderLake-S R680E" },
diff --git a/src/soc/intel/alderlake/cpu.c b/src/soc/intel/alderlake/cpu.c
index 9e4ed52c44..c2efff3419 100644
--- a/src/soc/intel/alderlake/cpu.c
+++ b/src/soc/intel/alderlake/cpu.c
@@ -249,6 +249,12 @@ enum adl_cpu_type get_adl_cpu_type(void)
 		PCI_DID_INTEL_ADL_N_ID_9,
 	};
 
+	const uint16_t asl_mch_ids[] = {
+		PCI_DID_INTEL_ASL_ID_1,
+		PCI_DID_INTEL_ASL_ID_2,
+		PCI_DID_INTEL_ASL_ID_3,
+	};
+
 	const uint16_t rpl_hx_mch_ids[] = {
 		PCI_DID_INTEL_RPL_HX_ID_1,
 		PCI_DID_INTEL_RPL_HX_ID_2,
@@ -298,6 +304,11 @@ enum adl_cpu_type get_adl_cpu_type(void)
 			return ADL_S;
 	}
 
+	for (size_t i = 0; i < ARRAY_SIZE(asl_mch_ids); i++) {
+		if (asl_mch_ids[i] == mchid)
+			return ASL;
+	}
+
 	for (size_t i = 0; i < ARRAY_SIZE(rpl_s_mch_ids); i++) {
 		if (rpl_s_mch_ids[i] == mchid)
 			return RPL_S;
@@ -332,6 +343,7 @@ uint8_t get_supported_lpm_mask(void)
 	case ADL_M: /* fallthrough */
 	case ADL_N:
 	case ADL_P:
+	case ASL:
 	case RPL_P:
 		return LPM_S0i2_0 | LPM_S0i3_0;
 	case ADL_S:
diff --git a/src/soc/intel/alderlake/fsp_params.c b/src/soc/intel/alderlake/fsp_params.c
index 28c9169529..380f40ba60 100644
--- a/src/soc/intel/alderlake/fsp_params.c
+++ b/src/soc/intel/alderlake/fsp_params.c
@@ -518,6 +518,9 @@ static uint16_t get_vccin_aux_imon_iccmax(const struct soc_intel_alderlake_confi
 	case PCI_DID_INTEL_ADL_S_ID_10:
 	case PCI_DID_INTEL_ADL_S_ID_11:
 	case PCI_DID_INTEL_ADL_S_ID_12:
+	case PCI_DID_INTEL_ASL_ID_1:
+	case PCI_DID_INTEL_ASL_ID_2:
+	case PCI_DID_INTEL_ASL_ID_3:
 	case PCI_DID_INTEL_RPL_HX_ID_1:
 	case PCI_DID_INTEL_RPL_HX_ID_2:
 	case PCI_DID_INTEL_RPL_HX_ID_3:
diff --git a/src/soc/intel/alderlake/include/soc/cpu.h b/src/soc/intel/alderlake/include/soc/cpu.h
index d081e85a57..36f966a937 100644
--- a/src/soc/intel/alderlake/include/soc/cpu.h
+++ b/src/soc/intel/alderlake/include/soc/cpu.h
@@ -25,6 +25,7 @@ enum adl_cpu_type {
 	ADL_N,
 	ADL_P,
 	ADL_S,
+	ASL,
 	RPL_HX,
 	RPL_P,
 	RPL_S,
diff --git a/src/soc/intel/common/block/systemagent/systemagent.c b/src/soc/intel/common/block/systemagent/systemagent.c
index 098c3c4385..3a6273505a 100644
--- a/src/soc/intel/common/block/systemagent/systemagent.c
+++ b/src/soc/intel/common/block/systemagent/systemagent.c
@@ -538,6 +538,9 @@ static const unsigned short systemagent_ids[] = {
 	PCI_DID_INTEL_ADL_N_ID_7,
 	PCI_DID_INTEL_ADL_N_ID_8,
 	PCI_DID_INTEL_ADL_N_ID_9,
+	PCI_DID_INTEL_ASL_ID_1,
+	PCI_DID_INTEL_ASL_ID_2,
+	PCI_DID_INTEL_ASL_ID_3,
 	PCI_DID_INTEL_RPL_HX_ID_1,
 	PCI_DID_INTEL_RPL_HX_ID_2,
 	PCI_DID_INTEL_RPL_HX_ID_3,

From c8f7f677453d0958a49409a11369ee28a929c27b Mon Sep 17 00:00:00 2001
From: Harrie Paijmans <hpaijmans@eltan.com>
Date: Wed, 9 Apr 2025 15:20:24 +0200
Subject: [PATCH 0728/3886] soc/intel/alderlake/vr_config: Add i7-1370PE
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Add the Raptorlake-P/H/H Refresh (6+8)(28W) with MCH_ID 0xa706
to the vr_config table.

BUG=NA
TEST=Customer platform with Raptorlake-P

Change-Id: Iabc668e81596b136470cbe2a1c84f8f53403448f
Signed-off-by: Harrie Paijmans <hpaijmans@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87245
Reviewed-by: Erik van den Bogaert <ebogaert@eltan.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
---
 src/soc/intel/alderlake/vr_config.c | 6 +++++-
 1 file changed, 5 insertions(+), 1 deletion(-)

diff --git a/src/soc/intel/alderlake/vr_config.c b/src/soc/intel/alderlake/vr_config.c
index 95dba9fbd0..7128a2a79a 100644
--- a/src/soc/intel/alderlake/vr_config.c
+++ b/src/soc/intel/alderlake/vr_config.c
@@ -81,7 +81,7 @@
  * |                |    GT     |  3.2  |  3.2  |    55   |      86     |  28000   |
  * +----------------+-----------+-------+-------+---------+-------------+----------+
  * | RPL-P 482(28W) |    IA     |  2.3  |  2.3  |   102   |      33     |  28000   |
- * +                +-----------+-------+-------+---------+-------------+----------+
+ * +       682(28W) +-----------+-------+-------+---------+-------------+----------+
  * |                |    GT     |  3.2  |  3.2  |    55   |      33     |  28000   |
  * +----------------+-----------+-------+-------+---------+-------------+----------+
  * | RPL-P 282(15W) |    IA     |  2.8  |  2.8  |    80   |      22     |  28000   |
@@ -134,6 +134,7 @@ static const struct vr_lookup vr_config_ll[] = {
 	{ PCI_DID_INTEL_ADL_N_ID_7, 12, VR_CFG_ALL_DOMAINS_LOADLINE(5.0, 6.5) },
 	{ PCI_DID_INTEL_ADL_N_ID_8, 6,  VR_CFG_ALL_DOMAINS_LOADLINE(5.0, 6.5) },
 	{ PCI_DID_INTEL_ADL_N_ID_9, 10, VR_CFG_ALL_DOMAINS_LOADLINE(5.0, 6.5) },
+	{ PCI_DID_INTEL_RPL_P_ID_1, 28, VR_CFG_ALL_DOMAINS_LOADLINE(2.3, 3.2) },
 	{ PCI_DID_INTEL_RPL_P_ID_1, 45, VR_CFG_ALL_DOMAINS_LOADLINE(2.3, 3.2) },
 	{ PCI_DID_INTEL_RPL_P_ID_2, 28, VR_CFG_ALL_DOMAINS_LOADLINE(2.3, 3.2) },
 	{ PCI_DID_INTEL_RPL_P_ID_2, 45, VR_CFG_ALL_DOMAINS_LOADLINE(2.3, 3.2) },
@@ -204,6 +205,7 @@ static const struct vr_lookup vr_config_icc[] = {
 	{ PCI_DID_INTEL_ADL_N_ID_7, 12, VR_CFG_ALL_DOMAINS_ICC(37, 23) },
 	{ PCI_DID_INTEL_ADL_N_ID_8, 6,  VR_CFG_ALL_DOMAINS_ICC(27, 23) },
 	{ PCI_DID_INTEL_ADL_N_ID_9, 10, VR_CFG_ALL_DOMAINS_ICC(27, 23) },
+	{ PCI_DID_INTEL_RPL_P_ID_1, 28, VR_CFG_ALL_DOMAINS_ICC(102, 55) },
 	{ PCI_DID_INTEL_RPL_P_ID_1, 45, VR_CFG_ALL_DOMAINS_ICC(160, 55) },
 	{ PCI_DID_INTEL_RPL_P_ID_2, 28, VR_CFG_ALL_DOMAINS_ICC(102, 55) },
 	{ PCI_DID_INTEL_RPL_P_ID_2, 45, VR_CFG_ALL_DOMAINS_ICC(160, 55) },
@@ -274,6 +276,7 @@ static const struct vr_lookup vr_config_tdc_timewindow[] = {
 	{ PCI_DID_INTEL_ADL_N_ID_7, 12, VR_CFG_ALL_DOMAINS_TDC(28000, 28000) },
 	{ PCI_DID_INTEL_ADL_N_ID_8, 6,  VR_CFG_ALL_DOMAINS_TDC(28000, 28000) },
 	{ PCI_DID_INTEL_ADL_N_ID_9, 10, VR_CFG_ALL_DOMAINS_TDC(28000, 28000) },
+	{ PCI_DID_INTEL_RPL_P_ID_1, 28, VR_CFG_ALL_DOMAINS_TDC(28000, 28000) },
 	{ PCI_DID_INTEL_RPL_P_ID_1, 45, VR_CFG_ALL_DOMAINS_TDC(28000, 28000) },
 	{ PCI_DID_INTEL_RPL_P_ID_2, 28, VR_CFG_ALL_DOMAINS_TDC(28000, 28000) },
 	{ PCI_DID_INTEL_RPL_P_ID_2, 45, VR_CFG_ALL_DOMAINS_TDC(28000, 28000) },
@@ -344,6 +347,7 @@ static const struct vr_lookup vr_config_tdc_currentlimit[] = {
 	{ PCI_DID_INTEL_ADL_N_ID_7, 12, VR_CFG_ALL_DOMAINS_TDC_CURRENT(12, 20) },
 	{ PCI_DID_INTEL_ADL_N_ID_8, 6,  VR_CFG_ALL_DOMAINS_TDC_CURRENT(12, 16) },
 	{ PCI_DID_INTEL_ADL_N_ID_9, 10, VR_CFG_ALL_DOMAINS_TDC_CURRENT(12, 16) },
+	{ PCI_DID_INTEL_RPL_P_ID_1, 28, VR_CFG_ALL_DOMAINS_TDC_CURRENT(33, 33) },
 	{ PCI_DID_INTEL_RPL_P_ID_1, 45, VR_CFG_ALL_DOMAINS_TDC_CURRENT(86, 86) },
 	{ PCI_DID_INTEL_RPL_P_ID_2, 28, VR_CFG_ALL_DOMAINS_TDC_CURRENT(33, 33) },
 	{ PCI_DID_INTEL_RPL_P_ID_2, 45, VR_CFG_ALL_DOMAINS_TDC_CURRENT(86, 86) },

From 3e0cfc6222c4d6543a3429e0e3dff22f537c3719 Mon Sep 17 00:00:00 2001
From: Jamie Ryu <jamie.m.ryu@intel.com>
Date: Thu, 27 Mar 2025 23:00:30 -0700
Subject: [PATCH 0729/3886] mb/intel/ptlrvp: Update flashmap to allocate 14MB
 to BIOS
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

This updates the Flashmap (FMAP) descriptor to allocate 18MB to
Silicon Management Engine (SI_ME) and 14MB for BIOS. Panther Lake
(PTL) Reference Validation Platform (RVP) coreboot is used with
several types of RVP boards, and this layout with a 14MB BIOS is
very convenient for debugging and creating coreboot for certain
use cases and testing purposes.

TEST=Build the ptlrvp variant (ES) and check if the flashmap of
the coreboot is updated correctly.

Change-Id: Ie85b79ae8f7d4e30cf48eb6301224b0cf01b8dff
Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87035
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
---
 src/mainboard/intel/ptlrvp/chromeos.fmd | 14 +++++---------
 1 file changed, 5 insertions(+), 9 deletions(-)

diff --git a/src/mainboard/intel/ptlrvp/chromeos.fmd b/src/mainboard/intel/ptlrvp/chromeos.fmd
index 693f485e4a..852fba0bab 100644
--- a/src/mainboard/intel/ptlrvp/chromeos.fmd
+++ b/src/mainboard/intel/ptlrvp/chromeos.fmd
@@ -1,20 +1,17 @@
 FLASH 32M {
-	SI_ALL 8M {
+	SI_ALL 18M {
 		SI_DESC 16K
 		SI_EC 576K
 		SI_ME
+		SI_ME_PAD@16M 2M
 	}
-	SI_BIOS 24M {
-		RW_SECTION_A 8M {
+	SI_BIOS 14M {
+		RW_SECTION_A 4M {
 			VBLOCK_A 8K
 			FW_MAIN_A(CBFS)
 			RW_FWID_A 64
 		}
-		# This section starts at the 16M boundary in SPI flash.
-		# PTL does not support a region crossing this boundary,
-		# because the SPI flash is memory-mapped into two non-
-		# contiguous windows.
-		RW_SECTION_B 8M {
+		RW_SECTION_B 4M {
 			VBLOCK_B 8K
 			FW_MAIN_B(CBFS)
 			RW_FWID_B 64
@@ -33,7 +30,6 @@ FLASH 32M {
 			RW_NVRAM(PRESERVE) 24K
 		}
 		RW_LEGACY(CBFS) 1M
-		RW_UNUSED 2M
 		# Make WP_RO region align with SPI vendor
 		# memory protected range specification.
 		WP_RO 4M {

From 8a132f3a512df2a46a91655edcc5ec2cb894b3ba Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Thu, 10 Apr 2025 11:58:54 +0100
Subject: [PATCH 0730/3886] mb/starlabs/starbook/tgl: Reconfigure PCH Strap
 GPIOs

Configure all strap GPIOs as outputs, rather than some being not
connected. This doesn't change anything, but is more explicit.

Set these all to sample on RSMRST.

Change-Id: I944744f103aa2d1c347856a059d3dd6231b219c4
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87258
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
---
 .../starlabs/starbook/variants/tgl/gpio.c     | 38 +++++++------------
 1 file changed, 14 insertions(+), 24 deletions(-)

diff --git a/src/mainboard/starlabs/starbook/variants/tgl/gpio.c b/src/mainboard/starlabs/starbook/variants/tgl/gpio.c
index 2794ea4c55..41565f913c 100644
--- a/src/mainboard/starlabs/starbook/variants/tgl/gpio.c
+++ b/src/mainboard/starlabs/starbook/variants/tgl/gpio.c
@@ -90,12 +90,24 @@ const struct pad_config gpio_table[] = {
 	PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1),				/* Clock */
 	PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1),				/* Data */
 
+	/* Config Straps 									[ Low      / High     ] */
+	PAD_CFG_GPO(GPP_B14, 0, RSMRST),				/* Top Swap		[ Disabled / Enabled  ] */
+	PAD_CFG_GPO(GPP_B18, 0, RSMRST),				/* Reboot Support	[ Enabled  / Disabled ] */
+	PAD_CFG_GPO(GPP_C2, 1, RSMRST),					/* TLS Confidentiality	[ Disabled / Enabled  ] */
+	PAD_CFG_GPO(GPP_B23, 0, DEEP),					/* XTAL			[ 38.4Mhz  / 19.2MHz  ] */
+	PAD_CFG_GPO(GPP_C5, 0, RSMRST),					/* eSPI			[ Enabled  / Disabled ] */
+	PAD_CFG_GPO(GPP_E6, 0, RSMRST),					/* JTAG ODT		[ Disabled / Enabled  ] */
+	PAD_CFG_GPO(GPP_E21, 0, RSMRST),				/* TBT LSX #1		[ 1.8V     / 3.3V     ] */
+	PAD_CFG_GPO(GPP_H0, 0, RSMRST),					/* BFX Strap 2 Bit 2	[ Disabled / Enabled  ] */
+	PAD_CFG_GPO(GPP_H1, 0, RSMRST),					/* BFX Strap 2 Bit 3	[ Disabled / Enabled  ] */
+	PAD_CFG_GPO(GPP_H2, 0, RSMRST),					/* BFX Strap 2 Bit 4	[ Disabled / Enabled  ] */
+	PAD_CFG_GPO(GPP_F7, 0, RSMRST),					/* MCRO LDO		[ Disabled / Bypass   ] */
+	PAD_CFG_GPO(GPD7, 0, RSMRST),					/* RTC Clock Delay	[ Disabled / 95ms     ] */
+
 	/* GPD2:	LAN_WAKE#		*/
 	PAD_NC(GPD2, NONE),
 	/* GPD6:	SIO_SLP_A#		*/
 	PAD_NC(GPD6, NONE),
-	/* GPD7:	PCH_TBT_PERST#		*/
-	PAD_CFG_GPO(GPD7, 0, PLTRST),
 	/* GPD9:	SIO_SLP_WLAN#		*/
 	PAD_NC(GPD9, NONE),
 	/* GPD10:	SIO_SLP_S5#		*/
@@ -144,16 +156,12 @@ const struct pad_config gpio_table[] = {
 	PAD_NC(GPP_B10, NONE),
 	/* B12:	PM_SLP_S0_N			*/
 	PAD_NC(GPP_B12, NONE),
-	/* B14:	FPS_RST_N			*/
-	PAD_CFG_GPO(GPP_B14, 1, PLTRST),
 	/* B15:	Not Connected			*/
 	PAD_NC(GPP_B15, NONE),
 	/* B16:	M2_PCH_SSD_PWREN		*/
 	PAD_NC(GPP_B16, NONE),
 	/* B17:	Not Connected			*/
 	PAD_NC(GPP_B17, NONE),
-	/* B18:	UF_CAM_STROBE			*/
-	PAD_CFG_GPO(GPP_B18, 0, DEEP),
 	/* B19:	GSPI1_CS0_FPS_N			*/
 	PAD_NC(GPP_B19, NONE),
 	/* B20:	GSPI1_CLK_FPS			*/
@@ -162,17 +170,11 @@ const struct pad_config gpio_table[] = {
 	PAD_NC(GPP_B21, NONE),
 	/* B22:	GSPI1_MOSI_FPS			*/
 	PAD_CFG_GPO(GPP_B22, 0, DEEP),
-	/* B23:	CPU_CLKFREQ			*/
-	PAD_CFG_GPO(GPP_B23, 0, DEEP),
 
-	/* C2:	SMBALERT_N			*/
-	PAD_CFG_GPO(GPP_C2, 0, DEEP),
 	/* C3:	SML0_CLK			*/
 	PAD_NC(GPP_C3, NONE),
 	/* C4:	SML0_DATA			*/
 	PAD_NC(GPP_C4, NONE),
-	/* C5:	SML0ALERT_IN			*/
-	PAD_CFG_GPO(GPP_C5, 0, DEEP),
 	/* C9:	Not Connected			*/
 	PAD_NC(GPP_C9, NONE),
 	/* C10:	Not Connected			*/
@@ -243,8 +245,6 @@ const struct pad_config gpio_table[] = {
 	PAD_NC(GPP_E4, NONE),
 	/* E5:	Not Connected			*/
 	PAD_NC(GPP_E5, NONE),
-	/* E6:	THC0_SPI1_RST_N_TCH_PNL		*/
-	PAD_NC(GPP_E6, NONE),
 	/* E7:	EC_SMI_LP_N			*/
 	PAD_NC(GPP_E7, NONE),
 	/* E8:	EC_SLP_S0IX_N			*/
@@ -267,8 +267,6 @@ const struct pad_config gpio_table[] = {
 	PAD_NC(GPP_E17, NONE),
 	/* E20:	Not Connected			*/
 	PAD_NC(GPP_E20, NONE),
-	/* E21:	TBT_LSX1_RXD			*/
-	PAD_NC(GPP_E21, NATIVE),
 	/* E22:	Not Connected			*/
 	PAD_NC(GPP_E22, NONE),
 	/* E23:	Not Connected			*/
@@ -280,8 +278,6 @@ const struct pad_config gpio_table[] = {
 	PAD_NC(GPP_F5, NONE),
 	/* F6:					*/
 	PAD_NC(GPP_F6, NONE),
-	/* F7:	BIOS_REC			*/
-	PAD_CFG_GPO(GPP_F7, 1, PLTRST),
 	/* F8:	Not Connected			*/
 	PAD_NC(GPP_F8, NONE),
 	/* F9:	Not Connected			*/
@@ -315,12 +311,6 @@ const struct pad_config gpio_table[] = {
 	/* F23:	Not Connected			*/
 	PAD_NC(GPP_F23, NONE),
 
-	/* H0:	GPPC_H0_M2_SSD_RST_N		*/
-	PAD_CFG_GPO(GPP_H0, 0, DEEP),
-	/* H1:	GPPC_H_1			*/
-	PAD_CFG_GPO(GPP_H1, 0, DEEP),
-	/* H2:	GPPC_H_2			*/
-	PAD_CFG_GPO(GPP_H2, 0, DEEP),
 	/* H3:	Not Connected			*/
 	PAD_NC(GPP_H3, NONE),
 	/* H4:	GSENSOR_I2C_SDA			*/

From be79c86f9e62069e47d63c27761eb700ae1bf4ee Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Thu, 10 Apr 2025 12:01:06 +0100
Subject: [PATCH 0731/3886] mb/starlabs/starbook/tgl: Move webcam GPIO to it's
 own group

Change-Id: I88fa42782e4f262f6595bb6394f21f65bb3c1b21
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87259
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
---
 src/mainboard/starlabs/starbook/variants/tgl/gpio.c | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/src/mainboard/starlabs/starbook/variants/tgl/gpio.c b/src/mainboard/starlabs/starbook/variants/tgl/gpio.c
index 41565f913c..2a28a6d87c 100644
--- a/src/mainboard/starlabs/starbook/variants/tgl/gpio.c
+++ b/src/mainboard/starlabs/starbook/variants/tgl/gpio.c
@@ -64,6 +64,9 @@ const struct pad_config gpio_table[] = {
 	PAD_CFG_NF(GPP_C6, NONE, PWROK, NF1),				/* SML Clock */
 	PAD_CFG_NF(GPP_C7, NONE, PWROK, NF1),				/* SML Data */
 
+	/* Webcam */
+	PAD_CFG_TERM_GPO(GPP_D19, 1, UP_20K, DEEP),			/* Power */
+
 	/* Retimer */
 	PAD_NC(GPP_E18, NATIVE),					/* TBT0 TXD */
 	PAD_NC(GPP_E19, NATIVE),					/* TBT0 RXD */
@@ -230,8 +233,6 @@ const struct pad_config gpio_table[] = {
 	PAD_NC(GPP_D17, NONE),
 	/* D18:	Not Connected			*/
 	PAD_NC(GPP_D18, NONE),
-	/* D19:	GPPC_D_19_WFCAM_PD_N		*/
-	PAD_CFG_TERM_GPO(GPP_D19, 1, UP_20K, DEEP),
 
 	/* E0:	SATAXPCIE_0_SATAGP_0		*/
 	PAD_NC(GPP_E0, NONE),

From 75bbdaac3928b103559ee45df15b8aa488e7acae Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Thu, 10 Apr 2025 12:02:49 +0100
Subject: [PATCH 0732/3886] mb/starlabs/starbook/tgl: Disconnect unused GPIOs

Configure pads that aren't connected to anything to PAD_NC.

Also, remove comments for these pads.

Change-Id: Iaee9f3fc5639d5147f5bdf45fb5311a0121e2c78
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87260
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 .../starlabs/starbook/variants/tgl/gpio.c     | 136 +-----------------
 1 file changed, 2 insertions(+), 134 deletions(-)

diff --git a/src/mainboard/starlabs/starbook/variants/tgl/gpio.c b/src/mainboard/starlabs/starbook/variants/tgl/gpio.c
index 2a28a6d87c..2fec5297b7 100644
--- a/src/mainboard/starlabs/starbook/variants/tgl/gpio.c
+++ b/src/mainboard/starlabs/starbook/variants/tgl/gpio.c
@@ -107,280 +107,148 @@ const struct pad_config gpio_table[] = {
 	PAD_CFG_GPO(GPP_F7, 0, RSMRST),					/* MCRO LDO		[ Disabled / Bypass   ] */
 	PAD_CFG_GPO(GPD7, 0, RSMRST),					/* RTC Clock Delay	[ Disabled / 95ms     ] */
 
-	/* GPD2:	LAN_WAKE#		*/
 	PAD_NC(GPD2, NONE),
-	/* GPD6:	SIO_SLP_A#		*/
 	PAD_NC(GPD6, NONE),
-	/* GPD9:	SIO_SLP_WLAN#		*/
 	PAD_NC(GPD9, NONE),
-	/* GPD10:	SIO_SLP_S5#		*/
 	PAD_NC(GPD10, NONE),
-	/* GPD11:	PM_LANPHY_EN		*/
 	PAD_NC(GPD11, NONE),
 
-	/* A7:	WLAN_PCM_CLK			*/
 	PAD_NC(GPP_A7, NONE),
-	/* A10:	WLAN_PCM_IN			*/
 	PAD_NC(GPP_A10, NONE),
-	/* A13:	Not Connected			*/
 	PAD_NC(GPP_A13, NONE),
-	/* A14:	Not Connected			*/
 	PAD_NC(GPP_A14, NONE),
-	/* A15	Not Connected			*/
 	PAD_NC(GPP_A15, NONE),
-	/* A16:	USB2_OCB_3			*/
 	PAD_NC(GPP_A16, NONE),
-	/* A17:	Not Connected			*/
 	PAD_NC(GPP_A17, NONE),
-	/* A19	Not Connected			*/
 	PAD_NC(GPP_A19, NONE),
-	/* A20:	Not Connected			*/
 	PAD_NC(GPP_A20, NONE),
-	/* A21	Not Connected			*/
 	PAD_NC(GPP_A21, NONE),
-	/* A22:	Not Connected			*/
 	PAD_NC(GPP_A22, NONE),
 
-	/* B3:	Not Connected			*/
 	PAD_NC(GPP_B3, NONE),
-	/* B4:	Not Connected			*/
 	PAD_NC(GPP_B4, NONE),
-	/* B5:	Not Connected			*/
 	PAD_NC(GPP_B5, NONE),
-	/* B6:	Not Connected			*/
 	PAD_NC(GPP_B6, NONE),
-	/* B7:	Not Connected			*/
 	PAD_NC(GPP_B7, NONE),
-	/* B8:	Not Connected			*/
 	PAD_NC(GPP_B8, NONE),
-	/* B9:	PWR_MON_I2C_SDA_R		*/
 	PAD_NC(GPP_B9, NONE),
-	/* B10:	PWR_MON_I2C_SCL_R		*/
 	PAD_NC(GPP_B10, NONE),
-	/* B12:	PM_SLP_S0_N			*/
 	PAD_NC(GPP_B12, NONE),
-	/* B15:	Not Connected			*/
 	PAD_NC(GPP_B15, NONE),
-	/* B16:	M2_PCH_SSD_PWREN		*/
 	PAD_NC(GPP_B16, NONE),
-	/* B17:	Not Connected			*/
 	PAD_NC(GPP_B17, NONE),
-	/* B19:	GSPI1_CS0_FPS_N			*/
 	PAD_NC(GPP_B19, NONE),
-	/* B20:	GSPI1_CLK_FPS			*/
 	PAD_NC(GPP_B20, NONE),
-	/* B21:	GSPI1_MISO_FPS			*/
 	PAD_NC(GPP_B21, NONE),
-	/* B22:	GSPI1_MOSI_FPS			*/
-	PAD_CFG_GPO(GPP_B22, 0, DEEP),
+	PAD_NC(GPP_B22, NONE),
 
-	/* C3:	SML0_CLK			*/
 	PAD_NC(GPP_C3, NONE),
-	/* C4:	SML0_DATA			*/
 	PAD_NC(GPP_C4, NONE),
-	/* C9:	Not Connected			*/
 	PAD_NC(GPP_C9, NONE),
-	/* C10:	Not Connected			*/
 	PAD_NC(GPP_C10, NONE),
-	/* C11:	Not Connected			*/
 	PAD_NC(GPP_C11, NONE),
-	/* C12:	Not Connected			*/
 	PAD_NC(GPP_C12, NONE),
-	/* C13:	Not Connected			*/
 	PAD_NC(GPP_C13, NONE),
-	/* C15:	TPM_RST				*/
 	PAD_NC(GPP_C15, NONE),
-	/* C18:	TOUCH_I2C_SDA			*/
 	PAD_NC(GPP_C18, NONE),
-	/* C19:	TOUCH_I2C_CLK			*/
 	PAD_NC(GPP_C19, NONE),
-	/* C22:	Not Connected			*/
 	PAD_NC(GPP_C22, NONE),
-	/* C23:	WLAN_WAKE_N			*/
 	PAD_NC(GPP_C23, NONE),
 
-	/* D0:	ACCEL1_INT			*/
 	PAD_NC(GPP_D0, NONE),
-	/* D1:	ACCEL2_INT			*/
 	PAD_NC(GPP_D1, NONE),
-	/* D2:	Not Connected			*/
 	PAD_NC(GPP_D2, NONE),
-	/* D3:	Not Connected			*/
 	PAD_NC(GPP_D3, NONE),
-	/* D4:	Not Connected			*/
 	PAD_NC(GPP_D4, NONE),
-	/* D5:	CLKREQ0_M2_SSD_N		*/
 	PAD_NC(GPP_D5, NONE),
-	/* D6:	CLKREQ1_WLAN_N			*/
 	PAD_NC(GPP_D6, NONE),
-	/* D7:	LAN_CLKREQ#			*/
 	PAD_NC(GPP_D7, NONE),
-	/* D9:	Not Connected			*/
 	PAD_NC(GPP_D9, NONE),
-	/* D10:	Not Connected			*/
 	PAD_NC(GPP_D10, NONE),
-	/* D11:	Not Connected			*/
 	PAD_NC(GPP_D11, NONE),
-	/* D12:	Not Connected			*/
 	PAD_NC(GPP_D12, NONE),
-	/* D13:	Not Connected			*/
 	PAD_NC(GPP_D13, NONE),
-	/* D14:	Not Connected			*/
 	PAD_NC(GPP_D14, NONE),
-	/* D15:	Not Connected			*/
 	PAD_NC(GPP_D15, NONE),
-	/* D17:	Not Connected			*/
 	PAD_NC(GPP_D17, NONE),
-	/* D18:	Not Connected			*/
 	PAD_NC(GPP_D18, NONE),
 
-	/* E0:	SATAXPCIE_0_SATAGP_0		*/
 	PAD_NC(GPP_E0, NONE),
-	/* E1:	Not Connected			*/
 	PAD_NC(GPP_E1, NONE),
-	/* E2:	Not Connected			*/
 	PAD_NC(GPP_E2, NONE),
-	/* E3:	FPS_INT				*/
 	PAD_NC(GPP_E3, NONE),
-	/* E4:	Not Connected			*/
 	PAD_NC(GPP_E4, NONE),
-	/* E5:	Not Connected			*/
 	PAD_NC(GPP_E5, NONE),
-	/* E7:	EC_SMI_LP_N			*/
 	PAD_NC(GPP_E7, NONE),
-	/* E8:	EC_SLP_S0IX_N			*/
 	PAD_NC(GPP_E8, NONE),
-	/* E9:	USB2_TCP01_OC_N			*/
 	PAD_NC(GPP_E9, NONE),
-	/* E10:	SPI1_TCH_PNL_CS_N		*/
 	PAD_NC(GPP_E10, NONE),
-	/* E11:	SPI1_CLK			*/
 	PAD_NC(GPP_E11, NONE),
-	/* E12:	Not Connected			*/
 	PAD_NC(GPP_E12, NONE),
-	/* E13:	Not Connected			*/
 	PAD_NC(GPP_E13, NONE),
-	/* E15:	Not Connected			*/
 	PAD_NC(GPP_E15, NONE),
-	/* E16:	Not Connected			*/
 	PAD_NC(GPP_E16, NONE),
-	/* E17:	Not Connected			*/
 	PAD_NC(GPP_E17, NONE),
-	/* E20:	Not Connected			*/
 	PAD_NC(GPP_E20, NONE),
-	/* E22:	Not Connected			*/
 	PAD_NC(GPP_E22, NONE),
-	/* E23:	Not Connected			*/
 	PAD_NC(GPP_E23, NONE),
 
-	/* F4:	Not Connected			*/
 	PAD_NC(GPP_F4, NONE),
-	/* F5:	GPPC_F5_MODEM_CLKREQ		*/
 	PAD_NC(GPP_F5, NONE),
-	/* F6:					*/
 	PAD_NC(GPP_F6, NONE),
-	/* F8:	Not Connected			*/
 	PAD_NC(GPP_F8, NONE),
-	/* F9:	Not Connected			*/
 	PAD_NC(GPP_F9, NONE),
-	/* F10:	GPPC_F_10			*/
-	PAD_CFG_GPO(GPP_F10, 0, DEEP),
-	/* F11:	Not Connected			*/
+	PAD_NC(GPP_F10, NONE),
 	PAD_NC(GPP_F11, NONE),
-	/* F12:	Not Connected			*/
 	PAD_NC(GPP_F12, NONE),
-	/* F13:	Not Connected			*/
 	PAD_NC(GPP_F13, NONE),
-	/* F14:	Not Connected			*/
 	PAD_NC(GPP_F14, NONE),
-	/* F15:	Not Connected			*/
 	PAD_NC(GPP_F15, NONE),
-	/* F16:	Not Connected			*/
 	PAD_NC(GPP_F16, NONE),
-	/* F17:	TOUCH_PANEL_RESET_N		*/
 	PAD_NC(GPP_F17, NONE),
-	/* F18:	TOUCH_PANEL_INT_N		*/
 	PAD_NC(GPP_F18, NONE),
-	/* F19:	Not Connected			*/
 	PAD_NC(GPP_F19, NONE),
-	/* F20:	Not Connected			*/
 	PAD_NC(GPP_F20, NONE),
-	/* F21:	Not Connected			*/
 	PAD_NC(GPP_F21, NONE),
-	/* F22:	Not Connected			*/
 	PAD_NC(GPP_F22, NONE),
-	/* F23:	Not Connected			*/
 	PAD_NC(GPP_F23, NONE),
 
-	/* H3:	Not Connected			*/
 	PAD_NC(GPP_H3, NONE),
-	/* H4:	GSENSOR_I2C_SDA			*/
 	PAD_NC(GPP_H4, NONE),
-	/* H5:	GSENSOR_I2C_SCL			*/
 	PAD_NC(GPP_H5, NONE),
-	/* H6:	Not Connected			*/
 	PAD_NC(GPP_H6, NONE),
-	/* H7:	Not Connected			*/
 	PAD_NC(GPP_H7, NONE),
-	/* H8:	Not Connected			*/
 	PAD_NC(GPP_H8, NONE),
-	/* H9:	Not Connected			*/
 	PAD_NC(GPP_H9, NONE),
-	/* H10:	Not Connected			*/
 	PAD_NC(GPP_H10, NONE),
-	/* H11:	Not Connected			*/
 	PAD_NC(GPP_H11, NONE),
-	/* H12:	Not Connected			*/
 	PAD_NC(GPP_H12, NONE),
-	/* H13:	Not Connected			*/
 	PAD_NC(GPP_H13, NONE),
-	/* H14:	Not Connected			*/
 	PAD_NC(GPP_H14, NONE),
-	/* H15:	Not Connected			*/
 	PAD_NC(GPP_H15, NONE),
-	/* H19:	UART_BT_WAKE_N			*/
 	PAD_NC(GPP_H19, NONE),
-	/* H20:	Not Connected			*/
 	PAD_NC(GPP_H20, NONE),
-	/* H21:	Not Connected			*/
 	PAD_NC(GPP_H21, NONE),
-	/* H22:	Not Connected			*/
 	PAD_NC(GPP_H22, NONE),
-	/* H23:	Not Connected			*/
 	PAD_NC(GPP_H23, NONE),
 
-	/* R5:	Not Connected			*/
 	PAD_NC(GPP_R5, NONE),
-	/* R6:	Not Connected			*/
 	PAD_NC(GPP_R6, NONE),
-	/* R7:	Not Connected			*/
 	PAD_NC(GPP_R7, NONE),
 
-	/* S0:	Not Connected			*/
 	PAD_NC(GPP_S0, NONE),
-	/* S1:	Not Connected			*/
 	PAD_NC(GPP_S1, NONE),
-	/* S2:	Not Connected			*/
 	PAD_NC(GPP_S2, NONE),
-	/* S3:	Not Connected			*/
 	PAD_NC(GPP_S3, NONE),
-	/* S4:	Not Connected			*/
 	PAD_NC(GPP_S4, NONE),
-	/* S5:	Not Connected			*/
 	PAD_NC(GPP_S5, NONE),
-	/* S6:	Not Connected			*/
 	PAD_NC(GPP_S6, NONE),
-	/* S7:	Not Connected			*/
 	PAD_NC(GPP_S7, NONE),
 
-	/* T2:	Not Connected			*/
 	PAD_NC(GPP_T2, NONE),
-	/* T3:	Not Connected			*/
 	PAD_NC(GPP_T3, NONE),
 
-	/* U4:	Not Connected			*/
 	PAD_NC(GPP_U4, NONE),
-	/* U5:	Not Connected			*/
 	PAD_NC(GPP_U5, NONE),
 };
 

From b46c6ec181c57f862f63142cb9ae3b9db3120c60 Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Thu, 10 Apr 2025 12:03:51 +0100
Subject: [PATCH 0733/3886] mb/starlabs/starbook/tgl: Correct GPIO configs

Several pads were not configured or configured incorrectly. FSP was
correcting them, but adjust the config in coreboot so this is not
necassary.

The config aligns with all other Star Labs boards.

Change-Id: Id41ea5d2f4f4321526d25b27411dad02fbde90b6
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87261
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/starlabs/starbook/variants/tgl/gpio.c | 12 ++++++------
 1 file changed, 6 insertions(+), 6 deletions(-)

diff --git a/src/mainboard/starlabs/starbook/variants/tgl/gpio.c b/src/mainboard/starlabs/starbook/variants/tgl/gpio.c
index 2fec5297b7..0aa6cbe7b4 100644
--- a/src/mainboard/starlabs/starbook/variants/tgl/gpio.c
+++ b/src/mainboard/starlabs/starbook/variants/tgl/gpio.c
@@ -37,10 +37,10 @@ const struct pad_config gpio_table[] = {
 	/* Touchpad */
 	PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1),				/* Data */
 	PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1),				/* Clock */
-	PAD_CFG_GPI_APIC_LOW(GPP_C8, NONE, PLTRST),			/* Interrupt */
+	PAD_CFG_GPI_APIC(GPP_C8, NONE, DEEP, LEVEL, INVERT),		/* Interrupt */
 
 	/* SSD */
-	PAD_NC(GPP_D8, NONE),						/* Clock Request 3 */
+	PAD_CFG_NF(GPP_D8, NONE, DEEP, NF1),				/* Clock Request 3 */
 	PAD_CFG_GPO(GPP_A11, 1, PLTRST),				/* Reset */
 	PAD_CFG_GPO(GPP_D16, 1, PLTRST),				/* Enable */
 
@@ -68,8 +68,8 @@ const struct pad_config gpio_table[] = {
 	PAD_CFG_TERM_GPO(GPP_D19, 1, UP_20K, DEEP),			/* Power */
 
 	/* Retimer */
-	PAD_NC(GPP_E18, NATIVE),					/* TBT0 TXD */
-	PAD_NC(GPP_E19, NATIVE),					/* TBT0 RXD */
+	PAD_CFG_NF(GPP_E18, NONE, DEEP, NF2),				/* TBT0 TXD */
+	PAD_CFG_NF(GPP_E19, NONE, DEEP, NF2),				/* TBT0 RXD */
 	PAD_CFG_GPO(GPP_A23, 0, DEEP),					/* Force Power */
 
 	/* High-Definition Audio */
@@ -77,14 +77,14 @@ const struct pad_config gpio_table[] = {
 	PAD_CFG_NF(GPP_R1, NATIVE, DEEP, NF1),				/* Sync */
 	PAD_CFG_NF(GPP_R2, NATIVE, DEEP, NF1),				/* Data Output */
 	PAD_CFG_NF(GPP_R3, NATIVE, DEEP, NF1),				/* Data Input */
-	PAD_NC(GPP_R4, NONE),						/* Reset */
+	PAD_CFG_NF(GPP_R4, NATIVE, DEEP, NF1),				/* Reset */
 
 	/* PCH */
 	PAD_CFG_NF(GPP_H18, NONE, DEEP, NF1),				/* C10 Gate */
 	PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1),				/* Platform Reset */
 	PAD_CFG_NF(GPP_B0, NONE, DEEP, NF1),				/* Vendor ID 0 */
 	PAD_CFG_NF(GPP_B1, NONE, DEEP, NF1),				/* Vendor ID 1 */
-	PAD_NC(GPP_B2, NONE),						/* Processor Hot */
+	PAD_CFG_GPI_SCI(GPP_B2, NONE, PLTRST, EDGE_SINGLE, INVERT),	/* Processor Hot */
 
 	/* TPM */
 	PAD_CFG_GPI_APIC_LOW(GPP_C14, NONE, PLTRST),			/* Interrupt */

From 2f28ec300e81f23e5300ca9316a0c390037e3a29 Mon Sep 17 00:00:00 2001
From: Harrie Paijmans <hpaijmans@eltan.com>
Date: Wed, 9 Apr 2025 15:18:45 +0200
Subject: [PATCH 0734/3886] device/pci_ids: Add Raptor Lake P root port ID
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Add Raptor Lake P specific PCIe root port ID.
Based on intel document 640552 rev 2.81.

BUG=NA
TEST=Customer platform with Raptorlake-P

Change-Id: Ifa7c131b5ae47294c055b9e68dad2764607c032b
Signed-off-by: Harrie Paijmans <hpaijmans@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87244
Reviewed-by: Erik van den Bogaert <ebogaert@eltan.com>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
---
 src/include/device/pci_ids.h           | 1 +
 src/soc/intel/common/block/pcie/pcie.c | 1 +
 2 files changed, 2 insertions(+)

diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h
index 6a45fbb4a8..fdcddb2ffe 100644
--- a/src/include/device/pci_ids.h
+++ b/src/include/device/pci_ids.h
@@ -3607,6 +3607,7 @@
 #define PCI_DID_INTEL_RPL_P_PCIE_RP1			0xa74d
 #define PCI_DID_INTEL_RPL_P_PCIE_RP2			0xa70d
 #define PCI_DID_INTEL_RPL_P_PCIE_RP3			0xa72d
+#define PCI_DID_INTEL_RPL_P_PCIE_RP4			0xa73d
 
 #define PCI_DID_INTEL_LNL_PCIE_RP1			0xa838
 #define PCI_DID_INTEL_LNL_PCIE_RP2			0xa839
diff --git a/src/soc/intel/common/block/pcie/pcie.c b/src/soc/intel/common/block/pcie/pcie.c
index ddea3b667b..6a1225d62b 100644
--- a/src/soc/intel/common/block/pcie/pcie.c
+++ b/src/soc/intel/common/block/pcie/pcie.c
@@ -100,6 +100,7 @@ static const unsigned short pcie_device_ids[] = {
 	PCI_DID_INTEL_RPL_P_PCIE_RP1,
 	PCI_DID_INTEL_RPL_P_PCIE_RP2,
 	PCI_DID_INTEL_RPL_P_PCIE_RP3,
+	PCI_DID_INTEL_RPL_P_PCIE_RP4,
 	PCI_DID_INTEL_MTL_SOC_PCIE_RP1,
 	PCI_DID_INTEL_MTL_SOC_PCIE_RP2,
 	PCI_DID_INTEL_MTL_SOC_PCIE_RP3,

From d696fa69877ce3b2f63ee7ee85a94d872e8ae144 Mon Sep 17 00:00:00 2001
From: Maximilian Brune <maximilian.brune@9elements.com>
Date: Tue, 1 Apr 2025 16:28:03 +0200
Subject: [PATCH 0735/3886] Revert "acpi,Makefile: Add preload_acpi_dsdt"

This reverts commit 6b446b991b00c44902b70d86c75b23a8f93d510b.

Reason for revert: This effort was apparently given up on since 4 years.
So remove the function, since it is not used at the moment. If someone
wants to bring that effort back to live, said person can feel free to do
so.

Change-Id: Ifa1ca58c8bf6aabb5b291d3244b1a1a0a7aec6c7
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87065
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 Makefile.mk             |  3 ---
 src/acpi/acpi.c         | 11 -----------
 src/include/acpi/acpi.h |  1 -
 3 files changed, 15 deletions(-)

diff --git a/Makefile.mk b/Makefile.mk
index 576cebd904..3969bfbd05 100644
--- a/Makefile.mk
+++ b/Makefile.mk
@@ -306,9 +306,6 @@ define asl_template
 $(CONFIG_CBFS_PREFIX)/$(1).aml-file = $(obj)/$(1).aml
 $(CONFIG_CBFS_PREFIX)/$(1).aml-type = raw
 $(CONFIG_CBFS_PREFIX)/$(1).aml-compression = none
-ifeq ($(CONFIG_SOC_AMD_COMMON_BLOCK_LPC_SPI_DMA),y)
-$(CONFIG_CBFS_PREFIX)/$(1).aml-align = 64
-endif
 cbfs-files-$(if $(2),$(2),y) += $(CONFIG_CBFS_PREFIX)/$(1).aml
 $(eval DEPENDENCIES += $(obj)/$(1).d)
 $(obj)/$(1).aml: $(src)/mainboard/$(MAINBOARDDIR)/$(1).asl $(obj)/config.h
diff --git a/src/acpi/acpi.c b/src/acpi/acpi.c
index 06879540bf..6c463c93d4 100644
--- a/src/acpi/acpi.c
+++ b/src/acpi/acpi.c
@@ -1349,17 +1349,6 @@ unsigned long __weak fw_cfg_acpi_tables(unsigned long start)
 	return 0;
 }
 
-void preload_acpi_dsdt(void)
-{
-	const char *file = CONFIG_CBFS_PREFIX "/dsdt.aml";
-
-	if (!CONFIG(CBFS_PRELOAD))
-		return;
-
-	printk(BIOS_DEBUG, "Preloading %s\n", file);
-	cbfs_preload(file);
-}
-
 static void acpi_create_dsdt(acpi_header_t *header, void *dsdt_file_arg)
 {
 	dsdt = header;
diff --git a/src/include/acpi/acpi.h b/src/include/acpi/acpi.h
index 604c60dad0..3b0aa626e2 100644
--- a/src/include/acpi/acpi.h
+++ b/src/include/acpi/acpi.h
@@ -1739,7 +1739,6 @@ void acpi_create_einj(acpi_einj_t *einj, uintptr_t addr, u8 actions);
 unsigned long fw_cfg_acpi_tables(unsigned long start);
 
 /* These are implemented by the target port or north/southbridge. */
-void preload_acpi_dsdt(void);
 unsigned long write_acpi_tables(const unsigned long addr);
 unsigned long acpi_fill_madt(unsigned long current);
 unsigned long acpi_arch_fill_madt(acpi_madt_t *madt, unsigned long current);

From aec4a9b2e5aa8e7d6bd5da78ced4cbf2dc58752f Mon Sep 17 00:00:00 2001
From: Maximilian Brune <maximilian.brune@9elements.com>
Date: Tue, 1 Apr 2025 16:52:37 +0200
Subject: [PATCH 0736/3886] Revert "src/cpu,soc/amd/common/block/cpu: Add
 preload_microcode"

This reverts commit 4b5a490b6f3faffe1880c731b50d1a4adabfb622.

Reason for revert: This effort was apparently given up on since 4 years.
So remove the function, since it is not used at the moment. If someone
wants to bring that effort back to live, said person can feel free to do
so.

Change-Id: I26d5c9fbfd6eae24f876d857a6e952ca0d1a64ae
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87066
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
---
 src/cpu/Makefile.mk                             |  5 -----
 src/include/cpu/amd/microcode.h                 |  1 -
 src/soc/amd/common/block/cpu/update_microcode.c | 13 -------------
 3 files changed, 19 deletions(-)

diff --git a/src/cpu/Makefile.mk b/src/cpu/Makefile.mk
index 0afe454c1e..2ab8727562 100644
--- a/src/cpu/Makefile.mk
+++ b/src/cpu/Makefile.mk
@@ -59,12 +59,7 @@ $(obj)/cpu_microcode_blob.bin: $$(wildcard $$(cpu_microcode_bins)) $(DOTCONFIG)
 
 cpu_microcode_blob.bin-file ?= $(obj)/cpu_microcode_blob.bin
 cpu_microcode_blob.bin-type := microcode
-# The AMD LPC SPI DMA controller requires source files to be 64 byte aligned.
-ifeq ($(CONFIG_SOC_AMD_COMMON_BLOCK_LPC_SPI_DMA),y)
-cpu_microcode_blob.bin-align := 64
-else
 cpu_microcode_blob.bin-align := 16
-endif
 
 ifneq ($(CONFIG_CPU_MICROCODE_CBFS_LOC),)
 cpu_microcode_blob.bin-COREBOOT-position := $(CONFIG_CPU_MICROCODE_CBFS_LOC)
diff --git a/src/include/cpu/amd/microcode.h b/src/include/cpu/amd/microcode.h
index b6b158c99a..96cac59db9 100644
--- a/src/include/cpu/amd/microcode.h
+++ b/src/include/cpu/amd/microcode.h
@@ -7,6 +7,5 @@ void amd_update_microcode_from_cbfs(void);
 void amd_load_microcode_from_cbfs(void);
 void amd_free_microcode(void);
 void amd_apply_microcode_patch(void);
-void preload_microcode(void);
 
 #endif /* CPU_AMD_MICROCODE_H */
diff --git a/src/soc/amd/common/block/cpu/update_microcode.c b/src/soc/amd/common/block/cpu/update_microcode.c
index 14c4f36b98..e80339bd5f 100644
--- a/src/soc/amd/common/block/cpu/update_microcode.c
+++ b/src/soc/amd/common/block/cpu/update_microcode.c
@@ -119,16 +119,3 @@ void amd_free_microcode(void)
 		ucode = NULL;
 	}
 }
-
-void preload_microcode(void)
-{
-	if (!CONFIG(CBFS_PRELOAD))
-		return;
-
-	char name[] = CPU_MICROCODE_BLOB_NAME;
-	uint16_t equivalent_processor_rev_id = get_equivalent_processor_rev_id();
-
-	snprintf(name, sizeof(name), CPU_MICROCODE_BLOB_FORMAT, equivalent_processor_rev_id);
-	printk(BIOS_DEBUG, "Preloading microcode %s\n", name);
-	cbfs_preload(name);
-}

From 4186587fe052b98b43ee12182ca3b5ce10c3264f Mon Sep 17 00:00:00 2001
From: Nicholas Chin <nic.c3.14@gmail.com>
Date: Mon, 24 Jun 2024 21:51:48 -0600
Subject: [PATCH 0737/3886] docs/getting-started: Update guide for writing docs

- Update the instructions for building the documentation to account for
  the switch from Recommonmark to MyST Parser
- Update outdated URLs
- Update various details to account for the current behavior and
  features resulting from previous changes

Change-Id: I569862e30fb88a421ad2338aafabeaf3ea76836a
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85857
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
---
 .../getting_started/writing_documentation.md  | 72 +++++++++----------
 1 file changed, 32 insertions(+), 40 deletions(-)

diff --git a/Documentation/getting_started/writing_documentation.md b/Documentation/getting_started/writing_documentation.md
index 6b1cf3ceb5..a24af0840e 100644
--- a/Documentation/getting_started/writing_documentation.md
+++ b/Documentation/getting_started/writing_documentation.md
@@ -14,18 +14,13 @@ coreboot uses [Sphinx] documentation tool. We prefer the markdown format
 over reStructuredText so only embedded ReST is supported. Checkout the
 [Markdown Guide] for more information.
 
-### option 1: Use the docker image
+### Option 1: Use the docker image
 
 The easiest way to build the documentation is using a docker image.
 To build the image run the following in the base directory:
 
 	make -C util/docker/ doc.coreboot.org
 
-Before building the documentation make sure the output directory is given
-the correct permissions before running docker.
-
-	mkdir -p Documentation/_build
-
 To build the documentation:
 
 	make -C util/docker docker-build-docs
@@ -36,30 +31,29 @@ To have the documentation build and served over a web server live run:
 
 On the host machine, open a browser to the address <http://0.0.0.0:8000>.
 
-### option 2: Install Sphinx
+### Option 2: Install Sphinx
 
-Please follow this official [guide] to install sphinx.
-You will also need python-recommonmark for sphinx to be able to handle
-markdown documentation.
+Please follow this official [guide] to install sphinx. You will also need
+myst-parser for sphinx to be able to handle markdown documentation.
 
 Since some Linux distributions don't package every needed sphinx extension,
 the installation via pip in a venv is recommended. You'll need these python3
 modules:
 
 * sphinx
-* recommonmark
-* sphinx_rtd_theme
+* myst-parser
+* sphinx-rtd-theme
 
-The following combination of versions has been tested: sphinx 2.3.1,
-recommonmark 0.6.0, and sphinx_rtd_theme 0.4.3.
+The following combination of versions has been tested: sphinx 8.1.3,
+myst-parser 4.0.0, and sphinx-rtd-theme 2.0.0.
 
 Now change into the `Documentation` folder in the coreboot directory and run
 this command in there
 
-	make sphinx
+	make
 
 If no error occurs, you can find the generated HTML documentation in
-`Documentation/_build` now.
+`Documentation/_build/html` now.
 
 ### Optional
 
@@ -88,15 +82,17 @@ Documentation:
 12.  Shouldn't cover implementation details; for details, the code is the
      reference.
 
-## Referencing markdown documents
-
-Starting with Sphinx 1.6 recommonmark's *auto_doc_ref* feature is broken.
-To reference documents use the TOC tree or inline RST code.
-
 ## Markdown and Tables
 
-Under Sphinx markdown tables are not supported. Therefore you can use following
-code block to write tables in reStructuredText and embed them into the markdown:
+Markdown tables are supported:
+
+    | Header 1   | Header 2  | Header 3  |
+    |------------|-----------|-----------|
+    | body row 1 | column 2  | column 3  |
+    | body row 2 | column 2  | column 3  |
+
+Tables can also be written using embedded reStructured Text, which provides
+additional features like the ability to merge cells:
 
     ```{eval-rst}
     +------------+------------+-----------+
@@ -117,22 +113,20 @@ code block to write tables in reStructuredText and embed them into the markdown:
 To make sure that all documents are included into the final documentation, you
 must reference each document from at least one *toctree*. The *toctree* must
 only reference files in the same folder or in subfolders !
-To create a toctree, simply use a bullet list or numbered list with a single
-reference. References in regular text aren't considered as *toctree* .
-This feature is enabled by recommonmark's *enable_auto_toc_tree* .
+To create a toctree, you must use the following syntax to invoke the
+Sphinx toctree directive:
 
 **Example toctree:**
 
-```
-* [Chapter 1](chapter1.md)
-* [Chapter 2](chapter2.md)
-* [Subchapter](sub/index.md)
-```
+    ```{toctree}
+    :maxdepth: 1
 
-```
-1. [Chapter 1](chapter1.md)
-2. [Chapter 2](chapter2.md)
-```
+    Chapter 1 <chapter1.md>
+    Chapter 2 <chapter2.md>
+    Subchapter <sub/index.md>
+    ```
+
+References in regular text aren't considered as *toctree* .
 
 If you do only reference the document, but do not include it in any toctree,
 you'll see the following warning:
@@ -152,11 +146,9 @@ readable tables, using the following reStructuredText snipped:
 Of course this can only be done from a markdown file that is included in the
 TOC tree.
 
-[coreboot]: https://coreboot.org
-[Documentation]: https://review.coreboot.org/cgit/coreboot.git/tree/Documentation
-[sphinx-autobuild]: https://github.com/GaretJax/sphinx-autobuild
-[guide]: http://www.sphinx-doc.org/en/stable/install.html
-[Sphinx]: http://www.sphinx-doc.org/en/master/
+[sphinx-autobuild]: https://github.com/sphinx-doc/sphinx-autobuild
+[guide]: https://www.sphinx-doc.org/en/master/usage/installation.html
+[Sphinx]: https://www.sphinx-doc.org/en/master/
 [Markdown Guide]: https://www.markdownguide.org/
 [Gerrit Guidelines]: ../contributing/gerrit_guidelines.md
 [review.coreboot.org]: https://review.coreboot.org

From c4a46b7340d0014e2e69dfaa3af55a81fa13877f Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Micha=C5=82=20=C5=BBygowski?= <michal.zygowski@3mdeb.com>
Date: Mon, 31 Mar 2025 15:39:31 +0200
Subject: [PATCH 0738/3886] soc/intel/elkhartlake/pmc,gpio: Fix PMC GPE GPIO
 routes
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Based on the description of PMC GPIO_CONF register from
EHL EDS Vol 2 Book 2 rev 2.3 #614109.

Some of the groups had incorrect values or even defined
non-existent GPIO groups.

TEST=Boot Protectli VP2420 to Ubuntu 24.04.

Change-Id: I910f3c4c0d31b8d24b83cd2c3a28688b898b5d9f
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87050
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
---
 src/soc/intel/elkhartlake/gpio.c                      |  1 -
 src/soc/intel/elkhartlake/include/soc/gpio_soc_defs.h | 11 +++++------
 src/soc/intel/elkhartlake/include/soc/pmc.h           | 11 +++++------
 3 files changed, 10 insertions(+), 13 deletions(-)

diff --git a/src/soc/intel/elkhartlake/gpio.c b/src/soc/intel/elkhartlake/gpio.c
index 1b07bc5d27..795763ed00 100644
--- a/src/soc/intel/elkhartlake/gpio.c
+++ b/src/soc/intel/elkhartlake/gpio.c
@@ -226,7 +226,6 @@ const struct pmc_to_gpio_route *soc_pmc_gpio_routes(size_t *num)
 		{ PMC_GPP_C, GPP_C },
 		{ PMC_GPP_E, GPP_E },
 		{ PMC_GPP_G, GPP_G },
-		{ PMC_GPP_S, GPP_S }
 	};
 
 	*num = ARRAY_SIZE(routes);
diff --git a/src/soc/intel/elkhartlake/include/soc/gpio_soc_defs.h b/src/soc/intel/elkhartlake/include/soc/gpio_soc_defs.h
index 33fcb6bfb7..0aefe96520 100644
--- a/src/soc/intel/elkhartlake/include/soc/gpio_soc_defs.h
+++ b/src/soc/intel/elkhartlake/include/soc/gpio_soc_defs.h
@@ -10,19 +10,18 @@
  */
 #define GPP_B			0x0
 #define GPP_T			0x1
-#define GPP_D			0x2
-#define GPP_A			0x3
-#define GPP_R			0x4
+#define GPP_A			0x2
+#define GPP_R			0x3
+#define GPD			0x4
 #define GPP_V			0x5
-#define GPD			0x6
-#define GPP_H			0x7
+#define GPP_H			0x6
+#define GPP_D			0x7
 #define GPP_U			0x8
 #define VGPIO			0x9
 #define GPP_F			0xA
 #define GPP_C			0xB
 #define GPP_E			0xC
 #define GPP_G			0xD
-#define GPP_S			0xE
 
 #define GPIO_NUM_GROUPS		15
 #define GPIO_MAX_NUM_PER_GROUP	32
diff --git a/src/soc/intel/elkhartlake/include/soc/pmc.h b/src/soc/intel/elkhartlake/include/soc/pmc.h
index 1c8cb1a674..a20d6fef9a 100644
--- a/src/soc/intel/elkhartlake/include/soc/pmc.h
+++ b/src/soc/intel/elkhartlake/include/soc/pmc.h
@@ -105,19 +105,18 @@
 
 #define PMC_GPP_B				0x0
 #define PMC_GPP_T				0x1
-#define PMC_GPP_D				0x2
-#define PMC_GPP_A				0x3
-#define PMC_GPP_R				0x4
+#define PMC_GPP_A				0x2
+#define PMC_GPP_R				0x3
+#define PMC_GPD					0x4
 #define PMC_GPP_V				0x5
-#define PMC_GPD					0x6
-#define PMC_GPP_H				0x7
+#define PMC_GPP_H				0x6
+#define PMC_GPP_D				0x7
 #define PMC_GPP_U				0x8
 #define PMC_VGPIO				0x9
 #define PMC_GPP_F				0xA
 #define PMC_GPP_C				0xB
 #define PMC_GPP_E				0xC
 #define PMC_GPP_G				0xD
-#define PMC_GPP_S				0xE
 
 #define GBLRST_CAUSE0			0x1924
 #define   GBLRST_CAUSE0_THERMTRIP	(1 << 5)

From 6a082679cded3a423a988648b433c2953f719ed0 Mon Sep 17 00:00:00 2001
From: Felix Held <felix-coreboot@felixheld.de>
Date: Fri, 11 Apr 2025 18:18:34 +0200
Subject: [PATCH 0739/3886] soc/amd/*/i2c: add missing iomap.h include

APU_I2C*_BASE are defined in the SoC's iomap.h, so include it.

Change-Id: Id7b1674914a045699d6df53b20e35028c3936f67
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87281
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/soc/amd/cezanne/i2c.c   | 1 +
 src/soc/amd/genoa_poc/i2c.c | 1 +
 src/soc/amd/glinda/i2c.c    | 1 +
 src/soc/amd/mendocino/i2c.c | 1 +
 src/soc/amd/phoenix/i2c.c   | 1 +
 5 files changed, 5 insertions(+)

diff --git a/src/soc/amd/cezanne/i2c.c b/src/soc/amd/cezanne/i2c.c
index b8654eff95..81aa739b39 100644
--- a/src/soc/amd/cezanne/i2c.c
+++ b/src/soc/amd/cezanne/i2c.c
@@ -3,6 +3,7 @@
 #include <amdblocks/i2c.h>
 #include <console/console.h>
 #include <soc/i2c.h>
+#include <soc/iomap.h>
 #include <soc/southbridge.h>
 #include <static.h>
 #include "chip.h"
diff --git a/src/soc/amd/genoa_poc/i2c.c b/src/soc/amd/genoa_poc/i2c.c
index 6436e3d190..60767a9c5f 100644
--- a/src/soc/amd/genoa_poc/i2c.c
+++ b/src/soc/amd/genoa_poc/i2c.c
@@ -2,6 +2,7 @@
 
 #include <amdblocks/i2c.h>
 #include <soc/i2c.h>
+#include <soc/iomap.h>
 #include <soc/southbridge.h>
 #include <static.h>
 #include "chip.h"
diff --git a/src/soc/amd/glinda/i2c.c b/src/soc/amd/glinda/i2c.c
index ab45ff5994..aaafbc5c78 100644
--- a/src/soc/amd/glinda/i2c.c
+++ b/src/soc/amd/glinda/i2c.c
@@ -5,6 +5,7 @@
 #include <amdblocks/i2c.h>
 #include <console/console.h>
 #include <soc/i2c.h>
+#include <soc/iomap.h>
 #include <soc/southbridge.h>
 #include <static.h>
 #include "chip.h"
diff --git a/src/soc/amd/mendocino/i2c.c b/src/soc/amd/mendocino/i2c.c
index 92433a735d..da9d3fbb36 100644
--- a/src/soc/amd/mendocino/i2c.c
+++ b/src/soc/amd/mendocino/i2c.c
@@ -3,6 +3,7 @@
 #include <amdblocks/i2c.h>
 #include <console/console.h>
 #include <soc/i2c.h>
+#include <soc/iomap.h>
 #include <soc/southbridge.h>
 #include <static.h>
 #include "chip.h"
diff --git a/src/soc/amd/phoenix/i2c.c b/src/soc/amd/phoenix/i2c.c
index e069c230d4..a2b3067d24 100644
--- a/src/soc/amd/phoenix/i2c.c
+++ b/src/soc/amd/phoenix/i2c.c
@@ -3,6 +3,7 @@
 #include <amdblocks/i2c.h>
 #include <console/console.h>
 #include <soc/i2c.h>
+#include <soc/iomap.h>
 #include <soc/southbridge.h>
 #include <static.h>
 #include "chip.h"

From df3935ed878029527ccbcce8562242ff68e5e604 Mon Sep 17 00:00:00 2001
From: Subrata Banik <subratabanik@google.com>
Date: Fri, 11 Apr 2025 04:44:26 +0000
Subject: [PATCH 0740/3886] soc/qualcomm/common: Avoid hardcoding SPI bus from
 QUP range

The `spi_ctrlr_bus_map` defines the range of SPI bus numbers managed
by different controllers. Previously, the generic `spi_qup_ctrlr`
was hardcoded to manage buses 0 through 15.

Modify the `.bus_end` value for the `spi_qup_ctrlr` entry to be
`QUPV3_SE_MAX - 1`.

TEST=Able to build google/herobrine.

Change-Id: I7e9ec555a6d72d93bc23285e48eab52030978e1a
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87270
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
---
 src/soc/qualcomm/common/spi.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/src/soc/qualcomm/common/spi.c b/src/soc/qualcomm/common/spi.c
index aee124dd59..3cc7681004 100644
--- a/src/soc/qualcomm/common/spi.c
+++ b/src/soc/qualcomm/common/spi.c
@@ -2,6 +2,7 @@
 
 #include <spi-generic.h>
 #include <spi_flash.h>
+#include <soc/qcom_qup_se.h>
 #include <soc/qspi_common.h>
 #include <soc/qupv3_spi_common.h>
 
@@ -29,7 +30,7 @@ const struct spi_ctrlr_buses spi_ctrlr_bus_map[] = {
 	{
 		.ctrlr = &spi_qup_ctrlr,
 		.bus_start = 0,
-		.bus_end = 15,
+		.bus_end = QUPV3_SE_MAX - 1,
 	},
 };
 

From 62aaef76f1079eb4441dfee987ef2cb9c0d93c3b Mon Sep 17 00:00:00 2001
From: Avi Uday <aviuday@google.com>
Date: Mon, 14 Apr 2025 15:07:05 +0530
Subject: [PATCH 0741/3886] MAINTAINERS: Add Avi for intel/pantherlake and
 google/fatcat

Change-Id: I295df41b6754dc3ef33f4979e325fbba7d0b8e82
Signed-off-by: Avi Uday <aviuday@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87303
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Jayvik Desai <jayvik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
---
 MAINTAINERS | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/MAINTAINERS b/MAINTAINERS
index cf6c04fa3e..cc268c5c26 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -356,6 +356,7 @@ M:	Subrata Banik <subratabanik@google.com>
 M:	Kapil Porwal <kapilporwal@google.com>
 M:	Pranava Y N <pranavayn@google.com>
 M:	Jayvik Desai <jayvik@google.com>
+M:	Avi Uday <aviuday@google.com>
 F:	src/mainboard/google/fatcat/
 
 GOOGLE HATCH MAINBOARDS
@@ -924,6 +925,7 @@ M:	Subrata Banik <subratabanik@google.com>
 M:	Kapil Porwal <kapilporwal@google.com>
 M:	Pranava Y N <pranavayn@google.com>
 M:	Jayvik Desai <jayvik@google.com>
+M:	Avi Uday <aviuday@google.com>
 S:	Maintained
 F:	src/soc/intel/pantherlake/
 

From 9a3eae088cf220db794df59448c659aad3ec3687 Mon Sep 17 00:00:00 2001
From: Mac Chiang <mac.chiang@intel.com>
Date: Wed, 9 Apr 2025 13:44:59 +0800
Subject: [PATCH 0742/3886] mb/google/fatcat/var/felino: fix DMIC1 recording

According to the PTL GPIO implementation summary document,
NF2 is a null function pin. Correct to NF3 for DMIC_CLK_A1 and
DMIC_DAT_A1 function pins.

BUG=b:378629979
Test=emerge-fatcat coreboot
Verify DMIC recording functionality.
Command: arecord -D hw:0,10 -r 48000 -c 4 -f s32 dmic.wav

Signed-off-by: Mac Chiang <mac.chiang@intel.com>
Change-Id: Ic73b43e6d58376e0c592ef4a1a9c9d9fc7e66928
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87237
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Jayvik Desai <jayvik@google.com>
---
 src/mainboard/google/fatcat/variants/felino/gpio.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/mainboard/google/fatcat/variants/felino/gpio.c b/src/mainboard/google/fatcat/variants/felino/gpio.c
index 3b2a6934e2..a70e9fe09f 100644
--- a/src/mainboard/google/fatcat/variants/felino/gpio.c
+++ b/src/mainboard/google/fatcat/variants/felino/gpio.c
@@ -182,9 +182,9 @@ static const struct pad_config gpio_table[] = {
 	/* GPP_D15:     NC */
 	PAD_NC(GPP_D15, NONE),
 	/* GPP_D16:     PCH_DMIC_CLK1 */
-	PAD_CFG_NF(GPP_D16, NONE, DEEP, NF2),
+	PAD_CFG_NF(GPP_D16, NONE, DEEP, NF3),
 	/* GPP_D17:     PCH_DMIC_DATA1 */
-	PAD_CFG_NF(GPP_D17, NONE, DEEP, NF2),
+	PAD_CFG_NF(GPP_D17, NONE, DEEP, NF3),
 	/* GPP_D18:     PCIE_CLKREQ_SD_N */
 	PAD_CFG_NF(GPP_D18, NONE, DEEP, NF1),
 	/* GPP_D19:     NC */

From 3ea8f422550ff8672f1b08f81c1bd3791a3096d2 Mon Sep 17 00:00:00 2001
From: David Wu <david_wu@quanta.corp-partner.google.com>
Date: Wed, 9 Apr 2025 11:03:32 +0800
Subject: [PATCH 0743/3886] mb/google/nissa/var/dirks: Enable ASPM of RTL8111H

Because the NIC does not enter ASPM L1.2.
Here we add "enable_aspm_l1_2" in overridetree for RTL8111H.

BUG=b:407469351
TEST=emerge and test with command powerd_dbus_suspend.
Check firmware log output
[INFO ]  rtl: Enable ASPM L1.2

Change-Id: I0e4f0a4aba736811f3b803f4a1245a635ec59407
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87232
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
---
 src/mainboard/google/brya/variants/dirks/overridetree.cb | 1 +
 1 file changed, 1 insertion(+)

diff --git a/src/mainboard/google/brya/variants/dirks/overridetree.cb b/src/mainboard/google/brya/variants/dirks/overridetree.cb
index 27de59cc50..d80ddc488c 100644
--- a/src/mainboard/google/brya/variants/dirks/overridetree.cb
+++ b/src/mainboard/google/brya/variants/dirks/overridetree.cb
@@ -233,6 +233,7 @@ chip soc/intel/alderlake
 				register "customized_leds" = "0x05af"
 				register "wake" = "GPE0_DW2_14"	# GPP_F14
 				register "device_index" = "0"
+				register "enable_aspm_l1_2" = "1"
 				register "add_acpi_dma_property" = "true"
 				device pci 00.0 on end
 			end

From 49a257a7db8fb6245bc63d0bd06f56a16c4789e4 Mon Sep 17 00:00:00 2001
From: Tongtong Pan <pantongtong@huaqin.corp-partner.google.com>
Date: Tue, 8 Apr 2025 20:51:10 +0800
Subject: [PATCH 0744/3886] mb/google/fatcat/var/felino: Use GPP_E03 for
 EC_SYNC_IRQ

Use GPP_E03 as the EC sync interrupt and provide this value
to the embedded controller to be exported to the OS.

BUG=b:403383143
Test=emerge-fatcat coreboot and Confirm the log:
cros_ec_lpcs GOOG0004:00: Chrome EC device registered

Change-Id: If7d120fcf2de8dbbbc399d2ead4e294d11ea8a14
Signed-off-by: Tongtong Pan <pantongtong@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87210
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Jayvik Desai <jayvik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com>
---
 .../fatcat/variants/baseboard/fatcat/include/baseboard/gpio.h | 2 +-
 src/mainboard/google/fatcat/variants/felino/gpio.c            | 4 ++--
 2 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/src/mainboard/google/fatcat/variants/baseboard/fatcat/include/baseboard/gpio.h b/src/mainboard/google/fatcat/variants/baseboard/fatcat/include/baseboard/gpio.h
index dc4ce13185..067c361161 100644
--- a/src/mainboard/google/fatcat/variants/baseboard/fatcat/include/baseboard/gpio.h
+++ b/src/mainboard/google/fatcat/variants/baseboard/fatcat/include/baseboard/gpio.h
@@ -26,7 +26,7 @@
 /* Used to gate SoC's SLP_S0# signal */
 #define GPIO_SLP_S0_GATE	GPP_F23
 #elif CONFIG(BOARD_GOOGLE_FELINO)
- #define EC_SYNC_IRQ	0 /* TODO */
+ #define EC_SYNC_IRQ	GPP_E03_IRQ
  #define GPIO_PCH_WP	0 /* TODO */
 /* Used to gate SoC's SLP_S0# signal */
 #define GPIO_SLP_S0_GATE	GPP_D03
diff --git a/src/mainboard/google/fatcat/variants/felino/gpio.c b/src/mainboard/google/fatcat/variants/felino/gpio.c
index a70e9fe09f..a7df5fccb7 100644
--- a/src/mainboard/google/fatcat/variants/felino/gpio.c
+++ b/src/mainboard/google/fatcat/variants/felino/gpio.c
@@ -206,8 +206,8 @@ static const struct pad_config gpio_table[] = {
 	PAD_CFG_GPI(GPP_E01, NONE, PLTRST),
 	/* GPP_E02:     NC  */
 	PAD_NC(GPP_E02, NONE),
-	/* GPP_E03:     NC */
-	PAD_NC(GPP_E03, NONE),
+	/* GPP_E03:     EC_SYNC_IRQ */
+	PAD_CFG_GPI_APIC(GPP_E03, NONE, PLTRST, LEVEL, INVERT),
 	/* GPP_E05:     NC */
 	PAD_NC(GPP_E05, NONE),
 	/* GPP_E06:     GPP_E06 */

From eecddf1b4655356a24a1d8a540a0fbfd2684f883 Mon Sep 17 00:00:00 2001
From: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com>
Date: Thu, 10 Apr 2025 17:03:32 +0900
Subject: [PATCH 0745/3886] mb/google/nissa/var/meliks: Get wifi sar name

Add get_wifi_sar_cbfs_file_name() to return to wifi SAR file name.

BUG=b:404374545
TEST=FW_NAME=meliks emerge-nissa coreboot

Change-Id: I2d7a08059c0ed7588311a421faf59146ac43001d
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87253
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jayvik Desai <jayvik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
---
 src/mainboard/google/brya/Kconfig                     | 1 +
 src/mainboard/google/brya/variants/meliks/Makefile.mk | 1 +
 src/mainboard/google/brya/variants/meliks/variant.c   | 8 ++++++++
 3 files changed, 10 insertions(+)
 create mode 100644 src/mainboard/google/brya/variants/meliks/variant.c

diff --git a/src/mainboard/google/brya/Kconfig b/src/mainboard/google/brya/Kconfig
index c60f22a7f9..b2efed7ad9 100644
--- a/src/mainboard/google/brya/Kconfig
+++ b/src/mainboard/google/brya/Kconfig
@@ -367,6 +367,7 @@ config BOARD_GOOGLE_MARASOV
 
 config BOARD_GOOGLE_MELIKS
 	select BOARD_GOOGLE_BASEBOARD_NISSA
+	select CHROMEOS_WIFI_SAR if CHROMEOS
 	select DRIVERS_I2C_DA7219
 	select DRIVERS_INTEL_MIPI_CAMERA
 	select ENFORCE_MEM_CHANNEL_DISABLE
diff --git a/src/mainboard/google/brya/variants/meliks/Makefile.mk b/src/mainboard/google/brya/variants/meliks/Makefile.mk
index 30365181de..c6c945bd45 100644
--- a/src/mainboard/google/brya/variants/meliks/Makefile.mk
+++ b/src/mainboard/google/brya/variants/meliks/Makefile.mk
@@ -6,3 +6,4 @@ romstage-y += memory.c
 ramstage-$(CONFIG_FW_CONFIG) += fw_config.c
 ramstage-y += gpio.c
 ramstage-y += ramstage.c
+ramstage-y += variant.c
diff --git a/src/mainboard/google/brya/variants/meliks/variant.c b/src/mainboard/google/brya/variants/meliks/variant.c
new file mode 100644
index 0000000000..6a79780f6e
--- /dev/null
+++ b/src/mainboard/google/brya/variants/meliks/variant.c
@@ -0,0 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <sar.h>
+
+const char *get_wifi_sar_cbfs_filename(void)
+{
+	return "wifi_sar_0.hex";
+}

From 4e0e59e24454d0fbae80d8822c5a1112aa315fb8 Mon Sep 17 00:00:00 2001
From: Maximilian Brune <maximilian.brune@9elements.com>
Date: Sat, 12 Apr 2025 15:29:26 +0200
Subject: [PATCH 0746/3886] soc/amd/mendocino/Makefile.mk: Fix syntax with
 trailing "/"

It doesn't cause any problems, because the next line is empty. But it
is wrong nonetheless.

Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: I8f1e99e06575e769f5698e4cd86e44f0b4df8a07
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87289
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/soc/amd/mendocino/Makefile.mk | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/soc/amd/mendocino/Makefile.mk b/src/soc/amd/mendocino/Makefile.mk
index 69578d11f9..be7f4daca9 100644
--- a/src/soc/amd/mendocino/Makefile.mk
+++ b/src/soc/amd/mendocino/Makefile.mk
@@ -52,10 +52,10 @@ AMD_FW_AB_POSITION := 0x40
 endif # ($(CONFIG_CBFS_VERIFICATION), y)
 
 MENDOCINO_FW_A_POSITION=$(call int-add, \
-	$(call get_fmap_value,FMAP_SECTION_FW_MAIN_A_START) $(AMD_FW_AB_POSITION)) \
+	$(call get_fmap_value,FMAP_SECTION_FW_MAIN_A_START) $(AMD_FW_AB_POSITION))
 
 MENDOCINO_FW_B_POSITION=$(call int-add, \
-	$(call get_fmap_value,FMAP_SECTION_FW_MAIN_B_START) $(AMD_FW_AB_POSITION)) \
+	$(call get_fmap_value,FMAP_SECTION_FW_MAIN_B_START) $(AMD_FW_AB_POSITION))
 
 MENDOCINO_FW_BODY_OFFSET := 0x100
 

From 717a795f7bbd69ab2683d73510a7d074545b3423 Mon Sep 17 00:00:00 2001
From: Brian Hsu <Brian_Hsu@pegatron.corp-partner.google.com>
Date: Thu, 10 Apr 2025 16:18:51 +0800
Subject: [PATCH 0747/3886] mb/google/nissa/var/guren: Add SPD ID for
 H58G56CK8BX146

Support memory of SK-hynix H58G56CK8BX146 in mem_parts_used list,
and generate SPD ID for this part.

DRAM Part Name      Vendor     Model Spec         ID to assign
H58G56CK8BX146      SK hynix   LPDDR5X 8533 32Gb  6 (0110)

BUG=b:409971450
BRANCH=firmware-nissa-15217.B
TEST=Run command "go run ./util/spd_tools/src/part_id_gen/\
     part_id_gen.go ADL lp5 \
     src/mainboard/google/brya/variants/guren/memory/ \
     src/mainboard/google/brya/variants/guren/memory/\
     mem_parts_used.txt"

Change-Id: I4616b44a164391d7a14cc97efb059e731d35c308
Signed-off-by: Brian Hsu <Brian_Hsu@pegatron.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87275
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Brian Hsu <brian_hsu@pegatron.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Jayvik Desai <jayvik@google.com>
---
 src/mainboard/google/brya/variants/guren/memory/Makefile.mk    | 3 ++-
 .../google/brya/variants/guren/memory/dram_id.generated.txt    | 3 ++-
 .../google/brya/variants/guren/memory/mem_parts_used.txt       | 1 +
 3 files changed, 5 insertions(+), 2 deletions(-)

diff --git a/src/mainboard/google/brya/variants/guren/memory/Makefile.mk b/src/mainboard/google/brya/variants/guren/memory/Makefile.mk
index 943dfba198..87fd132c6f 100644
--- a/src/mainboard/google/brya/variants/guren/memory/Makefile.mk
+++ b/src/mainboard/google/brya/variants/guren/memory/Makefile.mk
@@ -1,7 +1,7 @@
 # SPDX-License-Identifier: GPL-2.0-or-later
 # This is an auto-generated file. Do not edit!!
 # Generated by:
-# /tmp/go-build776947141/b001/exe/part_id_gen ADL lp5 src/mainboard/google/brya/variants/guren/memory/ src/mainboard/google/brya/variants/guren/memory/mem_parts_used.txt
+# /tmp/go-build3837031112/b001/exe/part_id_gen ADL lp5 src/mainboard/google/brya/variants/guren/memory/ src/mainboard/google/brya/variants/guren/memory/mem_parts_used.txt
 
 SPD_SOURCES =
 SPD_SOURCES += spd/lp5/set-0/spd-7.hex      # ID = 0(0b0000)  Parts = K3KL8L80CM-MGCT
@@ -10,3 +10,4 @@ SPD_SOURCES += spd/lp5/set-0/spd-3.hex      # ID = 2(0b0010)  Parts = H58G56AK6B
 SPD_SOURCES += spd/lp5/set-0/spd-1.hex      # ID = 3(0b0011)  Parts = H9JCNNNBK3MLYR-N6E
 SPD_SOURCES += spd/lp5/set-0/spd-6.hex      # ID = 4(0b0100)  Parts = H58G66AK6BX070
 SPD_SOURCES += spd/lp5/set-0/spd-8.hex      # ID = 5(0b0101)  Parts = K3KL9L90CM-MGCT
+SPD_SOURCES += spd/lp5/set-0/spd-11.hex      # ID = 6(0b0110)  Parts = H58G56CK8BX146
diff --git a/src/mainboard/google/brya/variants/guren/memory/dram_id.generated.txt b/src/mainboard/google/brya/variants/guren/memory/dram_id.generated.txt
index 62cd085718..cb4da42345 100644
--- a/src/mainboard/google/brya/variants/guren/memory/dram_id.generated.txt
+++ b/src/mainboard/google/brya/variants/guren/memory/dram_id.generated.txt
@@ -1,7 +1,7 @@
 # SPDX-License-Identifier: GPL-2.0-or-later
 # This is an auto-generated file. Do not edit!!
 # Generated by:
-# /tmp/go-build776947141/b001/exe/part_id_gen ADL lp5 src/mainboard/google/brya/variants/guren/memory/ src/mainboard/google/brya/variants/guren/memory/mem_parts_used.txt
+# /tmp/go-build3837031112/b001/exe/part_id_gen ADL lp5 src/mainboard/google/brya/variants/guren/memory/ src/mainboard/google/brya/variants/guren/memory/mem_parts_used.txt
 
 DRAM Part Name                 ID to assign
 K3KL8L80CM-MGCT                0 (0000)
@@ -11,3 +11,4 @@ H9JCNNNBK3MLYR-N6E             3 (0011)
 H58G66AK6BX070                 4 (0100)
 K3KL9L90CM-MGCT                5 (0101)
 K3LKBKB0BM-MGCP                2 (0010)
+H58G56CK8BX146                 6 (0110)
diff --git a/src/mainboard/google/brya/variants/guren/memory/mem_parts_used.txt b/src/mainboard/google/brya/variants/guren/memory/mem_parts_used.txt
index a7e81204ae..796d10a21c 100644
--- a/src/mainboard/google/brya/variants/guren/memory/mem_parts_used.txt
+++ b/src/mainboard/google/brya/variants/guren/memory/mem_parts_used.txt
@@ -16,3 +16,4 @@ H9JCNNNBK3MLYR-N6E
 H58G66AK6BX070
 K3KL9L90CM-MGCT
 K3LKBKB0BM-MGCP
+H58G56CK8BX146

From 24ff10d76e2b6be4d90bc2ccb2843f857178e6a1 Mon Sep 17 00:00:00 2001
From: Ana Carolina Cabral <ana.cpmelo95@gmail.com>
Date: Tue, 25 Mar 2025 09:14:02 -0300
Subject: [PATCH 0748/3886] mb/amd/crater: Enable CPPC support

Enable CPPC configuration in mainboard devicetree.

Change-Id: Ifbe65db23aff932ceb92861426fda9358cd655be
Signed-off-by: Ana Carolina Cabral <ana.cpmelo95@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87217
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/amd/crater/devicetree_renoir.cb | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/src/mainboard/amd/crater/devicetree_renoir.cb b/src/mainboard/amd/crater/devicetree_renoir.cb
index 16d2c7e18a..cc9ad45dd1 100644
--- a/src/mainboard/amd/crater/devicetree_renoir.cb
+++ b/src/mainboard/amd/crater/devicetree_renoir.cb
@@ -37,6 +37,14 @@ chip soc/amd/cezanne
 
 	register "s0ix_enable" = "false"
 
+	# CPPC register configuration
+	register "cppc_ctrl" = "true"
+	register "cppc_perf_limit_max_range" = "0xFF"
+	register "cppc_perf_limit_min_range" = "0x00"
+	register "cppc_epp_max_range" 		 = "0xFF"
+	register "cppc_epp_min_range"		 = "0x00"
+
+
 	# general purpose PCIe clock output configuration
 	register "gpp_clk_config[0]" = "GPP_CLK_ON"
 	register "gpp_clk_config[1]" = "GPP_CLK_ON"

From 7fd815dffed936838da8f044d4142dd3c756b296 Mon Sep 17 00:00:00 2001
From: Ana Carolina Cabral <ana.cpmelo95@gmail.com>
Date: Mon, 31 Mar 2025 13:56:40 -0300
Subject: [PATCH 0749/3886] soc/amd/cezanne: Add DPTC support

Add support for DPTC by calling SB.DPTC() as part of PNOT().

Change-Id: I29d7177c96217bf03eaea818cfc1f944f4e640a6
Signed-off-by: Ana Carolina Cabral <ana.cpmelo95@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87218
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/soc/amd/cezanne/acpi/soc.asl | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/src/soc/amd/cezanne/acpi/soc.asl b/src/soc/amd/cezanne/acpi/soc.asl
index 4ab03d0f36..f89aaf4f1f 100644
--- a/src/soc/amd/cezanne/acpi/soc.asl
+++ b/src/soc/amd/cezanne/acpi/soc.asl
@@ -36,6 +36,9 @@ Scope(\_SB) {
 #include <soc/amd/common/acpi/dptc.asl>
 #endif
 
+/* Enable DPTC interface with AMD ALIB */
+External(\_SB.DPTC, MethodObj)
+
 #include "rtc_workaround.asl"
 
 /*
@@ -47,4 +50,8 @@ Method (PNOT)
 {
 	/* Report AC/DC state to ALIB using WAL1() */
 	\WAL1 ()
+
+	If (CondRefOf (\_SB.DPTC)) {
+		\_SB.DPTC()
+	}
 }

From 7e706dc02783fae97a96a58cc54ec22d2633c36f Mon Sep 17 00:00:00 2001
From: Ana Carolina Cabral <ana.cpmelo95@gmail.com>
Date: Tue, 25 Mar 2025 11:07:03 -0300
Subject: [PATCH 0750/3886] mb/amb/crater: Clean up port descriptors

Use defines to create dxio descriptors as other mainboards.

Change-Id: I09e8a9fc37a7b775b76a3d8e5faaee7828f99000
Signed-off-by: Ana Carolina Cabral <ana.cpmelo95@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87220
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 .../amd/crater/port_descriptors_renoir.c      | 68 ++++++++++---------
 1 file changed, 36 insertions(+), 32 deletions(-)

diff --git a/src/mainboard/amd/crater/port_descriptors_renoir.c b/src/mainboard/amd/crater/port_descriptors_renoir.c
index bcddf1e33e..757dab1b49 100644
--- a/src/mainboard/amd/crater/port_descriptors_renoir.c
+++ b/src/mainboard/amd/crater/port_descriptors_renoir.c
@@ -20,38 +20,37 @@
 
 #define CRATER_REVB     0x42
 
-static const fsp_dxio_descriptor crater_dxio_descriptors[] = {
-	{ /* MXM */
-		.engine_type = PCIE_ENGINE,
-		.port_present = true,
-		.start_logical_lane = 16,
-		.end_logical_lane = 23,
-		.device_number = 1,
-		.function_number = 1,
-		.link_aspm = ASPM_L1,
-		.link_aspm_L1_1 = true,
-		.link_aspm_L1_2 = true,
-		.turn_off_unused_lanes = false,
-		.clk_req = CLK_REQ0,
-		.gpio_group_id = GPIO_4,
-		.port_params = {PP_PSPP_AC, 0x133, PP_PSPP_DC, 0x122}
-	},
-	{ /* SSD */
-		.engine_type = PCIE_ENGINE,
-		.port_present = true,
-		.start_logical_lane = 8,
-		.end_logical_lane = 11,
-		.device_number = 2,
-		.function_number = 4,
-		.link_aspm = ASPM_DISABLED,
-		.link_aspm_L1_1 = false,
-		.link_aspm_L1_2 = false,
-		.turn_off_unused_lanes = false,
-		.clk_req = CLK_REQ3,
-		.gpio_group_id = GPIO_27,
-		.port_params = {PP_PSPP_AC, 0x133, PP_PSPP_DC, 0x122}
-	},
-};
+#define mxm_dxio_descriptor {	\
+	.engine_type = PCIE_ENGINE, \
+	.port_present = true, \
+	.start_logical_lane = 16, \
+	.end_logical_lane = 23, \
+	.device_number = 1, \
+	.function_number = 1, \
+	.link_aspm = ASPM_L1, \
+	.link_aspm_L1_1 = true, \
+	.link_aspm_L1_2 = true, \
+	.turn_off_unused_lanes = false, \
+	.clk_req = CLK_REQ0, \
+	.gpio_group_id = GPIO_4, \
+	.port_params = {PP_PSPP_AC, 0x133, PP_PSPP_DC, 0x122}, \
+}
+
+#define ssd_dxio_descriptor { \
+	.engine_type = PCIE_ENGINE, \
+	.port_present = true, \
+	.start_logical_lane = 8, \
+	.end_logical_lane = 11, \
+	.device_number = 2, \
+	.function_number = 4, \
+	.link_aspm = ASPM_DISABLED, \
+	.link_aspm_L1_1 = false, \
+	.link_aspm_L1_2 = false, \
+	.turn_off_unused_lanes = false, \
+	.clk_req = CLK_REQ3, \
+	.gpio_group_id = GPIO_27, \
+	.port_params = {PP_PSPP_AC, 0x133, PP_PSPP_DC, 0x122}, \
+}
 
 static fsp_ddi_descriptor crater_ddi_descriptors[] = {
 	{ /* DDI0 - DP */
@@ -102,6 +101,11 @@ void mainboard_get_dxio_ddi_descriptors(
 			crater_ddi_descriptors[1].connector_type = DDI_HDMI;
 	}
 
+	static const fsp_dxio_descriptor crater_dxio_descriptors[] = {
+		mxm_dxio_descriptor,
+		ssd_dxio_descriptor
+	};
+
 	*dxio_descs = crater_dxio_descriptors;
 	*dxio_num = ARRAY_SIZE(crater_dxio_descriptors);
 	*ddi_descs = crater_ddi_descriptors;

From aa9f0881b3e01e6dac1b1308800e8d60c3aae859 Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Tue, 1 Apr 2025 22:20:45 -0500
Subject: [PATCH 0751/3886] mb/starlabs/starbook: Simplify CFR options

Move declaration of all CFR objects to a header file, so they don't
need to be guarded. Simplify the enablement of CFR options by creating
board-level Kconfig options as needed.

TEST=build/boot starbook MTL, TGL, ADL-N.

Change-Id: I43dfa6795708e9975b938ce1359629f6b9c4f1cf
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87088
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
---
 src/mainboard/starlabs/starbook/Kconfig |  20 +++
 src/mainboard/starlabs/starbook/cfr.c   | 216 +-----------------------
 src/mainboard/starlabs/starbook/cfr.h   | 204 ++++++++++++++++++++++
 3 files changed, 229 insertions(+), 211 deletions(-)
 create mode 100644 src/mainboard/starlabs/starbook/cfr.h

diff --git a/src/mainboard/starlabs/starbook/Kconfig b/src/mainboard/starlabs/starbook/Kconfig
index f902f96ade..eb718cc169 100644
--- a/src/mainboard/starlabs/starbook/Kconfig
+++ b/src/mainboard/starlabs/starbook/Kconfig
@@ -244,4 +244,24 @@ config VARIANT_DIR
 	default "adl_n" if BOARD_STARLABS_STARBOOK_ADL_N
 	default "mtl" if BOARD_STARLABS_STARBOOK_MTL
 
+config BOARD_HAS_FPR
+	bool
+	default y if BOARD_STARLABS_STARBOOK_ADL || BOARD_STARLABS_STARBOOK_RPL
+	default n
+
+config BOARD_HAS_GNA
+	bool
+	default y if SOC_INTEL_TIGERLAKE || SOC_INTEL_ALDERLAKE || SOC_INTEL_RAPTORLAKE || SOC_INTEL_METEORLAKE
+	default n
+
+config BOARD_SUPPORTS_HT
+	bool
+	default n if SOC_INTEL_ALDERLAKE_PCH_N
+	default y
+
+config BOARD_SUPPORTS_HOTPLUG
+	bool
+	default y if BOARD_STARLABS_STARBOOK_ADL
+	default n
+
 endif
diff --git a/src/mainboard/starlabs/starbook/cfr.c b/src/mainboard/starlabs/starbook/cfr.c
index 33d4b64727..92416b91de 100644
--- a/src/mainboard/starlabs/starbook/cfr.c
+++ b/src/mainboard/starlabs/starbook/cfr.c
@@ -5,215 +5,9 @@
 #include <drivers/option/cfr_frontend.h>
 #include <ec/starlabs/merlin/cfr.h>
 #include <inttypes.h>
-#include <intelblocks/pcie_rp.h>
 #include <string.h>
 #include <types.h>
-#include <variants.h>
-
-static const struct sm_object boot_option = SM_DECLARE_ENUM({
-	.opt_name	= "boot_option",
-	.ui_name	= "Boot Option",
-	.ui_helptext	= "Change the boot device in the event of a failed boot",
-	.default_value	= 0,
-	.values		= (const struct sm_enum_value[]) {
-				{ "Fallback",		0		},
-				{ "Normal",		1		},
-				SM_ENUM_VALUE_END			},
-});
-
-static const struct sm_object card_reader = SM_DECLARE_BOOL({
-	.opt_name	= "card_reader",
-	.ui_name	= "Card Reader",
-	.ui_helptext	= "Enable or disable the built-in card reader",
-	.default_value	= true,
-});
-
-static const struct sm_object debug_level = SM_DECLARE_ENUM({
-	.opt_name	= "debug_level",
-	.ui_name	= "Debug Level",
-	.ui_helptext	= "Set the verbosity of the debug output.",
-	.default_value	= 0,
-	.values		= (const struct sm_enum_value[]) {
-				{ "Emergency",		0		},
-				{ "Alert",		1		},
-				{ "Critical",		2		},
-				{ "Error",		3		},
-				{ "Warning",		4		},
-				{ "Notice",		5		},
-				{ "Info",		6		},
-				{ "Debug",		7		},
-				{ "Spew",		8		},
-				SM_ENUM_VALUE_END			},
-});
-
-#if CONFIG(BOARD_STARLABS_STARBOOK_ADL) || CONFIG(BOARD_STARLABS_STARBOOK_RPL)
-static const struct sm_object fingerprint_reader = SM_DECLARE_BOOL({
-	.opt_name	= "fingerprint_reader",
-	.ui_name	= "Fingerprint Reader",
-	.ui_helptext	= "Enable or disable the built-in fingerprint reader",
-	.default_value	= true,
-});
-#endif
-
-#if CONFIG(SOC_INTEL_TIGERLAKE) || CONFIG(SOC_INTEL_ALDERLAKE) || CONFIG(SOC_INTEL_RAPTORLAKE) || CONFIG(SOC_INTEL_METEORLAKE)
-static const struct sm_object gna = SM_DECLARE_BOOL({
-	.opt_name	= "gna",
-	.ui_name	= "Gaussian & Neural Accelerator",
-	.ui_helptext	= "Enable or Disable the Gaussian & Neural Accelerator",
-	.default_value	= false,
-});
-#endif
-
-#if !CONFIG(SOC_INTEL_ALDERLAKE_PCH_N)
-static const struct sm_object hyper_threading = SM_DECLARE_BOOL({
-	.opt_name	= "hyper_threading",
-	.ui_name	= "Hyper-Threading",
-	.ui_helptext	= "Enable or disable Hyper-Threading",
-	.default_value	= true,
-});
-#endif
-
-static const struct sm_object me_state = SM_DECLARE_ENUM({
-	.opt_name	= "me_state",
-	.ui_name	= "Intel Management Engine",
-	.ui_helptext	= "Enable or disable the Intel Management Engine",
-	.default_value	= 1,
-	.values		= (const struct sm_enum_value[]) {
-				{ "Disabled",		1		},
-				{ "Enabled",		0		},
-				SM_ENUM_VALUE_END			},
-});
-
-static const struct sm_object me_state_counter = SM_DECLARE_NUMBER({
-	.opt_name	= "me_state_counter",
-	.ui_name	= "ME State Counter",
-	.flags		= CFR_OPTFLAG_SUPPRESS,
-	.default_value	= 0,
-});
-
-static const struct sm_object power_on_after_fail = SM_DECLARE_BOOL({
-	.opt_name	= "power_on_after_fail",
-	.ui_name	= "Power on after failure",
-	.ui_helptext	= "Automatically turn on after a power failure",
-	.default_value	= false,
-});
-
-static const struct sm_object power_profile = SM_DECLARE_ENUM({
-	.opt_name	= "power_profile",
-	.ui_name	= "Power Profile",
-	.ui_helptext	= "Select whether to maximize performance, battery life or both.",
-	.default_value	= 1,
-	.values		= (const struct sm_enum_value[]) {
-				{ "Power Saver",	PP_POWER_SAVER	},
-				{ "Balanced",		PP_BALANCED	},
-				{ "Performance",	PP_PERFORMANCE	},
-				SM_ENUM_VALUE_END			},
-});
-
-static const struct sm_object microphone = SM_DECLARE_BOOL({
-	.opt_name	= "microphone",
-	.ui_name	= "Microphone",
-	.ui_helptext	= "Enable or disable the built-in microphone",
-	.default_value	= true,
-});
-
-#if CONFIG(BOARD_STARLABS_STARBOOK_ADL)
-static const struct sm_object pci_hot_plug = SM_DECLARE_BOOL({
-	.opt_name	= "pci_hot_plug",
-	.ui_name	= "Third-Party SSD Support",
-	.ui_helptext	= "Enables PCI Hot Plug, which slows down the SSD initialization. It"
-			  " is required for certain third-party SSDs to be detected.",
-	.default_value	= false,
-});
-#endif
-
-#if CONFIG(SOC_INTEL_ALDERLAKE) || CONFIG(SOC_INTEL_METEORLAKE)
-static const struct sm_object pciexp_aspm = SM_DECLARE_ENUM({
-	.opt_name	= "pciexp_aspm",
-	.ui_name	= "PCI ASPM",
-	.ui_helptext	= "Controls the Active State Power Management for PCI devices."
-			  " Enabling this feature can reduce power consumption of"
-			  " PCI-connected devices during idle times.",
-	.default_value	= ASPM_L0S_L1,
-	.values		= (const struct sm_enum_value[]) {
-				{ "Disabled",		ASPM_DISABLE	},
-				{ "L0s",		ASPM_L0S	},
-				{ "L1",			ASPM_L1		},
-				{ "L0sL1",		ASPM_L0S_L1	},
-				SM_ENUM_VALUE_END			},
-});
-
-static const struct sm_object pciexp_clk_pm = SM_DECLARE_BOOL({
-	.opt_name	= "pciexp_clk_pm",
-	.ui_name	= "PCI Clock Power Management",
-	.ui_helptext	= "Enables or disables power management for the PCI clock. When"
-			  " enabled, it reduces power consumption during idle states."
-			  " This can help lower overall energy use but may impact"
-			  " performance in power-sensitive tasks.",
-	.default_value	= true,
-});
-
-static const struct sm_object pciexp_l1ss = SM_DECLARE_ENUM({
-	.opt_name	= "pciexp_l1ss",
-	.ui_name	= "PCI L1 Substates",
-	.ui_helptext	= "Controls deeper power-saving states for PCI devices."
-			  " Enabling this feature allows supported devices to achieve"
-			  " lower power states at the cost of slightly increased"
-			  " latency when exiting these states.",
-	.default_value	= L1_SS_L1_2,
-	.values		= (const struct sm_enum_value[]) {
-				{ "Disabled",		L1_SS_DISABLED	},
-				{ "L1.1",		L1_SS_L1_1	},
-				{ "L1.2",		L1_SS_L1_2	},
-				SM_ENUM_VALUE_END			},
-});
-#endif
-
-static const struct sm_object reboot_counter = SM_DECLARE_NUMBER({
-	.opt_name	= "reboot_counter",
-	.ui_name	= "Reboot Counter",
-	.flags		= CFR_OPTFLAG_SUPPRESS,
-	.default_value	= 0,
-});
-
-#if CONFIG(DRIVERS_INTEL_USB4_RETIMER)
-static const struct sm_object thunderbolt = SM_DECLARE_BOOL({
-	.opt_name	= "thunderbolt",
-	.ui_name	= "Thunderbolt",
-	.ui_helptext	= "Enable or disable Thunderbolt support",
-	.default_value	= true,
-});
-#endif
-
-#if CONFIG(SOC_INTEL_METEORLAKE)
-static const struct sm_object vpu = SM_DECLARE_BOOL({
-	.opt_name	= "vpu",
-	.ui_name	= "VPU",
-	.ui_helptext	= "Enable or disable VPU",
-	.default_value	= true,
-});
-#endif
-
-static const struct sm_object webcam = SM_DECLARE_BOOL({
-	.opt_name	= "webcam",
-	.ui_name	= "Webcam",
-	.ui_helptext	= "Enable or disable the built-in webcam",
-	.default_value	= true,
-});
-
-static const struct sm_object wireless = SM_DECLARE_BOOL({
-	.opt_name	= "wireless",
-	.ui_name	= "Wireless",
-	.ui_helptext	= "Enable or disable the built-in wireless card",
-	.default_value	= true,
-});
-
-static const struct sm_object vtd = SM_DECLARE_BOOL({
-	.opt_name	= "vtd",
-	.ui_name	= "VT-d",
-	.ui_helptext	= "Enable or disable Intel VT-d (virtualization)",
-	.default_value	= true,
-});
+#include "cfr.h"
 
 static struct sm_obj_form performance = {
 	.ui_name = "Performance",
@@ -229,7 +23,7 @@ static struct sm_obj_form processor = {
 	.obj_list = (const struct sm_object *[]) {
 		&me_state,
 		&me_state_counter,
-		#if !CONFIG(SOC_INTEL_ALDERLAKE_PCH_N)
+		#if CONFIG(BOARD_SUPPORTS_HT)
 		&hyper_threading,
 		#endif
 		&vtd,
@@ -262,10 +56,10 @@ static struct sm_obj_form devices = {
 	.ui_name = "Devices",
 	.obj_list = (const struct sm_object *[]) {
 		&card_reader,
-		#if CONFIG(BOARD_STARLABS_STARBOOK_ADL) || CONFIG(BOARD_STARLABS_STARBOOK_RPL)
+		#if CONFIG(BOARD_HAS_FPR)
 		&fingerprint_reader,
 		#endif
-		#if CONFIG(SOC_INTEL_TIGERLAKE) || CONFIG(SOC_INTEL_ALDERLAKE) || CONFIG(SOC_INTEL_RAPTORLAKE) || CONFIG(SOC_INTEL_METEORLAKE)
+		#if CONFIG(BOARD_HAS_GNA)
 		&gna,
 		#endif
 		#if CONFIG(EC_STARLABS_LID_SWITCH)
@@ -290,7 +84,7 @@ static struct sm_obj_form pci = {
 		#if CONFIG(BOARD_STARLABS_STARBOOK_ADL)
 		&pci_hot_plug,
 		#endif
-		#if CONFIG(SOC_INTEL_ALDERLAKE) || CONFIG(SOC_INTEL_METEORLAKE)
+		#if CONFIG(SOC_INTEL_COMMON_BLOCK_ASPM)
 		&pciexp_clk_pm,
 		&pciexp_aspm,
 		&pciexp_l1ss,
diff --git a/src/mainboard/starlabs/starbook/cfr.h b/src/mainboard/starlabs/starbook/cfr.h
new file mode 100644
index 0000000000..4ddf363573
--- /dev/null
+++ b/src/mainboard/starlabs/starbook/cfr.h
@@ -0,0 +1,204 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+
+#ifndef _STARBOOK_CFR_H_
+#define _STARBOOK_CFR_H_
+
+#include <drivers/option/cfr_frontend.h>
+#include <intelblocks/pcie_rp.h>
+#include <variants.h>
+
+static const struct sm_object boot_option = SM_DECLARE_ENUM({
+	.opt_name	= "boot_option",
+	.ui_name	= "Boot Option",
+	.ui_helptext	= "Change the boot device in the event of a failed boot",
+	.default_value	= 0,
+	.values		= (const struct sm_enum_value[]) {
+				{ "Fallback",		0		},
+				{ "Normal",		1		},
+				SM_ENUM_VALUE_END			},
+});
+
+static const struct sm_object card_reader = SM_DECLARE_BOOL({
+	.opt_name	= "card_reader",
+	.ui_name	= "Card Reader",
+	.ui_helptext	= "Enable or disable the built-in card reader",
+	.default_value	= true,
+});
+
+static const struct sm_object debug_level = SM_DECLARE_ENUM({
+	.opt_name	= "debug_level",
+	.ui_name	= "Debug Level",
+	.ui_helptext	= "Set the verbosity of the debug output.",
+	.default_value	= 0,
+	.values		= (const struct sm_enum_value[]) {
+				{ "Emergency",		0		},
+				{ "Alert",		1		},
+				{ "Critical",		2		},
+				{ "Error",		3		},
+				{ "Warning",		4		},
+				{ "Notice",		5		},
+				{ "Info",		6		},
+				{ "Debug",		7		},
+				{ "Spew",		8		},
+				SM_ENUM_VALUE_END			},
+});
+
+static const struct sm_object fingerprint_reader = SM_DECLARE_BOOL({
+	.opt_name	= "fingerprint_reader",
+	.ui_name	= "Fingerprint Reader",
+	.ui_helptext	= "Enable or disable the built-in fingerprint reader",
+	.default_value	= true,
+});
+
+static const struct sm_object gna = SM_DECLARE_BOOL({
+	.opt_name	= "gna",
+	.ui_name	= "Gaussian & Neural Accelerator",
+	.ui_helptext	= "Enable or Disable the Gaussian & Neural Accelerator",
+	.default_value	= false,
+});
+
+static const struct sm_object hyper_threading = SM_DECLARE_BOOL({
+	.opt_name	= "hyper_threading",
+	.ui_name	= "Hyper-Threading",
+	.ui_helptext	= "Enable or disable Hyper-Threading",
+	.default_value	= true,
+});
+
+static const struct sm_object me_state = SM_DECLARE_ENUM({
+	.opt_name	= "me_state",
+	.ui_name	= "Intel Management Engine",
+	.ui_helptext	= "Enable or disable the Intel Management Engine",
+	.default_value	= 1,
+	.values		= (const struct sm_enum_value[]) {
+				{ "Disabled",		1		},
+				{ "Enabled",		0		},
+				SM_ENUM_VALUE_END			},
+});
+
+static const struct sm_object me_state_counter = SM_DECLARE_NUMBER({
+	.opt_name	= "me_state_counter",
+	.ui_name	= "ME State Counter",
+	.flags		= CFR_OPTFLAG_SUPPRESS,
+	.default_value	= 0,
+});
+
+static const struct sm_object power_on_after_fail = SM_DECLARE_BOOL({
+	.opt_name	= "power_on_after_fail",
+	.ui_name	= "Power on after failure",
+	.ui_helptext	= "Automatically turn on after a power failure",
+	.default_value	= false,
+});
+
+static const struct sm_object power_profile = SM_DECLARE_ENUM({
+	.opt_name	= "power_profile",
+	.ui_name	= "Power Profile",
+	.ui_helptext	= "Select whether to maximize performance, battery life or both.",
+	.default_value	= 1,
+	.values		= (const struct sm_enum_value[]) {
+				{ "Power Saver",	PP_POWER_SAVER	},
+				{ "Balanced",		PP_BALANCED	},
+				{ "Performance",	PP_PERFORMANCE	},
+				SM_ENUM_VALUE_END			},
+});
+
+static const struct sm_object microphone = SM_DECLARE_BOOL({
+	.opt_name	= "microphone",
+	.ui_name	= "Microphone",
+	.ui_helptext	= "Enable or disable the built-in microphone",
+	.default_value	= true,
+});
+
+static const struct sm_object pci_hot_plug = SM_DECLARE_BOOL({
+	.opt_name	= "pci_hot_plug",
+	.ui_name	= "Third-Party SSD Support",
+	.ui_helptext	= "Enables PCI Hot Plug, which slows down the SSD initialization. It"
+			  " is required for certain third-party SSDs to be detected.",
+	.default_value	= false,
+});
+
+static const struct sm_object pciexp_aspm = SM_DECLARE_ENUM({
+	.opt_name	= "pciexp_aspm",
+	.ui_name	= "PCI ASPM",
+	.ui_helptext	= "Controls the Active State Power Management for PCI devices."
+			  " Enabling this feature can reduce power consumption of"
+			  " PCI-connected devices during idle times.",
+	.default_value	= ASPM_L0S_L1,
+	.values		= (const struct sm_enum_value[]) {
+				{ "Disabled",		ASPM_DISABLE	},
+				{ "L0s",		ASPM_L0S	},
+				{ "L1",			ASPM_L1		},
+				{ "L0sL1",		ASPM_L0S_L1	},
+				SM_ENUM_VALUE_END			},
+});
+
+static const struct sm_object pciexp_clk_pm = SM_DECLARE_BOOL({
+	.opt_name	= "pciexp_clk_pm",
+	.ui_name	= "PCI Clock Power Management",
+	.ui_helptext	= "Enables or disables power management for the PCI clock. When"
+			  " enabled, it reduces power consumption during idle states."
+			  " This can help lower overall energy use but may impact"
+			  " performance in power-sensitive tasks.",
+	.default_value	= true,
+});
+
+static const struct sm_object pciexp_l1ss = SM_DECLARE_ENUM({
+	.opt_name	= "pciexp_l1ss",
+	.ui_name	= "PCI L1 Substates",
+	.ui_helptext	= "Controls deeper power-saving states for PCI devices."
+			  " Enabling this feature allows supported devices to achieve"
+			  " lower power states at the cost of slightly increased"
+			  " latency when exiting these states.",
+	.default_value	= L1_SS_L1_2,
+	.values		= (const struct sm_enum_value[]) {
+				{ "Disabled",		L1_SS_DISABLED	},
+				{ "L1.1",		L1_SS_L1_1	},
+				{ "L1.2",		L1_SS_L1_2	},
+				SM_ENUM_VALUE_END			},
+});
+
+static const struct sm_object reboot_counter = SM_DECLARE_NUMBER({
+	.opt_name	= "reboot_counter",
+	.ui_name	= "Reboot Counter",
+	.flags		= CFR_OPTFLAG_SUPPRESS,
+	.default_value	= 0,
+});
+
+
+static const struct sm_object thunderbolt = SM_DECLARE_BOOL({
+	.opt_name	= "thunderbolt",
+	.ui_name	= "Thunderbolt",
+	.ui_helptext	= "Enable or disable Thunderbolt support",
+	.default_value	= true,
+});
+
+
+static const struct sm_object vpu = SM_DECLARE_BOOL({
+	.opt_name	= "vpu",
+	.ui_name	= "VPU",
+	.ui_helptext	= "Enable or disable VPU",
+	.default_value	= true,
+});
+
+static const struct sm_object webcam = SM_DECLARE_BOOL({
+	.opt_name	= "webcam",
+	.ui_name	= "Webcam",
+	.ui_helptext	= "Enable or disable the built-in webcam",
+	.default_value	= true,
+});
+
+static const struct sm_object wireless = SM_DECLARE_BOOL({
+	.opt_name	= "wireless",
+	.ui_name	= "Wireless",
+	.ui_helptext	= "Enable or disable the built-in wireless card",
+	.default_value	= true,
+});
+
+static const struct sm_object vtd = SM_DECLARE_BOOL({
+	.opt_name	= "vtd",
+	.ui_name	= "VT-d",
+	.ui_helptext	= "Enable or disable Intel VT-d (virtualization)",
+	.default_value	= true,
+});
+
+#endif /* _STARBOOK_CFR_H_ */

From deda4ee3040ed770724a1c3792ac8906f905be9a Mon Sep 17 00:00:00 2001
From: Yuval Peress <peress@google.com>
Date: Tue, 15 Apr 2025 04:22:00 +0000
Subject: [PATCH 0752/3886] mb/google/brya/var/uldrenite: Enable ISH

Re-enable the ISH for uldrenite and set the correct firmware name. ISH
was disabled on uldrenite due to a suspend issue that's no longer
there. Uldrenite PoR is to use the ISH. The issue was caused by a bug
in Intel's Zephyr HAL which included power management logic that
incorrectly handled one of the interrupts.

BUG=b:410645679
TEST=ISH device under lscpi.

# lspci -s 00:12.0 -knn
00:12.0 Serial controller [0700]: Intel Corporation Device [8086:54fc]
        Subsystem: Intel Corporation Device [8086:7270]
        Kernel driver in use: intel_ish_ipc
        Kernel modules: intel_ish_ipc


Change-Id: I567fd43857da0023d063c0bb1b70c206dbee47f4
Signed-off-by: Yuval Peress <peress@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87313
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
---
 src/mainboard/google/brya/variants/uldrenite/gpio.c       | 8 ++++----
 .../google/brya/variants/uldrenite/overridetree.cb        | 7 ++++++-
 2 files changed, 10 insertions(+), 5 deletions(-)

diff --git a/src/mainboard/google/brya/variants/uldrenite/gpio.c b/src/mainboard/google/brya/variants/uldrenite/gpio.c
index e8355d37e8..9097af2584 100644
--- a/src/mainboard/google/brya/variants/uldrenite/gpio.c
+++ b/src/mainboard/google/brya/variants/uldrenite/gpio.c
@@ -61,10 +61,10 @@ static const struct pad_config gpio_table[] = {
 	PAD_CFG_GPI_IRQ_WAKE(GPP_B3, NONE, PWROK, LEVEL, INVERT),
 	/* B4  : PROC_GP3 ==> EN_PP3300_UCAM_X */
 	PAD_CFG_GPO_LOCK(GPP_B4, 1, LOCK_CONFIG),
-	/* B5  : GPP_B5 ==> NC */
-	PAD_NC(GPP_B5, NONE),
-	/* B6  : GPP_B6 ==> NC */
-	PAD_NC(GPP_B6, NONE),
+	/* B5  : GPP_B5 ==> ISH_I2C0_SCL */
+	PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_B5, NONE, DEEP, NF1),
+	/* B6  : GPP_B6 ==> ISH_I2C0_SDA */
+	PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_B6, NONE, DEEP, NF1),
 	/* B7  : GPP_B7 ==> NC */
 	PAD_NC_LOCK(GPP_B7, NONE, LOCK_CONFIG),
 	/* B8  : GPP_B8 ==> NC */
diff --git a/src/mainboard/google/brya/variants/uldrenite/overridetree.cb b/src/mainboard/google/brya/variants/uldrenite/overridetree.cb
index e8ffc6072b..00de214d99 100644
--- a/src/mainboard/google/brya/variants/uldrenite/overridetree.cb
+++ b/src/mainboard/google/brya/variants/uldrenite/overridetree.cb
@@ -486,7 +486,12 @@ chip soc/intel/alderlake
 			end
 			probe DB_CELLULAR CELLULAR_RW350R
 		end # PCIE2 WWAN card
-		device ref ish off end
+		device ref ish on
+			chip drivers/intel/ish
+				register "firmware_name" = ""uldrenite_ish.bin""
+				device generic 0 on end
+			end
+		end
 		device ref shared_sram on end
 		device ref heci1 on end
 		device ref pmc hidden end

From 321f30d89e2f7131e936932ca3207b8a3491b67a Mon Sep 17 00:00:00 2001
From: Felix Held <felix-coreboot@felixheld.de>
Date: Tue, 15 Apr 2025 20:07:24 +0200
Subject: [PATCH 0753/3886] soc/amd: select RESET_VECTOR_IN_RAM from common
 non-CAR Kconfig

Select RESET_VECTOR_IN_RAM from the common SOC_AMD_COMMON_BLOCK_NONCAR
Kconfig option instead of selecting it in each AMD SoC's Kconfig which
selects SOC_AMD_COMMON_BLOCK_NONCAR.

From family 17h on, the AMD SoCs don't use cache as RAM (CAR) any more.
In most cases, including the coreboot case, the PSP puts coreboot's
bootblock into DRAM, thus RESET_VECTOR_IN_RAM needs to be selected.
There might be a case where the RESET_VECTOR_IN_RAM part isn't true, but
that isn't specific to a SoC generation, so even this unlikely case
doesn't prevent us from moving the selection of the Kconfig option to
the common non-CAR Kconfig option.

Change-Id: I87d7908f94505647f504f9d214e3c52f9c3a3715
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87322
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/soc/amd/cezanne/Kconfig          | 1 -
 src/soc/amd/common/block/cpu/Kconfig | 1 +
 src/soc/amd/genoa_poc/Kconfig        | 1 -
 src/soc/amd/glinda/Kconfig           | 1 -
 src/soc/amd/mendocino/Kconfig        | 1 -
 src/soc/amd/phoenix/Kconfig          | 1 -
 src/soc/amd/picasso/Kconfig          | 1 -
 7 files changed, 1 insertion(+), 6 deletions(-)

diff --git a/src/soc/amd/cezanne/Kconfig b/src/soc/amd/cezanne/Kconfig
index d0a2c5ec74..96e4f31e50 100644
--- a/src/soc/amd/cezanne/Kconfig
+++ b/src/soc/amd/cezanne/Kconfig
@@ -23,7 +23,6 @@ config SOC_AMD_CEZANNE
 	select PROVIDES_ROM_SHARING
 	select PSP_VERSTAGE_CCP_DMA if VBOOT_STARTS_BEFORE_BOOTBLOCK
 	select PSP_VERSTAGE_MAP_ENTIRE_SPIROM if VBOOT_STARTS_BEFORE_BOOTBLOCK
-	select RESET_VECTOR_IN_RAM
 	select RTC
 	select SOC_AMD_COMMON
 	select SOC_AMD_COMMON_BLOCK_ACP_GEN1
diff --git a/src/soc/amd/common/block/cpu/Kconfig b/src/soc/amd/common/block/cpu/Kconfig
index 0b44c55649..44ea1eb844 100644
--- a/src/soc/amd/common/block/cpu/Kconfig
+++ b/src/soc/amd/common/block/cpu/Kconfig
@@ -16,6 +16,7 @@ config SOC_AMD_COMMON_BLOCK_CAR
 config SOC_AMD_COMMON_BLOCK_NONCAR
 	bool
 	select RESERVED_PHYSICAL_ADDRESS_BITS_SUPPORT
+	select RESET_VECTOR_IN_RAM
 	help
 	  From family 17h on AMD CPUs/APUs don't use cache as RAM (CAR) any
 	  more, since the RAM initialization is already done by the PSP when
diff --git a/src/soc/amd/genoa_poc/Kconfig b/src/soc/amd/genoa_poc/Kconfig
index 503b9fd999..4754af185f 100644
--- a/src/soc/amd/genoa_poc/Kconfig
+++ b/src/soc/amd/genoa_poc/Kconfig
@@ -13,7 +13,6 @@ config SOC_SPECIFIC_OPTIONS
 	select HAVE_ACPI_TABLES
 	select HAVE_X86_64_SUPPORT
 	select HAVE_SMI_HANDLER
-	select RESET_VECTOR_IN_RAM
 	select SOC_AMD_COMMON
 	select SOC_AMD_COMMON_BLOCK_ACPI
 	select SOC_AMD_COMMON_BLOCK_ACPIMMIO
diff --git a/src/soc/amd/glinda/Kconfig b/src/soc/amd/glinda/Kconfig
index 17b349f071..9cc446c679 100644
--- a/src/soc/amd/glinda/Kconfig
+++ b/src/soc/amd/glinda/Kconfig
@@ -25,7 +25,6 @@ config SOC_AMD_GLINDA
 	select PROVIDES_ROM_SHARING
 	select PSP_SUPPORTS_EFS2_RELATIVE_ADDR if VBOOT_STARTS_BEFORE_BOOTBLOCK
 	select PSP_VERSTAGE_CCP_DMA if VBOOT_STARTS_BEFORE_BOOTBLOCK
-	select RESET_VECTOR_IN_RAM
 	select RTC
 	select SOC_AMD_COMMON
 	select SOC_AMD_COMMON_BLOCK_ACP_GEN2		# TODO: Check if this is still correct
diff --git a/src/soc/amd/mendocino/Kconfig b/src/soc/amd/mendocino/Kconfig
index b51e9e9f54..2adb012264 100644
--- a/src/soc/amd/mendocino/Kconfig
+++ b/src/soc/amd/mendocino/Kconfig
@@ -25,7 +25,6 @@ config SOC_AMD_REMBRANDT_BASE
 	select PSP_INCLUDES_HSP
 	select PSP_SUPPORTS_EFS2_RELATIVE_ADDR if VBOOT_STARTS_BEFORE_BOOTBLOCK
 	select PSP_VERSTAGE_CCP_DMA if VBOOT_STARTS_BEFORE_BOOTBLOCK
-	select RESET_VECTOR_IN_RAM
 	select RTC
 	select SOC_AMD_COMMON
 	select SOC_AMD_COMMON_BLOCK_ACP_GEN2
diff --git a/src/soc/amd/phoenix/Kconfig b/src/soc/amd/phoenix/Kconfig
index 07b1bc0b83..995b1cc535 100644
--- a/src/soc/amd/phoenix/Kconfig
+++ b/src/soc/amd/phoenix/Kconfig
@@ -22,7 +22,6 @@ config SOC_AMD_PHOENIX_BASE
 	select PSP_SUPPORTS_EFS2_RELATIVE_ADDR if VBOOT_STARTS_BEFORE_BOOTBLOCK
 	# TODO: (b/303516266) Re-enable CCP DMA after addressing a stall
 	# select PSP_VERSTAGE_CCP_DMA if VBOOT_STARTS_BEFORE_BOOTBLOCK
-	select RESET_VECTOR_IN_RAM
 	select RTC
 	select SOC_AMD_COMMON
 	select SOC_AMD_COMMON_BLOCK_ACP_GEN2
diff --git a/src/soc/amd/picasso/Kconfig b/src/soc/amd/picasso/Kconfig
index f450e294d7..5678aaf1fb 100644
--- a/src/soc/amd/picasso/Kconfig
+++ b/src/soc/amd/picasso/Kconfig
@@ -19,7 +19,6 @@ config SOC_AMD_PICASSO
 	select PARALLEL_MP_AP_WORK
 	select PLATFORM_USES_FSP2_0
 	select PROVIDES_ROM_SHARING
-	select RESET_VECTOR_IN_RAM
 	select RTC
 	select SOC_AMD_COMMON
 	select SOC_AMD_COMMON_BLOCK_ACP_GEN1

From 4ae6fd792aee06acb5b9d1ed454b3a129f7144df Mon Sep 17 00:00:00 2001
From: Yidi Lin <yidilin@chromium.org>
Date: Thu, 27 Mar 2025 12:52:56 +0800
Subject: [PATCH 0754/3886] soc/mediatek/common/display: Add force max swing
 quirk

A 'quirks' variable is added for panels that require special handling
in the display driver due to sensitivity to the eDP signal quality. The
display driver can then handle the special requests accordingly.

On Navi, the swing level needs to be increased to 3 (500mV) for the
ATNA40HQ01-0 panel to resolve a flickering issue.

BRANCH=rauru
BUG=b:392040003
TEST=check edp training pass and show log:
[INFO ]  fw_config match found: OLED_WQXGA_PLUS=PRESENT
...
[INFO ]  update_swing_preemphasis: Force swing setting to 3 (500 mV)

Signed-off-by: Bincai Liu <bincai.liu@mediatek.corp-partner.google.com>
Signed-off-by: Yidi Lin <yidilin@chromium.org>
Change-Id: Ifa8c45050f61d3dff1fa7aed8fa8e435391a6f3a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86999
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
---
 src/soc/mediatek/common/display.c                    | 8 ++++++++
 src/soc/mediatek/common/dp/include/soc/dptx_common.h | 1 +
 src/soc/mediatek/common/include/soc/display.h        | 3 +++
 src/soc/mediatek/mt8196/dptx.c                       | 8 +++++++-
 4 files changed, 19 insertions(+), 1 deletion(-)

diff --git a/src/soc/mediatek/common/display.c b/src/soc/mediatek/common/display.c
index c7493feeb8..417a764499 100644
--- a/src/soc/mediatek/common/display.c
+++ b/src/soc/mediatek/common/display.c
@@ -56,6 +56,13 @@ __weak int mtk_dsi_init(u32 mode_flags, u32 format, u32 lanes,
 	return -1;
 }
 
+static void process_panel_quirks(struct mtk_dp *mtk_dp,
+				 struct panel_description *panel)
+{
+	if (panel->quirks & PANEL_QUIRK_FORCE_MAX_SWING)
+		mtk_dp->force_max_swing = true;
+}
+
 int mtk_display_init(void)
 {
 	struct edid edid = {0};
@@ -80,6 +87,7 @@ int mtk_display_init(void)
 		panel->power_on();
 
 	mtk_ddp_init();
+	process_panel_quirks(&mtk_edp, panel);
 
 	if (panel->disp_path == DISP_PATH_EDP) {
 		mdelay(200);
diff --git a/src/soc/mediatek/common/dp/include/soc/dptx_common.h b/src/soc/mediatek/common/dp/include/soc/dptx_common.h
index 2ea070eca7..af8c9dce6d 100644
--- a/src/soc/mediatek/common/dp/include/soc/dptx_common.h
+++ b/src/soc/mediatek/common/dp/include/soc/dptx_common.h
@@ -212,6 +212,7 @@ struct mtk_dp {
 	bool dsc_enable;
 	bool enabled;
 	bool powered;
+	bool force_max_swing;
 };
 
 int mtk_edp_init(struct mtk_dp *mtk_dp, struct edid *edid);
diff --git a/src/soc/mediatek/common/include/soc/display.h b/src/soc/mediatek/common/include/soc/display.h
index 61bc21fc98..2881505860 100644
--- a/src/soc/mediatek/common/include/soc/display.h
+++ b/src/soc/mediatek/common/include/soc/display.h
@@ -12,6 +12,8 @@ enum disp_path_sel {
 	DISP_PATH_MIPI,
 };
 
+#define PANEL_QUIRK_FORCE_MAX_SWING	BIT(0)
+
 struct panel_description {
 	const char *name;
 	void (*configure_backlight)(void);
@@ -21,6 +23,7 @@ struct panel_description {
 	enum lb_fb_orientation orientation;
 	enum disp_path_sel disp_path;
 	bool pwm_ctrl_gpio;
+	uint32_t quirks;
 };
 
 int mtk_display_init(void);
diff --git a/src/soc/mediatek/mt8196/dptx.c b/src/soc/mediatek/mt8196/dptx.c
index 926850a675..b892b1a562 100644
--- a/src/soc/mediatek/mt8196/dptx.c
+++ b/src/soc/mediatek/mt8196/dptx.c
@@ -61,7 +61,13 @@ static void update_swing_preemphasis(struct mtk_dp *mtk_dp, u8 lane_count,
 		int shift = lane % 2 ? DP_ADJUST_VOLTAGE_SWING_LANE1_SHIFT : 0;
 		u8 swing_value = dpcd_adjust_req[index] >> shift;
 
-		swing_val[lane] = swing_value & DP_ADJUST_VOLTAGE_SWING_LANE0_MASK;
+		if (mtk_dp->force_max_swing) {
+			swing_val[lane] = DPTX_SWING3;
+			printk(BIOS_INFO, "%s: Force swing setting to %u (500 mV)\n",
+			       __func__, swing_val[lane]);
+		} else {
+			swing_val[lane] = swing_value & DP_ADJUST_VOLTAGE_SWING_LANE0_MASK;
+		}
 		preemphasis[lane] = swing_value & DP_ADJUST_PRE_EMPHASIS_LANE0_MASK;
 		preemphasis[lane] >>= DP_ADJUST_PRE_EMPHASIS_LANE0_SHIFT;
 		val = swing_val[lane] << DP_TRAIN_VOLTAGE_SWING_SHIFT |

From 816d956dfd18c0d59f092d880e3513b1e3e3c677 Mon Sep 17 00:00:00 2001
From: Patrick Rudolph <patrick.rudolph@9elements.com>
Date: Thu, 10 Apr 2025 08:26:40 +0200
Subject: [PATCH 0755/3886] arch/x86: Use defines for GDT segments

Stop using magic values and use defines for Global Descriptor Table
(GDT) offsets. Use the existing defines from the corresponding headers.

Change-Id: I40c15f6341bdef9cd457619ec81e7ac624ec2d63
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87254
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/arch/x86/wakeup.S               | 8 +++++---
 src/cpu/x86/smm/smm_stub.S          | 5 +++--
 src/device/oprom/realmode/x86_asm.S | 2 +-
 3 files changed, 9 insertions(+), 6 deletions(-)

diff --git a/src/arch/x86/wakeup.S b/src/arch/x86/wakeup.S
index 7462dadbe8..7bff006d14 100644
--- a/src/arch/x86/wakeup.S
+++ b/src/arch/x86/wakeup.S
@@ -1,5 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
+#include <arch/ram_segs.h>
+
 #define WAKEUP_BASE		0x600
 #define RELOCATED(x)	(x - __wakeup + WAKEUP_BASE)
 
@@ -29,7 +31,7 @@ __wakeup:
 	add	$8, %rax
 	push	%rax
 	pushfq
-	push	$0x10
+	push	$RAM_CODE_SEG
 	lea	3(%rip), %rax
 	push	%rax
 	iretq
@@ -58,7 +60,7 @@ __wakeup:
 	movw	%ax, (__wakeup_segment)
 
 	/* Activate the right segment descriptor real mode. */
-	ljmp	$0x28, $RELOCATED(1f)
+	ljmp	$RAM_CODE16_SEG, $RELOCATED(1f)
 1:
 .code16
 	/* 16 bit code from here on... */
@@ -68,7 +70,7 @@ __wakeup:
 	 * configurations (limits, writability, etc.) once
 	 * protected mode is turned off.
 	 */
-	mov	$0x30, %ax
+	mov	$RAM_DATA16_SEG, %ax
 	mov	%ax, %ds
 	mov	%ax, %es
 	mov	%ax, %fs
diff --git a/src/cpu/x86/smm/smm_stub.S b/src/cpu/x86/smm/smm_stub.S
index 9b4b966f7c..ae8e047f4e 100644
--- a/src/cpu/x86/smm/smm_stub.S
+++ b/src/cpu/x86/smm/smm_stub.S
@@ -9,6 +9,7 @@
  * found in smm.h.
  */
 
+#include <arch/rom_segs.h>
 #include <cpu/x86/cr.h>
 #include <cpu/x86/msr.h>
 #include <cpu/x86/lapic_def.h>
@@ -93,7 +94,7 @@ untampered_lapic:
 	movl	%eax, %cr0
 
 	/* Enable protected mode */
-	ljmpl	$0x8, $smm_trampoline32
+	ljmpl	$ROM_CODE_SEG, $smm_trampoline32
 
 .align 4
 smm_relocate_gdt:
@@ -124,7 +125,7 @@ smm_relocate_gdt_end:
 .global smm_trampoline32
 smm_trampoline32:
 	/* Use flat data segment */
-	movw	$0x10, %ax
+	movw	$ROM_DATA_SEG, %ax
 	movw	%ax, %ds
 	movw	%ax, %es
 	movw	%ax, %ss
diff --git a/src/device/oprom/realmode/x86_asm.S b/src/device/oprom/realmode/x86_asm.S
index a2c4aa56b9..ff33c0f4ba 100644
--- a/src/device/oprom/realmode/x86_asm.S
+++ b/src/device/oprom/realmode/x86_asm.S
@@ -150,7 +150,7 @@ __realmode_call:
 	mov	%ax, %es
 	mov	%ax, %fs
 	mov	%ax, %gs
-	mov	$0x40, %ax
+	mov	$RAM_DATA_ACPI_SEG, %ax
 	mov	%ax, %ds
 	pop	%ax
 

From b375a5bbba0d8c252b8d44c387e5b7d349121fbd Mon Sep 17 00:00:00 2001
From: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Date: Mon, 14 Apr 2025 11:03:08 +0800
Subject: [PATCH 0756/3886] mb/google/nissa/var/dirks: correct usb2_ports
 setting

When re-purposing the TCSS port to USB Type-A, PortResetMessageEnable
must be enabled for USB2 ports that are paired with the CPU XHCI port.
Set to USB2_PORT_TYPE_C to enable PortResetMessageEnable.

Also remove the workaround. (workaround CL:87053)

BUG=b:400809281
TEST=Connecting a USB3 speed device,using lsusb -t to check enumerated status.
with change:
/:  Bus 02.Port 1: Dev 1, Class=root_hub, Driver=xhci_hcd/2p, 20000M/x2
    |__ Port 2: Dev 2, If 0, Class=Mass Storage, Driver=usb-storage, 5000M

without change:
/:  Bus 03.Port 1: Dev 1, Class=root_hub, Driver=xhci_hcd/12p, 480M
    |__ Port 2: Dev 4, If 0, Class=Mass Storage, Driver=usb-storage, 480M

Change-Id: I7c4743d1d3bcf2567fdca9c0e07ed02c240d4baf
Signed-off-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87301
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
---
 src/mainboard/google/brya/Kconfig                        | 4 ----
 src/mainboard/google/brya/variants/dirks/overridetree.cb | 4 +++-
 2 files changed, 3 insertions(+), 5 deletions(-)

diff --git a/src/mainboard/google/brya/Kconfig b/src/mainboard/google/brya/Kconfig
index b2efed7ad9..931cef4218 100644
--- a/src/mainboard/google/brya/Kconfig
+++ b/src/mainboard/google/brya/Kconfig
@@ -1183,8 +1183,4 @@ config SKIP_RAM_ID_STRAPS
 
 	  If unsure, leave this option disabled.
 
-config D3COLD_SUPPORT
-	bool
-	default n if BOARD_GOOGLE_DIRKS
-
 endif # BOARD_GOOGLE_BRYA_COMMON
diff --git a/src/mainboard/google/brya/variants/dirks/overridetree.cb b/src/mainboard/google/brya/variants/dirks/overridetree.cb
index d80ddc488c..6a5d444f12 100644
--- a/src/mainboard/google/brya/variants/dirks/overridetree.cb
+++ b/src/mainboard/google/brya/variants/dirks/overridetree.cb
@@ -71,7 +71,9 @@ chip soc/intel/alderlake
 	register "typec_aux_bias_pads[0]" = "{.pad_auxp_dc = GPP_A21, .pad_auxn_dc = GPP_A22}"
 
 	register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC_SKIP)"	# USB2_C0
-	register "usb2_ports[1]" = "USB2_PORT_MID(OC0)"		# USB2_A0
+	# This port is repurposed from Type-C to type-A port.
+	# Still declare it as Type-C port in order to set PortResetMessageEnable UPD.
+	register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC0)"	# USB2_A0
 	register "usb2_ports[2]" = "USB2_PORT_MID(OC1)"		# USB2_A1
 	register "usb2_ports[3]" = "USB2_PORT_MID(OC2)"		# USB2_A2
 	register "usb2_ports[4]" = "USB2_PORT_MID(OC3)"		# USB2_A3

From 432625d9077c994ee9b9e6c5df69830a1f8ae96a Mon Sep 17 00:00:00 2001
From: Harrie Paijmans <hpaijmans@eltan.com>
Date: Wed, 9 Apr 2025 15:55:57 +0200
Subject: [PATCH 0757/3886] soc/intel/alderlake/vr_config: Add Amston Lake
 X7433RE
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Add the Amston Lake (9W) with MCH_ID 0x4674 to the vr_config table.

Based on Intel docs 721616 rev 2.3.

BUG=NA
TEST=Boots on Intel Alder Lake CRB with X7433RE processor

Change-Id: I7249d3223ccbb1671a0b84da1c2347737e1aec89
Signed-off-by: Harrie Paijmans <hpaijmans@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87246
Reviewed-by: Erik van den Bogaert <ebogaert@eltan.com>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
---
 src/soc/intel/alderlake/chip.h      |  2 ++
 src/soc/intel/alderlake/vr_config.c | 18 ++++++++++++++++++
 2 files changed, 20 insertions(+)

diff --git a/src/soc/intel/alderlake/chip.h b/src/soc/intel/alderlake/chip.h
index 6a95918d54..10f2d3cc0f 100644
--- a/src/soc/intel/alderlake/chip.h
+++ b/src/soc/intel/alderlake/chip.h
@@ -83,6 +83,7 @@ enum soc_intel_alderlake_power_limits {
 	ADL_S_402_35W_CORE,
 	ADL_S_202_46W_CORE,
 	ADL_S_202_35W_CORE,
+	ASL_041_9W_CORE,
 	RPL_P_682_642_482_45W_CORE,
 	RPL_P_682_482_282_28W_CORE,
 	RPL_P_282_242_142_15W_CORE,
@@ -185,6 +186,7 @@ static const struct {
 	{ PCI_DID_INTEL_ADL_S_ID_11, ADL_S_402_60W_CORE, TDP_60W },
 	{ PCI_DID_INTEL_ADL_S_ID_12, ADL_S_202_35W_CORE, TDP_35W },
 	{ PCI_DID_INTEL_ADL_S_ID_12, ADL_S_202_46W_CORE, TDP_46W },
+	{ PCI_DID_INTEL_ASL_ID_2, ASL_041_9W_CORE, TDP_9W },
 	{ PCI_DID_INTEL_RPL_P_ID_1, RPL_P_682_642_482_45W_CORE, TDP_45W },
 	{ PCI_DID_INTEL_RPL_P_ID_1, RPL_P_682_482_282_28W_CORE, TDP_28W },
 	{ PCI_DID_INTEL_RPL_P_ID_2, RPL_P_682_482_282_28W_CORE, TDP_28W },
diff --git a/src/soc/intel/alderlake/vr_config.c b/src/soc/intel/alderlake/vr_config.c
index 7128a2a79a..6a29a02960 100644
--- a/src/soc/intel/alderlake/vr_config.c
+++ b/src/soc/intel/alderlake/vr_config.c
@@ -90,6 +90,20 @@
  * +----------------+-----------+-------+-------+---------+-------------+----------+
  */
 
+/*
+ * VR Configurations for IA and GT domains for ASL SKU's.
+ * Per doc#721616 ADL N ASL EDS Addendum
+ *
+ * +----------------+-----------+-------+-------+---------+-------------+----------+
+ * |      SKU       | Setting   | AC LL | DC LL | ICC MAX | TDC Current | TDC Time |
+ * |                |           |(mOhms)|(mOhms)|   (A)   |     (A)     |   (msec) |
+ * +----------------+-----------+-------+-------+---------+-------------+----------+
+ * | ASL 041 (9W)   |    IA     |  5.0  |  5.0  |    32   |      12     |  28000   |
+ * +                +-----------+-------+-------+---------+-------------+----------+
+ * |                |    GT     |  6.5  |  6.5  |    29   |      22     |  28000   |
+ * +----------------+-----------+-------+-------+---------+-------------+----------+
+ */
+
 struct vr_lookup {
 	uint16_t mchid;
 	uint8_t tdp;
@@ -134,6 +148,7 @@ static const struct vr_lookup vr_config_ll[] = {
 	{ PCI_DID_INTEL_ADL_N_ID_7, 12, VR_CFG_ALL_DOMAINS_LOADLINE(5.0, 6.5) },
 	{ PCI_DID_INTEL_ADL_N_ID_8, 6,  VR_CFG_ALL_DOMAINS_LOADLINE(5.0, 6.5) },
 	{ PCI_DID_INTEL_ADL_N_ID_9, 10, VR_CFG_ALL_DOMAINS_LOADLINE(5.0, 6.5) },
+	{ PCI_DID_INTEL_ASL_ID_2, 9, VR_CFG_ALL_DOMAINS_LOADLINE(5.0, 6.5) },
 	{ PCI_DID_INTEL_RPL_P_ID_1, 28, VR_CFG_ALL_DOMAINS_LOADLINE(2.3, 3.2) },
 	{ PCI_DID_INTEL_RPL_P_ID_1, 45, VR_CFG_ALL_DOMAINS_LOADLINE(2.3, 3.2) },
 	{ PCI_DID_INTEL_RPL_P_ID_2, 28, VR_CFG_ALL_DOMAINS_LOADLINE(2.3, 3.2) },
@@ -205,6 +220,7 @@ static const struct vr_lookup vr_config_icc[] = {
 	{ PCI_DID_INTEL_ADL_N_ID_7, 12, VR_CFG_ALL_DOMAINS_ICC(37, 23) },
 	{ PCI_DID_INTEL_ADL_N_ID_8, 6,  VR_CFG_ALL_DOMAINS_ICC(27, 23) },
 	{ PCI_DID_INTEL_ADL_N_ID_9, 10, VR_CFG_ALL_DOMAINS_ICC(27, 23) },
+	{ PCI_DID_INTEL_ASL_ID_2, 9, VR_CFG_ALL_DOMAINS_ICC(32, 29) },
 	{ PCI_DID_INTEL_RPL_P_ID_1, 28, VR_CFG_ALL_DOMAINS_ICC(102, 55) },
 	{ PCI_DID_INTEL_RPL_P_ID_1, 45, VR_CFG_ALL_DOMAINS_ICC(160, 55) },
 	{ PCI_DID_INTEL_RPL_P_ID_2, 28, VR_CFG_ALL_DOMAINS_ICC(102, 55) },
@@ -276,6 +292,7 @@ static const struct vr_lookup vr_config_tdc_timewindow[] = {
 	{ PCI_DID_INTEL_ADL_N_ID_7, 12, VR_CFG_ALL_DOMAINS_TDC(28000, 28000) },
 	{ PCI_DID_INTEL_ADL_N_ID_8, 6,  VR_CFG_ALL_DOMAINS_TDC(28000, 28000) },
 	{ PCI_DID_INTEL_ADL_N_ID_9, 10, VR_CFG_ALL_DOMAINS_TDC(28000, 28000) },
+	{ PCI_DID_INTEL_ASL_ID_2, 9, VR_CFG_ALL_DOMAINS_TDC(28000, 28000) },
 	{ PCI_DID_INTEL_RPL_P_ID_1, 28, VR_CFG_ALL_DOMAINS_TDC(28000, 28000) },
 	{ PCI_DID_INTEL_RPL_P_ID_1, 45, VR_CFG_ALL_DOMAINS_TDC(28000, 28000) },
 	{ PCI_DID_INTEL_RPL_P_ID_2, 28, VR_CFG_ALL_DOMAINS_TDC(28000, 28000) },
@@ -347,6 +364,7 @@ static const struct vr_lookup vr_config_tdc_currentlimit[] = {
 	{ PCI_DID_INTEL_ADL_N_ID_7, 12, VR_CFG_ALL_DOMAINS_TDC_CURRENT(12, 20) },
 	{ PCI_DID_INTEL_ADL_N_ID_8, 6,  VR_CFG_ALL_DOMAINS_TDC_CURRENT(12, 16) },
 	{ PCI_DID_INTEL_ADL_N_ID_9, 10, VR_CFG_ALL_DOMAINS_TDC_CURRENT(12, 16) },
+	{ PCI_DID_INTEL_ASL_ID_2, 9, VR_CFG_ALL_DOMAINS_TDC_CURRENT(12, 22) },
 	{ PCI_DID_INTEL_RPL_P_ID_1, 28, VR_CFG_ALL_DOMAINS_TDC_CURRENT(33, 33) },
 	{ PCI_DID_INTEL_RPL_P_ID_1, 45, VR_CFG_ALL_DOMAINS_TDC_CURRENT(86, 86) },
 	{ PCI_DID_INTEL_RPL_P_ID_2, 28, VR_CFG_ALL_DOMAINS_TDC_CURRENT(33, 33) },

From eabe3957782b232e357c8ba60a559beafb2bedcf Mon Sep 17 00:00:00 2001
From: Subrata Banik <subratabanik@google.com>
Date: Tue, 15 Apr 2025 17:12:12 +0530
Subject: [PATCH 0758/3886] soc/intel/fatcat: Override FSP-M UART MMIO for GFX
 PEIM debug
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

This patch overrides the FSP-M UART MMIO base address to ensure the FSP
GFX PEIM can output debug console messages when required.

Currently, the default UART MMIO base used by FSP-M/S might not be the
intended console UART for debug output in boot stages, particularly for
the GFX PEIM. By overriding it with the value derived from
`CONFIG_UART_FOR_CONSOLE` when either `PcdSerialDebugLevel` or
`SerialDebugMrcLevel` is non-zero, we ensure that debug logs are
directed to the configured console.

This change is crucial for debugging issues within the GFX PEIM
initialization process.

BUG=b:380375181
TEST=Verified that enabling FSP debug tokens after this change allows
viewing debug output from the GFX PEIM during display initialization.

Steps to reproduce:

1. Flash an AP FW image (`image.fatcat.serial.bin`).
2. Observe the absence of debug output from the GFX PEIM during display
   initialization.
3. Dynamically enable the FSP debug token using

```
sudo cbfstool image-fatcat.serial.bin add-int -i 3 -n option/fsp_pcd_debug_level
```
4. Flash the modified AP FW image.
5. Observe debug output from the GFX PEIM during display initialization

```
[INFO]:[IsGraphicsDeviceSupported()]...
[INFO]:[GetVbtStartAddress()]
```

Change-Id: I835ef75cb3046217127823c92f708bfe4f3ff741
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87318
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Jayvik Desai <jayvik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Alok Agarwal <alok.agarwal@intel.com>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
---
 src/soc/intel/pantherlake/romstage/fsp_params.c | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/src/soc/intel/pantherlake/romstage/fsp_params.c b/src/soc/intel/pantherlake/romstage/fsp_params.c
index 521d2f2f09..b83eb18c7a 100644
--- a/src/soc/intel/pantherlake/romstage/fsp_params.c
+++ b/src/soc/intel/pantherlake/romstage/fsp_params.c
@@ -359,8 +359,11 @@ static void fsp_control_log_level(FSPM_UPD *mupd, bool is_enabled)
 	}
 
 	/* Set Event Handler if log-level is non-zero */
-	if (m_cfg->PcdSerialDebugLevel || m_cfg->SerialDebugMrcLevel)
+	if (m_cfg->PcdSerialDebugLevel || m_cfg->SerialDebugMrcLevel) {
 		arch_upd->FspEventHandler = (uintptr_t)((FSP_EVENT_HANDLER *)fsp_debug_event_handler);
+		/* Override SerialIo Uart default MMIO resource if log-level is non-zero */
+		m_cfg->SerialIoUartDebugMmioBase = UART_BASE(CONFIG_UART_FOR_CONSOLE);
+	}
 }
 
 static void fill_fsp_event_handler(FSPM_UPD *mupd)

From 5ef9259d765c2292df4ace7878ca51ce4b1f974f Mon Sep 17 00:00:00 2001
From: Kenneth Chan <kenneth.chan@quanta.corp-partner.google.com>
Date: Thu, 17 Apr 2025 11:58:30 +0800
Subject: [PATCH 0759/3886] mb/google/rex/var/kanix: Configure Acoustic noise
 mitigation

Enable Acoustic noise mitigation for google/kanix and set slew rate
to 1/8 for IA and GT domains.

BUG=b:409934780
BRANCH=firmware-rex-15709.B
TEST=Able to build and boot to google/kanix
Change-Id: I73460715ac71428843cf505a21de15a6e4d15bea
Signed-off-by: Kenneth Chan <kenneth.chan@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87349
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 .../google/rex/variants/kanix/overridetree.cb          | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/src/mainboard/google/rex/variants/kanix/overridetree.cb b/src/mainboard/google/rex/variants/kanix/overridetree.cb
index 8f2aed31bf..7ba3538879 100644
--- a/src/mainboard/google/rex/variants/kanix/overridetree.cb
+++ b/src/mainboard/google/rex/variants/kanix/overridetree.cb
@@ -88,6 +88,16 @@ chip soc/intel/meteorlake
 		[PchSerialIoIndexI2C5] = PchSerialIoPci,
 	}"
 
+	# Acoustic Noise settings and slew rate configuration:
+	#  slew rate for IA Domain: Fast/8
+	#  slew rate for GT Domain: Fast/8
+	#  Ignore slew rate configuration for SA Domain
+	register "enable_acoustic_noise_mitigation" = "1"
+	register "disable_fast_pkgc_ramp[VR_DOMAIN_IA]" = "1"
+	register "slow_slew_rate_config[VR_DOMAIN_IA]" = "SLEW_FAST_8"
+	register "disable_fast_pkgc_ramp[VR_DOMAIN_GT]" = "1"
+	register "slow_slew_rate_config[VR_DOMAIN_GT]" = "SLEW_FAST_8"
+
 	# Intel Common SoC Config
 	#+-------------------+---------------------------+
 	#| Field             |  Value                    |

From ee16627a6d67c60797aae67beb422c796138902a Mon Sep 17 00:00:00 2001
From: Yidi Lin <yidilin@chromium.org>
Date: Thu, 27 Mar 2025 12:53:05 +0800
Subject: [PATCH 0760/3886] mb/google/rauru: Add FORCE_MAX_SWING quirk for
 ATNA40HQ01-0

The flickering issue on ATNA40HQ01-0 panel can be resolved by setting
the swing level to the maximum (500mV). Therefore, add FORCE_MAX_SWING
quirk for ATNA40HQ01-0 panel where the fw config's OLED_WQXGA_PLUS field
is set to PRESENT. As OLED_WQXGA_PLUS is currently only available on
Navi, add an overridetree.cb for Navi.

BRANCH=rauru
BUG=b:392040003
TEST=check edp training pass and show log:
[INFO ]  fw_config match found: OLED_WQXGA_PLUS=PRESENT
...
[INFO ]  update_swing_preemphasis: Force swing setting to 3 (500 mV)

Change-Id: I4797ef8fe2257a9b578a969794d624d6e0f97d07
Signed-off-by: Yidi Lin <yidilin@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87028
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
---
 src/mainboard/google/rauru/Kconfig                  |  6 ++++++
 src/mainboard/google/rauru/Makefile.mk              |  4 ++++
 src/mainboard/google/rauru/include/variants.h       | 10 ++++++++++
 src/mainboard/google/rauru/panel.c                  | 11 +++++++++--
 .../google/rauru/variants/navi/Makefile.mk          |  3 +++
 .../google/rauru/variants/navi/fw_config.c          | 11 +++++++++++
 .../google/rauru/variants/navi/overridetree.cb      | 13 +++++++++++++
 7 files changed, 56 insertions(+), 2 deletions(-)
 create mode 100644 src/mainboard/google/rauru/include/variants.h
 create mode 100644 src/mainboard/google/rauru/variants/navi/Makefile.mk
 create mode 100644 src/mainboard/google/rauru/variants/navi/fw_config.c
 create mode 100644 src/mainboard/google/rauru/variants/navi/overridetree.cb

diff --git a/src/mainboard/google/rauru/Kconfig b/src/mainboard/google/rauru/Kconfig
index b32923dd23..9bccc87893 100644
--- a/src/mainboard/google/rauru/Kconfig
+++ b/src/mainboard/google/rauru/Kconfig
@@ -48,6 +48,12 @@ config MAINBOARD_PART_NUMBER
 	default "Navi" if BOARD_GOOGLE_NAVI
 	default "Rauru" if BOARD_GOOGLE_RAURU
 
+config VARIANT_DIR
+	default "navi" if BOARD_GOOGLE_NAVI
+
+config OVERRIDE_DEVICETREE
+	default "variants/\$(CONFIG_VARIANT_DIR)/overridetree.cb" if BOARD_GOOGLE_NAVI
+
 config BOOT_DEVICE_SPI_FLASH_BUS
 	int
 	default 8
diff --git a/src/mainboard/google/rauru/Makefile.mk b/src/mainboard/google/rauru/Makefile.mk
index 6ea1ffb83a..64624a16a9 100644
--- a/src/mainboard/google/rauru/Makefile.mk
+++ b/src/mainboard/google/rauru/Makefile.mk
@@ -12,3 +12,7 @@ ramstage-y += boardid.c
 ramstage-y += mainboard.c
 ramstage-y += panel.c
 ramstage-y += regulator.c
+
+CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/include
+
+subdirs-y += variants/$(VARIANT_DIR)
diff --git a/src/mainboard/google/rauru/include/variants.h b/src/mainboard/google/rauru/include/variants.h
new file mode 100644
index 0000000000..853b64a8ba
--- /dev/null
+++ b/src/mainboard/google/rauru/include/variants.h
@@ -0,0 +1,10 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef __MAINBOARD_GOOGLE_RAURU_VARIANTS_H__
+#define __MAINBOARD_GOOGLE_RAURU_VARIANTS_H__
+
+#include <soc/display.h>
+
+void fw_config_panel_override(struct panel_description *panel);
+
+#endif /* __MAINBOARD_GOOGLE_RAURU_VARIANTS_H__ */
diff --git a/src/mainboard/google/rauru/panel.c b/src/mainboard/google/rauru/panel.c
index 92d2f30cf1..cb7042ae3c 100644
--- a/src/mainboard/google/rauru/panel.c
+++ b/src/mainboard/google/rauru/panel.c
@@ -4,6 +4,7 @@
 #include <gpio.h>
 #include <soc/ddp.h>
 #include <soc/dsi.h>
+#include <variants.h>
 
 #include "gpio.h"
 #include "panel.h"
@@ -20,7 +21,7 @@ static void power_on_panel(void)
 	gpio_set_mode(GPIO_EDP_HPD_1V8, GPIO_FUNC(EINT13, EDP_TX_HPD));
 }
 
-static struct panel_description panel = {
+static struct panel_description rauru_panel = {
 	.configure_backlight = configure_backlight,
 	.power_on = power_on_panel,
 	.disp_path = DISP_PATH_EDP,
@@ -41,10 +42,16 @@ static struct panel_description edp_panel = {
 	.orientation = LB_FB_ORIENTATION_NORMAL,
 };
 
+__weak void fw_config_panel_override(struct panel_description *panel)
+{
+}
+
 struct panel_description *get_active_panel(void)
 {
 	if (CONFIG(BOARD_GOOGLE_RAURU))
-		return &panel;
+		return &rauru_panel;
+
+	fw_config_panel_override(&edp_panel);
 
 	return &edp_panel;
 }
diff --git a/src/mainboard/google/rauru/variants/navi/Makefile.mk b/src/mainboard/google/rauru/variants/navi/Makefile.mk
new file mode 100644
index 0000000000..52fd109576
--- /dev/null
+++ b/src/mainboard/google/rauru/variants/navi/Makefile.mk
@@ -0,0 +1,3 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
+ramstage-y += fw_config.c
diff --git a/src/mainboard/google/rauru/variants/navi/fw_config.c b/src/mainboard/google/rauru/variants/navi/fw_config.c
new file mode 100644
index 0000000000..50f5df9903
--- /dev/null
+++ b/src/mainboard/google/rauru/variants/navi/fw_config.c
@@ -0,0 +1,11 @@
+/* SPDX-License-Identifier: GPL-2.0-only OR MIT */
+
+#include <fw_config.h>
+#include <soc/display.h>
+#include <variants.h>
+
+void fw_config_panel_override(struct panel_description *panel)
+{
+	if (fw_config_probe(FW_CONFIG(OLED_WQXGA_PLUS, PRESENT)))
+		panel->quirks |= PANEL_QUIRK_FORCE_MAX_SWING;
+}
diff --git a/src/mainboard/google/rauru/variants/navi/overridetree.cb b/src/mainboard/google/rauru/variants/navi/overridetree.cb
new file mode 100644
index 0000000000..cbc5e29713
--- /dev/null
+++ b/src/mainboard/google/rauru/variants/navi/overridetree.cb
@@ -0,0 +1,13 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
+fw_config
+	field OLED_WQXGA_PLUS 1 1
+		option PRESENT	1
+		option ABSENT	0
+	end
+end
+
+chip soc/mediatek/mt8196
+	device domain 0 on
+	end
+end

From e183dc803700918c1772ac2c60734335953429c9 Mon Sep 17 00:00:00 2001
From: Zhigang Qin <zhigang.qin@mediatek.corp-partner.google.com>
Date: Wed, 26 Mar 2025 21:21:21 +0800
Subject: [PATCH 0761/3886] soc/mediatek/common: Remove infracfg.h in pmif_spi

Since infracfg.h is not used in pmif_spi.c, remove its inclusion to
prevent build errors in projects that don't have infracfg.h.

BUG=b:379008996
BRANCH=none
TEST=build pass

Signed-off-by: Zhigang Qin <zhigang.qin@mediatek.corp-partner.google.com>
Change-Id: I09229ff370a53407b3f0c290704887de367ed80b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87339
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/soc/mediatek/common/pmif_spi.c | 1 -
 1 file changed, 1 deletion(-)

diff --git a/src/soc/mediatek/common/pmif_spi.c b/src/soc/mediatek/common/pmif_spi.c
index 0ed44a041f..ea791cb91d 100644
--- a/src/soc/mediatek/common/pmif_spi.c
+++ b/src/soc/mediatek/common/pmif_spi.c
@@ -2,7 +2,6 @@
 
 #include <console/console.h>
 #include <device/mmio.h>
-#include <soc/infracfg.h>
 #include <soc/pll.h>
 #include <soc/pmif_spi.h>
 #include <soc/pmif_sw.h>

From 7dc9e62f4047d88d7699ccc73a69594e0fe39d51 Mon Sep 17 00:00:00 2001
From: Vince Liu <vince-wl.liu@mediatek.corp-partner.google.com>
Date: Fri, 8 Nov 2024 15:53:08 +0800
Subject: [PATCH 0762/3886] soc/mediatek/mt8189: Enable ARM Trusted Firmware
 integration

Enable configuration to build with MT8189 arm-trusted-firmware drivers.

BUG=b:379008996
BRANCH=none
TEST=build passed. Output coreboot log:
[INFO ]  CBFS: Found 'fallback/bl31' @0x4e880 size 0x42e9 in mcache
@0xffffeb90

Signed-off-by: Vince Liu <vince-wl.liu@mediatek.corp-partner.google.com>
Change-Id: If5c311bea10ad8cb0b8b7a5e48d9e36d0d569a7e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87003
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
---
 src/soc/mediatek/mt8189/Kconfig     | 1 +
 src/soc/mediatek/mt8189/Makefile.mk | 3 +++
 2 files changed, 4 insertions(+)

diff --git a/src/soc/mediatek/mt8189/Kconfig b/src/soc/mediatek/mt8189/Kconfig
index bf55327a78..1bbcb49344 100644
--- a/src/soc/mediatek/mt8189/Kconfig
+++ b/src/soc/mediatek/mt8189/Kconfig
@@ -7,6 +7,7 @@ config SOC_MEDIATEK_MT8189
 	select ARCH_VERSTAGE_ARMV8_64
 	select ARCH_ROMSTAGE_ARMV8_64
 	select ARCH_RAMSTAGE_ARMV8_64
+	select ARM64_USE_ARM_TRUSTED_FIRMWARE
 	select HAVE_UART_SPECIAL
 	select CACHE_MRC_SETTINGS
 	select MEDIATEK_DRAM_BLOB_FAST_INIT
diff --git a/src/soc/mediatek/mt8189/Makefile.mk b/src/soc/mediatek/mt8189/Makefile.mk
index 592734f9e4..49336930a4 100644
--- a/src/soc/mediatek/mt8189/Makefile.mk
+++ b/src/soc/mediatek/mt8189/Makefile.mk
@@ -19,6 +19,7 @@ romstage-y += ../common/emi.c
 romstage-y += ../common/memory.c ../common/memory_test.c
 romstage-y += ../common/mmu_operations.c ../common/mmu_cmops.c
 
+ramstage-$(CONFIG_ARM64_USE_ARM_TRUSTED_FIRMWARE) += ../common/bl31.c
 ramstage-y += ../common/dramc_info.c
 ramstage-y += ../common/emi.c
 ramstage-y += ../common/memory.c
@@ -26,6 +27,8 @@ ramstage-y += ../common/mmu_operations.c ../common/mmu_cmops.c
 ramstage-y += soc.c
 ramstage-y += ../common/usb.c usb.c
 
+BL31_MAKEARGS += PLAT=mt8189
+
 CPPFLAGS_common += -Isrc/soc/mediatek/mt8189/include
 CPPFLAGS_common += -Isrc/soc/mediatek/common/include
 

From 644dea4a472a0d5ebeff47128554c2c583d25b25 Mon Sep 17 00:00:00 2001
From: "ot_chhao.chang" <ot_chhao.chang@mediatek.com>
Date: Thu, 5 Dec 2024 15:21:28 +0800
Subject: [PATCH 0763/3886] soc/mediatek/mt8189: Add EINT support

Add support for configuring GPIO pull settings for external
interrupts (EINT).

BUG=b:379008996
BRANCH=none
TEST=build pass

Signed-off-by: ot_chhao.chang <ot_chhao.chang@mediatek.com>
Change-Id: I0a8e0a45eb4466d893405684f560b84e7a992630
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87337
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
---
 src/soc/mediatek/mt8189/Makefile.mk           |   2 +-
 src/soc/mediatek/mt8189/gpio_eint.c           | 225 ++++++++++++++++++
 .../mediatek/mt8189/include/soc/addressmap.h  |   8 +
 3 files changed, 234 insertions(+), 1 deletion(-)
 create mode 100644 src/soc/mediatek/mt8189/gpio_eint.c

diff --git a/src/soc/mediatek/mt8189/Makefile.mk b/src/soc/mediatek/mt8189/Makefile.mk
index 49336930a4..feba664bec 100644
--- a/src/soc/mediatek/mt8189/Makefile.mk
+++ b/src/soc/mediatek/mt8189/Makefile.mk
@@ -3,7 +3,7 @@
 ifeq ($(CONFIG_SOC_MEDIATEK_MT8189),y)
 
 all-y += ../common/flash_controller.c
-all-y += ../common/gpio.c ../common/gpio_op.c gpio.c
+all-y += ../common/gpio.c ../common/gpio_op.c ../common/gpio_eint_v2.c gpio.c gpio_eint.c
 all-$(CONFIG_SPI_FLASH) += spi.c
 all-y += ../common/timer_prepare.c timer.c
 all-y += ../common/uart.c
diff --git a/src/soc/mediatek/mt8189/gpio_eint.c b/src/soc/mediatek/mt8189/gpio_eint.c
new file mode 100644
index 0000000000..1dd1d5931b
--- /dev/null
+++ b/src/soc/mediatek/mt8189/gpio_eint.c
@@ -0,0 +1,225 @@
+/* SPDX-License-Identifier: GPL-2.0-only OR MIT */
+
+/*
+ * This file is created based on MT8189_EINT_Datasheet
+ * Chapter number: 1
+ */
+
+#include <commonlib/bsd/helpers.h>
+#include <soc/gpio_eint_v2.h>
+
+const struct eint_info eint_data[] = {
+	[0] = { EINT_E, 0 },
+	[1] = { EINT_E, 1 },
+	[2] = { EINT_E, 2 },
+	[3] = { EINT_E, 3 },
+	[4] = { EINT_E, 4 },
+	[5] = { EINT_E, 5 },
+	[6] = { EINT_E, 6 },
+	[7] = { EINT_E, 7 },
+	[8] = { EINT_E, 8 },
+	[9] = { EINT_E, 9 },
+	[10] = { EINT_E, 10 },
+	[11] = { EINT_E, 11 },
+	[12] = { EINT_S, 0 },
+	[13] = { EINT_S, 1 },
+	[14] = { EINT_S, 2 },
+	[15] = { EINT_S, 3 },
+	[16] = { EINT_S, 4 },
+	[17] = { EINT_S, 5 },
+	[18] = { EINT_E, 12 },
+	[19] = { EINT_E, 13 },
+	[20] = { EINT_E, 14 },
+	[21] = { EINT_E, 15 },
+	[22] = { EINT_E, 16 },
+	[23] = { EINT_E, 17 },
+	[24] = { EINT_E, 18 },
+	[25] = { EINT_W, 0 },
+	[26] = { EINT_W, 1 },
+	[27] = { EINT_S, 6 },
+	[28] = { EINT_S, 7 },
+	[29] = { EINT_W, 2 },
+	[30] = { EINT_S, 8 },
+	[31] = { EINT_S, 9 },
+	[32] = { EINT_S, 10 },
+	[33] = { EINT_S, 11 },
+	[34] = { EINT_S, 12 },
+	[35] = { EINT_S, 13 },
+	[36] = { EINT_S, 14 },
+	[37] = { EINT_S, 15 },
+	[38] = { EINT_S, 16 },
+	[39] = { EINT_S, 17 },
+	[40] = { EINT_S, 18 },
+	[41] = { EINT_S, 19 },
+	[42] = { EINT_S, 20 },
+	[43] = { EINT_S, 21 },
+	[44] = { EINT_E, 19 },
+	[45] = { EINT_E, 20 },
+	[46] = { EINT_E, 21 },
+	[47] = { EINT_E, 22 },
+	[48] = { EINT_W, 3 },
+	[49] = { EINT_W, 4 },
+	[50] = { EINT_W, 5 },
+	[51] = { EINT_E, 23 },
+	[52] = { EINT_E, 24 },
+	[53] = { EINT_E, 25 },
+	[54] = { EINT_E, 26 },
+	[55] = { EINT_W, 6 },
+	[56] = { EINT_W, 7 },
+	[57] = { EINT_S, 22 },
+	[58] = { EINT_S, 23 },
+	[59] = { EINT_S, 24 },
+	[60] = { EINT_S, 25 },
+	[61] = { EINT_S, 26 },
+	[62] = { EINT_S, 27 },
+	[63] = { EINT_S, 28 },
+	[64] = { EINT_S, 29 },
+	[65] = { EINT_E, 27 },
+	[66] = { EINT_E, 28 },
+	[67] = { EINT_E, 29 },
+	[68] = { EINT_E, 30 },
+	[69] = { EINT_S, 30 },
+	[70] = { EINT_S, 31 },
+	[71] = { EINT_S, 32 },
+	[72] = { EINT_S, 33 },
+	[73] = { EINT_S, 34 },
+	[74] = { EINT_S, 35 },
+	[75] = { EINT_S, 36 },
+	[76] = { EINT_S, 37 },
+	[77] = { EINT_E, 31 },
+	[78] = { EINT_E, 32 },
+	[79] = { EINT_E, 33 },
+	[80] = { EINT_E, 34 },
+	[81] = { EINT_S, 38 },
+	[82] = { EINT_S, 39 },
+	[83] = { EINT_S, 40 },
+	[84] = { EINT_E, 35 },
+	[85] = { EINT_E, 36 },
+	[86] = { EINT_E, 37 },
+	[87] = { EINT_E, 38 },
+	[88] = { EINT_W, 8 },
+	[89] = { EINT_W, 9 },
+	[90] = { EINT_W, 10 },
+	[91] = { EINT_W, 11 },
+	[92] = { EINT_W, 12 },
+	[93] = { EINT_W, 13 },
+	[94] = { EINT_W, 14 },
+	[95] = { EINT_W, 15 },
+	[96] = { EINT_W, 16 },
+	[97] = { EINT_W, 17 },
+	[98] = { EINT_W, 18 },
+	[99] = { EINT_W, 19 },
+	[100] = { EINT_W, 20 },
+	[101] = { EINT_W, 21 },
+	[102] = { EINT_W, 22 },
+	[103] = { EINT_E, 39 },
+	[104] = { EINT_E, 40 },
+	[105] = { EINT_E, 41 },
+	[106] = { EINT_E, 42 },
+	[107] = { EINT_E, 43 },
+	[108] = { EINT_E, 44 },
+	[109] = { EINT_E, 45 },
+	[110] = { EINT_E, 46 },
+	[111] = { EINT_E, 47 },
+	[112] = { EINT_E, 48 },
+	[113] = { EINT_E, 49 },
+	[114] = { EINT_E, 50 },
+	[115] = { EINT_S, 41 },
+	[116] = { EINT_S, 42 },
+	[117] = { EINT_S, 43 },
+	[118] = { EINT_S, 44 },
+	[119] = { EINT_S, 45 },
+	[120] = { EINT_S, 46 },
+	[121] = { EINT_S, 47 },
+	[122] = { EINT_S, 48 },
+	[123] = { EINT_S, 49 },
+	[124] = { EINT_S, 50 },
+	[125] = { EINT_S, 51 },
+	[126] = { EINT_S, 52 },
+	[127] = { EINT_S, 53 },
+	[128] = { EINT_S, 54 },
+	[129] = { EINT_S, 55 },
+	[130] = { EINT_S, 56 },
+	[131] = { EINT_S, 57 },
+	[132] = { EINT_S, 58 },
+	[133] = { EINT_S, 59 },
+	[134] = { EINT_S, 60 },
+	[135] = { EINT_S, 61 },
+	[136] = { EINT_S, 62 },
+	[137] = { EINT_S, 63 },
+	[138] = { EINT_S, 64 },
+	[139] = { EINT_S, 65 },
+	[140] = { EINT_S, 66 },
+	[141] = { EINT_S, 67 },
+	[142] = { EINT_S, 68 },
+	[143] = { EINT_S, 69 },
+	[144] = { EINT_S, 70 },
+	[145] = { EINT_S, 71 },
+	[146] = { EINT_S, 72 },
+	[147] = { EINT_S, 73 },
+	[148] = { EINT_S, 74 },
+	[149] = { EINT_S, 75 },
+	[150] = { EINT_S, 76 },
+	[151] = { EINT_S, 77 },
+	[152] = { EINT_S, 78 },
+	[153] = { EINT_S, 79 },
+	[154] = { EINT_S, 80 },
+	[155] = { EINT_S, 81 },
+	[156] = { EINT_W, 23 },
+	[157] = { EINT_W, 24 },
+	[158] = { EINT_W, 25 },
+	[159] = { EINT_N, 0 },
+	[160] = { EINT_W, 26 },
+	[161] = { EINT_W, 27 },
+	[162] = { EINT_W, 28 },
+	[163] = { EINT_N, 1 },
+	[164] = { EINT_W, 29 },
+	[165] = { EINT_W, 30 },
+	[166] = { EINT_N, 2 },
+	[167] = { EINT_W, 31 },
+	[168] = { EINT_S, 82 },
+	[169] = { EINT_S, 83 },
+	[170] = { EINT_S, 84 },
+	[171] = { EINT_S, 85 },
+	[172] = { EINT_S, 86 },
+	[173] = { EINT_S, 87 },
+	[174] = { EINT_N, 3 },
+	[175] = { EINT_N, 4 },
+	[176] = { EINT_N, 5 },
+	[177] = { EINT_N, 6 },
+	[178] = { EINT_N, 7 },
+	[179] = { EINT_N, 8 },
+	[180] = { EINT_W, 32 },
+	[181] = { EINT_W, 33 },
+	[182] = { EINT_C, 0 },
+	[183] = { EINT_C, 1 },
+	[184] = { EINT_C, 2 },
+	[185] = { EINT_C, 3 },
+	[186] = { EINT_C, 4 },
+	[187] = { EINT_C, 5 },
+	[188] = { EINT_C, 6 },
+	[189] = { EINT_C, 7 },
+	[190] = { EINT_C, 8 },
+	[191] = { EINT_C, 9 },
+	[192] = { EINT_C, 10 },
+	[193] = { EINT_C, 11 },
+	[194] = { EINT_C, 12 },
+	[195] = { EINT_C, 13 },
+	[196] = { EINT_C, 14 },
+	[197] = { EINT_C, 15 },
+	[198] = { EINT_C, 16 },
+	[199] = { EINT_C, 17 },
+	[200] = { EINT_C, 18 },
+	[201] = { EINT_C, 19 },
+	[202] = { EINT_C, 20 },
+	[203] = { EINT_C, 21 },
+	[204] = { EINT_C, 22 },
+	[205] = { EINT_C, 23 },
+	[206] = { EINT_C, 24 },
+	[207] = { EINT_C, 25 },
+	[208] = { EINT_C, 26 },
+	[209] = { EINT_C, 27 },
+};
+_Static_assert(ARRAY_SIZE(eint_data) == 210, "Incorrect eint_data size");
+
+const size_t eint_data_len = ARRAY_SIZE(eint_data);
diff --git a/src/soc/mediatek/mt8189/include/soc/addressmap.h b/src/soc/mediatek/mt8189/include/soc/addressmap.h
index 5d997283d0..3d559a9294 100644
--- a/src/soc/mediatek/mt8189/include/soc/addressmap.h
+++ b/src/soc/mediatek/mt8189/include/soc/addressmap.h
@@ -7,6 +7,14 @@ enum {
 	IO_PHYS = 0x10000000,
 };
 
+enum {
+	EINT_E_BASE		= IO_PHYS + 0x01CE0000,
+	EINT_S_BASE		= IO_PHYS + 0x01DE0000,
+	EINT_W_BASE		= IO_PHYS + 0x01E60000,
+	EINT_N_BASE		= IO_PHYS + 0x01F00000,
+	EINT_C_BASE		= IO_PHYS + 0x0C01E000,
+};
+
 enum {
 	CKSYS_BASE			= IO_PHYS + 0x00000000,
 	INFRACFG_AO_BASE		= IO_PHYS + 0x00001000,

From 56d60167ff593fa5a28a012b1a897155dd42893b Mon Sep 17 00:00:00 2001
From: Cong Yang <yangcong5@huaqin.corp-partner.google.com>
Date: Fri, 17 Jan 2025 12:49:04 +0800
Subject: [PATCH 0764/3886] mb/google/skywalker: Pass XHCI_INIT_DONE to the
 payload

Configure GPIO (XHCI_INIT_DONE) as output, so that payloads (for example
depthcharge) can assert it to notify EC to enable USB VBUS.

BUG=b:390357201
BRANCH=none
TEST=detect USB devices in depthcharge, and the log is like "Added USB
disk 2."

Change-Id: I99760ace3e87626f55c52dc4f8a30bab27cba345
Signed-off-by: Cong Yang <yangcong5@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87347
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
---
 src/mainboard/google/skywalker/chromeos.c |  8 +++++++-
 src/mainboard/google/skywalker/gpio.h     | 10 ++++++++++
 2 files changed, 17 insertions(+), 1 deletion(-)
 create mode 100644 src/mainboard/google/skywalker/gpio.h

diff --git a/src/mainboard/google/skywalker/chromeos.c b/src/mainboard/google/skywalker/chromeos.c
index 0e0f62d252..b779fe7bce 100644
--- a/src/mainboard/google/skywalker/chromeos.c
+++ b/src/mainboard/google/skywalker/chromeos.c
@@ -1,8 +1,14 @@
 /* SPDX-License-Identifier: GPL-2.0-only OR MIT */
 
 #include <boot/coreboot_tables.h>
+#include <gpio.h>
+
+#include "gpio.h"
 
 void fill_lb_gpios(struct lb_gpios *gpios)
 {
-	/* TODO: add ChromeOS specific gpios */
+	struct lb_gpio chromeos_gpios[] = {
+		{GPIO_XHCI_INIT_DONE.id, ACTIVE_HIGH, -1, "XHCI init done"},
+	};
+	lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios));
 }
diff --git a/src/mainboard/google/skywalker/gpio.h b/src/mainboard/google/skywalker/gpio.h
new file mode 100644
index 0000000000..11e2eb36dc
--- /dev/null
+++ b/src/mainboard/google/skywalker/gpio.h
@@ -0,0 +1,10 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef __MAINBOARD_GOOGLE_SKYWALKER_GPIO_H__
+#define __MAINBOARD_GOOGLE_SKYWALKER_GPIO_H__
+
+#include <soc/gpio.h>
+
+#define GPIO_XHCI_INIT_DONE	GPIO(GBE_MDC)
+
+#endif

From cf7460f6ea72327d509951f50c712b4870eb253a Mon Sep 17 00:00:00 2001
From: Cong Yang <yangcong5@huaqin.corp-partner.google.com>
Date: Fri, 17 Jan 2025 12:51:12 +0800
Subject: [PATCH 0765/3886] mb/google/skywalker: Enable USB3_HUB_RST

We have to reset the USB hub as early as possible. Otherwise the USB3
hub may not be usable in the payload. This design has been introduced
since Cherry.

BUG=b:390357201
BRANCH=none
TEST=detect USB devices in depthcharge, and the log is like "Added USB
disk 2."

Change-Id: I4ee24aef2a887c8a30738912a8bf90f830a72bed
Signed-off-by: Cong Yang <yangcong5@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87348
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
---
 src/mainboard/google/skywalker/bootblock.c | 9 +++++++++
 src/mainboard/google/skywalker/gpio.h      | 1 +
 2 files changed, 10 insertions(+)

diff --git a/src/mainboard/google/skywalker/bootblock.c b/src/mainboard/google/skywalker/bootblock.c
index 1062d9bbe5..71c3dfc418 100644
--- a/src/mainboard/google/skywalker/bootblock.c
+++ b/src/mainboard/google/skywalker/bootblock.c
@@ -1,9 +1,18 @@
 /* SPDX-License-Identifier: GPL-2.0-only OR MIT */
 
 #include <bootblock_common.h>
+#include <gpio.h>
 #include <soc/spi.h>
 
+#include "gpio.h"
+
+static void usb3_hub_reset(void)
+{
+	gpio_output(GPIO_USB3_HUB_RST_L, 1);
+}
+
 void bootblock_mainboard_init(void)
 {
 	mtk_snfc_init();
+	usb3_hub_reset();
 }
diff --git a/src/mainboard/google/skywalker/gpio.h b/src/mainboard/google/skywalker/gpio.h
index 11e2eb36dc..74d9b04154 100644
--- a/src/mainboard/google/skywalker/gpio.h
+++ b/src/mainboard/google/skywalker/gpio.h
@@ -6,5 +6,6 @@
 #include <soc/gpio.h>
 
 #define GPIO_XHCI_INIT_DONE	GPIO(GBE_MDC)
+#define GPIO_USB3_HUB_RST_L	GPIO(GPIO07)
 
 #endif

From b76f2dc35530ecf669094747c3f513673ae54808 Mon Sep 17 00:00:00 2001
From: Zhigang Qin <zhigang.qin@mediatek.corp-partner.google.com>
Date: Tue, 8 Apr 2025 18:51:26 +0800
Subject: [PATCH 0766/3886] soc/mediatek/common: Convert mt6359p_read_field()
 to a general API

Make mt6359p_read_field() a general API usable by multiple drivers,
instead of a static function limited to the original driver.

BUG=b:379008996
BRANCH=none
TEST=build pass

Signed-off-by: Zhigang Qin <zhigang.qin@mediatek.corp-partner.google.com>
Change-Id: I2d9c3de9ad08f918a84fa63c1e9b3af7adc5974a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87336
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
---
 src/soc/mediatek/common/include/soc/mt6359p.h | 1 +
 src/soc/mediatek/common/mt6359p.c             | 2 +-
 2 files changed, 2 insertions(+), 1 deletion(-)

diff --git a/src/soc/mediatek/common/include/soc/mt6359p.h b/src/soc/mediatek/common/include/soc/mt6359p.h
index fa21eaa06d..b829eb6e83 100644
--- a/src/soc/mediatek/common/include/soc/mt6359p.h
+++ b/src/soc/mediatek/common/include/soc/mt6359p.h
@@ -88,6 +88,7 @@ void mt6359p_enable_vpa(bool enable);
 void mt6359p_enable_vsim1(bool enable);
 void mt6359p_enable_vm18(bool enable);
 void mt6359p_init_pmif_arb(void);
+u32 mt6359p_read_field(u32 reg, u32 mask, u32 shift);
 void mt6359p_write_field(u32 reg, u32 val, u32 mask, u32 shift);
 void mt6359p_init_setting(void);
 void mt6359p_lp_setting(void);
diff --git a/src/soc/mediatek/common/mt6359p.c b/src/soc/mediatek/common/mt6359p.c
index 530f4d1f87..6b09d57caa 100644
--- a/src/soc/mediatek/common/mt6359p.c
+++ b/src/soc/mediatek/common/mt6359p.c
@@ -50,7 +50,7 @@ static void mt6359p_write(u32 reg, u32 data)
 	pmif_arb->write(pmif_arb, 0, reg, data);
 }
 
-static u32 mt6359p_read_field(u32 reg, u32 mask, u32 shift)
+u32 mt6359p_read_field(u32 reg, u32 mask, u32 shift)
 {
 	return pmif_arb->read_field(pmif_arb, 0, reg, mask, shift);
 }

From 4c22c3d83e7fa68e706f4533685e983583c56b53 Mon Sep 17 00:00:00 2001
From: Jarried Lin <jarried.lin@mediatek.corp-partner.google.com>
Date: Tue, 15 Apr 2025 13:35:54 +0800
Subject: [PATCH 0767/3886] soc/mediatek/mt8196: Add DCC driver support in
 ramstage

Duty Cycle Correlation (DCC) analyzes and optimizes the relationship
between the duty cycles of multiple signals. This commit implements DCC
driver support to improve clock signals, power management, and
communication systems, enhancing system stability and performance.
These improvements will become more significant as the SoC ages.

BUG=b:389784352
BRANCH=rauru
TEST=Build pass, check dcc log:
[DEBUG]  [DCC] DSU=0x0, LCPU=0x0, MCPU=0x17, BCPU=0x1b

Change-Id: I77e5cd951f45dad7a6e2e77c135b821e4179e019
Signed-off-by: Jarried Lin <jarried.lin@mediatek.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87320
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
---
 src/soc/mediatek/mt8196/Makefile.mk       |  1 +
 src/soc/mediatek/mt8196/dcc.c             | 23 +++++++++++++++++++++++
 src/soc/mediatek/mt8196/include/soc/dcc.h | 15 +++++++++++++++
 src/soc/mediatek/mt8196/soc.c             |  2 ++
 4 files changed, 41 insertions(+)
 create mode 100644 src/soc/mediatek/mt8196/dcc.c
 create mode 100644 src/soc/mediatek/mt8196/include/soc/dcc.h

diff --git a/src/soc/mediatek/mt8196/Makefile.mk b/src/soc/mediatek/mt8196/Makefile.mk
index 9d05ee46ea..93be1b434b 100644
--- a/src/soc/mediatek/mt8196/Makefile.mk
+++ b/src/soc/mediatek/mt8196/Makefile.mk
@@ -55,6 +55,7 @@ romstage-y += thermal.c
 romstage-y += thermal_sram.c
 
 ramstage-$(CONFIG_ARM64_USE_ARM_TRUSTED_FIRMWARE) += ../common/bl31.c
+ramstage-y += dcc.c
 ramstage-y += ddp.c
 ramstage-y += ../common/display.c
 ramstage-y += ../common/dpm_v2.c
diff --git a/src/soc/mediatek/mt8196/dcc.c b/src/soc/mediatek/mt8196/dcc.c
new file mode 100644
index 0000000000..13a621c5b3
--- /dev/null
+++ b/src/soc/mediatek/mt8196/dcc.c
@@ -0,0 +1,23 @@
+/* SPDX-License-Identifier: GPL-2.0-only OR MIT */
+
+#include <console/console.h>
+#include <device/mmio.h>
+#include <soc/dcc.h>
+
+void dcc_init(void)
+{
+	/* DSU */
+	clrbits32p(BUS_PLLDIV_CFG1, GENMASK(20, 16));
+	/* LCPU */
+	clrbits32p(CPU_PLLDIV_0_CFG1, GENMASK(20, 16));
+	/* MCPU */
+	clrsetbits32p(CPU_PLLDIV_1_CFG1, GENMASK(20, 16), BIT(20) | GENMASK(18, 16));
+	/* BCPU */
+	clrsetbits32p(CPU_PLLDIV_2_CFG1, GENMASK(20, 16), GENMASK(17, 16) | GENMASK(20, 19));
+
+	printk(BIOS_DEBUG, "[DCC] DSU=%#x, LCPU=%#x, MCPU=%#x, BCPU=%#x\n",
+	       (read32p(BUS_PLLDIV_CFG1) >> 16) & 0x1F,
+	       (read32p(CPU_PLLDIV_0_CFG1) >> 16) & 0x1F,
+	       (read32p(CPU_PLLDIV_1_CFG1) >> 16) & 0x1F,
+	       (read32p(CPU_PLLDIV_2_CFG1) >> 16) & 0x1F);
+}
diff --git a/src/soc/mediatek/mt8196/include/soc/dcc.h b/src/soc/mediatek/mt8196/include/soc/dcc.h
new file mode 100644
index 0000000000..3aba1f1d1c
--- /dev/null
+++ b/src/soc/mediatek/mt8196/include/soc/dcc.h
@@ -0,0 +1,15 @@
+/* SPDX-License-Identifier: GPL-2.0-only OR MIT */
+
+#ifndef SOC_MEDIATEK_MT8196_DCC_H
+#define SOC_MEDIATEK_MT8196_DCC_H
+
+#include <soc/addressmap.h>
+
+#define BUS_PLLDIV_CFG1		(MCUSYS_BASE + 0x0104) /* DSU */
+#define CPU_PLLDIV_0_CFG1	(MCUSYS_BASE + 0x0110) /* LCPU */
+#define CPU_PLLDIV_1_CFG1	(MCUSYS_BASE + 0x011C) /* MCPU */
+#define CPU_PLLDIV_2_CFG1	(MCUSYS_BASE + 0x0128) /* BCPU */
+
+void dcc_init(void);
+
+#endif /* SOC_MEDIATEK_MT8196_DCC_H */
diff --git a/src/soc/mediatek/mt8196/soc.c b/src/soc/mediatek/mt8196/soc.c
index 2d32bc3d45..c5a83d0c73 100644
--- a/src/soc/mediatek/mt8196/soc.c
+++ b/src/soc/mediatek/mt8196/soc.c
@@ -3,6 +3,7 @@
 #include <bootmem.h>
 #include <device/device.h>
 #include <device/pci.h>
+#include <soc/dcc.h>
 #include <soc/dramc_info.h>
 #include <soc/emi.h>
 #include <soc/gpueb.h>
@@ -52,6 +53,7 @@ static void soc_init(struct device *dev)
 {
 	uint32_t storage_type = mainboard_get_storage_type();
 
+	dcc_init();
 	mtk_fsp_init(RAMSTAGE_SOC_INIT);
 	mtk_fsp_add_param(FSP_PARAM_TYPE_STORAGE, sizeof(storage_type), &storage_type);
 	add_pi_image_params();

From 6f2a01f7431ed49671c77b5880863d5e0350fb8a Mon Sep 17 00:00:00 2001
From: Maximilian Brune <maximilian.brune@9elements.com>
Date: Sat, 8 Mar 2025 23:23:18 +0100
Subject: [PATCH 0768/3886] include/fmap.h: Require FMAP_SECTION_FLASH_START ==
 0

For simplicity we are going to impose this restriction to coreboot.
Note however that this is only a restriction for coreboot itself. The
FMAP tool itself is still a generic tool that does not require the FMAP
to start at offset 0.

Add an defacto empty fmap_config.h to our test cases, since fmap.h now
includes fmap_config.h.

Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: Iba04ebdcd5557664a865d2854028dd811f052249
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86770
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jakub "Kuba" Czapiga <czapiga@google.com>
---
 src/include/fmap.h                    |  5 +++++
 tests/include/tests/lib/fmap_config.h | 12 ++++++++++++
 tests/lib/Makefile.mk                 |  4 ++++
 3 files changed, 21 insertions(+)
 create mode 100644 tests/include/tests/lib/fmap_config.h

diff --git a/src/include/fmap.h b/src/include/fmap.h
index 761e742f56..fc49dbdf5e 100644
--- a/src/include/fmap.h
+++ b/src/include/fmap.h
@@ -5,9 +5,14 @@
 
 #include <commonlib/bsd/fmap_serialized.h>
 #include <commonlib/region.h>
+#include <fmap_config.h>
 #include <stddef.h>
 #include <stdint.h>
 
+#if FMAP_SECTION_FLASH_START != 0
+	#error "FMAP must always start flash address 0"
+#endif
+
 /* Locate the named area in the fmap and fill in a region device representing
  * that area. The region is a sub-region of the readonly boot media. Return
  * 0 on success, < 0 on error. */
diff --git a/tests/include/tests/lib/fmap_config.h b/tests/include/tests/lib/fmap_config.h
new file mode 100644
index 0000000000..5b3540020b
--- /dev/null
+++ b/tests/include/tests/lib/fmap_config.h
@@ -0,0 +1,12 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef FMAPTOOL_GENERATED_HEADER_H_
+#define FMAPTOOL_GENERATED_HEADER_H_
+
+/*
+ * This file is used for tests that include (directly as well as indirectly) fmap.h.
+ * Keeps the build tests from failing since fmap.h needs fmap_config.h
+ */
+#define FMAP_SECTION_FLASH_START 0
+
+#endif
diff --git a/tests/lib/Makefile.mk b/tests/lib/Makefile.mk
index 1a96c7d620..31603cdf03 100644
--- a/tests/lib/Makefile.mk
+++ b/tests/lib/Makefile.mk
@@ -163,6 +163,7 @@ spd_cache-ddr3-test-config += CONFIG_SPD_CACHE_FMAP_NAME=\"RW_SPD_CACHE\" \
 				CONFIG_DIMM_MAX=4 CONFIG_DIMM_SPD_SIZE=256 \
 				CONFIG_BOOT_DEVICE_MEMORY_MAPPED=1
 spd_cache-ddr3-test-cflags += -D__TEST_SPD_CACHE_DDR=3
+spd_cache-ddr3-test-cflags += -I tests/include/tests/lib/fmap
 
 spd_cache-ddr4-test-srcs += tests/lib/spd_cache-test.c
 spd_cache-ddr4-test-srcs += tests/stubs/console.c
@@ -174,6 +175,7 @@ spd_cache-ddr4-test-config += CONFIG_SPD_CACHE_FMAP_NAME=\"RW_SPD_CACHE\" \
 				CONFIG_DIMM_MAX=4 CONFIG_DIMM_SPD_SIZE=512 \
 				CONFIG_BOOT_DEVICE_MEMORY_MAPPED=1
 spd_cache-ddr4-test-cflags += -D__TEST_SPD_CACHE_DDR=4
+spd_cache-ddr4-test-cflags += -I tests/include/tests/lib/fmap
 
 cbmem_stage_cache-test-srcs += tests/lib/cbmem_stage_cache-test.c
 cbmem_stage_cache-test-srcs += tests/stubs/console.c
@@ -201,6 +203,7 @@ cbfs-verification-no-sha512-test-config += CONFIG_COLLECT_TIMESTAMPS=0 \
 					CONFIG_CBFS_VERIFICATION=1 \
 					CONFIG_NO_CBFS_MCACHE=1 \
 					VB2_SUPPORT_SHA512=0
+cbfs-verification-no-sha512-test-cflags += -I tests/include/tests/lib/fmap
 
 $(call copy-test,cbfs-verification-no-sha512-test,cbfs-verification-has-sha512-test)
 cbfs-verification-has-sha512-test-config += VB2_SUPPORT_SHA512=1
@@ -229,6 +232,7 @@ cbfs-lookup-no-mcache-test-mocks += cbfs_get_boot_device \
 cbfs-lookup-no-mcache-test-config += CONFIG_ARCH_X86=0 \
 				CONFIG_COLLECT_TIMESTAMPS=0 \
 				CONFIG_NO_CBFS_MCACHE=1
+cbfs-lookup-no-mcache-test-cflags += -I tests/include/tests/lib/fmap
 
 $(call copy-test,cbfs-lookup-no-mcache-test,cbfs-lookup-has-mcache-test)
 cbfs-lookup-has-mcache-test-config += CONFIG_NO_CBFS_MCACHE=0

From 2efe4df5227a1d7b6bf32b2f6611a1ef125c4b25 Mon Sep 17 00:00:00 2001
From: Maximilian Brune <maximilian.brune@9elements.com>
Date: Sun, 9 Mar 2025 00:02:00 +0100
Subject: [PATCH 0769/3886] treewide: Assume FMAP_SECTION_FLASH_START = 0

Now that we require the FMAP to start at offset 0 in the flash, we can
assume this across the entire codebase and therefore simplify it on
several ends.

Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: Ieb1a23f9c0ae8c0e1c91287d7eb6f7f0abbf0c2c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86771
Reviewed-by: Erik van den Bogaert <ebogaert@eltan.com>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
---
 src/arch/x86/walkcbfs.S                                |  4 ----
 src/lib/cbfs_master_header.c                           |  5 ++---
 src/lib/master_header_pointer.c                        |  4 ----
 src/soc/amd/common/Makefile.mk                         |  4 +---
 src/soc/intel/common/block/fast_spi/Makefile.mk        |  2 --
 src/southbridge/amd/pi/hudson/Makefile.mk              |  4 ++--
 .../eltan/security/verified_boot/vboot_check.c         |  4 ----
 tests/lib/fmap-test.c                                  |  2 +-
 util/amdfwtool/opts.c                                  | 10 ----------
 9 files changed, 6 insertions(+), 33 deletions(-)

diff --git a/src/arch/x86/walkcbfs.S b/src/arch/x86/walkcbfs.S
index a017ee1e5c..37eab33161 100644
--- a/src/arch/x86/walkcbfs.S
+++ b/src/arch/x86/walkcbfs.S
@@ -17,11 +17,7 @@
 
 #define CBFS_FILE_STRUCTSIZE (CBFS_FILE_OFFSET + 4)
 
-#if FMAP_SECTION_COREBOOT_START < (0xffffffff - CONFIG_ROM_SIZE + 1)
 #define COREBOOT_CBFS_START (0xffffffff - CONFIG_ROM_SIZE + 1 + FMAP_SECTION_COREBOOT_START)
-#else
-#define COREBOOT_CBFS_START FMAP_SECTION_COREBOOT_START
-#endif
 
 .code32
 .section .init
diff --git a/src/lib/cbfs_master_header.c b/src/lib/cbfs_master_header.c
index d358d1a37d..41bba01353 100644
--- a/src/lib/cbfs_master_header.c
+++ b/src/lib/cbfs_master_header.c
@@ -14,8 +14,7 @@ struct cbfs_header header = {
 	 * representing the CBFS region's size is added to the offset of
 	 * the region within a larger image.
 	 */
-	.romsize = cpu_to_be32(FMAP_SECTION_COREBOOT_START + FMAP_SECTION_COREBOOT_SIZE
-			       - FMAP_SECTION_FLASH_START),
+	.romsize = cpu_to_be32(FMAP_SECTION_COREBOOT_START + FMAP_SECTION_COREBOOT_SIZE),
 	/*
 	 * The 4 bytes are left out for two reasons:
 	 * 1. the cbfs master header pointer resides there
@@ -25,6 +24,6 @@ struct cbfs_header header = {
 	 */
 	.bootblocksize = cpu_to_be32(4),
 	.align = cpu_to_be32(CBFS_ALIGNMENT),
-	.offset = cpu_to_be32(FMAP_SECTION_COREBOOT_START - FMAP_SECTION_FLASH_START),
+	.offset = cpu_to_be32(FMAP_SECTION_COREBOOT_START),
 	.architecture = cpu_to_be32(CBFS_ARCHITECTURE_UNKNOWN),
 };
diff --git a/src/lib/master_header_pointer.c b/src/lib/master_header_pointer.c
index b2c3fe64ef..f73cc2997e 100644
--- a/src/lib/master_header_pointer.c
+++ b/src/lib/master_header_pointer.c
@@ -9,11 +9,7 @@
 __attribute__((used, __section__(".header_pointer")))
 #endif
 
-#if FMAP_SECTION_COREBOOT_START < (0xffffffff - CONFIG_ROM_SIZE + 1)
 #define COREBOOT_CBFS_START (0xffffffff - CONFIG_ROM_SIZE + 1 + FMAP_SECTION_COREBOOT_START)
-#else
-#define COREBOOT_CBFS_START FMAP_SECTION_COREBOOT_START
-#endif
 
 uint32_t header_pointer =
 	cpu_to_le32(COREBOOT_CBFS_START + ALIGN_UP(sizeof(struct cbfs_file)
diff --git a/src/soc/amd/common/Makefile.mk b/src/soc/amd/common/Makefile.mk
index a030687817..db60c01b87 100644
--- a/src/soc/amd/common/Makefile.mk
+++ b/src/soc/amd/common/Makefile.mk
@@ -45,9 +45,7 @@ $(objcbfs)/bootblock.bin: $(obj)/amdfw.rom $(obj)/fmap_config.h
 amdfw_region_start=$(subst $(spc),,FMAP_SECTION_$(call regions-for-file,apu/amdfw)_START)
 amdfw_offset=$(call int-subtract, \
 	$(CONFIG_AMD_FWM_POSITION) \
-	$(call int-subtract, \
-	$(call get_fmap_value,$(amdfw_region_start)) \
-	$(call get_fmap_value,FMAP_SECTION_FLASH_START)))
+	$(call get_fmap_value,$(amdfw_region_start)))
 
 add_bootblock = \
 	$(CBFSTOOL) $(1) add -f $(2) -n apu/amdfw -t amdfw \
diff --git a/src/soc/intel/common/block/fast_spi/Makefile.mk b/src/soc/intel/common/block/fast_spi/Makefile.mk
index ddf15748ae..6e274df69f 100644
--- a/src/soc/intel/common/block/fast_spi/Makefile.mk
+++ b/src/soc/intel/common/block/fast_spi/Makefile.mk
@@ -45,7 +45,6 @@ smm-y += mmap_boot.c
 $(call add_intermediate, check-fmap-16mib-crossing, $(obj)/fmap_config.h)
 	fmap_get() { awk "/$$1/ { print \$$NF }" < $<; };		\
 									\
-	flash_offset=$$(fmap_get FMAP_SECTION_FLASH_START);		\
 	flash_size=$$(fmap_get FMAP_SECTION_FLASH_SIZE);		\
 	if [ $$((flash_size)) -le $$((0x1000000)) ]; then		\
 	   exit;							\
@@ -55,7 +54,6 @@ $(call add_intermediate, check-fmap-16mib-crossing, $(obj)/fmap_config.h)
 	do								\
 	    start=$$(fmap_get "FMAP_SECTION_$${x}_START");		\
 	    size=$$(fmap_get "FMAP_SECTION_$${x}_SIZE");		\
-	    start=$$((start-flash_offset));				\
 	    end=$$((start+size-1));					\
 	    if [ $$((start)) -lt $$((bios_16M_boundary)) ] &&		\
 			[ $$((end)) -ge $$((bios_16M_boundary)) ];	\
diff --git a/src/southbridge/amd/pi/hudson/Makefile.mk b/src/southbridge/amd/pi/hudson/Makefile.mk
index e7ec1b73ec..9d71df5efc 100644
--- a/src/southbridge/amd/pi/hudson/Makefile.mk
+++ b/src/southbridge/amd/pi/hudson/Makefile.mk
@@ -48,9 +48,9 @@ CPPFLAGS_common += -I$(src)/southbridge/amd/pi/hudson/include
 # EC ROM should be 64K aligned.
 
 ifeq ($(CONFIG_AMDFW_OUTSIDE_CBFS),y)
-HUDSON_FWM_POSITION=$(call int-add, $(call int-subtract, 0xffffffff $(CONFIG_ROM_SIZE)) 0x20000 1)
+HUDSON_FWM_POSITION=0x20000
 else
-HUDSON_FWM_POSITION=0xfff20000
+HUDSON_FWM_POSITION=0x720000
 endif
 
 ifeq ($(CONFIG_HUDSON_PSP), y)
diff --git a/src/vendorcode/eltan/security/verified_boot/vboot_check.c b/src/vendorcode/eltan/security/verified_boot/vboot_check.c
index 62c60f7b5d..5ac002c6b1 100644
--- a/src/vendorcode/eltan/security/verified_boot/vboot_check.c
+++ b/src/vendorcode/eltan/security/verified_boot/vboot_check.c
@@ -184,11 +184,7 @@ static void verified_boot_check_buffer(const char *name, void *start, size_t siz
 	}
 }
 
-#if FMAP_SECTION_COREBOOT_START < (0xffffffff - CONFIG_ROM_SIZE + 1)
 #define COREBOOT_CBFS_START (0xffffffff - CONFIG_ROM_SIZE + 1 + FMAP_SECTION_COREBOOT_START)
-#else
-#define COREBOOT_CBFS_START FMAP_SECTION_COREBOOT_START
-#endif
 
 void verified_boot_check_cbfsfile(const char *name, uint32_t type, uint32_t hash_index,
 				  void **buffer, uint32_t *filesize, int32_t pcr)
diff --git a/tests/lib/fmap-test.c b/tests/lib/fmap-test.c
index 1cc8246b4b..d6dcd67bed 100644
--- a/tests/lib/fmap-test.c
+++ b/tests/lib/fmap-test.c
@@ -204,7 +204,7 @@ static void test_fmap_find_region_name(void **state)
 	assert_int_equal(-1, fmap_find_region_name(NULL, found_area_name));
 
 	/* Try to find area outside of flash region */
-	ar.offset = FMAP_SECTION_FLASH_START + FMAP_SECTION_FLASH_SIZE + 0x100;
+	ar.offset = FMAP_SECTION_FLASH_SIZE + 0x100;
 	ar.size = 0x1000;
 	assert_int_equal(-1, fmap_find_region_name(&ar, found_area_name));
 
diff --git a/util/amdfwtool/opts.c b/util/amdfwtool/opts.c
index 5d1ee6754d..15bc7ca3a5 100644
--- a/util/amdfwtool/opts.c
+++ b/util/amdfwtool/opts.c
@@ -639,16 +639,6 @@ int amdfwtool_getopt(int argc, char *argv[], amd_cb_config *cb_config, context *
 
 	printf("    AMDFWTOOL  Using ROM size of %dKB\n", ctx->rom_size / 1024);
 
-	if (ctx->rom_size <= MAX_MAPPED_WINDOW) {
-		uint32_t rom_base_address;
-
-		rom_base_address = 0xFFFFFFFF - ctx->rom_size + 1;
-		if (cb_config->efs_location & ~MAX_MAPPED_WINDOW_MASK)
-			cb_config->efs_location = cb_config->efs_location - rom_base_address;
-		if (cb_config->body_location & ~MAX_MAPPED_WINDOW_MASK)
-			cb_config->body_location = cb_config->body_location - rom_base_address;
-	}
-
 	/* If the flash size is larger than 16M, we assume the given
 	   addresses are already relative ones. Otherwise we print error.*/
 	if (cb_config->efs_location && cb_config->efs_location > ctx->rom_size) {

From 08d15e1ea132537f6364a9814f51ad066f5e31a4 Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Fri, 4 Apr 2025 11:37:58 +0100
Subject: [PATCH 0770/3886] mb/starlabs/starfighter: Reconfigure PCH Strap
 GPIOs

Configure all strap GPIOs as outputs, rather than some being not
connected. This doesn't change anything, but is more explicit.

Set these all to sample on RSMRST.

Change-Id: I3f7133666743b8aa0dc39df54ffe3483a1ddd605
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87162
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 .../starlabs/starfighter/variants/rpl/gpio.c  | 35 ++++++-------------
 1 file changed, 11 insertions(+), 24 deletions(-)

diff --git a/src/mainboard/starlabs/starfighter/variants/rpl/gpio.c b/src/mainboard/starlabs/starfighter/variants/rpl/gpio.c
index 85970a16b3..b4cff02b06 100644
--- a/src/mainboard/starlabs/starfighter/variants/rpl/gpio.c
+++ b/src/mainboard/starlabs/starfighter/variants/rpl/gpio.c
@@ -103,12 +103,21 @@ const struct pad_config gpio_table[] = {
 	PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1),				/* Data */
 	PAD_CFG_GPO(GPP_E8, 1, DEEP),					/* DRAM Sleep */
 
+	/* Config Straps 									[ Low      / High     ] */
+	PAD_CFG_GPO(GPP_B14, 0, RSMRST),				/* Top Swap		[ Disabled / Enabled  ] */
+	PAD_CFG_GPO(GPP_B18, 0, RSMRST),				/* Reboot Support	[ Enabled  / Disabled ] */
+	PAD_CFG_GPO(GPP_C2, 1, RSMRST),					/* TLS Confidentiality	[ Disabled / Enabled  ] */
+	PAD_CFG_GPO(GPP_C5, 0, RSMRST),					/* eSPI			[ Enabled  / Disabled ] */
+	PAD_CFG_GPO(GPP_E6, 0, RSMRST),					/* JTAG ODT		[ Disabled / Enabled  ] */
+	PAD_CFG_GPO(GPP_H1, 0, RSMRST),					/* BFX Strap 2 Bit 3	[ Disabled / Enabled  ] */
+	PAD_CFG_GPO(GPP_F2, 1, RSMRST),					/* M.2 CNVi		[ Enabled  / Disabled ] */
+	PAD_CFG_GPO(GPP_F7, 0, RSMRST),					/* MCRO LDO		[ Disabled / Bypass   ] */
+	PAD_CFG_GPO(GPD7, 0, RSMRST),					/* RTC Clock Delay	[ Disabled / 95ms     ] */
+
 	/* GPD2:	LAN Wake					*/
 	PAD_NC(GPD2, NONE),
 	/* GPD6:	Sleep A						*/
 	PAD_NC(GPD6, NONE),
-	/* GPD7:	Power Adapter Disable				*/
-	PAD_CFG_GPO(GPD7, 0, PWROK),
 	/* GPD9:	Wireless LAN Sleep				*/
 	PAD_CFG_NF(GPD9, NONE, DEEP, NF1),
 	/* GPD10:	Sleep S5					*/
@@ -165,16 +174,12 @@ const struct pad_config gpio_table[] = {
 	PAD_NC(GPP_B10, NONE),
 	/* B12:		PM SLP S0					*/
 	PAD_NC(GPP_B12, NONE),
-	/* B14:		Not Connected					*/
-	PAD_NC(GPP_B14, NONE),
 	/* B15:		Not Connected					*/
 	PAD_NC(GPP_B15, NONE),
 	/* B16:		Not Connected					*/
 	PAD_NC(GPP_B16, NONE),
 	/* B17:		Not Connected					*/
 	PAD_NC(GPP_B17, NONE),
-	/* B18:		Not Connected					*/
-	PAD_NC(GPP_B18, NONE),
 	/* B19:		Not Connected					*/
 	PAD_NC(GPP_B19, NONE),
 	/* B20:		Not Connected					*/
@@ -190,18 +195,10 @@ const struct pad_config gpio_table[] = {
 	/* B25:		Not Connected					*/
 	PAD_NC(GPP_B25, NONE),
 
-	/* C2:		TLS Confidentiality	Weak Internal PD 20K
-				Low:	Disabled
-				High:	Enabled				*/
-	PAD_CFG_GPO(GPP_C2, 1, PLTRST),
 	/* C3:		SML 0 Clock					*/
 	PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1),
 	/* C4:		SML 0 Data					*/
 	PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1),
-	/* C5:		Boot Strap		Weak Internal PD 20K
-				Low:	ESPI
-				High:	Disabled			*/
-	PAD_CFG_GPO(GPP_C5, 0, DEEP),
 	/* C8:		Not Connected					*/
 	PAD_NC(GPP_C8, NONE),
 	/* C9:		Not Connected					*/
@@ -272,10 +269,6 @@ const struct pad_config gpio_table[] = {
 	PAD_NC(GPP_E2, NONE),
 	/* E5:		Not Connected					*/
 	PAD_NC(GPP_E5, NONE),
-	/* E6:		JTAG ODT		No internal PD
-				Low:	Disabled
-				High:	Enabled				*/
-	PAD_CFG_GPO(GPP_E6, 0, DEEP),
 	/* E7:		Embedded Controller SMI				*/
 	PAD_NC(GPP_E7, NONE),
 	/* E9:		USB OverCurrent 0				*/
@@ -313,10 +306,6 @@ const struct pad_config gpio_table[] = {
 	PAD_NC(GPP_F5, NONE),
 	/* F6:		Not used					*/
 	PAD_NC(GPP_F6, NONE),
-	/* F7:		TBT LSX VCCIO		Weak Internal PD 20K
-				Low:	1.8V
-				High:	3.3V				*/
-	PAD_CFG_GPO(GPP_F7, 0, DEEP),
 	/* F8:		Not Connected					*/
 	PAD_NC(GPP_F8, NONE),
 	/* F9:		EC Sleep S0					*/
@@ -340,8 +329,6 @@ const struct pad_config gpio_table[] = {
 	/* F23:		Not Connected					*/
 	PAD_NC(GPP_F23, NONE),
 
-	/* H1:		BFX Strap 2 Bit 3	Weak Internal PD 20K	*/
-	PAD_CFG_GPO(GPP_H1, 0, DEEP),
 	/* H3:		Not Connected					*/
 	PAD_NC(GPP_H3, NONE),
 	/* H6:		Not Connected					*/

From 1bfad8c22cb7ec570976f6680dc0cd2dfd7e84ec Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Fri, 4 Apr 2025 11:44:49 +0100
Subject: [PATCH 0771/3886] mb/starlabs/starfighter: Disconnect unused GPIOs

These GPIOs are not used, so configure them accordingly.

Change-Id: I4e58a0e7545167db2c4034499bb99d3bfffc2277
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87164
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/starlabs/starfighter/variants/rpl/gpio.c | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/src/mainboard/starlabs/starfighter/variants/rpl/gpio.c b/src/mainboard/starlabs/starfighter/variants/rpl/gpio.c
index b4cff02b06..72d007213c 100644
--- a/src/mainboard/starlabs/starfighter/variants/rpl/gpio.c
+++ b/src/mainboard/starlabs/starfighter/variants/rpl/gpio.c
@@ -119,7 +119,7 @@ const struct pad_config gpio_table[] = {
 	/* GPD6:	Sleep A						*/
 	PAD_NC(GPD6, NONE),
 	/* GPD9:	Wireless LAN Sleep				*/
-	PAD_CFG_NF(GPD9, NONE, DEEP, NF1),
+	PAD_NC(GPD9, NONE),
 	/* GPD10:	Sleep S5					*/
 	PAD_NC(GPD10, NONE),
 	/* GPD11:	LAN PHY Enable					*/
@@ -196,9 +196,9 @@ const struct pad_config gpio_table[] = {
 	PAD_NC(GPP_B25, NONE),
 
 	/* C3:		SML 0 Clock					*/
-	PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1),
+	PAD_NC(GPP_C3, NONE),
 	/* C4:		SML 0 Data					*/
-	PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1),
+	PAD_NC(GPP_C4, NONE),
 	/* C8:		Not Connected					*/
 	PAD_NC(GPP_C8, NONE),
 	/* C9:		Not Connected					*/
@@ -311,7 +311,7 @@ const struct pad_config gpio_table[] = {
 	/* F9:		EC Sleep S0					*/
 	PAD_NC(GPP_F9, NONE),
 	/* F10:		Weak Internal PD 20K				*/
-	PAD_CFG_GPO(GPP_F10, 0, PLTRST),
+	PAD_NC(GPP_F10, NONE),
 	/* F11:		TPM ID						*/
 	PAD_NC(GPP_F11, NONE),
 	/* F16:		Not Connected					*/

From dd4ccb60441fff227efc5650025cb94e4cfcbcd1 Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Fri, 4 Apr 2025 11:48:13 +0100
Subject: [PATCH 0772/3886] mb/starlabs/starfighter: Remove comments for
 disconnected GPIOs

Change-Id: Ia609053b61937a2da01e99b13adb4b964f3ae2ad
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87165
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 .../starlabs/starfighter/variants/rpl/gpio.c  | 145 ------------------
 1 file changed, 145 deletions(-)

diff --git a/src/mainboard/starlabs/starfighter/variants/rpl/gpio.c b/src/mainboard/starlabs/starfighter/variants/rpl/gpio.c
index 72d007213c..c506789ff4 100644
--- a/src/mainboard/starlabs/starfighter/variants/rpl/gpio.c
+++ b/src/mainboard/starlabs/starfighter/variants/rpl/gpio.c
@@ -114,303 +114,158 @@ const struct pad_config gpio_table[] = {
 	PAD_CFG_GPO(GPP_F7, 0, RSMRST),					/* MCRO LDO		[ Disabled / Bypass   ] */
 	PAD_CFG_GPO(GPD7, 0, RSMRST),					/* RTC Clock Delay	[ Disabled / 95ms     ] */
 
-	/* GPD2:	LAN Wake					*/
 	PAD_NC(GPD2, NONE),
-	/* GPD6:	Sleep A						*/
 	PAD_NC(GPD6, NONE),
-	/* GPD9:	Wireless LAN Sleep				*/
 	PAD_NC(GPD9, NONE),
-	/* GPD10:	Sleep S5					*/
 	PAD_NC(GPD10, NONE),
-	/* GPD11:	LAN PHY Enable					*/
 	PAD_NC(GPD11, NONE),
 
-	/* A5:		Not Connected					*/
-	PAD_NC(GPP_A5, NONE),
-	/* A6:		Not Connected					*/
 	PAD_NC(GPP_A6, NONE),
-	/* A7:		Embedded Controller SCI				*/
 	PAD_NC(GPP_A7, NONE),
-	/* A8:		Not Connected					*/
 	PAD_NC(GPP_A8, NONE),
-	/* A11:		Not Connected					*/
 	PAD_NC(GPP_A11, NONE),
-	/* A12:		PCH M.2 SSD PEDET				*/
 	PAD_NC(GPP_A12, NONE),
-	/* A14:		Test Point 45					*/
 	PAD_NC(GPP_A14, NONE),
-	/* A15:		Test Point 52					*/
 	PAD_NC(GPP_A15, NONE),
-	/* A16:		USB OverCurrent 3				*/
 	PAD_NC(GPP_A16, NONE),
-	/* A17:		Not Connected					*/
 	PAD_NC(GPP_A17, NONE),
-	/* A19:		Not Connected					*/
 	PAD_NC(GPP_A19, NONE),
-	/* A20:		Test Point 44					*/
 	PAD_NC(GPP_A20, NONE),
-	/* A21:		Not Connected					*/
 	PAD_NC(GPP_A21, NONE),
-	/* A22:		Not Connected					*/
 	PAD_NC(GPP_A22, NONE),
-	/* A23:		Not Connected					*/
 	PAD_NC(GPP_A23, NONE),
 
-	/* B3:		Not Connected					*/
 	PAD_NC(GPP_B3, NONE),
-	/* B4:		Not Connected					*/
 	PAD_NC(GPP_B4, NONE),
-	/* B5:		I2C 2 SDA		Touch Panel SDA		*/
 	PAD_NC(GPP_B5, NONE),
-	/* B6:		I2C 2 SCL		Touch Panel Clock	*/
 	PAD_NC(GPP_B6, NONE),
-	/* B7:		I2C 3 SDA		Test Point 15		*/
 	PAD_NC(GPP_B7, NONE),
-	/* B8:		I2C 3 SCL		Test Point 16		*/
 	PAD_NC(GPP_B8, NONE),
-	/* B9:		Not Connected					*/
 	PAD_NC(GPP_B9, NONE),
-	/* B10:		Not Connected					*/
 	PAD_NC(GPP_B10, NONE),
-	/* B12:		PM SLP S0					*/
 	PAD_NC(GPP_B12, NONE),
-	/* B15:		Not Connected					*/
 	PAD_NC(GPP_B15, NONE),
-	/* B16:		Not Connected					*/
 	PAD_NC(GPP_B16, NONE),
-	/* B17:		Not Connected					*/
 	PAD_NC(GPP_B17, NONE),
-	/* B19:		Not Connected					*/
 	PAD_NC(GPP_B19, NONE),
-	/* B20:		Not Connected					*/
 	PAD_NC(GPP_B20, NONE),
-	/* B21:		Not Connected					*/
 	PAD_NC(GPP_B21, NONE),
-	/* B22:		Not Connected					*/
 	PAD_NC(GPP_B22, NONE),
-	/* B23:		Not Connected					*/
 	PAD_NC(GPP_B23, NONE),
-	/* B24:		Not Connected					*/
 	PAD_NC(GPP_B24, NONE),
-	/* B25:		Not Connected					*/
 	PAD_NC(GPP_B25, NONE),
 
-	/* C3:		SML 0 Clock					*/
 	PAD_NC(GPP_C3, NONE),
-	/* C4:		SML 0 Data					*/
 	PAD_NC(GPP_C4, NONE),
-	/* C8:		Not Connected					*/
 	PAD_NC(GPP_C8, NONE),
-	/* C9:		Not Connected					*/
 	PAD_NC(GPP_C9, NONE),
-	/* C10:		Not Connected					*/
 	PAD_NC(GPP_C10, NONE),
-	/* C11:		Not Connected					*/
 	PAD_NC(GPP_C11, NONE),
-	/* C12:		Not Connected					*/
 	PAD_NC(GPP_C12, NONE),
-	/* C13:		Not Connected					*/
 	PAD_NC(GPP_C13, NONE),
-	/* C14:		Not Connected					*/
 	PAD_NC(GPP_C14, NONE),
-	/* C15:		Not Connected					*/
 	PAD_NC(GPP_C15, NONE),
-	/* C16:		Not Connected					*/
 	PAD_NC(GPP_C16, NONE),
-	/* C17:		Not Connected					*/
 	PAD_NC(GPP_C17, NONE),
-	/* C18:		Not Connected					*/
 	PAD_NC(GPP_C18, NONE),
-	/* C19:		Not Connected					*/
 	PAD_NC(GPP_C19, NONE),
-	/* C20:		Not Connected					*/
 	PAD_NC(GPP_C20, NONE),
-	/* C21:		Not Connected					*/
 	PAD_NC(GPP_C21, NONE),
-	/* C22:		Not Connected					*/
 	PAD_NC(GPP_C22, NONE),
-	/* C23:		Not Connected					*/
 	PAD_NC(GPP_C23, NONE),
 
-	/* D0:		Not used		Audio ID 0		*/
 	PAD_NC(GPP_D0, NONE),
-	/* D1:		Not used		Audio ID 1		*/
 	PAD_NC(GPP_D1, NONE),
-	/* D2:		Not used		Audio ID 2		*/
 	PAD_NC(GPP_D2, NONE),
-	/* D3:		Not Connected					*/
 	PAD_NC(GPP_D3, NONE),
-	/* D4:		Not Connected					*/
 	PAD_NC(GPP_D4, NONE),
-	/* D5:		Clock Request 0					*/
 	PAD_NC(GPP_D5, NONE),
-	/* D8:		Clock Request 3		LAN			*/
 	PAD_NC(GPP_D8, NONE),
-	/* D9:		PWD_AMP_IN					*/
 	PAD_NC(GPP_D9, NONE),
-	/* D12:		ES8336_INT_N					*/
 	PAD_NC(GPP_D12, NONE),
-	/* D13:		Wireless LAN Wake				*/
 	PAD_NC(GPP_D13, NONE),
-	/* D15:		Not Connected					*/
 	PAD_NC(GPP_D15, NONE),
-	/* D17:		Not used		Fingerprint ID		*/
 	PAD_NC(GPP_D17, NONE),
-	/* D18:		Trackpad reset					*/
 	PAD_NC(GPP_D18, NONE),
-	/* D19:		I2S_MCLK1_OUT					*/
 	PAD_NC(GPP_D19, NONE),
 
-	/* E0:		SATA x PCIe					*/
 	PAD_NC(GPP_E0, NONE),
-	/* E1:		Not Connected					*/
 	PAD_NC(GPP_E1, NONE),
-	/* E2:		Not Connected					*/
 	PAD_NC(GPP_E2, NONE),
-	/* E5:		Not Connected					*/
 	PAD_NC(GPP_E5, NONE),
-	/* E7:		Embedded Controller SMI				*/
 	PAD_NC(GPP_E7, NONE),
-	/* E9:		USB OverCurrent 0				*/
 	PAD_NC(GPP_E9, NONE),
-	/* E10:		Not Connected					*/
 	PAD_NC(GPP_E10, NONE),
-	/* E11:		Not Connected					*/
 	PAD_NC(GPP_E11, NONE),
-	/* E12:		Not Connected					*/
 	PAD_NC(GPP_E12, NONE),
-	/* E13:		Not connected					*/
 	PAD_NC(GPP_E13, NONE),
-	/* E15:		Not Connected					*/
 	PAD_NC(GPP_E15, NONE),
-	/* E16:		Not Connected					*/
 	PAD_NC(GPP_E16, NONE),
-	/* E17:		Not Connected					*/
 	PAD_NC(GPP_E17, NONE),
-	/* E22:		Not Connected					*/
 	PAD_NC(GPP_E22, NONE),
-	/* E23:		Not Connected					*/
 	PAD_NC(GPP_E23, NONE),
 
-	/* F0:		CNV BRI Data					*/
 	PAD_NC(GPP_F0, NONE),
-	/* F1:		CNV BRI Response				*/
 	PAD_NC(GPP_F1, NONE),
-	/* F2:		CNV RGI Data					*/
 	PAD_NC(GPP_F2, NONE),
-	/* F3:		CNV RGI Response				*/
 	PAD_NC(GPP_F3, NONE),
-	/* F4:		CNV RF Reset					*/
 	PAD_NC(GPP_F4, NONE),
-	/* F5:		Not used					*/
 	PAD_NC(GPP_F5, NONE),
-	/* F6:		Not used					*/
 	PAD_NC(GPP_F6, NONE),
-	/* F8:		Not Connected					*/
 	PAD_NC(GPP_F8, NONE),
-	/* F9:		EC Sleep S0					*/
 	PAD_NC(GPP_F9, NONE),
-	/* F10:		Weak Internal PD 20K				*/
 	PAD_NC(GPP_F10, NONE),
-	/* F11:		TPM ID						*/
 	PAD_NC(GPP_F11, NONE),
-	/* F16:		Not Connected					*/
 	PAD_NC(GPP_F16, NONE),
-	/* F17:		Not used		Touch Panel Reset	*/
 	PAD_NC(GPP_F17, NONE),
-	/* F18:		Not used		Touch Panel Interrupt	*/
 	PAD_NC(GPP_F18, NONE),
-	/* F19:		Not Connected					*/
 	PAD_NC(GPP_F19, NONE),
-	/* F21:		GPPC_F21					*/
 	PAD_NC(GPP_F21, NONE),
-	/* F22:		Not Connected					*/
 	PAD_NC(GPP_F22, NONE),
-	/* F23:		Not Connected					*/
 	PAD_NC(GPP_F23, NONE),
 
-	/* H3:		Not Connected					*/
 	PAD_NC(GPP_H3, NONE),
-	/* H6:		Not Connected					*/
 	PAD_NC(GPP_H6, NONE),
-	/* H7:		Not Connected					*/
 	PAD_NC(GPP_H7, NONE),
-	/* H8:		Not Connected					*/
 	PAD_NC(GPP_H8, NONE),
-	/* H9:		Not Connected					*/
 	PAD_NC(GPP_H9, NONE),
-	/* H12:		Not Connected					*/
 	PAD_NC(GPP_H12, NONE),
-	/* H13:		PCH M.2 SSD Device Sleep			*/
 	PAD_NC(GPP_H13, NONE),
-	/* H14:		Not Connected					*/
 	PAD_NC(GPP_H14, NONE),
-	/* H16:		Not Connected					*/
 	PAD_NC(GPP_H16, NONE),
-	/* H20:		Not Connected					*/
 	PAD_NC(GPP_H20, NONE),
-	/* H21:		Not Connected					*/
 	PAD_NC(GPP_H21, NONE),
-	/* H22:		Not Connected					*/
 	PAD_NC(GPP_H22, NONE),
-	/* H23:		Clock Request 5					*/
 	PAD_NC(GPP_H23, NONE),
 
-	/* S0:		Not Connected					*/
 	PAD_NC(GPP_S0, NONE),
-	/* S1:		Not Connected					*/
 	PAD_NC(GPP_S1, NONE),
-	/* S2:		DMIC Clock					*/
 	PAD_NC(GPP_S2, NONE),
-	/* S3:		DMIC Data					*/
 	PAD_NC(GPP_S3, NONE),
-	/* S4:		Not Connected					*/
 	PAD_NC(GPP_S4, NONE),
-	/* S5:		Not Connected					*/
 	PAD_NC(GPP_S5, NONE),
-	/* S6:		Not Connected					*/
 	PAD_NC(GPP_S6, NONE),
-	/* S7:		Not Connected					*/
 	PAD_NC(GPP_S7, NONE),
 
-	/* T0:		 Not Connected					*/
 	PAD_NC(GPP_T0, NONE),
-	/* T1:		 Not Connected					*/
 	PAD_NC(GPP_T1, NONE),
-	/* T2:		 Not Connected					*/
 	PAD_NC(GPP_T2, NONE),
-	/* T3:		 Not Connected					*/
 	PAD_NC(GPP_T3, NONE),
-	/* T4:		 Not Connected					*/
 	PAD_NC(GPP_T4, NONE),
-	/* T5:		 Not Connected					*/
 	PAD_NC(GPP_T5, NONE),
-	/* T6:		 Not Connected					*/
 	PAD_NC(GPP_T6, NONE),
-	/* T7:		 Not Connected					*/
 	PAD_NC(GPP_T7, NONE),
-	/* T8:		 Not Connected					*/
 	PAD_NC(GPP_T8, NONE),
-	/* T9:		 Not Connected					*/
 	PAD_NC(GPP_T9, NONE),
-	/* T10:		 Not Connected					*/
 	PAD_NC(GPP_T10, NONE),
-	/* T11:		 Not Connected					*/
 	PAD_NC(GPP_T11, NONE),
-	/* T12:		 Not Connected					*/
 	PAD_NC(GPP_T12, NONE),
-	/* T13:		 Not Connected					*/
 	PAD_NC(GPP_T13, NONE),
-	/* T14:		 Not Connected					*/
 	PAD_NC(GPP_T14, NONE),
-	/* T15:		 Not Connected					*/
 	PAD_NC(GPP_T15, NONE),
 
-	/* R5:		MiPi Cam Reset					*/
 	PAD_NC(GPP_R5, NONE),
-	/* R6:		Not Connected					*/
 	PAD_NC(GPP_R6, NONE),
-	/* R7:		Not Connected					*/
 	PAD_NC(GPP_R7, NONE),
 };
 

From 69a1a055805955e727963cc1c8c739c96eb73c58 Mon Sep 17 00:00:00 2001
From: Felix Held <felix-coreboot@felixheld.de>
Date: Fri, 11 Apr 2025 15:34:04 +0200
Subject: [PATCH 0773/3886] soc/amd: add functions to retrieve I3C controller
 info

Similarly to how things are done for the I2C controller configuration,
implement the 'soc_get_i3c_ctrlr_info' function in all SoCs that have
I3C controllers. This function returns the contents of the SoC's
'i3c_ctrlr' array containing the base addresses and ACPI names of the
I3C controllers. This function will eventually be called by the common
I3C code which will be implemented in future patches.

Change-Id: Ib23fd896925770f49e567324bc8d12ac4c0944bd
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87280
Reviewed-by: Ana Carolina Cabral <ana.cpmelo95@gmail.com>
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 .../amd/common/block/include/amdblocks/i2c.h   |  8 ++++++++
 src/soc/amd/genoa_poc/Makefile.mk              |  1 +
 src/soc/amd/genoa_poc/i3c.c                    | 18 ++++++++++++++++++
 src/soc/amd/genoa_poc/include/soc/iomap.h      |  1 +
 src/soc/amd/glinda/Makefile.mk                 |  1 +
 src/soc/amd/glinda/i3c.c                       | 18 ++++++++++++++++++
 src/soc/amd/glinda/include/soc/iomap.h         |  1 +
 src/soc/amd/mendocino/Makefile.mk              |  1 +
 src/soc/amd/mendocino/i3c.c                    | 18 ++++++++++++++++++
 src/soc/amd/mendocino/include/soc/iomap.h      |  1 +
 src/soc/amd/phoenix/Makefile.mk                |  1 +
 src/soc/amd/phoenix/i3c.c                      | 18 ++++++++++++++++++
 src/soc/amd/phoenix/include/soc/iomap.h        |  1 +
 13 files changed, 88 insertions(+)
 create mode 100644 src/soc/amd/genoa_poc/i3c.c
 create mode 100644 src/soc/amd/glinda/i3c.c
 create mode 100644 src/soc/amd/mendocino/i3c.c
 create mode 100644 src/soc/amd/phoenix/i3c.c

diff --git a/src/soc/amd/common/block/include/amdblocks/i2c.h b/src/soc/amd/common/block/include/amdblocks/i2c.h
index b02487a32a..94ac173d9b 100644
--- a/src/soc/amd/common/block/include/amdblocks/i2c.h
+++ b/src/soc/amd/common/block/include/amdblocks/i2c.h
@@ -68,6 +68,11 @@ struct i2c_pad_control {
 	enum i2c_pad_rx_level rx_level;
 };
 
+struct soc_i3c_ctrlr_info {
+	uintptr_t bar;
+	const char *acpi_name;
+};
+
 void fch_i2c_pad_init(unsigned int bus,
 		      enum i2c_speed speed,
 		      const struct i2c_pad_control *ctrl);
@@ -94,4 +99,7 @@ void i2c_soc_init(void);
 /* Reset I2C peripherals. */
 void sb_reset_i2c_peripherals(const struct soc_i2c_peripheral_reset_info *reset_info);
 
+/* Getter function to get the SoC I3C controller information. */
+const struct soc_i3c_ctrlr_info *soc_get_i3c_ctrlr_info(size_t *num_ctrlrs);
+
 #endif /* AMD_COMMON_BLOCK_I2C_H */
diff --git a/src/soc/amd/genoa_poc/Makefile.mk b/src/soc/amd/genoa_poc/Makefile.mk
index 73f10a8a44..8a62852157 100644
--- a/src/soc/amd/genoa_poc/Makefile.mk
+++ b/src/soc/amd/genoa_poc/Makefile.mk
@@ -5,6 +5,7 @@ all-y		+= reset.c
 all-y		+= config.c
 all-y		+= gpio.c
 all-y		+= i2c.c
+all-y		+= i3c.c
 all-y		+= uart.c
 
 bootblock-y	+= early_fch.c
diff --git a/src/soc/amd/genoa_poc/i3c.c b/src/soc/amd/genoa_poc/i3c.c
new file mode 100644
index 0000000000..e694623177
--- /dev/null
+++ b/src/soc/amd/genoa_poc/i3c.c
@@ -0,0 +1,18 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <amdblocks/i2c.h>
+#include <soc/iomap.h>
+#include <types.h>
+
+static const struct soc_i3c_ctrlr_info i3c_ctrlr[I3C_CTRLR_COUNT] = {
+	{ APU_I3C0_BASE, "I3C0" },
+	{ APU_I3C1_BASE, "I3C1" },
+	{ APU_I3C2_BASE, "I3C2" },
+	{ APU_I3C3_BASE, "I3C3" }
+};
+
+const struct soc_i3c_ctrlr_info *soc_get_i3c_ctrlr_info(size_t *num_ctrlrs)
+{
+	*num_ctrlrs = ARRAY_SIZE(i3c_ctrlr);
+	return i3c_ctrlr;
+}
diff --git a/src/soc/amd/genoa_poc/include/soc/iomap.h b/src/soc/amd/genoa_poc/include/soc/iomap.h
index f7a1bac235..179fb3d2c9 100644
--- a/src/soc/amd/genoa_poc/include/soc/iomap.h
+++ b/src/soc/amd/genoa_poc/include/soc/iomap.h
@@ -6,6 +6,7 @@
 #define I2C_MASTER_DEV_COUNT		6
 #define I2C_PERIPHERAL_DEV_COUNT	0
 #define I2C_CTRLR_COUNT			(I2C_MASTER_DEV_COUNT + I2C_PERIPHERAL_DEV_COUNT)
+#define I3C_CTRLR_COUNT			4
 
 #define SPI_BASE_ADDRESS		0xfec10000
 
diff --git a/src/soc/amd/glinda/Makefile.mk b/src/soc/amd/glinda/Makefile.mk
index d451199219..eb488d6a0f 100644
--- a/src/soc/amd/glinda/Makefile.mk
+++ b/src/soc/amd/glinda/Makefile.mk
@@ -14,6 +14,7 @@ all-y		+= i2c.c
 
 # all_x86-y adds the compilation unit to all stages that run on the x86 cores
 all_x86-y	+= gpio.c
+all_x86-y	+= i3c.c
 all_x86-y	+= uart.c
 
 bootblock-y	+= early_fch.c
diff --git a/src/soc/amd/glinda/i3c.c b/src/soc/amd/glinda/i3c.c
new file mode 100644
index 0000000000..e694623177
--- /dev/null
+++ b/src/soc/amd/glinda/i3c.c
@@ -0,0 +1,18 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <amdblocks/i2c.h>
+#include <soc/iomap.h>
+#include <types.h>
+
+static const struct soc_i3c_ctrlr_info i3c_ctrlr[I3C_CTRLR_COUNT] = {
+	{ APU_I3C0_BASE, "I3C0" },
+	{ APU_I3C1_BASE, "I3C1" },
+	{ APU_I3C2_BASE, "I3C2" },
+	{ APU_I3C3_BASE, "I3C3" }
+};
+
+const struct soc_i3c_ctrlr_info *soc_get_i3c_ctrlr_info(size_t *num_ctrlrs)
+{
+	*num_ctrlrs = ARRAY_SIZE(i3c_ctrlr);
+	return i3c_ctrlr;
+}
diff --git a/src/soc/amd/glinda/include/soc/iomap.h b/src/soc/amd/glinda/include/soc/iomap.h
index bb68e17ed4..32890dd800 100644
--- a/src/soc/amd/glinda/include/soc/iomap.h
+++ b/src/soc/amd/glinda/include/soc/iomap.h
@@ -6,6 +6,7 @@
 #define I2C_MASTER_DEV_COUNT		4
 #define I2C_PERIPHERAL_DEV_COUNT	0 /* TODO: Only master for now. */
 #define I2C_CTRLR_COUNT			(I2C_MASTER_DEV_COUNT + I2C_PERIPHERAL_DEV_COUNT)
+#define I3C_CTRLR_COUNT			4
 
 #if ENV_X86
 
diff --git a/src/soc/amd/mendocino/Makefile.mk b/src/soc/amd/mendocino/Makefile.mk
index be7f4daca9..06ac55bda4 100644
--- a/src/soc/amd/mendocino/Makefile.mk
+++ b/src/soc/amd/mendocino/Makefile.mk
@@ -11,6 +11,7 @@ all-y		+= i2c.c
 
 # all_x86-y adds the compilation unit to all stages that run on the x86 cores
 all_x86-y	+= gpio.c
+all_x86-y	+= i3c.c
 all_x86-y	+= uart.c
 
 bootblock-y	+= early_fch.c
diff --git a/src/soc/amd/mendocino/i3c.c b/src/soc/amd/mendocino/i3c.c
new file mode 100644
index 0000000000..e694623177
--- /dev/null
+++ b/src/soc/amd/mendocino/i3c.c
@@ -0,0 +1,18 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <amdblocks/i2c.h>
+#include <soc/iomap.h>
+#include <types.h>
+
+static const struct soc_i3c_ctrlr_info i3c_ctrlr[I3C_CTRLR_COUNT] = {
+	{ APU_I3C0_BASE, "I3C0" },
+	{ APU_I3C1_BASE, "I3C1" },
+	{ APU_I3C2_BASE, "I3C2" },
+	{ APU_I3C3_BASE, "I3C3" }
+};
+
+const struct soc_i3c_ctrlr_info *soc_get_i3c_ctrlr_info(size_t *num_ctrlrs)
+{
+	*num_ctrlrs = ARRAY_SIZE(i3c_ctrlr);
+	return i3c_ctrlr;
+}
diff --git a/src/soc/amd/mendocino/include/soc/iomap.h b/src/soc/amd/mendocino/include/soc/iomap.h
index bffdb5f6a9..81a5d17e7e 100644
--- a/src/soc/amd/mendocino/include/soc/iomap.h
+++ b/src/soc/amd/mendocino/include/soc/iomap.h
@@ -6,6 +6,7 @@
 #define I2C_MASTER_DEV_COUNT		4
 #define I2C_PERIPHERAL_DEV_COUNT	0 /* TODO: Only master for now. */
 #define I2C_CTRLR_COUNT			(I2C_MASTER_DEV_COUNT + I2C_PERIPHERAL_DEV_COUNT)
+#define I3C_CTRLR_COUNT			4
 
 #if ENV_X86
 
diff --git a/src/soc/amd/phoenix/Makefile.mk b/src/soc/amd/phoenix/Makefile.mk
index 2766e0eb53..878ebe7bb7 100644
--- a/src/soc/amd/phoenix/Makefile.mk
+++ b/src/soc/amd/phoenix/Makefile.mk
@@ -14,6 +14,7 @@ all-y		+= i2c.c
 
 # all_x86-y adds the compilation unit to all stages that run on the x86 cores
 all_x86-y	+= gpio.c
+all_x86-y	+= i3c.c
 all_x86-y	+= uart.c
 
 bootblock-y	+= early_fch.c
diff --git a/src/soc/amd/phoenix/i3c.c b/src/soc/amd/phoenix/i3c.c
new file mode 100644
index 0000000000..e694623177
--- /dev/null
+++ b/src/soc/amd/phoenix/i3c.c
@@ -0,0 +1,18 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <amdblocks/i2c.h>
+#include <soc/iomap.h>
+#include <types.h>
+
+static const struct soc_i3c_ctrlr_info i3c_ctrlr[I3C_CTRLR_COUNT] = {
+	{ APU_I3C0_BASE, "I3C0" },
+	{ APU_I3C1_BASE, "I3C1" },
+	{ APU_I3C2_BASE, "I3C2" },
+	{ APU_I3C3_BASE, "I3C3" }
+};
+
+const struct soc_i3c_ctrlr_info *soc_get_i3c_ctrlr_info(size_t *num_ctrlrs)
+{
+	*num_ctrlrs = ARRAY_SIZE(i3c_ctrlr);
+	return i3c_ctrlr;
+}
diff --git a/src/soc/amd/phoenix/include/soc/iomap.h b/src/soc/amd/phoenix/include/soc/iomap.h
index 63d8b08a7a..d5dadaffd4 100644
--- a/src/soc/amd/phoenix/include/soc/iomap.h
+++ b/src/soc/amd/phoenix/include/soc/iomap.h
@@ -6,6 +6,7 @@
 #define I2C_MASTER_DEV_COUNT		4
 #define I2C_PERIPHERAL_DEV_COUNT	0 /* TODO: Only master for now. */
 #define I2C_CTRLR_COUNT			(I2C_MASTER_DEV_COUNT + I2C_PERIPHERAL_DEV_COUNT)
+#define I3C_CTRLR_COUNT			4
 
 #if ENV_X86
 

From 360678f79a9c578325e902cb2b4c290e4808188c Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Tue, 15 Apr 2025 19:53:37 +0100
Subject: [PATCH 0774/3886] soc/intel/cnvi: Correct value of CNVI_ABORT_PLDR
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

The definitions were reversed, as PCH_S should use 0x44, and all others
0x80.

These values can be seen in SlimBootloader, and most UEFI firmwares.

Change-Id: Ia2e3866ef7d0756220f15a8d2bdf639ac6667738
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87323
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
---
 src/soc/intel/common/block/include/intelblocks/cnvi.h | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/soc/intel/common/block/include/intelblocks/cnvi.h b/src/soc/intel/common/block/include/intelblocks/cnvi.h
index fa96fdd37d..52f9238206 100644
--- a/src/soc/intel/common/block/include/intelblocks/cnvi.h
+++ b/src/soc/intel/common/block/include/intelblocks/cnvi.h
@@ -15,9 +15,9 @@
 
 /* CNVi PLDR Control */
 #if CONFIG(SOC_INTEL_ALDERLAKE_PCH_S)
-#define CNVI_ABORT_PLDR		0x80
-#else
 #define CNVI_ABORT_PLDR		0x44
+#else
+#define CNVI_ABORT_PLDR		0x80
 #endif
 
 #define CNVI_ABORT_ENABLE	BIT(0)

From c731ef0e478de1e69ce76fc6d4b7023334fde95a Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Wed, 16 Apr 2025 09:19:37 -0500
Subject: [PATCH 0775/3886] drv/wifi/generic: Drop guard for cnvi_gpio_enable
 register

Guarding the existence of this register isn't necessary since we
guard its usage as well, and it complicates some subsequent changes,
so drop it.

Change-Id: I557c400e6dffeb9dc5b4b67a6cc6f15ba0ef27d0
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87343
Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
---
 src/drivers/wifi/generic/chip.h | 2 --
 1 file changed, 2 deletions(-)

diff --git a/src/drivers/wifi/generic/chip.h b/src/drivers/wifi/generic/chip.h
index f6a68e2068..e53459a864 100644
--- a/src/drivers/wifi/generic/chip.h
+++ b/src/drivers/wifi/generic/chip.h
@@ -22,13 +22,11 @@ struct drivers_wifi_generic_config {
 	 */
 	bool enable_cnvi_ddr_rfim;
 
-#if CONFIG(SOC_INTEL_COMMON_BLOCK_CNVI)
 	/*
 	 * Enable GPIO for CNVi that will be used for WiFi SW RF Kill (Low
 	 * Power Mode).
 	 */
 	struct acpi_gpio cnvi_enable_gpio;
-#endif
 
 	/* Pointer to the Bluetooth companion device */
 	DEVTREE_CONST struct device *bluetooth_companion;

From 9b80b36c4af38c620a3dfcfc6ca61d3dcdb61286 Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Wed, 9 Apr 2025 12:28:22 +0100
Subject: [PATCH 0776/3886] drivers/usb/bluetooth: Skip calling _ON when device
 is already enabled

Add a check in the _ON method, similar to coreboot's ONSK handling
in its RTD3 driver, to determine whether the enable GPIO is already
asserted.

This prevents the OS from repeatedly invoking _ON, which can happen
because USB Bluetooth takes around 200ms to initialize after the
GPIO is enabled.

Change-Id: I424bc5f4c5b990fd5cb54daa3d6207828386c6f2
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87239
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/drivers/usb/acpi/intel_bluetooth.c | 15 ++++++++++++++-
 1 file changed, 14 insertions(+), 1 deletion(-)

diff --git a/src/drivers/usb/acpi/intel_bluetooth.c b/src/drivers/usb/acpi/intel_bluetooth.c
index 97fb4816f8..180320349b 100644
--- a/src/drivers/usb/acpi/intel_bluetooth.c
+++ b/src/drivers/usb/acpi/intel_bluetooth.c
@@ -110,6 +110,9 @@ void acpi_device_intel_bt(const struct acpi_gpio *enable_gpio,
  *		}
  *		Method (_ON, 0, NotSerialized)
  *		{
+ *			If ((\_SB.PCI0.GBTE() == 1))
+ *				Return (1)
+ *			}
  *			\_SB.PCI0.SBTE(1)
  *		}
  *		Method (_OFF, 0, NotSerialized)
@@ -126,7 +129,7 @@ void acpi_device_intel_bt(const struct acpi_gpio *enable_gpio,
  *				\_SB.PCI0.BTRK (One)
  *				Sleep (RDLY)
  *				Release (\_SB.PCI0.CNMT)
-			}
+ *			}
  *		}
  *	}
  */
@@ -149,6 +152,16 @@ void acpi_device_intel_bt(const struct acpi_gpio *enable_gpio,
 		acpigen_write_method("_ON", 0);
 		{
 			if (enable_gpio->pin_count) {
+				acpigen_write_store();
+				acpigen_emit_namestring("\\_SB.PCI0.GBTE");
+				acpigen_emit_byte(LOCAL0_OP);
+
+				acpigen_write_if_lequal_op_int(LOCAL0_OP, 1);
+				{
+					acpigen_write_return_integer(1);
+				}
+				acpigen_pop_len();
+
 				acpigen_emit_namestring("\\_SB.PCI0.SBTE");
 				acpigen_emit_byte(1);
 			}

From ba7ed69583e772e13bc27b5560498524e3d08ef8 Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Wed, 9 Apr 2025 12:34:52 +0100
Subject: [PATCH 0777/3886] soc/intel/cnvi: Skip calling _ON when device is
 already enabled

Add a check in the _ON method, similar to coreboot's ONSK handling
in its RTD3 driver, to determine whether the enable GPIO is already
asserted.

This prevents the OS from repeatedly invoking _ON, which can happen
because CNVi takes around 300ms to initialize after the GPIO is
enabled.

Change-Id: I53986aa11714666c12056460aa47396266a00a1c
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87240
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
---
 src/soc/intel/common/block/cnvi/cnvi.c | 14 ++++++++++++++
 1 file changed, 14 insertions(+)

diff --git a/src/soc/intel/common/block/cnvi/cnvi.c b/src/soc/intel/common/block/cnvi/cnvi.c
index 1c668ba736..6d7bbad4e8 100644
--- a/src/soc/intel/common/block/cnvi/cnvi.c
+++ b/src/soc/intel/common/block/cnvi/cnvi.c
@@ -113,6 +113,9 @@ static void cnvw_fill_ssdt(const struct device *dev)
  *		Method(_ON, 0)
  *		{
  *			If (CondRefOf (\_SB.PCI0.CNVC)) {
+ *				If ((\_SB.PCI0.CNVS() == 1)) {
+ *					Return (1)
+ *				}
  *				\_SB.PCI0.CNVS(1)
  *			}
  *		}
@@ -194,6 +197,17 @@ static void cnvw_fill_ssdt(const struct device *dev)
 		{
 			acpigen_write_if_cond_ref_of("\\_SB.PCI0.CNVC");
 			{
+
+				acpigen_write_store();
+				acpigen_emit_namestring("\\_SB.PCI0.CNVS");
+				acpigen_emit_byte(LOCAL0_OP);
+
+				acpigen_write_if_lequal_op_int(LOCAL0_OP, 1);
+				{
+					acpigen_write_return_integer(1);
+				}
+				acpigen_pop_len();
+
 				acpigen_emit_namestring("\\_SB.PCI0.CNVC");
 				acpigen_emit_byte(1);
 			}

From ea17ba0cf2b93bcc59ccbbf574cddafc1f9ec364 Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Wed, 9 Apr 2025 12:44:30 +0100
Subject: [PATCH 0778/3886] drivers/usb/intel_bluetooth: Replace _PRx methods
 with _S0W object

The previous implementation used _PS0 and _PS3 methods to control the
device power states. These are now replaced by a _S0W object to better
align with both coreboot's existing RTD3 driver, and the examples in
the ACPI specification.

This ensures that the Bluetooth device is recognized as capable of
reaching D3Hot when the system is in S0.

Test=build and boot starlite_adl with Windows and Linux, check Bluetooth
is functional and power draw decreases ~0.4W with no devices connected.

Change-Id: I8aa49ee2220ba2ea39b343ea9a9486fca9f5f3d5
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87241
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/drivers/usb/acpi/intel_bluetooth.c | 31 +++++---------------------
 1 file changed, 5 insertions(+), 26 deletions(-)

diff --git a/src/drivers/usb/acpi/intel_bluetooth.c b/src/drivers/usb/acpi/intel_bluetooth.c
index 180320349b..6da937af34 100644
--- a/src/drivers/usb/acpi/intel_bluetooth.c
+++ b/src/drivers/usb/acpi/intel_bluetooth.c
@@ -48,6 +48,11 @@ void acpi_device_intel_bt(const struct acpi_gpio *enable_gpio,
 			  const struct acpi_gpio *reset_gpio,
 			  bool audio_offload)
 {
+/*
+ *	Name (_S0W, 3)
+ */
+	acpigen_write_name_integer("_S0W", ACPI_DEVICE_SLEEP_D3_HOT);
+
 /*
  *	Name (RDLY, 0x69)
  */
@@ -233,32 +238,6 @@ void acpi_device_intel_bt(const struct acpi_gpio *enable_gpio,
 	}
 	acpigen_pop_len();
 
-/*
- *	Method (_PS0, 0, NotSerialized)
- *	{
- *		\_SB.PCI0.SBTE(1)
- *	}
- */
-	acpigen_write_method("_PS0", 0);
-	{
-		acpigen_emit_namestring("\\_SB.PCI0.SBTE");
-		acpigen_emit_byte(1);
-	}
-	acpigen_pop_len();
-
-/*
- *	Name (_PS3, Package (0x01)
- *	{
- *		\_SB.PCI0.SBTE(0)
- *	}
- */
-	acpigen_write_method("_PS3", 0);
-	{
-		acpigen_emit_namestring("\\_SB.PCI0.SBTE");
-		acpigen_emit_byte(0);
-	}
-	acpigen_pop_len();
-
 /*
  *	Method (AOLD, 0, NotSerialized)
  *	{

From ffe19bb7addf21b9d726b00ad48157e738d59361 Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Wed, 9 Apr 2025 12:49:07 +0100
Subject: [PATCH 0779/3886] soc/intel/cnvi: Replace _PRx methods with _S0W
 object

The previous implementation used _PS0 and _PS3 methods to control the
device power states. These are now replaced by a _S0W object to better
align with both coreboot's existing RTD3 driver, and the examples in
the ACPI specification.

This ensures that the Bluetooth device is recognized as capable of
reaching D3Hot when the system is in S0.

Test=build and boot starlite_adl with Windows and Linux, check Bluetooth
is functional and power draw decreases ~0.4W with no devices connected.

Change-Id: I6762b4a2a2454d4e4de2b25e3e5db17df5a8fc63
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87242
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
---
 src/soc/intel/common/block/cnvi/cnvi.c | 43 +++-----------------------
 1 file changed, 5 insertions(+), 38 deletions(-)

diff --git a/src/soc/intel/common/block/cnvi/cnvi.c b/src/soc/intel/common/block/cnvi/cnvi.c
index 6d7bbad4e8..1d35f0cc2d 100644
--- a/src/soc/intel/common/block/cnvi/cnvi.c
+++ b/src/soc/intel/common/block/cnvi/cnvi.c
@@ -86,6 +86,11 @@ static void cnvw_fill_ssdt(const struct device *dev)
 	acpigen_write_field("CWAR", fields2, ARRAY_SIZE(fields2),
 		FIELD_BYTEACC | FIELD_NOLOCK | FIELD_PRESERVE);
 
+/*
+ *	Name (_S0W, 3)
+ */
+	acpigen_write_name_integer("_S0W", ACPI_DEVICE_SLEEP_D3_HOT);
+
 /*
  *	Name (PRRS, Zero)
  */
@@ -355,44 +360,6 @@ static void cnvw_fill_ssdt(const struct device *dev)
 	}
 	acpigen_pop_len();
 
-/*
- *	Method (_PS0, 0, NotSerialized)
- *	{
- *		If (CondRefOf (\_SB.PCI0.CNVC)) {
- *			\_SB.PCI0.CNVS(1)
- *		}
- *	}
- */
-	acpigen_write_method("_PS0", 0);
-	{
-		acpigen_write_if_cond_ref_of("\\_SB.PCI0.CNVC");
-		{
-			acpigen_emit_namestring("\\_SB.PCI0.CNVC");
-			acpigen_emit_byte(1);
-		}
-		acpigen_pop_len();
-	}
-	acpigen_pop_len();
-
-/*
- *	Method (_PS3, 0, NotSerialized)
- *	{
- *		If (CondRefOf (\_SB.PCI0.CNVC)) {
- *			\_SB.PCI0.CNVS(0)
- *		}
- *	}
- */
-	acpigen_write_method("_PS3", 0);
-	{
-		acpigen_write_if_cond_ref_of("\\_SB.PCI0.CNVC");
-		{
-			acpigen_emit_namestring("\\_SB.PCI0.CNVC");
-			acpigen_emit_byte(0);
-		}
-		acpigen_pop_len();
-	}
-	acpigen_pop_len();
-
 /*
  *	Method (GPEH, 0, NotSerialized)
  *	{

From 8800dc7798603c72b18eaead553e25e632e111b2 Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Tue, 15 Apr 2025 19:58:49 +0100
Subject: [PATCH 0780/3886] drivers/usb/intel_bluetooth: Add HotPlugSupportInD3
 DSD Property

Add a DSD with the HotPlugSupportInD3, as when it RTD3, the device
will appear as not-present. This will cause Windows to constantly
try to enable it, causing an endless loop of the device becoming
visible.

Test=build and boot `starlabs/starlite_adl`, check Bluetooth is
always visible in device manager.

Change-Id: I51a2c764ebe8b98b137eb0c98cfdcf2de6f4b86c
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87324
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/drivers/usb/acpi/intel_bluetooth.c | 17 +++++++++++++++++
 1 file changed, 17 insertions(+)

diff --git a/src/drivers/usb/acpi/intel_bluetooth.c b/src/drivers/usb/acpi/intel_bluetooth.c
index 6da937af34..acefffc041 100644
--- a/src/drivers/usb/acpi/intel_bluetooth.c
+++ b/src/drivers/usb/acpi/intel_bluetooth.c
@@ -53,6 +53,23 @@ void acpi_device_intel_bt(const struct acpi_gpio *enable_gpio,
  */
 	acpigen_write_name_integer("_S0W", ACPI_DEVICE_SLEEP_D3_HOT);
 
+/*
+ *	Name (_DSD, Package (0x02)
+ *	{
+ *		ToUUID ("6211e2c0-58a3-4af3-90e1-927a4e0c55a4")
+ *		Package (0x01)
+ *		{
+ *			Package (0x02)
+ *			{
+ *				"HotPlugSupportInD3",
+ *				One
+ *			}
+ *		}
+ *	})
+ *
+ */
+	acpi_device_add_hotplug_support_in_d3(NULL);
+
 /*
  *	Name (RDLY, 0x69)
  */

From b81b7a2014f860b5335c6df229f91c1cc5a679d8 Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Tue, 15 Apr 2025 20:02:13 +0100
Subject: [PATCH 0781/3886] soc/intel/cnvi: Add HotPlugSupportInD3 Property

Add a DSD with the HotPlugSupportInD3, as when it RTD3, the device
will appear as not-present. This will cause Windows to constantly
try to enable it, causing an endless loop of the device becoming
visible.

Test=build and boot `starlabs/starlite_adl`, check CNVi is always
visible in device manager.

Change-Id: I598ab173074522e9d5af002782c5d3ec7691a815
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87325
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/drivers/wifi/generic/acpi.c | 15 ++++++++++++---
 1 file changed, 12 insertions(+), 3 deletions(-)

diff --git a/src/drivers/wifi/generic/acpi.c b/src/drivers/wifi/generic/acpi.c
index 8cab106d36..e64ff01a59 100644
--- a/src/drivers/wifi/generic/acpi.c
+++ b/src/drivers/wifi/generic/acpi.c
@@ -1051,9 +1051,18 @@ static void wifi_ssdt_write_properties(const struct device *dev, const char *sco
 		/* Wake capabilities */
 		acpigen_write_PRW(config->wake, ACPI_S3);
 
-		/* Add _DSD for DmaProperty property. */
-		if (config->add_acpi_dma_property)
-			acpi_device_add_dma_property(NULL);
+		if ((config->add_acpi_dma_property) || (config->cnvi_enable_gpio.pin_count)) {
+			struct acpi_dp *dsd = acpi_dp_new_table("_DSD");
+
+			/* Add _DSD for DmaProperty property. */
+			if (config->add_acpi_dma_property)
+				acpi_device_add_dma_property(dsd);
+
+			if (config->cnvi_enable_gpio.pin_count)
+				acpi_device_add_hotplug_support_in_d3(dsd);
+
+			acpi_dp_write(dsd);
+		}
 	}
 
 	/* Fill regulatory domain structure */

From b6871ab330a37083fb0e3a116ac86ab65d528032 Mon Sep 17 00:00:00 2001
From: Maxim Polyakov <max.senia.poliak@gmail.com>
Date: Thu, 9 Jan 2025 16:29:16 +0300
Subject: [PATCH 0782/3886] mb/asrock/imb-1222: Remove comments for
 non-functional pads

Change-Id: I00a9ab77a9b4ea9b42a50fceffdde382241b6950
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85927
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
---
 src/mainboard/asrock/imb-1222/gpio.c | 82 ++++++++++++++--------------
 1 file changed, 41 insertions(+), 41 deletions(-)

diff --git a/src/mainboard/asrock/imb-1222/gpio.c b/src/mainboard/asrock/imb-1222/gpio.c
index 0c303afa30..549b716fee 100644
--- a/src/mainboard/asrock/imb-1222/gpio.c
+++ b/src/mainboard/asrock/imb-1222/gpio.c
@@ -37,7 +37,7 @@ static const struct pad_config gpio_table[] = {
 
 	/* ------- GPIO Group GPP_B ------- */
 	PAD_NC(GPP_B0, NONE),
-	PAD_CFG_GPO(GPP_B1, 1, PLTRST),			/* GPIO */
+	PAD_CFG_GPO(GPP_B1, 1, PLTRST),
 	PAD_NC(GPP_B2, NONE),
 	PAD_NC(GPP_B3, NONE),
 	PAD_NC(GPP_B4, NONE),
@@ -65,10 +65,10 @@ static const struct pad_config gpio_table[] = {
 	/* ------- GPIO Group GPP_C ------- */
 	PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1),		/* SMBCLK */
 	PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1),		/* SMBDATA */
-	PAD_CFG_GPO(GPP_C2, 1, PLTRST),			/* GPIO */
+	PAD_CFG_GPO(GPP_C2, 1, PLTRST),
 	PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1),		/* SML0CLK */
 	PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1),		/* SML0DATA */
-	PAD_CFG_GPO(GPP_C5, 0, PLTRST),			/* GPIO */
+	PAD_CFG_GPO(GPP_C5, 0, PLTRST),
 	PAD_CFG_NF(GPP_C6, NONE, DEEP, NF1),		/* SML1CLK */
 	PAD_CFG_NF(GPP_C7, NONE, DEEP, NF1),		/* SML1DATA */
 	PAD_NC(GPP_C8, NONE),
@@ -115,12 +115,12 @@ static const struct pad_config gpio_table[] = {
 	PAD_NC(GPP_D23, NONE),
 
 	/* ------- GPIO Group GPP_G ------- */
-	PAD_CFG_GPI_TRIG_OWN(GPP_G0, NONE, DEEP, OFF, ACPI),	/* GPIO */
-	PAD_CFG_GPO(GPP_G1, 1, DEEP),				/* GPIO */
-	PAD_CFG_GPO(GPP_G2, 1, DEEP),				/* GPIO */
-	PAD_CFG_GPO(GPP_G3, 1, DEEP),				/* GPIO */
-	PAD_CFG_GPO(GPP_G4, 1, DEEP),				/* GPIO */
-	PAD_CFG_GPO(GPP_G5, 1, DEEP),				/* GPIO */
+	PAD_CFG_GPI_TRIG_OWN(GPP_G0, NONE, DEEP, OFF, ACPI),
+	PAD_CFG_GPO(GPP_G1, 1, DEEP),
+	PAD_CFG_GPO(GPP_G2, 1, DEEP),
+	PAD_CFG_GPO(GPP_G3, 1, DEEP),
+	PAD_CFG_GPO(GPP_G4, 1, DEEP),
+	PAD_CFG_GPO(GPP_G5, 1, DEEP),
 	PAD_NC(GPP_G6, NONE),
 	PAD_NC(GPP_G7, NONE),
 
@@ -133,7 +133,7 @@ static const struct pad_config gpio_table[] = {
 	PAD_CFG_NF(GPD4, NONE, RSMRST, NF1),		/* SLP_S3# */
 	PAD_CFG_NF(GPD5, NONE, RSMRST, NF1),		/* SLP_S4# */
 	PAD_CFG_NF(GPD6, NONE, RSMRST, NF1),		/* SLP_A# */
-	PAD_CFG_GPO(GPD7, 1, PLTRST),			/* GPIO */
+	PAD_CFG_GPO(GPD7, 1, PLTRST),
 	PAD_CFG_NF(GPD8, NONE, RSMRST, NF1),		/* SUSCLK */
 	PAD_CFG_NF(GPD9, NONE, RSMRST, NF1),		/* SLP_WLAN# */
 	PAD_CFG_NF(GPD10, NONE, RSMRST, NF1),		/* SLP_S5# */
@@ -141,30 +141,30 @@ static const struct pad_config gpio_table[] = {
 
 	/* ------- GPIO Community 3 ------- */
 	/* ------- GPIO Group GPP_K ------- */
-	PAD_CFG_GPO(GPP_K0, 0, PLTRST),			/* GPIO */
-	PAD_CFG_GPO(GPP_K1, 0, PLTRST),			/* GPIO */
-	PAD_CFG_GPO(GPP_K2, 0, PLTRST),			/* GPIO */
-	PAD_CFG_GPO(GPP_K3, 0, PLTRST),			/* GPIO */
-	PAD_CFG_GPO(GPP_K4, 1, PLTRST),			/* GPIO */
-	PAD_CFG_GPO(GPP_K5, 1, PLTRST),			/* GPIO */
+	PAD_CFG_GPO(GPP_K0, 0, PLTRST),
+	PAD_CFG_GPO(GPP_K1, 0, PLTRST),
+	PAD_CFG_GPO(GPP_K2, 0, PLTRST),
+	PAD_CFG_GPO(GPP_K3, 0, PLTRST),
+	PAD_CFG_GPO(GPP_K4, 1, PLTRST),
+	PAD_CFG_GPO(GPP_K5, 1, PLTRST),
 	PAD_NC(GPP_K6, NONE),
 	PAD_NC(GPP_K7, NONE),
-	PAD_CFG_GPO(GPP_K8, 0, PLTRST),			/* GPIO */
-	PAD_CFG_GPO(GPP_K9, 0, PLTRST),			/* GPIO */
-	PAD_CFG_GPO(GPP_K10, 0, PLTRST),		/* GPIO */
-	PAD_CFG_GPO(GPP_K11, 0, PLTRST),		/* GPIO */
-	PAD_CFG_GPI_SCI(GPP_K12, NONE, PLTRST, EDGE_SINGLE, INVERT),	/* GPIO */
-	PAD_NC(GPP_K13, NONE),				/* GPIO */
-	PAD_CFG_GPO(GPP_K14, 0, DEEP),			/* GPIO */
-	PAD_CFG_GPI_TRIG_OWN(GPP_K15, NONE, PLTRST, OFF, ACPI),	/* GPIO */
-	PAD_CFG_GPO(GPP_K16, 0, PLTRST),		/* GPIO */
-	PAD_CFG_GPI_TRIG_OWN(GPP_K17, NONE, PLTRST, OFF, ACPI),	/* GPIO */
+	PAD_CFG_GPO(GPP_K8, 0, PLTRST),
+	PAD_CFG_GPO(GPP_K9, 0, PLTRST),
+	PAD_CFG_GPO(GPP_K10, 0, PLTRST),
+	PAD_CFG_GPO(GPP_K11, 0, PLTRST),
+	PAD_CFG_GPI_SCI(GPP_K12, NONE, PLTRST, EDGE_SINGLE, INVERT),
+	PAD_NC(GPP_K13, NONE),
+	PAD_CFG_GPO(GPP_K14, 0, DEEP),
+	PAD_CFG_GPI_TRIG_OWN(GPP_K15, NONE, PLTRST, OFF, ACPI),
+	PAD_CFG_GPO(GPP_K16, 0, PLTRST),
+	PAD_CFG_GPI_TRIG_OWN(GPP_K17, NONE, PLTRST, OFF, ACPI),
 	PAD_NC(GPP_K18, NONE),
 	PAD_NC(GPP_K19, NONE),
-	PAD_CFG_GPI_TRIG_OWN(GPP_K20, NONE, PLTRST, OFF, ACPI),	/* GPIO */
-	PAD_CFG_GPI_TRIG_OWN(GPP_K21, NONE, DEEP, OFF, ACPI),	/* GPIO */
-	PAD_CFG_GPI_TRIG_OWN(GPP_K22, NONE, PLTRST, OFF, ACPI),	/* GPIO */
-	PAD_CFG_GPI_TRIG_OWN(GPP_K23, NONE, PLTRST, OFF, ACPI),	/* GPIO */
+	PAD_CFG_GPI_TRIG_OWN(GPP_K20, NONE, PLTRST, OFF, ACPI),
+	PAD_CFG_GPI_TRIG_OWN(GPP_K21, NONE, DEEP, OFF, ACPI),
+	PAD_CFG_GPI_TRIG_OWN(GPP_K22, NONE, PLTRST, OFF, ACPI),
+	PAD_CFG_GPI_TRIG_OWN(GPP_K23, NONE, PLTRST, OFF, ACPI),
 
 	/* ------- GPIO Group GPP_H ------- */
 	/* [*] GPP_H0 GPIO/SRCCLKREQ6# */
@@ -179,7 +179,7 @@ static const struct pad_config gpio_table[] = {
 	PAD_NC(GPP_H9, NONE),
 	PAD_NC(GPP_H10, NONE),
 	PAD_NC(GPP_H11, NONE),
-	PAD_CFG_GPO(GPP_H12, 0, PLTRST),		/* GPIO */
+	PAD_CFG_GPO(GPP_H12, 0, PLTRST),
 	PAD_NC(GPP_H13, NONE),
 	PAD_NC(GPP_H14, NONE),
 	PAD_NC(GPP_H15, NONE),
@@ -196,10 +196,10 @@ static const struct pad_config gpio_table[] = {
 	PAD_CFG_NF(GPP_E0, NONE, PLTRST, NF1),		/* SATAXPCIE0 */
 	PAD_CFG_NF(GPP_E1, NONE, PLTRST, NF1),		/* SATAXPCIE1 */
 	PAD_CFG_NF(GPP_E2, NONE, PLTRST, NF1),		/* SATAXPCIE2 */
-	PAD_CFG_GPO(GPP_E3, 1, PLTRST),			/* GPIO */
+	PAD_CFG_GPO(GPP_E3, 1, PLTRST),
 	PAD_NC(GPP_E4, NONE),
-	PAD_CFG_GPI_SMI(GPP_E5, NONE, PLTRST, EDGE_SINGLE, INVERT),	/* GPIO */
-	PAD_CFG_GPI_SMI(GPP_E6, NONE, PLTRST, EDGE_SINGLE, INVERT),	/* GPIO */
+	PAD_CFG_GPI_SMI(GPP_E5, NONE, PLTRST, EDGE_SINGLE, INVERT),
+	PAD_CFG_GPI_SMI(GPP_E6, NONE, PLTRST, EDGE_SINGLE, INVERT),
 	PAD_NC(GPP_E7, NONE),
 	PAD_CFG_NF(GPP_E8, UP_5K, PLTRST, NF1),		/* SATALED# */
 	PAD_NC(GPP_E9, NONE),
@@ -208,11 +208,11 @@ static const struct pad_config gpio_table[] = {
 	PAD_NC(GPP_E12, NONE),
 
 	/* ------- GPIO Group GPP_F ------- */
-	PAD_CFG_GPO(GPP_F0, 0, PLTRST),			/* GPIO */
+	PAD_CFG_GPO(GPP_F0, 0, PLTRST),
 	PAD_CFG_NF(GPP_F1, UP_5K, PLTRST, NF1),		/* SATAXPCIE4 */
-	PAD_CFG_GPO(GPP_F2, 0, PLTRST),			/* GPIO */
-	PAD_CFG_GPO(GPP_F3, 0, PLTRST),			/* GPIO */
-	PAD_CFG_GPO(GPP_F4, 0, PLTRST),			/* GPIO */
+	PAD_CFG_GPO(GPP_F2, 0, PLTRST),
+	PAD_CFG_GPO(GPP_F3, 0, PLTRST),
+	PAD_CFG_GPO(GPP_F4, 0, PLTRST),
 	PAD_NC(GPP_F5, NONE),
 	PAD_NC(GPP_F6, NONE),
 	PAD_NC(GPP_F7, NONE),
@@ -231,7 +231,7 @@ static const struct pad_config gpio_table[] = {
 	PAD_CFG_NF(GPP_F20, NONE, PLTRST, NF1),		/* eDP_BKLTEN */
 	PAD_CFG_NF(GPP_F21, NONE, PLTRST, NF1),		/* eDP_BKLTCTL */
 	PAD_NC(GPP_F22, NONE),
-	PAD_CFG_GPO(GPP_F23, 0, PLTRST),		/* GPIO */
+	PAD_CFG_GPO(GPP_F23, 0, PLTRST),
 
 	/* ------- GPIO Community 4 ------- */
 	/* ------- GPIO Group GPP_I ------- */
@@ -247,9 +247,9 @@ static const struct pad_config gpio_table[] = {
 	PAD_CFG_NF(GPP_I9, NONE, PLTRST, NF1),		/* DDPD_CTRLCLK */
 	PAD_CFG_NF(GPP_I10, NONE, PLTRST, NF1),		/* DDPD_CTRLDATA */
 	PAD_NC(GPP_I11, NONE),
-	PAD_CFG_GPO(GPP_I12, 1, PLTRST),		/* GPIO */
+	PAD_CFG_GPO(GPP_I12, 1, PLTRST),
 	PAD_NC(GPP_I13, NONE),
-	PAD_CFG_GPO(GPP_I14, 1, PLTRST),		/* GPIO */
+	PAD_CFG_GPO(GPP_I14, 1, PLTRST),
 
 	/* ------- GPIO Group GPP_J ------- */
 	PAD_CFG_NF(GPP_J0, NONE, PLTRST, NF1),		/* CNV_PA_BLANKING */

From d71a9697580c31c56bf0f4278e40cab4c8553411 Mon Sep 17 00:00:00 2001
From: Kapil Porwal <kapilporwal@google.com>
Date: Wed, 16 Apr 2025 23:54:29 +0530
Subject: [PATCH 0783/3886] mb/google/brya/var/uldrenite: Use FW_CONFIG for ISH

Control ISH device and corresponding GPIOs using a FW_CONFIG field.

BUG=b:410645679
TEST=Enable/Disable ISH using the new FW_CONFIG field.

Change-Id: I69805116722535d77c7fd7701df261e0faa9138f
Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87344
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jayvik Desai <jayvik@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Yuval Peress <peress@google.com>
---
 .../google/brya/variants/uldrenite/overridetree.cb   |  5 +++++
 .../google/brya/variants/uldrenite/variant.c         | 12 ++++++++++++
 2 files changed, 17 insertions(+)

diff --git a/src/mainboard/google/brya/variants/uldrenite/overridetree.cb b/src/mainboard/google/brya/variants/uldrenite/overridetree.cb
index 00de214d99..55e15175c7 100644
--- a/src/mainboard/google/brya/variants/uldrenite/overridetree.cb
+++ b/src/mainboard/google/brya/variants/uldrenite/overridetree.cb
@@ -15,6 +15,10 @@ fw_config
 		option MB_C_TWO			0
 		option MB_C_ONE			1
 	end
+	field ISH 8 8
+		option ISH_DISABLE		0
+		option ISH_ENABLE		1
+	end
 end
 
 chip soc/intel/alderlake
@@ -487,6 +491,7 @@ chip soc/intel/alderlake
 			probe DB_CELLULAR CELLULAR_RW350R
 		end # PCIE2 WWAN card
 		device ref ish on
+			probe ISH ISH_ENABLE
 			chip drivers/intel/ish
 				register "firmware_name" = ""uldrenite_ish.bin""
 				device generic 0 on end
diff --git a/src/mainboard/google/brya/variants/uldrenite/variant.c b/src/mainboard/google/brya/variants/uldrenite/variant.c
index cbaf20bac8..9944328dca 100644
--- a/src/mainboard/google/brya/variants/uldrenite/variant.c
+++ b/src/mainboard/google/brya/variants/uldrenite/variant.c
@@ -40,6 +40,13 @@ static const struct pad_config lte_disable_pads[] = {
 	PAD_NC(GPP_H23, NONE),
 };
 
+static const struct pad_config ish_disable_pads[] = {
+	/* B5  : GPP_B5 ==> NC */
+	PAD_NC(GPP_B5, NONE),
+	/* B6  : GPP_B6 ==> NC */
+	PAD_NC(GPP_B6, NONE),
+};
+
 void fw_config_gpio_padbased_override(struct pad_config *padbased_table)
 {
 	if (fw_config_probe(FW_CONFIG(TOUCHSCREEN, TOUCHSCREEN_NONE))) {
@@ -52,6 +59,11 @@ void fw_config_gpio_padbased_override(struct pad_config *padbased_table)
 		gpio_padbased_override(padbased_table, lte_disable_pads,
 				ARRAY_SIZE(lte_disable_pads));
 	}
+	if (!fw_config_probe(FW_CONFIG(ISH, ISH_ENABLE))) {
+		printk(BIOS_INFO, "Disable ISH GPIO pins.\n");
+		gpio_padbased_override(padbased_table, ish_disable_pads,
+				ARRAY_SIZE(ish_disable_pads));
+	}
 }
 
 void variant_update_soc_chip_config(struct soc_intel_alderlake_config *config)

From ee5256bfe5b73560a5503a8028c12357f7338543 Mon Sep 17 00:00:00 2001
From: David Wu <david_wu@quanta.corp-partner.google.com>
Date: Mon, 14 Apr 2025 16:21:41 +0800
Subject: [PATCH 0784/3886] mb/google/fatcat: Create kinmen variant

Create the kinmen variant of the fatcat reference board by copying
the fatcat files to a new directory named for the variant.

BUG=b:409148565
TEST=1. util/abuild/abuild -p none -t google/fatcat -x -a
        make sure the build includes GOOGLE_KINMEN
     2. Run part_id_gen tool without any errors

Change-Id: I51e388e61f102216f6ce9233c87c1915596602be
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87317
Reviewed-by: Bob Moragues <moragues@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Derek Huang <derekhuang@google.com>
Reviewed-by: YH Lin <yueherngl@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Jayvik Desai <jayvik@google.com>
---
 src/mainboard/google/fatcat/Kconfig           |   7 +
 src/mainboard/google/fatcat/Kconfig.name      |   3 +
 .../baseboard/fatcat/include/baseboard/gpio.h |   4 +
 .../google/fatcat/variants/kinmen/Makefile.mk |   6 +
 .../google/fatcat/variants/kinmen/gpio.c      | 423 ++++++++++++++++++
 .../google/fatcat/variants/kinmen/hda_verb.c  | 126 ++++++
 .../variants/kinmen/include/variant/ec.h      |   8 +
 .../variants/kinmen/include/variant/gpio.h    |  11 +
 .../google/fatcat/variants/kinmen/memory.c    |  76 ++++
 .../fatcat/variants/kinmen/memory/Makefile.mk |   7 +
 .../kinmen/memory/dram_id.generated.txt       |   7 +
 .../variants/kinmen/memory/mem_parts_used.txt |  12 +
 .../fatcat/variants/kinmen/overridetree.cb    |   5 +
 13 files changed, 695 insertions(+)
 create mode 100644 src/mainboard/google/fatcat/variants/kinmen/Makefile.mk
 create mode 100644 src/mainboard/google/fatcat/variants/kinmen/gpio.c
 create mode 100644 src/mainboard/google/fatcat/variants/kinmen/hda_verb.c
 create mode 100644 src/mainboard/google/fatcat/variants/kinmen/include/variant/ec.h
 create mode 100644 src/mainboard/google/fatcat/variants/kinmen/include/variant/gpio.h
 create mode 100644 src/mainboard/google/fatcat/variants/kinmen/memory.c
 create mode 100644 src/mainboard/google/fatcat/variants/kinmen/memory/Makefile.mk
 create mode 100644 src/mainboard/google/fatcat/variants/kinmen/memory/dram_id.generated.txt
 create mode 100644 src/mainboard/google/fatcat/variants/kinmen/memory/mem_parts_used.txt
 create mode 100644 src/mainboard/google/fatcat/variants/kinmen/overridetree.cb

diff --git a/src/mainboard/google/fatcat/Kconfig b/src/mainboard/google/fatcat/Kconfig
index d24f3c0294..b5f649c648 100644
--- a/src/mainboard/google/fatcat/Kconfig
+++ b/src/mainboard/google/fatcat/Kconfig
@@ -91,6 +91,9 @@ config BOARD_GOOGLE_FRANCKA
 	select BOARD_GOOGLE_BASEBOARD_FATCAT
 	select HAVE_SLP_S0_GATE
 
+config BOARD_GOOGLE_KINMEN
+	select BOARD_GOOGLE_BASEBOARD_FATCAT
+
 if BOARD_GOOGLE_FATCAT_COMMON
 
 config BASEBOARD_DIR
@@ -127,6 +130,7 @@ config DRIVER_TPM_I2C_BUS
 	default 0x03 if BOARD_GOOGLE_MODEL_FATCAT
 	default 0x01 if BOARD_GOOGLE_FRANCKA
 	default 0x01 if BOARD_GOOGLE_FELINO
+	default 0x03 if BOARD_GOOGLE_KINMEN
 
 config HAVE_SLP_S0_GATE
 	def_bool n
@@ -145,6 +149,7 @@ config MAINBOARD_PART_NUMBER
 	default "Fatcatnuvo" if BOARD_GOOGLE_FATCATNUVO
 	default "Francka" if BOARD_GOOGLE_FRANCKA
 	default "Felino" if BOARD_GOOGLE_FELINO
+	default "Kinmen" if BOARD_GOOGLE_KINMEN
 
 config MEMORY_SOLDERDOWN
 	def_bool n
@@ -156,6 +161,7 @@ config TPM_TIS_ACPI_INTERRUPT
 	default 47 if BOARD_GOOGLE_MODEL_FATCAT # GPE0_DW1_15 (GPP_D15)
 	default 79 if BOARD_GOOGLE_FELINO # GPE0_DW2_15 (GPP_F15)
 	default 11 if BOARD_GOOGLE_FRANCKA # GPE0_DW0_11 (GPP_H11)
+	default 47 if BOARD_GOOGLE_KINMEN # GPE0_DW1_15 (GPP_D15)
 
 # FIXME: update as per board schematics
 config UART_FOR_CONSOLE
@@ -170,6 +176,7 @@ config VARIANT_DIR
 	default "fatcat" if BOARD_GOOGLE_MODEL_FATCAT
 	default "francka" if BOARD_GOOGLE_FRANCKA
 	default "felino" if BOARD_GOOGLE_FELINO
+	default "kinmen" if BOARD_GOOGLE_KINMEN
 
 config OVERRIDE_DEVICETREE
 	default "variants/\$(CONFIG_VARIANT_DIR)/overridetree.cb"
diff --git a/src/mainboard/google/fatcat/Kconfig.name b/src/mainboard/google/fatcat/Kconfig.name
index 7c6cb89e65..786c0e7f4b 100644
--- a/src/mainboard/google/fatcat/Kconfig.name
+++ b/src/mainboard/google/fatcat/Kconfig.name
@@ -19,3 +19,6 @@ config BOARD_GOOGLE_FELINO
 
 config BOARD_GOOGLE_FRANCKA
 	bool "-> Francka"
+
+config BOARD_GOOGLE_KINMEN
+	bool "-> Kinmen"
diff --git a/src/mainboard/google/fatcat/variants/baseboard/fatcat/include/baseboard/gpio.h b/src/mainboard/google/fatcat/variants/baseboard/fatcat/include/baseboard/gpio.h
index 067c361161..6934bf12a7 100644
--- a/src/mainboard/google/fatcat/variants/baseboard/fatcat/include/baseboard/gpio.h
+++ b/src/mainboard/google/fatcat/variants/baseboard/fatcat/include/baseboard/gpio.h
@@ -30,6 +30,10 @@
  #define GPIO_PCH_WP	0 /* TODO */
 /* Used to gate SoC's SLP_S0# signal */
 #define GPIO_SLP_S0_GATE	GPP_D03
+#elif CONFIG(BOARD_GOOGLE_KINMEN)
+ #define EC_SYNC_IRQ	GPP_E07_IRQ
+ #define GPIO_PCH_WP	GPP_D02
+#define GPIO_SLP_S0_GATE	0 /* Not Connected */
 #endif
 
 #endif /* __BASEBOARD_GPIO_H__ */
diff --git a/src/mainboard/google/fatcat/variants/kinmen/Makefile.mk b/src/mainboard/google/fatcat/variants/kinmen/Makefile.mk
new file mode 100644
index 0000000000..4c33dad4db
--- /dev/null
+++ b/src/mainboard/google/fatcat/variants/kinmen/Makefile.mk
@@ -0,0 +1,6 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
+bootblock-y += gpio.c
+romstage-y += gpio.c
+romstage-y += memory.c
+ramstage-y += gpio.c
diff --git a/src/mainboard/google/fatcat/variants/kinmen/gpio.c b/src/mainboard/google/fatcat/variants/kinmen/gpio.c
new file mode 100644
index 0000000000..ede819d698
--- /dev/null
+++ b/src/mainboard/google/fatcat/variants/kinmen/gpio.c
@@ -0,0 +1,423 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <baseboard/gpio.h>
+#include <baseboard/variants.h>
+#include <boardid.h>
+#include <soc/gpio.h>
+
+/* Pad configuration in ramstage*/
+static const struct pad_config gpio_table[] = {
+	/* GPP_A00:     ESPI_IO0_EC_R */
+	/*  GPP_A00 : GPP_A00 ==> ESPI_IO0_EC_R configured on reset, do not touch */
+
+	/* GPP_A01:     ESPI_IO1_EC_R */
+	/*  GPP_A01 : GPP_A01 ==> ESPI_IO1_EC_R configured on reset, do not touch */
+
+	/* GPP_A02:     ESPI_IO2_EC_R */
+	/*  GPP_A02 : GPP_A02 ==> ESPI_IO2_EC_R configured on reset, do not touch */
+
+	/* GPP_A03:     ESPI_IO3_EC_R */
+	/*  GPP_A03 : GPP_A03 ==> ESPI_IO3_EC_R configured on reset, do not touch */
+
+	/* GPP_A04:     ESPI_CS0_EC_R_N */
+	/*  GPP_A04 : GPP_A04 ==> ESPI_CS0_HDR_L configured on reset, do not touch */
+
+	/* GPP_A05:     ESPI_CLK_EC_R */
+	/*  GPP_A05 : GPP_A05 ==> ESPI_CLK_HDR configured on reset, do not touch */
+
+	/* GPP_A06:     ESPI_RST_EC_R_N */
+	/*  GPP_A06 : GPP_A06 ==> ESPI_RST_HDR configured on reset, do not touch */
+
+	/* GPP_A09:     M.2_WWAN_FCP_OFF_N */
+	PAD_CFG_GPO(GPP_A09, 1, PLTRST),
+	/* GPP_A10:     M.2_WWAN_DISABLE_N */
+	PAD_CFG_GPO(GPP_A10, 1, PLTRST),
+	/* GPP_A11:     WLAN_RST_N */
+	PAD_CFG_GPO(GPP_A11, 1, PLTRST),
+	/* GPP_A12:     WIFI_WAKE_N */
+	PAD_CFG_GPI_SCI_LOW(GPP_A12, NONE, DEEP, LEVEL),
+	/* GPP_A15:     GPP_A15_DNX_FORCE_RELOAD */
+	PAD_CFG_NF(GPP_A15, NONE, DEEP, NF1),
+	/* GPP_A16:     BT_RF_KILL_N */
+	PAD_CFG_GPO(GPP_A16, 1, DEEP),
+	/* GPP_A17:     WIFI_RF_KILL_N */
+	PAD_CFG_GPO(GPP_A17, 1, DEEP),
+
+	/* GPP_B00:     USBC_SML_CLK_PD */
+	PAD_CFG_NF(GPP_B00, NONE, DEEP, NF1),
+	/* GPP_B01:     USBC_SML_DATA_PD */
+	PAD_CFG_NF(GPP_B01, NONE, DEEP, NF1),
+	/* GPP_B02:     ISH_I2C0_SDA_SNSR_HDR */
+	/* NOTE: IOSSTAGE: 'Ignore' for S0ix */
+	PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_B02, NONE, DEEP, NF3),
+	/* GPP_B03:     ISH_I2C0_SCL_SNSR_HDR */
+	/* NOTE: IOSSTAGE: 'Ignore' for S0ix */
+	PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_B03, NONE, DEEP, NF3),
+	/* GPP_B04:     ISH_GP_0_SNSR_HDR */
+	PAD_CFG_NF(GPP_B04, NONE, DEEP, NF4),
+	/* GPP_B05:     ISH_GP_1_SNSR_HDR */
+	PAD_CFG_NF(GPP_B05, NONE, DEEP, NF4),
+	/* GPP_B06:     ISH_GP_2_SNSR_HDR */
+	PAD_CFG_NF(GPP_B06, NONE, DEEP, NF4),
+	/* GPP_B07:     ISH_GP_3_SNSR_HDR */
+	PAD_CFG_NF(GPP_B07, NONE, DEEP, NF4),
+	/* GPP_B08:     ISH_GP_4_SNSR_HDR */
+	PAD_CFG_NF(GPP_B08, NONE, DEEP, NF4),
+	/* GPP_B09:     M2_GEN4_SSD_RESET_N */
+	PAD_CFG_GPO(GPP_B09, 1, PLTRST),
+	/* GPP_B10:     GEN4_SSD_PWREN */
+	PAD_CFG_GPO(GPP_B10, 1, PLTRST),
+	/* GPP_B11:     MOD_TCSS1_DISP_HPD3 */
+	PAD_CFG_NF(GPP_B11, NONE, DEEP, NF2),
+	/* GPP_B12:     PM_SLP_S0_N */
+	PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1),
+	/* GPP_B13:     PLT_RST_N */
+	PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1),
+	/* GPP_B14:     MOD_TCSS2_DISP_HPD4 */
+	PAD_CFG_NF(GPP_B14, NONE, DEEP, NF2),
+	/* GPP_B15:     MOD_TCSS_USB_TYP_A_OC3_N */
+	PAD_CFG_NF(GPP_B15, NONE, DEEP, NF1),
+	/* GPP_B16:     GEN5_SSD_PWREN */
+	PAD_CFG_GPO(GPP_B16, 1, PLTRST),
+	/* GPP_B17:     Not used */
+	PAD_NC(GPP_B17, NONE),
+	/* GPP_B18:     ISH_I2C2_SDA_SNSR_HDR */
+	/* NOTE: IOSSTAGE: 'Ignore' for S0ix */
+	PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_B18, NONE, DEEP, NF1),
+	/* GPP_B19:     ISH_I2C2_SCL_SNSR_HDR */
+	/* NOTE: IOSSTAGE: 'Ignore' for S0ix */
+	PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_B19, NONE, DEEP, NF1),
+	/* GPP_B20:     M.2_WWAN_RST_N */
+	PAD_CFG_GPO(GPP_B20, 1, PLTRST),
+	/* GPP_B21:     TCP_RETIMER_FORCE_PWR */
+	PAD_CFG_GPO(GPP_B21, 0, DEEP),
+	/* GPP_B22:     ISH_GP_5_SNSR_HDR */
+	PAD_CFG_NF(GPP_B22, NONE, DEEP, NF4),
+	/* GPP_B23:     ISH_GP_6_SNSR_HDR */
+	PAD_CFG_NF(GPP_B23, NONE, DEEP, NF4),
+	/* GPP_B24:     ESPI_ALERT0_EC_R_N */
+	PAD_NC(GPP_B24, NONE),
+
+	/* GPP_C00:     GPP_C0_SMBCLK */
+	PAD_CFG_NF(GPP_C00, NONE, DEEP, NF1),
+	/* GPP_C01:     GPP_C1_SMBDATA */
+	PAD_CFG_NF(GPP_C01, NONE, DEEP, NF1),
+	/* GPP_C02:     Not used */
+	PAD_NC(GPP_C02, NONE),
+	/* GPP_C03:     TCP_LAN_SML0_SCL_R */
+	PAD_CFG_NF(GPP_C03, NONE, DEEP, NF1),
+	/* GPP_C04:     TCP_LAN_SML0_SDA_R */
+	PAD_CFG_NF(GPP_C04, NONE, DEEP, NF1),
+	/* GPP_C06:     SML1_CLK */
+	PAD_CFG_NF(GPP_C06, NONE, DEEP, NF1),
+	/* GPP_C07:     SML1_DATA */
+	PAD_CFG_NF(GPP_C07, NONE, DEEP, NF1),
+	/* GPP_C09:     CLKREQ0_X8_GEN5_DT_CEM_SLOT_N */
+	PAD_CFG_NF(GPP_C09, NONE, DEEP, NF1),
+	/* GPP_C10:     CLKREQ1_X4_GEN5_M2_SSD_N */
+	PAD_CFG_NF(GPP_C10, NONE, DEEP, NF1),
+	/* GPP_C11:     CLKREQ2_X1_GEN4_DT_CEM_SLOT_N */
+	PAD_CFG_NF(GPP_C11, NONE, DEEP, NF1),
+	/* GPP_C12:     CLKREQ3_X1_GEN1_GBE_LAN_N */
+	PAD_CFG_NF(GPP_C12, NONE, DEEP, NF1),
+	/* GPP_C13:     CLKREQ4_X1_GEN4_M2_WLAN_N */
+	PAD_CFG_NF(GPP_C13, NONE, DEEP, NF1),
+	/* GPP_C14:     CLKREQ5_X1_GEN4_M2_WWAN_N */
+	PAD_CFG_NF(GPP_C14, NONE, DEEP, NF1),
+	/* GPP_C16:     TBT_LSX0_TXD  */
+	PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1),
+	/* GPP_C17:     TBT_LSX0_RXD  */
+	PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1),
+	/* GPP_C18:     TBT_LSX1_TXD  */
+	PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1),
+	/* GPP_C19:     TBT_LSX1_RXD */
+	PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1),
+	/* GPP_C20:     MOD_TCSS1_LS_TX_DDC_SCL */
+	PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1),
+	/* GPP_C21:     MOD_TCSS1_LS_RX_DDC_SDA */
+	PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1),
+	/* GPP_C22:     MOD_TCSS2_LS_TX_DDC_SCL */
+	PAD_CFG_NF(GPP_C22, NONE, DEEP, NF2),
+	/* GPP_C23:     MOD_TCSS2_LS_RX_DDC_SDA */
+	PAD_CFG_NF(GPP_C23, NONE, DEEP, NF2),
+
+	/* GPP_D00:     IMGCLKOUT_1 */
+	PAD_CFG_NF(GPP_D00, NONE, DEEP, NF1),
+	/* GPP_D02:     Not used */
+	PAD_NC(GPP_D02, NONE),
+	/* GPP_D03:     M.2_WWAN_PERST_GPIO_N */
+	PAD_CFG_GPO(GPP_D03, 1, PLTRST),
+	/* GPP_D04:     IMGCLKOUT_0 */
+	PAD_CFG_NF(GPP_D04, NONE, DEEP, NF1),
+	/* GPP_D05:     disable ISH_UART0_RXD */
+	PAD_NC(GPP_D05, NONE),
+	/* GPP_D07:     NC */
+	PAD_NC(GPP_D07, NONE),
+	/* GPP_D08:     NC */
+	PAD_NC(GPP_D08, NONE),
+	/* GPP_D09:     PEG_SLOT_RST_N */
+	PAD_CFG_GPO(GPP_D09, 1, PLTRST),
+	/* GPP_D10:     HDA_BCLK */
+	PAD_CFG_NF(GPP_D10, NONE, DEEP, NF1),
+	/* GPP_D11:     HDA_SYNC */
+	PAD_CFG_NF(GPP_D11, NONE, DEEP, NF1),
+	/* GPP_D12:     HDA_SDO */
+	PAD_CFG_NF(GPP_D12, NONE, DEEP, NF1),
+	/* GPP_D13:     HDA_SDI0 */
+	PAD_CFG_NF(GPP_D13, NONE, DEEP, NF1),
+	/* GPP_D14:     COINLESS_MODE_SELECT */
+	PAD_CFG_GPI_TRIG_OWN(GPP_D14, NONE, PLTRST, LEVEL, ACPI),
+	/* GPP_D15:     SPI_TPM_INT_N */
+	PAD_CFG_GPI_APIC_LOCK(GPP_D15, NONE, LEVEL, INVERT, LOCK_CONFIG),
+	/* GPP_D16:     HDA_RST_N_HDR */
+	PAD_CFG_NF(GPP_D16, NONE, DEEP, NF1),
+	/* GPP_D17:     HDA_SDI1_HDR */
+	PAD_CFG_NF(GPP_D17, NONE, DEEP, NF1),
+	/* GPP_D18:     CLKREQ6_X4_GEN4_M2_SSD_N */
+	PAD_CFG_NF(GPP_D18, NONE, DEEP, NF1),
+	/* GPP_D20:     CSE_EARLY_SW */
+	PAD_CFG_GPI_SCI_HIGH(GPP_D20, NONE, DEEP, LEVEL),
+	/* GPP_D21:     NC */
+	PAD_NC(GPP_D21, NONE),
+	/* GPP_D22:     BPKI3C_SDA */
+	PAD_CFG_NF(GPP_D22, NONE, DEEP, NF1),
+	/* GPP_D23:     BPKI3C_SCL */
+	PAD_CFG_NF(GPP_D23, NONE, DEEP, NF1),
+	/* GPP_D24:     PEG_SLOT_WAKE_N */
+	PAD_CFG_GPI_SCI_LOW(GPP_D24, NONE, DEEP, LEVEL),
+	/* GPP_D25:     X4_SLOT_WAKE_N */
+	PAD_CFG_GPI_SCI_LOW(GPP_D25, NONE, DEEP, LEVEL),
+
+	/* GPP_E01:     CRD2_RST_N */
+	PAD_CFG_GPO(GPP_E01, 1, PLTRST),
+	/* GPP_E02:     WWAN_WAKE_GPIO_N  */
+	PAD_CFG_GPI_SCI_LOW(GPP_E02, NONE, DEEP, LEVEL),
+	/* GPP_E03:     M2_GEN5_SSD_RESET_N */
+	PAD_CFG_GPO(GPP_E03, 1, PLTRST),
+	/* GPP_E06:     SECURE_CAM_SW */
+	PAD_CFG_GPI_TRIG_OWN(GPP_E06, NONE, PLTRST, LEVEL, ACPI),
+	/* GPP_E07 : [] ==> EC_SOC_INT_ODL */
+	PAD_CFG_GPI_APIC_LOCK(GPP_E07, NONE, LEVEL, INVERT, LOCK_CONFIG),
+	/* GPP_E08:     Not used */
+	PAD_NC(GPP_E08, NONE),
+	/* GPP_E09:     USB_RD_FP_CONN_12_OC0_N */
+	PAD_CFG_NF(GPP_E09, NONE, DEEP, NF1),
+	/* GPP_E10:     CRD1_RST_N */
+	PAD_CFG_GPO(GPP_E10, 1, PLTRST),
+	/* GPP_E11:     THC0_SPI1_CLK_TCH_PNL1 */
+	PAD_CFG_NF(GPP_E11, NONE, DEEP, NF3),
+	/* GPP_E12:     THC0_SPI1_IO_0_I2C4_SCL_TCH_PNL1 */
+	PAD_CFG_NF(GPP_E12, NONE, DEEP, NF3),
+	/* GPP_E13:     THC0_SPI1_IO_1_I2C4_SDA_TCH_PNL1 */
+	PAD_CFG_NF(GPP_E13, NONE, DEEP, NF3),
+	/* GPP_E14:     THC0_SPI1_IO_2_TCH_PNL1 */
+	PAD_CFG_NF(GPP_E14, NONE, DEEP, NF3),
+	/* GPP_E15:     THC0_SPI1_IO_3_TCH_PNL1 */
+	PAD_CFG_NF(GPP_E15, NONE, DEEP, NF3),
+	/* GPP_E16:     THC0_SPI1_RST_N_TCH_PNL1 */
+	/* THC NOTE: use GPO instead of GPO for THC0 Rst */
+	PAD_CFG_GPO(GPP_E16, 1, DEEP),
+	/* GPP_E18:     THC0_SPI1_INT_N_TCH_PNL1 */
+	PAD_CFG_NF(GPP_E18, NONE, DEEP, NF3),
+	/* GPP_E21:     I2C_PMC_PD_INT_N */
+	PAD_CFG_NF(GPP_E21, NONE, DEEP, NF1),
+	/* GPP_E22:     THC0_SPI1_DSYNC */
+	PAD_CFG_NF(GPP_E22, NONE, DEEP, NF3),
+
+	/* GPP_F00:     M.2_CNV_BRI_DT_BT_UART2_RTS_N */
+	/* NOTE: IOSSTAGE: 'Ignore' for S0ix */
+	PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_F00, NONE, DEEP, NF1),
+	/* GPP_F01:     M.2_CNV_BRI_RSP_BT_UART2_RXD */
+	/* NOTE: IOSSTAGE: 'Ignore' for S0ix */
+	PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_F01, NONE, DEEP, NF1),
+	/* GPP_F02:     M.2_CNV_RGI_DT_BT_UART2_TXD */
+	/* NOTE: IOSSTAGE: 'Ignore' for S0ix */
+	PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_F02, NONE, DEEP, NF1),
+	/* GPP_F03:     M.2_CNV_RGI_RSP_BT_UART2_CTS_N */
+	/* NOTE: IOSSTAGE: 'Ignore' for S0ix */
+	PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_F03, NONE, DEEP, NF1),
+	/* GPP_F04:     CNV_RF_RESET_R_N */
+	/* NOTE: IOSSTAGE: 'Ignore' for S0ix */
+	PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_F04, NONE, DEEP, NF1),
+	/* GPP_F05:     CRF_CLKREQ_R */
+	/* NOTE: IOSSTAGE: 'Ignore' for S0ix */
+	PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_F05, NONE, DEEP, NF3),
+	/* GPP_F06:     WLAN_WWAN_COEX3 */
+	PAD_CFG_NF(GPP_F06, NONE, DEEP, NF1),
+	/* GPP_F07:     IMGCLKOUT_2 */
+	PAD_CFG_NF(GPP_F07, NONE, DEEP, NF2),
+	/* GPP_F08:     TCH_PNL1_PWR_EN */
+	PAD_CFG_GPO(GPP_F08, 1, PLTRST),
+	/* GPP_F09:     NC */
+	PAD_NC(GPP_F09, NONE),
+	/* GPP_F10:     PEG_SLOT_PWR_EN_N */
+	PAD_CFG_GPO(GPP_F10, 0, PLTRST),
+	/* GPP_F11:     MOD_TCSS2_TYP_A_VBUS_EN */
+	PAD_CFG_GPO(GPP_F11, 1, DEEP),
+	/* GPP_F12:     THC_I2C1_SCL_TCH_PAD */
+	PAD_CFG_NF(GPP_F12, NONE, DEEP, NF8),
+	/* GPP_F13:     THC_I2C1_SDA_TCH_PAD */
+	PAD_CFG_NF(GPP_F13, NONE, DEEP, NF8),
+	/* GPP_F17:     Not used */
+	PAD_CFG_GPI_INT(GPP_F17, NONE, PLTRST, EDGE_BOTH),
+	/* GPP_F18:     TCH_PAD_INT_N */
+	/* NOTE: require rework to switch from GPP_A13 to GPP_F18 */
+	PAD_CFG_GPI_APIC(GPP_F18, NONE, PLTRST, LEVEL, INVERT),
+	/* GPP_F19:     GPP_PRIVACY_LED_CAM2 */
+	PAD_CFG_GPO(GPP_F19, 0, PLTRST),
+	/* GPP_F20:     GPP_PRIVACY_LED_CAM1_CVS_HST_WAKE */
+	PAD_CFG_GPO(GPP_F20, 0, PLTRST),
+	/* GPP_F22:     THC1_SPI2_DSYNC */
+	PAD_CFG_NF(GPP_F22, NONE, DEEP, NF3),
+
+	/* GPP_H00:     Not used */
+	PAD_NC(GPP_H00, NONE),
+	/* GPP_H01:     CRD_CAM_STROBE */
+	PAD_CFG_GPO(GPP_H01, 0, PLTRST),
+	/* GPP_H02:     DEBUG_TRACE_PNP */
+	PAD_CFG_GPO(GPP_H02, 1, PLTRST),
+	/* GPP_H03:     MIC MUTE */
+	PAD_CFG_NF(GPP_H03, NONE, DEEP, NF1),
+	/* GPP_H04:     I2C2_SDA_CAM_FLSH */
+	PAD_CFG_NF(GPP_H04, NONE, DEEP, NF1),
+	/* GPP_H05:     I2C2_SCL_CAM_FLSH */
+	PAD_CFG_NF(GPP_H05, NONE, DEEP, NF1),
+	/* GPP_H06:     I2C3_SDA_PSS */
+	PAD_CFG_NF(GPP_H06, NONE, DEEP, NF1),
+	/* GPP_H07:     I2C3_SCL_PSS */
+	PAD_CFG_NF(GPP_H07, NONE, DEEP, NF1),
+	/* GPP_H08:     UART0_BUF_RXD */
+	PAD_CFG_NF(GPP_H08, NONE, DEEP, NF1),
+	/* GPP_H09:     UART0_BUF_TXD */
+	PAD_CFG_NF(GPP_H09, NONE, DEEP, NF1),
+	/* GPP_H10:     UART0_BUF_RTS */
+	PAD_CFG_NF(GPP_H10, NONE, DEEP, NF1),
+	/* GPP_H11:     UART0_BUF_CTS */
+	PAD_CFG_NF(GPP_H11, NONE, DEEP, NF1),
+	/* GPP_H13:     CPU_C10_GATE_N_R */
+	PAD_CFG_NF(GPP_H13, NONE, DEEP, NF1),
+	/* GPP_H14:     NC */
+	PAD_NC(GPP_H14, NONE),
+	/* GPP_H15:     NC */
+	PAD_NC(GPP_H15, NONE),
+	/* GPP_H16:     WWAN_PWREN */
+	PAD_CFG_GPO(GPP_H16, 1, PLTRST),
+	/* GPP_H17:     MIC MUTE LED */
+	PAD_CFG_NF(GPP_H17, NONE, DEEP, NF1),
+	/* GPP_H19:     I3C0_SDA_HDR */
+	PAD_CFG_NF(GPP_H19, NONE, DEEP, NF2),
+	/* GPP_H20:     I3C0_SCL_HDR */
+	PAD_CFG_NF(GPP_H20, NONE, DEEP, NF2),
+	/* GPP_H21:     I2C1_SDA_I3C1_SDA_CAM_FLSH_CVS */
+	PAD_CFG_NF(GPP_H21, NONE, DEEP, NF1),
+	/* GPP_H22:     I2C1_SCL_I3C1_SCL_CAM_FLSH_CVS */
+	PAD_CFG_NF(GPP_H22, NONE, DEEP, NF1),
+
+	/* GPP_S00:     SNDW3_CLK_CODEC */
+	PAD_CFG_NF(GPP_S00, NONE, DEEP, NF1),
+	/* GPP_S01:     SNDW3_DATA0_CODEC */
+	PAD_CFG_NF(GPP_S01, NONE, DEEP, NF1),
+	/* GPP_S02:     SNDW3_DATA1_CODEC */
+	PAD_CFG_NF(GPP_S02, NONE, DEEP, NF1),
+	/* GPP_S03:     SNDW3_DATA2_CODEC */
+	PAD_CFG_NF(GPP_S03, NONE, DEEP, NF1),
+	/* GPP_S04:     SNDW2_CLK */
+	PAD_CFG_NF(GPP_S04, NONE, DEEP, NF2),
+	/* GPP_S05:     SNDW2_DATA0 */
+	PAD_CFG_NF(GPP_S05, NONE, DEEP, NF2),
+	/* GPP_S06:     SNDW1_CLK */
+	PAD_CFG_NF(GPP_S06, NONE, DEEP, NF3),
+	/* GPP_S07:     SNDW1_DATA0 */
+	PAD_CFG_NF(GPP_S07, NONE, DEEP, NF3),
+
+	/* GPP_V00:     PM_BATLOW_N */
+	PAD_CFG_NF(GPP_V00, NONE, DEEP, NF1),
+	/* GPP_V01:     BC_ACOK_MCP */
+	PAD_CFG_NF(GPP_V01, NONE, DEEP, NF1),
+	/* GPP_V02:     LANWAKE_N_R */
+	PAD_CFG_NF(GPP_V02, NONE, DEEP, NF1),
+	/* GPP_V03:     PWRBTN_MCP_N */
+	PAD_CFG_NF(GPP_V03, NONE, DEEP, NF1),
+	/* GPP_V04:     PM_SLP_S3_N */
+	PAD_CFG_NF(GPP_V04, NONE, DEEP, NF1),
+	/* GPP_V05:     PM_SLP_S4_N */
+	PAD_CFG_NF(GPP_V05, NONE, DEEP, NF1),
+	/* GPP_V06:     PM_SLP_A_N */
+	PAD_CFG_NF(GPP_V06, NONE, DEEP, NF1),
+	/* GPP_V07:     Not used */
+	PAD_NC(GPP_V07, NONE),
+	/* GPP_V08:     SLP_WLAN_N */
+	PAD_CFG_NF(GPP_V08, NONE, DEEP, NF1),
+	/* GPP_V09:     PM_SLP_S5_N */
+	PAD_CFG_NF(GPP_V09, NONE, DEEP, NF1),
+	/* GPP_V10:     LANPHYPC_R_N */
+	PAD_CFG_NF(GPP_V10, NONE, DEEP, NF1),
+	/* GPP_V11:     PM_SLP_LAN_N */
+	PAD_CFG_NF(GPP_V11, NONE, DEEP, NF1),
+	/* GPP_V12:     WAKE_N */
+	PAD_CFG_NF(GPP_V12, NONE, DEEP, NF1),
+	/* GPP_V13:     GPP_V13_CATERR_N */
+	PAD_CFG_NF(GPP_V13, NONE, DEEP, NF1),
+	/* GPP_V14:     GPP_V14_FORCEPR_N */
+	PAD_CFG_NF(GPP_V14, NONE, DEEP, NF1),
+	/* GPP_V15:     GPP_V15_THERMTRIP_N */
+	PAD_CFG_NF(GPP_V15, NONE, DEEP, NF1),
+	/* GPP_V16:     GPP_V16_VCCST_EN */
+	PAD_CFG_NF(GPP_V16, NONE, DEEP, NF1),
+	/* GPP_V17:     TCP_RT_S0IX_ENTRY_EXIT_N */
+	PAD_CFG_GPO(GPP_V17, 1, DEEP),
+};
+
+/* Early pad configuration in bootblock */
+static const struct pad_config early_gpio_table[] = {
+	/* GPP_H08:     UART0_BUF_RXD */
+	PAD_CFG_NF(GPP_H08, NONE, DEEP, NF1),
+	/* GPP_H09:     UART0_BUF_TXD */
+	PAD_CFG_NF(GPP_H09, NONE, DEEP, NF1),
+
+	/* GPP_H06: I2C3_SDA_PSS */
+	PAD_CFG_NF(GPP_H06, NONE, DEEP, NF1),
+	/* GPP_H07: I2C3_SCL_PSS */
+	PAD_CFG_NF(GPP_H07, NONE, DEEP, NF1),
+	/* GPP_D15: SPI_TPM_INT_N */
+	PAD_CFG_GPI_APIC(GPP_D15, NONE, PLTRST, LEVEL, INVERT),
+};
+
+/* Pad configuration in romstage */
+static const struct pad_config romstage_gpio_table[] = {
+	/* GPP_A08:     X1_PCIE_SLOT_PWR_EN */
+	PAD_CFG_GPO(GPP_A08, 0, PLTRST),
+	/* GPP_C00:     GPP_C0_SMBCLK */
+	PAD_CFG_NF(GPP_C00, NONE, DEEP, NF1),
+	/* GPP_C01:     GPP_C1_SMBDATA */
+	PAD_CFG_NF(GPP_C01, NONE, DEEP, NF1),
+};
+
+const struct pad_config *variant_gpio_table(size_t *num)
+{
+	*num = ARRAY_SIZE(gpio_table);
+	return gpio_table;
+}
+
+const struct pad_config *variant_early_gpio_table(size_t *num)
+{
+	*num = ARRAY_SIZE(early_gpio_table);
+	return early_gpio_table;
+}
+
+/* Create the stub for romstage gpio, typically use for power sequence */
+const struct pad_config *variant_romstage_gpio_table(size_t *num)
+{
+	*num = ARRAY_SIZE(romstage_gpio_table);
+	return romstage_gpio_table;
+}
+
+static const struct cros_gpio cros_gpios[] = {
+	CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE0_NAME),
+	CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE1_NAME),
+	CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE2_NAME),
+	CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE3_NAME),
+	CROS_GPIO_WP_AH(GPIO_PCH_WP, CROS_GPIO_DEVICE4_NAME),
+};
+
+DECLARE_CROS_GPIOS(cros_gpios);
diff --git a/src/mainboard/google/fatcat/variants/kinmen/hda_verb.c b/src/mainboard/google/fatcat/variants/kinmen/hda_verb.c
new file mode 100644
index 0000000000..2f703b78ee
--- /dev/null
+++ b/src/mainboard/google/fatcat/variants/kinmen/hda_verb.c
@@ -0,0 +1,126 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <device/azalia_device.h>
+
+const u32 cim_verb_data[] = {
+	/* coreboot specific header */
+	0x10ec0256,	/* Codec Vendor / Device ID: Realtek ALC256 */
+	0x10ec12ac,	/* Subsystem ID */
+	0x00000013,	/* Number of jacks (NID entries) */
+
+	AZALIA_RESET(0x1),
+	/* NID 0x01, HDA Codec Subsystem ID Verb Table */
+	AZALIA_SUBVENDOR(0, 0x10ec12ac),
+
+	/* Pin Widget Verb Table */
+	/*
+	 * DMIC
+	 * Requirement is to use PCH DMIC. Hence,
+	 * commented out codec's Internal DMIC.
+	 * AZALIA_PIN_CFG(0, 0x12, 0x90A60130),
+	 * AZALIA_PIN_CFG(0, 0x13, 0x40000000),
+	 */
+	/* Pin widget 0x14 - Front (Port-D) */
+	AZALIA_PIN_CFG(0, 0x14, 0x90170110),
+	/* Pin widget 0x18 - NPC */
+	AZALIA_PIN_CFG(0, 0x18, 0x411111F0),
+	/* Pin widget 0x19 - MIC2 (Port-F) */
+	AZALIA_PIN_CFG(0, 0x19, 0x04A11040),
+	/* Pin widget 0x1A - LINE1 (Port-C) */
+	AZALIA_PIN_CFG(0, 0x1a, 0x411111F0),
+	/* Pin widget 0x1B - NPC */
+	AZALIA_PIN_CFG(0, 0x1b, 0x411111F0),
+	/* Pin widget 0x1D - BEEP-IN */
+	AZALIA_PIN_CFG(0, 0x1d, 0x40610041),
+	/* Pin widget 0x1E - NPC */
+	AZALIA_PIN_CFG(0, 0x1e, 0x411111F0),
+	/* Pin widget 0x21 - HP1-OUT (Port-I) */
+	AZALIA_PIN_CFG(0, 0x21, 0x04211020),
+	/*
+	 * Widget node 0x20 - 1
+	 * Codec hidden reset and speaker power 2W/4ohm
+	 */
+	0x0205001A,
+	0x0204C003,
+	0x02050038,
+	0x02047901,
+	/*
+	 * Widget node 0x20 - 2
+	 * Class D power on Reset
+	 */
+	0x0205003C,
+	0x02040354,
+	0x0205003C,
+	0x02040314,
+	/*
+	 * Widget node 0x20 - 3
+	 * Disable AGC and set AGC limit to -1.5dB
+	 */
+	0x02050016,
+	0x02040C50,
+	0x02050012,
+	0x0204EBC1,
+	/*
+	 * Widget node 0x20 - 4
+	 * Set AGC Post gain +1.5dB then Enable AGC
+	 */
+	0x02050013,
+	0x02044023,
+	0x02050016,
+	0x02040E50,
+	/*
+	 * Widget node 0x20 - 5
+	 * Silence detector enabling + Set EAPD to verb control
+	 */
+	0x02050037,
+	0x0204FE15,
+	0x02050010,
+	0x02040020,
+	/*
+	 * Widget node 0x20 - 6
+	 * Silence data mode Threshold (-90dB)
+	 */
+	0x02050030,
+	0x0204A000,
+	0x0205001B,
+	0x02040A4B,
+	/*
+	 * Widget node 0x20 - 7
+	 * Default setting-1
+	 */
+	0x05750003,
+	0x05740DA3,
+	0x02050046,
+	0x02040004,
+	/*
+	 * Widget node 0x20 - 8
+	 * support 1 pin detect two port
+	 */
+	0x02050009,
+	0x0204E003,
+	0x0205000A,
+	0x02047770,
+	/*
+	 * Widget node 0x20 - 9
+	 * To set LDO1/LDO2 as default
+	 */
+	0x02050008,
+	0x02046A0C,
+	0x02050008,
+	0x02046A0C,
+};
+
+const u32 pc_beep_verbs[] = {
+	/* Dos beep path - 1 */
+	0x01470C00,
+	0x02050036,
+	0x02047151,
+	0x01470740,
+	/* Dos beep path - 2 */
+	0x0143b000,
+	0x01470C02,
+	0x01470C02,
+	0x01470C02,
+};
+
+AZALIA_ARRAY_SIZES;
diff --git a/src/mainboard/google/fatcat/variants/kinmen/include/variant/ec.h b/src/mainboard/google/fatcat/variants/kinmen/include/variant/ec.h
new file mode 100644
index 0000000000..4fc0622f15
--- /dev/null
+++ b/src/mainboard/google/fatcat/variants/kinmen/include/variant/ec.h
@@ -0,0 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#ifndef MAINBOARD_EC_H
+#define MAINBOARD_EC_H
+
+#include <baseboard/ec.h>
+
+#endif /* MAINBOARD_GPIO_H */
diff --git a/src/mainboard/google/fatcat/variants/kinmen/include/variant/gpio.h b/src/mainboard/google/fatcat/variants/kinmen/include/variant/gpio.h
new file mode 100644
index 0000000000..cced66807a
--- /dev/null
+++ b/src/mainboard/google/fatcat/variants/kinmen/include/variant/gpio.h
@@ -0,0 +1,11 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#ifndef __MAINBOARD_GPIO_H__
+#define __MAINBOARD_GPIO_H__
+
+#include <baseboard/gpio.h>
+
+/* EC wake is LAN_WAKE# which is a special DeepSX wake pin */
+#define GPE_EC_WAKE	GPE0_LAN_WAK
+
+#endif /* __MAINBOARD_GPIO_H__ */
diff --git a/src/mainboard/google/fatcat/variants/kinmen/memory.c b/src/mainboard/google/fatcat/variants/kinmen/memory.c
new file mode 100644
index 0000000000..e0908adabd
--- /dev/null
+++ b/src/mainboard/google/fatcat/variants/kinmen/memory.c
@@ -0,0 +1,76 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <baseboard/variants.h>
+#include <soc/romstage.h>
+#include <soc/meminit.h>
+
+static const struct mb_cfg lp5_mem_config = {
+	.type = MEM_TYPE_LP5X,
+
+	.lpx_dq_map = {
+		.ddr0 = {
+			.dq0 = {  13,  14,  12,  15, 11,  10,  8,  9, },
+			.dq1 = {  7,  5,  4,  6,  0,  3,  1,  2 },
+		},
+		.ddr1 = {
+			.dq0 = {  1,  3,  0,  2,  7,  4,  6,  5, },
+			.dq1 = {  12,  13,  14,  15,  11,  10,  9,  8 },
+		},
+		.ddr2 = {
+			.dq0 = {  0,  2,  1,  3,  6,  4,  7,  5 },
+			.dq1 = {  14,  13,  15,  12,  8,  11,  10,  9, },
+		},
+		.ddr3 = {
+			.dq0 = {  6,  5,  7,  4,  2,  3,  1,  0, },
+			.dq1 = {  10,  8,  11,  9,  12,  15,  13,  14 },
+		},
+		.ddr4 = {
+			.dq0 = {  2,  1,  3,  0,  4,  7,  5,  6 },
+			.dq1 = {  15,  14,  12,  13,  9,  11,  10,  8, },
+		},
+		.ddr5 = {
+			.dq0 = {  6,  5,  7,  4,  3,  1,  0,  2, },
+			.dq1 = {  10,  9,  11,  8,  13,  14,  12,  15 },
+		},
+		.ddr6 = {
+			.dq0 = {  9,  10,  11,  8,  14,  12,  13, 15, },
+			.dq1 = {  0,  1,  2,  3,  5,  7,  4,  6 },
+		},
+		.ddr7 = {
+			.dq0 = {  0,  1,  2,  3,  7,  5,  6,  4, },
+			.dq1 = {  14,  13,  15,  12,  10,  8,  11,  9 },
+		},
+	},
+
+	.lpx_dqs_map = {
+		.ddr0 = { .dqs0 = 1, .dqs1 = 0 },
+		.ddr1 = { .dqs0 = 0, .dqs1 = 1 },
+		.ddr2 = { .dqs0 = 0, .dqs1 = 1 },
+		.ddr3 = { .dqs0 = 0, .dqs1 = 1 },
+		.ddr4 = { .dqs0 = 0, .dqs1 = 1 },
+		.ddr5 = { .dqs0 = 0, .dqs1 = 1 },
+		.ddr6 = { .dqs0 = 1, .dqs1 = 0 },
+		.ddr7 = { .dqs0 = 0, .dqs1 = 1 }
+	},
+
+	.ect = true, /* Early Command Training */
+
+	.lp_ddr_dq_dqs_re_training = 1,
+
+	.user_bd = BOARD_TYPE_ULT_ULX,
+
+	.lp5x_config = {
+		.ccc_config = 0xFF,
+	},
+};
+
+const struct mb_cfg *variant_memory_params(void)
+{
+	return &lp5_mem_config;
+}
+
+void variant_get_spd_info(struct mem_spd *spd_info)
+{
+	spd_info->topo = MEM_TOPO_MEMORY_DOWN;
+	spd_info->cbfs_index = 0;
+}
diff --git a/src/mainboard/google/fatcat/variants/kinmen/memory/Makefile.mk b/src/mainboard/google/fatcat/variants/kinmen/memory/Makefile.mk
new file mode 100644
index 0000000000..8fccc97b68
--- /dev/null
+++ b/src/mainboard/google/fatcat/variants/kinmen/memory/Makefile.mk
@@ -0,0 +1,7 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+# This is an auto-generated file. Do not edit!!
+# Generated by:
+# ./util/spd_tools/bin/part_id_gen PTL lp5 src/mainboard/google/fatcat/variants/kinmen/memory src/mainboard/google/fatcat/variants/kinmen/memory/mem_parts_used.txt
+
+SPD_SOURCES =
+SPD_SOURCES += spd/lp5/set-0/spd-7.hex      # ID = 0(0b0000)  Parts = H58G56BK7BX068
diff --git a/src/mainboard/google/fatcat/variants/kinmen/memory/dram_id.generated.txt b/src/mainboard/google/fatcat/variants/kinmen/memory/dram_id.generated.txt
new file mode 100644
index 0000000000..15fcc5cf14
--- /dev/null
+++ b/src/mainboard/google/fatcat/variants/kinmen/memory/dram_id.generated.txt
@@ -0,0 +1,7 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+# This is an auto-generated file. Do not edit!!
+# Generated by:
+# ./util/spd_tools/bin/part_id_gen PTL lp5 src/mainboard/google/fatcat/variants/kinmen/memory src/mainboard/google/fatcat/variants/kinmen/memory/mem_parts_used.txt
+
+DRAM Part Name                 ID to assign
+H58G56BK7BX068                 0 (0000)
diff --git a/src/mainboard/google/fatcat/variants/kinmen/memory/mem_parts_used.txt b/src/mainboard/google/fatcat/variants/kinmen/memory/mem_parts_used.txt
new file mode 100644
index 0000000000..17ee7efc60
--- /dev/null
+++ b/src/mainboard/google/fatcat/variants/kinmen/memory/mem_parts_used.txt
@@ -0,0 +1,12 @@
+# This is a CSV file containing a list of memory parts used by this variant.
+# One part per line with an optional fixed ID in column 2.
+# Only include a fixed ID if it is required for legacy reasons!
+# Generated IDs are dependent on the order of parts in this file,
+# so new parts must always be added at the end of the file!
+#
+# Generate an updated Makefile.mk and dram_id.generated.txt by running the
+# part_id_gen tool from util/spd_tools.
+# See util/spd_tools/README.md for more details and instructions.
+
+# Part Name
+H58G56BK7BX068
diff --git a/src/mainboard/google/fatcat/variants/kinmen/overridetree.cb b/src/mainboard/google/fatcat/variants/kinmen/overridetree.cb
new file mode 100644
index 0000000000..bfd637ae50
--- /dev/null
+++ b/src/mainboard/google/fatcat/variants/kinmen/overridetree.cb
@@ -0,0 +1,5 @@
+chip soc/intel/pantherlake
+
+	device domain 0 on
+	end
+end

From 051fdff0e8f68760cf76cc556392d6cb1e30a853 Mon Sep 17 00:00:00 2001
From: Yuval Peress <peress@google.com>
Date: Wed, 16 Apr 2025 03:52:42 +0000
Subject: [PATCH 0785/3886] mb/google/brya/var/uldrenite/gpio: Enable ISH
 sensor interrupts

Enable the interrupts coming from the sensors into the ISH.

BUG=b:410645679

Change-Id: I2acaed1900e248cfe7fcc81201c6991a9741f26c
Signed-off-by: Yuval Peress <peress@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87333
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/google/brya/variants/uldrenite/gpio.c    | 8 ++++----
 src/mainboard/google/brya/variants/uldrenite/variant.c | 4 ++++
 2 files changed, 8 insertions(+), 4 deletions(-)

diff --git a/src/mainboard/google/brya/variants/uldrenite/gpio.c b/src/mainboard/google/brya/variants/uldrenite/gpio.c
index 9097af2584..900daea2e0 100644
--- a/src/mainboard/google/brya/variants/uldrenite/gpio.c
+++ b/src/mainboard/google/brya/variants/uldrenite/gpio.c
@@ -119,8 +119,8 @@ static const struct pad_config gpio_table[] = {
 
 	/* D0  : ISH_GP0 ==> UCAM_FW_PROTECT */
 	PAD_CFG_GPO(GPP_D0, 1, DEEP),
-	/* D1  : ISH_GP1 ==> NC */
-	PAD_NC(GPP_D1, NONE),
+	/* D1  : ISH_GP1 ==> SOC_GSEN2_INT# */
+	PAD_CFG_NF(GPP_D1, NONE, DEEP, NF1),
 	/* D2  : ISH_GP2 ==> TOUCH_SCREEN_DET# */
 	PAD_CFG_GPO_LOCK(GPP_D2, 1, LOCK_CONFIG),
 	/* D3  : NC ==> PHY_SHUTTER_DET */
@@ -176,8 +176,8 @@ static const struct pad_config gpio_table[] = {
 	PAD_NC(GPP_E7, NONE),
 	/* E8  : GPP_E8 ==> WLAN_DISABLE_L */
 	PAD_CFG_GPO(GPP_E8, 1, DEEP),
-	/* E9  : NC */
-	PAD_NC_LOCK(GPP_E9, NONE, LOCK_CONFIG),
+	/* E9  : GPP_E9 ==> SOC_ACC2_INT# */
+	PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1),
 	/* E10 : NC */
 	PAD_NC_LOCK(GPP_E10, NONE, LOCK_CONFIG),
 	/* E11 : NC */
diff --git a/src/mainboard/google/brya/variants/uldrenite/variant.c b/src/mainboard/google/brya/variants/uldrenite/variant.c
index 9944328dca..ed27bb825f 100644
--- a/src/mainboard/google/brya/variants/uldrenite/variant.c
+++ b/src/mainboard/google/brya/variants/uldrenite/variant.c
@@ -45,6 +45,10 @@ static const struct pad_config ish_disable_pads[] = {
 	PAD_NC(GPP_B5, NONE),
 	/* B6  : GPP_B6 ==> NC */
 	PAD_NC(GPP_B6, NONE),
+	/* D1  : ISH_GP1 ==> NC */
+	PAD_NC(GPP_D1, NONE),
+	/* E9  : SOC_ACC2_INT ==> NC */
+	PAD_NC_LOCK(GPP_E9, NONE, LOCK_CONFIG),
 };
 
 void fw_config_gpio_padbased_override(struct pad_config *padbased_table)

From fb2d62dbd0b16a79ca41fcdcc5708b5c11449b2c Mon Sep 17 00:00:00 2001
From: Naresh Solanki <naresh.solanki@9elements.com>
Date: Mon, 24 Mar 2025 17:45:07 +0530
Subject: [PATCH 0786/3886] soc/amd/common/cpu/noncar: Compute core info boost
 freq & L3 cache

On SoCs like Glinda, CPU cores may exhibit slight variations in
maximum boost frequency, and the L3 cache can be composed of
multiple blocks with different sizes and unique IDs.

Add helper functions,
1. get_max_boost_frequency() to compute max boost frequenncy.
2. ap_stash_core_info() to update core_info struct with max boost
   frequency & all L3 cache block uniq ID & its size.

To accurately determine the total L3 cache size:
1. Retrieve L3 cache information for each CPU core.
2. Identify the unique cache ID associated with each core.
3. Aggregate cache sizes for all unique cache IDs to compute the
   total L3 cache size, ensuring correct summation when L3 cache
   blocks have different sizes.

TEST=Build for Glinda SoC, with L3 cache = 16MB + 8MB. Ran command
'dmidecode -t 7' & verified L3 cache is 24MB(Previously it was
wrongly reported as 32MB).

Change-Id: I46947e8ac62c903036a81642e03201e353c3dac6
Signed-off-by: Naresh Solanki <naresh.solanki@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85640
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/soc/amd/common/block/cpu/noncar/cpu.c | 39 +++++++++++++++++++++++
 1 file changed, 39 insertions(+)

diff --git a/src/soc/amd/common/block/cpu/noncar/cpu.c b/src/soc/amd/common/block/cpu/noncar/cpu.c
index c97e2f4f44..dfa6a69f42 100644
--- a/src/soc/amd/common/block/cpu/noncar/cpu.c
+++ b/src/soc/amd/common/block/cpu/noncar/cpu.c
@@ -9,6 +9,7 @@
 #include <cpu/amd/microcode.h>
 #include <cpu/amd/msr.h>
 #include <cpu/amd/mtrr.h>
+#include <lib.h>
 #include <smbios.h>
 #include <soc/iomap.h>
 #include <soc/msr.h>
@@ -18,6 +19,17 @@
 
 #define UNINITIALIZED ((uint64_t)-1)
 
+struct core_info {
+	/* Core max boost frequency */
+	uint32_t max_frequency;
+
+	/* L3 Cache block unique ID & size (in bytes) */
+	uint16_t l3_cache_uid;
+	size_t l3_cache_size;
+};
+
+static struct core_info core_info_list[CONFIG_MAX_CPUS];
+
 static union pstate_msr get_pstate0_msr(void)
 {
 	static union pstate_msr pstate_reg = { .raw = UNINITIALIZED };
@@ -103,6 +115,30 @@ unsigned int get_reserved_phys_addr_bits(void)
 			CPUID_EBX_MEM_ENCRYPT_ADDR_BITS_SHIFT;
 }
 
+static uint32_t get_max_boost_frequency(void)
+{
+	msr_t msr = rdmsr(MSR_CPPC_CAPABILITY_1);
+	uint16_t nominal_perf = (msr.lo >> SHIFT_CPPC_CAPABILITY_1_NOMINAL_PERF) & 0xff;
+	uint16_t max_perf = (msr.lo >> SHIFT_CPPC_CAPABILITY_1_HIGHEST_PERF) & 0xff;
+
+	return (smbios_cpu_get_current_speed_mhz() * max_perf)/nominal_perf;
+}
+
+static void ap_stash_core_info(void)
+{
+	unsigned int cpuid_cpu_id = cpuid_ebx(CPUID_EBX_CORE_ID) & 0xff;
+
+	const uint8_t level = CACHE_L3;
+	struct cpu_cache_info info;
+	x86_get_cpu_cache_info(level, &info);
+
+	struct core_info *core_info = &core_info_list[cpu_index()];
+	core_info->l3_cache_uid = cpuid_cpu_id >> log2(info.num_cores_shared);
+	core_info->l3_cache_size = info.size;
+
+	core_info->max_frequency = get_max_boost_frequency();
+}
+
 void amd_cpu_init(struct device *dev)
 {
 	if (CONFIG(SOC_AMD_COMMON_BLOCK_MCA_COMMON))
@@ -112,4 +148,7 @@ void amd_cpu_init(struct device *dev)
 
 	if (CONFIG(SOC_AMD_COMMON_BLOCK_UCODE))
 		amd_apply_microcode_patch();
+
+	if (CONFIG(SOC_FILL_CPU_CACHE_INFO))
+		ap_stash_core_info();
 }

From 77fed6f508540e579d5d6e9fecb36f63279e490d Mon Sep 17 00:00:00 2001
From: Maxim Polyakov <max.senia.poliak@gmail.com>
Date: Tue, 14 Jan 2025 21:31:38 +0300
Subject: [PATCH 0787/3886] configs: Add config for Asrock IMB-1222

Change-Id: I5238b90f3d86a106ce28ea395eccad347c9de193
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85984
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 configs/config.asrock_imb1222 | 7 +++++++
 1 file changed, 7 insertions(+)
 create mode 100644 configs/config.asrock_imb1222

diff --git a/configs/config.asrock_imb1222 b/configs/config.asrock_imb1222
new file mode 100644
index 0000000000..613f281861
--- /dev/null
+++ b/configs/config.asrock_imb1222
@@ -0,0 +1,7 @@
+CONFIG_VENDOR_ASROCK=y
+CONFIG_BOARD_ASROCK_IMB_1222=y
+CONFIG_USE_INTEL_FSP_MP_INIT=y
+CONFIG_SOC_INTEL_COMMON_BLOCK_SMM_TCO_ENABLE=y
+CONFIG_RUN_FSP_GOP=y
+CONFIG_PCIEXP_SUPPORT_RESIZABLE_BARS=y
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL_5=y

From c247f62749b967143e58c33aa0e5e234711a628f Mon Sep 17 00:00:00 2001
From: Elyes Haouas <ehaouas@noos.fr>
Date: Sat, 8 Feb 2025 09:46:59 +0100
Subject: [PATCH 0788/3886] tree: remove duplicated includes

Change-Id: Iaf10e1b9fb8ce51605a75ec0a92ee33924c42aa6
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86330
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jayvik Desai <jayvik@google.com>
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
---
 src/commonlib/device_tree.c                               | 1 -
 src/mainboard/emulation/qemu-sbsa/mainboard.c             | 2 --
 src/mainboard/google/dedede/variants/baseboard/ramstage.c | 1 -
 src/northbridge/intel/haswell/broadwell_mrc/raminit.c     | 1 -
 src/soc/amd/genoa_poc/chip.c                              | 1 -
 src/soc/amd/genoa_poc/config.c                            | 1 -
 src/soc/amd/picasso/acpi.c                                | 1 -
 src/soc/intel/apollolake/cpu.c                            | 1 -
 src/soc/intel/denverton_ns/include/soc/pci_devs.h         | 1 -
 src/soc/intel/pantherlake/bootblock/report_platform.c     | 1 -
 util/superiotool/superiotool.h                            | 6 +-----
 11 files changed, 1 insertion(+), 16 deletions(-)

diff --git a/src/commonlib/device_tree.c b/src/commonlib/device_tree.c
index 4d72fb0bbc..b5c0ede7f3 100644
--- a/src/commonlib/device_tree.c
+++ b/src/commonlib/device_tree.c
@@ -10,7 +10,6 @@
 #ifdef __COREBOOT__
 #include <console/console.h>
 #else
-#include <stdio.h>
 #define printk(level, ...) printf(__VA_ARGS__)
 #endif
 #include <stdio.h>
diff --git a/src/mainboard/emulation/qemu-sbsa/mainboard.c b/src/mainboard/emulation/qemu-sbsa/mainboard.c
index 9d64b73c6b..55e4c671e4 100644
--- a/src/mainboard/emulation/qemu-sbsa/mainboard.c
+++ b/src/mainboard/emulation/qemu-sbsa/mainboard.c
@@ -7,8 +7,6 @@
 #include <cbfs.h>
 #include <device/device.h>
 #include <commonlib/device_tree.h>
-#include <bootmem.h>
-#include <arch/mmu.h>
 #include <mainboard/addressmap.h>
 #include <stdint.h>
 #include <symbols.h>
diff --git a/src/mainboard/google/dedede/variants/baseboard/ramstage.c b/src/mainboard/google/dedede/variants/baseboard/ramstage.c
index f5a8f98d62..6833b70e09 100644
--- a/src/mainboard/google/dedede/variants/baseboard/ramstage.c
+++ b/src/mainboard/google/dedede/variants/baseboard/ramstage.c
@@ -6,7 +6,6 @@
 #include <drivers/usb/acpi/chip.h>
 #include <fw_config.h>
 #include <gpio.h>
-#include <soc/pci_devs.h>
 #include <ec/google/chromeec/ec.h>
 #include <device/pci_ops.h>
 #include <intelblocks/power_limit.h>
diff --git a/src/northbridge/intel/haswell/broadwell_mrc/raminit.c b/src/northbridge/intel/haswell/broadwell_mrc/raminit.c
index beae4965ff..5b2427b918 100644
--- a/src/northbridge/intel/haswell/broadwell_mrc/raminit.c
+++ b/src/northbridge/intel/haswell/broadwell_mrc/raminit.c
@@ -14,7 +14,6 @@
 #include <device/device.h>
 #include <device/pci_def.h>
 #include <device/pci_ops.h>
-#include <device/dram/ddr3.h>
 #include <northbridge/intel/haswell/chip.h>
 #include <northbridge/intel/haswell/haswell.h>
 #include <northbridge/intel/haswell/raminit.h>
diff --git a/src/soc/amd/genoa_poc/chip.c b/src/soc/amd/genoa_poc/chip.c
index 98a995fdd2..c76b71661f 100644
--- a/src/soc/amd/genoa_poc/chip.c
+++ b/src/soc/amd/genoa_poc/chip.c
@@ -5,7 +5,6 @@
 #include <device/device.h>
 #include <drivers/amd/opensil/opensil.h>
 #include <soc/southbridge.h>
-#include <soc/southbridge.h>
 
 static void soc_init(void *chip_info)
 {
diff --git a/src/soc/amd/genoa_poc/config.c b/src/soc/amd/genoa_poc/config.c
index eab1ae44bc..600ace6e1f 100644
--- a/src/soc/amd/genoa_poc/config.c
+++ b/src/soc/amd/genoa_poc/config.c
@@ -1,6 +1,5 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
-#include <device/device.h>
 #include <amdblocks/chip.h>
 #include <device/device.h>
 #include <static.h>
diff --git a/src/soc/amd/picasso/acpi.c b/src/soc/amd/picasso/acpi.c
index b95db5de94..d07b38ca57 100644
--- a/src/soc/amd/picasso/acpi.c
+++ b/src/soc/amd/picasso/acpi.c
@@ -19,7 +19,6 @@
 #include <amdblocks/chip.h>
 #include <amdblocks/cpu.h>
 #include <amdblocks/ioapic.h>
-#include <device/device.h>
 #include <soc/pci_devs.h>
 #include <soc/southbridge.h>
 #include "chip.h"
diff --git a/src/soc/intel/apollolake/cpu.c b/src/soc/intel/apollolake/cpu.c
index b8bf39197e..fb95009f7d 100644
--- a/src/soc/intel/apollolake/cpu.c
+++ b/src/soc/intel/apollolake/cpu.c
@@ -13,7 +13,6 @@
 #include <cpu/x86/mtrr.h>
 #include <cpu/x86/smm.h>
 #include <cpu/intel/em64t100_save_state.h>
-#include <cpu/intel/microcode.h>
 #include <cpu/intel/smm_reloc.h>
 #include <device/device.h>
 #include <device/pci.h>
diff --git a/src/soc/intel/denverton_ns/include/soc/pci_devs.h b/src/soc/intel/denverton_ns/include/soc/pci_devs.h
index f62ea2b5c3..5ad39cc3a9 100644
--- a/src/soc/intel/denverton_ns/include/soc/pci_devs.h
+++ b/src/soc/intel/denverton_ns/include/soc/pci_devs.h
@@ -22,7 +22,6 @@
 #if defined(__SIMPLE_DEVICE__)
 #define  SA_DEV_ROOT		PCI_DEV(0, SA_DEV_SLOT_ROOT, 0)
 #else
-#include <device/device.h>
 #define  SA_DEV_ROOT		pcidev_path_on_root(PCI_DEVFN(SA_DEV_SLOT_ROOT, 0))
 #endif
 #define SA_DEV 0x0
diff --git a/src/soc/intel/pantherlake/bootblock/report_platform.c b/src/soc/intel/pantherlake/bootblock/report_platform.c
index aa8b03077a..28ec7473af 100644
--- a/src/soc/intel/pantherlake/bootblock/report_platform.c
+++ b/src/soc/intel/pantherlake/bootblock/report_platform.c
@@ -1,6 +1,5 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
-#include <device/pci_ops.h>
 #include <console/console.h>
 #include <cpu/cpu.h>
 #include <cpu/intel/cpu_ids.h>
diff --git a/util/superiotool/superiotool.h b/util/superiotool/superiotool.h
index ef2bfd6685..1d41e12023 100644
--- a/util/superiotool/superiotool.h
+++ b/util/superiotool/superiotool.h
@@ -9,6 +9,7 @@
 #include <string.h>
 #include <getopt.h>
 #include <commonlib/bsd/helpers.h>
+#include <sys/types.h>
 #if defined(__linux__)
 #include <sys/io.h>
 #endif
@@ -25,11 +26,7 @@
 # endif
 #endif
 
-#include <sys/types.h>
-#include <stdint.h>
-
 #if defined(__FreeBSD__)
-#include <sys/types.h>
 #include <machine/cpufunc.h>
 #define OUTB(x, y) do { u_int tmp = (y); outb(tmp, (x)); } while (0)
 #define OUTW(x, y) do { u_int tmp = (y); outw(tmp, (x)); } while (0)
@@ -47,7 +44,6 @@
 #endif
 
 #if defined(__NetBSD__) && (defined(__i386__) || defined(__x86_64__))
-#include <sys/types.h>
 #include <machine/sysarch.h>
 #if defined(__i386__)
 #define iopl i386_iopl

From 0307f52cd9a907fd15d70311abee3f79eb2bf5bc Mon Sep 17 00:00:00 2001
From: mtk17664 <kun.lu@mediatek.com>
Date: Mon, 14 Apr 2025 09:10:32 +0800
Subject: [PATCH 0789/3886] soc/mediatek/mt8196: Move SPM loader functions to
 common part

To promote code reuse and maintainability, move SPM loader functions to
common/spm_v2.c.

BUG=b:379008996
BRANCH=none
TEST=build passed

Signed-off-by: Kun Lu <kun.lu@mediatek.corp-partner.google.com>
Change-Id: I20de8662d17e3dbedd84f267f2be7d5d62356ecd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87340
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/soc/mediatek/common/spm_v2.c    | 86 +++++++++++++++++++++++++++++
 src/soc/mediatek/mt8196/Makefile.mk |  2 +-
 src/soc/mediatek/mt8196/spm.c       | 81 ---------------------------
 3 files changed, 87 insertions(+), 82 deletions(-)
 create mode 100644 src/soc/mediatek/common/spm_v2.c

diff --git a/src/soc/mediatek/common/spm_v2.c b/src/soc/mediatek/common/spm_v2.c
new file mode 100644
index 0000000000..b101ab0b14
--- /dev/null
+++ b/src/soc/mediatek/common/spm_v2.c
@@ -0,0 +1,86 @@
+/* SPDX-License-Identifier: GPL-2.0-only OR MIT */
+
+#include <delay.h>
+#include <device/mmio.h>
+#include <soc/spm.h>
+
+void spm_reset_and_init_pcm(void)
+{
+	/* disable r0 and r7 to control power */
+	write32(&mtk_spm->pcm_pwr_io_en, 0);
+
+	/* disable pcm timer after leaving FW */
+	clrsetbits32(&mtk_spm->pcm_con1,
+		     REG_PCM_TIMER_EN_LSB, SPM_REGWR_CFG_KEY);
+
+	/* reset PCM */
+	write32(&mtk_spm->pcm_con0,
+		SPM_REGWR_CFG_KEY | PCM_CK_EN_LSB | PCM_SW_RESET_LSB);
+	write32(&mtk_spm->pcm_con0, SPM_REGWR_CFG_KEY | PCM_CK_EN_LSB);
+
+	/* init PCM_CON1 (disable PCM timer but keep PCM WDT setting) */
+	clrsetbits32(&mtk_spm->pcm_con1, ~REG_PCM_WDT_WAKE_LSB,
+		     SPM_REGWR_CFG_KEY | REG_SPM_APB_INTERNAL_EN_LSB |
+		     REG_SSPM_APB_P2P_EN_LSB);
+}
+
+void spm_set_wakeup_event(const struct pwr_ctrl *pwrctrl)
+{
+	u32 val, mask;
+
+	/* toggle event counter clear */
+	write32(&mtk_spm->spm_event_counter_clear, REG_SPM_EVENT_COUNTER_CLR_LSB);
+	/* toggle for reset SYS TIMER start point */
+	setbits32(&mtk_spm->sys_timer_con, SYS_TIMER_START_EN_LSB);
+
+	if (pwrctrl->timer_val_cust == 0)
+		val = pwrctrl->timer_val ? pwrctrl->timer_val : PCM_TIMER_SUSPEND;
+	else
+		val = pwrctrl->timer_val_cust;
+
+	write32(&mtk_spm->pcm_timer_val, val);
+	setbits32(&mtk_spm->pcm_con1, SPM_REGWR_CFG_KEY | REG_PCM_TIMER_EN_LSB);
+
+	/* unmask AP wakeup source */
+	if (pwrctrl->wake_src_cust == 0)
+		mask = pwrctrl->wake_src;
+	else
+		mask = pwrctrl->wake_src_cust;
+
+	if (pwrctrl->reg_csyspwrup_ack_mask)
+		mask &= ~R12_CSYSPWREQ_B;
+	write32(&mtk_spm->spm_wakeup_event_mask, ~mask);
+
+	/* unmask SPM ISR (keep TWAM setting) */
+	setbits32(&mtk_spm->spm_irq_mask, ISRM_RET_IRQ_AUX);
+
+	/* toggle event counter clear */
+	write32(&mtk_spm->spm_event_counter_clear, 0);
+	/* toggle for reset SYS TIMER start point */
+	clrbits32(&mtk_spm->sys_timer_con, SYS_TIMER_START_EN_LSB);
+}
+
+void spm_init_pcm_register(void)
+{
+	write32(&mtk_spm->pcm_pwr_io_en, 0);
+}
+
+void spm_kick_pcm_to_run(const struct pwr_ctrl *pwrctrl)
+{
+	/* Waiting for loading SPMFW done*/
+	while (read32(&mtk_spm->md32pcm_dma0_rlct) != 0x0)
+		;
+
+	/* In the new SOC design, this part has been simplified */
+	spm_set_pcm_flags(pwrctrl);
+
+	/* Kick PCM to run (only toggle PCM_KICK) */
+	setbits32(&mtk_spm->pcm_con0, SPM_REGWR_CFG_KEY | PCM_CK_EN_LSB);
+
+	/* Reset md32pcm */
+	SET32_BITFIELDS(&mtk_spm->md32pcm_cfgreg_sw_rstn,
+			MD32PCM_CFGREG_SW_RSTN_RESET, 1);
+
+	/* Waiting for SPM init done */
+	udelay(SPM_INIT_DONE_US);
+}
diff --git a/src/soc/mediatek/mt8196/Makefile.mk b/src/soc/mediatek/mt8196/Makefile.mk
index 93be1b434b..4a2fdcc970 100644
--- a/src/soc/mediatek/mt8196/Makefile.mk
+++ b/src/soc/mediatek/mt8196/Makefile.mk
@@ -79,7 +79,7 @@ ramstage-y += mtcmos.c
 ramstage-y += ../common/mtk_fsp.c
 ramstage-y += pi_image.c
 ramstage-y += soc.c
-ramstage-y += ../common/spm.c spm.c
+ramstage-y += ../common/spm.c ../common/spm_v2.c spm.c
 ramstage-y += ../common/sspm.c sspm_sram.c
 ramstage-y += ../common/pmif_clk.c pmif_clk.c
 ramstage-y += ../common/pmif.c pmif_init.c
diff --git a/src/soc/mediatek/mt8196/spm.c b/src/soc/mediatek/mt8196/spm.c
index 66964fb866..f6319069b9 100644
--- a/src/soc/mediatek/mt8196/spm.c
+++ b/src/soc/mediatek/mt8196/spm.c
@@ -836,87 +836,6 @@ void spm_register_init(void)
 	spm_set_power_control(&spm_init_ctrl);
 }
 
-void spm_reset_and_init_pcm(void)
-{
-	/* disable r0 and r7 to control power */
-	write32(&mtk_spm->pcm_pwr_io_en, 0);
-
-	/* disable pcm timer after leaving FW */
-	clrsetbits32(&mtk_spm->pcm_con1,
-		     REG_PCM_TIMER_EN_LSB, SPM_REGWR_CFG_KEY);
-
-	/* reset PCM */
-	write32(&mtk_spm->pcm_con0,
-		SPM_REGWR_CFG_KEY | PCM_CK_EN_LSB | PCM_SW_RESET_LSB);
-	write32(&mtk_spm->pcm_con0, SPM_REGWR_CFG_KEY | PCM_CK_EN_LSB);
-
-	/* init PCM_CON1 (disable PCM timer but keep PCM WDT setting) */
-	clrsetbits32(&mtk_spm->pcm_con1, ~REG_PCM_WDT_WAKE_LSB,
-		     SPM_REGWR_CFG_KEY | REG_SPM_APB_INTERNAL_EN_LSB |
-		     REG_SSPM_APB_P2P_EN_LSB);
-}
-
-void spm_set_wakeup_event(const struct pwr_ctrl *pwrctrl)
-{
-	u32 val, mask;
-
-	/* toggle event counter clear */
-	write32(&mtk_spm->spm_event_counter_clear, REG_SPM_EVENT_COUNTER_CLR_LSB);
-	/* toggle for reset SYS TIMER start point */
-	setbits32(&mtk_spm->sys_timer_con, SYS_TIMER_START_EN_LSB);
-
-	if (pwrctrl->timer_val_cust == 0)
-		val = pwrctrl->timer_val ? pwrctrl->timer_val : PCM_TIMER_SUSPEND;
-	else
-		val = pwrctrl->timer_val_cust;
-
-	write32(&mtk_spm->pcm_timer_val, val);
-	setbits32(&mtk_spm->pcm_con1, SPM_REGWR_CFG_KEY | REG_PCM_TIMER_EN_LSB);
-
-	/* unmask AP wakeup source */
-	if (pwrctrl->wake_src_cust == 0)
-		mask = pwrctrl->wake_src;
-	else
-		mask = pwrctrl->wake_src_cust;
-
-	if (pwrctrl->reg_csyspwrup_ack_mask)
-		mask &= ~R12_CSYSPWREQ_B;
-	write32(&mtk_spm->spm_wakeup_event_mask, ~mask);
-
-	/* unmask SPM ISR (keep TWAM setting) */
-	setbits32(&mtk_spm->spm_irq_mask, ISRM_RET_IRQ_AUX);
-
-	/* toggle event counter clear */
-	write32(&mtk_spm->spm_event_counter_clear, 0);
-	/* toggle for reset SYS TIMER start point */
-	clrbits32(&mtk_spm->sys_timer_con, SYS_TIMER_START_EN_LSB);
-}
-
-void spm_init_pcm_register(void)
-{
-	write32(&mtk_spm->pcm_pwr_io_en, 0);
-}
-
-void spm_kick_pcm_to_run(const struct pwr_ctrl *pwrctrl)
-{
-	/* Waiting for loading SPMFW done*/
-	while (read32(&mtk_spm->md32pcm_dma0_rlct) != 0x0)
-		;
-
-	/* In the new SOC design, this part has been simplified */
-	spm_set_pcm_flags(pwrctrl);
-
-	/* Kick PCM to run (only toggle PCM_KICK) */
-	setbits32(&mtk_spm->pcm_con0, SPM_REGWR_CFG_KEY | PCM_CK_EN_LSB);
-
-	/* Reset md32pcm */
-	SET32_BITFIELDS(&mtk_spm->md32pcm_cfgreg_sw_rstn,
-			MD32PCM_CFGREG_SW_RSTN_RESET, 1);
-
-	/* Waiting for SPM init done */
-	udelay(SPM_INIT_DONE_US);
-}
-
 const struct pwr_ctrl *get_pwr_ctrl(void)
 {
 	return &spm_init_ctrl;

From 36c89598a747cd84fc50b85adc9fef05ae94ff74 Mon Sep 17 00:00:00 2001
From: Alicja Michalska <alicja.michalska@9elements.com>
Date: Sun, 20 Apr 2025 03:37:43 +0200
Subject: [PATCH 0790/3886] mb/erying/tgl: fsp_params: Replace half_populated
 with statement

It looks neater, but does the same exact thing.

Change-Id: Id02ba24ec0295cd4621c69079d719d3df36e6499
Signed-off-by: Alicja Michalska <alicja.michalska@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87362
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/erying/tgl/romstage_fsp_params.c | 4 +---
 1 file changed, 1 insertion(+), 3 deletions(-)

diff --git a/src/mainboard/erying/tgl/romstage_fsp_params.c b/src/mainboard/erying/tgl/romstage_fsp_params.c
index 047f6fffe0..cffb53a57d 100644
--- a/src/mainboard/erying/tgl/romstage_fsp_params.c
+++ b/src/mainboard/erying/tgl/romstage_fsp_params.c
@@ -16,8 +16,6 @@ static const struct mem_spd spd_info = {
 	},
 };
 
-const bool half_populated = false;
-
 void mainboard_memory_init_params(FSPM_UPD *mupd)
 {
 	// Performance settings
@@ -70,5 +68,5 @@ void mainboard_memory_init_params(FSPM_UPD *mupd)
 	mupd->FspmConfig.MemTestOnWarmBoot = 1;
 	mupd->FspmConfig.DdrFreqLimit = 3200; // Maximum tested speed.
 
-	memcfg_init(mupd, &mem_config, &spd_info, half_populated);
+	memcfg_init(mupd, &mem_config, &spd_info, false);
 }

From d04d7d80b05b4d18c1a4a0dcfd821becdbd4f341 Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Sun, 6 Apr 2025 15:59:15 -0500
Subject: [PATCH 0791/3886] drivers/intel/mipi_camera: Only generate ADR if no
 HID supplied

It's an ACPI spec violation for a device to have both an _ADR and
a _HID method, so prefer the latter if a HID value is specified
via the chip registers.

Change-Id: I5d84dbea52595e61df56a5ff779d5e0ee0d84bdf
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87248
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/drivers/intel/mipi_camera/camera.c | 5 ++---
 1 file changed, 2 insertions(+), 3 deletions(-)

diff --git a/src/drivers/intel/mipi_camera/camera.c b/src/drivers/intel/mipi_camera/camera.c
index 63a409a300..bf457f5b4e 100644
--- a/src/drivers/intel/mipi_camera/camera.c
+++ b/src/drivers/intel/mipi_camera/camera.c
@@ -844,14 +844,13 @@ static void write_i2c_camera_device(const struct device *dev, const char *scope)
 		acpigen_pop_len(); /* Power Resource */
 	}
 
-	if (config->device_type == INTEL_ACPI_CAMERA_SENSOR)
-		acpigen_write_name_integer("_ADR", 0);
-
 	if (config->acpi_hid)
 		acpigen_write_name_string("_HID", config->acpi_hid);
 	else if (config->device_type == INTEL_ACPI_CAMERA_VCM ||
 		 config->device_type == INTEL_ACPI_CAMERA_NVM)
 		acpigen_write_name_string("_HID", ACPI_DT_NAMESPACE_HID);
+	else if (config->device_type == INTEL_ACPI_CAMERA_SENSOR)
+		acpigen_write_name_integer("_ADR", 0);
 
 	acpigen_write_name_integer("_UID", config->acpi_uid);
 	acpigen_write_name_string("_DDN", config->chip_name);

From fc8e88da9bd9b03da9e84cdf7795db4d1009e7ef Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Tue, 8 Apr 2025 13:01:00 -0500
Subject: [PATCH 0792/3886] drivers/intel/mipi_camera: Rework info print output

Fix the INFO print for a mipi camera device:

- fix device path type for generic devices
- print parent device path and PCI devfn for generic devices
- reformat the output for both device types to improve readability

before:
[INFO ]  \_SB.PCI0.IPU0.IPU0: Intel MIPI Camera Device I2C address 00h
[INFO ]  \_SB.PCI0.I2C3.CAM0: Intel MIPI Camera Device I2C address 010h
[INFO ]  \_SB.PCI0.I2C3.VCM0: Intel MIPI Camera Device I2C address 0ch
[INFO ]  \_SB.PCI0.I2C3.NVM0: Intel MIPI Camera Device I2C address 050h

after:
[INFO ]  \_SB.PCI0.IPU0: Intel MIPI Camera Device at PCI 05.0
[INFO ]  \_SB.PCI0.I2C3.CAM0: Intel MIPI Camera Device at I2C 0x10
[INFO ]  \_SB.PCI0.I2C3.VCM0: Intel MIPI Camera Device at I2C 0x0c
[INFO ]  \_SB.PCI0.I2C3.NVM0: Intel MIPI Camera Device at I2C 0x50

Change-Id: I5c4a072e35c4e0a14b6df0d5f199c5ffb3d61d32
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87249
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
---
 src/drivers/intel/mipi_camera/camera.c | 13 ++++++-------
 1 file changed, 6 insertions(+), 7 deletions(-)

diff --git a/src/drivers/intel/mipi_camera/camera.c b/src/drivers/intel/mipi_camera/camera.c
index bf457f5b4e..4268646de8 100644
--- a/src/drivers/intel/mipi_camera/camera.c
+++ b/src/drivers/intel/mipi_camera/camera.c
@@ -930,10 +930,9 @@ static void camera_fill_ssdt(const struct device *dev)
 {
 	struct drivers_intel_mipi_camera_config *config = dev->chip_info;
 	const char *scope = NULL;
-	const struct device *pdev;
+	const struct device *pdev = dev->upstream->dev;
 
 	if (config->has_power_resource) {
-		pdev = dev->upstream->dev;
 		if (!pdev || !pdev->enabled)
 			return;
 
@@ -957,7 +956,6 @@ static void camera_fill_ssdt(const struct device *dev)
 		write_i2c_camera_device(dev, scope);
 		break;
 	case DEVICE_PATH_GENERIC:
-		pdev = dev->upstream->dev;
 		scope = acpi_device_scope(pdev);
 		if (!scope)
 			return;
@@ -976,11 +974,12 @@ static void camera_fill_ssdt(const struct device *dev)
 	acpigen_pop_len(); /* Device */
 	acpigen_pop_len(); /* Scope */
 
-	if (dev->path.type == DEVICE_PATH_PCI) {
-		printk(BIOS_INFO, "%s: %s PCI address 0%x\n", acpi_device_path(dev),
-		       dev->chip_ops->name, dev->path.pci.devfn);
+	if (dev->path.type == DEVICE_PATH_GENERIC) {
+		printk(BIOS_INFO, "%s: %s at PCI %02x.%01x\n", acpi_device_path(pdev),
+		       dev->chip_ops->name, PCI_SLOT(pdev->path.pci.devfn),
+		       PCI_FUNC(pdev->path.pci.devfn));
 	} else {
-		printk(BIOS_INFO, "%s: %s I2C address 0%xh\n", acpi_device_path(dev),
+		printk(BIOS_INFO, "%s: %s at I2C 0x%02x\n", acpi_device_path(dev),
 		       dev->chip_ops->name, dev->path.i2c.device);
 	}
 }

From a1210875e9fe76e5ba6be029bd7bd08a8349e343 Mon Sep 17 00:00:00 2001
From: Maxim Polyakov <max.senia.poliak@gmail.com>
Date: Thu, 9 Jan 2025 16:43:27 +0300
Subject: [PATCH 0793/3886] mb/imb-1222: Update some GPIOs according to new
 vendor config

The memory dump was done for the 1.80 (2023-04-07) version of the
vendor's UEFI.

Change-Id: I649e2c3ae715651b5f0eadc9b52e61e4deae77a1
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85928
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
---
 src/mainboard/asrock/imb-1222/gpio.c | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/src/mainboard/asrock/imb-1222/gpio.c b/src/mainboard/asrock/imb-1222/gpio.c
index 549b716fee..19f14f8655 100644
--- a/src/mainboard/asrock/imb-1222/gpio.c
+++ b/src/mainboard/asrock/imb-1222/gpio.c
@@ -147,15 +147,15 @@ static const struct pad_config gpio_table[] = {
 	PAD_CFG_GPO(GPP_K3, 0, PLTRST),
 	PAD_CFG_GPO(GPP_K4, 1, PLTRST),
 	PAD_CFG_GPO(GPP_K5, 1, PLTRST),
-	PAD_NC(GPP_K6, NONE),
-	PAD_NC(GPP_K7, NONE),
+	PAD_CFG_GPO(GPP_K6, 0, RSMRST),
+	PAD_CFG_GPO(GPP_K7, 0, RSMRST),
 	PAD_CFG_GPO(GPP_K8, 0, PLTRST),
 	PAD_CFG_GPO(GPP_K9, 0, PLTRST),
 	PAD_CFG_GPO(GPP_K10, 0, PLTRST),
 	PAD_CFG_GPO(GPP_K11, 0, PLTRST),
 	PAD_CFG_GPI_SCI(GPP_K12, NONE, PLTRST, EDGE_SINGLE, INVERT),
 	PAD_NC(GPP_K13, NONE),
-	PAD_CFG_GPO(GPP_K14, 0, DEEP),
+	PAD_CFG_GPO(GPP_K14, 1, DEEP),
 	PAD_CFG_GPI_TRIG_OWN(GPP_K15, NONE, PLTRST, OFF, ACPI),
 	PAD_CFG_GPO(GPP_K16, 0, PLTRST),
 	PAD_CFG_GPI_TRIG_OWN(GPP_K17, NONE, PLTRST, OFF, ACPI),
@@ -247,7 +247,7 @@ static const struct pad_config gpio_table[] = {
 	PAD_CFG_NF(GPP_I9, NONE, PLTRST, NF1),		/* DDPD_CTRLCLK */
 	PAD_CFG_NF(GPP_I10, NONE, PLTRST, NF1),		/* DDPD_CTRLDATA */
 	PAD_NC(GPP_I11, NONE),
-	PAD_CFG_GPO(GPP_I12, 1, PLTRST),
+	PAD_CFG_GPO(GPP_I12, 0, PLTRST),
 	PAD_NC(GPP_I13, NONE),
 	PAD_CFG_GPO(GPP_I14, 1, PLTRST),
 

From eb68ff66ebd7a38d5b0f44e8100589f1ca0babd5 Mon Sep 17 00:00:00 2001
From: Maxim Polyakov <max.senia.poliak@gmail.com>
Date: Thu, 9 Jan 2025 16:05:09 +0300
Subject: [PATCH 0794/3886] mb/asrock/imb-1222: Update GPIO config using new
 intelp2m

- use intelp2m, 2.5-a48e94c74b version;
- add missing VGPIO groups.

Change-Id: I351a32962561947296b115af96674a4cd1cb192d
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85919
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
---
 src/mainboard/asrock/imb-1222/gpio.c | 99 +++++++++++++++++++++++++++-
 1 file changed, 98 insertions(+), 1 deletion(-)

diff --git a/src/mainboard/asrock/imb-1222/gpio.c b/src/mainboard/asrock/imb-1222/gpio.c
index 19f14f8655..2c26bf3bfd 100644
--- a/src/mainboard/asrock/imb-1222/gpio.c
+++ b/src/mainboard/asrock/imb-1222/gpio.c
@@ -4,7 +4,7 @@
 #include <mainboard/gpio.h>
 
 /*
- * Pad configuration was generated automatically using intelp2m utility
+ * Pad configuration was generated automatically using intelp2m 2.5-a48e94c74b
  * [*] - allow FSP to configure this pad
  */
 static const struct pad_config gpio_table[] = {
@@ -60,6 +60,7 @@ static const struct pad_config gpio_table[] = {
 	PAD_NC(GPP_B21, NONE),
 	PAD_CFG_GPO(GPP_B22, 0, PLTRST),
 	PAD_CFG_GPO(GPP_B23, 0, PLTRST),
+	PAD_CFG_NF(GSPI0_CLK_LOOPBK, NONE, DEEP, NF1),	/* GSPI0_CLK_LOOPBK */
 
 	/* ------- GPIO Community 1 ------- */
 	/* ------- GPIO Group GPP_C ------- */
@@ -124,6 +125,60 @@ static const struct pad_config gpio_table[] = {
 	PAD_NC(GPP_G6, NONE),
 	PAD_NC(GPP_G7, NONE),
 
+	/* ------- GPIO Group AZA ------- */
+	PAD_CFG_NF(HDA_BCLK, NATIVE, DEEP, NF1),	/* HDA_BCLK */
+	PAD_CFG_NF(HDA_RST_B, NATIVE, DEEP, NF1),	/* HDA_RST# */
+	PAD_CFG_NF(HDA_SYNC, NATIVE, DEEP, NF1),	/* HDA_SYNC */
+	PAD_CFG_NF(HDA_SDO, NATIVE, DEEP, NF1),		/* HDA_SDO */
+	PAD_CFG_NF(HDA_SDI0, NATIVE, DEEP, NF1),	/* HDA_SDI0 */
+	PAD_CFG_NF(HDA_SDI1, NATIVE, DEEP, NF1),	/* HDA_SDI1 */
+	PAD_CFG_NF(I2S1_SFRM, NATIVE, DEEP, NF1),	/* I2S1_SFRM */
+	PAD_CFG_NF(I2S1_TXD, NATIVE, DEEP, NF1),	/* I2S1_TXD */
+
+	/* ------- GPIO Group VGPIO_0 ------- */
+	PAD_CFG_GPO(CNV_BTEN, 0, DEEP),
+	PAD_CFG_GPIO_BIDIRECT(CNV_GNEN, 0, NONE, DEEP, LEVEL, ACPI),
+	PAD_CFG_GPIO_BIDIRECT(CNV_WFEN, 0, NONE, DEEP, LEVEL, ACPI),
+	PAD_CFG_GPIO_BIDIRECT(CNV_WCEN, 1, NONE, DEEP, LEVEL, ACPI),
+	PAD_CFG_GPI_TRIG_OWN(vCNV_GNSS_HOST_WAKE_B, NONE, DEEP, OFF, ACPI),
+	PAD_CFG_GPIO_BIDIRECT(vSD3_CD_B, 0, NONE, DEEP, OFF, ACPI),
+	PAD_CFG_GPIO_BIDIRECT(CNV_BT_HOST_WAKE_B, 0, NONE, DEEP, OFF, ACPI),
+	PAD_CFG_GPIO_BIDIRECT(CNV_BT_IF_SELECT, 1, NONE, DEEP, LEVEL, ACPI),
+	PAD_CFG_NF(vCNV_BT_UART_TXD, NONE, DEEP, NF1),
+	PAD_CFG_NF(vCNV_BT_UART_RXD, NONE, DEEP, NF1),
+	PAD_CFG_NF(vCNV_BT_UART_CTS_B, NONE, DEEP, NF1),
+	PAD_CFG_NF(vCNV_BT_UART_RTS_B, NONE, DEEP, NF1),
+	PAD_CFG_NF(vCNV_MFUART1_TXD, NONE, DEEP, NF1),
+	PAD_CFG_NF(vCNV_MFUART1_RXD, NONE, DEEP, NF1),
+	PAD_CFG_NF(vCNV_MFUART1_CTS_B, NONE, DEEP, NF1),
+	PAD_CFG_NF(vCNV_MFUART1_RTS_B, NONE, DEEP, NF1),
+	PAD_CFG_NF(vCNV_GNSS_UART_TXD, NONE, DEEP, NF1),
+	PAD_CFG_NF(vCNV_GNSS_UART_RXD, NONE, DEEP, NF1),
+	PAD_CFG_NF(vCNV_GNSS_UART_CTS_B, NONE, DEEP, NF1),
+	PAD_CFG_NF(vCNV_GNSS_UART_RTS_B, NONE, DEEP, NF1),
+	PAD_CFG_NF(vUART0_TXD, NONE, DEEP, NF1),
+	PAD_CFG_NF(vUART0_RXD, NONE, DEEP, NF1),
+	PAD_CFG_NF(vUART0_CTS_B, NONE, DEEP, NF1),
+	PAD_CFG_NF(vUART0_RTS_B, NONE, DEEP, NF1),
+	PAD_CFG_NF(vISH_UART0_TXD, NONE, DEEP, NF1),
+	PAD_CFG_NF(vISH_UART0_RXD, NONE, DEEP, NF1),
+	PAD_CFG_NF(vISH_UART0_CTS_B, NONE, DEEP, NF1),
+	PAD_CFG_NF(vISH_UART0_RTS_B, NONE, DEEP, NF1),
+	PAD_CFG_NF(vISH_UART1_TXD, NONE, DEEP, NF1),
+	PAD_CFG_NF(vISH_UART1_RXD, NONE, DEEP, NF1),
+	PAD_CFG_NF(vISH_UART1_CTS_B, NONE, DEEP, NF1),
+	PAD_CFG_NF(vISH_UART1_RTS_B, NONE, DEEP, NF1),
+
+	/* ------- GPIO Group VGPIO_1 ------- */
+	PAD_CFG_NF(vCNV_BT_I2S_BCLK, NONE, DEEP, NF1),
+	PAD_CFG_NF(vCNV_BT_I2S_WS_SYNC, NONE, DEEP, NF1),
+	PAD_CFG_NF(vCNV_BT_I2S_SDO, NONE, DEEP, NF1),
+	PAD_CFG_NF(vCNV_BT_I2S_SDI, NONE, DEEP, NF1),
+	PAD_CFG_NF(vSSP2_SCLK, NONE, DEEP, NF1),
+	PAD_CFG_NF(vSSP2_SFRM, NONE, DEEP, NF1),
+	PAD_CFG_NF(vSSP2_TXD, NONE, DEEP, NF1),
+	PAD_CFG_NF(vSSP2_RXD, NONE, DEEP, NF1),
+
 	/* ------- GPIO Community 2 ------- */
 	/* ------- GPIO Group GPD ------- */
 	PAD_CFG_NF(GPD0, NONE, RSMRST, NF1),		/* BATLOW# */
@@ -138,6 +193,10 @@ static const struct pad_config gpio_table[] = {
 	PAD_CFG_NF(GPD9, NONE, RSMRST, NF1),		/* SLP_WLAN# */
 	PAD_CFG_NF(GPD10, NONE, RSMRST, NF1),		/* SLP_S5# */
 	PAD_CFG_NF(GPD11, NONE, RSMRST, NF1),		/* LANPHYPC */
+	PAD_CFG_NF(SLP_LAN_B, NONE, RSMRST, NF1),	/* SLP_LAN# */
+	PAD_CFG_NF(SLP_SUS_B, NONE, RSMRST, NF1),	/* SLP_SUS# */
+	PAD_CFG_NF(WAKE_B, NONE, RSMRST, NF1),		/* WAKE# */
+	PAD_CFG_NF(DRAM_RESET_B, NONE, RSMRST, NF1),	/* DRAM_RESET# */
 
 	/* ------- GPIO Community 3 ------- */
 	/* ------- GPIO Group GPP_K ------- */
@@ -233,7 +292,42 @@ static const struct pad_config gpio_table[] = {
 	PAD_NC(GPP_F22, NONE),
 	PAD_CFG_GPO(GPP_F23, 0, PLTRST),
 
+	/* ------- GPIO Group SPI ------- */
+	PAD_CFG_NF(SPI0_IO_2, NATIVE, DEEP, NF1),	/* SPI0_IO_2 */
+	PAD_CFG_NF(SPI0_IO_3, NATIVE, DEEP, NF1),	/* SPI0_IO_3 */
+	PAD_CFG_NF(SPI0_MISO, NATIVE, DEEP, NF1),	/* SPI0_MISO */
+	PAD_CFG_NF(SPI0_MOSI, NATIVE, DEEP, NF1),	/* SPI0_MOSI */
+	PAD_CFG_NF(SPI0_CS2_B, NATIVE, DEEP, NF1),	/* SPI0_CS2# */
+	PAD_CFG_NF(SPI0_CS0_B, NATIVE, DEEP, NF1),	/* SPI0_CS0# */
+	PAD_CFG_NF(SPI0_CS1_B, NATIVE, DEEP, NF1),	/* SPI0_CS1# */
+	PAD_CFG_NF(SPI0_CLK, NATIVE, DEEP, NF1),	/* SPI0_CLK */
+	PAD_CFG_NF(SPI0_CLK_LOOPBK, NONE, DEEP, NF1),	/* SPI0_CLK_LOOPBK */
+
 	/* ------- GPIO Community 4 ------- */
+	/* ------- GPIO Group CPU ------- */
+	PAD_CFG_NF(HDACPU_SDI, NATIVE, DEEP, NF1),	/* HDACPU_SDI */
+	PAD_CFG_NF(HDACPU_SDO, NATIVE, DEEP, NF1),	/* HDACPU_SDO */
+	PAD_CFG_NF(HDACPU_SCLK, NATIVE, DEEP, NF1),	/* HDACPU_SCLK */
+	PAD_CFG_NF(PM_SYNC, NONE, DEEP, NF1),		/* PM_SYNC */
+	PAD_CFG_NF(PECI_IO, NONE, DEEP, NF1),		/* PECI_IO */
+	PAD_CFG_NF(CPUPWRGD, NONE, DEEP, NF1),		/* CPUPWRG# */
+	PAD_CFG_NF(THRMTRIP_B, NONE, DEEP, NF1),	/* THRMTRIP# */
+	PAD_CFG_NF(PLTRST_CPU_B, NONE, DEEP, NF1),	/* PLTRST_CPU# */
+	PAD_CFG_NF(PM_DOWN, NONE, DEEP, NF1),		/* PM_DOWN */
+	PAD_CFG_NF(TRIGGER_IN, DN_20K, DEEP, NF1),	/* TRIGGER_IN */
+	PAD_CFG_NF(TRIGGER_OUT, DN_20K, DEEP, NF1),	/* TRIGGER_OUT */
+
+	/* ------- GPIO Group JTAG ------- */
+	PAD_CFG_NF(PCH_TDO, NATIVE, DEEP, NF1),		/* PCH_TDO */
+	PAD_CFG_NF(PCH_JTAGX, NATIVE, DEEP, NF1),	/* PCH_JTAGX */
+	PAD_CFG_NF(PROC_PRDY_B, NATIVE, DEEP, NF1),	/* PROC_RDY# */
+	PAD_CFG_NF(PROC_PREQ_B, NATIVE, DEEP, NF1),	/* PROC_REQ# */
+	PAD_CFG_NF(CPU_TRST_B, NATIVE, DEEP, NF1),	/* CPU_TRST# */
+	PAD_CFG_NF(PCH_TDI, NATIVE, DEEP, NF1),		/* PCH_TDI */
+	PAD_CFG_NF(PCH_TMS, NATIVE, DEEP, NF1),		/* PCH_TMS */
+	PAD_CFG_NF(PCH_TCK, NATIVE, DEEP, NF1),		/* PCH_TCK */
+	PAD_CFG_NF(ITP_PMODE, NATIVE, DEEP, NF1),	/* ITP_PMODE */
+
 	/* ------- GPIO Group GPP_I ------- */
 	PAD_CFG_NF(GPP_I0, NONE, PLTRST, NF1),		/* DDPB_HPD0 */
 	PAD_CFG_NF(GPP_I1, NONE, PLTRST, NF1),		/* DDPB_HPD1 */
@@ -250,6 +344,9 @@ static const struct pad_config gpio_table[] = {
 	PAD_CFG_GPO(GPP_I12, 0, PLTRST),
 	PAD_NC(GPP_I13, NONE),
 	PAD_CFG_GPO(GPP_I14, 1, PLTRST),
+	PAD_CFG_NF(SYS_PWROK, NONE, DEEP, NF1),		/* SYS_PWROK */
+	PAD_CFG_NF(SYS_RESET_B, NONE, DEEP, NF1),	/* SYS_RESET# */
+	PAD_CFG_NF(CL_RST_B, NONE, DEEP, NF1),		/* CL_RST# */
 
 	/* ------- GPIO Group GPP_J ------- */
 	PAD_CFG_NF(GPP_J0, NONE, PLTRST, NF1),		/* CNV_PA_BLANKING */

From ac7717a7b0b0ffb8bcf570d947215bf584258e02 Mon Sep 17 00:00:00 2001
From: Maxim Polyakov <max.senia.poliak@gmail.com>
Date: Sun, 13 Apr 2025 00:02:28 +0300
Subject: [PATCH 0795/3886] mainboard/asrock/imb-1222: Enable USB3 port in WWAN
 slot

TEST=connect Sandisk USB 3.1 flash via converter (M.2 Key-B to USB3.0);
boot ubuntu 24.04 and run "Benchmark Partition" in the Disks utility;
average read rate = 161.1 MB/s (20 samples/10 MiB).

Change-Id: Iba5d1d7c4f8180e3d37348c1c4dafce6f6c68cb4
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87293
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
---
 src/mainboard/asrock/imb-1222/devicetree.cb | 24 ++++++++++++++++-----
 1 file changed, 19 insertions(+), 5 deletions(-)

diff --git a/src/mainboard/asrock/imb-1222/devicetree.cb b/src/mainboard/asrock/imb-1222/devicetree.cb
index 8edbf62934..216a60f8fb 100644
--- a/src/mainboard/asrock/imb-1222/devicetree.cb
+++ b/src/mainboard/asrock/imb-1222/devicetree.cb
@@ -72,6 +72,7 @@ chip soc/intel/cannonlake
 				[3] = USB2_PORT_MID(OC_SKIP),		/* Front (USB3_4) */
 				[4] = USB2_PORT_MID(OC_SKIP),		/* Rear  (USB3_5) */
 				[5] = USB2_PORT_MID(OC_SKIP),   	/* Rear  (USB3_6) */
+				[6] = USB2_PORT_MID(OC_SKIP),		/* WWAN  (M.2 Key-B 3042/3052) */
 				[7] = USB2_PORT_MID(OC_SKIP),		/* Front (USB2_8_9) */
 				[8] = USB2_PORT_MID(OC_SKIP),		/* Front (USB2_8_9) */
 				[10] = USB2_PORT_MID(OC_SKIP),		/* Front (USB2_11_12) */
@@ -83,6 +84,7 @@ chip soc/intel/cannonlake
 				[1] = USB3_PORT_DEFAULT(OC_SKIP),	/* Rear  (USB3_2) */
 				[2] = USB3_PORT_DEFAULT(OC_SKIP),	/* Front (USB3_3) */
 				[3] = USB3_PORT_DEFAULT(OC_SKIP),	/* Front (USB3_4) */
+				[4] = USB3_PORT_DEFAULT(OC_SKIP),	/* WWAN  (M.2 Key-B 3042/3052) */
 				[6] = USB3_PORT_DEFAULT(OC_SKIP),	/* Rear  (USB3_5) */
 				[7] = USB3_PORT_DEFAULT(OC_SKIP),	/* Rear  (USB3_6) */
 			}"
@@ -161,34 +163,46 @@ chip soc/intel/cannonlake
 						register "group" = "ACPI_PLD_GROUP(0, 5)"
 						device ref usb3_port8 on  end
 					end
+					chip drivers/usb/acpi
+						register "desc"  = ""M.2 WWAN""
+						register "type"  = "UPC_TYPE_INTERNAL"
+						register "group" = "ACPI_PLD_GROUP(0, 6)"
+						device ref usb2_port7 on  end
+					end
+					chip drivers/usb/acpi
+						register "desc"  = ""M.2 WWAN""
+						register "type"  = "UPC_TYPE_INTERNAL"
+						register "group" = "ACPI_PLD_GROUP(0, 6)"
+						device ref usb3_port5 on  end
+					end
 					chip drivers/usb/acpi
 						register "desc"  = ""USB2_8 Front""
 						register "type"  = "UPC_TYPE_A"
-						register "group" = "ACPI_PLD_GROUP(0, 6)"
+						register "group" = "ACPI_PLD_GROUP(0, 7)"
 						device ref usb2_port8 on  end
 					end
 					chip drivers/usb/acpi
 						register "desc"  = ""USB2_9 Front""
 						register "type"  = "UPC_TYPE_A"
-						register "group" = "ACPI_PLD_GROUP(0, 7)"
+						register "group" = "ACPI_PLD_GROUP(0, 8)"
 						device ref usb2_port9 on  end
 					end
 					chip drivers/usb/acpi
 						register "desc"  = ""USB2_11 Front""
 						register "type"  = "UPC_TYPE_A"
-						register "group" = "ACPI_PLD_GROUP(0, 8)"
+						register "group" = "ACPI_PLD_GROUP(0, 9)"
 						device ref usb2_port11 on  end
 					end
 					chip drivers/usb/acpi
 						register "desc"  = ""USB2_12 Front""
 						register "type"  = "UPC_TYPE_A"
-						register "group" = "ACPI_PLD_GROUP(0, 9)"
+						register "group" = "ACPI_PLD_GROUP(0, 10)"
 						device ref usb2_port12 on  end
 					end
 					chip drivers/usb/acpi
 						register "desc"  = ""M.2 Bluetooth""
 						register "type"  = "UPC_TYPE_INTERNAL"
-						register "group" = "ACPI_PLD_GROUP(0, 10)"
+						register "group" = "ACPI_PLD_GROUP(0, 11)"
 						device ref usb2_port14 on  end
 					end
 				end

From c7a450ba7ddecee4a992966954d0fe4facb1bff0 Mon Sep 17 00:00:00 2001
From: Maxim Polyakov <max.senia.poliak@gmail.com>
Date: Sun, 13 Apr 2025 13:56:58 +0300
Subject: [PATCH 0796/3886] Documentation/mainboard/asrock/imb-1222.md: Update
 information

- some formatting fixes;
- add information about proprietary blobs;
- update information about the tested hardware and operating systems.

Change-Id: I85a8f1df2ffc6e0e1674c4b82888a3964aa8d672
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87295
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
---
 Documentation/mainboard/asrock/imb-1222.md | 93 ++++++++++++++++------
 1 file changed, 70 insertions(+), 23 deletions(-)

diff --git a/Documentation/mainboard/asrock/imb-1222.md b/Documentation/mainboard/asrock/imb-1222.md
index b4238b9a13..5ef934753e 100644
--- a/Documentation/mainboard/asrock/imb-1222.md
+++ b/Documentation/mainboard/asrock/imb-1222.md
@@ -5,24 +5,24 @@ This page describes how to run coreboot on the [ASRock IMB-1222].
 ## Technology
 
 ```{eval-rst}
-+------------+---------------------------------------------------------------+
-| CPU        | Intel 10th Gen (Comet lake-S) Core Processors (LGA-1200)      |
-|            | CPUs over 80W will be limited due to power design             |
-+------------+---------------------------------------------------------------+
-| DRAM       | 2 SO-DIMM slots, DDR4 2933/2666/2400 MHz                      |
-+------------+---------------------------------------------------------------+
-| Chipset    | Intel Q470E                                                   |
-+------------+---------------------------------------------------------------+
-| Super I/O  | Fintek F81966                                                 |
-+------------+---------------------------------------------------------------+
-| TPM        | Infineon SLB 9670VQ2.0                                        |
-+------------+---------------------------------------------------------------+
-| Boot       | USB, SATA, NVMe                                               |
-+------------+---------------------------------------------------------------+
-| Power      | Laptop Power Supply:                                          |
-|            | - 12V DC-in (IMB-1222)                                        |
-|            | - 12V~28V DC-in (IMB-1222-WV)                                 |
-+------------+---------------------------------------------------------------+
++---------+---------------------------------------------------------------+
+| CPU     | | Intel 10th Gen (Comet lake-S) Core Processors (LGA-1200)    |
+|         | | CPUs over 80W will be limited due to power design           |
++---------+---------------------------------------------------------------+
+| DRAM    | 2 SO-DIMM slots, DDR4 2933/2666/2400 MHz                      |
++---------+---------------------------------------------------------------+
+| Chipset | Intel Q470E                                                   |
++---------+---------------------------------------------------------------+
+| SuperIO | Fintek F81966                                                 |
++---------+---------------------------------------------------------------+
+| TPM     | Infineon SLB 9670VQ2.0                                        |
++---------+---------------------------------------------------------------+
+| Boot    | USB, SATA, NVMe                                               |
++---------+---------------------------------------------------------------+
+| Power   | | Laptop Power Supply:                                        |
+|         | | - 12V DC-in (IMB-1222)                                      |
+|         | | - 12V~28V DC-in (IMB-1222-WV)                               |
++---------+---------------------------------------------------------------+
 ```
 
 ```text
@@ -70,7 +70,7 @@ This page describes how to run coreboot on the [ASRock IMB-1222].
                     |    ALC122    |                  | LPC
                     +--------------+           +--------------+
 +-----------------------+   +--------------+   |              |    +------------+
-| 2 x COM RS232/422/482 |---|   ST3243E    |---|    Fintek    |----| CPU FAN x1 |
+| 2 x COM RS232/422/485 |---|   ST3243E    |---|    Fintek    |----| CPU FAN x1 |
 +-----------------------+   +--------------+   |    F81966    |    +------------+
 +-----------------------+   +--------------+   |    SuperIO   |    +------------+
 | 2 x COM RS232         |---|   ST3243E    |---|              |----| NCT 3941SA |
@@ -85,6 +85,48 @@ This page describes how to run coreboot on the [ASRock IMB-1222].
 This port was created without a schematic/boardview, reverse engineering only.
 Feel free to make changes.
 
+## Required proprietary blobs
+
+To build full working image of coreboot, the following blobs are required:
+
+```{eval-rst}
++-----------------+-------------------------------------------+-------------------------+
+| Binary file     | Apply                                     | Required/Optional       |
++=================+===========================================+=========================+
+| FSP-M & FSP-S   | | Intel Firmware Support Package 2.1      | Required                |
+|                 | | 10th Generation Intel® Core™ processors |                         |
+|                 | | and chipsets (formerly Comet Lake)      |                         |
++-----------------+-------------------------------------------+-------------------------+
+| IFD             | Intel Flash Descriptor                    | Required                |
++-----------------+-------------------------------------------+-------------------------+
+| ME              | Intel Management Engine                   | Required                |
++-----------------+-------------------------------------------+-------------------------+
+| GBE             | Gigabit Ethernet Configuration            | | Optional              |
+|                 |                                           | | (if LAN2 is enabled)  |
++-----------------+-------------------------------------------+-------------------------+
+```
+
+### FSP
+
+Intel company provides [Firmware Support Package (2.1)](../../soc/intel/fsp/index.md)
+to initialize this generation silicon. Please see this
+[document](../../soc/intel/code_development_model/code_development_model.md).
+
+### IFD, ME, GBE
+
+Use the [vendor's firmware] version 1.80 to extract the IFD, ME, GBE blobs from it, according to
+the [Intel IFD Binary Extraction Tutorial](../../util/ifdtool/binary_extraction.md).
+
+```bash
+wget --tries=5 "https://web.archive.org/web/20250413105432/https://download.asrock.com/IPC/BIOS/IMB-1222(1.80)ROM.zip"
+unzip "IMB-1222(1.80)ROM.zip"
+ifdtool --platform cnl -x IM12221.80
+File IM12221.80 is 33554432 bytes
+  flashregion_0_flashdescriptor.bin  Flash Region 0 (Flash Descriptor): 00000000 - 00000fff
+  flashregion_2_intel_me.bin         Flash Region 2 (Intel ME):         00003000 - 01002fff
+  flashregion_3_gbe.bin              Flash Region 3 (GbE):              00001000 - 00002fff
+```
+
 ## Building coreboot
 
 The following commands will help quickly configure and build a project for this board:
@@ -110,6 +152,8 @@ make
 +---------------+------+---------+-----------+
 | Windows 10    |  V   |         |           |
 +---------------+------+---------+-----------+
+| Windows 11    |  V   |         |           |
++---------------+------+---------+-----------+
 | Android 13    |      |    V    |           |
 +---------------+------+---------+-----------+
 ```
@@ -118,9 +162,12 @@ make
 - SeaBIOS (1.16.3);
 - edk2 [MrChromebox fork] (uefipayload_2408).
 
+### Additional information
+
 - Ubuntu 22.04 (Linux 6.5.0-15-generic);
 - Ubuntu 24.04 (Linux 6.8.0-41-generic);
 - Microsoft Windows 10 Pro (10.0.19045.4780, 22H2 2022);
+- Microsoft Windows 11 Pro (10.0.26100.3194, 24H2 2024);
 - Andoid 13, [Bliss OS] x86_64 (16.9.7, Linux 6.1.112-gloria-xanmod1).
 
 ## Flashing coreboot
@@ -131,8 +178,8 @@ make
 +=====================+==========================+
 | Socketed flash      | yes                      |
 +---------------------+--------------------------+
-| Model               | W25Q256JV                |
-|                     | MX25L25673G              |
+| Model               | | W25Q256JV              |
+|                     | | MX25L25673G            |
 +---------------------+--------------------------+
 | Size                | 32 MiB                   |
 +---------------------+--------------------------+
@@ -171,7 +218,7 @@ information about this [here](../../tutorial/flashing_firmware/index.md).
 - USB 2.0 ports;
 - USB 3.2 ports;
 - M.2 Key-E 2230 slot for Wireless (PCIe x1, USB 2.0 and CNVi);
-- M.2 Key-B 3042/3052 slot for 4G/5G modem (PCIe x1);
+- M.2 Key-B 3042/3052 WWAN slot for 4G/5G modem (PCIe x1, USB 3.0);
 - M.2 Key-M 2242/2260/2280 for SSD/NVMe (PCIE x4, SATA3);
 - LAN1 Intel I225LM/I225V, 10/100/1000/2500 Mbps;
 - LAN2 Intel I219LM, 10/100/1000 Mbps;
@@ -185,13 +232,13 @@ information about this [here](../../tutorial/flashing_firmware/index.md).
 
 ## Unknown/untested
 
-- USB 3.0 in M.2 Key-B 3042/3052 slot (currently disabled);
 - eDP/LVDS (currently disabled);
 - PCIe riser cards;
 - SPDIF;
 - SATA RAID.
 
 [ASRock IMB-1222]: https://web.archive.org/web/20220924171403/https://www.asrockind.com/en-gb/IMB-1222
+[vendor's firmware]: https://web.archive.org/web/20250413105432/https://download.asrock.com/IPC/BIOS/IMB-1222(1.80)ROM.zip
 [flashrom]: https://flashrom.org/Flashrom
 [MrChromebox fork]: https://github.com/MrChromebox/edk2
 [XutaxKamay fork]: https://github.com/XutaxKamay/me_cleaner

From 430ab9257b8f2156dca7e69673f30fb105d4afb6 Mon Sep 17 00:00:00 2001
From: Rui Zhou <zhourui@huaqin.corp-partner.google.com>
Date: Mon, 21 Apr 2025 15:50:14 +0800
Subject: [PATCH 0797/3886] spd/lp5: Add SPD for K3KL8L80EM-MGCU

Add K3KL8L80DM-MGCU in the memory_parts.json
and re-generate the SPD

Samsung:K3KL8L80EM-MGCU

BUG=b:412237636
TEST=util/spd_tools/bin/spd_gen spd/lp5/memory_parts.json lp5

Change-Id: I34c8d8e1fc7b8aa107bc181f51b5dc2ff287aa4c
Signed-off-by: Rui Zhou <zhourui@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87395
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
---
 spd/lp5/memory_parts.json                      | 11 +++++++++++
 spd/lp5/set-0/parts_spd_manifest.generated.txt |  1 +
 spd/lp5/set-1/parts_spd_manifest.generated.txt |  1 +
 3 files changed, 13 insertions(+)

diff --git a/spd/lp5/memory_parts.json b/spd/lp5/memory_parts.json
index 2e00140115..1c34505056 100644
--- a/spd/lp5/memory_parts.json
+++ b/spd/lp5/memory_parts.json
@@ -284,6 +284,17 @@
                 "speedMbps": 8533,
                 "lp5x": true
             }
+        }，
+        {
+            "name":  "K3KL8L80EM-MGCU",
+            "attribs": {
+                "densityPerDieGb": 16,
+                "diesPerPackage": 2,
+                "bitWidthPerChannel": 16,
+                "ranksPerChannel": 1,
+                "speedMbps": 8533,
+                "lp5x": true
+            }
         }
     ]
 }
diff --git a/spd/lp5/set-0/parts_spd_manifest.generated.txt b/spd/lp5/set-0/parts_spd_manifest.generated.txt
index 6af57e2fa9..f560ba3f1a 100644
--- a/spd/lp5/set-0/parts_spd_manifest.generated.txt
+++ b/spd/lp5/set-0/parts_spd_manifest.generated.txt
@@ -28,3 +28,4 @@ MT62F1G32D2DS-023 WT:C,spd-11.hex
 K3KL8L80DM-MGCU,spd-11.hex
 MT62F2G32D4DS-020 WT:F,spd-10.hex
 H58G56CK8BX146,spd-11.hex
+K3KL8L80EM-MGCU,spd-11.hex
diff --git a/spd/lp5/set-1/parts_spd_manifest.generated.txt b/spd/lp5/set-1/parts_spd_manifest.generated.txt
index 6af57e2fa9..f560ba3f1a 100644
--- a/spd/lp5/set-1/parts_spd_manifest.generated.txt
+++ b/spd/lp5/set-1/parts_spd_manifest.generated.txt
@@ -28,3 +28,4 @@ MT62F1G32D2DS-023 WT:C,spd-11.hex
 K3KL8L80DM-MGCU,spd-11.hex
 MT62F2G32D4DS-020 WT:F,spd-10.hex
 H58G56CK8BX146,spd-11.hex
+K3KL8L80EM-MGCU,spd-11.hex

From 3ce612194c7922aee51f59d28e4bfde480560c3a Mon Sep 17 00:00:00 2001
From: Rui Zhou <zhourui@huaqin.corp-partner.google.com>
Date: Mon, 21 Apr 2025 16:03:34 +0800
Subject: [PATCH 0798/3886] mb/google/rex: Generate RAM IDs

Generate RAM IDs for K3KL8L80DM-MGCU

BUG=b:412237636
BRANCH=None
TEST=Run part_id_gen tool without any errors

Change-Id: Ie3f87f5920942060e8e9f8fcf34c3124ba79f3da
Signed-off-by: Rui Zhou <zhourui@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87396
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
---
 src/mainboard/google/rex/variants/screebo/memory/Makefile.mk     | 1 +
 .../google/rex/variants/screebo/memory/dram_id.generated.txt     | 1 +
 .../google/rex/variants/screebo/memory/mem_parts_used.txt        | 1 +
 3 files changed, 3 insertions(+)

diff --git a/src/mainboard/google/rex/variants/screebo/memory/Makefile.mk b/src/mainboard/google/rex/variants/screebo/memory/Makefile.mk
index 5b38bfc96c..d633b43bef 100644
--- a/src/mainboard/google/rex/variants/screebo/memory/Makefile.mk
+++ b/src/mainboard/google/rex/variants/screebo/memory/Makefile.mk
@@ -8,3 +8,4 @@ SPD_SOURCES += spd/lp5/set-0/spd-1.hex      # ID = 0(0b0000)  Parts = MT62F512M3
 SPD_SOURCES += spd/lp5/set-0/spd-7.hex      # ID = 1(0b0001)  Parts = MT62F1G32D2DS-026 WT:B, H58G56BK7BX068, K3KL8L80CM-MGCT
 SPD_SOURCES += spd/lp5/set-0/spd-8.hex      # ID = 2(0b0010)  Parts = K3KL9L90CM-MGCT
 SPD_SOURCES += spd/lp5/set-0/spd-9.hex      # ID = 3(0b0011)  Parts = K3KL6L60GM-MGCT
+SPD_SOURCES += spd/lp5/set-0/spd-11.hex      # ID = 4(0b0100)  Parts = K3KL8L80EM-MGCU
diff --git a/src/mainboard/google/rex/variants/screebo/memory/dram_id.generated.txt b/src/mainboard/google/rex/variants/screebo/memory/dram_id.generated.txt
index b1172e6b65..a7e4fe684f 100644
--- a/src/mainboard/google/rex/variants/screebo/memory/dram_id.generated.txt
+++ b/src/mainboard/google/rex/variants/screebo/memory/dram_id.generated.txt
@@ -11,3 +11,4 @@ H58G56BK7BX068                 1 (0001)
 K3KL9L90CM-MGCT                2 (0010)
 K3KL6L60GM-MGCT                3 (0011)
 K3KL8L80CM-MGCT                1 (0001)
+K3KL8L80EM-MGCU                4 (0100)
diff --git a/src/mainboard/google/rex/variants/screebo/memory/mem_parts_used.txt b/src/mainboard/google/rex/variants/screebo/memory/mem_parts_used.txt
index 5757ad7b75..7d8cfba3d1 100644
--- a/src/mainboard/google/rex/variants/screebo/memory/mem_parts_used.txt
+++ b/src/mainboard/google/rex/variants/screebo/memory/mem_parts_used.txt
@@ -16,3 +16,4 @@ H58G56BK7BX068
 K3KL9L90CM-MGCT
 K3KL6L60GM-MGCT
 K3KL8L80CM-MGCT
+K3KL8L80EM-MGCU

From 2f62dd8a6b4059787e90dade7c753c5d7e06dab6 Mon Sep 17 00:00:00 2001
From: Kapil Porwal <kapilporwal@google.com>
Date: Thu, 17 Apr 2025 00:26:14 +0530
Subject: [PATCH 0799/3886] mb/google/brya/var/uldrenite: Configure ISH_GP5
 GPIO

BUG=b:410645679

Change-Id: I25285e7a7ae92a19f8750d30661930c4d6c2e1d2
Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87345
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Jayvik Desai <jayvik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Pranava Y N <pranavayn@google.com>
Reviewed-by: Yuval Peress <peress@google.com>
---
 src/mainboard/google/brya/variants/uldrenite/gpio.c    | 4 ++--
 src/mainboard/google/brya/variants/uldrenite/variant.c | 2 ++
 2 files changed, 4 insertions(+), 2 deletions(-)

diff --git a/src/mainboard/google/brya/variants/uldrenite/gpio.c b/src/mainboard/google/brya/variants/uldrenite/gpio.c
index 900daea2e0..3695ad0d23 100644
--- a/src/mainboard/google/brya/variants/uldrenite/gpio.c
+++ b/src/mainboard/google/brya/variants/uldrenite/gpio.c
@@ -34,8 +34,8 @@ static const struct pad_config gpio_table[] = {
 	PAD_CFG_NF(GPP_A14, NONE, DEEP, NF1),
 	/* A15 : USB_OC2# ==> NC */
 	PAD_NC(GPP_A15, NONE),
-	/* A16 : USB_OC3# ==> NC */
-	PAD_NC_LOCK(GPP_A16, NONE, LOCK_CONFIG),
+	/* A16 : ISH_GP5 */
+	PAD_CFG_NF(GPP_A16, NONE, DEEP, NF2),
 	/* A17 : GPP_A17 ==> GSC_SOC_INT_ODL */
 	PAD_CFG_GPI_APIC(GPP_A17, NONE, PLTRST, LEVEL, INVERT),
 	/* A18 : DDSP_HPDB ==> NC */
diff --git a/src/mainboard/google/brya/variants/uldrenite/variant.c b/src/mainboard/google/brya/variants/uldrenite/variant.c
index ed27bb825f..532752837f 100644
--- a/src/mainboard/google/brya/variants/uldrenite/variant.c
+++ b/src/mainboard/google/brya/variants/uldrenite/variant.c
@@ -41,6 +41,8 @@ static const struct pad_config lte_disable_pads[] = {
 };
 
 static const struct pad_config ish_disable_pads[] = {
+	/* A16 : ISH_GP5 ==> NC */
+	PAD_NC_LOCK(GPP_A16, NONE, LOCK_CONFIG),
 	/* B5  : GPP_B5 ==> NC */
 	PAD_NC(GPP_B5, NONE),
 	/* B6  : GPP_B6 ==> NC */

From 6322be799218a54b2df49b4f3d2a6dd7007d68ba Mon Sep 17 00:00:00 2001
From: Keith Hui <buurin@gmail.com>
Date: Sun, 20 Apr 2025 15:14:27 -0400
Subject: [PATCH 0800/3886] sb/intel/bd82x6x/me.h: Add missing definitions
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Two ME current working state definitions are missing. They are
needed for CB:85413. Get them from intelmetool.

Change-Id: Ie163c4b29155e3fd44f0cb3096f825c84da37559
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87394
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/southbridge/intel/bd82x6x/me.h | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/src/southbridge/intel/bd82x6x/me.h b/src/southbridge/intel/bd82x6x/me.h
index a1e688dbdd..4edaad9739 100644
--- a/src/southbridge/intel/bd82x6x/me.h
+++ b/src/southbridge/intel/bd82x6x/me.h
@@ -21,6 +21,8 @@
 #define  ME_HFS_CWS_RESET	0
 #define  ME_HFS_CWS_INIT	1
 #define  ME_HFS_CWS_REC		2
+#define  ME_HFS_CWS_TEST	3
+#define  ME_HFS_CWS_DISABLED	4
 #define  ME_HFS_CWS_NORMAL	5
 #define  ME_HFS_CWS_WAIT	6
 #define  ME_HFS_CWS_TRANS	7

From d14ebe39574d7e1779a1176dc6bfb6c86c013c17 Mon Sep 17 00:00:00 2001
From: Tongtong Pan <pantongtong@huaqin.corp-partner.google.com>
Date: Mon, 21 Apr 2025 10:12:37 +0800
Subject: [PATCH 0801/3886] mb/google/fatcat/var/felino: Use GPP_C08 for
 GPIO_PCH_WP

Use GPP_C08 as the GPIO_PCH_WP.

BUG=b:409472563
Test=TEST=wp status update verified by toggling it on and off.

Change-Id: I0f6c7c051b2d38a787fe3bb21266a6ef6ebc487b
Signed-off-by: Tongtong Pan <pantongtong@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87413
Reviewed-by: Pranava Y N <pranavayn@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
---
 .../fatcat/variants/baseboard/fatcat/include/baseboard/gpio.h   | 2 +-
 src/mainboard/google/fatcat/variants/felino/gpio.c              | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/mainboard/google/fatcat/variants/baseboard/fatcat/include/baseboard/gpio.h b/src/mainboard/google/fatcat/variants/baseboard/fatcat/include/baseboard/gpio.h
index 6934bf12a7..65186d5a44 100644
--- a/src/mainboard/google/fatcat/variants/baseboard/fatcat/include/baseboard/gpio.h
+++ b/src/mainboard/google/fatcat/variants/baseboard/fatcat/include/baseboard/gpio.h
@@ -27,7 +27,7 @@
 #define GPIO_SLP_S0_GATE	GPP_F23
 #elif CONFIG(BOARD_GOOGLE_FELINO)
  #define EC_SYNC_IRQ	GPP_E03_IRQ
- #define GPIO_PCH_WP	0 /* TODO */
+ #define GPIO_PCH_WP	GPP_C08
 /* Used to gate SoC's SLP_S0# signal */
 #define GPIO_SLP_S0_GATE	GPP_D03
 #elif CONFIG(BOARD_GOOGLE_KINMEN)
diff --git a/src/mainboard/google/fatcat/variants/felino/gpio.c b/src/mainboard/google/fatcat/variants/felino/gpio.c
index a7df5fccb7..ac36ab9b00 100644
--- a/src/mainboard/google/fatcat/variants/felino/gpio.c
+++ b/src/mainboard/google/fatcat/variants/felino/gpio.c
@@ -117,7 +117,7 @@ static const struct pad_config gpio_table[] = {
 	/* GPP_C07:     NC */
 	PAD_NC(GPP_C07, NONE),
 	/* GPP_C08:     PCH_WP_OD */
-	PAD_CFG_GPO(GPP_C08, 1, PLTRST),
+	PAD_CFG_GPI(GPP_C08, NONE, DEEP),
 	/* GPP_C09:     PCIE_CLKREQ_SSD1_N */
 	PAD_CFG_NF(GPP_C09, NONE, DEEP, NF1),
 	/* GPP_C10:     NC */

From 14b66cb01b5fbbb3e55c5b6b042efab3cf6f013c Mon Sep 17 00:00:00 2001
From: Sowmya Aralguppe <sowmya.aralguppe@intel.com>
Date: Mon, 21 Apr 2025 22:17:58 +0530
Subject: [PATCH 0802/3886] soc/intel/pantherlake: Add new SoC config for Intel
 Wildcat Lake(WCL)

TEST=Compiled and Verified on Wildcat Lake Simulation Platform.

Change-Id: Ifd5bb19dd41c9e44b5399f570d4e21f03d5fce18
Signed-off-by: Sowmya Aralguppe <sowmya.aralguppe@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87402
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Pranava Y N <pranavayn@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
---
 src/soc/intel/pantherlake/Kconfig | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/src/soc/intel/pantherlake/Kconfig b/src/soc/intel/pantherlake/Kconfig
index b325aaf4c7..b1bff143a9 100644
--- a/src/soc/intel/pantherlake/Kconfig
+++ b/src/soc/intel/pantherlake/Kconfig
@@ -125,6 +125,12 @@ config SOC_INTEL_PANTHERLAKE_H
 	help
 	  Choose this option if the mainboard is built using PTL-H 4Xe system-on-a-chip (SoC).
 
+config SOC_INTEL_WILDCATLAKE
+	bool
+	select SOC_INTEL_PANTHERLAKE_U_H
+	help
+	  Choose this option if the mainboard is built using WCL system-on-a-chip (SoC).
+
 if SOC_INTEL_PANTHERLAKE_BASE
 
 config SOC_INTEL_PANTHERLAKE_TCSS_USB4_SUPPORT

From 7814b8a6bec6e7777033bfd9785b9012b52a73f6 Mon Sep 17 00:00:00 2001
From: Yidi Lin <yidilin@chromium.org>
Date: Tue, 22 Apr 2025 15:57:42 +0800
Subject: [PATCH 0803/3886] Revert "soc/mediatek/mt8196: Specify MTKLIB_PATH
 for building BL31"

This reverts commit 2fdfa504377f0032c6d1c99fb9febcf824a413d3.

Reason for revert: libbl31.a is under refactoring. Stop linking to this
library before finalizing the binary. This patch will be re-landed when
the binary is ready.

BUG=b:412560091

Change-Id: Ie2c315141a51f30027414cfe59552cb50f2b52f6
Signed-off-by: Yidi Lin <yidilin@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87414
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/soc/mediatek/mt8196/Makefile.mk | 6 ------
 1 file changed, 6 deletions(-)

diff --git a/src/soc/mediatek/mt8196/Makefile.mk b/src/soc/mediatek/mt8196/Makefile.mk
index 4a2fdcc970..a1ee6fb304 100644
--- a/src/soc/mediatek/mt8196/Makefile.mk
+++ b/src/soc/mediatek/mt8196/Makefile.mk
@@ -95,12 +95,6 @@ CPPFLAGS_common += -Isrc/soc/mediatek/common/dp/include
 
 MT8196_BLOB_DIR := 3rdparty/blobs/soc/mediatek/mt8196
 
-BL31_LIB := $(top)/$(MT8196_BLOB_DIR)/libbl31.a
-
-ifneq ($(wildcard $(BL31_LIB)),)
-BL31_MAKEARGS += MTKLIB_PATH=$(BL31_LIB)
-endif
-
 PI_IMG := $(MT8196_BLOB_DIR)/$(call strip_quotes,$(CONFIG_PI_IMG_FIRMWARE))
 
 .PHONY: check_pi_img

From 0cc0e6996c8ef2e46bc776f405c8384077f90225 Mon Sep 17 00:00:00 2001
From: Krystian Hebel <krystian.hebel@3mdeb.com>
Date: Wed, 26 Jun 2024 19:52:19 +0200
Subject: [PATCH 0804/3886] drivers/smmstore: allow full flash access for
 capsule updates
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

With DRIVERS_EFI_UPDATE_CAPSULES enabled and when at least one capsule
was found, SMMSTORE SMI handler can use commands with the highest
bit (0x80) set to access the whole flash instead of just the SMMSTORE
region. The rest of the interface is identical to regular SMMSTORE v2
except for a new call to control full flash access.

The added call saves information about the availability of capsules in
SMM memory. The call is ignored when run more than once, meaning there
should be no way of enabling full flash handling after it was disabled
and vice versa. The call should always be made by the firmware to lock
further calls, so that an OS could not gain full flash access. This is
done on entry to BS_POST_DEVICE after capsules are obtained in
BS_DEV_INIT.

Change-Id: I7f3dbfa965b9dcbade8b2f06a5bd2ac1345c7972
Signed-off-by: Krystian Hebel <krystian.hebel@3mdeb.com>
Signed-off-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83424
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
---
 Documentation/drivers/smmstorev2.md | 39 +++++++++++++++++++++++++++++
 src/drivers/efi/capsules.c          | 16 +++++++++++-
 src/drivers/smmstore/smi.c          |  3 +++
 src/drivers/smmstore/store.c        | 35 ++++++++++++++++++++++++++
 src/include/smmstore.h              | 12 +++++++++
 5 files changed, 104 insertions(+), 1 deletion(-)

diff --git a/Documentation/drivers/smmstorev2.md b/Documentation/drivers/smmstorev2.md
index af6e0ce7a6..cf714835a5 100644
--- a/Documentation/drivers/smmstorev2.md
+++ b/Documentation/drivers/smmstorev2.md
@@ -197,6 +197,45 @@ coreboot tables, there's no risk that a malicious application capable
 of issuing SMIs could extract arbitrary data or modify the currently
 running kernel.
 
+## Capsule update API
+
+Availability of this command is tied to `CONFIG_DRIVERS_EFI_UPDATE_CAPSULES`.
+
+To allow updating full flash content (except if locked at hardware
+level), few new calls were added. They reuse communication buffer, SMI
+command, return values and calling arguments of SMMSTORE commands listed
+above, with the exception of subcommand passed via `%ah`. If the
+subcommand is to operate on full flash size, it has the highest bit set,
+e.g. it is `0x85` for `SMMSTORE_CMD_RAW_READ` and `0x86` for
+`SMMSTORE_CMD_RAW_WRITE`. Every `block_id` describes block relative to
+the beginning of a flash, maximum value depends on its size.
+
+Attempts to write the protected memory regions can lead to undesired
+consequences ranging from system instability to bricking and security
+vulnerabilities. When this feature is used, care must be taken to temporarily
+lift protections for the duration of an update when the whole flash is
+rewritten or the update must be constrained to affect only writable portions of
+the flash (e.g., "BIOS" region).
+
+There is one new subcommand that must be called before any other subcommands
+with highest bit set can be used.
+
+### - SMMSTORE_CMD_USE_FULL_FLASH = 0x80
+
+This command can only be executed once and is done by the firmware.
+Calling this function at runtime has no effect. It takes one additional
+parameter that, contrary to other commands, isn't a pointer. Instead,
+`%ebx` indicates requested state of full flash access. If it equals 0,
+commands for accessing full flash are permanently disabled, otherwise
+they are permanently enabled until the next boot.
+
+The assumption is that if capsule updates are enabled at build time and
+whole flash access is enabled at runtime, a UEFI payload (highly likely
+EDK2 or its derivative) won't allow a regular OS to boot if the handler is
+enabled without rebooting first. There could be a way of deactivating the
+handler, but coreboot, having no way of enforcing its usage, might as well
+permit access until a reboot and rely on the payload to do the right thing.
+
 ## External links
 
 * [A Tour Beyond BIOS Implementing UEFI Authenticated Variables in SMM with EDK II](https://github.com/tianocore-docs/Docs/raw/master/White_Papers/A_Tour_Beyond_BIOS_Implementing_UEFI_Authenticated_Variables_in_SMM_with_EDKII_V2.pdf)
diff --git a/src/drivers/efi/capsules.c b/src/drivers/efi/capsules.c
index e8078bbd48..c92438311c 100644
--- a/src/drivers/efi/capsules.c
+++ b/src/drivers/efi/capsules.c
@@ -10,9 +10,10 @@
 #include <drivers/efi/efivars.h>
 #include <drivers/efi/capsules.h>
 #include <memrange.h>
+#include <smm_call.h>
+#include <smmstore.h>
 #include <string.h>
 #include <stdio.h>
-#include <smmstore.h>
 #include <types.h>
 
 #include <Uefi/UefiSpec.h>
@@ -786,3 +787,16 @@ static void parse_capsules(void *unused)
 BOOT_STATE_INIT_ENTRY(BS_DEV_INIT, BS_ON_EXIT, parse_capsules, NULL);
 
 #endif
+
+static void enable_capsule_smi(void *unused)
+{
+	uint32_t ret;
+
+	ret = call_smm(APM_CNT_SMMSTORE, SMMSTORE_CMD_USE_FULL_FLASH,
+		       (void *)(uintptr_t)uefi_capsule_count);
+
+	printk(BIOS_INFO, "%sabled capsule update SMI handler\n",
+	       ret == SMMSTORE_RET_SUCCESS ? "En" : "Dis");
+}
+
+BOOT_STATE_INIT_ENTRY(BS_POST_DEVICE, BS_ON_ENTRY, enable_capsule_smi, NULL);
diff --git a/src/drivers/smmstore/smi.c b/src/drivers/smmstore/smi.c
index 4f7b4bdac0..3ac52dc345 100644
--- a/src/drivers/smmstore/smi.c
+++ b/src/drivers/smmstore/smi.c
@@ -138,6 +138,9 @@ static uint32_t smmstorev2_exec(uint8_t command, void *param)
 
 uint32_t smmstore_exec(uint8_t command, void *param)
 {
+	if (smmstore_preprocess_cmd(&command, param))
+		return SMMSTORE_RET_SUCCESS;
+
 	if (command != SMMSTORE_CMD_CLEAR && !param)
 		return SMMSTORE_RET_FAILURE;
 
diff --git a/src/drivers/smmstore/store.c b/src/drivers/smmstore/store.c
index f1e07e41dd..35887b3c7f 100644
--- a/src/drivers/smmstore/store.c
+++ b/src/drivers/smmstore/store.c
@@ -41,8 +41,43 @@ _Static_assert(SMM_BLOCK_SIZE <= FMAP_SECTION_SMMSTORE_SIZE,
  * crash/reboot could clear out all variables.
  */
 
+static int smmstore_use_full_flash;
+static int has_capsules = -1;
+
+int smmstore_preprocess_cmd(uint8_t *cmd, void *param)
+{
+	if (CONFIG(DRIVERS_EFI_UPDATE_CAPSULES)) {
+		if (has_capsules == -1 && *cmd == SMMSTORE_CMD_USE_FULL_FLASH) {
+			has_capsules = !!(uintptr_t)param;
+			/*
+			 * If we have capsules, return success, otherwise let smmstore_exec()
+			 * fail on !param check, which will be 0 in that case. This informs
+			 * the caller whether capsule handling was enabled or not.
+			 */
+			return has_capsules;
+		} else if (has_capsules == 1 && *cmd & SMMSTORE_CMD_USE_FULL_FLASH) {
+			smmstore_use_full_flash = 1;
+			*cmd &= ~SMMSTORE_CMD_USE_FULL_FLASH;
+		} else {
+			smmstore_use_full_flash = 0;
+		}
+	}
+
+	return 0;
+}
+
 static enum cb_err lookup_store_region(struct region *region)
 {
+	if (CONFIG(DRIVERS_EFI_UPDATE_CAPSULES) && smmstore_use_full_flash) {
+		const struct region_device *rdev = boot_device_rw();
+
+		if (rdev == NULL)
+			return CB_ERR;
+
+		*region = *region_device_region(rdev);
+		return CB_SUCCESS;
+	}
+
 	if (fmap_locate_area(SMMSTORE_REGION, region)) {
 		printk(BIOS_WARNING,
 		       "smm store: Unable to find SMM store FMAP region '%s'\n",
diff --git a/src/include/smmstore.h b/src/include/smmstore.h
index 6805cbc069..595fe8b29b 100644
--- a/src/include/smmstore.h
+++ b/src/include/smmstore.h
@@ -21,6 +21,16 @@
 #define SMMSTORE_CMD_RAW_WRITE 6
 #define SMMSTORE_CMD_RAW_CLEAR 7
 
+/*
+ * Used by capsule updates as a standalone command or modifier to v2 commands.
+ *
+ * Availability depends on CONFIG(DRIVERS_EFI_UPDATE_CAPSULES). Usage of this
+ * extension requires considering which portions of the flash is read-only or
+ * otherwise protected to avoid causing problems while trying to overwrite
+ * them.
+ */
+#define SMMSTORE_CMD_USE_FULL_FLASH 0x80
+
 /* Version 1 */
 struct smmstore_params_read {
 	void *buf;
@@ -117,6 +127,8 @@ int smmstore_get_info(struct smmstore_params_info *info);
 #endif
 struct region_device;
 int smmstore_lookup_region(struct region_device *rstore);
+/* Returns 0 if normal parsing should continue, 1 otherwise */
+int smmstore_preprocess_cmd(uint8_t *cmd, void *param);
 
 /* Advertise SMMSTORE v2 support */
 struct lb_header;

From c4e60501462500027741dc14ce6b89671c169320 Mon Sep 17 00:00:00 2001
From: Cong Yang <yangcong5@huaqin.corp-partner.google.com>
Date: Mon, 21 Apr 2025 17:27:47 +0800
Subject: [PATCH 0805/3886] mb/google/skywalker: Create variant Obiwan

Create the variant Obiwan.

BUG=b:406115783
TEST=emerge-skywalker coreboot
BRANCH=None

Change-Id: Ic3478653cee2906117b69aa7335864a0c7b95b29
Signed-off-by: Cong Yang <yangcong5@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87397
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/google/skywalker/Kconfig      | 4 +++-
 src/mainboard/google/skywalker/Kconfig.name | 3 +++
 2 files changed, 6 insertions(+), 1 deletion(-)

diff --git a/src/mainboard/google/skywalker/Kconfig b/src/mainboard/google/skywalker/Kconfig
index b3da5482b2..fcf37dda14 100644
--- a/src/mainboard/google/skywalker/Kconfig
+++ b/src/mainboard/google/skywalker/Kconfig
@@ -2,7 +2,8 @@
 
 # Umbrella option to be selected by variant boards.
 config BOARD_GOOGLE_SKYWALKER_COMMON
-	def_bool BOARD_GOOGLE_SKYWALKER
+	def_bool BOARD_GOOGLE_OBIWAN || \
+		 BOARD_GOOGLE_SKYWALKER
 
 if BOARD_GOOGLE_SKYWALKER_COMMON
 
@@ -26,6 +27,7 @@ config MAINBOARD_DIR
 
 config MAINBOARD_PART_NUMBER
 	string
+	default "Obiwan" if BOARD_GOOGLE_OBIWAN
 	default "Skywalker" if BOARD_GOOGLE_SKYWALKER
 
 config BOOT_DEVICE_SPI_FLASH_BUS
diff --git a/src/mainboard/google/skywalker/Kconfig.name b/src/mainboard/google/skywalker/Kconfig.name
index 0fc672d2db..eb0e7c0c9e 100644
--- a/src/mainboard/google/skywalker/Kconfig.name
+++ b/src/mainboard/google/skywalker/Kconfig.name
@@ -2,5 +2,8 @@
 
 comment "Skywalker"
 
+config BOARD_GOOGLE_OBIWAN
+	bool "->  Obiwan"
+
 config BOARD_GOOGLE_SKYWALKER
 	bool "->  Skywalker"

From 439d7fb7d00cb1ae1b7ac2536412a70b91c169a4 Mon Sep 17 00:00:00 2001
From: Yunlong Jia <yunlong.jia@ecs.corp-partner.google.com>
Date: Fri, 28 Mar 2025 10:20:41 +0000
Subject: [PATCH 0806/3886] mb/google/brya: Create epic variant

Create the epic variant of the nissa reference board by copying
the template files to a new directory named for the variant.

This variant is a Nirul project,support TWL devices and select
BOARD_GOOGLE_BASEBOARD_NISSA.

DRAM Part Name                 ID to assign
MT62F512M32D2DR-031 WT:B       0 (0000)
H58G56AK6BX069                 1 (0001)
K3LKBKB0BM-MGCP                2 (0010)
H9JCNNNBK3MLYR-N6E             0 (0000)
H9JCNNNCP3MLYR-N6E             3 (0011)

BUG=404301972
BRANCH=None
TEST=util/abuild/abuild -p none -t google/brya -x -a
make sure the build includes GOOGLE_EPIC

Signed-off-by: Yunlong Jia <yunlong.jia@ecs.corp-partner.google.com>
Change-Id: I09e5f3c28b95ae8ef318b7af1dd8634279345ce0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87041
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Jayvik Desai <jayvik@google.com>
---
 src/mainboard/google/brya/Kconfig             |  13 +
 src/mainboard/google/brya/Kconfig.name        |   3 +
 .../google/brya/variants/epic/Makefile.mk     |  11 +
 .../google/brya/variants/epic/fw_config.c     |  43 ++
 .../google/brya/variants/epic/gpio.c          | 100 ++++
 .../brya/variants/epic/include/variant/ec.h   |   8 +
 .../brya/variants/epic/include/variant/gpio.h |  12 +
 .../brya/variants/epic/memory/Makefile.mk     |  10 +
 .../epic/memory/dram_id.generated.txt         |  11 +
 .../variants/epic/memory/mem_parts_used.txt   |  17 +
 .../google/brya/variants/epic/overridetree.cb | 556 ++++++++++++++++++
 .../google/brya/variants/epic/variant.c       |  29 +
 12 files changed, 813 insertions(+)
 create mode 100644 src/mainboard/google/brya/variants/epic/Makefile.mk
 create mode 100644 src/mainboard/google/brya/variants/epic/fw_config.c
 create mode 100644 src/mainboard/google/brya/variants/epic/gpio.c
 create mode 100644 src/mainboard/google/brya/variants/epic/include/variant/ec.h
 create mode 100644 src/mainboard/google/brya/variants/epic/include/variant/gpio.h
 create mode 100644 src/mainboard/google/brya/variants/epic/memory/Makefile.mk
 create mode 100644 src/mainboard/google/brya/variants/epic/memory/dram_id.generated.txt
 create mode 100644 src/mainboard/google/brya/variants/epic/memory/mem_parts_used.txt
 create mode 100644 src/mainboard/google/brya/variants/epic/overridetree.cb
 create mode 100644 src/mainboard/google/brya/variants/epic/variant.c

diff --git a/src/mainboard/google/brya/Kconfig b/src/mainboard/google/brya/Kconfig
index 931cef4218..014d939160 100644
--- a/src/mainboard/google/brya/Kconfig
+++ b/src/mainboard/google/brya/Kconfig
@@ -753,6 +753,15 @@ config BOARD_GOOGLE_ZYDRON
 	select SOC_INTEL_COMMON_BLOCK_IPU
 	select SOC_INTEL_RAPTORLAKE
 
+config BOARD_GOOGLE_EPIC
+	select BOARD_GOOGLE_BASEBOARD_NISSA
+	select DRIVERS_GENERIC_GPIO_KEYS
+	select DRIVERS_GENESYSLOGIC_GL9750
+	select DRIVERS_I2C_SX9324
+	select DRIVERS_I2C_SX9324_SUPPORT_LEGACY_LINUX_DRIVER
+	select HAVE_WWAN_POWER_SEQUENCE
+	select SOC_INTEL_TWINLAKE
+
 if BOARD_GOOGLE_BRYA_COMMON
 
 config BASEBOARD_DIR
@@ -851,6 +860,7 @@ config DRIVER_TPM_I2C_BUS
 	default 0x0 if BOARD_GOOGLE_TELITH
 	default 0x0 if BOARD_GOOGLE_PUJJOGATWIN
 	default 0x0 if BOARD_GOOGLE_MELIKS
+	default 0x0 if BOARD_GOOGLE_EPIC
 
 config DRIVER_TPM_I2C_ADDR
 	hex
@@ -935,6 +945,7 @@ config TPM_TIS_ACPI_INTERRUPT
 	default 13 if BOARD_GOOGLE_TELITH
 	default 13 if BOARD_GOOGLE_PUJJOGATWIN
 	default 13 if BOARD_GOOGLE_MELIKS
+	default 13 if BOARD_GOOGLE_EPIC
 
 config OVERRIDE_DEVICETREE
 	default "variants/\$(CONFIG_VARIANT_DIR)/overridetree_pujjogatwin.cb" if BOARD_GOOGLE_PUJJOGATWIN
@@ -1027,6 +1038,7 @@ config MAINBOARD_PART_NUMBER
 	default "Telith" if BOARD_GOOGLE_TELITH
 	default "Pujjogatwin" if BOARD_GOOGLE_PUJJOGATWIN
 	default "Meliks" if BOARD_GOOGLE_MELIKS
+	default "Epic" if BOARD_GOOGLE_EPIC
 
 config VARIANT_DIR
 	default "agah" if BOARD_GOOGLE_AGAH
@@ -1104,6 +1116,7 @@ config VARIANT_DIR
 	default "telith" if BOARD_GOOGLE_TELITH
 	default "pujjoga" if BOARD_GOOGLE_PUJJOGATWIN
 	default "meliks" if BOARD_GOOGLE_MELIKS
+	default "epic" if BOARD_GOOGLE_EPIC
 
 config VBOOT
 	select VBOOT_EARLY_EC_SYNC if !(BOARD_GOOGLE_BASEBOARD_NISSA || BOARD_GOOGLE_BASEBOARD_TRULO) || BOARD_GOOGLE_RULL
diff --git a/src/mainboard/google/brya/Kconfig.name b/src/mainboard/google/brya/Kconfig.name
index ac4c262d78..5431cba4c3 100644
--- a/src/mainboard/google/brya/Kconfig.name
+++ b/src/mainboard/google/brya/Kconfig.name
@@ -226,3 +226,6 @@ config BOARD_GOOGLE_TELITH
 
 config BOARD_GOOGLE_MELIKS
 	bool "->  Meliks"
+
+config BOARD_GOOGLE_EPIC
+	bool "->  Epic"
diff --git a/src/mainboard/google/brya/variants/epic/Makefile.mk b/src/mainboard/google/brya/variants/epic/Makefile.mk
new file mode 100644
index 0000000000..44792c487d
--- /dev/null
+++ b/src/mainboard/google/brya/variants/epic/Makefile.mk
@@ -0,0 +1,11 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+bootblock-y += gpio.c
+
+romstage-y += gpio.c
+
+ramstage-$(CONFIG_FW_CONFIG) += fw_config.c
+
+ramstage-y += variant.c
+
+ramstage-y += gpio.c
diff --git a/src/mainboard/google/brya/variants/epic/fw_config.c b/src/mainboard/google/brya/variants/epic/fw_config.c
new file mode 100644
index 0000000000..4eed44cb25
--- /dev/null
+++ b/src/mainboard/google/brya/variants/epic/fw_config.c
@@ -0,0 +1,43 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <baseboard/gpio.h>
+#include <baseboard/variants.h>
+#include <boardid.h>
+#include <console/console.h>
+#include <fw_config.h>
+
+static const struct pad_config lte_disable_pads_gothrax[] = {
+	/* A8  : WWAN_RF_DISABLE_ODL */
+	PAD_NC(GPP_A8, NONE),
+	/* E13  : WWAN_EN */
+	PAD_NC_LOCK(GPP_E13, NONE, LOCK_CONFIG),
+	/* F12 : WWAN_RST_L */
+	PAD_NC_LOCK(GPP_F12, NONE, LOCK_CONFIG),
+	/* H19 : SOC_I2C_SUB_INT_ODL */
+	PAD_NC(GPP_H19, NONE),
+	/* H23 : WWAN_SAR_DETECT_ODL */
+	PAD_NC(GPP_H23, NONE),
+};
+
+static const struct pad_config wfc_disable_pads[] = {
+	/* R6 : DMIC_WCAM_CLK_R */
+	PAD_NC(GPP_R6, NONE),
+	/* R7 : DMIC_WCAM_DATA */
+	PAD_NC(GPP_R7, NONE),
+};
+
+void fw_config_gpio_padbased_override(struct pad_config *padbased_table)
+{
+	if (!(fw_config_probe(FW_CONFIG(DB_USB, DB_C_A_LTE)) ||
+		fw_config_probe(FW_CONFIG(DB_USB, DB_A_HDMI_LTE)))) {
+		printk(BIOS_INFO, "Disable LTE-related GPIO pins on gothrax.\n");
+		gpio_padbased_override(padbased_table, lte_disable_pads_gothrax,
+						ARRAY_SIZE(lte_disable_pads_gothrax));
+	}
+
+	if (!fw_config_probe(FW_CONFIG(WFC, WFC_PRESENT))) {
+		printk(BIOS_INFO, "Disable WFC GPIO pins.\n");
+		gpio_padbased_override(padbased_table, wfc_disable_pads,
+						ARRAY_SIZE(wfc_disable_pads));
+	}
+}
diff --git a/src/mainboard/google/brya/variants/epic/gpio.c b/src/mainboard/google/brya/variants/epic/gpio.c
new file mode 100644
index 0000000000..ae236fbe1c
--- /dev/null
+++ b/src/mainboard/google/brya/variants/epic/gpio.c
@@ -0,0 +1,100 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <baseboard/variants.h>
+#include <soc/gpio.h>
+#include <fw_config.h>
+
+/* Pad configuration in ramstage */
+static const struct pad_config override_gpio_table[] = {
+	/* A8  : WWAN_RF_DISABLE_ODL */
+	PAD_CFG_GPO(GPP_A8, 1, DEEP),
+	/* H23 : WWAN_SAR_DETECT_ODL */
+	PAD_CFG_GPO(GPP_H23, 1, DEEP),
+	/* H3  : WLAN_PCIE_WAKE_ODL */
+	PAD_NC_LOCK(GPP_H3, NONE, LOCK_CONFIG),
+	/* E13  : SRCCLKREQ1# ==> WWAN_EN */
+	PAD_CFG_GPO_LOCK(GPP_E13, 1, LOCK_CONFIG),
+	/* F12 : WWAN_RST_L */
+	PAD_CFG_GPO_LOCK(GPP_F12, 1, LOCK_CONFIG),
+
+	/* A21 : GPP_A21 ==> USB_C1_AUX_DC_P */
+	PAD_CFG_GPO(GPP_A21, 0, DEEP),
+	/* A22 : GPP_A22 ==> USB_C1_AUX_DC_N */
+	PAD_CFG_GPO(GPP_A22, 1, DEEP),
+
+	/* C1  : SMBDATA ==> TCHSCR_RST_L */
+	PAD_CFG_GPO(GPP_C1, 1, DEEP),
+
+	/* D3  : WCAM_RST_L */
+	PAD_NC_LOCK(GPP_D3, NONE, LOCK_CONFIG),
+	/* D15 : EN_PP2800_WCAM_X */
+	PAD_NC_LOCK(GPP_D15, NONE, LOCK_CONFIG),
+	/* D16 : EN_PP1800_PP1200_WCAM_X */
+	PAD_NC_LOCK(GPP_D16, NONE, LOCK_CONFIG),
+
+	/* H19 : SOC_I2C_SUB_INT_ODL */
+	PAD_CFG_GPI_APIC(GPP_H19, NONE, PLTRST, LEVEL, NONE),
+	/* H22 : WCAM_MCLK_R */
+	PAD_NC(GPP_H22, NONE),
+};
+
+/* Early pad configuration in bootblock */
+static const struct pad_config early_gpio_table[] = {
+	/* F12 : GSXDOUT ==> WWAN_RST_L */
+	PAD_CFG_GPO(GPP_F12, 0, DEEP),
+	/* E13  : SRCCLKREQ1# ==> WWAN_EN */
+	PAD_CFG_GPO(GPP_E13, 1, DEEP),
+
+	/* H12 : UART0_RTS# ==> SD_PERST_L */
+	PAD_CFG_GPO(GPP_H12, 0, DEEP),
+
+	/* H20 : IMGCLKOUT1 ==> WLAN_PERST_L */
+	PAD_CFG_GPO(GPP_H20, 0, DEEP),
+	/* A13 : GPP_A13 ==> GSC_SOC_INT_ODL */
+	PAD_CFG_GPI_APIC(GPP_A13, NONE, PLTRST, LEVEL, INVERT),
+	/* E12 : THC0_SPI1_IO1 ==> SOC_WP_OD */
+	PAD_CFG_GPI_GPIO_DRIVER(GPP_E12, NONE, DEEP),
+	/* F18 : THC1_SPI2_INT# ==> EC_IN_RW_OD */
+	PAD_CFG_GPI(GPP_F18, NONE, DEEP),
+	/* H4  : I2C0_SDA ==> SOC_I2C_GSC_SDA */
+	PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1),
+	/* H5  : I2C0_SCL ==> SOC_I2C_GSC_SCL */
+	PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1),
+	/* H10 : UART0_RXD ==> UART_SOC_RX_DBG_TX */
+	PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2),
+	/* H11 : UART0_TXD ==> UART_SOC_TX_DBG_RX */
+	PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2),
+
+	/* H13 : UART0_CTS# ==> EN_PP3300_SD_X */
+	PAD_CFG_GPO(GPP_H13, 1, DEEP),
+};
+
+static const struct pad_config romstage_gpio_table[] = {
+	/* Enable touchscreen, hold in reset */
+	/* C0  : SMBCLK ==> EN_PP3300_TCHSCR_X */
+	PAD_CFG_GPO(GPP_C0, 1, DEEP),
+	/* C1  : SMBDATA ==> TCHSCR_RST_L */
+	PAD_CFG_GPO(GPP_C1, 0, DEEP),
+	/* H12 : UART0_RTS# ==> SD_PERST_L */
+	PAD_CFG_GPO(GPP_H12, 1, DEEP),
+	/* H20 : IMGCLKOUT1 ==> WLAN_PERST_L */
+	PAD_CFG_GPO(GPP_H20, 1, DEEP),
+};
+
+const struct pad_config *variant_gpio_override_table(size_t *num)
+{
+	*num = ARRAY_SIZE(override_gpio_table);
+	return override_gpio_table;
+}
+
+const struct pad_config *variant_early_gpio_table(size_t *num)
+{
+	*num = ARRAY_SIZE(early_gpio_table);
+	return early_gpio_table;
+}
+
+const struct pad_config *variant_romstage_gpio_table(size_t *num)
+{
+	*num = ARRAY_SIZE(romstage_gpio_table);
+	return romstage_gpio_table;
+}
diff --git a/src/mainboard/google/brya/variants/epic/include/variant/ec.h b/src/mainboard/google/brya/variants/epic/include/variant/ec.h
new file mode 100644
index 0000000000..7a2a6ff8b7
--- /dev/null
+++ b/src/mainboard/google/brya/variants/epic/include/variant/ec.h
@@ -0,0 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#ifndef __VARIANT_EC_H__
+#define __VARIANT_EC_H__
+
+#include <baseboard/ec.h>
+
+#endif
diff --git a/src/mainboard/google/brya/variants/epic/include/variant/gpio.h b/src/mainboard/google/brya/variants/epic/include/variant/gpio.h
new file mode 100644
index 0000000000..9b6b711f3c
--- /dev/null
+++ b/src/mainboard/google/brya/variants/epic/include/variant/gpio.h
@@ -0,0 +1,12 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#ifndef VARIANT_GPIO_H
+#define VARIANT_GPIO_H
+
+#include <baseboard/gpio.h>
+
+#define WWAN_FCPO	GPP_E13
+#define WWAN_RST	GPP_F12
+#define T2_OFF_MS	20
+
+#endif
diff --git a/src/mainboard/google/brya/variants/epic/memory/Makefile.mk b/src/mainboard/google/brya/variants/epic/memory/Makefile.mk
new file mode 100644
index 0000000000..99db10e40b
--- /dev/null
+++ b/src/mainboard/google/brya/variants/epic/memory/Makefile.mk
@@ -0,0 +1,10 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+# This is an auto-generated file. Do not edit!!
+# Generated by:
+# ./util/spd_tools/bin/part_id_gen ADL lp5 src/mainboard/google/brya/variants/epic/memory src/mainboard/google/brya/variants/epic/memory/mem_parts_used.txt
+
+SPD_SOURCES =
+SPD_SOURCES += spd/lp5/set-0/spd-1.hex      # ID = 0(0b0000)  Parts = MT62F512M32D2DR-031 WT:B, H9JCNNNBK3MLYR-N6E
+SPD_SOURCES += spd/lp5/set-0/spd-3.hex      # ID = 1(0b0001)  Parts = H58G56AK6BX069
+SPD_SOURCES += spd/lp5/set-0/spd-3.hex      # ID = 2(0b0010)  Parts = K3LKBKB0BM-MGCP
+SPD_SOURCES += spd/lp5/set-0/spd-2.hex      # ID = 3(0b0011)  Parts = H9JCNNNCP3MLYR-N6E
diff --git a/src/mainboard/google/brya/variants/epic/memory/dram_id.generated.txt b/src/mainboard/google/brya/variants/epic/memory/dram_id.generated.txt
new file mode 100644
index 0000000000..17a6ba6db5
--- /dev/null
+++ b/src/mainboard/google/brya/variants/epic/memory/dram_id.generated.txt
@@ -0,0 +1,11 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+# This is an auto-generated file. Do not edit!!
+# Generated by:
+# ./util/spd_tools/bin/part_id_gen ADL lp5 src/mainboard/google/brya/variants/epic/memory src/mainboard/google/brya/variants/epic/memory/mem_parts_used.txt
+
+DRAM Part Name                 ID to assign
+MT62F512M32D2DR-031 WT:B       0 (0000)
+H58G56AK6BX069                 1 (0001)
+K3LKBKB0BM-MGCP                2 (0010)
+H9JCNNNBK3MLYR-N6E             0 (0000)
+H9JCNNNCP3MLYR-N6E             3 (0011)
diff --git a/src/mainboard/google/brya/variants/epic/memory/mem_parts_used.txt b/src/mainboard/google/brya/variants/epic/memory/mem_parts_used.txt
new file mode 100644
index 0000000000..5d050345ae
--- /dev/null
+++ b/src/mainboard/google/brya/variants/epic/memory/mem_parts_used.txt
@@ -0,0 +1,17 @@
+# This is a CSV file containing a list of memory parts used by this variant.
+# One part per line with an optional fixed ID in column 2.
+# Only include a fixed ID if it is required for legacy reasons!
+# Generated IDs are dependent on the order of parts in this file,
+# so new parts must always be added at the end of the file!
+#
+# Generate an updated Makefile.mk and dram_id.generated.txt by running the
+# part_id_gen tool from util/spd_tools.
+# See util/spd_tools/README.md for more details and instructions.
+
+# Part Name
+
+MT62F512M32D2DR-031 WT:B,
+H58G56AK6BX069,*1
+K3LKBKB0BM-MGCP,
+H9JCNNNBK3MLYR-N6E,
+H9JCNNNCP3MLYR-N6E,
diff --git a/src/mainboard/google/brya/variants/epic/overridetree.cb b/src/mainboard/google/brya/variants/epic/overridetree.cb
new file mode 100644
index 0000000000..dcd8593098
--- /dev/null
+++ b/src/mainboard/google/brya/variants/epic/overridetree.cb
@@ -0,0 +1,556 @@
+fw_config
+	field DB_USB 0 2
+		option DB_NONE		0
+		option DB_C_A		1
+		option DB_C_A_LTE	2
+		option DB_A		3
+		option DB_A_HDMI_LTE		6
+	end
+	field WLAN 3 4
+		option WLAN_MT7921_AZUREWAVE	0
+		option WLAN_AX211_Intel		1
+	end
+	field AUDIO 5 6
+		option AUDIO_ALC1019_ALC5682IVS	0
+	end
+	field STYLUS 7
+		option STYLUS_ABSENT	0
+		option STYLUS_PRESENT	1
+	end
+	field WFC 8
+		option WFC_PRESENT	0
+		option WFC_ABSENT	1
+	end
+	field TOUCH_PANEL 9 10
+		option TOUCH_PANEL_I2C_HID	0
+		option TOUCH_PANEL_DISABLE	1
+		option TOUCH_PANEL_I2C_GENERIC	2
+	end
+	field ADP_VOL_LIM 11
+		option ADP_VOL_LIM_MAX15	0
+		option ADP_VOL_LIM_MAX20	1
+	end
+	field THERMAL_SOLUTION 22
+		option THERMAL_SOLUTION_PASSIVE	0
+		option THERMAL_SOLUTION_ACTIVE	1
+	end
+end
+
+chip soc/intel/alderlake
+	register "sagv" = "SaGv_Enabled"
+
+	# EMMC Tx CMD Delay
+	# Refer to EDS-Vol2-42.3.7.
+	# [14:8] steps of delay for DDR mode, each 125ps, range: 0 - 39.
+	# [6:0] steps of delay for SDR mode, each 125ps, range: 0 - 39.
+	register "common_soc_config.emmc_dll.emmc_tx_cmd_cntl" = "0x505"
+
+	# EMMC TX DATA Delay 1
+	# Refer to EDS-Vol2-42.3.8.
+	# [14:8] steps of delay for HS400, each 125ps, range: 0 - 78.
+	# [6:0] steps of delay for SDR104/HS200, each 125ps, range: 0 - 79.
+	register "common_soc_config.emmc_dll.emmc_tx_data_cntl1" = "0x909"
+
+	# EMMC TX DATA Delay 2
+	# Refer to EDS-Vol2-42.3.9.
+	# [30:24] steps of delay for SDR50, each 125ps, range: 0 - 79.
+	# [22:16] steps of delay for DDR50, each 125ps, range: 0 - 78.
+	# [14:8] steps of delay for SDR25/HS50, each 125ps, range: 0 -79.
+	# [6:0] steps of delay for SDR12, each 125ps. Range: 0 - 79.
+	register "common_soc_config.emmc_dll.emmc_tx_data_cntl2" = "0x1C2A2828"
+
+	# EMMC RX CMD/DATA Delay 1
+	# Refer to EDS-Vol2-42.3.10.
+	# [30:24] steps of delay for SDR50, each 125ps, range: 0 - 119.
+	# [22:16] steps of delay for DDR50, each 125ps, range: 0 - 78.
+	# [14:8] steps of delay for SDR25/HS50, each 125ps, range: 0 - 119.
+	# [6:0] steps of delay for SDR12, each 125ps, range: 0 - 119.
+	register "common_soc_config.emmc_dll.emmc_rx_cmd_data_cntl1" = "0x1C1B4F1B"
+
+	# EMMC RX CMD/DATA Delay 2
+	# Refer to EDS-Vol2-42.3.12.
+	# [17:16] stands for Rx Clock before Output Buffer,
+	#         00: Rx clock after output buffer,
+	#         01: Rx clock before output buffer,
+	#         10: Automatic selection based on working mode.
+	#         11: Reserved
+	# [14:8] steps of delay for Auto Tuning Mode, each 125ps, range: 0 - 39.
+	# [6:0] steps of delay for HS200, each 125ps, range: 0 - 79.
+	register "common_soc_config.emmc_dll.emmc_rx_cmd_data_cntl2" = "0x10005"
+
+	# EMMC Rx Strobe Delay
+	# Refer to EDS-Vol2-42.3.11.
+	# [14:8] Rx Strobe Delay DLL 1(HS400 Mode), each 125ps, range: 0 - 39.
+	# [6:0] Rx Strobe Delay DLL 2(HS400 Mode), each 125ps, range: 0 - 39.
+	register "common_soc_config.emmc_dll.emmc_rx_strobe_cntl" = "0x11515"
+
+	# Bit 0 - C0 has no redriver, so enable SBU muxing in the SoC.
+	# Bit 2 - C1 has a redriver which does SBU muxing.
+	# Bit 1,3 - AUX lines are not swapped on the motherboard for either C0 or C1.
+	register "tcss_aux_ori" = "5"
+
+	register "typec_aux_bias_pads[0]" = "{.pad_auxp_dc = GPP_E22, .pad_auxn_dc = GPP_E23}"
+	register "typec_aux_bias_pads[1]" = "{.pad_auxp_dc = GPP_A21, .pad_auxn_dc = GPP_A22}"
+
+	# Configure external V1P05/Vnn/VnnSx Rails
+	register "ext_fivr_settings" = "{
+		.configure_ext_fivr = 1,
+		.v1p05_enable_bitmap = FIVR_ENABLE_ALL_SX & ~FIVR_ENABLE_S0,
+		.vnn_enable_bitmap = FIVR_ENABLE_ALL_SX,
+		.vnn_sx_enable_bitmap = FIVR_ENABLE_ALL_SX,
+		.v1p05_supported_voltage_bitmap = FIVR_VOLTAGE_NORMAL,
+		.vnn_supported_voltage_bitmap = FIVR_VOLTAGE_MIN_ACTIVE,
+		.v1p05_voltage_mv = 1050,
+		.vnn_voltage_mv = 780,
+		.vnn_sx_voltage_mv = 1050,
+		.v1p05_icc_max_ma = 500,
+		.vnn_icc_max_ma = 500,
+	}"
+
+	# Intel Common SoC Config
+	#+-------------------+---------------------------+
+	#| Field             |  Value                    |
+	#+-------------------+---------------------------+
+	#| I2C0              | TPM. Early init is        |
+	#|                   | required to set up a BAR  |
+	#|                   | for TPM communication     |
+	#| I2C1              | Touchscreen               |
+	#| I2C2              | Sub-board(PSensor)/WCAM   |
+	#| I2C3              | Audio                     |
+	#| I2C5              | Trackpad                  |
+	#+-------------------+---------------------------+
+	register "common_soc_config" = "{
+		.i2c[0] = {
+			.early_init = 1,
+			.speed = I2C_SPEED_FAST_PLUS,
+			.speed_config[0] = {
+				.speed = I2C_SPEED_FAST_PLUS,
+				.scl_lcnt = 55,
+				.scl_hcnt = 30,
+				.sda_hold = 7,
+			}
+		},
+		.i2c[1] = {
+			.speed = I2C_SPEED_FAST,
+			.speed_config[0] = {
+				.speed = I2C_SPEED_FAST,
+				.scl_lcnt = 160,
+				.scl_hcnt = 79,
+				.sda_hold = 7,
+			}
+		},
+		.i2c[2] = {
+			.speed = I2C_SPEED_FAST,
+			.speed_config[0] = {
+				.speed = I2C_SPEED_FAST,
+				.scl_lcnt = 157,
+				.scl_hcnt = 79,
+				.sda_hold = 7,
+			}
+		},
+		.i2c[3] = {
+			.speed = I2C_SPEED_FAST,
+			.speed_config[0] = {
+				.speed = I2C_SPEED_FAST,
+				.scl_lcnt = 157,
+				.scl_hcnt = 79,
+				.sda_hold = 7,
+			}
+		},
+		.i2c[5] = {
+			.speed = I2C_SPEED_FAST,
+			.speed_config[0] = {
+				.speed = I2C_SPEED_FAST,
+				.scl_lcnt = 152,
+				.scl_hcnt = 79,
+				.sda_hold = 7,
+			}
+		},
+	}"
+
+	device domain 0 on
+		device ref dtt on
+			chip drivers/intel/dptf
+				## sensor information
+				register "options.tsr[0].desc" = ""Memory""
+				register "options.tsr[1].desc" = ""Charger""
+				register "options.tsr[2].desc" = ""Ambient""
+
+				# TODO: below values are initial reference values only
+				## Passive Policy
+				register "policies.passive" = "{
+					[0] = DPTF_PASSIVE(CPU,         CPU,           95, 5000),
+					[1] = DPTF_PASSIVE(CPU,         TEMP_SENSOR_0, 75, 5000),
+					[2] = DPTF_PASSIVE(CHARGER,     TEMP_SENSOR_1, 75, 5000),
+					[3] = DPTF_PASSIVE(CPU,         TEMP_SENSOR_2, 75, 5000),
+				}"
+
+				## Critical Policy
+				register "policies.critical" = "{
+					[0] = DPTF_CRITICAL(CPU,               105, SHUTDOWN),
+					[1] = DPTF_CRITICAL(TEMP_SENSOR_0,      85, SHUTDOWN),
+					[2] = DPTF_CRITICAL(TEMP_SENSOR_1,      85, SHUTDOWN),
+					[3] = DPTF_CRITICAL(TEMP_SENSOR_2,      85, SHUTDOWN),
+				}"
+
+				register "controls.power_limits" = "{
+					.pl1 = {
+							.min_power = 3000,
+							.max_power = 6000,
+							.time_window_min = 28 * MSECS_PER_SEC,
+							.time_window_max = 32 * MSECS_PER_SEC,
+							.granularity = 200
+						},
+					.pl2 = {
+							.min_power = 25000,
+							.max_power = 25000,
+							.time_window_min = 28 * MSECS_PER_SEC,
+							.time_window_max = 32 * MSECS_PER_SEC,
+							.granularity = 1000
+						}
+				}"
+
+				## Charger Performance Control (Control, mA)
+				register "controls.charger_perf" = "{
+					[0] = { 255, 1700 },
+					[1] = {  24, 1500 },
+					[2] = {  16, 1000 },
+					[3] = {   8,  500 }
+				}"
+
+				device generic 0 on end
+			end
+		end
+		device ref i2c1 on
+			chip drivers/i2c/hid
+				register "generic.hid" = ""ELAN7B13""
+				register "generic.desc" = ""ELAN Touchscreen""
+				register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_C7_IRQ)"
+				register "generic.detect" = "1"
+				register "generic.reset_gpio" =
+					"ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C1)"
+				register "generic.reset_delay_ms" = "300"
+				register "generic.reset_off_delay_ms" = "2"
+				register "generic.enable_gpio" =
+					"ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C0)"
+				register "generic.enable_delay_ms" = "6"
+				register "generic.has_power_resource" = "1"
+				register "generic.use_gpio_for_status" = "true"
+				register "hid_desc_reg_offset" = "0x01"
+				device i2c 0x10 on
+					probe TOUCH_PANEL TOUCH_PANEL_I2C_HID
+				end
+			end
+			chip drivers/i2c/hid
+				register "generic.hid" = ""ILI2901""
+				register "generic.desc" = ""ILI Touchscreen""
+				register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_C7_IRQ)"
+				register "generic.detect" = "1"
+				register "generic.reset_gpio" =
+					"ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C1)"
+				register "generic.reset_delay_ms" = "200"
+				register "generic.reset_off_delay_ms" = "2"
+				register "generic.enable_gpio" =
+					"ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C0)"
+				register "generic.enable_delay_ms" = "6"
+				register "generic.has_power_resource" = "1"
+				register "generic.use_gpio_for_status" = "true"
+				register "hid_desc_reg_offset" = "0x01"
+				device i2c 0x41 on
+					probe TOUCH_PANEL TOUCH_PANEL_I2C_HID
+				end
+			end
+			chip drivers/i2c/generic
+				register "hid" = ""ELAN0001""
+				register "desc" = ""ELAN Touchscreen""
+				register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_C7_IRQ)"
+				register "detect" = "1"
+				register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C1)"
+				register "reset_delay_ms" = "150"
+				register "reset_off_delay_ms" = "1"
+				register "enable_gpio" =
+							"ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C0)"
+				register "enable_delay_ms" = "6"
+				register "has_power_resource" = "1"
+				register "use_gpio_for_status" = "true"
+				device i2c 10 on
+					probe TOUCH_PANEL TOUCH_PANEL_I2C_GENERIC
+				end
+			end
+		end
+		device ref i2c2 on
+			chip drivers/i2c/sx9324
+				register "desc" = ""SAR2 Proximity Sensor""
+				register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_H19_IRQ)"
+				register "speed" = "I2C_SPEED_FAST"
+				register "uid" = "1"
+				register "reg_gnrl_ctrl0" = "0x16"
+				register "reg_gnrl_ctrl1" = "0x21"
+				register "reg_afe_ctrl0" = "0x20"
+				register "reg_afe_ctrl1" = "0x10"
+				register "reg_afe_ctrl2" = "0x00"
+				register "reg_afe_ctrl3" = "0x01"
+				register "reg_afe_ctrl4" = "0x46"
+				register "reg_afe_ctrl5" = "0x00"
+				register "reg_afe_ctrl6" = "0x00"
+				register "reg_afe_ctrl7" = "0x07"
+				register "reg_afe_ctrl8" = "0x12"
+				register "reg_afe_ctrl9" = "0x0f"
+				register "reg_prox_ctrl0" = "0x09"
+				register "reg_prox_ctrl1" = "0x12"
+				register "reg_prox_ctrl2" = "0x90"
+				register "reg_prox_ctrl3" = "0x60"
+				register "reg_prox_ctrl4" = "0x0c"
+				register "reg_prox_ctrl5" = "0x12"
+				register "reg_prox_ctrl6" = "0x1e"
+				register "reg_prox_ctrl7" = "0x58"
+				register "reg_adv_ctrl0" = "0x00"
+				register "reg_adv_ctrl1" = "0x00"
+				register "reg_adv_ctrl2" = "0x00"
+				register "reg_adv_ctrl3" = "0x00"
+				register "reg_adv_ctrl4" = "0x00"
+				register "reg_adv_ctrl5" = "0x05"
+				register "reg_adv_ctrl6" = "0x00"
+				register "reg_adv_ctrl7" = "0x00"
+				register "reg_adv_ctrl8" = "0x00"
+				register "reg_adv_ctrl9" = "0x00"
+				register "reg_adv_ctrl10" = "0x5c"
+				register "reg_adv_ctrl11" = "0x52"
+				register "reg_adv_ctrl12" = "0xb5"
+				register "reg_adv_ctrl13" = "0x00"
+				register "reg_adv_ctrl14" = "0x80"
+				register "reg_adv_ctrl15" = "0x0c"
+				register "reg_adv_ctrl16" = "0x38"
+				register "reg_adv_ctrl17" = "0x56"
+				register "reg_adv_ctrl18" = "0x33"
+				register "reg_adv_ctrl19" = "0xf0"
+				register "reg_adv_ctrl20" = "0xf0"
+
+				register "ph0_pin" = "{1, 3, 3}"
+				register "ph1_pin" = "{3, 2, 1}"
+				register "ph2_pin" = "{3, 3, 1}"
+				register "ph3_pin" = "{1, 3, 3}"
+				register "ph01_resolution" = "512"
+				register "ph23_resolution" = "1024"
+				register "startup_sensor" = "1"
+				register "ph01_proxraw_strength" = "1"
+				register "ph23_proxraw_strength" = "1"
+				register "avg_pos_strength" = "256"
+				register "cs_idle_sleep" = ""gnd""
+				register "int_comp_resistor" = ""lowest""
+				register "input_precharge_resistor_ohms" = "4000"
+				register "input_analog_gain" = "3"
+				device i2c 28 on
+					probe DB_USB DB_C_A_LTE
+					probe DB_USB DB_A_HDMI_LTE
+				end
+			end
+		end
+		device ref i2c3 on
+			chip drivers/i2c/generic
+				register "hid" = ""RTL5682""
+				register "name" = ""RT58""
+				register "desc" = ""Headset Codec""
+				register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_A23)"
+				# Set the jd_src to RT5668_JD1 for jack detection
+				register "property_count" = "1"
+				register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER"
+				register "property_list[0].name" = ""realtek,jd-src""
+				register "property_list[0].integer" = "1"
+				device i2c 1a on end
+			end
+			chip drivers/generic/alc1015
+				register "hid" = ""RTL1019""
+				register "sdb" =  "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A11)"
+				device generic 0 on end
+			end
+		end
+
+		device ref i2c5 on
+			chip drivers/i2c/hid
+				register "generic.hid" = ""PNP0C50""
+				register "generic.desc" = ""PIXART Touchpad""
+				register "generic.irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_F14_IRQ)"
+				register "generic.wake" = "GPE0_DW2_14"
+				register "generic.detect" = "1"
+				register "hid_desc_reg_offset" = "0x01"
+				device i2c 15 on end
+			end
+		end
+		device ref pcie_rp4 on
+			# PCIe 4 WLAN
+			register "pch_pcie_rp[PCH_RP(4)]" = "{
+				.clk_src = 2,
+				.clk_req = 2,
+				.flags = PCIE_RP_LTR | PCIE_RP_AER,
+			}"
+			chip drivers/wifi/generic
+				register "wake" = "GPE0_DW1_03"
+				register "add_acpi_dma_property" = "true"
+				device pci 00.0 on end
+			end
+		end
+		device ref pcie_rp7 on
+			# Enable SD Card PCIe 7 using clk 3
+			register "pch_pcie_rp[PCH_RP(7)]" = "{
+				.clk_src = 3,
+				.clk_req = 3,
+				.flags = PCIE_RP_HOTPLUG | PCIE_RP_LTR | PCIE_RP_AER,
+			}"
+			chip soc/intel/common/block/pcie/rtd3
+				register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_H13)"
+				register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_H12)"
+				register "srcclk_pin" = "3"
+				device generic 0 on end
+			end
+		end
+		device ref pch_espi on
+			chip ec/google/chromeec
+				use conn0 as mux_conn[0]
+				use conn1 as mux_conn[1]
+				device pnp 0c09.0 on end
+			end
+		end
+		device ref pmc hidden
+			chip drivers/intel/pmc_mux
+				device generic 0 on
+					chip drivers/intel/pmc_mux/conn
+						use usb2_port1 as usb2_port
+						use tcss_usb3_port1 as usb3_port
+						device generic 0 alias conn0 on end
+					end
+					chip drivers/intel/pmc_mux/conn
+						use usb2_port2 as usb2_port
+						use tcss_usb3_port2 as usb3_port
+						device generic 1 alias conn1 on
+							probe DB_USB DB_C_A
+							probe DB_USB DB_C_A_LTE
+						end
+					end
+				end
+			end
+		end
+		device ref tcss_xhci on
+			chip drivers/usb/acpi
+				device ref tcss_root_hub on
+					chip drivers/usb/acpi
+						register "desc" = ""USB3 Type-C Port C0 (MLB)""
+						register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
+						register "use_custom_pld" = "true"
+						register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(1, 1))"
+						device ref tcss_usb3_port1 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB3 Type-C Port C1 (DB)""
+						register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
+						register "use_custom_pld" = "true"
+						register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, RIGHT, ACPI_PLD_GROUP(2, 1))"
+						device ref tcss_usb3_port2 on
+							probe DB_USB DB_C_A
+							probe DB_USB DB_C_A_LTE
+						end
+					end
+				end
+			end
+		end
+		device ref xhci on
+			register "usb2_ports[4]" = "USB2_PORT_MID(OC_SKIP)"     # USB2_A1
+			register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)"     # WFC
+			register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)"     # Bluetooth port for PCIe WLAN
+			register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)"     # Bluetooth port for CNVi WLAN
+			register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB3/3 Type A port A1
+
+			chip drivers/usb/acpi
+				device ref xhci_root_hub on
+					chip drivers/usb/acpi
+						register "desc" = ""USB2 Type-C Port C0 (MLB)""
+						register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
+						register "use_custom_pld" = "true"
+						register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(1, 1))"
+						device ref usb2_port1 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB2 Type-C Port C1 (DB)""
+						register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
+						register "use_custom_pld" = "true"
+						register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, RIGHT, ACPI_PLD_GROUP(2, 1))"
+						device ref usb2_port2 on
+							probe DB_USB DB_C_A
+							probe DB_USB DB_C_A_LTE
+						end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB2 Type-A Port A0 (MLB)""
+						register "type" = "UPC_TYPE_A"
+						register "use_custom_pld" = "true"
+						register "custom_pld" = "ACPI_PLD_TYPE_A(LEFT, RIGHT, ACPI_PLD_GROUP(3, 1))"
+						device ref usb2_port3 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB2 Type-A Port A1 (DB)""
+						register "type" = "UPC_TYPE_A"
+						register "use_custom_pld" = "true"
+						register "custom_pld" = "ACPI_PLD_TYPE_A(RIGHT, LEFT, ACPI_PLD_GROUP(4, 1))"
+						device ref usb2_port4 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB2 WWAN""
+						register "type" = "UPC_TYPE_INTERNAL"
+						device ref usb2_port5 on
+							probe DB_USB DB_C_A_LTE
+							probe DB_USB DB_A_HDMI_LTE
+						end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB2 UFC""
+						register "type" = "UPC_TYPE_INTERNAL"
+						device ref usb2_port6 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB2 WFC""
+						register "type" = "UPC_TYPE_INTERNAL"
+						device ref usb2_port7 on
+							probe WFC WFC_PRESENT
+						end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB2 Bluetooth""
+						register "type" = "UPC_TYPE_INTERNAL"
+						register "reset_gpio" =
+							"ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D4)"
+						device ref usb2_port8 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""CNVi Bluetooth""
+						register "type" = "UPC_TYPE_INTERNAL"
+						register "reset_gpio" =
+							"ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D4)"
+						device ref usb2_port10 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB3 Type-A Port A0 (MLB)""
+						register "type" = "UPC_TYPE_USB3_A"
+						register "use_custom_pld" = "true"
+						register "custom_pld" = "ACPI_PLD_TYPE_A(LEFT, RIGHT, ACPI_PLD_GROUP(3, 1))"
+						device ref usb3_port1 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB3 Type-A Port A1 (DB)""
+						register "type" = "UPC_TYPE_USB3_A"
+						register "use_custom_pld" = "true"
+						register "custom_pld" = "ACPI_PLD_TYPE_A(RIGHT, LEFT, ACPI_PLD_GROUP(4, 1))"
+						device ref usb3_port2 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB3 WWAN""
+						register "type" = "UPC_TYPE_INTERNAL"
+						device ref usb3_port3 on
+							probe DB_USB DB_C_A_LTE
+							probe DB_USB DB_A_HDMI_LTE
+						end
+					end
+				end
+			end
+		end
+	end
+end
diff --git a/src/mainboard/google/brya/variants/epic/variant.c b/src/mainboard/google/brya/variants/epic/variant.c
new file mode 100644
index 0000000000..033abc7788
--- /dev/null
+++ b/src/mainboard/google/brya/variants/epic/variant.c
@@ -0,0 +1,29 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <baseboard/gpio.h>
+#include <baseboard/variants.h>
+#include <console/console.h>
+#include <fw_config.h>
+
+void variant_update_soc_chip_config(struct soc_intel_alderlake_config *config)
+{
+	if (!(fw_config_probe(FW_CONFIG(DB_USB, DB_C_A_LTE)) ||
+		fw_config_probe(FW_CONFIG(DB_USB, DB_A_HDMI_LTE)))) {
+		printk(BIOS_INFO, "Disable usb2_port5 and usb3_port3 of WWAN.\n");
+
+		config->usb2_ports[4] = (struct usb2_port_config) USB2_PORT_EMPTY;
+		config->usb3_ports[2] = (struct usb3_port_config) USB3_PORT_EMPTY;
+	}
+
+	if (!fw_config_probe(FW_CONFIG(WFC, WFC_PRESENT))) {
+		printk(BIOS_INFO, "Disable usb2_port7 of WFC.\n");
+
+		config->usb2_ports[6] = (struct usb2_port_config) USB2_PORT_EMPTY;
+	}
+
+	if (fw_config_probe(FW_CONFIG(DB_USB, DB_A)) || fw_config_probe(FW_CONFIG(DB_USB, DB_A_HDMI_LTE))) {
+		printk(BIOS_INFO, "Disable typec aux_bias_pads in the SOC.\n");
+		config->typec_aux_bias_pads[1].pad_auxp_dc = 0x00;
+		config->typec_aux_bias_pads[1].pad_auxn_dc = 0x00;
+	}
+}

From ee30558c49c9c4622277785ee0cd54c32720e489 Mon Sep 17 00:00:00 2001
From: Nico Huber <nico.h@gmx.de>
Date: Fri, 12 Jan 2024 16:22:19 +0100
Subject: [PATCH 0807/3886] soc/intel/skylake: Drop redundant PcieRpEnable

The PcieRpEnable option is redundant to our on/off setting in the
devicetrees. Let's use the common coreboot infrastructure instead.

Thanks to Nicholas for doing all the mainboard legwork!

Change-Id: I2f7e3e1dc6b3d8d6159bd4701e6fd90f4b0f67f4
Signed-off-by: Nico Huber <nico.h@gmx.de>
Signed-off-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79917
Reviewed-by: Erik van den Bogaert <ebogaert@eltan.com>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/51nb/x210/devicetree.cb         |  3 --
 .../acer/aspire_vn7_572g/devicetree.cb        |  4 ---
 src/mainboard/asrock/h110m/devicetree.cb      |  3 --
 .../clevo/kbl-u/variants/n13xwu/devicetree.cb |  4 ---
 .../dell/optiplex_3050/devicetree.cb          |  3 --
 src/mainboard/facebook/monolith/devicetree.cb |  3 --
 src/mainboard/google/eve/devicetree.cb        |  2 --
 .../fizz/variants/baseboard/devicetree.cb     |  6 ----
 .../fizz/variants/endeavour/overridetree.cb   | 15 ++--------
 src/mainboard/google/glados/devicetree.cb     |  1 -
 .../google/poppy/variants/atlas/devicetree.cb |  1 -
 .../poppy/variants/baseboard/devicetree.cb    |  1 -
 .../google/poppy/variants/nami/devicetree.cb  |  3 --
 .../poppy/variants/nautilus/devicetree.cb     |  1 -
 .../poppy/variants/nocturne/devicetree.cb     |  2 --
 .../poppy/variants/rammus/devicetree.cb       |  1 -
 .../poppy/variants/soraka/devicetree.cb       |  1 -
 src/mainboard/hp/280_g2/devicetree.cb         |  4 ---
 .../kblrvp/variants/rvp11/overridetree.cb     |  6 ----
 .../kblrvp/variants/rvp3/overridetree.cb      |  5 ----
 .../kblrvp/variants/rvp7/overridetree.cb      |  5 ----
 .../kblrvp/variants/rvp8/overridetree.cb      |  4 ---
 src/mainboard/intel/kunimitsu/devicetree.cb   |  2 --
 src/mainboard/intel/saddlebrook/devicetree.cb |  4 ---
 src/mainboard/kontron/bsl6/devicetree.cb      | 12 ++------
 .../bsl6/variants/bsl6/overridetree.cb        | 25 ++++------------
 src/mainboard/lenovo/m900/devicetree.cb       |  3 --
 src/mainboard/lenovo/m900_tiny/devicetree.cb  |  2 --
 .../lenovo/thinkcentre_m710s/devicetree.cb    |  6 ----
 src/mainboard/libretrend/lt1000/devicetree.cb | 10 +------
 .../protectli/vault_kbl/devicetree.cb         |  7 -----
 src/mainboard/purism/librem_skl/devicetree.cb |  8 ++---
 .../razer/blade_stealth_kbl/devicetree.cb     |  3 --
 .../starbook/variants/kbl/devicetree.cb       |  2 --
 .../variants/x11ssh-f/overridetree.cb         |  7 -----
 .../variants/x11ssh-tf/overridetree.cb        |  4 ---
 .../variants/x11ssm-f/overridetree.cb         |  5 ----
 .../variants/x11ssw-f/overridetree.cb         |  5 ----
 src/mainboard/system76/kbl-u/devicetree.cb    |  4 ---
 src/soc/intel/skylake/Makefile.mk             |  2 ++
 src/soc/intel/skylake/chip.c                  | 22 ++------------
 src/soc/intel/skylake/chip.h                  |  7 -----
 src/soc/intel/skylake/include/soc/pcie.h      | 10 +++++++
 src/soc/intel/skylake/pcie_rp.c               | 29 +++++++++++++++++++
 src/soc/intel/skylake/romstage/fsp_params.c   | 11 ++-----
 45 files changed, 60 insertions(+), 208 deletions(-)
 create mode 100644 src/soc/intel/skylake/include/soc/pcie.h
 create mode 100644 src/soc/intel/skylake/pcie_rp.c

diff --git a/src/mainboard/51nb/x210/devicetree.cb b/src/mainboard/51nb/x210/devicetree.cb
index a5bb944cb3..a2e08bf862 100644
--- a/src/mainboard/51nb/x210/devicetree.cb
+++ b/src/mainboard/51nb/x210/devicetree.cb
@@ -89,7 +89,6 @@ chip soc/intel/skylake
 		end
 		device ref pcie_rp3	on
 			# Ethernet controller
-			register "PcieRpEnable[2]" = "true"
 			register "PcieRpClkReqSupport[2]" = "1"
 			register "PcieRpClkReqNumber[2]" = "0"
 			register "PcieRpClkSrcNumber[2]" = "0"
@@ -98,7 +97,6 @@ chip soc/intel/skylake
 		end
 		device ref pcie_rp4	on
 			# Wireless controller
-			register "PcieRpEnable[3]" = "true"
 			register "PcieRpClkReqSupport[3]" = "1"
 			register "PcieRpClkReqNumber[3]" = "1"
 			register "PcieRpClkSrcNumber[3]" = "1"
@@ -107,7 +105,6 @@ chip soc/intel/skylake
 		end
 		device ref pcie_rp9	on
 			# NVMe controller
-			register "PcieRpEnable[8]" = "true"
 			register "PcieRpClkReqSupport[8]" = "1"
 			register "PcieRpClkReqNumber[8]" = "4"
 			register "PcieRpClkSrcNumber[8]" = "4"
diff --git a/src/mainboard/acer/aspire_vn7_572g/devicetree.cb b/src/mainboard/acer/aspire_vn7_572g/devicetree.cb
index 60136ed84a..f308894c5b 100644
--- a/src/mainboard/acer/aspire_vn7_572g/devicetree.cb
+++ b/src/mainboard/acer/aspire_vn7_572g/devicetree.cb
@@ -251,7 +251,6 @@ chip soc/intel/skylake
 		# Board has no GPIO expander on I2C4 (despite SetupUtility claim that it does - this would be static text)
 		device ref pcie_rp1	on
 			# dGPU; x4
-			register "PcieRpEnable[0]" = "true"
 			register "PcieRpAdvancedErrorReporting[0]" = "1"
 			register "PcieRpLtrEnable[0]" = "true"
 			register "PcieRpClkReqSupport[0]" = "1"
@@ -260,7 +259,6 @@ chip soc/intel/skylake
 		end
 		device ref pcie_rp7	on
 			# NGFF; x2
-			register "PcieRpEnable[6]" = "true"
 			register "PcieRpAdvancedErrorReporting[6]" = "1"
 			register "PcieRpLtrEnable[6]" = "true"
 			register "PcieRpClkReqSupport[6]" = "1"
@@ -269,7 +267,6 @@ chip soc/intel/skylake
 		end
 		device ref pcie_rp9	on
 			# LAN
-			register "PcieRpEnable[8]" = "true"
 			register "PcieRpAdvancedErrorReporting[8]" = "1"
 			register "PcieRpLtrEnable[8]" = "true"
 			register "PcieRpClkReqSupport[8]" = "1"
@@ -278,7 +275,6 @@ chip soc/intel/skylake
 		end
 		device ref pcie_rp10	on
 			# WLAN
-			register "PcieRpEnable[9]" = "true"
 			register "PcieRpAdvancedErrorReporting[9]" = "1"
 			register "PcieRpLtrEnable[9]" = "true"
 			register "PcieRpClkReqSupport[9]" = "1"
diff --git a/src/mainboard/asrock/h110m/devicetree.cb b/src/mainboard/asrock/h110m/devicetree.cb
index cc36ce8ec7..9be53d7b7d 100644
--- a/src/mainboard/asrock/h110m/devicetree.cb
+++ b/src/mainboard/asrock/h110m/devicetree.cb
@@ -113,7 +113,6 @@ chip soc/intel/skylake
 		end
 		device ref pcie_rp1	on	end
 		device ref pcie_rp5	on
-			register "PcieRpEnable[4]"			= "1"
 			register "PcieRpClkReqSupport[4]"		= "1"
 			register "PcieRpClkReqNumber[4]"		= "2"
 			register "PcieRpAdvancedErrorReporting[4]"	= "1"
@@ -122,7 +121,6 @@ chip soc/intel/skylake
 			register "PcieRpHotPlug[4]"			= "1"
 		end
 		device ref pcie_rp6	on
-			register "PcieRpEnable[5]"			= "1"
 
 			# Disable CLKREQ#, since onboard LAN is always present
 			register "PcieRpClkReqSupport[5]"		= "0"
@@ -131,7 +129,6 @@ chip soc/intel/skylake
 			register "PcieRpClkSrcNumber[5]"		= "1"
 		end
 		device ref pcie_rp7	on
-			register "PcieRpEnable[6]"			= "1"
 			register "PcieRpClkReqSupport[6]"		= "1"
 			register "PcieRpClkReqNumber[6]"		= "3"
 			register "PcieRpAdvancedErrorReporting[6]"	= "1"
diff --git a/src/mainboard/clevo/kbl-u/variants/n13xwu/devicetree.cb b/src/mainboard/clevo/kbl-u/variants/n13xwu/devicetree.cb
index 15e7064131..54c59ddf40 100644
--- a/src/mainboard/clevo/kbl-u/variants/n13xwu/devicetree.cb
+++ b/src/mainboard/clevo/kbl-u/variants/n13xwu/devicetree.cb
@@ -66,7 +66,6 @@ chip soc/intel/skylake
 		device ref uart2	on	end
 		device ref pcie_rp1	on
 			device pci 00.0 on end # x4 TBT
-			register "PcieRpEnable[0]" = "true"
 			register "PcieRpClkReqSupport[0]" = "1"
 			register "PcieRpClkReqNumber[0]" = "4"
 			register "PcieRpClkSrcNumber[0]" = "4"
@@ -76,7 +75,6 @@ chip soc/intel/skylake
 		end
 		device ref pcie_rp5	on
 			device pci 00.0 on end # x1 LAN
-			register "PcieRpEnable[4]" = "true"
 			register "PcieRpClkReqSupport[4]" = "1"
 			register "PcieRpClkReqNumber[4]" = "3"
 			register "PcieRpClkSrcNumber[4]" = "3"
@@ -84,7 +82,6 @@ chip soc/intel/skylake
 		end
 		device ref pcie_rp6	on
 			device pci 00.0 on end # x1 WLAN
-			register "PcieRpEnable[5]" = "true"
 			register "PcieRpClkReqSupport[5]" = "1"
 			register "PcieRpClkReqNumber[5]" = "2"
 			register "PcieRpClkSrcNumber[5]" = "2"
@@ -93,7 +90,6 @@ chip soc/intel/skylake
 		end
 		device ref pcie_rp9	on
 			device pci 00.0 on end # x4 M.2/M (J_SSD1)
-			register "PcieRpEnable[8]" = "true"
 			register "PcieRpClkReqSupport[8]" = "1"
 			register "PcieRpClkReqNumber[8]" = "5"
 			register "PcieRpClkSrcNumber[8]" = "5"
diff --git a/src/mainboard/dell/optiplex_3050/devicetree.cb b/src/mainboard/dell/optiplex_3050/devicetree.cb
index da11085ab6..0d2adff74a 100644
--- a/src/mainboard/dell/optiplex_3050/devicetree.cb
+++ b/src/mainboard/dell/optiplex_3050/devicetree.cb
@@ -39,7 +39,6 @@ chip soc/intel/skylake
 
 		# M.2 SSD
 		device ref pcie_rp21 on
-			register "PcieRpEnable[20]"                     = "1"
 			register "PcieRpClkReqSupport[20]"              = "1"
 			register "PcieRpClkReqNumber[20]"               = "3"
 			register "PcieRpAdvancedErrorReporting[20]"     = "1"
@@ -50,14 +49,12 @@ chip soc/intel/skylake
 
 		# Realtek LAN
 		device ref pcie_rp5 on
-			register "PcieRpEnable[4]"			= "1"
 			register "PcieRpClkReqSupport[4]"		= "0"
 			register "PcieRpHotPlug[4]"			= "0"
 		end
 
 		# M.2 WiFi
 		device ref pcie_rp8 on
-			register "PcieRpEnable[7]"			= "1"
 			register "PcieRpClkReqSupport[7]"		= "0"
 			register "PcieRpHotPlug[7]"			= "1"
 		end
diff --git a/src/mainboard/facebook/monolith/devicetree.cb b/src/mainboard/facebook/monolith/devicetree.cb
index d87db24114..6cacba505a 100644
--- a/src/mainboard/facebook/monolith/devicetree.cb
+++ b/src/mainboard/facebook/monolith/devicetree.cb
@@ -157,7 +157,6 @@ chip soc/intel/skylake
 		device ref pcie_rp3	on
 			# x1 baseboard WWAN
 			# PCIE Port 3 x1 -> Module x1 : Mapped to PCIe 2 on the baseboard
-			register "PcieRpEnable[2]" = "true"
 			register "PcieRpClkReqSupport[2]" = "0"
 			register "PcieRpMaxPayload[2]" = "RpMaxPayload_256"
 			register "PcieRpLtrEnable[2]" = "true"
@@ -167,7 +166,6 @@ chip soc/intel/skylake
 		device ref pcie_rp6	on
 			# x1 baseboard i210
 			# PCIE Port 6 x1 -> BASEBOARD x1 i210 : Mapped to PCIe 4 on the baseboard
-			register "PcieRpEnable[5]" = "true"
 			register "PcieRpClkReqSupport[5]" = "0"
 			register "PcieRpMaxPayload[5]" = "RpMaxPayload_256"
 			register "PcieRpLtrEnable[5]" = "true"
@@ -177,7 +175,6 @@ chip soc/intel/skylake
 		device ref pcie_rp9	on
 			# x4 FPGA
 			# PCIE Port 9 x4 -> BASEBOARD PEG0-3 FPGA
-			register "PcieRpEnable[8]" = "true"
 			register "PcieRpClkReqSupport[8]" = "0"
 			register "PcieRpHotPlug[8]" = "1"
 			register "PcieRpMaxPayload[8]" = "RpMaxPayload_256"
diff --git a/src/mainboard/google/eve/devicetree.cb b/src/mainboard/google/eve/devicetree.cb
index 5ff43927a5..15e2ff6095 100644
--- a/src/mainboard/google/eve/devicetree.cb
+++ b/src/mainboard/google/eve/devicetree.cb
@@ -336,7 +336,6 @@ chip soc/intel/skylake
 			end
 		end # I2C #4
 		device ref pcie_rp1	on
-			register "PcieRpEnable[0]" = "true"
 			register "PcieRpClkReqSupport[0]" = "1"
 			register "PcieRpClkReqNumber[0]" = "1"
 			register "PcieRpAdvancedErrorReporting[0]" = "1"
@@ -349,7 +348,6 @@ chip soc/intel/skylake
 			end
 		end
 		device ref pcie_rp5	on
-			register "PcieRpEnable[4]" = "true"
 			register "PcieRpClkReqSupport[4]" = "1"
 			register "PcieRpClkReqNumber[4]" = "4"
 			register "PcieRpAdvancedErrorReporting[4]" = "1"
diff --git a/src/mainboard/google/fizz/variants/baseboard/devicetree.cb b/src/mainboard/google/fizz/variants/baseboard/devicetree.cb
index d2bb08e830..8cf8d27da6 100644
--- a/src/mainboard/google/fizz/variants/baseboard/devicetree.cb
+++ b/src/mainboard/google/fizz/variants/baseboard/devicetree.cb
@@ -289,7 +289,6 @@ chip soc/intel/skylake
 		device ref pcie_rp3	on
 			# LAN, will be swapped to port 1 by FSP
 			# x1
-			register "PcieRpEnable[2]" = "true"
 			register "PcieRpClkReqSupport[2]" = "1"
 			register "PcieRpClkReqNumber[2]" = "0"
 			register "PcieRpAdvancedErrorReporting[2]" = "1"
@@ -304,7 +303,6 @@ chip soc/intel/skylake
 		end
 		device ref pcie_rp4	on
 			# x1 WLAN
-			register "PcieRpEnable[3]" = "true"
 			register "PcieRpClkReqSupport[3]" = "1"
 			register "PcieRpClkReqNumber[3]" = "5"
 			register "PcieRpAdvancedErrorReporting[3]" = "1"
@@ -317,7 +315,6 @@ chip soc/intel/skylake
 		end
 		device ref pcie_rp5	on
 			# x4 NVMe
-			register "PcieRpEnable[4]" = "true"
 			register "PcieRpClkReqSupport[4]" = "1"
 			register "PcieRpClkReqNumber[4]" = "1"
 			register "PcieRpAdvancedErrorReporting[4]" = "1"
@@ -326,7 +323,6 @@ chip soc/intel/skylake
 		end
 		device ref pcie_rp9	on
 			# 2nd LAN
-			register "PcieRpEnable[8]" = "true"
 			register "PcieRpClkReqSupport[8]" = "1"
 			register "PcieRpClkReqNumber[8]" = "2"
 			register "PcieRpAdvancedErrorReporting[8]" = "1"
@@ -339,7 +335,6 @@ chip soc/intel/skylake
 			end
 		end
 		device ref pcie_rp11	on
-			register "PcieRpEnable[10]" = "true"
 			register "PcieRpClkReqSupport[10]" = "1"
 			register "PcieRpClkReqNumber[10]" = "2"
 			register "PcieRpAdvancedErrorReporting[10]" = "1"
@@ -347,7 +342,6 @@ chip soc/intel/skylake
 			register "PcieRpClkSrcNumber[10]" = "2"
 		end
 		device ref pcie_rp12	on
-			register "PcieRpEnable[11]" = "true"
 			register "PcieRpClkReqSupport[11]" = "1"
 			register "PcieRpClkReqNumber[11]" = "2"
 			register "PcieRpAdvancedErrorReporting[11]" = "1"
diff --git a/src/mainboard/google/fizz/variants/endeavour/overridetree.cb b/src/mainboard/google/fizz/variants/endeavour/overridetree.cb
index 7b6de183e7..8421ae477e 100644
--- a/src/mainboard/google/fizz/variants/endeavour/overridetree.cb
+++ b/src/mainboard/google/fizz/variants/endeavour/overridetree.cb
@@ -116,7 +116,6 @@ chip soc/intel/skylake
 		end
 		device ref pcie_rp7 on
 			# x1 TPU1
-			register "PcieRpEnable[6]" = "true"
 			register "PcieRpClkReqSupport[6]" = "1"
 			register "PcieRpClkReqNumber[6]" = "4"
 			register "PcieRpAdvancedErrorReporting[6]" = "1"
@@ -125,7 +124,6 @@ chip soc/intel/skylake
 		end
 		device ref pcie_rp8 on
 			# x1 TPU0
-			register "PcieRpEnable[7]" = "true"
 			register "PcieRpClkReqSupport[7]" = "1"
 			register "PcieRpClkReqNumber[7]" = "2"
 			register "PcieRpAdvancedErrorReporting[7]" = "1"
@@ -134,20 +132,13 @@ chip soc/intel/skylake
 		end
 		device ref pcie_rp9 on
 			# x4 i350 LAN
-			register "PcieRpEnable[8]" = "true"
 			register "PcieRpClkReqSupport[8]" = "0"
 			register "PcieRpAdvancedErrorReporting[8]" = "1"
 			register "PcieRpLtrEnable[8]" = "true"
 			register "PcieRpClkSrcNumber[8]" = "2"
 		end
-		device ref pcie_rp10 off
-			register "PcieRpEnable[9]" = "false"
-		end
-		device ref pcie_rp11 off
-			register "PcieRpEnable[10]" = "false"
-		end
-		device ref pcie_rp12 off
-			register "PcieRpEnable[11]" = "false"
-		end
+		device ref pcie_rp10 off end
+		device ref pcie_rp11 off end
+		device ref pcie_rp12 off end
 	end
 end
diff --git a/src/mainboard/google/glados/devicetree.cb b/src/mainboard/google/glados/devicetree.cb
index bac1ed3cc0..5bbcd2cf17 100644
--- a/src/mainboard/google/glados/devicetree.cb
+++ b/src/mainboard/google/glados/devicetree.cb
@@ -78,7 +78,6 @@ chip soc/intel/skylake
 		device ref uart2	on  end
 		device ref i2c4		on  end
 		device ref pcie_rp1	on
-			register "PcieRpEnable[0]" = "true"
 			register "PcieRpClkReqSupport[0]" = "1"
 			register "PcieRpClkReqNumber[0]" = "1"
 			chip drivers/wifi/generic
diff --git a/src/mainboard/google/poppy/variants/atlas/devicetree.cb b/src/mainboard/google/poppy/variants/atlas/devicetree.cb
index d1a3542dc3..0ef59f8a91 100644
--- a/src/mainboard/google/poppy/variants/atlas/devicetree.cb
+++ b/src/mainboard/google/poppy/variants/atlas/devicetree.cb
@@ -310,7 +310,6 @@ chip soc/intel/skylake
 		end
 		device ref pcie_rp1		on
 			# WLAN
-			register "PcieRpEnable[0]" = "true"
 			register "PcieRpClkReqSupport[0]" = "1"
 			register "PcieRpClkReqNumber[0]" = "1"
 			register "PcieRpClkSrcNumber[0]" = "1"
diff --git a/src/mainboard/google/poppy/variants/baseboard/devicetree.cb b/src/mainboard/google/poppy/variants/baseboard/devicetree.cb
index 160dfd333e..5bc4bdce00 100644
--- a/src/mainboard/google/poppy/variants/baseboard/devicetree.cb
+++ b/src/mainboard/google/poppy/variants/baseboard/devicetree.cb
@@ -323,7 +323,6 @@ chip soc/intel/skylake
 		end
 		device ref i2c4			on end
 		device ref pcie_rp1		on
-			register "PcieRpEnable[0]" = "true"
 			register "PcieRpClkReqSupport[0]" = "1"
 			register "PcieRpClkReqNumber[0]" = "1"
 			register "PcieRpAdvancedErrorReporting[0]" = "1"
diff --git a/src/mainboard/google/poppy/variants/nami/devicetree.cb b/src/mainboard/google/poppy/variants/nami/devicetree.cb
index e32e5e4557..2e7726ec1d 100644
--- a/src/mainboard/google/poppy/variants/nami/devicetree.cb
+++ b/src/mainboard/google/poppy/variants/nami/devicetree.cb
@@ -366,7 +366,6 @@ chip soc/intel/skylake
 		device ref pcie_rp1		on  end
 		device ref pcie_rp4		on
 			# x1
-			register "PcieRpEnable[3]" = "true"
 			register "PcieRpClkReqSupport[3]" = "1"
 			register "PcieRpClkReqNumber[3]" = "1"
 			register "PcieRpClkSrcNumber[3]" = "1"
@@ -379,7 +378,6 @@ chip soc/intel/skylake
 		end
 		device ref pcie_rp5		on
 			# x4
-			register "PcieRpEnable[4]" = "true"
 			register "PcieRpClkReqSupport[4]" = "1"
 			register "PcieRpClkReqNumber[4]" = "3"
 			register "PcieRpClkSrcNumber[4]" = "3"
@@ -388,7 +386,6 @@ chip soc/intel/skylake
 		end
 		device ref pcie_rp9		on
 			# x2
-			register "PcieRpEnable[8]" = "true"
 			register "PcieRpClkReqSupport[8]" = "1"
 			register "PcieRpClkReqNumber[8]" = "2"
 			register "PcieRpClkSrcNumber[8]" = "2"
diff --git a/src/mainboard/google/poppy/variants/nautilus/devicetree.cb b/src/mainboard/google/poppy/variants/nautilus/devicetree.cb
index dfb11ee48c..b226e6b6a6 100644
--- a/src/mainboard/google/poppy/variants/nautilus/devicetree.cb
+++ b/src/mainboard/google/poppy/variants/nautilus/devicetree.cb
@@ -361,7 +361,6 @@ chip soc/intel/skylake
 			end
 		end
 		device ref pcie_rp1		on
-			register "PcieRpEnable[0]" = "true"
 			register "PcieRpClkReqSupport[0]" = "1"
 			register "PcieRpClkReqNumber[0]" = "1"
 			register "PcieRpClkSrcNumber[0]" = "1"
diff --git a/src/mainboard/google/poppy/variants/nocturne/devicetree.cb b/src/mainboard/google/poppy/variants/nocturne/devicetree.cb
index e64d408eb2..fd95a61b45 100644
--- a/src/mainboard/google/poppy/variants/nocturne/devicetree.cb
+++ b/src/mainboard/google/poppy/variants/nocturne/devicetree.cb
@@ -325,7 +325,6 @@ chip soc/intel/skylake
 			end
 		end
 		device ref pcie_rp1		on
-			register "PcieRpEnable[0]" = "true"
 			register "PcieRpClkReqSupport[0]" = "1"
 			register "PcieRpClkReqNumber[0]" = "1"
 			register "PcieRpClkSrcNumber[0]" = "1"
@@ -338,7 +337,6 @@ chip soc/intel/skylake
 		end
 		device ref pcie_rp9		on
 			# x2
-			register "PcieRpEnable[8]" = "true"
 			register "PcieRpClkReqSupport[8]" = "1"
 			register "PcieRpClkReqNumber[8]" = "2"
 			register "PcieRpClkSrcNumber[8]" = "3"
diff --git a/src/mainboard/google/poppy/variants/rammus/devicetree.cb b/src/mainboard/google/poppy/variants/rammus/devicetree.cb
index 3251916ffc..a84e45748c 100644
--- a/src/mainboard/google/poppy/variants/rammus/devicetree.cb
+++ b/src/mainboard/google/poppy/variants/rammus/devicetree.cb
@@ -314,7 +314,6 @@ chip soc/intel/skylake
 			end
 		end
 		device ref pcie_rp1		on
-			register "PcieRpEnable[0]" = "true"
 			register "PcieRpClkReqSupport[0]" = "1"
 			register "PcieRpClkReqNumber[0]" = "1"
 			register "PcieRpClkSrcNumber[0]" = "1"
diff --git a/src/mainboard/google/poppy/variants/soraka/devicetree.cb b/src/mainboard/google/poppy/variants/soraka/devicetree.cb
index 7602bcb6bf..29d6974bc1 100644
--- a/src/mainboard/google/poppy/variants/soraka/devicetree.cb
+++ b/src/mainboard/google/poppy/variants/soraka/devicetree.cb
@@ -305,7 +305,6 @@ chip soc/intel/skylake
 		end
 		device ref i2c4			on  end
 		device ref pcie_rp1		on
-			register "PcieRpEnable[0]" = "true"
 			register "PcieRpClkReqSupport[0]" = "1"
 			register "PcieRpClkReqNumber[0]" = "1"
 			register "PcieRpAdvancedErrorReporting[0]" = "1"
diff --git a/src/mainboard/hp/280_g2/devicetree.cb b/src/mainboard/hp/280_g2/devicetree.cb
index afb564ece5..4c17d5de48 100644
--- a/src/mainboard/hp/280_g2/devicetree.cb
+++ b/src/mainboard/hp/280_g2/devicetree.cb
@@ -64,14 +64,12 @@ chip soc/intel/skylake
 		device ref uart2	on	end
 		device ref pcie_rp5	on
 			# IT8893E PCI Bridge
-			register "PcieRpEnable[4]"			= "1"
 			register "PcieRpLtrEnable[4]"			= "true"
 			register "PcieRpAdvancedErrorReporting[4]"	= "1"
 			register "PcieRpClkSrcNumber[4]"		= "11"
 		end
 		device ref pcie_rp6	on
 			# PCIe x1 slot
-			register "PcieRpEnable[5]"			= "1"
 			register "PcieRpHotPlug[5]"			= "1"
 			register "PcieRpLtrEnable[5]"			= "true"
 			register "PcieRpAdvancedErrorReporting[5]"	= "1"
@@ -79,14 +77,12 @@ chip soc/intel/skylake
 		end
 		device ref pcie_rp7	on
 			# RTL8111 GbE NIC
-			register "PcieRpEnable[6]"			= "1"
 			register "PcieRpLtrEnable[6]"			= "true"
 			register "PcieRpAdvancedErrorReporting[6]"	= "1"
 			register "PcieRpClkSrcNumber[6]"		= "10"
 		end
 		device ref pcie_rp8	on
 			# M.2 2230 slot
-			register "PcieRpEnable[7]"			= "1"
 			register "PcieRpHotPlug[7]"			= "1"
 			register "PcieRpLtrEnable[7]"			= "true"
 			register "PcieRpAdvancedErrorReporting[7]"	= "1"
diff --git a/src/mainboard/intel/kblrvp/variants/rvp11/overridetree.cb b/src/mainboard/intel/kblrvp/variants/rvp11/overridetree.cb
index 5da43c2098..cc3d9555be 100644
--- a/src/mainboard/intel/kblrvp/variants/rvp11/overridetree.cb
+++ b/src/mainboard/intel/kblrvp/variants/rvp11/overridetree.cb
@@ -75,37 +75,31 @@ chip soc/intel/skylake
 		end
 		device ref i2c4		off end
 		device ref pcie_rp6	on
-			register "PcieRpEnable[5]" = "true"
 			register "PcieRpClkReqSupport[5]" = "1"
 			register "PcieRpClkReqNumber[5]" = "1"
 			register "PcieRpClkSrcNumber[5]" = "1"
 		end
 		device ref pcie_rp7	on
-			register "PcieRpEnable[6]" = "true"
 			register "PcieRpClkReqSupport[6]" = "1"
 			register "PcieRpClkReqNumber[6]" = "2"
 			register "PcieRpClkSrcNumber[6]" = "2"
 		end
 		device ref pcie_rp8	on
-			register "PcieRpEnable[7]" = "true"
 			register "PcieRpClkReqSupport[7]" = "1"
 			register "PcieRpClkReqNumber[7]" = "3"
 			register "PcieRpClkSrcNumber[7]" = "3"
 		end
 		device ref pcie_rp9	on
-			register "PcieRpEnable[8]" = "true"
 			register "PcieRpClkReqSupport[8]" = "1"
 			register "PcieRpClkReqNumber[8]" = "4"
 			register "PcieRpClkSrcNumber[8]" = "4"
 		end
 		device ref pcie_rp14	on
-			register "PcieRpEnable[13]" = "true"
 			register "PcieRpClkReqSupport[13]" = "1"
 			register "PcieRpClkReqNumber[13]" = "5"
 			register "PcieRpClkSrcNumber[13]" = "5"
 		end
 		device ref pcie_rp17	on
-			register "PcieRpEnable[16]" = "true"
 			register "PcieRpClkReqSupport[16]" = "1"
 			register "PcieRpClkReqNumber[16]" = "7"
 			register "PcieRpClkSrcNumber[16]" = "7"
diff --git a/src/mainboard/intel/kblrvp/variants/rvp3/overridetree.cb b/src/mainboard/intel/kblrvp/variants/rvp3/overridetree.cb
index 1880cd9fa9..93e62e2776 100644
--- a/src/mainboard/intel/kblrvp/variants/rvp3/overridetree.cb
+++ b/src/mainboard/intel/kblrvp/variants/rvp3/overridetree.cb
@@ -77,35 +77,30 @@ chip soc/intel/skylake
 		device ref cio		on  end
 		device ref pcie_rp1	on
 			# PCIE x4 -> SLOT1
-			register "PcieRpEnable[0]" = "true"
 			register "PcieRpClkReqSupport[0]" = "1"
 			register "PcieRpClkReqNumber[0]" = "2"
 			register "PcieRpClkSrcNumber[0]" = "2"
 		end
 		device ref pcie_rp5	on
 			# PCIE x1 -> SLOT2/LAN
-			register "PcieRpEnable[4]" = "true"
 			register "PcieRpClkReqSupport[4]" = "1"
 			register "PcieRpClkReqNumber[4]" = "3"
 			register "PcieRpClkSrcNumber[4]" = "3"
 		end
 		device ref pcie_rp6	on
 			# PCIE x1 -> SLOT3
-			register "PcieRpEnable[5]" = "true"
 			register "PcieRpClkReqSupport[5]" = "1"
 			register "PcieRpClkReqNumber[5]" = "1"
 			register "PcieRpClkSrcNumber[5]" = "1"
 		end
 		device ref pcie_rp9	on
 			# PCIE x1 -> WLAN
-			register "PcieRpEnable[8]" = "true"
 			register "PcieRpClkReqSupport[8]" = "1"
 			register "PcieRpClkReqNumber[8]" = "5"
 			register "PcieRpClkSrcNumber[8]" = "5"
 		end
 		device ref pcie_rp10	on
 			# PCIE x1 -> WiGig
-			register "PcieRpEnable[9]" = "true"
 			register "PcieRpClkReqSupport[9]" = "1"
 			register "PcieRpClkReqNumber[9]" = "4"
 			register "PcieRpClkSrcNumber[9]" = "4"
diff --git a/src/mainboard/intel/kblrvp/variants/rvp7/overridetree.cb b/src/mainboard/intel/kblrvp/variants/rvp7/overridetree.cb
index a030fe758f..a5d30d3640 100644
--- a/src/mainboard/intel/kblrvp/variants/rvp7/overridetree.cb
+++ b/src/mainboard/intel/kblrvp/variants/rvp7/overridetree.cb
@@ -124,31 +124,26 @@ chip soc/intel/skylake
 			}"
 		end
 		device ref pcie_rp3	on
-			register "PcieRpEnable[2]" = "true"
 			register "PcieRpClkReqSupport[2]" = "1"
 			register "PcieRpClkReqNumber[2]" = "5"
 			register "PcieRpClkSrcNumber[2]" = "5"
 		end
 		device ref pcie_rp4	on
-			register "PcieRpEnable[3]" = "true"
 			register "PcieRpClkReqSupport[3]" = "1"
 			register "PcieRpClkReqNumber[3]" = "2"
 			register "PcieRpClkSrcNumber[3]" = "2"
 		end
 		device ref pcie_rp5	on
-			register "PcieRpEnable[4]" = "true"
 			register "PcieRpClkReqSupport[4]" = "1"
 			register "PcieRpClkReqNumber[4]" = "3"
 			register "PcieRpClkSrcNumber[4]" = "3"
 		end
 		device ref pcie_rp6	on
-			register "PcieRpEnable[5]" = "true"
 			register "PcieRpClkReqSupport[5]" = "1"
 			register "PcieRpClkReqNumber[5]" = "4"
 			register "PcieRpClkSrcNumber[5]" = "4"
 		end
 		device ref pcie_rp9	on
-			register "PcieRpEnable[8]" = "true"
 			register "PcieRpClkReqSupport[8]" = "1"
 			register "PcieRpClkReqNumber[8]" = "1"
 			register "PcieRpClkSrcNumber[8]" = "1"
diff --git a/src/mainboard/intel/kblrvp/variants/rvp8/overridetree.cb b/src/mainboard/intel/kblrvp/variants/rvp8/overridetree.cb
index 1b8e39124f..2d8a9c1263 100644
--- a/src/mainboard/intel/kblrvp/variants/rvp8/overridetree.cb
+++ b/src/mainboard/intel/kblrvp/variants/rvp8/overridetree.cb
@@ -148,22 +148,18 @@ chip soc/intel/skylake
 		device ref pcie_rp1	off end
 		device ref pcie_rp3	on  end
 		device ref pcie_rp4	on
-			register "PcieRpEnable[3]" = "true"
 			register "PcieRpClkReqSupport[3]" = "1"
 			register "PcieRpClkReqNumber[3]" = "2"
 		end
 		device ref pcie_rp5	on
-			register "PcieRpEnable[4]" = "true"
 			register "PcieRpClkReqSupport[4]" = "1"
 			register "PcieRpClkReqNumber[4]" = "1"
 		end
 		device ref pcie_rp9	on
-			register "PcieRpEnable[8]" = "true"
 			register "PcieRpClkReqSupport[8]" = "1"
 			register "PcieRpClkReqNumber[8]" = "6"
 		end
 		device ref pcie_rp17	on
-			register "PcieRpEnable[16]" = "true"
 			register "PcieRpClkReqSupport[16]" = "1"
 			register "PcieRpClkReqNumber[16]" = "7"
 		end
diff --git a/src/mainboard/intel/kunimitsu/devicetree.cb b/src/mainboard/intel/kunimitsu/devicetree.cb
index 758b913c98..c52b290d93 100644
--- a/src/mainboard/intel/kunimitsu/devicetree.cb
+++ b/src/mainboard/intel/kunimitsu/devicetree.cb
@@ -210,7 +210,6 @@ chip soc/intel/skylake
 			end
 		end
 		device ref pcie_rp1	on
-			register "PcieRpEnable[0]" = "true"
 			register "PcieRpClkReqSupport[0]" = "1"
 			register "PcieRpClkReqNumber[0]" = "1"
 			chip drivers/wifi/generic
@@ -219,7 +218,6 @@ chip soc/intel/skylake
 			end
 		end
 		device ref pcie_rp5	on
-			register "PcieRpEnable[4]" = "true"
 			register "PcieRpClkReqSupport[4]" = "1"
 			register "PcieRpClkReqNumber[4]" = "2"
 		end
diff --git a/src/mainboard/intel/saddlebrook/devicetree.cb b/src/mainboard/intel/saddlebrook/devicetree.cb
index fd2ae4108b..b6000910e7 100644
--- a/src/mainboard/intel/saddlebrook/devicetree.cb
+++ b/src/mainboard/intel/saddlebrook/devicetree.cb
@@ -186,24 +186,20 @@ chip soc/intel/skylake
 		device ref i2c4		on end
 		device ref pcie_rp1	on end
 		device ref pcie_rp6	on
-			register "PcieRpEnable[5]" = "true"
 			register "PcieRpClkReqSupport[5]" = "1"
 			register "PcieRpClkReqNumber[5]" = "0"
 		end
 		device ref pcie_rp8	on
 			# x1
-			register "PcieRpEnable[7]" = "true"
 			register "PcieRpClkReqSupport[7]" = "1"
 			register "PcieRpClkReqNumber[7]" = "3"
 		end
 		device ref pcie_rp9	on
 			# x4
-			register "PcieRpEnable[8]" = "true"
 			register "PcieRpClkReqSupport[8]" = "1"
 			register "PcieRpClkReqNumber[8]" = "4"
 		end
 		device ref pcie_rp13	on
-			register "PcieRpEnable[12]" = "true"
 			register "PcieRpClkReqSupport[12]" = "1"
 			register "PcieRpClkReqNumber[12]" = "1"
 		end
diff --git a/src/mainboard/kontron/bsl6/devicetree.cb b/src/mainboard/kontron/bsl6/devicetree.cb
index 9fb142971f..26f31e026e 100644
--- a/src/mainboard/kontron/bsl6/devicetree.cb
+++ b/src/mainboard/kontron/bsl6/devicetree.cb
@@ -85,15 +85,9 @@ chip soc/intel/skylake
 				[2] = 1,
 			}"
 		end
-		device ref pcie_rp9	on
-			register "PcieRpEnable[8]" = "true"
-		end
-		device ref pcie_rp10	on
-			register "PcieRpEnable[9]" = "true"
-		end
-		device ref pcie_rp11	on
-			register "PcieRpEnable[10]" = "true"
-		end
+		device ref pcie_rp9	on  end
+		device ref pcie_rp10	on  end
+		device ref pcie_rp11	on  end
 		device ref lpc_espi	on
 			register "serirq_mode" = "SERIRQ_CONTINUOUS"
 
diff --git a/src/mainboard/kontron/bsl6/variants/bsl6/overridetree.cb b/src/mainboard/kontron/bsl6/variants/bsl6/overridetree.cb
index 5624d6bf38..2fa0145d75 100644
--- a/src/mainboard/kontron/bsl6/variants/bsl6/overridetree.cb
+++ b/src/mainboard/kontron/bsl6/variants/bsl6/overridetree.cb
@@ -20,26 +20,11 @@ chip soc/intel/skylake
 		device ref sata		on
 			register "SataPortsEnable[3]"	= "1"
 		end
-		device ref pcie_rp1	on
-			# COMe 4
-			register "PcieRpEnable[0]" = "true"
-		end
-		device ref pcie_rp2	on
-			# COMe 5
-			register "PcieRpEnable[1]" = "true"
-		end
-		device ref pcie_rp3	on
-			# COMe 6
-			register "PcieRpEnable[2]" = "true"
-		end
-		device ref pcie_rp4	on
-			# COMe 7
-			register "PcieRpEnable[3]" = "true"
-		end
-		device ref pcie_rp12	on
-			# COMe 3
-			register "PcieRpEnable[11]" = "true"
-		end
+		device ref pcie_rp1	on  end # COMe 4
+		device ref pcie_rp2	on  end # COMe 5
+		device ref pcie_rp3	on  end # COMe 6
+		device ref pcie_rp4	on  end # COMe 7
+		device ref pcie_rp12	on  end # COMe 3
 		device ref smbus	on
 			chip drivers/i2c/nct7802y
 				register "peci[0]" = "{ PECI_DOMAIN_0, 100 }"
diff --git a/src/mainboard/lenovo/m900/devicetree.cb b/src/mainboard/lenovo/m900/devicetree.cb
index 4f96ac186e..8b550a74d3 100644
--- a/src/mainboard/lenovo/m900/devicetree.cb
+++ b/src/mainboard/lenovo/m900/devicetree.cb
@@ -85,7 +85,6 @@ chip soc/intel/skylake
 			}"
 		end
 		device ref pcie_rp5 on
-			register "PcieRpEnable[4]"			= "true"
 			register "PcieRpClkReqSupport[4]"		= "false"
 			register "PcieRpAdvancedErrorReporting[4]"	= "true"
 			register "PcieRpLtrEnable[4]"			= "true"
@@ -96,7 +95,6 @@ chip soc/intel/skylake
 					 "PCIE1X_1" "SlotDataBusWidth1X"
 		end
 		device ref pcie_rp7 on # M.2 E-key
-			register "PcieRpEnable[6]"			= "true"
 			register "PcieRpClkReqSupport[6]"		= "true"
 			register "PcieRpClkReqNumber[6]"		= "4"
 			register "PcieRpAdvancedErrorReporting[6]"	= "true"
@@ -108,7 +106,6 @@ chip soc/intel/skylake
 					 "M_2" "SlotDataBusWidth1X"
 		end
 		device ref pcie_rp9 on
-			register "PcieRpEnable[8]"			= "true"
 			register "PcieRpClkReqSupport[8]"		= "false"
 			register "PcieRpAdvancedErrorReporting[8]"	= "true"
 			register "PcieRpLtrEnable[8]"			= "true"
diff --git a/src/mainboard/lenovo/m900_tiny/devicetree.cb b/src/mainboard/lenovo/m900_tiny/devicetree.cb
index 88245c3c1d..439cbc1ebc 100644
--- a/src/mainboard/lenovo/m900_tiny/devicetree.cb
+++ b/src/mainboard/lenovo/m900_tiny/devicetree.cb
@@ -161,14 +161,12 @@ chip soc/intel/skylake
 			}"
 		end
 		device ref pcie_rp17 on # M.2 2280 / 2242 - SSD
-			register "PcieRpEnable[16]"			= "1"
 			register "PcieRpAdvancedErrorReporting[16]"	= "1"
 			register "PcieRpLtrEnable[16]"			= "true"
 			register "PcieRpClkSrcNumber[16]"		= "7"
 			register "PcieRpHotPlug[16]"			= "1"
 		end
 		device ref pcie_rp7 on # M.2 2230 - WLAN
-			register "PcieRpEnable[6]"			= "1"
 			register "PcieRpAdvancedErrorReporting[6]"	= "1"
 			register "PcieRpLtrEnable[6]"			= "true"
 			register "PcieRpClkSrcNumber[6]"		= "1"
diff --git a/src/mainboard/lenovo/thinkcentre_m710s/devicetree.cb b/src/mainboard/lenovo/thinkcentre_m710s/devicetree.cb
index 4d1828c5ab..04e6e7d672 100644
--- a/src/mainboard/lenovo/thinkcentre_m710s/devicetree.cb
+++ b/src/mainboard/lenovo/thinkcentre_m710s/devicetree.cb
@@ -160,7 +160,6 @@ chip soc/intel/skylake
 			}"
 		end
 		device ref pcie_rp5	on	# USB_LAN
-			register "PcieRpEnable[4]"                 = "true"
 			register "PcieRpLtrEnable[4]"              = "true"
 			register "PcieRpClkReqSupport[4]"          = "true"
 			register "PcieRpClkReqNumber[4]"           = "5"
@@ -173,7 +172,6 @@ chip soc/intel/skylake
 			                 "PCIE1X_2"
 			                 "SlotDataBusWidth1X"
 
-			register "PcieRpEnable[6]"                 = "true"
 			register "PcieRpLtrEnable[6]"              = "true"
 			register "PcieRpClkReqSupport[6]"          = "true"
 			register "PcieRpClkReqNumber[6]"           = "7"
@@ -186,8 +184,6 @@ chip soc/intel/skylake
 			                 "PCIE1X_1"
 			                 "SlotDataBusWidth1X"
 
-			register "PcieRpEnable[7]"                 = "true"
-			register "PcieRpLtrEnable[7]"              = "true"
 			register "PcieRpClkReqSupport[7]"          = "true"
 			register "PcieRpClkReqNumber[7]"           = "8"
 			register "PcieRpClkSrcNumber[7]"           = "8"
@@ -199,7 +195,6 @@ chip soc/intel/skylake
 			                 "M2_WIFI"
 			                 "SlotDataBusWidth1X"
 
-			register "PcieRpEnable[10]"                 = "true"
 			register "PcieRpLtrEnable[10]"              = "true"
 			register "PcieRpClkReqSupport[10]"          = "true"
 			register "PcieRpClkReqNumber[10]"           = "1"
@@ -212,7 +207,6 @@ chip soc/intel/skylake
 			                 "M2_SSD"
 			                 "SlotDataBusWidth1X"
 
-			register "PcieRpEnable[20]"                 = "true"
 			register "PcieRpLtrEnable[20]"              = "true"
 			register "PcieRpClkReqSupport[20]"          = "true"
 			register "PcieRpClkReqNumber[20]"           = "6"
diff --git a/src/mainboard/libretrend/lt1000/devicetree.cb b/src/mainboard/libretrend/lt1000/devicetree.cb
index 29d82de222..b503ad83eb 100644
--- a/src/mainboard/libretrend/lt1000/devicetree.cb
+++ b/src/mainboard/libretrend/lt1000/devicetree.cb
@@ -140,36 +140,28 @@ chip soc/intel/skylake
 			}"
 			register "SataSpeedLimit" = "2"
 		end
-		device ref pcie_rp3	on
-			register "PcieRpEnable[2]"  = "1"
-		end
+		device ref pcie_rp3	on  end
 		device ref pcie_rp4	on
-			register "PcieRpEnable[3]"  = "1"
 			register "PcieRpClkSrcNumber[3]"  = "1"
 		end
 		device ref pcie_rp5	on
-			register "PcieRpEnable[4]"  = "1"
 			register "PcieRpClkSrcNumber[4]"  = "2"
 			smbios_slot_desc "SlotTypePciExpressMini52pinWithoutBSKO"
 					 "SlotLengthOther" "MPCIE_WIFI1" "SlotDataBusWidth1X"
 		end
 		device ref pcie_rp6	on  end
 		device ref pcie_rp9	on
-			register "PcieRpEnable[8]"  = "1"
 			register "PcieRpClkSrcNumber[8]"  = "3"
 			smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther"
 					 "SSD_M.2 2242/2280" "SlotDataBusWidth4X"
 		end
 		device ref pcie_rp10	on
-			register "PcieRpEnable[9]"  = "1"
 			register "PcieRpClkSrcNumber[9]"  = "3"
 		end
 		device ref pcie_rp11	on
-			register "PcieRpEnable[10]" = "true"
 			register "PcieRpClkSrcNumber[10]" = "3"
 		end
 		device ref pcie_rp12	on
-			register "PcieRpEnable[11]" = "true"
 			register "PcieRpClkSrcNumber[11]" = "3"
 		end
 		device ref lpc_espi	on
diff --git a/src/mainboard/protectli/vault_kbl/devicetree.cb b/src/mainboard/protectli/vault_kbl/devicetree.cb
index 30152b5462..b47c53c7b5 100644
--- a/src/mainboard/protectli/vault_kbl/devicetree.cb
+++ b/src/mainboard/protectli/vault_kbl/devicetree.cb
@@ -142,49 +142,42 @@ chip soc/intel/skylake
 		end
 		device ref pcie_rp1	on
 			# LAN
-			register "PcieRpEnable[0]" = "true"
 			register "PcieRpAdvancedErrorReporting[0]" = "1"
 			register "PcieRpLtrEnable[0]" = "true"
 			register "PcieRpClkSrcNumber[0]" = "0"
 		end
 		device ref pcie_rp2	on
 			# LAN
-			register "PcieRpEnable[1]" = "true"
 			register "PcieRpAdvancedErrorReporting[1]" = "1"
 			register "PcieRpLtrEnable[1]" = "true"
 			register "PcieRpClkSrcNumber[1]" = "1"
 		end
 		device ref pcie_rp3	on
 			# LAN
-			register "PcieRpEnable[2]" = "true"
 			register "PcieRpAdvancedErrorReporting[2]" = "1"
 			register "PcieRpLtrEnable[2]" = "true"
 			register "PcieRpClkSrcNumber[2]" = "2"
 		end
 		device ref pcie_rp4	on
 			# LAN
-			register "PcieRpEnable[3]" = "true"
 			register "PcieRpAdvancedErrorReporting[3]" = "1"
 			register "PcieRpLtrEnable[3]" = "true"
 			register "PcieRpClkSrcNumber[3]" = "3"
 		end
 		device ref pcie_rp5	on
 			# LAN
-			register "PcieRpEnable[4]" = "true"
 			register "PcieRpAdvancedErrorReporting[4]" = "1"
 			register "PcieRpLtrEnable[4]" = "true"
 			register "PcieRpClkSrcNumber[4]" = "4"
 		end
 		device ref pcie_rp6	on
 			# LAN
-			register "PcieRpEnable[5]" = "true"
 			register "PcieRpAdvancedErrorReporting[5]" = "1"
 			register "PcieRpLtrEnable[5]" = "true"
 			register "PcieRpClkSrcNumber[5]" = "5"
 		end
 		device ref pcie_rp9	on
 			# mPCIe WIFI
-			register "PcieRpEnable[8]" = "true"
 			register "PcieRpAdvancedErrorReporting[8]" = "1"
 			register "PcieRpLtrEnable[8]" = "true"
 			register "PcieRpClkSrcNumber[8]" = "5"
diff --git a/src/mainboard/purism/librem_skl/devicetree.cb b/src/mainboard/purism/librem_skl/devicetree.cb
index 9af8046762..67330b444b 100644
--- a/src/mainboard/purism/librem_skl/devicetree.cb
+++ b/src/mainboard/purism/librem_skl/devicetree.cb
@@ -143,12 +143,8 @@ chip soc/intel/skylake
 				[2] = 1,
 			}"
 		end
-		device ref pcie_rp5	on
-			register "PcieRpEnable[4]" = "true"
-		end
-		device ref pcie_rp9	on
-			register "PcieRpEnable[8]" = "true"
-		end
+		device ref pcie_rp5	on  end
+		device ref pcie_rp9	on  end
 		device ref lpc_espi	on
 			# EC/KBC requires continuous mode
 			register "serirq_mode" = "SERIRQ_CONTINUOUS"
diff --git a/src/mainboard/razer/blade_stealth_kbl/devicetree.cb b/src/mainboard/razer/blade_stealth_kbl/devicetree.cb
index 637427adb5..55888fa02e 100644
--- a/src/mainboard/razer/blade_stealth_kbl/devicetree.cb
+++ b/src/mainboard/razer/blade_stealth_kbl/devicetree.cb
@@ -157,16 +157,13 @@ chip soc/intel/skylake
 		device ref uart2	on  end
 		device ref pcie_rp1	on  end
 		device ref pcie_rp3	on
-			register "PcieRpEnable[2]" = "true"
 			register "PcieRpLtrEnable[2]" = "true"
 		end
 		device ref pcie_rp5	on
-			register "PcieRpEnable[4]" = "true"
 			register "PcieRpLtrEnable[4]" = "true"
 			register "PcieRpHotPlug[4]" = "1"
 		end
 		device ref pcie_rp9	on
-			register "PcieRpEnable[8]" = "true"
 			register "PcieRpLtrEnable[8]" = "true"
 		end
 		device ref lpc_espi	on
diff --git a/src/mainboard/starlabs/starbook/variants/kbl/devicetree.cb b/src/mainboard/starlabs/starbook/variants/kbl/devicetree.cb
index a9ac9c1554..0f1c922acd 100644
--- a/src/mainboard/starlabs/starbook/variants/kbl/devicetree.cb
+++ b/src/mainboard/starlabs/starbook/variants/kbl/devicetree.cb
@@ -89,7 +89,6 @@ chip soc/intel/skylake
 		end
 		device ref uart2	on  end
 		device ref pcie_rp6	on
-			register "PcieRpEnable[5]"		= "1"
 			register "PcieRpClkReqSupport[5]"	= "1"
 			register "PcieRpClkReqNumber[5]"	= "4"
 			register "PcieRpClkSrcNumber[5]"	= "4"
@@ -101,7 +100,6 @@ chip soc/intel/skylake
 			end
 		end
 		device ref pcie_rp9	on
-			register "PcieRpEnable[8]"		= "1"
 			register "PcieRpClkReqSupport[8]"	= "1"
 			register "PcieRpClkReqNumber[8]"	= "0"
 			register "PcieRpClkSrcNumber[8]"	= "0"
diff --git a/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-f/overridetree.cb b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-f/overridetree.cb
index 15d217b2a5..0e431dc548 100644
--- a/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-f/overridetree.cb
+++ b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-f/overridetree.cb
@@ -49,34 +49,27 @@ chip soc/intel/skylake
 		end
 		device ref igpu on end
 		device ref pcie_rp1 on
-			register "PcieRpEnable[0]" = "true"
 			device pci 00.0 on end	# GbE
 		end
 		device ref pcie_rp2 on
-			register "PcieRpEnable[1]" = "true"
 			device pci 00.0 on end	# GbE
 		end
 		device ref pcie_rp3 on
-			register "PcieRpEnable[2]" = "true"
 			device pci 00.0 on end	# GbE
 		end
 		device ref pcie_rp4 on
-			register "PcieRpEnable[3]" = "true"
 			device pci 00.0 on end	# GbE
 		end
 		device ref pcie_rp5 on
-			register "PcieRpEnable[4]" = "true"
 			smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M.2 2280" "SlotDataBusWidth2X"
 		end
 		device ref pcie_rp7 on
-			register "PcieRpEnable[6]" = "true"
 			device pci 00.0 on	# Aspeed PCI Bridge
 				device pci 00.0 on end	# Aspeed 2400 VGA
 			end
 		end
 		device ref pcie_rp9 on
 			# Slot JPCIE1
-			register "PcieRpEnable[8]" = "true"
 			smbios_slot_desc "SlotTypePciExpressGen3X4" "SlotLengthLong" "PCH SLOT4 PCI-E 3.0 X4(IN X8)" "SlotDataBusWidth4X"
 		end
 		device ref lpc_espi on
diff --git a/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-tf/overridetree.cb b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-tf/overridetree.cb
index 14dbb0fe84..7b38e10e6c 100644
--- a/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-tf/overridetree.cb
+++ b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-tf/overridetree.cb
@@ -41,12 +41,10 @@ chip soc/intel/skylake
 		device ref peg0 on end	# unused
 		device ref peg1 on
 			# Slot JPCIE1
-			register "PcieRpEnable[0]" = "true"
 			smbios_slot_desc "SlotTypePciExpressGen3X8" "SlotLengthShort" "CPU SLOT6 PCI-E 3.0 X8" "SlotDataBusWidth4X"
 		end
 		device ref pcie_rp1 on
 			# Slot JPCIE1
-			register "PcieRpEnable[2]" = "true"
 			smbios_slot_desc "SlotTypePciExpressGen3X4" "SlotLengthLong" "PCH SLOT4 PCI-E 3.0 X2(IN X4)" "SlotDataBusWidth2X"
 		end
 		device ref pcie_rp3 on
@@ -55,12 +53,10 @@ chip soc/intel/skylake
 			end
 		end
 		device ref pcie_rp5 on
-			register "PcieRpEnable[4]" = "true"
 			device pci 00.0 on end	# 10GbE
 			device pci 00.1 on end	# 10GbE
 		end
 		device ref pcie_rp9 on
-			register "PcieRpEnable[8]" = "true"
 			smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M.2 2280" "SlotDataBusWidth4X"
 		end
 		device ref lpc_espi on
diff --git a/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/overridetree.cb b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/overridetree.cb
index d7505ef261..858297d6f1 100644
--- a/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/overridetree.cb
+++ b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/overridetree.cb
@@ -44,20 +44,17 @@ chip soc/intel/skylake
 		end
 		device ref pcie_rp1 on
 			# Slot JPCIE4
-			register "PcieRpEnable[0]" = "true"
 			register "PcieRpLtrEnable[0]" = "true"
 			register "PcieRpAdvancedErrorReporting[0]" = "1"
 			smbios_slot_desc "SlotTypePciExpressGen3X8" "SlotLengthShort" "PCH SLOT4 PCI-E 3.0 X4(IN X8)" "SlotDataBusWidth4X"
 		end
 		device ref pcie_rp5 on
 			# Slot JPCIE5
-			register "PcieRpEnable[4]" = "true"
 			register "PcieRpLtrEnable[4]" = "true"
 			register "PcieRpAdvancedErrorReporting[4]" = "1"
 			smbios_slot_desc "SlotTypePciExpressGen3X8" "SlotLengthShort" "PCH SLOT5 PCI-E 3.0 X4(IN X8)" "SlotDataBusWidth4X"
 		end
 		device ref pcie_rp9 on
-			register "PcieRpEnable[8]" = "true"
 			register "PcieRpLtrEnable[8]" = "true"
 			register "PcieRpAdvancedErrorReporting[8]" = "1"
 			device pci 00.0 on	# GbE 1
@@ -65,7 +62,6 @@ chip soc/intel/skylake
 			end
 		end
 		device ref pcie_rp10 on
-			register "PcieRpEnable[9]" = "true"
 			register "PcieRpLtrEnable[9]" = "true"
 			register "PcieRpAdvancedErrorReporting[9]" = "1"
 			device pci 00.0 on	# GbE 2
@@ -73,7 +69,6 @@ chip soc/intel/skylake
 			end
 		end
 		device ref pcie_rp11 on
-			register "PcieRpEnable[10]" = "true"
 			register "PcieRpLtrEnable[10]" = "true"
 			register "PcieRpAdvancedErrorReporting[10]" = "1"
 			device pci 00.0 on	# Aspeed PCI Bridge
diff --git a/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssw-f/overridetree.cb b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssw-f/overridetree.cb
index eec01fb73d..698cde3163 100644
--- a/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssw-f/overridetree.cb
+++ b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssw-f/overridetree.cb
@@ -45,24 +45,19 @@ chip soc/intel/skylake
 			smbios_slot_desc "SlotTypePciExpressGen3X16" "SlotLengthLong" "CPU SLOT1 PCI-E 3.0 X16" "SlotDataBusWidth16X"
 		end
 		device ref pcie_rp1 on
-			register "PcieRpEnable[0]" = "true"
 			device pci 00.0 on end	# GbE
 		end
 		device ref pcie_rp2 on
-			register "PcieRpEnable[1]" = "true"
 			device pci 00.0 on end	# GbE
 		end
 		device ref pcie_rp5 on
-			register "PcieRpEnable[4]" = "true"
 			smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M.2 2280" "SlotDataBusWidth4X"
 		end
 		device ref pcie_rp9 on
 			# Slot JSXB2
-			register "PcieRpEnable[8]" = "true"
 			smbios_slot_desc "SlotTypePciExpressGen3X4" "SlotLengthShort" "PCH SLOT2 PCI-E 3.0 X4(IN X8)" "SlotDataBusWidth4X"
 		end
 		device ref pcie_rp13 on
-			register "PcieRpEnable[12]" = "true"
 			device pci 00.0 on	# Aspeed PCI Bridge
 				device pci 00.0 on end	# Aspeed 2400 VGA
 			end
diff --git a/src/mainboard/system76/kbl-u/devicetree.cb b/src/mainboard/system76/kbl-u/devicetree.cb
index 10a5750ecc..4f3e148944 100644
--- a/src/mainboard/system76/kbl-u/devicetree.cb
+++ b/src/mainboard/system76/kbl-u/devicetree.cb
@@ -133,7 +133,6 @@ chip soc/intel/skylake
 		end
 		device ref pcie_rp1 on
 			# Root port #1 x4 (TBT)
-			register "PcieRpEnable[0]" = "true"
 			register "PcieRpClkReqSupport[0]" = "1"
 			register "PcieRpClkReqNumber[0]" = "4"
 			register "PcieRpClkSrcNumber[0]" = "4"
@@ -143,7 +142,6 @@ chip soc/intel/skylake
 		end
 		device ref pcie_rp5 on
 			# Root port #5 x1 (LAN)
-			register "PcieRpEnable[4]" = "true"
 			register "PcieRpClkReqSupport[4]" = "1"
 			register "PcieRpClkReqNumber[4]" = "3"
 			register "PcieRpClkSrcNumber[4]" = "3"
@@ -152,7 +150,6 @@ chip soc/intel/skylake
 		end
 		device ref pcie_rp6 on
 			# Root port #6 x1 (WLAN)
-			register "PcieRpEnable[5]" = "true"
 			register "PcieRpClkReqSupport[5]" = "1"
 			register "PcieRpClkReqNumber[5]" = "2"
 			register "PcieRpClkSrcNumber[5]" = "2"
@@ -161,7 +158,6 @@ chip soc/intel/skylake
 		end
 		device ref pcie_rp9 on
 			# Root port #9 x4 (NVMe)
-			register "PcieRpEnable[8]" = "true"
 			register "PcieRpClkReqSupport[8]" = "1"
 			register "PcieRpClkReqNumber[8]" = "5"
 			register "PcieRpClkSrcNumber[8]" = "5"
diff --git a/src/soc/intel/skylake/Makefile.mk b/src/soc/intel/skylake/Makefile.mk
index 6b082ed29e..04ba96b7dd 100644
--- a/src/soc/intel/skylake/Makefile.mk
+++ b/src/soc/intel/skylake/Makefile.mk
@@ -30,6 +30,7 @@ romstage-y += gpio.c
 romstage-y += gspi.c
 romstage-y += i2c.c
 romstage-y += me.c
+romstage-y += pcie_rp.c
 romstage-y += pmutil.c
 romstage-y += reset.c
 romstage-y += spi.c
@@ -50,6 +51,7 @@ ramstage-y += lockdown.c
 ramstage-y += lpc.c
 ramstage-y += me.c
 ramstage-y += p2sb.c
+ramstage-y += pcie_rp.c
 ramstage-y += pmc.c
 ramstage-y += pmutil.c
 ramstage-y += reset.c
diff --git a/src/soc/intel/skylake/chip.c b/src/soc/intel/skylake/chip.c
index d7364fdca2..715c008666 100644
--- a/src/soc/intel/skylake/chip.c
+++ b/src/soc/intel/skylake/chip.c
@@ -25,6 +25,7 @@
 #include <soc/itss.h>
 #include <soc/irq.h>
 #include <soc/pci_devs.h>
+#include <soc/pcie.h>
 #include <soc/ramstage.h>
 #include <soc/systemagent.h>
 #include <soc/usb.h>
@@ -34,22 +35,6 @@
 
 #include "chip.h"
 
-static const struct pcie_rp_group pch_lp_rp_groups[] = {
-	{ .slot = PCH_DEV_SLOT_PCIE,	.count = 8, .lcap_port_base = 1 },
-	{ .slot = PCH_DEV_SLOT_PCIE_1,	.count = 4, .lcap_port_base = 1 },
-	{ 0 }
-};
-
-static const struct pcie_rp_group pch_h_rp_groups[] = {
-	{ .slot = PCH_DEV_SLOT_PCIE,	.count = 8, .lcap_port_base = 1 },
-	{ .slot = PCH_DEV_SLOT_PCIE_1,	.count = 8, .lcap_port_base = 1 },
-	/* Sunrise Point PCH-H actually only has 4 ports in the
-	   third group. But that would require a runtime check
-	   and probing 4 non-existent ports shouldn't hurt. */
-	{ .slot = PCH_DEV_SLOT_PCIE_2,	.count = 8, .lcap_port_base = 1 },
-	{ 0 }
-};
-
 #if CONFIG(HAVE_ACPI_TABLES)
 const char *soc_acpi_name(const struct device *dev)
 {
@@ -181,10 +166,7 @@ void soc_init_pre_device(void *chip_info)
 	itss_restore_irq_polarities(GPIO_IRQ_START, GPIO_IRQ_END);
 
 	/* swap enabled PCI ports in device tree if needed */
-	if (CONFIG(SKYLAKE_SOC_PCH_H))
-		pcie_rp_update_devicetree(pch_h_rp_groups);
-	else
-		pcie_rp_update_devicetree(pch_lp_rp_groups);
+	pcie_rp_update_devicetree(get_pch_pcie_rp_table());
 }
 
 struct device_operations pci_domain_ops = {
diff --git a/src/soc/intel/skylake/chip.h b/src/soc/intel/skylake/chip.h
index 8d5a9d1414..d12c3eb218 100644
--- a/src/soc/intel/skylake/chip.h
+++ b/src/soc/intel/skylake/chip.h
@@ -170,13 +170,6 @@ struct soc_intel_skylake_config {
 		Peg2_x2,
 	} Peg2MaxLinkWidth;
 
-	/*
-	 * Enable/Disable Root Port
-	 * 0: Disable Root Port
-	 * 1: Enable Root Port
-	 */
-	bool PcieRpEnable[CONFIG_MAX_ROOT_PORTS];
-
 	/*
 	 * Enable/Disable Clk-req support for Root Port
 	 * 0: Disable Clk-Req
diff --git a/src/soc/intel/skylake/include/soc/pcie.h b/src/soc/intel/skylake/include/soc/pcie.h
new file mode 100644
index 0000000000..4c0713156f
--- /dev/null
+++ b/src/soc/intel/skylake/include/soc/pcie.h
@@ -0,0 +1,10 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef __SOC_SKYLAKE_PCIE_H__
+#define __SOC_SKYLAKE_PCIE_H__
+
+#include <intelblocks/pcie_rp.h>
+
+const struct pcie_rp_group *get_pch_pcie_rp_table(void);
+
+#endif /* __SOC_SKYLAKE_PCIE_H__ */
diff --git a/src/soc/intel/skylake/pcie_rp.c b/src/soc/intel/skylake/pcie_rp.c
new file mode 100644
index 0000000000..08e9c300dc
--- /dev/null
+++ b/src/soc/intel/skylake/pcie_rp.c
@@ -0,0 +1,29 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <intelblocks/pcie_rp.h>
+#include <soc/pci_devs.h>
+#include <soc/pcie.h>
+
+static const struct pcie_rp_group pch_lp_rp_groups[] = {
+	{ .slot = PCH_DEV_SLOT_PCIE,	.count = 8, .lcap_port_base = 1 },
+	{ .slot = PCH_DEV_SLOT_PCIE_1,	.count = 4, .lcap_port_base = 1 },
+	{ 0 }
+};
+
+static const struct pcie_rp_group pch_h_rp_groups[] = {
+	{ .slot = PCH_DEV_SLOT_PCIE,	.count = 8, .lcap_port_base = 1 },
+	{ .slot = PCH_DEV_SLOT_PCIE_1,	.count = 8, .lcap_port_base = 1 },
+	/* Sunrise Point PCH-H actually only has 4 ports in the
+	   third group. But that would require a runtime check
+	   and probing 4 non-existent ports shouldn't hurt. */
+	{ .slot = PCH_DEV_SLOT_PCIE_2,	.count = 8, .lcap_port_base = 1 },
+	{ 0 }
+};
+
+const struct pcie_rp_group *get_pch_pcie_rp_table(void)
+{
+	if (CONFIG(SKYLAKE_SOC_PCH_H))
+		return pch_h_rp_groups;
+
+	return pch_lp_rp_groups;
+}
diff --git a/src/soc/intel/skylake/romstage/fsp_params.c b/src/soc/intel/skylake/romstage/fsp_params.c
index bd3d086879..99bb5f1b6c 100644
--- a/src/soc/intel/skylake/romstage/fsp_params.c
+++ b/src/soc/intel/skylake/romstage/fsp_params.c
@@ -4,10 +4,12 @@
 #include <cpu/x86/msr.h>
 #include <fsp/util.h>
 #include <intelblocks/cpulib.h>
+#include <intelblocks/pcie_rp.h>
 #include <option.h>
 #include <soc/iomap.h>
 #include <soc/msr.h>
 #include <soc/pci_devs.h>
+#include <soc/pcie.h>
 #include <soc/romstage.h>
 #include <soc/soc_chip.h>
 #include <static.h>
@@ -75,9 +77,6 @@ static void soc_peg_init_params(FSP_M_CONFIG *m_cfg,
 static void soc_memory_init_params(FSP_M_CONFIG *m_cfg,
 			const struct soc_intel_skylake_config *config)
 {
-	int i;
-	uint32_t mask = 0;
-
 	m_cfg->MmioSize = 0x800; /* 2GB in MB */
 	m_cfg->TsegSize = CONFIG_SMM_TSEG_SIZE;
 	m_cfg->IedSize = CONFIG_IED_REGION_SIZE;
@@ -92,11 +91,7 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg,
 	m_cfg->DdrFreqLimit = 0;
 	m_cfg->VmxEnable = CONFIG(ENABLE_VMX);
 	m_cfg->PrmrrSize = get_valid_prmrr_size();
-	for (i = 0; i < ARRAY_SIZE(config->PcieRpEnable); i++) {
-		if (config->PcieRpEnable[i])
-			mask |= (1<<i);
-	}
-	m_cfg->PcieRpEnableMask = mask;
+	m_cfg->PcieRpEnableMask = pcie_rp_enable_mask(get_pch_pcie_rp_table());
 
 	cpu_flex_override(m_cfg);
 

From 60b414fc135a49751812b37442b8c166cc2ae199 Mon Sep 17 00:00:00 2001
From: Nico Huber <nico.h@gmx.de>
Date: Fri, 12 Jan 2024 16:22:19 +0100
Subject: [PATCH 0808/3886] soc/intel/cannonlake: Drop redundant PcieRpEnable

The PcieRpEnable option is redundant to our on/off setting in the
devicetrees. Let's use the common coreboot infrastructure instead.

Thanks to Nicholas for doing all the mainboard legwork!

Change-Id: I734262c8191bc217c721c0174d0f844755bc73a9
Signed-off-by: Nico Huber <nico.h@gmx.de>
Signed-off-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79918
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
---
 src/mainboard/asrock/imb-1222/devicetree.cb   |  4 --
 .../clevo/cml-u/variants/l140cu/devicetree.cb |  4 --
 .../drallion/variants/drallion/devicetree.cb  |  2 -
 .../hatch/variants/baseboard/devicetree.cb    |  2 -
 .../hatch/variants/helios/overridetree.cb     |  2 +-
 .../variants/helios_diskswap/overridetree.cb  |  8 ++-
 .../hatch/variants/kohaku/overridetree.cb     |  4 +-
 .../hatch/variants/mushu/overridetree.cb      |  4 +-
 .../hatch/variants/nightfury/overridetree.cb  |  4 +-
 .../hatch/variants/palkia/overridetree.cb     |  4 +-
 .../puff/variants/ambassador/overridetree.cb  |  2 -
 .../puff/variants/baseboard/devicetree.cb     |  2 -
 .../puff/variants/dooly/overridetree.cb       |  1 -
 .../puff/variants/duffy/overridetree.cb       |  2 -
 .../puff/variants/faffy/overridetree.cb       |  2 -
 .../puff/variants/genesis/overridetree.cb     | 13 -----
 .../puff/variants/kaisa/overridetree.cb       |  2 -
 .../puff/variants/moonbuggy/overridetree.cb   | 13 -----
 .../puff/variants/noibat/overridetree.cb      |  2 -
 .../google/puff/variants/puff/overridetree.cb |  2 -
 .../puff/variants/scout/overridetree.cb       | 13 -----
 .../puff/variants/wyvern/overridetree.cb      |  2 -
 .../sarien/variants/arcada/devicetree.cb      |  3 --
 .../sarien/variants/sarien/devicetree.cb      |  4 --
 .../variants/cfl_h/overridetree.cb            | 46 ++---------------
 .../variants/cfl_s/overridetree.cb            | 51 +++----------------
 .../variants/cfl_u/overridetree.cb            | 33 ++----------
 .../variants/cml_u/overridetree.cb            | 33 ++----------
 .../variants/whl_u/overridetree.cb            | 33 ++----------
 src/mainboard/lenovo/m920q/devicetree.cb      |  4 --
 src/mainboard/prodrive/hermes/devicetree.cb   | 10 ----
 .../protectli/vault_cml/devicetree.cb         |  9 ----
 .../variants/librem_14/overridetree.cb        |  4 --
 .../variants/librem_mini/overridetree.cb      |  3 --
 .../purism/librem_l1um_v2/devicetree.cb       |  5 --
 .../siemens/chili/variants/base/devicetree.cb |  4 --
 .../chili/variants/chili/devicetree.cb        |  6 ---
 .../starbook/variants/cml/devicetree.cb       |  1 -
 src/mainboard/system76/addw1/devicetree.cb    |  6 ---
 src/mainboard/system76/bonw14/devicetree.cb   |  8 ---
 .../cml-u/variants/darp6/overridetree.cb      |  4 --
 .../cml-u/variants/galp4/overridetree.cb      |  4 --
 .../cml-u/variants/lemp9/overridetree.cb      |  4 --
 src/mainboard/system76/gaze15/devicetree.cb   |  4 --
 src/mainboard/system76/oryp5/devicetree.cb    |  5 --
 src/mainboard/system76/oryp6/devicetree.cb    |  6 ---
 src/mainboard/system76/whl-u/devicetree.cb    |  4 --
 src/soc/intel/cannonlake/Makefile.mk          |  2 +
 src/soc/intel/cannonlake/chip.c               | 18 ++-----
 src/soc/intel/cannonlake/chip.h               |  1 -
 src/soc/intel/cannonlake/include/soc/pcie.h   | 10 ++++
 src/soc/intel/cannonlake/pcie_rp.c            | 26 ++++++++++
 .../intel/cannonlake/romstage/fsp_params.c    |  9 ++--
 53 files changed, 73 insertions(+), 381 deletions(-)
 create mode 100644 src/soc/intel/cannonlake/include/soc/pcie.h
 create mode 100644 src/soc/intel/cannonlake/pcie_rp.c

diff --git a/src/mainboard/asrock/imb-1222/devicetree.cb b/src/mainboard/asrock/imb-1222/devicetree.cb
index 216a60f8fb..0a84b106bb 100644
--- a/src/mainboard/asrock/imb-1222/devicetree.cb
+++ b/src/mainboard/asrock/imb-1222/devicetree.cb
@@ -223,7 +223,6 @@ chip soc/intel/cannonlake
 			}"
 		end
 		device ref pcie_rp17 on # M.2 Key-M 2242/2260/2280 slot for SSD (PCIEx4)
-			register "PcieRpEnable[16]" = "true"
 			register "PcieRpLtrEnable[16]" = "true"
 			register "PcieRpSlotImplemented[16]" = "1"
 			register "PcieClkSrcUsage[7]" = "16"
@@ -231,13 +230,11 @@ chip soc/intel/cannonlake
 			smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M.2/M 2242/2260/2280 (M2_KEYM1)" "SlotDataBusWidth4X"
 		end
 		device ref pcie_rp5 on # Intel Corporation Ethernet Controller I225-LM
-			register "PcieRpEnable[4]" = "true"
 			register "PcieRpLtrEnable[4]" = "true"
 			register "PcieClkSrcUsage[3]" = "4"
 			register "PcieClkSrcClkReq[3]" = "3"
 		end
 		device ref pcie_rp6 on # M.2 Key-E 2230 slot for Wireless M.2 Key-E (PCIe x1)
-			register "PcieRpEnable[5]" = "true"
 			register "PcieRpSlotImplemented[5]" = "1"
 			register "PcieRpLtrEnable[5]" = "true"
 			register "PcieClkSrcUsage[5]" = "5"
@@ -245,7 +242,6 @@ chip soc/intel/cannonlake
 			smbios_slot_desc "SlotTypeM2Socket1_SD" "SlotLengthOther" "M.2/E 2230 (M2_KEYE1)" "SlotDataBusWidth1X"
 		end
 		device ref pcie_rp7 on # M.2 Key-B 3042/3052 slot for 4G/5G modem (PCIe x1)
-			register "PcieRpEnable[6]" = "true"
 			register "PcieRpSlotImplemented[6]" = "1"
 			register "PcieRpLtrEnable[6]" = "true"
 			register "PcieClkSrcUsage[6]" = "6"
diff --git a/src/mainboard/clevo/cml-u/variants/l140cu/devicetree.cb b/src/mainboard/clevo/cml-u/variants/l140cu/devicetree.cb
index 749488fb6a..57b3b0f783 100644
--- a/src/mainboard/clevo/cml-u/variants/l140cu/devicetree.cb
+++ b/src/mainboard/clevo/cml-u/variants/l140cu/devicetree.cb
@@ -112,7 +112,6 @@ chip soc/intel/cannonlake
 		device ref uart2 on	end
 		device ref pcie_rp6 on
 			device pci 00.0 on end # x1 Card reader
-			register "PcieRpEnable[5]" = "true"
 			register "PcieRpLtrEnable[5]" = "true"
 			register "PcieClkSrcUsage[3]" = "5"
 			register "PcieClkSrcClkReq[3]" = "3"
@@ -121,7 +120,6 @@ chip soc/intel/cannonlake
 			chip drivers/wifi/generic
 				device pci 00.0 on end
 			end
-			register "PcieRpEnable[7]" = "true"
 			register "PcieRpLtrEnable[7]" = "true"
 			register "PcieClkSrcUsage[2]" = "7"
 			register "PcieClkSrcClkReq[2]" = "2"
@@ -129,7 +127,6 @@ chip soc/intel/cannonlake
 			smbios_slot_desc "SlotTypeM2Socket1_SD" "SlotLengthOther" "M.2/E 2230 (J_WLAN1)" "SlotDataBusWidth1X"
 		end
 		device ref pcie_rp9 on
-			register "PcieRpEnable[8]" = "true"
 			register "PcieRpLtrEnable[8]" = "true"
 			register "PcieClkSrcUsage[4]" = "8"
 			register "PcieClkSrcClkReq[4]" = "4"
@@ -137,7 +134,6 @@ chip soc/intel/cannonlake
 			smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M.2/M 2280 (J_SSD2)" "SlotDataBusWidth4X"
 		end
 		device ref pcie_rp13 on
-			register "PcieRpEnable[12]" = "true"
 			register "PcieRpLtrEnable[12]" = "true"
 			register "PcieClkSrcUsage[5]" = "12"
 			register "PcieClkSrcClkReq[5]" = "5"
diff --git a/src/mainboard/google/drallion/variants/drallion/devicetree.cb b/src/mainboard/google/drallion/variants/drallion/devicetree.cb
index 0f72b08418..0485639654 100644
--- a/src/mainboard/google/drallion/variants/drallion/devicetree.cb
+++ b/src/mainboard/google/drallion/variants/drallion/devicetree.cb
@@ -193,13 +193,11 @@ chip soc/intel/cannonlake
 	}"
 
 	# PCIe port 9 for Card Reader
-	register "PcieRpEnable[8]" = "true"
 	register "PcieRpLtrEnable[8]" = "true"
 	register "PcieClkSrcUsage[4]" = "8"
 	register "PcieClkSrcClkReq[4]" = "4"
 
 	# PCIe port 13 for M.2 2280 SSD
-	register "PcieRpEnable[12]" = "true"
 	register "PcieRpLtrEnable[12]" = "true"
 	register "PcieClkSrcUsage[2]" = "12"
 	register "PcieClkSrcClkReq[2]" = "2"
diff --git a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb
index da1c45f1a5..00b4d83d21 100644
--- a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb
+++ b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb
@@ -162,7 +162,6 @@ chip soc/intel/cannonlake
 	register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC_SKIP)"	# WWAN
 
 	# Enable Root port 9(x4) for NVMe.
-	register "PcieRpEnable[8]" = "true"
 	register "PcieRpLtrEnable[8]" = "true"
 	# RP 9 uses CLK SRC 1
 	register "PcieClkSrcUsage[1]" = "8"
@@ -170,7 +169,6 @@ chip soc/intel/cannonlake
 	register "PcieClkSrcClkReq[1]" = "1"
 
 	# PCIe port 14 for M.2 E-key WLAN
-	register "PcieRpEnable[13]" = "true"
 	register "PcieRpLtrEnable[13]" = "true"
 	# RP 14 uses CLK SRC 3
 	register "PcieClkSrcUsage[3]" = "13"
diff --git a/src/mainboard/google/hatch/variants/helios/overridetree.cb b/src/mainboard/google/hatch/variants/helios/overridetree.cb
index 09a95df637..c9f0caeb0d 100644
--- a/src/mainboard/google/hatch/variants/helios/overridetree.cb
+++ b/src/mainboard/google/hatch/variants/helios/overridetree.cb
@@ -20,7 +20,6 @@ chip soc/intel/cannonlake
 	}"
 
 	# No PCIe WiFi
-	register "PcieRpEnable[13]" = "false"
 
 	# Intel Common SoC Config
 	#+-------------------+---------------------------+
@@ -176,6 +175,7 @@ chip soc/intel/cannonlake
 				device i2c 3b on end
 			end
 		end #I2C #4
+		device ref pcie_rp14	off end # No PCIe Wifi
 		device ref gspi1	on
 			chip drivers/spi/acpi
 				register "name" = ""CRFP""
diff --git a/src/mainboard/google/hatch/variants/helios_diskswap/overridetree.cb b/src/mainboard/google/hatch/variants/helios_diskswap/overridetree.cb
index 7bc453db45..b4421b0ec6 100644
--- a/src/mainboard/google/hatch/variants/helios_diskswap/overridetree.cb
+++ b/src/mainboard/google/hatch/variants/helios_diskswap/overridetree.cb
@@ -20,7 +20,6 @@ chip soc/intel/cannonlake
 	}"
 
 	# Enable Root port 9(x2) for NVMe.
-	register "PcieRpEnable[8]" = "true"
 	register "PcieRpLtrEnable[8]" = "true"
 	# RP 9 uses CLK SRC 1
 	register "PcieClkSrcUsage[1]" = "8"
@@ -28,7 +27,6 @@ chip soc/intel/cannonlake
 	register "PcieClkSrcClkReq[1]" = "1"
 
 	# Enable Root port 11(x2) for NVMe.
-	register "PcieRpEnable[10]" = "true"
 	register "PcieRpLtrEnable[10]" = "true"
 	# RP 11 uses CLK SRC 2
 	register "PcieClkSrcUsage[2]" = "10"
@@ -36,7 +34,6 @@ chip soc/intel/cannonlake
 	register "PcieClkSrcClkReq[2]" = "1"
 
 	# No PCIe WiFi
-	register "PcieRpEnable[13]" = "false"
 
 	# Intel Common SoC Config
 	#+-------------------+---------------------------+
@@ -184,8 +181,9 @@ chip soc/intel/cannonlake
 				device i2c 3b on end
 			end
 		end #I2C #4
-		device ref pcie_rp9	on end # (x2 NVMe)
-		device ref pcie_rp11	on end # (x2 NVMe)
+		device ref pcie_rp9	on  end # (x2 NVMe)
+		device ref pcie_rp11	on  end # (x2 NVMe)
+		device ref pcie_rp14	off end # No PCIe Wifi
 		device ref gspi1	on
 			chip drivers/spi/acpi
 				register "name" = ""CRFP""
diff --git a/src/mainboard/google/hatch/variants/kohaku/overridetree.cb b/src/mainboard/google/hatch/variants/kohaku/overridetree.cb
index 656cd6b294..f00d9bb9d5 100644
--- a/src/mainboard/google/hatch/variants/kohaku/overridetree.cb
+++ b/src/mainboard/google/hatch/variants/kohaku/overridetree.cb
@@ -20,7 +20,6 @@ chip soc/intel/cannonlake
 	}"
 
 	# No PCIe WiFi
-	register "PcieRpEnable[13]" = "false"
 
 	# Enable DMIC1
 	register "PchHdaAudioLinkDmic1" = "1"
@@ -211,8 +210,7 @@ chip soc/intel/cannonlake
 				device i2c 0x1a on end
 			end
 		end
-		# No PCIe WiFi
-		device ref pcie_rp14	off end
+		device ref pcie_rp14	off end # No PCIe Wifi
 		device ref gspi1	on
 			chip drivers/spi/acpi
 				register "name" = ""CRFP""
diff --git a/src/mainboard/google/hatch/variants/mushu/overridetree.cb b/src/mainboard/google/hatch/variants/mushu/overridetree.cb
index 985c1afd0f..8766c9ec3a 100644
--- a/src/mainboard/google/hatch/variants/mushu/overridetree.cb
+++ b/src/mainboard/google/hatch/variants/mushu/overridetree.cb
@@ -71,14 +71,12 @@ chip soc/intel/cannonlake
 	}"
 
 	# PCIe port 7 for M.2 E-key WLAN
-	register "PcieRpEnable[6]" = "true"
 	register "PcieRpLtrEnable[6]" = "true"
 	# RP 7 uses CLK SRC 3
 	register "PcieClkSrcUsage[3]" = "6"
 	register "PcieClkSrcClkReq[3]" = "3"
 
 	# Enable Root port 13 (x4) for dGPU
-	register "PcieRpEnable[12]" = "true"
 	register "PcieRpLtrEnable[12]" = "true"
 	# RP 13 uses CLK SRC 5
 	register "PcieClkSrcUsage[5]" = "12"
@@ -178,6 +176,8 @@ chip soc/intel/cannonlake
 				device i2c 1a on end
 			end
 		end
+		device ref pcie_rp7	on  end
+		device ref pcie_rp13	on  end
 		device ref gspi1	on
 			chip drivers/spi/acpi
 				register "name" = ""CRFP""
diff --git a/src/mainboard/google/hatch/variants/nightfury/overridetree.cb b/src/mainboard/google/hatch/variants/nightfury/overridetree.cb
index bcdcd527e3..f020f468c4 100644
--- a/src/mainboard/google/hatch/variants/nightfury/overridetree.cb
+++ b/src/mainboard/google/hatch/variants/nightfury/overridetree.cb
@@ -20,7 +20,6 @@ chip soc/intel/cannonlake
 	}"
 
 	# No PCIe WiFi
-	register "PcieRpEnable[13]" = "false"
 
 	# Enable DMIC1
 	register "PchHdaAudioLinkDmic1" = "1"
@@ -219,8 +218,7 @@ chip soc/intel/cannonlake
 				device i2c 0x39 on end
 			end
 		end
-		# No PCIe WiFi
-		device ref pcie_rp14	off end
+		device ref pcie_rp14	off end # No PCIe Wifi
 		device ref emmc		on end
 		device ref hda		on
 			chip drivers/sof
diff --git a/src/mainboard/google/hatch/variants/palkia/overridetree.cb b/src/mainboard/google/hatch/variants/palkia/overridetree.cb
index 45c364b6dd..7fca6cc661 100644
--- a/src/mainboard/google/hatch/variants/palkia/overridetree.cb
+++ b/src/mainboard/google/hatch/variants/palkia/overridetree.cb
@@ -22,9 +22,6 @@ chip soc/intel/cannonlake
 	register "usb2_ports[2]" = "USB2_PORT_LONG(OC_SKIP)"    # SD CARD
 	register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # SD CARD
 
-	# No PCIe WiFi
-	register "PcieRpEnable[13]" = "false"
-
 	# Intel Common SoC Config
 	#+-------------------+---------------------------+
 	#| Field	     |	Value			 |
@@ -175,6 +172,7 @@ chip soc/intel/cannonlake
 				device i2c 39 on end
 			end
 		end
+		device ref pcie_rp14	off end # No PCIe Wifi
 		device ref hda		on
 			chip drivers/generic/max98357a
 				register "hid" = ""MX98357A""
diff --git a/src/mainboard/google/puff/variants/ambassador/overridetree.cb b/src/mainboard/google/puff/variants/ambassador/overridetree.cb
index 9c9880f385..e2fc98b2fa 100644
--- a/src/mainboard/google/puff/variants/ambassador/overridetree.cb
+++ b/src/mainboard/google/puff/variants/ambassador/overridetree.cb
@@ -184,10 +184,8 @@ chip soc/intel/cannonlake
 	}"
 
 	# PCIe port 7 for LAN
-	register "PcieRpEnable[6]" = "true"
 	register "PcieRpLtrEnable[6]" = "true"
 	# PCIe port 11 (x2) for NVMe hybrid storage devices
-	register "PcieRpEnable[10]" = "true"
 	register "PcieRpLtrEnable[10]" = "true"
 	# Uses CLK SRC 0
 	register "PcieClkSrcUsage[0]" = "6"
diff --git a/src/mainboard/google/puff/variants/baseboard/devicetree.cb b/src/mainboard/google/puff/variants/baseboard/devicetree.cb
index c5b01215a5..ca3817f463 100644
--- a/src/mainboard/google/puff/variants/baseboard/devicetree.cb
+++ b/src/mainboard/google/puff/variants/baseboard/devicetree.cb
@@ -162,7 +162,6 @@ chip soc/intel/cannonlake
 	register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC_SKIP)"	# WWAN
 
 	# Enable Root port 9(x4) for NVMe.
-	register "PcieRpEnable[8]" = "true"
 	register "PcieRpLtrEnable[8]" = "true"
 	# RP 9 uses CLK SRC 1
 	register "PcieClkSrcUsage[1]" = "8"
@@ -170,7 +169,6 @@ chip soc/intel/cannonlake
 	register "PcieClkSrcClkReq[1]" = "1"
 
 	# PCIe port 14 for M.2 E-key WLAN
-	register "PcieRpEnable[13]" = "true"
 	register "PcieRpLtrEnable[13]" = "true"
 	# RP 14 uses CLK SRC 3
 	register "PcieClkSrcUsage[3]" = "13"
diff --git a/src/mainboard/google/puff/variants/dooly/overridetree.cb b/src/mainboard/google/puff/variants/dooly/overridetree.cb
index a9a9b8eec8..4dd2865c88 100644
--- a/src/mainboard/google/puff/variants/dooly/overridetree.cb
+++ b/src/mainboard/google/puff/variants/dooly/overridetree.cb
@@ -173,7 +173,6 @@ chip soc/intel/cannonlake
 	}"
 
 	# PCIe port 11 (x2) for NVMe hybrid storage devices
-	register "PcieRpEnable[10]" = "true"
 	register "PcieRpLtrEnable[10]" = "true"
 	# Uses CLK SRC 0
 	register "PcieClkSrcUsage[0]" = "6"
diff --git a/src/mainboard/google/puff/variants/duffy/overridetree.cb b/src/mainboard/google/puff/variants/duffy/overridetree.cb
index 408a00bb07..ba06ff855d 100644
--- a/src/mainboard/google/puff/variants/duffy/overridetree.cb
+++ b/src/mainboard/google/puff/variants/duffy/overridetree.cb
@@ -245,10 +245,8 @@ chip soc/intel/cannonlake
 	}"
 
 	# PCIe port 7 for LAN
-	register "PcieRpEnable[6]" = "true"
 	register "PcieRpLtrEnable[6]" = "true"
 	# PCIe port 11 (x2) for NVMe hybrid storage devices
-	register "PcieRpEnable[10]" = "true"
 	register "PcieRpLtrEnable[10]" = "true"
 	# Uses CLK SRC 0
 	register "PcieClkSrcUsage[0]" = "6"
diff --git a/src/mainboard/google/puff/variants/faffy/overridetree.cb b/src/mainboard/google/puff/variants/faffy/overridetree.cb
index eac754e6dd..840a9fdab2 100644
--- a/src/mainboard/google/puff/variants/faffy/overridetree.cb
+++ b/src/mainboard/google/puff/variants/faffy/overridetree.cb
@@ -253,10 +253,8 @@ chip soc/intel/cannonlake
 	}"
 
 	# PCIe port 7 for LAN
-	register "PcieRpEnable[6]" = "true"
 	register "PcieRpLtrEnable[6]" = "true"
 	# PCIe port 11 (x2) for NVMe hybrid storage devices
-	register "PcieRpEnable[10]" = "true"
 	register "PcieRpLtrEnable[10]" = "true"
 	# Uses CLK SRC 0
 	register "PcieClkSrcUsage[0]" = "6"
diff --git a/src/mainboard/google/puff/variants/genesis/overridetree.cb b/src/mainboard/google/puff/variants/genesis/overridetree.cb
index 19e42ba595..d11d7efbb9 100644
--- a/src/mainboard/google/puff/variants/genesis/overridetree.cb
+++ b/src/mainboard/google/puff/variants/genesis/overridetree.cb
@@ -177,45 +177,38 @@ chip soc/intel/cannonlake
 	}"
 
 	# PCIe root port 7 for LAN
-	register "PcieRpEnable[6]" = "true"
 	register "PcieRpLtrEnable[6]" = "true"
 	# Uses CLK SRC 0
 	register "PcieClkSrcUsage[0]" = "6"
 	register "PcieClkSrcClkReq[0]" = "0"
 
 	# PCIe root port 8 for WLAN
-	register "PcieRpEnable[7]" = "true"
 	register "PcieRpLtrEnable[7]" = "true"
 	# Uses CLK SRC 5
 	register "PcieClkSrcUsage[5]" = "7"
 	register "PcieClkSrcClkReq[5]" = "5"
 
 	# PCIe root port 9 for SSD (PCIe Lanes 11, 12)
-	register "PcieRpEnable[8]" = "true"
 	register "PcieRpLtrEnable[8]" = "true"
 	# RP 9 uses CLK SRC 1
 	register "PcieClkSrcUsage[1]" = "8"
 	register "PcieClkSrcClkReq[1]" = "1"
 
 	# PCIe root port 10 disabled
-	register "PcieRpEnable[9]" = "false"
 
 	# PCIe root port 11 TPU1
-	register "PcieRpEnable[10]" = "true"
 	register "PcieRpLtrEnable[10]" = "true"
 	# RP 11 uses CLK SRC 1
 	register "PcieClkSrcUsage[4]" = "10"
 	register "PcieClkSrcClkReq[4]" = "4"
 
 	# PCIe root port 12 TPU0
-	register "PcieRpEnable[11]" = "true"
 	register "PcieRpLtrEnable[11]" = "true"
 	# RP 11 uses CLK SRC 1
 	register "PcieClkSrcUsage[2]" = "11"
 	register "PcieClkSrcClkReq[2]" = "2"
 
 	# PCIe port 13 for i350 NIC (x4)
-	register "PcieRpEnable[12]" = "true"
 	register "PcieRpLtrEnable[12]" = "true"
 	# RP 13 uses CLK SRC 3
 	register "PcieClkSrcUsage[3]" = "12"
@@ -224,9 +217,6 @@ chip soc/intel/cannonlake
 	# effectively "not connected"
 	register "PcieClkSrcClkReq[3]" = "0xFF"
 	# Disable the remaining ports 14-16
-	register "PcieRpEnable[13]" = "false"
-	register "PcieRpEnable[14]" = "false"
-	register "PcieRpEnable[15]" = "false"
 
 	# GPIO for SD card detect
 	register "sdcard_cd_gpio" = "vSD3_CD_B"
@@ -440,9 +430,6 @@ chip soc/intel/cannonlake
 			# X4 i350 NIC
 			register "PcieRpSlotImplemented[12]" = "0" # Built-in
 		end
-		device ref pcie_rp14	on end # non-root
-		device ref pcie_rp15	on end # non-root
-		device ref pcie_rp16	on end # non-root
 	end
 
 	# VR Settings Configuration for 4 Domains
diff --git a/src/mainboard/google/puff/variants/kaisa/overridetree.cb b/src/mainboard/google/puff/variants/kaisa/overridetree.cb
index f0bad9d941..1193d6bf68 100644
--- a/src/mainboard/google/puff/variants/kaisa/overridetree.cb
+++ b/src/mainboard/google/puff/variants/kaisa/overridetree.cb
@@ -245,10 +245,8 @@ chip soc/intel/cannonlake
 	}"
 
 	# PCIe port 7 for LAN
-	register "PcieRpEnable[6]" = "true"
 	register "PcieRpLtrEnable[6]" = "true"
 	# PCIe port 11 (x2) for NVMe hybrid storage devices
-	register "PcieRpEnable[10]" = "true"
 	register "PcieRpLtrEnable[10]" = "true"
 	# Uses CLK SRC 0
 	register "PcieClkSrcUsage[0]" = "6"
diff --git a/src/mainboard/google/puff/variants/moonbuggy/overridetree.cb b/src/mainboard/google/puff/variants/moonbuggy/overridetree.cb
index 9b6f020454..85a3c7fb16 100644
--- a/src/mainboard/google/puff/variants/moonbuggy/overridetree.cb
+++ b/src/mainboard/google/puff/variants/moonbuggy/overridetree.cb
@@ -177,45 +177,38 @@ chip soc/intel/cannonlake
 	}"
 
 	# PCIe root port 7 for LAN
-	register "PcieRpEnable[6]" = "true"
 	register "PcieRpLtrEnable[6]" = "true"
 	# Uses CLK SRC 0
 	register "PcieClkSrcUsage[0]" = "6"
 	register "PcieClkSrcClkReq[0]" = "0"
 
 	# PCIe root port 8 for WLAN
-	register "PcieRpEnable[7]" = "true"
 	register "PcieRpLtrEnable[7]" = "true"
 	# Uses CLK SRC 5
 	register "PcieClkSrcUsage[5]" = "7"
 	register "PcieClkSrcClkReq[5]" = "5"
 
 	# PCIe root port 9 for SSD (PCIe Lanes 11, 12)
-	register "PcieRpEnable[8]" = "true"
 	register "PcieRpLtrEnable[8]" = "true"
 	# RP 9 uses CLK SRC 1
 	register "PcieClkSrcUsage[1]" = "8"
 	register "PcieClkSrcClkReq[1]" = "1"
 
 	# PCIe root port 10 disabled
-	register "PcieRpEnable[9]" = "false"
 
 	# PCIe root port 11 TPU1
-	register "PcieRpEnable[10]" = "true"
 	register "PcieRpLtrEnable[10]" = "true"
 	# RP 11 uses CLK SRC 1
 	register "PcieClkSrcUsage[4]" = "10"
 	register "PcieClkSrcClkReq[4]" = "4"
 
 	# PCIe root port 12 TPU0
-	register "PcieRpEnable[11]" = "true"
 	register "PcieRpLtrEnable[11]" = "true"
 	# RP 11 uses CLK SRC 1
 	register "PcieClkSrcUsage[2]" = "11"
 	register "PcieClkSrcClkReq[2]" = "2"
 
 	# PCIe port 13 for i350 NIC (x4)
-	register "PcieRpEnable[12]" = "true"
 	register "PcieRpLtrEnable[12]" = "true"
 	# RP 13 uses CLK SRC 3
 	register "PcieClkSrcUsage[3]" = "12"
@@ -224,9 +217,6 @@ chip soc/intel/cannonlake
 	# effectively "not connected"
 	register "PcieClkSrcClkReq[3]" = "0xFF"
 	# Disable the remaining ports 14-16
-	register "PcieRpEnable[13]" = "false"
-	register "PcieRpEnable[14]" = "false"
-	register "PcieRpEnable[15]" = "false"
 
 	# GPIO for SD card detect
 	register "sdcard_cd_gpio" = "vSD3_CD_B"
@@ -442,9 +432,6 @@ chip soc/intel/cannonlake
 			# X4 i350 NIC
 			register "PcieRpSlotImplemented[12]" = "0" # Built-in
 		end
-		device ref pcie_rp14	on end # non-root
-		device ref pcie_rp15	on end # non-root
-		device ref pcie_rp16	on end # non-root
 		device ref uart1	on end
 	end
 
diff --git a/src/mainboard/google/puff/variants/noibat/overridetree.cb b/src/mainboard/google/puff/variants/noibat/overridetree.cb
index 61f73a08df..006f954a49 100644
--- a/src/mainboard/google/puff/variants/noibat/overridetree.cb
+++ b/src/mainboard/google/puff/variants/noibat/overridetree.cb
@@ -168,10 +168,8 @@ chip soc/intel/cannonlake
 	}"
 
 	# PCIe port 7 for LAN
-	register "PcieRpEnable[6]" = "true"
 	register "PcieRpLtrEnable[6]" = "true"
 	# PCIe port 11 (x2) for NVMe hybrid storage devices
-	register "PcieRpEnable[10]" = "true"
 	register "PcieRpLtrEnable[10]" = "true"
 	# Uses CLK SRC 0
 	register "PcieClkSrcUsage[0]" = "6"
diff --git a/src/mainboard/google/puff/variants/puff/overridetree.cb b/src/mainboard/google/puff/variants/puff/overridetree.cb
index 4638eeef36..43402ab192 100644
--- a/src/mainboard/google/puff/variants/puff/overridetree.cb
+++ b/src/mainboard/google/puff/variants/puff/overridetree.cb
@@ -178,10 +178,8 @@ chip soc/intel/cannonlake
 	}"
 
 	# PCIe port 7 for LAN
-	register "PcieRpEnable[6]" = "true"
 	register "PcieRpLtrEnable[6]" = "true"
 	# PCIe port 11 (x2) for NVMe hybrid storage devices
-	register "PcieRpEnable[10]" = "true"
 	register "PcieRpLtrEnable[10]" = "true"
 	# Uses CLK SRC 0
 	register "PcieClkSrcUsage[0]" = "6"
diff --git a/src/mainboard/google/puff/variants/scout/overridetree.cb b/src/mainboard/google/puff/variants/scout/overridetree.cb
index 66bf31fa8d..8c593d5b71 100644
--- a/src/mainboard/google/puff/variants/scout/overridetree.cb
+++ b/src/mainboard/google/puff/variants/scout/overridetree.cb
@@ -184,48 +184,37 @@ chip soc/intel/cannonlake
 	}"
 
 	# PCIe root port 7 for LAN
-	register "PcieRpEnable[6]" = "true"
 	register "PcieRpLtrEnable[6]" = "true"
 	# Uses CLK SRC 0
 	register "PcieClkSrcUsage[0]" = "6"
 	register "PcieClkSrcClkReq[0]" = "0"
 
 	# PCIe root port 8 for WLAN
-	register "PcieRpEnable[7]" = "true"
 	register "PcieRpLtrEnable[7]" = "true"
 	# Uses CLK SRC 3
 	register "PcieClkSrcUsage[3]" = "7"
 	register "PcieClkSrcClkReq[3]" = "3"
 
 	# PCIe root port 9 for SSD (PCIe Lanes 9-12)
-	register "PcieRpEnable[8]" = "true"
 	register "PcieRpLtrEnable[8]" = "true"
 	# RP 9 uses CLK SRC 1
 	register "PcieClkSrcUsage[1]" = "8"
 	register "PcieClkSrcClkReq[1]" = "1"
 
 	# PCIe root port 10-12 disabled
-	register "PcieRpEnable[9]" = "false"
-	register "PcieRpEnable[10]" = "false"
-	register "PcieRpEnable[11]" = "false"
 
 	# PCIe root port 13 TPU0
-	register "PcieRpEnable[12]" = "true"
 	register "PcieRpLtrEnable[12]" = "true"
 	# RP 13 uses CLK SRC 2
 	register "PcieClkSrcUsage[2]" = "12"
 	register "PcieClkSrcClkReq[2]" = "2"
 
 	# PCIe root port 14 TPU1
-	register "PcieRpEnable[13]" = "true"
 	register "PcieRpLtrEnable[13]" = "true"
 	# RP 14 uses CLK SRC 4
 	register "PcieClkSrcUsage[4]" = "13"
 	register "PcieClkSrcClkReq[4]" = "4"
 
-	register "PcieRpEnable[14]" = "false"
-	register "PcieRpEnable[15]" = "false"
-
 	# GPIO for SD card detect
 	register "sdcard_cd_gpio" = "vSD3_CD_B"
 
@@ -422,8 +411,6 @@ chip soc/intel/cannonlake
 			# TPU1
 			register "PcieRpSlotImplemented[13]" = "1" # M.2 Slot
 		end
-		device ref pcie_rp15	on end # non-root
-		device ref pcie_rp16	on end # non-root
 		device ref uart1	on end
 	end
 
diff --git a/src/mainboard/google/puff/variants/wyvern/overridetree.cb b/src/mainboard/google/puff/variants/wyvern/overridetree.cb
index a373bea730..e38a0c741e 100644
--- a/src/mainboard/google/puff/variants/wyvern/overridetree.cb
+++ b/src/mainboard/google/puff/variants/wyvern/overridetree.cb
@@ -179,10 +179,8 @@ chip soc/intel/cannonlake
 	}"
 
 	# PCIe port 7 for LAN
-	register "PcieRpEnable[6]" = "true"
 	register "PcieRpLtrEnable[6]" = "true"
 	# PCIe port 11 (x2) for NVMe hybrid storage devices
-	register "PcieRpEnable[10]" = "true"
 	register "PcieRpLtrEnable[10]" = "true"
 	# Uses CLK SRC 0
 	register "PcieClkSrcUsage[0]" = "6"
diff --git a/src/mainboard/google/sarien/variants/arcada/devicetree.cb b/src/mainboard/google/sarien/variants/arcada/devicetree.cb
index b52176338b..faec225f67 100644
--- a/src/mainboard/google/sarien/variants/arcada/devicetree.cb
+++ b/src/mainboard/google/sarien/variants/arcada/devicetree.cb
@@ -182,18 +182,15 @@ chip soc/intel/cannonlake
 	}"
 
 	# PCIe port 10 for M.2 2230 WLAN
-	register "PcieRpEnable[9]" = "true"
 	register "PcieClkSrcUsage[2]" = "9"
 	register "PcieClkSrcClkReq[2]" = "2"
 
 	# PCIe port 11 for card reader
-	register "PcieRpEnable[10]" = "true"
 	register "PcieRpLtrEnable[10]" = "true"
 	register "PcieClkSrcUsage[1]" = "10"
 	register "PcieClkSrcClkReq[1]" = "1"
 
 	# PCIe port 13 for M.2 2280 SSD
-	register "PcieRpEnable[12]" = "true"
 	register "PcieRpLtrEnable[12]" = "true"
 	register "PcieClkSrcUsage[4]" = "12"
 	register "PcieClkSrcClkReq[4]" = "4"
diff --git a/src/mainboard/google/sarien/variants/sarien/devicetree.cb b/src/mainboard/google/sarien/variants/sarien/devicetree.cb
index 7445bbc16b..9608e52dae 100644
--- a/src/mainboard/google/sarien/variants/sarien/devicetree.cb
+++ b/src/mainboard/google/sarien/variants/sarien/devicetree.cb
@@ -182,23 +182,19 @@ chip soc/intel/cannonlake
 	}"
 
 	# PCIe port 8 for Card Reader
-	register "PcieRpEnable[7]" = "true"
 	register "PcieRpLtrEnable[7]" = "true"
 	register "PcieClkSrcUsage[4]" = "7"
 	register "PcieClkSrcClkReq[4]" = "4"
 
 	# PCIe port 9 for LAN
-	register "PcieRpEnable[8]" = "true"
 	register "PcieClkSrcUsage[3]" = "PCIE_CLK_LAN"
 	register "PcieClkSrcClkReq[3]" = "3"
 
 	# PCIe port 10 for M.2 2230 WLAN
-	register "PcieRpEnable[9]" = "true"
 	register "PcieClkSrcUsage[1]" = "9"
 	register "PcieClkSrcClkReq[1]" = "1"
 
 	# PCIe port 13 for M.2 2280 SSD
-	register "PcieRpEnable[12]" = "true"
 	register "PcieRpLtrEnable[12]" = "true"
 	register "PcieClkSrcUsage[2]" = "12"
 	register "PcieClkSrcClkReq[2]" = "2"
diff --git a/src/mainboard/intel/coffeelake_rvp/variants/cfl_h/overridetree.cb b/src/mainboard/intel/coffeelake_rvp/variants/cfl_h/overridetree.cb
index 031974fdca..a10d271610 100644
--- a/src/mainboard/intel/coffeelake_rvp/variants/cfl_h/overridetree.cb
+++ b/src/mainboard/intel/coffeelake_rvp/variants/cfl_h/overridetree.cb
@@ -42,31 +42,6 @@ chip soc/intel/cannonlake
 	register "PchHdaDspEnable" = "false"
 	register "PchHdaAudioLinkHda" = "1"
 
-	register "PcieRpEnable[0]" = "true"
-	register "PcieRpEnable[1]" = "true"
-	register "PcieRpEnable[2]" = "true"
-	register "PcieRpEnable[3]" = "true"
-	register "PcieRpEnable[4]" = "true"
-	register "PcieRpEnable[5]" = "false"
-	register "PcieRpEnable[6]" = "false"
-	register "PcieRpEnable[7]" = "false"
-	register "PcieRpEnable[8]" = "true"
-	register "PcieRpEnable[9]" = "true"
-	register "PcieRpEnable[10]" = "true"
-	register "PcieRpEnable[11]" = "true"
-	register "PcieRpEnable[12]" = "false"
-	register "PcieRpEnable[13]" = "false"
-	register "PcieRpEnable[14]" = "false"
-	register "PcieRpEnable[15]" = "false"
-	register "PcieRpEnable[16]" = "false"
-	register "PcieRpEnable[17]" = "false"
-	register "PcieRpEnable[18]" = "false"
-	register "PcieRpEnable[19]" = "false"
-	register "PcieRpEnable[20]" = "false"
-	register "PcieRpEnable[21]" = "false"
-	register "PcieRpEnable[22]" = "false"
-	register "PcieRpEnable[23]" = "false"
-
 	register "PcieClkSrcUsage[0]" = "1"
 	register "PcieClkSrcUsage[1]" = "8"
 	register "PcieClkSrcUsage[2]" = "PCIE_CLK_NOTUSED"
@@ -95,30 +70,15 @@ chip soc/intel/cannonlake
 		device pci 19.1 off end # I2C #5 (Not available on PCH-H)
 		device pci 19.2 on  end # UART #2
 		device pci 1a.0 on  end # eMMC
-		device pci 1c.0 on	# PCI Express Port 1 x4 SLOT1
+		device ref pcie_rp1 on	# x4 SLOT1
 			register "PcieRpSlotImplemented[0]" = "1"
 		end
-		device pci 1c.4 on	# PCI Express Port 5 x1 SLOT2/LAN
+		device ref pcie_rp5 on	# x1 SLOT2/LAN
 			register "PcieRpSlotImplemented[4]" = "1"
 		end
-		device pci 1c.5 off end # PCI Express Port 6
-		device pci 1c.6 off end # PCI Express Port 7
-		device pci 1c.7 off end # PCI Express Port 8
-		device pci 1d.0 on	# PCI Express Port 9
+		device ref pcie_rp9 on
 			register "PcieRpSlotImplemented[8]" = "1"
 		end
-		device pci 1d.4 off end # PCI Express Port 13
-		device pci 1d.5 off end # PCI Express Port 14
-		device pci 1d.6 off end # PCI Express Port 15
-		device pci 1d.7 off end # PCI Express Port 16
-		device pci 1b.0 off end # PCI Express Port 17
-		device pci 1b.1 off end # PCI Express Port 18
-		device pci 1b.2 off end # PCI Express Port 19
-		device pci 1b.3 off end # PCI Express Port 20
-		device pci 1b.4 off end # PCI Express Port 21
-		device pci 1b.5 off end # PCI Express Port 22
-		device pci 1b.6 off end # PCI Express Port 23
-		device pci 1b.7 off end # PCI Express Port 24
 		device pci 1e.1 off end # UART #1
 		device pci 1e.2 off end # GSPI #0
 		device pci 1e.3 off end # GSPI #1
diff --git a/src/mainboard/intel/coffeelake_rvp/variants/cfl_s/overridetree.cb b/src/mainboard/intel/coffeelake_rvp/variants/cfl_s/overridetree.cb
index 3f1820e3e0..c8c443486f 100644
--- a/src/mainboard/intel/coffeelake_rvp/variants/cfl_s/overridetree.cb
+++ b/src/mainboard/intel/coffeelake_rvp/variants/cfl_s/overridetree.cb
@@ -40,31 +40,6 @@ chip soc/intel/cannonlake
 	register "PchHdaDspEnable" = "false"
 	register "PchHdaAudioLinkHda" = "1"
 
-	register "PcieRpEnable[0]" = "true"
-	register "PcieRpEnable[1]" = "true"
-	register "PcieRpEnable[2]" = "true"
-	register "PcieRpEnable[3]" = "true"
-	register "PcieRpEnable[4]" = "true"
-	register "PcieRpEnable[5]" = "false"
-	register "PcieRpEnable[6]" = "false"
-	register "PcieRpEnable[7]" = "false"
-	register "PcieRpEnable[8]" = "true"
-	register "PcieRpEnable[9]" = "false"
-	register "PcieRpEnable[10]" = "false"
-	register "PcieRpEnable[11]" = "false"
-	register "PcieRpEnable[12]" = "false"
-	register "PcieRpEnable[13]" = "false"
-	register "PcieRpEnable[14]" = "false"
-	register "PcieRpEnable[15]" = "false"
-	register "PcieRpEnable[16]" = "true"
-	register "PcieRpEnable[17]" = "true"
-	register "PcieRpEnable[18]" = "true"
-	register "PcieRpEnable[19]" = "true"
-	register "PcieRpEnable[20]" = "true"
-	register "PcieRpEnable[21]" = "true"
-	register "PcieRpEnable[22]" = "true"
-	register "PcieRpEnable[23]" = "true"
-
 	register "PcieClkSrcUsage[0]" = "PCIE_CLK_NOTUSED"
 	register "PcieClkSrcUsage[1]" = "8"
 	register "PcieClkSrcUsage[2]" = "PCIE_CLK_LAN"
@@ -103,38 +78,28 @@ chip soc/intel/cannonlake
 		device pci 19.1 off end # I2C #5 (Not available on PCH-H)
 		device pci 19.2 on  end # UART #2
 		device pci 1a.0 on  end # eMMC
-		device pci 1c.0 on	# PCI Express Port 1
+		device ref pcie_rp1 on
 			register "PcieRpSlotImplemented[0]" = "1"
 		end
-		device pci 1c.4 on	# PCI Express Port 5
+		device ref pcie_rp5 on
 			register "PcieRpSlotImplemented[4]" = "1"
 		end
-		device pci 1c.5 off end # PCI Express Port 6
-		device pci 1c.6 off end # PCI Express Port 7
-		device pci 1c.7 off end # PCI Express Port 8
-		device pci 1d.0 on	# PCI Express Port 9 x4 SLOT 1
+		device ref pcie_rp9 on	# x4 SLOT 1
 			register "PcieRpSlotImplemented[8]" = "1"
 		end
-		device pci 1d.1 off end # PCI Express Port 10
-		device pci 1d.2 off end # PCI Express Port 11
-		device pci 1d.3 off end # PCI Express Port 12
-		device pci 1d.4 off end # PCI Express Port 13
-		device pci 1d.5 off end # PCI Express Port 14
-		device pci 1d.6 off end # PCI Express Port 15
-		device pci 1d.7 off end # PCI Express Port 16
-		device pci 1b.0 on	# PCI Express Port 17
+		device ref pcie_rp17 on
 			register "PcieRpSlotImplemented[16]" = "1"
 		end
-		device pci 1b.1 on	# PCI Express Port 18
+		device ref pcie_rp18 on
 			register "PcieRpSlotImplemented[17]" = "1"
 		end
-		device pci 1b.2 on	# PCI Express Port 19
+		device ref pcie_rp19 on
 			register "PcieRpSlotImplemented[18]" = "1"
 		end
-		device pci 1b.3 on	# PCI Express Port 20
+		device ref pcie_rp20 on
 			register "PcieRpSlotImplemented[19]" = "1"
 		end
-		device pci 1b.4 on	# PCI Express Port 21 X4 SLOT 2
+		device ref pcie_rp21 on	# x4 SLOT 2
 			register "PcieRpSlotImplemented[20]" = "1"
 		end
 		device pci 1e.1 off end # UART #1
diff --git a/src/mainboard/intel/coffeelake_rvp/variants/cfl_u/overridetree.cb b/src/mainboard/intel/coffeelake_rvp/variants/cfl_u/overridetree.cb
index 84ebda58fc..25d084ac16 100644
--- a/src/mainboard/intel/coffeelake_rvp/variants/cfl_u/overridetree.cb
+++ b/src/mainboard/intel/coffeelake_rvp/variants/cfl_u/overridetree.cb
@@ -3,23 +3,6 @@ chip soc/intel/cannonlake
 	register "PchHdaDspEnable" = "true"
 	register "PchHdaAudioLinkHda" = "1"
 
-	register "PcieRpEnable[0]" = "true"
-	register "PcieRpEnable[1]" = "true"
-	register "PcieRpEnable[2]" = "true"
-	register "PcieRpEnable[3]" = "true"
-	register "PcieRpEnable[4]" = "true"
-	register "PcieRpEnable[5]" = "false"
-	register "PcieRpEnable[6]" = "false"
-	register "PcieRpEnable[7]" = "false"
-	register "PcieRpEnable[8]" = "true"
-	register "PcieRpEnable[9]" = "false"
-	register "PcieRpEnable[10]" = "false"
-	register "PcieRpEnable[11]" = "false"
-	register "PcieRpEnable[12]" = "false"
-	register "PcieRpEnable[13]" = "false"
-	register "PcieRpEnable[14]" = "false"
-	register "PcieRpEnable[15]" = "false"
-
 	register "PcieClkSrcUsage[0]" = "1"
 	register "PcieClkSrcUsage[1]" = "8"
 	register "PcieClkSrcUsage[2]" = "PCIE_CLK_LAN"
@@ -80,25 +63,15 @@ chip soc/intel/cannonlake
 		device pci 19.1 off end # I2C #5
 		device pci 19.2 on  end # UART #2
 		device pci 1a.0 on  end # eMMC
-		device pci 1c.0 on	# PCI Express Port 1 x4 SLOT1
+		device ref pcie_rp1 on	# x4 SLOT1
 			register "PcieRpSlotImplemented[0]" = "1"
 		end
-		device pci 1c.4 on	# PCI Express Port 5 x1 SLOT2/LAN
+		device ref pcie_rp5 on	# x1 SLOT2/LAN
 			register "PcieRpSlotImplemented[4]" = "1"
 		end
-		device pci 1c.5 off end # PCI Express Port 6
-		device pci 1c.6 off end # PCI Express Port 7
-		device pci 1c.7 off end # PCI Express Port 8
-		device pci 1d.0 on	# PCI Express Port 9
+		device ref pcie_rp9 on
 			register "PcieRpSlotImplemented[8]" = "1"
 		end
-		device pci 1d.1 off end # PCI Express Port 10
-		device pci 1d.2 off end # PCI Express Port 11
-		device pci 1d.3 off end # PCI Express Port 12
-		device pci 1d.4 off end # PCI Express Port 13
-		device pci 1d.5 off end # PCI Express Port 14
-		device pci 1d.6 off end # PCI Express Port 15
-		device pci 1d.7 off end # PCI Express Port 16
 		device pci 1e.1 off end # UART #1
 		device pci 1e.2 off end # GSPI #0
 		device pci 1e.3 off end # GSPI #1
diff --git a/src/mainboard/intel/coffeelake_rvp/variants/cml_u/overridetree.cb b/src/mainboard/intel/coffeelake_rvp/variants/cml_u/overridetree.cb
index 846fea9c3d..1f3bf9074b 100644
--- a/src/mainboard/intel/coffeelake_rvp/variants/cml_u/overridetree.cb
+++ b/src/mainboard/intel/coffeelake_rvp/variants/cml_u/overridetree.cb
@@ -41,23 +41,6 @@ chip soc/intel/cannonlake
 	register "PchHdaDspEnable" = "true"
 	register "PchHdaAudioLinkHda" = "1"
 
-	register "PcieRpEnable[0]" = "true"
-	register "PcieRpEnable[1]" = "true"
-	register "PcieRpEnable[2]" = "true"
-	register "PcieRpEnable[3]" = "true"
-	register "PcieRpEnable[4]" = "true"
-	register "PcieRpEnable[5]" = "false"
-	register "PcieRpEnable[6]" = "false"
-	register "PcieRpEnable[7]" = "false"
-	register "PcieRpEnable[8]" = "true"
-	register "PcieRpEnable[9]" = "false"
-	register "PcieRpEnable[10]" = "false"
-	register "PcieRpEnable[11]" = "false"
-	register "PcieRpEnable[12]" = "false"
-	register "PcieRpEnable[13]" = "false"
-	register "PcieRpEnable[14]" = "false"
-	register "PcieRpEnable[15]" = "false"
-
 	register "PcieClkSrcUsage[0]" = "1"
 	register "PcieClkSrcUsage[1]" = "8"
 	register "PcieClkSrcUsage[2]" = "PCIE_CLK_LAN"
@@ -92,25 +75,15 @@ chip soc/intel/cannonlake
 		device pci 19.1 off end # I2C #5
 		device pci 19.2 on  end # UART #2
 		device pci 1a.0 on  end # eMMC
-		device pci 1c.0 on	# PCI Express Port 1 x4 SLOT1
+		device ref pcie_rp1 on	# x4 SLOT1
 			register "PcieRpSlotImplemented[0]" = "1"
 		end
-		device pci 1c.4 on	# PCI Express Port 5 x1 SLOT2/LAN
+		device ref pcie_rp5 on	# x1 SLOT2/LAN
 			register "PcieRpSlotImplemented[4]" = "1"
 		end
-		device pci 1c.5 off end # PCI Express Port 6
-		device pci 1c.6 off end # PCI Express Port 7
-		device pci 1c.7 off end # PCI Express Port 8
-		device pci 1d.0 on	# PCI Express Port 9
+		device ref pcie_rp9 on
 			register "PcieRpSlotImplemented[8]" = "1"
 		end
-		device pci 1d.1 off end # PCI Express Port 10
-		device pci 1d.2 off end # PCI Express Port 11
-		device pci 1d.3 off end # PCI Express Port 12
-		device pci 1d.4 off end # PCI Express Port 13
-		device pci 1d.5 off end # PCI Express Port 14
-		device pci 1d.6 off end # PCI Express Port 15
-		device pci 1d.7 off end # PCI Express Port 16
 		device pci 1e.1 off end # UART #1
 		device pci 1f.6 on  end # GbE
 	end
diff --git a/src/mainboard/intel/coffeelake_rvp/variants/whl_u/overridetree.cb b/src/mainboard/intel/coffeelake_rvp/variants/whl_u/overridetree.cb
index 89e59a469c..309082ed4d 100644
--- a/src/mainboard/intel/coffeelake_rvp/variants/whl_u/overridetree.cb
+++ b/src/mainboard/intel/coffeelake_rvp/variants/whl_u/overridetree.cb
@@ -26,23 +26,6 @@ chip soc/intel/cannonlake
 	register "PchHdaDspEnable" = "true"
 	register "PchHdaAudioLinkHda" = "1"
 
-	register "PcieRpEnable[0]" = "true"
-	register "PcieRpEnable[1]" = "true"
-	register "PcieRpEnable[2]" = "true"
-	register "PcieRpEnable[3]" = "true"
-	register "PcieRpEnable[4]" = "true"
-	register "PcieRpEnable[5]" = "false"
-	register "PcieRpEnable[6]" = "false"
-	register "PcieRpEnable[7]" = "false"
-	register "PcieRpEnable[8]" = "true"
-	register "PcieRpEnable[9]" = "false"
-	register "PcieRpEnable[10]" = "false"
-	register "PcieRpEnable[11]" = "false"
-	register "PcieRpEnable[12]" = "false"
-	register "PcieRpEnable[13]" = "false"
-	register "PcieRpEnable[14]" = "false"
-	register "PcieRpEnable[15]" = "false"
-
 	register "PcieClkSrcUsage[0]" = "1"
 	register "PcieClkSrcUsage[1]" = "8"
 	register "PcieClkSrcUsage[2]" = "PCIE_CLK_LAN"
@@ -76,25 +59,15 @@ chip soc/intel/cannonlake
 		device pci 19.1 off end # I2C #5
 		device pci 19.2 on  end # UART #2
 		device pci 1a.0 on  end # eMMC
-		device pci 1c.0 on	# PCI Express Port 1 x4 SLOT1
+		device ref pcie_rp1 on	# x4 SLOT1
 			register "PcieRpSlotImplemented[0]" = "1"
 		end
-		device pci 1c.4 on	# PCI Express Port 5 x1 SLOT2/LAN
+		device ref pcie_rp5 on	# x1 SLOT2/LAN
 			register "PcieRpSlotImplemented[4]" = "1"
 		end
-		device pci 1c.5 off end # PCI Express Port 6
-		device pci 1c.6 off end # PCI Express Port 7
-		device pci 1c.7 off end # PCI Express Port 8
-		device pci 1d.0 on	# PCI Express Port 9
+		device ref pcie_rp9 on
 			register "PcieRpSlotImplemented[8]" = "1"
 		end
-		device pci 1d.1 off end # PCI Express Port 10
-		device pci 1d.2 off end # PCI Express Port 11
-		device pci 1d.3 off end # PCI Express Port 12
-		device pci 1d.4 off end # PCI Express Port 13
-		device pci 1d.5 off end # PCI Express Port 14
-		device pci 1d.6 off end # PCI Express Port 15
-		device pci 1d.7 off end # PCI Express Port 16
 		device pci 1e.1 off end # UART #1
 		device pci 1f.6 on  end # GbE
 	end
diff --git a/src/mainboard/lenovo/m920q/devicetree.cb b/src/mainboard/lenovo/m920q/devicetree.cb
index 61fa868a76..87e11fff62 100644
--- a/src/mainboard/lenovo/m920q/devicetree.cb
+++ b/src/mainboard/lenovo/m920q/devicetree.cb
@@ -67,28 +67,24 @@ chip soc/intel/cannonlake
 		end
 
 		device ref pcie_rp6	on # WLAN
-			register "PcieRpEnable[5]"		= "1"
 			register "PcieRpSlotImplemented[5]"	= "1"
 			register "PcieClkSrcUsage[3]"		= "5"
 			register "PcieClkSrcClkReq[3]"		= "3"
 		end
 
 		device ref pcie_rp9	on # PCIe x4
-			register "PcieRpEnable[8]"		= "1"
 			register "PcieRpSlotImplemented[8]"	= "1"
 			register "PcieClkSrcUsage[2]"		= "8"
 			register "PcieClkSrcClkReq[2]"		= "2"
 		end
 
 		device ref pcie_rp17 on # M.2 SSD #2
-			register "PcieRpEnable[16]"		= "1"
 			register "PcieRpSlotImplemented[16]"	= "1"
 			register "PcieClkSrcUsage[10]"		= "16"
 			register "PcieClkSrcClkReq[10]"		= "10"
 		end
 
 		device ref pcie_rp21 on # M.2 SSD #1
-			register "PcieRpEnable[20]"		= "1"
 			register "PcieRpSlotImplemented[20]"	= "1"
 			register "PcieClkSrcUsage[4]"		= "20"
 			register "PcieClkSrcClkReq[4]"		= "4"
diff --git a/src/mainboard/prodrive/hermes/devicetree.cb b/src/mainboard/prodrive/hermes/devicetree.cb
index e9bd24a072..aaa8e53d9c 100644
--- a/src/mainboard/prodrive/hermes/devicetree.cb
+++ b/src/mainboard/prodrive/hermes/devicetree.cb
@@ -171,7 +171,6 @@ chip soc/intel/cannonlake
 		device ref uart2 hidden end # in ACPI mode
 		device ref pcie_rp21 on
 			smbios_slot_desc "SlotTypePciExpressGen3X16" "SlotLengthOther" "SLOT1" "SlotDataBusWidth4X"
-			register "PcieRpEnable[20]" = "true"
 			register "PcieRpLtrEnable[20]" = "true"
 			register "PcieRpSlotImplemented[20]" = "1"
 			register "PcieRpMaxPayload[20]" = "RpMaxPayload_256"
@@ -180,7 +179,6 @@ chip soc/intel/cannonlake
 		end
 		device ref pcie_rp1 on
 			smbios_slot_desc "SlotTypePciExpressGen3X16" "SlotLengthOther" "SLOT3" "SlotDataBusWidth4X"
-			register "PcieRpEnable[0]" = "true"
 			register "PcieRpLtrEnable[0]" = "true"
 			register "PcieRpSlotImplemented[0]" = "1"
 			register "PcieRpMaxPayload[0]" = "RpMaxPayload_256"
@@ -188,28 +186,24 @@ chip soc/intel/cannonlake
 			register "PcieRpAspm[0]" = "AspmDisabled"
 		end
 		device ref pcie_rp5 on	# PHY 3
-			register "PcieRpEnable[4]" = "true"
 			register "PcieRpLtrEnable[4]" = "true"
 			device pci 00.0 on
 				smbios_dev_info 3
 			end
 		end
 		device ref pcie_rp6 on	# PHY 4
-			register "PcieRpEnable[5]" = "true"
 			register "PcieRpLtrEnable[5]" = "true"
 			device pci 00.0 on
 				smbios_dev_info 4
 			end
 		end
 		device ref pcie_rp7 on	# PHY 2
-			register "PcieRpEnable[6]" = "true"
 			register "PcieRpLtrEnable[6]" = "true"
 			device pci 00.0 on
 				smbios_dev_info 2
 			end
 		end
 		device ref pcie_rp8 on	# PHY 1
-			register "PcieRpEnable[7]" = "true"
 			register "PcieRpLtrEnable[7]" = "true"
 			device pci 00.0 on
 				smbios_dev_info 1
@@ -217,12 +211,10 @@ chip soc/intel/cannonlake
 		end
 		device ref pcie_rp9 on
 			smbios_slot_desc "SlotTypePciExpressGen3X16" "SlotLengthOther" "M2 M" "SlotDataBusWidth4X"
-			register "PcieRpEnable[8]" = "true"
 			register "PcieRpLtrEnable[8]" = "true"
 			register "PcieRpSlotImplemented[8]" = "1"
 		end
 		device ref pcie_rp14 on	# PHY 0
-			register "PcieRpEnable[13]" = "true"
 			register "PcieRpLtrEnable[13]" = "true"
 			device pci 00.0 on
 				smbios_dev_info 0
@@ -232,13 +224,11 @@ chip soc/intel/cannonlake
 			device pci 00.0 on	# Aspeed PCI Bridge
 				device pci 00.0 on end  # Aspeed 2500 VGA
 			end
-			register "PcieRpEnable[14]" = "true"
 			register "PcieRpLtrEnable[14]" = "true"
 			register "PcieRpSlotImplemented[14]" = "1"
 		end
 		device ref pcie_rp16 on	# M.2 E/CNVi
 			# Disabled when CNVi is present
-			register "PcieRpEnable[15]" = "true"
 			register "PcieRpLtrEnable[15]" = "true"
 			register "PcieRpSlotImplemented[15]" = "1"
 		end
diff --git a/src/mainboard/protectli/vault_cml/devicetree.cb b/src/mainboard/protectli/vault_cml/devicetree.cb
index 7143aad827..2c8d25752e 100644
--- a/src/mainboard/protectli/vault_cml/devicetree.cb
+++ b/src/mainboard/protectli/vault_cml/devicetree.cb
@@ -52,15 +52,6 @@ chip soc/intel/cannonlake
 	register "SataPortsEnable[0]" = "1"
 	register "SataPortsEnable[2]" = "1"
 
-	register "PcieRpEnable[4]" = "true" # LAN1
-	register "PcieRpEnable[5]" = "true" # LAN2
-	register "PcieRpEnable[6]" = "true" # LAN3
-	register "PcieRpEnable[7]" = "true" # LAN4
-	register "PcieRpEnable[8]" = "true" # LAN5
-	register "PcieRpEnable[9]" = "true" # LAN6
-	register "PcieRpEnable[11]" = "true" # M.2 WiFi
-	register "PcieRpEnable[12]" = "true" # M.2 NVMe x4
-
 	# Enable Advanced Error Reporting for RP 5-10, 12, 13
 	register "PcieRpAdvancedErrorReporting[4]" = "1"
 	register "PcieRpAdvancedErrorReporting[5]" = "1"
diff --git a/src/mainboard/purism/librem_cnl/variants/librem_14/overridetree.cb b/src/mainboard/purism/librem_cnl/variants/librem_14/overridetree.cb
index e9a4d8856d..6bd2eb0f8f 100644
--- a/src/mainboard/purism/librem_cnl/variants/librem_14/overridetree.cb
+++ b/src/mainboard/purism/librem_cnl/variants/librem_14/overridetree.cb
@@ -125,7 +125,6 @@ chip soc/intel/cannonlake
 			register "SataPortsDevSlp[2]" = "1"
 		end
 		device ref pcie_rp7 on	# x1 M.2/E 2230 (WLAN)
-			register "PcieRpEnable[6]" = "true"
 			register "PcieRpSlotImplemented[6]" = "1"
 			register "PcieRpLtrEnable[6]" = "true"
 			register "PcieRpHotPlug[6]" = "1"
@@ -135,12 +134,10 @@ chip soc/intel/cannonlake
 		end
 		device ref pcie_rp8 on
 			device pci 00.0 on end # x1 (LAN)
-			register "PcieRpEnable[7]" = "true"
 			register "PcieClkSrcUsage[3]" = "7"
 			register "PcieClkSrcClkReq[3]" = "3"
 		end
 		device ref pcie_rp9 on	# x4 M.2/M 2280 (NVMe)
-			register "PcieRpEnable[8]" = "true"
 			register "PcieRpSlotImplemented[8]" = "1"
 			register "PcieRpLtrEnable[8]" = "true"
 			register "PcieClkSrcUsage[0]" = "8"
@@ -148,7 +145,6 @@ chip soc/intel/cannonlake
 			smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M.2/M 2280" "SlotDataBusWidth4X"
 		end
 		device ref pcie_rp13 on	# x4 M.2/M 2280 (NVMe)
-			register "PcieRpEnable[12]" = "true"
 			register "PcieRpSlotImplemented[12]" = "1"
 			register "PcieRpLtrEnable[12]" = "true"
 			register "PcieClkSrcUsage[1]" = "12"
diff --git a/src/mainboard/purism/librem_cnl/variants/librem_mini/overridetree.cb b/src/mainboard/purism/librem_cnl/variants/librem_mini/overridetree.cb
index f4455b7784..036a82e366 100644
--- a/src/mainboard/purism/librem_cnl/variants/librem_mini/overridetree.cb
+++ b/src/mainboard/purism/librem_cnl/variants/librem_mini/overridetree.cb
@@ -118,7 +118,6 @@ chip soc/intel/cannonlake
 		end
 		device ref pcie_rp8 on	# x1 M.2/E 2230 (WLAN)
 			register "PcieRpSlotImplemented[7]" = "1"
-			register "PcieRpEnable[7]" = "true"
 			register "PcieRpLtrEnable[7]" = "true"
 			# ClkSrcUsage must be set to free-run since SRCCLKREQ2 is NC
 			register "PcieClkSrcUsage[2]" = "0x80"
@@ -126,13 +125,11 @@ chip soc/intel/cannonlake
 		end
 		device ref pcie_rp10 on
 			device pci 00.0 on end # x1 (LAN)
-			register "PcieRpEnable[9]" = "true"
 			register "PcieClkSrcUsage[3]" = "9"
 			register "PcieClkSrcClkReq[3]" = "3"
 		end
 		device ref pcie_rp13 on	# x4 M.2/M 2280 (NVMe)
 			register "PcieRpSlotImplemented[12]" = "1"
-			register "PcieRpEnable[12]" = "true"
 			register "PcieRpLtrEnable[12]" = "true"
 			register "PcieClkSrcUsage[1]" = "12"
 			register "PcieClkSrcClkReq[1]" = "1"
diff --git a/src/mainboard/purism/librem_l1um_v2/devicetree.cb b/src/mainboard/purism/librem_l1um_v2/devicetree.cb
index cd409933a9..e7c7fea41d 100644
--- a/src/mainboard/purism/librem_l1um_v2/devicetree.cb
+++ b/src/mainboard/purism/librem_l1um_v2/devicetree.cb
@@ -210,20 +210,17 @@ chip soc/intel/cannonlake
 		end
 		device ref pcie_rp21 on
 			register "PcieRpSlotImplemented[20]" = "1"
-			register "PcieRpEnable[20]" = "true"
 			register "PcieRpLtrEnable[20]" = "true"
 			register "PcieClkSrcUsage[10]" = "20"
 			smbios_slot_desc "SlotTypePciExpressGen3X4" "SlotLengthOther" "PCIE5" "SlotDataBusWidth4X"
 		end
 		device ref pcie_rp1 on
 			register "PcieRpSlotImplemented[0]" = "1"
-			register "PcieRpEnable[0]" = "true"
 			register "PcieRpLtrEnable[0]" = "true"
 			register "PcieClkSrcUsage[1]" = "0x80"
 			smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M2_1" "SlotDataBusWidth4X"
 		end
 		device ref pcie_rp9 on	# GbE #1
-			register "PcieRpEnable[8]" = "true"
 			register "PcieRpLtrEnable[8]" = "true"
 			register "PcieClkSrcUsage[14]" = "8"
 			# Type indexes are needed for systemd to use "onboard" names by default
@@ -236,12 +233,10 @@ chip soc/intel/cannonlake
 			end
 		end
 		device ref pcie_rp10 on	# BMC video
-			register "PcieRpEnable[9]" = "true"
 			register "PcieRpLtrEnable[9]" = "true"
 			register "PcieClkSrcUsage[8]" = "9"
 		end
 		device ref pcie_rp11 on	# GbE #2
-			register "PcieRpEnable[10]" = "true"
 			register "PcieRpLtrEnable[10]" = "true"
 			register "PcieClkSrcUsage[11]" = "10"
 			device pci 00.0 on
diff --git a/src/mainboard/siemens/chili/variants/base/devicetree.cb b/src/mainboard/siemens/chili/variants/base/devicetree.cb
index f217461645..fb39040008 100644
--- a/src/mainboard/siemens/chili/variants/base/devicetree.cb
+++ b/src/mainboard/siemens/chili/variants/base/devicetree.cb
@@ -38,25 +38,21 @@ chip soc/intel/cannonlake
 		end
 		device ref pcie_rp5		on
 			device pci 00.0 on end	# x1 i219
-			register "PcieRpEnable[4]" = "true"
 			register "PcieClkSrcUsage[4]" = "0x70"
 			register "PcieClkSrcClkReq[4]" = "4"
 			register "PcieRpSlotImplemented[4]" = "0"
 		end
 		device ref pcie_rp6		on
 			device pci 00.0 on end	# x1 i210
-			register "PcieRpEnable[5]" = "true"
 			register "PcieClkSrcUsage[5]" = "5"
 			register "PcieClkSrcClkReq[5]" = "5"
 			register "PcieRpSlotImplemented[5]" = "0"
 		end
 		device ref pcie_rp7		on
-			register "PcieRpEnable[6]" = "true"
 			register "PcieRpSlotImplemented[6]" = "1"
 			smbios_slot_desc "SlotTypeM2Socket1_SD" "SlotLengthOther" "M.2/E 2230" "SlotDataBusWidth1X"
 		end
 		device ref pcie_rp17		on
-			register "PcieRpEnable[16]" = "true"
 			register "PcieClkSrcUsage[7]" = "16"
 			register "PcieClkSrcClkReq[7]" = "7"
 			register "PcieRpSlotImplemented[16]" = "1"
diff --git a/src/mainboard/siemens/chili/variants/chili/devicetree.cb b/src/mainboard/siemens/chili/variants/chili/devicetree.cb
index 38358d824f..794db85bc0 100644
--- a/src/mainboard/siemens/chili/variants/chili/devicetree.cb
+++ b/src/mainboard/siemens/chili/variants/chili/devicetree.cb
@@ -81,39 +81,33 @@ chip soc/intel/cannonlake
 			end
 		end
 		device ref pcie_rp1		off
-			register "PcieRpEnable[0]" = "false" # Debug (x1)
 			register "PcieClkSrcUsage[2]" = "0"
 			register "PcieClkSrcClkReq[2]" = "2"
 		end
 		device ref pcie_rp5		on
-			register "PcieRpEnable[4]" = "true" # CORE (x1)
 			register "PcieClkSrcUsage[4]" = "4"
 			register "PcieClkSrcClkReq[4]" = "4"
 			register "PcieRpSlotImplemented[4]" = "1"
 		end
 		device ref pcie_rp6		on
 			device pci 00.0 on end	# i210 (x1)
-			register "PcieRpEnable[5]" = "true"
 			register "PcieClkSrcUsage[5]" = "5"
 			register "PcieClkSrcClkReq[5]" = "5"
 			register "PcieRpSlotImplemented[5]" = "0"
 		end
 		device ref pcie_rp7		on
 			device pci 00.0 on end	# VL805 Front Rack/UIB (x1)
-			register "PcieRpEnable[6]" = "true"
 			register "PcieClkSrcUsage[1]" = "6"
 			register "PcieClkSrcClkReq[1]" = "1"
 			register "PcieRpSlotImplemented[6]" = "0"
 		end
 		device ref pcie_rp8		on
 			device pci 00.0 on end	# VL805 Back MB (x1)
-			register "PcieRpEnable[7]" = "true"
 			register "PcieClkSrcUsage[0]" = "7"
 			register "PcieClkSrcClkReq[0]" = "0"
 			register "PcieRpSlotImplemented[7]" = "0"
 		end
 		device ref pcie_rp17		on
-			register "PcieRpEnable[16]" = "true" # NVMe (x4)
 			register "PcieClkSrcUsage[7]" = "16"
 			register "PcieClkSrcClkReq[7]" = "7"
 			register "PcieRpSlotImplemented[16]" = "1"
diff --git a/src/mainboard/starlabs/starbook/variants/cml/devicetree.cb b/src/mainboard/starlabs/starbook/variants/cml/devicetree.cb
index 7a659ce214..4d04df714f 100644
--- a/src/mainboard/starlabs/starbook/variants/cml/devicetree.cb
+++ b/src/mainboard/starlabs/starbook/variants/cml/devicetree.cb
@@ -163,7 +163,6 @@ chip soc/intel/cannonlake
 		device ref uart2 on  end
 		device ref pcie_rp9 on						# SSD x4
 			register "PcieRpSlotImplemented[8]"	= "1"
-			register "PcieRpEnable[8]"		= "1"
 			register "PcieRpLtrEnable[8]"		= "true"
 			register "PcieClkSrcUsage[1]"		= "0x08"
 			register "PcieClkSrcClkReq[1]"		= "1"
diff --git a/src/mainboard/system76/addw1/devicetree.cb b/src/mainboard/system76/addw1/devicetree.cb
index 850d485d2e..07e960c50d 100644
--- a/src/mainboard/system76/addw1/devicetree.cb
+++ b/src/mainboard/system76/addw1/devicetree.cb
@@ -98,7 +98,6 @@ chip soc/intel/cannonlake
 		end
 		device ref pcie_rp17	on
 			# PCI Express root port #17 x4, Clock 0 (Thunderbolt)
-			register "PcieRpEnable[16]" = "true"
 			register "PcieRpLtrEnable[16]" = "true"
 			register "PcieRpHotPlug[16]" = "1"
 			register "PcieClkSrcUsage[0]" = "16"
@@ -106,7 +105,6 @@ chip soc/intel/cannonlake
 		end
 		device ref pcie_rp21	on
 			# PCI Express root port #21 x4, Clock 10 (SSD2)
-			register "PcieRpEnable[20]" = "true"
 			register "PcieRpLtrEnable[20]" = "true"
 			register "PcieClkSrcUsage[10]" = "20"
 			register "PcieClkSrcClkReq[10]" = "10"
@@ -114,7 +112,6 @@ chip soc/intel/cannonlake
 		end
 		device ref pcie_rp9	on
 			# PCI Express root port #9 x4, Clock 9 (SSD1)
-			register "PcieRpEnable[8]" = "true"
 			register "PcieRpLtrEnable[8]" = "true"
 			register "PcieClkSrcUsage[9]" = "8"
 			register "PcieClkSrcClkReq[9]" = "9"
@@ -122,7 +119,6 @@ chip soc/intel/cannonlake
 		end
 		device ref pcie_rp14	on
 			# PCI Express root port #14 x1, Clock 5 (GLAN)
-			register "PcieRpEnable[13]" = "true"
 			register "PcieRpLtrEnable[13]" = "true"
 			register "PcieClkSrcUsage[5]" = "13"
 			register "PcieClkSrcClkReq[5]" = "5"
@@ -130,7 +126,6 @@ chip soc/intel/cannonlake
 		end
 		device ref pcie_rp15	on
 			# PCI Express root port #15 x1, Clock 7 (Card Reader)
-			register "PcieRpEnable[14]" = "true"
 			register "PcieRpLtrEnable[14]" = "true"
 			register "PcieClkSrcUsage[7]" = "14"
 			register "PcieClkSrcClkReq[7]" = "7"
@@ -138,7 +133,6 @@ chip soc/intel/cannonlake
 		end
 		device ref pcie_rp16	on
 			# PCI Express root port #16 x1, Clock 6 (WLAN)
-			register "PcieRpEnable[15]" = "true"
 			register "PcieRpLtrEnable[15]" = "true"
 			register "PcieClkSrcUsage[6]" = "15"
 			register "PcieClkSrcClkReq[6]" = "6"
diff --git a/src/mainboard/system76/bonw14/devicetree.cb b/src/mainboard/system76/bonw14/devicetree.cb
index 36a9b90285..f5493874f6 100644
--- a/src/mainboard/system76/bonw14/devicetree.cb
+++ b/src/mainboard/system76/bonw14/devicetree.cb
@@ -113,21 +113,18 @@ chip soc/intel/cannonlake
 		end
 		device ref pcie_rp17	on
 			# PCI Express root port #17 x4, Clock 14 (SSD2)
-			register "PcieRpEnable[16]" = "true"
 			register "PcieRpLtrEnable[16]" = "true"
 			register "PcieClkSrcUsage[14]" = "16"
 			register "PcieClkSrcClkReq[14]" = "14"
 		end
 		device ref pcie_rp21	on
 			# PCI Express root port #21 x4, Clock 15 (SSD3)
-			register "PcieRpEnable[20]" = "true"
 			register "PcieRpLtrEnable[20]" = "true"
 			register "PcieClkSrcUsage[15]" = "20"
 			register "PcieClkSrcClkReq[15]" = "15"
 		end
 		device ref pcie_rp1	on
 			# PCI Express root port #1 x4, Clock 6 (Thunderbolt)
-			register "PcieRpEnable[0]" = "true"
 			register "PcieRpLtrEnable[0]" = "true"
 			register "PcieRpHotPlug[0]" = "1"
 			register "PcieClkSrcUsage[6]" = "PCIE_CLK_RP0" # 0 is converted to PCIE_CLK_NOTUSED
@@ -135,35 +132,30 @@ chip soc/intel/cannonlake
 		end
 		device ref pcie_rp5	on
 			# PCI Express root port #5 x4, Clock 10 (USB 3.2)
-			register "PcieRpEnable[4]" = "true"
 			register "PcieRpLtrEnable[4]" = "true"
 			register "PcieClkSrcUsage[10]" = "4"
 			register "PcieClkSrcClkReq[10]" = "10"
 		end
 		device ref pcie_rp9	on
 			# PCI Express root port #9 x4, Clock 8 (SSD)
-			register "PcieRpEnable[8]" = "true"
 			register "PcieRpLtrEnable[8]" = "true"
 			register "PcieClkSrcUsage[8]" = "8"
 			register "PcieClkSrcClkReq[8]" = "8"
 		end
 		device ref pcie_rp13	on
 			# PCI Express root port #13 x1, Clock 0 (WLAN)
-			register "PcieRpEnable[12]" = "true"
 			register "PcieRpLtrEnable[12]" = "true"
 			register "PcieClkSrcUsage[0]" = "12"
 			register "PcieClkSrcClkReq[0]" = "0"
 		end
 		device ref pcie_rp14	on
 			# PCI Express root port #14 x1, Clock 1 (GLAN)
-			register "PcieRpEnable[13]" = "true"
 			register "PcieRpLtrEnable[13]" = "true"
 			register "PcieClkSrcUsage[1]" = "13"
 			register "PcieClkSrcClkReq[1]" = "1"
 		end
 		device ref pcie_rp15	on
 			# PCI Express root port #15 x1, Clock 4 (Card Reader)
-			register "PcieRpEnable[14]" = "true"
 			register "PcieRpLtrEnable[14]" = "true"
 			register "PcieClkSrcUsage[4]" = "14"
 			register "PcieClkSrcClkReq[4]" = "4"
diff --git a/src/mainboard/system76/cml-u/variants/darp6/overridetree.cb b/src/mainboard/system76/cml-u/variants/darp6/overridetree.cb
index 5e70ec0dd6..5b9a3bb060 100644
--- a/src/mainboard/system76/cml-u/variants/darp6/overridetree.cb
+++ b/src/mainboard/system76/cml-u/variants/darp6/overridetree.cb
@@ -40,7 +40,6 @@ chip soc/intel/cannonlake
 		end
 		device ref pcie_rp5	on
 			# PCI Express Root port #5 x4, Clock 4 (TBT)
-			register "PcieRpEnable[4]" = "true"
 			register "PcieRpLtrEnable[4]" = "true"
 			register "PcieRpHotPlug[4]" = "1"
 			register "PcieClkSrcUsage[4]" = "4"
@@ -48,21 +47,18 @@ chip soc/intel/cannonlake
 		end
 		device ref pcie_rp9	on
 			# PCI Express Root port #9 x1, Clock 3 (LAN)
-			register "PcieRpEnable[8]" = "true"
 			register "PcieRpLtrEnable[8]" = "true"
 			register "PcieClkSrcUsage[3]" = "8"
 			register "PcieClkSrcClkReq[3]" = "3"
 		end
 		device ref pcie_rp10	on
 			# PCI Express Root port #10 x1, Clock 2 (WLAN)
-			register "PcieRpEnable[9]" = "true"
 			register "PcieRpLtrEnable[9]" = "false"
 			register "PcieClkSrcUsage[2]" = "9"
 			register "PcieClkSrcClkReq[2]" = "2"
 		end
 		device ref pcie_rp13	on
 			# PCI Express Root port #13 x4, Clock 5 (NVMe)
-			register "PcieRpEnable[12]" = "true"
 			register "PcieRpLtrEnable[12]" = "true"
 			register "PcieClkSrcUsage[5]" = "12"
 			register "PcieClkSrcClkReq[5]" = "5"
diff --git a/src/mainboard/system76/cml-u/variants/galp4/overridetree.cb b/src/mainboard/system76/cml-u/variants/galp4/overridetree.cb
index fb902bbdb5..cc9c4d76c8 100644
--- a/src/mainboard/system76/cml-u/variants/galp4/overridetree.cb
+++ b/src/mainboard/system76/cml-u/variants/galp4/overridetree.cb
@@ -33,7 +33,6 @@ chip soc/intel/cannonlake
 		end
 		device ref pcie_rp5	on
 			# PCI Express Root port #5 x4, Clock 4 (TBT)
-			register "PcieRpEnable[4]" = "true"
 			register "PcieRpLtrEnable[4]" = "true"
 			register "PcieRpHotPlug[4]" = "1"
 			register "PcieClkSrcUsage[4]" = "4"
@@ -41,21 +40,18 @@ chip soc/intel/cannonlake
 		end
 		device ref pcie_rp9	on
 			# PCI Express Root port #9 x1, Clock 3 (LAN)
-			register "PcieRpEnable[8]" = "true"
 			register "PcieRpLtrEnable[8]" = "true"
 			register "PcieClkSrcUsage[3]" = "8"
 			register "PcieClkSrcClkReq[3]" = "3"
 		end
 		device ref pcie_rp10	on
 			# PCI Express Root port #10 x1, Clock 2 (WLAN)
-			register "PcieRpEnable[9]" = "true"
 			register "PcieRpLtrEnable[9]" = "false"
 			register "PcieClkSrcUsage[2]" = "9"
 			register "PcieClkSrcClkReq[2]" = "2"
 		end
 		device ref pcie_rp13	on
 			# PCI Express Root port #13 x4, Clock 5 (NVMe)
-			register "PcieRpEnable[12]" = "true"
 			register "PcieRpLtrEnable[12]" = "true"
 			register "PcieClkSrcUsage[5]" = "12"
 			register "PcieClkSrcClkReq[5]" = "5"
diff --git a/src/mainboard/system76/cml-u/variants/lemp9/overridetree.cb b/src/mainboard/system76/cml-u/variants/lemp9/overridetree.cb
index 2010b82ea7..4dfd3cc648 100644
--- a/src/mainboard/system76/cml-u/variants/lemp9/overridetree.cb
+++ b/src/mainboard/system76/cml-u/variants/lemp9/overridetree.cb
@@ -41,7 +41,6 @@ chip soc/intel/cannonlake
 		end
 		device ref pcie_rp6	on
 			device pci 00.0 on end # x1 Card reader
-			register "PcieRpEnable[5]" = "true"
 			register "PcieRpLtrEnable[5]" = "true"
 			register "PcieClkSrcUsage[3]" = "5"
 			register "PcieClkSrcClkReq[3]" = "3"
@@ -49,7 +48,6 @@ chip soc/intel/cannonlake
 		end
 		device ref pcie_rp8	on
 			device pci 00.0 on end # x1 M.2/E 2230 (J_WLAN1)
-			register "PcieRpEnable[7]" = "true"
 			register "PcieRpLtrEnable[7]" = "true"
 			register "PcieClkSrcUsage[2]" = "7"
 			register "PcieClkSrcClkReq[2]" = "2"
@@ -61,7 +59,6 @@ chip soc/intel/cannonlake
 		end
 		device ref pcie_rp9	on
 			device pci 00.0 on end # x4 M.2/M 2280 (J_SSD2)
-			register "PcieRpEnable[8]" = "true"
 			register "PcieRpLtrEnable[8]" = "true"
 			register "PcieClkSrcUsage[4]" = "8"
 			register "PcieClkSrcClkReq[4]" = "4"
@@ -70,7 +67,6 @@ chip soc/intel/cannonlake
 		end
 		device ref pcie_rp13	on
 			device pci 00.0 on end # x4 M.2/M 2280 (J_SSD1)
-			register "PcieRpEnable[12]" = "true"
 			register "PcieRpLtrEnable[12]" = "true"
 			register "PcieClkSrcUsage[5]" = "12"
 			register "PcieClkSrcClkReq[5]" = "5"
diff --git a/src/mainboard/system76/gaze15/devicetree.cb b/src/mainboard/system76/gaze15/devicetree.cb
index 1c5aed681c..cc76124695 100644
--- a/src/mainboard/system76/gaze15/devicetree.cb
+++ b/src/mainboard/system76/gaze15/devicetree.cb
@@ -96,7 +96,6 @@ chip soc/intel/cannonlake
 		device ref uart2	on	end
 		device ref pcie_rp21	on
 			# PCI Express root port #21 x4, Clock 11 (SSD2)
-			register "PcieRpEnable[20]" = "true"
 			register "PcieRpLtrEnable[20]" = "true"
 			register "PcieClkSrcUsage[11]" = "20"
 			register "PcieClkSrcClkReq[11]" = "11"
@@ -104,7 +103,6 @@ chip soc/intel/cannonlake
 		end
 		device ref pcie_rp9	on
 			# PCI Express root port #9 x4, Clock 10 (SSD)
-			register "PcieRpEnable[8]" = "true"
 			register "PcieRpLtrEnable[8]" = "true"
 			register "PcieClkSrcUsage[10]" = "8"
 			register "PcieClkSrcClkReq[10]" = "10"
@@ -112,7 +110,6 @@ chip soc/intel/cannonlake
 		end
 		device ref pcie_rp14	on
 			# PCI Express root port #14 x1, Clock 6 (WLAN)
-			register "PcieRpEnable[13]" = "true"
 			register "PcieRpLtrEnable[13]" = "true"
 			register "PcieClkSrcUsage[6]" = "13"
 			register "PcieClkSrcClkReq[6]" = "6"
@@ -120,7 +117,6 @@ chip soc/intel/cannonlake
 		end
 		device ref pcie_rp15	on
 			# PCI Express root port #15 x1, Clock 5 (LAN)
-			register "PcieRpEnable[14]" = "true"
 			register "PcieRpLtrEnable[14]" = "true"
 			register "PcieClkSrcUsage[5]" = "14"
 			register "PcieClkSrcClkReq[5]" = "5"
diff --git a/src/mainboard/system76/oryp5/devicetree.cb b/src/mainboard/system76/oryp5/devicetree.cb
index a465e5640e..e18ab9a397 100644
--- a/src/mainboard/system76/oryp5/devicetree.cb
+++ b/src/mainboard/system76/oryp5/devicetree.cb
@@ -109,35 +109,30 @@ chip soc/intel/cannonlake
 		device ref uart2	on	end
 		device ref pcie_rp21	on
 			# PCI Express root port #21 x4, Clock 11 (SSD2)
-			register "PcieRpEnable[20]" = "true"
 			register "PcieRpLtrEnable[20]" = "true"
 			register "PcieClkSrcUsage[11]" = "20"
 			register "PcieClkSrcClkReq[11]" = "11"
 		end
 		device ref pcie_rp9	on
 			# PCI Express root port #9 x4, Clock 12 (SSD)
-			register "PcieRpEnable[8]" = "true"
 			register "PcieRpLtrEnable[8]" = "true"
 			register "PcieClkSrcUsage[12]" = "8"
 			register "PcieClkSrcClkReq[12]" = "12"
 		end
 		device ref pcie_rp14	on
 			# PCI Express root port #14 x1, Clock 13 (WLAN)
-			register "PcieRpEnable[13]" = "true"
 			register "PcieRpLtrEnable[13]" = "true"
 			register "PcieClkSrcUsage[13]" = "13"
 			register "PcieClkSrcClkReq[13]" = "13"
 		end
 		device ref pcie_rp15	on
 			# PCI Express root port #15 x1, Clock 14 (GLAN)
-			register "PcieRpEnable[14]" = "true"
 			register "PcieRpLtrEnable[14]" = "true"
 			register "PcieClkSrcUsage[14]" = "14"
 			register "PcieClkSrcClkReq[14]" = "14"
 		end
 		device ref pcie_rp16	on
 			# PCI Express root port #16 x1, Clock 15 (Card Reader)
-			register "PcieRpEnable[15]" = "true"
 			register "PcieRpLtrEnable[15]" = "true"
 			register "PcieClkSrcUsage[15]" = "15"
 			register "PcieClkSrcClkReq[15]" = "15"
diff --git a/src/mainboard/system76/oryp6/devicetree.cb b/src/mainboard/system76/oryp6/devicetree.cb
index b1a0097711..d6423f3c2e 100644
--- a/src/mainboard/system76/oryp6/devicetree.cb
+++ b/src/mainboard/system76/oryp6/devicetree.cb
@@ -106,7 +106,6 @@ chip soc/intel/cannonlake
 		end
 		device ref pcie_rp17	on
 			# PCI Express root port #17 x4, Clock 0 (Thunderbolt)
-			register "PcieRpEnable[16]" = "true"
 			register "PcieRpLtrEnable[16]" = "true"
 			register "PcieRpHotPlug[16]" = "1"
 			register "PcieClkSrcUsage[0]" = "16"
@@ -115,7 +114,6 @@ chip soc/intel/cannonlake
 		end
 		device ref pcie_rp21	on
 			# PCI Express root port #21 x4, Clock 11 (SSD2)
-			register "PcieRpEnable[20]" = "true"
 			register "PcieRpLtrEnable[20]" = "true"
 			register "PcieClkSrcUsage[11]" = "20"
 			register "PcieClkSrcClkReq[11]" = "11"
@@ -123,7 +121,6 @@ chip soc/intel/cannonlake
 		end
 		device ref pcie_rp9	on
 			# PCI Express root port #9 x4, Clock 12 (SSD1)
-			register "PcieRpEnable[8]" = "true"
 			register "PcieRpLtrEnable[8]" = "true"
 			register "PcieClkSrcUsage[12]" = "8"
 			register "PcieClkSrcClkReq[12]" = "12"
@@ -131,7 +128,6 @@ chip soc/intel/cannonlake
 		end
 		device ref pcie_rp14	on
 			# PCI Express root port #14 x1, Clock 7 (GLAN)
-			register "PcieRpEnable[13]" = "true"
 			register "PcieRpLtrEnable[13]" = "true"
 			register "PcieClkSrcUsage[7]" = "13"
 			register "PcieClkSrcClkReq[7]" = "7"
@@ -139,7 +135,6 @@ chip soc/intel/cannonlake
 		end
 		device ref pcie_rp15	on
 			# PCI Express root port #15 x1, Clock 9 (Card Reader)
-			register "PcieRpEnable[14]" = "true"
 			register "PcieRpLtrEnable[14]" = "true"
 			register "PcieClkSrcUsage[9]" = "14"
 			register "PcieClkSrcClkReq[9]" = "9"
@@ -147,7 +142,6 @@ chip soc/intel/cannonlake
 		end
 		device ref pcie_rp16	on
 			# PCI Express root port #16 x1, Clock 6 (WLAN)
-			register "PcieRpEnable[15]" = "true"
 			register "PcieRpLtrEnable[15]" = "true"
 			register "PcieClkSrcUsage[6]" = "15"
 			register "PcieClkSrcClkReq[6]" = "6"
diff --git a/src/mainboard/system76/whl-u/devicetree.cb b/src/mainboard/system76/whl-u/devicetree.cb
index f3a7dffea4..1686f95eda 100644
--- a/src/mainboard/system76/whl-u/devicetree.cb
+++ b/src/mainboard/system76/whl-u/devicetree.cb
@@ -99,7 +99,6 @@ chip soc/intel/cannonlake
 		device ref pcie_rp1	on	end
 		device ref pcie_rp5	on
 			# PCI Express Root port #5 x4, Clock 4 (TBT)
-			register "PcieRpEnable[4]" = "true"
 			register "PcieRpLtrEnable[4]" = "true"
 			register "PcieRpHotPlug[4]" = "1"
 			register "PcieClkSrcUsage[4]" = "4"
@@ -107,21 +106,18 @@ chip soc/intel/cannonlake
 		end
 		device ref pcie_rp9	on
 			# PCI Express Root port #9 x1, Clock 3 (LAN)
-			register "PcieRpEnable[8]" = "true"
 			register "PcieRpLtrEnable[8]" = "true"
 			register "PcieClkSrcUsage[3]" = "8"
 			register "PcieClkSrcClkReq[3]" = "3"
 		end
 		device ref pcie_rp10	on
 			# PCI Express Root port #10 x1, Clock 2 (WLAN)
-			register "PcieRpEnable[9]" = "true"
 			register "PcieRpLtrEnable[9]" = "false"
 			register "PcieClkSrcUsage[2]" = "9"
 			register "PcieClkSrcClkReq[2]" = "2"
 		end
 		device ref pcie_rp13	on
 			# PCI Express Root port #13 x4, Clock 5 (NVMe)
-			register "PcieRpEnable[12]" = "true"
 			register "PcieRpLtrEnable[12]" = "true"
 			register "PcieClkSrcUsage[5]" = "12"
 			register "PcieClkSrcClkReq[5]" = "5"
diff --git a/src/soc/intel/cannonlake/Makefile.mk b/src/soc/intel/cannonlake/Makefile.mk
index 5ae0099990..96c02074ef 100644
--- a/src/soc/intel/cannonlake/Makefile.mk
+++ b/src/soc/intel/cannonlake/Makefile.mk
@@ -21,6 +21,7 @@ romstage-y += cnl_memcfg_init.c
 romstage-y += gspi.c
 romstage-y += i2c.c
 romstage-y += lpc.c
+romstage-y += pcie_rp.c
 romstage-y += pmutil.c
 romstage-y += reset.c
 romstage-y += spi.c
@@ -39,6 +40,7 @@ ramstage-y += lockdown.c
 ramstage-y += lpc.c
 ramstage-y += nhlt.c
 ramstage-y += p2sb.c
+ramstage-y += pcie_rp.c
 ramstage-y += pmc.c
 ramstage-y += pmutil.c
 ramstage-y += reset.c
diff --git a/src/soc/intel/cannonlake/chip.c b/src/soc/intel/cannonlake/chip.c
index 11bd9b6148..5df89641d3 100644
--- a/src/soc/intel/cannonlake/chip.c
+++ b/src/soc/intel/cannonlake/chip.c
@@ -15,23 +15,11 @@
 #include <intelblocks/xdci.h>
 #include <soc/intel/common/vbt.h>
 #include <soc/pci_devs.h>
+#include <soc/pcie.h>
 #include <soc/ramstage.h>
 
 #include "chip.h"
 
-static const struct pcie_rp_group pch_lp_rp_groups[] = {
-	{ .slot = PCH_DEV_SLOT_PCIE,	.count = 8, .lcap_port_base = 1 },
-	{ .slot = PCH_DEV_SLOT_PCIE_1,	.count = 8, .lcap_port_base = 1 },
-	{ 0 }
-};
-
-static const struct pcie_rp_group pch_h_rp_groups[] = {
-	{ .slot = PCH_DEV_SLOT_PCIE,	.count = 8, .lcap_port_base = 1 },
-	{ .slot = PCH_DEV_SLOT_PCIE_1,	.count = 8, .lcap_port_base = 1 },
-	{ .slot = PCH_DEV_SLOT_PCIE_2,	.count = 8, .lcap_port_base = 1 },
-	{ 0 }
-};
-
 #if CONFIG(HAVE_ACPI_TABLES)
 const char *soc_acpi_name(const struct device *dev)
 {
@@ -155,7 +143,7 @@ void soc_init_pre_device(void *chip_info)
 
 	/* swap enabled PCI ports in device tree if needed */
 	if (CONFIG(SOC_INTEL_CANNONLAKE_PCH_H)) {
-		pcie_rp_update_devicetree(pch_h_rp_groups);
+		pcie_rp_update_devicetree(get_pch_pcie_rp_table());
 
 		/*
 		 * Fix up device ID of hidden PCI device in devicetree.
@@ -166,7 +154,7 @@ void soc_init_pre_device(void *chip_info)
 			uart2->device = PCI_DID_INTEL_CNP_H_UART2;
 
 	} else {
-		pcie_rp_update_devicetree(pch_lp_rp_groups);
+		pcie_rp_update_devicetree(get_pch_pcie_rp_table());
 	}
 }
 
diff --git a/src/soc/intel/cannonlake/chip.h b/src/soc/intel/cannonlake/chip.h
index d4d9d0d11d..c01f36fdac 100644
--- a/src/soc/intel/cannonlake/chip.h
+++ b/src/soc/intel/cannonlake/chip.h
@@ -166,7 +166,6 @@ struct soc_intel_cannonlake_config {
 	bool PchHdaAudioLinkSndw4;
 
 	/* PCIe Root Ports */
-	bool PcieRpEnable[CONFIG_MAX_ROOT_PORTS];
 	/* PCIe output clocks type to PCIe devices.
 	 * 0-23: PCH rootport, 0x70: LAN, 0x80: unspecified but in use,
 	 * 0xFF: not used */
diff --git a/src/soc/intel/cannonlake/include/soc/pcie.h b/src/soc/intel/cannonlake/include/soc/pcie.h
new file mode 100644
index 0000000000..1ae524d412
--- /dev/null
+++ b/src/soc/intel/cannonlake/include/soc/pcie.h
@@ -0,0 +1,10 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef __SOC_CANNONLAKE_PCIE_H__
+#define __SOC_CANNONLAKE_PCIE_H__
+
+#include <intelblocks/pcie_rp.h>
+
+const struct pcie_rp_group *get_pch_pcie_rp_table(void);
+
+#endif /* __SOC_CANNONLAKE_PCIE_H__ */
diff --git a/src/soc/intel/cannonlake/pcie_rp.c b/src/soc/intel/cannonlake/pcie_rp.c
new file mode 100644
index 0000000000..4d37841c73
--- /dev/null
+++ b/src/soc/intel/cannonlake/pcie_rp.c
@@ -0,0 +1,26 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <intelblocks/pcie_rp.h>
+#include <soc/pci_devs.h>
+#include <soc/pcie.h>
+
+static const struct pcie_rp_group pch_lp_rp_groups[] = {
+	{ .slot = PCH_DEV_SLOT_PCIE,	.count = 8, .lcap_port_base = 1 },
+	{ .slot = PCH_DEV_SLOT_PCIE_1,	.count = 8, .lcap_port_base = 1 },
+	{ 0 }
+};
+
+static const struct pcie_rp_group pch_h_rp_groups[] = {
+	{ .slot = PCH_DEV_SLOT_PCIE,	.count = 8, .lcap_port_base = 1 },
+	{ .slot = PCH_DEV_SLOT_PCIE_1,	.count = 8, .lcap_port_base = 1 },
+	{ .slot = PCH_DEV_SLOT_PCIE_2,	.count = 8, .lcap_port_base = 1 },
+	{ 0 }
+};
+
+const struct pcie_rp_group *get_pch_pcie_rp_table(void)
+{
+	if (CONFIG(SOC_INTEL_CANNONLAKE_PCH_H))
+		return pch_h_rp_groups;
+
+	return pch_lp_rp_groups;
+}
diff --git a/src/soc/intel/cannonlake/romstage/fsp_params.c b/src/soc/intel/cannonlake/romstage/fsp_params.c
index f0dd1c39cd..f934459435 100644
--- a/src/soc/intel/cannonlake/romstage/fsp_params.c
+++ b/src/soc/intel/cannonlake/romstage/fsp_params.c
@@ -6,11 +6,13 @@
 #include <console/console.h>
 #include <fsp/util.h>
 #include <intelblocks/cpulib.h>
+#include <intelblocks/pcie_rp.h>
 #include <intelblocks/pmclib.h>
 #include <option.h>
 #include <soc/iomap.h>
 #include <soc/msr.h>
 #include <soc/pci_devs.h>
+#include <soc/pcie.h>
 #include <soc/romstage.h>
 #include <types.h>
 
@@ -24,7 +26,6 @@ void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version)
 	FSP_M_CONFIG *m_cfg = &mupd->FspmConfig;
 	FSP_M_TEST_CONFIG *tconfig = &mupd->FspmTestConfig;
 	unsigned int i;
-	uint32_t mask = 0;
 
 	m_cfg->HyperThreading = get_uint_option("hyper_threading", CONFIG(FSP_HYPERTHREADING));
 
@@ -51,11 +52,7 @@ void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version)
 		m_cfg->UserBd = BOARD_TYPE_ULT_ULX;
 	m_cfg->RMT = config->RMT;
 
-	for (i = 0; i < ARRAY_SIZE(config->PcieRpEnable); i++) {
-		if (config->PcieRpEnable[i])
-			mask |= (1 << i);
-	}
-	m_cfg->PcieRpEnableMask = mask;
+	m_cfg->PcieRpEnableMask = pcie_rp_enable_mask(get_pch_pcie_rp_table());
 	m_cfg->PrmrrSize = get_valid_prmrr_size();
 	m_cfg->EnableC6Dram = config->enable_c6dram;
 #if CONFIG(SOC_INTEL_COMETLAKE)

From fbca3e6806bfcc44de99295bbe07d7ac0da5da5f Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Sun, 20 Apr 2025 14:20:36 -0500
Subject: [PATCH 0809/3886] superio/ite/*: Move setting of power state to
 common code

Move the programming of the power state after power failure to the ITE
EC common code, in order to unify and extend to other ITE SIO chips.
The implementations in the it8720f and it8728f are functionally
identical, so take the "best" style elements of both, using clear
variable names and defines for registers rather than magic values.

Change-Id: I4b7e9455e964320f35997fdf04a515b942e030c7
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87382
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
---
 src/superio/ite/common/env_ctrl.c | 28 +++++++++++++++++++++++++++
 src/superio/ite/common/env_ctrl.h | 11 +++++++++++
 src/superio/ite/it8720f/it8720f.h |  4 ----
 src/superio/ite/it8720f/superio.c | 32 +------------------------------
 src/superio/ite/it8728f/superio.c | 30 +----------------------------
 5 files changed, 41 insertions(+), 64 deletions(-)

diff --git a/src/superio/ite/common/env_ctrl.c b/src/superio/ite/common/env_ctrl.c
index 105d6da8cf..c6b5ef04d5 100644
--- a/src/superio/ite/common/env_ctrl.c
+++ b/src/superio/ite/common/env_ctrl.c
@@ -4,6 +4,7 @@
 #include <delay.h>
 #include <stddef.h>
 #include <superio/hwm5_conf.h>
+#include <option.h>
 
 #include "env_ctrl.h"
 #include "env_ctrl_chip.h"
@@ -374,3 +375,30 @@ void ite_ec_init(const u16 base, const struct ite_ec_config *const conf)
 		if (conf->tmpin[i].mode == THERMAL_PECI)
 			extemp_force_idle_status(base);
 }
+
+void ite_ec_set_power_state(struct device *dev)
+{
+	uint8_t power_status;
+	uint8_t reg_pcr1, reg_pcr2;
+
+	/* Set power state after power fail */
+	power_status = get_uint_option("power_on_after_fail",
+					CONFIG_MAINBOARD_POWER_FAILURE_STATE);
+	pnp_enter_conf_mode(dev);
+	pnp_set_logical_device(dev);
+	reg_pcr1 = pnp_read_config(dev, ITE_EC_REG_PCR1);
+	reg_pcr2 = pnp_read_config(dev, ITE_EC_REG_PCR2);
+	if (power_status == MAINBOARD_POWER_ON) {
+		reg_pcr2 |= (1 << 5);
+	} else if (power_status == MAINBOARD_POWER_KEEP) {
+		reg_pcr2 &= ~(1 << 5);
+		reg_pcr1 |=  (1 << 5);
+	} else {
+		reg_pcr2 &= ~(1 << 5);
+		reg_pcr1 &= ~(1 << 5);
+	}
+	pnp_write_config(dev, ITE_EC_REG_PCR1, reg_pcr1);
+	pnp_write_config(dev, ITE_EC_REG_PCR2, reg_pcr2);
+	pnp_exit_conf_mode(dev);
+	printk(BIOS_INFO, "set power %u after power fail\n", power_status);
+}
diff --git a/src/superio/ite/common/env_ctrl.h b/src/superio/ite/common/env_ctrl.h
index 8a461aa3f2..4471bea756 100644
--- a/src/superio/ite/common/env_ctrl.h
+++ b/src/superio/ite/common/env_ctrl.h
@@ -235,6 +235,17 @@ static const u8 ITE_EC_TEMP_ADJUST[] = { 0x56, 0x57, 0x59 };
 #define PECI_GETTEMP_WRITE_LENGTH		0x01
 #define PECI_GETTEMP_READ_LENGTH		0x02
 
+/* Registers in EC LDN */
+#define ITE_EC_REG_PCR1				0xf2
+#define ITE_EC_REG_PCR2				0xf4
+
+/* These must match the values in src/mainboard/Kconfig */
+#define MAINBOARD_POWER_OFF			0
+#define MAINBOARD_POWER_ON			1
+#define MAINBOARD_POWER_KEEP			2
+
+void ite_ec_set_power_state(struct device *dev);
+
 void ite_ec_init(u16 base, const struct ite_ec_config *conf);
 
 #endif /* SUPERIO_ITE_ENV_CTRL_H */
diff --git a/src/superio/ite/it8720f/it8720f.h b/src/superio/ite/it8720f/it8720f.h
index 45c8256b64..77159506eb 100644
--- a/src/superio/ite/it8720f/it8720f.h
+++ b/src/superio/ite/it8720f/it8720f.h
@@ -14,8 +14,4 @@
 #define IT8720F_GPIO 0x07 /* GPIO (including SPI flash interface) */
 #define IT8720F_CIR  0x0a /* Consumer IR */
 
-/* Registers in LDNs */
-#define IT8720F_EC_PCR1	0xf2
-#define IT8720F_EC_PCR2	0xf4
-
 #endif /* SUPERIO_ITE_IT8720F_H */
diff --git a/src/superio/ite/it8720f/superio.c b/src/superio/ite/it8720f/superio.c
index 4491c10134..b51e768aef 100644
--- a/src/superio/ite/it8720f/superio.c
+++ b/src/superio/ite/it8720f/superio.c
@@ -3,7 +3,6 @@
 #include <device/device.h>
 #include <device/pnp.h>
 #include <pc80/keyboard.h>
-#include <option.h>
 #include <superio/ite/common/env_ctrl.h>
 #include <superio/conf_mode.h>
 #include <types.h>
@@ -11,35 +10,6 @@
 #include "chip.h"
 #include "it8720f.h"
 
-#define MAINBOARD_POWER_OFF	0
-#define MAINBOARD_POWER_ON	1
-#define MAINBOARD_POWER_KEEP	2
-
-static void power_control_init(struct device *dev)
-{
-	unsigned int power_on = get_uint_option("power_on_after_fail", MAINBOARD_POWER_OFF);
-	u8 value;
-
-	pnp_enter_conf_mode(dev);
-	pnp_set_logical_device(dev);
-
-	value = pnp_read_config(dev, IT8720F_EC_PCR1);
-	if (power_on == MAINBOARD_POWER_KEEP)
-		value |= (1 << 5);
-	else
-		value &= ~(1 << 5);
-	pnp_write_config(dev, IT8720F_EC_PCR1, value);
-
-	value = pnp_read_config(dev, IT8720F_EC_PCR2);
-	if (power_on == MAINBOARD_POWER_ON)
-		value |= (1 << 5);
-	else
-		value &= ~(1 << 5);
-	pnp_write_config(dev, IT8720F_EC_PCR2, value);
-
-	pnp_exit_conf_mode(dev);
-}
-
 static void it8720f_init(struct device *dev)
 {
 	const struct superio_ite_it8720f_config *conf;
@@ -55,7 +25,7 @@ static void it8720f_init(struct device *dev)
 		if (!conf || !res)
 			break;
 		ite_ec_init(res->base, &conf->ec);
-		power_control_init(dev);
+		ite_ec_set_power_state(dev);
 		break;
 	case IT8720F_KBCK:
 		pc_keyboard_init(NO_AUX_DEVICE);
diff --git a/src/superio/ite/it8728f/superio.c b/src/superio/ite/it8728f/superio.c
index f3bdd85b49..ca18e68f57 100644
--- a/src/superio/ite/it8728f/superio.c
+++ b/src/superio/ite/it8728f/superio.c
@@ -5,21 +5,14 @@
 #include <superio/conf_mode.h>
 #include <pc80/keyboard.h>
 #include <superio/ite/common/env_ctrl.h>
-#include <option.h>
 
 #include "chip.h"
 #include "it8728f.h"
 
-#define MAINBOARD_POWER_OFF	0
-#define MAINBOARD_POWER_ON	1
-#define MAINBOARD_POWER_KEEP	2
-
 static void it8728f_init(struct device *dev)
 {
 	const struct superio_ite_it8728f_config *conf = dev->chip_info;
 	const struct resource *res;
-	uint8_t power_status;
-	uint8_t byte_f2, byte_f4;
 
 	if (!dev->enabled)
 		return;
@@ -31,28 +24,7 @@ static void it8728f_init(struct device *dev)
 		if (!conf || !res)
 			break;
 		ite_ec_init(res->base, &conf->ec);
-
-		/* Set power state after power fail */
-		power_status = get_uint_option("power_on_after_fail",
-				CONFIG_MAINBOARD_POWER_FAILURE_STATE);
-		pnp_enter_conf_mode(dev);
-		pnp_set_logical_device(dev);
-		byte_f4 = pnp_read_config(dev, 0xf4);
-		byte_f2 = pnp_read_config(dev, 0xf2);
-		if (power_status == MAINBOARD_POWER_ON) {
-			byte_f4 |= 0x20;
-		} else if (power_status == MAINBOARD_POWER_KEEP) {
-			byte_f4 &= ~0x20;
-			byte_f2 |=  0x20;
-		} else {
-			byte_f4 &= ~0x20;
-			byte_f2 &= ~0x20;
-		}
-		pnp_write_config(dev, 0xf4, byte_f4);
-		pnp_write_config(dev, 0xf2, byte_f2);
-		pnp_exit_conf_mode(dev);
-		printk(BIOS_INFO, "set power %u after power fail\n", power_status);
-
+		ite_ec_set_power_state(dev);
 		break;
 	case IT8728F_KBCK:
 		set_kbc_ps2_mode();

From 4eba4e3f269624a1655860f5bcfe441503e62133 Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Sun, 20 Apr 2025 14:23:27 -0500
Subject: [PATCH 0810/3886] superio/ite/it8772f: Program power state after
 failure

Allow the power state after failure to be set using an option backend
if used, otherwise fall back to the Kconfig selection. This is a
noop for all it8772f boards unless they enable an option backend, in
which case that option setting is now functional, whereas before it
would have been ignored for the Kconfig selection.

TEST=build/boot google/panther with various power state after fail
Kconfig selections.

Change-Id: I1988d70fe27a287cd2cc91dbb905c243c24c816d
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87383
Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/superio/ite/it8772f/superio.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/src/superio/ite/it8772f/superio.c b/src/superio/ite/it8772f/superio.c
index 662b8a2ca9..59aca6243b 100644
--- a/src/superio/ite/it8772f/superio.c
+++ b/src/superio/ite/it8772f/superio.c
@@ -26,6 +26,7 @@ static void it8772f_init(struct device *dev)
 		if (!conf || !res)
 			break;
 		ite_ec_init(res->base, &conf->ec);
+		ite_ec_set_power_state(dev);
 		break;
 	case IT8772F_GPIO:
 		/* Set GPIO output levels */

From 73b095d5ea9b3efaa4f79ace501343f61b1ab084 Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Mon, 21 Apr 2025 19:33:13 -0500
Subject: [PATCH 0811/3886] mb/starlabs/*: Select DRIVERS_OPTION_CFR_ENABLED

Per the documentation, mainboards should select
`DRIVERS_OPTION_CFR_ENABLED` vs `DRIVERS_OPTION_CFR`, since the latter
is meant to be user selectable.

Change-Id: Ica2980fb9a8c69cae48e235ebbd72e824c24e010
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87411
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
---
 src/mainboard/starlabs/byte_adl/Kconfig     | 2 +-
 src/mainboard/starlabs/lite/Kconfig         | 2 +-
 src/mainboard/starlabs/starbook/Kconfig     | 2 +-
 src/mainboard/starlabs/starfighter/Kconfig  | 2 +-
 src/mainboard/starlabs/starlite_adl/Kconfig | 2 +-
 5 files changed, 5 insertions(+), 5 deletions(-)

diff --git a/src/mainboard/starlabs/byte_adl/Kconfig b/src/mainboard/starlabs/byte_adl/Kconfig
index 9b06ea43fa..0da8f59f40 100644
--- a/src/mainboard/starlabs/byte_adl/Kconfig
+++ b/src/mainboard/starlabs/byte_adl/Kconfig
@@ -1,7 +1,7 @@
 config BOARD_STARLABS_BYTE_SERIES
 	def_bool n
 	select DRIVERS_EFI_VARIABLE_STORE
-	select DRIVERS_OPTION_CFR
+	select DRIVERS_OPTION_CFR_ENABLED
 	select EC_STARLABS_ITE
 	select HAVE_ACPI_RESUME
 	select HAVE_ACPI_TABLES
diff --git a/src/mainboard/starlabs/lite/Kconfig b/src/mainboard/starlabs/lite/Kconfig
index 1f5c766262..09bc333e04 100644
--- a/src/mainboard/starlabs/lite/Kconfig
+++ b/src/mainboard/starlabs/lite/Kconfig
@@ -4,7 +4,7 @@ config BOARD_STARLABS_LITE_SERIES
 	def_bool n
 	select BOARD_ROMSIZE_KB_8192
 	select DRIVERS_EFI_VARIABLE_STORE
-	select DRIVERS_OPTION_CFR
+	select DRIVERS_OPTION_CFR_ENABLED
 	select DRIVERS_I2C_HID
 	select HAVE_ACPI_RESUME
 	select HAVE_ACPI_TABLES
diff --git a/src/mainboard/starlabs/starbook/Kconfig b/src/mainboard/starlabs/starbook/Kconfig
index eb718cc169..b266ba60c7 100644
--- a/src/mainboard/starlabs/starbook/Kconfig
+++ b/src/mainboard/starlabs/starbook/Kconfig
@@ -3,7 +3,7 @@
 config BOARD_STARLABS_STARBOOK_SERIES
 	def_bool n
 	select DRIVERS_EFI_VARIABLE_STORE
-	select DRIVERS_OPTION_CFR
+	select DRIVERS_OPTION_CFR_ENABLED
 	select DRIVERS_I2C_HID
 	select EC_STARLABS_ITE
 	select EC_STARLABS_FAN
diff --git a/src/mainboard/starlabs/starfighter/Kconfig b/src/mainboard/starlabs/starfighter/Kconfig
index a030d5ed02..4013bb6e91 100644
--- a/src/mainboard/starlabs/starfighter/Kconfig
+++ b/src/mainboard/starlabs/starfighter/Kconfig
@@ -4,7 +4,7 @@ config BOARD_STARLABS_STARFIGHTER_SERIES
 	def_bool n
 	select BOARD_ROMSIZE_KB_32768
 	select DRIVERS_EFI_VARIABLE_STORE
-	select DRIVERS_OPTION_CFR
+	select DRIVERS_OPTION_CFR_ENABLED
 	select DRIVERS_INTEL_PMC
 	select DRIVERS_INTEL_USB4_RETIMER
 	select DRIVERS_I2C_HID
diff --git a/src/mainboard/starlabs/starlite_adl/Kconfig b/src/mainboard/starlabs/starlite_adl/Kconfig
index 359fc9de8e..897b5a28fd 100644
--- a/src/mainboard/starlabs/starlite_adl/Kconfig
+++ b/src/mainboard/starlabs/starlite_adl/Kconfig
@@ -6,7 +6,7 @@ config BOARD_STARLABS_STARLITE_SERIES
 	select DRIVERS_GFX_GENERIC
 	select DRIVERS_I2C_HID
 	select DRIVERS_INTEL_PMC
-	select DRIVERS_OPTION_CFR
+	select DRIVERS_OPTION_CFR_ENABLED
 	select EC_STARLABS_CHARGING_SPEED
 	select EC_STARLABS_ITE
 	select EC_STARLABS_LID_SWITCH

From 32c78b7e22fb63855f74a72cd250b31a14b373b4 Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Sun, 20 Apr 2025 22:32:30 -0500
Subject: [PATCH 0812/3886] soc/intel/skylake: Hook up S0ix setting to option
 API
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Hook up the s0ix_enable setting to the option API, so it can be changed
at runtime without recompilation. Default to the value set by the
mainboard.

Change-Id: I1684439755db9d8194ac5533513e65c9ba8f0768
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87391
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
---
 src/soc/intel/skylake/chip.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/src/soc/intel/skylake/chip.c b/src/soc/intel/skylake/chip.c
index 715c008666..0356c3e8dd 100644
--- a/src/soc/intel/skylake/chip.c
+++ b/src/soc/intel/skylake/chip.c
@@ -417,6 +417,7 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
 	params->PchPmWolEnableOverride = config->WakeConfigWolEnableOverride;
 	params->PchPmPcieWakeFromDeepSx = config->WakeConfigPcieWakeFromDeepSx;
 	params->PchPmDeepSxPol = config->PmConfigDeepSxPol;
+	config->s0ix_enable = get_uint_option("s0ix_enable", config->s0ix_enable);
 	params->PchPmSlpS0Enable = config->s0ix_enable;
 	params->PchPmSlpS3MinAssert = config->PmConfigSlpS3MinAssert;
 	params->PchPmSlpS4MinAssert = config->PmConfigSlpS4MinAssert;

From f51c0bb090584a958f60192da35cf0f93e5038fb Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Sun, 20 Apr 2025 22:37:12 -0500
Subject: [PATCH 0813/3886] soc/intel/skylake: Hook up IGD config to option API
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Hook up the IGD config options IgdDvmt50PreAlloc and ApertureSize to the
option API, so they can be configured at runtime without recompilation.

The Aperture size falls back to the FSP default value, so no change if
unconfigured.

Change-Id: Ic900cb7bdc6dc532aef0c0b51b32bf8308a8ae36
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87392
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/soc/intel/skylake/romstage/fsp_params.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/src/soc/intel/skylake/romstage/fsp_params.c b/src/soc/intel/skylake/romstage/fsp_params.c
index 99bb5f1b6c..906301dd1f 100644
--- a/src/soc/intel/skylake/romstage/fsp_params.c
+++ b/src/soc/intel/skylake/romstage/fsp_params.c
@@ -116,7 +116,8 @@ static void soc_primary_gfx_config_params(FSP_M_CONFIG *m_cfg,
 	 *
 	 * If disabled, don't reserve memory for it.
 	 */
-	m_cfg->IgdDvmt50PreAlloc = m_cfg->InternalGfx ? 2 : 0;
+	m_cfg->IgdDvmt50PreAlloc = m_cfg->InternalGfx ? get_uint_option("igd_dvmt_prealloc", 2) : 0;
+	m_cfg->ApertureSize = get_uint_option("igd_aperture_size", 1);
 
 	m_cfg->PrimaryDisplay = config->PrimaryDisplay;
 }

From f14aa06606759d60db98089458362b4f2135187d Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Sun, 20 Apr 2025 22:54:43 -0500
Subject: [PATCH 0814/3886] soc/intel/skylake: Add CFR objects for existing
 options

Add a header with CFR objects for existing configuration options,
so that supported boards can make use of them without duplication.

Change-Id: Id69295ae1708164b1afbafe5724e19bf13fc3963
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87393
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/soc/intel/skylake/include/soc/cfr.h | 87 +++++++++++++++++++++++++
 1 file changed, 87 insertions(+)
 create mode 100644 src/soc/intel/skylake/include/soc/cfr.h

diff --git a/src/soc/intel/skylake/include/soc/cfr.h b/src/soc/intel/skylake/include/soc/cfr.h
new file mode 100644
index 0000000000..ad5c6f6f53
--- /dev/null
+++ b/src/soc/intel/skylake/include/soc/cfr.h
@@ -0,0 +1,87 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+/*
+ * CFR enums and structs which are used to control SoC settings.
+ */
+
+#ifndef SKYLAKE_CFR_H
+#define SKYLAKE_CFR_H
+
+#include <drivers/option/cfr_frontend.h>
+
+/* FSP hyperthreading */
+static const struct sm_object hyper_threading = SM_DECLARE_ENUM({
+	.opt_name	= "hyper_threading",
+	.ui_name	= "Hyper-Threading",
+	.ui_helptext	= "Enable or disable Hyper-Threading",
+	.default_value	= CONFIG(FSP_HYPERTHREADING),
+	.values		= (const struct sm_enum_value[]) {
+				{ "Disabled",		0	},
+				{ "Enabled",		1	},
+				SM_ENUM_VALUE_END		},
+});
+
+/* IGD Aperture Size */
+static const struct sm_object igd_aperture = SM_DECLARE_ENUM({
+	.opt_name	= "igd_aperture_size",
+	.ui_name	= "IGD Aperture Size",
+	.ui_helptext	= "Select the Aperture Size",
+	.default_value	= 1,
+	.values		= (const struct sm_enum_value[]) {
+				{ "128 MB",		0	},
+				{ "256 MB",		1	},
+				{ "512 MB",		2	},
+				SM_ENUM_VALUE_END		},
+});
+
+/* IGD DVMT pre-allocated memory */
+static const struct sm_object igd_dvmt = SM_DECLARE_ENUM({
+	.opt_name	= "igd_dvmt_prealloc",
+	.ui_name	= "IGD DVMT Size",
+	.ui_helptext	= "Size of memory preallocated for internal graphics",
+	.default_value	= 2,
+	.values		= (const struct sm_enum_value[]) {
+				{ "32 MB",		1	},
+				{ "64 MB",		2	},
+				{ "96 MB",		3	},
+				{ "128 MB",		4	},
+				SM_ENUM_VALUE_END		},
+});
+
+/* Legacy 8254 Timer */
+static const struct sm_object legacy_8254_timer = SM_DECLARE_ENUM({
+	.opt_name	= "legacy_8254_timer",
+	.ui_name	= "Legacy 8254 Timer",
+	.ui_helptext	= "Enable the legacy 8254 timer by disabling clock gating.",
+	.default_value	= 0,
+	.values		= (const struct sm_enum_value[]) {
+				{ "Disabled",		0	},
+				{ "Enabled",		1	},
+				SM_ENUM_VALUE_END		},
+});
+
+/* S0ix Enable */
+static const struct sm_object s0ix_enable = SM_DECLARE_ENUM({
+	.opt_name	= "s0ix_enable",
+	.ui_name	= "Modern Standby (S0ix)",
+	.ui_helptext	= "Enabled: use Modern Standby / S0ix. Disabled: use APCI S3 sleep",
+	.default_value	= 1,
+	.values		= (const struct sm_enum_value[]) {
+				{ "Disabled",		0	},
+				{ "Enabled",		1	},
+				SM_ENUM_VALUE_END		},
+});
+
+/* VT-d */
+static const struct sm_object vtd = SM_DECLARE_ENUM({
+	.opt_name	= "vtd",
+	.ui_name	= "VT-d",
+	.ui_helptext	= "Enable or disable Intel VT-d (virtualization)",
+	.default_value	= 1,
+	.values		= (const struct sm_enum_value[]) {
+				{ "Disabled",		0	},
+				{ "Enabled",		1	},
+				SM_ENUM_VALUE_END		},
+});
+
+#endif /* SKYLAKE_CFR_H */

From ada6b987663d2298a88a4751beaa4bef3a6eb9bd Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Sun, 20 Apr 2025 17:11:27 -0500
Subject: [PATCH 0815/3886] nb/intel/sandybridge: Add CFR objects for existing
 options
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Add a header with CFR objects for existing configuration options,
so that supported boards can make use of them.

Currently only one option for IGD UMA size, but others can be added
as needed.

Change-Id: I892ffcc74d36a266697cbc7ea3c8880db6b67f44
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87388
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
---
 src/northbridge/intel/sandybridge/cfr.h | 34 +++++++++++++++++++++++++
 1 file changed, 34 insertions(+)
 create mode 100644 src/northbridge/intel/sandybridge/cfr.h

diff --git a/src/northbridge/intel/sandybridge/cfr.h b/src/northbridge/intel/sandybridge/cfr.h
new file mode 100644
index 0000000000..fafc80b809
--- /dev/null
+++ b/src/northbridge/intel/sandybridge/cfr.h
@@ -0,0 +1,34 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+/*
+ * CFR enums and structs for nb/sandybridge
+ */
+
+#ifndef NB_SANDYBRIDGE_CFR_H
+#define NB_SANDYBRIDGE_CFR_H
+
+#include <drivers/option/cfr_frontend.h>
+
+/* Values must match nb/sandybridge/Kconfig */
+enum {
+	IGD_UMA_SIZE_32MB,
+	IGD_UMA_SIZE_64MB,
+	IGD_UMA_SIZE_96MB,
+	IGD_UMA_SIZE_128MB,
+};
+
+/* IGD UMA Size */
+static const struct sm_object gfx_uma_size = SM_DECLARE_ENUM({
+	.opt_name	= "gfx_uma_size",
+	.ui_name	= "IGD UMA Size",
+	.ui_helptext	= "Size of memory preallocated for internal graphics.",
+	.default_value	= CONFIG_IGD_DEFAULT_UMA_INDEX,
+	.values		= (const struct sm_enum_value[]) {
+				{ " 32MB", IGD_UMA_SIZE_32MB	},
+				{ " 64MB", IGD_UMA_SIZE_64MB	},
+				{ " 96MB", IGD_UMA_SIZE_96MB	},
+				{ "128MB", IGD_UMA_SIZE_128MB	},
+				SM_ENUM_VALUE_END		},
+});
+
+#endif /* NB_SANDYBRIDGE_CFR_H */

From a899359720158a619f2933940cc2da8a48c43aad Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Sun, 20 Apr 2025 17:14:18 -0500
Subject: [PATCH 0816/3886] sb/intel/bd82x6x: Add CFR objects for existing
 options

Add a header with CFR objects for existing configuration options,
so that supported boards can make use of them without duplication.

TEST=build/boot samsung/stumpy with CFR options enabled.

Change-Id: Ia6906992deb948869ecfd8a5f6fc3883220811ec
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87389
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
---
 src/southbridge/intel/bd82x6x/cfr.h | 83 +++++++++++++++++++++++++++++
 1 file changed, 83 insertions(+)
 create mode 100644 src/southbridge/intel/bd82x6x/cfr.h

diff --git a/src/southbridge/intel/bd82x6x/cfr.h b/src/southbridge/intel/bd82x6x/cfr.h
new file mode 100644
index 0000000000..8b9f928f34
--- /dev/null
+++ b/src/southbridge/intel/bd82x6x/cfr.h
@@ -0,0 +1,83 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+/*
+ * CFR enums and structs for sb/bd82x6x
+ */
+
+#ifndef SB_BD82X6X_CFR_H
+#define SB_BD82X6X_CFR_H
+
+#include <drivers/option/cfr_frontend.h>
+#include <southbridge/intel/common/pmutil.h>
+#include "me.h"
+
+/* Power state after power loss */
+static const struct sm_object power_on_after_fail = SM_DECLARE_ENUM({
+	.opt_name	= "power_on_after_fail",
+	.ui_name	= "Restore AC Power Loss",
+	.ui_helptext	= "Specify what to do when power is re-applied after a power loss.",
+	.default_value	= CONFIG_MAINBOARD_POWER_FAILURE_STATE,
+	.values		= (const struct sm_enum_value[]) {
+				{ "Power off (S5)", MAINBOARD_POWER_OFF		},
+				{ "Power on  (S0)", MAINBOARD_POWER_ON		},
+				{ "Previous state", MAINBOARD_POWER_KEEP	},
+				SM_ENUM_VALUE_END				},
+});
+
+/* Intel ME State */
+static const struct sm_object me_state = SM_DECLARE_ENUM({
+	.opt_name	= "me_state",
+	.ui_name	= "Intel Management Engine",
+	.ui_helptext	= "Enable or disable the Intel Management Engine",
+	.default_value	= CMOS_ME_STATE_NORMAL,
+	.values		= (const struct sm_enum_value[]) {
+				{ "Disabled",		CMOS_ME_STATE_DISABLED	},
+				{ "Enabled",		CMOS_ME_STATE_NORMAL	},
+				SM_ENUM_VALUE_END				},
+});
+
+/* Intel ME State on previous boot */
+static const struct sm_object me_state_prev = SM_DECLARE_NUMBER({
+	.opt_name	= "me_state_prev",
+	.ui_name	= "ME State Previous Boot",
+	.flags		= CFR_OPTFLAG_SUPPRESS,
+	.default_value	= CMOS_ME_STATE_NORMAL,
+});
+
+enum {
+	SATA_MODE_AHCI,
+	SATA_MODE_IDE_COMPAT,
+	SATA_MODE_IDE_LEGACY,
+};
+
+/* SATA controller mode */
+static const struct sm_object sata_mode = SM_DECLARE_ENUM({
+	.opt_name	= "sata_mode",
+	.ui_name	= "SATA Mode",
+	.ui_helptext	= "Specify mode of the SATA controller",
+	.default_value	= SATA_MODE_AHCI,
+	.values		= (const struct sm_enum_value[]) {
+				{ "AHCI",		SATA_MODE_AHCI		},
+				{ "IDE (compatible)",	SATA_MODE_IDE_COMPAT	},
+				{ "IDE (legacy)",	SATA_MODE_IDE_LEGACY	},
+				SM_ENUM_VALUE_END				},
+});
+
+enum {
+	NMI_OFF,
+	NMI_ON,
+};
+
+/* Non-maskable interrupts */
+static const struct sm_object nmi = SM_DECLARE_ENUM({
+	.opt_name	= "nmi",
+	.ui_name	= "Non-maskable Interrupts",
+	.ui_helptext	= "Enable or disable non-maskable interrupts",
+	.default_value	= NMI_OFF,
+	.values		= (const struct sm_enum_value[]) {
+				{ "Disabled",	NMI_OFF	},
+				{ "Enabled",	NMI_ON	},
+				SM_ENUM_VALUE_END	},
+});
+
+#endif /* SB_BD82X6X_CFR_H */

From c0e3f6d1d20cc87d7d081606479c597bade4033b Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Mon, 21 Apr 2025 16:04:12 -0500
Subject: [PATCH 0817/3886] drivers/efi/variable_store: Select necessary UDK
 binding as needed

DRIVERS_EFI_VARIABLE_STORE requires some Intel vendorcode headers which
are selected by default on FSP 2.x platforms, but not by earlier ones.
Select the oldest UDK binding for non-FSP 2.x boards, so that the
required headers are available, rather than depending on UDK_BASE
and requiring those boards to manually select the binding.

TEST=build samsung/stumpy with EFI variable store support, without
manually selecting UDK_2017_BINDING at the mainboard level.

Change-Id: I099d3cc7690a0faecfe32a8bc814766c67c63fbb
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87408
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/drivers/efi/Kconfig | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/drivers/efi/Kconfig b/src/drivers/efi/Kconfig
index 07e5f146a6..7969c6a2b4 100644
--- a/src/drivers/efi/Kconfig
+++ b/src/drivers/efi/Kconfig
@@ -2,7 +2,7 @@
 
 config DRIVERS_EFI_VARIABLE_STORE
 	bool "Include EFI variable store driver"
-	depends on UDK_BASE
+	select UDK_2017_BINDING if !PLATFORM_USES_FSP2_0
 	help
 	  Adds a driver that is able to read and write an EFI formatted
 	  VariableStore as used by tianocore.

From 20ceed192904542bbc6eb1729796681129bb67e1 Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Mon, 21 Apr 2025 16:10:19 -0500
Subject: [PATCH 0818/3886] drivers/efi/fw_info: Select necessary UDK binding
 as needed

DRIVERS_EFI_FW_INFO requires some Intel vendorcode headers which are
selected by default on FSP 2.x platforms, but not by earlier ones.
Select the oldest UDK binding for non-FSP 2.x boards, so that the
required headers are available, rather than depending on UDK_BASE
and requiring those boards to manually select the binding

Change-Id: I27ab64ab0c9d4d45cc09061f6f8c3725c24df706
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87409
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
---
 src/drivers/efi/Kconfig | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/drivers/efi/Kconfig b/src/drivers/efi/Kconfig
index 7969c6a2b4..9f63938a3a 100644
--- a/src/drivers/efi/Kconfig
+++ b/src/drivers/efi/Kconfig
@@ -9,7 +9,7 @@ config DRIVERS_EFI_VARIABLE_STORE
 
 config DRIVERS_EFI_FW_INFO
 	bool "Expose firmware version in a EFI-friendly form"
-	depends on UDK_BASE
+	select UDK_2017_BINDING if !PLATFORM_USES_FSP2_0
 	help
 	  Adds firmware version information to coreboot table in a form similar to
 	  EFI System Resource Table (ESRT) that can be used for firmware updates.

From 936ca8404a8efd8936266241c4a62f8afda2876f Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Mon, 21 Apr 2025 16:11:26 -0500
Subject: [PATCH 0819/3886] drivers/option/cfr: Select EFI variable store when
 edk2 payload used

Since CFR options require a backend to store the keys/values, select
DRIVERS_EFI_VARIABLE_STORE when edk2 is used as the payload and
SMMSTORE is enabled, so that boards only need to select
DRIVERS_OPTION_CFR in order to have a fully-functioning configuration
setup.

TEST=build samsung/stumpy with DRIVERS_OPTION_CFR selected and edk2
payload used.

Change-Id: Ib8565e4fefb1b3f05e58ab039be8ab0d1bc046f1
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87410
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
---
 src/drivers/option/Kconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/src/drivers/option/Kconfig b/src/drivers/option/Kconfig
index 6c63bb49b0..2d005cc11f 100644
--- a/src/drivers/option/Kconfig
+++ b/src/drivers/option/Kconfig
@@ -3,4 +3,5 @@ config DRIVERS_OPTION_CFR_ENABLED
 
 config DRIVERS_OPTION_CFR
 	bool "Support generating a CFR list of options"
+	select DRIVERS_EFI_VARIABLE_STORE if PAYLOAD_EDK2 && SMMSTORE
 	default y if DRIVERS_OPTION_CFR_ENABLED

From e3d3fc5b4affe53e479f9b5894a736b4beabf42f Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Mon, 21 Apr 2025 13:56:30 -0500
Subject: [PATCH 0820/3886] mb/samsung/stumpy: Use CFR setup menu to manage
 options

Enable support for managing system options via CFR, and select it by
default when using edk2 with SMMSTORE.

TEST=build/boot stumpy w/edk2 payload

Change-Id: I91166a3932931c04eae78065fec6b856aebc6f0b
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87404
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
---
 src/mainboard/samsung/stumpy/Kconfig     |  1 +
 src/mainboard/samsung/stumpy/Makefile.mk |  2 ++
 src/mainboard/samsung/stumpy/cfr.c       | 37 ++++++++++++++++++++++++
 3 files changed, 40 insertions(+)
 create mode 100644 src/mainboard/samsung/stumpy/cfr.c

diff --git a/src/mainboard/samsung/stumpy/Kconfig b/src/mainboard/samsung/stumpy/Kconfig
index 456791fdf3..5d8bc32326 100644
--- a/src/mainboard/samsung/stumpy/Kconfig
+++ b/src/mainboard/samsung/stumpy/Kconfig
@@ -5,6 +5,7 @@ if BOARD_SAMSUNG_STUMPY
 config BOARD_SPECIFIC_OPTIONS
 	def_bool y
 	select BOARD_ROMSIZE_KB_8192
+	select DRIVERS_OPTION_CFR_ENABLED if PAYLOAD_EDK2 && SMMSTORE
 	select MAINBOARD_HAS_CHROMEOS
 	select MEMORY_MAPPED_TPM
 	select MAINBOARD_HAS_TPM1
diff --git a/src/mainboard/samsung/stumpy/Makefile.mk b/src/mainboard/samsung/stumpy/Makefile.mk
index 57ec1c5048..ab23599f60 100644
--- a/src/mainboard/samsung/stumpy/Makefile.mk
+++ b/src/mainboard/samsung/stumpy/Makefile.mk
@@ -8,3 +8,5 @@ romstage-y += gpio.c
 ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads
 bootblock-y += early_init.c
 romstage-y += early_init.c
+
+ramstage-$(CONFIG_DRIVERS_OPTION_CFR) += cfr.c
diff --git a/src/mainboard/samsung/stumpy/cfr.c b/src/mainboard/samsung/stumpy/cfr.c
new file mode 100644
index 0000000000..d1650a0503
--- /dev/null
+++ b/src/mainboard/samsung/stumpy/cfr.c
@@ -0,0 +1,37 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <boot/coreboot_tables.h>
+#include <drivers/option/cfr_frontend.h>
+#include <northbridge/intel/sandybridge/cfr.h>
+#include <southbridge/intel/bd82x6x/cfr.h>
+
+static struct sm_obj_form system = {
+	.ui_name = "System",
+	.obj_list = (const struct sm_object *[]) {
+		&gfx_uma_size,
+		&me_state,
+		&me_state_prev,
+		&nmi,
+		&sata_mode,
+		NULL
+	},
+};
+
+static struct sm_obj_form power = {
+	.ui_name = "Power",
+	.obj_list = (const struct sm_object *[]) {
+		&power_on_after_fail,
+		NULL
+	},
+};
+
+static struct sm_obj_form *sm_root[] = {
+	&system,
+	&power,
+	NULL
+};
+
+void mb_cfr_setup_menu(struct lb_cfr *cfr_root)
+{
+	cfr_write_setup_menu(cfr_root, sm_root);
+}

From 204aae207ddd7b68e5279b9dc95cbe52500f39cd Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Mon, 21 Apr 2025 14:02:36 -0500
Subject: [PATCH 0821/3886] mb/samsung/stumpy: Clean up makefile

Organize according to stage, alphabetize, and guard inclusion of
ChromeOS-specific code.

TEST=build/boot stumpy

Change-Id: Id6ea4e685ff3e098f6c619e1cab48a5a9320c29b
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87405
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/samsung/stumpy/Makefile.mk | 12 ++++++------
 1 file changed, 6 insertions(+), 6 deletions(-)

diff --git a/src/mainboard/samsung/stumpy/Makefile.mk b/src/mainboard/samsung/stumpy/Makefile.mk
index ab23599f60..6997db7876 100644
--- a/src/mainboard/samsung/stumpy/Makefile.mk
+++ b/src/mainboard/samsung/stumpy/Makefile.mk
@@ -1,12 +1,12 @@
 ## SPDX-License-Identifier: GPL-2.0-only
 
-romstage-y += chromeos.c
-ramstage-y += chromeos.c
+bootblock-y += early_init.c
 bootblock-y += gpio.c
+
+romstage-$(CONFIG_CHROMEOS) += chromeos.c
+romstage-y += early_init.c
 romstage-y += gpio.c
 
-ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads
-bootblock-y += early_init.c
-romstage-y += early_init.c
-
 ramstage-$(CONFIG_DRIVERS_OPTION_CFR) += cfr.c
+ramstage-$(CONFIG_CHROMEOS) += chromeos.c
+ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads

From 42379e7f76079587bfed4a14707a351df0448e49 Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Sun, 20 Apr 2025 16:02:43 -0500
Subject: [PATCH 0822/3886] sb/intel/lynxpoint: Allow ME enable/disable via
 option
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Add an option variable 'me_disable' to control the visibility of the
HECI PCI device at runtime. Default to the Kconfig selection if not set.

Change-Id: I12c4c9f062cb5904c2f9c05b333bf0ed81aba632
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87384
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/southbridge/intel/lynxpoint/me.c | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/src/southbridge/intel/lynxpoint/me.c b/src/southbridge/intel/lynxpoint/me.c
index b0d98d4c2b..ddeb4b4b50 100644
--- a/src/southbridge/intel/lynxpoint/me.c
+++ b/src/southbridge/intel/lynxpoint/me.c
@@ -18,6 +18,7 @@
 #include <string.h>
 #include <delay.h>
 #include <elog.h>
+#include <option.h>
 #include <stdlib.h>
 
 #include "chip.h"
@@ -542,7 +543,7 @@ void intel_me_finalize(struct device *dev)
 	/* Try to send EOP command so ME stops accepting other commands */
 	mkhi_end_of_post();
 
-	if (!CONFIG(DISABLE_ME_PCI))
+	if (!get_uint_option("me_disable", CONFIG(DISABLE_ME_PCI)))
 		return;
 
 	/* Make sure IO is disabled */
@@ -905,7 +906,7 @@ static void intel_me_init(struct device *dev)
 static void intel_me_enable(struct device *dev)
 {
 	/* Avoid talking to the device in S3 path */
-	if (acpi_is_wakeup_s3() && CONFIG(DISABLE_ME_PCI)) {
+	if (acpi_is_wakeup_s3() && get_uint_option("me_disable", CONFIG(DISABLE_ME_PCI))) {
 		dev->enabled = 0;
 		pch_disable_devfn(dev);
 	}

From 5efb54d371334fc352da4d7df3378a68d05aceff Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Sun, 20 Apr 2025 16:05:54 -0500
Subject: [PATCH 0823/3886] soc/intel/broadwell: Allow ME enable/disable to be
 set via option

Add an option variable 'me_disable' to control the visibility of the
HECI PCI device at runtime. Default to the Kconfig selection if not set.

Change-Id: I6e7c018115780c74f1662948ed8dad3e0559051a
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87386
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
---
 src/soc/intel/broadwell/pch/me.c | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/src/soc/intel/broadwell/pch/me.c b/src/soc/intel/broadwell/pch/me.c
index 147eb29a2f..5756bdb00d 100644
--- a/src/soc/intel/broadwell/pch/me.c
+++ b/src/soc/intel/broadwell/pch/me.c
@@ -19,6 +19,7 @@
 #include <string.h>
 #include <delay.h>
 #include <elog.h>
+#include <option.h>
 #include <soc/me.h>
 #include <soc/lpc.h>
 #include <soc/pch.h>
@@ -600,7 +601,7 @@ static void intel_me_finalize(struct device *dev)
 	if (!mei_base_address || mei_base_address == (u8 *)0xfffffff0)
 		return;
 
-	if (!CONFIG(DISABLE_ME_PCI))
+	if (!get_uint_option("me_disable", CONFIG(DISABLE_ME_PCI)))
 		return;
 
 	/* Make sure IO is disabled */
@@ -1025,7 +1026,7 @@ static void intel_me_init(struct device *dev)
 static void intel_me_enable(struct device *dev)
 {
 	/* Avoid talking to the device in S3 path */
-	if (acpi_is_wakeup_s3() && CONFIG(DISABLE_ME_PCI)) {
+	if (acpi_is_wakeup_s3() && get_uint_option("me_disable", CONFIG(DISABLE_ME_PCI))) {
 		dev->enabled = 0;
 		pch_disable_devfn(dev);
 	}

From b830fdc2d7d9f9b275c6024db2730d64ca87a677 Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Mon, 21 Apr 2025 10:25:40 -0500
Subject: [PATCH 0824/3886] soc/intel/cannonlake: Hook up IGD config to option
 API

Hook up the IGD config options IgdDvmt50PreAlloc and ApertureSize to the
option API, so they can be configured at runtime without recompilation.

The Aperture size falls back to the FSP default value, so no change if
unconfigured.

Change-Id: Idad22ca79c10d575320b4360ec24c2019a837446
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87398
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
---
 src/soc/intel/cannonlake/romstage/fsp_params.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/src/soc/intel/cannonlake/romstage/fsp_params.c b/src/soc/intel/cannonlake/romstage/fsp_params.c
index f934459435..5083e577ad 100644
--- a/src/soc/intel/cannonlake/romstage/fsp_params.c
+++ b/src/soc/intel/cannonlake/romstage/fsp_params.c
@@ -37,7 +37,8 @@ void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version)
 	if (igd_on && pci_read_config16(SA_DEV_IGD, PCI_VENDOR_ID) != 0xffff) {
 		/* Set IGD stolen size to 64MB. */
 		m_cfg->InternalGfx = 1;
-		m_cfg->IgdDvmt50PreAlloc = 2;
+		m_cfg->IgdDvmt50PreAlloc = get_uint_option("igd_dvmt_prealloc", 2);
+		m_cfg->ApertureSize = get_uint_option("igd_aperture_size", 1);
 	} else {
 		m_cfg->InternalGfx = 0;
 		m_cfg->IgdDvmt50PreAlloc = 0;

From 509b01c3b6af3c4e575606fcd706411ef473e4bf Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Mon, 21 Apr 2025 10:34:22 -0500
Subject: [PATCH 0825/3886] soc/intel/cannonlake: Hook up S0ix setting to
 option API

Hook up the s0ix_enable setting to the option API, so it can be changed
at runtime without recompilation. Default to the value set by the
mainboard.

Change-Id: I1c51e653a9e34bb7f5ac07bcae8481be269f83cf
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87400
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
---
 src/soc/intel/cannonlake/fsp_params.c | 7 ++++---
 1 file changed, 4 insertions(+), 3 deletions(-)

diff --git a/src/soc/intel/cannonlake/fsp_params.c b/src/soc/intel/cannonlake/fsp_params.c
index f1db0f7d20..55a7c92aa0 100644
--- a/src/soc/intel/cannonlake/fsp_params.c
+++ b/src/soc/intel/cannonlake/fsp_params.c
@@ -381,6 +381,10 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
 	s_cfg->PchPmSlpS0Vm070VSupport = config->PchPmSlpS0Vm070VSupport;
 	s_cfg->PchPmSlpS0Vm075VSupport = config->PchPmSlpS0Vm075VSupport;
 
+	/* S0ix */
+	config->s0ix_enable = get_uint_option("s0ix_enable", config->s0ix_enable);
+	s_cfg->PchPmSlpS0Enable = config->s0ix_enable;
+
 	/* Lan */
 	s_cfg->PchLanEnable = is_devfn_enabled(PCH_DEVFN_GBE);
 	if (s_cfg->PchLanEnable) {
@@ -433,9 +437,6 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
 	s_cfg->PchPmPcieWakeFromDeepSx = config->LanWakeFromDeepSx;
 	s_cfg->PchPmWolEnableOverride = config->WolEnableOverride;
 
-	/* S0ix */
-	s_cfg->PchPmSlpS0Enable = config->s0ix_enable;
-
 	/* disable Legacy PME */
 	memset(s_cfg->PcieRpPmSci, 0, sizeof(s_cfg->PcieRpPmSci));
 

From 49bf8f94a06d636208a0afb2c35b56df57f2eeea Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Mon, 17 Mar 2025 18:56:48 -0500
Subject: [PATCH 0826/3886] soc/intel/common: Add CFR objects for existing
 options

Add a header with CFR objects for existing configuration options,
so that supported boards can make use of them without duplication.

Change-Id: I97d5d8b78cc9e5516dbfc64f81a925b1715b941b
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87390
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
---
 .../common/block/include/intelblocks/cfr.h    | 106 ++++++++++++++++++
 1 file changed, 106 insertions(+)
 create mode 100644 src/soc/intel/common/block/include/intelblocks/cfr.h

diff --git a/src/soc/intel/common/block/include/intelblocks/cfr.h b/src/soc/intel/common/block/include/intelblocks/cfr.h
new file mode 100644
index 0000000000..c240b769f3
--- /dev/null
+++ b/src/soc/intel/common/block/include/intelblocks/cfr.h
@@ -0,0 +1,106 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+/*
+ * CFR enums and structs which are used to control various Intel common block settings.
+ */
+
+#ifndef SOC_INTEL_CMN_CFR_H
+#define SOC_INTEL_CMN_CFR_H
+
+#include <drivers/option/cfr_frontend.h>
+#include <intelblocks/pcie_rp.h>
+#include <intelblocks/pmclib.h>
+
+/* Intel ME State */
+static const struct sm_object me_state = SM_DECLARE_ENUM({
+	.opt_name	= "me_state",
+	.ui_name	= "Intel Management Engine",
+	.ui_helptext	= "Enable or disable the Intel Management Engine",
+	.default_value	= 0,
+	.values		= (const struct sm_enum_value[]) {
+				{ "Disabled",		1		},
+				{ "Enabled",		0		},
+				SM_ENUM_VALUE_END			},
+});
+
+/* Intel ME State Counter */
+static const struct sm_object me_state_counter = SM_DECLARE_NUMBER({
+	.opt_name	= "me_state_counter",
+	.ui_name	= "ME State Counter",
+	.flags		= CFR_OPTFLAG_SUPPRESS,
+	.default_value	= 0,
+});
+
+/* Power state after power loss */
+static const struct sm_object power_on_after_fail = SM_DECLARE_ENUM({
+	.opt_name	= "power_on_after_fail",
+	.ui_name	= "Restore AC Power Loss",
+	.ui_helptext	= "Specify what to do when power is re-applied after a power loss.",
+	.default_value	= CONFIG_MAINBOARD_POWER_FAILURE_STATE,
+	.values		= (const struct sm_enum_value[]) {
+				{ "Power off (S5)", MAINBOARD_POWER_STATE_OFF		},
+				{ "Power on  (S0)", MAINBOARD_POWER_STATE_ON		},
+				{ "Previous state", MAINBOARD_POWER_STATE_PREVIOUS	},
+				SM_ENUM_VALUE_END					},
+});
+
+/* PCIe RP ASPM */
+static const struct sm_object pciexp_aspm = SM_DECLARE_ENUM({
+	.opt_name	= "pciexp_aspm",
+	.ui_name	= "PCIe RP ASPM",
+	.ui_helptext	= "Controls the Active State Power Management for PCIe devices."
+			  " Enabling this feature can reduce power consumption of"
+			  " PCIe-connected devices during idle times.",
+	.default_value	= ASPM_AUTO,
+	.values		= (const struct sm_enum_value[]) {
+				{ "Disabled",	ASPM_DISABLE	},
+				{ "L0s",	ASPM_L0S	},
+				{ "L1",		ASPM_L1		},
+				{ "L0sL1",	ASPM_L0S_L1	},
+				{ "Auto",	ASPM_AUTO	},
+				SM_ENUM_VALUE_END		},
+});
+
+/* PCIe Clock PM */
+static const struct sm_object pciexp_clk_pm = SM_DECLARE_BOOL({
+	.opt_name	= "pciexp_clk_pm",
+	.ui_name	= "PCIe Clock Power Management",
+	.ui_helptext	= "Enables or disables power management for the PCIe clock. When"
+			  " enabled, it reduces power consumption during idle states."
+			  " This can help lower overall energy use but may impact"
+			  " performance in power-sensitive tasks.",
+	.default_value	= true,
+});
+
+/* PCIe L1 Substates */
+static const struct sm_object pciexp_l1ss = SM_DECLARE_ENUM({
+	.opt_name	= "pciexp_l1ss",
+	.ui_name	= "PCIe L1 Substates",
+	.ui_helptext	= "Controls deeper power-saving states for PCIe devices."
+			  " Enabling this feature allows supported devices to achieve"
+			  " lower power states at the cost of slightly increased"
+			  " latency when exiting these states.",
+	.default_value	= L1_SS_L1_2,
+	.values		= (const struct sm_enum_value[]) {
+				{ "Disabled",	L1_SS_DISABLED	},
+				{ "L1.1",	L1_SS_L1_1	},
+				{ "L1.2",	L1_SS_L1_2	},
+				SM_ENUM_VALUE_END		},
+});
+
+/* PCIe PCH Root Port Speed */
+static const struct sm_object pciexp_speed = SM_DECLARE_ENUM({
+	.opt_name	= "pciexp_speed",
+	.ui_name	= "PCIe PCH Root Port Speed",
+	.ui_helptext	= "Sets the maximum port speed for PCIe devices attached to PCH root ports.",
+	.default_value	= SPEED_AUTO,
+	.values		= (const struct sm_enum_value[]) {
+				{ "Auto",	SPEED_AUTO	},
+				{ "Gen1",	SPEED_GEN1	},
+				{ "Gen2",	SPEED_GEN2	},
+				{ "Gen3",	SPEED_GEN3	},
+				{ "Gen4",	SPEED_GEN4	},
+				SM_ENUM_VALUE_END		},
+});
+
+#endif /* SOC_INTEL_CMN_CFR_H */

From 92f9c8a9850e82f06f3b96c7e51d854271d30d28 Mon Sep 17 00:00:00 2001
From: Nick Vaccaro <nvaccaro@google.com>
Date: Mon, 14 Apr 2025 10:59:11 -0700
Subject: [PATCH 0827/3886] mb/google/ocelot: update FW_CONFIG

Update the FW_CONFIG to correspond to the Google Ocelot hardware SKUs
and remove code that is no longer needed due to the FW_CONFIG changes.

Removed support for AUDIO_ALC722_SNDW, AUDIO_MAX98360_ALC56821_I2S,
AUDIO_MAX98373_ALC5682_SNDW, TOUCHSCREEN_LPSS_I2C, UFC_MIPI, UFC_USB,
WFC_MIPI and WFC_USB.

Added support for AUDIO_ALC721_SNDW, DISPLAY_TOUCH_PRESENT, and
DISPLAY_NO_TOUCH_PRESENT.

BUG=b:412736286
BRANCH=None
TEST=`emerge-ocelot coreboot` and verify it compiles without error.

Change-Id: I5fd7010230a3f17005f5ca395ffaca0724a615e9
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87310
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
---
 .../google/ocelot/variants/ocelot/fw_config.c | 113 +-----
 .../ocelot/variants/ocelot/overridetree.cb    | 354 ++----------------
 .../google/ocelot/variants/ocelot/variant.c   |   6 +-
 3 files changed, 37 insertions(+), 436 deletions(-)

diff --git a/src/mainboard/google/ocelot/variants/ocelot/fw_config.c b/src/mainboard/google/ocelot/variants/ocelot/fw_config.c
index 9419caf709..fd29768aa6 100644
--- a/src/mainboard/google/ocelot/variants/ocelot/fw_config.c
+++ b/src/mainboard/google/ocelot/variants/ocelot/fw_config.c
@@ -11,37 +11,6 @@
 /* t: table */
 #define GPIO_CONFIGURE_PADS(t) gpio_configure_pads(t, ARRAY_SIZE(t))
 
-static const struct pad_config i2s_enable_pads[] = {
-	/* I2S_MCLK1_OUT */
-	PAD_CFG_NF(GPP_D09, NONE, DEEP, NF2),
-	/* I2S0_SCLK_HDR */
-	PAD_CFG_NF(GPP_D10, NONE, DEEP, NF2),
-	/* I2S0_SFRM_HDR */
-	PAD_CFG_NF(GPP_D11, NONE, DEEP, NF2),
-	/* I2S0_TXD_HDR */
-	PAD_CFG_NF(GPP_D12, NONE, DEEP, NF2),
-	/* I2S0_RXD_HDR */
-	PAD_CFG_NF(GPP_D13, NONE, DEEP, NF2),
-	/* I2S1_SCLK_HDR */
-	PAD_CFG_NF(GPP_S00, NONE, DEEP, NF6),
-	/* I2S1_SFRM_HDR */
-	PAD_CFG_NF(GPP_S01, NONE, DEEP, NF6),
-	/* I2S1_TXD_HDR */
-	PAD_CFG_NF(GPP_S02, NONE, DEEP, NF6),
-	/* I2S1_RXD_HDR */
-	PAD_CFG_NF(GPP_S03, NONE, DEEP, NF6),
-
-	/* DMIC_CLK */
-	PAD_CFG_NF(GPP_D16, NONE, DEEP, NF3),
-	/* DMIC_DATA */
-	PAD_CFG_NF(GPP_D17, NONE, DEEP, NF3),
-
-	/* DMIC_CLK */
-	PAD_CFG_NF(GPP_S04, NONE, DEEP, NF5),
-	/* DMIC_DATA */
-	PAD_CFG_NF(GPP_S05, NONE, DEEP, NF5),
-};
-
 static const struct pad_config hda_enable_pads[] = {
 	/* HDA_BCLK */
 	PAD_CFG_NF(GPP_D10, NONE, DEEP, NF1),
@@ -62,29 +31,6 @@ static const struct pad_config hda_enable_pads[] = {
 	PAD_CFG_NF(GPP_S05, NONE, DEEP, NF5),
 };
 
-static const struct pad_config sndw_external_codec_enable_pads[] = {
-	/* Soundwire - External codec - JE Header */
-	/* SNDW3_CLK */
-	PAD_CFG_NF(GPP_S00, NONE, DEEP, NF1),
-	/* SNDW3_DATA0 */
-	PAD_CFG_NF(GPP_S01, NONE, DEEP, NF1),
-	/* SNDW0_CLK */
-	PAD_CFG_NF(GPP_S02, NONE, DEEP, NF3),
-	/* SNDW0_DATA */
-	PAD_CFG_NF(GPP_S03, NONE, DEEP, NF3),
-	/* SNDW2_CLK */
-	PAD_CFG_NF(GPP_S04, NONE, DEEP, NF2),
-	/* SNDW2_DATA */
-	PAD_CFG_NF(GPP_S05, NONE, DEEP, NF2),
-	/* SNDW1_CLK */
-	PAD_CFG_NF(GPP_S06, NONE, DEEP, NF3),
-	/* SNDW1_DATA */
-	PAD_CFG_NF(GPP_S07, NONE, DEEP, NF3),
-
-	/* GPP_D13: RST_HP_L */
-	PAD_CFG_GPO(GPP_D13, 1, PLTRST),
-};
-
 static const struct pad_config bt_i2s_enable_pads[] = {
 	/* GPP_V30 : [] ==> BT_I2S_BCLK - SSP2 */
 	PAD_CFG_NF(GPP_VGPIO30, NONE, DEEP, NF3),
@@ -123,7 +69,7 @@ static const struct pad_config bt_i2s_disable_pads[] = {
 	PAD_NC(GPP_VGPIO37, NONE),
 };
 
-static const struct pad_config sndw_alc722_enable_pads[] = {
+static const struct pad_config sndw_alc721_enable_pads[] = {
 	/* SNDW3_CLK   */
 	PAD_CFG_NF(GPP_S00, NONE, DEEP, NF1),
 	/* SNDW3_DATA0 */
@@ -353,25 +299,6 @@ static const struct pad_config touchscreen_disable_pads[] = {
 	PAD_NC(GPP_E18, NONE),
 };
 
-static const struct pad_config touchscreen_lpss_i2c_enable_pads[] = {
-	/* GPP_E11:     THC0_SPI1_CLK_TCH_PNL1 */
-	PAD_NC(GPP_E11, NONE),
-	/* GPP_E12:     THC0_SPI1_IO_0_I2C4_SCL_TCH_PNL1 NF8: I2C4_SCL */
-	PAD_CFG_NF(GPP_E12, NONE, DEEP, NF8),
-	/* GPP_E13:     THC0_SPI1_IO_1_I2C4_SDA_TCH_PNL1 NF8: I2C4 SDA */
-	PAD_CFG_NF(GPP_E13, NONE, DEEP, NF8),
-	/* GPP_E14:     THC0_SPI1_IO_2_TCH_PNL1 */
-	PAD_NC(GPP_E14, NONE),
-	/* GPP_E15:     THC0_SPI1_IO_3_TCH_PNL1 */
-	PAD_NC(GPP_E15, NONE),
-	/* GPP_E16:     THC0_SPI1_RST_N_TCH_PNL1 */
-	PAD_CFG_GPO(GPP_E16, 1, DEEP),
-	/* GPP_E17:     THC0_SPI1_CS0_N_TCH_PNL1 */
-	PAD_NC(GPP_E17, NONE),
-	/* GPP_E18:     THC0_SPI1_INT_N_TCH_PNL1 */
-	PAD_CFG_GPI_APIC(GPP_E18, NONE, PLTRST, LEVEL, NONE),
-};
-
 static const struct pad_config touchscreen_thc_i2c_enable_pads[] = {
 	/* GPP_E11:     THC0_SPI1_CLK_TCH_PNL1 */
 	PAD_NC(GPP_E11, NONE),
@@ -391,25 +318,6 @@ static const struct pad_config touchscreen_thc_i2c_enable_pads[] = {
 	PAD_CFG_GPI_APIC(GPP_E18, NONE, PLTRST, LEVEL, NONE),
 };
 
-static const struct pad_config touchscreen_gspi_enable_pads[] = {
-	/* GPP_E11:     THC0_SPI1_CLK_TCH_PNL1 NF5: GSPI0 */
-	PAD_CFG_NF(GPP_E11, NONE, DEEP, NF5),
-	/* GPP_E12:     THC0_SPI1_IO_0_I2C4_SCL_TCH_PNL1 NF5: GSPI0 */
-	PAD_CFG_NF(GPP_E12, NONE, DEEP, NF5),
-	/* GPP_E13:     THC0_SPI1_IO_1_I2C4_SDA_TCH_PNL1 NF5: GSPI0 */
-	PAD_CFG_NF(GPP_E13, NONE, DEEP, NF5),
-	/* GPP_E14:     THC0_SPI1_IO_2_TCH_PNL1 */
-	PAD_NC(GPP_E14, NONE),
-	/* GPP_E15:     THC0_SPI1_IO_3_TCH_PNL1 */
-	PAD_NC(GPP_E15, NONE),
-	/* GPP_E16:     THC0_SPI1_RST_N_TCH_PNL1 */
-	PAD_CFG_GPO(GPP_E16, 1, DEEP),
-	/* GPP_E17:     THC0_SPI1_CS0_N_TCH_PNL1 NF5: GSPI0 */
-	PAD_CFG_NF(GPP_E17, NONE, DEEP, NF5),
-	/* GPP_E18:     THC0_SPI1_INT_N_TCH_PNL1 */
-	PAD_CFG_GPI_APIC(GPP_E18, NONE, PLTRST, EDGE_SINGLE, INVERT)
-};
-
 static const struct pad_config touchscreen_thc_spi_enable_pads[] = {
 	/* GPP_E11:     THC0_SPI1_CLK_TCH_PNL1 NF3: THC HID-SPI */
 	PAD_CFG_NF(GPP_E11, NONE, DEEP, NF3),
@@ -576,18 +484,9 @@ void fw_config_gpio_padbased_override(struct pad_config *padbased_table)
 	if (fw_config_probe(FW_CONFIG(AUDIO, AUDIO_NONE))) {
 		GPIO_PADBASED_OVERRIDE(padbased_table, audio_disable_pads);
 		GPIO_PADBASED_OVERRIDE(padbased_table, bt_i2s_disable_pads);
-	} else if (fw_config_probe(FW_CONFIG(AUDIO, AUDIO_MAX98360_ALC5682I_I2S))) {
-		printk(BIOS_INFO, "Configure GPIOs for I2S MAX98360 ALC5682 audio.\n");
-		GPIO_PADBASED_OVERRIDE(padbased_table, i2s_enable_pads);
-		printk(BIOS_INFO, "Configure GPIOs for BT offload mode.\n");
-		GPIO_PADBASED_OVERRIDE(padbased_table, bt_i2s_enable_pads);
-	} else if (fw_config_probe(FW_CONFIG(AUDIO, AUDIO_MAX98373_ALC5682_SNDW))) {
-		GPIO_PADBASED_OVERRIDE(padbased_table, sndw_external_codec_enable_pads);
-		GPIO_PADBASED_OVERRIDE(padbased_table, bt_i2s_disable_pads);
-	} else if (fw_config_probe(FW_CONFIG(AUDIO, AUDIO_ALC722_SNDW)) ||
-			fw_config_probe(FW_CONFIG(AUDIO, AUDIO_ALC721_SNDW))) {
+	} else if (fw_config_probe(FW_CONFIG(AUDIO, AUDIO_ALC721_SNDW))) {
 		printk(BIOS_INFO, "Configure GPIOs for Soundwire audio.\n");
-		GPIO_PADBASED_OVERRIDE(padbased_table, sndw_alc722_enable_pads);
+		GPIO_PADBASED_OVERRIDE(padbased_table, sndw_alc721_enable_pads);
 		printk(BIOS_INFO, "Configure GPIOs for BT offload mode.\n");
 		GPIO_PADBASED_OVERRIDE(padbased_table, bt_i2s_enable_pads);
 	} else if (fw_config_probe(FW_CONFIG(AUDIO, AUDIO_ALC256_HDA))) {
@@ -625,12 +524,8 @@ void fw_config_gpio_padbased_override(struct pad_config *padbased_table)
 	else
 		GPIO_PADBASED_OVERRIDE(padbased_table, touchpad_i2c_disable_pads);
 
-	if (fw_config_probe(FW_CONFIG(TOUCHSCREEN, TOUCHSCREEN_LPSS_I2C)))
-		GPIO_PADBASED_OVERRIDE(padbased_table, touchscreen_lpss_i2c_enable_pads);
-	else if (fw_config_probe(FW_CONFIG(TOUCHSCREEN, TOUCHSCREEN_THC_I2C)))
+	if (fw_config_probe(FW_CONFIG(TOUCHSCREEN, TOUCHSCREEN_THC_I2C)))
 		GPIO_PADBASED_OVERRIDE(padbased_table, touchscreen_thc_i2c_enable_pads);
-	else if (fw_config_probe(FW_CONFIG(TOUCHSCREEN, TOUCHSCREEN_GSPI)))
-		GPIO_PADBASED_OVERRIDE(padbased_table, touchscreen_gspi_enable_pads);
 	else if (fw_config_probe(FW_CONFIG(TOUCHSCREEN, TOUCHSCREEN_THC_SPI)))
 		GPIO_PADBASED_OVERRIDE(padbased_table, touchscreen_thc_spi_enable_pads);
 	else
diff --git a/src/mainboard/google/ocelot/variants/ocelot/overridetree.cb b/src/mainboard/google/ocelot/variants/ocelot/overridetree.cb
index cb4c21a1f7..6b99983b7c 100644
--- a/src/mainboard/google/ocelot/variants/ocelot/overridetree.cb
+++ b/src/mainboard/google/ocelot/variants/ocelot/overridetree.cb
@@ -1,72 +1,59 @@
 fw_config
-	field AUDIO 0 3
-		option AUDIO_NONE			0
-		option AUDIO_MAX98373_ALC5682_SNDW	1
-		option AUDIO_ALC722_SNDW		2
-		option AUDIO_ALC256_HDA			3
-		option AUDIO_MAX98360_ALC5682I_I2S	4
-		option AUDIO_ALC721_SNDW		5
+	field AUDIO 0 1
+		option AUDIO_NONE		0
+		option AUDIO_ALC721_SNDW	1
+		option AUDIO_ALC256_HDA		2
 	end
-	field WIFI 4 5
-		option WIFI_CNVI_6		0
-		option WIFI_CNVI_7		1
+	field WIFI 2 4
+		option WIFI_NONE		0
+		option WIFI_CNVI_6		1
 		option WIFI_PCIE_6		2
-		option WIFI_PCIE_7		3
+		option WIFI_CNVI_7		3
+		option WIFI_PCIE_7		4
 	end
-	field CELLULAR 6 7
+	field CELLULAR 5 6
 		option CELLULAR_ABSENT		0
 		option CELLULAR_USB		1
 		option CELLULAR_PCIE		2
 	end
-	field TOUCHSCREEN 8 10
+	field TOUCHSCREEN 7 8
 		option TOUCHSCREEN_NONE		0
-		option TOUCHSCREEN_LPSS_I2C	1
-		option TOUCHSCREEN_GSPI		2
-		option TOUCHSCREEN_THC_SPI	3
-		option TOUCHSCREEN_THC_I2C	4
+		option TOUCHSCREEN_THC_SPI	1
+		option TOUCHSCREEN_THC_I2C	2
 	end
-	field TOUCHPAD 11 12
+	field TOUCHPAD 9 10
 		option TOUCHPAD_NONE		0
 		option TOUCHPAD_THC_I2C		1
 		option TOUCHPAD_LPSS_I2C	2
 	end
-	field SD 13 14
+	field SD 11 12
 		option SD_NONE			0
 		option SD_GENSYS		1
 		option SD_BAYHUB		2
 	end
-	field STORAGE 15 16
+	field STORAGE 13 14
 		option STORAGE_UNKNOWN		0
 		option STORAGE_NVME_GEN4	1
 		option STORAGE_NVME_GEN5	2
 		option STORAGE_UFS		3
 	end
-	field FP 17
+	field FP 15
 		option FP_ABSENT		0
 		option FP_PRESENT		1
 	end
-	field DISPLAY 18
+	field DISPLAY 16 17
 		option DISPLAY_ABSENT		0
-		option DISPLAY_PRESENT		1
+		option DISPLAY_TOUCH_PRESENT	1
+		option DISPLAY_NO_TOUCH_PRESENT	2
+	end
+	field ISH 18
+		option ISH_DISABLE		0
+		option ISH_ENABLE		1
 	end
 	field KB 19
 		option KB_ABSENT		0
 		option KB_PRESENT		1
 	end
-	field UFC 20 21
-		option UFC_ABSENT		0
-		option UFC_MIPI			1
-		option UFC_USB			2
-	end
-	field WFC 22 23
-		option WFC_ABSENT		0
-		option WFC_MIPI			1
-		option WFC_USB			2
-	end
-	field ISH 24
-		option ISH_DISABLE		0
-		option ISH_ENABLE		1
-	end
 end
 
 chip soc/intel/pantherlake
@@ -145,7 +132,8 @@ chip soc/intel/pantherlake
 
 	device domain 0 on
 		device ref igpu on
-			probe DISPLAY DISPLAY_PRESENT
+			probe DISPLAY DISPLAY_TOUCH_PRESENT
+			probe DISPLAY DISPLAY_NO_TOUCH_PRESENT
 			chip drivers/gfx/generic
 				register "device_count" = "5"
 				# DDIA for eDP
@@ -296,24 +284,7 @@ chip soc/intel/pantherlake
 			end
 		end
 
-		device ref ipu on
-			chip drivers/intel/mipi_camera
-				register "acpi_uid" = "0x50000"
-				register "acpi_name" = ""IPU0""
-				register "device_type" = "INTEL_ACPI_CAMERA_CIO2"
-				register "cio2_num_ports" = "2"
-				register "cio2_lanes_used" = "{4,2}" # 4 and 2 CSI Camera lanes are used
-				register "cio2_lane_endpoint[0]" = ""^I2C1.CAM0""
-				register "cio2_lane_endpoint[1]" = ""^I2C2.CAM1""
-				register "cio2_prt[0]" = "0"
-				register "cio2_prt[1]" = "2"
-				device generic 0 on
-					probe UFC UFC_MIPI
-					probe WFC WFC_MIPI
-				end
-			end
-		end
-
+		device ref ipu off end
 		device ref iaa off end
 
 		device ref thc0 on
@@ -576,246 +547,16 @@ chip soc/intel/pantherlake
 		# NOTE: i2c0 is function 0; hence it needs to be enabled when any of i2c1-5 is enabled.
 		# TPM device is under i2c3. Therefore, i2c0 needs to be enabled anyways.
 		device ref i2c0 on end
-		device ref i2c1 on
-			chip drivers/intel/mipi_camera
-				register "acpi_hid" = ""OVTIDB10""
-				register "acpi_uid" = "0"
-				register "acpi_name" = ""CAM0""
-				register "chip_name" = ""Ov 13b10 Camera""
-				register "device_type" = "INTEL_ACPI_CAMERA_SENSOR"
-
-				register "ssdb.vcm_type" = "0x0C"
-				register "vcm_name" = ""VCM1""
-
-				register "ssdb.lanes_used" = "4"
-				register "num_freq_entries" = "1"
-				register "link_freq[0]" = "560 * MHz" # 560 MHz
-				register "remote_name" = ""IPU0""
-				register "max_dstate_for_probe" = "ACPI_DEVICE_SLEEP_D3_COLD"
-
-				register "has_power_resource" = "true"
-				#Controls
-				register "clk_panel.clks[0].clknum" = "0" # IMGCLKOUT_0
-				register "clk_panel.clks[0].freq" = "1" #19.2 Mhz
-				register "gpio_panel.gpio[0].gpio_num" = "GPP_C05" #power_enable
-				register "gpio_panel.gpio[1].gpio_num" = "GPP_E10" #reset
-
-				#_ON
-				register "on_seq.ops_cnt" = "4"
-				register "on_seq.ops[0]" = "SEQ_OPS_CLK_ENABLE(0, 0)"
-				register "on_seq.ops[1]" = "SEQ_OPS_GPIO_ENABLE(0, 2)"
-				register "on_seq.ops[2]" = "SEQ_OPS_GPIO_DISABLE(1, 1)"
-				register "on_seq.ops[3]" = "SEQ_OPS_GPIO_ENABLE(1, 1)"
-
-				#_OFF
-				register "off_seq.ops_cnt" = "3"
-				register "off_seq.ops[0]" = "SEQ_OPS_CLK_DISABLE(0, 0)"
-				register "off_seq.ops[1]" = "SEQ_OPS_GPIO_DISABLE(1, 0)"
-				register "off_seq.ops[2]" = "SEQ_OPS_GPIO_DISABLE(0, 0)"
-
-				device i2c 36 on
-					probe WFC WFC_MIPI
-				end
-			end
-			chip drivers/intel/mipi_camera
-				register "acpi_uid" = "3"
-				register "acpi_name" = ""VCM1""
-				register "chip_name" = ""DW AF VCM""
-				register "device_type" = "INTEL_ACPI_CAMERA_VCM"
-
-				register "vcm_compat" = ""dongwoon,dw9714""
-
-				register "max_dstate_for_probe" = "ACPI_DEVICE_SLEEP_D0"
-
-				register "has_power_resource" = "true"
-
-				#Controls
-				register "gpio_panel.gpio[0].gpio_num" = "GPP_C05" #power_enable
-
-				#_ON
-				register "on_seq.ops_cnt" = "1"
-				register "on_seq.ops[0]" = "SEQ_OPS_GPIO_ENABLE(0, 0)"
-
-				#_OFF
-				register "off_seq.ops_cnt" = "1"
-				register "off_seq.ops[0]" = "SEQ_OPS_GPIO_DISABLE(0, 0)"
-
-				device i2c 0C on
-					probe WFC WFC_MIPI
-				end
-			end
-			chip drivers/intel/mipi_camera
-				register "acpi_uid" = "1"
-				register "acpi_name" = ""NVM1""
-				register "chip_name" = ""BRCA016GWZ""
-				register "device_type" = "INTEL_ACPI_CAMERA_NVM"
-
-				register "nvm_compat" = ""atmel,24c16""
-
-				register "nvm_size" = "0x800"
-				register "nvm_pagesize" = "0x01"
-				register "nvm_readonly" = "0x01"
-				register "nvm_width" = "0x08"
-
-				register "max_dstate_for_probe" = "ACPI_DEVICE_SLEEP_D0"
-
-				register "has_power_resource" = "true"
-
-				#Controls
-				register "gpio_panel.gpio[0].gpio_num" = "GPP_C05" #power_enable
-
-				#_ON
-				register "on_seq.ops_cnt" = "1"
-				register "on_seq.ops[0]" = "SEQ_OPS_GPIO_ENABLE(0, 0)"
-
-				#_OFF
-				register "off_seq.ops_cnt" = "1"
-				register "off_seq.ops[0]" = "SEQ_OPS_GPIO_DISABLE(0, 0)"
-
-				device i2c 50 on
-					probe WFC WFC_MIPI
-				end
-			end
-		end # I2C1
-		device ref i2c2 on
-			chip drivers/intel/mipi_camera
-				register "acpi_hid" = ""OVTIDB10""
-				register "acpi_uid" = "0"
-				register "acpi_name" = ""CAM1""
-				register "chip_name" = ""Ov 13b10 Camera""
-				register "device_type" = "INTEL_ACPI_CAMERA_SENSOR"
-
-				register "ssdb.vcm_type" = "0x0C"
-				register "vcm_name" = ""VCM1""
-
-				register "ssdb.lanes_used" = "2"
-				register "num_freq_entries" = "1"
-				register "link_freq[0]" = "560 * MHz" # 560 MHz
-				register "remote_name" = ""IPU0""
-				register "max_dstate_for_probe" = "ACPI_DEVICE_SLEEP_D3_COLD"
-
-				register "has_power_resource" = "true"
-				#Controls
-				register "clk_panel.clks[0].clknum" = "1" # IMGCLKOUT_1
-				register "clk_panel.clks[0].freq" = "1" #19.2 Mhz
-				register "gpio_panel.gpio[0].gpio_num" = "GPP_C08" #power_enable
-				register "gpio_panel.gpio[1].gpio_num" = "GPP_E01" #reset
-
-				#_ON
-				register "on_seq.ops_cnt" = "4"
-				register "on_seq.ops[0]" = "SEQ_OPS_CLK_ENABLE(0, 0)"
-				register "on_seq.ops[1]" = "SEQ_OPS_GPIO_ENABLE(0, 2)"
-				register "on_seq.ops[2]" = "SEQ_OPS_GPIO_DISABLE(1, 1)"
-				register "on_seq.ops[3]" = "SEQ_OPS_GPIO_ENABLE(1, 1)"
-
-				#_OFF
-				register "off_seq.ops_cnt" = "3"
-				register "off_seq.ops[0]" = "SEQ_OPS_CLK_DISABLE(0, 0)"
-				register "off_seq.ops[1]" = "SEQ_OPS_GPIO_DISABLE(1, 0)"
-				register "off_seq.ops[2]" = "SEQ_OPS_GPIO_DISABLE(0, 0)"
-
-				device i2c 36 on
-					probe UFC UFC_MIPI
-				end
-			end
-			chip drivers/intel/mipi_camera
-				register "acpi_uid" = "3"
-				register "acpi_name" = ""VCM1""
-				register "chip_name" = ""DW AF VCM""
-				register "device_type" = "INTEL_ACPI_CAMERA_VCM"
-
-				register "vcm_compat" = ""dongwoon,dw9714""
-
-				register "max_dstate_for_probe" = "ACPI_DEVICE_SLEEP_D0"
-
-				register "has_power_resource" = "true"
-
-				#Controls
-				register "gpio_panel.gpio[0].gpio_num" = "GPP_C08" #power_enable
-
-				#_ON
-				register "on_seq.ops_cnt" = "1"
-				register "on_seq.ops[0]" = "SEQ_OPS_GPIO_ENABLE(0, 0)"
-
-				#_OFF
-				register "off_seq.ops_cnt" = "1"
-				register "off_seq.ops[0]" = "SEQ_OPS_GPIO_DISABLE(0, 0)"
-
-				device i2c 0C on
-					probe UFC UFC_MIPI
-				end
-			end
-			chip drivers/intel/mipi_camera
-				register "acpi_uid" = "1"
-				register "acpi_name" = ""NVM1""
-				register "chip_name" = ""BRCA016GWZ""
-				register "device_type" = "INTEL_ACPI_CAMERA_NVM"
-
-				register "nvm_compat" = ""atmel,24c16""
-
-				register "nvm_size" = "0x800"
-				register "nvm_pagesize" = "0x01"
-				register "nvm_readonly" = "0x01"
-				register "nvm_width" = "0x08"
-
-				register "max_dstate_for_probe" = "ACPI_DEVICE_SLEEP_D0"
-
-				register "has_power_resource" = "true"
-
-				#Controls
-				register "gpio_panel.gpio[0].gpio_num" = "GPP_C08" #power_enable
-
-				#_ON
-				register "on_seq.ops_cnt" = "1"
-				register "on_seq.ops[0]" = "SEQ_OPS_GPIO_ENABLE(0, 0)"
-
-				#_OFF
-				register "off_seq.ops_cnt" = "1"
-				register "off_seq.ops[0]" = "SEQ_OPS_GPIO_DISABLE(0, 0)"
-
-				device i2c 50 on
-					probe UFC UFC_MIPI
-				end
-			end
-		end # I2C2
+		device ref i2c1 on end
+		device ref i2c2 on end
 		device ref i2c3 on
-			chip drivers/i2c/generic
-				register "hid" = ""RTL5682""
-				register "name" = ""RT58""
-				register "desc" = ""Headset Codec""
-				register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_F17)"
-				# Set the jd_src to RT5668_JD1 for jack detection
-				register "property_count" = "1"
-				register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER"
-				register "property_list[0].name" = ""realtek,jd-src""
-				register "property_list[0].integer" = "1"
-				device i2c 1a on
-					probe AUDIO AUDIO_MAX98360_ALC5682I_I2S
-				end
-			end
 			chip drivers/i2c/tpm
 				register "hid" = ""GOOG0005""
 				register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_D15_IRQ)"
 				device i2c 50 on end
 			end
 		end # I2C3
-		device ref i2c4 on
-			chip drivers/i2c/hid
-				register "generic.hid" = ""ELAN6918""
-				register "generic.desc" = ""ELAN Touchscreen""
-				register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_E18_IRQ)"
-				register "generic.probed" = "1"
-				register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_E16)"
-				register "generic.reset_delay_ms" = "20"
-				register "generic.reset_off_delay_ms" = "2"
-				register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_F08)"
-				register "generic.enable_delay_ms" = "1"
-				register "generic.has_power_resource" = "1"
-				register "hid_desc_reg_offset" = "0x01"
-				device i2c 16 on
-					probe TOUCHSCREEN TOUCHSCREEN_LPSS_I2C
-				end
-			end
+		device ref i2c4 off
 		end # I2C4
 		device ref i2c5 on
 			chip drivers/i2c/hid
@@ -852,39 +593,6 @@ chip soc/intel/pantherlake
 
 		device ref smbus on end
 		device ref npk on end
-		device ref hda on
-			chip drivers/intel/soundwire
-				device generic 0 on
-					chip drivers/soundwire/alc711
-						register "desc" = ""Headset Codec""
-						register "alc711_address.version" = "SOUNDWIRE_VERSION_1_2"
-						register "alc711_address.class" = "MIPI_CLASS_SDCA"
-						register "alc711_address.part_id" = "MIPI_DEV_ID_REALTEK_ALC722"
-						# SoundWire Link 1 ID 1
-						device generic 1.1 on
-							probe AUDIO AUDIO_ALC722_SNDW
-						end
-					end
-					chip drivers/soundwire/alc711
-						register "desc" = ""Headset Codec""
-						register "alc711_address.version" = "SOUNDWIRE_VERSION_1_2"
-						register "alc711_address.class" = "MIPI_CLASS_SDCA"
-						register "alc711_address.part_id" = "MIPI_DEV_ID_REALTEK_ALC721"
-						# SoundWire Link 3 ID 1
-						device generic 3.1 on
-							probe AUDIO AUDIO_ALC721_SNDW
-						end
-					end
-				end
-			end
-			chip drivers/generic/max98357a
-				register "hid" = ""MX98360A""
-				register "sdmode_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E19)"
-				register "sdmode_delay" = "5"
-				device generic 0 on
-					probe AUDIO AUDIO_MAX98360_ALC5682I_I2S
-				end
-			end
-		end
+		device ref hda off end
 	end
 end
diff --git a/src/mainboard/google/ocelot/variants/ocelot/variant.c b/src/mainboard/google/ocelot/variants/ocelot/variant.c
index c7aa7aa605..34974da918 100644
--- a/src/mainboard/google/ocelot/variants/ocelot/variant.c
+++ b/src/mainboard/google/ocelot/variants/ocelot/variant.c
@@ -16,13 +16,11 @@ void variant_update_soc_chip_config(struct soc_intel_pantherlake_config *config)
 	config->cnvi_bt_core = false;
 	/* CNVi */
 	if (fw_config_probe(FW_CONFIG(WIFI, WIFI_CNVI_6)) ||
-		fw_config_probe(FW_CONFIG(WIFI, WIFI_CNVI_7))) {
+			fw_config_probe(FW_CONFIG(WIFI, WIFI_CNVI_7))) {
 		config->cnvi_wifi_core = true;
 		config->cnvi_bt_core = true;
 
-		if (fw_config_probe(FW_CONFIG(AUDIO, AUDIO_MAX98360_ALC5682I_I2S)) ||
-			fw_config_probe(FW_CONFIG(AUDIO, AUDIO_ALC722_SNDW)) ||
-			fw_config_probe(FW_CONFIG(AUDIO, AUDIO_ALC721_SNDW))) {
+		if (fw_config_probe(FW_CONFIG(AUDIO, AUDIO_ALC721_SNDW))) {
 			printk(BIOS_INFO, "BT audio offload configured.\n");
 			config->cnvi_bt_audio_offload = true;
 		}

From 8be95806a6f9a0ed61ff56e5a361d33c3201eb2d Mon Sep 17 00:00:00 2001
From: Nick Vaccaro <nvaccaro@google.com>
Date: Tue, 22 Apr 2025 13:48:04 -0700
Subject: [PATCH 0828/3886] mb/google/ocelot/var/ocelot: update gpios

Update gpio configuration to match ocelot schematic.

BUG=b:412736286
BRANCH=None
TEST=`emerge-ocelot coreboot` and verify it compiles without error.

Change-Id: Id2e2eb9fdf008445124e99393fe4b192ccb27f5d
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87423
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eran Mitrani <mitrani@google.com>
---
 .../google/ocelot/variants/ocelot/gpio.c      | 603 +++++++++---------
 1 file changed, 300 insertions(+), 303 deletions(-)

diff --git a/src/mainboard/google/ocelot/variants/ocelot/gpio.c b/src/mainboard/google/ocelot/variants/ocelot/gpio.c
index 1c1219228c..945cda97be 100644
--- a/src/mainboard/google/ocelot/variants/ocelot/gpio.c
+++ b/src/mainboard/google/ocelot/variants/ocelot/gpio.c
@@ -7,392 +7,389 @@
 
 /* Pad configuration in ramstage*/
 static const struct pad_config gpio_table[] = {
-	/* GPP_A00:     ESPI_IO0_EC_R */
-	/*  GPP_A00 : GPP_A00 ==> ESPI_IO0_EC_R configured on reset, do not touch */
-
-	/* GPP_A01:     ESPI_IO1_EC_R */
-	/*  GPP_A01 : GPP_A01 ==> ESPI_IO1_EC_R configured on reset, do not touch */
-
-	/* GPP_A02:     ESPI_IO2_EC_R */
-	/*  GPP_A02 : GPP_A02 ==> ESPI_IO2_EC_R configured on reset, do not touch */
-
-	/* GPP_A03:     ESPI_IO3_EC_R */
-	/*  GPP_A03 : GPP_A03 ==> ESPI_IO3_EC_R configured on reset, do not touch */
-
-	/* GPP_A04:     ESPI_CS0_EC_R_N */
-	/*  GPP_A04 : GPP_A04 ==> ESPI_CS0_HDR_L configured on reset, do not touch */
-
-	/* GPP_A05:     ESPI_CLK_EC_R */
-	/*  GPP_A05 : GPP_A05 ==> ESPI_CLK_HDR configured on reset, do not touch */
-
-	/* GPP_A06:     ESPI_RST_EC_R_N */
-	/*  GPP_A06 : GPP_A06 ==> ESPI_RST_HDR configured on reset, do not touch */
-
-	/* GPP_A09:     M.2_WWAN_FCP_OFF_N */
-	PAD_CFG_GPO(GPP_A09, 1, PLTRST),
-	/* GPP_A10:     M.2_WWAN_DISABLE_N */
+	/* GPP_A00:     ESPI_ASOC_IO0_R */
+	PAD_CFG_NF(GPP_A00, NONE, DEEP, NF1),
+	/* GPP_A01:     ESPI_SOC_IO1_R */
+	PAD_CFG_NF(GPP_A01, NONE, DEEP, NF1),
+	/* GPP_A02:     ESPI_SOC_IO2_R */
+	PAD_CFG_NF(GPP_A02, NONE, DEEP, NF1),
+	/* GPP_A03:     ESPI_SOC_IO3_R */
+	PAD_CFG_NF(GPP_A03, NONE, DEEP, NF1),
+	/* GPP_A04:     ESPI_SOC_CS_R_L */
+	PAD_CFG_NF(GPP_A04, NONE, DEEP, NF1),
+	/* GPP_A05:     ESPI_SOC_CLK_R */
+	PAD_CFG_NF(GPP_A05, NONE, DEEP, NF1),
+	/* GPP_A06:     ESPI_SOC_RST_L # */
+	PAD_CFG_NF(GPP_A06, NONE, DEEP, NF1),
+	/* GPP_A08:     SSD_PERST_L # */
+	PAD_CFG_GPO(GPP_A08, 1, PLTRST),
+	/* GPP_A09:     WWAN_EN */
+	PAD_CFG_GPO(GPP_A09, 0, PLTRST),
+	/* GPP_A10:     WWAN_RF_DISABLE_ODL */
 	PAD_CFG_GPO(GPP_A10, 1, PLTRST),
-	/* GPP_A11:     WLAN_RST_N */
+	/* GPP_A11:     WLAN_PERST_L */
 	PAD_CFG_GPO(GPP_A11, 1, PLTRST),
-	/* GPP_A12:     WIFI_WAKE_N */
+	/* GPP_A12:     WLAN_PCIE_WAKE_ODL */
 	PAD_CFG_GPI_SCI_LOW(GPP_A12, NONE, DEEP, LEVEL),
-	/* GPP_A15:     GPP_A15_DNX_FORCE_RELOAD */
-	PAD_CFG_NF(GPP_A15, NONE, DEEP, NF1),
-	/* GPP_A16:     BT_RF_KILL_N */
-	PAD_CFG_GPO(GPP_A16, 1, DEEP),
-	/* GPP_A17:     WIFI_RF_KILL_N */
-	PAD_CFG_GPO(GPP_A17, 1, DEEP),
+	/* GPP_A13:     NC */
+	PAD_NC(GPP_A13, NONE),
+	/* GPP_A15:     EN_SPK_PA */
+	PAD_CFG_GPO(GPP_A15, 1, DEEP),
 
-	/* GPP_B00:     USBC_SML_CLK_PD */
+	/* GPP_B00:     PMC_I2C_PD_SCL */
 	PAD_CFG_NF(GPP_B00, NONE, DEEP, NF1),
-	/* GPP_B01:     USBC_SML_DATA_PD */
+	/* GPP_B01:     PMC_I2C_PD_SDA */
 	PAD_CFG_NF(GPP_B01, NONE, DEEP, NF1),
-	/* GPP_B02:     ISH_I2C0_SDA_SNSR_HDR */
-	/* NOTE: IOSSTAGE: 'Ignore' for S0ix */
-	PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_B02, NONE, DEEP, NF3),
-	/* GPP_B03:     ISH_I2C0_SCL_SNSR_HDR */
-	/* NOTE: IOSSTAGE: 'Ignore' for S0ix */
-	PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_B03, NONE, DEEP, NF3),
-	/* GPP_B04:     ISH_GP_0_SNSR_HDR */
-	PAD_CFG_NF(GPP_B04, NONE, DEEP, NF4),
-	/* GPP_B05:     ISH_GP_1_SNSR_HDR */
+	/* GPP_B02:     SOC_I2C_AUDIO_SDA */
+	PAD_CFG_NF(GPP_B02, NONE, DEEP, NF8),
+	/* GPP_B03:     SOC_I2C_AUDIO_SCL */
+	PAD_CFG_NF(GPP_B03, NONE, DEEP, NF8),
+	/* GPP_B04:     GPP_B04_STRAP */
+	PAD_NC(GPP_B04, NONE),
+	/* GPP_B05:     EC_ISH_INT_ODL */
 	PAD_CFG_NF(GPP_B05, NONE, DEEP, NF4),
-	/* GPP_B06:     ISH_GP_2_SNSR_HDR */
-	PAD_CFG_NF(GPP_B06, NONE, DEEP, NF4),
-	/* GPP_B07:     ISH_GP_3_SNSR_HDR */
-	PAD_CFG_NF(GPP_B07, NONE, DEEP, NF4),
-	/* GPP_B08:     ISH_GP_4_SNSR_HDR */
-	PAD_CFG_NF(GPP_B08, NONE, DEEP, NF4),
-	/* GPP_B09:     M2_GEN4_SSD_RESET_N */
+	/* GPP_B06:     MEM_STRAP_2 */
+	PAD_CFG_GPI(GPP_B06, NONE, DEEP),
+	/* GPP_B07:     WWAN_SAR_DETECT_ODL */
+	/* FIXME */
+	PAD_CFG_GPI(GPP_B07, NONE, DEEP),
+	/* GPP_B08:     MEM_STRAP_3 */
+	PAD_CFG_GPI(GPP_B08, NONE, DEEP),
+	/* GPP_B09:     BT_DISABLE_L */
 	PAD_CFG_GPO(GPP_B09, 1, PLTRST),
-	/* GPP_B10:     GEN4_SSD_PWREN */
-	PAD_CFG_GPO(GPP_B10, 1, PLTRST),
-	/* GPP_B11:     MOD_TCSS1_DISP_HPD3 */
-	PAD_CFG_NF(GPP_B11, NONE, DEEP, NF2),
-	/* GPP_B12:     PM_SLP_S0_N */
+	/* GPP_B10:     NC */
+	PAD_NC(GPP_B10, NONE),
+	/* GPP_B12:     SLR_SO_R_L */
 	PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1),
-	/* GPP_B13:     PLT_RST_N */
+	/* GPP_B13:     PLT_RST_L */
 	PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1),
-	/* GPP_B14:     MOD_TCSS2_DISP_HPD4 */
+	/* GPP_B14:     HDMI_HPD_STRAP */
 	PAD_CFG_NF(GPP_B14, NONE, DEEP, NF2),
-	/* GPP_B15:     MOD_TCSS_USB_TYP_A_OC3_N */
-	PAD_CFG_NF(GPP_B15, NONE, DEEP, NF1),
-	/* GPP_B16:     GEN5_SSD_PWREN */
-	PAD_CFG_GPO(GPP_B16, 1, PLTRST),
-	/* GPP_B17:     Not used */
-	PAD_NC(GPP_B17, NONE),
-	/* GPP_B18:     ISH_I2C2_SDA_SNSR_HDR */
-	/* NOTE: IOSSTAGE: 'Ignore' for S0ix */
-	PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_B18, NONE, DEEP, NF1),
-	/* GPP_B19:     ISH_I2C2_SCL_SNSR_HDR */
-	/* NOTE: IOSSTAGE: 'Ignore' for S0ix */
-	PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_B19, NONE, DEEP, NF1),
-	/* GPP_B20:     M.2_WWAN_RST_N */
+	/* GPP_B16:     NC */
+	PAD_NC(GPP_B16, NONE),
+	/* GPP_B17:     GSC_SOC_INT_ODL */
+	PAD_CFG_GPI(GPP_B17, NONE, DEEP),
+	/* GPP_B18:     ISH_I2C_SENSOR_SDA */
+	PAD_CFG_NF(GPP_B18, NONE, DEEP, NF1),
+	/* GPP_B19:     ISH_I2C_SENSOR_SCL */
+	PAD_CFG_NF(GPP_B19, NONE, DEEP, NF1),
+	/* GPP_B20:     WWAN_RST_ODL */
 	PAD_CFG_GPO(GPP_B20, 1, PLTRST),
-	/* GPP_B21:     TCP_RETIMER_FORCE_PWR */
+	/* GPP_B21:     USB_RT_FORCE_PWR */
+	/* FIXME */
 	PAD_CFG_GPO(GPP_B21, 0, DEEP),
-	/* GPP_B22:     ISH_GP_5_SNSR_HDR */
+	/* GPP_B22:     ISH_ACCEL_DB_INT_L */
 	PAD_CFG_NF(GPP_B22, NONE, DEEP, NF4),
-	/* GPP_B23:     ISH_GP_6_SNSR_HDR */
-	PAD_CFG_NF(GPP_B23, NONE, DEEP, NF4),
-	/* GPP_B24:     ESPI_ALERT0_EC_R_N */
-	PAD_NC(GPP_B24, NONE),
+	/* GPP_B23:     GPP_B23_STRAP */
+	PAD_NC(GPP_B23, NONE),
+	/* GPP_B24:     EC_SOC_INT_ODL */
+	PAD_CFG_GPI(GPP_B24, NONE, DEEP),
+	/* GPP_B25:     GPP_B23_STRAP */
+	PAD_NC(GPP_B25, NONE),
 
-	/* GPP_C00:     GPP_C0_SMBCLK */
-	PAD_CFG_NF(GPP_C00, NONE, DEEP, NF1),
-	/* GPP_C01:     GPP_C1_SMBDATA */
-	PAD_CFG_NF(GPP_C01, NONE, DEEP, NF1),
-	/* GPP_C02:     Not used */
+	/* GPP_C00:     NC */
+	PAD_NC(GPP_C00, NONE),
+	/* GPP_C01:     NC */
+	PAD_NC(GPP_C01, NONE),
+	/* GPP_C02:     GPP_C02_STRAP */
 	PAD_NC(GPP_C02, NONE),
-	/* GPP_C03:     TCP_LAN_SML0_SCL_R */
+	/* GPP_C03:     TP_SMB_SML0_CLK */
 	PAD_CFG_NF(GPP_C03, NONE, DEEP, NF1),
-	/* GPP_C04:     TCP_LAN_SML0_SDA_R */
+	/* GPP_C04:     TP_SMB_SML0_DAT */
 	PAD_CFG_NF(GPP_C04, NONE, DEEP, NF1),
-	/* GPP_C06:     SML1_CLK */
-	PAD_CFG_NF(GPP_C06, NONE, DEEP, NF1),
-	/* GPP_C07:     SML1_DATA */
-	PAD_CFG_NF(GPP_C07, NONE, DEEP, NF1),
-	/* GPP_C09:     CLKREQ0_X8_GEN5_DT_CEM_SLOT_N */
+	/* GPP_C05:     GPP_C05_STRAP */
+	PAD_NC(GPP_C05, NONE),
+	/* GPP_C06:     NC */
+	PAD_NC(GPP_C06, NONE),
+	/* GPP_C07:     NC */
+	PAD_NC(GPP_C07, NONE),
+	/* GPP_C08:     ASLP_S0_GATE_R */
+	/* FIXME */
+	PAD_CFG_GPO(GPP_C08, 0, DEEP),
+	/* GPP_C09:     WLAN_PCIE_CLKREQ_ODL */
 	PAD_CFG_NF(GPP_C09, NONE, DEEP, NF1),
-	/* GPP_C10:     CLKREQ1_X4_GEN5_M2_SSD_N */
-	PAD_CFG_NF(GPP_C10, NONE, DEEP, NF1),
-	/* GPP_C11:     CLKREQ2_X1_GEN4_DT_CEM_SLOT_N */
+	/* GPP_C10:     WIFI_DISABLE_L */
+	PAD_CFG_GPO(GPP_C10, 1, PLTRST),
+	/* GPP_C11:     OPT_PCIE_CLKREQ_ODL */
 	PAD_CFG_NF(GPP_C11, NONE, DEEP, NF1),
-	/* GPP_C12:     CLKREQ3_X1_GEN1_GBE_LAN_N */
+	/* GPP_C12:     SSD_PCIE_CLKREQ_ODL */
 	PAD_CFG_NF(GPP_C12, NONE, DEEP, NF1),
-	/* GPP_C13:     CLKREQ4_X1_GEN4_M2_WLAN_N */
-	PAD_CFG_NF(GPP_C13, NONE, DEEP, NF1),
-	/* GPP_C14:     CLKREQ5_X1_GEN4_M2_WWAN_N */
-	PAD_CFG_NF(GPP_C14, NONE, DEEP, NF1),
-	/* GPP_C16:     TBT_LSX0_TXD  */
+	/* GPP_C13:     NC */
+	PAD_NC(GPP_C13, NONE),
+	/* GPP_C14:     NC */
+	PAD_NC(GPP_C14, NONE),
+	/* GPP_C15:     SOC_FP_RST_STRAP_L */
+	PAD_CFG_GPO(GPP_C15, 1, DEEP),
+	/* GPP_C16:     USB_C0_LSX_TX  */
 	PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1),
-	/* GPP_C17:     TBT_LSX0_RXD  */
+	/* GPP_C17:     USB_C0_LSX_RX  */
 	PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1),
-	/* GPP_C18:     TBT_LSX1_TXD  */
+	/* GPP_C18:     USB_C1_LSX_TX  */
 	PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1),
-	/* GPP_C19:     TBT_LSX1_RXD */
+	/* GPP_C19:     USB_C1_LSX_TX */
 	PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1),
-	/* GPP_C20:     MOD_TCSS1_LS_TX_DDC_SCL */
+	/* GPP_C20:     USB_C1_LSX_RX */
 	PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1),
-	/* GPP_C21:     MOD_TCSS1_LS_RX_DDC_SDA */
-	PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1),
-	/* GPP_C22:     MOD_TCSS2_LS_TX_DDC_SCL */
+	/* GPP_C22:     DDIB_HDMI_CTRLCLK */
 	PAD_CFG_NF(GPP_C22, NONE, DEEP, NF2),
-	/* GPP_C23:     MOD_TCSS2_LS_RX_DDC_SDA */
+	/* GPP_C23:     DDIB_HDMI_CTRLDATA */
 	PAD_CFG_NF(GPP_C23, NONE, DEEP, NF2),
 
-	/* GPP_D00:     IMGCLKOUT_1 */
-	PAD_CFG_NF(GPP_D00, NONE, DEEP, NF1),
-	/* GPP_D02:     Not used */
-	PAD_NC(GPP_D02, NONE),
-	/* GPP_D03:     M.2_WWAN_PERST_GPIO_N */
-	PAD_CFG_GPO(GPP_D03, 1, PLTRST),
-	/* GPP_D04:     IMGCLKOUT_0 */
-	PAD_CFG_NF(GPP_D04, NONE, DEEP, NF1),
-	/* GPP_D05:     disable ISH_UART0_RXD */
-	PAD_NC(GPP_D05, NONE),
+	/* GPP_D01:     NC */
+	PAD_NC(GPP_D01, NONE),
+	/* GPP_D02:     SOC_WP_OD */
+	PAD_CFG_GPI(GPP_D02, NONE, DEEP),
+	/* GPP_D03:     OPT_PCIE_WAKE_ODL */
+	PAD_CFG_GPI_SCI_LOW(GPP_D03, NONE, DEEP, LEVEL),
+	/* GPP_D05:     UART_ISH_RX_DBG_TX */
+	PAD_CFG_NF(GPP_D05, NONE, DEEP, NF2),
+	/* GPP_D06:     UART_ISH_TX_DBG_RX */
+	PAD_CFG_NF(GPP_D06, NONE, DEEP, NF2),
 	/* GPP_D07:     NC */
 	PAD_NC(GPP_D07, NONE),
 	/* GPP_D08:     NC */
 	PAD_NC(GPP_D08, NONE),
-	/* GPP_D09:     PEG_SLOT_RST_N */
-	PAD_CFG_GPO(GPP_D09, 1, PLTRST),
-	/* GPP_D10:     HDA_BCLK */
+	/* GPP_D09:     I2S0_MCLK_R */
+	PAD_CFG_NF(GPP_D09, NONE, DEEP, NF2),
+	/* GPP_D10:     HDA_BCLK_I2S0_SCLK */
 	PAD_CFG_NF(GPP_D10, NONE, DEEP, NF1),
-	/* GPP_D11:     HDA_SYNC */
+	/* GPP_D11:     HDA_SYNC_I2S0_SFRM */
 	PAD_CFG_NF(GPP_D11, NONE, DEEP, NF1),
-	/* GPP_D12:     HDA_SDO */
+	/* GPP_D12:     HDA_SD0_I2S0_TXD_STRAP */
 	PAD_CFG_NF(GPP_D12, NONE, DEEP, NF1),
-	/* GPP_D13:     HDA_SDI0 */
+	/* GPP_D13:     HDA_SDI0_I2S0_RDX */
 	PAD_CFG_NF(GPP_D13, NONE, DEEP, NF1),
-	/* GPP_D14:     COINLESS_MODE_SELECT */
-	PAD_CFG_GPI_TRIG_OWN(GPP_D14, NONE, PLTRST, LEVEL, ACPI),
-	/* GPP_D15:     SPI_TPM_INT_N */
-	PAD_CFG_GPI_APIC_LOCK(GPP_D15, NONE, LEVEL, INVERT, LOCK_CONFIG),
-	/* GPP_D16:     HDA_RST_N_HDR */
-	PAD_CFG_NF(GPP_D16, NONE, DEEP, NF1),
-	/* GPP_D17:     HDA_SDI1_HDR */
-	PAD_CFG_NF(GPP_D17, NONE, DEEP, NF1),
-	/* GPP_D18:     CLKREQ6_X4_GEN4_M2_SSD_N */
-	PAD_CFG_NF(GPP_D18, NONE, DEEP, NF1),
-	/* GPP_D20:     CSE_EARLY_SW */
-	PAD_CFG_GPI_SCI_HIGH(GPP_D20, NONE, DEEP, LEVEL),
-	/* GPP_D21:     NC */
-	PAD_NC(GPP_D21, NONE),
-	/* GPP_D22:     BPKI3C_SDA */
-	PAD_CFG_NF(GPP_D22, NONE, DEEP, NF1),
-	/* GPP_D23:     BPKI3C_SCL */
-	PAD_CFG_NF(GPP_D23, NONE, DEEP, NF1),
-	/* GPP_D24:     PEG_SLOT_WAKE_N */
-	PAD_CFG_GPI_SCI_LOW(GPP_D24, NONE, DEEP, LEVEL),
-	/* GPP_D25:     X4_SLOT_WAKE_N */
-	PAD_CFG_GPI_SCI_LOW(GPP_D25, NONE, DEEP, LEVEL),
+	/* GPP_D16:     NC */
+	PAD_NC(GPP_D16, NONE),
+	/* GPP_D17:     NC */
+	PAD_NC(GPP_D17, NONE),
+	/* GPP_D19:     SOC_TCHSCR_REPORT_EN */
+	PAD_CFG_GPO(GPP_D18, 0, DEEP),
+	/* GPP_D21:     SOC_UFS_REFCLK */
+	PAD_CFG_NF(GPP_D21, NONE, DEEP, NF1),
 
-	/* GPP_E01:     CRD2_RST_N */
+	/* GPP_E01:     EN_WWAN_PWR */
 	PAD_CFG_GPO(GPP_E01, 1, PLTRST),
-	/* GPP_E02:     WWAN_WAKE_GPIO_N  */
-	PAD_CFG_GPI_SCI_LOW(GPP_E02, NONE, DEEP, LEVEL),
-	/* GPP_E03:     M2_GEN5_SSD_RESET_N */
-	PAD_CFG_GPO(GPP_E03, 1, PLTRST),
-	/* GPP_E06:     SECURE_CAM_SW */
-	PAD_CFG_GPI_TRIG_OWN(GPP_E06, NONE, PLTRST, LEVEL, ACPI),
-#if CONFIG(BOARD_GOOGLE_OCELOT)
-	/* GPP_E07:     Not used */
+	/* GPP_E02:     NC */
+	PAD_NC(GPP_E02, NONE),
+	/* GPP_E03:     OPT_PERST_L */
+	PAD_CFG_GPO(GPP_E03, 1, DEEP),
+	/* GPP_E05:     EN_PWR_FP */
+	PAD_CFG_GPO(GPP_E05, 0, PLTRST),
+	/* GPP_E06:     GPP_E06_STRAP */
+	PAD_NC(GPP_E06, NONE),
+	/* GPP_E07:     NC */
 	PAD_NC(GPP_E07, NONE),
-#else
-	/* GPP_E07 : [] ==> EC_SOC_INT_ODL */
-	PAD_CFG_GPI_APIC_LOCK(GPP_E07, NONE, LEVEL, INVERT, LOCK_CONFIG),
-#endif
-	/* GPP_E08:     Not used */
+	/* GPP_E08:     NC */
 	PAD_NC(GPP_E08, NONE),
-	/* GPP_E09:     USB_RD_FP_CONN_12_OC0_N */
+	/* GPP_E09:     USB_A_OC_ODL */
 	PAD_CFG_NF(GPP_E09, NONE, DEEP, NF1),
-	/* GPP_E10:     CRD1_RST_N */
-	PAD_CFG_GPO(GPP_E10, 1, PLTRST),
-	/* GPP_E11:     THC0_SPI1_CLK_TCH_PNL1 */
-	PAD_CFG_NF(GPP_E11, NONE, DEEP, NF3),
-	/* GPP_E12:     THC0_SPI1_IO_0_I2C4_SCL_TCH_PNL1 */
-	PAD_CFG_NF(GPP_E12, NONE, DEEP, NF3),
-	/* GPP_E13:     THC0_SPI1_IO_1_I2C4_SDA_TCH_PNL1 */
-	PAD_CFG_NF(GPP_E13, NONE, DEEP, NF3),
-	/* GPP_E14:     THC0_SPI1_IO_2_TCH_PNL1 */
-	PAD_CFG_NF(GPP_E14, NONE, DEEP, NF3),
-	/* GPP_E15:     THC0_SPI1_IO_3_TCH_PNL1 */
-	PAD_CFG_NF(GPP_E15, NONE, DEEP, NF3),
-	/* GPP_E16:     THC0_SPI1_RST_N_TCH_PNL1 */
-	/* THC NOTE: use GPO instead of GPO for THC0 Rst */
-	PAD_CFG_GPO(GPP_E16, 1, DEEP),
-	/* GPP_E17:     THC0_SPI1_CS0_N_TCH_PNL1 */
-	PAD_CFG_NF(GPP_E17, NONE, DEEP, NF3),
-	/* GPP_E18:     THC0_SPI1_INT_N_TCH_PNL1 */
+	/* GPP_E10:     SD_PE_PRSNT_L */
+	PAD_CFG_GPI(GPP_E10, NONE, DEEP),
+	/* GPP_E11:     SPI_SOC_CLK_FP_R */
+	PAD_CFG_NF(GPP_E11, NONE, DEEP, NF5),
+	/* GPP_E12:     SOC_I2C_TCHPAD_SCL */
+	PAD_CFG_NF(GPP_E12, NONE, DEEP, NF1),
+	/* GPP_E13:     SOC_I2C_TCHPAD_SCL */
+	PAD_CFG_NF(GPP_E13, NONE, DEEP, NF1),
+	/* GPP_E14:     NC */
+	PAD_NC(GPP_E14, NONE),
+	/* GPP_E15:     NC */
+	PAD_NC(GPP_E15, NONE),
+	/* GPP_E16:     NC */
+	PAD_NC(GPP_E16, NONE),
+	/* GPP_E17:     SPI_SOC_CS_FP_R_L */
+	PAD_CFG_NF(GPP_E17, NONE, DEEP, NF5),
+	/* GPP_E18:     SOC_TCHPAD_INT_ODL */
 	PAD_CFG_NF(GPP_E18, NONE, DEEP, NF3),
-	/* GPP_E21:     I2C_PMC_PD_INT_N */
+	/* GPP_E19:     FP_SOC_INT_L */
+	PAD_CFG_GPI_SCI_LOW(GPP_E19, NONE, DEEP, LEVEL),
+	/* GPP_E20:     SOC_FP_FW_UP */
+	PAD_CFG_GPO(GPP_E20, 0, DEEP),
+	/* GPP_E21:     PMC_I2C_PD_INT_ODL */
 	PAD_CFG_NF(GPP_E21, NONE, DEEP, NF1),
-	/* GPP_E22:     THC0_SPI1_DSYNC */
-	PAD_CFG_NF(GPP_E22, NONE, DEEP, NF3),
+	/* GPP_E22:     NC */
+	PAD_NC(GPP_E22, NONE),
 
-	/* GPP_F00:     M.2_CNV_BRI_DT_BT_UART2_RTS_N */
-	/* NOTE: IOSSTAGE: 'Ignore' for S0ix */
-	PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_F00, NONE, DEEP, NF1),
-	/* GPP_F01:     M.2_CNV_BRI_RSP_BT_UART2_RXD */
-	/* NOTE: IOSSTAGE: 'Ignore' for S0ix */
-	PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_F01, NONE, DEEP, NF1),
-	/* GPP_F02:     M.2_CNV_RGI_DT_BT_UART2_TXD */
-	/* NOTE: IOSSTAGE: 'Ignore' for S0ix */
-	PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_F02, NONE, DEEP, NF1),
-	/* GPP_F03:     M.2_CNV_RGI_RSP_BT_UART2_CTS_N */
-	/* NOTE: IOSSTAGE: 'Ignore' for S0ix */
-	PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_F03, NONE, DEEP, NF1),
-	/* GPP_F04:     CNV_RF_RESET_R_N */
-	/* NOTE: IOSSTAGE: 'Ignore' for S0ix */
-	PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_F04, NONE, DEEP, NF1),
-	/* GPP_F05:     CRF_CLKREQ_R */
-	/* NOTE: IOSSTAGE: 'Ignore' for S0ix */
-	PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_F05, NONE, DEEP, NF3),
-	/* GPP_F06:     WLAN_WWAN_COEX3 */
+	/* GPP_F00:     CNV_BRI_DT_R */
+	PAD_CFG_NF(GPP_F00, NONE, DEEP, NF1),
+	/* GPP_F01:     CNV_BRI_RSP */
+	PAD_CFG_NF(GPP_F01, NONE, DEEP, NF1),
+	/* GPP_F02:     WLAN_CNVI_RGI_DT_STRAP_R */
+	PAD_CFG_NF(GPP_F02, NONE, DEEP, NF1),
+	/* GPP_F03:     CNV_RGI_RSP */
+	PAD_CFG_NF(GPP_F03, NONE, DEEP, NF1),
+	/* GPP_F04:     CNV_RF_RST_L */
+	PAD_CFG_NF(GPP_F04, NONE, DEEP, NF1),
+	/* GPP_F05:     CNV_CLKREQ0 */
+	PAD_CFG_NF(GPP_F05, NONE, DEEP, NF3),
+	/* GPP_F06:     COEX3_WWAN_WLAN */
 	PAD_CFG_NF(GPP_F06, NONE, DEEP, NF1),
-	/* GPP_F07:     IMGCLKOUT_2 */
-	PAD_CFG_NF(GPP_F07, NONE, DEEP, NF2),
-	/* GPP_F08:     TCH_PNL1_PWR_EN */
+	/* GPP_F07:     EN_PP3300_SD */
+	PAD_CFG_GPO(GPP_F07, 1, PLTRST),
+	/* GPP_F08:     EN_PP3300_TCHSCR */
 	PAD_CFG_GPO(GPP_F08, 1, PLTRST),
-	/* GPP_F09:     NC */
-	PAD_NC(GPP_F09, NONE),
-	/* GPP_F10:     PEG_SLOT_PWR_EN_N */
-	PAD_CFG_GPO(GPP_F10, 0, PLTRST),
-	/* GPP_F11:     MOD_TCSS2_TYP_A_VBUS_EN */
-	PAD_CFG_GPO(GPP_F11, 1, DEEP),
-	/* GPP_F12:     THC_I2C1_SCL_TCH_PAD */
-	PAD_CFG_NF(GPP_F12, NONE, DEEP, NF8),
-	/* GPP_F13:     THC_I2C1_SDA_TCH_PAD */
-	PAD_CFG_NF(GPP_F13, NONE, DEEP, NF8),
-	/* GPP_F17:     Not used */
-	PAD_CFG_GPI_INT(GPP_F17, NONE, PLTRST, EDGE_BOTH),
-	/* GPP_F19:     GPP_PRIVACY_LED_CAM2 */
-	PAD_CFG_GPO(GPP_F19, 0, PLTRST),
-	/* GPP_F20:     GPP_PRIVACY_LED_CAM1_CVS_HST_WAKE */
+	/* GPP_F09:     SOC_UFS_RST_L */
+	PAD_CFG_GPO(GPP_F09, 0, PLTRST),
+	/* GPP_F10:     ISH_ACCEL_MB_INT_L */
+	PAD_CFG_NF(GPP_F10, NONE, PLTRST, NF8),
+	/* GPP_F11:     SPI_TCHSCR_CLK */
+	PAD_CFG_NF(GPP_F11, NONE, DEEP, NF3),
+	/* GPP_F12:     SPI_I2C_TCHSCR_MOSI_SCL */
+	PAD_CFG_NF(GPP_F12, NONE, DEEP, NF3),
+	/* GPP_F13:     SPI_I2C_TCHSCR_MISO_SDA */
+	PAD_CFG_NF(GPP_F13, NONE, DEEP, NF3),
+	/* GPP_F14:     SPI_SOC_D0_FP_D1_R */
+	PAD_CFG_NF(GPP_F14, NONE, DEEP, NF8),
+	/* GPP_F15:     SPI_SOC_D1_FP_D0 */
+	PAD_CFG_NF(GPP_F15, NONE, DEEP, NF8),
+	/* GPP_F16:     THCSCR_RST_L */
+	PAD_CFG_NF(GPP_F16, NONE, DEEP, NF3),
+	/* GPP_F17:     SPI_THCSCR_CS_L */
+	PAD_CFG_NF(GPP_F17, NONE, DEEP, NF3),
+	/* GPP_F18:     TCHSCR_INT_ODL */
+	PAD_CFG_NF(GPP_F18, NONE, DEEP, NF3),
+	/* GPP_F19:     GPP_F19_STRAP */
+	PAD_NC(GPP_F19, NONE),
+	/* GPP_F20:     EC_SOC_REC_SWITCH_ODL */
 	PAD_CFG_GPO(GPP_F20, 0, PLTRST),
-	/* GPP_F22:     THC1_SPI2_DSYNC */
-	PAD_CFG_NF(GPP_F22, NONE, DEEP, NF3),
+	/* GPP_F22:     NC */
+	PAD_NC(GPP_F22, NONE),
+	/* GPP_F23:     TP_ISH_LID_OPEN */
+	PAD_CFG_NF(GPP_F23, NONE, PLTRST, NF8),
 
-	/* GPP_H00:     Not used */
-	PAD_NC(GPP_H00, NONE),
-	/* GPP_H01:     CRD_CAM_STROBE */
-	PAD_CFG_GPO(GPP_H01, 0, PLTRST),
-	/* GPP_H02:     DEBUG_TRACE_PNP */
-	PAD_CFG_GPO(GPP_H02, 1, PLTRST),
-	/* GPP_H03:     MIC MUTE */
-	PAD_CFG_NF(GPP_H03, NONE, DEEP, NF1),
-	/* GPP_H04:     I2C2_SDA_CAM_FLSH */
-	PAD_CFG_NF(GPP_H04, NONE, DEEP, NF1),
-	/* GPP_H05:     I2C2_SCL_CAM_FLSH */
-	PAD_CFG_NF(GPP_H05, NONE, DEEP, NF1),
-	/* GPP_H06:     I2C3_SDA_PSS */
-	PAD_CFG_NF(GPP_H06, NONE, DEEP, NF1),
-	/* GPP_H07:     I2C3_SCL_PSS */
-	PAD_CFG_NF(GPP_H07, NONE, DEEP, NF1),
-	/* GPP_H08:     UART0_BUF_RXD */
+	/* GPP_H02:     GPP_H02_STRAP */
+	PAD_NC(GPP_H02, NONE),
+	/* GPP_H03:     NC */
+	PAD_NC(GPP_H03, NONE),
+	/* GPP_H04:     COEX1_SOC_RX_WWAN_RX_WLAN_TX */
+	PAD_CFG_NF(GPP_H04, NONE, DEEP, NF2),
+	/* GPP_H05:     COEX1_SOC_TX_WWAN_TX_WLAN_RX */
+	PAD_CFG_NF(GPP_H05, NONE, DEEP, NF2),
+	/* GPP_H06:     UART_SOC_RX_FP_TX */
+	PAD_CFG_NF(GPP_H06, NONE, DEEP, NF2),
+	/* GPP_H07:     UART_SOC_TX_FP_RX */
+	PAD_CFG_NF(GPP_H07, NONE, DEEP, NF2),
+	/* GPP_H08:     UART_SOC_RX_DBG_TX */
 	PAD_CFG_NF(GPP_H08, NONE, DEEP, NF1),
-	/* GPP_H09:     UART0_BUF_TXD */
+	/* GPP_H09:     UART_SOC_TX_DBG_RX */
 	PAD_CFG_NF(GPP_H09, NONE, DEEP, NF1),
-	/* GPP_H10:     UART0_BUF_RTS */
-	PAD_CFG_NF(GPP_H10, NONE, DEEP, NF1),
-	/* GPP_H11:     UART0_BUF_CTS */
-	PAD_CFG_NF(GPP_H11, NONE, DEEP, NF1),
-	/* GPP_H13:     CPU_C10_GATE_N_R */
+	/* GPP_H10:     TP_ISH_TABLET_MODE */
+	PAD_CFG_NF(GPP_H10, NONE, DEEP, NF8),
+	/* GPP_H11:     TP_ISH_GP11 */
+	PAD_CFG_NF(GPP_H11, NONE, DEEP, NF8),
+	/* GPP_H13:     TP_PROC_C10_GATE_L */
 	PAD_CFG_NF(GPP_H13, NONE, DEEP, NF1),
 	/* GPP_H14:     NC */
 	PAD_NC(GPP_H14, NONE),
 	/* GPP_H15:     NC */
 	PAD_NC(GPP_H15, NONE),
-	/* GPP_H16:     WWAN_PWREN */
-	PAD_CFG_GPO(GPP_H16, 1, PLTRST),
-	/* GPP_H17:     MIC MUTE LED */
-	PAD_CFG_NF(GPP_H17, NONE, DEEP, NF1),
-	/* GPP_H19:     I3C0_SDA_HDR */
-	PAD_CFG_NF(GPP_H19, NONE, DEEP, NF2),
-	/* GPP_H20:     I3C0_SCL_HDR */
-	PAD_CFG_NF(GPP_H20, NONE, DEEP, NF2),
-	/* GPP_H21:     I2C1_SDA_I3C1_SDA_CAM_FLSH_CVS */
+	/* GPP_H17:     HP_INT_L */
+	PAD_CFG_GPI_SCI_LOW(GPP_H17, NONE, DEEP, LEVEL),
+	/* GPP_H18:     EN_PP3300_SSD */
+	PAD_CFG_GPO(GPP_H18, 1, DEEP),
+	/* GPP_H19:     TP_SOC_I2C0_I3C0SDA */
+	PAD_CFG_NF(GPP_H19, NONE, DEEP, NF1),
+	/* GPP_H20:     TP_SOC_I2C0_I3C0SCL */
+	PAD_CFG_NF(GPP_H20, NONE, DEEP, NF1),
+	/* GPP_H21:     SOC_I2C_GSC_SDA */
 	PAD_CFG_NF(GPP_H21, NONE, DEEP, NF1),
-	/* GPP_H22:     I2C1_SCL_I3C1_SCL_CAM_FLSH_CVS */
+	/* GPP_H22:     SOC_I2C_GSC_SCL */
 	PAD_CFG_NF(GPP_H22, NONE, DEEP, NF1),
+	/* GPP_H23:     MEM_STRAP_0 */
+	PAD_CFG_GPI(GPP_H23, NONE, DEEP),
+	/* GPP_H24:     MEM_STRAP_1 */
+	PAD_CFG_GPI(GPP_H24, NONE, DEEP),
 
-	/* GPP_S00:     SNDW3_CLK_CODEC */
+	/* GPP_S00:     SDW3_CLK_I2S1_TXD */
 	PAD_CFG_NF(GPP_S00, NONE, DEEP, NF1),
-	/* GPP_S01:     SNDW3_DATA0_CODEC */
+	/* GPP_S01:     SNDW3_DAT0 */
 	PAD_CFG_NF(GPP_S01, NONE, DEEP, NF1),
-	/* GPP_S02:     SNDW3_DATA1_CODEC */
+	/* GPP_S02:     SNDW3_DAT1_I2S1_SCLK */
 	PAD_CFG_NF(GPP_S02, NONE, DEEP, NF1),
-	/* GPP_S03:     SNDW3_DATA2_CODEC */
+	/* GPP_S03:     SNDW3_DAT2_I2S1_SFRM */
 	PAD_CFG_NF(GPP_S03, NONE, DEEP, NF1),
-	/* GPP_S04:     SNDW2_CLK */
-	PAD_CFG_NF(GPP_S04, NONE, DEEP, NF2),
-	/* GPP_S05:     SNDW2_DATA0 */
-	PAD_CFG_NF(GPP_S05, NONE, DEEP, NF2),
-	/* GPP_S06:     SNDW1_CLK */
-	PAD_CFG_NF(GPP_S06, NONE, DEEP, NF3),
-	/* GPP_S07:     SNDW1_DATA0 */
-	PAD_CFG_NF(GPP_S07, NONE, DEEP, NF3),
+	/* GPP_S04:     DMIC_CLK0_R */
+	PAD_CFG_NF(GPP_S04, NONE, DEEP, NF5),
+	/* GPP_S05:     DMIC_DATA0_EDP */
+	PAD_CFG_NF(GPP_S05, NONE, DEEP, NF5),
+	/* GPP_S06:     NC */
+	PAD_NC(GPP_S06, NONE),
+	/* GPP_S07:     NC */
+	PAD_NC(GPP_S07, NONE),
 
-	/* GPP_V00:     PM_BATLOW_N */
+	/* GPP_V00:     BATLOW_L */
 	PAD_CFG_NF(GPP_V00, NONE, DEEP, NF1),
-	/* GPP_V01:     BC_ACOK_MCP */
+	/* GPP_V01:     EC_AC_PRESENT_OD */
 	PAD_CFG_NF(GPP_V01, NONE, DEEP, NF1),
-	/* GPP_V02:     LANWAKE_N_R */
-	PAD_CFG_NF(GPP_V02, NONE, DEEP, NF1),
-	/* GPP_V03:     PWRBTN_MCP_N */
+	/* GPP_V02:     EC_SOC_WAKE_ODL */
+	/* FIXME */
+	PAD_CFG_GPI_IRQ_WAKE(GPP_V02, NONE, PLTRST, LEVEL, INVERT),
+	/* GPP_V03:     EC_SOC_PWR_BTN_ODL */
 	PAD_CFG_NF(GPP_V03, NONE, DEEP, NF1),
-	/* GPP_V04:     PM_SLP_S3_N */
+	/* GPP_V04:     SLP_S3_L */
 	PAD_CFG_NF(GPP_V04, NONE, DEEP, NF1),
-	/* GPP_V05:     PM_SLP_S4_N */
+	/* GPP_V05:     SLP_S4_L */
 	PAD_CFG_NF(GPP_V05, NONE, DEEP, NF1),
-	/* GPP_V06:     PM_SLP_A_N */
+	/* GPP_V06:     TP_SLP_A_L */
 	PAD_CFG_NF(GPP_V06, NONE, DEEP, NF1),
-	/* GPP_V07:     Not used */
-	PAD_NC(GPP_V07, NONE),
-	/* GPP_V08:     SLP_WLAN_N */
-	PAD_CFG_NF(GPP_V08, NONE, DEEP, NF1),
-	/* GPP_V09:     PM_SLP_S5_N */
+	/* GPP_V07:     SOC_WLAN_SUSCLK */
+	PAD_CFG_NF(GPP_V07, NONE, DEEP, NF1),
+	/* GPP_V08:     NC */
+	PAD_NC(GPP_V08, NONE),
+	/* GPP_V09:     SLP_S5_L */
 	PAD_CFG_NF(GPP_V09, NONE, DEEP, NF1),
-	/* GPP_V10:     LANPHYPC_R_N */
-	PAD_CFG_NF(GPP_V10, NONE, DEEP, NF1),
-	/* GPP_V11:     PM_SLP_LAN_N */
+	/* GPP_V10:     NC */
+	PAD_NC(GPP_V10, NONE),
+	/* GPP_V11:     TP_SLP_LAN_L */
 	PAD_CFG_NF(GPP_V11, NONE, DEEP, NF1),
-	/* GPP_V12:     WAKE_N */
+	/* GPP_V12:     PCH_WAKE_L */
 	PAD_CFG_NF(GPP_V12, NONE, DEEP, NF1),
-	/* GPP_V13:     GPP_V13_CATERR_N */
-	PAD_CFG_NF(GPP_V13, NONE, DEEP, NF1),
-	/* GPP_V14:     GPP_V14_FORCEPR_N */
-	PAD_CFG_NF(GPP_V14, NONE, DEEP, NF1),
-	/* GPP_V15:     GPP_V15_THERMTRIP_N */
-	PAD_CFG_NF(GPP_V15, NONE, DEEP, NF1),
-	/* GPP_V16:     GPP_V16_VCCST_EN */
+	/* GPP_V16:     EN_VCCST */
 	PAD_CFG_NF(GPP_V16, NONE, DEEP, NF1),
-	/* GPP_V17:     TCP_RT_S0IX_ENTRY_EXIT_N */
-	PAD_CFG_GPO(GPP_V17, 1, DEEP),
 };
 
 /* Early pad configuration in bootblock */
 static const struct pad_config early_gpio_table[] = {
-	/* GPP_H08:     UART0_BUF_RXD */
-	PAD_CFG_NF(GPP_H08, NONE, DEEP, NF1),
-	/* GPP_H09:     UART0_BUF_TXD */
-	PAD_CFG_NF(GPP_H09, NONE, DEEP, NF1),
+	/* GPP_B05:     EC_ISH_INT_ODL */
+	PAD_CFG_NF(GPP_B05, NONE, DEEP, NF4),
+	/* GPP_B17:     GSC_SOC_INT_ODL */
+	PAD_CFG_GPI(GPP_B17, NONE, DEEP),
+	/* GPP_B24:     EC_SOC_INT_ODL */
+	PAD_CFG_GPI(GPP_B24, NONE, DEEP),
 
-	/* GPP_H06: I2C3_SDA_PSS */
-	PAD_CFG_NF(GPP_H06, NONE, DEEP, NF1),
-	/* GPP_H07: I2C3_SCL_PSS */
-	PAD_CFG_NF(GPP_H07, NONE, DEEP, NF1),
-	/* GPP_D15: SPI_TPM_INT_N */
-	PAD_CFG_GPI_APIC(GPP_D15, NONE, PLTRST, LEVEL, INVERT),
+	/* GPP_D05:     UART_ISH_RX_DBG_TX */
+	PAD_CFG_NF(GPP_D05, NONE, DEEP, NF2),
+	/* GPP_D06:     UART_ISH_TX_DBG_RX */
+	PAD_CFG_NF(GPP_D06, NONE, DEEP, NF2),
+
+	/* GPP_F20:     EC_SOC_REC_SWITCH_ODL */
+	PAD_CFG_GPO(GPP_F20, 0, PLTRST),
+
+	/* GPP_H06:     UART_SOC_RX_FP_TX */
+	PAD_CFG_NF(GPP_H06, NONE, DEEP, NF2),
+	/* GPP_H07:     UART_SOC_TX_FP_RX */
+	PAD_CFG_NF(GPP_H07, NONE, DEEP, NF2),
+	/* GPP_H08:     UART_SOC_RX_DBG_TX */
+	PAD_CFG_NF(GPP_H08, NONE, DEEP, NF1),
+	/* GPP_H09:     UART_SOC_TX_DBG_RX */
+	PAD_CFG_NF(GPP_H09, NONE, DEEP, NF1),
+	/* GPP_H21:     SOC_I2C_GSC_SDA */
+	PAD_CFG_NF(GPP_H21, NONE, DEEP, NF1),
+	/* GPP_H22:     SOC_I2C_GSC_SCL */
+	PAD_CFG_NF(GPP_H22, NONE, DEEP, NF1),
+
+	/* GPP_V01:     EC_AC_PRESENT_OD */
+	PAD_CFG_NF(GPP_V01, NONE, DEEP, NF1),
+	/* GPP_V02:     EC_SOC_WAKE_ODL */
+	/* FIXME */
+	PAD_CFG_GPI_IRQ_WAKE(GPP_V02, NONE, PLTRST, LEVEL, INVERT),
+	/* GPP_V03:     EC_SOC_PWR_BTN_ODL */
+	PAD_CFG_NF(GPP_V03, NONE, DEEP, NF1),
 };
 
 /* Pad configuration in romstage */
 static const struct pad_config romstage_gpio_table[] = {
-	/* GPP_C00:     GPP_C0_SMBCLK */
-	PAD_CFG_NF(GPP_C00, NONE, DEEP, NF1),
-	/* GPP_C01:     GPP_C1_SMBDATA */
-	PAD_CFG_NF(GPP_C01, NONE, DEEP, NF1),
 };
 
 const struct pad_config *variant_gpio_table(size_t *num)

From 5d7e2b4c0cf052a4889f071a91c420d42cb8bed0 Mon Sep 17 00:00:00 2001
From: Jeremy Compostella <jeremy.compostella@intel.com>
Date: Mon, 21 Apr 2025 12:03:05 -0700
Subject: [PATCH 0829/3886] mb/google/fatcat: Disable VR settings on Panther
 Lake H SoC

Introduce a new static function `disable_vr_settings_on_pantherlake_h()`
to disable Voltage Regulator (VR) settings when a Panther Lake H System
on Chip (SoC) is detected.

The existing VR configurations, introduced by commit d19dd192dbe3
("mb/google/fatcat: Add PTL-U Fast VMode Voltage Regulator settings"),
are optimized for Panther Lake U SoC, which can cause performance issues
on Panther Lake H boards under stress due to the I_TRIP value being
lower than what the device could actually use. By disabling these
settings, the Firmware Support Package (FSP) falls back to default
values for the SoC, which are more suitable.

TEST=Observe the "Disabling VR settings on PTL-H" log during a boot test
     on a Panther Lake H variant.

Change-Id: Ifc371212259fa724425158ad9ebadebd30c81705
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87403
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
---
 src/mainboard/google/fatcat/romstage.c | 47 ++++++++++++++++++++++++++
 1 file changed, 47 insertions(+)

diff --git a/src/mainboard/google/fatcat/romstage.c b/src/mainboard/google/fatcat/romstage.c
index 8f0000c2ce..44a901a0ec 100644
--- a/src/mainboard/google/fatcat/romstage.c
+++ b/src/mainboard/google/fatcat/romstage.c
@@ -1,6 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0-or-later */
 
 #include <baseboard/variants.h>
+#include <device/pci_ops.h>
 #include <fsp/api.h>
 #include <soc/romstage.h>
 #include <soc/soc_chip.h>
@@ -22,6 +23,49 @@ __weak void variant_update_soc_memory_init_params(FSPM_UPD *memupd)
 	/* Nothing to do */
 }
 
+static bool soc_is_pantherlake_h(void)
+{
+	uint16_t mch_id = pci_s_read_config16(PCI_DEV(0, 0, 0), PCI_DEVICE_ID);
+
+	if (mch_id == 0xffff) {
+		printk(BIOS_ERR, "No matching PCI DID present\n");
+		return false;
+	}
+
+	/*
+	 * Identify Panther Lake H by testing all Memory Controller Hub (MCH) IDs utilized on fatcat
+	 * devices.
+	 */
+	switch (mch_id) {
+	case PCI_DID_INTEL_PTL_H_ID_1:
+	case PCI_DID_INTEL_PTL_H_ID_2:
+	case PCI_DID_INTEL_PTL_H_ID_3:
+	case PCI_DID_INTEL_PTL_H_ID_4:
+		return true;
+	default:
+		return false;
+	}
+}
+
+static void disable_vr_settings_on_pantherlake_h(FSP_M_CONFIG *m_cfg)
+{
+	if (!soc_is_pantherlake_h())
+		return;
+
+	/*
+	 * The board operates a Panther Lake H SoC; disable the PTL-U VR settings.
+	 *
+	 * The Voltage Regulator (VR) configurations supplied by the device tree are
+	 * specifically adjusted for a Panther Lake U SoC, which is intended for fatcat board
+	 * designs. When these settings are applied to a board equipped with a Panther Lake H
+	 * SoC, it may experience performance problems under high-stress conditions. This is
+	 * because the I_TRIP value is set lower than the device's actual capability.
+	 */
+	printk(BIOS_INFO, "Disabling VR settings on PTL-H.\n");
+	for (size_t i = 0; i < NUM_VR_DOMAINS; i++)
+		m_cfg->CepEnable[i] = false;
+}
+
 void mainboard_memory_init_params(FSPM_UPD *memupd)
 {
 	const struct pad_config *pads;
@@ -40,6 +84,9 @@ void mainboard_memory_init_params(FSPM_UPD *memupd)
 
 	memcfg_init(memupd, mem_config, &spd_info, half_populated);
 
+	/* Override FSP-M Voltage Regulator settings on Panther Lake H. */
+	disable_vr_settings_on_pantherlake_h(&memupd->FspmConfig);
+
 	/* Override FSP-M UPD per board if required. */
 	variant_update_soc_memory_init_params(memupd);
 }

From fed584e100d3d549d6b281cb55cc1c6e5952e0ba Mon Sep 17 00:00:00 2001
From: Appukuttan V K <appukuttan.vk@intel.com>
Date: Thu, 10 Apr 2025 19:57:25 +0530
Subject: [PATCH 0830/3886] soc/intel: Add Wildcat Lake CPU and PCIe device IDs

This patch adds Wildcat Lake-specific CPU and PCIe device IDs to the
header files and driver-specific code.

Reference:
Wildcat Lake Processor Prelim External Device IDs (820363)

BUG=b:394208231
TEST=Verified on Wildcat Lake Simulation Platform

Change-Id: I4bc7a8ea898ee30d565a95b9f85d6f19886bcffb
Signed-off-by: Appukuttan V K <appukuttan.vk@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87262
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/drivers/intel/ish/ish.c                   |  1 +
 src/drivers/intel/touch/touch.c               |  4 +
 src/include/cpu/intel/cpu_ids.h               |  1 +
 src/include/device/pci_ids.h                  | 94 +++++++++++++++++++
 src/soc/intel/common/block/cnvi/cnvi.c        |  5 +
 src/soc/intel/common/block/cpu/mp_init.c      |  1 +
 src/soc/intel/common/block/cse/cse.c          |  1 +
 src/soc/intel/common/block/dsp/dsp.c          |  8 ++
 src/soc/intel/common/block/dtt/dtt.c          |  1 +
 .../intel/common/block/graphics/graphics.c    |  2 +
 src/soc/intel/common/block/hda/hda.c          |  8 ++
 src/soc/intel/common/block/i2c/i2c.c          |  6 ++
 src/soc/intel/common/block/lpc/lpc.c          | 32 +++++++
 src/soc/intel/common/block/p2sb/ioe_p2sb.c    |  1 +
 src/soc/intel/common/block/p2sb/p2sb.c        |  1 +
 src/soc/intel/common/block/pcie/pcie.c        |  6 ++
 src/soc/intel/common/block/pmc/pmc.c          |  1 +
 src/soc/intel/common/block/smbus/smbus.c      |  1 +
 src/soc/intel/common/block/spi/spi.c          |  4 +
 src/soc/intel/common/block/sram/sram.c        |  2 +
 .../common/block/systemagent/systemagent.c    |  2 +
 .../intel/common/block/tracehub/tracehub.c    |  1 +
 src/soc/intel/common/block/uart/uart.c        |  6 ++
 src/soc/intel/common/block/usb4/usb4.c        |  1 +
 src/soc/intel/common/block/usb4/xhci.c        |  1 +
 src/soc/intel/common/block/xdci/xdci.c        |  1 +
 src/soc/intel/common/block/xhci/xhci.c        |  1 +
 27 files changed, 193 insertions(+)

diff --git a/src/drivers/intel/ish/ish.c b/src/drivers/intel/ish/ish.c
index 5dd4a799bb..43342f0283 100644
--- a/src/drivers/intel/ish/ish.c
+++ b/src/drivers/intel/ish/ish.c
@@ -85,6 +85,7 @@ static const struct device_operations pci_ish_device_ops = {
 };
 
 static const unsigned short pci_device_ids[] = {
+	PCI_DID_INTEL_WCL_ISHB,
 	PCI_DID_INTEL_PTL_H_ISHB,
 	PCI_DID_INTEL_PTL_U_H_ISHB,
 	PCI_DID_INTEL_LNL_ISHB,
diff --git a/src/drivers/intel/touch/touch.c b/src/drivers/intel/touch/touch.c
index a89d2e61ab..5ad4518a2a 100644
--- a/src/drivers/intel/touch/touch.c
+++ b/src/drivers/intel/touch/touch.c
@@ -581,6 +581,10 @@ static const unsigned short pci_device_ids[] = {
 	PCI_DID_INTEL_PTL_H_THC0_SPI,
 	PCI_DID_INTEL_PTL_H_THC1_I2C,
 	PCI_DID_INTEL_PTL_H_THC1_SPI,
+	PCI_DID_INTEL_WCL_THC0_I2C,
+	PCI_DID_INTEL_WCL_THC0_SPI,
+	PCI_DID_INTEL_WCL_THC1_I2C,
+	PCI_DID_INTEL_WCL_THC1_SPI,
 	0
 };
 
diff --git a/src/include/cpu/intel/cpu_ids.h b/src/include/cpu/intel/cpu_ids.h
index 9ef74b9e3f..22d2e58693 100644
--- a/src/include/cpu/intel/cpu_ids.h
+++ b/src/include/cpu/intel/cpu_ids.h
@@ -92,5 +92,6 @@
 #define CPUID_SNOWRIDGE_B0		0x80664
 #define CPUID_SNOWRIDGE_B1		0x80665
 #define CPUID_SNOWRIDGE_C0		0x80667
+#define CPUID_WILDCATLAKE_A0		0xd0650
 
 #endif /* CPU_INTEL_CPU_IDS_H */
diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h
index fdcddb2ffe..40844f5972 100644
--- a/src/include/device/pci_ids.h
+++ b/src/include/device/pci_ids.h
@@ -2187,6 +2187,7 @@
 #define PCI_DID_INTEL_LNL_ISHB		0xa845
 #define PCI_DID_INTEL_PTL_H_ISHB	0xe445
 #define PCI_DID_INTEL_PTL_U_H_ISHB	0xe345
+#define PCI_DID_INTEL_WCL_ISHB		0x4d45
 
 /* Intel 82371FB (PIIX) */
 #define PCI_DID_INTEL_82371FB_ISA		0x122e
@@ -3246,6 +3247,38 @@
 #define PCI_DID_INTEL_PTL_U_H_ESPI_30			0xe31e
 #define PCI_DID_INTEL_PTL_U_H_ESPI_31			0xe31f
 #define PCI_DID_INTEL_SNR_LPC					0x18dc
+#define PCI_DID_INTEL_WCL_ESPI_0			0x4d00
+#define PCI_DID_INTEL_WCL_ESPI_1			0x4d01
+#define PCI_DID_INTEL_WCL_ESPI_2			0x4d02
+#define PCI_DID_INTEL_WCL_ESPI_3			0x4d03
+#define PCI_DID_INTEL_WCL_ESPI_4			0x4d04
+#define PCI_DID_INTEL_WCL_ESPI_5			0x4d05
+#define PCI_DID_INTEL_WCL_ESPI_6			0x4d06
+#define PCI_DID_INTEL_WCL_ESPI_7			0x4d07
+#define PCI_DID_INTEL_WCL_ESPI_8			0x4d08
+#define PCI_DID_INTEL_WCL_ESPI_9			0x4d09
+#define PCI_DID_INTEL_WCL_ESPI_10			0x4d0a
+#define PCI_DID_INTEL_WCL_ESPI_11			0x4d0b
+#define PCI_DID_INTEL_WCL_ESPI_12			0x4d0c
+#define PCI_DID_INTEL_WCL_ESPI_13			0x4d0d
+#define PCI_DID_INTEL_WCL_ESPI_14			0x4d0e
+#define PCI_DID_INTEL_WCL_ESPI_15			0x4d0f
+#define PCI_DID_INTEL_WCL_ESPI_16			0x4d10
+#define PCI_DID_INTEL_WCL_ESPI_17			0x4d11
+#define PCI_DID_INTEL_WCL_ESPI_18			0x4d12
+#define PCI_DID_INTEL_WCL_ESPI_19			0x4d13
+#define PCI_DID_INTEL_WCL_ESPI_20			0x4d14
+#define PCI_DID_INTEL_WCL_ESPI_21			0x4d15
+#define PCI_DID_INTEL_WCL_ESPI_22			0x4d16
+#define PCI_DID_INTEL_WCL_ESPI_23			0x4d17
+#define PCI_DID_INTEL_WCL_ESPI_24			0x4d18
+#define PCI_DID_INTEL_WCL_ESPI_25			0x4d19
+#define PCI_DID_INTEL_WCL_ESPI_26			0x4d1a
+#define PCI_DID_INTEL_WCL_ESPI_27			0x4d1b
+#define PCI_DID_INTEL_WCL_ESPI_28			0x4d1c
+#define PCI_DID_INTEL_WCL_ESPI_29			0x4d1d
+#define PCI_DID_INTEL_WCL_ESPI_30			0x4d1e
+#define PCI_DID_INTEL_WCL_ESPI_31			0x4d1f
 
 /* Intel PCIE device ids  */
 #define PCI_DID_INTEL_LPT_H_PCIE_RP1			0x8c10
@@ -3681,6 +3714,13 @@
 #define PCI_DID_INTEL_SNR_PCH_PCIE_RP10			0x18af
 #define PCI_DID_INTEL_SNR_PCH_PCIE_RP11			0x18a2
 
+#define PCI_DID_INTEL_WCL_PCIE_RP1                      0x4d3c
+#define PCI_DID_INTEL_WCL_PCIE_RP2                      0x4d3d
+#define PCI_DID_INTEL_WCL_PCIE_RP3                      0x4d3e
+#define PCI_DID_INTEL_WCL_PCIE_RP4                      0x4d3f
+#define PCI_DID_INTEL_WCL_PCIE_RP5                      0x4d61
+#define PCI_DID_INTEL_WCL_PCIE_RP6                      0x4d5c
+
 /* Intel SATA device Ids */
 #define PCI_DID_INTEL_LPT_H_DESKTOP_SATA_IDE			0x8c00
 #define PCI_DID_INTEL_LPT_H_DESKTOP_SATA_AHCI			0x8c02
@@ -3799,6 +3839,7 @@
 #define PCI_DID_INTEL_LNL_PMC			0xa821
 #define PCI_DID_INTEL_PTL_H_PMC			0xe421
 #define PCI_DID_INTEL_PTL_U_H_PMC		0xe321
+#define PCI_DID_INTEL_WCL_PMC			0x4d21
 
 /* Intel I2C device Ids */
 #define PCI_DID_INTEL_LPT_LP_I2C0		0x9c61
@@ -3943,6 +3984,13 @@
 #define PCI_DID_INTEL_PTL_U_H_I2C4		0xe350
 #define PCI_DID_INTEL_PTL_U_H_I2C5		0xe351
 
+#define PCI_DID_INTEL_WCL_I2C0			0x4d78
+#define PCI_DID_INTEL_WCL_I2C1			0x4d79
+#define PCI_DID_INTEL_WCL_I2C2			0x4d7a
+#define PCI_DID_INTEL_WCL_I2C3			0x4d7b
+#define PCI_DID_INTEL_WCL_I2C4			0x4d50
+#define PCI_DID_INTEL_WCL_I2C5			0x4d51
+
 /* Intel UART device Ids */
 #define PCI_DID_INTEL_LPT_LP_UART0		0x9c63
 #define PCI_DID_INTEL_LPT_LP_UART1		0x9c64
@@ -4033,6 +4081,10 @@
 #define PCI_DID_INTEL_PTL_U_H_UART1		0xe326
 #define PCI_DID_INTEL_PTL_U_H_UART2		0xe352
 
+#define PCI_DID_INTEL_WCL_UART0			0x4d25
+#define PCI_DID_INTEL_WCL_UART1			0x4d26
+#define PCI_DID_INTEL_WCL_UART2			0x4d52
+
 /* Intel SPI device Ids */
 #define PCI_DID_INTEL_LPT_LP_GSPI0		0x9c65
 #define PCI_DID_INTEL_LPT_LP_GSPI1		0x9c66
@@ -4143,6 +4195,11 @@
 
 #define PCI_DID_INTEL_SNR_SPI			0x18e0
 
+#define PCI_DID_INTEL_WCL_HWSEQ_SPI		0x4d23
+#define PCI_DID_INTEL_WCL_SPI0			0x4d27
+#define PCI_DID_INTEL_WCL_SPI1			0x4d30
+#define PCI_DID_INTEL_WCL_SPI2			0x4d46
+
 /* Intel IGD device Ids */
 #define PCI_DID_INTEL_SKL_GT1F_DT2			0x1902
 #define PCI_DID_INTEL_SKL_GT1_SULTM			0x1906
@@ -4310,6 +4367,8 @@
 #define PCI_DID_INTEL_PTL_H_GT2_1			0xb080
 #define PCI_DID_INTEL_PTL_H_GT2_2			0xb0a0
 #define PCI_DID_INTEL_PTL_H_GT2_3			0xb0b0
+#define PCI_DID_INTEL_WCL_GT2_1				0xfd80
+#define PCI_DID_INTEL_WCL_GT2_2				0xfd81
 
 /* Intel Northbridge Ids */
 #define PCI_DID_INTEL_APL_NB			0x5af0
@@ -4466,6 +4525,8 @@
 #define PCI_DID_INTEL_PTL_H_ID_3		0xb004
 #define PCI_DID_INTEL_PTL_H_ID_4		0xb00a
 #define PCI_DID_INTEL_SNR_ID			0x09a2
+#define PCI_DID_INTEL_WCL_ID_1			0xfd00
+#define PCI_DID_INTEL_WCL_ID_2			0xfd01
 
 /* Intel SMBUS device Ids */
 #define PCI_DID_INTEL_LPT_H_SMBUS			0x8c22
@@ -4497,6 +4558,7 @@
 #define PCI_DID_INTEL_LNL_SMBUS				0xa822
 #define PCI_DID_INTEL_PTL_H_SMBUS			0xe422
 #define PCI_DID_INTEL_PTL_U_H_SMBUS			0xe322
+#define PCI_DID_INTEL_WCL_SMBUS				0x4d22
 
 /* Intel EHCI device IDs */
 #define PCI_DID_INTEL_LPT_H_EHCI_1		0x8c26
@@ -4544,6 +4606,8 @@
 #define PCI_DID_INTEL_PTL_U_H_XHCI		0xe37d
 #define PCI_DID_INTEL_PTL_U_H_TCSS_XHCI		0xe331
 #define PCI_DID_INTEL_SNR_XHCI			0x18d0
+#define PCI_DID_INTEL_WCL_XHCI			0x4d7d
+#define PCI_DID_INTEL_WCL_TCSS_XHCI		0x4d31
 
 /* Intel P2SB device Ids */
 #define PCI_DID_INTEL_APL_P2SB			0x5a92
@@ -4577,6 +4641,8 @@
 #define PCI_DID_INTEL_PTL_U_H_P2SB		0xe320
 #define PCI_DID_INTEL_PTL_U_H_P2SB2		0xe34c
 #define PCI_DID_INTEL_SNR_P2SB			0x18dd
+#define PCI_DID_INTEL_WCL_P2SB			0x4d20
+#define PCI_DID_INTEL_WCL_P2SB2			0x4d4c
 
 /* Intel SRAM device Ids */
 #define PCI_DID_INTEL_APL_SRAM			0x5aec
@@ -4594,6 +4660,7 @@
 #define PCI_DID_INTEL_LNL_SRAM			0xa87f
 #define PCI_DID_INTEL_PTL_H_SRAM		0xe47f
 #define PCI_DID_INTEL_PTL_U_H_SRAM		0xe37f
+#define PCI_DID_INTEL_WCL_SRAM			0x4d7f
 
 /* Intel AUDIO device Ids */
 #define PCI_DID_INTEL_LPT_H_AUDIO		0x8c20
@@ -4677,6 +4744,15 @@
 #define PCI_DID_INTEL_PTL_U_H_AUDIO_7		0xe32e
 #define PCI_DID_INTEL_PTL_U_H_AUDIO_8		0xe32f
 
+#define PCI_DID_INTEL_WCL_AUDIO_1		0x4d28
+#define PCI_DID_INTEL_WCL_AUDIO_2		0x4d29
+#define PCI_DID_INTEL_WCL_AUDIO_3		0x4d2a
+#define PCI_DID_INTEL_WCL_AUDIO_4		0x4d2b
+#define PCI_DID_INTEL_WCL_AUDIO_5		0x4d2c
+#define PCI_DID_INTEL_WCL_AUDIO_6		0x4d2d
+#define PCI_DID_INTEL_WCL_AUDIO_7		0x4d2e
+#define PCI_DID_INTEL_WCL_AUDIO_8		0x4d2f
+
 /* Intel HECI/ME device Ids */
 #define PCI_DID_INTEL_LPT_H_MEI			0x8c3a
 #define PCI_DID_INTEL_LPT_H_MEI_9		0x8cba
@@ -4725,6 +4801,7 @@
 #define PCI_DID_INTEL_PTL_H_CSE0		0xe470
 #define PCI_DID_INTEL_PTL_U_H_CSE0		0xe370
 #define PCI_DID_INTEL_SNR_HECI1			0x18d3
+#define PCI_DID_INTEL_WCL_CSE0			0x4d70
 
 /* Intel XDCI device Ids */
 #define PCI_DID_INTEL_APL_XDCI			0x5aaa
@@ -4750,6 +4827,7 @@
 #define PCI_DID_INTEL_MTL_P_TCSS_XDCI		0x7ec1
 #define PCI_DID_INTEL_PTL_H_XDCI		0xe47e
 #define PCI_DID_INTEL_PTL_U_H_XDCI		0xe37e
+#define PCI_DID_INTEL_WCL_XDCI		0x4d7e
 
 /* Intel SD device Ids */
 #define PCI_DID_INTEL_LPT_LP_SD			0x9c35
@@ -4810,6 +4888,7 @@
 #define PCI_DID_INTEL_LNL_TBT_DMA1		0xa834
 #define PCI_DID_INTEL_PTL_TBT_DMA0		0xe433
 #define PCI_DID_INTEL_PTL_TBT_DMA1		0xe434
+#define PCI_DID_INTEL_WCL_TBT_DMA0		0x4d33
 
 /* Intel WIFI Ids */
 #define PCI_DID_1000_SERIES_WIFI		0x0084
@@ -4861,6 +4940,7 @@
 #define PCI_DID_INTEL_MTL_DTT			0x7d03
 #define PCI_DID_INTEL_RPL_DTT			0xa71d
 #define PCI_DID_INTEL_PTL_DTT			0xb01d
+#define PCI_DID_INTEL_WCL_DTT			0xfd1d
 
 /* Intel CNVi WiFi/BT device IDs */
 #define PCI_DID_INTEL_CML_LP_CNVI_WIFI		0x02f0
@@ -4922,11 +5002,19 @@
 #define PCI_DID_INTEL_PTL_U_H_CNVI_WIFI_2	0xe342
 #define PCI_DID_INTEL_PTL_U_H_CNVI_WIFI_3	0xe343
 #define PCI_DID_INTEL_PTL_U_H_CNVI_BT		0xe376
+#define PCI_DID_INTEL_WCL_CNVI_WIFI_0		0x4d40
+#define PCI_DID_INTEL_WCL_CNVI_WIFI_1		0x4d41
+#define PCI_DID_INTEL_WCL_CNVI_WIFI_2		0x4d42
+#define PCI_DID_INTEL_WCL_CNVI_WIFI_3		0x4d43
+#define PCI_DID_INTEL_WCL_CNVI_BT		0x4d76
 
 /* Platform Security Engine */
 #define PCI_DID_INTEL_LNL_PSE0			0xa862
 #define PCI_DID_INTEL_LNL_PSE1			0xa863
 #define PCI_DID_INTEL_LNL_PSE2			0xa864
+#define PCI_DID_INTEL_WCL_PSE0			0x4d62
+#define PCI_DID_INTEL_WCL_PSE1			0x4d63
+#define PCI_DID_INTEL_WCL_PSE2			0x4d64
 
 /* In-memory Analytics Accelerator device IDs */
 #define PCI_DID_INTEL_LNL_IAA			0x642d
@@ -4942,12 +5030,14 @@
 #define PCI_DID_INTEL_RPL_CPU_CRASHLOG_SRAM		0xa77d
 #define PCI_DID_INTEL_RPP_S_PMC_CRASHLOG_SRAM		0x7a27
 #define PCI_DID_INTEL_PTL_PUNIT_CRASHLOG_SRAM		0xb07d
+#define PCI_DID_INTEL_WCL_PUNIT_CRASHLOG_SRAM		0xfd7d
 
 /* Intel Trace Hub */
 #define PCI_DID_INTEL_MTL_TRACEHUB			0x7e24
 #define PCI_DID_INTEL_RPL_TRACEHUB			0xa76f
 #define PCI_DID_INTEL_PTL_H_TRACEHUB			0xe424
 #define PCI_DID_INTEL_PTL_U_H_TRACEHUB			0xe324
+#define PCI_DID_INTEL_WCL_TRACEHUB			0x4d24
 
 /* Intel Ethernet Controller device Ids */
 #define PCI_DID_INTEL_EHL_GBE_HOST		0x4B32
@@ -4967,6 +5057,10 @@
 #define PCI_DID_INTEL_PTL_H_THC0_SPI	0xe449
 #define PCI_DID_INTEL_PTL_H_THC1_I2C	0xe44a
 #define PCI_DID_INTEL_PTL_H_THC1_SPI	0xe44b
+#define PCI_DID_INTEL_WCL_THC0_I2C	0x4d48
+#define PCI_DID_INTEL_WCL_THC0_SPI	0x4d49
+#define PCI_DID_INTEL_WCL_THC1_I2C	0x4d4a
+#define PCI_DID_INTEL_WCL_THC1_SPI	0x4d4b
 
 #define PCI_VID_COMPUTONE		0x8e0e
 #define PCI_DID_COMPUTONE_IP2EX		0x0291
diff --git a/src/soc/intel/common/block/cnvi/cnvi.c b/src/soc/intel/common/block/cnvi/cnvi.c
index 1d35f0cc2d..3abd907440 100644
--- a/src/soc/intel/common/block/cnvi/cnvi.c
+++ b/src/soc/intel/common/block/cnvi/cnvi.c
@@ -422,6 +422,10 @@ static struct device_operations cnvi_wifi_ops = {
 };
 
 static const unsigned short wifi_pci_device_ids[] = {
+	PCI_DID_INTEL_WCL_CNVI_WIFI_0,
+	PCI_DID_INTEL_WCL_CNVI_WIFI_1,
+	PCI_DID_INTEL_WCL_CNVI_WIFI_2,
+	PCI_DID_INTEL_WCL_CNVI_WIFI_3,
 	PCI_DID_INTEL_PTL_H_CNVI_WIFI_0,
 	PCI_DID_INTEL_PTL_H_CNVI_WIFI_1,
 	PCI_DID_INTEL_PTL_H_CNVI_WIFI_2,
@@ -496,6 +500,7 @@ static struct device_operations cnvi_bt_ops = {
 };
 
 static const unsigned short bt_pci_device_ids[] = {
+	PCI_DID_INTEL_WCL_CNVI_BT,
 	PCI_DID_INTEL_PTL_H_CNVI_BT,
 	PCI_DID_INTEL_PTL_U_H_CNVI_BT,
 	PCI_DID_INTEL_TGL_CNVI_BT_0,
diff --git a/src/soc/intel/common/block/cpu/mp_init.c b/src/soc/intel/common/block/cpu/mp_init.c
index 95e52d5d9c..1602126890 100644
--- a/src/soc/intel/common/block/cpu/mp_init.c
+++ b/src/soc/intel/common/block/cpu/mp_init.c
@@ -32,6 +32,7 @@ static struct device_operations cpu_dev_ops = {
 };
 
 static const struct cpu_device_id cpu_table[] = {
+	{ X86_VENDOR_INTEL, CPUID_WILDCATLAKE_A0, CPUID_EXACT_MATCH_MASK },
 	{ X86_VENDOR_INTEL, CPUID_PANTHERLAKE_A0, CPUID_EXACT_MATCH_MASK },
 	{ X86_VENDOR_INTEL, CPUID_LUNARLAKE_A0_1, CPUID_EXACT_MATCH_MASK },
 	{ X86_VENDOR_INTEL, CPUID_LUNARLAKE_A0_2, CPUID_EXACT_MATCH_MASK },
diff --git a/src/soc/intel/common/block/cse/cse.c b/src/soc/intel/common/block/cse/cse.c
index 68d0c21342..55dd3d2da7 100644
--- a/src/soc/intel/common/block/cse/cse.c
+++ b/src/soc/intel/common/block/cse/cse.c
@@ -1512,6 +1512,7 @@ struct device_operations cse_ops = {
 };
 
 static const unsigned short pci_device_ids[] = {
+	PCI_DID_INTEL_WCL_CSE0,
 	PCI_DID_INTEL_PTL_H_CSE0,
 	PCI_DID_INTEL_PTL_U_H_CSE0,
 	PCI_DID_INTEL_LNL_CSE0,
diff --git a/src/soc/intel/common/block/dsp/dsp.c b/src/soc/intel/common/block/dsp/dsp.c
index ab0e1168a4..bd8c9acabb 100644
--- a/src/soc/intel/common/block/dsp/dsp.c
+++ b/src/soc/intel/common/block/dsp/dsp.c
@@ -13,6 +13,14 @@ static struct device_operations dsp_dev_ops = {
 };
 
 static const unsigned short pci_device_ids[] = {
+	PCI_DID_INTEL_WCL_AUDIO_1,
+	PCI_DID_INTEL_WCL_AUDIO_2,
+	PCI_DID_INTEL_WCL_AUDIO_3,
+	PCI_DID_INTEL_WCL_AUDIO_4,
+	PCI_DID_INTEL_WCL_AUDIO_5,
+	PCI_DID_INTEL_WCL_AUDIO_6,
+	PCI_DID_INTEL_WCL_AUDIO_7,
+	PCI_DID_INTEL_WCL_AUDIO_8,
 	PCI_DID_INTEL_PTL_H_AUDIO_1,
 	PCI_DID_INTEL_PTL_H_AUDIO_2,
 	PCI_DID_INTEL_PTL_H_AUDIO_3,
diff --git a/src/soc/intel/common/block/dtt/dtt.c b/src/soc/intel/common/block/dtt/dtt.c
index 8b086e0fb9..b2ce8b9c41 100644
--- a/src/soc/intel/common/block/dtt/dtt.c
+++ b/src/soc/intel/common/block/dtt/dtt.c
@@ -8,6 +8,7 @@
 #include <intelblocks/acpi.h>
 
 static const unsigned short pci_device_ids[] = {
+	PCI_DID_INTEL_WCL_DTT,
 	PCI_DID_INTEL_PTL_DTT,
 	PCI_DID_INTEL_RPL_DTT,
 	PCI_DID_INTEL_MTL_DTT,
diff --git a/src/soc/intel/common/block/graphics/graphics.c b/src/soc/intel/common/block/graphics/graphics.c
index cf3e7b1b23..b2229152c4 100644
--- a/src/soc/intel/common/block/graphics/graphics.c
+++ b/src/soc/intel/common/block/graphics/graphics.c
@@ -342,6 +342,8 @@ const struct device_operations graphics_ops = {
 };
 
 static const unsigned short pci_device_ids[] = {
+	PCI_DID_INTEL_WCL_GT2_1,
+	PCI_DID_INTEL_WCL_GT2_2,
 	PCI_DID_INTEL_PTL_U_GT2_1,
 	PCI_DID_INTEL_PTL_H_GT2_1,
 	PCI_DID_INTEL_PTL_H_GT2_2,
diff --git a/src/soc/intel/common/block/hda/hda.c b/src/soc/intel/common/block/hda/hda.c
index 59ecb502af..d68c5b6998 100644
--- a/src/soc/intel/common/block/hda/hda.c
+++ b/src/soc/intel/common/block/hda/hda.c
@@ -21,6 +21,14 @@ struct device_operations hda_ops = {
 };
 
 static const unsigned short pci_device_ids[] = {
+	PCI_DID_INTEL_WCL_AUDIO_1,
+	PCI_DID_INTEL_WCL_AUDIO_2,
+	PCI_DID_INTEL_WCL_AUDIO_3,
+	PCI_DID_INTEL_WCL_AUDIO_4,
+	PCI_DID_INTEL_WCL_AUDIO_5,
+	PCI_DID_INTEL_WCL_AUDIO_6,
+	PCI_DID_INTEL_WCL_AUDIO_7,
+	PCI_DID_INTEL_WCL_AUDIO_8,
 	PCI_DID_INTEL_PTL_H_AUDIO_1,
 	PCI_DID_INTEL_PTL_H_AUDIO_2,
 	PCI_DID_INTEL_PTL_H_AUDIO_3,
diff --git a/src/soc/intel/common/block/i2c/i2c.c b/src/soc/intel/common/block/i2c/i2c.c
index 3c2f211d28..8097b74022 100644
--- a/src/soc/intel/common/block/i2c/i2c.c
+++ b/src/soc/intel/common/block/i2c/i2c.c
@@ -174,6 +174,12 @@ struct device_operations i2c_dev_ops = {
 };
 
 static const unsigned short pci_device_ids[] = {
+	PCI_DID_INTEL_WCL_I2C0,
+	PCI_DID_INTEL_WCL_I2C1,
+	PCI_DID_INTEL_WCL_I2C2,
+	PCI_DID_INTEL_WCL_I2C3,
+	PCI_DID_INTEL_WCL_I2C4,
+	PCI_DID_INTEL_WCL_I2C5,
 	PCI_DID_INTEL_PTL_H_I2C0,
 	PCI_DID_INTEL_PTL_H_I2C1,
 	PCI_DID_INTEL_PTL_H_I2C2,
diff --git a/src/soc/intel/common/block/lpc/lpc.c b/src/soc/intel/common/block/lpc/lpc.c
index db06db9a06..7ed01c6f85 100644
--- a/src/soc/intel/common/block/lpc/lpc.c
+++ b/src/soc/intel/common/block/lpc/lpc.c
@@ -151,6 +151,38 @@ struct device_operations lpc_ops = {
 };
 
 static const unsigned short pci_device_ids[] = {
+	PCI_DID_INTEL_WCL_ESPI_0,
+	PCI_DID_INTEL_WCL_ESPI_1,
+	PCI_DID_INTEL_WCL_ESPI_2,
+	PCI_DID_INTEL_WCL_ESPI_3,
+	PCI_DID_INTEL_WCL_ESPI_4,
+	PCI_DID_INTEL_WCL_ESPI_5,
+	PCI_DID_INTEL_WCL_ESPI_6,
+	PCI_DID_INTEL_WCL_ESPI_7,
+	PCI_DID_INTEL_WCL_ESPI_8,
+	PCI_DID_INTEL_WCL_ESPI_9,
+	PCI_DID_INTEL_WCL_ESPI_10,
+	PCI_DID_INTEL_WCL_ESPI_11,
+	PCI_DID_INTEL_WCL_ESPI_12,
+	PCI_DID_INTEL_WCL_ESPI_13,
+	PCI_DID_INTEL_WCL_ESPI_14,
+	PCI_DID_INTEL_WCL_ESPI_15,
+	PCI_DID_INTEL_WCL_ESPI_16,
+	PCI_DID_INTEL_WCL_ESPI_17,
+	PCI_DID_INTEL_WCL_ESPI_18,
+	PCI_DID_INTEL_WCL_ESPI_19,
+	PCI_DID_INTEL_WCL_ESPI_20,
+	PCI_DID_INTEL_WCL_ESPI_21,
+	PCI_DID_INTEL_WCL_ESPI_22,
+	PCI_DID_INTEL_WCL_ESPI_23,
+	PCI_DID_INTEL_WCL_ESPI_24,
+	PCI_DID_INTEL_WCL_ESPI_25,
+	PCI_DID_INTEL_WCL_ESPI_26,
+	PCI_DID_INTEL_WCL_ESPI_27,
+	PCI_DID_INTEL_WCL_ESPI_28,
+	PCI_DID_INTEL_WCL_ESPI_29,
+	PCI_DID_INTEL_WCL_ESPI_30,
+	PCI_DID_INTEL_WCL_ESPI_31,
 	PCI_DID_INTEL_PTL_U_H_ESPI_0,
 	PCI_DID_INTEL_PTL_U_H_ESPI_1,
 	PCI_DID_INTEL_PTL_U_H_ESPI_2,
diff --git a/src/soc/intel/common/block/p2sb/ioe_p2sb.c b/src/soc/intel/common/block/p2sb/ioe_p2sb.c
index 3f45e69af9..a27a23dd74 100644
--- a/src/soc/intel/common/block/p2sb/ioe_p2sb.c
+++ b/src/soc/intel/common/block/p2sb/ioe_p2sb.c
@@ -37,6 +37,7 @@ struct device_operations device_ops = {
 };
 
 static const unsigned short pci_device_ids[] = {
+	PCI_DID_INTEL_WCL_P2SB2,
 	PCI_DID_INTEL_PTL_H_P2SB2,
 	PCI_DID_INTEL_PTL_U_H_P2SB2,
 	PCI_DID_INTEL_MTL_IOE_M_P2SB,
diff --git a/src/soc/intel/common/block/p2sb/p2sb.c b/src/soc/intel/common/block/p2sb/p2sb.c
index 27e969cb55..c32982f30e 100644
--- a/src/soc/intel/common/block/p2sb/p2sb.c
+++ b/src/soc/intel/common/block/p2sb/p2sb.c
@@ -137,6 +137,7 @@ const struct device_operations p2sb_ops = {
 };
 
 static const unsigned short pci_device_ids[] = {
+	PCI_DID_INTEL_WCL_P2SB,
 	PCI_DID_INTEL_PTL_H_P2SB,
 	PCI_DID_INTEL_PTL_U_H_P2SB,
 	PCI_DID_INTEL_LNL_P2SB,
diff --git a/src/soc/intel/common/block/pcie/pcie.c b/src/soc/intel/common/block/pcie/pcie.c
index 6a1225d62b..a2db276195 100644
--- a/src/soc/intel/common/block/pcie/pcie.c
+++ b/src/soc/intel/common/block/pcie/pcie.c
@@ -67,6 +67,12 @@ struct device_operations pcie_rp_ops = {
 };
 
 static const unsigned short pcie_device_ids[] = {
+	PCI_DID_INTEL_WCL_PCIE_RP1,
+	PCI_DID_INTEL_WCL_PCIE_RP2,
+	PCI_DID_INTEL_WCL_PCIE_RP3,
+	PCI_DID_INTEL_WCL_PCIE_RP4,
+	PCI_DID_INTEL_WCL_PCIE_RP5,
+	PCI_DID_INTEL_WCL_PCIE_RP6,
 	PCI_DID_INTEL_PTL_H_PCIE_RP1,
 	PCI_DID_INTEL_PTL_H_PCIE_RP2,
 	PCI_DID_INTEL_PTL_H_PCIE_RP3,
diff --git a/src/soc/intel/common/block/pmc/pmc.c b/src/soc/intel/common/block/pmc/pmc.c
index ca1c4b02bb..50c3945044 100644
--- a/src/soc/intel/common/block/pmc/pmc.c
+++ b/src/soc/intel/common/block/pmc/pmc.c
@@ -111,6 +111,7 @@ struct device_operations pmc_ops = {
 };
 
 static const unsigned short pci_device_ids[] = {
+	PCI_DID_INTEL_WCL_PMC,
 	PCI_DID_INTEL_PTL_H_PMC,
 	PCI_DID_INTEL_PTL_U_H_PMC,
 	PCI_DID_INTEL_LNL_PMC,
diff --git a/src/soc/intel/common/block/smbus/smbus.c b/src/soc/intel/common/block/smbus/smbus.c
index 37e0cd2305..87b44f547b 100644
--- a/src/soc/intel/common/block/smbus/smbus.c
+++ b/src/soc/intel/common/block/smbus/smbus.c
@@ -49,6 +49,7 @@ struct device_operations smbus_ops = {
 };
 
 static const unsigned short pci_device_ids[] = {
+	PCI_DID_INTEL_WCL_SMBUS,
 	PCI_DID_INTEL_PTL_H_SMBUS,
 	PCI_DID_INTEL_PTL_U_H_SMBUS,
 	PCI_DID_INTEL_LNL_SMBUS,
diff --git a/src/soc/intel/common/block/spi/spi.c b/src/soc/intel/common/block/spi/spi.c
index 74f9e314cf..5b45facd4c 100644
--- a/src/soc/intel/common/block/spi/spi.c
+++ b/src/soc/intel/common/block/spi/spi.c
@@ -123,6 +123,10 @@ struct device_operations spi_dev_ops = {
 };
 
 static const unsigned short pci_device_ids[] = {
+	PCI_DID_INTEL_WCL_HWSEQ_SPI,
+	PCI_DID_INTEL_WCL_SPI0,
+	PCI_DID_INTEL_WCL_SPI1,
+	PCI_DID_INTEL_WCL_SPI2,
 	PCI_DID_INTEL_PTL_H_HWSEQ_SPI,
 	PCI_DID_INTEL_PTL_H_SPI0,
 	PCI_DID_INTEL_PTL_H_SPI1,
diff --git a/src/soc/intel/common/block/sram/sram.c b/src/soc/intel/common/block/sram/sram.c
index da7022df64..f4eda9790d 100644
--- a/src/soc/intel/common/block/sram/sram.c
+++ b/src/soc/intel/common/block/sram/sram.c
@@ -33,6 +33,8 @@ static const struct device_operations device_ops = {
 };
 
 static const unsigned short pci_device_ids[] = {
+	PCI_DID_INTEL_WCL_SRAM,
+	PCI_DID_INTEL_WCL_PUNIT_CRASHLOG_SRAM,
 	PCI_DID_INTEL_PTL_H_SRAM,
 	PCI_DID_INTEL_PTL_U_H_SRAM,
 	PCI_DID_INTEL_PTL_PUNIT_CRASHLOG_SRAM,
diff --git a/src/soc/intel/common/block/systemagent/systemagent.c b/src/soc/intel/common/block/systemagent/systemagent.c
index 3a6273505a..bb3b821c44 100644
--- a/src/soc/intel/common/block/systemagent/systemagent.c
+++ b/src/soc/intel/common/block/systemagent/systemagent.c
@@ -425,6 +425,8 @@ struct device_operations systemagent_ops = {
 };
 
 static const unsigned short systemagent_ids[] = {
+	PCI_DID_INTEL_WCL_ID_1,
+	PCI_DID_INTEL_WCL_ID_2,
 	PCI_DID_INTEL_PTL_U_ID_1,
 	PCI_DID_INTEL_PTL_H_ID_1,
 	PCI_DID_INTEL_PTL_H_ID_2,
diff --git a/src/soc/intel/common/block/tracehub/tracehub.c b/src/soc/intel/common/block/tracehub/tracehub.c
index ba56c4c6fc..ab1d4a6b99 100644
--- a/src/soc/intel/common/block/tracehub/tracehub.c
+++ b/src/soc/intel/common/block/tracehub/tracehub.c
@@ -42,6 +42,7 @@ static struct device_operations dev_ops = {
 };
 
 static const unsigned short pci_device_ids[] = {
+	PCI_DID_INTEL_WCL_TRACEHUB,
 	PCI_DID_INTEL_PTL_H_TRACEHUB,
 	PCI_DID_INTEL_PTL_U_H_TRACEHUB,
 	PCI_DID_INTEL_MTL_TRACEHUB,
diff --git a/src/soc/intel/common/block/uart/uart.c b/src/soc/intel/common/block/uart/uart.c
index ef83f5342a..839f54ebe5 100644
--- a/src/soc/intel/common/block/uart/uart.c
+++ b/src/soc/intel/common/block/uart/uart.c
@@ -308,6 +308,7 @@ static const char *uart_acpi_hid(const struct device *dev)
 static const char *uart_acpi_name(const struct device *dev)
 {
 	switch (dev->device) {
+	case PCI_DID_INTEL_WCL_UART0:
 	case PCI_DID_INTEL_PTL_H_UART0:
 	case PCI_DID_INTEL_PTL_U_H_UART0:
 	case PCI_DID_INTEL_LNL_UART0:
@@ -318,6 +319,7 @@ static const char *uart_acpi_name(const struct device *dev)
 	case PCI_DID_INTEL_SPT_H_UART0:
 	case PCI_DID_INTEL_CNP_H_UART0:
 		return "UAR0";
+	case PCI_DID_INTEL_WCL_UART1:
 	case PCI_DID_INTEL_PTL_H_UART1:
 	case PCI_DID_INTEL_PTL_U_H_UART1:
 	case PCI_DID_INTEL_LNL_UART1:
@@ -328,6 +330,7 @@ static const char *uart_acpi_name(const struct device *dev)
 	case PCI_DID_INTEL_SPT_H_UART1:
 	case PCI_DID_INTEL_CNP_H_UART1:
 		return "UAR1";
+	case PCI_DID_INTEL_WCL_UART2:
 	case PCI_DID_INTEL_PTL_H_UART2:
 	case PCI_DID_INTEL_PTL_U_H_UART2:
 	case PCI_DID_INTEL_LNL_UART2:
@@ -357,6 +360,9 @@ struct device_operations uart_ops = {
 };
 
 static const unsigned short pci_device_ids[] = {
+	PCI_DID_INTEL_WCL_UART0,
+	PCI_DID_INTEL_WCL_UART1,
+	PCI_DID_INTEL_WCL_UART2,
 	PCI_DID_INTEL_PTL_H_UART0,
 	PCI_DID_INTEL_PTL_H_UART1,
 	PCI_DID_INTEL_PTL_H_UART2,
diff --git a/src/soc/intel/common/block/usb4/usb4.c b/src/soc/intel/common/block/usb4/usb4.c
index ff898abb12..9d176a3695 100644
--- a/src/soc/intel/common/block/usb4/usb4.c
+++ b/src/soc/intel/common/block/usb4/usb4.c
@@ -52,6 +52,7 @@ static void tbt_dma_fill_ssdt(const struct device *dev)
 #endif
 
 static const unsigned short pci_device_ids[] = {
+	PCI_DID_INTEL_WCL_TBT_DMA0,
 	PCI_DID_INTEL_PTL_TBT_DMA0,
 	PCI_DID_INTEL_PTL_TBT_DMA1,
 	PCI_DID_INTEL_LNL_TBT_DMA0,
diff --git a/src/soc/intel/common/block/usb4/xhci.c b/src/soc/intel/common/block/usb4/xhci.c
index 8776e4d840..a23845820a 100644
--- a/src/soc/intel/common/block/usb4/xhci.c
+++ b/src/soc/intel/common/block/usb4/xhci.c
@@ -26,6 +26,7 @@ static struct device_operations usb4_xhci_ops = {
 };
 
 static const unsigned short pci_device_ids[] = {
+	PCI_DID_INTEL_WCL_TCSS_XHCI,
 	PCI_DID_INTEL_PTL_H_TCSS_XHCI,
 	PCI_DID_INTEL_PTL_U_H_TCSS_XHCI,
 	PCI_DID_INTEL_LNL_TCSS_XHCI,
diff --git a/src/soc/intel/common/block/xdci/xdci.c b/src/soc/intel/common/block/xdci/xdci.c
index 86625da968..3878bf9ada 100644
--- a/src/soc/intel/common/block/xdci/xdci.c
+++ b/src/soc/intel/common/block/xdci/xdci.c
@@ -28,6 +28,7 @@ struct device_operations usb_xdci_ops = {
 };
 
 static const unsigned short pci_device_ids[] = {
+	PCI_DID_INTEL_WCL_XDCI,
 	PCI_DID_INTEL_PTL_H_XDCI,
 	PCI_DID_INTEL_PTL_U_H_XDCI,
 	PCI_DID_INTEL_MTL_XDCI,
diff --git a/src/soc/intel/common/block/xhci/xhci.c b/src/soc/intel/common/block/xhci/xhci.c
index 6d35f39afb..4892e11e16 100644
--- a/src/soc/intel/common/block/xhci/xhci.c
+++ b/src/soc/intel/common/block/xhci/xhci.c
@@ -131,6 +131,7 @@ struct device_operations usb_xhci_ops = {
 };
 
 static const unsigned short pci_device_ids[] = {
+	PCI_DID_INTEL_WCL_XHCI,
 	PCI_DID_INTEL_PTL_H_XHCI,
 	PCI_DID_INTEL_PTL_U_H_XHCI,
 	PCI_DID_INTEL_LNL_XHCI,

From 76a1e81b103161da28e0cb6f19984250239be967 Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Fri, 18 Apr 2025 19:42:14 +0100
Subject: [PATCH 0831/3886] mb/starlabs/*: Unify Sleep S3 and S4 GPIO
 configurations

Ensure all boards configure these two GPIOs to NF1.

Change-Id: Ie8a222bff349a427083adb1c4d7ca73a41de3095
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87360
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
---
 src/mainboard/starlabs/byte_adl/variants/mk_ii/gpio.c    | 4 ++--
 src/mainboard/starlabs/starbook/variants/adl/gpio.c      | 4 ++--
 src/mainboard/starlabs/starbook/variants/rpl/gpio.c      | 4 ++--
 src/mainboard/starlabs/starfighter/variants/rpl/gpio.c   | 4 ++--
 src/mainboard/starlabs/starlite_adl/variants/mk_v/gpio.c | 4 ++--
 5 files changed, 10 insertions(+), 10 deletions(-)

diff --git a/src/mainboard/starlabs/byte_adl/variants/mk_ii/gpio.c b/src/mainboard/starlabs/byte_adl/variants/mk_ii/gpio.c
index 242124c415..6b9fb5be6e 100644
--- a/src/mainboard/starlabs/byte_adl/variants/mk_ii/gpio.c
+++ b/src/mainboard/starlabs/byte_adl/variants/mk_ii/gpio.c
@@ -21,8 +21,8 @@ const struct pad_config gpio_table[] = {
 	PAD_CFG_NF(GPD0, NONE, DEEP, NF1),				/* Battery Low */
 	PAD_CFG_NF(GPD1, NONE, DEEP, NF1),				/* Charger Connected */
 	PAD_CFG_NF(GPD3, UP_20K, DEEP, NF1),				/* Power Button */
-	PAD_NC(GPD4, NONE),						/* Sleep S3 */
-	PAD_NC(GPD5, NONE),						/* Sleep S4 */
+	PAD_CFG_NF(GPD4, NONE, DEEP, NF1),				/* Sleep S3 */
+	PAD_CFG_NF(GPD5, NONE, DEEP, NF1),				/* Sleep S4 */
 	PAD_CFG_NF(GPD8, NONE, DEEP, NF1),				/* Bluetooth Suspend */
 
 	/* eSPI */
diff --git a/src/mainboard/starlabs/starbook/variants/adl/gpio.c b/src/mainboard/starlabs/starbook/variants/adl/gpio.c
index 3ddf06c7fb..7edf4ce7b9 100644
--- a/src/mainboard/starlabs/starbook/variants/adl/gpio.c
+++ b/src/mainboard/starlabs/starbook/variants/adl/gpio.c
@@ -21,8 +21,8 @@ const struct pad_config gpio_table[] = {
 	PAD_CFG_NF(GPD0, NONE, DEEP, NF1),				/* Battery Low */
 	PAD_CFG_NF(GPD1, NONE, DEEP, NF1),				/* Charger Connected */
 	PAD_CFG_NF(GPD3, UP_20K, DEEP, NF1),				/* Power Button */
-	PAD_NC(GPD4, NONE),						/* Sleep S3 */
-	PAD_NC(GPD5, NONE),						/* Sleep S4 */
+	PAD_CFG_NF(GPD4, NONE, DEEP, NF1),				/* Sleep S3 */
+	PAD_CFG_NF(GPD5, NONE, DEEP, NF1),				/* Sleep S4 */
 	PAD_CFG_NF(GPD8, NONE, DEEP, NF1),				/* Bluetooth Suspend */
 
 	/* eSPI */
diff --git a/src/mainboard/starlabs/starbook/variants/rpl/gpio.c b/src/mainboard/starlabs/starbook/variants/rpl/gpio.c
index 6682a39cd4..56ab332835 100644
--- a/src/mainboard/starlabs/starbook/variants/rpl/gpio.c
+++ b/src/mainboard/starlabs/starbook/variants/rpl/gpio.c
@@ -21,8 +21,8 @@ const struct pad_config gpio_table[] = {
 	PAD_CFG_NF(GPD0, NONE, DEEP, NF1),				/* Battery Low */
 	PAD_CFG_NF(GPD1, NONE, DEEP, NF1),				/* Charger Connected */
 	PAD_CFG_NF(GPD3, UP_20K, DEEP, NF1),				/* Power Button */
-	PAD_NC(GPD4, NONE),						/* Sleep S3 */
-	PAD_NC(GPD5, NONE),						/* Sleep S4 */
+	PAD_CFG_NF(GPD4, NONE, DEEP, NF1),				/* Sleep S3 */
+	PAD_CFG_NF(GPD5, NONE, DEEP, NF1),				/* Sleep S4 */
 	PAD_CFG_NF(GPD8, NONE, DEEP, NF1),				/* Bluetooth Suspend */
 
 	/* eSPI */
diff --git a/src/mainboard/starlabs/starfighter/variants/rpl/gpio.c b/src/mainboard/starlabs/starfighter/variants/rpl/gpio.c
index c506789ff4..ab97afe180 100644
--- a/src/mainboard/starlabs/starfighter/variants/rpl/gpio.c
+++ b/src/mainboard/starlabs/starfighter/variants/rpl/gpio.c
@@ -31,8 +31,8 @@ const struct pad_config gpio_table[] = {
 	PAD_CFG_NF(GPD0, NONE, DEEP, NF1),				/* Battery Low */
 	PAD_CFG_NF(GPD1, NONE, DEEP, NF1),				/* Charger Connected */
 	PAD_CFG_NF(GPD3, UP_20K, DEEP, NF1),				/* Power Button */
-	PAD_NC(GPD4, NONE),						/* Sleep S3 */
-	PAD_NC(GPD5, NONE),						/* Sleep S4 */
+	PAD_CFG_NF(GPD4, NONE, DEEP, NF1),				/* Sleep S3 */
+	PAD_CFG_NF(GPD5, NONE, DEEP, NF1),				/* Sleep S4 */
 	PAD_CFG_NF(GPD8, NONE, DEEP, NF1),				/* Bluetooth Suspend */
 
 	/* eSPI */
diff --git a/src/mainboard/starlabs/starlite_adl/variants/mk_v/gpio.c b/src/mainboard/starlabs/starlite_adl/variants/mk_v/gpio.c
index 2b0e710d29..40cdafa3aa 100644
--- a/src/mainboard/starlabs/starlite_adl/variants/mk_v/gpio.c
+++ b/src/mainboard/starlabs/starlite_adl/variants/mk_v/gpio.c
@@ -21,8 +21,8 @@ const struct pad_config gpio_table[] = {
 	PAD_CFG_NF(GPD0, NONE, DEEP, NF1),				/* Battery Low */
 	PAD_CFG_NF(GPD1, NONE, DEEP, NF1),				/* Charger Connected */
 	PAD_CFG_NF(GPD3, UP_20K, DEEP, NF1),				/* Power Button */
-	PAD_NC(GPD4, NONE),						/* Sleep S3 */
-	PAD_NC(GPD5, NONE),						/* Sleep S4 */
+	PAD_CFG_NF(GPD4, NONE, DEEP, NF1),				/* Sleep S3 */
+	PAD_CFG_NF(GPD5, NONE, DEEP, NF1),				/* Sleep S4 */
 	PAD_CFG_NF(GPD8, NONE, DEEP, NF1),				/* Bluetooth Suspend */
 
 	/* eSPI */

From 157b7ae778e7d00c7abf0c9c67f7e0a2740967d4 Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Mon, 21 Apr 2025 14:22:31 -0500
Subject: [PATCH 0832/3886] payloads/edk2: Update default branch for
 MrChromebox repo to 2025-02

Update the default branch used for MrChromebox's edk2 fork from 2024-08
to 2025-02. This updated branch has been rebased on the latest upstream
stable tag (edk2-stable202502), and updates the EFI revocation database
used for SecureBoot. It also adds support for the CFR-based setup menu
and configuration management, and support for running OpROMs on
external dGPUs.

TEST=build/boot google boards link, panther, lulu, reef, ampton, akemi,
banshee, zork, dewatt, frostflow with edk2 payload selected.

Change-Id: I1f900d0e33e88d747547a1f5218445bb0cce4e4b
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87406
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
---
 payloads/external/edk2/Kconfig | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/payloads/external/edk2/Kconfig b/payloads/external/edk2/Kconfig
index 291da7a1f6..ea24cee4bf 100644
--- a/payloads/external/edk2/Kconfig
+++ b/payloads/external/edk2/Kconfig
@@ -86,7 +86,7 @@ config EDK2_REPOSITORY
 
 config EDK2_TAG_OR_REV
 	string "Insert a commit's SHA-1 or a branch name"
-	default "origin/uefipayload_2408" if EDK2_REPO_MRCHROMEBOX
+	default "origin/uefipayload_2502" if EDK2_REPO_MRCHROMEBOX
 	default "origin/universalpayload" if EDK2_UNIVERSAL_PAYLOAD
 	default "origin/master" if EDK2_REPO_OFFICIAL
 	default "" if EDK2_REPO_CUSTOM

From 608db150f1cfdfab9ec8cda7891e341a8102a9f3 Mon Sep 17 00:00:00 2001
From: Patrick Rudolph <patrick.rudolph@9elements.com>
Date: Thu, 10 Apr 2025 11:05:03 +0200
Subject: [PATCH 0833/3886] smmrelocate: Drop unused parameter
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

The parameter CPU isn't used, thus drop it.

Change-Id: Ie7f6179f0545f905463752e94243b438143d8234
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87257
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
---
 src/cpu/intel/haswell/smmrelocate.c          | 8 ++++----
 src/soc/intel/common/block/cpu/smmrelocate.c | 8 ++++----
 src/soc/intel/xeon_sp/smmrelocate.c          | 8 ++++----
 3 files changed, 12 insertions(+), 12 deletions(-)

diff --git a/src/cpu/intel/haswell/smmrelocate.c b/src/cpu/intel/haswell/smmrelocate.c
index 9e3554f9e3..47946e8401 100644
--- a/src/cpu/intel/haswell/smmrelocate.c
+++ b/src/cpu/intel/haswell/smmrelocate.c
@@ -17,9 +17,9 @@
 #include <smp/node.h>
 #include "haswell.h"
 
-static void update_save_state(int cpu, uintptr_t curr_smbase,
-				uintptr_t staggered_smbase,
-				struct smm_relocation_params *relo_params)
+static void update_save_state(uintptr_t curr_smbase,
+			      uintptr_t staggered_smbase,
+			      struct smm_relocation_params *relo_params)
 {
 	u32 smbase;
 	u32 iedbase;
@@ -120,7 +120,7 @@ void smm_relocation_handler(int cpu, uintptr_t curr_smbase,
 	}
 
 	/* Make appropriate changes to the save state map. */
-	update_save_state(cpu, curr_smbase, staggered_smbase, relo_params);
+	update_save_state(curr_smbase, staggered_smbase, relo_params);
 
 	/* Write PRMRR and SMRR MSRs based on indicated support. */
 	mtrr_cap = rdmsr(MTRR_CAP_MSR);
diff --git a/src/soc/intel/common/block/cpu/smmrelocate.c b/src/soc/intel/common/block/cpu/smmrelocate.c
index 4df90fd7ce..20697825cf 100644
--- a/src/soc/intel/common/block/cpu/smmrelocate.c
+++ b/src/soc/intel/common/block/cpu/smmrelocate.c
@@ -19,9 +19,9 @@
 #include <string.h>
 #include <types.h>
 
-static void update_save_state(int cpu, uintptr_t curr_smbase,
-				uintptr_t staggered_smbase,
-				struct smm_relocation_params *relo_params)
+static void update_save_state(uintptr_t curr_smbase,
+			      uintptr_t staggered_smbase,
+			      struct smm_relocation_params *relo_params)
 {
 	u32 smbase;
 	u32 iedbase;
@@ -136,7 +136,7 @@ void smm_relocation_handler(int cpu, uintptr_t curr_smbase,
 	}
 
 	/* Make appropriate changes to the save state map. */
-	update_save_state(cpu, curr_smbase, staggered_smbase, relo_params);
+	update_save_state(curr_smbase, staggered_smbase, relo_params);
 
 	/*
 	 * The SMRR MSRs are core-level registers, so if two threads that share
diff --git a/src/soc/intel/xeon_sp/smmrelocate.c b/src/soc/intel/xeon_sp/smmrelocate.c
index c359237463..c1079d31a6 100644
--- a/src/soc/intel/xeon_sp/smmrelocate.c
+++ b/src/soc/intel/xeon_sp/smmrelocate.c
@@ -84,9 +84,9 @@ void get_smm_info(uintptr_t *perm_smbase, size_t *perm_smsize,
 	*smm_save_state_size = sizeof(em64t101_smm_state_save_area_t);
 }
 
-static void update_save_state(int cpu, uintptr_t curr_smbase,
-				uintptr_t staggered_smbase,
-				struct smm_relocation_params *relo_params)
+static void update_save_state(uintptr_t curr_smbase,
+			      uintptr_t staggered_smbase,
+			      struct smm_relocation_params *relo_params)
 {
 	u32 smbase;
 	u32 iedbase;
@@ -122,7 +122,7 @@ void smm_relocation_handler(int cpu, uintptr_t curr_smbase,
 	printk(BIOS_DEBUG, "%s : CPU %d\n", __func__, cpu);
 
 	/* Make appropriate changes to the save state map. */
-	update_save_state(cpu, curr_smbase, staggered_smbase, relo_params);
+	update_save_state(curr_smbase, staggered_smbase, relo_params);
 
 	/* Write SMRR MSRs based on indicated support. */
 	mtrr_cap = rdmsr(MTRR_CAP_MSR);

From 4e55225f2c7335b8b34f6d35098151f5d43b48a3 Mon Sep 17 00:00:00 2001
From: Ana Carolina Cabral <ana.cpmelo95@gmail.com>
Date: Tue, 15 Apr 2025 10:19:00 -0300
Subject: [PATCH 0834/3886] mb/amd/crater: Add missing dxio descriptors

Add DT, WLAN, WWLAN, TB and XGBE port descriptors
according to PI source package #67683 (NDA).

Change-Id: Iccc74fd03f6833112b370ba503d9d33033609c5b
Signed-off-by: Ana Carolina Cabral <ana.cpmelo95@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87319
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
---
 src/mainboard/amd/crater/Kconfig              | 17 ++++
 .../amd/crater/port_descriptors_renoir.c      | 92 ++++++++++++++++++-
 2 files changed, 108 insertions(+), 1 deletion(-)

diff --git a/src/mainboard/amd/crater/Kconfig b/src/mainboard/amd/crater/Kconfig
index 61b8f3e6d5..0e43ed3624 100644
--- a/src/mainboard/amd/crater/Kconfig
+++ b/src/mainboard/amd/crater/Kconfig
@@ -98,6 +98,23 @@ config ENABLE_EVAL_19V
 	help
 	  Enable the 19V rail for Eval Card PCIe slot
 
+choice
+	prompt "XGBE/WWAN/WLAN/DT Selection"
+	default XGBE_WWAN_WLAN
+	help
+	  Select the configuration for GPP[0:3] lanes
+
+config XGBE_WWAN_WLAN
+	bool "XGBE_WWAN_WLAN"
+	help
+	  Use GPP[0:1] for XGBE (ETH_AIC_SLOT), GPP[2] for WWAN slot and GPP[3] for WLAN slot.
+
+config ETH_AIC_SLOT_ONLY
+	bool "DT Enablement"
+	help
+	  Use GPP[0:3] for as PCIE (ETH_AIC_SLOT) only
+endchoice
+
 if !EM100	# EM100 defaults in soc/amd/common/blocks/spi/Kconfig
 config EFS_SPI_READ_MODE
 	default 3	# Quad IO (1-1-4)
diff --git a/src/mainboard/amd/crater/port_descriptors_renoir.c b/src/mainboard/amd/crater/port_descriptors_renoir.c
index 757dab1b49..7ecb797a28 100644
--- a/src/mainboard/amd/crater/port_descriptors_renoir.c
+++ b/src/mainboard/amd/crater/port_descriptors_renoir.c
@@ -52,6 +52,86 @@
 	.port_params = {PP_PSPP_AC, 0x133, PP_PSPP_DC, 0x122}, \
 }
 
+#define dt_dxio_descriptor {  \
+	.engine_type = PCIE_ENGINE,  \
+	.port_present = true,  \
+	.start_logical_lane = 0,  \
+	.end_logical_lane = 3,  \
+	.device_number = 1,  \
+	.function_number = 2,  \
+	.link_aspm = ASPM_L1,  \
+	.link_aspm_L1_1 = true,  \
+	.link_aspm_L1_2 = true,  \
+	.turn_off_unused_lanes = false,  \
+	.clk_req = CLK_REQ5,  \
+	.port_params = {PP_PSPP_AC, 0x133, PP_PSPP_DC, 0x122},  \
+}
+
+#define wwan_dxio_descriptor {	\
+	.engine_type = PCIE_ENGINE,  \
+	.port_present = true,  \
+	.start_logical_lane = 2,  \
+	.end_logical_lane = 2,  \
+	.device_number = 1,  \
+	.function_number = 3,  \
+	.link_aspm = ASPM_L1,  \
+	.link_aspm_L1_1 = true,  \
+	.link_aspm_L1_2 = true,  \
+	.turn_off_unused_lanes = false,  \
+	.clk_req = CLK_REQ2,  \
+	.port_params = {PP_PSPP_AC, 0x133, PP_PSPP_DC, 0x122},  \
+}
+
+#define wlan_dxio_descriptor {  \
+	.engine_type = PCIE_ENGINE,  \
+	.port_present = true,  \
+	.start_logical_lane = 3,  \
+	.end_logical_lane = 3,  \
+	.device_number = 2,  \
+	.function_number = 2,  \
+	.link_aspm = ASPM_L1,  \
+	.link_aspm_L1_1 = true,  \
+	.link_aspm_L1_2 = true,  \
+	.turn_off_unused_lanes = false,  \
+	.clk_req = CLK_REQ6,  \
+	.port_params = {PP_PSPP_AC, 0x133, PP_PSPP_DC, 0x122},  \
+}
+
+#define tb_dxio_descriptor {  \
+	.engine_type = PCIE_ENGINE,  \
+	.port_present = true,  \
+	.start_logical_lane = 4,  \
+	.end_logical_lane = 7,  \
+	.device_number = 2,  \
+	.function_number = 3,  \
+	.link_aspm = ASPM_L1,  \
+	.link_aspm_L1_1 = true,  \
+	.link_aspm_L1_2 = true,  \
+	.turn_off_unused_lanes = false,  \
+	.clk_req = CLK_REQ4_GFX,  \
+	.port_params = {PP_PSPP_AC, 0x133, PP_PSPP_DC, 0x122},  \
+}
+
+/* XGBE ETHERNET PORTS Entry Port 0 */
+// XGBE SGMII interface: Physical lane 4, Logical lane 0
+// NOTE: Ancillary data not yet captured here due to FSP limitations
+#define xgbe_port0_dxio_descriptor {  \
+	.port_present = true,  \
+	.engine_type = ETHERNET_ENGINE,  \
+	.start_logical_lane = 0,  \
+	.end_logical_lane = 0,  \
+}
+
+/* XGBE ETHERNET PORTS Entry Port 1 */
+// XGBE SGMII interface: Physical lane 5, Logical lane 1
+// NOTE: Ancillary data not yet captured here due to FSP limitations
+#define xgbe_port1_dxio_descriptor {  \
+	.port_present = true,  \
+	.engine_type = ETHERNET_ENGINE,  \
+	.start_logical_lane = 1,  \
+	.end_logical_lane = 1,  \
+}
+
 static fsp_ddi_descriptor crater_ddi_descriptors[] = {
 	{ /* DDI0 - DP */
 		.connector_type = DDI_DP,
@@ -103,7 +183,17 @@ void mainboard_get_dxio_ddi_descriptors(
 
 	static const fsp_dxio_descriptor crater_dxio_descriptors[] = {
 		mxm_dxio_descriptor,
-		ssd_dxio_descriptor
+		ssd_dxio_descriptor,
+		tb_dxio_descriptor,
+#if CONFIG(ETH_AIC_SLOT_ONLY)
+		dt_dxio_descriptor, // GPP 0~3
+#endif
+#if CONFIG(XGBE_WWAN_WLAN)
+		xgbe_port0_dxio_descriptor, // GPP 0
+		xgbe_port1_dxio_descriptor, // GPP 1
+		wwan_dxio_descriptor, // GPP 2
+		wlan_dxio_descriptor // GPP 3
+#endif
 	};
 
 	*dxio_descs = crater_dxio_descriptors;

From 443f514365013eea6be6015da97466ac0cf32459 Mon Sep 17 00:00:00 2001
From: Ana Carolina Cabral <ana.cpmelo95@gmail.com>
Date: Mon, 14 Apr 2025 10:32:37 -0300
Subject: [PATCH 0835/3886] mb/amd/crater: Add touchscreen support

Add edp I2C touch panel suport.

Change-Id: I33f13fc4c76dfe7cb9abf114d31e83e7ad24bdb9
Signed-off-by: Ana Carolina Cabral <ana.cpmelo95@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87219
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
---
 src/mainboard/amd/crater/Kconfig              |  1 +
 src/mainboard/amd/crater/devicetree_renoir.cb | 16 +++++++++++++++-
 src/mainboard/amd/crater/ec.c                 | 18 ++++++++++++++++++
 3 files changed, 34 insertions(+), 1 deletion(-)

diff --git a/src/mainboard/amd/crater/Kconfig b/src/mainboard/amd/crater/Kconfig
index 0e43ed3624..620bc3d084 100644
--- a/src/mainboard/amd/crater/Kconfig
+++ b/src/mainboard/amd/crater/Kconfig
@@ -6,6 +6,7 @@ config BOARD_AMD_CRATER_COMMON
 	select EC_ACPI
 	select SOC_AMD_COMMON_BLOCK_USE_ESPI if !SOC_AMD_COMMON_BLOCK_SIMNOW_BUILD
 	select DRIVERS_PCIE_RTD3_DEVICE
+	select DRIVERS_I2C_HID
 	select MAINBOARD_HAS_CHROMEOS
 	select HAVE_ACPI_RESUME
 	select PCIEXP_ASPM
diff --git a/src/mainboard/amd/crater/devicetree_renoir.cb b/src/mainboard/amd/crater/devicetree_renoir.cb
index cc9ad45dd1..33f25e9c29 100644
--- a/src/mainboard/amd/crater/devicetree_renoir.cb
+++ b/src/mainboard/amd/crater/devicetree_renoir.cb
@@ -131,7 +131,21 @@ chip soc/amd/cezanne
 	end
 
 	device ref i2c_0 on end
-	device ref i2c_1 on end
+	device ref i2c_1 on # eDP Touch Panel
+		chip drivers/i2c/hid
+			register "generic.hid" = ""PNP0C50""
+			register "generic.desc" = ""ELAN Touchscreen""
+			register "generic.detect" = "1"
+			register "generic.irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPIO_4)"
+			register "generic.enable_delay_ms" = "1"
+			register "generic.reset_delay_ms" = "20"
+			register "generic.reset_off_delay_ms" = "2"
+			register "generic.stop_off_delay_ms" = "2"
+			register "generic.has_power_resource" = "1"
+			register "hid_desc_reg_offset" = "0x01"
+			device i2c 9 on end
+		end
+	end
 	device ref i2c_2 on end
 	device ref i2c_3 on end
 	device ref uart_0 on end # UART0
diff --git a/src/mainboard/amd/crater/ec.c b/src/mainboard/amd/crater/ec.c
index b3ef97a8e9..0a283d05da 100644
--- a/src/mainboard/amd/crater/ec.c
+++ b/src/mainboard/amd/crater/ec.c
@@ -63,6 +63,10 @@
 #define   ECA_SMBUS1_EN		BIT(1)
 #define   ECA_SMBUS0_EN		BIT(0)
 
+#define EC_GPIO_B_ADDR		0xAB
+#define   ECB_TPNL_EN		BIT(2)
+#define   ECB_TPNL_PWR_EN	BIT(0)
+
 #define EC_GPIO_C_ADDR		0xAC
 #define   ECC_TPNL_BUF_EN	BIT(6)
 #define   ECC_TPAD_BUF_EN	BIT(5)
@@ -141,6 +145,20 @@ static void configure_ec_gpio(void)
 	}
 	printk(BIOS_SPEW, "Write reg [0x%02x] = 0x%02x\n", EC_GPIO_8_ADDR, tmp);
 	ec_write(EC_GPIO_8_ADDR, tmp);
+
+	/* eDP Touch panel  */
+	if(CONFIG(ENABLE_EDP)) {
+		tmp = ec_read(EC_GPIO_9_ADDR);
+		tmp &= ~(EC9_MUX0_S1);
+		tmp |= EC9_MUX0_S0;
+		printk(BIOS_SPEW, "Write reg [0x%02x] = 0x%02x\n", EC_GPIO_9_ADDR, tmp);
+		ec_write(EC_GPIO_9_ADDR, tmp);
+
+		tmp  = ec_read(EC_GPIO_B_ADDR);
+		tmp |= ECB_TPNL_EN | ECB_TPNL_EN;
+		printk(BIOS_SPEW, "Write reg [0x%02x] = 0x%02x\n", EC_GPIO_B_ADDR, tmp);
+		ec_write(EC_GPIO_B_ADDR, tmp);
+	}
 }
 
 static const struct soc_amd_gpio RevA_gpio_set_stage_ram[] = {

From b249275e3d72a7ea3b2f6657bb312486c9dde0f8 Mon Sep 17 00:00:00 2001
From: Ana Carolina Cabral <ana.cpmelo95@gmail.com>
Date: Mon, 14 Apr 2025 10:27:47 -0300
Subject: [PATCH 0836/3886] mb/amd/crater: Fix some ec defines

Fix some ec bits name and indentation.

Change-Id: I23407e4e7be661980c16ef96dd0efabb3898e3da
Signed-off-by: Ana Carolina Cabral <ana.cpmelo95@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87304
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/amd/crater/ec.c | 35 +++++++++++++++++------------------
 1 file changed, 17 insertions(+), 18 deletions(-)

diff --git a/src/mainboard/amd/crater/ec.c b/src/mainboard/amd/crater/ec.c
index 0a283d05da..fa7c21fa1b 100644
--- a/src/mainboard/amd/crater/ec.c
+++ b/src/mainboard/amd/crater/ec.c
@@ -36,22 +36,21 @@
 #define   EC7_CAM1_EN		BIT(0)
 
 #define EC_GPIO_8_ADDR		0xA8
-#define EC8_ODD_PWR_EN     BIT(0)
-#define EC8_HDD_PWR_EN     BIT(1)
-#define EC8_M2SSD_PWREN    BIT(5)
-#define EC8_WL_RADIO       BIT(6)
-#define EC8_BT_RADIO       BIT(7)
+#define     EC8_ODD_PWR_EN	BIT(0)
+#define     EC8_HDD_PWR_EN	BIT(1)
+#define     EC8_M2SSD_PWREN	BIT(5)
+#define     EC8_WL_RADIO	BIT(6)
+#define     EC8_BT_RADIO	BIT(7)
 
 #define EC_GPIO_9_ADDR		0xA9
-#define SMBUS1_DEV_MUX_SW   BIT(0)       // ECRAMxA9[0]
-#define SMBUS0_DEV_MUX_SW   BIT(1)       // ECRAMxA9[1]
-#define MUX0_S0             BIT(2)       // ECRAMxA9[2]
-#define MUX0_S1             BIT(3)       // ECRAMxA9[3]
-#define MUX1_S0             BIT(4)       // ECRAMxA9[4]
-#define MUX1_S1             BIT(5)       // ECRAMxA9[5]
-#define MUX2_S0             BIT(6)       // ECRAMxA9[6]
-#define MUX2_S1             BIT(7)       // ECRAMxA9[7]
-
+#define    EC9_MUX2_S1             BIT(7)
+#define    EC9_MUX2_S0             BIT(6)
+#define    EC9_MUX1_S1             BIT(5)
+#define    EC9_MUX1_S0             BIT(4)
+#define    EC9_MUX0_S1             BIT(3)
+#define    EC9_MUX0_S0             BIT(2)
+#define    EC9_SMBUS0_DEV_MUX_SW   BIT(1)
+#define    EC9_SMBUS1_DEV_MUX_SW   BIT(0)
 
 #define EC_GPIO_A_ADDR		0xAA
 #define   ECA_MUX2_S0		BIT(7)
@@ -128,17 +127,17 @@ static void configure_ec_gpio(void)
 
 	tmp = ec_read(EC_GPIO_7_ADDR);
 	printk(BIOS_SPEW, "A7: Write reg [0x%02x] = 0x%02x\n", EC_GPIO_7_ADDR, tmp);
-	if (ENABLE_M2_SSD1) {
-		tmp |= (EC7_ODD_SSD_SW|EC7_SSD_HDD_SW);
+	if (CONFIG(ENABLE_M2_SSD1)) {
+		tmp |= (EC7_ODD_SSD_SW | EC7_SSD_HDD_SW);
 	} else {
-		tmp &= ~(EC7_ODD_SSD_SW|EC7_SSD_HDD_SW);
+		tmp &= ~(EC7_ODD_SSD_SW | EC7_SSD_HDD_SW);
 	}
 	printk(BIOS_SPEW, "Write reg [0x%02x] = 0x%02x\n", EC_GPIO_7_ADDR, tmp);
 	ec_write(EC_GPIO_7_ADDR, tmp);
 
 	tmp = ec_read(EC_GPIO_8_ADDR);
 	printk(BIOS_SPEW, "A8: Write reg [0x%02x] = 0x%02x\n", EC_GPIO_8_ADDR, tmp);
-	if (ENABLE_M2_SSD1) {
+	if (CONFIG(ENABLE_M2_SSD1)) {
 		tmp |= EC8_M2SSD_PWREN;
 	} else {
 		tmp &= ~EC8_M2SSD_PWREN;

From 1e0941c2950897578bae54f06e1738bdf677c63c Mon Sep 17 00:00:00 2001
From: Sowmya Aralguppe <sowmya.aralguppe@intel.com>
Date: Tue, 22 Apr 2025 23:22:49 +0530
Subject: [PATCH 0837/3886] mb/google/ocelot: Select Wildcat Lake(WCL) SoC
 config

TEST=Compiled and Verified on Wildcat Lake Simulation Platform.

Change-Id: I0eed357931dfdc74509e6ed8c536fecba5a019f9
Signed-off-by: Sowmya Aralguppe <sowmya.aralguppe@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87421
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
---
 src/mainboard/google/ocelot/Kconfig | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/mainboard/google/ocelot/Kconfig b/src/mainboard/google/ocelot/Kconfig
index 8383c8fb3e..7060929fc7 100644
--- a/src/mainboard/google/ocelot/Kconfig
+++ b/src/mainboard/google/ocelot/Kconfig
@@ -37,8 +37,8 @@ config BOARD_GOOGLE_OCELOT_COMMON
 	select SOC_INTEL_COMMON_BLOCK_VARIANT_POWER_LIMIT
 	select SOC_INTEL_CSE_LITE_SYNC_BY_PAYLOAD
 	select SOC_INTEL_CSE_SEND_EOP_BY_PAYLOAD
-	select SOC_INTEL_PANTHERLAKE_U_H
 	select SOC_INTEL_TCSS_USE_PDC_PMC_USBC_MUX_CONFIGURATION
+	select SOC_INTEL_WILDCATLAKE
 
 config BOARD_GOOGLE_BASEBOARD_OCELOT
 	def_bool n

From b3bdffa47511483690a47e506944722f8e46f5c8 Mon Sep 17 00:00:00 2001
From: Vince Liu <vince-wl.liu@mediatek.corp-partner.google.com>
Date: Fri, 18 Apr 2025 15:24:12 +0800
Subject: [PATCH 0838/3886] soc/mediatek/common: Move I2C functions to common
 code

To promote code reuse and maintainability, move i2c functions to common
folder. The function prototype "mtk_i2c_bus_init(uint8_t bus)" used by
some legacy platforms are changed to "mtk_i2c_bus_init(uint8_t bus,
uint32_t speed)" for better API integration.

BUG=b:379008996
BRANCH=none
TEST=build passed.

Signed-off-by: Vince Liu <vince-wl.liu@mediatek.corp-partner.google.com>
Change-Id: I6ac7009f5af4e6379d3f73aec61d0f4abd28471c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87352
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/google/asurada/mainboard.c      |  2 +-
 src/mainboard/google/kukui/boardid.c          |  2 +-
 src/mainboard/google/kukui/panel_anx7625.c    |  2 +-
 src/mainboard/google/kukui/panel_ps8640.c     |  2 +-
 src/mainboard/google/oak/bootblock.c          |  2 +-
 src/mainboard/google/oak/mainboard.c          |  6 ++--
 src/soc/mediatek/common/i2c_common.c          | 29 +++++++++++++++++++
 .../mediatek/common/include/soc/i2c_common.h  |  2 ++
 src/soc/mediatek/mt8173/i2c.c                 |  3 +-
 src/soc/mediatek/mt8173/include/soc/i2c.h     |  2 --
 src/soc/mediatek/mt8183/i2c.c                 |  5 ++--
 src/soc/mediatek/mt8183/include/soc/i2c.h     |  2 --
 src/soc/mediatek/mt8186/Makefile.mk           |  2 +-
 src/soc/mediatek/mt8186/i2c.c                 | 24 +--------------
 src/soc/mediatek/mt8186/include/soc/i2c.h     |  2 --
 src/soc/mediatek/mt8188/Makefile.mk           |  2 +-
 src/soc/mediatek/mt8188/i2c.c                 | 24 +--------------
 src/soc/mediatek/mt8188/include/soc/i2c.h     |  2 --
 src/soc/mediatek/mt8192/i2c.c                 |  5 ++--
 src/soc/mediatek/mt8192/include/soc/i2c.h     |  2 --
 src/soc/mediatek/mt8195/Makefile.mk           |  2 +-
 src/soc/mediatek/mt8195/i2c.c                 | 24 +--------------
 src/soc/mediatek/mt8195/include/soc/i2c.h     |  2 --
 src/soc/mediatek/mt8196/Makefile.mk           |  2 +-
 src/soc/mediatek/mt8196/i2c.c                 | 24 +--------------
 src/soc/mediatek/mt8196/include/soc/i2c.h     |  2 --
 26 files changed, 55 insertions(+), 123 deletions(-)
 create mode 100644 src/soc/mediatek/common/i2c_common.c

diff --git a/src/mainboard/google/asurada/mainboard.c b/src/mainboard/google/asurada/mainboard.c
index 358717b690..6a0d433ca4 100644
--- a/src/mainboard/google/asurada/mainboard.c
+++ b/src/mainboard/google/asurada/mainboard.c
@@ -83,7 +83,7 @@ static bool configure_display(void)
 	printk(BIOS_INFO, "%s: Starting display init\n", __func__);
 
 	configure_backlight_and_bridge();
-	mtk_i2c_bus_init(i2c_bus);
+	mtk_i2c_bus_init(i2c_bus, I2C_SPEED_FAST);
 
 	if (anx7625_init(i2c_bus)) {
 		printk(BIOS_ERR, "%s: Can't init ANX7625 bridge\n", __func__);
diff --git a/src/mainboard/google/kukui/boardid.c b/src/mainboard/google/kukui/boardid.c
index 117475680f..a15f6d08c9 100644
--- a/src/mainboard/google/kukui/boardid.c
+++ b/src/mainboard/google/kukui/boardid.c
@@ -128,7 +128,7 @@ static uint8_t wfc_id(void)
 		[1] = 0x5035,  /* GC5035 */
 	};
 
-	mtk_i2c_bus_init(bus);
+	mtk_i2c_bus_init(bus, I2C_SPEED_FAST);
 
 	/* Turn on camera sensor EEPROM */
 	pwrap_write(PMIC_LDO_VCAMIO_CON0, 0x1);
diff --git a/src/mainboard/google/kukui/panel_anx7625.c b/src/mainboard/google/kukui/panel_anx7625.c
index 90a041b42a..45cf27c64c 100644
--- a/src/mainboard/google/kukui/panel_anx7625.c
+++ b/src/mainboard/google/kukui/panel_anx7625.c
@@ -60,7 +60,7 @@ struct panel_description *get_panel_description(int panel_id)
 	/* To read panel EDID, we have to first power on anx7625. */
 	power_on_anx7625();
 
-	mtk_i2c_bus_init(ANX7625_I2C_BUS);
+	mtk_i2c_bus_init(ANX7625_I2C_BUS, I2C_SPEED_FAST);
 
 	if (anx7625_init(ANX7625_I2C_BUS)) {
 		printk(BIOS_ERR, "Can't init ANX7625 bridge.\n");
diff --git a/src/mainboard/google/kukui/panel_ps8640.c b/src/mainboard/google/kukui/panel_ps8640.c
index c4e90ea81c..c1e8c4cc2c 100644
--- a/src/mainboard/google/kukui/panel_ps8640.c
+++ b/src/mainboard/google/kukui/panel_ps8640.c
@@ -49,7 +49,7 @@ struct panel_description *get_panel_description(int panel_id)
 	power_on_ps8640();
 
 	u8 i2c_bus = 4, i2c_addr = 0x08;
-	mtk_i2c_bus_init(i2c_bus);
+	mtk_i2c_bus_init(i2c_bus, I2C_SPEED_FAST);
 
 	ps8640_init(i2c_bus, i2c_addr);
 	struct edid *edid = &ps8640_data.edid;
diff --git a/src/mainboard/google/oak/bootblock.c b/src/mainboard/google/oak/bootblock.c
index dd3d7a362a..365b80311e 100644
--- a/src/mainboard/google/oak/bootblock.c
+++ b/src/mainboard/google/oak/bootblock.c
@@ -70,7 +70,7 @@ void bootblock_mainboard_init(void)
 		gpio_output(GPIO(SRCLKENAI2), 1);
 
 	/* Init i2c bus 2 Timing register for TPM */
-	mtk_i2c_bus_init(CONFIG_DRIVER_TPM_I2C_BUS);
+	mtk_i2c_bus_init(CONFIG_DRIVER_TPM_I2C_BUS, I2C_SPEED_FAST);
 
 	mtk_spi_init(CONFIG_EC_GOOGLE_CHROMEEC_SPI_BUS, SPI_PAD1_MASK, 6*MHz,
 		     0);
diff --git a/src/mainboard/google/oak/mainboard.c b/src/mainboard/google/oak/mainboard.c
index 55ef91aad1..9c8481f621 100644
--- a/src/mainboard/google/oak/mainboard.c
+++ b/src/mainboard/google/oak/mainboard.c
@@ -26,7 +26,7 @@ enum {
 
 static void configure_ext_buck(void)
 {
-	mtk_i2c_bus_init(EXT_BUCK_I2C_BUS);
+	mtk_i2c_bus_init(EXT_BUCK_I2C_BUS, I2C_SPEED_FAST);
 
 	switch (board_id() + CONFIG_BOARD_ID_ADJUSTMENT) {
 	case 3:
@@ -97,7 +97,7 @@ static void configure_audio(void)
 	}
 
 	/* Init i2c bus Timing register for audio codecs */
-	mtk_i2c_bus_init(CODEC_I2C_BUS);
+	mtk_i2c_bus_init(CODEC_I2C_BUS, I2C_SPEED_FAST);
 
 	/* set I2S clock to 48KHz */
 	mt_pll_set_aud_div(48 * KHz);
@@ -193,7 +193,7 @@ static int read_edid_from_ps8640(struct edid *edid)
 		i2c_addr = 0x18;
 	}
 
-	mtk_i2c_bus_init(i2c_bus);
+	mtk_i2c_bus_init(i2c_bus, I2C_SPEED_FAST);
 
 	ps8640_init(i2c_bus, i2c_addr);
 	if (ps8640_get_edid(i2c_bus, i2c_addr, edid)) {
diff --git a/src/soc/mediatek/common/i2c_common.c b/src/soc/mediatek/common/i2c_common.c
new file mode 100644
index 0000000000..d68fb87e53
--- /dev/null
+++ b/src/soc/mediatek/common/i2c_common.c
@@ -0,0 +1,29 @@
+/* SPDX-License-Identifier: GPL-2.0-only OR MIT */
+
+#include <console/console.h>
+#include <device/mmio.h>
+#include <soc/i2c.h>
+#include <soc/i2c_common.h>
+#include <device/i2c_simple.h>
+
+void mtk_i2c_bus_init(uint8_t bus, uint32_t speed)
+{
+	mtk_i2c_speed_init(bus, speed);
+	mtk_i2c_set_gpio_pinmux(bus);
+}
+
+void mtk_i2c_dump_more_info(struct mt_i2c_regs *regs)
+{
+	printk(BIOS_DEBUG, "LTIMING %x\nCLK_DIV %x\n",
+	       read32(&regs->ltiming),
+	       read32(&regs->clock_div));
+}
+
+void mtk_i2c_config_timing(struct mt_i2c_regs *regs, struct mtk_i2c *bus_ctrl)
+{
+	write32(&regs->clock_div, bus_ctrl->ac_timing.inter_clk_div);
+	write32(&regs->timing, bus_ctrl->ac_timing.htiming);
+	write32(&regs->ltiming, bus_ctrl->ac_timing.ltiming);
+	write32(&regs->hs, bus_ctrl->ac_timing.hs);
+	write32(&regs->ext_conf, bus_ctrl->ac_timing.ext);
+}
diff --git a/src/soc/mediatek/common/include/soc/i2c_common.h b/src/soc/mediatek/common/include/soc/i2c_common.h
index 63eef92f27..d59fcce2d2 100644
--- a/src/soc/mediatek/common/include/soc/i2c_common.h
+++ b/src/soc/mediatek/common/include/soc/i2c_common.h
@@ -154,5 +154,7 @@ int mtk_i2c_calculate_speed(uint8_t bus, uint32_t clk_src,
 			    uint32_t *timing_sample_cnt);
 void mtk_i2c_speed_init(uint8_t bus, uint32_t speed);
 void mtk_i2c_config_timing(struct mt_i2c_regs *regs, struct mtk_i2c *bus_ctrl);
+void mtk_i2c_set_gpio_pinmux(uint8_t bus);
+void mtk_i2c_bus_init(uint8_t bus, uint32_t speed);
 
 #endif
diff --git a/src/soc/mediatek/mt8173/i2c.c b/src/soc/mediatek/mt8173/i2c.c
index 9cd20cf465..a87dd0b5db 100644
--- a/src/soc/mediatek/mt8173/i2c.c
+++ b/src/soc/mediatek/mt8173/i2c.c
@@ -60,13 +60,14 @@ _Static_assert(ARRAY_SIZE(mtk_i2c_bus_controller) == I2C_BUS_NUMBER,
 #define I2CLOG(fmt, arg...)
 #endif /* CONFIG_DEBUG_I2C */
 
-void mtk_i2c_bus_init(uint8_t bus)
+void mtk_i2c_bus_init(uint8_t bus, uint32_t speed)
 {
 	uint8_t step_div;
 	uint32_t i2c_freq;
 	const uint8_t sample_div = 1;
 
 	assert(bus < ARRAY_SIZE(mtk_i2c_bus_controller));
+	assert(speed == I2C_SPEED_FAST);
 
 	/* Calculate i2c frequency */
 	step_div = DIV_ROUND_UP(I2C_CLK_HZ, (400 * KHz * sample_div * 2));
diff --git a/src/soc/mediatek/mt8173/include/soc/i2c.h b/src/soc/mediatek/mt8173/include/soc/i2c.h
index 02a21817d9..cc23f547ee 100644
--- a/src/soc/mediatek/mt8173/include/soc/i2c.h
+++ b/src/soc/mediatek/mt8173/include/soc/i2c.h
@@ -42,6 +42,4 @@ struct mt_i2c_regs {
 
 check_member(mt_i2c_regs, debug_stat, 0x64);
 
-void mtk_i2c_bus_init(uint8_t bus);
-
 #endif /* SOC_MEDIATEK_MT8173_I2C_H */
diff --git a/src/soc/mediatek/mt8183/i2c.c b/src/soc/mediatek/mt8183/i2c.c
index c23377e8af..36354d2809 100644
--- a/src/soc/mediatek/mt8183/i2c.c
+++ b/src/soc/mediatek/mt8183/i2c.c
@@ -84,7 +84,7 @@ static const struct pad_func i2c_funcs[I2C_BUS_NUMBER][2] = {
 	},
 };
 
-static void mtk_i2c_set_gpio_pinmux(uint8_t bus)
+void mtk_i2c_set_gpio_pinmux(uint8_t bus)
 {
 	assert(bus < I2C_BUS_NUMBER);
 
@@ -122,8 +122,9 @@ static void mtk_i2c_speed_init_soc(uint8_t bus)
 		clock_div - 1);
 }
 
-void mtk_i2c_bus_init(uint8_t bus)
+void mtk_i2c_bus_init(uint8_t bus, uint32_t speed)
 {
+	assert(speed == I2C_SPEED_FAST);
 	mtk_i2c_speed_init_soc(bus);
 	mtk_i2c_set_gpio_pinmux(bus);
 }
diff --git a/src/soc/mediatek/mt8183/include/soc/i2c.h b/src/soc/mediatek/mt8183/include/soc/i2c.h
index ebe75facce..237a182da9 100644
--- a/src/soc/mediatek/mt8183/include/soc/i2c.h
+++ b/src/soc/mediatek/mt8183/include/soc/i2c.h
@@ -46,6 +46,4 @@ struct mt_i2c_regs {
 
 check_member(mt_i2c_regs, multi_dma, 0xf8c);
 
-void mtk_i2c_bus_init(uint8_t bus);
-
 #endif /* SOC_MEDIATEK_MT8183_I2C_H */
diff --git a/src/soc/mediatek/mt8186/Makefile.mk b/src/soc/mediatek/mt8186/Makefile.mk
index c6c47fdd92..4e0526c0e5 100644
--- a/src/soc/mediatek/mt8186/Makefile.mk
+++ b/src/soc/mediatek/mt8186/Makefile.mk
@@ -5,7 +5,7 @@ ifeq ($(CONFIG_SOC_MEDIATEK_MT8186),y)
 all-y += ../common/cpu_id.c
 all-y += ../common/flash_controller.c
 all-y += ../common/gpio_eint_v1.c ../common/gpio.c ../common/gpio_op.c  gpio.c
-all-y += ../common/i2c.c i2c.c
+all-y += ../common/i2c.c ../common/i2c_common.c i2c.c
 all-y += ../common/pll.c pll.c
 all-$(CONFIG_SPI_FLASH) += ../common/spi.c spi.c
 all-y += ../common/timer.c ../common/timer_prepare.c
diff --git a/src/soc/mediatek/mt8186/i2c.c b/src/soc/mediatek/mt8186/i2c.c
index 536627583e..64506a625e 100644
--- a/src/soc/mediatek/mt8186/i2c.c
+++ b/src/soc/mediatek/mt8186/i2c.c
@@ -101,7 +101,7 @@ static const struct pad_func i2c_funcs[I2C_BUS_NUMBER][2] = {
 	},
 };
 
-static void mtk_i2c_set_gpio_pinmux(uint8_t bus)
+void mtk_i2c_set_gpio_pinmux(uint8_t bus)
 {
 	assert(bus < I2C_BUS_NUMBER);
 
@@ -111,25 +111,3 @@ static void mtk_i2c_set_gpio_pinmux(uint8_t bus)
 		gpio_set_pull(ptr[i].gpio, GPIO_PULL_ENABLE, ptr[i].select);
 	}
 }
-
-void mtk_i2c_bus_init(uint8_t bus, uint32_t speed)
-{
-	mtk_i2c_speed_init(bus, speed);
-	mtk_i2c_set_gpio_pinmux(bus);
-}
-
-void mtk_i2c_dump_more_info(struct mt_i2c_regs *regs)
-{
-	printk(BIOS_DEBUG, "LTIMING %x\nCLK_DIV %x\n",
-	       read32(&regs->ltiming),
-	       read32(&regs->clock_div));
-}
-
-void mtk_i2c_config_timing(struct mt_i2c_regs *regs, struct mtk_i2c *bus_ctrl)
-{
-	write32(&regs->clock_div, bus_ctrl->ac_timing.inter_clk_div);
-	write32(&regs->timing, bus_ctrl->ac_timing.htiming);
-	write32(&regs->ltiming, bus_ctrl->ac_timing.ltiming);
-	write32(&regs->hs, bus_ctrl->ac_timing.hs);
-	write32(&regs->ext_conf, bus_ctrl->ac_timing.ext);
-}
diff --git a/src/soc/mediatek/mt8186/include/soc/i2c.h b/src/soc/mediatek/mt8186/include/soc/i2c.h
index 4024e7de6b..28da112efc 100644
--- a/src/soc/mediatek/mt8186/include/soc/i2c.h
+++ b/src/soc/mediatek/mt8186/include/soc/i2c.h
@@ -65,6 +65,4 @@ enum {
 
 check_member(mt_i2c_regs, multi_dma, 0xf8c);
 
-void mtk_i2c_bus_init(uint8_t bus, uint32_t speed);
-
 #endif /* SOC_MEDIATEK_MT8186_I2C_H */
diff --git a/src/soc/mediatek/mt8188/Makefile.mk b/src/soc/mediatek/mt8188/Makefile.mk
index dc6b649299..e28c50d02e 100644
--- a/src/soc/mediatek/mt8188/Makefile.mk
+++ b/src/soc/mediatek/mt8188/Makefile.mk
@@ -3,7 +3,7 @@ ifeq ($(CONFIG_SOC_MEDIATEK_MT8188),y)
 
 all-y += ../common/flash_controller.c
 all-y += ../common/gpio_eint_v1.c ../common/gpio.c ../common/gpio_op.c gpio.c
-all-y += ../common/i2c.c i2c.c
+all-y += ../common/i2c.c ../common/i2c_common.c i2c.c
 all-y += ../common/pll.c pll.c
 all-$(CONFIG_SPI_FLASH) += ../common/spi.c spi.c
 all-y += timer.c ../common/timer_prepare.c
diff --git a/src/soc/mediatek/mt8188/i2c.c b/src/soc/mediatek/mt8188/i2c.c
index edfe510202..6aae8fbc53 100644
--- a/src/soc/mediatek/mt8188/i2c.c
+++ b/src/soc/mediatek/mt8188/i2c.c
@@ -84,7 +84,7 @@ static const struct pad_func i2c_funcs[I2C_BUS_NUMBER][2] = {
 	},
 };
 
-static void mtk_i2c_set_gpio_pinmux(uint8_t bus)
+void mtk_i2c_set_gpio_pinmux(uint8_t bus)
 {
 	assert(bus < I2C_BUS_NUMBER);
 
@@ -94,25 +94,3 @@ static void mtk_i2c_set_gpio_pinmux(uint8_t bus)
 		gpio_set_pull(ptr[i].gpio, GPIO_PULL_ENABLE, ptr[i].select);
 	}
 }
-
-void mtk_i2c_bus_init(uint8_t bus, uint32_t speed)
-{
-	mtk_i2c_speed_init(bus, speed);
-	mtk_i2c_set_gpio_pinmux(bus);
-}
-
-void mtk_i2c_dump_more_info(struct mt_i2c_regs *regs)
-{
-	printk(BIOS_DEBUG, "LTIMING %x\nCLK_DIV %x\n",
-	       read32(&regs->ltiming),
-	       read32(&regs->clock_div));
-}
-
-void mtk_i2c_config_timing(struct mt_i2c_regs *regs, struct mtk_i2c *bus_ctrl)
-{
-	write32(&regs->clock_div, bus_ctrl->ac_timing.inter_clk_div);
-	write32(&regs->timing, bus_ctrl->ac_timing.htiming);
-	write32(&regs->ltiming, bus_ctrl->ac_timing.ltiming);
-	write32(&regs->hs, bus_ctrl->ac_timing.hs);
-	write32(&regs->ext_conf, bus_ctrl->ac_timing.ext);
-}
diff --git a/src/soc/mediatek/mt8188/include/soc/i2c.h b/src/soc/mediatek/mt8188/include/soc/i2c.h
index 104da9a7be..615660bde8 100644
--- a/src/soc/mediatek/mt8188/include/soc/i2c.h
+++ b/src/soc/mediatek/mt8188/include/soc/i2c.h
@@ -69,6 +69,4 @@ enum {
 
 check_member(mt_i2c_regs, dma_nreq, 0xf94);
 
-void mtk_i2c_bus_init(uint8_t bus, uint32_t speed);
-
 #endif /* SOC_MEDIATEK_MT8188_I2C_H */
diff --git a/src/soc/mediatek/mt8192/i2c.c b/src/soc/mediatek/mt8192/i2c.c
index 3e8c21e30a..278972a6e7 100644
--- a/src/soc/mediatek/mt8192/i2c.c
+++ b/src/soc/mediatek/mt8192/i2c.c
@@ -109,7 +109,7 @@ static const struct pad_func i2c_funcs[I2C_BUS_NUMBER][2] = {
 	},
 };
 
-static void mtk_i2c_set_gpio_pinmux(uint8_t bus)
+void mtk_i2c_set_gpio_pinmux(uint8_t bus)
 {
 	assert(bus < I2C_BUS_NUMBER);
 
@@ -169,8 +169,9 @@ static void mtk_i2c_speed_init_soc(uint8_t bus)
 	write32(&mtk_i2c_bus_controller[bus].i2c_regs->ext_conf, I2C_FS_START_CON);
 }
 
-void mtk_i2c_bus_init(uint8_t bus)
+void mtk_i2c_bus_init(uint8_t bus, uint32_t speed)
 {
+	assert(speed == I2C_SPEED_FAST);
 	mtk_i2c_speed_init_soc(bus);
 	mtk_i2c_set_gpio_pinmux(bus);
 }
diff --git a/src/soc/mediatek/mt8192/include/soc/i2c.h b/src/soc/mediatek/mt8192/include/soc/i2c.h
index fbf41e6c48..45d664e325 100644
--- a/src/soc/mediatek/mt8192/include/soc/i2c.h
+++ b/src/soc/mediatek/mt8192/include/soc/i2c.h
@@ -46,6 +46,4 @@ struct mt_i2c_regs {
 
 check_member(mt_i2c_regs, multi_dma, 0xf8c);
 
-void mtk_i2c_bus_init(uint8_t bus);
-
 #endif /* SOC_MEDIATEK_MT8192_I2C_H */
diff --git a/src/soc/mediatek/mt8195/Makefile.mk b/src/soc/mediatek/mt8195/Makefile.mk
index c460d5894f..5e4e98f121 100644
--- a/src/soc/mediatek/mt8195/Makefile.mk
+++ b/src/soc/mediatek/mt8195/Makefile.mk
@@ -4,7 +4,7 @@ ifeq ($(CONFIG_SOC_MEDIATEK_MT8195),y)
 # for bootblock, verstage, romstage, ramstage
 all-y += ../common/flash_controller.c
 all-y += ../common/gpio_eint_v1.c ../common/gpio.c ../common/gpio_op.c gpio.c
-all-y += ../common/i2c.c i2c.c
+all-y += ../common/i2c.c ../common/i2c_common.c i2c.c
 all-$(CONFIG_SPI_FLASH) += ../common/spi.c spi.c
 all-y += ../common/timer.c ../common/timer_prepare.c
 all-y += ../common/uart.c
diff --git a/src/soc/mediatek/mt8195/i2c.c b/src/soc/mediatek/mt8195/i2c.c
index 1fa9608fb9..a9593fed19 100644
--- a/src/soc/mediatek/mt8195/i2c.c
+++ b/src/soc/mediatek/mt8195/i2c.c
@@ -89,7 +89,7 @@ static const struct pad_func i2c_funcs[I2C_BUS_NUMBER][2] = {
 
 };
 
-static void mtk_i2c_set_gpio_pinmux(uint8_t bus)
+void mtk_i2c_set_gpio_pinmux(uint8_t bus)
 {
 	assert(bus < I2C_BUS_NUMBER);
 
@@ -100,25 +100,3 @@ static void mtk_i2c_set_gpio_pinmux(uint8_t bus)
 			gpio_set_pull(ptr[i].gpio, GPIO_PULL_ENABLE, ptr[i].select);
 	}
 }
-
-void mtk_i2c_bus_init(uint8_t bus, uint32_t speed)
-{
-	mtk_i2c_speed_init(bus, speed);
-	mtk_i2c_set_gpio_pinmux(bus);
-}
-
-void mtk_i2c_dump_more_info(struct mt_i2c_regs *regs)
-{
-	printk(BIOS_DEBUG, "LTIMING %x\nCLK_DIV %x\n",
-	       read32(&regs->ltiming),
-	       read32(&regs->clock_div));
-}
-
-void mtk_i2c_config_timing(struct mt_i2c_regs *regs, struct mtk_i2c *bus_ctrl)
-{
-	write32(&regs->clock_div, bus_ctrl->ac_timing.inter_clk_div);
-	write32(&regs->timing, bus_ctrl->ac_timing.htiming);
-	write32(&regs->ltiming, bus_ctrl->ac_timing.ltiming);
-	write32(&regs->hs, bus_ctrl->ac_timing.hs);
-	write32(&regs->ext_conf, bus_ctrl->ac_timing.ext);
-}
diff --git a/src/soc/mediatek/mt8195/include/soc/i2c.h b/src/soc/mediatek/mt8195/include/soc/i2c.h
index e7ba71474d..64d77ef410 100644
--- a/src/soc/mediatek/mt8195/include/soc/i2c.h
+++ b/src/soc/mediatek/mt8195/include/soc/i2c.h
@@ -59,6 +59,4 @@ enum {
 
 check_member(mt_i2c_regs, multi_dma, 0xf8c);
 
-void mtk_i2c_bus_init(uint8_t bus, uint32_t speed);
-
 #endif /* SOC_MEDIATEK_MT8195_I2C_H */
diff --git a/src/soc/mediatek/mt8196/Makefile.mk b/src/soc/mediatek/mt8196/Makefile.mk
index a1ee6fb304..5d6e1db74d 100644
--- a/src/soc/mediatek/mt8196/Makefile.mk
+++ b/src/soc/mediatek/mt8196/Makefile.mk
@@ -5,7 +5,7 @@ ifeq ($(CONFIG_SOC_MEDIATEK_MT8196),y)
 all-y += ../common/flash_controller.c
 all-y += ../common/gpio.c ../common/gpio_op.c gpio.c
 all-y += ../common/gpio_eint_v2.c gpio_eint.c
-all-y += ../common/i2c.c i2c.c
+all-y += ../common/i2c.c ../common/i2c_common.c i2c.c
 all-y += ../common/pll.c pll.c
 all-$(CONFIG_SPI_FLASH) += ../common/spi.c spi.c
 all-y += timer.c timer_prepare.c
diff --git a/src/soc/mediatek/mt8196/i2c.c b/src/soc/mediatek/mt8196/i2c.c
index c3d3ccb31c..21ae058fb8 100644
--- a/src/soc/mediatek/mt8196/i2c.c
+++ b/src/soc/mediatek/mt8196/i2c.c
@@ -156,7 +156,7 @@ static const struct pad_func i2c_funcs[I2C_BUS_NUMBER][2] = {
 	},
 };
 
-static void mtk_i2c_set_gpio_pinmux(uint8_t bus)
+void mtk_i2c_set_gpio_pinmux(uint8_t bus)
 {
 	assert(bus < I2C_BUS_NUMBER);
 
@@ -167,25 +167,3 @@ static void mtk_i2c_set_gpio_pinmux(uint8_t bus)
 		gpio_set_pull(ptr[i].gpio, GPIO_PULL_ENABLE, ptr[i].select);
 	}
 }
-
-void mtk_i2c_bus_init(uint8_t bus, uint32_t speed)
-{
-	mtk_i2c_speed_init(bus, speed);
-	mtk_i2c_set_gpio_pinmux(bus);
-}
-
-void mtk_i2c_dump_more_info(struct mt_i2c_regs *regs)
-{
-	printk(BIOS_DEBUG, "LTIMING %x\nCLK_DIV %x\n",
-	       read32(&regs->ltiming),
-	       read32(&regs->clock_div));
-}
-
-void mtk_i2c_config_timing(struct mt_i2c_regs *regs, struct mtk_i2c *bus_ctrl)
-{
-	write32(&regs->clock_div, bus_ctrl->ac_timing.inter_clk_div);
-	write32(&regs->timing, bus_ctrl->ac_timing.htiming);
-	write32(&regs->ltiming, bus_ctrl->ac_timing.ltiming);
-	write32(&regs->hs, bus_ctrl->ac_timing.hs);
-	write32(&regs->ext_conf, bus_ctrl->ac_timing.ext);
-}
diff --git a/src/soc/mediatek/mt8196/include/soc/i2c.h b/src/soc/mediatek/mt8196/include/soc/i2c.h
index 7dae2d804a..884902b2af 100644
--- a/src/soc/mediatek/mt8196/include/soc/i2c.h
+++ b/src/soc/mediatek/mt8196/include/soc/i2c.h
@@ -68,6 +68,4 @@ enum {
 
 check_member(mt_i2c_regs, fifo_thresh, 0xf8);
 
-void mtk_i2c_bus_init(uint8_t bus, uint32_t speed);
-
 #endif /* __SOC_MEDIATEK_MT8196_I2C_H__ */

From 934fcfb6a0d39c6ec9c64ecac6c2273b5fca4911 Mon Sep 17 00:00:00 2001
From: "ot_ryanw.wang" <ot_ryanw.wang@mediatek.com>
Date: Thu, 19 Dec 2024 10:07:47 +0800
Subject: [PATCH 0839/3886] soc/mediatek/mt8189: Add I2C driver support

Add I2C controller driver.

BUG=b:379008996
BRANCH=none
TEST=build passed

Signed-off-by: ot_ryanw.wang <ot_ryanw.wang@mediatek.com>
Change-Id: I4baa291a83ecce60eb2d41e329c2182f3ea273b7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87338
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
---
 src/soc/mediatek/mt8189/Makefile.mk           |   1 +
 src/soc/mediatek/mt8189/i2c.c                 | 114 ++++++++++++++++++
 .../mediatek/mt8189/include/soc/addressmap.h  |  18 +++
 src/soc/mediatek/mt8189/include/soc/i2c.h     |  81 +++++++++++++
 4 files changed, 214 insertions(+)
 create mode 100644 src/soc/mediatek/mt8189/i2c.c
 create mode 100644 src/soc/mediatek/mt8189/include/soc/i2c.h

diff --git a/src/soc/mediatek/mt8189/Makefile.mk b/src/soc/mediatek/mt8189/Makefile.mk
index feba664bec..56a7033eb3 100644
--- a/src/soc/mediatek/mt8189/Makefile.mk
+++ b/src/soc/mediatek/mt8189/Makefile.mk
@@ -4,6 +4,7 @@ ifeq ($(CONFIG_SOC_MEDIATEK_MT8189),y)
 
 all-y += ../common/flash_controller.c
 all-y += ../common/gpio.c ../common/gpio_op.c ../common/gpio_eint_v2.c gpio.c gpio_eint.c
+all-y += ../common/i2c.c ../common/i2c_common.c i2c.c
 all-$(CONFIG_SPI_FLASH) += spi.c
 all-y += ../common/timer_prepare.c timer.c
 all-y += ../common/uart.c
diff --git a/src/soc/mediatek/mt8189/i2c.c b/src/soc/mediatek/mt8189/i2c.c
new file mode 100644
index 0000000000..4f73d608ac
--- /dev/null
+++ b/src/soc/mediatek/mt8189/i2c.c
@@ -0,0 +1,114 @@
+/* SPDX-License-Identifier: GPL-2.0-only OR MIT */
+
+/*
+ * This file is created based on MT8189 Functional Specification
+ * Chapter number: 9.10
+ */
+
+#include <assert.h>
+#include <console/console.h>
+#include <device/i2c_simple.h>
+#include <device/mmio.h>
+#include <gpio.h>
+#include <soc/i2c.h>
+
+struct mtk_i2c mtk_i2c_bus_controller[] = {
+	[0] = {
+		.i2c_regs = (void *)I2C0_BASE,
+		.i2c_dma_regs = (void *)I2C0_DMA_BASE,
+		.mt_i2c_flag = I2C_APDMA_ASYNC,
+	},
+	[1] = {
+		.i2c_regs = (void *)I2C1_BASE,
+		.i2c_dma_regs = (void *)I2C1_DMA_BASE,
+		.mt_i2c_flag = I2C_APDMA_ASYNC,
+	},
+	[2] = {
+		.i2c_regs = (void *)I2C2_BASE,
+		.i2c_dma_regs = (void *)I2C2_DMA_BASE,
+		.mt_i2c_flag = I2C_APDMA_ASYNC,
+	},
+	[3] = {
+		.i2c_regs = (void *)I2C3_BASE,
+		.i2c_dma_regs = (void *)I2C3_DMA_BASE,
+		.mt_i2c_flag = I2C_APDMA_ASYNC,
+	},
+	[4] = {
+		.i2c_regs = (void *)I2C4_BASE,
+		.i2c_dma_regs = (void *)I2C4_DMA_BASE,
+		.mt_i2c_flag = I2C_APDMA_ASYNC,
+	},
+	[5] = {
+		.i2c_regs = (void *)I2C5_BASE,
+		.i2c_dma_regs = (void *)I2C5_DMA_BASE,
+		.mt_i2c_flag = I2C_APDMA_ASYNC,
+	},
+	[6] = {
+		.i2c_regs = (void *)I2C6_BASE,
+		.i2c_dma_regs = (void *)I2C6_DMA_BASE,
+		.mt_i2c_flag = I2C_APDMA_ASYNC,
+	},
+	[7] = {
+		.i2c_regs = (void *)I2C7_BASE,
+		.i2c_dma_regs = (void *)I2C7_DMA_BASE,
+		.mt_i2c_flag = I2C_APDMA_ASYNC,
+	},
+	[8] = {
+		.i2c_regs = (void *)I2C8_BASE,
+		.i2c_dma_regs = (void *)I2C8_DMA_BASE,
+		.mt_i2c_flag = I2C_APDMA_ASYNC,
+	},
+};
+
+_Static_assert(ARRAY_SIZE(mtk_i2c_bus_controller) == I2C_BUS_NUMBER,
+	       "Wrong size of mtk_i2c_bus_controller");
+
+static const struct pad_func i2c_funcs[I2C_BUS_NUMBER][2] = {
+	[0] = {
+		PAD_FUNC_UP(SCP_SDA0, SDA0),
+		PAD_FUNC_UP(SCP_SCL0, SCL0),
+	},
+	[1] = {
+		PAD_FUNC_UP(SCP_SDA1, SDA1),
+		PAD_FUNC_UP(SCP_SCL1, SCL1),
+	},
+	[2] = {
+		PAD_FUNC_UP(SDA2, SDA2),
+		PAD_FUNC_UP(SCL2, SCL2),
+	},
+	[3] = {
+		PAD_FUNC_UP(SDA3, SDA3),
+		PAD_FUNC_UP(SCL3, SCL3),
+	},
+	[4] = {
+		PAD_FUNC_UP(SDA4, SDA4),
+		PAD_FUNC_UP(SCL4, SCL4),
+	},
+	[5] = {
+		PAD_FUNC_UP(SDA5, SDA5),
+		PAD_FUNC_UP(SCL5, SCL5),
+	},
+	[6] = {
+		PAD_FUNC_UP(SDA6, SDA6),
+		PAD_FUNC_UP(SCL6, SCL6),
+	},
+	[7] = {
+		PAD_FUNC_UP(SDA7, SDA7),
+		PAD_FUNC_UP(SCL7, SCL7),
+	},
+	[8] = {
+		PAD_FUNC_UP(SDA8, SDA8),
+		PAD_FUNC_UP(SCL8, SCL8),
+	},
+};
+
+void mtk_i2c_set_gpio_pinmux(uint8_t bus)
+{
+	assert(bus < I2C_BUS_NUMBER);
+
+	const struct pad_func *ptr = i2c_funcs[bus];
+	for (size_t i = 0; i < 2; i++) {
+		gpio_set_mode(ptr[i].gpio, ptr[i].func);
+		gpio_set_pull(ptr[i].gpio, GPIO_PULL_DISABLE, ptr[i].select);
+	}
+}
diff --git a/src/soc/mediatek/mt8189/include/soc/addressmap.h b/src/soc/mediatek/mt8189/include/soc/addressmap.h
index 3d559a9294..84006623a4 100644
--- a/src/soc/mediatek/mt8189/include/soc/addressmap.h
+++ b/src/soc/mediatek/mt8189/include/soc/addressmap.h
@@ -40,10 +40,28 @@ enum {
 	DEVAPC_PERI_PAR_AO_BASE		= IO_PHYS + 0x0103C000,
 	SSUSB_IPPC_BASE			= IO_PHYS + 0x01263E00,
 	UFSHCI_BASE			= IO_PHYS + 0x012B0000,
+	I2C0_DMA_BASE			= IO_PHYS + 0x01300200,
+	I2C1_DMA_BASE			= IO_PHYS + 0x01300300,
+	I2C2_DMA_BASE			= IO_PHYS + 0x01300400,
+	I2C3_DMA_BASE			= IO_PHYS + 0x01300500,
+	I2C4_DMA_BASE			= IO_PHYS + 0x01300600,
+	I2C5_DMA_BASE			= IO_PHYS + 0x01300700,
+	I2C6_DMA_BASE			= IO_PHYS + 0x01300800,
+	I2C7_DMA_BASE			= IO_PHYS + 0x01300900,
+	I2C8_DMA_BASE			= IO_PHYS + 0x01300A00,
 	SSUSB_SIF_BASE			= IO_PHYS + 0x01B00300,
+	I2C2_BASE			= IO_PHYS + 0x01B20000,
 	MIPITX0_BASE			= IO_PHYS + 0x01B40000,
 	IOCFG_LM_BASE			= IO_PHYS + 0x01B50000,
 	EDP_BASE			= IO_PHYS + 0x01B70000,
+	I2C0_BASE			= IO_PHYS + 0x01C20000,
+	I2C1_BASE			= IO_PHYS + 0x01C21000,
+	I2C3_BASE			= IO_PHYS + 0x01D70000,
+	I2C4_BASE			= IO_PHYS + 0x01D71000,
+	I2C5_BASE			= IO_PHYS + 0x01D72000,
+	I2C6_BASE			= IO_PHYS + 0x01D73000,
+	I2C7_BASE			= IO_PHYS + 0x01F30000,
+	I2C8_BASE			= IO_PHYS + 0x01F31000,
 	IOCFG_RB0_BASE			= IO_PHYS + 0x01C50000,
 	IOCFG_RB1_BASE			= IO_PHYS + 0x01C60000,
 	IOCFG_BM0_BASE			= IO_PHYS + 0x01D20000,
diff --git a/src/soc/mediatek/mt8189/include/soc/i2c.h b/src/soc/mediatek/mt8189/include/soc/i2c.h
new file mode 100644
index 0000000000..b39c0d734d
--- /dev/null
+++ b/src/soc/mediatek/mt8189/include/soc/i2c.h
@@ -0,0 +1,81 @@
+/* SPDX-License-Identifier: GPL-2.0-only OR MIT */
+
+/*
+ * This file is created based on MT8189 Functional Specification
+ * Chapter number: 9.10
+ */
+
+#ifndef __SOC_MEDIATEK_MT8189_INCLUDE_SOC_I2C_H__
+#define __SOC_MEDIATEK_MT8189_INCLUDE_SOC_I2C_H__
+
+#include <soc/i2c_common.h>
+
+/* I2C Register */
+struct mt_i2c_regs {
+	uint32_t data_port;
+	uint32_t reserved0[1];
+	uint32_t intr_mask;
+	uint32_t intr_stat;
+	uint32_t control;
+	uint32_t transfer_len;
+	uint32_t transac_len;
+	uint32_t delay_len;
+	uint32_t timing;
+	uint32_t start;
+	uint32_t ext_conf;
+	uint32_t ltiming;
+	uint32_t hs;
+	uint32_t io_config;
+	uint32_t fifo_addr_clr;
+	uint32_t reserved1[2];
+	uint32_t transfer_aux_len;
+	uint32_t clock_div;
+	uint32_t time_out;
+	uint32_t softreset;
+	uint32_t reserved2[16];
+	uint32_t slave_addr;
+	uint32_t reserved3[19];
+	uint32_t debug_stat;
+	uint32_t debug_ctrl;
+	uint32_t reserved4[2];
+	uint32_t fifo_stat;
+	uint32_t fifo_thresh;
+	uint32_t reserved5[897];
+	uint32_t sec_control;
+	uint32_t reserved6[31];
+	uint32_t channel_lock;
+	uint32_t channel_sec;
+	uint32_t hw_cg_en;
+	uint32_t reserved7[1];
+	uint32_t dma_req;
+	uint32_t dma_nreq;
+};
+
+check_member(mt_i2c_regs, intr_mask, 0x08);
+check_member(mt_i2c_regs, transfer_aux_len, 0x44);
+check_member(mt_i2c_regs, slave_addr, 0x94);
+check_member(mt_i2c_regs, debug_stat, 0xE4);
+check_member(mt_i2c_regs, fifo_stat, 0xF4);
+check_member(mt_i2c_regs, sec_control, 0xF00);
+check_member(mt_i2c_regs, channel_lock, 0xF80);
+check_member(mt_i2c_regs, dma_req, 0xF90);
+check_member(mt_i2c_regs, dma_nreq, 0xF94);
+
+/* I2C ID Number*/
+enum {
+	I2C0,
+	I2C1,
+	I2C2,
+	I2C3,
+	I2C4,
+	I2C5,
+	I2C6,
+	I2C7,
+	I2C8,
+};
+
+#define I2C_BUS_NUMBER	9
+#define MAX_CLOCK_DIV	32
+#define I2C_CLK_HZ	124800000
+
+#endif /* __SOC_MEDIATEK_MT8189_INCLUDE_SOC_I2C_H__ */

From 36f01c3481c7f86b95236d23ae2c06607db44448 Mon Sep 17 00:00:00 2001
From: Tongtong Pan <pantongtong@huaqin.corp-partner.google.com>
Date: Wed, 23 Apr 2025 12:09:37 +0800
Subject: [PATCH 0840/3886] mb/google/fatcat/var/felino: Add Write Protect GPIO
 to cros_gpios

This enables the utility crossystem to access WP GPIO,
`GPIO_PCH_WP` aka GPP_C08 is part of PTL GPIO community 0
therefore add `CROS_GPIO_DEVICE0_NAME` into the `cros_gpios` lists.

BUG=b:409472563
TEST= wpsw_cur in crossystem reads the correct gpio

Change-Id: Ia21b95d220d8df30fb3aa73b4c71047b135a52e6
Signed-off-by: Tongtong Pan <pantongtong@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87426
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
---
 src/mainboard/google/fatcat/variants/felino/gpio.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/src/mainboard/google/fatcat/variants/felino/gpio.c b/src/mainboard/google/fatcat/variants/felino/gpio.c
index ac36ab9b00..83c45bf54f 100644
--- a/src/mainboard/google/fatcat/variants/felino/gpio.c
+++ b/src/mainboard/google/fatcat/variants/felino/gpio.c
@@ -439,6 +439,7 @@ static const struct cros_gpio cros_gpios[] = {
 	CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE1_NAME),
 	CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE2_NAME),
 	CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE3_NAME),
+	CROS_GPIO_WP_AH(GPIO_PCH_WP, CROS_GPIO_DEVICE0_NAME),
 };
 
 DECLARE_CROS_GPIOS(cros_gpios);

From fb3f025ea6f5a8a2f6e3dbc6c693c5e3943dbf53 Mon Sep 17 00:00:00 2001
From: Naresh Solanki <naresh.solanki@9elements.com>
Date: Wed, 2 Apr 2025 19:24:17 +0530
Subject: [PATCH 0841/3886] soc/amd/common/cpu/noncar: Add SMBIOS helper

Some SoC like Glinda,
1. It has multiple L3 caches block, each identified by a unique cache
UID. Each core is associated with a specific L3 cache, which can be
determined based on the CPU core ID.
2. Each CPU core have slightly different CPU boost frequency.

For L3 cache info in DMI table type 7, the default implementation
(x86_get_cpu_cache_info) retrieves cache information only for the
current core and assumes that the same L3 cache is shared across all
cores.

To accurately determine the total L3 cache size:
1. Retrieves L3 cache information for each CPU core.
2. Identifies the unique cache ID associated with each core.
3. Aggregates cache sizes for all unique cache IDs to compute the
   total L3 cache size, ensuring correct summation even when L3 cache
   blocks have different sizes.

Additionally to get core max boost frequency,
1. Determine max boost frequency among all cores & update
   smbios_cpu_get_max_speed_mhz such that it return max of all cores.

TEST=Build for Glinda SoC & check output of `dmidecode -t 7` &
`dmidecode -t 4`. Verify DMI Type7 table to report L3 cache size as 24MB
(16 + 8) & Also verify DMI Type4 'Max Speed: 5408 MHz' which is maximum
boost clock frequency.

Change-Id: I2569a9c744f7f41e4df692626e77a178184b7e0e
Signed-off-by: Naresh Solanki <naresh.solanki@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87123
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
---
 src/soc/amd/common/block/cpu/noncar/cpu.c | 56 +++++++++++++++++++++++
 1 file changed, 56 insertions(+)

diff --git a/src/soc/amd/common/block/cpu/noncar/cpu.c b/src/soc/amd/common/block/cpu/noncar/cpu.c
index dfa6a69f42..c88e541ab6 100644
--- a/src/soc/amd/common/block/cpu/noncar/cpu.c
+++ b/src/soc/amd/common/block/cpu/noncar/cpu.c
@@ -115,6 +115,62 @@ unsigned int get_reserved_phys_addr_bits(void)
 			CPUID_EBX_MEM_ENCRYPT_ADDR_BITS_SHIFT;
 }
 
+unsigned int smbios_cpu_get_max_speed_mhz(void)
+{
+	uint32_t max_freq = 0;
+
+	for (int i = 0; i < get_cpu_count(); i++) {
+		struct core_info *core_info = &core_info_list[i];
+
+		if (max_freq < core_info->max_frequency)
+			max_freq = core_info->max_frequency;
+	}
+	return max_freq;
+}
+
+/*
+ * On some SoCs like AMD Glinda, multiple unique L3 cache blocks exist,
+ * each with a distinct UID and possibly different sizes. The default
+ * method assumes a single shared L3 cache across all cores, which is
+ * inaccurate. This function aggregates sizes of all uniquely identified
+ * L3 cache blocks to compute the correct total L3 size.
+ */
+bool soc_fill_cpu_cache_info(uint8_t level, struct cpu_cache_info *info)
+{
+	if (level != CACHE_L3)
+		return x86_get_cpu_cache_info(level, info);
+
+	if (!info)
+		return false;
+
+	uint32_t total_cache = 0;
+	bool seen_cache_ids[CONFIG_MAX_CPUS] = {false};
+
+	x86_get_cpu_cache_info(level, info);
+
+	/*
+	 * To calculate the total L3 cache size, iterate over core_info_list and add up the sizes
+	 * of the L3 cache blocks with unique cache ID.
+	 */
+	for (int i = 0; i < get_cpu_count(); i++) {
+		struct core_info *cache = &core_info_list[i];
+
+		printk(BIOS_SPEW, "CPU %d: Cache Level: %d, Cache Size: %zu bytes\n",
+		       i, cache->l3_cache_uid, cache->l3_cache_size);
+
+		if (!seen_cache_ids[cache->l3_cache_uid]) {
+			total_cache += cache->l3_cache_size;
+			seen_cache_ids[cache->l3_cache_uid] = true;
+		}
+	}
+
+	info->num_cores_shared = get_cpu_count();
+	info->size = total_cache;
+
+	printk(BIOS_SPEW, "Total cache at level: %d is:%zu\n", level, info->size);
+	return true;
+}
+
 static uint32_t get_max_boost_frequency(void)
 {
 	msr_t msr = rdmsr(MSR_CPPC_CAPABILITY_1);

From ee76692571e932a5c53d8ba61add298124ca32cd Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Mon, 21 Apr 2025 14:32:01 -0500
Subject: [PATCH 0842/3886] payload/external/edk2: Add Kconfig to support use
 of PCIe OpROMs

Add a Kconfig to support passing `LOAD_OPTION_ROMS=TRUE` as a build
parameter in order to enable edk2 support for dGPUs.

Change-Id: I05444425d1cb98b023681639389949bf3f3b8e9c
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87407
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
---
 payloads/external/Makefile.mk   | 1 +
 payloads/external/edk2/Kconfig  | 8 ++++++++
 payloads/external/edk2/Makefile | 4 ++++
 3 files changed, 13 insertions(+)

diff --git a/payloads/external/Makefile.mk b/payloads/external/Makefile.mk
index c279121493..5e8c91fbb5 100644
--- a/payloads/external/Makefile.mk
+++ b/payloads/external/Makefile.mk
@@ -182,6 +182,7 @@ $(obj)/UEFIPAYLOAD.fd: $(DOTCONFIG)
 		CONFIG_EDK2_FULL_SCREEN_SETUP=$(CONFIG_EDK2_FULL_SCREEN_SETUP) \
 		CONFIG_EDK2_HAVE_EFI_SHELL=$(CONFIG_EDK2_HAVE_EFI_SHELL) \
 		CONFIG_EDK2_PRIORITIZE_INTERNAL=$(CONFIG_EDK2_PRIORITIZE_INTERNAL) \
+		CONFIG_EDK2_LOAD_OPTION_ROMS=$(CONFIG_EDK2_LOAD_OPTION_ROMS) \
 		CONFIG_EDK2_PS2_SUPPORT=$(CONFIG_EDK2_PS2_SUPPORT) \
 		CONFIG_EDK2_SERIAL_SUPPORT=$(CONFIG_EDK2_SERIAL_SUPPORT) \
 		CONFIG_EDK2_SD_MMC_TIMEOUT=$(CONFIG_EDK2_SD_MMC_TIMEOUT) \
diff --git a/payloads/external/edk2/Kconfig b/payloads/external/edk2/Kconfig
index ea24cee4bf..08e48e53ff 100644
--- a/payloads/external/edk2/Kconfig
+++ b/payloads/external/edk2/Kconfig
@@ -240,6 +240,14 @@ config EDK2_PRIORITIZE_INTERNAL
 	help
 	  Prioritize internal boot devices over external devices
 
+config EDK2_LOAD_OPTION_ROMS
+	bool "Load and Execute OpROMs on PCIe devices"
+	depends on EDK2_REPO_MRCHROMEBOX
+	default n
+	help
+	  Load and execute OpROMs on PCIe devices.
+	  Select this option to support use of an external dGPU.
+
 config EDK2_PS2_SUPPORT
 	bool "Support PS/2 Keyboards"
 	default y
diff --git a/payloads/external/edk2/Makefile b/payloads/external/edk2/Makefile
index 6464e9f851..0908f4d26c 100644
--- a/payloads/external/edk2/Makefile
+++ b/payloads/external/edk2/Makefile
@@ -149,6 +149,10 @@ endif
 ifeq ($(CONFIG_EDK2_USE_LAPIC_TIMER),y)
 BUILD_STR += -D TIMER_SUPPORT=LAPIC
 endif
+# LOAD_OPTION_ROMS		= FALSE
+ifeq ($(CONFIG_EDK2_LOAD_OPTION_ROMS),y)
+BUILD_STR += -D LOAD_OPTION_ROMS=TRUE
+endif
 
 endif
 

From c82f5fe1336961626ee309746d246b36a2f21d69 Mon Sep 17 00:00:00 2001
From: Naresh Solanki <naresh.solanki@9elements.com>
Date: Wed, 9 Apr 2025 02:07:25 +0530
Subject: [PATCH 0843/3886] soc/amd/glinda: Select SOC_FILL_CPU_CACHE_INFO

Use soc_fill_cpu_cache_info implementation to for computing L3 cache
size accurately for Glinda SoC.

Change-Id: I2827508ec0ae5f16d609e1bc76c00eb376a7b71b
Signed-off-by: Naresh Solanki <naresh.solanki@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87222
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/soc/amd/glinda/Kconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/src/soc/amd/glinda/Kconfig b/src/soc/amd/glinda/Kconfig
index 9cc446c679..cfee669184 100644
--- a/src/soc/amd/glinda/Kconfig
+++ b/src/soc/amd/glinda/Kconfig
@@ -81,6 +81,7 @@ config SOC_AMD_GLINDA
 	select SOC_AMD_COMMON_FSP_PCI			# TODO: Check if this is still correct
 	select SOC_AMD_COMMON_FSP_PRELOAD_FSPS
 	select SOC_AMD_COMMON_ROMSTAGE_LEGACY_DMA_FIXUP
+	select SOC_FILL_CPU_CACHE_INFO
 	select SSE2
 	select UDK_2017_BINDING
 	select USE_DDR5

From 57d7957e3c16791c8d5848dfb8ab4fe4b54eacfb Mon Sep 17 00:00:00 2001
From: Subrata Banik <subratabanik@google.com>
Date: Fri, 21 Mar 2025 18:32:19 +0530
Subject: [PATCH 0844/3886] soc/qualcomm/x1p42100: Add initial SoC skeleton for
 X1P-42-100

This commit introduces a basic SoC framework for the Qualcomm
X1P-42-100, enabling initial build integration.

Key changes:

- Add placeholder SoC callbacks to facilitate control flow from /lib
  and Qualcomm common code.
- Populate the x1p42100 SoC directory with a copy of the SC7280
  codebase, with SoC-specific implementations removed.

This provides a foundational structure for X1P-42-100 development
within the `soc/qualcomm/x1p42100` directory, ensuring the upstream
builder can successfully compile the SoC code.

This allows for incremental development and integration.

Reference Document: X1P42100 Hardware Register Description

BUG=b:404985109
TEST=Successfully built google/bluey with the Qualcomm x1p42100 SoC.

Change-Id: I6358177b9c6dc26967d364a2056a62d8ca77f89b
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86972
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
---
 src/soc/qualcomm/x1p42100/Kconfig             |  48 ++++++
 src/soc/qualcomm/x1p42100/Makefile.mk         | 162 ++++++++++++++++++
 src/soc/qualcomm/x1p42100/bootblock.c         |  10 ++
 src/soc/qualcomm/x1p42100/cbmem.c             |   8 +
 src/soc/qualcomm/x1p42100/clock.c             |  18 ++
 src/soc/qualcomm/x1p42100/cpucp_load_reset.c  |  13 ++
 src/soc/qualcomm/x1p42100/decompressor.c      |   9 +
 .../x1p42100/include/soc/addressmap.h         |  53 ++++++
 src/soc/qualcomm/x1p42100/include/soc/clock.h |  20 +++
 src/soc/qualcomm/x1p42100/include/soc/cpucp.h |   9 +
 src/soc/qualcomm/x1p42100/include/soc/gpio.h  |  22 +++
 src/soc/qualcomm/x1p42100/include/soc/mmu.h   |   8 +
 .../x1p42100/include/soc/qcom_qup_se.h        |  38 ++++
 src/soc/qualcomm/x1p42100/include/soc/sdhci.h |   8 +
 src/soc/qualcomm/x1p42100/include/soc/shrm.h  |   8 +
 src/soc/qualcomm/x1p42100/include/soc/uart.h  |   8 +
 src/soc/qualcomm/x1p42100/memlayout.ld        |  59 +++++++
 src/soc/qualcomm/x1p42100/mmu.c               |  21 +++
 src/soc/qualcomm/x1p42100/pcie.c              |  30 ++++
 src/soc/qualcomm/x1p42100/qcom_qup_se.c       |   8 +
 src/soc/qualcomm/x1p42100/shrm_load_reset.c   |   8 +
 src/soc/qualcomm/x1p42100/soc.c               |  46 +++++
 22 files changed, 614 insertions(+)
 create mode 100644 src/soc/qualcomm/x1p42100/Kconfig
 create mode 100644 src/soc/qualcomm/x1p42100/Makefile.mk
 create mode 100644 src/soc/qualcomm/x1p42100/bootblock.c
 create mode 100644 src/soc/qualcomm/x1p42100/cbmem.c
 create mode 100644 src/soc/qualcomm/x1p42100/clock.c
 create mode 100644 src/soc/qualcomm/x1p42100/cpucp_load_reset.c
 create mode 100644 src/soc/qualcomm/x1p42100/decompressor.c
 create mode 100644 src/soc/qualcomm/x1p42100/include/soc/addressmap.h
 create mode 100644 src/soc/qualcomm/x1p42100/include/soc/clock.h
 create mode 100644 src/soc/qualcomm/x1p42100/include/soc/cpucp.h
 create mode 100644 src/soc/qualcomm/x1p42100/include/soc/gpio.h
 create mode 100644 src/soc/qualcomm/x1p42100/include/soc/mmu.h
 create mode 100644 src/soc/qualcomm/x1p42100/include/soc/qcom_qup_se.h
 create mode 100644 src/soc/qualcomm/x1p42100/include/soc/sdhci.h
 create mode 100644 src/soc/qualcomm/x1p42100/include/soc/shrm.h
 create mode 100644 src/soc/qualcomm/x1p42100/include/soc/uart.h
 create mode 100644 src/soc/qualcomm/x1p42100/memlayout.ld
 create mode 100644 src/soc/qualcomm/x1p42100/mmu.c
 create mode 100644 src/soc/qualcomm/x1p42100/pcie.c
 create mode 100644 src/soc/qualcomm/x1p42100/qcom_qup_se.c
 create mode 100644 src/soc/qualcomm/x1p42100/shrm_load_reset.c
 create mode 100644 src/soc/qualcomm/x1p42100/soc.c

diff --git a/src/soc/qualcomm/x1p42100/Kconfig b/src/soc/qualcomm/x1p42100/Kconfig
new file mode 100644
index 0000000000..728f81e7c1
--- /dev/null
+++ b/src/soc/qualcomm/x1p42100/Kconfig
@@ -0,0 +1,48 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
+config SOC_QUALCOMM_X1P42100
+	bool
+	default n
+	depends on USE_QC_BLOBS
+	select ARCH_BOOTBLOCK_ARMV8_64
+	select ARCH_RAMSTAGE_ARMV8_64
+	select ARCH_ROMSTAGE_ARMV8_64
+	select ARCH_VERSTAGE_ARMV8_64
+	select ARM64_USE_ARCH_TIMER
+	select CACHE_MRC_SETTINGS
+	select COMMONLIB_STORAGE
+	select COMMONLIB_STORAGE_SD
+	select GENERIC_GPIO_LIB
+	select GENERIC_UDELAY
+	select HAS_RECOVERY_MRC_CACHE
+	select HAVE_LINEAR_FRAMEBUFFER
+	select HAVE_MONOTONIC_TIMER
+	select HAVE_UART_SPECIAL
+	select MAINBOARD_FORCE_NATIVE_VGA_INIT
+	select MAINBOARD_HAS_NATIVE_VGA_INIT
+	select SDHCI_CONTROLLER
+	select SOC_QUALCOMM_COMMON
+
+if SOC_QUALCOMM_X1P42100
+
+config MEMLAYOUT_LD_FILE
+	string
+	default "src/soc/qualcomm/x1p42100/memlayout.ld"
+
+config VBOOT
+	select VBOOT_MUST_REQUEST_DISPLAY
+	select VBOOT_RETURN_FROM_VERSTAGE
+	select VBOOT_SEPARATE_VERSTAGE
+	select VBOOT_STARTS_IN_BOOTBLOCK
+
+config BOOT_DEVICE_SPI_FLASH_BUS
+	int
+	default 0 # TODO
+
+config UART_FOR_CONSOLE
+	int
+	default 0 # TODO
+	help
+	 Select the QUP instance to be used for UART console output.
+
+endif
diff --git a/src/soc/qualcomm/x1p42100/Makefile.mk b/src/soc/qualcomm/x1p42100/Makefile.mk
new file mode 100644
index 0000000000..0135f9bf57
--- /dev/null
+++ b/src/soc/qualcomm/x1p42100/Makefile.mk
@@ -0,0 +1,162 @@
+## SPDX-License-Identifier: GPL-2.0-only
+ifeq ($(CONFIG_SOC_QUALCOMM_X1P42100),y)
+
+decompressor-y += decompressor.c
+decompressor-y += mmu.c
+decompressor-y += ../common/timer.c
+all-y += ../common/timer.c
+all-y += ../common/gpio.c
+all-y += clock.c
+all-y += ../common/spi.c
+all-y += ../common/qspi.c
+all-y += ../common/qupv3_config.c
+all-y += qcom_qup_se.c
+all-y += ../common/qup_se_handler.c
+all-y += ../common/qupv3_spi.c
+all-y += ../common/qupv3_i2c.c
+all-y += ../common/qupv3_spi.c
+
+################################################################################
+bootblock-y += bootblock.c
+bootblock-y += mmu.c
+bootblock-$(CONFIG_DRIVERS_UART) += ../common/uart_bitbang.c
+
+################################################################################
+verstage-$(CONFIG_DRIVERS_UART) += ../common/qupv3_uart.c
+
+################################################################################
+romstage-y += cbmem.c
+romstage-y += shrm_load_reset.c
+romstage-y += cpucp_load_reset.c
+romstage-y += ../common/qclib.c
+romstage-y += ../common/mmu.c
+romstage-y += ../common/watchdog.c
+romstage-y += mmu.c
+romstage-$(CONFIG_DRIVERS_UART) += ../common/qupv3_uart.c
+
+################################################################################
+ramstage-y += soc.c
+ramstage-y += cbmem.c
+ramstage-$(CONFIG_DRIVERS_UART) += ../common/qupv3_uart.c
+ramstage-y += cpucp_load_reset.c
+
+################################################################################
+
+CPPFLAGS_common += -Isrc/soc/qualcomm/x1p42100/include
+CPPFLAGS_common += -Isrc/soc/qualcomm/common/include
+
+################################################################################
+ifeq ($(CONFIG_USE_QC_BLOBS),y)
+# TODO: Upload X1P42100 SoC blobs
+X1P42100_BLOB := $(top)/3rdparty/qc_blobs/sc7280
+
+ifeq ($(CONFIG_QC_SDI_ENABLE),y)
+BL31_MAKEARGS += QTI_SDI_BUILD=1
+BL31_MAKEARGS += QTISECLIB_PATH=$(X1P42100_BLOB)/qtiseclib/libqtisec_dbg.a
+else
+BL31_MAKEARGS += QTISECLIB_PATH=$(X1P42100_BLOB)/qtiseclib/libqtisec.a
+endif # CONFIG_QC_SDI_ENABLE
+
+################################################################################
+ifeq ($(CONFIG_QC_SDI_ENABLE),y)
+QCSDI_FILE := $(X1P42100_BLOB)/boot/QcSdi.elf
+QCSDI_CBFS := $(CONFIG_CBFS_PREFIX)/qcsdi
+$(QCSDI_CBFS)-file := $(QCSDI_FILE)
+$(QCSDI_CBFS)-type := stage
+$(QCSDI_CBFS)-compression := $(CBFS_COMPRESS_FLAG)
+cbfs-files-y += $(QCSDI_CBFS)
+endif
+
+################################################################################
+QC_SEC_FILE := $(X1P42100_BLOB)/qc_sec/qc_sec.mbn
+$(objcbfs)/bootblock.bin: $(objcbfs)/bootblock.raw.elf
+	@util/qualcomm/createxbl.py --mbn_version 6 -f $(objcbfs)/bootblock.raw.elf \
+		-x $(QC_SEC_FILE) -o $(objcbfs)/merged_bb_qcsec.mbn \
+		-a 64 -d 64 -c 64
+	@printf "\nqgpt.py 4K sector size\n"
+	@util/qualcomm/qgpt.py $(objcbfs)/merged_bb_qcsec.mbn \
+		$(objcbfs)/bootblock.bin
+
+################################################################################
+QCLIB_FILE := $(X1P42100_BLOB)/boot/QcLib.elf
+QCLIB_CBFS := $(CONFIG_CBFS_PREFIX)/qclib
+$(QCLIB_CBFS)-file := $(QCLIB_FILE)
+$(QCLIB_CBFS)-type := stage
+$(QCLIB_CBFS)-compression := $(CBFS_PRERAM_COMPRESS_FLAG)
+cbfs-files-y += $(QCLIB_CBFS)
+
+################################################################################
+PMIC_FILE := $(X1P42100_BLOB)/boot/Pmic.bin
+PMIC_CBFS := $(CONFIG_CBFS_PREFIX)/pmiccfg
+$(PMIC_CBFS)-file := $(PMIC_FILE)
+$(PMIC_CBFS)-type := raw
+$(PMIC_CBFS)-compression := $(CBFS_COMPRESS_FLAG)
+cbfs-files-y += $(PMIC_CBFS)
+
+################################################################################
+DCB_FILE := $(X1P42100_BLOB)/boot/dcb.bin
+DCB_CBFS := $(CONFIG_CBFS_PREFIX)/dcb
+$(DCB_CBFS)-file := $(DCB_FILE)
+$(DCB_CBFS)-type := raw
+$(DCB_CBFS)-compression := $(CBFS_COMPRESS_FLAG)
+cbfs-files-y += $(DCB_CBFS)
+
+################################################################################
+UART_FW_FILE := $(X1P42100_BLOB)/qup_fw/uart_fw.bin
+UART_FW_CBFS := $(CONFIG_CBFS_PREFIX)/uart_fw
+$(UART_FW_CBFS)-file := $(UART_FW_FILE)
+$(UART_FW_CBFS)-type := raw
+$(UART_FW_CBFS)-compression := $(CBFS_PRERAM_COMPRESS_FLAG)
+cbfs-files-y += $(UART_FW_CBFS)
+
+################################################################################
+SPI_FW_FILE := $(X1P42100_BLOB)/qup_fw/spi_fw.bin
+SPI_FW_CBFS := $(CONFIG_CBFS_PREFIX)/spi_fw
+$(SPI_FW_CBFS)-file := $(SPI_FW_FILE)
+$(SPI_FW_CBFS)-type := raw
+$(SPI_FW_CBFS)-compression := $(CBFS_PRERAM_COMPRESS_FLAG)
+cbfs-files-y += $(SPI_FW_CBFS)
+
+################################################################################
+I2C_FW_FILE := $(X1P42100_BLOB)/qup_fw/i2c_fw.bin
+I2C_FW_CBFS := $(CONFIG_CBFS_PREFIX)/i2c_fw
+$(I2C_FW_CBFS)-file := $(I2C_FW_FILE)
+$(I2C_FW_CBFS)-type := raw
+$(I2C_FW_CBFS)-compression := $(CBFS_PRERAM_COMPRESS_FLAG)
+cbfs-files-y += $(I2C_FW_CBFS)
+
+################################################################################
+AOP_FILE := $(X1P42100_BLOB)/aop/aop.mbn
+AOP_CBFS := $(CONFIG_CBFS_PREFIX)/aop
+$(AOP_CBFS)-file := $(AOP_FILE)
+$(AOP_CBFS)-type := payload
+$(AOP_CBFS)-compression := $(CBFS_COMPRESS_FLAG)
+cbfs-files-y += $(AOP_CBFS)
+
+################################################################################
+CPUCP_FILE := $(X1P42100_BLOB)/cpucp/cpucp.elf
+CPUCP_CBFS := $(CONFIG_CBFS_PREFIX)/cpucp
+$(CPUCP_CBFS)-file := $(CPUCP_FILE)
+$(CPUCP_CBFS)-type := payload
+$(CPUCP_CBFS)-compression := $(CBFS_COMPRESS_FLAG)
+cbfs-files-y += $(CPUCP_CBFS)
+
+################################################################################
+SHRM_FILE := $(X1P42100_BLOB)/shrm/shrm.elf
+SHRM_CBFS := $(CONFIG_CBFS_PREFIX)/shrm
+$(SHRM_CBFS)-file := $(SHRM_FILE)
+$(SHRM_CBFS)-type := payload
+$(SHRM_CBFS)-compression := $(CBFS_PRERAM_COMPRESS_FLAG)
+cbfs-files-y += $(SHRM_CBFS)
+
+################################################################################
+GSI_FW_FILE := $(X1P42100_BLOB)/qup_fw/gsi_fw.bin
+GSI_FW_CBFS := $(CONFIG_CBFS_PREFIX)/gsi_fw
+$(GSI_FW_CBFS)-file := $(GSI_FW_FILE)
+$(GSI_FW_CBFS)-type := raw
+$(GSI_FW_CBFS)-compression := $(CBFS_COMPRESS_FLAG)
+cbfs-files-y += $(GSI_FW_CBFS)
+
+endif
+
+endif
diff --git a/src/soc/qualcomm/x1p42100/bootblock.c b/src/soc/qualcomm/x1p42100/bootblock.c
new file mode 100644
index 0000000000..a4cedfa69f
--- /dev/null
+++ b/src/soc/qualcomm/x1p42100/bootblock.c
@@ -0,0 +1,10 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <bootblock_common.h>
+#include <soc/mmu.h>
+
+void bootblock_soc_init(void)
+{
+	if (!CONFIG(COMPRESS_BOOTBLOCK))
+		soc_mmu_init();
+}
diff --git a/src/soc/qualcomm/x1p42100/cbmem.c b/src/soc/qualcomm/x1p42100/cbmem.c
new file mode 100644
index 0000000000..5fff371d58
--- /dev/null
+++ b/src/soc/qualcomm/x1p42100/cbmem.c
@@ -0,0 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <cbmem.h>
+
+uintptr_t cbmem_top_chipset(void)
+{
+	return (uintptr_t)4 * GiB;
+}
diff --git a/src/soc/qualcomm/x1p42100/clock.c b/src/soc/qualcomm/x1p42100/clock.c
new file mode 100644
index 0000000000..9a4b16d810
--- /dev/null
+++ b/src/soc/qualcomm/x1p42100/clock.c
@@ -0,0 +1,18 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <soc/clock.h>
+
+void clock_configure_qspi(uint32_t hz)
+{
+	/* placeholder */
+}
+
+void clock_enable_qup(int qup)
+{
+	/* placeholder */
+}
+
+void clock_configure_dfsr(int qup)
+{
+	/* placeholder */
+}
diff --git a/src/soc/qualcomm/x1p42100/cpucp_load_reset.c b/src/soc/qualcomm/x1p42100/cpucp_load_reset.c
new file mode 100644
index 0000000000..f415bb8555
--- /dev/null
+++ b/src/soc/qualcomm/x1p42100/cpucp_load_reset.c
@@ -0,0 +1,13 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <soc/cpucp.h>
+
+void cpucp_prepare(void)
+{
+	/* Placeholder */
+}
+
+void cpucp_fw_load_reset(void)
+{
+	/* Placeholder */
+}
diff --git a/src/soc/qualcomm/x1p42100/decompressor.c b/src/soc/qualcomm/x1p42100/decompressor.c
new file mode 100644
index 0000000000..12a3bac50b
--- /dev/null
+++ b/src/soc/qualcomm/x1p42100/decompressor.c
@@ -0,0 +1,9 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <bootblock_common.h>
+#include <soc/mmu.h>
+
+void decompressor_soc_init(void)
+{
+	soc_mmu_init();
+}
diff --git a/src/soc/qualcomm/x1p42100/include/soc/addressmap.h b/src/soc/qualcomm/x1p42100/include/soc/addressmap.h
new file mode 100644
index 0000000000..5bb39e3bb5
--- /dev/null
+++ b/src/soc/qualcomm/x1p42100/include/soc/addressmap.h
@@ -0,0 +1,53 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef _SOC_QUALCOMM_X1P42100_ADDRESS_MAP_H_
+#define _SOC_QUALCOMM_X1P42100_ADDRESS_MAP_H_
+
+#include <stdint.h>
+
+/* TODO: update as per datasheet */
+#define AOSS_CC_BASE			0x0C2A0000
+#define QSPI_BASE			0x088DC000
+#define TLMM_TILE_BASE			0x0F100000
+
+/* X1P42100 QSPI GPIO PINS */
+#define QSPI_CS				GPIO(0)
+#define QSPI_DATA_0			GPIO(0)
+#define QSPI_DATA_1			GPIO(0)
+#define QSPI_CLK			GPIO(0)
+
+#define GPIO_FUNC_QSPI_DATA_0		0
+#define GPIO_FUNC_QSPI_DATA_1		0
+#define GPIO_FUNC_QSPI_CLK		0
+
+/*
+ * QUP SERIAL ENGINE BASE ADDRESSES
+ */
+/* QUPV3_0 */
+#define QUP_SERIAL0_BASE		0x00980000
+#define QUP_SERIAL1_BASE		0x00984000
+#define QUP_SERIAL2_BASE		0x00988000
+#define QUP_SERIAL3_BASE		0x0098C000
+#define QUP_SERIAL4_BASE		0x00990000
+#define QUP_SERIAL5_BASE		0x00994000
+#define QUP_SERIAL6_BASE		0x00998000
+#define QUP_SERIAL7_BASE		0x0099C000
+#define QUP_WRAP0_BASE			0x009C0000
+#define QUP_0_GSI_BASE			0x00904000
+
+/* QUPV3_1 */
+#define QUP_SERIAL8_BASE		0x00A80000
+#define QUP_SERIAL9_BASE		0x00A84000
+#define QUP_SERIAL10_BASE		0x00A88000
+#define QUP_SERIAL11_BASE		0x00A8C000
+#define QUP_SERIAL12_BASE		0x00A90000
+#define QUP_SERIAL13_BASE		0x00A94000
+#define QUP_SERIAL14_BASE		0x00A98000
+#define QUP_SERIAL15_BASE		0x00A9C000
+#define QUP_WRAP1_BASE			0x00AC0000
+#define QUP_1_GSI_BASE			0x00A04000
+
+/* QUPV3_2 - Dummy Entry */
+#define QUP_WRAP2_BASE			0x00000000
+
+#endif /*  __SOC_QUALCOMM_X1P42100_ADDRESS_MAP_H__ */
diff --git a/src/soc/qualcomm/x1p42100/include/soc/clock.h b/src/soc/qualcomm/x1p42100/include/soc/clock.h
new file mode 100644
index 0000000000..97d418fdbb
--- /dev/null
+++ b/src/soc/qualcomm/x1p42100/include/soc/clock.h
@@ -0,0 +1,20 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <soc/addressmap.h>
+#include <types.h>
+#include <soc/clock_common.h>
+
+#ifndef __SOC_QUALCOMM_X1P42100_CLOCK_H__
+#define __SOC_QUALCOMM_X1P42100_CLOCK_H__
+
+#define SRC_XO_HZ		(38400 * KHz)
+
+/* TODO: update as per datasheet */
+void clock_configure_qspi(uint32_t hz);
+void clock_enable_qup(int qup);
+void clock_configure_dfsr(int qup);
+
+/* Subsystem Reset */
+static struct aoss *const aoss = (void *)AOSS_CC_BASE;
+
+#endif	// __SOC_QUALCOMM_X1P42100_CLOCK_H__
diff --git a/src/soc/qualcomm/x1p42100/include/soc/cpucp.h b/src/soc/qualcomm/x1p42100/include/soc/cpucp.h
new file mode 100644
index 0000000000..4aa7384da7
--- /dev/null
+++ b/src/soc/qualcomm/x1p42100/include/soc/cpucp.h
@@ -0,0 +1,9 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef _SOC_QUALCOMM_X1P42100_CPUCP_H__
+#define _SOC_QUALCOMM_X1P42100_CPUCP_H__
+
+void cpucp_fw_load_reset(void);
+void cpucp_prepare(void);
+
+#endif  // _SOC_QUALCOMM_X1P42100_CPUCP_H__
diff --git a/src/soc/qualcomm/x1p42100/include/soc/gpio.h b/src/soc/qualcomm/x1p42100/include/soc/gpio.h
new file mode 100644
index 0000000000..1c30f7881f
--- /dev/null
+++ b/src/soc/qualcomm/x1p42100/include/soc/gpio.h
@@ -0,0 +1,22 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef _SOC_QUALCOMM_X1P42100_GPIO_H_
+#define _SOC_QUALCOMM_X1P42100_GPIO_H_
+
+#include <types.h>
+#include <soc/addressmap.h>
+#include <soc/gpio_common.h>
+
+#define PIN(index, func1, func2, func3, func4) \
+GPIO##index##_ADDR = TLMM_TILE_BASE + (index * TLMM_GPIO_OFF_DELTA), \
+GPIO##index##_FUNC_##func1 = 1, \
+GPIO##index##_FUNC_##func2 = 2, \
+GPIO##index##_FUNC_##func3 = 3, \
+GPIO##index##_FUNC_##func4 = 4
+
+/* TODO: update as per datasheet */
+enum {
+	PIN(0, QUP0_L0, RES_2, RES_3, RES_4),
+};
+
+#endif /* _SOC_QUALCOMM_X1P42100_GPIO_H_ */
diff --git a/src/soc/qualcomm/x1p42100/include/soc/mmu.h b/src/soc/qualcomm/x1p42100/include/soc/mmu.h
new file mode 100644
index 0000000000..a0a25ba05b
--- /dev/null
+++ b/src/soc/qualcomm/x1p42100/include/soc/mmu.h
@@ -0,0 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef _SOC_QUALCOMM_X1P42100_MMU_H_
+#define _SOC_QUALCOMM_X1P42100_MMU_H_
+
+void soc_mmu_init(void);
+
+#endif /* _SOC_QUALCOMM_X1P42100_MMU_H_ */
diff --git a/src/soc/qualcomm/x1p42100/include/soc/qcom_qup_se.h b/src/soc/qualcomm/x1p42100/include/soc/qcom_qup_se.h
new file mode 100644
index 0000000000..f12616a51f
--- /dev/null
+++ b/src/soc/qualcomm/x1p42100/include/soc/qcom_qup_se.h
@@ -0,0 +1,38 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef __SOC_QCOM_QUP_SE_H__
+#define __SOC_QCOM_QUP_SE_H__
+
+#include <console/console.h>
+#include <device/mmio.h>
+#include <gpio.h>
+#include <soc/addressmap.h>
+#include <timer.h>
+#include <types.h>
+
+/* TODO: update qup_se entries as per datasheet */
+enum qup_se {
+	QUPV3_0_SE0,
+	QUPV3_0_SE1,
+	QUPV3_0_SE2,
+	QUPV3_0_SE3,
+	QUPV3_0_SE4,
+	QUPV3_0_SE5,
+	QUPV3_0_SE6,
+	QUPV3_0_SE7,
+	QUPV3_0_SE8,
+	QUPV3_SE_MAX,
+};
+
+struct qup {
+	struct qup_regs *regs;
+	gpio_t pin[4];
+	u8 func[4];
+};
+
+extern struct qup qup[QUPV3_SE_MAX];
+
+/* TODO: update MAX_OFFSET_CFG_REG as per datasheet */
+#define MAX_OFFSET_CFG_REG		0x000001c4
+
+#endif /* __SOC_QCOM_QUP_SE_H__ */
diff --git a/src/soc/qualcomm/x1p42100/include/soc/sdhci.h b/src/soc/qualcomm/x1p42100/include/soc/sdhci.h
new file mode 100644
index 0000000000..3e5f10793a
--- /dev/null
+++ b/src/soc/qualcomm/x1p42100/include/soc/sdhci.h
@@ -0,0 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef _SOC_QUALCOMM_X1P42100_SDHCI_H__
+#define _SOC_QUALCOMM_X1P42100_SDHCI_H__
+
+int qc_emmc_early_init(void);
+
+#endif  // _SOC_QUALCOMM_X1P42100_SDHCI_H__
diff --git a/src/soc/qualcomm/x1p42100/include/soc/shrm.h b/src/soc/qualcomm/x1p42100/include/soc/shrm.h
new file mode 100644
index 0000000000..667e257e6c
--- /dev/null
+++ b/src/soc/qualcomm/x1p42100/include/soc/shrm.h
@@ -0,0 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef _SOC_QUALCOMM_X1P42100_SHRM_H__
+#define _SOC_QUALCOMM_X1P42100_SHRM_H__
+
+void shrm_fw_load_reset(void);
+
+#endif  // _SOC_QUALCOMM_X1P42100_SHRM_H__
diff --git a/src/soc/qualcomm/x1p42100/include/soc/uart.h b/src/soc/qualcomm/x1p42100/include/soc/uart.h
new file mode 100644
index 0000000000..179deb3021
--- /dev/null
+++ b/src/soc/qualcomm/x1p42100/include/soc/uart.h
@@ -0,0 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef _SOC_QUALCOMM_X1P42100_UART_TX_H_
+#define _SOC_QUALCOMM_X1P42100_UART_TX_H_
+
+#define UART_TX_PIN GPIO(0)
+
+#endif /* _SOC_QUALCOMM_X1P42100_UART_TX_H_ */
diff --git a/src/soc/qualcomm/x1p42100/memlayout.ld b/src/soc/qualcomm/x1p42100/memlayout.ld
new file mode 100644
index 0000000000..c2e2f90766
--- /dev/null
+++ b/src/soc/qualcomm/x1p42100/memlayout.ld
@@ -0,0 +1,59 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <memlayout.h>
+#include <arch/header.ld>
+
+/* Copied from Qualcomm previous generation SoC SC7280 and need cleanup */
+
+/* SYSTEM_IMEM : 0x14680000 - 0x146AB000 */
+#define SSRAM_START(addr) REGION_START(ssram, addr)
+#define SSRAM_END(addr) REGION_END(ssram, addr)
+
+/* BOOT_IMEM   : 0x14800000 - 0x14980000 */
+#define BSRAM_START(addr) REGION_START(bsram, addr)
+#define BSRAM_END(addr) REGION_END(bsram, addr)
+
+/* AOP : 0x0B000000 - 0x0B100000 */
+#define AOPSRAM_START(addr) REGION_START(aopsram, addr)
+#define AOPSRAM_END(addr) REGION_END(aopsram, addr)
+
+SECTIONS
+{
+	REGION(shrm, 0x09060000, 64K , 4K)
+
+	AOPSRAM_START(0x0B000000)
+	REGION(aop_code_ram, 0x0B000000, 0x80000, 4096)
+	REGION(aop_data_ram, 0x0B0E0000, 0x20000, 4096)
+	AOPSRAM_END(0x0B100000)
+
+	SSRAM_START(0x14680000)
+	OVERLAP_DECOMPRESSOR_VERSTAGE_ROMSTAGE(0x14680000, 132K)
+	REGION(qcsdi, 0x146A1000, 40K, 4K)
+	SSRAM_END(0x146AB000)
+
+	BSRAM_START(0x14800000)
+	REGION(pbl_timestamps, 0x14800000, 84K, 4K)
+	WATCHDOG_TOMBSTONE(0x14818FFC, 4)
+	BOOTBLOCK(0x14819000, 60K)
+	PRERAM_CBFS_CACHE(0x14828000, 103K)
+	TIMESTAMP(0x14841C00, 1K)
+	TTB(0x14842000, 56K)
+	STACK(0x14850000, 16K)
+	VBOOT2_WORK(0x14854000, 12K)
+	DMA_COHERENT(0x14857000, 8K)
+	REGION(qclib_serial_log, 0x1485B000, 4K, 4K)
+	CBFS_MCACHE(0x1485C000,16K)
+	REGION(ddr_information, 0x14860000, 1K, 1K)
+	FMAP_CACHE(0x14860400, 2K)
+	REGION(dcb, 0x14862000, 32K, 4K)
+	REGION(pmic, 0x1486A000, 96K, 4K)
+	REGION(ddr_training, 0x14882000, 32K, 4K)
+	REGION(qclib, 0x1488A000, 800K, 4K)
+	PRERAM_CBMEM_CONSOLE(0x14954000, 32K)
+	BSRAM_END(0x1495C000)
+
+	DRAM_START(0x80000000)
+	POSTRAM_CBFS_CACHE(0x9F800000, 16M)
+	RAMSTAGE(0xA0800000, 16M)
+	BL31(0xC0000000, 1M)
+}
diff --git a/src/soc/qualcomm/x1p42100/mmu.c b/src/soc/qualcomm/x1p42100/mmu.c
new file mode 100644
index 0000000000..9279d8e1a0
--- /dev/null
+++ b/src/soc/qualcomm/x1p42100/mmu.c
@@ -0,0 +1,21 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <symbols.h>
+#include <arch/mmu.h>
+#include <arch/cache.h>
+#include <soc/mmu.h>
+#include <soc/mmu_common.h>
+#include <soc/symbols_common.h>
+
+void soc_mmu_init(void)
+{
+	mmu_init();
+
+	mmu_config_range((void *)(4 * KiB), ((4UL * GiB) - (4 * KiB)), DEV_MEM);
+	mmu_config_range((void *)_ssram, REGION_SIZE(ssram), CACHED_RAM);
+	mmu_config_range((void *)_bsram, REGION_SIZE(bsram), CACHED_RAM);
+	mmu_config_range((void *)_dma_coherent, REGION_SIZE(dma_coherent),
+			 UNCACHED_RAM);
+
+	mmu_enable();
+}
diff --git a/src/soc/qualcomm/x1p42100/pcie.c b/src/soc/qualcomm/x1p42100/pcie.c
new file mode 100644
index 0000000000..3e38450c4b
--- /dev/null
+++ b/src/soc/qualcomm/x1p42100/pcie.c
@@ -0,0 +1,30 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <soc/pcie.h>
+
+/* Enable PIPE clock */
+int qcom_dw_pcie_enable_pipe_clock(void)
+{
+	/* placeholder */
+
+	return 0;
+}
+
+/* Enable controller specific clocks */
+int32_t qcom_dw_pcie_enable_clock(void)
+{
+	/* placeholder */
+
+	return 0;
+}
+
+/* Turn on NVMe */
+void gcom_pcie_power_on_ep(void)
+{
+	/* placeholder */
+}
+
+void gcom_pcie_get_config(struct qcom_pcie_cntlr_t *host_cfg)
+{
+	/* placeholder */
+}
diff --git a/src/soc/qualcomm/x1p42100/qcom_qup_se.c b/src/soc/qualcomm/x1p42100/qcom_qup_se.c
new file mode 100644
index 0000000000..8b2284d4b1
--- /dev/null
+++ b/src/soc/qualcomm/x1p42100/qcom_qup_se.c
@@ -0,0 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <soc/qcom_qup_se.h>
+
+/* TODO: update qup entries as per datasheet */
+struct qup qup[QUPV3_SE_MAX] = {
+
+};
diff --git a/src/soc/qualcomm/x1p42100/shrm_load_reset.c b/src/soc/qualcomm/x1p42100/shrm_load_reset.c
new file mode 100644
index 0000000000..6bd1b1d530
--- /dev/null
+++ b/src/soc/qualcomm/x1p42100/shrm_load_reset.c
@@ -0,0 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <soc/shrm.h>
+
+void shrm_fw_load_reset(void)
+{
+	/* Placeholder */
+}
diff --git a/src/soc/qualcomm/x1p42100/soc.c b/src/soc/qualcomm/x1p42100/soc.c
new file mode 100644
index 0000000000..c23aa89c69
--- /dev/null
+++ b/src/soc/qualcomm/x1p42100/soc.c
@@ -0,0 +1,46 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <device/device.h>
+#include <soc/mmu.h>
+#include <soc/mmu_common.h>
+#include <soc/symbols_common.h>
+#include <soc/cpucp.h>
+#include <soc/pcie.h>
+
+static struct device_operations pci_domain_ops = {
+	.read_resources = noop_read_resources,
+	.set_resources = noop_set_resources,
+};
+
+static void soc_read_resources(struct device *dev)
+{
+	/* placeholder */
+}
+
+static void soc_init(struct device *dev)
+{
+	/* placeholder */
+}
+
+static struct device_operations soc_ops = {
+	.read_resources = soc_read_resources,
+	.set_resources = noop_set_resources,
+	.init = soc_init,
+};
+
+static void enable_soc_dev(struct device *dev)
+{
+	/* Set the operations if it is a special bus type */
+	if (dev->path.type == DEVICE_PATH_DOMAIN) {
+		if (mainboard_needs_pcie_init())
+			dev->ops = &pci_domain_ops;
+		else
+			printk(BIOS_DEBUG, "Skip setting PCIe ops\n");
+	} else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER)
+		dev->ops = &soc_ops;
+}
+
+struct chip_operations soc_qualcomm_x1p42100_ops = {
+	.name = "SOC Qualcomm X1P-42-100",
+	.enable_dev = enable_soc_dev,
+};

From 7da36ad79adb2f9f85b2780402c6a137f9dc71a6 Mon Sep 17 00:00:00 2001
From: Subrata Banik <subratabanik@google.com>
Date: Fri, 21 Mar 2025 18:39:04 +0530
Subject: [PATCH 0845/3886] mb/google/bluey: Add initial support for Bluey

This commit introduces basic support for the google/bluey mainboard,
based on the Qualcomm X1P-42-100 SoC.

Changes:

- Add placeholder mainboard callbacks to enable control flow from /lib
  and Qualcomm SoC code.
- Populate the bluey mainboard directory with a copy of the herobrine
  codebase, removing SoC/mainboard-specific implementations.

This provides a minimal working build for google/bluey, allowing
upstream builders to compile the mainboard. This facilitates easier
verification of subsequent changes.

BUG=b:404985109
TEST=Successfully built google/bluey with Qualcomm X1P-42-100 SoC.

Change-Id: Id0da1846b8aef6f4ef4345be9cd803aa60406cdf
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86973
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/google/bluey/Kconfig        | 61 +++++++++++++++++++++++
 src/mainboard/google/bluey/Kconfig.name   |  6 +++
 src/mainboard/google/bluey/Makefile.mk    | 11 ++++
 src/mainboard/google/bluey/board.h        | 14 ++++++
 src/mainboard/google/bluey/board_info.txt |  6 +++
 src/mainboard/google/bluey/boardid.c      | 17 +++++++
 src/mainboard/google/bluey/bootblock.c    |  8 +++
 src/mainboard/google/bluey/chromeos.c     | 31 ++++++++++++
 src/mainboard/google/bluey/chromeos.fmd   | 42 ++++++++++++++++
 src/mainboard/google/bluey/devicetree.cb  |  7 +++
 src/mainboard/google/bluey/mainboard.c    | 24 +++++++++
 src/mainboard/google/bluey/reset.c        | 11 ++++
 src/mainboard/google/bluey/romstage.c     |  8 +++
 13 files changed, 246 insertions(+)
 create mode 100644 src/mainboard/google/bluey/Kconfig
 create mode 100644 src/mainboard/google/bluey/Kconfig.name
 create mode 100644 src/mainboard/google/bluey/Makefile.mk
 create mode 100644 src/mainboard/google/bluey/board.h
 create mode 100644 src/mainboard/google/bluey/board_info.txt
 create mode 100644 src/mainboard/google/bluey/boardid.c
 create mode 100644 src/mainboard/google/bluey/bootblock.c
 create mode 100644 src/mainboard/google/bluey/chromeos.c
 create mode 100644 src/mainboard/google/bluey/chromeos.fmd
 create mode 100644 src/mainboard/google/bluey/devicetree.cb
 create mode 100644 src/mainboard/google/bluey/mainboard.c
 create mode 100644 src/mainboard/google/bluey/reset.c
 create mode 100644 src/mainboard/google/bluey/romstage.c

diff --git a/src/mainboard/google/bluey/Kconfig b/src/mainboard/google/bluey/Kconfig
new file mode 100644
index 0000000000..a22cae6bab
--- /dev/null
+++ b/src/mainboard/google/bluey/Kconfig
@@ -0,0 +1,61 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
+config BOARD_GOOGLE_BLUEY_COMMON
+	def_bool n
+	select BOARD_ROMSIZE_KB_8192
+	select COMMON_CBFS_SPI_WRAPPER
+	select EC_GOOGLE_CHROMEEC
+	select EC_GOOGLE_CHROMEEC_RTC
+	select EC_GOOGLE_CHROMEEC_SPI
+	select I2C_TPM
+	select MAINBOARD_HAS_CHROMEOS
+	select MAINBOARD_HAS_TPM2
+	select RTC
+	select SOC_QUALCOMM_X1P42100
+	select SPI_FLASH
+	select SPI_FLASH_EXIT_4_BYTE_ADDR_MODE
+	select SPI_FLASH_GIGADEVICE
+	select SPI_FLASH_MACRONIX
+	select SPI_FLASH_WINBOND
+	select TPM_GOOGLE_TI50
+
+config BOARD_GOOGLE_BASEBOARD_BLUEY
+	def_bool n
+	select BOARD_GOOGLE_BLUEY_COMMON
+
+config BOARD_GOOGLE_BLUEY
+	select BOARD_GOOGLE_BASEBOARD_BLUEY
+
+if BOARD_GOOGLE_BLUEY_COMMON
+
+config MAINBOARD_DIR
+	default "google/bluey"
+
+config MAINBOARD_VENDOR
+	string
+	default "Google"
+
+config VBOOT
+	select EC_GOOGLE_CHROMEEC_SWITCHES
+	select VBOOT_VBNV_FLASH
+
+##########################################################
+#### Update below when adding a new derivative board. ####
+##########################################################
+
+config MAINBOARD_PART_NUMBER
+	default "Bluey" if BOARD_GOOGLE_BLUEY
+
+config DRIVER_TPM_I2C_BUS
+	depends on I2C_TPM
+	hex
+	default 0x00 # TODO
+
+config DRIVER_TPM_I2C_ADDR
+	default 0x50
+
+config EC_GOOGLE_CHROMEEC_SPI_BUS
+	hex
+	default 0x0 # TODO
+
+endif # BOARD_GOOGLE_BLUEY_COMMON
diff --git a/src/mainboard/google/bluey/Kconfig.name b/src/mainboard/google/bluey/Kconfig.name
new file mode 100644
index 0000000000..19cb4b1e17
--- /dev/null
+++ b/src/mainboard/google/bluey/Kconfig.name
@@ -0,0 +1,6 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
+comment "Bluey"
+
+config BOARD_GOOGLE_BLUEY
+	bool "->  Bluey"
diff --git a/src/mainboard/google/bluey/Makefile.mk b/src/mainboard/google/bluey/Makefile.mk
new file mode 100644
index 0000000000..553634c29c
--- /dev/null
+++ b/src/mainboard/google/bluey/Makefile.mk
@@ -0,0 +1,11 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
+all-y += boardid.c
+all-y += chromeos.c
+all-y += reset.c
+
+bootblock-y += bootblock.c
+
+romstage-y += romstage.c
+
+ramstage-y += mainboard.c
diff --git a/src/mainboard/google/bluey/board.h b/src/mainboard/google/bluey/board.h
new file mode 100644
index 0000000000..e6de22ef48
--- /dev/null
+++ b/src/mainboard/google/bluey/board.h
@@ -0,0 +1,14 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef MAINBOARD_GOOGLE_BLUEY_BOARD_H
+#define MAINBOARD_GOOGLE_BLUEY_BOARD_H
+
+#include <assert.h>
+#include <gpio.h>
+
+#define GPIO_AP_EC_INT		GPIO(0)
+#define GPIO_GSC_AP_INT		GPIO(0)
+
+void setup_chromeos_gpios(void);
+
+#endif /* MAINBOARD_GOOGLE_BLUEY_BOARD_H */
diff --git a/src/mainboard/google/bluey/board_info.txt b/src/mainboard/google/bluey/board_info.txt
new file mode 100644
index 0000000000..be67b9c6af
--- /dev/null
+++ b/src/mainboard/google/bluey/board_info.txt
@@ -0,0 +1,6 @@
+Vendor name: Google
+Board name: Bluey Qualcomm X1P-42-100 reference board
+Category: eval
+ROM protocol: SPI
+ROM socketed: n
+Flashrom support: y
diff --git a/src/mainboard/google/bluey/boardid.c b/src/mainboard/google/bluey/boardid.c
new file mode 100644
index 0000000000..b529ff1ec1
--- /dev/null
+++ b/src/mainboard/google/bluey/boardid.c
@@ -0,0 +1,17 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <boardid.h>
+
+uint32_t board_id(void)
+{
+	static uint32_t id = UNDEFINED_STRAPPING_ID;
+	/* Placeholder */
+	return id;
+}
+
+uint32_t sku_id(void)
+{
+	static uint32_t id = UNDEFINED_STRAPPING_ID;
+	/* Placeholder */
+	return id;
+}
diff --git a/src/mainboard/google/bluey/bootblock.c b/src/mainboard/google/bluey/bootblock.c
new file mode 100644
index 0000000000..b8edccd598
--- /dev/null
+++ b/src/mainboard/google/bluey/bootblock.c
@@ -0,0 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <bootblock_common.h>
+
+void bootblock_mainboard_init(void)
+{
+	/* Placeholder */
+}
diff --git a/src/mainboard/google/bluey/chromeos.c b/src/mainboard/google/bluey/chromeos.c
new file mode 100644
index 0000000000..aad0b0fea3
--- /dev/null
+++ b/src/mainboard/google/bluey/chromeos.c
@@ -0,0 +1,31 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <boot/coreboot_tables.h>
+#include <bootmode.h>
+#include "board.h"
+#include <drivers/tpm/cr50.h>
+
+void setup_chromeos_gpios(void)
+{
+	gpio_input_pullup(GPIO_AP_EC_INT);
+
+	gpio_input_irq(GPIO_GSC_AP_INT, IRQ_TYPE_RISING_EDGE, GPIO_PULL_UP);
+}
+
+void fill_lb_gpios(struct lb_gpios *gpios)
+{
+	/* TODO: Add required GPIO after referring to the schematics */
+	const struct lb_gpio chromeos_gpios[] = {
+		{GPIO_AP_EC_INT.addr, ACTIVE_LOW, gpio_get(GPIO_AP_EC_INT),
+			"EC interrupt"},
+		{GPIO_GSC_AP_INT.addr, ACTIVE_HIGH, gpio_get(GPIO_GSC_AP_INT),
+			"TPM interrupt"},
+	};
+
+	lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios));
+}
+
+int cr50_plat_irq_status(void)
+{
+	return gpio_irq_status(GPIO_GSC_AP_INT);
+}
diff --git a/src/mainboard/google/bluey/chromeos.fmd b/src/mainboard/google/bluey/chromeos.fmd
new file mode 100644
index 0000000000..0ad818b6db
--- /dev/null
+++ b/src/mainboard/google/bluey/chromeos.fmd
@@ -0,0 +1,42 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
+FLASH@0x0 CONFIG_ROM_SIZE {
+	WP_RO 4M {
+		RO_SECTION 0x3c4000 {
+			BOOTBLOCK 96K
+			COREBOOT(CBFS)
+			FMAP@0x3c0000 0x1000
+			GBB 0x2f00
+			RO_FRID 0x100
+		}
+		RO_GSCVD 8K
+		RO_VPD(PRESERVE)
+	}
+
+	RW_MISC 128K {
+		UNIFIED_MRC_CACHE(PRESERVE) 64K {
+			RECOVERY_MRC_CACHE 32K
+			RW_MRC_CACHE 32K
+		}
+		RW_ELOG(PRESERVE) 4K
+		RW_SHARED 4K {
+			SHARED_DATA
+		}
+		RW_VPD(PRESERVE) 32K
+		RW_NVRAM(PRESERVE) 16K
+	}
+
+	RW_SECTION_A 1536K {
+		VBLOCK_A 8K
+		FW_MAIN_A(CBFS)
+		RW_FWID_A 256
+	}
+
+	RW_SECTION_B 1536K {
+		VBLOCK_B 8K
+		FW_MAIN_B(CBFS)
+		RW_FWID_B 256
+	}
+
+	RW_LEGACY(CBFS)
+}
diff --git a/src/mainboard/google/bluey/devicetree.cb b/src/mainboard/google/bluey/devicetree.cb
new file mode 100644
index 0000000000..7aed490a72
--- /dev/null
+++ b/src/mainboard/google/bluey/devicetree.cb
@@ -0,0 +1,7 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
+chip soc/qualcomm/x1p42100
+	device cpu_cluster 0 on end
+	device domain 0 on
+	end
+end
diff --git a/src/mainboard/google/bluey/mainboard.c b/src/mainboard/google/bluey/mainboard.c
new file mode 100644
index 0000000000..c633e8dfb1
--- /dev/null
+++ b/src/mainboard/google/bluey/mainboard.c
@@ -0,0 +1,24 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <device/device.h>
+#include <soc/pcie.h>
+
+bool mainboard_needs_pcie_init(void)
+{
+	/* Placeholder */
+	return false;
+}
+
+static void mainboard_init(struct device *dev)
+{
+	/* Placeholder */
+}
+
+static void mainboard_enable(struct device *dev)
+{
+	dev->ops->init = &mainboard_init;
+}
+
+struct chip_operations mainboard_ops = {
+	.enable_dev = mainboard_enable,
+};
diff --git a/src/mainboard/google/bluey/reset.c b/src/mainboard/google/bluey/reset.c
new file mode 100644
index 0000000000..d64c650b99
--- /dev/null
+++ b/src/mainboard/google/bluey/reset.c
@@ -0,0 +1,11 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <ec/google/chromeec/ec.h>
+#include <reset.h>
+
+/* Can't do a "real" reset before the PMIC is initialized in QcLib (romstage),
+   but this works well enough for our purposes. */
+void do_board_reset(void)
+{
+	google_chromeec_reboot(EC_REBOOT_COLD, 0);
+}
diff --git a/src/mainboard/google/bluey/romstage.c b/src/mainboard/google/bluey/romstage.c
new file mode 100644
index 0000000000..8d15157e70
--- /dev/null
+++ b/src/mainboard/google/bluey/romstage.c
@@ -0,0 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <arch/stages.h>
+
+void platform_romstage_main(void)
+{
+	/* Placeholder */
+}

From fe881c990c97354297473314c2d38941b96a1e89 Mon Sep 17 00:00:00 2001
From: Kun Liu <liukun11@huaqin.corp-partner.google.com>
Date: Wed, 9 Apr 2025 10:18:27 +0800
Subject: [PATCH 0846/3886] mb/google/brya: Create pujjocento variant

Create the pujjocento variant of the nissa reference board by
copying the template files to a new directory named for the variant.

(Auto-Generated by create_coreboot_variant.sh version 4.5.0)

BUG=b:409254508
BRANCH=None
TEST=util/abuild/abuild -p none -t google/brya -x -a
make sure the build includes GOOGLE_PUJJOCENTO

Change-Id: I33b0642624ba67f53126e92976096ba53750ae89
Signed-off-by: Kun Liu <liukun11@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87419
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jayvik Desai <jayvik@google.com>
---
 src/mainboard/google/brya/Kconfig             |  10 +
 src/mainboard/google/brya/Kconfig.name        |   3 +
 .../brya/variants/pujjocento/Makefile.mk      |   8 +
 .../google/brya/variants/pujjocento/gpio.c    | 491 +++++++++++++++++
 .../brya/variants/pujjocento/hda_verb.c       | 128 +++++
 .../variants/pujjocento/include/variant/ec.h  |   8 +
 .../pujjocento/include/variant/gpio.h         |  11 +
 .../google/brya/variants/pujjocento/memory.c  | 111 ++++
 .../variants/pujjocento/memory/Makefile.mk    |  10 +
 .../pujjocento/memory/dram_id.generated.txt   |  10 +
 .../pujjocento/memory/mem_parts_used.txt      |  15 +
 .../brya/variants/pujjocento/overridetree.cb  | 513 ++++++++++++++++++
 .../google/brya/variants/pujjocento/variant.c |  38 ++
 13 files changed, 1356 insertions(+)
 create mode 100644 src/mainboard/google/brya/variants/pujjocento/Makefile.mk
 create mode 100644 src/mainboard/google/brya/variants/pujjocento/gpio.c
 create mode 100644 src/mainboard/google/brya/variants/pujjocento/hda_verb.c
 create mode 100644 src/mainboard/google/brya/variants/pujjocento/include/variant/ec.h
 create mode 100644 src/mainboard/google/brya/variants/pujjocento/include/variant/gpio.h
 create mode 100644 src/mainboard/google/brya/variants/pujjocento/memory.c
 create mode 100644 src/mainboard/google/brya/variants/pujjocento/memory/Makefile.mk
 create mode 100644 src/mainboard/google/brya/variants/pujjocento/memory/dram_id.generated.txt
 create mode 100644 src/mainboard/google/brya/variants/pujjocento/memory/mem_parts_used.txt
 create mode 100644 src/mainboard/google/brya/variants/pujjocento/overridetree.cb
 create mode 100644 src/mainboard/google/brya/variants/pujjocento/variant.c

diff --git a/src/mainboard/google/brya/Kconfig b/src/mainboard/google/brya/Kconfig
index 014d939160..2bc0daaf94 100644
--- a/src/mainboard/google/brya/Kconfig
+++ b/src/mainboard/google/brya/Kconfig
@@ -501,6 +501,12 @@ config BOARD_GOOGLE_PUJJONIRU
 	select MAINBOARD_HAS_GOOGLE_STRAUSS_KEYBOARD
 	select SOC_INTEL_TWINLAKE
 
+config BOARD_GOOGLE_PUJJOCENTO
+	select BOARD_GOOGLE_BASEBOARD_TRULO
+	select SOC_INTEL_COMMON_BLOCK_HDA_VERB
+	select SOC_INTEL_TCSS_USE_PDC_PMC_USBC_MUX_CONFIGURATION
+	select USE_UNIFIED_AP_FIRMWARE_FOR_UFS_AND_NON_UFS
+
 config BOARD_GOOGLE_QUANDISO
 	select BOARD_GOOGLE_BASEBOARD_NISSA
 	select CHROMEOS_WIFI_SAR if CHROMEOS
@@ -861,6 +867,7 @@ config DRIVER_TPM_I2C_BUS
 	default 0x0 if BOARD_GOOGLE_PUJJOGATWIN
 	default 0x0 if BOARD_GOOGLE_MELIKS
 	default 0x0 if BOARD_GOOGLE_EPIC
+	default 0x0 if BOARD_GOOGLE_PUJJOCENTO
 
 config DRIVER_TPM_I2C_ADDR
 	hex
@@ -946,6 +953,7 @@ config TPM_TIS_ACPI_INTERRUPT
 	default 13 if BOARD_GOOGLE_PUJJOGATWIN
 	default 13 if BOARD_GOOGLE_MELIKS
 	default 13 if BOARD_GOOGLE_EPIC
+	default 13 if BOARD_GOOGLE_PUJJOCENTO
 
 config OVERRIDE_DEVICETREE
 	default "variants/\$(CONFIG_VARIANT_DIR)/overridetree_pujjogatwin.cb" if BOARD_GOOGLE_PUJJOGATWIN
@@ -1039,6 +1047,7 @@ config MAINBOARD_PART_NUMBER
 	default "Pujjogatwin" if BOARD_GOOGLE_PUJJOGATWIN
 	default "Meliks" if BOARD_GOOGLE_MELIKS
 	default "Epic" if BOARD_GOOGLE_EPIC
+	default "Pujjocento" if BOARD_GOOGLE_PUJJOCENTO
 
 config VARIANT_DIR
 	default "agah" if BOARD_GOOGLE_AGAH
@@ -1117,6 +1126,7 @@ config VARIANT_DIR
 	default "pujjoga" if BOARD_GOOGLE_PUJJOGATWIN
 	default "meliks" if BOARD_GOOGLE_MELIKS
 	default "epic" if BOARD_GOOGLE_EPIC
+	default "pujjocento" if BOARD_GOOGLE_PUJJOCENTO
 
 config VBOOT
 	select VBOOT_EARLY_EC_SYNC if !(BOARD_GOOGLE_BASEBOARD_NISSA || BOARD_GOOGLE_BASEBOARD_TRULO) || BOARD_GOOGLE_RULL
diff --git a/src/mainboard/google/brya/Kconfig.name b/src/mainboard/google/brya/Kconfig.name
index 5431cba4c3..764226ddf8 100644
--- a/src/mainboard/google/brya/Kconfig.name
+++ b/src/mainboard/google/brya/Kconfig.name
@@ -229,3 +229,6 @@ config BOARD_GOOGLE_MELIKS
 
 config BOARD_GOOGLE_EPIC
 	bool "->  Epic"
+
+config BOARD_GOOGLE_PUJJOCENTO
+	bool "->  Pujjocento"
diff --git a/src/mainboard/google/brya/variants/pujjocento/Makefile.mk b/src/mainboard/google/brya/variants/pujjocento/Makefile.mk
new file mode 100644
index 0000000000..f265e04132
--- /dev/null
+++ b/src/mainboard/google/brya/variants/pujjocento/Makefile.mk
@@ -0,0 +1,8 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
+bootblock-y += gpio.c
+romstage-y += gpio.c
+romstage-y += memory.c
+ramstage-y += gpio.c
+ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_HDA_VERB) += hda_verb.c
+ramstage-y += variant.c
diff --git a/src/mainboard/google/brya/variants/pujjocento/gpio.c b/src/mainboard/google/brya/variants/pujjocento/gpio.c
new file mode 100644
index 0000000000..488038b9aa
--- /dev/null
+++ b/src/mainboard/google/brya/variants/pujjocento/gpio.c
@@ -0,0 +1,491 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <baseboard/gpio.h>
+#include <baseboard/variants.h>
+#include <soc/gpio.h>
+#include <types.h>
+#include <vendorcode/google/chromeos/chromeos.h>
+
+/* Pad configuration in ramstage */
+static const struct pad_config gpio_table[] = {
+	/* A0 thru A4, A9 and A10 come configured out of reset, do not touch */
+	/* A0  : ESPI_IO0 ==> ESPI_SOC_D0_EC */
+	/* A1  : ESPI_IO1 ==> ESPI_SOC_D1_EC */
+	/* A2  : ESPI_IO2 ==> ESPI_SOC_D2_EC */
+	/* A3  : ESPI_IO3 ==> ESPI_SOC_D3_EC */
+	/* A4  : ESPI_CS0# ==> ESPI_SOC_CS_EC_L */
+	/* A5  : ESPI_ALERT0# ==> NC */
+	PAD_NC(GPP_A5, NONE),
+	/* A6  : ESPI_ALERT1# ==> NC */
+	PAD_NC(GPP_A6, NONE),
+	/* A7  : NC ==> SLP_S0_GATE_R */
+	PAD_CFG_GPO(GPP_A7, 1, DEEP),
+	/* A8  : GPP_A8 ==> WWAN_RF_DISABLE_ODL */
+	PAD_CFG_GPO(GPP_A8, 1, DEEP),
+	/* A9  : ESPI_CLK ==> ESPI_SOC_CLK */
+	/* A10 : ESPI_RESET# ==> ESPI_SOC_RST_EC_L */
+	/* A11 : SOC_PD1_INT */
+	PAD_CFG_NF(GPP_A11, NONE, DEEP, NF1),
+	/* A12 : SOC_PEN_DETECT_ODL */
+	PAD_CFG_GPI_SCI_HIGH(GPP_A12, NONE, PLTRST, EDGE_BOTH),
+	/* A13 : GPP_A13 ==> GSC_SOC_INT_ODL */
+	PAD_CFG_GPI_APIC_LOCK(GPP_A13, NONE, LEVEL, INVERT, LOCK_CONFIG),
+	/* A14 : USB_OC1# */
+	PAD_CFG_NF(GPP_A14, NONE, DEEP, NF1),
+	/* A15 : USB_OC2# */
+	PAD_CFG_NF(GPP_A15, NONE, DEEP, NF1),
+	/* A16 : USB_OC3# ==> NC */
+	PAD_NC_LOCK(GPP_A16, NONE, LOCK_CONFIG),
+	/* A17 : NC */
+	PAD_NC(GPP_A17, NONE),
+	/* A18 : NC */
+	PAD_NC(GPP_A18, NONE),
+	/* A19 : NC */
+	PAD_NC(GPP_A19, NONE),
+	/* A20 : DDSP_HPD2 ==> SOC_HDMI_HPD */
+	PAD_CFG_NF(GPP_A20, NONE, DEEP, NF1),
+	/* A21 : GPP_A21 ==> USB_C1_AUX_DC_P */
+	PAD_CFG_NF(GPP_A21, NONE, DEEP, NF6),
+	/* A22 : GPP_A22 ==> USB_C1_AUX_DC_N */
+	PAD_CFG_NF(GPP_A22, NONE, DEEP, NF6),
+	/* A23 : GPP_A23 ==> NC */
+	PAD_NC(GPP_A23, NONE),
+
+	/* B0  : CORE_VID0 ==> VCCIN_AUX_VID0 */
+	PAD_CFG_NF(GPP_B0, NONE, DEEP, NF1),
+	/* B1  : CORE_VID1 ==> VCCIN_AUX_VID1 */
+	PAD_CFG_NF(GPP_B1, NONE, DEEP, NF1),
+	/* B2  : NC */
+	PAD_NC(GPP_B2, NONE),
+	/* B3  : CPU_GP2 ==> GYRO_SENSOR_INT */
+	PAD_CFG_GPI_APIC(GPP_B3, NONE, PWROK, LEVEL, INVERT),
+	/* B4  : PROC_GP3 ==> ACC_SENSOR_INT */
+	PAD_CFG_GPI_APIC(GPP_B4, NONE, PWROK, LEVEL, INVERT),
+	/* B5  : GPP_B5 ==> ISH_I2C0_SENSOR_SCL */
+	PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_B5, NONE, DEEP, NF1),
+	/* B6  : GPP_B6 ==> ISH_I2C0_SENSOR_SDA */
+	PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_B6, NONE, DEEP, NF1),
+	/* B7  : I2C3_SDA ==> SOC_I2C_SAR_SDA */
+	PAD_CFG_NF_LOCK(GPP_B7, NONE, NF2, LOCK_CONFIG),
+	/* B8  : I2C3_SCL ==> SOC_I2C_SAR_SCL */
+	PAD_CFG_NF_LOCK(GPP_B8, NONE, NF2, LOCK_CONFIG),
+	/* B9  : Not available */
+	PAD_NC(GPP_B9, NONE),
+	/* B10 : Not available */
+	PAD_NC(GPP_B10, NONE),
+	/* B11 : SOC_PD0_INT# */
+	PAD_CFG_NF(GPP_B11, NONE, DEEP, NF1),
+	/* B12 : SLP_S0# ==> PM_SLP_S0# */
+	PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1),
+	/* B13 : PLTRST# ==> PLT_RST_L */
+	PAD_CFG_NF_LOCK(GPP_B13, NONE, NF1, LOCK_CONFIG),
+	/* B14 : ACZ_SPKR */
+	PAD_CFG_NF(GPP_B14, NONE, DEEP, NF1),
+	/* B15 : NC */
+	PAD_NC_LOCK(GPP_B15, NONE, LOCK_CONFIG),
+	/* B16  : GPP_B16 ==> I2C_TOUCHPAD_SDA */
+	PAD_CFG_NF_LOCK(GPP_B16, NONE, NF2, LOCK_CONFIG),
+	/* B17  : GPP_B17 ==> I2C_TOUCHPAD_SCL */
+	PAD_CFG_NF_LOCK(GPP_B17, NONE, NF2, LOCK_CONFIG),
+	/* B18 : GPP_B18 ==> GPP_B18_STRAP */
+	PAD_NC(GPP_B18, NONE),
+	/* B19 : Not available */
+	PAD_NC(GPP_B19, NONE),
+	/* B20 : Not available */
+	PAD_NC(GPP_B20, NONE),
+	/* B21 : Not available */
+	PAD_NC(GPP_B21, NONE),
+	/* B22 : Not available */
+	PAD_NC(GPP_B22, NONE),
+	/* B23 : SML1ALERT# ==> PCHHOT_ODL_STRAP */
+	PAD_NC(GPP_B23, NONE),
+
+	/* C0  : SMBCLK ==> EN_PP3300_TCHSCR_X */
+	PAD_CFG_GPO(GPP_C0, 1, DEEP),
+	/* C1  : SMBDATA ==> TCHSCR_RST_L */
+	PAD_CFG_GPO(GPP_C1, 1, DEEP),
+	/* C2  : SMBALERT# ==> GPP_C2_STRAP */
+	PAD_NC(GPP_C2, NONE),
+	/* C3  : EN_PP3300_UCAM_X */
+	PAD_CFG_GPO_LOCK(GPP_C3, 1, LOCK_CONFIG),
+	/* C4  : TCHSCR_REPORT_EN */
+	PAD_CFG_GPO(GPP_C4, 0, DEEP),
+	/* C5  : SML0ALERT# ==> GPP_C5_STRAP */
+	PAD_NC(GPP_C5, NONE),
+	/* C6  : SML1_SMBCLK */
+	PAD_CFG_NF(GPP_C6, NONE, DEEP, NF1),
+	/* C7  : SML1_SMBDATA */
+	PAD_CFG_NF(GPP_C7, NONE, DEEP, NF1),
+
+	/* D0  : NC */
+	PAD_NC_LOCK(GPP_D0, NONE, LOCK_CONFIG),
+	/* D1  : ISH_GP1 ==> SOC_GSEN2_INT# */
+	PAD_CFG_NF(GPP_D1, NONE, DEEP, NF1),
+	/* D2  : NC */
+	PAD_NC_LOCK(GPP_D2, NONE, LOCK_CONFIG),
+	/* D3  : ISH_GP3 ==> WCAM_RST_L */
+	PAD_CFG_GPO_LOCK(GPP_D3, 0, LOCK_CONFIG),
+	/* D4  : IMGCLKOUT0 ==> BT_DISABLE_L */
+	PAD_CFG_GPO(GPP_D4, 1, DEEP),
+	/* D5  : NC */
+	PAD_NC(GPP_D5, NONE),
+	/* D6  : SRCCLKREQ1# ==> WWAN_EN */
+	PAD_CFG_GPO(GPP_D6, 1, DEEP),
+	/* D7  : SRCCLKREQ2# ==> WLAN_CLKREQ_ODL */
+	PAD_CFG_NF(GPP_D7, NONE, DEEP, NF1),
+	/* D8  : SRCCLKREQ3# ==> NC */
+	PAD_NC_LOCK(GPP_D8, NONE, LOCK_CONFIG),
+	/* D9  : NC */
+	PAD_NC_LOCK(GPP_D9, NONE, LOCK_CONFIG),
+	/* D10 : ISH_SPI_CLK ==> GPP_D10_STRAP */
+	PAD_NC_LOCK(GPP_D10, NONE, LOCK_CONFIG),
+	/* D11 : NC */
+	PAD_NC_LOCK(GPP_D11, NONE, LOCK_CONFIG),
+	/* D12 : ISH_SPI_MOSI ==> GPP_D12_STRAP */
+	PAD_NC_LOCK(GPP_D12, NONE, LOCK_CONFIG),
+	/* D13 : UART0_ISH_RX_DBG_TX */
+	PAD_CFG_NF(GPP_D13, NONE, DEEP, NF1),
+	/* D14 : UART0_ISH_TX_DBG_RX */
+	PAD_CFG_NF(GPP_D14, NONE, DEEP, NF1),
+	/* D15 : ISH_UART0_RTS# ==> EN_PP2800_WCAM_X */
+	PAD_CFG_GPO_LOCK(GPP_D15, 0, LOCK_CONFIG),
+	/* D16 : ISH_UART0_CTS# ==> EN_PP1800_PP1200_WCAM_X */
+	PAD_CFG_GPO_LOCK(GPP_D16, 0, LOCK_CONFIG),
+	/* D17 : NC */
+	PAD_NC_LOCK(GPP_D17, NONE, LOCK_CONFIG),
+	/* D18 : NC */
+	PAD_NC_LOCK(GPP_D18, NONE, LOCK_CONFIG),
+	/* D19 : I2S_MCLK1_OUT ==> NC */
+	PAD_NC(GPP_D19, NONE),
+
+	/* E0  : SOC_PEN_DETECT_R_ODL */
+	PAD_CFG_GPI_INT(GPP_E0, NONE, PLTRST, EDGE_BOTH),
+	/* E1  : THC0_SPI1_IO2 ==> MEM_STRAP_0 */
+	PAD_CFG_GPI_LOCK(GPP_E1, NONE, LOCK_CONFIG),
+	/* E2  : THC0_SPI1_IO3 ==> MEM_STRAP_1 */
+	PAD_CFG_GPI_LOCK(GPP_E2, NONE, LOCK_CONFIG),
+	/* E3  : PROC_GP0 ==> MEM_STRAP_2 */
+	PAD_CFG_GPI(GPP_E3, NONE, DEEP),
+	/* E4  : NC */
+	PAD_NC(GPP_E4, NONE),
+	/* E5  : NC */
+	PAD_NC(GPP_E5, NONE),
+	/* E6  : THC0_SPI1_RST# ==> GPP_E6_STRAP */
+	PAD_NC_LOCK(GPP_E6, NONE, LOCK_CONFIG),
+	/* E7  : NC */
+	PAD_NC(GPP_E7, NONE),
+	/* E8  : GPP_E8 ==> WLAN_DISABLE_L */
+	PAD_CFG_GPO(GPP_E8, 1, DEEP),
+	/* E9  : NC */
+	PAD_NC_LOCK(GPP_E9, NONE, LOCK_CONFIG),
+	/* E10 : EN_PP3300_WLAN_X */
+	PAD_CFG_GPO(GPP_E10, 0, DEEP),
+	/* E11 : TCHSCR_INT_ODL */
+	PAD_CFG_GPI_APIC(GPP_E11, NONE, PLTRST, LEVEL, INVERT),
+	/* E12 : THC0_SPI1_IO1 ==> SOC_WP_OD */
+	PAD_CFG_GPI_GPIO_DRIVER_LOCK(GPP_E12, NONE, LOCK_CONFIG),
+	/* E13 : THC0_SPI1_IO0 ==> SINGLE CHANNEL*/
+	PAD_CFG_GPI_LOCK(GPP_E13, NONE, LOCK_CONFIG),
+	/* E14 : DDSP_HPDA ==> EDP_HPD */
+	PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1),
+	/* E15 : NC */
+	PAD_NC(GPP_E15, NONE),
+	/* E16 : NC */
+	PAD_NC(GPP_E16, NONE),
+	/* E17  : WWAN_RST_L */
+	PAD_CFG_GPO_LOCK(GPP_E17, 1, LOCK_CONFIG),
+	/* E18 : NC */
+	PAD_NC(GPP_E18, NONE),
+	/* E19 : DDP1_CTRLDATA ==> GPP_E19_STRAP */
+	PAD_NC(GPP_E19, NONE),
+	/* E20 : DDP2_CTRLCLK ==> HDMI_DDC_SCL */
+	PAD_CFG_NF(GPP_E20, NONE, DEEP, NF1),
+	/* E21 : DDP2_CTRLDATA ==> HDMI_DDC_SDA_STRAP */
+	PAD_CFG_NF(GPP_E21, NONE, DEEP, NF1),
+	/* E22 : DDPA_CTRLCLK ==> USB_C0_AUX_DC_P */
+	PAD_CFG_NF(GPP_E22, NONE, DEEP, NF6),
+	/* E23 : DDPA_CTRLDATA ==> USB_C0_AUX_DC_N */
+	PAD_CFG_NF(GPP_E23, NONE, DEEP, NF6),
+
+	/* F0  : CNV_BRI_DT ==> CNV_BRI_DT_STRAP */
+	PAD_CFG_NF(GPP_F0, NONE, DEEP, NF1),
+	/* F1  : CNV_BRI_RSP ==> CNV_BRI_RSP */
+	PAD_CFG_NF(GPP_F1, UP_20K, DEEP, NF1),
+	/* F2  : CNV_RGI_DT ==> CNV_RGI_DT_STRAP */
+	PAD_CFG_NF(GPP_F2, NONE, DEEP, NF1),
+	/* F3  : CNV_RGI_RSP ==> CNV_RGI_RSP */
+	PAD_CFG_NF(GPP_F3, UP_20K, DEEP, NF1),
+	/* F4  : CNV_RF_RESET# ==> CNV_RF_RST_L */
+	PAD_CFG_NF(GPP_F4, NONE, DEEP, NF1),
+	/* F5  : CRF_XTAL_CLKREQ ==> CNV_CLKREQ0 */
+	PAD_CFG_NF(GPP_F5, NONE, DEEP, NF3),
+	/* F6  : CNV_PA_BLANKING ==> WLAN_WWAN_COEX_3 */
+	PAD_CFG_NF(GPP_F6, NONE, DEEP, NF1),
+	/* F7  : GPP_F7 ==> GPP_F7_STRAP */
+	PAD_NC(GPP_F7, NONE),
+	/* F8  : Not available */
+	PAD_NC(GPP_F8, NONE),
+	/* F9  : Not available */
+	PAD_NC(GPP_F9, NONE),
+	/* F10 : GPP_F10 ==> GPP_F10_STRAP */
+	PAD_NC(GPP_F10, NONE),
+	/* F11 : NC */
+	PAD_NC_LOCK(GPP_F11, NONE, LOCK_CONFIG),
+	/* F12 : NC */
+	PAD_NC_LOCK(GPP_F12, NONE, LOCK_CONFIG),
+	/* F13 : NC */
+	PAD_NC(GPP_F13, NONE),
+	/* F14 : GSXDIN ==> TCHPAD_INT_ODL */
+	PAD_CFG_GPI_IRQ_WAKE(GPP_F14, NONE, PWROK, LEVEL, INVERT),
+	/* F15 : NC */
+	PAD_NC_LOCK(GPP_F15, NONE, LOCK_CONFIG),
+	/* F16 : NC */
+	PAD_NC_LOCK(GPP_F16, NONE, LOCK_CONFIG),
+	/* F17 : THC1_SPI2_RST# ==> EC_SOC_WAKE_ODL */
+	PAD_CFG_GPI_IRQ_WAKE_LOCK(GPP_F17, NONE, EDGE_SINGLE, INVERT, LOCK_CONFIG),
+	/* F18 : THC1_SPI2_INT# ==> EC_IN_RW_OD */
+	PAD_CFG_GPI_LOCK(GPP_F18, NONE, LOCK_CONFIG),
+	/* F19 : Not available */
+	PAD_NC(GPP_F19, NONE),
+	/* F20 : Not available */
+	PAD_NC(GPP_F20, NONE),
+	/* F21 : Not available */
+	PAD_NC(GPP_F21, NONE),
+	/* F22 : NC */
+	PAD_NC(GPP_F22, NONE),
+	/* F23 : V1P05_CTRL ==> V1P05EXT_CTRL */
+	PAD_CFG_NF(GPP_F23, NONE, DEEP, NF1),
+
+	/* H0  : GPP_H0_STRAP */
+	PAD_NC(GPP_H0, NONE),
+	/* H1  : GPP_H1_STRAP */
+	PAD_NC(GPP_H1, NONE),
+	/* H2  : GPP_H2_STRAP */
+	PAD_NC(GPP_H2, NONE),
+	/* H3  : SX_EXIT_HOLDOFF# ==> WLAN_PCIE_WAKE_ODL */
+	PAD_CFG_GPI_SCI_LOW_LOCK(GPP_H3, NONE, EDGE_SINGLE, LOCK_CONFIG),
+	/* H4  : I2C0_SDA ==> SOC_I2C_GSC_SDA */
+	PAD_CFG_NF_LOCK(GPP_H4, NONE, NF1, LOCK_CONFIG),
+	/* H5  : I2C0_SCL ==> SOC_I2C_GSC_SCL */
+	PAD_CFG_NF_LOCK(GPP_H5, NONE, NF1, LOCK_CONFIG),
+	/* H6  : I2C1_SDA ==> SOC_I2C_TCHSCR_SDA */
+	PAD_CFG_NF(GPP_H6, NONE, DEEP, NF1),
+	/* H7  : I2C1_SCL ==> SOC_I2C_TCHSCR_SCL */
+	PAD_CFG_NF(GPP_H7, NONE, DEEP, NF1),
+	/* H8  : MIPI_WCAM_SDA */
+	PAD_CFG_NF(GPP_H8, NONE, DEEP, NF1),
+	/* H9  : MIPI_WCAM_SCL */
+	PAD_CFG_NF(GPP_H9, NONE, DEEP, NF1),
+	/* H10 : UART0_RXD ==> UART_SOC_RX_DBG_TX */
+	PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2),
+	/* H11 : UART0_TXD ==> UART_SOC_TX_DBG_RX */
+	PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2),
+	/* H12 : GPP_H12 ==> NC */
+	PAD_NC_LOCK(GPP_H12, NONE, LOCK_CONFIG),
+	/* H13 : GPP_H13 ==> NC */
+	PAD_NC_LOCK(GPP_H13, NONE, LOCK_CONFIG),
+	/* H14 : Not available */
+	PAD_NC(GPP_H14, NONE),
+	/* H15  : DDPB_CTRLCLK ==> SOC_DP2_CTRL_CLK */
+	PAD_CFG_NF(GPP_H15, NONE, DEEP, NF1),
+	/* H16 : Not available */
+	PAD_NC(GPP_H16, NONE),
+	/* H17  : DDPB_CTRLDATA ==> SOC_DP2_CTRL_DATA */
+	PAD_CFG_NF(GPP_H17, NONE, DEEP, NF1),
+	/* H18 : PROC_C10_GATE# ==> CPU_C10_GATE# */
+	PAD_CFG_NF(GPP_H18, NONE, DEEP, NF1),
+	/* H19 : SAR_INT_L */
+	PAD_CFG_GPI_APIC(GPP_H19, NONE, PLTRST, LEVEL, NONE),
+	/* H20 : IMGCLKOUT1 ==> WLAN_PERST_L */
+	PAD_CFG_GPO(GPP_H20, 1, DEEP),
+	/* H21 : NC */
+	PAD_NC(GPP_H21, NONE),
+	/* H22 : IMGCLKOUT3 ==> WCAM_MCLK_R */
+	PAD_CFG_NF(GPP_H22, NONE, DEEP, NF1),
+	/* H23 : GPP_H23 ==> WWAN_SAR_DETECT_ODL */
+	PAD_CFG_GPO(GPP_H23, 1, DEEP),
+
+	/* R0  : HDA_BCLK ==> HDA_BIT_CLK */
+	PAD_CFG_NF(GPP_R0, NONE, DEEP, NF1),
+	/* R1  : HDA_SYNC ==> HDA_SYNC */
+	PAD_CFG_NF(GPP_R1, NONE, DEEP, NF1),
+	/* R2 : HDA_SDO ==> HDA_SDOUT */
+	PAD_CFG_NF(GPP_R2, NONE, DEEP, NF1),
+	/* R3 : HDA_SDI0 ==> HDA_SDIN0 */
+	PAD_CFG_NF(GPP_R3, NONE, DEEP, NF1),
+	/* R4 : HDA_RST# ==> HDA_RST# */
+	PAD_CFG_NF(GPP_R4, NONE, DEEP, NF1),
+	/* R5 : HDA_SDI1 ==> HDA_SDIN1 */
+	PAD_CFG_NF(GPP_R5, NONE, DEEP, NF1),
+	/* R6 : DMIC_CLK_A_1A ==> DMIC_WCAM_CLK_R */
+	PAD_CFG_NF(GPP_R6, NONE, DEEP, NF3),
+	/* R7 : DMIC_DATA_1A ==> DMIC_WCAM_DATA */
+	PAD_CFG_NF(GPP_R7, NONE, DEEP, NF3),
+
+	/* S0  : I2S_SPK_BCLK_R ==> NC */
+	PAD_NC(GPP_S0, NONE),
+	/* S1  : I2S_SPK_LRCK_R ==> NC */
+	PAD_NC(GPP_S1, NONE),
+	/* S2 : DMIC_CKL_A0 ==> NC */
+	PAD_NC(GPP_S2, NONE),
+	/* S3 : DMIC_DATA0 ==> NC */
+	PAD_NC(GPP_S3, NONE),
+	/* S4  : NC */
+	PAD_NC(GPP_S4, NONE),
+	/* S5  : NC */
+	PAD_NC(GPP_S5, NONE),
+	/* S6  : NC */
+	PAD_NC(GPP_S6, NONE),
+	/* S7  : NC */
+	PAD_NC(GPP_S7, NONE),
+
+	/* I5  : NC */
+	PAD_NC(GPP_I5, NONE),
+	/* I7  : EMMC_CMD ==> NC */
+	PAD_NC(GPP_I7, NONE),
+	/* I8  : EMMC_DATA0 ==> NC */
+	PAD_NC(GPP_I8, NONE),
+	/* I9  : EMMC_DATA1 ==> NC */
+	PAD_NC(GPP_I9, NONE),
+	/* I10 : EMMC_DATA2 ==> NC */
+	PAD_NC(GPP_I10, NONE),
+	/* I11 : EMMC_DATA3 ==> NC */
+	PAD_NC(GPP_I11, NONE),
+	/* I12 : EMMC_DATA4 ==> NC */
+	PAD_NC(GPP_I12, NONE),
+	/* I13 : EMMC_DATA5 ==> NC */
+	PAD_NC(GPP_I13, NONE),
+	/* I14 : EMMC_DATA6 ==> NC */
+	PAD_NC(GPP_I14, NONE),
+	/* I15 : EMMC_DATA7 ==> NC */
+	PAD_NC(GPP_I15, NONE),
+	/* I16 : EMMC_RCLK ==> NC */
+	PAD_NC(GPP_I16, NONE),
+	/* I17 : EMMC_CLK ==> NC */
+	PAD_NC(GPP_I17, NONE),
+	/* I18 : EMMC_RESET# ==> NC */
+	PAD_NC(GPP_I18, NONE),
+
+	/* GPD0  : BATLOW# ==> SOC_BATLOW_L */
+	PAD_CFG_NF(GPD0, NONE, DEEP, NF1),
+	/* GPD1  : ACPRESENT ==> SOC_ACPRESENT */
+	PAD_CFG_NF(GPD1, NONE, DEEP, NF1),
+	/* GPD2  : EC_SOC_INT_ODL */
+	PAD_CFG_GPI_APIC(GPD2, NONE, PLTRST, LEVEL, INVERT),
+	/* GPD3  : PWRBTN# ==> EC_SOC_PWR_BTN_ODL */
+	PAD_CFG_NF(GPD3, NONE, DEEP, NF1),
+	/* GPD4  : SLP_S3# ==> SLP_S3_L */
+	PAD_CFG_NF(GPD4, NONE, DEEP, NF1),
+	/* GPD5  : SLP_S4# ==> SLP_S4_L */
+	PAD_CFG_NF(GPD5, NONE, DEEP, NF1),
+	/* GPD6  : SLP_A# ==> NC */
+	PAD_NC(GPD6, NONE),
+	/* GPD7  : GPD7_STRAP */
+	PAD_NC(GPD7, NONE),
+	/* GPD8  : SUSCLK ==> PCH_SUSCLK */
+	PAD_CFG_NF(GPD8, NONE, DEEP, NF1),
+	/* GPD9  : NC */
+	PAD_NC(GPD9, NONE),
+	/* GPD10 : SLP_S5# ==> NC */
+	PAD_NC(GPD10, NONE),
+	/* GPD11 : NC */
+	PAD_NC(GPD11, NONE),
+
+	/* Configure the unused virtual CNVi Bluetooth UART pads to NC mode. */
+	/* vCNV_BT_UART_TXD */
+	PAD_NC(GPP_VGPIO_6, NONE),
+	/* vCNV_BT_UART_RXD */
+	PAD_NC(GPP_VGPIO_7, NONE),
+	/* vCNV_BT_UART_CTS_B */
+	PAD_NC(GPP_VGPIO_8, NONE),
+	/* vCNV_BT_UART_RTS_B */
+	PAD_NC(GPP_VGPIO_9, NONE),
+
+	/* Configure the unused vUART for Bluetooth pads to NC mode. */
+	/* vUART0_TXD */
+	PAD_NC(GPP_VGPIO_18, NONE),
+	/* vUART0_RXD */
+	PAD_NC(GPP_VGPIO_19, NONE),
+	/* vUART0_CTS_B */
+	PAD_NC(GPP_VGPIO_20, NONE),
+	/* vUART0_RTS_B */
+	PAD_NC(GPP_VGPIO_21, NONE),
+
+	/* Configure the virtual CNVi Bluetooth I2S GPIO Pads.*/
+	/* BT_I2S_BCLK */
+	PAD_CFG_NF(GPP_VGPIO_30, NONE, DEEP, NF3),
+	/* BT_I2S_SYNC */
+	PAD_CFG_NF(GPP_VGPIO_31, NONE, DEEP, NF3),
+	/* BT_I2S_SDO */
+	PAD_CFG_NF(GPP_VGPIO_32, NONE, DEEP, NF3),
+	/* BT_I2S_SDI */
+	PAD_CFG_NF(GPP_VGPIO_33, NONE, DEEP, NF3),
+	/* SSP2_SCLK */
+	PAD_CFG_NF(GPP_VGPIO_34, NONE, DEEP, NF1),
+	/* SSP2_SFRM */
+	PAD_CFG_NF(GPP_VGPIO_35, NONE, DEEP, NF1),
+	/* SSP_TXD */
+	PAD_CFG_NF(GPP_VGPIO_36, NONE, DEEP, NF1),
+	/* SSP_RXD */
+	PAD_CFG_NF(GPP_VGPIO_37, NONE, DEEP, NF1),
+};
+
+/* Early pad configuration in bootblock */
+static const struct pad_config early_gpio_table[] = {
+	/* C0  : SMBCLK ==> EN_PP3300_TCHSCR_X */
+	PAD_CFG_GPO(GPP_C0, 1, DEEP),
+	/* C1  : SMBDATA ==> TCHSCR_RST_L */
+	PAD_CFG_GPO(GPP_C1, 1, DEEP),
+	/* A13 : GPP_A13 ==> GSC_SOC_INT_ODL */
+	PAD_CFG_GPI_APIC(GPP_A13, NONE, PLTRST, LEVEL, INVERT),
+	/* E3 : PROC_GP0 ==> SOC_WP_OD */
+	PAD_CFG_GPI_GPIO_DRIVER(GPP_E12, NONE, DEEP),
+	/* F18 : THC1_SPI2_INT# ==> EC_IN_RW_OD */
+	PAD_CFG_GPI(GPP_F18, NONE, DEEP),
+	/* H4  : I2C0_SDA ==> SOC_I2C_GSC_SDA */
+	PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1),
+	/* H5  : I2C0_SCL ==> SOC_I2C_GSC_SCL */
+	PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1),
+	/* H10 : UART0_RXD ==> UART_SOC_RX_DBG_TX */
+	PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2),
+	/* H11 : UART0_TXD ==> UART_SOC_TX_DBG_RX */
+	PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2),
+	/* E13 : THC0_SPI1_IO0 ==> SINGLE CHANNEL */
+	PAD_CFG_GPI(GPP_E13, NONE, DEEP),
+	/* H20 : IMGCLKOUT1 ==> WLAN_PERST_L */
+	PAD_CFG_GPO(GPP_H20, 0, DEEP),
+};
+
+/* Fill romstage gpio configuration */
+static const struct pad_config romstage_gpio_table[] = {
+};
+
+const struct pad_config *variant_gpio_table(size_t *num)
+{
+	*num = ARRAY_SIZE(gpio_table);
+	return gpio_table;
+}
+
+const struct pad_config *variant_gpio_override_table(size_t *num)
+{
+	*num = 0;
+	return NULL;
+}
+
+const struct pad_config *variant_early_gpio_table(size_t *num)
+{
+	*num = ARRAY_SIZE(early_gpio_table);
+	return early_gpio_table;
+}
+
+static const struct cros_gpio cros_gpios[] = {
+	CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME),
+	CROS_GPIO_WP_AH(GPIO_PCH_WP, CROS_GPIO_DEVICE_NAME),
+};
+DECLARE_CROS_GPIOS(cros_gpios);
+
+const struct pad_config *variant_romstage_gpio_table(size_t *num)
+{
+	*num = ARRAY_SIZE(romstage_gpio_table);
+	return romstage_gpio_table;
+}
diff --git a/src/mainboard/google/brya/variants/pujjocento/hda_verb.c b/src/mainboard/google/brya/variants/pujjocento/hda_verb.c
new file mode 100644
index 0000000000..bf998e1f0c
--- /dev/null
+++ b/src/mainboard/google/brya/variants/pujjocento/hda_verb.c
@@ -0,0 +1,128 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <device/azalia_device.h>
+
+const u32 cim_verb_data[] = {
+	/* coreboot specific header */
+	0x10ec0256,	// Codec Vendor / Device ID: Realtek ALC256
+	0x10ec12ac,	// Subsystem ID
+	0x00000013,	// Number of jacks (NID entries)
+
+	AZALIA_RESET(0x1),
+	/* NID 0x01, HDA Codec Subsystem ID Verb table */
+	AZALIA_SUBVENDOR(0, 0x10ec12ac),
+
+	/* Pin Widget Verb Table */
+
+	/*
+	 * DMIC
+	 * Requirement is to use PCH DMIC. Hence,
+	 * commented out codec's Internal DMIC.
+	 * AZALIA_PIN_CFG(0, 0x12, 0x90A60130),
+	 * AZALIA_PIN_CFG(0, 0x13, 0x40000000),
+	 */
+
+	/* Pin widget 0x14 - Front (Port-D) */
+	AZALIA_PIN_CFG(0, 0x14, 0x90170110),
+	/* Pin widget 0x18 - NPC */
+	AZALIA_PIN_CFG(0, 0x18, 0x411111F0),
+	/* Pin widget 0x19 - MIC2 (Port-F) */
+	AZALIA_PIN_CFG(0, 0x19, 0x04A11040),
+	/* Pin widget 0x1A - LINE1 (Port-C) */
+	AZALIA_PIN_CFG(0, 0x1a, 0x411111F0),
+	/* Pin widget 0x1B - NPC */
+	AZALIA_PIN_CFG(0, 0x1b, 0x411111F0),
+	/* Pin widget 0x1D - BEEP-IN */
+	AZALIA_PIN_CFG(0, 0x1d, 0x40610041),
+	/* Pin widget 0x1E - NPC */
+	AZALIA_PIN_CFG(0, 0x1e, 0x411111F0),
+	/* Pin widget 0x21 - HP1-OUT (Port-I) */
+	AZALIA_PIN_CFG(0, 0x21, 0x04211020),
+	/*
+	 * Widget node 0x20 - 1
+	 * Codec hidden reset and speaker power 2W/4ohm
+	 */
+	0x0205001A,
+	0x0204C003,
+	0x02050038,
+	0x02047901,
+	/*
+	 * Widget node 0x20 - 2
+	 * Class D power on Reset
+	 */
+	0x0205003C,
+	0x02040354,
+	0x0205003C,
+	0x02040314,
+	/*
+	 * Widget node 0x20 - 3
+	 * Disable AGC and set AGC limit to -1.5dB
+	 */
+	0x02050016,
+	0x02040C50,
+	0x02050012,
+	0x0204EBC1,
+	/*
+	 * Widget node 0x20 - 4
+	 * Set AGC Post gain +1.5dB then Enable AGC
+	 */
+	0x02050013,
+	0x02044023,
+	0x02050016,
+	0x02040E50,
+	/*
+	 * Widget node 0x20 - 5
+	 * Silence detector enabling + Set EAPD to verb control
+	 */
+	0x02050037,
+	0x0204FE15,
+	0x02050010,
+	0x02040020,
+	/*
+	 * Widget node 0x20 - 6
+	 * Silence data mode Threshold (-90dB)
+	 */
+	0x02050030,
+	0x0204A000,
+	0x0205001B,
+	0x02040A4B,
+	/*
+	 * Widget node 0x20 - 7
+	 * Default setting - 1
+	 */
+	0x05750003,
+	0x05740DA3,
+	0x02050046,
+	0x02040004,
+	/*
+	 * Widget node 0x20 - 8
+	 * support 1 pin detect two port
+	 */
+	0x02050009,
+	0x0204E003,
+	0x0205000A,
+	0x02047770,
+	/*
+	 * Widget node 0x20 - 9
+	 * To set LDO1/LDO2 as default (used for headset)
+	 */
+	0x02050008,
+	0x02046A0C,
+	0x02050008,
+	0x02046A0C,
+};
+
+const u32 pc_beep_verbs[] = {
+	/* Dos beep path - 1 */
+	0x01470C00,
+	0x02050036,
+	0x02047151,
+	0x01470740,
+	/* Dos beep path - 2 */
+	0x0143b000,
+	0x01470C02,
+	0x01470C02,
+	0x01470C02,
+};
+
+AZALIA_ARRAY_SIZES;
diff --git a/src/mainboard/google/brya/variants/pujjocento/include/variant/ec.h b/src/mainboard/google/brya/variants/pujjocento/include/variant/ec.h
new file mode 100644
index 0000000000..7a2a6ff8b7
--- /dev/null
+++ b/src/mainboard/google/brya/variants/pujjocento/include/variant/ec.h
@@ -0,0 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#ifndef __VARIANT_EC_H__
+#define __VARIANT_EC_H__
+
+#include <baseboard/ec.h>
+
+#endif
diff --git a/src/mainboard/google/brya/variants/pujjocento/include/variant/gpio.h b/src/mainboard/google/brya/variants/pujjocento/include/variant/gpio.h
new file mode 100644
index 0000000000..be080eb46e
--- /dev/null
+++ b/src/mainboard/google/brya/variants/pujjocento/include/variant/gpio.h
@@ -0,0 +1,11 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#ifndef VARIANT_GPIO_H
+#define VARIANT_GPIO_H
+
+#include <baseboard/gpio.h>
+
+#define WWAN_RST	GPP_E17
+#define T2_OFF_MS	20
+#define SLP_S0_HDMI_EN	GPP_A7
+#endif
diff --git a/src/mainboard/google/brya/variants/pujjocento/memory.c b/src/mainboard/google/brya/variants/pujjocento/memory.c
new file mode 100644
index 0000000000..bb80ee15ec
--- /dev/null
+++ b/src/mainboard/google/brya/variants/pujjocento/memory.c
@@ -0,0 +1,111 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <baseboard/variants.h>
+#include <gpio.h>
+#include <soc/romstage.h>
+
+static const struct mb_cfg variant_memcfg = {
+	.type = MEM_TYPE_LP5X,
+
+	.rcomp = {
+		/* Baseboard uses only 100ohm Rcomp resistors */
+		.resistor = 100,
+	},
+
+	/* DQ byte map */
+	.lpx_dq_map = {
+		.ddr0 = {
+			.dq0 = { 12,  9, 10, 11, 14, 13,  8, 15 },
+			.dq1 = {  3,  1,  2,  0,  4,  7,  5,  6 },
+		},
+		.ddr1 = {
+			.dq0 = {  3,  1,  2,  0,  4,  7,  5,  6 },
+			.dq1 = { 13,  9,  8, 11, 10, 14, 15, 12 },
+		},
+		.ddr2 = {
+			.dq0 = {  2,  1,  3,  0,  4,  6,  5,  7 },
+			.dq1 = {  8,  9, 10, 11, 13, 14, 12, 15 },
+		},
+		.ddr3 = {
+			.dq0 = {  3,  0,  1,  2,  5,  6,  4,  7 },
+			.dq1 = { 13,  9, 11,  8, 14, 15, 10, 12 },
+		},
+		.ddr4 = {
+			.dq0 = { 12,  9, 10, 11, 14, 13,  8, 15 },
+			.dq1 = {  3,  1,  2,  0,  4,  7,  5,  6 },
+		},
+		.ddr5 = {
+			.dq0 = {  3,  1,  2,  0,  4,  7,  5,  6 },
+			.dq1 = { 13,  9,  8, 11, 10, 14, 15, 12 },
+		},
+		.ddr6 = {
+			.dq0 = {  2,  1,  3,  0,  4,  6,  5,  7 },
+			.dq1 = {  8,  9, 10, 11, 13, 14, 12, 15 },
+		},
+		.ddr7 = {
+			.dq0 = {  3,  0,  1,  2,  5,  6,  4,  7 },
+			.dq1 = { 13,  9, 11,  8, 14, 15, 10, 12 },
+		},
+	},
+
+	/* DQS CPU<>DRAM map */
+	.lpx_dqs_map = {
+		.ddr0 = { .dqs0 = 1, .dqs1 = 0 },
+		.ddr1 = { .dqs0 = 0, .dqs1 = 1 },
+		.ddr2 = { .dqs0 = 0, .dqs1 = 1 },
+		.ddr3 = { .dqs0 = 0, .dqs1 = 1 },
+		.ddr4 = { .dqs0 = 1, .dqs1 = 0 },
+		.ddr5 = { .dqs0 = 0, .dqs1 = 1 },
+		.ddr6 = { .dqs0 = 0, .dqs1 = 1 },
+		.ddr7 = { .dqs0 = 0, .dqs1 = 1 },
+	},
+
+	.lp5x_config = {
+		.ccc_config = 0xff,
+	},
+
+	.ect = 1, /* Early Command Training */
+
+	.UserBd = BOARD_TYPE_MOBILE,
+};
+
+const struct mb_cfg *variant_memory_params(void)
+{
+	return &variant_memcfg;
+}
+
+int variant_memory_sku(void)
+{
+	/*
+	 * Memory configuration board straps
+	 * GPIO_MEM_CONFIG_0	GPP_E1
+	 * GPIO_MEM_CONFIG_1	GPP_E2
+	 * GPIO_MEM_CONFIG_2	GPP_E3
+	 */
+	gpio_t spd_gpios[] = {
+		GPP_E1,
+		GPP_E2,
+		GPP_E3,
+	};
+
+	return gpio_base2_value(spd_gpios, ARRAY_SIZE(spd_gpios));
+}
+
+bool variant_is_half_populated(void)
+{
+	/*
+	 * Ideally half_populated is used in platforms with multiple channels to
+	 * enable only one half of the channel. Alder Lake N has single channel,
+	 * and it would require for new structures to be defined in meminit block
+	 * driver for LPx memory configurations. In order to avoid adding new
+	 * structures, set half_populated to true. This has the same effect as
+	 * having single channel with 64-bit width.
+	*/
+	return true;
+}
+
+void variant_get_spd_info(struct mem_spd *spd_info)
+{
+	spd_info->topo = MEM_TOPO_MEMORY_DOWN;
+	spd_info->cbfs_index = variant_memory_sku();
+}
diff --git a/src/mainboard/google/brya/variants/pujjocento/memory/Makefile.mk b/src/mainboard/google/brya/variants/pujjocento/memory/Makefile.mk
new file mode 100644
index 0000000000..c60f5439fe
--- /dev/null
+++ b/src/mainboard/google/brya/variants/pujjocento/memory/Makefile.mk
@@ -0,0 +1,10 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+# This is an auto-generated file. Do not edit!!
+# Generated by:
+# util/spd_tools/bin/part_id_gen ADL lp5 src/mainboard/google/brya/variants/pujjocento/memory src/mainboard/google/brya/variants/pujjocento/memory/mem_parts_used.txt
+
+SPD_SOURCES =
+SPD_SOURCES += spd/lp5/set-0/spd-9.hex      # ID = 0(0b0000)  Parts = K3KL6L60GM-MGCT
+SPD_SOURCES += spd/lp5/set-0/spd-1.hex      # ID = 1(0b0001)  Parts = H9JCNNNBK3MLYR-N6E
+SPD_SOURCES += spd/lp5/set-0/spd-11.hex      # ID = 2(0b0010)  Parts = H58G56CK8BX146
+SPD_SOURCES += spd/lp5/set-0/spd-7.hex      # ID = 3(0b0011)  Parts = K3KL8L80CM-MGCT
diff --git a/src/mainboard/google/brya/variants/pujjocento/memory/dram_id.generated.txt b/src/mainboard/google/brya/variants/pujjocento/memory/dram_id.generated.txt
new file mode 100644
index 0000000000..94e605c7b2
--- /dev/null
+++ b/src/mainboard/google/brya/variants/pujjocento/memory/dram_id.generated.txt
@@ -0,0 +1,10 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+# This is an auto-generated file. Do not edit!!
+# Generated by:
+# util/spd_tools/bin/part_id_gen ADL lp5 src/mainboard/google/brya/variants/pujjocento/memory src/mainboard/google/brya/variants/pujjocento/memory/mem_parts_used.txt
+
+DRAM Part Name                 ID to assign
+K3KL6L60GM-MGCT                0 (0000)
+H9JCNNNBK3MLYR-N6E             1 (0001)
+H58G56CK8BX146                 2 (0010)
+K3KL8L80CM-MGCT                3 (0011)
diff --git a/src/mainboard/google/brya/variants/pujjocento/memory/mem_parts_used.txt b/src/mainboard/google/brya/variants/pujjocento/memory/mem_parts_used.txt
new file mode 100644
index 0000000000..e38d99697d
--- /dev/null
+++ b/src/mainboard/google/brya/variants/pujjocento/memory/mem_parts_used.txt
@@ -0,0 +1,15 @@
+# This is a CSV file containing a list of memory parts used by this variant.
+# One part per line with an optional fixed ID in column 2.
+# Only include a fixed ID if it is required for legacy reasons!
+# Generated IDs are dependent on the order of parts in this file,
+# so new parts must always be added at the end of the file!
+#
+# Generate an updated Makefile.mk and dram_id.generated.txt by running the
+# part_id_gen tool from util/spd_tools.
+# See util/spd_tools/README.md for more details and instructions.
+
+# Part Name
+K3KL6L60GM-MGCT
+H9JCNNNBK3MLYR-N6E
+H58G56CK8BX146
+K3KL8L80CM-MGCT
diff --git a/src/mainboard/google/brya/variants/pujjocento/overridetree.cb b/src/mainboard/google/brya/variants/pujjocento/overridetree.cb
new file mode 100644
index 0000000000..4a9ae54d8a
--- /dev/null
+++ b/src/mainboard/google/brya/variants/pujjocento/overridetree.cb
@@ -0,0 +1,513 @@
+fw_config
+	field WIFI 3 4
+		option WIFI_CNVI_WIFI6E		0
+		option WIFI_PCIE_WIFI7		1
+		option WIFI_UNKNOWN		2
+	end
+	field THERMAL_SOLUTION 9 9
+		option THERMAL_SOLUTION_6W	0
+		option THERMAL_SOLUTION_15W	1
+	end
+	field PDC_CONTROL 11 12
+		option PDC_CONTROL_UNKNOWN	0
+		option PDC_RTS_BYPASS		1
+		option PDC_TI_BYPASS		2
+	end
+end
+
+chip soc/intel/alderlake
+	register "sagv" = "SaGv_Enabled"
+
+	# GPE configuration
+	register "pmc_gpe0_dw0" = "GPP_A"
+	register "pmc_gpe0_dw1" = "GPP_H"
+	register "pmc_gpe0_dw2" = "GPP_F"
+
+	# S0ix enable
+	register "s0ix_enable" = "true"
+
+	# DPTF enable
+	register "dptf_enable" = "true"
+
+	register "tcc_offset" = "10"     # TCC of 90
+
+	# Enable CNVi BT
+	register "cnvi_bt_core" = "true"
+
+
+	register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC_SKIP)"	# Type-C MB (7.5 inch)
+	register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC_SKIP)"	# Type-C DB (7.1 inch)
+	register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)"		# Type-A MB (6.4 inch)
+	register "usb2_ports[3]" = "USB2_PORT_MID(OC_SKIP)"		# Type-A DB (6.2 inch)
+	register "usb2_ports[4]" = "USB2_PORT_SHORT(OC_SKIP)"	# LTE (3.3 inch)
+	register "usb2_ports[5]" = "USB2_PORT_SHORT(OC_SKIP)"	# UFC (3.7 inch)
+	register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)"	# Bluetooth port for PCIe WLAN (2.5 inch)
+	register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)"	# Bluetooth port for CNVi WLAN
+
+	register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)"	# USB3 Type-A port A0(MLB))
+	register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)"	# USB3 Type-A port A1(DB)
+	register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)"	# USB3 WWAN(LTE)
+
+	register "tcss_ports[0]" = "TCSS_PORT_DEFAULT(OC_SKIP)"
+
+
+	# HD Audio
+	register "pch_hda_dsp_enable" = "1"
+	register "pch_hda_audio_link_hda_enable" = "1"
+	register "pch_hda_idisp_link_tmode" = "HDA_TMODE_8T"
+	register "pch_hda_idisp_link_frequency" = "HDA_LINKFREQ_96MHZ"
+	register "pch_hda_idisp_codec_enable" = "1"
+
+	# FIVR configurations for rull are disabled since the board doesn't have V1p05 and Vnn
+	# bypass rails implemented.
+	register "ext_fivr_settings" = "{
+		.configure_ext_fivr = 0,
+	}"
+
+	# Enable CNVi BT Audio offload
+	register "cnvi_bt_audio_offload" = "1"
+
+	register "serial_io_i2c_mode" = "{
+		[PchSerialIoIndexI2C0] = PchSerialIoPci,
+		[PchSerialIoIndexI2C1] = PchSerialIoPci,
+		[PchSerialIoIndexI2C2] = PchSerialIoDisabled,
+		[PchSerialIoIndexI2C3] = PchSerialIoDisabled,
+		[PchSerialIoIndexI2C4] = PchSerialIoDisabled,
+		[PchSerialIoIndexI2C5] = PchSerialIoDisabled,
+	}"
+
+	register "serial_io_gspi_mode" = "{
+		[PchSerialIoIndexGSPI0] = PchSerialIoDisabled,
+		[PchSerialIoIndexGSPI1] = PchSerialIoDisabled,
+	}"
+
+	register "serial_io_uart_mode" = "{
+		[PchSerialIoIndexUART0] = PchSerialIoPci,
+		[PchSerialIoIndexUART1] = PchSerialIoDisabled,
+		[PchSerialIoIndexUART2] = PchSerialIoDisabled,
+	}"
+
+	# FIXME: To be enabled in future based on PNP impact data.
+	# Disable Package C-state demotion for nissa baseboard.
+	register "disable_package_c_state_demotion" = "true"
+
+	# Intel Common SoC Config
+	#+-------------------+---------------------------+
+	#| Field             |  Value                    |
+	#+-------------------+---------------------------+
+	#| I2C0              | TPM. Early init is        |
+	#|                   | required to set up a BAR  |
+	#|                   | for TPM communication     |
+	#| I2C1              | Trackpad                  |
+	#+-------------------+---------------------------+
+	register "common_soc_config" = "{
+		.i2c[0] = {
+			.early_init = 1,
+			.speed = I2C_SPEED_FAST_PLUS,
+			.speed_config[0] = {
+				.speed = I2C_SPEED_FAST_PLUS,
+				.scl_lcnt = 55,
+				.scl_hcnt = 30,
+				.sda_hold = 7,
+			}
+		},
+		.i2c[1] = {
+			.speed = I2C_SPEED_FAST,
+			.speed_config[0] = {
+				.speed = I2C_SPEED_FAST,
+				.scl_lcnt = 158,
+				.scl_hcnt = 79,
+				.sda_hold = 7,
+			}
+		},
+		.i2c[5] = {
+			.speed = I2C_SPEED_FAST,
+			.speed_config[0] = {
+				.speed = I2C_SPEED_FAST,
+				.scl_lcnt = 150,
+				.scl_hcnt = 85,
+				.sda_hold = 35,
+			}
+		},
+	}"
+
+	device domain 0 on
+		device ref igpu on end
+		device ref dtt on
+			chip drivers/intel/dptf
+				## sensor information
+				register "options.tsr[0].desc" = ""DDR""
+				register "options.tsr[1].desc" = ""charger""
+				register "options.tsr[2].desc" = ""ambient""
+
+				## Active Policy
+				register "policies.active" = "{
+					[0] = {
+						.target = DPTF_CPU,
+						.thresholds = {
+								TEMP_PCT(70, 100),
+								TEMP_PCT(60, 65),
+								TEMP_PCT(42, 60),
+								TEMP_PCT(39, 55),
+								TEMP_PCT(38, 50),
+								TEMP_PCT(35, 43),
+								TEMP_PCT(31, 30),
+						}
+					},
+					[1] = {
+						.target = DPTF_TEMP_SENSOR_0,
+						.thresholds = {
+								TEMP_PCT(60, 100),
+								TEMP_PCT(55, 65),
+								TEMP_PCT(52, 60),
+								TEMP_PCT(50, 55),
+								TEMP_PCT(48, 50),
+								TEMP_PCT(45, 43),
+								TEMP_PCT(41, 30),
+						}
+					}
+				}"
+
+				## Passive Policy
+				register "policies.passive" = "{
+					[0] = DPTF_PASSIVE(CPU,         CPU,           95, 5000),
+					[1] = DPTF_PASSIVE(CPU,         TEMP_SENSOR_0, 70, 5000),
+					[2] = DPTF_PASSIVE(CHARGER,     TEMP_SENSOR_1, 70, 5000),
+					[3] = DPTF_PASSIVE(CPU,         TEMP_SENSOR_2, 70, 5000),
+				}"
+
+				## Critical Policy
+				register "policies.critical" = "{
+					[0] = DPTF_CRITICAL(CPU,               100, SHUTDOWN),
+					[1] = DPTF_CRITICAL(TEMP_SENSOR_0,     95, SHUTDOWN),
+					[2] = DPTF_CRITICAL(TEMP_SENSOR_1,     95, SHUTDOWN),
+					[3] = DPTF_CRITICAL(TEMP_SENSOR_2,     95, SHUTDOWN),
+				}"
+
+				register "controls.power_limits" = "{
+					.pl1 = {
+						.min_power = 5000,
+						.max_power = 6000,
+						.time_window_min = 28 * MSECS_PER_SEC,
+						.time_window_max = 28 * MSECS_PER_SEC,
+						.granularity = 500
+					},
+					.pl2 = {
+						.min_power = 25000,
+						.max_power = 25000,
+						.time_window_min = 32 * MSECS_PER_SEC,
+						.time_window_max = 32 * MSECS_PER_SEC,
+						.granularity = 500
+					}
+				}"
+
+				## Charger Performance Control (Control, mA)
+				register "controls.charger_perf" = "{
+					[0] = { 255, 1700 },
+					[1] = {  24, 1500 },
+					[2] = {  16, 1000 },
+					[3] = {   8,  500 }
+				}"
+
+				## Fan Performance Control (Percent, Speed, Noise, Power)
+				register "controls.fan_perf" = "{
+					[0] = { 100, 6000, 220, 2200, },
+					[1] = {  92, 5500, 180, 1800, },
+					[2] = {  85, 5000, 145, 1450, },
+					[3] = {  70, 4400, 115, 1150, },
+					[4] = {  56, 3900,  90,  900, },
+					[5] = {  45, 3300,  55,  550, },
+					[6] = {  38, 3000,  30,  300, },
+					[7] = {  33, 2900,  15,  150, },
+					[8] = {  10,  800,  10,  100, },
+					[9] = {   0,    0,   0,   50, }
+				}"
+
+				## Fan options
+				register "options.fan.fine_grained_control" = "true"
+				register "options.fan.step_size" = "2"
+
+				device generic 0 on
+					probe THERMAL_SOLUTION THERMAL_SOLUTION_6W
+				end
+			end
+			chip drivers/intel/dptf
+				## sensor information
+				register "options.tsr[0].desc" = ""DDR""
+				register "options.tsr[1].desc" = ""charger""
+				register "options.tsr[2].desc" = ""ambient""
+
+				## Active Policy
+				register "policies.active" = "{
+					[0] = {
+						.target = DPTF_CPU,
+						.thresholds = {
+								TEMP_PCT(70, 100),
+								TEMP_PCT(60, 65),
+								TEMP_PCT(42, 58),
+								TEMP_PCT(39, 53),
+								TEMP_PCT(38, 47),
+								TEMP_PCT(35, 43),
+								TEMP_PCT(31, 30),
+						}
+					},
+					[1] = {
+						.target = DPTF_TEMP_SENSOR_0,
+						.thresholds = {
+								TEMP_PCT(60, 100),
+								TEMP_PCT(55, 65),
+								TEMP_PCT(52, 58),
+								TEMP_PCT(50, 53),
+								TEMP_PCT(48, 47),
+								TEMP_PCT(45, 43),
+								TEMP_PCT(41, 30),
+						}
+					}
+				}"
+
+				## Passive Policy
+				register "policies.passive" = "{
+					[0] = DPTF_PASSIVE(CPU,         CPU,           95, 5000),
+					[1] = DPTF_PASSIVE(CPU,         TEMP_SENSOR_0, 70, 5000),
+					[2] = DPTF_PASSIVE(CHARGER,     TEMP_SENSOR_1, 70, 5000),
+					[3] = DPTF_PASSIVE(CPU,         TEMP_SENSOR_2, 70, 5000),
+				}"
+
+				## Critical Policy
+				register "policies.critical" = "{
+					[0] = DPTF_CRITICAL(CPU,               100, SHUTDOWN),
+					[1] = DPTF_CRITICAL(TEMP_SENSOR_0,     95, SHUTDOWN),
+					[2] = DPTF_CRITICAL(TEMP_SENSOR_1,     95, SHUTDOWN),
+					[3] = DPTF_CRITICAL(TEMP_SENSOR_2,     95, SHUTDOWN),
+				}"
+
+				register "controls.power_limits" = "{
+					.pl1 = {
+						.min_power = 14000,
+						.max_power = 15000,
+						.time_window_min = 28 * MSECS_PER_SEC,
+						.time_window_max = 28 * MSECS_PER_SEC,
+						.granularity = 500
+					},
+					.pl2 = {
+						.min_power = 35000,
+						.max_power = 35000,
+						.time_window_min = 32 * MSECS_PER_SEC,
+						.time_window_max = 32 * MSECS_PER_SEC,
+						.granularity = 500
+					}
+				}"
+
+				## Charger Performance Control (Control, mA)
+				register "controls.charger_perf" = "{
+					[0] = { 255, 1700 },
+					[1] = {  24, 1500 },
+					[2] = {  16, 1000 },
+					[3] = {   8,  500 }
+				}"
+
+				## Fan Performance Control (Percent, Speed, Noise, Power)
+				register "controls.fan_perf" = "{
+					[0] = { 100, 6000, 220, 2200, },
+					[1] = {  92, 5500, 180, 1800, },
+					[2] = {  85, 5000, 145, 1450, },
+					[3] = {  70, 4400, 115, 1150, },
+					[4] = {  56, 3900,  90,  900, },
+					[5] = {  45, 3300,  55,  550, },
+					[6] = {  38, 3000,  30,  300, },
+					[7] = {  33, 2900,  15,  150, },
+					[8] = {  10,  800,  10,  100, },
+					[9] = {   0,    0,   0,   50, }
+				}"
+
+				## Fan options
+				register "options.fan.fine_grained_control" = "true"
+				register "options.fan.step_size" = "2"
+
+				device generic 1 on
+					probe THERMAL_SOLUTION THERMAL_SOLUTION_15W
+				end
+			end
+		end
+		device ref tcss_xhci on
+			chip drivers/usb/acpi
+				device ref tcss_root_hub on
+					chip drivers/usb/acpi
+						register "desc" = ""USB3 Type-C Port C0 (MLB)""
+						register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
+						register "use_custom_pld" = "true"
+						register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(1, 1))"
+						device ref tcss_usb3_port1 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB3 Type-C Port C1 (MLB)""
+						register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
+						register "use_custom_pld" = "true"
+						register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, RIGHT, ACPI_PLD_GROUP(2, 1))"
+						device ref tcss_usb3_port2 on end
+					end
+				end
+			end
+		end
+		device ref xhci on
+			chip drivers/usb/acpi
+				device ref xhci_root_hub on
+					chip drivers/usb/acpi
+						register "desc" = ""USB2 Type-C Port C0 (MLB)""
+						register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
+						register "use_custom_pld" = "true"
+						register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(1, 1))"
+						device ref usb2_port1 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB2 Type-C Port C1 (MLB)""
+						register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
+						register "use_custom_pld" = "true"
+						register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, RIGHT, ACPI_PLD_GROUP(2, 1))"
+						device ref usb2_port2 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB2 Type-A Port A0 (MLB)""
+						register "type" = "UPC_TYPE_A"
+						register "use_custom_pld" = "true"
+						register "custom_pld" = "ACPI_PLD_TYPE_A(LEFT, RIGHT, ACPI_PLD_GROUP(3, 1))"
+						device ref usb2_port3 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB2 Type-A Port A1 (DB)""
+						register "type" = "UPC_TYPE_A"
+						register "use_custom_pld" = "true"
+						register "custom_pld" = "ACPI_PLD_TYPE_A(RIGHT, LEFT, ACPI_PLD_GROUP(4, 1))"
+						device ref usb2_port4 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB2 LTE""
+						register "type" = "UPC_TYPE_INTERNAL"
+						device ref usb2_port5 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB2 Camera""
+						register "type" = "UPC_TYPE_INTERNAL"
+						device ref usb2_port6 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""PCIe Bluetooth""
+						register "type" = "UPC_TYPE_INTERNAL"
+						register "reset_gpio" =	"ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D4)"
+						device ref usb2_port8 on
+							probe WIFI WIFI_PCIE_WIFI7
+							probe WIFI WIFI_UNKNOWN
+						end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""CNVi Bluetooth""
+						register "type" = "UPC_TYPE_INTERNAL"
+						register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D4)"
+						device ref usb2_port10 on
+							probe WIFI WIFI_CNVI_WIFI6E
+							probe WIFI WIFI_UNKNOWN
+						end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB3 Type-A Port A0 (MLB)""
+						register "type" = "UPC_TYPE_USB3_A"
+						register "use_custom_pld" = "true"
+						register "custom_pld" = "ACPI_PLD_TYPE_A(LEFT, RIGHT, ACPI_PLD_GROUP(3, 1))"
+						device ref usb3_port1 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB3 Type-A Port A1 (DB)""
+						register "type" = "UPC_TYPE_USB3_A"
+						register "use_custom_pld" = "true"
+						register "custom_pld" = "ACPI_PLD_TYPE_A(RIGHT, LEFT, ACPI_PLD_GROUP(4, 1))"
+						device ref usb3_port2 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB3 WWAN""
+						register "type" = "UPC_TYPE_INTERNAL"
+						device ref usb3_port3 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB3 WLAN""
+						register "type" = "UPC_TYPE_INTERNAL"
+						device ref usb3_port4 on end
+					end
+				end
+			end
+		end
+		device ref shared_sram on end
+		device ref cnvi_wifi on
+			chip drivers/wifi/generic
+				register "wake" = "GPE0_PME_B0"
+				register "enable_cnvi_ddr_rfim" = "true"
+				register "add_acpi_dma_property" = "true"
+				device generic 0 on end
+			end
+			probe WIFI WIFI_CNVI_WIFI6E
+			probe WIFI WIFI_UNKNOWN
+		end
+		device ref pcie_rp4 on
+			# PCIe 4 WLAN
+			register "pch_pcie_rp[PCH_RP(4)]" = "{
+				.clk_src = 2,
+				.clk_req = 2,
+				.flags = PCIE_RP_LTR | PCIE_RP_AER,
+			}"
+			chip drivers/wifi/generic
+				register "wake" = "GPE0_DW1_03"
+				register "add_acpi_dma_property" = "true"
+				device pci 00.0 on end
+			end
+			chip soc/intel/common/block/pcie/rtd3
+				# # enable_gpio is controlled by the EC with EC_EN_PP3300_WLAN
+				register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E10)"
+				register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_H20)"
+				register "srcclk_pin" = "2"
+				device generic 0 on end
+			end
+			probe WIFI WIFI_PCIE_WIFI7
+			probe WIFI WIFI_UNKNOWN
+		end
+
+		device ref i2c0 on
+			chip drivers/i2c/tpm
+				register "hid" = ""GOOG0005""
+				register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_A13_IRQ)"
+				device i2c 50 on end
+			end
+		end #I2C0
+		device ref i2c5 on
+			chip drivers/i2c/generic
+				register "hid" = ""ELAN0000""
+				register "desc" = ""ELAN Touchpad""
+				register "irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_F14_IRQ)"
+				register "wake" = "GPE0_DW2_14"
+				register "detect" = "1"
+				device i2c 0x15 on end
+			end
+		end
+		device ref heci1 on end
+		device ref ish on
+			chip drivers/intel/ish
+				register "add_acpi_dma_property" = "true"
+				device generic 0 on end
+			end
+		end
+		device ref ufs on end
+		device ref uart0 on end
+		device ref pch_espi on
+			chip ec/google/chromeec
+				device pnp 0c09.0 on end
+			end
+		end
+		device ref pmc hidden end
+		device ref hda on
+			chip drivers/sof
+				register "spkr_tplg" = "max98360a"
+				register "jack_tplg" = "rt5682"
+				register "mic_tplg" = "_2ch_pdm0"
+				device generic 0 on end
+			end
+		end
+	end
+end
diff --git a/src/mainboard/google/brya/variants/pujjocento/variant.c b/src/mainboard/google/brya/variants/pujjocento/variant.c
new file mode 100644
index 0000000000..d202cbd110
--- /dev/null
+++ b/src/mainboard/google/brya/variants/pujjocento/variant.c
@@ -0,0 +1,38 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <baseboard/variants.h>
+#include <chip.h>
+#include <fw_config.h>
+#include <sar.h>
+#include <soc/gpio_soc_defs.h>
+#include <intelblocks/graphics.h>
+#include <acpi/acpi.h>
+#include <acpi/acpigen.h>
+#include <variant/gpio.h>
+
+const char *get_wifi_sar_cbfs_filename(void)
+{
+	return get_wifi_sar_fw_config_filename(FW_CONFIG_FIELD(WIFI));
+}
+
+void variant_update_soc_chip_config(struct soc_intel_alderlake_config *config)
+{
+	if (fw_config_probe(FW_CONFIG(WIFI, WIFI_CNVI_WIFI6E))
+		|| fw_config_probe(FW_CONFIG(WIFI, WIFI_UNKNOWN))) {
+		printk(BIOS_INFO, "CNVi bluetooth enabled by fw_config\n");
+		config->cnvi_bt_core = true;
+		config->cnvi_bt_audio_offload = true;
+	} else {
+		printk(BIOS_INFO, "CNVi bluetooth disabled by fw_config\n");
+		config->cnvi_bt_core = false;
+		config->cnvi_bt_audio_offload = false;
+	}
+}
+
+void variant_generate_s0ix_hook(enum s0ix_entry entry)
+{
+	if (entry == S0IX_ENTRY)
+		acpigen_soc_clear_tx_gpio(SLP_S0_HDMI_EN);
+	else if (entry == S0IX_EXIT)
+		acpigen_soc_set_tx_gpio(SLP_S0_HDMI_EN);
+}

From 7f8d1f208664424871fe1246030ed8b2ce622ff3 Mon Sep 17 00:00:00 2001
From: Qinghong Zeng <zengqinghong@huaqin.corp-partner.google.com>
Date: Thu, 10 Apr 2025 10:47:22 +0800
Subject: [PATCH 0847/3886] mb/google/nissa/var/pujjoniru: Support x32 memory
 configuration

Use GPP_E19 level to determine whether x32 memory configuration is
supported.

BUG=b:409144310
TEST=emerge-nissa coreboot chromeos-bootimage

Change-Id: I7c1f48f89186c3803e8e6a1bf163b824f2f06731
Signed-off-by: Qinghong Zeng <zengqinghong@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87250
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jayvik Desai <jayvik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com>
---
 src/mainboard/google/brya/Kconfig             |  1 +
 .../brya/variants/pujjoniru/Makefile.mk       |  1 +
 .../google/brya/variants/pujjoniru/gpio.c     |  5 +++++
 .../google/brya/variants/pujjoniru/memory.c   | 20 +++++++++++++++++++
 4 files changed, 27 insertions(+)
 create mode 100644 src/mainboard/google/brya/variants/pujjoniru/memory.c

diff --git a/src/mainboard/google/brya/Kconfig b/src/mainboard/google/brya/Kconfig
index 2bc0daaf94..73e908a75c 100644
--- a/src/mainboard/google/brya/Kconfig
+++ b/src/mainboard/google/brya/Kconfig
@@ -498,6 +498,7 @@ config BOARD_GOOGLE_PUJJONIRU
 	select DRIVERS_GENERIC_GPIO_KEYS
 	select DRIVERS_GFX_GENERIC
 	select DRIVERS_AUDIO_SOF
+	select ENFORCE_MEM_CHANNEL_DISABLE
 	select MAINBOARD_HAS_GOOGLE_STRAUSS_KEYBOARD
 	select SOC_INTEL_TWINLAKE
 
diff --git a/src/mainboard/google/brya/variants/pujjoniru/Makefile.mk b/src/mainboard/google/brya/variants/pujjoniru/Makefile.mk
index 4cf7fcace8..102ec17861 100644
--- a/src/mainboard/google/brya/variants/pujjoniru/Makefile.mk
+++ b/src/mainboard/google/brya/variants/pujjoniru/Makefile.mk
@@ -2,6 +2,7 @@
 
 bootblock-y += gpio.c
 
+romstage-y += memory.c
 romstage-y += gpio.c
 
 ramstage-y += gpio.c
diff --git a/src/mainboard/google/brya/variants/pujjoniru/gpio.c b/src/mainboard/google/brya/variants/pujjoniru/gpio.c
index 6845a6e9fd..3fb85ed3b5 100644
--- a/src/mainboard/google/brya/variants/pujjoniru/gpio.c
+++ b/src/mainboard/google/brya/variants/pujjoniru/gpio.c
@@ -140,6 +140,9 @@ static const struct pad_config override_gpio_table[] = {
 	/* C7  : SML1DATA ==> TCHSCR_INT_ODL */
 	PAD_CFG_GPI_APIC(GPP_C7, NONE, PLTRST, LEVEL, INVERT),
 
+	/* E19 : DDP1_CTRLDATA ==> GPP_E19_STRAP */
+	PAD_CFG_GPI_LOCK(GPP_E19, DN_20K, LOCK_CONFIG),
+
 	/* Configure the virtual CNVi Bluetooth I2S GPIO pads */
 	/* BT_I2S_BCLK */
 	PAD_CFG_NF(GPP_VGPIO_30, NONE, DEEP, NF3),
@@ -178,6 +181,8 @@ static const struct pad_config early_gpio_table[] = {
 	PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2),
 	/* H20 : IMGCLKOUT1 ==> WLAN_PERST_L */
 	PAD_CFG_GPO(GPP_H20, 0, DEEP),
+	/* E19 : DDP1_CTRLDATA ==> GPP_E19_STRAP */
+	PAD_CFG_GPI_LOCK(GPP_E19, DN_20K, LOCK_CONFIG),
 };
 
 static const struct pad_config romstage_gpio_table[] = {
diff --git a/src/mainboard/google/brya/variants/pujjoniru/memory.c b/src/mainboard/google/brya/variants/pujjoniru/memory.c
new file mode 100644
index 0000000000..51a7ff504c
--- /dev/null
+++ b/src/mainboard/google/brya/variants/pujjoniru/memory.c
@@ -0,0 +1,20 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <baseboard/gpio.h>
+#include <baseboard/variants.h>
+#include <gpio.h>
+#include <soc/romstage.h>
+
+uint8_t mb_get_channel_disable_mask(void)
+{
+	/*
+	 * GPP_E19 High -> One RAM Chip
+	 * GPP_E19 Low  -> Two RAM Chip
+	 */
+	if (gpio_get(GPP_E19)) {
+		/* Disable all other channels except first two on each controller */
+		return (BIT(2) | BIT(3));
+	}
+
+	return 0;
+}

From ad704e05008acc3ca1ddcd660a9ed505cca406a4 Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Mon, 21 Apr 2025 10:33:26 -0500
Subject: [PATCH 0848/3886] soc/intel/cannonlake: Hook up the VT-d setting to
 option API
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Hook up the VT-d setting to the option API, so it can be changed at
runtime without recompilation.

Change-Id: Iaddaf56563bd5916bc27d99171af48bf46127052
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87399
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
---
 src/soc/intel/cannonlake/romstage/fsp_params.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/soc/intel/cannonlake/romstage/fsp_params.c b/src/soc/intel/cannonlake/romstage/fsp_params.c
index 5083e577ad..74812f31bf 100644
--- a/src/soc/intel/cannonlake/romstage/fsp_params.c
+++ b/src/soc/intel/cannonlake/romstage/fsp_params.c
@@ -125,7 +125,7 @@ void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version)
 	m_cfg->PlatformDebugConsent = CONFIG_SOC_INTEL_COMMON_DEBUG_CONSENT;
 
 	/* Configure VT-d */
-	tconfig->VtdDisable = 0;
+	tconfig->VtdDisable = !get_uint_option("vtd", 1);
 
 	/* Set HECI1 PCI BAR address */
 	m_cfg->Heci1BarAddress = HECI1_BASE_ADDRESS;

From 17347eedc3387afac801df1fefb3982a9b693f3d Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Mon, 21 Apr 2025 10:35:03 -0500
Subject: [PATCH 0849/3886] soc/intel/cannonlake: Add CFR objects for existing
 options

Add a header with CFR objects for existing configuration options,
so that supported boards can make use of them without duplication.

Change-Id: I925002958b5de93e833f06fddf772e5334a7bdb8
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87401
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
---
 src/soc/intel/cannonlake/include/soc/cfr.h | 87 ++++++++++++++++++++++
 1 file changed, 87 insertions(+)
 create mode 100644 src/soc/intel/cannonlake/include/soc/cfr.h

diff --git a/src/soc/intel/cannonlake/include/soc/cfr.h b/src/soc/intel/cannonlake/include/soc/cfr.h
new file mode 100644
index 0000000000..ae61799a68
--- /dev/null
+++ b/src/soc/intel/cannonlake/include/soc/cfr.h
@@ -0,0 +1,87 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+/*
+ * CFR enums and structs which are used to control SoC settings.
+ */
+
+#ifndef CANNONLAKE_CFR_H
+#define CANNONLAKE_CFR_H
+
+#include <drivers/option/cfr_frontend.h>
+
+/* FSP hyperthreading */
+static const struct sm_object hyper_threading = SM_DECLARE_ENUM({
+	.opt_name	= "hyper_threading",
+	.ui_name	= "Hyper-Threading",
+	.ui_helptext	= "Enable or disable Hyper-Threading",
+	.default_value	= CONFIG(FSP_HYPERTHREADING),
+	.values		= (const struct sm_enum_value[]) {
+				{ "Disabled",		0	},
+				{ "Enabled",		1	},
+				SM_ENUM_VALUE_END		},
+});
+
+/* IGD Aperture Size */
+static const struct sm_object igd_aperture = SM_DECLARE_ENUM({
+	.opt_name	= "igd_aperture_size",
+	.ui_name	= "IGD Aperture Size",
+	.ui_helptext	= "Select the Aperture Size",
+	.default_value	= 1,
+	.values		= (const struct sm_enum_value[]) {
+				{ "128 MB",		0	},
+				{ "256 MB",		1	},
+				{ "512 MB",		2	},
+				SM_ENUM_VALUE_END		},
+});
+
+/* IGD DVMT pre-allocated memory */
+static const struct sm_object igd_dvmt = SM_DECLARE_ENUM({
+	.opt_name	= "igd_dvmt_prealloc",
+	.ui_name	= "IGD DVMT Size",
+	.ui_helptext	= "Size of memory preallocated for internal graphics",
+	.default_value	= 2,
+	.values		= (const struct sm_enum_value[]) {
+				{ "32 MB",		1	},
+				{ "64 MB",		2	},
+				{ "96 MB",		3	},
+				{ "128 MB",		4	},
+				SM_ENUM_VALUE_END		},
+});
+
+/* Legacy 8254 Timer */
+static const struct sm_object legacy_8254_timer = SM_DECLARE_ENUM({
+	.opt_name	= "legacy_8254_timer",
+	.ui_name	= "Legacy 8254 Timer",
+	.ui_helptext	= "Enable the legacy 8254 timer by disabling clock gating.",
+	.default_value	= 0,
+	.values		= (const struct sm_enum_value[]) {
+				{ "Disabled",		0	},
+				{ "Enabled",		1	},
+				SM_ENUM_VALUE_END		},
+});
+
+/* S0ix Enable */
+static const struct sm_object s0ix_enable = SM_DECLARE_ENUM({
+	.opt_name	= "s0ix_enable",
+	.ui_name	= "Modern Standby (S0ix)",
+	.ui_helptext	= "Enabled: use Modern Standby / S0ix. Disabled: use APCI S3 sleep",
+	.default_value	= 1,
+	.values		= (const struct sm_enum_value[]) {
+				{ "Disabled",		0	},
+				{ "Enabled",		1	},
+				SM_ENUM_VALUE_END		},
+});
+
+/* VT-d */
+static const struct sm_object vtd = SM_DECLARE_ENUM({
+	.opt_name	= "vtd",
+	.ui_name	= "VT-d",
+	.ui_helptext	= "Enable or disable Intel VT-d (virtualization)",
+	.default_value	= 1,
+	.values		= (const struct sm_enum_value[]) {
+				{ "Disabled",		0	},
+				{ "Enabled",		1	},
+				SM_ENUM_VALUE_END		},
+});
+
+#endif /* CANNONLAKE_CFR_H */

From ce6f7820f419b8ff70b72558047886afc9f77587 Mon Sep 17 00:00:00 2001
From: Pranava Y N <pranavayn@google.com>
Date: Wed, 23 Apr 2025 11:06:52 +0530
Subject: [PATCH 0850/3886] ec/google/chromeec: Increase EC status timeout to
 30 seconds

Some ITE ECs take long time (15-20s) to complete flash erase operation
during EC software sync. Increasing the timeout value to 30s avoids
EC_CMD_FLASH_ERASE command from timing out. As this is just a timeout
value, it should not have any effect on the boot time.

BUGS=b:386920751, b:412210635
TEST= Verify that the EC_CMD_FLASH_ERASE(0x13) is not timing out while
performing EC sync. Below error is avoided,

```
[ERROR]  Timeout waiting for EC process command 19!
[INFO ]  VB2:update_ec() vb2ex_ec_update_image(select) returned 0x10000001
[INFO ]  VB2:vb2api_fail() Need recovery, reason: 0x26 / 0x1
[INFO ]  VB2:sync_ec() update_ec(ctx, select_rw) returned 0x10000001
[INFO ]  VB2:vb2api_fail() Need recovery, reason: 0x26 / 0x1
[INFO ]  VB2:vb2api_ec_sync() ec_sync_phase2(ctx) returned 0x10000001
[INFO ]  Saving nvdata
[ERROR]  EC software sync failed (0x10000001), rebooting
[INFO ]  board_reset() called!
[INFO ]  full_reset() called!
```

Change-Id: Id7bfa620e8c19d5b162b60e5cc37003ff339b589
Signed-off-by: Pranava Y N <pranavayn@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87427
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
---
 src/ec/google/chromeec/ec_lpc.c | 7 +++++--
 1 file changed, 5 insertions(+), 2 deletions(-)

diff --git a/src/ec/google/chromeec/ec_lpc.c b/src/ec/google/chromeec/ec_lpc.c
index b86ba7ba7f..b32d25c6a8 100644
--- a/src/ec/google/chromeec/ec_lpc.c
+++ b/src/ec/google/chromeec/ec_lpc.c
@@ -103,8 +103,11 @@ static inline u8 write_byte(u8 val, u16 port)
 static int google_chromeec_status_check(u16 port, u8 mask, u8 cond)
 {
 	struct stopwatch timeout_sw;
-	/* One second is more than plenty for any EC operation to complete */
-	const uint64_t ec_status_timeout_us = 1 * USECS_PER_SEC;
+	/*
+	 * Wait up to 30s for EC operation to complete.
+	 * Some ECs take 15-20s to complete Flash Erase operation.
+	 */
+	const uint64_t ec_status_timeout_us = 30 * USECS_PER_SEC;
 	/* Wait 1 usec between read attempts  */
 	const uint64_t ec_status_read_period_us = 1;
 

From 96fd20c5e0a5be604ddde6788ad7e40cb827df3d Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Sun, 20 Apr 2025 17:27:19 -0500
Subject: [PATCH 0851/3886] soc/intel/broadwell: Add CFR objects for existing
 options

Add a header with CFR objects for existing configuration options,
so that supported boards can make use of them without duplication.

TEST=build/boot google/guado with CFR options enabled.

Change-Id: Iaf9950a3b446b1b55d836e54e8b231d047571768
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87387
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/soc/intel/broadwell/include/soc/cfr.h | 38 +++++++++++++++++++++++
 1 file changed, 38 insertions(+)
 create mode 100644 src/soc/intel/broadwell/include/soc/cfr.h

diff --git a/src/soc/intel/broadwell/include/soc/cfr.h b/src/soc/intel/broadwell/include/soc/cfr.h
new file mode 100644
index 0000000000..91dc9048c7
--- /dev/null
+++ b/src/soc/intel/broadwell/include/soc/cfr.h
@@ -0,0 +1,38 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+/*
+ * CFR enums and structs for soc/intel/broadwell
+ */
+
+#ifndef _BROADWELL_CFR_H_
+#define _BROADWELL_CFR_H_
+
+#include <drivers/option/cfr_frontend.h>
+#include "pm.h"
+
+/* Power state after power loss */
+static const struct sm_object power_on_after_fail = SM_DECLARE_ENUM({
+	.opt_name	= "power_on_after_fail",
+	.ui_name	= "Restore AC Power Loss",
+	.ui_helptext	= "Specify what to do when power is re-applied after a power loss.",
+	.default_value	= CONFIG_MAINBOARD_POWER_FAILURE_STATE,
+	.values		= (const struct sm_enum_value[]) {
+				{ "Power off (S5)", MAINBOARD_POWER_OFF		},
+				{ "Power on  (S0)", MAINBOARD_POWER_ON		},
+				{ "Previous state", MAINBOARD_POWER_KEEP	},
+				SM_ENUM_VALUE_END				},
+});
+
+/* Intel ME State */
+static const struct sm_object me_disable = SM_DECLARE_ENUM({
+	.opt_name	= "me_disable",
+	.ui_name	= "Intel Management Engine",
+	.ui_helptext	= "Enable or disable the PCI/HECI interface of the Intel Management Engine",
+	.default_value	= 0,
+	.values		= (const struct sm_enum_value[]) {
+				{ "Disabled",	1	},
+				{ "Enabled",	0	},
+				SM_ENUM_VALUE_END	},
+});
+
+#endif /* _BROADWELL_CFR_H_ */

From c2c95fbd241c45a5d3dbdfb72a710909fbae0687 Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Sun, 20 Apr 2025 17:19:38 -0500
Subject: [PATCH 0852/3886] sb/intel/lynxpoint: Add CFR objects for existing
 options

Add a header with CFR objects for existing configuration options,
so that supported boards can make use of them without duplication.

TEST=build/boot google/panther with CFR options enabled.

Change-Id: I5067e7a69f1f53f0f93d337198d3c349facec086
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87385
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
---
 src/southbridge/intel/lynxpoint/cfr.h | 55 +++++++++++++++++++++++++++
 1 file changed, 55 insertions(+)
 create mode 100644 src/southbridge/intel/lynxpoint/cfr.h

diff --git a/src/southbridge/intel/lynxpoint/cfr.h b/src/southbridge/intel/lynxpoint/cfr.h
new file mode 100644
index 0000000000..4d56b5c421
--- /dev/null
+++ b/src/southbridge/intel/lynxpoint/cfr.h
@@ -0,0 +1,55 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+/*
+ * CFR enums and structs for sb/lynxpoint
+ */
+
+#ifndef _LYNXPOINT_CFR_H_
+#define _LYNXPOINT_CFR_H_
+
+#include <drivers/option/cfr_frontend.h>
+#include "pch.h"
+
+/* Power state after power loss */
+static const struct sm_object power_on_after_fail = SM_DECLARE_ENUM({
+	.opt_name	= "power_on_after_fail",
+	.ui_name	= "Restore AC Power Loss",
+	.ui_helptext	= "Specify what to do when power is re-applied after a power loss.",
+	.default_value	= CONFIG_MAINBOARD_POWER_FAILURE_STATE,
+	.values		= (const struct sm_enum_value[]) {
+				{ "Power off (S5)", MAINBOARD_POWER_OFF		},
+				{ "Power on  (S0)", MAINBOARD_POWER_ON		},
+				{ "Previous state", MAINBOARD_POWER_KEEP	},
+				SM_ENUM_VALUE_END				},
+});
+
+/* Intel ME State */
+static const struct sm_object me_disable = SM_DECLARE_ENUM({
+	.opt_name	= "me_disable",
+	.ui_name	= "Intel Management Engine",
+	.ui_helptext	= "Enable or disable the PCI/HECI interface of the Intel Management Engine",
+	.default_value	= 0,
+	.values		= (const struct sm_enum_value[]) {
+				{ "Disabled",	1	},
+				{ "Enabled",	0	},
+				SM_ENUM_VALUE_END	},
+});
+
+enum {
+	NMI_OFF = 0,
+	NMI_ON,
+};
+
+/* Non-maskable interrupts */
+static const struct sm_object nmi = SM_DECLARE_ENUM({
+	.opt_name	= "nmi",
+	.ui_name	= "Non-maskable Interrupts",
+	.ui_helptext	= "Enable or disable non-maskable interrupts",
+	.default_value	= NMI_OFF,
+	.values		= (const struct sm_enum_value[]) {
+				{ "Disabled",	NMI_OFF	},
+				{ "Enabled",	NMI_ON	},
+				SM_ENUM_VALUE_END	},
+});
+
+#endif /* _LYNXPOINT_CFR_H_ */

From 6a503fe5a4f623c27ad13faf6c9e5d5458ebd791 Mon Sep 17 00:00:00 2001
From: Kapil Porwal <kapilporwal@google.com>
Date: Thu, 24 Apr 2025 21:44:23 +0530
Subject: [PATCH 0853/3886] mb/google/var/uldrenite: Configure GPP_A16 as NF4

GPP_A16 was wrongly configured to NF2 instead of NF4 i.e. ISH_GP5.
Reference: Intel doc#648094

BUG=b:410645679
TEST=Check GPIO config in the OS.

Change-Id: Ic91ac116513e27992679b0d301afed3bc057bf71
Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87444
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yuval Peress <peress@google.com>
---
 src/mainboard/google/brya/variants/uldrenite/gpio.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/mainboard/google/brya/variants/uldrenite/gpio.c b/src/mainboard/google/brya/variants/uldrenite/gpio.c
index 3695ad0d23..d9ace37526 100644
--- a/src/mainboard/google/brya/variants/uldrenite/gpio.c
+++ b/src/mainboard/google/brya/variants/uldrenite/gpio.c
@@ -35,7 +35,7 @@ static const struct pad_config gpio_table[] = {
 	/* A15 : USB_OC2# ==> NC */
 	PAD_NC(GPP_A15, NONE),
 	/* A16 : ISH_GP5 */
-	PAD_CFG_NF(GPP_A16, NONE, DEEP, NF2),
+	PAD_CFG_NF(GPP_A16, NONE, DEEP, NF4),
 	/* A17 : GPP_A17 ==> GSC_SOC_INT_ODL */
 	PAD_CFG_GPI_APIC(GPP_A17, NONE, PLTRST, LEVEL, INVERT),
 	/* A18 : DDSP_HPDB ==> NC */

From 2201f574936732aba5020aac942a3dbf59ea2b08 Mon Sep 17 00:00:00 2001
From: Subrata Banik <subratabanik@google.com>
Date: Wed, 2 Apr 2025 08:44:40 +0000
Subject: [PATCH 0854/3886] soc/qualcomm/x1p42100: Add QUP Serial Engine (SE)
 entries

This patch adds QUP-SE entries as applicable for the Qualcomm X1P-42-100
SoC.

This includes:
- Add new entries for QUPV3_2 SEs.
- Update base addresses for all QUP-SEs.
- Base GPIO pin function assignments.
- Definition and GPIO mapping for relevant QUP Serial Engines (SEs).
- GPIO mapping for the QSPI interface.

Additionally, update GPIO PINS for QSPI and UART.

BUG=b:404985109
TEST=Successfully built google/bluey with the Qualcomm x1p42100 SoC.

Change-Id: Ib0535aa5dfadef8c412c5e9dd51859068539821f
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87093
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
---
 .../x1p42100/include/soc/addressmap.h         |  48 ++--
 src/soc/qualcomm/x1p42100/include/soc/clock.h |  27 ++
 src/soc/qualcomm/x1p42100/include/soc/gpio.h  | 247 +++++++++++++++++-
 .../x1p42100/include/soc/qcom_qup_se.h        |  18 +-
 src/soc/qualcomm/x1p42100/include/soc/uart.h  |   2 +-
 src/soc/qualcomm/x1p42100/qcom_qup_se.c       | 122 ++++++++-
 6 files changed, 435 insertions(+), 29 deletions(-)

diff --git a/src/soc/qualcomm/x1p42100/include/soc/addressmap.h b/src/soc/qualcomm/x1p42100/include/soc/addressmap.h
index 5bb39e3bb5..a119d17295 100644
--- a/src/soc/qualcomm/x1p42100/include/soc/addressmap.h
+++ b/src/soc/qualcomm/x1p42100/include/soc/addressmap.h
@@ -5,35 +5,34 @@
 
 #include <stdint.h>
 
-/* TODO: update as per datasheet */
 #define AOSS_CC_BASE			0x0C2A0000
 #define QSPI_BASE			0x088DC000
 #define TLMM_TILE_BASE			0x0F100000
 
 /* X1P42100 QSPI GPIO PINS */
-#define QSPI_CS				GPIO(0)
-#define QSPI_DATA_0			GPIO(0)
-#define QSPI_DATA_1			GPIO(0)
-#define QSPI_CLK			GPIO(0)
+#define QSPI_CS				GPIO(132)
+#define QSPI_DATA_0			GPIO(128)
+#define QSPI_DATA_1			GPIO(129)
+#define QSPI_CLK			GPIO(127)
 
-#define GPIO_FUNC_QSPI_DATA_0		0
-#define GPIO_FUNC_QSPI_DATA_1		0
-#define GPIO_FUNC_QSPI_CLK		0
+#define GPIO_FUNC_QSPI_DATA_0		GPIO128_FUNC_QSPI0_DATA_0
+#define GPIO_FUNC_QSPI_DATA_1		GPIO129_FUNC_QSPI0_DATA_1
+#define GPIO_FUNC_QSPI_CLK		GPIO127_FUNC_QSPI0_CLK
 
 /*
  * QUP SERIAL ENGINE BASE ADDRESSES
  */
 /* QUPV3_0 */
-#define QUP_SERIAL0_BASE		0x00980000
-#define QUP_SERIAL1_BASE		0x00984000
-#define QUP_SERIAL2_BASE		0x00988000
-#define QUP_SERIAL3_BASE		0x0098C000
-#define QUP_SERIAL4_BASE		0x00990000
-#define QUP_SERIAL5_BASE		0x00994000
-#define QUP_SERIAL6_BASE		0x00998000
-#define QUP_SERIAL7_BASE		0x0099C000
-#define QUP_WRAP0_BASE			0x009C0000
-#define QUP_0_GSI_BASE			0x00904000
+#define QUP_SERIAL0_BASE		0x00B80000
+#define QUP_SERIAL1_BASE		0x00B84000
+#define QUP_SERIAL2_BASE		0x00B88000
+#define QUP_SERIAL3_BASE		0x00B8C000
+#define QUP_SERIAL4_BASE		0x00B90000
+#define QUP_SERIAL5_BASE		0x00B94000
+#define QUP_SERIAL6_BASE		0x00B98000
+#define QUP_SERIAL7_BASE		0x00B9C000
+#define QUP_WRAP0_BASE			0x00BC0000
+#define QUP_0_GSI_BASE			0x00B04000
 
 /* QUPV3_1 */
 #define QUP_SERIAL8_BASE		0x00A80000
@@ -47,7 +46,16 @@
 #define QUP_WRAP1_BASE			0x00AC0000
 #define QUP_1_GSI_BASE			0x00A04000
 
-/* QUPV3_2 - Dummy Entry */
-#define QUP_WRAP2_BASE			0x00000000
+/* QUPV3_2 */
+#define QUP_SERIAL16_BASE		0x00880000
+#define QUP_SERIAL17_BASE		0x00884000
+#define QUP_SERIAL18_BASE		0x00888000
+#define QUP_SERIAL19_BASE		0x0088C000
+#define QUP_SERIAL20_BASE		0x00890000
+#define QUP_SERIAL21_BASE		0x00894000
+#define QUP_SERIAL22_BASE		0x00898000
+#define QUP_SERIAL23_BASE		0x0089C000
+#define QUP_WRAP2_BASE			0x008C0000
+#define QUP_2_GSI_BASE			0x00804000
 
 #endif /*  __SOC_QUALCOMM_X1P42100_ADDRESS_MAP_H__ */
diff --git a/src/soc/qualcomm/x1p42100/include/soc/clock.h b/src/soc/qualcomm/x1p42100/include/soc/clock.h
index 97d418fdbb..c6b01f8f91 100644
--- a/src/soc/qualcomm/x1p42100/include/soc/clock.h
+++ b/src/soc/qualcomm/x1p42100/include/soc/clock.h
@@ -9,6 +9,33 @@
 
 #define SRC_XO_HZ		(38400 * KHz)
 
+enum clk_qup {
+	QUP_WRAP0_S0,
+	QUP_WRAP0_S1,
+	QUP_WRAP0_S2,
+	QUP_WRAP0_S3,
+	QUP_WRAP0_S4,
+	QUP_WRAP0_S5,
+	QUP_WRAP0_S6,
+	QUP_WRAP0_S7,
+	QUP_WRAP1_S0,
+	QUP_WRAP1_S1,
+	QUP_WRAP1_S2,
+	QUP_WRAP1_S3,
+	QUP_WRAP1_S4,
+	QUP_WRAP1_S5,
+	QUP_WRAP1_S6,
+	QUP_WRAP1_S7,
+	QUP_WRAP2_S0,
+	QUP_WRAP2_S1,
+	QUP_WRAP2_S2,
+	QUP_WRAP2_S3,
+	QUP_WRAP2_S4,
+	QUP_WRAP2_S5,
+	QUP_WRAP2_S6,
+	QUP_WRAP2_S7,
+};
+
 /* TODO: update as per datasheet */
 void clock_configure_qspi(uint32_t hz);
 void clock_enable_qup(int qup);
diff --git a/src/soc/qualcomm/x1p42100/include/soc/gpio.h b/src/soc/qualcomm/x1p42100/include/soc/gpio.h
index 1c30f7881f..d9eaab83a1 100644
--- a/src/soc/qualcomm/x1p42100/include/soc/gpio.h
+++ b/src/soc/qualcomm/x1p42100/include/soc/gpio.h
@@ -7,16 +7,255 @@
 #include <soc/addressmap.h>
 #include <soc/gpio_common.h>
 
-#define PIN(index, func1, func2, func3, func4) \
+#define PIN(index, func1, func2, func3, func4, func5, func6) \
 GPIO##index##_ADDR = TLMM_TILE_BASE + (index * TLMM_GPIO_OFF_DELTA), \
 GPIO##index##_FUNC_##func1 = 1, \
 GPIO##index##_FUNC_##func2 = 2, \
 GPIO##index##_FUNC_##func3 = 3, \
-GPIO##index##_FUNC_##func4 = 4
+GPIO##index##_FUNC_##func4 = 4, \
+GPIO##index##_FUNC_##func5 = 5, \
+GPIO##index##_FUNC_##func6 = 6
 
-/* TODO: update as per datasheet */
 enum {
-	PIN(0, QUP0_L0, RES_2, RES_3, RES_4),
+	PIN(0, QUP0_SE0_L0, IBI_I3C_QUP0_SE0_SDA, RES_3, RES_4, RES_5, RES_6),
+	PIN(1, QUP0_SE0_L1, IBI_I3C_QUP0_SE0_SCL, RES_3, RES_4, RES_5, RES_6),
+	PIN(2, QUP0_SE0_L2, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(3, QUP0_SE0_L3, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(4, QUP0_SE1_L0, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(5, QUP0_SE1_L1, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(6, QUP0_SE1_L2, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(7, QUP0_SE1_L3, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(8, QUP0_SE2_L0, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(9, QUP0_SE2_L1, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(10, QUP0_SE2_L2, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(11, QUP0_SE2_L3, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(12, QUP0_SE3_L0, QUP0_SE7_L2, RES_3, RES_4, RES_5, RES_6),
+	PIN(13, QUP0_SE3_L1, QUP0_SE7_L3, RES_3, RES_4, RES_5, RES_6),
+	PIN(14, QUP0_SE3_L2, QUP0_SE7_L0, RES_3, RES_4, RES_5, RES_6),
+	PIN(15, QUP0_SE3_L3, QUP0_SE7_L1, RES_3, RES_4, RES_5, RES_6),
+	PIN(16, QUP0_SE4_L0, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(17, QUP0_SE4_L1, QUP0_SE2_L4, RES_3, RES_4, RES_5, RES_6),
+	PIN(18, QUP0_SE4_L2, QUP0_SE2_L5, RES_3, RES_4, QDSS_CTI_TRIG0_OUT_MIRB, RES_6),
+	PIN(19, QUP0_SE4_L3, QUP0_SE2_L6, RES_3, RES_4, QDSS_CTI_TRIG1_OUT_MIRB, RES_6),
+	PIN(20, QUP0_SE5_L0, GP_PDM_MIRB_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(21, QUP0_SE5_L1, QUP0_SE3_L6, GP_PDM_MIRB_1, RES_4, RES_5, RES_6),
+	PIN(22, QUP0_SE5_L2, QUP0_SE3_L5, GP_PDM_MIRB_0, RES_4, RES_5, RES_6),
+	PIN(23, QUP0_SE5_L3, QUP0_SE3_L4, RES_3, RES_4, QDSS_CTI_TRIG0_IN_MIRA, RES_6),
+	PIN(24, QUP0_SE6_L0, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(25, QUP0_SE6_L1, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(26, QUP0_SE6_L2, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(27, QUP0_SE6_L3, RES_2, RES_3, QDSS_CTI_TRIG1_IN_MIRA, RES_5, RES_6),
+	PIN(28, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(29, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(30, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(31, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(32, QUP1_SE0_L0, IBI_I3C_QUP1_SE0_SDA, RES_3, RES_4, RES_5, RES_6),
+	PIN(33, QUP1_SE0_L1, IBI_I3C_QUP1_SE0_SCL, QUP1_SE3_L6, RES_4, RES_5, RES_6),
+	PIN(34, QUP1_SE0_L2, QUP1_SE3_L5, TSENSE_PWM1_OUT_MIRNAT, TSENSE_PWM2_OUT_MIRNAT,
+		 TSENSE_PWM3_OUT_MIRNAT, TSENSE_PWM4_OUT_MIRNAT),
+	PIN(35, QUP1_SE0_L3, QUP1_SE3_L4, PLL_CLK_AUX, RES_4, RES_5, RES_6),
+	PIN(36, QUP1_SE1_L0, IBI_I3C_QUP1_SE1_SDA, RES_3, RES_4, RES_5, RES_6),
+	PIN(37, QUP1_SE1_L1, IBI_I3C_QUP1_SE1_SCL, RES_3, RES_4, RES_5, RES_6),
+	PIN(38, QUP1_SE1_L2, VSENSE_TRIGGER_MIRNAT, RES_3, RES_4, RES_5, RES_6),
+	PIN(39, QUP1_SE1_L3, SYS_THROTTLE_MIRA, RES_3, RES_4, RES_5, RES_6),
+	PIN(40, QUP1_SE2_L0, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(41, QUP1_SE2_L1, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(42, QUP1_SE2_L2, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(43, QUP1_SE2_L3, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(44, QUP1_SE3_L0, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(45, QUP1_SE3_L1, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(46, QUP1_SE3_L2, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(47, QUP1_SE3_L3, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(48, QUP1_SE4_L0, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(49, QUP1_SE4_L1, QUP1_SE2_L4, RES_3, RES_4, RES_5, RES_6),
+	PIN(50, QUP1_SE4_L2, QUP1_SE2_L5, RES_3, RES_4, RES_5, RES_6),
+	PIN(51, QUP1_SE4_L3, QUP1_SE2_L6, RES_3, RES_4, RES_5, RES_6),
+	PIN(52, QUP1_SE5_L0, QUP1_SE7_L2, RES_3, RES_4, RES_5, RES_6),
+	PIN(53, QUP1_SE5_L1, QUP1_SE7_L3, GP_MN, RES_4, RES_5, RES_6),
+	PIN(54, QUP1_SE5_L2, QUP1_SE7_L0, RES_3, RES_4, RES_5, RES_6),
+	PIN(55, QUP1_SE5_L3, QUP1_SE7_L1, RES_3, RES_4, RES_5, RES_6),
+	PIN(56, QUP1_SE6_L0, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(57, QUP1_SE6_L1, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(58, QUP1_SE6_L2, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(59, QUP1_SE6_L3, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(60, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(61, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(62, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(63, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(64, QUP2_SE0_L0, GCC_GP2_CLK_MIRB, RES_3, RES_4, RES_5, RES_6),
+	PIN(65, QUP2_SE0_L1, QUP2_SE3_L6, TGU_CH1_TRIGOUT, RES_4, RES_5, RES_6),
+	PIN(66, QUP2_SE0_L2, QUP2_SE3_L5, TGU_CH2_TRIGOUT, RES_4, RES_5, RES_6),
+	PIN(67, QUP2_SE0_L3, QUP2_SE3_L4, TGU_CH3_TRIGOUT, RES_4, RES_5, RES_6),
+	PIN(68, QUP2_SE1_L0, IBI_I3C_QUP2_SE1_SDA, TGU_CH4_TRIGOUT, RES_4, RES_5, RES_6),
+	PIN(69, QUP2_SE1_L1, IBI_I3C_QUP2_SE1_SCL, TGU_CH5_TRIGOUT, RES_4, RES_5, RES_6),
+	PIN(70, QUP2_SE1_L2, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(71, QUP2_SE1_L3, GCC_GP1_CLK_MIRB, RES_3, RES_4, RES_5, RES_6),
+	PIN(72, QUP2_SE2_L0, GCC_GP1_CLK_MIRA, RES_3, RES_4, RES_5, RES_6),
+	PIN(73, QUP2_SE2_L1, GCC_GP2_CLK_MIRA, RES_3, RES_4, RES_5, RES_6),
+	PIN(74, QUP2_SE2_L2, GCC_GP3_CLK_MIRA, RES_3, RES_4, RES_5, RES_6),
+	PIN(75, QUP2_SE2_L3, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(76, QUP2_SE3_L0, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(77, QUP2_SE3_L1, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(78, QUP2_SE3_L2, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(79, QUP2_SE3_L3, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(80, QUP2_SE4_L0, TGU_CH7_TRIGOUT, RES_3, RES_4, RES_5, RES_6),
+	PIN(81, QUP2_SE4_L1, QUP2_SE2_L4, TGU_CH0_TRIGOUT, RES_4, RES_5, RES_6),
+	PIN(82, QUP2_SE4_L2, QUP2_SE2_L5, GCC_GP3_CLK_MIRB, RES_4, RES_5, RES_6),
+	PIN(83, QUP2_SE4_L3, QUP2_SE2_L6, TGU_CH6_TRIGOUT, RES_4, RES_5, RES_6),
+	PIN(84, QUP2_SE5_L0, QUP2_SE7_L2, RES_3, RES_4, RES_5, RES_6),
+	PIN(85, QUP2_SE5_L1, QUP2_SE7_L3, RES_3, RES_4, RES_5, RES_6),
+	PIN(86, QUP2_SE5_L2, QUP2_SE7_L0, RES_3, RES_4, RES_5, RES_6),
+	PIN(87, QUP2_SE5_L3, QUP2_SE7_L1, RES_3, RES_4, RES_5, RES_6),
+	PIN(88, QUP2_SE6_L0, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(89, QUP2_SE6_L1, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(90, QUP2_SE6_L2, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(91, QUP2_SE6_L3, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(92, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(93, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(94, SYS_THROTTLE_MIRB, RES_2, MDP_VSYNC_P, RES_4, RES_5, RES_6),
+	PIN(95, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(96, CAM_MCLK0, QDSS_GPIO_TRACEDATA_LOCA_0, RES_3, RES_4, RES_5, RES_6),
+	PIN(97, CAM_MCLK1, QDSS_GPIO_TRACEDATA_LOCA_1, RES_3, RES_4, RES_5, RES_6),
+	PIN(98, CAM_MCLK2, QDSS_GPIO_TRACEDATA_LOCA_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(99, RES_1, QDSS_GPIO_TRACEDATA_LOCA_3, RES_3, RES_4, RES_5, RES_6),
+	PIN(100, CAM_AON_MCLK4, QDSS_GPIO_TRACEDATA_LOCA_4, RES_3, RES_4, RES_5, RES_6),
+	PIN(101, CCI_I2C_SDA0, QDSS_GPIO_TRACEDATA_LOCA_5, RES_3, RES_4, RES_5, RES_6),
+	PIN(102, CCI_I2C_SCL0, QDSS_GPIO_TRACEDATA_LOCA_6, RES_3, RES_4, RES_5, RES_6),
+	PIN(103, CCI_I2C_SDA1, QDSS_GPIO_TRACEDATA_LOCA_7, RES_3, RES_4, RES_5, RES_6),
+	PIN(104, CCI_I2C_SCL1, QDSS_GPIO_TRACECTL_LOCA, RES_3, RES_4, RES_5, RES_6),
+	PIN(105, CCI_I2C_SDA2, QDSS_GPIO_TRACECLK_LOCA, RES_3, RES_4, RES_5, RES_6),
+	PIN(106, CCI_I2C_SCL2, QDSS_GPIO_TRACEDATA_LOCA_8, RES_3, RES_4, RES_5, RES_6),
+	PIN(107, QDSS_GPIO_TRACEDATA_LOCA_9, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(108, QDSS_GPIO_TRACEDATA_LOCA_10, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(109, CCI_TIMER0, MDP_VSYNC4_OUT, QDSS_GPIO_TRACEDATA_LOCA_11, RES_4, RES_5, RES_6),
+	PIN(110, CCI_TIMER1, MDP_VSYNC5_OUT, QDSS_GPIO_TRACEDATA_LOCA_12, RES_4, RES_5, RES_6),
+	PIN(111, CCI_TIMER2, CCI_ASYNC_IN2, MDP_VSYNC6_OUT, QDSS_GPIO_TRACEDATA_LOCA_13, RES_5, RES_6),
+	PIN(112, CCI_TIMER3, CCI_ASYNC_IN1, MDP_VSYNC7_OUT, QDSS_GPIO_TRACEDATA_LOCA_14, RES_5, RES_6),
+	PIN(113, CCI_TIMER4, CCI_ASYNC_IN0, MDP_VSYNC8_OUT, QDSS_GPIO_TRACEDATA_LOCA_15, RES_5, RES_6),
+	PIN(114, RES_2, MDP_VSYNC0_OUT, MDP_VSYNC1_OUT, RES_4, RES_5, RES_6),
+	PIN(115, RES_2, MDP_VSYNC3_OUT, MDP_VSYNC2_OUT, RES_4, RES_5, RES_6),
+	PIN(116, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(117, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(118, HOST2WLAN_SOL, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(119, EDP0_HOT_PLUG_DETECT, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(120, EDP1_HOT_PLUG_DETECT, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(121, USB0_PHY_PS, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(122, USB0_DP_HOT_PLUG_DETECT, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(123, USB1_PHY_PS, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(124, USB1_DP_HOT_PLUG_DETECT, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(125, USB2_PHY_PS, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(126, USB2_DP_HOT_PLUG_DETECT, GP_PDM_MIRA_0, RES_3, RES_4, RES_5, RES_6),
+	PIN(127, QSPI0_CLK, RES_2, GP_PDM_MIRA_1, RES_4, RES_5, RES_6),
+	PIN(128, QSPI0_DATA_0, RES_2, GP_PDM_MIRA_2, RES_4, RES_5, RES_6),
+	PIN(129, QSPI0_DATA_1, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(130, QSPI0_DATA_2, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(131, QSPI0_DATA_3, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(132, QSPI0_CS0_N, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(133, QSPI0_CS1_N, RES_2, TB_TRIG_SDC1, RES_4, RES_5, RES_6),
+	PIN(134, AUDIO_EXT_MCLK0, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(135, I2S0_SCK, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(136, I2S0_DATA0, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(137, I2S0_DATA1, TB_TRIG_SDC2, RES_3, RES_4, RES_5, RES_6),
+	PIN(138, I2S0_WS, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(139, I2S1_SCK, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(140, I2S1_DATA0, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(141, I2S1_WS, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(142, I2S1_DATA1, AUDIO_EXT_MCLK1, AUDIO_REF_CLK, RES_4, RES_5, RES_6),
+	PIN(143, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(144, PCIE3_CLK_REQ_N, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(145, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(146, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(147, PCIE4_CLK_REQ_N, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(148, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(149, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(150, PCIE5_CLK_REQ_N, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(151, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(152, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(153, PCIE6_CLK_REQ_N, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(154, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(155, MDP_VSYNC_S, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(156, RES_2, MDP_VSYNC_E, RES_3, RES_4, RES_5, RES_6),
+	PIN(157, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(158, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(159, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(160, RESOUT_GPIO_N, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(161, QDSS_CTI_TRIG0_OUT_MIRA, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(162, SD_WRITE_PROTECT, QDSS_CTI_TRIG1_OUT_MIRA, RES_3, RES_4, RES_5, RES_6),
+	PIN(163, USB0_SBRX, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(164, USB0_SBTX, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(165, USB0_SBTX_DIR_OUT, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(166, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(167, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(168, EUSB0_AC_EN, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(169, EUSB3_AC_EN, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(170, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(171, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(172, USB1_SBRX, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(173, USB1_SBTX, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(174, USB1_SBTX_DIR_OUT, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(175, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(176, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(177, EUSB1_AC_EN, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(178, EUSB6_AC_EN, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(179, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(180, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(181, USB2_SBRX, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(182, USB2_SBTX, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(183, USB2_SBTX_DIR_OUT, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(184, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(185, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(186, EUSB2_AC_EN, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(187, EUSB5_AC_EN, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(188, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(189, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(190, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(191, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(192, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(193, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(194, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(195, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(196, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(197, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(198, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(199, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(200, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(201, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(202, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(203, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(204, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(205, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(206, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(207, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(208, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(209, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(210, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(211, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(212, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(213, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(214, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(215, RES_2, QDSS_CTI_TRIG1_IN_MIRB, RES_3, RES_4, RES_5, RES_6),
+	PIN(216, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(217, RES_2, QDSS_CTI_TRIG0_IN_MIRB, RES_3, RES_4, RES_5, RES_6),
+	PIN(218, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(219, RES_1, QDSS_GPIO_TRACEDATA_LOCB_0, RES_3, RES_4, RES_5, RES_6),
+	PIN(220, RES_1, QDSS_GPIO_TRACEDATA_LOCB_1, RES_3, RES_4, RES_5, RES_6),
+	PIN(221, RES_1, QDSS_GPIO_TRACEDATA_LOCB_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(222, RES_1, QDSS_GPIO_TRACEDATA_LOCB_3, RES_3, RES_4, RES_5, RES_6),
+	PIN(223, RES_1, QDSS_GPIO_TRACEDATA_LOCB_4, RES_3, RES_4, RES_5, RES_6),
+	PIN(224, RES_1, QDSS_GPIO_TRACEDATA_LOCB_5, RES_3, RES_4, RES_5, RES_6),
+	PIN(225, RES_1, QDSS_GPIO_TRACEDATA_LOCB_6, RES_3, RES_4, RES_5, RES_6),
+	PIN(226, RES_1, QDSS_GPIO_TRACEDATA_LOCB_7, RES_3, RES_4, RES_5, RES_6),
+	PIN(227, RES_1, QDSS_GPIO_TRACECLK_LOCB, RES_3, RES_4, RES_5, RES_6),
+	PIN(228, RES_1, QDSS_GPIO_TRACECTL_LOCB, RES_3, RES_4, RES_5, RES_6),
+	PIN(229, QDSS_GPIO_TRACEDATA_LOCB_8, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(230, QDSS_GPIO_TRACEDATA_LOCB_9, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(231, QDSS_GPIO_TRACEDATA_LOCB_10, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(232, QDSS_GPIO_TRACEDATA_LOCB_11, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(233, QDSS_GPIO_TRACEDATA_LOCB_12, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(234, QDSS_GPIO_TRACEDATA_LOCB_13, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(235, AON_CCI_I2C_SDA3, QDSS_GPIO_TRACEDATA_LOCB_14, RES_3, RES_4, RES_5, RES_6),
+	PIN(236, AON_CCI_I2C_SCL3, QDSS_GPIO_TRACEDATA_LOCB_15, RES_3, RES_4, RES_5, RES_6),
+	PIN(237, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6),
 };
 
 #endif /* _SOC_QUALCOMM_X1P42100_GPIO_H_ */
diff --git a/src/soc/qualcomm/x1p42100/include/soc/qcom_qup_se.h b/src/soc/qualcomm/x1p42100/include/soc/qcom_qup_se.h
index f12616a51f..a8f48c549c 100644
--- a/src/soc/qualcomm/x1p42100/include/soc/qcom_qup_se.h
+++ b/src/soc/qualcomm/x1p42100/include/soc/qcom_qup_se.h
@@ -10,7 +10,6 @@
 #include <timer.h>
 #include <types.h>
 
-/* TODO: update qup_se entries as per datasheet */
 enum qup_se {
 	QUPV3_0_SE0,
 	QUPV3_0_SE1,
@@ -20,7 +19,22 @@ enum qup_se {
 	QUPV3_0_SE5,
 	QUPV3_0_SE6,
 	QUPV3_0_SE7,
-	QUPV3_0_SE8,
+	QUPV3_1_SE0,
+	QUPV3_1_SE1,
+	QUPV3_1_SE2,
+	QUPV3_1_SE3,
+	QUPV3_1_SE4,
+	QUPV3_1_SE5,
+	QUPV3_1_SE6,
+	QUPV3_1_SE7,
+	QUPV3_2_SE0,
+	QUPV3_2_SE1,
+	QUPV3_2_SE2,
+	QUPV3_2_SE3,
+	QUPV3_2_SE4,
+	QUPV3_2_SE5,
+	QUPV3_2_SE6,
+	QUPV3_2_SE7,
 	QUPV3_SE_MAX,
 };
 
diff --git a/src/soc/qualcomm/x1p42100/include/soc/uart.h b/src/soc/qualcomm/x1p42100/include/soc/uart.h
index 179deb3021..4b03831942 100644
--- a/src/soc/qualcomm/x1p42100/include/soc/uart.h
+++ b/src/soc/qualcomm/x1p42100/include/soc/uart.h
@@ -3,6 +3,6 @@
 #ifndef _SOC_QUALCOMM_X1P42100_UART_TX_H_
 #define _SOC_QUALCOMM_X1P42100_UART_TX_H_
 
-#define UART_TX_PIN GPIO(0)
+#define UART_TX_PIN GPIO(86)
 
 #endif /* _SOC_QUALCOMM_X1P42100_UART_TX_H_ */
diff --git a/src/soc/qualcomm/x1p42100/qcom_qup_se.c b/src/soc/qualcomm/x1p42100/qcom_qup_se.c
index 8b2284d4b1..a3217d4a63 100644
--- a/src/soc/qualcomm/x1p42100/qcom_qup_se.c
+++ b/src/soc/qualcomm/x1p42100/qcom_qup_se.c
@@ -2,7 +2,125 @@
 
 #include <soc/qcom_qup_se.h>
 
-/* TODO: update qup entries as per datasheet */
 struct qup qup[QUPV3_SE_MAX] = {
-
+	[QUPV3_0_SE0] = { .regs = (void *)QUP_SERIAL0_BASE,
+		.pin = { GPIO(0), GPIO(1), GPIO(2), GPIO(3) },
+		.func = { GPIO0_FUNC_QUP0_SE0_L0, GPIO1_FUNC_QUP0_SE0_L1,
+			GPIO2_FUNC_QUP0_SE0_L2, GPIO3_FUNC_QUP0_SE0_L3 }
+		},
+	[QUPV3_0_SE1] = { .regs = (void *)QUP_SERIAL1_BASE,
+		.pin = { GPIO(4), GPIO(5), GPIO(6), GPIO(7) },
+		.func = { GPIO4_FUNC_QUP0_SE1_L0, GPIO5_FUNC_QUP0_SE1_L1,
+			GPIO6_FUNC_QUP0_SE1_L2, GPIO7_FUNC_QUP0_SE1_L3 }
+		},
+	[QUPV3_0_SE2] = { .regs = (void *)QUP_SERIAL2_BASE,
+		.pin = { GPIO(8), GPIO(9), GPIO(10), GPIO(11) },
+		.func = { GPIO8_FUNC_QUP0_SE2_L0, GPIO9_FUNC_QUP0_SE2_L1,
+			GPIO10_FUNC_QUP0_SE2_L2, GPIO11_FUNC_QUP0_SE2_L3 }
+		},
+	[QUPV3_0_SE3] = { .regs = (void *)QUP_SERIAL3_BASE,
+		.pin = { GPIO(12), GPIO(13), GPIO(14), GPIO(15) },
+		.func = { GPIO12_FUNC_QUP0_SE3_L0, GPIO13_FUNC_QUP0_SE3_L1,
+			GPIO14_FUNC_QUP0_SE3_L2, GPIO15_FUNC_QUP0_SE3_L3 }
+		},
+	[QUPV3_0_SE4] = { .regs = (void *)QUP_SERIAL4_BASE,
+		.pin = { GPIO(16), GPIO(17), GPIO(18), GPIO(19) },
+		.func = { GPIO16_FUNC_QUP0_SE4_L0, GPIO17_FUNC_QUP0_SE4_L1,
+			GPIO18_FUNC_QUP0_SE4_L2, GPIO19_FUNC_QUP0_SE4_L3 }
+		},
+	[QUPV3_0_SE5] = { .regs = (void *)QUP_SERIAL5_BASE,
+		.pin = { GPIO(20), GPIO(21), GPIO(22), GPIO(23) },
+		.func = { GPIO20_FUNC_QUP0_SE5_L0, GPIO21_FUNC_QUP0_SE5_L1,
+			GPIO22_FUNC_QUP0_SE5_L2, GPIO23_FUNC_QUP0_SE5_L3 }
+		},
+	[QUPV3_0_SE6] = { .regs = (void *)QUP_SERIAL6_BASE,
+		.pin = { GPIO(24), GPIO(25), GPIO(26), GPIO(27) },
+		.func = { GPIO24_FUNC_QUP0_SE6_L0, GPIO25_FUNC_QUP0_SE6_L1,
+			GPIO26_FUNC_QUP0_SE6_L2, GPIO27_FUNC_QUP0_SE6_L3 }
+		},
+	[QUPV3_0_SE7] = { .regs = (void *)QUP_SERIAL7_BASE,
+		.pin = { GPIO(14), GPIO(15), GPIO(12), GPIO(13) },
+		.func = { GPIO14_FUNC_QUP0_SE7_L0, GPIO15_FUNC_QUP0_SE7_L1,
+			GPIO12_FUNC_QUP0_SE7_L2, GPIO13_FUNC_QUP0_SE7_L3 }
+		},
+	[QUPV3_1_SE0] = { .regs = (void *)QUP_SERIAL8_BASE,
+		.pin = { GPIO(32), GPIO(33), GPIO(34), GPIO(35) },
+		.func = { GPIO32_FUNC_QUP1_SE0_L0, GPIO33_FUNC_QUP1_SE0_L1,
+			GPIO34_FUNC_QUP1_SE0_L2, GPIO35_FUNC_QUP1_SE0_L3 }
+		},
+	[QUPV3_1_SE1] = { .regs = (void *)QUP_SERIAL9_BASE,
+		.pin = { GPIO(36), GPIO(37), GPIO(38), GPIO(39) },
+		.func = { GPIO36_FUNC_QUP1_SE1_L0, GPIO37_FUNC_QUP1_SE1_L1,
+			GPIO38_FUNC_QUP1_SE1_L2, GPIO39_FUNC_QUP1_SE1_L3 }
+		},
+	[QUPV3_1_SE2] = { .regs = (void *)QUP_SERIAL10_BASE,
+		.pin = { GPIO(40), GPIO(41), GPIO(42), GPIO(43) },
+		.func = { GPIO40_FUNC_QUP1_SE2_L0, GPIO41_FUNC_QUP1_SE2_L1,
+			GPIO42_FUNC_QUP1_SE2_L2, GPIO43_FUNC_QUP1_SE2_L3 }
+		},
+	[QUPV3_1_SE3] = { .regs = (void *)QUP_SERIAL11_BASE,
+		.pin = { GPIO(44), GPIO(45), GPIO(46), GPIO(47) },
+		.func = { GPIO44_FUNC_QUP1_SE3_L0, GPIO45_FUNC_QUP1_SE3_L1,
+			GPIO46_FUNC_QUP1_SE3_L2, GPIO47_FUNC_QUP1_SE3_L3 }
+		},
+	[QUPV3_1_SE4] = { .regs = (void *)QUP_SERIAL12_BASE,
+		.pin = { GPIO(48), GPIO(49), GPIO(50), GPIO(51) },
+		.func = { GPIO48_FUNC_QUP1_SE4_L0, GPIO49_FUNC_QUP1_SE4_L1,
+			GPIO50_FUNC_QUP1_SE4_L2, GPIO51_FUNC_QUP1_SE4_L3 }
+		},
+	[QUPV3_1_SE5] = { .regs = (void *)QUP_SERIAL13_BASE,
+		.pin = { GPIO(52), GPIO(53), GPIO(54), GPIO(55) },
+		.func = { GPIO52_FUNC_QUP1_SE5_L0, GPIO53_FUNC_QUP1_SE5_L1,
+			GPIO54_FUNC_QUP1_SE5_L2, GPIO55_FUNC_QUP1_SE5_L3 }
+		},
+	[QUPV3_1_SE6] = { .regs = (void *)QUP_SERIAL14_BASE,
+		.pin = { GPIO(56), GPIO(57), GPIO(58), GPIO(59) },
+		.func = { GPIO56_FUNC_QUP1_SE6_L0, GPIO57_FUNC_QUP1_SE6_L1,
+			GPIO58_FUNC_QUP1_SE6_L2, GPIO59_FUNC_QUP1_SE6_L3 }
+		},
+	[QUPV3_1_SE7] = { .regs = (void *)QUP_SERIAL15_BASE,
+		.pin = { GPIO(54), GPIO(55), GPIO(52), GPIO(53) },
+		.func = { GPIO54_FUNC_QUP1_SE7_L0, GPIO55_FUNC_QUP1_SE7_L1,
+			GPIO52_FUNC_QUP1_SE7_L2, GPIO53_FUNC_QUP1_SE7_L3 }
+		},
+	[QUPV3_2_SE0] = { .regs = (void *)QUP_SERIAL16_BASE,
+		.pin = { GPIO(64), GPIO(65), GPIO(66), GPIO(67) },
+		.func = { GPIO64_FUNC_QUP2_SE0_L0, GPIO65_FUNC_QUP2_SE0_L1,
+			GPIO66_FUNC_QUP2_SE0_L2, GPIO67_FUNC_QUP2_SE0_L3 }
+		},
+	[QUPV3_2_SE1] = { .regs = (void *)QUP_SERIAL17_BASE,
+		.pin = { GPIO(68), GPIO(69), GPIO(70), GPIO(71) },
+		.func = { GPIO68_FUNC_QUP2_SE1_L0, GPIO69_FUNC_QUP2_SE1_L1,
+			GPIO70_FUNC_QUP2_SE1_L2, GPIO71_FUNC_QUP2_SE1_L3 }
+		},
+	[QUPV3_2_SE2] = { .regs = (void *)QUP_SERIAL18_BASE,
+		.pin = { GPIO(72), GPIO(73), GPIO(74), GPIO(75) },
+		.func = { GPIO72_FUNC_QUP2_SE2_L0, GPIO73_FUNC_QUP2_SE2_L1,
+			GPIO74_FUNC_QUP2_SE2_L2, GPIO75_FUNC_QUP2_SE2_L3 }
+		},
+	[QUPV3_2_SE3] = { .regs = (void *)QUP_SERIAL19_BASE,
+		.pin = { GPIO(76), GPIO(77), GPIO(78), GPIO(79) },
+		.func = { GPIO76_FUNC_QUP2_SE3_L0, GPIO77_FUNC_QUP2_SE3_L1,
+			GPIO78_FUNC_QUP2_SE3_L2, GPIO79_FUNC_QUP2_SE3_L3 }
+		},
+	[QUPV3_2_SE4] = { .regs = (void *)QUP_SERIAL20_BASE,
+		.pin = { GPIO(80), GPIO(81), GPIO(82), GPIO(83) },
+		.func = { GPIO80_FUNC_QUP2_SE4_L0, GPIO81_FUNC_QUP2_SE4_L1,
+			GPIO82_FUNC_QUP2_SE4_L2, GPIO83_FUNC_QUP2_SE4_L3 }
+		},
+	[QUPV3_2_SE5] = { .regs = (void *)QUP_SERIAL21_BASE,
+		.pin = { GPIO(84), GPIO(85), GPIO(86), GPIO(87) },
+		.func = { GPIO84_FUNC_QUP2_SE5_L0, GPIO85_FUNC_QUP2_SE5_L1,
+			GPIO86_FUNC_QUP2_SE5_L2, GPIO87_FUNC_QUP2_SE5_L3 }
+		},
+	[QUPV3_2_SE6] = { .regs = (void *)QUP_SERIAL22_BASE,
+		.pin = { GPIO(88), GPIO(89), GPIO(90), GPIO(91) },
+		.func = { GPIO88_FUNC_QUP2_SE6_L0, GPIO89_FUNC_QUP2_SE6_L1,
+			GPIO90_FUNC_QUP2_SE6_L2, GPIO91_FUNC_QUP2_SE6_L3 }
+		},
+	[QUPV3_2_SE7] = { .regs = (void *)QUP_SERIAL23_BASE,
+		.pin = { GPIO(86), GPIO(87), GPIO(84), GPIO(85) },
+		.func = { GPIO86_FUNC_QUP2_SE7_L0, GPIO87_FUNC_QUP2_SE7_L1,
+			GPIO84_FUNC_QUP2_SE7_L2, GPIO85_FUNC_QUP2_SE7_L3 }
+		},
 };

From 34d6bc878480627a71654106a5c8b5e5a73bb980 Mon Sep 17 00:00:00 2001
From: Subrata Banik <subratabanik@google.com>
Date: Fri, 11 Apr 2025 03:13:04 +0000
Subject: [PATCH 0855/3886] soc/qualcomm/x1p42100: Set correct Kconfig defaults
 for peripherals

Update the default Kconfig values for the `soc/qualcomm/x1p42100`
to specify the correct hardware instances/buses used for various
peripherals as per datasheet for bluey (dated 04/15).

Changes:
- Boot SPI flash bus set to 24.
- Console UART instance set to 21.
- Select FIXED_UART_FOR_CONSOLE Kconfig as UART is not really
  selectable due to GPIO Function 0 (bit-bang mode) default
  configuration.

Additionally, remove previous used TODO placeholders.

BUG=b:404985109
TEST=Successfully built google/bluey with the Qualcomm x1p42100 SoC.

Change-Id: Ia053edb731f7e08c98ffa3fe273ddd1c97b651bb
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87272
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/soc/qualcomm/x1p42100/Kconfig | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/src/soc/qualcomm/x1p42100/Kconfig b/src/soc/qualcomm/x1p42100/Kconfig
index 728f81e7c1..52f270b6d9 100644
--- a/src/soc/qualcomm/x1p42100/Kconfig
+++ b/src/soc/qualcomm/x1p42100/Kconfig
@@ -12,6 +12,7 @@ config SOC_QUALCOMM_X1P42100
 	select CACHE_MRC_SETTINGS
 	select COMMONLIB_STORAGE
 	select COMMONLIB_STORAGE_SD
+	select FIXED_UART_FOR_CONSOLE
 	select GENERIC_GPIO_LIB
 	select GENERIC_UDELAY
 	select HAS_RECOVERY_MRC_CACHE
@@ -37,11 +38,11 @@ config VBOOT
 
 config BOOT_DEVICE_SPI_FLASH_BUS
 	int
-	default 0 # TODO
+	default 24
 
 config UART_FOR_CONSOLE
 	int
-	default 0 # TODO
+	default 21
 	help
 	 Select the QUP instance to be used for UART console output.
 

From d2e698056e389d5c05b98abb79b0d87411463232 Mon Sep 17 00:00:00 2001
From: Subrata Banik <subratabanik@google.com>
Date: Wed, 2 Apr 2025 08:46:32 +0000
Subject: [PATCH 0856/3886] mb/google/bluey: Set correct Kconfig defaults for
 peripherals

Update the default Kconfig values for the google/bluey mainboard
to specify the correct hardware instances/buses used for various
peripherals as per bluey schematics (dated 04/15).

Changes:
- TPM I2C bus set to 0x10.
- ChromeEC SPI bus set to 0xb.

Removes previous TODO placeholders.

BUG=b:404985109
TEST=Successfully built google/bluey with the Qualcomm x1p42100 SoC.

Change-Id: I48283e9f5b9dc1d2f203dadbdf6d4e27566f0a83
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87094
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
---
 src/mainboard/google/bluey/Kconfig | 4 ++--
 src/mainboard/google/bluey/board.h | 4 ++--
 2 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/src/mainboard/google/bluey/Kconfig b/src/mainboard/google/bluey/Kconfig
index a22cae6bab..0746970bc5 100644
--- a/src/mainboard/google/bluey/Kconfig
+++ b/src/mainboard/google/bluey/Kconfig
@@ -49,13 +49,13 @@ config MAINBOARD_PART_NUMBER
 config DRIVER_TPM_I2C_BUS
 	depends on I2C_TPM
 	hex
-	default 0x00 # TODO
+	default 0x10
 
 config DRIVER_TPM_I2C_ADDR
 	default 0x50
 
 config EC_GOOGLE_CHROMEEC_SPI_BUS
 	hex
-	default 0x0 # TODO
+	default 0xb
 
 endif # BOARD_GOOGLE_BLUEY_COMMON
diff --git a/src/mainboard/google/bluey/board.h b/src/mainboard/google/bluey/board.h
index e6de22ef48..f7c4f23d91 100644
--- a/src/mainboard/google/bluey/board.h
+++ b/src/mainboard/google/bluey/board.h
@@ -6,8 +6,8 @@
 #include <assert.h>
 #include <gpio.h>
 
-#define GPIO_AP_EC_INT		GPIO(0)
-#define GPIO_GSC_AP_INT		GPIO(0)
+#define GPIO_AP_EC_INT		GPIO(67)
+#define GPIO_GSC_AP_INT		GPIO(34)
 
 void setup_chromeos_gpios(void);
 

From 7c965f9df0bd9810b296b6accbc9c41360d09579 Mon Sep 17 00:00:00 2001
From: Pranava Y N <pranavayn@google.com>
Date: Thu, 24 Apr 2025 10:42:44 +0530
Subject: [PATCH 0857/3886] MAINTAINERS: Add Nick, Avi, and Pranava for new
 google/ocelot entry

Add GOOGLE OCELOT MAINBOARDS section for src/mb/google/ocelot and
update the maintainers list to add Nick Vaccaro, Pranava Y N, and
Avi Uday as maintainers.

Change-Id: Ia5fc7fcdd5ea2f3588343834dccd86ee2b17f9a8
Signed-off-by: Pranava Y N <pranavayn@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87438
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
---
 MAINTAINERS | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/MAINTAINERS b/MAINTAINERS
index cc268c5c26..203868e252 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -365,6 +365,12 @@ M:	Nick Vaccaro <nvaccaro@chromium.org>
 S:	Maintained
 F:	src/mainboard/google/hatch/
 
+GOOGLE OCELOT MAINBOARDS
+M:	Nick Vaccaro <nvaccaro@chromium.org>
+M:	Pranava Y N <pranavayn@google.com>
+M:	Avi Uday <aviuday@google.com>
+F:	src/mainboard/google/ocelot/
+
 GOOGLE VOLTEER MAINBOARDS
 M:	Nick Vaccaro <nvaccaro@chromium.org>
 S:	Maintained

From 9ef62ad64c2fe3373da1ee0fc7dfe91d9169f207 Mon Sep 17 00:00:00 2001
From: Bora Guvendik <bora.guvendik@intel.com>
Date: Mon, 24 Mar 2025 15:08:53 -0700
Subject: [PATCH 0858/3886] mb/intel/ptlrvp: Introduce PTL RVP External and
 Internal EC Configurations
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

This commit adds configurations for both external and internal EC
versions of the PTL RVP board. The changes involve updates to the
Kconfig files to select appropriate EC configurations based on the
specific PTL RVP variant. By organizing these options, it ensures
that the build system selects the right EC components and
configurations, aligning with the specific needs of the board version
in use.

The new configuration for external EC (`BOARD_INTEL_PTLRVP_CHROMEEC`)
enables Chrome EC related config options and enables TPM, whereas
Intel EC (`BOARD_INTEL_PTLRVP`) disables Chrome EC related config
options and uses MOCK TPM.

BUG=none
TEST=Build the firmware for PTL RVP with both external and internal EC
settings, verifying that the correct components are included based on
the chosen configuration. Ensure that the board operates correctly
with the selected EC setup.

Change-Id: Ic3e40f2a19d7ed4f7a16e6e516a284a9a778b9fd
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86991
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
---
 src/mainboard/intel/ptlrvp/Kconfig            |  40 +-
 src/mainboard/intel/ptlrvp/Kconfig.name       |   3 +
 src/mainboard/intel/ptlrvp/Makefile.mk        |   3 +
 src/mainboard/intel/ptlrvp/intel.c            |  35 +
 src/mainboard/intel/ptlrvp/smihandler.c       |  13 +
 .../variants/baseboard/ptlrvp/Makefile.mk     |   2 +-
 .../variants/baseboard/ptlrvp/devicetree.cb   |   5 -
 .../ptlrvp/variants/ptlrvp/overridetree.cb    |   5 -
 .../variants/ptlrvp_chromeec/overridetree.cb  | 895 ++++++++++++++++++
 9 files changed, 974 insertions(+), 27 deletions(-)
 create mode 100644 src/mainboard/intel/ptlrvp/intel.c
 create mode 100644 src/mainboard/intel/ptlrvp/variants/ptlrvp_chromeec/overridetree.cb

diff --git a/src/mainboard/intel/ptlrvp/Kconfig b/src/mainboard/intel/ptlrvp/Kconfig
index 73e170d610..ad6ac41e22 100644
--- a/src/mainboard/intel/ptlrvp/Kconfig
+++ b/src/mainboard/intel/ptlrvp/Kconfig
@@ -16,21 +16,14 @@ config BOARD_INTEL_PTLRVP_COMMON
 	select DRIVERS_SPI_ACPI
 	select DUMP_SMBIOS_TYPE17
 	select EC_ACPI
-	select EC_GOOGLE_CHROMEEC
-	select EC_GOOGLE_CHROMEEC_BOARDID
-	select EC_GOOGLE_CHROMEEC_ESPI
-	select EC_GOOGLE_CHROMEEC_SMBIOS
 	select FW_CONFIG
-	select FW_CONFIG_SOURCE_CHROMEEC_CBI
 	select GENERATE_SMBIOS_TABLES
 	select GOOGLE_SMBIOS_MAINBOARD_VERSION
 	select HAVE_ACPI_RESUME
 	select HAVE_ACPI_TABLES
 	select HAVE_SPD_IN_CBFS
-	select I2C_TPM
 	select INTEL_LPSS_UART_FOR_CONSOLE
 	select MAINBOARD_DISABLE_STAGE_CACHE
-	select MAINBOARD_HAS_TPM2
 	select MB_COMPRESS_RAMSTAGE_LZ4
 	select PMC_IPC_ACPI_INTERFACE
 	select SOC_INTEL_COMMON_BLOCK_VARIANT_POWER_LIMIT
@@ -53,7 +46,6 @@ config BOARD_INTEL_BASEBOARD_PTLRVP
 	select SOC_INTEL_IOE_DIE_SUPPORT
 	select SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES
 	select SYSTEM_TYPE_LAPTOP
-	select TPM_GOOGLE_TI50
 
 config BOARD_INTEL_MODEL_PTLRVP
 	def_bool n
@@ -63,8 +55,22 @@ config BOARD_INTEL_MODEL_PTLRVP
 
 config BOARD_INTEL_PTLRVP
 	select BOARD_INTEL_MODEL_PTLRVP
-	select EC_GOOGLE_CHROMEEC_MEC
 	select MAINBOARD_USES_IFD_EC_REGION
+	select FW_CONFIG_SOURCE_CBFS
+
+config BOARD_INTEL_PTLRVP_CHROMEEC
+	select BOARD_INTEL_MODEL_PTLRVP
+	select EC_GOOGLE_CHROMEEC
+	select EC_GOOGLE_CHROMEEC_BOARDID
+	select EC_GOOGLE_CHROMEEC_ESPI
+	select EC_GOOGLE_CHROMEEC_MEC
+	select EC_GOOGLE_CHROMEEC_SKUID
+	select EC_GOOGLE_CHROMEEC_SMBIOS
+	select FW_CONFIG_SOURCE_CHROMEEC_CBI
+	select I2C_TPM
+	select MAINBOARD_HAS_TPM2
+	select MAINBOARD_USES_IFD_EC_REGION
+	select TPM_GOOGLE_TI50
 
 if BOARD_INTEL_PTLRVP_COMMON
 
@@ -73,7 +79,7 @@ config BASEBOARD_DIR
 	default "ptlrvp"
 
 config CHROMEOS
-	select EC_GOOGLE_CHROMEEC_SWITCHES
+	select EC_GOOGLE_CHROMEEC_SWITCHES if BOARD_INTEL_PTLRVP_CHROMEEC
 	select GBB_FLAG_DISABLE_EC_SOFTWARE_SYNC
 	select GBB_FLAG_FORCE_DEV_BOOT_USB
 	select GBB_FLAG_FORCE_MANUAL_RECOVERY
@@ -95,11 +101,11 @@ config DIMM_SPD_SIZE
 
 config DRIVER_TPM_I2C_ADDR
 	hex
-	default 0x50
+	default 0x50 if BOARD_INTEL_PTLRVP_CHROMEEC
 
 config DRIVER_TPM_I2C_BUS
 	hex
-	default 0x03 if BOARD_INTEL_MODEL_PTLRVP
+	default 0x03 if BOARD_INTEL_PTLRVP_CHROMEEC
 
 config HAVE_SLP_S0_GATE
 	def_bool n
@@ -112,16 +118,16 @@ config MAINBOARD_FAMILY
 	default "Intel_Ptlrvp"
 
 config MAINBOARD_PART_NUMBER
-	default "Ptlrvp" if BOARD_INTEL_PTLRVP
+	default "Ptlrvp"
 
 config MEMORY_SOLDERDOWN
 	def_bool n
-	select CHROMEOS_DRAM_PART_NUMBER_IN_CBI if CHROMEOS
+	select CHROMEOS_DRAM_PART_NUMBER_IN_CBI if CHROMEOS && EC_GOOGLE_CHROMEEC_MEC
 	select HAVE_SPD_IN_CBFS
 
 config TPM_TIS_ACPI_INTERRUPT
 	int
-	default 47 if BOARD_INTEL_MODEL_PTLRVP # GPE0_DW1_15 (GPP_D15)
+	default 47 if BOARD_INTEL_PTLRVP_CHROMEEC # GPE0_DW1_15 (GPP_D15)
 
 # FIXME: update as per board schematics
 config UART_FOR_CONSOLE
@@ -136,9 +142,11 @@ config VARIANT_DIR
 	default "ptlrvp" if BOARD_INTEL_MODEL_PTLRVP
 
 config OVERRIDE_DEVICETREE
-	default "variants/\$(CONFIG_VARIANT_DIR)/overridetree.cb"
+	default "variants/\$(CONFIG_VARIANT_DIR)/overridetree.cb" if BOARD_INTEL_PTLRVP
+	default "variants/\$(CONFIG_VARIANT_DIR)_chromeec/overridetree.cb" if BOARD_INTEL_PTLRVP_CHROMEEC
 
 config VBOOT
 	select VBOOT_LID_SWITCH
+	select VBOOT_MOCK_SECDATA if BOARD_INTEL_PTLRVP
 
 endif # BOARD_INTEL_PTLRVP_COMMON
diff --git a/src/mainboard/intel/ptlrvp/Kconfig.name b/src/mainboard/intel/ptlrvp/Kconfig.name
index f8d8f17dc1..9bcf99b2f2 100644
--- a/src/mainboard/intel/ptlrvp/Kconfig.name
+++ b/src/mainboard/intel/ptlrvp/Kconfig.name
@@ -4,3 +4,6 @@ comment "Ptlrvp"
 
 config BOARD_INTEL_PTLRVP
 	bool "-> Ptlrvp"
+
+config BOARD_INTEL_PTLRVP_CHROMEEC
+	bool "-> Google Chrome EC"
diff --git a/src/mainboard/intel/ptlrvp/Makefile.mk b/src/mainboard/intel/ptlrvp/Makefile.mk
index aea91d577a..d2c78f4411 100644
--- a/src/mainboard/intel/ptlrvp/Makefile.mk
+++ b/src/mainboard/intel/ptlrvp/Makefile.mk
@@ -3,14 +3,17 @@
 bootblock-y += bootblock.c
 
 verstage-$(CONFIG_CHROMEOS) += chromeos.c
+verstage-$(CONFIG_BOARD_INTEL_PTLRVP) += intel.c
 
 romstage-y += romstage.c
 romstage-$(CONFIG_CHROMEOS) += chromeos.c
+romstage-$(CONFIG_BOARD_INTEL_PTLRVP) += intel.c
 
 ramstage-y += mainboard.c
 ramstage-$(CONFIG_CHROMEOS) += chromeos.c
 ramstage-y += ec.c
 ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_HDA_VERB) += variants/$(VARIANT_DIR)/hda_verb.c
+ramstage-$(CONFIG_BOARD_INTEL_PTLRVP) += intel.c
 
 smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c
 
diff --git a/src/mainboard/intel/ptlrvp/intel.c b/src/mainboard/intel/ptlrvp/intel.c
new file mode 100644
index 0000000000..600d1b3bb7
--- /dev/null
+++ b/src/mainboard/intel/ptlrvp/intel.c
@@ -0,0 +1,35 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <bootmode.h>
+#include <cpu/x86/smm.h>
+#include <ec/google/chromeec/ec.h>
+#include <elog.h>
+#include <intelblocks/smihandler.h>
+#include <vendorcode/google/chromeos/chromeos.h>
+
+void google_chromeec_events_init(const struct google_chromeec_event_info *info,
+				 bool is_s3_wakeup)
+{
+	/* no-op */
+}
+
+int get_lid_switch(void)
+{
+	/* Lid always open */
+	return 1;
+}
+
+int get_recovery_mode_switch(void)
+{
+	return 0;
+}
+
+bool chromeos_device_branded_plus_hard(void)
+{
+	return false;
+}
+
+bool chromeos_device_branded_plus_soft(void)
+{
+	return false;
+}
diff --git a/src/mainboard/intel/ptlrvp/smihandler.c b/src/mainboard/intel/ptlrvp/smihandler.c
index 9208d51613..118f7536dd 100644
--- a/src/mainboard/intel/ptlrvp/smihandler.c
+++ b/src/mainboard/intel/ptlrvp/smihandler.c
@@ -9,21 +9,34 @@
 
 void mainboard_smi_sleep(u8 slp_typ)
 {
+	if (!CONFIG(EC_GOOGLE_CHROMEEC))
+		return;
+
 	chromeec_smi_sleep(slp_typ, MAINBOARD_EC_S3_WAKE_EVENTS, MAINBOARD_EC_S5_WAKE_EVENTS);
 }
 
 int mainboard_smi_apmc(u8 apmc)
 {
+	if (!CONFIG(EC_GOOGLE_CHROMEEC))
+		return 0;
+
 	chromeec_smi_apmc(apmc, MAINBOARD_EC_SCI_EVENTS, MAINBOARD_EC_SMI_EVENTS);
+
 	return 0;
 }
 
 void elog_gsmi_cb_mainboard_log_wake_source(void)
 {
+	if (!CONFIG(EC_GOOGLE_CHROMEEC))
+		return;
+
 	google_chromeec_log_events(MAINBOARD_EC_LOG_EVENTS | MAINBOARD_EC_S0IX_WAKE_EVENTS);
 }
 
 void mainboard_smi_espi_handler(void)
 {
+	if (!CONFIG(EC_GOOGLE_CHROMEEC))
+		return;
+
 	chromeec_smi_process_events();
 }
diff --git a/src/mainboard/intel/ptlrvp/variants/baseboard/ptlrvp/Makefile.mk b/src/mainboard/intel/ptlrvp/variants/baseboard/ptlrvp/Makefile.mk
index 47123cd318..ff6ed05ded 100644
--- a/src/mainboard/intel/ptlrvp/variants/baseboard/ptlrvp/Makefile.mk
+++ b/src/mainboard/intel/ptlrvp/variants/baseboard/ptlrvp/Makefile.mk
@@ -1,4 +1,4 @@
 ## SPDX-License-Identifier: GPL-2.0-only
 
 romstage-y += memory.c
-ramstage-y += ramstage.c
+ramstage-$(CONFIG_EC_GOOGLE_CHROMEEC) += ramstage.c
diff --git a/src/mainboard/intel/ptlrvp/variants/baseboard/ptlrvp/devicetree.cb b/src/mainboard/intel/ptlrvp/variants/baseboard/ptlrvp/devicetree.cb
index 2cf249f9aa..c45738a090 100644
--- a/src/mainboard/intel/ptlrvp/variants/baseboard/ptlrvp/devicetree.cb
+++ b/src/mainboard/intel/ptlrvp/variants/baseboard/ptlrvp/devicetree.cb
@@ -90,10 +90,5 @@ chip soc/intel/pantherlake
 		device ref pmc_shared_sram on end
 		device ref heci1 on end
 		device ref uart0 on end
-		device ref soc_espi on
-			chip ec/google/chromeec
-				device pnp 0c09.0 on end
-			end
-		end
 	end
 end
diff --git a/src/mainboard/intel/ptlrvp/variants/ptlrvp/overridetree.cb b/src/mainboard/intel/ptlrvp/variants/ptlrvp/overridetree.cb
index cb4c21a1f7..4a33387cb2 100644
--- a/src/mainboard/intel/ptlrvp/variants/ptlrvp/overridetree.cb
+++ b/src/mainboard/intel/ptlrvp/variants/ptlrvp/overridetree.cb
@@ -793,11 +793,6 @@ chip soc/intel/pantherlake
 					probe AUDIO AUDIO_MAX98360_ALC5682I_I2S
 				end
 			end
-			chip drivers/i2c/tpm
-				register "hid" = ""GOOG0005""
-				register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_D15_IRQ)"
-				device i2c 50 on end
-			end
 		end # I2C3
 		device ref i2c4 on
 			chip drivers/i2c/hid
diff --git a/src/mainboard/intel/ptlrvp/variants/ptlrvp_chromeec/overridetree.cb b/src/mainboard/intel/ptlrvp/variants/ptlrvp_chromeec/overridetree.cb
new file mode 100644
index 0000000000..d836ab5564
--- /dev/null
+++ b/src/mainboard/intel/ptlrvp/variants/ptlrvp_chromeec/overridetree.cb
@@ -0,0 +1,895 @@
+fw_config
+	field AUDIO 0 3
+		option AUDIO_NONE			0
+		option AUDIO_MAX98373_ALC5682_SNDW	1
+		option AUDIO_ALC722_SNDW		2
+		option AUDIO_ALC256_HDA			3
+		option AUDIO_MAX98360_ALC5682I_I2S	4
+		option AUDIO_ALC721_SNDW		5
+	end
+	field WIFI 4 5
+		option WIFI_CNVI_6		0
+		option WIFI_CNVI_7		1
+		option WIFI_PCIE_6		2
+		option WIFI_PCIE_7		3
+	end
+	field CELLULAR 6 7
+		option CELLULAR_ABSENT		0
+		option CELLULAR_USB		1
+		option CELLULAR_PCIE		2
+	end
+	field TOUCHSCREEN 8 10
+		option TOUCHSCREEN_NONE		0
+		option TOUCHSCREEN_LPSS_I2C	1
+		option TOUCHSCREEN_GSPI		2
+		option TOUCHSCREEN_THC_SPI	3
+		option TOUCHSCREEN_THC_I2C	4
+	end
+	field TOUCHPAD 11 12
+		option TOUCHPAD_NONE		0
+		option TOUCHPAD_THC_I2C		1
+		option TOUCHPAD_LPSS_I2C	2
+	end
+	field SD 13 14
+		option SD_NONE			0
+		option SD_GENSYS		1
+		option SD_BAYHUB		2
+	end
+	field STORAGE 15 16
+		option STORAGE_UNKNOWN		0
+		option STORAGE_NVME_GEN4	1
+		option STORAGE_NVME_GEN5	2
+		option STORAGE_UFS		3
+	end
+	field FP 17
+		option FP_ABSENT		0
+		option FP_PRESENT		1
+	end
+	field DISPLAY 18
+		option DISPLAY_ABSENT		0
+		option DISPLAY_PRESENT		1
+	end
+	field KB 19
+		option KB_ABSENT		0
+		option KB_PRESENT		1
+	end
+	field UFC 20 21
+		option UFC_ABSENT		0
+		option UFC_MIPI			1
+		option UFC_USB			2
+	end
+	field WFC 22 23
+		option WFC_ABSENT		0
+		option WFC_MIPI			1
+		option WFC_USB			2
+	end
+	field ISH 24
+		option ISH_DISABLE		0
+		option ISH_ENABLE		1
+	end
+end
+
+chip soc/intel/pantherlake
+
+	register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC_SKIP)" # USB2_C0
+	register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC_SKIP)" # USB2_C1
+	register "usb2_ports[2]" = "USB2_PORT_TYPE_C(OC_SKIP)" # USB2_C2
+	register "usb2_ports[3]" = "USB2_PORT_TYPE_C(OC_SKIP)" # USB2_C3
+	register "usb2_ports[4]" = "USB2_PORT_MID(OC0)" # Type-A Port A0
+	register "usb2_ports[5]" = "USB2_PORT_MID(OC0)" # Type-A Port A1 / WWAN with rework
+	register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # CNVi BT or discrete BT
+
+	register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)" # USB3.2 x1 Type-A Con #1
+	register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC0)" # USB3.2 x1 Type-A Con #2 / M.2 WWAN with rework
+
+	register "tcss_ports[0]" = "TCSS_PORT_DEFAULT(OC_SKIP)"
+	register "tcss_ports[1]" = "TCSS_PORT_DEFAULT(OC_SKIP)"
+	register "tcss_ports[2]" = "TCSS_PORT_DEFAULT(OC_SKIP)"
+	register "tcss_ports[3]" = "TCSS_PORT_DEFAULT(OC_SKIP)"
+
+	register "tcss_cap_policy[0]" = "TCSS_TYPE_C_PORT_FULL_FUN"
+	register "tcss_cap_policy[1]" = "TCSS_TYPE_C_PORT_FULL_FUN"
+	register "tcss_cap_policy[2]" = "TCSS_TYPE_C_PORT_FULL_FUN"
+	register "tcss_cap_policy[3]" = "TCSS_TYPE_C_PORT_FULL_FUN"
+
+	# Enable EDP in PortA
+	register "ddi_port_A_config" = "1"
+	register "ddi_ports_config" = "{
+                [DDI_PORT_A] = DDI_ENABLE_HPD,
+        }"
+
+	register "serial_io_i2c_mode" = "{
+		[PchSerialIoIndexI2C0]  = PchSerialIoPci,
+		[PchSerialIoIndexI2C1]  = PchSerialIoPci,
+		[PchSerialIoIndexI2C2]  = PchSerialIoPci,
+		[PchSerialIoIndexI2C3]  = PchSerialIoPci,
+		[PchSerialIoIndexI2C4]  = PchSerialIoPci,
+		[PchSerialIoIndexI2C5]  = PchSerialIoPci,
+	}"
+
+	register "serial_io_gspi_mode" = "{
+		[PchSerialIoIndexGSPI0] = PchSerialIoPci,
+		[PchSerialIoIndexGSPI1] = PchSerialIoDisabled,
+		[PchSerialIoIndexGSPI0A] = PchSerialIoDisabled,
+	}"
+
+	# Intel Common SoC Config
+	#+-------------------+---------------------------+
+	#| Field             |  Value                    |
+	#+-------------------+---------------------------+
+	#| I2C1              | Camera(CRD1)              |
+	#| I2C2              | Camera(CRD2)              |
+	#| I2C3              | Audio, TPM(cr50)          |
+	#| I2C4              | Touchscreen               |
+	#| I2C5              | Touchpad                  |
+	#+-------------------+---------------------------+
+	register "common_soc_config" = "{
+		.chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT,
+		.i2c[1] = {
+			.speed = I2C_SPEED_FAST,
+		},
+		.i2c[2] = {
+			.speed = I2C_SPEED_FAST,
+		},
+		.i2c[3] = {
+			.early_init = 1,
+			.speed = I2C_SPEED_FAST,
+		},
+		.i2c[4] = {
+			.speed = I2C_SPEED_FAST,
+		},
+		.i2c[5] = {
+			.speed = I2C_SPEED_FAST,
+		},
+	}"
+
+	device domain 0 on
+		device ref igpu on
+			probe DISPLAY DISPLAY_PRESENT
+			chip drivers/gfx/generic
+				register "device_count" = "5"
+				# DDIA for eDP
+				register "device[0].name" = ""LCD0""
+				register "device[0].type" = "panel"
+				# DDIB for HDMI
+				# If HDMI is not enumerated in the kernel, then no GFX device should be added for DDIB
+				register "device[1].name" = ""DD01""
+				# TCP0 (DP-1) for port C0
+				register "device[2].name" = ""DD02""
+				register "device[2].use_pld" = "true"
+				register "device[2].pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(1, 1))"
+				# TCP1 (DP-2) for port C1
+				register "device[3].name" = ""DD03""
+				register "device[3].use_pld" = "true"
+				register "device[3].pld" = "ACPI_PLD_TYPE_C(LEFT, RIGHT, ACPI_PLD_GROUP(2, 1))"
+				# TCP2 (DP-3) for port C2
+				register "device[4].name" = ""DD04""
+				register "device[4].use_pld" = "true"
+				register "device[4].pld" = "ACPI_PLD_TYPE_C(RIGHT, LEFT, ACPI_PLD_GROUP(3, 1))"
+				device generic 0 on end
+			end
+		end
+
+		device ref dtt on
+			chip drivers/intel/dptf
+				## sensor information
+				register "options.tsr[0].desc" = ""DDR_SOC""
+				register "options.tsr[1].desc" = ""Ambient""
+				register "options.tsr[2].desc" = ""Charger""
+				register "options.tsr[3].desc" = ""wwan""
+
+				## Active Policy
+				# FIXME: below values are initial reference values only
+				register "policies.active" = "{
+						[0] = {
+							.target = DPTF_TEMP_SENSOR_0,
+							.thresholds = {
+									TEMP_PCT(70, 97),
+									TEMP_PCT(65, 90),
+									TEMP_PCT(60, 80),
+									TEMP_PCT(55, 75),
+									TEMP_PCT(50, 65),
+									TEMP_PCT(45, 45),
+									TEMP_PCT(43, 30),
+								}
+							},
+						[1] = {
+							.target = DPTF_TEMP_SENSOR_1,
+							.thresholds = {
+									TEMP_PCT(70, 97),
+									TEMP_PCT(65, 90),
+									TEMP_PCT(60, 80),
+									TEMP_PCT(55, 75),
+									TEMP_PCT(50, 65),
+									TEMP_PCT(45, 45),
+									TEMP_PCT(43, 30),
+								}
+							},
+						[2] = {
+							.target = DPTF_TEMP_SENSOR_2,
+							.thresholds = {
+									TEMP_PCT(75, 90),
+									TEMP_PCT(70, 80),
+									TEMP_PCT(65, 70),
+									TEMP_PCT(60, 50),
+								}
+							},
+						[3] = {
+							.target = DPTF_TEMP_SENSOR_3,
+							.thresholds = {
+									TEMP_PCT(75, 90),
+									TEMP_PCT(70, 80),
+									TEMP_PCT(65, 70),
+									TEMP_PCT(60, 60),
+									TEMP_PCT(55, 50),
+									TEMP_PCT(50, 40),
+									TEMP_PCT(45, 30),
+								}
+							}
+				}"
+
+				## Passive Policy
+				# TODO: below values are initial reference values only
+				register "policies.passive" = "{
+						[0] = DPTF_PASSIVE(CPU,         CPU,           95, 5000),
+						[1] = DPTF_PASSIVE(CPU,         TEMP_SENSOR_0, 80, 5000),
+						[2] = DPTF_PASSIVE(CPU,         TEMP_SENSOR_1, 80, 5000),
+						[3] = DPTF_PASSIVE(CHARGER,     TEMP_SENSOR_2, 75, 5000),
+						[4] = DPTF_PASSIVE(CPU,         TEMP_SENSOR_3, 80, 5000),
+				}"
+
+				## Critical Policy
+				# TODO: below values are initial reference values only
+				register "policies.critical" = "{
+						[0] = DPTF_CRITICAL(CPU,          105, SHUTDOWN),
+						[1] = DPTF_CRITICAL(TEMP_SENSOR_0, 85, SHUTDOWN),
+						[2] = DPTF_CRITICAL(TEMP_SENSOR_1, 85, SHUTDOWN),
+						[3] = DPTF_CRITICAL(TEMP_SENSOR_2, 85, SHUTDOWN),
+						[4] = DPTF_CRITICAL(TEMP_SENSOR_3, 85, SHUTDOWN),
+				}"
+
+				## Power Limits Control
+				register "controls.power_limits" = "{
+						.pl1 = {
+							.min_power = 25000,
+							.max_power = 25000,
+							.time_window_min = 28 * MSECS_PER_SEC,
+							.time_window_max = 32 * MSECS_PER_SEC,
+							.granularity = 200,
+						},
+						.pl2 = {
+							.min_power = 95000,
+							.max_power = 95000,
+							.time_window_min = 28 * MSECS_PER_SEC,
+							.time_window_max = 32 * MSECS_PER_SEC,
+							.granularity = 1000,
+						}
+				}"
+
+				## Charger Performance Control (Control, mA)
+				register "controls.charger_perf" = "{
+						[0] = { 255, 3000 },
+						[1] = {  24, 1500 },
+						[2] = {  16, 1000 },
+						[3] = {   8,  500 }
+				}"
+
+				## Fan Performance Control (Percent, Speed, Noise, Power)
+				register "controls.fan_perf" = "{
+						[0] = {  90, 6700, 220, 2200, },
+						[1] = {  80, 5800, 180, 1800, },
+						[2] = {  70, 5000, 145, 1450, },
+						[3] = {  60, 4900, 115, 1150, },
+						[4] = {  50, 3838,  90,  900, },
+						[5] = {  40, 2904,  55,  550, },
+						[6] = {  30, 2337,  30,  300, },
+						[7] = {  20, 1608,  15,  150, },
+						[8] = {  10,  800,  10,  100, },
+						[9] = {   0,    0,   0,   50, }
+				}"
+
+				## Fan options
+				register "options.fan.fine_grained_control" = "true"
+				register "options.fan.step_size" = "2"
+
+				device generic 0 alias dptf_policy on end
+			end
+		end
+
+		device ref ipu on
+			chip drivers/intel/mipi_camera
+				register "acpi_uid" = "0x50000"
+				register "acpi_name" = ""IPU0""
+				register "device_type" = "INTEL_ACPI_CAMERA_CIO2"
+				register "cio2_num_ports" = "2"
+				register "cio2_lanes_used" = "{4,2}" # 4 and 2 CSI Camera lanes are used
+				register "cio2_lane_endpoint[0]" = ""^I2C1.CAM0""
+				register "cio2_lane_endpoint[1]" = ""^I2C2.CAM1""
+				register "cio2_prt[0]" = "0"
+				register "cio2_prt[1]" = "2"
+				device generic 0 on
+					probe UFC UFC_MIPI
+					probe WFC WFC_MIPI
+				end
+			end
+		end
+
+		device ref iaa off end
+
+		device ref thc0 on
+			probe TOUCHSCREEN TOUCHSCREEN_THC_SPI
+			probe TOUCHSCREEN TOUCHSCREEN_THC_I2C
+			# THC0 is function 0; hence it needs to be enabled when THC1 is to be enabled.
+			probe TOUCHPAD TOUCHPAD_THC_I2C
+		end
+		device ref thc1 on
+			probe TOUCHPAD TOUCHPAD_THC_I2C
+		end
+
+		device ref tbt_pcie_rp0 on end
+		device ref tbt_pcie_rp1 on end
+		device ref tbt_pcie_rp2 on end
+		device ref tbt_pcie_rp3 on end
+		device ref tcss_xhci on
+			chip drivers/usb/acpi
+				device ref tcss_root_hub on
+					chip drivers/usb/acpi
+						register "desc" = ""USB3 Type-C Port C0""
+						register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
+						register "group" = "ACPI_PLD_GROUP(4, 2)"
+						device ref tcss_usb3_port0 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB3 Type-C Port C1""
+						register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
+						register "group" = "ACPI_PLD_GROUP(3, 2)"
+						device ref tcss_usb3_port1 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB3 Type-C Port C2""
+						register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
+						register "group" = "ACPI_PLD_GROUP(2, 2)"
+						device ref tcss_usb3_port2 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB3 Type-C Port C3""
+						register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
+						register "group" = "ACPI_PLD_GROUP(1, 2)"
+						device ref tcss_usb3_port3 on end
+					end
+				end
+			end
+		end
+
+		device ref tcss_dma0 on
+			chip drivers/intel/usb4/retimer
+				register "dfp[0].power_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B21)"
+				use tcss_usb3_port0 as dfp[0].typec_port
+				device generic 0 on end
+			end
+			chip drivers/intel/usb4/retimer
+				register "dfp[1].power_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B21)"
+				use tcss_usb3_port1 as dfp[1].typec_port
+				device generic 0 on end
+			end
+		end
+		device ref tcss_dma1 on
+			chip drivers/intel/usb4/retimer
+				register "dfp[0].power_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B21)"
+				use tcss_usb3_port2 as dfp[0].typec_port
+				device generic 0 on end
+			end
+			chip drivers/intel/usb4/retimer
+				register "dfp[1].power_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B21)"
+				use tcss_usb3_port3 as dfp[1].typec_port
+				device generic 0 on end
+			end
+		end
+
+		device ref ish on
+			probe ISH ISH_ENABLE
+			probe FP FP_PRESENT
+			chip drivers/intel/ish
+				register "add_acpi_dma_property" = "true"
+				device generic 0 on end
+			end
+		end
+
+		device ref xhci on
+			chip drivers/usb/acpi
+				device ref xhci_root_hub on
+					chip drivers/usb/acpi
+						register "desc" = ""USB2 Type-C Port C0""
+						register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
+						register "group" = "ACPI_PLD_GROUP(1, 1)"
+						device ref usb2_port1 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB2 Type-C Port C1""
+						register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
+						register "group" = "ACPI_PLD_GROUP(2, 1)"
+						device ref usb2_port2 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB2 Type-C Port C2""
+						register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
+						register "group" = "ACPI_PLD_GROUP(3, 1)"
+						device ref usb2_port3 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB2 Type-C Port C3""
+						register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
+						register "group" = "ACPI_PLD_GROUP(4, 1)"
+						device ref usb2_port4 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB2 Type-A Port 1""
+						register "type" = "UPC_TYPE_A"
+						register "group" = "ACPI_PLD_GROUP(5, 1)"
+						device ref usb2_port5 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB2 Type-A Port 2""
+						register "type" = "UPC_TYPE_A"
+						register "group" = "ACPI_PLD_GROUP(6, 1)"
+						device ref usb2_port6 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB2 Type-A Port 3""
+						register "type" = "UPC_TYPE_A"
+						register "group" = "ACPI_PLD_GROUP(7, 1)"
+						device ref usb2_port7 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB2 Bluetooth""
+						register "type" = "UPC_TYPE_INTERNAL"
+						register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A16)"
+						device ref usb2_port8 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB3 Type-A Port 1""
+						register "type" = "UPC_TYPE_USB3_A"
+						register "group" = "ACPI_PLD_GROUP(1, 2)"
+						device ref usb3_port1 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB3 Type-A Port 2""
+						register "type" = "UPC_TYPE_USB3_A"
+						register "group" = "ACPI_PLD_GROUP(2, 2)"
+						device ref usb3_port2 on end
+					end
+				end
+			end
+		end
+
+		device ref ufs on
+			probe STORAGE STORAGE_UFS
+			probe STORAGE STORAGE_UNKNOWN
+		end
+
+		device ref pcie_rp2 on
+			probe CELLULAR CELLULAR_PCIE
+			register "pcie_rp[PCIE_RP(2)]" = "{
+				.clk_src = 5,
+				.clk_req = 5,
+				.flags = PCIE_RP_CLK_REQ_DETECT | PCIE_RP_LTR | PCIE_RP_AER,
+			}"
+			chip soc/intel/common/block/pcie/rtd3
+				register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D03)"
+				register "reset_off_delay_ms" = "20"
+				register "srcclk_pin" = "5"
+				register "ext_pm_support" = "ACPI_PCIE_RP_EMIT_ALL"
+				register "skip_on_off_support" = "true"
+				register "use_rp_mutex" = "true"
+				device generic 0 alias rp2_rtd3 on end
+			end
+			chip drivers/wwan/fm
+				register "fcpo_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A09)"
+				register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B20)"
+				register "perst_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D03)"
+				register "wake_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_E02)"
+				register "add_acpi_dma_property" = "true"
+				use rp2_rtd3 as rtd3dev
+				device generic 0 on end
+			end
+		end # WWAN
+		device ref pcie_rp3 on
+			probe SD SD_GENSYS
+			probe SD SD_BAYHUB
+			# Enable PCH PCIE x1 slot using CLK 3
+			register "pcie_rp[PCIE_RP(3)]" = "{
+				.clk_src = 2,
+				.clk_req = 2,
+				.flags = PCIE_RP_CLK_REQ_DETECT | PCIE_RP_LTR | PCIE_RP_AER,
+			}"
+			chip soc/intel/common/block/pcie/rtd3
+				register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A08)"
+				register "enable_delay_ms" = "100"
+				register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D19)"
+				register "reset_delay_ms" = "20"
+				register "srcclk_pin" = "2"
+				device generic 0 on end
+			end
+		end # PCIE x1 slot
+		device ref pcie_rp4 on
+			probe WIFI WIFI_PCIE_6
+			probe WIFI WIFI_PCIE_7
+			register "pcie_rp[PCH_RP(4)]" = "{
+				.clk_src = 4,
+				.clk_req = 4,
+				.flags = PCIE_RP_CLK_REQ_DETECT | PCIE_RP_LTR | PCIE_RP_AER,
+			}"
+			chip soc/intel/common/block/pcie/rtd3
+				register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A11)"
+				register "srcclk_pin" = "4"
+				device pci 00.0 on end
+			end
+			chip drivers/wifi/generic
+				register "add_acpi_dma_property" = "true"
+				register "wake" = "GPE0_DW0_12" # GPP_A12
+				use usb2_port7 as bluetooth_companion
+				device pci 00.0 on end
+			end
+		end # discrete WLAN
+		device ref pcie_rp5 on
+			probe STORAGE STORAGE_NVME_GEN4
+			probe STORAGE STORAGE_UNKNOWN
+			register "pcie_rp[PCIE_RP(5)]" = "{
+			.clk_src = 6,
+			.clk_req = 6,
+			.flags = PCIE_RP_CLK_REQ_DETECT | PCIE_RP_LTR | PCIE_RP_AER,
+			}"
+			chip soc/intel/common/block/pcie/rtd3
+				register "is_storage" = "true"
+				register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B10)"
+				register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B09)"
+				register "srcclk_pin" = "6"
+				device generic 0 on end
+			end
+		end # Gen4 M.2 SSD
+		device ref pcie_rp9 on
+			probe STORAGE STORAGE_NVME_GEN5
+			probe STORAGE STORAGE_UNKNOWN
+			register "pcie_rp[PCIE_RP(9)]" = "{
+			.clk_src = 1,
+			.clk_req = 1,
+			.flags = PCIE_RP_CLK_REQ_DETECT | PCIE_RP_LTR | PCIE_RP_AER,
+			}"
+			chip soc/intel/common/block/pcie/rtd3
+				register "is_storage" = "true"
+				register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B16)"
+				register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_E03)"
+				register "srcclk_pin" = "1"
+				device generic 0 on end
+			end
+		end # Gen5 M.2 SSD
+		device ref cnvi_wifi on
+			probe WIFI WIFI_CNVI_6
+			probe WIFI WIFI_CNVI_7
+			chip drivers/wifi/generic
+				register "wake" = "GPE0_PME_B0"
+				register "add_acpi_dma_property" = "true"
+				register "enable_cnvi_ddr_rfim" = "true"
+				device generic 0 on end
+			end
+		end # CNVi
+		# NOTE: i2c0 is function 0; hence it needs to be enabled when any of i2c1-5 is enabled.
+		# TPM device is under i2c3. Therefore, i2c0 needs to be enabled anyways.
+		device ref i2c0 on end
+		device ref i2c1 on
+			chip drivers/intel/mipi_camera
+				register "acpi_hid" = ""OVTIDB10""
+				register "acpi_uid" = "0"
+				register "acpi_name" = ""CAM0""
+				register "chip_name" = ""Ov 13b10 Camera""
+				register "device_type" = "INTEL_ACPI_CAMERA_SENSOR"
+
+				register "ssdb.vcm_type" = "0x0C"
+				register "vcm_name" = ""VCM1""
+
+				register "ssdb.lanes_used" = "4"
+				register "num_freq_entries" = "1"
+				register "link_freq[0]" = "560 * MHz" # 560 MHz
+				register "remote_name" = ""IPU0""
+				register "max_dstate_for_probe" = "ACPI_DEVICE_SLEEP_D3_COLD"
+
+				register "has_power_resource" = "true"
+				#Controls
+				register "clk_panel.clks[0].clknum" = "0" # IMGCLKOUT_0
+				register "clk_panel.clks[0].freq" = "1" #19.2 Mhz
+				register "gpio_panel.gpio[0].gpio_num" = "GPP_C05" #power_enable
+				register "gpio_panel.gpio[1].gpio_num" = "GPP_E10" #reset
+
+				#_ON
+				register "on_seq.ops_cnt" = "4"
+				register "on_seq.ops[0]" = "SEQ_OPS_CLK_ENABLE(0, 0)"
+				register "on_seq.ops[1]" = "SEQ_OPS_GPIO_ENABLE(0, 2)"
+				register "on_seq.ops[2]" = "SEQ_OPS_GPIO_DISABLE(1, 1)"
+				register "on_seq.ops[3]" = "SEQ_OPS_GPIO_ENABLE(1, 1)"
+
+				#_OFF
+				register "off_seq.ops_cnt" = "3"
+				register "off_seq.ops[0]" = "SEQ_OPS_CLK_DISABLE(0, 0)"
+				register "off_seq.ops[1]" = "SEQ_OPS_GPIO_DISABLE(1, 0)"
+				register "off_seq.ops[2]" = "SEQ_OPS_GPIO_DISABLE(0, 0)"
+
+				device i2c 36 on
+					probe WFC WFC_MIPI
+				end
+			end
+			chip drivers/intel/mipi_camera
+				register "acpi_uid" = "3"
+				register "acpi_name" = ""VCM1""
+				register "chip_name" = ""DW AF VCM""
+				register "device_type" = "INTEL_ACPI_CAMERA_VCM"
+
+				register "vcm_compat" = ""dongwoon,dw9714""
+
+				register "max_dstate_for_probe" = "ACPI_DEVICE_SLEEP_D0"
+
+				register "has_power_resource" = "true"
+
+				#Controls
+				register "gpio_panel.gpio[0].gpio_num" = "GPP_C05" #power_enable
+
+				#_ON
+				register "on_seq.ops_cnt" = "1"
+				register "on_seq.ops[0]" = "SEQ_OPS_GPIO_ENABLE(0, 0)"
+
+				#_OFF
+				register "off_seq.ops_cnt" = "1"
+				register "off_seq.ops[0]" = "SEQ_OPS_GPIO_DISABLE(0, 0)"
+
+				device i2c 0C on
+					probe WFC WFC_MIPI
+				end
+			end
+			chip drivers/intel/mipi_camera
+				register "acpi_uid" = "1"
+				register "acpi_name" = ""NVM1""
+				register "chip_name" = ""BRCA016GWZ""
+				register "device_type" = "INTEL_ACPI_CAMERA_NVM"
+
+				register "nvm_compat" = ""atmel,24c16""
+
+				register "nvm_size" = "0x800"
+				register "nvm_pagesize" = "0x01"
+				register "nvm_readonly" = "0x01"
+				register "nvm_width" = "0x08"
+
+				register "max_dstate_for_probe" = "ACPI_DEVICE_SLEEP_D0"
+
+				register "has_power_resource" = "true"
+
+				#Controls
+				register "gpio_panel.gpio[0].gpio_num" = "GPP_C05" #power_enable
+
+				#_ON
+				register "on_seq.ops_cnt" = "1"
+				register "on_seq.ops[0]" = "SEQ_OPS_GPIO_ENABLE(0, 0)"
+
+				#_OFF
+				register "off_seq.ops_cnt" = "1"
+				register "off_seq.ops[0]" = "SEQ_OPS_GPIO_DISABLE(0, 0)"
+
+				device i2c 50 on
+					probe WFC WFC_MIPI
+				end
+			end
+		end # I2C1
+		device ref i2c2 on
+			chip drivers/intel/mipi_camera
+				register "acpi_hid" = ""OVTIDB10""
+				register "acpi_uid" = "0"
+				register "acpi_name" = ""CAM1""
+				register "chip_name" = ""Ov 13b10 Camera""
+				register "device_type" = "INTEL_ACPI_CAMERA_SENSOR"
+
+				register "ssdb.vcm_type" = "0x0C"
+				register "vcm_name" = ""VCM1""
+
+				register "ssdb.lanes_used" = "2"
+				register "num_freq_entries" = "1"
+				register "link_freq[0]" = "560 * MHz" # 560 MHz
+				register "remote_name" = ""IPU0""
+				register "max_dstate_for_probe" = "ACPI_DEVICE_SLEEP_D3_COLD"
+
+				register "has_power_resource" = "true"
+				#Controls
+				register "clk_panel.clks[0].clknum" = "1" # IMGCLKOUT_1
+				register "clk_panel.clks[0].freq" = "1" #19.2 Mhz
+				register "gpio_panel.gpio[0].gpio_num" = "GPP_C08" #power_enable
+				register "gpio_panel.gpio[1].gpio_num" = "GPP_E01" #reset
+
+				#_ON
+				register "on_seq.ops_cnt" = "4"
+				register "on_seq.ops[0]" = "SEQ_OPS_CLK_ENABLE(0, 0)"
+				register "on_seq.ops[1]" = "SEQ_OPS_GPIO_ENABLE(0, 2)"
+				register "on_seq.ops[2]" = "SEQ_OPS_GPIO_DISABLE(1, 1)"
+				register "on_seq.ops[3]" = "SEQ_OPS_GPIO_ENABLE(1, 1)"
+
+				#_OFF
+				register "off_seq.ops_cnt" = "3"
+				register "off_seq.ops[0]" = "SEQ_OPS_CLK_DISABLE(0, 0)"
+				register "off_seq.ops[1]" = "SEQ_OPS_GPIO_DISABLE(1, 0)"
+				register "off_seq.ops[2]" = "SEQ_OPS_GPIO_DISABLE(0, 0)"
+
+				device i2c 36 on
+					probe UFC UFC_MIPI
+				end
+			end
+			chip drivers/intel/mipi_camera
+				register "acpi_uid" = "3"
+				register "acpi_name" = ""VCM1""
+				register "chip_name" = ""DW AF VCM""
+				register "device_type" = "INTEL_ACPI_CAMERA_VCM"
+
+				register "vcm_compat" = ""dongwoon,dw9714""
+
+				register "max_dstate_for_probe" = "ACPI_DEVICE_SLEEP_D0"
+
+				register "has_power_resource" = "true"
+
+				#Controls
+				register "gpio_panel.gpio[0].gpio_num" = "GPP_C08" #power_enable
+
+				#_ON
+				register "on_seq.ops_cnt" = "1"
+				register "on_seq.ops[0]" = "SEQ_OPS_GPIO_ENABLE(0, 0)"
+
+				#_OFF
+				register "off_seq.ops_cnt" = "1"
+				register "off_seq.ops[0]" = "SEQ_OPS_GPIO_DISABLE(0, 0)"
+
+				device i2c 0C on
+					probe UFC UFC_MIPI
+				end
+			end
+			chip drivers/intel/mipi_camera
+				register "acpi_uid" = "1"
+				register "acpi_name" = ""NVM1""
+				register "chip_name" = ""BRCA016GWZ""
+				register "device_type" = "INTEL_ACPI_CAMERA_NVM"
+
+				register "nvm_compat" = ""atmel,24c16""
+
+				register "nvm_size" = "0x800"
+				register "nvm_pagesize" = "0x01"
+				register "nvm_readonly" = "0x01"
+				register "nvm_width" = "0x08"
+
+				register "max_dstate_for_probe" = "ACPI_DEVICE_SLEEP_D0"
+
+				register "has_power_resource" = "true"
+
+				#Controls
+				register "gpio_panel.gpio[0].gpio_num" = "GPP_C08" #power_enable
+
+				#_ON
+				register "on_seq.ops_cnt" = "1"
+				register "on_seq.ops[0]" = "SEQ_OPS_GPIO_ENABLE(0, 0)"
+
+				#_OFF
+				register "off_seq.ops_cnt" = "1"
+				register "off_seq.ops[0]" = "SEQ_OPS_GPIO_DISABLE(0, 0)"
+
+				device i2c 50 on
+					probe UFC UFC_MIPI
+				end
+			end
+		end # I2C2
+		device ref i2c3 on
+			chip drivers/i2c/generic
+				register "hid" = ""RTL5682""
+				register "name" = ""RT58""
+				register "desc" = ""Headset Codec""
+				register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_F17)"
+				# Set the jd_src to RT5668_JD1 for jack detection
+				register "property_count" = "1"
+				register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER"
+				register "property_list[0].name" = ""realtek,jd-src""
+				register "property_list[0].integer" = "1"
+				device i2c 1a on
+					probe AUDIO AUDIO_MAX98360_ALC5682I_I2S
+				end
+			end
+			chip drivers/i2c/tpm
+				register "hid" = ""GOOG0005""
+				register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_D15_IRQ)"
+				device i2c 50 on end
+			end
+		end # I2C3
+		device ref i2c4 on
+			chip drivers/i2c/hid
+				register "generic.hid" = ""ELAN6918""
+				register "generic.desc" = ""ELAN Touchscreen""
+				register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_E18_IRQ)"
+				register "generic.probed" = "1"
+				register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_E16)"
+				register "generic.reset_delay_ms" = "20"
+				register "generic.reset_off_delay_ms" = "2"
+				register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_F08)"
+				register "generic.enable_delay_ms" = "1"
+				register "generic.has_power_resource" = "1"
+				register "hid_desc_reg_offset" = "0x01"
+				device i2c 16 on
+					probe TOUCHSCREEN TOUCHSCREEN_LPSS_I2C
+				end
+			end
+		end # I2C4
+		device ref i2c5 on
+			chip drivers/i2c/hid
+				register "generic.hid" = ""HFW68H""
+				register "generic.desc" = ""Hynitron TOUCHPAD""
+				register "generic.irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_A13_IRQ)"
+				register "generic.wake" = "GPE0_DW0_13"
+				register "generic.uid" = "5"
+				register "generic.detect" = "1"
+				register "hid_desc_reg_offset" = "0x20"
+				device i2c 2c on
+					probe TOUCHPAD TOUCHPAD_LPSS_I2C
+				end
+			end
+		end # I2C5
+
+		device ref gspi0 on
+			chip drivers/spi/acpi
+				register "name" = ""CRFP""
+				register "hid" = "ACPI_DT_NAMESPACE_HID"
+				register "uid" = "1"
+				register "compat_string" = ""google,cros-ec-spi""
+				register "irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_D01_IRQ)"
+				register "wake" = "GPE0_DW1_01"
+				register "has_power_resource" = "true"
+				register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C15)"
+				register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E19)"
+				register "enable_delay_ms" = "3"
+				device spi 0 on
+					probe FP FP_PRESENT
+				end
+			end # FPMCU
+		end
+
+		device ref smbus on end
+		device ref npk on end
+		device ref hda on
+			chip drivers/intel/soundwire
+				device generic 0 on
+					chip drivers/soundwire/alc711
+						register "desc" = ""Headset Codec""
+						register "alc711_address.version" = "SOUNDWIRE_VERSION_1_2"
+						register "alc711_address.class" = "MIPI_CLASS_SDCA"
+						register "alc711_address.part_id" = "MIPI_DEV_ID_REALTEK_ALC722"
+						# SoundWire Link 1 ID 1
+						device generic 1.1 on
+							probe AUDIO AUDIO_ALC722_SNDW
+						end
+					end
+					chip drivers/soundwire/alc711
+						register "desc" = ""Headset Codec""
+						register "alc711_address.version" = "SOUNDWIRE_VERSION_1_2"
+						register "alc711_address.class" = "MIPI_CLASS_SDCA"
+						register "alc711_address.part_id" = "MIPI_DEV_ID_REALTEK_ALC721"
+						# SoundWire Link 3 ID 1
+						device generic 3.1 on
+							probe AUDIO AUDIO_ALC721_SNDW
+						end
+					end
+				end
+			end
+			chip drivers/generic/max98357a
+				register "hid" = ""MX98360A""
+				register "sdmode_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E19)"
+				register "sdmode_delay" = "5"
+				device generic 0 on
+					probe AUDIO AUDIO_MAX98360_ALC5682I_I2S
+				end
+			end
+		end
+		device ref soc_espi on
+			chip ec/google/chromeec
+				device pnp 0c09.0 on end
+			end
+		end
+	end
+end

From 54c87dbed07d8060f5e89391ae6ef32f87dfe5c5 Mon Sep 17 00:00:00 2001
From: John Su <john_su@compal.corp-partner.google.com>
Date: Wed, 23 Apr 2025 10:34:37 +0800
Subject: [PATCH 0859/3886] mb/google/trulo/var/uldrenite: Update DPTF
 parameters

Update the DPTF parameters as provided by thermal team.

1. Tcc_offset: 5 -> 3
2. Modify critical policy and passive policy setting

BUG=b:411866724
BRANCH=firmware-trulo-15217.771.B
TEST=build test firmware and verified by thermal team

Change-Id: Id5fda2e8c4985d41d0871454bb808a9cdfedc3e6
Signed-off-by: John Su <john_su@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87425
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
---
 .../brya/variants/uldrenite/overridetree.cb   | 24 +++++++++----------
 1 file changed, 12 insertions(+), 12 deletions(-)

diff --git a/src/mainboard/google/brya/variants/uldrenite/overridetree.cb b/src/mainboard/google/brya/variants/uldrenite/overridetree.cb
index 55e15175c7..78fec3dab2 100644
--- a/src/mainboard/google/brya/variants/uldrenite/overridetree.cb
+++ b/src/mainboard/google/brya/variants/uldrenite/overridetree.cb
@@ -30,7 +30,7 @@ chip soc/intel/alderlake
 	# DPTF enable
 	register "dptf_enable" = "true"
 
-	register "tcc_offset" = "5"     # TCC of 100
+	register "tcc_offset" = "3"
 
 	# Enable CNVi BT
 	register "cnvi_bt_core" = "true"
@@ -194,17 +194,17 @@ chip soc/intel/alderlake
 				## Passive Policy
 				register "policies.passive" = "{
 					[0] = DPTF_PASSIVE(CPU,         CPU,           95, 5000),
-					[1] = DPTF_PASSIVE(CPU,         TEMP_SENSOR_0, 90, 5000),
-					[2] = DPTF_PASSIVE(CPU,         TEMP_SENSOR_1, 90, 5000),
-					[3] = DPTF_PASSIVE(CPU,         TEMP_SENSOR_2, 90, 5000),
+					[1] = DPTF_PASSIVE(CPU,         TEMP_SENSOR_0, 85, 5000),
+					[2] = DPTF_PASSIVE(CPU,         TEMP_SENSOR_1, 85, 5000),
+					[3] = DPTF_PASSIVE(CPU,         TEMP_SENSOR_2, 85, 5000),
 				}"
 
 				## Critical Policy
 				register "policies.critical" = "{
-					[0] = DPTF_CRITICAL(CPU,               105, SHUTDOWN),
-					[1] = DPTF_CRITICAL(TEMP_SENSOR_0,     98, SHUTDOWN),
-					[2] = DPTF_CRITICAL(TEMP_SENSOR_1,     98, SHUTDOWN),
-					[3] = DPTF_CRITICAL(TEMP_SENSOR_2,     98, SHUTDOWN),
+					[0] = DPTF_CRITICAL(CPU,               130, SHUTDOWN),
+					[1] = DPTF_CRITICAL(TEMP_SENSOR_0,     105, SHUTDOWN),
+					[2] = DPTF_CRITICAL(TEMP_SENSOR_1,     105, SHUTDOWN),
+					[3] = DPTF_CRITICAL(TEMP_SENSOR_2,     105, SHUTDOWN),
 				}"
 
 				register "controls.power_limits" = "{
@@ -213,14 +213,14 @@ chip soc/intel/alderlake
 						.max_power = 10000,
 						.time_window_min = 28 * MSECS_PER_SEC,
 						.time_window_max = 28 * MSECS_PER_SEC,
-						.granularity = 500
+						.granularity = 125
 					},
 					.pl2 = {
 						.min_power = 25000,
 						.max_power = 25000,
-						.time_window_min = 32 * MSECS_PER_SEC,
-						.time_window_max = 32 * MSECS_PER_SEC,
-						.granularity = 500
+						.time_window_min = 28 * MSECS_PER_SEC,
+						.time_window_max = 28 * MSECS_PER_SEC,
+						.granularity = 1000
 					}
 				}"
 

From 22118a137b9ca0abf240ecf8e87b619ae32f0e55 Mon Sep 17 00:00:00 2001
From: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Date: Thu, 24 Apr 2025 11:52:56 +0800
Subject: [PATCH 0860/3886] mb/google/fatcat/var/kinmen: Add memory settings

Update memory settings based on the schematics.

BUG=b:406040704
TEST=emerge-fatcat coreboot

Change-Id: I8651cc15696764cf76b3ce2edee735003908b244
Signed-off-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87439
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
---
 .../google/fatcat/variants/kinmen/gpio.c      | 16 ++++++----
 .../google/fatcat/variants/kinmen/memory.c    | 29 +++++++++++++++----
 2 files changed, 34 insertions(+), 11 deletions(-)

diff --git a/src/mainboard/google/fatcat/variants/kinmen/gpio.c b/src/mainboard/google/fatcat/variants/kinmen/gpio.c
index ede819d698..6b67795410 100644
--- a/src/mainboard/google/fatcat/variants/kinmen/gpio.c
+++ b/src/mainboard/google/fatcat/variants/kinmen/gpio.c
@@ -36,6 +36,8 @@ static const struct pad_config gpio_table[] = {
 	PAD_CFG_GPO(GPP_A11, 1, PLTRST),
 	/* GPP_A12:     WIFI_WAKE_N */
 	PAD_CFG_GPI_SCI_LOW(GPP_A12, NONE, DEEP, LEVEL),
+	/* GPP_A13:     MEM_STRAP_0 */
+	PAD_CFG_GPI(GPP_A13, NONE, DEEP),
 	/* GPP_A15:     GPP_A15_DNX_FORCE_RELOAD */
 	PAD_CFG_NF(GPP_A15, NONE, DEEP, NF1),
 	/* GPP_A16:     BT_RF_KILL_N */
@@ -95,8 +97,10 @@ static const struct pad_config gpio_table[] = {
 	PAD_CFG_NF(GPP_B22, NONE, DEEP, NF4),
 	/* GPP_B23:     ISH_GP_6_SNSR_HDR */
 	PAD_CFG_NF(GPP_B23, NONE, DEEP, NF4),
-	/* GPP_B24:     ESPI_ALERT0_EC_R_N */
-	PAD_NC(GPP_B24, NONE),
+	/* GPP_B24:     MEM_STRAP_3 */
+	PAD_CFG_GPI(GPP_B24, NONE, DEEP),
+	/* GPP_B25:     MEM_STRAP_2 */
+	PAD_CFG_GPI(GPP_B25, NONE, DEEP),
 
 	/* GPP_C00:     GPP_C0_SMBCLK */
 	PAD_CFG_NF(GPP_C00, NONE, DEEP, NF1),
@@ -110,8 +114,8 @@ static const struct pad_config gpio_table[] = {
 	PAD_CFG_NF(GPP_C04, NONE, DEEP, NF1),
 	/* GPP_C06:     SML1_CLK */
 	PAD_CFG_NF(GPP_C06, NONE, DEEP, NF1),
-	/* GPP_C07:     SML1_DATA */
-	PAD_CFG_NF(GPP_C07, NONE, DEEP, NF1),
+	/* GPP_C07:     MEM_CH_SEL */
+	PAD_CFG_GPI(GPP_C07, NONE, DEEP),
 	/* GPP_C09:     CLKREQ0_X8_GEN5_DT_CEM_SLOT_N */
 	PAD_CFG_NF(GPP_C09, NONE, DEEP, NF1),
 	/* GPP_C10:     CLKREQ1_X4_GEN5_M2_SSD_N */
@@ -183,8 +187,8 @@ static const struct pad_config gpio_table[] = {
 	PAD_CFG_NF(GPP_D22, NONE, DEEP, NF1),
 	/* GPP_D23:     BPKI3C_SCL */
 	PAD_CFG_NF(GPP_D23, NONE, DEEP, NF1),
-	/* GPP_D24:     PEG_SLOT_WAKE_N */
-	PAD_CFG_GPI_SCI_LOW(GPP_D24, NONE, DEEP, LEVEL),
+	/* GPP_D24:     MEM_STRAP_1 */
+	PAD_CFG_GPI(GPP_D24, NONE, DEEP),
 	/* GPP_D25:     X4_SLOT_WAKE_N */
 	PAD_CFG_GPI_SCI_LOW(GPP_D25, NONE, DEEP, LEVEL),
 
diff --git a/src/mainboard/google/fatcat/variants/kinmen/memory.c b/src/mainboard/google/fatcat/variants/kinmen/memory.c
index e0908adabd..4637347562 100644
--- a/src/mainboard/google/fatcat/variants/kinmen/memory.c
+++ b/src/mainboard/google/fatcat/variants/kinmen/memory.c
@@ -33,8 +33,8 @@ static const struct mb_cfg lp5_mem_config = {
 			.dq1 = {  10,  9,  11,  8,  13,  14,  12,  15 },
 		},
 		.ddr6 = {
-			.dq0 = {  9,  10,  11,  8,  14,  12,  13, 15, },
-			.dq1 = {  0,  1,  2,  3,  5,  7,  4,  6 },
+			.dq0 = {  9,  8,  11,  10,  14,  12,  13, 15, },
+			.dq1 = {  6,  4,  5,  7,  1,  3,  0,  2 },
 		},
 		.ddr7 = {
 			.dq0 = {  0,  1,  2,  3,  7,  5,  6,  4, },
@@ -69,8 +69,27 @@ const struct mb_cfg *variant_memory_params(void)
 	return &lp5_mem_config;
 }
 
-void variant_get_spd_info(struct mem_spd *spd_info)
+int variant_memory_sku(void)
 {
-	spd_info->topo = MEM_TOPO_MEMORY_DOWN;
-	spd_info->cbfs_index = 0;
+	/*
+	 * Memory configuration board straps
+	 * GPIO_MEM_CONFIG_0	GPP_A13
+	 * GPIO_MEM_CONFIG_1	GPP_D24
+	 * GPIO_MEM_CONFIG_2	GPP_B25
+	 * GPIO_MEM_CONFIG_3    GPP_B24
+	 */
+	gpio_t spd_gpios[] = {
+		GPP_A13,
+		GPP_D24,
+		GPP_B25,
+		GPP_B24,
+	};
+
+	return gpio_base2_value(spd_gpios, ARRAY_SIZE(spd_gpios));
+}
+
+bool variant_is_half_populated(void)
+{
+	/* GPIO_MEM_CH_SEL GPP_C07 */
+	return gpio_get(GPP_C07);
 }

From 2170ad0c60d1fc2b95f6a174e65fd9b3110444c0 Mon Sep 17 00:00:00 2001
From: Martin Roth <gaumless@gmail.com>
Date: Sat, 12 Apr 2025 11:55:17 -0600
Subject: [PATCH 0861/3886] Documentation/lib/timestamp.md: Reformat to 72
 characters per line

Change-Id: Ifecd528dc5ee3d728104632b84a505c70ac2077b
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87291
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nicholas Chin <nic.c3.14@gmail.com>
---
 Documentation/lib/timestamp.md | 100 +++++++++++++++++----------------
 1 file changed, 53 insertions(+), 47 deletions(-)

diff --git a/Documentation/lib/timestamp.md b/Documentation/lib/timestamp.md
index a769f99098..d08d4420dd 100644
--- a/Documentation/lib/timestamp.md
+++ b/Documentation/lib/timestamp.md
@@ -2,15 +2,16 @@
 
 ## Introduction
 
-The aim of the timestamp library is to make it easier for different boards
-to  save timestamps in cbmem / stash (until cbmem is brought up) by
-providing a simple API to initialize, add and sync timestamps. In order
-to make the timestamps persistent and accessible from the kernel, we
-need to ensure that all the saved timestamps end up in cbmem under
+The aim of the timestamp library is to make it easier for different
+boards to save timestamps in cbmem / stash (until cbmem is brought up)
+by providing a simple API to initialize, add and sync timestamps. In
+order to make the timestamps persistent and accessible from the kernel,
+we need to ensure that all the saved timestamps end up in cbmem under
 the CBMEM_ID_TIMESTAMP tag. However, until the cbmem area is available,
 the timestamps can be saved to a SoC-defined \_timestamp region or in a
-local stage-specific stash. The work of identifying the right location for
-storing timestamps is done by the library and is not exposed to the user.
+local stage-specific stash. The work of identifying the right location
+for storing timestamps is done by the library and is not exposed to the
+user.
 
 Working of timestamp library from a user perspective can be outlined in
 the following steps:
@@ -18,17 +19,18 @@ the following steps:
 2. Start adding timestamps
 
 Behind the scenes, the timestamp library takes care of:
-1. Identifying the correct location for storing timestamps (cbmem or timestamp
-   region or local stash).
-2. Once cbmem is up, ensure that all timestamps are synced from timestamp
-   region or local stash into the cbmem area.
+1. Identifying the correct location for storing timestamps (cbmem or
+   timestamp region or local stash).
+2. Once cbmem is up, ensure that all timestamps are synced from
+   timestamp region or local stash into the cbmem area.
 3. Add a new cbmem timestamp area based on whether a reset of the cbmem
    timestamp region is required or not.
 
 ### Transition from cache to cbmem
 
-To move timestamps from the cache to cbmem (and initialize the cbmem area in
-the first place), we use the CBMEM_INIT_HOOK infrastructure of coreboot.
+To move timestamps from the cache to cbmem (and initialize the cbmem
+area in the first place), we use the CBMEM_INIT_HOOK infrastructure of
+coreboot.
 
 When cbmem is initialized, the hook is called, which creates the area,
 copies all timestamps to cbmem and disables the cache.
@@ -38,7 +40,8 @@ After such a transition, timestamp_init() must not be run again.
 
 ## Data structures used
 
-The main structure that maintains information about the timestamp cache is:
+The main structure that maintains information about the timestamp cache
+is:
 
 ```c
 struct __packed timestamp_cache {
@@ -50,8 +53,8 @@ struct __packed timestamp_cache {
 
 ### cache_state
 
-The state of the cache is maintained by `cache_state` attribute which can
-be any one of the following:
+The state of the cache is maintained by `cache_state` attribute which
+can be any one of the following:
 
 ```c
 enum {
@@ -61,10 +64,10 @@ enum {
 };
 ```
 
-By default, if the cache is stored in local stash (bss area), then
-it will be reset to uninitialized state. However, if the cache is
-stored in timestamp region, then it might have garbage in any of the
-attributes. Thus, if the timestamp region is being used by any board, it is
+By default, if the cache is stored in local stash (bss area), then it
+will be reset to uninitialized state. However, if the cache is stored in
+timestamp region, then it might have garbage in any of the attributes.
+Thus, if the timestamp region is being used by any board, it is
 initialized to default values by the library.
 
 Once the cache is initialized, its state is set to
@@ -72,10 +75,11 @@ Once the cache is initialized, its state is set to
 know that the state reflected is valid and timestamps can be directly
 saved in the cache.
 
-Once the cbmem area is up (i.e. call to `timestamp_sync_cache_to_cbmem`),
-we do not need to store the timestamps in local stash / timestamp area
-anymore. Thus, the cache state is set to `CACHE_NOT_NEEDED`, which allows
-`timestamp_add` to store all timestamps directly into the cbmem area.
+Once the cbmem area is up (i.e. call to
+`timestamp_sync_cache_to_cbmem`), we do not need to store the timestamps
+in local stash / timestamp area anymore. Thus, the cache state is set to
+`CACHE_NOT_NEEDED`, which allows `timestamp_add` to store all timestamps
+directly into the cbmem area.
 
 
 ### table
@@ -92,15 +96,15 @@ struct timestamp_table {
 } __packed;
 ```
 
-It indicates the base time for all timestamp entries, maximum number
-of entries that can be stored, total number of entries that currently
-exist and an entry structure to hold variable number of entries.
+It indicates the base time for all timestamp entries, maximum number of
+entries that can be stored, total number of entries that currently exist
+and an entry structure to hold variable number of entries.
 
 
 ### entries
 
-This field holds the details of each timestamp entry, up to a maximum
-of `MAX_TIMESTAMP_CACHE` which is defined as 16 entries. Each entry is
+This field holds the details of each timestamp entry, up to a maximum of
+`MAX_TIMESTAMP_CACHE` which is defined as 16 entries. Each entry is
 defined by:
 
 ```c
@@ -114,10 +118,10 @@ struct timestamp_entry {
 `entry_stamp` holds the actual timestamp.
 
 
-For timestamps stored in the cbmem area, a `timestamp_table` is allocated
-with space for `MAX_TIMESTAMPS` equal to 30. Thus, the cbmem area holds
-`base_time`, `max_entries` (which is 30), current number of entries and the
-actual entries represented by `timestamp_entry`.
+For timestamps stored in the cbmem area, a `timestamp_table` is
+allocated with space for `MAX_TIMESTAMPS` equal to 30. Thus, the cbmem
+area holds `base_time`, `max_entries` (which is 30), current number of
+entries and the actual entries represented by `timestamp_entry`.
 
 
 ## Function APIs
@@ -138,39 +142,41 @@ or `_timestamp` region or local stash.
 
 ### timestamp_add_now
 
-This function calls `timestamp_add` with user-provided id and current time.
+This function calls `timestamp_add` with user-provided id and current
+time.
 
 
 ## Use / Test Cases
 
 The following cases have been considered while designing the timestamp
-library. It is important to ensure that any changes made to this library satisfy
-each of the following use cases:
+library. It is important to ensure that any changes made to this library
+satisfy each of the following use cases:
 
 ### Case 1: Timestamp Region Exists (Fresh Boot / Resume)
 
-In this case, the library needs to call `timestamp_init` as early as possible to
-enable the timestamp cache. Once cbmem is available, the values will be
-transferred automatically.
+In this case, the library needs to call `timestamp_init` as early as
+possible to enable the timestamp cache. Once cbmem is available, the
+values will be transferred automatically.
 
 All regions are automatically reset on initialization.
 
 ### Case 2: No timestamp region, fresh boot, cbmem_initialize called after timestamp_init
 
-`timestamp_init` will set up a local cache. cbmem must be initialized before that
-cache vanishes - as happens when jumping to the next stage.
+`timestamp_init` will set up a local cache. cbmem must be initialized
+before that cache vanishes - as happens when jumping to the next stage.
 
 ### Case 3: No timestamp region, fresh boot, cbmem_initialize called before timestamp_init
 
-This case is not supported right now, just don't call `timestamp_init` after
-`cbmem_initialize`. (Patches to make this more robust are welcome.)
+This case is not supported right now, just don't call `timestamp_init`
+after `cbmem_initialize`. (Patches to make this more robust are
+welcome.)
 
 ### Case 4: No timestamp region, resume, cbmem_initialize called after timestamp_init
 
-We always reset the cbmem region before using it, so pre-suspend timestamps
-will be gone.
+We always reset the cbmem region before using it, so pre-suspend
+timestamps will be gone.
 
 ### Case 5: No timestamp region, resume, cbmem_initialize called before timestamp_init
 
-We always reset the cbmem region before using it, so pre-suspend timestamps
-will be gone.
+We always reset the cbmem region before using it, so pre-suspend
+timestamps will be gone.

From 1044f03878c30a12ebc6ce20641b4358204d2327 Mon Sep 17 00:00:00 2001
From: Patrick Rudolph <patrick.rudolph@9elements.com>
Date: Tue, 22 Apr 2025 10:48:00 +0200
Subject: [PATCH 0862/3886] payloads/external/edk2: Set StatusD register to
 work around failing AMD boot

On recent AMD platforms the VRT bit in the StatusD register is
read-writeable and set every 1024msec when RTC power is good.
This leads to a timeout in RtcWaitToUpdate() waiting for the bit
to be set and the gEfiRealTimeClockArchProtocolGuid won't be installed.
The protocol is critical to boot.

Adjust the code to not clear the VRT bit, as RtcWaitToUpdate() will
return an error, as it assumes the VRT bit is read-only and hardwired
to one as on Intel ICHs. While the timeout could be increased it
would also increase boot time by up to a second.

On platforms where the VRT bit is read-only the introduced code
does the same as before.

Change-Id: I8bc432114c83fa5f5fb35a144e3a35c38ee8a3de
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87415
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
---
 payloads/external/Makefile.mk   | 1 +
 payloads/external/edk2/Makefile | 6 ++++++
 2 files changed, 7 insertions(+)

diff --git a/payloads/external/Makefile.mk b/payloads/external/Makefile.mk
index 5e8c91fbb5..655e14df03 100644
--- a/payloads/external/Makefile.mk
+++ b/payloads/external/Makefile.mk
@@ -199,6 +199,7 @@ $(obj)/UEFIPAYLOAD.fd: $(DOTCONFIG)
 		CONFIG_EDK2_UFS_ENABLE=$(CONFIG_EDK2_UFS_ENABLE) \
 		CONFIG_EDK2_PCO_MMIO_EMMC=$(CONFIG_EDK2_PCO_MMIO_EMMC) \
 		CONFIG_EDK2_USE_LAPIC_TIMER=$(CONFIG_EDK2_USE_LAPIC_TIMER) \
+		CONFIG_SOC_AMD_COMMON_BLOCK_PSP_GEN2=$(CONFIG_SOC_AMD_COMMON_BLOCK_PSP_GEN2) \
 		GCC_CC_x86_32=$(GCC_CC_x86_32) \
 		GCC_CC_x86_64=$(GCC_CC_x86_64) \
 		GCC_CC_arm=$(GCC_CC_arm) \
diff --git a/payloads/external/edk2/Makefile b/payloads/external/edk2/Makefile
index 0908f4d26c..358c8c6125 100644
--- a/payloads/external/edk2/Makefile
+++ b/payloads/external/edk2/Makefile
@@ -115,6 +115,12 @@ endif
 ifeq ($(CONFIG_PCIEXP_SUPPORT_RESIZABLE_BARS), y)
 BUILD_STR += --pcd gEfiMdeModulePkgTokenSpaceGuid.PcdPcieResizableBarSupport=TRUE
 endif
+# Preserve VRT bit in RTC_ADDRESS_REGISTER_D
+# AMD SoC sets this every 1.024msec, but the generic code assumes it's read-only and
+# hardcoded to 1 like on every Intel chipset since Intel ICH.
+ifeq ($(CONFIG_SOC_AMD_COMMON_BLOCK_PSP_GEN2), y)
+BUILD_STR += --pcd gPcAtChipsetPkgTokenSpaceGuid.PcdInitialValueRtcRegisterD=0x80
+endif
 
 #
 # The MrChromebox repository has the following addition options:

From effd1ffdad73e23e23ffbab8fbd0f7de052126ff Mon Sep 17 00:00:00 2001
From: Avi Uday <aviuday@google.com>
Date: Thu, 17 Apr 2025 17:34:12 +0530
Subject: [PATCH 0863/3886] mb/google/ocelot: Update Ocelot board

Syncing ocelot code to fatcat so that it has the recent changes made to fatcat. This is done by manually copying the fatcat code, similar to https://review.coreboot.org/c/coreboot/+/86692

List of commits -
86702: mb/google/fatcat/var/fatcat: Update GSPI0 CS pin for FPS | https://review.coreboot.org/c/coreboot/+/86702
86479: mb/google/fatcat/var/fatcat: Update THC Interrupt for Touchpad Development | https://review.coreboot.org/c/coreboot/+/86479
86938: mb/google/fatcat/var/fatcat: Add Write Protect GPIO to cros_gpios | https://review.coreboot.org/c/coreboot/+/86938
86981: mb/google/fatcat: Implement S0ix hooks aka `MS0X` method | https://review.coreboot.org/c/coreboot/+/86981
85662: mb/google/fatcat: Rationalize Wi-Fi and Bluetooth combinations | https://review.coreboot.org/c/coreboot/+/85662
87089: mb/google/fatcat: Allow board-specific FSP-M UPD override | https://review.coreboot.org/c/coreboot/+/87089
87090: mb/google/fatcat: Enable HDA SDI based on FW config | https://review.coreboot.org/c/coreboot/+/87090
85200: mb/google/fatcat: Add Intel Touch support for touchscreen and touchpad | https://review.coreboot.org/c/coreboot/+/85200
87154: mb/google/fatcat/variants/fatcat: Refactor X1 PCIe power enable GPIO | https://review.coreboot.org/c/coreboot/+/87154
87191: mb/google/fatcat: Perform early post-memory GPIO configuration | https://review.coreboot.org/c/coreboot/+/87191
87183: mb/google/fatcat: Introduce variant-specific barrel jack presence check | https://review.coreboot.org/c/coreboot/+/87183
87207: mb/google/fatcat/var/fatcat: Implement barrel jack presence check | https://review.coreboot.org/c/coreboot/+/87207
87236: mb/google/fatcat: Enable FSP_UGOP_EARLY_SIGN_OF_LIFE | https://review.coreboot.org/c/coreboot/+/87236

BUG=b:412736286
BRANCH=None
TEST=Build AP firmware image.

Change-Id: Icb8ec9ff26abd71931e0689f94ea6af260f7618c
Signed-off-by: Avi Uday <aviuday@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87351
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
---
 src/mainboard/google/ocelot/Kconfig           |  4 +-
 src/mainboard/google/ocelot/mainboard.c       | 37 ++++++++-
 src/mainboard/google/ocelot/romstage.c        |  9 ++
 .../baseboard/include/baseboard/variants.h    |  3 +
 .../variants/baseboard/ocelot/devicetree.cb   |  1 -
 .../baseboard/ocelot/include/baseboard/gpio.h |  1 +
 .../variants/baseboard/ocelot/ramstage.c      | 14 +++-
 .../google/ocelot/variants/ocelot/Makefile.mk |  1 +
 .../google/ocelot/variants/ocelot/fw_config.c | 83 +++++++++++++------
 .../google/ocelot/variants/ocelot/gpio.c      | 10 ++-
 .../ocelot/variants/ocelot/overridetree.cb    | 76 ++++++++++++++++-
 .../google/ocelot/variants/ocelot/variant.c   | 69 ++++++++++++++-
 12 files changed, 266 insertions(+), 42 deletions(-)

diff --git a/src/mainboard/google/ocelot/Kconfig b/src/mainboard/google/ocelot/Kconfig
index 7060929fc7..a4b042235c 100644
--- a/src/mainboard/google/ocelot/Kconfig
+++ b/src/mainboard/google/ocelot/Kconfig
@@ -60,8 +60,8 @@ config BOARD_GOOGLE_OCELOT
 	select BOARD_GOOGLE_BASEBOARD_OCELOT
 	select DRIVERS_GENERIC_BAYHUB_LV2
 	select DRIVERS_GENERIC_MAX98357A
-	select EC_GOOGLE_CHROMEEC_MEC
-	select MAINBOARD_USES_IFD_EC_REGION
+	select DRIVERS_INTEL_TOUCH
+	select FSP_UGOP_EARLY_SIGN_OF_LIFE
 
 if BOARD_GOOGLE_OCELOT_COMMON
 
diff --git a/src/mainboard/google/ocelot/mainboard.c b/src/mainboard/google/ocelot/mainboard.c
index f514eb96d1..5bd9892480 100644
--- a/src/mainboard/google/ocelot/mainboard.c
+++ b/src/mainboard/google/ocelot/mainboard.c
@@ -4,6 +4,7 @@
 #include <acpi/acpigen.h>
 #include <baseboard/gpio.h>
 #include <baseboard/variants.h>
+#include <bootstate.h>
 #include <device/device.h>
 #include <ec/ec.h>
 #include <soc/ramstage.h>
@@ -26,6 +27,12 @@ void __weak variant_update_soc_chip_config(struct soc_intel_pantherlake_config *
 }
 
 static void mainboard_init(void *chip_info)
+{
+	baseboard_devtree_update();
+}
+
+/* Must happen before MPinit */
+static void mainboard_early(void *unused)
 {
 	struct pad_config *padbased_table;
 	const struct pad_config *base_pads;
@@ -37,9 +44,10 @@ static void mainboard_init(void *chip_info)
 	fw_config_gpio_padbased_override(padbased_table);
 	gpio_configure_pads_with_padbased(padbased_table);
 	free(padbased_table);
-	baseboard_devtree_update();
 }
 
+BOOT_STATE_INIT_ENTRY(BS_PRE_DEVICE, BS_ON_EXIT, mainboard_early, NULL);
+
 void __weak baseboard_devtree_update(void)
 {
 	/* Override dev tree settings per baseboard */
@@ -58,6 +66,32 @@ void __weak variant_generate_s0ix_hook(enum s0ix_entry entry)
 	 */
 }
 
+static void mainboard_generate_s0ix_hook(void)
+{
+	acpigen_write_if_lequal_op_int(ARG0_OP, 1);
+	{
+		if (CONFIG(HAVE_SLP_S0_GATE))
+			acpigen_soc_clear_tx_gpio(GPIO_SLP_S0_GATE);
+		variant_generate_s0ix_hook(S0IX_ENTRY);
+	}
+	acpigen_write_else();
+	{
+		if (CONFIG(HAVE_SLP_S0_GATE))
+			acpigen_soc_set_tx_gpio(GPIO_SLP_S0_GATE);
+		variant_generate_s0ix_hook(S0IX_EXIT);
+	}
+	acpigen_write_if_end();
+}
+
+static void mainboard_fill_ssdt(const struct device *dev)
+{
+	acpigen_write_scope("\\_SB");
+	acpigen_write_method_serialized("MS0X", 1);
+	mainboard_generate_s0ix_hook();
+	acpigen_write_method_end(); /* Method */
+	acpigen_write_scope_end(); /* Scope */
+}
+
 static void mainboard_dev_init(struct device *dev)
 {
 	mainboard_ec_init();
@@ -66,6 +100,7 @@ static void mainboard_dev_init(struct device *dev)
 static void mainboard_enable(struct device *dev)
 {
 	dev->ops->init = mainboard_dev_init;
+	dev->ops->acpi_fill_ssdt = mainboard_fill_ssdt;
 }
 
 struct chip_operations mainboard_ops = {
diff --git a/src/mainboard/google/ocelot/romstage.c b/src/mainboard/google/ocelot/romstage.c
index 7b56e28e3c..8f0000c2ce 100644
--- a/src/mainboard/google/ocelot/romstage.c
+++ b/src/mainboard/google/ocelot/romstage.c
@@ -3,6 +3,7 @@
 #include <baseboard/variants.h>
 #include <fsp/api.h>
 #include <soc/romstage.h>
+#include <soc/soc_chip.h>
 #include <string.h>
 
 /*
@@ -16,6 +17,11 @@ __weak void fw_config_configure_pre_mem_gpio(void)
 	/* Nothing to do */
 }
 
+__weak void variant_update_soc_memory_init_params(FSPM_UPD *memupd)
+{
+	/* Nothing to do */
+}
+
 void mainboard_memory_init_params(FSPM_UPD *memupd)
 {
 	const struct pad_config *pads;
@@ -33,4 +39,7 @@ void mainboard_memory_init_params(FSPM_UPD *memupd)
 	variant_get_spd_info(&spd_info);
 
 	memcfg_init(memupd, mem_config, &spd_info, half_populated);
+
+	/* Override FSP-M UPD per board if required. */
+	variant_update_soc_memory_init_params(memupd);
 }
diff --git a/src/mainboard/google/ocelot/variants/baseboard/include/baseboard/variants.h b/src/mainboard/google/ocelot/variants/baseboard/include/baseboard/variants.h
index 2a70408e0d..ad26ab8a67 100644
--- a/src/mainboard/google/ocelot/variants/baseboard/include/baseboard/variants.h
+++ b/src/mainboard/google/ocelot/variants/baseboard/include/baseboard/variants.h
@@ -4,6 +4,7 @@
 #define __BASEBOARD_VARIANTS_H__
 
 #include <chip.h>
+#include <fsp/api.h>
 #include <soc/gpio.h>
 #include <soc/meminit.h>
 #include <stdint.h>
@@ -23,7 +24,9 @@ const struct mb_cfg *variant_memory_params(void);
 void variant_get_spd_info(struct mem_spd *spd_info);
 int variant_memory_sku(void);
 bool variant_is_half_populated(void);
+void variant_update_soc_memory_init_params(FSPM_UPD *memupd);
 void variant_update_soc_chip_config(struct soc_intel_pantherlake_config *config);
+bool variant_is_barrel_charger_present(void);
 
 enum s0ix_entry {
 	S0IX_EXIT,
diff --git a/src/mainboard/google/ocelot/variants/baseboard/ocelot/devicetree.cb b/src/mainboard/google/ocelot/variants/baseboard/ocelot/devicetree.cb
index 8bfe819b7c..1ac4027eec 100644
--- a/src/mainboard/google/ocelot/variants/baseboard/ocelot/devicetree.cb
+++ b/src/mainboard/google/ocelot/variants/baseboard/ocelot/devicetree.cb
@@ -81,7 +81,6 @@ chip soc/intel/pantherlake
 	register "pch_hda_idisp_link_tmode" = "HDA_TMODE_8T"
 	register "pch_hda_idisp_link_frequency" = "HDA_LINKFREQ_96MHZ"
 	register "pch_hda_idisp_codec_enable" = "true"
-	register "pch_hda_sdi_enable" = "{ true, false }"
 
 	device domain 0 on
 		device ref dtt on end
diff --git a/src/mainboard/google/ocelot/variants/baseboard/ocelot/include/baseboard/gpio.h b/src/mainboard/google/ocelot/variants/baseboard/ocelot/include/baseboard/gpio.h
index 56c2fb0aca..2cc9e7407a 100644
--- a/src/mainboard/google/ocelot/variants/baseboard/ocelot/include/baseboard/gpio.h
+++ b/src/mainboard/google/ocelot/variants/baseboard/ocelot/include/baseboard/gpio.h
@@ -17,5 +17,6 @@
  #define EC_SYNC_IRQ	0 /* Not Connected */
 #endif
 #define GPIO_PCH_WP	GPP_D02
+#define GPIO_SLP_S0_GATE	0 /* Not Connected */
 
 #endif /* __BASEBOARD_GPIO_H__ */
diff --git a/src/mainboard/google/ocelot/variants/baseboard/ocelot/ramstage.c b/src/mainboard/google/ocelot/variants/baseboard/ocelot/ramstage.c
index 030b587579..69d0d67cd0 100644
--- a/src/mainboard/google/ocelot/variants/baseboard/ocelot/ramstage.c
+++ b/src/mainboard/google/ocelot/variants/baseboard/ocelot/ramstage.c
@@ -50,10 +50,22 @@ const struct cpu_tdp_power_limits power_optimized_limits[] = {
 	},
 };
 
+/*
+ * Placeholder to check if variant has support for barrel jack for powering
+ * on the device.
+ *
+ * Most of the chromebook device is powering on with USB-C hence, unless overridden
+ * by some variant, assume barrel jack not present.
+ */
+__weak bool variant_is_barrel_charger_present(void)
+{
+	return false;
+}
+
 void baseboard_devtree_update(void)
 {
 	/* Don't optimize the power limit if booting with barrel attached */
-	if (google_chromeec_is_barrel_charger_present())
+	if (variant_is_barrel_charger_present())
 		return;
 
 	if (!google_chromeec_is_battery_present())
diff --git a/src/mainboard/google/ocelot/variants/ocelot/Makefile.mk b/src/mainboard/google/ocelot/variants/ocelot/Makefile.mk
index eb361dfe89..3fdd4642c0 100644
--- a/src/mainboard/google/ocelot/variants/ocelot/Makefile.mk
+++ b/src/mainboard/google/ocelot/variants/ocelot/Makefile.mk
@@ -5,5 +5,6 @@ romstage-y += gpio.c
 romstage-y += memory.c
 romstage-$(CONFIG_FW_CONFIG) += fw_config.c
 ramstage-y += gpio.c
+romstage-$(CONFIG_FW_CONFIG) += variant.c
 ramstage-$(CONFIG_FW_CONFIG) += variant.c
 ramstage-$(CONFIG_FW_CONFIG) += fw_config.c
diff --git a/src/mainboard/google/ocelot/variants/ocelot/fw_config.c b/src/mainboard/google/ocelot/variants/ocelot/fw_config.c
index fd29768aa6..511ec7e421 100644
--- a/src/mainboard/google/ocelot/variants/ocelot/fw_config.c
+++ b/src/mainboard/google/ocelot/variants/ocelot/fw_config.c
@@ -111,10 +111,6 @@ static const struct pad_config audio_disable_pads[] = {
 	PAD_NC(GPP_D17, NONE),
 };
 
-static const struct pad_config pre_mem_x1slot_pads[] = {
-	/* GPP_A08:     X1_PCIE_SLOT_PWR_EN */
-	PAD_CFG_GPO(GPP_A08, 0, PLTRST),
-};
 static const struct pad_config x1slot_pads[] = {
 	/* GPP_A08:     X1_PCIE_SLOT_PWR_EN */
 	PAD_CFG_GPO(GPP_A08, 1, PLTRST),
@@ -297,6 +293,8 @@ static const struct pad_config touchscreen_disable_pads[] = {
 	PAD_NC(GPP_E17, NONE),
 	/* GPP_E18:     THC0_SPI1_INT_N_TCH_PNL1 */
 	PAD_NC(GPP_E18, NONE),
+	/* GPP_VGPIO3_THC0: THC0_WOT */
+	PAD_NC(GPP_VGPIO3_THC0, NONE),
 };
 
 static const struct pad_config touchscreen_thc_i2c_enable_pads[] = {
@@ -315,7 +313,10 @@ static const struct pad_config touchscreen_thc_i2c_enable_pads[] = {
 	/* GPP_E17:     THC0_SPI1_CS0_N_TCH_PNL1 */
 	PAD_NC(GPP_E17, NONE),
 	/* GPP_E18:     THC0_SPI1_INT_N_TCH_PNL1 */
-	PAD_CFG_GPI_APIC(GPP_E18, NONE, PLTRST, LEVEL, NONE),
+	/* NOTE: this SPI INT NF is also used in THC-I2C mode */
+	PAD_CFG_NF(GPP_E18, NONE, DEEP, NF3),
+	/* GPP_VGPIO3_THC0: THC0_WOT */
+	PAD_NC(GPP_VGPIO3_THC0, NONE),
 };
 
 static const struct pad_config touchscreen_thc_spi_enable_pads[] = {
@@ -336,13 +337,21 @@ static const struct pad_config touchscreen_thc_spi_enable_pads[] = {
 	PAD_CFG_NF(GPP_E17, NONE, DEEP, NF3),
 	/* GPP_E18:     THC0_SPI1_INT_N_TCH_PNL1 NF3: THC HID-SPI */
 	PAD_CFG_NF(GPP_E18, NONE, DEEP, NF3),
+	/* GPP_VGPIO3_THC0: THC0_WOT */
+	PAD_NC(GPP_VGPIO3_THC0, NONE),
 };
 
 static const struct pad_config touchpad_thc_i2c_enable_pads[] = {
-	/* GPP_F12:     NF1: thc_i2c1_scl */
+	/* GPP_F12:     NF1: THC_I2C1_SCL */
 	PAD_CFG_NF(GPP_F12, NONE, DEEP, NF1),
-	/* GPP_F13:     NF1: thc_i2c1_sda */
+	/* GPP_F13:     NF1: THC_I2C1_SDA */
 	PAD_CFG_NF(GPP_F13, NONE, DEEP, NF1),
+	/* GPP_F18:     TCH_PAD_INT_N */
+	/* NOTE: this SPI INT NF is also used in THC-I2C mode */
+	/* NOTE: require rework to switch from GPP_A13 to GPP_F18 */
+	PAD_CFG_NF(GPP_F18, NONE, DEEP, NF3),
+	/* GPP_VGPIO3_THC1: THC1_WOT */
+	PAD_NC(GPP_VGPIO3_THC1, NONE),
 };
 
 static const struct pad_config touchpad_lpss_i2c_enable_pads[] = {
@@ -350,8 +359,11 @@ static const struct pad_config touchpad_lpss_i2c_enable_pads[] = {
 	PAD_CFG_NF(GPP_F12, NONE, DEEP, NF8),
 	/* GPP_F13:     THC_I2C1_SDA_TCH_PAD */
 	PAD_CFG_NF(GPP_F13, NONE, DEEP, NF8),
-	/* GPP_A13:     TCH_PAD_INT_N */
-	PAD_CFG_GPI_IRQ_WAKE(GPP_A13, NONE, PWROK, EDGE_SINGLE, INVERT),
+	/* GPP_F18:     TCH_PAD_INT_N */
+	/* NOTE: require rework to switch from GPP_A13 to GPP_F18 */
+	PAD_CFG_GPI_APIC(GPP_F18, NONE, PLTRST, LEVEL, INVERT),
+	/* GPP_VGPIO3_THC1: THC1_WOT */
+	PAD_NC(GPP_VGPIO3_THC1, NONE),
 };
 
 static const struct pad_config touchpad_i2c_disable_pads[] = {
@@ -359,8 +371,21 @@ static const struct pad_config touchpad_i2c_disable_pads[] = {
 	PAD_NC(GPP_F12, NONE),
 	/* GPP_F13:     THC_I2C1_SDA_TCH_PAD */
 	PAD_NC(GPP_F13, NONE),
-	/* GPP_A13:     TCH_PAD_INT_N */
-	PAD_NC(GPP_A13, NONE),
+	/* GPP_F18:     TCH_PAD_INT_N */
+	/* NOTE: require rework to switch from GPP_A13 to GPP_F18 */
+	PAD_NC(GPP_F18, NONE),
+	/* GPP_VGPIO3_THC1: THC1_WOT */
+	PAD_NC(GPP_VGPIO3_THC1, NONE),
+};
+
+static const struct pad_config thc0_enable_wake[] = {
+	/* GPP_VGPIO3_THC0: THC0_WOT */
+	PAD_CFG_GPI_APIC_DRIVER(GPP_VGPIO3_THC0, NONE, PLTRST, LEVEL, NONE),
+};
+
+static const struct pad_config thc1_enable_wake[] = {
+	/* GPP_VGPIO3_THC1: THC1_WOT */
+	PAD_CFG_GPI_APIC_DRIVER(GPP_VGPIO3_THC1, NONE, PLTRST, LEVEL, NONE),
 };
 
 static const struct pad_config ish_disable_pads[] = {
@@ -385,6 +410,7 @@ static const struct pad_config fp_disable_pads[] = {
 	PAD_NC(GPP_C15, NONE),
 	/* GPP_D01:     MOD_TCSS1_TYP_A_VBUS_EN */
 	PAD_CFG_GPO(GPP_D01, 1, DEEP),
+	PAD_NC(GPP_E17, NONE),
 	/* FIXME: b/390031369
 	 * use dedicated GPIO PIN for codec enable
 	 * when FPS is enabled.
@@ -395,7 +421,6 @@ static const struct pad_config fp_disable_pads[] = {
 	PAD_NC(GPP_F14, NONE),
 	PAD_NC(GPP_F15, NONE),
 	PAD_NC(GPP_F16, NONE),
-	PAD_NC(GPP_F18, NONE),
 };
 
 static const struct pad_config fp_enable_pads[] = {
@@ -403,6 +428,8 @@ static const struct pad_config fp_enable_pads[] = {
 	PAD_CFG_GPO_LOCK(GPP_C15, 1, LOCK_CONFIG),
 	/* GPP_D01:     FPS_SOC_INT_L */
 	PAD_CFG_GPI_IRQ_WAKE(GPP_D01, NONE, PWROK, LEVEL, INVERT),
+	/* GPP_E17:     GSPI0A_CS0 */
+	PAD_CFG_NF(GPP_E17, NONE, DEEP, NF5),
 	/* GPP_E19:     FPMCU_PWREN */
 	PAD_CFG_GPO(GPP_E19, 1, DEEP),
 	/* GPP_E20:     FPMCU_FW_UPDATE */
@@ -413,8 +440,6 @@ static const struct pad_config fp_enable_pads[] = {
 	PAD_CFG_NF(GPP_F15, NONE, DEEP, NF8),
 	/* GPP_F16:     GPSI0A_CLK */
 	PAD_CFG_NF(GPP_F16, NONE, DEEP, NF8),
-	/* GPP_F18:     GSPI0A_CS0 */
-	PAD_CFG_NF(GPP_F18, NONE, DEEP, NF8),
 };
 
 static const struct pad_config pre_mem_fp_enable_pads[] = {
@@ -441,9 +466,6 @@ void fw_config_configure_pre_mem_gpio(void)
 		GPIO_CONFIGURE_PADS(pre_mem_gen5_ssd_pwr_pads);
 	}
 
-	if (!fw_config_probe(FW_CONFIG(SD, SD_NONE)))
-		GPIO_CONFIGURE_PADS(pre_mem_x1slot_pads);
-
 	/*
 	 * NOTE: We place WWAN sequence 2 here. According to the WWAN FIBOCOM
 	 * FM350-GL datasheet, the minimum time requirement (Tpr: time between 3.3V
@@ -464,6 +486,8 @@ void fw_config_configure_pre_mem_gpio(void)
 
 void fw_config_gpio_padbased_override(struct pad_config *padbased_table)
 {
+	const struct soc_intel_pantherlake_config *config = config_of_soc();
+
 	if (!fw_config_is_provisioned()) {
 		printk(BIOS_WARNING, "FW_CONFIG is not provisioned, Exiting\n");
 		return;
@@ -517,19 +541,25 @@ void fw_config_gpio_padbased_override(struct pad_config *padbased_table)
 	else
 		GPIO_PADBASED_OVERRIDE(padbased_table, x1slot_pads);
 
-	if (fw_config_probe(FW_CONFIG(TOUCHPAD, TOUCHPAD_LPSS_I2C)))
+	if (fw_config_probe(FW_CONFIG(TOUCHPAD, TOUCHPAD_LPSS_I2C))) {
 		GPIO_PADBASED_OVERRIDE(padbased_table, touchpad_lpss_i2c_enable_pads);
-	else if (fw_config_probe(FW_CONFIG(TOUCHPAD, TOUCHPAD_THC_I2C)))
+	} else if (fw_config_probe(FW_CONFIG(TOUCHPAD, TOUCHPAD_THC_I2C))) {
 		GPIO_PADBASED_OVERRIDE(padbased_table, touchpad_thc_i2c_enable_pads);
-	else
+		if (config->thc_wake_on_touch[1])
+			GPIO_PADBASED_OVERRIDE(padbased_table, thc1_enable_wake);
+	} else {
 		GPIO_PADBASED_OVERRIDE(padbased_table, touchpad_i2c_disable_pads);
+	}
 
 	if (fw_config_probe(FW_CONFIG(TOUCHSCREEN, TOUCHSCREEN_THC_I2C)))
 		GPIO_PADBASED_OVERRIDE(padbased_table, touchscreen_thc_i2c_enable_pads);
-	else if (fw_config_probe(FW_CONFIG(TOUCHSCREEN, TOUCHSCREEN_THC_SPI)))
+	else if (fw_config_probe(FW_CONFIG(TOUCHSCREEN, TOUCHSCREEN_THC_SPI))) {
 		GPIO_PADBASED_OVERRIDE(padbased_table, touchscreen_thc_spi_enable_pads);
-	else
+		if (config->thc_wake_on_touch[0])
+			GPIO_PADBASED_OVERRIDE(padbased_table, thc0_enable_wake);
+	} else {
 		GPIO_PADBASED_OVERRIDE(padbased_table, touchscreen_disable_pads);
+	}
 
 	if (fw_config_probe(FW_CONFIG(ISH, ISH_DISABLE)))
 		GPIO_PADBASED_OVERRIDE(padbased_table, ish_disable_pads);
@@ -539,8 +569,9 @@ void fw_config_gpio_padbased_override(struct pad_config *padbased_table)
 	/* NOTE: disable PEG (x8 slot) and x4 slot wake for now */
 	GPIO_PADBASED_OVERRIDE(padbased_table, peg_x4slot_wake_disable_pads);
 
-	if (fw_config_probe(FW_CONFIG(FP, FP_PRESENT)))
-		GPIO_CONFIGURE_PADS(fp_enable_pads);
-	else
-		GPIO_CONFIGURE_PADS(fp_disable_pads);
+	if (fw_config_probe(FW_CONFIG(FP, FP_PRESENT))) {
+		GPIO_PADBASED_OVERRIDE(padbased_table, fp_enable_pads);
+	} else {
+		GPIO_PADBASED_OVERRIDE(padbased_table, fp_disable_pads);
+	}
 }
diff --git a/src/mainboard/google/ocelot/variants/ocelot/gpio.c b/src/mainboard/google/ocelot/variants/ocelot/gpio.c
index 945cda97be..c22de38f2f 100644
--- a/src/mainboard/google/ocelot/variants/ocelot/gpio.c
+++ b/src/mainboard/google/ocelot/variants/ocelot/gpio.c
@@ -198,8 +198,6 @@ static const struct pad_config gpio_table[] = {
 	PAD_NC(GPP_E15, NONE),
 	/* GPP_E16:     NC */
 	PAD_NC(GPP_E16, NONE),
-	/* GPP_E17:     SPI_SOC_CS_FP_R_L */
-	PAD_CFG_NF(GPP_E17, NONE, DEEP, NF5),
 	/* GPP_E18:     SOC_TCHPAD_INT_ODL */
 	PAD_CFG_NF(GPP_E18, NONE, DEEP, NF3),
 	/* GPP_E19:     FP_SOC_INT_L */
@@ -247,8 +245,9 @@ static const struct pad_config gpio_table[] = {
 	PAD_CFG_NF(GPP_F16, NONE, DEEP, NF3),
 	/* GPP_F17:     SPI_THCSCR_CS_L */
 	PAD_CFG_NF(GPP_F17, NONE, DEEP, NF3),
-	/* GPP_F18:     TCHSCR_INT_ODL */
-	PAD_CFG_NF(GPP_F18, NONE, DEEP, NF3),
+	/* GPP_F18:     TCH_PAD_INT_N */
+	/* NOTE: require rework to switch from GPP_A13 to GPP_F18 */
+	PAD_CFG_GPI_APIC(GPP_F18, NONE, PLTRST, LEVEL, INVERT),
 	/* GPP_F19:     GPP_F19_STRAP */
 	PAD_NC(GPP_F19, NONE),
 	/* GPP_F20:     EC_SOC_REC_SWITCH_ODL */
@@ -390,6 +389,8 @@ static const struct pad_config early_gpio_table[] = {
 
 /* Pad configuration in romstage */
 static const struct pad_config romstage_gpio_table[] = {
+	/* GPP_A08:     X1_PCIE_SLOT_PWR_EN */
+	PAD_CFG_GPO(GPP_A08, 0, PLTRST),
 };
 
 const struct pad_config *variant_gpio_table(size_t *num)
@@ -416,6 +417,7 @@ static const struct cros_gpio cros_gpios[] = {
 	CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE1_NAME),
 	CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE2_NAME),
 	CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE3_NAME),
+	CROS_GPIO_WP_AH(GPIO_PCH_WP, CROS_GPIO_DEVICE4_NAME),
 };
 
 DECLARE_CROS_GPIOS(cros_gpios);
diff --git a/src/mainboard/google/ocelot/variants/ocelot/overridetree.cb b/src/mainboard/google/ocelot/variants/ocelot/overridetree.cb
index 6b99983b7c..30daba5572 100644
--- a/src/mainboard/google/ocelot/variants/ocelot/overridetree.cb
+++ b/src/mainboard/google/ocelot/variants/ocelot/overridetree.cb
@@ -54,6 +54,10 @@ fw_config
 		option KB_ABSENT		0
 		option KB_PRESENT		1
 	end
+	field PSU 20
+		option PSU_USBC			0
+		option PSU_BJ			1
+	end
 end
 
 chip soc/intel/pantherlake
@@ -64,7 +68,7 @@ chip soc/intel/pantherlake
 	register "usb2_ports[3]" = "USB2_PORT_TYPE_C(OC_SKIP)" # USB2_C3
 	register "usb2_ports[4]" = "USB2_PORT_MID(OC0)" # Type-A Port A0
 	register "usb2_ports[5]" = "USB2_PORT_MID(OC0)" # Type-A Port A1 / WWAN with rework
-	register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # CNVi BT or discrete BT
+	register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # Discrete Bluetooth
 
 	register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)" # USB3.2 x1 Type-A Con #1
 	register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC0)" # USB3.2 x1 Type-A Con #2 / M.2 WWAN with rework
@@ -288,13 +292,66 @@ chip soc/intel/pantherlake
 		device ref iaa off end
 
 		device ref thc0 on
+			register "thc_wake_on_touch[0]" = "true"
 			probe TOUCHSCREEN TOUCHSCREEN_THC_SPI
 			probe TOUCHSCREEN TOUCHSCREEN_THC_I2C
 			# THC0 is function 0; hence it needs to be enabled when THC1 is to be enabled.
 			probe TOUCHPAD TOUCHPAD_THC_I2C
+			chip drivers/intel/touch
+				register "name" = "INTEL_THC0_NAME"
+				register "mode" = "THC_HID_I2C_MODE"
+				register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_F08)"
+				register "enable_delay_ms" = "2"
+				register "enable_off_delay_ms" = "2"
+				register "wake_on_touch" = "true"
+				# NOTE: Use GpioInt() in _CRS and does not use GPE.
+				register "wake_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW_WAKE(GPP_VGPIO3_THC0)"
+				register "active_ltr" = "1"
+				register "idle_ltr" = "0"
+				register "connected_device" = "TH_SENSOR_ELAN"
+				register "add_acpi_dma_property" = "true"
+				device generic 0 alias touch_0_i2c_elan on
+					probe TOUCHSCREEN TOUCHSCREEN_THC_I2C
+				end
+			end
+			chip drivers/intel/touch
+				register "name" = "INTEL_THC0_NAME"
+				register "mode" = "THC_HID_SPI_MODE"
+				register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_F08)"
+				register "enable_delay_ms" = "2"
+				register "enable_off_delay_ms" = "2"
+				register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_E16)"
+				register "reset_delay_ms" = "10"
+				register "reset_off_delay_ms" = "2"
+				register "wake_on_touch" = "true"
+				# NOTE: Use GpioInt() in _CRS and does not use GPE.
+				register "wake_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW_WAKE(GPP_VGPIO3_THC0)"
+				register "active_ltr" = "1"
+				register "idle_ltr" = "0"
+				register "connected_device" = "TH_SENSOR_ELAN"
+				register "soc_hidspi.write_mode" = "HIDSPI_WRITE_MODE_MULTI_SINGLE_SPI"
+				register "soc_hidspi.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_E16)"
+				register "add_acpi_dma_property" = "true"
+				device generic 0 alias touch_0_spi_elan on
+					probe TOUCHSCREEN TOUCHSCREEN_THC_SPI
+				end
+			end
 		end
 		device ref thc1 on
+			register "thc_wake_on_touch[1]" = "true"
 			probe TOUCHPAD TOUCHPAD_THC_I2C
+			chip drivers/intel/touch
+				register "name" = "INTEL_THC1_NAME"
+				register "mode" = "THC_HID_I2C_MODE"
+				register "wake_on_touch" = "true"
+				# NOTE: Use GpioInt() in _CRS and does not use GPE.
+				register "wake_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW_WAKE(GPP_VGPIO3_THC1)"
+				register "active_ltr" = "1"
+				register "idle_ltr" = "0"
+				register "connected_device" = "TH_SENSOR_HYNITRON"
+				register "add_acpi_dma_property" = "true"
+				device generic 0 alias touch_1_i2c_hynitron on end
+			end
 		end
 
 		device ref tbt_pcie_rp0 on end
@@ -415,7 +472,10 @@ chip soc/intel/pantherlake
 						register "desc" = ""USB2 Bluetooth""
 						register "type" = "UPC_TYPE_INTERNAL"
 						register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A16)"
-						device ref usb2_port8 on end
+						device ref usb2_port8 on
+							probe WIFI WIFI_PCIE_6
+							probe WIFI WIFI_PCIE_7
+						end
 					end
 					chip drivers/usb/acpi
 						register "desc" = ""USB3 Type-A Port 1""
@@ -541,9 +601,16 @@ chip soc/intel/pantherlake
 				register "wake" = "GPE0_PME_B0"
 				register "add_acpi_dma_property" = "true"
 				register "enable_cnvi_ddr_rfim" = "true"
+				use cnvi_bluetooth as bluetooth_companion
 				device generic 0 on end
 			end
 		end # CNVi
+
+		device ref cnvi_bluetooth on
+			probe WIFI WIFI_CNVI_6
+			probe WIFI WIFI_CNVI_7
+		end
+
 		# NOTE: i2c0 is function 0; hence it needs to be enabled when any of i2c1-5 is enabled.
 		# TPM device is under i2c3. Therefore, i2c0 needs to be enabled anyways.
 		device ref i2c0 on end
@@ -562,8 +629,9 @@ chip soc/intel/pantherlake
 			chip drivers/i2c/hid
 				register "generic.hid" = ""HFW68H""
 				register "generic.desc" = ""Hynitron TOUCHPAD""
-				register "generic.irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_A13_IRQ)"
-				register "generic.wake" = "GPE0_DW0_13"
+				register "generic.irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_F18_IRQ)"
+				# NOTE: pmc_gpe0_dw0 will be overridden to GPP_F in variant.c.
+				register "generic.wake" = "GPE0_DW0_18"
 				register "generic.uid" = "5"
 				register "generic.detect" = "1"
 				register "hid_desc_reg_offset" = "0x20"
diff --git a/src/mainboard/google/ocelot/variants/ocelot/variant.c b/src/mainboard/google/ocelot/variants/ocelot/variant.c
index 34974da918..2f40fadad1 100644
--- a/src/mainboard/google/ocelot/variants/ocelot/variant.c
+++ b/src/mainboard/google/ocelot/variants/ocelot/variant.c
@@ -1,9 +1,12 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
-#include <acpi/acpigen.h>
 #include <baseboard/variants.h>
+#include <ec/google/chromeec/ec.h>
+#include <fsp/api.h>
 #include <fw_config.h>
 #include <sar.h>
+#include <soc/gpio_soc_defs.h>
+#include <drivers/intel/touch/chip.h>
 
 const char *get_wifi_sar_cbfs_filename(void)
 {
@@ -12,8 +15,6 @@ const char *get_wifi_sar_cbfs_filename(void)
 
 void variant_update_soc_chip_config(struct soc_intel_pantherlake_config *config)
 {
-	config->cnvi_wifi_core = false;
-	config->cnvi_bt_core = false;
 	/* CNVi */
 	if (fw_config_probe(FW_CONFIG(WIFI, WIFI_CNVI_6)) ||
 			fw_config_probe(FW_CONFIG(WIFI, WIFI_CNVI_7))) {
@@ -25,4 +26,66 @@ void variant_update_soc_chip_config(struct soc_intel_pantherlake_config *config)
 			config->cnvi_bt_audio_offload = true;
 		}
 	}
+
+    /* Touchscreen and touchpad WOT support:
+     * +===================+==================+=================+============================+
+     * | touchsreen        | touchpad         | PMC_GPE0_DW0    | WOT                        |
+     * +===================+==================+==============================================+
+     * | THC-SPI/THC-I2C   | LPSS-I2C         | GPP_F           | TS, TP                     |
+     * +-------------------+------------------+----------------------------------------------+
+     * | THC-SPI/THC-I2C   | not used or      | GPP_A (default) | TS                         |
+     * |                   | with WOT disabled|                 |                            |
+     * +-------------------+------------------+----------------------------------------------+
+     * | THC-SPI/THC-I2C   | THC-I2C          | GPP_A (default) | TS, TP                     |
+     * +-------------------+------------------+----------------------------------------------+
+     * | LPSS-SPI/LPSS-I2C | LPSS-I2C         | GPP_F           | TS via PMC_GPE0_DW2: GPP_E,|
+     * |                   |                  |                 | TP                         |
+     * +-------------------+------------------+----------------------------------------------+
+     * | LPSS-SPI/LPSS-I2C | not used or      | GPP_A (default) | TS via PMC_GPE0_DW2: GPP_E |
+     * |                   | with WOT disabled|                 |                            |
+     * +-------------------+------------------+----------------------------------------------+
+     * | not used          | not used or      | GPP_A (default) | NA                         |
+     * | with WOT disabled | with WOT disabled|                 |                            |
+     * +===================+==================+=================+============================+
+     */
+	if (fw_config_probe(FW_CONFIG(TOUCHSCREEN, TOUCHSCREEN_THC_I2C))) {
+		config->thc_mode[0] = THC_HID_I2C_MODE;
+	} else if (fw_config_probe(FW_CONFIG(TOUCHSCREEN, TOUCHSCREEN_THC_SPI))) {
+		config->thc_mode[0] = THC_HID_SPI_MODE;
+	}
+
+	if (fw_config_probe(FW_CONFIG(TOUCHPAD, TOUCHPAD_LPSS_I2C))) {
+		/* touchpad: GPP_F18: GPE0_DW0_18 */
+		if (config->thc_wake_on_touch[1])
+			config->pmc_gpe0_dw0 = GPP_F;
+	} else if (fw_config_probe(FW_CONFIG(TOUCHPAD, TOUCHPAD_THC_I2C))) {
+		config->thc_mode[1] = THC_HID_I2C_MODE;
+
+		if (fw_config_probe(FW_CONFIG(TOUCHSCREEN, TOUCHSCREEN_NONE)))
+			/* When THC0 is only enabled due to THC1 is enabled, we force THC0
+			 * to I2C mode so that kernel THC I2C driver will find it and put
+			 * THC0 to low power state because no connected device is found.
+			 */
+			config->thc_mode[0] = THC_HID_I2C_MODE;
+	}
+}
+
+void variant_update_soc_memory_init_params(FSPM_UPD *memupd)
+{
+	FSP_M_CONFIG *m_cfg = &memupd->FspmConfig;
+
+	/* HDA Audio */
+	if (fw_config_probe(FW_CONFIG(AUDIO, AUDIO_ALC256_HDA))) {
+		printk(BIOS_INFO, "Overriding HDA SDI lanes.\n");
+		m_cfg->PchHdaSdiEnable[0] = true;
+		m_cfg->PchHdaSdiEnable[1] = false;
+	}
+}
+
+bool variant_is_barrel_charger_present(void)
+{
+	if (fw_config_probe(FW_CONFIG(PSU, PSU_BJ)))
+		return google_chromeec_is_barrel_charger_present();
+	else
+		return false;
 }

From aafcb01ec42ca099a9b82f88c32638b3bb625f7e Mon Sep 17 00:00:00 2001
From: Jeremy Compostella <jeremy.compostella@intel.com>
Date: Mon, 13 Jan 2025 13:20:12 -0800
Subject: [PATCH 0864/3886] mb/intel/ptlrvp: Synchronize codebase with fatcat

This commit imports changes from mb/google/fatcat to mb/intel/ptlrvp as
of coreboot codebase commit 010cfa28421b
("doc/internals/devicetree_language: multiple segment groups
supported").

Here is the list of imported commits:
- commit 9495063993e3 ("mainboard/google/fatcat: Fix SMBIOS Processor
  upgrade info")
- commit 27f3427f4a1d ("mb/google/fatcat/var/fatcat: Update GSPI0 CS pin
  for FPS")
- commit c41af2d43c49 ("mb/google/fatcat/var/fatcat: Update THC
  Interrupt for Touchpad Development")
- commit b5dea9fa999a ("mb/google/fatcat/var/francka: Add Write Protect
  GPIO to cros_gpios")
- commit ef80ccbc4364 ("mb/google/fatcat: Disable EC software sync for
  Microchip EC")
- commit 9f39d6ec5e9f ("mb/google/fatcat: Enable HAVE_SLP_S0_GATE for
  felino and francka")
- commit eb85dfae1f23 ("mb/google/fatcat: Configure GPIO_SLP_S0_GATE for
  francka and felino")
- commit 0fc2422e88dc ("mb/google/fatcat: Implement S0ix hooks aka
  `MS0X` method")
- commit 1fa5ab805bb1 ("mb/google/fatcat: Remove unnecessary CNVi core
  variables settings")
- commit 5c0340349ecb ("mb/google/fatcat: Rationalize Wi-Fi and
  Bluetooth combinations")
- commit 275beb93db80 ("mb/google/fatcat: Conditionally check for barrel
  charger")
- commit e9b020f02e3a ("mb/google/fatcat: Allow board-specific FSP-M UPD
  override")
- commit 3a88eb8cb6c6 ("mb/google/fatcat: Enable HDA SDI based on FW
  config")
- commit 0ac2058dbee6 ("mb/google/fatcat: Increase sagv_freq_mhz for
  work point #1 to #3")
- commit 6e529e7c0611 ("mb/google/fatcat: Add Intel Touch support for
  touchscreen and touchpad")

Overall, these commits aim to improve the configuration, performance,
and compatibility of the Intel Panther Lake Reference Validation
Platform (PTLRVP) mainboard across various aspects, including processor
upgrade support, peripheral integration, power management, and audio
functionality.

TEST=Successful boot with a ptlrvp image on a Fatcat board.

Change-Id: Ie27763a367d8d53c64ad78d26909f1068af3c819
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87223
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Zhixing Ma <zhixing.ma@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/intel/ptlrvp/Kconfig            |   5 +-
 src/mainboard/intel/ptlrvp/mainboard.c        |  27 +++++
 src/mainboard/intel/ptlrvp/romstage.c         |   9 ++
 .../baseboard/include/baseboard/variants.h    |   2 +
 .../variants/baseboard/ptlrvp/devicetree.cb   |   7 +-
 .../baseboard/ptlrvp/include/baseboard/gpio.h |   1 +
 .../variants/baseboard/ptlrvp/ramstage.c      |   2 +-
 .../intel/ptlrvp/variants/ptlrvp/Makefile.mk  |   2 +-
 .../intel/ptlrvp/variants/ptlrvp/fw_config.c  | 107 ++++++++++++++----
 .../intel/ptlrvp/variants/ptlrvp/gpio.c       |   6 +-
 .../ptlrvp/variants/ptlrvp/overridetree.cb    |  76 ++++++++++++-
 .../intel/ptlrvp/variants/ptlrvp/variant.c    |  62 +++++++++-
 .../variants/ptlrvp_chromeec/overridetree.cb  |  76 ++++++++++++-
 13 files changed, 336 insertions(+), 46 deletions(-)

diff --git a/src/mainboard/intel/ptlrvp/Kconfig b/src/mainboard/intel/ptlrvp/Kconfig
index ad6ac41e22..096821f885 100644
--- a/src/mainboard/intel/ptlrvp/Kconfig
+++ b/src/mainboard/intel/ptlrvp/Kconfig
@@ -3,6 +3,7 @@
 config BOARD_INTEL_PTLRVP_COMMON
 	def_bool n
 	select BOARD_ROMSIZE_KB_32768
+	select CPU_INTEL_SOCKET_OTHER
 	select DRIVERS_GFX_GENERIC
 	select DRIVERS_I2C_GENERIC
 	select DRIVERS_I2C_HID
@@ -39,7 +40,6 @@ config BOARD_INTEL_BASEBOARD_PTLRVP
 	select DRIVERS_INTEL_ISH
 	select DRIVER_INTEL_ISH_HAS_MAIN_FW
 	select DRIVERS_INTEL_USB4_RETIMER
-	select HAVE_SLP_S0_GATE
 	select MAINBOARD_HAS_CHROMEOS
 	select MEMORY_SOLDERDOWN
 	select SOC_INTEL_COMMON_BLOCK_HDA_VERB
@@ -52,6 +52,7 @@ config BOARD_INTEL_MODEL_PTLRVP
 	select BOARD_INTEL_BASEBOARD_PTLRVP
 	select DRIVERS_GENERIC_BAYHUB_LV2
 	select DRIVERS_GENERIC_MAX98357A
+	select DRIVERS_INTEL_TOUCH
 
 config BOARD_INTEL_PTLRVP
 	select BOARD_INTEL_MODEL_PTLRVP
@@ -80,7 +81,7 @@ config BASEBOARD_DIR
 
 config CHROMEOS
 	select EC_GOOGLE_CHROMEEC_SWITCHES if BOARD_INTEL_PTLRVP_CHROMEEC
-	select GBB_FLAG_DISABLE_EC_SOFTWARE_SYNC
+	select GBB_FLAG_DISABLE_EC_SOFTWARE_SYNC if EC_GOOGLE_CHROMEEC_MEC
 	select GBB_FLAG_FORCE_DEV_BOOT_USB
 	select GBB_FLAG_FORCE_MANUAL_RECOVERY
 	select HAS_RECOVERY_MRC_CACHE
diff --git a/src/mainboard/intel/ptlrvp/mainboard.c b/src/mainboard/intel/ptlrvp/mainboard.c
index f514eb96d1..e14c5ace79 100644
--- a/src/mainboard/intel/ptlrvp/mainboard.c
+++ b/src/mainboard/intel/ptlrvp/mainboard.c
@@ -58,6 +58,32 @@ void __weak variant_generate_s0ix_hook(enum s0ix_entry entry)
 	 */
 }
 
+static void mainboard_generate_s0ix_hook(void)
+{
+	acpigen_write_if_lequal_op_int(ARG0_OP, 1);
+	{
+		if (CONFIG(HAVE_SLP_S0_GATE))
+			acpigen_soc_clear_tx_gpio(GPIO_SLP_S0_GATE);
+		variant_generate_s0ix_hook(S0IX_ENTRY);
+	}
+	acpigen_write_else();
+	{
+		if (CONFIG(HAVE_SLP_S0_GATE))
+			acpigen_soc_set_tx_gpio(GPIO_SLP_S0_GATE);
+		variant_generate_s0ix_hook(S0IX_EXIT);
+	}
+	acpigen_write_if_end();
+}
+
+static void mainboard_fill_ssdt(const struct device *dev)
+{
+	acpigen_write_scope("\\_SB");
+	acpigen_write_method_serialized("MS0X", 1);
+	mainboard_generate_s0ix_hook();
+	acpigen_write_method_end(); /* Method */
+	acpigen_write_scope_end(); /* Scope */
+}
+
 static void mainboard_dev_init(struct device *dev)
 {
 	mainboard_ec_init();
@@ -66,6 +92,7 @@ static void mainboard_dev_init(struct device *dev)
 static void mainboard_enable(struct device *dev)
 {
 	dev->ops->init = mainboard_dev_init;
+	dev->ops->acpi_fill_ssdt = mainboard_fill_ssdt;
 }
 
 struct chip_operations mainboard_ops = {
diff --git a/src/mainboard/intel/ptlrvp/romstage.c b/src/mainboard/intel/ptlrvp/romstage.c
index b6e3681891..1c5297125b 100644
--- a/src/mainboard/intel/ptlrvp/romstage.c
+++ b/src/mainboard/intel/ptlrvp/romstage.c
@@ -4,6 +4,7 @@
 #include <ec/intel/board_id.h>
 #include <fsp/api.h>
 #include <soc/romstage.h>
+#include <soc/soc_chip.h>
 #include <string.h>
 
 /*
@@ -17,6 +18,11 @@ __weak void fw_config_configure_pre_mem_gpio(void)
 	/* Nothing to do */
 }
 
+__weak void variant_update_soc_memory_init_params(FSPM_UPD *memupd)
+{
+	/* Nothing to do */
+}
+
 void mainboard_memory_init_params(FSPM_UPD *memupd)
 {
 	const struct pad_config *pads;
@@ -45,4 +51,7 @@ void mainboard_memory_init_params(FSPM_UPD *memupd)
 		die("Unknown board id = 0x%x\n", board_id);
 		break;
 	}
+
+	/* Override FSP-M UPD per board if required. */
+	variant_update_soc_memory_init_params(memupd);
 }
diff --git a/src/mainboard/intel/ptlrvp/variants/baseboard/include/baseboard/variants.h b/src/mainboard/intel/ptlrvp/variants/baseboard/include/baseboard/variants.h
index 5a59f1ff7c..d44ef98552 100644
--- a/src/mainboard/intel/ptlrvp/variants/baseboard/include/baseboard/variants.h
+++ b/src/mainboard/intel/ptlrvp/variants/baseboard/include/baseboard/variants.h
@@ -4,6 +4,7 @@
 #define __BASEBOARD_VARIANTS_H__
 
 #include <chip.h>
+#include <fsp/api.h>
 #include <soc/gpio.h>
 #include <soc/meminit.h>
 #include <stdint.h>
@@ -30,6 +31,7 @@ const struct mb_cfg *variant_memory_params(void);
 void variant_get_spd_info(struct mem_spd *spd_info);
 int variant_memory_sku(void);
 bool variant_is_half_populated(void);
+void variant_update_soc_memory_init_params(FSPM_UPD *memupd);
 void variant_update_soc_chip_config(struct soc_intel_pantherlake_config *config);
 
 enum s0ix_entry {
diff --git a/src/mainboard/intel/ptlrvp/variants/baseboard/ptlrvp/devicetree.cb b/src/mainboard/intel/ptlrvp/variants/baseboard/ptlrvp/devicetree.cb
index c45738a090..c599a00139 100644
--- a/src/mainboard/intel/ptlrvp/variants/baseboard/ptlrvp/devicetree.cb
+++ b/src/mainboard/intel/ptlrvp/variants/baseboard/ptlrvp/devicetree.cb
@@ -36,13 +36,13 @@ chip soc/intel/pantherlake
 	register "sagv_freq_mhz[0]" = "2400"
 	register "sagv_gear[0]" = "GEAR_4"
 
-	register "sagv_freq_mhz[1]" = "3200"
+	register "sagv_freq_mhz[1]" = "4800"
 	register "sagv_gear[1]" = "GEAR_4"
 
-	register "sagv_freq_mhz[2]" = "6000"
+	register "sagv_freq_mhz[2]" = "6400"
 	register "sagv_gear[2]" = "GEAR_4"
 
-	register "sagv_freq_mhz[3]" = "6400"
+	register "sagv_freq_mhz[3]" = "6800"
 	register "sagv_gear[3]" = "GEAR_4"
 
 	# Enable s0ix
@@ -81,7 +81,6 @@ chip soc/intel/pantherlake
 	register "pch_hda_idisp_link_tmode" = "HDA_TMODE_8T"
 	register "pch_hda_idisp_link_frequency" = "HDA_LINKFREQ_96MHZ"
 	register "pch_hda_idisp_codec_enable" = "true"
-	register "pch_hda_sdi_enable" = "{ true, false }"
 
 	device domain 0 on
 		device ref dtt on end
diff --git a/src/mainboard/intel/ptlrvp/variants/baseboard/ptlrvp/include/baseboard/gpio.h b/src/mainboard/intel/ptlrvp/variants/baseboard/ptlrvp/include/baseboard/gpio.h
index 5a77e4eb2c..b169d358dd 100644
--- a/src/mainboard/intel/ptlrvp/variants/baseboard/ptlrvp/include/baseboard/gpio.h
+++ b/src/mainboard/intel/ptlrvp/variants/baseboard/ptlrvp/include/baseboard/gpio.h
@@ -13,5 +13,6 @@
 #define EC_SYNC_IRQ	0
 /* WP signal to PCH */
 #define GPIO_PCH_WP	0
+#define GPIO_SLP_S0_GATE	0 /* Not Connected */
 
 #endif /* __BASEBOARD_GPIO_H__ */
diff --git a/src/mainboard/intel/ptlrvp/variants/baseboard/ptlrvp/ramstage.c b/src/mainboard/intel/ptlrvp/variants/baseboard/ptlrvp/ramstage.c
index 030b587579..6c7668fa4b 100644
--- a/src/mainboard/intel/ptlrvp/variants/baseboard/ptlrvp/ramstage.c
+++ b/src/mainboard/intel/ptlrvp/variants/baseboard/ptlrvp/ramstage.c
@@ -53,7 +53,7 @@ const struct cpu_tdp_power_limits power_optimized_limits[] = {
 void baseboard_devtree_update(void)
 {
 	/* Don't optimize the power limit if booting with barrel attached */
-	if (google_chromeec_is_barrel_charger_present())
+	if (CONFIG(BOARD_INTEL_MODEL_PTLRVP) && google_chromeec_is_barrel_charger_present())
 		return;
 
 	if (!google_chromeec_is_battery_present())
diff --git a/src/mainboard/intel/ptlrvp/variants/ptlrvp/Makefile.mk b/src/mainboard/intel/ptlrvp/variants/ptlrvp/Makefile.mk
index eb361dfe89..b9f1fd15dd 100644
--- a/src/mainboard/intel/ptlrvp/variants/ptlrvp/Makefile.mk
+++ b/src/mainboard/intel/ptlrvp/variants/ptlrvp/Makefile.mk
@@ -5,5 +5,5 @@ romstage-y += gpio.c
 romstage-y += memory.c
 romstage-$(CONFIG_FW_CONFIG) += fw_config.c
 ramstage-y += gpio.c
-ramstage-$(CONFIG_FW_CONFIG) += variant.c
+romstage-$(CONFIG_FW_CONFIG) += variant.c
 ramstage-$(CONFIG_FW_CONFIG) += fw_config.c
diff --git a/src/mainboard/intel/ptlrvp/variants/ptlrvp/fw_config.c b/src/mainboard/intel/ptlrvp/variants/ptlrvp/fw_config.c
index 9419caf709..afd8a63084 100644
--- a/src/mainboard/intel/ptlrvp/variants/ptlrvp/fw_config.c
+++ b/src/mainboard/intel/ptlrvp/variants/ptlrvp/fw_config.c
@@ -351,6 +351,8 @@ static const struct pad_config touchscreen_disable_pads[] = {
 	PAD_NC(GPP_E17, NONE),
 	/* GPP_E18:     THC0_SPI1_INT_N_TCH_PNL1 */
 	PAD_NC(GPP_E18, NONE),
+	/* GPP_VGPIO3_THC0: THC0_WOT */
+	PAD_NC(GPP_VGPIO3_THC0, NONE),
 };
 
 static const struct pad_config touchscreen_lpss_i2c_enable_pads[] = {
@@ -370,6 +372,8 @@ static const struct pad_config touchscreen_lpss_i2c_enable_pads[] = {
 	PAD_NC(GPP_E17, NONE),
 	/* GPP_E18:     THC0_SPI1_INT_N_TCH_PNL1 */
 	PAD_CFG_GPI_APIC(GPP_E18, NONE, PLTRST, LEVEL, NONE),
+	/* GPP_VGPIO3_THC0: THC0_WOT */
+	PAD_NC(GPP_VGPIO3_THC0, NONE),
 };
 
 static const struct pad_config touchscreen_thc_i2c_enable_pads[] = {
@@ -388,7 +392,10 @@ static const struct pad_config touchscreen_thc_i2c_enable_pads[] = {
 	/* GPP_E17:     THC0_SPI1_CS0_N_TCH_PNL1 */
 	PAD_NC(GPP_E17, NONE),
 	/* GPP_E18:     THC0_SPI1_INT_N_TCH_PNL1 */
-	PAD_CFG_GPI_APIC(GPP_E18, NONE, PLTRST, LEVEL, NONE),
+	/* NOTE: this SPI INT NF is also used in THC-I2C mode */
+	PAD_CFG_NF(GPP_E18, NONE, DEEP, NF3),
+	/* GPP_VGPIO3_THC0: THC0_WOT */
+	PAD_NC(GPP_VGPIO3_THC0, NONE),
 };
 
 static const struct pad_config touchscreen_gspi_enable_pads[] = {
@@ -407,7 +414,9 @@ static const struct pad_config touchscreen_gspi_enable_pads[] = {
 	/* GPP_E17:     THC0_SPI1_CS0_N_TCH_PNL1 NF5: GSPI0 */
 	PAD_CFG_NF(GPP_E17, NONE, DEEP, NF5),
 	/* GPP_E18:     THC0_SPI1_INT_N_TCH_PNL1 */
-	PAD_CFG_GPI_APIC(GPP_E18, NONE, PLTRST, EDGE_SINGLE, INVERT)
+	PAD_CFG_GPI_APIC(GPP_E18, NONE, PLTRST, EDGE_SINGLE, INVERT),
+	/* GPP_VGPIO3_THC0: THC0_WOT */
+	PAD_NC(GPP_VGPIO3_THC0, NONE),
 };
 
 static const struct pad_config touchscreen_thc_spi_enable_pads[] = {
@@ -428,13 +437,21 @@ static const struct pad_config touchscreen_thc_spi_enable_pads[] = {
 	PAD_CFG_NF(GPP_E17, NONE, DEEP, NF3),
 	/* GPP_E18:     THC0_SPI1_INT_N_TCH_PNL1 NF3: THC HID-SPI */
 	PAD_CFG_NF(GPP_E18, NONE, DEEP, NF3),
+	/* GPP_VGPIO3_THC0: THC0_WOT */
+	PAD_NC(GPP_VGPIO3_THC0, NONE),
 };
 
 static const struct pad_config touchpad_thc_i2c_enable_pads[] = {
-	/* GPP_F12:     NF1: thc_i2c1_scl */
+	/* GPP_F12:     NF1: THC_I2C1_SCL */
 	PAD_CFG_NF(GPP_F12, NONE, DEEP, NF1),
-	/* GPP_F13:     NF1: thc_i2c1_sda */
+	/* GPP_F13:     NF1: THC_I2C1_SDA */
 	PAD_CFG_NF(GPP_F13, NONE, DEEP, NF1),
+	/* GPP_F18:     TCH_PAD_INT_N */
+	/* NOTE: this SPI INT NF is also used in THC-I2C mode */
+	/* NOTE: require rework to switch from GPP_A13 to GPP_F18 */
+	PAD_CFG_NF(GPP_F18, NONE, DEEP, NF3),
+	/* GPP_VGPIO3_THC1: THC1_WOT */
+	PAD_NC(GPP_VGPIO3_THC1, NONE),
 };
 
 static const struct pad_config touchpad_lpss_i2c_enable_pads[] = {
@@ -442,8 +459,11 @@ static const struct pad_config touchpad_lpss_i2c_enable_pads[] = {
 	PAD_CFG_NF(GPP_F12, NONE, DEEP, NF8),
 	/* GPP_F13:     THC_I2C1_SDA_TCH_PAD */
 	PAD_CFG_NF(GPP_F13, NONE, DEEP, NF8),
-	/* GPP_A13:     TCH_PAD_INT_N */
-	PAD_CFG_GPI_IRQ_WAKE(GPP_A13, NONE, PWROK, EDGE_SINGLE, INVERT),
+	/* GPP_F18:     TCH_PAD_INT_N */
+	/* NOTE: require rework to switch from GPP_A13 to GPP_F18 */
+	PAD_CFG_GPI_APIC(GPP_F18, NONE, PLTRST, LEVEL, INVERT),
+	/* GPP_VGPIO3_THC1: THC1_WOT */
+	PAD_NC(GPP_VGPIO3_THC1, NONE),
 };
 
 static const struct pad_config touchpad_i2c_disable_pads[] = {
@@ -451,8 +471,21 @@ static const struct pad_config touchpad_i2c_disable_pads[] = {
 	PAD_NC(GPP_F12, NONE),
 	/* GPP_F13:     THC_I2C1_SDA_TCH_PAD */
 	PAD_NC(GPP_F13, NONE),
-	/* GPP_A13:     TCH_PAD_INT_N */
-	PAD_NC(GPP_A13, NONE),
+	/* GPP_F18:     TCH_PAD_INT_N */
+	/* NOTE: require rework to switch from GPP_A13 to GPP_F18 */
+	PAD_NC(GPP_F18, NONE),
+	/* GPP_VGPIO3_THC1: THC1_WOT */
+	PAD_NC(GPP_VGPIO3_THC1, NONE),
+};
+
+static const struct pad_config thc0_enable_wake[] = {
+	/* GPP_VGPIO3_THC0: THC0_WOT */
+	PAD_CFG_GPI_APIC_DRIVER(GPP_VGPIO3_THC0, NONE, PLTRST, LEVEL, NONE),
+};
+
+static const struct pad_config thc1_enable_wake[] = {
+	/* GPP_VGPIO3_THC1: THC1_WOT */
+	PAD_CFG_GPI_APIC_DRIVER(GPP_VGPIO3_THC1, NONE, PLTRST, LEVEL, NONE),
 };
 
 static const struct pad_config ish_disable_pads[] = {
@@ -477,6 +510,7 @@ static const struct pad_config fp_disable_pads[] = {
 	PAD_NC(GPP_C15, NONE),
 	/* GPP_D01:     MOD_TCSS1_TYP_A_VBUS_EN */
 	PAD_CFG_GPO(GPP_D01, 1, DEEP),
+	PAD_NC(GPP_E17, NONE),
 	/* FIXME: b/390031369
 	 * use dedicated GPIO PIN for codec enable
 	 * when FPS is enabled.
@@ -487,7 +521,6 @@ static const struct pad_config fp_disable_pads[] = {
 	PAD_NC(GPP_F14, NONE),
 	PAD_NC(GPP_F15, NONE),
 	PAD_NC(GPP_F16, NONE),
-	PAD_NC(GPP_F18, NONE),
 };
 
 static const struct pad_config fp_enable_pads[] = {
@@ -495,6 +528,8 @@ static const struct pad_config fp_enable_pads[] = {
 	PAD_CFG_GPO_LOCK(GPP_C15, 1, LOCK_CONFIG),
 	/* GPP_D01:     FPS_SOC_INT_L */
 	PAD_CFG_GPI_IRQ_WAKE(GPP_D01, NONE, PWROK, LEVEL, INVERT),
+	/* GPP_E17:     GSPI0A_CS0 */
+	PAD_CFG_NF(GPP_E17, NONE, DEEP, NF5),
 	/* GPP_E19:     FPMCU_PWREN */
 	PAD_CFG_GPO(GPP_E19, 1, DEEP),
 	/* GPP_E20:     FPMCU_FW_UPDATE */
@@ -505,8 +540,6 @@ static const struct pad_config fp_enable_pads[] = {
 	PAD_CFG_NF(GPP_F15, NONE, DEEP, NF8),
 	/* GPP_F16:     GPSI0A_CLK */
 	PAD_CFG_NF(GPP_F16, NONE, DEEP, NF8),
-	/* GPP_F18:     GSPI0A_CS0 */
-	PAD_CFG_NF(GPP_F18, NONE, DEEP, NF8),
 };
 
 static const struct pad_config pre_mem_fp_enable_pads[] = {
@@ -556,6 +589,8 @@ void fw_config_configure_pre_mem_gpio(void)
 
 void fw_config_gpio_padbased_override(struct pad_config *padbased_table)
 {
+	const struct soc_intel_pantherlake_config *config = config_of_soc();
+
 	if (!fw_config_is_provisioned()) {
 		printk(BIOS_WARNING, "FW_CONFIG is not provisioned, Exiting\n");
 		return;
@@ -618,23 +653,31 @@ void fw_config_gpio_padbased_override(struct pad_config *padbased_table)
 	else
 		GPIO_PADBASED_OVERRIDE(padbased_table, x1slot_pads);
 
-	if (fw_config_probe(FW_CONFIG(TOUCHPAD, TOUCHPAD_LPSS_I2C)))
+	if (fw_config_probe(FW_CONFIG(TOUCHPAD, TOUCHPAD_LPSS_I2C))) {
 		GPIO_PADBASED_OVERRIDE(padbased_table, touchpad_lpss_i2c_enable_pads);
-	else if (fw_config_probe(FW_CONFIG(TOUCHPAD, TOUCHPAD_THC_I2C)))
+	} else if (fw_config_probe(FW_CONFIG(TOUCHPAD, TOUCHPAD_THC_I2C))) {
 		GPIO_PADBASED_OVERRIDE(padbased_table, touchpad_thc_i2c_enable_pads);
-	else
+		if (config->thc_wake_on_touch[1])
+			GPIO_PADBASED_OVERRIDE(padbased_table, thc1_enable_wake);
+	} else {
 		GPIO_PADBASED_OVERRIDE(padbased_table, touchpad_i2c_disable_pads);
+	}
 
-	if (fw_config_probe(FW_CONFIG(TOUCHSCREEN, TOUCHSCREEN_LPSS_I2C)))
+	if (fw_config_probe(FW_CONFIG(TOUCHSCREEN, TOUCHSCREEN_LPSS_I2C))) {
 		GPIO_PADBASED_OVERRIDE(padbased_table, touchscreen_lpss_i2c_enable_pads);
-	else if (fw_config_probe(FW_CONFIG(TOUCHSCREEN, TOUCHSCREEN_THC_I2C)))
+	} else if (fw_config_probe(FW_CONFIG(TOUCHSCREEN, TOUCHSCREEN_THC_I2C))) {
 		GPIO_PADBASED_OVERRIDE(padbased_table, touchscreen_thc_i2c_enable_pads);
-	else if (fw_config_probe(FW_CONFIG(TOUCHSCREEN, TOUCHSCREEN_GSPI)))
+		if (config->thc_wake_on_touch[0])
+			GPIO_PADBASED_OVERRIDE(padbased_table, thc0_enable_wake);
+	} else if (fw_config_probe(FW_CONFIG(TOUCHSCREEN, TOUCHSCREEN_GSPI))) {
 		GPIO_PADBASED_OVERRIDE(padbased_table, touchscreen_gspi_enable_pads);
-	else if (fw_config_probe(FW_CONFIG(TOUCHSCREEN, TOUCHSCREEN_THC_SPI)))
+	} else if (fw_config_probe(FW_CONFIG(TOUCHSCREEN, TOUCHSCREEN_THC_SPI))) {
 		GPIO_PADBASED_OVERRIDE(padbased_table, touchscreen_thc_spi_enable_pads);
-	else
+		if (config->thc_wake_on_touch[0])
+			GPIO_PADBASED_OVERRIDE(padbased_table, thc0_enable_wake);
+	} else {
 		GPIO_PADBASED_OVERRIDE(padbased_table, touchscreen_disable_pads);
+	}
 
 	if (fw_config_probe(FW_CONFIG(ISH, ISH_DISABLE)))
 		GPIO_PADBASED_OVERRIDE(padbased_table, ish_disable_pads);
@@ -644,8 +687,26 @@ void fw_config_gpio_padbased_override(struct pad_config *padbased_table)
 	/* NOTE: disable PEG (x8 slot) and x4 slot wake for now */
 	GPIO_PADBASED_OVERRIDE(padbased_table, peg_x4slot_wake_disable_pads);
 
-	if (fw_config_probe(FW_CONFIG(FP, FP_PRESENT)))
-		GPIO_CONFIGURE_PADS(fp_enable_pads);
-	else
-		GPIO_CONFIGURE_PADS(fp_disable_pads);
+	/*
+	 * *=========================================================================*
+	 * |             userage                   |           GPP_E17               |
+	 * *=========================================================================*
+	 * | touchscreen in THC-SPI (with rework)  | NF3: THC HID-SPI CS0            |
+	 * *---------------------------------------*---------------------------------*
+	 * | touchscreen in gSPI    (with rework)  | NF5: GSPI0 CS0                  |
+	 * *---------------------------------------*---------------------------------*
+	 * | FPS present         (without rework)  | NF5: GSPI0 CS0                  |
+	 * *---------------------------------------*---------------------------------*
+	 *
+	 * NOTE: 1. CBI selecting TS THC-SPI or GSPI mode implies TS rework is applied for the board.
+	 *       2. CBI selecting TS THC-SPI or TS GSPI with FSP present is invalid case.
+	 */
+	if (fw_config_probe(FW_CONFIG(TOUCHSCREEN, TOUCHSCREEN_GSPI)) ||
+		fw_config_probe(FW_CONFIG(TOUCHSCREEN, TOUCHSCREEN_THC_SPI))) {
+		/*  board has TS SPI rework and not FPS support */
+	} else if (fw_config_probe(FW_CONFIG(FP, FP_PRESENT))) {
+		GPIO_PADBASED_OVERRIDE(padbased_table, fp_enable_pads);
+	} else {
+		GPIO_PADBASED_OVERRIDE(padbased_table, fp_disable_pads);
+	}
 }
diff --git a/src/mainboard/intel/ptlrvp/variants/ptlrvp/gpio.c b/src/mainboard/intel/ptlrvp/variants/ptlrvp/gpio.c
index 1accd4d597..9531065689 100644
--- a/src/mainboard/intel/ptlrvp/variants/ptlrvp/gpio.c
+++ b/src/mainboard/intel/ptlrvp/variants/ptlrvp/gpio.c
@@ -217,8 +217,6 @@ static const struct pad_config gpio_table[] = {
 	/* GPP_E16:     THC0_SPI1_RST_N_TCH_PNL1 */
 	/* THC NOTE: use GPO instead of GPO for THC0 Rst */
 	PAD_CFG_GPO(GPP_E16, 1, DEEP),
-	/* GPP_E17:     THC0_SPI1_CS0_N_TCH_PNL1 */
-	PAD_CFG_NF(GPP_E17, NONE, DEEP, NF3),
 	/* GPP_E18:     THC0_SPI1_INT_N_TCH_PNL1 */
 	PAD_CFG_NF(GPP_E18, NONE, DEEP, NF3),
 	/* GPP_E21:     I2C_PMC_PD_INT_N */
@@ -262,6 +260,9 @@ static const struct pad_config gpio_table[] = {
 	PAD_CFG_NF(GPP_F13, NONE, DEEP, NF8),
 	/* GPP_F17:     Not used */
 	PAD_CFG_GPI_INT(GPP_F17, NONE, PLTRST, EDGE_BOTH),
+	/* GPP_F18:     TCH_PAD_INT_N */
+	/* NOTE: require rework to switch from GPP_A13 to GPP_F18 */
+	PAD_CFG_GPI_APIC(GPP_F18, NONE, PLTRST, LEVEL, INVERT),
 	/* GPP_F19:     GPP_PRIVACY_LED_CAM2 */
 	PAD_CFG_GPO(GPP_F19, 0, PLTRST),
 	/* GPP_F20:     GPP_PRIVACY_LED_CAM1_CVS_HST_WAKE */
@@ -414,6 +415,7 @@ static const struct cros_gpio cros_gpios[] = {
 	CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE1_NAME),
 	CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE2_NAME),
 	CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE3_NAME),
+	CROS_GPIO_WP_AH(GPIO_PCH_WP, CROS_GPIO_DEVICE4_NAME),
 };
 
 DECLARE_CROS_GPIOS(cros_gpios);
diff --git a/src/mainboard/intel/ptlrvp/variants/ptlrvp/overridetree.cb b/src/mainboard/intel/ptlrvp/variants/ptlrvp/overridetree.cb
index 4a33387cb2..68136d26ea 100644
--- a/src/mainboard/intel/ptlrvp/variants/ptlrvp/overridetree.cb
+++ b/src/mainboard/intel/ptlrvp/variants/ptlrvp/overridetree.cb
@@ -77,7 +77,7 @@ chip soc/intel/pantherlake
 	register "usb2_ports[3]" = "USB2_PORT_TYPE_C(OC_SKIP)" # USB2_C3
 	register "usb2_ports[4]" = "USB2_PORT_MID(OC0)" # Type-A Port A0
 	register "usb2_ports[5]" = "USB2_PORT_MID(OC0)" # Type-A Port A1 / WWAN with rework
-	register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # CNVi BT or discrete BT
+	register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # Discrete Bluetooth
 
 	register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)" # USB3.2 x1 Type-A Con #1
 	register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC0)" # USB3.2 x1 Type-A Con #2 / M.2 WWAN with rework
@@ -317,13 +317,66 @@ chip soc/intel/pantherlake
 		device ref iaa off end
 
 		device ref thc0 on
+			register "thc_wake_on_touch[0]" = "true"
 			probe TOUCHSCREEN TOUCHSCREEN_THC_SPI
 			probe TOUCHSCREEN TOUCHSCREEN_THC_I2C
 			# THC0 is function 0; hence it needs to be enabled when THC1 is to be enabled.
 			probe TOUCHPAD TOUCHPAD_THC_I2C
+			chip drivers/intel/touch
+				register "name" = "INTEL_THC0_NAME"
+				register "mode" = "THC_HID_I2C_MODE"
+				register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_F08)"
+				register "enable_delay_ms" = "2"
+				register "enable_off_delay_ms" = "2"
+				register "wake_on_touch" = "true"
+				# NOTE: Use GpioInt() in _CRS and does not use GPE.
+				register "wake_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW_WAKE(GPP_VGPIO3_THC0)"
+				register "active_ltr" = "1"
+				register "idle_ltr" = "0"
+				register "connected_device" = "TH_SENSOR_ELAN"
+				register "add_acpi_dma_property" = "true"
+				device generic 0 alias touch_0_i2c_elan on
+					probe TOUCHSCREEN TOUCHSCREEN_THC_I2C
+				end
+			end
+			chip drivers/intel/touch
+				register "name" = "INTEL_THC0_NAME"
+				register "mode" = "THC_HID_SPI_MODE"
+				register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_F08)"
+				register "enable_delay_ms" = "2"
+				register "enable_off_delay_ms" = "2"
+				register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_E16)"
+				register "reset_delay_ms" = "10"
+				register "reset_off_delay_ms" = "2"
+				register "wake_on_touch" = "true"
+				# NOTE: Use GpioInt() in _CRS and does not use GPE.
+				register "wake_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW_WAKE(GPP_VGPIO3_THC0)"
+				register "active_ltr" = "1"
+				register "idle_ltr" = "0"
+				register "connected_device" = "TH_SENSOR_ELAN"
+				register "soc_hidspi.write_mode" = "HIDSPI_WRITE_MODE_MULTI_SINGLE_SPI"
+				register "soc_hidspi.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_E16)"
+				register "add_acpi_dma_property" = "true"
+				device generic 0 alias touch_0_spi_elan on
+					probe TOUCHSCREEN TOUCHSCREEN_THC_SPI
+				end
+			end
 		end
 		device ref thc1 on
+			register "thc_wake_on_touch[1]" = "true"
 			probe TOUCHPAD TOUCHPAD_THC_I2C
+			chip drivers/intel/touch
+				register "name" = "INTEL_THC1_NAME"
+				register "mode" = "THC_HID_I2C_MODE"
+				register "wake_on_touch" = "true"
+				# NOTE: Use GpioInt() in _CRS and does not use GPE.
+				register "wake_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW_WAKE(GPP_VGPIO3_THC1)"
+				register "active_ltr" = "1"
+				register "idle_ltr" = "0"
+				register "connected_device" = "TH_SENSOR_HYNITRON"
+				register "add_acpi_dma_property" = "true"
+				device generic 0 alias touch_1_i2c_hynitron on end
+			end
 		end
 
 		device ref tbt_pcie_rp0 on end
@@ -444,7 +497,10 @@ chip soc/intel/pantherlake
 						register "desc" = ""USB2 Bluetooth""
 						register "type" = "UPC_TYPE_INTERNAL"
 						register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A16)"
-						device ref usb2_port8 on end
+						device ref usb2_port8 on
+							probe WIFI WIFI_PCIE_6
+							probe WIFI WIFI_PCIE_7
+						end
 					end
 					chip drivers/usb/acpi
 						register "desc" = ""USB3 Type-A Port 1""
@@ -570,9 +626,16 @@ chip soc/intel/pantherlake
 				register "wake" = "GPE0_PME_B0"
 				register "add_acpi_dma_property" = "true"
 				register "enable_cnvi_ddr_rfim" = "true"
+				use cnvi_bluetooth as bluetooth_companion
 				device generic 0 on end
 			end
 		end # CNVi
+
+		device ref cnvi_bluetooth on
+			probe WIFI WIFI_CNVI_6
+			probe WIFI WIFI_CNVI_7
+		end
+
 		# NOTE: i2c0 is function 0; hence it needs to be enabled when any of i2c1-5 is enabled.
 		# TPM device is under i2c3. Therefore, i2c0 needs to be enabled anyways.
 		device ref i2c0 on end
@@ -796,9 +859,11 @@ chip soc/intel/pantherlake
 		end # I2C3
 		device ref i2c4 on
 			chip drivers/i2c/hid
-				register "generic.hid" = ""ELAN6918""
+				register "generic.hid" = ""ELAN9048""
 				register "generic.desc" = ""ELAN Touchscreen""
 				register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_E18_IRQ)"
+				# NOTE: pmc_gpe0_dw2 is GPP_E in baseboard devicetree.cb.
+				register "generic.wake" = "GPE0_DW2_18"
 				register "generic.probed" = "1"
 				register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_E16)"
 				register "generic.reset_delay_ms" = "20"
@@ -816,8 +881,9 @@ chip soc/intel/pantherlake
 			chip drivers/i2c/hid
 				register "generic.hid" = ""HFW68H""
 				register "generic.desc" = ""Hynitron TOUCHPAD""
-				register "generic.irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_A13_IRQ)"
-				register "generic.wake" = "GPE0_DW0_13"
+				register "generic.irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_F18_IRQ)"
+				# NOTE: pmc_gpe0_dw0 will be overridden to GPP_F in variant.c.
+				register "generic.wake" = "GPE0_DW0_18"
 				register "generic.uid" = "5"
 				register "generic.detect" = "1"
 				register "hid_desc_reg_offset" = "0x20"
diff --git a/src/mainboard/intel/ptlrvp/variants/ptlrvp/variant.c b/src/mainboard/intel/ptlrvp/variants/ptlrvp/variant.c
index c7aa7aa605..5ba7683640 100644
--- a/src/mainboard/intel/ptlrvp/variants/ptlrvp/variant.c
+++ b/src/mainboard/intel/ptlrvp/variants/ptlrvp/variant.c
@@ -1,9 +1,11 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
-#include <acpi/acpigen.h>
 #include <baseboard/variants.h>
+#include <fsp/api.h>
 #include <fw_config.h>
 #include <sar.h>
+#include <soc/gpio_soc_defs.h>
+#include <drivers/intel/touch/chip.h>
 
 const char *get_wifi_sar_cbfs_filename(void)
 {
@@ -12,8 +14,6 @@ const char *get_wifi_sar_cbfs_filename(void)
 
 void variant_update_soc_chip_config(struct soc_intel_pantherlake_config *config)
 {
-	config->cnvi_wifi_core = false;
-	config->cnvi_bt_core = false;
 	/* CNVi */
 	if (fw_config_probe(FW_CONFIG(WIFI, WIFI_CNVI_6)) ||
 		fw_config_probe(FW_CONFIG(WIFI, WIFI_CNVI_7))) {
@@ -27,4 +27,60 @@ void variant_update_soc_chip_config(struct soc_intel_pantherlake_config *config)
 			config->cnvi_bt_audio_offload = true;
 		}
 	}
+
+    /* Touchscreen and touchpad WOT support:
+     * +===================+==================+=================+============================+
+     * | touchsreen        | touchpad         | PMC_GPE0_DW0    | WOT                        |
+     * +===================+==================+==============================================+
+     * | THC-SPI/THC-I2C   | LPSS-I2C         | GPP_F           | TS, TP                     |
+     * +-------------------+------------------+----------------------------------------------+
+     * | THC-SPI/THC-I2C   | not used or      | GPP_A (default) | TS                         |
+     * |                   | with WOT disabled|                 |                            |
+     * +-------------------+------------------+----------------------------------------------+
+     * | THC-SPI/THC-I2C   | THC-I2C          | GPP_A (default) | TS, TP                     |
+     * +-------------------+------------------+----------------------------------------------+
+     * | LPSS-SPI/LPSS-I2C | LPSS-I2C         | GPP_F           | TS via PMC_GPE0_DW2: GPP_E,|
+     * |                   |                  |                 | TP                         |
+     * +-------------------+------------------+----------------------------------------------+
+     * | LPSS-SPI/LPSS-I2C | not used or      | GPP_A (default) | TS via PMC_GPE0_DW2: GPP_E |
+     * |                   | with WOT disabled|                 |                            |
+     * +-------------------+------------------+----------------------------------------------+
+     * | not used          | not used or      | GPP_A (default) | NA                         |
+     * | with WOT disabled | with WOT disabled|                 |                            |
+     * +===================+==================+=================+============================+
+     */
+	if (fw_config_probe(FW_CONFIG(TOUCHSCREEN, TOUCHSCREEN_THC_I2C))) {
+		config->thc_mode[0] = THC_HID_I2C_MODE;
+	} else if (fw_config_probe(FW_CONFIG(TOUCHSCREEN, TOUCHSCREEN_THC_SPI))) {
+		config->thc_mode[0] = THC_HID_SPI_MODE;
+	} else if (fw_config_probe(FW_CONFIG(TOUCHSCREEN, TOUCHSCREEN_GSPI))) {
+		config->serial_io_gspi_mode[PchSerialIoIndexGSPI0] = PchSerialIoPci;
+	}
+
+	if (fw_config_probe(FW_CONFIG(TOUCHPAD, TOUCHPAD_LPSS_I2C))) {
+		/* touchpad: GPP_F18: GPE0_DW0_18 */
+		if (config->thc_wake_on_touch[1])
+			config->pmc_gpe0_dw0 = GPP_F;
+	} else if (fw_config_probe(FW_CONFIG(TOUCHPAD, TOUCHPAD_THC_I2C))) {
+		config->thc_mode[1] = THC_HID_I2C_MODE;
+
+		if (fw_config_probe(FW_CONFIG(TOUCHSCREEN, TOUCHSCREEN_NONE)))
+			/* When THC0 is only enabled due to THC1 is enabled, we force THC0
+			 * to I2C mode so that kernel THC I2C driver will find it and put
+			 * THC0 to low power state because no connected device is found.
+			 */
+			config->thc_mode[0] = THC_HID_I2C_MODE;
+	}
+}
+
+void variant_update_soc_memory_init_params(FSPM_UPD *memupd)
+{
+	FSP_M_CONFIG *m_cfg = &memupd->FspmConfig;
+
+	/* HDA Audio */
+	if (fw_config_probe(FW_CONFIG(AUDIO, AUDIO_ALC256_HDA))) {
+		printk(BIOS_INFO, "Overriding HDA SDI lanes.\n");
+		m_cfg->PchHdaSdiEnable[0] = true;
+		m_cfg->PchHdaSdiEnable[1] = false;
+	}
 }
diff --git a/src/mainboard/intel/ptlrvp/variants/ptlrvp_chromeec/overridetree.cb b/src/mainboard/intel/ptlrvp/variants/ptlrvp_chromeec/overridetree.cb
index d836ab5564..033a0b475b 100644
--- a/src/mainboard/intel/ptlrvp/variants/ptlrvp_chromeec/overridetree.cb
+++ b/src/mainboard/intel/ptlrvp/variants/ptlrvp_chromeec/overridetree.cb
@@ -77,7 +77,7 @@ chip soc/intel/pantherlake
 	register "usb2_ports[3]" = "USB2_PORT_TYPE_C(OC_SKIP)" # USB2_C3
 	register "usb2_ports[4]" = "USB2_PORT_MID(OC0)" # Type-A Port A0
 	register "usb2_ports[5]" = "USB2_PORT_MID(OC0)" # Type-A Port A1 / WWAN with rework
-	register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # CNVi BT or discrete BT
+	register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # Discrete Bluetooth
 
 	register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)" # USB3.2 x1 Type-A Con #1
 	register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC0)" # USB3.2 x1 Type-A Con #2 / M.2 WWAN with rework
@@ -317,13 +317,66 @@ chip soc/intel/pantherlake
 		device ref iaa off end
 
 		device ref thc0 on
+			register "thc_wake_on_touch[0]" = "true"
 			probe TOUCHSCREEN TOUCHSCREEN_THC_SPI
 			probe TOUCHSCREEN TOUCHSCREEN_THC_I2C
 			# THC0 is function 0; hence it needs to be enabled when THC1 is to be enabled.
 			probe TOUCHPAD TOUCHPAD_THC_I2C
+			chip drivers/intel/touch
+				register "name" = "INTEL_THC0_NAME"
+				register "mode" = "THC_HID_I2C_MODE"
+				register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_F08)"
+				register "enable_delay_ms" = "2"
+				register "enable_off_delay_ms" = "2"
+				register "wake_on_touch" = "true"
+				# NOTE: Use GpioInt() in _CRS and does not use GPE.
+				register "wake_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW_WAKE(GPP_VGPIO3_THC0)"
+				register "active_ltr" = "1"
+				register "idle_ltr" = "0"
+				register "connected_device" = "TH_SENSOR_ELAN"
+				register "add_acpi_dma_property" = "true"
+				device generic 0 alias touch_0_i2c_elan on
+					probe TOUCHSCREEN TOUCHSCREEN_THC_I2C
+				end
+			end
+			chip drivers/intel/touch
+				register "name" = "INTEL_THC0_NAME"
+				register "mode" = "THC_HID_SPI_MODE"
+				register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_F08)"
+				register "enable_delay_ms" = "2"
+				register "enable_off_delay_ms" = "2"
+				register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_E16)"
+				register "reset_delay_ms" = "10"
+				register "reset_off_delay_ms" = "2"
+				register "wake_on_touch" = "true"
+				# NOTE: Use GpioInt() in _CRS and does not use GPE.
+				register "wake_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW_WAKE(GPP_VGPIO3_THC0)"
+				register "active_ltr" = "1"
+				register "idle_ltr" = "0"
+				register "connected_device" = "TH_SENSOR_ELAN"
+				register "soc_hidspi.write_mode" = "HIDSPI_WRITE_MODE_MULTI_SINGLE_SPI"
+				register "soc_hidspi.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_E16)"
+				register "add_acpi_dma_property" = "true"
+				device generic 0 alias touch_0_spi_elan on
+					probe TOUCHSCREEN TOUCHSCREEN_THC_SPI
+				end
+			end
 		end
 		device ref thc1 on
+			register "thc_wake_on_touch[1]" = "true"
 			probe TOUCHPAD TOUCHPAD_THC_I2C
+			chip drivers/intel/touch
+				register "name" = "INTEL_THC1_NAME"
+				register "mode" = "THC_HID_I2C_MODE"
+				register "wake_on_touch" = "true"
+				# NOTE: Use GpioInt() in _CRS and does not use GPE.
+				register "wake_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW_WAKE(GPP_VGPIO3_THC1)"
+				register "active_ltr" = "1"
+				register "idle_ltr" = "0"
+				register "connected_device" = "TH_SENSOR_HYNITRON"
+				register "add_acpi_dma_property" = "true"
+				device generic 0 alias touch_1_i2c_hynitron on end
+			end
 		end
 
 		device ref tbt_pcie_rp0 on end
@@ -444,7 +497,10 @@ chip soc/intel/pantherlake
 						register "desc" = ""USB2 Bluetooth""
 						register "type" = "UPC_TYPE_INTERNAL"
 						register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A16)"
-						device ref usb2_port8 on end
+						device ref usb2_port8 on
+							probe WIFI WIFI_PCIE_6
+							probe WIFI WIFI_PCIE_7
+						end
 					end
 					chip drivers/usb/acpi
 						register "desc" = ""USB3 Type-A Port 1""
@@ -570,9 +626,16 @@ chip soc/intel/pantherlake
 				register "wake" = "GPE0_PME_B0"
 				register "add_acpi_dma_property" = "true"
 				register "enable_cnvi_ddr_rfim" = "true"
+				use cnvi_bluetooth as bluetooth_companion
 				device generic 0 on end
 			end
 		end # CNVi
+
+		device ref cnvi_bluetooth on
+			probe WIFI WIFI_CNVI_6
+			probe WIFI WIFI_CNVI_7
+		end
+
 		# NOTE: i2c0 is function 0; hence it needs to be enabled when any of i2c1-5 is enabled.
 		# TPM device is under i2c3. Therefore, i2c0 needs to be enabled anyways.
 		device ref i2c0 on end
@@ -801,9 +864,11 @@ chip soc/intel/pantherlake
 		end # I2C3
 		device ref i2c4 on
 			chip drivers/i2c/hid
-				register "generic.hid" = ""ELAN6918""
+				register "generic.hid" = ""ELAN9048""
 				register "generic.desc" = ""ELAN Touchscreen""
 				register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_E18_IRQ)"
+				# NOTE: pmc_gpe0_dw2 is GPP_E in baseboard devicetree.cb.
+				register "generic.wake" = "GPE0_DW2_18"
 				register "generic.probed" = "1"
 				register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_E16)"
 				register "generic.reset_delay_ms" = "20"
@@ -821,8 +886,9 @@ chip soc/intel/pantherlake
 			chip drivers/i2c/hid
 				register "generic.hid" = ""HFW68H""
 				register "generic.desc" = ""Hynitron TOUCHPAD""
-				register "generic.irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_A13_IRQ)"
-				register "generic.wake" = "GPE0_DW0_13"
+				register "generic.irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_F18_IRQ)"
+				# NOTE: pmc_gpe0_dw0 will be overridden to GPP_F in variant.c.
+				register "generic.wake" = "GPE0_DW0_18"
 				register "generic.uid" = "5"
 				register "generic.detect" = "1"
 				register "hid_desc_reg_offset" = "0x20"

From 92955fbfa6571a6c1d35d8c14cd9f05c182ff82f Mon Sep 17 00:00:00 2001
From: John Su <john_su@compal.corp-partner.google.com>
Date: Mon, 28 Apr 2025 11:03:43 +0800
Subject: [PATCH 0865/3886] mb/google/trulo/var/uldrenite: Configure GPP_E9 as
 NF2

GPP_E9 was wrongly configured to NF1 instead of NF2 i.e. ISH_GP4.
Reference: Intel doc#648094

BUG=b:410645679
TEST=Check GPIO config in the OS.

Change-Id: I43e3ec2e29138d59ed82e5ff4b264ab8dc3a39fb
Signed-off-by: John Su <john_su@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87471
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yuval Peress <peress@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
---
 src/mainboard/google/brya/variants/uldrenite/gpio.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/mainboard/google/brya/variants/uldrenite/gpio.c b/src/mainboard/google/brya/variants/uldrenite/gpio.c
index d9ace37526..d453adb181 100644
--- a/src/mainboard/google/brya/variants/uldrenite/gpio.c
+++ b/src/mainboard/google/brya/variants/uldrenite/gpio.c
@@ -177,7 +177,7 @@ static const struct pad_config gpio_table[] = {
 	/* E8  : GPP_E8 ==> WLAN_DISABLE_L */
 	PAD_CFG_GPO(GPP_E8, 1, DEEP),
 	/* E9  : GPP_E9 ==> SOC_ACC2_INT# */
-	PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_E9, NONE, DEEP, NF2),
 	/* E10 : NC */
 	PAD_NC_LOCK(GPP_E10, NONE, LOCK_CONFIG),
 	/* E11 : NC */

From 85c65b0c20add304615d2467357ca154cd1fc678 Mon Sep 17 00:00:00 2001
From: Subrata Banik <subratabanik@google.com>
Date: Fri, 25 Apr 2025 16:27:21 +0530
Subject: [PATCH 0866/3886] mb/google/fatcat: Remove NPK device from fatcat and
 francka variants

This commit removes the `device ref npk on end` from the
`overridetree.cb` files for the `fatcat` and `francka` variants
of the `google/fatcat` mainboard. This effectively disables
the NPK device for these configurations (because `npk` is default
set to disable).

BUG=b:328770565
TEST=Able to build google/fatcat.

Change-Id: I9dda20552781af6b29a2156cbc1e3bea352c5836
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87453
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jamie Ryu <jamie.m.ryu@intel.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
---
 src/mainboard/google/fatcat/variants/fatcat/overridetree.cb  | 1 -
 src/mainboard/google/fatcat/variants/francka/overridetree.cb | 1 -
 2 files changed, 2 deletions(-)

diff --git a/src/mainboard/google/fatcat/variants/fatcat/overridetree.cb b/src/mainboard/google/fatcat/variants/fatcat/overridetree.cb
index e154ffc46c..565aad6f98 100644
--- a/src/mainboard/google/fatcat/variants/fatcat/overridetree.cb
+++ b/src/mainboard/google/fatcat/variants/fatcat/overridetree.cb
@@ -921,7 +921,6 @@ chip soc/intel/pantherlake
 		end
 
 		device ref smbus on end
-		device ref npk on end
 		device ref hda on
 			chip drivers/intel/soundwire
 				device generic 0 on
diff --git a/src/mainboard/google/fatcat/variants/francka/overridetree.cb b/src/mainboard/google/fatcat/variants/francka/overridetree.cb
index f9e172c8cf..b44cdc6291 100644
--- a/src/mainboard/google/fatcat/variants/francka/overridetree.cb
+++ b/src/mainboard/google/fatcat/variants/francka/overridetree.cb
@@ -273,7 +273,6 @@ chip soc/intel/pantherlake
 		end # M.2 SSD
 
 		device ref smbus on end
-		device ref npk on end
 		device ref hda on
 			chip drivers/sof
 				register "spkr_tplg" = "max98360a"

From 03d2ef67d7ca2018785b2ac20403adc8377aa400 Mon Sep 17 00:00:00 2001
From: Subrata Banik <subratabanik@google.com>
Date: Sat, 26 Apr 2025 23:35:00 +0530
Subject: [PATCH 0867/3886] soc/intel/cmn/hda: Introduce mainboard hook for HDA
 initialization
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

This commit refactors the HDA initialization within the common Intel
SoC block to provide mainboard-level customization.

A new weak function, mainboard_is_hda_codec_enabled(), is
introduced. The `hda_init()` function invokes `azalia_audio_init()` when
`CONFIG(SOC_INTEL_COMMON_BLOCK_HDA_VERB)` is enabled and
`mainboard_is_hda_codec_enabled()` is also true.

The default (weak) implementation of `mainboard_is_hda_codec_enabled()`
simply returns `true`, ensuring that the original behavior is maintained
for mainboards that do not provide an override.

This change allows specific mainboards to implement their own
`mainboard_is_hda_codec_enabled()` to specify if hardware design has
support for HDA codec depending upon the firmware config (FW_CONFIG) for
the audio subsystem.

BUG=b:413638298
TEST=Able to build and boot google/fatcat.

Change-Id: Ided1413e828f6bc3421e538a969c38e15b5f3116
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87461
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jamie Ryu <jamie.m.ryu@intel.com>
Reviewed-by: Pranava Y N <pranavayn@google.com>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
---
 src/soc/intel/common/block/hda/hda.c                 | 12 ++++++++++--
 src/soc/intel/common/block/include/intelblocks/hda.h | 11 +++++++++++
 2 files changed, 21 insertions(+), 2 deletions(-)
 create mode 100644 src/soc/intel/common/block/include/intelblocks/hda.h

diff --git a/src/soc/intel/common/block/hda/hda.c b/src/soc/intel/common/block/hda/hda.c
index d68c5b6998..028b9eaacf 100644
--- a/src/soc/intel/common/block/hda/hda.c
+++ b/src/soc/intel/common/block/hda/hda.c
@@ -1,13 +1,21 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
-#include <device/device.h>
 #include <device/azalia_device.h>
+#include <device/device.h>
 #include <device/pci.h>
 #include <device/pci_ids.h>
+#include <intelblocks/hda.h>
+
+/* Mainboard overrides. */
+
+__weak bool mainboard_is_hda_codec_enabled(void)
+{
+	return true;
+}
 
 static void hda_init(struct device *dev)
 {
-	if (CONFIG(SOC_INTEL_COMMON_BLOCK_HDA_VERB))
+	if (CONFIG(SOC_INTEL_COMMON_BLOCK_HDA_VERB) && mainboard_is_hda_codec_enabled())
 		azalia_audio_init(dev);
 }
 
diff --git a/src/soc/intel/common/block/include/intelblocks/hda.h b/src/soc/intel/common/block/include/intelblocks/hda.h
new file mode 100644
index 0000000000..2cbaf206cb
--- /dev/null
+++ b/src/soc/intel/common/block/include/intelblocks/hda.h
@@ -0,0 +1,11 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef SOC_INTEL_COMMON_BLOCK_HDA_H
+#define SOC_INTEL_COMMON_BLOCK_HDA_H
+
+/* Mainboard overrides. */
+
+/* Mainboard hooks to convey if HD-Audio codec is supported */
+bool mainboard_is_hda_codec_enabled(void);
+
+#endif /* SOC_INTEL_COMMON_BLOCK_HDA_H */

From e545494f6d74618fb418cd04dab49c7fd557c003 Mon Sep 17 00:00:00 2001
From: Subrata Banik <subratabanik@google.com>
Date: Sat, 26 Apr 2025 23:57:09 +0530
Subject: [PATCH 0868/3886] mb/google/fatcat/var/fatcat: Conditionally init
 ALC256 HDA

This commit implements `mainboard_is_hda_codec_enabled()` for the
Google Fatcat mainboard variant. This overrides the default weak HDA
common initialization.

Initialization of the High Definition Audio (HDA) controller,
managed by `azalia_audio_init()` (which handles HDA verb table
loading), is now conditional. It proceeds only if the firmware
config `FW_CONFIG(AUDIO, AUDIO_ALC256_HDA)` is set. This value
(3) specifically targets the ALC256 HDA codec.

This change ensures that HDA verb tables are loaded only when the
ALC256 HDA codec is actively configured for the Fatcat variant.
Crucially, this prevents attempts to incorrectly load HDA verbs
for other audio interfaces, like SoundWire (SNDW) or I2S, which might
be present in different Fatcat hardware configurations.

The header file `intelblocks/hda.h` added for this. As a minor stylistic
update, header inclusions in this file are also alphabetized.

BUG=b:413638298
TEST=Verified HDA verb table loading is skipped on Fatcat platforms
     when configured with non-HDA audio codecs (e.g., SNDW, I2S),
     and proceeds as expected when ALC256 HDA is configured.

Change-Id: Ifc158b7d15c763cc07d28154259b7e64709bea16
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87462
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Pranava Y N <pranavayn@google.com>
---
 .../google/fatcat/variants/fatcat/variant.c   | 22 ++++++++++++++++++-
 1 file changed, 21 insertions(+), 1 deletion(-)

diff --git a/src/mainboard/google/fatcat/variants/fatcat/variant.c b/src/mainboard/google/fatcat/variants/fatcat/variant.c
index 3e0ee54505..a3d7e79e65 100644
--- a/src/mainboard/google/fatcat/variants/fatcat/variant.c
+++ b/src/mainboard/google/fatcat/variants/fatcat/variant.c
@@ -1,12 +1,13 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
 #include <baseboard/variants.h>
+#include <drivers/intel/touch/chip.h>
 #include <ec/google/chromeec/ec.h>
 #include <fsp/api.h>
 #include <fw_config.h>
+#include <intelblocks/hda.h>
 #include <sar.h>
 #include <soc/gpio_soc_defs.h>
-#include <drivers/intel/touch/chip.h>
 
 const char *get_wifi_sar_cbfs_filename(void)
 {
@@ -93,3 +94,22 @@ bool variant_is_barrel_charger_present(void)
 	else
 		return false;
 }
+
+/*
+ * HDA verb table loading is supported based on the firmware configuration.
+ *
+ * This function determines if the current platform has an HDA codec enabled by
+ * examining the `FW_CONFIG` value. Specifically, it checks if the
+ * `FW_CONFIG` includes the `AUDIO_ALC256_HDA` value, which is used to identify
+ * Fatcat SKUs with HDA codec support.
+ *
+ * Return true if the `FW_CONFIG` indicates HDA support (i.e., contains
+ * `AUDIO_ALC256_HDA`), false otherwise.
+ */
+bool mainboard_is_hda_codec_enabled(void)
+{
+	if (fw_config_probe(FW_CONFIG(AUDIO, AUDIO_ALC256_HDA)))
+		return true;
+
+	return false;
+}

From 2e387e13f51ce107a89c53fa7b1b3bb9a630a86f Mon Sep 17 00:00:00 2001
From: Subrata Banik <subratabanik@google.com>
Date: Sun, 27 Apr 2025 00:02:30 +0530
Subject: [PATCH 0869/3886] mb/google/fatcat/var/francka: Conditionally init
 HDA

This commit implements `mainboard_is_hda_codec_enabled` for the Google
Francka mainboard variant. This overrides the default weak HDA common
initialization.

Initialization of the High Definition Audio (HDA) controller, managed by
`azalia_audio_init()` (which handles HDA verb table loading), is now
conditional. It proceeds only if the firmware config
`FW_CONFIG(AUDIO, AUDIO_ALC256M_CG_HDA)` is set. This targets the
ALC256M-CG HDA codec.

This change ensures that HDA verb tables are loaded only when the
ALC256M-CG HDA codec is actively configured for the Francka variant.
Crucially, this prevents attempts to incorrectly load HDA verbs for
other audio interfaces, like SoundWire (SNDW), which might be present
in different Francka hardware configurations.

The header `intelblocks/hda.h` added to support this HDA initialization
logic.

BUG=b:ENTER_FRANCKA_BUG_ID_HERE
TEST=Verified HDA verb table loading is skipped on Francka platforms
     when configured with non-HDA audio codecs (e.g., SNDW),
     and proceeds as expected when ALC256M-CG HDA is configured

Change-Id: Idbc506c1ad180c7e8ecdec51c3491e6f0518204c
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87463
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Pranava Y N <pranavayn@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
---
 .../google/fatcat/variants/francka/variant.c  | 20 +++++++++++++++++++
 1 file changed, 20 insertions(+)

diff --git a/src/mainboard/google/fatcat/variants/francka/variant.c b/src/mainboard/google/fatcat/variants/francka/variant.c
index 0943ee18be..1ca6e41125 100644
--- a/src/mainboard/google/fatcat/variants/francka/variant.c
+++ b/src/mainboard/google/fatcat/variants/francka/variant.c
@@ -3,6 +3,7 @@
 #include <baseboard/variants.h>
 #include <fsp/api.h>
 #include <fw_config.h>
+#include <intelblocks/hda.h>
 
 void variant_update_soc_memory_init_params(FSPM_UPD *memupd)
 {
@@ -15,3 +16,22 @@ void variant_update_soc_memory_init_params(FSPM_UPD *memupd)
 		m_cfg->PchHdaSdiEnable[1] = false;
 	}
 }
+
+/*
+ * HDA verb table loading is supported based on the firmware configuration.
+ *
+ * This function determines if the current platform has an HDA codec enabled by
+ * examining the `FW_CONFIG` value. Specifically, it checks if the
+ * `FW_CONFIG` includes the `AUDIO_ALC256M_CG_HDA` value, which is used to identify
+ * Francka SKUs with HDA codec support.
+ *
+ * Return true if the `FW_CONFIG` indicates HDA support (i.e., contains
+ * `AUDIO_ALC256M_CG_HDA`), false otherwise.
+ */
+bool mainboard_is_hda_codec_enabled(void)
+{
+	if (fw_config_probe(FW_CONFIG(AUDIO, AUDIO_ALC256M_CG_HDA)))
+		return true;
+
+	return false;
+}

From c0920396d04f7b0369ee1ba9d3a02984bc599a7d Mon Sep 17 00:00:00 2001
From: Subrata Banik <subratabanik@google.com>
Date: Fri, 25 Apr 2025 12:51:01 +0530
Subject: [PATCH 0870/3886] mb/google/bluey: Make GSC_AP_INT GPIO configurable
 via Kconfig

This commit introduces a Kconfig option to define the GPIO pin used
for the Google Security Chip (GSC) to Application Processor (AP)
interrupt on the Bluey mainboard.

Previously, the GPIO_GSC_AP_INT was hardcoded to GPIO 34 in
board.h. This change makes it configurable for any future variants
using Qualcomm X1P-42-100 SoC.

BUG=b:404985109
TEST=Successfully built google/bluey with the Qualcomm x1p42100 SoC.

Change-Id: I5759667158082a80124bf3faa3c56aee50c1be34
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87450
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
---
 src/mainboard/google/bluey/Kconfig | 8 ++++++++
 src/mainboard/google/bluey/board.h | 3 ++-
 2 files changed, 10 insertions(+), 1 deletion(-)

diff --git a/src/mainboard/google/bluey/Kconfig b/src/mainboard/google/bluey/Kconfig
index 0746970bc5..5c74c81ac4 100644
--- a/src/mainboard/google/bluey/Kconfig
+++ b/src/mainboard/google/bluey/Kconfig
@@ -58,4 +58,12 @@ config EC_GOOGLE_CHROMEEC_SPI_BUS
 	hex
 	default 0xb
 
+config MAINBOARD_GPIO_PIN_FOR_GSC_AP_INTERRUPT
+	int
+	default 34
+	help
+	  This option specifies the GPIO pin number on the mainboard that is
+	  used for the interrupt line from the Google Security Chip (GSC) to the
+	  Application Processor (AP).
+
 endif # BOARD_GOOGLE_BLUEY_COMMON
diff --git a/src/mainboard/google/bluey/board.h b/src/mainboard/google/bluey/board.h
index f7c4f23d91..618eadce2a 100644
--- a/src/mainboard/google/bluey/board.h
+++ b/src/mainboard/google/bluey/board.h
@@ -7,7 +7,8 @@
 #include <gpio.h>
 
 #define GPIO_AP_EC_INT		GPIO(67)
-#define GPIO_GSC_AP_INT		GPIO(34)
+#define GSC_AP_INT(x)		GPIO(x)
+#define GPIO_GSC_AP_INT		GSC_AP_INT(CONFIG_MAINBOARD_GPIO_PIN_FOR_GSC_AP_INTERRUPT)
 
 void setup_chromeos_gpios(void);
 

From 08722cd9f95de5f2c5625f3e12f3129bcdfce4fa Mon Sep 17 00:00:00 2001
From: Yunlong Jia <yunlong.jia@ecs.corp-partner.google.com>
Date: Thu, 24 Apr 2025 08:50:15 +0000
Subject: [PATCH 0871/3886] mb/google/dedede/var/beadrix: Add Ziliatech part to
 RAM ID table

Add Ziliatech SDVB8D8A34XGCL3N3T as id 2, resulting in the list below:

DRAM Part Name                 ID to assign
MT53E512M32D1NP-046 WT:B       0 (0000)
K4U6E3S4AA-MGCR                0 (0000)
H54G46CYRBX267                 0 (0000)
CXDB4CBAM-ML-A                 1 (0001)
SDVB8D8A34XGCL3N3T             2 (0010)

BUG=b:398700043
BRANCH=None
TEST=Use part_id_gen to generate related settings

Signed-off-by: Yunlong Jia <yunlong.jia@ecs.corp-partner.google.com>
Change-Id: If85ea78828ab520d10dcbe4ccbba685ac1746c51
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87440
Reviewed-by: Derek Huang <derekhuang@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
---
 src/mainboard/google/dedede/variants/beadrix/memory/Makefile.mk  | 1 +
 .../google/dedede/variants/beadrix/memory/dram_id.generated.txt  | 1 +
 .../google/dedede/variants/beadrix/memory/mem_parts_used.txt     | 1 +
 3 files changed, 3 insertions(+)

diff --git a/src/mainboard/google/dedede/variants/beadrix/memory/Makefile.mk b/src/mainboard/google/dedede/variants/beadrix/memory/Makefile.mk
index d260b55866..74955edb8d 100644
--- a/src/mainboard/google/dedede/variants/beadrix/memory/Makefile.mk
+++ b/src/mainboard/google/dedede/variants/beadrix/memory/Makefile.mk
@@ -6,3 +6,4 @@
 SPD_SOURCES =
 SPD_SOURCES += spd/lp4x/set-1/spd-1.hex      # ID = 0(0b0000)  Parts = MT53E512M32D1NP-046 WT:B, K4U6E3S4AA-MGCR, H54G46CYRBX267
 SPD_SOURCES += spd/lp4x/set-1/spd-11.hex      # ID = 1(0b0001)  Parts = CXDB4CBAM-ML-A
+SPD_SOURCES += spd/lp4x/set-1/spd-5.hex      # ID = 2(0b0010)  Parts = SDVB8D8A34XGCL3N3T
diff --git a/src/mainboard/google/dedede/variants/beadrix/memory/dram_id.generated.txt b/src/mainboard/google/dedede/variants/beadrix/memory/dram_id.generated.txt
index ddbed1a22d..080e808939 100644
--- a/src/mainboard/google/dedede/variants/beadrix/memory/dram_id.generated.txt
+++ b/src/mainboard/google/dedede/variants/beadrix/memory/dram_id.generated.txt
@@ -8,3 +8,4 @@ MT53E512M32D1NP-046 WT:B       0 (0000)
 K4U6E3S4AA-MGCR                0 (0000)
 H54G46CYRBX267                 0 (0000)
 CXDB4CBAM-ML-A                 1 (0001)
+SDVB8D8A34XGCL3N3T             2 (0010)
diff --git a/src/mainboard/google/dedede/variants/beadrix/memory/mem_parts_used.txt b/src/mainboard/google/dedede/variants/beadrix/memory/mem_parts_used.txt
index 56e9d6e249..d95fdb6cd5 100644
--- a/src/mainboard/google/dedede/variants/beadrix/memory/mem_parts_used.txt
+++ b/src/mainboard/google/dedede/variants/beadrix/memory/mem_parts_used.txt
@@ -13,3 +13,4 @@ MT53E512M32D1NP-046 WT:B
 K4U6E3S4AA-MGCR
 H54G46CYRBX267
 CXDB4CBAM-ML-A
+SDVB8D8A34XGCL3N3T

From 4b871c6314cbd75692e74d1a91ca43719aa03b8c Mon Sep 17 00:00:00 2001
From: Wonkyu Kim <wonkyu.kim@intel.com>
Date: Wed, 9 Apr 2025 09:52:44 -0700
Subject: [PATCH 0872/3886] ec/intel: read board ID one time from EC per stage

Use a static variable to cache the board ID. It optimizes boot time by
reading the ID once per stage and retaining it for subsequent use.
Rewrite the function to avoid the unnecessary ChromeEC wrapper function.

Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com>
Change-Id: I166ca1abdf7838f91319d0bcf11354055ed93eef
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87247
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/ec/intel/board_id.c | 53 ++++++++++++++++++++++++++---------------
 1 file changed, 34 insertions(+), 19 deletions(-)

diff --git a/src/ec/intel/board_id.c b/src/ec/intel/board_id.c
index 72d74c51f0..028c4e103e 100644
--- a/src/ec/intel/board_id.c
+++ b/src/ec/intel/board_id.c
@@ -2,32 +2,47 @@
 
 #include <boardid.h>
 #include "board_id.h"
+#include <console/console.h>
 #include <ec/acpi/ec.h>
 #include <ec/google/chromeec/ec.h>
 #include <types.h>
 
-static uint32_t get_board_id_via_ext_ec(void)
+static int intel_ec_get_board_version(uint32_t *id)
 {
-	uint32_t id = BOARD_ID_INIT;
+	if (send_ec_command(EC_FAB_ID_CMD))
+		return -1;
 
-	if (google_chromeec_get_board_version(&id))
+	*id = recv_ec_data() << 8 | recv_ec_data();
+	return 0;
+}
+
+/* Read Board ID from EC */
+int get_rvp_board_id(void)
+{
+	static uint32_t id = BOARD_ID_INIT;
+	const char *ec_type;
+	int ret;
+
+	/* If already initialized, return the cached board ID. */
+	if (id != BOARD_ID_INIT)
+		return id;
+
+	/* Reading board ID. */
+	if (CONFIG(EC_GOOGLE_CHROMEEC)) { /* Chrome EC */
+		ec_type = "ChromeEC";
+		ret = google_chromeec_get_board_version(&id);
+	} else { /* Intel EC */
+		ec_type = "IntelEC";
+		ret = intel_ec_get_board_version(&id);
+	}
+
+	if (ret == -1) {
 		id = BOARD_ID_UNKNOWN;
+		printk(BIOS_INFO, "[%s] board id: unknown\n", ec_type);
+	} else {
+		id &= BOARD_ID_MASK;
+		printk(BIOS_INFO, "[%s] board id: 0x%x\n", ec_type, id);
+	}
 
 	return id;
 }
-
-/* Get Board ID via EC I/O port write/read */
-int get_rvp_board_id(void)
-{
-	static int id = BOARD_ID_UNKNOWN;
-
-	if (CONFIG(EC_GOOGLE_CHROMEEC)) { /* CHROME_EC */
-		id = get_board_id_via_ext_ec();
-	} else { /* WINDOWS_EC */
-		if (send_ec_command(EC_FAB_ID_CMD) == 0) {
-			id = recv_ec_data() << 8;
-			id |= recv_ec_data();
-		}
-	}
-	return (id & BOARD_ID_MASK);
-}

From 2b598a94725e54a804bcd10fa3715b648916afc4 Mon Sep 17 00:00:00 2001
From: Keith Hui <buurin@gmail.com>
Date: Wed, 23 Apr 2025 15:01:02 -0400
Subject: [PATCH 0873/3886] drivers/net/r8168.c: Add option to program MAC
 address to ERI registers

On mainboard/asus/p8z77-v_le_plus, programmed MAC address is being
reverted with controller resets done at loading and unloading of Linux
r8169 kernel module.

Ghidra examination of vendor BIOS reveals an additional sequence to
program the MAC address into its ERI register block. This patch
adds code to replicate that sequence, gated by a Kconfig so it's
only included where necessary.

BUG=https://ticket.coreboot.org/issues/579
TEST=When applied with mainboard level changes in CB:87437, specified
MAC address now recognized and retained by Linux r8169 driver without
further work.

Change-Id: Iae33e24e564f9fba52acb16138fe89085d9eeb03
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87436
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/drivers/net/Kconfig | 10 ++++++++++
 src/drivers/net/r8168.c | 34 +++++++++++++++++++++++++++++++---
 2 files changed, 41 insertions(+), 3 deletions(-)

diff --git a/src/drivers/net/Kconfig b/src/drivers/net/Kconfig
index 8e087f7f6d..b8e5812b71 100644
--- a/src/drivers/net/Kconfig
+++ b/src/drivers/net/Kconfig
@@ -16,6 +16,16 @@ config REALTEK_8168_MACADDRESS
 	  hexadecimal number for it to be valid. Failing to do so will
 	  result in the default macaddress being used.
 
+config RT8168_PUT_MAC_TO_ERI
+	bool
+	help
+	  After programming MAC address into the regular rt8168 ID registers,
+	  also program it into ERI. On some mainboards our programmed
+	  MAC address will not survive a controller reset without this step.
+
+	  Select at mainboard level only if its rt8168 has no EEPROM and
+	  programmed MAC address is lost after booting to OS.
+
 config RT8168_GET_MAC_FROM_VPD
 	bool
 	default n
diff --git a/src/drivers/net/r8168.c b/src/drivers/net/r8168.c
index 6d93ed2dd7..8ef2ee8148 100644
--- a/src/drivers/net/r8168.c
+++ b/src/drivers/net/r8168.c
@@ -37,6 +37,8 @@
 #define  CFG_9346_UNLOCK	0xc0
 #define CMD_REG_ASPM		0xb0
 #define ASPM_L1_2_MASK		0xe059000f
+#define ERIDR			0x70
+#define ERIAR			0x74
 
 #define DEVICE_INDEX_BYTE	12
 #define MAX_DEVICE_SUPPORT	10
@@ -200,6 +202,7 @@ static void get_mac_address(u8 *macaddr, const u8 *strbuf)
 static void program_mac_address(struct device *dev, u16 io_base)
 {
 	u8 macstrbuf[MACLEN] = { 0 };
+	u32 maclo, machi;
 	int i = 0;
 	/* Default MAC Address of 00:E0:4C:00:C0:B0 */
 	u8 mac[6] = { 0x00, 0xe0, 0x4c, 0x00, 0xc0, 0xb0 };
@@ -234,11 +237,36 @@ static void program_mac_address(struct device *dev, u16 io_base)
 	outb(CFG_9346_UNLOCK, io_base + CFG_9346);
 
 	/* Set MAC address: only 4-byte write accesses allowed */
-	outl(mac[4] | mac[5] << 8, io_base + 4);
+	maclo = mac[0] | mac[1] << 8 | mac[2] << 16 | mac[3] << 24;
+	machi = mac[4] | mac[5] << 8;
+	outl(machi, io_base + 4);
 	inl(io_base + 4);
-	outl(mac[0] | mac[1] << 8 | mac[2] << 16 | mac[3] << 24,
-		io_base);
+	outl(maclo, io_base);
 	inl(io_base);
+	/* Some boards (e.g. asus/p8z77-v_le_plus) need the MAC address set here too */
+	if (CONFIG(RT8168_PUT_MAC_TO_ERI)) {
+		switch (pci_read_config8(dev, PCI_REVISION_ID)) {
+		case 6:
+			outl((maclo & 0xffff) << 16, io_base + ERIDR);
+			inl(io_base + ERIDR);
+			outl(0x8000f0f0, io_base + ERIAR);
+			inl(io_base + ERIAR);
+			outl((machi << 16 | maclo >> 16), io_base + ERIDR);
+			inl(io_base + ERIDR);
+			outl(0x8000f0f4, io_base + ERIAR);
+			break;
+		case 9:
+			outl(maclo, io_base + ERIDR);
+			inl(io_base + ERIDR);
+			outl(0x8000f0e0, io_base + ERIAR);
+			inl(io_base + ERIAR);
+			outl(machi, io_base + ERIDR);
+			inl(io_base + ERIDR);
+			outl(0x800030e4, io_base + ERIAR);
+			break;
+		}
+		udelay(1000);
+	}
 	/* Lock config regs */
 	outb(CFG_9346_LOCK, io_base + CFG_9346);
 

From 9f98a2a78a21ccd6603b2f85618d4cd9b60f4d9e Mon Sep 17 00:00:00 2001
From: Keith Hui <buurin@gmail.com>
Date: Wed, 23 Apr 2025 15:17:54 -0400
Subject: [PATCH 0874/3886] mb/asus/p8z77-v_le_plus: Use additional rt8168 MAC
 programming

Use an additional Realtek NIC MAC programming sequence recently
added to drivers/net/r8168.c.

BUG=https://ticket.coreboot.org/issues/579
TEST=Specified MAC address now recognized and retained by Linux r8169
driver without further work.

Change-Id: Ia1409874920b2e598e8b8b3c186fc46bd0cef296
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87437
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 Documentation/mainboard/asus/p8z77-v_le_plus.md | 2 --
 src/mainboard/asus/p8x7x-series/Kconfig         | 1 +
 2 files changed, 1 insertion(+), 2 deletions(-)

diff --git a/Documentation/mainboard/asus/p8z77-v_le_plus.md b/Documentation/mainboard/asus/p8z77-v_le_plus.md
index 2664127a4e..dc80eeb8c3 100644
--- a/Documentation/mainboard/asus/p8z77-v_le_plus.md
+++ b/Documentation/mainboard/asus/p8z77-v_le_plus.md
@@ -100,8 +100,6 @@ See "PCIe config" section below for more details.
 
 ## Known issues
 
-- RTL8111F here has no EEPROM for vital product data such as MAC address, which is also not
-  being properly programmed. You may need to fuse your MAC address with [rtnicpg] instead.
 - For 7.1 analog audio to work, at least the front channel (green jack) must be connected.
 
 ## Untested
diff --git a/src/mainboard/asus/p8x7x-series/Kconfig b/src/mainboard/asus/p8x7x-series/Kconfig
index e3e977f00e..112d861f94 100644
--- a/src/mainboard/asus/p8x7x-series/Kconfig
+++ b/src/mainboard/asus/p8x7x-series/Kconfig
@@ -62,6 +62,7 @@ config BOARD_ASUS_P8Z77_V_LE_PLUS
 	select BOARD_ASUS_P8X7X_SERIES
 	select BOARD_ROMSIZE_KB_8192
 	select RT8168_SET_LED_MODE
+	select RT8168_PUT_MAC_TO_ERI
 	select SUPERIO_NUVOTON_NCT6779D
 	select USE_NATIVE_RAMINIT
 	select POWER_LED_USES_GPIO8

From e2705d93d8186ceddcba6995f503559e01ee917f Mon Sep 17 00:00:00 2001
From: Subrata Banik <subratabanik@google.com>
Date: Sat, 26 Apr 2025 22:56:14 +0530
Subject: [PATCH 0875/3886] soc/intel/pantherlake: Reduce IGD stolen memory
 size from 128MB to 64MB
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

This commit updates the pre-allocated IGD stolen memory size for Intel
Panther Lake SoCs from 128MB to 64MB within the FSP-M configuration
parameters.

Reducing the IGD stolen memory allocation from 128MB to 64MB
significantly optimizes system memory resource utilization (by 64MB).

Furthermore, this reduction frees one MTRR. Previously, the 128MB IGD
allocation consumed all 10 available BIOS MTRRs; the new 64MB allocation
now leaves MTRR index 9 available.

BUG=b:413638298
TEST=Able to boot google/fatcat to OS w/ internal and/or external
display attached.

Change-Id: Ifd60973bc5d37cbbc4ea6c8eaf5d851069d53083
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87460
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
---
 src/soc/intel/pantherlake/romstage/fsp_params.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/soc/intel/pantherlake/romstage/fsp_params.c b/src/soc/intel/pantherlake/romstage/fsp_params.c
index b83eb18c7a..3f13be2735 100644
--- a/src/soc/intel/pantherlake/romstage/fsp_params.c
+++ b/src/soc/intel/pantherlake/romstage/fsp_params.c
@@ -36,8 +36,8 @@ static void fill_fspm_igd_params(FSP_M_CONFIG *m_cfg,
 	};
 	m_cfg->InternalGraphics = !CONFIG(SOC_INTEL_DISABLE_IGD) && is_devfn_enabled(PCI_DEVFN_IGD);
 	if (m_cfg->InternalGraphics) {
-		/* IGD is enabled, set IGD stolen size to 128MB. */
-		m_cfg->IgdDvmt50PreAlloc = IGD_SM_128MB;
+		/* IGD is enabled, set IGD stolen size to 64MB. */
+		m_cfg->IgdDvmt50PreAlloc = IGD_SM_64MB;
 		/* DP port config */
 		m_cfg->DdiPortAConfig = config->ddi_port_A_config;
 		m_cfg->DdiPortBConfig = config->ddi_port_B_config;

From 9660279966a4fee54ad5002f24f4b63749b446eb Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Tue, 15 Apr 2025 20:09:50 +0100
Subject: [PATCH 0876/3886] drivers/usb/intel_bluetooth: Hook RTD3 up to the
 option API

This makes Bluetooth RTD3 runtime configurable.

Change-Id: I467634e013a140e0a39802d2a1767583ba33a76e
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87326
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
---
 src/drivers/usb/acpi/intel_bluetooth.c | 10 +++++++---
 1 file changed, 7 insertions(+), 3 deletions(-)

diff --git a/src/drivers/usb/acpi/intel_bluetooth.c b/src/drivers/usb/acpi/intel_bluetooth.c
index acefffc041..4c882cde9d 100644
--- a/src/drivers/usb/acpi/intel_bluetooth.c
+++ b/src/drivers/usb/acpi/intel_bluetooth.c
@@ -1,6 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
 #include <acpi/acpigen.h>
+#include <option.h>
 #include "chip.h"
 
 /*
@@ -51,7 +52,10 @@ void acpi_device_intel_bt(const struct acpi_gpio *enable_gpio,
 /*
  *	Name (_S0W, 3)
  */
-	acpigen_write_name_integer("_S0W", ACPI_DEVICE_SLEEP_D3_HOT);
+	if (get_uint_option("bluetooth_rtd3", 1))
+		acpigen_write_name_integer("_S0W", ACPI_DEVICE_SLEEP_D3_HOT);
+	else
+		acpigen_write_name_integer("_S0W", ACPI_DEVICE_SLEEP_D0);
 
 /*
  *	Name (_DSD, Package (0x02)
@@ -173,7 +177,7 @@ void acpi_device_intel_bt(const struct acpi_gpio *enable_gpio,
 
 		acpigen_write_method("_ON", 0);
 		{
-			if (enable_gpio->pin_count) {
+			if (get_uint_option("bluetooth_rtd3", 1) && enable_gpio->pin_count) {
 				acpigen_write_store();
 				acpigen_emit_namestring("\\_SB.PCI0.GBTE");
 				acpigen_emit_byte(LOCAL0_OP);
@@ -192,7 +196,7 @@ void acpi_device_intel_bt(const struct acpi_gpio *enable_gpio,
 
 		acpigen_write_method("_OFF", 0);
 		{
-			if (enable_gpio->pin_count) {
+			if (get_uint_option("bluetooth_rtd3", 1) && enable_gpio->pin_count) {
 				acpigen_emit_namestring("\\_SB.PCI0.SBTE");
 				acpigen_emit_byte(0);
 			}

From 2ce567f1d04253e28e9c0460fff873822a4cc6f8 Mon Sep 17 00:00:00 2001
From: Jeremy Soller <jackpot51@gmail.com>
Date: Thu, 21 Mar 2024 12:38:52 -0600
Subject: [PATCH 0877/3886] soc/intel/common/block/cse: Prevent HECI commands
 when flash descriptor override is set
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Sending the disable and EOP commands will not work if flash descriptor
override is set on Meteor Lake.

Change-Id: I3b5a56229434c9cc326141d48359faa7759541ee
Signed-off-by: Jeremy Soller <Jeremy@system76.com>
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82728
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michał Kopeć <michal.kopec@3mdeb.com>
---
 src/soc/intel/common/block/cse/cse.c                     | 8 ++++++++
 src/soc/intel/common/block/cse/cse_eop.c                 | 6 ++++++
 src/soc/intel/common/block/fast_spi/fast_spi.c           | 9 +++++++++
 .../intel/common/block/include/intelblocks/fast_spi.h    | 4 ++++
 4 files changed, 27 insertions(+)

diff --git a/src/soc/intel/common/block/cse/cse.c b/src/soc/intel/common/block/cse/cse.c
index 55dd3d2da7..29a0c2192b 100644
--- a/src/soc/intel/common/block/cse/cse.c
+++ b/src/soc/intel/common/block/cse/cse.c
@@ -11,6 +11,7 @@
 #include <device/pci_ids.h>
 #include <device/pci_ops.h>
 #include <intelblocks/cse.h>
+#include <intelblocks/fast_spi.h>
 #include <intelblocks/me.h>
 #include <intelblocks/pmclib.h>
 #include <intelblocks/post_codes.h>
@@ -1348,6 +1349,13 @@ static void cse_set_state(struct device *dev)
 
 	int send;
 	int result;
+
+	if (fast_spi_flash_descriptor_override()) {
+		printk(BIOS_WARNING, "HECI: not setting ME state because "
+			"flash descriptor override is enabled\n");
+		return;
+	}
+
 	/*
 	 * Check if the CMOS value "me_state" exists, if it doesn't, then
 	 * don't do anything.
diff --git a/src/soc/intel/common/block/cse/cse_eop.c b/src/soc/intel/common/block/cse/cse_eop.c
index 265fe04bbc..f2701d52da 100644
--- a/src/soc/intel/common/block/cse/cse_eop.c
+++ b/src/soc/intel/common/block/cse/cse_eop.c
@@ -4,6 +4,7 @@
 #include <bootstate.h>
 #include <console/console.h>
 #include <intelblocks/cse.h>
+#include <intelblocks/fast_spi.h>
 #include <intelblocks/pmc_ipc.h>
 #include <security/vboot/vboot_common.h>
 #include <soc/intel/common/reset.h>
@@ -243,6 +244,11 @@ static void do_send_end_of_post(bool wait_for_completion)
 		return;
 	}
 
+	if (fast_spi_flash_descriptor_override()) {
+		printk(BIOS_WARNING, "CSE: not sending EOP because flash descriptor override is enabled\n");
+		return;
+	}
+
 	if (!eop_sent) {
 		set_cse_device_state(PCH_DEVFN_CSE, DEV_ACTIVE);
 		timestamp_add_now(TS_ME_END_OF_POST_START);
diff --git a/src/soc/intel/common/block/fast_spi/fast_spi.c b/src/soc/intel/common/block/fast_spi/fast_spi.c
index 45519611ab..8cff0707b6 100644
--- a/src/soc/intel/common/block/fast_spi/fast_spi.c
+++ b/src/soc/intel/common/block/fast_spi/fast_spi.c
@@ -472,6 +472,15 @@ void fast_spi_clear_outstanding_status(void)
 	write32(spibar + SPIBAR_HSFSTS_CTL, SPIBAR_HSFSTS_W1C_BITS);
 }
 
+/* Check if flash descriptor override is asserted */
+bool fast_spi_flash_descriptor_override(void)
+{
+	void *spibar = fast_spi_get_bar();
+	uint32_t hsfsts = read32(spibar + SPIBAR_HSFSTS_CTL);
+	printk(BIOS_DEBUG, "HSFSTS: 0x%X\n", hsfsts);
+	return !(hsfsts & SPIBAR_HSFSTS_FDOPSS);
+}
+
 
 /* As there is no official ACPI ID for this controller use the generic PNP ID for now. */
 static const char *fast_spi_acpi_hid(const struct device *dev)
diff --git a/src/soc/intel/common/block/include/intelblocks/fast_spi.h b/src/soc/intel/common/block/include/intelblocks/fast_spi.h
index 716f16a07a..6c28f25430 100644
--- a/src/soc/intel/common/block/include/intelblocks/fast_spi.h
+++ b/src/soc/intel/common/block/include/intelblocks/fast_spi.h
@@ -107,5 +107,9 @@ void fast_spi_cache_ext_bios_postcar(struct postcar_frame *pcf);
  * Set FAST_SPIBAR BIOS Decode Lock bit
  */
 void fast_spi_set_bde(void);
+/*
+ * Check if flash descriptor override is asserted
+ */
+bool fast_spi_flash_descriptor_override(void);
 
 #endif	/* SOC_INTEL_COMMON_BLOCK_FAST_SPI_H */

From a4a2cdeb17fd44978d31567a360d4f6a4519d721 Mon Sep 17 00:00:00 2001
From: Appukuttan V K <appukuttan.vk@intel.com>
Date: Fri, 25 Apr 2025 13:56:54 +0530
Subject: [PATCH 0878/3886] soc/intel/ptl: Add GPIOs for Wildcat Lake SoC

This patch introduces GPIO changes for the Wildcat Lake SoC.
These changes coexist with the Panther Lake SoC GPIO files.

Key Changes:
  - The CPUJTAG group is moved from community 3 to community 4.
  - A new pin is added to Group H.
  - Wildcat Lake-specific register definitions are included.
  - Kconfig is utilized to segregate Wildcat Lake GPIO changes.

References:
- Wildcat Lake External Design Specification (EDS) Volume 2 (#829345)
- Wildcat Lake GPIO Implementation Summary (#836031)

BUG=b:394208231
TEST=Both Ocelot and Fatcat variants are built

Change-Id: Ib364d41097c53cd085c6cf89b0461ce38117b21e
Signed-off-by: Appukuttan V K <appukuttan.vk@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87452
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
---
 src/soc/intel/pantherlake/gpio.c              |  27 +-
 .../intel/pantherlake/include/soc/gpio_defs.h |  28 +-
 .../pantherlake/include/soc/gpio_soc_defs.h   | 270 +++++++++++-------
 3 files changed, 221 insertions(+), 104 deletions(-)

diff --git a/src/soc/intel/pantherlake/gpio.c b/src/soc/intel/pantherlake/gpio.c
index 581607d4e3..8b1257e17a 100644
--- a/src/soc/intel/pantherlake/gpio.c
+++ b/src/soc/intel/pantherlake/gpio.c
@@ -32,6 +32,18 @@ static const struct pad_group ptl_community1_groups[] = {
 	INTEL_GPP_BASE(GPP_F00, GPP_E00, GPP_THC0_GSPI_CLK_LPBK, 32),	/* GPP_E */
 };
 
+#if CONFIG(SOC_INTEL_WILDCATLAKE)
+static const struct pad_group ptl_community3_groups[] = {
+	INTEL_GPP_BASE(GPP_H00, GPP_H00, GPP_SHD3C_CLK_LPBK, 0),	/* GPP_H */
+	INTEL_GPP_BASE(GPP_H00, GPP_A00, GPP_SPI0_CLK_LOOPBK, 32),	/* GPP_A */
+	INTEL_GPP(GPP_H00, GPP_VGPIO3_USB0, GPP_VGPIO3_THC3),		/* GPP_VGPIO_3*/
+};
+
+static const struct pad_group ptl_community4_groups[] = {
+	INTEL_GPP_BASE(GPP_S00, GPP_S00, GPP_S07, 0),			/* GPP_S */
+	INTEL_GPP(GPP_S00, GPP_EPD_ON, GPP_DDSP_HPDALV),		/* GPP_CPUJTAG */
+};
+#else
 static const struct pad_group ptl_community3_groups[] = {
 	INTEL_GPP(GPP_EPD_ON, GPP_EPD_ON, GPP_DDSP_HPDALV),		/* GPP_CPUJTAG */
 	INTEL_GPP_BASE(GPP_EPD_ON, GPP_H00, GPP_ISHI3C1_CLK_LPBK, 32),	/* GPP_H */
@@ -42,6 +54,7 @@ static const struct pad_group ptl_community3_groups[] = {
 static const struct pad_group ptl_community4_groups[] = {
 	INTEL_GPP_BASE(GPP_S00, GPP_S00, GPP_S07, 0),			/* GPP_S */
 };
+#endif
 
 static const struct pad_group ptl_community5_groups[] = {
 	INTEL_GPP_BASE(GPP_B00, GPP_B00, GPP_ISHI3C0_CLK_LPBK, 0),	/* GPP_B */
@@ -94,7 +107,8 @@ static const struct pad_community ptl_communities[] = {
 		.groups = ptl_community1_groups,
 		.num_groups = ARRAY_SIZE(ptl_community1_groups),
 	},
-	[COMM_3] = { /* GPP: CPUJTAG, H, A, VGPIO3 */
+	[COMM_3] = { /* GPP: CPUJTAG, H, A, VGPIO3 for PTL
+			GPP: H, A, VGPIO3 for WCL */
 		.port = PID_GPIOCOM3,
 		.first_pad = COM3_GRP_PAD_START,
 		.last_pad = COM3_GRP_PAD_END,
@@ -109,14 +123,19 @@ static const struct pad_community ptl_communities[] = {
 		.gpi_smi_sts_reg_0 = GPI_SMI_STS_0,
 		.gpi_smi_en_reg_0 = GPI_SMI_EN_0,
 		.max_pads_per_group = GPIO_MAX_NUM_PER_GROUP,
+#if CONFIG(SOC_INTEL_WILDCATLAKE)
+		.name = "GPP_H_A_VGPIO3",
+#else
 		.name = "GPP_CPUJTAG_H_A_VGPIO3",
+#endif
 		.acpi_path = "\\_SB.PCI0.GPI3",
 		.reset_map = rst_map,
 		.num_reset_vals = ARRAY_SIZE(rst_map),
 		.groups = ptl_community3_groups,
 		.num_groups = ARRAY_SIZE(ptl_community3_groups),
 	},
-	[COMM_4] = { /* GPP: S */
+	[COMM_4] = { /* GPP: S for PTL
+			GPP: S, CPUJTAG for WCL */
 		.port = PID_GPIOCOM4,
 		.first_pad = COM4_GRP_PAD_START,
 		.last_pad = COM4_GRP_PAD_END,
@@ -131,7 +150,11 @@ static const struct pad_community ptl_communities[] = {
 		.gpi_smi_sts_reg_0 = GPI_SMI_STS_0,
 		.gpi_smi_en_reg_0 = GPI_SMI_EN_0,
 		.max_pads_per_group = GPIO_MAX_NUM_PER_GROUP,
+#if CONFIG(SOC_INTEL_WILDCATLAKE)
+		.name = "GPP_S_CPUJTAG",
+#else
 		.name = "GPP_S",
+#endif
 		.acpi_path = "\\_SB.PCI0.GPI4",
 		.reset_map = rst_map,
 		.num_reset_vals = ARRAY_SIZE(rst_map),
diff --git a/src/soc/intel/pantherlake/include/soc/gpio_defs.h b/src/soc/intel/pantherlake/include/soc/gpio_defs.h
index 2c6a8101d6..e99859390c 100644
--- a/src/soc/intel/pantherlake/include/soc/gpio_defs.h
+++ b/src/soc/intel/pantherlake/include/soc/gpio_defs.h
@@ -242,10 +242,33 @@
 #define GPE_DW_SHIFT		8
 #define GPE_DW_MASK		0xfff00
 #define PAD_OWN_REG_0		0x130
-#define PAD_CFG_LOCK_REG_0	0x290
-#define HOSTSW_OWN_REG_0	0x2c0
 #define GPI_INT_STS_0		0x300
 #define GPI_INT_EN_0		0x310
+#if CONFIG(SOC_INTEL_WILDCATLAKE)
+#define PAD_CFG_LOCK_REG_0	0x250
+#define HOSTSW_OWN_REG_0	0x270
+#define GPI_GPE_STS_0		0x320
+#define GPI_GPE_EN_0		0x330
+#define GPI_SMI_STS_0		0x344
+#define GPI_SMI_EN_0		0x354
+#define GPI_NMI_STS_0		0x364
+#define GPI_NMI_EN_0		0x374
+#define PAD_CFG_BASE		0x700
+#define GPP_V_START_OFFSET		0x700
+#define GPP_C_START_OFFSET		0x880
+#define GPP_F_START_OFFSET		0x700
+#define GPP_E_START_OFFSET		0x8a0
+#define GPP_RSVD_START_OFFSET	0x780
+#define GPP_H_START_OFFSET		0x700
+#define GPP_A_START_OFFSET		0x8d0
+#define GPP_VGPIO3_START_OFFSET		0xA90
+#define GPP_S_START_OFFSET		0x700
+#define GPP_B_START_OFFSET		0x700
+#define GPP_D_START_OFFSET		0x8b0
+#define GPP_VGPIO_START_OFFSET		0xA50
+#else
+#define PAD_CFG_LOCK_REG_0	0x290
+#define HOSTSW_OWN_REG_0	0x2c0
 #define GPI_GPE_STS_0		0x330
 #define GPI_GPE_EN_0		0x350
 #define GPI_SMI_STS_0		0x370
@@ -273,5 +296,6 @@
 #define GPP_B_START_OFFSET		0x800
 #define GPP_D_START_OFFSET		0x9b0
 #define GPP_VGPIO_START_OFFSET		0xb60
+#endif
 
 #endif //_SOC_PANTHERLAKE_GPIO_DEFS_H_
diff --git a/src/soc/intel/pantherlake/include/soc/gpio_soc_defs.h b/src/soc/intel/pantherlake/include/soc/gpio_soc_defs.h
index 49e34e0460..0ecd32a5ce 100644
--- a/src/soc/intel/pantherlake/include/soc/gpio_soc_defs.h
+++ b/src/soc/intel/pantherlake/include/soc/gpio_soc_defs.h
@@ -45,7 +45,11 @@
 #define GPP_D_NAME		"GPP_D"
 #define GPP_VGPIO_NAME		"vGPIO"
 
+#if CONFIG(SOC_INTEL_WILDCATLAKE)
+#define GPIO_MAX_NUM_PER_GROUP	29
+#else
 #define GPIO_MAX_NUM_PER_GROUP	28
+#endif
 
 #define COMM_0		0
 #define COMM_1		INC(COMM_0)
@@ -63,15 +67,15 @@
  */
 
 /*
- * +----------------------------+
- * |        Group V             |
- * +------------------+---------+
- * |                  | PTL-U/H |
- * +------------------+---------+
- * | Pad Start Number |    0    |
- * +------------------+---------+
- * | Pad End Number   |    23   |
- * +------------------+---------+
+ * +----------------------------------+
+ * |             Group V              |
+ * +------------------+---------------+
+ * |                  |  PTL-U/H/WCL  |
+ * +------------------+---------------+
+ * | Pad Start Number |       0       |
+ * +------------------+---------------+
+ * | Pad End Number   |      23       |
+ * +------------------+---------------+
  */
 #define GPP_V00			0
 #define GPP_V01			INC(GPP_V00)
@@ -103,15 +107,15 @@
 #define NUM_GPP_V_PADS		(GPP_V17 - GPP_V00 + 1)
 
 /*
- * +----------------------------+
- * |        Group C             |
- * +------------------+---------+
- * |                  | PTL-UH/H|
- * +------------------+---------+
- * | Pad Start Number |    24   |
- * +------------------+---------+
- * | Pad End Number   |    47   |
- * +------------------+---------+
+ * +----------------------------------+
+ * |             Group C              |
+ * +------------------+---------------+
+ * |                  |  PTL-U/H/WCL  |
+ * +------------------+---------------+
+ * | Pad Start Number |      24       |
+ * +------------------+---------------+
+ * | Pad End Number   |      47       |
+ * +------------------+---------------+
  */
 #define GPP_C00			INC(GPP_RST_B)
 #define GPP_C01			INC(GPP_C00)
@@ -154,15 +158,15 @@
  */
 
 /*
- * +----------------------------+
- * |        Group F             |
- * +------------------+---------+
- * |                  | PTL-UH/H|
- * +------------------+---------+
- * | Pad Start Number |    48   |
- * +------------------+---------+
- * | Pad End Number   |    73   |
- * +------------------+---------+
+ * +----------------------------------+
+ * |             Group F              |
+ * +------------------+---------------+
+ * |                  |  PTL-U/H/WCL  |
+ * +------------------+---------------+
+ * | Pad Start Number |      48       |
+ * +------------------+---------------+
+ * | Pad End Number   |      73       |
+ * +------------------+---------------+
  */
 #define GPP_F00			INC(GPP_C23)
 #define GPP_F01			INC(GPP_F00)
@@ -195,15 +199,15 @@
 #define NUM_GPP_F_PADS		(GPP_F23 - GPP_F00 + 1)
 
 /*
- * +----------------------------+
- * |        Group E             |
- * +------------------+---------+
- * |                  | PTL-UH/H|
- * +------------------+---------+
- * | Pad Start Number |    74   |
- * +------------------+---------+
- * | Pad End Number   |    98   |
- * +------------------+---------+
+ * +----------------------------------+
+ * |             Group E              |
+ * +------------------+---------------+
+ * |                  |  PTL-U/H/WCL  |
+ * +------------------+---------------+
+ * | Pad Start Number |      74       |
+ * +------------------+---------------+
+ * | Pad End Number   |      98       |
+ * +------------------+---------------+
  *
  * NOTE: GPP_E00 is not a connected PAD in PTL and should be treated
  * as other internal used only PADs. It does not meant to be used.
@@ -250,6 +254,7 @@
  * +----------------------------+
  */
 
+#if (!CONFIG(SOC_INTEL_WILDCATLAKE))
 /*
  * +----------------------------+
  * |        Group CPUJTAG       |
@@ -280,19 +285,24 @@
 #define GPP_DDSP_HPDALV		INC(GPP_JTAG_TRST_B)
 
 #define NUM_GRP_RSVD_PADS	(GPP_DDSP_HPDALV - GPP_EPD_ON + 1)
+#endif
 
 /*
- * +----------------------------+
- * |        Group H             |
- * +------------------+---------+
- * |                  | PTL-UH/H|
- * +------------------+---------+
- * | Pad Start Number |    114  |
- * +------------------+---------+
- * | Pad End Number   |    141  |
- * +------------------+---------+
+ * +----------------------------------+
+ * |                Group H           |
+ * +------------------+---------+-----+
+ * |                  | PTL-UH/H| WCL |
+ * +------------------+---------+-----+
+ * | Pad Start Number |   114   |  99 |
+ * +------------------+---------+-----+
+ * | Pad End Number   |   141   | 127 |
+ * +------------------+---------+-----+
  */
+#if CONFIG(SOC_INTEL_WILDCATLAKE)
+#define GPP_H00			INC(GPP_THC0_GSPI_CLK_LPBK)
+#else
 #define GPP_H00			INC(GPP_DDSP_HPDALV)
+#endif
 #define GPP_H01			INC(GPP_H00)
 #define GPP_H02			INC(GPP_H01)
 #define GPP_H03			INC(GPP_H02)
@@ -320,22 +330,30 @@
 #define GPP_LPI3C1_CLK_LPBK	INC(GPP_H24)
 #define GPP_LPI3C0_CLK_LPBK	INC(GPP_LPI3C1_CLK_LPBK)
 #define GPP_ISHI3C1_CLK_LPBK	INC(GPP_LPI3C0_CLK_LPBK)
-
+#if CONFIG(SOC_INTEL_WILDCATLAKE)
+#define GPP_SHD3C_CLK_LPBK	INC(GPP_ISHI3C1_CLK_LPBK)
+#define NUM_GRP_H_PADS		(GPP_SHD3C_CLK_LPBK - GPP_H00 + 1)
+#else
 #define NUM_GRP_H_PADS		(GPP_ISHI3C1_CLK_LPBK - GPP_H00 + 1)
+#endif
 #define NUM_GPP_H_PADS		(GPP_H24 - GPP_H00 + 1)
 
 /*
- * +----------------------------+
- * |        Group A             |
- * +------------------+---------+
- * |                  | PTL-UH/H|
- * +------------------+---------+
- * | Pad Start Number |    142  |
- * +------------------+---------+
- * | Pad End Number   |    169  |
- * +------------------+---------+
+ * +----------------------------------+
+ * |                Group A           |
+ * +------------------+---------+-----+
+ * |                  | PTL-UH/H| WCL |
+ * +------------------+---------+-----+
+ * | Pad Start Number |   142   | 128 |
+ * +------------------+---------+-----+
+ * | Pad End Number   |   169   | 155 |
+ * +------------------+---------+-----+
  */
+#if CONFIG(SOC_INTEL_WILDCATLAKE)
+#define GPP_A00			INC(GPP_SHD3C_CLK_LPBK)
+#else
 #define GPP_A00			INC(GPP_ISHI3C1_CLK_LPBK)
+#endif
 #define GPP_A01			INC(GPP_A00)
 #define GPP_A02			INC(GPP_A01)
 #define GPP_A03			INC(GPP_A02)
@@ -369,15 +387,15 @@
 #define NUM_GPP_A_PADS		(GPP_A17 - GPP_A00 + 1)
 
 /*
- * +----------------------------+
- * |        Group vGPIO3        |
- * +------------------+---------+
- * |                  | PTL-UH/H|
- * +------------------+---------+
- * | Pad Start Number |    170  |
- * +------------------+---------+
- * | Pad End Number   |    183  |
- * +------------------+---------+
+ * +----------------------------------+
+ * |              Group vGPIO3        |
+ * +------------------+---------+-----+
+ * |                  | PTL-UH/H| WCL |
+ * +------------------+---------+-----+
+ * | Pad Start Number |    170  | 156 |
+ * +------------------+---------+-----+
+ * | Pad End Number   |    183  | 169 |
+ * +------------------+---------+-----+
  */
 #define GPP_VGPIO3_USB0		INC(GPP_SPI0_CLK_LOOPBK)
 #define GPP_VGPIO3_USB1		INC(GPP_VGPIO3_USB0)
@@ -396,11 +414,19 @@
 
 #define NUM_GRP_VGPIO3_PADS	(GPP_VGPIO3_THC3 - GPP_VGPIO3_USB0 + 1)
 
+#if CONFIG(SOC_INTEL_WILDCATLAKE)
+#define COM3_GRP_PAD_START	GPP_H00
+#define COM3_GRP_PAD_END	GPP_VGPIO3_THC3
+#define NUM_COM3_GRP_PADS	(GPP_VGPIO3_THC3 - GPP_H00 + 1)
+#define NUM_COM3_GPP_PADS	(NUM_GPP_H_PADS + NUM_GPP_A_PADS)
+#define NUM_COM3_GROUPS		3
+#else
 #define COM3_GRP_PAD_START	GPP_EPD_ON
 #define COM3_GRP_PAD_END	GPP_VGPIO3_THC3
 #define NUM_COM3_GRP_PADS	(GPP_VGPIO3_THC3 - GPP_EPD_ON + 1)
 #define NUM_COM3_GPP_PADS	(NUM_GPP_H_PADS + NUM_GPP_A_PADS)
 #define NUM_COM3_GROUPS		4
+#endif
 
 /*
  * +----------------------------+
@@ -409,15 +435,15 @@
  */
 
 /*
- * +----------------------------+
- * |        Group S             |
- * +------------------+---------+
- * |                  | PTL-UH/H|
- * +------------------+---------+
- * | Pad Start Number |    184  |
- * +------------------+---------+
- * | Pad End Number   |    191  |
- * +------------------+---------+
+ * +----------------------------------+
+ * |                Group S           |
+ * +------------------+---------+-----+
+ * |                  | PTL-UH/H| WCL |
+ * +------------------+---------+-----+
+ * | Pad Start Number |    184  | 170 |
+ * +------------------+---------+-----+
+ * | Pad End Number   |    191  | 177 |
+ * +------------------+---------+-----+
  */
 #define GPP_S00			INC(GPP_VGPIO3_THC3)
 #define GPP_S01			INC(GPP_S00)
@@ -431,11 +457,51 @@
 #define NUM_GRP_S_PADS		(GPP_S07 - GPP_S00 + 1)
 #define NUM_GPP_S_PADS		(GPP_S07 - GPP_S00 + 1)
 
+#if CONFIG(SOC_INTEL_WILDCATLAKE)
+/*
+ * +------------------------+
+ * |      Group CPUJTAG     |
+ * +------------------+-----+
+ * |                  | WCL |
+ * +------------------+-----+
+ * | Pad Start Number | 178 |
+ * +------------------+-----+
+ * | Pad End Number   | 192 |
+ * +------------------+-----+
+ */
+
+#define GPP_EPD_ON		INC(GPP_S07)
+#define GPP_VDD2_PWRGD		INC(GPP_EPD_ON)
+
+#define GPP_JTAG_MBPB0		INC(GPP_VDD2_PWRGD)
+#define GPP_JTAG_MBPB1		INC(GPP_JTAG_MBPB0)
+#define GPP_JTAG_MBPB2		INC(GPP_JTAG_MBPB1)
+#define GPP_JTAG_MBPB3		INC(GPP_JTAG_MBPB2)
+#define GPP_JTAG_TD0		INC(GPP_JTAG_MBPB3)
+#define GPP_PRDY_B		INC(GPP_JTAG_TD0)
+#define GPP_PREQ_B		INC(GPP_PRDY_B)
+#define GPP_JTAG_TDI		INC(GPP_PREQ_B)
+#define GPP_JTAG_TMS		INC(GPP_JTAG_TDI)
+#define GPP_JTAG_TCK		INC(GPP_JTAG_TMS)
+#define GPP_DBG_PMODE		INC(GPP_JTAG_TCK)
+#define GPP_JTAG_TRST_B		INC(GPP_DBG_PMODE)
+#define GPP_DDSP_HPDALV		INC(GPP_JTAG_TRST_B)
+
+#define NUM_GRP_RSVD_PADS	(GPP_DDSP_HPDALV - GPP_EPD_ON + 1)
+#endif
 #define COM4_GRP_PAD_START	GPP_S00
+
+#if CONFIG(SOC_INTEL_WILDCATLAKE)
+#define COM4_GRP_PAD_END	GPP_DDSP_HPDALV
+#define NUM_COM4_GRP_PADS	(GPP_DDSP_HPDALV - GPP_S00 + 1)
+#define NUM_COM4_GPP_PADS	(NUM_GPP_S_PADS)
+#define NUM_COM4_GROUPS		2
+#else
 #define COM4_GRP_PAD_END	GPP_S07
 #define NUM_COM4_GRP_PADS	(GPP_S07 - GPP_S00 + 1)
 #define NUM_COM4_GPP_PADS	(GPP_S07 - GPP_S00 + 1)
 #define NUM_COM4_GROUPS		1
+#endif
 
 /*
  * +----------------------------+
@@ -444,17 +510,21 @@
  */
 
 /*
- * +----------------------------+
- * |        Group B             |
- * +------------------+---------+
- * |                  | PTL-UH/H|
- * +------------------+---------+
- * | Pad Start Number |    192  |
- * +------------------+---------+
- * | Pad End Number   |    218  |
- * +------------------+---------+
+ * +----------------------------------+
+ * |              Group B             |
+ * +------------------+---------+-----+
+ * |                  | PTL-UH/H| WCL |
+ * +------------------+---------+-----+
+ * | Pad Start Number |    192  | 193 |
+ * +------------------+---------+-----+
+ * | Pad End Number   |    218  | 219 |
+ * +------------------+---------+-----+
  */
+#if CONFIG(SOC_INTEL_WILDCATLAKE)
+#define GPP_B00			INC(GPP_DDSP_HPDALV)
+#else
 #define GPP_B00			INC(GPP_S07)
+#endif
 #define GPP_B01			INC(GPP_B00)
 #define GPP_B02			INC(GPP_B01)
 #define GPP_B03			INC(GPP_B02)
@@ -486,15 +556,15 @@
 #define NUM_GPP_B_PADS		(GPP_B25 - GPP_B00 + 1)
 
 /*
- * +----------------------------+
- * |        Group D             |
- * +------------------+---------+
- * |                  | PTL-UH/H|
- * +------------------+---------+
- * | Pad Start Number |    219  |
- * +------------------+---------+
- * | Pad End Number   |    245  |
- * +------------------+---------+
+ * +----------------------------------+
+ * |              Group D             |
+ * +------------------+---------+-----+
+ * |                  | PTL-UH/H| WCL |
+ * +------------------+---------+-----+
+ * | Pad Start Number |    219  | 220 |
+ * +------------------+---------+-----+
+ * | Pad End Number   |    245  | 246 |
+ * +------------------+---------+-----+
  */
 #define GPP_D00			INC(GPP_ISHI3C0_CLK_LPBK)
 #define GPP_D01			INC(GPP_D00)
@@ -528,15 +598,15 @@
 #define NUM_GPP_D_PADS		(GPP_D25 - GPP_D00 + 1)
 
 /*
- * +----------------------------+
- * |        Group vGPIO         |
- * +------------------+---------+
- * |                  | PTL-UH/H|
- * +------------------+---------+
- * | Pad Start Number |    246  |
- * +------------------+---------+
- * | Pad End Number   |    263  |
- * +------------------+---------+
+ * +----------------------------------+
+ * |             Group vGPIO          |
+ * +------------------+---------+-----+
+ * |                  | PTL-UH/H| WCL |
+ * +------------------+---------+-----+
+ * | Pad Start Number |    246  | 247 |
+ * +------------------+---------+-----+
+ * | Pad End Number   |    263  | 264 |
+ * +------------------+---------+-----+
  */
 #define GPP_VGPIO0		INC(GPP_ISDI3C1_CLK_LPBK)
 #define GPP_VGPIO5		INC(GPP_VGPIO0)

From 4a89d1b77da68b82cc9abd28a0579335edaf375b Mon Sep 17 00:00:00 2001
From: Appukuttan V K <appukuttan.vk@intel.com>
Date: Mon, 28 Apr 2025 17:39:43 +0530
Subject: [PATCH 0879/3886] soc/intel/ptl: Add GPIO ACPI support for Wildcat
 Lake SoC
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Key changes:
 - Relocate the package corresponding to CPUJTAG group from GPI3
   device to the GPI4 device in the ACPI table, utilizing a Kconfig
   guard for conditional compilation.
 - Add ACPI IDs specific to Wildcat Lake GPIO communities.
 - Select SOC_INTEL_PANTHERLAKE_BASE for SOC_INTEL_WILDCATLAKE to
   clearly differentiate between Panther Lake and Wildcat Lake
   changes.

References:
- Wildcat Lake EDS Volume 2 (#829345)
- Wildcat Lake GPIO Implementation Summary (#836031)

BUG=b:394208231
TEST=Both Ocelot and Fatcat variants are built

Change-Id: I934c193c75e459c72cc8b01a575cc0bbd65dc273
Signed-off-by: Appukuttan V K <appukuttan.vk@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87474
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
---
 src/soc/intel/pantherlake/Kconfig            |  2 +-
 src/soc/intel/pantherlake/acpi/gpio.asl      | 69 ++++++++++++++++++++
 src/soc/intel/pantherlake/include/soc/gpio.h |  9 +++
 3 files changed, 79 insertions(+), 1 deletion(-)

diff --git a/src/soc/intel/pantherlake/Kconfig b/src/soc/intel/pantherlake/Kconfig
index b1bff143a9..beda98acbe 100644
--- a/src/soc/intel/pantherlake/Kconfig
+++ b/src/soc/intel/pantherlake/Kconfig
@@ -127,7 +127,7 @@ config SOC_INTEL_PANTHERLAKE_H
 
 config SOC_INTEL_WILDCATLAKE
 	bool
-	select SOC_INTEL_PANTHERLAKE_U_H
+	select SOC_INTEL_PANTHERLAKE_BASE
 	help
 	  Choose this option if the mainboard is built using WCL system-on-a-chip (SoC).
 
diff --git a/src/soc/intel/pantherlake/acpi/gpio.asl b/src/soc/intel/pantherlake/acpi/gpio.asl
index fe73b13b78..18df92dd38 100644
--- a/src/soc/intel/pantherlake/acpi/gpio.asl
+++ b/src/soc/intel/pantherlake/acpi/gpio.asl
@@ -506,6 +506,28 @@ Device (GPI3)
 		},
 
 		ToUUID ("dbb8e3e6-5886-4ba6-8795-1319f52a966b"),
+#if CONFIG(SOC_INTEL_WILDCATLAKE)
+		Package (0x03)
+		{
+			Package (0x02)
+			{
+				"intc-gpio-group-0-subproperties",
+				GPPH
+			},
+
+			Package (0x02)
+			{
+				"intc-gpio-group-1-subproperties",
+				GPPA
+			},
+
+			Package (0x02)
+			{
+				"intc-gpio-group-2-subproperties",
+				VGP3
+			}
+		}
+#else
 		Package (0x04)
 		{
 			Package (0x02)
@@ -532,7 +554,9 @@ Device (GPI3)
 				VGP3
 			}
 		}
+#endif
 	})
+#if (CONFIG(SOC_INTEL_PANTHERLAKE_U_H) || CONFIG(SOC_INTEL_PANTHERLAKE_H))
 	/* first bank/group in community 3: RSVD */
 	Name (RSVD, Package (0x02)
 	{
@@ -558,6 +582,7 @@ Device (GPI3)
 			}
 		}
 	})
+#endif
 	/* 2nd bank/group in community 3: GPP_H */
 	Name (GPPH, Package (0x02)
 	{
@@ -710,6 +735,22 @@ Device (GPI4)
 		},
 
 		ToUUID ("dbb8e3e6-5886-4ba6-8795-1319f52a966b"),
+#if CONFIG(SOC_INTEL_WILDCATLAKE)
+		Package (0x02)
+		{
+			Package (0x02)
+			{
+				"intc-gpio-group-0-subproperties",
+				GPPS
+			},
+
+			Package (0x02)
+			{
+				"intc-gpio-group-1-subproperties",
+				RSVD
+			}
+		}
+#else
 		Package (0x01)
 		{
 			Package (0x02)
@@ -718,6 +759,7 @@ Device (GPI4)
 				GPPS
 			}
 		}
+#endif
 	})
 	/* only bank/group in community 4: GPP_S */
 	Name (GPPS, Package (0x02)
@@ -744,6 +786,33 @@ Device (GPI4)
 			}
 		}
 	})
+#if CONFIG(SOC_INTEL_WILDCATLAKE)
+	/* second bank/group in community 4: RSVD */
+	Name (RSVD, Package (0x02)
+	{
+		ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+		Package (0x03)
+		{
+			Package (0x02)
+			{
+				"intc-gpio-group-name",
+				"RSVD"
+			},
+
+			Package (0x02)
+			{
+				"intc-gpio-pad-count",
+				NUM_GRP_RSVD_PADS
+			},
+
+			Package (0x02)
+			{
+				"intc-gpio-group-offset",
+				GPP_RSVD_START_OFFSET
+			}
+		}
+	})
+#endif
 	Method (_STA, 0, NotSerialized)
 	{
 		Return (0xF)
diff --git a/src/soc/intel/pantherlake/include/soc/gpio.h b/src/soc/intel/pantherlake/include/soc/gpio.h
index d7b562f173..5f3a2e1548 100644
--- a/src/soc/intel/pantherlake/include/soc/gpio.h
+++ b/src/soc/intel/pantherlake/include/soc/gpio.h
@@ -6,12 +6,21 @@
 #include <soc/gpio_defs.h>
 #include <intelblocks/gpio.h>
 
+#if CONFIG(SOC_INTEL_WILDCATLAKE)
+#define CROS_GPIO_NAME           "INTC10EC"
+#define CROS_GPIO_DEVICE0_NAME   "INTC10EC:00"
+#define CROS_GPIO_DEVICE1_NAME   "INTC10EC:01"
+#define CROS_GPIO_DEVICE2_NAME   "INTC10EC:02"
+#define CROS_GPIO_DEVICE3_NAME   "INTC10EC:03"
+#define CROS_GPIO_DEVICE4_NAME   "INTC10EC:04"
+#else
 #define CROS_GPIO_NAME           "INTC10BC"
 #define CROS_GPIO_DEVICE0_NAME   "INTC10BC:00"
 #define CROS_GPIO_DEVICE1_NAME   "INTC10BC:01"
 #define CROS_GPIO_DEVICE2_NAME   "INTC10BC:02"
 #define CROS_GPIO_DEVICE3_NAME   "INTC10BC:03"
 #define CROS_GPIO_DEVICE4_NAME   "INTC10BC:04"
+#endif
 
 #define ACPI_GPIO_CID "INTC105F"
 #define ACPI_GPIO_HID CROS_GPIO_NAME

From 89e915e98131249c7e1584e86c2efc3e482e214b Mon Sep 17 00:00:00 2001
From: CoolStar <coolstarorganization@gmail.com>
Date: Sun, 26 Mar 2023 02:35:43 -0700
Subject: [PATCH 0880/3886] ec/google/wilco/acpi: Fix S3/S4 support

- Only run _REG on attach
- Reinitialize on WAK to support S3 / Hibernate

Adjustments taken from EC ACPI on Dell 5400/7410 Windows devices.

TEST=build/boot google/drallion, verify S3 sleep works properly as
well as S0ix.

Change-Id: I162d02c7d3c81f1106ddc65a3804f7112dda66b2
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87488
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Reviewed-by: Boris Mittelberg <bmbm@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/ec/google/wilco/acpi/ec.asl       |  4 ++++
 src/ec/google/wilco/acpi/platform.asl | 22 ++++++++++++++++++++--
 2 files changed, 24 insertions(+), 2 deletions(-)

diff --git a/src/ec/google/wilco/acpi/ec.asl b/src/ec/google/wilco/acpi/ec.asl
index 2e8432844b..806f6086d7 100644
--- a/src/ec/google/wilco/acpi/ec.asl
+++ b/src/ec/google/wilco/acpi/ec.asl
@@ -29,6 +29,10 @@ Device (EC0)
 	OperationRegion (ERAM, EmbeddedControl, 0, 0xff)
 	Method (_REG, 2)
 	{
+		If (Arg1 != 1) {
+			Return ()
+		}
+
 		/* Indicate region is registered */
 		EREG = Arg1
 
diff --git a/src/ec/google/wilco/acpi/platform.asl b/src/ec/google/wilco/acpi/platform.asl
index f815a3533c..cd23512ef9 100644
--- a/src/ec/google/wilco/acpi/platform.asl
+++ b/src/ec/google/wilco/acpi/platform.asl
@@ -4,12 +4,30 @@
 Method (PTS, 1, Serialized)
 {
 	Printf ("EC _PTS")
-	W (FPTS, Arg0)
+	If (EREG){
+		W (FPTS, Arg0)
+	}
 }
 
 /* Call from \_SB._WAK() */
 Method (WAK, 1, Serialized)
 {
 	Printf ("EC _WAK")
-	W (FWAK, Arg0)
+	If (EREG){
+		W (FWAK, Arg0)
+
+		/* Indicate to EC that OS is ready for queries */
+		W (ERDY, 1)
+
+		/* Indicate that the OS supports S0ix */
+		W (CSOS, 1)
+
+		/* Tell EC to stop emulating PS/2 mouse */
+		W (PS2M, 0)
+
+		/* Enable DPTF support if enabled in devicetree */
+		If (\DPTE == 1) {
+			W (DWST, 1)
+		}
+	}
 }

From cf47edb173967775f325086f3f599cb9585f614b Mon Sep 17 00:00:00 2001
From: CoolStar <coolstarorganization@gmail.com>
Date: Sun, 26 Mar 2023 04:34:18 -0700
Subject: [PATCH 0881/3886] ec/google/wilco/acpi: Add UCSI port data

Add UCSI port data/port location data which is required for Windows to
use UCSI.

Adjustments taken from EC ACPI on Dell 5400/7410 Windows devices.

TEST=build/boot google/drallion, verify type-C ports functional under
Windows 11.

Change-Id: I04aa87ec10f320d1740cd3897864d154f2aea507
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87489
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/ec/google/wilco/acpi/ucsi.asl             | 72 +++++++++++++++++++
 .../variants/drallion/include/variant/ec.h    |  3 +
 2 files changed, 75 insertions(+)

diff --git a/src/ec/google/wilco/acpi/ucsi.asl b/src/ec/google/wilco/acpi/ucsi.asl
index 043e1e7abc..7880f7fc8c 100644
--- a/src/ec/google/wilco/acpi/ucsi.asl
+++ b/src/ec/google/wilco/acpi/ucsi.asl
@@ -156,5 +156,77 @@ Scope (\_SB)
 			^CCI2 = R (^^UCI2)
 			^CCI3 = R (^^UCI3)
 		}
+
+		// GPLD: Generate Port Location Data (PLD)
+		Method (GPLD, 2, Serialized)
+		{
+			Name (PCKG, Package (0x01)
+			{
+				Buffer (0x10){}
+			})
+
+			// REV: Revision 0x02 for ACPI 5.0
+			CreateField (DerefOf (PCKG[0]), 0, 0x07, REV)
+			REV = 0x02
+
+			// VISI: Port visibility to user per port
+			CreateField (DerefOf (PCKG[0]), 0x40, 1, VISI)
+			VISI = Arg0
+
+			CreateField (DerefOf (PCKG[0]), 0x57, 0x08, GPOS)
+			GPOS = Arg1
+
+			CreateField (DerefOf (PCKG[0]), 0x4A, 0x04, SHAP)
+			SHAP = 0x01
+
+			CreateField (DerefOf (PCKG[0]), 0x20, 0x10, WID)
+			WID = 0x08
+
+			CreateField (DerefOf (PCKG[0]), 0x30, 0x10, HGT)
+			HGT = 0x03
+			Return (PCKG)
+		}
+
+		Method (GUPC, 1, Serialized)
+		{
+			Name (PCKG, Package (0x04)
+			{
+				One,
+				Zero,
+				Zero,
+				Zero
+			})
+			PCKG[1] = Arg0
+			Return (PCKG)
+		}
+
+		Device (TC01)
+		{
+			Name (_ADR, 0)  // _ADR: Address
+			Method (_UPC, 0, NotSerialized)  // _UPC: USB Port Capabilities
+			{
+				Return (GUPC (0x09))
+			}
+
+			Method (_PLD, 0, NotSerialized)  // _PLD: Physical Location of Device
+			{
+				Return (GPLD (1, 1))
+			}
+		}
+#ifdef EC_BOARD_HAS_2ND_TYPEC_PORT
+		Device (TC02)
+		{
+			Name (_ADR, 1)  // _ADR: Address
+			Method (_UPC, 0, NotSerialized)  // _UPC: USB Port Capabilities
+			{
+				Return (GUPC (0x09))
+			}
+
+			Method (_PLD, 0, NotSerialized)  // _PLD: Physical Location of Device
+			{
+				Return (GPLD (1, 2))
+			}
+		}
+#endif
 	}
 }
diff --git a/src/mainboard/google/drallion/variants/drallion/include/variant/ec.h b/src/mainboard/google/drallion/variants/drallion/include/variant/ec.h
index ba9c01d8e8..0843d53a30 100644
--- a/src/mainboard/google/drallion/variants/drallion/include/variant/ec.h
+++ b/src/mainboard/google/drallion/variants/drallion/include/variant/ec.h
@@ -21,4 +21,7 @@
 /* Enable privacy screen functionality */
 #define EC_ENABLE_PRIVACY
 
+/* Drallion has 2 type-C ports */
+#define EC_BOARD_HAS_2ND_TYPEC_PORT
+
 #endif

From bbd8f0aef80bb41ee9a94e203ae9d0f5cfaa4039 Mon Sep 17 00:00:00 2001
From: Sowmya Aralguppe <sowmya.aralguppe@intel.com>
Date: Wed, 30 Apr 2025 13:41:27 +0530
Subject: [PATCH 0882/3886] soc/intel/ptl: Refactoring NUM_COMx_GRP_PADS
 calculation
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

NUM_COMx_GRP_PADS value is calculated based on COMx_GRP_PAD_END
and COMx_GRP_PAD_START values instead of using GPIO pin names.

TEST=Compiled and Verified on Wildcat Lake Simulation Platform.

Change-Id: I0c5b2ebc00f328bd4b9df4653d5339781e38fcba
Signed-off-by: Sowmya Aralguppe <sowmya.aralguppe@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87484
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
---
 .../pantherlake/include/soc/gpio_soc_defs.h   | 19 +++++++------------
 1 file changed, 7 insertions(+), 12 deletions(-)

diff --git a/src/soc/intel/pantherlake/include/soc/gpio_soc_defs.h b/src/soc/intel/pantherlake/include/soc/gpio_soc_defs.h
index 0ecd32a5ce..fd44d837ce 100644
--- a/src/soc/intel/pantherlake/include/soc/gpio_soc_defs.h
+++ b/src/soc/intel/pantherlake/include/soc/gpio_soc_defs.h
@@ -147,7 +147,7 @@
 
 #define COM0_GRP_PAD_START	GPP_V00
 #define COM0_GRP_PAD_END	GPP_C23
-#define NUM_COM0_GRP_PADS	(GPP_C23 - GPP_V00 + 1)
+#define NUM_COM0_GRP_PADS	(COM0_GRP_PAD_END - COM0_GRP_PAD_START + 1)
 #define NUM_COM0_GPP_PADS	(NUM_GPP_V_PADS + NUM_GPP_C_PADS)
 #define NUM_COM0_GROUPS		2
 
@@ -244,7 +244,7 @@
 
 #define COM1_GRP_PAD_START	GPP_F00
 #define COM1_GRP_PAD_END	GPP_THC0_GSPI_CLK_LPBK
-#define NUM_COM1_GRP_PADS	(GPP_THC0_GSPI_CLK_LPBK - GPP_F00 + 1)
+#define NUM_COM1_GRP_PADS	(COM1_GRP_PAD_END - COM1_GRP_PAD_START + 1)
 #define NUM_COM1_GPP_PADS	(NUM_GPP_F_PADS + NUM_GPP_E_PADS)
 #define NUM_COM1_GROUPS		2
 
@@ -416,17 +416,14 @@
 
 #if CONFIG(SOC_INTEL_WILDCATLAKE)
 #define COM3_GRP_PAD_START	GPP_H00
-#define COM3_GRP_PAD_END	GPP_VGPIO3_THC3
-#define NUM_COM3_GRP_PADS	(GPP_VGPIO3_THC3 - GPP_H00 + 1)
-#define NUM_COM3_GPP_PADS	(NUM_GPP_H_PADS + NUM_GPP_A_PADS)
 #define NUM_COM3_GROUPS		3
 #else
 #define COM3_GRP_PAD_START	GPP_EPD_ON
-#define COM3_GRP_PAD_END	GPP_VGPIO3_THC3
-#define NUM_COM3_GRP_PADS	(GPP_VGPIO3_THC3 - GPP_EPD_ON + 1)
-#define NUM_COM3_GPP_PADS	(NUM_GPP_H_PADS + NUM_GPP_A_PADS)
 #define NUM_COM3_GROUPS		4
 #endif
+#define COM3_GRP_PAD_END	GPP_VGPIO3_THC3
+#define NUM_COM3_GRP_PADS	(COM3_GRP_PAD_END - COM3_GRP_PAD_START + 1)
+#define NUM_COM3_GPP_PADS	(NUM_GPP_H_PADS + NUM_GPP_A_PADS)
 
 /*
  * +----------------------------+
@@ -493,16 +490,14 @@
 
 #if CONFIG(SOC_INTEL_WILDCATLAKE)
 #define COM4_GRP_PAD_END	GPP_DDSP_HPDALV
-#define NUM_COM4_GRP_PADS	(GPP_DDSP_HPDALV - GPP_S00 + 1)
 #define NUM_COM4_GPP_PADS	(NUM_GPP_S_PADS)
 #define NUM_COM4_GROUPS		2
 #else
 #define COM4_GRP_PAD_END	GPP_S07
-#define NUM_COM4_GRP_PADS	(GPP_S07 - GPP_S00 + 1)
 #define NUM_COM4_GPP_PADS	(GPP_S07 - GPP_S00 + 1)
 #define NUM_COM4_GROUPS		1
 #endif
-
+#define NUM_COM4_GRP_PADS	(COM4_GRP_PAD_END - COM4_GRP_PAD_START + 1)
 /*
  * +----------------------------+
  * | Community 5                |
@@ -631,7 +626,7 @@
 
 #define COM5_GRP_PAD_START	GPP_B00
 #define COM5_GRP_PAD_END	GPP_VGPIO47
-#define NUM_COM5_GRP_PADS	(GPP_VGPIO47 - GPP_B00 + 1)
+#define NUM_COM5_GRP_PADS	(COM5_GRP_PAD_END - COM5_GRP_PAD_START + 1)
 #define NUM_COM5_GPP_PADS	(NUM_GPP_B_PADS + NUM_GPP_D_PADS)
 #define NUM_COM5_GROUPS		3
 

From 094f75162f05efc56652cc30f539323fbb5d1d26 Mon Sep 17 00:00:00 2001
From: Patrick Rudolph <patrick.rudolph@9elements.com>
Date: Thu, 17 Apr 2025 15:32:53 +0200
Subject: [PATCH 0883/3886] cpu/x86/64bit/pt: Fix integer arithmethic in
 assembly
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

The GNU assembler allows to use arithmetics on constant expression,
except for division using the '/' character. By default the '/'
introduces a line comment, see [1]. This behaviour can be changed when
the command line argument --divide is being used. However that's not
the case for coreboot.

Since the divide doesn't work as expected the assembler generates 512
times as much instructions on the .rept evaluation than it should. This
didn't cause any problem since it only filled PML4E, but the additional
entries pointed to non existing PDPTs. As long as the memory above 512GB
wasn't accessed it worked just fine.

Use shifts to fix the arithmetic and thus generate only the expected
number of page table entries. Required for the following patch, which
walks page tables and expects to find sane directories.

1: https://sourceware.org/binutils/docs-2.26/as/i386_002dChars.html#i386_002dChars

TEST=GAS generates 512 times less entries on .rept evaluation
Change-Id: I480142df010bf4e7d6fb84c9891e93b6ee21e908
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87356
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/cpu/x86/64bit/pt.S   | 4 ++--
 src/cpu/x86/64bit/pt1G.S | 2 +-
 2 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/src/cpu/x86/64bit/pt.S b/src/cpu/x86/64bit/pt.S
index 5b10b10118..85d425e29a 100644
--- a/src/cpu/x86/64bit/pt.S
+++ b/src/cpu/x86/64bit/pt.S
@@ -21,14 +21,14 @@
 .align 4096
 PML4E:
 /* For every 512GiB generate a pointer to the corresponding PDPT */
-.rept (CONFIG_CPU_PT_ROM_MAP_GB + 511) / 512
+.rept ((CONFIG_CPU_PT_ROM_MAP_GB + 511) >> 9)
 .quad _GEN_DIR(PDPT + 4096 * ((. - PML4E) >> 3)) /* Point to PDPT */
 .endr
 
 .align 4096
 PDT:
 /* For every 2MiB generate a page entry. In one GiB there are 512 pages. */
-.rept 512 * CONFIG_CPU_PT_ROM_MAP_GB
+.rept (CONFIG_CPU_PT_ROM_MAP_GB << 9)
 .quad _GEN_PAGE(0x200000 * ((. - PDT) >> 3)) /* identity map 2MiB page */
 .endr
 
diff --git a/src/cpu/x86/64bit/pt1G.S b/src/cpu/x86/64bit/pt1G.S
index b1f443301d..30dd0cb239 100644
--- a/src/cpu/x86/64bit/pt1G.S
+++ b/src/cpu/x86/64bit/pt1G.S
@@ -21,7 +21,7 @@
 .align 4096
 PML4E:
 /* For every 512GiB generate a pointer to the corresponding PDPT */
-.rept (CONFIG_CPU_PT_ROM_MAP_GB + 511) / 512
+.rept ((CONFIG_CPU_PT_ROM_MAP_GB + 511) >> 9)
 .quad _GEN_DIR(PDPT + 4096 * ((. - PML4E) >> 3)) /* Point to PDPT */
 .endr
 

From b7d59185ab269fcf100e9e8e2a842fd9d1bd3089 Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Tue, 29 Apr 2025 17:39:18 -0500
Subject: [PATCH 0884/3886] soc/intel/common/dtt: Add Kconfig to skip SSDT
 generation
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Some mainboards use the common DPTF ASL rather than the DPTF chip
driver, and those boards need to skip generation of the TCPU ACPI
device in order to avoid a duplicate being created and causing
issues with ACPI table parsing. Create a Kconfig that affected
boards will select to skip generating the TCPU in the SSDT.

Change-Id: Iec58d480821a273cdb4ff086f4995d21fd4bdb2e
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87481
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
---
 src/soc/intel/common/block/dtt/Kconfig | 9 +++++++++
 src/soc/intel/common/block/dtt/dtt.c   | 4 ++--
 2 files changed, 11 insertions(+), 2 deletions(-)

diff --git a/src/soc/intel/common/block/dtt/Kconfig b/src/soc/intel/common/block/dtt/Kconfig
index 1735c2ac21..fcf6788832 100644
--- a/src/soc/intel/common/block/dtt/Kconfig
+++ b/src/soc/intel/common/block/dtt/Kconfig
@@ -7,3 +7,12 @@ config SOC_INTEL_COMMON_BLOCK_DTT
 	  Minimal PCI Driver for enabling SSDT generation of Intel
 	  Dynamic Tuning Technology (DTT) policies and controls, also
 	  known as Intel DPTF (Dynamic Platform and Thermal Framework)
+
+config SOC_INTEL_COMMON_BLOCK_DTT_STATIC_ASL
+	bool
+	depends on SOC_INTEL_COMMON_BLOCK_DTT
+	default n
+	help
+	  Mainboards which include `soc/intel/common/acpi/dptf/dptf.asl`
+	  should select this to avoid generating a duplicate TCPU ACPI
+	  device and rendering the SSDT invalid.
diff --git a/src/soc/intel/common/block/dtt/dtt.c b/src/soc/intel/common/block/dtt/dtt.c
index b2ce8b9c41..1d0451fc78 100644
--- a/src/soc/intel/common/block/dtt/dtt.c
+++ b/src/soc/intel/common/block/dtt/dtt.c
@@ -21,8 +21,8 @@ static const unsigned short pci_device_ids[] = {
 
 static void dtt_acpi_fill_ssdt(const struct device *dev)
 {
-	/* Skip if DPTF driver in use since TCPU device will already exist */
-	if (CONFIG(DRIVERS_INTEL_DPTF))
+	/* Skip if DPTF driver or common DPTF ASL in use since TCPU device will already exist */
+	if (CONFIG(DRIVERS_INTEL_DPTF) || CONFIG(SOC_INTEL_COMMON_BLOCK_DTT_STATIC_ASL))
 		return;
 
 	const char *scope = acpi_device_scope(dev);

From f63c3bb2978b6c3eb286180bb98ede01985c6ed8 Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Tue, 29 Apr 2025 17:24:35 -0500
Subject: [PATCH 0885/3886] soc/intel/cannonlake: Hook up DPTF device to
 devicetree
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Hook up `Device4Enable` FSP setting to devicetree state and drop its
redundant devicetree setting `Device4Enable`. For boards where the
register setting and PCI device status are not in agreement, use
the register setting to determine the PCI device status, since that
is what FSP uses.

Modeled after similar patches for other SoCs.

Change-Id: If17e6e86f6933b334e13f2c05ca513cef0998996
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87483
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/clevo/cml-u/variants/l140cu/devicetree.cb       | 4 +---
 src/mainboard/google/drallion/variants/drallion/devicetree.cb | 1 -
 src/mainboard/google/hatch/variants/baseboard/devicetree.cb   | 2 +-
 src/mainboard/google/puff/variants/baseboard/devicetree.cb    | 2 +-
 src/mainboard/google/sarien/variants/arcada/devicetree.cb     | 1 -
 src/mainboard/google/sarien/variants/sarien/devicetree.cb     | 1 -
 src/mainboard/purism/librem_cnl/devicetree.cb                 | 4 +---
 src/mainboard/system76/addw1/devicetree.cb                    | 4 +---
 src/mainboard/system76/cml-u/devicetree.cb                    | 4 +---
 src/mainboard/system76/gaze15/devicetree.cb                   | 4 +---
 src/mainboard/system76/oryp5/devicetree.cb                    | 4 +---
 src/mainboard/system76/oryp6/devicetree.cb                    | 4 +---
 src/mainboard/system76/whl-u/devicetree.cb                    | 4 +---
 src/soc/intel/cannonlake/chip.h                               | 2 --
 src/soc/intel/cannonlake/fsp_params.c                         | 2 +-
 15 files changed, 11 insertions(+), 32 deletions(-)

diff --git a/src/mainboard/clevo/cml-u/variants/l140cu/devicetree.cb b/src/mainboard/clevo/cml-u/variants/l140cu/devicetree.cb
index 57b3b0f783..1dc9f1b8d9 100644
--- a/src/mainboard/clevo/cml-u/variants/l140cu/devicetree.cb
+++ b/src/mainboard/clevo/cml-u/variants/l140cu/devicetree.cb
@@ -68,9 +68,7 @@ chip soc/intel/cannonlake
 				.backlight_off_delay_ms	=    1,
 			}"
 		end
-		device ref dptf on
-			register "Device4Enable" = "1"
-		end
+		device ref dptf on	end
 		device ref thermal on	end
 		device ref xhci on
 			# USB2
diff --git a/src/mainboard/google/drallion/variants/drallion/devicetree.cb b/src/mainboard/google/drallion/variants/drallion/devicetree.cb
index 0485639654..b79c1cd1d7 100644
--- a/src/mainboard/google/drallion/variants/drallion/devicetree.cb
+++ b/src/mainboard/google/drallion/variants/drallion/devicetree.cb
@@ -46,7 +46,6 @@ chip soc/intel/cannonlake
 		.tdp_pl2_override = 51,
 		.psys_pmax = 140,
 	}"
-	register "Device4Enable" = "1"
 	register "AcousticNoiseMitigation" = "1"
 	register "SlowSlewRateForIa" = "2"
 	register "SlowSlewRateForGt" = "2"
diff --git a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb
index 00b4d83d21..0c4ebd7b65 100644
--- a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb
+++ b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb
@@ -35,7 +35,6 @@ chip soc/intel/cannonlake
 		.tdp_pl1_override = 15,
 		.tdp_pl2_override = 64,
 	}"
-	register "Device4Enable" = "1"
 	# Enable eDP device
 	register "DdiPortEdp" = "1"
 	# Enable HPD for DDI ports B/C
@@ -195,6 +194,7 @@ chip soc/intel/cannonlake
 
 	device domain 0 on
 		device ref igpu		on end
+		device ref dptf		on end
 		device ref thermal	on end
 		device ref xhci		on
 			chip drivers/usb/acpi
diff --git a/src/mainboard/google/puff/variants/baseboard/devicetree.cb b/src/mainboard/google/puff/variants/baseboard/devicetree.cb
index ca3817f463..2e851c8e39 100644
--- a/src/mainboard/google/puff/variants/baseboard/devicetree.cb
+++ b/src/mainboard/google/puff/variants/baseboard/devicetree.cb
@@ -35,7 +35,6 @@ chip soc/intel/cannonlake
 		.tdp_pl1_override = 15,
 		.tdp_pl2_override = 64,
 	}"
-	register "Device4Enable" = "1"
 	# Enable eDP device
 	register "DdiPortEdp" = "1"
 	# Enable HPD for DDI ports B/C
@@ -195,6 +194,7 @@ chip soc/intel/cannonlake
 
 	device domain 0 on
 		device ref igpu		on end
+		device ref dptf		on end
 		device ref thermal	on end
 		device ref xhci		on
 			chip drivers/usb/acpi
diff --git a/src/mainboard/google/sarien/variants/arcada/devicetree.cb b/src/mainboard/google/sarien/variants/arcada/devicetree.cb
index faec225f67..aed9743573 100644
--- a/src/mainboard/google/sarien/variants/arcada/devicetree.cb
+++ b/src/mainboard/google/sarien/variants/arcada/devicetree.cb
@@ -35,7 +35,6 @@ chip soc/intel/cannonlake
 		.tdp_pl2_override = 51,
 		.psys_pmax = 140,
 	}"
-	register "Device4Enable" = "1"
 	register "AcousticNoiseMitigation" = "1"
 	register "SlowSlewRateForIa" = "2"
 	register "SlowSlewRateForGt" = "2"
diff --git a/src/mainboard/google/sarien/variants/sarien/devicetree.cb b/src/mainboard/google/sarien/variants/sarien/devicetree.cb
index 9608e52dae..c88bf6fff0 100644
--- a/src/mainboard/google/sarien/variants/sarien/devicetree.cb
+++ b/src/mainboard/google/sarien/variants/sarien/devicetree.cb
@@ -43,7 +43,6 @@ chip soc/intel/cannonlake
 		.tdp_pl2_override = 51,
 		.psys_pmax = 136,
 	}"
-	register "Device4Enable" = "1"
 	# Enable eDP device
 	register "DdiPortEdp" = "1"
 	# Enable HPD for DDI ports B/C
diff --git a/src/mainboard/purism/librem_cnl/devicetree.cb b/src/mainboard/purism/librem_cnl/devicetree.cb
index dfacdea686..44a995b801 100644
--- a/src/mainboard/purism/librem_cnl/devicetree.cb
+++ b/src/mainboard/purism/librem_cnl/devicetree.cb
@@ -43,9 +43,7 @@ chip soc/intel/cannonlake
 # Actual device tree
 	device domain 0 on
 		device ref igpu		on end
-		device ref dptf		on
-			register "Device4Enable" = "1"
-		end
+		device ref dptf		on end
 		device ref thermal	on end
 		device ref xhci		on end
 		device ref sata		on end
diff --git a/src/mainboard/system76/addw1/devicetree.cb b/src/mainboard/system76/addw1/devicetree.cb
index 07e960c50d..59491134c7 100644
--- a/src/mainboard/system76/addw1/devicetree.cb
+++ b/src/mainboard/system76/addw1/devicetree.cb
@@ -57,9 +57,7 @@ chip soc/intel/cannonlake
 			register "PcieClkSrcClkReq[8]" = "8"
 		end
 		device ref igpu		on	end
-		device ref dptf		on
-			register "Device4Enable" = "1"
-		end
+		device ref dptf		on	end
 		device ref thermal	on	end
 		device ref xhci		on
 			register "usb2_ports" = "{
diff --git a/src/mainboard/system76/cml-u/devicetree.cb b/src/mainboard/system76/cml-u/devicetree.cb
index ed0a520d6e..14de0548ea 100644
--- a/src/mainboard/system76/cml-u/devicetree.cb
+++ b/src/mainboard/system76/cml-u/devicetree.cb
@@ -60,9 +60,7 @@ chip soc/intel/cannonlake
 		device ref igpu		on
 			register "gfx" = "GMA_DEFAULT_PANEL(0)"
 		end
-		device ref dptf		on
-			register "Device4Enable" = "1"
-		end
+		device ref dptf		on	end
 		device ref thermal	on	end
 		device ref cnvi_wifi	on
 			chip drivers/wifi/generic
diff --git a/src/mainboard/system76/gaze15/devicetree.cb b/src/mainboard/system76/gaze15/devicetree.cb
index cc76124695..1f8fb88c67 100644
--- a/src/mainboard/system76/gaze15/devicetree.cb
+++ b/src/mainboard/system76/gaze15/devicetree.cb
@@ -58,9 +58,7 @@ chip soc/intel/cannonlake
 		device ref igpu		on
 			register "gfx" = "GMA_DEFAULT_PANEL(0)"
 		end
-		device ref dptf		on
-			register "Device4Enable" = "1"
-		end
+		device ref dptf		on	end
 		device ref thermal	on	end
 		device ref xhci		on
 			register "usb2_ports" = "{
diff --git a/src/mainboard/system76/oryp5/devicetree.cb b/src/mainboard/system76/oryp5/devicetree.cb
index e18ab9a397..ea9e14e436 100644
--- a/src/mainboard/system76/oryp5/devicetree.cb
+++ b/src/mainboard/system76/oryp5/devicetree.cb
@@ -66,9 +66,7 @@ chip soc/intel/cannonlake
 		device ref igpu		on
 			register "gfx" = "GMA_DEFAULT_PANEL(0)"
 		end
-		device ref dptf		on
-			register "Device4Enable" = "1"
-		end
+		device ref dptf		on	end
 		device ref thermal	on	end
 		device ref xhci		on
 			register "usb2_ports" = "{
diff --git a/src/mainboard/system76/oryp6/devicetree.cb b/src/mainboard/system76/oryp6/devicetree.cb
index d6423f3c2e..e682fefe53 100644
--- a/src/mainboard/system76/oryp6/devicetree.cb
+++ b/src/mainboard/system76/oryp6/devicetree.cb
@@ -63,9 +63,7 @@ chip soc/intel/cannonlake
 		device ref igpu		on
 			register "gfx" = "GMA_DEFAULT_PANEL(0)"
 		end
-		device ref dptf		on
-			register "Device4Enable" = "1"
-		end
+		device ref dptf		on	end
 		device ref thermal	on	end
 		device ref xhci		on
 			register "usb2_ports" = "{
diff --git a/src/mainboard/system76/whl-u/devicetree.cb b/src/mainboard/system76/whl-u/devicetree.cb
index 1686f95eda..5593b11b97 100644
--- a/src/mainboard/system76/whl-u/devicetree.cb
+++ b/src/mainboard/system76/whl-u/devicetree.cb
@@ -60,9 +60,7 @@ chip soc/intel/cannonlake
 		device ref igpu		on
 			register "gfx" = "GMA_STATIC_DISPLAYS(0)"
 		end
-		device ref dptf		on
-			register "Device4Enable" = "1"
-		end
+		device ref dptf		on  end
 		device ref thermal	on  end
 		device ref xhci		on
 			register "usb2_ports" = "{
diff --git a/src/soc/intel/cannonlake/chip.h b/src/soc/intel/cannonlake/chip.h
index c01f36fdac..591abbeaae 100644
--- a/src/soc/intel/cannonlake/chip.h
+++ b/src/soc/intel/cannonlake/chip.h
@@ -220,8 +220,6 @@ struct soc_intel_cannonlake_config {
 	/* Gfx related */
 	bool SkipExtGfxScan;
 
-	bool Device4Enable;
-
 	/* CPU PL2/4 Config
 	 * Performance: Maximum PLs for maximum performance.
 	 * Baseline: Baseline PLs for balanced performance at lower power.
diff --git a/src/soc/intel/cannonlake/fsp_params.c b/src/soc/intel/cannonlake/fsp_params.c
index 55a7c92aa0..993efbb107 100644
--- a/src/soc/intel/cannonlake/fsp_params.c
+++ b/src/soc/intel/cannonlake/fsp_params.c
@@ -631,7 +631,7 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
 	 * the `Heci1Disabled` UPD to `0`.
 	 */
 	s_cfg->Heci1Disabled = 0;
-	s_cfg->Device4Enable = config->Device4Enable;
+	s_cfg->Device4Enable = is_devfn_enabled(SA_DEVFN_TS);
 
 	/* Teton Glacier hybrid storage support */
 	s_cfg->TetonGlacierMode = config->TetonGlacierMode;

From 4b765fdd988615140ac743305361e96bf0aa24eb Mon Sep 17 00:00:00 2001
From: Jeremy Compostella <jeremy.compostella@intel.com>
Date: Wed, 30 Apr 2025 15:06:36 -0700
Subject: [PATCH 0886/3886] mb/google/fatcat: Disable EnableFastVmode on
 Panther Lake H SoC

This commit addresses a performance issue on the Panther Lake H SoC by
disabling the EnableFastVmode setting in addition to the CepEnable
setting. It was discovered that merely disabling CepEnable was
insufficient, as the FSP continued to program Panther Lake U IccLimit on
FastVMode capable boards, causing performance degradation under
high-stress conditions. By also disabling EnableFastVmode, the I_TRIP
value is prevented from being set lower than the device's actual
capability.

TEST=Verify that IccLimit is programmed with FSP default values.

Change-Id: I2974f1311b69f283d7fa4982c28a9037a8ab23f7
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87505
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Zhixing Ma <zhixing.ma@intel.com>
---
 src/mainboard/google/fatcat/romstage.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/src/mainboard/google/fatcat/romstage.c b/src/mainboard/google/fatcat/romstage.c
index 44a901a0ec..7a509384b2 100644
--- a/src/mainboard/google/fatcat/romstage.c
+++ b/src/mainboard/google/fatcat/romstage.c
@@ -62,8 +62,10 @@ static void disable_vr_settings_on_pantherlake_h(FSP_M_CONFIG *m_cfg)
 	 * because the I_TRIP value is set lower than the device's actual capability.
 	 */
 	printk(BIOS_INFO, "Disabling VR settings on PTL-H.\n");
-	for (size_t i = 0; i < NUM_VR_DOMAINS; i++)
+	for (size_t i = 0; i < NUM_VR_DOMAINS; i++) {
 		m_cfg->CepEnable[i] = false;
+		m_cfg->EnableFastVmode[i] = false;
+	}
 }
 
 void mainboard_memory_init_params(FSPM_UPD *memupd)

From 5d3664ce3bd9884215170bc64d460dea9d7eba4a Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Wed, 30 Apr 2025 12:11:48 -0500
Subject: [PATCH 0887/3886] mb/starlabs/starbook/adl_n: Update VBT to fix HDMI
 output

The HDMI output was not enabled and therefore not functional; enable
it on port DDI-B as per the schematics.

TEST=build/boot Ubuntu 24.10 on starlabs/starbook adl-n, verify
HDMI output functional when connected at boot and when hotplugging.

Change-Id: I746eb1c2284778d46ee5d5a85dae41f284254cb0
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87491
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 .../starlabs/starbook/variants/adl_n/data.vbt | Bin 9216 -> 9216 bytes
 1 file changed, 0 insertions(+), 0 deletions(-)

diff --git a/src/mainboard/starlabs/starbook/variants/adl_n/data.vbt b/src/mainboard/starlabs/starbook/variants/adl_n/data.vbt
index 58864e2150446e5e9ac6c541b26b4fbf19c5776e..6cf0f8be2b47494c42021df9001fc998ebd2df45 100644
GIT binary patch
delta 48
ycmZqhXz-XI#r%rFU~(a&@J55Rj1rd;7z6|ulobUSK!6cUG8|xF*!-1|TL}Oy3<^{L

delta 48
zcmZqhXz-XI#mvHBFu9OXc%#8uMhON61_1#EWkmrXgMopafq@A~9bgdH{FRYg2>|A=
B2vh(7


From 0f0d5fc7252e42d585afa6b41f27d02539f2f071 Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Tue, 29 Apr 2025 18:44:32 -0500
Subject: [PATCH 0888/3886] soc/intel/apollolake/acpi: Add function to get PCIe
 BAR

Commit 12abfb43dc0a ("soc/intel/cnvi: Add CNVW OpRegion") added an
ACPI function call to \_SB_.PCI0.GPCB(), which is present in the SoC
common northbridge.asl, but not in the ApolloLake northbridge.asl.

Add the missing GPCB function to the APL northbridge. Per Intel doc
336561, the PCIEXBAR starts at bit 28 vs 26 on other platforms.

TEST=build/boot google/ampton, verify no ACPI errors in dmesg related
to missing function/object, Windows boots without ACPI_BIOS_ERROR BSOD.

Change-Id: Ib45d655a30bf68e9b3d24a444c505e515c4950a6
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87486
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/soc/intel/apollolake/acpi/northbridge.asl | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/src/soc/intel/apollolake/acpi/northbridge.asl b/src/soc/intel/apollolake/acpi/northbridge.asl
index a304331f1d..fcbd1d0494 100644
--- a/src/soc/intel/apollolake/acpi/northbridge.asl
+++ b/src/soc/intel/apollolake/acpi/northbridge.asl
@@ -124,5 +124,12 @@ Device (PDRC)	/* PCI Device Resource Consumption */
 	}
 }
 
+/* Get PCIe BAR */
+Method (GPCB, 0, Serialized)
+{
+	Local0 = \_SB.PCI0.MCHC.PXBR << 28
+	Return (Local0)
+}
+
 /* GFX 00:02.0 */
 #include <drivers/intel/gma/acpi/gfx.asl>

From 1166f9be0dcfd7b191991d9bba8db1028310bcc8 Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Sun, 20 Apr 2025 18:11:24 -0500
Subject: [PATCH 0889/3886] include/console: Add CFR object for setting the
 logging level

Add a header with a CFR object for setting the coreboot console log
level, so that all mainboards can make use of it without duplication.

Change-Id: I473421e0e6b2031eb9846f5a798b427104dc3af3
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87487
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
---
 src/include/console/cfr.h | 30 ++++++++++++++++++++++++++++++
 1 file changed, 30 insertions(+)
 create mode 100644 src/include/console/cfr.h

diff --git a/src/include/console/cfr.h b/src/include/console/cfr.h
new file mode 100644
index 0000000000..899fb3e464
--- /dev/null
+++ b/src/include/console/cfr.h
@@ -0,0 +1,30 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+/*
+ * CFR enums and structs for console
+ */
+
+#ifndef _CONSOLE_CFR_H_
+#define _CONSOLE_CFR_H_
+
+#include <drivers/option/cfr_frontend.h>
+
+const struct sm_object debug_level = SM_DECLARE_ENUM({
+	.opt_name	= "debug_level",
+	.ui_name	= "Console Log Level",
+	.ui_helptext	= "Set the verbosity of the coreboot console output.",
+	.default_value	= CONFIG_DEFAULT_CONSOLE_LOGLEVEL,
+	.values		= (const struct sm_enum_value[]) {
+				{ "Emergency",		0		},
+				{ "Alert",		1		},
+				{ "Critical",		2		},
+				{ "Error",		3		},
+				{ "Warning",		4		},
+				{ "Notice",		5		},
+				{ "Info",		6		},
+				{ "Debug",		7		},
+				{ "Spew",		8		},
+				SM_ENUM_VALUE_END			},
+});
+
+#endif /* _CONSOLE_CFR_H_ */

From 173c5d0aad8c0d327bfe55a0436369c48d4fa3ac Mon Sep 17 00:00:00 2001
From: NyeonWoo Kim <knw0507@naver.com>
Date: Sat, 5 Apr 2025 19:44:56 +0900
Subject: [PATCH 0890/3886] src/arch/x86/c_start: Delete duplicated code
 masking stack pointer

I found duplicated code masking stack pointer.

So, i'd like to remove the duplicate for refactoring :-).

This is my build output of c_start.o, before vs after modifying.
  before modifying
	...
	44:   f3 ab                   rep stos %eax,%es:(%edi)
	46:   bc 00 00 00 00          mov    $0x0,%esp
	4b:   83 e4 f0                and    $0xfffffff0,%esp
	4e:   b0 6e                   mov    $0x6e,%al
	50:   e6 80                   out    %al,$0x80
	52:   83 e4 f0                and    $0xfffffff0,%esp  // deleted.
	55:   e8 fc ff ff ff          call   56 <_start+0x56>
	...
  after modifying
	...
	44:   f3 ab                   rep stos %eax,%es:(%edi)
	46:   bc 00 00 00 00          mov    $0x0,%esp
	4b:   83 e4 f0                and    $0xfffffff0,%esp
	4e:   b0 6e                   mov    $0x6e,%al
	50:   e6 80                   out    %al,$0x80
	52:   e8 fc ff ff ff          call   53 <_start+0x53>
	...

P.S. it is commits which introduced duplication.
  32bit : 4d75dbd1c1d
  64bit : 1c4c7ad1e5a

Change-Id: I417ce90279fea4b00432e6a209f77a6dd0c0fee6
Signed-off-by: NyeonWoo Kim <knw0507@naver.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87181
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
---
 src/arch/x86/c_start.S | 7 -------
 1 file changed, 7 deletions(-)

diff --git a/src/arch/x86/c_start.S b/src/arch/x86/c_start.S
index 94b9bd9fa5..fd61cab44d 100644
--- a/src/arch/x86/c_start.S
+++ b/src/arch/x86/c_start.S
@@ -101,13 +101,6 @@ _start:
 	 */
 	post_code(POSTCODE_PRE_HARDWAREMAIN)	/* post 6e */
 
-#if ENV_X86_64
-	movq	$0xFFFFFFFFFFFFFFF0, %rax
-	and	%rax, %rsp
-#else
-	andl	$0xFFFFFFF0, %esp
-#endif
-
 #if CONFIG(ASAN_IN_RAMSTAGE)
 	call asan_init
 #endif

From f2cf7329971958c1a6b0bcc8926549bd50d6e6a2 Mon Sep 17 00:00:00 2001
From: Julius Werner <jwerner@chromium.org>
Date: Thu, 1 May 2025 14:32:34 -0700
Subject: [PATCH 0891/3886] libpayload: usbmsc: Correctly deal with disks
 larger than 2TB

Disks larger than 2TB (technically disks with more than 2^32 blocks, but
for the common block size of 512 that comes out to 2TB) cannot represent
their full amount of blocks in the SCSI READ_CAPACITY(10) command used
by libpayload's USB mass storage driver. The entire driver isn't written
to support block addresses larger than 32 bits anyway.

The SCSI command has been designed in a clever way so that devices are
supposed to return the maximum value (0xffffffff) if the actual value
doesn't fit. However, our code adds one to the value (because it is
actually the address of the last block, but we want to know the number
of blocks). This makes it overflow back to 0 which is not great.

This patch caps the result before incrementing it so that the overflow
cannot occur, allowing us to at least access the first 2TB of super
large USB sticks.

Change-Id: Ic445923b7d588c4f523c4ed95a06291bc1969261
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87506
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
---
 payloads/libpayload/drivers/usb/usbmsc.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/payloads/libpayload/drivers/usb/usbmsc.c b/payloads/libpayload/drivers/usb/usbmsc.c
index 3f249d8bbb..762e644311 100644
--- a/payloads/libpayload/drivers/usb/usbmsc.c
+++ b/payloads/libpayload/drivers/usb/usbmsc.c
@@ -28,6 +28,7 @@
 
 //#define USB_DEBUG
 #include <endian.h>
+#include <limits.h>
 #include <usb/usb.h>
 #include <usb/usbmsc.h>
 #include <usb/usbdisk.h>
@@ -520,7 +521,7 @@ read_capacity(usbdev_t *dev)
 		MSC_INST(dev)->numblocks = 0xffffffff;
 		MSC_INST(dev)->blocksize = 512;
 	} else {
-		MSC_INST(dev)->numblocks = ntohl(buf[0]) + 1;
+		MSC_INST(dev)->numblocks = MIN(ntohl(buf[0]), UINT_MAX - 1) + 1;
 		MSC_INST(dev)->blocksize = ntohl(buf[1]);
 	}
 	usb_debug("  %d %d-byte sectors (%d MB)\n", MSC_INST(dev)->numblocks,

From 7b27b1ca99d137055fa8bee32f8aaf115f362db0 Mon Sep 17 00:00:00 2001
From: Cathy Xu <ot_cathy.xu@mediatek.com>
Date: Tue, 1 Apr 2025 10:43:35 +0800
Subject: [PATCH 0892/3886] soc/mediatek/mt8189: Fix incorrect GPIO register
 address

The previous commit incorrectly set GPIO register address due to a lack
of checking. This commit fixes the register address to ensure GPIO
function can work well.

BUG=b:379008996
BRANCH=none
TEST=build passed, and check SD card can be identified in depthcharge
firmware-shell: storage init
Man 000002 Snr 1759900928 Product SA02 Revision 9.12
*  0: UFS LUN 0
   1: removable mtk_mmc
2 devices total

Signed-off-by: Cathy Xu <ot_cathy.xu@mediatek.com>
Change-Id: I14125ff331f965ce8cbb83cb25d8a2feff0359f2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87510
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/soc/mediatek/mt8189/gpio.c             | 288 ++++++++--------
 src/soc/mediatek/mt8189/include/soc/gpio.h | 366 ++++++++++-----------
 2 files changed, 327 insertions(+), 327 deletions(-)

diff --git a/src/soc/mediatek/mt8189/gpio.c b/src/soc/mediatek/mt8189/gpio.c
index dde8d14ad5..62bfee5266 100644
--- a/src/soc/mediatek/mt8189/gpio.c
+++ b/src/soc/mediatek/mt8189/gpio.c
@@ -21,7 +21,7 @@ enum {
 
 static const struct gpio_drv_info bootblock_gpio_driving_info[] = {
 	[SPI_NOR_CK] = { 0x10, 12, 3, },
-	[SPI_NOR_CS] = { 0x10, 27, 3, },
+	[SPI_NOR_CS] = { 0x20, 27, 3, },
 	[SPI_NOR_IO0] = { 0x10, 15, 3, },
 	[SPI_NOR_IO1] = { 0x10, 18, 3, },
 	[SPI_NOR_IO2] = { 0x10, 21, 3, },
@@ -29,63 +29,63 @@ static const struct gpio_drv_info bootblock_gpio_driving_info[] = {
 };
 
 static const struct gpio_drv_info gpio_driving_info[] = {
-	[0] = { 0x10, 15, 3, },
-	[1] = { 0x10, 9, 3, },
-	[2] = { 0x10, 12, 3, },
-	[3] = { 0x10, 15, 3, },
-	[4] = { 0x10, 18, 3, },
-	[5] = { 0x10, 21, 3, },
-	[6] = { 0x10, 18, 3, },
-	[7] = { 0x10, 21, 3, },
-	[8] = { 0x10, 24, 3, },
-	[9] = { 0x10, 27, 3, },
+	[0] = { 0x00, 15, 3, },
+	[1] = { 0x00, 9, 3, },
+	[2] = { 0x00, 12, 3, },
+	[3] = { 0x00, 15, 3, },
+	[4] = { 0x00, 18, 3, },
+	[5] = { 0x00, 21, 3, },
+	[6] = { 0x00, 18, 3, },
+	[7] = { 0x00, 21, 3, },
+	[8] = { 0x00, 24, 3, },
+	[9] = { 0x00, 27, 3, },
 	[10] = { 0x10, 0, 3, },
 	[11] = { 0x10, 3, 3, },
-	[12] = { 0x10, 15, 3, },
-	[13] = { 0x10, 18, 3, },
-	[14] = { 0x10, 0, 3, },
-	[15] = { 0x10, 3, 3, },
-	[16] = { 0x10, 21, 3, },
-	[17] = { 0x10, 24, 3, },
-	[18] = { 0x10, 0, 3, },
-	[19] = { 0x10, 6, 3, },
-	[20] = { 0x10, 3, 3, },
-	[21] = { 0x10, 9, 3, },
-	[22] = { 0x10, 0, 3, },
-	[23] = { 0x10, 3, 3, },
-	[24] = { 0x10, 6, 3, },
-	[25] = { 0x10, 6, 3, },
-	[26] = { 0x10, 3, 3, },
-	[27] = { 0x10, 3, 3, },
-	[28] = { 0x10, 6, 3, },
-	[29] = { 0x10, 0, 3, },
-	[30] = { 0x10, 0, 3, },
+	[12] = { 0x00, 15, 3, },
+	[13] = { 0x00, 18, 3, },
+	[14] = { 0x00, 0, 3, },
+	[15] = { 0x00, 3, 3, },
+	[16] = { 0x00, 21, 3, },
+	[17] = { 0x00, 24, 3, },
+	[18] = { 0x00, 0, 3, },
+	[19] = { 0x00, 6, 3, },
+	[20] = { 0x00, 3, 3, },
+	[21] = { 0x00, 9, 3, },
+	[22] = { 0x00, 0, 3, },
+	[23] = { 0x00, 3, 3, },
+	[24] = { 0x00, 6, 3, },
+	[25] = { 0x00, 6, 3, },
+	[26] = { 0x00, 3, 3, },
+	[27] = { 0x00, 3, 3, },
+	[28] = { 0x00, 6, 3, },
+	[29] = { 0x00, 0, 3, },
+	[30] = { 0x00, 0, 3, },
 	[31] = { 0x10, 27, 3, },
-	[32] = { 0x10, 0, 3, },
-	[33] = { 0x10, 3, 3, },
-	[34] = { 0x10, 0, 3, },
-	[35] = { 0x10, 9, 3, },
-	[36] = { 0x10, 6, 3, },
-	[37] = { 0x10, 15, 3, },
-	[38] = { 0x10, 12, 3, },
-	[39] = { 0x10, 15, 3, },
-	[40] = { 0x10, 6, 3, },
-	[41] = { 0x10, 9, 3, },
-	[42] = { 0x10, 12, 3, },
-	[43] = { 0x10, 18, 3, },
-	[44] = { 0x10, 0, 3, },
-	[45] = { 0x10, 3, 3, },
-	[46] = { 0x10, 6, 3, },
-	[47] = { 0x10, 9, 3, },
-	[48] = { 0x10, 15, 3, },
-	[49] = { 0x10, 12, 3, },
-	[50] = { 0x10, 9, 3, },
-	[51] = { 0x10, 24, 3, },
+	[32] = { 0x30, 0, 3, },
+	[33] = { 0x20, 3, 3, },
+	[34] = { 0x20, 0, 3, },
+	[35] = { 0x20, 9, 3, },
+	[36] = { 0x20, 6, 3, },
+	[37] = { 0x20, 15, 3, },
+	[38] = { 0x20, 12, 3, },
+	[39] = { 0x00, 15, 3, },
+	[40] = { 0x00, 6, 3, },
+	[41] = { 0x00, 9, 3, },
+	[42] = { 0x00, 12, 3, },
+	[43] = { 0x00, 18, 3, },
+	[44] = { 0x20, 0, 3, },
+	[45] = { 0x20, 3, 3, },
+	[46] = { 0x20, 6, 3, },
+	[47] = { 0x20, 9, 3, },
+	[48] = { 0x00, 15, 3, },
+	[49] = { 0x00, 12, 3, },
+	[50] = { 0x00, 9, 3, },
+	[51] = { 0x00, 24, 3, },
 	[52] = { 0x10, 0, 3, },
-	[53] = { 0x10, 27, 3, },
+	[53] = { 0x00, 27, 3, },
 	[54] = { 0x10, 3, 3, },
-	[55] = { 0x10, 18, 3, },
-	[56] = { 0x10, 21, 3, },
+	[55] = { 0x00, 18, 3, },
+	[56] = { 0x00, 21, 3, },
 	[57] = { 0x10, 9, 3, },
 	[58] = { 0x10, 21, 3, },
 	[59] = { 0x10, 12, 3, },
@@ -93,45 +93,45 @@ static const struct gpio_drv_info gpio_driving_info[] = {
 	[61] = { 0x10, 15, 3, },
 	[62] = { 0x10, 27, 3, },
 	[63] = { 0x10, 18, 3, },
-	[64] = { 0x10, 0, 3, },
+	[64] = { 0x20, 0, 3, },
 	[65] = { 0x10, 0, 3, },
 	[66] = { 0x10, 6, 3, },
 	[67] = { 0x10, 3, 3, },
 	[68] = { 0x10, 9, 3, },
-	[69] = { 0x10, 6, 3, },
-	[70] = { 0x10, 3, 3, },
-	[71] = { 0x10, 12, 3, },
-	[72] = { 0x10, 9, 3, },
-	[73] = { 0x10, 18, 3, },
-	[74] = { 0x10, 15, 3, },
+	[69] = { 0x20, 6, 3, },
+	[70] = { 0x20, 3, 3, },
+	[71] = { 0x20, 12, 3, },
+	[72] = { 0x20, 9, 3, },
+	[73] = { 0x20, 18, 3, },
+	[74] = { 0x20, 15, 3, },
 	[75] = { 0x10, 9, 3, },
-	[76] = { 0x10, 21, 3, },
+	[76] = { 0x20, 21, 3, },
 	[77] = { 0x10, 9, 3, },
 	[78] = { 0x10, 6, 3, },
 	[79] = { 0x10, 15, 3, },
 	[80] = { 0x10, 12, 3, },
-	[81] = { 0x10, 27, 3, },
-	[82] = { 0x10, 24, 3, },
-	[83] = { 0x10, 0, 3, },
-	[84] = { 0x10, 12, 3, },
-	[85] = { 0x10, 15, 3, },
-	[86] = { 0x10, 18, 3, },
-	[87] = { 0x10, 21, 3, },
-	[88] = { 0x10, 0, 3, },
+	[81] = { 0x20, 27, 3, },
+	[82] = { 0x20, 24, 3, },
+	[83] = { 0x30, 0, 3, },
+	[84] = { 0x20, 12, 3, },
+	[85] = { 0x20, 15, 3, },
+	[86] = { 0x20, 18, 3, },
+	[87] = { 0x20, 21, 3, },
+	[88] = { 0x20, 0, 3, },
 	[89] = { 0x10, 27, 3, },
-	[90] = { 0x10, 6, 3, },
-	[91] = { 0x10, 3, 3, },
+	[90] = { 0x20, 6, 3, },
+	[91] = { 0x20, 3, 3, },
 	[92] = { 0x10, 18, 3, },
 	[93] = { 0x10, 21, 3, },
-	[94] = { 0x10, 9, 3, },
+	[94] = { 0x20, 9, 3, },
 	[95] = { 0x10, 15, 3, },
 	[96] = { 0x10, 24, 3, },
-	[97] = { 0x10, 0, 3, },
-	[98] = { 0x10, 15, 3, },
-	[99] = { 0x10, 9, 3, },
-	[100] = { 0x10, 12, 3, },
-	[101] = { 0x10, 3, 3, },
-	[102] = { 0x10, 6, 3, },
+	[97] = { 0x00, 0, 3, },
+	[98] = { 0x00, 15, 3, },
+	[99] = { 0x00, 9, 3, },
+	[100] = { 0x00, 12, 3, },
+	[101] = { 0x00, 3, 3, },
+	[102] = { 0x00, 6, 3, },
 	[103] = { 0x10, 15, 3, },
 	[104] = { 0x10, 6, 3, },
 	[105] = { 0x10, 12, 3, },
@@ -140,47 +140,47 @@ static const struct gpio_drv_info gpio_driving_info[] = {
 	[108] = { 0x10, 18, 3, },
 	[109] = { 0x10, 24, 3, },
 	[110] = { 0x10, 21, 3, },
-	[111] = { 0x10, 12, 3, },
-	[112] = { 0x10, 0, 3, },
-	[113] = { 0x10, 3, 3, },
-	[114] = { 0x10, 6, 3, },
-	[115] = { 0x10, 27, 3, },
+	[111] = { 0x00, 12, 3, },
+	[112] = { 0x00, 0, 3, },
+	[113] = { 0x00, 3, 3, },
+	[114] = { 0x00, 6, 3, },
+	[115] = { 0x00, 27, 3, },
 	[116] = { 0x10, 6, 3, },
 	[117] = { 0x10, 0, 3, },
 	[118] = { 0x10, 3, 3, },
-	[119] = { 0x10, 18, 3, },
-	[120] = { 0x10, 15, 3, },
-	[121] = { 0x10, 12, 3, },
-	[122] = { 0x10, 9, 3, },
+	[119] = { 0x20, 18, 3, },
+	[120] = { 0x20, 15, 3, },
+	[121] = { 0x20, 12, 3, },
+	[122] = { 0x20, 9, 3, },
 	[123] = { 0x10, 27, 3, },
 	[124] = { 0x10, 24, 3, },
 	[125] = { 0x10, 21, 3, },
 	[126] = { 0x10, 18, 3, },
-	[127] = { 0x10, 6, 3, },
+	[127] = { 0x20, 6, 3, },
 	[128] = { 0x10, 15, 3, },
-	[129] = { 0x10, 0, 3, },
-	[130] = { 0x10, 21, 3, },
+	[129] = { 0x20, 0, 3, },
+	[130] = { 0x20, 21, 3, },
 	[131] = { 0x10, 9, 3, },
 	[132] = { 0x10, 12, 3, },
-	[133] = { 0x10, 24, 3, },
-	[134] = { 0x10, 3, 3, },
+	[133] = { 0x20, 24, 3, },
+	[134] = { 0x20, 3, 3, },
 	[135] = { 0x10, 3, 3, },
 	[136] = { 0x10, 6, 3, },
-	[137] = { 0x10, 9, 3, },
-	[138] = { 0x10, 12, 3, },
-	[139] = { 0x10, 9, 3, },
-	[140] = { 0x10, 12, 3, },
-	[141] = { 0x10, 0, 3, },
-	[142] = { 0x10, 3, 3, },
-	[143] = { 0x10, 6, 3, },
-	[144] = { 0x10, 15, 3, },
-	[145] = { 0x10, 18, 3, },
-	[146] = { 0x10, 21, 3, },
-	[147] = { 0x10, 24, 3, },
-	[148] = { 0x10, 27, 3, },
+	[137] = { 0x00, 9, 3, },
+	[138] = { 0x00, 12, 3, },
+	[139] = { 0x00, 9, 3, },
+	[140] = { 0x00, 12, 3, },
+	[141] = { 0x00, 0, 3, },
+	[142] = { 0x00, 3, 3, },
+	[143] = { 0x00, 6, 3, },
+	[144] = { 0x00, 15, 3, },
+	[145] = { 0x00, 18, 3, },
+	[146] = { 0x00, 21, 3, },
+	[147] = { 0x00, 24, 3, },
+	[148] = { 0x00, 27, 3, },
 	[149] = { 0x10, 0, 3, },
 	[150] = { 0x10, 12, 3, },
-	[151] = { 0x10, 27, 3, },
+	[151] = { 0x20, 27, 3, },
 	[152] = { 0x10, 15, 3, },
 	[153] = { 0x10, 18, 3, },
 	[154] = { 0x10, 21, 3, },
@@ -188,55 +188,55 @@ static const struct gpio_drv_info gpio_driving_info[] = {
 	[156] = { 0x10, 6, 3, },
 	[157] = { 0x10, 3, 3, },
 	[158] = { 0x10, 0, 3, },
-	[159] = { 0x10, 6, 3, },
+	[159] = { 0x00, 6, 3, },
 	[160] = { 0x10, 12, 3, },
-	[161] = { 0x10, 21, 3, },
-	[162] = { 0x10, 18, 3, },
-	[163] = { 0x10, 3, 3, },
-	[164] = { 0x10, 27, 3, },
-	[165] = { 0x10, 24, 3, },
-	[166] = { 0x10, 0, 3, },
+	[161] = { 0x00, 21, 3, },
+	[162] = { 0x00, 18, 3, },
+	[163] = { 0x00, 3, 3, },
+	[164] = { 0x00, 27, 3, },
+	[165] = { 0x00, 24, 3, },
+	[166] = { 0x00, 0, 3, },
 	[167] = { 0x10, 9, 3, },
-	[168] = { 0x10, 24, 3, },
-	[169] = { 0x10, 21, 3, },
-	[170] = { 0x10, 27, 3, },
+	[168] = { 0x00, 24, 3, },
+	[169] = { 0x00, 21, 3, },
+	[170] = { 0x00, 27, 3, },
 	[171] = { 0x10, 0, 3, },
 	[172] = { 0x10, 3, 3, },
 	[173] = { 0x10, 6, 3, },
-	[174] = { 0x10, 15, 3, },
-	[175] = { 0x10, 12, 3, },
-	[176] = { 0x10, 18, 3, },
-	[177] = { 0x10, 21, 3, },
-	[178] = { 0x10, 24, 3, },
-	[179] = { 0x10, 27, 3, },
-	[180] = { 0x10, 12, 3, },
-	[181] = { 0x10, 15, 3, },
-	[182] = { 0x10, 9, 3, },
+	[174] = { 0x00, 15, 3, },
+	[175] = { 0x00, 12, 3, },
+	[176] = { 0x00, 18, 3, },
+	[177] = { 0x00, 21, 3, },
+	[178] = { 0x00, 24, 3, },
+	[179] = { 0x00, 27, 3, },
+	[180] = { 0x20, 12, 3, },
+	[181] = { 0x20, 15, 3, },
+	[182] = { 0x00, 9, 3, },
 };
 _Static_assert(ARRAY_SIZE(gpio_driving_info) == GPIO_NUM,
 	       "gpio_driving_info array size not match");
 
 static const struct gpio_drv_info gpio_driving_adv_info[] = {
-	[51] = { 0x10, 0, 3, },
-	[52] = { 0x10, 6, 3, },
-	[53] = { 0x10, 3, 3, },
-	[54] = { 0x10, 9, 3, },
-	[55] = { 0x10, 0, 3, },
-	[56] = { 0x10, 3, 3, },
-	[57] = { 0x10, 0, 3, },
-	[58] = { 0x10, 12, 3, },
-	[59] = { 0x10, 3, 3, },
-	[60] = { 0x10, 15, 3, },
-	[61] = { 0x10, 6, 3, },
-	[62] = { 0x10, 18, 3, },
-	[63] = { 0x10, 9, 3, },
-	[64] = { 0x10, 21, 3, },
-	[65] = { 0x10, 0, 3, },
-	[66] = { 0x10, 6, 3, },
-	[67] = { 0x10, 3, 3, },
-	[68] = { 0x10, 9, 3, },
-	[180] = { 0x10, 0, 3, },
-	[181] = { 0x10, 3, 3, },
+	[51] = { 0x20, 0, 3, },
+	[52] = { 0x20, 6, 3, },
+	[53] = { 0x20, 3, 3, },
+	[54] = { 0x20, 9, 3, },
+	[55] = { 0x20, 0, 3, },
+	[56] = { 0x20, 3, 3, },
+	[57] = { 0x40, 0, 3, },
+	[58] = { 0x40, 12, 3, },
+	[59] = { 0x40, 3, 3, },
+	[60] = { 0x40, 15, 3, },
+	[61] = { 0x40, 6, 3, },
+	[62] = { 0x40, 18, 3, },
+	[63] = { 0x40, 9, 3, },
+	[64] = { 0x40, 21, 3, },
+	[65] = { 0x20, 0, 3, },
+	[66] = { 0x20, 6, 3, },
+	[67] = { 0x20, 3, 3, },
+	[68] = { 0x20, 9, 3, },
+	[180] = { 0x30, 0, 3, },
+	[181] = { 0x30, 3, 3, },
 };
 
 void *gpio_find_reg_addr(gpio_t gpio)
diff --git a/src/soc/mediatek/mt8189/include/soc/gpio.h b/src/soc/mediatek/mt8189/include/soc/gpio.h
index 91914f1258..ff7eaf72e9 100644
--- a/src/soc/mediatek/mt8189/include/soc/gpio.h
+++ b/src/soc/mediatek/mt8189/include/soc/gpio.h
@@ -23,553 +23,553 @@ struct gpio_regs {
 };
 
 enum {
-	PIN(0, GPIO00, 0, 0, 0x01, 0,
+	PIN(0, GPIO00, 0, 5, 0x22, 0x00a0,
 	    TP_GPIO0_AO, SPIM3_A_CSB, I2SOUT0_MCK, SCP_SPI0_CS,
 	    RES5, CONN_BPI_BUS6, DBG_MON_A0),
-	PIN(1, GPIO01, 0, 0, 0x01, 0,
+	PIN(1, GPIO01, 0, 3, 0x13, 0x0090,
 	    TP_GPIO1_AO, SPIM3_A_CLK, I2SOUT0_BCK, SCP_SPI0_CK,
 	    RES5, CONN_BPI_BUS7, DBG_MON_A1),
-	PIN(2, GPIO02, 0, 0, 0x01, 0,
+	PIN(2, GPIO02, 0, 4, 0x13, 0x0090,
 	    TP_GPIO2_AO, SPIM3_A_MO, I2SOUT0_LRCK, SCP_SPI0_MO,
 	    RES5, CONN_BPI_BUS8, DBG_MON_A2),
-	PIN(3, GPIO03, 0, 0, 0x01, 0,
+	PIN(3, GPIO03, 0, 5, 0x13, 0x0090,
 	    TP_GPIO3_AO, SPIM3_A_MI, I2SOUT0_DO, SCP_SPI0_MI,
 	    RES5, CONN_BPI_BUS9, DBG_MON_A3),
-	PIN(4, GPIO04, 0, 0, 0x01, 0,
+	PIN(4, GPIO04, 0, 6, 0x13, 0x0090,
 	    TP_GPIO4_AO, SPIM4_A_CSB, I2SIN0_DI, SCP_SPI1_CS,
 	    RES5, CONN_BPI_BUS10, DBG_MON_A4),
-	PIN(5, GPIO05, 0, 0, 0x01, 0,
+	PIN(5, GPIO05, 0, 7, 0x13, 0x0090,
 	    TP_GPIO5_AO, SPIM4_A_CLK, I2SIN0_BCK, SCP_SPI1_CK,
 	    RES5, CONN_BPI_BUS11_OLAT0, DBG_MON_A5),
-	PIN(6, GPIO06, 0, 0, 0x01, 0,
+	PIN(6, GPIO06, 0, 6, 0x22, 0x00a0,
 	    TP_GPIO6_AO, SPIM4_A_MO, I2SIN0_LRCK, SCP_SPI1_MO,
 	    RES5, CONN_BPI_BUS12_OLAT1, DBG_MON_A6),
-	PIN(7, GPIO07, 0, 0, 0x01, 0,
+	PIN(7, GPIO07, 0, 7, 0x22, 0x00a0,
 	    TP_GPIO7_AO, SPIM4_A_MI, I2SIN0_MCK, SCP_SPI1_MI,
 	    RES5, CONN_BPI_BUS13_OLAT2, DBG_MON_A7),
-	PIN(8, GPIO08, 0, 0, 0x01, 0,
+	PIN(8, GPIO08, 0, 8, 0x22, 0x00a0,
 	    TP_UTXD1_VLP, SPIM5_A_CSB, I2SOUT1_MCK, VADSP_UTXD0,
 	    RES5, CONN_BPI_BUS14_OLAT3, DBG_MON_A8),
-	PIN(9, GPIO09, 0, 0, 0x01, 0,
+	PIN(9, GPIO09, 0, 9, 0x22, 0x00a0,
 	    TP_URXD1_VLP, SPIM5_A_CLK, I2SOUT1_BCK, VADSP_URXD0,
 	    RES5, CONN_BPI_BUS15_OLAT4, DBG_MON_A9),
-	PIN(10, GPIO10, 0, 0, 0x01, 0,
+	PIN(10, GPIO10, 0, 10, 0x22, 0x00a0,
 	    TP_UCTS1_VLP, SPIM5_A_MO, I2SOUT1_LRCK, SRCLKENAI0,
 	    RES5, CONN_BPI_BUS16_OLAT5, DBG_MON_A10),
-	PIN(11, GPIO11, 0, 0, 0x01, 0,
+	PIN(11, GPIO11, 0, 11, 0x22, 0x00a0,
 	    TP_URTS1_VLP, SPIM5_A_MI, I2SOUT1_DO, SRCLKENAI1,
 	    PWM_vlp, RES6, DBG_MON_A11),
-	PIN(12, GPIO12, 0, 0, 0x01, 0,
+	PIN(12, GPIO12, 0, 5, 0x15, 0x00b0,
 	    TP_UTXD1_VCORE, UTXD3, CLKM0, CMFLASH0,
 	    RES5, ANT_SEL0, DBG_MON_B20),
-	PIN(13, GPIO13, 0, 0, 0x01, 0,
+	PIN(13, GPIO13, 0, 6, 0x15, 0x00b0,
 	    TP_URXD1_VCORE, URXD3, CLKM1, CMFLASH1,
 	    RES5, ANT_SEL1, DBG_MON_B21),
-	PIN(14, GPIO14, 0, 0, 0x01, 0,
+	PIN(14, GPIO14, 0, 0, 0x26, 0x00a0,
 	    TP_UCTS1_VCORE, UCTS3, CLKM2, CMFLASH2,
 	    RES5, ANT_SEL2, DBG_MON_B22),
-	PIN(15, GPIO15, 0, 0, 0x01, 0,
+	PIN(15, GPIO15, 0, 1, 0x26, 0x00a0,
 	    TP_URTS1_VCORE, URTS3, CLKM3, CMVREF0,
 	    RES5, ANT_SEL3, DBG_MON_B23),
-	PIN(16, GPIO16, 0, 0, 0x01, 0,
+	PIN(16, GPIO16, 0, 7, 0x15, 0x00b0,
 	    PWM_0, UCTS2, DP_TX_HPD, CMVREF1,
 	    MD32_0_GPIO0, ANT_SEL4, DBG_MON_B24),
-	PIN(17, GPIO17, 0, 0, 0x01, 0,
+	PIN(17, GPIO17, 0, 8, 0x15, 0x00b0,
 	    PWM_1, URTS2, EDP_TX_HPD, CMVREF2,
 	    MD32_1_GPIO0, PMSR_SMAP, DBG_MON_B25),
-	PIN(18, CMMPDN0, 0, 0, 0x01, 0,
+	PIN(18, CMMPDN0, 0, 0, 0x22, 0x00a0,
 	    CMFLASH0, CMVREF3, UTXD2, DISP_PWM1,
 	    I2SIN1_MCK, mbistreaden_trigger, DBG_MON_A12),
-	PIN(19, CMMRST0, 0, 0, 0x01, 0,
+	PIN(19, CMMRST0, 0, 2, 0x22, 0x00a0,
 	    CMFLASH1, CMVREF2, URXD2, USB_DRVVBUS_1P,
 	    I2SIN1_BCK, mbistwriteen_trigger, DBG_MON_A13),
-	PIN(20, CMMPDN1, 0, 0, 0x01, 0,
+	PIN(20, CMMPDN1, 0, 1, 0x22, 0x00a0,
 	    CMFLASH2, CMVREF1, UCTS2, PERSTN,
 	    I2SIN1_LRCK, DMIC0_DAT1, DBG_MON_A14),
-	PIN(21, CMMRST1, 0, 0, 0x01, 0,
+	PIN(21, CMMRST1, 0, 3, 0x22, 0x00a0,
 	    CMFLASH3, CMVREF0, URTS2, CLKREQN,
 	    I2SIN1_DI, DMIC1_DAT1, DBG_MON_A15),
-	PIN(22, CMMCLK0, 0, 0, 0x01, 0,
+	PIN(22, CMMCLK0, 0, 0, 0x29, 0x0090,
 	    CMMCLK0, TP_GPIO4_AO, RES3, RES4,
 	    RES5, RES6, RES7),
-	PIN(23, CMMCLK1, 0, 0, 0x01, 0,
+	PIN(23, CMMCLK1, 0, 1, 0x29, 0x0090,
 	    CMMCLK1, TP_GPIO5_AO, SSPM_UTXD_AO_VLP, PWM_vlp,
 	    RES5, SRCLKENAI0, RES7),
-	PIN(24, CMMCLK2, 0, 0, 0x01, 0,
+	PIN(24, CMMCLK2, 0, 2, 0x29, 0x0090,
 	    CMMCLK2, TP_GPIO6_AO, SSPM_URXD_AO_VLP, WAKEN,
 	    SPMI_P_TRIG_FLAG, SRCLKENAI1, RES7),
-	PIN(25, DSI_LCM_RST, 0, 0, 0x01, 0,
+	PIN(25, DSI_LCM_RST, 0, 2, 0x11, 0x0090,
 	    LCM_RST, DP_TX_HPD, CMFLASH3, MD32_0_GPIO0,
 	    USB_DRVVBUS_2P, RES6, RES7),
-	PIN(26, DSI_DSI_TE, 0, 0, 0x01, 0,
+	PIN(26, DSI_DSI_TE, 0, 1, 0x11, 0x0090,
 	    DSI_TE, EDP_TX_HPD, CMVREF3, MD32_1_GPIO0,
 	    USB_DRVVBUS_3P, RES6, RES7),
-	PIN(27, DP_TX_HPD, 0, 0, 0x01, 0,
+	PIN(27, DP_TX_HPD, 0, 1, 0x15, 0x00b0,
 	    DP_TX_HPD, mbistreaden_trigger, MD32_0_GPIO0, TP_UCTS1_VCORE,
 	    CMVREF4, EXTIF0_ACT, ANT_SEL0),
-	PIN(28, EDP_TX_HPD, 0, 0, 0x01, 0,
+	PIN(28, EDP_TX_HPD, 0, 2, 0x15, 0x00b0,
 	    EDP_TX_HPD, mbistwriteen_trigger, MD32_1_GPIO0, TP_URTS1_VCORE,
 	    RES5, EXTIF0_PRI, ANT_SEL1),
-	PIN(29, DISP_PWM0, 0, 0, 0x01, 0,
+	PIN(29, DISP_PWM0, 0, 0, 0x11, 0x0090,
 	    DISP_PWM0, MD32_1_TXD, SSPM_UTXD_AO_VCORE, RES4,
 	    USB_DRVVBUS_4P, RES6, RES7),
-	PIN(30, DISP_PWM1, 0, 0, 0x01, 0,
+	PIN(30, DISP_PWM1, 0, 0, 0x15, 0x00b0,
 	    DISP_PWM1, MD32_1_RXD, SSPM_URXD_AO_VCORE, RES4,
 	    PMSR_SMAP, EXTIF0_GNT_B, ANT_SEL2),
-	PIN(31, UART0_TXD, 0, 0, 0x01, 0,
+	PIN(31, UART0_TXD, 0, 13, 0x26, 0x00a0,
 	    UTXD0, MD32_0_TXD, RES3, RES4,
 	    RES5, RES6, RES7),
-	PIN(32, UART0_RXD, 0, 0, 0x01, 0,
+	PIN(32, UART0_RXD, 0, 30, 0x14, 0x0090,
 	    URXD0, MD32_0_RXD, RES3, RES4,
 	    RES5, RES6, RES7),
-	PIN(33, UART1_TXD, 0, 0, 0x01, 0,
+	PIN(33, UART1_TXD, 0, 15, 0x26, 0x00a0,
 	    UTXD1, VADSP_UTXD0, TP_UTXD1_VLP, MD32_1_TXD,
 	    CONN_BGF_UART0_TXD, CONN_WIFI_TXD, RES7),
-	PIN(34, UART1_RXD, 0, 0, 0x01, 0,
+	PIN(34, UART1_RXD, 0, 14, 0x26, 0x00a0,
 	    URXD1, VADSP_URXD0, TP_URXD1_VLP, MD32_1_RXD,
 	    CONN_BGF_UART0_RXD, RES6, RES7),
-	PIN(35, UART2_TXD, 0, 0, 0x01, 0,
+	PIN(35, UART2_TXD, 0, 17, 0x26, 0x00a0,
 	    UTXD2, UCTS1, TP_UCTS1_VLP, SSPM_UTXD_AO_VLP,
 	    VADSP_UTXD0, CONN_BT_TXD, RES7),
-	PIN(36, UART2_RXD, 0, 0, 0x01, 0,
+	PIN(36, UART2_RXD, 0, 16, 0x26, 0x00a0,
 	    URXD2, URTS1, TP_URTS1_VLP, SSPM_URXD_AO_VLP,
 	    VADSP_URXD0, RES6, RES7),
-	PIN(37, UART3_TXD, 0, 0, 0x01, 0,
+	PIN(37, UART3_TXD, 0, 19, 0x26, 0x00a0,
 	    UTXD3, UCTS0, TP_UTXD1_VCORE, SSPM_UTXD_AO_VCORE,
 	    RES5, MD32_0_TXD, CONN_BGF_UART0_TXD),
-	PIN(38, UART3_RXD, 0, 0, 0x01, 0,
+	PIN(38, UART3_RXD, 0, 18, 0x26, 0x00a0,
 	    URXD3, URTS0, TP_URXD1_VCORE, SSPM_URXD_AO_VCORE,
 	    RES5, MD32_0_RXD, CONN_BGF_UART0_RXD),
-	PIN(39, JTMS, 0, 0, 0x01, 0,
+	PIN(39, JTMS, 0, 5, 0x26, 0x00a0,
 	    JTMS_SEL1, RES2, RES3, RES4,
 	    RES5, RES6, RES7),
-	PIN(40, JTCK, 0, 0, 0x01, 0,
+	PIN(40, JTCK, 0, 2, 0x26, 0x00a0,
 	    JTCK_SEL1, RES2, RES3, RES4,
 	    RES5, RES6, RES7),
-	PIN(41, JTDI, 0, 0, 0x01, 0,
+	PIN(41, JTDI, 0, 3, 0x26, 0x00a0,
 	    JTDI_SEL1, RES2, RES3, RES4,
 	    RES5, RES6, RES7),
-	PIN(42, JTDO, 0, 0, 0x01, 0,
+	PIN(42, JTDO, 0, 4, 0x26, 0x00a0,
 	    JTDO_SEL1, RES2, RES3, RES4,
 	    RES5, RES6, RES7),
-	PIN(43, JTRST, 0, 0, 0x01, 0,
+	PIN(43, JTRST, 0, 6, 0x26, 0x00a0,
 	    JTRSTn_SEL1, RES2, RES3, RES4,
 	    RES5, RES6, RES7),
-	PIN(44, KPCOL0, 0, 0, 0x01, 0,
+	PIN(44, KPCOL0, 1, 0, 0x22, 0x0090,
 	    KPCOL0, RES2, RES3, RES4,
 	    RES5, RES6, RES7),
-	PIN(45, KPCOL1, 0, 0, 0x01, 0,
+	PIN(45, KPCOL1, 1, 1, 0x22, 0x0090,
 	    KPCOL1, TP_GPIO0_AO, SRCLKENAI1, RES4,
 	    RES5, RES6, DBG_MON_A31),
-	PIN(46, KPROW0, 0, 0, 0x01, 0,
+	PIN(46, KPROW0, 1, 2, 0x22, 0x0090,
 	    KPROW0, TP_GPIO1_AO, RES3, RES4,
 	    RES5, RES6, RES7),
-	PIN(47, KPROW1, 0, 0, 0x01, 0,
+	PIN(47, KPROW1, 1, 3, 0x22, 0x0090,
 	    KPROW1, TP_GPIO2_AO, SRCLKENAI0, RES4,
 	    RES5, RES6, DBG_MON_A32),
-	PIN(48, PCIE_WAKE_N, 0, 0, 0x01, 0,
+	PIN(48, PCIE_WAKE_N, 0, 5, 0x11, 0x0090,
 	    WAKEN, TP_GPIO3_AO, SPMI_P_TRIG_FLAG, RES4,
 	    RES5, RES6, RES7),
-	PIN(49, PCIE_PERESET_N, 0, 0, 0x01, 0,
+	PIN(49, PCIE_PERESET_N, 0, 4, 0x11, 0x0090,
 	    PERSTN, MD32_0_GPIO0, UFS_MPHY_SCL, RES4,
 	    RES5, RES6, ANT_SEL3),
-	PIN(50, PCIE_CLKREQ_N, 0, 0, 0x01, 0,
+	PIN(50, PCIE_CLKREQ_N, 0, 3, 0x11, 0x0090,
 	    CLKREQN, MD32_1_GPIO0, UFS_MPHY_SDA, RES4,
 	    RES5, RES6, ANT_SEL4),
-	PIN(51, SCP_SCL0, 0, 0, 0x01, 0,
+	PIN(51, SCP_SCL0, 0, 8, 0x13, 0x0090,
 	    SCP_SCL0, SCL0, RES3, RES4,
 	    RES5, RES6, RES7),
-	PIN(52, SCP_SDA0, 0, 0, 0x01, 0,
+	PIN(52, SCP_SDA0, 0, 10, 0x13, 0x0090,
 	    SCP_SDA0, SDA0, RES3, RES4,
 	    RES5, RES6, RES7),
-	PIN(53, SCP_SCL1, 0, 0, 0x01, 0,
+	PIN(53, SCP_SCL1, 0, 9, 0x13, 0x0090,
 	    SCP_SCL1, SCL1, RES3, RES4,
 	    RES5, RES6, RES7),
-	PIN(54, SCP_SDA1, 0, 0, 0x01, 0,
+	PIN(54, SCP_SDA1, 0, 11, 0x13, 0x0090,
 	    SCP_SDA1, SDA1, RES3, RES4,
 	    RES5, RES6, RES7),
-	PIN(55, SCL2, 0, 0, 0x01, 0,
+	PIN(55, SCL2, 0, 6, 0x11, 0x0090,
 	    SCL2, UFS_MPHY_SCL, SSUSB_U2SIF_SCL, RES4,
 	    RES5, RES6, RES7),
-	PIN(56, SDA2, 0, 0, 0x01, 0,
+	PIN(56, SDA2, 0, 7, 0x11, 0x0090,
 	    SDA2, UFS_MPHY_SDA, SSUSB_U2SIF_SDA, RES4,
 	    RES5, RES6, RES7),
-	PIN(57, SCL3, 0, 0, 0x01, 0,
+	PIN(57, SCL3, 0, 13, 0x15, 0x00b0,
 	    SCL3, PCIE_PHY_I2C_SCL, SSUSB_U2SIF_SCL_1P, RES4,
 	    RES5, RES6, RES7),
-	PIN(58, SDA3, 0, 0, 0x01, 0,
+	PIN(58, SDA3, 0, 17, 0x15, 0x00b0,
 	    SDA3, PCIE_PHY_I2C_SDA, SSUSB_U2SIF_SDA_1P, RES4,
 	    RES5, RES6, RES7),
-	PIN(59, SCL4, 0, 0, 0x01, 0,
+	PIN(59, SCL4, 0, 14, 0x15, 0x00b0,
 	    SCL4, SSUSB_U3PHY_I2C_SCL, RES3, RES4,
 	    RES5, RES6, RES7),
-	PIN(60, SDA4, 0, 0, 0x01, 0,
+	PIN(60, SDA4, 0, 18, 0x15, 0x00b0,
 	    SDA4, SSUSB_U3PHY_I2C_SDA, RES3, RES4,
 	    RES5, RES6, RES7),
-	PIN(61, SCL5, 0, 0, 0x01, 0,
+	PIN(61, SCL5, 0, 15, 0x15, 0x00b0,
 	    SCL5, SSPXTP_U3PHY_I2C_SCL, RES3, RES4,
 	    RES5, RES6, RES7),
-	PIN(62, SDA5, 0, 0, 0x01, 0,
+	PIN(62, SDA5, 0, 19, 0x15, 0x00b0,
 	    SDA5, SSPXTP_U3PHY_I2C_SDA, RES3, RES4,
 	    RES5, RES6, RES7),
-	PIN(63, SCL6, 0, 0, 0x01, 0,
+	PIN(63, SCL6, 0, 16, 0x15, 0x00b0,
 	    SCL6, RES2, RES3, RES4,
 	    RES5, RES6, RES7),
-	PIN(64, SDA6, 0, 0, 0x01, 0,
+	PIN(64, SDA6, 0, 20, 0x15, 0x00b0,
 	    SDA6, RES2, RES3, RES4,
 	    RES5, RES6, RES7),
-	PIN(65, SCL7, 0, 0, 0x01, 0,
+	PIN(65, SCL7, 0, 4, 0x29, 0x0090,
 	    SCL7, RES2, RES3, RES4,
 	    RES5, RES6, RES7),
-	PIN(66, SDA7, 0, 0, 0x01, 0,
+	PIN(66, SDA7, 0, 6, 0x29, 0x0090,
 	    SDA7, RES2, RES3, RES4,
 	    RES5, RES6, RES7),
-	PIN(67, SCL8, 0, 0, 0x01, 0,
+	PIN(67, SCL8, 0, 5, 0x29, 0x0090,
 	    SCL8, RES2, RES3, RES4,
 	    RES5, RES6, RES7),
-	PIN(68, SDA8, 0, 0, 0x01, 0,
+	PIN(68, SDA8, 0, 7, 0x29, 0x0090,
 	    SDA8, RES2, RES3, RES4,
 	    RES5, RES6, RES7),
-	PIN(69, SPIM0_CSB, 0, 0, 0x01, 0,
+	PIN(69, SPIM0_CSB, 0, 22, 0x15, 0x00b0,
 	    SPIM0_CSB, SCP_SPI0_CS, SPM_JTAG_TMS_VCORE, VADSP_JTAG0_TMS,
 	    SPM_JTAG_TMS, SSPM_JTAG_TMS_VLP, SCP_JTAG0_TMS_VLP),
-	PIN(70, SPIM0_CLK, 0, 0, 0x01, 0,
+	PIN(70, SPIM0_CLK, 0, 21, 0x15, 0x00b0,
 	    SPIM0_CLK, SCP_SPI0_CK, SPM_JTAG_TCK_VCORE, VADSP_JTAG0_TCK,
 	    SPM_JTAG_TCK, SSPM_JTAG_TCK_VLP, SCP_JTAG0_TCK_VLP),
-	PIN(71, SPIM0_MOSI, 0, 0, 0x01, 0,
+	PIN(71, SPIM0_MOSI, 0, 24, 0x15, 0x00b0,
 	    SPIM0_MO, SCP_SPI0_MO, SPM_JTAG_TDI_VCORE, VADSP_JTAG0_TDI,
 	    SPM_JTAG_TDI, SSPM_JTAG_TDI_VLP, SCP_JTAG0_TDI_VLP),
-	PIN(72, SPIM0_MISO, 0, 0, 0x01, 0,
+	PIN(72, SPIM0_MISO, 0, 23, 0x15, 0x00b0,
 	    SPIM0_MI, SCP_SPI0_MI, SPM_JTAG_TDO_VCORE, VADSP_JTAG0_TDO,
 	    SPM_JTAG_TDO, SSPM_JTAG_TDO_VLP, SCP_JTAG0_TDO_VLP),
-	PIN(73, SPIM1_CSB, 0, 0, 0x01, 0,
+	PIN(73, SPIM1_CSB, 0, 26, 0x15, 0x00b0,
 	    SPIM1_CSB, SCP_SPI1_CS, SPM_JTAG_TRSTN_VCORE, VADSP_JTAG0_TRSTN,
 	    SPM_JTAG_TRSTN, SSPM_JTAG_TRSTN_VLP, SCP_JTAG0_TRSTN_VLP),
-	PIN(74, SPIM1_CLK, 0, 0, 0x01, 0,
+	PIN(74, SPIM1_CLK, 0, 25, 0x15, 0x00b0,
 	    SPIM1_CLK, SCP_SPI1_CK, RES3, RES4,
 	    RES5, RES6, RES7),
-	PIN(75, SPIM1_MOSI, 0, 0, 0x01, 0,
+	PIN(75, SPIM1_MOSI, 0, 7, 0x26, 0x00a0,
 	    SPIM1_MO, SCP_SPI1_MO, RES3, RES4,
 	    RES5, RES6, RES7),
-	PIN(76, SPIM1_MISO, 0, 0, 0x01, 0,
+	PIN(76, SPIM1_MISO, 0, 27, 0x15, 0x00b0,
 	    SPIM1_MI, SCP_SPI1_MI, RES3, RES4,
 	    RES5, RES6, RES7),
-	PIN(77, SPIM2_CSB, 0, 0, 0x01, 0,
+	PIN(77, SPIM2_CSB, 0, 13, 0x13, 0x0090,
 	    SPIM2_CSB, PCM0_SYNC, SSUSB_U2SIF_SCL, RES4,
 	    RES5, RES6, DBG_MON_A27),
-	PIN(78, SPIM2_CLK, 0, 0, 0x01, 0,
+	PIN(78, SPIM2_CLK, 0, 12, 0x13, 0x0090,
 	    SPIM2_CLK, PCM0_CLK, SSUSB_U2SIF_SDA, RES4,
 	    RES5, RES6, DBG_MON_A28),
-	PIN(79, SPIM2_MOSI, 0, 0, 0x01, 0,
+	PIN(79, SPIM2_MOSI, 0, 15, 0x13, 0x0090,
 	    SPIM2_MO, PCM0_DO, SSUSB_U2SIF_SCL_1P, RES4,
 	    RES5, RES6, DBG_MON_A29),
-	PIN(80, SPIM2_MISO, 0, 0, 0x01, 0,
+	PIN(80, SPIM2_MISO, 0, 14, 0x13, 0x0090,
 	    SPIM2_MI, PCM0_DI, SSUSB_U2SIF_SDA_1P, RES4,
 	    RES5, RES6, DBG_MON_A30),
-	PIN(81, USB0_IDDIG, 0, 0, 0x01, 0,
+	PIN(81, USB0_IDDIG, 0, 29, 0x15, 0x00b0,
 	    IDDIG, RES2, RES3, RES4,
 	    RES5, RES6, DBG_MON_B32),
-	PIN(82, USB0_DRV_VBUS, 0, 0, 0x01, 0,
+	PIN(82, USB0_DRV_VBUS, 0, 28, 0x15, 0x00b0,
 	    USB_DRVVBUS, RES2, RES3, RES4,
 	    RES5, RES6, RES7),
-	PIN(83, USB0_VBUS_VALID, 0, 0, 0x01, 0,
+	PIN(83, USB0_VBUS_VALID, 0, 30, 0x15, 0x00b0,
 	    VBUSVALID, RES2, RES3, RES4,
 	    RES5, RES6, RES7),
-	PIN(84, USB1_DRV_VBUS, 0, 0, 0x01, 0,
+	PIN(84, USB1_DRV_VBUS, 0, 22, 0x22, 0x00a0,
 	    USB_DRVVBUS_1P, RES2, RES3, RES4,
 	    RES5, RES6, DBG_MON_A16),
-	PIN(85, USB2_DRV_VBUS, 0, 0, 0x01, 0,
+	PIN(85, USB2_DRV_VBUS, 0, 23, 0x22, 0x00a0,
 	    USB_DRVVBUS_2P, RES2, RES3, RES4,
 	    RES5, RES6, DBG_MON_A17),
-	PIN(86, USB3_DRV_VBUS, 0, 0, 0x01, 0,
+	PIN(86, USB3_DRV_VBUS, 0, 24, 0x22, 0x00a0,
 	    USB_DRVVBUS_3P, RES2, RES3, RES4,
 	    RES5, RES6, DBG_MON_A18),
-	PIN(87, USB4_DRV_VBUS, 0, 0, 0x01, 0,
+	PIN(87, USB4_DRV_VBUS, 0, 25, 0x22, 0x00a0,
 	    USB_DRVVBUS_4P, RES2, RES3, RES4,
 	    RES5, CMVREF4, DBG_MON_A19),
-	PIN(88, PWRAP_SPI_CSN, 0, 0, 0x01, 0,
+	PIN(88, PWRAP_SPI_CSN, 0, 11, 0x27, 0x00b0,
 	    PWRAP_SPI0_CSN, RES2, RES3, RES4,
 	    RES5, RES6, RES7),
-	PIN(89, PWRAP_SPI_CK, 0, 0, 0x01, 0,
+	PIN(89, PWRAP_SPI_CK, 0, 10, 0x27, 0x00b0,
 	    PWRAP_SPI0_CK, RES2, RES3, RES4,
 	    RES5, RES6, RES7),
-	PIN(90, PWRAP_SPI_MO, 0, 0, 0x01, 0,
+	PIN(90, PWRAP_SPI_MO, 0, 13, 0x27, 0x00b0,
 	    PWRAP_SPI0_MO, RES2, RES3, RES4,
 	    RES5, RES6, RES7),
-	PIN(91, PWRAP_SPI_MI, 0, 0, 0x01, 0,
+	PIN(91, PWRAP_SPI_MI, 0, 12, 0x27, 0x00b0,
 	    PWRAP_SPI0_MI, RES2, RES3, RES4,
 	    RES5, RES6, RES7),
-	PIN(92, PMIC_SRCLKENA0, 0, 0, 0x01, 0,
+	PIN(92, PMIC_SRCLKENA0, 0, 7, 0x27, 0x00b0,
 	    SRCLKENA0, RES2, RES3, RES4,
 	    RES5, RES6, RES7),
-	PIN(93, PMIC_SRCLKENA1, 0, 0, 0x01, 0,
+	PIN(93, PMIC_SRCLKENA1, 0, 8, 0x27, 0x00b0,
 	    SRCLKENA1, RES2, RES3, RES4,
 	    RES5, RES6, RES7),
-	PIN(94, SCP_VREQ_VAO, 0, 0, 0x01, 0,
+	PIN(94, SCP_VREQ_VAO, 0, 14, 0x27, 0x00b0,
 	    SCP_VREQ_VAO, RES2, RES3, RES4,
 	    RES5, RES6, RES7),
-	PIN(95, PMIC_RTC32K_CK, 0, 0, 0x01, 0,
+	PIN(95, PMIC_RTC32K_CK, 0, 6, 0x27, 0x00b0,
 	    RTC32K_CK, RES2, RES3, RES4,
 	    RES5, RES6, RES7),
-	PIN(96, PMIC_WATCHDOG, 0, 0, 0x01, 0,
+	PIN(96, PMIC_WATCHDOG, 0, 9, 0x27, 0x00b0,
 	    WATCHDOG, RES2, RES3, RES4,
 	    RES5, RES6, RES7),
-	PIN(97, AUD_CLK_MOSI, 0, 0, 0x01, 0,
+	PIN(97, AUD_CLK_MOSI, 0, 0, 0x27, 0x00b0,
 	    AUD_CLK_MOSI, RES2, RES3, RES4,
 	    RES5, RES6, RES7),
-	PIN(98, AUD_SYNC_MOSI, 0, 0, 0x01, 0,
+	PIN(98, AUD_SYNC_MOSI, 0, 5, 0x27, 0x00b0,
 	    AUD_SYNC_MOSI, RES2, RES3, RES4,
 	    RES5, RES6, RES7),
-	PIN(99, AUD_DAT_MOSI0, 0, 0, 0x01, 0,
+	PIN(99, AUD_DAT_MOSI0, 0, 3, 0x27, 0x00b0,
 	    AUD_DAT_MOSI0, RES2, RES3, RES4,
 	    RES5, RES6, RES7),
-	PIN(100, AUD_DAT_MOSI1, 0, 0, 0x01, 0,
+	PIN(100, AUD_DAT_MOSI1, 0, 4, 0x27, 0x00b0,
 	    AUD_DAT_MOSI1, RES2, RES3, RES4,
 	    RES5, RES6, RES7),
-	PIN(101, AUD_DAT_MISO0, 0, 0, 0x01, 0,
+	PIN(101, AUD_DAT_MISO0, 0, 1, 0x27, 0x00b0,
 	    AUD_DAT_MISO0, RES2, RES3, RES4,
 	    RES5, RES6, RES7),
-	PIN(102, AUD_DAT_MISO1, 0, 0, 0x01, 0,
+	PIN(102, AUD_DAT_MISO1, 0, 2, 0x27, 0x00b0,
 	    AUD_DAT_MISO1, RES2, RES3, RES4,
 	    RES5, RES6, RES7),
-	PIN(103, I2SIN0_MCK, 0, 0, 0x01, 0,
+	PIN(103, I2SIN0_MCK, 0, 15, 0x22, 0x00a0,
 	    I2SIN0_MCK, SPIM3_B_CSB, APU_JTAG_TMS, SCP_JTAG0_TMS_VCORE,
 	    CONN_WF_MCU_TMS, SSPM_JTAG_TMS_VCORE, IPU_JTAG_TMS),
-	PIN(104, I2SIN0_BCK, 0, 0, 0x01, 0,
+	PIN(104, I2SIN0_BCK, 0, 12, 0x22, 0x00a0,
 	    I2SIN0_BCK, SPIM3_B_CLK, APU_JTAG_TCK, SCP_JTAG0_TCK_VCORE,
 	    CONN_WF_MCU_TCK, SSPM_JTAG_TCK_VCORE, IPU_JTAG_TCK),
-	PIN(105, I2SIN0_LRCK, 0, 0, 0x01, 0,
+	PIN(105, I2SIN0_LRCK, 0, 14, 0x22, 0x00a0,
 	    I2SIN0_LRCK, SPIM3_B_MO, APU_JTAG_TDI, SCP_JTAG0_TDI_VCORE,
 	    CONN_WF_MCU_TDI, SSPM_JTAG_TDI_VCORE, IPU_JTAG_TDI),
-	PIN(106, I2SIN0_DI, 0, 0, 0x01, 0,
+	PIN(106, I2SIN0_DI, 0, 13, 0x22, 0x00a0,
 	    I2SIN0_DI, SPIM3_B_MI, APU_JTAG_TDO, SCP_JTAG0_TDO_VCORE,
 	    CONN_WF_MCU_TDO, SSPM_JTAG_TDO_VCORE, IPU_JTAG_TDO),
-	PIN(107, I2SOUT0_MCK, 0, 0, 0x01, 0,
+	PIN(107, I2SOUT0_MCK, 0, 19, 0x22, 0x00a0,
 	    I2SOUT0_MCK, SPIM4_B_CSB, APU_JTAG_TRST, SCP_JTAG0_TRSTN_VCORE,
 	    CONN_WF_MCU_TRST_B, SSPM_JTAG_TRSTN_VCORE, IPU_JTAG_TRST),
-	PIN(108, I2SOUT0_BCK, 0, 0, 0x01, 0,
+	PIN(108, I2SOUT0_BCK, 0, 16, 0x22, 0x00a0,
 	    I2SOUT0_BCK, SPIM4_B_CLK, EXTIF0_ACT, SPM_JTAG_TMS_VCORE,
 	    RES5, CLKM2, DBG_MON_A20),
-	PIN(109, I2SOUT0_LRCK, 0, 0, 0x01, 0,
+	PIN(109, I2SOUT0_LRCK, 0, 18, 0x22, 0x00a0,
 	    I2SOUT0_LRCK, SPIM4_B_MO, EXTIF0_PRI, SPM_JTAG_TCK_VCORE,
 	    RES5, CLKM3, DBG_MON_A21),
-	PIN(110, I2SOUT0_DO, 0, 0, 0x01, 0,
+	PIN(110, I2SOUT0_DO, 0, 17, 0x22, 0x00a0,
 	    I2SOUT0_DO, SPIM4_B_MI, EXTIF0_GNT_B, SPM_JTAG_TDI_VCORE,
 	    RES5, RES6, DBG_MON_A22),
-	PIN(111, DMIC0_CLK, 0, 0, 0x01, 0,
+	PIN(111, DMIC0_CLK, 0, 4, 0x22, 0x00a0,
 	    DMIC0_CLK, I2SIN1_MCK, I2SOUT1_MCK, SPM_JTAG_TDO_VCORE,
 	    RES5, CONN_MIPI0_SDATA, DBG_MON_A23),
-	PIN(112, DMIC0_DAT0, 0, 0, 0x01, 0,
+	PIN(112, DMIC0_DAT0, 0, 0, 0x13, 0x0090,
 	    DMIC0_DAT0, I2SIN1_BCK, I2SOUT1_BCK, SPM_JTAG_TRSTN_VCORE,
 	    RES5, CONN_MIPI0_SCLK, DBG_MON_A24),
-	PIN(113, DMIC1_CLK, 0, 0, 0x01, 0,
+	PIN(113, DMIC1_CLK, 0, 1, 0x13, 0x0090,
 	    DMIC1_CLK, I2SIN1_LRCK, I2SOUT1_LRCK, PMSR_SMAP,
 	    RES5, CONN_MIPI1_SDATA, DBG_MON_A25),
-	PIN(114, DMIC1_DAT0, 0, 0, 0x01, 0,
+	PIN(114, DMIC1_DAT0, 0, 2, 0x13, 0x0090,
 	    DMIC1_DAT0, I2SIN1_DI, I2SOUT1_DO, RES4,
 	    RES5, CONN_MIPI1_SCLK, DBG_MON_A26),
-	PIN(115, PCM_CLK, 0, 0, 0x01, 0,
+	PIN(115, PCM_CLK, 0, 9, 0x15, 0x00b0,
 	    PCM0_CLK, USB_DRVVBUS_1P, PCIE_PHY_I2C_SCL, SSUSB_U3PHY_I2C_SCL,
 	    RES5, CMFLASH0, EXTIF0_ACT),
-	PIN(116, PCM_SYNC, 0, 0, 0x01, 0,
+	PIN(116, PCM_SYNC, 0, 12, 0x15, 0x00b0,
 	    PCM0_SYNC, USB_DRVVBUS_2P, PCIE_PHY_I2C_SDA, SSUSB_U3PHY_I2C_SDA,
 	    RES5, CMFLASH1, EXTIF0_PRI),
-	PIN(117, PCM_DI, 0, 0, 0x01, 0,
+	PIN(117, PCM_DI, 0, 10, 0x15, 0x00b0,
 	    PCM0_DI, USB_DRVVBUS_3P, DP_TX_HPD, SSPXTP_U3PHY_I2C_SCL,
 	    RES5, CMVREF0, EXTIF0_GNT_B),
-	PIN(118, PCM_DO, 0, 0, 0x01, 0,
+	PIN(118, PCM_DO, 0, 11, 0x15, 0x00b0,
 	    PCM0_DO, USB_DRVVBUS_4P, EDP_TX_HPD, SSPXTP_U3PHY_I2C_SDA,
 	    RES5, CMVREF1, RES7),
-	PIN(119, GBE_TXD3, 0, 0, 0x01, 0,
+	PIN(119, GBE_TXD3, 0, 26, 0x14, 0x0090,
 	    GBE_TXD3, DMIC0_CLK, LVTS_FOUT, CONN_BGF_MCU_TMS,
 	    UDI_TMS, ANT_SEL5, DBG_MON_B0),
-	PIN(120, GBE_TXD2, 0, 0, 0x01, 0,
+	PIN(120, GBE_TXD2, 0, 25, 0x14, 0x0090,
 	    GBE_TXD2, DMIC0_DAT0, LVTS_SDO, CONN_BGF_MCU_TCK,
 	    UDI_TCK, ANT_SEL6, DBG_MON_B1),
-	PIN(121, GBE_TXD1, 0, 0, 0x01, 0,
+	PIN(121, GBE_TXD1, 0, 24, 0x14, 0x0090,
 	    GBE_TXD1, DMIC0_DAT1, LVTS_26M, CONN_BGF_MCU_TDI,
 	    UDI_TDI, ANT_SEL7, DBG_MON_B2),
-	PIN(122, GBE_TXD0, 0, 0, 0x01, 0,
+	PIN(122, GBE_TXD0, 0, 23, 0x14, 0x0090,
 	    GBE_TXD0, DMIC1_CLK, LVTS_SCF, CONN_BGF_MCU_TDO,
 	    UDI_TDO, ANT_SEL8, DBG_MON_B3),
-	PIN(123, GBE_RXD3, 0, 0, 0x01, 0,
+	PIN(123, GBE_RXD3, 0, 19, 0x14, 0x0090,
 	    GBE_RXD3, DMIC1_DAT0, LVTS_SCK, CONN_BGF_MCU_TRST_B,
 	    UDI_NTRST, ANT_SEL9, DBG_MON_B4),
-	PIN(124, GBE_RXD2, 0, 0, 0x01, 0,
+	PIN(124, GBE_RXD2, 0, 18, 0x14, 0x0090,
 	    GBE_RXD2, DMIC1_DAT1, LVTS_SDI, CONN_WF_MCU_TMS,
 	    SCP_JTAG0_TMS_VCORE, ANT_SEL10, DBG_MON_B5),
-	PIN(125, GBE_RXD1, 0, 0, 0x01, 0,
+	PIN(125, GBE_RXD1, 0, 17, 0x14, 0x0090,
 	    GBE_RXD1, CLKM2, RES3, CONN_WF_MCU_TCK,
 	    SCP_JTAG0_TCK_VCORE, ANT_SEL11, DBG_MON_B6),
-	PIN(126, GBE_RXD0, 0, 0, 0x01, 0,
+	PIN(126, GBE_RXD0, 0, 16, 0x14, 0x0090,
 	    GBE_RXD0, CLKM3, RES3, CONN_WF_MCU_TDI,
 	    SCP_JTAG0_TDI_VCORE, ANT_SEL12, DBG_MON_B7),
-	PIN(127, GBE_TXC, 0, 0, 0x01, 0,
+	PIN(127, GBE_TXC, 0, 22, 0x14, 0x0090,
 	    GBE_TXC, I2SIN1_MCK, RES3, CONN_WF_MCU_TDO,
 	    SCP_JTAG0_TDO_VCORE, ANT_SEL13, DBG_MON_B8),
-	PIN(128, GBE_RXC, 0, 0, 0x01, 0,
+	PIN(128, GBE_RXC, 0, 15, 0x14, 0x0090,
 	    GBE_RXC, I2SIN1_BCK, RES3, CONN_WF_MCU_TRST_B,
 	    SCP_JTAG0_TRSTN_VCORE, ANT_SEL14, DBG_MON_B9),
-	PIN(129, GBE_RXDV, 0, 0, 0x01, 0,
+	PIN(129, GBE_RXDV, 0, 20, 0x14, 0x0090,
 	    GBE_RXDV, I2SIN1_LRCK, RES3, CONN_BGF_MCU_AICE_TMSC,
 	    IPU_JTAG_TMS, ANT_SEL15, DBG_MON_B10),
-	PIN(130, GBE_TXEN, 0, 0, 0x01, 0,
+	PIN(130, GBE_TXEN, 0, 27, 0x14, 0x0090,
 	    GBE_TXEN, I2SIN1_DI, RES3, CONN_BGF_MCU_AICE_TCKC,
 	    IPU_JTAG_TCK, ANT_SEL16, DBG_MON_B11),
-	PIN(131, GBE_MDC, 0, 0, 0x01, 0,
+	PIN(131, GBE_MDC, 0, 13, 0x14, 0x0090,
 	    GBE_MDC, CLKM0, mbistreaden_trigger, CONN_BGF_UART0_TXD,
 	    IPU_JTAG_TDI, ANT_SEL17, DBG_MON_B12),
-	PIN(132, GBE_MDIO, 0, 0, 0x01, 0,
+	PIN(132, GBE_MDIO, 0, 14, 0x14, 0x0090,
 	    GBE_MDIO, CLKM1, mbistwriteen_trigger, CONN_BGF_UART0_RXD,
 	    IPU_JTAG_TDO, ANT_SEL18, DBG_MON_B13),
-	PIN(133, GBE_TXER, 0, 0, 0x01, 0,
+	PIN(133, GBE_TXER, 0, 28, 0x14, 0x0090,
 	    GBE_TXER, GBE_AUX_PPS2, RES3, CONN_BT_TXD,
 	    IPU_JTAG_TRST, ANT_SEL19, DBG_MON_B14),
-	PIN(134, GBE_RXER, 0, 0, 0x01, 0,
+	PIN(134, GBE_RXER, 0, 21, 0x14, 0x0090,
 	    GBE_RXER, GBE_AUX_PPS3, MCUPM_JTAG_TMS, CONN_WF_MCU_AICE_TMSC,
 	    APU_JTAG_TMS, ANT_SEL20, DBG_MON_B15),
-	PIN(135, GBE_COL, 0, 0, 0x01, 0,
+	PIN(135, GBE_COL, 0, 11, 0x14, 0x0090,
 	    GBE_COL, I2SOUT1_MCK, MCUPM_JTAG_TCK, CONN_WF_MCU_AICE_TCKC,
 	    APU_JTAG_TCK, ANT_SEL21, DBG_MON_B16),
-	PIN(136, GBE_INTR, 0, 0, 0x01, 0,
+	PIN(136, GBE_INTR, 0, 12, 0x14, 0x0090,
 	    GBE_INTR, I2SOUT1_BCK, MCUPM_JTAG_TDI, CONN_WIFI_TXD,
 	    APU_JTAG_TDI, PWM_0, DBG_MON_B17),
-	PIN(137, GBE_AUX_PPS0, 0, 0, 0x01, 0,
+	PIN(137, GBE_AUX_PPS0, 0, 3, 0x15, 0x00b0,
 	    GBE_AUX_PPS0, I2SOUT1_LRCK, MCUPM_JTAG_TDO, DP_TX_HPD,
 	    APU_JTAG_TDO, PWM_1, DBG_MON_B18),
-	PIN(138, GBE_AUX_PPS1, 0, 0, 0x01, 0,
+	PIN(138, GBE_AUX_PPS1, 0, 4, 0x15, 0x00b0,
 	    GBE_AUX_PPS1, I2SOUT1_DO, MCUPM_JTAG_TRSTN, EDP_TX_HPD,
 	    APU_JTAG_TRST, PWM_2, DBG_MON_B19),
-	PIN(139, CONN_TOP_CLK, 0, 0, 0x01, 0,
+	PIN(139, CONN_TOP_CLK, 0, 3, 0x14, 0x0090,
 	    CONN_TOP_CLK, RES2, RES3, RES4,
 	    RES5, RES6, RES7),
-	PIN(140, CONN_TOP_DATA, 0, 0, 0x01, 0,
+	PIN(140, CONN_TOP_DATA, 0, 4, 0x14, 0x0090,
 	    CONN_TOP_DATA, RES2, RES3, RES4,
 	    RES5, RES6, RES7),
-	PIN(141, CONN_BT_CLK, 0, 0, 0x01, 0,
+	PIN(141, CONN_BT_CLK, 0, 0, 0x14, 0x0090,
 	    CONN_BT_CLK, RES2, RES3, RES4,
 	    RES5, RES6, RES7),
-	PIN(142, CONN_BT_DATA, 0, 0, 0x01, 0,
+	PIN(142, CONN_BT_DATA, 0, 1, 0x14, 0x0090,
 	    CONN_BT_DATA, RES2, RES3, RES4,
 	    RES5, RES6, RES7),
-	PIN(143, CONN_HRST_B, 0, 0, 0x01, 0,
+	PIN(143, CONN_HRST_B, 0, 2, 0x14, 0x0090,
 	    CONN_HRST_B, RES2, RES3, RES4,
 	    RES5, RES6, RES7),
-	PIN(144, CONN_WB_PTA, 0, 0, 0x01, 0,
+	PIN(144, CONN_WB_PTA, 0, 5, 0x14, 0x0090,
 	    CONN_WB_PTA, RES2, RES3, RES4,
 	    RES5, RES6, RES7),
-	PIN(145, CONN_WF_CTRL0, 0, 0, 0x01, 0,
+	PIN(145, CONN_WF_CTRL0, 0, 6, 0x14, 0x0090,
 	    CONN_WF_CTRL0, RES2, RES3, RES4,
 	    RES5, RES6, RES7),
-	PIN(146, CONN_WF_CTRL1, 0, 0, 0x01, 0,
+	PIN(146, CONN_WF_CTRL1, 0, 7, 0x14, 0x0090,
 	    CONN_WF_CTRL1, RES2, RES3, RES4,
 	    RES5, RES6, RES7),
-	PIN(147, CONN_WF_CTRL2, 0, 0, 0x01, 0,
+	PIN(147, CONN_WF_CTRL2, 0, 8, 0x14, 0x0090,
 	    CONN_WF_CTRL2, RES2, RES3, RES4,
 	    RES5, RES6, RES7),
-	PIN(148, CONN_WF_CTRL3, 0, 0, 0x01, 0,
+	PIN(148, CONN_WF_CTRL3, 0, 9, 0x14, 0x0090,
 	    CONN_WF_CTRL3, RES2, RES3, RES4,
 	    RES5, RES6, RES7),
-	PIN(149, CONN_WF_CTRL4, 0, 0, 0x01, 0,
+	PIN(149, CONN_WF_CTRL4, 0, 10, 0x14, 0x0090,
 	    CONN_WF_CTRL4, RES2, RES3, RES4,
 	    RES5, RES6, RES7),
-	PIN(150, SPINOR_CK, 0, 0, 0x01, 0,
+	PIN(150, SPINOR_CK, 0, 8, 0x26, 0x00a0,
 	    SPINOR_CK, DMIC0_CLK, DP_TX_HPD, PWM_0,
 	    CONN_BPI_BUS17_ANT0, LVTS_FOUT, DBG_MON_B26),
-	PIN(151, SPINOR_CS, 0, 0, 0x01, 0,
+	PIN(151, SPINOR_CS, 0, 29, 0x14, 0x0090,
 	    SPINOR_CS, DMIC0_DAT0, EDP_TX_HPD, PWM_1,
 	    CONN_BPI_BUS18_ANT1, LVTS_SDO, DBG_MON_B27),
-	PIN(152, SPINOR_IO0, 0, 0, 0x01, 0,
+	PIN(152, SPINOR_IO0, 0, 9, 0x26, 0x00a0,
 	    SPINOR_IO0, DMIC0_DAT1, UTXD2, USB_DRVVBUS_1P,
 	    CONN_BPI_BUS19_ANT2, LVTS_26M, DBG_MON_B28),
-	PIN(153, SPINOR_IO1, 0, 0, 0x01, 0,
+	PIN(153, SPINOR_IO1, 0, 10, 0x26, 0x00a0,
 	    SPINOR_IO1, DMIC1_CLK, UCTS2, USB_DRVVBUS_2P,
 	    CONN_BPI_BUS20_ANT3, LVTS_SCF, DBG_MON_B29),
-	PIN(154, SPINOR_IO2, 0, 0, 0x01, 0,
+	PIN(154, SPINOR_IO2, 0, 11, 0x26, 0x00a0,
 	    SPINOR_IO2, DMIC1_DAT0, URTS2, USB_DRVVBUS_3P,
 	    CONN_BPI_BUS21_ANT4, LVTS_SCK, DBG_MON_B30),
-	PIN(155, SPINOR_IO3, 0, 0, 0x01, 0,
+	PIN(155, SPINOR_IO3, 0, 12, 0x26, 0x00a0,
 	    SPINOR_IO3, DMIC1_DAT1, URXD2, USB_DRVVBUS_4P,
 	    DISP_PWM1, LVTS_SDI, DBG_MON_B31),
-	PIN(156, EMMC_DAT7, 0, 0, 0x01, 0,
+	PIN(156, EMMC_DAT7, 1, 6, 0x27, 0x00a0,
 	    MSDC0_DAT7, RES2, RES3, RES4,
 	    RES5, RES6, RES7),
-	PIN(157, EMMC_DAT6, 0, 0, 0x01, 0,
+	PIN(157, EMMC_DAT6, 1, 5, 0x27, 0x00a0,
 	    MSDC0_DAT6, RES2, RES3, RES4,
 	    RES5, RES6, RES7),
-	PIN(158, EMMC_DAT5, 0, 0, 0x01, 0,
+	PIN(158, EMMC_DAT5, 1, 4, 0x27, 0x00a0,
 	    MSDC0_DAT5, RES2, RES3, RES4,
 	    RES5, RES6, RES7),
-	PIN(159, EMMC_DAT4, 0, 0, 0x01, 0,
+	PIN(159, EMMC_DAT4, 1, 2, 0x18, 0x0050,
 	    MSDC0_DAT4, RES2, RES3, RES4,
 	    RES5, RES6, RES7),
-	PIN(160, EMMC_RSTB, 0, 0, 0x01, 0,
+	PIN(160, EMMC_RSTB, 1, 8, 0x27, 0x00a0,
 	    MSDC0_RSTB, RES2, RES3, RES4,
 	    RES5, RES6, RES7),
-	PIN(161, EMMC_CMD, 0, 0, 0x01, 0,
+	PIN(161, EMMC_CMD, 1, 1, 0x27, 0x00a0,
 	    MSDC0_CMD, RES2, RES3, RES4,
 	    RES5, RES6, RES7),
-	PIN(162, EMMC_CLK, 0, 0, 0x01, 0,
+	PIN(162, EMMC_CLK, 1, 0, 0x27, 0x00a0,
 	    MSDC0_CLK, RES2, RES3, RES4,
 	    RES5, RES6, RES7),
-	PIN(163, EMMC_DAT3, 0, 0, 0x01, 0,
+	PIN(163, EMMC_DAT3, 1, 1, 0x18, 0x0050,
 	    MSDC0_DAT3, RES2, RES3, RES4,
 	    RES5, RES6, RES7),
-	PIN(164, EMMC_DAT2, 0, 0, 0x01, 0,
+	PIN(164, EMMC_DAT2, 1, 3, 0x27, 0x00a0,
 	    MSDC0_DAT2, RES2, RES3, RES4,
 	    RES5, RES6, RES7),
-	PIN(165, EMMC_DAT1, 0, 0, 0x01, 0,
+	PIN(165, EMMC_DAT1, 1, 2, 0x27, 0x00a0,
 	    MSDC0_DAT1, RES2, RES3, RES4,
 	    RES5, RES6, RES7),
-	PIN(166, EMMC_DAT0, 0, 0, 0x01, 0,
+	PIN(166, EMMC_DAT0, 1, 0, 0x18, 0x0050,
 	    MSDC0_DAT0, RES2, RES3, RES4,
 	    RES5, RES6, RES7),
-	PIN(167, EMMC_DSL, 0, 0, 0x01, 0,
+	PIN(167, EMMC_DSL, 1, 7, 0x27, 0x00a0,
 	    MSDC0_DSL, RES2, RES3, RES4,
 	    RES5, RES6, RES7),
-	PIN(168, MSDC1_CMD, 0, 0, 0x01, 0,
+	PIN(168, MSDC1_CMD, 1, 1, 0x26, 0x0090,
 	    MSDC1_CMD, CONN_WF_MCU_AICE_TMSC, UCTS1, UDI_TMS,
 	    SSPM_JTAG_TMS_VCORE, MCUPM_JTAG_TMS, CONN_BGF_MCU_TMS),
-	PIN(169, MSDC1_CLK, 0, 0, 0x01, 0,
+	PIN(169, MSDC1_CLK, 1, 0, 0x26, 0x0090,
 	    MSDC1_CLK, CONN_WF_MCU_AICE_TCKC, URTS1, UDI_TCK,
 	    SSPM_JTAG_TCK_VCORE, MCUPM_JTAG_TCK, CONN_BGF_MCU_TCK),
-	PIN(170, MSDC1_DAT0, 0, 0, 0x01, 0,
+	PIN(170, MSDC1_DAT0, 1, 2, 0x26, 0x0090,
 	    MSDC1_DAT0, SPIM5_B_CSB, UCTS2, UDI_TDI,
 	    SSPM_JTAG_TDI_VCORE, MCUPM_JTAG_TDI, CONN_BGF_MCU_TDI),
-	PIN(171, MSDC1_DAT1, 0, 0, 0x01, 0,
+	PIN(171, MSDC1_DAT1, 1, 3, 0x26, 0x0090,
 	    MSDC1_DAT1, SPIM5_B_CLK, URTS2, UDI_TDO,
 	    SSPM_JTAG_TDO_VCORE, MCUPM_JTAG_TDO, CONN_BGF_MCU_TDO),
-	PIN(172, MSDC1_DAT2, 0, 0, 0x01, 0,
+	PIN(172, MSDC1_DAT2, 1, 4, 0x26, 0x0090,
 	    MSDC1_DAT2, SPIM5_B_MO, UCTS3, UDI_NTRST,
 	    SSPM_JTAG_TRSTN_VCORE, MCUPM_JTAG_TRSTN, CONN_BGF_MCU_TRST_B),
-	PIN(173, MSDC1_DAT3, 0, 0, 0x01, 0,
+	PIN(173, MSDC1_DAT3, 1, 5, 0x26, 0x0090,
 	    MSDC1_DAT3, SPIM5_B_MI, URTS3, CLKM0,
 	    PWM_2, RES6, RES7),
-	PIN(174, MSDC2_CMD, 0, 0, 0x01, 0,
+	PIN(174, MSDC2_CMD, 1, 1, 0x29, 0x0080,
 	    MSDC2_CMD, CONN_BGF_MCU_AICE_TMSC, UTXD1, VADSP_JTAG0_TMS,
 	    SSPM_JTAG_TMS_VLP, SPM_JTAG_TMS, SCP_JTAG0_TMS_VLP),
-	PIN(175, MSDC2_CLK, 0, 0, 0x01, 0,
+	PIN(175, MSDC2_CLK, 1, 0, 0x29, 0x0080,
 	    MSDC2_CLK, CONN_BGF_MCU_AICE_TCKC, URXD1, VADSP_JTAG0_TCK,
 	    SSPM_JTAG_TCK_VLP, SPM_JTAG_TCK, SCP_JTAG0_TCK_VLP),
-	PIN(176, MSDC2_DAT0, 0, 0, 0x01, 0,
+	PIN(176, MSDC2_DAT0, 1, 2, 0x29, 0x0080,
 	    MSDC2_DAT0, SRCLKENAI0, UTXD2, VADSP_JTAG0_TDI,
 	    SSPM_JTAG_TDI_VLP, SPM_JTAG_TDI, SCP_JTAG0_TDI_VLP),
-	PIN(177, MSDC2_DAT1, 0, 0, 0x01, 0,
+	PIN(177, MSDC2_DAT1, 1, 3, 0x29, 0x0080,
 	    MSDC2_DAT1, SRCLKENAI1, URXD2, VADSP_JTAG0_TDO,
 	    SSPM_JTAG_TDO_VLP, SPM_JTAG_TDO, SCP_JTAG0_TDO_VLP),
-	PIN(178, MSDC2_DAT2, 0, 0, 0x01, 0,
+	PIN(178, MSDC2_DAT2, 1, 4, 0x29, 0x0080,
 	    MSDC2_DAT2, RES2, UTXD3, VADSP_JTAG0_TRSTN,
 	    SSPM_JTAG_TRSTN_VLP, SPM_JTAG_TRSTN, SCP_JTAG0_TRSTN_VLP),
-	PIN(179, MSDC2_DAT3, 0, 0, 0x01, 0,
+	PIN(179, MSDC2_DAT3, 1, 5, 0x29, 0x0080,
 	    MSDC2_DAT3, RES2, URXD3, CLKM1,
 	    PWM_vlp, RES6, TP_GPIO7_AO),
-	PIN(180, SPMI_P_SCL, 0, 0, 0x01, 0,
+	PIN(180, SPMI_P_SCL, 0, 15, 0x27, 0x00b0,
 	    SPMI_P_SCL, RES2, RES3, RES4,
 	    RES5, RES6, RES7),
-	PIN(181, SPMI_P_SDA, 0, 0, 0x01, 0,
+	PIN(181, SPMI_P_SDA, 0, 16, 0x27, 0x00b0,
 	    SPMI_P_SDA, RES2, RES3, RES4,
 	    RES5, RES6, RES7),
-	PIN(182, EMI_RESETB, 0, 0, 0x01, 0,
+	PIN(182, EMI_RESETB, 0, 3, 0x29, 0x0090,
 	    DDR_PAD_RRESETB, RES2, RES3, RES4,
 	    RES5, RES6, RES7),
 };

From f83fb11e5fd07d5c310630fbc43a03f637fb0d51 Mon Sep 17 00:00:00 2001
From: Vince Liu <vince-wl.liu@mediatek.corp-partner.google.com>
Date: Wed, 11 Dec 2024 11:39:49 +0800
Subject: [PATCH 0893/3886] soc/mediatek/mt8189: Add CPU segment ID support

Some of MTK's ICs (such as the MT8189) use two eFuse registers to
record CPU ID information.

Users can use get_cpu_id and get_cpu_segment_id to obtain the SoC
version. For example, the CPU ID of the MT8189H is 0x81890000, and
the CPU segment ID is 0x21.

BUG=b:379008996
BRANCH=none
TEST=build pass

Signed-off-by: Vince Liu <vince-wl.liu@mediatek.corp-partner.google.com>
Change-Id: I535874025cde7f6f975246105e32e165083601e0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87509
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
---
 src/soc/mediatek/common/cpu_segment_id.c     | 15 +++++++++++++++
 src/soc/mediatek/common/include/soc/cpu_id.h |  4 ++++
 src/soc/mediatek/mt8189/include/soc/efuse.h  | 20 ++++++++++++++++++++
 3 files changed, 39 insertions(+)
 create mode 100644 src/soc/mediatek/common/cpu_segment_id.c
 create mode 100644 src/soc/mediatek/mt8189/include/soc/efuse.h

diff --git a/src/soc/mediatek/common/cpu_segment_id.c b/src/soc/mediatek/common/cpu_segment_id.c
new file mode 100644
index 0000000000..f7cdc8ad34
--- /dev/null
+++ b/src/soc/mediatek/common/cpu_segment_id.c
@@ -0,0 +1,15 @@
+/* SPDX-License-Identifier: GPL-2.0-only OR MIT */
+
+#include <console/console.h>
+#include <device/mmio.h>
+#include <soc/cpu_id.h>
+#include <soc/efuse.h>
+
+u32 get_cpu_segment_id(void)
+{
+	u32 id = read32(&mtk_efuse->cpu_seg_id_reg);
+
+	printk(BIOS_INFO, "CPU Segment ID: %#x\n", id);
+
+	return id;
+}
diff --git a/src/soc/mediatek/common/include/soc/cpu_id.h b/src/soc/mediatek/common/include/soc/cpu_id.h
index 9453a15864..173518fc42 100644
--- a/src/soc/mediatek/common/include/soc/cpu_id.h
+++ b/src/soc/mediatek/common/include/soc/cpu_id.h
@@ -5,7 +5,11 @@
 
 #define MTK_CPU_ID_MT8186G	0x81861001
 #define MTK_CPU_ID_MT8186T	0x81862001
+#define MTK_CPU_ID_MT8189	0x81890000
+#define MTK_CPU_SEG_ID_MT8189G	0x20
+#define MTK_CPU_SEG_ID_MT8189H	0x21
 
 u32 get_cpu_id(void);
+u32 get_cpu_segment_id(void);
 
 #endif /* SOC_MEDIATEK_COMMON_CPU_ID_H */
diff --git a/src/soc/mediatek/mt8189/include/soc/efuse.h b/src/soc/mediatek/mt8189/include/soc/efuse.h
new file mode 100644
index 0000000000..031dd5ef78
--- /dev/null
+++ b/src/soc/mediatek/mt8189/include/soc/efuse.h
@@ -0,0 +1,20 @@
+/* SPDX-License-Identifier: GPL-2.0-only OR MIT */
+
+#ifndef __SOC_MEDIATEK_MT8189_INCLUDE_SOC_EFUSE_H__
+#define __SOC_MEDIATEK_MT8189_INCLUDE_SOC_EFUSE_H__
+
+#include <soc/addressmap.h>
+#include <stdint.h>
+
+struct efuse_regs {
+	u32 reserved1[488];
+	u32 cpu_id_reg;
+	u32 reserved2[15];
+	u32 cpu_seg_id_reg;
+};
+check_member(efuse_regs, cpu_id_reg, 0x7A0);
+check_member(efuse_regs, cpu_seg_id_reg, 0x7E0);
+
+static struct efuse_regs *const mtk_efuse = (void *)EFUSEC_BASE;
+
+#endif /*__SOC_MEDIATEK_MT8189_INCLUDE_SOC_EFUSE_H__*/

From e99532d99b66e48099b2d55cf0763f9b110c6c41 Mon Sep 17 00:00:00 2001
From: Zhigang Qin <zhigang.qin@mediatek.corp-partner.google.com>
Date: Wed, 26 Mar 2025 21:11:03 +0800
Subject: [PATCH 0894/3886] soc/mediatek/common: Update SPMI calibration
 process

The original SPMI calibration process is only suitable for pre-MT8189
SoCs. Update the flow to also support MT8189.

BUG=b:379008996
BRANCH=none
TEST=build pass and driver log is normal:
[INFO ]  [Pass] dly:1, pol:0, sampl:0x2
[INFO ]  [Pass] dly:1, pol:0, sampl:0x2

Signed-off-by: Zhigang Qin <zhigang.qin@mediatek.corp-partner.google.com>
Change-Id: I636b3062fc25fc1d7d39e3426602e6434be4c26a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87508
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/soc/mediatek/common/pmif_spmi.c | 37 ++++++++++++++++-------------
 1 file changed, 20 insertions(+), 17 deletions(-)

diff --git a/src/soc/mediatek/common/pmif_spmi.c b/src/soc/mediatek/common/pmif_spmi.c
index 0de4df0fb1..e4c4e82daa 100644
--- a/src/soc/mediatek/common/pmif_spmi.c
+++ b/src/soc/mediatek/common/pmif_spmi.c
@@ -48,37 +48,40 @@ static int spmi_read_check(struct pmif *pmif_arb, int slvid)
 	return 0;
 }
 
-static int spmi_cali_rd_clock_polarity(struct pmif *pmif_arb, const struct spmi_device *dev)
+static int spmi_cali_rd_clock_polarity(struct pmif *pmif_arb)
 {
-	int i;
-	bool success = false;
+	int i, j;
 	const struct cali cali_data[] = {
+		{SPMI_CK_DLY_1T, SPMI_CK_POL_NEG},
 		{SPMI_CK_DLY_1T, SPMI_CK_POL_POS},
 		{SPMI_CK_NO_DLY, SPMI_CK_POL_POS},
 		{SPMI_CK_NO_DLY, SPMI_CK_POL_NEG},
-		{SPMI_CK_DLY_1T, SPMI_CK_POL_NEG},
 	};
 
 	/* Indicate sampling clock polarity, 1: Positive 0: Negative */
 	for (i = 0; i < ARRAY_SIZE(cali_data); i++) {
-		SET32_BITFIELDS(&mtk_spmi_mst->mst_sampl, SAMPL_CK_DLY, cali_data[i].dly,
-				SAMPL_CK_POL, cali_data[i].pol);
-		if (spmi_read_check(pmif_arb, dev->slvid) == 0) {
-			success = true;
-			break;
+		bool success = true;
+		SET32_BITFIELDS(&mtk_spmi_mst->mst_sampl, SAMPL_CK_DLY,
+				cali_data[i].dly, SAMPL_CK_POL, cali_data[i].pol);
+		for (j = 0; j < spmi_dev_cnt; j++) {
+			if (spmi_read_check(pmif_arb, spmi_dev[j].slvid) != 0) {
+				success = false;
+				break;
+			}
+		}
+		if (success) {
+			printk(BIOS_INFO, "calibration success for spmi clk: "
+			       "cali_data[%d] dly = %u, pol = %u\n",
+			       i, cali_data[i].dly, cali_data[i].pol);
+			return 0;
 		}
 	}
 
-	if (!success)
-		die("ERROR - calibration fail for spmi clk");
-
-	return 0;
+	return -E_NODEV;
 }
 
 static int spmi_mst_init(struct pmif *pmif_arb)
 {
-	size_t i;
-
 	if (!pmif_arb) {
 		printk(BIOS_ERR, "%s: null pointer for pmif dev.\n", __func__);
 		return -E_INVAL;
@@ -88,8 +91,8 @@ static int spmi_mst_init(struct pmif *pmif_arb)
 		pmif_spmi_iocfg();
 	spmi_config_master();
 
-	for (i = 0; i < spmi_dev_cnt; i++)
-		spmi_cali_rd_clock_polarity(pmif_arb, &spmi_dev[i]);
+	if (spmi_cali_rd_clock_polarity(pmif_arb) != 0)
+		die("ERROR - calibration fail for spmi clk");
 
 	return 0;
 }

From cf5696834b0aa1f1c274246b99a2e835a5182852 Mon Sep 17 00:00:00 2001
From: Appukuttan V K <appukuttan.vk@intel.com>
Date: Fri, 2 May 2025 10:40:03 +0530
Subject: [PATCH 0895/3886] soc/intel/ptl: Refactor Panther Lake SoC
 configuration

This commit refactors the configuration options for Intel
Panther Lake SoC variants to improve clarity and maintainability.

Key changes:
  - Introduce a new SOC_INTEL_PANTHERLAKE configuration option to
    serve as a base selection for all Panther Lake SoC variants.
  - Update SOC_INTEL_PANTHERLAKE_U_H and SOC_INTEL_PANTHERLAKE_H to
    select SOC_INTEL_PANTHERLAKE instead of
    SOC_INTEL_PANTHERLAKE_BASE.
  - Update existing code to utilize the new SOC_INTEL_PANTHERLAKE
    guard where Panther Lake variant guards are applied.

BUG=b:394208231
TEST=Build Ocelot and Fatcat and verify it compiles without any error.

Change-Id: I656006dab6f08c9a16996ad194fa0b5b751f91aa
Signed-off-by: Appukuttan V K <appukuttan.vk@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87511
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Usha P <usha.p@intel.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/soc/intel/pantherlake/Kconfig                     | 10 ++++++++--
 src/soc/intel/pantherlake/acpi/gpio.asl               |  2 +-
 src/soc/intel/pantherlake/include/soc/gpio_soc_defs.h |  2 +-
 src/soc/intel/pantherlake/retimer.c                   |  2 ++
 4 files changed, 12 insertions(+), 4 deletions(-)

diff --git a/src/soc/intel/pantherlake/Kconfig b/src/soc/intel/pantherlake/Kconfig
index beda98acbe..23eaaa61ed 100644
--- a/src/soc/intel/pantherlake/Kconfig
+++ b/src/soc/intel/pantherlake/Kconfig
@@ -111,9 +111,15 @@ config SOC_INTEL_PANTHERLAKE_BASE
 	  type using the `SOC_INTEL_PANTHERLAKE_*` options instead
 	  of selecting this option directly.
 
-config SOC_INTEL_PANTHERLAKE_U_H
+config SOC_INTEL_PANTHERLAKE
 	bool
 	select SOC_INTEL_PANTHERLAKE_BASE
+	help
+	  Intel Pantherlake SoC. This should be selected by all Pantherlake SoC variants.
+
+config SOC_INTEL_PANTHERLAKE_U_H
+	bool
+	select SOC_INTEL_PANTHERLAKE
 	help
 	  Choose this option if the mainboard is built using either a PTL-U (15W) or
 	  PTL-H 12Xe (25W) system-on-a-chip SoC.
@@ -121,7 +127,7 @@ config SOC_INTEL_PANTHERLAKE_U_H
 config SOC_INTEL_PANTHERLAKE_H
 	bool
 	depends on !SOC_INTEL_PANTHERLAKE_U_H
-	select SOC_INTEL_PANTHERLAKE_BASE
+	select SOC_INTEL_PANTHERLAKE
 	help
 	  Choose this option if the mainboard is built using PTL-H 4Xe system-on-a-chip (SoC).
 
diff --git a/src/soc/intel/pantherlake/acpi/gpio.asl b/src/soc/intel/pantherlake/acpi/gpio.asl
index 18df92dd38..5aea294e61 100644
--- a/src/soc/intel/pantherlake/acpi/gpio.asl
+++ b/src/soc/intel/pantherlake/acpi/gpio.asl
@@ -556,7 +556,7 @@ Device (GPI3)
 		}
 #endif
 	})
-#if (CONFIG(SOC_INTEL_PANTHERLAKE_U_H) || CONFIG(SOC_INTEL_PANTHERLAKE_H))
+#if CONFIG(SOC_INTEL_PANTHERLAKE)
 	/* first bank/group in community 3: RSVD */
 	Name (RSVD, Package (0x02)
 	{
diff --git a/src/soc/intel/pantherlake/include/soc/gpio_soc_defs.h b/src/soc/intel/pantherlake/include/soc/gpio_soc_defs.h
index fd44d837ce..352df92b6e 100644
--- a/src/soc/intel/pantherlake/include/soc/gpio_soc_defs.h
+++ b/src/soc/intel/pantherlake/include/soc/gpio_soc_defs.h
@@ -254,7 +254,7 @@
  * +----------------------------+
  */
 
-#if (!CONFIG(SOC_INTEL_WILDCATLAKE))
+#if CONFIG(SOC_INTEL_PANTHERLAKE)
 /*
  * +----------------------------+
  * |        Group CPUJTAG       |
diff --git a/src/soc/intel/pantherlake/retimer.c b/src/soc/intel/pantherlake/retimer.c
index 329d9b2ad3..04144f655b 100644
--- a/src/soc/intel/pantherlake/retimer.c
+++ b/src/soc/intel/pantherlake/retimer.c
@@ -11,8 +11,10 @@ int retimer_get_index_for_typec(uint8_t typec_port)
 	const struct device *tcss_port_arr[] = {
 		DEV_PTR(tcss_usb3_port0),
 		DEV_PTR(tcss_usb3_port1),
+#if CONFIG(SOC_INTEL_PANTHERLAKE)
 		DEV_PTR(tcss_usb3_port2),
 		DEV_PTR(tcss_usb3_port3),
+#endif
 	};
 
 	for (int i = 0, ec_port = 0; i < MAX_TYPE_C_PORTS; i++) {

From 30a4fec86e5a3109e6312c7602a338a0c771b323 Mon Sep 17 00:00:00 2001
From: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Date: Tue, 29 Apr 2025 11:03:26 +0800
Subject: [PATCH 0896/3886] mb/google/fatcat/var/kinmen: Generate SPD ID for
 Micron modules

Add 2 Micron memory parts in mem_parts_used.txt, and generate
SPD id for these parts.

1. MT62F1G32D2DS-023 WT:C (Micron)
2. MT62F2G32D4DS-020 WT:F (Micron)

BUG=b:409148565
TEST=Run part_id_gen tool and check the generated files.

Change-Id: Ib975e31734369a8f8bd410063cc2d236a6d4cc66
Signed-off-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87534
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
---
 src/mainboard/google/fatcat/variants/kinmen/memory/Makefile.mk  | 2 ++
 .../google/fatcat/variants/kinmen/memory/dram_id.generated.txt  | 2 ++
 .../google/fatcat/variants/kinmen/memory/mem_parts_used.txt     | 2 ++
 3 files changed, 6 insertions(+)

diff --git a/src/mainboard/google/fatcat/variants/kinmen/memory/Makefile.mk b/src/mainboard/google/fatcat/variants/kinmen/memory/Makefile.mk
index 8fccc97b68..bc3362d843 100644
--- a/src/mainboard/google/fatcat/variants/kinmen/memory/Makefile.mk
+++ b/src/mainboard/google/fatcat/variants/kinmen/memory/Makefile.mk
@@ -5,3 +5,5 @@
 
 SPD_SOURCES =
 SPD_SOURCES += spd/lp5/set-0/spd-7.hex      # ID = 0(0b0000)  Parts = H58G56BK7BX068
+SPD_SOURCES += spd/lp5/set-0/spd-11.hex      # ID = 1(0b0001)  Parts = MT62F1G32D2DS-023 WT:C
+SPD_SOURCES += spd/lp5/set-0/spd-10.hex      # ID = 2(0b0010)  Parts = MT62F2G32D4DS-020 WT:F
diff --git a/src/mainboard/google/fatcat/variants/kinmen/memory/dram_id.generated.txt b/src/mainboard/google/fatcat/variants/kinmen/memory/dram_id.generated.txt
index 15fcc5cf14..8cfde18141 100644
--- a/src/mainboard/google/fatcat/variants/kinmen/memory/dram_id.generated.txt
+++ b/src/mainboard/google/fatcat/variants/kinmen/memory/dram_id.generated.txt
@@ -5,3 +5,5 @@
 
 DRAM Part Name                 ID to assign
 H58G56BK7BX068                 0 (0000)
+MT62F1G32D2DS-023 WT:C         1 (0001)
+MT62F2G32D4DS-020 WT:F         2 (0010)
diff --git a/src/mainboard/google/fatcat/variants/kinmen/memory/mem_parts_used.txt b/src/mainboard/google/fatcat/variants/kinmen/memory/mem_parts_used.txt
index 17ee7efc60..5ab8b585a3 100644
--- a/src/mainboard/google/fatcat/variants/kinmen/memory/mem_parts_used.txt
+++ b/src/mainboard/google/fatcat/variants/kinmen/memory/mem_parts_used.txt
@@ -10,3 +10,5 @@
 
 # Part Name
 H58G56BK7BX068
+MT62F1G32D2DS-023 WT:C
+MT62F2G32D4DS-020 WT:F

From 33b3269d91e9c810f2a905a549a2c6074e19d3b5 Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Fri, 2 May 2025 10:34:01 -0500
Subject: [PATCH 0897/3886] soc/intel/cmn/cse: Add function to check if ME
 state is M3_NO_UMA
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

When soft-disabled, boards which select SOC_INTEL_CSE_LITE_SKU boot
with their working state having a value of M3_NO_UMA (0x4), as
opposed to the "normal" value of M0_NO_UMA (0x5). Add a define for
this value (taken from older ME code in coreboot) and add a function
to check if the CSE is in that state, which will be used in a
subsequent commit.

TEST=tested with rest of patch train

Change-Id: I405987ece00b3849a9fcdf1bfc8b377fd8d010dc
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87516
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
---
 src/soc/intel/common/block/cse/cse.c                 | 7 +++++++
 src/soc/intel/common/block/include/intelblocks/cse.h | 7 +++++++
 2 files changed, 14 insertions(+)

diff --git a/src/soc/intel/common/block/cse/cse.c b/src/soc/intel/common/block/cse/cse.c
index 29a0c2192b..ef1105cfdf 100644
--- a/src/soc/intel/common/block/cse/cse.c
+++ b/src/soc/intel/common/block/cse/cse.c
@@ -268,6 +268,13 @@ bool cse_is_hfs1_cws_normal(void)
 	return false;
 }
 
+bool cse_is_hfs1_cws_m3_no_uma(void)
+{
+	union me_hfsts1 hfs1;
+	hfs1.data = me_read_config32(PCI_ME_HFSTS1);
+	return hfs1.fields.working_state == ME_HFS1_CWS_M3_NO_UMA;
+}
+
 bool cse_is_hfs1_com_normal(void)
 {
 	return cse_check_hfs1_com(ME_HFS1_COM_NORMAL);
diff --git a/src/soc/intel/common/block/include/intelblocks/cse.h b/src/soc/intel/common/block/include/intelblocks/cse.h
index 99dd7d5e17..ac3f2cdcf9 100644
--- a/src/soc/intel/common/block/include/intelblocks/cse.h
+++ b/src/soc/intel/common/block/include/intelblocks/cse.h
@@ -57,6 +57,7 @@ enum mkhi_group_id {
 #define MKHI_BUP_COMMON_GET_BOOT_PERF_DATA	0x8
 
 /* ME Current Working States */
+#define ME_HFS1_CWS_M3_NO_UMA	0x4
 #define ME_HFS1_CWS_NORMAL	0x5
 
 /* ME Current Operation Modes */
@@ -453,6 +454,12 @@ void print_me_fw_version(void *unused);
  */
 bool cse_is_hfs1_cws_normal(void);
 
+/*
+ * Checks current working operation state is M3_NO_UMA or not.
+ * Returns true if CSE's current working state is M3_NO_UMA, otherwise false.
+ */
+bool cse_is_hfs1_cws_m3_no_uma(void);
+
 /*
  * Checks CSE's current operation mode is normal or not.
  * Returns true if CSE's current operation mode is normal, otherwise false.

From 4d7b56cdaabd6510abda45edae5f226442903729 Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Fri, 2 May 2025 10:43:57 -0500
Subject: [PATCH 0898/3886] soc/intel/cmn/cse_lite: Fix handling of soft
 disable state
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

When soft-disabled, boards selecting SOC_INTEL_CSE_LITE_SKU boot up
with a working state of M3_NO_UMA vs NORMAL, so handle this condition.
Without this, when vboot is not used, the board will simply fail to
boot as vboot_recovery_mode does not exist:

[ERROR]  cse_lite: CSE does not meet prerequisites
[ERROR]  cse_lite: Failed to get CSE boot partition info
[DEBUG]  cse: CSE status registers: HFSTS1: 0x80032044,
              HFSTS2: 0x32280126 HFSTS3: 0x50
[EMERG]  cse: Failed to trigger recovery mode(recovery subcode:6)

This commit addresses the first error (does not meet prerequisites),
which allows CSE sync to continue and boot the RW partition in
the soft-disabled state. It also allows the CSE to properly transition
back into the normal working state (when that option is selected via
CMOS or CFR).

TEST=build/boot google/wyvern, verify able to disable/enable the ME
properly via CFR option.

Change-Id: I46da5ac248e267acee958d66ebbd97d945e722b9
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87517
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
---
 src/soc/intel/common/block/cse/cse_lite.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/src/soc/intel/common/block/cse/cse_lite.c b/src/soc/intel/common/block/cse/cse_lite.c
index 5647a36b32..e4923ca376 100644
--- a/src/soc/intel/common/block/cse/cse_lite.c
+++ b/src/soc/intel/common/block/cse/cse_lite.c
@@ -267,6 +267,7 @@ static void cse_print_boot_partition_info(void)
  *	- When CSE boots from RW partition (COM: Normal and CWS: Normal)
  *	- When CSE boots from RO partition (COM: Soft Temp Disable and CWS: Normal)
  *	- After HMRFPO_ENABLE command is issued to CSE (COM: SECOVER_MEI_MSG and CWS: Normal)
+ *	- When CSE boots from RW partition (COM: Soft Temp Disable and CWS: M3 w/o UMA)
  * The prerequisite check should be handled in cse_get_bp_info() and
  * cse_set_next_boot_partition() since the CSE's current operation mode is changed between these
  * cmd handler calls.
@@ -280,6 +281,8 @@ static bool cse_is_bp_cmd_info_possible(void)
 			return true;
 		if (cse_is_hfs1_com_soft_temp_disable())
 			return true;
+	} else if (cse_is_hfs1_cws_m3_no_uma() && cse_is_hfs1_com_soft_temp_disable()) {
+		return true;
 	}
 	return false;
 }

From d2b0220a380c84140df339d8d72b2c85a240b87a Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Wed, 30 Apr 2025 16:51:01 -0500
Subject: [PATCH 0899/3886] allocator_v4: Re-enable top-down allocation for
 edk2

Commit a959f0ad7620 ("allocator_v4: Disable top-down allocation for
EDK2") disabled top-down allocation for edk2 due to a bug which broke
display init with Intel IGD. A workaround has been implemented in
MrChromebox's fork (and others) while the issue is being resolved
upstream, so re-enable top-down allocation unless upstream edk2
is being used.

TEST=build/boot various Google mainboards with edk2 payload selected.

Change-Id: I0e9b0d02bbf30878aef37a97d6a743a402700fc7
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87504
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
---
 src/device/Kconfig | 8 +++++---
 1 file changed, 5 insertions(+), 3 deletions(-)

diff --git a/src/device/Kconfig b/src/device/Kconfig
index bfb38b442f..e1a8d38ea3 100644
--- a/src/device/Kconfig
+++ b/src/device/Kconfig
@@ -994,14 +994,16 @@ config I2C_TRANSFER_TIMEOUT_US
 
 config RESOURCE_ALLOCATION_TOP_DOWN
 	bool "Allocate resources from top down"
-	default n if PAYLOAD_EDK2
+	default n if PAYLOAD_EDK2 && EDK2_REPO_OFFICIAL
 	default y
 	help
 	  Top-down allocation is required to place resources above 4G by
 	  default (i.e. even when there is still space below). On some
 	  platforms, it might make a difference because of conflicts with
-	  undeclared resources. EDK2 is currently reported to also have
-	  problems on some platforms, at least with Intel's IGD.
+	  undeclared resources.
+
+	  Upstream EDK2 is currently reported to also have problems on some
+	  platforms at least with Intel's IGD; MrChromebox's fork works fine.
 
 config ALWAYS_ALLOW_ABOVE_4G_ALLOCATION
 	bool

From 8fa84d9111ce6e1152cd0710a7c62bb93dbfe1cb Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Wed, 16 Apr 2025 09:17:24 -0500
Subject: [PATCH 0900/3886] mb/starlabs/*: Add CFR entry for Bluetooth RTD3

Allows the Bluetooth RTD3 feature to be toggled on/off.

On some devices, enabling Bluetooth RTD3 causes the BT device to
continually disconnect/reconnect under Windows, so having the ability
to disable it in those cases is useful.

Change-Id: I1730dc35d56919fcf03acdf577288caf1e1a4ee3
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87492
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
---
 src/mainboard/starlabs/byte_adl/cfr.c     | 9 +++++++++
 src/mainboard/starlabs/starbook/cfr.c     | 1 +
 src/mainboard/starlabs/starbook/cfr.h     | 8 ++++++++
 src/mainboard/starlabs/starfighter/cfr.c  | 9 +++++++++
 src/mainboard/starlabs/starlite_adl/cfr.c | 9 +++++++++
 5 files changed, 36 insertions(+)

diff --git a/src/mainboard/starlabs/byte_adl/cfr.c b/src/mainboard/starlabs/byte_adl/cfr.c
index 442326f41c..e360e3b419 100644
--- a/src/mainboard/starlabs/byte_adl/cfr.c
+++ b/src/mainboard/starlabs/byte_adl/cfr.c
@@ -136,9 +136,18 @@ static const struct sm_object vtd = SM_DECLARE_BOOL({
 	.default_value	= true,
 });
 
+static const struct sm_object bluetooth_rtd3 = SM_DECLARE_BOOL({
+	.opt_name	= "bluetooth_rtd3",
+	.ui_name	= "Bluetooth Runtime-D3",
+	.ui_helptext	= "Enable or disable Bluetooth power optimization.\n"
+			  "Recommended to disable when booting Windows.",
+	.default_value	= true,
+});
+
 static struct sm_obj_form performance = {
 	.ui_name = "Performance",
 	.obj_list = (const struct sm_object *[]) {
+		&bluetooth_rtd3,
 		&power_profile,
 		NULL
 	},
diff --git a/src/mainboard/starlabs/starbook/cfr.c b/src/mainboard/starlabs/starbook/cfr.c
index 92416b91de..5fed679631 100644
--- a/src/mainboard/starlabs/starbook/cfr.c
+++ b/src/mainboard/starlabs/starbook/cfr.c
@@ -12,6 +12,7 @@
 static struct sm_obj_form performance = {
 	.ui_name = "Performance",
 	.obj_list = (const struct sm_object *[]) {
+		&bluetooth_rtd3,
 		&fan_mode,
 		&power_profile,
 		NULL
diff --git a/src/mainboard/starlabs/starbook/cfr.h b/src/mainboard/starlabs/starbook/cfr.h
index 4ddf363573..554062aeeb 100644
--- a/src/mainboard/starlabs/starbook/cfr.h
+++ b/src/mainboard/starlabs/starbook/cfr.h
@@ -201,4 +201,12 @@ static const struct sm_object vtd = SM_DECLARE_BOOL({
 	.default_value	= true,
 });
 
+static const struct sm_object bluetooth_rtd3 = SM_DECLARE_BOOL({
+	.opt_name	= "bluetooth_rtd3",
+	.ui_name	= "Bluetooth Runtime-D3",
+	.ui_helptext	= "Enable or disable Bluetooth power optimization.\n"
+			  "Recommended to disable when booting Windows.",
+	.default_value	= true,
+});
+
 #endif /* _STARBOOK_CFR_H_ */
diff --git a/src/mainboard/starlabs/starfighter/cfr.c b/src/mainboard/starlabs/starfighter/cfr.c
index 7e040cce31..e8522f10eb 100644
--- a/src/mainboard/starlabs/starfighter/cfr.c
+++ b/src/mainboard/starlabs/starfighter/cfr.c
@@ -157,9 +157,18 @@ static const struct sm_object vtd = SM_DECLARE_BOOL({
 	.default_value	= true,
 });
 
+static const struct sm_object bluetooth_rtd3 = SM_DECLARE_BOOL({
+	.opt_name	= "bluetooth_rtd3",
+	.ui_name	= "Bluetooth Runtime-D3",
+	.ui_helptext	= "Enable or disable Bluetooth power optimization.\n"
+			  "Recommended to disable when booting Windows.",
+	.default_value	= true,
+});
+
 static struct sm_obj_form performance = {
 	.ui_name = "Performance",
 	.obj_list = (const struct sm_object *[]) {
+		&bluetooth_rtd3,
 		&fan_mode,
 		&power_profile,
 		NULL
diff --git a/src/mainboard/starlabs/starlite_adl/cfr.c b/src/mainboard/starlabs/starlite_adl/cfr.c
index a00a7a7f4a..3292835c08 100644
--- a/src/mainboard/starlabs/starlite_adl/cfr.c
+++ b/src/mainboard/starlabs/starlite_adl/cfr.c
@@ -189,9 +189,18 @@ static const struct sm_object vtd = SM_DECLARE_BOOL({
 	.default_value	= true,
 });
 
+static const struct sm_object bluetooth_rtd3 = SM_DECLARE_BOOL({
+	.opt_name	= "bluetooth_rtd3",
+	.ui_name	= "Bluetooth Runtime-D3",
+	.ui_helptext	= "Enable or disable Bluetooth power optimization.\n"
+			  "Recommended to disable when booting Windows.",
+	.default_value	= true,
+});
+
 static struct sm_obj_form performance = {
 	.ui_name = "Performance",
 	.obj_list = (const struct sm_object *[]) {
+		&bluetooth_rtd3,
 		&memory_speed,
 		&power_profile,
 		NULL

From d13afbbbca6cecf5288314bb8d1f2e823247e6ac Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Thu, 17 Apr 2025 12:15:05 -0500
Subject: [PATCH 0901/3886] mb/starlabs/starbook: Add CFR option to use native
 panel resolution

For boards for which set the 'Fixed Mode at boot' flag in the VBT, add
a CFR option to boot using the native panel resolution, rather than
a fixed/scaled video mode. This option selects between two VBT files:
one with the 'fixed mode' flag enabled, and one with it disabled.

This feature is mainly a workaround to a GNOME-related bug which
causes the creation of a 2nd display at the boot resolution. This
2nd display being a lower/different resolution than the native
panel resolution causes severe flickering/artifacting rendering
the display unusable unless this 2nd phantom display is disabled
on every boot

Change-Id: Ia75727f393744caf9062763e6118c1e2601512fa
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87493
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
---
 src/mainboard/starlabs/starbook/Kconfig          |   5 +++++
 src/mainboard/starlabs/starbook/cfr.c            |   3 +++
 src/mainboard/starlabs/starbook/cfr.h            |   8 ++++++++
 src/mainboard/starlabs/starbook/mainboard.c      |   9 +++++++++
 .../starlabs/starbook/variants/adl_n/Makefile.mk |   2 ++
 .../starbook/variants/adl_n/data_native_res.vbt  | Bin 0 -> 9216 bytes
 .../starlabs/starbook/variants/mtl/Makefile.mk   |   2 ++
 .../starbook/variants/mtl/data_native_res.vbt    | Bin 0 -> 7680 bytes
 8 files changed, 29 insertions(+)
 create mode 100644 src/mainboard/starlabs/starbook/variants/adl_n/data_native_res.vbt
 create mode 100644 src/mainboard/starlabs/starbook/variants/mtl/data_native_res.vbt

diff --git a/src/mainboard/starlabs/starbook/Kconfig b/src/mainboard/starlabs/starbook/Kconfig
index b266ba60c7..be0ed13177 100644
--- a/src/mainboard/starlabs/starbook/Kconfig
+++ b/src/mainboard/starlabs/starbook/Kconfig
@@ -264,4 +264,9 @@ config BOARD_SUPPORTS_HOTPLUG
 	default y if BOARD_STARLABS_STARBOOK_ADL
 	default n
 
+config BOARD_USES_FIXED_MODE_VBT
+	bool
+	default y if BOARD_STARLABS_STARBOOK_ADL_N || BOARD_STARLABS_STARBOOK_MTL
+	default n
+
 endif
diff --git a/src/mainboard/starlabs/starbook/cfr.c b/src/mainboard/starlabs/starbook/cfr.c
index 5fed679631..5acb1a2d8d 100644
--- a/src/mainboard/starlabs/starbook/cfr.c
+++ b/src/mainboard/starlabs/starbook/cfr.c
@@ -57,6 +57,9 @@ static struct sm_obj_form devices = {
 	.ui_name = "Devices",
 	.obj_list = (const struct sm_object *[]) {
 		&card_reader,
+		#if CONFIG(BOARD_USES_FIXED_MODE_VBT)
+		&display_native_res,
+		#endif
 		#if CONFIG(BOARD_HAS_FPR)
 		&fingerprint_reader,
 		#endif
diff --git a/src/mainboard/starlabs/starbook/cfr.h b/src/mainboard/starlabs/starbook/cfr.h
index 554062aeeb..6270e7a50f 100644
--- a/src/mainboard/starlabs/starbook/cfr.h
+++ b/src/mainboard/starlabs/starbook/cfr.h
@@ -209,4 +209,12 @@ static const struct sm_object bluetooth_rtd3 = SM_DECLARE_BOOL({
 	.default_value	= true,
 });
 
+static const struct sm_object display_native_res = SM_DECLARE_BOOL({
+	.opt_name	= "display_native_res",
+	.ui_name	= "Display: Use Native Resolution",
+	.ui_helptext	= "Enabled: use the native panel resolution at boot.\n"
+			  "Disabled: use a fixed/scaled video mode at boot.",
+	.default_value	= false,
+});
+
 #endif /* _STARBOOK_CFR_H_ */
diff --git a/src/mainboard/starlabs/starbook/mainboard.c b/src/mainboard/starlabs/starbook/mainboard.c
index d394f2579d..4141475a5d 100644
--- a/src/mainboard/starlabs/starbook/mainboard.c
+++ b/src/mainboard/starlabs/starbook/mainboard.c
@@ -1,6 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
 #include <device/device.h>
+#include <drivers/intel/gma/opregion.h>
 #include <soc/ramstage.h>
 #include <option.h>
 #include <variants.h>
@@ -25,3 +26,11 @@ static void init_mainboard(void *chip_info)
 struct chip_operations mainboard_ops = {
 	.init = init_mainboard,
 };
+
+const char *mainboard_vbt_filename(void)
+{
+	if (CONFIG(BOARD_USES_FIXED_MODE_VBT) && get_uint_option("display_native_res", 0) == 1)
+		return "vbt_native_res.bin";
+
+	return "vbt.bin";
+}
diff --git a/src/mainboard/starlabs/starbook/variants/adl_n/Makefile.mk b/src/mainboard/starlabs/starbook/variants/adl_n/Makefile.mk
index 9abc069b38..bfea7ef255 100644
--- a/src/mainboard/starlabs/starbook/variants/adl_n/Makefile.mk
+++ b/src/mainboard/starlabs/starbook/variants/adl_n/Makefile.mk
@@ -8,3 +8,5 @@ ramstage-y += devtree.c
 ramstage-y += gpio.c
 ramstage-y += hda_verb.c
 ramstage-y += ramstage.c
+
+$(call add_vbt_to_cbfs, vbt_native_res.bin, data_native_res.vbt)
diff --git a/src/mainboard/starlabs/starbook/variants/adl_n/data_native_res.vbt b/src/mainboard/starlabs/starbook/variants/adl_n/data_native_res.vbt
new file mode 100644
index 0000000000000000000000000000000000000000..d4b86ca2169d2f724e70f3fdb3dfdc7e784700f1
GIT binary patch
literal 9216
zcmeHMU2Gdg5T3oWFRpQjOG4|0Hf)kAbwZPzoi?PArJR2f>NY>NlSZzJ6gRb@5pHAB
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literal 0
HcmV?d00001

diff --git a/src/mainboard/starlabs/starbook/variants/mtl/Makefile.mk b/src/mainboard/starlabs/starbook/variants/mtl/Makefile.mk
index 2a505c35c7..53efc2f0fe 100644
--- a/src/mainboard/starlabs/starbook/variants/mtl/Makefile.mk
+++ b/src/mainboard/starlabs/starbook/variants/mtl/Makefile.mk
@@ -7,3 +7,5 @@ romstage-y += romstage.c
 ramstage-y += devtree.c
 ramstage-y += gpio.c
 ramstage-y += hda_verb.c
+
+$(call add_vbt_to_cbfs, vbt_native_res.bin, data_native_res.vbt)
diff --git a/src/mainboard/starlabs/starbook/variants/mtl/data_native_res.vbt b/src/mainboard/starlabs/starbook/variants/mtl/data_native_res.vbt
new file mode 100644
index 0000000000000000000000000000000000000000..228f85636c4363007d73c609814be32874765ef3
GIT binary patch
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literal 0
HcmV?d00001


From 3593314cf5faea25700df5f2b05429340cb9796a Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Thu, 17 Apr 2025 11:41:10 -0500
Subject: [PATCH 0902/3886] mb/starlabs/starlite_adl: Add CFR option to use
 native panel resolution

Add a CFR option to boot using the native panel resolution, rather than
a fixed/scaled video mode. This option selects between two VBT files:
one with the 'fixed mode' flag enabled, and one with it disabled.

This feature is mainly a workaround to a GNOME-related bug which
causes the creation of a 2nd display at the boot resolution. This
2nd display being a lower/different resolution than the native
panel resolution causes severe flickering/artifacting rendering
the display unusable unless this 2nd phantom display is disabled
on every boot.

Change-Id: I275b5f8455fed58c0167e3a69db27bbc21577db0
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87494
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
---
 src/mainboard/starlabs/starlite_adl/cfr.c        |   9 +++++++++
 .../starlite_adl/variants/mk_v/Makefile.mk       |   2 ++
 .../variants/mk_v/data_native_res.vbt            | Bin 0 -> 9216 bytes
 .../starlite_adl/variants/mk_v/ramstage.c        |  10 ++++++++++
 4 files changed, 21 insertions(+)
 create mode 100644 src/mainboard/starlabs/starlite_adl/variants/mk_v/data_native_res.vbt

diff --git a/src/mainboard/starlabs/starlite_adl/cfr.c b/src/mainboard/starlabs/starlite_adl/cfr.c
index 3292835c08..cd58641e1a 100644
--- a/src/mainboard/starlabs/starlite_adl/cfr.c
+++ b/src/mainboard/starlabs/starlite_adl/cfr.c
@@ -197,6 +197,14 @@ static const struct sm_object bluetooth_rtd3 = SM_DECLARE_BOOL({
 	.default_value	= true,
 });
 
+static const struct sm_object display_native_res = SM_DECLARE_BOOL({
+	.opt_name	= "display_native_res",
+	.ui_name	= "Display: Use Native Resolution",
+	.ui_helptext	= "Enabled: use the native panel resolution at boot.\n"
+			  "Disabled: use a fixed/scaled video mode at boot.",
+	.default_value	= false,
+});
+
 static struct sm_obj_form performance = {
 	.ui_name = "Performance",
 	.obj_list = (const struct sm_object *[]) {
@@ -234,6 +242,7 @@ static struct sm_obj_form devices = {
 	.ui_name = "Devices",
 	.obj_list = (const struct sm_object *[]) {
 		&accelerometer,
+		&display_native_res,
 		#if CONFIG(SOC_INTEL_TIGERLAKE) || CONFIG(SOC_INTEL_ALDERLAKE) || CONFIG(SOC_INTEL_RAPTORLAKE)
 		&gna,
 		#endif
diff --git a/src/mainboard/starlabs/starlite_adl/variants/mk_v/Makefile.mk b/src/mainboard/starlabs/starlite_adl/variants/mk_v/Makefile.mk
index 9abc069b38..bfea7ef255 100644
--- a/src/mainboard/starlabs/starlite_adl/variants/mk_v/Makefile.mk
+++ b/src/mainboard/starlabs/starlite_adl/variants/mk_v/Makefile.mk
@@ -8,3 +8,5 @@ ramstage-y += devtree.c
 ramstage-y += gpio.c
 ramstage-y += hda_verb.c
 ramstage-y += ramstage.c
+
+$(call add_vbt_to_cbfs, vbt_native_res.bin, data_native_res.vbt)
diff --git a/src/mainboard/starlabs/starlite_adl/variants/mk_v/data_native_res.vbt b/src/mainboard/starlabs/starlite_adl/variants/mk_v/data_native_res.vbt
new file mode 100644
index 0000000000000000000000000000000000000000..556fa45c615329baa9a00e20c58f7318887d2ef7
GIT binary patch
literal 9216
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literal 0
HcmV?d00001

diff --git a/src/mainboard/starlabs/starlite_adl/variants/mk_v/ramstage.c b/src/mainboard/starlabs/starlite_adl/variants/mk_v/ramstage.c
index c6c16c0a37..140101fb14 100644
--- a/src/mainboard/starlabs/starlite_adl/variants/mk_v/ramstage.c
+++ b/src/mainboard/starlabs/starlite_adl/variants/mk_v/ramstage.c
@@ -1,6 +1,8 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
+#include <drivers/intel/gma/opregion.h>
 #include <soc/ramstage.h>
+#include <option.h>
 
 void mainboard_silicon_init_params(FSP_S_CONFIG *supd)
 {
@@ -13,3 +15,11 @@ void mainboard_silicon_init_params(FSP_S_CONFIG *supd)
 	supd->PchSerialIoI2cSdaPinMux[0]	= 0x1947c404;	// GPP_H4
 	supd->PchSerialIoI2cSclPinMux[0]	= 0x1947a405;	// GPP_H5
 }
+
+const char *mainboard_vbt_filename(void)
+{
+	if (get_uint_option("display_native_res", 0) == 1)
+		return "vbt_native_res.bin";
+
+	return "vbt.bin";
+}

From f1509a467ce317f10a453956930f503a5f49ca9b Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Thu, 17 Apr 2025 22:31:34 -0500
Subject: [PATCH 0903/3886] mb/starlabs/starfighter: Add CFR option to use
 native panel resolution

Add a CFR option to boot using the native panel resolution, rather than
a fixed/scaled video mode. This option selects between two VBT files:
one with the 'fixed mode' flag enabled, and one with it disabled.

This feature is mainly a workaround to a GNOME-related bug which
causes the creation of a 2nd display at the boot resolution. This
2nd display being a lower/different resolution than the native
panel resolution causes severe flickering/artifacting rendering
the display unusable unless this 2nd phantom display is disabled
on every boot.

Change-Id: I9e39258ce0171aab425150679d1ce30d69b2b1ef
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87495
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
---
 src/mainboard/starlabs/starfighter/cfr.c         |   9 +++++++++
 src/mainboard/starlabs/starfighter/mainboard.c   |   9 +++++++++
 .../starfighter/variants/rpl/Makefile.mk         |   2 ++
 .../starfighter/variants/rpl/data_native_res.vbt | Bin 0 -> 9216 bytes
 4 files changed, 20 insertions(+)
 create mode 100644 src/mainboard/starlabs/starfighter/variants/rpl/data_native_res.vbt

diff --git a/src/mainboard/starlabs/starfighter/cfr.c b/src/mainboard/starlabs/starfighter/cfr.c
index e8522f10eb..bbef3a7c26 100644
--- a/src/mainboard/starlabs/starfighter/cfr.c
+++ b/src/mainboard/starlabs/starfighter/cfr.c
@@ -165,6 +165,14 @@ static const struct sm_object bluetooth_rtd3 = SM_DECLARE_BOOL({
 	.default_value	= true,
 });
 
+static const struct sm_object display_native_res = SM_DECLARE_BOOL({
+	.opt_name	= "display_native_res",
+	.ui_name	= "Display: Use Native Resolution",
+	.ui_helptext	= "Enabled: use the native panel resolution at boot.\n"
+			  "Disabled: use a fixed/scaled video mode at boot.",
+	.default_value	= false,
+});
+
 static struct sm_obj_form performance = {
 	.ui_name = "Performance",
 	.obj_list = (const struct sm_object *[]) {
@@ -213,6 +221,7 @@ static struct sm_obj_form devices = {
 		#if CONFIG(SOC_INTEL_TIGERLAKE) || CONFIG(SOC_INTEL_ALDERLAKE) || CONFIG(SOC_INTEL_RAPTORLAKE)
 		&gna,
 		#endif
+		&display_native_res,
 		#if CONFIG(EC_STARLABS_LID_SWITCH)
 		&lid_switch,
 		#endif
diff --git a/src/mainboard/starlabs/starfighter/mainboard.c b/src/mainboard/starlabs/starfighter/mainboard.c
index d394f2579d..e9c17e53ed 100644
--- a/src/mainboard/starlabs/starfighter/mainboard.c
+++ b/src/mainboard/starlabs/starfighter/mainboard.c
@@ -1,6 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
 #include <device/device.h>
+#include <drivers/intel/gma/opregion.h>
 #include <soc/ramstage.h>
 #include <option.h>
 #include <variants.h>
@@ -25,3 +26,11 @@ static void init_mainboard(void *chip_info)
 struct chip_operations mainboard_ops = {
 	.init = init_mainboard,
 };
+
+const char *mainboard_vbt_filename(void)
+{
+	if (get_uint_option("display_native_res", 0) == 1)
+		return "vbt_native_res.bin";
+
+	return "vbt.bin";
+}
diff --git a/src/mainboard/starlabs/starfighter/variants/rpl/Makefile.mk b/src/mainboard/starlabs/starfighter/variants/rpl/Makefile.mk
index 2a505c35c7..53efc2f0fe 100644
--- a/src/mainboard/starlabs/starfighter/variants/rpl/Makefile.mk
+++ b/src/mainboard/starlabs/starfighter/variants/rpl/Makefile.mk
@@ -7,3 +7,5 @@ romstage-y += romstage.c
 ramstage-y += devtree.c
 ramstage-y += gpio.c
 ramstage-y += hda_verb.c
+
+$(call add_vbt_to_cbfs, vbt_native_res.bin, data_native_res.vbt)
diff --git a/src/mainboard/starlabs/starfighter/variants/rpl/data_native_res.vbt b/src/mainboard/starlabs/starfighter/variants/rpl/data_native_res.vbt
new file mode 100644
index 0000000000000000000000000000000000000000..9020e8740d6c5e194e749680361434ccf102137a
GIT binary patch
literal 9216
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mmZCVXzK1W;c6<lNk8IV5#d!B`@cC!s_axXrTUq|E4Ezp%r*|#@

literal 0
HcmV?d00001


From ac948173ad46564f30cff8a9e93a511a7c5c2cb3 Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Thu, 17 Apr 2025 23:19:27 -0500
Subject: [PATCH 0904/3886] mb/starlabs/starfighter/rpl: Add ramstage.c to
 makefile

Was inadvertently left out when this board was created.

TEST=build, verify ramstage.o created in variant subdir of build dir.

Change-Id: I3c728ba2abe94be4115a60d3a532cf0a19bec33c
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87496
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
---
 src/mainboard/starlabs/starfighter/variants/rpl/Makefile.mk | 1 +
 1 file changed, 1 insertion(+)

diff --git a/src/mainboard/starlabs/starfighter/variants/rpl/Makefile.mk b/src/mainboard/starlabs/starfighter/variants/rpl/Makefile.mk
index 53efc2f0fe..bfea7ef255 100644
--- a/src/mainboard/starlabs/starfighter/variants/rpl/Makefile.mk
+++ b/src/mainboard/starlabs/starfighter/variants/rpl/Makefile.mk
@@ -7,5 +7,6 @@ romstage-y += romstage.c
 ramstage-y += devtree.c
 ramstage-y += gpio.c
 ramstage-y += hda_verb.c
+ramstage-y += ramstage.c
 
 $(call add_vbt_to_cbfs, vbt_native_res.bin, data_native_res.vbt)

From 565c768c20513416cc21bac098f345430d363521 Mon Sep 17 00:00:00 2001
From: Harrie Paijmans <hpaijmans@eltan.com>
Date: Tue, 22 Apr 2025 13:45:26 +0200
Subject: [PATCH 0905/3886] soc/intel/alderlake: only add wifi Mitigation if
 DRIVERS_WIFI_GENERIC
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

If DRIVERS_WIFI_GENERIC is disabled
`wifi_generic_cnvi_ddr_rfim_enabled` can't be found by the linker.
Additionally if there is no WIFI driver the CNVi DDR RFI Mitigation is
redundant.

Add DRIVERS_WIFI_GENERIC check around `CNVi DDR RFI Mitigation`.

TEST=Boot Intel Alder Lake-P RVP with DRIVERS_WIFI_GENERIC=N and
cnvi_wifi disabled

Change-Id: I4f89ef41a730e38e08886828db0d14f1277ccaf0
Signed-off-by: Harrie Paijmans <hpaijmans@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87418
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
---
 src/soc/intel/alderlake/romstage/fsp_params.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/src/soc/intel/alderlake/romstage/fsp_params.c b/src/soc/intel/alderlake/romstage/fsp_params.c
index 24b2c8c002..427de4d7c3 100644
--- a/src/soc/intel/alderlake/romstage/fsp_params.c
+++ b/src/soc/intel/alderlake/romstage/fsp_params.c
@@ -232,6 +232,7 @@ static void fill_fspm_misc_params(FSP_M_CONFIG *m_cfg,
 	m_cfg->GpioOverride = 0x1;
 
 	/* CNVi DDR RFI Mitigation */
+#if (CONFIG(DRIVERS_WIFI_GENERIC))
 	const struct device_path path[] = {
 		{ .type = DEVICE_PATH_PCI, .pci.devfn = PCH_DEVFN_CNVI_WIFI },
 		{ .type = DEVICE_PATH_GENERIC, .generic.id = 0 } };
@@ -239,6 +240,7 @@ static void fill_fspm_misc_params(FSP_M_CONFIG *m_cfg,
 							ARRAY_SIZE(path));
 	if (is_dev_enabled(dev))
 		m_cfg->CnviDdrRfim = wifi_generic_cnvi_ddr_rfim_enabled(dev);
+#endif
 
 	/* Skip MBP HOB */
 	m_cfg->SkipMbpHob = !CONFIG(FSP_PUBLISH_MBP_HOB);

From c1bcb43f7c0256db4bce8aac46217c67afa4c027 Mon Sep 17 00:00:00 2001
From: Julius Werner <jwerner@chromium.org>
Date: Fri, 2 May 2025 18:12:51 -0700
Subject: [PATCH 0906/3886] cbgfx: Prevent divide-by-zero edge case in Lanczos
 kernel

The existing lanczos_weight() implementation naively follows the purely
mathematical definition for the `x == 0` special case. However, the
point of defining that special case is obviously to prevent division by
zero in the general case formula. Unfortunately we are still doing some
multiplications with `x` before we get to the division step, and our
fpmath library loses precision during multiplication. This can lead to
edge cases where `x` is not zero but `x_times_pi` later ends up being 0,
which causes the division to throw an exception after all. (I guess
we've just been lucky to not see this case in practice for now... it
requires the output pixel coordinate to be extremely close to but not
quite on the next input pixel coordinate, which may be rare in practice
with our scaling algorithms.)

This patch fixes the issue by implementing the special case later and
checking if `x_times_pi` is zero instead. Note that as long as we pass
this check, we can be confident that the division cannot fail even
though fpdiv() also truncates the divisor: this is because `x_times_pi`
was calculated from an fpmul() call with the constant fppi(), which has
34 significant bits. Even if x is the smallest possible non-zero value
after scaling for multiplication, the result `x_times_pi` must still
have 18 significant bits. That means it can be scaled down a further 16
bits for division without becoming zero.

Also add a simple unit test forcing exactly this condition to ensure the
code will not regress.

Change-Id: I2f212ee5df38252e97ec55aba3d2d25320c4b102
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87532
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Jakub "Kuba" Czapiga <czapiga@google.com>
---
 payloads/libpayload/drivers/video/graphics.c  |  9 ++++----
 payloads/libpayload/tests/drivers/Makefile.mk |  5 +++-
 .../libpayload/tests/drivers/graphics-test.c  | 23 +++++++++++++++++++
 3 files changed, 32 insertions(+), 5 deletions(-)
 create mode 100644 payloads/libpayload/tests/drivers/graphics-test.c

diff --git a/payloads/libpayload/drivers/video/graphics.c b/payloads/libpayload/drivers/video/graphics.c
index 632a283de9..b9a93a03e2 100644
--- a/payloads/libpayload/drivers/video/graphics.c
+++ b/payloads/libpayload/drivers/video/graphics.c
@@ -715,19 +715,20 @@ static fpmath_t lanczos_weight(fpmath_t in, int off)
 	 *
 	 * So (off - S0) - (in - floor(in)) is the distance from the sample
 	 * pixel to S0 minus the distance from S0 to the output pixel, aka
-	 * the distance from the sample pixel to the output pixel.
+	 * the distance from the sample pixel to the output pixel. (Note that
+	 * this calculation using fpfloor() is only valid if |in| is not
+	 * negative, which is always the case for our current code.)
 	 */
 	fpmath_t x = fpisub(off - S0, fpsubi(in, fpfloor(in)));
 
-	if (fpequals(x, fp(0)))
-		return fp(1);
-
 	/* x * 2 / a can save some instructions if a == 2 */
 	fpmath_t x2a = x;
 	if (LNCZ_A != 2)
 		x2a = fpmul(x, fpfrac(2, LNCZ_A));
 
 	fpmath_t x_times_pi = fpmul(x, fppi());
+	if (fpequals(x_times_pi, fp(0)))
+		return fp(1);
 
 	/*
 	 * Rather than using sinr(pi*x), we leverage the "one-based" sine
diff --git a/payloads/libpayload/tests/drivers/Makefile.mk b/payloads/libpayload/tests/drivers/Makefile.mk
index 7705473ef7..8d668c2e42 100644
--- a/payloads/libpayload/tests/drivers/Makefile.mk
+++ b/payloads/libpayload/tests/drivers/Makefile.mk
@@ -1,6 +1,9 @@
 # SPDX-License-Identifier: GPL-2.0-only
 
-tests-y += speaker-test
+tests-y += graphics-test speaker-test
+
+graphics-test-srcs += tests/drivers/graphics-test.c
+graphics-test-srcs += libc/fpmath.c
 
 speaker-test-srcs += tests/drivers/speaker-test.c
 speaker-test-mocks += inb
diff --git a/payloads/libpayload/tests/drivers/graphics-test.c b/payloads/libpayload/tests/drivers/graphics-test.c
new file mode 100644
index 0000000000..6e4d9b3528
--- /dev/null
+++ b/payloads/libpayload/tests/drivers/graphics-test.c
@@ -0,0 +1,23 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include "../drivers/video/graphics.c"
+
+#include <libpayload.h>
+#include <tests/test.h>
+
+static void test_lanczos(void **state)
+{
+	/* This makes sure the `x` in lanczos_weight() becomes very small. This
+	   test is mostly here to prove we won't end up dividing by zero. */
+	fpmath_t x = lanczos_weight(fpisub(1, fpfrac(1, 1 << 30)), S0 + 1);
+	assert_true(fpequals(x, fp(1)));
+}
+
+int main(void)
+{
+	const struct CMUnitTest tests[] = {
+		cmocka_unit_test(test_lanczos),
+	};
+
+	return lp_run_group_tests(tests, NULL, NULL);
+}

From a85b9a21b281d5aed28c294d82ebaed9df99d0f7 Mon Sep 17 00:00:00 2001
From: Bora Guvendik <bora.guvendik@intel.com>
Date: Fri, 4 Apr 2025 19:07:51 -0700
Subject: [PATCH 0907/3886] mb/intel/ptlrvp: Add support for DDR5 configuration
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

This commit introduces support for DDR5 memory configuration on the
PTL RVP DDR5 board. It adds the necessary board ID for PTLP_DDR5_RVP
and integrates a new DDR5 memory configuration within the variant
parameters. The memory configuration includes settings such as
resistor values, sagv values, early command training, and
DDR5-specific training parameters.

Additionally, SPD information retrieval is adapted to accommodate
DDR5-specific settings, such as DIMM module topology and SMBus
addresses.

BUG=none
TEST=Boot to OS with PTL RVP DDR5 board and verify memory
initialization.

Change-Id: I7e3bbb66edcbf4d4a10fcf6899156f125dc3d529
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87179
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/intel/ptlrvp/romstage.c         | 36 +++++++++-----
 .../baseboard/include/baseboard/variants.h    |  1 +
 .../intel/ptlrvp/variants/ptlrvp/memory.c     | 47 ++++++++++++++++++-
 3 files changed, 70 insertions(+), 14 deletions(-)

diff --git a/src/mainboard/intel/ptlrvp/romstage.c b/src/mainboard/intel/ptlrvp/romstage.c
index 1c5297125b..171465ec12 100644
--- a/src/mainboard/intel/ptlrvp/romstage.c
+++ b/src/mainboard/intel/ptlrvp/romstage.c
@@ -23,11 +23,30 @@ __weak void variant_update_soc_memory_init_params(FSPM_UPD *memupd)
 	/* Nothing to do */
 }
 
+static void update_ddr5_sagv_points(FSP_M_CONFIG *m_cfg)
+{
+	int board_id = get_rvp_board_id();
+
+	if (board_id != PTLP_DDR5_RVP)
+		return;
+
+	m_cfg->SaGvFreq[0] = 3200;
+	m_cfg->SaGvGear[0] = GEAR_4;
+
+	m_cfg->SaGvFreq[1] = 4800;
+	m_cfg->SaGvGear[1] = GEAR_4;
+
+	m_cfg->SaGvFreq[2] = 5600;
+	m_cfg->SaGvGear[2] = GEAR_4;
+
+	m_cfg->SaGvFreq[3] = 6400;
+	m_cfg->SaGvGear[3] = GEAR_4;
+}
+
 void mainboard_memory_init_params(FSPM_UPD *memupd)
 {
 	const struct pad_config *pads;
 	size_t pads_num;
-	int board_id = get_rvp_board_id();
 	const struct mb_cfg *mem_config = variant_memory_params();
 	bool half_populated = variant_is_half_populated();
 	struct mem_spd spd_info;
@@ -40,17 +59,10 @@ void mainboard_memory_init_params(FSPM_UPD *memupd)
 	memset(&spd_info, 0, sizeof(spd_info));
 	variant_get_spd_info(&spd_info);
 
-	switch (board_id) {
-	case PTLP_LP5_T3_RVP:
-	case PTLP_LP5_T4_RVP:
-	case GCS_32GB:
-	case GCS_64GB:
-		memcfg_init(memupd, mem_config, &spd_info, half_populated);
-		break;
-	default:
-		die("Unknown board id = 0x%x\n", board_id);
-		break;
-	}
+	memcfg_init(memupd, mem_config, &spd_info, half_populated);
+
+	/* Override FSP-M SaGv frequency and gear for DDR5 boards */
+	update_ddr5_sagv_points(&memupd->FspmConfig);
 
 	/* Override FSP-M UPD per board if required. */
 	variant_update_soc_memory_init_params(memupd);
diff --git a/src/mainboard/intel/ptlrvp/variants/baseboard/include/baseboard/variants.h b/src/mainboard/intel/ptlrvp/variants/baseboard/include/baseboard/variants.h
index d44ef98552..0ee09a5835 100644
--- a/src/mainboard/intel/ptlrvp/variants/baseboard/include/baseboard/variants.h
+++ b/src/mainboard/intel/ptlrvp/variants/baseboard/include/baseboard/variants.h
@@ -13,6 +13,7 @@
 enum ptl_boardid {
 	PTLP_LP5_T3_RVP = 0x01,
 	PTLP_LP5_T4_RVP = 0x03,
+	PTLP_DDR5_RVP = 0x04,
 	GCS_32GB = 0x11,
 	GCS_64GB = 0x12,
 };
diff --git a/src/mainboard/intel/ptlrvp/variants/ptlrvp/memory.c b/src/mainboard/intel/ptlrvp/variants/ptlrvp/memory.c
index 3a223e46a7..6a1706fe9f 100644
--- a/src/mainboard/intel/ptlrvp/variants/ptlrvp/memory.c
+++ b/src/mainboard/intel/ptlrvp/variants/ptlrvp/memory.c
@@ -125,6 +125,24 @@ static const struct mb_cfg lp5_mem_config = {
 	},
 };
 
+static const struct mb_cfg ddr5_mem_config = {
+	.type = MEM_TYPE_DDR5,
+
+	.rcomp = {
+		.resistor = 100,
+	},
+
+	.ect = true, /* Early Command Training */
+
+	.user_bd = BOARD_TYPE_ULT_ULX,
+
+	.lp_ddr_dq_dqs_re_training = 1,
+
+	.ddr_config = {
+		.dq_pins_interleaved = false,
+	}
+};
+
 const struct mb_cfg *variant_memory_params(void)
 {
 	int board_id = get_rvp_board_id();
@@ -136,6 +154,8 @@ const struct mb_cfg *variant_memory_params(void)
 	case GCS_32GB:
 	case GCS_64GB:
 		return &gcs_mem_config;
+	case PTLP_DDR5_RVP:
+		return &ddr5_mem_config;
 	default:
 		die("Unknown board id = 0x%x\n", board_id);
 		break;
@@ -144,6 +164,29 @@ const struct mb_cfg *variant_memory_params(void)
 
 void variant_get_spd_info(struct mem_spd *spd_info)
 {
-	spd_info->topo = MEM_TOPO_MEMORY_DOWN;
-	spd_info->cbfs_index = variant_memory_sku();
+	int board_id = get_rvp_board_id();
+
+	switch (board_id) {
+	case PTLP_LP5_T3_RVP:
+	case PTLP_LP5_T4_RVP:
+	case GCS_32GB:
+	case GCS_64GB:
+		spd_info->topo = MEM_TOPO_MEMORY_DOWN;
+		spd_info->cbfs_index = variant_memory_sku();
+		break;
+	case PTLP_DDR5_RVP:
+		spd_info->topo = MEM_TOPO_DIMM_MODULE;
+		spd_info->smbus[0].addr_dimm[0] = 0x50;
+		spd_info->smbus[0].addr_dimm[1] = 0x0;
+		spd_info->smbus[1].addr_dimm[0] = 0x50;
+		spd_info->smbus[1].addr_dimm[1] = 0x0;
+		spd_info->smbus[2].addr_dimm[0] = 0x52;
+		spd_info->smbus[2].addr_dimm[1] = 0x0;
+		spd_info->smbus[3].addr_dimm[0] = 0x52;
+		spd_info->smbus[3].addr_dimm[1] = 0x0;
+		break;
+	default:
+		die("Unknown board id = 0x%x\n", board_id);
+		break;
+	}
 }

From 1015d4332fc9c8b0e3417eafab8154603b14b758 Mon Sep 17 00:00:00 2001
From: Subrata Banik <subratabanik@google.com>
Date: Fri, 25 Apr 2025 12:11:11 +0530
Subject: [PATCH 0908/3886] mainboard/google/bluey: Add fingerprint sensor GPIO
 entries

This commit introduces Kconfig options and GPIO definitions to support
onboard fingerprint sensors for the Bluey mainboard.

Source: Bluey schematics (dated 04/15).

BUG=b:404985109
TEST=Successfully built google/bluey with the Qualcomm x1p42100 SoC.

Change-Id: Ia8f1a7b2dab3bef1a9332d8c0020489c06bd4f99
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87448
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jayvik Desai <jayvik@google.com>
---
 src/mainboard/google/bluey/Kconfig | 22 ++++++++++++++++++++++
 src/mainboard/google/bluey/board.h | 14 ++++++++++++++
 2 files changed, 36 insertions(+)

diff --git a/src/mainboard/google/bluey/Kconfig b/src/mainboard/google/bluey/Kconfig
index 5c74c81ac4..2de1c01649 100644
--- a/src/mainboard/google/bluey/Kconfig
+++ b/src/mainboard/google/bluey/Kconfig
@@ -25,12 +25,34 @@ config BOARD_GOOGLE_BASEBOARD_BLUEY
 
 config BOARD_GOOGLE_BLUEY
 	select BOARD_GOOGLE_BASEBOARD_BLUEY
+	select MAINBOARD_HAS_FINGERPRINT_VIA_USB
 
 if BOARD_GOOGLE_BLUEY_COMMON
 
 config MAINBOARD_DIR
 	default "google/bluey"
 
+config MAINBOARD_HAS_FINGERPRINT_VIA_SPI
+	bool
+	default n
+	help
+	  Enable this option if your mainboard's fingerprint reader
+	  is connected via the SPI interface.
+
+config MAINBOARD_HAS_FINGERPRINT_VIA_USB
+	bool
+	default n
+	help
+	  Enable this option if your mainboard's fingerprint reader
+	  is connected via the USB interface.
+
+config MAINBOARD_HAS_FINGERPRINT
+	bool
+	default y if MAINBOARD_HAS_FINGERPRINT_VIA_SPI || MAINBOARD_HAS_FINGERPRINT_VIA_USB
+	help
+	  Enable this option if your mainboard is equipped with an onboard
+	  fingerprint reader. This could be connected via SPI or USB.
+
 config MAINBOARD_VENDOR
 	string
 	default "Google"
diff --git a/src/mainboard/google/bluey/board.h b/src/mainboard/google/bluey/board.h
index 618eadce2a..c47b164127 100644
--- a/src/mainboard/google/bluey/board.h
+++ b/src/mainboard/google/bluey/board.h
@@ -10,6 +10,20 @@
 #define GSC_AP_INT(x)		GPIO(x)
 #define GPIO_GSC_AP_INT		GSC_AP_INT(CONFIG_MAINBOARD_GPIO_PIN_FOR_GSC_AP_INTERRUPT)
 
+/* Fingerprint-specific GPIOs. Only for fingerprint-enabled devices. */
+#if CONFIG(MAINBOARD_HAS_FINGERPRINT)
+#define GPIO_FP_RST_L		GPIO(25)
+#if CONFIG(MAINBOARD_HAS_FINGERPRINT_VIA_SPI)
+#define GPIO_FPMCU_BOOT0	GPIO(24)
+#define GPIO_FPMCU_INT		GPIO(23)
+#define GPIO_EN_FP_RAILS	GPIO(22)
+#else
+#define GPIO_FPMCU_BOOT0	dead_code_t(gpio_t)
+#define GPIO_FPMCU_INT		dead_code_t(gpio_t)
+#define GPIO_EN_FP_RAILS	dead_code_t(gpio_t)
+#endif
+#endif
+
 void setup_chromeos_gpios(void);
 
 #endif /* MAINBOARD_GOOGLE_BLUEY_BOARD_H */

From 80901a4494ff0a29f6fac9cbea73c92c7f5e32dc Mon Sep 17 00:00:00 2001
From: Subrata Banik <subratabanik@google.com>
Date: Fri, 25 Apr 2025 12:22:33 +0530
Subject: [PATCH 0909/3886] mb/google/bluey: Add GPIOs for Soundwire, Display,
 and SD Card

This commit introduces several new GPIO definitions and a Kconfig
option for the Bluey mainboard to support additional hardware features.

Kconfig changes:

 - MAINBOARD_HAS_SD_CONTROLLER: To indicate the presence of an SD card
   controller. It defaults to 'n'.

GPIO changes (in board.h):

 - Soundwire Amplifier GPIOs:
     - GPIO_SNDW_AMP_0_ENABLE (GPIO 204)
     - GPIO_SNDW_AMP_1_ENABLE (GPIO 205)

 - Display specific GPIOs:
     - GPIO_PANEL_POWER_ON (GPIO 70)
     - GPIO_PANEL_HPD (GPIO 119)

 - SD Card specific GPIO:
     - GPIO_SD_CD_L (GPIO 71): This GPIO is conditionally defined based
       on the new CONFIG_MAINBOARD_HAS_SD_CONTROLLER option.

Source: Bluey schematics (dated 04/15).

BUG=b:404985109
TEST=Successfully built google/bluey with the Qualcomm x1p42100 SoC.

Change-Id: I556b06bff73805c6451a5f8cf291c83cd0431465
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87449
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jayvik Desai <jayvik@google.com>
---
 src/mainboard/google/bluey/Kconfig |  6 ++++++
 src/mainboard/google/bluey/board.h | 13 +++++++++++++
 2 files changed, 19 insertions(+)

diff --git a/src/mainboard/google/bluey/Kconfig b/src/mainboard/google/bluey/Kconfig
index 2de1c01649..87cefb5483 100644
--- a/src/mainboard/google/bluey/Kconfig
+++ b/src/mainboard/google/bluey/Kconfig
@@ -53,6 +53,12 @@ config MAINBOARD_HAS_FINGERPRINT
 	  Enable this option if your mainboard is equipped with an onboard
 	  fingerprint reader. This could be connected via SPI or USB.
 
+config MAINBOARD_HAS_SD_CONTROLLER
+	bool
+	default n
+	help
+	  Enable this option if your mainboard is equipped with SD card controller.
+
 config MAINBOARD_VENDOR
 	string
 	default "Google"
diff --git a/src/mainboard/google/bluey/board.h b/src/mainboard/google/bluey/board.h
index c47b164127..b5b719d7bc 100644
--- a/src/mainboard/google/bluey/board.h
+++ b/src/mainboard/google/bluey/board.h
@@ -24,6 +24,19 @@
 #endif
 #endif
 
+/* Soundwire AMP GPIOs */
+#define GPIO_SNDW_AMP_0_ENABLE	GPIO(204)
+#define GPIO_SNDW_AMP_1_ENABLE	GPIO(205)
+
+/* Display specific GPIOs */
+#define GPIO_PANEL_POWER_ON	GPIO(70)
+#define GPIO_PANEL_HPD		GPIO(119)
+
+/* SD card specific GPIOs. Only for SD-enabled devices. */
+#if CONFIG(MAINBOARD_HAS_SD_CONTROLLER)
+#define GPIO_SD_CD_L		GPIO(71)
+#endif
+
 void setup_chromeos_gpios(void);
 
 #endif /* MAINBOARD_GOOGLE_BLUEY_BOARD_H */

From 18172b600903cd9067283032615a6f14eeeb7e3f Mon Sep 17 00:00:00 2001
From: Subrata Banik <subratabanik@google.com>
Date: Fri, 25 Apr 2025 13:17:52 +0530
Subject: [PATCH 0910/3886] mb/google/bluey: Add SoundWire amp and SD card
 GPIOs to lb_gpios

This commit updates the `fill_lb_gpios` function in
`src/mainboard/google/bluey/chromeos.c` to include additional
GPIO states for Chrome OS diagnostics.

The following GPIOs are now reported:
- GPIO_SNDW_AMP_0_ENABLE: "Speaker 0 enable" (active high)
- GPIO_SNDW_AMP_1_ENABLE: "Speaker 1 enable" (active high)
- GPIO_SD_CD_L: "SD card detect" (active low), reported
  conditionally if CONFIG_MAINBOARD_HAS_SD_CONTROLLER is enabled.

BUG=b:404985109
TEST=Successfully built google/bluey with the Qualcomm x1p42100 SoC.

Change-Id: I0063e8190571241edda64165b9ade9c4331a3499
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87451
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jayvik Desai <jayvik@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
---
 src/mainboard/google/bluey/chromeos.c | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/src/mainboard/google/bluey/chromeos.c b/src/mainboard/google/bluey/chromeos.c
index aad0b0fea3..9fa8718e02 100644
--- a/src/mainboard/google/bluey/chromeos.c
+++ b/src/mainboard/google/bluey/chromeos.c
@@ -20,6 +20,14 @@ void fill_lb_gpios(struct lb_gpios *gpios)
 			"EC interrupt"},
 		{GPIO_GSC_AP_INT.addr, ACTIVE_HIGH, gpio_get(GPIO_GSC_AP_INT),
 			"TPM interrupt"},
+		{GPIO_SNDW_AMP_0_ENABLE.addr, ACTIVE_HIGH, gpio_get(GPIO_SNDW_AMP_0_ENABLE),
+			"Speaker 0 enable"},
+		{GPIO_SNDW_AMP_1_ENABLE.addr, ACTIVE_HIGH, gpio_get(GPIO_SNDW_AMP_1_ENABLE),
+			"Speaker 1 enable"},
+#if CONFIG(MAINBOARD_HAS_SD_CONTROLLER)
+		{GPIO_SD_CD_L.addr, ACTIVE_LOW, gpio_get(GPIO_SD_CD_L),
+			"SD card detect"},
+#endif
 	};
 
 	lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios));

From 3278551f8ca925388c31291d52e7ba3cf4a465f4 Mon Sep 17 00:00:00 2001
From: Subrata Banik <subratabanik@google.com>
Date: Mon, 5 May 2025 17:19:09 +0530
Subject: [PATCH 0911/3886] drivers/intel/fsp2_0: Include coreboot_tables.h in
 fsp_gop_blt.h
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

The fsp_gop_blt.h header includes `enum lb_fb_orientation`. This enum
is defined within `<boot/coreboot_tables.h>`.

This commit adds the necessary include directive to ensure that
`enum lb_fb_orientation` is available.

BUG=b:409718202
TEST=Able to build and boot google/fatcat.

Change-Id: I0e432bef13ab1425c29e9ca4a82b06ff264a8613
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87537
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/drivers/intel/fsp2_0/include/fsp/fsp_gop_blt.h | 1 +
 1 file changed, 1 insertion(+)

diff --git a/src/drivers/intel/fsp2_0/include/fsp/fsp_gop_blt.h b/src/drivers/intel/fsp2_0/include/fsp/fsp_gop_blt.h
index 4e1f68952e..377607929a 100644
--- a/src/drivers/intel/fsp2_0/include/fsp/fsp_gop_blt.h
+++ b/src/drivers/intel/fsp2_0/include/fsp/fsp_gop_blt.h
@@ -3,6 +3,7 @@
 #ifndef FSP_GOP_BLT_H
 #define FSP_GOP_BLT_H
 
+#include <boot/coreboot_tables.h>
 #include <efi/efi_datatype.h>
 #include <types.h>
 

From 2fc246cd2dd60f15c3a726fe7c6b04ebf4cf31ed Mon Sep 17 00:00:00 2001
From: Appukuttan V K <appukuttan.vk@intel.com>
Date: Tue, 29 Apr 2025 10:30:20 +0530
Subject: [PATCH 0912/3886] mb/google/ocelot: Remove unused devices from
 devicetree

This patch removes device entries from the Ocelot mainboard
devicetree that do not exist in the Wildcat Lake SoC. This ensures
that the Ocelot firmware compiles without any errors when device
tree changes of Wildcat Lake SoC are added in the subsequent patches.

Key changes:
  - Remove the following devices, which are not present in the
    Wildcat Lake SoC, from Ocelot:
        ipu
        tbt_pcie_rp2
        tbt_pcie_rp3
        tcss_dma1
        pcie_rp9
        tcss USB port 2 & 3

References:
- Wildcat Lake Processor EDS Volume 1 (#842271)
- Wildcat Lake External Design Specification (EDS) Volume 2 (#829345)

BUG=b:394208231
TEST=Build Ocelot and verify it compiles  without any error.

Change-Id: Ib09f66f2e567f3f42810215bca8956c7cee7b646
Signed-off-by: Appukuttan V K <appukuttan.vk@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87479
Reviewed-by: Usha P <usha.p@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 .../ocelot/variants/ocelot/overridetree.cb    | 43 -------------------
 1 file changed, 43 deletions(-)

diff --git a/src/mainboard/google/ocelot/variants/ocelot/overridetree.cb b/src/mainboard/google/ocelot/variants/ocelot/overridetree.cb
index 30daba5572..f0c1039c01 100644
--- a/src/mainboard/google/ocelot/variants/ocelot/overridetree.cb
+++ b/src/mainboard/google/ocelot/variants/ocelot/overridetree.cb
@@ -288,7 +288,6 @@ chip soc/intel/pantherlake
 			end
 		end
 
-		device ref ipu off end
 		device ref iaa off end
 
 		device ref thc0 on
@@ -356,8 +355,6 @@ chip soc/intel/pantherlake
 
 		device ref tbt_pcie_rp0 on end
 		device ref tbt_pcie_rp1 on end
-		device ref tbt_pcie_rp2 on end
-		device ref tbt_pcie_rp3 on end
 		device ref tcss_xhci on
 			chip drivers/usb/acpi
 				device ref tcss_root_hub on
@@ -373,18 +370,6 @@ chip soc/intel/pantherlake
 						register "group" = "ACPI_PLD_GROUP(3, 2)"
 						device ref tcss_usb3_port1 on end
 					end
-					chip drivers/usb/acpi
-						register "desc" = ""USB3 Type-C Port C2""
-						register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
-						register "group" = "ACPI_PLD_GROUP(2, 2)"
-						device ref tcss_usb3_port2 on end
-					end
-					chip drivers/usb/acpi
-						register "desc" = ""USB3 Type-C Port C3""
-						register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
-						register "group" = "ACPI_PLD_GROUP(1, 2)"
-						device ref tcss_usb3_port3 on end
-					end
 				end
 			end
 		end
@@ -401,18 +386,6 @@ chip soc/intel/pantherlake
 				device generic 0 on end
 			end
 		end
-		device ref tcss_dma1 on
-			chip drivers/intel/usb4/retimer
-				register "dfp[0].power_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B21)"
-				use tcss_usb3_port2 as dfp[0].typec_port
-				device generic 0 on end
-			end
-			chip drivers/intel/usb4/retimer
-				register "dfp[1].power_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B21)"
-				use tcss_usb3_port3 as dfp[1].typec_port
-				device generic 0 on end
-			end
-		end
 
 		device ref ish on
 			probe ISH ISH_ENABLE
@@ -578,22 +551,6 @@ chip soc/intel/pantherlake
 				device generic 0 on end
 			end
 		end # Gen4 M.2 SSD
-		device ref pcie_rp9 on
-			probe STORAGE STORAGE_NVME_GEN5
-			probe STORAGE STORAGE_UNKNOWN
-			register "pcie_rp[PCIE_RP(9)]" = "{
-			.clk_src = 1,
-			.clk_req = 1,
-			.flags = PCIE_RP_CLK_REQ_DETECT | PCIE_RP_LTR | PCIE_RP_AER,
-			}"
-			chip soc/intel/common/block/pcie/rtd3
-				register "is_storage" = "true"
-				register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B16)"
-				register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_E03)"
-				register "srcclk_pin" = "1"
-				device generic 0 on end
-			end
-		end # Gen5 M.2 SSD
 		device ref cnvi_wifi on
 			probe WIFI WIFI_CNVI_6
 			probe WIFI WIFI_CNVI_7

From 1baf0baf580982d1aa5cdb1e1cce149977618d18 Mon Sep 17 00:00:00 2001
From: Appukuttan V K <appukuttan.vk@intel.com>
Date: Wed, 30 Apr 2025 22:14:55 +0530
Subject: [PATCH 0913/3886] soc/intel/ptl: Add Wildcat Lake SoC device tree

This patch introduces a new chipset device tree file for Wildcat
Lake SoC.

Key changes:
 - Copy the Panther Lake chipset.cb to chipset_wcl.cb and update
   it with device information specific to the Wildcat Lake SoC.
   1) Remove following devices:
        - Ipu         - 00:05.0
        - Tbt Rp      - 00:07.2 & 00:07.3
        - Type-C xDCI - 00:0d.1
        - Tcss Dma    - 00:0d.3
        - Pci Rp      - 00:1c.4 to 00:1c.7
                      - 00:06.2 & 00:06.3
        - Two TCSS USB ports
   2) Remove Panther Lake Power limits config and add placeholder
      for WCL config.
 - Guard removed TCSS port references in the shared SoC code with
   Kconfig.
 - Rename Panther Lake chipset device tree to chipset_ptl.cb to
   align with the new device tree naming.
 - Update Kconfig to select the newly added chipset device tree
   file when the Wildcat Lake SoC is in use.

References:
- Wildcat Lake Processor EDS, Volume 1 (#842271)
- Wildcat Lake External Design Specification (EDS) Volume 2 (#829345)

BUG=b:394208231
TEST=Build Ocelot and Fatcat and verify it compiles without any error.

Change-Id: Ieafb9856daaa48e3ecc6fc9068ae2b2d4019ff80
Signed-off-by: Appukuttan V K <appukuttan.vk@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87490
Reviewed-by: Usha P <usha.p@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/soc/intel/pantherlake/Kconfig             |   3 +-
 .../{chipset.cb => chipset_ptl.cb}            |   0
 src/soc/intel/pantherlake/chipset_wcl.cb      | 132 ++++++++++++++++++
 3 files changed, 134 insertions(+), 1 deletion(-)
 rename src/soc/intel/pantherlake/{chipset.cb => chipset_ptl.cb} (100%)
 create mode 100644 src/soc/intel/pantherlake/chipset_wcl.cb

diff --git a/src/soc/intel/pantherlake/Kconfig b/src/soc/intel/pantherlake/Kconfig
index 23eaaa61ed..412ccda4c3 100644
--- a/src/soc/intel/pantherlake/Kconfig
+++ b/src/soc/intel/pantherlake/Kconfig
@@ -192,7 +192,8 @@ config HEAP_SIZE
 
 config CHIPSET_DEVICETREE
 	string
-	default "soc/intel/pantherlake/chipset.cb"
+	default "soc/intel/pantherlake/chipset_wcl.cb" if SOC_INTEL_WILDCATLAKE
+	default "soc/intel/pantherlake/chipset_ptl.cb"
 
 config EXT_BIOS_WIN_BASE
 	default 0xf8000000
diff --git a/src/soc/intel/pantherlake/chipset.cb b/src/soc/intel/pantherlake/chipset_ptl.cb
similarity index 100%
rename from src/soc/intel/pantherlake/chipset.cb
rename to src/soc/intel/pantherlake/chipset_ptl.cb
diff --git a/src/soc/intel/pantherlake/chipset_wcl.cb b/src/soc/intel/pantherlake/chipset_wcl.cb
new file mode 100644
index 0000000000..c5f1d2bd11
--- /dev/null
+++ b/src/soc/intel/pantherlake/chipset_wcl.cb
@@ -0,0 +1,132 @@
+chip soc/intel/pantherlake
+
+	device cpu_cluster 0 on end
+
+	# TODO: Add WCL power limits
+
+	# Reduce the size of BasicMemoryTests to speed up the boot time.
+	register "lower_basic_mem_test_size" = "true"
+
+	# NOTE: if any variant wants to override this value, use the same format
+	# as register "common_soc_config.pch_thermal_trip" = "value", instead of
+	# putting it under register "common_soc_config" in overridetree.cb file.
+	register "common_soc_config.pch_thermal_trip" = "125"
+
+	device domain 0 on
+		device pci 00.0 alias system_agent on end
+		device pci 02.0 alias igpu on end
+		device pci 04.0 alias dtt off end
+		device pci 06.0 alias pcie_rp5 off end
+		device pci 06.1 alias pcie_rp6 off end
+		device pci 07.0 alias tbt_pcie_rp0 off
+			chip soc/intel/common/block/usb4
+				use tcss_dma0 as usb4_port
+				device generic 0 on end
+			end
+		end
+		device pci 07.1 alias tbt_pcie_rp1 off
+			chip soc/intel/common/block/usb4
+				use tcss_dma0 as usb4_port
+				device generic 1 on end
+			end
+		end
+		device pci 0a.0 alias crashlog on end
+		device pci 0b.0 alias npu off end
+		device pci 0c.0 alias iaa on end
+		device pci 0d.0 alias tcss_xhci off
+			chip drivers/usb/acpi
+				register "type" = "UPC_TYPE_HUB"
+				device usb 0.0 alias tcss_root_hub off
+					chip drivers/usb/acpi
+						device usb 3.0 alias tcss_usb3_port0 off end
+					end
+					chip drivers/usb/acpi
+						device usb 3.1 alias tcss_usb3_port1 off end
+					end
+				end
+			end
+		end
+		device pci 0d.2 alias tcss_dma0 off end
+		device pci 0e.0 alias vmd off end
+		device pci 10.0 alias thc0 off end
+		device pci 10.1 alias thc1 off end
+		device pci 12.0 alias ish off end
+		device pci 12.1 alias p2sb2 hidden end
+		device pci 12.6 alias gspi0a off end
+		device pci 13.0 alias heci_1 off end
+		device pci 13.1 alias heci_2 off end
+		device pci 13.2 alias heci_3 off end
+		device pci 14.0 alias xhci on
+			chip drivers/usb/acpi
+				register "type" = "UPC_TYPE_HUB"
+				device usb 0.0 alias xhci_root_hub off
+					chip drivers/usb/acpi
+						device usb 2.0 alias usb2_port1 off end
+					end
+					chip drivers/usb/acpi
+						device usb 2.1 alias usb2_port2 off end
+					end
+					chip drivers/usb/acpi
+						device usb 2.2 alias usb2_port3 off end
+					end
+					chip drivers/usb/acpi
+						device usb 2.3 alias usb2_port4 off end
+					end
+					chip drivers/usb/acpi
+						device usb 2.4 alias usb2_port5 off end
+					end
+					chip drivers/usb/acpi
+						device usb 2.5 alias usb2_port6 off end
+					end
+					chip drivers/usb/acpi
+						device usb 2.6 alias usb2_port7 off end
+					end
+					chip drivers/usb/acpi
+						device usb 2.7 alias usb2_port8 off end
+					end
+					chip drivers/usb/acpi
+						device usb 3.0 alias usb3_port1 off end
+					end
+					chip drivers/usb/acpi
+						device usb 3.1 alias usb3_port2 off end
+					end
+				end
+			end
+		end
+		device pci 14.2 alias pmc_shared_sram off end
+		device pci 14.3 alias cnvi_wifi off end
+		device pci 14.7 alias cnvi_bluetooth off end
+		device pci 14.5 alias ieh off end
+		device pci 15.0 alias i2c0 off end
+		device pci 15.1 alias i2c1 off end
+		device pci 15.2 alias i2c2 off end
+		device pci 15.3 alias i2c3 off end
+		device pci 16.0 alias heci1 on end
+		device pci 16.1 alias heci2 off end
+		device pci 16.4 alias heci3 off end
+		device pci 16.5 alias heci4 off end
+		device pci 17.0 alias ufs off end
+		device pci 18.0 alias eheci1 off end
+		device pci 18.1 alias eheci2 off end
+		device pci 18.2 alias eheci3 off end
+		device pci 19.0 alias i2c4 off end
+		device pci 19.1 alias i2c5 off end
+		device pci 19.2 alias uart2 off end
+		device pci 1c.0 alias pcie_rp1 off end
+		device pci 1c.1 alias pcie_rp2 off end
+		device pci 1c.2 alias pcie_rp3 off end
+		device pci 1c.3 alias pcie_rp4 off end
+		device pci 1e.0 alias uart0 off end
+		device pci 1e.1 alias uart1 off end
+		device pci 1e.2 alias gspi0 off end
+		device pci 1e.3 alias gspi1 off end
+		device pci 1f.0 alias soc_espi on end
+		device pci 1f.1 alias p2sb hidden end
+		device pci 1f.2 alias pmc hidden end
+		device pci 1f.3 alias hda off end
+		device pci 1f.4 alias smbus off end
+		device pci 1f.5 alias fast_spi on end
+		device pci 1f.6 alias gbe off end
+		device pci 1f.7 alias npk off end
+	end
+end

From db4162adce781ae2f167fdb6eaf109284e4fdfa6 Mon Sep 17 00:00:00 2001
From: Appukuttan V K <appukuttan.vk@intel.com>
Date: Fri, 2 May 2025 13:22:54 +0530
Subject: [PATCH 0914/3886] soc/intel/ptl: Add Wildcat Lake PCIe Device details
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

This commit introduces PCI device details specific to the Wildcat
Lake to Panther Lake code with conditional compilation.

Key changes:
  - Add Wildcat Lake-specific PCI device definitions and
    configurations, including adjustments to device function
    numbers and slot assignments.
       - Remove following
         - PCIe RP : 00:1c.4 to 00:1c.7
                   : 00:06.2 & 00:06.3
       - Change following
         - PCIe RP5 : 00:1c.4 to 00:06.0
         - PCIe RP6 : 00:1c.5 to 00:06.1
  - Following devices are not present in Wildcat Lake, but their
    device definitions are retained as they do not impact
    functionality.
       - IPU  : 00.05.0
       - TBT2 : 00.07.2
       - TBT3 : 00.07.3
       - TCSS_XDCI : 00.0d.1
       - TCSS_DMA1 : 00.0d.3
  - Update Kconfig to conditionally select COMMON_BLOCK_IPU
    only when SOC_INTEL_PANTHERLAKE is selected.
  - Modify existing code to utilize the guards, ensuring that
    Panther Lake-specific devices and configurations are only
    included when appropriate.
  - Add configuration options for MAX_TBT_ROOT_PORTS, MAX_ROOT_PORTS,
    and MAX_PCIE_CLOCK_SRC with Wildcat Lake values.
         MAX_TBT_ROOT_PORTS = 2
         MAX_ROOT_PORTS     = 6
         MAX_PCIE_CLOCK_SRC = 6

References:
- Wildcat Lake Processor EDS Volume 1 (#842271)
- Wildcat Lake External Design Specification (EDS) Volume 2 (#829345)

BUG=b:394208231
TEST=Build Ocelot and verify it compiles without any error.

Change-Id: I89f9d9f043d3ff04c0c65dc9d92a76566e901da9
Signed-off-by: Appukuttan V K <appukuttan.vk@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87514
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Reviewed-by: Usha P <usha.p@intel.com>
---
 src/soc/intel/pantherlake/Kconfig               |  5 ++++-
 src/soc/intel/pantherlake/acpi.c                |  2 ++
 src/soc/intel/pantherlake/chip.c                |  2 ++
 src/soc/intel/pantherlake/elog.c                |  4 ++++
 src/soc/intel/pantherlake/fsp_params.c          | 13 ++++++++++++-
 .../intel/pantherlake/include/soc/pci_devs.h    | 17 ++++++++++++++---
 src/soc/intel/pantherlake/pcie_rp.c             |  4 ++++
 7 files changed, 42 insertions(+), 5 deletions(-)

diff --git a/src/soc/intel/pantherlake/Kconfig b/src/soc/intel/pantherlake/Kconfig
index 412ccda4c3..df14a2fe91 100644
--- a/src/soc/intel/pantherlake/Kconfig
+++ b/src/soc/intel/pantherlake/Kconfig
@@ -72,7 +72,7 @@ config SOC_INTEL_PANTHERLAKE_BASE
 	select SOC_INTEL_COMMON_BLOCK_HECI1_DISABLE_USING_PMC_IPC
 	select SOC_INTEL_COMMON_BLOCK_IOC
 	select SOC_INTEL_COMMON_BLOCK_IOE_P2SB
-	select SOC_INTEL_COMMON_BLOCK_IPU
+	select SOC_INTEL_COMMON_BLOCK_IPU if SOC_INTEL_PANTHERLAKE
 	select SOC_INTEL_COMMON_BLOCK_IRQ
 	select SOC_INTEL_COMMON_BLOCK_ME_SPEC_21
 	select SOC_INTEL_COMMON_BLOCK_MEMINIT
@@ -231,15 +231,18 @@ endif # SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES
 
 config MAX_TBT_ROOT_PORTS
 	int
+	default 2 if SOC_INTEL_WILDCATLAKE
 	default 4
 
 config MAX_ROOT_PORTS
 	int
+	default 6 if SOC_INTEL_WILDCATLAKE
 	default 10 if SOC_INTEL_PANTHERLAKE_H
 	default 12
 
 config MAX_PCIE_CLOCK_SRC
 	int
+	default 6 if SOC_INTEL_WILDCATLAKE
 	default 9
 
 config SMM_TSEG_SIZE
diff --git a/src/soc/intel/pantherlake/acpi.c b/src/soc/intel/pantherlake/acpi.c
index 1c965f411e..0252e1c503 100644
--- a/src/soc/intel/pantherlake/acpi.c
+++ b/src/soc/intel/pantherlake/acpi.c
@@ -214,12 +214,14 @@ static struct min_sleep_state min_pci_sleep_states[] = {
 	{ PCI_DEVFN_PCIE4,	ACPI_DEVICE_SLEEP_D0 },
 	{ PCI_DEVFN_PCIE5,	ACPI_DEVICE_SLEEP_D0 },
 	{ PCI_DEVFN_PCIE6,	ACPI_DEVICE_SLEEP_D0 },
+#if CONFIG(SOC_INTEL_PANTHERLAKE)
 	{ PCI_DEVFN_PCIE7,	ACPI_DEVICE_SLEEP_D0 },
 	{ PCI_DEVFN_PCIE8,	ACPI_DEVICE_SLEEP_D0 },
 	{ PCI_DEVFN_PCIE9,	ACPI_DEVICE_SLEEP_D0 },
 	{ PCI_DEVFN_PCIE10,	ACPI_DEVICE_SLEEP_D0 },
 	{ PCI_DEVFN_PCIE11,	ACPI_DEVICE_SLEEP_D0 },
 	{ PCI_DEVFN_PCIE12,	ACPI_DEVICE_SLEEP_D0 },
+#endif
 	{ PCI_DEVFN_UART0,	ACPI_DEVICE_SLEEP_D3 },
 	{ PCI_DEVFN_UART1,	ACPI_DEVICE_SLEEP_D3 },
 	{ PCI_DEVFN_GSPI0,	ACPI_DEVICE_SLEEP_D3 },
diff --git a/src/soc/intel/pantherlake/chip.c b/src/soc/intel/pantherlake/chip.c
index 5fe2a37043..317fa5fa0e 100644
--- a/src/soc/intel/pantherlake/chip.c
+++ b/src/soc/intel/pantherlake/chip.c
@@ -102,12 +102,14 @@ const char *soc_acpi_name(const struct device *dev)
 	case PCI_DEVFN_PCIE4:		return "RP04";
 	case PCI_DEVFN_PCIE5:		return "RP05";
 	case PCI_DEVFN_PCIE6:		return "RP06";
+#if CONFIG(SOC_INTEL_PANTHERLAKE)
 	case PCI_DEVFN_PCIE7:		return "RP07";
 	case PCI_DEVFN_PCIE8:		return "RP08";
 	case PCI_DEVFN_PCIE9:		return "RP09";
 	case PCI_DEVFN_PCIE10:		return "RP10";
 	case PCI_DEVFN_PCIE11:		return "RP11";
 	case PCI_DEVFN_PCIE12:		return "RP12";
+#endif
 	case PCI_DEVFN_PMC:		return "PMC";
 	case PCI_DEVFN_UART0:		return "UAR0";
 	case PCI_DEVFN_UART1:		return "UAR1";
diff --git a/src/soc/intel/pantherlake/elog.c b/src/soc/intel/pantherlake/elog.c
index 7750058be4..5abf766fc7 100644
--- a/src/soc/intel/pantherlake/elog.c
+++ b/src/soc/intel/pantherlake/elog.c
@@ -36,6 +36,7 @@ static void pch_log_rp_wake_source(void)
 		{ PCI_DEVFN_PCIE4,	ELOG_WAKE_SOURCE_PME_PCIE4 },
 		{ PCI_DEVFN_PCIE5,	ELOG_WAKE_SOURCE_PME_PCIE5 },
 		{ PCI_DEVFN_PCIE6,	ELOG_WAKE_SOURCE_PME_PCIE6 },
+#if CONFIG(SOC_INTEL_PANTHERLAKE)
 		{ PCI_DEVFN_PCIE7,	ELOG_WAKE_SOURCE_PME_PCIE7 },
 		{ PCI_DEVFN_PCIE8,	ELOG_WAKE_SOURCE_PME_PCIE8 },
 		{ PCI_DEVFN_PCIE9,	ELOG_WAKE_SOURCE_PME_PCIE9 },
@@ -43,6 +44,7 @@ static void pch_log_rp_wake_source(void)
 #if CONFIG(SOC_INTEL_PANTHERLAKE_U_H)
 		{ PCI_DEVFN_PCIE11,	ELOG_WAKE_SOURCE_PME_PCIE11 },
 		{ PCI_DEVFN_PCIE12,	ELOG_WAKE_SOURCE_PME_PCIE12 },
+#endif
 #endif
 	};
 
@@ -62,7 +64,9 @@ static void pch_log_pme_internal_wake_source(void)
 		{ PCI_DEVFN_XHCI,	ELOG_WAKE_SOURCE_PME_XHCI },
 		{ PCI_DEVFN_USBOTG,	ELOG_WAKE_SOURCE_PME_XDCI },
 		{ PCI_DEVFN_CNVI_WIFI,	ELOG_WAKE_SOURCE_PME_WIFI },
+#if CONFIG(SOC_INTEL_PANTHERLAKE)
 		{ PCI_DEVFN_TCSS_XDCI,	ELOG_WAKE_SOURCE_PME_TCSS_XDCI },
+#endif
 	};
 	const struct xhci_wake_info xhci_wake_info[] = {
 		{ PCI_DEVFN_XHCI,	ELOG_WAKE_SOURCE_PME_XHCI },
diff --git a/src/soc/intel/pantherlake/fsp_params.c b/src/soc/intel/pantherlake/fsp_params.c
index cac866f39a..32be2852db 100644
--- a/src/soc/intel/pantherlake/fsp_params.c
+++ b/src/soc/intel/pantherlake/fsp_params.c
@@ -119,6 +119,7 @@ static const struct slot_irq_constraints irq_constraints[] = {
 			FIXED_INT_PIRQ(PCI_DEVFN_DPTF, PCI_INT_A, PIRQ_A),
 		},
 	},
+#if CONFIG(SOC_INTEL_PANTHERLAKE)
 	{
 		.slot = PCI_DEV_SLOT_IPU,
 		.fns = {
@@ -127,14 +128,20 @@ static const struct slot_irq_constraints irq_constraints[] = {
 			FIXED_INT_PIRQ(PCI_DEVFN_IPU, PCI_INT_A, PIRQ_A),
 		},
 	},
+#endif
 	{
 		.slot = PCI_DEV_SLOT_PCIE_2,
 		.fns = {
+#if CONFIG(SOC_INTEL_WILDCATLAKE)
+			FIXED_INT_PIRQ(PCI_DEVFN_PCIE5, PCI_INT_A, PIRQ_A),
+			FIXED_INT_PIRQ(PCI_DEVFN_PCIE6, PCI_INT_B, PIRQ_B),
+#else
 			FIXED_INT_PIRQ(PCI_DEVFN_PCIE9, PCI_INT_A, PIRQ_A),
 			FIXED_INT_PIRQ(PCI_DEVFN_PCIE10, PCI_INT_B, PIRQ_B),
 #if CONFIG(SOC_INTEL_PANTHERLAKE_H)
 			FIXED_INT_PIRQ(PCI_DEVFN_PCIE11, PCI_INT_C, PIRQ_C),
 			FIXED_INT_PIRQ(PCI_DEVFN_PCIE12, PCI_INT_D, PIRQ_D),
+#endif
 #endif
 		},
 	},
@@ -143,8 +150,10 @@ static const struct slot_irq_constraints irq_constraints[] = {
 		.fns = {
 			ANY_PIRQ(PCI_DEVFN_TBT0),
 			ANY_PIRQ(PCI_DEVFN_TBT1),
+#if CONFIG(SOC_INTEL_PANTHERLAKE)
 			ANY_PIRQ(PCI_DEVFN_TBT2),
 			ANY_PIRQ(PCI_DEVFN_TBT3),
+#endif
 		},
 	},
 	{
@@ -201,7 +210,7 @@ static const struct slot_irq_constraints irq_constraints[] = {
 			ANY_PIRQ(PCI_DEVFN_CSE_4),
 		},
 	},
-#if CONFIG(SOC_INTEL_PANTHERLAKE_U_H)
+#if (CONFIG(SOC_INTEL_PANTHERLAKE_U_H) || CONFIG(SOC_INTEL_WILDCATLAKE))
 	{
 		.slot = PCI_DEV_SLOT_UFS,
 		.fns = {
@@ -224,10 +233,12 @@ static const struct slot_irq_constraints irq_constraints[] = {
 			FIXED_INT_PIRQ(PCI_DEVFN_PCIE2, PCI_INT_B, PIRQ_B),
 			FIXED_INT_PIRQ(PCI_DEVFN_PCIE3, PCI_INT_C, PIRQ_C),
 			FIXED_INT_PIRQ(PCI_DEVFN_PCIE4, PCI_INT_D, PIRQ_D),
+#if CONFIG(SOC_INTEL_PANTHERLAKE)
 			FIXED_INT_PIRQ(PCI_DEVFN_PCIE5, PCI_INT_A, PIRQ_A),
 			FIXED_INT_PIRQ(PCI_DEVFN_PCIE6, PCI_INT_B, PIRQ_B),
 			FIXED_INT_PIRQ(PCI_DEVFN_PCIE7, PCI_INT_C, PIRQ_C),
 			FIXED_INT_PIRQ(PCI_DEVFN_PCIE8, PCI_INT_D, PIRQ_D),
+#endif
 		},
 	},
 	{
diff --git a/src/soc/intel/pantherlake/include/soc/pci_devs.h b/src/soc/intel/pantherlake/include/soc/pci_devs.h
index a69f4820c8..dc7130cbb5 100644
--- a/src/soc/intel/pantherlake/include/soc/pci_devs.h
+++ b/src/soc/intel/pantherlake/include/soc/pci_devs.h
@@ -33,6 +33,12 @@
 #define  PCI_DEV_IPU		_PCI_DEV(IPU, 0)
 
 #define PCI_DEV_SLOT_PCIE_2	0x06
+#if CONFIG(SOC_INTEL_WILDCATLAKE)
+#define  PCI_DEVFN_PCIE5	_PCI_DEVFN(PCIE_2, 0)
+#define  PCI_DEVFN_PCIE6	_PCI_DEVFN(PCIE_2, 1)
+#define  PCI_DEV_PCIE5		_PCI_DEV(PCIE_2, 0)
+#define  PCI_DEV_PCIE6		_PCI_DEV(PCIE_2, 1)
+#else
 #define  PCI_DEVFN_PCIE9	_PCI_DEVFN(PCIE_2, 0)
 #define  PCI_DEVFN_PCIE10	_PCI_DEVFN(PCIE_2, 1)
 #define  PCI_DEVFN_PCIE11	_PCI_DEVFN(PCIE_2, 2)
@@ -41,6 +47,7 @@
 #define  PCI_DEV_PCIE10		_PCI_DEV(PCIE_2, 1)
 #define  PCI_DEV_PCIE11		_PCI_DEV(PCIE_2, 2)
 #define  PCI_DEV_PCIE12		_PCI_DEV(PCIE_2, 3)
+#endif
 
 #define PCI_DEV_SLOT_TBT	0x07
 #define PCI_DEVFN_TBT(x)	_PCI_DEVFN(TBT, (x))
@@ -48,11 +55,11 @@
 #define  PCI_DEVFN_TBT0		_PCI_DEVFN(TBT, 0)
 #define  PCI_DEVFN_TBT1		_PCI_DEVFN(TBT, 1)
 #define  PCI_DEVFN_TBT2		_PCI_DEVFN(TBT, 2)
-#define  PCI_DEVFN_TBT3         _PCI_DEVFN(TBT, 3)
+#define  PCI_DEVFN_TBT3		_PCI_DEVFN(TBT, 3)
 #define  PCI_DEV_TBT0		_PCI_DEV(TBT, 0)
 #define  PCI_DEV_TBT1		_PCI_DEV(TBT, 1)
 #define  PCI_DEV_TBT2		_PCI_DEV(TBT, 2)
-#define  PCI_DEV_TBT3           _PCI_DEV(TBT, 3)
+#define  PCI_DEV_TBT3		_PCI_DEV(TBT, 3)
 
 #define PCI_DEV_SLOT_TELEMETRY	0x0a
 #define  PCI_DEVFN_TELEMETRY	_PCI_DEVFN(TELEMETRY, 0)
@@ -143,7 +150,7 @@
 #define  PCI_DEV_CSE_3		_PCI_DEV(CSE, 4)
 #define  PCI_DEV_CSE_4		_PCI_DEV(CSE, 5)
 
-#if CONFIG(SOC_INTEL_PANTHERLAKE_U_H)
+#if (CONFIG(SOC_INTEL_PANTHERLAKE_U_H) || CONFIG(SOC_INTEL_WILDCATLAKE))
 #define PCI_DEV_SLOT_UFS	0x17
 #define  PCI_DEVFN_UFS		_PCI_DEVFN(UFS, 0)
 #define  PCI_DEV_UFS		_PCI_DEV(UFS, 0)
@@ -170,19 +177,23 @@
 #define  PCI_DEVFN_PCIE2	_PCI_DEVFN(PCIE_1, 1)
 #define  PCI_DEVFN_PCIE3	_PCI_DEVFN(PCIE_1, 2)
 #define  PCI_DEVFN_PCIE4	_PCI_DEVFN(PCIE_1, 3)
+#if CONFIG(SOC_INTEL_PANTHERLAKE)
 #define  PCI_DEVFN_PCIE5	_PCI_DEVFN(PCIE_1, 4)
 #define  PCI_DEVFN_PCIE6	_PCI_DEVFN(PCIE_1, 5)
 #define  PCI_DEVFN_PCIE7	_PCI_DEVFN(PCIE_1, 6)
 #define  PCI_DEVFN_PCIE8	_PCI_DEVFN(PCIE_1, 7)
+#endif
 
 #define  PCI_DEV_PCIE1		_PCI_DEV(PCIE_1, 0)
 #define  PCI_DEV_PCIE2		_PCI_DEV(PCIE_1, 1)
 #define  PCI_DEV_PCIE3		_PCI_DEV(PCIE_1, 2)
 #define  PCI_DEV_PCIE4		_PCI_DEV(PCIE_1, 3)
+#if CONFIG(SOC_INTEL_PANTHERLAKE)
 #define  PCI_DEV_PCIE5		_PCI_DEV(PCIE_1, 4)
 #define  PCI_DEV_PCIE6		_PCI_DEV(PCIE_1, 5)
 #define  PCI_DEV_PCIE7		_PCI_DEV(PCIE_1, 6)
 #define  PCI_DEV_PCIE8		_PCI_DEV(PCIE_1, 7)
+#endif
 
 #define PCI_DEV_SLOT_SIO2	0x1e
 #define  PCI_DEVFN_UART0	_PCI_DEVFN(SIO2, 0)
diff --git a/src/soc/intel/pantherlake/pcie_rp.c b/src/soc/intel/pantherlake/pcie_rp.c
index 604e7af1b2..cacbab83ad 100644
--- a/src/soc/intel/pantherlake/pcie_rp.c
+++ b/src/soc/intel/pantherlake/pcie_rp.c
@@ -18,7 +18,11 @@ static const struct pcie_rp_group tbt_rp_groups[] = {
 };
 
 static const struct pcie_rp_group ptl_rp_groups[] = {
+#if CONFIG(SOC_INTEL_WILDCATLAKE)
+	{ .slot = PCI_DEV_SLOT_PCIE_1,	.count = 4, .lcap_port_base = 1 },
+#else
 	{ .slot = PCI_DEV_SLOT_PCIE_1,	.count = 8, .lcap_port_base = 1 },
+#endif
 #if CONFIG(SOC_INTEL_PANTHERLAKE_U_H)
 	{ .slot = PCI_DEV_SLOT_PCIE_2,	.count = 4, .lcap_port_base = 1 },
 #else

From f8071719e79d302c817e89e2f4ad105fe106f5da Mon Sep 17 00:00:00 2001
From: Appukuttan V K <appukuttan.vk@intel.com>
Date: Fri, 2 May 2025 15:32:20 +0530
Subject: [PATCH 0915/3886] soc/intel/ptl: Add Wildcat Lake platform reporting

This commit updates the platform reporting logic to include support
for Wildcat Lake SoC.

Key changes:
  - Add Wildcat Lake-specific entries for MCH, PCH, and IGD device
    IDs.

References:
- Wildcat Lake Processor EDS Volume 1 (#842271)
- Wildcat Lake External Design Specification (EDS) Volume 2 (#829345)

BUG=b:394208231
TEST=Build Ocelot and verify it compiles without any error.

Change-Id: Ia4efb173f3ff9247d50bcfa496ed92b211729a3a
Signed-off-by: Appukuttan V K <appukuttan.vk@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87515
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 .../pantherlake/bootblock/report_platform.c   | 36 +++++++++++++++++++
 1 file changed, 36 insertions(+)

diff --git a/src/soc/intel/pantherlake/bootblock/report_platform.c b/src/soc/intel/pantherlake/bootblock/report_platform.c
index 28ec7473af..07e1261916 100644
--- a/src/soc/intel/pantherlake/bootblock/report_platform.c
+++ b/src/soc/intel/pantherlake/bootblock/report_platform.c
@@ -32,6 +32,8 @@ static struct {
 	{ PCI_DID_INTEL_PTL_H_ID_2, "Pantherlake H" },
 	{ PCI_DID_INTEL_PTL_H_ID_3, "Pantherlake H" },
 	{ PCI_DID_INTEL_PTL_H_ID_4, "Pantherlake H" },
+	{ PCI_DID_INTEL_WCL_ID_1, "Wildcatlake" },
+	{ PCI_DID_INTEL_WCL_ID_2, "Wildcatlake" },
 };
 
 static struct {
@@ -102,6 +104,38 @@ static struct {
 	{ PCI_DID_INTEL_PTL_H_ESPI_29, "Pantherlake SOC-H" },
 	{ PCI_DID_INTEL_PTL_H_ESPI_30, "Pantherlake SOC-H" },
 	{ PCI_DID_INTEL_PTL_H_ESPI_31, "Pantherlake SOC-H" },
+	{ PCI_DID_INTEL_WCL_ESPI_0, "Wildcatlake SOC" },
+	{ PCI_DID_INTEL_WCL_ESPI_1, "Wildcatlake SOC" },
+	{ PCI_DID_INTEL_WCL_ESPI_2, "Wildcatlake SOC" },
+	{ PCI_DID_INTEL_WCL_ESPI_3, "Wildcatlake SOC" },
+	{ PCI_DID_INTEL_WCL_ESPI_4, "Wildcatlake SOC" },
+	{ PCI_DID_INTEL_WCL_ESPI_5, "Wildcatlake SOC" },
+	{ PCI_DID_INTEL_WCL_ESPI_6, "Wildcatlake SOC" },
+	{ PCI_DID_INTEL_WCL_ESPI_7, "Wildcatlake SOC" },
+	{ PCI_DID_INTEL_WCL_ESPI_8, "Wildcatlake SOC" },
+	{ PCI_DID_INTEL_WCL_ESPI_9, "Wildcatlake SOC" },
+	{ PCI_DID_INTEL_WCL_ESPI_10, "Wildcatlake SOC" },
+	{ PCI_DID_INTEL_WCL_ESPI_11, "Wildcatlake SOC" },
+	{ PCI_DID_INTEL_WCL_ESPI_12, "Wildcatlake SOC" },
+	{ PCI_DID_INTEL_WCL_ESPI_13, "Wildcatlake SOC" },
+	{ PCI_DID_INTEL_WCL_ESPI_14, "Wildcatlake SOC" },
+	{ PCI_DID_INTEL_WCL_ESPI_15, "Wildcatlake SOC" },
+	{ PCI_DID_INTEL_WCL_ESPI_16, "Wildcatlake SOC" },
+	{ PCI_DID_INTEL_WCL_ESPI_17, "Wildcatlake SOC" },
+	{ PCI_DID_INTEL_WCL_ESPI_18, "Wildcatlake SOC" },
+	{ PCI_DID_INTEL_WCL_ESPI_19, "Wildcatlake SOC" },
+	{ PCI_DID_INTEL_WCL_ESPI_20, "Wildcatlake SOC" },
+	{ PCI_DID_INTEL_WCL_ESPI_21, "Wildcatlake SOC" },
+	{ PCI_DID_INTEL_WCL_ESPI_22, "Wildcatlake SOC" },
+	{ PCI_DID_INTEL_WCL_ESPI_23, "Wildcatlake SOC" },
+	{ PCI_DID_INTEL_WCL_ESPI_24, "Wildcatlake SOC" },
+	{ PCI_DID_INTEL_WCL_ESPI_25, "Wildcatlake SOC" },
+	{ PCI_DID_INTEL_WCL_ESPI_26, "Wildcatlake SOC" },
+	{ PCI_DID_INTEL_WCL_ESPI_27, "Wildcatlake SOC" },
+	{ PCI_DID_INTEL_WCL_ESPI_28, "Wildcatlake SOC" },
+	{ PCI_DID_INTEL_WCL_ESPI_29, "Wildcatlake SOC" },
+	{ PCI_DID_INTEL_WCL_ESPI_30, "Wildcatlake SOC" },
+	{ PCI_DID_INTEL_WCL_ESPI_31, "Wildcatlake SOC" },
 };
 
 static struct {
@@ -112,6 +146,8 @@ static struct {
 	{ PCI_DID_INTEL_PTL_H_GT2_1, "Pantherlake-H GT2" },
 	{ PCI_DID_INTEL_PTL_H_GT2_2, "Pantherlake-H GT2" },
 	{ PCI_DID_INTEL_PTL_H_GT2_3, "Pantherlake-H GT2" },
+	{ PCI_DID_INTEL_WCL_GT2_1, "Wildcatlake GT2" },
+	{ PCI_DID_INTEL_WCL_GT2_2, "Wildcatlake GT2" },
 };
 
 static inline uint8_t get_dev_revision(pci_devfn_t dev)

From 36ac6226ff8855b68741c78fd01f6c066d5f1ef8 Mon Sep 17 00:00:00 2001
From: Nicholas Chin <nic.c3.14@gmail.com>
Date: Sun, 23 Jun 2024 10:39:23 -0600
Subject: [PATCH 0916/3886] util/autoport: Add function to create empty files

As per commit cf4722d317ea ("src/mb: Update unlicensable files with the
CC-PDDC SPDX ID") effectively empty files should use the Creative
Commons Public Domain Dedication and Certification (CC-PDDC) license
header. Add a function to create an empty file and add the CC-PDDC SPDX
header and a comment to change the license if content is added.

The only empty files that autoport currently generates are ec.asl and
superio.asl on non-laptop systems, where NoEC() is used.

Change-Id: I409a6d90d671258e318c26e34a35c238d6fd28c1
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84329
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
---
 util/autoport/ec_none.go |  7 ++-----
 util/autoport/main.go    | 12 ++++++++++--
 2 files changed, 12 insertions(+), 7 deletions(-)

diff --git a/util/autoport/ec_none.go b/util/autoport/ec_none.go
index a1a0df94f0..ceb84a0528 100644
--- a/util/autoport/ec_none.go
+++ b/util/autoport/ec_none.go
@@ -16,9 +16,6 @@ Method(_PTS, 1)
 }
 `)
 
-	si := Create(ctx, "acpi/superio.asl")
-	defer si.Close()
-
-	ec := Create(ctx, "acpi/ec.asl")
-	defer ec.Close()
+	Create_Empty(ctx, "acpi/superio.asl", ASL)
+	Create_Empty(ctx, "acpi/ec.asl", ASL)
 }
diff --git a/util/autoport/main.go b/util/autoport/main.go
index c4f884a985..1246e3277c 100644
--- a/util/autoport/main.go
+++ b/util/autoport/main.go
@@ -120,8 +120,9 @@ var CommentFormatStrings map[Filetype]string = map[Filetype]string {
 type License string
 
 const (
-    GPL2_only License = "GPL-2.0-only"
-    GPL2_or_later     = "GPL-2.0-or-later"
+    CC_PDDC License	= "CC-PDDC"
+    GPL2_only		= "GPL-2.0-only"
+    GPL2_or_later	= "GPL-2.0-or-later"
 )
 
 var KconfigBool map[string]bool = map[string]bool{}
@@ -233,6 +234,13 @@ func Create(ctx Context, name string) *os.File {
 	}
 	return mf
 }
+func Create_Empty(ctx Context, name string, filetype Filetype) {
+	f := Create(ctx, name)
+	defer f.Close()
+	Add_SPDX(f, filetype, CC_PDDC)
+	Add_Comment(f, filetype,
+		"Please update the license if adding licensable material.")
+}
 
 func Add_SPDX(f *os.File, filetype Filetype, license License) {
 	Add_Comment(f, filetype, "SPDX-License-Identifier: " + string(license))

From b1b8b0e8e1d5a9f09401283d0a59d0d68c8e3c6c Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Fri, 4 Apr 2025 13:05:13 +0100
Subject: [PATCH 0917/3886] mb/starlabs/starbook/tgl: Reconfigure PCH Strap
 GPIOs

Configure all strap GPIOs as outputs, rather than some being not
connected. This doesn't change anything, but is more explicit.

Set these all to sample on RSMRST.

Change-Id: I557bfc1339bad169753640c9404813305a16024e
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87172
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
---
 src/mainboard/starlabs/starbook/variants/tgl/gpio.c | 12 ++++++------
 1 file changed, 6 insertions(+), 6 deletions(-)

diff --git a/src/mainboard/starlabs/starbook/variants/tgl/gpio.c b/src/mainboard/starlabs/starbook/variants/tgl/gpio.c
index 0aa6cbe7b4..82d1a21a0e 100644
--- a/src/mainboard/starlabs/starbook/variants/tgl/gpio.c
+++ b/src/mainboard/starlabs/starbook/variants/tgl/gpio.c
@@ -97,15 +97,17 @@ const struct pad_config gpio_table[] = {
 	PAD_CFG_GPO(GPP_B14, 0, RSMRST),				/* Top Swap		[ Disabled / Enabled  ] */
 	PAD_CFG_GPO(GPP_B18, 0, RSMRST),				/* Reboot Support	[ Enabled  / Disabled ] */
 	PAD_CFG_GPO(GPP_C2, 1, RSMRST),					/* TLS Confidentiality	[ Disabled / Enabled  ] */
-	PAD_CFG_GPO(GPP_B23, 0, DEEP),					/* XTAL			[ 38.4Mhz  / 19.2MHz  ] */
-	PAD_CFG_GPO(GPP_C5, 0, RSMRST),					/* eSPI			[ Enabled  / Disabled ] */
+	PAD_CFG_GPO(GPP_B22, 0, RSMRST),				/* eSPI			[ Enabled  / Disabled ] */
 	PAD_CFG_GPO(GPP_E6, 0, RSMRST),					/* JTAG ODT		[ Disabled / Enabled  ] */
-	PAD_CFG_GPO(GPP_E21, 0, RSMRST),				/* TBT LSX #1		[ 1.8V     / 3.3V     ] */
+	PAD_CFG_GPO(GPP_C5, 0, RSMRST),					/* BFX Strap 2 Bit 1	[ Disabled / Enabled  ] */
 	PAD_CFG_GPO(GPP_H0, 0, RSMRST),					/* BFX Strap 2 Bit 2	[ Disabled / Enabled  ] */
 	PAD_CFG_GPO(GPP_H1, 0, RSMRST),					/* BFX Strap 2 Bit 3	[ Disabled / Enabled  ] */
 	PAD_CFG_GPO(GPP_H2, 0, RSMRST),					/* BFX Strap 2 Bit 4	[ Disabled / Enabled  ] */
+	PAD_CFG_GPO(GPP_E21, 0, RSMRST),				/* TBT LSX #1		[ 1,8V     / 3.3V     ] */
 	PAD_CFG_GPO(GPP_F7, 0, RSMRST),					/* MCRO LDO		[ Disabled / Bypass   ] */
 	PAD_CFG_GPO(GPD7, 0, RSMRST),					/* RTC Clock Delay	[ Disabled / 95ms     ] */
+	PAD_CFG_GPO(GPP_B23, 0, DEEP),					/* CPUNSSC		[ 19.2MHz  / 38.4MHz  ] */
+	PAD_CFG_GPO(GPP_F10, 0, DEEP),					/* XTAL Mode		[ Attached / Single   ] */
 
 	PAD_NC(GPD2, NONE),
 	PAD_NC(GPD6, NONE),
@@ -140,8 +142,6 @@ const struct pad_config gpio_table[] = {
 	PAD_NC(GPP_B19, NONE),
 	PAD_NC(GPP_B20, NONE),
 	PAD_NC(GPP_B21, NONE),
-	PAD_NC(GPP_B22, NONE),
-
 	PAD_NC(GPP_C3, NONE),
 	PAD_NC(GPP_C4, NONE),
 	PAD_NC(GPP_C9, NONE),
@@ -198,7 +198,6 @@ const struct pad_config gpio_table[] = {
 	PAD_NC(GPP_F6, NONE),
 	PAD_NC(GPP_F8, NONE),
 	PAD_NC(GPP_F9, NONE),
-	PAD_NC(GPP_F10, NONE),
 	PAD_NC(GPP_F11, NONE),
 	PAD_NC(GPP_F12, NONE),
 	PAD_NC(GPP_F13, NONE),
@@ -213,6 +212,7 @@ const struct pad_config gpio_table[] = {
 	PAD_NC(GPP_F22, NONE),
 	PAD_NC(GPP_F23, NONE),
 
+	/* H3:	Not Connected			*/
 	PAD_NC(GPP_H3, NONE),
 	PAD_NC(GPP_H4, NONE),
 	PAD_NC(GPP_H5, NONE),

From 663dbd462a82324356d59b5b164708ebe14d72da Mon Sep 17 00:00:00 2001
From: Nicolas Kochlowski <nickkochlowski@gmail.com>
Date: Fri, 20 Dec 2024 13:54:58 -0300
Subject: [PATCH 0918/3886] soc/amd/phoenix: Remove outdated TODO comments

Delete the "TODO: Update for Phoenix" comment from files that have
already been updated in the previous chained patches (CB:85631,
CB:85632, CB:85633).

Change-Id: I137dbba5094ae8cbf842b45d6137c5b0528e5413
Signed-off-by: Nicolas Kochlowski <nickkochlowski@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85719
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ana Carolina Cabral <ana.cpmelo95@gmail.com>
---
 src/mainboard/amd/birman/devicetree_phoenix_opensil.cb | 2 --
 src/soc/amd/phoenix/Kconfig                            | 1 -
 src/soc/amd/phoenix/Makefile.mk                        | 1 -
 src/soc/amd/phoenix/acpi.c                             | 1 -
 src/soc/amd/phoenix/chip.h                             | 2 --
 5 files changed, 7 deletions(-)

diff --git a/src/mainboard/amd/birman/devicetree_phoenix_opensil.cb b/src/mainboard/amd/birman/devicetree_phoenix_opensil.cb
index 9916931545..75b50a199d 100644
--- a/src/mainboard/amd/birman/devicetree_phoenix_opensil.cb
+++ b/src/mainboard/amd/birman/devicetree_phoenix_opensil.cb
@@ -1,7 +1,5 @@
 # SPDX-License-Identifier: GPL-2.0-only
 
-# TODO: Update for birman
-
 chip soc/amd/phoenix
 	register "common_config.espi_config" = "{
 		.std_io_decode_bitmap = ESPI_DECODE_IO_0x80_EN | ESPI_DECODE_IO_0X2E_0X2F_EN | ESPI_DECODE_IO_0X60_0X64_EN,
diff --git a/src/soc/amd/phoenix/Kconfig b/src/soc/amd/phoenix/Kconfig
index 995b1cc535..ac227b9f6f 100644
--- a/src/soc/amd/phoenix/Kconfig
+++ b/src/soc/amd/phoenix/Kconfig
@@ -1,7 +1,6 @@
 # SPDX-License-Identifier: GPL-2.0-only
 
 # TODO: Evaluate what can be moved to a common directory
-# TODO: Update for Phoenix
 
 config SOC_AMD_PHOENIX_BASE
 	bool
diff --git a/src/soc/amd/phoenix/Makefile.mk b/src/soc/amd/phoenix/Makefile.mk
index 878ebe7bb7..68cc935f75 100644
--- a/src/soc/amd/phoenix/Makefile.mk
+++ b/src/soc/amd/phoenix/Makefile.mk
@@ -1,7 +1,6 @@
 # SPDX-License-Identifier: BSD-3-Clause
 
 # TODO: Move as much as possible to common
-# TODO: Update for Phoenix
 
 ifeq ($(CONFIG_SOC_AMD_PHOENIX_BASE),y)
 
diff --git a/src/soc/amd/phoenix/acpi.c b/src/soc/amd/phoenix/acpi.c
index 1475b6166a..0f0ec26dae 100644
--- a/src/soc/amd/phoenix/acpi.c
+++ b/src/soc/amd/phoenix/acpi.c
@@ -1,6 +1,5 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
-/* TODO: Update for Phoenix */
 /* TODO: See what can be made common */
 
 /* ACPI - create the Fixed ACPI Description Tables (FADT) */
diff --git a/src/soc/amd/phoenix/chip.h b/src/soc/amd/phoenix/chip.h
index eabd44518e..fb0ef0f78a 100644
--- a/src/soc/amd/phoenix/chip.h
+++ b/src/soc/amd/phoenix/chip.h
@@ -1,7 +1,5 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
-/* TODO: Update for Phoenix */
-
 #ifndef PHOENIX_CHIP_H
 #define PHOENIX_CHIP_H
 

From 2e27ceed6778fac0ecdb67af589ee0c57b7716cb Mon Sep 17 00:00:00 2001
From: Jon Murphy <jpmurphy@google.com>
Date: Tue, 11 Mar 2025 13:23:20 -0600
Subject: [PATCH 0919/3886] mb/google/volteer/var/elemi: Check FP presence
 against SKU ID

Add/update FP enable/disable based on SKU ID. This is meant
to resolve a UMA issue with devices that had the FPMCU populated on
non-fp devices.  Since the FPMCU is present, and the firmware enables
the power GPIO's based on variant, not SKU, the devices were reporting
data on fingerprint errantly.  Specify the SKUs which should not have a
FP sensor and default to true to maintain the legacy behavior for
undefined devices and limit risk.  Variants which do not have FP SKUs
will be unaffected.

BUG=b:354769653
TEST=Flash on device, test FP.
Disable test SKU, flash on device, test FP.

To test, run `ectool --name=cros_fp version` in the shell
When enabled, the fpmcu fw version should be displayed.
When disabled, an error should be displayed because the fpmcu
is inaccessible.

Change-Id: I9811721d0b345614e10ac27946ad45b6ec6f7494
Signed-off-by: Jon Murphy <jpmurphy@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86826
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
---
 .../google/volteer/variants/elemi/ramstage.c  | 34 +++++++++++++------
 1 file changed, 24 insertions(+), 10 deletions(-)

diff --git a/src/mainboard/google/volteer/variants/elemi/ramstage.c b/src/mainboard/google/volteer/variants/elemi/ramstage.c
index f7a174d888..16261b7d45 100644
--- a/src/mainboard/google/volteer/variants/elemi/ramstage.c
+++ b/src/mainboard/google/volteer/variants/elemi/ramstage.c
@@ -3,17 +3,31 @@
 #include <delay.h>
 #include <gpio.h>
 #include <baseboard/variants.h>
+#include <ec/google/chromeec/ec.h>
 
 void variant_ramstage_init(void)
 {
-	/*
-	 * Assert FPMCU reset and enable power to FPMCU,
-	 * wait for power rail to stabilize,
-	 * and then deassert FPMCU reset.
-	 * Waiting for the power rail to stabilize can take a while.
-	 */
-	gpio_output(GPP_C23, 0);
-	gpio_output(GPP_A21, 1);
-	mdelay(1);
-	gpio_output(GPP_C23, 1);
+	uint32_t sku_id = google_chromeec_get_board_sku();
+
+	switch (sku_id) {
+	case 102:
+	case 104:
+	case 107:
+	case 109:
+	case 115:
+		/*
+		 * Assert FPMCU reset and enable power to FPMCU,
+		 * wait for power rail to stabilize,
+		 * and then deassert FPMCU reset.
+		 * Waiting for the power rail to stabilize can take a while.
+		 */
+		gpio_output(GPP_C23, 0);
+		gpio_output(GPP_A21, 1);
+		mdelay(1);
+		gpio_output(GPP_C23, 1);
+		break;
+	default:
+		/* SKU does not have FP Sensor, do not enable FPMCU */
+		break;
+	}
 }

From 245cba6795c0c80d8c0b08b7273f2bf138d38dbb Mon Sep 17 00:00:00 2001
From: Patrick Rudolph <patrick.rudolph@9elements.com>
Date: Tue, 8 Apr 2025 12:59:35 +0200
Subject: [PATCH 0920/3886] cpu/x86/smm: Add support for exception handling

Add an exception handler to SMM to debug crashes when a serial
console is enabled and DEBUG_SMI is set. This allows for narrowing
down issues faster than letting the machine triple fault.

Change-Id: I2ccaf8d23d508d773ce56912983884ad6832ede6
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87208
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
---
 src/arch/x86/exception.c             | 2 ++
 src/cpu/x86/smm/smm_module_handler.c | 4 ++++
 2 files changed, 6 insertions(+)

diff --git a/src/arch/x86/exception.c b/src/arch/x86/exception.c
index 224f0e1d41..e21cfa6de5 100644
--- a/src/arch/x86/exception.c
+++ b/src/arch/x86/exception.c
@@ -665,6 +665,8 @@ asmlinkage void exception_init(void)
 
 	load_idt(idt, sizeof(idt));
 
+#if !ENV_SMM
 	null_breakpoint_init();
 	stack_canary_breakpoint_init();
+#endif
 }
diff --git a/src/cpu/x86/smm/smm_module_handler.c b/src/cpu/x86/smm/smm_module_handler.c
index d25b5f47cf..d9f64204d6 100644
--- a/src/cpu/x86/smm/smm_module_handler.c
+++ b/src/cpu/x86/smm/smm_module_handler.c
@@ -1,6 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
 #include <arch/io.h>
+#include <arch/exception.h>
 #include <commonlib/region.h>
 #include <console/cbmem_console.h>
 #include <console/console.h>
@@ -169,6 +170,9 @@ asmlinkage void smm_handler_start(void *arg)
 
 	printk(BIOS_SPEW, "\nSMI# #%d\n", cpu);
 
+	if (CONFIG(DEBUG_SMI) && CONFIG(CONSOLE_SERIAL))
+		exception_init();
+
 	/* Allow drivers to initialize variables in SMM context. */
 	if (do_driver_init) {
 #if CONFIG(SPI_FLASH_SMM)

From 3cc728110d05a745c2c3cd18c82b91fe10ad4754 Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Wed, 30 Apr 2025 12:47:38 -0500
Subject: [PATCH 0921/3886] soc/intel/alderlake: Hook up S0ix setting to option
 API

Hook up the s0ix_enable setting to the option API, so it can be changed
at runtime without recompilation. Default to the value set by the
mainboard.

Change-Id: I8f55bb7b31936c098da64f65b76965a09981ff73
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87498
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-by: Jayvik Desai <jayvik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/soc/intel/alderlake/fsp_params.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/src/soc/intel/alderlake/fsp_params.c b/src/soc/intel/alderlake/fsp_params.c
index 380f40ba60..022b41e08a 100644
--- a/src/soc/intel/alderlake/fsp_params.c
+++ b/src/soc/intel/alderlake/fsp_params.c
@@ -1249,6 +1249,9 @@ static void soc_silicon_init_params(FSP_S_CONFIG *s_cfg,
 	/* Override settings per board if required. */
 	mainboard_update_soc_chip_config(config);
 
+	/* Runtime configuration of S0ix */
+	config->s0ix_enable = get_uint_option("s0ix_enable", config->s0ix_enable);
+
 	void (*const fill_fsps_params[])(FSP_S_CONFIG *s_cfg,
 			const struct soc_intel_alderlake_config *config) = {
 		fill_fsps_lpss_params,

From 55afbe250d3174f2f58bf8b28e323f6fd230351b Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Wed, 30 Apr 2025 12:48:38 -0500
Subject: [PATCH 0922/3886] soc/intel/elkhartlake: Hook up S0ix setting to
 option API
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Hook up the s0ix_enable setting to the option API, so it can be changed
at runtime without recompilation. Default to the value set by the
mainboard.

Change-Id: I2d2f5c1587bd86c8fee634a49e1ec989c2bef783
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87499
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/soc/intel/elkhartlake/fsp_params.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/src/soc/intel/elkhartlake/fsp_params.c b/src/soc/intel/elkhartlake/fsp_params.c
index 2f2e7408c4..082acaf7ae 100644
--- a/src/soc/intel/elkhartlake/fsp_params.c
+++ b/src/soc/intel/elkhartlake/fsp_params.c
@@ -505,6 +505,9 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
 
 	/* Override/Fill FSP Silicon Param for mainboard */
 	mainboard_silicon_init_params(params);
+
+	/* Runtime configuration of S0ix */
+	config->s0ix_enable = get_uint_option("s0ix_enable", config->s0ix_enable);
 }
 
 /* Mainboard GPIO Configuration */

From 514ad949e3a0f487abee95ab61a51425b09a8325 Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Wed, 30 Apr 2025 12:49:05 -0500
Subject: [PATCH 0923/3886] soc/intel/jasperlake: Hook up S0ix setting to
 option API
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Hook up the s0ix_enable setting to the option API, so it can be changed
at runtime without recompilation. Default to the value set by the
mainboard.

Change-Id: Id35705304e872395ce88617c83d9edecb03b02a1
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87500
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
---
 src/soc/intel/jasperlake/fsp_params.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/src/soc/intel/jasperlake/fsp_params.c b/src/soc/intel/jasperlake/fsp_params.c
index 3bad533424..b01610d2fe 100644
--- a/src/soc/intel/jasperlake/fsp_params.c
+++ b/src/soc/intel/jasperlake/fsp_params.c
@@ -253,6 +253,9 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
 
 	/* Override/Fill FSP Silicon Param for mainboard */
 	mainboard_silicon_init_params(params);
+
+	/* Runtime configuration of S0ix */
+	config->s0ix_enable = get_uint_option("s0ix_enable", config->s0ix_enable);
 }
 
 /* Mainboard GPIO Configuration */

From ba4b26c4fc94501487f01b1b0827ed4404d7e421 Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Wed, 30 Apr 2025 12:49:23 -0500
Subject: [PATCH 0924/3886] soc/intel/meteorlake: Hook up S0ix setting to
 option API
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Hook up the s0ix_enable setting to the option API, so it can be changed
at runtime without recompilation. Default to the value set by the
mainboard.

Change-Id: Id9e75020ab359bf94c75ffc1aaaef7af83d4c9c6
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87501
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/soc/intel/meteorlake/fsp_params.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/src/soc/intel/meteorlake/fsp_params.c b/src/soc/intel/meteorlake/fsp_params.c
index ad85702dbe..a14d385ecf 100644
--- a/src/soc/intel/meteorlake/fsp_params.c
+++ b/src/soc/intel/meteorlake/fsp_params.c
@@ -784,6 +784,9 @@ static void soc_silicon_init_params(FSP_S_CONFIG *s_cfg,
 	/* Override settings per board if required. */
 	mainboard_update_soc_chip_config(config);
 
+	/* Runtime configuration of S0ix */
+	config->s0ix_enable = get_uint_option("s0ix_enable", config->s0ix_enable);
+
 	 void (*fill_fsps_params[])(FSP_S_CONFIG *s_cfg,
 			const struct soc_intel_meteorlake_config *config) = {
 		fill_fsps_lpss_params,

From 1e7e4e943fa4642042b8e269fc0ec20a5eb6cdb0 Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Wed, 30 Apr 2025 16:40:07 -0500
Subject: [PATCH 0925/3886] soc/intel/tigerlake: Hook up S0ix setting to option
 API

Hook up the s0ix_enable setting to the option API, so it can be changed
at runtime without recompilation. Default to the value set by the
mainboard.

Change-Id: I6c05212eaf004ea74b7fd3fa92cbaa314474b7e9
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87503
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
---
 src/soc/intel/tigerlake/fsp_params.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/src/soc/intel/tigerlake/fsp_params.c b/src/soc/intel/tigerlake/fsp_params.c
index c3400b45c9..35562d1a69 100644
--- a/src/soc/intel/tigerlake/fsp_params.c
+++ b/src/soc/intel/tigerlake/fsp_params.c
@@ -682,6 +682,9 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
 	params->SiSkipSsidProgramming = 0;
 
 	mainboard_silicon_init_params(params);
+
+	/* Runtime configuration of S0ix */
+	config->s0ix_enable = get_uint_option("s0ix_enable", config->s0ix_enable);
 }
 
 /*

From a6be271e63f33a1e19fdbe18ccc7bbb8b35c9bdf Mon Sep 17 00:00:00 2001
From: Patrick Rudolph <patrick.rudolph@9elements.com>
Date: Thu, 10 Apr 2025 08:51:55 +0200
Subject: [PATCH 0926/3886] arch/x86: Unify GDT entries

Currently there are 3 GDTs (Global Descriptor Tables) being used on x86:
- preRAM (gdt_init.S)
- SMM (smm_stub.S)
- RAM (c_start.S)

They have different layouts and thus different offsets for the segments
being used in assembly code. Stop using different GDT segments and
ensure that for ROM (preRAM + SMM) and RAM (ramstage) the segments
match. RAM will have additional entries, not found in pre RAM GDT,
but the segments for protected mode and 64-bit mode now match in
all stages.

This allows to use the same defines in all stages. It also drops the
need to know in which stage the code is compiled and it's no longer
necessary to switch the code segment between stages.

While at it fix the comments in the ramstage GDT and drop unused
declarations from header files, always set the accessed bit and drop
GDT_CODE_ACPI_SEG.

Change-Id: I208496e6e4cc82833636f4f42503b44b0d702b9e
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87255
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
---
 src/arch/x86/c_start.S                    | 71 ++++++++++-------------
 src/arch/x86/include/arch/ram_segs.h      | 14 -----
 src/arch/x86/include/arch/rom_segs.h      | 17 ------
 src/arch/x86/wakeup.S                     |  8 +--
 src/cpu/x86/64bit/entry64.inc             | 12 +---
 src/cpu/x86/64bit/exit32.inc              | 14 +----
 src/cpu/x86/entry16.S                     |  4 +-
 src/cpu/x86/entry32.S                     |  4 +-
 src/cpu/x86/sipi_vector.S                 |  6 +-
 src/cpu/x86/smm/smm_stub.S                |  6 +-
 src/device/oprom/realmode/x86_asm.S       | 30 +++++-----
 src/include/cpu/x86/gdt.h                 | 20 +++++--
 src/security/intel/stm/StmPlatformSmm.c   | 12 ++--
 src/security/intel/txt/getsec_enteraccs.S |  6 +-
 14 files changed, 89 insertions(+), 135 deletions(-)
 delete mode 100644 src/arch/x86/include/arch/ram_segs.h
 delete mode 100644 src/arch/x86/include/arch/rom_segs.h

diff --git a/src/arch/x86/c_start.S b/src/arch/x86/c_start.S
index fd61cab44d..acd26a41be 100644
--- a/src/arch/x86/c_start.S
+++ b/src/arch/x86/c_start.S
@@ -1,7 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
+#include <cpu/x86/gdt.h>
 #include <cpu/x86/post_code.h>
-#include <arch/ram_segs.h>
 
 /* Place the stack in the bss section. It's not necessary to define it in
  * the linker script. */
@@ -30,9 +30,9 @@ _start:
 	lgdt	(%rax)
 #else
 	lgdt	%cs:gdtaddr
-	ljmp	$RAM_CODE_SEG, $1f
+	ljmp	$GDT_CODE_SEG, $1f
 #endif
-1:	movl	$RAM_DATA_SEG, %eax
+1:	movl	$GDT_DATA_SEG, %eax
 	movl	%eax, %ds
 	movl	%eax, %es
 	movl	%eax, %ss
@@ -40,7 +40,7 @@ _start:
 	movl	%eax, %fs
 	movl	%eax, %gs /* Will be used for cpu_info */
 #if ENV_X86_64
-	mov	$RAM_CODE_SEG64, %ecx
+	mov	$GDT_CODE_SEG64, %ecx
 	call	SetCodeSelector
 #endif
 
@@ -152,46 +152,44 @@ gdtaddr:
 
 	.data
 
-	/* This is the gdt for GCC part of coreboot.
+	/*
+	 * This is the gdt for coreboot's ramstage.
 	 * It is different from the gdt in ASM part of coreboot
 	 * which is defined in gdt_init.S
 	 *
 	 * When the machine is initially started, we use a very simple
 	 * gdt from ROM (that in gdt_init.S) which only contains those
-	 * entries we need for protected mode.
+	 * entries we need for protected mode and long mode.
 	 *
 	 * When we're executing code from RAM, we want to do more complex
 	 * stuff, like initializing PCI option ROMs in real mode, or doing
-	 * a resume from a suspend to RAM.
+	 * a resume from a suspend to RAM, which happens in real mode.
+	 *
+	 * Keep in sync with 'cpu/x86/gdt.h'.
 	 */
 gdt:
 	/* selgdt 0, unused */
 	.word	0x0000, 0x0000		/* dummy */
 	.byte	0x00, 0x00, 0x00, 0x00
 
-	/* selgdt 8, unused */
-	.word	0x0000, 0x0000		/* dummy */
-	.byte	0x00, 0x00, 0x00, 0x00
-
-	/* selgdt 0x10, flat code segment */
+	/* selgdt 0x08, flat code segment */
 	.word	0xffff, 0x0000
-	.byte	0x00, 0x9b, 0xcf, 0x00 /* G=1 and 0x0f, So we get 4Gbytes for
-					* limit
-					*/
+	.byte	0x00, 0x9b, 0xcf, 0x00 /* G=1 and 0x0f, So we get 4Gbytes
+					  for limit */
 
-	/* selgdt 0x18, flat data segment */
+	/* selgdt 0x10, flat data segment */
 	.word	0xffff, 0x0000
-#if ENV_X86_64
-	.byte	0x00, 0x92, 0xcf, 0x00
-#else
 	.byte	0x00, 0x93, 0xcf, 0x00
-#endif
 
-	/* selgdt 0x20, unused */
-	.word	0x0000, 0x0000		/* dummy */
-	.byte	0x00, 0x00, 0x00, 0x00
+	/* selgdt 0x18, flat code segment (64-bit) */
+	.word   0xffff, 0x0000
+	.byte   0x00, 0x9b, 0xaf, 0x00
 
-	/* The next two entries are used for executing VGA option ROMs */
+	/* gdt selector 0x20 tss segment, used by STM */
+	.word   0xffff, 0x0000
+	.byte   0x00, 0x8b, 0x80, 0x00
+
+	/* The next two entries are used for executing ACPI S3 RESUME and VGA option ROMs */
 
 	/* selgdt 0x28 16 bit 64k code at 0x00000000 */
 	.word	0xffff, 0x0000
@@ -201,34 +199,25 @@ gdt:
 	.word	0xffff, 0x0000
 	.byte	0, 0x92, 0, 0
 
-	/* The next two entries are used for ACPI S3 RESUME */
+	/* The next entry is used for VGA option ROMs. See x86_asm.S */
 
-	/* selgdt 0x38, flat data segment 16 bit */
-	.word	0x0000, 0x0000		/* dummy */
-	.byte	0x00, 0x93, 0x8f, 0x00 /* G=1 and 0x0f, So we get 4Gbytes for
-					* limit
-					*/
-
-	/* selgdt 0x40, flat code segment 16 bit */
+	/*
+	 * selgdt 0x38, flat code segment 16 bits
+	 *
+	 * FIXME: It's only used in %ds (therefore used like a data segment).
+	 *        The PCI Specification doesn't enforce this.
+	 *        Is this a workaround for broken Option ROMs?
+	 */
 	.word	0xffff, 0x0000
 	.byte	0x00, 0x9b, 0x8f, 0x00 /* G=1 and 0x0f, So we get 4Gbytes for
 					* limit
 					*/
 
-#if ENV_X86_64
-	/* selgdt 0x48, flat x64 code segment */
-	.word	0xffff, 0x0000
-	.byte	0x00, 0x9b, 0xaf, 0x00
-#endif
 per_cpu_segment_descriptors:
 	.rept CONFIG_MAX_CPUS
 	/* flat data segment */
 	.word	0xffff, 0x0000
-#if ENV_X86_64
-	.byte	0x00, 0x92, 0xcf, 0x00
-#else
 	.byte	0x00, 0x93, 0xcf, 0x00
-#endif
 	.endr
 gdt_end:
 
diff --git a/src/arch/x86/include/arch/ram_segs.h b/src/arch/x86/include/arch/ram_segs.h
deleted file mode 100644
index 3f92a1f680..0000000000
--- a/src/arch/x86/include/arch/ram_segs.h
+++ /dev/null
@@ -1,14 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#ifndef RAM_SEGS_H
-#define RAM_SEGS_H
-
-#define RAM_CODE_SEG            0x10
-#define RAM_DATA_SEG            0x18
-#define RAM_CODE16_SEG          0x28
-#define RAM_DATA16_SEG          0x30
-#define RAM_CODE_ACPI_SEG       0x38
-#define RAM_DATA_ACPI_SEG       0x40
-#define RAM_CODE_SEG64          0x48
-
-#endif /* RAM_SEGS_H */
diff --git a/src/arch/x86/include/arch/rom_segs.h b/src/arch/x86/include/arch/rom_segs.h
deleted file mode 100644
index a7e31d2951..0000000000
--- a/src/arch/x86/include/arch/rom_segs.h
+++ /dev/null
@@ -1,17 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#ifndef ROM_SEGS_H
-#define ROM_SEGS_H
-
-#define ROM_CODE_SEG 0x08
-#define ROM_DATA_SEG 0x10
-#define ROM_CODE_SEG64 0x18
-
-/*
- * This define is placed here to make sure future romstage programmers
- * know about it.
- * It is used for STM setup code.
- */
-#define SMM_TASK_STATE_SEG 0x20
-
-#endif /* ROM_SEGS_H */
diff --git a/src/arch/x86/wakeup.S b/src/arch/x86/wakeup.S
index 7bff006d14..1afc311735 100644
--- a/src/arch/x86/wakeup.S
+++ b/src/arch/x86/wakeup.S
@@ -1,6 +1,6 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
-#include <arch/ram_segs.h>
+#include <cpu/x86/gdt.h>
 
 #define WAKEUP_BASE		0x600
 #define RELOCATED(x)	(x - __wakeup + WAKEUP_BASE)
@@ -31,7 +31,7 @@ __wakeup:
 	add	$8, %rax
 	push	%rax
 	pushfq
-	push	$RAM_CODE_SEG
+	push	$GDT_CODE_SEG
 	lea	3(%rip), %rax
 	push	%rax
 	iretq
@@ -60,7 +60,7 @@ __wakeup:
 	movw	%ax, (__wakeup_segment)
 
 	/* Activate the right segment descriptor real mode. */
-	ljmp	$RAM_CODE16_SEG, $RELOCATED(1f)
+	ljmp	$GDT_CODE16_SEG, $RELOCATED(1f)
 1:
 .code16
 	/* 16 bit code from here on... */
@@ -70,7 +70,7 @@ __wakeup:
 	 * configurations (limits, writability, etc.) once
 	 * protected mode is turned off.
 	 */
-	mov	$RAM_DATA16_SEG, %ax
+	mov	$GDT_DATA16_SEG, %ax
 	mov	%ax, %ds
 	mov	%ax, %es
 	mov	%ax, %fs
diff --git a/src/cpu/x86/64bit/entry64.inc b/src/cpu/x86/64bit/entry64.inc
index 52da6037d5..a9f7ba49a8 100644
--- a/src/cpu/x86/64bit/entry64.inc
+++ b/src/cpu/x86/64bit/entry64.inc
@@ -17,12 +17,8 @@
 #endif
 #endif
 
+#include <cpu/x86/gdt.h>
 #include <cpu/x86/msr.h>
-#if defined(__RAMSTAGE__)
-#include <arch/ram_segs.h>
-#else
-#include <arch/rom_segs.h>
-#endif
 
 .macro setup_longmode page_table
 	/* Get page table address */
@@ -48,12 +44,8 @@
 	movl	%eax, %cr0
 
 	/* use long jump to switch to 64-bit code segment */
-#if defined(__RAMSTAGE__)
-	ljmp $RAM_CODE_SEG64, $jmp_addr\@
-#else
-	ljmp $ROM_CODE_SEG64, $jmp_addr\@
+	ljmp $GDT_CODE_SEG64, $jmp_addr\@
 
-#endif
 .code64
 jmp_addr\@:
 .endm
diff --git a/src/cpu/x86/64bit/exit32.inc b/src/cpu/x86/64bit/exit32.inc
index 3ac86a9df1..a3d215e785 100644
--- a/src/cpu/x86/64bit/exit32.inc
+++ b/src/cpu/x86/64bit/exit32.inc
@@ -10,17 +10,9 @@
  */
 .code64
 
+#include <cpu/x86/gdt.h>
 #include <cpu/x86/msr.h>
 #include <cpu/x86/cr.h>
-#if defined(__RAMSTAGE__)
-#include <arch/ram_segs.h>
-#define CODE_SEG RAM_CODE_SEG
-#define DATA_SEG RAM_DATA_SEG
-#else
-#include <arch/rom_segs.h>
-#define CODE_SEG ROM_CODE_SEG
-#define DATA_SEG ROM_DATA_SEG
-#endif
 
 drop_longmode:
 #if !ENV_CACHE_AS_RAM
@@ -28,7 +20,7 @@ drop_longmode:
 	wbinvd
 #endif
 	/* Set  32-bit code segment and ss */
-	mov	$CODE_SEG, %rcx
+	mov	$GDT_CODE_SEG, %rcx
 	/* SetCodeSelector32 will drop us to protected mode on return */
 	call	SetCodeSelector32
 
@@ -63,7 +55,7 @@ __longmode_compatibility:
 	/* Running in 32-bit compatibility mode */
 
 	/* Use flat data segment */
-	movl	$DATA_SEG, %eax
+	movl	$GDT_DATA_SEG, %eax
 	movl	%eax, %ds
 	movl	%eax, %es
 	movl	%eax, %ss
diff --git a/src/cpu/x86/entry16.S b/src/cpu/x86/entry16.S
index ff4f1a26d0..b19ffa5d6a 100644
--- a/src/cpu/x86/entry16.S
+++ b/src/cpu/x86/entry16.S
@@ -27,7 +27,7 @@
 /* Start code to put an i386 or later processor into 32-bit protected mode.
  */
 
-#include <arch/rom_segs.h>
+#include <cpu/x86/gdt.h>
 #include <cpu/x86/post_code.h>
 
 .section .init._start, "ax", @progbits
@@ -136,7 +136,7 @@ _start16bit:
 	movl	%ebp, %eax
 
 	/* Now that we are in protected mode jump to a 32 bit code segment. */
-	ljmpl	$ROM_CODE_SEG, $bootblock_protected_mode_entry
+	ljmpl	$GDT_CODE_SEG, $bootblock_protected_mode_entry
 
 	/**
 	 * The gdt is defined in gdt_init.S, it has a 4 Gb code segment
diff --git a/src/cpu/x86/entry32.S b/src/cpu/x86/entry32.S
index 5c29581090..d013cbaf60 100644
--- a/src/cpu/x86/entry32.S
+++ b/src/cpu/x86/entry32.S
@@ -11,7 +11,7 @@
  *
  */
 
-#include <arch/rom_segs.h>
+#include <cpu/x86/gdt.h>
 #include <cpu/x86/cr.h>
 #include <cpu/x86/post_code.h>
 
@@ -33,7 +33,7 @@ bootblock_protected_mode_entry:
 
 	post_code(POSTCODE_ENTER_PROTECTED_MODE)
 
-	movw	$ROM_DATA_SEG, %ax
+	movw	$GDT_DATA_SEG, %ax
 	movw	%ax, %ds
 	movw	%ax, %es
 	movw	%ax, %ss
diff --git a/src/cpu/x86/sipi_vector.S b/src/cpu/x86/sipi_vector.S
index b7d700fb39..6057282d76 100644
--- a/src/cpu/x86/sipi_vector.S
+++ b/src/cpu/x86/sipi_vector.S
@@ -1,9 +1,9 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
 #include <cpu/x86/cr.h>
+#include <cpu/x86/gdt.h>
 #include <cpu/amd/mtrr.h>
 #include <cpu/x86/msr.h>
-#include <arch/ram_segs.h>
 
 #define __RAMSTAGE__
 #include <cpu/x86/64bit/entry64.inc>
@@ -77,10 +77,10 @@ _start:
 	orl	$CR0_SET_FLAGS, %eax
 	movl	%eax, %cr0
 
-	ljmpl	$RAM_CODE_SEG, $1f
+	ljmpl	$GDT_CODE_SEG, $1f
 1:
 	.code32
-	movw	$RAM_DATA_SEG, %ax
+	movw	$GDT_DATA_SEG, %ax
 	movw	%ax, %ds
 	movw	%ax, %es
 	movw	%ax, %ss
diff --git a/src/cpu/x86/smm/smm_stub.S b/src/cpu/x86/smm/smm_stub.S
index ae8e047f4e..c7a55f6ea6 100644
--- a/src/cpu/x86/smm/smm_stub.S
+++ b/src/cpu/x86/smm/smm_stub.S
@@ -9,8 +9,8 @@
  * found in smm.h.
  */
 
-#include <arch/rom_segs.h>
 #include <cpu/x86/cr.h>
+#include <cpu/x86/gdt.h>
 #include <cpu/x86/msr.h>
 #include <cpu/x86/lapic_def.h>
 #include <cpu/x86/64bit/entry64.inc>
@@ -94,7 +94,7 @@ untampered_lapic:
 	movl	%eax, %cr0
 
 	/* Enable protected mode */
-	ljmpl	$ROM_CODE_SEG, $smm_trampoline32
+	ljmpl	$GDT_CODE_SEG, $smm_trampoline32
 
 .align 4
 smm_relocate_gdt:
@@ -125,7 +125,7 @@ smm_relocate_gdt_end:
 .global smm_trampoline32
 smm_trampoline32:
 	/* Use flat data segment */
-	movw	$ROM_DATA_SEG, %ax
+	movw	$GDT_DATA_SEG, %ax
 	movw	%ax, %ds
 	movw	%ax, %es
 	movw	%ax, %ss
diff --git a/src/device/oprom/realmode/x86_asm.S b/src/device/oprom/realmode/x86_asm.S
index ff33c0f4ba..39c504bad7 100644
--- a/src/device/oprom/realmode/x86_asm.S
+++ b/src/device/oprom/realmode/x86_asm.S
@@ -3,7 +3,7 @@
 #define REALMODE_BASE		0x600
 #define RELOCATED(x)	(x - __realmode_code + REALMODE_BASE)
 
-#include <arch/ram_segs.h>
+#include <cpu/x86/gdt.h>
 
 /* CR0 bits */
 #define PE		(1 << 0)
@@ -97,7 +97,7 @@ __realmode_call:
 	movl	%eax, __registers + 20 /* edi */
 
 	/* Activate the right segment descriptor real mode. */
-	ljmp	$RAM_CODE16_SEG, $RELOCATED(1f)
+	ljmp	$GDT_CODE16_SEG, $RELOCATED(1f)
 1:
 .code16
 	/* 16 bit code from here on... */
@@ -107,7 +107,7 @@ __realmode_call:
 	 * configurations (limits, writability, etc.) once
 	 * protected mode is turned off.
 	 */
-	mov	$RAM_DATA16_SEG, %ax
+	mov	$GDT_DATA16_SEG, %ax
 	mov	%ax, %ds
 	mov	%ax, %es
 	mov	%ax, %fs
@@ -144,13 +144,13 @@ __realmode_call:
 	movl	__registers + 16, %esi
 	movl	__registers + 20, %edi
 
-	/* Set all segments to 0x0000, ds to 0x0040 */
+	/* Set all segments to 0x0000, ds to 0x0038 */
 	push	%ax
 	xor	%ax, %ax
 	mov	%ax, %es
 	mov	%ax, %fs
 	mov	%ax, %gs
-	mov	$RAM_DATA_ACPI_SEG, %ax
+	mov	$GDT_DATA_ACPI_SEG, %ax
 	mov	%ax, %ds
 	pop	%ax
 
@@ -177,10 +177,10 @@ __lcall_instr = RELOCATED(.)
 	/* Now that we are in protected mode
 	 * jump to a 32 bit code segment.
 	 */
-	ljmpl	$RAM_CODE_SEG, $RELOCATED(1f)
+	ljmpl	$GDT_CODE_SEG, $RELOCATED(1f)
 1:
 	.code32
-	mov	$RAM_DATA_SEG, %ax
+	mov	$GDT_DATA_SEG, %ax
 	mov	%ax, %ds
 	mov	%ax, %es
 	mov	%ax, %fs
@@ -233,7 +233,7 @@ __realmode_interrupt:
 	movl	%eax, __registers + 20 /* edi */
 
 	/*  This configures CS properly for real mode. */
-	ljmp 	$RAM_CODE16_SEG, $RELOCATED(1f)
+	ljmp 	$GDT_CODE16_SEG, $RELOCATED(1f)
 1:
 	.code16 /* 16 bit code from here on... */
 
@@ -241,7 +241,7 @@ __realmode_interrupt:
 	 * descriptors.  They will retain these configurations (limits,
 	 * writability, etc.) once protected mode is turned off.
 	 */
-	mov	$RAM_DATA16_SEG, %ax
+	mov	$GDT_DATA16_SEG, %ax
 	mov	%ax, %ds
 	mov	%ax, %es
 	mov	%ax, %fs
@@ -305,10 +305,10 @@ __intXX_instr = RELOCATED(.)
 	movl	%eax, %cr0
 
 	/* Now that we are in protected mode jump to a 32-bit code segment. */
-	ljmpl	$RAM_CODE_SEG, $RELOCATED(1f)
+	ljmpl	$GDT_CODE_SEG, $RELOCATED(1f)
 1:
 	.code32
-	mov	$RAM_DATA_SEG, %ax
+	mov	$GDT_DATA_SEG, %ax
 	mov	%ax, %ds
 	mov	%ax, %es
 	mov	%ax, %fs
@@ -354,10 +354,10 @@ __interrupt_handler_16bit = RELOCATED(.)
 	movl	%eax, %cr0
 
 	/* ... and jump to a 32 bit code segment. */
-	ljmpl	$RAM_CODE_SEG, $RELOCATED(1f)
+	ljmpl	$GDT_CODE_SEG, $RELOCATED(1f)
 1:
 	.code32
-	mov	$RAM_DATA_SEG, %ax
+	mov	$GDT_DATA_SEG, %ax
 	mov	%ax, %ds
 	mov	%ax, %es
 	mov	%ax, %fs
@@ -371,14 +371,14 @@ __interrupt_handler_16bit = RELOCATED(.)
 	call	*%eax
 
 	/* Now return to real mode ... */
-	ljmp	$RAM_CODE16_SEG, $RELOCATED(1f)
+	ljmp	$GDT_CODE16_SEG, $RELOCATED(1f)
 1:
 	.code16
 	/* Load the segment registers with properly configured segment
 	 * descriptors.  They will retain these configurations (limits,
 	 * writability, etc.) once protected mode is turned off.
 	 */
-	mov	$RAM_DATA16_SEG, %ax
+	mov	$GDT_DATA16_SEG, %ax
 	mov	%ax, %ds
 	mov	%ax, %es
 	mov	%ax, %fs
diff --git a/src/include/cpu/x86/gdt.h b/src/include/cpu/x86/gdt.h
index 27a863ee33..767e79467f 100644
--- a/src/include/cpu/x86/gdt.h
+++ b/src/include/cpu/x86/gdt.h
@@ -3,16 +3,28 @@
 #ifndef CPU_X86_GDT
 #define CPU_X86_GDT
 
+#ifndef __ASSEMBLER__
 /* These symbols are defined in c_start.S. */
 extern char gdt[];
 extern char per_cpu_segment_descriptors[];
 extern uint32_t per_cpu_segment_selector;
 extern char gdt_end[];
 extern char idtarg[];
+#endif
 
-/* These symbols are defined in secondary.S. */
-extern char _secondary_gdt_addr[];
-extern char _secondary_start[];
-extern char _secondary_start_end[];
+/* Offset to GDT's segment descriptors: */
+#define GDT_CODE_SEG            0x08
+#define GDT_DATA_SEG            0x10
+#define GDT_CODE_SEG64          0x18
+/*
+ * This define is placed here to make sure future romstage programmers
+ * know about it.
+ * It is used only in SMM for STM setup code.
+ */
+#define GDT_TASK_STATE_SEG      0x20
+
+#define GDT_CODE16_SEG          0x28
+#define GDT_DATA16_SEG          0x30
+#define GDT_DATA_ACPI_SEG       0x38
 
 #endif /* CPU_X86_GDT */
diff --git a/src/security/intel/stm/StmPlatformSmm.c b/src/security/intel/stm/StmPlatformSmm.c
index 9c5ae5264e..99e62c77c0 100644
--- a/src/security/intel/stm/StmPlatformSmm.c
+++ b/src/security/intel/stm/StmPlatformSmm.c
@@ -4,6 +4,7 @@
 #include <security/intel/stm/SmmStm.h>
 #include <security/intel/stm/StmPlatformResource.h>
 #include <security/tpm/tspi.h>
+#include <cpu/x86/gdt.h>
 #include <cpu/x86/smm.h>
 #include <cpu/x86/msr.h>
 
@@ -11,7 +12,6 @@
 #include <console/console.h>
 #include <stdbool.h>
 #include <stdint.h>
-#include <arch/rom_segs.h>
 
 /*
  * Load STM image to MSEG
@@ -109,11 +109,11 @@ void setup_smm_descriptor(void *smbase, int32_t apic_id, int32_t entry32_off)
 	psd->acpi_rsdp = 0;
 	psd->bios_hw_resource_requirements_ptr =
 		(uint64_t)((uintptr_t)get_stm_resource());
-	psd->smm_cs = ROM_CODE_SEG;
-	psd->smm_ds = ROM_DATA_SEG;
-	psd->smm_ss = ROM_DATA_SEG;
-	psd->smm_other_segment = ROM_DATA_SEG;
-	psd->smm_tr = SMM_TASK_STATE_SEG;
+	psd->smm_cs = GDT_CODE_SEG;
+	psd->smm_ds = GDT_DATA_SEG;
+	psd->smm_ss = GDT_DATA_SEG;
+	psd->smm_other_segment = GDT_DATA_SEG;
+	psd->smm_tr = GDT_TASK_STATE_SEG;
 
 	// At this point the coreboot smm_stub is relative to the default
 	// smbase and not the one for the smi handler in tseg.  So we have
diff --git a/src/security/intel/txt/getsec_enteraccs.S b/src/security/intel/txt/getsec_enteraccs.S
index ff9db05f06..9c0f5319a3 100644
--- a/src/security/intel/txt/getsec_enteraccs.S
+++ b/src/security/intel/txt/getsec_enteraccs.S
@@ -3,7 +3,7 @@
 #include <cpu/x86/mtrr.h>
 #include <cpu/x86/cr.h>
 #include <cpu/x86/msr.h>
-#include <arch/ram_segs.h>
+#include <cpu/x86/gdt.h>
 
 #include "getsec_mtrr_setup.inc"
 
@@ -257,10 +257,10 @@ cond_clear_var_mtrrs:
 	lgdt	-48(%ebp)
 
 	/* Set cs */
-	ljmp	$RAM_CODE_SEG, $1f
+	ljmp	$GDT_CODE_SEG, $1f
 1:
 	/* Fix segment registers */
-	movl	$RAM_DATA_SEG, %eax
+	movl	$GDT_DATA_SEG, %eax
 	movl	%eax, %ds
 	movl	%eax, %es
 	movl	%eax, %ss

From 18b43494229bc1c31a6861e71d0a2a462dad1dfd Mon Sep 17 00:00:00 2001
From: John Su <john_su@compal.corp-partner.google.com>
Date: Tue, 6 May 2025 19:08:29 +0800
Subject: [PATCH 0927/3886] mb/var/uldrenite: Fix
 fw_config_gpio_padbased_override not being called

Found that certain pins did not change according to the fw_config
settings. After tracing the code, discovered that
fw_config_gpio_padbased_override() was not being called, so this change
fixes the issue.

BUG=b:410481989
TEST=emerge-nissa coreboot

Change-Id: I07fb7860b32bae4922783fe437baafdd1c86482e
Signed-off-by: John Su <john_su@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87546
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
---
 .../google/brya/variants/uldrenite/variant.c      | 15 +++++++++++++++
 1 file changed, 15 insertions(+)

diff --git a/src/mainboard/google/brya/variants/uldrenite/variant.c b/src/mainboard/google/brya/variants/uldrenite/variant.c
index 532752837f..f5d01c1a89 100644
--- a/src/mainboard/google/brya/variants/uldrenite/variant.c
+++ b/src/mainboard/google/brya/variants/uldrenite/variant.c
@@ -8,6 +8,7 @@
 #include <fw_config.h>
 #include <sar.h>
 #include <soc/bootblock.h>
+#include <stdlib.h>
 
 const char *get_wifi_sar_cbfs_filename(void)
 {
@@ -122,3 +123,17 @@ void variant_update_descriptor(void)
 		configure_descriptor(fivr_bytes, ARRAY_SIZE(fivr_bytes));
 	}
 }
+
+void variant_configure_pads(void)
+{
+	const struct pad_config *base_pads;
+	struct pad_config *padbased_table;
+	size_t base_num;
+
+	padbased_table = new_padbased_table();
+	base_pads = variant_gpio_table(&base_num);
+	gpio_padbased_override(padbased_table, base_pads, base_num);
+	fw_config_gpio_padbased_override(padbased_table);
+	gpio_configure_pads_with_padbased(padbased_table);
+	free(padbased_table);
+}

From e180971560d5cebae57f51e7332f93e31038397e Mon Sep 17 00:00:00 2001
From: Subrata Banik <subratabanik@google.com>
Date: Mon, 5 May 2025 18:30:59 +0530
Subject: [PATCH 0928/3886] drivers/intel/fsp2_0: Move graphics info
 struct/GUID to FSP header

This patch moves `struct hob_graphics_info` and `fsp_graphics_info_guid`
into the FSP header file.

This change allows other coreboot APIs to utilize this information for
locating FSP graphics-related data to know the display resolutions and
other useful information (required for coreboot native implementation
of rendering splash screen).

BUG=b:409718202
TEST=Able to build and boot google/fatcat.

Change-Id: I445a4efa59769f25c93fc61ad1d15857716f5247
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87538
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/drivers/intel/fsp2_0/graphics.c           | 19 -------------------
 .../intel/fsp2_0/include/fsp/graphics.h       | 19 +++++++++++++++++++
 2 files changed, 19 insertions(+), 19 deletions(-)

diff --git a/src/drivers/intel/fsp2_0/graphics.c b/src/drivers/intel/fsp2_0/graphics.c
index b7466a55ab..08609b67c1 100644
--- a/src/drivers/intel/fsp2_0/graphics.c
+++ b/src/drivers/intel/fsp2_0/graphics.c
@@ -15,25 +15,6 @@ enum pixel_format {
 	pixel_bitmask = 2,		/* defined by <rgb>_mask values */
 };
 
-static const uint8_t fsp_graphics_info_guid[16] = {
-	0xce, 0x2c, 0xf6, 0x39, 0x25, 0x68, 0x69, 0x46,
-	0xbb, 0x56, 0x54, 0x1a, 0xba, 0x75, 0x3a, 0x07
-};
-
-struct hob_graphics_info {
-	uint64_t framebuffer_base;
-	uint32_t framebuffer_size;
-	uint32_t version;
-	uint32_t horizontal_resolution;
-	uint32_t vertical_resolution;
-	uint32_t pixel_format;		/* See enum pixel_format */
-	uint32_t red_mask;
-	uint32_t green_mask;
-	uint32_t blue_mask;
-	uint32_t reserved_mask;
-	uint32_t pixels_per_scanline;
-} __packed;
-
 struct pixel {
 	uint8_t pos;
 	uint8_t size;
diff --git a/src/drivers/intel/fsp2_0/include/fsp/graphics.h b/src/drivers/intel/fsp2_0/include/fsp/graphics.h
index a5f781f87f..7348237f1b 100644
--- a/src/drivers/intel/fsp2_0/include/fsp/graphics.h
+++ b/src/drivers/intel/fsp2_0/include/fsp/graphics.h
@@ -5,6 +5,25 @@
 
 #include <types.h>
 
+static const uint8_t fsp_graphics_info_guid[16] = {
+	0xce, 0x2c, 0xf6, 0x39, 0x25, 0x68, 0x69, 0x46,
+	0xbb, 0x56, 0x54, 0x1a, 0xba, 0x75, 0x3a, 0x07
+};
+
+struct hob_graphics_info {
+	uint64_t framebuffer_base;
+	uint32_t framebuffer_size;
+	uint32_t version;
+	uint32_t horizontal_resolution;
+	uint32_t vertical_resolution;
+	uint32_t pixel_format;		/* See enum pixel_format */
+	uint32_t red_mask;
+	uint32_t green_mask;
+	uint32_t blue_mask;
+	uint32_t reserved_mask;
+	uint32_t pixels_per_scanline;
+} __packed;
+
 /*
  * Report the fsp_graphics_info_guid HOB to framebuffer info.
  *

From 5f941893ef9901c82e09d4a79e7e1a42fbdedff3 Mon Sep 17 00:00:00 2001
From: Subrata Banik <subratabanik@google.com>
Date: Mon, 5 May 2025 16:58:02 +0530
Subject: [PATCH 0929/3886] cpu/x86/mtrr: Introduce mtrrlib with common MTRR
 helper functions
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

This change refactors MTRR handling by consolidating helper functions
from `earlymtrr.c` and `mtrr.c` into a new MTRR library (`mtrrlib`).
This approach improves code modularity and reusability, making these
utilities consistently available across different coreboot boot phases.

The following functions are now part of `mtrrlib`:

- `get_free_var_mtrr`: Retrieves the index of the first available
  variable MTRR.
- `set_var_mtrr`: Configures the variable MTRR, specified by an `index`,
  for a memory region defined by `base`, `size`, and `type`.
- `clear_var_mtrr`: Disables the variable MTRR at a given index.
- `acquire_and_configure_mtrr`: Acquires a free variable MTRR, configures
   it with the given `base`, `size`, and `type`.

BUG=b:409718202
TEST=Built and booted google/fatcat successfully.

Change-Id: Iba332b7088221fd930e973fad9410833bff184b9
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87539
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
---
 src/cpu/x86/mtrr/Makefile.mk |  6 +++
 src/cpu/x86/mtrr/earlymtrr.c | 57 +-----------------------
 src/cpu/x86/mtrr/mtrr.c      |  8 ----
 src/cpu/x86/mtrr/mtrrlib.c   | 85 ++++++++++++++++++++++++++++++++++++
 src/include/cpu/x86/mtrr.h   |  4 +-
 5 files changed, 96 insertions(+), 64 deletions(-)
 create mode 100644 src/cpu/x86/mtrr/mtrrlib.c

diff --git a/src/cpu/x86/mtrr/Makefile.mk b/src/cpu/x86/mtrr/Makefile.mk
index c74f014531..2846280d25 100644
--- a/src/cpu/x86/mtrr/Makefile.mk
+++ b/src/cpu/x86/mtrr/Makefile.mk
@@ -1,5 +1,11 @@
 ## SPDX-License-Identifier: GPL-2.0-only
 
+bootblock-y	+= mtrrlib.c
+verstage_x86-y	+= mtrrlib.c
+romstage-y	+= mtrrlib.c
+postcar-y	+= mtrrlib.c
+ramstage-y	+= mtrrlib.c
+
 ramstage-y	+= mtrr.c
 
 romstage-y	+= earlymtrr.c
diff --git a/src/cpu/x86/mtrr/earlymtrr.c b/src/cpu/x86/mtrr/earlymtrr.c
index 6c819a8c46..4ca7a0a5a4 100644
--- a/src/cpu/x86/mtrr/earlymtrr.c
+++ b/src/cpu/x86/mtrr/earlymtrr.c
@@ -7,67 +7,14 @@
 #include <commonlib/bsd/helpers.h>
 #include <types.h>
 
-/* Get first available variable MTRR.
- * Returns var# if available, else returns -1.
- */
-int get_free_var_mtrr(void)
-{
-	msr_t maskm;
-	int vcnt;
-	int i;
-
-	vcnt = get_var_mtrr_count();
-
-	/* Identify the first var mtrr which is not valid. */
-	for (i = 0; i < vcnt; i++) {
-		maskm = rdmsr(MTRR_PHYS_MASK(i));
-		if ((maskm.lo & MTRR_PHYS_MASK_VALID) == 0)
-			return i;
-	}
-
-	/* No free var mtrr. */
-	return -1;
-}
-
-void set_var_mtrr(
-	unsigned int reg, unsigned int base, unsigned int size,
-	unsigned int type)
-{
-	/* Bit 32-35 of MTRRphysMask should be set to 1 */
-	/* FIXME: It only support 4G less range */
-	msr_t basem, maskm;
-
-	if (type == MTRR_TYPE_WRBACK && !is_cache_sets_power_of_two() && ENV_CACHE_AS_RAM)
-		printk(BIOS_ERR, "MTRR Error: Type %x may not be supported due to NEM limitation\n",
-			 type);
-	if (!IS_POWER_OF_2(size))
-		printk(BIOS_ERR, "MTRR Error: size %#x is not a power of two\n", size);
-	if (size < 4 * KiB)
-		printk(BIOS_ERR, "MTRR Error: size %#x smaller than 4KiB\n", size);
-	if (base % size != 0)
-		printk(BIOS_ERR, "MTRR Error: base %#x must be aligned to size %#x\n", base,
-		       size);
-
-	basem.lo = base | type;
-	basem.hi = 0;
-	wrmsr(MTRR_PHYS_BASE(reg), basem);
-	maskm.lo = ~(size - 1) | MTRR_PHYS_MASK_VALID;
-	maskm.hi = (1 << (cpu_phys_address_size() - 32)) - 1;
-	wrmsr(MTRR_PHYS_MASK(reg), maskm);
-}
-
 void clear_all_var_mtrr(void)
 {
-	msr_t mtrr = { .raw = 0 };
 	int vcnt;
-	int i;
 
 	vcnt = get_var_mtrr_count();
 
-	for (i = 0; i < vcnt; i++) {
-		wrmsr(MTRR_PHYS_MASK(i), mtrr);
-		wrmsr(MTRR_PHYS_BASE(i), mtrr);
-	}
+	for (int i = 0; i < vcnt; i++)
+		clear_var_mtrr(i);
 }
 
 void var_mtrr_context_init(struct var_mtrr_context *ctx)
diff --git a/src/cpu/x86/mtrr/mtrr.c b/src/cpu/x86/mtrr/mtrr.c
index 0d31cab769..33fc46e362 100644
--- a/src/cpu/x86/mtrr/mtrr.c
+++ b/src/cpu/x86/mtrr/mtrr.c
@@ -369,14 +369,6 @@ struct var_mtrr_state {
 	struct var_mtrr_regs *regs;
 };
 
-static void clear_var_mtrr(int index)
-{
-	msr_t msr = { .lo = 0, .hi = 0 };
-
-	wrmsr(MTRR_PHYS_BASE(index), msr);
-	wrmsr(MTRR_PHYS_MASK(index), msr);
-}
-
 static int get_os_reserved_mtrrs(void)
 {
 	return CONFIG(RESERVE_MTRRS_FOR_OS) ? 2 : 0;
diff --git a/src/cpu/x86/mtrr/mtrrlib.c b/src/cpu/x86/mtrr/mtrrlib.c
new file mode 100644
index 0000000000..fe6bd6aef5
--- /dev/null
+++ b/src/cpu/x86/mtrr/mtrrlib.c
@@ -0,0 +1,85 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <cpu/cpu.h>
+#include <cpu/x86/mtrr.h>
+#include <cpu/x86/msr.h>
+#include <console/console.h>
+#include <commonlib/bsd/helpers.h>
+#include <types.h>
+
+/*
+ * Get first available variable MTRR.
+ * Returns var# if available, else returns -1.
+ */
+int get_free_var_mtrr(void)
+{
+	msr_t maskm;
+	int vcnt;
+	int i;
+
+	vcnt = get_var_mtrr_count();
+
+	/* Identify the first var mtrr which is not valid. */
+	for (i = 0; i < vcnt; i++) {
+		maskm = rdmsr(MTRR_PHYS_MASK(i));
+		if ((maskm.lo & MTRR_PHYS_MASK_VALID) == 0)
+			return i;
+	}
+
+	/* No free var mtrr. */
+	return -1;
+}
+
+/*
+ * Sets the specified variable MTRR (as per index) with the
+ * given base, size, and memory type.
+ */
+void set_var_mtrr(
+	unsigned int index, unsigned int base, unsigned int size,
+	unsigned int type)
+{
+	/* Bit 32-35 of MTRRphysMask should be set to 1 */
+	/* FIXME: It only support 4G less range */
+	msr_t basem, maskm;
+
+	if (type == MTRR_TYPE_WRBACK && !is_cache_sets_power_of_two() && ENV_CACHE_AS_RAM)
+		printk(BIOS_ERR, "MTRR Error: Type %x may not be supported due to NEM limitation\n",
+			 type);
+	if (!IS_POWER_OF_2(size))
+		printk(BIOS_ERR, "MTRR Error: size %#x is not a power of two\n", size);
+	if (size < 4 * KiB)
+		printk(BIOS_ERR, "MTRR Error: size %#x smaller than 4KiB\n", size);
+	if (base % size != 0)
+		printk(BIOS_ERR, "MTRR Error: base %#x must be aligned to size %#x\n", base,
+		       size);
+
+	basem.lo = base | type;
+	basem.hi = 0;
+	wrmsr(MTRR_PHYS_BASE(index), basem);
+	maskm.lo = ~(size - 1) | MTRR_PHYS_MASK_VALID;
+	maskm.hi = (1 << (cpu_phys_address_size() - 32)) - 1;
+	wrmsr(MTRR_PHYS_MASK(index), maskm);
+}
+
+/* Disables the variable MTRR at the given index by clearing its base and mask MSRs. */
+void clear_var_mtrr(int index)
+{
+	msr_t msr = { .lo = 0, .hi = 0 };
+
+	wrmsr(MTRR_PHYS_BASE(index), msr);
+	wrmsr(MTRR_PHYS_MASK(index), msr);
+}
+
+/*
+ * Acquires a free variable MTRR, configures it with the given base, size, and type.
+ * Returns the MTRR index if successful (>=0), or an error code (<0) if acquisition failed.
+ */
+int acquire_and_configure_mtrr(unsigned int base, unsigned int size, unsigned int type)
+{
+	int index = get_free_var_mtrr();
+
+	if (index >= 0)
+		set_var_mtrr(index, base, size, type);
+
+	return index;
+}
diff --git a/src/include/cpu/x86/mtrr.h b/src/include/cpu/x86/mtrr.h
index 930edfdef7..87aee95c67 100644
--- a/src/include/cpu/x86/mtrr.h
+++ b/src/include/cpu/x86/mtrr.h
@@ -124,9 +124,11 @@ static inline int get_var_mtrr_count(void)
 	return rdmsr(MTRR_CAP_MSR).lo & MTRR_CAP_VCNT;
 }
 
-void set_var_mtrr(unsigned int reg, unsigned int base, unsigned int size,
+int acquire_and_configure_mtrr(unsigned int base, unsigned int size, unsigned int type);
+void set_var_mtrr(unsigned int index, unsigned int base, unsigned int size,
 	unsigned int type);
 int get_free_var_mtrr(void);
+void clear_var_mtrr(int index);
 void clear_all_var_mtrr(void);
 
 asmlinkage void display_mtrrs(void);

From 78d15d9a12743e7cd4d2b10a734232711fcc3963 Mon Sep 17 00:00:00 2001
From: Subrata Banik <subratabanik@google.com>
Date: Fri, 2 May 2025 13:19:01 +0530
Subject: [PATCH 0930/3886] drivers/intel/fsp2_0: Add Kconfig to select FSP for
 BMP rendering
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

This patch introduces `USE_COREBOOT_FOR_BMP_RENDERING`, a Kconfig option
allowing platforms to choose coreboot to use its native bitmap (BMP)
logo image rendering and skip using the FSP for this purpose during
the boot process.

By default this option is disabled (default 'n'), therefore, the FSP
is utilized for displaying the BMP logo by populating the necessary
FSP UPD parameters.

Select this option for platforms that will use a coreboot native
implementation for BMP rendering (note: the native coreboot rendering
path is still under development/to be implemented).

This Kconfig provides the switch for such future integration.

Key changes:
- A new boolean Kconfig `USE_COREBOOT_FOR_BMP_RENDERING` is added under
  `drivers/intel/fsp2_0/Kconfig`. It depends on `BMP_LOGO` and
  defaults to 'n'.
- The help text clarifies that selecting this option will skip FSP-based
  BMP rendering. Deselection implies a fallback to the FSP based
  implementation.
- The function `soc_load_logo`, previously responsible for populating
  FSP UPD parameters for the logo, is renamed to `soc_load_logo_by_fsp`.
  This clarifies its role is specific to FSP-driven logo display.
- The call to `soc_load_logo_by_fsp` in `fsp2_0/silicon_init.c` is
  now conditional on `CONFIG(BMP_LOGO)` being enabled but the new
  `CONFIG(USE_COREBOOT_FOR_BMP_RENDERING)` remains disabled.
- Implementations and calls to the renamed function are updated across
  relevant SoC directories (AMD Mendocino, Intel Alder Lake, Apollolake,
  Cannon Lake, Meteor Lake, Panther Lake, Skylake).

This change offers platforms greater flexibility in managing BMP logo
display, allowing them to either leverage FSP capabilities or integrate
with coreboot's native methods as they become available.

BUG=b:409718202
TEST=Built and booted google/fatcat. Verified boot splash was rendered
by FSP as `USE_COREBOOT_FOR_BMP_RENDERING` was set to `n`.

Change-Id: Ieda085df02263b9bf4bdd8f5d0e2137bef75def9
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87513
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
---
 src/drivers/intel/fsp2_0/Kconfig           | 18 ++++++++++++++++++
 src/drivers/intel/fsp2_0/include/fsp/api.h |  7 +++++--
 src/drivers/intel/fsp2_0/silicon_init.c    | 11 +++++++----
 src/soc/amd/mendocino/fsp_s_params.c       |  2 +-
 src/soc/intel/alderlake/fsp_params.c       |  2 +-
 src/soc/intel/apollolake/chip.c            |  2 +-
 src/soc/intel/cannonlake/fsp_params.c      |  2 +-
 src/soc/intel/meteorlake/fsp_params.c      |  2 +-
 src/soc/intel/pantherlake/fsp_params.c     |  2 +-
 src/soc/intel/skylake/chip.c               |  2 +-
 10 files changed, 37 insertions(+), 13 deletions(-)

diff --git a/src/drivers/intel/fsp2_0/Kconfig b/src/drivers/intel/fsp2_0/Kconfig
index 942591585d..715ec2a759 100644
--- a/src/drivers/intel/fsp2_0/Kconfig
+++ b/src/drivers/intel/fsp2_0/Kconfig
@@ -475,4 +475,22 @@ config BUILDING_WITH_DEBUG_FSP
 	  Enable this option if you are using a debug build of the FSP (Firmware Support Package)
 	  in your project.
 
+config USE_COREBOOT_FOR_BMP_RENDERING
+	bool
+	default n
+	help
+	  This option forces coreboot to use its native bitmap (BMP) image rendering
+	  and skip using the FSP for this purpose during the boot process.
+
+	  If this option is selected (y), the platform will rely on the
+	  coreboot native implementation for rendering BMP images. This might be
+	  chosen if there are issues with FSP rendering or if native rendering
+	  is preferred for specific reasons.
+
+	  If this option is not selected (n), the FSP's capabilities for BMP rendering
+	  will be utilized.
+
+	  Platforms can choose to override this Kconfig option based on their
+	  specific graphics requirements and FSP capabilities.
+
 endif
diff --git a/src/drivers/intel/fsp2_0/include/fsp/api.h b/src/drivers/intel/fsp2_0/include/fsp/api.h
index 0cbefbe9ae..8c9dc8c529 100644
--- a/src/drivers/intel/fsp2_0/include/fsp/api.h
+++ b/src/drivers/intel/fsp2_0/include/fsp/api.h
@@ -85,8 +85,11 @@ void platform_fsp_notify_status(enum fsp_notify_phase phase);
 
 /* Initialize memory margin analysis settings. */
 void setup_mma(FSP_M_CONFIG *memory_cfg);
-/* Update the SOC specific logo param and load the logo. */
-void soc_load_logo(FSPS_UPD *supd);
+/*
+ * Populate UPD entries for the logo if the platform utilizes
+ * the FSP's capability for rendering bitmap (BMP) images.
+ */
+void soc_load_logo_by_fsp(FSPS_UPD *supd);
 /* Update the SOC specific memory config param for mma. */
 void soc_update_memory_params_for_mma(FSP_M_CONFIG *memory_cfg,
 	struct mma_config_param *mma_cfg);
diff --git a/src/drivers/intel/fsp2_0/silicon_init.c b/src/drivers/intel/fsp2_0/silicon_init.c
index f3472420bc..cd4b5cb682 100644
--- a/src/drivers/intel/fsp2_0/silicon_init.c
+++ b/src/drivers/intel/fsp2_0/silicon_init.c
@@ -124,9 +124,12 @@ static void do_silicon_init(struct fsp_header *hdr)
 	/* Give SoC/mainboard a chance to populate entries */
 	platform_fsp_silicon_init_params_cb(upd);
 
-	/* Populate logo related entries */
-	if (CONFIG(BMP_LOGO))
-		soc_load_logo(upd);
+	/*
+	 * Populate UPD entries for the logo if the platform utilizes
+	 * the FSP's capability for rendering bitmap (BMP) images.
+	 */
+	if (CONFIG(BMP_LOGO) && !CONFIG(USE_COREBOOT_FOR_BMP_RENDERING))
+		soc_load_logo_by_fsp(upd);
 
 	/* Call SiliconInit */
 	silicon_init = (void *)(uintptr_t)(hdr->image_base +
@@ -269,7 +272,7 @@ void fsp_silicon_init(void)
 		fsp_display_timestamp();
 }
 
-__weak void soc_load_logo(FSPS_UPD *supd) { }
+__weak void soc_load_logo_by_fsp(FSPS_UPD *supd) { }
 
 static void release_logo(void *arg_unused)
 {
diff --git a/src/soc/amd/mendocino/fsp_s_params.c b/src/soc/amd/mendocino/fsp_s_params.c
index 5393eba911..23b2cfe5ce 100644
--- a/src/soc/amd/mendocino/fsp_s_params.c
+++ b/src/soc/amd/mendocino/fsp_s_params.c
@@ -59,7 +59,7 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
 		payload_preload();
 }
 
-void soc_load_logo(FSPS_UPD *supd)
+void soc_load_logo_by_fsp(FSPS_UPD *supd)
 {
 	size_t logo_size;
 	supd->FspsConfig.logo_bmp_buffer = (uint32_t)(uintptr_t)bmp_load_logo(&logo_size);
diff --git a/src/soc/intel/alderlake/fsp_params.c b/src/soc/intel/alderlake/fsp_params.c
index 022b41e08a..a788319efc 100644
--- a/src/soc/intel/alderlake/fsp_params.c
+++ b/src/soc/intel/alderlake/fsp_params.c
@@ -1381,7 +1381,7 @@ __weak void mainboard_silicon_init_params(FSP_S_CONFIG *s_cfg)
 }
 
 /* Handle FSP logo params */
-void soc_load_logo(FSPS_UPD *supd)
+void soc_load_logo_by_fsp(FSPS_UPD *supd)
 {
 	struct soc_intel_common_config *config = chip_get_common_soc_structure();
 	FSP_S_CONFIG *s_cfg = &supd->FspsConfig;
diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c
index ab5b5d884d..c5553780ea 100644
--- a/src/soc/intel/apollolake/chip.c
+++ b/src/soc/intel/apollolake/chip.c
@@ -914,7 +914,7 @@ void mainboard_silicon_init_params(FSP_S_CONFIG *silconfig)
 }
 
 /* Handle FSP logo params */
-void soc_load_logo(FSPS_UPD *supd)
+void soc_load_logo_by_fsp(FSPS_UPD *supd)
 {
 	size_t logo_size;
 	supd->FspsConfig.LogoPtr = (uint32_t)(uintptr_t)bmp_load_logo(&logo_size);
diff --git a/src/soc/intel/cannonlake/fsp_params.c b/src/soc/intel/cannonlake/fsp_params.c
index 993efbb107..2e00018f36 100644
--- a/src/soc/intel/cannonlake/fsp_params.c
+++ b/src/soc/intel/cannonlake/fsp_params.c
@@ -801,7 +801,7 @@ __weak void mainboard_silicon_init_params(FSPS_UPD *supd)
 }
 
 /* Handle FSP logo params */
-void soc_load_logo(FSPS_UPD *supd)
+void soc_load_logo_by_fsp(FSPS_UPD *supd)
 {
 	size_t logo_size;
 	supd->FspsConfig.LogoPtr = (uintptr_t)bmp_load_logo(&logo_size);
diff --git a/src/soc/intel/meteorlake/fsp_params.c b/src/soc/intel/meteorlake/fsp_params.c
index a14d385ecf..30ea478432 100644
--- a/src/soc/intel/meteorlake/fsp_params.c
+++ b/src/soc/intel/meteorlake/fsp_params.c
@@ -871,7 +871,7 @@ __weak void mainboard_silicon_init_params(FSP_S_CONFIG *s_cfg)
 }
 
 /* Handle FSP logo params */
-void soc_load_logo(FSPS_UPD *supd)
+void soc_load_logo_by_fsp(FSPS_UPD *supd)
 {
 	struct soc_intel_common_config *config = chip_get_common_soc_structure();
 	FSP_S_CONFIG *s_cfg = &supd->FspsConfig;
diff --git a/src/soc/intel/pantherlake/fsp_params.c b/src/soc/intel/pantherlake/fsp_params.c
index 32be2852db..f45d333032 100644
--- a/src/soc/intel/pantherlake/fsp_params.c
+++ b/src/soc/intel/pantherlake/fsp_params.c
@@ -800,7 +800,7 @@ __weak void mainboard_silicon_init_params(FSP_S_CONFIG *s_cfg)
 }
 
 /* Handle FSP logo params */
-void soc_load_logo(FSPS_UPD *supd)
+void soc_load_logo_by_fsp(FSPS_UPD *supd)
 {
 	efi_uintn_t logo, blt_size;
 	uint32_t logo_size;
diff --git a/src/soc/intel/skylake/chip.c b/src/soc/intel/skylake/chip.c
index 0356c3e8dd..0061c10ae8 100644
--- a/src/soc/intel/skylake/chip.c
+++ b/src/soc/intel/skylake/chip.c
@@ -511,7 +511,7 @@ __weak void mainboard_silicon_init_params(FSP_S_CONFIG *params)
 }
 
 /* Handle FSP logo params */
-void soc_load_logo(FSPS_UPD *supd)
+void soc_load_logo_by_fsp(FSPS_UPD *supd)
 {
 	size_t logo_size;
 	supd->FspsConfig.LogoPtr = (uint32_t)(uintptr_t)bmp_load_logo(&logo_size);

From 2f238962995ba1487d328cea06b240cc65768d4e Mon Sep 17 00:00:00 2001
From: Subrata Banik <subratabanik@google.com>
Date: Mon, 5 May 2025 19:15:37 +0530
Subject: [PATCH 0931/3886] soc/intel/intelblocks/cfg: Add splash screen
 vertical alignment options

This commit introduces an enum `fw_splash_vertical_alignment` to
configure the vertical placement of the splash screen image.

The enum provides options for aligning the logo to the top, bottom,
center (geometrical center), or middle (top edge at midpoint) of the
display.

BUG=b:409718202
TEST=Able to build and boot google/fatcat.

Change-Id: Id70fb56a038fba93d51dc1a7906724dbed6edf94
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87540
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 .../common/block/include/intelblocks/cfg.h    | 71 +++++++++++++++++++
 1 file changed, 71 insertions(+)

diff --git a/src/soc/intel/common/block/include/intelblocks/cfg.h b/src/soc/intel/common/block/include/intelblocks/cfg.h
index 8563520961..299e923d85 100644
--- a/src/soc/intel/common/block/include/intelblocks/cfg.h
+++ b/src/soc/intel/common/block/include/intelblocks/cfg.h
@@ -13,6 +13,76 @@ enum {
 	CHIPSET_LOCKDOWN_FSP,		/* FSP handles locking per UPDs */
 };
 
+/*
+ * Specifies the vertical alignment for the splash screen image.
+ *
+ * Visual Guide (representing the display area and the [LOGO]):
+ *
+ * Each option dictates the vertical placement of the splash image
+ * within the display's height.
+ */
+enum fw_splash_vertical_alignment {
+	/* FW_SPLASH_VALIGNMENT_CENTER:
+	 * The splash image is centered vertically `(Y-axis - logo_height)/2` on the screen.
+	 * The center of the [LOGO] aligns with the vertical center of the screen.
+	 *
+	 * +---------------+
+	 * |               |
+	 * |               |
+	 * |    [LOGO]     |  <-- Vertically Centered
+	 * |               |
+	 * |               |
+	 * +---------------+
+	 */
+	FW_SPLASH_VALIGNMENT_CENTER = 0,
+
+	/* FW_SPLASH_VALIGNMENT_TOP:
+	 * The splash image is aligned to the top edge of the screen.
+	 *
+	 * +---------------+
+	 * |    [LOGO]     |  <-- Top Aligned
+	 * |               |
+	 * |               |
+	 * |               |
+	 * |               |
+	 * +---------------+
+	 */
+	FW_SPLASH_VALIGNMENT_TOP = 1,
+
+	/* FW_SPLASH_VALIGNMENT_BOTTOM:
+	 * The splash image is aligned to the bottom edge of the screen.
+	 *
+	 * +---------------+
+	 * |               |
+	 * |               |
+	 * |               |
+	 * |               |
+	 * |    [LOGO]     |  <-- Bottom Aligned
+	 * +---------------+
+	 */
+	FW_SPLASH_VALIGNMENT_BOTTOM = 2,
+
+	/* FW_SPLASH_VALIGNMENT_MIDDLE:
+	 * The splash image is placed in the vertical middle `(Y-axis/2)` of the screen
+	 * (without considering the `logo height`). This means the TOP EDGE of the
+	 * [LOGO] aligns with the screen's vertical midpoint line.
+	 *
+	 * +---------------+
+	 * | (Upper Half)  |
+	 * |               |
+	 * |    [LOGO]     | <-- [LOGO] aligns at Middle of the Y-axis
+	 * |               |
+	 * | (Lower Half)  |
+	 * +---------------+
+	 *
+	 * Note: The distinction between CENTER and MIDDLE is relevant as in for MIDDLE
+	 * alignment, it ignores the logo height (i.e., the logo's top edge is placed
+	 * at the screen's Y-midpoint). CENTER alignment, by contrast, would place
+	 * the geometrical center of the logo at the screen's Y-midpoint.
+	 */
+	FW_SPLASH_VALIGNMENT_MIDDLE = 3,
+};
+
 /*
  * This structure will hold data required by common blocks.
  * These are soc specific configurations which will be filled by soc.
@@ -26,6 +96,7 @@ struct soc_intel_common_config {
 	uint8_t pch_thermal_trip;
 	struct mmc_dll_params emmc_dll;
 	enum lb_fb_orientation panel_orientation;
+	enum fw_splash_vertical_alignment logo_valignment;
 };
 
 /* This function to retrieve soc config structure required by common code */

From e446c1f9171445229c070ea152975f342a396d75 Mon Sep 17 00:00:00 2001
From: Subrata Banik <subratabanik@google.com>
Date: Mon, 5 May 2025 19:36:42 +0530
Subject: [PATCH 0932/3886] drivers/intel/fsp2_0: Introduce coreboot native
 logo rendering
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

This commit implements coreboot native logo rendering when
`USE_COREBOOT_FOR_BMP_RENDERING` Kconfig is enabled.

When enabled, this option allows coreboot to perform the boot logo
rendering directly after the FSP initializes the display. A new API
`soc_load_logo_by_coreboot` is introduced for this purpose.

This approach offers greater flexibility for platform-specific logo
customizations (e.g., alignment) that might be impractical to
implement within the FSP.

Note that enabling this option might introduce a slight delay (~10-30ms)
in displaying BMP images compared to FSP-based rendering.

BUG=b:409718202
TEST=Built and booted google/fatcat. Verified boot splash was rendered
by coreboot as `USE_COREBOOT_FOR_BMP_RENDERING` was set to `y`.

Change-Id: I9454d0941458e29a5533a92170831f360765b413
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87541
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
---
 src/drivers/intel/fsp2_0/Makefile.mk       |   1 +
 src/drivers/intel/fsp2_0/cb_logo.c         | 175 +++++++++++++++++++++
 src/drivers/intel/fsp2_0/include/fsp/api.h |  22 +++
 src/drivers/intel/fsp2_0/silicon_init.c    |  20 +++
 4 files changed, 218 insertions(+)
 create mode 100644 src/drivers/intel/fsp2_0/cb_logo.c

diff --git a/src/drivers/intel/fsp2_0/Makefile.mk b/src/drivers/intel/fsp2_0/Makefile.mk
index 18a62e3b57..16905ca373 100644
--- a/src/drivers/intel/fsp2_0/Makefile.mk
+++ b/src/drivers/intel/fsp2_0/Makefile.mk
@@ -35,6 +35,7 @@ ramstage-$(CONFIG_FSP_NVS_DATA_POST_SILICON_INIT) += save_mrc_data.c
 ramstage-$(CONFIG_MMA) += mma_core.c
 ramstage-$(CONFIG_ENABLE_FSP_ERROR_INFO) += fsp_error_info_hob.c
 ramstage-$(CONFIG_BMP_LOGO) += fsp_gop_blt.c
+ramstage-$(CONFIG_USE_COREBOOT_FOR_BMP_RENDERING) += cb_logo.c
 
 ifneq ($(CONFIG_NO_FSP_TEMP_RAM_EXIT),y)
 postcar-$(CONFIG_FSP_CAR) += temp_ram_exit.c
diff --git a/src/drivers/intel/fsp2_0/cb_logo.c b/src/drivers/intel/fsp2_0/cb_logo.c
new file mode 100644
index 0000000000..cc62a1c553
--- /dev/null
+++ b/src/drivers/intel/fsp2_0/cb_logo.c
@@ -0,0 +1,175 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#define __SIMPLE_DEVICE__
+
+#include <bootmode.h>
+#include <console/console.h>
+#include <cpu/x86/mtrr.h>
+#include <device/pci_ops.h>
+#include <fsp/api.h>
+#include <fsp/fsp_gop_blt.h>
+#include <fsp/graphics.h>
+#include <fsp/util.h>
+#include <intelblocks/graphics.h>
+#include <soc/iomap.h>
+#include <soc/soc_chip.h>
+#include <stdlib.h>
+#include <string.h>
+
+struct logo_coordinates {
+	uint32_t x;
+	uint32_t y;
+};
+
+/*
+ * Programs the Local Memory BAR (LMEMBAR) for the IGD.
+ *
+ * This function disables PCI command bits related to I/O, memory, and bus mastering
+ * for the IGD, programs the LMEMBAR with the provided base address, and then
+ * re-enables the PCI command bits.
+ */
+static void program_igd_lmembar(uint32_t base)
+{
+	const uint16_t disable_mask = ~(PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
+	const uint16_t enable_mask = (PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
+
+	/* Disable response in IO, MMIO space and Bus Master. */
+	pci_and_config16(SA_DEV_IGD, PCI_COMMAND, disable_mask);
+
+	/* Program IGD Base Address Register 2 aka LMEMBAR */
+	pci_write_config32(SA_DEV_IGD, PCI_BASE_ADDRESS_2, base);
+
+	/* Enable response in IO, MMIO space and Bus Master. */
+	pci_or_config16(SA_DEV_IGD, PCI_COMMAND, enable_mask);
+}
+
+/*
+ * Calculates the destination coordinates for the logo based on alignment settings.
+ *
+ * horizontal_resolution: The horizontal resolution of the display panel.
+ * vertical_resolution: The vertical resolution of the display panel.
+ * logo_width: The width of the logo bitmap.
+ * logo_height: The height of the logo bitmap.
+ * valignment: The vertical alignment setting.
+ *
+ * Returning `struct logo_coordinates` that contains the calculated x and y coordinates
+ * for rendering the logo.
+ */
+static struct logo_coordinates calculate_logo_coordinates(
+	uint32_t horizontal_resolution, uint32_t vertical_resolution,
+	uint32_t logo_width, uint32_t logo_height, enum fw_splash_vertical_alignment valignment)
+{
+	struct logo_coordinates coords;
+	/* Always horizontally centered */
+	coords.x = (horizontal_resolution - logo_width) / 2;
+
+	switch (valignment) {
+	case FW_SPLASH_VALIGNMENT_MIDDLE:
+		coords.y = vertical_resolution / 2;
+		break;
+	case FW_SPLASH_VALIGNMENT_TOP:
+		coords.y = 0;
+		break;
+	case FW_SPLASH_VALIGNMENT_BOTTOM:
+		coords.y = vertical_resolution - logo_height;
+		break;
+	default: /* FW_SPLASH_VALIGNMENT_CENTER (default) */
+		coords.y = (vertical_resolution - logo_height) / 2;
+		break;
+	}
+
+	return coords;
+}
+
+/*
+ * Copies the logo to the framebuffer.
+ *
+ * framebuffer_base: The base address of the framebuffer.
+ * bytes_per_scanline: The number of bytes per scanline in the framebuffer.
+ * logo_buffer_addr: The address of the logo data in BLT format.
+ * logo_width: The width of the logo bitmap.
+ * logo_height: The height of the logo bitmap.
+ * dest_x: The destination x-coordinate in the framebuffer for rendering the logo.
+ * dest_y: The destination y-coordinate in the framebuffer for rendering the logo.
+ */
+static void copy_logo_to_framebuffer(
+	uintptr_t framebuffer_base, uint32_t bytes_per_scanline,
+	efi_uintn_t logo_buffer_addr, uint32_t logo_width, uint32_t logo_height,
+	efi_uintn_t dest_x, efi_uintn_t dest_y)
+{
+	size_t pixel_size = sizeof(efi_graphics_output_blt_pixel);
+	size_t logo_line_bytes = logo_width * pixel_size;
+	efi_uintn_t framebuffer_offset = framebuffer_base + dest_y * bytes_per_scanline
+					 + dest_x * pixel_size;
+	uint8_t *dst_row_address = (uint8_t *)framebuffer_offset;
+	uint8_t *src_row_address = (uint8_t *)(uintptr_t)logo_buffer_addr;
+	for (uint32_t i = 0; i < logo_height; i++) {
+		memcpy(dst_row_address, src_row_address, logo_line_bytes);
+		dst_row_address += bytes_per_scanline;
+		src_row_address += logo_line_bytes;
+	}
+}
+
+void soc_load_logo_by_coreboot(void)
+{
+	size_t size;
+	const struct hob_graphics_info *ginfo;
+	struct soc_intel_common_config *config = chip_get_common_soc_structure();
+	efi_uintn_t logo, blt_size;
+	efi_uintn_t blt_buffer_addr;
+	uint32_t logo_size, logo_height, logo_width;
+	int temp_mtrr_index = -1;
+
+	/* Find the graphics information HOB */
+	ginfo = fsp_find_extension_hob_by_guid(fsp_graphics_info_guid, &size);
+	if (!ginfo || ginfo->framebuffer_base == 0) {
+		printk(BIOS_ERR, "Graphics information HOB not found or invalid framebuffer base.\n");
+		return;
+	}
+
+	/* Program the IGD LMEMBAR */
+	program_igd_lmembar(GMADR_BASE);
+
+	/* Set up a temporary Write Combine (WC) MTRR for the GMADR range */
+	temp_mtrr_index = acquire_and_configure_mtrr(GMADR_BASE, GMADR_SIZE, MTRR_TYPE_WRCOMB);
+	if (temp_mtrr_index < 0) {
+		printk(BIOS_ERR, "Failed to configure WC MTRR for GMADR.\n");
+		return;
+	}
+
+	uintptr_t framebuffer_bar = ginfo->framebuffer_base;
+	uint32_t horizontal_resolution = ginfo->horizontal_resolution;
+	uint32_t vertical_resolution = ginfo->vertical_resolution;
+	uint32_t bytes_per_scanline = ginfo->pixels_per_scanline *
+				 sizeof(efi_graphics_output_blt_pixel);
+
+	/*
+	 * Adjusts panel orientation for external display when the lid is closed.
+	 *
+	 * When the lid is closed, indicating the onboard display is inactive,
+	 * below logic forces the panel orientation to normal. This ensures proper display
+	 * on an external monitor, as rotated orientations are typically not suitable in
+	 * such state.
+	 */
+	if (CONFIG(VBOOT_LID_SWITCH) ? !get_lid_switch() : !CONFIG(RUN_FSP_GOP))
+		config->panel_orientation = LB_FB_ORIENTATION_NORMAL;
+
+	/* Convert BMP logo to GOP BLT format */
+	fsp_convert_bmp_to_gop_blt(&logo, &logo_size, &blt_buffer_addr, &blt_size,
+			   &logo_height, &logo_width, config->panel_orientation);
+
+	/* Override logo alignment if the default screen orientation is not normal */
+	if (config->panel_orientation != LB_FB_ORIENTATION_NORMAL)
+		config->logo_valignment = FW_SPLASH_VALIGNMENT_CENTER;
+
+	/* Calculate logo destination coordinates */
+	struct logo_coordinates logo_coords = calculate_logo_coordinates(horizontal_resolution,
+			 vertical_resolution, logo_width, logo_height, config->logo_valignment);
+
+	/* Copy the logo to the framebuffer */
+	copy_logo_to_framebuffer(framebuffer_bar, bytes_per_scanline, blt_buffer_addr, logo_width,
+			 logo_height, logo_coords.x, logo_coords.y);
+
+	/* Clear temporary Write Combine (WC) MTRR */
+	clear_var_mtrr(temp_mtrr_index);
+}
diff --git a/src/drivers/intel/fsp2_0/include/fsp/api.h b/src/drivers/intel/fsp2_0/include/fsp/api.h
index 8c9dc8c529..9ff32be6fc 100644
--- a/src/drivers/intel/fsp2_0/include/fsp/api.h
+++ b/src/drivers/intel/fsp2_0/include/fsp/api.h
@@ -90,6 +90,28 @@ void setup_mma(FSP_M_CONFIG *memory_cfg);
  * the FSP's capability for rendering bitmap (BMP) images.
  */
 void soc_load_logo_by_fsp(FSPS_UPD *supd);
+/*
+ * API that allows coreboot to perform native logo rendering after FSP display initialization.
+ *
+ * This implementation handles rendering the boot logo directly within coreboot.
+ * It depends on the FSP to initialize the display panel.
+ * Once the FSP completes display initialization and transfers control, coreboot
+ * renders the logo.
+ *
+ * Note: This native approach may introduce a ~10-30ms delay in displaying
+ * BMP images compared to rendering via FSP (when `USE_COREBOOT_FOR_BMP_RENDERING`
+ * Kconfig is not enable).
+ *
+ * coreboot native logo rendering provides greater flexibility for platform-specific
+ * logo customizations (e.g., alignment) that are not feasible or practical to implement
+ * within the FSP (silicon firmware) depending upon the OEM device need.
+ */
+#if CONFIG(USE_COREBOOT_FOR_BMP_RENDERING)
+void soc_load_logo_by_coreboot(void);
+#else
+static inline void soc_load_logo_by_coreboot(void) { /* nop */ }
+#endif
+
 /* Update the SOC specific memory config param for mma. */
 void soc_update_memory_params_for_mma(FSP_M_CONFIG *memory_cfg,
 	struct mma_config_param *mma_cfg);
diff --git a/src/drivers/intel/fsp2_0/silicon_init.c b/src/drivers/intel/fsp2_0/silicon_init.c
index cd4b5cb682..76636dd7a8 100644
--- a/src/drivers/intel/fsp2_0/silicon_init.c
+++ b/src/drivers/intel/fsp2_0/silicon_init.c
@@ -157,6 +157,17 @@ static void do_silicon_init(struct fsp_header *hdr)
 	fsp_debug_after_silicon_init(status);
 	fsps_return_value_handler(FSP_SILICON_INIT_API, status);
 
+	/*
+	 * Only applies for SoC platforms prior to FSP 2.2 specification:
+	 * If a BMP logo is enabled (`BMP_LOGO`) and the platform is
+	 * configured to skip the FSP for rendering logo bitmap
+	 * (`USE_COREBOOT_FOR_BMP_RENDERING`), then call the coreboot
+	 * native function to handle BMP logo loading and display.
+	 */
+	if (!CONFIG(PLATFORM_USES_FSP2_2) && CONFIG(BMP_LOGO) &&
+			 CONFIG(USE_COREBOOT_FOR_BMP_RENDERING))
+		soc_load_logo_by_coreboot();
+
 	/* Reinitialize CPUs if FSP-S has done MP Init */
 	if (CONFIG(USE_INTEL_FSP_MP_INIT) && !fsp_is_multi_phase_init_enabled())
 		do_mpinit_after_fsp();
@@ -205,6 +216,15 @@ static void do_silicon_init(struct fsp_header *hdr)
 	timestamp_add_now(TS_FSP_MULTI_PHASE_SI_INIT_END);
 	post_code(POSTCODE_FSP_MULTI_PHASE_SI_INIT_EXIT);
 
+	/*
+	 * If a BMP logo is enabled (`BMP_LOGO`) and the platform is
+	 * configured to skip the FSP for rendering logo bitmap
+	 * (`USE_COREBOOT_FOR_BMP_RENDERING`), then call the coreboot
+	 * native function to handle BMP logo loading and display.
+	 */
+	if (CONFIG(BMP_LOGO) && CONFIG(USE_COREBOOT_FOR_BMP_RENDERING))
+		soc_load_logo_by_coreboot();
+
 	/* Reinitialize CPUs if FSP-S has done MP Init */
 	if (CONFIG(USE_INTEL_FSP_MP_INIT))
 		do_mpinit_after_fsp();

From 210371e25babcc44f81a368990de11f658733a81 Mon Sep 17 00:00:00 2001
From: Subrata Banik <subratabanik@google.com>
Date: Mon, 5 May 2025 19:45:09 +0530
Subject: [PATCH 0933/3886] mainboard/google/fatcat: Configure middle logo
 vertical alignment

This commit overrides the `logo_valignment` setting in the
`common_soc_config` for the Fatcat board variant.

The vertical alignment for the firmware splash screen logo is now set to
`FW_SPLASH_VALIGNMENT_MIDDLE`, which places the top edge of the logo at
the vertical midpoint of the screen.

BUG=b:409718202
TEST=Built and booted google/fatcat.

Change-Id: I82cb0f9e06f23fb441011b9714284ac52a76d818
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87543
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
---
 src/mainboard/google/fatcat/variants/fatcat/overridetree.cb | 1 +
 1 file changed, 1 insertion(+)

diff --git a/src/mainboard/google/fatcat/variants/fatcat/overridetree.cb b/src/mainboard/google/fatcat/variants/fatcat/overridetree.cb
index 565aad6f98..858205902d 100644
--- a/src/mainboard/google/fatcat/variants/fatcat/overridetree.cb
+++ b/src/mainboard/google/fatcat/variants/fatcat/overridetree.cb
@@ -128,6 +128,7 @@ chip soc/intel/pantherlake
 	#| I2C5              | Touchpad                  |
 	#+-------------------+---------------------------+
 	register "common_soc_config" = "{
+		.logo_valignment = FW_SPLASH_VALIGNMENT_MIDDLE,
 		.chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT,
 		.i2c[1] = {
 			.speed = I2C_SPEED_FAST,

From 0ca46ac0d257f123fbc8c0d09f987b5dc0b9b9b0 Mon Sep 17 00:00:00 2001
From: Subrata Banik <subratabanik@google.com>
Date: Mon, 5 May 2025 19:43:12 +0530
Subject: [PATCH 0934/3886] soc/intel/pantherlake: Enable coreboot native logo
 rendering

This commit enables the `USE_COREBOOT_FOR_BMP_RENDERING` Kconfig option for
Panther Lake.

This allows the platform to utilize coreboot's native logo rendering
capabilities after the FSP initializes the display.

Additionally, this commit adds temporary MMIO definitions for the
Panther Lake I/O map: GMADR_BASE (0xB0000000) and GMADR_SIZE
(0x10000000). These definitions are necessary to program the IGD LMEM
BAR for accessible framebuffer and to enable Write Combine (WC) MTRR
caching for the LMEM BAR.

BUG=b:409718202
TEST=Built and booted google/fatcat. Verified boot splash was rendered
by coreboot as `USE_COREBOOT_FOR_BMP_RENDERING` was set to `y`.

Observed a slight delay (~10-30ms) in displaying BMP image with native
coreboot implementation compared to FSP-based rendering.

Change-Id: I658db63906e051fa82f3297f039f9e3c814df43f
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87542
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
---
 src/soc/intel/pantherlake/Kconfig             | 1 +
 src/soc/intel/pantherlake/include/soc/iomap.h | 4 ++++
 2 files changed, 5 insertions(+)

diff --git a/src/soc/intel/pantherlake/Kconfig b/src/soc/intel/pantherlake/Kconfig
index df14a2fe91..6787642f24 100644
--- a/src/soc/intel/pantherlake/Kconfig
+++ b/src/soc/intel/pantherlake/Kconfig
@@ -104,6 +104,7 @@ config SOC_INTEL_PANTHERLAKE_BASE
 	select TSC_MONOTONIC_TIMER
 	select UDELAY_TSC
 	select UDK_202302_BINDING
+	select USE_COREBOOT_FOR_BMP_RENDERING
 	select USE_X86_64_SUPPORT
 	select X86_INIT_NEED_1_SIPI
 	help
diff --git a/src/soc/intel/pantherlake/include/soc/iomap.h b/src/soc/intel/pantherlake/include/soc/iomap.h
index 0bd56975a9..fac9c03f1c 100644
--- a/src/soc/intel/pantherlake/include/soc/iomap.h
+++ b/src/soc/intel/pantherlake/include/soc/iomap.h
@@ -86,6 +86,10 @@
 #define IOM_BASE_SIZE		0x10000
 #define IOM_BASE_ADDR_MAX	0x401080ffff /* ((IOM_BASE_ADDR + IOM_BASE_SIZE) - 1) */
 
+/* Temporary MMIO address for GMADR (aka LMEMBAR) with 256MB */
+#define GMADR_BASE		0xB0000000
+#define GMADR_SIZE		0x10000000
+
 /* I/O port address space */
 #define ACPI_BASE_ADDRESS	0x1800
 #define ACPI_BASE_SIZE		0x100

From 7f826fddc55c53bb48374b81dcfd7f5e133f9047 Mon Sep 17 00:00:00 2001
From: Bora Guvendik <bora.guvendik@intel.com>
Date: Wed, 7 May 2025 11:00:34 -0700
Subject: [PATCH 0935/3886] mb/intel/ptlrvp: Compile variant.c in ramstage for
 ptlrvp
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

In the mainboard directory for Intel's ptlrvp variant, ensure that the
`variant.c` file is compiled during the ramstage build process. This
adjustment enables the execution of variant_update_soc_chip_config()
for ptlrvp in ramstage, addressing CNVi Wi-Fi-related issues.

BUG=None
TEST=Verify that variant.c is compiled correctly in ramstage for
ptlrvp.

Change-Id: Iec9591aac536abfdd36dfba8a8fea689830ee41a
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87570
Reviewed-by: Zhixing Ma <zhixing.ma@intel.com>
Reviewed-by: Jamie Ryu <jamie.m.ryu@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Reviewed-by: Cliff Huang <cliff.huang@intel.com>
---
 src/mainboard/intel/ptlrvp/variants/ptlrvp/Makefile.mk | 1 +
 1 file changed, 1 insertion(+)

diff --git a/src/mainboard/intel/ptlrvp/variants/ptlrvp/Makefile.mk b/src/mainboard/intel/ptlrvp/variants/ptlrvp/Makefile.mk
index b9f1fd15dd..598167cbe4 100644
--- a/src/mainboard/intel/ptlrvp/variants/ptlrvp/Makefile.mk
+++ b/src/mainboard/intel/ptlrvp/variants/ptlrvp/Makefile.mk
@@ -7,3 +7,4 @@ romstage-$(CONFIG_FW_CONFIG) += fw_config.c
 ramstage-y += gpio.c
 romstage-$(CONFIG_FW_CONFIG) += variant.c
 ramstage-$(CONFIG_FW_CONFIG) += fw_config.c
+ramstage-$(CONFIG_FW_CONFIG) += variant.c

From 40b62ff6c4847279aea885afd3f138aeb2915483 Mon Sep 17 00:00:00 2001
From: Bora Guvendik <bora.guvendik@intel.com>
Date: Tue, 22 Apr 2025 11:28:19 -0700
Subject: [PATCH 0936/3886] mb/intel/ptlrvp: Add memory configuration support
 for T4 LP5 board
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

This commit introduces support for the T4 LP5 board memory
configuration within the ptlrvp mainboard. The addition includes
defining the specific memory configurations such as data and strobe
signal mappings, early command training, and memory part ID
assignments. By implementing these changes, compatibility and
functionality are ensured for systems using the T4 LP5 board.

The memory configuration is specified for LP5 type memory with
detailed DQ and DQS mapping for different DDR channels. This
facilitates accurate signal routing and memory initialization.
Additionally, updates to associated Makefiles and documentation files
reflect these new memory parts (Hynix H58G56BK8BX068) and their IDs,
ensuring proper recognition and usage during system builds.

BUG=none
TEST=Build and verify system initialization on the T4 LP5 board with
the updated memory configuration. Confirm that memory training and
setup proceed correctly with the newly supported memory part.

Change-Id: Ia6e862af8c322fe4467465557c416d4171796e83
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87422
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 .../intel/ptlrvp/variants/ptlrvp/memory.c     | 65 ++++++++++++++++++-
 .../ptlrvp/variants/ptlrvp/memory/Makefile.mk |  1 +
 .../ptlrvp/memory/dram_id.generated.txt       |  1 +
 .../variants/ptlrvp/memory/mem_parts_used.txt |  1 +
 4 files changed, 66 insertions(+), 2 deletions(-)

diff --git a/src/mainboard/intel/ptlrvp/variants/ptlrvp/memory.c b/src/mainboard/intel/ptlrvp/variants/ptlrvp/memory.c
index 6a1706fe9f..350405dc29 100644
--- a/src/mainboard/intel/ptlrvp/variants/ptlrvp/memory.c
+++ b/src/mainboard/intel/ptlrvp/variants/ptlrvp/memory.c
@@ -65,7 +65,7 @@ static const struct mb_cfg gcs_mem_config = {
 	},
 };
 
-static const struct mb_cfg lp5_mem_config = {
+static const struct mb_cfg lp5_t3_mem_config = {
 	.type = MEM_TYPE_LP5X,
 
 	.lpx_dq_map = {
@@ -125,6 +125,66 @@ static const struct mb_cfg lp5_mem_config = {
 	},
 };
 
+static const struct mb_cfg lp5_t4_mem_config = {
+	.type = MEM_TYPE_LP5X,
+
+	.lpx_dq_map = {
+		.ddr0 = {
+			.dq0 = {  10, 8,  11, 9,  15, 12, 14, 13 },
+			.dq1 = {  6,  7,  5,  4,  3,  1,  0,  2 },
+		},
+		.ddr1 = {
+			.dq0 = {  1,  0,  3,  2,  7,  6,  5,  4 },
+			.dq1 = {  14, 13, 12, 15, 11, 9,  8,  10 },
+		},
+		.ddr2 = {
+			.dq0 = {  13, 14, 12, 15, 8,  10, 9,  11 },
+			.dq1 = {  6,  7,  5,  4,  1,  3,  2,  0 },
+		},
+		.ddr3 = {
+			.dq0 = {  6,  5,  7,  4,  3,  2,  0,  1 },
+			.dq1 = {  14, 13, 12, 15, 11, 9,  8,  10 },
+		},
+		.ddr4 = {
+			.dq0 = {  10, 8,  9,  11, 13, 12, 14, 15 },
+			.dq1 = {  1,  3,  0,  2,  4,  7,  5,  6 },
+		},
+		.ddr5 = {
+			.dq0 = {  1,  0,  2,  3,  7,  6,  5,  4 },
+			.dq1 = {  10, 8,  11, 9,  13, 12, 14, 15 },
+		},
+		.ddr6 = {
+			.dq0 = {  10, 8,  11, 9,  13, 12, 14, 15 },
+			.dq1 = {  6,  5,  7,  4,  0,  1,  2,  3 },
+		},
+		.ddr7 = {
+			.dq0 = {  1,  0,  2,  3,  7,  4,  6,  5 },
+			.dq1 = {  14, 13, 15, 12, 10, 11, 9,  8 },
+		},
+	},
+
+	.lpx_dqs_map = {
+		.ddr0 = { .dqs0 = 1, .dqs1 = 0 },
+		.ddr1 = { .dqs0 = 0, .dqs1 = 1 },
+		.ddr2 = { .dqs0 = 1, .dqs1 = 0 },
+		.ddr3 = { .dqs0 = 0, .dqs1 = 1 },
+		.ddr4 = { .dqs0 = 1, .dqs1 = 0 },
+		.ddr5 = { .dqs0 = 0, .dqs1 = 1 },
+		.ddr6 = { .dqs0 = 1, .dqs1 = 0 },
+		.ddr7 = { .dqs0 = 0, .dqs1 = 1 }
+	},
+
+	.ect = true, /* Early Command Training */
+
+	.lp_ddr_dq_dqs_re_training = 1,
+
+	.user_bd = BOARD_TYPE_ULT_ULX,
+
+	.lp5x_config = {
+		.ccc_config = 0xFF,
+	},
+};
+
 static const struct mb_cfg ddr5_mem_config = {
 	.type = MEM_TYPE_DDR5,
 
@@ -149,8 +209,9 @@ const struct mb_cfg *variant_memory_params(void)
 
 	switch (board_id) {
 	case PTLP_LP5_T3_RVP:
+		return &lp5_t3_mem_config;
 	case PTLP_LP5_T4_RVP:
-		return &lp5_mem_config;
+		return &lp5_t4_mem_config;
 	case GCS_32GB:
 	case GCS_64GB:
 		return &gcs_mem_config;
diff --git a/src/mainboard/intel/ptlrvp/variants/ptlrvp/memory/Makefile.mk b/src/mainboard/intel/ptlrvp/variants/ptlrvp/memory/Makefile.mk
index 1a93597f4e..5575815d1b 100644
--- a/src/mainboard/intel/ptlrvp/variants/ptlrvp/memory/Makefile.mk
+++ b/src/mainboard/intel/ptlrvp/variants/ptlrvp/memory/Makefile.mk
@@ -6,3 +6,4 @@
 SPD_SOURCES =
 SPD_SOURCES += spd/lp5/set-0/spd-7.hex      # ID = 0(0b0000)  Parts = H58G56BK7BX068
 SPD_SOURCES += spd/lp5/set-0/spd-10.hex      # ID = 1(0b0001)  Parts = H58G66BK8BX067
+SPD_SOURCES += spd/lp5/set-0/spd-11.hex      # ID = 2(0b0010)  Parts = H58G56BK8BX068
diff --git a/src/mainboard/intel/ptlrvp/variants/ptlrvp/memory/dram_id.generated.txt b/src/mainboard/intel/ptlrvp/variants/ptlrvp/memory/dram_id.generated.txt
index 7f7236d0ec..244c063804 100644
--- a/src/mainboard/intel/ptlrvp/variants/ptlrvp/memory/dram_id.generated.txt
+++ b/src/mainboard/intel/ptlrvp/variants/ptlrvp/memory/dram_id.generated.txt
@@ -6,3 +6,4 @@
 DRAM Part Name                 ID to assign
 H58G56BK7BX068                 0 (0000)
 H58G66BK8BX067                 1 (0001)
+H58G56BK8BX068                 2 (0010)
diff --git a/src/mainboard/intel/ptlrvp/variants/ptlrvp/memory/mem_parts_used.txt b/src/mainboard/intel/ptlrvp/variants/ptlrvp/memory/mem_parts_used.txt
index 86a6e201d7..98255ad4d3 100644
--- a/src/mainboard/intel/ptlrvp/variants/ptlrvp/memory/mem_parts_used.txt
+++ b/src/mainboard/intel/ptlrvp/variants/ptlrvp/memory/mem_parts_used.txt
@@ -11,3 +11,4 @@
 # Part Name
 H58G56BK7BX068
 H58G66BK8BX067
+H58G56BK8BX068

From 2706ce0266214d4bb15de6232f08a4ffb9382d56 Mon Sep 17 00:00:00 2001
From: Cliff Huang <cliff.huang@intel.com>
Date: Thu, 24 Apr 2025 21:58:58 -0700
Subject: [PATCH 0937/3886] mb/intel/ptlrvp: Add GPIO support for T4 LP5 board
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

This commit introduces the GPIO configuration support for the T4 LP5
Reference Validation Platform (RVP). It includes a table that outlines
the differences in GPIO configuration between the T3 LP5 RVP and T4 LP5
RVP. The GPIO differences are applied when the board ID is recognized as
T4.

BUG=none
TEST=Ensure the T4 RVP boots to the OS, then verify the GPIO pad
configurations by inspecting the output from /sys/kernel/debug/pinctrl.
Check that the GPIO PADs match the expected configuration for the T4
board.

Signed-off-by: Cliff Huang <cliff.huang@intel.com>
Change-Id: Ica870752bed2ba47c73d8fcd5f2f41b9cc6db65a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87447
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
---
 src/mainboard/intel/ptlrvp/mainboard.c        |  7 ++-
 .../baseboard/include/baseboard/variants.h    |  1 +
 .../intel/ptlrvp/variants/ptlrvp/gpio.c       | 63 ++++++++++++++++++-
 3 files changed, 66 insertions(+), 5 deletions(-)

diff --git a/src/mainboard/intel/ptlrvp/mainboard.c b/src/mainboard/intel/ptlrvp/mainboard.c
index e14c5ace79..5b80d9d650 100644
--- a/src/mainboard/intel/ptlrvp/mainboard.c
+++ b/src/mainboard/intel/ptlrvp/mainboard.c
@@ -28,12 +28,15 @@ void __weak variant_update_soc_chip_config(struct soc_intel_pantherlake_config *
 static void mainboard_init(void *chip_info)
 {
 	struct pad_config *padbased_table;
-	const struct pad_config *base_pads;
-	size_t base_num;
+	const struct pad_config *base_pads, *variant_diff_pads;
+	size_t base_num, variant_diff_num;
 
 	padbased_table = new_padbased_table();
 	base_pads = variant_gpio_table(&base_num);
 	gpio_padbased_override(padbased_table, base_pads, base_num);
+	variant_diff_pads = variant_board_gpio_diff_table(&variant_diff_num);
+	if (variant_diff_pads)
+		gpio_padbased_override(padbased_table, variant_diff_pads, variant_diff_num);
 	fw_config_gpio_padbased_override(padbased_table);
 	gpio_configure_pads_with_padbased(padbased_table);
 	free(padbased_table);
diff --git a/src/mainboard/intel/ptlrvp/variants/baseboard/include/baseboard/variants.h b/src/mainboard/intel/ptlrvp/variants/baseboard/include/baseboard/variants.h
index 0ee09a5835..05ddf5bb5f 100644
--- a/src/mainboard/intel/ptlrvp/variants/baseboard/include/baseboard/variants.h
+++ b/src/mainboard/intel/ptlrvp/variants/baseboard/include/baseboard/variants.h
@@ -23,6 +23,7 @@ enum ptl_boardid {
  */
 
 const struct pad_config *variant_gpio_table(size_t *num);
+const struct pad_config *variant_board_gpio_diff_table(size_t *num);
 const struct pad_config *variant_early_gpio_table(size_t *num);
 const struct pad_config *variant_romstage_gpio_table(size_t *num);
 void fw_config_configure_pre_mem_gpio(void);
diff --git a/src/mainboard/intel/ptlrvp/variants/ptlrvp/gpio.c b/src/mainboard/intel/ptlrvp/variants/ptlrvp/gpio.c
index 9531065689..7b4dbe3c9f 100644
--- a/src/mainboard/intel/ptlrvp/variants/ptlrvp/gpio.c
+++ b/src/mainboard/intel/ptlrvp/variants/ptlrvp/gpio.c
@@ -3,10 +3,11 @@
 #include <baseboard/gpio.h>
 #include <baseboard/variants.h>
 #include <boardid.h>
+#include <ec/intel/board_id.h>
 #include <soc/gpio.h>
 
 /* Pad configuration in ramstage*/
-static const struct pad_config gpio_table[] = {
+static const struct pad_config t3_gpio_table[] = {
 	/* GPP_A00:     ESPI_IO0_EC_R */
 	/*  GPP_A00 : GPP_A00 ==> ESPI_IO0_EC_R configured on reset, do not touch */
 
@@ -391,10 +392,48 @@ static const struct pad_config romstage_gpio_table[] = {
 	PAD_CFG_NF(GPP_C01, NONE, DEEP, NF1),
 };
 
+/* Pad difference in ramstage for LP5 T4 RVP */
+static const struct pad_config t4_gpio_diff_table[] = {
+	/* GPP_B09:     MOD_TCSS2_DISP_HPD1 */
+	PAD_CFG_NF(GPP_B09, NONE, DEEP, NF2),
+	/* GPP_B10:     MOD_TCSS1_DISP_HPD2 */
+	PAD_CFG_NF(GPP_B10, NONE, DEEP, NF2),
+	/* GPP_B11:     GEN4_SSD_PWREN */
+	PAD_CFG_GPO(GPP_B11, 1, PLTRST),
+
+	/* GPP_B14:     Not used */
+	PAD_NC(GPP_B14, NONE),
+
+	/* GPP_B17:     MOD_TCSS2_LSX_DIR_SEL_EDP_VDD_EN */
+	PAD_CFG_NF(GPP_B17, NONE, DEEP, NF2),
+
+	/* GPP_C06:     X4_PCIE_SLOT_PWR_EN_N */
+	PAD_CFG_GPO(GPP_C06, 0, DEEP),
+	/* GPP_C07:     X4_DT_PCIE_RST_N */
+	PAD_CFG_GPO(GPP_C07, 1, DEEP),
+
+	/* GPP_D01:     MOD_TCSS2_TYP_A_VBUS_EN_EDP_BKLT_EN */
+	PAD_CFG_NF(GPP_D01, NONE, DEEP, NF2),
+	/* GPP_D02:     MOD_TCSS2_EDP_BKLT_CTRL */
+	PAD_CFG_NF(GPP_D02, NONE, DEEP, NF2),
+
+	/* GPP_D20:     CLKREQ7_X4_GEN5_DT_CEM_SLOT_N */
+	PAD_CFG_NF(GPP_D20, NONE, DEEP, NF1),
+
+	/* GPP_E08:     M2_GEN4_SSD_RESET_N */
+	PAD_CFG_GPO(GPP_E08, 1, PLTRST),
+
+	/* GPP_F23:     SMC_LID */
+	PAD_CFG_GPI_TRIG_OWN(GPP_F23, NONE, DEEP, LEVEL, ACPI),
+
+	/* GPP_V17:     TCP_RT_S0IX_ENTRY_EXIT_N */
+	PAD_CFG_GPO(GPP_V17, 1, PLTRST),
+};
+
 const struct pad_config *variant_gpio_table(size_t *num)
 {
-	*num = ARRAY_SIZE(gpio_table);
-	return gpio_table;
+	*num = ARRAY_SIZE(t3_gpio_table);
+	return t3_gpio_table;
 }
 
 const struct pad_config *variant_early_gpio_table(size_t *num)
@@ -410,6 +449,24 @@ const struct pad_config *variant_romstage_gpio_table(size_t *num)
 	return romstage_gpio_table;
 }
 
+const struct pad_config *variant_board_gpio_diff_table(size_t *num)
+{
+	int board_id = get_rvp_board_id();
+
+	switch (board_id) {
+	case PTLP_LP5_T3_RVP:
+		return NULL;
+	case PTLP_LP5_T4_RVP:
+		*num = ARRAY_SIZE(t4_gpio_diff_table);
+		return t4_gpio_diff_table;
+	case GCS_32GB:
+	case GCS_64GB:
+		return NULL;
+	default:
+		die("Unknown board ID = 0x%x\n", board_id);
+	}
+}
+
 static const struct cros_gpio cros_gpios[] = {
 	CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE0_NAME),
 	CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE1_NAME),

From 5bf88a44e9607cad5d75e87c55917815948b3bf1 Mon Sep 17 00:00:00 2001
From: Patrick Rudolph <patrick.rudolph@9elements.com>
Date: Mon, 31 Mar 2025 11:19:07 +0200
Subject: [PATCH 0938/3886] drivers/smmstore: Support 64-bit MMIO addresses

Currently the SMMSTOREv2 only supports MMIO ROM below 4GiB. As the
space below 4GiB is typically limited on x86, add support for extended
MMIO ROM windows as found on recent hardware.

Allow the SMMSTOREv2 to be memory mapped above 4GiB by adding a new
field to the coreboot table called 'mmap_addr'. The users outside
of coreboot must check the size field of the coreboot struct to
determine if mmap_addr is supported. When it is it holds the
64-bit physical address to the MMIO ROM window.
The old 'mmap_addr' was renamed to 'mmap_addr_deprecated' to indicate
that it should not be used any more.

Change-Id: I1131cfa5cdbf92bbd33de3e5b22a305136eec9f7
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87114
Reviewed-by: Naresh Solanki <naresh.solanki@9elements.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
---
 Documentation/drivers/smmstorev2.md           | 25 +++++++++++++------
 .../include/commonlib/coreboot_tables.h       |  8 +++++-
 src/drivers/smmstore/ramstage.c               |  4 +++
 src/include/smmstore.h                        |  2 +-
 4 files changed, 30 insertions(+), 9 deletions(-)

diff --git a/Documentation/drivers/smmstorev2.md b/Documentation/drivers/smmstorev2.md
index cf714835a5..b29ffa886f 100644
--- a/Documentation/drivers/smmstorev2.md
+++ b/Documentation/drivers/smmstorev2.md
@@ -74,19 +74,30 @@ has to read the coreboot table with tag `0x0039`, containing:
 struct lb_smmstorev2 {
 	uint32_t tag;
 	uint32_t size;
-	uint32_t num_blocks;	/* Number of writeable blocks in SMM */
-	uint32_t block_size;	/* Size of a block in byte. Default: 64 KiB */
-	uint32_t mmap_addr;	/* MMIO address of the store for read only access */
-	uint32_t com_buffer;	/* Physical address of the communication buffer */
-	uint32_t com_buffer_size;	/* Size of the communication buffer in byte */
-	uint8_t apm_cmd;	/* The command byte to write to the APM I/O port */
-	uint8_t unused[3];	/* Set to zero */
+	uint32_t num_blocks;		/* Number of writable blocks in SMM */
+	uint32_t block_size;		/* Size of a block in byte. Default: 64 KiB */
+	uint32_t mmap_addr_deprecated;	/* 32-bit MMIO address of the store for read only access.
+					   Prefer 'mmap_addr' for new software.
+					   Zero when the address won't fit into 32-bits. */
+	uint32_t com_buffer;		/* Physical address of the communication buffer */
+	uint32_t com_buffer_size;	/* Size of the communication buffer in bytes */
+	uint8_t apm_cmd;		/* The command byte to write to the APM I/O port */
+	uint8_t unused[3];		/* Set to zero */
+	uint64_t mmap_addr;		/* 64-bit MMIO address of the store for read only access.
+					   Introduced after the initial implementation. Users of
+					   this table must check the 'size' field to detect if its
+					   written out by coreboot. */
 };
 ```
 
 The absence of this coreboot table entry indicates that there's no
 SMMSTOREv2 support.
 
+`mmap_addr` is an optional field added after the initial implementation.
+Users of this table must check the size field to know if it's written by coreboot.
+In case it's not present 'mmap_addr_deprecated' is to be used as the SPI ROM MMIO
+address and it must be below 4 GiB.
+
 ### Blocks
 
 The SMMSTOREv2 splits the SMMSTORE FMAP partition into smaller chunks
diff --git a/src/commonlib/include/commonlib/coreboot_tables.h b/src/commonlib/include/commonlib/coreboot_tables.h
index 78dbe8ef4c..7860a413ce 100644
--- a/src/commonlib/include/commonlib/coreboot_tables.h
+++ b/src/commonlib/include/commonlib/coreboot_tables.h
@@ -539,11 +539,17 @@ struct lb_smmstorev2 {
 	uint32_t size;
 	uint32_t num_blocks;		/* Number of writable blocks in SMM */
 	uint32_t block_size;		/* Size of a block in byte. Default: 64 KiB */
-	uint32_t mmap_addr;		/* MMIO address of the store for read only access */
+	uint32_t mmap_addr_deprecated;	/* 32-bit MMIO address of the store for read only access.
+					   Prefer 'mmap_addr' for new software.
+					   Zero when the address won't fit into 32-bits. */
 	uint32_t com_buffer;		/* Physical address of the communication buffer */
 	uint32_t com_buffer_size;	/* Size of the communication buffer in bytes */
 	uint8_t apm_cmd;		/* The command byte to write to the APM I/O port */
 	uint8_t unused[3];		/* Set to zero */
+	uint64_t mmap_addr;		/* 64-bit MMIO address of the store for read only access.
+					   Introduced after the initial implementation. Users of
+					   this table must check the 'size' field to detect if its
+					   written out by coreboot. */
 };
 
 enum lb_tpm_ppi_tpm_version {
diff --git a/src/drivers/smmstore/ramstage.c b/src/drivers/smmstore/ramstage.c
index 1cbf9fb28a..507678754c 100644
--- a/src/drivers/smmstore/ramstage.c
+++ b/src/drivers/smmstore/ramstage.c
@@ -28,6 +28,10 @@ void lb_smmstorev2(struct lb_header *header)
 	store->size = sizeof(*store);
 	store->com_buffer = (uintptr_t)cbmem_entry_start(e);
 	store->com_buffer_size = cbmem_entry_size(e);
+	if (info.mmap_addr < 4ULL * GiB)
+		store->mmap_addr_deprecated = info.mmap_addr;
+	else
+		store->mmap_addr_deprecated = 0;
 	store->mmap_addr = info.mmap_addr;
 	store->num_blocks = info.num_blocks;
 	store->block_size = info.block_size;
diff --git a/src/include/smmstore.h b/src/include/smmstore.h
index 595fe8b29b..4ee4c55c75 100644
--- a/src/include/smmstore.h
+++ b/src/include/smmstore.h
@@ -69,7 +69,7 @@ struct smmstore_params_init {
 struct smmstore_params_info {
 	uint32_t num_blocks;
 	uint32_t block_size;
-	uint32_t mmap_addr;
+	uint64_t mmap_addr;
 } __packed;
 
 /*

From 21ca6701ffc41ddb1bae9b3d154f8df2d2635fe6 Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Tue, 29 Apr 2025 17:46:25 -0500
Subject: [PATCH 0939/3886] mb/google/{drallion,hatch,sarien}: Skip adding
 DTT/TCPU to SSDT
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

These three boards use <soc/intel/common/acpi/dptf/dptf.asl> and should skip generating the TCPU device via SSDT, so select
SOC_INTEL_COMMON_BLOCK_DTT_STATIC_ASL to make that happen.

TEST=build/boot drallion, hatch, and sarien. Dump ACPI and verify no
duplicate TCPU ACPI device, verify no ACPI errors in dmesg.

Change-Id: I6070e5291ce2476fc1c24d39583fcca94bed1395
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87482
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
---
 src/mainboard/google/drallion/Kconfig | 1 +
 src/mainboard/google/hatch/Kconfig    | 1 +
 src/mainboard/google/sarien/Kconfig   | 1 +
 3 files changed, 3 insertions(+)

diff --git a/src/mainboard/google/drallion/Kconfig b/src/mainboard/google/drallion/Kconfig
index 484fd027ca..cd14d2c10e 100644
--- a/src/mainboard/google/drallion/Kconfig
+++ b/src/mainboard/google/drallion/Kconfig
@@ -22,6 +22,7 @@ config BOARD_GOOGLE_BASEBOARD_DRALLION
 	select MAINBOARD_USES_IFD_EC_REGION
 	select SMBIOS_SERIAL_FROM_VPD if VPD
 	select SOC_INTEL_COMETLAKE_1
+	select SOC_INTEL_COMMON_BLOCK_DTT_STATIC_ASL
 	select SOC_INTEL_COMMON_BLOCK_HDA_VERB
 	select SOC_INTEL_COMMON_BLOCK_SMM_ESPI_DISABLE
 	select SYSTEM_TYPE_LAPTOP
diff --git a/src/mainboard/google/hatch/Kconfig b/src/mainboard/google/hatch/Kconfig
index 82a632692a..850234153f 100644
--- a/src/mainboard/google/hatch/Kconfig
+++ b/src/mainboard/google/hatch/Kconfig
@@ -26,6 +26,7 @@ config BOARD_GOOGLE_BASEBOARD_HATCH
 	select MAINBOARD_HAS_TPM2
 	select MB_HAS_ACTIVE_HIGH_SD_PWR_ENABLE
 	select SOC_INTEL_COMETLAKE_1
+	select SOC_INTEL_COMMON_BLOCK_DTT_STATIC_ASL
 	select SPI_TPM
 	select SYSTEM_TYPE_LAPTOP
 	select TPM_GOOGLE_CR50
diff --git a/src/mainboard/google/sarien/Kconfig b/src/mainboard/google/sarien/Kconfig
index 5f678aa4be..666fb8f7f0 100644
--- a/src/mainboard/google/sarien/Kconfig
+++ b/src/mainboard/google/sarien/Kconfig
@@ -20,6 +20,7 @@ config BOARD_GOOGLE_BASEBOARD_SARIEN
 	select MAINBOARD_HAS_TPM2
 	select MAINBOARD_USES_IFD_EC_REGION
 	select SMBIOS_SERIAL_FROM_VPD if VPD
+	select SOC_INTEL_COMMON_BLOCK_DTT_STATIC_ASL
 	select SOC_INTEL_COMMON_BLOCK_HDA_VERB
 	select SOC_INTEL_COMMON_BLOCK_SMM_ESPI_DISABLE
 	select SOC_INTEL_WHISKEYLAKE

From e8c724fe1a0bcfc2e8a69a0291ebdc1da1daf963 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Micha=C5=82=20Kope=C4=87?= <michal.kopec@3mdeb.com>
Date: Sat, 26 Oct 2024 13:15:38 +0200
Subject: [PATCH 0940/3886] mb/lenovo/m900_tiny: Update VBT to build 1037 with
 Kaby Lake gfx support
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Update VBT to one extracted from newer Lenovo UEFI, version FWKTBFA.

The newer VBT has build number 1037 and supports Kaby Lake graphics,
while the old VBT with build number 1000 only supports Skylake.

The old VBT starts with $VBT_SKYLAKE while the new one starts with
$VBT_KABYLAKE.

TEST=Insert CPU with integrated HD 630 graphics (i3-7100) and check if
all video outputs work in firmware.

Change-Id: I5e108d4ad8bf0663f3e1fa32145e40ea9babeac5
Signed-off-by: Michał Kopeć <michal.kopec@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84873
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
---
 src/mainboard/lenovo/m900_tiny/data.vbt | Bin 4608 -> 8192 bytes
 1 file changed, 0 insertions(+), 0 deletions(-)

diff --git a/src/mainboard/lenovo/m900_tiny/data.vbt b/src/mainboard/lenovo/m900_tiny/data.vbt
index 7e6fe3dc1399c6c0793e24ff34cf789f84da426b..4c26ae512bd8fd364796b3f273419252cf18968f 100644
GIT binary patch
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Swqfwq8Sw3*cVx|fI{yNu(0K;{


From 9154070320654f6b55884826db8835ca44066a40 Mon Sep 17 00:00:00 2001
From: Angel Pons <th3fanbus@gmail.com>
Date: Wed, 5 Mar 2025 12:57:46 +0100
Subject: [PATCH 0941/3886] mb/asus/h61-series: Add H61M-A/USB3

Add support for yet another of these LGA1155 boards. Nothing too fancy,
just another slightly different combination of the same chips.

Working:
- Booting to Arch Linux using SeaBIOS (current version)
- Native RAM init
- Realtek Ethernet NIC
- Some rear USB 2.0 and 3.0 (ASM1042) ports (did not test all)
- At least one SATA port (did not test all)
- libgfxinit to initialise a DVI-D display
- VBT (extracted from `/sys/kernel/debug/dri/0/i915_vbt`)
- PCIe x16 slot
- Both PCIe x1 slots
- EHCI debug (one of the rear USB 2.0 ports)

Not working:
- Automatic fan speed control (known limitation of Super I/O code)

Untested:
- HDMI, VGA
- Internal flashing (board was ported using an EM100Pro)
- Audio
- Front USB ports
- PS/2 ports

Change-Id: I18b116d265e0b7105e13a317b552aab0e4bbc762
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86726
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/asus/h61-series/Kconfig         |  21 +-
 src/mainboard/asus/h61-series/Kconfig.name    |   3 +
 .../variants/h61m-a_usb3/board_info.txt       |   6 +
 .../variants/h61m-a_usb3/cmos.default         |   7 +
 .../variants/h61m-a_usb3/cmos.layout          |  65 ++++++
 .../h61-series/variants/h61m-a_usb3/data.vbt  | Bin 0 -> 7168 bytes
 .../variants/h61m-a_usb3/early_init.c         |  29 +++
 .../variants/h61m-a_usb3/gma-mainboard.ads    |  21 ++
 .../h61-series/variants/h61m-a_usb3/gpio.c    | 211 ++++++++++++++++++
 .../variants/h61m-a_usb3/hda_verb.c           |  51 +++++
 .../variants/h61m-a_usb3/overridetree.cb      |  82 +++++++
 11 files changed, 491 insertions(+), 5 deletions(-)
 create mode 100644 src/mainboard/asus/h61-series/variants/h61m-a_usb3/board_info.txt
 create mode 100644 src/mainboard/asus/h61-series/variants/h61m-a_usb3/cmos.default
 create mode 100644 src/mainboard/asus/h61-series/variants/h61m-a_usb3/cmos.layout
 create mode 100644 src/mainboard/asus/h61-series/variants/h61m-a_usb3/data.vbt
 create mode 100644 src/mainboard/asus/h61-series/variants/h61m-a_usb3/early_init.c
 create mode 100644 src/mainboard/asus/h61-series/variants/h61m-a_usb3/gma-mainboard.ads
 create mode 100644 src/mainboard/asus/h61-series/variants/h61m-a_usb3/gpio.c
 create mode 100644 src/mainboard/asus/h61-series/variants/h61m-a_usb3/hda_verb.c
 create mode 100644 src/mainboard/asus/h61-series/variants/h61m-a_usb3/overridetree.cb

diff --git a/src/mainboard/asus/h61-series/Kconfig b/src/mainboard/asus/h61-series/Kconfig
index 4c4fd7e2be..d09ed1e244 100644
--- a/src/mainboard/asus/h61-series/Kconfig
+++ b/src/mainboard/asus/h61-series/Kconfig
@@ -12,6 +12,16 @@ config BOARD_ASUS_H61_SERIES
 	select SOUTHBRIDGE_INTEL_BD82X6X
 	select USE_NATIVE_RAMINIT
 
+config BOARD_ASUS_H61M_A_USB3
+	select BOARD_ASUS_H61_SERIES
+	select BOARD_ROMSIZE_KB_8192
+	select HAVE_CMOS_DEFAULT
+	select HAVE_OPTION_TABLE
+	select NO_UART_ON_SUPERIO
+	select REALTEK_8168_RESET
+	select RT8168_SET_LED_MODE
+	select SUPERIO_NUVOTON_NCT6779D
+
 config BOARD_ASUS_H61M_CS
 	select BOARD_ASUS_H61_SERIES
 	select BOARD_ROMSIZE_KB_8192
@@ -75,12 +85,13 @@ config MAINBOARD_DIR
 	default "asus/h61-series"
 
 config VARIANT_DIR
-	default "h61m-cs"          if BOARD_ASUS_H61M_CS
-	default "p8h61-m_lx"       if BOARD_ASUS_P8H61_M_LX
-	default "p8h61-m_lx3_r2_0" if BOARD_ASUS_P8H61_M_LX3_R2_0
-	default "p8h61-m_pro"      if BOARD_ASUS_P8H61_M_PRO
+	default "h61m-a_usb3"        if BOARD_ASUS_H61M_A_USB3
+	default "h61m-cs"            if BOARD_ASUS_H61M_CS
+	default "p8h61-m_lx"         if BOARD_ASUS_P8H61_M_LX
+	default "p8h61-m_lx3_r2_0"   if BOARD_ASUS_P8H61_M_LX3_R2_0
+	default "p8h61-m_pro"        if BOARD_ASUS_P8H61_M_PRO
 	default "p8h61-m_pro_cm6630" if BOARD_ASUS_P8H61_M_PRO_CM6630
-	default "p8h67-i_deluxe"   if BOARD_ASUS_P8H67_I_DELUXE
+	default "p8h67-i_deluxe"     if BOARD_ASUS_P8H67_I_DELUXE
 
 config MAINBOARD_PART_NUMBER
 	default "H61M-CS"          if BOARD_ASUS_H61M_CS
diff --git a/src/mainboard/asus/h61-series/Kconfig.name b/src/mainboard/asus/h61-series/Kconfig.name
index eee48c0f91..e1e2317f09 100644
--- a/src/mainboard/asus/h61-series/Kconfig.name
+++ b/src/mainboard/asus/h61-series/Kconfig.name
@@ -1,5 +1,8 @@
 ## SPDX-License-Identifier: GPL-2.0-only
 
+config BOARD_ASUS_H61M_A_USB3
+	bool "H61M-A/USB3"
+
 config BOARD_ASUS_H61M_CS
 	bool "H61M-CS"
 
diff --git a/src/mainboard/asus/h61-series/variants/h61m-a_usb3/board_info.txt b/src/mainboard/asus/h61-series/variants/h61m-a_usb3/board_info.txt
new file mode 100644
index 0000000000..9008bcc862
--- /dev/null
+++ b/src/mainboard/asus/h61-series/variants/h61m-a_usb3/board_info.txt
@@ -0,0 +1,6 @@
+Category: desktop
+Board URL: https://www.asus.com/supportonly/h61mausb3/helpdesk_knowledge/
+ROM package: DIP-8
+ROM protocol: SPI
+ROM socketed: y
+Flashrom support: y
diff --git a/src/mainboard/asus/h61-series/variants/h61m-a_usb3/cmos.default b/src/mainboard/asus/h61-series/variants/h61m-a_usb3/cmos.default
new file mode 100644
index 0000000000..76c0b2d6ce
--- /dev/null
+++ b/src/mainboard/asus/h61-series/variants/h61m-a_usb3/cmos.default
@@ -0,0 +1,7 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
+boot_option=Fallback
+debug_level=Debug
+power_on_after_fail=Enable
+sata_mode=AHCI
+gfx_uma_size=32M
diff --git a/src/mainboard/asus/h61-series/variants/h61m-a_usb3/cmos.layout b/src/mainboard/asus/h61-series/variants/h61m-a_usb3/cmos.layout
new file mode 100644
index 0000000000..227711afa2
--- /dev/null
+++ b/src/mainboard/asus/h61-series/variants/h61m-a_usb3/cmos.layout
@@ -0,0 +1,65 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
+# -----------------------------------------------------------------
+entries
+
+# -----------------------------------------------------------------
+0	120	r	0	reserved_memory
+
+# -----------------------------------------------------------------
+# RTC_BOOT_BYTE (coreboot hardcoded)
+384	1	e	4	boot_option
+388	4	h	0	reboot_counter
+
+# -----------------------------------------------------------------
+# coreboot config options: console
+395	4	e	6	debug_level
+
+# coreboot config options: southbridge
+409	2	e	7	power_on_after_fail
+
+421	1	e	9	sata_mode
+
+# coreboot config options: cpu
+
+# coreboot config options: northbridge
+432	3	e	11	gfx_uma_size
+
+# coreboot config options: check sums
+984	16	h	0	check_sum
+
+# -----------------------------------------------------------------
+
+enumerations
+
+#ID	value	text
+1	0	Disable
+1	1	Enable
+4	0	Fallback
+4	1	Normal
+6	0	Emergency
+6	1	Alert
+6	2	Critical
+6	3	Error
+6	4	Warning
+6	5	Notice
+6	6	Info
+6	7	Debug
+6	8	Spew
+7	0	Disable
+7	1	Enable
+7	2	Keep
+9	0	AHCI
+9	1	IDE
+11	0	32M
+11	1	64M
+11	2	96M
+11	3	128M
+11	4	160M
+11	5	192M
+11	6	224M
+
+# -----------------------------------------------------------------
+checksums
+
+checksum 392 439 984
diff --git a/src/mainboard/asus/h61-series/variants/h61m-a_usb3/data.vbt b/src/mainboard/asus/h61-series/variants/h61m-a_usb3/data.vbt
new file mode 100644
index 0000000000000000000000000000000000000000..7739a7fb36d27f9ee7c1bb2e0dc94e001e8d99a1
GIT binary patch
literal 7168
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literal 0
HcmV?d00001

diff --git a/src/mainboard/asus/h61-series/variants/h61m-a_usb3/early_init.c b/src/mainboard/asus/h61-series/variants/h61m-a_usb3/early_init.c
new file mode 100644
index 0000000000..37da16c471
--- /dev/null
+++ b/src/mainboard/asus/h61-series/variants/h61m-a_usb3/early_init.c
@@ -0,0 +1,29 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <bootblock_common.h>
+#include <device/pnp_ops.h>
+#include <superio/nuvoton/common/nuvoton.h>
+#include <superio/nuvoton/nct6779d/nct6779d.h>
+
+#define GLOBAL_DEV PNP_DEV(0x2e, 0)
+#define ACPI_DEV   PNP_DEV(0x2e, NCT6779D_ACPI)
+
+void bootblock_mainboard_early_init(void)
+{
+	nuvoton_pnp_enter_conf_state(GLOBAL_DEV);
+
+	/* Select SIO pin states. */
+	pnp_write_config(GLOBAL_DEV, 0x1c, 0x71);
+	pnp_write_config(GLOBAL_DEV, 0x1d, 0x0e);
+	pnp_write_config(GLOBAL_DEV, 0x22, 0xd7);
+	pnp_write_config(GLOBAL_DEV, 0x24, 0x00);
+	pnp_write_config(GLOBAL_DEV, 0x2a, 0x48);
+	pnp_write_config(GLOBAL_DEV, 0x2c, 0x00);
+	pnp_write_config(GLOBAL_DEV, 0x2f, 0x01);
+
+	/* Power RAM in S3. */
+	pnp_set_logical_device(ACPI_DEV);
+	pnp_write_config(ACPI_DEV, 0xe4, 0x10);
+
+	nuvoton_pnp_exit_conf_state(GLOBAL_DEV);
+}
diff --git a/src/mainboard/asus/h61-series/variants/h61m-a_usb3/gma-mainboard.ads b/src/mainboard/asus/h61-series/variants/h61m-a_usb3/gma-mainboard.ads
new file mode 100644
index 0000000000..20c53ef0f4
--- /dev/null
+++ b/src/mainboard/asus/h61-series/variants/h61m-a_usb3/gma-mainboard.ads
@@ -0,0 +1,21 @@
+-- SPDX-License-Identifier: GPL-2.0-or-later
+
+with HW.GFX.GMA;
+with HW.GFX.GMA.Display_Probing;
+
+use HW.GFX.GMA;
+use HW.GFX.GMA.Display_Probing;
+
+private package GMA.Mainboard is
+
+   -- For a three-pipe setup, bandwidth is shared between the 2nd and
+   -- the 3rd pipe. Thus, probe ports that likely have a high-resolution
+   -- display attached first.
+
+   ports : constant Port_List :=
+     (HDMI2, -- mainboard HDMI port
+      HDMI1, -- mainboard DVI-D port
+      Analog,
+      others => Disabled);
+
+end GMA.Mainboard;
diff --git a/src/mainboard/asus/h61-series/variants/h61m-a_usb3/gpio.c b/src/mainboard/asus/h61-series/variants/h61m-a_usb3/gpio.c
new file mode 100644
index 0000000000..66fc05a680
--- /dev/null
+++ b/src/mainboard/asus/h61-series/variants/h61m-a_usb3/gpio.c
@@ -0,0 +1,211 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <southbridge/intel/common/gpio.h>
+
+static const struct pch_gpio_set1 pch_gpio_set1_mode = {
+	.gpio0 = GPIO_MODE_GPIO,
+	.gpio1 = GPIO_MODE_GPIO,
+	.gpio2 = GPIO_MODE_GPIO,
+	.gpio3 = GPIO_MODE_GPIO,
+	.gpio4 = GPIO_MODE_GPIO,
+	.gpio5 = GPIO_MODE_GPIO,
+	.gpio6 = GPIO_MODE_GPIO,
+	.gpio7 = GPIO_MODE_GPIO,
+	.gpio8 = GPIO_MODE_GPIO,
+	.gpio9 = GPIO_MODE_NATIVE,
+	.gpio10 = GPIO_MODE_GPIO,
+	.gpio11 = GPIO_MODE_GPIO,
+	.gpio12 = GPIO_MODE_GPIO,
+	.gpio13 = GPIO_MODE_GPIO,
+	.gpio14 = GPIO_MODE_GPIO,
+	.gpio15 = GPIO_MODE_GPIO,
+	.gpio16 = GPIO_MODE_GPIO,
+	.gpio17 = GPIO_MODE_GPIO,
+	.gpio18 = GPIO_MODE_NATIVE,
+	.gpio19 = GPIO_MODE_GPIO,
+	.gpio20 = GPIO_MODE_GPIO,
+	.gpio21 = GPIO_MODE_GPIO,
+	.gpio22 = GPIO_MODE_GPIO,
+	.gpio23 = GPIO_MODE_GPIO,
+	.gpio24 = GPIO_MODE_GPIO,
+	.gpio25 = GPIO_MODE_NATIVE,
+	.gpio26 = GPIO_MODE_NATIVE,
+	.gpio27 = GPIO_MODE_GPIO,
+	.gpio28 = GPIO_MODE_GPIO,
+	.gpio29 = GPIO_MODE_GPIO,
+	.gpio30 = GPIO_MODE_GPIO,
+	.gpio31 = GPIO_MODE_GPIO,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_direction = {
+	.gpio0 = GPIO_DIR_OUTPUT,
+	.gpio1 = GPIO_DIR_INPUT,
+	.gpio2 = GPIO_DIR_INPUT,
+	.gpio3 = GPIO_DIR_INPUT,
+	.gpio4 = GPIO_DIR_INPUT,
+	.gpio5 = GPIO_DIR_INPUT,
+	.gpio6 = GPIO_DIR_INPUT,
+	.gpio7 = GPIO_DIR_INPUT,
+	.gpio8 = GPIO_DIR_INPUT,
+	.gpio10 = GPIO_DIR_INPUT,
+	.gpio11 = GPIO_DIR_INPUT,
+	.gpio12 = GPIO_DIR_INPUT,
+	.gpio13 = GPIO_DIR_INPUT,
+	.gpio14 = GPIO_DIR_INPUT,
+	.gpio15 = GPIO_DIR_INPUT,
+	.gpio16 = GPIO_DIR_INPUT,
+	.gpio17 = GPIO_DIR_INPUT,
+	.gpio19 = GPIO_DIR_INPUT,
+	.gpio20 = GPIO_DIR_INPUT,
+	.gpio21 = GPIO_DIR_INPUT,
+	.gpio22 = GPIO_DIR_INPUT,
+	.gpio23 = GPIO_DIR_INPUT,
+	.gpio24 = GPIO_DIR_INPUT,
+	.gpio27 = GPIO_DIR_INPUT,
+	.gpio28 = GPIO_DIR_INPUT,
+	.gpio29 = GPIO_DIR_INPUT,
+	.gpio30 = GPIO_DIR_INPUT,
+	.gpio31 = GPIO_DIR_INPUT,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_level = {
+	.gpio0 = GPIO_LEVEL_LOW,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_reset = {
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_invert = {
+	.gpio1 = GPIO_INVERT,
+	.gpio13 = GPIO_INVERT,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_blink = {
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_mode = {
+	.gpio32 = GPIO_MODE_GPIO,
+	.gpio33 = GPIO_MODE_GPIO,
+	.gpio34 = GPIO_MODE_GPIO,
+	.gpio35 = GPIO_MODE_GPIO,
+	.gpio36 = GPIO_MODE_GPIO,
+	.gpio37 = GPIO_MODE_GPIO,
+	.gpio38 = GPIO_MODE_GPIO,
+	.gpio39 = GPIO_MODE_GPIO,
+	.gpio40 = GPIO_MODE_NATIVE,
+	.gpio41 = GPIO_MODE_NATIVE,
+	.gpio42 = GPIO_MODE_GPIO,
+	.gpio43 = GPIO_MODE_NATIVE,
+	.gpio44 = GPIO_MODE_GPIO,
+	.gpio45 = GPIO_MODE_GPIO,
+	.gpio46 = GPIO_MODE_GPIO,
+	.gpio47 = GPIO_MODE_NATIVE,
+	.gpio48 = GPIO_MODE_GPIO,
+	.gpio49 = GPIO_MODE_GPIO,
+	.gpio50 = GPIO_MODE_GPIO,
+	.gpio51 = GPIO_MODE_GPIO,
+	.gpio52 = GPIO_MODE_GPIO,
+	.gpio53 = GPIO_MODE_GPIO,
+	.gpio54 = GPIO_MODE_GPIO,
+	.gpio55 = GPIO_MODE_GPIO,
+	.gpio56 = GPIO_MODE_NATIVE,
+	.gpio57 = GPIO_MODE_GPIO,
+	.gpio58 = GPIO_MODE_GPIO,
+	.gpio59 = GPIO_MODE_NATIVE,
+	.gpio60 = GPIO_MODE_GPIO,
+	.gpio61 = GPIO_MODE_GPIO,
+	.gpio62 = GPIO_MODE_NATIVE,
+	.gpio63 = GPIO_MODE_GPIO,
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_direction = {
+	.gpio32 = GPIO_DIR_INPUT,
+	.gpio33 = GPIO_DIR_INPUT,
+	.gpio34 = GPIO_DIR_INPUT,
+	.gpio35 = GPIO_DIR_INPUT,
+	.gpio36 = GPIO_DIR_INPUT,
+	.gpio37 = GPIO_DIR_INPUT,
+	.gpio38 = GPIO_DIR_INPUT,
+	.gpio39 = GPIO_DIR_INPUT,
+	.gpio42 = GPIO_DIR_INPUT,
+	.gpio44 = GPIO_DIR_INPUT,
+	.gpio45 = GPIO_DIR_INPUT,
+	.gpio46 = GPIO_DIR_INPUT,
+	.gpio48 = GPIO_DIR_INPUT,
+	.gpio49 = GPIO_DIR_INPUT,
+	.gpio50 = GPIO_DIR_INPUT,
+	.gpio51 = GPIO_DIR_INPUT,
+	.gpio52 = GPIO_DIR_INPUT,
+	.gpio53 = GPIO_DIR_INPUT,
+	.gpio54 = GPIO_DIR_INPUT,
+	.gpio55 = GPIO_DIR_INPUT,
+	.gpio57 = GPIO_DIR_INPUT,
+	.gpio58 = GPIO_DIR_INPUT,
+	.gpio60 = GPIO_DIR_INPUT,
+	.gpio61 = GPIO_DIR_INPUT,
+	.gpio63 = GPIO_DIR_OUTPUT,
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_level = {
+	.gpio63 = GPIO_LEVEL_HIGH,
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_reset = {
+	.gpio57 = GPIO_RESET_RSMRST,
+	.gpio63 = GPIO_RESET_RSMRST,
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_mode = {
+	.gpio64 = GPIO_MODE_GPIO,
+	.gpio65 = GPIO_MODE_NATIVE,
+	.gpio66 = GPIO_MODE_GPIO,
+	.gpio67 = GPIO_MODE_NATIVE,
+	.gpio68 = GPIO_MODE_GPIO,
+	.gpio69 = GPIO_MODE_GPIO,
+	.gpio70 = GPIO_MODE_GPIO,
+	.gpio71 = GPIO_MODE_GPIO,
+	.gpio72 = GPIO_MODE_GPIO,
+	.gpio73 = GPIO_MODE_NATIVE,
+	.gpio74 = GPIO_MODE_GPIO,
+	.gpio75 = GPIO_MODE_NATIVE,
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_direction = {
+	.gpio64 = GPIO_DIR_INPUT,
+	.gpio66 = GPIO_DIR_INPUT,
+	.gpio68 = GPIO_DIR_INPUT,
+	.gpio69 = GPIO_DIR_INPUT,
+	.gpio70 = GPIO_DIR_INPUT,
+	.gpio71 = GPIO_DIR_INPUT,
+	.gpio72 = GPIO_DIR_INPUT,
+	.gpio74 = GPIO_DIR_INPUT,
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_level = {
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_reset = {
+};
+
+const struct pch_gpio_map mainboard_gpio_map = {
+	.set1 = {
+		.mode		= &pch_gpio_set1_mode,
+		.direction	= &pch_gpio_set1_direction,
+		.level		= &pch_gpio_set1_level,
+		.blink		= &pch_gpio_set1_blink,
+		.invert		= &pch_gpio_set1_invert,
+		.reset		= &pch_gpio_set1_reset,
+	},
+	.set2 = {
+		.mode		= &pch_gpio_set2_mode,
+		.direction	= &pch_gpio_set2_direction,
+		.level		= &pch_gpio_set2_level,
+		.reset		= &pch_gpio_set2_reset,
+	},
+	.set3 = {
+		.mode		= &pch_gpio_set3_mode,
+		.direction	= &pch_gpio_set3_direction,
+		.level		= &pch_gpio_set3_level,
+		.reset		= &pch_gpio_set3_reset,
+	},
+};
diff --git a/src/mainboard/asus/h61-series/variants/h61m-a_usb3/hda_verb.c b/src/mainboard/asus/h61-series/variants/h61m-a_usb3/hda_verb.c
new file mode 100644
index 0000000000..1af52eb94e
--- /dev/null
+++ b/src/mainboard/asus/h61-series/variants/h61m-a_usb3/hda_verb.c
@@ -0,0 +1,51 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <device/azalia_device.h>
+
+const u32 cim_verb_data[] = {
+	0x10ec0887,	/* Codec Vendor / Device ID: Realtek */
+	0x10438445,	/* Subsystem ID */
+	15,		/* Number of 4 dword sets */
+	AZALIA_SUBVENDOR(0, 0x10438445),
+	AZALIA_PIN_CFG(0, 0x11, 0x40330000),
+	AZALIA_PIN_CFG(0, 0x12, AZALIA_PIN_CFG_NC(0)),
+	AZALIA_PIN_CFG(0, 0x14, 0x01014010),
+	AZALIA_PIN_CFG(0, 0x15, AZALIA_PIN_CFG_NC(0)),
+	AZALIA_PIN_CFG(0, 0x16, AZALIA_PIN_CFG_NC(0)),
+	AZALIA_PIN_CFG(0, 0x17, AZALIA_PIN_CFG_NC(0)),
+	AZALIA_PIN_CFG(0, 0x18, 0x01a19030),
+	AZALIA_PIN_CFG(0, 0x19, 0x02a19040),
+	AZALIA_PIN_CFG(0, 0x1a, 0x0181303f),
+	AZALIA_PIN_CFG(0, 0x1b, 0x02214020),
+	AZALIA_PIN_CFG(0, 0x1c, AZALIA_PIN_CFG_NC(0)),
+	AZALIA_PIN_CFG(0, 0x1d, 0x4024c601),
+	AZALIA_PIN_CFG(0, 0x1e, AZALIA_PIN_CFG_NC(0)),
+	AZALIA_PIN_CFG(0, 0x1f, AZALIA_PIN_CFG_NC(0)),
+
+	0x8086281c,	/* Codec Vendor / Device ID: Intel */
+	0x80860101,	/* Subsystem ID */
+	10,		/* Number of 4 dword sets */
+	AZALIA_SUBVENDOR(2, 0x80860101),
+	AZALIA_PIN_CFG(2, 0x04, 0x18560010),
+	AZALIA_PIN_CFG(2, 0x06, 0x18560010),
+	AZALIA_PIN_CFG(2, 0x08, 0x18560010),
+	AZALIA_PIN_CFG(2, 0x0a, 0x18560010),
+	AZALIA_PIN_CFG(2, 0x0b, 0x18560010),
+	AZALIA_PIN_CFG(2, 0x0c, 0x18560010),
+	AZALIA_PIN_CFG(2, 0x0d, 0x18560010),
+	AZALIA_PIN_CFG(2, 0x0e, 0x18560010),
+	AZALIA_PIN_CFG(2, 0x0f, 0x18560010),
+
+	0x80862805,	/* Codec Vendor / Device ID: Intel */
+	0x80860101,	/* Subsystem ID */
+	4,		/* Number of 4 dword sets */
+	AZALIA_SUBVENDOR(3, 0x80860101),
+	AZALIA_PIN_CFG(3, 0x05, 0x58560010),
+	AZALIA_PIN_CFG(3, 0x06, 0x58560020),
+	AZALIA_PIN_CFG(3, 0x07, 0x18560030),
+
+};
+
+const u32 pc_beep_verbs[0] = {};
+
+AZALIA_ARRAY_SIZES;
diff --git a/src/mainboard/asus/h61-series/variants/h61m-a_usb3/overridetree.cb b/src/mainboard/asus/h61-series/variants/h61m-a_usb3/overridetree.cb
new file mode 100644
index 0000000000..be9667a328
--- /dev/null
+++ b/src/mainboard/asus/h61-series/variants/h61m-a_usb3/overridetree.cb
@@ -0,0 +1,82 @@
+## SPDX-License-Identifier: GPL-2.0-or-later
+
+chip northbridge/intel/sandybridge
+	register "gpu_dp_b_hotplug" = "4"
+	register "gpu_dp_d_hotplug" = "4"
+	device domain 0 on
+		subsystemid 0x1043 0x844d inherit
+		chip southbridge/intel/bd82x6x
+			register "usb_port_config" = "{
+				{ 1, 0x95f, 0 },
+				{ 1, 0x95f, 0 },
+				{ 1, 0x9df, 1 },
+				{ 1, 0xfff, 1 },
+				{ 1, 0x95f, 2 },
+				{ 1, 0xfbf, 2 },
+				{ 1, 0xb57, 3 },
+				{ 1, 0xb57, 3 },
+				{ 1, 0x353, 4 },
+				{ 1, 0x353, 4 },
+				{ 1, 0xb5f, 6 },
+				{ 1, 0xb5f, 5 },
+				{ 1, 0xb57, 5 },
+				{ 1, 0xb57, 6 },
+			}"
+			register "pcie_port_coalesce" = "1"
+			register "gen1_dec" = "0x000c0291"
+			device ref hda on
+				subsystemid 0x1043 0x8445
+			end
+			device ref pcie_rp1 off end
+			device ref pcie_rp2 on  end # ASM1042 USB 3.0 controller
+			device ref pcie_rp3 off end
+			device ref pcie_rp4 on  end # PCIEX1_1 slot
+			device ref pcie_rp5 on  end # PCIEX1_2 slot
+			device ref pcie_rp6 on      # Realtek Gigabit NIC
+				device pci 00.0 on end
+			end
+			device ref pcie_rp7 off end
+			device ref pcie_rp8 off end
+
+			device ref lpc on
+				chip superio/nuvoton/nct6779d
+					device pnp 2e.1 off end	# Parallel
+					device pnp 2e.2 off end	# UART A
+					device pnp 2e.3 off end # UART B, IR
+					device pnp 2e.5 on	# Keyboard
+						io 0x60 = 0x0060
+						io 0x62 = 0x0064
+						irq 0x70 = 1
+						irq 0x72 = 12
+					end
+					device pnp 2e.6   off end # CIR
+					device pnp 2e.7   off end # GPIO6-8
+					device pnp 2e.8   off end # WDT1, GPIO0, GPIO1
+					device pnp 2e.108 on  end # GPIO0
+					device pnp 2e.9   off end # GPIO1-8
+					device pnp 2e.109 off end # GPIO1
+					device pnp 2e.209 off end # GPIO2
+					device pnp 2e.309 off end # GPIO3
+					device pnp 2e.409 off end # GPIO4
+					device pnp 2e.509 off end # GPIO5
+					device pnp 2e.609 off end # GPIO6
+					device pnp 2e.709 off end # GPIO7
+					device pnp 2e.a   on      # ACPI
+						irq 0xe7 = 0x11
+						irq 0xf2 = 0x5d
+					end
+					device pnp 2e.b   on      # H/W Monitor, FP LED
+						io 0x60 = 0x0290
+						io 0x62 = 0
+						irq 0x70 = 0
+					end
+					device pnp 2e.d   off end # WDT1
+					device pnp 2e.e   off end # CIR WAKE-UP
+					device pnp 2e.f   off end # GPIO Push-pull/Open-drain selection
+					device pnp 2e.14  off end # PORT80 UART
+					device pnp 2e.16  off end # Deep Sleep
+				end
+			end
+		end
+	end
+end

From da5101fde42b1d33aee70cda7235e09581b7dc6c Mon Sep 17 00:00:00 2001
From: Patrick Rudolph <patrick.rudolph@9elements.com>
Date: Tue, 6 May 2025 17:07:24 +0200
Subject: [PATCH 0942/3886] cpu/x86/smm: Drop unused label

To avoid confusion drop the label smm_handler_start, since it's unused
and the same name is also used in the permanent handler as C entry point
(see smm_module_handler.c).

Change-Id: I22bb5d378e8848d526f897cb2de70c0221827d0d
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87554
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
---
 src/cpu/x86/smm/smm_stub.S | 1 -
 1 file changed, 1 deletion(-)

diff --git a/src/cpu/x86/smm/smm_stub.S b/src/cpu/x86/smm/smm_stub.S
index c7a55f6ea6..dcfbcba590 100644
--- a/src/cpu/x86/smm/smm_stub.S
+++ b/src/cpu/x86/smm/smm_stub.S
@@ -48,7 +48,6 @@ fallback_stack_top:
 .code16
 .global _start
 _start:
-smm_handler_start:
 #if CONFIG(SMM_LAPIC_REMAP_MITIGATION)
 	/* Check if the LAPIC register block overlaps with the stub.
 	 * This block needs to work without data accesses because they

From c9f4cfa4632881ccdaab3bd189c39a017f85ae02 Mon Sep 17 00:00:00 2001
From: Martin Roth <gaumless@gmail.com>
Date: Sun, 20 Apr 2025 18:10:20 -0600
Subject: [PATCH 0943/3886] AUTHORS: Update list to 25.03

This adds the contributor names from the 24.05 release to the 25.03
release.

Anyone who is making contributions on behalf of a company, please
add the company name to the list.

Change-Id: I23f38bd125a8369e0a636c4d1602c783f6730a0a
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87381
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
---
 AUTHORS | 90 +++++++++++++++++++++++++++++++++++++++++++++++++++++++--
 1 file changed, 88 insertions(+), 2 deletions(-)

diff --git a/AUTHORS b/AUTHORS
index 435a938df5..21e1cd567f 100644
--- a/AUTHORS
+++ b/AUTHORS
@@ -15,12 +15,14 @@ Aaron Durbin
 Abe Levkoy
 Abel Briggs
 Abhinav Hardikar
+Abhishek Pandit-Subedi
 AdaCore
 Adam Liu
 Adam Mills
 Advanced Computing Lab, LANL
 Advanced Micro Devices, Inc.
 AG Electronics Ltd.
+Agogo
 Ahamed Husni
 Akshu Agrawal
 Al Hirani
@@ -41,24 +43,30 @@ Alexey Vazhnov
 Alice Sell
 Alicja Michalska
 Allen-KH Cheng
+Alok Agarwal
 Alper Nebi Yasak
 Amanda Hwang
 American Megatrends International, LLC
 Amersel
 Amit Caleechurn
+Ana Carolina Cabral
 Analog Devices Inc.
 Analogix Semiconductor
 Anand Mistry
 Anand Vaikar
+Anastasios Koutian
+Andre
 Andre Heider
 Andrew McRae
 Andrew SH Cheng
 Andrey Pronin
 Andriy Gapon
+Andy
 Andy Fleming
 Andy Pont
 Andy-ld Lu
 Angel Pons
+Angela Czubak
 Anil Kumar K
 Anna Karaś
 Annie Chen
@@ -68,6 +76,7 @@ Appukuttan V K
 Arashk Mahshidfar
 Arec Kao
 Ariel Fang
+Ariel Otilibili
 ARM Limited and Contributors
 Arthur Heymans
 Asami Doi
@@ -77,9 +86,12 @@ Ashqti
 ASPEED Technology Inc.
 Atheros Corporation
 Atmel Corporation
+Avi Uday
+Avinash Munduru
 Balaji Manigandan
 Balázs Vinarz
 BAP - Bruhnspace Advanced Projects
+Bartłomiej Grzesik
 Baruch Siach
 Ben Chuang
 Ben Kao
@@ -90,6 +102,7 @@ Bernardo Perez Priego
 Bhanu Prakash Maiya
 Bill Xie
 Bin Meng
+Bincai Liu
 Bitland Tech Inc.
 Bob Moragues
 Bora Guvendik
@@ -97,10 +110,13 @@ Boris Barbulovski
 Boris Mittelberg
 Brandon Breitenstein
 Brandon Weeks
+Brian Hsu
 Brian Norris
 Bryant Ou
 Carl-Daniel Hailfinger
+Carlos López
 Casper Chang
+Cathy Xu
 Caveh Jalali
 Cavium Inc.
 Chao Gui
@@ -125,6 +141,7 @@ Cong Yang
 CoolStar
 coresystems GmbH
 Corey Osgood
+Crystal Guo
 Curt Brune
 Curtis Chen
 Custom Ideas
@@ -144,6 +161,7 @@ Dave Airlie
 David Brownell
 David Greenman
 David Hendricks
+David Li
 David Lin
 David Milosevic
 David Mosberger-Tang
@@ -153,6 +171,7 @@ David Wu
 Dawei Chien
 Deepika Punyamurtula
 Deepti Deshatty
+Dehui Sun
 Denis 'GNUtoo' Carikli
 Denis Dowling
 DENX Software Engineering
@@ -166,6 +185,7 @@ Divya S Sasidharan
 Dmitry Ponamorev
 Dmitry Torokhov
 DMP Electronics Inc.
+Dolan Liu
 Dominik Behr
 Donghwa Lee
 Drew Eckhardt
@@ -186,6 +206,7 @@ ELSOFT AG
 Eltan B.V
 Eltan B.V.
 Elyes Haouas
+Emilie Roberts
 Eran Mitrani
 Eren Peng
 Eric Biederman
@@ -205,11 +226,13 @@ Fabian Meyer
 Fabio Aiuto
 Fabrice Bellard
 Facebook, Inc.
+Federico Amedeo Izzo
 Fei Yan
 Felix Friedlander
 Felix Held
 Felix Singer
 Fengquan Chen
+Filip Brozovic
 Filip Lewiński
 Flora Fu
 Florian Laufenböck
@@ -225,8 +248,12 @@ Freescale Semiconductor, Inc.
 Furquan Shaikh
 Gaggery Tsai
 Gang C Chen
+Garen Wu
+Gareth Yu
 Garmin Chang
 Gary Jennejohn
+Gavin Liu
+George Burgess
 George Trudeau
 Gerald Van Baren
 Gerd Hoffmann
@@ -234,6 +261,7 @@ Gergely Kiss
 Google LLC
 Greg Watson
 Grzegorz Bernacki
+Guangjie Song
 Guennadi Liakhovetski
 Guodong Liu
 Gwendal Grignou
@@ -241,6 +269,7 @@ Hal Martin
 Hao Chou
 Hao Wang
 HardenedLinux
+Harrie Paijmans
 Harsha B R
 Harshit Sharma
 Henry C Chen
@@ -248,11 +277,13 @@ Herbert Wu
 Hewlett Packard Enterprise Development LP
 Hewlett-Packard Development Company, L.P.
 Himanshu Sahdev
+Hope Wang
 Housong Zhang
 Hsiao Chien Sung
 Hsin-hsiung wang
 Hsin-Te Yuan
 Hsuan Ting Chen
+Hualin Wei
 Huaqin Technology Co., Ltd
 Huaqin Telecom Inc.
 Hui Liu
@@ -267,6 +298,7 @@ Igor Pavlov
 Ikjoon Jang
 Imagination Technologies
 Infineon Technologies
+Ingo Reitz
 InKi Dae
 INSPUR Co., Ltd
 Intel Corporation
@@ -284,11 +316,14 @@ Jakub Czapiga
 James Chao
 James Lo
 James Ye
+Jameson Thies
 Jamie Chen
 Jamie Ryu
 Jan Dabros
+Jan Philipp Groß
 Jan Samek
 Jan Tatje
+Jarried Lin
 Jason Glenesk
 Jason Nein
 Jason V Le
@@ -297,7 +332,9 @@ Jason Zhao
 jason-ch chen
 Jason-jh Lin
 Jay Patel
+Jayvik Desai
 Jean Lucas
+Jędrzej Ciupis
 Jeff Chase
 Jeff Daly
 Jeff Li
@@ -318,10 +355,12 @@ Jingle Hsu
 Jitao Shi
 Joe Pillow
 Joe Tessler
+Joel Bueno
 Joel Kitching
 Joel Linn
 Joey Peng
 Johanna Schander
+Johannes Hahn
 John Su
 John Zhao
 Johnny Li
@@ -339,7 +378,9 @@ Jörg Mische
 Joseph Smith
 Josie Nordrum
 Juan José García-Castro Crespo
+Julia Kittlinger
 Julia Tsai
+Julian Intronati
 Julian Schroeder
 Julian Stecklina
 Julien Viard de Galbert
@@ -351,6 +392,7 @@ Kangheui Won
 Kapil Porwal
 Karol Zmyslowski
 Karthik Ramasubramanian
+Ke Zheng
 Kei Hiroyoshi
 Keith Hui
 Keith Packard
@@ -362,10 +404,12 @@ Kevin Chowski
 Kevin Cody-Little
 Kevin Keijzer
 Kevin O'Connor
+Kevin Yang
 Kevin3 Yang
 kewei xu
 Kilari Raasi
 Kirk Wang
+Kiwi Liu
 Konrad Adamczyk
 Kontron Europe GmbH
 Kornel Dulęba
@@ -375,6 +419,7 @@ Kshitij
 Kshitiz Godara
 Kulkarni. Srinivas
 Kun Liu
+KunYi Chen
 Kyle Lin
 Kyösti Mälkki
 Lance Zhao
@@ -397,9 +442,13 @@ linear
 Linus Torvalds
 Linux Networx, Inc.
 LiPPERT ADLINK Technology GmbH
+Liu Liu
 Liya Li
+Lu Tang
+Lu. Pen-ChunX
 Lubomir Rintel
 Luc Verhaegen
+Luca Lai
 Lucas Chen
 Mac Chiang
 Maciej Matuszczyk
@@ -420,6 +469,7 @@ Mario Scheithauer
 Marius Gröger
 Mariusz Szafranski
 Mariusz Szafrański
+Mark Chang
 Mark Hasemeyer
 Mark Hsieh
 Mars Chen
@@ -430,6 +480,7 @@ Martin Roth
 Marvell International Ltd.
 Marvell Semiconductor Inc.
 Marx Wang
+Masa Nakura
 Masanori Ogino
 Máté Kukri
 Matei Dibu
@@ -438,6 +489,7 @@ Matt Chen
 Matt Delco
 Matt DeVillier
 Matt Papageorge
+Matt Turner
 Matthew Blecker
 Matthew Ziegelbaum
 Mattias Nissler
@@ -450,6 +502,7 @@ Maximilian Brune
 Mediatek Inc.
 MediaTek Inc.
 Meera Ravindranath
+Melongmelong
 Meng-Huan Yu
 Meta Platforms, Inc
 mgabryelski1
@@ -462,15 +515,20 @@ Michael Strosche
 Michael Walle
 Michał Kopeć
 Michal Suchanek
+Michał Zieliński
 Michał Żygowski
 Micro-Star INT'L CO., LTD.
 Mika Westerberg
 Mike Banon
+Mike Lin
 Mike Shih
+Mingjin Ge
 Miriam Polzer
 mkurumel
 Moises Garcia
+Momoko Hattori
 Mondrian Nuessle
+Monika A
 Monikaanan
 MontaVista Software, Inc.
 Morgan Jang
@@ -480,7 +538,7 @@ mtk15698
 mturney mturney
 Musse Abdullahi
 Myles Watson
-Nancy.Lin
+Nancy Lin
 Naresh Solanki
 Nathan Lu
 Naveen R. Iyer
@@ -491,12 +549,14 @@ Nicholas Sielicki
 Nicholas Sudsgaard
 Nick Barker
 Nick Chen
+Nick Kochlowski
 Nick Vaccaro
 Nico Huber
 Nico Rikken
 Nicola Corna
 Nicolas Boichat
 Nicole Faerber
+Nigel Tao
 Nikolai Vyssotski
 Nils Jacobs
 Nina Wu
@@ -510,6 +570,10 @@ Omar Pakker
 Online SAS
 Opal Voravootivat
 Orion Technologies, LLC
+Ot_chhao.chang
+Ot_hao.han
+Ot_song Fan
+Pablo
 Pablo Ceballos
 Pablo Stebler
 Pan Gao
@@ -542,13 +606,14 @@ Philipp Hug
 Piotr Kleinschmidt
 Po Xu
 Poornima Tom
+Pranava Y N
 Prasad Malisetty
 Prashant Malani
 Pratik Vishwakarma
 Pratikkumar Prajapati
 Pratikkumar V Prajapati
 Protectli
-Purism SPC
+PugzAreCute
 Purism, SPC
 Qii Wang
 Qinghong Zeng
@@ -566,6 +631,7 @@ Ravindra
 Ravishankar Sarawadi
 Ray Han Lim Ng
 Raymond Chung
+Reagan
 Red Hat, Inc
 ReddestDream
 Rehan Ghori
@@ -583,6 +649,7 @@ Richard Woodruff
 Rick Lee
 Ricky Chang
 Riku Viitanen
+Rishika Raj
 Ritul Guru
 Rizwan Qureshi
 Rnhmjoj
@@ -602,6 +669,7 @@ Roman Zippel
 Ron Lee
 Ron Minnich
 Ronak Kanabar
+Ronald Claveau
 Ronald G. Minnich
 Rory Liu
 Rudolf Marek
@@ -623,6 +691,7 @@ Samuel Holland
 Sandeep Maheswaram
 Sathya Prakash M R
 Satya Priya Kakitapalli
+Satya SreenivasL
 Saurabh Mishra
 SciTech Software, Inc.
 Scott Chao
@@ -650,6 +719,7 @@ Shiyu Sun
 Shon Wang
 Shou-Chieh Hsu
 Shreesh Chhabbi
+Shunxi Zhang
 Shuo Liu
 Siemens AG
 SiFive, Inc
@@ -662,10 +732,12 @@ Simon Zhou
 Sindhoor Tilak
 Solomon Alan-Dei
 Song Fan
+Sowmya Aralguppe
 Sridhar Siricilla
 Srinidhi N Kaushik
 Srinivasa Rao Mandadapu
 ST Microelectronics
+Stanisław Kardach
 Stanley Wu
 Star Labs Online Ltd
 Stefan Binding
@@ -693,6 +765,7 @@ Tao Xia
 Tarun Tuli
 Teddy Shih
 Terry Chen
+Terry Cheong
 Texas Instruments
 The Android Open Source Project
 The ChromiumOS Authors
@@ -712,6 +785,7 @@ tinghan shen
 Tobias Diedrich
 Tom Hiller
 Tommie Lin
+Tongtong Pan
 Tony Huang
 Tracy Wu
 Trevor Wu
@@ -730,8 +804,10 @@ Uwe Poeche
 V Sowmya
 Václav Straka
 Vadim Bendebury
+Valentyn Sudomyr
 Van Chen
 Varshit B Pandya
+Varun Upadhyay
 Veerabhadrarao Badiganti
 Venkat Thogaru
 Venkata Krishna Nimmagadda
@@ -740,6 +816,7 @@ Victor Ding
 Vidya Gopalakrishnan
 Vikram Narayanan
 Vikrant L Jadeja
+Vince Liu
 Vinod Polimera
 Vipin Kumar
 Vitaly Rodionov
@@ -752,8 +829,10 @@ Ward Vandewege
 Wayne Wang
 Weimin Wu
 Weiyi Lu
+Wen Zhang
 Wenbin Mei
 Wentao Qin
+Wenzhen Yu
 Werner Zeh
 Wilbert Duijvenvoorde
 William Wei
@@ -772,7 +851,10 @@ Wonkyu Kim
 Wuxy
 Xiang W
 Xin Ji
+Xiwen Shao
 Xixi Chen
+Xue Yao
+Xueqi Zhang
 Xuxin Xiong
 YADRO
 Yan Liu
@@ -792,14 +874,18 @@ Yu-Ping Wu
 Yuanliding
 Yuchen He
 Yuchen Huang
+Yuchiche
 Yunlong Jia
 Yuval Peress
 Zachary Yedidia
 Zanxi Chen
+Zebreus
 Zhanyong Wang
+Zhaoqing Jiu
 Zheng Bao
 Zhenguo Li
 Zhi7 Li
+Zhigang Qin
 Zhiqiang Ma
 Zhixing Ma
 Zhiyong Tao

From eec228987e0ce24baeedb0fdbc811e05841ba242 Mon Sep 17 00:00:00 2001
From: Felix Singer <felixsinger@posteo.net>
Date: Thu, 18 Jul 2024 00:35:12 +0200
Subject: [PATCH 0944/3886] mb/intel/coffelake_rvp: Make use of chipset
 devicetree

Make use of the alias names defined in the chipset devicetree. Remove
devices which are equal to the ones from the chipset devicetree.

Change-Id: I79de952d95798aa3c241e7864223c63c0a72ce31
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83524
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
---
 .../variants/baseboard/devicetree.cb          | 35 ++++++-------------
 .../variants/cfl_h/overridetree.cb            | 19 ++++------
 .../variants/cfl_s/overridetree.cb            | 23 ++++++------
 .../variants/cfl_u/overridetree.cb            | 25 +++++--------
 .../variants/cml_u/overridetree.cb            | 24 ++++++-------
 .../variants/whl_u/overridetree.cb            | 22 +++++-------
 6 files changed, 54 insertions(+), 94 deletions(-)

diff --git a/src/mainboard/intel/coffeelake_rvp/variants/baseboard/devicetree.cb b/src/mainboard/intel/coffeelake_rvp/variants/baseboard/devicetree.cb
index 16c68cd1a3..476e4f78db 100644
--- a/src/mainboard/intel/coffeelake_rvp/variants/baseboard/devicetree.cb
+++ b/src/mainboard/intel/coffeelake_rvp/variants/baseboard/devicetree.cb
@@ -43,33 +43,18 @@ chip soc/intel/cannonlake
 	register "s0ix_enable" = "false"
 
 	device domain 0 on
-		device pci 00.0 on  end # Host Bridge
-		device pci 02.0 on  end # Integrated Graphics Device
-		device pci 04.0 on  end # SA Thermal device
-		device pci 12.0 on  end # Thermal Subsystem
-		device pci 12.5 off end # UFS SCS
-		device pci 12.6 off end # GSPI #2
-		device pci 14.0 on  end # USB xHCI
-		device pci 14.1 off end # USB xDCI (OTG)
-		device pci 14.5 on  end # SDCard
-		device pci 16.0 on  end # Management Engine Interface 1
-		device pci 16.1 off end # Management Engine Interface 2
-		device pci 16.2 off end # Management Engine IDE-R
-		device pci 16.3 off end # Management Engine KT Redirection
-		device pci 16.4 off end # Management Engine Interface 3
-		device pci 16.5 off end # Management Engine Interface 4
-		device pci 1e.0 on  end # UART #0
-		device pci 1e.2 off end # GSPI #0
-		device pci 1e.3 off end # GSPI #1
-		device pci 1f.0 on
+		device ref igpu on  end
+		device ref dptf on  end
+		device ref thermal on  end
+		device ref xhci on  end
+		device ref sdxc on  end
+		device ref uart0 on  end
+		device ref lpc_espi on
 			chip drivers/pc80/tpm
 				device pnp 0c31.0 on end
 			end
-		end # LPC Interface
-		device pci 1f.1 on  end # P2SB
-		device pci 1f.2 hidden end # Power Management Controller
-		device pci 1f.3 on  end # Intel HDA
-		device pci 1f.4 on  end # SMBus
-		device pci 1f.5 on  end # PCH SPI
+		end
+		device ref hda on  end
+		device ref smbus on  end
 	end
 end
diff --git a/src/mainboard/intel/coffeelake_rvp/variants/cfl_h/overridetree.cb b/src/mainboard/intel/coffeelake_rvp/variants/cfl_h/overridetree.cb
index a10d271610..d36f9e22a4 100644
--- a/src/mainboard/intel/coffeelake_rvp/variants/cfl_h/overridetree.cb
+++ b/src/mainboard/intel/coffeelake_rvp/variants/cfl_h/overridetree.cb
@@ -61,15 +61,11 @@ chip soc/intel/cannonlake
 	register "PcieClkSrcClkReq[9]" = "9"
 
 	device domain 0 on
-		device pci 15.0 on  end # I2C #0
-		device pci 15.1 on  end # I2C #1
-		device pci 15.2 off end # I2C #2
-		device pci 15.3 off end # I2C #3
-		device pci 17.0 on  end # SATA
-		device pci 19.0 off end # I2C #4 (Not available on PCH-H)
-		device pci 19.1 off end # I2C #5 (Not available on PCH-H)
-		device pci 19.2 on  end # UART #2
-		device pci 1a.0 on  end # eMMC
+		device ref i2c0 on  end
+		device ref i2c1 on  end
+		device ref sata on  end
+		device ref uart2 on  end
+		device ref emmc on  end
 		device ref pcie_rp1 on	# x4 SLOT1
 			register "PcieRpSlotImplemented[0]" = "1"
 		end
@@ -79,9 +75,6 @@ chip soc/intel/cannonlake
 		device ref pcie_rp9 on
 			register "PcieRpSlotImplemented[8]" = "1"
 		end
-		device pci 1e.1 off end # UART #1
-		device pci 1e.2 off end # GSPI #0
-		device pci 1e.3 off end # GSPI #1
-		device pci 1f.6 on  end # GbE
+		device ref gbe on  end
 	end
 end
diff --git a/src/mainboard/intel/coffeelake_rvp/variants/cfl_s/overridetree.cb b/src/mainboard/intel/coffeelake_rvp/variants/cfl_s/overridetree.cb
index c8c443486f..607eb6a371 100644
--- a/src/mainboard/intel/coffeelake_rvp/variants/cfl_s/overridetree.cb
+++ b/src/mainboard/intel/coffeelake_rvp/variants/cfl_s/overridetree.cb
@@ -63,21 +63,19 @@ chip soc/intel/cannonlake
 	register "PcieClkSrcClkReq[10]" = "10"
 
 	device domain 0 on
-		device pci 14.3 on
+		device ref cnvi_wifi on
 			chip drivers/wifi/generic
 				register "wake" = "PME_B0_EN_BIT"
 				device generic 0 on end
 			end
-		end # CNVi wifi
-		device pci 15.0 on  end # I2C #0
-		device pci 15.1 on  end # I2C #1
-		device pci 15.2 on  end # I2C #2
-		device pci 15.3 on  end # I2C #3
-		device pci 17.0 on  end # SATA
-		device pci 19.0 off end # I2C #4 (Not available on PCH-H)
-		device pci 19.1 off end # I2C #5 (Not available on PCH-H)
-		device pci 19.2 on  end # UART #2
-		device pci 1a.0 on  end # eMMC
+		end
+		device ref i2c0 on  end
+		device ref i2c1 on  end
+		device ref i2c2 on  end
+		device ref i2c3 on  end
+		device ref sata on  end
+		device ref uart2 on  end
+		device ref emmc on  end
 		device ref pcie_rp1 on
 			register "PcieRpSlotImplemented[0]" = "1"
 		end
@@ -102,7 +100,6 @@ chip soc/intel/cannonlake
 		device ref pcie_rp21 on	# x4 SLOT 2
 			register "PcieRpSlotImplemented[20]" = "1"
 		end
-		device pci 1e.1 off end # UART #1
-		device pci 1f.6 on  end # GbE
+		device ref gbe on  end
 	end
 end
diff --git a/src/mainboard/intel/coffeelake_rvp/variants/cfl_u/overridetree.cb b/src/mainboard/intel/coffeelake_rvp/variants/cfl_u/overridetree.cb
index 25d084ac16..908632093c 100644
--- a/src/mainboard/intel/coffeelake_rvp/variants/cfl_u/overridetree.cb
+++ b/src/mainboard/intel/coffeelake_rvp/variants/cfl_u/overridetree.cb
@@ -38,16 +38,15 @@ chip soc/intel/cannonlake
 	}"
 
 	device domain 0 on
-		device pci 14.3 on
+		device ref cnvi_wifi on
 			chip drivers/wifi/generic
 				register "wake" = "PME_B0_EN_BIT"
 				device generic 0 on end
 			end
-		end # CNVi wifi
-		device pci 15.0 on  end # I2C #0
-		device pci 15.1 on  end # I2C #1
-		device pci 15.2 off end # I2C #2
-		device pci 15.3 on
+		end
+		device ref i2c0 on  end
+		device ref i2c1 on  end
+		device ref i2c3 on
 			chip drivers/i2c/max98373
 				register "interleave_mode" = "1"
 				register "vmon_slot_no" = "4"
@@ -57,12 +56,10 @@ chip soc/intel/cannonlake
 				register "name" = ""MAXR""
 				device i2c 32 on end
 			end
-		end # I2C #3
-		device pci 17.0 off end # SATA
-		device pci 19.0 on  end # I2C #4
-		device pci 19.1 off end # I2C #5
-		device pci 19.2 on  end # UART #2
-		device pci 1a.0 on  end # eMMC
+		end
+		device ref i2c4 on  end
+		device ref uart2 on  end
+		device ref emmc on  end
 		device ref pcie_rp1 on	# x4 SLOT1
 			register "PcieRpSlotImplemented[0]" = "1"
 		end
@@ -72,9 +69,5 @@ chip soc/intel/cannonlake
 		device ref pcie_rp9 on
 			register "PcieRpSlotImplemented[8]" = "1"
 		end
-		device pci 1e.1 off end # UART #1
-		device pci 1e.2 off end # GSPI #0
-		device pci 1e.3 off end # GSPI #1
-		device pci 1f.6 off end # GbE
 	end
 end
diff --git a/src/mainboard/intel/coffeelake_rvp/variants/cml_u/overridetree.cb b/src/mainboard/intel/coffeelake_rvp/variants/cml_u/overridetree.cb
index 1f3bf9074b..a14e9910c1 100644
--- a/src/mainboard/intel/coffeelake_rvp/variants/cml_u/overridetree.cb
+++ b/src/mainboard/intel/coffeelake_rvp/variants/cml_u/overridetree.cb
@@ -59,22 +59,19 @@ chip soc/intel/cannonlake
 	register "sdcard_cd_gpio" = "GPP_G5"
 
 	device domain 0 on
-		device pci 14.3 on
+		device ref cnvi_wifi on
 			chip drivers/wifi/generic
 				register "wake" = "PME_B0_EN_BIT"
 				device generic 0 on end
 			end
-		end # CNVi wifi
-		device pci 14.5 on  end # SDCard
-		device pci 15.0 on  end # I2C #0
-		device pci 15.1 on  end # I2C #1
-		device pci 15.2 off end # I2C #2
-		device pci 15.3 off end # I2C #3
-		device pci 17.0 on  end # SATA
-		device pci 19.0 on  end # I2C #4
-		device pci 19.1 off end # I2C #5
-		device pci 19.2 on  end # UART #2
-		device pci 1a.0 on  end # eMMC
+		end
+		device ref sdxc on  end
+		device ref i2c0 on  end
+		device ref i2c1 on  end
+		device ref sata on  end
+		device ref i2c4 on  end
+		device ref uart2 on  end
+		device ref emmc on  end
 		device ref pcie_rp1 on	# x4 SLOT1
 			register "PcieRpSlotImplemented[0]" = "1"
 		end
@@ -84,7 +81,6 @@ chip soc/intel/cannonlake
 		device ref pcie_rp9 on
 			register "PcieRpSlotImplemented[8]" = "1"
 		end
-		device pci 1e.1 off end # UART #1
-		device pci 1f.6 on  end # GbE
+		device ref gbe on  end
 	end
 end
diff --git a/src/mainboard/intel/coffeelake_rvp/variants/whl_u/overridetree.cb b/src/mainboard/intel/coffeelake_rvp/variants/whl_u/overridetree.cb
index 309082ed4d..ded8e72c23 100644
--- a/src/mainboard/intel/coffeelake_rvp/variants/whl_u/overridetree.cb
+++ b/src/mainboard/intel/coffeelake_rvp/variants/whl_u/overridetree.cb
@@ -44,21 +44,18 @@ chip soc/intel/cannonlake
 	register "sdcard_cd_gpio" = "GPP_G5"
 
 	device domain 0 on
-		device pci 14.3 on
+		device ref cnvi_wifi on
 			chip drivers/wifi/generic
 				register "wake" = "PME_B0_EN_BIT"
 				device generic 0 on end
 			end
-		end # CNVi wifi
-		device pci 15.0 on  end # I2C #0
-		device pci 15.1 on  end # I2C #1
-		device pci 15.2 off end # I2C #2
-		device pci 15.3 off end # I2C #3
-		device pci 17.0 on  end # SATA
-		device pci 19.0 on  end # I2C #4
-		device pci 19.1 off end # I2C #5
-		device pci 19.2 on  end # UART #2
-		device pci 1a.0 on  end # eMMC
+		end
+		device ref i2c0 on  end
+		device ref i2c1 on  end
+		device ref sata on  end
+		device ref i2c4 on  end
+		device ref uart2 on  end
+		device ref emmc on  end
 		device ref pcie_rp1 on	# x4 SLOT1
 			register "PcieRpSlotImplemented[0]" = "1"
 		end
@@ -68,7 +65,6 @@ chip soc/intel/cannonlake
 		device ref pcie_rp9 on
 			register "PcieRpSlotImplemented[8]" = "1"
 		end
-		device pci 1e.1 off end # UART #1
-		device pci 1f.6 on  end # GbE
+		device ref gbe on  end
 	end
 end

From bf38f8eddc1d3d4caa53ef3ff5d4195ffa7a1eee Mon Sep 17 00:00:00 2001
From: Felix Singer <felixsinger@posteo.net>
Date: Thu, 7 Mar 2024 19:44:37 +0100
Subject: [PATCH 0945/3886] vc/intel/fsp2: Drop superfluous header for Raptor
 Lake S

The missing header was added to the Intel FSP repo (commit 43f7092a6156
("IoT RPL-S MR2 (4415_02) FSP"), so remove it from vendorcode as it is
no longer needed.

This reverts commit c651a27b5332 ("vc/intel/fsp2_0: Add a copy of
ADL-S IOT FSP MemInfoHob.h for RPL-S IOT") which was only meant to
be a temporary fix.

Change-Id: I1e7a35f62677e39fda47f61c6c49bec0b415c2a5
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81120
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jayvik Desai <jayvik@google.com>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
---
 src/soc/intel/alderlake/Makefile.mk           |   5 -
 .../fsp/fsp2_0/iot/raptorlake_s/MemInfoHob.h  | 315 ------------------
 2 files changed, 320 deletions(-)
 delete mode 100644 src/vendorcode/intel/fsp/fsp2_0/iot/raptorlake_s/MemInfoHob.h

diff --git a/src/soc/intel/alderlake/Makefile.mk b/src/soc/intel/alderlake/Makefile.mk
index 55fc83ea7c..6262cf2999 100644
--- a/src/soc/intel/alderlake/Makefile.mk
+++ b/src/soc/intel/alderlake/Makefile.mk
@@ -70,11 +70,6 @@ endif
 CPPFLAGS_common += -I$(src)/soc/intel/alderlake
 CPPFLAGS_common += -I$(src)/soc/intel/alderlake/include
 
-# Include the missing MemInfoHob.h from vendorcode
-ifeq ($(CONFIG_SOC_INTEL_RAPTORLAKE_PCH_S)$(CONFIG_FSP_TYPE_IOT),yy)
-CPPFLAGS_common += -I$(src)/vendorcode/intel/fsp/fsp2_0/iot/raptorlake_s
-endif
-
 ifeq ($(CONFIG_SOC_INTEL_ALDERLAKE_PCH_S),y)
 # 06-97-00, 06-97-01, 06-97-04 are ADL-S Engineering Samples
 # 06-97-02 are ADL-S/HX Quality Samples but also ADL-HX Engineering Samples
diff --git a/src/vendorcode/intel/fsp/fsp2_0/iot/raptorlake_s/MemInfoHob.h b/src/vendorcode/intel/fsp/fsp2_0/iot/raptorlake_s/MemInfoHob.h
deleted file mode 100644
index 989bfb1a95..0000000000
--- a/src/vendorcode/intel/fsp/fsp2_0/iot/raptorlake_s/MemInfoHob.h
+++ /dev/null
@@ -1,315 +0,0 @@
-/** @file
-  This file contains definitions required for creation of
-  Memory S3 Save data, Memory Info data and Memory Platform
-  data hobs.
-
-@copyright
-  Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
-
-  SPDX-License-Identifier: BSD-2-Clause-Patent
-
-@par Specification Reference:
-**/
-#ifndef _MEM_INFO_HOB_H_
-#define _MEM_INFO_HOB_H_
-
-
-#pragma pack (push, 1)
-
-extern EFI_GUID gSiMemoryS3DataGuid;
-extern EFI_GUID gSiMemoryInfoDataGuid;
-extern EFI_GUID gSiMemoryPlatformDataGuid;
-
-#define MAX_NODE        2
-#define MAX_CH          4
-#define MAX_DIMM        2
-// Must match definitions in
-// Intel\ClientOneSiliconPkg\IpBlock\MemoryInit\Mtl\Include\MrcInterface.h
-#define HOB_MAX_SAGV_POINTS 4
-
-///
-/// Host reset states from MRC.
-///
-#define  WARM_BOOT        2
-
-#define R_MC_CHNL_RANK_PRESENT  0x7C
-#define   B_RANK0_PRS           BIT0
-#define   B_RANK1_PRS           BIT1
-#define   B_RANK2_PRS           BIT4
-#define   B_RANK3_PRS           BIT5
-
-// @todo remove and use the MdePkg\Include\Pi\PiHob.h
-#if !defined(_PEI_HOB_H_) && !defined(__PI_HOB_H__)
-#ifndef __HOB__H__
-typedef struct _EFI_HOB_GENERIC_HEADER {
-  UINT16  HobType;
-  UINT16  HobLength;
-  UINT32  Reserved;
-} EFI_HOB_GENERIC_HEADER;
-
-typedef struct _EFI_HOB_GUID_TYPE {
-  EFI_HOB_GENERIC_HEADER  Header;
-  EFI_GUID                Name;
-  ///
-  /// Guid specific data goes here
-  ///
-} EFI_HOB_GUID_TYPE;
-#endif
-#endif
-
-///
-/// Defines taken from MRC so avoid having to include MrcInterface.h
-///
-
-//
-// Matches MAX_SPD_SAVE define in MRC
-//
-#ifndef MAX_SPD_SAVE
-#define MAX_SPD_SAVE 29
-#endif
-
-//
-// MRC version description.
-//
-typedef struct {
-  UINT8  Major;     ///< Major version number
-  UINT8  Minor;     ///< Minor version number
-  UINT8  Rev;       ///< Revision number
-  UINT8  Build;     ///< Build number
-} SiMrcVersion;
-
-//
-// Matches MrcChannelSts enum in MRC
-//
-#ifndef CHANNEL_NOT_PRESENT
-#define CHANNEL_NOT_PRESENT     0  // There is no channel present on the controller.
-#endif
-#ifndef CHANNEL_DISABLED
-#define CHANNEL_DISABLED        1  // There is a channel present but it is disabled.
-#endif
-#ifndef CHANNEL_PRESENT
-#define CHANNEL_PRESENT         2  // There is a channel present and it is enabled.
-#endif
-
-//
-// Matches MrcDimmSts enum in MRC
-//
-#ifndef DIMM_ENABLED
-#define DIMM_ENABLED     0  // DIMM/rank Pair is enabled, presence will be detected.
-#endif
-#ifndef DIMM_DISABLED
-#define DIMM_DISABLED    1  // DIMM/rank Pair is disabled, regardless of presence.
-#endif
-#ifndef DIMM_PRESENT
-#define DIMM_PRESENT     2  // There is a DIMM present in the slot/rank pair and it will be used.
-#endif
-#ifndef DIMM_NOT_PRESENT
-#define DIMM_NOT_PRESENT 3  // There is no DIMM present in the slot/rank pair.
-#endif
-
-//
-// Matches MrcBootMode enum in MRC
-//
-#ifndef __MRC_BOOT_MODE__
-#define __MRC_BOOT_MODE__                 //The below values are originated from MrcCommonTypes.h
-  #ifndef INT32_MAX
-  #define INT32_MAX                       (0x7FFFFFFF)
-  #endif  //INT32_MAX
-typedef enum {
-  bmCold,                                 ///< Cold boot
-  bmWarm,                                 ///< Warm boot
-  bmS3,                                   ///< S3 resume
-  bmFast,                                 ///< Fast boot
-  MrcBootModeMax,                         ///< MRC_BOOT_MODE enumeration maximum value.
-  MrcBootModeDelim = INT32_MAX            ///< This value ensures the enum size is consistent on both sides of the PPI.
-} MRC_BOOT_MODE;
-#endif  //__MRC_BOOT_MODE__
-
-//
-// Matches MrcDdrType enum in MRC
-//
-#ifndef MRC_DDR_TYPE_DDR5
-#define MRC_DDR_TYPE_DDR5     1
-#endif
-#ifndef MRC_DDR_TYPE_LPDDR5
-#define MRC_DDR_TYPE_LPDDR5   2
-#endif
-#ifndef MRC_DDR_TYPE_LPDDR4
-#define MRC_DDR_TYPE_LPDDR4   3
-#endif
-#ifndef MRC_DDR_TYPE_UNKNOWN
-#define MRC_DDR_TYPE_UNKNOWN  4
-#endif
-
-#define MAX_PROFILE_NUM     7 // number of memory profiles supported
-#define MAX_XMP_PROFILE_NUM 5 // number of XMP profiles supported
-
-#define MAX_TRACE_REGION             5
-#define MAX_TRACE_CACHE_TYPE         2
-
-//
-// DIMM timings
-//
-typedef struct {
-  UINT32 tCK;       ///< Memory cycle time, in femtoseconds.
-  UINT16 NMode;     ///< Number of tCK cycles for the channel DIMM's command rate mode.
-  UINT16 tCL;       ///< Number of tCK cycles for the channel DIMM's CAS latency.
-  UINT16 tCWL;      ///< Number of tCK cycles for the channel DIMM's minimum CAS write latency time.
-  UINT16 tFAW;      ///< Number of tCK cycles for the channel DIMM's minimum four activate window delay time.
-  UINT16 tRAS;      ///< Number of tCK cycles for the channel DIMM's minimum active to precharge delay time.
-  UINT16 tRCDtRP;   ///< Number of tCK cycles for the channel DIMM's minimum RAS# to CAS# delay time and Row Precharge delay time.
-  UINT16 tREFI;     ///< Number of tCK cycles for the channel DIMM's minimum Average Periodic Refresh Interval.
-  UINT16 tRFC;      ///< Number of tCK cycles for the channel DIMM's minimum refresh recovery delay time.
-  UINT16 tRFCpb;    ///< Number of tCK cycles for the channel DIMM's minimum per bank refresh recovery delay time.
-  UINT16 tRFC2;     ///< Number of tCK cycles for the channel DIMM's minimum refresh recovery delay time.
-  UINT16 tRFC4;     ///< Number of tCK cycles for the channel DIMM's minimum refresh recovery delay time.
-  UINT16 tRPab;     ///< Number of tCK cycles for the channel DIMM's minimum row precharge delay time for all banks.
-  UINT16 tRRD;      ///< Number of tCK cycles for the channel DIMM's minimum row active to row active delay time.
-  UINT16 tRRD_L;    ///< Number of tCK cycles for the channel DIMM's minimum row active to row active delay time for same bank groups.
-  UINT16 tRRD_S;    ///< Number of tCK cycles for the channel DIMM's minimum row active to row active delay time for different bank groups.
-  UINT16 tRTP;      ///< Number of tCK cycles for the channel DIMM's minimum internal read to precharge command delay time.
-  UINT16 tWR;       ///< Number of tCK cycles for the channel DIMM's minimum write recovery time.
-  UINT16 tWTR;      ///< Number of tCK cycles for the channel DIMM's minimum internal write to read command delay time.
-  UINT16 tWTR_L;    ///< Number of tCK cycles for the channel DIMM's minimum internal write to read command delay time for same bank groups.
-  UINT16 tWTR_S;    ///< Number of tCK cycles for the channel DIMM's minimum internal write to read command delay time for different bank groups.
-  UINT16 tCCD_L;  ///< Number of tCK cycles for the channel DIMM's minimum CAS-to-CAS delay for same bank group.
-} MRC_CH_TIMING;
-
-typedef struct {
-  UINT16 tRDPRE;     ///< Read CAS to Precharge cmd delay
-} MRC_IP_TIMING;
-
-///
-/// Memory SMBIOS & OC Memory Data Hob
-///
-typedef struct {
-  UINT8            Status;                  ///< See MrcDimmStatus for the definition of this field.
-  UINT8            DimmId;
-  UINT32           DimmCapacity;            ///< DIMM size in MBytes.
-  UINT16           MfgId;
-  UINT8            ModulePartNum[20];       ///< Module part number for DDR3 is 18 bytes however for DRR4 20 bytes as per JEDEC Spec, so reserving 20 bytes
-  UINT8            RankInDimm;              ///< The number of ranks in this DIMM.
-  UINT8            SpdDramDeviceType;       ///< Save SPD DramDeviceType information needed for SMBIOS structure creation.
-  UINT8            SpdModuleType;           ///< Save SPD ModuleType information needed for SMBIOS structure creation.
-  UINT8            SpdModuleMemoryBusWidth; ///< Save SPD ModuleMemoryBusWidth information needed for SMBIOS structure creation.
-  UINT8            SpdSave[MAX_SPD_SAVE];   ///< Save SPD Manufacturing information needed for SMBIOS structure creation.
-  UINT16           Speed;                   ///< The maximum capable speed of the device, in MHz
-  UINT8            MdSocket;                ///< MdSocket: 0 = Memory Down, 1 = Socketed. Needed for SMBIOS structure creation.
-} DIMM_INFO;
-
-typedef struct {
-  UINT8            Status;                  ///< Indicates whether this channel should be used.
-  UINT8            ChannelId;
-  UINT8            DimmCount;               ///< Number of valid DIMMs that exist in the channel.
-  MRC_CH_TIMING    Timing[MAX_PROFILE_NUM]; ///< The channel timing values.
-  DIMM_INFO        DimmInfo[MAX_DIMM];      ///< Save the DIMM output characteristics.
-} CHANNEL_INFO;
-
-typedef struct {
-  UINT8            Status;                  ///< Indicates whether this controller should be used.
-  UINT16           DeviceId;                ///< The PCI device id of this memory controller.
-  UINT8            RevisionId;              ///< The PCI revision id of this memory controller.
-  UINT8            ChannelCount;            ///< Number of valid channels that exist on the controller.
-  CHANNEL_INFO     ChannelInfo[MAX_CH];     ///< The following are channel level definitions.
-} CONTROLLER_INFO;
-
-typedef struct {
-  UINT64   BaseAddress;   ///< Trace Base Address
-  UINT64   TotalSize;     ///< Total Trace Region of Same Cache type
-  UINT8    CacheType;     ///< Trace Cache Type
-  UINT8    ErrorCode;     ///< Trace Region Allocation Fail Error code
-  UINT8    Rsvd[2];
-} PSMI_MEM_INFO;
-
-/// This data structure contains per-SaGv timing values that are considered output by the MRC.
-typedef struct {
-  UINT32        DataRate;    ///< The memory rate for the current SaGv Point in units of MT/s
-  MRC_CH_TIMING JedecTiming; ///< Timings used for this entry's corresponding SaGv Point - derived from JEDEC SPD spec
-  MRC_IP_TIMING IpTiming;    ///< Timings used for this entry's corresponding SaGv Point - IP specific
-} HOB_SAGV_TIMING_OUT;
-
-/// This data structure contains SAGV config values that are considered output by the MRC.
-typedef struct {
-  UINT32              NumSaGvPointsEnabled; ///< Count of the total number of SAGV Points enabled.
-  UINT32              SaGvPointMask;        ///< Bit mask where each bit indicates an enabled SAGV point.
-  HOB_SAGV_TIMING_OUT SaGvTiming[HOB_MAX_SAGV_POINTS];
-} HOB_SAGV_INFO;
-
-typedef struct {
-  UINT8             Revision;
-  UINT16            DataWidth;              ///< Data width, in bits, of this memory device
-  /** As defined in SMBIOS 3.0 spec
-    Section 7.18.2 and Table 75
-  **/
-  UINT8             MemoryType;             ///< DDR type: DDR3, DDR4, or LPDDR3
-  UINT16            MaximumMemoryClockSpeed;///< The maximum capable speed of the device, in megahertz (MHz)
-  UINT16            ConfiguredMemoryClockSpeed; ///< The configured clock speed to the memory device, in megahertz (MHz)
-  /** As defined in SMBIOS 3.0 spec
-    Section 7.17.3 and Table 72
-  **/
-  UINT8             ErrorCorrectionType;
-
-  SiMrcVersion      Version;
-  BOOLEAN           EccSupport;
-  UINT8             MemoryProfile;
-  UINT8             IsDMBRunning;                      ///< Deprecated.
-  UINT32            TotalPhysicalMemorySize;
-  UINT32            DefaultXmptCK[MAX_XMP_PROFILE_NUM];///< Stores the tCK value read from SPD XMP profiles if they exist.
-  ///
-  /// Set of bit flags showing XMP and User Profile capability status for the DIMMs detected in system. For each bit, 1 is supported, 0 is unsupported.
-  /// Bit 0: XMP Profile 1 capability status
-  /// Bit 1: XMP Profile 2 capability status
-  /// Bit 2: XMP Profile 3 capability status
-  /// Bit 3: User Profile 4 capability status
-  /// Bit 4: User Profile 5 capability status
-  ///
-  UINT8             XmpProfileEnable;
-  UINT8             XmpConfigWarning;                  ///< If XMP capable DIMMs config support only 1DPC, but 2DPC is installed
-  UINT8             Ratio;                             ///< DDR Frequency Ratio, Max Value 255
-  UINT8             RefClk;
-  UINT32            VddVoltage[MAX_PROFILE_NUM];
-  UINT32            VddqVoltage[MAX_PROFILE_NUM];
-  UINT32            VppVoltage[MAX_PROFILE_NUM];
-  CONTROLLER_INFO   Controller[MAX_NODE];
-  UINT16            Ratio_UINT16;                      ///< DDR Frequency Ratio, used for programs that require ratios higher then 255
-  UINT32            NumPopulatedChannels;              ///< Total number of memory channels populated
-  HOB_SAGV_INFO     SagvConfigInfo;                    ///< This data structure contains SAGV config values that are considered output by the MRC.
-  UINT16            TotalMemWidth;                     ///< Total Memory Width in bits from all populated channels
-  BOOLEAN           MemorySpeedReducedWrongDimmSlot;   ///< Can be used by OEM BIOS to display a warning on the screen that DDR speed was reduced due to wrong DIMM population
-  BOOLEAN           MemorySpeedReducedMixedConfig;     ///< Can be used by OEM BIOS to display a warning on the screen that DDR speed was reduced due to mixed DIMM config
-  BOOLEAN           DynamicMemoryBoostTrainingFailed;  ///< TRUE if Dynamic Memory Boost failed to train and was force disabled on the last full training boot. FALSE otherwise.
-} MEMORY_INFO_DATA_HOB;
-
-/**
-  Memory Platform Data Hob
-
-  <b>Revision 1:</b>
-  - Initial version.
-  <b>Revision 2:</b>
-  - Added TsegBase, PrmrrSize, PrmrrBase, Gttbase, MmioSize, PciEBaseAddress fields
-**/
-typedef struct {
-  UINT8             Revision;
-  UINT8             Reserved[3];
-  UINT32            BootMode;
-  UINT32            TsegSize;
-  UINT32            TsegBase;
-  UINT32            PrmrrSize;
-  UINT64            PrmrrBase;
-  UINT32            GttBase;
-  UINT32            MmioSize;
-  UINT32            PciEBaseAddress;
-  PSMI_MEM_INFO     PsmiInfo[MAX_TRACE_CACHE_TYPE];
-  PSMI_MEM_INFO     PsmiRegionInfo[MAX_TRACE_REGION];
-  BOOLEAN           MrcBasicMemoryTestPass;
-} MEMORY_PLATFORM_DATA;
-
-typedef struct {
-  EFI_HOB_GUID_TYPE    EfiHobGuidType;
-  MEMORY_PLATFORM_DATA Data;
-  UINT8                *Buffer;
-} MEMORY_PLATFORM_DATA_HOB;
-
-#pragma pack (pop)
-
-#endif // _MEM_INFO_HOB_H_

From 20d7eaeb0f5a0eaabcd816c0572f0d2b9279efc6 Mon Sep 17 00:00:00 2001
From: Martin Roth <gaumless@gmail.com>
Date: Mon, 7 Apr 2025 12:01:25 -0600
Subject: [PATCH 0946/3886] Documentation: Add chip operations
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Change-Id: I5373eab2de2e255f9e3576794b9ad02d9711a6c2
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87201
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 Documentation/internals/chip_operations.md | 537 +++++++++++++++++++++
 Documentation/internals/index.md           |   2 +-
 2 files changed, 538 insertions(+), 1 deletion(-)
 create mode 100644 Documentation/internals/chip_operations.md

diff --git a/Documentation/internals/chip_operations.md b/Documentation/internals/chip_operations.md
new file mode 100644
index 0000000000..636b51372b
--- /dev/null
+++ b/Documentation/internals/chip_operations.md
@@ -0,0 +1,537 @@
+# The `chip_operations` Structure in coreboot
+
+## Introduction
+
+The `chip_operations` structure is a fundamental component of coreboot's
+chipset abstraction layer. It provides a standardized interface for chipset-
+specific code to interact with coreboot's device initialization framework.
+This structure enables coreboot to support a wide variety of chipsets
+while maintaining a consistent initialization flow across different hardware
+platforms.
+
+In coreboot's architecture, a "chip" refers to a collection of hardware
+components that form a logical unit, such as a System-on-Chip (SoC),
+a CPU, or a distinct southbridge/northbridge. The `chip_operations`
+structure provides the hooks necessary for coreboot to discover, configure,
+and initialize these components during the boot process.
+
+The `chip_operations` structure is particularly crucial for the ramstage
+portion of coreboot, where it connects the static device tree definitions
+with the actual hardware initialization code. It serves as the bridge
+between the declarative device descriptions and the imperative code that
+brings those devices to life.
+
+
+## Structure Definition
+
+The `chip_operations` structure is defined in `src/include/device/device.h`
+as follows:
+
+```c
+struct chip_operations {
+    void (*enable_dev)(struct device *dev);
+    void (*init)(void *chip_info);
+    void (*final)(void *chip_info);
+    unsigned int initialized : 1;
+    unsigned int finalized : 1;
+    const char *name;
+};
+```
+
+
+### Field Descriptions
+
+- **enable_dev**: A function pointer that takes a `struct device*`
+parameter. This function is called for each device associated with the
+chip during the device enumeration phase (specifically, within the
+`scan_bus` operations triggered by `dev_enumerate`). Its primary
+purpose is to set up device operations (`dev->ops`) based on the
+device's role in the system.
+
+- **init**: A function pointer that takes a `void*` parameter pointing to
+the chip's configuration data (typically cast to a chip-specific struct).
+This function is called during the chip initialization phase
+(`BS_DEV_INIT_CHIPS`), before device enumeration. It usually performs
+early hardware setup needed before individual devices can be configured.
+
+- **final**: A function pointer that takes a `void*` parameter pointing to
+the chip's configuration data (typically cast to a chip-specific struct).
+This function is called during the final table writing phase of coreboot
+initialization (`BS_WRITE_TABLES`), after all devices have been
+initialized. It performs any necessary cleanup or late initialization
+operations.
+
+- **initialized**: A bit flag indicating whether the chip's init function
+has been called.
+
+- **finalized**: A bit flag indicating whether the chip's final function
+has been called.
+
+- **name**: A string containing the human-readable name of the chip, used
+for debugging and logging purposes.
+
+
+## Initialization Sequence and `chip_operations`
+
+The `chip_operations` structure integrates with coreboot's boot state
+machine, which is defined in `src/lib/hardwaremain.c`. The functions in
+this structure are called at specific points during the boot process:
+
+1. **BS_DEV_INIT_CHIPS** state: The `init` function is called for each
+chip in the device tree. This is handled by `dev_initialize_chips()`
+which iterates through all devices, identifies unique chip instances,
+and invokes their `init` functions.
+
+2. **BS_DEV_ENUMERATE** state: During the execution of this state,
+`dev_enumerate()` is called, which triggers bus scanning
+(e.g., `pci_scan_bus`). Within these scan routines, the `enable_dev`
+function is called for devices associated with a chip. This commonly
+assigns the appropriate `device_operations` structure to each device
+based on its type and purpose.
+
+3. **BS_WRITE_TABLES** state: The `final` function is called for each
+chip by `dev_finalize_chips()` after all devices have been initialized
+and just before payloads are loaded.
+
+This sequence ensures that chips can perform necessary setup before their
+individual devices are configured, and also perform cleanup or finalization
+after all devices have been initialized but before the final tables are
+written and the payload is executed.
+
+
+## Relationship Between `chip_operations` and `device_operations`
+
+It's important to understand the distinction and relationship between
+`chip_operations` and `device_operations`:
+
+- **chip_operations**: Operates at the chipset or SoC level, providing
+hooks for chip-wide initialization. It's responsible for the overall
+setup of a collection of devices that belong to the same logical chip.
+
+- **device_operations**: Operates at the individual device level,
+providing functions to manage specific devices within a chip. These
+operations include resource allocation, device initialization, and device-
+specific functionality.
+
+The key relationship is that `chip_operations.enable_dev` is typically
+responsible for assigning the appropriate `device_operations` structure
+to each device based on its type and function. This is where the bridge
+between the chip-level and device-level abstractions occurs.
+
+For example, a typical implementation of the `enable_dev` function might
+look like this:
+
+```c
+static void soc_enable(struct device *dev)
+{
+    if (dev->path.type == DEVICE_PATH_DOMAIN)
+        dev->ops = &pci_domain_ops;
+    else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER)
+        dev->ops = &cpu_bus_ops;
+    else if (dev->path.type == DEVICE_PATH_GPIO)
+        block_gpio_enable(dev);
+    else if (dev->path.type == DEVICE_PATH_PCI &&
+             dev->path.pci.devfn == PCH_DEVFN_PMC)
+        dev->ops = &pmc_ops;
+}
+```
+
+This function examines each device's path type and assigns the appropriate
+operations based on the device's role in the system.
+
+
+## Integration with the Devicetree
+
+The `chip_operations` structure is tightly integrated with coreboot's
+devicetree mechanism. The devicetree is a hierarchical description of the
+hardware platform, defined in `.cb` files (typically `chipset.cb`,
+`devicetree.cb`, and optionally `overridetree.cb`).
+
+In the devicetree, a `chip` directive starts a collection of devices
+associated with a particular chip driver. The path specified with the
+`chip` directive corresponds to a directory in the coreboot source tree
+that contains the chip driver code, including a `chip.c` file that defines
+the `chip_operations` structure for that chip.
+
+For example, a devicetree might contain:
+
+```
+chip soc/intel/cannonlake
+    device domain 0 on
+        device pci 00.0 on end  # Host Bridge
+        device pci 12.0 on end  # Thermal Subsystem
+        # ... more devices ...
+    end
+end
+```
+
+This connects the devices under this chip directive with the
+`chip_operations` structure defined in
+`src/soc/intel/cannonlake/chip.c`:
+
+```c
+struct chip_operations soc_intel_cannonlake_ops = {
+    .name = "Intel Cannonlake",
+    .enable_dev = &soc_enable,
+    .init = &soc_init_pre_device,
+};
+```
+
+During coreboot's build process, the `sconfig` utility processes the
+devicetree files and generates code that links the devices defined in the
+devicetree with their corresponding `chip_operations` structures.
+
+
+## Chip Configuration Data
+
+Each chip typically defines a configuration structure in a `chip.h` file
+within its source directory. This structure contains configuration settings
+that can be specified in the devicetree using `register` directives.
+
+For example, a chip might define a configuration structure like:
+
+```c
+/* In src/soc/intel/cannonlake/chip.h */
+struct soc_intel_cannonlake_config {
+    uint8_t pcie_rp_aspm[CONFIG_MAX_ROOT_PORTS];
+    uint8_t usb2_ports[16];
+    uint8_t usb3_ports[10];
+    /* ... more configuration options ... */
+};
+```
+
+In the devicetree, you would configure these options using register
+directives:
+
+```
+chip soc/intel/cannonlake
+    register "pcie_rp_aspm[0]" = "ASPM_AUTO"
+    register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)"
+    # ... more register settings ...
+
+    device domain 0 on
+        # ... devices ...
+    end
+end
+```
+
+These configuration values are made available to the chip's `init` and
+`final` functions through the `chip_info` parameter, which points to
+an instance of the chip's configuration structure (after appropriate
+casting from `void *`).
+
+
+## Implementation Examples
+
+### Minimal Implementation
+
+Some chips may not need extensive initialization and can provide a
+minimal implementation of the `chip_operations` structure:
+
+```c
+struct chip_operations soc_ucb_riscv_ops = {
+    .name = "UCB RISC-V",
+};
+```
+
+This implementation only provides a name for debugging purposes but
+doesn't define any initialization functions.
+
+
+### Basic Implementation with Initialization
+
+A more typical implementation includes at least initialization hooks:
+
+```c
+struct chip_operations soc_amd_genoa_poc_ops = {
+    .name = "AMD Genoa SoC Proof of Concept",
+    .init = soc_init,
+    .final = soc_final,
+};
+```
+
+The `init` function might perform chip-wide initialization:
+
+```c
+static void soc_init(void *chip_info)
+{
+    default_dev_ops_root.write_acpi_tables = soc_acpi_write_tables;
+    amd_opensil_silicon_init();
+    data_fabric_print_mmio_conf();
+    fch_init(chip_info);
+}
+```
+
+
+### Complete Implementation
+
+A complete implementation includes all three function pointers:
+
+```c
+struct chip_operations soc_intel_xeon_sp_cpx_ops = {
+    .name = "Intel Cooper Lake-SP",
+    .enable_dev = chip_enable_dev,
+    .init = chip_init,
+    .final = chip_final,
+};
+```
+
+The `enable_dev` function would typically assign device operations
+based on device types:
+
+```c
+static void chip_enable_dev(struct device *dev)
+{
+    /* PCI root complex */
+    if (dev->path.type == DEVICE_PATH_DOMAIN)
+        dev->ops = &pci_domain_ops;
+    /* CPU cluster */
+    else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER)
+        dev->ops = &cpu_cluster_ops;
+    /* PCIe root ports */
+    else if (dev->path.type == DEVICE_PATH_PCI &&
+             PCI_SLOT(dev->path.pci.devfn) == PCIE_PORT1_SLOT)
+        dev->ops = &pcie_rp_ops;
+    /* ... other device types ... */
+}
+```
+
+
+### Mainboard Implementation
+
+It's also common for the mainboard-specific code (e.g.,
+`src/mainboard/vendor/board/mainboard.c`) to define its own
+`chip_operations`, often named `mainboard_ops`. The `mainboard_ops.init`
+can perform early board-level setup, and `mainboard_ops.enable_dev` can
+assign operations for devices specific to the mainboard or set default
+operations.
+
+```c
+/* Example from src/mainboard/google/zork/mainboard.c */
+struct chip_operations mainboard_ops = {
+       .enable_dev = mainboard_enable,
+       .init = mainboard_init,
+       .final = mainboard_final,
+};
+```
+
+
+## Device Registration and Discovery
+
+The `chip_operations` structure plays a key role in device registration
+and discovery within coreboot. Here's how it fits into this process:
+
+1. **Static Device Definition**: Devices are statically defined in the
+devicetree files (`chipset.cb`, `devicetree.cb`, `overridetree.cb`).
+
+2. **Code Generation**: The `sconfig` utility processes these files and
+generates code in `build/static.c` that creates the device structures
+and links them to their corresponding chip configuration data.
+
+3. **Chip Initialization**: During the `BS_DEV_INIT_CHIPS` boot state,
+`dev_initialize_chips()` calls each chip's `init` function to perform
+chip-wide setup.
+
+4. **Device Enumeration and Enabling**: During the `BS_DEV_ENUMERATE`
+    boot state, `dev_enumerate()` initiates bus scanning. The scan
+    functions call the associated chip's `enable_dev` function for each
+    device, which assigns the appropriate device operations (`dev->ops`).
+
+5. **Device Configuration and Initialization**: Subsequent boot states
+    (`BS_DEV_RESOURCES`, `BS_DEV_ENABLE`, `BS_DEV_INIT`) configure and
+    initialize the devices according to their assigned device operations.
+
+6. **Chip Finalization**: After all devices have been initialized,
+    `dev_finalize_chips()` calls each chip's `final` function during the
+    `BS_WRITE_TABLES` boot state.
+
+
+## Build Process Integration
+
+The `chip_operations` structures are integrated into the coreboot build
+process through several mechanisms:
+
+1. **Devicetree Processing**: The `sconfig` utility processes the
+devicetree files and generates code that creates and links the device
+structures.
+
+2. **Static Structure Declaration**: Each chip (and often the mainboard)
+    defines its `chip_operations` structure in its respective `.c` file.
+    These structures are collected during the build process.
+
+3. **External References**: The generated code in `build/static.c`
+includes external references to these `chip_operations` structures.
+
+4. **Linking**: The linker collects all the `chip_operations` structures
+and includes them in the final firmware image.
+
+This process ensures that the appropriate chip operations are available
+during the boot process for each chip included in the devicetree.
+
+
+## Best Practices for Implementing `chip_operations`
+
+When implementing the `chip_operations` structure for a new chip,
+follow these best practices:
+
+1. **Provide a Meaningful Name**: The `name` field should be descriptive
+and identify the chip clearly for debugging purposes.
+
+2. **Implement `enable_dev` Correctly**: The `enable_dev` function should
+assign the appropriate device operations based on device types and
+functions. It should handle all device types that might be part of the chip.
+Consider interactions with the mainboard `enable_dev`.
+
+3. **Use Configuration Data**: The `init` and `final` functions should
+make use of the chip configuration data passed via the `chip_info`
+parameter (casting it to the correct type) to configure the chip
+according to the settings specified in the devicetree.
+
+4. **Minimize Dependencies**: The `init` function should minimize
+dependencies on other chips being initialized, as the order of chip
+initialization is not guaranteed.
+
+5. **Handle Resources Properly**: If the chip manages resources (memory
+regions, I/O ports, etc.), ensure that these are properly allocated and
+assigned to devices, usually within the associated `device_operations`.
+
+6. **Implement Error Handling**: Include appropriate error handling in
+the initialization functions to handle hardware initialization failures
+gracefully.
+
+7. **Document Special Requirements**: If the chip has special
+requirements or dependencies, document these clearly in comments or
+accompanying documentation.
+
+
+## Troubleshooting `chip_operations` Issues
+
+When implementing or debugging `chip_operations`, you might encounter
+certain issues:
+
+1. **Missing Device Operations**: If devices are not being initialized
+properly, check that the `enable_dev` function is correctly
+assigning device operations based on device types. Ensure it's being
+called during bus scanning.
+
+2. **Initialization Order Problems**: If a chip's initialization depends
+on another chip being initialized first, you might need to adjust the
+initialization sequence or add explicit dependencies, possibly using
+boot state callbacks if necessary.
+
+3. **Configuration Data Issues**: If chip configuration settings are not
+being applied correctly, check that the configuration structure is
+correctly defined in `chip.h`, that the register values in the
+devicetree match the expected format, and that the `chip_info` pointer
+is cast correctly in the `init`/`final` functions.
+
+4. **Build Errors**: If you encounter build errors related to
+`chip_operations`, check that the structure is correctly defined and
+that all required symbols are properly exported and linked. Check for
+conflicts if multiple files define the same symbol.
+
+5. **Runtime Failures**: If the chip initialization fails at runtime,
+add debug logging (using `printk`) to the `init`, `enable_dev`, and
+`final` functions to identify the specific point of failure.
+
+
+## Advanced `chip_operations` Patterns
+
+### Hierarchical Chip Initialization
+
+For complex chips with multiple components, you can implement a
+hierarchical initialization pattern within the `init` function:
+
+```c
+static void soc_init(void *chip_info)
+{
+    /* Initialize common components first */
+    common_init(chip_info);
+
+    /* Initialize specific blocks */
+    pcie_init(chip_info);
+    usb_init(chip_info);
+    sata_init(chip_info);
+
+    /* Final SoC-wide configuration */
+    power_management_init(chip_info);
+}
+```
+
+
+### Variant Support
+
+For chips with multiple variants, you can implement variant detection
+and specific initialization within the `init` function:
+
+```c
+static void soc_init(void *chip_info)
+{
+    uint32_t variant = read_chip_variant();
+
+    /* Common initialization */
+    common_init(chip_info);
+
+    /* Variant-specific initialization */
+    switch (variant) {
+    case VARIANT_A:
+        variant_a_init(chip_info);
+        break;
+    case VARIANT_B:
+        variant_b_init(chip_info);
+        break;
+    default:
+        printk(BIOS_WARNING, "Unknown variant %u\\n", variant);
+        break;
+    }
+}
+```
+
+
+### Conditional Feature Initialization
+
+You can conditionally initialize features based on configuration settings
+passed via `chip_info`:
+
+```c
+static void soc_init(void *chip_info)
+{
+    struct soc_config *config = chip_info;
+
+    /* Always initialize core components */
+    core_init();
+
+    /* Conditionally initialize optional features */
+    if (config->enable_xhci)
+        xhci_init(config);
+
+    if (config->enable_sata)
+        sata_init(config);
+
+    if (config->enable_pcie)
+        pcie_init(config);
+}
+```
+
+
+## Conclusion
+
+The `chip_operations` structure is a fundamental component of coreboot's
+chipset abstraction layer. It provides a standardized interface for chipset-
+specific code to interact with coreboot's device initialization framework,
+enabling support for a wide variety of chipsets while maintaining a
+consistent initialization flow.
+
+By implementing the `chip_operations` structure for a specific chipset
+(and often for the mainboard), developers can integrate their
+hardware-specific code with coreboot's device enumeration, configuration,
+and initialization process. This structure serves as the bridge between
+the declarative device descriptions in the devicetree and the imperative
+code that initializes the hardware.
+
+Understanding the `chip_operations` structure and its role in the
+coreboot boot process is essential for anyone working on chipset or
+mainboard support in coreboot. By following the best practices and
+patterns outlined in this document, developers can create robust and
+maintainable hardware support code that integrates seamlessly with the
+coreboot firmware ecosystem.
diff --git a/Documentation/internals/index.md b/Documentation/internals/index.md
index 17dee55ada..9e55965fa1 100644
--- a/Documentation/internals/index.md
+++ b/Documentation/internals/index.md
@@ -10,5 +10,5 @@ programming APIs internal to coreboot
 
 coreboot devicetree <devicetree.md>
 coreboot devicetree language <devicetree_language.md>
-
+Chip Operations <chip_operations.md>
 ```

From 407c7d0da3e2abd49685cef43c52737d30ad12b6 Mon Sep 17 00:00:00 2001
From: Martin Roth <gaumless@gmail.com>
Date: Mon, 7 Apr 2025 12:02:47 -0600
Subject: [PATCH 0947/3886] Documentation: Add Device Operations

Change-Id: I3ed78f8ce50bb3914f55b2cbb7f5eb668706949a
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87202
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 Documentation/internals/device_operations.md | 696 +++++++++++++++++++
 Documentation/internals/index.md             |   1 +
 2 files changed, 697 insertions(+)
 create mode 100644 Documentation/internals/device_operations.md

diff --git a/Documentation/internals/device_operations.md b/Documentation/internals/device_operations.md
new file mode 100644
index 0000000000..c0c98d0ebf
--- /dev/null
+++ b/Documentation/internals/device_operations.md
@@ -0,0 +1,696 @@
+# Device Operations in coreboot Firmware
+
+## Introduction
+
+The `device_operations` structure is a cornerstone of coreboot's
+hardware abstraction layer. It represents a set of function pointers
+defining how the firmware interacts with a specific hardware device
+during various boot stages. This structure lets the coreboot
+architecture establish a consistent interface for device initialization,
+configuration, resource allocation, and ACPI table generation, while
+allowing device-specific implementations behind this common interface.
+
+At its core, `device_operations` applies the strategy pattern in
+systems programming. It decouples algorithms (device operations) from
+the core boot sequence, allowing devices to define their own behavior
+while the boot process follows a predictable flow. This pattern enables
+coreboot to support a wide range of hardware platforms with minimal
+changes to the core boot sequence code.
+
+
+## Structure Definition
+
+The `device_operations` structure, defined in
+`src/include/device/device.h`, consists of several function pointers,
+each representing a specific operation performed on a device during
+boot:
+
+```c
+struct device_operations {
+    void (*read_resources)(struct device *dev);
+    void (*set_resources)(struct device *dev);
+    void (*enable_resources)(struct device *dev);
+    void (*init)(struct device *dev);
+    void (*final)(struct device *dev);
+    void (*scan_bus)(struct device *bus);
+    void (*enable)(struct device *dev);
+    void (*vga_disable)(struct device *dev);
+    void (*reset_bus)(struct bus *bus);
+
+    int (*get_smbios_data)(struct device *dev, int *handle,
+        unsigned long *current);
+    void (*get_smbios_strings)(struct device *dev, struct smbios_type11 *t);
+
+    unsigned long (*write_acpi_tables)(const struct device *dev,
+        unsigned long start, struct acpi_rsdp *rsdp);
+    void (*acpi_fill_ssdt)(const struct device *dev);
+    const char *(*acpi_name)(const struct device *dev);
+    const char *(*acpi_hid)(const struct device *dev);
+
+    const struct pci_operations *ops_pci;
+    const struct i2c_bus_operations *ops_i2c_bus;
+    const struct spi_bus_operations *ops_spi_bus;
+    const struct smbus_bus_operations *ops_smbus_bus;
+    const struct pnp_mode_ops *ops_pnp_mode;
+    const struct gpio_operations *ops_gpio;
+    const struct mdio_bus_operations *ops_mdio;
+};
+```
+
+
+### Core Resource Management Functions
+
+*   `read_resources`: Discovers and collects resources required by the
+    device (I/O ports, memory regions, IRQs, etc.). This typically
+    involves reading configuration registers or static device tree
+    information.
+*   `set_resources`: Assigns finalized resources to the device after the
+    resource allocation phase. This writes the assigned base addresses,
+    lengths, and other parameters back to the device structure, but not
+    necessarily to hardware registers yet.
+*   `enable_resources`: Activates the assigned resources in the device's
+    hardware registers (e.g., writing to PCI BARs, enabling memory
+    decoding).
+
+
+### Device Lifecycle Functions
+
+*   `init`: Performs device-specific initialization, often requiring
+    access to the device's assigned resources. This is called after
+    resources have been enabled.
+*   `final`: Executes final setup or cleanup operations before the
+    payload is loaded. This is useful for tasks that depend on other
+    devices being initialized.
+*   `enable`: Enables the device in the hardware, often setting bits in
+    configuration registers to make the device active. Called after
+    `enable_resources`.
+
+
+### Bus Management Functions
+
+*   `scan_bus`: Enumerates child devices on a bus device (e.g., scanning
+    a PCI bus for devices, probing I2C devices). Only applicable to
+    devices that act as buses.
+*   `reset_bus`: Resets all devices on a specific bus.
+*   `vga_disable`: Disables VGA decoding on a PCI device when another VGA
+    device is active. Used to manage legacy VGA resources.
+
+
+### System Table Generation Functions
+
+*   `get_smbios_data`: Provides SMBIOS data specific to the device for
+    Type 9 (System Slots) or Type 41 (Onboard Devices Extended
+    Information).
+*   `get_smbios_strings`: Supplies string information for SMBIOS tables,
+    often related to the data provided by `get_smbios_data`.
+*   `write_acpi_tables`: Generates device-specific ACPI tables (like SSDTs)
+    or contributes data to system-wide tables.
+*   `acpi_fill_ssdt`: Adds device-specific objects (scopes, methods, data)
+    to the Secondary System Description Table (SSDT).
+*   `acpi_name`: Returns the ACPI name for the device (e.g.,
+    `\_SB.PCI0.GFX0`). This defines the device's path in the ACPI
+    namespace.
+*   `acpi_hid`: Returns the ACPI Hardware ID (HID) for the device (e.g.,
+    `PNP0A08`). Used by the OS to match drivers.
+
+
+### Bus-Specific Operation Pointers
+
+These fields point to bus-specific operation structures when a device
+functions as a bus controller (or exposes bus-like functionality). See
+the "Bus-Specific Operations" section for details.
+
+*   `ops_pci`: Operations for PCI configuration space access.
+*   `ops_i2c_bus`: Operations for I2C bus transactions (read, write,
+    transfer).
+*   `ops_spi_bus`: Operations for SPI bus transactions.
+*   `ops_smbus_bus`: Operations for SMBus transactions.
+*   `ops_pnp_mode`: Operations for Plug-and-Play device configuration.
+*   `ops_gpio`: Operations for GPIO control (get, set, configure
+    direction/pulls).
+*   `ops_mdio`: Operations for MDIO (Management Data Input/Output) bus
+    access, used for Ethernet PHYs.
+
+
+## Device Lifecycle in coreboot
+
+The function pointers in `device_operations` are called at specific
+stages during the boot process, following a sequence defined in
+coreboot's boot state machine (`src/lib/hardwaremain.c`). Understanding
+this lifecycle helps developers implement appropriate behavior for each
+function pointer.
+
+
+### Boot Sequence and Device Operations
+
+coreboot's main device initialization sequence involves these boot
+states:
+
+1.  **BS_DEV_INIT_CHIPS** (`dev_initialize_chips()`): Initializes chip
+    drivers (`chip_operations`).
+2.  **BS_DEV_ENUMERATE** (`dev_enumerate()`): Discovers and enumerates
+    devices.
+    *   Calls `scan_bus()` for each bus to detect child devices.
+3.  **BS_DEV_RESOURCES** (`dev_configure()`): Allocates resources across
+    all enumerated devices.
+    *   Calls `read_resources()` for each device to discover required
+        resources.
+    *   Calls `set_resources()` for each device to assign allocated
+        resources back to the `struct device`.
+4.  **BS_DEV_ENABLE** (`dev_enable()`): Enables devices and their
+    resources.
+    *   Calls `enable_resources()` for each device to activate assigned
+        resources in hardware.
+    *   Calls `enable()` for each device to perform general hardware
+        enablement.
+5.  **BS_DEV_INIT** (`dev_initialize()`): Initializes devices.
+    *   Calls `init()` for each device to perform device-specific setup.
+6.  **BS_POST_DEVICE** (`dev_finalize()`): Finalizes devices before
+    payload loading.
+    *   Calls `final()` for each device for any final cleanup or setup.
+
+The sequence is primarily driven by the `boot_states` array in
+`src/lib/hardwaremain.c`:
+
+```c
+static struct boot_state boot_states[] = {
+    /* ... other states ... */
+    BS_INIT_ENTRY(BS_PRE_DEVICE, bs_pre_device),
+    BS_INIT_ENTRY(BS_DEV_INIT_CHIPS, bs_dev_init_chips),
+    BS_INIT_ENTRY(BS_DEV_ENUMERATE, bs_dev_enumerate),
+    BS_INIT_ENTRY(BS_DEV_RESOURCES, bs_dev_resources),
+    BS_INIT_ENTRY(BS_DEV_ENABLE, bs_dev_enable),
+    BS_INIT_ENTRY(BS_DEV_INIT, bs_dev_init),
+    BS_INIT_ENTRY(BS_POST_DEVICE, bs_post_device),
+    /* ... other states ... */
+};
+```
+
+Later stages include ACPI and SMBIOS table generation, where functions
+like `write_acpi_tables()`, `acpi_fill_ssdt()`, `get_smbios_data()`, and
+`get_smbios_strings()` are invoked as part of the table construction
+process.
+
+
+## Inheritance and Code Reuse Patterns
+
+The `device_operations` structure enables several patterns for code
+reuse:
+
+
+### 1. Default Implementations
+
+coreboot provides default implementations for common device types (like
+root devices, PCI devices, PCI bridges), which can be used directly or
+extended. Chip or mainboard code often assigns these defaults if no
+specific driver is found.
+
+```c
+/* From src/device/root_device.c */
+struct device_operations default_dev_ops_root = {
+    .read_resources   = noop_read_resources,
+    .set_resources    = noop_set_resources,
+    .scan_bus         = scan_static_bus,
+    .reset_bus        = root_dev_reset,
+#if CONFIG(HAVE_ACPI_TABLES)
+    .acpi_name        = root_dev_acpi_name,
+#endif
+};
+```
+
+
+### 2. No-op Functions
+
+Simple shim functions (often static inline) are provided for cases where
+a device doesn't need to implement specific operations. Using these avoids
+leaving function pointers NULL.
+
+```c
+/* From src/include/device/device.h */
+static inline void noop_read_resources(struct device *dev) {}
+static inline void noop_set_resources(struct device *dev) {}
+```
+
+
+### 3. Chain of Responsibility / Delegation
+
+Some implementations delegate to parent devices or use helper functions
+when they can't handle an operation themselves or when common logic can
+be shared. For example, ACPI name generation often traverses up the
+device tree.
+
+```c
+/* Simplified example logic */
+const char *acpi_device_name(const struct device *dev)
+{
+    const char *name = NULL;
+    const struct device *pdev = dev;
+
+    /* Check for device specific handler */
+    if (dev->ops && dev->ops->acpi_name) {
+        name = dev->ops->acpi_name(dev);
+        if (name)
+            return name; /* Device handled it */
+    }
+
+    /* Walk up the tree to find if any parent can provide a name */
+    while (pdev->upstream && pdev->upstream->dev) {
+        pdev = pdev->upstream->dev;
+        if (pdev->ops && pdev->ops->acpi_name) {
+            /* Note: Parent's acpi_name might handle the original child 'dev' */
+            name = pdev->ops->acpi_name(dev);
+            if (name)
+                return name; /* Parent handled it */
+        }
+    }
+
+    /* Fallback or default logic if needed */
+    return NULL;
+}
+```
+This pattern allows parent devices (like buses) to provide default
+behavior or naming schemes if a child device doesn't specify its own.
+
+
+## Implementation Examples
+
+These examples show typical `device_operations` assignments. Actual
+implementations might involve more conditional compilation based on
+Kconfig options.
+
+
+### PCI Device Operations (Default)
+
+```c
+/* From src/device/pci_device.c */
+struct device_operations default_pci_ops_dev = {
+    .read_resources   = pci_dev_read_resources,
+    .set_resources    = pci_dev_set_resources,
+    .enable_resources = pci_dev_enable_resources,
+#if CONFIG(HAVE_ACPI_TABLES)
+    .write_acpi_tables = pci_rom_write_acpi_tables,
+    .acpi_fill_ssdt    = pci_rom_ssdt,
+#endif
+    .init             = pci_dev_init,
+    /* Assigns PCI-specific operations */
+    .ops_pci          = &pci_dev_ops_pci,
+};
+```
+
+
+### CPU Cluster Operations
+
+```c
+/* From src/soc/intel/alderlake/chip.c (representative example) */
+static struct device_operations cpu_bus_ops = {
+    .read_resources   = noop_read_resources,
+    .set_resources    = noop_set_resources,
+    .enable_resources = cpu_set_north_irqs,
+#if CONFIG(HAVE_ACPI_TABLES)
+    .acpi_fill_ssdt = cpu_fill_ssdt,
+#endif
+    /* CPU clusters often don't need scan_bus, init, etc. */
+};
+```
+
+
+### GPIO Controller Operations
+
+```c
+/* From src/soc/intel/common/block/gpio/gpio_dev.c */
+static struct gpio_operations gpio_ops = {
+    .get         = gpio_get,
+    .set         = gpio_set,
+    /* ... other GPIO functions ... */
+};
+
+struct device_operations block_gpio_ops = {
+    .read_resources = noop_read_resources,
+    .set_resources  = noop_set_resources,
+    /* Assigns GPIO-specific operations */
+    .ops_gpio      = &gpio_ops,
+};
+```
+
+
+## Registration and Discovery
+
+How are `device_operations` structures associated with `struct device`
+instances?
+
+
+### 1. Static Assignment (via `chip_operations`)
+
+For devices known at build time (defined in devicetree.cb), the
+`device_operations` structure is often assigned in the SOC's or
+mainboard's `chip_operations->enable_dev()` function based on the
+device path type or other properties.
+
+```c
+/* Example from src/soc/intel/alderlake/chip.c */
+static void soc_enable(struct device *dev)
+{
+    /* Assign ops based on the device's role in the tree */
+    if (dev->path.type == DEVICE_PATH_DOMAIN)
+        dev->ops = &pci_domain_ops; /* Handles PCI domain resources */
+    else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER)
+        dev->ops = &cpu_bus_ops;   /* Handles CPU cluster setup */
+    else if (dev->path.type == DEVICE_PATH_GPIO)
+        block_gpio_enable(dev); /* Assigns block_gpio_ops */
+    /* ... other assignments for specific PCI devices, etc. ... */
+}
+```
+The `enable_dev` function is part of `struct chip_operations`, which
+handles broader chip-level initialization (see "Relationship with
+`chip_operations`" section).
+
+
+### 2. Dynamic Detection (PCI Drivers)
+
+For PCI devices discovered during bus scanning (`scan_bus`), coreboot
+looks through a list of registered PCI drivers (`_pci_drivers` array)
+to find one matching the device's vendor and device IDs.
+
+```c
+/* Logic from src/device/pci_device.c::set_pci_ops() */
+static void set_pci_ops(struct device *dev)
+{
+    struct pci_driver *driver;
+
+    /* Check if ops already assigned (e.g., by chip_ops->enable_dev) */
+    if (dev->ops)
+        return;
+
+    /* Look through registered PCI drivers */
+    for (driver = &_pci_drivers[0]; driver != &_epci_drivers[0]; driver++) {
+        if ((driver->vendor == dev->vendor) &&
+            device_id_match(driver, dev->device)) {
+            /* Found a matching driver, assign its ops */
+            dev->ops = (struct device_operations *)driver->ops;
+            printk(BIOS_SPEW, "%s: Assigned ops from driver for %04x:%04x\n",
+                   dev_path(dev), driver->vendor, driver->device);
+            return; /* Stop searching */
+        }
+    }
+
+    /* Fall back to default operations if no specific driver found */
+    if (!dev->ops) {
+        if ((dev->hdr_type & 0x7f) == PCI_HEADER_TYPE_BRIDGE) {
+            dev->ops = get_pci_bridge_ops(dev); /* Special ops for bridges */
+        } else {
+            dev->ops = &default_pci_ops_dev; /* Default for normal devices */
+        }
+        printk(BIOS_SPEW, "%s: Assigned default PCI ops\n", dev_path(dev));
+    }
+}
+```
+
+
+## Build Process Integration
+
+The `device_operations` structures are integrated into the coreboot
+build process:
+
+1.  **Static Device Tree**: The mainboard's `devicetree.cb` defines the
+    initial device hierarchy. The build process converts this into C
+    code (`static.c`) containing `struct device` instances.
+2.  **PCI Driver Registration**: PCI drivers (containing their own
+    `device_operations`) register themselves using the `__pci_driver`
+    linker set macro.
+
+    ```c
+    /* Example pattern */
+    struct pci_driver example_pci_driver __pci_driver = {
+        .ops    = &example_device_ops, /* Pointer to device_operations */
+        .vendor = VENDOR_ID,
+        .device = DEVICE_ID, /* Or .devices for a list */
+    };
+    ```
+3.  **Linking**: The build system collects all structures placed in the
+    `__pci_driver` section and creates the `_pci_drivers` array used by
+    `set_pci_ops()`. It ensures all necessary code (default ops, driver
+    ops, core device functions) is linked into the final firmware image.
+
+
+## Relationship with `chip_operations`
+
+It's important to distinguish `device_operations` from
+`chip_operations` (defined in `src/include/chip.h`).
+
+*   `chip_operations`: Defines operations related to the overall chipset
+    or mainboard logic. It includes functions called earlier in the boot
+    process, like `enable_dev`, `init`, and `final`.
+    *   `chip_operations->enable_dev()` is crucial as it often performs
+        initial setup for static devices and is the primary place where
+        `device_operations` pointers are *assigned* for non-PCI devices
+        based on their path or type.
+    *   `chip_operations->init()` runs during `BS_DEV_INIT_CHIPS`, before
+        most `device_operations` functions.
+*   `device_operations`: Defines operations for *individual* devices
+    within the device tree. These are called *after* the corresponding
+    `chip_operations` stage and operate on a specific `struct device`.
+
+Essentially, `chip_operations` sets the stage at the SoC/mainboard level,
+including assigning the correct `device_operations` to static devices,
+while `device_operations` handles the specific actions for each device
+later in the boot process.
+
+
+## Bus-Specific Operations
+
+The `ops_*` pointers within `struct device_operations` (e.g., `ops_pci`,
+`ops_i2c_bus`, `ops_spi_bus`, `ops_gpio`) provide a way for devices that
+act as bus controllers or expose bus-like interfaces to offer
+standardized access methods.
+
+*   **Purpose:** They abstract the low-level details of interacting with
+    that specific bus type. For example, a PCI host bridge device will
+    implement `struct pci_operations` via its `ops_pci` pointer,
+    allowing other code to perform PCI config reads/writes through it
+    without knowing the exact hardware mechanism. Similarly, an I2C
+    controller device implements `struct i2c_bus_operations` via
+    `ops_i2c_bus` to provide standard `read`, `write`, and `transfer`
+    functions for that bus segment.
+*   **Usage:** Code needing to interact with a bus first finds the
+    controller `struct device` in the tree, then accesses the relevant
+    bus operations through the appropriate `ops_*` pointer, passing the
+    target address or parameters. For instance, to talk to an I2C device
+    at address `0x50` on the bus controlled by `i2c_controller_dev`, one
+    might call:
+    `i2c_controller_dev->ops->ops_i2c_bus->transfer(...)`. Helper
+    functions often wrap this access pattern.
+*   **Implementation:** The structures like `struct pci_operations`,
+    `struct i2c_bus_operations`, etc., are defined in corresponding
+    header files (e.g., `src/include/device/pci_ops.h`,
+    `src/include/drivers/i2c/i2c_bus.h`). Devices acting as controllers
+    provide concrete implementations of these functions, tailored to their
+    hardware.
+
+This mechanism allows coreboot to manage diverse bus types using a
+consistent device model, where the controller device itself exposes the
+necessary functions for interacting with devices on its bus.
+
+
+## Best Practices
+
+When implementing `device_operations`:
+
+1.  **Leverage Defaults/No-ops**: Use default or no-op implementations
+    whenever possible. Only override functions that require custom
+    behavior for your specific device.
+2.  **Error Handling**: Check return values from functions called within
+    your ops implementations and handle errors gracefully (e.g., log an
+    error, return an error code if applicable).
+3.  **Resource Management**: In `read_resources`, accurately declare all
+    resources (MMIO, I/O ports, IRQs) your device needs, specifying
+    flags like fixed vs. alignment, or bridge vs. standard device.
+    Incorrect resource declaration is a common source of issues.
+4.  **Initialization Order**: Be mindful of dependencies in `init`. If
+    your device relies on another device being fully initialized, consider
+    deferring that part of the initialization to the `final` callback,
+    which runs later.
+5.  **Minimal Implementation**: Only implement the functions relevant to
+    your device type. A simple MMIO device might only need
+    `read_resources`, `set_resources`, `enable_resources`, and perhaps
+    ACPI functions. A bus device additionally needs `scan_bus`.
+6.  **Bus Operations**: If implementing a bus controller, correctly
+    implement the corresponding bus operations structure (e.g.,
+    `struct pci_operations`, `struct i2c_bus_operations`) and assign it
+    to the appropriate `ops_*` field.
+7.  **ACPI/SMBIOS**: If the device needs OS visibility via ACPI or
+    SMBIOS, implement the relevant functions (`acpi_name`, `acpi_hid`,
+    `acpi_fill_ssdt`, `get_smbios_data`, etc.). Ensure ACPI names and
+    HIDs are correct according to specifications and platform needs.
+
+
+## Logging and Debugging
+
+Use coreboot's logging facilities (`printk`) within your `device_operations`
+functions to provide visibility during development and debugging. Use
+appropriate log levels (e.g., `BIOS_DEBUG`, `BIOS_INFO`, `BIOS_ERR`).
+
+```c
+static void example_device_init(struct device *dev)
+{
+    printk(BIOS_DEBUG, "%s: Initializing device at %s\n", __func__,
+           dev_path(dev));
+
+    /* ... Device initialization code ... */
+    if (/* some condition */) {
+        printk(BIOS_SPEW, "%s: Condition met, applying setting X\n",
+               dev_path(dev));
+        /* ... */
+    }
+
+    if (/* error condition */) {
+        printk(BIOS_ERR, "%s: Failed to initialize feature Y!\n",
+               dev_path(dev));
+        /* Handle error */
+    }
+
+    printk(BIOS_DEBUG, "%s: Initialization complete for %s\n", __func__,
+           dev_path(dev));
+}
+```
+Consistent logging helps trace the boot process and pinpoint where issues
+occur.
+
+
+## Common Troubleshooting
+
+*   **Missing Resource Declarations**:
+    *   *Problem*: Device fails to function, or conflicts arise because a
+        required resource (MMIO range, I/O port, IRQ) was not declared
+        in `read_resources`. The resource allocator is unaware of the
+        need.
+    *   *Solution*: Verify that `read_resources` correctly calls functions
+        like `pci_dev_read_resources` or manually adds all necessary
+        resources using functions like `mmio_resource()`,
+        `io_resource()`, etc. Check PCI BARs or device datasheets.
+*   **Initialization Order Issues**:
+    *   *Problem*: `init()` fails because it depends on another device
+        that hasn't been fully initialized yet (e.g., accessing a shared
+        resource like SMBus before the SMBus controller is ready).
+    *   *Solution*: Move the dependent initialization code to the `final`
+        callback if possible. Alternatively, ensure the dependency is met
+        by careful ordering in the device tree or using boot state
+        callbacks if necessary for complex scenarios.
+*   **Resource Conflicts**:
+    *   *Problem*: Boot fails during resource allocation, or devices
+        misbehave because multiple devices requested the same
+        non-sharable resource (e.g., conflicting fixed MMIO regions).
+    *   *Solution*: Review resource declarations in `read_resources` across
+        all relevant devices. Ensure fixed resources don't overlap. Check
+        if bridge windows are correctly defined and large enough. Use
+        coreboot's resource reporting logs to identify overlaps.
+*   **ACPI Table Generation Errors**:
+    *   *Problem*: The operating system fails to recognize the device,
+        assigns the wrong driver, or the device doesn't function correctly
+        (e.g., power management issues).
+    *   *Solution*: Double-check the `acpi_name`, `acpi_hid`, `_CRS`
+        (generated from assigned resources), and `acpi_fill_ssdt`
+        implementations. Verify names match the ACPI hierarchy and HIDs
+        match expected driver bindings. Ensure SSDT methods correctly
+        access hardware. Use OS debugging tools (e.g., `acpidump`, Device
+        Manager errors) to diagnose.
+*   **Incorrect `ops` Pointer Assigned**:
+    *   *Problem*: Device behaves incorrectly because the wrong
+        `device_operations` structure was assigned (e.g., default PCI ops
+        assigned to a device needing a specific driver's ops).
+    *   *Solution*: Check the logic in `chip_operations->enable_dev` (for
+        static devices) or the PCI driver registration (`__pci_driver`
+        macro and `set_pci_ops` fallback logic) to ensure the correct
+        `ops` structure is being selected and assigned based on device
+        type, path, or PCI ID. Add debug prints to verify which `ops`
+        structure is assigned.
+
+
+## Advanced Usage
+
+### Complex Device Hierarchies
+
+For devices with non-standard interactions or complex initialization,
+custom `device_operations` can be created, often inheriting from defaults
+but overriding specific functions.
+
+```c
+static void advanced_device_init(struct device *dev)
+{
+    /* First, perform standard PCI init */
+    pci_dev_init(dev);
+
+    /* Then, add custom initialization steps */
+    printk(BIOS_DEBUG, "%s: Performing advanced init\n", dev_path(dev));
+    /* ... custom register writes, configuration ... */
+}
+
+static const char *advanced_device_acpi_name(const struct device *dev)
+{
+    /* Provide a custom ACPI name based on some property */
+    if (/* condition */)
+        return "ADV0001";
+    else
+        return "ADV0002";
+}
+
+/* Combine default and custom operations */
+static struct device_operations advanced_device_ops = {
+    /* Inherit resource handling from default PCI ops */
+    .read_resources   = pci_dev_read_resources,
+    .set_resources    = pci_dev_set_resources,
+    .enable_resources = pci_dev_enable_resources,
+
+    /* Override init */
+    .init             = advanced_device_init,
+
+    /* Override ACPI naming */
+    .acpi_name        = advanced_device_acpi_name,
+    /* Other functions might use defaults or no-ops */
+};
+```
+
+### Dynamic Configuration based on Probing
+
+Some `init` or other op implementations might probe the device's
+capabilities or read configuration data (e.g., from SPD, VPD, or straps)
+and alter their behavior accordingly.
+
+```c
+static void conditional_device_init(struct device *dev)
+{
+    uint8_t feature_flags;
+
+    /* Read capability register from the device */
+    feature_flags = pci_read_config8(dev, EXAMPLE_CAP_REG);
+
+    printk(BIOS_DEBUG, "%s: Feature flags: 0x%02x\n", dev_path(dev),
+           feature_flags);
+
+    /* Conditional initialization based on detected features */
+    if (feature_flags & FEATURE_X_ENABLED) {
+        printk(BIOS_INFO, "%s: Initializing Feature X\n", dev_path(dev));
+        init_feature_x(dev);
+    }
+    if (feature_flags & FEATURE_Y_ENABLED) {
+        printk(BIOS_INFO, "%s: Initializing Feature Y\n", dev_path(dev));
+        init_feature_y(dev);
+    }
+}
+```
+
+
+## Conclusion
+
+The `device_operations` structure is a powerful abstraction mechanism in
+coreboot. It enables consistent handling of diverse hardware while
+allowing for device-specific behavior. By providing a standard interface
+for device operations throughout the boot process, it simplifies the
+codebase, enhances maintainability, and provides the extensibility needed
+to support new hardware platforms.
+
+Understanding this structure, its relationship with `chip_operations`,
+and its role in the boot process is essential for coreboot developers,
+particularly when adding support for new devices or debugging hardware
+initialization issues. By following the patterns and best practices
+outlined here, developers can create robust and reusable device driver
+implementations that integrate smoothly into the coreboot architecture.
diff --git a/Documentation/internals/index.md b/Documentation/internals/index.md
index 9e55965fa1..56c8221793 100644
--- a/Documentation/internals/index.md
+++ b/Documentation/internals/index.md
@@ -11,4 +11,5 @@ programming APIs internal to coreboot
 coreboot devicetree <devicetree.md>
 coreboot devicetree language <devicetree_language.md>
 Chip Operations <chip_operations.md>
+Device Operations <device_operations>
 ```

From 3fe4b00966e0eadd56c627bfa70fb846d66eb731 Mon Sep 17 00:00:00 2001
From: John Su <john_su@compal.corp-partner.google.com>
Date: Mon, 5 May 2025 15:21:32 +0800
Subject: [PATCH 0948/3886] mb/trulo/var/uldrenite: Swap ISH UART from UART1 to
 UART0

As per the requirement, the ISH UART needs to be the same as Trulo, so
swap ISH UART from UART1 to UART0. And configure ISH_UART0 GPIO;
if not used, the pins will be set to NC. Additionally, the LCD_CBL_DET#
pin has been changed from GPP_D14 to GPP_D18.

BUG=b:415605630, b:411249861
TEST=emerge-nissa coreboot

Change-Id: I88bca9a56fa96ad0a52c29fec12b8d4dbee23be4
Signed-off-by: John Su <john_su@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87535
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
---
 .../google/brya/variants/uldrenite/gpio.c        | 16 ++++++++--------
 .../google/brya/variants/uldrenite/variant.c     |  4 ++++
 2 files changed, 12 insertions(+), 8 deletions(-)

diff --git a/src/mainboard/google/brya/variants/uldrenite/gpio.c b/src/mainboard/google/brya/variants/uldrenite/gpio.c
index d453adb181..667a369604 100644
--- a/src/mainboard/google/brya/variants/uldrenite/gpio.c
+++ b/src/mainboard/google/brya/variants/uldrenite/gpio.c
@@ -143,18 +143,18 @@ static const struct pad_config gpio_table[] = {
 	PAD_NC_LOCK(GPP_D11, NONE, LOCK_CONFIG),
 	/* D12 : ISH_SPI_MOSI ==> GPP_D12_STRAP */
 	PAD_NC_LOCK(GPP_D12, NONE, LOCK_CONFIG),
-	/* D13 : UART0_ISH_RXD ==> NC */
-	PAD_NC(GPP_D13, NONE),
-	/* D14 : UART0_ISH_TXD ==> LCD_CBL_DET# */
-	PAD_CFG_GPO(GPP_D14, 1, DEEP),
+	/* D13 : UART0_ISH_RXD */
+	PAD_CFG_NF(GPP_D13, NONE, DEEP, NF1),
+	/* D14 : UART0_ISH_TXD */
+	PAD_CFG_NF(GPP_D14, NONE, DEEP, NF1),
 	/* D15  : GPP_D15 ==> SOC_TS_I2C_RST# */
 	PAD_CFG_GPO_LOCK(GPP_D15, 1, LOCK_CONFIG),
 	/* D16 : ISH_UART0_CTS# ==> SOC_TS_I2C_INT# */
 	PAD_CFG_GPI_APIC(GPP_D16, NONE, PLTRST, LEVEL, INVERT),
-	/* D17 : NC ==> UART1_ISH_RX_DBG_TX */
-	PAD_CFG_NF(GPP_D17, NONE, DEEP, NF2),
-	/* D18 : NC ==> UART1_ISH_TX_DBG_RX */
-	PAD_CFG_NF(GPP_D18, NONE, DEEP, NF2),
+	/* D17 : NC */
+	PAD_NC(GPP_D17, NONE),
+	/* D18 : LCD_CBL_DET# */
+	PAD_CFG_GPO(GPP_D18, 1, DEEP),
 	/* D19 : I2S_MCLK1_OUT ==> NC */
 	PAD_NC(GPP_D19, NONE),
 
diff --git a/src/mainboard/google/brya/variants/uldrenite/variant.c b/src/mainboard/google/brya/variants/uldrenite/variant.c
index f5d01c1a89..a2ed02247d 100644
--- a/src/mainboard/google/brya/variants/uldrenite/variant.c
+++ b/src/mainboard/google/brya/variants/uldrenite/variant.c
@@ -50,6 +50,10 @@ static const struct pad_config ish_disable_pads[] = {
 	PAD_NC(GPP_B6, NONE),
 	/* D1  : ISH_GP1 ==> NC */
 	PAD_NC(GPP_D1, NONE),
+	/* D13  : UART0_ISH_RXD ==> NC */
+	PAD_NC(GPP_D13, NONE),
+	/* D14  : UART0_ISH_TXD ==> NC */
+	PAD_NC(GPP_D14, NONE),
 	/* E9  : SOC_ACC2_INT ==> NC */
 	PAD_NC_LOCK(GPP_E9, NONE, LOCK_CONFIG),
 };

From 60916d0f100919e8ba14c8cfece68bcd14730f2a Mon Sep 17 00:00:00 2001
From: John Su <john_su@compal.corp-partner.google.com>
Date: Wed, 7 May 2025 00:56:32 +0800
Subject: [PATCH 0949/3886] mb/trulo/var/uldrenite: Support different ISH UART
 mappings

Due to the ISH UART configuration change and the need to support
different phases of the motherboard, we use the board ID to
distinguish which configuration to apply.

BUG=b:415605630, b:411249861
TEST=emerge-nissa coreboot

Change-Id: Id6e0e67595d3b4a44382ce82d160fe865cda275c
Signed-off-by: John Su <john_su@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87567
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
---
 .../google/brya/variants/uldrenite/variant.c  | 54 +++++++++++++++++--
 1 file changed, 49 insertions(+), 5 deletions(-)

diff --git a/src/mainboard/google/brya/variants/uldrenite/variant.c b/src/mainboard/google/brya/variants/uldrenite/variant.c
index a2ed02247d..75809e233f 100644
--- a/src/mainboard/google/brya/variants/uldrenite/variant.c
+++ b/src/mainboard/google/brya/variants/uldrenite/variant.c
@@ -41,7 +41,7 @@ static const struct pad_config lte_disable_pads[] = {
 	PAD_NC(GPP_H23, NONE),
 };
 
-static const struct pad_config ish_disable_pads[] = {
+static const struct pad_config ish_uart0_disable_pads[] = {
 	/* A16 : ISH_GP5 ==> NC */
 	PAD_NC_LOCK(GPP_A16, NONE, LOCK_CONFIG),
 	/* B5  : GPP_B5 ==> NC */
@@ -58,8 +58,38 @@ static const struct pad_config ish_disable_pads[] = {
 	PAD_NC_LOCK(GPP_E9, NONE, LOCK_CONFIG),
 };
 
+static const struct pad_config switch_ish_uart1_pads[] = {
+	/* D13  : UART0_ISH_RXD ==> NC  */
+	PAD_NC(GPP_D13, NONE),
+	/* D14  : UART0_ISH_TXD ==> LCD_CBL_DET# */
+	PAD_CFG_GPO(GPP_D14, 1, DEEP),
+	/* D17 : NC ==> UART1_ISH_RDX */
+	PAD_CFG_NF(GPP_D17, NONE, DEEP, NF2),
+	/* D18 : LCD_CBL_DET# ==> UART1_ISH_TDX */
+	PAD_CFG_NF(GPP_D18, NONE, DEEP, NF2),
+};
+
+static const struct pad_config ish_uart1_disable_pads[] = {
+	/* A16 : ISH_GP5 ==> NC */
+	PAD_NC_LOCK(GPP_A16, NONE, LOCK_CONFIG),
+	/* B5  : GPP_B5 ==> NC */
+	PAD_NC(GPP_B5, NONE),
+	/* B6  : GPP_B6 ==> NC */
+	PAD_NC(GPP_B6, NONE),
+	/* D1  : ISH_GP1 ==> NC */
+	PAD_NC(GPP_D1, NONE),
+	/* D17 : UART1_ISH_RDX ==> NC */
+	PAD_NC(GPP_D17, NONE),
+	/* D18 : UART1_ISH_TDX ==> NC*/
+	PAD_NC(GPP_D18, NONE),
+	/* E9  : SOC_ACC2_INT ==> NC */
+	PAD_NC_LOCK(GPP_E9, NONE, LOCK_CONFIG),
+};
+
 void fw_config_gpio_padbased_override(struct pad_config *padbased_table)
 {
+	uint32_t board_version = board_id();
+
 	if (fw_config_probe(FW_CONFIG(TOUCHSCREEN, TOUCHSCREEN_NONE))) {
 		printk(BIOS_INFO, "Disable touchscreen GPIO pins.\n");
 		gpio_padbased_override(padbased_table, touchscreen_disable_pads,
@@ -70,10 +100,24 @@ void fw_config_gpio_padbased_override(struct pad_config *padbased_table)
 		gpio_padbased_override(padbased_table, lte_disable_pads,
 				ARRAY_SIZE(lte_disable_pads));
 	}
-	if (!fw_config_probe(FW_CONFIG(ISH, ISH_ENABLE))) {
-		printk(BIOS_INFO, "Disable ISH GPIO pins.\n");
-		gpio_padbased_override(padbased_table, ish_disable_pads,
-				ARRAY_SIZE(ish_disable_pads));
+
+	/* b/415605630: Support different ISH UART mappings according the board id */
+	if (board_version < 2) {
+		/* Override ISH UART0 to ISH UART1 */
+		gpio_padbased_override(padbased_table, switch_ish_uart1_pads,
+			ARRAY_SIZE(switch_ish_uart1_pads));
+
+		if (!fw_config_probe(FW_CONFIG(ISH, ISH_ENABLE))) {
+			printk(BIOS_INFO, "Disable ISH GPIO pins is based on ISH UART1.\n");
+			gpio_padbased_override(padbased_table, ish_uart1_disable_pads,
+				ARRAY_SIZE(ish_uart1_disable_pads));
+		}
+	} else {
+		if (!fw_config_probe(FW_CONFIG(ISH, ISH_ENABLE))) {
+			printk(BIOS_INFO, "Disable ISH GPIO pins is based on ISH UART0.\n");
+			gpio_padbased_override(padbased_table, ish_uart0_disable_pads,
+				ARRAY_SIZE(ish_uart0_disable_pads));
+		}
 	}
 }
 

From da291075728fb69d8a789a7e64d2aaeee6289408 Mon Sep 17 00:00:00 2001
From: Subrata Banik <subratabanik@google.com>
Date: Wed, 7 May 2025 17:35:18 +0530
Subject: [PATCH 0950/3886] mb/google/fatcat/var/francka: Reduce generic reset
 delay to 10ms

The existing 200ms `generic.reset_delay_ms` for the Francka variant
is unnecessarily long. This commit reduces the delay to 10ms.

A 10ms delay has been verified as adequate for the hardware to reset
correctly, maintaining touchscreen operation post-boot. This change
contributes to a slightly faster resume sequence (optimized by ~190ms)
by removing a superfluous wait time.

BUG=b:411164455
TEST=Able to boot google/francka with touchscreen functional.

Change-Id: I8984617669c804b7d4ad32b3c67d87f3027fa1c1
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87568
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Pranava Y N <pranavayn@google.com>
---
 src/mainboard/google/fatcat/variants/francka/overridetree.cb | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/mainboard/google/fatcat/variants/francka/overridetree.cb b/src/mainboard/google/fatcat/variants/francka/overridetree.cb
index b44cdc6291..405be4547d 100644
--- a/src/mainboard/google/fatcat/variants/francka/overridetree.cb
+++ b/src/mainboard/google/fatcat/variants/francka/overridetree.cb
@@ -206,7 +206,7 @@ chip soc/intel/pantherlake
 				register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_E01_IRQ)"
 				register "generic.detect" = "1"
 				register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B08)"
-				register "generic.reset_delay_ms" = "200"
+				register "generic.reset_delay_ms" = "10"
 				register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B18)"
 				register "generic.enable_delay_ms" = "12"
 				register "generic.has_power_resource" = "1"

From aa1eba2f254d570469ff3bdd77423f518083e88d Mon Sep 17 00:00:00 2001
From: Subrata Banik <subratabanik@google.com>
Date: Fri, 9 May 2025 08:58:42 +0000
Subject: [PATCH 0951/3886] drivers/intel/fsp2_0: Enable firmware splash using
 24-bit BMP logo

The get_color_map_num function previously returned 0 for both error
conditions (e.g., NULL header, invalid image offset) and for BMPs
that legitimately lack a color map, such as 24-bit BMP logo. This
ambiguity prevented the correct processing of 24-bit BMPs for
firmware splash screens, as the caller could not distinguish them
from malformed images.

This commit addresses this by refining error handling:
1. Modifying `get_color_map_num` to return -1 for actual errors.
2. Ensuring a return value of 0 from `get_color_map_num` now
   unambiguously signifies that the BMP has no color map. This
   is relevant for formats like 24-bit or 32-bit, where the
   default switch case now explicitly sets the color map count to 0.
3. Changing the function's return type and its internal color map
   count variable (`col_map_number`) to `int` to accommodate the
   negative error code.
4. Updating the caller, `fsp_convert_bmp_to_gop_blt`, to check for
   a return value `< 0` to identify errors, separating these from
   the valid no-colormap case (return 0).

These changes enable the successful rendering of 24-bit BMP images
as firmware splash screens. This also provides more robust BMP
parsing and clearer error distinction overall.

BUG=b:410318591
TEST=Able to build and boot google/fatcat. Verified 24-bit
BMP logo is able to render successful.

Change-Id: I7006e823e10b9892da17ff904095ef5892bb690d
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87581
Reviewed-by: Jayvik Desai <jayvik@google.com>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/drivers/intel/fsp2_0/fsp_gop_blt.c | 15 ++++++++++-----
 1 file changed, 10 insertions(+), 5 deletions(-)

diff --git a/src/drivers/intel/fsp2_0/fsp_gop_blt.c b/src/drivers/intel/fsp2_0/fsp_gop_blt.c
index 087fb02df0..2ab716c4b7 100644
--- a/src/drivers/intel/fsp2_0/fsp_gop_blt.c
+++ b/src/drivers/intel/fsp2_0/fsp_gop_blt.c
@@ -100,12 +100,12 @@ static uint32_t calculate_blt_buffer_size(efi_bmp_image_header *header)
 	return blt_buffer_size;
 }
 
-static uint32_t get_color_map_num(efi_bmp_image_header *header)
+static int get_color_map_num(efi_bmp_image_header *header)
 {
-	uint32_t col_map_number = 0;
+	int col_map_number;
 
 	if (header == NULL)
-		return 0;
+		return -1;
 
 	switch (header->BitPerPixel) {
 	case 1:
@@ -118,6 +118,11 @@ static uint32_t get_color_map_num(efi_bmp_image_header *header)
 		col_map_number = 256;
 		break;
 	default:
+		/*
+		 * For other bit depths (e.g., 24-bit and 32-bit) that doesn't have
+		 * a standard palette, col_map_number remains 0.
+		 */
+		col_map_number = 0;
 		break;
 	}
 
@@ -127,7 +132,7 @@ static uint32_t get_color_map_num(efi_bmp_image_header *header)
 	 */
 	if (header->ImageOffset - sizeof(efi_bmp_image_header) <
 			 sizeof(efi_bmp_color_map) * col_map_number)
-		return 0;
+		return -1;
 
 	return col_map_number;
 }
@@ -450,7 +455,7 @@ void fsp_convert_bmp_to_gop_blt(efi_uintn_t *logo, uint32_t *logo_size,
 	if (!blt_buffer_size)
 		return;
 
-	if (!get_color_map_num(bmp_header))
+	if (get_color_map_num(bmp_header) < 0)
 		return;
 
 	bool is_standard_orientation = (orientation == LB_FB_ORIENTATION_NORMAL ||

From 183c414577fc31e83304eac582956b75118edeef Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Mon, 24 Mar 2025 14:01:34 +0000
Subject: [PATCH 0952/3886] soc/intel/meteorlake: Add Kconfig to skip FSP TBT
 connect topology
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Add a Kconfig to direct FSP to skip sending the TBT Connect Topology
(CNTP) command, which is not needed when using software connection
manager (as opposed to firmware connection manager). There are also
situations where boards using FW CM may wish to skip sending the
command.

When selected, the FSP UPD ITbtConnectTopologyTimeoutInMs will be set
to zero, which tells FSP to skip sending the command.

Previous SoCs always set this UPD to zero, but upon discussion it was
determined that this is not universally desirable, so guard it with a
Kconfig.

Change-Id: I634dfb9969410b57e8415ac659fa3e8d6943d52c
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86989
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
---
 src/soc/intel/meteorlake/Kconfig      | 12 ++++++++++++
 src/soc/intel/meteorlake/fsp_params.c |  7 +++++++
 2 files changed, 19 insertions(+)

diff --git a/src/soc/intel/meteorlake/Kconfig b/src/soc/intel/meteorlake/Kconfig
index 8a51abd496..cbab6a7f7c 100644
--- a/src/soc/intel/meteorlake/Kconfig
+++ b/src/soc/intel/meteorlake/Kconfig
@@ -458,4 +458,16 @@ config SOC_PHYSICAL_ADDRESS_WIDTH
 	int
 	default 42
 
+config SKIP_SEND_CONNECT_TOPOLOGY_CMD
+	bool
+	default y if SOFTWARE_CONNECTION_MANAGER
+	default n
+	help
+	  When selected, the FSP UPD ITbtConnectTopologyTimeoutInMs will be set to
+	  zero, causing FSP to skip sending the Connect Topology (CNTP) command,
+	  which by default has a 5s timeout. CNTP is not needed when using software
+	  connection manager, and sending it will cause a 5-10s boot delay.
+	  Mainboards which use firmware connection manager may also wish to select this
+	  as needed.
+
 endif
diff --git a/src/soc/intel/meteorlake/fsp_params.c b/src/soc/intel/meteorlake/fsp_params.c
index 30ea478432..8c3ceb75cc 100644
--- a/src/soc/intel/meteorlake/fsp_params.c
+++ b/src/soc/intel/meteorlake/fsp_params.c
@@ -396,6 +396,13 @@ static void fill_fsps_tcss_params(FSP_S_CONFIG *s_cfg,
 	/* Explicitly clear this field to avoid using defaults */
 	memset(s_cfg->IomTypeCPortPadCfg, 0, sizeof(s_cfg->IomTypeCPortPadCfg));
 
+	/*
+	 * Set ITbtConnectTopologyTimeoutInMs to 0 if config selected,
+	 * in order to skip sending the connect toplogy (CNTP) command.
+	 */
+	if (CONFIG(SKIP_SEND_CONNECT_TOPOLOGY_CMD))
+		s_cfg->ITbtConnectTopologyTimeoutInMs = 0;
+
 	/* D3Hot and D3Cold for TCSS */
 	s_cfg->D3HotEnable = !config->tcss_d3_hot_disable;
 	s_cfg->D3ColdEnable = CONFIG(D3COLD_SUPPORT);

From 4aa1861fbbf9976e139aae6a37840490a0cf9c24 Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Wed, 26 Mar 2025 21:13:37 +0000
Subject: [PATCH 0953/3886] mb/starlabs/starbook/mtl: Configure sleep assertion
 times

Configure these to match the other Star Labs boards.

Change-Id: Icb57f58902cc6cf2e1faf40194a6a500c6280882
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87017
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
---
 src/mainboard/starlabs/starbook/variants/mtl/devicetree.cb | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/src/mainboard/starlabs/starbook/variants/mtl/devicetree.cb b/src/mainboard/starlabs/starbook/variants/mtl/devicetree.cb
index b86e01bc15..11b969fd26 100644
--- a/src/mainboard/starlabs/starbook/variants/mtl/devicetree.cb
+++ b/src/mainboard/starlabs/starbook/variants/mtl/devicetree.cb
@@ -18,6 +18,12 @@ chip soc/intel/meteorlake
 		[PchSerialIoIndexUART0]			= PchSerialIoSkipInit,
 	}"
 
+	# Power
+	register "pch_slp_s3_min_assertion_width"	= "SLP_S3_ASSERTION_1_MS"
+	register "pch_slp_s4_min_assertion_width"	= "SLP_S4_ASSERTION_3S"
+	register "pch_slp_sus_min_assertion_width"	= "SLP_SUS_ASSERTION_1_S"
+	register "pch_slp_a_min_assertion_width"	= "SLP_A_ASSERTION_98_MS"
+
 	# Device Tree
 	device domain 0 on
 		device ref igpu		on

From d50019d432066a9a234a9ca5357f291024e0525c Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Wed, 7 May 2025 10:33:01 -0500
Subject: [PATCH 0954/3886] mb/starlabs/starbook_mtl: Select
 SKIP_SEND_CONNECT_TOPOLOGY_CMD

Not needed for this is board, and using the default timeout value
causes boot delays when the public IOT FSP is used.

TEST=build/boot starbook MTL.

Change-Id: Ia87e4239dbff57894af4c7b4b2857f809007843d
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87569
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/starlabs/starbook/Kconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/src/mainboard/starlabs/starbook/Kconfig b/src/mainboard/starlabs/starbook/Kconfig
index be0ed13177..a948e45c76 100644
--- a/src/mainboard/starlabs/starbook/Kconfig
+++ b/src/mainboard/starlabs/starbook/Kconfig
@@ -116,6 +116,7 @@ config BOARD_STARLABS_STARBOOK_MTL
 	select MAINBOARD_HAS_TPM2
 	select MEMORY_MAPPED_TPM
 	select PMC_IPC_ACPI_INTERFACE
+	select SKIP_SEND_CONNECT_TOPOLOGY_CMD
 	select SOC_INTEL_COMMON_BLOCK_VTD
 	select SOC_INTEL_METEORLAKE
 	select SOC_INTEL_METEORLAKE_U_H

From 0b120de7c032211b09d9549d2cdb8067513cfdde Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Thu, 1 May 2025 16:38:43 -0500
Subject: [PATCH 0955/3886] Documentation: Update documentation for Topton
 X2F-N100

- Clean up section on flashrom vs flashprog
- Clarify flash regions and command used to flash `bios` region only
- Specify command used for external flashing

Change-Id: Icf464f4532b956731040fed97da0726856524c16
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87507
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
---
 .../mainboard/topton/adl/x2f-n100.md          | 28 +++++++++++--------
 1 file changed, 16 insertions(+), 12 deletions(-)

diff --git a/Documentation/mainboard/topton/adl/x2f-n100.md b/Documentation/mainboard/topton/adl/x2f-n100.md
index c386ad35a1..941c8a7cb0 100644
--- a/Documentation/mainboard/topton/adl/x2f-n100.md
+++ b/Documentation/mainboard/topton/adl/x2f-n100.md
@@ -28,26 +28,26 @@ Doing so **may kill your device**. You have been warned :)
 ### Internally
 
 Vendor of this motherboard hasn't locked any flash regions, resulting
-in [flashprog] having full access to the SPI chip.
-Assuming that user had booted Linux with `iomem=relaxed`, they can:
+in internal programmers such as [flashrom]/[flashprog] having full access
+to the SPI chip. Assuming that user had booted Linux with `iomem=relaxed`,
+they can:
 - Flash coreboot from stock firmware
 - Flash stock firmware from coreboot
 - Update coreboot build to a newer version
 
 	Without opening the case and connecting the SPI flasher.
 
-Please note that for AlderLake-N platform you will need to use
-[flashprog] v1.3.0 or newer.
+Note: some users have reported bricked devices when using [flashrom] to
+flash the board, so the current recommendation is to use [flashprog]
+v1.3.0 or newer.
 
-[flashrom] is broken due to regressions, which results in
-failed flashes, bricking the device.
+Since we only need to flash the `bios` region of the flash chip, there is
+no need to extract the `ifd` or `me` regions from your backup of the stock
+firmware. One can flash the `bios` region only using the following command:
+`flashprog -p internal --ifd -i bios -w ./build/coreboot.rom -N`
 
-[flashprog] is a better maintained fork of [flashrom], which
-works flawlessly.
-
-You can skip extracting `SI_BIOS` and `SI_ME` regions from your ROM
-and flash coreboot to `SI_BIOS` region by issuing the following command:
-`flashprog -p internal --ifd -i SI_BIOS -w ./build/coreboot.rom`
+The `-N` tells [flashprog`] to skip verification on the other regions of the
+flash chip which are not being written.
 
 ### Externally
 
@@ -57,6 +57,10 @@ Please note that SPI voltage on this board is standard 3.3V, despite
 using mobile SoC.
 Vendor populated this board with Winbond W25Q128JV chip in SOIC-8 package.
 
+Flashing coreboot using an external programmer is exactly the same as
+using an internal programmer, other than the `programmer` argument:
+`flashprog -p <programmer> --ifd -i bios -w ./build/coreboot.rom -N`
+
 ## Functionality
 
 ### Tested and working

From b23db384a9a0f2dce5f8754a53840d54f5c665e8 Mon Sep 17 00:00:00 2001
From: Maximilian Brune <maximilian.brune@9elements.com>
Date: Wed, 16 Apr 2025 20:45:20 +0200
Subject: [PATCH 0956/3886] vc/amd/fsp: Update SMBIOS Type 17 PartNumber size

The size is different depending on the SOC in question.

Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: Iecd3d8b41c530c1c71f659facaa5a75659930ea9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87584
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/vendorcode/amd/fsp/cezanne/soc_dmi_info.h   | 1 +
 src/vendorcode/amd/fsp/common/dmi_info.h        | 2 +-
 src/vendorcode/amd/fsp/glinda/soc_dmi_info.h    | 1 +
 src/vendorcode/amd/fsp/mendocino/soc_dmi_info.h | 1 +
 src/vendorcode/amd/fsp/phoenix/soc_dmi_info.h   | 1 +
 src/vendorcode/amd/fsp/picasso/soc_dmi_info.h   | 1 +
 6 files changed, 6 insertions(+), 1 deletion(-)

diff --git a/src/vendorcode/amd/fsp/cezanne/soc_dmi_info.h b/src/vendorcode/amd/fsp/cezanne/soc_dmi_info.h
index bbc67bf5fa..76f165d061 100644
--- a/src/vendorcode/amd/fsp/cezanne/soc_dmi_info.h
+++ b/src/vendorcode/amd/fsp/cezanne/soc_dmi_info.h
@@ -10,6 +10,7 @@
 #define AGESA_STRUCT_SOCKET_COUNT         2   ///< Number of sockets in AGESA FSP DMI T17 table
 #define AGESA_STRUCT_CHANNELS_PER_SOCKET  8   ///< Channels per socket in AGESA FSP DMI T17 table
 #define AGESA_STRUCT_DIMMS_PER_CHANNEL    4   ///< DIMMs per channel in AGESA FSP DMI T17 table
+#define AGESA_STRUCT_PART_NUMBER_SIZE     21
 
 #define SMBIOS_3_2_3_3_SUPPORT            1
 
diff --git a/src/vendorcode/amd/fsp/common/dmi_info.h b/src/vendorcode/amd/fsp/common/dmi_info.h
index 390732df6f..5593d760f5 100644
--- a/src/vendorcode/amd/fsp/common/dmi_info.h
+++ b/src/vendorcode/amd/fsp/common/dmi_info.h
@@ -157,7 +157,7 @@ typedef struct {
   OUT UINT16                    Speed;                  ///< Identifies the speed of the device, in megahertz (MHz).
   OUT UINT64                    ManufacturerIdCode;     ///< Manufacturer ID code.
   OUT CHAR8                     SerialNumber[9];        ///< Serial Number.
-  OUT CHAR8                     PartNumber[21];         ///< Part Number.
+  OUT CHAR8                     PartNumber[AGESA_STRUCT_PART_NUMBER_SIZE]; ///< Part Number.
   OUT UINT8                     Attributes;             ///< Bits 7-4: Reserved, Bits 3-0: rank.
   OUT UINT32                    ExtSize;                ///< Extended Size.
   OUT UINT16                    ConfigSpeed;            ///< Configured memory clock speed
diff --git a/src/vendorcode/amd/fsp/glinda/soc_dmi_info.h b/src/vendorcode/amd/fsp/glinda/soc_dmi_info.h
index 08f5f5cd1b..9ff71b124d 100644
--- a/src/vendorcode/amd/fsp/glinda/soc_dmi_info.h
+++ b/src/vendorcode/amd/fsp/glinda/soc_dmi_info.h
@@ -11,6 +11,7 @@
 #define AGESA_STRUCT_SOCKET_COUNT         2   ///< Number of sockets in AGESA FSP DMI T17 table
 #define AGESA_STRUCT_CHANNELS_PER_SOCKET  8   ///< Channels per socket in AGESA FSP DMI T17 table
 #define AGESA_STRUCT_DIMMS_PER_CHANNEL    4   ///< DIMMs per channel in AGESA FSP DMI T17 table
+#define AGESA_STRUCT_PART_NUMBER_SIZE     31
 
 #define SMBIOS_3_2_3_3_SUPPORT            1
 
diff --git a/src/vendorcode/amd/fsp/mendocino/soc_dmi_info.h b/src/vendorcode/amd/fsp/mendocino/soc_dmi_info.h
index 12f3e8fa57..1c3cb1a0b1 100644
--- a/src/vendorcode/amd/fsp/mendocino/soc_dmi_info.h
+++ b/src/vendorcode/amd/fsp/mendocino/soc_dmi_info.h
@@ -10,6 +10,7 @@
 #define AGESA_STRUCT_SOCKET_COUNT         4   ///< Number of sockets in AGESA FSP DMI T17 table
 #define AGESA_STRUCT_CHANNELS_PER_SOCKET  12  ///< Channels per socket in AGESA FSP DMI T17 table
 #define AGESA_STRUCT_DIMMS_PER_CHANNEL    2   ///< DIMMs per channel in AGESA FSP DMI T17 table
+#define AGESA_STRUCT_PART_NUMBER_SIZE     21
 
 #define SMBIOS_3_2_3_3_SUPPORT            1
 
diff --git a/src/vendorcode/amd/fsp/phoenix/soc_dmi_info.h b/src/vendorcode/amd/fsp/phoenix/soc_dmi_info.h
index 12f3e8fa57..1c3cb1a0b1 100644
--- a/src/vendorcode/amd/fsp/phoenix/soc_dmi_info.h
+++ b/src/vendorcode/amd/fsp/phoenix/soc_dmi_info.h
@@ -10,6 +10,7 @@
 #define AGESA_STRUCT_SOCKET_COUNT         4   ///< Number of sockets in AGESA FSP DMI T17 table
 #define AGESA_STRUCT_CHANNELS_PER_SOCKET  12  ///< Channels per socket in AGESA FSP DMI T17 table
 #define AGESA_STRUCT_DIMMS_PER_CHANNEL    2   ///< DIMMs per channel in AGESA FSP DMI T17 table
+#define AGESA_STRUCT_PART_NUMBER_SIZE     21
 
 #define SMBIOS_3_2_3_3_SUPPORT            1
 
diff --git a/src/vendorcode/amd/fsp/picasso/soc_dmi_info.h b/src/vendorcode/amd/fsp/picasso/soc_dmi_info.h
index 109a01a6e0..94a43f55b0 100644
--- a/src/vendorcode/amd/fsp/picasso/soc_dmi_info.h
+++ b/src/vendorcode/amd/fsp/picasso/soc_dmi_info.h
@@ -10,5 +10,6 @@
 #define AGESA_STRUCT_SOCKET_COUNT         1   ///< Number of sockets in AGESA FSP DMI T17 table
 #define AGESA_STRUCT_CHANNELS_PER_SOCKET  4   ///< Channels per socket in AGESA FSP DMI T17 table
 #define AGESA_STRUCT_DIMMS_PER_CHANNEL    4   ///< DIMMs per channel in AGESA FSP DMI T17 table
+#define AGESA_STRUCT_PART_NUMBER_SIZE     21
 
 #endif /* SOC_DMI_INFO_H */

From 66873a38125902eca5093f7ca602b936cc11e9b8 Mon Sep 17 00:00:00 2001
From: Maximilian Brune <maximilian.brune@9elements.com>
Date: Wed, 16 Apr 2025 20:55:21 +0200
Subject: [PATCH 0957/3886] vc/amd/fsp/glinda: Update SMBIOS Type 17
 information

Update values for glinda SOC.

Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: I02110647db86d7ff23f3ea3640dd531c7954ca42
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87585
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
---
 src/vendorcode/amd/fsp/glinda/soc_dmi_info.h | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/src/vendorcode/amd/fsp/glinda/soc_dmi_info.h b/src/vendorcode/amd/fsp/glinda/soc_dmi_info.h
index 9ff71b124d..3f24fe9b16 100644
--- a/src/vendorcode/amd/fsp/glinda/soc_dmi_info.h
+++ b/src/vendorcode/amd/fsp/glinda/soc_dmi_info.h
@@ -8,9 +8,9 @@
 #ifndef SOC_DMI_INFO_H
 #define SOC_DMI_INFO_H
 
-#define AGESA_STRUCT_SOCKET_COUNT         2   ///< Number of sockets in AGESA FSP DMI T17 table
-#define AGESA_STRUCT_CHANNELS_PER_SOCKET  8   ///< Channels per socket in AGESA FSP DMI T17 table
-#define AGESA_STRUCT_DIMMS_PER_CHANNEL    4   ///< DIMMs per channel in AGESA FSP DMI T17 table
+#define AGESA_STRUCT_SOCKET_COUNT         4   ///< Number of sockets in AGESA FSP DMI T17 table
+#define AGESA_STRUCT_CHANNELS_PER_SOCKET  16   ///< Channels per socket in AGESA FSP DMI T17 table
+#define AGESA_STRUCT_DIMMS_PER_CHANNEL    2   ///< DIMMs per channel in AGESA FSP DMI T17 table
 #define AGESA_STRUCT_PART_NUMBER_SIZE     31
 
 #define SMBIOS_3_2_3_3_SUPPORT            1

From ac2bd7581710d3fc9bb975904c9118c73f5acccd Mon Sep 17 00:00:00 2001
From: Zhongtian Wu <wuzhongtian@huaqin.corp-partner.google.com>
Date: Fri, 9 May 2025 14:41:17 +0800
Subject: [PATCH 0958/3886] spd/lp5: Add SPD for K3KL9L90EM-MGCU

Add K3KL9L90EM-MGCU in the memory_parts.json and re-generate the SPD

Samsung:K3KL9L90EM-MGCU

BUG=b:416632273
TEST=util/spd_tools/bin/spd_gen spd/lp5/memory_parts.json lp5

Change-Id: I693d52714a3d1846dec1f990ba7d9f23ec5f219f
Signed-off-by: Zhongtian Wu <wuzhongtian@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87578
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kun Liu <liukun11@huaqin.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: YH Lin <yueherngl@google.com>
---
 spd/lp5/memory_parts.json                      | 13 ++++++++++++-
 spd/lp5/set-0/parts_spd_manifest.generated.txt |  1 +
 spd/lp5/set-1/parts_spd_manifest.generated.txt |  1 +
 3 files changed, 14 insertions(+), 1 deletion(-)

diff --git a/spd/lp5/memory_parts.json b/spd/lp5/memory_parts.json
index 1c34505056..e13ffec930 100644
--- a/spd/lp5/memory_parts.json
+++ b/spd/lp5/memory_parts.json
@@ -284,7 +284,7 @@
                 "speedMbps": 8533,
                 "lp5x": true
             }
-        }，
+        },
         {
             "name":  "K3KL8L80EM-MGCU",
             "attribs": {
@@ -295,6 +295,17 @@
                 "speedMbps": 8533,
                 "lp5x": true
             }
+        },
+        {
+            "name":  "K3KL9L90EM-MGCU",
+            "attribs": {
+                "densityPerDieGb": 16,
+                "diesPerPackage": 4,
+                "bitWidthPerChannel": 16,
+                "ranksPerChannel": 2,
+                "speedMbps": 8533,
+                "lp5x": true
+            }
         }
     ]
 }
diff --git a/spd/lp5/set-0/parts_spd_manifest.generated.txt b/spd/lp5/set-0/parts_spd_manifest.generated.txt
index f560ba3f1a..f28554c4e9 100644
--- a/spd/lp5/set-0/parts_spd_manifest.generated.txt
+++ b/spd/lp5/set-0/parts_spd_manifest.generated.txt
@@ -29,3 +29,4 @@ K3KL8L80DM-MGCU,spd-11.hex
 MT62F2G32D4DS-020 WT:F,spd-10.hex
 H58G56CK8BX146,spd-11.hex
 K3KL8L80EM-MGCU,spd-11.hex
+K3KL9L90EM-MGCU,spd-10.hex
diff --git a/spd/lp5/set-1/parts_spd_manifest.generated.txt b/spd/lp5/set-1/parts_spd_manifest.generated.txt
index f560ba3f1a..f28554c4e9 100644
--- a/spd/lp5/set-1/parts_spd_manifest.generated.txt
+++ b/spd/lp5/set-1/parts_spd_manifest.generated.txt
@@ -29,3 +29,4 @@ K3KL8L80DM-MGCU,spd-11.hex
 MT62F2G32D4DS-020 WT:F,spd-10.hex
 H58G56CK8BX146,spd-11.hex
 K3KL8L80EM-MGCU,spd-11.hex
+K3KL9L90EM-MGCU,spd-10.hex

From 6c830088da6ed51bd7c634125fca9eb43eef2aa3 Mon Sep 17 00:00:00 2001
From: Zhongtian Wu <wuzhongtian@huaqin.corp-partner.google.com>
Date: Fri, 9 May 2025 14:48:39 +0800
Subject: [PATCH 0959/3886] mb/google/rex/var/screebo: Generate RAM IDs

Generate RAM IDs for K3KL9L90EM-MGCU

BUG=b:416632273
BRANCH=None
TEST=Run part_id_gen tool without any errors

Change-Id: I8b19e768ad81b0ef46bf1f5f6ec83952d784c3f2
Signed-off-by: Zhongtian Wu <wuzhongtian@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87579
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: YH Lin <yueherngl@google.com>
---
 src/mainboard/google/rex/variants/screebo/memory/Makefile.mk     | 1 +
 .../google/rex/variants/screebo/memory/dram_id.generated.txt     | 1 +
 .../google/rex/variants/screebo/memory/mem_parts_used.txt        | 1 +
 3 files changed, 3 insertions(+)

diff --git a/src/mainboard/google/rex/variants/screebo/memory/Makefile.mk b/src/mainboard/google/rex/variants/screebo/memory/Makefile.mk
index d633b43bef..d0dfec1db0 100644
--- a/src/mainboard/google/rex/variants/screebo/memory/Makefile.mk
+++ b/src/mainboard/google/rex/variants/screebo/memory/Makefile.mk
@@ -9,3 +9,4 @@ SPD_SOURCES += spd/lp5/set-0/spd-7.hex      # ID = 1(0b0001)  Parts = MT62F1G32D
 SPD_SOURCES += spd/lp5/set-0/spd-8.hex      # ID = 2(0b0010)  Parts = K3KL9L90CM-MGCT
 SPD_SOURCES += spd/lp5/set-0/spd-9.hex      # ID = 3(0b0011)  Parts = K3KL6L60GM-MGCT
 SPD_SOURCES += spd/lp5/set-0/spd-11.hex      # ID = 4(0b0100)  Parts = K3KL8L80EM-MGCU
+SPD_SOURCES += spd/lp5/set-0/spd-10.hex      # ID = 5(0b0101)  Parts = K3KL9L90EM-MGCU
diff --git a/src/mainboard/google/rex/variants/screebo/memory/dram_id.generated.txt b/src/mainboard/google/rex/variants/screebo/memory/dram_id.generated.txt
index a7e4fe684f..6498a2b97e 100644
--- a/src/mainboard/google/rex/variants/screebo/memory/dram_id.generated.txt
+++ b/src/mainboard/google/rex/variants/screebo/memory/dram_id.generated.txt
@@ -12,3 +12,4 @@ K3KL9L90CM-MGCT                2 (0010)
 K3KL6L60GM-MGCT                3 (0011)
 K3KL8L80CM-MGCT                1 (0001)
 K3KL8L80EM-MGCU                4 (0100)
+K3KL9L90EM-MGCU                5 (0101)
diff --git a/src/mainboard/google/rex/variants/screebo/memory/mem_parts_used.txt b/src/mainboard/google/rex/variants/screebo/memory/mem_parts_used.txt
index 7d8cfba3d1..76e077f98c 100644
--- a/src/mainboard/google/rex/variants/screebo/memory/mem_parts_used.txt
+++ b/src/mainboard/google/rex/variants/screebo/memory/mem_parts_used.txt
@@ -17,3 +17,4 @@ K3KL9L90CM-MGCT
 K3KL6L60GM-MGCT
 K3KL8L80CM-MGCT
 K3KL8L80EM-MGCU
+K3KL9L90EM-MGCU

From f07a1a76f3c4f6d5d089f6f9d12326675200e9e8 Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Thu, 31 Aug 2023 10:11:15 -0500
Subject: [PATCH 0960/3886] mb/google/brya: Enable GNA scoring accelerator

Enable the GNA PCI device, and include the ACPI stub so the OS driver
can attach.

TEST=build/boot Win10 on google/brya (banshee)

Change-Id: Ib97278820d93a8fae52a74f36a5f60d9a9b2b363
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Signed-off-by: CoolStar <coolstarorganization@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77577
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Jayvik Desai <jayvik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/google/brya/dsdt.asl                               | 1 +
 src/mainboard/google/brya/variants/baseboard/brask/devicetree.cb | 1 +
 src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb  | 1 +
 src/mainboard/google/brya/variants/baseboard/hades/devicetree.cb | 1 +
 src/mainboard/google/brya/variants/baseboard/nissa/devicetree.cb | 1 +
 5 files changed, 5 insertions(+)

diff --git a/src/mainboard/google/brya/dsdt.asl b/src/mainboard/google/brya/dsdt.asl
index 4c1574e55f..4f82409565 100644
--- a/src/mainboard/google/brya/dsdt.asl
+++ b/src/mainboard/google/brya/dsdt.asl
@@ -27,6 +27,7 @@ DefinitionBlock(
 			#include <soc/intel/alderlake/acpi/southbridge.asl>
 			#include <soc/intel/alderlake/acpi/tcss.asl>
 			#include <drivers/intel/gma/acpi/default_brightness_levels.asl>
+			#include <soc/intel/common/block/acpi/acpi/gna.asl>
 		}
 	}
 
diff --git a/src/mainboard/google/brya/variants/baseboard/brask/devicetree.cb b/src/mainboard/google/brya/variants/baseboard/brask/devicetree.cb
index 3009f65703..d54c68d866 100644
--- a/src/mainboard/google/brya/variants/baseboard/brask/devicetree.cb
+++ b/src/mainboard/google/brya/variants/baseboard/brask/devicetree.cb
@@ -111,6 +111,7 @@ chip soc/intel/alderlake
 		device ref tbt_pcie_rp0 on end
 		device ref tbt_pcie_rp1 on end
 		device ref tbt_pcie_rp2 on end
+		device ref gna on end
 		device ref tcss_xhci on end
 		device ref tcss_dma0 on end
 		device ref tcss_dma1 on end
diff --git a/src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb b/src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb
index 6160ebf084..71dfb54b46 100644
--- a/src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb
+++ b/src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb
@@ -162,6 +162,7 @@ chip soc/intel/alderlake
 		device ref tbt_pcie_rp0 on end
 		device ref tbt_pcie_rp1 on end
 		device ref tbt_pcie_rp2 on end
+		device ref gna on end
 		device ref tcss_xhci on end
 		device ref tcss_dma0 on end
 		device ref tcss_dma1 on end
diff --git a/src/mainboard/google/brya/variants/baseboard/hades/devicetree.cb b/src/mainboard/google/brya/variants/baseboard/hades/devicetree.cb
index 6bd659dbce..54046b904b 100644
--- a/src/mainboard/google/brya/variants/baseboard/hades/devicetree.cb
+++ b/src/mainboard/google/brya/variants/baseboard/hades/devicetree.cb
@@ -100,6 +100,7 @@ chip soc/intel/alderlake
 			}"
 		end
 		device ref dtt on end
+		device ref gna on end
 		device ref tcss_xhci on end
 		device ref xhci on end
 		device ref shared_sram on end
diff --git a/src/mainboard/google/brya/variants/baseboard/nissa/devicetree.cb b/src/mainboard/google/brya/variants/baseboard/nissa/devicetree.cb
index 65d3518b7b..8b1cebd1a5 100644
--- a/src/mainboard/google/brya/variants/baseboard/nissa/devicetree.cb
+++ b/src/mainboard/google/brya/variants/baseboard/nissa/devicetree.cb
@@ -192,6 +192,7 @@ chip soc/intel/alderlake
 			register "gfx" = "GMA_DEFAULT_PANEL(0)"
 		end
 		device ref dtt on end
+		device ref gna on end
 		device ref tcss_xhci on end
 		device ref xhci on end
 		device ref shared_sram on end

From 8efdbf0c348cff9792dbe45dc68278ea530b35f1 Mon Sep 17 00:00:00 2001
From: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com>
Date: Thu, 8 May 2025 14:49:33 +0900
Subject: [PATCH 0961/3886] mb/google/nissa/var/meliks: Use default
 domain_vr_config[] settings

Meliks' domain_vr_config[] parameters were from pirrha at the
beginning, remove this configuration overrides to use the default
configufation of SoC to avoid potential side effect from it.

BUG=b:409205469
TEST=Built and boot
     The score gap of 3D mark and Geekbench was within 1 percent in
     our internal test

Change-Id: I6a34b6a3c3694b4e7084a515b6f0d2aeaeadbd36
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87572
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
---
 .../brya/variants/meliks/overridetree.cb      | 20 -------------------
 1 file changed, 20 deletions(-)

diff --git a/src/mainboard/google/brya/variants/meliks/overridetree.cb b/src/mainboard/google/brya/variants/meliks/overridetree.cb
index 913ccb8897..c98d31e6d6 100644
--- a/src/mainboard/google/brya/variants/meliks/overridetree.cb
+++ b/src/mainboard/google/brya/variants/meliks/overridetree.cb
@@ -77,26 +77,6 @@ chip soc/intel/alderlake
 		[PchSerialIoIndexI2C5] = PchSerialIoPci,
 	}"
 
-	# VR Settings
-	register "domain_vr_config[VR_DOMAIN_IA]" = "{
-		.vr_config_enable = 1,
-		.tdc_timewindow = 1000,
-		.ac_loadline = 500,
-		.dc_loadline = 500,
-		.psi1threshold = VR_CFG_AMP(20),
-		.psi2threshold = VR_CFG_AMP(5),
-		.psi3threshold = VR_CFG_AMP(1),
-	}"
-
-	register "domain_vr_config[VR_DOMAIN_GT]" = "{
-		.vr_config_enable = 1,
-		.tdc_timewindow = 1000,
-		.psi1threshold = VR_CFG_AMP(13),
-		.psi2threshold = VR_CFG_AMP(5),
-		.psi3threshold = VR_CFG_AMP(1),
-
-	}"
-
 	# Enable the Cnvi BT Audio Offload
 	register "cnvi_bt_audio_offload" = "1"
 

From 4456c125f600ed97348313799e9041eb851abc33 Mon Sep 17 00:00:00 2001
From: Zhigang Qin <zhigang.qin@mediatek.corp-partner.google.com>
Date: Sat, 19 Apr 2025 16:54:12 +0800
Subject: [PATCH 0962/3886] soc/mediatek/common: Move PMIF SPI macros to
 per-SoC's header

Different SoCs may require distinct PMIF SPI settings. This commit moves
the common PMIF SPI macros to SoC-specific headers to enhance code
reusability and maintainability.

BUG=b:379008996
BRANCH=none
TEST=build pass and driver log is normal

Signed-off-by: Zhigang Qin <zhigang.qin@mediatek.corp-partner.google.com>
Change-Id: Ifcdf555df4256d7de08b66c3a630a8eb7afb4a35
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87577
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
---
 src/soc/mediatek/common/include/soc/pmif_spi.h |  8 --------
 src/soc/mediatek/common/pmif_spi.c             |  6 ++----
 src/soc/mediatek/mt8188/include/soc/pmif.h     | 14 ++++++++++++++
 src/soc/mediatek/mt8192/include/soc/pmif.h     | 14 ++++++++++++++
 src/soc/mediatek/mt8195/include/soc/pmif.h     | 14 ++++++++++++++
 5 files changed, 44 insertions(+), 12 deletions(-)

diff --git a/src/soc/mediatek/common/include/soc/pmif_spi.h b/src/soc/mediatek/common/include/soc/pmif_spi.h
index ead1e81705..b704ec1e12 100644
--- a/src/soc/mediatek/common/include/soc/pmif_spi.h
+++ b/src/soc/mediatek/common/include/soc/pmif_spi.h
@@ -57,14 +57,6 @@ enum {
 	PMIC_AUXADC_RQST0     = PMIC_BASE + 0x1108,
 };
 
-#define PMIF_SPI_HW_INF		0x307F
-#define PMIF_SPI_MD		BIT(8)
-#define PMIF_SPI_AP_SECURE	BIT(9)
-#define PMIF_SPI_AP		BIT(10)
-#define PMIF_SPI_STAUPD		BIT(14)
-#define PMIF_SPI_TSX_HW		BIT(19)
-#define PMIF_SPI_DCXO_HW	BIT(20)
-
 #define DEFAULT_SLVID	0
 
 #define PMIF_CMD_STA	BIT(2)
diff --git a/src/soc/mediatek/common/pmif_spi.c b/src/soc/mediatek/common/pmif_spi.c
index ea791cb91d..e6ee1b7e8c 100644
--- a/src/soc/mediatek/common/pmif_spi.c
+++ b/src/soc/mediatek/common/pmif_spi.c
@@ -309,11 +309,9 @@ int pmif_spi_init(struct pmif *arb)
 	write32(&arb->mtk_pmif->timer_ctrl, 0x3);
 
 	/* Enable interfaces and arbitration */
-	write32(&arb->mtk_pmif->inf_en, PMIF_SPI_HW_INF | PMIF_SPI_MD |
-		PMIF_SPI_AP_SECURE | PMIF_SPI_AP);
+	write32(&arb->mtk_pmif->inf_en, PMIF_SPI_INF_EN);
 
-	write32(&arb->mtk_pmif->arb_en, PMIF_SPI_HW_INF | PMIF_SPI_MD | PMIF_SPI_AP_SECURE |
-		PMIF_SPI_AP | PMIF_SPI_STAUPD | PMIF_SPI_TSX_HW | PMIF_SPI_DCXO_HW);
+	write32(&arb->mtk_pmif->arb_en, PMIF_SPI_ARB_EN);
 
 	/* Enable GPS AUXADC HW 0 and 1 */
 	SET32_BITFIELDS(&arb->mtk_pmif->other_inf_en, INTGPSADCINF_EN, 0x3);
diff --git a/src/soc/mediatek/mt8188/include/soc/pmif.h b/src/soc/mediatek/mt8188/include/soc/pmif.h
index c22a77399b..a6cf06bcb6 100644
--- a/src/soc/mediatek/mt8188/include/soc/pmif.h
+++ b/src/soc/mediatek/mt8188/include/soc/pmif.h
@@ -124,6 +124,20 @@ check_member(mtk_pmif_regs, pmic_eint_sta_addr, 0x414);
 check_member(mtk_pmif_regs, irq_event_en_0, 0x420);
 check_member(mtk_pmif_regs, swinf_0_acc, 0x800);
 
+#define PMIF_SPI_HW_INF		0x307F
+#define PMIF_SPI_MD		BIT(8)
+#define PMIF_SPI_AP_SECURE	BIT(9)
+#define PMIF_SPI_AP		BIT(10)
+#define PMIF_SPI_STAUPD		BIT(14)
+#define PMIF_SPI_TSX_HW		BIT(19)
+#define PMIF_SPI_DCXO_HW	BIT(20)
+
+#define PMIF_SPI_INF_EN		(PMIF_SPI_HW_INF | PMIF_SPI_MD | PMIF_SPI_AP_SECURE | \
+				PMIF_SPI_AP)
+#define PMIF_SPI_ARB_EN		(PMIF_SPI_HW_INF | PMIF_SPI_MD | PMIF_SPI_AP_SECURE | \
+				PMIF_SPI_AP | PMIF_SPI_STAUPD | PMIF_SPI_TSX_HW | \
+				PMIF_SPI_DCXO_HW)
+
 #define PMIF_SPMI_AP_CHAN	(PMIF_SPMI_BASE + 0x880)
 #define PMIF_SPI_AP_CHAN	(PMIF_SPI_BASE + 0x880)
 
diff --git a/src/soc/mediatek/mt8192/include/soc/pmif.h b/src/soc/mediatek/mt8192/include/soc/pmif.h
index 30432d935b..d532616d91 100644
--- a/src/soc/mediatek/mt8192/include/soc/pmif.h
+++ b/src/soc/mediatek/mt8192/include/soc/pmif.h
@@ -123,6 +123,20 @@ check_member(mtk_pmif_regs, pmic_eint_sta_addr, 0x40C);
 check_member(mtk_pmif_regs, irq_event_en_0, 0x418);
 check_member(mtk_pmif_regs, swinf_0_acc, 0xC00);
 
+#define PMIF_SPI_HW_INF		0x307F
+#define PMIF_SPI_MD		BIT(8)
+#define PMIF_SPI_AP_SECURE	BIT(9)
+#define PMIF_SPI_AP		BIT(10)
+#define PMIF_SPI_STAUPD		BIT(14)
+#define PMIF_SPI_TSX_HW		BIT(19)
+#define PMIF_SPI_DCXO_HW	BIT(20)
+
+#define PMIF_SPI_INF_EN		(PMIF_SPI_HW_INF | PMIF_SPI_MD | PMIF_SPI_AP_SECURE | \
+				PMIF_SPI_AP)
+#define PMIF_SPI_ARB_EN		(PMIF_SPI_HW_INF | PMIF_SPI_MD | PMIF_SPI_AP_SECURE | \
+				PMIF_SPI_AP | PMIF_SPI_STAUPD | PMIF_SPI_TSX_HW | \
+				PMIF_SPI_DCXO_HW)
+
 #define PMIF_SPMI_AP_CHAN	(PMIF_SPMI_BASE + 0xC80)
 #define PMIF_SPI_AP_CHAN	(PMIF_SPI_BASE + 0xC80)
 
diff --git a/src/soc/mediatek/mt8195/include/soc/pmif.h b/src/soc/mediatek/mt8195/include/soc/pmif.h
index 530b31ea62..1a386dcf52 100644
--- a/src/soc/mediatek/mt8195/include/soc/pmif.h
+++ b/src/soc/mediatek/mt8195/include/soc/pmif.h
@@ -124,6 +124,20 @@ check_member(mtk_pmif_regs, pmic_eint_sta_addr, 0x414);
 check_member(mtk_pmif_regs, irq_event_en_0, 0x420);
 check_member(mtk_pmif_regs, swinf_0_acc, 0x800);
 
+#define PMIF_SPI_HW_INF		0x307F
+#define PMIF_SPI_MD		BIT(8)
+#define PMIF_SPI_AP_SECURE	BIT(9)
+#define PMIF_SPI_AP		BIT(10)
+#define PMIF_SPI_STAUPD		BIT(14)
+#define PMIF_SPI_TSX_HW		BIT(19)
+#define PMIF_SPI_DCXO_HW	BIT(20)
+
+#define PMIF_SPI_INF_EN		(PMIF_SPI_HW_INF | PMIF_SPI_MD | PMIF_SPI_AP_SECURE | \
+				PMIF_SPI_AP)
+#define PMIF_SPI_ARB_EN		(PMIF_SPI_HW_INF | PMIF_SPI_MD | PMIF_SPI_AP_SECURE | \
+				PMIF_SPI_AP | PMIF_SPI_STAUPD | PMIF_SPI_TSX_HW | \
+				PMIF_SPI_DCXO_HW)
+
 #define PMIF_SPMI_AP_CHAN	(PMIF_SPMI_BASE + 0x880)
 #define PMIF_SPI_AP_CHAN	(PMIF_SPI_BASE + 0x880)
 

From 376a5acc24426896a62fcd3406fccf061b54ae9f Mon Sep 17 00:00:00 2001
From: Maximilian Brune <maximilian.brune@9elements.com>
Date: Tue, 8 Apr 2025 14:59:30 +0200
Subject: [PATCH 0963/3886] util/lint: Add lint file for gofmt

Add a linter file to check the formatting of our go files.
For now only intelp2m utiliy is checked.

Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: I9c75fc0bf20a2625ddae43b0472a6586ae78f213
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87211
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
---
 util/lint/lint-stable-031-gofmt | 33 +++++++++++++++++++++++++++++++++
 1 file changed, 33 insertions(+)
 create mode 100755 util/lint/lint-stable-031-gofmt

diff --git a/util/lint/lint-stable-031-gofmt b/util/lint/lint-stable-031-gofmt
new file mode 100755
index 0000000000..f22d39ae34
--- /dev/null
+++ b/util/lint/lint-stable-031-gofmt
@@ -0,0 +1,33 @@
+#!/usr/bin/env sh
+#
+# SPDX-License-Identifier: GPL-2.0-only
+
+# DESCR: Run gofmt on util/intelp2m
+
+LINTDIR="$(
+  cd -- "$(dirname "$0")" > /dev/null 2>&1 || return
+  pwd -P
+)"
+
+# shellcheck source=helper_functions.sh
+. "${LINTDIR}/helper_functions.sh"
+
+# Until we require this by default, we need a list of opted-in directories
+# If the script isn't looking at a git repository, just exit
+if [ "${IN_GIT_TREE}" -eq 0 ]; then
+	exit 0
+fi
+
+files_to_check=$(${GIT} log HEAD~..HEAD --format= --name-only util/intelp2m | grep "\.go$")
+
+# nothing to do
+if [ -z "$files_to_check" ]; then
+	exit 0
+fi
+
+diff_files=$(gofmt -l $files_to_check)
+if [ "$diff_files" != "" ]; then
+	echo "Coding style mismatch. Run \"gofmt -w $files_to_check\" before pushing changes"
+	exit 1
+fi
+exit 0

From 445575525c4b33b813aa08aec960d8cd1279e28a Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Sun, 20 Apr 2025 14:54:59 -0500
Subject: [PATCH 0964/3886] mb/google/beltino: Use CFR setup menu to manage
 options

Enable support for managing system options via CFR, and select it by
default when using edk2 with SMMSTORE.

TEST=build/boot panther w/edk2 payload

Change-Id: Ic5dff1f046de2b477361822772dd1add64d608af
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87561
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
---
 src/mainboard/google/beltino/Kconfig     |  1 +
 src/mainboard/google/beltino/Makefile.mk |  1 +
 src/mainboard/google/beltino/cfr.c       | 33 ++++++++++++++++++++++++
 3 files changed, 35 insertions(+)
 create mode 100644 src/mainboard/google/beltino/cfr.c

diff --git a/src/mainboard/google/beltino/Kconfig b/src/mainboard/google/beltino/Kconfig
index 8bde8e6d1c..2d5c3e9637 100644
--- a/src/mainboard/google/beltino/Kconfig
+++ b/src/mainboard/google/beltino/Kconfig
@@ -3,6 +3,7 @@
 config BOARD_GOOGLE_BASEBOARD_BELTINO
 	def_bool n
 	select BOARD_ROMSIZE_KB_8192
+	select DRIVERS_OPTION_CFR_ENABLED if PAYLOAD_EDK2 && SMMSTORE
 	select HAVE_ACPI_RESUME
 	select HAVE_ACPI_TABLES
 	select HAVE_OPTION_TABLE
diff --git a/src/mainboard/google/beltino/Makefile.mk b/src/mainboard/google/beltino/Makefile.mk
index 77edc30b8e..21a5825f29 100644
--- a/src/mainboard/google/beltino/Makefile.mk
+++ b/src/mainboard/google/beltino/Makefile.mk
@@ -14,6 +14,7 @@ romstage-y += variants/$(VARIANT_DIR)/gpio.c
 bootblock-y += variants/$(VARIANT_DIR)/led.c
 
 ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads
+ramstage-$(CONFIG_DRIVERS_OPTION_CFR) += cfr.c
 
 subdirs-y += variants/$(VARIANT_DIR)
 CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/include
diff --git a/src/mainboard/google/beltino/cfr.c b/src/mainboard/google/beltino/cfr.c
new file mode 100644
index 0000000000..0ff1433e57
--- /dev/null
+++ b/src/mainboard/google/beltino/cfr.c
@@ -0,0 +1,33 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <boot/coreboot_tables.h>
+#include <drivers/option/cfr_frontend.h>
+#include <southbridge/intel/lynxpoint/cfr.h>
+
+static struct sm_obj_form system = {
+	.ui_name = "System",
+	.obj_list = (const struct sm_object *[]) {
+		&me_disable,
+		&nmi,
+		NULL
+	},
+};
+
+static struct sm_obj_form power = {
+	.ui_name = "Power",
+	.obj_list = (const struct sm_object *[]) {
+		&power_on_after_fail,
+		NULL
+	},
+};
+
+static struct sm_obj_form *sm_root[] = {
+	&system,
+	&power,
+	NULL
+};
+
+void mb_cfr_setup_menu(struct lb_cfr *cfr_root)
+{
+	cfr_write_setup_menu(cfr_root, sm_root);
+}

From 6eddde31bb1638660ba6cf1fc86917f45af84fe4 Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Mon, 21 Apr 2025 19:56:21 -0500
Subject: [PATCH 0965/3886] mb/google/beltino: Clean up makefile

Organize according to stage and alphabetize makefile entries.

TEST=build/boot panther

Change-Id: I03dd4a522124eb15e68c720fe44a6ef477667672
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87562
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
---
 src/mainboard/google/beltino/Makefile.mk | 15 +++++++--------
 1 file changed, 7 insertions(+), 8 deletions(-)

diff --git a/src/mainboard/google/beltino/Makefile.mk b/src/mainboard/google/beltino/Makefile.mk
index 21a5825f29..00255b834e 100644
--- a/src/mainboard/google/beltino/Makefile.mk
+++ b/src/mainboard/google/beltino/Makefile.mk
@@ -1,20 +1,19 @@
 ## SPDX-License-Identifier: GPL-2.0-only
 
 bootblock-y += bootblock.c
+bootblock-y += variants/$(VARIANT_DIR)/led.c
 
 romstage-$(CONFIG_CHROMEOS) += chromeos.c
+romstage-y += variants/$(VARIANT_DIR)/gpio.c
+
+ramstage-$(CONFIG_DRIVERS_OPTION_CFR) += cfr.c
 ramstage-$(CONFIG_CHROMEOS) += chromeos.c
-verstage-y += chromeos.c
+ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads
 ramstage-y += lan.c
 
+verstage-y += chromeos.c
+
 smm-y += variants/$(VARIANT_DIR)/led.c
 
-romstage-y += variants/$(VARIANT_DIR)/gpio.c
-
-bootblock-y += variants/$(VARIANT_DIR)/led.c
-
-ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads
-ramstage-$(CONFIG_DRIVERS_OPTION_CFR) += cfr.c
-
 subdirs-y += variants/$(VARIANT_DIR)
 CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/include

From 4112c7791920aadab079865db4ae24790775c204 Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Sun, 20 Apr 2025 17:43:21 -0500
Subject: [PATCH 0966/3886] mb/google/jecht: Use CFR setup menu to manage
 options

Enable support for managing system options via CFR, and select it by
default when using edk2 with SMMSTORE.

TEST=build/boot guado w/edk2 payload

Change-Id: I1d407a702513bcffde6b1578469b6e307e5db662
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87563
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
---
 src/mainboard/google/jecht/Kconfig     |  1 +
 src/mainboard/google/jecht/Makefile.mk |  1 +
 src/mainboard/google/jecht/cfr.c       | 33 ++++++++++++++++++++++++++
 3 files changed, 35 insertions(+)
 create mode 100644 src/mainboard/google/jecht/cfr.c

diff --git a/src/mainboard/google/jecht/Kconfig b/src/mainboard/google/jecht/Kconfig
index eb3b985e5a..9122e8750f 100644
--- a/src/mainboard/google/jecht/Kconfig
+++ b/src/mainboard/google/jecht/Kconfig
@@ -3,6 +3,7 @@
 config BOARD_GOOGLE_BASEBOARD_JECHT
 	def_bool n
 	select BOARD_ROMSIZE_KB_8192
+	select DRIVERS_OPTION_CFR_ENABLED if PAYLOAD_EDK2 && SMMSTORE
 	select HAVE_ACPI_RESUME
 	select HAVE_ACPI_TABLES
 	select HAVE_OPTION_TABLE
diff --git a/src/mainboard/google/jecht/Makefile.mk b/src/mainboard/google/jecht/Makefile.mk
index ed74d75109..43d6b2471d 100644
--- a/src/mainboard/google/jecht/Makefile.mk
+++ b/src/mainboard/google/jecht/Makefile.mk
@@ -16,6 +16,7 @@ bootblock-y += led.c
 bootblock-y += bootblock.c
 
 ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads
+ramstage-$(CONFIG_DRIVERS_OPTION_CFR) += cfr.c
 
 subdirs-y += variants/$(VARIANT_DIR)
 CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/include
diff --git a/src/mainboard/google/jecht/cfr.c b/src/mainboard/google/jecht/cfr.c
new file mode 100644
index 0000000000..9f4d19088e
--- /dev/null
+++ b/src/mainboard/google/jecht/cfr.c
@@ -0,0 +1,33 @@
+
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <boot/coreboot_tables.h>
+#include <drivers/option/cfr_frontend.h>
+#include <soc/cfr.h>
+
+static struct sm_obj_form system = {
+	.ui_name = "System",
+	.obj_list = (const struct sm_object *[]) {
+		&me_disable,
+		NULL
+	},
+};
+
+static struct sm_obj_form power = {
+	.ui_name = "Power",
+	.obj_list = (const struct sm_object *[]) {
+		&power_on_after_fail,
+		NULL
+	},
+};
+
+static struct sm_obj_form *sm_root[] = {
+	&system,
+	&power,
+	NULL
+};
+
+void mb_cfr_setup_menu(struct lb_cfr *cfr_root)
+{
+	cfr_write_setup_menu(cfr_root, sm_root);
+}

From 1d62a1e85759bb9656fa3b667b05da208f1a730f Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Mon, 21 Apr 2025 20:00:22 -0500
Subject: [PATCH 0967/3886] mb/google/jecht: Clean up makefile

Organize according to stage and alphabetize makefile entries.

TEST=build/boot guado

Change-Id: I9ee30ab4ff22eb5919ccf9832e813d2c45dea62d
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87564
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
---
 src/mainboard/google/jecht/Makefile.mk | 26 ++++++++++++--------------
 1 file changed, 12 insertions(+), 14 deletions(-)

diff --git a/src/mainboard/google/jecht/Makefile.mk b/src/mainboard/google/jecht/Makefile.mk
index 43d6b2471d..66ffb86555 100644
--- a/src/mainboard/google/jecht/Makefile.mk
+++ b/src/mainboard/google/jecht/Makefile.mk
@@ -1,24 +1,22 @@
 ## SPDX-License-Identifier: GPL-2.0-only
 
-subdirs-y += spd
+bootblock-y += bootblock.c
+bootblock-y += led.c
+
 romstage-$(CONFIG_CHROMEOS) += chromeos.c
+romstage-y += variants/$(VARIANT_DIR)/gpio.c
+romstage-y += variants/$(VARIANT_DIR)/pei_data.c
+
+ramstage-$(CONFIG_DRIVERS_OPTION_CFR) += cfr.c
 ramstage-$(CONFIG_CHROMEOS) += chromeos.c
-verstage-$(CONFIG_CHROMEOS) += chromeos.c
+ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads
 ramstage-y += lan.c
+ramstage-y += variants/$(VARIANT_DIR)/pei_data.c
+
+verstage-$(CONFIG_CHROMEOS) += chromeos.c
 
 smm-y += led.c
 
-romstage-y += variants/$(VARIANT_DIR)/pei_data.c
-ramstage-y += variants/$(VARIANT_DIR)/pei_data.c
-
-bootblock-y += led.c
-
-bootblock-y += bootblock.c
-
-ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads
-ramstage-$(CONFIG_DRIVERS_OPTION_CFR) += cfr.c
-
+subdirs-y += spd
 subdirs-y += variants/$(VARIANT_DIR)
 CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/include
-
-romstage-y += variants/$(VARIANT_DIR)/gpio.c

From dc19824e56b039a8a152d5ce24b4adc4eab013db Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Mon, 13 Jan 2025 14:07:31 -0600
Subject: [PATCH 0968/3886] mb/google/fizz: Use CFR setup menu to manage
 options

Enable support for managing system options via CFR, and select it by
default when using edk2 with SMMSTORE.

TEST=build/boot fizz w/edk2 payload

Change-Id: I211a91f16622b048d15ebe373106b0f70b429312
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87565
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
---
 src/mainboard/google/fizz/Kconfig     |  1 +
 src/mainboard/google/fizz/Makefile.mk |  1 +
 src/mainboard/google/fizz/cfr.c       | 44 +++++++++++++++++++++++++++
 3 files changed, 46 insertions(+)
 create mode 100644 src/mainboard/google/fizz/cfr.c

diff --git a/src/mainboard/google/fizz/Kconfig b/src/mainboard/google/fizz/Kconfig
index 84a514566e..635170cc4c 100644
--- a/src/mainboard/google/fizz/Kconfig
+++ b/src/mainboard/google/fizz/Kconfig
@@ -4,6 +4,7 @@ config BOARD_GOOGLE_BASEBOARD_FIZZ
 	def_bool n
 	select BOARD_ROMSIZE_KB_16384
 	select DRIVERS_I2C_GENERIC
+	select DRIVERS_OPTION_CFR_ENABLED if PAYLOAD_EDK2 && SMMSTORE
 	select DRIVERS_SPI_ACPI
 	select DRIVERS_USB_ACPI
 	select EC_GOOGLE_CHROMEEC
diff --git a/src/mainboard/google/fizz/Makefile.mk b/src/mainboard/google/fizz/Makefile.mk
index 6c20356bb6..a99eb95ec1 100644
--- a/src/mainboard/google/fizz/Makefile.mk
+++ b/src/mainboard/google/fizz/Makefile.mk
@@ -7,6 +7,7 @@ verstage-$(CONFIG_CHROMEOS) += chromeos.c
 
 romstage-$(CONFIG_CHROMEOS) += chromeos.c
 
+ramstage-$(CONFIG_DRIVERS_OPTION_CFR) += cfr.c
 ramstage-$(CONFIG_CHROMEOS) += chromeos.c
 ramstage-$(CONFIG_EC_GOOGLE_CHROMEEC) += ec.c
 ramstage-y += mainboard.c
diff --git a/src/mainboard/google/fizz/cfr.c b/src/mainboard/google/fizz/cfr.c
new file mode 100644
index 0000000000..c775136d54
--- /dev/null
+++ b/src/mainboard/google/fizz/cfr.c
@@ -0,0 +1,44 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <boot/coreboot_tables.h>
+#include <drivers/option/cfr_frontend.h>
+#include <intelblocks/cfr.h>
+#include <soc/cfr.h>
+
+static struct sm_obj_form system = {
+	.ui_name = "System",
+	.obj_list = (const struct sm_object *[]) {
+		&hyper_threading,
+		&igd_dvmt,
+		&igd_aperture,
+		&legacy_8254_timer,
+		&me_state,
+		&me_state_counter,
+		&pciexp_aspm,
+		&pciexp_clk_pm,
+		&pciexp_l1ss,
+		&pciexp_speed,
+		&s0ix_enable,
+		&vtd,
+		NULL
+	},
+};
+
+static struct sm_obj_form power = {
+	.ui_name = "Power",
+	.obj_list = (const struct sm_object *[]) {
+		&power_on_after_fail,
+		NULL
+	},
+};
+
+static struct sm_obj_form *sm_root[] = {
+	&system,
+	&power,
+	NULL
+};
+
+void mb_cfr_setup_menu(struct lb_cfr *cfr_root)
+{
+	cfr_write_setup_menu(cfr_root, sm_root);
+}

From c8ddae9ebe1934361e5efa29a2e2db49c3c0d560 Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Mon, 21 Apr 2025 10:38:04 -0500
Subject: [PATCH 0969/3886] mb/google/puff: Use CFR setup menu to manage
 options

Enable support for managing system options via CFR, and select it by
default when using edk2 with SMMSTORE.

TEST=build/boot wyvern w/edk2 payload

Change-Id: I6ccf0c9c50babb3134669c977eb27b7b3f567546
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87566
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/google/puff/Kconfig     |  1 +
 src/mainboard/google/puff/Makefile.mk |  1 +
 src/mainboard/google/puff/cfr.c       | 45 +++++++++++++++++++++++++++
 3 files changed, 47 insertions(+)
 create mode 100644 src/mainboard/google/puff/cfr.c

diff --git a/src/mainboard/google/puff/Kconfig b/src/mainboard/google/puff/Kconfig
index d5786a5e62..c35cf6b188 100644
--- a/src/mainboard/google/puff/Kconfig
+++ b/src/mainboard/google/puff/Kconfig
@@ -11,6 +11,7 @@ config BOARD_GOOGLE_BASEBOARD_PUFF
 	select DRIVERS_I2C_HID
 	select DRIVERS_I2C_SX9310
 	select DRIVERS_INTEL_DPTF
+	select DRIVERS_OPTION_CFR_ENABLED if PAYLOAD_EDK2 && SMMSTORE
 	select DRIVERS_SPI_ACPI
 	select DRIVERS_USB_ACPI
 	select EC_GOOGLE_CHROMEEC
diff --git a/src/mainboard/google/puff/Makefile.mk b/src/mainboard/google/puff/Makefile.mk
index b26f1d20e5..bbe2f38e18 100644
--- a/src/mainboard/google/puff/Makefile.mk
+++ b/src/mainboard/google/puff/Makefile.mk
@@ -6,6 +6,7 @@ bootblock-$(CONFIG_CHROMEOS) += chromeos.c
 ramstage-y += ramstage.c
 ramstage-$(CONFIG_CHROMEOS) += chromeos.c
 ramstage-$(CONFIG_EC_GOOGLE_CHROMEEC) += ec.c
+ramstage-$(CONFIG_DRIVERS_OPTION_CFR) += cfr.c
 
 romstage-y += romstage.c
 romstage-$(CONFIG_CHROMEOS) += chromeos.c
diff --git a/src/mainboard/google/puff/cfr.c b/src/mainboard/google/puff/cfr.c
new file mode 100644
index 0000000000..8a60ed7d53
--- /dev/null
+++ b/src/mainboard/google/puff/cfr.c
@@ -0,0 +1,45 @@
+
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <boot/coreboot_tables.h>
+#include <drivers/option/cfr_frontend.h>
+#include <intelblocks/cfr.h>
+#include <soc/cfr.h>
+
+static struct sm_obj_form system = {
+	.ui_name = "System",
+	.obj_list = (const struct sm_object *[]) {
+		&hyper_threading,
+		&igd_dvmt,
+		&igd_aperture,
+		&legacy_8254_timer,
+		&me_state,
+		&me_state_counter,
+		&pciexp_aspm,
+		&pciexp_clk_pm,
+		&pciexp_l1ss,
+		&pciexp_speed,
+		&s0ix_enable,
+		&vtd,
+		NULL
+	},
+};
+
+static struct sm_obj_form power = {
+	.ui_name = "Power",
+	.obj_list = (const struct sm_object *[]) {
+		&power_on_after_fail,
+		NULL
+	},
+};
+
+static struct sm_obj_form *sm_root[] = {
+	&system,
+	&power,
+	NULL
+};
+
+void mb_cfr_setup_menu(struct lb_cfr *cfr_root)
+{
+	cfr_write_setup_menu(cfr_root, sm_root);
+}

From 05eb3e3716bd4123946f9badd84336b39cfa5a32 Mon Sep 17 00:00:00 2001
From: mikelee <mike.lee@lcfc.corp-partner.google.com>
Date: Fri, 9 May 2025 19:38:14 +0800
Subject: [PATCH 0970/3886] mb/google/skywalker: Create variant Yoda

Create the variant Yoda.

BUG=b:416360178
TEST=emerge-skywalker coreboot
BRANCH=None

Change-Id: I26be90010a92c05f68c274898de0cf5676d1147d
Signed-off-by: mikelee <mike.lee@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87583
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
---
 src/mainboard/google/skywalker/Kconfig      | 4 +++-
 src/mainboard/google/skywalker/Kconfig.name | 3 +++
 2 files changed, 6 insertions(+), 1 deletion(-)

diff --git a/src/mainboard/google/skywalker/Kconfig b/src/mainboard/google/skywalker/Kconfig
index fcf37dda14..cf9c69f9b5 100644
--- a/src/mainboard/google/skywalker/Kconfig
+++ b/src/mainboard/google/skywalker/Kconfig
@@ -3,7 +3,8 @@
 # Umbrella option to be selected by variant boards.
 config BOARD_GOOGLE_SKYWALKER_COMMON
 	def_bool BOARD_GOOGLE_OBIWAN || \
-		 BOARD_GOOGLE_SKYWALKER
+		 BOARD_GOOGLE_SKYWALKER || \
+		 BOARD_GOOGLE_YODA
 
 if BOARD_GOOGLE_SKYWALKER_COMMON
 
@@ -29,6 +30,7 @@ config MAINBOARD_PART_NUMBER
 	string
 	default "Obiwan" if BOARD_GOOGLE_OBIWAN
 	default "Skywalker" if BOARD_GOOGLE_SKYWALKER
+	default "Yoda" if BOARD_GOOGLE_YODA
 
 config BOOT_DEVICE_SPI_FLASH_BUS
 	int
diff --git a/src/mainboard/google/skywalker/Kconfig.name b/src/mainboard/google/skywalker/Kconfig.name
index eb0e7c0c9e..1bef303a12 100644
--- a/src/mainboard/google/skywalker/Kconfig.name
+++ b/src/mainboard/google/skywalker/Kconfig.name
@@ -7,3 +7,6 @@ config BOARD_GOOGLE_OBIWAN
 
 config BOARD_GOOGLE_SKYWALKER
 	bool "->  Skywalker"
+
+config BOARD_GOOGLE_YODA
+	bool "-> Yoda"

From b5581d556bf15bf5e064875ea6ba0d61895e0096 Mon Sep 17 00:00:00 2001
From: Ivan Kuzneczov <ivan.kuzneczov@hardenedvault.net>
Date: Mon, 16 Dec 2024 12:44:25 +0000
Subject: [PATCH 0971/3886] drivers/mrc_cache: Measure MRC cache as runtime
 data

MRC cache used to be measured as runtime data when it was resided in
CBFS before commit 82aa8338c74 ("drivers/mrc_cache: Always generate an
FMAP region"). This patch will restore this behavior for MRC cache
stored in FMAP region outside of CBFS.

Now, MRC cache will be measured at the end of
mrc_cache_load_current(), mrc_cache_current_mmap_leak() and
update_mrc_cache_by_type(), to guarantee that a tamper with the memory
(like https://badram.eu/ ) will be detected, controlled by Kconfig
option TPM_MEASURE_MRC_CACHE.

TEST=On Ivy Bridge platforms, Empty MRC cache is not measured.
     Changing DIMM causes both the old cache and new cache being
     measured, thus the runtime data measurement is changed, which
     could be used as an alarm for memory tampering. Starting from the
     second boot after changing DIMM, the runtime data measurement
     becomes stable.

Signed-off-by: Ivan Kuzneczov <ivan.kuzneczov@hardenedvault.net>
Change-Id: I0d82642c24de1b317851d0afd44985195e92c104
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85605
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
---
 src/drivers/mrc_cache/mrc_cache.c | 23 +++++++++++++++++++++++
 src/security/tpm/Kconfig          | 11 +++++++++++
 2 files changed, 34 insertions(+)

diff --git a/src/drivers/mrc_cache/mrc_cache.c b/src/drivers/mrc_cache/mrc_cache.c
index 17f5fee727..a066fa8f3a 100644
--- a/src/drivers/mrc_cache/mrc_cache.c
+++ b/src/drivers/mrc_cache/mrc_cache.c
@@ -9,6 +9,7 @@
 #include <elog.h>
 #include <fmap.h>
 #include <region_file.h>
+#include <security/tpm/tspi.h>
 #include <security/vboot/antirollback.h>
 #include <security/vboot/mrc_cache_hash_tpm.h>
 #include <security/vboot/vboot_common.h>
@@ -248,6 +249,19 @@ static int mrc_data_valid(int type, const struct mrc_metadata *md,
 	return 0;
 }
 
+static tpm_result_t mrc_measure_cache(int type, struct region_device *cache_region)
+{
+	tpm_result_t rc = TPM_SUCCESS;
+	char rname[TPM_CB_LOG_PCR_HASH_NAME];
+	snprintf(rname, sizeof(rname), "MRC: %s cache",
+		 (type == MRC_VARIABLE_DATA) ? "variable" : "training");
+	rc = tpm_measure_region(cache_region, CONFIG_PCR_RUNTIME_DATA, rname);
+	if (rc)
+		printk(BIOS_ERR, "MRC: Couldn't measure %s! rc %#x\n", rname, rc);
+
+	return rc;
+}
+
 static int mrc_cache_get_latest_slot_info(const char *name,
 				const struct region_device *backing_rdev,
 				struct mrc_metadata *md,
@@ -346,6 +360,9 @@ ssize_t mrc_cache_load_current(int type, uint32_t version, void *buffer,
 	if (mrc_data_valid(type, &md, buffer, data_size) < 0)
 		return -1;
 
+	if (CONFIG(TPM_MEASURE_MRC_CACHE))
+		mrc_measure_cache(type, &rdev);
+
 	return data_size;
 }
 
@@ -373,6 +390,9 @@ void *mrc_cache_current_mmap_leak(int type, uint32_t version,
 	if (mrc_data_valid(type, &md, data, region_device_size) < 0)
 		return NULL;
 
+	if (CONFIG(TPM_MEASURE_MRC_CACHE))
+		mrc_measure_cache(type, &rdev);
+
 	return data;
 }
 
@@ -509,6 +529,9 @@ static void update_mrc_cache_by_type(int type,
 		hash_idx = cr->tpm_hash_index;
 		if (hash_idx && CONFIG(MRC_SAVE_HASH_IN_TPM))
 			mrc_cache_update_hash(hash_idx, new_data, new_data_size);
+		if (CONFIG(TPM_MEASURE_MRC_CACHE) &&
+		    !rdev_chain_mem(&read_rdev, new_data, new_data_size))
+			mrc_measure_cache(type, &read_rdev);
 	}
 }
 
diff --git a/src/security/tpm/Kconfig b/src/security/tpm/Kconfig
index 377d6dcb88..c8eb446839 100644
--- a/src/security/tpm/Kconfig
+++ b/src/security/tpm/Kconfig
@@ -78,6 +78,17 @@ config TPM_MEASURED_BOOT
 	help
 	  Enables measured boot (experimental)
 
+config TPM_MEASURE_MRC_CACHE
+	bool "Measure MRC cache"
+	default n
+	depends on TPM_MEASURED_BOOT
+	depends on CACHE_MRC_SETTINGS
+	help
+	  Measures MRC cache as runtime data to guarantee that a
+	  tamper with the memory will be detected. The runtime data
+	  measurement becomes stable after the second boot after
+	  changing DIMM.
+
 choice
 	prompt "TPM event log format"
 	depends on TPM_MEASURED_BOOT

From 511872dae3ea820ad840272af287f419632f48e8 Mon Sep 17 00:00:00 2001
From: Nicholas Chin <nic.c3.14@gmail.com>
Date: Sat, 11 Jan 2025 12:36:22 -0700
Subject: [PATCH 0972/3886] mb/dell: Convert Latitude E7240 into a variant

In preparation for adding additional Haswell based Dell Latitude
laptops, rework the E7240 port to use a variant scheme.

TEST=Timeless build with CONFIG_INCLUDE_CONFIG_FILE=n for the E7240 did
not change between main and this commit

Change-Id: I3031910db6d817824320320f137b0f99cdfe1d9a
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86096
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
---
 src/mainboard/dell/e7240/Makefile.mk          |  5 ----
 .../dell/{e7240 => haswell_latitude}/Kconfig  | 30 +++++++++++++------
 .../{e7240 => haswell_latitude}/Kconfig.name  |  0
 .../dell/haswell_latitude/Makefile.mk         |  7 +++++
 .../{e7240 => haswell_latitude}/acpi/ec.asl   |  0
 .../acpi/platform.asl                         |  0
 .../acpi/superio.asl                          |  0
 .../board_info.txt                            |  0
 .../{e7240 => haswell_latitude}/bootblock.c   |  1 -
 .../devicetree_lp.cb}                         | 17 ++++-------
 .../dell/{e7240 => haswell_latitude}/dsdt.asl |  0
 .../gma-mainboard.ads                         |  0
 .../variants}/e7240/gpio.c                    |  0
 .../variants}/e7240/hda_verb.c                |  0
 .../variants/e7240/overridetree.cb            | 21 +++++++++++++
 .../variants}/e7240/romstage.c                |  0
 16 files changed, 55 insertions(+), 26 deletions(-)
 delete mode 100644 src/mainboard/dell/e7240/Makefile.mk
 rename src/mainboard/dell/{e7240 => haswell_latitude}/Kconfig (51%)
 rename src/mainboard/dell/{e7240 => haswell_latitude}/Kconfig.name (100%)
 create mode 100644 src/mainboard/dell/haswell_latitude/Makefile.mk
 rename src/mainboard/dell/{e7240 => haswell_latitude}/acpi/ec.asl (100%)
 rename src/mainboard/dell/{e7240 => haswell_latitude}/acpi/platform.asl (100%)
 rename src/mainboard/dell/{e7240 => haswell_latitude}/acpi/superio.asl (100%)
 rename src/mainboard/dell/{e7240 => haswell_latitude}/board_info.txt (100%)
 rename src/mainboard/dell/{e7240 => haswell_latitude}/bootblock.c (87%)
 rename src/mainboard/dell/{e7240/devicetree.cb => haswell_latitude/devicetree_lp.cb} (82%)
 rename src/mainboard/dell/{e7240 => haswell_latitude}/dsdt.asl (100%)
 rename src/mainboard/dell/{e7240 => haswell_latitude}/gma-mainboard.ads (100%)
 rename src/mainboard/dell/{ => haswell_latitude/variants}/e7240/gpio.c (100%)
 rename src/mainboard/dell/{ => haswell_latitude/variants}/e7240/hda_verb.c (100%)
 create mode 100644 src/mainboard/dell/haswell_latitude/variants/e7240/overridetree.cb
 rename src/mainboard/dell/{ => haswell_latitude/variants}/e7240/romstage.c (100%)

diff --git a/src/mainboard/dell/e7240/Makefile.mk b/src/mainboard/dell/e7240/Makefile.mk
deleted file mode 100644
index c3dd619421..0000000000
--- a/src/mainboard/dell/e7240/Makefile.mk
+++ /dev/null
@@ -1,5 +0,0 @@
-## SPDX-License-Identifier: GPL-2.0-only
-
-bootblock-y += bootblock.c
-romstage-y += gpio.c
-ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads
diff --git a/src/mainboard/dell/e7240/Kconfig b/src/mainboard/dell/haswell_latitude/Kconfig
similarity index 51%
rename from src/mainboard/dell/e7240/Kconfig
rename to src/mainboard/dell/haswell_latitude/Kconfig
index 4f24cf93ed..c01735d35d 100644
--- a/src/mainboard/dell/e7240/Kconfig
+++ b/src/mainboard/dell/haswell_latitude/Kconfig
@@ -1,26 +1,38 @@
 ## SPDX-License-Identifier: GPL-2.0-only
 
-if BOARD_DELL_LATITUDE_E7240
-
-config BOARD_SPECIFIC_OPTIONS
-	def_bool y
-	select BOARD_ROMSIZE_KB_8192
+config BOARD_DELL_HASWELL_LATITUDE_COMMON
+	def_bool n
 	select EC_DELL_MEC5035
 	select HAVE_ACPI_RESUME
 	select HAVE_ACPI_TABLES
-	select INTEL_LYNXPOINT_LP
 	select MAINBOARD_HAS_LIBGFXINIT
-	select MAINBOARD_USES_IFD_GBE_REGION
 	select NORTHBRIDGE_INTEL_HASWELL
 	select SERIRQ_CONTINUOUS_MODE
 	select SOUTHBRIDGE_INTEL_LYNXPOINT
 	select SYSTEM_TYPE_LAPTOP
 
+config BOARD_DELL_LATITUDE_E7240
+	select BOARD_DELL_HASWELL_LATITUDE_COMMON
+	select BOARD_ROMSIZE_KB_8192
+	select INTEL_LYNXPOINT_LP
+	select MAINBOARD_USES_IFD_GBE_REGION
+
+if BOARD_DELL_HASWELL_LATITUDE_COMMON
+
 config MAINBOARD_DIR
-	default "dell/e7240"
+	default "dell/haswell_latitude"
 
 config MAINBOARD_PART_NUMBER
-	default "Latitude E7240"
+	default "Latitude E7240" if BOARD_DELL_LATITUDE_E7240
+
+config DEVICETREE
+	default "devicetree_lp.cb" if INTEL_LYNXPOINT_LP
+
+config VARIANT_DIR
+	default "e7240" if BOARD_DELL_LATITUDE_E7240
+
+config OVERRIDE_DEVICETREE
+	default "variants/\$(CONFIG_VARIANT_DIR)/overridetree.cb"
 
 config VGA_BIOS_ID
 	default "8086,0a16"
diff --git a/src/mainboard/dell/e7240/Kconfig.name b/src/mainboard/dell/haswell_latitude/Kconfig.name
similarity index 100%
rename from src/mainboard/dell/e7240/Kconfig.name
rename to src/mainboard/dell/haswell_latitude/Kconfig.name
diff --git a/src/mainboard/dell/haswell_latitude/Makefile.mk b/src/mainboard/dell/haswell_latitude/Makefile.mk
new file mode 100644
index 0000000000..38679fffac
--- /dev/null
+++ b/src/mainboard/dell/haswell_latitude/Makefile.mk
@@ -0,0 +1,7 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
+bootblock-y += bootblock.c
+romstage-y += variants/$(VARIANT_DIR)/gpio.c
+romstage-y += variants/$(VARIANT_DIR)/romstage.c
+ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads
+ramstage-y += variants/$(VARIANT_DIR)/hda_verb.c
diff --git a/src/mainboard/dell/e7240/acpi/ec.asl b/src/mainboard/dell/haswell_latitude/acpi/ec.asl
similarity index 100%
rename from src/mainboard/dell/e7240/acpi/ec.asl
rename to src/mainboard/dell/haswell_latitude/acpi/ec.asl
diff --git a/src/mainboard/dell/e7240/acpi/platform.asl b/src/mainboard/dell/haswell_latitude/acpi/platform.asl
similarity index 100%
rename from src/mainboard/dell/e7240/acpi/platform.asl
rename to src/mainboard/dell/haswell_latitude/acpi/platform.asl
diff --git a/src/mainboard/dell/e7240/acpi/superio.asl b/src/mainboard/dell/haswell_latitude/acpi/superio.asl
similarity index 100%
rename from src/mainboard/dell/e7240/acpi/superio.asl
rename to src/mainboard/dell/haswell_latitude/acpi/superio.asl
diff --git a/src/mainboard/dell/e7240/board_info.txt b/src/mainboard/dell/haswell_latitude/board_info.txt
similarity index 100%
rename from src/mainboard/dell/e7240/board_info.txt
rename to src/mainboard/dell/haswell_latitude/board_info.txt
diff --git a/src/mainboard/dell/e7240/bootblock.c b/src/mainboard/dell/haswell_latitude/bootblock.c
similarity index 87%
rename from src/mainboard/dell/e7240/bootblock.c
rename to src/mainboard/dell/haswell_latitude/bootblock.c
index 2f6090a40f..a9223d3372 100644
--- a/src/mainboard/dell/e7240/bootblock.c
+++ b/src/mainboard/dell/haswell_latitude/bootblock.c
@@ -1,6 +1,5 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
-#include <device/pci_ops.h>
 #include <ec/dell/mec5035/mec5035.h>
 #include <southbridge/intel/lynxpoint/pch.h>
 
diff --git a/src/mainboard/dell/e7240/devicetree.cb b/src/mainboard/dell/haswell_latitude/devicetree_lp.cb
similarity index 82%
rename from src/mainboard/dell/e7240/devicetree.cb
rename to src/mainboard/dell/haswell_latitude/devicetree_lp.cb
index 07d7cd1d5b..d9537886c0 100644
--- a/src/mainboard/dell/e7240/devicetree.cb
+++ b/src/mainboard/dell/haswell_latitude/devicetree_lp.cb
@@ -10,7 +10,6 @@ chip northbridge/intel/haswell
 
 	device domain 0x0 on
 		ops haswell_pci_domain_ops
-		subsystemid  0x1028 0x05ca inherit
 
 		device pci 00.0 on end # Host bridge
 		device pci 02.0 on # Internal graphics VGA controller
@@ -30,7 +29,7 @@ chip northbridge/intel/haswell
 		end
 		device pci 03.0 on end # Mini-HD audio
 
-		chip southbridge/intel/lynxpoint # Intel Series 8 Lynx Point PCH
+		chip southbridge/intel/lynxpoint # Intel Series 8 Lynx Point LP PCH
 			register "docking_supported" = "true"
 			register "alt_gp_smi_en" = "0x00002000"
 			register "gpe0_en_1" = "0x00000100"
@@ -53,13 +52,12 @@ chip northbridge/intel/haswell
 			device pci 17.0 off end # SDIO
 			device pci 19.0 on  end # Intel Gigabit Ethernet
 			device pci 1b.0 on  end # High Definition Audio
-			device pci 1c.0 on  end # PCIe Port #1
+			device pci 1c.0 off end # PCIe Port #1
 			device pci 1c.1 off end # PCIe Port #2
 			device pci 1c.2 off end # PCIe Port #3
-			device pci 1c.3 on  end # PCIe Port #4, WLAN
-			device pci 1c.4 on  end # PCIe Port #5, SD/MMC Card Reader
-			# PCIe Port #6 Can be muxed between PCIe and SATA
-			device pci 1c.5 on  end # PCIe Port #6
+			device pci 1c.3 off end # PCIe Port #4
+			device pci 1c.4 off end # PCIe Port #5
+			device pci 1c.5 off end # PCIe Port #6
 			device pci 1d.0 on  end # USB2 EHCI #1
 			device pci 1f.0 on      # LPC bridge
 				register "gen1_dec" = "0x007c0681"
@@ -72,10 +70,7 @@ chip northbridge/intel/haswell
 					device pnp ff.0 on end
                                 end
 			end
-			device pci 1f.2 on # SATA Controller (AHCI)
-				# 0(eSATA on dock), 1(mSATA near the fan), 3(mSATA near WLAN)
-				register "sata_port_map" = "0x0b"
-			end
+			device pci 1f.2 on  end # SATA Controller (AHCI)
 			device pci 1f.3 on  end # SMBus
 			device pci 1f.6 off end # Thermal
 		end
diff --git a/src/mainboard/dell/e7240/dsdt.asl b/src/mainboard/dell/haswell_latitude/dsdt.asl
similarity index 100%
rename from src/mainboard/dell/e7240/dsdt.asl
rename to src/mainboard/dell/haswell_latitude/dsdt.asl
diff --git a/src/mainboard/dell/e7240/gma-mainboard.ads b/src/mainboard/dell/haswell_latitude/gma-mainboard.ads
similarity index 100%
rename from src/mainboard/dell/e7240/gma-mainboard.ads
rename to src/mainboard/dell/haswell_latitude/gma-mainboard.ads
diff --git a/src/mainboard/dell/e7240/gpio.c b/src/mainboard/dell/haswell_latitude/variants/e7240/gpio.c
similarity index 100%
rename from src/mainboard/dell/e7240/gpio.c
rename to src/mainboard/dell/haswell_latitude/variants/e7240/gpio.c
diff --git a/src/mainboard/dell/e7240/hda_verb.c b/src/mainboard/dell/haswell_latitude/variants/e7240/hda_verb.c
similarity index 100%
rename from src/mainboard/dell/e7240/hda_verb.c
rename to src/mainboard/dell/haswell_latitude/variants/e7240/hda_verb.c
diff --git a/src/mainboard/dell/haswell_latitude/variants/e7240/overridetree.cb b/src/mainboard/dell/haswell_latitude/variants/e7240/overridetree.cb
new file mode 100644
index 0000000000..a29e184fde
--- /dev/null
+++ b/src/mainboard/dell/haswell_latitude/variants/e7240/overridetree.cb
@@ -0,0 +1,21 @@
+## SPDX-License-Identifier: GPL-2.0-or-later
+
+chip northbridge/intel/haswell
+	device domain 0 on
+		subsystemid  0x1028 0x05ca inherit
+
+		chip southbridge/intel/lynxpoint # Intel Series 8 Lynx Point PCH
+			device pci 1c.0 on  end # PCIe Port #1
+			device pci 1c.1 off end # PCIe Port #2
+			device pci 1c.2 off end # PCIe Port #3
+			device pci 1c.3 on  end # PCIe Port #4, WLAN
+			device pci 1c.4 on  end # PCIe Port #5, SD/MMC Card Reader
+			# PCIe Port #6 Can be muxed between PCIe and SATA
+			device pci 1c.5 on  end # PCIe Port #6
+			device pci 1f.2 on # SATA Controller (AHCI)
+				# 0(eSATA on dock), 1(mSATA near the fan), 3(mSATA near WLAN)
+				register "sata_port_map" = "0x0b"
+			end
+		end
+	end
+end
diff --git a/src/mainboard/dell/e7240/romstage.c b/src/mainboard/dell/haswell_latitude/variants/e7240/romstage.c
similarity index 100%
rename from src/mainboard/dell/e7240/romstage.c
rename to src/mainboard/dell/haswell_latitude/variants/e7240/romstage.c

From 166f0ea14695399f17d1158e70d93f97b3f57516 Mon Sep 17 00:00:00 2001
From: Martin Roth <gaumless@gmail.com>
Date: Sun, 20 Apr 2025 11:51:08 -0600
Subject: [PATCH 0973/3886] util/abuild: Identify abuild builds with an env
 variable

This environment variable can be used to identify when the build is
running from abuild. This can control things like whether or not the
payloads will pull down a new version from git.
This is important on the builders because the network can't be accessed,
but also it'd be unexpected to change the state of the tree when running
abuild locally.

Change-Id: I03a29aeff655ba7067b505b4e26d5b0f4157c67f
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87366
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
---
 util/abuild/abuild | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/util/abuild/abuild b/util/abuild/abuild
index 58f48f2b05..5e81f2640f 100755
--- a/util/abuild/abuild
+++ b/util/abuild/abuild
@@ -29,6 +29,9 @@ TESTRUN="${TESTRUN_DEFAULT}"
 
 export KCONFIG_OVERWRITECONFIG=1
 
+# Identify this as a coreboot autobuild
+export COREBOOT_ABUILD=1
+
 # path to payload. Should be more generic
 PAYLOAD=/dev/null
 

From 02ca72b2d43ec6d79496f0455b6b815774af3379 Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Thu, 6 Mar 2025 13:52:52 +0000
Subject: [PATCH 0974/3886] soc/intel/meteorlake: Hook up Pch Sleep Assertion
 widths

Hook up devicetree to the assertion width UPDs, in the same way
that Tiger Lake does - specifically, only setting the UPDs if a
non-default value is set via devicetree; otherwise, use the
FSP default value.

Change-Id: Ifd92ef8217055eb7b558bc494a6586b35403c368
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86754
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/soc/intel/meteorlake/chip.h       | 49 +++++++++++++++++++++++++++
 src/soc/intel/meteorlake/fsp_params.c | 19 +++++++++++
 2 files changed, 68 insertions(+)

diff --git a/src/soc/intel/meteorlake/chip.h b/src/soc/intel/meteorlake/chip.h
index fa657733d8..2c93aac69d 100644
--- a/src/soc/intel/meteorlake/chip.h
+++ b/src/soc/intel/meteorlake/chip.h
@@ -457,6 +457,55 @@ struct soc_intel_meteorlake_config {
 	 */
 	bool cpu_replacement_check;
 
+	enum {
+		SLP_S3_ASSERTION_DEFAULT,
+		SLP_S3_ASSERTION_60_US,
+		SLP_S3_ASSERTION_1_MS,
+		SLP_S3_ASSERTION_50_MS,
+		SLP_S3_ASSERTION_2_S,
+	} pch_slp_s3_min_assertion_width;
+
+	enum {
+		SLP_S4_ASSERTION_DEFAULT,
+		SLP_S4_ASSERTION_1S,
+		SLP_S4_ASSERTION_2S,
+		SLP_S4_ASSERTION_3S,
+		SLP_S4_ASSERTION_4S,
+	} pch_slp_s4_min_assertion_width;
+
+	enum {
+		SLP_SUS_ASSERTION_DEFAULT,
+		SLP_SUS_ASSERTION_0_MS,
+		SLP_SUS_ASSERTION_500_MS,
+		SLP_SUS_ASSERTION_1_S,
+		SLP_SUS_ASSERTION_4_S,
+	} pch_slp_sus_min_assertion_width;
+
+	enum {
+		SLP_A_ASSERTION_DEFAULT,
+		SLP_A_ASSERTION_0_MS,
+		SLP_A_ASSERTION_4_S,
+		SLP_A_ASSERTION_98_MS,
+		SLP_A_ASSERTION_2_S,
+	} pch_slp_a_min_assertion_width;
+
+	/*
+	 * PCH PM Reset Power Cycle Duration
+	 * NOTE: Duration programmed in the PchPmPwrCycDur should never be smaller than the
+	 * stretch duration programmed in the following registers:
+	 *  - GEN_PMCON_A.SLP_S3_MIN_ASST_WDTH (PchPmSlpS3MinAssert)
+	 *  - GEN_PMCON_A.S4MAW (PchPmSlpS4MinAssert)
+	 *  - PM_CFG.SLP_A_MIN_ASST_WDTH (PchPmSlpAMinAssert)
+	 *  - PM_CFG.SLP_LAN_MIN_ASST_WDTH
+	 */
+	enum {
+		POWER_CYCLE_DURATION_DEFAULT,
+		POWER_CYCLE_DURATION_1S,
+		POWER_CYCLE_DURATION_2S,
+		POWER_CYCLE_DURATION_3S,
+		POWER_CYCLE_DURATION_4S,
+	} pch_reset_power_cycle_duration;
+
 	/* ISA Serial Base selection. */
 	enum {
 		ISA_SERIAL_BASE_ADDR_3F8,
diff --git a/src/soc/intel/meteorlake/fsp_params.c b/src/soc/intel/meteorlake/fsp_params.c
index 8c3ceb75cc..9adee42f7f 100644
--- a/src/soc/intel/meteorlake/fsp_params.c
+++ b/src/soc/intel/meteorlake/fsp_params.c
@@ -22,6 +22,7 @@
 #include <intelblocks/irq.h>
 #include <intelblocks/lpss.h>
 #include <intelblocks/mp_init.h>
+#include <intelblocks/pmclib.h>
 #include <intelblocks/systemagent.h>
 #include <intelblocks/xdci.h>
 #include <intelpch/lockdown.h>
@@ -658,6 +659,24 @@ static void fill_fsps_misc_power_params(FSP_S_CONFIG *s_cfg,
 	/* Enable the energy efficient turbo mode */
 	s_cfg->EnergyEfficientTurbo = 1;
 	s_cfg->PmcLpmS0ixSubStateEnableMask = get_supported_lpm_mask();
+
+	/* Apply minimum assertion width settings if non-zero */
+	if (config->pch_slp_s3_min_assertion_width)
+		s_cfg->PchPmSlpS3MinAssert = config->pch_slp_s3_min_assertion_width;
+	if (config->pch_slp_s4_min_assertion_width)
+		s_cfg->PchPmSlpS4MinAssert = config->pch_slp_s4_min_assertion_width;
+	if (config->pch_slp_sus_min_assertion_width)
+		s_cfg->PchPmSlpSusMinAssert = config->pch_slp_sus_min_assertion_width;
+	if (config->pch_slp_a_min_assertion_width)
+		s_cfg->PchPmSlpAMinAssert = config->pch_slp_a_min_assertion_width;
+
+	/* Set Power Cycle Duration */
+	if (config->pch_reset_power_cycle_duration)
+		s_cfg->PchPmPwrCycDur = get_pm_pwr_cyc_dur(config->pch_slp_s4_min_assertion_width,
+							   config->pch_slp_s3_min_assertion_width,
+							   config->pch_slp_a_min_assertion_width,
+							   config->pch_reset_power_cycle_duration);
+
 	/* Un-Demotion from Demoted C1 need to be disable when
 	 * C1 auto demotion is disabled */
 	s_cfg->C1StateUnDemotion = !config->disable_c1_state_auto_demotion;

From 074dd4f6f588f55e1723e5b026b4313517f52abe Mon Sep 17 00:00:00 2001
From: Subrata Banik <subratabanik@google.com>
Date: Sat, 10 May 2025 01:45:36 +0530
Subject: [PATCH 0975/3886] mb/google/fatcat: Set logo vertical alignment to
 middle for variants

This commit configures the firmware splash logo's vertical alignment to
be centered (middle) for the Fatcat variants: Felino, Francka, and
Kinmen.

This is achieved by setting the 'logo_valignment' field to
'FW_SPLASH_VALIGNMENT_MIDDLE' within the 'common_soc_config' register.

BUG=b:409718202
TEST=Able to see FW splash screen at the middle of the screen while
booting google/fatcat.

Change-Id: Idf7f06cac89c14f58e5a3bcab5fe61d72171352b
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87617
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jayvik Desai <jayvik@google.com>
---
 src/mainboard/google/fatcat/variants/felino/overridetree.cb  | 1 +
 src/mainboard/google/fatcat/variants/francka/overridetree.cb | 1 +
 src/mainboard/google/fatcat/variants/kinmen/overridetree.cb  | 3 +++
 3 files changed, 5 insertions(+)

diff --git a/src/mainboard/google/fatcat/variants/felino/overridetree.cb b/src/mainboard/google/fatcat/variants/felino/overridetree.cb
index ff7d07a2c2..979583d67f 100644
--- a/src/mainboard/google/fatcat/variants/felino/overridetree.cb
+++ b/src/mainboard/google/fatcat/variants/felino/overridetree.cb
@@ -102,6 +102,7 @@ chip soc/intel/pantherlake
 	#| I2C4              | CLICK PAD                 |
 	#+-------------------+---------------------------+
 	register "common_soc_config" = "{
+		.logo_valignment = FW_SPLASH_VALIGNMENT_MIDDLE,
 		.i2c[1] = {
 			.early_init=1,
 			.speed = I2C_SPEED_FAST,
diff --git a/src/mainboard/google/fatcat/variants/francka/overridetree.cb b/src/mainboard/google/fatcat/variants/francka/overridetree.cb
index 405be4547d..d11ff4ab62 100644
--- a/src/mainboard/google/fatcat/variants/francka/overridetree.cb
+++ b/src/mainboard/google/fatcat/variants/francka/overridetree.cb
@@ -78,6 +78,7 @@ chip soc/intel/pantherlake
 	#| I2C4              | Touchscreen, Touchpad     |
 	#+-------------------+---------------------------+
 	register "common_soc_config" = "{
+		.logo_valignment = FW_SPLASH_VALIGNMENT_MIDDLE,
 		.chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT,
 		.i2c[1] = {
 			.early_init = 1,
diff --git a/src/mainboard/google/fatcat/variants/kinmen/overridetree.cb b/src/mainboard/google/fatcat/variants/kinmen/overridetree.cb
index bfd637ae50..b012da9872 100644
--- a/src/mainboard/google/fatcat/variants/kinmen/overridetree.cb
+++ b/src/mainboard/google/fatcat/variants/kinmen/overridetree.cb
@@ -1,4 +1,7 @@
 chip soc/intel/pantherlake
+	register "common_soc_config" = "{
+		.logo_valignment = FW_SPLASH_VALIGNMENT_MIDDLE,
+	}"
 
 	device domain 0 on
 	end

From aebef786221b1470a5a02e23964fa748b2f90f25 Mon Sep 17 00:00:00 2001
From: Elyes Haouas <ehaouas@noos.fr>
Date: Sat, 24 Aug 2024 08:33:22 +0200
Subject: [PATCH 0976/3886] xcompile: Use Walloc-size GCC option

Warn about allocation function calls with insufficient size for the
target type of the pointer.
commit 6ab188ee6c99 ("Makefile.mk: Use Walloc-size GCC option")
introduced this GCC option, then commit d05fe9fd3ce9 ("Revert
"Makefile.mk:Use Localiser GCC option"") reverted it because older GCC
versions did not support it.
This change re-enables it for GCC version equal or greater than 14.1.0.

Change-Id: If5d36b073bb5b4cccb0cf2b67b43edb3f97f168c
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84074
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
---
 util/xcompile/xcompile | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/util/xcompile/xcompile b/util/xcompile/xcompile
index 3fb0cb7591..6443dd2a90 100755
--- a/util/xcompile/xcompile
+++ b/util/xcompile/xcompile
@@ -208,6 +208,9 @@ detect_special_flags() {
 	testcc "$GCC"      "$CFLAGS_GCC -Wcalloc-transposed-args" &&
 		CFLAGS_GCC="$CFLAGS_GCC -Wcalloc-transposed-args"
 
+	testcc "$GCC"	"$CFLAGS_GCC -Walloc-size" &&
+		CFLAGS_GCC="$CFLAGS_GCC -Walloc-size"
+
 	testcc "$GCC"      "$CFLAGS_GCC -Wno-unused-parameter" &&
 		CFLAGS_GCC="$CFLAGS_GCC -Wno-unused-parameter"
 

From 452e17972707dde39ef550b66d9c1310c00c7539 Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Thu, 1 May 2025 09:31:58 -0500
Subject: [PATCH 0977/3886] mb/starlabs/*/cfr: Use global console CFR object

Now that a global CFR object exists to set the console output level,
use it instead of duplicating the object for each mainboard.

TEST=build lite_adl_sb

Change-Id: Ie39e77e8345381a018e3df80aebe3126616fc556
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87558
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
---
 src/mainboard/starlabs/byte_adl/cfr.c     | 19 +------------------
 src/mainboard/starlabs/lite/cfr.c         | 19 +------------------
 src/mainboard/starlabs/starbook/cfr.c     |  1 +
 src/mainboard/starlabs/starbook/cfr.h     | 18 ------------------
 src/mainboard/starlabs/starfighter/cfr.c  | 19 +------------------
 src/mainboard/starlabs/starlite_adl/cfr.c | 19 +------------------
 6 files changed, 5 insertions(+), 90 deletions(-)

diff --git a/src/mainboard/starlabs/byte_adl/cfr.c b/src/mainboard/starlabs/byte_adl/cfr.c
index e360e3b419..71c2d40941 100644
--- a/src/mainboard/starlabs/byte_adl/cfr.c
+++ b/src/mainboard/starlabs/byte_adl/cfr.c
@@ -2,6 +2,7 @@
 
 #include <boot/coreboot_tables.h>
 #include <commonlib/coreboot_tables.h>
+#include <console/cfr.h>
 #include <drivers/option/cfr_frontend.h>
 #include <inttypes.h>
 #include <intelblocks/pcie_rp.h>
@@ -20,24 +21,6 @@ static const struct sm_object boot_option = SM_DECLARE_ENUM({
 				SM_ENUM_VALUE_END			},
 });
 
-static const struct sm_object debug_level = SM_DECLARE_ENUM({
-	.opt_name	= "debug_level",
-	.ui_name	= "Debug Level",
-	.ui_helptext	= "Set the verbosity of the debug output.",
-	.default_value	= 0,
-	.values		= (const struct sm_enum_value[]) {
-				{ "Emergency",		0		},
-				{ "Alert",		1		},
-				{ "Critical",		2		},
-				{ "Error",		3		},
-				{ "Warning",		4		},
-				{ "Notice",		5		},
-				{ "Info",		6		},
-				{ "Debug",		7		},
-				{ "Spew",		8		},
-				SM_ENUM_VALUE_END			},
-});
-
 static const struct sm_object gna = SM_DECLARE_BOOL({
 	.opt_name	= "gna",
 	.ui_name	= "Gaussian & Neural Accelerator",
diff --git a/src/mainboard/starlabs/lite/cfr.c b/src/mainboard/starlabs/lite/cfr.c
index 251f55c339..c12d31da3d 100644
--- a/src/mainboard/starlabs/lite/cfr.c
+++ b/src/mainboard/starlabs/lite/cfr.c
@@ -2,6 +2,7 @@
 
 #include <boot/coreboot_tables.h>
 #include <commonlib/coreboot_tables.h>
+#include <console/cfr.h>
 #include <drivers/option/cfr_frontend.h>
 #include <ec/starlabs/merlin/cfr.h>
 #include <inttypes.h>
@@ -28,24 +29,6 @@ static const struct sm_object card_reader = SM_DECLARE_BOOL({
 	.default_value	= true,
 });
 
-static const struct sm_object debug_level = SM_DECLARE_ENUM({
-	.opt_name	= "debug_level",
-	.ui_name	= "Debug Level",
-	.ui_helptext	= "Set the verbosity of the debug output.",
-	.default_value	= 0,
-	.values		= (const struct sm_enum_value[]) {
-				{ "Emergency",		0		},
-				{ "Alert",		1		},
-				{ "Critical",		2		},
-				{ "Error",		3		},
-				{ "Warning",		4		},
-				{ "Notice",		5		},
-				{ "Info",		6		},
-				{ "Debug",		7		},
-				{ "Spew",		8		},
-				SM_ENUM_VALUE_END			},
-});
-
 #if CONFIG(EC_STARLABS_FAST_CHARGE)
 static const struct sm_object fast_charge = SM_DECLARE_BOOL({
 	.opt_name	= "fast_charge",
diff --git a/src/mainboard/starlabs/starbook/cfr.c b/src/mainboard/starlabs/starbook/cfr.c
index 5acb1a2d8d..2af7cddc67 100644
--- a/src/mainboard/starlabs/starbook/cfr.c
+++ b/src/mainboard/starlabs/starbook/cfr.c
@@ -2,6 +2,7 @@
 
 #include <boot/coreboot_tables.h>
 #include <commonlib/coreboot_tables.h>
+#include <console/cfr.h>
 #include <drivers/option/cfr_frontend.h>
 #include <ec/starlabs/merlin/cfr.h>
 #include <inttypes.h>
diff --git a/src/mainboard/starlabs/starbook/cfr.h b/src/mainboard/starlabs/starbook/cfr.h
index 6270e7a50f..622356ac00 100644
--- a/src/mainboard/starlabs/starbook/cfr.h
+++ b/src/mainboard/starlabs/starbook/cfr.h
@@ -26,24 +26,6 @@ static const struct sm_object card_reader = SM_DECLARE_BOOL({
 	.default_value	= true,
 });
 
-static const struct sm_object debug_level = SM_DECLARE_ENUM({
-	.opt_name	= "debug_level",
-	.ui_name	= "Debug Level",
-	.ui_helptext	= "Set the verbosity of the debug output.",
-	.default_value	= 0,
-	.values		= (const struct sm_enum_value[]) {
-				{ "Emergency",		0		},
-				{ "Alert",		1		},
-				{ "Critical",		2		},
-				{ "Error",		3		},
-				{ "Warning",		4		},
-				{ "Notice",		5		},
-				{ "Info",		6		},
-				{ "Debug",		7		},
-				{ "Spew",		8		},
-				SM_ENUM_VALUE_END			},
-});
-
 static const struct sm_object fingerprint_reader = SM_DECLARE_BOOL({
 	.opt_name	= "fingerprint_reader",
 	.ui_name	= "Fingerprint Reader",
diff --git a/src/mainboard/starlabs/starfighter/cfr.c b/src/mainboard/starlabs/starfighter/cfr.c
index bbef3a7c26..c988148afc 100644
--- a/src/mainboard/starlabs/starfighter/cfr.c
+++ b/src/mainboard/starlabs/starfighter/cfr.c
@@ -2,6 +2,7 @@
 
 #include <boot/coreboot_tables.h>
 #include <commonlib/coreboot_tables.h>
+#include <console/cfr.h>
 #include <drivers/option/cfr_frontend.h>
 #include <ec/starlabs/merlin/cfr.h>
 #include <inttypes.h>
@@ -21,24 +22,6 @@ static const struct sm_object boot_option = SM_DECLARE_ENUM({
 				SM_ENUM_VALUE_END			},
 });
 
-static const struct sm_object debug_level = SM_DECLARE_ENUM({
-	.opt_name	= "debug_level",
-	.ui_name	= "Debug Level",
-	.ui_helptext	= "Set the verbosity of the debug output.",
-	.default_value	= 0,
-	.values		= (const struct sm_enum_value[]) {
-				{ "Emergency",		0		},
-				{ "Alert",		1		},
-				{ "Critical",		2		},
-				{ "Error",		3		},
-				{ "Warning",		4		},
-				{ "Notice",		5		},
-				{ "Info",		6		},
-				{ "Debug",		7		},
-				{ "Spew",		8		},
-				SM_ENUM_VALUE_END			},
-});
-
 #if CONFIG(SOC_INTEL_TIGERLAKE) || CONFIG(SOC_INTEL_ALDERLAKE) || CONFIG(SOC_INTEL_RAPTORLAKE)
 static const struct sm_object gna = SM_DECLARE_BOOL({
 	.opt_name	= "gna",
diff --git a/src/mainboard/starlabs/starlite_adl/cfr.c b/src/mainboard/starlabs/starlite_adl/cfr.c
index cd58641e1a..53e6a9f134 100644
--- a/src/mainboard/starlabs/starlite_adl/cfr.c
+++ b/src/mainboard/starlabs/starlite_adl/cfr.c
@@ -2,6 +2,7 @@
 
 #include <boot/coreboot_tables.h>
 #include <commonlib/coreboot_tables.h>
+#include <console/cfr.h>
 #include <drivers/option/cfr_frontend.h>
 #include <ec/starlabs/merlin/cfr.h>
 #include <inttypes.h>
@@ -28,24 +29,6 @@ static const struct sm_object boot_option = SM_DECLARE_ENUM({
 				SM_ENUM_VALUE_END			},
 });
 
-static const struct sm_object debug_level = SM_DECLARE_ENUM({
-	.opt_name	= "debug_level",
-	.ui_name	= "Debug Level",
-	.ui_helptext	= "Set the verbosity of the debug output.",
-	.default_value	= 0,
-	.values		= (const struct sm_enum_value[]) {
-				{ "Emergency",		0		},
-				{ "Alert",		1		},
-				{ "Critical",		2		},
-				{ "Error",		3		},
-				{ "Warning",		4		},
-				{ "Notice",		5		},
-				{ "Info",		6		},
-				{ "Debug",		7		},
-				{ "Spew",		8		},
-				SM_ENUM_VALUE_END			},
-});
-
 #if CONFIG(SOC_INTEL_TIGERLAKE) || CONFIG(SOC_INTEL_ALDERLAKE) || CONFIG(SOC_INTEL_RAPTORLAKE)
 static const struct sm_object gna = SM_DECLARE_BOOL({
 	.opt_name	= "gna",

From d4cb553986be17687df7cf3a081153e59d226e3d Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Fri, 2 May 2025 11:43:03 -0500
Subject: [PATCH 0978/3886] mb/starlabs/*/cfr: Remove `boot_option` CFR option

This option isn't hooked up to anything currently, so remove it.

Change-Id: I1777ee1910bb635181a348c55642aca1ff711b02
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87559
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
---
 src/mainboard/starlabs/byte_adl/cfr.c     | 12 ------------
 src/mainboard/starlabs/lite/cfr.c         | 12 ------------
 src/mainboard/starlabs/starbook/cfr.c     |  1 -
 src/mainboard/starlabs/starbook/cfr.h     | 11 -----------
 src/mainboard/starlabs/starfighter/cfr.c  | 12 ------------
 src/mainboard/starlabs/starlite_adl/cfr.c | 12 ------------
 6 files changed, 60 deletions(-)

diff --git a/src/mainboard/starlabs/byte_adl/cfr.c b/src/mainboard/starlabs/byte_adl/cfr.c
index 71c2d40941..08e6e4e0a2 100644
--- a/src/mainboard/starlabs/byte_adl/cfr.c
+++ b/src/mainboard/starlabs/byte_adl/cfr.c
@@ -10,17 +10,6 @@
 #include <types.h>
 #include <variants.h>
 
-static const struct sm_object boot_option = SM_DECLARE_ENUM({
-	.opt_name	= "boot_option",
-	.ui_name	= "Boot Option",
-	.ui_helptext	= "Change the boot device in the event of a failed boot",
-	.default_value	= 0,
-	.values		= (const struct sm_enum_value[]) {
-				{ "Fallback",		0		},
-				{ "Normal",		1		},
-				SM_ENUM_VALUE_END			},
-});
-
 static const struct sm_object gna = SM_DECLARE_BOOL({
 	.opt_name	= "gna",
 	.ui_name	= "Gaussian & Neural Accelerator",
@@ -175,7 +164,6 @@ static struct sm_obj_form pci = {
 static struct sm_obj_form coreboot = {
 	.ui_name = "coreboot",
 	.obj_list = (const struct sm_object *[]) {
-		&boot_option,
 		&debug_level,
 		&reboot_counter,
 		NULL
diff --git a/src/mainboard/starlabs/lite/cfr.c b/src/mainboard/starlabs/lite/cfr.c
index c12d31da3d..b35b29609e 100644
--- a/src/mainboard/starlabs/lite/cfr.c
+++ b/src/mainboard/starlabs/lite/cfr.c
@@ -11,17 +11,6 @@
 #include <types.h>
 #include <variants.h>
 
-static const struct sm_object boot_option = SM_DECLARE_ENUM({
-	.opt_name	= "boot_option",
-	.ui_name	= "Boot Option",
-	.ui_helptext	= "Change the boot device in the event of a failed boot",
-	.default_value	= 0,
-	.values		= (const struct sm_enum_value[]) {
-				{ "Fallback",		0		},
-				{ "Normal",		1		},
-				SM_ENUM_VALUE_END			},
-});
-
 static const struct sm_object card_reader = SM_DECLARE_BOOL({
 	.opt_name	= "card_reader",
 	.ui_name	= "Card Reader",
@@ -154,7 +143,6 @@ static struct sm_obj_form pci = {
 static struct sm_obj_form coreboot = {
 	.ui_name = "coreboot",
 	.obj_list = (const struct sm_object *[]) {
-		&boot_option,
 		&debug_level,
 		&reboot_counter,
 		NULL
diff --git a/src/mainboard/starlabs/starbook/cfr.c b/src/mainboard/starlabs/starbook/cfr.c
index 2af7cddc67..f549a18920 100644
--- a/src/mainboard/starlabs/starbook/cfr.c
+++ b/src/mainboard/starlabs/starbook/cfr.c
@@ -101,7 +101,6 @@ static struct sm_obj_form pci = {
 static struct sm_obj_form coreboot = {
 	.ui_name = "coreboot",
 	.obj_list = (const struct sm_object *[]) {
-		&boot_option,
 		&debug_level,
 		&reboot_counter,
 		NULL
diff --git a/src/mainboard/starlabs/starbook/cfr.h b/src/mainboard/starlabs/starbook/cfr.h
index 622356ac00..cd247b9d83 100644
--- a/src/mainboard/starlabs/starbook/cfr.h
+++ b/src/mainboard/starlabs/starbook/cfr.h
@@ -8,17 +8,6 @@
 #include <intelblocks/pcie_rp.h>
 #include <variants.h>
 
-static const struct sm_object boot_option = SM_DECLARE_ENUM({
-	.opt_name	= "boot_option",
-	.ui_name	= "Boot Option",
-	.ui_helptext	= "Change the boot device in the event of a failed boot",
-	.default_value	= 0,
-	.values		= (const struct sm_enum_value[]) {
-				{ "Fallback",		0		},
-				{ "Normal",		1		},
-				SM_ENUM_VALUE_END			},
-});
-
 static const struct sm_object card_reader = SM_DECLARE_BOOL({
 	.opt_name	= "card_reader",
 	.ui_name	= "Card Reader",
diff --git a/src/mainboard/starlabs/starfighter/cfr.c b/src/mainboard/starlabs/starfighter/cfr.c
index c988148afc..9f2f1dd295 100644
--- a/src/mainboard/starlabs/starfighter/cfr.c
+++ b/src/mainboard/starlabs/starfighter/cfr.c
@@ -11,17 +11,6 @@
 #include <types.h>
 #include <variants.h>
 
-static const struct sm_object boot_option = SM_DECLARE_ENUM({
-	.opt_name	= "boot_option",
-	.ui_name	= "Boot Option",
-	.ui_helptext	= "Change the boot device in the event of a failed boot",
-	.default_value	= 0,
-	.values		= (const struct sm_enum_value[]) {
-				{ "Fallback",		0		},
-				{ "Normal",		1		},
-				SM_ENUM_VALUE_END			},
-});
-
 #if CONFIG(SOC_INTEL_TIGERLAKE) || CONFIG(SOC_INTEL_ALDERLAKE) || CONFIG(SOC_INTEL_RAPTORLAKE)
 static const struct sm_object gna = SM_DECLARE_BOOL({
 	.opt_name	= "gna",
@@ -230,7 +219,6 @@ static struct sm_obj_form pci = {
 static struct sm_obj_form coreboot = {
 	.ui_name = "coreboot",
 	.obj_list = (const struct sm_object *[]) {
-		&boot_option,
 		&debug_level,
 		&reboot_counter,
 		NULL
diff --git a/src/mainboard/starlabs/starlite_adl/cfr.c b/src/mainboard/starlabs/starlite_adl/cfr.c
index 53e6a9f134..8455d3c592 100644
--- a/src/mainboard/starlabs/starlite_adl/cfr.c
+++ b/src/mainboard/starlabs/starlite_adl/cfr.c
@@ -18,17 +18,6 @@ static const struct sm_object accelerometer = SM_DECLARE_BOOL({
 	.default_value	= true,
 });
 
-static const struct sm_object boot_option = SM_DECLARE_ENUM({
-	.opt_name	= "boot_option",
-	.ui_name	= "Boot Option",
-	.ui_helptext	= "Change the boot device in the event of a failed boot",
-	.default_value	= 0,
-	.values		= (const struct sm_enum_value[]) {
-				{ "Fallback",		0		},
-				{ "Normal",		1		},
-				SM_ENUM_VALUE_END			},
-});
-
 #if CONFIG(SOC_INTEL_TIGERLAKE) || CONFIG(SOC_INTEL_ALDERLAKE) || CONFIG(SOC_INTEL_RAPTORLAKE)
 static const struct sm_object gna = SM_DECLARE_BOOL({
 	.opt_name	= "gna",
@@ -255,7 +244,6 @@ static struct sm_obj_form pci = {
 static struct sm_obj_form coreboot = {
 	.ui_name = "coreboot",
 	.obj_list = (const struct sm_object *[]) {
-		&boot_option,
 		&debug_level,
 		&reboot_counter,
 		NULL

From ea32e30a18d82ee6ff339b6303afe9ebbe6c7290 Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Fri, 2 May 2025 13:26:20 -0500
Subject: [PATCH 0979/3886] mb/starlabs/*/cfr: Remove `reboot_counter` CFR
 option

This option isn't hooked up to anything currently, so remove it.

Change-Id: I01cddc6dbffa5a0cf914ef3c529366ee6ceaaf02
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87560
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/starlabs/byte_adl/cfr.c     | 8 --------
 src/mainboard/starlabs/lite/cfr.c         | 8 --------
 src/mainboard/starlabs/starbook/cfr.c     | 1 -
 src/mainboard/starlabs/starbook/cfr.h     | 8 --------
 src/mainboard/starlabs/starfighter/cfr.c  | 8 --------
 src/mainboard/starlabs/starlite_adl/cfr.c | 8 --------
 6 files changed, 41 deletions(-)

diff --git a/src/mainboard/starlabs/byte_adl/cfr.c b/src/mainboard/starlabs/byte_adl/cfr.c
index 08e6e4e0a2..7dfacd6fa3 100644
--- a/src/mainboard/starlabs/byte_adl/cfr.c
+++ b/src/mainboard/starlabs/byte_adl/cfr.c
@@ -94,13 +94,6 @@ static const struct sm_object pciexp_l1ss = SM_DECLARE_ENUM({
 				SM_ENUM_VALUE_END			},
 });
 
-static const struct sm_object reboot_counter = SM_DECLARE_NUMBER({
-	.opt_name	= "reboot_counter",
-	.ui_name	= "Reboot Counter",
-	.flags		= CFR_OPTFLAG_SUPPRESS,
-	.default_value	= 0,
-});
-
 static const struct sm_object vtd = SM_DECLARE_BOOL({
 	.opt_name	= "vtd",
 	.ui_name	= "VT-d",
@@ -165,7 +158,6 @@ static struct sm_obj_form coreboot = {
 	.ui_name = "coreboot",
 	.obj_list = (const struct sm_object *[]) {
 		&debug_level,
-		&reboot_counter,
 		NULL
 	},
 };
diff --git a/src/mainboard/starlabs/lite/cfr.c b/src/mainboard/starlabs/lite/cfr.c
index b35b29609e..8cfedf8224 100644
--- a/src/mainboard/starlabs/lite/cfr.c
+++ b/src/mainboard/starlabs/lite/cfr.c
@@ -53,13 +53,6 @@ static const struct sm_object microphone = SM_DECLARE_BOOL({
 	.default_value	= true,
 });
 
-static const struct sm_object reboot_counter = SM_DECLARE_NUMBER({
-	.opt_name	= "reboot_counter",
-	.ui_name	= "Reboot Counter",
-	.flags		= CFR_OPTFLAG_SUPPRESS,
-	.default_value	= 0,
-});
-
 static const struct sm_object webcam = SM_DECLARE_BOOL({
 	.opt_name	= "webcam",
 	.ui_name	= "Webcam",
@@ -144,7 +137,6 @@ static struct sm_obj_form coreboot = {
 	.ui_name = "coreboot",
 	.obj_list = (const struct sm_object *[]) {
 		&debug_level,
-		&reboot_counter,
 		NULL
 	},
 };
diff --git a/src/mainboard/starlabs/starbook/cfr.c b/src/mainboard/starlabs/starbook/cfr.c
index f549a18920..de8ad2eeb0 100644
--- a/src/mainboard/starlabs/starbook/cfr.c
+++ b/src/mainboard/starlabs/starbook/cfr.c
@@ -102,7 +102,6 @@ static struct sm_obj_form coreboot = {
 	.ui_name = "coreboot",
 	.obj_list = (const struct sm_object *[]) {
 		&debug_level,
-		&reboot_counter,
 		NULL
 	},
 };
diff --git a/src/mainboard/starlabs/starbook/cfr.h b/src/mainboard/starlabs/starbook/cfr.h
index cd247b9d83..fe1a01e93c 100644
--- a/src/mainboard/starlabs/starbook/cfr.h
+++ b/src/mainboard/starlabs/starbook/cfr.h
@@ -128,14 +128,6 @@ static const struct sm_object pciexp_l1ss = SM_DECLARE_ENUM({
 				SM_ENUM_VALUE_END			},
 });
 
-static const struct sm_object reboot_counter = SM_DECLARE_NUMBER({
-	.opt_name	= "reboot_counter",
-	.ui_name	= "Reboot Counter",
-	.flags		= CFR_OPTFLAG_SUPPRESS,
-	.default_value	= 0,
-});
-
-
 static const struct sm_object thunderbolt = SM_DECLARE_BOOL({
 	.opt_name	= "thunderbolt",
 	.ui_name	= "Thunderbolt",
diff --git a/src/mainboard/starlabs/starfighter/cfr.c b/src/mainboard/starlabs/starfighter/cfr.c
index 9f2f1dd295..bb0c34b83f 100644
--- a/src/mainboard/starlabs/starfighter/cfr.c
+++ b/src/mainboard/starlabs/starfighter/cfr.c
@@ -106,13 +106,6 @@ static const struct sm_object pciexp_l1ss = SM_DECLARE_ENUM({
 });
 #endif
 
-static const struct sm_object reboot_counter = SM_DECLARE_NUMBER({
-	.opt_name	= "reboot_counter",
-	.ui_name	= "Reboot Counter",
-	.flags		= CFR_OPTFLAG_SUPPRESS,
-	.default_value	= 0,
-});
-
 #if CONFIG(DRIVERS_INTEL_USB4_RETIMER)
 static const struct sm_object thunderbolt = SM_DECLARE_BOOL({
 	.opt_name	= "thunderbolt",
@@ -220,7 +213,6 @@ static struct sm_obj_form coreboot = {
 	.ui_name = "coreboot",
 	.obj_list = (const struct sm_object *[]) {
 		&debug_level,
-		&reboot_counter,
 		NULL
 	},
 };
diff --git a/src/mainboard/starlabs/starlite_adl/cfr.c b/src/mainboard/starlabs/starlite_adl/cfr.c
index 8455d3c592..e1c86cf17f 100644
--- a/src/mainboard/starlabs/starlite_adl/cfr.c
+++ b/src/mainboard/starlabs/starlite_adl/cfr.c
@@ -126,13 +126,6 @@ static const struct sm_object pciexp_l1ss = SM_DECLARE_ENUM({
 });
 #endif
 
-static const struct sm_object reboot_counter = SM_DECLARE_NUMBER({
-	.opt_name	= "reboot_counter",
-	.ui_name	= "Reboot Counter",
-	.flags		= CFR_OPTFLAG_SUPPRESS,
-	.default_value	= 0,
-});
-
 static const struct sm_object touchscreen = SM_DECLARE_BOOL({
 	.opt_name	= "touchscreen",
 	.ui_name	= "Touchscreen",
@@ -245,7 +238,6 @@ static struct sm_obj_form coreboot = {
 	.ui_name = "coreboot",
 	.obj_list = (const struct sm_object *[]) {
 		&debug_level,
-		&reboot_counter,
 		NULL
 	},
 };

From 49ae935b377809012688d3694b1629bd7ec34c2a Mon Sep 17 00:00:00 2001
From: Martin Roth <gaumless@gmail.com>
Date: Sun, 20 Apr 2025 12:01:10 -0600
Subject: [PATCH 0980/3886] util/abuild: Change [...] to [[...]] for
 consistency

The [[...]] form is generally recommended as it's more robust and
handles edge cases better (e.g., word splitting, pathname expansion).

Change-Id: I74189c25f0e602a4359272033c6725494a0f487f
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87367
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 util/abuild/abuild | 142 ++++++++++++++++++++++-----------------------
 1 file changed, 71 insertions(+), 71 deletions(-)

diff --git a/util/abuild/abuild b/util/abuild/abuild
index 5e81f2640f..36dcbfb373 100755
--- a/util/abuild/abuild
+++ b/util/abuild/abuild
@@ -36,12 +36,12 @@ export COREBOOT_ABUILD=1
 PAYLOAD=/dev/null
 
 # get path to coreboot XGCC if it's not already set
-if [ -z "$XGCCPATH" ]; then
+if [[ -z "$XGCCPATH" ]]; then
 	XGCCPATH="${TOP}/util/crossgcc/xgcc/bin/"
 fi
 
 # Add XGCC to the path.
-if [ -d "$XGCCPATH" ] && [[ ":$PATH:" != *":$XGCCPATH:"* ]]; then
+if [[ -d "$XGCCPATH" ]] && [[ ":$PATH:" != *":$XGCCPATH:"* ]]; then
 	PATH="$XGCCPATH:$PATH"
 fi
 
@@ -73,7 +73,7 @@ TIMELESS=0
 for i in make gmake gnumake nonexistent_make; do
 	$i --version 2>/dev/null |grep "GNU Make" >/dev/null && break
 done
-if [ "$i" = "nonexistent_make" ]; then
+if [[ "$i" = "nonexistent_make" ]]; then
 	echo No GNU Make found.
 	exit 1
 fi
@@ -106,7 +106,7 @@ trap interrupt INT
 function interrupt
 {
 	printf "\n%s: execution interrupted manually.\n" "$0"
-	if [ "$mode" == "junit" ]; then
+	if [[ "$mode" == "junit" ]]; then
 		printf "%s: deleting incomplete xml output file.\n" "$0"
 	fi
 	exit 1
@@ -167,7 +167,7 @@ function mainboard_vendor
 	grep -l "^[[:space:]]*config\>[[:space:]]*\<BOARD_${MAINBOARD}\>" \
 		${ROOT}/src/mainboard/*/*/Kconfig.name | \
 		sed "s:^\(${ROOT}/src/mainboard/.*\)/.*/\(Kconfig.name\)$:\1/\2:" )
-	if [ ! -f "$kconfig_file" ]; then
+	if [[ ! -f "$kconfig_file" ]]; then
 		exit 1
 	fi
 	grep "^[[:space:]]*config\>[[:space:]]*\<VENDOR_" "$kconfig_file" | \
@@ -187,7 +187,7 @@ function normalize_target
 	VARIANT_UC=$(echo "${variant}" | tr '[:lower:]' '[:upper:]' | tr '-' '_')
 
 	targets=$(get_mainboards "$1")
-	if [ -n "$targets" ]; then
+	if [[ -n "$targets" ]]; then
 		# shellcheck disable=SC2086
 		targets="$(grep "${VARIANT_UC}\$" <<< ${targets})"
 		echo "$targets"
@@ -196,7 +196,7 @@ function normalize_target
 
 	targets=$(echo "$1" | tr ',' ' ')
 	for i in $targets; do
-		if [ -n "$(mainboard_directory "$i")" ]; then
+		if [[ -n "$(mainboard_directory "$i")" ]]; then
 			echo "$i"
 		else
 			echo "$i is not a valid target" >&2
@@ -218,7 +218,7 @@ function create_config
 	mkdir -p "${build_dir}"
 	mkdir -p "$TARGET/sharedutils"
 
-	if [ "$quiet" == "false" ]; then echo "  Creating config file for $BUILD_NAME..."; fi
+	if [[ "$quiet" == "false" ]]; then echo "  Creating config file for $BUILD_NAME..."; fi
 	echo "CONFIG_VENDOR_$(mainboard_vendor "${BUILD_NAME}")=y" > "${config_file}"
 	echo "CONFIG_BOARD_${BUILD_NAME}=y" >> "${config_file}"
 	grep "select[\t ]*ARCH" "${ROOT}/src/mainboard/${board_srcdir}/Kconfig" | \
@@ -228,12 +228,12 @@ function create_config
 	update_config "$BUILD_NAME" "$build_dir" "$config_file"
 
 	ret=$?
-	if [ $ret -eq 0 ]; then
-		if [ "$quiet" == "false" ]; then echo "  $BUILD_NAME config created."; fi
+	if [[ $ret -eq 0 ]]; then
+		if [[ "$quiet" == "false" ]]; then echo "  $BUILD_NAME config created."; fi
 		return 0
 	else
 		# Does this ever happen?
-		if [ "$quiet" == "false" ]; then printf "%s config creation FAILED!\nLog excerpt:\n" "$BUILD_NAME"; fi
+		if [[ "$quiet" == "false" ]]; then printf "%s config creation FAILED!\nLog excerpt:\n" "$BUILD_NAME"; fi
 		tail -n $CONTEXT "$build_dir/config.log" 2> /dev/null || tail -$CONTEXT "$build_dir/config.log"
 		return 1
 	fi
@@ -255,24 +255,24 @@ function update_config
 	#   Usage: payload.sh [BOARD]
 	# the script returns an absolute path to the payload binary.
 
-	if [ -f "$payloads/payload.sh" ]; then
+	if [[ -f "$payloads/payload.sh" ]]; then
 		PAYLOAD=$(sh "$payloads/payload.sh" "$BUILD_NAME")
 		local PAYLOAD_OK=$?
-		if [ $PAYLOAD_OK -gt 0 ]; then
+		if [[ $PAYLOAD_OK -gt 0 ]]; then
 			echo "problem with payload"
 			exit 1
 		fi
-		if [ "$quiet" == "false" ]; then printf "Using payload %s\n" "$PAYLOAD"; fi
-	elif [ "$payloads" = "none" ]; then
+		if [[ "$quiet" == "false" ]]; then printf "Using payload %s\n" "$PAYLOAD"; fi
+	elif [[ "$payloads" = "none" ]]; then
 		PAYLOAD=none
 	fi
 
-	if [ "$PAYLOAD" = "none" ]; then
+	if [[ "$PAYLOAD" = "none" ]]; then
 		{
 			echo "CONFIG_PAYLOAD_NONE=y"
 			echo "# CONFIG_PAYLOAD_ELF is not set"
 		} >> "${config_file}"
-	elif [ "$PAYLOAD" != "/dev/null" ]; then
+	elif [[ "$PAYLOAD" != "/dev/null" ]]; then
 		{
 			echo "# CONFIG_PAYLOAD_NONE is not set"
 			echo "CONFIG_PAYLOAD_ELF=y"
@@ -296,13 +296,13 @@ function update_config
 		echo "# CONFIG_TINT_SECONDARY_PAYLOAD is not set"
 	} >> "${config_file}"
 
-	if [ "$quiet" == "false" ]; then echo "    $MAINBOARD ($customizing)"; fi
+	if [[ "$quiet" == "false" ]]; then echo "    $MAINBOARD ($customizing)"; fi
 	# shellcheck disable=SC2059
 	printf "$configoptions" >> "${config_file}"
 
 	$MAKE olddefconfig "$verboseopt" "DOTCONFIG=${config_file}" "obj=${build_dir}" "objutil=$TARGET/sharedutils" &> "${build_dir}/config.log" ; \
 		CONFIG_OK=$?
-	if [ $CONFIG_OK -eq 0 ]; then
+	if [[ $CONFIG_OK -eq 0 ]]; then
 		$MAKE savedefconfig "$verboseopt" DEFCONFIG="${defconfig_file}" DOTCONFIG="${config_file}" obj="${build_dir}" objutil="$TARGET/sharedutils" &>> "${build_dir}/config.log"
 		return $?
 	else
@@ -317,7 +317,7 @@ function create_buildenv
 	local build_dir=$2
 	local config_file=$3
 
-	if [ -z "$config_file" ]; then
+	if [[ -z "$config_file" ]]; then
 		create_config "$BUILD_NAME" "$build_dir"
 	else
 		local new_config_file="${build_dir}/config.build"
@@ -354,7 +354,7 @@ function check_config
 	local CONFIG_FILE="$BUILD_DIR/config.build"
 	local CONFIG_LOG="$BUILD_DIR/config.log"
 
-	if [ -z "$NEGATE" ]; then
+	if [[ -z "$NEGATE" ]]; then
 		if ! grep -q "$TEST_STRING" "$CONFIG_FILE"; then
 			echo "config file: $CONFIG_FILE has incorrect $TEST_TYPE"
 			echo "Error: Expected '$TEST_STRING' in config file." >> "$CONFIG_LOG"
@@ -400,7 +400,7 @@ function ts_delta_string
 	ts_seconds=$(( delta / 1000))
 	delta=$(( delta % 1000 ))
 
-	if [ $ts_minutes -ne 0 ] ; then
+	if [[ $ts_minutes -ne 0 ]] ; then
 		printf "%d min %d sec" $ts_minutes $ts_seconds
 	else
 		printf "%d.%03d seconds" $ts_seconds $delta
@@ -411,7 +411,7 @@ function compile_target
 {
 	local BUILD_NAME=$1
 
-	if [ "$quiet" == "false" ]; then echo "  Compiling $MAINBOARD image$cpuconfig..."; fi
+	if [[ "$quiet" == "false" ]]; then echo "  Compiling $MAINBOARD image$cpuconfig..."; fi
 
 	CURR=$( pwd )
 
@@ -434,7 +434,7 @@ function compile_target
 	duration_str=$(ts_delta_string $ts_0 $ts_2)
 	junit " <testcase classname='${TESTRUN}${testclass/#/.}' name='$BUILD_NAME' time='$duration' >"
 
-	if [ $MAKE_FAILED -eq 0 ]; then
+	if [[ $MAKE_FAILED -eq 0 ]]; then
 		junit "<system-out>"
 		junitfile make.log
 		junit "</system-out>"
@@ -448,7 +448,7 @@ function compile_target
 		printf "failed\n" > compile.status
 		printf "%s build FAILED after %s!\nLog excerpt:\n" "$BUILD_NAME" "${duration_str}"
 		tail -n $CONTEXT make.log 2> /dev/null || tail -$CONTEXT make.log
-		if [ "$clean_work" = "true" ]; then
+		if [[ "$clean_work" = "true" ]]; then
 			echo "$BUILD_NAME" >> "$FAILED_BOARDS"
 		else
 			echo "$BUILD_NAME - Log: ${build_dir}/make.log" >> "$FAILED_BOARDS"
@@ -456,22 +456,22 @@ function compile_target
 		failed=1
 	fi
 	cd "$CURR" || return $?
-	if [ -n "$checksum_file" ]; then
+	if [[ -n "$checksum_file" ]]; then
 		sha256sum "${build_dir}/coreboot.rom" >> "${checksum_file}_platform"
 		sort "${build_dir}/config.h" | grep CONFIG_ > "${build_dir}/config.h.sorted"
 		sha256sum "${build_dir}/config.h.sorted" >> "${checksum_file}_config"
 	fi
 
 	stats_files="${build_dir}/${timestamps}"
-	if [ -f ${build_dir}/ccache.stats ]; then
+	if [[ -f ${build_dir}/ccache.stats ]]; then
 		stats_files="${stats_files} ${build_dir}/ccache.stats"
 	fi
 	flock -F -w 0.1 $TARGET/.statslock tar -rf ${stats_archive} ${stats_files} 2> /dev/null
 
-	if [ "$clean_work" = "true" ]; then
+	if [[ "$clean_work" = "true" ]]; then
 		rm -rf "${build_dir}"
 	fi
-	if [ "$clean_objs" = "true" ]; then
+	if [[ "$clean_objs" = "true" ]]; then
 		find ${build_dir} \! \( -name coreboot.rom -o -name config.h -o -name config.build -o -name make.log \) -type f -exec rm {} +
 		find ${build_dir} -type d -exec rmdir -p {} + 2>/dev/null
 	fi
@@ -489,20 +489,20 @@ function build_config
 
 	board_srcdir=$(mainboard_directory "${MAINBOARD}")
 
-	if [ "$(cat "${build_dir}/compile.status" 2>/dev/null)" = "ok" ] && \
-		[ "$buildall" = "false" ]; then
+	if [[ "$(cat "${build_dir}/compile.status" 2>/dev/null)" = "ok" ]] && \
+		[[ "$buildall" = "false" ]]; then
 		echo "Skipping $BUILD_NAME; (already successful)"
 		return
 	fi
 
 	export HOSTCC='gcc'
 
-	if [ "$chromeos" = true ] && [ "$(grep -c "^[[:space:]]*select[[:space:]]*MAINBOARD_HAS_CHROMEOS\>" "${ROOT}/src/mainboard/${board_srcdir}/Kconfig")" -eq 0 ]; then
+	if [[ "$chromeos" = true ]] && [[ "$(grep -c "^[[:space:]]*select[[:space:]]*MAINBOARD_HAS_CHROMEOS>" "${ROOT}/src/mainboard/${board_srcdir}/Kconfig")" -eq 0 ]]; then
 		echo "${BUILD_NAME} doesn't support ChromeOS, skipping."
 		return
 	fi
 
-	if [ "$quiet" == "false" ]; then echo "Building $BUILD_NAME"; fi
+	if [[ "$quiet" == "false" ]]; then echo "Building $BUILD_NAME"; fi
 	mkdir -p "$TARGET/${BUILD_NAME}" "$TARGET/abuild"
 	ABSPATH="$(cd "$TARGET/abuild" && pwd)"
 	XMLFILE="$ABSPATH/${BUILD_NAME}.xml"
@@ -519,7 +519,7 @@ function build_config
 	check_config "$build_dir" "vendor" "CONFIG_VENDOR_$(mainboard_vendor "${MAINBOARD}")=y"
 	local VENDOR_OK=$?
 
-	if [ "$chromeos" = false ]; then
+	if [[ "$chromeos" = false ]]; then
 		# Skip this rule for configs created from templates that already
 		# come with CHROMEOS enabled.
 		grep -q "^CONFIG_CHROMEOS=y" ${config_file:-/dev/null} || \
@@ -529,31 +529,31 @@ function build_config
 		local FORCE_ENABLED_CROS=0
 	fi
 
-	if [ "$clang" = true ]; then
+	if [[ "$clang" = true ]]; then
 		check_config "$build_dir" "clang" "CONFIG_COMPILER_LLVM_CLANG=y"
-		if [ $? -ne 0 ]; then
+		if [[ $? -ne 0 ]]; then
 			echo "${MAINBOARD} doesn't support clang, skipping."
 			return
 		fi
 	fi
 
-	if [ -n "${skipconfig_set}" ]; then
+	if [[ -n "${skipconfig_set}" ]]; then
 		check_config "${build_dir}" "config value" "CONFIG_${skipconfig_set}=y" negate
-		if [ $? -ne 0 ]; then
+		if [[ $? -ne 0 ]]; then
 			echo "${MAINBOARD} has ${skipconfig_set} set. Skipping at user's request."
 			return
 		fi
 	fi
 
-	if [ -n "${skipconfig_unset}" ]; then
+	if [[ -n "${skipconfig_unset}" ]]; then
 		check_config "${build_dir}" "config value" "CONFIG_${skipconfig_unset}=y"
-		if [ $? -ne 0 ]; then
+		if [[ $? -ne 0 ]]; then
 			echo "${MAINBOARD} does not have ${skipconfig_unset} set. Skipping at user's request."
 			return
 		fi
 	fi
 
-	if [ $BUILDENV_CREATED -ne 0 ] || [ $MAINBOARD_OK -ne 0 ] || [ $VENDOR_OK -ne 0 ] || [ $FORCE_ENABLED_CROS -eq 1 ]; then
+	if [[ $BUILDENV_CREATED -ne 0 ]] || [[ $MAINBOARD_OK -ne 0 ]] || [[ $VENDOR_OK -ne 0 ]] || [[ $FORCE_ENABLED_CROS -eq 1 ]]; then
 		junit " <testcase classname='${TESTRUN}${testclass/#/.}' name='$BUILD_NAME' >"
 
 		junit "<failure type='BuildFailed'>"
@@ -588,20 +588,20 @@ EOF
 		exit 1
 	fi
 
-	if [ -n "$missing_arches" ]; then
+	if [[ -n "$missing_arches" ]]; then
 		printf "skipping %s because we're missing compilers for (%s)\n" "$BUILD_NAME" "$missing_arches"
 		return
 	fi
 
-	if [ $BUILDENV_CREATED -eq 0 ] && [ $configureonly -eq 0 ]; then
+	if [[ $BUILDENV_CREATED -eq 0 ]] && [[ $configureonly -eq 0 ]]; then
 		BUILDPREFIX=
-		if [ "$scanbuild" = "true" ]; then
+		if [[ "$scanbuild" = "true" ]]; then
 			scanbuild_out=$TARGET/${BUILD_NAME}-scanbuild
 			rm -rf "${scanbuild_out}"
 			BUILDPREFIX="scan-build ${SCANBUILD_ARGS} -o ${scanbuild_out}tmp"
 		fi
 		compile_target "${BUILD_NAME}"
-		if [ "$scanbuild" = "true" ]; then
+		if [[ "$scanbuild" = "true" ]]; then
 			mv "${scanbuild_out}"tmp/* "${scanbuild_out}"
 			rmdir "${scanbuild_out}tmp"
 		fi
@@ -630,7 +630,7 @@ function build_target
 	MAINBOARD_LC=$(echo "$MAINBOARD" | tr '[:upper:]' '[:lower:]')
 
 	# look for config files in the config directory that match the boardname
-	if [ -n "$( find "$configdir" -maxdepth 1 -name "config.${MAINBOARD_LC}*" -print -quit )" ]; then
+	if [[ -n "$( find "$configdir" -maxdepth 1 -name "config.${MAINBOARD_LC}*" -print -quit )" ]]; then
 		for config in "$configdir/config.${MAINBOARD_LC}"*; do
 			BUILD_NAME="${config##*/}"
 			BUILD_NAME="${BUILD_NAME##config.}"
@@ -639,7 +639,7 @@ function build_target
 			# If the file in configs/ results in the same build_name as the default config
 			# append a '_' to differentiate. Otherwise the default configuration would
 			# override the results.
-			if [ "${MAINBOARD}" = "${BUILD_NAME}" ]; then
+			if [[ "${MAINBOARD}" = "${BUILD_NAME}" ]]; then
 				BUILD_NAME=${BUILD_NAME}"_"
 			fi
 			echo "Building config $BUILD_NAME"
@@ -659,14 +659,14 @@ function build_target
 
 function remove_target
 {
-	if [ "$remove" != "true" ]; then
+	if [[ "$remove" != "true" ]]; then
 		return
 	fi
 
 	local BUILD_NAME=$1
 
 	# Save the generated coreboot.rom file of each board.
-	if [ -r "$TARGET/${BUILD_NAME}/coreboot.rom" ]; then
+	if [[ -r "$TARGET/${BUILD_NAME}/coreboot.rom" ]]; then
 		cp "$TARGET/${BUILD_NAME}/coreboot.rom" \
 		   "${BUILD_NAME}_coreboot.rom"
 	fi
@@ -768,7 +768,7 @@ cmdline=("$@")
 getoptbrand="$(getopt -V)"
 
 # shellcheck disable=SC2086
-if [ "${getoptbrand:0:6}" == "getopt" ]; then
+if [[ "${getoptbrand:0:6}" == "getopt" ]]; then
 	# Detected GNU getopt that supports long options.
 	args=$(getopt -l version,verbose,quiet,help,all,target:,board-variant:,payloads:,cpus:,silent,junit,config,loglevel:,remove,prefix:,update,scan-build,ccache,blobs,clang,any-toolchain,clean,clean-somewhat,outdir:,chromeos,xmlfile:,kconfig:,dir:,root:,recursive,checksum:,timeless,exitcode,asserts,name:,skip_set:,skip_unset: -o Vvqhat:b:p:c:sJCl:rP:uyBLAzZo:xX:K:d:R:Ien: -- "$@") || exit 1
 	eval set -- $args
@@ -780,7 +780,7 @@ else
 	retval=$?
 fi
 
-if [ $retval != 0 ]; then
+if [[ $retval != 0 ]]; then
 	myhelp
 	exit 1
 fi
@@ -917,11 +917,11 @@ if [[ "${TESTRUN}" != "${TESTRUN_DEFAULT}" ]]; then
 	fi
 fi
 
-if [ -n "$1" ]; then
+if [[ -n "$1" ]]; then
 	printf "Invalid option '%s'\n\n" "$1"; myhelp; exit 1;
 fi
 
-if [ -z "$TARGET" ] || [ "$TARGET" = "/" ]; then
+if [[ -z "$TARGET" || "$TARGET" = "/" ]]; then
 	echo "Please specify a valid, non-root build directory."
 	exit 1
 fi
@@ -937,7 +937,7 @@ if echo "${skipconfig_set}${skipconfig_unset}" | grep -q "CONFIG_" >/dev/null 2>
 fi
 
 customizing=$(echo "$customizing" | cut -c3-)
-if [ -z "$customizing" ]; then
+if [[ -z "$customizing" ]]; then
 	customizing="Default configuration"
 fi
 customizing="Config: ${customizing}"
@@ -949,7 +949,7 @@ stats_archive="$TARGET/statistics.tar"
 # Generate a single xcompile for all boards
 export xcompile="${TARGET}/xcompile"
 
-if [ "$recursive" = "false" ]; then
+if [[ "$recursive" = "false" ]]; then
 	rm -f "${xcompile}"
 	$MAKE -C"${ROOT}" obj="$TARGET/temp" objutil="$TARGET/sharedutils" UPDATED_SUBMODULES=1 "${xcompile}" || exit 1
 	rm -f "$FAILED_BOARDS" "$PASSED_BOARDS"
@@ -959,11 +959,11 @@ if [ "$recursive" = "false" ]; then
 fi
 
 USE_XARGS=0
-if [ "$cpus" != "1" ]; then
+if [[ "$cpus" != "1" ]]; then
 	# Limit to 32 parallel builds for now.
 	# Thrashing all caches because we run
 	# 160 abuilds in parallel is no fun.
-	if [ "$cpus" = "max" ]; then
+	if [[ "$cpus" = "max" ]]; then
 		cpus=32
 	fi
 	# Test if xargs supports the non-standard -P flag
@@ -971,7 +971,7 @@ if [ "$cpus" != "1" ]; then
 	echo | xargs -P ${cpus:-0} -n 1 echo 2>/dev/null >/dev/null && USE_XARGS=1
 fi
 
-if [ "$USE_XARGS" = "0" ]; then
+if [[ "$USE_XARGS" = "0" ]]; then
 test "$MAKEFLAGS" == "" && test "$cpus" != "" && export MAKEFLAGS="-j $cpus"
 export MAKEFLAGS="$MAKEFLAGS UPDATED_SUBMODULES=1" # no need to re-download
 build_targets()
@@ -996,7 +996,7 @@ build_targets()
 	printf "%s" "$configoptions" > "$TMPCFG"
 	$MAKE -j "$cpus" DOTCONFIG="$TMPCFG" obj="$TARGET/temp" objutil="$TARGET/sharedutils" olddefconfig 2>/dev/null
 	BUILDPREFIX=
-	if [ "$scanbuild" = "true" ]; then
+	if [[ "$scanbuild" = "true" ]]; then
 		scanbuild_out=$TARGET/sharedutils-scanbuild
 		rm -rf "${scanbuild_out}"
 		BUILDPREFIX="scan-build -o ${scanbuild_out}tmp"
@@ -1012,7 +1012,7 @@ build_targets()
 	local duration=$(ts_delta_seconds $stime $etime)
 
 	junit " <testcase classname='util' name='all' time='$duration' >"
-	if [ $ret -eq 0 ]; then
+	if [[ $ret -eq 0 ]]; then
 		junit "<system-out>"
 		junitfile "$TARGET/sharedutils/make.log"
 		junit "</system-out>"
@@ -1027,7 +1027,7 @@ build_targets()
 		return
 	fi
 
-	if [ "$scanbuild" = "true" ]; then
+	if [[ "$scanbuild" = "true" ]]; then
 		mv "${scanbuild_out}tmp/"* "${scanbuild_out}"
 		rmdir "${scanbuild_out}tmp"
 	fi
@@ -1041,21 +1041,21 @@ fi
 junit '<?xml version="1.0" encoding="utf-8"?>'
 junit '<testsuite>'
 
-if [ "$target" != "" ]; then
+if [[ "$target" != "" ]]; then
 	# build a single board
 	MAINBOARD=$(normalize_target "${target}")
-	if [ -z "${MAINBOARD}" ]; then
+	if [[ -z "${MAINBOARD}" ]]; then
 		printf "No such target: %s" "${target}"
-		if [ -n "${variant}" ]; then
+		if [[ -n "${variant}" ]]; then
 			printf ", variant: %s" "${variant}"
 		fi
 		printf "\n"
 		exit 1
 	fi
 	build_srcdir="$(mainboard_directory "${MAINBOARD}")"
-	if [ "$(echo "${MAINBOARD}" | wc -w)" -gt 1 ]; then
+	if [[ "$(echo "${MAINBOARD}" | wc -w)" -gt 1 ]]; then
 		build_targets "${MAINBOARD}"
-	elif [ ! -r "$ROOT/src/mainboard/${build_srcdir}" ]; then
+	elif [[ ! -r "$ROOT/src/mainboard/${build_srcdir}" ]]; then
 		echo "No such target: ${MAINBOARD}"
 		exit 1
 	else
@@ -1068,7 +1068,7 @@ else
 	XMLFILE="$REAL_XMLFILE"
 	junit '<?xml version="1.0" encoding="utf-8"?>'
 	junit '<testsuite>'
-	if [ "$mode" != "text" ]; then
+	if [[ "$mode" != "text" ]]; then
 		for xmlfile in $TARGET/abuild/*_*.xml; do
 			cat "$xmlfile" >> "$REAL_XMLFILE"
 		done
@@ -1077,17 +1077,17 @@ else
 fi
 junit '</testsuite>'
 
-if [ "$recursive" = "false" ]; then
+if [[ "$recursive" = "false" ]]; then
 
 	# Print the list of failed configurations
-	if [ -f "$FAILED_BOARDS" ]; then
+	if [[ -f "$FAILED_BOARDS" ]]; then
 		printf "%s configuration(s) failed:\n" "$( wc -l < "$FAILED_BOARDS" )"
 		cat "$FAILED_BOARDS"
 		echo
-		if [ "$exitcode" != "0" ]; then
+		if [[ "$exitcode" != "0" ]]; then
 			failed=1
 		fi
-	elif [ -f "$PASSED_BOARDS" ]; then
+	elif [[ -f "$PASSED_BOARDS" ]]; then
 		printf "All %s tested configurations passed.\n" "$( wc -l < "$PASSED_BOARDS" )"
 	else
 		printf "No boards tested.\n"

From f66c7c1037e9e943f8de7493da6349c2716897f2 Mon Sep 17 00:00:00 2001
From: Martin Roth <gaumless@gmail.com>
Date: Sun, 20 Apr 2025 12:13:43 -0600
Subject: [PATCH 0981/3886] util/abuild: Update echo to printf for consistency.

Abuild used a mix of echo and printf. This updates them all to printf,
which is generally safer, especially when printing variable content
that might contain special characters or start with '-'.

Change-Id: Ib7f35fbaaffe8a85e2b9a1d7c0b8e04ffe0e9901
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87368
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
---
 util/abuild/abuild | 154 +++++++++++++++++++++++----------------------
 1 file changed, 79 insertions(+), 75 deletions(-)

diff --git a/util/abuild/abuild b/util/abuild/abuild
index 36dcbfb373..d126f79253 100755
--- a/util/abuild/abuild
+++ b/util/abuild/abuild
@@ -74,7 +74,7 @@ for i in make gmake gnumake nonexistent_make; do
 	$i --version 2>/dev/null |grep "GNU Make" >/dev/null && break
 done
 if [[ "$i" = "nonexistent_make" ]]; then
-	echo No GNU Make found.
+	printf "No GNU Make found.\n"
 	exit 1
 fi
 MAKE=$i
@@ -114,12 +114,12 @@ function interrupt
 
 function debug
 {
-	test "$verbose" == "true" && echo "$*"
+	[[ "$verbose" == "true" ]] && printf "%s\n" "$*"
 }
 
 function junit
 {
-	test "$mode" == "junit" && echo "$*" >> "$XMLFILE"
+	[[ "$mode" == "junit" ]] && printf "%s\n" "$*" >> "$XMLFILE"
 	return 0
 }
 
@@ -197,9 +197,9 @@ function normalize_target
 	targets=$(echo "$1" | tr ',' ' ')
 	for i in $targets; do
 		if [[ -n "$(mainboard_directory "$i")" ]]; then
-			echo "$i"
+			printf "%s\n" "$i"
 		else
-			echo "$i is not a valid target" >&2
+			printf "%s is not a valid target\n" "$i" >&2
 			exit 1
 		fi
 	done
@@ -218,22 +218,24 @@ function create_config
 	mkdir -p "${build_dir}"
 	mkdir -p "$TARGET/sharedutils"
 
-	if [[ "$quiet" == "false" ]]; then echo "  Creating config file for $BUILD_NAME..."; fi
-	echo "CONFIG_VENDOR_$(mainboard_vendor "${BUILD_NAME}")=y" > "${config_file}"
-	echo "CONFIG_BOARD_${BUILD_NAME}=y" >> "${config_file}"
-	grep "select[\t ]*ARCH" "${ROOT}/src/mainboard/${board_srcdir}/Kconfig" | \
-		sed "s,^.*\(ARCH_.*\)[^A-Z0-9_]*,CONFIG_\1=y," >> "${config_file}"
-	echo "CONFIG_MAINBOARD_DIR=\"${board_srcdir}\"" >> "${config_file}"
+	if [[ "$quiet" == "false" ]]; then printf "  Creating config file for %s...\n" "$BUILD_NAME"; fi
+	{
+		printf "CONFIG_VENDOR_%s=y\n" "$(mainboard_vendor "${BUILD_NAME}")"
+		printf "CONFIG_BOARD_%s=y\n" "${BUILD_NAME}"
+		grep "select[\t ]*ARCH" "${ROOT}/src/mainboard/${board_srcdir}/Kconfig" | \
+			sed "s,^.*\\(ARCH_.*\)[^A-Z0-9_]*,CONFIG_\\1=y,"
+		printf "CONFIG_MAINBOARD_DIR=\\\"%s\\\"\n" "${board_srcdir}"
+	} > "${config_file}"
 
 	update_config "$BUILD_NAME" "$build_dir" "$config_file"
 
 	ret=$?
 	if [[ $ret -eq 0 ]]; then
-		if [[ "$quiet" == "false" ]]; then echo "  $BUILD_NAME config created."; fi
+		if [[ "${quiet}" == "false" ]]; then printf "  %s config created.\n" "$BUILD_NAME"; fi
 		return 0
 	else
 		# Does this ever happen?
-		if [[ "$quiet" == "false" ]]; then printf "%s config creation FAILED!\nLog excerpt:\n" "$BUILD_NAME"; fi
+		if [[ "${quiet}" == "false" ]]; then printf "%s config creation FAILED!\nLog excerpt:\n" "$BUILD_NAME"; fi
 		tail -n $CONTEXT "$build_dir/config.log" 2> /dev/null || tail -$CONTEXT "$build_dir/config.log"
 		return 1
 	fi
@@ -259,7 +261,7 @@ function update_config
 		PAYLOAD=$(sh "$payloads/payload.sh" "$BUILD_NAME")
 		local PAYLOAD_OK=$?
 		if [[ $PAYLOAD_OK -gt 0 ]]; then
-			echo "problem with payload"
+			printf "Problem with payload\n"
 			exit 1
 		fi
 		if [[ "$quiet" == "false" ]]; then printf "Using payload %s\n" "$PAYLOAD"; fi
@@ -269,34 +271,34 @@ function update_config
 
 	if [[ "$PAYLOAD" = "none" ]]; then
 		{
-			echo "CONFIG_PAYLOAD_NONE=y"
-			echo "# CONFIG_PAYLOAD_ELF is not set"
+			printf "CONFIG_PAYLOAD_NONE=y\n"
+			printf "# CONFIG_PAYLOAD_ELF is not set\n"
 		} >> "${config_file}"
 	elif [[ "$PAYLOAD" != "/dev/null" ]]; then
 		{
-			echo "# CONFIG_PAYLOAD_NONE is not set"
-			echo "CONFIG_PAYLOAD_ELF=y"
-			echo "CONFIG_PAYLOAD_FILE=\"$PAYLOAD\""
+			printf "# CONFIG_PAYLOAD_NONE is not set\n"
+			printf "CONFIG_PAYLOAD_ELF=y\n"
+			printf "CONFIG_PAYLOAD_FILE=\"%s\"\n" "$PAYLOAD"
 		} >> "${config_file}"
 	fi
 	# Disable all other payload config options
 	{
-		echo "# CONFIG_PAYLOAD_SEABIOS is not set"
-		echo "# CONFIG_PAYLOAD_FILO is not set"
-		echo "# CONFIG_PAYLOAD_GRUB2 is not set"
-		echo "# CONFIG_PAYLOAD_DEPTHCHARGE is not set"
-		echo "# CONFIG_PAYLOAD_LINUXBOOT is not set"
-		echo "# CONFIG_PAYLOAD_UBOOT is not set"
-		echo "# CONFIG_PAYLOAD_EDK2 is not set"
-		echo "# CONFIG_PXE is not set"
-		echo "# CONFIG_BUILD_IPXE is not set"
-		echo "# CONFIG_MEMTEST_SECONDARY_PAYLOAD is not set"
-		echo "# CONFIG_COREINFO_SECONDARY_PAYLOAD is not set"
-		echo "# CONFIG_NVRAMCUI_SECONDARY_PAYLOAD is not set"
-		echo "# CONFIG_TINT_SECONDARY_PAYLOAD is not set"
+		printf "# CONFIG_PAYLOAD_SEABIOS is not set\n"
+		printf "# CONFIG_PAYLOAD_FILO is not set\n"
+		printf "# CONFIG_PAYLOAD_GRUB2 is not set\n"
+		printf "# CONFIG_PAYLOAD_DEPTHCHARGE is not set\n"
+		printf "# CONFIG_PAYLOAD_LINUXBOOT is not set\n"
+		printf "# CONFIG_PAYLOAD_UBOOT is not set\n"
+		printf "# CONFIG_PAYLOAD_EDK2 is not set\n"
+		printf "# CONFIG_PXE is not set\n"
+		printf "# CONFIG_BUILD_IPXE is not set\n"
+		printf "# CONFIG_MEMTEST_SECONDARY_PAYLOAD is not set\n"
+		printf "# CONFIG_COREINFO_SECONDARY_PAYLOAD is not set\n"
+		printf "# CONFIG_NVRAMCUI_SECONDARY_PAYLOAD is not set\n"
+		printf "# CONFIG_TINT_SECONDARY_PAYLOAD is not set\n"
 	} >> "${config_file}"
 
-	if [[ "$quiet" == "false" ]]; then echo "    $MAINBOARD ($customizing)"; fi
+	if [[ "$quiet" == "false" ]]; then printf "    %s (%s)\n" "$MAINBOARD" "$customizing"; fi
 	# shellcheck disable=SC2059
 	printf "$configoptions" >> "${config_file}"
 
@@ -328,18 +330,18 @@ function create_buildenv
 
 	# Allow simple "make" in the target directory
 	local MAKEFILE=$TARGET/${BUILD_NAME}/Makefile
-	echo "# autogenerated" > "$MAKEFILE"
-	echo "TOP=$ROOT" >> "$MAKEFILE"
-	echo "BUILD=$TARGET" >> "$MAKEFILE"
-	echo "OBJ=\$(BUILD)/${MAINBOARD}" >> "$MAKEFILE"
-	echo "OBJUTIL=\$(BUILD)/sharedutils" >> "$MAKEFILE"
-	echo "all:" >> "$MAKEFILE"
-	echo "	@cp -a config.h config.h.bak" >> "$MAKEFILE"
-	echo "	@cd \$(TOP); \$(MAKE) olddefconfig DOTCONFIG=\$(OBJ)/config.build objutil=\$(OBJUTIL) obj=\$(OBJ)" >> "$MAKEFILE"
-	echo "	@tail -n+6 config.h > config.new; tail -n+6 config.h.bak > config.old" >> "$MAKEFILE"
-	echo "	@cmp -s config.new config.old && cp -a config.h.bak config.h || echo \"Config file changed\"" >> "$MAKEFILE"
-	echo "	@rm config.h.bak config.new config.old" >> "$MAKEFILE"
-	echo "	@cd \$(TOP); \$(MAKE) DOTCONFIG=\$(OBJ)/config.build objutil=\$(OBJUTIL) obj=\$(OBJ)" >> "$MAKEFILE"
+	printf "# autogenerated\n" > "$MAKEFILE"
+	printf "TOP=%s\n" "$ROOT" >> "$MAKEFILE"
+	printf "BUILD=%s\n" "$TARGET" >> "$MAKEFILE"
+	printf "OBJ=\$(BUILD)/%s\n" "${MAINBOARD}" >> "$MAKEFILE"
+	printf "OBJUTIL=\$(BUILD)/sharedutils\n" >> "$MAKEFILE"
+	printf "all:\n" >> "$MAKEFILE"
+	printf "\t@cp -a config.h config.h.bak\n" >> "$MAKEFILE"
+	printf "\t@cd \$(TOP); \$(MAKE) olddefconfig DOTCONFIG=\$(OBJ)/config.build objutil=\$(OBJUTIL) obj=\$(OBJ)\n" >> "$MAKEFILE"
+	printf "\t@tail -n+6 config.h > config.new; tail -n+6 config.h.bak > config.old\n" >> "$MAKEFILE"
+	printf "\t@cmp -s config.new config.old && cp -a config.h.bak config.h || printf \"Config file changed\"\n" >> "$MAKEFILE"
+	printf "\t@rm config.h.bak config.new config.old\n" >> "$MAKEFILE"
+	printf "\t@cd \$(TOP); \$(MAKE) DOTCONFIG=\$(OBJ)/config.build objutil=\$(OBJUTIL) obj=\$(OBJ)\n" >> "$MAKEFILE"
 
 	return $ret
 }
@@ -356,14 +358,14 @@ function check_config
 
 	if [[ -z "$NEGATE" ]]; then
 		if ! grep -q "$TEST_STRING" "$CONFIG_FILE"; then
-			echo "config file: $CONFIG_FILE has incorrect $TEST_TYPE"
-			echo "Error: Expected '$TEST_STRING' in config file." >> "$CONFIG_LOG"
+			printf "config file: %s has incorrect %s\n" "$CONFIG_FILE" "$TEST_TYPE"
+			printf "Error: Expected '%s' in config file.\n" "$TEST_STRING" >> "$CONFIG_LOG"
 			return 1
 		fi
 	else
 		if grep -q "$TEST_STRING" "$CONFIG_FILE"; then
-			echo "config file: $CONFIG_FILE has incorrect $TEST_TYPE"
-			echo "Error: Expected not to see '$TEST_STRING' in config file." >> "$CONFIG_LOG"
+			printf "config file: %s has incorrect %s\n" "$CONFIG_FILE" "$TEST_TYPE"
+			printf "Error: Expected not to see '%s' in config file.\n" "$TEST_STRING" >> "$CONFIG_LOG"
 			return 1
 		fi
 	fi
@@ -411,7 +413,7 @@ function compile_target
 {
 	local BUILD_NAME=$1
 
-	if [[ "$quiet" == "false" ]]; then echo "  Compiling $MAINBOARD image$cpuconfig..."; fi
+	if [[ "${quiet}" == "false" ]]; then printf "  Compiling %s image%s...\n" "$MAINBOARD" "$cpuconfig"; fi
 
 	CURR=$( pwd )
 
@@ -491,18 +493,19 @@ function build_config
 
 	if [[ "$(cat "${build_dir}/compile.status" 2>/dev/null)" = "ok" ]] && \
 		[[ "$buildall" = "false" ]]; then
-		echo "Skipping $BUILD_NAME; (already successful)"
+		printf "Skipping %s; (already successful)\n" "$BUILD_NAME"
 		return
 	fi
 
 	export HOSTCC='gcc'
 
 	if [[ "$chromeos" = true ]] && [[ "$(grep -c "^[[:space:]]*select[[:space:]]*MAINBOARD_HAS_CHROMEOS>" "${ROOT}/src/mainboard/${board_srcdir}/Kconfig")" -eq 0 ]]; then
-		echo "${BUILD_NAME} doesn't support ChromeOS, skipping."
+		printf "%s doesn't support ChromeOS, skipping.\n" "${BUILD_NAME}"
+
 		return
 	fi
 
-	if [[ "$quiet" == "false" ]]; then echo "Building $BUILD_NAME"; fi
+	if [[ "${quiet}" == "false" ]]; then printf "Building %s\n" "$BUILD_NAME"; fi
 	mkdir -p "$TARGET/${BUILD_NAME}" "$TARGET/abuild"
 	ABSPATH="$(cd "$TARGET/abuild" && pwd)"
 	XMLFILE="$ABSPATH/${BUILD_NAME}.xml"
@@ -532,7 +535,7 @@ function build_config
 	if [[ "$clang" = true ]]; then
 		check_config "$build_dir" "clang" "CONFIG_COMPILER_LLVM_CLANG=y"
 		if [[ $? -ne 0 ]]; then
-			echo "${MAINBOARD} doesn't support clang, skipping."
+			printf "%s doesn't support clang, skipping.\n" "${MAINBOARD}"
 			return
 		fi
 	fi
@@ -540,7 +543,7 @@ function build_config
 	if [[ -n "${skipconfig_set}" ]]; then
 		check_config "${build_dir}" "config value" "CONFIG_${skipconfig_set}=y" negate
 		if [[ $? -ne 0 ]]; then
-			echo "${MAINBOARD} has ${skipconfig_set} set. Skipping at user's request."
+			printf "%s has %s set. Skipping at user's request.\n" "${MAINBOARD}" "${skipconfig_set}"
 			return
 		fi
 	fi
@@ -548,7 +551,7 @@ function build_config
 	if [[ -n "${skipconfig_unset}" ]]; then
 		check_config "${build_dir}" "config value" "CONFIG_${skipconfig_unset}=y"
 		if [[ $? -ne 0 ]]; then
-			echo "${MAINBOARD} does not have ${skipconfig_unset} set. Skipping at user's request."
+			printf "%s does not have %s set. Skipping at user's request.\n" "${MAINBOARD}" "${skipconfig_unset}"
 			return
 		fi
 	fi
@@ -560,11 +563,11 @@ function build_config
 		junitfile "$build_dir/config.log"
 		junit "</failure>"
 		printf "failed\n" > compile.status
-		printf "%s build configuration FAILED!\nLog excerpt:\n" "$BUILD_NAME"
+		printf "%s build configuration FAILED!\\nLog excerpt:\n" "$BUILD_NAME"
 		tail -n $CONTEXT "$build_dir/config.log" 2> /dev/null || tail -$CONTEXT "$build_dir/config.log"
 
 		junit "</testcase>"
-		echo "$BUILD_NAME - Log: $build_dir/config.log" >> "$FAILED_BOARDS"
+		printf "%s - Log: %s/config.log\n" "$BUILD_NAME" "$build_dir" >> "$FAILED_BOARDS"
 		return
 	fi
 
@@ -579,12 +582,12 @@ include $(xcompile)
 .PHONY: missing_arches
 missing_arches:
 	$(if $(XCOMPILE_COMPLETE),,$(error $(xcompile) is invalid.))
-	@echo $(foreach arch,$(REQUIRED_ARCHES),$(if $(filter $(arch),$(SUBARCH_SUPPORTED)),,$(arch)))
+	@printf "%s\n" "$(foreach arch,$(REQUIRED_ARCHES),$(if $(filter $(arch),$(SUBARCH_SUPPORTED)),,$(arch)))"
 EOF
 )"
 	# shellcheck disable=SC2181
 	if [[ $? -ne 0 ]]; then
-		echo "Calculating missing_arches failed" >&2
+		printf "Calculating missing_arches failed\n" >&2
 		exit 1
 	fi
 
@@ -614,11 +617,12 @@ function record_mainboard
 {
 	local log=$1
 
+		printf "%s/abuild/%s.xml written to %s\n" "$TARGET" "${log}" "$REAL_XMLFILE" >&2
 	if test "$mode" != "text" && test -f "$TARGET/abuild/${log}.xml"; then
 		cat "$TARGET/abuild/${log}.xml" >> "$REAL_XMLFILE"
-		echo "$TARGET/abuild/${log}.xml written to $REAL_XMLFILE" >&2
+		printf "%s/abuild/%s.xml written to %s\\n" "$TARGET" "${log}" "$REAL_XMLFILE" >&2
 	else
-		echo "Warning: $TARGET/abuild/${log}.xml not found." >&2
+		printf "Warning: %s/abuild/%s.xml not found.\n" "$TARGET" "${log}" >&2
 	fi
 }
 
@@ -635,14 +639,14 @@ function build_target
 			BUILD_NAME="${config##*/}"
 			BUILD_NAME="${BUILD_NAME##config.}"
 			BUILD_NAME=$(echo "${BUILD_NAME}" | tr '[:lower:]' '[:upper:]')
-			echo $BUILD_NAME $MAINBOARD
+			printf "%s %s\n" "$BUILD_NAME" "$MAINBOARD"
 			# If the file in configs/ results in the same build_name as the default config
 			# append a '_' to differentiate. Otherwise the default configuration would
 			# override the results.
 			if [[ "${MAINBOARD}" = "${BUILD_NAME}" ]]; then
 				BUILD_NAME=${BUILD_NAME}"_"
 			fi
-			echo "Building config $BUILD_NAME"
+			printf "Building config %s\n" "$BUILD_NAME"
 			build_dir=$TARGET/${BUILD_NAME}
 			build_config "$MAINBOARD" "$build_dir" "$BUILD_NAME" "$config"
 			record_mainboard "$BUILD_NAME"
@@ -650,7 +654,7 @@ function build_target
 		done
 	fi
 
-	echo "Building board $MAINBOARD (using default config)"
+	printf "Building board %s (using default config)\n" "$MAINBOARD"
 	build_dir=$TARGET/${MAINBOARD}
 	build_config "$MAINBOARD" "$build_dir" "$MAINBOARD"
 	record_mainboard "$MAINBOARD"
@@ -671,7 +675,7 @@ function remove_target
 		   "${BUILD_NAME}_coreboot.rom"
 	fi
 
-	echo "Removing build dir for $BUILD_NAME..."
+	printf "Removing build dir for %s...\n" "$BUILD_NAME"
 	rm -rf "${TARGET:?}/${BUILD_NAME}"
 
 	return
@@ -921,18 +925,18 @@ if [[ -n "$1" ]]; then
 	printf "Invalid option '%s'\n\n" "$1"; myhelp; exit 1;
 fi
 
-if [[ -z "$TARGET" || "$TARGET" = "/" ]]; then
-	echo "Please specify a valid, non-root build directory."
+if [[ -z "$TARGET" ]] || [[ "$TARGET" = "/" ]]; then
+	printf "Please specify a valid, non-root build directory.\n"
 	exit 1
 fi
 
 if ! mkdir -p "$TARGET"; then
-	echo "Unable to create build directory"
+	printf "Unable to create build directory\\n"
 	exit 1
 fi
 
 if echo "${skipconfig_set}${skipconfig_unset}" | grep -q "CONFIG_" >/dev/null 2>&1; then
-	echo "Error: Do not include CONFIG_ in the Kconfig value to skip"
+	printf "Error: Do not include CONFIG_ in the Kconfig value to skip\n"
 	exit 1
 fi
 
@@ -968,7 +972,7 @@ if [[ "$cpus" != "1" ]]; then
 	fi
 	# Test if xargs supports the non-standard -P flag
 	# FIXME: disabled until we managed to eliminate all the make(1) quirks
-	echo | xargs -P ${cpus:-0} -n 1 echo 2>/dev/null >/dev/null && USE_XARGS=1
+	printf "\n" | xargs -P ${cpus:-0} -n 1 printf "%s\n" 2>/dev/null >/dev/null && USE_XARGS=1
 fi
 
 if [[ "$USE_XARGS" = "0" ]]; then
@@ -1028,13 +1032,13 @@ build_targets()
 	fi
 
 	if [[ "$scanbuild" = "true" ]]; then
-		mv "${scanbuild_out}tmp/"* "${scanbuild_out}"
+		mv "${scanbuild_out}tmp"/* "${scanbuild_out}"
 		rmdir "${scanbuild_out}tmp"
 	fi
 	rm -rf "$TARGET/temp" "$TMPCFG"
 	num_targets=$(wc -w <<<"$targets")
 	cpus_per_target=$(((${cpus:-1} + num_targets - 1) / num_targets))
-	echo "$targets" | xargs -P ${cpus:-0} -n 1 "$0" "${cmdline[@]}" -I -c "$cpus_per_target" -t
+	printf "%s\n" "$targets" | xargs -P ${cpus:-0} -n 1 "$0" "${cmdline[@]}" -I -c "$cpus_per_target" -t
 }
 fi
 
@@ -1056,7 +1060,7 @@ if [[ "$target" != "" ]]; then
 	if [[ "$(echo "${MAINBOARD}" | wc -w)" -gt 1 ]]; then
 		build_targets "${MAINBOARD}"
 	elif [[ ! -r "$ROOT/src/mainboard/${build_srcdir}" ]]; then
-		echo "No such target: ${MAINBOARD}"
+		printf "No such target: %s\n" "${MAINBOARD}"
 		exit 1
 	else
 		build_target "${MAINBOARD}"
@@ -1083,7 +1087,7 @@ if [[ "$recursive" = "false" ]]; then
 	if [[ -f "$FAILED_BOARDS" ]]; then
 		printf "%s configuration(s) failed:\n" "$( wc -l < "$FAILED_BOARDS" )"
 		cat "$FAILED_BOARDS"
-		echo
+		printf "\n"
 		if [[ "$exitcode" != "0" ]]; then
 			failed=1
 		fi

From 9ddb54e6ad034680bc21ecc9cc78daf958ed6433 Mon Sep 17 00:00:00 2001
From: Martin Roth <gaumless@gmail.com>
Date: Sun, 20 Apr 2025 12:21:11 -0600
Subject: [PATCH 0982/3886] util/abuild: Update syntax from 'function func' to
 'func()'

Abuild used a mix of 'function funcname' and 'funcname()`. This
standardizes them all to use the 'funcname()' format. While they do
the same thing, we should be consistent across the file, and the
'funcname()' syntax is generally preferred.

Change-Id: I7530aa41b6413f0d5febe3d8a0db4a98113e1448
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87369
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
---
 util/abuild/abuild | 44 ++++++++++++++++++++++----------------------
 1 file changed, 22 insertions(+), 22 deletions(-)

diff --git a/util/abuild/abuild b/util/abuild/abuild
index d126f79253..5e4080b84f 100755
--- a/util/abuild/abuild
+++ b/util/abuild/abuild
@@ -103,7 +103,7 @@ ts_basetime_str=$(date -u --date=@${ts_exec_shell})
 
 trap interrupt INT
 
-function interrupt
+interrupt()
 {
 	printf "\n%s: execution interrupted manually.\n" "$0"
 	if [[ "$mode" == "junit" ]]; then
@@ -112,18 +112,18 @@ function interrupt
 	exit 1
 }
 
-function debug
+debug()
 {
 	[[ "$verbose" == "true" ]] && printf "%s\n" "$*"
 }
 
-function junit
+junit()
 {
 	[[ "$mode" == "junit" ]] && printf "%s\n" "$*" >> "$XMLFILE"
 	return 0
 }
 
-function junitfile
+junitfile()
 {
 	test "$mode" == "junit" && {
 		printf '<![CDATA[\n'
@@ -136,7 +136,7 @@ function junitfile
 # By default all mainboards are listed, but when passing a two-level path
 # below src/mainboard, such as emulation/qemu-i440fx, or emulation/*, it
 # returns all board descriptors in that hierarchy.
-function get_mainboards
+get_mainboards()
 {
 	local search_space=${1-*/*}
 	# shellcheck disable=SC2086
@@ -146,7 +146,7 @@ function get_mainboards
 }
 
 # Given a mainboard descriptor, return its directory below src/mainboard
-function mainboard_directory
+mainboard_directory()
 {
 	local MAINBOARD=$1
 
@@ -157,7 +157,7 @@ function mainboard_directory
 }
 
 # Given a mainboard descriptor, return its vendor (CONFIG_VENDOR_*)
-function mainboard_vendor
+mainboard_vendor()
 {
 	local MAINBOARD=$1
 	local kconfig_file
@@ -178,7 +178,7 @@ function mainboard_vendor
 # descriptors (eg. EMULATION_QEMU_X86_I440F} and returns the latter
 # format.
 # If a directory contains multiple boards, returns them all.
-function normalize_target
+normalize_target()
 {
 	# TODO: Change 'targets' variable to an array
 	local targets
@@ -206,7 +206,7 @@ function normalize_target
 }
 
 # shellcheck disable=SC2129
-function create_config
+create_config()
 {
 	local BUILD_NAME=$1
 	local build_dir=$2
@@ -241,7 +241,7 @@ function create_config
 	fi
 }
 
-function update_config
+update_config()
 {
 	local BUILD_NAME=$1
 	local build_dir=$2
@@ -313,7 +313,7 @@ function update_config
 }
 
 # shellcheck disable=SC2129
-function create_buildenv
+create_buildenv()
 {
 	local BUILD_NAME=$1
 	local build_dir=$2
@@ -346,7 +346,7 @@ function create_buildenv
 	return $ret
 }
 
-function check_config
+check_config()
 {
 	local BUILD_DIR="$1"
 	local TEST_TYPE="$2"
@@ -374,7 +374,7 @@ function check_config
 }
 
 # Counting microseconds since start of shell
-function add_timestamp
+add_timestamp()
 {
 	local now=${EPOCHREALTIME}
 	local seconds=$(echo $now | cut -f 1 -d '.')
@@ -384,13 +384,13 @@ function add_timestamp
 	printf "%s" $usecs
 }
 
-function ts_delta_seconds
+ts_delta_seconds()
 {
 	local delta=$(( ($2 - $1) / (1000 * 1000) ))
 	printf "%s" $delta
 }
 
-function ts_delta_string
+ts_delta_string()
 {
 	local ts_minutes
 	local ts_seconds
@@ -409,7 +409,7 @@ function ts_delta_string
 	fi
 }
 
-function compile_target
+compile_target()
 {
 	local BUILD_NAME=$1
 
@@ -480,7 +480,7 @@ function compile_target
 	return $MAKE_FAILED
 }
 
-function build_config
+build_config()
 {
 	local MAINBOARD=$1
 	local build_dir=$2
@@ -613,7 +613,7 @@ EOF
 	junit "</testcase>"
 }
 
-function record_mainboard
+record_mainboard()
 {
 	local log=$1
 
@@ -627,7 +627,7 @@ function record_mainboard
 }
 
 # One target may build several configs
-function build_target
+build_target()
 {
 	local MAINBOARD=$1
 	local MAINBOARD_LC
@@ -661,7 +661,7 @@ function build_target
 	remove_target "$MAINBOARD"
 }
 
-function remove_target
+remove_target()
 {
 	if [[ "$remove" != "true" ]]; then
 		return
@@ -681,7 +681,7 @@ function remove_target
 	return
 }
 
-function myhelp
+myhelp()
 {
 cat << __END_OF_HELP
 Usage: $0 [options]
@@ -736,7 +736,7 @@ Options:\n
 __END_OF_HELP
 }
 
-function myversion
+myversion()
 {
 	cat << EOF
 

From a2baaec067e16220c678eade508ed00038c3ee08 Mon Sep 17 00:00:00 2001
From: Martin Roth <gaumless@gmail.com>
Date: Sun, 20 Apr 2025 12:54:47 -0600
Subject: [PATCH 0983/3886] util/abuild: Use ${} around variable names

While not always necessary, for consistency, use the ${} around all
variables.

Change-Id: I53fdddfd41e8aaa062bee73f441c5a816282c8ed
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87370
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
---
 util/abuild/abuild | 417 ++++++++++++++++++++++-----------------------
 1 file changed, 208 insertions(+), 209 deletions(-)

diff --git a/util/abuild/abuild b/util/abuild/abuild
index 5e4080b84f..a9525f8b1f 100755
--- a/util/abuild/abuild
+++ b/util/abuild/abuild
@@ -14,12 +14,12 @@
 ABUILD_DATE="Nov 18, 2023"
 ABUILD_VERSION="0.11.03"
 
-TOP=$PWD
+TOP=${PWD}
 
 # Where shall we place all the build trees?
 TARGET_DEFAULT=coreboot-builds
 TARGET=${COREBOOT_BUILD_DIR:-${TARGET_DEFAULT}}
-XML_DEFAULT="$TOP/abuild.xml"
+XML_DEFAULT="${TOP}/abuild.xml"
 XMLFILE="${XML_DEFAULT}"
 REAL_XMLFILE="${XML_DEFAULT}"
 
@@ -36,13 +36,13 @@ export COREBOOT_ABUILD=1
 PAYLOAD=/dev/null
 
 # get path to coreboot XGCC if it's not already set
-if [[ -z "$XGCCPATH" ]]; then
+if [[ -z "${XGCCPATH}" ]]; then
 	XGCCPATH="${TOP}/util/crossgcc/xgcc/bin/"
 fi
 
 # Add XGCC to the path.
-if [[ -d "$XGCCPATH" ]] && [[ ":$PATH:" != *":$XGCCPATH:"* ]]; then
-	PATH="$XGCCPATH:$PATH"
+if [[ -d "${XGCCPATH}" ]] && [[ ":${PATH}:" != *":${XGCCPATH}:"* ]]; then
+	PATH="${XGCCPATH}:${PATH}"
 fi
 
 # Lines of error context to be printed in FAILURE case
@@ -64,7 +64,7 @@ checksum_file=""
 cpus=1
 
 # change with -d <directory>
-configdir="$TOP/configs"
+configdir="${TOP}/configs"
 
 # Timeless builds
 TIMELESS=0
@@ -114,22 +114,22 @@ interrupt()
 
 debug()
 {
-	[[ "$verbose" == "true" ]] && printf "%s\n" "$*"
+	[[ "${verbose}" == "true" ]] && printf "%s\n" "$*"
 }
 
 junit()
 {
-	[[ "$mode" == "junit" ]] && printf "%s\n" "$*" >> "$XMLFILE"
+	[[ "${mode}" == "junit" ]] && printf "%s\n" "$*" >> "${XMLFILE}"
 	return 0
 }
 
 junitfile()
 {
-	test "$mode" == "junit" && {
+	test "${mode}" == "junit" && {
 		printf '<![CDATA[\n'
 		cat "$1"
 		printf ']]>\n'
-	} >> "$XMLFILE"
+	} >> "${XMLFILE}"
 }
 
 # Return mainboard descriptors.
@@ -167,10 +167,10 @@ mainboard_vendor()
 	grep -l "^[[:space:]]*config\>[[:space:]]*\<BOARD_${MAINBOARD}\>" \
 		${ROOT}/src/mainboard/*/*/Kconfig.name | \
 		sed "s:^\(${ROOT}/src/mainboard/.*\)/.*/\(Kconfig.name\)$:\1/\2:" )
-	if [[ ! -f "$kconfig_file" ]]; then
+	if [[ ! -f "${kconfig_file}" ]]; then
 		exit 1
 	fi
-	grep "^[[:space:]]*config\>[[:space:]]*\<VENDOR_" "$kconfig_file" | \
+	grep "^[[:space:]]*config\>[[:space:]]*\<VENDOR_" "${kconfig_file}" | \
 		sed "s,^.*\<VENDOR_\([A-Z0-9_]*\)\>.*$,\1,"
 }
 
@@ -187,19 +187,19 @@ normalize_target()
 	VARIANT_UC=$(echo "${variant}" | tr '[:lower:]' '[:upper:]' | tr '-' '_')
 
 	targets=$(get_mainboards "$1")
-	if [[ -n "$targets" ]]; then
+	if [[ -n "${targets}" ]]; then
 		# shellcheck disable=SC2086
 		targets="$(grep "${VARIANT_UC}\$" <<< ${targets})"
-		echo "$targets"
+		echo "${targets}"
 		return
 	fi
 
 	targets=$(echo "$1" | tr ',' ' ')
-	for i in $targets; do
-		if [[ -n "$(mainboard_directory "$i")" ]]; then
-			printf "%s\n" "$i"
+	for i in ${targets}; do
+		if [[ -n "$(mainboard_directory "${i}")" ]]; then
+			printf "%s\n" "${i}"
 		else
-			printf "%s is not a valid target\n" "$i" >&2
+			printf "%s is not a valid target\n" "${i}" >&2
 			exit 1
 		fi
 	done
@@ -213,12 +213,12 @@ create_config()
 	local board_srcdir
 
 	local config_file="${build_dir}/config.build"
-	board_srcdir="$(mainboard_directory "${BUILD_NAME}")"
+	board_srcdir=$(mainboard_directory "${BUILD_NAME}")
 
 	mkdir -p "${build_dir}"
-	mkdir -p "$TARGET/sharedutils"
+	mkdir -p "${TARGET}/sharedutils"
 
-	if [[ "$quiet" == "false" ]]; then printf "  Creating config file for %s...\n" "$BUILD_NAME"; fi
+	if [[ "${quiet}" == "false" ]]; then printf "  Creating config file for %s...\n" "${BUILD_NAME}"; fi
 	{
 		printf "CONFIG_VENDOR_%s=y\n" "$(mainboard_vendor "${BUILD_NAME}")"
 		printf "CONFIG_BOARD_%s=y\n" "${BUILD_NAME}"
@@ -227,16 +227,16 @@ create_config()
 		printf "CONFIG_MAINBOARD_DIR=\\\"%s\\\"\n" "${board_srcdir}"
 	} > "${config_file}"
 
-	update_config "$BUILD_NAME" "$build_dir" "$config_file"
+	update_config "${BUILD_NAME}" "${build_dir}" "${config_file}"
 
 	ret=$?
-	if [[ $ret -eq 0 ]]; then
-		if [[ "${quiet}" == "false" ]]; then printf "  %s config created.\n" "$BUILD_NAME"; fi
+	if [[ ${ret} -eq 0 ]]; then
+		if [[ "${quiet}" == "false" ]]; then printf "  %s config created.\n" "${BUILD_NAME}"; fi
 		return 0
 	else
 		# Does this ever happen?
-		if [[ "${quiet}" == "false" ]]; then printf "%s config creation FAILED!\nLog excerpt:\n" "$BUILD_NAME"; fi
-		tail -n $CONTEXT "$build_dir/config.log" 2> /dev/null || tail -$CONTEXT "$build_dir/config.log"
+		if [[ "${quiet}" == "false" ]]; then printf "%s config creation FAILED!\nLog excerpt:\n" "${BUILD_NAME}"; fi
+		tail -n ${CONTEXT} "${build_dir}/config.log" 2> /dev/null || tail -${CONTEXT} "${build_dir}/config.log"
 		return 1
 	fi
 }
@@ -257,24 +257,24 @@ update_config()
 	#   Usage: payload.sh [BOARD]
 	# the script returns an absolute path to the payload binary.
 
-	if [[ -f "$payloads/payload.sh" ]]; then
-		PAYLOAD=$(sh "$payloads/payload.sh" "$BUILD_NAME")
+	if [[ -f "${payloads}/payload.sh" ]]; then
+		PAYLOAD=$(sh "${payloads}/payload.sh" "${BUILD_NAME}")
 		local PAYLOAD_OK=$?
-		if [[ $PAYLOAD_OK -gt 0 ]]; then
+		if [[ ${PAYLOAD_OK} -gt 0 ]]; then
 			printf "Problem with payload\n"
 			exit 1
 		fi
-		if [[ "$quiet" == "false" ]]; then printf "Using payload %s\n" "$PAYLOAD"; fi
-	elif [[ "$payloads" = "none" ]]; then
+		if [[ "${quiet}" == "false" ]]; then printf "Using payload %s\n" "${PAYLOAD}"; fi
+	elif [[ "${payloads}" = "none" ]]; then
 		PAYLOAD=none
 	fi
 
-	if [[ "$PAYLOAD" = "none" ]]; then
+	if [[ "${PAYLOAD}" = "none" ]]; then
 		{
 			printf "CONFIG_PAYLOAD_NONE=y\n"
 			printf "# CONFIG_PAYLOAD_ELF is not set\n"
 		} >> "${config_file}"
-	elif [[ "$PAYLOAD" != "/dev/null" ]]; then
+	elif [[ "${PAYLOAD}" != "/dev/null" ]]; then
 		{
 			printf "# CONFIG_PAYLOAD_NONE is not set\n"
 			printf "CONFIG_PAYLOAD_ELF=y\n"
@@ -298,14 +298,14 @@ update_config()
 		printf "# CONFIG_TINT_SECONDARY_PAYLOAD is not set\n"
 	} >> "${config_file}"
 
-	if [[ "$quiet" == "false" ]]; then printf "    %s (%s)\n" "$MAINBOARD" "$customizing"; fi
+	if [[ "${quiet}" == "false" ]]; then printf "    %s (%s)\n" "${MAINBOARD}" "${customizing}"; fi
 	# shellcheck disable=SC2059
-	printf "$configoptions" >> "${config_file}"
+	printf "${configoptions}" >> "${config_file}"
 
-	$MAKE olddefconfig "$verboseopt" "DOTCONFIG=${config_file}" "obj=${build_dir}" "objutil=$TARGET/sharedutils" &> "${build_dir}/config.log" ; \
+	${MAKE} olddefconfig "${verboseopt}" "DOTCONFIG=${config_file}" "obj=${build_dir}" "objutil=${TARGET}/sharedutils" &> "${build_dir}/config.log" ; \
 		CONFIG_OK=$?
-	if [[ $CONFIG_OK -eq 0 ]]; then
-		$MAKE savedefconfig "$verboseopt" DEFCONFIG="${defconfig_file}" DOTCONFIG="${config_file}" obj="${build_dir}" objutil="$TARGET/sharedutils" &>> "${build_dir}/config.log"
+	if [[ ${CONFIG_OK} -eq 0 ]]; then
+		${MAKE} savedefconfig "${verboseopt}" DEFCONFIG="${defconfig_file}" DOTCONFIG="${config_file}" obj="${build_dir}" objutil="${TARGET}/sharedutils" &>> "${build_dir}/config.log"
 		return $?
 	else
 		return 1
@@ -319,31 +319,31 @@ create_buildenv()
 	local build_dir=$2
 	local config_file=$3
 
-	if [[ -z "$config_file" ]]; then
-		create_config "$BUILD_NAME" "$build_dir"
+	if [[ -z "${config_file}" ]]; then
+		create_config "${BUILD_NAME}" "${build_dir}"
 	else
 		local new_config_file="${build_dir}/config.build"
-		cp "$config_file" "$new_config_file"
-		update_config "$BUILD_NAME" "$build_dir" "$new_config_file"
+		cp "${config_file}" "${new_config_file}"
+		update_config "${BUILD_NAME}" "${build_dir}" "${new_config_file}"
 	fi
 	local ret=$?
 
 	# Allow simple "make" in the target directory
-	local MAKEFILE=$TARGET/${BUILD_NAME}/Makefile
-	printf "# autogenerated\n" > "$MAKEFILE"
-	printf "TOP=%s\n" "$ROOT" >> "$MAKEFILE"
-	printf "BUILD=%s\n" "$TARGET" >> "$MAKEFILE"
-	printf "OBJ=\$(BUILD)/%s\n" "${MAINBOARD}" >> "$MAKEFILE"
-	printf "OBJUTIL=\$(BUILD)/sharedutils\n" >> "$MAKEFILE"
-	printf "all:\n" >> "$MAKEFILE"
-	printf "\t@cp -a config.h config.h.bak\n" >> "$MAKEFILE"
-	printf "\t@cd \$(TOP); \$(MAKE) olddefconfig DOTCONFIG=\$(OBJ)/config.build objutil=\$(OBJUTIL) obj=\$(OBJ)\n" >> "$MAKEFILE"
-	printf "\t@tail -n+6 config.h > config.new; tail -n+6 config.h.bak > config.old\n" >> "$MAKEFILE"
-	printf "\t@cmp -s config.new config.old && cp -a config.h.bak config.h || printf \"Config file changed\"\n" >> "$MAKEFILE"
-	printf "\t@rm config.h.bak config.new config.old\n" >> "$MAKEFILE"
-	printf "\t@cd \$(TOP); \$(MAKE) DOTCONFIG=\$(OBJ)/config.build objutil=\$(OBJUTIL) obj=\$(OBJ)\n" >> "$MAKEFILE"
+	local MAKEFILE=${TARGET}/${BUILD_NAME}/Makefile
+	printf "# autogenerated\n" > "${MAKEFILE}"
+	printf "TOP=%s\n" "${ROOT}" >> "${MAKEFILE}"
+	printf "BUILD=%s\n" "${TARGET}" >> "${MAKEFILE}"
+	printf "OBJ=\$(BUILD)/%s\n" "${MAINBOARD}" >> "${MAKEFILE}"
+	printf "OBJUTIL=\$(BUILD)/sharedutils\n" >> "${MAKEFILE}"
+	printf "all:\n" >> "${MAKEFILE}"
+	printf "\t@cp -a config.h config.h.bak\n" >> "${MAKEFILE}"
+	printf "\t@cd \$(TOP); \$(MAKE) olddefconfig DOTCONFIG=\$(OBJ)/config.build objutil=\$(OBJUTIL) obj=\$(OBJ)\n" >> "${MAKEFILE}"
+	printf "\t@tail -n+6 config.h > config.new; tail -n+6 config.h.bak > config.old\n" >> "${MAKEFILE}"
+	printf "\t@cmp -s config.new config.old && cp -a config.h.bak config.h || printf \"Config file changed\"\n" >> "${MAKEFILE}"
+	printf "\t@rm config.h.bak config.new config.old\n" >> "${MAKEFILE}"
+	printf "\t@cd \$(TOP); \$(MAKE) DOTCONFIG=\$(OBJ)/config.build objutil=\$(OBJUTIL) obj=\$(OBJ)\n" >> "${MAKEFILE}"
 
-	return $ret
+	return ${ret}
 }
 
 check_config()
@@ -356,16 +356,16 @@ check_config()
 	local CONFIG_FILE="$BUILD_DIR/config.build"
 	local CONFIG_LOG="$BUILD_DIR/config.log"
 
-	if [[ -z "$NEGATE" ]]; then
-		if ! grep -q "$TEST_STRING" "$CONFIG_FILE"; then
-			printf "config file: %s has incorrect %s\n" "$CONFIG_FILE" "$TEST_TYPE"
-			printf "Error: Expected '%s' in config file.\n" "$TEST_STRING" >> "$CONFIG_LOG"
+	if [[ -z "${NEGATE}" ]]; then
+		if ! grep -q "${TEST_STRING}" "${CONFIG_FILE}"; then
+			printf "config file: %s has incorrect %s\n" "${CONFIG_FILE}" "${TEST_TYPE}"
+			printf "Error: Expected '%s' in config file.\n" "${TEST_STRING}" >> "${CONFIG_LOG}"
 			return 1
 		fi
 	else
-		if grep -q "$TEST_STRING" "$CONFIG_FILE"; then
-			printf "config file: %s has incorrect %s\n" "$CONFIG_FILE" "$TEST_TYPE"
-			printf "Error: Expected not to see '%s' in config file.\n" "$TEST_STRING" >> "$CONFIG_LOG"
+		if grep -q "${TEST_STRING}" "${CONFIG_FILE}"; then
+			printf "config file: %s has incorrect %s\n" "${CONFIG_FILE}" "${TEST_TYPE}"
+			printf "Error: Expected not to see '%s' in config file.\n" "${TEST_STRING}" >> "${CONFIG_LOG}"
 			return 1
 		fi
 	fi
@@ -377,17 +377,17 @@ check_config()
 add_timestamp()
 {
 	local now=${EPOCHREALTIME}
-	local seconds=$(echo $now | cut -f 1 -d '.')
-	local usecs=$(echo $now | cut -f 2 -d '.')
+	local seconds=$(echo ${now} | cut -f 1 -d '.')
+	local usecs=$(echo ${now} | cut -f 2 -d '.')
 	seconds=$(( seconds - ts_exec_shell ))
 	usecs=$(( seconds * 1000 * 1000 + 10#$usecs ))
-	printf "%s" $usecs
+	printf "%s" ${usecs}
 }
 
 ts_delta_seconds()
 {
 	local delta=$(( ($2 - $1) / (1000 * 1000) ))
-	printf "%s" $delta
+	printf "%s" ${delta}
 }
 
 ts_delta_string()
@@ -402,10 +402,10 @@ ts_delta_string()
 	ts_seconds=$(( delta / 1000))
 	delta=$(( delta % 1000 ))
 
-	if [[ $ts_minutes -ne 0 ]] ; then
-		printf "%d min %d sec" $ts_minutes $ts_seconds
+	if [[ ${ts_minutes} -ne 0 ]] ; then
+		printf "%d min %d sec" ${ts_minutes} ${ts_seconds}
 	else
-		printf "%d.%03d seconds" $ts_seconds $delta
+		printf "%d.%03d seconds" ${ts_seconds} ${delta}
 	fi
 }
 
@@ -413,12 +413,12 @@ compile_target()
 {
 	local BUILD_NAME=$1
 
-	if [[ "${quiet}" == "false" ]]; then printf "  Compiling %s image%s...\n" "$MAINBOARD" "$cpuconfig"; fi
+	if [[ "${quiet}" == "false" ]]; then printf "  Compiling %s image%s...\n" "${MAINBOARD}" "${cpuconfig}"; fi
 
 	CURR=$( pwd )
 
 	ts_1=$(add_timestamp)
-	eval "$BUILDPREFIX" "$MAKE" "$verboseopt" DOTCONFIG="${build_dir}/config.build" obj="${build_dir}" objutil="$TARGET/sharedutils" BUILD_TIMELESS=$TIMELESS \
+	eval "${BUILDPREFIX}" "${MAKE}" "${verboseopt}" DOTCONFIG="${build_dir}/config.build" obj="${build_dir}" objutil="${TARGET}/sharedutils" BUILD_TIMELESS=${TIMELESS} \
 		&> "${build_dir}/make.log" ; \
 		MAKE_FAILED=$?
 	ts_2=$(add_timestamp)
@@ -427,38 +427,38 @@ compile_target()
 
 	timestamps="abuild.timestamps"
 	printf "Build started %s\n" "${ts_basetime_str}" > "${timestamps}"
-	printf "BASETIME_SECONDS %d\n" $ts_exec_shell >> "${timestamps}"
-	printf "TS_0 %d\n" $ts_0 >> "${timestamps}"
-	printf "TS_1 %d\n" $ts_1 >> "${timestamps}"
-	printf "TS_2 %d\n" $ts_2 >> "${timestamps}"
+	printf "BASETIME_SECONDS %d\n" ${ts_exec_shell} >> "${timestamps}"
+	printf "TS_0 %d\n" ${ts_0} >> "${timestamps}"
+	printf "TS_1 %d\n" ${ts_1} >> "${timestamps}"
+	printf "TS_2 %d\n" ${ts_2} >> "${timestamps}"
 
-	duration=$(ts_delta_seconds $ts_0 $ts_2)
-	duration_str=$(ts_delta_string $ts_0 $ts_2)
-	junit " <testcase classname='${TESTRUN}${testclass/#/.}' name='$BUILD_NAME' time='$duration' >"
+	duration=$(ts_delta_seconds ${ts_0} ${ts_2})
+	duration_str=$(ts_delta_string ${ts_0} ${ts_2})
+	junit " <testcase classname='${TESTRUN}${testclass/#/.}' name='${BUILD_NAME}' time='${duration}' >"
 
-	if [[ $MAKE_FAILED -eq 0 ]]; then
+	if [[ ${MAKE_FAILED} -eq 0 ]]; then
 		junit "<system-out>"
 		junitfile make.log
 		junit "</system-out>"
 		printf "ok\n" > compile.status
-		printf "%s built successfully. (took %s)\n" "$BUILD_NAME" "${duration_str}"
-		echo "$BUILD_NAME" >> "$PASSED_BOARDS"
+		printf "%s built successfully. (took %s)\n" "${BUILD_NAME}" "${duration_str}"
+		echo "${BUILD_NAME}" >> "${PASSED_BOARDS}"
 	else
 		junit "<failure type='BuildFailed'>"
 		junitfile make.log
 		junit "</failure>"
 		printf "failed\n" > compile.status
-		printf "%s build FAILED after %s!\nLog excerpt:\n" "$BUILD_NAME" "${duration_str}"
-		tail -n $CONTEXT make.log 2> /dev/null || tail -$CONTEXT make.log
-		if [[ "$clean_work" = "true" ]]; then
-			echo "$BUILD_NAME" >> "$FAILED_BOARDS"
+		printf "%s build FAILED after %s!\nLog excerpt:\n" "${BUILD_NAME}" "${duration_str}"
+		tail -n ${CONTEXT} make.log 2> /dev/null || tail -${CONTEXT} make.log
+		if [[ "${clean_work}" = "true" ]]; then
+			echo "${BUILD_NAME}" >> "${FAILED_BOARDS}"
 		else
-			echo "$BUILD_NAME - Log: ${build_dir}/make.log" >> "$FAILED_BOARDS"
+			echo "${BUILD_NAME} - Log: ${build_dir}/make.log" >> "${FAILED_BOARDS}"
 		fi
 		failed=1
 	fi
-	cd "$CURR" || return $?
-	if [[ -n "$checksum_file" ]]; then
+	cd "${CURR}" || return $?
+	if [[ -n "${checksum_file}" ]]; then
 		sha256sum "${build_dir}/coreboot.rom" >> "${checksum_file}_platform"
 		sort "${build_dir}/config.h" | grep CONFIG_ > "${build_dir}/config.h.sorted"
 		sha256sum "${build_dir}/config.h.sorted" >> "${checksum_file}_config"
@@ -468,16 +468,16 @@ compile_target()
 	if [[ -f ${build_dir}/ccache.stats ]]; then
 		stats_files="${stats_files} ${build_dir}/ccache.stats"
 	fi
-	flock -F -w 0.1 $TARGET/.statslock tar -rf ${stats_archive} ${stats_files} 2> /dev/null
+	flock -F -w 0.1 ${TARGET}/.statslock tar -rf ${stats_archive} ${stats_files} 2> /dev/null
 
-	if [[ "$clean_work" = "true" ]]; then
+	if [[ "${clean_work}" = "true" ]]; then
 		rm -rf "${build_dir}"
 	fi
-	if [[ "$clean_objs" = "true" ]]; then
+	if [[ "${clean_objs}" = "true" ]]; then
 		find ${build_dir} \! \( -name coreboot.rom -o -name config.h -o -name config.build -o -name make.log \) -type f -exec rm {} +
 		find ${build_dir} -type d -exec rmdir -p {} + 2>/dev/null
 	fi
-	return $MAKE_FAILED
+	return ${MAKE_FAILED}
 }
 
 build_config()
@@ -492,48 +492,48 @@ build_config()
 	board_srcdir=$(mainboard_directory "${MAINBOARD}")
 
 	if [[ "$(cat "${build_dir}/compile.status" 2>/dev/null)" = "ok" ]] && \
-		[[ "$buildall" = "false" ]]; then
-		printf "Skipping %s; (already successful)\n" "$BUILD_NAME"
+				[[ "${buildall}" = "false" ]]; then
+		printf "Skipping %s; (already successful)\n" "${BUILD_NAME}"
+
 		return
 	fi
 
 	export HOSTCC='gcc'
 
-	if [[ "$chromeos" = true ]] && [[ "$(grep -c "^[[:space:]]*select[[:space:]]*MAINBOARD_HAS_CHROMEOS>" "${ROOT}/src/mainboard/${board_srcdir}/Kconfig")" -eq 0 ]]; then
 		printf "%s doesn't support ChromeOS, skipping.\n" "${BUILD_NAME}"
-
+	if [[ "${chromeos}" = true ]] && [[ "$(grep -c "^[[:space:]]*select[[:space:]]*MAINBOARD_HAS_CHROMEOS>" "${ROOT}/src/mainboard/${board_srcdir}/Kconfig")" -eq 0 ]]; then
 		return
 	fi
 
-	if [[ "${quiet}" == "false" ]]; then printf "Building %s\n" "$BUILD_NAME"; fi
-	mkdir -p "$TARGET/${BUILD_NAME}" "$TARGET/abuild"
-	ABSPATH="$(cd "$TARGET/abuild" && pwd)"
-	XMLFILE="$ABSPATH/${BUILD_NAME}.xml"
+	if [[ "${quiet}" == "false" ]]; then printf "Building %s\n" "${BUILD_NAME}"; fi
+	mkdir -p "${TARGET}/${BUILD_NAME}" "${TARGET}/abuild"
+	ABSPATH="$(cd "${TARGET}/abuild" && pwd)"
+	XMLFILE="${ABSPATH}/${BUILD_NAME}.xml"
 	rm -f "${XMLFILE}"
 
 	ts_0=$(add_timestamp)
 
-	create_buildenv "$BUILD_NAME" "$build_dir" "$config_file"
+	create_buildenv "${BUILD_NAME}" "${build_dir}" "${config_file}"
 	local BUILDENV_CREATED=$?
 
-	check_config "$build_dir" "mainboard" "CONFIG_BOARD_${MAINBOARD}=y"
+	check_config "${build_dir}" "mainboard" "CONFIG_BOARD_${MAINBOARD}=y"
 	local MAINBOARD_OK=$?
 
-	check_config "$build_dir" "vendor" "CONFIG_VENDOR_$(mainboard_vendor "${MAINBOARD}")=y"
+	check_config "${build_dir}" "vendor" "CONFIG_VENDOR_$(mainboard_vendor "${MAINBOARD}")=y"
 	local VENDOR_OK=$?
 
-	if [[ "$chromeos" = false ]]; then
+	if [[ "${chromeos}" = false ]]; then
 		# Skip this rule for configs created from templates that already
 		# come with CHROMEOS enabled.
 		grep -q "^CONFIG_CHROMEOS=y" ${config_file:-/dev/null} || \
-		check_config "$build_dir" "ChromeOS" "CONFIG_CHROMEOS=y" negate
+		check_config "${build_dir}" "ChromeOS" "CONFIG_CHROMEOS=y" negate
 		local FORCE_ENABLED_CROS=$?
 	else
 		local FORCE_ENABLED_CROS=0
 	fi
 
-	if [[ "$clang" = true ]]; then
-		check_config "$build_dir" "clang" "CONFIG_COMPILER_LLVM_CLANG=y"
+	if [[ "${clang}" = true ]]; then
+		check_config "${build_dir}" "clang" "CONFIG_COMPILER_LLVM_CLANG=y"
 		if [[ $? -ne 0 ]]; then
 			printf "%s doesn't support clang, skipping.\n" "${MAINBOARD}"
 			return
@@ -556,28 +556,28 @@ build_config()
 		fi
 	fi
 
-	if [[ $BUILDENV_CREATED -ne 0 ]] || [[ $MAINBOARD_OK -ne 0 ]] || [[ $VENDOR_OK -ne 0 ]] || [[ $FORCE_ENABLED_CROS -eq 1 ]]; then
-		junit " <testcase classname='${TESTRUN}${testclass/#/.}' name='$BUILD_NAME' >"
+	if [[ ${BUILDENV_CREATED} -ne 0 ]] || [[ ${MAINBOARD_OK} -ne 0 ]] || [[ ${VENDOR_OK} -ne 0 ]] || [[ ${FORCE_ENABLED_CROS} -eq 1 ]]; then
+		junit " <testcase classname='${TESTRUN}${testclass/#/.}' name='${BUILD_NAME}' >"
 
 		junit "<failure type='BuildFailed'>"
-		junitfile "$build_dir/config.log"
+		junitfile "${build_dir}/config.log"
 		junit "</failure>"
 		printf "failed\n" > compile.status
-		printf "%s build configuration FAILED!\\nLog excerpt:\n" "$BUILD_NAME"
-		tail -n $CONTEXT "$build_dir/config.log" 2> /dev/null || tail -$CONTEXT "$build_dir/config.log"
+		printf "%s build configuration FAILED!\nLog excerpt:\n" "${BUILD_NAME}"
+		tail -n ${CONTEXT} "${build_dir}/config.log" 2> /dev/null || tail -${CONTEXT} "${build_dir}/config.log"
 
 		junit "</testcase>"
-		printf "%s - Log: %s/config.log\n" "$BUILD_NAME" "$build_dir" >> "$FAILED_BOARDS"
+		printf "%s - Log: %s/config.log\n" "${BUILD_NAME}" "${build_dir}" >> "${FAILED_BOARDS}"
 		return
 	fi
 
 	local required_arches
 
-	required_arches=$(grep -E "^CONFIG_ARCH_(BOOTBLOCK|R.MSTAGE|VERSTAGE)" "$TARGET/${BUILD_NAME}/config.build" | \
+	required_arches=$(grep -E "^CONFIG_ARCH_(BOOTBLOCK|R.MSTAGE|VERSTAGE)" "${TARGET}/${BUILD_NAME}/config.build" | \
 			sed "s,^CONFIG_ARCH_[^_]*_\([^=]*\)=.*$,\1," |sort -u |tr 'A-Z\n\r' 'a-z  ')
 
-	missing_arches="$($MAKE --no-print-directory -f - \
-		REQUIRED_ARCHES="$required_arches" <<'EOF'
+	missing_arches="$(${MAKE} --no-print-directory -f - \
+		REQUIRED_ARCHES="${required_arches}" <<'EOF'
 include $(xcompile)
 .PHONY: missing_arches
 missing_arches:
@@ -591,20 +591,20 @@ EOF
 		exit 1
 	fi
 
-	if [[ -n "$missing_arches" ]]; then
-		printf "skipping %s because we're missing compilers for (%s)\n" "$BUILD_NAME" "$missing_arches"
+	if [[ -n "${missing_arches}" ]]; then
+		printf "skipping %s because we're missing compilers for (%s)\n" "${BUILD_NAME}" "${missing_arches}"
 		return
 	fi
 
-	if [[ $BUILDENV_CREATED -eq 0 ]] && [[ $configureonly -eq 0 ]]; then
+	if [[ ${BUILDENV_CREATED} -eq 0 ]] && [[ ${configureonly} -eq 0 ]]; then
 		BUILDPREFIX=
-		if [[ "$scanbuild" = "true" ]]; then
-			scanbuild_out=$TARGET/${BUILD_NAME}-scanbuild
+		if [[ "${scanbuild}" = "true" ]]; then
+			scanbuild_out="${TARGET}/${BUILD_NAME}-scanbuild"
 			rm -rf "${scanbuild_out}"
 			BUILDPREFIX="scan-build ${SCANBUILD_ARGS} -o ${scanbuild_out}tmp"
 		fi
 		compile_target "${BUILD_NAME}"
-		if [[ "$scanbuild" = "true" ]]; then
+		if [[ "${scanbuild}" = "true" ]]; then
 			mv "${scanbuild_out}"tmp/* "${scanbuild_out}"
 			rmdir "${scanbuild_out}tmp"
 		fi
@@ -617,12 +617,11 @@ record_mainboard()
 {
 	local log=$1
 
-		printf "%s/abuild/%s.xml written to %s\n" "$TARGET" "${log}" "$REAL_XMLFILE" >&2
-	if test "$mode" != "text" && test -f "$TARGET/abuild/${log}.xml"; then
-		cat "$TARGET/abuild/${log}.xml" >> "$REAL_XMLFILE"
-		printf "%s/abuild/%s.xml written to %s\\n" "$TARGET" "${log}" "$REAL_XMLFILE" >&2
+		printf "%s/abuild/%s.xml written to %s\n" "${TARGET}" "${log}" "${REAL_XMLFILE}" >&2
+	if test "${mode}" != "text" && test -f "${TARGET}/abuild/${log}.xml"; then
+		cat "${TARGET}/abuild/${log}.xml" >> "${REAL_XMLFILE}"
 	else
-		printf "Warning: %s/abuild/%s.xml not found.\n" "$TARGET" "${log}" >&2
+		printf "Warning: %s/abuild/%s.xml not found.\n" "${TARGET}" "${log}" >&2
 	fi
 }
 
@@ -631,51 +630,51 @@ build_target()
 {
 	local MAINBOARD=$1
 	local MAINBOARD_LC
-	MAINBOARD_LC=$(echo "$MAINBOARD" | tr '[:upper:]' '[:lower:]')
+	MAINBOARD_LC=$(echo "${MAINBOARD}" | tr '[:upper:]' '[:lower:]')
 
 	# look for config files in the config directory that match the boardname
-	if [[ -n "$( find "$configdir" -maxdepth 1 -name "config.${MAINBOARD_LC}*" -print -quit )" ]]; then
-		for config in "$configdir/config.${MAINBOARD_LC}"*; do
+	if [[ -n "$( find "${configdir}" -maxdepth 1 -name "config.${MAINBOARD_LC}*" -print -quit )" ]]; then
+		for config in "${configdir}/config.${MAINBOARD_LC}"*; do
 			BUILD_NAME="${config##*/}"
 			BUILD_NAME="${BUILD_NAME##config.}"
 			BUILD_NAME=$(echo "${BUILD_NAME}" | tr '[:lower:]' '[:upper:]')
-			printf "%s %s\n" "$BUILD_NAME" "$MAINBOARD"
+			printf "%s %s\n" "${BUILD_NAME}" "${MAINBOARD}"
 			# If the file in configs/ results in the same build_name as the default config
 			# append a '_' to differentiate. Otherwise the default configuration would
 			# override the results.
 			if [[ "${MAINBOARD}" = "${BUILD_NAME}" ]]; then
 				BUILD_NAME=${BUILD_NAME}"_"
 			fi
-			printf "Building config %s\n" "$BUILD_NAME"
-			build_dir=$TARGET/${BUILD_NAME}
-			build_config "$MAINBOARD" "$build_dir" "$BUILD_NAME" "$config"
-			record_mainboard "$BUILD_NAME"
-			remove_target "$BUILD_NAME"
+			printf "Building config %s\n" "${BUILD_NAME}"
+			build_dir="${TARGET}/${BUILD_NAME}"
+			build_config "${MAINBOARD}" "${build_dir}" "${BUILD_NAME}" "${config}"
+			record_mainboard "${BUILD_NAME}"
+			remove_target "${BUILD_NAME}"
 		done
 	fi
 
-	printf "Building board %s (using default config)\n" "$MAINBOARD"
-	build_dir=$TARGET/${MAINBOARD}
-	build_config "$MAINBOARD" "$build_dir" "$MAINBOARD"
-	record_mainboard "$MAINBOARD"
-	remove_target "$MAINBOARD"
+	printf "Building board %s (using default config)\n" "${MAINBOARD}"
+	build_dir="${TARGET}/${MAINBOARD}"
+	build_config "${MAINBOARD}" "${build_dir}" "${MAINBOARD}"
+	record_mainboard "${MAINBOARD}"
+	remove_target "${MAINBOARD}"
 }
 
 remove_target()
 {
-	if [[ "$remove" != "true" ]]; then
+	if [[ "${remove}" != "true" ]]; then
 		return
 	fi
 
 	local BUILD_NAME=$1
 
 	# Save the generated coreboot.rom file of each board.
-	if [[ -r "$TARGET/${BUILD_NAME}/coreboot.rom" ]]; then
-		cp "$TARGET/${BUILD_NAME}/coreboot.rom" \
+	if [[ -r "${TARGET}/${BUILD_NAME}/coreboot.rom" ]]; then
+		cp "${TARGET}/${BUILD_NAME}/coreboot.rom" \
 		   "${BUILD_NAME}_coreboot.rom"
 	fi
 
-	printf "Removing build dir for %s...\n" "$BUILD_NAME"
+	printf "Removing build dir for %s...\n" "${BUILD_NAME}"
 	rm -rf "${TARGET:?}/${BUILD_NAME}"
 
 	return
@@ -706,13 +705,13 @@ Options:\n
     [-n|--name]                   Set build name - also sets xmlfile if not
                                   already set
     [-o|--outdir <path>]          Store build results in path
-                                  (defaults to $TARGET)
+                                  (defaults to ${TARGET})
     [-p|--payloads <dir>]         Use payloads in <dir> to build images
     [-P|--prefix <name>]          File name prefix in CBFS
     [-q|--quiet]                  Print fewer messages
     [-r|--remove]                 Remove output dir after build
     [-R|--root <path>]            Absolute path to coreboot sources
-                                  (defaults to $ROOT)
+                                  (defaults to ${ROOT})
     [--scan-build]                Use clang's static analyzer
     [--skip_set <value>]          Skip building boards with this Kconfig set
     [--skip_unset <value>]        Skip building boards with this Kconfig not set
@@ -724,7 +723,7 @@ Options:\n
     [-x|--chromeos]               Build with CHROMEOS enabled
                                   Skip boards without ChromeOS support
     [-X|--xmlfile <name>]         Set JUnit XML log file filename
-                                  (defaults to $XMLFILE)
+                                  (defaults to ${XMLFILE})
     [-y|--ccache]                 Use ccache
     [-z|--clean]                  Remove build results when finished
     [-Z|--clean-somewhat]         Remove build but keep coreboot.rom + config
@@ -740,7 +739,7 @@ myversion()
 {
 	cat << EOF
 
-coreboot autobuild v$ABUILD_VERSION ($ABUILD_DATE)
+coreboot autobuild v${ABUILD_VERSION} (${ABUILD_DATE})
 
 Copyright (C) 2004 by Stefan Reinauer <stepan@openbios.org>
 Copyright (C) 2006-2010 by coresystems GmbH <info@coresystems.de>
@@ -759,10 +758,10 @@ verbose=false
 
 test -f util/sconfig/sconfig.l && ROOT=$( pwd )
 test -f ../util/sconfig/sconfig.l && ROOT=$( cd .. && pwd )
-test "$ROOT" = "" && ROOT=$( cd ../.. && pwd )
+test "${ROOT}" = "" && ROOT=$( cd ../.. && pwd )
 
 # Look if we have getopt. If not, build it.
-export PATH=$PATH:util/abuild
+export PATH=${PATH}:util/abuild
 getopt - > /dev/null 2>/dev/null || gcc -o util/abuild/getopt util/abuild/getopt.c
 
 # Save command line for xargs parallelization.
@@ -775,16 +774,16 @@ getoptbrand="$(getopt -V)"
 if [[ "${getoptbrand:0:6}" == "getopt" ]]; then
 	# Detected GNU getopt that supports long options.
 	args=$(getopt -l version,verbose,quiet,help,all,target:,board-variant:,payloads:,cpus:,silent,junit,config,loglevel:,remove,prefix:,update,scan-build,ccache,blobs,clang,any-toolchain,clean,clean-somewhat,outdir:,chromeos,xmlfile:,kconfig:,dir:,root:,recursive,checksum:,timeless,exitcode,asserts,name:,skip_set:,skip_unset: -o Vvqhat:b:p:c:sJCl:rP:uyBLAzZo:xX:K:d:R:Ien: -- "$@") || exit 1
-	eval set -- $args
+	eval set -- ${args}
 	retval=$?
 else
 	# Detected non-GNU getopt
 	args=$(getopt Vvqhat:b:p:c:sJCl:rP:uyBLAZzo:xX:K:d:R:Ien: "$@")
-	set -- $args
+	set -- ${args}
 	retval=$?
 fi
 
-if [[ $retval != 0 ]]; then
+if [[ ${retval} != 0 ]]; then
 	myhelp
 	exit 1
 fi
@@ -800,7 +799,7 @@ configoptions=""
 unset testclass
 while true ; do
 	case "$1" in
-		-J|--junit)     shift; mode=junit; rm -f "$XMLFILE" ;;
+		-J|--junit)     shift; mode=junit; rm -f "${XMLFILE}" ;;
 		-t|--target)	shift; target="$1"; shift;;
 		-b|--board-variant)	shift; variant="$1"; shift;;
 		-a|--all)	shift; buildall=true;;
@@ -812,13 +811,13 @@ while true ; do
 		-V|--version)	shift; myversion; exit 0;;
 		-h|--help)	shift; myversion; myhelp; exit 0;;
 		-p|--payloads)  shift; payloads="$1"; shift;;
-		-R|--root)	shift; ROOT="$1"; MAKE="$MAKE -C $1"; shift;;
+		-R|--root)	shift; ROOT="$1"; MAKE="${MAKE} -C $1"; shift;;
 		-c|--cpus)	shift
 			export MAKEFLAGS="-j $1"
 			cpus=$1
-			test "$MAKEFLAGS" == "-j max" && export MAKEFLAGS="-j" && cpuconfig=" in parallel"
+			test "${MAKEFLAGS}" == "-j max" && export MAKEFLAGS="-j" && cpuconfig=" in parallel"
 			test "$1" == "1" && cpuconfig=" on 1 cpu"
-			expr "$1" : '-\?[0-9]\+$' > /dev/null && test "0$1" -gt 1 && cpuconfig=" on $1 cpus in parallel"
+			expr "$1" : '-\?[0-9]\+$' > /dev/null && test "0$1" -gt 1 && cpuconfig=" on ${1} cpus in parallel"
 			shift;;
 		# obsolete option
 		-s|--silent)    shift;;
@@ -925,13 +924,13 @@ if [[ -n "$1" ]]; then
 	printf "Invalid option '%s'\n\n" "$1"; myhelp; exit 1;
 fi
 
-if [[ -z "$TARGET" ]] || [[ "$TARGET" = "/" ]]; then
 	printf "Please specify a valid, non-root build directory.\n"
+if [[ -z "${TARGET}" ]] || [[ "${TARGET}" = "/" ]]; then
 	exit 1
 fi
 
-if ! mkdir -p "$TARGET"; then
-	printf "Unable to create build directory\\n"
+if ! mkdir -p "${TARGET}"; then
+	printf "Unable to create build directory\n"
 	exit 1
 fi
 
@@ -940,34 +939,34 @@ if echo "${skipconfig_set}${skipconfig_unset}" | grep -q "CONFIG_" >/dev/null 2>
 	exit 1
 fi
 
-customizing=$(echo "$customizing" | cut -c3-)
-if [[ -z "$customizing" ]]; then
+customizing=$(echo "${customizing}" | cut -c3-)
+if [[ -z "${customizing}" ]]; then
 	customizing="Default configuration"
 fi
 customizing="Config: ${customizing}"
 FAILED_BOARDS="$(realpath ${TARGET}/failed_boards)"
 PASSED_BOARDS="$(realpath ${TARGET}/passing_boards)"
 
-stats_archive="$TARGET/statistics.tar"
+stats_archive="${TARGET}/statistics.tar"
 
 # Generate a single xcompile for all boards
 export xcompile="${TARGET}/xcompile"
 
-if [[ "$recursive" = "false" ]]; then
+if [[ "${recursive}" = "false" ]]; then
 	rm -f "${xcompile}"
-	$MAKE -C"${ROOT}" obj="$TARGET/temp" objutil="$TARGET/sharedutils" UPDATED_SUBMODULES=1 "${xcompile}" || exit 1
-	rm -f "$FAILED_BOARDS" "$PASSED_BOARDS"
+	${MAKE} -C"${ROOT}" obj="${TARGET}/temp" objutil="${TARGET}/sharedutils" UPDATED_SUBMODULES=1 "${xcompile}" || exit 1
+	rm -f "${FAILED_BOARDS}" "${PASSED_BOARDS}"
 
 	# Initialize empty statistics archive
 	tar -cf "${stats_archive}" "${xcompile}" 2> /dev/null
 fi
 
 USE_XARGS=0
-if [[ "$cpus" != "1" ]]; then
+if [[ "${cpus}" != "1" ]]; then
 	# Limit to 32 parallel builds for now.
 	# Thrashing all caches because we run
 	# 160 abuilds in parallel is no fun.
-	if [[ "$cpus" = "max" ]]; then
+	if [[ "${cpus}" = "max" ]]; then
 		cpus=32
 	fi
 	# Test if xargs supports the non-standard -P flag
@@ -975,13 +974,13 @@ if [[ "$cpus" != "1" ]]; then
 	printf "\n" | xargs -P ${cpus:-0} -n 1 printf "%s\n" 2>/dev/null >/dev/null && USE_XARGS=1
 fi
 
-if [[ "$USE_XARGS" = "0" ]]; then
-test "$MAKEFLAGS" == "" && test "$cpus" != "" && export MAKEFLAGS="-j $cpus"
-export MAKEFLAGS="$MAKEFLAGS UPDATED_SUBMODULES=1" # no need to re-download
+if [[ "${USE_XARGS}" = "0" ]]; then
+test "${MAKEFLAGS}" == "" && test "${cpus}" != "" && export MAKEFLAGS="-j ${cpus}"
+export MAKEFLAGS="${MAKEFLAGS} UPDATED_SUBMODULES=1" # no need to re-download
 build_targets()
 {
 	local targets=${*-$(get_mainboards)}
-	for MAINBOARD in $targets; do
+	for MAINBOARD in ${targets}; do
 		build_target "${MAINBOARD}"
 	done
 }
@@ -997,48 +996,48 @@ build_targets()
 	local targets=${*-$(get_mainboards)}
 	# seed shared utils
 	TMPCFG=$(mktemp)
-	printf "%s" "$configoptions" > "$TMPCFG"
-	$MAKE -j "$cpus" DOTCONFIG="$TMPCFG" obj="$TARGET/temp" objutil="$TARGET/sharedutils" olddefconfig 2>/dev/null
+	printf "%s" "${configoptions}" > "${TMPCFG}"
+	${MAKE} -j "${cpus}" DOTCONFIG="${TMPCFG}" obj="${TARGET}/temp" objutil="${TARGET}/sharedutils" olddefconfig 2>/dev/null
 	BUILDPREFIX=
-	if [[ "$scanbuild" = "true" ]]; then
-		scanbuild_out=$TARGET/sharedutils-scanbuild
+	if [[ "${scanbuild}" = "true" ]]; then
+		scanbuild_out="${TARGET}/sharedutils-scanbuild"
 		rm -rf "${scanbuild_out}"
 		BUILDPREFIX="scan-build -o ${scanbuild_out}tmp"
 	fi
-	mkdir -p "$TARGET/abuild"
-	ABSPATH="$(cd "$TARGET/abuild" && pwd)"
-	local XMLFILE="$ABSPATH/__util.xml"
+	mkdir -p "${TARGET}/abuild"
+	ABSPATH="$(cd "${TARGET}/abuild" && pwd)"
+	local XMLFILE="${ABSPATH}/__util.xml"
 	rm -f "${XMLFILE}"
 	stime=$(add_timestamp)
-	$BUILDPREFIX "$MAKE" -j "$cpus" DOTCONFIG="$TMPCFG" obj="$TARGET/temp" objutil="$TARGET/sharedutils" tools > "$TARGET/sharedutils/make.log" 2>&1
+	${BUILDPREFIX} "${MAKE}" -j "${cpus}" DOTCONFIG="${TMPCFG}" obj="${TARGET}/temp" objutil="${TARGET}/sharedutils" tools > "${TARGET}/sharedutils/make.log" 2>&1
 	local ret=$?
 	etime=$(add_timestamp)
-	local duration=$(ts_delta_seconds $stime $etime)
+	local duration=$(ts_delta_seconds ${stime} ${etime})
 
-	junit " <testcase classname='util' name='all' time='$duration' >"
-	if [[ $ret -eq 0 ]]; then
+	junit " <testcase classname='util' name='all' time='${duration}' >"
+	if [[ ${ret} -eq 0 ]]; then
 		junit "<system-out>"
-		junitfile "$TARGET/sharedutils/make.log"
+		junitfile "${TARGET}/sharedutils/make.log"
 		junit "</system-out>"
 		junit "</testcase>"
 	else
 		junit "<failure type='BuildFailed'>"
-		junitfile "$TARGET/sharedutils/make.log"
+		junitfile "${TARGET}/sharedutils/make.log"
 		junit "</failure>"
 		junit "</testcase>"
-		echo "Shared Utilities - Log: $TARGET/sharedutils/make.log" >> "$FAILED_BOARDS"
-		rm "$TMPCFG"
+		echo "Shared Utilities - Log: ${TARGET}/sharedutils/make.log" >> "${FAILED_BOARDS}"
+		rm "${TMPCFG}"
 		return
 	fi
 
-	if [[ "$scanbuild" = "true" ]]; then
-		mv "${scanbuild_out}tmp"/* "${scanbuild_out}"
+	if [[ "${scanbuild}" = "true" ]]; then
+		mv "${scanbuild_out}tmp/"* "${scanbuild_out}"
 		rmdir "${scanbuild_out}tmp"
 	fi
-	rm -rf "$TARGET/temp" "$TMPCFG"
-	num_targets=$(wc -w <<<"$targets")
 	cpus_per_target=$(((${cpus:-1} + num_targets - 1) / num_targets))
-	printf "%s\n" "$targets" | xargs -P ${cpus:-0} -n 1 "$0" "${cmdline[@]}" -I -c "$cpus_per_target" -t
+	printf "%s\n" "${targets}" | xargs -P ${cpus:-0} -n 1 "$0" "${cmdline[@]}" -I -c "${cpus_per_target}" -t
+	rm -rf "${TARGET}/temp" "${TMPCFG}"
+	num_targets=$(wc -w <<<"${targets}")
 }
 fi
 
@@ -1059,43 +1058,43 @@ if [[ "$target" != "" ]]; then
 	build_srcdir="$(mainboard_directory "${MAINBOARD}")"
 	if [[ "$(echo "${MAINBOARD}" | wc -w)" -gt 1 ]]; then
 		build_targets "${MAINBOARD}"
-	elif [[ ! -r "$ROOT/src/mainboard/${build_srcdir}" ]]; then
+	elif [[ ! -r "${ROOT}/src/mainboard/${build_srcdir}" ]]; then
 		printf "No such target: %s\n" "${MAINBOARD}"
 		exit 1
 	else
 		build_target "${MAINBOARD}"
-		XMLFILE=$REAL_XMLFILE
+		XMLFILE=${REAL_XMLFILE}
 	fi
 else
 	build_targets
-	rm -f "$REAL_XMLFILE"
-	XMLFILE="$REAL_XMLFILE"
+	rm -f "${REAL_XMLFILE}"
+	XMLFILE="${REAL_XMLFILE}"
 	junit '<?xml version="1.0" encoding="utf-8"?>'
 	junit '<testsuite>'
 	if [[ "$mode" != "text" ]]; then
-		for xmlfile in $TARGET/abuild/*_*.xml; do
-			cat "$xmlfile" >> "$REAL_XMLFILE"
+		for xmlfile in ${TARGET}/abuild/*_*.xml; do
+			cat "${xmlfile}" >> "${REAL_XMLFILE}"
 		done
 	fi
-	XMLFILE=$REAL_XMLFILE
+	XMLFILE=${REAL_XMLFILE}
 fi
 junit '</testsuite>'
 
-if [[ "$recursive" = "false" ]]; then
+if [[ "${recursive}" = "false" ]]; then
 
 	# Print the list of failed configurations
-	if [[ -f "$FAILED_BOARDS" ]]; then
-		printf "%s configuration(s) failed:\n" "$( wc -l < "$FAILED_BOARDS" )"
-		cat "$FAILED_BOARDS"
+	if [[ -f "${FAILED_BOARDS}" ]]; then
+		printf "%s configuration(s) failed:\n" "$( wc -l < "${FAILED_BOARDS}" )"
+		cat "${FAILED_BOARDS}"
 		printf "\n"
-		if [[ "$exitcode" != "0" ]]; then
+		if [[ "${exitcode}" != "0" ]]; then
 			failed=1
 		fi
-	elif [[ -f "$PASSED_BOARDS" ]]; then
-		printf "All %s tested configurations passed.\n" "$( wc -l < "$PASSED_BOARDS" )"
+	elif [[ -f "${PASSED_BOARDS}" ]]; then
+		printf "All %s tested configurations passed.\n" "$( wc -l < "${PASSED_BOARDS}" )"
 	else
 		printf "No boards tested.\n"
 	fi
 fi
 
-exit $failed
+exit ${failed}

From 82dea9d6d1e0ba0f63374ee7f9669900ae4ab8d0 Mon Sep 17 00:00:00 2001
From: Martin Roth <gaumless@gmail.com>
Date: Sun, 20 Apr 2025 13:47:05 -0600
Subject: [PATCH 0984/3886] util/abuild: Disable shellcheck warning on
 interrupt()

Shellcheck warns that the interrupt() function is unreachable, but it's
set to run on CTL-C. Disable the warning.

Change-Id: I0b850573964c732b1a3875dfdc7c1f0d406bac1a
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87371
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 util/abuild/abuild | 1 +
 1 file changed, 1 insertion(+)

diff --git a/util/abuild/abuild b/util/abuild/abuild
index a9525f8b1f..9c48bf5fbb 100755
--- a/util/abuild/abuild
+++ b/util/abuild/abuild
@@ -103,6 +103,7 @@ ts_basetime_str=$(date -u --date=@${ts_exec_shell})
 
 trap interrupt INT
 
+# shellcheck disable=SC2317 # Disable unreacheable code warning. It's a trap!
 interrupt()
 {
 	printf "\n%s: execution interrupted manually.\n" "$0"

From d88ea14e8dc13c2b1587dac72e8b4813299476bd Mon Sep 17 00:00:00 2001
From: Martin Roth <gaumless@gmail.com>
Date: Sun, 20 Apr 2025 13:47:30 -0600
Subject: [PATCH 0985/3886] util/abuild: Remove unused debug() function

Change-Id: I30951f232da5dd0eeea536945fcc85d0748a019b
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87372
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 util/abuild/abuild | 8 +-------
 1 file changed, 1 insertion(+), 7 deletions(-)

diff --git a/util/abuild/abuild b/util/abuild/abuild
index 9c48bf5fbb..ee4aba65a2 100755
--- a/util/abuild/abuild
+++ b/util/abuild/abuild
@@ -113,11 +113,6 @@ interrupt()
 	exit 1
 }
 
-debug()
-{
-	[[ "${verbose}" == "true" ]] && printf "%s\n" "$*"
-}
-
 junit()
 {
 	[[ "${mode}" == "junit" ]] && printf "%s\n" "$*" >> "${XMLFILE}"
@@ -755,7 +750,6 @@ EOF
 # default options
 target=""
 buildall=false
-verbose=false
 
 test -f util/sconfig/sconfig.l && ROOT=$( pwd )
 test -f ../util/sconfig/sconfig.l && ROOT=$( cd .. && pwd )
@@ -807,7 +801,7 @@ while true ; do
 		-d|--dir)	shift; configdir="$1"; shift;;
 		-e|--exitcode)	shift; exitcode=1;;
 		-r|--remove)	shift; remove=true;;
-		-v|--verbose)	shift; verbose=true; verboseopt='V=1';;
+		-v|--verbose)	shift; verboseopt='V=1';;
 		-q|--quiet)	shift; quiet=true;;
 		-V|--version)	shift; myversion; exit 0;;
 		-h|--help)	shift; myversion; myhelp; exit 0;;

From ad19c94d87d81ddd4c1f6897240f00af3339e9ce Mon Sep 17 00:00:00 2001
From: Martin Roth <gaumless@gmail.com>
Date: Sun, 20 Apr 2025 13:57:29 -0600
Subject: [PATCH 0986/3886] util/abuild: Fix shellcheck warnings about local
 vars

This fixes the shellcheck warnings about declaring and using local
variables at the same time.

Change-Id: Ia16911c9ea0a1b32c3480a93ca0e53a409e80d22
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87373
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 util/abuild/abuild | 19 +++++++++++++------
 1 file changed, 13 insertions(+), 6 deletions(-)

diff --git a/util/abuild/abuild b/util/abuild/abuild
index ee4aba65a2..6199b7d2b1 100755
--- a/util/abuild/abuild
+++ b/util/abuild/abuild
@@ -372,9 +372,13 @@ check_config()
 # Counting microseconds since start of shell
 add_timestamp()
 {
-	local now=${EPOCHREALTIME}
-	local seconds=$(echo ${now} | cut -f 1 -d '.')
-	local usecs=$(echo ${now} | cut -f 2 -d '.')
+	local now
+	local seconds
+	local usecs
+
+	now=${EPOCHREALTIME}
+	seconds=$(echo ${now} | cut -f 1 -d '.')
+	usecs=$(echo ${now} | cut -f 2 -d '.')
 	seconds=$(( seconds - ts_exec_shell ))
 	usecs=$(( seconds * 1000 * 1000 + 10#$usecs ))
 	printf "%s" ${usecs}
@@ -974,7 +978,8 @@ test "${MAKEFLAGS}" == "" && test "${cpus}" != "" && export MAKEFLAGS="-j ${cpus
 export MAKEFLAGS="${MAKEFLAGS} UPDATED_SUBMODULES=1" # no need to re-download
 build_targets()
 {
-	local targets=${*-$(get_mainboards)}
+	local targets
+	targets=${*-$(get_mainboards)}
 	for MAINBOARD in ${targets}; do
 		build_target "${MAINBOARD}"
 	done
@@ -987,6 +992,8 @@ build_targets()
 	local etime
 	local num_targets
 	local cpus_per_target
+	local XMLFILE
+	local duration
 
 	local targets=${*-$(get_mainboards)}
 	# seed shared utils
@@ -1001,13 +1008,13 @@ build_targets()
 	fi
 	mkdir -p "${TARGET}/abuild"
 	ABSPATH="$(cd "${TARGET}/abuild" && pwd)"
-	local XMLFILE="${ABSPATH}/__util.xml"
+	XMLFILE="${ABSPATH}/__util.xml"
 	rm -f "${XMLFILE}"
 	stime=$(add_timestamp)
 	${BUILDPREFIX} "${MAKE}" -j "${cpus}" DOTCONFIG="${TMPCFG}" obj="${TARGET}/temp" objutil="${TARGET}/sharedutils" tools > "${TARGET}/sharedutils/make.log" 2>&1
 	local ret=$?
 	etime=$(add_timestamp)
-	local duration=$(ts_delta_seconds ${stime} ${etime})
+	duration=$(ts_delta_seconds "${stime}" "${etime}")
 
 	junit " <testcase classname='util' name='all' time='${duration}' >"
 	if [[ ${ret} -eq 0 ]]; then

From 52b932df3b32505b9534546e053727a04259bc53 Mon Sep 17 00:00:00 2001
From: Martin Roth <gaumless@gmail.com>
Date: Sun, 20 Apr 2025 14:03:19 -0600
Subject: [PATCH 0987/3886] util/abuild: Group printfs to timestamps file
 together

This fixes the abuild warning/suggestion.

Change-Id: I3a28811becfde69c3e539406bde5938445f16c29
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87374
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 util/abuild/abuild | 12 +++++++-----
 1 file changed, 7 insertions(+), 5 deletions(-)

diff --git a/util/abuild/abuild b/util/abuild/abuild
index 6199b7d2b1..4a01737af0 100755
--- a/util/abuild/abuild
+++ b/util/abuild/abuild
@@ -426,11 +426,13 @@ compile_target()
 	cd "${build_dir}" || return $?
 
 	timestamps="abuild.timestamps"
-	printf "Build started %s\n" "${ts_basetime_str}" > "${timestamps}"
-	printf "BASETIME_SECONDS %d\n" ${ts_exec_shell} >> "${timestamps}"
-	printf "TS_0 %d\n" ${ts_0} >> "${timestamps}"
-	printf "TS_1 %d\n" ${ts_1} >> "${timestamps}"
-	printf "TS_2 %d\n" ${ts_2} >> "${timestamps}"
+	{
+		printf "Build started %s\n" "${ts_basetime_str}"
+		printf "BASETIME_SECONDS %d\n" ${ts_exec_shell}
+		printf "TS_0 %d\n" ${ts_0}
+		printf "TS_1 %d\n" ${ts_1}
+		printf "TS_2 %d\n" ${ts_2}
+	} > "${timestamps}"
 
 	duration=$(ts_delta_seconds ${ts_0} ${ts_2})
 	duration_str=$(ts_delta_string ${ts_0} ${ts_2})

From b128abcdadcdfb9e9ee4c3daa30949ab3aab5184 Mon Sep 17 00:00:00 2001
From: Martin Roth <gaumless@gmail.com>
Date: Sun, 20 Apr 2025 14:10:55 -0600
Subject: [PATCH 0988/3886] util/abuild: Add quotes around variables

Change-Id: I8822c8a5004b9b37cd3a7c4a981b52e8fbeba0e1
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87375
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 util/abuild/abuild | 34 +++++++++++++++++-----------------
 1 file changed, 17 insertions(+), 17 deletions(-)

diff --git a/util/abuild/abuild b/util/abuild/abuild
index 4a01737af0..e2ce6dcd46 100755
--- a/util/abuild/abuild
+++ b/util/abuild/abuild
@@ -428,14 +428,14 @@ compile_target()
 	timestamps="abuild.timestamps"
 	{
 		printf "Build started %s\n" "${ts_basetime_str}"
-		printf "BASETIME_SECONDS %d\n" ${ts_exec_shell}
-		printf "TS_0 %d\n" ${ts_0}
-		printf "TS_1 %d\n" ${ts_1}
-		printf "TS_2 %d\n" ${ts_2}
+		printf "BASETIME_SECONDS %d\n" "${ts_exec_shell}"
+		printf "TS_0 %d\n" "${ts_0}"
+		printf "TS_1 %d\n" "${ts_1}"
+		printf "TS_2 %d\n" "${ts_2}"
 	} > "${timestamps}"
 
-	duration=$(ts_delta_seconds ${ts_0} ${ts_2})
-	duration_str=$(ts_delta_string ${ts_0} ${ts_2})
+	duration=$(ts_delta_seconds "${ts_0}" "${ts_2}")
+	duration_str=$(ts_delta_string "${ts_0}" "${ts_2}")
 	junit " <testcase classname='${TESTRUN}${testclass/#/.}' name='${BUILD_NAME}' time='${duration}' >"
 
 	if [[ ${MAKE_FAILED} -eq 0 ]]; then
@@ -470,14 +470,14 @@ compile_target()
 	if [[ -f ${build_dir}/ccache.stats ]]; then
 		stats_files="${stats_files} ${build_dir}/ccache.stats"
 	fi
-	flock -F -w 0.1 ${TARGET}/.statslock tar -rf ${stats_archive} ${stats_files} 2> /dev/null
+	flock -F -w 0.1 "${TARGET}/.statslock" tar -rf "${stats_archive}" "${stats_files}" 2> /dev/null
 
 	if [[ "${clean_work}" = "true" ]]; then
 		rm -rf "${build_dir}"
 	fi
 	if [[ "${clean_objs}" = "true" ]]; then
-		find ${build_dir} \! \( -name coreboot.rom -o -name config.h -o -name config.build -o -name make.log \) -type f -exec rm {} +
-		find ${build_dir} -type d -exec rmdir -p {} + 2>/dev/null
+		find "${build_dir}" \! \( -name coreboot.rom -o -name config.h -o -name config.build -o -name make.log \) -type f -exec rm {} +
+		find "${build_dir}" -type d -exec rmdir -p {} + 2>/dev/null
 	fi
 	return ${MAKE_FAILED}
 }
@@ -527,7 +527,7 @@ build_config()
 	if [[ "${chromeos}" = false ]]; then
 		# Skip this rule for configs created from templates that already
 		# come with CHROMEOS enabled.
-		grep -q "^CONFIG_CHROMEOS=y" ${config_file:-/dev/null} || \
+		grep -q "^CONFIG_CHROMEOS=y" "${config_file:-/dev/null}" || \
 		check_config "${build_dir}" "ChromeOS" "CONFIG_CHROMEOS=y" negate
 		local FORCE_ENABLED_CROS=$?
 	else
@@ -607,7 +607,7 @@ EOF
 		fi
 		compile_target "${BUILD_NAME}"
 		if [[ "${scanbuild}" = "true" ]]; then
-			mv "${scanbuild_out}"tmp/* "${scanbuild_out}"
+			mv "${scanbuild_out}tmp"/* "${scanbuild_out}"
 			rmdir "${scanbuild_out}tmp"
 		fi
 	fi
@@ -945,8 +945,8 @@ if [[ -z "${customizing}" ]]; then
 	customizing="Default configuration"
 fi
 customizing="Config: ${customizing}"
-FAILED_BOARDS="$(realpath ${TARGET}/failed_boards)"
-PASSED_BOARDS="$(realpath ${TARGET}/passing_boards)"
+FAILED_BOARDS="$(realpath "${TARGET}/failed_boards")"
+PASSED_BOARDS="$(realpath "${TARGET}/passing_boards")"
 
 stats_archive="${TARGET}/statistics.tar"
 
@@ -972,7 +972,7 @@ if [[ "${cpus}" != "1" ]]; then
 	fi
 	# Test if xargs supports the non-standard -P flag
 	# FIXME: disabled until we managed to eliminate all the make(1) quirks
-	printf "\n" | xargs -P ${cpus:-0} -n 1 printf "%s\n" 2>/dev/null >/dev/null && USE_XARGS=1
+	printf "\n" | xargs -P "${cpus:-0}" -n 1 printf "%s\n" 2>/dev/null >/dev/null && USE_XARGS=1
 fi
 
 if [[ "${USE_XARGS}" = "0" ]]; then
@@ -1039,7 +1039,7 @@ build_targets()
 		rmdir "${scanbuild_out}tmp"
 	fi
 	cpus_per_target=$(((${cpus:-1} + num_targets - 1) / num_targets))
-	printf "%s\n" "${targets}" | xargs -P ${cpus:-0} -n 1 "$0" "${cmdline[@]}" -I -c "${cpus_per_target}" -t
+	printf "%s\n" "${targets}" | xargs -P "${cpus:-0}" -n 1 "$0" "${cmdline[@]}" -I -c "${cpus_per_target}" -t
 	rm -rf "${TARGET}/temp" "${TMPCFG}"
 	num_targets=$(wc -w <<<"${targets}")
 }
@@ -1075,8 +1075,8 @@ else
 	XMLFILE="${REAL_XMLFILE}"
 	junit '<?xml version="1.0" encoding="utf-8"?>'
 	junit '<testsuite>'
-	if [[ "$mode" != "text" ]]; then
-		for xmlfile in ${TARGET}/abuild/*_*.xml; do
+	if [[ "${mode}" != "text" ]]; then
+		for xmlfile in "${TARGET}"/abuild/*_*.xml; do
 			cat "${xmlfile}" >> "${REAL_XMLFILE}"
 		done
 	fi

From a8e1113e3b6d8e92df05227974997d8f177479d2 Mon Sep 17 00:00:00 2001
From: Martin Roth <gaumless@gmail.com>
Date: Sun, 20 Apr 2025 14:11:58 -0600
Subject: [PATCH 0989/3886] util/abuild: Check functions directly instead of
 with $?

Change-Id: I5d28e8f9533602a2ffbacd858c7380af08b56788
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87376
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 util/abuild/abuild | 9 +++------
 1 file changed, 3 insertions(+), 6 deletions(-)

diff --git a/util/abuild/abuild b/util/abuild/abuild
index e2ce6dcd46..ad708d7b4b 100755
--- a/util/abuild/abuild
+++ b/util/abuild/abuild
@@ -535,24 +535,21 @@ build_config()
 	fi
 
 	if [[ "${clang}" = true ]]; then
-		check_config "${build_dir}" "clang" "CONFIG_COMPILER_LLVM_CLANG=y"
-		if [[ $? -ne 0 ]]; then
+		if ! check_config "${build_dir}" "clang" "CONFIG_COMPILER_LLVM_CLANG=y"; then
 			printf "%s doesn't support clang, skipping.\n" "${MAINBOARD}"
 			return
 		fi
 	fi
 
 	if [[ -n "${skipconfig_set}" ]]; then
-		check_config "${build_dir}" "config value" "CONFIG_${skipconfig_set}=y" negate
-		if [[ $? -ne 0 ]]; then
+		if ! check_config "${build_dir}" "config value" "CONFIG_${skipconfig_set}=y" negate; then
 			printf "%s has %s set. Skipping at user's request.\n" "${MAINBOARD}" "${skipconfig_set}"
 			return
 		fi
 	fi
 
 	if [[ -n "${skipconfig_unset}" ]]; then
-		check_config "${build_dir}" "config value" "CONFIG_${skipconfig_unset}=y"
-		if [[ $? -ne 0 ]]; then
+		if ! check_config "${build_dir}" "config value" "CONFIG_${skipconfig_unset}=y"; then
 			printf "%s does not have %s set. Skipping at user's request.\n" "${MAINBOARD}" "${skipconfig_unset}"
 			return
 		fi

From 8504c796fc45cc024199f6ea4d200897d156cb4a Mon Sep 17 00:00:00 2001
From: Martin Roth <gaumless@gmail.com>
Date: Sun, 20 Apr 2025 14:16:24 -0600
Subject: [PATCH 0990/3886] util/abuild: Remove obsolete FIXME

Change-Id: I51ca0acc18d052f464debaec96154ed07f639355
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87377
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
---
 util/abuild/abuild | 1 -
 1 file changed, 1 deletion(-)

diff --git a/util/abuild/abuild b/util/abuild/abuild
index ad708d7b4b..2a37ca8c6e 100755
--- a/util/abuild/abuild
+++ b/util/abuild/abuild
@@ -968,7 +968,6 @@ if [[ "${cpus}" != "1" ]]; then
 		cpus=32
 	fi
 	# Test if xargs supports the non-standard -P flag
-	# FIXME: disabled until we managed to eliminate all the make(1) quirks
 	printf "\n" | xargs -P "${cpus:-0}" -n 1 printf "%s\n" 2>/dev/null >/dev/null && USE_XARGS=1
 fi
 

From 902288db225f411c610e27eb2f1814a7f415a822 Mon Sep 17 00:00:00 2001
From: Martin Roth <gaumless@gmail.com>
Date: Sun, 20 Apr 2025 11:48:12 -0600
Subject: [PATCH 0991/3886] util/abuild: Update version and date string

Increment the version number for the current changes.

Change-Id: Iec94067e34292df3b85744a820ace4aa198a6322
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87378
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
---
 util/abuild/abuild | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/util/abuild/abuild b/util/abuild/abuild
index 2a37ca8c6e..f1c7edc2a8 100755
--- a/util/abuild/abuild
+++ b/util/abuild/abuild
@@ -11,8 +11,8 @@
 
 #set -x # Turn echo on....
 
-ABUILD_DATE="Nov 18, 2023"
-ABUILD_VERSION="0.11.03"
+ABUILD_DATE="Apr 20, 2025"
+ABUILD_VERSION="0.11.04"
 
 TOP=${PWD}
 

From 64fe6fd94a3fde6b80c4112b81b9e0255e4e31d6 Mon Sep 17 00:00:00 2001
From: Martin Roth <gaumless@gmail.com>
Date: Sun, 20 Apr 2025 13:54:03 -0600
Subject: [PATCH 0992/3886] util/abuild: fix TODO and update targets variable
 to an array

Use an array instead of a variable as suggested by the TODO, so we can
remove the shellcheck disable and fix the warning.

Change-Id: I5e872ebe350f339b932a711fe7f6a68743f002ed
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87379
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
---
 util/abuild/abuild | 26 +++++++++++++++++---------
 1 file changed, 17 insertions(+), 9 deletions(-)

diff --git a/util/abuild/abuild b/util/abuild/abuild
index f1c7edc2a8..5b87cbc2e7 100755
--- a/util/abuild/abuild
+++ b/util/abuild/abuild
@@ -176,22 +176,30 @@ mainboard_vendor()
 # If a directory contains multiple boards, returns them all.
 normalize_target()
 {
-	# TODO: Change 'targets' variable to an array
-	local targets
+	local target_input=$1
+	local -a targets=() # Initialize as an empty array
 	local VARIANT_UC
+	local i
 
 	VARIANT_UC=$(echo "${variant}" | tr '[:lower:]' '[:upper:]' | tr '-' '_')
 
-	targets=$(get_mainboards "$1")
-	if [[ -n "${targets}" ]]; then
-		# shellcheck disable=SC2086
-		targets="$(grep "${VARIANT_UC}\$" <<< ${targets})"
-		echo "${targets}"
+	# Read output of get_mainboards into the targets array
+	mapfile -t targets < <(get_mainboards "${target_input}")
+	if [[ ${#targets[@]} -gt 0 ]]; then
+		# Filter the array using grep
+		mapfile -t targets < <(printf '%s\n' "${targets[@]}" | grep "${VARIANT_UC}\$")
+		# Print the filtered targets, one per line
+		if [[ ${#targets[@]} -gt 0 ]]; then
+			printf '%s\n' "${targets[@]}"
+		fi
 		return
 	fi
 
-	targets=$(echo "$1" | tr ',' ' ')
-	for i in ${targets}; do
+	# Handle comma-separated input string
+	IFS=',' read -ra targets <<< "${target_input}"
+	for i in "${targets[@]}"; do
+		# Trim whitespace if necessary (read -ra might include it)
+		i=$(echo "$i" | xargs)
 		if [[ -n "$(mainboard_directory "${i}")" ]]; then
 			printf "%s\n" "${i}"
 		else

From 2c986d016e58625494e3f8c6d8ec8554c17f4b6c Mon Sep 17 00:00:00 2001
From: Subrata Banik <subratabanik@google.com>
Date: Mon, 12 May 2025 16:03:45 +0530
Subject: [PATCH 0993/3886] MAINTAINERS: Add Google Bluey and Qualcomm SOC
 maintainers

This commit updates the MAINTAINERS file to reflect active
maintenance for the Google Bluey mainboard and Qualcomm SOCs.

Specifically:
- A new section `GOOGLE BLUEY MAINBOARDS` is added, assigning
  Subrata Banik and Kapil Porwal as maintainers for
  `src/mainboard/google/bluey/`. This is for the newly
  supported Bluey platform.

- A new section `QUALCOMM SOCS` is added, assigning Subrata
  Banik and Kapil Porwal as maintainers for `src/soc/qualcomm/`.
  Consequently, `src/soc/qualcomm/` is removed from the
  `ORPHANED ARM SOCS` section. This establishes active support
  for Qualcomm SOCs within coreboot.

Change-Id: I355fcf7a7c6c865a1cc3c405d5f8d03747b2d9fc
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87645
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
---
 MAINTAINERS | 11 +++++++++--
 1 file changed, 9 insertions(+), 2 deletions(-)

diff --git a/MAINTAINERS b/MAINTAINERS
index 203868e252..98fe4f2ee8 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -329,7 +329,10 @@ M:	Angel Pons <th3fanbus@gmail.com>
 S:	Maintained
 F:	src/mainboard/gigabyte/ga-h61m-series/
 
-
+GOOGLE BLUEY MAINBOARDS
+M:	Subrata Banik <subratabanik@google.com>
+M:	Kapil Porwal <kapilporwal@google.com>
+F:	src/mainboard/google/bluey/
 
 GOOGLE REX MAINBOARDS
 M:	Subrata Banik <subratabanik@google.com>
@@ -977,11 +980,15 @@ S:	Maintained
 F:	src/soc/mediatek/mt8192/
 F:	src/vendorcode/mediatek/mt8192/
 
+QUALCOMM SOCS
+M:	Subrata Banik <subratabanik@google.com>
+M:	Kapil Porwal <kapilporwal@google.com>
+F:	src/soc/qualcomm/
+
 ORPHANED ARM SOCS
 S:	Orphan
 F:	src/cpu/armltd/
 F:	src/soc/ti/
-F:	src/soc/qualcomm/
 F:	src/soc/samsung/
 F:	util/exynos/
 F:	util/ipqheader/

From 5cf460dce9e479039fdf4f77a6cdab22b54bbd17 Mon Sep 17 00:00:00 2001
From: Shunxi Zhang <ot_shunxi.zhang@mediatek.com>
Date: Fri, 9 May 2025 18:39:36 +0800
Subject: [PATCH 0994/3886] soc/mediatek/mt8196: Fix RTC protection register
 unlock failure

Add flow of checking RTC unlock protection state after RTC protection
unlock sequence. On failure, retry this flow several times.
Additionally, change the time of CBUSY maximum timeout to 1 second.

BRANCH=rauru
BUG=b:392197855
TEST=emerge-rauru coreboot chromeos-bootimage, when suspend/warmboot/
coldboot, RTC boots and works normally.
After 15 tests, the boot time will increase by approximately 1.3ms from
890.508ms to 891.832ms

Signed-off-by: Shunxi Zhang <ot_shunxi.zhang@mediatek.com>
Change-Id: Id4d537d9c60dc7520c446f1816ef95f9f1e0ff80
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87638
Reviewed-by: Shunxi Zhang <ot_shunxi.zhang@mediatek.corp-partner.google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 .../mediatek/mt8196/include/soc/mt6685_rtc.h  |  5 ++
 src/soc/mediatek/mt8196/include/soc/rtc.h     |  4 +-
 src/soc/mediatek/mt8196/mt6685_rtc.c          | 54 ++++++++++++++-----
 3 files changed, 49 insertions(+), 14 deletions(-)

diff --git a/src/soc/mediatek/mt8196/include/soc/mt6685_rtc.h b/src/soc/mediatek/mt8196/include/soc/mt6685_rtc.h
index e46fd90ff6..612d2d424e 100644
--- a/src/soc/mediatek/mt8196/include/soc/mt6685_rtc.h
+++ b/src/soc/mediatek/mt8196/include/soc/mt6685_rtc.h
@@ -49,6 +49,11 @@
 
 #define RG_FQMTR_DATA			0x54a
 
+#define RTC_SPAR_MACRO			0x5d8
+#define RTC_SPAR_PROT_STAT_SHIFT	6
+#define RTC_SPAR_PROT_STAT_MASK		0x3
+#define RTC_PROT_UNLOCK_SUCCESS		0x3
+
 #define RG_FQMTR_CLK_CK_PDN_SET		0x10c
 #define RG_FQMTR_CLK_CK_PDN_MASK	0x1
 #define RG_FQMTR_CLK_CK_PDN_SHIFT	5
diff --git a/src/soc/mediatek/mt8196/include/soc/rtc.h b/src/soc/mediatek/mt8196/include/soc/rtc.h
index b315998713..f45e4384ce 100644
--- a/src/soc/mediatek/mt8196/include/soc/rtc.h
+++ b/src/soc/mediatek/mt8196/include/soc/rtc.h
@@ -12,6 +12,7 @@
 #include <soc/rtc_common.h>
 #include <soc/rtc_reg_common.h>
 #include <stdbool.h>
+#include <timer.h>
 #include <types.h>
 
 /* RTC registers */
@@ -21,7 +22,7 @@ enum {
 	RTC_BBPU_RELOAD		= BIT(5),
 	RTC_BBPU_CBUSY		= BIT(6),
 
-	RTC_CBUSY_TIMEOUT_US	= 8000,
+	RTC_CBUSY_TIMEOUT_US	= USECS_PER_SEC,
 };
 
 enum {
@@ -59,6 +60,7 @@ enum {
 #define BBPU_RELOAD_TIMEOUT_US		100000
 #define EOSC_CHECK_CLK_TIMEOUT_US	1000000
 #define RECOVERY_RETRY_COUNT		3
+#define PROT_UNLOCK_RETRY_COUNT		3
 
 struct rtc_clk_freq {
 	u16 fqm26m_ck;
diff --git a/src/soc/mediatek/mt8196/mt6685_rtc.c b/src/soc/mediatek/mt8196/mt6685_rtc.c
index 95e8dd6907..36e29f5a2a 100644
--- a/src/soc/mediatek/mt8196/mt6685_rtc.c
+++ b/src/soc/mediatek/mt8196/mt6685_rtc.c
@@ -33,6 +33,34 @@ void rtc_write(u16 addr, u16 wdata)
 	mt6685_write16(addr, wdata);
 }
 
+static u16 rtc_get_prot_stat(void)
+{
+	u16 val;
+	u16 state = 0;
+
+	udelay(100);
+
+	rtc_read(RTC_SPAR_MACRO, &val);
+
+	state = (val >> RTC_SPAR_PROT_STAT_SHIFT) & RTC_SPAR_PROT_STAT_MASK;
+
+	return state;
+}
+
+static bool mt6685_writeif_unlock(void)
+{
+	if (!retry(PROT_UNLOCK_RETRY_COUNT,
+		   rtc_writeif_unlock() &&
+		   rtc_get_prot_stat() == RTC_PROT_UNLOCK_SUCCESS)) {
+
+		printk(BIOS_ERR, "%s: retry failed!!\n", __func__);
+
+		return false;
+	}
+
+	return true;
+}
+
 static bool rtc_eosc_check_clock(const struct rtc_clk_freq *result)
 {
 	if ((result->fqm26m_ck >= 3 && result->fqm26m_ck <= 7) &&
@@ -319,7 +347,7 @@ static bool rtc_init_after_recovery(void)
 	/* write powerkeys */
 	if (!rtc_powerkey_init())
 		return false;
-	if (!rtc_writeif_unlock())
+	if (!mt6685_writeif_unlock())
 		return false;
 	if (!rtc_gpio_init())
 		return false;
@@ -332,7 +360,7 @@ static bool rtc_init_after_recovery(void)
 
 	if (!rtc_powerkey_init())
 		return false;
-	if (!rtc_writeif_unlock())
+	if (!mt6685_writeif_unlock())
 		return false;
 
 	secure_rtc_init();
@@ -366,9 +394,9 @@ static bool rtc_first_boot_init(void)
 	if (!rtc_write_trigger())
 		return false;
 
-	if (!rtc_writeif_unlock()) {
+	if (!mt6685_writeif_unlock()) {
 		printk(BIOS_ERR,
-		       "%s: rtc_writeif_unlock failed after BBPU written\n", __func__);
+		       "%s: mt6685_writeif_unlock failed after BBPU written\n", __func__);
 		return false;
 	}
 
@@ -387,9 +415,9 @@ static bool rtc_first_boot_init(void)
 		return false;
 	}
 
-	if (!rtc_writeif_unlock()) {
+	if (!mt6685_writeif_unlock()) {
 		printk(BIOS_ERR,
-		       "%s: rtc_writeif_unlock failed after POWERKEY written\n", __func__);
+		       "%s: mt6685_writeif_unlock failed after POWERKEY written\n", __func__);
 		return false;
 	}
 
@@ -402,9 +430,9 @@ static bool rtc_first_boot_init(void)
 		return false;
 	}
 
-	if (!rtc_writeif_unlock()) {
+	if (!mt6685_writeif_unlock()) {
 		printk(BIOS_ERR,
-		       "%s rtc_writeif_unlock failed after BBPU written\n", __func__);
+		       "%s mt6685_writeif_unlock failed after BBPU written\n", __func__);
 		return false;
 	}
 
@@ -418,9 +446,9 @@ static bool rtc_first_boot_init(void)
 		return false;
 	}
 
-	if (!rtc_writeif_unlock()) {
+	if (!mt6685_writeif_unlock()) {
 		printk(BIOS_ERR,
-		       "%s rtc_writeif_unlock failed after POWERKEY written\n", __func__);
+		       "%s mt6685_writeif_unlock failed after POWERKEY written\n", __func__);
 		return false;
 	}
 
@@ -444,8 +472,8 @@ static void rtc_enable_dcxo(void)
 	u16 con, osc32con, sec;
 
 	/* Unlock for reload */
-	if (!rtc_writeif_unlock())
-		printk(BIOS_ERR, "rtc_writeif_unlock() failed\n");
+	if (!mt6685_writeif_unlock())
+		printk(BIOS_ERR, "mt6685_writeif_unlock() failed\n");
 
 	rtc_read(RTC_BBPU, &rdata);
 	rtc_write(RTC_BBPU, rdata | RTC_BBPU_KEY | RTC_BBPU_RELOAD);
@@ -525,7 +553,7 @@ void rtc_boot(void)
 	rtc_read(RTC_BBPU, &rtc_bbpu);
 	rtc_write(RTC_BBPU, rtc_bbpu | RTC_BBPU_KEY | RTC_BBPU_RELOAD);
 
-	if (!rtc_write_trigger() || !rtc_writeif_unlock()) {
+	if (!rtc_write_trigger() || !mt6685_writeif_unlock()) {
 		rtc_recovery_flow();
 	} else {
 		rtc_read(RTC_POWERKEY1, &rtc_pwrkey1);

From e4cbd9ea9f1b4f66128a29c306842619d494d243 Mon Sep 17 00:00:00 2001
From: "Irving-CH.lin" <irving-ch.lin@mediatek.corp-partner.google.com>
Date: Thu, 7 Nov 2024 14:23:31 +0800
Subject: [PATCH 0995/3886] soc/mediatek/mt8189: Add MTCMOS init support

Add MTCMOS init code and APIs for controlling power domain.

BUG=b:379008996
BRANCH=none
TEST=build pass and driver init ok.

Change-Id: I39ab203da4d17b72fc5ccdbce664100d671f5e29
Signed-off-by: Irving-CH.lin <irving-ch.lin@mediatek.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87634
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
---
 src/soc/mediatek/common/include/soc/mtcmos.h  |   16 +-
 src/soc/mediatek/common/mtcmos.c              |   25 +-
 src/soc/mediatek/mt8189/Makefile.mk           |    2 +
 src/soc/mediatek/mt8189/bootblock.c           |    2 +
 .../mediatek/mt8189/include/soc/addressmap.h  |    3 +
 src/soc/mediatek/mt8189/include/soc/spm.h     | 1028 +++++++++++++++++
 .../mediatek/mt8189/include/soc/spm_mtcmos.h  |   91 ++
 src/soc/mediatek/mt8189/mtcmos.c              |   82 ++
 8 files changed, 1244 insertions(+), 5 deletions(-)
 create mode 100644 src/soc/mediatek/mt8189/include/soc/spm.h
 create mode 100644 src/soc/mediatek/mt8189/include/soc/spm_mtcmos.h
 create mode 100644 src/soc/mediatek/mt8189/mtcmos.c

diff --git a/src/soc/mediatek/common/include/soc/mtcmos.h b/src/soc/mediatek/common/include/soc/mtcmos.h
index 75f1c3818a..15b4367fc4 100644
--- a/src/soc/mediatek/common/include/soc/mtcmos.h
+++ b/src/soc/mediatek/common/include/soc/mtcmos.h
@@ -1,15 +1,25 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
-#ifndef __SOC_MEDIATEK_COMMON_MTCMOS_H__
-#define __SOC_MEDIATEK_COMMON_MTCMOS_H__
+#ifndef __SOC_MEDIATEK_COMMON_INCLUDE_SOC_MTCMOS_H__
+#define __SOC_MEDIATEK_COMMON_INCLUDE_SOC_MTCMOS_H__
+
+struct bus_protect {
+	void *clr_addr;
+	u32 mask;
+};
 
 struct power_domain_data {
 	void *pwr_con;
+	void *pwr_status;
+	void *pwr_status_2nd;
 	u32 pwr_sta_mask;
 	u32 sram_pdn_mask;
 	u32 sram_ack_mask;
 	u32 ext_buck_iso_bits;
 	u32 caps;
+	size_t bp_steps;
+	/* Bus protection */
+	const struct bus_protect *bp_table;
 };
 
 #define SCPD_SRAM_ISO		BIT(0)
@@ -26,4 +36,4 @@ void mtcmos_protect_adsp_bus(void);
 void mtcmos_protect_audio_bus(void);
 void mtcmos_protect_display_bus(void);
 
-#endif /* __SOC_MEDIATEK_COMMON_MTCMOS_H__ */
+#endif /* __SOC_MEDIATEK_COMMON_INCLUDE_SOC_MTCMOS_H__ */
diff --git a/src/soc/mediatek/common/mtcmos.c b/src/soc/mediatek/common/mtcmos.c
index 2f4bd22d54..f69e84fab7 100644
--- a/src/soc/mediatek/common/mtcmos.c
+++ b/src/soc/mediatek/common/mtcmos.c
@@ -19,8 +19,19 @@ __weak void mtcmos_set_scpd_ext_buck_iso(const struct power_domain_data *pd)
 	/* do nothing */
 }
 
+static void release_bus_protection(const struct power_domain_data *pd)
+{
+	int i;
+
+	for (i = 0; i < pd->bp_steps; i++)
+		write32(pd->bp_table[i].clr_addr, pd->bp_table[i].mask);
+}
+
 void mtcmos_power_on(const struct power_domain_data *pd)
 {
+	u32 *pwr_status;
+	u32 *pwr_status_2nd;
+
 	write32(&mtk_spm->poweron_config_set,
 		(SPM_PROJECT_CODE << 16) | (1U << 0));
 
@@ -30,8 +41,16 @@ void mtcmos_power_on(const struct power_domain_data *pd)
 	setbits32(pd->pwr_con, PWR_ON);
 	setbits32(pd->pwr_con, PWR_ON_2ND);
 
-	while (!(read32(&mtk_spm->pwr_status) & pd->pwr_sta_mask) ||
-	       !(read32(&mtk_spm->pwr_status_2nd) & pd->pwr_sta_mask))
+	if ((pd->pwr_status != NULL) && (pd->pwr_status_2nd != NULL)) {
+		pwr_status = pd->pwr_status;
+		pwr_status_2nd = pd->pwr_status_2nd;
+	} else {
+		pwr_status = &mtk_spm->pwr_status;
+		pwr_status_2nd = &mtk_spm->pwr_status_2nd;
+	}
+
+	while (!(read32(pwr_status) & pd->pwr_sta_mask) ||
+	       !(read32(pwr_status_2nd) & pd->pwr_sta_mask))
 		continue;
 
 	clrbits32(pd->pwr_con, PWR_CLK_DIS);
@@ -47,6 +66,8 @@ void mtcmos_power_on(const struct power_domain_data *pd)
 		udelay(1);
 		clrbits32(pd->pwr_con, SRAM_CKISO);
 	}
+
+	release_bus_protection(pd);
 }
 
 void mtcmos_display_power_on(void)
diff --git a/src/soc/mediatek/mt8189/Makefile.mk b/src/soc/mediatek/mt8189/Makefile.mk
index 56a7033eb3..baa176f882 100644
--- a/src/soc/mediatek/mt8189/Makefile.mk
+++ b/src/soc/mediatek/mt8189/Makefile.mk
@@ -11,6 +11,7 @@ all-y += ../common/uart.c
 
 bootblock-y += bootblock.c
 bootblock-y += ../common/mmu_operations.c
+bootblock-y += ../common/mtcmos.c mtcmos.c
 bootblock-y += ../common/wdt.c ../common/wdt_req.c wdt.c
 
 romstage-y += ../common/cbmem.c
@@ -25,6 +26,7 @@ ramstage-y += ../common/dramc_info.c
 ramstage-y += ../common/emi.c
 ramstage-y += ../common/memory.c
 ramstage-y += ../common/mmu_operations.c ../common/mmu_cmops.c
+ramstage-y += ../common/mtcmos.c mtcmos.c
 ramstage-y += soc.c
 ramstage-y += ../common/usb.c usb.c
 
diff --git a/src/soc/mediatek/mt8189/bootblock.c b/src/soc/mediatek/mt8189/bootblock.c
index ed78d65354..0c55272cbe 100644
--- a/src/soc/mediatek/mt8189/bootblock.c
+++ b/src/soc/mediatek/mt8189/bootblock.c
@@ -2,10 +2,12 @@
 
 #include <bootblock_common.h>
 #include <soc/mmu_operations.h>
+#include <soc/spm_mtcmos.h>
 #include <soc/wdt.h>
 
 void bootblock_soc_init(void)
 {
 	mtk_mmu_init();
 	mtk_wdt_init();
+	mtcmos_init();
 }
diff --git a/src/soc/mediatek/mt8189/include/soc/addressmap.h b/src/soc/mediatek/mt8189/include/soc/addressmap.h
index 84006623a4..826945347a 100644
--- a/src/soc/mediatek/mt8189/include/soc/addressmap.h
+++ b/src/soc/mediatek/mt8189/include/soc/addressmap.h
@@ -27,6 +27,7 @@ enum {
 	EMI0_BASE			= IO_PHYS + 0x00219000,
 	EMI0_MPU_BASE			= IO_PHYS + 0x00226000,
 	DRAMC_CHA_AO_BASE		= IO_PHYS + 0x00230000,
+	EMICFG_AO_MEM_BASE		= IO_PHYS + 0x00270000,
 	THERM_CTRL_BASE			= IO_PHYS + 0x00315000,
 	DPM_PM_SRAM_BASE		= IO_PHYS + 0x00900000,
 	DPM_DM_SRAM_BASE		= IO_PHYS + 0x00920000,
@@ -72,7 +73,9 @@ enum {
 	IOCFG_RT_BASE			= IO_PHYS + 0x01F20000,
 	DSI0_BASE			= IO_PHYS + 0x04016000,
 	DISP_DVO0			= IO_PHYS + 0x04019000,
+	SPM_BASE			= IO_PHYS + 0x0C001000,
 	RGU_BASE			= IO_PHYS + 0x0C00A000,
+	VLPCFG_REG_BASE			= IO_PHYS + 0x0C00C000,
 	SPMI_MST_BASE			= IO_PHYS + 0x0C013000,
 	DEVAPC_VLP_AO_BASE		= IO_PHYS + 0x0C018000,
 	SPMI_MST_P_BASE			= IO_PHYS + 0x0CC00000,
diff --git a/src/soc/mediatek/mt8189/include/soc/spm.h b/src/soc/mediatek/mt8189/include/soc/spm.h
new file mode 100644
index 0000000000..c504672b2a
--- /dev/null
+++ b/src/soc/mediatek/mt8189/include/soc/spm.h
@@ -0,0 +1,1028 @@
+/* SPDX-License-Identifier: GPL-2.0-only OR MIT */
+
+#ifndef __SOC_MEDIATEK_MT8189_INCLUDE_SOC_SPM_H__
+#define __SOC_MEDIATEK_MT8189_INCLUDE_SOC_SPM_H__
+
+#include <device/mmio.h>
+#include <soc/addressmap.h>
+#include <soc/mtcmos.h>
+#include <soc/pll.h>
+#include <soc/spm_common.h>
+#include <types.h>
+
+/* SPM READ/WRITE CFG */
+#define SPM_PROJECT_CODE			0xB16
+#define SPM_REGWR_CFG_KEY			(SPM_PROJECT_CODE << 16)
+
+/* POWERON_CONFIG_EN (0x1C001000 + 0x000) */
+#define BCLK_CG_EN_LSB				BIT(0)
+#define PROJECT_CODE_LSB			BIT(16)
+
+/* SPM_CLK_CON (0x1C001000 + 0x024) */
+#define REG_SPM_LOCK_INFRA_DCM_LSB		BIT(0)
+#define REG_CXO32K_REMOVE_EN_LSB		BIT(1)
+#define REG_SPM_LEAVE_SUSPEND_MERGE_MASK_LSB	BIT(4)
+#define REG_SRCLKENO0_SRC_MASK_B_LSB		BIT(8)
+#define REG_SRCLKENO1_SRC_MASK_B_LSB		BIT(16)
+#define REG_SRCLKENO2_SRC_MASK_B_LSB		BIT(24)
+
+/* PCM_CON0 (0x1C001000 + 0x018) */
+#define PCM_CK_EN_LSB				BIT(2)
+#define PCM_SW_RESET_LSB			BIT(15)
+#define PCM_CON0_PROJECT_CODE_LSB		BIT(16)
+
+/* PCM_CON1 (0x1C001000 + 0x01C) */
+#define REG_SPM_APB_INTERNAL_EN_LSB		BIT(3)
+#define REG_PCM_TIMER_EN_LSB			BIT(5)
+#define REG_PCM_WDT_EN_LSB			BIT(8)
+#define REG_PCM_WDT_WAKE_LSB			BIT(9)
+#define REG_SSPM_APB_P2P_EN_LSB			BIT(10)
+#define REG_MCUPM_APB_P2P_EN_LSB		BIT(11)
+#define REG_RSV_APB_P2P_EN_LSB			BIT(12)
+#define RG_PCM_IRQ_MSK_LSB			BIT(15)
+#define PCM_CON1_PROJECT_CODE_LSB		BIT(16)
+
+/* SPM_WAKEUP_EVENT_MASK (0x1C001000 + 0x808) */
+#define REG_WAKEUP_EVENT_MASK_LSB		BIT(0)
+
+/* DDREN_DBC_CON (0x1C001000 + 0x890) */
+#define REG_DDREN_DBC_LEN_LSB			BIT(0)
+#define REG_DDREN_DBC_EN_LSB			BIT(16)
+
+/* SPM_DVFS_CON (0x1C001000 + 0x3AC) */
+#define SPM_DVFS_FORCE_ENABLE_LSB		BIT(2)
+#define FORCE_DVFS_WAKE_LSB			BIT(3)
+#define SPM_DVFSRC_ENABLE_LSB			BIT(4)
+#define DVFSRC_WAKEUP_EVENT_MASK_LSB		BIT(6)
+#define SPM2RC_EVENT_ABORT_LSB			BIT(7)
+#define DVFSRC_LEVEL_ACK_LSB			BIT(8)
+
+/* SPM_SW_FLAG_0 (0x1C001000 + 0x600) */
+#define SPM_SW_FLAG_LSB				BIT(0)
+
+/* SYS_TIMER_CON (0x1C001000 + 0x500) */
+#define SYS_TIMER_START_EN_LSB			BIT(0)
+#define SYS_TIMER_LATCH_EN_LSB			BIT(1)
+#define SYS_TIMER_ID_LSB			BIT(8)
+#define SYS_TIMER_VALID_LSB			BIT(31)
+
+/**************************************
+ * Config and Parameter
+ **************************************/
+#define POWER_ON_VAL0_DEF		0x0000F100
+#define POWER_ON_VAL1_DEF		0x003FFE20
+#define SPM_WAKEUP_EVENT_MASK_DEF	0xF97FFCFF
+#define SPM_BUS_PROTECT_MASK_B_DEF	0xFFFFFFFF
+#define SPM_BUS_PROTECT2_MASK_B_DEF	0xFFFFFFFF
+#define MD32PCM_DMA0_CON_VAL		0x0003820E
+#define MD32PCM_DMA0_START_VAL		0x00008000
+#define SPM_DVFS_LEVEL_DEF		0x00000001
+#define SPM_DVS_DFS_LEVEL_DEF		0x00010001
+#define SPM_RESOURCE_ACK_CON0_DEF	0xCC4E4ECC
+#define SPM_RESOURCE_ACK_CON1_DEF	0x00CCCCCC
+#define SPM_SYSCLK_SETTLE		0x60FE /* 1685us */
+#define SPM_INIT_DONE_US		20
+#define PCM_WDT_TIMEOUT			(30 * 32768)
+#define PCM_TIMER_MAX			((5400 - 30) * 32768) /* 90min - 30sec */
+
+/**************************************
+ * Definition and Declaration
+ **************************************/
+/* SPM_IRQ_MASK */
+#define ISRM_TWAM		BIT(2)
+#define ISRM_RET_IRQ1		BIT(9)
+#define ISRM_RET_IRQ2		BIT(10)
+#define ISRM_RET_IRQ3		BIT(11)
+#define ISRM_RET_IRQ4		BIT(12)
+#define ISRM_RET_IRQ5		BIT(13)
+#define ISRM_RET_IRQ6		BIT(14)
+#define ISRM_RET_IRQ7		BIT(15)
+#define ISRM_RET_IRQ8		BIT(16)
+#define ISRM_RET_IRQ9		BIT(17)
+#define ISRM_RET_IRQ_AUX	(ISRM_RET_IRQ9 | ISRM_RET_IRQ8 | \
+				 ISRM_RET_IRQ7 | ISRM_RET_IRQ6 | \
+				 ISRM_RET_IRQ5 | ISRM_RET_IRQ4 | \
+				 ISRM_RET_IRQ3 | ISRM_RET_IRQ2 | \
+				 ISRM_RET_IRQ1)
+
+#define ISRM_ALL_EXC_TWAM	ISRM_RET_IRQ_AUX
+#define ISRM_ALL		(ISRM_ALL_EXC_TWAM | ISRM_TWAM)
+
+/* SPM_IRQ_STA */
+#define ISRS_TWAM		BIT(2)
+#define ISRS_PCM_RETURN		BIT(3)
+#define ISRC_TWAM		ISRS_TWAM
+#define ISRC_ALL_EXC_TWAM	ISRS_PCM_RETURN
+#define ISRC_ALL		(ISRC_ALL_EXC_TWAM | ISRC_TWAM)
+
+/* PCM_PWR_IO_EN */
+#define PCM_PWRIO_EN_R0		BIT(0)
+#define PCM_PWRIO_EN_R7		BIT(7)
+#define PCM_RF_SYNC_R0		BIT(16)
+#define PCM_RF_SYNC_R6		BIT(22)
+#define PCM_RF_SYNC_R7		BIT(23)
+
+/* SPM_SWINT */
+#define PCM_SW_INT0		BIT(0)
+#define PCM_SW_INT1		BIT(1)
+#define PCM_SW_INT2		BIT(2)
+#define PCM_SW_INT3		BIT(3)
+#define PCM_SW_INT4		BIT(4)
+#define PCM_SW_INT5		BIT(5)
+#define PCM_SW_INT6		BIT(6)
+#define PCM_SW_INT7		BIT(7)
+#define PCM_SW_INT8		BIT(8)
+#define PCM_SW_INT9		BIT(9)
+#define PCM_SW_INT_ALL		(PCM_SW_INT9 | PCM_SW_INT8 | PCM_SW_INT7 | \
+				 PCM_SW_INT6 | PCM_SW_INT5 | PCM_SW_INT4 | \
+				 PCM_SW_INT3 | PCM_SW_INT2 | PCM_SW_INT1 | \
+				 PCM_SW_INT0)
+
+#define SPM_ACK_CHK_3_SEL_HW_S1	0x00350098
+#define SPM_ACK_CHK_3_HW_S1_CNT	1
+
+DEFINE_BIT(SPM_ACK_CHK_3_CON_CLR_ALL, 1)
+DEFINE_BIT(SPM_ACK_CHK_3_CON_EN_0, 4)
+DEFINE_BIT(SPM_ACK_CHK_3_CON_EN_1, 8)
+DEFINE_BIT(SPM_ACK_CHK_3_CON_HW_MODE_TRIG, 11)
+
+struct pwr_ctrl {
+	/* for SPM */
+	u32 pcm_flags;
+	/* can override pcm_flags */
+	u32 pcm_flags_cust;
+	/* set bit of pcm_flags, after pcm_flags_cust */
+	u32 pcm_flags_cust_set;
+	/* clr bit of pcm_flags, after pcm_flags_cust */
+	u32 pcm_flags_cust_clr;
+	u32 pcm_flags1;
+	/* can override pcm_flags1 */
+	u32 pcm_flags1_cust;
+	/* set bit of pcm_flags1, after pcm_flags1_cust */
+	u32 pcm_flags1_cust_set;
+	/* clr bit of pcm_flags1, after pcm_flags1_cust */
+	u32 pcm_flags1_cust_clr;
+	/* @ 1T 32K */
+	u32 timer_val;
+	/* @ 1T 32K, can override timer_val */
+	u32 timer_val_cust;
+	/* stress for dpidle */
+	u32 timer_val_ramp_en;
+	/* stress for suspend */
+	u32 timer_val_ramp_en_sec;
+	u32 wake_src;
+	/* can override wake_src */
+	u32 wake_src_cust;
+	u32 wakelock_timer_val;
+	/* disable wdt in suspend */
+	u8 wdt_disable;
+
+	/* SPM_CLK_CON */
+	u8 reg_spm_lock_infra_dcm_lsb;
+	u8 reg_cxo32k_remove_en_lsb;
+	u8 reg_spm_leave_suspend_merge_mask_lsb;
+	u8 reg_sysclk0_src_mask_b_lsb;
+	u8 reg_sysclk1_src_mask_b_lsb;
+	u8 reg_sysclk2_src_mask_b_lsb;
+
+	/* SPM_AP_STANDBY_CON */
+	u8 reg_wfi_op;
+	u8 reg_wfi_type;
+	u8 reg_mp0_cputop_idle_mask;
+	u8 reg_mp1_cputop_idle_mask;
+	u8 reg_mcusys_idle_mask;
+	u8 reg_csyspwrup_req_mask_lsb;
+	u8 reg_wfi_af_sel;
+	u8 reg_cpu_sleep_wfi;
+
+	/* SPM_SRC_REQ */
+	u8 reg_spm_adsp_mailbox_req;
+	u8 reg_spm_apsrc_req;
+	u8 reg_spm_ddren_req;
+	u8 reg_spm_dvfs_req;
+	u8 reg_spm_emi_req;
+	u8 reg_spm_f26m_req;
+	u8 reg_spm_infra_req;
+	u8 reg_spm_pmic_req;
+	u8 reg_spm_scp_mailbox_req;
+	u8 reg_spm_sspm_mailbox_req;
+	u8 reg_spm_sw_mailbox_req;
+	u8 reg_spm_vcore_req;
+	u8 reg_spm_vrf18_req;
+	u8 adsp_mailbox_state;
+	u8 apsrc_state;
+	u8 ddren_state;
+	u8 dvfs_state;
+	u8 emi_state;
+	u8 f26m_state;
+	u8 infra_state;
+	u8 pmic_state;
+	u8 scp_mailbox_state;
+	u8 sspm_mailbox_state;
+	u8 sw_mailbox_state;
+	u8 vcore_state;
+	u8 vrf18_state;
+
+	/* SPM_SRC_MASK_0 */
+	u8 reg_apu_apsrc_req_mask_b;
+	u8 reg_apu_ddren_req_mask_b;
+	u8 reg_apu_emi_req_mask_b;
+	u8 reg_apu_infra_req_mask_b;
+	u8 reg_apu_pmic_req_mask_b;
+	u8 reg_apu_srcclkena_mask_b;
+	u8 reg_apu_vrf18_req_mask_b;
+	u8 reg_audio_dsp_apsrc_req_mask_b;
+	u8 reg_audio_dsp_ddren_req_mask_b;
+	u8 reg_audio_dsp_emi_req_mask_b;
+	u8 reg_audio_dsp_infra_req_mask_b;
+	u8 reg_audio_dsp_pmic_req_mask_b;
+	u8 reg_audio_dsp_srcclkena_mask_b;
+	u8 reg_audio_dsp_vcore_req_mask_b;
+	u8 reg_audio_dsp_vrf18_req_mask_b;
+	u8 reg_cam_apsrc_req_mask_b;
+	u8 reg_cam_ddren_req_mask_b;
+	u8 reg_cam_emi_req_mask_b;
+	u8 reg_cam_infra_req_mask_b;
+	u8 reg_cam_pmic_req_mask_b;
+	u8 reg_cam_srcclkena_mask_b;
+	u8 reg_cam_vrf18_req_mask_b;
+	u8 reg_mdp_emi_req_mask_b;
+
+	/* SPM_SRC_MASK_1 */
+	u32 reg_ccif_apsrc_req_mask_b;
+	u32 reg_ccif_emi_req_mask_b;
+
+	/* SPM_SRC_MASK_2 */
+	u32 reg_ccif_infra_req_mask_b;
+	u32 reg_ccif_pmic_req_mask_b;
+
+	/* SPM_SRC_MASK_3 */
+	u32 reg_ccif_srcclkena_mask_b;
+	u32 reg_ccif_vrf18_req_mask_b;
+	u8 reg_ccu_apsrc_req_mask_b;
+	u8 reg_ccu_ddren_req_mask_b;
+	u8 reg_ccu_emi_req_mask_b;
+	u8 reg_ccu_infra_req_mask_b;
+	u8 reg_ccu_pmic_req_mask_b;
+	u8 reg_ccu_srcclkena_mask_b;
+	u8 reg_ccu_vrf18_req_mask_b;
+	u8 reg_cg_check_apsrc_req_mask_b;
+
+	/* SPM_SRC_MASK_4 */
+	u8 reg_cg_check_ddren_req_mask_b;
+	u8 reg_cg_check_emi_req_mask_b;
+	u8 reg_cg_check_infra_req_mask_b;
+	u8 reg_cg_check_pmic_req_mask_b;
+	u8 reg_cg_check_srcclkena_mask_b;
+	u8 reg_cg_check_vcore_req_mask_b;
+	u8 reg_cg_check_vrf18_req_mask_b;
+	u8 reg_conn_apsrc_req_mask_b;
+	u8 reg_conn_ddren_req_mask_b;
+	u8 reg_conn_emi_req_mask_b;
+	u8 reg_conn_infra_req_mask_b;
+	u8 reg_conn_pmic_req_mask_b;
+	u8 reg_conn_srcclkena_mask_b;
+	u8 reg_conn_srcclkenb_mask_b;
+	u8 reg_conn_vcore_req_mask_b;
+	u8 reg_conn_vrf18_req_mask_b;
+	u8 reg_cpueb_apsrc_req_mask_b;
+	u8 reg_cpueb_ddren_req_mask_b;
+	u8 reg_cpueb_emi_req_mask_b;
+	u8 reg_cpueb_infra_req_mask_b;
+	u8 reg_cpueb_pmic_req_mask_b;
+	u8 reg_cpueb_srcclkena_mask_b;
+	u8 reg_cpueb_vrf18_req_mask_b;
+	u8 reg_disp0_apsrc_req_mask_b;
+	u8 reg_disp0_ddren_req_mask_b;
+	u8 reg_disp0_emi_req_mask_b;
+	u8 reg_disp0_infra_req_mask_b;
+	u8 reg_disp0_pmic_req_mask_b;
+	u8 reg_disp0_srcclkena_mask_b;
+	u8 reg_disp0_vrf18_req_mask_b;
+	u8 reg_disp1_apsrc_req_mask_b;
+	u8 reg_disp1_ddren_req_mask_b;
+
+	/* SPM_SRC_MASK_5 */
+	u8 reg_disp1_emi_req_mask_b;
+	u8 reg_disp1_infra_req_mask_b;
+	u8 reg_disp1_pmic_req_mask_b;
+	u8 reg_disp1_srcclkena_mask_b;
+	u8 reg_disp1_vrf18_req_mask_b;
+	u8 reg_dpm_apsrc_req_mask_b;
+	u8 reg_dpm_ddren_req_mask_b;
+	u8 reg_dpm_emi_req_mask_b;
+	u8 reg_dpm_infra_req_mask_b;
+	u8 reg_dpm_pmic_req_mask_b;
+	u8 reg_dpm_srcclkena_mask_b;
+
+	/* SPM_SRC_MASK_6 */
+	u8 reg_dpm_vcore_req_mask_b;
+	u8 reg_dpm_vrf18_req_mask_b;
+	u8 reg_dpmaif_apsrc_req_mask_b;
+	u8 reg_dpmaif_ddren_req_mask_b;
+	u8 reg_dpmaif_emi_req_mask_b;
+	u8 reg_dpmaif_infra_req_mask_b;
+	u8 reg_dpmaif_pmic_req_mask_b;
+	u8 reg_dpmaif_srcclkena_mask_b;
+	u8 reg_dpmaif_vrf18_req_mask_b;
+	u8 reg_dvfsrc_level_req_mask_b;
+	u8 reg_emisys_apsrc_req_mask_b;
+	u8 reg_emisys_ddren_req_mask_b;
+	u8 reg_emisys_emi_req_mask_b;
+	u8 reg_gce_d_apsrc_req_mask_b;
+	u8 reg_gce_d_ddren_req_mask_b;
+	u8 reg_gce_d_emi_req_mask_b;
+	u8 reg_gce_d_infra_req_mask_b;
+	u8 reg_gce_d_pmic_req_mask_b;
+	u8 reg_gce_d_srcclkena_mask_b;
+	u8 reg_gce_d_vrf18_req_mask_b;
+	u8 reg_gce_m_apsrc_req_mask_b;
+	u8 reg_gce_m_ddren_req_mask_b;
+	u8 reg_gce_m_emi_req_mask_b;
+	u8 reg_gce_m_infra_req_mask_b;
+	u8 reg_gce_m_pmic_req_mask_b;
+	u8 reg_gce_m_srcclkena_mask_b;
+
+	/* SPM_SRC_MASK_7 */
+	u8 reg_gce_m_vrf18_req_mask_b;
+	u8 reg_gpueb_apsrc_req_mask_b;
+	u8 reg_gpueb_ddren_req_mask_b;
+	u8 reg_gpueb_emi_req_mask_b;
+	u8 reg_gpueb_infra_req_mask_b;
+	u8 reg_gpueb_pmic_req_mask_b;
+	u8 reg_gpueb_srcclkena_mask_b;
+	u8 reg_gpueb_vrf18_req_mask_b;
+	u8 reg_hwccf_apsrc_req_mask_b;
+	u8 reg_hwccf_ddren_req_mask_b;
+	u8 reg_hwccf_emi_req_mask_b;
+	u8 reg_hwccf_infra_req_mask_b;
+	u8 reg_hwccf_pmic_req_mask_b;
+	u8 reg_hwccf_srcclkena_mask_b;
+	u8 reg_hwccf_vcore_req_mask_b;
+	u8 reg_hwccf_vrf18_req_mask_b;
+	u8 reg_img_apsrc_req_mask_b;
+	u8 reg_img_ddren_req_mask_b;
+	u8 reg_img_emi_req_mask_b;
+	u8 reg_img_infra_req_mask_b;
+	u8 reg_img_pmic_req_mask_b;
+	u8 reg_img_srcclkena_mask_b;
+	u8 reg_img_vrf18_req_mask_b;
+	u8 reg_infrasys_apsrc_req_mask_b;
+	u8 reg_infrasys_ddren_req_mask_b;
+	u8 reg_infrasys_emi_req_mask_b;
+	u8 reg_ipic_infra_req_mask_b;
+	u8 reg_ipic_vrf18_req_mask_b;
+	u8 reg_mcu_apsrc_req_mask_b;
+	u8 reg_mcu_ddren_req_mask_b;
+	u8 reg_mcu_emi_req_mask_b;
+
+	/* SPM_SRC_MASK_8 */
+	u8 reg_mcusys_apsrc_req_mask_b;
+	u8 reg_mcusys_ddren_req_mask_b;
+	u8 reg_mcusys_emi_req_mask_b;
+	u8 reg_mcusys_infra_req_mask_b;
+
+	/* SPM_SRC_MASK_9 */
+	u8 reg_mcusys_pmic_req_mask_b;
+	u8 reg_mcusys_srcclkena_mask_b;
+	u8 reg_mcusys_vrf18_req_mask_b;
+	u8 reg_md_apsrc_req_mask_b;
+	u8 reg_md_ddren_req_mask_b;
+	u8 reg_md_emi_req_mask_b;
+	u8 reg_md_infra_req_mask_b;
+	u8 reg_md_pmic_req_mask_b;
+	u8 reg_md_srcclkena_mask_b;
+	u8 reg_md_srcclkena1_mask_b;
+	u8 reg_md_vcore_req_mask_b;
+
+	/* SPM_SRC_MASK_10 */
+	u8 reg_md_vrf18_req_mask_b;
+	u8 reg_mdp_apsrc_req_mask_b;
+	u8 reg_mdp_ddren_req_mask_b;
+	u8 reg_mm_proc_apsrc_req_mask_b;
+	u8 reg_mm_proc_ddren_req_mask_b;
+	u8 reg_mm_proc_emi_req_mask_b;
+	u8 reg_mm_proc_infra_req_mask_b;
+	u8 reg_mm_proc_pmic_req_mask_b;
+	u8 reg_mm_proc_srcclkena_mask_b;
+	u8 reg_mm_proc_vrf18_req_mask_b;
+	u8 reg_mmsys_apsrc_req_mask_b;
+	u8 reg_mmsys_ddren_req_mask_b;
+	u8 reg_mmsys_vrf18_req_mask_b;
+	u8 reg_pcie0_apsrc_req_mask_b;
+	u8 reg_pcie0_ddren_req_mask_b;
+	u8 reg_pcie0_infra_req_mask_b;
+	u8 reg_pcie0_srcclkena_mask_b;
+	u8 reg_pcie0_vrf18_req_mask_b;
+	u8 reg_pcie1_apsrc_req_mask_b;
+	u8 reg_pcie1_ddren_req_mask_b;
+	u8 reg_pcie1_infra_req_mask_b;
+	u8 reg_pcie1_srcclkena_mask_b;
+	u8 reg_pcie1_vrf18_req_mask_b;
+	u8 reg_perisys_apsrc_req_mask_b;
+	u8 reg_perisys_ddren_req_mask_b;
+	u8 reg_perisys_emi_req_mask_b;
+	u8 reg_perisys_infra_req_mask_b;
+	u8 reg_perisys_pmic_req_mask_b;
+	u8 reg_perisys_srcclkena_mask_b;
+	u8 reg_perisys_vcore_req_mask_b;
+	u8 reg_perisys_vrf18_req_mask_b;
+	u8 reg_scp_apsrc_req_mask_b;
+
+	/* SPM_SRC_MASK_11 */
+	u8 reg_scp_ddren_req_mask_b;
+	u8 reg_scp_emi_req_mask_b;
+	u8 reg_scp_infra_req_mask_b;
+	u8 reg_scp_pmic_req_mask_b;
+	u8 reg_scp_srcclkena_mask_b;
+	u8 reg_scp_vcore_req_mask_b;
+	u8 reg_scp_vrf18_req_mask_b;
+	u8 reg_srcclkeni_infra_req_mask_b;
+	u8 reg_srcclkeni_pmic_req_mask_b;
+	u8 reg_srcclkeni_srcclkena_mask_b;
+	u8 reg_sspm_apsrc_req_mask_b;
+	u8 reg_sspm_ddren_req_mask_b;
+	u8 reg_sspm_emi_req_mask_b;
+	u8 reg_sspm_infra_req_mask_b;
+	u8 reg_sspm_pmic_req_mask_b;
+	u8 reg_sspm_srcclkena_mask_b;
+	u8 reg_sspm_vrf18_req_mask_b;
+	u8 reg_ssr_apsrc_req_mask_b;
+	u8 reg_ssr_ddren_req_mask_b;
+	u8 reg_ssr_emi_req_mask_b;
+	u8 reg_ssr_infra_req_mask_b;
+	u8 reg_ssr_pmic_req_mask_b;
+	u8 reg_ssr_srcclkena_mask_b;
+	u8 reg_ssr_vrf18_req_mask_b;
+	u8 reg_ufs_apsrc_req_mask_b;
+	u8 reg_ufs_ddren_req_mask_b;
+	u8 reg_ufs_emi_req_mask_b;
+	u8 reg_ufs_infra_req_mask_b;
+	u8 reg_ufs_pmic_req_mask_b;
+
+	/* SPM_SRC_MASK_12 */
+	u8 reg_ufs_srcclkena_mask_b;
+	u8 reg_ufs_vrf18_req_mask_b;
+	u8 reg_vdec_apsrc_req_mask_b;
+	u8 reg_vdec_ddren_req_mask_b;
+	u8 reg_vdec_emi_req_mask_b;
+	u8 reg_vdec_infra_req_mask_b;
+	u8 reg_vdec_pmic_req_mask_b;
+	u8 reg_vdec_srcclkena_mask_b;
+	u8 reg_vdec_vrf18_req_mask_b;
+	u8 reg_venc_apsrc_req_mask_b;
+	u8 reg_venc_ddren_req_mask_b;
+	u8 reg_venc_emi_req_mask_b;
+	u8 reg_venc_infra_req_mask_b;
+	u8 reg_venc_pmic_req_mask_b;
+	u8 reg_venc_srcclkena_mask_b;
+	u8 reg_venc_vrf18_req_mask_b;
+	u8 reg_ipe_apsrc_req_mask_b;
+	u8 reg_ipe_ddren_req_mask_b;
+	u8 reg_ipe_emi_req_mask_b;
+	u8 reg_ipe_infra_req_mask_b;
+	u8 reg_ipe_pmic_req_mask_b;
+	u8 reg_ipe_srcclkena_mask_b;
+	u8 reg_ipe_vrf18_req_mask_b;
+	u8 reg_ufs_vcore_req_mask_b;
+
+	/* SPM_EVENT_CON_MISC */
+	u8 reg_srcclken_fast_resp;
+	u8 reg_csyspwrup_ack_mask;
+
+	/* SPM_WAKEUP_EVENT_MASK */
+	u32 reg_wakeup_event_mask;
+
+	/* SPM_WAKEUP_EVENT_EXT_MASK */
+	u32 reg_ext_wakeup_event_mask;
+};
+
+struct mtk_spm_regs {
+	u32 poweron_config_set;
+	u32 spm_power_on_val[4];
+	u32 pcm_pwr_io_en;
+	u32 pcm_con0;
+	u32 pcm_con1;
+	u32 spm_sram_sleep_ctrl;
+	u32 spm_clk_con;
+	u32 spm_clk_settle;
+	u32 spm_clk_con1;
+	u8 reserved0[16];
+	u32 spm_sw_rst_con;
+	u32 spm_sw_rst_con_set;
+	u32 spm_sw_rst_con_clr;
+	u8 reserved1[4];
+	u32 spm_sec_read_mask;
+	u32 spm_one_time_lock_l;
+	u32 spm_one_time_lock_m;
+	u32 spm_one_time_lock_h;
+	u8 reserved2[36];
+	u32 sspm_clk_con;
+	u32 scp_clk_con;
+	u8 reserved3[4];
+	u32 spm_swint;
+	u32 spm_swint_set;
+	u32 spm_swint_clr;
+	u8 reserved4[20];
+	u32 spm_cpu_wakeup_event;
+	u32 spm_irq_mask;
+	u8 reserved5[72];
+	u32 md32pcm_scu_ctrl[4];
+	u32 md32pcm_scu_sta0;
+	u8 reserved6[20];
+	u32 spm_irq_sta;
+	u8 reserved7[4];
+	u32 md32pcm_wakeup_sta;
+	u32 md32pcm_event_sta;
+	u8 reserved8[8];
+	u32 spm_wakeup_misc;
+	u8 reserved9[32];
+	u32 spm_ck_sta;
+	u8 reserved10[40];
+	u32 md32pcm_sta;
+	u32 md32pcm_pc;
+	u8 reserved11[104];
+	u32 spm_ap_standby_con;
+	u32 cpu_wfi_en;
+	u32 cpu_wfi_en_set;
+	u32 cpu_wfi_en_clr;
+	u32 ext_int_wakeup_req;
+	u32 ext_int_wakeup_req_set;
+	u32 ext_int_wakeup_req_clr;
+	u32 mcusys_idle_sta;
+	u32 cpu_pwr_status;
+	u32 sw2spm_wakeup;
+	u32 sw2spm_wakeup_set;
+	u32 sw2spm_wakeup_clr;
+	u32 sw2spm_mailbox[4];
+	u32 spm2sw_mailbox[4];
+	u32 spm2mcupm_con;
+	u8 reserved12[12];
+	u32 spm_mcusys_pwr_con;
+	u32 spm_cputop_pwr_con;
+	u32 spm_cpu0_pwr_con;
+	u32 spm_cpu1_pwr_con;
+	u32 spm_cpu2_pwr_con;
+	u32 spm_cpu3_pwr_con;
+	u32 spm_cpu4_pwr_con;
+	u32 spm_cpu5_pwr_con;
+	u32 spm_cpu6_pwr_con;
+	u32 spm_cpu7_pwr_con;
+	u32 spm_mcupm_spmc_con;
+	u8 reserved13[20];
+	u32 spm_dpm_p2p_sta;
+	u32 spm_dpm_p2p_con;
+	u32 spm_dpm_intf_sta;
+	u32 spm_dpm_wb_con;
+	u32 spm_ack_chk_timer_3;
+	u32 spm_ack_chk_sta_3;
+	u8 reserved14[72];
+	u32 spm_pwrap_con;
+	u32 spm_pwrap_con_sta;
+	u32 spm_pmic_spmi_con;
+	u8 reserved15[4];
+	u32 spm_pwrap_cmd[32];
+	u32 dvfsrc_event_sta;
+	u32 spm_force_dvfs;
+	u32 spm_dvfs_sta;
+	u32 spm_dvs_dfs_level;
+	u32 spm_dvfs_level;
+	u32 spm_dvfs_opp;
+	u32 spm_ultra_req;
+	u32 spm_dvfs_con;
+	u32 spm_sramrc_con;
+	u32 spm_srclkenrc_con;
+	u32 spm_dpsw_con;
+	u8 reserved16[68];
+	u32 ulposc_con;
+	u32 ap_mdsrc_req;
+	u32 spm2md_switch_ctrl;
+	u32 rc_spm_ctrl;
+	u32 spm2gpupm_con;
+	u32 spm2apu_con;
+	u32 spm2efuse_con;
+	u32 spm2dfd_con;
+	u32 rsv_pll_con;
+	u32 emi_slb_con;
+	u32 spm_suspend_flag_con;
+	u32 spm2pmsr_con;
+	u32 spm_topck_rtff_con;
+	u32 emi_shf_con;
+	u32 cirq_byoass_con;
+	u32 aoc_vcore_sram_con;
+	u8 reserved17[32];
+	u32 reg_module_sw_cg_ddren_req_mask_0;
+	u32 reg_module_sw_cg_ddren_req_mask_1;
+	u32 reg_module_sw_cg_ddren_req_mask_2;
+	u32 reg_module_sw_cg_ddren_req_mask_3;
+	u32 reg_module_sw_cg_vrf18_req_mask_0;
+	u32 reg_module_sw_cg_vrf18_req_mask_1;
+	u32 reg_module_sw_cg_vrf18_req_mask_2;
+	u32 reg_module_sw_cg_vrf18_req_mask_3;
+	u32 reg_module_sw_cg_infra_req_mask_0;
+	u32 reg_module_sw_cg_infra_req_mask_1;
+	u32 reg_module_sw_cg_infra_req_mask_2;
+	u32 reg_module_sw_cg_infra_req_mask_3;
+	u32 reg_module_sw_cg_f26m_req_mask_0;
+	u32 reg_module_sw_cg_f26m_req_mask_1;
+	u32 reg_module_sw_cg_f26m_req_mask_2;
+	u32 reg_module_sw_cg_f26m_req_mask_3;
+	u32 reg_module_sw_cg_vcore_req_mask_0;
+	u32 reg_module_sw_cg_vcore_req_mask_1;
+	u32 reg_module_sw_cg_vcore_req_mask_2;
+	u32 reg_module_sw_cg_vcore_req_mask_3;
+	u32 reg_pwr_status_ddren_req_mask;
+	u32 reg_pwr_status_vrf18_req_mask;
+	u32 reg_pwr_status_infra_req_mask;
+	u32 reg_pwr_status_f26m_req_mask;
+	u32 reg_pwr_status_pmic_req_mask;
+	u32 reg_pwr_status_vcore_req_mask;
+	u32 reg_pwr_status_msb_ddren_req_mask;
+	u32 reg_pwr_status_msb_vrf18_req_mask;
+	u32 reg_pwr_status_msb_infra_req_mask;
+	u32 reg_pwr_status_msb_f26m_req_mask;
+	u32 reg_pwr_status_msb_pmic_req_mask;
+	u32 reg_pwr_status_msb_vcore_req_mask;
+	u32 reg_module_busy_msb_ddren_req_mask;
+	u32 reg_module_busy_msb_vrf18_req_mask;
+	u32 reg_module_busy_msb_infra_req_mask;
+	u32 reg_module_busy_msb_f26m_req_mask;
+	u32 reg_module_busy_msb_pmic_req_mask;
+	u32 reg_module_busy_msb_vcore_req_mask;
+	u8 reserved18[8];
+	u32 sys_timer_con;
+	u32 sys_timer_value_l;
+	u32 sys_timer_value_h;
+	u32 sys_timer_start_l;
+	u32 sys_timer_start_h;
+	struct {
+		u32 latch_l;
+		u32 latch_h;
+	} sys_timer_latch[16];
+	u32 pcm_timer_val;
+	u32 pcm_timer_out;
+	u32 spm_counter_0;
+	u32 spm_counter_1;
+	u32 spm_counter_2;
+	u32 pcm_wdt_val;
+	u32 pcm_wdt_out;
+	u8 reserved19[80];
+	u32 spm_sw_flag_0;
+	u32 spm_sw_debug_0;
+	u32 spm_sw_flag_1;
+	u32 spm_sw_debug_1;
+	u32 spm_sw_rsv[9];
+	u32 spm_bk_wake_event;
+	u32 spm_bk_vtcxo_dur;
+	u32 spm_bk_wake_misc;
+	u32 spm_bk_pcm_timer;
+	u8 reserved20[12];
+	u32 spm_rsv_con_0;
+	u32 spm_rsv_con_1;
+	u32 spm_rsv_sta_0;
+	u32 spm_rsv_sta_1;
+	u32 spm_spare_con;
+	u32 spm_spare_con_set;
+	u32 spm_spare_con_clr;
+	u32 spm_cross_wake_m00_req;
+	u32 spm_cross_wake_m01_req;
+	u32 spm_cross_wake_m02_req;
+	u32 spm_cross_wake_m03_req;
+	u32 scp_vcore_level;
+	u32 spm_ddren_ack_sel_con;
+	u32 spm_sw_flag_2;
+	u32 spm_sw_debug_2;
+	u32 spm_dv_con_0;
+	u32 spm_dv_con_1;
+	u8 reserved21[8];
+	u32 spm_sema_m0;
+	u32 spm_sema_m1;
+	u32 spm_sema_m2;
+	u32 spm_sema_m3;
+	u32 spm_sema_m4;
+	u32 spm_sema_m5;
+	u32 spm_sema_m6;
+	u32 spm_sema_m7;
+	u32 spm2adsp_mailbox;
+	u32 adsp2spm_mailbox;
+	u32 vcore_rtff_ctrl_mask_set;
+	u32 vcore_rtff_ctrl_mask_clr;
+	u32 spm2pmcu_mailbox_0;
+	u32 spm2pmcu_mailbox_1;
+	u32 spm2pmcu_mailbox_2;
+	u32 spm2pmcu_mailbox_3;
+	u32 pmcu2spm_mailbox_0;
+	u32 pmcu2spm_mailbox_1;
+	u32 pmcu2spm_mailbox_2;
+	u32 pmcu2spm_mailbox_3;
+	u32 spm2scp_mailbox;
+	u32 scp2spm_mailbox;
+	u32 scp_aov_bus_con;
+	u32 vcore_rtff_ctrl_mask;
+	u32 spm_sram_srclkeno_mask;
+	u32 emi_pdn_req;
+	u32 emi_busy_req;
+	u32 emi_reserved_sta;
+	u32 sc_univpll_div_rst_b;
+	u32 eco_armpll_div_clock_off;
+	u32 spm_mcdsr_cg_check_x1;
+	u32 spm_sodi2_cg_check_x1;
+	u8 reserved22[228];
+	u32 spm_wakeup_sta;
+	u32 spm_wakeup_ext_sta;
+	u32 spm_wakeup_event_mask;
+	u32 spm_wakeup_event_ext_mask;
+	u32 spm_wakeup_event_sens;
+	u32 spm_wakeup_event_clear;
+	u32 spm_src_req;
+	u32 spm_src_mask_0;
+	u32 spm_src_mask_1;
+	u32 spm_src_mask_2;
+	u32 spm_src_mask_3;
+	u32 spm_src_mask_4;
+	u32 spm_src_mask_5;
+	u32 spm_src_mask_6;
+	u32 spm_src_mask_7;
+	u32 spm_src_mask_8;
+	u32 spm_src_mask_9;
+	u32 spm_src_mask_10;
+	u32 spm_src_mask_11;
+	u32 spm_src_mask_12;
+	u32 src_req_sta_0;
+	u32 src_req_sta_1;
+	u32 src_req_sta_2;
+	u32 src_req_sta_3;
+	u32 src_req_sta_4;
+	u32 src_req_sta_5;
+	u32 src_req_sta_6;
+	u32 src_req_sta_7;
+	u32 src_req_sta_8;
+	u32 src_req_sta_9;
+	u32 src_req_sta_10;
+	u32 src_req_sta_11;
+	u32 src_req_sta_12;
+	u32 spm_ipc_wakeup_req;
+	u32 ipc_wakeup_req_mask_sta;
+	u32 spm_event_con_misc;
+	u32 ddren_dbc_con;
+	u32 spm_resource_ack_con0;
+	u32 spm_resource_ack_con1;
+	u32 spm_resource_ack_mask0;
+	u32 spm_resource_ack_mask1;
+	u32 spm_resource_ack_mask2;
+	u32 spm_resource_ack_mask3;
+	u32 spm_resource_ack_mask4;
+	u32 spm_resource_ack_mask5;
+	u32 spm_resource_ack_mask6;
+	u32 spm_event_counter_clear;
+	u32 spm_vcore_event_count_sta;
+	u32 spm_pmic_event_count_sta;
+	u32 spm_srcclkena_event_count_sta;
+	u32 spm_infra_event_count_sta;
+	u32 spm_vrf18_event_count_sta;
+	u32 spm_emi_event_count_sta;
+	u32 spm_apsrc_event_count_sta;
+	u32 spm_ddren_event_count_sta;
+	u32 pcm_wdt_latch_0;
+	u32 pcm_wdt_latch_1;
+	u32 pcm_wdt_latch_2;
+	u32 pcm_wdt_latch_3;
+	u32 pcm_wdt_latch_4;
+	u32 pcm_wdt_latch_5;
+	u32 pcm_wdt_latch_6;
+	u32 pcm_wdt_latch_7;
+	u32 pcm_wdt_latch_8;
+	u32 pcm_wdt_latch_9;
+	u32 pcm_wdt_latch_10;
+	u32 pcm_wdt_latch_11;
+	u32 pcm_wdt_latch_12;
+	u32 pcm_wdt_latch_13;
+	u32 pcm_wdt_latch_14;
+	u32 pcm_wdt_latch_15;
+	u32 pcm_wdt_latch_16;
+	u32 pcm_wdt_latch_17;
+	u32 pcm_wdt_latch_18;
+	u32 pcm_wdt_latch_19;
+	u32 pcm_wdt_latch_20;
+	u32 pcm_wdt_latch_21;
+	u32 pcm_wdt_latch_22;
+	u32 pcm_wdt_latch_23;
+	u32 pcm_wdt_latch_24;
+	u32 pcm_wdt_latch_25;
+	u32 pcm_wdt_latch_26;
+	u32 pcm_wdt_latch_27;
+	u32 pcm_wdt_latch_28;
+	u32 pcm_wdt_latch_29;
+	u32 pcm_wdt_latch_30;
+	u32 pcm_wdt_latch_31;
+	u32 pcm_wdt_latch_32;
+	u32 pcm_wdt_latch_33;
+	u32 pcm_wdt_latch_34;
+	u32 pcm_wdt_latch_35;
+	u32 pcm_wdt_latch_36;
+	u32 pcm_wdt_latch_37;
+	u32 pcm_wdt_latch_38;
+	u32 pcm_wdt_latch_39;
+	u32 pcm_wdt_latch_40;
+	u32 pcm_wdt_latch_spare_0;
+	u32 pcm_wdt_latch_spare_1;
+	u32 pcm_wdt_latch_spare_2;
+	u32 pcm_wdt_latch_spare_3;
+	u32 pcm_wdt_latch_spare_4;
+	u32 pcm_wdt_latch_spare_5;
+	u32 pcm_wdt_latch_spare_6;
+	u32 pcm_wdt_latch_spare_7;
+	u32 pcm_wdt_latch_spare_8;
+	u32 pcm_wdt_latch_spare_9;
+	u32 dramc_gating_err_latch_0;
+	u32 dramc_gating_err_latch_1;
+	u32 dramc_gating_err_latch_2;
+	u32 dramc_gating_err_latch_3;
+	u32 dramc_gating_err_latch_4;
+	u32 dramc_gating_err_latch_5;
+	u32 dramc_gating_err_latch_spare_0;
+	u32 spm_debug_con;
+	u32 spm_ack_chk_con_0;
+	u32 spm_ack_chk_sel_0;
+	u32 spm_ack_chk_timer_0;
+	u32 spm_ack_chk_sta_0;
+	u32 spm_ack_chk_con_1;
+	u32 spm_ack_chk_sel_1;
+	u32 spm_ack_chk_timer_1;
+	u32 spm_ack_chk_sta_1;
+	u32 spm_ack_chk_con_2;
+	u32 spm_ack_chk_sel_2;
+	u32 spm_ack_chk_timer_2;
+	u32 spm_ack_chk_sta_2;
+	u32 spm_ack_chk_con_3;
+	u32 spm_ack_chk_sel_3;
+	u8 reserved23[1024];
+	u32 md1_pwr_con;
+	u32 conn_pwr_con;
+	u32 ifr_pwr_con;
+	u32 peri_pwr_con;
+	u32 ufs0_pwr_con;
+	u32 ufs0_phy_pwr_con;
+	u32 audio_pwr_con;
+	u32 adsp_top_pwr_con;
+	u32 adsp_infra_pwr_con;
+	u32 adsp_ao_pwr_con;
+	u32 isp_img1_pwr_con;
+	u32 isp_img2_pwr_con;
+	u32 isp_ipe_pwr_con;
+	u32 isp_vcore_pwr_con;
+	u32 vde0_pwr_con;
+	u32 vde1_pwr_con;
+	u32 ven0_pwr_con;
+	u32 ven1_pwr_con;
+	u32 cam_main_pwr_con;
+	u32 cam_mraw_pwr_con;
+	u32 cam_suba_pwr_con;
+	u32 cam_subb_pwr_con;
+	u32 cam_subc_pwr_con;
+	u32 cam_vcore_pwr_con;
+	u32 cam_ccu_pwr_con;
+	u32 cam_ccu_ao_pwr_con;
+	u32 mdp0_pwr_con;
+	u32 mdp1_pwr_con;
+	u32 dis0_pwr_con;
+	u32 dis1_pwr_con;
+	u32 mm_infra_pwr_con;
+	u32 mm_proc_pwr_con;
+	u32 dp_tx_pwr_con;
+	u32 scp_core_pwr_con;
+	u32 scp_peri_pwr_con;
+	u32 dpm0_pwr_con;
+	u32 dpm1_pwr_con;
+	u32 emi0_pwr_con;
+	u32 emi1_pwr_con;
+	u32 csi_rx_pwr_con;
+	u32 ssrsys_pwr_con;
+	u32 sspm_pwr_con;
+	u32 ssusb_pwr_con;
+	u32 ssusb_phy_pwr_con;
+	u32 cpueb_pwr_con;
+	u32 mfg0_pwr_con;
+	u32 mfg1_pwr_con;
+	u32 mfg2_pwr_con;
+	u32 mfg3_pwr_con;
+	u32 mfg4_pwr_con;
+	u32 mfg5_pwr_con;
+	u32 mfg6_pwr_con;
+	u32 mfg7_pwr_con;
+	u32 adsp_hre_sram_con;
+	u32 ccu_sleep_sram_con;
+	u32 efuse_sram_con;
+	u32 emi_hre_sram_con;
+	u32 emi_slb_sram_con;
+	u32 infra_hre_sram_con;
+	u32 infra_sleep_sram_con;
+	u32 mm_hre_sram_con;
+	u32 nth_emi_slb_sram_con;
+	u32 nth_emi_slb_sram_ack;
+	u32 peri_sleep_sram_con;
+	u32 spm_sram_con;
+	u32 sspm_sram_con;
+	u32 ssr_sleep_sram_con;
+	u32 sth_emi_slb_sram_con;
+	u32 sth_emi_slb_sram_ack;
+	u32 ufs_pdn_sram_con;
+	u32 ufs_sleep_sram_con;
+	u32 unipro_pdn_sram_con;
+	u32 cpu_buck_iso_con;
+	u32 md_buck_iso_con;
+	u32 soc_buck_iso_con;
+	u32 soc_buck_iso_con_set;
+	u32 soc_buck_iso_con_clr;
+	u32 soc_buck_iso_con_2;
+	u32 soc_buck_iso_con_2_set;
+	u32 soc_buck_iso_con_2_clr;
+	u32 pwr_status;
+	u32 pwr_status_2nd;
+	u32 pwr_status_msb;
+	u32 pwr_status_msb_2nd;
+	u32 xpu_pwr_status;
+	u32 xpu_pwr_status_2nd;
+	u32 dfd_soc_pwr_latch;
+	u32 subsys_pm_bypass;
+	u32 vadsp_hre_sram_con;
+	u32 vadsp_hre_sram_ack;
+	u32 gcpu_sram_con;
+	u32 gcpu_sram_ack;
+	u32 edp_tx_pwr_con;
+	u32 pcie_pwr_con;
+	u32 pcie_phy_pwr_con;
+	u8 reserved24[4];
+	u32 spm_twam_con;
+	u32 spm_twam_window_len;
+	u32 spm_twam_idle_sel;
+	u32 spm_twam_last_sta0;
+	u32 spm_twam_last_sta1;
+	u32 spm_twam_last_sta2;
+	u32 spm_twam_last_sta3;
+	u32 spm_twam_curr_sta0;
+	u32 spm_twam_curr_sta1;
+	u32 spm_twam_curr_sta2;
+	u32 spm_twam_curr_sta3;
+	u32 spm_twam_timer_out;
+};
+
+check_member(mtk_spm_regs, ap_mdsrc_req, 0x404);
+check_member(mtk_spm_regs, ulposc_con, 0x400);
+check_member(mtk_spm_regs, conn_pwr_con, 0x0E04);
+check_member(mtk_spm_regs, ufs0_pwr_con, 0x0E10);
+check_member(mtk_spm_regs, audio_pwr_con, 0xe18);
+check_member(mtk_spm_regs, vde0_pwr_con, 0x0E38);
+check_member(mtk_spm_regs, ven0_pwr_con, 0x0E40);
+check_member(mtk_spm_regs, cam_main_pwr_con, 0x0E48);
+check_member(mtk_spm_regs, cam_suba_pwr_con, 0x0E50);
+check_member(mtk_spm_regs, mdp0_pwr_con, 0x0E68);
+check_member(mtk_spm_regs, dis0_pwr_con, 0x0E70);
+check_member(mtk_spm_regs, mm_infra_pwr_con, 0x0E78);
+check_member(mtk_spm_regs, dp_tx_pwr_con, 0x0E80);
+check_member(mtk_spm_regs, scp_peri_pwr_con, 0x0E88);
+check_member(mtk_spm_regs, csi_rx_pwr_con, 0x0E9C);
+check_member(mtk_spm_regs, ssusb_pwr_con, 0x0EA8);
+check_member(mtk_spm_regs, mfg0_pwr_con, 0x0EB4);
+check_member(mtk_spm_regs, mfg3_pwr_con, 0x0EC0);
+check_member(mtk_spm_regs, pwr_status, 0x0F40);
+check_member(mtk_spm_regs, edp_tx_pwr_con, 0x0F70);
+
+static struct mtk_spm_regs *const mtk_spm = (void *)SPM_BASE;
+
+static const struct power_domain_data disp[] = {
+	{
+		/* dis0 */
+		.pwr_con = &mtk_spm->dis0_pwr_con,
+		.pwr_sta_mask = BIT(28),
+		.sram_pdn_mask = BIT(8),
+		.sram_ack_mask = BIT(12),
+	},
+	{
+		/* edp_tx */
+		.pwr_con = &mtk_spm->edp_tx_pwr_con,
+		.pwr_status = &mtk_spm->pwr_status_msb,
+		.pwr_status_2nd = &mtk_spm->pwr_status_msb_2nd,
+		.pwr_sta_mask = BIT(12),
+		.sram_pdn_mask = BIT(8),
+		.sram_ack_mask = BIT(12),
+		.caps = SCPD_SRAM_ISO,
+	},
+};
+
+static const struct power_domain_data audio[] = {
+	{
+		/* adsp_ao */
+		.pwr_con = &mtk_spm->adsp_ao_pwr_con,
+		.pwr_sta_mask = BIT(9),
+	},
+	{
+		/* audio */
+		.pwr_con = &mtk_spm->audio_pwr_con,
+		.pwr_sta_mask = BIT(6),
+		.sram_pdn_mask = BIT(8),
+		.sram_ack_mask = BIT(12),
+	},
+};
+
+#endif  /* __SOC_MEDIATEK_MT8189_INCLUDE_SOC_SPM_H__ */
diff --git a/src/soc/mediatek/mt8189/include/soc/spm_mtcmos.h b/src/soc/mediatek/mt8189/include/soc/spm_mtcmos.h
new file mode 100644
index 0000000000..f9b9f473a6
--- /dev/null
+++ b/src/soc/mediatek/mt8189/include/soc/spm_mtcmos.h
@@ -0,0 +1,91 @@
+/* SPDX-License-Identifier: GPL-2.0-only OR MIT */
+
+#ifndef __SOC_MEDIATEK_MT8189_INCLUDE_SOC_SPM_MTCMOS_H__
+#define __SOC_MEDIATEK_MT8189_INCLUDE_SOC_SPM_MTCMOS_H__
+
+#include <device/mmio.h>
+#include <soc/addressmap.h>
+#include <types.h>
+
+struct mtk_reg_cfg {
+	u32 status;
+	u32 set;
+	u32 clr;
+	u32 ready;
+};
+
+struct mtk_vlpcfg_regs {
+	u32 reserved1;
+	u32 vlp_test_ck_ctrl;
+	u32 reserved2[130];
+	u32 bus_vlp_topaxi_protecten;
+	u32 bus_vlp_topaxi_protecten_set;
+	u32 bus_vlp_topaxi_protecten_clr;
+	u32 bus_vlp_topaxi_protecten_sta1;
+};
+check_member(mtk_vlpcfg_regs, vlp_test_ck_ctrl, 0x0004);
+check_member(mtk_vlpcfg_regs, bus_vlp_topaxi_protecten, 0x0210);
+
+struct mtk_infracfg_ao_regs {
+	u32 reserved1[28];
+	u32 infra_bus_dcm_ctrl;
+	u32 reserved2[3];
+	u32 infracfg_ao_module_cg_0_set;
+	u32 infracfg_ao_module_cg_0_clr;
+	u32 infracfg_ao_module_cg_1_set;
+	u32 infracfg_ao_module_cg_1_clr;
+	u32 infracfg_ao_module_cg_0;
+	u32 infracfg_ao_module_cg_1;
+	u32 reserved3[3];
+	u32 infracfg_ao_module_cg_2_set;
+	u32 infracfg_ao_module_cg_2_clr;
+	u32 infracfg_ao_module_cg_2;
+	u32 reserved4[4];
+	u32 infracfg_ao_module_cg_3_set;
+	u32 infracfg_ao_module_cg_3_clr;
+	u32 infracfg_ao_module_cg_3;
+	u32 reserved5[721];
+	struct mtk_reg_cfg mmsys_protect[2];
+	u32 reserved6[4];
+	struct mtk_reg_cfg infrasys_protect[2];
+	struct mtk_reg_cfg emisys_protect;
+	u32 reserved7[4];
+	struct mtk_reg_cfg perisys_protect;
+	struct mtk_reg_cfg mcu_connsys_protect;
+	struct mtk_reg_cfg md_mfgsys_protect;
+};
+check_member(mtk_infracfg_ao_regs, infra_bus_dcm_ctrl, 0x0070);
+check_member(mtk_infracfg_ao_regs, infracfg_ao_module_cg_0_set, 0x0080);
+check_member(mtk_infracfg_ao_regs, infracfg_ao_module_cg_1, 0x0094);
+check_member(mtk_infracfg_ao_regs, infracfg_ao_module_cg_2_set, 0x00A4);
+check_member(mtk_infracfg_ao_regs, infracfg_ao_module_cg_3_set, 0x00C0);
+check_member(mtk_infracfg_ao_regs, mmsys_protect[0].status, 0x0C10);
+check_member(mtk_infracfg_ao_regs, mmsys_protect[0].set, 0x0C14);
+check_member(mtk_infracfg_ao_regs, mmsys_protect[0].clr, 0x0C18);
+check_member(mtk_infracfg_ao_regs, mmsys_protect[0].ready, 0x0C1C);
+check_member(mtk_infracfg_ao_regs, infrasys_protect[0].status, 0x0C40);
+check_member(mtk_infracfg_ao_regs, infrasys_protect[0].set, 0x0C44);
+check_member(mtk_infracfg_ao_regs, infrasys_protect[0].clr, 0x0C48);
+check_member(mtk_infracfg_ao_regs, infrasys_protect[0].ready, 0x0C4C);
+check_member(mtk_infracfg_ao_regs, perisys_protect.status, 0x0C80);
+check_member(mtk_infracfg_ao_regs, perisys_protect.set, 0x0C84);
+check_member(mtk_infracfg_ao_regs, perisys_protect.clr, 0x0C88);
+check_member(mtk_infracfg_ao_regs, perisys_protect.ready, 0x0C8C);
+
+struct mtk_emicfg_ao_mem_regs {
+	u32 reserved[32];
+	struct mtk_reg_cfg gals_slp_prot;
+};
+check_member(mtk_emicfg_ao_mem_regs, gals_slp_prot.status, 0x0080);
+check_member(mtk_emicfg_ao_mem_regs, gals_slp_prot.set, 0x0084);
+check_member(mtk_emicfg_ao_mem_regs, gals_slp_prot.clr, 0x0088);
+check_member(mtk_emicfg_ao_mem_regs, gals_slp_prot.ready, 0x008C);
+
+static struct mtk_vlpcfg_regs *const mtk_vlpcfg = (void *)VLPCFG_REG_BASE;
+static struct mtk_infracfg_ao_regs *const mtk_infracfg_ao = (void *)INFRACFG_AO_BASE;
+static struct mtk_emicfg_ao_mem_regs *const mtk_emicfg_ao_mem = (void *)EMICFG_AO_MEM_BASE;
+
+void spm_power_on(void);
+void mtcmos_init(void);
+
+#endif /* __SOC_MEDIATEK_MT8189_INCLUDE_SOC_SPM_MTCMOS_H__ */
diff --git a/src/soc/mediatek/mt8189/mtcmos.c b/src/soc/mediatek/mt8189/mtcmos.c
new file mode 100644
index 0000000000..2f10517886
--- /dev/null
+++ b/src/soc/mediatek/mt8189/mtcmos.c
@@ -0,0 +1,82 @@
+/* SPDX-License-Identifier: GPL-2.0-only OR MIT */
+
+/*
+ * This file is created based on MT8189 Functional Specification
+ * Chapter number: 8.1
+ */
+
+#include <console/console.h>
+#include <soc/mtcmos.h>
+#include <soc/spm.h>
+#include <soc/spm_mtcmos.h>
+
+static const struct bus_protect bp_ufs[] = {
+	{&mtk_vlpcfg->bus_vlp_topaxi_protecten_clr, BIT(6)},
+	{&mtk_infracfg_ao->perisys_protect.clr, BIT(4)},
+	{&mtk_vlpcfg->bus_vlp_topaxi_protecten_clr, BIT(5)},
+};
+
+static const struct bus_protect bp_mminfra[] = {
+	{&mtk_infracfg_ao->emisys_protect.clr, BIT(20) | BIT(21)},
+	{&mtk_infracfg_ao->infrasys_protect[0].clr, BIT(16)},
+	{&mtk_infracfg_ao->mmsys_protect[1].clr,
+	 BIT(0) | BIT(7) | BIT(8) | BIT(9) | BIT(10) |
+	 BIT(11) | BIT(12) | BIT(13) | BIT(14) | BIT(15)},
+	{&mtk_infracfg_ao->infrasys_protect[1].clr, BIT(11)},
+	{&mtk_infracfg_ao->mmsys_protect[1].clr,
+	 BIT(1) | BIT(2) | BIT(3)},
+};
+
+static const struct bus_protect bp_ssusb[] = {
+	{&mtk_infracfg_ao->perisys_protect.clr, BIT(7)},
+};
+
+static const struct power_domain_data pd_plat[] = {
+	{
+		/* ufs0 */
+		.pwr_con = &mtk_spm->ufs0_pwr_con,
+		.pwr_sta_mask = BIT(4),
+		.sram_pdn_mask = BIT(8),
+		.sram_ack_mask = BIT(12),
+		.bp_steps = ARRAY_SIZE(bp_ufs),
+		.bp_table = bp_ufs,
+	},
+	{
+		/* ufs0_phy */
+		.pwr_con = &mtk_spm->ufs0_phy_pwr_con,
+		.pwr_sta_mask = BIT(5),
+	},
+	{
+		/* mm_infra */
+		.pwr_con = &mtk_spm->mm_infra_pwr_con,
+		.pwr_sta_mask = BIT(30),
+		.sram_pdn_mask = BIT(8),
+		.sram_ack_mask = BIT(12),
+		.bp_steps = ARRAY_SIZE(bp_mminfra),
+		.bp_table = bp_mminfra,
+	},
+	{
+		/* ssusb */
+		.pwr_con = &mtk_spm->ssusb_pwr_con,
+		.pwr_status = &mtk_spm->pwr_status_msb,
+		.pwr_status_2nd = &mtk_spm->pwr_status_msb_2nd,
+		.pwr_sta_mask = BIT(10),
+		.sram_pdn_mask = BIT(8),
+		.sram_ack_mask = BIT(12),
+		.bp_steps = ARRAY_SIZE(bp_ssusb),
+		.bp_table = bp_ssusb,
+	},
+};
+
+void spm_power_on(void)
+{
+	write32(&mtk_spm->poweron_config_set, SPM_REGWR_CFG_KEY | (0x1 << 0));
+}
+
+void mtcmos_init(void)
+{
+	int i;
+
+	for (i = 0; i < ARRAY_SIZE(pd_plat); i++)
+		mtcmos_power_on(&pd_plat[i]);
+}

From c2b17a083db3c1c4bbba3f5119f3197b5d9bcf17 Mon Sep 17 00:00:00 2001
From: Vince Liu <vince-wl.liu@mediatek.corp-partner.google.com>
Date: Wed, 4 Sep 2024 15:19:26 +0800
Subject: [PATCH 0996/3886] soc/mediatek/mt8189: Add PLL and clock init support

Add PLL and clock drivers.

BUG=b:379008996
BRANCH=none
TEST=build pass and driver init ok.

Change-Id: I1fd6a09e80e5f681af3034b0f703a0d2bc7bb786
Signed-off-by: Irving-CH.lin <irving-ch.lin@mediatek.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87639
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/soc/mediatek/mt8189/Makefile.mk           |   2 +
 src/soc/mediatek/mt8189/bootblock.c           |   3 +
 .../mediatek/mt8189/include/soc/addressmap.h  |  40 +-
 src/soc/mediatek/mt8189/include/soc/pll.h     | 544 ++++++++++++-
 src/soc/mediatek/mt8189/pll.c                 | 727 ++++++++++++++++++
 5 files changed, 1308 insertions(+), 8 deletions(-)
 create mode 100644 src/soc/mediatek/mt8189/pll.c

diff --git a/src/soc/mediatek/mt8189/Makefile.mk b/src/soc/mediatek/mt8189/Makefile.mk
index baa176f882..eefdae1f41 100644
--- a/src/soc/mediatek/mt8189/Makefile.mk
+++ b/src/soc/mediatek/mt8189/Makefile.mk
@@ -12,6 +12,7 @@ all-y += ../common/uart.c
 bootblock-y += bootblock.c
 bootblock-y += ../common/mmu_operations.c
 bootblock-y += ../common/mtcmos.c mtcmos.c
+bootblock-y += ../common/pll.c pll.c
 bootblock-y += ../common/wdt.c ../common/wdt_req.c wdt.c
 
 romstage-y += ../common/cbmem.c
@@ -20,6 +21,7 @@ romstage-y += ../common/dramc_param.c
 romstage-y += ../common/emi.c
 romstage-y += ../common/memory.c ../common/memory_test.c
 romstage-y += ../common/mmu_operations.c ../common/mmu_cmops.c
+romstage-y += ../common/pll.c pll.c
 
 ramstage-$(CONFIG_ARM64_USE_ARM_TRUSTED_FIRMWARE) += ../common/bl31.c
 ramstage-y += ../common/dramc_info.c
diff --git a/src/soc/mediatek/mt8189/bootblock.c b/src/soc/mediatek/mt8189/bootblock.c
index 0c55272cbe..8465a4974f 100644
--- a/src/soc/mediatek/mt8189/bootblock.c
+++ b/src/soc/mediatek/mt8189/bootblock.c
@@ -2,6 +2,7 @@
 
 #include <bootblock_common.h>
 #include <soc/mmu_operations.h>
+#include <soc/pll.h>
 #include <soc/spm_mtcmos.h>
 #include <soc/wdt.h>
 
@@ -9,5 +10,7 @@ void bootblock_soc_init(void)
 {
 	mtk_mmu_init();
 	mtk_wdt_init();
+	mt_pll_init();
 	mtcmos_init();
+	mt_pll_post_init();
 }
diff --git a/src/soc/mediatek/mt8189/include/soc/addressmap.h b/src/soc/mediatek/mt8189/include/soc/addressmap.h
index 826945347a..c02f25accd 100644
--- a/src/soc/mediatek/mt8189/include/soc/addressmap.h
+++ b/src/soc/mediatek/mt8189/include/soc/addressmap.h
@@ -4,7 +4,15 @@
 #define __SOC_MEDIATEK_MT8189_INCLUDE_SOC_ADDRESSMAP_H__
 
 enum {
-	IO_PHYS = 0x10000000,
+	MCUCFG_BASE	= 0x0C530000,
+	DBGAO_BASE	= 0x0D01A000,
+	DEM_BASE	= 0x0D0A0000,
+	IO_PHYS		= 0x10000000,
+};
+
+enum {
+	CPU_PLLDIV_CTRL_BASE	= MCUCFG_BASE + 0x0000A2A0,
+	BUS_PLLDIV_CTRL_BASE	= MCUCFG_BASE + 0x0000A2E0,
 };
 
 enum {
@@ -21,7 +29,7 @@ enum {
 	GPIO_BASE			= IO_PHYS + 0x00005000,
 	APMIXED_BASE			= IO_PHYS + 0x0000C000,
 	DEVAPC_INFRA_SECU_AO_BASE	= IO_PHYS + 0x0001C000,
-	BCRM_INFRA_AO_BASE		= IO_PHYS + 0x00022000,
+	INFRA_AO_BCRM_BASE		= IO_PHYS + 0x00022000,
 	DEVAPC_INFRA_AO_BASE		= IO_PHYS + 0x00030000,
 	DEVAPC_INFRA_AO1_BASE		= IO_PHYS + 0x00034000,
 	EMI0_BASE			= IO_PHYS + 0x00219000,
@@ -37,10 +45,14 @@ enum {
 	DPM_CFG_BASE2			= IO_PHYS + 0x00A40000,
 	UART0_BASE			= IO_PHYS + 0x01001000,
 	SFLASH_REG_BASE			= IO_PHYS + 0x01018000,
+	PERI_AO_BCRM_BASE		= IO_PHYS + 0x01035000,
 	PERICFG_AO_BASE			= IO_PHYS + 0x01036000,
 	DEVAPC_PERI_PAR_AO_BASE		= IO_PHYS + 0x0103C000,
+	AUDIO_BASE			= IO_PHYS + 0x01050000,
 	SSUSB_IPPC_BASE			= IO_PHYS + 0x01263E00,
 	UFSHCI_BASE			= IO_PHYS + 0x012B0000,
+	UFS0_AO_CFG_BASE		= IO_PHYS + 0x012B8000,
+	UFS0_PDN_CFG_BASE		= IO_PHYS + 0x012BB000,
 	I2C0_DMA_BASE			= IO_PHYS + 0x01300200,
 	I2C1_DMA_BASE			= IO_PHYS + 0x01300300,
 	I2C2_DMA_BASE			= IO_PHYS + 0x01300400,
@@ -52,6 +64,7 @@ enum {
 	I2C8_DMA_BASE			= IO_PHYS + 0x01300A00,
 	SSUSB_SIF_BASE			= IO_PHYS + 0x01B00300,
 	I2C2_BASE			= IO_PHYS + 0x01B20000,
+	IMP_IIC_WRAP_WS_BASE		= IO_PHYS + 0x01B21000,
 	MIPITX0_BASE			= IO_PHYS + 0x01B40000,
 	IOCFG_LM_BASE			= IO_PHYS + 0x01B50000,
 	EDP_BASE			= IO_PHYS + 0x01B70000,
@@ -63,26 +76,49 @@ enum {
 	I2C6_BASE			= IO_PHYS + 0x01D73000,
 	I2C7_BASE			= IO_PHYS + 0x01F30000,
 	I2C8_BASE			= IO_PHYS + 0x01F31000,
+	IMP_IIC_WRAP_E_BASE		= IO_PHYS + 0x01C22000,
 	IOCFG_RB0_BASE			= IO_PHYS + 0x01C50000,
 	IOCFG_RB1_BASE			= IO_PHYS + 0x01C60000,
 	IOCFG_BM0_BASE			= IO_PHYS + 0x01D20000,
 	IOCFG_BM1_BASE			= IO_PHYS + 0x01D30000,
 	IOCFG_BM2_BASE			= IO_PHYS + 0x01D40000,
+	IMP_IIC_WRAP_S_BASE		= IO_PHYS + 0x01D74000,
 	IOCFG_LT0_BASE			= IO_PHYS + 0x01E20000,
 	IOCFG_LT1_BASE			= IO_PHYS + 0x01E30000,
 	IOCFG_RT_BASE			= IO_PHYS + 0x01F20000,
+	IMP_IIC_WRAP_EN_BASE		= IO_PHYS + 0x01F32000,
+	MFGCFG_BASE			= IO_PHYS + 0x03FBF000,
+	MMSYS_CONFIG_BASE		= IO_PHYS + 0x04000000,
 	DSI0_BASE			= IO_PHYS + 0x04016000,
 	DISP_DVO0			= IO_PHYS + 0x04019000,
+	IMGSYS1_BASE			= IO_PHYS + 0x05020000,
+	IMGSYS2_BASE			= IO_PHYS + 0x05820000,
+	VDEC_CORE_BASE			= IO_PHYS + 0x0602F000,
+	VENC_GCON_BASE			= IO_PHYS + 0x07000000,
+	CAMSYS_MAIN_BASE		= IO_PHYS + 0x0A000000,
+	CAMSYS_RAWA_BASE		= IO_PHYS + 0x0A04F000,
+	CAMSYS_RAWB_BASE		= IO_PHYS + 0x0A06F000,
+	IPE_BASE			= IO_PHYS + 0x0B000000,
+	VLPCFG_AO_REG_BASE		= IO_PHYS + 0x0C000000,
 	SPM_BASE			= IO_PHYS + 0x0C001000,
 	RGU_BASE			= IO_PHYS + 0x0C00A000,
 	VLPCFG_REG_BASE			= IO_PHYS + 0x0C00C000,
+	DVFSRC_TOP_BASE			= IO_PHYS + 0x0C00F000,
+	VLP_CK_BASE			= IO_PHYS + 0x0C012000,
 	SPMI_MST_BASE			= IO_PHYS + 0x0C013000,
 	DEVAPC_VLP_AO_BASE		= IO_PHYS + 0x0C018000,
+	SCP_IIC_BASE			= IO_PHYS + 0x0C80A000,
+	SCP_BASE			= IO_PHYS + 0x0CB21000,
 	SPMI_MST_P_BASE			= IO_PHYS + 0x0CC00000,
 	PMIF_SPMI_BASE			= IO_PHYS + 0x0CC04000,
 	PMIF_SPMI_P_BASE		= IO_PHYS + 0x0CC06000,
 	SYSTIMER_BASE			= IO_PHYS + 0x0CC10000,
+	VAD_BASE			= IO_PHYS + 0x0E010000,
 	DEVAPC_MM_AO_BASE		= IO_PHYS + 0x0E820000,
+	MMINFRA_CONFIG_BASE		= IO_PHYS + 0x0E800000,
+	GCE_BASE			= IO_PHYS + 0x0E980000,
+	MDP_GCE_BASE			= IO_PHYS + 0x0E990000,
+	MDPSYS_CONFIG_BASE		= IO_PHYS + 0x0F000000,
 };
 
 #endif /* __SOC_MEDIATEK_MT8189_INCLUDE_SOC_ADDRESSMAP_H__ */
diff --git a/src/soc/mediatek/mt8189/include/soc/pll.h b/src/soc/mediatek/mt8189/include/soc/pll.h
index 8d6de12dd1..fb8069c010 100644
--- a/src/soc/mediatek/mt8189/include/soc/pll.h
+++ b/src/soc/mediatek/mt8189/include/soc/pll.h
@@ -8,16 +8,548 @@
 #ifndef __SOC_MEDIATEK_MT8189_INCLUDE_SOC_PLL_H__
 #define __SOC_MEDIATEK_MT8189_INCLUDE_SOC_PLL_H__
 
+#include <soc/addressmap.h>
 #include <soc/pll_common.h>
 
-/* top_div rate */
-enum {
-	CLK26M_HZ	= 26 * MHz,
+static struct mtk_infra_ao_bcrm_regs *const
+	mtk_infra_ao_bcrm = (void *)INFRA_AO_BCRM_BASE;
+static struct mtk_cpu_plldiv_cfg_regs *const
+	mtk_cpu_plldiv_cfg = (void *)CPU_PLLDIV_CTRL_BASE;
+static struct mtk_bus_plldiv_cfg_regs *const
+	mtk_bus_plldiv_cfg = (void *)BUS_PLLDIV_CTRL_BASE;
+static struct mtk_peri_ao_bcrm_regs *const
+	mtk_peri_ao_bcrm = (void *)PERI_AO_BCRM_BASE;
+static struct mtk_vlp_regs *const
+	mtk_vlpsys = (void *)VLP_CK_BASE;
+static struct mtk_pericfg_ao_regs *const
+	mtk_pericfg_ao = (void *)PERICFG_AO_BASE;
+static struct mtk_afe_regs *const
+	mtk_afe = (void *)AUDIO_BASE;
+static struct mtk_ufscfg_ao_regs *const
+	mtk_ufscfg_ao = (void *)UFS0_AO_CFG_BASE;
+static struct mtk_ufscfg_pdn_regs *const
+	mtk_ufscfg_pdn = (void *)UFS0_PDN_CFG_BASE;
+static struct mtk_imp_iic_wrap_ws_regs *const
+	mtk_imp_iic_wrap_ws = (void *)IMP_IIC_WRAP_WS_BASE;
+static struct mtk_imp_iic_wrap_e_regs *const
+	mtk_imp_iic_wrap_e = (void *)IMP_IIC_WRAP_E_BASE;
+static struct mtk_imp_iic_wrap_s_regs *const
+	mtk_imp_iic_wrap_s = (void *)IMP_IIC_WRAP_S_BASE;
+static struct mtk_imp_iic_wrap_en_regs *const
+	mtk_imp_iic_wrap_en = (void *)IMP_IIC_WRAP_EN_BASE;
+static struct mtk_mfg_regs *const
+	mtk_mfg = (void *)MFGCFG_BASE;
+static struct mtk_mmsys_config_regs *const
+	mtk_mmsys_config = (void *)MMSYS_CONFIG_BASE;
+static struct mtk_imgsys1_regs *const
+	mtk_imgsys1 = (void *)IMGSYS1_BASE;
+static struct mtk_imgsys2_regs *const
+	mtk_imgsys2 = (void *)IMGSYS2_BASE;
+static struct mtk_vdec_core_regs *const
+	mtk_vdec_core = (void *)VDEC_CORE_BASE;
+static struct mtk_venc_gcon_regs *const
+	mtk_venc_gcon = (void *)VENC_GCON_BASE;
+static struct mtk_scp_iic_regs *const
+	mtk_scp_iic = (void *)SCP_IIC_BASE;
+static struct mtk_scp_regs *const
+	mtk_scp = (void *)SCP_BASE;
+static struct mtk_vadsys_regs *const
+	mtk_vadsys = (void *)VAD_BASE;
+static struct mtk_camsys_main_regs *const
+	mtk_camsys_main = (void *)CAMSYS_MAIN_BASE;
+static struct mtk_camsys_rawa_regs *const
+	mtk_camsys_rawa = (void *)CAMSYS_RAWA_BASE;
+static struct mtk_camsys_rawb_regs *const
+	mtk_camsys_rawb = (void *)CAMSYS_RAWB_BASE;
+static struct mtk_ipesys_regs *const
+	mtk_ipesys = (void *)IPE_BASE;
+static struct mtk_vlpcfg_ao_regs *const
+	mtk_vlpcfg_ao = (void *)VLPCFG_AO_REG_BASE;
+static struct mtk_dvfsrc_top_regs *const
+	mtk_dvfsrc_top = (void *)DVFSRC_TOP_BASE;
+static struct mtk_mminfra_config_regs *const
+	mtk_mminfra_config = (void *)MMINFRA_CONFIG_BASE;
+static struct mtk_gce_d_regs *const
+	mtk_gce_d = (void *)GCE_BASE;
+static struct mtk_gce_m_regs *const
+	mtk_gce_m = (void *)MDP_GCE_BASE;
+static struct mtk_mdpsys_config_regs *const
+	mtk_mdpsys_config = (void *)MDPSYS_CONFIG_BASE;
+static struct mtk_dbgao_regs *const
+	mtk_dbgao = (void *)DBGAO_BASE;
+static struct mtk_dem_regs *const
+	mtk_dem = (void *)DEM_BASE;
+
+struct mtk_infra_ao_bcrm_regs {
+	u32 reserved[14];
+	u32 vdnr_dcm_infra_par_bus_ctrl_0;
+};
+check_member(mtk_infra_ao_bcrm_regs, vdnr_dcm_infra_par_bus_ctrl_0, 0x0038);
+
+struct mtk_cpu_plldiv_cfg_regs {
+	u32 cpu_plldiv_0_cfg0;
+	u32 cpu_plldiv_1_cfg0;
 };
 
-/* top_mux rate */
-enum {
-	UART_HZ		= CLK26M_HZ,
+struct mtk_bus_plldiv_cfg_regs {
+	u32 bus_plldiv_cfg0;
 };
 
+struct mtk_peri_ao_bcrm_regs {
+	u32 reserved1[8];
+	u32 vdnr_dcm_peri_par_bus_ctrl_0;
+	u32 reserved2[8];
+};
+check_member(mtk_peri_ao_bcrm_regs, vdnr_dcm_peri_par_bus_ctrl_0, 0x0020);
+
+struct mtk_clk_cfg {
+	u32 cfg;
+	u32 set;
+	u32 clr;
+	u32 reserved;
+};
+
+struct mtk_vlp_clk_cfg {
+	u32 cfg;
+	u32 set;
+	u32 clr;
+};
+
+struct mtk_vlp_regs {
+	u32 reserved1;
+	u32 vlp_clk_cfg_update;
+	struct mtk_vlp_clk_cfg vlp_clk_cfg[6];
+	u32 reserved2[104];
+	u32 vlp_clk_cfg_30;
+	u32 vlp_clk_cfg_30_set;
+	u32 vlp_clk_cfg_30_clr;
+	u32 reserved3[13];
+	u32 vlp_fqmtr_con[2];
+};
+
+check_member(mtk_vlp_regs, vlp_clk_cfg_update, 0x0004);
+check_member(mtk_vlp_regs, vlp_clk_cfg[0].set, 0x000C);
+check_member(mtk_vlp_regs, vlp_clk_cfg[0].clr, 0x0010);
+check_member(mtk_vlp_regs, vlp_clk_cfg[5].set, 0x0048);
+check_member(mtk_vlp_regs, vlp_clk_cfg[5].clr, 0x004C);
+check_member(mtk_vlp_regs, vlp_clk_cfg_30, 0x01F0);
+check_member(mtk_vlp_regs, vlp_fqmtr_con[0], 0x0230);
+
+struct mtk_topckgen_regs {
+	u32 reserved1;
+	u32 clk_cfg_update[3];
+	struct mtk_clk_cfg clk_cfg[17];
+	u32 reserved2[8];
+	u32 clk_misc_cfg_0;
+	u32 reserved3[7];
+	u32 clk_mem_dfs_cfg;
+	u32 reserved4[6];
+	u32 clk_dbg_cfg;
+	struct mtk_clk_cfg clk_cfg_17;
+	struct mtk_clk_cfg clk_cfg_18;
+	u32 reserved5[24];
+	u32 clk_scp_cfg_0;
+	u32 reserved6[7];
+	u32 clk26cali[2];
+	u32 reserved7[6];
+	struct mtk_clk_cfg clk_cfg_19;
+	u32 reserved8[176];
+	struct mtk_clk_cfg clk_misc_cfg_3;
+};
+check_member(mtk_topckgen_regs, clk_cfg_update[0], 0x0004);
+check_member(mtk_topckgen_regs, clk_cfg[0].set, 0x0014);
+check_member(mtk_topckgen_regs, clk_cfg[0].clr, 0x0018);
+check_member(mtk_topckgen_regs, clk_cfg[16].set, 0x0114);
+check_member(mtk_topckgen_regs, clk_cfg[16].clr, 0x0118);
+check_member(mtk_topckgen_regs, clk_misc_cfg_0, 0x0140);
+check_member(mtk_topckgen_regs, clk_mem_dfs_cfg, 0x0160);
+check_member(mtk_topckgen_regs, clk_dbg_cfg, 0x017C);
+check_member(mtk_topckgen_regs, clk_cfg_17.set, 0x0184);
+check_member(mtk_topckgen_regs, clk_cfg_17.clr, 0x0188);
+check_member(mtk_topckgen_regs, clk_cfg_18.set, 0x0194);
+check_member(mtk_topckgen_regs, clk_cfg_18.clr, 0x0198);
+check_member(mtk_topckgen_regs, clk_scp_cfg_0, 0x0200);
+check_member(mtk_topckgen_regs, clk26cali, 0x0220);
+check_member(mtk_topckgen_regs, clk_cfg_19.set, 0x0244);
+check_member(mtk_topckgen_regs, clk_cfg_19.clr, 0x0248);
+check_member(mtk_topckgen_regs, clk_misc_cfg_3.cfg, 0x0510);
+check_member(mtk_topckgen_regs, clk_misc_cfg_3.set, 0x0514);
+check_member(mtk_topckgen_regs, clk_misc_cfg_3.clr, 0x0518);
+
+struct mtk_apmixed_regs {
+	u32 reserved1[16];
+	u32 apll1_tuner_con0; /* 0x0040 */
+	u32 apll2_tuner_con0;
+	u32 reserved2[11];
+	u32 pllen_all_set; /* 0x0074 */
+	u32 pllen_all_clr;
+	u32 reserved3[2];
+	u32 pll_div_rstb_all_set; /* 0x0084 */
+	u32 reserved4[95];
+	u32 armpll_ll_con[2]; /* 0x0204 */
+	u32 reserved5[2];
+	u32 armpll_bl_con[2]; /* 0x0214 */
+	u32 reserved6[2];
+	u32 ccipll_con[2]; /* 0x0224 */
+	u32 reserved7[54];
+	u32 mainpll_con[2]; /* 0x0304 */
+	u32 reserved8[2];
+	u32 univpll_con[2]; /* 0x0314 */
+	u32 reserved9[2];
+	u32 mmpll_con[2]; /* 0x0324 */
+	u32 reserved10[2];
+	u32 emipll_con[2]; /* 0x0334 */
+	u32 reserved11[50];
+	u32 apll1_con[3]; /* 0x0404 */
+	u32 reserved12[2];
+	u32 apll2_con[3]; /* 0x0418 */
+	u32 reserved13[2];
+	u32 tvdpll1_con[2]; /* 0x042c */
+	u32 reserved14[2];
+	u32 tvdpll2_con[2]; /* 0x043c */
+	u32 reserved15[48];
+	u32 mfgpll_con[2]; /* 0x0504 */
+	u32 reserved16[2];
+	u32 ethpll_con[2]; /* 0x0514 */
+	u32 reserved17[2];
+	u32 msdcpll_con[2]; /* 0x0524 */
+	u32 reserved18[2];
+	u32 ufspll_con[2]; /* 0x0534 */
+	u32 reserved19[50];
+	u32 apupll_con[2]; /* 0x0604 */
+	u32 reserved20[2];
+	u32 apupll2_con[2]; /* 0x0614 */
+	u32 reserved21[57];
+	u32 ap_clksq_con0; /* 0x0700 */
+};
+check_member(mtk_apmixed_regs, apll1_tuner_con0, 0x0040);
+check_member(mtk_apmixed_regs, pllen_all_set, 0x0074);
+check_member(mtk_apmixed_regs, pll_div_rstb_all_set, 0x0084);
+check_member(mtk_apmixed_regs, armpll_ll_con[0], 0x0204);
+check_member(mtk_apmixed_regs, armpll_bl_con[0], 0x0214);
+check_member(mtk_apmixed_regs, ccipll_con[0], 0x0224);
+check_member(mtk_apmixed_regs, mainpll_con[0], 0x0304);
+check_member(mtk_apmixed_regs, univpll_con[0], 0x0314);
+check_member(mtk_apmixed_regs, mmpll_con[0], 0x0324);
+check_member(mtk_apmixed_regs, emipll_con[0], 0x0334);
+check_member(mtk_apmixed_regs, apll1_con[0], 0x0404);
+check_member(mtk_apmixed_regs, apll2_con[0], 0x0418);
+check_member(mtk_apmixed_regs, tvdpll1_con[0], 0x042C);
+check_member(mtk_apmixed_regs, tvdpll2_con[0], 0x043C);
+check_member(mtk_apmixed_regs, mfgpll_con[0], 0x0504);
+check_member(mtk_apmixed_regs, ethpll_con[0], 0x0514);
+check_member(mtk_apmixed_regs, msdcpll_con[0], 0x0524);
+check_member(mtk_apmixed_regs, ufspll_con[0], 0x0534);
+check_member(mtk_apmixed_regs, apupll_con[0], 0x0604);
+check_member(mtk_apmixed_regs, apupll2_con[0], 0x0614);
+check_member(mtk_apmixed_regs, ap_clksq_con0, 0x0700);
+
+struct mtk_pericfg_ao_regs {
+	u32 reserved1[4];
+	u32 pericfg_ao_peri_cg_0;
+	u32 pericfg_ao_peri_cg_1;
+	u32 pericfg_ao_peri_cg_2;
+	u32 reserved2[2];
+	u32 pericfg_ao_peri_cg_0_set;
+	u32 pericfg_ao_peri_cg_0_clr;
+	u32 pericfg_ao_peri_cg_1_set;
+	u32 pericfg_ao_peri_cg_1_clr;
+	u32 pericfg_ao_peri_cg_2_set;
+	u32 pericfg_ao_peri_cg_2_clr;
+};
+check_member(mtk_pericfg_ao_regs, pericfg_ao_peri_cg_0, 0x0010);
+check_member(mtk_pericfg_ao_regs, pericfg_ao_peri_cg_0_set, 0x0024);
+
+struct mtk_afe_regs {
+	u32 audio_audio_top[5];
+};
+
+struct mtk_ufscfg_ao_regs {
+	u32 reserved1;
+	u32 ufscfg_ao_reg_ufs_ao_cg_0;
+	u32 ufscfg_ao_reg_ufs_ao_cg_0_set;
+	u32 ufscfg_ao_reg_ufs_ao_cg_0_clr;
+};
+
+struct mtk_ufscfg_pdn_regs {
+	u32 reserved1;
+	u32 ufscfg_pdn_reg_ufs_pdn_cg_0;
+	u32 ufscfg_pdn_reg_ufs_pdn_cg_0_set;
+	u32 ufscfg_pdn_reg_ufs_pdn_cg_0_clr;
+};
+
+struct mtk_imp_iic_wrap_ws_regs {
+	u32 reserved1[896];
+	u32 imp_iic_wrap_ws_ap_clock_cg;
+	u32 imp_iic_wrap_ws_ap_clock_cg_clr;
+	u32 imp_iic_wrap_ws_ap_clock_cg_set;
+};
+check_member(mtk_imp_iic_wrap_ws_regs, imp_iic_wrap_ws_ap_clock_cg, 0x0E00);
+
+struct mtk_imp_iic_wrap_e_regs {
+	u32 reserved1[896];
+	u32 imp_iic_wrap_e_ap_clock_cg;
+	u32 imp_iic_wrap_e_ap_clock_cg_clr;
+	u32 imp_iic_wrap_e_ap_clock_cg_set;
+};
+check_member(mtk_imp_iic_wrap_e_regs, imp_iic_wrap_e_ap_clock_cg, 0x0E00);
+
+struct mtk_imp_iic_wrap_s_regs {
+	u32 reserved1[896];
+	u32 imp_iic_wrap_s_ap_clock_cg;
+	u32 imp_iic_wrap_s_ap_clock_cg_clr;
+	u32 imp_iic_wrap_s_ap_clock_cg_set;
+};
+check_member(mtk_imp_iic_wrap_s_regs, imp_iic_wrap_s_ap_clock_cg, 0x0E00);
+
+struct mtk_imp_iic_wrap_en_regs {
+	u32 reserved1[896];
+	u32 imp_iic_wrap_en_ap_clock_cg;
+	u32 imp_iic_wrap_en_ap_clock_cg_clr;
+	u32 imp_iic_wrap_en_ap_clock_cg_set;
+};
+check_member(mtk_imp_iic_wrap_en_regs, imp_iic_wrap_en_ap_clock_cg, 0x0E00);
+
+struct mtk_mfg_regs {
+	u32 mfg_mfg_cg_con;
+	u32 mfg_mfg_cg_con_set;
+	u32 mfg_mfg_cg_con_clr;
+};
+
+struct mtk_mmsys_config_regs {
+	u32 reserved1[64];
+	u32 mmsys_config_mmsys_cg_0;
+	u32 mmsys_config_mmsys_cg_0_set;
+	u32 mmsys_config_mmsys_cg_0_clr;
+	u32 reserved2[1];
+	u32 mmsys_config_mmsys_cg_1;
+	u32 mmsys_config_mmsys_cg_1_set;
+	u32 mmsys_config_mmsys_cg_1_clr;
+};
+check_member(mtk_mmsys_config_regs, mmsys_config_mmsys_cg_0, 0x0100);
+check_member(mtk_mmsys_config_regs, mmsys_config_mmsys_cg_1, 0x0110);
+
+struct mtk_imgsys1_regs {
+	u32 imgsys1_img_cg;
+	u32 imgsys1_img_cg_set;
+	u32 imgsys1_img_cg_clr;
+};
+
+struct mtk_imgsys2_regs {
+	u32 imgsys2_img_cg;
+	u32 imgsys2_img_cg_set;
+	u32 imgsys2_img_cg_clr;
+};
+
+struct mtk_vdec_core_regs {
+	u32 vdec_core_vdec_cken;
+	u32 vdec_core_vdec_cken_clr;
+	u32 vdec_core_larb_cken_con;
+	u32 vdec_core_larb_cken_con_clr;
+};
+
+struct mtk_venc_gcon_regs {
+	u32 venc_gcon_vencsys_cg;
+	u32 venc_gcon_vencsys_cg_set;
+	u32 venc_gcon_vencsys_cg_clr;
+};
+
+struct mtk_scp_iic_regs {
+	u32 reserved[900];
+	u32 scp_iic_ccu_clock_cg;
+	u32 scp_iic_ccu_clock_cg_clr;
+	u32 scp_iic_ccu_clock_cg_set;
+};
+check_member(mtk_scp_iic_regs, scp_iic_ccu_clock_cg, 0x0E10);
+
+struct mtk_scp_regs {
+	u32 reserved[85];
+	u32 scp_ap_spi_cg;
+	u32 scp_ap_spi_cg_clr;
+};
+check_member(mtk_scp_regs, scp_ap_spi_cg, 0x0154);
+
+struct mtk_vadsys_regs {
+	u32 vad_vadsys_ck_en;
+	u32 reserved1[95];
+	u32 vad_vow_audiodsp_sw_cg;
+};
+check_member(mtk_vadsys_regs, vad_vow_audiodsp_sw_cg, 0x0180);
+
+struct mtk_camsys_main_regs {
+	u32 camsys_main_camsys_cg;
+	u32 camsys_main_camsys_cg_set;
+	u32 camsys_main_camsys_cg_clr;
+};
+
+struct mtk_camsys_rawa_regs {
+	u32 camsys_rawa_camsys_cg;
+	u32 camsys_rawa_camsys_cg_set;
+	u32 camsys_rawa_camsys_cg_clr;
+};
+
+struct mtk_camsys_rawb_regs {
+	u32 camsys_rawb_camsys_cg;
+	u32 camsys_rawb_camsys_cg_set;
+	u32 camsys_rawb_camsys_cg_clr;
+};
+
+struct mtk_ipesys_regs {
+	u32 ipe_img_cg;
+	u32 ipe_img_cg_set;
+	u32 ipe_img_cg_clr;
+};
+
+struct mtk_vlpcfg_ao_regs {
+	u32 reserved[512];
+	u32 vlpcfg_ao_reg_debugtop_vlpao_ctrl;
+};
+check_member(mtk_vlpcfg_ao_regs, vlpcfg_ao_reg_debugtop_vlpao_ctrl, 0x0800);
+
+struct mtk_dvfsrc_top_regs {
+	u32 dvfsrc_top_dvfsrc_basic_control;
+};
+
+struct mtk_mminfra_config_regs {
+	u32 reserved1[64];
+	u32 mminfra_config_mminfra_cg_0;
+	u32 mminfra_config_mminfra_cg_0_set;
+	u32 mminfra_config_mminfra_cg_0_clr;
+	u32 reserved2[1];
+	u32 mminfra_config_mminfra_cg_1;
+	u32 mminfra_config_mminfra_cg_1_set;
+	u32 mminfra_config_mminfra_cg_1_clr;
+};
+check_member(mtk_mminfra_config_regs, mminfra_config_mminfra_cg_0, 0x0100);
+check_member(mtk_mminfra_config_regs, mminfra_config_mminfra_cg_1, 0x0110);
+
+struct mtk_gce_d_regs {
+	u32 reserved[60];
+	u32 gce_gce_ctl_int0;
+};
+check_member(mtk_gce_d_regs, gce_gce_ctl_int0, 0x00F0);
+
+struct mtk_gce_m_regs {
+	u32 reserved[60];
+	u32 mdp_gce_gce_ctl_int0;
+};
+check_member(mtk_gce_m_regs, mdp_gce_gce_ctl_int0, 0x00F0);
+
+struct mtk_mdpsys_config_regs {
+	u32 reserved1[64];
+	u32 mdpsys_config_mdpsys_cg_0;
+	u32 mdpsys_config_mdpsys_cg_0_set;
+	u32 mdpsys_config_mdpsys_cg_0_clr;
+	u32 reserved2[1];
+	u32 mdpsys_config_mdpsys_cg_1;
+	u32 mdpsys_config_mdpsys_cg_1_set;
+	u32 mdpsys_config_mdpsys_cg_1_clr;
+};
+check_member(mtk_mdpsys_config_regs, mdpsys_config_mdpsys_cg_0, 0x0100);
+check_member(mtk_mdpsys_config_regs, mdpsys_config_mdpsys_cg_1, 0x0110);
+
+struct mtk_dbgao_regs {
+	u32 reserved[28];
+	u32 dbgao_atb;
+};
+check_member(mtk_dbgao_regs, dbgao_atb, 0x0070);
+
+struct mtk_dem_regs {
+	u32 reserved1[11];
+	u32 dem_dbgbusclk_en;
+	u32 dem_dbgsysclk_en;
+	u32 reserved2[15];
+	u32 dem_atb;
+};
+check_member(mtk_dem_regs, dem_dbgbusclk_en, 0x002C);
+check_member(mtk_dem_regs, dem_atb, 0x0070);
+
+/* Fmeter Type */
+enum fmeter_id {
+	APLL1_CTRL,
+	APLL2_CTRL,
+	ARMPLL_BL_CTRL,
+	ARMPLL_LL_CTRL,
+	CCIPLL_CTRL,
+	MAINPLL_CTRL,
+	MMPLL_CTRL,
+	MSDCPLL_CTRL,
+	UFSPLL_CTRL,
+	UNIVPLL_CTRL,
+	EMIPLL_CTRL,
+	TVDPLL1_CTRL,
+	TVDPLL2_CTRL,
+	MFGPLL_CTRL,
+	ETHPLL_CTRL,
+	APUPLL_CTRL,
+	APUPLL2_CTRL,
+	VLP_CKSYS_TOP_CTRL,
+};
+
+/* PLL set rate list */
+enum pll_rate_type {
+	ARMPLL_LL_RATE = 0,
+	ARMPLL_BL_RATE,
+	CCIPLL_RATE,
+	PLL_RATE_NUM,
+};
+
+#define ARMPLL_BL_ID	6
+#define ARMPLL_LL_ID	8
+#define CCIPLL_ID	10
+
+enum {
+	ARMPLL_LL_HZ	= 1600UL * MHz,
+	ARMPLL_BL_HZ	= 1700UL * MHz,
+	CCIPLL_HZ	= 1140UL * MHz,
+	MAINPLL_HZ	= 2184UL * MHz,
+	UNIVPLL_HZ	= 2496UL * MHz,
+	MMPLL_HZ	= 2750UL * MHz,
+	MFGPLL_HZ	= 390 * MHz,
+	APLL1_HZ	= 180633600UL,
+	APLL2_HZ	= 196608UL * KHz,
+	EMIPLL_HZ	= 387 * MHz,
+	APUPLL2_HZ	= 230 * MHz,
+	APUPLL_HZ	= 330 * MHz,
+	TVDPLL1_HZ	= 594 * MHz,
+	TVDPLL2_HZ	= 594 * MHz,
+	ETHPLL_HZ	= 500 * MHz,
+	MSDCPLL_HZ	= 416 * MHz,
+	UFSPLL_HZ	= 594 * MHz,
+};
+
+enum {
+	CLK26M_HZ		= 26 * MHz,
+	UNIVPLL_D6_D2_HZ	= UNIVPLL_HZ / 6 / 2,
+};
+
+enum {
+	PCW_INTEGER_BITS = 8,
+};
+
+enum {
+	SPI_HZ	= UNIVPLL_D6_D2_HZ,
+	UART_HZ	= CLK26M_HZ,
+};
+
+enum {
+	PLL_EN_DELAY = 20,
+};
+
+enum {
+	MCU_DIV_MASK = 0x1f << 17,
+	MCU_DIV_1 = 0x8 << 17,
+
+	MCU_MUX_MASK = 0x3 << 9,
+	MCU_MUX_SRC_PLL = 0x1 << 9,
+	MCU_MUX_SRC_26M = 0x0 << 9,
+};
+
+/*
+ * Clock manager functions
+ */
+void mt_pll_post_init(void);
+u32 mt_get_vlpck_freq(u32 id);
+void mt_set_topck_default(void);
+
 #endif /* __SOC_MEDIATEK_MT8189_INCLUDE_SOC_PLL_H__ */
diff --git a/src/soc/mediatek/mt8189/pll.c b/src/soc/mediatek/mt8189/pll.c
new file mode 100644
index 0000000000..24c7cc59e9
--- /dev/null
+++ b/src/soc/mediatek/mt8189/pll.c
@@ -0,0 +1,727 @@
+/* SPDX-License-Identifier: GPL-2.0-only OR MIT */
+
+/*
+ * This file is created based on MT8189 Functional Specification
+ * Chapter number: 8.1
+ */
+
+#include <console/console.h>
+#include <delay.h>
+#include <device/mmio.h>
+#include <timer.h>
+#include <soc/addressmap.h>
+#include <soc/mtcmos.h>
+#include <soc/pll.h>
+#include <soc/spm.h>
+#include <soc/spm_mtcmos.h>
+
+#define VLP_FM_WAIT_TIME	40
+
+enum mux_id {
+	CLK_TOP_AXI_SEL,
+	CLK_TOP_AXI_PERI_SEL,
+	CLK_TOP_AXI_U_SEL,
+	CLK_TOP_BUS_AXIMEM_SEL,
+	CLK_TOP_DISP0_SEL,
+	CLK_TOP_MMINFRA_SEL,
+	CLK_TOP_UART_SEL,
+	CLK_TOP_SPI0_SEL,
+	CLK_TOP_SPI1_SEL,
+	CLK_TOP_SPI2_SEL,
+	CLK_TOP_SPI3_SEL,
+	CLK_TOP_SPI4_SEL,
+	CLK_TOP_SPI5_SEL,
+	CLK_TOP_MSDC_MACRO_0P_SEL,
+	CLK_TOP_MSDC50_0_HCLK_SEL,
+	CLK_TOP_MSDC50_0_SEL,
+	CLK_TOP_AES_MSDCFDE_SEL,
+	CLK_TOP_MSDC_MACRO_1P_SEL,
+	CLK_TOP_MSDC30_1_SEL,
+	CLK_TOP_MSDC30_1_HCLK_SEL,
+	CLK_TOP_MSDC_MACRO_2P_SEL,
+	CLK_TOP_MSDC30_2_SEL,
+	CLK_TOP_MSDC30_2_HCLK_SEL,
+	CLK_TOP_AUD_INTBUS_SEL,
+	CLK_TOP_ATB_SEL,
+	CLK_TOP_DISP_PWM_SEL,
+	CLK_TOP_USB_TOP_P0_SEL,
+	CLK_TOP_USB_XHCI_P0_SEL,
+	CLK_TOP_USB_TOP_P1_SEL,
+	CLK_TOP_USB_XHCI_P1_SEL,
+	CLK_TOP_USB_TOP_P2_SEL,
+	CLK_TOP_USB_XHCI_P2_SEL,
+	CLK_TOP_USB_TOP_P3_SEL,
+	CLK_TOP_USB_XHCI_P3_SEL,
+	CLK_TOP_USB_TOP_P4_SEL,
+	CLK_TOP_USB_XHCI_P4_SEL,
+	CLK_TOP_I2C_SEL,
+	CLK_TOP_AUD_ENGEN1_SEL,
+	CLK_TOP_AUD_ENGEN2_SEL,
+	CLK_TOP_AES_UFSFDE_SEL,
+	CLK_TOP_U_SEL,
+	CLK_TOP_U_MBIST_SEL,
+	CLK_TOP_AUD_1_SEL,
+	CLK_TOP_AUD_2_SEL,
+	CLK_TOP_PWM_SEL,
+	CLK_TOP_AUDIO_H_SEL,
+	CLK_TOP_MCUPM_SEL,
+	CLK_TOP_MEM_SUB_SEL,
+	CLK_TOP_MEM_SUB_U_SEL,
+	CLK_TOP_DXCC_SEL,
+	CLK_TOP_DP_SEL,
+	CLK_TOP_EDP_SEL,
+	CLK_TOP_EDP_FAVT_SEL,
+	CLK_TOP_SFLASH_SEL,
+	CLK_TOP_ECC_SEL,
+	CLK_TOP_APLL_I2SIN0_MCK_SEL,
+	CLK_TOP_APLL_I2SIN1_MCK_SEL,
+	CLK_TOP_APLL_I2SIN4_MCK_SEL,
+	CLK_TOP_APLL_I2SOUT0_MCK_SEL,
+	CLK_TOP_APLL_I2SOUT1_MCK_SEL,
+	CLK_TOP_APLL_I2SOUT4_MCK_SEL,
+	CLK_TOP_APLL_TDMOUT_MCK_SEL,
+};
+
+enum vlp_mux_id {
+	CLK_VLP_CK_SCP_SEL,
+	CLK_VLP_CK_PWRAP_ULPOSC_SEL,
+	CLK_VLP_CK_SPMI_P_MST_SEL,
+	CLK_VLP_CK_DVFSRC_SEL,
+	CLK_VLP_CK_PWM_VLP_SEL,
+	CLK_VLP_CK_AXI_VLP_SEL,
+	CLK_VLP_CK_SYSTIMER_26M_SEL,
+	CLK_VLP_CK_SSPM_SEL,
+	CLK_VLP_CK_SSPM_F26M_SEL,
+	CLK_VLP_CK_SRCK_SEL,
+	CLK_VLP_CK_SCP_SPI_SEL,
+	CLK_VLP_CK_SCP_IIC_SEL,
+	CLK_VLP_CK_SCP_SPI_HIGH_SPD_SEL,
+	CLK_VLP_CK_SCP_IIC_HIGH_SPD_SEL,
+	CLK_VLP_CK_SSPM_ULPOSC_SEL,
+	CLK_VLP_CK_APXGPT_26M_SEL,
+	CLK_VLP_CK_AUD_ADC_SEL,
+	CLK_VLP_CK_KP_IRQ_GEN_SEL
+};
+
+struct mux_sel {
+	u8 id;
+	u8 sel;
+};
+
+struct vlp_mux_sel {
+	u8 id;
+	u8 sel;
+};
+
+#define MUX(_id, _sys, _clk_cfg, _mux_shift, _mux_width)\
+	[_id] = {					\
+		.reg = &_sys->_clk_cfg.cfg,		\
+		.set_reg = &_sys->_clk_cfg.set,		\
+		.clr_reg = &_sys->_clk_cfg.clr,		\
+		.mux_shift = _mux_shift,		\
+		.mux_width = _mux_width,		\
+	}
+
+#define MUX_UPD(_id, _sys, _clk_cfg, _mux_shift, _mux_width, _upd_reg, _upd_shift)\
+	[_id] = {					\
+		.reg = &_sys->_clk_cfg.cfg,		\
+		.set_reg = &_sys->_clk_cfg.set,		\
+		.clr_reg = &_sys->_clk_cfg.clr,		\
+		.mux_shift = _mux_shift,		\
+		.mux_width = _mux_width,		\
+		.upd_reg = &_sys->_upd_reg,		\
+		.upd_shift = _upd_shift,		\
+	}
+
+#define CKSYS_MUX(_id, _clk_cfg, _mux_shift, _mux_width)\
+	MUX(_id, mtk_topckgen, _clk_cfg, _mux_shift, _mux_width)
+
+#define CKSYS_MUX_UPD(_id, _clk_cfg, _mux_shift, _mux_width, _upd_reg, _upd_shift)\
+	MUX_UPD(_id, mtk_topckgen, _clk_cfg, _mux_shift, _mux_width, _upd_reg, _upd_shift)
+
+#define VLP_MUX_UPD(_id, _clk_cfg, _mux_shift, _mux_width, _upd_shift)\
+	MUX_UPD(_id, mtk_vlpsys, _clk_cfg, _mux_shift, _mux_width, vlp_clk_cfg_update, \
+		_upd_shift)
+
+static const struct mux muxes[] = {
+	CKSYS_MUX_UPD(CLK_TOP_AXI_SEL, clk_cfg[0], 0, 3, clk_cfg_update[0], 0),
+	CKSYS_MUX_UPD(CLK_TOP_AXI_PERI_SEL, clk_cfg[0], 8, 2, clk_cfg_update[0], 1),
+	CKSYS_MUX_UPD(CLK_TOP_AXI_U_SEL, clk_cfg[0], 16, 2, clk_cfg_update[0], 2),
+	CKSYS_MUX_UPD(CLK_TOP_BUS_AXIMEM_SEL, clk_cfg[0], 24, 3, clk_cfg_update[0], 3),
+	CKSYS_MUX_UPD(CLK_TOP_DISP0_SEL, clk_cfg[1], 0, 4, clk_cfg_update[0], 4),
+	CKSYS_MUX_UPD(CLK_TOP_MMINFRA_SEL, clk_cfg[1], 8, 4, clk_cfg_update[0], 5),
+	CKSYS_MUX_UPD(CLK_TOP_UART_SEL, clk_cfg[1], 16, 1, clk_cfg_update[0], 6),
+	CKSYS_MUX_UPD(CLK_TOP_SPI0_SEL, clk_cfg[1], 24, 3, clk_cfg_update[0], 7),
+	CKSYS_MUX_UPD(CLK_TOP_SPI1_SEL, clk_cfg[2], 0, 3, clk_cfg_update[0], 8),
+	CKSYS_MUX_UPD(CLK_TOP_SPI2_SEL, clk_cfg[2], 8, 3, clk_cfg_update[0], 9),
+	CKSYS_MUX_UPD(CLK_TOP_SPI3_SEL, clk_cfg[2], 16, 3, clk_cfg_update[0], 10),
+	CKSYS_MUX_UPD(CLK_TOP_SPI4_SEL, clk_cfg[2], 24, 3, clk_cfg_update[0], 11),
+	CKSYS_MUX_UPD(CLK_TOP_SPI5_SEL, clk_cfg[3], 0, 3, clk_cfg_update[0], 12),
+	CKSYS_MUX_UPD(CLK_TOP_MSDC_MACRO_0P_SEL, clk_cfg[3], 8, 2, clk_cfg_update[0], 13),
+	CKSYS_MUX_UPD(CLK_TOP_MSDC50_0_HCLK_SEL, clk_cfg[3], 16, 2, clk_cfg_update[0], 14),
+	CKSYS_MUX_UPD(CLK_TOP_MSDC50_0_SEL, clk_cfg[3], 24, 3, clk_cfg_update[0], 15),
+	CKSYS_MUX_UPD(CLK_TOP_AES_MSDCFDE_SEL, clk_cfg[4], 0, 3, clk_cfg_update[0], 16),
+	CKSYS_MUX_UPD(CLK_TOP_MSDC_MACRO_1P_SEL, clk_cfg[4], 8, 2, clk_cfg_update[0], 17),
+	CKSYS_MUX_UPD(CLK_TOP_MSDC30_1_SEL, clk_cfg[4], 16, 3, clk_cfg_update[0], 18),
+	CKSYS_MUX_UPD(CLK_TOP_MSDC30_1_HCLK_SEL, clk_cfg[4], 24, 2, clk_cfg_update[0], 19),
+	CKSYS_MUX_UPD(CLK_TOP_MSDC_MACRO_2P_SEL, clk_cfg[5], 0, 2, clk_cfg_update[0], 20),
+	CKSYS_MUX_UPD(CLK_TOP_MSDC30_2_SEL, clk_cfg[5], 8, 3, clk_cfg_update[0], 21),
+	CKSYS_MUX_UPD(CLK_TOP_MSDC30_2_HCLK_SEL, clk_cfg[5], 16, 2, clk_cfg_update[0], 22),
+	CKSYS_MUX_UPD(CLK_TOP_AUD_INTBUS_SEL, clk_cfg[5], 24, 2, clk_cfg_update[0], 23),
+	CKSYS_MUX_UPD(CLK_TOP_ATB_SEL, clk_cfg[6], 0, 2, clk_cfg_update[0], 24),
+	CKSYS_MUX_UPD(CLK_TOP_DISP_PWM_SEL, clk_cfg[6], 8, 3, clk_cfg_update[0], 25),
+	CKSYS_MUX_UPD(CLK_TOP_USB_TOP_P0_SEL, clk_cfg[6], 16, 2, clk_cfg_update[0], 26),
+	CKSYS_MUX_UPD(CLK_TOP_USB_XHCI_P0_SEL, clk_cfg[6], 24, 2, clk_cfg_update[0], 27),
+	CKSYS_MUX_UPD(CLK_TOP_USB_TOP_P1_SEL, clk_cfg[7], 0, 2, clk_cfg_update[0], 28),
+	CKSYS_MUX_UPD(CLK_TOP_USB_XHCI_P1_SEL, clk_cfg[7], 8, 2, clk_cfg_update[0], 29),
+	CKSYS_MUX_UPD(CLK_TOP_USB_TOP_P2_SEL, clk_cfg[7], 16, 2, clk_cfg_update[0], 30),
+	CKSYS_MUX_UPD(CLK_TOP_USB_XHCI_P2_SEL, clk_cfg[7], 24, 2, clk_cfg_update[1], 0),
+	CKSYS_MUX_UPD(CLK_TOP_USB_TOP_P3_SEL, clk_cfg[8], 0, 2, clk_cfg_update[1], 1),
+	CKSYS_MUX_UPD(CLK_TOP_USB_XHCI_P3_SEL, clk_cfg[8], 8, 2, clk_cfg_update[1], 2),
+	CKSYS_MUX_UPD(CLK_TOP_USB_TOP_P4_SEL, clk_cfg[8], 16, 2, clk_cfg_update[1], 3),
+	CKSYS_MUX_UPD(CLK_TOP_USB_XHCI_P4_SEL, clk_cfg[8], 24, 2, clk_cfg_update[1], 4),
+	CKSYS_MUX_UPD(CLK_TOP_I2C_SEL, clk_cfg[9], 0, 2, clk_cfg_update[1], 5),
+	CKSYS_MUX_UPD(CLK_TOP_AUD_ENGEN1_SEL, clk_cfg[9], 24, 2, clk_cfg_update[1], 8),
+	CKSYS_MUX_UPD(CLK_TOP_AUD_ENGEN2_SEL, clk_cfg[10], 0, 2, clk_cfg_update[1], 9),
+	CKSYS_MUX_UPD(CLK_TOP_AES_UFSFDE_SEL, clk_cfg[10], 8, 3, clk_cfg_update[1], 10),
+	CKSYS_MUX_UPD(CLK_TOP_U_SEL, clk_cfg[10], 16, 3, clk_cfg_update[1], 11),
+	CKSYS_MUX_UPD(CLK_TOP_U_MBIST_SEL, clk_cfg[10], 24, 2, clk_cfg_update[1], 12),
+	CKSYS_MUX_UPD(CLK_TOP_AUD_1_SEL, clk_cfg[11], 0, 1, clk_cfg_update[1], 13),
+	CKSYS_MUX_UPD(CLK_TOP_AUD_2_SEL, clk_cfg[11], 8, 1, clk_cfg_update[1], 14),
+	CKSYS_MUX_UPD(CLK_TOP_PWM_SEL, clk_cfg[12], 0, 1, clk_cfg_update[1], 17),
+	CKSYS_MUX_UPD(CLK_TOP_AUDIO_H_SEL, clk_cfg[12], 8, 2, clk_cfg_update[1], 18),
+	CKSYS_MUX_UPD(CLK_TOP_MCUPM_SEL, clk_cfg[12], 16, 2, clk_cfg_update[1], 19),
+	CKSYS_MUX_UPD(CLK_TOP_MEM_SUB_SEL, clk_cfg[12], 24, 4, clk_cfg_update[1], 20),
+	CKSYS_MUX_UPD(CLK_TOP_MEM_SUB_U_SEL, clk_cfg[13], 8, 3, clk_cfg_update[1], 22),
+	CKSYS_MUX_UPD(CLK_TOP_DXCC_SEL, clk_cfg[15], 24, 2, clk_cfg_update[2], 1),
+	CKSYS_MUX_UPD(CLK_TOP_DP_SEL, clk_cfg[16], 16, 3, clk_cfg_update[2], 4),
+	CKSYS_MUX_UPD(CLK_TOP_EDP_SEL, clk_cfg[16], 24, 3, clk_cfg_update[2], 5),
+	CKSYS_MUX_UPD(CLK_TOP_EDP_FAVT_SEL, clk_cfg_17, 0, 3, clk_cfg_update[2], 6),
+	CKSYS_MUX_UPD(CLK_TOP_SFLASH_SEL, clk_cfg_18, 0, 3, clk_cfg_update[2], 10),
+	CKSYS_MUX_UPD(CLK_TOP_ECC_SEL, clk_cfg_19, 8, 3, clk_cfg_update[2], 15),
+};
+
+static const struct mux_sel mux_sels[] = {
+	{ .id = CLK_TOP_AXI_SEL, .sel = 2 },
+	{ .id = CLK_TOP_AXI_PERI_SEL, .sel = 2 },
+	{ .id = CLK_TOP_AXI_U_SEL, .sel = 2 },
+	{ .id = CLK_TOP_BUS_AXIMEM_SEL, .sel = 2 },
+	{ .id = CLK_TOP_DISP0_SEL, .sel = 11 },
+	{ .id = CLK_TOP_MMINFRA_SEL, .sel = 14 },
+	{ .id = CLK_TOP_UART_SEL, .sel = 1 },
+	{ .id = CLK_TOP_SPI0_SEL, .sel = 1 },
+	{ .id = CLK_TOP_SPI1_SEL, .sel = 1 },
+	{ .id = CLK_TOP_SPI2_SEL, .sel = 1 },
+	{ .id = CLK_TOP_SPI3_SEL, .sel = 1 },
+	{ .id = CLK_TOP_SPI4_SEL, .sel = 1 },
+	{ .id = CLK_TOP_SPI5_SEL, .sel = 1 },
+	{ .id = CLK_TOP_MSDC_MACRO_0P_SEL, .sel = 1 },
+	{ .id = CLK_TOP_MSDC50_0_HCLK_SEL, .sel = 1 },
+	{ .id = CLK_TOP_MSDC50_0_SEL, .sel = 1 },
+	{ .id = CLK_TOP_AES_MSDCFDE_SEL, .sel = 4 },
+	{ .id = CLK_TOP_MSDC_MACRO_1P_SEL, .sel = 1 },
+	{ .id = CLK_TOP_MSDC30_1_SEL, .sel = 4 },
+	{ .id = CLK_TOP_MSDC30_1_HCLK_SEL, .sel = 1 },
+	{ .id = CLK_TOP_MSDC_MACRO_2P_SEL, .sel = 1 },
+	{ .id = CLK_TOP_MSDC30_2_SEL, .sel = 4 },
+	{ .id = CLK_TOP_MSDC30_2_HCLK_SEL, .sel = 1 },
+	{ .id = CLK_TOP_AUD_INTBUS_SEL, .sel = 1 },
+	{ .id = CLK_TOP_ATB_SEL, .sel = 1 },
+	{ .id = CLK_TOP_DISP_PWM_SEL, .sel = 6 },
+	{ .id = CLK_TOP_USB_TOP_P0_SEL, .sel = 1 },
+	{ .id = CLK_TOP_USB_XHCI_P0_SEL, .sel = 1 },
+	{ .id = CLK_TOP_USB_TOP_P1_SEL, .sel = 1 },
+	{ .id = CLK_TOP_USB_XHCI_P1_SEL, .sel = 1 },
+	{ .id = CLK_TOP_USB_TOP_P2_SEL, .sel = 1 },
+	{ .id = CLK_TOP_USB_XHCI_P2_SEL, .sel = 1 },
+	{ .id = CLK_TOP_USB_TOP_P3_SEL, .sel = 1 },
+	{ .id = CLK_TOP_USB_XHCI_P3_SEL, .sel = 1 },
+	{ .id = CLK_TOP_USB_TOP_P4_SEL, .sel = 1 },
+	{ .id = CLK_TOP_USB_XHCI_P4_SEL, .sel = 1 },
+	{ .id = CLK_TOP_I2C_SEL, .sel = 2 },
+	{ .id = CLK_TOP_AUD_ENGEN1_SEL, .sel = 2 },
+	{ .id = CLK_TOP_AUD_ENGEN2_SEL, .sel = 2 },
+	{ .id = CLK_TOP_AES_UFSFDE_SEL, .sel = 1 },
+	{ .id = CLK_TOP_U_SEL, .sel = 5 },
+	{ .id = CLK_TOP_U_MBIST_SEL, .sel = 3 },
+	{ .id = CLK_TOP_AUD_1_SEL, .sel = 1 },
+	{ .id = CLK_TOP_AUD_2_SEL, .sel = 1 },
+	{ .id = CLK_TOP_PWM_SEL, .sel = 0 },
+	{ .id = CLK_TOP_AUDIO_H_SEL, .sel = 3 },
+	{ .id = CLK_TOP_MCUPM_SEL, .sel = 2 },
+	{ .id = CLK_TOP_MEM_SUB_SEL, .sel = 9 },
+	{ .id = CLK_TOP_MEM_SUB_U_SEL, .sel = 7 },
+	{ .id = CLK_TOP_DXCC_SEL, .sel = 1 },
+	{ .id = CLK_TOP_DP_SEL, .sel = 4 },
+	{ .id = CLK_TOP_EDP_SEL, .sel = 4 },
+	{ .id = CLK_TOP_EDP_FAVT_SEL, .sel = 4 },
+	{ .id = CLK_TOP_SFLASH_SEL, .sel = 0 },
+	{ .id = CLK_TOP_ECC_SEL, .sel = 5 },
+};
+
+static const struct mux vlp_muxes[] = {
+	VLP_MUX_UPD(CLK_VLP_CK_SCP_SEL, vlp_clk_cfg[0], 0, 4, 0),
+	VLP_MUX_UPD(CLK_VLP_CK_PWRAP_ULPOSC_SEL, vlp_clk_cfg[0], 8, 3, 1),
+	VLP_MUX_UPD(CLK_VLP_CK_SPMI_P_MST_SEL, vlp_clk_cfg[0], 16, 4, 2),
+	VLP_MUX_UPD(CLK_VLP_CK_DVFSRC_SEL, vlp_clk_cfg[0], 24, 1, 3),
+	VLP_MUX_UPD(CLK_VLP_CK_PWM_VLP_SEL, vlp_clk_cfg[1], 0, 3, 4),
+	VLP_MUX_UPD(CLK_VLP_CK_AXI_VLP_SEL, vlp_clk_cfg[1], 8, 3, 5),
+	VLP_MUX_UPD(CLK_VLP_CK_SYSTIMER_26M_SEL, vlp_clk_cfg[1], 16, 1, 6),
+	VLP_MUX_UPD(CLK_VLP_CK_SSPM_SEL, vlp_clk_cfg[1], 24, 3, 7),
+	VLP_MUX_UPD(CLK_VLP_CK_SSPM_F26M_SEL, vlp_clk_cfg[2], 0, 1, 8),
+	VLP_MUX_UPD(CLK_VLP_CK_SRCK_SEL, vlp_clk_cfg[2], 8, 1, 9),
+	VLP_MUX_UPD(CLK_VLP_CK_SCP_SPI_SEL, vlp_clk_cfg[2], 16, 2, 10),
+	VLP_MUX_UPD(CLK_VLP_CK_SCP_IIC_SEL, vlp_clk_cfg[2], 24, 2, 11),
+	VLP_MUX_UPD(CLK_VLP_CK_SCP_SPI_HIGH_SPD_SEL, vlp_clk_cfg[3], 0, 2, 12),
+	VLP_MUX_UPD(CLK_VLP_CK_SCP_IIC_HIGH_SPD_SEL, vlp_clk_cfg[3], 8, 2, 13),
+	VLP_MUX_UPD(CLK_VLP_CK_SSPM_ULPOSC_SEL, vlp_clk_cfg[3], 16, 2, 14),
+	VLP_MUX_UPD(CLK_VLP_CK_APXGPT_26M_SEL, vlp_clk_cfg[3], 24, 1, 15),
+	VLP_MUX_UPD(CLK_VLP_CK_AUD_ADC_SEL, vlp_clk_cfg[5], 16, 2, 22),
+	VLP_MUX_UPD(CLK_VLP_CK_KP_IRQ_GEN_SEL, vlp_clk_cfg[5], 24, 3, 23),
+};
+
+static const struct vlp_mux_sel vlp_mux_sels[] = {
+	{ .id = CLK_VLP_CK_SCP_SEL, .sel = 0 },
+	{ .id = CLK_VLP_CK_PWRAP_ULPOSC_SEL, .sel = 0 },
+	{ .id = CLK_VLP_CK_SPMI_P_MST_SEL, .sel = 0 },
+	{ .id = CLK_VLP_CK_DVFSRC_SEL, .sel = 0 },
+	{ .id = CLK_VLP_CK_PWM_VLP_SEL, .sel = 0 },
+	{ .id = CLK_VLP_CK_AXI_VLP_SEL, .sel = 4 },
+	{ .id = CLK_VLP_CK_SYSTIMER_26M_SEL, .sel = 0 },
+	{ .id = CLK_VLP_CK_SSPM_SEL, .sel = 4 },
+	{ .id = CLK_VLP_CK_SSPM_F26M_SEL, .sel = 0 },
+	{ .id = CLK_VLP_CK_SRCK_SEL, .sel = 0 },
+	{ .id = CLK_VLP_CK_SCP_SPI_SEL, .sel = 0 },
+	{ .id = CLK_VLP_CK_SCP_IIC_SEL, .sel = 0 },
+	{ .id = CLK_VLP_CK_SCP_SPI_HIGH_SPD_SEL, .sel = 0 },
+	{ .id = CLK_VLP_CK_SCP_IIC_HIGH_SPD_SEL, .sel = 0 },
+	{ .id = CLK_VLP_CK_SSPM_ULPOSC_SEL, .sel = 0 },
+	{ .id = CLK_VLP_CK_APXGPT_26M_SEL, .sel = 0 },
+	{ .id = CLK_VLP_CK_AUD_ADC_SEL, .sel = 1 },
+	{ .id = CLK_VLP_CK_KP_IRQ_GEN_SEL, .sel = 4 }
+};
+
+enum pll_id {
+	CLK_APMIXED_ARMPLL_LL,
+	CLK_APMIXED_ARMPLL_BL,
+	CLK_APMIXED_CCIPLL,
+	CLK_APMIXED_MAINPLL,
+	CLK_APMIXED_UNIVPLL,
+	CLK_APMIXED_MMPLL,
+	CLK_APMIXED_MFGPLL,
+	CLK_APMIXED_APLL1,
+	CLK_APMIXED_APLL2,
+	CLK_APMIXED_EMIPLL,
+	CLK_APMIXED_APUPLL2,
+	CLK_APMIXED_APUPLL,
+	CLK_APMIXED_TVDPLL1,
+	CLK_APMIXED_TVDPLL2,
+	CLK_APMIXED_ETHPLL,
+	CLK_APMIXED_MSDCPLL,
+	CLK_APMIXED_UFSPLL
+};
+
+struct rate {
+	u8 id; /* enum pll_id */
+	u32 rate;
+};
+
+static const struct rate pll_rates[] = {
+	{ CLK_APMIXED_ARMPLL_LL, ARMPLL_LL_HZ },
+	{ CLK_APMIXED_ARMPLL_BL, ARMPLL_BL_HZ },
+	{ CLK_APMIXED_CCIPLL, CCIPLL_HZ },
+	{ CLK_APMIXED_MAINPLL, MAINPLL_HZ },
+	{ CLK_APMIXED_UNIVPLL, UNIVPLL_HZ },
+	{ CLK_APMIXED_MMPLL, MMPLL_HZ },
+	{ CLK_APMIXED_MFGPLL, MFGPLL_HZ },
+	{ CLK_APMIXED_APLL1, APLL1_HZ },
+	{ CLK_APMIXED_APLL2, APLL2_HZ },
+	{ CLK_APMIXED_EMIPLL, EMIPLL_HZ },
+	{ CLK_APMIXED_APUPLL2, APUPLL2_HZ },
+	{ CLK_APMIXED_APUPLL, APUPLL_HZ },
+	{ CLK_APMIXED_TVDPLL1, TVDPLL1_HZ },
+	{ CLK_APMIXED_TVDPLL2, TVDPLL2_HZ },
+	{ CLK_APMIXED_ETHPLL, ETHPLL_HZ },
+	{ CLK_APMIXED_MSDCPLL, MSDCPLL_HZ },
+	{ CLK_APMIXED_UFSPLL, UFSPLL_HZ }
+};
+
+static const u32 pll_div_rate[] = {
+	3800UL * MHz,
+	1900 * MHz,
+	950 * MHz,
+	475 * MHz,
+	237500 * KHz,
+	0,
+};
+
+#define PLL_SYS(_id, _reg, _rstb, _pcwbits, _div_reg, _div_shift,	\
+	_pcw_reg, _pcw_shift, _div_rate)				\
+	[_id] = {							\
+		.reg = &mtk_apmixed->_reg,				\
+		.rstb_shift = _rstb,					\
+		.pcwbits = _pcwbits,					\
+		.div_reg = &mtk_apmixed->_div_reg,			\
+		.div_shift = _div_shift,				\
+		.pcw_reg = &mtk_apmixed->_pcw_reg,			\
+		.pcw_shift = _pcw_shift,				\
+		.div_rate = _div_rate,					\
+	}
+
+static const struct pll plls[] = {
+	PLL_SYS(CLK_APMIXED_ARMPLL_LL, armpll_ll_con[0], NO_RSTB_SHIFT, 22,
+		armpll_ll_con[1], 24, armpll_ll_con[1], 0, pll_div_rate),
+	PLL_SYS(CLK_APMIXED_ARMPLL_BL, armpll_bl_con[0], NO_RSTB_SHIFT, 22,
+		armpll_bl_con[1], 24, armpll_bl_con[1], 0, pll_div_rate),
+	PLL_SYS(CLK_APMIXED_CCIPLL, ccipll_con[0], NO_RSTB_SHIFT, 22,
+		ccipll_con[1], 24, ccipll_con[1], 0, pll_div_rate),
+	PLL_SYS(CLK_APMIXED_MAINPLL, mainpll_con[0], 23, 22,
+		mainpll_con[1], 24, mainpll_con[1], 0, pll_div_rate),
+	PLL_SYS(CLK_APMIXED_UNIVPLL, univpll_con[0], 23, 22,
+		univpll_con[1], 24, univpll_con[1], 0, pll_div_rate),
+	PLL_SYS(CLK_APMIXED_MMPLL, mmpll_con[0], 23, 22,
+		mmpll_con[1], 24, mmpll_con[1], 0, pll_div_rate),
+	PLL_SYS(CLK_APMIXED_MFGPLL, mfgpll_con[0], NO_RSTB_SHIFT, 22,
+		mfgpll_con[1], 24, mfgpll_con[1], 0, pll_div_rate),
+	PLL_SYS(CLK_APMIXED_APLL1, apll1_con[0], NO_RSTB_SHIFT, 32,
+		apll1_con[1], 24, apll1_con[2], 0, pll_div_rate),
+	PLL_SYS(CLK_APMIXED_APLL2, apll2_con[0], NO_RSTB_SHIFT, 32,
+		apll2_con[1], 24, apll2_con[2], 0, pll_div_rate),
+	PLL_SYS(CLK_APMIXED_EMIPLL, emipll_con[0], NO_RSTB_SHIFT, 22,
+		emipll_con[1], 24, emipll_con[1], 0, pll_div_rate),
+	PLL_SYS(CLK_APMIXED_APUPLL2, apupll2_con[0], NO_RSTB_SHIFT, 22,
+		apupll2_con[1], 24, apupll2_con[1], 0, pll_div_rate),
+	PLL_SYS(CLK_APMIXED_APUPLL, apupll_con[0], NO_RSTB_SHIFT, 22,
+		apupll_con[1], 24, apupll_con[1], 0, pll_div_rate),
+	PLL_SYS(CLK_APMIXED_TVDPLL1, tvdpll1_con[0], NO_RSTB_SHIFT, 22,
+		tvdpll1_con[1], 24, tvdpll1_con[1], 0, pll_div_rate),
+	PLL_SYS(CLK_APMIXED_TVDPLL2, tvdpll2_con[0], NO_RSTB_SHIFT, 22,
+		tvdpll2_con[1], 24, tvdpll2_con[1], 0, pll_div_rate),
+	PLL_SYS(CLK_APMIXED_ETHPLL, ethpll_con[0], NO_RSTB_SHIFT, 22,
+		ethpll_con[1], 24, ethpll_con[1], 0, pll_div_rate),
+	PLL_SYS(CLK_APMIXED_MSDCPLL, msdcpll_con[0], NO_RSTB_SHIFT, 22,
+		msdcpll_con[1], 24, msdcpll_con[1], 0, pll_div_rate),
+	PLL_SYS(CLK_APMIXED_UFSPLL, ufspll_con[0], NO_RSTB_SHIFT, 22,
+		ufspll_con[1], 24, ufspll_con[1], 0, pll_div_rate),
+};
+
+struct pll_reg_list {
+	const char *name;
+	void *div_reg;
+	void *con0;
+	void *con1;
+};
+
+struct fmeter_data {
+	u8 id;
+	void *pll_con0;
+	void *pll_con1;
+	void *con0;
+	void *con1;
+};
+
+static const struct fmeter_data fmd[] = {
+	[APLL1_CTRL] = {APLL1_CTRL, &mtk_apmixed->apll1_con[0]},
+	[APLL2_CTRL] = {APLL2_CTRL, &mtk_apmixed->apll2_con[0]},
+	[ARMPLL_BL_CTRL] = {ARMPLL_BL_CTRL, &mtk_apmixed->armpll_bl_con[0]},
+	[ARMPLL_LL_CTRL] = {ARMPLL_LL_CTRL, &mtk_apmixed->armpll_ll_con[0]},
+	[CCIPLL_CTRL] = {CCIPLL_CTRL, &mtk_apmixed->ccipll_con[0]},
+	[MAINPLL_CTRL] = {MAINPLL_CTRL, &mtk_apmixed->mainpll_con[0]},
+	[MMPLL_CTRL] = {MMPLL_CTRL, &mtk_apmixed->mmpll_con[0]},
+	[MSDCPLL_CTRL] = {MSDCPLL_CTRL, &mtk_apmixed->msdcpll_con[0]},
+	[UFSPLL_CTRL] = {UFSPLL_CTRL, &mtk_apmixed->ufspll_con[0]},
+	[UNIVPLL_CTRL] = {UNIVPLL_CTRL, &mtk_apmixed->univpll_con[0]},
+	[EMIPLL_CTRL] = {EMIPLL_CTRL, &mtk_apmixed->emipll_con[0]},
+	[TVDPLL1_CTRL] = {TVDPLL1_CTRL, &mtk_apmixed->tvdpll1_con[0]},
+	[TVDPLL2_CTRL] = {TVDPLL2_CTRL, &mtk_apmixed->tvdpll2_con[0]},
+	[MFGPLL_CTRL] = {MFGPLL_CTRL, &mtk_apmixed->mfgpll_con[0]},
+	[ETHPLL_CTRL] = {ETHPLL_CTRL, &mtk_apmixed->ethpll_con[0]},
+	[APUPLL_CTRL] = {APUPLL_CTRL, &mtk_apmixed->apupll_con[0]},
+	[APUPLL2_CTRL] = {APUPLL2_CTRL, &mtk_apmixed->apupll2_con[0]},
+	[VLP_CKSYS_TOP_CTRL] = {VLP_CKSYS_TOP_CTRL, 0, 0,
+				&mtk_vlpsys->vlp_fqmtr_con[0],
+				&mtk_vlpsys->vlp_fqmtr_con[1]},
+};
+
+static u32 mt_get_subsys_freq(const struct fmeter_data fm_data, u32 id)
+{
+	u32 output = 0, ckdiv_en = 0;
+	u32 temp;
+
+	if (fm_data.pll_con0 != 0) {
+		/* check ckdiv_en */
+		if (read32(fm_data.pll_con0) & 0x00010000)
+			ckdiv_en = 1;
+		/* pll con0[19] = 1, pll con0[16] = 1, pll con0[12] = 1 */
+		/* select pll_ckdiv, enable pll_ckdiv, enable test clk */
+		setbits32(fm_data.pll_con0, BIT(19) | BIT(16) | BIT(12));
+	}
+
+	/* CLK26CALI_0[15]: rst 1 -> 0 */
+	write32(fm_data.con0, 0);
+	/* CLK26CALI_0[15]: rst 0 -> 1 */
+	setbits32(fm_data.con0, BIT(15));
+
+	/* vlp freq meter sel ckgen[20:16] */
+	/* other subsys freq meter sel ckgen[2:0] */
+	if (fm_data.id == VLP_CKSYS_TOP_CTRL)
+		clrsetbits32(fm_data.con0, GENMASK(20, 16), id << 16);
+	else
+		clrsetbits32(fm_data.con0, GENMASK(2, 0), id);
+
+	clrsetbits32(fm_data.con1, GENMASK(31, 16), 0x1FF << 16);
+
+	/* select divider?dvt set zero */
+	clrbits32(fm_data.con0, GENMASK(31, 24));
+
+	setbits32(fm_data.con0, BIT(12));
+	setbits32(fm_data.con0, BIT(4));
+	/* fmeter con0[1:0] = 0 */
+	/* choose test clk */
+	clrbits32(fm_data.con0, BIT(1) | BIT(0));
+
+	/* wait frequency meter finish */
+	if (fm_data.id == VLP_CKSYS_TOP_CTRL)
+		udelay(VLP_FM_WAIT_TIME);
+	else
+		wait_us(1000, !(read32(fm_data.con0) & BIT(4)));
+
+	temp = read32(fm_data.con1) & 0xFFFF;
+	output = ((temp * 26000)) / 512; /* Khz */
+
+	if (fm_data.pll_con0 != 0) {
+		/* pll con0[19] = 0, pll con0[12] = 0 */
+		if (ckdiv_en)
+			clrbits32(fm_data.pll_con0, BIT(19) | BIT(12));
+		else
+			clrbits32(fm_data.pll_con0, BIT(19) | BIT(16) | BIT(12));
+	}
+
+	write32(fm_data.con0, 0x8000);
+
+	printk(BIOS_INFO, "subsys meter[%d:%d] = %d Khz\n", fm_data.id, id, output);
+
+	return output;
+}
+
+u32 mt_get_vlpck_freq(u32 id)
+{
+	return mt_get_subsys_freq(fmd[VLP_CKSYS_TOP_CTRL], id);
+}
+
+void mt_set_topck_default(void)
+{
+	int i;
+
+	write32(&mtk_topckgen->clk_cfg[0].clr, 0xFFFFFFF0);
+	for (i = 1; i <= 16; i++)
+		write32(&mtk_topckgen->clk_cfg[i].clr, 0xFFFFFFFF);
+	write32(&mtk_topckgen->clk_cfg_17.clr, 0xFFFFFFFF);
+	write32(&mtk_topckgen->clk_cfg_18.clr, 0xFFFFFFFF);
+	write32(&mtk_topckgen->clk_cfg_19.clr, 0xFFFFFFFF);
+	write32(&mtk_topckgen->clk_cfg_update[0], 0x7FFFFFFE);
+	write32(&mtk_topckgen->clk_cfg_update[1], 0x7FFFFFFF);
+	write32(&mtk_topckgen->clk_cfg_update[2], 0x0000FFFF);
+}
+
+void pll_set_pcw_change(const struct pll *pll)
+{
+	setbits32(pll->div_reg, PLL_PCW_CHG);
+}
+
+void mt_pll_init(void)
+{
+	int i;
+
+	printk(BIOS_INFO, "Pll init start...\n");
+
+	spm_power_on();
+
+	printk(BIOS_INFO, "pll control start...\n");
+	/* [0]=1 (CLKSQ_EN) + Default Value to avoid using BootROM's setting */
+	setbits32(&mtk_apmixed->ap_clksq_con0, BIT(0));
+
+	/* Wait 100us */
+	udelay(100);
+
+	/* [2]=1 (CLKSQ_LPF_EN) */
+	setbits32(&mtk_apmixed->ap_clksq_con0, BIT(2));
+
+	for (i = 0; i < ARRAY_SIZE(pll_rates); i++)
+		pll_set_rate(&plls[pll_rates[i].id], pll_rates[i].rate);
+
+	write32(&mtk_apmixed->apll1_tuner_con0, 0x6F28BD4D);
+	write32(&mtk_apmixed->apll2_tuner_con0, 0x78FD5266);
+	setbits32(&mtk_apmixed->emipll_con[0], BIT(8));
+
+	/* PLL all enable */
+	write32(&mtk_apmixed->pllen_all_set, 0x0007FFFC);
+
+	/* Wait PLL stable (20us) */
+	udelay(20);
+
+	/* turn on pll div en */
+	setbits32(&mtk_apmixed->mainpll_con[0], GENMASK(31, 24));
+	setbits32(&mtk_apmixed->univpll_con[0], GENMASK(31, 24));
+	udelay(20);
+
+	/* pll all rstb */
+	write32(&mtk_apmixed->pll_div_rstb_all_set, 0x00000007);
+
+	printk(BIOS_INFO, "pll control done...\n");
+
+	/* [10:9] muxsel: switch to PLL speed */
+	clrsetbits32(&mtk_cpu_plldiv_cfg->cpu_plldiv_0_cfg0, GENMASK(10, 9), BIT(9));
+
+	/* [10:9] muxsel: switch to PLL speed */
+	clrsetbits32(&mtk_cpu_plldiv_cfg->cpu_plldiv_1_cfg0, GENMASK(10, 9), BIT(9));
+
+	/* [10:9] muxsel: switch to PLL speed */
+	clrsetbits32(&mtk_bus_plldiv_cfg->bus_plldiv_cfg0, GENMASK(10, 9), BIT(9));
+
+	/* Infra DCM divider */
+	setbits32(&mtk_infra_ao_bcrm->vdnr_dcm_infra_par_bus_ctrl_0, BIT(6) | BIT(3));
+
+	/* Peri DCM divider */
+	setbits32(&mtk_peri_ao_bcrm->vdnr_dcm_peri_par_bus_ctrl_0, BIT(10) | BIT(7) | BIT(4));
+
+	printk(BIOS_INFO, "mux switch control start...\n");
+
+	for (i = 0; i < ARRAY_SIZE(mux_sels); i++)
+		pll_mux_set_sel(&muxes[mux_sels[i].id], mux_sels[i].sel);
+
+	/* update mux */
+	write32(&mtk_topckgen->clk_cfg_update[0], 0x7FFFFFFF);
+	write32(&mtk_topckgen->clk_cfg_update[1], 0x7FFFFFFF);
+	write32(&mtk_topckgen->clk_cfg_update[2], 0x0000FFFF);
+
+	/* femisys_dvfs_ck_gfmux_sel = 1(emipll_ck) */
+	write32(&mtk_topckgen->clk_mem_dfs_cfg, 0x1);
+
+	for (i = 0; i < ARRAY_SIZE(vlp_mux_sels); i++)
+		pll_mux_set_sel(&vlp_muxes[vlp_mux_sels[i].id], vlp_mux_sels[i].sel);
+
+	/* update mux */
+	write32(&mtk_vlpsys->vlp_clk_cfg_update, 0x00FFFFFF);
+
+	printk(BIOS_INFO, "mux switch control done...\n");
+
+	printk(BIOS_INFO, "Pll init Done!!\n");
+}
+
+void mt_pll_post_init(void)
+{
+	/* for CG */
+	printk(BIOS_INFO, "subsysCG enable start...\n");
+
+	/* TOPCKGEN CG Clear */
+	write32(&mtk_topckgen->clk_misc_cfg_3.clr, 0x00010000);
+	write32(&mtk_topckgen->clk_misc_cfg_3.set, 0xDF3CFCFF);
+	/* INFRACFG_AO CG Clear */
+	write32(&mtk_infracfg_ao->infracfg_ao_module_cg_0_clr, 0x10000000);
+	write32(&mtk_infracfg_ao->infracfg_ao_module_cg_1_clr, 0x21000000);
+	write32(&mtk_infracfg_ao->infracfg_ao_module_cg_2_clr, 0x08000000);
+	write32(&mtk_infracfg_ao->infracfg_ao_module_cg_3_clr, 0x02000000);
+	/* PERICFG_AO CG Clear */
+	write32(&mtk_pericfg_ao->pericfg_ao_peri_cg_0_clr, 0x3FFFFFFF);
+	write32(&mtk_pericfg_ao->pericfg_ao_peri_cg_1_clr, 0x3DBDFBF6);
+	write32(&mtk_pericfg_ao->pericfg_ao_peri_cg_2_clr, 0x0FFFFFFB);
+	/* UFSCFG_AO_REG CG Clear */
+	write32(&mtk_ufscfg_ao->ufscfg_ao_reg_ufs_ao_cg_0_clr, 0x0000007F);
+	/* IMP_IIC_WRAP_WS CG Clear */
+	write32(&mtk_imp_iic_wrap_ws->imp_iic_wrap_ws_ap_clock_cg_clr, 0x00000001);
+	/* IMP_IIC_WRAP_E CG Clear */
+	write32(&mtk_imp_iic_wrap_e->imp_iic_wrap_e_ap_clock_cg_clr, 0x00000003);
+	/* IMP_IIC_WRAP_S CG Clear */
+	write32(&mtk_imp_iic_wrap_s->imp_iic_wrap_s_ap_clock_cg_clr, 0x0000000F);
+	/* IMP_IIC_WRAP_EN CG Clear */
+	write32(&mtk_imp_iic_wrap_en->imp_iic_wrap_en_ap_clock_cg_clr, 0x00000003);
+	/* VLP_CK CG Clear */
+	write32(&mtk_vlpsys->vlp_clk_cfg_30_set, 0x00000832);
+	/* SCP_IIC CG Clear */
+	write32(&mtk_scp_iic->scp_iic_ccu_clock_cg_set, 0x00000003);
+	/* SCP CG Clear */
+	setbits32(&mtk_scp->scp_ap_spi_cg, BIT(1) | BIT(0));
+	/* VLPCFG_AO_REG CG Clear */
+	clrbits32(&mtk_vlpcfg_ao->vlpcfg_ao_reg_debugtop_vlpao_ctrl, BIT(8));
+	/* VLPCFG_REG CG Clear */
+	setbits32(&mtk_vlpcfg->vlp_test_ck_ctrl,
+		  BIT(28) | BIT(24) | BIT(23) | BIT(22) | BIT(21) | BIT(20) |
+		  BIT(18) | BIT(13) | BIT(12) | BIT(11) | BIT(10) | BIT(9) |
+		  BIT(8) | BIT(7) | BIT(4) | BIT(3) | BIT(2) | BIT(1) | BIT(0));
+	/* DVFSRC_TOP CG Clear */
+	setbits32(&mtk_dvfsrc_top->dvfsrc_top_dvfsrc_basic_control, BIT(0));
+
+	/* DBGAO CG Clear */
+	setbits32(&mtk_dbgao->dbgao_atb, BIT(0));
+	/* DEM CG Clear*/
+	setbits32(&mtk_dem->dem_atb, BIT(0));
+	setbits32(&mtk_dem->dem_dbgbusclk_en, BIT(0));
+	setbits32(&mtk_dem->dem_dbgsysclk_en, BIT(0));
+	/* UFSCFG_PDN_REG CG Clear */
+	write32(&mtk_ufscfg_pdn->ufscfg_pdn_reg_ufs_pdn_cg_0_clr, 0x0000002B);
+
+	/* MMINFRA_CONFIG CG Clear */
+	write32(&mtk_mminfra_config->mminfra_config_mminfra_cg_0_clr, 0x00000007);
+	write32(&mtk_mminfra_config->mminfra_config_mminfra_cg_1_clr, 0x00020000);
+	/* GCE CG Clear */
+	clrbits32(&mtk_gce_d->gce_gce_ctl_int0, BIT(16));
+
+	printk(BIOS_INFO, "subsysCG enable done...\n");
+}
+
+void mt_pll_raise_little_cpu_freq(u32 freq)
+{
+	/* switch clock source to intermediate clock */
+	clrsetbits32(&mtk_cpu_plldiv_cfg->cpu_plldiv_0_cfg0, MCU_MUX_MASK, MCU_MUX_SRC_26M);
+
+	/* disable armpll_ll frequency output */
+	write32(&mtk_apmixed->pllen_all_clr, 0x40000);
+
+	/* raise armpll_ll frequency */
+	pll_set_rate(&plls[CLK_APMIXED_ARMPLL_LL], freq);
+
+	/* enable armpll_ll frequency output */
+	write32(&mtk_apmixed->pllen_all_set, 0x40000);
+	udelay(PLL_EN_DELAY);
+
+	/* switch clock source back to armpll_ll */
+	clrsetbits32(&mtk_cpu_plldiv_cfg->cpu_plldiv_0_cfg0, MCU_MUX_MASK, MCU_MUX_SRC_PLL);
+}
+
+void mt_pll_raise_cci_freq(u32 freq)
+{
+	/* switch clock source to intermediate clock */
+	clrsetbits32(&mtk_bus_plldiv_cfg->bus_plldiv_cfg0, MCU_MUX_MASK, MCU_MUX_SRC_26M);
+
+	/* disable ccipll frequency output */
+	write32(&mtk_apmixed->pllen_all_clr, 0x10000);
+
+	/* raise ccipll frequency */
+	pll_set_rate(&plls[CLK_APMIXED_CCIPLL], freq);
+
+	/* enable ccipll frequency output */
+	write32(&mtk_apmixed->pllen_all_set, 0x10000);
+	udelay(PLL_EN_DELAY);
+
+	/* switch clock source back to ccipll */
+	clrsetbits32(&mtk_bus_plldiv_cfg->bus_plldiv_cfg0, MCU_MUX_MASK, MCU_MUX_SRC_PLL);
+}
+
+void mt_pll_set_tvd_pll1_freq(u32 freq)
+{
+	/* disable tvdpll frequency output */
+	write32(&mtk_apmixed->pllen_all_clr, 0x200);
+
+	/* set tvdpll frequency */
+	pll_set_rate(&plls[CLK_APMIXED_TVDPLL2], freq);
+
+	/* enable tvdpll frequency output */
+	write32(&mtk_apmixed->pllen_all_set, 0x200);
+	udelay(PLL_EN_DELAY);
+}
+
+void mt_pll_edp_mux_set_sel(u32 sel)
+{
+	pll_mux_set_sel(&muxes[CLK_TOP_EDP_SEL], sel);
+}

From fe3420644216af4a6eea55ba41277348413b2186 Mon Sep 17 00:00:00 2001
From: Vince Liu <vince-wl.liu@mediatek.corp-partner.google.com>
Date: Mon, 12 May 2025 14:09:37 +0800
Subject: [PATCH 0997/3886] soc/mediatek/mt8189: Add audio/display bus
 protection release functions

Add audio and display bus protection release functions to enable audio
and display subsystems. These functions should be called after
mtcmos_audio_power_on() and mtcmos_display_power_on() respectively.

BUG=b:379008996
BRANCH=none
TEST=build pass and driver init ok.

Signed-off-by: Irving-CH.lin <irving-ch.lin@mediatek.corp-partner.google.com>
Change-Id: Idb9d6e7b3adac275ccbcb71e22126eed88149d0d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87640
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
---
 src/soc/mediatek/mt8189/mtcmos.c | 21 +++++++++++++++++++++
 1 file changed, 21 insertions(+)

diff --git a/src/soc/mediatek/mt8189/mtcmos.c b/src/soc/mediatek/mt8189/mtcmos.c
index 2f10517886..8b89e58ad2 100644
--- a/src/soc/mediatek/mt8189/mtcmos.c
+++ b/src/soc/mediatek/mt8189/mtcmos.c
@@ -80,3 +80,24 @@ void mtcmos_init(void)
 	for (i = 0; i < ARRAY_SIZE(pd_plat); i++)
 		mtcmos_power_on(&pd_plat[i]);
 }
+
+void mtcmos_protect_audio_bus(void)
+{
+	write32(&mtk_infracfg_ao->perisys_protect.clr, BIT(6));
+
+	/* AUDIO CG Clear */
+	clrbits32(&mtk_afe->audio_audio_top[0], 0x03364F80);
+	clrbits32(&mtk_afe->audio_audio_top[1], 0x00F000FF);
+	clrbits32(&mtk_afe->audio_audio_top[2], 0x01323000);
+	clrbits32(&mtk_afe->audio_audio_top[3], 0x03F00000);
+	clrbits32(&mtk_afe->audio_audio_top[4], 0x0000301F);
+}
+
+void mtcmos_protect_display_bus(void)
+{
+	write32(&mtk_infracfg_ao->mmsys_protect[0].clr, BIT(1) | BIT(0));
+
+	/* MMSYS_CONFIG CG Clear */
+	write32(&mtk_mmsys_config->mmsys_config_mmsys_cg_0_clr, 0xFF7FFFFF);
+	write32(&mtk_mmsys_config->mmsys_config_mmsys_cg_1_clr, 0x0000007B);
+}

From b4c6984a40714d0ab54d83dff24ab8cd9765fd46 Mon Sep 17 00:00:00 2001
From: Subrata Banik <subratabanik@google.com>
Date: Mon, 12 May 2025 12:43:10 +0530
Subject: [PATCH 0998/3886] soc/qualcomm/x1p42100: Initialize QSPI and QUPv3 in
 bootblock

The bootblock requires early initialization of the Quad-SPI (QSPI)
controller to enable reading firmware from flash memory.

This commit adds calls to `quadspi_init()` with a 50 MHz bus clock
and `qupv3_fw_init()` within `bootblock_soc_init()`. This ensures
that the essential hardware for flash access and related QUPv3
functions are properly configured during the boot process.

BUG=b:404985109
TEST=Able to build google/bluey.

Change-Id: Ia32114527f4b7cbabef1c1f8b7ad6d2d4b71c1f8
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87641
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: mukesh.savaliya
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
---
 src/soc/qualcomm/x1p42100/bootblock.c | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/src/soc/qualcomm/x1p42100/bootblock.c b/src/soc/qualcomm/x1p42100/bootblock.c
index a4cedfa69f..32a958b687 100644
--- a/src/soc/qualcomm/x1p42100/bootblock.c
+++ b/src/soc/qualcomm/x1p42100/bootblock.c
@@ -2,9 +2,16 @@
 
 #include <bootblock_common.h>
 #include <soc/mmu.h>
+#include <soc/qspi_common.h>
+#include <soc/qupv3_config_common.h>
+
+#define SPI_BUS_CLOCK_FREQ (50 * MHz)
 
 void bootblock_soc_init(void)
 {
 	if (!CONFIG(COMPRESS_BOOTBLOCK))
 		soc_mmu_init();
+
+	quadspi_init(SPI_BUS_CLOCK_FREQ);
+	qupv3_fw_init();
 }

From 850703b32b3e1ff0c0bcf5b2fe4381f508af0f2a Mon Sep 17 00:00:00 2001
From: Subrata Banik <subratabanik@google.com>
Date: Mon, 12 May 2025 15:46:20 +0530
Subject: [PATCH 0999/3886] mb/google/bluey: Configure FPMCU power, reset, and
 QUPv3 peripherals

Perform comprehensive peripheral initialization across romstage
and ramstage for the Bluey mainboard. This brings up essential
ChromeOS components and manages their power/reset sequences.

Key changes include:
- FPMCU Power & Reset:
  - Enable `GPIO_EN_FP_RAILS` in romstage for power rail
    stabilization (conditional on SPI fingerprint).
  - Deassert `GPIO_FP_RST_L` in ramstage once FPMCU power is stable.

- QUPv3/GPI Peripherals:
  - Load GSI (Generic Software Interface) firmware for
    QUP_0/1/2_GSI_BASE.
  - Initialize various QUPv3 Serial Engines (SE) in ramstage:
    - UART for console (if not `CONFIG_CONSOLE_SERIAL`).
    - I2C for Touch and Trackpad controllers.
    - UART for Bluetooth module.
    - SPI for the Fingerprint module (conditional on Kconfig).

- Display Initialization: Add a placeholder function `display_startup()`
  in ramstage.

BUG=b:404985109
TEST=Able to build google/bluey.

Change-Id: Iaa800e89eb521dc9d7b0a01984ca07b46a2a29d6
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87643
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/google/bluey/mainboard.c | 42 +++++++++++++++++++++++++-
 src/mainboard/google/bluey/romstage.c  | 11 +++++++
 2 files changed, 52 insertions(+), 1 deletion(-)

diff --git a/src/mainboard/google/bluey/mainboard.c b/src/mainboard/google/bluey/mainboard.c
index c633e8dfb1..db44fe7972 100644
--- a/src/mainboard/google/bluey/mainboard.c
+++ b/src/mainboard/google/bluey/mainboard.c
@@ -1,7 +1,13 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
+#include <bootmode.h>
+#include <console/console.h>
 #include <device/device.h>
+#include <gpio.h>
 #include <soc/pcie.h>
+#include <soc/qupv3_config_common.h>
+#include <soc/qup_se_handlers_common.h>
+#include "board.h"
 
 bool mainboard_needs_pcie_init(void)
 {
@@ -9,9 +15,43 @@ bool mainboard_needs_pcie_init(void)
 	return false;
 }
 
+static void display_startup(void)
+{
+	if (!display_init_required()) {
+		printk(BIOS_INFO, "Skipping display init.\n");
+		return;
+	}
+
+	/* TODO: add logic for display init */
+}
+
 static void mainboard_init(struct device *dev)
 {
-	/* Placeholder */
+	gpi_firmware_load(QUP_0_GSI_BASE);
+	gpi_firmware_load(QUP_1_GSI_BASE);
+	gpi_firmware_load(QUP_2_GSI_BASE);
+
+	/*
+	 * Load console UART QUP firmware.
+	 * This is required even if coreboot's serial output is disabled.
+	 */
+	if (!CONFIG(CONSOLE_SERIAL))
+		qupv3_se_fw_load_and_init(QUPV3_2_SE5, SE_PROTOCOL_UART, FIFO);
+
+	qupv3_se_fw_load_and_init(QUPV3_1_SE0, SE_PROTOCOL_I2C, MIXED); /* Touch I2C */
+	qupv3_se_fw_load_and_init(QUPV3_1_SE6, SE_PROTOCOL_UART, FIFO); /* BT UART */
+	qupv3_se_fw_load_and_init(QUPV3_0_SE0, SE_PROTOCOL_I2C, MIXED); /* Trackpad I2C */
+	if (CONFIG(MAINBOARD_HAS_FINGERPRINT_VIA_SPI))
+		qupv3_se_fw_load_and_init(QUPV3_2_SE2, SE_PROTOCOL_SPI, MIXED); /* Fingerprint SPI */
+
+	/*
+	 * Deassert FPMCU reset. Power applied in romstage
+	 * has now stabilized.
+	 */
+	if (CONFIG(MAINBOARD_HAS_FINGERPRINT))
+		gpio_output(GPIO_FP_RST_L, 1);
+
+	display_startup();
 }
 
 static void mainboard_enable(struct device *dev)
diff --git a/src/mainboard/google/bluey/romstage.c b/src/mainboard/google/bluey/romstage.c
index 8d15157e70..f6932fefdc 100644
--- a/src/mainboard/google/bluey/romstage.c
+++ b/src/mainboard/google/bluey/romstage.c
@@ -1,8 +1,19 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
 #include <arch/stages.h>
+#include <gpio.h>
+#include "board.h"
 
 void platform_romstage_main(void)
 {
 	/* Placeholder */
+
+	/*
+	 * Enable this power rail now for FPMCU stability prior to
+	 * its reset being deasserted in ramstage. This applies
+	 * when MAINBOARD_HAS_FINGERPRINT_VIA_SPI Kconfig is enabled.
+	 * Requires >=200ms delay after its pin was driven low in bootblock.
+	 */
+	if (CONFIG(MAINBOARD_HAS_FINGERPRINT_VIA_SPI))
+		gpio_output(GPIO_EN_FP_RAILS, 1);
 }

From b50ceba64a85eeadc56afd950e2ea8c94ebfad26 Mon Sep 17 00:00:00 2001
From: Patrick Rudolph <patrick.rudolph@9elements.com>
Date: Tue, 4 Mar 2025 09:34:00 +0100
Subject: [PATCH 1000/3886] mb/amd: Increase ROM size on boards, incorrectly
 limited to 16 MB

Since commit bb66d07d410139d6b2fe07ff5a39bd0c5a3e682a
"soc/amd/common: Always use genoa SPI MMAP driver" the ROM size can be
actually be greater than 16MiB on all AMD platforms without seeing a
boot failure. Since still only 16MiB of the SPI flash are MMAPed,
the FMAP should not be extended, and if so should only contain non x86
firmwares in the upper 16MiB of flash.

Now that common code supports ROM_SIZE greater than 16MiB select the
correct BOARD_ROMSIZE_KB for each mainboard.

Change-Id: Icdce01bddbc4873ba42ceddcda6d9075f5a42914
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86701
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
---
 src/mainboard/amd/birman/Kconfig      | 2 +-
 src/mainboard/amd/birman_plus/Kconfig | 2 +-
 src/mainboard/amd/crater/Kconfig      | 2 +-
 src/mainboard/amd/mayan/Kconfig       | 2 +-
 4 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/src/mainboard/amd/birman/Kconfig b/src/mainboard/amd/birman/Kconfig
index 9fafae15e3..3a9ffc77f1 100644
--- a/src/mainboard/amd/birman/Kconfig
+++ b/src/mainboard/amd/birman/Kconfig
@@ -2,7 +2,7 @@
 
 config BOARD_AMD_BIRMAN_COMMON
 	def_bool n
-	select BOARD_ROMSIZE_KB_16384	# Birman actually has a 32MiB ROM
+	select BOARD_ROMSIZE_KB_32768
 	select EC_ACPI
 	select SOC_AMD_COMMON_BLOCK_USE_ESPI if !SOC_AMD_COMMON_BLOCK_SIMNOW_BUILD
 	select DRIVERS_PCIE_RTD3_DEVICE
diff --git a/src/mainboard/amd/birman_plus/Kconfig b/src/mainboard/amd/birman_plus/Kconfig
index 91e39bf260..62d5c29141 100644
--- a/src/mainboard/amd/birman_plus/Kconfig
+++ b/src/mainboard/amd/birman_plus/Kconfig
@@ -2,7 +2,7 @@
 
 config BOARD_AMD_BIRMANPLUS_COMMON
 	def_bool n
-	select BOARD_ROMSIZE_KB_16384   # Birman+ actually has a 64MiB ROM
+	select BOARD_ROMSIZE_KB_65536
 	select EC_ACPI
 	select SOC_AMD_COMMON_BLOCK_USE_ESPI if !SOC_AMD_COMMON_BLOCK_SIMNOW_BUILD
 	select DRIVERS_PCIE_RTD3_DEVICE
diff --git a/src/mainboard/amd/crater/Kconfig b/src/mainboard/amd/crater/Kconfig
index 620bc3d084..11bd6b9cf7 100644
--- a/src/mainboard/amd/crater/Kconfig
+++ b/src/mainboard/amd/crater/Kconfig
@@ -2,7 +2,7 @@
 
 config BOARD_AMD_CRATER_COMMON
 	def_bool n
-	select BOARD_ROMSIZE_KB_16384	# Birman actually has a 32MiB ROM
+	select BOARD_ROMSIZE_KB_32768
 	select EC_ACPI
 	select SOC_AMD_COMMON_BLOCK_USE_ESPI if !SOC_AMD_COMMON_BLOCK_SIMNOW_BUILD
 	select DRIVERS_PCIE_RTD3_DEVICE
diff --git a/src/mainboard/amd/mayan/Kconfig b/src/mainboard/amd/mayan/Kconfig
index 327599d78c..1af2d1838b 100644
--- a/src/mainboard/amd/mayan/Kconfig
+++ b/src/mainboard/amd/mayan/Kconfig
@@ -4,7 +4,7 @@ if BOARD_AMD_MAYAN_PHOENIX
 
 config BOARD_SPECIFIC_OPTIONS
 	def_bool y
-	select BOARD_ROMSIZE_KB_16384	# Mayan actually has a 32MiB ROM
+	select BOARD_ROMSIZE_KB_32768
 	select EC_ACPI
 	select SOC_AMD_COMMON_BLOCK_USE_ESPI
 	select AMD_SOC_CONSOLE_UART

From e6dc71fe9fa815951b97d3885535dec1fc4d8b42 Mon Sep 17 00:00:00 2001
From: Keith Hui <buurin@gmail.com>
Date: Sat, 19 Apr 2025 16:20:56 -0400
Subject: [PATCH 1001/3886] util/superiotool: Dump one more NCT6779D register

Nuvoton NCT6779D has an undocumented GPIOE# functionality similar
to that found in NCT6791D. Its latched status can be read from
LDN B register 0xfb. Add it to the roster of dumped registers to
help development.

Change-Id: Id050b8efde855dec8099f1ac35307f7d372ae499
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87364
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
---
 util/superiotool/nuvoton.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/util/superiotool/nuvoton.c b/util/superiotool/nuvoton.c
index 05974f27d4..80ba12ecdd 100644
--- a/util/superiotool/nuvoton.c
+++ b/util/superiotool/nuvoton.c
@@ -596,10 +596,10 @@ static const struct superio_registers reg_table[] = {
 		{0x0b, "Hardware Monitor, Front Panel LED",
 			{0x30,0x60,0x61,0x62,0x63,0x70,0xe0,0xe1,0xe2,
 			 0xe4,0xf0,0xf1,0xf2,0xf5,0xf6,0xf7,0xf8,0xf9,
-			 0xfa,EOT},
+			 0xfa,0xfb,EOT},
 			{0x00,0x00,0x00,0x00,0x00,0x00,0x7f,0x7f,0xff,
 			 0xff,0x00,0x00,0x00,0x10,0x00,0x87,0x47,0x00,
-			 0x00,EOT}},
+			 0x00,0x00,EOT}},
 		{0x0d, "WDT1",
 			{0xf0,EOT},
 			{0x00,EOT}},

From 3008b8de53bf04a38e4f64790568c11e7a9e99bf Mon Sep 17 00:00:00 2001
From: Benjamin Doron <benjamin.doron@9elements.com>
Date: Fri, 9 May 2025 16:24:39 -0400
Subject: [PATCH 1002/3886] soc/intel/skylake: Show that SMRAM is
 unconditionally locked

Align with Cannon Lake SoCs and make it clear that SMRAM is
and should always be locked. This is cleanup, since Skylake's
Kconfig selects HAVE_SMI_HANDLER.

Change-Id: I136c69ad831d9e16d5034d6e488ee061c9b887f5
Signed-off-by: Benjamin Doron <benjamin.doron@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87618
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
---
 src/soc/intel/skylake/cpu.c | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/src/soc/intel/skylake/cpu.c b/src/soc/intel/skylake/cpu.c
index 8f294f7c8f..853ad6840e 100644
--- a/src/soc/intel/skylake/cpu.c
+++ b/src/soc/intel/skylake/cpu.c
@@ -199,8 +199,7 @@ static void post_mp_init(void)
 	global_smi_enable_no_pwrbtn();
 
 	/* Lock down the SMRAM space. */
-	if (CONFIG(HAVE_SMI_HANDLER))
-		smm_lock();
+	smm_lock();
 
 	if (mp_run_on_all_cpus(vmx_configure, NULL) != CB_SUCCESS)
 		failure = true;

From 3e1f96a0f44ab1410955f9e86d618ae0cffe5ba7 Mon Sep 17 00:00:00 2001
From: Jeremy Soller <jeremy@system76.com>
Date: Wed, 28 Aug 2024 08:24:34 -0600
Subject: [PATCH 1003/3886] mb/system76/mtl: Add Lemur Pro 13

The Lemur Pro 13 (lemp13) is an Intel Meteor Lake-U based board.

There are 2 variants to differentiate which keyboard design the unit
uses, as they require different EC firmware.

Change-Id: Icac8c7dafd6371881622d797f399f8ddbe13cbce
Signed-off-by: Jeremy Soller <jeremy@system76.com>
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82788
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
---
 src/mainboard/system76/mtl/Kconfig            |   20 +
 src/mainboard/system76/mtl/Kconfig.name       |    6 +
 src/mainboard/system76/mtl/Makefile.mk        |    2 +
 .../spd/samsung-M425R1GB4BB0-CQKOD.spd.hex    |   65 +
 .../spd/samsung-M425R1GB4PB0-CWMOD.spd.hex    |   65 +
 .../system76/mtl/variants/lemp13/board.fmd    |   12 +
 .../mtl/variants/lemp13/board_info.txt        |    2 +
 .../system76/mtl/variants/lemp13/data.vbt     |  Bin 0 -> 7680 bytes
 .../system76/mtl/variants/lemp13/gpio.c       |  216 ++++
 .../system76/mtl/variants/lemp13/gpio_early.c |   17 +
 .../system76/mtl/variants/lemp13/hda_verb.c   |   50 +
 .../mtl/variants/lemp13/overridetree.cb       |  125 ++
 .../system76/mtl/variants/lemp13/ramstage.c   |   20 +
 .../system76/mtl/variants/lemp13/romstage.c   |   35 +
 .../system76/mtl/variants/lemp13/tas5825m.c   | 1049 +++++++++++++++++
 15 files changed, 1684 insertions(+)
 create mode 100644 src/mainboard/system76/mtl/spd/samsung-M425R1GB4BB0-CQKOD.spd.hex
 create mode 100644 src/mainboard/system76/mtl/spd/samsung-M425R1GB4PB0-CWMOD.spd.hex
 create mode 100644 src/mainboard/system76/mtl/variants/lemp13/board.fmd
 create mode 100644 src/mainboard/system76/mtl/variants/lemp13/board_info.txt
 create mode 100644 src/mainboard/system76/mtl/variants/lemp13/data.vbt
 create mode 100644 src/mainboard/system76/mtl/variants/lemp13/gpio.c
 create mode 100644 src/mainboard/system76/mtl/variants/lemp13/gpio_early.c
 create mode 100644 src/mainboard/system76/mtl/variants/lemp13/hda_verb.c
 create mode 100644 src/mainboard/system76/mtl/variants/lemp13/overridetree.cb
 create mode 100644 src/mainboard/system76/mtl/variants/lemp13/ramstage.c
 create mode 100644 src/mainboard/system76/mtl/variants/lemp13/romstage.c
 create mode 100644 src/mainboard/system76/mtl/variants/lemp13/tas5825m.c

diff --git a/src/mainboard/system76/mtl/Kconfig b/src/mainboard/system76/mtl/Kconfig
index 6f1c23d2d2..60eba4aaa6 100644
--- a/src/mainboard/system76/mtl/Kconfig
+++ b/src/mainboard/system76/mtl/Kconfig
@@ -36,6 +36,20 @@ config BOARD_SYSTEM76_DARP10_B
 	select SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES
 	select SOC_INTEL_METEORLAKE_U_H
 
+config BOARD_SYSTEM76_LEMP13
+	select BOARD_SYSTEM76_MTL_COMMON
+	select DRIVERS_I2C_TAS5825M
+	select HAVE_SPD_IN_CBFS
+	select SOC_INTEL_METEORLAKE_U_H
+	select SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES
+
+config BOARD_SYSTEM76_LEMP13_B
+	select BOARD_SYSTEM76_MTL_COMMON
+	select DRIVERS_I2C_TAS5825M
+	select HAVE_SPD_IN_CBFS
+	select SOC_INTEL_METEORLAKE_U_H
+	select SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES
+
 if BOARD_SYSTEM76_MTL_COMMON
 
 config MAINBOARD_DIR
@@ -43,6 +57,7 @@ config MAINBOARD_DIR
 
 config VARIANT_DIR
 	default "darp10" if BOARD_SYSTEM76_DARP10 || BOARD_SYSTEM76_DARP10_B
+	default "lemp13" if BOARD_SYSTEM76_LEMP13 || BOARD_SYSTEM76_LEMP13_B
 
 config OVERRIDE_DEVICETREE
 	default "variants/\$(CONFIG_VARIANT_DIR)/overridetree.cb"
@@ -50,13 +65,18 @@ config OVERRIDE_DEVICETREE
 config MAINBOARD_PART_NUMBER
 	default "darp10" if BOARD_SYSTEM76_DARP10
 	default "darp10-b" if BOARD_SYSTEM76_DARP10_B
+	default "lemp13" if BOARD_SYSTEM76_LEMP13
+	default "lemp13-b" if BOARD_SYSTEM76_LEMP13_B
 
 config MAINBOARD_SMBIOS_PRODUCT_NAME
 	default "Darter Pro" if BOARD_SYSTEM76_DARP10 || BOARD_SYSTEM76_DARP10_B
+	default "Lemur Pro" if BOARD_SYSTEM76_LEMP13 || BOARD_SYSTEM76_LEMP13_B
 
 config MAINBOARD_VERSION
 	default "darp10" if BOARD_SYSTEM76_DARP10
 	default "darp10-b" if BOARD_SYSTEM76_DARP10_B
+	default "lemp13" if BOARD_SYSTEM76_LEMP13
+	default "lemp13-b" if BOARD_SYSTEM76_LEMP13_B
 
 config CMOS_DEFAULT_FILE
 	default "src/mainboard/\$(MAINBOARDDIR)/cmos.default"
diff --git a/src/mainboard/system76/mtl/Kconfig.name b/src/mainboard/system76/mtl/Kconfig.name
index 877f91c236..299c834f82 100644
--- a/src/mainboard/system76/mtl/Kconfig.name
+++ b/src/mainboard/system76/mtl/Kconfig.name
@@ -5,3 +5,9 @@ config BOARD_SYSTEM76_DARP10
 
 config BOARD_SYSTEM76_DARP10_B
 	bool "darp10-b"
+
+config BOARD_SYSTEM76_LEMP13
+	bool "lemp13"
+
+config BOARD_SYSTEM76_LEMP13_B
+	bool "lemp13-b"
diff --git a/src/mainboard/system76/mtl/Makefile.mk b/src/mainboard/system76/mtl/Makefile.mk
index d61ee9c198..b91991c7d2 100644
--- a/src/mainboard/system76/mtl/Makefile.mk
+++ b/src/mainboard/system76/mtl/Makefile.mk
@@ -12,3 +12,5 @@ ramstage-y += variants/$(VARIANT_DIR)/hda_verb.c
 ramstage-y += variants/$(VARIANT_DIR)/gpio.c
 ramstage-y += variants/$(VARIANT_DIR)/ramstage.c
 ramstage-$(CONFIG_DRIVERS_I2C_TAS5825M) += variants/$(VARIANT_DIR)/tas5825m.c
+
+SPD_SOURCES = samsung-M425R1GB4BB0-CQKOD samsung-M425R1GB4PB0-CWMOD
diff --git a/src/mainboard/system76/mtl/spd/samsung-M425R1GB4BB0-CQKOD.spd.hex b/src/mainboard/system76/mtl/spd/samsung-M425R1GB4BB0-CQKOD.spd.hex
new file mode 100644
index 0000000000..a9a61c7703
--- /dev/null
+++ b/src/mainboard/system76/mtl/spd/samsung-M425R1GB4BB0-CQKOD.spd.hex
@@ -0,0 +1,65 @@
+# Samsung M425R1GB4BB0-CQKOD
+30 10 12 03 04 00 40 42 00 00 00 00 90 02 00 00
+00 00 00 00 A0 01 F2 03 7A 0D 00 00 00 00 80 3E
+80 3E 80 3E 00 7D 80 BB 30 75 27 01 A0 00 82 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 88 13 08 88 13 08 20 4E 20 10
+27 10 1A 41 28 10 27 10 C4 09 04 4C 1D 0C 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+10 00 80 B3 80 21 80 B3 82 20 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 0F 01 02 81 00 22 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 09 D1
+80 CE 00 00 00 00 00 00 00 4D 34 32 35 52 31 47
+42 34 42 42 30 2D 43 51 4B 4F 44 20 20 20 20 20
+20 20 20 20 20 20 20 00 80 CE 95 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
diff --git a/src/mainboard/system76/mtl/spd/samsung-M425R1GB4PB0-CWMOD.spd.hex b/src/mainboard/system76/mtl/spd/samsung-M425R1GB4PB0-CWMOD.spd.hex
new file mode 100644
index 0000000000..40af92f230
--- /dev/null
+++ b/src/mainboard/system76/mtl/spd/samsung-M425R1GB4PB0-CWMOD.spd.hex
@@ -0,0 +1,65 @@
+# Samsung M425R1GB4PB0-CWMOD
+30 10 12 03 04 00 40 42 00 00 00 00 B0 02 09 00
+00 00 00 00 65 01 F2 03 7A AD 00 00 00 00 80 3E
+80 3E 80 3E 00 7D 80 BB 30 75 27 01 A0 00 82 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 88 13 08 88 13 08 20 4E 20 10
+27 10 CD 37 28 10 27 10 C4 09 04 4C 1D 0C 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+10 00 80 B3 80 21 80 B3 82 20 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 0F 01 02 81 00 22 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 5E 9B
+80 CE 00 00 00 00 00 00 00 4D 34 32 35 52 31 47
+42 34 50 42 30 2D 43 57 4D 4F 44 20 20 20 20 20
+20 20 20 20 20 20 20 00 80 CE 50 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
diff --git a/src/mainboard/system76/mtl/variants/lemp13/board.fmd b/src/mainboard/system76/mtl/variants/lemp13/board.fmd
new file mode 100644
index 0000000000..965e6bc319
--- /dev/null
+++ b/src/mainboard/system76/mtl/variants/lemp13/board.fmd
@@ -0,0 +1,12 @@
+FLASH 32M {
+	SI_DESC 16K
+	SI_ME 10128K
+	SI_BIOS@16M 16M {
+		RW_MRC_CACHE 64K
+		SMMSTORE(PRESERVE) 256K
+		WP_RO {
+			FMAP 4K
+			COREBOOT(CBFS)
+		}
+	}
+}
diff --git a/src/mainboard/system76/mtl/variants/lemp13/board_info.txt b/src/mainboard/system76/mtl/variants/lemp13/board_info.txt
new file mode 100644
index 0000000000..1e2fe1d69a
--- /dev/null
+++ b/src/mainboard/system76/mtl/variants/lemp13/board_info.txt
@@ -0,0 +1,2 @@
+Board name: lemp13
+Release year: 2024
diff --git a/src/mainboard/system76/mtl/variants/lemp13/data.vbt b/src/mainboard/system76/mtl/variants/lemp13/data.vbt
new file mode 100644
index 0000000000000000000000000000000000000000..9218279ba0e6978f4dabfd3b2fd30294774c27ca
GIT binary patch
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zO0#!G^9;^@QFd}Qq^yq+FX7Y}D(BU)(hPz;$AKWuru7jbJ4p9YmFAgiHW56{GpbAg
zfM6wyKxo5mSlbJ&mgf6N)3u58W`!5%DA1hK*0Q`1rg>kPOLyIezzp%A&lll~hUw+L
zvMN0^pS6J*A_pL+Zd=U5h9ie`ZDi4_>xnFa%}jEfL)LsE`Nqpb3w>0fbs6co5Ro)Q
zmPRlopE$f*Z^Xl86}raLbAd=&j7`#uSW!M+RJX<A6N|fnP%C;7iMcT3L)RI%&gQWm
zuGYkpeY2HX@XGcKf=VxlG9sA|f>x_9g=Zt0r%$c{X@iQzBoLl(O~MORWRe2G%JcBz
zP8r36e7ok<{Gyj>gMs}Bgji9FTn}QAuf3|3)|lt5mO4FDmz@ihkfsV7kTS2oFKToO
z$H*Oaxi*Vl={U$-(b?S<91fm3A00b>>Rj|WsF)5u-D@iKN+Yu!T_Rg(;i+5=24v)^
zIix7c7I20{+WMp%L|<_xJt>RTXMcdu^jO+ALceuEBY@QV1O+KV``E{X{03gmh#%Y$
zG_xg_a0=$1P}OUU<}$P~ie}VS-$MTNdy_oYO(XU<<0vw4GRQ;nf$2=84#}Ai$FZ<7
znSSvWhil2qONUA^v0{SPqP8}&dq=Cfni=gLJ@3WK<8XBwd7&;}F>x=9oQ+)}+W-6t
zTVdvJ&i(gG*_p{L*(9~xGP8nQ*#@s2{J>(vc~GE21PT!-MBu-PK<j5pIlVqY6jKbm
z?u2QX?ULVdg*geZevOE$#HuMqA?PymjbF-c--CihXC9iv7mzBvXxY#JEb#K@_`YGC
zXBtgFM?*jJtV^V2(^k%0kd;|nIWpsCM$^`17NU8`s&Zt>X@zu~rsx=b(c;aK-R)sC
zWL;ogWWbgR$VB2~+VWG9kztGDFDDMnij18J$c>W<#fnVXqGdOHH$PnqnI+CBZcVZv
zU7=aE5}0OACS<}t-L^y?>VqsIw83V~){094@;${OE^(xQutwdEUfH;mb_iQM@V$;&
nEOj|{UVR^5?d|xJ1V6I5VT=5JB<JCA^Y=W+5Vits#0dNa%~p2`

literal 0
HcmV?d00001

diff --git a/src/mainboard/system76/mtl/variants/lemp13/gpio.c b/src/mainboard/system76/mtl/variants/lemp13/gpio.c
new file mode 100644
index 0000000000..6a6df8c797
--- /dev/null
+++ b/src/mainboard/system76/mtl/variants/lemp13/gpio.c
@@ -0,0 +1,216 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <mainboard/gpio.h>
+#include <soc/gpio.h>
+
+static const struct pad_config gpio_table[] = {
+	PAD_CFG_NF(GPP_A00, UP_20K, DEEP, NF1), // ESPI_IO0_EC
+	PAD_CFG_NF(GPP_A01, UP_20K, DEEP, NF1), // ESPI_IO1_EC
+	PAD_CFG_NF(GPP_A02, UP_20K, DEEP, NF1), // ESPI_IO2_EC
+	PAD_CFG_NF(GPP_A03, UP_20K, DEEP, NF1), // ESPI_IO3_EC
+	PAD_CFG_NF(GPP_A04, UP_20K, DEEP, NF1), // ESPI_CS_EC#
+	PAD_CFG_NF(GPP_A05, UP_20K, DEEP, NF1), // ESPI_CLK_EC
+	PAD_CFG_NF(GPP_A06, NONE, DEEP, NF1), // ESPI_RESET#
+	PAD_NC(GPP_A07, NONE),
+	PAD_NC(GPP_A08, NONE),
+	PAD_NC(GPP_A09, NONE),
+	PAD_NC(GPP_A10, NONE),
+	PAD_NC(GPP_A11, NONE),
+	PAD_NC(GPP_A12, NONE),
+	PAD_CFG_TERM_GPO(GPP_A13, 1, UP_20K, PLTRST), // M2_SSD2_RST#
+	PAD_NC(GPP_A14, NONE),
+	PAD_NC(GPP_A15, NONE),
+	PAD_CFG_NF(GPP_A16, UP_20K, DEEP, NF1), // ESPI_ALRT0#
+	PAD_CFG_GPI_INT(GPP_A17, NONE, PLTRST, LEVEL), // TP_ATTN#
+	PAD_NC(GPP_A18, NONE),
+	PAD_NC(GPP_A19, NONE),
+	PAD_NC(GPP_A20, NONE),
+	PAD_NC(GPP_A21, NONE),
+
+	PAD_NC(GPP_B00, NONE),
+	PAD_NC(GPP_B01, NONE),
+	PAD_NC(GPP_B02, NONE),
+	PAD_NC(GPP_B03, NONE),
+	PAD_NC(GPP_B04, NONE),
+	PAD_NC(GPP_B05, NONE),
+	PAD_CFG_GPO(GPP_B06, 0, DEEP), // ROM_I2C_EN
+	PAD_NC(GPP_B07, NONE),
+	PAD_NC(GPP_B08, NONE),
+	PAD_NC(GPP_B09, NONE), // 10k pull to 1.8V
+	PAD_NC(GPP_B10, NONE), // 10k pull to 1.8V
+	PAD_CFG_NF(GPP_B11, NONE, DEEP, NF2), // CPU_HDMI_HPD
+	PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), // SLP_S0#
+	PAD_CFG_NF(GPP_B13, NONE, PLTRST, NF1), // PLT_RST#
+	PAD_NC(GPP_B14, NONE), // 10k pull to 1.8V
+	PAD_CFG_GPI(GPP_B15, NONE, DEEP), // USB_OC3#
+	PAD_NC(GPP_B16, NONE), // 10k P/U to 1.8V
+	PAD_CFG_GPO(GPP_B17, 1, PLTRST), // HDMI_EN
+	PAD_CFG_GPO(GPP_B18, 1, PLTRST), // PCH_BT_EN
+	PAD_CFG_GPO(GPP_B19, 1, PLTRST), // WIFI_RF_EN
+	PAD_CFG_GPO(GPP_B20, 1, PLTRST), // 5G_PLT_RST_N
+	PAD_CFG_GPO(GPP_B21, 0, PLTRST), // TBT_FORCE_PWR
+	PAD_CFG_GPI(GPP_B22, NONE, DEEP), // MODEL_ID4
+	PAD_CFG_GPO(GPP_B23, 1, DEEP), // NC or PCH_SPKR?
+
+	PAD_CFG_NF(GPP_C00, NONE, DEEP, NF1), // SMB_CLK_DDR
+	PAD_CFG_NF(GPP_C01, NONE, DEEP, NF1), // SMB_DATA_DDR
+	PAD_CFG_NF(GPP_C02, NONE, DEEP, NF1), // CSME TLS confidentiality strap
+	PAD_CFG_NF(GPP_C03, UP_20K, DEEP, NF1), // SML0_CLK
+	PAD_CFG_NF(GPP_C04, UP_20K, DEEP, NF1), // SML0_DATA
+	PAD_CFG_NF(GPP_C05, UP_20K, DEEP, NF1), // eSPI disable strap
+	PAD_CFG_NF(GPP_C06, UP_20K, DEEP, NF1), // TBT_I2C_SCL
+	PAD_CFG_NF(GPP_C07, UP_20K, DEEP, NF1), // TBT_I2C_SDA
+	PAD_NC(GPP_C08, NONE),
+	PAD_CFG_NF(GPP_C09, NONE, DEEP, NF1), // CARD_CLKREQ
+	PAD_CFG_GPO(GPP_C10, 0, PLTRST), // 5G_PCIE_CLKREQ
+	PAD_CFG_NF(GPP_C11, NONE, PWROK, NF1), // WLAN_CLKREQ
+	PAD_NC(GPP_C12, NONE),
+	PAD_NC(GPP_C13, NONE),
+	// GPP_C14 missing
+	PAD_CFG_GPI(GPP_C15, NONE, DEEP), // strap
+	// GPP_C16 (TBTA_LSX0_TXD) configured by FSP
+	// GPP_C17 (TBTA_LSX0_RXD) configured by FSP
+	PAD_NC(GPP_C18, NONE),
+	PAD_NC(GPP_C19, NONE),
+	PAD_CFG_NF(GPP_C20, NONE, DEEP, NF2), // HDMI_CTRLCLK
+	PAD_CFG_NF(GPP_C21, NONE, DEEP, NF2), // HDMI_CTRLDATA
+	PAD_NC(GPP_C22, NONE),
+	PAD_NC(GPP_C23, NONE),
+
+	PAD_CFG_GPO(GPP_D00, 1, PLTRST), // SB_BLON
+	PAD_CFG_GPO(GPP_D01, 1, PLTRST), // SSD2_PWR_EN
+	PAD_CFG_GPO(GPP_D02, 1, PLTRST), // M2_SSD1_RST#
+	PAD_NC(GPP_D03, NONE),
+	PAD_NC(GPP_D04, NONE),
+	PAD_CFG_GPO(GPP_D05, 1, PLTRST), // SSD1_PWR_EN
+	PAD_NC(GPP_D06, NONE),
+	PAD_NC(GPP_D07, NONE),
+	PAD_NC(GPP_D08, NONE),
+	PAD_NC(GPP_D09, NONE),
+	PAD_CFG_NF(GPP_D10, NONE, DEEP, NF1), // HDA_BITCLK
+	PAD_CFG_NF(GPP_D11, NATIVE, DEEP, NF1), // HDA_SYNC
+	PAD_CFG_NF(GPP_D12, NATIVE, DEEP, NF1), // HDA_SDOUT / CPU_ME_WE
+	PAD_CFG_NF(GPP_D13, NATIVE, DEEP, NF1), // HDA_SDIN0
+	PAD_NC(GPP_D14, NONE),
+	PAD_NC(GPP_D15, NONE),
+	PAD_CFG_GPO(GPP_D16, 0, DEEP), // PCH_MUTE#
+	PAD_CFG_NF(GPP_D17, NONE, DEEP, NF1), // HDA_RST#
+	PAD_NC(GPP_D18, NONE),
+	PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1), // SSD2_CLKREQ
+	PAD_CFG_NF(GPP_D20, NONE, DEEP, NF1), // SSD1_CLKREQ
+	PAD_NC(GPP_D21, NONE),
+	PAD_CFG_NF(GPP_D22, NATIVE, DEEP, NF1), // 1.1k pull to 1.8V
+	PAD_CFG_NF(GPP_D23, NATIVE, DEEP, NF1), // 1.1k pull to 1.8V
+
+	PAD_NC(GPP_E00, NONE),
+	_PAD_CFG_STRUCT(GPP_E01, 0x40100100, 0x1000), // TPM_PIRQ#
+	PAD_CFG_GPI(GPP_E02, NONE, DEEP), // BOARD_ID2
+	PAD_NC(GPP_E03, NONE), // CNVI_WAKE#
+	PAD_NC(GPP_E04, NONE),
+	PAD_NC(GPP_E05, NONE),
+	PAD_CFG_GPI(GPP_E06, NONE, DEEP), // JTAG ODT strap
+	PAD_NC(GPP_E07, NONE),
+	PAD_NC(GPP_E08, NONE),
+	PAD_CFG_GPI(GPP_E09, NONE, DEEP), // USB_OC0#
+	PAD_NC(GPP_E10, NONE),
+	PAD_CFG_GPI(GPP_E11, NONE, DEEP), // BOARD_ID1
+	PAD_NC(GPP_E12, NONE),
+	PAD_CFG_GPI(GPP_E13, NONE, DEEP), // BOARD_ID3
+	PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), // CPU_EDP_HPD
+	PAD_NC(GPP_E15, NONE),
+	PAD_NC(GPP_E16, NONE),
+	PAD_NC(GPP_E17, NONE),
+	// GPP_E18 missing
+	// GPP_E19 missing
+	// GPP_E20 missing
+	// GPP_E21 missing
+	PAD_NC(GPP_E22, NONE),
+
+	PAD_CFG_NF(GPP_F00, NONE, DEEP, NF1), // CNVI_BRI_DT
+	PAD_CFG_NF(GPP_F01, UP_20K, DEEP, NF1), // CNVI_BRI_RSP
+	PAD_CFG_NF(GPP_F02, NONE, DEEP, NF1), // CNVI_RGI_DT
+	PAD_CFG_NF(GPP_F03, UP_20K, DEEP, NF1), // CNVI_RGI_RSP
+	PAD_CFG_NF(GPP_F04, NONE, DEEP, NF1), // CNVI_RST#
+	PAD_CFG_NF(GPP_F05, NONE, DEEP, NF3), // CNVI_CLKREQ
+	PAD_CFG_NF(GPP_F06, NONE, DEEP, NF1), // CNVI_GNSS_PA_BLANKING
+	PAD_NC(GPP_F07, NONE),
+	PAD_NC(GPP_F08, NONE),
+	PAD_CFG_GPI(GPP_F09, NONE, DEEP), // TPM_DET
+	PAD_NC(GPP_F10, NONE), // WAKE_ON_WWAN_N
+	PAD_NC(GPP_F11, NONE),
+	_PAD_CFG_STRUCT(GPP_F12, 0x44002300, 0x0000), // AMP_SMB_CLK
+	_PAD_CFG_STRUCT(GPP_F13, 0x44002300, 0x0000), // AMP_SMB_DATA
+	PAD_NC(GPP_F14, NONE),
+	PAD_NC(GPP_F15, NONE),
+	PAD_NC(GPP_F16, NONE),
+	PAD_NC(GPP_F17, NONE),
+	PAD_CFG_GPO(GPP_F18, 0, DEEP), // CCD_WP#
+	PAD_NC(GPP_F19, NONE),
+	PAD_CFG_GPI(GPP_F20, NONE, PLTRST), // VRs supporting SVID strap
+	PAD_NC(GPP_F21, NONE),
+	PAD_NC(GPP_F22, NONE),
+	PAD_NC(GPP_F23, NONE),
+
+	PAD_CFG_GPO(GPP_H00, 0, PLTRST), // MAFS strap
+	PAD_CFG_GPO(GPP_H01, 0, PLTRST), // Flash Descriptor Recovery strap
+	PAD_CFG_GPO(GPP_H02, 1, PLTRST), // WLAN_RST#
+	// GPP_H03 missing
+	PAD_NC(GPP_H04, NONE), // CNVI_MFUART2_RXD
+	PAD_NC(GPP_H05, NONE), // CNVI_MFUART2_TXD
+	PAD_NC(GPP_H06, NONE),
+	PAD_NC(GPP_H07, NONE),
+	PAD_NC(GPP_H08, NONE),
+	PAD_NC(GPP_H09, NONE),
+	PAD_NC(GPP_H10, NONE),
+	PAD_NC(GPP_H11, NONE),
+	// GPP_H12 missing
+	PAD_CFG_NF(GPP_H13, NONE, DEEP, NF1), // CPU_C10_GATE#
+	PAD_NC(GPP_H14, NONE),
+	PAD_NC(GPP_H15, NONE),
+	PAD_NC(GPP_H16, NONE),
+	PAD_NC(GPP_H17, NONE),
+	// GPP_H18 missing
+	PAD_CFG_NF(GPP_H19, NONE, DEEP, NF1), // I2C_SDA_TP
+	PAD_CFG_NF(GPP_H20, NONE, DEEP, NF1), // I2C_SCL_TP
+	PAD_CFG_NF(GPP_H21, NONE, DEEP, NF1), // PCH_I2C_SDA
+	PAD_CFG_NF(GPP_H22, NONE, DEEP, NF1), // PCH_I2C_SCL
+
+	PAD_NC(GPP_S00, NONE),
+	PAD_NC(GPP_S01, NONE),
+	PAD_CFG_GPO(GPP_S02, 0, PLTRST), // DMIC_CLK
+	PAD_CFG_GPO(GPP_S03, 0, PLTRST), // DMIC_DATA
+	PAD_NC(GPP_S04, NONE),
+	PAD_NC(GPP_S05, NONE),
+	PAD_NC(GPP_S06, NONE),
+	PAD_NC(GPP_S07, NONE),
+
+	PAD_CFG_NF(GPP_V00, NONE, DEEP, NF1), // 100k pull to 1.8V
+	PAD_CFG_NF(GPP_V01, NONE, DEEP, NF1), // AC_PRESENT
+	PAD_CFG_NF(GPP_V02, NONE, DEEP, NF1), // 10k pull to 1.8V
+	PAD_CFG_NF(GPP_V03, NONE, DEEP, NF1), // CPU_PWR_BTN#
+	PAD_CFG_NF(GPP_V04, NONE, DEEP, NF1), // SUSB#_PCH
+	PAD_CFG_NF(GPP_V05, UP_20K, DEEP, NF1), // SUSC#_PCH
+	PAD_CFG_NF(GPP_V06, NATIVE, DEEP, NF1), // SLP_A#
+	// GPP_V07 missing
+	PAD_CFG_NF(GPP_V08, NONE, DEEP, NF1), // SUS_CLK
+	PAD_CFG_NF(GPP_V09, NONE, DEEP, NF1), // SLP_WLAN#
+	PAD_NC(GPP_V10, NONE),
+	PAD_NC(GPP_V11, NONE),
+	PAD_NC(GPP_V12, NONE),
+	// GPP_V13 missing
+	PAD_CFG_NF(GPP_V14, NONE, DEEP, NF1), // PCH_WAKE#
+	// GPP_V15 missing
+	// GPP_V16 missing
+	// GPP_V17 missing
+	// GPP_V18 missing
+	// GPP_V19 missing
+	// GPP_V20 missing
+	// GPP_V21 missing
+	PAD_NC(GPP_V22, NONE),
+	PAD_NC(GPP_V23, NONE),
+};
+
+void mainboard_configure_gpios(void)
+{
+	gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table));
+}
diff --git a/src/mainboard/system76/mtl/variants/lemp13/gpio_early.c b/src/mainboard/system76/mtl/variants/lemp13/gpio_early.c
new file mode 100644
index 0000000000..a2a5e5bb19
--- /dev/null
+++ b/src/mainboard/system76/mtl/variants/lemp13/gpio_early.c
@@ -0,0 +1,17 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <mainboard/gpio.h>
+#include <soc/gpio.h>
+
+static const struct pad_config early_gpio_table[] = {
+	PAD_CFG_NF(GPP_C00, NONE, DEEP, NF1), // SMB_CLK
+	PAD_CFG_NF(GPP_C01, NONE, DEEP, NF1), // SMB_DATA
+	PAD_CFG_GPI(GPP_E11, NONE, DEEP), // BOARD_ID1
+	PAD_CFG_NF(GPP_H08, NONE, DEEP, NF1), // UART0_RX
+	PAD_CFG_NF(GPP_H09, NONE, DEEP, NF1), // UART0_TX
+};
+
+void mainboard_configure_early_gpios(void)
+{
+	gpio_configure_pads(early_gpio_table, ARRAY_SIZE(early_gpio_table));
+}
diff --git a/src/mainboard/system76/mtl/variants/lemp13/hda_verb.c b/src/mainboard/system76/mtl/variants/lemp13/hda_verb.c
new file mode 100644
index 0000000000..fa135ad340
--- /dev/null
+++ b/src/mainboard/system76/mtl/variants/lemp13/hda_verb.c
@@ -0,0 +1,50 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <device/azalia_device.h>
+
+const u32 cim_verb_data[] = {
+	/* Realtek, ALC245 */
+	0x10ec0245, /* Vendor ID */
+	0x15582624, /* Subsystem ID */
+	34, /* Number of entries */
+
+	AZALIA_SUBVENDOR(0, 0x15582624),
+	AZALIA_RESET(1),
+	AZALIA_PIN_CFG(0, 0x12, 0x90a60130),
+	AZALIA_PIN_CFG(0, 0x13, 0x40000000),
+	AZALIA_PIN_CFG(0, 0x14, 0x411111f0),
+	AZALIA_PIN_CFG(0, 0x17, 0x90170110),
+	AZALIA_PIN_CFG(0, 0x18, 0x411111f0),
+	AZALIA_PIN_CFG(0, 0x19, 0x411111f0),
+	AZALIA_PIN_CFG(0, 0x1a, 0x411111f0),
+	AZALIA_PIN_CFG(0, 0x1b, 0x411111f0),
+	AZALIA_PIN_CFG(0, 0x1d, 0x40689b2d),
+	AZALIA_PIN_CFG(0, 0x1e, 0x411111f0),
+	AZALIA_PIN_CFG(0, 0x21, 0x04211020),
+
+	0x05b50006, 0x05b40011, 0x0205001a, 0x0204810b,
+	0x0205004a, 0x02042010, 0x02050038, 0x02046909,
+	0x05c50000, 0x05c43d82, 0x05c50000, 0x05c43d82,
+	0x05350000, 0x0534201a, 0x05350000, 0x0534201a,
+	0x0535001d, 0x05340800, 0x0535001e, 0x05340800,
+	0x05350003, 0x05341ec4, 0x05350004, 0x05340000,
+	0x05450000, 0x05442000, 0x0545001d, 0x05440800,
+	0x0545001e, 0x05440800, 0x05450003, 0x05441ec4,
+	0x05450004, 0x05440000, 0x05350000, 0x0534a01a,
+	0x0205003c, 0x0204f175, 0x0205003c, 0x0204f135,
+	0x02050040, 0x02048800, 0x05a50001, 0x05a4001f,
+	0x02050010, 0x02040020, 0x02050010, 0x02040020,
+	0x0205006b, 0x0204a390, 0x0205006b, 0x0204a390,
+	0x0205006c, 0x02040c9e, 0x0205006d, 0x02040c00,
+	0x00170500, 0x00170500, 0x05a50004, 0x05a40113,
+	0x02050008, 0x02046a8c, 0x02050076, 0x0204f000,
+	0x0205000e, 0x020465c0, 0x02050033, 0x02048580,
+	0x02050069, 0x0204fda8, 0x02050068, 0x02040000,
+	0x02050003, 0x02040002, 0x02050069, 0x02040000,
+	0x02050068, 0x02040001, 0x0205002e, 0x0204290e,
+	0x02050010, 0x02040020, 0x02050010, 0x02040020,
+};
+
+const u32 pc_beep_verbs[] = {};
+
+AZALIA_ARRAY_SIZES;
diff --git a/src/mainboard/system76/mtl/variants/lemp13/overridetree.cb b/src/mainboard/system76/mtl/variants/lemp13/overridetree.cb
new file mode 100644
index 0000000000..a1533d644c
--- /dev/null
+++ b/src/mainboard/system76/mtl/variants/lemp13/overridetree.cb
@@ -0,0 +1,125 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
+chip soc/intel/meteorlake
+	#TODO: POWER LIMITS
+	#register "power_limits_config[RPL_P_282_242_142_15W_CORE]" = "{
+	#	.tdp_pl1_override = 15,
+	#	.tdp_pl2_override = 46,
+	#}"
+
+	device domain 0 on
+		subsystemid 0x1558 0x2624 inherit
+
+		device ref tbt_pcie_rp0 on end
+		device ref tcss_xhci on
+			register "tcss_ports[0]" = "TCSS_PORT_DEFAULT(OC_SKIP)"
+			#TODO: TCP1 is used as USB Type-A
+			register "tcss_ports[1]" = "TCSS_PORT_DEFAULT(OC_SKIP)"
+			#TODO: TCP2 is used as HDMI
+			#TODO: TCP3 goes to redriver, then mux, then USB Type-C
+			register "tcss_ports[3]" = "TCSS_PORT_DEFAULT(OC_SKIP)"
+			chip drivers/usb/acpi
+				device ref tcss_root_hub on
+					chip drivers/usb/acpi
+						register "desc" = ""TBT Type-C""
+						register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
+						device ref tcss_usb3_port0 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB Type-A""
+						register "type" = "UPC_TYPE_USB3_A"
+						device ref tcss_usb3_port1 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB Type-C""
+						register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
+						device ref tcss_usb3_port3 on end
+					end
+				end
+			end
+		end
+		device ref tcss_dma0 on end
+		device ref xhci on
+			register "usb2_ports" = "{
+				[0] = USB2_PORT_MID(OC_SKIP),		/* TODO: USB TYPEA port1 GEN2 */
+				[1] = USB2_PORT_MID(OC_SKIP),		/* TODO: USB TYPEA port2 GEN1 */
+				[2] = USB2_PORT_TYPE_C(OC_SKIP),	/* TODO: TBT TYPEC USB2.0 */
+				[4] = USB2_PORT_TYPE_C(OC_SKIP),	/* TODO: TYPEC USB2.0 */
+				[6] = USB2_PORT_MID(OC_SKIP),		/* Camera */
+				[9] = USB2_PORT_MID(OC_SKIP),		/* Bluetooth */
+			}"
+			register "usb3_ports" = "{
+				[0] = USB3_PORT_DEFAULT(OC_SKIP),	/* TODO: USB port1 GEN1 */
+			}"
+		end
+
+		device ref i2c0 on
+			# Touchpad I2C bus
+			register "serial_io_i2c_mode[PchSerialIoIndexI2C0]" = "PchSerialIoPci"
+			chip drivers/i2c/hid
+				register "generic.hid" = ""ELAN0412""
+				register "generic.desc" = ""ELAN Touchpad""
+				register "generic.irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPP_A17)"
+				register "generic.detect" = "1"
+				register "hid_desc_reg_offset" = "0x01"
+				device i2c 15 on end
+			end
+			chip drivers/i2c/hid
+				register "generic.hid" = ""FTCS1000""
+				register "generic.desc" = ""FocalTech Touchpad""
+				register "generic.irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPP_A17)"
+				register "generic.detect" = "1"
+				register "hid_desc_reg_offset" = "0x01"
+				device i2c 38 on end
+			end
+		end
+		device ref i2c5 on
+			# Smart Amplifier I2C bus
+			register "serial_io_i2c_mode[PchSerialIoIndexI2C5]" = "PchSerialIoPci"
+			chip drivers/i2c/tas5825m
+				register "id" = "0"
+				device i2c 4e on end # (8bit address: 0x9c)
+			end
+		end
+
+		device ref pcie_rp1 on
+			# PCH RP#1 x1, Clock 0 (CARD)
+			register "pcie_rp[PCH_RP(1)]" = "{
+				.clk_src = 0,
+				.clk_req = 0,
+				.flags = PCIE_RP_LTR | PCIE_RP_AER,
+			}"
+		end
+		device ref pcie_rp2 on
+			# PCH RP#2 x1, Clock 2 (WLAN)
+			register "pcie_rp[PCH_RP(2)]" = "{
+				.clk_src = 2,
+				.clk_req = 2,
+				.flags = PCIE_RP_LTR | PCIE_RP_AER,
+			}"
+			smbios_slot_desc "SlotTypeM2Socket1_SD" "SlotLengthOther" "M.2/E 2230 (J_WLAN1)" "SlotDataBusWidth1X"
+		end
+		device ref pcie_rp10 on
+			# PCH RP#10 x4, Clock 7 (SSD2)
+			# This uses signals PCIE_13 through PCIE_16 in the schematics
+			# but is identified as root port 10 in firmware.
+			register "pcie_rp[PCH_RP(10)]" = "{
+				.clk_src = 7,
+				.clk_req = 7,
+				.flags = PCIE_RP_LTR | PCIE_RP_AER,
+			}"
+			smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M.2/M 2280 (J_SSD2)" "SlotDataBusWidth4X"
+		end
+		device ref pcie_rp11 on
+			# CPU RP#11 x4, Clock 8 (SSD1)
+			# This uses signals PCIE_17 through PCIE_20 in the schematics
+			# but is identified as root port 11 in firmware.
+			register "pcie_rp[PCIE_RP(11)]" = "{
+				.clk_src = 8,
+				.clk_req = 8,
+				.flags = PCIE_RP_LTR | PCIE_RP_AER,
+			}"
+			smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M.2/M 2280 (J_SSD1)" "SlotDataBusWidth4X"
+		end
+	end
+end
diff --git a/src/mainboard/system76/mtl/variants/lemp13/ramstage.c b/src/mainboard/system76/mtl/variants/lemp13/ramstage.c
new file mode 100644
index 0000000000..f99c93b0f2
--- /dev/null
+++ b/src/mainboard/system76/mtl/variants/lemp13/ramstage.c
@@ -0,0 +1,20 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <soc/ramstage.h>
+
+void mainboard_silicon_init_params(FSP_S_CONFIG *params)
+{
+	// TODO: Pin Mux settings
+
+	// Enable TCP1 and TCP3 USB-A conversion
+	// BIT 0:3 is mapping to PCH XHCI USB2 port
+	// BIT 4:5 is reserved
+	// BIT 6 is orientational
+	// BIT 7 is enable
+	// TODO: Add to coreboot FSP headers as no Client FSP release will be made.
+	//params->EnableTcssCovTypeA[1] = 0x81;
+	//params->EnableTcssCovTypeA[3] = 0x85;
+
+	// Disable reporting CPU C10 state over eSPI (causes LED flicker).
+	params->PchEspiHostC10ReportEnable = 0;
+}
diff --git a/src/mainboard/system76/mtl/variants/lemp13/romstage.c b/src/mainboard/system76/mtl/variants/lemp13/romstage.c
new file mode 100644
index 0000000000..1d3409090d
--- /dev/null
+++ b/src/mainboard/system76/mtl/variants/lemp13/romstage.c
@@ -0,0 +1,35 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <soc/gpio.h>
+#include <soc/meminit.h>
+#include <soc/romstage.h>
+
+static size_t get_spd_index(void)
+{
+	// BOARD_ID1 is high if 5600 MT/s and low if 4800 MT/s
+	if (gpio_get(GPP_E11)) {
+		return 1;
+	} else {
+		return 0;
+	}
+}
+
+void mainboard_memory_init_params(FSPM_UPD *mupd)
+{
+	const struct mb_cfg board_cfg = {
+		.type = MEM_TYPE_DDR5,
+		.ect = true,
+		.LpDdrDqDqsReTraining = 1,
+	};
+	const struct mem_spd spd_info = {
+		.topo = MEM_TOPO_MIXED,
+		.cbfs_index = get_spd_index(),
+		.smbus[1] = { .addr_dimm[0] = 0x52, },
+	};
+	const bool half_populated = false;
+
+	mupd->FspmConfig.DmiMaxLinkSpeed = 4;
+	mupd->FspmConfig.GpioOverride = 0;
+
+	memcfg_init(mupd, &board_cfg, &spd_info, half_populated);
+}
diff --git a/src/mainboard/system76/mtl/variants/lemp13/tas5825m.c b/src/mainboard/system76/mtl/variants/lemp13/tas5825m.c
new file mode 100644
index 0000000000..171d9c1ed2
--- /dev/null
+++ b/src/mainboard/system76/mtl/variants/lemp13/tas5825m.c
@@ -0,0 +1,1049 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <delay.h>
+#include <drivers/i2c/tas5825m/tas5825m.h>
+
+int tas5825m_setup(struct device *dev, int id)
+{
+	int res;
+
+	res = tas5825m_set_book(dev, 0x00);
+	if (res < 0)
+		return res;
+
+	res = tas5825m_write_at(dev, 0x03, 0x02);
+	if (res < 0)
+		return res;
+
+	res = tas5825m_write_at(dev, 0x01, 0x11);
+	if (res < 0)
+		return res;
+
+	res = tas5825m_write_at(dev, 0x03, 0x02);
+	if (res < 0)
+		return res;
+
+	mdelay(5);
+
+	res = tas5825m_write_at(dev, 0x03, 0x12);
+	if (res < 0)
+		return res;
+
+	res = tas5825m_write_at(dev, 0x48, 0x0C);
+	if (res < 0)
+		return res;
+
+	res = tas5825m_write_at(dev, 0x7F, 0x64);
+	if (res < 0)
+		return res;
+
+	res = tas5825m_set_page(dev, 0x01);
+	if (res < 0)
+		return res;
+
+	{
+		const uint8_t values[] = {
+			0x00, 0xFE, 0x00, 0x40, 0x00, 0xFC, 0x00, 0x00,
+			0x00, 0xFC, 0x00, 0x00, 0x00, 0xFC, 0x00, 0x00,
+			0x00, 0xFC, 0x00, 0x00, 0x00, 0xFC, 0x00, 0x00,
+			0x00, 0xFC, 0x00, 0x00, 0x00, 0xFC, 0x00, 0x00,
+			0x00, 0xFC, 0x50, 0x00, 0x00, 0xFC, 0x00, 0x00,
+			0x00, 0xFC, 0x00, 0x00, 0x00, 0xFC, 0x00, 0x00,
+			0x00, 0xFC, 0x00, 0x00, 0x00, 0xFC, 0x00, 0x00,
+			0x00, 0xFC, 0x00, 0x00, 0x00, 0xFC, 0x00, 0x00,
+			0x00, 0xFC, 0x00, 0x00, 0x00, 0xFC, 0x00, 0x00,
+			0x00, 0xFC, 0x00, 0x00, 0x00, 0xFC, 0x00, 0x00,
+			0x00, 0xFC, 0x00, 0x00, 0x00, 0xFC, 0x00, 0x00,
+			0x00, 0xFC, 0x00, 0x00, 0x00, 0xFC, 0x00, 0x00,
+			0x00, 0x82, 0x00, 0x93, 0x00, 0xFC, 0x00, 0x00,
+			0x8F, 0x00, 0xFF, 0xEF, 0x84, 0x49, 0x03, 0x27,
+			0x84, 0x02, 0x04, 0x06, 0x02, 0x60, 0x00, 0x01,
+			0x00
+		};
+		res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values));
+		if (res < 0)
+			return res;
+	}
+
+	res = tas5825m_set_page(dev, 0x02);
+	if (res < 0)
+		return res;
+
+	{
+		const uint8_t values[] = {
+			0x02, 0x70, 0x00, 0x06, 0x02, 0x78, 0x00, 0x05,
+			0x02, 0x68, 0x00, 0x02, 0x02, 0x28, 0x03, 0x4D,
+			0x84, 0x2A, 0x04, 0x00, 0xE2, 0x57, 0x91, 0x9F,
+			0x84, 0x82, 0x20, 0xE0, 0x84, 0x82, 0x04, 0x01,
+			0xF0, 0x1C, 0x31, 0xA0, 0xF0, 0x1C, 0x31, 0xA1,
+			0xF0, 0x1C, 0x31, 0xA2, 0xF0, 0x1F, 0x31, 0xA3,
+			0xE4, 0x00, 0x11, 0xA6, 0x80, 0x27, 0x80, 0xE1,
+			0xF4, 0x00, 0x11, 0xA4, 0xF4, 0x1D, 0x31, 0xA5,
+			0xF4, 0x1C, 0x31, 0xA7, 0xF4, 0x1F, 0x31, 0xA8,
+			0x02, 0x78, 0x00, 0x03, 0xE2, 0x68, 0xF1, 0xC3,
+			0x80, 0x67, 0x80, 0xE9, 0x84, 0x4B, 0x03, 0x27,
+			0x02, 0x70, 0x00, 0x04, 0x84, 0x41, 0x03, 0x37,
+			0x80, 0x07, 0x00, 0x80, 0xE0, 0x00, 0x11, 0xA9,
+			0x84, 0x82, 0x00, 0xE0, 0x8E, 0xFC, 0x04, 0x10,
+			0xF0, 0x1C, 0x11, 0xAA, 0xF0, 0x1C, 0x11, 0xAB,
+			0x00
+		};
+		res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values));
+		if (res < 0)
+			return res;
+	}
+
+	res = tas5825m_set_page(dev, 0x03);
+	if (res < 0)
+		return res;
+
+	{
+		const uint8_t values[] = {
+			0xF0, 0x1C, 0x11, 0xAC, 0xF0, 0x1F, 0x11, 0xAD,
+			0x86, 0xA1, 0x01, 0xC2, 0x80, 0x27, 0x80, 0xE8,
+			0x60, 0x00, 0x00, 0x00, 0x84, 0x43, 0x03, 0x37,
+			0x80, 0x00, 0x00, 0x81, 0x0D, 0x00, 0x10, 0x20,
+			0x84, 0x51, 0x03, 0x3E, 0x08, 0x44, 0x26, 0x30,
+			0x84, 0xC3, 0x03, 0x47, 0x84, 0xC2, 0x40, 0xE0,
+			0x8C, 0xFF, 0x03, 0x23, 0xE0, 0x10, 0x11, 0xB3,
+			0xF0, 0x1C, 0x51, 0xB4, 0xF0, 0x1C, 0x51, 0xB5,
+			0xF0, 0x1C, 0x51, 0xB6, 0xF0, 0x1F, 0x51, 0xB7,
+			0x86, 0xA1, 0x01, 0xC6, 0x80, 0x27, 0x80, 0xEA,
+			0x84, 0x53, 0x03, 0x3E, 0x84, 0x82, 0x04, 0x05,
+			0x84, 0x51, 0x03, 0x75, 0xE2, 0x6B, 0xC0, 0x00,
+			0x80, 0x07, 0x00, 0x80, 0xE0, 0x80, 0x31, 0xB8,
+			0x84, 0x82, 0x40, 0xE0, 0xF0, 0x1C, 0x51, 0xB9,
+			0xF0, 0x1C, 0x51, 0xBA, 0xF0, 0x1C, 0x51, 0xBB,
+			0x00
+		};
+		res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values));
+		if (res < 0)
+			return res;
+	}
+
+	res = tas5825m_set_page(dev, 0x04);
+	if (res < 0)
+		return res;
+
+	{
+		const uint8_t values[] = {
+			0xF0, 0x1F, 0x51, 0xBC, 0x86, 0xA1, 0x01, 0xC5,
+			0x80, 0x27, 0x80, 0xEA, 0x60, 0x00, 0x00, 0x00,
+			0x80, 0x00, 0x00, 0x81, 0x84, 0xA1, 0x03, 0x4F,
+			0xE0, 0x80, 0xA0, 0x00, 0x01, 0x07, 0x11, 0x20,
+			0x08, 0x44, 0x26, 0x30, 0x08, 0x00, 0x98, 0x4A,
+			0x84, 0x53, 0x03, 0x75, 0x08, 0x00, 0x30, 0x48,
+			0x02, 0xCA, 0x00, 0x01, 0x08, 0x60, 0x26, 0x32,
+			0x84, 0x51, 0x03, 0x45, 0xE4, 0x10, 0x40, 0x00,
+			0x80, 0x40, 0xC0, 0x82, 0x84, 0xC2, 0x40, 0xE0,
+			0x84, 0xC3, 0x03, 0x5E, 0x08, 0x00, 0x50, 0x48,
+			0xE0, 0x10, 0x11, 0xBD, 0x02, 0xC2, 0x00, 0x02,
+			0x08, 0x60, 0x06, 0x12, 0x84, 0xD3, 0x03, 0x4F,
+			0xF0, 0x1C, 0x51, 0xBE, 0xF0, 0x1C, 0x51, 0xBF,
+			0xF0, 0x1C, 0x51, 0xC0, 0xF0, 0x1F, 0x51, 0xC1,
+			0x84, 0xA1, 0x03, 0x65, 0x80, 0x27, 0x80, 0xEA,
+			0x00
+		};
+		res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values));
+		if (res < 0)
+			return res;
+	}
+
+	res = tas5825m_set_page(dev, 0x05);
+	if (res < 0)
+		return res;
+
+	{
+		const uint8_t values[] = {
+			0xE0, 0x00, 0x00, 0x00, 0x80, 0x07, 0x00, 0x83,
+			0x08, 0x00, 0x98, 0x6B, 0x08, 0x00, 0x30, 0x68,
+			0x84, 0x53, 0x03, 0x45, 0x08, 0x60, 0x26, 0x33,
+			0x84, 0x51, 0x03, 0x25, 0xE4, 0x10, 0x60, 0x00,
+			0x80, 0x40, 0xC0, 0x81, 0x02, 0x70, 0x00, 0x7F,
+			0x08, 0x00, 0x50, 0x28, 0x08, 0x60, 0x06, 0x11,
+			0x84, 0xCB, 0x03, 0x65, 0xE0, 0x10, 0x51, 0xC4,
+			0x84, 0x80, 0x41, 0x00, 0x02, 0xA3, 0x00, 0x10,
+			0xE4, 0x00, 0x00, 0x00, 0x84, 0xD0, 0x04, 0x01,
+			0x84, 0xA2, 0x04, 0x03, 0x84, 0xD2, 0x50, 0x01,
+			0x84, 0x53, 0x03, 0x25, 0x80, 0x00, 0xC4, 0x04,
+			0x8F, 0x30, 0x00, 0x00, 0x88, 0x67, 0x03, 0x00,
+			0xE4, 0x00, 0x11, 0x9B, 0xEE, 0x64, 0x60, 0x00,
+			0x02, 0xD3, 0x00, 0x10, 0x88, 0x47, 0x00, 0x80,
+			0x10, 0x00, 0x18, 0x02, 0x86, 0xC1, 0x01, 0x9D,
+			0x00
+		};
+		res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values));
+		if (res < 0)
+			return res;
+	}
+
+	res = tas5825m_set_page(dev, 0x06);
+	if (res < 0)
+		return res;
+
+	{
+		const uint8_t values[] = {
+			0xE0, 0x10, 0x31, 0xC7, 0x86, 0xC9, 0x01, 0x9E,
+			0x80, 0x00, 0xC4, 0x02, 0x02, 0x50, 0x01, 0x9C,
+			0x00, 0xFF, 0x21, 0x65, 0x00, 0xFC, 0x00, 0x00,
+			0x02, 0x60, 0x00, 0x01, 0x02, 0x70, 0x00, 0x04,
+			0x84, 0xC8, 0x04, 0x10, 0x84, 0x41, 0x03, 0x67,
+			0x84, 0x51, 0x03, 0x6D, 0x84, 0xC0, 0x04, 0x02,
+			0x04, 0x80, 0x91, 0x20, 0x08, 0x60, 0x26, 0x30,
+			0x02, 0x78, 0x00, 0x03, 0x02, 0x68, 0x00, 0x02,
+			0x0D, 0x00, 0x10, 0x10, 0x08, 0x60, 0x06, 0x12,
+			0x84, 0x49, 0x03, 0x2F, 0xE0, 0x80, 0x71, 0xA9,
+			0x02, 0x28, 0x03, 0x55, 0x84, 0x82, 0x00, 0xE0,
+			0x84, 0x2A, 0x04, 0x00, 0xF0, 0x1C, 0x11, 0xAA,
+			0xF0, 0x1C, 0x11, 0xAB, 0xF0, 0x1C, 0x11, 0xAC,
+			0xF0, 0x1F, 0x11, 0xAD, 0x86, 0xA1, 0x01, 0xAE,
+			0x80, 0x27, 0x80, 0xE8, 0x84, 0x82, 0x04, 0x07,
+			0x00
+		};
+		res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values));
+		if (res < 0)
+			return res;
+	}
+
+	res = tas5825m_set_page(dev, 0x07);
+	if (res < 0)
+		return res;
+
+	{
+		const uint8_t values[] = {
+			0xE0, 0x80, 0x60, 0x00, 0x84, 0x82, 0x40, 0xE0,
+			0x84, 0x43, 0x03, 0x67, 0xF0, 0x1C, 0x51, 0xAF,
+			0xF0, 0x1C, 0x51, 0xB0, 0xF0, 0x1C, 0x51, 0xB1,
+			0xF0, 0x1F, 0x51, 0xB2, 0x02, 0x78, 0x00, 0x05,
+			0x80, 0x27, 0x80, 0xEA, 0x84, 0x82, 0x04, 0x08,
+			0x02, 0x70, 0x00, 0x06, 0x84, 0x53, 0x03, 0x6D,
+			0x84, 0x80, 0x04, 0x07, 0xE0, 0x00, 0x00, 0x82,
+			0xF0, 0x81, 0x00, 0x80, 0x80, 0x07, 0x12, 0xBC,
+			0x86, 0xA1, 0x01, 0x9F, 0xE2, 0x57, 0xA0, 0x00,
+			0x84, 0x82, 0x04, 0x09, 0x84, 0x82, 0x20, 0xE0,
+			0xF0, 0x1C, 0x31, 0xA0, 0xF0, 0x1C, 0x31, 0xA1,
+			0xF0, 0x1C, 0x31, 0xA2, 0xF0, 0x1F, 0x31, 0xA3,
+			0xE4, 0x00, 0x11, 0xA6, 0x80, 0x27, 0x80, 0xE1,
+			0xF4, 0x00, 0x11, 0xA4, 0xF4, 0x1D, 0x31, 0xA5,
+			0xF4, 0x1C, 0x31, 0xA7, 0xF4, 0x1F, 0x31, 0xA8,
+			0x00
+		};
+		res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values));
+		if (res < 0)
+			return res;
+	}
+
+	res = tas5825m_set_page(dev, 0x08);
+	if (res < 0)
+		return res;
+
+	{
+		const uint8_t values[] = {
+			0x02, 0x78, 0x00, 0x03, 0xE2, 0x6A, 0xF1, 0xC3,
+			0x80, 0x67, 0x80, 0xE9, 0x84, 0x4B, 0x03, 0x2F,
+			0x02, 0x70, 0x00, 0x04, 0x84, 0x59, 0x03, 0x3D,
+			0x80, 0x07, 0x00, 0x80, 0xE0, 0x00, 0x11, 0xA9,
+			0x84, 0x82, 0x60, 0xE0, 0x8E, 0xFC, 0x04, 0x10,
+			0xF0, 0x1C, 0x71, 0xAA, 0xF0, 0x1C, 0x71, 0xAB,
+			0xF0, 0x1C, 0x71, 0xAC, 0xF0, 0x1F, 0x71, 0xAD,
+			0x86, 0xA1, 0x01, 0xC2, 0x80, 0x27, 0x80, 0xEB,
+			0x60, 0x00, 0x00, 0x00, 0x84, 0x5B, 0x03, 0x3D,
+			0x80, 0x00, 0x00, 0x81, 0x0D, 0x00, 0x10, 0x20,
+			0x84, 0x59, 0x03, 0x3F, 0x08, 0x44, 0x26, 0x30,
+			0x84, 0xC3, 0x03, 0x57, 0x84, 0xC2, 0x60, 0xE0,
+			0xE0, 0x10, 0x11, 0xB3, 0xF0, 0x1C, 0x71, 0xB4,
+			0xF0, 0x1C, 0x71, 0xB5, 0xF0, 0x1C, 0x71, 0xB6,
+			0xF0, 0x1F, 0x71, 0xB7, 0x86, 0xA1, 0x01, 0xC6,
+			0x00
+		};
+		res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values));
+		if (res < 0)
+			return res;
+	}
+
+	res = tas5825m_set_page(dev, 0x09);
+	if (res < 0)
+		return res;
+
+	{
+		const uint8_t values[] = {
+			0x80, 0x27, 0x80, 0xEB, 0x84, 0x5B, 0x03, 0x3F,
+			0x84, 0x82, 0x04, 0x0D, 0x84, 0x41, 0x03, 0x76,
+			0xE2, 0x6B, 0xE0, 0x00, 0x80, 0x07, 0x00, 0x80,
+			0xE0, 0x81, 0x31, 0xB8, 0x84, 0x82, 0x00, 0xE0,
+			0xF0, 0x1C, 0x11, 0xB9, 0xF0, 0x1C, 0x11, 0xBA,
+			0xF0, 0x1C, 0x11, 0xBB, 0xF0, 0x1F, 0x11, 0xBC,
+			0x86, 0xA1, 0x01, 0xC5, 0x80, 0x27, 0x80, 0xE8,
+			0x60, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x81,
+			0x84, 0xA1, 0x03, 0x5D, 0xE0, 0x81, 0xA0, 0x00,
+			0x01, 0x07, 0x11, 0x20, 0x08, 0x44, 0x26, 0x30,
+			0x08, 0x00, 0x98, 0x4A, 0x84, 0x43, 0x03, 0x76,
+			0x08, 0x00, 0x30, 0x48, 0x02, 0xCA, 0x00, 0x01,
+			0x08, 0x60, 0x26, 0x32, 0x84, 0x41, 0x03, 0x46,
+			0xE4, 0x10, 0x40, 0x00, 0x80, 0x40, 0xC0, 0x82,
+			0x84, 0xC2, 0x00, 0xE0, 0x84, 0xC3, 0x03, 0x5F,
+			0x00
+		};
+		res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values));
+		if (res < 0)
+			return res;
+	}
+
+	res = tas5825m_set_page(dev, 0x0A);
+	if (res < 0)
+		return res;
+
+	{
+		const uint8_t values[] = {
+			0x08, 0x00, 0x50, 0x48, 0xE0, 0x10, 0x11, 0xBD,
+			0x02, 0xC2, 0x00, 0x02, 0x08, 0x60, 0x06, 0x12,
+			0x84, 0xD3, 0x03, 0x5D, 0xF0, 0x1C, 0x11, 0xBE,
+			0xF0, 0x1C, 0x11, 0xBF, 0xF0, 0x1C, 0x11, 0xC0,
+			0xF0, 0x1F, 0x11, 0xC1, 0x84, 0xA1, 0x03, 0x66,
+			0x80, 0x27, 0x80, 0xE8, 0xE0, 0x00, 0x00, 0x00,
+			0x80, 0x07, 0x00, 0x83, 0x08, 0x00, 0x98, 0x6B,
+			0x08, 0x00, 0x30, 0x68, 0x84, 0x43, 0x03, 0x46,
+			0x08, 0x60, 0x26, 0x33, 0x84, 0x51, 0x03, 0x26,
+			0xE4, 0x10, 0x60, 0x00, 0x80, 0x40, 0xC0, 0x81,
+			0x02, 0x70, 0x00, 0x7F, 0x08, 0x00, 0x50, 0x28,
+			0x08, 0x60, 0x06, 0x11, 0x8C, 0xFF, 0x03, 0x24,
+			0x84, 0xCB, 0x03, 0x66, 0xE0, 0x10, 0x51, 0xC4,
+			0x84, 0x80, 0x41, 0x00, 0x02, 0xA3, 0x00, 0x10,
+			0xE4, 0x00, 0x00, 0x00, 0x84, 0xD0, 0x04, 0x09,
+			0x00
+		};
+		res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values));
+		if (res < 0)
+			return res;
+	}
+
+	res = tas5825m_set_page(dev, 0x0B);
+	if (res < 0)
+		return res;
+
+	{
+		const uint8_t values[] = {
+			0x84, 0xA2, 0x04, 0x0B, 0x84, 0xD2, 0x50, 0x01,
+			0x84, 0x53, 0x03, 0x26, 0x80, 0x00, 0xC4, 0x0C,
+			0x8F, 0x30, 0x00, 0x00, 0x88, 0x67, 0x03, 0x00,
+			0xE4, 0x00, 0x11, 0x9B, 0xEE, 0x64, 0x80, 0x00,
+			0x02, 0xD3, 0x00, 0x10, 0x88, 0x47, 0x00, 0x80,
+			0x10, 0x00, 0x18, 0x02, 0x86, 0xC1, 0x01, 0x9D,
+			0xE0, 0x10, 0x31, 0xC7, 0x86, 0xC9, 0x01, 0x9E,
+			0x80, 0x00, 0xC4, 0x0A, 0x02, 0x50, 0x01, 0x9C,
+			0x00, 0xFF, 0x21, 0x65, 0x00, 0xFC, 0x00, 0x00,
+			0x02, 0x70, 0x00, 0x04, 0x02, 0x68, 0x00, 0x01,
+			0x02, 0x60, 0x00, 0x03, 0x02, 0x78, 0x00, 0x02,
+			0x84, 0x49, 0x03, 0x6E, 0x84, 0x41, 0x03, 0x6F,
+			0x84, 0xC8, 0x04, 0x10, 0x84, 0xC0, 0x04, 0x0A,
+			0x04, 0x81, 0x91, 0x20, 0x08, 0x60, 0x26, 0x30,
+			0x0D, 0x00, 0x10, 0x10, 0x08, 0x60, 0x06, 0x12,
+			0x00
+		};
+		res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values));
+		if (res < 0)
+			return res;
+	}
+
+	res = tas5825m_set_page(dev, 0x0C);
+	if (res < 0)
+		return res;
+
+	{
+		const uint8_t values[] = {
+			0x84, 0x00, 0x04, 0x06, 0xE0, 0x81, 0x71, 0xA9,
+			0x84, 0x82, 0x20, 0xE8, 0xF0, 0x1D, 0x31, 0xAA,
+			0xF0, 0x1D, 0x31, 0xAB, 0xF0, 0x1D, 0x31, 0xAC,
+			0xF0, 0x1C, 0x31, 0xAD, 0x86, 0xA1, 0x01, 0xAE,
+			0x80, 0x27, 0x80, 0xF9, 0x84, 0x82, 0x04, 0x0E,
+			0xE0, 0x81, 0x60, 0x00, 0x84, 0x82, 0x00, 0xE8,
+			0x84, 0x4B, 0x03, 0x6E, 0xF0, 0x1D, 0x11, 0xAF,
+			0xF0, 0x1D, 0x11, 0xB0, 0xF0, 0x1D, 0x11, 0xB1,
+			0xF0, 0x1C, 0x11, 0xB2, 0x02, 0xA3, 0x00, 0x1A,
+			0x80, 0x27, 0x80, 0xF8, 0x84, 0x82, 0x04, 0x0F,
+			0xE0, 0x81, 0xC0, 0x00, 0xF0, 0x81, 0xE0, 0x80,
+			0x84, 0x43, 0x03, 0x6F, 0x80, 0x07, 0x12, 0xBD,
+			0x02, 0xC0, 0x00, 0x00, 0x00, 0xFC, 0x50, 0x00,
+			0x8F, 0x00, 0x00, 0x11, 0x8F, 0x00, 0xFF, 0xFF,
+			0x84, 0x58, 0x04, 0x01, 0x84, 0xC2, 0x04, 0x00,
+			0x00
+		};
+		res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values));
+		if (res < 0)
+			return res;
+	}
+
+	res = tas5825m_set_page(dev, 0x0D);
+	if (res < 0)
+		return res;
+
+	{
+		const uint8_t values[] = {
+			0x02, 0xC2, 0x60, 0x00, 0x84, 0xA0, 0x61, 0x00,
+			0xE0, 0x20, 0x00, 0x00, 0x00, 0xFC, 0x00, 0x00,
+			0x40, 0x40, 0xA0, 0x00, 0x80, 0x00, 0xC0, 0x82,
+			0x08, 0xFC, 0x48, 0x3A, 0x08, 0xFC, 0x18, 0x50,
+			0x00, 0xFC, 0x00, 0x00, 0xE0, 0x10, 0x00, 0x00,
+			0x86, 0xA0, 0x41, 0x00, 0x40, 0x47, 0x20, 0x00,
+			0x80, 0x00, 0xC0, 0x83, 0x04, 0xE0, 0x3D, 0x1E,
+			0x04, 0x80, 0x11, 0xE0, 0x08, 0x44, 0x26, 0x33,
+			0x02, 0xCB, 0x00, 0x10, 0xE0, 0x10, 0x40, 0x83,
+			0x08, 0x00, 0x28, 0x21, 0x84, 0xCA, 0x61, 0x00,
+			0x80, 0x07, 0x00, 0x81, 0x0C, 0xE0, 0x2C, 0x09,
+			0x84, 0xCA, 0x21, 0x00, 0x00, 0xFC, 0x50, 0x00,
+			0x8F, 0x00, 0x00, 0x01, 0x00
+		};
+		res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values));
+		if (res < 0)
+			return res;
+	}
+
+	res = tas5825m_set_book(dev, 0x78);
+	if (res < 0)
+		return res;
+
+	res = tas5825m_set_page(dev, 0x18);
+	if (res < 0)
+		return res;
+
+	{
+		const uint8_t values[] = {
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00
+		};
+		res = tas5825m_write_block_at(dev, 0x30, values, ARRAY_SIZE(values));
+		if (res < 0)
+			return res;
+	}
+
+	res = tas5825m_set_page(dev, 0x1B);
+	if (res < 0)
+		return res;
+
+	{
+		const uint8_t values[] = {
+			0x00, 0x00, 0x03, 0x80, 0x00, 0x00, 0x04, 0x00,
+			0x00, 0x00, 0x03, 0x28, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00
+		};
+		res = tas5825m_write_block_at(dev, 0x6C, values, ARRAY_SIZE(values));
+		if (res < 0)
+			return res;
+	}
+
+	res = tas5825m_set_page(dev, 0x1C);
+	if (res < 0)
+		return res;
+
+	{
+		const uint8_t values[] = {
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00
+		};
+		res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values));
+		if (res < 0)
+			return res;
+	}
+
+	{
+		const uint8_t values[] = {
+			0x00, 0x00, 0x03, 0x30, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00
+		};
+		res = tas5825m_write_block_at(dev, 0x1C, values, ARRAY_SIZE(values));
+		if (res < 0)
+			return res;
+	}
+
+	{
+		const uint8_t values[] = {
+			0x00, 0x00, 0x03, 0x38, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00
+		};
+		res = tas5825m_write_block_at(dev, 0x3C, values, ARRAY_SIZE(values));
+		if (res < 0)
+			return res;
+	}
+
+	{
+		const uint8_t values[] = {
+			0x00, 0x00, 0x03, 0x40, 0x00, 0x00, 0x03, 0x48,
+			0x00, 0x00, 0x03, 0x50, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00
+		};
+		res = tas5825m_write_block_at(dev, 0x54, values, ARRAY_SIZE(values));
+		if (res < 0)
+			return res;
+	}
+
+	{
+		const uint8_t values[] = {
+			0x00, 0x00, 0x03, 0x58, 0x00, 0x00, 0x03, 0x60,
+			0x00, 0x00, 0x00, 0x00, 0x00
+		};
+		res = tas5825m_write_block_at(dev, 0x74, values, ARRAY_SIZE(values));
+		if (res < 0)
+			return res;
+	}
+
+	res = tas5825m_set_page(dev, 0x1D);
+	if (res < 0)
+		return res;
+
+	{
+		const uint8_t values[] = {
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00
+		};
+		res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values));
+		if (res < 0)
+			return res;
+	}
+
+	{
+		const uint8_t values[] = {
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00
+		};
+		res = tas5825m_write_block_at(dev, 0x1C, values, ARRAY_SIZE(values));
+		if (res < 0)
+			return res;
+	}
+
+	{
+		const uint8_t values[] = {
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00
+		};
+		res = tas5825m_write_block_at(dev, 0x3C, values, ARRAY_SIZE(values));
+		if (res < 0)
+			return res;
+	}
+
+	res = tas5825m_set_page(dev, 0x1E);
+	if (res < 0)
+		return res;
+
+	{
+		const uint8_t values[] = {
+			0x00, 0x00, 0x00, 0x00, 0x00
+		};
+		res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values));
+		if (res < 0)
+			return res;
+	}
+
+	{
+		const uint8_t values[] = {
+			0x00, 0x00, 0x03, 0x68, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00
+		};
+		res = tas5825m_write_block_at(dev, 0x0C, values, ARRAY_SIZE(values));
+		if (res < 0)
+			return res;
+	}
+
+	{
+		const uint8_t values[] = {
+			0x00, 0x00, 0x03, 0x70, 0x00, 0x00, 0x03, 0x78,
+			0x00, 0x00, 0x04, 0x80, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00
+		};
+		res = tas5825m_write_block_at(dev, 0x24, values, ARRAY_SIZE(values));
+		if (res < 0)
+			return res;
+	}
+
+	{
+		const uint8_t values[] = {
+			0x00, 0x00, 0x04, 0x88, 0x00, 0x00, 0x04, 0x90,
+			0x00
+		};
+		res = tas5825m_write_block_at(dev, 0x44, values, ARRAY_SIZE(values));
+		if (res < 0)
+			return res;
+	}
+
+	res = tas5825m_set_book(dev, 0x8C);
+	if (res < 0)
+		return res;
+
+	res = tas5825m_set_page(dev, 0x0E);
+	if (res < 0)
+		return res;
+
+	{
+		const uint8_t values[] = {
+			0x00, 0xA7, 0x26, 0x4A, 0x7F, 0xFF, 0xFF, 0xFF,
+			0x00, 0x20, 0xC4, 0x9C, 0x00, 0x20, 0xC4, 0x9C,
+			0x00, 0x00, 0x68, 0xDB, 0x00, 0x00, 0xD1, 0xB7,
+			0x00, 0x00, 0x68, 0xDB, 0x0F, 0xA4, 0xA8, 0xC1,
+			0xF8, 0x59, 0x7F, 0x63, 0x00
+		};
+		res = tas5825m_write_block_at(dev, 0x5C, values, ARRAY_SIZE(values));
+		if (res < 0)
+			return res;
+	}
+
+	res = tas5825m_set_page(dev, 0x0F);
+	if (res < 0)
+		return res;
+
+	{
+		const uint8_t values[] = {
+			0x07, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x2F, 0xB7, 0xE9,
+			0x00, 0x5F, 0x6F, 0xD2, 0x00, 0x2F, 0xB7, 0xE9,
+			0x0B, 0x1E, 0x4F, 0x76, 0xFC, 0x23, 0x05, 0x54,
+			0xFA, 0x41, 0x20, 0x5C, 0x0B, 0x7D, 0xBF, 0x48,
+			0xFA, 0x41, 0x20, 0x5C, 0x0B, 0x1E, 0x4F, 0x76,
+			0xFC, 0x23, 0x05, 0x54, 0x00, 0x04, 0x81, 0x6F,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x0F, 0x3F, 0xE5, 0xC9, 0xF8, 0xBB, 0x98, 0xC8,
+			0x07, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x04, 0x81, 0x6F,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x0F, 0x3F, 0xE5, 0xC9, 0xF8, 0xBB, 0x98, 0xC8,
+			0x00
+		};
+		res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values));
+		if (res < 0)
+			return res;
+	}
+
+	res = tas5825m_set_page(dev, 0x10);
+	if (res < 0)
+		return res;
+
+	{
+		const uint8_t values[] = {
+			0x00, 0x89, 0xA0, 0x27, 0x7F, 0xEC, 0x56, 0xD5,
+			0x7F, 0xFC, 0xB9, 0x23, 0x00, 0x89, 0xA0, 0x27,
+			0x7F, 0xEC, 0x56, 0xD5, 0x7F, 0xFC, 0xB9, 0x23,
+			0x00
+		};
+		res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values));
+		if (res < 0)
+			return res;
+	}
+
+	res = tas5825m_set_book(dev, 0x00);
+	if (res < 0)
+		return res;
+
+	res = tas5825m_write_at(dev, 0x40, 0x00);
+	if (res < 0)
+		return res;
+
+	{
+		const uint8_t values[] = {
+			0x11, 0xFF, 0x00
+		};
+		res = tas5825m_write_block_at(dev, 0x7D, values, ARRAY_SIZE(values));
+		if (res < 0)
+			return res;
+	}
+
+	res = tas5825m_set_page(dev, 0x01);
+	if (res < 0)
+		return res;
+
+	res = tas5825m_write_at(dev, 0x51, 0x05);
+	if (res < 0)
+		return res;
+
+	res = tas5825m_set_page(dev, 0x02);
+	if (res < 0)
+		return res;
+
+	res = tas5825m_write_at(dev, 0x19, 0xDF);
+	if (res < 0)
+		return res;
+
+	res = tas5825m_set_page(dev, 0x00);
+	if (res < 0)
+		return res;
+
+	res = tas5825m_write_at(dev, 0x46, 0x11);
+	if (res < 0)
+		return res;
+
+	res = tas5825m_write_at(dev, 0x02, 0x00);
+	if (res < 0)
+		return res;
+
+	res = tas5825m_write_at(dev, 0x53, 0x01);
+	if (res < 0)
+		return res;
+
+	res = tas5825m_write_at(dev, 0x54, 0x17);
+	if (res < 0)
+		return res;
+
+	res = tas5825m_write_at(dev, 0x03, 0x02);
+	if (res < 0)
+		return res;
+
+	res = tas5825m_write_at(dev, 0x7F, 0x8C);
+	if (res < 0)
+		return res;
+
+	res = tas5825m_set_page(dev, 0x01);
+	if (res < 0)
+		return res;
+
+	{
+		const uint8_t values[] = {
+			0x00, 0x71, 0x94, 0x9A, 0x00
+		};
+		res = tas5825m_write_block_at(dev, 0x2C, values, ARRAY_SIZE(values));
+		if (res < 0)
+			return res;
+	}
+
+	res = tas5825m_set_page(dev, 0x0A);
+	if (res < 0)
+		return res;
+
+	{
+		const uint8_t values[] = {
+			0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00,
+			0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00
+		};
+		res = tas5825m_write_block_at(dev, 0x64, values, ARRAY_SIZE(values));
+		if (res < 0)
+			return res;
+	}
+
+	res = tas5825m_set_page(dev, 0x0B);
+	if (res < 0)
+		return res;
+
+	{
+		const uint8_t values[] = {
+			0x00, 0x80, 0x00, 0x00, 0x00, 0x28, 0x7A, 0x27,
+			0x00, 0x28, 0x7A, 0x27, 0x00, 0x80, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x80, 0x00, 0x00, 0x00
+		};
+		res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values));
+		if (res < 0)
+			return res;
+	}
+
+	{
+		const uint8_t values[] = {
+			0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x57, 0x62, 0x00, 0x00, 0x00, 0x00,
+			0x00
+		};
+		res = tas5825m_write_block_at(dev, 0x28, values, ARRAY_SIZE(values));
+		if (res < 0)
+			return res;
+	}
+
+	res = tas5825m_set_page(dev, 0x0E);
+	if (res < 0)
+		return res;
+
+	{
+		const uint8_t values[] = {
+			0x00, 0x03, 0x69, 0xC5, 0x00, 0xEE, 0xC9, 0x55,
+			0x00, 0x22, 0x1D, 0x95, 0x00, 0x03, 0x69, 0xC5,
+			0x00
+		};
+		res = tas5825m_write_block_at(dev, 0x5C, values, ARRAY_SIZE(values));
+		if (res < 0)
+			return res;
+	}
+
+	res = tas5825m_set_page(dev, 0x0F);
+	if (res < 0)
+		return res;
+
+	{
+		const uint8_t values[] = {
+			0x7F, 0xF9, 0x2C, 0x60, 0x07, 0x77, 0x1A, 0x4F,
+			0x00
+		};
+		res = tas5825m_write_block_at(dev, 0x5C, values, ARRAY_SIZE(values));
+		if (res < 0)
+			return res;
+	}
+
+	res = tas5825m_set_page(dev, 0x07);
+	if (res < 0)
+		return res;
+
+	{
+		const uint8_t values[] = {
+			0x00, 0x80, 0x00, 0x00, 0x00
+		};
+		res = tas5825m_write_block_at(dev, 0x64, values, ARRAY_SIZE(values));
+		if (res < 0)
+			return res;
+	}
+
+	{
+		const uint8_t values[] = {
+			0x40, 0x00, 0x00, 0x00, 0x40, 0x00, 0x00, 0x00,
+			0x00
+		};
+		res = tas5825m_write_block_at(dev, 0x6C, values, ARRAY_SIZE(values));
+		if (res < 0)
+			return res;
+	}
+
+	res = tas5825m_set_book(dev, 0xAA);
+	if (res < 0)
+		return res;
+
+	res = tas5825m_set_page(dev, 0x01);
+	if (res < 0)
+		return res;
+
+	{
+		const uint8_t values[] = {
+			0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00
+		};
+		res = tas5825m_write_block_at(dev, 0x30, values, ARRAY_SIZE(values));
+		if (res < 0)
+			return res;
+	}
+
+	res = tas5825m_set_page(dev, 0x02);
+	if (res < 0)
+		return res;
+
+	{
+		const uint8_t values[] = {
+			0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00
+		};
+		res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values));
+		if (res < 0)
+			return res;
+	}
+
+	res = tas5825m_set_page(dev, 0x03);
+	if (res < 0)
+		return res;
+
+	{
+		const uint8_t values[] = {
+			0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x07, 0xC5, 0xCA, 0x98,
+			0xF0, 0x74, 0x6A, 0xD0, 0x07, 0xC5, 0xCA, 0x98,
+			0x0F, 0x8A, 0x9A, 0x1D, 0xF8, 0x73, 0x6F, 0xBD,
+			0x07, 0xCC, 0x4D, 0x23, 0xF0, 0x8F, 0xEC, 0x92,
+			0x07, 0xA8, 0xA9, 0xB4, 0x0F, 0x70, 0x13, 0x6E,
+			0xF8, 0x8B, 0x09, 0x29, 0x08, 0x2F, 0x93, 0x82,
+			0xF0, 0x34, 0x1D, 0x7A, 0x07, 0xA1, 0x4F, 0x7F,
+			0x0F, 0xCD, 0x63, 0x79, 0xF8, 0x30, 0x9D, 0xF2,
+			0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00
+		};
+		res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values));
+		if (res < 0)
+			return res;
+	}
+
+	res = tas5825m_set_page(dev, 0x04);
+	if (res < 0)
+		return res;
+
+	{
+		const uint8_t values[] = {
+			0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00
+		};
+		res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values));
+		if (res < 0)
+			return res;
+	}
+
+	res = tas5825m_set_page(dev, 0x05);
+	if (res < 0)
+		return res;
+
+	{
+		const uint8_t values[] = {
+			0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x07, 0xC5, 0xCA, 0x98, 0xF0, 0x74, 0x6A, 0xD0,
+			0x07, 0xC5, 0xCA, 0x98, 0x0F, 0x8A, 0x9A, 0x1D,
+			0xF8, 0x73, 0x6F, 0xBD, 0x07, 0xCC, 0x4D, 0x23,
+			0xF0, 0x8F, 0xEC, 0x92, 0x07, 0xA8, 0xA9, 0xB4,
+			0x0F, 0x70, 0x13, 0x6E, 0xF8, 0x8B, 0x09, 0x29,
+			0x00
+		};
+		res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values));
+		if (res < 0)
+			return res;
+	}
+
+	res = tas5825m_set_page(dev, 0x06);
+	if (res < 0)
+		return res;
+
+	{
+		const uint8_t values[] = {
+			0x08, 0x2F, 0x93, 0x82, 0xF0, 0x34, 0x1D, 0x7A,
+			0x07, 0xA1, 0x4F, 0x7F, 0x0F, 0xCD, 0x63, 0x79,
+			0xF8, 0x30, 0x9D, 0xF2, 0x08, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00
+		};
+		res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values));
+		if (res < 0)
+			return res;
+	}
+
+	res = tas5825m_set_page(dev, 0x0E);
+	if (res < 0)
+		return res;
+
+	{
+		const uint8_t values[] = {
+			0x00, 0x91, 0xDC, 0xC5, 0xFF, 0x04, 0xF3, 0x02,
+			0x00, 0x6E, 0x34, 0x0A, 0x0F, 0xD6, 0x6C, 0x7A,
+			0xF8, 0x24, 0x8F, 0xB5, 0x00
+		};
+		res = tas5825m_write_block_at(dev, 0x6C, values, ARRAY_SIZE(values));
+		if (res < 0)
+			return res;
+	}
+
+	res = tas5825m_set_page(dev, 0x0F);
+	if (res < 0)
+		return res;
+
+	{
+		const uint8_t values[] = {
+			0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0xFF, 0xF4, 0x49, 0x81,
+			0xFF, 0xE8, 0x93, 0x02, 0xFF, 0xF4, 0x49, 0x81,
+			0x0D, 0x94, 0x7A, 0x64, 0xFA, 0x3C, 0xAB, 0xA1,
+			0x06, 0xD5, 0xF3, 0xB1, 0xF2, 0x54, 0x18, 0x9F,
+			0x06, 0xD5, 0xF3, 0xB1, 0x0D, 0x94, 0x7A, 0x64,
+			0xFA, 0x3C, 0xAB, 0xA1, 0x00, 0x00, 0x38, 0xE4,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x0F, 0xD5, 0x55, 0x55, 0xF8, 0x2A, 0x71, 0xC7,
+			0x00
+		};
+		res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values));
+		if (res < 0)
+			return res;
+	}
+
+	res = tas5825m_set_book(dev, 0x00);
+	if (res < 0)
+		return res;
+
+	res = tas5825m_write_at(dev, 0x30, 0x00);
+	if (res < 0)
+		return res;
+
+	res = tas5825m_write_at(dev, 0x60, 0x02);
+	if (res < 0)
+		return res;
+
+	res = tas5825m_write_at(dev, 0x62, 0x09);
+	if (res < 0)
+		return res;
+
+	res = tas5825m_write_at(dev, 0x4C, 0x30);
+	if (res < 0)
+		return res;
+
+	res = tas5825m_write_at(dev, 0x03, 0x03);
+	if (res < 0)
+		return res;
+
+	res = tas5825m_write_at(dev, 0x78, 0x80);
+	if (res < 0)
+		return res;
+
+	return 0;
+}

From ba8407f0c18607ab4095bd75b94ee5289f51d7c8 Mon Sep 17 00:00:00 2001
From: Jeremy Soller <jackpot51@gmail.com>
Date: Mon, 17 Mar 2025 14:00:03 -0600
Subject: [PATCH 1004/3886] soc/intel: Add Arrow Lake-H/U IDs
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Add IDs from the EDS, with a couple extras:

- eSPI: EDS says 0x7202, but our boards show 0x7702
- GT: Value changes between 0x7d51 and 0x7dd1 based on DIMMs installed

Change-Id: I8430914edd02954cbb38592bff896733b01c735d
Ref: Intel Arrow Lake-H/U EDS, Volume 1 (#777369, rev 2.0)
Signed-off-by: Jeremy Soller <jeremy@system76.com>
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87131
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
---
 src/drivers/intel/ish/ish.c                   |  1 +
 src/include/cpu/intel/cpu_ids.h               |  1 +
 src/include/device/pci_ids.h                  | 50 +++++++++++++++++++
 src/soc/intel/common/block/cnvi/cnvi.c        |  1 +
 src/soc/intel/common/block/cpu/mp_init.c      |  1 +
 src/soc/intel/common/block/cse/cse.c          |  1 +
 src/soc/intel/common/block/dsp/dsp.c          |  1 +
 .../intel/common/block/fast_spi/fast_spi.c    |  1 +
 .../intel/common/block/graphics/graphics.c    |  2 +
 src/soc/intel/common/block/hda/hda.c          |  1 +
 src/soc/intel/common/block/i2c/i2c.c          |  6 +++
 src/soc/intel/common/block/lpc/lpc.c          |  3 ++
 src/soc/intel/common/block/p2sb/p2sb.c        |  1 +
 src/soc/intel/common/block/pcie/pcie.c        |  9 ++++
 src/soc/intel/common/block/pmc/pmc.c          |  1 +
 src/soc/intel/common/block/sata/sata.c        |  1 +
 src/soc/intel/common/block/smbus/smbus.c      |  1 +
 src/soc/intel/common/block/spi/spi.c          |  3 ++
 src/soc/intel/common/block/sram/sram.c        |  1 +
 .../common/block/systemagent/systemagent.c    |  2 +
 .../intel/common/block/tracehub/tracehub.c    |  1 +
 src/soc/intel/common/block/uart/uart.c        |  3 ++
 src/soc/intel/common/block/xdci/xdci.c        |  1 +
 src/soc/intel/common/block/xhci/xhci.c        |  1 +
 .../meteorlake/bootblock/report_platform.c    |  8 +++
 src/soc/intel/meteorlake/chip.h               |  2 +
 26 files changed, 104 insertions(+)

diff --git a/src/drivers/intel/ish/ish.c b/src/drivers/intel/ish/ish.c
index 43342f0283..8f2a187c4f 100644
--- a/src/drivers/intel/ish/ish.c
+++ b/src/drivers/intel/ish/ish.c
@@ -90,6 +90,7 @@ static const unsigned short pci_device_ids[] = {
 	PCI_DID_INTEL_PTL_U_H_ISHB,
 	PCI_DID_INTEL_LNL_ISHB,
 	PCI_DID_INTEL_MTL_ISHB,
+	PCI_DID_INTEL_ARL_ISHB,
 	PCI_DID_INTEL_CNL_ISHB,
 	PCI_DID_INTEL_CML_ISHB,
 	PCI_DID_INTEL_TGL_ISHB,
diff --git a/src/include/cpu/intel/cpu_ids.h b/src/include/cpu/intel/cpu_ids.h
index 22d2e58693..e14cb797ab 100644
--- a/src/include/cpu/intel/cpu_ids.h
+++ b/src/include/cpu/intel/cpu_ids.h
@@ -84,6 +84,7 @@
 #define CPUID_RAPTORLAKE_Q0		0xb06a3
 #define CPUID_LUNARLAKE_A0_1		0xb06d0
 #define CPUID_LUNARLAKE_A0_2		0xb06d1
+#define CPUID_ARROWLAKE_H_A0		0xc0652
 #define CPUID_PANTHERLAKE_A0		0xc06c0
 #define CPUID_SNOWRIDGE_A0		0x80660
 #define CPUID_SNOWRIDGE_A1		0x80661
diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h
index 40844f5972..01854a51a2 100644
--- a/src/include/device/pci_ids.h
+++ b/src/include/device/pci_ids.h
@@ -2182,6 +2182,7 @@
 #define PCI_DID_INTEL_TGL_ISHB		0xa0fc
 #define PCI_DID_INTEL_TGL_H_ISHB	0x43fc
 #define PCI_DID_INTEL_MTL_ISHB		0x7e45
+#define PCI_DID_INTEL_ARL_ISHB		0x7745
 #define PCI_DID_INTEL_ADL_N_ISHB	0x54fc
 #define PCI_DID_INTEL_ADL_P_ISHB	0x51fc
 #define PCI_DID_INTEL_LNL_ISHB		0xa845
@@ -3142,6 +3143,9 @@
 #define PCI_DID_INTEL_MTL_ESPI_5			0x7e05
 #define PCI_DID_INTEL_MTL_ESPI_6			0x7e06
 #define PCI_DID_INTEL_MTL_ESPI_7			0x7e07
+#define PCI_DID_INTEL_ARL_H_ESPI_0			0x7202
+#define PCI_DID_INTEL_ARL_H_ESPI_1			0x7702
+#define PCI_DID_INTEL_ARL_U_ESPI_0			0x7203
 #define PCI_DID_INTEL_RPP_P_ESPI_0			0x5180
 #define PCI_DID_INTEL_RPP_P_ADP_P_ESPI_1		0x5181
 #define PCI_DID_INTEL_RPP_P_ADP_P_ESPI_2		0x5182
@@ -3637,6 +3641,16 @@
 #define PCI_DID_INTEL_MTL_IOE_P_PCIE_RP11		0x7ecb
 #define PCI_DID_INTEL_MTL_IOE_P_PCIE_RP12		0x7ecc
 
+#define PCI_DID_INTEL_ARL_SOC_PCIE_RP1			0x7738
+#define PCI_DID_INTEL_ARL_SOC_PCIE_RP2			0x7739
+#define PCI_DID_INTEL_ARL_SOC_PCIE_RP3			0x773a
+#define PCI_DID_INTEL_ARL_SOC_PCIE_RP4			0x773b
+#define PCI_DID_INTEL_ARL_SOC_PCIE_RP5			0x773c
+#define PCI_DID_INTEL_ARL_SOC_PCIE_RP6			0x773d
+#define PCI_DID_INTEL_ARL_SOC_PCIE_RP7			0x773e
+#define PCI_DID_INTEL_ARL_SOC_PCIE_RP8			0x773f
+#define PCI_DID_INTEL_ARL_SOC_PCIE_RP9			0x774d
+
 #define PCI_DID_INTEL_RPL_P_PCIE_RP1			0xa74d
 #define PCI_DID_INTEL_RPL_P_PCIE_RP2			0xa70d
 #define PCI_DID_INTEL_RPL_P_PCIE_RP3			0xa72d
@@ -3805,6 +3819,7 @@
 #define PCI_DID_INTEL_ADP_M_SATA_2		0x54d7
 #define PCI_DID_INTEL_ADP_M_SATA_3		0x282a
 #define PCI_DID_INTEL_MTL_SATA			0x7e63
+#define PCI_DID_INTEL_ARL_SATA			0x7763
 #define PCI_DID_INTEL_RPP_P_SATA_1		0x51d3
 #define PCI_DID_INTEL_RPP_P_SATA_2		0x51d7
 #define PCI_DID_INTEL_RPP_S_SATA		0x7a62
@@ -3834,6 +3849,7 @@
 #define PCI_DID_INTEL_MTL_SOC_PMC		0x7e21
 #define PCI_DID_INTEL_MTL_IOE_M_PMC		0x7ebe
 #define PCI_DID_INTEL_MTL_IOE_P_PMC		0x7ece
+#define PCI_DID_INTEL_ARL_SOC_PMC		0x7721
 #define PCI_DID_INTEL_RPP_P_PMC			0x51a1
 #define PCI_DID_INTEL_RPP_S_PMC			0x7a21
 #define PCI_DID_INTEL_LNL_PMC			0xa821
@@ -3964,6 +3980,13 @@
 #define PCI_DID_INTEL_MTL_I2C4			0x7e50
 #define PCI_DID_INTEL_MTL_I2C5			0x7e51
 
+#define PCI_DID_INTEL_ARL_I2C0			0x7778
+#define PCI_DID_INTEL_ARL_I2C1			0x7779
+#define PCI_DID_INTEL_ARL_I2C2			0x777A
+#define PCI_DID_INTEL_ARL_I2C3			0x777B
+#define PCI_DID_INTEL_ARL_I2C4			0x7750
+#define PCI_DID_INTEL_ARL_I2C5			0x7751
+
 #define PCI_DID_INTEL_LNL_I2C0			0xa878
 #define PCI_DID_INTEL_LNL_I2C1			0xa879
 #define PCI_DID_INTEL_LNL_I2C2			0xa87a
@@ -4070,6 +4093,10 @@
 #define PCI_DID_INTEL_MTL_UART1			0x7e26
 #define PCI_DID_INTEL_MTL_UART2			0x7e52
 
+#define PCI_DID_INTEL_ARL_UART0			0x7725
+#define PCI_DID_INTEL_ARL_UART1			0x7726
+#define PCI_DID_INTEL_ARL_UART2			0x7752
+
 #define PCI_DID_INTEL_LNL_UART0			0xa825
 #define PCI_DID_INTEL_LNL_UART1			0xa826
 #define PCI_DID_INTEL_LNL_UART2			0xa852
@@ -4179,6 +4206,11 @@
 #define PCI_DID_INTEL_MTL_GSPI1			0x7e30
 #define PCI_DID_INTEL_MTL_GSPI2			0x7e46
 
+#define PCI_DID_INTEL_ARL_HWSEQ_SPI		0x7723
+#define PCI_DID_INTEL_ARL_GSPI0			0x7727
+#define PCI_DID_INTEL_ARL_GSPI1			0x7730
+#define PCI_DID_INTEL_ARL_GSPI2			0x7746
+
 #define PCI_DID_INTEL_LNL_HWSEQ_SPI		0xa823
 #define PCI_DID_INTEL_LNL_GSPI0			0xa827
 #define PCI_DID_INTEL_LNL_GSPI1			0xa830
@@ -4342,6 +4374,8 @@
 #define PCI_DID_INTEL_MTL_P_GT2_3			0x7d55
 #define PCI_DID_INTEL_MTL_P_GT2_4			0x7d60
 #define PCI_DID_INTEL_MTL_P_GT2_5			0x7dd5
+#define PCI_DID_INTEL_ARL_H_GT2_1			0x7d51
+#define PCI_DID_INTEL_ARL_H_GT2_2			0x7dd1
 #define PCI_DID_INTEL_RPL_HX_GT1			0xa788
 #define PCI_DID_INTEL_RPL_HX_GT2			0xa78b
 #define PCI_DID_INTEL_RPL_HX_GT3			0x4688
@@ -4496,6 +4530,8 @@
 #define PCI_DID_INTEL_MTL_P_ID_3		0x7d14
 #define PCI_DID_INTEL_MTL_P_ID_4		0x7d15
 #define PCI_DID_INTEL_MTL_P_ID_5		0x7d16
+#define PCI_DID_INTEL_ARL_H_ID_1		0x7d06
+#define PCI_DID_INTEL_ARL_H_ID_2		0x7d20
 #define PCI_DID_INTEL_RPL_HX_ID_1		0xa702
 #define PCI_DID_INTEL_RPL_HX_ID_2		0xa729
 #define PCI_DID_INTEL_RPL_HX_ID_3		0xa728
@@ -4553,6 +4589,7 @@
 #define PCI_DID_INTEL_ADP_S_SMBUS			0x7aa3
 #define PCI_DID_INTEL_ADP_M_N_SMBUS			0x54a3
 #define PCI_DID_INTEL_MTL_SMBUS				0x7e22
+#define PCI_DID_INTEL_ARL_SMBUS				0x7722
 #define PCI_DID_INTEL_RPP_P_SMBUS			0x51a3
 #define PCI_DID_INTEL_RPP_S_SMBUS			0x7a23
 #define PCI_DID_INTEL_LNL_SMBUS				0xa822
@@ -4597,6 +4634,7 @@
 #define PCI_DID_INTEL_MTL_XHCI			0x7e7d
 #define PCI_DID_INTEL_MTL_M_TCSS_XHCI		0x7eb0
 #define PCI_DID_INTEL_MTL_P_TCSS_XHCI		0x7ec0
+#define PCI_DID_INTEL_ARL_XHCI			0x777d
 #define PCI_DID_INTEL_RPP_P_TCSS_XHCI		0xa71e
 #define PCI_DID_INTEL_RPP_S_XHCI		0x7a60
 #define PCI_DID_INTEL_LNL_XHCI			0xa87d
@@ -4632,6 +4670,7 @@
 #define PCI_DID_INTEL_MTL_SOC_P2SB		0x7e20
 #define PCI_DID_INTEL_MTL_IOE_M_P2SB		0x7eb8
 #define PCI_DID_INTEL_MTL_IOE_P_P2SB		0x7ec8
+#define PCI_DID_INTEL_ARL_SOC_P2SB		0x7720
 #define PCI_DID_INTEL_RPP_P_P2SB		0x51a0
 #define PCI_DID_INTEL_RPP_S_P2SB		0x7a20
 #define PCI_DID_INTEL_LNL_P2SB			0xa820
@@ -4657,6 +4696,7 @@
 #define PCI_DID_INTEL_MTL_SOC_SRAM		0x7e7f
 #define PCI_DID_INTEL_MTL_IOE_M_SRAM		0x7ebf
 #define PCI_DID_INTEL_MTL_IOE_P_SRAM		0x7ecf
+#define PCI_DID_INTEL_ARL_SOC_SRAM		0x777f
 #define PCI_DID_INTEL_LNL_SRAM			0xa87f
 #define PCI_DID_INTEL_PTL_H_SRAM		0xe47f
 #define PCI_DID_INTEL_PTL_U_H_SRAM		0xe37f
@@ -4718,6 +4758,8 @@
 #define PCI_DID_INTEL_MTL_AUDIO_7		0x7e2e
 #define PCI_DID_INTEL_MTL_AUDIO_8		0x7e2f
 
+#define PCI_DID_INTEL_ARL_AUDIO		0x7728
+
 #define PCI_DID_INTEL_LNL_AUDIO_1		0xa828
 #define PCI_DID_INTEL_LNL_AUDIO_2		0xa829
 #define PCI_DID_INTEL_LNL_AUDIO_3		0xa82a
@@ -4797,6 +4839,7 @@
 #define PCI_DID_INTEL_RPP_S_CSE2		0x7a6c
 #define PCI_DID_INTEL_RPP_S_CSE3		0x7a6d
 #define PCI_DID_INTEL_MTL_CSE0			0x7e70
+#define PCI_DID_INTEL_ARL_CSE0			0x7770
 #define PCI_DID_INTEL_LNL_CSE0			0xa870
 #define PCI_DID_INTEL_PTL_H_CSE0		0xe470
 #define PCI_DID_INTEL_PTL_U_H_CSE0		0xe370
@@ -4825,6 +4868,7 @@
 #define PCI_DID_INTEL_MTL_XDCI			0x7e7e
 #define PCI_DID_INTEL_MTL_M_TCSS_XDCI		0x7eb1
 #define PCI_DID_INTEL_MTL_P_TCSS_XDCI		0x7ec1
+#define PCI_DID_INTEL_ARL_XDCI			0x777e
 #define PCI_DID_INTEL_PTL_H_XDCI		0xe47e
 #define PCI_DID_INTEL_PTL_U_H_XDCI		0xe37e
 #define PCI_DID_INTEL_WCL_XDCI		0x4d7e
@@ -4983,6 +5027,7 @@
 #define PCI_DID_INTEL_MTL_CNVI_WIFI_1		0x7e41
 #define PCI_DID_INTEL_MTL_CNVI_WIFI_2		0x7e42
 #define PCI_DID_INTEL_MTL_CNVI_WIFI_3		0x7e43
+#define PCI_DID_INTEL_ARL_CNVI_WIFI		0x7740
 #define PCI_DID_INTEL_RPL_S_CNVI_WIFI_0		0x7a70
 #define PCI_DID_INTEL_RPL_S_CNVI_WIFI_1		0x7a71
 #define PCI_DID_INTEL_RPL_S_CNVI_WIFI_2		0x7a72
@@ -5034,6 +5079,7 @@
 
 /* Intel Trace Hub */
 #define PCI_DID_INTEL_MTL_TRACEHUB			0x7e24
+#define PCI_DID_INTEL_ARL_TRACEHUB			0x7724
 #define PCI_DID_INTEL_RPL_TRACEHUB			0xa76f
 #define PCI_DID_INTEL_PTL_H_TRACEHUB			0xe424
 #define PCI_DID_INTEL_PTL_U_H_TRACEHUB			0xe324
@@ -5061,6 +5107,10 @@
 #define PCI_DID_INTEL_WCL_THC0_SPI	0x4d49
 #define PCI_DID_INTEL_WCL_THC1_I2C	0x4d4a
 #define PCI_DID_INTEL_WCL_THC1_SPI	0x4d4b
+#define PCI_DID_INTEL_ARL_THC0_1	0x7748
+#define PCI_DID_INTEL_ARL_THC0_2	0x7749
+#define PCI_DID_INTEL_ARL_THC1_1	0x774a
+#define PCI_DID_INTEL_ARL_THC1_2	0x774b
 
 #define PCI_VID_COMPUTONE		0x8e0e
 #define PCI_DID_COMPUTONE_IP2EX		0x0291
diff --git a/src/soc/intel/common/block/cnvi/cnvi.c b/src/soc/intel/common/block/cnvi/cnvi.c
index 3abd907440..7aada20079 100644
--- a/src/soc/intel/common/block/cnvi/cnvi.c
+++ b/src/soc/intel/common/block/cnvi/cnvi.c
@@ -442,6 +442,7 @@ static const unsigned short wifi_pci_device_ids[] = {
 	PCI_DID_INTEL_MTL_CNVI_WIFI_1,
 	PCI_DID_INTEL_MTL_CNVI_WIFI_2,
 	PCI_DID_INTEL_MTL_CNVI_WIFI_3,
+	PCI_DID_INTEL_ARL_CNVI_WIFI,
 	PCI_DID_INTEL_CML_LP_CNVI_WIFI,
 	PCI_DID_INTEL_CML_H_CNVI_WIFI,
 	PCI_DID_INTEL_CNL_LP_CNVI_WIFI,
diff --git a/src/soc/intel/common/block/cpu/mp_init.c b/src/soc/intel/common/block/cpu/mp_init.c
index 1602126890..a8ee838710 100644
--- a/src/soc/intel/common/block/cpu/mp_init.c
+++ b/src/soc/intel/common/block/cpu/mp_init.c
@@ -40,6 +40,7 @@ static const struct cpu_device_id cpu_table[] = {
 	{ X86_VENDOR_INTEL, CPUID_METEORLAKE_A0_2, CPUID_EXACT_MATCH_MASK },
 	{ X86_VENDOR_INTEL, CPUID_METEORLAKE_B0, CPUID_EXACT_MATCH_MASK },
 	{ X86_VENDOR_INTEL, CPUID_METEORLAKE_C0, CPUID_EXACT_MATCH_MASK },
+	{ X86_VENDOR_INTEL, CPUID_ARROWLAKE_H_A0, CPUID_EXACT_MATCH_MASK },
 	{ X86_VENDOR_INTEL, CPUID_SKYLAKE_C0, CPUID_EXACT_MATCH_MASK },
 	{ X86_VENDOR_INTEL, CPUID_SKYLAKE_D0, CPUID_EXACT_MATCH_MASK },
 	{ X86_VENDOR_INTEL, CPUID_SKYLAKE_HQ0, CPUID_EXACT_MATCH_MASK },
diff --git a/src/soc/intel/common/block/cse/cse.c b/src/soc/intel/common/block/cse/cse.c
index ef1105cfdf..58999c0b9f 100644
--- a/src/soc/intel/common/block/cse/cse.c
+++ b/src/soc/intel/common/block/cse/cse.c
@@ -1532,6 +1532,7 @@ static const unsigned short pci_device_ids[] = {
 	PCI_DID_INTEL_PTL_U_H_CSE0,
 	PCI_DID_INTEL_LNL_CSE0,
 	PCI_DID_INTEL_MTL_CSE0,
+	PCI_DID_INTEL_ARL_CSE0,
 	PCI_DID_INTEL_APL_CSE0,
 	PCI_DID_INTEL_GLK_CSE0,
 	PCI_DID_INTEL_CNL_CSE0,
diff --git a/src/soc/intel/common/block/dsp/dsp.c b/src/soc/intel/common/block/dsp/dsp.c
index bd8c9acabb..f36ab088aa 100644
--- a/src/soc/intel/common/block/dsp/dsp.c
+++ b/src/soc/intel/common/block/dsp/dsp.c
@@ -53,6 +53,7 @@ static const unsigned short pci_device_ids[] = {
 	PCI_DID_INTEL_MTL_AUDIO_6,
 	PCI_DID_INTEL_MTL_AUDIO_7,
 	PCI_DID_INTEL_MTL_AUDIO_8,
+	PCI_DID_INTEL_ARL_AUDIO,
 	PCI_DID_INTEL_RPP_P_AUDIO,
 	PCI_DID_INTEL_RPP_S_AUDIO_1,
 	PCI_DID_INTEL_RPP_S_AUDIO_2,
diff --git a/src/soc/intel/common/block/fast_spi/fast_spi.c b/src/soc/intel/common/block/fast_spi/fast_spi.c
index 8cff0707b6..b5ee53a715 100644
--- a/src/soc/intel/common/block/fast_spi/fast_spi.c
+++ b/src/soc/intel/common/block/fast_spi/fast_spi.c
@@ -577,6 +577,7 @@ static const unsigned short pci_device_ids[] = {
 	PCI_DID_INTEL_LWB_SPI_SUPER,
 	PCI_DID_INTEL_MCC_SPI0,
 	PCI_DID_INTEL_MTL_HWSEQ_SPI,
+	PCI_DID_INTEL_ARL_HWSEQ_SPI,
 	PCI_DID_INTEL_RPP_S_HWSEQ_SPI,
 	PCI_DID_INTEL_SPR_HWSEQ_SPI,
 	PCI_DID_INTEL_TGP_SPI0,
diff --git a/src/soc/intel/common/block/graphics/graphics.c b/src/soc/intel/common/block/graphics/graphics.c
index b2229152c4..165727ef0e 100644
--- a/src/soc/intel/common/block/graphics/graphics.c
+++ b/src/soc/intel/common/block/graphics/graphics.c
@@ -365,6 +365,8 @@ static const unsigned short pci_device_ids[] = {
 	PCI_DID_INTEL_MTL_P_GT2_3,
 	PCI_DID_INTEL_MTL_P_GT2_4,
 	PCI_DID_INTEL_MTL_P_GT2_5,
+	PCI_DID_INTEL_ARL_H_GT2_1,
+	PCI_DID_INTEL_ARL_H_GT2_2,
 	PCI_DID_INTEL_APL_IGD_HD_505,
 	PCI_DID_INTEL_APL_IGD_HD_500,
 	PCI_DID_INTEL_CNL_GT2_ULX_1,
diff --git a/src/soc/intel/common/block/hda/hda.c b/src/soc/intel/common/block/hda/hda.c
index 028b9eaacf..f375e0c58d 100644
--- a/src/soc/intel/common/block/hda/hda.c
+++ b/src/soc/intel/common/block/hda/hda.c
@@ -69,6 +69,7 @@ static const unsigned short pci_device_ids[] = {
 	PCI_DID_INTEL_MTL_AUDIO_6,
 	PCI_DID_INTEL_MTL_AUDIO_7,
 	PCI_DID_INTEL_MTL_AUDIO_8,
+	PCI_DID_INTEL_ARL_AUDIO,
 	PCI_DID_INTEL_RPP_P_AUDIO,
 	PCI_DID_INTEL_RPP_S_AUDIO_1,
 	PCI_DID_INTEL_RPP_S_AUDIO_2,
diff --git a/src/soc/intel/common/block/i2c/i2c.c b/src/soc/intel/common/block/i2c/i2c.c
index 8097b74022..dfb14a0ea5 100644
--- a/src/soc/intel/common/block/i2c/i2c.c
+++ b/src/soc/intel/common/block/i2c/i2c.c
@@ -204,6 +204,12 @@ static const unsigned short pci_device_ids[] = {
 	PCI_DID_INTEL_MTL_I2C3,
 	PCI_DID_INTEL_MTL_I2C4,
 	PCI_DID_INTEL_MTL_I2C5,
+	PCI_DID_INTEL_ARL_I2C0,
+	PCI_DID_INTEL_ARL_I2C1,
+	PCI_DID_INTEL_ARL_I2C2,
+	PCI_DID_INTEL_ARL_I2C3,
+	PCI_DID_INTEL_ARL_I2C4,
+	PCI_DID_INTEL_ARL_I2C5,
 	PCI_DID_INTEL_APL_I2C0,
 	PCI_DID_INTEL_APL_I2C1,
 	PCI_DID_INTEL_APL_I2C2,
diff --git a/src/soc/intel/common/block/lpc/lpc.c b/src/soc/intel/common/block/lpc/lpc.c
index 7ed01c6f85..960a26f7d3 100644
--- a/src/soc/intel/common/block/lpc/lpc.c
+++ b/src/soc/intel/common/block/lpc/lpc.c
@@ -263,6 +263,9 @@ static const unsigned short pci_device_ids[] = {
 	PCI_DID_INTEL_MTL_ESPI_5,
 	PCI_DID_INTEL_MTL_ESPI_6,
 	PCI_DID_INTEL_MTL_ESPI_7,
+	PCI_DID_INTEL_ARL_H_ESPI_0,
+	PCI_DID_INTEL_ARL_H_ESPI_1,
+	PCI_DID_INTEL_ARL_U_ESPI_0,
 	PCI_DID_INTEL_RPP_P_ESPI_0,
 	PCI_DID_INTEL_RPP_P_ADP_P_ESPI_1,
 	PCI_DID_INTEL_RPP_P_ADP_P_ESPI_2,
diff --git a/src/soc/intel/common/block/p2sb/p2sb.c b/src/soc/intel/common/block/p2sb/p2sb.c
index c32982f30e..1986e4ce4f 100644
--- a/src/soc/intel/common/block/p2sb/p2sb.c
+++ b/src/soc/intel/common/block/p2sb/p2sb.c
@@ -142,6 +142,7 @@ static const unsigned short pci_device_ids[] = {
 	PCI_DID_INTEL_PTL_U_H_P2SB,
 	PCI_DID_INTEL_LNL_P2SB,
 	PCI_DID_INTEL_MTL_SOC_P2SB,
+	PCI_DID_INTEL_ARL_SOC_P2SB,
 	PCI_DID_INTEL_RPP_P_P2SB,
 	PCI_DID_INTEL_APL_P2SB,
 	PCI_DID_INTEL_GLK_P2SB,
diff --git a/src/soc/intel/common/block/pcie/pcie.c b/src/soc/intel/common/block/pcie/pcie.c
index a2db276195..1b3e148f15 100644
--- a/src/soc/intel/common/block/pcie/pcie.c
+++ b/src/soc/intel/common/block/pcie/pcie.c
@@ -119,6 +119,15 @@ static const unsigned short pcie_device_ids[] = {
 	PCI_DID_INTEL_MTL_IOE_P_PCIE_RP10,
 	PCI_DID_INTEL_MTL_IOE_P_PCIE_RP11,
 	PCI_DID_INTEL_MTL_IOE_P_PCIE_RP12,
+	PCI_DID_INTEL_ARL_SOC_PCIE_RP1,
+	PCI_DID_INTEL_ARL_SOC_PCIE_RP2,
+	PCI_DID_INTEL_ARL_SOC_PCIE_RP3,
+	PCI_DID_INTEL_ARL_SOC_PCIE_RP4,
+	PCI_DID_INTEL_ARL_SOC_PCIE_RP5,
+	PCI_DID_INTEL_ARL_SOC_PCIE_RP6,
+	PCI_DID_INTEL_ARL_SOC_PCIE_RP7,
+	PCI_DID_INTEL_ARL_SOC_PCIE_RP8,
+	PCI_DID_INTEL_ARL_SOC_PCIE_RP9,
 	PCI_DID_INTEL_LWB_PCIE_RP1,
 	PCI_DID_INTEL_LWB_PCIE_RP2,
 	PCI_DID_INTEL_LWB_PCIE_RP3,
diff --git a/src/soc/intel/common/block/pmc/pmc.c b/src/soc/intel/common/block/pmc/pmc.c
index 50c3945044..dbdf2fe5fd 100644
--- a/src/soc/intel/common/block/pmc/pmc.c
+++ b/src/soc/intel/common/block/pmc/pmc.c
@@ -118,6 +118,7 @@ static const unsigned short pci_device_ids[] = {
 	PCI_DID_INTEL_MTL_SOC_PMC,
 	PCI_DID_INTEL_MTL_IOE_M_PMC,
 	PCI_DID_INTEL_MTL_IOE_P_PMC,
+	PCI_DID_INTEL_ARL_SOC_PMC,
 	PCI_DID_INTEL_RPP_P_PMC,
 	PCI_DID_INTEL_DNV_PMC,
 	PCI_DID_INTEL_LWB_PMC,
diff --git a/src/soc/intel/common/block/sata/sata.c b/src/soc/intel/common/block/sata/sata.c
index ca61c682df..ae51efa95c 100644
--- a/src/soc/intel/common/block/sata/sata.c
+++ b/src/soc/intel/common/block/sata/sata.c
@@ -36,6 +36,7 @@ struct device_operations sata_ops = {
 
 static const unsigned short pci_device_ids[] = {
 	PCI_DID_INTEL_MTL_SATA,
+	PCI_DID_INTEL_ARL_SATA,
 	PCI_DID_INTEL_RPP_P_SATA_1,
 	PCI_DID_INTEL_RPP_P_SATA_2,
 	PCI_DID_INTEL_RPP_S_SATA,
diff --git a/src/soc/intel/common/block/smbus/smbus.c b/src/soc/intel/common/block/smbus/smbus.c
index 87b44f547b..fc8c0aff09 100644
--- a/src/soc/intel/common/block/smbus/smbus.c
+++ b/src/soc/intel/common/block/smbus/smbus.c
@@ -54,6 +54,7 @@ static const unsigned short pci_device_ids[] = {
 	PCI_DID_INTEL_PTL_U_H_SMBUS,
 	PCI_DID_INTEL_LNL_SMBUS,
 	PCI_DID_INTEL_MTL_SMBUS,
+	PCI_DID_INTEL_ARL_SMBUS,
 	PCI_DID_INTEL_RPP_P_SMBUS,
 	PCI_DID_INTEL_RPP_S_SMBUS,
 	PCI_DID_INTEL_APL_SMBUS,
diff --git a/src/soc/intel/common/block/spi/spi.c b/src/soc/intel/common/block/spi/spi.c
index 5b45facd4c..1dc12d0b45 100644
--- a/src/soc/intel/common/block/spi/spi.c
+++ b/src/soc/intel/common/block/spi/spi.c
@@ -141,6 +141,9 @@ static const unsigned short pci_device_ids[] = {
 	PCI_DID_INTEL_MTL_GSPI0,
 	PCI_DID_INTEL_MTL_GSPI1,
 	PCI_DID_INTEL_MTL_GSPI2,
+	PCI_DID_INTEL_ARL_GSPI0,
+	PCI_DID_INTEL_ARL_GSPI1,
+	PCI_DID_INTEL_ARL_GSPI2,
 	PCI_DID_INTEL_APL_SPI0,
 	PCI_DID_INTEL_APL_SPI1,
 	PCI_DID_INTEL_APL_SPI2,
diff --git a/src/soc/intel/common/block/sram/sram.c b/src/soc/intel/common/block/sram/sram.c
index f4eda9790d..35777d98ba 100644
--- a/src/soc/intel/common/block/sram/sram.c
+++ b/src/soc/intel/common/block/sram/sram.c
@@ -43,6 +43,7 @@ static const unsigned short pci_device_ids[] = {
 	PCI_DID_INTEL_MTL_IOE_M_SRAM,
 	PCI_DID_INTEL_MTL_IOE_P_SRAM,
 	PCI_DID_INTEL_MTL_CRASHLOG_SRAM,
+	PCI_DID_INTEL_ARL_SOC_SRAM,
 	PCI_DID_INTEL_APL_SRAM,
 	PCI_DID_INTEL_GLK_SRAM,
 	PCI_DID_INTEL_CMP_SRAM,
diff --git a/src/soc/intel/common/block/systemagent/systemagent.c b/src/soc/intel/common/block/systemagent/systemagent.c
index bb3b821c44..b3f8c0c695 100644
--- a/src/soc/intel/common/block/systemagent/systemagent.c
+++ b/src/soc/intel/common/block/systemagent/systemagent.c
@@ -440,6 +440,8 @@ static const unsigned short systemagent_ids[] = {
 	PCI_DID_INTEL_MTL_P_ID_3,
 	PCI_DID_INTEL_MTL_P_ID_4,
 	PCI_DID_INTEL_MTL_P_ID_5,
+	PCI_DID_INTEL_ARL_H_ID_1,
+	PCI_DID_INTEL_ARL_H_ID_2,
 	PCI_DID_INTEL_GLK_NB,
 	PCI_DID_INTEL_APL_NB,
 	PCI_DID_INTEL_CNL_ID_U,
diff --git a/src/soc/intel/common/block/tracehub/tracehub.c b/src/soc/intel/common/block/tracehub/tracehub.c
index ab1d4a6b99..65eadf33b2 100644
--- a/src/soc/intel/common/block/tracehub/tracehub.c
+++ b/src/soc/intel/common/block/tracehub/tracehub.c
@@ -46,6 +46,7 @@ static const unsigned short pci_device_ids[] = {
 	PCI_DID_INTEL_PTL_H_TRACEHUB,
 	PCI_DID_INTEL_PTL_U_H_TRACEHUB,
 	PCI_DID_INTEL_MTL_TRACEHUB,
+	PCI_DID_INTEL_ARL_TRACEHUB,
 	PCI_DID_INTEL_RPL_TRACEHUB,
 	0
 };
diff --git a/src/soc/intel/common/block/uart/uart.c b/src/soc/intel/common/block/uart/uart.c
index 839f54ebe5..2c1075993a 100644
--- a/src/soc/intel/common/block/uart/uart.c
+++ b/src/soc/intel/common/block/uart/uart.c
@@ -375,6 +375,9 @@ static const unsigned short pci_device_ids[] = {
 	PCI_DID_INTEL_MTL_UART0,
 	PCI_DID_INTEL_MTL_UART1,
 	PCI_DID_INTEL_MTL_UART2,
+	PCI_DID_INTEL_ARL_UART0,
+	PCI_DID_INTEL_ARL_UART1,
+	PCI_DID_INTEL_ARL_UART2,
 	PCI_DID_INTEL_APL_UART0,
 	PCI_DID_INTEL_APL_UART1,
 	PCI_DID_INTEL_APL_UART2,
diff --git a/src/soc/intel/common/block/xdci/xdci.c b/src/soc/intel/common/block/xdci/xdci.c
index 3878bf9ada..a5a5158789 100644
--- a/src/soc/intel/common/block/xdci/xdci.c
+++ b/src/soc/intel/common/block/xdci/xdci.c
@@ -32,6 +32,7 @@ static const unsigned short pci_device_ids[] = {
 	PCI_DID_INTEL_PTL_H_XDCI,
 	PCI_DID_INTEL_PTL_U_H_XDCI,
 	PCI_DID_INTEL_MTL_XDCI,
+	PCI_DID_INTEL_ARL_XDCI,
 	PCI_DID_INTEL_APL_XDCI,
 	PCI_DID_INTEL_CNL_LP_XDCI,
 	PCI_DID_INTEL_GLK_XDCI,
diff --git a/src/soc/intel/common/block/xhci/xhci.c b/src/soc/intel/common/block/xhci/xhci.c
index 4892e11e16..0197f46626 100644
--- a/src/soc/intel/common/block/xhci/xhci.c
+++ b/src/soc/intel/common/block/xhci/xhci.c
@@ -136,6 +136,7 @@ static const unsigned short pci_device_ids[] = {
 	PCI_DID_INTEL_PTL_U_H_XHCI,
 	PCI_DID_INTEL_LNL_XHCI,
 	PCI_DID_INTEL_MTL_XHCI,
+	PCI_DID_INTEL_ARL_XHCI,
 	PCI_DID_INTEL_APL_XHCI,
 	PCI_DID_INTEL_CNL_LP_XHCI,
 	PCI_DID_INTEL_GLK_XHCI,
diff --git a/src/soc/intel/meteorlake/bootblock/report_platform.c b/src/soc/intel/meteorlake/bootblock/report_platform.c
index 405698962d..4744abb2c7 100644
--- a/src/soc/intel/meteorlake/bootblock/report_platform.c
+++ b/src/soc/intel/meteorlake/bootblock/report_platform.c
@@ -22,6 +22,7 @@ static struct {
 	{ CPUID_METEORLAKE_A0_2, "MeteorLake A0" },
 	{ CPUID_METEORLAKE_B0,   "MeteorLake B0" },
 	{ CPUID_METEORLAKE_C0,   "MeteorLake C0" },
+	{ CPUID_ARROWLAKE_H_A0,   "ArrowLake-H A0" },
 };
 
 static struct {
@@ -34,6 +35,8 @@ static struct {
 	{ PCI_DID_INTEL_MTL_P_ID_3, "MeteorLake P" },
 	{ PCI_DID_INTEL_MTL_P_ID_4, "MeteorLake P" },
 	{ PCI_DID_INTEL_MTL_P_ID_5, "MeteorLake P" },
+	{ PCI_DID_INTEL_ARL_H_ID_1, "ArrowLake-H" },
+	{ PCI_DID_INTEL_ARL_H_ID_2, "ArrowLake-H" },
 };
 
 static struct {
@@ -48,6 +51,9 @@ static struct {
 	{ PCI_DID_INTEL_MTL_ESPI_5, "MeteorLake SOC" },
 	{ PCI_DID_INTEL_MTL_ESPI_6, "MeteorLake SOC" },
 	{ PCI_DID_INTEL_MTL_ESPI_7, "MeteorLake SOC" },
+	{ PCI_DID_INTEL_ARL_H_ESPI_0, "ArrowLake-H SOC" },
+	{ PCI_DID_INTEL_ARL_H_ESPI_1, "ArrowLake-H SOC" },
+	{ PCI_DID_INTEL_ARL_U_ESPI_0, "ArrowLake-U SOC" },
 };
 
 static struct {
@@ -60,6 +66,8 @@ static struct {
 	{ PCI_DID_INTEL_MTL_P_GT2_3, "MeteorLake-P GT2" },
 	{ PCI_DID_INTEL_MTL_P_GT2_4, "Meteorlake-P GT2" },
 	{ PCI_DID_INTEL_MTL_P_GT2_5, "Meteorlake-P GT2" },
+	{ PCI_DID_INTEL_ARL_H_GT2_1, "ArrowLake-H GT2" },
+	{ PCI_DID_INTEL_ARL_H_GT2_2, "ArrowLake-H GT2" },
 };
 
 static inline uint8_t get_dev_revision(pci_devfn_t dev)
diff --git a/src/soc/intel/meteorlake/chip.h b/src/soc/intel/meteorlake/chip.h
index 2c93aac69d..88aaaf6435 100644
--- a/src/soc/intel/meteorlake/chip.h
+++ b/src/soc/intel/meteorlake/chip.h
@@ -65,6 +65,8 @@ static const struct {
 	{ PCI_DID_INTEL_MTL_P_ID_2, MTL_P_282_242_CORE, TDP_15W },
 	{ PCI_DID_INTEL_MTL_P_ID_3, MTL_P_682_482_CORE, TDP_28W },
 	{ PCI_DID_INTEL_MTL_P_ID_1, MTL_P_682_482_CORE, TDP_28W },
+	{ PCI_DID_INTEL_ARL_H_ID_1, MTL_P_682_482_CORE, TDP_28W },
+	{ PCI_DID_INTEL_ARL_H_ID_2, MTL_P_682_482_CORE, TDP_28W },
 };
 
 /* Types of display ports */

From 11408912112868823469e4f48d74199c678d9afb Mon Sep 17 00:00:00 2001
From: Subrata Banik <subratabanik@google.com>
Date: Mon, 12 May 2025 15:32:47 +0530
Subject: [PATCH 1005/3886] mb/google/bluey: Initialize I2C, SPI, and GPIOs in
 bootblock

Perform early initialization of essential ChromeOS-specific
peripherals and GPIOs within the `bootblock_mainboard_init()`
function. This ensures critical communication paths and
hardware states are configured early in the boot process.

Specifically, this commit:
- Calls `setup_chromeos_gpios()` to configure general AP/EC
  interrupts, and conditionally sets up GPIOs for the FPMCU
  (reset, boot mode, power rails) and Soundwire amplifiers
  (enable pins).
- Initializes the I2C bus for the H1/TPM via `i2c_init()`
  when `CONFIG_I2C_TPM` is enabled.
- Initializes the SPI bus for the ChromeEC via `qup_spi_init()`
  when `CONFIG_EC_GOOGLE_CHROMEEC` is enabled.

BUG=b:404985109
TEST=Able to build google/bluey.

Change-Id: Ic29de4c1f48f33bd1ce6a4385bfc22fdef7ab911
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87642
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/google/bluey/bootblock.c | 12 +++++++++++-
 src/mainboard/google/bluey/chromeos.c  | 14 +++++++++++++-
 2 files changed, 24 insertions(+), 2 deletions(-)

diff --git a/src/mainboard/google/bluey/bootblock.c b/src/mainboard/google/bluey/bootblock.c
index b8edccd598..cb641d8510 100644
--- a/src/mainboard/google/bluey/bootblock.c
+++ b/src/mainboard/google/bluey/bootblock.c
@@ -1,8 +1,18 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
 #include <bootblock_common.h>
+#include <soc/qupv3_i2c_common.h>
+#include <soc/qcom_qup_se.h>
+#include <soc/qupv3_spi_common.h>
+#include "board.h"
 
 void bootblock_mainboard_init(void)
 {
-	/* Placeholder */
+	setup_chromeos_gpios();
+
+	if (CONFIG(I2C_TPM))
+		i2c_init(CONFIG_DRIVER_TPM_I2C_BUS, I2C_SPEED_FAST); /* H1/TPM I2C */
+
+	if (CONFIG(EC_GOOGLE_CHROMEEC))
+		qup_spi_init(CONFIG_EC_GOOGLE_CHROMEEC_SPI_BUS, 1010 * KHz); /* EC SPI */
 }
diff --git a/src/mainboard/google/bluey/chromeos.c b/src/mainboard/google/bluey/chromeos.c
index 9fa8718e02..5dc73153b4 100644
--- a/src/mainboard/google/bluey/chromeos.c
+++ b/src/mainboard/google/bluey/chromeos.c
@@ -2,14 +2,26 @@
 
 #include <boot/coreboot_tables.h>
 #include <bootmode.h>
-#include "board.h"
 #include <drivers/tpm/cr50.h>
+#include "board.h"
 
 void setup_chromeos_gpios(void)
 {
 	gpio_input_pullup(GPIO_AP_EC_INT);
 
 	gpio_input_irq(GPIO_GSC_AP_INT, IRQ_TYPE_RISING_EDGE, GPIO_PULL_UP);
+
+	if (CONFIG(MAINBOARD_HAS_FINGERPRINT)) {
+		gpio_output(GPIO_FP_RST_L, 0);
+		if (CONFIG(MAINBOARD_HAS_FINGERPRINT_VIA_SPI)) {
+			gpio_output(GPIO_FPMCU_BOOT0, 0);
+			gpio_output(GPIO_EN_FP_RAILS, 0);
+			gpio_input_irq(GPIO_FPMCU_INT, IRQ_TYPE_LEVEL, GPIO_PULL_UP);
+		}
+	}
+
+	gpio_output(GPIO_SNDW_AMP_0_ENABLE, 0);
+	gpio_output(GPIO_SNDW_AMP_1_ENABLE, 0);
 }
 
 void fill_lb_gpios(struct lb_gpios *gpios)

From f0ad05b57ebe41352467416d803aceeb4f538ec8 Mon Sep 17 00:00:00 2001
From: John Su <john_su@compal.corp-partner.google.com>
Date: Mon, 12 May 2025 13:52:13 +0800
Subject: [PATCH 1006/3886] mb/google/brya/var/uldrenite: Fix USB_OC1 for USB3
 A0 port

According to the HW schematics, GPP_A14 should be set as USB_OC1
for the A0 port, but it was found that the USB3_A0 port did not
match the configuration, so this has been corrected.

BUG=b:410481989
TEST=emerge-nissa coreboot chromeos-bootimage

Change-Id: I2fcf15ca008eca6c74f4020c3fa7af8863a56a00
Signed-off-by: John Su <john_su@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87637
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
---
 src/mainboard/google/brya/variants/uldrenite/overridetree.cb | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/mainboard/google/brya/variants/uldrenite/overridetree.cb b/src/mainboard/google/brya/variants/uldrenite/overridetree.cb
index 78fec3dab2..8b17bd94c2 100644
--- a/src/mainboard/google/brya/variants/uldrenite/overridetree.cb
+++ b/src/mainboard/google/brya/variants/uldrenite/overridetree.cb
@@ -91,7 +91,7 @@ chip soc/intel/alderlake
 	register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)"    # User Facing Camera
 	register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)"    # World Facing Camera
 
-	register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)"	# USB3/2 Type A port A0
+	register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC1)"	# USB3/2 Type A port A0
 
 	register "tcss_ports[0]" = "TCSS_PORT_DEFAULT(OC_SKIP)"
 	register "tcss_ports[1]" = "TCSS_PORT_DEFAULT(OC_SKIP)"

From 4f7ea3667c0a3467253c5496603f8847f3e0c5de Mon Sep 17 00:00:00 2001
From: Kenneth Chan <kenneth.chan@quanta.corp-partner.google.com>
Date: Fri, 9 May 2025 16:21:47 +0800
Subject: [PATCH 1007/3886] mb/google/rex/var/kanix: Tune camera I2C timing

1. frequency changes to 366 kHz from 457 kHz
2. tHIGH changes to 0.8 us from 0.514 us
3. tSU:STA changes to 0.68 us from 0.56 us

BUG=b:417375114
BRANCH=firmware-rex-15709.B
TEST=1.emerge-rex coreboot chromeos-bootimage
     2.EA is measured and verified by HW
Change-Id: I996885a9acf2eea7f49ecf2fcd4f7d3fda842c8e
Signed-off-by: Kenneth Chan <kenneth.chan@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87580
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
---
 src/mainboard/google/rex/variants/kanix/overridetree.cb | 7 ++++++-
 1 file changed, 6 insertions(+), 1 deletion(-)

diff --git a/src/mainboard/google/rex/variants/kanix/overridetree.cb b/src/mainboard/google/rex/variants/kanix/overridetree.cb
index 7ba3538879..31fbf555a6 100644
--- a/src/mainboard/google/rex/variants/kanix/overridetree.cb
+++ b/src/mainboard/google/rex/variants/kanix/overridetree.cb
@@ -140,7 +140,12 @@ chip soc/intel/meteorlake
 			.speed = I2C_SPEED_FAST,
 			.rise_time_ns = 900,
 			.fall_time_ns = 400,
-			.data_hold_time_ns = 50,
+			.speed_config[0] = {
+				.speed = I2C_SPEED_FAST,
+				.scl_lcnt = 163,
+				.scl_hcnt = 85,
+				.sda_hold = 40,
+			}
 		},
 	}"
 

From d263e0bd927d94beb9449c4de6bf111c8df12cbb Mon Sep 17 00:00:00 2001
From: Maximilian Brune <maximilian.brune@9elements.com>
Date: Tue, 25 Feb 2025 13:29:28 +0100
Subject: [PATCH 1008/3886] soc/amd/glinda/Makefile.mk: Use relative address
 for APOB_NV

amdfwtool is always setting BIOS relative as address_mode for the APOB
NV binary. So instead of giving amdfwtool a memory address we should
give it a flash relative address.

Change-Id: I4596902ca6c9880217247ce6fe96fcb516aec54d
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86597
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
---
 src/soc/amd/glinda/Makefile.mk | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/src/soc/amd/glinda/Makefile.mk b/src/soc/amd/glinda/Makefile.mk
index eb488d6a0f..0232f2f55e 100644
--- a/src/soc/amd/glinda/Makefile.mk
+++ b/src/soc/amd/glinda/Makefile.mk
@@ -126,11 +126,13 @@ PSP_ELF_FILE=$(objcbfs)/bootblock.elf
 PSP_BIOSBIN_SIZE=$(shell $(READELF_bootblock) -Wl $(PSP_ELF_FILE) | grep LOAD | awk '{print $$5}')
 PSP_BIOSBIN_DEST=$(shell $(READELF_bootblock) -Wl $(PSP_ELF_FILE) | grep LOAD | awk '{print $$3}')
 
+FMAP_FLASH_START=$(call get_fmap_value,FMAP_SECTION_FLASH_START)
 ifneq ($(CONFIG_SOC_AMD_COMMON_BLOCK_APOB_NV_DISABLE),y)
 # type = 0x63 - construct APOB NV base/size from flash map
 # The flashmap section used for this is expected to be named RW_MRC_CACHE
 APOB_NV_SIZE=$(call get_fmap_value,FMAP_SECTION_RW_MRC_CACHE_SIZE)
-APOB_NV_BASE=$(call get_fmap_value,FMAP_SECTION_RW_MRC_CACHE_START)
+APOB_NV_BASE=$(call _tohex,$(call int-subtract, \
+	$(call get_fmap_value,FMAP_SECTION_RW_MRC_CACHE_START) $(FMAP_FLASH_START)))
 endif # !CONFIG_SOC_AMD_COMMON_BLOCK_APOB_NV_DISABLE
 
 ifeq ($(CONFIG_VBOOT_STARTS_BEFORE_BOOTBLOCK),y)

From 6f9de346ae35cd4619443d88029b0b1d713bb9c7 Mon Sep 17 00:00:00 2001
From: Felix Held <felix-coreboot@felixheld.de>
Date: Wed, 14 May 2025 15:12:08 +0200
Subject: [PATCH 1009/3886] Revert "soc/amd/glinda/Makefile.mk: Use relative
 address for APOB_NV"

This reverts commit d263e0bd927d94beb9449c4de6bf111c8df12cbb.

Commit a7eb390796ef ("mb/*/*/*.fmd: Start flash at 0") changed the FMAP
to always begin at 0 and not at the x86 MMIO address where it gets
mapped, so the commit reverted by this patch isn't needed any more after
the FMAP change has landed.

Change-Id: I6d866ce3a3395f9fe70c47892a224e89ff89b20e
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87673
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
---
 src/soc/amd/glinda/Makefile.mk | 4 +---
 1 file changed, 1 insertion(+), 3 deletions(-)

diff --git a/src/soc/amd/glinda/Makefile.mk b/src/soc/amd/glinda/Makefile.mk
index 0232f2f55e..eb488d6a0f 100644
--- a/src/soc/amd/glinda/Makefile.mk
+++ b/src/soc/amd/glinda/Makefile.mk
@@ -126,13 +126,11 @@ PSP_ELF_FILE=$(objcbfs)/bootblock.elf
 PSP_BIOSBIN_SIZE=$(shell $(READELF_bootblock) -Wl $(PSP_ELF_FILE) | grep LOAD | awk '{print $$5}')
 PSP_BIOSBIN_DEST=$(shell $(READELF_bootblock) -Wl $(PSP_ELF_FILE) | grep LOAD | awk '{print $$3}')
 
-FMAP_FLASH_START=$(call get_fmap_value,FMAP_SECTION_FLASH_START)
 ifneq ($(CONFIG_SOC_AMD_COMMON_BLOCK_APOB_NV_DISABLE),y)
 # type = 0x63 - construct APOB NV base/size from flash map
 # The flashmap section used for this is expected to be named RW_MRC_CACHE
 APOB_NV_SIZE=$(call get_fmap_value,FMAP_SECTION_RW_MRC_CACHE_SIZE)
-APOB_NV_BASE=$(call _tohex,$(call int-subtract, \
-	$(call get_fmap_value,FMAP_SECTION_RW_MRC_CACHE_START) $(FMAP_FLASH_START)))
+APOB_NV_BASE=$(call get_fmap_value,FMAP_SECTION_RW_MRC_CACHE_START)
 endif # !CONFIG_SOC_AMD_COMMON_BLOCK_APOB_NV_DISABLE
 
 ifeq ($(CONFIG_VBOOT_STARTS_BEFORE_BOOTBLOCK),y)

From 9979be74822ecb963277c85ec58946f16e4b98f5 Mon Sep 17 00:00:00 2001
From: Jeremy Compostella <jeremy.compostella@intel.com>
Date: Fri, 9 May 2025 11:08:48 -0700
Subject: [PATCH 1010/3886] drivers/intel/fsp2_0: Remove redundant NULL checks
 and simplify code

This commit refactors the code by eliminating unnecessary NULL pointer
checks for the `efi_bmp_image_header header` parameter in several
functions. The calling function `fsp_convert_bmp_to_gop_blt` already
verifies that the `header` pointer is not NULL before invoking these
functions, rendering these checks redundant. Similarly, checks for
`adjusted_x` and `adjusted_y` in `calculate_adj_height_width` have been
removed. This streamlines the code and reduces unnecessary operations.

Additionally, the `is_bmp_image_compressed` function has been simplified
for improved readability by directly returning the result of the
compression type comparison.

Change-Id: Ia8afcac0fb21633e379f5d8b9713ba6f8b92c1c8
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87616
Reviewed-by: Zhixing Ma <zhixing.ma@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Reviewed-by: Cliff Huang <cliff.huang@intel.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
---
 src/drivers/intel/fsp2_0/fsp_gop_blt.c | 32 +-------------------------
 1 file changed, 1 insertion(+), 31 deletions(-)

diff --git a/src/drivers/intel/fsp2_0/fsp_gop_blt.c b/src/drivers/intel/fsp2_0/fsp_gop_blt.c
index 2ab716c4b7..32d28e873c 100644
--- a/src/drivers/intel/fsp2_0/fsp_gop_blt.c
+++ b/src/drivers/intel/fsp2_0/fsp_gop_blt.c
@@ -9,9 +9,6 @@
 
 static bool is_bmp_image_valid(efi_bmp_image_header *header)
 {
-	if (header == NULL)
-		return false;
-
 	/* Check if the BMP Header Signature is valid */
 	if (header->CharB != 'B' || header->CharM != 'M')
 		return false;
@@ -31,20 +28,11 @@ static bool is_bmp_image_valid(efi_bmp_image_header *header)
 
 static bool is_bmp_image_compressed(efi_bmp_image_header *header)
 {
-	if (header == NULL)
-		return false;
-
-	if (header->CompressionType != 0)
-		return true;
-
-	return false;
+	return header->CompressionType != 0;
 }
 
 static bool is_bitmap_format_supported(efi_bmp_image_header *header)
 {
-	if (header == NULL)
-		return false;
-
 	/*
 	 * Check BITMAP format is supported
 	 * BMP_IMAGE_HEADER = BITMAP_FILE_HEADER + BITMAP_INFO_HEADER
@@ -58,9 +46,6 @@ static bool is_bitmap_format_supported(efi_bmp_image_header *header)
 
 static bool do_bmp_image_authentication(efi_bmp_image_header *header)
 {
-	if (header == NULL)
-		return false;
-
 	if (!is_bmp_image_valid(header)) {
 		printk(BIOS_ERR, "%s: BMP Image Header is invalid.\n", __func__);
 		return false;
@@ -88,9 +73,6 @@ static uint32_t calculate_blt_buffer_size(efi_bmp_image_header *header)
 {
 	uint32_t blt_buffer_size;
 
-	if (header == NULL)
-		return 0;
-
 	/* Calculate the size required for BLT buffer */
 	blt_buffer_size = header->PixelWidth * header->PixelHeight *
 			 sizeof(efi_graphics_output_blt_pixel);
@@ -104,9 +86,6 @@ static int get_color_map_num(efi_bmp_image_header *header)
 {
 	int col_map_number;
 
-	if (header == NULL)
-		return -1;
-
 	switch (header->BitPerPixel) {
 	case 1:
 		col_map_number = 2;
@@ -176,9 +155,6 @@ static int get_color_map_num(efi_bmp_image_header *header)
 static bool calculate_adj_height_width(const efi_bmp_image_header *header, size_t *adjusted_x,
 	 size_t *adjusted_y, enum lb_fb_orientation orientation, int blt_width, int blt_height)
 {
-	if (!header || !adjusted_x || !adjusted_y)
-		return false;
-
 	size_t flipped_x = header->PixelWidth - blt_width - 1;
 	size_t flipped_y = header->PixelHeight - blt_height - 1;
 
@@ -248,9 +224,6 @@ static efi_graphics_output_blt_pixel *get_gop_blt_pixel(
 	size_t gop_y;
 	size_t gop_width;
 
-	if (!header || !gop_blt_buffer)
-		return NULL;
-
 	switch (orientation) {
 	case LB_FB_ORIENTATION_LEFT_UP:
 	case LB_FB_ORIENTATION_RIGHT_UP:
@@ -324,9 +297,6 @@ static void *fill_blt_buffer(efi_bmp_image_header *header,
 	efi_bmp_color_map *bmp_color_map;
 	size_t image_index;
 
-	if (header == NULL)
-		return NULL;
-
 	gop_blt_ptr = malloc(sizeof(blt_buffer_size));
 	if (!gop_blt_ptr)
 		die("%s: out of memory. Consider increasing the `CONFIG_HEAP_SIZE`\n",

From af7fb83ed0bb56a71a1bca42e439162d82e3265e Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Fri, 9 May 2025 13:16:13 -0500
Subject: [PATCH 1011/3886] soc/intel/apollolake: Hook up S0ix setting to
 option API

Hook up the s0ix_enable setting to the option API, so it can be changed
at runtime without recompilation. Default to the value set by the
mainboard.

Change-Id: Icec6dd7d3c80fba5235f9aff5bef8e165302bf2a
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87646
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/soc/intel/apollolake/chip.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c
index c5553780ea..943573fff7 100644
--- a/src/soc/intel/apollolake/chip.c
+++ b/src/soc/intel/apollolake/chip.c
@@ -693,6 +693,7 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *silupd)
 	memcpy(silconfig->SataPortsHotPlug, cfg->sata_ports_hot_plug,
 		sizeof(silconfig->SataPortsHotPlug));
 
+	cfg->lpss_s0ix_enable = get_uint_option("s0ix_enable", cfg->lpss_s0ix_enable);
 	silconfig->LPSS_S0ixEnable = cfg->lpss_s0ix_enable;
 
 	/* Disable monitor mwait since it is broken due to a hardware bug

From de9d76c761376fa1b0fadc80308d1edb71bdd303 Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Mon, 12 May 2025 16:21:26 +0100
Subject: [PATCH 1012/3886] mb/starlabs/starbook/tgl: Configure the eSPI GPIOs

Let coreboot configure the eSPI GPIOs, to ensure they are correct
rather than letting FSP do it.

Change-Id: I14dc740be9a770b662dd61bfdc4f4ace8973d998
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87648
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
---
 .../starlabs/starbook/variants/tgl/gpio.c          | 14 +++++++-------
 1 file changed, 7 insertions(+), 7 deletions(-)

diff --git a/src/mainboard/starlabs/starbook/variants/tgl/gpio.c b/src/mainboard/starlabs/starbook/variants/tgl/gpio.c
index 82d1a21a0e..0bb71f4130 100644
--- a/src/mainboard/starlabs/starbook/variants/tgl/gpio.c
+++ b/src/mainboard/starlabs/starbook/variants/tgl/gpio.c
@@ -26,13 +26,13 @@ const struct pad_config gpio_table[] = {
 	PAD_CFG_NF(GPD8, NONE, DEEP, NF1),				/* Bluetooth Suspend */
 
 	/* eSPI */
-	// PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_A0, UP_20K, DEEP, NF1),	/* eSPI IO 0 */
-	// PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_A1, UP_20K, DEEP, NF1),	/* eSPI IO 1 */
-	// PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_A2, UP_20K, DEEP, NF1),	/* eSPI IO 2 */
-	// PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_A3, UP_20K, DEEP, NF1),	/* eSPI IO 3 */
-	// PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_A4, UP_20K, DEEP, NF1),	/* eSPI CS 0 */
-	// PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_A5, UP_20K, DEEP, NF1),	/* eSPI Clk */
-	// PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_A6, NONE, DEEP, NF1),	/* eSPI Reset */
+	PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_A0, UP_20K, DEEP, NF1),		/* eSPI IO 0 */
+	PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_A1, UP_20K, DEEP, NF1),		/* eSPI IO 1 */
+	PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_A2, UP_20K, DEEP, NF1),		/* eSPI IO 2 */
+	PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_A3, UP_20K, DEEP, NF1),		/* eSPI IO 3 */
+	PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_A4, UP_20K, DEEP, NF1),		/* eSPI CS 0 */
+	PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_A5, UP_20K, DEEP, NF1),		/* eSPI Clk */
+	PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_A6, NONE, DEEP, NF1),		/* eSPI Reset */
 
 	/* Touchpad */
 	PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1),				/* Data */

From 85972101e66c584b3cdf0b6f1322e794e6bcef72 Mon Sep 17 00:00:00 2001
From: Yu-Ping Wu <yupingso@chromium.org>
Date: Tue, 13 May 2025 09:40:33 +0800
Subject: [PATCH 1013/3886] commonlib/device_tree: Make *path const in
 dt_find_node()

dt_find_node() looks up nodes specified by the `const char **path`
array, without modifying the strings in the array. Therefore, the char
pointers in the array could be changed to const.

Change-Id: I8d330e78d0977bae54996bb622190f6546fcb59f
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87653
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
---
 src/commonlib/device_tree.c                   | 4 ++--
 src/commonlib/include/commonlib/device_tree.h | 5 +++--
 2 files changed, 5 insertions(+), 4 deletions(-)

diff --git a/src/commonlib/device_tree.c b/src/commonlib/device_tree.c
index b5c0ede7f3..c4fbae986d 100644
--- a/src/commonlib/device_tree.c
+++ b/src/commonlib/device_tree.c
@@ -1039,7 +1039,7 @@ void dt_read_cell_props(const struct device_tree_node *node, u32 *addrcp,
 }
 
 static struct device_tree_node *_dt_find_node(struct device_tree_node *parent,
-					      const char **path, u32 *addrcp,
+					      const char *const *path, u32 *addrcp,
 					      u32 *sizecp, int create)
 {
 	struct device_tree_node *node, *found = NULL;
@@ -1091,7 +1091,7 @@ static struct device_tree_node *_dt_find_node(struct device_tree_node *parent,
  * @return		The found/created node, or NULL.
  */
 struct device_tree_node *dt_find_node(struct device_tree_node *parent,
-				      const char **path, u32 *addrcp,
+				      const char *const *path, u32 *addrcp,
 				      u32 *sizecp, int create)
 {
 	/* Initialize cells to default values according to FDT spec. */
diff --git a/src/commonlib/include/commonlib/device_tree.h b/src/commonlib/include/commonlib/device_tree.h
index c15d7ae5b1..f51f827593 100644
--- a/src/commonlib/include/commonlib/device_tree.h
+++ b/src/commonlib/include/commonlib/device_tree.h
@@ -154,8 +154,9 @@ void dt_read_cell_props(const struct device_tree_node *node, u32 *addrcp,
 			u32 *sizecp);
 /* Look up or create a node relative to a parent node, through its path
    represented as an array of strings. */
-struct device_tree_node *dt_find_node(struct device_tree_node *parent, const char **path,
-			     u32 *addrcp, u32 *sizecp, int create);
+struct device_tree_node *dt_find_node(struct device_tree_node *parent,
+				      const char *const *path, u32 *addrcp,
+				      u32 *sizecp, int create);
 struct device_tree_node *dt_find_node_by_phandle(struct device_tree_node *root,
 						 uint32_t phandle);
 /* Look up or create a node in the tree, through its path

From d4a759a068a4631d73f96a2e16f6f8ee878d1235 Mon Sep 17 00:00:00 2001
From: Tim Crawford <tcrawford@system76.com>
Date: Fri, 30 Aug 2024 10:43:33 -0600
Subject: [PATCH 1014/3886] mb/system76/mtl: darp10: Add TCSS configs

Fixes using USB3 devices at USB3 speeds in all ports.

This fix requires `EnableTcssCovTypeA`, which is not available in the
coreboot FSP headers and not available upstream as Intel will not make a
Client FSP release.

Change-Id: I9bc6c5fc4c13bfa2e31ee1ce334b91e151373b6e
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83696
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jeremy Soller <jeremy@system76.com>
---
 .../mtl/variants/darp10/overridetree.cb       | 21 ++++++++++++++++++-
 .../system76/mtl/variants/darp10/ramstage.c   |  8 +++++++
 2 files changed, 28 insertions(+), 1 deletion(-)

diff --git a/src/mainboard/system76/mtl/variants/darp10/overridetree.cb b/src/mainboard/system76/mtl/variants/darp10/overridetree.cb
index 56487395b9..8baa5560b9 100644
--- a/src/mainboard/system76/mtl/variants/darp10/overridetree.cb
+++ b/src/mainboard/system76/mtl/variants/darp10/overridetree.cb
@@ -5,7 +5,26 @@ chip soc/intel/meteorlake
 		subsystemid 0x1558 0xa743 inherit
 
 		device ref tbt_pcie_rp0 on end
-		device ref tcss_xhci on end
+		device ref tcss_xhci on
+			register "tcss_ports[0]" = "TCSS_PORT_DEFAULT(OC_SKIP)"
+			register "tcss_ports[1]" = "TCSS_PORT_DEFAULT(OC_SKIP)"
+			# TCP2 is used as HDMI
+			# TCP3 is not used
+			chip drivers/usb/acpi
+				device ref tcss_root_hub on
+					chip drivers/usb/acpi
+						register "desc" = ""TBT Type-C""
+						register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
+						device ref tcss_usb3_port0 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB Type-C""
+						register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
+						device ref tcss_usb3_port1 on end
+					end
+				end
+			end
+		end
 		device ref tcss_dma0 on end
 		device ref xhci on
 			register "usb2_ports" = "{
diff --git a/src/mainboard/system76/mtl/variants/darp10/ramstage.c b/src/mainboard/system76/mtl/variants/darp10/ramstage.c
index 276279484f..0e3baf2ad6 100644
--- a/src/mainboard/system76/mtl/variants/darp10/ramstage.c
+++ b/src/mainboard/system76/mtl/variants/darp10/ramstage.c
@@ -4,6 +4,14 @@
 
 void mainboard_silicon_init_params(FSP_S_CONFIG *params)
 {
+	// Enable TCP1 USB-A conversion
+	// BIT 0:3 is mapping to PCH XHCI USB2 port
+	// BIT 4:5 is reserved
+	// BIT 6 is orientational
+	// BIT 7 is enable
+	// TODO: Add to coreboot FSP headers as no Client FSP release will be made.
+	//params->EnableTcssCovTypeA[1] = 0x82;
+
 	// XXX: Enabling C10 reporting causes system to constantly enter and
 	// exit opportunistic suspend when idle.
 	params->PchEspiHostC10ReportEnable = 0;

From f1f58b20b9148b167a38db106d2008b84dcd1ae9 Mon Sep 17 00:00:00 2001
From: Alex Gan <ot_alex.gan@mediatek.corp-partner.google.com>
Date: Fri, 20 Dec 2024 17:46:43 +0800
Subject: [PATCH 1015/3886] soc/mediatek/mt8189: Add SPI driver support

Add SPI controller driver code with support for 6 buses (SPI0 to SPI5).

BUG=b:379008996
BRANCH=none
TEST=build pass

Signed-off-by: Alex Gan <ot_alex.gan@mediatek.corp-partner.google.com>
Change-Id: I313eddefed466a5182b6e48ac1900674cc06b0b6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87424
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
---
 src/soc/mediatek/mt8189/Makefile.mk           |  2 +-
 .../mediatek/mt8189/include/soc/addressmap.h  |  6 ++
 src/soc/mediatek/mt8189/include/soc/spi.h     | 16 ++++
 src/soc/mediatek/mt8189/spi.c                 | 82 +++++++++++++++++++
 4 files changed, 105 insertions(+), 1 deletion(-)

diff --git a/src/soc/mediatek/mt8189/Makefile.mk b/src/soc/mediatek/mt8189/Makefile.mk
index eefdae1f41..3c506118b4 100644
--- a/src/soc/mediatek/mt8189/Makefile.mk
+++ b/src/soc/mediatek/mt8189/Makefile.mk
@@ -5,7 +5,7 @@ ifeq ($(CONFIG_SOC_MEDIATEK_MT8189),y)
 all-y += ../common/flash_controller.c
 all-y += ../common/gpio.c ../common/gpio_op.c ../common/gpio_eint_v2.c gpio.c gpio_eint.c
 all-y += ../common/i2c.c ../common/i2c_common.c i2c.c
-all-$(CONFIG_SPI_FLASH) += spi.c
+all-$(CONFIG_SPI_FLASH) += ../common/spi.c spi.c
 all-y += ../common/timer_prepare.c timer.c
 all-y += ../common/uart.c
 
diff --git a/src/soc/mediatek/mt8189/include/soc/addressmap.h b/src/soc/mediatek/mt8189/include/soc/addressmap.h
index c02f25accd..366a94ef16 100644
--- a/src/soc/mediatek/mt8189/include/soc/addressmap.h
+++ b/src/soc/mediatek/mt8189/include/soc/addressmap.h
@@ -44,6 +44,12 @@ enum {
 	DPM_DM_SRAM_BASE2		= IO_PHYS + 0x00A20000,
 	DPM_CFG_BASE2			= IO_PHYS + 0x00A40000,
 	UART0_BASE			= IO_PHYS + 0x01001000,
+	SPI0_BASE			= IO_PHYS + 0x01010800,
+	SPI1_BASE			= IO_PHYS + 0x01011800,
+	SPI2_BASE			= IO_PHYS + 0x01012800,
+	SPI3_BASE			= IO_PHYS + 0x01013800,
+	SPI4_BASE			= IO_PHYS + 0x01014800,
+	SPI5_BASE			= IO_PHYS + 0x01015800,
 	SFLASH_REG_BASE			= IO_PHYS + 0x01018000,
 	PERI_AO_BCRM_BASE		= IO_PHYS + 0x01035000,
 	PERICFG_AO_BASE			= IO_PHYS + 0x01036000,
diff --git a/src/soc/mediatek/mt8189/include/soc/spi.h b/src/soc/mediatek/mt8189/include/soc/spi.h
index 01e866bbd7..a742bbdfc5 100644
--- a/src/soc/mediatek/mt8189/include/soc/spi.h
+++ b/src/soc/mediatek/mt8189/include/soc/spi.h
@@ -8,6 +8,22 @@
 #ifndef __SOC_MEDIATEK_MT8189_INCLUDE_SOC_SPI_H__
 #define __SOC_MEDIATEK_MT8189_INCLUDE_SOC_SPI_H__
 
+#include <soc/spi_common.h>
+
+#define SPI_BUS_NUMBER 6
+
+#define GET_SCK_REG(x) ((x)->spi_cfg2_reg)
+#define GET_TICK_DLY_REG(x) ((x)->spi_cmd_reg)
+
+DEFINE_BITFIELD(SPI_CFG_CS_HOLD, 15, 0)
+DEFINE_BITFIELD(SPI_CFG_CS_SETUP, 31, 16)
+DEFINE_BITFIELD(SPI_CFG_SCK_LOW, 31, 16)
+DEFINE_BITFIELD(SPI_CFG_SCK_HIGH, 15, 0)
+DEFINE_BITFIELD(SPI_CFG1_CS_IDLE, 7, 0)
+DEFINE_BITFIELD(SPI_CFG1_PACKET_LOOP, 15, 8)
+DEFINE_BITFIELD(SPI_CFG1_PACKET_LENGTH, 31, 16)
+DEFINE_BITFIELD(SPI_TICK_DLY, 28, 22)
+
 /* Initialize SPI NOR Flash Controller */
 void mtk_snfc_init(void);
 
diff --git a/src/soc/mediatek/mt8189/spi.c b/src/soc/mediatek/mt8189/spi.c
index 410b53eb8a..4de218245f 100644
--- a/src/soc/mediatek/mt8189/spi.c
+++ b/src/soc/mediatek/mt8189/spi.c
@@ -10,6 +10,72 @@
 #include <soc/spi.h>
 #include <spi_flash.h>
 
+struct mtk_spi_bus spi_bus[SPI_BUS_NUMBER] = {
+	{
+		.regs = (void *)SPI0_BASE,
+		.cs_gpio = GPIO(SPIM0_CSB),
+	},
+	{
+		.regs = (void *)SPI1_BASE,
+		.cs_gpio = GPIO(SPIM1_CSB),
+	},
+	{
+		.regs = (void *)SPI2_BASE,
+		.cs_gpio = GPIO(SPIM2_CSB),
+	},
+	{
+		.regs = (void *)SPI3_BASE,
+		.cs_gpio = GPIO(GPIO00),
+	},
+	{
+		.regs = (void *)SPI4_BASE,
+		.cs_gpio = GPIO(GPIO04),
+	},
+	{
+		.regs = (void *)SPI5_BASE,
+		.cs_gpio = GPIO(GPIO08),
+	},
+};
+
+static const struct pad_func pad_funcs[SPI_BUS_NUMBER][4] = {
+	{
+		PAD_FUNC_DOWN(SPIM0_MISO, SPIM0_MI),
+		PAD_FUNC_GPIO(SPIM0_CSB),
+		PAD_FUNC_DOWN(SPIM0_MOSI, SPIM0_MO),
+		PAD_FUNC_DOWN(SPIM0_CLK, SPIM0_CLK),
+	},
+	{
+		PAD_FUNC_DOWN(SPIM1_MISO, SPIM1_MI),
+		PAD_FUNC_GPIO(SPIM1_CSB),
+		PAD_FUNC_DOWN(SPIM1_MOSI, SPIM1_MO),
+		PAD_FUNC_DOWN(SPIM1_CLK, SPIM1_CLK),
+	},
+	{
+		PAD_FUNC_DOWN(SPIM2_MISO, SPIM2_MI),
+		PAD_FUNC_GPIO(SPIM2_CSB),
+		PAD_FUNC_DOWN(SPIM2_MOSI, SPIM2_MO),
+		PAD_FUNC_DOWN(SPIM2_CLK, SPIM2_CLK),
+	},
+	{
+		PAD_FUNC_DOWN(GPIO03, SPIM3_A_MI),
+		PAD_FUNC_GPIO(GPIO00),
+		PAD_FUNC_DOWN(GPIO02, SPIM3_A_MO),
+		PAD_FUNC_DOWN(GPIO01, SPIM3_A_CLK),
+	},
+	{
+		PAD_FUNC_DOWN(GPIO07, SPIM4_A_MI),
+		PAD_FUNC_GPIO(GPIO04),
+		PAD_FUNC_DOWN(GPIO06, SPIM4_A_MO),
+		PAD_FUNC_DOWN(GPIO05, SPIM4_A_CLK),
+	},
+	{
+		PAD_FUNC_DOWN(GPIO11, SPIM5_A_MI),
+		PAD_FUNC_GPIO(GPIO08),
+		PAD_FUNC_DOWN(GPIO10, SPIM5_A_MO),
+		PAD_FUNC_DOWN(GPIO09, SPIM5_A_CLK),
+	},
+};
+
 static const struct pad_func nor_pinmux[4] = {
 	PAD_FUNC(SPINOR_CK, SPINOR_CK, GPIO_PULL_DOWN),
 	PAD_FUNC(SPINOR_CS, SPINOR_CS, GPIO_PULL_UP),
@@ -23,12 +89,28 @@ void mtk_snfc_init(void)
 		mtk_snfc_init_pad_func(&nor_pinmux[i], GPIO_DRV_8_MA);
 }
 
+void mtk_spi_set_gpio_pinmux(unsigned int bus, enum spi_pad_mask pad_select)
+{
+	assert(bus < SPI_BUS_NUMBER);
+	const struct pad_func *ptr;
+
+	ptr = pad_funcs[bus];
+
+	for (unsigned int i = 0; i < ARRAY_SIZE(pad_funcs[0]); i++)
+		gpio_set_mode(ptr[i].gpio, ptr[i].func);
+}
+
 static const struct spi_ctrlr spi_flash_ctrlr = {
 	.max_xfer_size = 65535,
 	.flash_probe = mtk_spi_flash_probe,
 };
 
 const struct spi_ctrlr_buses spi_ctrlr_bus_map[] = {
+	{
+		.ctrlr = &spi_ctrlr,
+		.bus_start = 0,
+		.bus_end = SPI_BUS_NUMBER - 1,
+	},
 	{
 		.ctrlr = &spi_flash_ctrlr,
 		.bus_start = CONFIG_BOOT_DEVICE_SPI_FLASH_BUS,

From ca9616b9840242a1811e9ab858e412b5c2ef2ceb Mon Sep 17 00:00:00 2001
From: Tim Crawford <tcrawford@system76.com>
Date: Tue, 1 Apr 2025 10:51:16 -0600
Subject: [PATCH 1016/3886] ec/system76/ec: Add config for 2nd fan without GPU

The darp10 has a second fan but no dGPU. The NFAN Method must exist, so
use the default hwmon names of "fan1" and "fan2" for labels.

Change-Id: I553deefea374b9dd916be6611850fca61afd490d
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87068
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jeremy Soller <jeremy@system76.com>
---
 src/ec/system76/ec/Kconfig         | 12 +++++++++---
 src/ec/system76/ec/acpi/s76.asl    |  7 ++++++-
 src/mainboard/system76/mtl/Kconfig |  2 ++
 3 files changed, 17 insertions(+), 4 deletions(-)

diff --git a/src/ec/system76/ec/Kconfig b/src/ec/system76/ec/Kconfig
index 4b7191241b..f0702a76d1 100644
--- a/src/ec/system76/ec/Kconfig
+++ b/src/ec/system76/ec/Kconfig
@@ -6,16 +6,22 @@ config EC_SYSTEM76_EC
 	  System76 EC
 
 config EC_SYSTEM76_EC_BAT_THRESHOLDS
-	depends on EC_SYSTEM76_EC
 	bool
 	default y
+	depends on EC_SYSTEM76_EC
+
+config EC_SYSTEM76_EC_FAN2
+	bool
+	default n
+	depends on EC_SYSTEM76_EC
 
 config EC_SYSTEM76_EC_DGPU
-	depends on EC_SYSTEM76_EC
 	bool
 	default n
+	select EC_SYSTEM76_EC_FAN2
+	depends on EC_SYSTEM76_EC
 
 config EC_SYSTEM76_EC_OLED
-	depends on EC_SYSTEM76_EC
 	bool
 	default n
+	depends on EC_SYSTEM76_EC
diff --git a/src/ec/system76/ec/acpi/s76.asl b/src/ec/system76/ec/acpi/s76.asl
index 06000a4077..f3e2deccdf 100644
--- a/src/ec/system76/ec/acpi/s76.asl
+++ b/src/ec/system76/ec/acpi/s76.asl
@@ -126,9 +126,14 @@ Device (S76D) {
 	// Fan names
 	Method (NFAN, 0, Serialized) {
 		Return (Package() {
-			"CPU fan",
 #if CONFIG(EC_SYSTEM76_EC_DGPU)
+			"CPU fan",
 			"GPU fan",
+#elif CONFIG(EC_SYSTEM76_EC_FAN2)
+			"fan1",
+			"fan2",
+#else
+			"CPU fan",
 #endif
 		})
 	}
diff --git a/src/mainboard/system76/mtl/Kconfig b/src/mainboard/system76/mtl/Kconfig
index 60eba4aaa6..81558aa34c 100644
--- a/src/mainboard/system76/mtl/Kconfig
+++ b/src/mainboard/system76/mtl/Kconfig
@@ -26,12 +26,14 @@ config BOARD_SYSTEM76_MTL_COMMON
 
 config BOARD_SYSTEM76_DARP10
 	select BOARD_SYSTEM76_MTL_COMMON
+	select EC_SYSTEM76_EC_FAN2
 	select MAINBOARD_USES_IFD_GBE_REGION
 	select SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES
 	select SOC_INTEL_METEORLAKE_U_H
 
 config BOARD_SYSTEM76_DARP10_B
 	select BOARD_SYSTEM76_MTL_COMMON
+	select EC_SYSTEM76_EC_FAN2
 	select MAINBOARD_USES_IFD_GBE_REGION
 	select SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES
 	select SOC_INTEL_METEORLAKE_U_H

From aa121a9bbef5e43cef64464d43a3ac8aba082fec Mon Sep 17 00:00:00 2001
From: Maximilian Brune <maximilian.brune@9elements.com>
Date: Mon, 12 May 2025 17:06:22 +0200
Subject: [PATCH 1017/3886] payloads/external/edk2/Makefile: Set OemId Pcd

Set the EDK2 PCD to COREv4 so that ACPI tables that are created by EDK2
always use the coreboot OEM ID instead of the default one ("INTEL").

The name is taken from: include/acpi/acpi.h (OEM_ID)

tested:
build and see that BGRT table contains COREv4 instead of INTEL as OEM
ID.

Change-Id: I5e3a7d0f133e5b790f59ea522a71647f72ffc79c
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87647
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 payloads/external/edk2/Makefile | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/payloads/external/edk2/Makefile b/payloads/external/edk2/Makefile
index 358c8c6125..d329b95b2a 100644
--- a/payloads/external/edk2/Makefile
+++ b/payloads/external/edk2/Makefile
@@ -173,6 +173,8 @@ BUILD_STR += --pcd gEfiMdeModulePkgTokenSpaceGuid.PcdSetupConOutRow=0
 BUILD_STR += --pcd gEfiMdeModulePkgTokenSpaceGuid.PcdSetupConOutColumn=0
 endif
 
+BUILD_STR += --pcd gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultOemId="COREv4"
+
 bootloader = $(word 8,$(subst /, ,$(BUILD_STR)))
 
 ifneq ($(CONFIG_EDK2_CUSTOM_BUILD_PARAMS),)

From 011baca89db4f641acf6265ad8ab671b084784ff Mon Sep 17 00:00:00 2001
From: Patrick Rudolph <patrick.rudolph@9elements.com>
Date: Wed, 7 May 2025 09:17:29 +0200
Subject: [PATCH 1018/3886] cpu/x86/smm/smm_module_loader: Install bigger page
 tables

In order to give SMM access to more than 4GiB on x86_64, update the
page table generation in the SMM loader.
Honor CONFIG_CPU_PT_ROM_MAP_GB and map the same amount of the address
space as done in other stages. This is required for SMM trying to access
the SPI BAR in high MMIO on AMD platforms.

TEST=Could access ROM3 BAR at 0xfd00000000 in SMM on AMD/birman+

Change-Id: Iae3dac8d39d3f5e55cc08aa96c8924f6364c5140
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87573
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
---
 src/cpu/x86/smm/smm_module_loader.c | 35 +++++++++++++++++++----------
 1 file changed, 23 insertions(+), 12 deletions(-)

diff --git a/src/cpu/x86/smm/smm_module_loader.c b/src/cpu/x86/smm/smm_module_loader.c
index ba92e1ff2f..dff2dde857 100644
--- a/src/cpu/x86/smm/smm_module_loader.c
+++ b/src/cpu/x86/smm/smm_module_loader.c
@@ -418,28 +418,39 @@ static int append_and_check_region(const struct region smram,
 #define _PS   (1ULL << 7)
 #define _GEN_DIR(a) (_PRES + _RW + _US + _A + (a))
 #define _GEN_PAGE(a) (_PRES + _RW + _US + _PS + _A +  _D + (a))
-#define PAGE_SIZE 8
+#define PTE_SIZE 8
 
 /* Return the PML4E */
 static uintptr_t install_page_table(const uintptr_t handler_base)
 {
 	const bool one_g_pages = !!(cpuid_edx(0x80000001) & (1 << 26));
-	/* 4 1G pages or 4 PDPE entries with 512 * 2M pages */
-	const size_t pages_needed = one_g_pages ? 4 : 2048 + 4;
-	const uintptr_t pages_base = ALIGN_DOWN(handler_base - pages_needed * PAGE_SIZE, 4096);
+
+	/*
+	 * CONFIG_CPU_PT_ROM_MAP_GB 1G pages or
+	 * CONFIG_CPU_PT_ROM_MAP_GB PDPE entries with 512 * 2M pages
+	 */
+	const size_t ptes_needed = CONFIG_CPU_PT_ROM_MAP_GB + (one_g_pages ? 0 :
+				   512 * CONFIG_CPU_PT_ROM_MAP_GB);
+	const uintptr_t pages_base = ALIGN_DOWN(handler_base - ptes_needed * PTE_SIZE, 4096);
 	const uintptr_t pml4e = ALIGN_DOWN(pages_base - 8, 4096);
+	uintptr_t pdpt;
 
 	if (one_g_pages) {
-		for (size_t i = 0; i < 4; i++)
-			write64p(pages_base + i * PAGE_SIZE, _GEN_PAGE(1ull * GiB * i));
-		write64p(pml4e, _GEN_DIR(pages_base));
+		for (size_t i = 0; i < CONFIG_CPU_PT_ROM_MAP_GB; i++)
+			write64p(pages_base + i * PTE_SIZE, _GEN_PAGE(1ull * GiB * i));
+		pdpt = pages_base;
 	} else {
-		for (size_t i = 0; i < 2048; i++)
-			write64p(pages_base + i * PAGE_SIZE, _GEN_PAGE(2ull * MiB * i));
-		write64p(pml4e, _GEN_DIR(pages_base + 2048 * PAGE_SIZE));
-		for (size_t i = 0; i < 4; i++)
-			write64p(pages_base + (2048 + i) * PAGE_SIZE, _GEN_DIR(pages_base + 4096 * i));
+		for (size_t i = 0; i < 512 * CONFIG_CPU_PT_ROM_MAP_GB; i++)
+			write64p(pages_base + i * PTE_SIZE, _GEN_PAGE(2ull * MiB * i));
+
+		pdpt = pages_base + 4096 * CONFIG_CPU_PT_ROM_MAP_GB;
+		for (size_t i = 0; i < CONFIG_CPU_PT_ROM_MAP_GB; i++)
+			write64p(pdpt + i * PTE_SIZE, _GEN_DIR(pages_base + 4096 * i));
 	}
+
+	for (size_t i = 0; i < DIV_ROUND_UP(CONFIG_CPU_PT_ROM_MAP_GB, 512); i++)
+		write64p(pml4e + i * PTE_SIZE, _GEN_DIR(pdpt + i * 4096));
+
 	return pml4e;
 }
 

From 9faf7ce4f45c685c673ac506ffab2b4501796c80 Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Sat, 10 May 2025 17:13:40 -0500
Subject: [PATCH 1019/3886] soc/intel/alderlake: Add CFR objects for existing
 options

Add a header with CFR objects for existing configuration options,
so that supported boards can make use of them without duplication.

Change-Id: Iec0b3b10b8cb78014ca1429be73ad2a6646f7de1
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87627
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
---
 src/soc/intel/alderlake/include/soc/cfr.h | 96 +++++++++++++++++++++++
 1 file changed, 96 insertions(+)
 create mode 100644 src/soc/intel/alderlake/include/soc/cfr.h

diff --git a/src/soc/intel/alderlake/include/soc/cfr.h b/src/soc/intel/alderlake/include/soc/cfr.h
new file mode 100644
index 0000000000..1e54d585f1
--- /dev/null
+++ b/src/soc/intel/alderlake/include/soc/cfr.h
@@ -0,0 +1,96 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+/*
+ * CFR enums and structs which are used to control SoC settings.
+ */
+
+#ifndef _ALDERLAKE_CFR_H_
+#define _ALDERLAKE_CFR_H_
+
+#include <drivers/option/cfr_frontend.h>
+#include <soc/soc_chip.h>
+
+/* FSP hyperthreading */
+static const struct sm_object hyper_threading = SM_DECLARE_ENUM({
+	.opt_name	= "hyper_threading",
+	.ui_name	= "Hyper-Threading",
+	.ui_helptext	= "Enable or disable Hyper-Threading",
+	.default_value	= CONFIG(FSP_HYPERTHREADING),
+	.values		= (const struct sm_enum_value[]) {
+				{ "Disabled",		0	},
+				{ "Enabled",		1	},
+				SM_ENUM_VALUE_END		},
+});
+
+/* IGD Aperture Size */
+static const struct sm_object igd_aperture = SM_DECLARE_ENUM({
+	.opt_name	= "igd_aperture_size",
+	.ui_name	= "IGD Aperture Size",
+	.ui_helptext	= "Select the Aperture Size",
+	.default_value	= IGD_AP_SZ_256MB,
+	.values		= (const struct sm_enum_value[]) {
+				{ " 128 MB",		IGD_AP_SZ_128MB		},
+				{ " 256 MB",		IGD_AP_SZ_256MB		},
+#if CONFIG(ALWAYS_ALLOW_ABOVE_4G_ALLOCATION)
+				{ " 512 MB (4G MMIO)",	IGD_AP_SZ_4G_512MB	},
+				{ "1024 MB (4G MMIO)",	IGD_AP_SZ_4G_1024MB	},
+				{ "2048 MB (4G MMIO)",	IGD_AP_SZ_4G_2048MB	},
+#else
+				{ " 512 MB",		IGD_AP_SZ_512MB		},
+#endif
+				SM_ENUM_VALUE_END				},
+});
+
+/* IGD DVMT pre-allocated memory */
+static const struct sm_object igd_dvmt = SM_DECLARE_ENUM({
+	.opt_name	= "igd_dvmt_prealloc",
+	.ui_name	= "IGD DVMT Size",
+	.ui_helptext	= "Size of memory preallocated for internal graphics",
+	.default_value	= IGD_SM_60MB,
+	.values		= (const struct sm_enum_value[]) {
+				{ " 32 MB",		IGD_SM_32MB	},
+				{ " 60 MB",		IGD_SM_60MB	},
+				{ " 64 MB",		IGD_SM_64MB	},
+				{ " 96 MB",		IGD_SM_96MB	},
+				{ "128 MB",		IGD_SM_128MB	},
+				{ "160 MB",		IGD_SM_160MB	},
+				SM_ENUM_VALUE_END			},
+});
+
+/* Legacy 8254 Timer */
+static const struct sm_object legacy_8254_timer = SM_DECLARE_ENUM({
+	.opt_name	= "legacy_8254_timer",
+	.ui_name	= "Legacy 8254 Timer",
+	.ui_helptext	= "Enable the legacy 8254 timer by disabling clock gating.",
+	.default_value	= 0,
+	.values		= (const struct sm_enum_value[]) {
+				{ "Disabled",		0	},
+				{ "Enabled",		1	},
+				SM_ENUM_VALUE_END		},
+});
+
+/* S0ix Enable */
+static const struct sm_object s0ix_enable = SM_DECLARE_ENUM({
+	.opt_name	= "s0ix_enable",
+	.ui_name	= "Modern Standby (S0ix)",
+	.ui_helptext	= "Enabled: use Modern Standby / S0ix. Disabled: use APCI S3 sleep",
+	.default_value	= 1,
+	.values		= (const struct sm_enum_value[]) {
+				{ "Disabled",		0	},
+				{ "Enabled",		1	},
+				SM_ENUM_VALUE_END		},
+});
+
+/* VT-d */
+static const struct sm_object vtd = SM_DECLARE_ENUM({
+	.opt_name	= "vtd",
+	.ui_name	= "VT-d",
+	.ui_helptext	= "Enable or disable Intel VT-d (virtualization)",
+	.default_value	= 1,
+	.values		= (const struct sm_enum_value[]) {
+				{ "Disabled",		0	},
+				{ "Enabled",		1	},
+				SM_ENUM_VALUE_END		},
+});
+
+#endif /* _ALDERLAKE_CFR_H_ */

From d930a3542c362c343a405284a02be7bd7a5f4d03 Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Sat, 10 May 2025 10:28:52 -0500
Subject: [PATCH 1020/3886] soc/intel/alderlake: Hook up IGD config to option
 API
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Hook up the IGD UPDs for configuring the DVMT allocated memory and
the aperture size to the option API, so they can be configured via
CMOS/CFR. Default values are set to existing values if option API
is not used.

Add an enum to map the aperture size UPD values to user-friendly ones,
as was already done for the DVMT size.

Change-Id: I03f100dff2d8a7f6bb87b9860c0be848e8aec61e
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87620
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/soc/intel/alderlake/chip.h                | 13 +++++++++++++
 src/soc/intel/alderlake/romstage/fsp_params.c |  3 ++-
 2 files changed, 15 insertions(+), 1 deletion(-)

diff --git a/src/soc/intel/alderlake/chip.h b/src/soc/intel/alderlake/chip.h
index 10f2d3cc0f..3473b0643a 100644
--- a/src/soc/intel/alderlake/chip.h
+++ b/src/soc/intel/alderlake/chip.h
@@ -483,6 +483,19 @@ struct soc_intel_alderlake_config {
 		IGD_SM_60MB = 0xFE,
 	} igd_dvmt50_pre_alloc;
 
+	enum {
+		IGD_AP_SZ_128MB = 0x00,
+		IGD_AP_SZ_256MB = 0x01,
+		IGD_AP_SZ_512MB = 0x02,
+		/*
+		 * Values below require use of above 4G MMIO,
+		 * otherwise FSP will hang
+		 */
+		IGD_AP_SZ_4G_512MB = 0x03,
+		IGD_AP_SZ_4G_1024MB = 0x07,
+		IGD_AP_SZ_4G_2048MB = 0x15,
+	} igd_aperture_size;
+
 	bool skip_ext_gfx_scan;
 	bool eist_enable;
 	bool enable_c6dram;
diff --git a/src/soc/intel/alderlake/romstage/fsp_params.c b/src/soc/intel/alderlake/romstage/fsp_params.c
index 427de4d7c3..8f6c57a3e4 100644
--- a/src/soc/intel/alderlake/romstage/fsp_params.c
+++ b/src/soc/intel/alderlake/romstage/fsp_params.c
@@ -134,7 +134,8 @@ static void fill_fspm_igd_params(FSP_M_CONFIG *m_cfg,
 	m_cfg->InternalGfx = !CONFIG(SOC_INTEL_DISABLE_IGD) && is_devfn_enabled(SA_DEVFN_IGD);
 	if (m_cfg->InternalGfx) {
 		/* IGD is enabled, set IGD stolen size to 60MB. */
-		m_cfg->IgdDvmt50PreAlloc = IGD_SM_60MB;
+		m_cfg->IgdDvmt50PreAlloc = get_uint_option("igd_dvmt_prealloc", IGD_SM_60MB);
+		m_cfg->ApertureSize = get_uint_option("igd_aperture_size", IGD_AP_SZ_256MB);
 		/* DP port config */
 		m_cfg->DdiPortAConfig = config->ddi_portA_config;
 		m_cfg->DdiPortBConfig = config->ddi_portB_config;

From dcbb5771c960295ddaeae5477a4564688feb7b8d Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Sat, 10 May 2025 16:36:13 -0500
Subject: [PATCH 1021/3886] soc/intel/tigerlake: Hook up IGD config to option
 API

Hook up the IGD UPDs for configuring the DVMT allocated memory and
the aperture size to the option API, so they can be configured via
CMOS/CFR. Default values are set to existing values if option API
is not used.

Add enums to map the DVMT and aperture size UPD values to user-
friendly ones, as was previously done for Alder Lake SoC.

Change-Id: I1c9596d12864bf60449c4e54797a8761e07e2ee4
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87621
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
---
 src/soc/intel/tigerlake/chip.h                | 36 +++++++++++++++++++
 src/soc/intel/tigerlake/romstage/fsp_params.c | 10 +++++-
 2 files changed, 45 insertions(+), 1 deletion(-)

diff --git a/src/soc/intel/tigerlake/chip.h b/src/soc/intel/tigerlake/chip.h
index 2c0a9b4073..6f9acb9a92 100644
--- a/src/soc/intel/tigerlake/chip.h
+++ b/src/soc/intel/tigerlake/chip.h
@@ -115,6 +115,42 @@ enum ddi_port_config {
 	DDI_PORT_CFG_MIPI_DSI	= 2,
 };
 
+enum igd_dvmt50_pre_alloc {
+	IGD_SM_0MB = 0x00,
+	IGD_SM_32MB = 0x01,
+	IGD_SM_64MB = 0x02,
+	IGD_SM_96MB = 0x03,
+	IGD_SM_128MB = 0x04,
+	IGD_SM_160MB = 0x05,
+	IGD_SM_4MB = 0xF0,
+	IGD_SM_8MB = 0xF1,
+	IGD_SM_12MB = 0xF2,
+	IGD_SM_16MB = 0xF3,
+	IGD_SM_20MB = 0xF4,
+	IGD_SM_24MB = 0xF5,
+	IGD_SM_28MB = 0xF6,
+	IGD_SM_36MB = 0xF8,
+	IGD_SM_40MB = 0xF9,
+	IGD_SM_44MB = 0xFA,
+	IGD_SM_48MB = 0xFB,
+	IGD_SM_52MB = 0xFC,
+	IGD_SM_56MB = 0xFD,
+	IGD_SM_60MB = 0xFE,
+};
+
+enum igd_aperture_size {
+	IGD_AP_SZ_128MB = 0x00,
+	IGD_AP_SZ_256MB = 0x01,
+	IGD_AP_SZ_512MB = 0x02,
+	/*
+	* Values below require use of above 4G MMIO,
+	* otherwise FSP will hang
+	*/
+	IGD_AP_SZ_4G_512MB = 0x03,
+	IGD_AP_SZ_4G_1024MB = 0x07,
+	IGD_AP_SZ_4G_2048MB = 0x15,
+};
+
 struct soc_intel_tigerlake_config {
 	/* Common struct containing soc config data required by common code */
 	struct soc_intel_common_config common_soc_config;
diff --git a/src/soc/intel/tigerlake/romstage/fsp_params.c b/src/soc/intel/tigerlake/romstage/fsp_params.c
index 5ebd46dd75..4f938f16d2 100644
--- a/src/soc/intel/tigerlake/romstage/fsp_params.c
+++ b/src/soc/intel/tigerlake/romstage/fsp_params.c
@@ -29,7 +29,15 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg,
 
 	m_cfg->InternalGfx = !CONFIG(SOC_INTEL_DISABLE_IGD) && is_devfn_enabled(SA_DEVFN_IGD);
 
-	/* If IGD is enabled, set IGD stolen size to 60MB. Otherwise, skip IGD init in FSP */
+	if (m_cfg->InternalGfx) {
+		/* IGD is enabled, set IGD stolen size to 60MB. */
+		m_cfg->IgdDvmt50PreAlloc = get_uint_option("igd_dvmt_prealloc", IGD_SM_60MB);
+		m_cfg->ApertureSize = get_uint_option("igd_aperture_size", IGD_AP_SZ_256MB);
+	} else {
+		/* IGD is disabled, skip IGD init in FSP. */
+		m_cfg->IgdDvmt50PreAlloc = 0;
+	}
+
 	m_cfg->IgdDvmt50PreAlloc = m_cfg->InternalGfx ? 0xFE : 0;
 
 	m_cfg->TsegSize = CONFIG_SMM_TSEG_SIZE;

From 09adda95b93864f909dc8b77cb45268aca84212b Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Sat, 10 May 2025 16:42:33 -0500
Subject: [PATCH 1022/3886] soc/intel/meteorlake: Hook up IGD config to option
 API
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Hook up the IGD UPD for configuring the DVMT allocated memory to the
option API, so it can be configured via CMOS/CFR. Default value is set
to the existing fixed value of 128MB if option API is not used.

Change-Id: I413e958e3c02632c3920b39dd370b89ecc99613f
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87622
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
---
 src/soc/intel/meteorlake/romstage/fsp_params.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/soc/intel/meteorlake/romstage/fsp_params.c b/src/soc/intel/meteorlake/romstage/fsp_params.c
index 8e49afa101..2001cdc79f 100644
--- a/src/soc/intel/meteorlake/romstage/fsp_params.c
+++ b/src/soc/intel/meteorlake/romstage/fsp_params.c
@@ -118,7 +118,7 @@ static void fill_fspm_igd_params(FSP_M_CONFIG *m_cfg,
 	m_cfg->InternalGfx = !CONFIG(SOC_INTEL_DISABLE_IGD) && is_devfn_enabled(PCI_DEVFN_IGD);
 	if (m_cfg->InternalGfx) {
 		/* IGD is enabled, set IGD stolen size to 128MB. */
-		m_cfg->IgdDvmt50PreAlloc = IGD_SM_128MB;
+		m_cfg->IgdDvmt50PreAlloc = get_uint_option("igd_dvmt_prealloc", IGD_SM_128MB);
 		/* DP port config */
 		m_cfg->DdiPortAConfig = config->ddi_port_A_config;
 		m_cfg->DdiPortBConfig = config->ddi_port_B_config;

From 947dd078232a6f0f58603926063cee3b085b46f9 Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Sat, 10 May 2025 16:49:28 -0500
Subject: [PATCH 1023/3886] soc/intel/jasperlake: Hook up IGD config to option
 API

Hook up the IGD UPDs for configuring the DVMT allocated memory and
the aperture size to the option API, so they can be configured via
CMOS/CFR. Default values are set to existing values if option API
is not used.

Add enums to map the DVMT and aperture size UPD values to user-
friendly ones, as was previously done for other SoCs.

Change-Id: Id85e698263b0193d0a83cd4d6ee6c10c89a1d2fa
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87623
Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/soc/intel/jasperlake/chip.h               | 30 +++++++++++++++++++
 .../intel/jasperlake/romstage/fsp_params.c    | 15 ++++++----
 2 files changed, 40 insertions(+), 5 deletions(-)

diff --git a/src/soc/intel/jasperlake/chip.h b/src/soc/intel/jasperlake/chip.h
index 408cdcfa46..380549451e 100644
--- a/src/soc/intel/jasperlake/chip.h
+++ b/src/soc/intel/jasperlake/chip.h
@@ -57,6 +57,36 @@ static const struct {
 	{ PCI_DID_INTEL_JSL_ID_6, JSL_N6005_10W_CORE, TDP_10W },
 };
 
+/* Gfx related */
+enum igd_dvmt50_pre_alloc {
+	IGD_SM_0MB = 0x00,
+	IGD_SM_32MB = 0x01,
+	IGD_SM_64MB = 0x02,
+	IGD_SM_96MB = 0x03,
+	IGD_SM_128MB = 0x04,
+	IGD_SM_160MB = 0x05,
+	IGD_SM_4MB = 0xF0,
+	IGD_SM_8MB = 0xF1,
+	IGD_SM_12MB = 0xF2,
+	IGD_SM_16MB = 0xF3,
+	IGD_SM_20MB = 0xF4,
+	IGD_SM_24MB = 0xF5,
+	IGD_SM_28MB = 0xF6,
+	IGD_SM_36MB = 0xF8,
+	IGD_SM_40MB = 0xF9,
+	IGD_SM_44MB = 0xFA,
+	IGD_SM_48MB = 0xFB,
+	IGD_SM_52MB = 0xFC,
+	IGD_SM_56MB = 0xFD,
+	IGD_SM_60MB = 0xFE,
+};
+
+enum igd_aperture_size {
+	IGD_AP_SZ_128MB = 0x00,
+	IGD_AP_SZ_256MB = 0x01,
+	IGD_AP_SZ_512MB = 0x02,
+};
+
 struct soc_intel_jasperlake_config {
 	/* Common struct containing soc config data required by common code */
 	struct soc_intel_common_config common_soc_config;
diff --git a/src/soc/intel/jasperlake/romstage/fsp_params.c b/src/soc/intel/jasperlake/romstage/fsp_params.c
index 5a06e12347..daa6754989 100644
--- a/src/soc/intel/jasperlake/romstage/fsp_params.c
+++ b/src/soc/intel/jasperlake/romstage/fsp_params.c
@@ -6,6 +6,7 @@
 #include <fsp/util.h>
 #include <intelblocks/cpulib.h>
 #include <intelblocks/pcie_rp.h>
+#include <option.h>
 #include <soc/iomap.h>
 #include <soc/pci_devs.h>
 #include <soc/pcie.h>
@@ -18,12 +19,16 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg,
 {
 	unsigned int i;
 
-	/*
-	 * If IGD is enabled, set IGD stolen size to 60MB.
-	 * Otherwise, skip IGD init in FSP.
-	 */
 	m_cfg->InternalGfx = !CONFIG(SOC_INTEL_DISABLE_IGD) && is_devfn_enabled(SA_DEVFN_IGD);
-	m_cfg->IgdDvmt50PreAlloc = m_cfg->InternalGfx ? 0xFE : 0;
+
+	if (m_cfg->InternalGfx) {
+		/* IGD is enabled, set IGD stolen size to 60MB. */
+		m_cfg->IgdDvmt50PreAlloc = get_uint_option("igd_dvmt_prealloc", IGD_SM_60MB);
+		m_cfg->ApertureSize = get_uint_option("igd_aperture_size", IGD_AP_SZ_256MB);
+	} else {
+		/* IGD is disabled, skip IGD init in FSP. */
+		m_cfg->IgdDvmt50PreAlloc = 0;
+	}
 
 	m_cfg->TsegSize = CONFIG_SMM_TSEG_SIZE;
 	m_cfg->SaGv = config->SaGv;

From c8199f26e0db8276f1898791422605265709625e Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Sat, 10 May 2025 16:57:25 -0500
Subject: [PATCH 1024/3886] soc/intel/skylake: Add/use enums for IGD config

Add enums for the IGD aperture size and DVMT/stolen memory size, as is
done for newer SoCs. Use these enums rather than their int values
when configuring the IGD.

Change-Id: I16dbfcd1862ea0c43c62eef59e35ca144a1b2715
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87624
Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/soc/intel/skylake/chip.h                | 15 +++++++++++++++
 src/soc/intel/skylake/include/soc/cfr.h     | 19 ++++++++++---------
 src/soc/intel/skylake/romstage/fsp_params.c | 10 ++++++++--
 3 files changed, 33 insertions(+), 11 deletions(-)

diff --git a/src/soc/intel/skylake/chip.h b/src/soc/intel/skylake/chip.h
index d12c3eb218..8edb08eb35 100644
--- a/src/soc/intel/skylake/chip.h
+++ b/src/soc/intel/skylake/chip.h
@@ -30,6 +30,21 @@ enum skylake_i2c_voltage {
 	I2C_VOLTAGE_1V8
 };
 
+/* Gfx related */
+enum igd_dvmt50_pre_alloc {
+	IGD_SM_0MB = 0x00,
+	IGD_SM_32MB = 0x01,
+	IGD_SM_64MB = 0x02,
+	IGD_SM_96MB = 0x03,
+	IGD_SM_128MB = 0x04,
+};
+
+enum igd_aperture_size {
+	IGD_AP_SZ_128MB = 0x00,
+	IGD_AP_SZ_256MB = 0x01,
+	IGD_AP_SZ_512MB = 0x02,
+};
+
 struct soc_intel_skylake_config {
 	/* Common struct containing soc config data required by common code */
 	struct soc_intel_common_config common_soc_config;
diff --git a/src/soc/intel/skylake/include/soc/cfr.h b/src/soc/intel/skylake/include/soc/cfr.h
index ad5c6f6f53..52899015d3 100644
--- a/src/soc/intel/skylake/include/soc/cfr.h
+++ b/src/soc/intel/skylake/include/soc/cfr.h
@@ -8,6 +8,7 @@
 #define SKYLAKE_CFR_H
 
 #include <drivers/option/cfr_frontend.h>
+#include <soc/soc_chip.h>
 
 /* FSP hyperthreading */
 static const struct sm_object hyper_threading = SM_DECLARE_ENUM({
@@ -26,11 +27,11 @@ static const struct sm_object igd_aperture = SM_DECLARE_ENUM({
 	.opt_name	= "igd_aperture_size",
 	.ui_name	= "IGD Aperture Size",
 	.ui_helptext	= "Select the Aperture Size",
-	.default_value	= 1,
+	.default_value	= IGD_AP_SZ_256MB,
 	.values		= (const struct sm_enum_value[]) {
-				{ "128 MB",		0	},
-				{ "256 MB",		1	},
-				{ "512 MB",		2	},
+				{ "128 MB",	IGD_AP_SZ_128MB	},
+				{ "256 MB",	IGD_AP_SZ_256MB	},
+				{ "512 MB",	IGD_AP_SZ_512MB	},
 				SM_ENUM_VALUE_END		},
 });
 
@@ -39,12 +40,12 @@ static const struct sm_object igd_dvmt = SM_DECLARE_ENUM({
 	.opt_name	= "igd_dvmt_prealloc",
 	.ui_name	= "IGD DVMT Size",
 	.ui_helptext	= "Size of memory preallocated for internal graphics",
-	.default_value	= 2,
+	.default_value	= IGD_SM_64MB,
 	.values		= (const struct sm_enum_value[]) {
-				{ "32 MB",		1	},
-				{ "64 MB",		2	},
-				{ "96 MB",		3	},
-				{ "128 MB",		4	},
+				{ "32 MB",	IGD_SM_32MB	},
+				{ "64 MB",	IGD_SM_64MB	},
+				{ "96 MB",	IGD_SM_96MB	},
+				{ "128 MB",	IGD_SM_128MB	},
 				SM_ENUM_VALUE_END		},
 });
 
diff --git a/src/soc/intel/skylake/romstage/fsp_params.c b/src/soc/intel/skylake/romstage/fsp_params.c
index 906301dd1f..02123f837a 100644
--- a/src/soc/intel/skylake/romstage/fsp_params.c
+++ b/src/soc/intel/skylake/romstage/fsp_params.c
@@ -116,8 +116,14 @@ static void soc_primary_gfx_config_params(FSP_M_CONFIG *m_cfg,
 	 *
 	 * If disabled, don't reserve memory for it.
 	 */
-	m_cfg->IgdDvmt50PreAlloc = m_cfg->InternalGfx ? get_uint_option("igd_dvmt_prealloc", 2) : 0;
-	m_cfg->ApertureSize = get_uint_option("igd_aperture_size", 1);
+	if (m_cfg->InternalGfx) {
+		/* IGD is enabled, set IGD stolen size to 64MB. */
+		m_cfg->IgdDvmt50PreAlloc = get_uint_option("igd_dvmt_prealloc", IGD_SM_64MB);
+		m_cfg->ApertureSize = get_uint_option("igd_aperture_size", IGD_AP_SZ_256MB);
+	} else {
+		/* IGD is disabled, skip IGD init in FSP. */
+		m_cfg->IgdDvmt50PreAlloc = 0;
+	}
 
 	m_cfg->PrimaryDisplay = config->PrimaryDisplay;
 }

From 6f9df7ace43f056a399e8d20cc50548b27dd9bec Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Sat, 10 May 2025 17:04:40 -0500
Subject: [PATCH 1025/3886] soc/intel/cannonlake: Add/use enums for IGD config
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Add enums for the IGD aperture size and DVMT/stolen memory size, as is
done for newer SoCs. Use these enums rather than their int values
when configuring the IGD.

Change-Id: I369f9c73a00b41b056c89975d4c7e643f1e900c1
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87625
Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
---
 src/soc/intel/cannonlake/chip.h               | 15 +++++++++++++++
 src/soc/intel/cannonlake/include/soc/cfr.h    | 19 ++++++++++---------
 .../intel/cannonlake/romstage/fsp_params.c    |  5 +++--
 3 files changed, 28 insertions(+), 11 deletions(-)

diff --git a/src/soc/intel/cannonlake/chip.h b/src/soc/intel/cannonlake/chip.h
index 591abbeaae..f4785bb365 100644
--- a/src/soc/intel/cannonlake/chip.h
+++ b/src/soc/intel/cannonlake/chip.h
@@ -36,6 +36,21 @@ enum chip_pl2_4_cfg {
 	value_not_set /* vr_config internal use only */
 };
 
+/* Gfx related */
+enum igd_dvmt50_pre_alloc {
+	IGD_SM_0MB = 0x00,
+	IGD_SM_32MB = 0x01,
+	IGD_SM_64MB = 0x02,
+	IGD_SM_96MB = 0x03,
+	IGD_SM_128MB = 0x04,
+};
+
+enum igd_aperture_size {
+	IGD_AP_SZ_128MB = 0x00,
+	IGD_AP_SZ_256MB = 0x01,
+	IGD_AP_SZ_512MB = 0x02,
+};
+
 struct soc_intel_cannonlake_config {
 	/* Common struct containing soc config data required by common code */
 	struct soc_intel_common_config common_soc_config;
diff --git a/src/soc/intel/cannonlake/include/soc/cfr.h b/src/soc/intel/cannonlake/include/soc/cfr.h
index ae61799a68..1526256703 100644
--- a/src/soc/intel/cannonlake/include/soc/cfr.h
+++ b/src/soc/intel/cannonlake/include/soc/cfr.h
@@ -8,6 +8,7 @@
 #define CANNONLAKE_CFR_H
 
 #include <drivers/option/cfr_frontend.h>
+#include <soc/soc_chip.h>
 
 /* FSP hyperthreading */
 static const struct sm_object hyper_threading = SM_DECLARE_ENUM({
@@ -26,11 +27,11 @@ static const struct sm_object igd_aperture = SM_DECLARE_ENUM({
 	.opt_name	= "igd_aperture_size",
 	.ui_name	= "IGD Aperture Size",
 	.ui_helptext	= "Select the Aperture Size",
-	.default_value	= 1,
+	.default_value	= IGD_AP_SZ_256MB,
 	.values		= (const struct sm_enum_value[]) {
-				{ "128 MB",		0	},
-				{ "256 MB",		1	},
-				{ "512 MB",		2	},
+				{ "128 MB",	IGD_AP_SZ_128MB	},
+				{ "256 MB",	IGD_AP_SZ_256MB	},
+				{ "512 MB",	IGD_AP_SZ_512MB	},
 				SM_ENUM_VALUE_END		},
 });
 
@@ -39,12 +40,12 @@ static const struct sm_object igd_dvmt = SM_DECLARE_ENUM({
 	.opt_name	= "igd_dvmt_prealloc",
 	.ui_name	= "IGD DVMT Size",
 	.ui_helptext	= "Size of memory preallocated for internal graphics",
-	.default_value	= 2,
+	.default_value	= IGD_SM_64MB,
 	.values		= (const struct sm_enum_value[]) {
-				{ "32 MB",		1	},
-				{ "64 MB",		2	},
-				{ "96 MB",		3	},
-				{ "128 MB",		4	},
+				{ "32 MB",	IGD_SM_32MB	},
+				{ "64 MB",	IGD_SM_64MB	},
+				{ "96 MB",	IGD_SM_96MB	},
+				{ "128 MB",	IGD_SM_128MB	},
 				SM_ENUM_VALUE_END		},
 });
 
diff --git a/src/soc/intel/cannonlake/romstage/fsp_params.c b/src/soc/intel/cannonlake/romstage/fsp_params.c
index 74812f31bf..a8523f14ab 100644
--- a/src/soc/intel/cannonlake/romstage/fsp_params.c
+++ b/src/soc/intel/cannonlake/romstage/fsp_params.c
@@ -14,6 +14,7 @@
 #include <soc/pci_devs.h>
 #include <soc/pcie.h>
 #include <soc/romstage.h>
+#include <soc/soc_chip.h>
 #include <types.h>
 
 #include "../chip.h"
@@ -37,8 +38,8 @@ void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version)
 	if (igd_on && pci_read_config16(SA_DEV_IGD, PCI_VENDOR_ID) != 0xffff) {
 		/* Set IGD stolen size to 64MB. */
 		m_cfg->InternalGfx = 1;
-		m_cfg->IgdDvmt50PreAlloc = get_uint_option("igd_dvmt_prealloc", 2);
-		m_cfg->ApertureSize = get_uint_option("igd_aperture_size", 1);
+		m_cfg->IgdDvmt50PreAlloc = get_uint_option("igd_dvmt_prealloc", IGD_SM_64MB);
+		m_cfg->ApertureSize = get_uint_option("igd_aperture_size", IGD_AP_SZ_256MB);
 	} else {
 		m_cfg->InternalGfx = 0;
 		m_cfg->IgdDvmt50PreAlloc = 0;

From 3cfb24a326915aa7ee9f77e9190a6ed923068058 Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Sat, 10 May 2025 17:12:37 -0500
Subject: [PATCH 1026/3886] soc/intel/alderlake: Hook up the VT-d setting to
 option API
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Hook up the VT-d setting to the option API, so it can be changed at
runtime without recompilation.

Change-Id: I728b71826798eb94c13e54aeadd3ca69c2bf5e8f
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87626
Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/soc/intel/alderlake/romstage/fsp_params.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/soc/intel/alderlake/romstage/fsp_params.c b/src/soc/intel/alderlake/romstage/fsp_params.c
index 8f6c57a3e4..6ab8bb3e50 100644
--- a/src/soc/intel/alderlake/romstage/fsp_params.c
+++ b/src/soc/intel/alderlake/romstage/fsp_params.c
@@ -316,7 +316,7 @@ static void fill_fspm_vtd_params(FSP_M_CONFIG *m_cfg,
 	m_cfg->VtdBaseAddress[VTD_IPU] = IPUVT_BASE_ADDRESS;
 	m_cfg->VtdBaseAddress[VTD_VTVCO] = VTVC0_BASE_ADDRESS;
 
-	m_cfg->VtdDisable = 0;
+	m_cfg->VtdDisable = !get_uint_option("vtd", 1);
 	m_cfg->VtdIopEnable = !m_cfg->VtdDisable;
 	m_cfg->VtdIgdEnable = m_cfg->InternalGfx;
 	m_cfg->VtdIpuEnable = m_cfg->SaIpuEnable;

From d06c8dde58ced7cb3fd2a1933c8954a2c7965037 Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Sat, 10 May 2025 17:17:21 -0500
Subject: [PATCH 1027/3886] soc/intel/tigerlake: Hook up the VT-d setting to
 option API
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Hook up the VT-d setting to the option API, so it can be changed at
runtime without recompilation.

Change-Id: Ifa0b567c05e48c4f0f5dc2fc385cf5f82eb083a0
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87628
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
---
 src/soc/intel/tigerlake/romstage/fsp_params.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/soc/intel/tigerlake/romstage/fsp_params.c b/src/soc/intel/tigerlake/romstage/fsp_params.c
index 4f938f16d2..82c4c64ff9 100644
--- a/src/soc/intel/tigerlake/romstage/fsp_params.c
+++ b/src/soc/intel/tigerlake/romstage/fsp_params.c
@@ -164,7 +164,7 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg,
 		m_cfg->VtdDisable = 1;
 	} else {
 		/* Enable VT-d support for QS platform */
-		m_cfg->VtdDisable = 0;
+		m_cfg->VtdDisable = !get_uint_option("vtd", 1);
 		m_cfg->VtdIopEnable = 0x1;
 
 		if (m_cfg->InternalGfx) {

From 2c0c2f46d7b411ce31a4f3d5078204fbb71bed03 Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Sat, 10 May 2025 17:18:46 -0500
Subject: [PATCH 1028/3886] soc/intel/tigerlake: Add CFR objects for existing
 options

Add a header with CFR objects for existing configuration options,
so that supported boards can make use of them without duplication.

Change-Id: I08d7c39ba9be92d6a267d20068f41980a5042755
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87629
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
---
 src/soc/intel/tigerlake/include/soc/cfr.h | 96 +++++++++++++++++++++++
 1 file changed, 96 insertions(+)
 create mode 100644 src/soc/intel/tigerlake/include/soc/cfr.h

diff --git a/src/soc/intel/tigerlake/include/soc/cfr.h b/src/soc/intel/tigerlake/include/soc/cfr.h
new file mode 100644
index 0000000000..529a4eba79
--- /dev/null
+++ b/src/soc/intel/tigerlake/include/soc/cfr.h
@@ -0,0 +1,96 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+/*
+ * CFR enums and structs which are used to control SoC settings.
+ */
+
+#ifndef _TIGERLAKE_CFR_H_
+#define _TIGERLAKE_CFR_H_
+
+#include <drivers/option/cfr_frontend.h>
+#include <soc/soc_chip.h>
+
+/* FSP hyperthreading */
+static const struct sm_object hyper_threading = SM_DECLARE_ENUM({
+	.opt_name	= "hyper_threading",
+	.ui_name	= "Hyper-Threading",
+	.ui_helptext	= "Enable or disable Hyper-Threading",
+	.default_value	= CONFIG(FSP_HYPERTHREADING),
+	.values		= (const struct sm_enum_value[]) {
+				{ "Disabled",		0	},
+				{ "Enabled",		1	},
+				SM_ENUM_VALUE_END		},
+});
+
+/* IGD Aperture Size */
+static const struct sm_object igd_aperture = SM_DECLARE_ENUM({
+	.opt_name	= "igd_aperture_size",
+	.ui_name	= "IGD Aperture Size",
+	.ui_helptext	= "Select the Aperture Size",
+	.default_value	= IGD_AP_SZ_256MB,
+	.values		= (const struct sm_enum_value[]) {
+				{ " 128 MB",		IGD_AP_SZ_128MB		},
+				{ " 256 MB",		IGD_AP_SZ_256MB		},
+#if CONFIG(ALWAYS_ALLOW_ABOVE_4G_ALLOCATION)
+				{ " 512 MB (4G MMIO)",	IGD_AP_SZ_4G_512MB	},
+				{ "1024 MB (4G MMIO)",	IGD_AP_SZ_4G_1024MB	},
+				{ "2048 MB (4G MMIO)",	IGD_AP_SZ_4G_2048MB	},
+#else
+				{ " 512 MB",		IGD_AP_SZ_512MB		},
+#endif
+				SM_ENUM_VALUE_END				},
+});
+
+/* IGD DVMT pre-allocated memory */
+static const struct sm_object igd_dvmt = SM_DECLARE_ENUM({
+	.opt_name	= "igd_dvmt_prealloc",
+	.ui_name	= "IGD DVMT Size",
+	.ui_helptext	= "Size of memory preallocated for internal graphics",
+	.default_value	= IGD_SM_60MB,
+	.values		= (const struct sm_enum_value[]) {
+				{ " 32 MB",		IGD_SM_32MB	},
+				{ " 60 MB",		IGD_SM_60MB	},
+				{ " 64 MB",		IGD_SM_64MB	},
+				{ " 96 MB",		IGD_SM_96MB	},
+				{ "128 MB",		IGD_SM_128MB	},
+				{ "160 MB",		IGD_SM_160MB	},
+				SM_ENUM_VALUE_END			},
+});
+
+/* Legacy 8254 Timer */
+static const struct sm_object legacy_8254_timer = SM_DECLARE_ENUM({
+	.opt_name	= "legacy_8254_timer",
+	.ui_name	= "Legacy 8254 Timer",
+	.ui_helptext	= "Enable the legacy 8254 timer by disabling clock gating.",
+	.default_value	= 0,
+	.values		= (const struct sm_enum_value[]) {
+				{ "Disabled",		0	},
+				{ "Enabled",		1	},
+				SM_ENUM_VALUE_END		},
+});
+
+/* S0ix Enable */
+static const struct sm_object s0ix_enable = SM_DECLARE_ENUM({
+	.opt_name	= "s0ix_enable",
+	.ui_name	= "Modern Standby (S0ix)",
+	.ui_helptext	= "Enabled: use Modern Standby / S0ix. Disabled: use APCI S3 sleep",
+	.default_value	= 1,
+	.values		= (const struct sm_enum_value[]) {
+				{ "Disabled",		0	},
+				{ "Enabled",		1	},
+				SM_ENUM_VALUE_END		},
+});
+
+/* VT-d */
+static const struct sm_object vtd = SM_DECLARE_ENUM({
+	.opt_name	= "vtd",
+	.ui_name	= "VT-d",
+	.ui_helptext	= "Enable or disable Intel VT-d (virtualization)",
+	.default_value	= 1,
+	.values		= (const struct sm_enum_value[]) {
+				{ "Disabled",		0	},
+				{ "Enabled",		1	},
+				SM_ENUM_VALUE_END		},
+});
+
+#endif /* _TIGERLAKE_CFR_H_ */

From 87663d1c0aa6aa3d4206ee7dfd79c07bbbec36f3 Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Sat, 10 May 2025 17:20:40 -0500
Subject: [PATCH 1029/3886] soc/intel/jasperlake: Hook up the VT-d setting to
 option API

Hook up the VT-d setting to the option API, so it can be changed at
runtime without recompilation.

Change-Id: Ib964e4c2779fe467086681f55136237a69a8f736
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87630
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
---
 src/soc/intel/jasperlake/romstage/fsp_params.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/soc/intel/jasperlake/romstage/fsp_params.c b/src/soc/intel/jasperlake/romstage/fsp_params.c
index daa6754989..b39bd778ba 100644
--- a/src/soc/intel/jasperlake/romstage/fsp_params.c
+++ b/src/soc/intel/jasperlake/romstage/fsp_params.c
@@ -105,7 +105,7 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg,
 	m_cfg->PlatformDebugConsent = CONFIG_SOC_INTEL_COMMON_DEBUG_CONSENT;
 
 	/* VT-d config */
-	m_cfg->VtdDisable = 0;
+	m_cfg->VtdDisable = !get_uint_option("vtd", 1);
 	m_cfg->VtdIopEnable = 0x1;
 
 	if (m_cfg->InternalGfx) {

From e356483eb6261dece8ecd9798be22cc598beb35a Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Sat, 10 May 2025 17:28:29 -0500
Subject: [PATCH 1030/3886] soc/intel/jasperlake: Add CFR objects for existing
 options

Add a header with CFR objects for existing configuration options,
so that supported boards can make use of them without duplication.

Change-Id: I083cd4dfc5d4ee7807345c423872d27b66c4edc1
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87631
Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/soc/intel/jasperlake/include/soc/cfr.h | 78 ++++++++++++++++++++++
 1 file changed, 78 insertions(+)
 create mode 100644 src/soc/intel/jasperlake/include/soc/cfr.h

diff --git a/src/soc/intel/jasperlake/include/soc/cfr.h b/src/soc/intel/jasperlake/include/soc/cfr.h
new file mode 100644
index 0000000000..9aca7bb0d0
--- /dev/null
+++ b/src/soc/intel/jasperlake/include/soc/cfr.h
@@ -0,0 +1,78 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+/*
+ * CFR enums and structs which are used to control SoC settings.
+ */
+
+#ifndef _JASPERLAKE_CFR_H_
+#define _JASPERLAKE_CFR_H_
+
+#include <drivers/option/cfr_frontend.h>
+#include <soc/soc_chip.h>
+
+/* IGD Aperture Size */
+static const struct sm_object igd_aperture = SM_DECLARE_ENUM({
+	.opt_name	= "igd_aperture_size",
+	.ui_name	= "IGD Aperture Size",
+	.ui_helptext	= "Select the Aperture Size",
+	.default_value	= IGD_AP_SZ_256MB,
+	.values		= (const struct sm_enum_value[]) {
+				{ " 128 MB",		IGD_AP_SZ_128MB		},
+				{ " 256 MB",		IGD_AP_SZ_256MB		},
+				{ " 512 MB",		IGD_AP_SZ_512MB		},
+				SM_ENUM_VALUE_END				},
+});
+
+/* IGD DVMT pre-allocated memory */
+static const struct sm_object igd_dvmt = SM_DECLARE_ENUM({
+	.opt_name	= "igd_dvmt_prealloc",
+	.ui_name	= "IGD DVMT Size",
+	.ui_helptext	= "Size of memory preallocated for internal graphics",
+	.default_value	= IGD_SM_60MB,
+	.values		= (const struct sm_enum_value[]) {
+				{ " 32 MB",		IGD_SM_32MB	},
+				{ " 60 MB",		IGD_SM_60MB	},
+				{ " 64 MB",		IGD_SM_64MB	},
+				{ " 96 MB",		IGD_SM_96MB	},
+				{ "128 MB",		IGD_SM_128MB	},
+				{ "160 MB",		IGD_SM_160MB	},
+				SM_ENUM_VALUE_END			},
+});
+
+/* Legacy 8254 Timer */
+static const struct sm_object legacy_8254_timer = SM_DECLARE_ENUM({
+	.opt_name	= "legacy_8254_timer",
+	.ui_name	= "Legacy 8254 Timer",
+	.ui_helptext	= "Enable the legacy 8254 timer by disabling clock gating.",
+	.default_value	= 0,
+	.values		= (const struct sm_enum_value[]) {
+				{ "Disabled",		0	},
+				{ "Enabled",		1	},
+				SM_ENUM_VALUE_END		},
+});
+
+/* S0ix Enable */
+static const struct sm_object s0ix_enable = SM_DECLARE_ENUM({
+	.opt_name	= "s0ix_enable",
+	.ui_name	= "Modern Standby (S0ix)",
+	.ui_helptext	= "Enabled: use Modern Standby / S0ix. Disabled: use APCI S3 sleep",
+	.default_value	= 1,
+	.values		= (const struct sm_enum_value[]) {
+				{ "Disabled",		0	},
+				{ "Enabled",		1	},
+				SM_ENUM_VALUE_END		},
+});
+
+/* VT-d */
+static const struct sm_object vtd = SM_DECLARE_ENUM({
+	.opt_name	= "vtd",
+	.ui_name	= "VT-d",
+	.ui_helptext	= "Enable or disable Intel VT-d (virtualization)",
+	.default_value	= 1,
+	.values		= (const struct sm_enum_value[]) {
+				{ "Disabled",		0	},
+				{ "Enabled",		1	},
+				SM_ENUM_VALUE_END		},
+});
+
+#endif /* _JASPERLAKE_CFR_H_ */

From d53f00fbd9c9b0a86007d8df24004561815135b2 Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Sat, 10 May 2025 17:31:04 -0500
Subject: [PATCH 1031/3886] soc/intel/meteorlake: Hook up the VT-d setting to
 option API

Hook up the VT-d setting to the option API, so it can be changed at
runtime without recompilation.

Change-Id: I2d02184c82ef4874518a3f8e1fe0f5a195188f2a
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87632
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
---
 src/soc/intel/meteorlake/romstage/fsp_params.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/soc/intel/meteorlake/romstage/fsp_params.c b/src/soc/intel/meteorlake/romstage/fsp_params.c
index 2001cdc79f..190cb73085 100644
--- a/src/soc/intel/meteorlake/romstage/fsp_params.c
+++ b/src/soc/intel/meteorlake/romstage/fsp_params.c
@@ -354,7 +354,7 @@ static void fill_fspm_usb4_params(FSP_M_CONFIG *m_cfg,
 static void fill_fspm_vtd_params(FSP_M_CONFIG *m_cfg,
 		const struct soc_intel_meteorlake_config *config)
 {
-	m_cfg->VtdDisable = 0;
+	m_cfg->VtdDisable = !get_uint_option("vtd", 1);
 	m_cfg->VtdBaseAddress[0] = GFXVT_BASE_ADDRESS;
 	m_cfg->VtdBaseAddress[1] = VTVC0_BASE_ADDRESS;
 

From 50a5fe77de7446642fc1875381ef380ff6896ff5 Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Sat, 10 May 2025 17:32:43 -0500
Subject: [PATCH 1032/3886] soc/intel/meteorlake: Add CFR objects for existing
 options

Add a header with CFR objects for existing configuration options,
so that supported boards can make use of them without duplication.

Change-Id: I572f119c86ea0e2a16d4bb543bc61afab423d092
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87633
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
---
 src/soc/intel/meteorlake/include/soc/cfr.h | 76 ++++++++++++++++++++++
 1 file changed, 76 insertions(+)
 create mode 100644 src/soc/intel/meteorlake/include/soc/cfr.h

diff --git a/src/soc/intel/meteorlake/include/soc/cfr.h b/src/soc/intel/meteorlake/include/soc/cfr.h
new file mode 100644
index 0000000000..c8db514c99
--- /dev/null
+++ b/src/soc/intel/meteorlake/include/soc/cfr.h
@@ -0,0 +1,76 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+/*
+ * CFR enums and structs which are used to control SoC settings.
+ */
+
+#ifndef _METEORLAKE_CFR_H_
+#define _METEORLAKE_CFR_H_
+
+#include <drivers/option/cfr_frontend.h>
+#include <soc/soc_chip.h>
+
+/* FSP hyperthreading */
+static const struct sm_object hyper_threading = SM_DECLARE_ENUM({
+	.opt_name	= "hyper_threading",
+	.ui_name	= "Hyper-Threading",
+	.ui_helptext	= "Enable or disable Hyper-Threading",
+	.default_value	= CONFIG(FSP_HYPERTHREADING),
+	.values		= (const struct sm_enum_value[]) {
+				{ "Disabled",		0	},
+				{ "Enabled",		1	},
+				SM_ENUM_VALUE_END		},
+});
+
+/* IGD DVMT pre-allocated memory */
+static const struct sm_object igd_dvmt = SM_DECLARE_ENUM({
+	.opt_name	= "igd_dvmt_prealloc",
+	.ui_name	= "IGD DVMT Size",
+	.ui_helptext	= "Size of memory preallocated for internal graphics",
+	.default_value	= IGD_SM_128MB,
+	.values		= (const struct sm_enum_value[]) {
+				{ " 32 MB",		IGD_SM_32MB	},
+				{ " 64 MB",		IGD_SM_64MB	},
+				{ " 96 MB",		IGD_SM_96MB	},
+				{ "128 MB",		IGD_SM_128MB	},
+				{ "160 MB",		IGD_SM_160MB	},
+				SM_ENUM_VALUE_END			},
+});
+
+/* Legacy 8254 Timer */
+static const struct sm_object legacy_8254_timer = SM_DECLARE_ENUM({
+	.opt_name	= "legacy_8254_timer",
+	.ui_name	= "Legacy 8254 Timer",
+	.ui_helptext	= "Enable the legacy 8254 timer by disabling clock gating.",
+	.default_value	= 0,
+	.values		= (const struct sm_enum_value[]) {
+				{ "Disabled",		0	},
+				{ "Enabled",		1	},
+				SM_ENUM_VALUE_END		},
+});
+
+/* S0ix Enable */
+static const struct sm_object s0ix_enable = SM_DECLARE_ENUM({
+	.opt_name	= "s0ix_enable",
+	.ui_name	= "Modern Standby (S0ix)",
+	.ui_helptext	= "Enabled: use Modern Standby / S0ix. Disabled: use APCI S3 sleep",
+	.default_value	= 1,
+	.values		= (const struct sm_enum_value[]) {
+				{ "Disabled",		0	},
+				{ "Enabled",		1	},
+				SM_ENUM_VALUE_END		},
+});
+
+/* VT-d */
+static const struct sm_object vtd = SM_DECLARE_ENUM({
+	.opt_name	= "vtd",
+	.ui_name	= "VT-d",
+	.ui_helptext	= "Enable or disable Intel VT-d (virtualization)",
+	.default_value	= 1,
+	.values		= (const struct sm_enum_value[]) {
+				{ "Disabled",		0	},
+				{ "Enabled",		1	},
+				SM_ENUM_VALUE_END		},
+});
+
+#endif /* _METEORLAKE_CFR_H_ */

From b59fef9678762df1b5a6a432623b26d0ee186398 Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Fri, 2 May 2025 13:12:13 -0500
Subject: [PATCH 1033/3886] soc/intel/cmn/cse: Add Kconfig to set ME default
 CFR option state

When using the CFR option backend, a mainboard may want to set the ME
default state to disabled, so add a Kconfig which can be selected to do
so.

Change-Id: I53d88af5e5cc9b7300b847e4aaf8e4cd2ce5bb75
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87649
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/soc/intel/common/block/cse/Kconfig               | 8 ++++++++
 src/soc/intel/common/block/include/intelblocks/cfr.h | 2 +-
 2 files changed, 9 insertions(+), 1 deletion(-)

diff --git a/src/soc/intel/common/block/cse/Kconfig b/src/soc/intel/common/block/cse/Kconfig
index d1548a1fcb..ce998e4b56 100644
--- a/src/soc/intel/common/block/cse/Kconfig
+++ b/src/soc/intel/common/block/cse/Kconfig
@@ -463,3 +463,11 @@ config CSE_RESET_CLEAR_EC_AP_IDLE_FLAG
 	  Select this if the variant is a Chromebox/base. This allows AP to direct EC
 	  to clear AP_IDLE flag before triggering reset to make sure AP can boot up
 	  after reset.
+
+config CSE_DEFAULT_CFR_OPTION_STATE_DISABLED
+	bool
+	default n
+	help
+	  Mainboards can select this if using the CFR option backend to configure
+	  the ME operational state and want the default state to be disabled.
+	  If not selected, the default state will be enabled.
diff --git a/src/soc/intel/common/block/include/intelblocks/cfr.h b/src/soc/intel/common/block/include/intelblocks/cfr.h
index c240b769f3..fe9af039a6 100644
--- a/src/soc/intel/common/block/include/intelblocks/cfr.h
+++ b/src/soc/intel/common/block/include/intelblocks/cfr.h
@@ -16,7 +16,7 @@ static const struct sm_object me_state = SM_DECLARE_ENUM({
 	.opt_name	= "me_state",
 	.ui_name	= "Intel Management Engine",
 	.ui_helptext	= "Enable or disable the Intel Management Engine",
-	.default_value	= 0,
+	.default_value	= CONFIG(CSE_DEFAULT_CFR_OPTION_STATE_DISABLED),
 	.values		= (const struct sm_enum_value[]) {
 				{ "Disabled",		1		},
 				{ "Enabled",		0		},

From d93f7f01a6a1c6d703e3972155b09c87466bf022 Mon Sep 17 00:00:00 2001
From: Alicja Michalska <alicja.michalska@9elements.com>
Date: Tue, 13 May 2025 00:44:08 +0200
Subject: [PATCH 1034/3886] mb/topton/adl: Use CFR setup menu to manage options

Much like ongoing CFR work, this patch adds support for configuring
certain options (such as iGPU memory allocation, ASPM, S3/s0ix, VT-d) at
runtime, using EDK2 payload.

TEST=Build/boot/toggle coreboot+edk2 on the firewall, test results by
booting Linux.

Change-Id: Id51e704750fd9aa4a8df72804d9205974747d708
Signed-off-by: Alicja Michalska <alicja.michalska@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87652
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
---
 src/mainboard/topton/adl/Kconfig     |  1 +
 src/mainboard/topton/adl/Makefile.mk |  3 ++
 src/mainboard/topton/adl/cfr.c       | 43 ++++++++++++++++++++++++++++
 3 files changed, 47 insertions(+)
 create mode 100644 src/mainboard/topton/adl/cfr.c

diff --git a/src/mainboard/topton/adl/Kconfig b/src/mainboard/topton/adl/Kconfig
index df8a513725..ffdfae1eee 100644
--- a/src/mainboard/topton/adl/Kconfig
+++ b/src/mainboard/topton/adl/Kconfig
@@ -5,6 +5,7 @@ if BOARD_TOPTON_X2F_N100
 config BOARD_SPECIFIC_OPTIONS
 	def_bool y
 	select BOARD_ROMSIZE_KB_16384
+	select DRIVERS_OPTION_CFR_ENABLED if PAYLOAD_EDK2 && SMMSTORE
 	select FSP_TYPE_IOT
 	select HAVE_ACPI_TABLES
 	select HAVE_ACPI_RESUME
diff --git a/src/mainboard/topton/adl/Makefile.mk b/src/mainboard/topton/adl/Makefile.mk
index 62d07cd369..e419baa665 100644
--- a/src/mainboard/topton/adl/Makefile.mk
+++ b/src/mainboard/topton/adl/Makefile.mk
@@ -1,5 +1,8 @@
 /* SPDX-License-Identifier: GPL-2.0-or-later */
 
 bootblock-y += bootblock.c
+
 romstage-y += romstage_fsp_params.c
+
 ramstage-y += mainboard.c
+ramstage-$(CONFIG_DRIVERS_OPTION_CFR) += cfr.c
diff --git a/src/mainboard/topton/adl/cfr.c b/src/mainboard/topton/adl/cfr.c
new file mode 100644
index 0000000000..d7cb7ba436
--- /dev/null
+++ b/src/mainboard/topton/adl/cfr.c
@@ -0,0 +1,43 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <boot/coreboot_tables.h>
+#include <drivers/option/cfr_frontend.h>
+#include <intelblocks/cfr.h>
+#include <soc/cfr.h>
+
+static struct sm_obj_form system = {
+	.ui_name = "System",
+	.obj_list = (const struct sm_object *[]) {
+		&igd_dvmt,
+		&igd_aperture,
+		&legacy_8254_timer,
+		&me_state,
+		&me_state_counter,
+		&pciexp_aspm,
+		&pciexp_clk_pm,
+		&pciexp_l1ss,
+		&pciexp_speed,
+		&s0ix_enable,
+		&vtd,
+		NULL
+	},
+};
+
+static struct sm_obj_form power = {
+	.ui_name = "Power",
+	.obj_list = (const struct sm_object *[]) {
+		&power_on_after_fail,
+		NULL
+	},
+};
+
+static struct sm_obj_form *sm_root[] = {
+	&system,
+	&power,
+	NULL
+};
+
+void mb_cfr_setup_menu(struct lb_cfr *cfr_root)
+{
+	cfr_write_setup_menu(cfr_root, sm_root);
+}

From 24757047e5c299287a6819a7f4c73b5a07625ce4 Mon Sep 17 00:00:00 2001
From: Martin Roth <gaumless@gmail.com>
Date: Wed, 14 May 2025 12:40:54 -0600
Subject: [PATCH 1035/3886] util/abuild: Fix merge error

In CB:87370 (util/abuild: Use ${} around variable names),
commit id: a2baaec067e, some lines were unintentionally reordered.

This led to abuild not working as intended.

Change-Id: I0aced8dde475f7338e4670c11a9cd1ec4502d743
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87681
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 util/abuild/abuild | 10 +++++-----
 1 file changed, 5 insertions(+), 5 deletions(-)

diff --git a/util/abuild/abuild b/util/abuild/abuild
index 5b87cbc2e7..66316e2eac 100755
--- a/util/abuild/abuild
+++ b/util/abuild/abuild
@@ -510,8 +510,8 @@ build_config()
 
 	export HOSTCC='gcc'
 
-		printf "%s doesn't support ChromeOS, skipping.\n" "${BUILD_NAME}"
 	if [[ "${chromeos}" = true ]] && [[ "$(grep -c "^[[:space:]]*select[[:space:]]*MAINBOARD_HAS_CHROMEOS>" "${ROOT}/src/mainboard/${board_srcdir}/Kconfig")" -eq 0 ]]; then
+		printf "%s doesn't support ChromeOS, skipping.\n" "${BUILD_NAME}"
 		return
 	fi
 
@@ -930,8 +930,8 @@ if [[ -n "$1" ]]; then
 	printf "Invalid option '%s'\n\n" "$1"; myhelp; exit 1;
 fi
 
-	printf "Please specify a valid, non-root build directory.\n"
 if [[ -z "${TARGET}" ]] || [[ "${TARGET}" = "/" ]]; then
+	printf "Please specify a valid, non-root build directory.\n"
 	exit 1
 fi
 
@@ -1039,13 +1039,13 @@ build_targets()
 	fi
 
 	if [[ "${scanbuild}" = "true" ]]; then
-		mv "${scanbuild_out}tmp/"* "${scanbuild_out}"
+		mv "${scanbuild_out}"tmp/* "${scanbuild_out}"
 		rmdir "${scanbuild_out}tmp"
 	fi
-	cpus_per_target=$(((${cpus:-1} + num_targets - 1) / num_targets))
-	printf "%s\n" "${targets}" | xargs -P "${cpus:-0}" -n 1 "$0" "${cmdline[@]}" -I -c "${cpus_per_target}" -t
 	rm -rf "${TARGET}/temp" "${TMPCFG}"
 	num_targets=$(wc -w <<<"${targets}")
+	cpus_per_target=$(((${cpus:-1} + num_targets - 1) / num_targets))
+	printf "%s\n" "${targets}" | xargs -P "${cpus:-0}" -n 1 "$0" "${cmdline[@]}" -I -c "${cpus_per_target}" -t
 }
 fi
 

From c4434785097cebcff6c2df8be839b9bfb0ec079c Mon Sep 17 00:00:00 2001
From: Luca Lai <luca.lai@lcfc.corp-partner.google.com>
Date: Mon, 28 Apr 2025 09:58:08 +0800
Subject: [PATCH 1036/3886] mb/trulo/var/pujjolo: Create pujjolo variant

Create the pujjolo variant of nissa reference board by copying the
template files to a new directory named for the variant.

Due to new_variant.py limitation that repo can no longer be used in
inside, created this CL manually following google suggestion.

BUG=b:395763555
TEST=util/abuild/abuild -p none -t google/brya -x -a
make sure the build includes GOOGLE_PUJJOLO

Change-Id: Ica959c0e22797ab75606af130fa1adff2b158b1d
Signed-off-by: Luca Lai <luca.lai@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87470
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/google/brya/Kconfig             |  16 +
 src/mainboard/google/brya/Kconfig.name        |   3 +
 .../google/brya/variants/pujjolo/Makefile.mk  |   9 +
 .../google/brya/variants/pujjolo/gpio.c       | 245 ++++++++
 .../google/brya/variants/pujjolo/hda_verb.c   |  78 +++
 .../variants/pujjolo/include/variant/ec.h     |   8 +
 .../variants/pujjolo/include/variant/gpio.h   |  18 +
 .../brya/variants/pujjolo/memory/Makefile.mk  |  10 +
 .../pujjolo/memory/dram_id.generated.txt      |  10 +
 .../pujjolo/memory/mem_parts_used.txt         |  15 +
 .../brya/variants/pujjolo/overridetree.cb     | 543 ++++++++++++++++++
 .../google/brya/variants/pujjolo/variant.c    |  19 +
 12 files changed, 974 insertions(+)
 create mode 100644 src/mainboard/google/brya/variants/pujjolo/Makefile.mk
 create mode 100644 src/mainboard/google/brya/variants/pujjolo/gpio.c
 create mode 100644 src/mainboard/google/brya/variants/pujjolo/hda_verb.c
 create mode 100644 src/mainboard/google/brya/variants/pujjolo/include/variant/ec.h
 create mode 100644 src/mainboard/google/brya/variants/pujjolo/include/variant/gpio.h
 create mode 100644 src/mainboard/google/brya/variants/pujjolo/memory/Makefile.mk
 create mode 100644 src/mainboard/google/brya/variants/pujjolo/memory/dram_id.generated.txt
 create mode 100644 src/mainboard/google/brya/variants/pujjolo/memory/mem_parts_used.txt
 create mode 100644 src/mainboard/google/brya/variants/pujjolo/overridetree.cb
 create mode 100644 src/mainboard/google/brya/variants/pujjolo/variant.c

diff --git a/src/mainboard/google/brya/Kconfig b/src/mainboard/google/brya/Kconfig
index 73e908a75c..4e9a0e6589 100644
--- a/src/mainboard/google/brya/Kconfig
+++ b/src/mainboard/google/brya/Kconfig
@@ -490,6 +490,18 @@ config BOARD_GOOGLE_PUJJOGATWIN
 	select HAVE_WWAN_POWER_SEQUENCE
 	select SOC_INTEL_TWINLAKE
 
+config BOARD_GOOGLE_PUJJOLO
+	select BOARD_GOOGLE_BASEBOARD_TRULO
+	select CHROMEOS_WIFI_SAR if CHROMEOS
+	select DRIVERS_GENERIC_GPIO_KEYS
+	select DRIVERS_INTEL_MIPI_CAMERA
+	select DRIVERS_I2C_SX9324
+	select DRIVERS_I2C_SX9324_SUPPORT_LEGACY_LINUX_DRIVER
+	select HAVE_WWAN_POWER_SEQUENCE
+	select SOC_INTEL_COMMON_BLOCK_HDA_VERB
+	select SOC_INTEL_TCSS_USE_PDC_PMC_USBC_MUX_CONFIGURATION
+	select SOC_INTEL_TWINLAKE
+
 config BOARD_GOOGLE_PUJJONIRU
 	select BOARD_GOOGLE_BASEBOARD_NISSA
 	select BOARD_ROMSIZE_KB_16384
@@ -869,6 +881,7 @@ config DRIVER_TPM_I2C_BUS
 	default 0x0 if BOARD_GOOGLE_MELIKS
 	default 0x0 if BOARD_GOOGLE_EPIC
 	default 0x0 if BOARD_GOOGLE_PUJJOCENTO
+	default 0x0 if BOARD_GOOGLE_PUJJOLO
 
 config DRIVER_TPM_I2C_ADDR
 	hex
@@ -955,6 +968,7 @@ config TPM_TIS_ACPI_INTERRUPT
 	default 13 if BOARD_GOOGLE_MELIKS
 	default 13 if BOARD_GOOGLE_EPIC
 	default 13 if BOARD_GOOGLE_PUJJOCENTO
+	default 13 if BOARD_GOOGLE_PUJJOLO
 
 config OVERRIDE_DEVICETREE
 	default "variants/\$(CONFIG_VARIANT_DIR)/overridetree_pujjogatwin.cb" if BOARD_GOOGLE_PUJJOGATWIN
@@ -1049,6 +1063,7 @@ config MAINBOARD_PART_NUMBER
 	default "Meliks" if BOARD_GOOGLE_MELIKS
 	default "Epic" if BOARD_GOOGLE_EPIC
 	default "Pujjocento" if BOARD_GOOGLE_PUJJOCENTO
+	default "Pujjolo" if BOARD_GOOGLE_PUJJOLO
 
 config VARIANT_DIR
 	default "agah" if BOARD_GOOGLE_AGAH
@@ -1128,6 +1143,7 @@ config VARIANT_DIR
 	default "meliks" if BOARD_GOOGLE_MELIKS
 	default "epic" if BOARD_GOOGLE_EPIC
 	default "pujjocento" if BOARD_GOOGLE_PUJJOCENTO
+	default "pujjolo" if BOARD_GOOGLE_PUJJOLO
 
 config VBOOT
 	select VBOOT_EARLY_EC_SYNC if !(BOARD_GOOGLE_BASEBOARD_NISSA || BOARD_GOOGLE_BASEBOARD_TRULO) || BOARD_GOOGLE_RULL
diff --git a/src/mainboard/google/brya/Kconfig.name b/src/mainboard/google/brya/Kconfig.name
index 764226ddf8..acc21afc28 100644
--- a/src/mainboard/google/brya/Kconfig.name
+++ b/src/mainboard/google/brya/Kconfig.name
@@ -218,6 +218,9 @@ config BOARD_GOOGLE_PUJJOGA
 config BOARD_GOOGLE_PUJJOGATWIN
 	bool "->  Pujjogatwin"
 
+config BOARD_GOOGLE_PUJJOLO
+	bool "->  Pujjolo"
+
 config BOARD_GOOGLE_ORISA
 	bool "->  Orisa"
 
diff --git a/src/mainboard/google/brya/variants/pujjolo/Makefile.mk b/src/mainboard/google/brya/variants/pujjolo/Makefile.mk
new file mode 100644
index 0000000000..902b65c59d
--- /dev/null
+++ b/src/mainboard/google/brya/variants/pujjolo/Makefile.mk
@@ -0,0 +1,9 @@
+# SPDX-License-Identifier: GPL-2.0-only
+bootblock-y += gpio.c
+
+romstage-y += gpio.c
+ramstage-y += gpio.c
+
+ramstage-y += variant.c
+
+ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_HDA_VERB) += hda_verb.c
diff --git a/src/mainboard/google/brya/variants/pujjolo/gpio.c b/src/mainboard/google/brya/variants/pujjolo/gpio.c
new file mode 100644
index 0000000000..8d60e59cb2
--- /dev/null
+++ b/src/mainboard/google/brya/variants/pujjolo/gpio.c
@@ -0,0 +1,245 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <baseboard/gpio.h>
+#include <baseboard/variants.h>
+#include <soc/gpio.h>
+#include <types.h>
+#include <vendorcode/google/chromeos/chromeos.h>
+
+/* Pad configuration in ramstage for Pujjolo */
+static const struct pad_config override_gpio_table[] = {
+	/* E17 : WWAN_RST_L */
+	PAD_CFG_GPO_LOCK(GPP_E17, 1, LOCK_CONFIG),
+	/* A7  : SLP_S0_GATE */
+	PAD_CFG_GPO(GPP_A7, 1, DEEP),
+	/* A8  : WWAN_RF_DISABLE_ODL */
+	PAD_CFG_GPO(GPP_A8, 1, DEEP),
+	/* A11 : EN_SPK_PA ==> NC */
+	PAD_NC(GPP_A11, NONE),
+	/* A12 : NC# ==> SOC_PEN_DETECT_ODL */
+	PAD_CFG_GPI_SCI_HIGH(GPP_A12, NONE, PLTRST, EDGE_SINGLE),
+	/* A13 : GPP_A13 ==> GSC_SOC_INT_ODL */
+	PAD_CFG_GPI_APIC(GPP_A13, NONE, PLTRST, LEVEL, INVERT),
+	/* A18 : DDSP_HPDB ==> DDI2_HPD */
+	/* A19 : NC */
+	PAD_NC(GPP_A19, NONE),
+	PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1),
+	/* A20  : HDMI_HPD */
+	PAD_NC(GPP_A20, NONE),
+	/* A21 : USB_C1_AUX_DC_P */
+	PAD_CFG_NF(GPP_A21, NONE, DEEP, NF6),
+	/* A22 : USB_C1_AUX_DC_N */
+	PAD_CFG_NF(GPP_A22, NONE, DEEP, NF6),
+	/* A23 :  NC */
+	PAD_NC(GPP_A23, NONE),
+	/* B2  : NC */
+	PAD_NC(GPP_B2, NONE),
+	/* B5  : SOC_I2C_SUB_SDA */
+	PAD_CFG_NF(GPP_B5, NONE, DEEP, NF2),
+	/* B6  : SOC_I2C_SUB_SCL */
+	PAD_CFG_NF(GPP_B6, NONE, DEEP, NF2),
+	/* D6  : SRCCLKREQ1# ==> WWAN_EN */
+	PAD_CFG_GPO(GPP_D6, 1, DEEP),
+	/* B7  : GPP_B7 ==> NC */
+	PAD_NC_LOCK(GPP_B7, NONE, LOCK_CONFIG),
+	/* B8  : WWAN_SAR_DETECT_2_ODL */
+	PAD_NC_LOCK(GPP_B8, NONE, LOCK_CONFIG),
+	/* B11 : SOC_PMC_PD0_INT_ODL */
+	PAD_CFG_NF(GPP_B11, NONE, DEEP, NF1),
+	/* B16  : GPP_B16 ==> I2C_5_SDA */
+	PAD_CFG_NF_LOCK(GPP_B16, NONE, NF2, LOCK_CONFIG),
+	/* B17  : GPP_B17 ==> I2C_5_SCL */
+	PAD_CFG_NF_LOCK(GPP_B17, NONE, NF2, LOCK_CONFIG),
+	/* C1  : SMBDATA ==> USI_RST_L */
+	PAD_CFG_GPO(GPP_C1, 1, DEEP),
+	/* C4  : TCHSCR_REPORT_EN */
+	PAD_CFG_GPO(GPP_C4, 0, DEEP),
+	/* C6  : I2C_SOC_PMC_PD_SCL */
+	PAD_CFG_NF(GPP_C6, NONE, DEEP, NF1),
+	/* C7  : I2C_SOC_PMC_PD_SDA */
+	PAD_CFG_NF(GPP_C7, NONE, DEEP, NF1),
+	/* D1  : SEN_MODE2_EC_ISH_INT_ODL */
+	PAD_CFG_NF(GPP_D1, NONE, DEEP, NF1),
+	/* D0  : ISH_GP0 ==> PCH_FP_BOOT0 */
+	PAD_CFG_GPO_LOCK(GPP_D0, 0, LOCK_CONFIG),
+	/* E7  : NC ==> FP_RST_ODL */
+	PAD_CFG_GPO_LOCK(GPP_E7, 1, LOCK_CONFIG),
+	/* D2 : NC ==> EN_FP_PWR */
+	PAD_CFG_GPO_LOCK(GPP_D2, 1, LOCK_CONFIG),
+	/* D3  : WCAM_RST_L ==> NC */
+	PAD_CFG_GPO_LOCK(GPP_D3, 0, LOCK_CONFIG),
+	/* D5  : SRCCLKREQ2# ==> WWAN_CLKREQ_ODL */
+	//PAD_CFG_NF(GPP_D5, NONE, DEEP, NF1),
+	/* D13 : UART0_ISH_RX_DBG_TX */
+	PAD_CFG_NF(GPP_D13, NONE, DEEP, NF1),
+	/* D14 : UART0_ISH_TX_DBG_RX */
+	PAD_CFG_NF(GPP_D14, NONE, DEEP, NF1),
+	/* D15 : ISH_UART0_RTS# ==> EN_PP2800_WCAM_X */
+	PAD_CFG_GPO_LOCK(GPP_D15, 1, LOCK_CONFIG),
+	/* D16 : ISH_UART0_CTS# ==> EN_PP1800_PP1200_WCAM_X */
+	PAD_CFG_GPO_LOCK(GPP_D16, 1, LOCK_CONFIG),
+	/* D17  : NC ==> UART_AP_RX_FP_TX */
+	PAD_CFG_NF(GPP_D17, NONE, DEEP, NF1),
+	/* D18  : NC ==> UART_AP_TX_FP_RX */
+	PAD_CFG_NF(GPP_D18, NONE, DEEP, NF1),
+	/* D19 : NC */
+	PAD_NC(GPP_D19, NONE),
+	/* E0 : NC ==> SOC_PEN_DETECT_R_ODL */
+	PAD_CFG_GPI_INT(GPP_E0, NONE, PLTRST, EDGE_BOTH),
+	/* E4  : WLAN_WWAN_COEX_1 temp out high*/
+	PAD_CFG_GPO(GPP_E4, 0, DEEP),
+	/* E5  : WLAN_WWAN_COEX_2 temp out high */
+	PAD_CFG_GPO(GPP_E5, 0, DEEP),
+	/* E11  : TCHSCR_INT_ODL */
+	PAD_CFG_GPI_APIC(GPP_E11, NONE, PLTRST, LEVEL, INVERT),
+	/* E13 : SD_WAKE_N */
+	PAD_CFG_GPI_LOCK(GPP_E13, NONE, LOCK_CONFIG),
+	/* E20 : DDP2_CTRLCLK ==> HDMI_DDC_SCL */
+	PAD_NC(GPP_E20, NONE),
+	/* E21 : DDP2_CTRLDATA ==> HDMI_DDC_SDA_STRAP */
+	PAD_NC(GPP_E21, NONE),
+	/* E22 : USB_C0_AUX_DC_P */
+	PAD_CFG_NF(GPP_E22, NONE, DEEP, NF6),
+	/* E23 : USB_C0_AUX_DC_N */
+	PAD_CFG_NF(GPP_E23, NONE, DEEP, NF6),
+	/* F11 : NC ==> GSPI_PCH_CLK_FPMCU */
+	PAD_CFG_NF(GPP_F11, NONE, DEEP, NF4),
+	/* F12 : WWAN_RST_L ==> GSPI_PCH_DO_FPMCU_DI_R */
+	PAD_CFG_NF(GPP_F12, NONE, DEEP, NF4),
+	/* F13 : SOC_PEN_DETECT_R_ODL ==> GSPI_PCH_DI_FPMCU_DO */
+	PAD_CFG_NF(GPP_F13, NONE, DEEP, NF4),
+	/* F15 : SOC_PEN_DETECT_ODL ==> FPMCU_INT_L */
+	PAD_CFG_GPI_IRQ_WAKE(GPP_F15, NONE, PWROK, LEVEL, INVERT),
+	/* F16  : NC ==> GSPI_PCH_CS_FPMCU_R_L */
+	PAD_CFG_NF(GPP_F16, NONE, DEEP, NF4),
+	/* H8 : I2C_1_SDA */
+	PAD_CFG_NF(GPP_H8, NONE, DEEP, NF1),
+	/* H9 : I2C_1_SCL */
+	PAD_CFG_NF(GPP_H9, NONE, DEEP, NF1),
+	/* H15  : PD0_SOC_DBG_L */
+	PAD_CFG_NF(GPP_H15, NONE, DEEP, NF1),
+	//PAD_CFG_GPI_LOCK(GPP_H15, NONE, LOCK_CONFIG),
+	/* H17  : PD1_SOC_DBG_L*/
+	//PAD_CFG_GPI_LOCK(GPP_H17, NONE, LOCK_CONFIG),
+	PAD_CFG_NF(GPP_H17, NONE, DEEP, NF1),
+	/* H18 : CPU_C10_GATE_L */
+	PAD_CFG_NF(GPP_H18, NONE, DEEP, NF1),
+	/* H19 : SOC_I2C_SUB_INT_ODL */
+	PAD_CFG_GPI_APIC(GPP_H19, NONE, PLTRST, LEVEL, NONE),
+	/* H21  : WWAN_PERST_L */
+	PAD_NC_LOCK(GPP_H21, NONE, LOCK_CONFIG),
+	/* H23 : WWAN_SAR_DETECT_ODL ==> NC */
+	PAD_NC_LOCK(GPP_H23, NONE, LOCK_CONFIG),
+	/* R0  : HDA_HP_BCLK_R */
+	PAD_CFG_NF(GPP_R0, NONE, DEEP, NF1),
+	/* R1  : HDA_HP_SYNC_R */
+	PAD_CFG_NF(GPP_R1, NONE, DEEP, NF1),
+	/* R2 : HDA_HP_SDO_R */
+	PAD_CFG_NF(GPP_R2, NONE, DEEP, NF1),
+	/* R3 : HDA_HP_SDIN0_R */
+	PAD_CFG_NF(GPP_R3, NONE, DEEP, NF1),
+	/* R4 : DMIC_CLK_A_0A ==> DMIC_UCAM_CLK_R */
+	PAD_CFG_NF(GPP_R4, NONE, DEEP, NF3),
+	/* R5 : DMIC_DATA_0A ==> DMIC_UCAM_DATA */
+	PAD_CFG_NF(GPP_R5, NONE, DEEP, NF3),
+	/* R6 : DMIC_CLK_A_1A ==> DMIC_WCAM_CLK_R */
+	PAD_CFG_NF(GPP_R6, NONE, DEEP, NF3),
+	/* R7 : DMIC_DATA_1A ==> DMIC_WCAM_DATA */
+	PAD_CFG_NF(GPP_R7, NONE, DEEP, NF3),
+	/* S0  : NC */
+	PAD_NC(GPP_S0, NONE),
+	/* S1  : NC */
+	PAD_NC(GPP_S1, NONE),
+	/* S2 :  NC */
+	PAD_NC(GPP_S2, NONE),
+
+};
+
+/* Early pad configuration in bootblock */
+static const struct pad_config early_gpio_table[] = {
+	/* A13 : GPP_A13 ==> GSC_SOC_INT_ODL */
+	PAD_CFG_GPI_APIC(GPP_A13, NONE, PLTRST, LEVEL, INVERT),
+	/*
+	* WWAN_EN is asserted in ramstage to meet the 500 ms warm reset toff
+	* requirement. WWAN_EN must be asserted before WWAN_RST_L is released
+	* (with min delay 0 ms), so this works as long as the pin used for
+	* WWAN_EN comes before the pin used for WWAN_RST_L.
+	*/
+	/* D6  : SRCCLKREQ1# ==> WWAN_EN */
+	PAD_CFG_GPO(GPP_D6, 0, DEEP),
+	/* E12 : THC0_SPI1_IO1 ==> SOC_WP_OD */
+	PAD_CFG_GPI_GPIO_DRIVER(GPP_E12, NONE, DEEP),
+	/*
+	 * E7 ==> FP_RST_ODL
+	 * FP_RST_ODL comes out of reset as hi-z and does not have an external pull-down.
+	 * To ensure proper power sequencing for the FPMCU device, reset signal is driven low
+	 * early on in bootblock, followed by enabling of power. Reset signal is deasserted
+	 * later on in ramstage. Since reset signal is asserted in bootblock, it results in
+	 * FPMCU not working after a S3 resume. This is a known issue.
+	 */
+	 PAD_CFG_GPO(GPP_E7, 0, DEEP),
+	 /* D2  : ISH_GP2 ==> EN_FP_PWR */
+	 PAD_CFG_GPO(GPP_D2, 1, DEEP),
+	/* E17 : WWAN_RST_L */
+	PAD_CFG_GPO(GPP_E17, 0, DEEP),
+	/* H4  : I2C0_SDA ==> SOC_I2C_GSC_SDA */
+	PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1),
+	/* H5  : I2C0_SCL ==> SOC_I2C_GSC_SCL */
+	PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1),
+	/* H10 : UART0_RXD ==> UART_SOC_RX_DBG_TX */
+	PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2),
+	/* H11 : UART0_TXD ==> UART_SOC_TX_DBG_RX */
+	PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2),
+};
+
+/* Pad configuration in romstage for Sundance */
+static const struct pad_config romstage_gpio_table[] = {
+	/* E17 : WWAN_RST_L */
+	PAD_CFG_GPO(GPP_E17, 1, DEEP),
+	/* Enable touchscreen, hold in reset */
+	/* C0  : SMBCLK ==> EN_PP3300_TCHSCR */
+	PAD_CFG_GPO(GPP_C0, 1, DEEP),
+	/* C1  : SMBDATA ==> USI_RST_L */
+	PAD_CFG_TERM_GPO(GPP_C1, 0, UP_20K, DEEP),
+	/*
+	 * E7 ==> FP_RST_ODL
+	 * FP_RST_ODL comes out of reset as hi-z and does not have an external pull-down.
+	 * To ensure proper power sequencing for the FPMCU device, reset signal is driven low
+	 * early on in bootblock, followed by enabling of power. Reset signal is deasserted
+	 * later on in ramstage. Since reset signal is asserted in bootblock, it results in
+	 * FPMCU not working after a S3 resume. This is a known issue.
+	 */
+	 PAD_CFG_GPO(GPP_E7, 0, DEEP),
+	 /* D2  : ISH_GP2 ==> EN_FP_PWR */
+	 PAD_CFG_GPO(GPP_D2, 0, DEEP),
+};
+
+const struct pad_config *variant_gpio_override_table(size_t *num)
+{
+	*num = ARRAY_SIZE(override_gpio_table);
+	return override_gpio_table;
+}
+
+const struct pad_config *variant_gpio_table(size_t *num)
+{
+	*num = ARRAY_SIZE(override_gpio_table);
+	return override_gpio_table;
+}
+
+const struct pad_config *variant_early_gpio_table(size_t *num)
+{
+	*num = ARRAY_SIZE(early_gpio_table);
+	return early_gpio_table;
+}
+
+const struct pad_config *variant_romstage_gpio_table(size_t *num)
+{
+	*num = ARRAY_SIZE(romstage_gpio_table);
+	return romstage_gpio_table;
+}
+
+static const struct cros_gpio cros_gpios[] = {
+	CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME),
+	CROS_GPIO_WP_AH(GPIO_PCH_WP, CROS_GPIO_DEVICE_NAME),
+};
+DECLARE_CROS_GPIOS(cros_gpios);
diff --git a/src/mainboard/google/brya/variants/pujjolo/hda_verb.c b/src/mainboard/google/brya/variants/pujjolo/hda_verb.c
new file mode 100644
index 0000000000..a34adef9f8
--- /dev/null
+++ b/src/mainboard/google/brya/variants/pujjolo/hda_verb.c
@@ -0,0 +1,78 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <device/azalia_device.h>
+
+const u32 cim_verb_data[] = {
+	/* coreboot specific header */
+	0x10ec0257,	// Codec Vendor / Device ID: Realtek ALC257
+	0x10ec0257,	// Subsystem ID
+	0x00000011,	// Number of jacks (NID entries)
+
+	AZALIA_RESET(0x1),
+	/* NID 0x01, HDA Codec Subsystem ID Verb table */
+	//AZALIA_SUBVENDOR(0, 0x10ec3a2c),
+
+	/* Pin Widget Verb Table */
+	/*
+	 * DMIC
+	 * Requirement is to use PCH DMIC. Hence,
+	 * commented out codec's Internal DMIC.
+	 * AZALIA_PIN_CFG(0, 0x12, 0x90A60130),
+	 * AZALIA_PIN_CFG(0, 0x13, 0x40000000),
+	 */
+	 AZALIA_PIN_CFG(0, 0x12, 0x40000000),
+	 AZALIA_PIN_CFG(0, 0x13, 0x411111F0),
+	 AZALIA_PIN_CFG(0, 0x14, 0x90170110),
+	 AZALIA_PIN_CFG(0, 0x18, 0x411111f0),
+	 AZALIA_PIN_CFG(0, 0x19, 0x04A11030),
+	 AZALIA_PIN_CFG(0, 0x1a, 0x411111f0),
+	 AZALIA_PIN_CFG(0, 0x1b, 0x411111f0),
+	 AZALIA_PIN_CFG(0, 0x1d, 0x40579A2D),
+	 AZALIA_PIN_CFG(0, 0x1e, 0x411111F0),
+	 AZALIA_PIN_CFG(0, 0x21, 0x04211020),
+	//==========Widget node 0x20 - 0 :Hidden register SW reset
+	0x0205001A,
+	0x0204C003,
+	0x0205001A,
+	0x0204C003,
+	//==========Widget node 0x20 - 1 : ClassD 2W
+	0x02050038,
+	0x02047981,
+	0x0205001B,
+	0x02040A4B,
+	//==========Widget node 0x20 - 2
+	0x0205003C,
+	0x02043154,
+	0x0205003C,
+	0x02043114,
+	//==========Widget node 0x20 - 3 :
+	0x02050046,
+	0x02040004,
+	0x05750003,
+	0x057409A3,
+	//==========Widget node 0x20 - 4 :JD1 enable 1JD port for HP JD
+	0x02050009,
+	0x02046003,
+	0x0205000A,
+	0x02047770,
+	//==========Widget node 0x20 - 5 : Silence data mode Threshold (-84dB)
+	0x02050037,
+	0x0204FE15,
+	0x02050030,
+	0x02041000,
+};
+
+const u32 pc_beep_verbs[] = {
+	/* Dos beep path - 1 */
+	0x02050010,
+	0x02040020,
+	0x02050036,
+	0x02047151,
+	/* Dos beep path - 2 */
+	0x01470740,
+	0x0143B000,
+	0x01470C02,
+	0x01470C02,
+};
+
+AZALIA_ARRAY_SIZES;
diff --git a/src/mainboard/google/brya/variants/pujjolo/include/variant/ec.h b/src/mainboard/google/brya/variants/pujjolo/include/variant/ec.h
new file mode 100644
index 0000000000..7a2a6ff8b7
--- /dev/null
+++ b/src/mainboard/google/brya/variants/pujjolo/include/variant/ec.h
@@ -0,0 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#ifndef __VARIANT_EC_H__
+#define __VARIANT_EC_H__
+
+#include <baseboard/ec.h>
+
+#endif
diff --git a/src/mainboard/google/brya/variants/pujjolo/include/variant/gpio.h b/src/mainboard/google/brya/variants/pujjolo/include/variant/gpio.h
new file mode 100644
index 0000000000..bb6eff297c
--- /dev/null
+++ b/src/mainboard/google/brya/variants/pujjolo/include/variant/gpio.h
@@ -0,0 +1,18 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#ifndef VARIANT_GPIO_H
+#define VARIANT_GPIO_H
+
+#include <baseboard/gpio.h>
+
+#define WWAN_FCPO	GPP_D6
+#define WWAN_RST	GPP_E17
+#define T2_OFF_MS	20
+/* FPR feature need add SLP_S0_GATE_R to control.
+Pujjoniru reference baord did not have HAVE_SLP_S0_GATE.
+So we add a variant specific S0ix hook to fill the SSDT
+table to control FPR feature. GPP_A7 pull down when do
+suspend and pull high when resume. */
+#define SLP_S0_FP_EN	GPP_A7
+
+#endif
diff --git a/src/mainboard/google/brya/variants/pujjolo/memory/Makefile.mk b/src/mainboard/google/brya/variants/pujjolo/memory/Makefile.mk
new file mode 100644
index 0000000000..07e09804c1
--- /dev/null
+++ b/src/mainboard/google/brya/variants/pujjolo/memory/Makefile.mk
@@ -0,0 +1,10 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+# This is an auto-generated file. Do not edit!!
+# Generated by:
+# util/spd_tools/bin/part_id_gen adl lp5 src/mainboard/google/brya/variants/pujjolo/memory src/mainboard/google/brya/variants/pujjolo/memory/mem_parts_used.txt
+
+SPD_SOURCES =
+SPD_SOURCES += spd/lp5/set-0/spd-9.hex      # ID = 0(0b0000)  Parts = K3KL6L60GM-MGCT
+SPD_SOURCES += spd/lp5/set-0/spd-7.hex      # ID = 1(0b0001)  Parts = K3KL8L80CM-MGCT
+SPD_SOURCES += spd/lp5/set-0/spd-11.hex      # ID = 2(0b0010)  Parts = H58G56CK8BX146
+SPD_SOURCES += spd/lp5/set-0/spd-2.hex      # ID = 3(0b0011)  Parts = H9JCNNNCP3MLYR-N6E
diff --git a/src/mainboard/google/brya/variants/pujjolo/memory/dram_id.generated.txt b/src/mainboard/google/brya/variants/pujjolo/memory/dram_id.generated.txt
new file mode 100644
index 0000000000..cf61f227ff
--- /dev/null
+++ b/src/mainboard/google/brya/variants/pujjolo/memory/dram_id.generated.txt
@@ -0,0 +1,10 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+# This is an auto-generated file. Do not edit!!
+# Generated by:
+# util/spd_tools/bin/part_id_gen adl lp5 src/mainboard/google/brya/variants/pujjolo/memory src/mainboard/google/brya/variants/pujjolo/memory/mem_parts_used.txt
+
+DRAM Part Name                 ID to assign
+K3KL6L60GM-MGCT                0 (0000)
+K3KL8L80CM-MGCT                1 (0001)
+H58G56CK8BX146                 2 (0010)
+H9JCNNNCP3MLYR-N6E             3 (0011)
diff --git a/src/mainboard/google/brya/variants/pujjolo/memory/mem_parts_used.txt b/src/mainboard/google/brya/variants/pujjolo/memory/mem_parts_used.txt
new file mode 100644
index 0000000000..c8815ed13e
--- /dev/null
+++ b/src/mainboard/google/brya/variants/pujjolo/memory/mem_parts_used.txt
@@ -0,0 +1,15 @@
+# This is a CSV file containing a list of memory parts used by this variant.
+# One part per line with an optional fixed ID in column 2.
+# Only include a fixed ID if it is required for legacy reasons!
+# Generated IDs are dependent on the order of parts in this file,
+# so new parts must always be added at the end of the file!
+#
+# Generate an updated Makefile.mk and dram_id.generated.txt by running the
+# part_id_gen tool from util/spd_tools.
+# See util/spd_tools/README.md for more details and instructions.
+
+# Part Name
+K3KL6L60GM-MGCT
+K3KL8L80CM-MGCT
+H58G56CK8BX146
+H9JCNNNCP3MLYR-N6E
diff --git a/src/mainboard/google/brya/variants/pujjolo/overridetree.cb b/src/mainboard/google/brya/variants/pujjolo/overridetree.cb
new file mode 100644
index 0000000000..9a3b1a0b46
--- /dev/null
+++ b/src/mainboard/google/brya/variants/pujjolo/overridetree.cb
@@ -0,0 +1,543 @@
+fw_config
+	field WWAN 3 4
+		option WWAN_ABSENT		0
+		option LTE_PRESENT		1
+		option 5G_PRESENT		2
+	end
+	field WIFI_SAR_ID 18 21
+		option WIFI_SAR_TABLE_AX211	0
+		option WIFI_SAR_TABLE_AX203	1
+	end
+end
+chip soc/intel/alderlake
+
+	# Acoustic settings
+	register "acoustic_noise_mitigation" = "1"
+	register "slow_slew_rate[VR_DOMAIN_IA]" = "SLEW_FAST_8"
+	register "slow_slew_rate[VR_DOMAIN_GT]" = "SLEW_FAST_8"
+	register "fast_pkg_c_ramp_disable[VR_DOMAIN_IA]" = "1"
+	register "fast_pkg_c_ramp_disable[VR_DOMAIN_GT]" = "1"
+	register "PreWake" = "100"
+
+	register "sagv" = "SaGv_Enabled"
+
+	# SOC Aux orientation override:
+	# This is a bitfield that corresponds to up to 4 TCSS ports.
+	# Bits (0,1) allocated for TCSS Port1 configuration and Bits (2,3)for TCSS Port2.
+	# TcssAuxOri = 0101b
+	# Bit0,Bit2 set to "1" indicates no retimer on USBC Ports
+	# Bit1,Bit3 set to "0" indicates Aux lines are not swapped on the
+	# motherboard to USBC connector
+	register "tcss_aux_ori" = "0"
+
+	register "typec_aux_bias_pads[0]" = "{.pad_auxp_dc = GPP_E22, .pad_auxn_dc = GPP_E23}"
+	register "typec_aux_bias_pads[1]" = "{.pad_auxp_dc = GPP_A21, .pad_auxn_dc = GPP_A22}"
+
+	register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC_SKIP)"	# USB2_C0
+	register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC_SKIP)"	# USB2_C1
+	register "usb2_ports[3]" = "USB2_PORT_MID(OC_SKIP)"	# USB-A1
+	register "usb2_ports[4]" = "USB2_PORT_MID(OC_SKIP)"	# WWAN
+	register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)"	# UF Camera
+	register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)"	# WF Camera
+	register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)"	# Bluetooth port for PCIe WLAN
+	register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)"	# Bluetooth port for CNVi WLAN
+
+	#register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)"	# USB3 port for WWAN
+
+	# HD Audio
+	register "pch_hda_dsp_enable" = "1"
+	register "pch_hda_audio_link_hda_enable" = "1"
+	register "pch_hda_idisp_link_tmode" = "HDA_TMODE_8T"
+	register "pch_hda_idisp_link_frequency" = "HDA_LINKFREQ_96MHZ"
+	register "pch_hda_idisp_codec_enable" = "1"
+	register "pch_hda_sdi_enable[0]" = "true"
+	register "pch_hda_sdi_enable[1]" = "true"
+
+
+	# Intel Common SoC Config
+	#+-------------------+---------------------------+
+	#| Field             |  Value                    |
+	#+-------------------+---------------------------+
+	#| I2C0              | TPM. Early init is        |
+	#|                   | required to set up a BAR  |
+	#|                   | for TPM communication     |
+	#| I2C1              | Touchscreen               |
+	#| I2C2              | Sub-board(PSensor)/WCAM   |
+	#| I2C5              | Trackpad                  |
+	#+-------------------+---------------------------+
+	register "common_soc_config" = "{
+		.i2c[0] = {
+			.early_init = 1,
+			.speed = I2C_SPEED_FAST_PLUS,
+			.speed_config[0] = {
+				.speed = I2C_SPEED_FAST_PLUS,
+				.scl_lcnt = 55,
+				.scl_hcnt = 30,
+				.sda_hold = 7,
+			}
+		},
+		.i2c[1] = {
+			.speed = I2C_SPEED_FAST,
+			.speed_config[0] = {
+				.speed = I2C_SPEED_FAST,
+				.scl_lcnt = 157,
+				.scl_hcnt = 79,
+				.sda_hold = 7,
+			}
+		},
+		.i2c[2] = {
+			.speed = I2C_SPEED_FAST,
+			.speed_config[0] = {
+				.speed = I2C_SPEED_FAST,
+				.scl_lcnt = 157,
+				.scl_hcnt = 79,
+				.sda_hold = 7,
+			}
+		},
+		.i2c[4] = {
+			.speed = I2C_SPEED_FAST,
+			.speed_config[0] = {
+				.speed = I2C_SPEED_FAST,
+				.scl_lcnt = 158,
+				.scl_hcnt = 79,
+				.sda_hold = 7,
+			}
+		},
+		.i2c[5] = {
+			.speed = I2C_SPEED_FAST,
+			.speed_config[0] = {
+				.speed = I2C_SPEED_FAST,
+				.scl_lcnt = 158,
+				.scl_hcnt = 79,
+				.sda_hold = 7,
+			}
+		},
+	}"
+
+	register "serial_io_gspi_mode" = "{
+		[PchSerialIoIndexGSPI0] = PchSerialIoPci,
+		[PchSerialIoIndexGSPI1] = PchSerialIoPci,
+	}"
+
+	register "serial_io_uart_mode" = "{
+		[PchSerialIoIndexUART0] = PchSerialIoPci,
+		[PchSerialIoIndexUART1] = PchSerialIoPci,
+		[PchSerialIoIndexUART2] = PchSerialIoDisabled,
+	}"
+
+	device domain 0 on
+		device ref ipu on
+			chip drivers/intel/mipi_camera
+				register "acpi_uid" = "0x50000"
+				register "acpi_name" = ""IPU0""
+				register "device_type" = "INTEL_ACPI_CAMERA_CIO2"
+
+				register "cio2_num_ports" = "1"
+				register "cio2_lanes_used" = "{2}" # 2 CSI Camera lanes are used
+				register "cio2_lane_endpoint[0]" = ""^I2C4.CAM0""
+				register "cio2_prt[0]" = "1"
+				device generic 0 on end
+			end
+		end
+		device ref i2c0 on
+			chip drivers/i2c/tpm
+				register "hid" = ""GOOG0005""
+				register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_A13_IRQ)"
+				device i2c 50 on end
+			end
+		end #I2C0
+		device ref i2c1 on
+			chip drivers/i2c/hid
+				register "generic.hid" = ""GDIX0000""
+				register "generic.desc" = ""Goodix Touchscreen""
+				register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_E11_IRQ)"
+				register "generic.detect" = "1"
+				register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C0)"
+				register "generic.enable_delay_ms" = "20"
+				register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C1)"
+				register "generic.reset_delay_ms" = "180"
+				register "generic.reset_off_delay_ms" = "3"
+				register "generic.stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C4)"
+				register "generic.stop_off_delay_ms" = "1"
+				register "generic.has_power_resource" = "1"
+				register "hid_desc_reg_offset" = "0x01"
+				device i2c 5d on end
+			end
+			chip drivers/generic/gpio_keys
+				register "name" = ""PENH""
+				register "gpio" = "ACPI_GPIO_INPUT_ACTIVE_LOW(GPP_E0)"
+				register "key.wake_gpe" = "GPE0_DW0_12"
+				register "key.wakeup_route" = "WAKEUP_ROUTE_SCI"
+				register "key.wakeup_event_action" = "EV_ACT_DEASSERTED"
+				register "key.dev_name" = ""EJCT""
+				register "key.linux_code" = "SW_PEN_INSERTED"
+				register "key.linux_input_type" = "EV_SW"
+				register "key.label" = ""pen_eject""
+				device generic 0 on end
+			end
+		end
+		device ref i2c2 on
+			chip drivers/i2c/sx9324
+				register "desc" = ""SAR Proximity Sensor""
+				register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_H19_IRQ)"
+				register "speed" = "I2C_SPEED_FAST"
+				register "uid" = "1"
+				register "reg_gnrl_ctrl0" = "0x16"
+				register "reg_gnrl_ctrl1" = "0x21"
+				register "reg_afe_ctrl0" = "0x00"
+				register "reg_afe_ctrl1" = "0x10"
+				register "reg_afe_ctrl2" = "0x00"
+				register "reg_afe_ctrl3" = "0x00"
+				register "reg_afe_ctrl4" = "0x47"
+				register "reg_afe_ctrl5" = "0x00"
+				register "reg_afe_ctrl6" = "0x00"
+				register "reg_afe_ctrl7" = "0x47"
+				register "reg_afe_ctrl8" = "0x12"
+				register "reg_afe_ctrl9" = "0x08"
+				register "reg_afe_ph0" = "0x3d"
+				register "reg_afe_ph1" = "0x1b"
+				register "reg_afe_ph2" = "0x1f"
+				register "reg_afe_ph3" = "0x3d"
+				register "reg_prox_ctrl0" = "0x0b"
+				register "reg_prox_ctrl1" = "0x0a"
+				register "reg_prox_ctrl2" = "0x90"
+				register "reg_prox_ctrl3" = "0x60"
+				register "reg_prox_ctrl4" = "0x0c"
+				register "reg_prox_ctrl5" = "0x00"
+				register "reg_prox_ctrl6" = "0x19"
+				register "reg_prox_ctrl7" = "0x58"
+				register "reg_adv_ctrl0" = "0x00"
+				register "reg_adv_ctrl1" = "0x00"
+				register "reg_adv_ctrl2" = "0x00"
+				register "reg_adv_ctrl3" = "0x00"
+				register "reg_adv_ctrl4" = "0x00"
+				register "reg_adv_ctrl5" = "0x05"
+				register "reg_adv_ctrl6" = "0x00"
+				register "reg_adv_ctrl7" = "0x00"
+				register "reg_adv_ctrl8" = "0x00"
+				register "reg_adv_ctrl9" = "0x00"
+				register "reg_adv_ctrl10" = "0x00"
+				register "reg_adv_ctrl11" = "0x00"
+				register "reg_adv_ctrl12" = "0x00"
+				register "reg_adv_ctrl13" = "0x00"
+				register "reg_adv_ctrl14" = "0x80"
+				register "reg_adv_ctrl15" = "0x0c"
+				register "reg_adv_ctrl16" = "0x08"
+				register "reg_adv_ctrl17" = "0x56"
+				register "reg_adv_ctrl18" = "0x33"
+				register "reg_adv_ctrl19" = "0x00"
+				register "reg_adv_ctrl20" = "0x00"
+
+				register "ph0_pin" = "{1, 3, 3}"
+				register "ph1_pin" = "{3, 2, 1}"
+				register "ph2_pin" = "{3, 3, 1}"
+				register "ph3_pin" = "{1, 3, 3}"
+				register "ph01_resolution" = "1024"
+				register "ph23_resolution" = "1024"
+				register "startup_sensor" = "1"
+				register "ph01_proxraw_strength" = "3"
+				register "ph23_proxraw_strength" = "2"
+				register "avg_pos_strength" = "256"
+				register "cs_idle_sleep" = ""hi-z""
+				register "int_comp_resistor" = ""lowest""
+				register "input_precharge_resistor_ohms" = "4000"
+				register "input_analog_gain" = "1"
+				device i2c 28 on end
+			end
+		end
+		device ref i2c4 on
+			chip drivers/intel/mipi_camera
+				register "acpi_hid" = ""OVTI8856""
+				register "acpi_uid" = "0"
+				register "acpi_name" = ""CAM0""
+				register "chip_name" = ""Ov 8856 Camera""
+				register "device_type" = "INTEL_ACPI_CAMERA_SENSOR"
+				register "has_power_resource" = "1"
+				register "max_dstate_for_probe" = "ACPI_DEVICE_SLEEP_D3_COLD"
+
+				register "ssdb.lanes_used" = "2"
+				register "ssdb.link_used" = "1"
+				register "ssdb.vcm_type" = "0x0C"
+				register "vcm_name" = ""VCM0""
+				register "num_freq_entries" = "2"
+				register "link_freq[0]" = "720000000"
+				register "link_freq[1]" = "360000000"
+				register "remote_name" = ""IPU0""
+
+				#Controls
+				register "clk_panel.clks[0].clknum" = "IMGCLKOUT_3"
+				register "clk_panel.clks[0].freq" = "FREQ_19_2_MHZ"
+
+				register "gpio_panel.gpio[0].gpio_num" = "GPP_D15"  # EN_PP2800_WCAM_X
+				register "gpio_panel.gpio[1].gpio_num" = "GPP_D16"  # EN_PP1800_PP1200_WCAM_X
+				register "gpio_panel.gpio[2].gpio_num" = "GPP_D3"   # WCAM_RST_L
+
+				#_ON
+				register "on_seq.ops_cnt" = "5"
+				register "on_seq.ops[0]" = "SEQ_OPS_CLK_ENABLE(0, 0)"
+				register "on_seq.ops[1]" = "SEQ_OPS_GPIO_ENABLE(0, 5)"
+				register "on_seq.ops[2]" = "SEQ_OPS_GPIO_ENABLE(1, 5)"
+				register "on_seq.ops[3]" = "SEQ_OPS_GPIO_DISABLE(2, 5)"
+				register "on_seq.ops[4]" = "SEQ_OPS_GPIO_ENABLE(2, 5)"
+
+				#_OFF
+				register "off_seq.ops_cnt" = "4"
+				register "off_seq.ops[0]" = "SEQ_OPS_CLK_DISABLE(0, 0)"
+				register "off_seq.ops[1]" = "SEQ_OPS_GPIO_DISABLE(2, 0)"
+				register "off_seq.ops[2]" = "SEQ_OPS_GPIO_DISABLE(1, 0)"
+				register "off_seq.ops[3]" = "SEQ_OPS_GPIO_DISABLE(0, 0)"
+
+				device i2c 10 on
+				end
+			end
+			chip drivers/intel/mipi_camera
+				register "acpi_uid" = "3"
+				register "acpi_name" = ""VCM0""
+				register "chip_name" = ""DW AF DAC""
+				register "device_type" = "INTEL_ACPI_CAMERA_VCM"
+
+				register "vcm_compat" = ""dongwoon,dw9714""
+				register "has_power_resource" = "true"
+				register "max_dstate_for_probe" = "ACPI_DEVICE_SLEEP_D3_COLD"
+
+				# Controls
+				register "gpio_panel.gpio[0].gpio_num" = "GPP_D15"  # EN_PP2800_WCAM_X
+				register "gpio_panel.gpio[1].gpio_num" = "GPP_D16"  # EN_PP1800_PP1200_WCAM_X
+
+				# _ON
+				register "on_seq.ops_cnt" = "2"
+				register "on_seq.ops[0]" = "SEQ_OPS_GPIO_ENABLE(0, 5)"
+				register "on_seq.ops[1]" = "SEQ_OPS_GPIO_ENABLE(1, 5)"
+
+				# _OFF
+				register "off_seq.ops_cnt" = "2"
+				register "off_seq.ops[0]" = "SEQ_OPS_GPIO_DISABLE(1, 0)"
+				register "off_seq.ops[1]" = "SEQ_OPS_GPIO_DISABLE(0, 0)"
+
+				device i2c 0C on
+				end
+			end
+			chip drivers/intel/mipi_camera
+				register "acpi_hid" = "ACPI_DT_NAMESPACE_HID"
+				register "acpi_uid" = "1"
+				register "acpi_name" = ""NVM0""
+				register "chip_name" = ""GT24C08""
+				register "device_type" = "INTEL_ACPI_CAMERA_NVM"
+				register "has_power_resource" = "true"
+				register "max_dstate_for_probe" = "ACPI_DEVICE_SLEEP_D3_COLD"
+
+				# Controls
+				register "gpio_panel.gpio[0].gpio_num" = "GPP_D16"  # EN_PP1800_PP1200_WCAM_X
+
+				# _ON
+				register "on_seq.ops_cnt" = "1"
+				register "on_seq.ops[0]" = "SEQ_OPS_GPIO_ENABLE(0, 5)"
+
+				# _OFF
+				register "off_seq.ops_cnt" = "1"
+				register "off_seq.ops[0]" = "SEQ_OPS_GPIO_DISABLE(0, 0)"
+
+				register "nvm_size" = "0x2000"
+				register "nvm_pagesize" = "1"
+				register "nvm_readonly" = "1"
+				register "nvm_width" = "0x10"
+				register "nvm_compat" = ""atmel,24c08""
+
+				device i2c 50 on
+				end
+			end
+		end
+		device ref i2c5 on
+			chip drivers/i2c/generic
+				register "hid" = ""ELAN0000""
+				register "desc" = ""ELAN Touchpad""
+				register "irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_F14_IRQ)"
+				register "wake" = "GPE0_DW2_14"
+				register "detect" = "1"
+				device i2c 15 on end
+			end
+			chip drivers/i2c/hid
+				register "generic.hid" = ""SYNA0000""
+				register "generic.cid" = ""ACPI0C50""
+				register "generic.desc" = ""Synaptics Touchpad""
+				register "generic.irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_F14_IRQ)"
+				register "generic.wake" = "GPE0_DW2_14"
+				register "generic.detect" = "1"
+				register "hid_desc_reg_offset" = "0x20"
+				device i2c 0x2c on end
+			end
+			chip drivers/i2c/hid
+				register "generic.hid" = ""FCAL0000""
+				register "generic.cid" = ""ACPI0C50""
+				register "generic.desc" = ""Focal Touchpad""
+				register "generic.irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_F14_IRQ)"
+				register "generic.wake" = "GPE0_DW2_14"
+				register "generic.detect" = "1"
+				register "hid_desc_reg_offset" = "0x20"
+				device i2c 0x38 on end
+			end
+		end
+		device ref ish on
+			chip drivers/intel/ish
+				register "add_acpi_dma_property" = "true"
+				device generic 0 on end
+			end
+		end
+		device ref ufs on end
+		device ref igpu on
+		end
+		device ref pcie_rp4 on
+			# PCIe 4 WLAN
+			register "pch_pcie_rp[PCH_RP(4)]" = "{
+				.clk_src = 2,
+				.clk_req = 2,
+				.flags = PCIE_RP_LTR | PCIE_RP_AER,
+			}"
+			chip drivers/wifi/generic
+				register "wake" = "GPE0_DW1_03"
+				register "add_acpi_dma_property" = "true"
+				device pci 00.0 on end
+			end
+		end
+		device ref pcie_rp7 on
+			# Enable SD Card PCIE 7 using clk 3
+			register "pch_pcie_rp[PCH_RP(7)]" = "{
+				.clk_src = 3,
+				.clk_req = 3,
+				.flags = PCIE_RP_HOTPLUG | PCIE_RP_LTR | PCIE_RP_AER,
+			}"
+			chip soc/intel/common/block/pcie/rtd3
+				register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_H13)"
+				register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_H12)"
+				register "srcclk_pin" = "3"
+				device generic 0 on end
+			end
+		end	#PCIE7 SD card
+		device ref pch_espi on
+			chip ec/google/chromeec
+				use conn0 as mux_conn[0]
+				device pnp 0c09.0 on end
+			end
+		end
+		device ref pmc hidden
+			chip drivers/intel/pmc_mux
+				device generic 0 on
+					chip drivers/intel/pmc_mux/conn
+						use usb2_port1 as usb2_port
+						use tcss_usb3_port1 as usb3_port
+						device generic 0 alias conn0 on end
+					end
+				end
+			end
+		end
+		device ref tcss_xhci on
+			chip drivers/usb/acpi
+				device ref tcss_root_hub on
+					chip drivers/usb/acpi
+						register "desc" = ""USB3 Type-C Port C0 (MLB)""
+						register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
+						register "use_custom_pld" = "true"
+						register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(1, 1))"
+						device ref tcss_usb3_port1 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB3 Type-C Port C1 (MLB)""
+						register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
+						register "use_custom_pld" = "true"
+						register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, LEFT, ACPI_PLD_GROUP(2, 1))"
+						device ref tcss_usb3_port2 on end
+					end
+				end
+			end
+		end
+		device ref xhci on
+			chip drivers/usb/acpi
+				device ref xhci_root_hub on
+					chip drivers/usb/acpi
+						register "desc" = ""USB2 Type-C Port C0 (MLB)""
+						register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
+						register "use_custom_pld" = "true"
+						register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(1, 1))"
+						device ref usb2_port1 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB2 Type-C Port C1 (MLB)""
+						register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
+						register "use_custom_pld" = "true"
+						register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, LEFT, ACPI_PLD_GROUP(2, 1))"
+						device ref usb2_port2 on end
+
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB2 Type-A Port A1 (DB)""
+						register "type" = "UPC_TYPE_A"
+						register "use_custom_pld" = "true"
+						register "custom_pld" = "ACPI_PLD_TYPE_A(RIGHT, LEFT, ACPI_PLD_GROUP(4, 1))"
+						device ref usb2_port4 on end
+					end
+
+					chip drivers/usb/acpi
+						register "desc" = ""USB2 WWAN""
+						register "type" = "UPC_TYPE_INTERNAL"
+						device ref usb2_port5 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB2 UFC""
+						register "type" = "UPC_TYPE_INTERNAL"
+						device ref usb2_port6 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB2 WFC""
+						register "type" = "UPC_TYPE_INTERNAL"
+						device ref usb2_port7 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB2 Bluetooth""
+						register "type" = "UPC_TYPE_INTERNAL"
+						register "reset_gpio" =
+							"ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D4)"
+						device ref usb2_port8 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""CNVi Bluetooth""
+						register "type" = "UPC_TYPE_INTERNAL"
+						register "reset_gpio" =
+							"ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D4)"
+						device ref usb2_port10 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB3 Type-A Port A1 (DB)""
+						register "type" = "UPC_TYPE_USB3_A"
+						register "use_custom_pld" = "true"
+						register "custom_pld" = "ACPI_PLD_TYPE_A(RIGHT, LEFT, ACPI_PLD_GROUP(4, 1))"
+						device ref usb3_port2 on end
+					end
+				end
+			end
+		end
+		device ref hda on
+			chip drivers/sof
+				register "spkr_tplg" = "max98360a"
+				register "jack_tplg" = "nau8825"
+				register "mic_tplg" = "_4ch"
+				device generic 0 on end
+			end
+		end
+		device ref gspi1 on
+			chip drivers/spi/acpi
+				register "name" = ""CRFP""
+				register "hid" = "ACPI_DT_NAMESPACE_HID"
+				register "uid" = "1"
+				register "compat_string" = ""google,cros-ec-spi""
+				register "irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_F15_IRQ)"
+				register "wake" = "GPE0_DW2_15"
+				register "has_power_resource" = "1"
+				register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_E7)"
+				register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D2)"
+				register "enable_delay_ms" = "3"
+				device spi 0 on
+				end
+			end # FPMCU
+		end
+	end
+end
diff --git a/src/mainboard/google/brya/variants/pujjolo/variant.c b/src/mainboard/google/brya/variants/pujjolo/variant.c
new file mode 100644
index 0000000000..e92119ae8c
--- /dev/null
+++ b/src/mainboard/google/brya/variants/pujjolo/variant.c
@@ -0,0 +1,19 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <baseboard/variants.h>
+#include <chip.h>
+#include <fw_config.h>
+#include <soc/gpio_soc_defs.h>
+#include <intelblocks/graphics.h>
+#include <acpi/acpi.h>
+#include <acpi/acpigen.h>
+#include <variant/gpio.h>
+
+
+void variant_generate_s0ix_hook(enum s0ix_entry entry)
+{
+	if (entry == S0IX_ENTRY)
+		acpigen_soc_clear_tx_gpio(SLP_S0_FP_EN);
+	else if (entry == S0IX_EXIT)
+		acpigen_soc_set_tx_gpio(SLP_S0_FP_EN);
+}

From 9a60da5297ba8922be03e82dc8b186355cebfc3a Mon Sep 17 00:00:00 2001
From: Wentao Qin <qinwentao@huaqin.corp-partner.google.com>
Date: Fri, 7 Feb 2025 11:26:41 +0800
Subject: [PATCH 1037/3886] mb/google/skywalker: Enable ChromeOS EC

1. Configure ChromeOS EC.
2. Pass GPIO_EC_AP_INT_ODL to the payload.
3. Initialize SPI bus 0 for ChromeOS EC control.

BUG=b:391957745
BRANCH=none
TEST=check boot log

Signed-off-by: Wentao Qin <qinwentao@huaqin.corp-partner.google.com>
Change-Id: Id3d53dfa8e1fdee5f04f01197592d31fee146299
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87358
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/google/skywalker/Kconfig     | 10 ++++++++++
 src/mainboard/google/skywalker/bootblock.c |  2 ++
 src/mainboard/google/skywalker/chromeos.c  |  8 ++++++++
 src/mainboard/google/skywalker/gpio.h      |  4 ++++
 src/mainboard/google/skywalker/reset.c     |  5 ++++-
 5 files changed, 28 insertions(+), 1 deletion(-)

diff --git a/src/mainboard/google/skywalker/Kconfig b/src/mainboard/google/skywalker/Kconfig
index cf9c69f9b5..ddc20e20f3 100644
--- a/src/mainboard/google/skywalker/Kconfig
+++ b/src/mainboard/google/skywalker/Kconfig
@@ -9,6 +9,7 @@ config BOARD_GOOGLE_SKYWALKER_COMMON
 if BOARD_GOOGLE_SKYWALKER_COMMON
 
 config VBOOT
+	select EC_GOOGLE_CHROMEEC_SWITCHES
 	select VBOOT_VBNV_FLASH
 	select VBOOT_NO_BOARD_SUPPORT
 	select VBOOT_MOCK_SECDATA
@@ -18,9 +19,13 @@ config BOARD_SPECIFIC_OPTIONS
 	select SOC_MEDIATEK_MT8189
 	select BOARD_ROMSIZE_KB_8192
 	select MAINBOARD_HAS_CHROMEOS
+	select CHROMEOS_USE_EC_WATCHDOG_FLAG if CHROMEOS
 	select COMMON_CBFS_SPI_WRAPPER
 	select SPI_FLASH
 	select SPI_FLASH_INCLUDE_ALL_DRIVERS
+	select EC_GOOGLE_CHROMEEC
+	select EC_GOOGLE_CHROMEEC_BOARDID
+	select EC_GOOGLE_CHROMEEC_SPI
 
 config MAINBOARD_DIR
 	string
@@ -35,4 +40,9 @@ config MAINBOARD_PART_NUMBER
 config BOOT_DEVICE_SPI_FLASH_BUS
 	int
 	default 7
+
+config EC_GOOGLE_CHROMEEC_SPI_BUS
+	hex
+	default 0x0
+
 endif
diff --git a/src/mainboard/google/skywalker/bootblock.c b/src/mainboard/google/skywalker/bootblock.c
index 71c3dfc418..b090924b77 100644
--- a/src/mainboard/google/skywalker/bootblock.c
+++ b/src/mainboard/google/skywalker/bootblock.c
@@ -13,6 +13,8 @@ static void usb3_hub_reset(void)
 
 void bootblock_mainboard_init(void)
 {
+	mtk_spi_init(CONFIG_EC_GOOGLE_CHROMEEC_SPI_BUS, SPI_PAD0_MASK, 3 * MHz, 0);
 	mtk_snfc_init();
 	usb3_hub_reset();
+	setup_chromeos_gpios();
 }
diff --git a/src/mainboard/google/skywalker/chromeos.c b/src/mainboard/google/skywalker/chromeos.c
index b779fe7bce..79b5d42b90 100644
--- a/src/mainboard/google/skywalker/chromeos.c
+++ b/src/mainboard/google/skywalker/chromeos.c
@@ -1,14 +1,22 @@
 /* SPDX-License-Identifier: GPL-2.0-only OR MIT */
 
 #include <boot/coreboot_tables.h>
+#include <ec/google/chromeec/ec.h>
 #include <gpio.h>
 
 #include "gpio.h"
 
+void setup_chromeos_gpios(void)
+{
+	gpio_input(GPIO_EC_AP_INT_ODL);
+	gpio_output(GPIO_AP_EC_WARM_RST_REQ, 0);
+}
+
 void fill_lb_gpios(struct lb_gpios *gpios)
 {
 	struct lb_gpio chromeos_gpios[] = {
 		{GPIO_XHCI_INIT_DONE.id, ACTIVE_HIGH, -1, "XHCI init done"},
+		{GPIO_EC_AP_INT_ODL.id, ACTIVE_LOW, -1, "EC interrupt"},
 	};
 	lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios));
 }
diff --git a/src/mainboard/google/skywalker/gpio.h b/src/mainboard/google/skywalker/gpio.h
index 74d9b04154..da1622edc0 100644
--- a/src/mainboard/google/skywalker/gpio.h
+++ b/src/mainboard/google/skywalker/gpio.h
@@ -7,5 +7,9 @@
 
 #define GPIO_XHCI_INIT_DONE	GPIO(GBE_MDC)
 #define GPIO_USB3_HUB_RST_L	GPIO(GPIO07)
+#define GPIO_EC_AP_INT_ODL	GPIO(GBE_MDIO)
+#define GPIO_AP_EC_WARM_RST_REQ	GPIO(GBE_AUX_PPS0)
+
+void setup_chromeos_gpios(void);
 
 #endif
diff --git a/src/mainboard/google/skywalker/reset.c b/src/mainboard/google/skywalker/reset.c
index 1a4b15682b..e50cf3bbfa 100644
--- a/src/mainboard/google/skywalker/reset.c
+++ b/src/mainboard/google/skywalker/reset.c
@@ -1,8 +1,11 @@
 /* SPDX-License-Identifier: GPL-2.0-only OR MIT */
 
+#include <gpio.h>
 #include <reset.h>
 
+#include "gpio.h"
+
 void do_board_reset(void)
 {
-	/* TODO: add reset function when gpio is ready */
+	gpio_output(GPIO_AP_EC_WARM_RST_REQ, 1);
 }

From be675e536991a1065fbac456d16c0dc57ae5da73 Mon Sep 17 00:00:00 2001
From: Vince Liu <vince-wl.liu@mediatek.corp-partner.google.com>
Date: Tue, 13 May 2025 18:10:21 +0800
Subject: [PATCH 1038/3886] mb/google/skywalker: Configure GPIO XHCI_INIT_DONE
 as output

Configure GPIO XHCI_INIT_DONE as output, so that payloads (for example
depthcharge) can assert it to notify EC to enable USB VBUS.

BUG=b:379008996
BRANCH=none
TEST=build passed

Signed-off-by: Vince Liu <vince-wl.liu@mediatek.corp-partner.google.com>
Change-Id: I054dad3783b7fd3c9b00003de9c3333759b8e44a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87657
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/google/skywalker/chromeos.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/src/mainboard/google/skywalker/chromeos.c b/src/mainboard/google/skywalker/chromeos.c
index 79b5d42b90..6c7aca8917 100644
--- a/src/mainboard/google/skywalker/chromeos.c
+++ b/src/mainboard/google/skywalker/chromeos.c
@@ -10,6 +10,7 @@ void setup_chromeos_gpios(void)
 {
 	gpio_input(GPIO_EC_AP_INT_ODL);
 	gpio_output(GPIO_AP_EC_WARM_RST_REQ, 0);
+	gpio_output(GPIO_XHCI_INIT_DONE, 0);
 }
 
 void fill_lb_gpios(struct lb_gpios *gpios)

From aaf373c2531426344015ff3ed971b2c9cb3cec6e Mon Sep 17 00:00:00 2001
From: Wentao Qin <qinwentao@huaqin.corp-partner.google.com>
Date: Mon, 10 Feb 2025 19:36:48 +0800
Subject: [PATCH 1039/3886] mb/google/skywalker: Implement sku_id()

Retrieve the SKU ID for Skywalker via CBI interface.

BUG=b:395551181
BRANCH=none
TEST=check boot log

Signed-off-by: Wentao Qin <qinwentao@huaqin.corp-partner.google.com>
Change-Id: I6f1343f127537f97bfa4e1f2cfef7db5d46fab67
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87359
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/google/skywalker/Kconfig     |  2 ++
 src/mainboard/google/skywalker/Makefile.mk |  1 +
 src/mainboard/google/skywalker/boardid.c   | 23 ++++++++++++++++++++++
 3 files changed, 26 insertions(+)
 create mode 100644 src/mainboard/google/skywalker/boardid.c

diff --git a/src/mainboard/google/skywalker/Kconfig b/src/mainboard/google/skywalker/Kconfig
index ddc20e20f3..a05f4bbdd6 100644
--- a/src/mainboard/google/skywalker/Kconfig
+++ b/src/mainboard/google/skywalker/Kconfig
@@ -26,6 +26,8 @@ config BOARD_SPECIFIC_OPTIONS
 	select EC_GOOGLE_CHROMEEC
 	select EC_GOOGLE_CHROMEEC_BOARDID
 	select EC_GOOGLE_CHROMEEC_SPI
+	select FW_CONFIG
+	select FW_CONFIG_SOURCE_CHROMEEC_CBI
 
 config MAINBOARD_DIR
 	string
diff --git a/src/mainboard/google/skywalker/Makefile.mk b/src/mainboard/google/skywalker/Makefile.mk
index c2ff8f6cb7..6c863fe287 100644
--- a/src/mainboard/google/skywalker/Makefile.mk
+++ b/src/mainboard/google/skywalker/Makefile.mk
@@ -8,4 +8,5 @@ bootblock-y += bootblock.c
 
 romstage-y += romstage.c
 
+ramstage-y += boardid.c
 ramstage-y += mainboard.c
diff --git a/src/mainboard/google/skywalker/boardid.c b/src/mainboard/google/skywalker/boardid.c
new file mode 100644
index 0000000000..cfac4d5d4d
--- /dev/null
+++ b/src/mainboard/google/skywalker/boardid.c
@@ -0,0 +1,23 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <boardid.h>
+#include <console/console.h>
+#include <ec/google/chromeec/ec.h>
+
+uint32_t sku_id(void)
+{
+	static uint32_t cached_sku_code = BOARD_ID_INIT;
+
+	if (cached_sku_code == BOARD_ID_INIT) {
+		cached_sku_code = google_chromeec_get_board_sku();
+
+		if (cached_sku_code == CROS_SKU_UNKNOWN ||
+		    cached_sku_code == CROS_SKU_UNPROVISIONED) {
+			printk(BIOS_WARNING, "Failed to get SKU code from EC\n");
+			cached_sku_code = CROS_SKU_UNPROVISIONED;
+		}
+		printk(BIOS_DEBUG, "SKU Code: %#02x\n", cached_sku_code);
+	}
+
+	return cached_sku_code;
+}

From 65523e98a6700dc9c590fcdb49748a47079661bf Mon Sep 17 00:00:00 2001
From: Yu-Ping Wu <yupingso@chromium.org>
Date: Wed, 14 May 2025 17:53:25 +0800
Subject: [PATCH 1040/3886] soc/mediatek: Extract DPM common code

Move function declarations to dpm_common.h, which is shared for both
dpm_v1 and dpm_v2. Add a new function dpm_init_mcu() to the header to
reduce duplicate code in dpm_v1.c, dpm_v2.c and dpm_4ch.c.

BUG=none
TEST=emerge-skywalker coreboot
BRANCH=none

Change-Id: I8d6318e9c3c4570cb8f3ff64242fc414770db653
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87667
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
---
 src/soc/mediatek/common/dpm.c                 | 21 +++++++++++++++++++
 src/soc/mediatek/common/dpm_4ch.c             | 15 ++-----------
 src/soc/mediatek/common/dpm_v1.c              | 14 +++----------
 src/soc/mediatek/common/dpm_v2.c              | 13 +++---------
 .../mediatek/common/include/soc/dpm_common.h  | 15 +++++++++++++
 src/soc/mediatek/common/include/soc/dpm_v1.h  |  7 +------
 src/soc/mediatek/common/include/soc/dpm_v2.h  |  5 +----
 src/soc/mediatek/mt8188/Makefile.mk           |  1 +
 src/soc/mediatek/mt8192/Makefile.mk           |  1 +
 src/soc/mediatek/mt8195/Makefile.mk           |  1 +
 src/soc/mediatek/mt8196/Makefile.mk           |  1 +
 11 files changed, 50 insertions(+), 44 deletions(-)
 create mode 100644 src/soc/mediatek/common/dpm.c
 create mode 100644 src/soc/mediatek/common/include/soc/dpm_common.h

diff --git a/src/soc/mediatek/common/dpm.c b/src/soc/mediatek/common/dpm.c
new file mode 100644
index 0000000000..5a2c6e9d9a
--- /dev/null
+++ b/src/soc/mediatek/common/dpm.c
@@ -0,0 +1,21 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <soc/dpm_common.h>
+#include <soc/mcu_common.h>
+#include <soc/symbols.h>
+
+int dpm_init_mcu(struct mtk_mcu *mcu_list)
+{
+	struct mtk_mcu *mcu = mcu_list;
+
+	while (mcu->firmware_name) {
+		mcu->load_buffer = _dram_dma;
+		mcu->buffer_size = REGION_SIZE(dram_dma);
+		if (mtk_init_mcu(mcu))
+			return -1;
+
+		mcu++;
+	}
+
+	return 0;
+}
diff --git a/src/soc/mediatek/common/dpm_4ch.c b/src/soc/mediatek/common/dpm_4ch.c
index 6b15411300..e4be08b08a 100644
--- a/src/soc/mediatek/common/dpm_4ch.c
+++ b/src/soc/mediatek/common/dpm_4ch.c
@@ -6,7 +6,6 @@
 #include <soc/dpm_v1.h>
 #include <soc/dramc_soc.h>
 #include <soc/spm.h>
-#include <soc/symbols.h>
 
 static struct dpm_regs *const mtk_dpm2 = (void *)DPM_CFG_BASE2;
 
@@ -62,6 +61,7 @@ static struct mtk_mcu dpm_mcu_4ch[] = {
 		.priv = mtk_dpm2,
 		.reset = dpm_reset,
 	},
+	{},
 };
 
 int dpm_4ch_init(void)
@@ -74,16 +74,5 @@ int dpm_4ch_init(void)
 
 int dpm_4ch_para_setting(void)
 {
-	int i;
-	struct mtk_mcu *dpm;
-
-	for (i = 0; i < ARRAY_SIZE(dpm_mcu_4ch); i++) {
-		dpm = &dpm_mcu_4ch[i];
-		dpm->load_buffer = _dram_dma;
-		dpm->buffer_size = REGION_SIZE(dram_dma);
-		if (mtk_init_mcu(dpm))
-			return -1;
-	}
-
-	return 0;
+	return dpm_init_mcu(dpm_mcu_4ch);
 }
diff --git a/src/soc/mediatek/common/dpm_v1.c b/src/soc/mediatek/common/dpm_v1.c
index 4691b35569..d059d02a80 100644
--- a/src/soc/mediatek/common/dpm_v1.c
+++ b/src/soc/mediatek/common/dpm_v1.c
@@ -3,7 +3,6 @@
 #include <device/mmio.h>
 #include <soc/dpm_v1.h>
 #include <soc/mcu_common.h>
-#include <soc/symbols.h>
 
 static struct mtk_mcu dpm_mcu[] = {
 	{
@@ -16,6 +15,7 @@ static struct mtk_mcu dpm_mcu[] = {
 		.priv = mtk_dpm,
 		.reset = dpm_reset,
 	},
+	{},
 };
 
 void dpm_reset(struct mtk_mcu *mcu)
@@ -32,9 +32,6 @@ void dpm_reset(struct mtk_mcu *mcu)
 
 int dpm_init(void)
 {
-	int i;
-	struct mtk_mcu *dpm;
-
 	if (CONFIG(DPM_FOUR_CHANNEL))
 		if (dpm_4ch_init())
 			return -1;
@@ -42,13 +39,8 @@ int dpm_init(void)
 	/* config DPM SRAM layout */
 	clrsetbits32(&mtk_dpm->sw_rstn, DPM_MEM_RATIO_MASK, DPM_MEM_RATIO_CFG1);
 
-	for (i = 0; i < ARRAY_SIZE(dpm_mcu); i++) {
-		dpm = &dpm_mcu[i];
-		dpm->load_buffer = _dram_dma;
-		dpm->buffer_size = REGION_SIZE(dram_dma);
-		if (mtk_init_mcu(dpm))
-			return -1;
-	}
+	if (dpm_init_mcu(dpm_mcu))
+		return -1;
 
 	if (CONFIG(DPM_FOUR_CHANNEL))
 		if (dpm_4ch_para_setting())
diff --git a/src/soc/mediatek/common/dpm_v2.c b/src/soc/mediatek/common/dpm_v2.c
index b0f0dbcb88..4df8bd0e13 100644
--- a/src/soc/mediatek/common/dpm_v2.c
+++ b/src/soc/mediatek/common/dpm_v2.c
@@ -3,7 +3,6 @@
 #include <device/mmio.h>
 #include <soc/dpm_v2.h>
 #include <soc/mcu_common.h>
-#include <soc/symbols.h>
 
 static struct mtk_mcu dpm_mcu[] = {
 	{
@@ -15,6 +14,7 @@ static struct mtk_mcu dpm_mcu[] = {
 		.run_address = (void *)DPM_PM_SRAM_BASE,
 		.reset = dpm_reset,
 	},
+	{},
 };
 
 void dpm_reset(struct mtk_mcu *mcu)
@@ -25,19 +25,12 @@ void dpm_reset(struct mtk_mcu *mcu)
 
 int dpm_init(void)
 {
-	int i;
-	struct mtk_mcu *dpm;
 	u32 dramc_wbr_backup = read32p(DRAMC_WBR);
 
 	setbits32p(DRAMC_WBR, ENABLE_DRAMC_WBR_MASK);
 
-	for (i = 0; i < ARRAY_SIZE(dpm_mcu); i++) {
-		dpm = &dpm_mcu[i];
-		dpm->load_buffer = _dram_dma;
-		dpm->buffer_size = REGION_SIZE(dram_dma);
-		if (mtk_init_mcu(dpm))
-			return -1;
-	}
+	if (dpm_init_mcu(dpm_mcu))
+		return -1;
 
 	write32p(DRAMC_WBR, dramc_wbr_backup);
 
diff --git a/src/soc/mediatek/common/include/soc/dpm_common.h b/src/soc/mediatek/common/include/soc/dpm_common.h
new file mode 100644
index 0000000000..75833151fb
--- /dev/null
+++ b/src/soc/mediatek/common/include/soc/dpm_common.h
@@ -0,0 +1,15 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef __SOC_MEDIATEK_COMMON_DPM_COMMON_H__
+#define __SOC_MEDIATEK_COMMON_DPM_COMMON_H__
+
+#include <soc/mcu_common.h>
+
+void dpm_reset(struct mtk_mcu *mcu);
+int dpm_init_mcu(struct mtk_mcu *mcu_list);
+int dpm_init(void);
+
+int dpm_4ch_para_setting(void);
+int dpm_4ch_init(void);
+
+#endif  /* __SOC_MEDIATEK_COMMON_DPM_COMMON_H__ */
diff --git a/src/soc/mediatek/common/include/soc/dpm_v1.h b/src/soc/mediatek/common/include/soc/dpm_v1.h
index 65623a2671..0f23b5b36f 100644
--- a/src/soc/mediatek/common/include/soc/dpm_v1.h
+++ b/src/soc/mediatek/common/include/soc/dpm_v1.h
@@ -4,7 +4,7 @@
 #define __SOC_MEDIATEK_COMMON_DPM_V1_H__
 
 #include <soc/addressmap.h>
-#include <soc/mcu_common.h>
+#include <soc/dpm_common.h>
 #include <types.h>
 
 struct dpm_regs {
@@ -48,9 +48,4 @@ check_member(dpm_regs, status_4, 0x70B0);
 
 static struct dpm_regs *const mtk_dpm = (void *)DPM_CFG_BASE;
 
-void dpm_reset(struct mtk_mcu *mcu);
-int dpm_init(void);
-int dpm_4ch_para_setting(void);
-int dpm_4ch_init(void);
-
 #endif  /* __SOC_MEDIATEK_COMMON_DPM_V1_H__ */
diff --git a/src/soc/mediatek/common/include/soc/dpm_v2.h b/src/soc/mediatek/common/include/soc/dpm_v2.h
index c11a9bb2da..1588622d67 100644
--- a/src/soc/mediatek/common/include/soc/dpm_v2.h
+++ b/src/soc/mediatek/common/include/soc/dpm_v2.h
@@ -4,7 +4,7 @@
 #define __SOC_MEDIATEK_COMMON_DPM_V2_H__
 
 #include <soc/addressmap.h>
-#include <soc/mcu_common.h>
+#include <soc/dpm_common.h>
 
 #define DPM_RST_OFFSET		0x7074
 #define DPM_SW_RSTN		BIT(0)
@@ -16,7 +16,4 @@
 
 #define ENABLE_DRAMC_WBR_MASK	0x2ffff
 
-void dpm_reset(struct mtk_mcu *mcu);
-int dpm_init(void);
-
 #endif  /* __SOC_MEDIATEK_COMMON_DPM_V2_H__ */
diff --git a/src/soc/mediatek/mt8188/Makefile.mk b/src/soc/mediatek/mt8188/Makefile.mk
index e28c50d02e..3c77664cfc 100644
--- a/src/soc/mediatek/mt8188/Makefile.mk
+++ b/src/soc/mediatek/mt8188/Makefile.mk
@@ -41,6 +41,7 @@ ramstage-y += ../common/dfd.c
 ramstage-y += ../common/display.c
 ramstage-y += ../common/dp/dptx_common.c ../common/dp/dptx_hal_common.c
 ramstage-y += ../common/dp/dp_intf.c ../common/dp/dptx.c ../common/dp/dptx_hal.c dp_intf.c
+ramstage-y += ../common/dpm.c
 ramstage-y += ../common/dpm_v1.c
 ramstage-$(CONFIG_DPM_FOUR_CHANNEL) += ../common/dpm_4ch.c
 ramstage-y += ../common/dsi.c ../common/mtk_mipi_dphy.c
diff --git a/src/soc/mediatek/mt8192/Makefile.mk b/src/soc/mediatek/mt8192/Makefile.mk
index 90a4e6d807..a92584da0b 100644
--- a/src/soc/mediatek/mt8192/Makefile.mk
+++ b/src/soc/mediatek/mt8192/Makefile.mk
@@ -38,6 +38,7 @@ ramstage-$(CONFIG_ARM64_USE_ARM_TRUSTED_FIRMWARE) += ../common/bl31.c
 ramstage-y += ../common/ddp.c ddp.c
 ramstage-y += devapc.c
 ramstage-y += ../common/dfd.c
+ramstage-y += ../common/dpm.c
 ramstage-y += ../common/dpm_v1.c
 ramstage-y += ../common/dsi.c ../common/mtk_mipi_dphy.c
 ramstage-y += ../common/l2c_ops.c
diff --git a/src/soc/mediatek/mt8195/Makefile.mk b/src/soc/mediatek/mt8195/Makefile.mk
index 5e4e98f121..b960f8955b 100644
--- a/src/soc/mediatek/mt8195/Makefile.mk
+++ b/src/soc/mediatek/mt8195/Makefile.mk
@@ -48,6 +48,7 @@ ramstage-y += ../common/ddp.c ddp.c
 ramstage-y += ../common/devapc.c devapc.c
 ramstage-y += ../common/dfd.c
 ramstage-y += ../common/display.c
+ramstage-y += ../common/dpm.c
 ramstage-y += ../common/dpm_v1.c
 ramstage-$(CONFIG_DPM_FOUR_CHANNEL) += ../common/dpm_4ch.c
 ramstage-y += ../common/dp/dptx_common.c ../common/dp/dptx_hal_common.c
diff --git a/src/soc/mediatek/mt8196/Makefile.mk b/src/soc/mediatek/mt8196/Makefile.mk
index 5d6e1db74d..17c768fb37 100644
--- a/src/soc/mediatek/mt8196/Makefile.mk
+++ b/src/soc/mediatek/mt8196/Makefile.mk
@@ -58,6 +58,7 @@ ramstage-$(CONFIG_ARM64_USE_ARM_TRUSTED_FIRMWARE) += ../common/bl31.c
 ramstage-y += dcc.c
 ramstage-y += ddp.c
 ramstage-y += ../common/display.c
+ramstage-y += ../common/dpm.c
 ramstage-y += ../common/dpm_v2.c
 ramstage-y += ../common/dp/dptx_common.c ../common/dp/dptx_hal_common.c
 ramstage-y += dptx.c dptx_hal.c dp_intf.c

From 4e8ea210bb72682f05b803a2ff97446fbb3e4212 Mon Sep 17 00:00:00 2001
From: Tongtong Pan <pantongtong@huaqin.corp-partner.google.com>
Date: Wed, 14 May 2025 09:09:47 +0800
Subject: [PATCH 1041/3886] mb/google/fatcat/var/felino: Add pull high setting
 on GPP_C03/GPP_C04 in gpio.c

SMBUS_CLK0/DAT0 need to be pulled high on SOC Side according to schematics revision 20241120.
otherwise board cannot enter s0ix due to SMBUS blocking.

BUG=b:403383143
TEST=emerge-fatcat coreboot and machine can enter the s0ix state.

Change-Id: Iac4ca81601331ac35705a73c13ede8efb89ab370
Signed-off-by: Tongtong Pan <pantongtong@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87659
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
---
 src/mainboard/google/fatcat/variants/felino/gpio.c | 9 +++++----
 1 file changed, 5 insertions(+), 4 deletions(-)

diff --git a/src/mainboard/google/fatcat/variants/felino/gpio.c b/src/mainboard/google/fatcat/variants/felino/gpio.c
index 83c45bf54f..fd16fa6de5 100644
--- a/src/mainboard/google/fatcat/variants/felino/gpio.c
+++ b/src/mainboard/google/fatcat/variants/felino/gpio.c
@@ -106,10 +106,11 @@ static const struct pad_config gpio_table[] = {
 	PAD_NC(GPP_C01, NONE),
 	/* GPP_C02:     GPPC_C2_SMB_ALERT_N */
 	PAD_CFG_NF(GPP_C02, NONE, DEEP, NF1),
+	/* FIXME: b/417841162 */
 	/* GPP_C03:     SMBUS_CLK0 */
-	PAD_CFG_NF(GPP_C03, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_C03, UP_20K, DEEP, NF1),
 	/* GPP_C04:     SMBUS_DAT0 */
-	PAD_CFG_NF(GPP_C04, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_C04, UP_20K, DEEP, NF1),
 	/* GPP_C05:     GPPC_C5 */
 	PAD_NC(GPP_C05, NONE),
 	/* GPP_C06:     NC */
@@ -410,9 +411,9 @@ static const struct pad_config early_gpio_table[] = {
 /* Pad configuration in romstage */
 static const struct pad_config romstage_gpio_table[] = {
 	/* GPP_C03:     GPP_C0_SMBCLK */
-	PAD_CFG_NF(GPP_C03, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_C03, UP_20K, DEEP, NF1),
 	/* GPP_C04:     GPP_C0_SMBDATA */
-	PAD_CFG_NF(GPP_C04, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_C04, UP_20K, DEEP, NF1),
 };
 
 const struct pad_config *variant_gpio_table(size_t *num)

From e8450f78a02cf586b0fa453dcfa4d802d637ad9d Mon Sep 17 00:00:00 2001
From: Subrata Banik <subratabanik@google.com>
Date: Wed, 14 May 2025 14:54:03 +0000
Subject: [PATCH 1042/3886] mb/google/bluey: Make GPIO setups conditional on
 Kconfig options

The `EC_GOOGLE_CHROMEEC_SPI_BUS` Kconfig and the `GPIO_AP_EC_INT`
setup in `chromeos.c` are now dependent on `EC_GOOGLE_CHROMEEC`.

Similarly, the `MAINBOARD_GPIO_PIN_FOR_GSC_AP_INTERRUPT` Kconfig
and the `GPIO_GSC_AP_INT` setup are now dependent on `TPM_GOOGLE_TI50`.

This ensures that GPIOs are only configured if their respective
features are enabled, preventing potential issues when they are
disabled.

BUG=b:404985109
TEST=Able to build google/bluey.

Change-Id: I44525dd008c42c42aa7e5c4a4f290b09312ed269
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87674
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/google/bluey/Kconfig    |  2 ++
 src/mainboard/google/bluey/chromeos.c | 10 ++++++++--
 2 files changed, 10 insertions(+), 2 deletions(-)

diff --git a/src/mainboard/google/bluey/Kconfig b/src/mainboard/google/bluey/Kconfig
index 87cefb5483..f1e2648af6 100644
--- a/src/mainboard/google/bluey/Kconfig
+++ b/src/mainboard/google/bluey/Kconfig
@@ -83,10 +83,12 @@ config DRIVER_TPM_I2C_ADDR
 	default 0x50
 
 config EC_GOOGLE_CHROMEEC_SPI_BUS
+	depends on EC_GOOGLE_CHROMEEC
 	hex
 	default 0xb
 
 config MAINBOARD_GPIO_PIN_FOR_GSC_AP_INTERRUPT
+	depends on TPM_GOOGLE_TI50
 	int
 	default 34
 	help
diff --git a/src/mainboard/google/bluey/chromeos.c b/src/mainboard/google/bluey/chromeos.c
index 5dc73153b4..0f2b7da21f 100644
--- a/src/mainboard/google/bluey/chromeos.c
+++ b/src/mainboard/google/bluey/chromeos.c
@@ -7,9 +7,11 @@
 
 void setup_chromeos_gpios(void)
 {
-	gpio_input_pullup(GPIO_AP_EC_INT);
+	if (CONFIG(EC_GOOGLE_CHROMEEC))
+		gpio_input_pullup(GPIO_AP_EC_INT);
 
-	gpio_input_irq(GPIO_GSC_AP_INT, IRQ_TYPE_RISING_EDGE, GPIO_PULL_UP);
+	if (CONFIG(TPM_GOOGLE_TI50))
+		gpio_input_irq(GPIO_GSC_AP_INT, IRQ_TYPE_RISING_EDGE, GPIO_PULL_UP);
 
 	if (CONFIG(MAINBOARD_HAS_FINGERPRINT)) {
 		gpio_output(GPIO_FP_RST_L, 0);
@@ -28,10 +30,14 @@ void fill_lb_gpios(struct lb_gpios *gpios)
 {
 	/* TODO: Add required GPIO after referring to the schematics */
 	const struct lb_gpio chromeos_gpios[] = {
+#if CONFIG(EC_GOOGLE_CHROMEEC)
 		{GPIO_AP_EC_INT.addr, ACTIVE_LOW, gpio_get(GPIO_AP_EC_INT),
 			"EC interrupt"},
+#endif
+#if CONFIG(TPM_GOOGLE_TI50)
 		{GPIO_GSC_AP_INT.addr, ACTIVE_HIGH, gpio_get(GPIO_GSC_AP_INT),
 			"TPM interrupt"},
+#endif
 		{GPIO_SNDW_AMP_0_ENABLE.addr, ACTIVE_HIGH, gpio_get(GPIO_SNDW_AMP_0_ENABLE),
 			"Speaker 0 enable"},
 		{GPIO_SNDW_AMP_1_ENABLE.addr, ACTIVE_HIGH, gpio_get(GPIO_SNDW_AMP_1_ENABLE),

From f9d933db36f67ac4f1e86e83b64f96396933ef7c Mon Sep 17 00:00:00 2001
From: Subrata Banik <subratabanik@google.com>
Date: Wed, 14 May 2025 15:43:42 +0000
Subject: [PATCH 1043/3886] mb/google/bluey: Introduce MAINBOARD_HAS_GOOGLE_TPM
 Kconfig

This commit introduces a new Kconfig option `MAINBOARD_HAS_GOOGLE_TPM`
for the Bluey mainboard.

Previously, `I2C_TPM`, `MAINBOARD_HAS_TPM2`, and `TPM_GOOGLE_TI50`
were unconditionally selected within `BOARD_GOOGLE_BLUEY_COMMON`.
These selections are now moved under the new `MAINBOARD_HAS_GOOGLE_TPM`
boolean option, which defaults to disabled.

This change allows for more granular control over enabling Google TPM
(aka GSC) support, making it optional for Bluey configurations.

As Bluey (Qualcomm CRD) lacks a Google TPM (GSC), the new
`MAINBOARD_HAS_GOOGLE_TPM` option defaults to 'n'. This ensures
GSC-related features (including `I2C_TPM`, `MAINBOARD_HAS_TPM2`,
and `TPM_GOOGLE_TI50`) are not selected by default for Bluey,
aligning the Kconfig with the hardware capabilities.

BUG=b:404985109
TEST=Able to build google/bluey. Ensure `VBOOT_MOCK_SECDATA` Kconfig
is default enabled for Bluey.

Change-Id: Idc3d998bfc5a747a3068e87fd2f503190a0c1f3f
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87676
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
---
 src/mainboard/google/bluey/Kconfig | 12 +++++++++---
 1 file changed, 9 insertions(+), 3 deletions(-)

diff --git a/src/mainboard/google/bluey/Kconfig b/src/mainboard/google/bluey/Kconfig
index f1e2648af6..059708fbd0 100644
--- a/src/mainboard/google/bluey/Kconfig
+++ b/src/mainboard/google/bluey/Kconfig
@@ -7,9 +7,7 @@ config BOARD_GOOGLE_BLUEY_COMMON
 	select EC_GOOGLE_CHROMEEC
 	select EC_GOOGLE_CHROMEEC_RTC
 	select EC_GOOGLE_CHROMEEC_SPI
-	select I2C_TPM
 	select MAINBOARD_HAS_CHROMEOS
-	select MAINBOARD_HAS_TPM2
 	select RTC
 	select SOC_QUALCOMM_X1P42100
 	select SPI_FLASH
@@ -17,7 +15,6 @@ config BOARD_GOOGLE_BLUEY_COMMON
 	select SPI_FLASH_GIGADEVICE
 	select SPI_FLASH_MACRONIX
 	select SPI_FLASH_WINBOND
-	select TPM_GOOGLE_TI50
 
 config BOARD_GOOGLE_BASEBOARD_BLUEY
 	def_bool n
@@ -59,6 +56,15 @@ config MAINBOARD_HAS_SD_CONTROLLER
 	help
 	  Enable this option if your mainboard is equipped with SD card controller.
 
+config MAINBOARD_HAS_GOOGLE_TPM
+	bool
+	default n
+	select I2C_TPM
+	select MAINBOARD_HAS_TPM2
+	select TPM_GOOGLE_TI50
+	help
+	  Enable this option if your mainboard is equipped with Google TPM aka GSC.
+
 config MAINBOARD_VENDOR
 	string
 	default "Google"

From 139a5b6fe038f7dfbd03bd9d0745b8fb6f9f9dad Mon Sep 17 00:00:00 2001
From: Subrata Banik <subratabanik@google.com>
Date: Wed, 14 May 2025 18:16:03 +0000
Subject: [PATCH 1044/3886] mb/google/bluey: Select MISSING_BOARD_RESET due to
 lack of Chrome EC

The Bluey board configuration (`BOARD_GOOGLE_BLUEY`) now selects
`MISSING_BOARD_RESET`.

This change is necessary because Bluey does not have a Chrome EC.
Without a Chrome EC, a board-specific `do_board_reset()`
implementation, which often handles system shutdown or reset sequences
by interacting with an EC, is not feasible for Bluey.

As a result of selecting `MISSING_BOARD_RESET`:
- Bluey's `reset.c` is no longer compiled.
- If a board reset is triggered, the system will use the stub
  `do_board_reset()` provided when `CONFIG_MISSING_BOARD_RESET`
  is enabled.

This aligns Bluey's configuration with its hardware capabilities
regarding system reset.

BUG=b:404985109
TEST=Able to build google/bluey.

Change-Id: I2f770ce9e96544b7e1891a3d8ec84a1313210891
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87677
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/google/bluey/Kconfig     | 1 +
 src/mainboard/google/bluey/Makefile.mk | 2 ++
 2 files changed, 3 insertions(+)

diff --git a/src/mainboard/google/bluey/Kconfig b/src/mainboard/google/bluey/Kconfig
index 059708fbd0..eb1499548b 100644
--- a/src/mainboard/google/bluey/Kconfig
+++ b/src/mainboard/google/bluey/Kconfig
@@ -23,6 +23,7 @@ config BOARD_GOOGLE_BASEBOARD_BLUEY
 config BOARD_GOOGLE_BLUEY
 	select BOARD_GOOGLE_BASEBOARD_BLUEY
 	select MAINBOARD_HAS_FINGERPRINT_VIA_USB
+	select MISSING_BOARD_RESET
 
 if BOARD_GOOGLE_BLUEY_COMMON
 
diff --git a/src/mainboard/google/bluey/Makefile.mk b/src/mainboard/google/bluey/Makefile.mk
index 553634c29c..6018c9152a 100644
--- a/src/mainboard/google/bluey/Makefile.mk
+++ b/src/mainboard/google/bluey/Makefile.mk
@@ -2,7 +2,9 @@
 
 all-y += boardid.c
 all-y += chromeos.c
+ifneq ($(CONFIG_MISSING_BOARD_RESET),y)
 all-y += reset.c
+endif
 
 bootblock-y += bootblock.c
 

From 47c171a1579f1a05197764da6db5598076254184 Mon Sep 17 00:00:00 2001
From: Subrata Banik <subratabanik@google.com>
Date: Wed, 14 May 2025 18:28:25 +0000
Subject: [PATCH 1045/3886] mb/google/bluey: Make Chrome EC optional

Bluey does not have a Chrome EC. This commit adjusts Kconfig settings
and related code to correctly reflect this hardware characteristic,
ensuring Bluey builds and operates appropriately without an EC.

Key changes:

1. Chrome EC Kconfig Optionalized:
   - Unconditional selections for `EC_GOOGLE_CHROMEEC`,
     `EC_GOOGLE_CHROMEEC_RTC`, `EC_GOOGLE_CHROMEEC_SPI`,
     `EC_GOOGLE_CHROMEEC_SWITCHES` (previously selected via `VBOOT`),
     and `RTC` have been removed from `BOARD_GOOGLE_BLUEY_COMMON`.
   - These are now grouped under a new Kconfig option
     `MAINBOARD_HAS_CHROME_EC` (default 'n'). This ensures
     EC-related features/APIs are off by default for Bluey.

2. VBoot Adaptation for no-EC:
   - `BOARD_GOOGLE_BLUEY` now selects `VBOOT_NO_BOARD_SUPPORT`.
   - VBoot relies on board functions (e.g. WP/recovery switches)
     often via an EC. `VBOOT_NO_BOARD_SUPPORT` provides stubs
     when an EC is absent, allowing vboot to link.

3. Conditional EC Reset Logic:
   - `reset.c`: `do_board_reset()` now calls `google_chromeec_reboot()`
     only if `CONFIG(EC_GOOGLE_CHROMEEC)` is enabled. This prevents
     errors if called when the EC is not configured.
   - (Note: Bluey typically selects `MISSING_BOARD_RESET`, so
     `reset.c` may not compile. This change makes `reset.c` safer if
     used in a no-EC setup without `MISSING_BOARD_RESET`.)

These modifications ensure that Bluey's firmware configuration aligns
with its actual hardware capabilities, specifically its lack of a
Chrome EC.

BUG=b:404985109
TEST=Able to build google/bluey.

Change-Id: Ibee39d76845ce6d9242ade9eacfdb9a8a655c05f
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87678
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/google/bluey/Kconfig | 17 ++++++++++++-----
 src/mainboard/google/bluey/reset.c |  3 ++-
 2 files changed, 14 insertions(+), 6 deletions(-)

diff --git a/src/mainboard/google/bluey/Kconfig b/src/mainboard/google/bluey/Kconfig
index eb1499548b..d23c66bf18 100644
--- a/src/mainboard/google/bluey/Kconfig
+++ b/src/mainboard/google/bluey/Kconfig
@@ -4,11 +4,7 @@ config BOARD_GOOGLE_BLUEY_COMMON
 	def_bool n
 	select BOARD_ROMSIZE_KB_8192
 	select COMMON_CBFS_SPI_WRAPPER
-	select EC_GOOGLE_CHROMEEC
-	select EC_GOOGLE_CHROMEEC_RTC
-	select EC_GOOGLE_CHROMEEC_SPI
 	select MAINBOARD_HAS_CHROMEOS
-	select RTC
 	select SOC_QUALCOMM_X1P42100
 	select SPI_FLASH
 	select SPI_FLASH_EXIT_4_BYTE_ADDR_MODE
@@ -66,12 +62,23 @@ config MAINBOARD_HAS_GOOGLE_TPM
 	help
 	  Enable this option if your mainboard is equipped with Google TPM aka GSC.
 
+config MAINBOARD_HAS_CHROME_EC
+	bool
+	default n
+	select EC_GOOGLE_CHROMEEC
+	select EC_GOOGLE_CHROMEEC_RTC
+	select EC_GOOGLE_CHROMEEC_SPI
+	select EC_GOOGLE_CHROMEEC_SWITCHES
+	select RTC
+	help
+	  Enable this option if your mainboard is equipped with Chrome EC.
+
 config MAINBOARD_VENDOR
 	string
 	default "Google"
 
 config VBOOT
-	select EC_GOOGLE_CHROMEEC_SWITCHES
+	select VBOOT_NO_BOARD_SUPPORT if BOARD_GOOGLE_BLUEY
 	select VBOOT_VBNV_FLASH
 
 ##########################################################
diff --git a/src/mainboard/google/bluey/reset.c b/src/mainboard/google/bluey/reset.c
index d64c650b99..b10e4d481a 100644
--- a/src/mainboard/google/bluey/reset.c
+++ b/src/mainboard/google/bluey/reset.c
@@ -7,5 +7,6 @@
    but this works well enough for our purposes. */
 void do_board_reset(void)
 {
-	google_chromeec_reboot(EC_REBOOT_COLD, 0);
+	if (CONFIG(EC_GOOGLE_CHROMEEC))
+		google_chromeec_reboot(EC_REBOOT_COLD, 0);
 }

From 276eb20b0450f7d40541e423bb6a0d4f26256084 Mon Sep 17 00:00:00 2001
From: Subrata Banik <subratabanik@google.com>
Date: Wed, 14 May 2025 18:38:06 +0000
Subject: [PATCH 1046/3886] mb/google/bluey: Limit SPI flash support to Winbond

Removed Kconfig selections for `SPI_FLASH_GIGADEVICE` and
`SPI_FLASH_MACRONIX` from `BOARD_GOOGLE_BLUEY_COMMON`.

This change aligns the configuration with hardware plans, as Bluey
is only intended to support Winbond SPI flash parts. Consequently,
support for GigaDevice and Macronix flash chips is removed.

The `SPI_FLASH_WINBOND` selection remains.

BUG=b:404985109
TEST=Able to build google/bluey.

Change-Id: Ib5f0d40e45f40e694e36cceade75f1f1ac0349c6
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87679
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/google/bluey/Kconfig | 2 --
 1 file changed, 2 deletions(-)

diff --git a/src/mainboard/google/bluey/Kconfig b/src/mainboard/google/bluey/Kconfig
index d23c66bf18..765f3cbc50 100644
--- a/src/mainboard/google/bluey/Kconfig
+++ b/src/mainboard/google/bluey/Kconfig
@@ -8,8 +8,6 @@ config BOARD_GOOGLE_BLUEY_COMMON
 	select SOC_QUALCOMM_X1P42100
 	select SPI_FLASH
 	select SPI_FLASH_EXIT_4_BYTE_ADDR_MODE
-	select SPI_FLASH_GIGADEVICE
-	select SPI_FLASH_MACRONIX
 	select SPI_FLASH_WINBOND
 
 config BOARD_GOOGLE_BASEBOARD_BLUEY

From 62b823f69ef65328ceb425f709d739c0397fa2fa Mon Sep 17 00:00:00 2001
From: Subrata Banik <subratabanik@google.com>
Date: Wed, 14 May 2025 18:50:10 +0000
Subject: [PATCH 1047/3886] mb/google/bluey: Increase flash size to 64MB for
 W25Q512NWEIM

This commit updates the flash configuration for the Bluey mainboard
to support the 64MB W25Q512NWEIM SPI flash part.

Key changes:
- Kconfig: The `BOARD_ROMSIZE_KB` selection is changed
  from 8192 (8MB) to 65536 (64MB).

These changes ensure the firmware is built correctly for the larger
SPI flash and the flash map accurately reflects the hardware.

BUG=b:404985109
TEST=Able to build google/bluey. Running `ls -l` shows that `coreboot.rom` is 64 MB.

Change-Id: I5acd476989e94fba4022eeb4e96fa50b459b5766
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87680
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
---
 src/mainboard/google/bluey/Kconfig | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/mainboard/google/bluey/Kconfig b/src/mainboard/google/bluey/Kconfig
index 765f3cbc50..09f7cae5dd 100644
--- a/src/mainboard/google/bluey/Kconfig
+++ b/src/mainboard/google/bluey/Kconfig
@@ -2,7 +2,7 @@
 
 config BOARD_GOOGLE_BLUEY_COMMON
 	def_bool n
-	select BOARD_ROMSIZE_KB_8192
+	select BOARD_ROMSIZE_KB_65536
 	select COMMON_CBFS_SPI_WRAPPER
 	select MAINBOARD_HAS_CHROMEOS
 	select SOC_QUALCOMM_X1P42100

From c81b08c4bac7f5de285fb14c84db4cd5e908f288 Mon Sep 17 00:00:00 2001
From: Yu-Ping Wu <yupingso@chromium.org>
Date: Fri, 16 May 2025 14:10:17 +0800
Subject: [PATCH 1048/3886] util/abuild: Fix building ChromeOS boards

The commit 49ae935b3778 ("util/abuild: Change [...] to [[...]] for
consistency") [1] accidentally replaced "\>" with ">" in a grep pattern,
causing all boards to be considered not supporting ChromeOS.

The commit f66c7c1037e9 ("util/abuild: Update echo to printf for
consistency") [2] replaced

 @echo $(foreach arch,$(REQUIRED_ARCHES),\
   $(if $(filter $(arch),$(SUBARCH_SUPPORTED)),,$(arch)))

with

 @printf "%s\n" "$(foreach arch,$(REQUIRED_ARCHES),\
   $(if $(filter $(arch),$(SUBARCH_SUPPORTED)),,$(arch)))"

and caused an additional whitespace character to be printed when all
required archs are supported. The result of the `missing_arches` shell
variable would be " ", and hence the `[[ -n "$missing_arches" ]]` check
would be wrong. Fix this by using `-z`.

[1] CB:87367
[2] CB:87368

Change-Id: Ib77566e70ac8b3717f3b29433ce9ae0a1fc69cce
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87708
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jakub "Kuba" Czapiga <czapiga@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
---
 util/abuild/abuild | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/util/abuild/abuild b/util/abuild/abuild
index 66316e2eac..007ced4ed8 100755
--- a/util/abuild/abuild
+++ b/util/abuild/abuild
@@ -510,7 +510,7 @@ build_config()
 
 	export HOSTCC='gcc'
 
-	if [[ "${chromeos}" = true ]] && [[ "$(grep -c "^[[:space:]]*select[[:space:]]*MAINBOARD_HAS_CHROMEOS>" "${ROOT}/src/mainboard/${board_srcdir}/Kconfig")" -eq 0 ]]; then
+	if [[ "${chromeos}" = true ]] && [[ "$(grep -c "^[[:space:]]*select[[:space:]]*MAINBOARD_HAS_CHROMEOS\>" "${ROOT}/src/mainboard/${board_srcdir}/Kconfig")" -eq 0 ]]; then
 		printf "%s doesn't support ChromeOS, skipping.\n" "${BUILD_NAME}"
 		return
 	fi
@@ -598,7 +598,7 @@ EOF
 		exit 1
 	fi
 
-	if [[ -n "${missing_arches}" ]]; then
+	if [[ -z "${missing_arches}" ]]; then
 		printf "skipping %s because we're missing compilers for (%s)\n" "${BUILD_NAME}" "${missing_arches}"
 		return
 	fi

From 5e2aee4474780c70faef84e0dc566042cbf99387 Mon Sep 17 00:00:00 2001
From: Vince Liu <vince-wl.liu@mediatek.corp-partner.google.com>
Date: Sun, 20 Apr 2025 16:30:12 +0800
Subject: [PATCH 1049/3886] soc/mediatek/mt8196: Move sspm_enable_sram() to
 common code

To promote code reuse and maintainability, move mt8196/sspm_sram.c to
common folder. The macro for the register SSPM_SRAM_CON is replaced by
'mtk_spm->sspm_sram_con' since it is already defined in spm.h.

BUG=b:379008996
BRANCH=none
TEST=build passed.

Signed-off-by: Vince Liu <vince-wl.liu@mediatek.corp-partner.google.com>
Change-Id: I71912a23537a8bb26ed431d06123a875b80b8e4f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87661
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
---
 src/soc/mediatek/{mt8196 => common}/sspm_sram.c | 7 ++++---
 src/soc/mediatek/mt8196/Makefile.mk             | 2 +-
 src/soc/mediatek/mt8196/include/soc/spm.h       | 1 +
 3 files changed, 6 insertions(+), 4 deletions(-)
 rename src/soc/mediatek/{mt8196 => common}/sspm_sram.c (54%)

diff --git a/src/soc/mediatek/mt8196/sspm_sram.c b/src/soc/mediatek/common/sspm_sram.c
similarity index 54%
rename from src/soc/mediatek/mt8196/sspm_sram.c
rename to src/soc/mediatek/common/sspm_sram.c
index 5c9a80e4fa..6f416cbb08 100644
--- a/src/soc/mediatek/mt8196/sspm_sram.c
+++ b/src/soc/mediatek/common/sspm_sram.c
@@ -1,9 +1,10 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
+/* SPDX-License-Identifier: GPL-2.0-only OR MIT */
 
 #include <device/mmio.h>
+#include <soc/addressmap.h>
+#include <soc/spm.h>
 #include <soc/sspm.h>
 
-#define SSPM_SRAM_CON		(SPM_BASE + 0xEE4)
 #define SPM_PRJ_CODE		0xB160001
 #define SSPM_SRAM_SLEEP_B	0x10
 #define SSPM_SRAM_ISOINT_B	0x2
@@ -11,5 +12,5 @@
 void sspm_enable_sram(void)
 {
 	write32p(SPM_BASE, SPM_PRJ_CODE);
-	write32p(SSPM_SRAM_CON, SSPM_SRAM_SLEEP_B | SSPM_SRAM_ISOINT_B);
+	write32(&mtk_spm->sspm_sram_con, SSPM_SRAM_SLEEP_B | SSPM_SRAM_ISOINT_B);
 }
diff --git a/src/soc/mediatek/mt8196/Makefile.mk b/src/soc/mediatek/mt8196/Makefile.mk
index 17c768fb37..5240fbb2bb 100644
--- a/src/soc/mediatek/mt8196/Makefile.mk
+++ b/src/soc/mediatek/mt8196/Makefile.mk
@@ -81,7 +81,7 @@ ramstage-y += ../common/mtk_fsp.c
 ramstage-y += pi_image.c
 ramstage-y += soc.c
 ramstage-y += ../common/spm.c ../common/spm_v2.c spm.c
-ramstage-y += ../common/sspm.c sspm_sram.c
+ramstage-y += ../common/sspm.c ../common/sspm_sram.c
 ramstage-y += ../common/pmif_clk.c pmif_clk.c
 ramstage-y += ../common/pmif.c pmif_init.c
 ramstage-y += pmif_spmi.c
diff --git a/src/soc/mediatek/mt8196/include/soc/spm.h b/src/soc/mediatek/mt8196/include/soc/spm.h
index 5e6b78497e..bdc5f8c150 100644
--- a/src/soc/mediatek/mt8196/include/soc/spm.h
+++ b/src/soc/mediatek/mt8196/include/soc/spm.h
@@ -1130,6 +1130,7 @@ check_member(mtk_spm_regs, md32pcm_cfgreg_sw_rstn, 0xA00);
 check_member(mtk_spm_regs, md32pcm_dma0_src, 0xC00);
 check_member(mtk_spm_regs, md32pcm_dma0_rlct, 0xC24);
 check_member(mtk_spm_regs, md1_pwr_con, 0xE00);
+check_member(mtk_spm_regs, sspm_sram_con, 0xEE4);
 check_member(mtk_spm_regs, soc_buck_iso_con, 0xF00);
 check_member(mtk_spm_regs, spm_twam_timer_out, 0xFFC);
 check_member(mtk_spm_regs, spm_lteclksq_bg_off, 0x9220);

From c0113106fabcd8714ff9e0bf8ae1ab4220cdf83f Mon Sep 17 00:00:00 2001
From: Felix Held <felix-coreboot@felixheld.de>
Date: Mon, 18 Dec 2023 22:19:25 +0100
Subject: [PATCH 1050/3886] nb/amd/pi/00730F01/northbridge: skip IVRS when
 IOMMU is disabled
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Don't generate the IVRS ACPI table if the IOMMU PCI device isn't enabled
in the devicetree.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I5e7f976011da92c0ca69decdca7aa77de24b6a2a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79677
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
---
 src/northbridge/amd/pi/00730F01/northbridge.c | 14 ++++++++------
 1 file changed, 8 insertions(+), 6 deletions(-)

diff --git a/src/northbridge/amd/pi/00730F01/northbridge.c b/src/northbridge/amd/pi/00730F01/northbridge.c
index 55074435ab..826c19e862 100644
--- a/src/northbridge/amd/pi/00730F01/northbridge.c
+++ b/src/northbridge/amd/pi/00730F01/northbridge.c
@@ -437,12 +437,14 @@ static unsigned long agesa_write_acpi_tables(const struct device *device,
 	current += ((acpi_header_t *)current)->length;
 
 	/* IVRS */
-	current = ALIGN_UP(current, 8);
-	printk(BIOS_DEBUG, "ACPI:   * IVRS at %lx\n", current);
-	ivrs = (acpi_ivrs_t *)current;
-	acpi_create_ivrs(ivrs, acpi_fill_ivrs);
-	current += ivrs->header.length;
-	acpi_add_table(rsdp, ivrs);
+	if (is_dev_enabled(DEV_PTR(iommu))) {
+		current = ALIGN_UP(current, 8);
+		printk(BIOS_DEBUG, "ACPI:   * IVRS at %lx\n", current);
+		ivrs = (acpi_ivrs_t *)current;
+		acpi_create_ivrs(ivrs, acpi_fill_ivrs);
+		current += ivrs->header.length;
+		acpi_add_table(rsdp, ivrs);
+	}
 
 	/* SRAT */
 	current = ALIGN_UP(current, 8);

From ae2f3ab15394684233d06327aa3ce46feb140e77 Mon Sep 17 00:00:00 2001
From: Tim Crawford <tcrawford@system76.com>
Date: Mon, 12 May 2025 12:21:53 -0600
Subject: [PATCH 1051/3886] mb/system76: Add SMBIOS slot descriptions

Change-Id: Ie68207dcdaab7e8de6e1c4099fc07f5c37720edb
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87651
Reviewed-by: Jeremy Soller <jeremy@system76.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
---
 src/mainboard/system76/addw1/devicetree.cb                    | 3 +++
 src/mainboard/system76/adl/variants/darp8/overridetree.cb     | 3 +++
 src/mainboard/system76/adl/variants/galp6/overridetree.cb     | 2 ++
 .../system76/adl/variants/gaze17-3050/overridetree.cb         | 3 +++
 .../system76/adl/variants/gaze17-3060-b/overridetree.cb       | 3 +++
 src/mainboard/system76/adl/variants/lemp11/overridetree.cb    | 3 +++
 src/mainboard/system76/adl/variants/oryp10/overridetree.cb    | 3 +++
 src/mainboard/system76/adl/variants/oryp9/overridetree.cb     | 3 +++
 src/mainboard/system76/bonw14/devicetree.cb                   | 4 ++++
 src/mainboard/system76/cml-u/variants/darp6/overridetree.cb   | 2 ++
 src/mainboard/system76/cml-u/variants/galp4/overridetree.cb   | 2 ++
 src/mainboard/system76/gaze15/devicetree.cb                   | 3 +++
 src/mainboard/system76/kbl-u/devicetree.cb                    | 2 ++
 src/mainboard/system76/mtl/variants/darp10/overridetree.cb    | 3 +++
 src/mainboard/system76/oryp5/devicetree.cb                    | 3 +++
 src/mainboard/system76/oryp6/devicetree.cb                    | 3 +++
 .../system76/tgl-h/variants/gaze16-3050/overridetree.cb       | 3 +++
 .../system76/tgl-h/variants/gaze16-3060/overridetree.cb       | 3 +++
 src/mainboard/system76/tgl-h/variants/oryp8/overridetree.cb   | 3 +++
 src/mainboard/system76/tgl-u/variants/darp7/overridetree.cb   | 3 +++
 src/mainboard/system76/tgl-u/variants/galp5/overridetree.cb   | 2 ++
 src/mainboard/system76/tgl-u/variants/lemp10/overridetree.cb  | 3 +++
 src/mainboard/system76/whl-u/devicetree.cb                    | 2 ++
 23 files changed, 64 insertions(+)

diff --git a/src/mainboard/system76/addw1/devicetree.cb b/src/mainboard/system76/addw1/devicetree.cb
index 59491134c7..e498173b07 100644
--- a/src/mainboard/system76/addw1/devicetree.cb
+++ b/src/mainboard/system76/addw1/devicetree.cb
@@ -107,6 +107,7 @@ chip soc/intel/cannonlake
 			register "PcieClkSrcUsage[10]" = "20"
 			register "PcieClkSrcClkReq[10]" = "10"
 			register "PcieRpSlotImplemented[20]" = "1"
+			smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M.2/M 2280 (J_SSD2)" "SlotDataBusWidth4X"
 		end
 		device ref pcie_rp9	on
 			# PCI Express root port #9 x4, Clock 9 (SSD1)
@@ -114,6 +115,7 @@ chip soc/intel/cannonlake
 			register "PcieClkSrcUsage[9]" = "8"
 			register "PcieClkSrcClkReq[9]" = "9"
 			register "PcieRpSlotImplemented[8]" = "1"
+			smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M.2/M 2280 (J_SSD1)" "SlotDataBusWidth4X"
 		end
 		device ref pcie_rp14	on
 			# PCI Express root port #14 x1, Clock 5 (GLAN)
@@ -135,6 +137,7 @@ chip soc/intel/cannonlake
 			register "PcieClkSrcUsage[6]" = "15"
 			register "PcieClkSrcClkReq[6]" = "6"
 			register "PcieRpSlotImplemented[15]" = "1"
+			smbios_slot_desc "SlotTypeM2Socket1_SD" "SlotLengthOther" "M.2/E 2230 (J_WLAN1)" "SlotDataBusWidth1X"
 		end
 		device ref lpc_espi	on
 			register "gen1_dec" = "0x00040069"
diff --git a/src/mainboard/system76/adl/variants/darp8/overridetree.cb b/src/mainboard/system76/adl/variants/darp8/overridetree.cb
index 7a7e14ee99..3af580229b 100644
--- a/src/mainboard/system76/adl/variants/darp8/overridetree.cb
+++ b/src/mainboard/system76/adl/variants/darp8/overridetree.cb
@@ -27,6 +27,7 @@ chip soc/intel/alderlake
 				register "srcclk_pin" = "0" # SSD2_CLKREQ#
 				device generic 0 on end
 			end
+			smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M.2/M 2280 (J_SSD2)" "SlotDataBusWidth4X"
 		end
 		device ref tcss_xhci on
 			register "tcss_ports[0]" = "TCSS_PORT_DEFAULT(OC_SKIP)"
@@ -131,6 +132,7 @@ chip soc/intel/alderlake
 				register "srcclk_pin" = "2" # WLAN_CLKREQ#
 				device generic 0 on end
 			end
+			smbios_slot_desc "SlotTypeM2Socket1_SD" "SlotLengthOther" "M.2/E 2230 (J_WLAN1)" "SlotDataBusWidth1X"
 		end
 		device ref pcie_rp6 on
 			# PCIe RP#6 x1, Clock 5 (CARD)
@@ -163,6 +165,7 @@ chip soc/intel/alderlake
 			#	register "srcclk_pin" = "4" # SSD1_CLKREQ#
 			#	device generic 0 on end
 			#end
+			smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M.2/M 2280 (J_SSD1)" "SlotDataBusWidth4X"
 		end
 		device ref pmc hidden
 			chip drivers/intel/pmc_mux
diff --git a/src/mainboard/system76/adl/variants/galp6/overridetree.cb b/src/mainboard/system76/adl/variants/galp6/overridetree.cb
index 79c614e761..6856cb2bdd 100644
--- a/src/mainboard/system76/adl/variants/galp6/overridetree.cb
+++ b/src/mainboard/system76/adl/variants/galp6/overridetree.cb
@@ -27,6 +27,7 @@ chip soc/intel/alderlake
 				register "srcclk_pin" = "0" # SSD1_CLKREQ#
 				device generic 0 on end
 			end
+			smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M.2/M 2280 (J_SSD1)" "SlotDataBusWidth4X"
 		end
 		device ref tcss_xhci on
 			register "tcss_ports[0]" = "TCSS_PORT_DEFAULT(OC_SKIP)"
@@ -152,6 +153,7 @@ chip soc/intel/alderlake
 				register "srcclk_pin" = "2" # WLAN_CLKREQ#
 				device generic 0 on end
 			end
+			smbios_slot_desc "SlotTypeM2Socket1_SD" "SlotLengthOther" "M.2/E 2230 (J_WLAN1)" "SlotDataBusWidth1X"
 		end
 		device ref pcie_rp9 on
 			# PCIe RP#9 x1, Clock 5 (CARD)
diff --git a/src/mainboard/system76/adl/variants/gaze17-3050/overridetree.cb b/src/mainboard/system76/adl/variants/gaze17-3050/overridetree.cb
index 603879bb8b..511e0535b7 100644
--- a/src/mainboard/system76/adl/variants/gaze17-3050/overridetree.cb
+++ b/src/mainboard/system76/adl/variants/gaze17-3050/overridetree.cb
@@ -48,6 +48,7 @@ chip soc/intel/alderlake
 				.clk_req = 0,
 				.flags = PCIE_RP_LTR,
 			}"
+			smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M.2/M 2280 (J_SSD2)" "SlotDataBusWidth4X"
 		end
 		device ref i2c0 on
 			# Touchpad I2C bus
@@ -102,6 +103,7 @@ chip soc/intel/alderlake
 				.flags = PCIE_RP_LTR,
 				.pcie_rp_detect_timeout_ms = 50,
 			}"
+			smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M.2/M 2280 (J_SSD1)" "SlotDataBusWidth4X"
 		end
 		device ref pcie_rp9 on
 			# PCIe RP#9 x1, Clock 6 (GLAN)
@@ -118,6 +120,7 @@ chip soc/intel/alderlake
 				.clk_req = 2,
 				.flags = PCIE_RP_LTR | PCIE_RP_AER,
 			}"
+			smbios_slot_desc "SlotTypeM2Socket1_SD" "SlotLengthOther" "M.2/E 2230 (J_WLAN1)" "SlotDataBusWidth1X"
 		end
 		device ref pcie_rp11 on
 			# PCIe RP#11 x1, Clock 5 (CARD)
diff --git a/src/mainboard/system76/adl/variants/gaze17-3060-b/overridetree.cb b/src/mainboard/system76/adl/variants/gaze17-3060-b/overridetree.cb
index a9c614e424..de67935293 100644
--- a/src/mainboard/system76/adl/variants/gaze17-3060-b/overridetree.cb
+++ b/src/mainboard/system76/adl/variants/gaze17-3060-b/overridetree.cb
@@ -55,6 +55,7 @@ chip soc/intel/alderlake
 				.clk_req = 0,
 				.flags = PCIE_RP_LTR,
 			}"
+			smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M.2/M 2280 (J_SSD2)" "SlotDataBusWidth4X"
 		end
 		device ref i2c0 on
 			# Touchpad I2C bus
@@ -107,6 +108,7 @@ chip soc/intel/alderlake
 				.clk_req = 2,
 				.flags = PCIE_RP_LTR,
 			}"
+			smbios_slot_desc "SlotTypeM2Socket1_SD" "SlotLengthOther" "M.2/E 2230 (J_WLAN1)" "SlotDataBusWidth1X"
 		end
 		device ref pcie_rp6 on
 			# PCIe root port #6 x1, Clock 5 (CARD)
@@ -134,6 +136,7 @@ chip soc/intel/alderlake
 				.flags = PCIE_RP_LTR,
 				.pcie_rp_detect_timeout_ms = 50,
 			}"
+			smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M.2/M 2280 (J_SSD1)" "SlotDataBusWidth4X"
 		end
 		device ref gbe on end
 	end
diff --git a/src/mainboard/system76/adl/variants/lemp11/overridetree.cb b/src/mainboard/system76/adl/variants/lemp11/overridetree.cb
index 10c6bfcf31..3b0678b44f 100644
--- a/src/mainboard/system76/adl/variants/lemp11/overridetree.cb
+++ b/src/mainboard/system76/adl/variants/lemp11/overridetree.cb
@@ -27,6 +27,7 @@ chip soc/intel/alderlake
 				register "srcclk_pin" = "0" # SSD0_CLKREQ#
 				device generic 0 on end
 			end
+			smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M.2/M 2280 (J_SSD2)" "SlotDataBusWidth4X"
 		end
 		device ref tcss_xhci on
 			register "tcss_ports[0]" = "TCSS_PORT_DEFAULT(OC_SKIP)"
@@ -125,6 +126,7 @@ chip soc/intel/alderlake
 				register "srcclk_pin" = "2" # WLAN_CLKREQ#
 				device generic 0 on end
 			end
+			smbios_slot_desc "SlotTypeM2Socket1_SD" "SlotLengthOther" "M.2/E 2230 (J_WLAN1)" "SlotDataBusWidth1X"
 		end
 		device ref pcie_rp6 on
 			# PCIe RP#6 x1, Clock 6 (CARD)
@@ -149,6 +151,7 @@ chip soc/intel/alderlake
 			#	register "srcclk_pin" = "1" # SSD1_CLKREQ#
 			#	device generic 0 on end
 			#end
+			smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M.2/M 2280 (J_SSD1)" "SlotDataBusWidth4X"
 		end
 		device ref pmc hidden
 			chip drivers/intel/pmc_mux
diff --git a/src/mainboard/system76/adl/variants/oryp10/overridetree.cb b/src/mainboard/system76/adl/variants/oryp10/overridetree.cb
index 09f07b6cce..b213892232 100644
--- a/src/mainboard/system76/adl/variants/oryp10/overridetree.cb
+++ b/src/mainboard/system76/adl/variants/oryp10/overridetree.cb
@@ -37,6 +37,7 @@ chip soc/intel/alderlake
 				.clk_req = 0,
 				.flags = PCIE_RP_LTR,
 			}"
+			smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M.2/M 2280 (J_SSD1)" "SlotDataBusWidth4X"
 		end
 		device ref pcie4_1 on
 			# CPU PCIe RP#3 x4, Clock 4 (SSD2)
@@ -45,6 +46,7 @@ chip soc/intel/alderlake
 				.clk_req = 4,
 				.flags = PCIE_RP_LTR,
 			}"
+			smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M.2/M 2280 (J_SSD2)" "SlotDataBusWidth4X"
 		end
 		device ref tcss_xhci on
 			register "tcss_ports[0]" = "TCSS_PORT_DEFAULT(OC_SKIP)"
@@ -150,6 +152,7 @@ chip soc/intel/alderlake
 				.clk_req = 2,
 				.flags = PCIE_RP_LTR | PCIE_RP_AER,
 			}"
+			smbios_slot_desc "SlotTypeM2Socket1_SD" "SlotLengthOther" "M.2/E 2230 (J_WLAN1)" "SlotDataBusWidth1X"
 		end
 		device ref pcie_rp6 on
 			# PCIe RP#6 x1, Clock 6 (CARD)
diff --git a/src/mainboard/system76/adl/variants/oryp9/overridetree.cb b/src/mainboard/system76/adl/variants/oryp9/overridetree.cb
index 4ca81ab12b..e41c0a278a 100644
--- a/src/mainboard/system76/adl/variants/oryp9/overridetree.cb
+++ b/src/mainboard/system76/adl/variants/oryp9/overridetree.cb
@@ -37,6 +37,7 @@ chip soc/intel/alderlake
 				.clk_req = 0,
 				.flags = PCIE_RP_LTR,
 			}"
+			smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M.2/M 2280 (J_SSD1)" "SlotDataBusWidth4X"
 		end
 		device ref pcie4_1 on
 			# CPU PCIe RP#3 x4, Clock 4 (SSD2)
@@ -45,6 +46,7 @@ chip soc/intel/alderlake
 				.clk_req = 4,
 				.flags = PCIE_RP_LTR,
 			}"
+			smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M.2/M 2280 (J_SSD2)" "SlotDataBusWidth4X"
 		end
 		device ref tcss_xhci on
 			register "tcss_ports[0]" = "TCSS_PORT_DEFAULT(OC_SKIP)"
@@ -150,6 +152,7 @@ chip soc/intel/alderlake
 				.clk_req = 2,
 				.flags = PCIE_RP_LTR | PCIE_RP_AER,
 			}"
+			smbios_slot_desc "SlotTypeM2Socket1_SD" "SlotLengthOther" "M.2/E 2230 (J_WLAN1)" "SlotDataBusWidth1X"
 		end
 		device ref pcie_rp6 on
 			# PCIe RP#6 x1, Clock 6 (CARD)
diff --git a/src/mainboard/system76/bonw14/devicetree.cb b/src/mainboard/system76/bonw14/devicetree.cb
index f5493874f6..4064c00b55 100644
--- a/src/mainboard/system76/bonw14/devicetree.cb
+++ b/src/mainboard/system76/bonw14/devicetree.cb
@@ -116,12 +116,14 @@ chip soc/intel/cannonlake
 			register "PcieRpLtrEnable[16]" = "true"
 			register "PcieClkSrcUsage[14]" = "16"
 			register "PcieClkSrcClkReq[14]" = "14"
+			smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M.2/M 2280 (J_SSD2)" "SlotDataBusWidth4X"
 		end
 		device ref pcie_rp21	on
 			# PCI Express root port #21 x4, Clock 15 (SSD3)
 			register "PcieRpLtrEnable[20]" = "true"
 			register "PcieClkSrcUsage[15]" = "20"
 			register "PcieClkSrcClkReq[15]" = "15"
+			smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M.2/M 2280 (J_SSD3)" "SlotDataBusWidth4X"
 		end
 		device ref pcie_rp1	on
 			# PCI Express root port #1 x4, Clock 6 (Thunderbolt)
@@ -141,12 +143,14 @@ chip soc/intel/cannonlake
 			register "PcieRpLtrEnable[8]" = "true"
 			register "PcieClkSrcUsage[8]" = "8"
 			register "PcieClkSrcClkReq[8]" = "8"
+			smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M.2/M 2280 (J_SSD1)" "SlotDataBusWidth4X"
 		end
 		device ref pcie_rp13	on
 			# PCI Express root port #13 x1, Clock 0 (WLAN)
 			register "PcieRpLtrEnable[12]" = "true"
 			register "PcieClkSrcUsage[0]" = "12"
 			register "PcieClkSrcClkReq[0]" = "0"
+			smbios_slot_desc "SlotTypeM2Socket1_SD" "SlotLengthOther" "M.2/E 2230 (J_WLAN1)" "SlotDataBusWidth1X"
 		end
 		device ref pcie_rp14	on
 			# PCI Express root port #14 x1, Clock 1 (GLAN)
diff --git a/src/mainboard/system76/cml-u/variants/darp6/overridetree.cb b/src/mainboard/system76/cml-u/variants/darp6/overridetree.cb
index 5b9a3bb060..23cbb80ee0 100644
--- a/src/mainboard/system76/cml-u/variants/darp6/overridetree.cb
+++ b/src/mainboard/system76/cml-u/variants/darp6/overridetree.cb
@@ -56,12 +56,14 @@ chip soc/intel/cannonlake
 			register "PcieRpLtrEnable[9]" = "false"
 			register "PcieClkSrcUsage[2]" = "9"
 			register "PcieClkSrcClkReq[2]" = "2"
+			smbios_slot_desc "SlotTypeM2Socket1_SD" "SlotLengthOther" "M.2/E 2230 (J_WLAN1)" "SlotDataBusWidth1X"
 		end
 		device ref pcie_rp13	on
 			# PCI Express Root port #13 x4, Clock 5 (NVMe)
 			register "PcieRpLtrEnable[12]" = "true"
 			register "PcieClkSrcUsage[5]" = "12"
 			register "PcieClkSrcClkReq[5]" = "5"
+			smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M.2/M 2280 (J_SSD1)" "SlotDataBusWidth4X"
 		end
 		device ref hda		on
 			register "PchHdaAudioLinkDmic0" = "1"
diff --git a/src/mainboard/system76/cml-u/variants/galp4/overridetree.cb b/src/mainboard/system76/cml-u/variants/galp4/overridetree.cb
index cc9c4d76c8..062bb8f4d6 100644
--- a/src/mainboard/system76/cml-u/variants/galp4/overridetree.cb
+++ b/src/mainboard/system76/cml-u/variants/galp4/overridetree.cb
@@ -49,12 +49,14 @@ chip soc/intel/cannonlake
 			register "PcieRpLtrEnable[9]" = "false"
 			register "PcieClkSrcUsage[2]" = "9"
 			register "PcieClkSrcClkReq[2]" = "2"
+			smbios_slot_desc "SlotTypeM2Socket1_SD" "SlotLengthOther" "M.2/E 2230 (J_WLAN1)" "SlotDataBusWidth1X"
 		end
 		device ref pcie_rp13	on
 			# PCI Express Root port #13 x4, Clock 5 (NVMe)
 			register "PcieRpLtrEnable[12]" = "true"
 			register "PcieClkSrcUsage[5]" = "12"
 			register "PcieClkSrcClkReq[5]" = "5"
+			smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M.2/M 2280 (J_SSD1)" "SlotDataBusWidth4X"
 		end
 		device ref hda		on
 			register "PchHdaAudioLinkDmic0" = "1"
diff --git a/src/mainboard/system76/gaze15/devicetree.cb b/src/mainboard/system76/gaze15/devicetree.cb
index 1f8fb88c67..02f4d70f58 100644
--- a/src/mainboard/system76/gaze15/devicetree.cb
+++ b/src/mainboard/system76/gaze15/devicetree.cb
@@ -98,6 +98,7 @@ chip soc/intel/cannonlake
 			register "PcieClkSrcUsage[11]" = "20"
 			register "PcieClkSrcClkReq[11]" = "11"
 			register "PcieRpSlotImplemented[20]" = "1"
+			smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M.2/M 2280 (J_SSD2)" "SlotDataBusWidth4X"
 		end
 		device ref pcie_rp9	on
 			# PCI Express root port #9 x4, Clock 10 (SSD)
@@ -105,6 +106,7 @@ chip soc/intel/cannonlake
 			register "PcieClkSrcUsage[10]" = "8"
 			register "PcieClkSrcClkReq[10]" = "10"
 			register "PcieRpSlotImplemented[8]" = "1"
+			smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M.2/M 2280 (J_SSD1)" "SlotDataBusWidth4X"
 		end
 		device ref pcie_rp14	on
 			# PCI Express root port #14 x1, Clock 6 (WLAN)
@@ -112,6 +114,7 @@ chip soc/intel/cannonlake
 			register "PcieClkSrcUsage[6]" = "13"
 			register "PcieClkSrcClkReq[6]" = "6"
 			register "PcieRpSlotImplemented[13]" = "1"
+			smbios_slot_desc "SlotTypeM2Socket1_SD" "SlotLengthOther" "M.2/E 2230 (J_WLAN1)" "SlotDataBusWidth1X"
 		end
 		device ref pcie_rp15	on
 			# PCI Express root port #15 x1, Clock 5 (LAN)
diff --git a/src/mainboard/system76/kbl-u/devicetree.cb b/src/mainboard/system76/kbl-u/devicetree.cb
index 4f3e148944..968e460130 100644
--- a/src/mainboard/system76/kbl-u/devicetree.cb
+++ b/src/mainboard/system76/kbl-u/devicetree.cb
@@ -155,6 +155,7 @@ chip soc/intel/skylake
 			register "PcieRpClkSrcNumber[5]" = "2"
 			register "PcieRpAdvancedErrorReporting[5]" = "1"
 			register "PcieRpLtrEnable[5]" = "true"
+			smbios_slot_desc "SlotTypeM2Socket1_SD" "SlotLengthOther" "M.2/E 2230" "SlotDataBusWidth1X"
 		end
 		device ref pcie_rp9 on
 			# Root port #9 x4 (NVMe)
@@ -163,6 +164,7 @@ chip soc/intel/skylake
 			register "PcieRpClkSrcNumber[8]" = "5"
 			register "PcieRpAdvancedErrorReporting[8]" = "1"
 			register "PcieRpLtrEnable[8]" = "true"
+			smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M.2/M 2280" "SlotDataBusWidth4X"
 		end
 		device ref lpc_espi on
 			register "serirq_mode" = "SERIRQ_CONTINUOUS"
diff --git a/src/mainboard/system76/mtl/variants/darp10/overridetree.cb b/src/mainboard/system76/mtl/variants/darp10/overridetree.cb
index 8baa5560b9..6c2467a76b 100644
--- a/src/mainboard/system76/mtl/variants/darp10/overridetree.cb
+++ b/src/mainboard/system76/mtl/variants/darp10/overridetree.cb
@@ -85,6 +85,7 @@ chip soc/intel/meteorlake
 				.clk_req = 5,
 				.flags = PCIE_RP_LTR | PCIE_RP_AER,
 			}"
+			smbios_slot_desc "SlotTypeM2Socket1_SD" "SlotLengthOther" "M.2/E 2230 (J_WLAN1)" "SlotDataBusWidth1X"
 		end
 		device ref pcie_rp10 on
 			# SSD2
@@ -94,6 +95,7 @@ chip soc/intel/meteorlake
 				.clk_req = 8,
 				.flags = PCIE_RP_LTR | PCIE_RP_AER,
 			}"
+			smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M.2/M 2280 (J_SSD2)" "SlotDataBusWidth4X"
 		end
 		device ref pcie_rp11 on
 			# SSD1
@@ -103,6 +105,7 @@ chip soc/intel/meteorlake
 				.clk_req = 7,
 				.flags = PCIE_RP_LTR | PCIE_RP_AER,
 			}"
+			smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M.2/M 2280 (J_SSD1)" "SlotDataBusWidth4X"
 		end
 		device ref hda on
 			subsystemid 0x1558 0xa763
diff --git a/src/mainboard/system76/oryp5/devicetree.cb b/src/mainboard/system76/oryp5/devicetree.cb
index ea9e14e436..b72d9ba854 100644
--- a/src/mainboard/system76/oryp5/devicetree.cb
+++ b/src/mainboard/system76/oryp5/devicetree.cb
@@ -110,18 +110,21 @@ chip soc/intel/cannonlake
 			register "PcieRpLtrEnable[20]" = "true"
 			register "PcieClkSrcUsage[11]" = "20"
 			register "PcieClkSrcClkReq[11]" = "11"
+			smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M.2/M 2280 (J_SSD2)" "SlotDataBusWidth4X"
 		end
 		device ref pcie_rp9	on
 			# PCI Express root port #9 x4, Clock 12 (SSD)
 			register "PcieRpLtrEnable[8]" = "true"
 			register "PcieClkSrcUsage[12]" = "8"
 			register "PcieClkSrcClkReq[12]" = "12"
+			smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M.2/M 2280 (J_SSD1)" "SlotDataBusWidth4X"
 		end
 		device ref pcie_rp14	on
 			# PCI Express root port #14 x1, Clock 13 (WLAN)
 			register "PcieRpLtrEnable[13]" = "true"
 			register "PcieClkSrcUsage[13]" = "13"
 			register "PcieClkSrcClkReq[13]" = "13"
+			smbios_slot_desc "SlotTypeM2Socket1_SD" "SlotLengthOther" "M.2/E 2230 (J_WLAN1)" "SlotDataBusWidth1X"
 		end
 		device ref pcie_rp15	on
 			# PCI Express root port #15 x1, Clock 14 (GLAN)
diff --git a/src/mainboard/system76/oryp6/devicetree.cb b/src/mainboard/system76/oryp6/devicetree.cb
index e682fefe53..0737ceb714 100644
--- a/src/mainboard/system76/oryp6/devicetree.cb
+++ b/src/mainboard/system76/oryp6/devicetree.cb
@@ -116,6 +116,7 @@ chip soc/intel/cannonlake
 			register "PcieClkSrcUsage[11]" = "20"
 			register "PcieClkSrcClkReq[11]" = "11"
 			register "PcieRpSlotImplemented[20]" = "1"
+			smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M.2/M 2280 (J_SSD2)" "SlotDataBusWidth4X"
 		end
 		device ref pcie_rp9	on
 			# PCI Express root port #9 x4, Clock 12 (SSD1)
@@ -123,6 +124,7 @@ chip soc/intel/cannonlake
 			register "PcieClkSrcUsage[12]" = "8"
 			register "PcieClkSrcClkReq[12]" = "12"
 			register "PcieRpSlotImplemented[8]" = "1"
+			smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M.2/M 2280 (J_SSD1)" "SlotDataBusWidth4X"
 		end
 		device ref pcie_rp14	on
 			# PCI Express root port #14 x1, Clock 7 (GLAN)
@@ -144,6 +146,7 @@ chip soc/intel/cannonlake
 			register "PcieClkSrcUsage[6]" = "15"
 			register "PcieClkSrcClkReq[6]" = "6"
 			register "PcieRpSlotImplemented[15]" = "1"
+			smbios_slot_desc "SlotTypeM2Socket1_SD" "SlotLengthOther" "M.2/E 2230 (J_WLAN1)" "SlotDataBusWidth1X"
 		end
 		device ref lpc_espi	on
 			register "gen1_dec" = "0x00040069" # EC PM channel
diff --git a/src/mainboard/system76/tgl-h/variants/gaze16-3050/overridetree.cb b/src/mainboard/system76/tgl-h/variants/gaze16-3050/overridetree.cb
index 6fa540c83c..b65c45b955 100644
--- a/src/mainboard/system76/tgl-h/variants/gaze16-3050/overridetree.cb
+++ b/src/mainboard/system76/tgl-h/variants/gaze16-3050/overridetree.cb
@@ -29,6 +29,7 @@ chip soc/intel/tigerlake
 			# PCIe PEG0 x4, Clock 4 (SSD2)
 			register "PcieClkSrcUsage[4]" = "0x40"
 			register "PcieClkSrcClkReq[4]" = "4"
+			smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M.2/M 2280 (J_SSD2)" "SlotDataBusWidth4X"
 		end
 		device ref south_xhci on
 			register "usb2_ports" = "{
@@ -71,6 +72,7 @@ chip soc/intel/tigerlake
 			register "PcieClkSrcUsage[8]" = "7"
 			register "PcieClkSrcClkReq[8]" = "8"
 			register "PcieRpSlotImplemented[7]" = "1"
+			smbios_slot_desc "SlotTypeM2Socket1_SD" "SlotLengthOther" "M.2/E 2230 (J_WLAN1)" "SlotDataBusWidth1X"
 		end
 		device ref pcie_rp9 on
 			# PCIe root port #9 x4, Clock 9 (SSD1)
@@ -78,6 +80,7 @@ chip soc/intel/tigerlake
 			register "PcieClkSrcUsage[9]" = "8"
 			register "PcieClkSrcClkReq[9]" = "9"
 			register "PcieRpSlotImplemented[8]" = "1"
+			smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M.2/M 2280 (J_SSD1)" "SlotDataBusWidth4X"
 		end
 	end
 end
diff --git a/src/mainboard/system76/tgl-h/variants/gaze16-3060/overridetree.cb b/src/mainboard/system76/tgl-h/variants/gaze16-3060/overridetree.cb
index 1eab4c95f8..461736c367 100644
--- a/src/mainboard/system76/tgl-h/variants/gaze16-3060/overridetree.cb
+++ b/src/mainboard/system76/tgl-h/variants/gaze16-3060/overridetree.cb
@@ -29,6 +29,7 @@ chip soc/intel/tigerlake
 			# PCIe PEG0 x4, Clock 7 (SSD1)
 			register "PcieClkSrcUsage[7]" = "0x40"
 			register "PcieClkSrcClkReq[7]" = "7"
+			smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M.2/M 2280 (J_SSD1)" "SlotDataBusWidth4X"
 		end
 		device ref south_xhci on
 			register "usb2_ports" = "{
@@ -71,6 +72,7 @@ chip soc/intel/tigerlake
 			register "PcieClkSrcUsage[2]" = "7"
 			register "PcieClkSrcClkReq[2]" = "2"
 			register "PcieRpSlotImplemented[7]" = "1"
+			smbios_slot_desc "SlotTypeM2Socket1_SD" "SlotLengthOther" "M.2/E 2230 (J_WLAN1)" "SlotDataBusWidth1X"
 		end
 		device ref pcie_rp9 on
 			# PCIe root port #9 x4, Clock 10 (SSD2)
@@ -78,6 +80,7 @@ chip soc/intel/tigerlake
 			register "PcieClkSrcUsage[10]" = "8"
 			register "PcieClkSrcClkReq[10]" = "10"
 			register "PcieRpSlotImplemented[8]" = "1"
+			smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M.2/M 2280 (J_SSD2)" "SlotDataBusWidth4X"
 		end
 		device ref gbe on end
 	end
diff --git a/src/mainboard/system76/tgl-h/variants/oryp8/overridetree.cb b/src/mainboard/system76/tgl-h/variants/oryp8/overridetree.cb
index de1e445612..3c4578bf61 100644
--- a/src/mainboard/system76/tgl-h/variants/oryp8/overridetree.cb
+++ b/src/mainboard/system76/tgl-h/variants/oryp8/overridetree.cb
@@ -36,6 +36,7 @@ chip soc/intel/tigerlake
 			# PCIe PEG0 x4, Clock 7 (SSD1)
 			register "PcieClkSrcUsage[7]" = "0x40"
 			register "PcieClkSrcClkReq[7]" = "7"
+			smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M.2/M 2280 (J_SSD1)" "SlotDataBusWidth4X"
 		end
 		device ref tbt_pcie_rp0 on end # TYPEC1
 		device ref north_xhci on # TYPEC1
@@ -80,6 +81,7 @@ chip soc/intel/tigerlake
 			register "PcieClkSrcUsage[2]" = "7"
 			register "PcieClkSrcClkReq[2]" = "2"
 			register "PcieRpSlotImplemented[7]" = "1"
+			smbios_slot_desc "SlotTypeM2Socket1_SD" "SlotLengthOther" "M.2/E 2230 (J_WLAN1)" "SlotDataBusWidth1X"
 		end
 		device ref pcie_rp9 on
 			# PCIe root port #9 x4, Clock 6 (SSD2)
@@ -87,6 +89,7 @@ chip soc/intel/tigerlake
 			register "PcieClkSrcUsage[6]" = "8"
 			register "PcieClkSrcClkReq[6]" = "6"
 			register "PcieRpSlotImplemented[8]" = "1"
+			smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M.2/M 2280 (J_SSD2)" "SlotDataBusWidth4X"
 		end
 		device ref smbus on
 			chip drivers/i2c/tas5825m
diff --git a/src/mainboard/system76/tgl-u/variants/darp7/overridetree.cb b/src/mainboard/system76/tgl-u/variants/darp7/overridetree.cb
index 768f1c7b4e..9ede4dd1d7 100644
--- a/src/mainboard/system76/tgl-u/variants/darp7/overridetree.cb
+++ b/src/mainboard/system76/tgl-u/variants/darp7/overridetree.cb
@@ -29,6 +29,7 @@ chip soc/intel/tigerlake
 				register "srcclk_pin" = "0" # SSD1_CLKREQ#
 				device generic 0 on end
 			end
+			smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M.2/M 2280 (J_SSD2)" "SlotDataBusWidth4X"
 		end
 		device ref north_xhci on # J_TYPEC2
 			register "UsbTcPortEn" = "1"
@@ -165,6 +166,7 @@ chip soc/intel/tigerlake
 			register "PcieClkSrcUsage[1]" = "7"
 			register "PcieClkSrcClkReq[1]" = "1"
 			register "PcieRpSlotImplemented[7]" = "1"
+			smbios_slot_desc "SlotTypeM2Socket1_SD" "SlotLengthOther" "M.2/E 2230 (J_WLAN1)" "SlotDataBusWidth1X"
 		end
 		device ref pcie_rp9 on
 			# PCIe root port #9 x4, Clock 4 (SSD0)
@@ -178,6 +180,7 @@ chip soc/intel/tigerlake
 				register "srcclk_pin" = "4"
 				device generic 0 on end
 			end
+			smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M.2/M 2280 (J_SSD1)" "SlotDataBusWidth4X"
 		end
 		device ref pmc hidden
 			# The pmc_mux chip driver is a placeholder for the
diff --git a/src/mainboard/system76/tgl-u/variants/galp5/overridetree.cb b/src/mainboard/system76/tgl-u/variants/galp5/overridetree.cb
index 8683bb834f..c272244222 100644
--- a/src/mainboard/system76/tgl-u/variants/galp5/overridetree.cb
+++ b/src/mainboard/system76/tgl-u/variants/galp5/overridetree.cb
@@ -29,6 +29,7 @@ chip soc/intel/tigerlake
 				register "srcclk_pin" = "0" # SSD1_CLKREQ#
 				device generic 0 on end
 			end
+			smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M.2/M 2280 (J_SSD1)" "SlotDataBusWidth4X"
 		end
 		device ref north_xhci on # J_TYPEC2
 			register "UsbTcPortEn" = "1"
@@ -181,6 +182,7 @@ chip soc/intel/tigerlake
 			register "PcieClkSrcUsage[1]" = "10"
 			register "PcieClkSrcClkReq[1]" = "1"
 			register "PcieRpSlotImplemented[10]" = "1"
+			smbios_slot_desc "SlotTypeM2Socket1_SD" "SlotLengthOther" "M.2/E 2230 (J_WLAN1)" "SlotDataBusWidth1X"
 		end
 		device ref pmc hidden
 			# The pmc_mux chip driver is a placeholder for the
diff --git a/src/mainboard/system76/tgl-u/variants/lemp10/overridetree.cb b/src/mainboard/system76/tgl-u/variants/lemp10/overridetree.cb
index 45abfec9d6..8ecb00e88d 100644
--- a/src/mainboard/system76/tgl-u/variants/lemp10/overridetree.cb
+++ b/src/mainboard/system76/tgl-u/variants/lemp10/overridetree.cb
@@ -30,6 +30,7 @@ chip soc/intel/tigerlake
 				register "srcclk_pin" = "3" # SSD2_CLKREQ#
 				device generic 0 on end
 			end
+			smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M.2/M 2280 (J_SSD1)" "SlotDataBusWidth4X"
 		end
 		device ref north_xhci on # J_TYPEC1
 			register "UsbTcPortEn" = "1"
@@ -124,6 +125,7 @@ chip soc/intel/tigerlake
 			register "PcieClkSrcUsage[1]" = "2"
 			register "PcieClkSrcClkReq[1]" = "1"
 			register "PcieRpSlotImplemented[2]" = "1"
+			smbios_slot_desc "SlotTypeM2Socket1_SD" "SlotLengthOther" "M.2/E 2230 (J_WLAN1)" "SlotDataBusWidth1X"
 		end
 		device ref pcie_rp6 on
 			# PCIe root port #6 x1, Clock 2 (CARD)
@@ -144,6 +146,7 @@ chip soc/intel/tigerlake
 				register "srcclk_pin" = "0"
 				device generic 0 on end
 			end
+			smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M.2/M 2280 (J_SSD2)" "SlotDataBusWidth4X"
 		end
 		device ref pmc hidden
 			# The pmc_mux chip driver is a placeholder for the
diff --git a/src/mainboard/system76/whl-u/devicetree.cb b/src/mainboard/system76/whl-u/devicetree.cb
index 5593b11b97..68d1c21783 100644
--- a/src/mainboard/system76/whl-u/devicetree.cb
+++ b/src/mainboard/system76/whl-u/devicetree.cb
@@ -113,12 +113,14 @@ chip soc/intel/cannonlake
 			register "PcieRpLtrEnable[9]" = "false"
 			register "PcieClkSrcUsage[2]" = "9"
 			register "PcieClkSrcClkReq[2]" = "2"
+			smbios_slot_desc "SlotTypeM2Socket1_SD" "SlotLengthOther" "M.2/E 2230" "SlotDataBusWidth1X"
 		end
 		device ref pcie_rp13	on
 			# PCI Express Root port #13 x4, Clock 5 (NVMe)
 			register "PcieRpLtrEnable[12]" = "true"
 			register "PcieClkSrcUsage[5]" = "12"
 			register "PcieClkSrcClkReq[5]" = "5"
+			smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M.2/M 2280" "SlotDataBusWidth4X"
 		end
 		device ref lpc_espi	on
 			register "gen1_dec" = "0x000c0081"

From b9a4d6ede15848382b945218e2b46de17a35eb60 Mon Sep 17 00:00:00 2001
From: Shunxi Zhang <ot_shunxi.zhang@mediatek.com>
Date: Fri, 9 May 2025 17:56:10 +0800
Subject: [PATCH 1052/3886] soc/mediatek/common: Correct MT6359 RTC EOSC
 setting

According to the MT6359 datasheet, set the RTC EOSC calibration period
to 8 seconds to ensure that the power source VXO22 in the MT6359 meets
the expected power sequence in AP power-off mode.

BUG=b:397292746
BRANCH=none
TEST=build pass & boot pass

Change-Id: I4043f4e82baeb8e0358e74dd6d088895e4deb0f4
Signed-off-by: Shunxi Zhang <ot_shunxi.zhang@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87705
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
---
 src/soc/mediatek/common/include/soc/rtc_mt6359p.h | 4 ++++
 src/soc/mediatek/common/rtc_mt6359p.c             | 5 +++++
 2 files changed, 9 insertions(+)

diff --git a/src/soc/mediatek/common/include/soc/rtc_mt6359p.h b/src/soc/mediatek/common/include/soc/rtc_mt6359p.h
index fcae61e914..76de250dc8 100644
--- a/src/soc/mediatek/common/include/soc/rtc_mt6359p.h
+++ b/src/soc/mediatek/common/include/soc/rtc_mt6359p.h
@@ -72,6 +72,10 @@ enum {
 	RTC_TC_MTH_MASK = 0xf,
 };
 
+enum {
+	RTC_EOSC_CALI_TD_DEFAULT = 6U << 5,
+};
+
 enum {
 	RTC_K_EOSC_RSV_0	= 1 << 8,
 	RTC_K_EOSC_RSV_1	= 1 << 9,
diff --git a/src/soc/mediatek/common/rtc_mt6359p.c b/src/soc/mediatek/common/rtc_mt6359p.c
index 6e8a3a0931..7ea23b0e79 100644
--- a/src/soc/mediatek/common/rtc_mt6359p.c
+++ b/src/soc/mediatek/common/rtc_mt6359p.c
@@ -220,6 +220,7 @@ int rtc_init(int recover)
 {
 	int ret;
 	u16 year;
+	u16 al_dow;
 
 	rtc_info("recovery: %d\n", recover);
 
@@ -256,6 +257,10 @@ int rtc_init(int recover)
 		goto err;
 	}
 
+	/* RTC EOSC calibration period setting and day-of-week value of alarm counter setting */
+	rtc_read(RTC_AL_DOW, &al_dow);
+	rtc_write(RTC_AL_DOW, al_dow | RTC_EOSC_CALI_TD_DEFAULT);
+
 	/* solution1 for EOSC cali*/
 	rtc_read(RTC_AL_YEA, &year);
 	rtc_write(RTC_AL_YEA, (year | RTC_K_EOSC_RSV_0) & (~RTC_K_EOSC_RSV_1)

From cb77cafbb45c7c6941e20fb82e88ae2db923acad Mon Sep 17 00:00:00 2001
From: Zhigang Qin <zhigang.qin@mediatek.corp-partner.google.com>
Date: Tue, 26 Nov 2024 17:29:13 +0800
Subject: [PATCH 1053/3886] soc/mediatek/mt8189: Add SPMI and PWRAP driver

Add System Power Management Interface(SPMI) and PMIC Wrapper(PWRAP)
driver for PMIC.

BUG=b:379008996
BRANCH=none
TEST=build pass and driver log is normal:
[DEBUG]  [pmif_ulposc_check] calibration done:
cur=260M, CAL_RATE=40, target=260
[INFO ]  [Pass] dly:1, pol:0, sampl:0x2
[INFO ]  [Pass] dly:1, pol:0, sampl:0x2
[DEBUG]  pmic_efuse_setting: Set efuses in 10 msecs

Signed-off-by: Zhigang Qin <zhigang.qin@mediatek.corp-partner.google.com>
Change-Id: I7d0783ccaebd79db69a5a8ef18d7feb6cd4b14f3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87694
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
---
 .../mediatek/common/include/soc/pmif_spi.h    |   2 +
 src/soc/mediatek/common/pmif_spi.c            |   7 +
 src/soc/mediatek/mt8189/Makefile.mk           |   6 +
 .../mediatek/mt8189/include/soc/addressmap.h  |   8 +-
 src/soc/mediatek/mt8189/include/soc/pll.h     |  10 +-
 src/soc/mediatek/mt8189/include/soc/pmif.h    | 156 +++++++++++++++++
 .../mediatek/mt8189/include/soc/spm_mtcmos.h  |   6 +-
 src/soc/mediatek/mt8189/pmif_clk.c            | 165 ++++++++++++++++++
 src/soc/mediatek/mt8189/pmif_spi.c            |  25 +++
 src/soc/mediatek/mt8189/pmif_spmi.c           |  46 +++++
 10 files changed, 424 insertions(+), 7 deletions(-)
 create mode 100644 src/soc/mediatek/mt8189/include/soc/pmif.h
 create mode 100644 src/soc/mediatek/mt8189/pmif_clk.c
 create mode 100644 src/soc/mediatek/mt8189/pmif_spi.c
 create mode 100644 src/soc/mediatek/mt8189/pmif_spmi.c

diff --git a/src/soc/mediatek/common/include/soc/pmif_spi.h b/src/soc/mediatek/common/include/soc/pmif_spi.h
index b704ec1e12..6067081507 100644
--- a/src/soc/mediatek/common/include/soc/pmif_spi.h
+++ b/src/soc/mediatek/common/include/soc/pmif_spi.h
@@ -108,4 +108,6 @@ enum {
 
 int pmif_spi_init(struct pmif *arb);
 void pmif_spi_iocfg(void);
+void pmif_spi_setting(struct pmif *arb);
+
 #endif /* __SOC_MEDIATEK_PMIF_SPI_H__ */
diff --git a/src/soc/mediatek/common/pmif_spi.c b/src/soc/mediatek/common/pmif_spi.c
index e6ee1b7e8c..ed01c0d9a6 100644
--- a/src/soc/mediatek/common/pmif_spi.c
+++ b/src/soc/mediatek/common/pmif_spi.c
@@ -271,6 +271,11 @@ static void init_staupd(struct pmif *arb)
 			STAUPD_CTRL_PMIC0_EINT_STA, 1);
 }
 
+__weak void pmif_spi_setting(struct pmif *arb)
+{
+	/* do nothing, only for special setting of IC */
+}
+
 int pmif_spi_init(struct pmif *arb)
 {
 	pmif_spi_config(arb);
@@ -316,6 +321,8 @@ int pmif_spi_init(struct pmif *arb)
 	/* Enable GPS AUXADC HW 0 and 1 */
 	SET32_BITFIELDS(&arb->mtk_pmif->other_inf_en, INTGPSADCINF_EN, 0x3);
 
+	pmif_spi_setting(arb);
+
 	/* Set INIT_DONE */
 	write32(&arb->mtk_pmif->init_done, 0x1);
 
diff --git a/src/soc/mediatek/mt8189/Makefile.mk b/src/soc/mediatek/mt8189/Makefile.mk
index 3c506118b4..dfef6452f0 100644
--- a/src/soc/mediatek/mt8189/Makefile.mk
+++ b/src/soc/mediatek/mt8189/Makefile.mk
@@ -22,6 +22,9 @@ romstage-y += ../common/emi.c
 romstage-y += ../common/memory.c ../common/memory_test.c
 romstage-y += ../common/mmu_operations.c ../common/mmu_cmops.c
 romstage-y += ../common/pll.c pll.c
+romstage-y += ../common/pmif.c ../common/pmif_clk.c ../common/pmif_init.c pmif_clk.c
+romstage-y += ../common/pmif_spi.c pmif_spi.c
+romstage-y += ../common/pmif_spmi.c pmif_spmi.c
 
 ramstage-$(CONFIG_ARM64_USE_ARM_TRUSTED_FIRMWARE) += ../common/bl31.c
 ramstage-y += ../common/dramc_info.c
@@ -29,6 +32,9 @@ ramstage-y += ../common/emi.c
 ramstage-y += ../common/memory.c
 ramstage-y += ../common/mmu_operations.c ../common/mmu_cmops.c
 ramstage-y += ../common/mtcmos.c mtcmos.c
+ramstage-y += ../common/pmif.c ../common/pmif_clk.c ../common/pmif_init.c pmif_clk.c
+ramstage-y += ../common/pmif_spi.c pmif_spi.c
+ramstage-y += ../common/pmif_spmi.c pmif_spmi.c
 ramstage-y += soc.c
 ramstage-y += ../common/usb.c usb.c
 
diff --git a/src/soc/mediatek/mt8189/include/soc/addressmap.h b/src/soc/mediatek/mt8189/include/soc/addressmap.h
index 366a94ef16..0f257cc543 100644
--- a/src/soc/mediatek/mt8189/include/soc/addressmap.h
+++ b/src/soc/mediatek/mt8189/include/soc/addressmap.h
@@ -111,13 +111,13 @@ enum {
 	VLPCFG_REG_BASE			= IO_PHYS + 0x0C00C000,
 	DVFSRC_TOP_BASE			= IO_PHYS + 0x0C00F000,
 	VLP_CK_BASE			= IO_PHYS + 0x0C012000,
-	SPMI_MST_BASE			= IO_PHYS + 0x0C013000,
+	PMICSPI_MST_BASE		= IO_PHYS + 0x0C013000,
 	DEVAPC_VLP_AO_BASE		= IO_PHYS + 0x0C018000,
 	SCP_IIC_BASE			= IO_PHYS + 0x0C80A000,
 	SCP_BASE			= IO_PHYS + 0x0CB21000,
-	SPMI_MST_P_BASE			= IO_PHYS + 0x0CC00000,
-	PMIF_SPMI_BASE			= IO_PHYS + 0x0CC04000,
-	PMIF_SPMI_P_BASE		= IO_PHYS + 0x0CC06000,
+	SPMI_MST_BASE			= IO_PHYS + 0x0CC00000,
+	PMIF_SPI_BASE			= IO_PHYS + 0x0CC04000,
+	PMIF_SPMI_BASE			= IO_PHYS + 0x0CC06000,
 	SYSTIMER_BASE			= IO_PHYS + 0x0CC10000,
 	VAD_BASE			= IO_PHYS + 0x0E010000,
 	DEVAPC_MM_AO_BASE		= IO_PHYS + 0x0E820000,
diff --git a/src/soc/mediatek/mt8189/include/soc/pll.h b/src/soc/mediatek/mt8189/include/soc/pll.h
index fb8069c010..e875663f9a 100644
--- a/src/soc/mediatek/mt8189/include/soc/pll.h
+++ b/src/soc/mediatek/mt8189/include/soc/pll.h
@@ -123,16 +123,22 @@ struct mtk_vlp_regs {
 	u32 vlp_clk_cfg_30;
 	u32 vlp_clk_cfg_30_set;
 	u32 vlp_clk_cfg_30_clr;
-	u32 reserved3[13];
+	u32 reserved3[3];
+	u32 vlp_ulposc1_con0;
+	u32 vlp_ulposc1_con1;
+	u32 vlp_ulposc1_con2;
+	u32 reserved4[7];
 	u32 vlp_fqmtr_con[2];
 };
-
 check_member(mtk_vlp_regs, vlp_clk_cfg_update, 0x0004);
 check_member(mtk_vlp_regs, vlp_clk_cfg[0].set, 0x000C);
 check_member(mtk_vlp_regs, vlp_clk_cfg[0].clr, 0x0010);
 check_member(mtk_vlp_regs, vlp_clk_cfg[5].set, 0x0048);
 check_member(mtk_vlp_regs, vlp_clk_cfg[5].clr, 0x004C);
 check_member(mtk_vlp_regs, vlp_clk_cfg_30, 0x01F0);
+check_member(mtk_vlp_regs, vlp_ulposc1_con0, 0x0208);
+check_member(mtk_vlp_regs, vlp_ulposc1_con1, 0x020C);
+check_member(mtk_vlp_regs, vlp_ulposc1_con2, 0x0210);
 check_member(mtk_vlp_regs, vlp_fqmtr_con[0], 0x0230);
 
 struct mtk_topckgen_regs {
diff --git a/src/soc/mediatek/mt8189/include/soc/pmif.h b/src/soc/mediatek/mt8189/include/soc/pmif.h
new file mode 100644
index 0000000000..6a842c1f50
--- /dev/null
+++ b/src/soc/mediatek/mt8189/include/soc/pmif.h
@@ -0,0 +1,156 @@
+/* SPDX-License-Identifier: GPL-2.0-only OR MIT */
+
+#ifndef __SOC_MEDIATEK_MT8189_INCLUDE_SOC_PMIF_H__
+#define __SOC_MEDIATEK_MT8189_INCLUDE_SOC_PMIF_H__
+
+#include <device/mmio.h>
+#include <soc/addressmap.h>
+#include <soc/pmif_common.h>
+#include <types.h>
+
+/* indicate which number SW channel start, by project */
+#define PMIF_SPMI_SW_CHAN	BIT(7)
+#define PMIF_SPMI_INF		0x7FF
+
+struct mtk_pmif_regs {
+	u32 init_done;
+	u32 reserved1[5];
+	u32 inf_busy_sta;
+	u32 other_busy_sta_0;
+	u32 other_busy_sta_1;
+	u32 inf_en;
+	u32 other_inf_en;
+	u32 inf_cmd_per_0;
+	u32 inf_cmd_per_1;
+	u32 inf_cmd_per_2;
+	u32 inf_cmd_per_3;
+	u32 inf_max_bytecnt_per_0;
+	u32 inf_max_bytecnt_per_1;
+	u32 inf_max_bytecnt_per_2;
+	u32 inf_max_bytecnt_per_3;
+	u32 staupd_ctrl;
+	u32 reserved2[48];
+	u32 int_gps_auxadc_cmd_addr;
+	u32 int_gps_auxadc_cmd;
+	u32 int_gps_auxadc_rdata_addr;
+	u32 reserved3[13];
+	u32 arb_en;
+	u32 reserved4[34];
+	u32 lat_cnter_ctrl;
+	u32 lat_cnter_en;
+	u32 lat_limit_loading;
+	u32 lat_limit_0;
+	u32 lat_limit_1;
+	u32 lat_limit_2;
+	u32 lat_limit_3;
+	u32 lat_limit_4;
+	u32 lat_limit_5;
+	u32 lat_limit_6;
+	u32 lat_limit_7;
+	u32 lat_limit_8;
+	u32 lat_limit_9;
+	u32 reserved5[99];
+	u32 crc_ctrl;
+	u32 crc_sta;
+	u32 sig_mode;
+	u32 pmic_sig_addr;
+	u32 pmic_sig_val;
+	u32 reserved6[2];
+	u32 cmdissue_en;
+	u32 reserved7[10];
+	u32 timer_ctrl;
+	u32 timer_sta;
+	u32 sleep_protection_ctrl;
+	u32 reserved8[6];
+	u32 spi_mode_ctrl;
+	u32 reserved9[2];
+	u32 pmic_eint_sta_addr;
+	u32 reserved10[2];
+	u32 irq_event_en_0;
+	u32 irq_flag_raw_0;
+	u32 irq_flag_0;
+	u32 irq_clr_0;
+	u32 reserved11[244];
+	u32 swinf_0_acc;
+	u32 swinf_0_wdata_31_0;
+	u32 swinf_0_wdata_63_32;
+	u32 reserved12[2];
+	u32 swinf_0_rdata_31_0;
+	u32 swinf_0_rdata_63_32;
+	u32 reserved13[2];
+	u32 swinf_0_vld_clr;
+	u32 swinf_0_sta;
+	u32 reserved14[5];
+	u32 swinf_1_acc;
+	u32 swinf_1_wdata_31_0;
+	u32 swinf_1_wdata_63_32;
+	u32 reserved15[2];
+	u32 swinf_1_rdata_31_0;
+	u32 swinf_1_rdata_63_32;
+	u32 reserved16[2];
+	u32 swinf_1_vld_clr;
+	u32 swinf_1_sta;
+	u32 reserved17[5];
+	u32 swinf_2_acc;
+	u32 swinf_2_wdata_31_0;
+	u32 swinf_2_wdata_63_32;
+	u32 reserved18[2];
+	u32 swinf_2_rdata_31_0;
+	u32 swinf_2_rdata_63_32;
+	u32 reserved19[2];
+	u32 swinf_2_vld_clr;
+	u32 swinf_2_sta;
+	u32 reserved20[5];
+	u32 swinf_3_acc;
+	u32 swinf_3_wdata_31_0;
+	u32 swinf_3_wdata_63_32;
+	u32 reserved21[2];
+	u32 swinf_3_rdata_31_0;
+	u32 swinf_3_rdata_63_32;
+	u32 reserved22[2];
+	u32 swinf_3_vld_clr;
+	u32 swinf_3_sta;
+	u32 reserved23[133];
+};
+
+check_member(mtk_pmif_regs, inf_busy_sta, 0x18);
+check_member(mtk_pmif_regs, int_gps_auxadc_cmd_addr, 0x110);
+check_member(mtk_pmif_regs, arb_en, 0x0150);
+check_member(mtk_pmif_regs, lat_cnter_en, 0x1E0);
+check_member(mtk_pmif_regs, crc_ctrl, 0x39C);
+check_member(mtk_pmif_regs, cmdissue_en, 0x3B8);
+check_member(mtk_pmif_regs, timer_ctrl, 0x3E4);
+check_member(mtk_pmif_regs, spi_mode_ctrl, 0x408);
+check_member(mtk_pmif_regs, pmic_eint_sta_addr, 0x414);
+check_member(mtk_pmif_regs, irq_event_en_0, 0x420);
+check_member(mtk_pmif_regs, swinf_0_acc, 0x800);
+
+#define PMIF_SPI_HW_INF		0x181F
+#define PMIF_SPI_MD		BIT(5)
+#define PMIF_SPI_AP_SECURE	BIT(6)
+#define PMIF_SPI_AP		BIT(7)
+
+#define PMIF_SPI_INF_EN		(PMIF_SPI_HW_INF | PMIF_SPI_MD | PMIF_SPI_AP_SECURE | \
+				PMIF_SPI_AP)
+#define PMIF_SPI_ARB_EN		(PMIF_SPI_HW_INF | PMIF_SPI_MD | PMIF_SPI_AP_SECURE | \
+				PMIF_SPI_AP)
+
+#define PMIF_SPMI_AP_CHAN	(PMIF_SPMI_BASE + 0x880)
+#define PMIF_SPI_AP_CHAN	(PMIF_SPI_BASE + 0x880)
+
+enum {
+	PMIF_TARGET_FREQ_MHZ = 260,
+};
+
+/* calibation tolerance rate, unit: 0.1% */
+enum {
+	CAL_TOL_RATE = 40,
+	CAL_MAX_VAL = 0x7F,
+};
+
+#define FREQ_METER_ABIST_AD_OSC_CK	42
+#define CALI_DEFAULT_CAP_VALUE		0x3d
+
+#define FREQ_METER_VLP_OSC_CK	28
+
+#endif /*__SOC_MEDIATEK_MT8189_INCLUDE_SOC_PMIF_H__*/
diff --git a/src/soc/mediatek/mt8189/include/soc/spm_mtcmos.h b/src/soc/mediatek/mt8189/include/soc/spm_mtcmos.h
index f9b9f473a6..707b96371b 100644
--- a/src/soc/mediatek/mt8189/include/soc/spm_mtcmos.h
+++ b/src/soc/mediatek/mt8189/include/soc/spm_mtcmos.h
@@ -17,13 +17,17 @@ struct mtk_reg_cfg {
 struct mtk_vlpcfg_regs {
 	u32 reserved1;
 	u32 vlp_test_ck_ctrl;
-	u32 reserved2[130];
+	u32 reserved2[3];
+	u32 pmicw_clock_ctrl_set;
+	u32 pmicw_clock_ctrl_clr;
+	u32 reserved3[125];
 	u32 bus_vlp_topaxi_protecten;
 	u32 bus_vlp_topaxi_protecten_set;
 	u32 bus_vlp_topaxi_protecten_clr;
 	u32 bus_vlp_topaxi_protecten_sta1;
 };
 check_member(mtk_vlpcfg_regs, vlp_test_ck_ctrl, 0x0004);
+check_member(mtk_vlpcfg_regs, pmicw_clock_ctrl_clr, 0x0018);
 check_member(mtk_vlpcfg_regs, bus_vlp_topaxi_protecten, 0x0210);
 
 struct mtk_infracfg_ao_regs {
diff --git a/src/soc/mediatek/mt8189/pmif_clk.c b/src/soc/mediatek/mt8189/pmif_clk.c
new file mode 100644
index 0000000000..8a38f8568f
--- /dev/null
+++ b/src/soc/mediatek/mt8189/pmif_clk.c
@@ -0,0 +1,165 @@
+/* SPDX-License-Identifier: GPL-2.0-only OR MIT */
+
+#include <commonlib/helpers.h>
+#include <console/console.h>
+#include <delay.h>
+#include <device/mmio.h>
+#include <soc/pll.h>
+#include <soc/pll_common.h>
+#include <soc/pmif.h>
+#include <soc/pmif_clk_common.h>
+#include <soc/pmif_spmi.h>
+#include <soc/pmif_sw.h>
+#include <soc/spm.h>
+#include <soc/spm_mtcmos.h>
+
+#define ULPOSC1_CHECK_RETRY_COUNT 5
+#define ULPOSC1_HW_CALI_VAL 0x11f10054
+
+DEFINE_BITFIELD(CLK_EN, 18, 0)
+
+/* APMIXED, ULPOSC1_CON0 */
+DEFINE_BITFIELD(OSC1_CALI, 6, 0)
+DEFINE_BITFIELD(OSC1_IBAND, 13, 7)
+DEFINE_BITFIELD(OSC1_FBAND, 17, 14)
+DEFINE_BITFIELD(OSC1_DIV, 23, 18)
+DEFINE_BIT(OSC1_CP_EN, 24)
+
+/* APMIXED, ULPOSC1_CON1 */
+DEFINE_BITFIELD(OSC1_32KCALI, 7, 0)
+DEFINE_BITFIELD(OSC1_RSV1, 15, 8)
+DEFINE_BITFIELD(OSC1_RSV2, 23, 16)
+DEFINE_BITFIELD(OSC1_MOD, 25, 24)
+DEFINE_BIT(OSC1_DIV2_EN, 26)
+
+/* APMIXED, ULPOSC1_CON2 */
+DEFINE_BITFIELD(OSC1_BIAS, 7, 0)
+
+/* SPM, POWERON_CONFIG_EN */
+DEFINE_BIT(BCLK_CG_EN, 0)
+DEFINE_BITFIELD(PROJECT_CODE, 31, 16)
+
+/* SPM, ULPOSC_CON */
+DEFINE_BIT(ULPOSC_EN, 0)
+DEFINE_BITFIELD(ULPOSC_RST, 1, 0)
+
+/* INFRA, PMICW_CLOCK_CTRL */
+DEFINE_BITFIELD(PMIC_SYSCK_26M_SEL, 3, 0)
+
+DEFINE_BITFIELD(CLK_PWRAP_ULPOSC_SEL, 10, 8)
+DEFINE_BITFIELD(CLK_SPMI_P_MST_SEL, 19, 16)
+DEFINE_BIT(CLK_PWRAP_ULPOSC_INV, 12)
+DEFINE_BIT(CLK_SPMI_P_MST_INV, 20)
+DEFINE_BIT(PDN_PWRAP_ULPOSC, 15)
+DEFINE_BIT(PDN_SPMI_P_MST_ULPOSC, 23)
+
+/* TOPCKGEN, CLK_CFG_UPDATE1 */
+DEFINE_BITFIELD(CLK_CFG_UPDATE, 2, 1)
+
+DEFINE_BITFIELD(SPMI_MST_RST, 13, 10)
+DEFINE_BITFIELD(UNLOCK_KEY, 31, 24)
+
+static void pmif_ulposc_config(void)
+{
+	SET32_BITFIELDS(&mtk_vlpsys->vlp_clk_cfg_30_set, CLK_EN, 0x70000);
+	/* ULPOSC1_CON0 */
+	SET32_BITFIELDS(&mtk_vlpsys->vlp_ulposc1_con0, OSC1_CP_EN, 1, OSC1_DIV, 0xE,
+			OSC1_FBAND, 0, OSC1_IBAND, 0, OSC1_CALI, 0x3D);
+	/* ULPOSC1_CON1 */
+	SET32_BITFIELDS(&mtk_vlpsys->vlp_ulposc1_con1, OSC1_DIV2_EN, 1, OSC1_MOD, 0,
+			OSC1_RSV2, 0, OSC1_RSV1, 0, OSC1_32KCALI, 0);
+	/* ULPOSC1_CON2 */
+	SET32_BITFIELDS(&mtk_vlpsys->vlp_ulposc1_con2, OSC1_BIAS, 0x0);
+
+	udelay(15);
+}
+
+u32 pmif_get_ulposc_freq_mhz(u32 cali_val)
+{
+	u32 result = 0;
+
+	/* set calibration value */
+	SET32_BITFIELDS(&mtk_vlpsys->vlp_ulposc1_con0, OSC1_CALI, cali_val);
+	udelay(50);
+	result = mt_get_vlpck_freq(FREQ_METER_VLP_OSC_CK);
+
+	return result / 1000;
+}
+
+static void pmif_turn_on_ulposc(void)
+{
+	/* enable APB clock swinf */
+	if (!READ32_BITFIELD(&mtk_spm->poweron_config_set, BCLK_CG_EN))
+		SET32_BITFIELDS(&mtk_spm->poweron_config_set, BCLK_CG_EN, 1,
+				PROJECT_CODE, 0xb16);
+
+	SET32_BITFIELDS(&mtk_spm->ulposc_con, ULPOSC_EN, 1);
+	udelay(20);
+	SET32_BITFIELDS(&mtk_spm->ulposc_con, ULPOSC_RST, 0x3);
+	udelay(20);
+	SET32_BITFIELDS(&mtk_spm->ulposc_con, ULPOSC_EN, 1);
+	udelay(120);
+}
+
+static int pmif_init_ulposc(void)
+{
+	/* calibrate ULPOSC1 */
+	pmif_ulposc_config();
+	pmif_turn_on_ulposc();
+
+	return pmif_ulposc_cali(PMIF_TARGET_FREQ_MHZ);
+}
+
+int pmif_clk_init(void)
+{
+	bool sw_cali = false;
+	u32 cali_val;
+
+	for (int i = 0; i < ULPOSC1_CHECK_RETRY_COUNT; i++) {
+		cali_val = mt_get_vlpck_freq(FREQ_METER_VLP_OSC_CK) / 1000;
+		if (pmif_ulposc_check(cali_val, PMIF_TARGET_FREQ_MHZ) != 0) {
+			sw_cali = true;
+			break;
+		}
+	}
+
+	if (sw_cali) {
+		/* initialize pmif clock */
+		printk(BIOS_INFO, "Using SW calibration!\n");
+		if (pmif_init_ulposc())
+			return E_NODEV;
+	} else {
+		printk(BIOS_INFO, "Using HW calibration!\n");
+		/* set calibration value */
+		cali_val = read32p(ULPOSC1_HW_CALI_VAL);
+		printk(BIOS_INFO, "calibration pre value: %#x, PLL_ULPOSC1_CON0 value: %#x\n",
+		       cali_val, read32(&mtk_vlpsys->vlp_ulposc1_con0));
+		SET32_BITFIELDS(&mtk_vlpsys->vlp_ulposc1_con0, OSC1_CALI,
+				(cali_val >> 1) & 0x7F);
+		SET32_BITFIELDS(&mtk_vlpsys->vlp_clk_cfg_30_set, CLK_EN, 0x70000);
+		pmif_turn_on_ulposc();
+		printk(BIOS_INFO, "PLL_ULPOSC1_CON0: 0x%x\n",
+		       read32(&mtk_vlpsys->vlp_ulposc1_con0));
+	}
+
+	/* turn off pmic_cg_tmr, cg_ap, cg_md, cg_conn clock */
+	SET32_BITFIELDS(&mtk_vlpsys->vlp_clk_cfg[0].clr, CLK_PWRAP_ULPOSC_SEL, 0x7,
+			CLK_PWRAP_ULPOSC_INV, 0x1, PDN_PWRAP_ULPOSC, 0x1);
+	SET32_BITFIELDS(&mtk_vlpsys->vlp_clk_cfg[0].set, CLK_PWRAP_ULPOSC_SEL, 1);
+
+	SET32_BITFIELDS(&mtk_vlpsys->vlp_clk_cfg[0].clr, CLK_SPMI_P_MST_SEL, 0xf,
+			CLK_SPMI_P_MST_INV, 0x1, PDN_SPMI_P_MST_ULPOSC, 0x1);
+	SET32_BITFIELDS(&mtk_vlpsys->vlp_clk_cfg[0].set, CLK_SPMI_P_MST_SEL, 0x3);
+
+	SET32_BITFIELDS(&mtk_vlpsys->vlp_clk_cfg_update, CLK_CFG_UPDATE, 0x3);
+	/* use ULPOSC1 clock */
+	SET32_BITFIELDS(&mtk_vlpcfg->pmicw_clock_ctrl_clr, PMIC_SYSCK_26M_SEL, 0xf);
+
+	/* toggle pwrap & SPMI-P sw reset */
+	/* [10]: pmifspmi_m_rst_b [11]: pmifspmi_p_rst_b*/
+	/* [12]: spmi_p_mst_rst_b [13]: pmicspi_grst_b*/
+	SET32_BITFIELDS(&mtk_rug->wdt_vlp_swsysrst0, UNLOCK_KEY, 0x88, SPMI_MST_RST, 0xf);
+	SET32_BITFIELDS(&mtk_rug->wdt_vlp_swsysrst0, UNLOCK_KEY, 0x88, SPMI_MST_RST, 0x0);
+
+	return 0;
+}
diff --git a/src/soc/mediatek/mt8189/pmif_spi.c b/src/soc/mediatek/mt8189/pmif_spi.c
new file mode 100644
index 0000000000..91fb74b306
--- /dev/null
+++ b/src/soc/mediatek/mt8189/pmif_spi.c
@@ -0,0 +1,25 @@
+/* SPDX-License-Identifier: GPL-2.0-only OR MIT */
+
+#include <device/mmio.h>
+#include <gpio.h>
+#include <soc/pmif_spi.h>
+
+/* PMIF, SLEEP_PROTECTION_CTRL */
+DEFINE_BITFIELD(SPM_SLEEP_REQ_SEL, 1, 0)
+DEFINE_BITFIELD(SCP_SLEEP_REQ_SEL, 10, 9)
+
+void pmif_spi_iocfg(void)
+{
+	/* Set SoC SPI IO driving strength to 6 mA */
+	gpio_set_driving(GPIO(PWRAP_SPI_CK), GPIO_DRV_6_MA);
+	gpio_set_driving(GPIO(PWRAP_SPI_CSN), GPIO_DRV_6_MA);
+	gpio_set_driving(GPIO(PWRAP_SPI_MI), GPIO_DRV_6_MA);
+	gpio_set_driving(GPIO(PWRAP_SPI_MO), GPIO_DRV_6_MA);
+}
+
+void pmif_spi_setting(struct pmif *arb)
+{
+	SET32_BITFIELDS(&arb->mtk_pmif->sleep_protection_ctrl,
+			SPM_SLEEP_REQ_SEL, 1,
+			SCP_SLEEP_REQ_SEL, 1);
+}
diff --git a/src/soc/mediatek/mt8189/pmif_spmi.c b/src/soc/mediatek/mt8189/pmif_spmi.c
new file mode 100644
index 0000000000..1b0005947a
--- /dev/null
+++ b/src/soc/mediatek/mt8189/pmif_spmi.c
@@ -0,0 +1,46 @@
+/* SPDX-License-Identifier: GPL-2.0-only OR MIT */
+
+#include <console/console.h>
+#include <delay.h>
+#include <device/mmio.h>
+#include <gpio.h>
+#include <soc/pll.h>
+#include <soc/pmif_spmi.h>
+
+const struct spmi_device spmi_dev[] = {
+	{
+		.slvid = SPMI_SLAVE_7,
+		.type = SUB_PMIC,
+		.type_id = SUB_PMIC_ID,
+	},
+	{
+		.slvid = SPMI_SLAVE_8,
+		.type = BUCK_CPU,
+		.type_id = BUCK_CPU_ID,
+	},
+};
+
+const size_t spmi_dev_cnt = ARRAY_SIZE(spmi_dev);
+
+int spmi_config_master(void)
+{
+	/* Enable SPMI */
+	write32(&mtk_spmi_mst->mst_req_en, 1);
+
+	return 0;
+}
+
+void pmif_spmi_config(struct pmif *arb)
+{
+	/* Clear all cmd permission for per channel */
+	write32(&arb->mtk_pmif->inf_cmd_per_0, 0x888888AA);
+	write32(&arb->mtk_pmif->inf_cmd_per_1, 0x88888888);
+	write32(&arb->mtk_pmif->inf_cmd_per_2, 0x88888888);
+	write32(&arb->mtk_pmif->inf_cmd_per_3, 0x88888888);
+}
+
+void pmif_spmi_iocfg(void)
+{
+	gpio_set_driving(GPIO(SPMI_P_SCL), GPIO_DRV_10_MA);
+	gpio_set_driving(GPIO(SPMI_P_SDA), GPIO_DRV_10_MA);
+}

From 8a4b3e1346a2ad0803c3891aea9d26eb5da8ee15 Mon Sep 17 00:00:00 2001
From: Simon Yang <simon1.yang@intel.com>
Date: Mon, 12 May 2025 12:34:34 +0800
Subject: [PATCH 1054/3886] cpu/intel/microcode: Add error handling if
 microcode directory is empty
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

If the directory specified by CONFIG_CPU_INTEL_UCODE_SPLIT_BINARIES does
not contain any files, no build error will occur, and resulting coreboot
image will not include any microcode.

BUG=None
TEST="src/cpu/intel/microcode/Makefile.mk:16: *** "microcode-params is
empty. Ensure CONFIG_CPU_INTEL_UCODE_SPLIT_BINARIES is set correctly and
contains valid files.".  Stop."

Change-Id: I095d9a24cb473b528d85bf8325c06fd3dc055b74
Signed-off-by: Simon Yang <simon1.yang@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87636
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
---
 src/cpu/intel/microcode/Makefile.mk | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/src/cpu/intel/microcode/Makefile.mk b/src/cpu/intel/microcode/Makefile.mk
index 4e10a4b15f..e58842b108 100644
--- a/src/cpu/intel/microcode/Makefile.mk
+++ b/src/cpu/intel/microcode/Makefile.mk
@@ -11,6 +11,11 @@ ifeq ($(CONFIG_CPU_INTEL_MICROCODE_CBFS_SPLIT_BINS),y)
 microcode-params-dir := $(call strip_quotes,$(CONFIG_CPU_INTEL_UCODE_SPLIT_BINARIES))/
 microcode-params := $(shell find "$(microcode-params-dir)" -type f -exec basename {} \;)
 
+# Ensure microcode-params is not empty
+ifeq ($(microcode-params),)
+$(error "microcode-params is empty. Ensure CONFIG_CPU_INTEL_UCODE_SPLIT_BINARIES is set correctly and contains valid files.")
+endif
+
 # Make "cpu_microcode_$(CPUID).bin" file entry into the FIT table
 $(call add_intermediate, add_mcu_fit, set_fit_ptr $(IFITTOOL))
 	$(foreach params, $(microcode-params), $(shell $(IFITTOOL) -f $< -a -n $(params) -t 1 \

From ac4503d0ddafecac8a219dd53f7606ce81827c39 Mon Sep 17 00:00:00 2001
From: Pranava Y N <pranavayn@google.com>
Date: Wed, 14 May 2025 12:50:45 +0530
Subject: [PATCH 1055/3886] security/vboot: Introduce VBOOT_EC_SYNC_ESOL
 Kconfig option

This change introduces a new Kconfig option `VBOOT_EC_SYNC_ESOL`.
This config can be used to enable the display of early sign-of-life
(eSOL) during EC software sync whenever supported. When this config
is enabled, the EC sync must be performed later from the SoC code
(mainboard_romstage_entry() function) in order to display the eSOL
screen.

This change also adds a hook function vboot_show_ec_sync_esol()
to be run before performing the EC firmware image update during the EC
sync when `VBOOT_EARLY_EC_SYNC` is enabled. This function needs to be
implemented in SoC code when `VBOOT_EC_SYNC_ESOL` is enabled to display
the eSOL and notify the users about the firmware update.

AP log during EC firmware update in romstage:

```
[DEBUG]  Google Chrome EC: version:
[DEBUG]  	ro: pujjo-15217.861.0
[DEBUG]  	rw: pujjo-15217.861.0
[DEBUG]    running image: 1
[DEBUG]  FMAP: area FW_MAIN_A found @ 3a2000 (2312128 bytes)
[INFO ]  MMAP window: SPI flash base=0x3a0000, Host base=0xff3a0000, Size=0xc60000
[INFO ]  CBFS: Found 'ecrw.hash' @0x7f8c0 size 0x20 in mcache @0xfef97708
[INFO ]  VB2:vb2_digest_init() 32 bytes, hash algo 2, HW acceleration enabled
[INFO ]  VB2:check_ec_hash() Hexp RW(active): 62d1d55d26f33bd01a3676656148bedacf44189c81b195ec5488499074fe9bb0
[INFO ]  VB2:check_ec_hash()            Hmir: 62d1d55d26f33bd01a3676656148bedacf44189c81b195ec5488499074fe9bb0
[INFO ]  EC took 1124us to calculate image hash
[INFO ]  VB2:check_ec_hash() Heff RW(active): 8d111297eb53ba2289d256a769409bcbba4cf5b488fea97e40edcc9342a0f77f
[INFO ]  VB2:check_ec_hash() Heff != Hexp. Schedule update
[INFO ]  VB2:sync_ec() select_rw=RW(active)
[INFO ]  VB2:update_ec() Updating RW(active)...
[INFO ]  CBFS: Found 'ecrw' @0x1a9f80 size 0x40000 in mcache @0xfef97a9c
[INFO ]  VB2:vb2_digest_init() 262144 bytes, hash algo 2, HW acceleration enabled
[INFO ]  CBFS: Found 'ecrw.hash' @0x7f8c0 size 0x20 in mcache @0xfef97708
[INFO ]  VB2:vb2_digest_init() 32 bytes, hash algo 2, HW acceleration enabled
[INFO ]  VB2:check_ec_hash() Hexp RW(active): 62d1d55d26f33bd01a3676656148bedacf44189c81b195ec5488499074fe9bb0
[INFO ]  VB2:check_ec_hash()            Hmir: 62d1d55d26f33bd01a3676656148bedacf44189c81b195ec5488499074fe9bb0
[WARN ]  ec_hash_image: No valid hash (status=0 size=0). Computing...
[INFO ]  EC took 482169us to calculate image hash
[INFO ]  VB2:check_ec_hash() Heff RW(active): 62d1d55d26f33bd01a3676656148bedacf44189c81b195ec5488499074fe9bb0
[INFO ]  VB2:update_ec() Updated RW(active) successfully
[INFO ]  VB2:sync_ec() Rebooting to jump to new EC-RW
[INFO ]  VB2:vb2api_ec_sync() ec_sync_phase2(ctx) returned 0x1004
[INFO ]  EC Reboot requested. Doing cold reboot
```

BUG=b:412210635
TEST=Able to perform successful EC sync when `VBOOT_EARLY_EC_SYNC` is
selected.

Change-Id: Id853c73b54942ab35d4e3f019c1eddf4449c8d3c
Signed-off-by: Pranava Y N <pranavayn@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87668
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/security/vboot/Kconfig        |  8 ++++++++
 src/security/vboot/ec_sync.c      |  1 +
 src/security/vboot/vboot_common.h | 14 ++++++++++++++
 3 files changed, 23 insertions(+)

diff --git a/src/security/vboot/Kconfig b/src/security/vboot/Kconfig
index 7e291e0c70..ef7c24d879 100644
--- a/src/security/vboot/Kconfig
+++ b/src/security/vboot/Kconfig
@@ -286,6 +286,14 @@ config VBOOT_EARLY_EC_SYNC
 	  significantly impact boot time, as this operation will be performed
 	  later in the boot flow if it is disabled here.
 
+config VBOOT_EC_SYNC_ESOL
+	bool
+	default n
+	depends on VBOOT_EARLY_EC_SYNC && CHROMEOS_ENABLE_ESOL
+	help
+	  Enables the display of early sign-of-life (eSOL) when the EC is slow
+	  to update its firmware to inform the user that the update is happening.
+
 config VBOOT_EC_EFS
 	bool "Early firmware selection (EFS) EC"
 	default n
diff --git a/src/security/vboot/ec_sync.c b/src/security/vboot/ec_sync.c
index ac65dbd189..47c21c7c23 100644
--- a/src/security/vboot/ec_sync.c
+++ b/src/security/vboot/ec_sync.c
@@ -518,6 +518,7 @@ vb2_error_t vb2ex_ec_disable_jump(void)
  */
 vb2_error_t vb2ex_ec_update_image(enum vb2_firmware_selection select)
 {
+	vboot_show_ec_sync_esol();
 	return ec_update_image(select);
 }
 
diff --git a/src/security/vboot/vboot_common.h b/src/security/vboot/vboot_common.h
index 2399bf30ce..3e8e2edebd 100644
--- a/src/security/vboot/vboot_common.h
+++ b/src/security/vboot/vboot_common.h
@@ -74,6 +74,20 @@ static inline const struct cbfs_boot_device *vboot_get_cbfs_boot_device(void)
 }
 #endif
 
+/*
+ * This function is called before updating the EC firmware image.
+ * This API must be implemented in the SoC/mainboard code to enable
+ * early sign-of-life (eSOL) during EC firmware update.
+ */
+#if CONFIG(VBOOT_EC_SYNC_ESOL)
+void vboot_show_ec_sync_esol(void);
+#else
+static inline void vboot_show_ec_sync_esol(void)
+{
+	/* nop */
+}
+#endif
+
 void vboot_save_data(struct vb2_context *ctx);
 
 /*

From e6a7666bcdd4d3efe7098805da1add8e7422b08f Mon Sep 17 00:00:00 2001
From: Pranava Y N <pranavayn@google.com>
Date: Wed, 14 May 2025 13:22:02 +0530
Subject: [PATCH 1056/3886] cpu/intel/car: Skip EC software sync in common code

When `VBOOT_EC_SYNC_ESOL` config is enabled, the EC sync must be
performed later from the SoC code (mainboard_romstage_entry() function)
in order to display the eSOL screen.

AP log during EC firmware update in romstage without eSOL enabled:

```
[DEBUG]  Google Chrome EC: version:
[DEBUG]  	ro: pujjo-15217.861.0
[DEBUG]  	rw: pujjo-15217.861.0
[DEBUG]    running image: 1
[DEBUG]  FMAP: area FW_MAIN_A found @ 3a2000 (2312128 bytes)
[INFO ]  MMAP window: SPI flash base=0x3a0000, Host base=0xff3a0000, Size=0xc60000
[INFO ]  CBFS: Found 'ecrw.hash' @0x7f8c0 size 0x20 in mcache @0xfef97708
[INFO ]  VB2:vb2_digest_init() 32 bytes, hash algo 2, HW acceleration enabled
[INFO ]  VB2:check_ec_hash() Hexp RW(active): 62d1d55d26f33bd01a3676656148bedacf44189c81b195ec5488499074fe9bb0
[INFO ]  VB2:check_ec_hash()            Hmir: 62d1d55d26f33bd01a3676656148bedacf44189c81b195ec5488499074fe9bb0
[INFO ]  EC took 1124us to calculate image hash
[INFO ]  VB2:check_ec_hash() Heff RW(active): 8d111297eb53ba2289d256a769409bcbba4cf5b488fea97e40edcc9342a0f77f
[INFO ]  VB2:check_ec_hash() Heff != Hexp. Schedule update
[INFO ]  VB2:sync_ec() select_rw=RW(active)
[INFO ]  VB2:update_ec() Updating RW(active)...
[INFO ]  CBFS: Found 'ecrw' @0x1a9f80 size 0x40000 in mcache @0xfef97a9c
[INFO ]  VB2:vb2_digest_init() 262144 bytes, hash algo 2, HW acceleration enabled
[INFO ]  CBFS: Found 'ecrw.hash' @0x7f8c0 size 0x20 in mcache @0xfef97708
[INFO ]  VB2:vb2_digest_init() 32 bytes, hash algo 2, HW acceleration enabled
[INFO ]  VB2:check_ec_hash() Hexp RW(active): 62d1d55d26f33bd01a3676656148bedacf44189c81b195ec5488499074fe9bb0
[INFO ]  VB2:check_ec_hash()            Hmir: 62d1d55d26f33bd01a3676656148bedacf44189c81b195ec5488499074fe9bb0
[WARN ]  ec_hash_image: No valid hash (status=0 size=0). Computing...
[INFO ]  EC took 482169us to calculate image hash
[INFO ]  VB2:check_ec_hash() Heff RW(active): 62d1d55d26f33bd01a3676656148bedacf44189c81b195ec5488499074fe9bb0
[INFO ]  VB2:update_ec() Updated RW(active) successfully
[INFO ]  VB2:sync_ec() Rebooting to jump to new EC-RW
[INFO ]  VB2:vb2api_ec_sync() ec_sync_phase2(ctx) returned 0x1004
[INFO ]  EC Reboot requested. Doing cold reboot
```

BUG=b:412210635
TEST=Verify successful EC sync when `VBOOT_EARLY_EC_SYNC` is enabled
and `VBOOT_EC_SYNC_ESOL` is disabled.

Change-Id: Ib8958710bfbf01fb80405121af1c8dd43b4ed893
Signed-off-by: Pranava Y N <pranavayn@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87669
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
---
 src/cpu/intel/car/romstage.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/cpu/intel/car/romstage.c b/src/cpu/intel/car/romstage.c
index 63a83abbd7..285c2f48b2 100644
--- a/src/cpu/intel/car/romstage.c
+++ b/src/cpu/intel/car/romstage.c
@@ -56,7 +56,7 @@ void __noreturn romstage_main(void)
 
 	stack_canary_breakpoint_init();
 
-	if (CONFIG(VBOOT_EARLY_EC_SYNC))
+	if (CONFIG(VBOOT_EARLY_EC_SYNC) && !CONFIG(VBOOT_EC_SYNC_ESOL))
 		vboot_sync_ec();
 
 	/*

From 2033075753259190e84e89ece6462b9371cadeb9 Mon Sep 17 00:00:00 2001
From: Pranava Y N <pranavayn@google.com>
Date: Wed, 14 May 2025 13:50:06 +0530
Subject: [PATCH 1057/3886] intel/alderlake/romstage: Implement eSOL during EC
 software sync

Move EC software sync to the SoC code when `VBOOT_EC_SYNC_ESOL` config
is selected. This allows the early Sign-Of-Life (eSOL) to be
displayed during EC firmware update.

`VBOOT_EC_SYNC_SOL` is not coupled with `VBOOT_EARLY_EC_SYNC`,
therefore it can be enabled only for variants whose EC firmware
takes a long time (15-20s) to update.

This change also implements `vboot_show_ec_sync_esol()` function
that displays the eSOL during the update for Alder Lake devices.

AP log during EC firmware update with `VBOOT_EC_SYNC_ESOL` enabled:
```
[INFO ]  VB2:check_ec_hash() Heff != Hexp. Schedule update
[0.216229] DP PHY mode status not complete
[0.217189] DP PHY mode status not complete
[INFO ]  Informing user on-display of EC software sync.
[DEBUG]  FMAP: area COREBOOT found @ c0a000 (4153344 bytes)
[WARN ]  CBFS: 'preram_locales' not found.
[INFO ]  ux_locales_get_text: preram_locales not found.
[INFO ]  VB2:sync_ec() select_rw=RW(active)
[INFO ]  VB2:update_ec() Updating RW(active)...
[INFO ]  CBFS: Found 'ecrw' @0x1a9f80 size 0x40000 in mcache @0xfef97a9c
[INFO ]  VB2:vb2_digest_init() 262144 bytes, hash algo 2, HW acceleration enabled
[INFO ]  CBFS: Found 'ecrw.hash' @0x7f8c0 size 0x20 in mcache @0xfef97708
[INFO ]  VB2:vb2_digest_init() 32 bytes, hash algo 2, HW acceleration enabled
[INFO ]  VB2:check_ec_hash() Hexp RW(active): 62d1d55d26f33bd01a3676656148bedacf44189c81b195ec5488499074fe9bb0
[INFO ]  VB2:check_ec_hash()            Hmir: 62d1d55d26f33bd01a3676656148bedacf44189c81b195ec5488499074fe9bb0
[WARN ]  ec_hash_image: No valid hash (status=0 size=0). Computing...
[INFO ]  EC took 482169us to calculate image hash
[INFO ]  VB2:check_ec_hash() Heff RW(active): 62d1d55d26f33bd01a3676656148bedacf44189c81b195ec5488499074fe9bb0
[INFO ]  VB2:update_ec() Updated RW(active) successfully
[INFO ]  VB2:sync_ec() Rebooting to jump to new EC-RW
[INFO ]  VB2:vb2api_ec_sync() ec_sync_phase2(ctx) returned 0x1004
[INFO ]  EC Reboot requested. Doing cold reboot
```

BUG=b:412210635
TEST=Verify successful EC sync in romstage. Verify eSOL is displayed
during EC update on a nissa (Alder Lake) board by enabling
`VBOOT_EC_SYNC_ESOL` config.

Change-Id: I351d464f2ca64a3e60c52f88c8633e05556c5324
Signed-off-by: Pranava Y N <pranavayn@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87670
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/soc/intel/alderlake/romstage/romstage.c | 11 +++++++++++
 1 file changed, 11 insertions(+)

diff --git a/src/soc/intel/alderlake/romstage/romstage.c b/src/soc/intel/alderlake/romstage/romstage.c
index b1ac1caefa..d6a822e440 100644
--- a/src/soc/intel/alderlake/romstage/romstage.c
+++ b/src/soc/intel/alderlake/romstage/romstage.c
@@ -25,6 +25,7 @@
 #include <cpu/intel/cpu_ids.h>
 #include <string.h>
 #include <security/intel/txt/txt.h>
+#include <security/vboot/vboot_common.h>
 #include <soc/pcr_ids.h>
 
 #define PSF_UFS0_BASE_ADDRESS  0x280
@@ -172,6 +173,13 @@ void cse_board_reset(void)
 	early_graphics_stop();
 }
 
+#if (CONFIG(VBOOT_EC_SYNC_ESOL))
+void vboot_show_ec_sync_esol(void)
+{
+	ux_inform_user_of_update_operation("EC software sync");
+}
+#endif
+
 void mainboard_romstage_entry(void)
 {
 	struct chipset_power_state *ps = pmc_get_power_state();
@@ -194,6 +202,9 @@ void mainboard_romstage_entry(void)
 	if (!CONFIG(INTEL_TXT))
 		disable_intel_txt();
 
+	if (CONFIG(VBOOT_EARLY_EC_SYNC) && CONFIG(VBOOT_EC_SYNC_ESOL))
+		vboot_sync_ec();
+
 	/* Program to Disable UFS Controllers */
 	if (!is_devfn_enabled(PCH_DEVFN_UFS) &&
 			 (CONFIG(USE_UNIFIED_AP_FIRMWARE_FOR_UFS_AND_NON_UFS))) {

From a2010cf5eeea6ad4a154cfb13760092f0865af3f Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Micha=C5=82=20Kope=C4=87?= <michal.kopec@3mdeb.com>
Date: Mon, 14 Apr 2025 15:59:01 +0200
Subject: [PATCH 1058/3886] mb/novacustom/mtl-h/Makefile.mk: include tas5825m.c
 in the build
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

The file was mistakenly left out in the version that got merged, so
internal speakers wouldn't work.

TEST=Boot to Windows 11 and verify internal speakers work

Change-Id: I5529030bb91a41236772ac410096dc6bff00dd32
Signed-off-by: Michał Kopeć <michal.kopec@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87306
Reviewed-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/novacustom/mtl-h/Makefile.mk | 1 +
 1 file changed, 1 insertion(+)

diff --git a/src/mainboard/novacustom/mtl-h/Makefile.mk b/src/mainboard/novacustom/mtl-h/Makefile.mk
index 2607864470..869f5772b5 100644
--- a/src/mainboard/novacustom/mtl-h/Makefile.mk
+++ b/src/mainboard/novacustom/mtl-h/Makefile.mk
@@ -14,3 +14,4 @@ ramstage-y += variants/$(VARIANT_DIR)/gpio.c
 ramstage-y += variants/$(VARIANT_DIR)/ramstage.c
 
 ramstage-$(CONFIG_HAVE_ACPI_TABLES) += fadt.c
+ramstage-$(CONFIG_DRIVERS_I2C_TAS5825M) += variants/$(VARIANT_DIR)/tas5825m.c

From 42ac3ccff467d5059a25f085211a2540a1ba2335 Mon Sep 17 00:00:00 2001
From: Zhigang Qin <zhigang.qin@mediatek.corp-partner.google.com>
Date: Tue, 26 Nov 2024 18:42:38 +0800
Subject: [PATCH 1059/3886] soc/mediatek/mt8189: Add PMIC MT6359 driver

Add PMIC MT6359 initial settings and APIs.

BUG=b:379008996
BRANCH=none
TEST=build pass and driver log is normal
[DEBUG]  [pmif_ulposc_check] calibration done: cur=260M, CAL_RATE=40, target=260
[INFO ]  [Pass] dly:1, pol:0, sampl:0x2
[INFO ]  [Pass] dly:1, pol:0, sampl:0x2
[DEBUG]  pmic_efuse_setting: Set efuses in 10 msecs

Signed-off-by: Zhigang Qin <zhigang.qin@mediatek.corp-partner.google.com>
Change-Id: I71bf853075e7ff8419796988ebf17f3cd1b8e803
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87698
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
---
 src/soc/mediatek/mt8189/Makefile.mk |   2 +
 src/soc/mediatek/mt8189/mt6359p.c   | 199 ++++++++++++++++++++++++++++
 2 files changed, 201 insertions(+)
 create mode 100644 src/soc/mediatek/mt8189/mt6359p.c

diff --git a/src/soc/mediatek/mt8189/Makefile.mk b/src/soc/mediatek/mt8189/Makefile.mk
index dfef6452f0..a70918272a 100644
--- a/src/soc/mediatek/mt8189/Makefile.mk
+++ b/src/soc/mediatek/mt8189/Makefile.mk
@@ -21,6 +21,7 @@ romstage-y += ../common/dramc_param.c
 romstage-y += ../common/emi.c
 romstage-y += ../common/memory.c ../common/memory_test.c
 romstage-y += ../common/mmu_operations.c ../common/mmu_cmops.c
+romstage-y += ../common/mt6359p.c mt6359p.c
 romstage-y += ../common/pll.c pll.c
 romstage-y += ../common/pmif.c ../common/pmif_clk.c ../common/pmif_init.c pmif_clk.c
 romstage-y += ../common/pmif_spi.c pmif_spi.c
@@ -31,6 +32,7 @@ ramstage-y += ../common/dramc_info.c
 ramstage-y += ../common/emi.c
 ramstage-y += ../common/memory.c
 ramstage-y += ../common/mmu_operations.c ../common/mmu_cmops.c
+ramstage-y += ../common/mt6359p.c mt6359p.c
 ramstage-y += ../common/mtcmos.c mtcmos.c
 ramstage-y += ../common/pmif.c ../common/pmif_clk.c ../common/pmif_init.c pmif_clk.c
 ramstage-y += ../common/pmif_spi.c pmif_spi.c
diff --git a/src/soc/mediatek/mt8189/mt6359p.c b/src/soc/mediatek/mt8189/mt6359p.c
new file mode 100644
index 0000000000..0f899a337a
--- /dev/null
+++ b/src/soc/mediatek/mt8189/mt6359p.c
@@ -0,0 +1,199 @@
+/* SPDX-License-Identifier: GPL-2.0-only OR MIT */
+
+#include <soc/mt6359p.h>
+
+/*
+ * These values are used by MediaTek internally.
+ * We can find these registers in "MT6359 datasheet".
+ * The setting values are provided by MediaTek designers.
+ */
+
+static const struct pmic_setting init_setting[] = {
+	{0x20, 0xA, 0xA, 0},
+	{0x24, 0x1F00, 0x1F00, 0},
+	{0x30, 0x1, 0x1, 0},
+	{0x32, 0x1, 0x1, 0},
+	{0x94, 0x0, 0xFFFF, 0},
+	{0x10C, 0x10, 0x10, 0},
+	{0x112, 0x4, 0x4, 0},
+	{0x118, 0x8, 0x8, 0},
+	{0x14A, 0x20, 0x20, 0},
+	{0x198, 0x0, 0x1FF, 0},
+	{0x1B2, 0x3, 0x3, 0},
+	{0x3B0, 0x0, 0x300, 0},
+	{0x790, 0x3, 0x3, 0},
+	{0x796, 0x1750, 0x3FFF, 0},
+	{0x798, 0x1750, 0x3FFF, 0},
+	{0x7A6, 0xF800, 0xFC00, 0},
+	{0x7A8, 0x80, 0x280, 0},
+	{0x98A, 0x80, 0x80, 0},
+	{0x992, 0xF00, 0xF00, 0},
+	{0xA08, 0x1, 0x1, 0},
+	{0xA0C, 0x300, 0x300, 0},
+	{0xA10, 0x0, 0x4000, 0},
+	{0xA12, 0x1E0, 0x1E0, 0},
+	{0xA24, 0xFFFF, 0xFFFF, 0},
+	{0xA26, 0xFFE0, 0xFFE0, 0},
+	{0xA2C, 0xC0DF, 0xC0DF, 0},
+	{0xA2E, 0xEBE0, 0xEBE0, 0},
+	{0xA34, 0x8000, 0x8000, 0},
+	{0xA3C, 0x1500, 0x1F00, 0},
+	{0xA3E, 0x5641, 0x7FFF, 0},
+	{0xA40, 0x3C63, 0x7FFF, 0},
+	{0xA42, 0x9AE, 0x7FFF, 0},
+	{0xA44, 0x20E4, 0x7FFF, 0},
+	{0xA46, 0x25AD, 0x7FFF, 0},
+	{0xA48, 0x416A, 0x7FFF, 0},
+	{0xA4A, 0x3A0C, 0x7FFF, 0},
+	{0xA4C, 0x3A45, 0x7FFF, 0},
+	{0xA4E, 0x4E34, 0x7FFF, 0},
+	{0xA50, 0x7CDF, 0x7FFF, 0},
+	{0xA9C, 0x4000, 0x4000, 0},
+	{0xA9E, 0x2E11, 0xFF11, 0},
+	{0xF8C, 0x115, 0x115, 0},
+	{0x1188, 0x0, 0x8000, 0},
+	{0x1198, 0x13, 0x3FF, 0},
+	{0x119E, 0x6000, 0x7000, 0},
+	{0x11D4, 0x0, 0x2, 0},
+	{0x1212, 0x0, 0x2, 0},
+	{0x1224, 0x0, 0x2, 0},
+	{0x1238, 0x0, 0x2, 0},
+	{0x124A, 0x0, 0x2, 0},
+	{0x125C, 0x0, 0x2, 0},
+	{0x125E, 0x0, 0x8000, 0},
+	{0x1260, 0x1, 0xFFF, 0},
+	{0x1262, 0x4, 0x4, 0},
+	{0x1412, 0x8, 0x8, 0},
+	{0x148E, 0x38, 0x7F, 0},
+	{0x1492, 0xF1F, 0x7F7F, 0},
+	{0x150E, 0x1C, 0x7F, 0},
+	{0x1512, 0xF1F, 0x7F7F, 0},
+	{0x158E, 0x18, 0x7F, 0},
+	{0x1592, 0xF00, 0x7F00, 0},
+	{0x160E, 0x18, 0x7F, 0},
+	{0x168E, 0x18, 0x7F, 0},
+	{0x1692, 0xF1F, 0x7F7F, 0},
+	{0x170E, 0x1C, 0x7F, 0},
+	{0x1712, 0xF0F, 0x7F7F, 0},
+	{0x178E, 0x18, 0x7F, 0},
+	{0x1792, 0xF1F, 0x7F7F, 0},
+	{0x1918, 0x0, 0x3F3F, 0},
+	{0x191A, 0x0, 0x3F00, 0},
+	{0x198A, 0x5004, 0x502C, 0},
+	{0x198C, 0x3E, 0x3F, 0},
+	{0x198E, 0x1E0, 0x1E0, 0},
+	{0x1990, 0xFD, 0xFF, 0},
+	{0x1994, 0x10, 0x38, 0},
+	{0x1996, 0x2004, 0xA02C, 0},
+	{0x1998, 0x3E, 0x3F, 0},
+	{0x199A, 0xFB78, 0xFF78, 0},
+	{0x199E, 0x2, 0x7, 0},
+	{0x19A0, 0x1050, 0x10F1, 0},
+	{0x19A2, 0x3E, 0x3F, 0},
+	{0x19A4, 0xFD0F, 0xFF0F, 0},
+	{0x19A6, 0x20, 0xFF, 0},
+	{0x19AC, 0x4208, 0x4698, 0},
+	{0x19AE, 0x6E, 0x7E, 0},
+	{0x19B0, 0x3C00, 0x3C00, 0},
+	{0x19B4, 0x20FD, 0xFFFF, 0},
+	{0x1A08, 0x4208, 0x4698, 0},
+	{0x1A0A, 0x6E, 0x7E, 0},
+	{0x1A0C, 0x3C00, 0x3C00, 0},
+	{0x1A10, 0x20FD, 0xFFFF, 0},
+	{0x1A14, 0x4208, 0x4698, 0},
+	{0x1A16, 0x6E, 0x7E, 0},
+	{0x1A18, 0x3C00, 0x3C00, 0},
+	{0x1A1C, 0x20FD, 0xFFFF, 0},
+	{0x1A1E, 0x0, 0x200, 0},
+	{0x1A20, 0x4208, 0x4698, 0},
+	{0x1A22, 0x4A, 0x7E, 0},
+	{0x1A24, 0x3C00, 0x3C00, 0},
+	{0x1A28, 0x20FD, 0xFFFF, 0},
+	{0x1A2C, 0x20, 0x74, 0},
+	{0x1A2E, 0x1E, 0x1E, 0},
+	{0x1A30, 0x42, 0xFF, 0},
+	{0x1A32, 0x480, 0x7E0, 0},
+	{0x1A34, 0x20, 0x74, 0},
+	{0x1A36, 0x1E, 0x1E, 0},
+	{0x1A38, 0x42, 0xFF, 0},
+	{0x1A3A, 0x480, 0x7E0, 0},
+	{0x1A3C, 0x14C, 0x3CC, 0},
+	{0x1A3E, 0x23C, 0x3FC, 0},
+	{0x1A40, 0xC400, 0xFF00, 0},
+	{0x1A42, 0x80, 0xFF, 0},
+	{0x1A44, 0x702C, 0xFF2C, 0},
+	{0x1B0E, 0xF, 0xF, 0},
+	{0x1B10, 0x1, 0x1, 0},
+	{0x1B14, 0xFFFF, 0xFFFF, 0},
+	{0x1B1A, 0x3FFF, 0x3FFF, 0},
+	{0x1B32, 0x8, 0x8, 0},
+	{0x1B8A, 0x30, 0x8030, 0},
+	{0x1B9C, 0x10, 0x8010, 0},
+	{0x1BA0, 0x4000, 0x4000, 0},
+	{0x1BAE, 0x1410, 0x9C10, 0},
+	{0x1BB2, 0x2, 0x2, 0},
+	{0x1BC0, 0x10, 0x8010, 0},
+	{0x1BD2, 0x13, 0x8013, 0},
+	{0x1BE4, 0x10, 0x8010, 0},
+	{0x1C0A, 0x10, 0x8010, 0},
+	{0x1C1E, 0x10, 0x8010, 0},
+	{0x1C30, 0x10, 0x8010, 0},
+	{0x1C42, 0x10, 0x8010, 0},
+	{0x1C54, 0x32, 0x8033, 0},
+	{0x1C66, 0x10, 0x8010, 0},
+	{0x1C8A, 0x10, 0x8010, 0},
+	{0x1C8E, 0x4000, 0x4000, 0},
+	{0x1C9C, 0x10, 0x8010, 0},
+	{0x1CAE, 0x10, 0x8010, 0},
+	{0x1CC0, 0x10, 0x8010, 0},
+	{0x1CD2, 0x33, 0x8033, 0},
+	{0x1CE4, 0x33, 0x8033, 0},
+	{0x1D0A, 0x10, 0x8010, 0},
+	{0x1D1E, 0x10, 0x8010, 0},
+	{0x1D22, 0x4000, 0x4000, 0},
+	{0x1D30, 0x10, 0x8010, 0},
+	{0x1D34, 0x4000, 0x4000, 0},
+	{0x1D42, 0x30, 0x8030, 0},
+	{0x1D46, 0x4000, 0x4000, 0},
+	{0x1D54, 0x30, 0x8030, 0},
+	{0x1D66, 0x32, 0x8033, 0},
+	{0x1D8A, 0x10, 0x8010, 0},
+	{0x1D9C, 0x10, 0x8010, 0},
+	{0x1E8A, 0x10, 0x8010, 0},
+	{0x1E8E, 0x10, 0x7F, 0},
+	{0x1E92, 0xF1F, 0x7F7F, 0},
+	{0x1EAA, 0x10, 0x8010, 0},
+	{0x1EAE, 0x10, 0x7F, 0},
+	{0x1EB2, 0xF15, 0x7F7F, 0},
+	{0x1F0A, 0x10, 0x8010, 0},
+	{0x1F0E, 0x8, 0x7F, 0},
+	{0x1F12, 0xF15, 0x7F7F, 0},
+	{0x1F30, 0x10, 0x8010, 0},
+	{0x1F34, 0x8, 0x7F, 0},
+	{0x1F38, 0xF15, 0x7F7F, 0},
+	{0x200A, 0x8, 0xC, 0},
+	{0x202C, 0x8, 0xC, 0},
+	{0x208C, 0x100, 0xF00, 0},
+	{0x209C, 0x80, 0x1E0, 0},
+
+	/*
+	 * 1. Set VS2_VOTER_VOSEL = 1.35V
+	 * 2. Clear VS2_VOTER
+	 * 3. Set VS2_VOSEL = 1.45V
+	 */
+	{0x18b0, 0x2C, 0x7F, 0},
+	{0x18aa, 0x0, 0xFFF, 0},
+	{0x18b4, 0x34, 0x7F, 0},
+};
+
+void mt6359p_init_setting(void)
+{
+	for (size_t i = 0; i < ARRAY_SIZE(init_setting); i++)
+		mt6359p_write_field(init_setting[i].addr, init_setting[i].val,
+			init_setting[i].mask, init_setting[i].shift);
+}
+
+void mt6359p_lp_setting(void)
+{
+	/* For mt8189, this function is implemented in ATF, so make it no-op here. */
+}

From 2a3fd0659dd0d63bece43cce5153988b7fc2a0fe Mon Sep 17 00:00:00 2001
From: Zhigang Qin <zhigang.qin@mediatek.corp-partner.google.com>
Date: Tue, 26 Nov 2024 18:45:38 +0800
Subject: [PATCH 1060/3886] soc/mediatek/mt8189: Add PMIC MT6315 driver

Add PMIC MT6315 initial settings.

BUG=b:379008996
BRANCH=none
TEST=build pass and driver log is normal
[DEBUG]  [pmif_ulposc_check] calibration done: cur=260M, CAL_RATE=40, target=260
[INFO ]  [Pass] dly:1, pol:0, sampl:0x2
[INFO ]  [Pass] dly:1, pol:0, sampl:0x2
[DEBUG]  pmic_efuse_setting: Set efuses in 10 msecs

Signed-off-by: Zhigang Qin <zhigang.qin@mediatek.corp-partner.google.com>
Change-Id: Id57f782e1b7fb20fd1e93d36caa03cbb89ecd4ef
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87699
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
---
 src/soc/mediatek/mt8189/Makefile.mk |   2 +
 src/soc/mediatek/mt8189/mt6315.c    | 209 ++++++++++++++++++++++++++++
 2 files changed, 211 insertions(+)
 create mode 100644 src/soc/mediatek/mt8189/mt6315.c

diff --git a/src/soc/mediatek/mt8189/Makefile.mk b/src/soc/mediatek/mt8189/Makefile.mk
index a70918272a..c0501d45a1 100644
--- a/src/soc/mediatek/mt8189/Makefile.mk
+++ b/src/soc/mediatek/mt8189/Makefile.mk
@@ -21,6 +21,7 @@ romstage-y += ../common/dramc_param.c
 romstage-y += ../common/emi.c
 romstage-y += ../common/memory.c ../common/memory_test.c
 romstage-y += ../common/mmu_operations.c ../common/mmu_cmops.c
+romstage-y += ../common/mt6315.c mt6315.c
 romstage-y += ../common/mt6359p.c mt6359p.c
 romstage-y += ../common/pll.c pll.c
 romstage-y += ../common/pmif.c ../common/pmif_clk.c ../common/pmif_init.c pmif_clk.c
@@ -32,6 +33,7 @@ ramstage-y += ../common/dramc_info.c
 ramstage-y += ../common/emi.c
 ramstage-y += ../common/memory.c
 ramstage-y += ../common/mmu_operations.c ../common/mmu_cmops.c
+ramstage-y += ../common/mt6315.c mt6315.c
 ramstage-y += ../common/mt6359p.c mt6359p.c
 ramstage-y += ../common/mtcmos.c mtcmos.c
 ramstage-y += ../common/pmif.c ../common/pmif_clk.c ../common/pmif_init.c pmif_clk.c
diff --git a/src/soc/mediatek/mt8189/mt6315.c b/src/soc/mediatek/mt8189/mt6315.c
new file mode 100644
index 0000000000..9968569008
--- /dev/null
+++ b/src/soc/mediatek/mt8189/mt6315.c
@@ -0,0 +1,209 @@
+/* SPDX-License-Identifier: GPL-2.0-only OR MIT */
+
+#include <soc/mt6315.h>
+
+/*
+ * These values are used by MediaTek internally.
+ * We can find these registers in "MT6315 datasheet v1.3.pdf".
+ * The setting values are provided by MediaTek designers.
+ */
+
+static const struct mt6315_setting slave7_init_setting[] = {
+	/* disable magic key protection */
+	{0x3A9, 0x63, 0xFF, 0},
+	{0x3A8, 0x15, 0xFF, 0},
+	{0x3A0, 0x9C, 0xFF, 0},
+	{0x39F, 0xEA, 0xFF, 0},
+	{0x993, 0x47, 0xFF, 0},
+	{0x992, 0x29, 0xFF, 0},
+	{0x1418, 0x55, 0xFF, 0},
+	{0x1417, 0x43, 0xFF, 0},
+	{0x3A2, 0x2A, 0xFF, 0},
+	{0x3A1, 0x7C, 0xFF, 0},
+
+	{0x13, 0x2, 0x2, 0},
+	{0x15, 0x1F, 0x1F, 0},
+	{0x22, 0x12, 0x12, 0},
+	{0x8A, 0x6, 0xF, 0},
+	{0x10B, 0x3, 0x3, 0},
+	{0x38B, 0x4, 0xFF, 0},
+	{0x3AD, 0xA2, 0xFF, 0},
+	{0xA07, 0x0, 0x1, 0},
+	{0x1457, 0x0, 0xFF, 0},
+	{0x997, 0xF, 0x7F, 0},
+	{0x999, 0xF0, 0xF0, 0},
+	{0x9A0, 0x2, 0x1F, 0},
+	{0x9A1, 0x2, 0x1F, 0},
+	{0x9A2, 0x0, 0x1F, 0},
+	{0x9A3, 0x3, 0x1F, 0},
+	{0xA0C, 0x0, 0x78, 0},
+	{0xA11, 0x1, 0x1F, 0},
+	{0xA1A, 0x1F, 0x1F, 0},
+	{0x1487, 0x58, 0xFF, 0},
+	{0x148B, 0x1, 0x7F, 0},
+	{0x148C, 0x4, 0x7F, 0},
+	{0x1507, 0x58, 0xFF, 0},
+	{0x150B, 0x1, 0x7F, 0},
+	{0x150C, 0x4, 0x7F, 0},
+	{0x1587, 0xA8, 0xFF, 0},
+	{0x158B, 0x4, 0x7F, 0},
+	{0x158C, 0x4, 0x7F, 0},
+	{0x1607, 0x51, 0xFF, 0},
+	{0x160B, 0x4, 0x7F, 0},
+	{0x160C, 0x4, 0x7F, 0},
+	{0x1687, 0x22, 0x76, 0},
+	{0x1688, 0xE, 0x2F, 0},
+	{0x1689, 0xA1, 0xE1, 0},
+	{0x168A, 0x79, 0x7F, 0},
+	{0x168B, 0x12, 0x3F, 0},
+	{0x168D, 0xC, 0xC, 0},
+	{0x168E, 0xD7, 0xFF, 0},
+	{0x168F, 0x81, 0xFF, 0},
+	{0x1690, 0x3, 0x3F, 0},
+	{0x1691, 0x22, 0x76, 0},
+	{0x1692, 0xE, 0x2F, 0},
+	{0x1693, 0xA1, 0xE1, 0},
+	{0x1694, 0x79, 0x7F, 0},
+	{0x1695, 0x12, 0x3F, 0},
+	{0x1697, 0xC, 0xC, 0},
+	{0x1698, 0xD7, 0xFF, 0},
+	{0x1699, 0x81, 0xFF, 0},
+	{0x169A, 0x3, 0x3F, 0},
+	{0x169B, 0x20, 0x70, 0},
+	{0x169C, 0xE, 0x2F, 0},
+	{0x169D, 0x81, 0xC1, 0},
+	{0x169E, 0xF8, 0xF8, 0},
+	{0x169F, 0x12, 0x3F, 0},
+	{0x16A1, 0xC, 0xC, 0},
+	{0x16A2, 0xDB, 0xFF, 0},
+	{0x16A3, 0xA1, 0xFF, 0},
+	{0x16A4, 0x3, 0xF, 0},
+	{0x16A5, 0x20, 0x70, 0},
+	{0x16A6, 0xE, 0x2F, 0},
+	{0x16A7, 0x80, 0xC1, 0},
+	{0x16A8, 0xF8, 0xF8, 0},
+	{0x16A9, 0x12, 0x3F, 0},
+	{0x16AB, 0xC, 0xC, 0},
+	{0x16AC, 0xDB, 0xFF, 0},
+	{0x16AD, 0xA1, 0xFF, 0},
+	{0x16AE, 0x1, 0xF, 0},
+	{0x16CE, 0x8, 0x8, 0},
+	/* enable magic key protection */
+	{0x3A9, 0, 0xFF, 0},
+	{0x3A8, 0, 0xFF, 0},
+	{0x3A0, 0, 0xFF, 0},
+	{0x39F, 0, 0xFF, 0},
+	{0x993, 0, 0xFF, 0},
+	{0x992, 0, 0xFF, 0},
+	{0x1418, 0, 0xFF, 0},
+	{0x1417, 0, 0xFF, 0},
+	{0x3a2, 0, 0xFF, 0},
+	{0x3a1, 0, 0xFF, 0},
+};
+
+static const struct mt6315_setting slave8_init_setting[] = {
+	/* disable magic key protection */
+	{0x3A9, 0x63, 0xFF, 0},
+	{0x3A8, 0x15, 0xFF, 0},
+	{0x3A0, 0x9C, 0xFF, 0},
+	{0x39F, 0xEA, 0xFF, 0},
+	{0x993, 0x47, 0xFF, 0},
+	{0x992, 0x29, 0xFF, 0},
+	{0x1418, 0x55, 0xFF, 0},
+	{0x1417, 0x43, 0xFF, 0},
+	{0x3a2, 0x2A, 0xFF, 0},
+	{0x3a1, 0x7C, 0xFF, 0},
+
+	{0x13, 0x2, 0x2, 0},
+	{0x15, 0x1F, 0x1F, 0},
+	{0x22, 0x12, 0x12, 0},
+	{0x8A, 0x6, 0xF, 0},
+	{0x10B, 0x3, 0x3, 0},
+	{0x38B, 0x4, 0xFF, 0},
+	{0x3AD, 0xA2, 0xFF, 0},
+	{0xA07, 0x0, 0x1, 0},
+	{0x1457, 0x0, 0xFF, 0},
+	{0x997, 0xB, 0x7F, 0},
+	{0x999, 0xF0, 0xF0, 0},
+	{0x9A0, 0x1, 0x1F, 0},
+	{0x9A1, 0x1, 0x1F, 0},
+	{0x9A2, 0x0, 0x1F, 0},
+	{0x9A3, 0x1, 0x1F, 0},
+	{0xA0C, 0x0, 0x78, 0},
+	{0xA11, 0x1, 0x1F, 0},
+	{0xA1A, 0x1F, 0x1F, 0},
+	{0x1487, 0x58, 0xFF, 0},
+	{0x148B, 0x1, 0x7F, 0},
+	{0x148C, 0x4, 0x7F, 0},
+	{0x1507, 0x58, 0xFF, 0},
+	{0x150B, 0x1, 0x7F, 0},
+	{0x150C, 0x4, 0x7F, 0},
+	{0x1587, 0x92, 0xFF, 0},
+	{0x158B, 0x4, 0x7F, 0},
+	{0x158C, 0x4, 0x7F, 0},
+	{0x1607, 0x58, 0xFF, 0},
+	{0x160B, 0x1, 0x7F, 0},
+	{0x160C, 0x4, 0x7F, 0},
+	{0x1687, 0x22, 0x76, 0},
+	{0x1688, 0xE, 0x2F, 0},
+	{0x1689, 0xA1, 0xE1, 0},
+	{0x168A, 0x79, 0x7F, 0},
+	{0x168B, 0x12, 0x3F, 0},
+	{0x168D, 0xC, 0xC, 0},
+	{0x168E, 0xD7, 0xFF, 0},
+	{0x168F, 0x81, 0xFF, 0},
+	{0x1690, 0x3, 0x3F, 0},
+	{0x1691, 0x22, 0x76, 0},
+	{0x1692, 0xE, 0x2F, 0},
+	{0x1693, 0xA1, 0xE1, 0},
+	{0x1694, 0x79, 0x7F, 0},
+	{0x1695, 0x12, 0x3F, 0},
+	{0x1697, 0xC, 0xC, 0},
+	{0x1698, 0xD7, 0xFF, 0},
+	{0x1699, 0x81, 0xFF, 0},
+	{0x169A, 0x3, 0x3F, 0},
+	{0x169B, 0x20, 0x70, 0},
+	{0x169C, 0xE, 0x2F, 0},
+	{0x169D, 0x81, 0xC1, 0},
+	{0x169E, 0xF8, 0xF8, 0},
+	{0x169F, 0x12, 0x3F, 0},
+	{0x16A1, 0xC, 0xC, 0},
+	{0x16A2, 0xDB, 0xFF, 0},
+	{0x16A3, 0xA1, 0xFF, 0},
+	{0x16A4, 0x3, 0xF, 0},
+	{0x16A5, 0x22, 0x76, 0},
+	{0x16A6, 0xE, 0x2F, 0},
+	{0x16A7, 0xA1, 0xE1, 0},
+	{0x16A8, 0x79, 0x7F, 0},
+	{0x16A9, 0x12, 0x3F, 0},
+	{0x16AB, 0xC, 0xC, 0},
+	{0x16AC, 0xD7, 0xFF, 0},
+	{0x16AD, 0x81, 0xFF, 0},
+	{0x16AE, 0x3, 0x3F, 0},
+	{0x16C7, 0x8, 0x8, 0},
+	/* enable magic key protection */
+	{0x3A9, 0, 0xFF, 0},
+	{0x3A8, 0, 0xFF, 0},
+	{0x3A0, 0, 0xFF, 0},
+	{0x39F, 0, 0xFF, 0},
+	{0x993, 0, 0xFF, 0},
+	{0x992, 0, 0xFF, 0},
+	{0x1418, 0, 0xFF, 0},
+	{0x1417, 0, 0xFF, 0},
+	{0x3a2, 0, 0xFF, 0},
+	{0x3a1, 0, 0xFF, 0},
+};
+
+static inline void write_field(enum spmi_slave slvid, const struct mt6315_setting *setting)
+{
+	mt6315_write_field(slvid, setting->addr, setting->val, setting->mask, setting->shift);
+}
+
+void mt6315_init_setting(void)
+{
+	for (size_t i = 0; i < ARRAY_SIZE(slave7_init_setting); i++)
+		write_field(SPMI_SLAVE_7, &slave7_init_setting[i]);
+
+	for (size_t i = 0; i < ARRAY_SIZE(slave8_init_setting); i++)
+		write_field(SPMI_SLAVE_8, &slave8_init_setting[i]);
+}

From 12d6d0606cd038d83c6e24fbb4ed33fcb95b3efe Mon Sep 17 00:00:00 2001
From: Zhigang Qin <zhigang.qin@mediatek.corp-partner.google.com>
Date: Tue, 26 Nov 2024 18:46:46 +0800
Subject: [PATCH 1061/3886] mb/google/skywalker: Initialize PMIC in romstage

Add PMIC function support.

BUG=b:379008996
BRANCH=none
TEST=build pass and driver log is normal:
[DEBUG]  [pmif_ulposc_check] calibration done: cur=260M, CAL_RATE=40, target=260
[INFO ]  [Pass] dly:1, pol:0, sampl:0x2
[INFO ]  [Pass] dly:1, pol:0, sampl:0x2
[DEBUG]  pmic_efuse_setting: Set efuses in 10 msecs

Signed-off-by: Zhigang Qin <zhigang.qin@mediatek.corp-partner.google.com>
Change-Id: I4f2601bbb15807a70348bd2aa9246630adf6e0aa
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87700
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
---
 src/mainboard/google/skywalker/romstage.c | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/src/mainboard/google/skywalker/romstage.c b/src/mainboard/google/skywalker/romstage.c
index 74cfb1bbd6..75175ce94a 100644
--- a/src/mainboard/google/skywalker/romstage.c
+++ b/src/mainboard/google/skywalker/romstage.c
@@ -2,8 +2,14 @@
 
 #include <arch/stages.h>
 #include <soc/emi.h>
+#include <soc/mt6315.h>
+#include <soc/mt6359p.h>
+#include <soc/pmif.h>
 
 void platform_romstage_main(void)
 {
+	mtk_pmif_init();
+	mt6315_init();
+	mt6359p_init();
 	mtk_dram_init();
 }

From b288aaee85cf71d352f9004d55fd27753eaac3be Mon Sep 17 00:00:00 2001
From: Shunxi Zhang <ot_shunxi.zhang@mediatek.com>
Date: Thu, 23 Jan 2025 13:18:25 +0800
Subject: [PATCH 1062/3886] soc/mediatek/mt8189: Use common RTC driver MT6359

Use common RTC driver MT6359.

BUG=b:379008996
BRANCH=none
TEST=build pass

Change-Id: I8a9f94dcbdc32eb242d51327703dad91eb9a88ab
Signed-off-by: Shunxi Zhang <ot_shunxi.zhang@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87706
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
---
 src/soc/mediatek/mt8189/Makefile.mk       |  2 ++
 src/soc/mediatek/mt8189/include/soc/rtc.h | 12 ++++++++++++
 2 files changed, 14 insertions(+)
 create mode 100644 src/soc/mediatek/mt8189/include/soc/rtc.h

diff --git a/src/soc/mediatek/mt8189/Makefile.mk b/src/soc/mediatek/mt8189/Makefile.mk
index c0501d45a1..915728ba1a 100644
--- a/src/soc/mediatek/mt8189/Makefile.mk
+++ b/src/soc/mediatek/mt8189/Makefile.mk
@@ -27,6 +27,7 @@ romstage-y += ../common/pll.c pll.c
 romstage-y += ../common/pmif.c ../common/pmif_clk.c ../common/pmif_init.c pmif_clk.c
 romstage-y += ../common/pmif_spi.c pmif_spi.c
 romstage-y += ../common/pmif_spmi.c pmif_spmi.c
+romstage-y += ../common/rtc.c ../common/rtc_osc_init.c ../common/rtc_mt6359p.c
 
 ramstage-$(CONFIG_ARM64_USE_ARM_TRUSTED_FIRMWARE) += ../common/bl31.c
 ramstage-y += ../common/dramc_info.c
@@ -39,6 +40,7 @@ ramstage-y += ../common/mtcmos.c mtcmos.c
 ramstage-y += ../common/pmif.c ../common/pmif_clk.c ../common/pmif_init.c pmif_clk.c
 ramstage-y += ../common/pmif_spi.c pmif_spi.c
 ramstage-y += ../common/pmif_spmi.c pmif_spmi.c
+ramstage-y += ../common/rtc.c ../common/rtc_mt6359p.c ../common/rtc_osc_init.c
 ramstage-y += soc.c
 ramstage-y += ../common/usb.c usb.c
 
diff --git a/src/soc/mediatek/mt8189/include/soc/rtc.h b/src/soc/mediatek/mt8189/include/soc/rtc.h
new file mode 100644
index 0000000000..28464a90af
--- /dev/null
+++ b/src/soc/mediatek/mt8189/include/soc/rtc.h
@@ -0,0 +1,12 @@
+/* SPDX-License-Identifier: GPL-2.0-only OR MIT */
+
+#ifndef __SOC_MEDIATEK_MT8189_INCLUDE_SOC_RTC_H__
+#define __SOC_MEDIATEK_MT8189_INCLUDE_SOC_RTC_H__
+
+#include <soc/pmif.h>
+#include <soc/rtc_common.h>
+#include <soc/rtc_mt6359p.h>
+#include <soc/rtc_reg_common.h>
+#include <stdbool.h>
+
+#endif /* __SOC_MEDIATEK_MT8189_INCLUDE_SOC_RTC_H__ */

From 24ab31f477cf2ae6ab29ea6123d5afc4b0c9aade Mon Sep 17 00:00:00 2001
From: Shunxi Zhang <ot_shunxi.zhang@mediatek.com>
Date: Thu, 23 Jan 2025 18:28:37 +0800
Subject: [PATCH 1063/3886] mb/google/skywalker: Enable RTC boot init

Enable RTC to get correct timestamp.

BUG=b:379008996
BRANCH=none
TEST=build passed and check RTC time is increasing by command 'cat
/proc/driver/rtc'

skywalker-rev1 ~ # cat /proc/driver/rtc
rtc_time        : 12:36:25
skywalker-rev1 ~ # cat /proc/driver/rtc
rtc_time        : 12:36:28

Change-Id: Idfe6185b9e2ad8d116da454c8d95ddeb32a5998d
Signed-off-by: Shunxi Zhang <ot_shunxi.zhang@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87707
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/google/skywalker/Kconfig    | 1 +
 src/mainboard/google/skywalker/romstage.c | 2 ++
 2 files changed, 3 insertions(+)

diff --git a/src/mainboard/google/skywalker/Kconfig b/src/mainboard/google/skywalker/Kconfig
index a05f4bbdd6..4287636c82 100644
--- a/src/mainboard/google/skywalker/Kconfig
+++ b/src/mainboard/google/skywalker/Kconfig
@@ -28,6 +28,7 @@ config BOARD_SPECIFIC_OPTIONS
 	select EC_GOOGLE_CHROMEEC_SPI
 	select FW_CONFIG
 	select FW_CONFIG_SOURCE_CHROMEEC_CBI
+	select RTC
 
 config MAINBOARD_DIR
 	string
diff --git a/src/mainboard/google/skywalker/romstage.c b/src/mainboard/google/skywalker/romstage.c
index 75175ce94a..1ba948ee9e 100644
--- a/src/mainboard/google/skywalker/romstage.c
+++ b/src/mainboard/google/skywalker/romstage.c
@@ -5,11 +5,13 @@
 #include <soc/mt6315.h>
 #include <soc/mt6359p.h>
 #include <soc/pmif.h>
+#include <soc/rtc.h>
 
 void platform_romstage_main(void)
 {
 	mtk_pmif_init();
 	mt6315_init();
 	mt6359p_init();
+	rtc_boot();
 	mtk_dram_init();
 }

From d5bfa1c697da09a3b56c686332119271548d5eb9 Mon Sep 17 00:00:00 2001
From: Mike Lin <mike.lin@mediatek.corp-partner.google.com>
Date: Thu, 2 Jan 2025 23:36:00 +0800
Subject: [PATCH 1064/3886] soc/mediatek/common: Add DPM V2 non-broadcast mode
 support

MT8196 DPM uses broadcast mode for loading DPM bin files. This means
that both dpm.dm and dpm.pm files only need to be loaded once, and
all channels will apply them.

In contrast, MT8189 DPM uses non-broadcast mode, which requires
loading the dpm.dm and dpm.pm files for each channel individually.

The original dpm_v2.c only supports broadcast mode. In this commit,
add support for non-broadcast mode to increase code reusability.

BUG=b:379008996
BRANCH=none
TEST=build passed.

Signed-off-by: Mike Lin <mike.lin@mediatek.corp-partner.google.com>
Change-Id: I599f06c5669f5fd8623966a1c03767ea02b6bd15
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87736
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/soc/mediatek/common/Kconfig              |  6 +++
 src/soc/mediatek/common/dpm_v1.c             |  3 ++
 src/soc/mediatek/common/dpm_v2.c             | 42 +++++++++++++++++---
 src/soc/mediatek/common/include/soc/dpm_v2.h |  1 +
 src/soc/mediatek/mt8196/Kconfig              |  1 +
 5 files changed, 47 insertions(+), 6 deletions(-)

diff --git a/src/soc/mediatek/common/Kconfig b/src/soc/mediatek/common/Kconfig
index 55ea5ecd44..63a11d0ca8 100644
--- a/src/soc/mediatek/common/Kconfig
+++ b/src/soc/mediatek/common/Kconfig
@@ -67,6 +67,12 @@ config DPM_FOUR_CHANNEL
 	help
 	  This option enables four channel configuration for DPM.
 
+config DPM_BROADCAST
+	bool
+	default n
+	help
+	  This option enables the DPM Broadcast function, applicable only for dpm_v2.
+
 config MTK_DFD
 	bool "Enable MediaTek DFD (Design For Debug) settings"
 	help
diff --git a/src/soc/mediatek/common/dpm_v1.c b/src/soc/mediatek/common/dpm_v1.c
index d059d02a80..31bdbca66e 100644
--- a/src/soc/mediatek/common/dpm_v1.c
+++ b/src/soc/mediatek/common/dpm_v1.c
@@ -4,6 +4,9 @@
 #include <soc/dpm_v1.h>
 #include <soc/mcu_common.h>
 
+_Static_assert(!CONFIG(DPM_BROADCAST),
+	       "DPM_BROADCAST not implemented in dpm_v1");
+
 static struct mtk_mcu dpm_mcu[] = {
 	{
 		.firmware_name = CONFIG_DPM_DM_FIRMWARE,
diff --git a/src/soc/mediatek/common/dpm_v2.c b/src/soc/mediatek/common/dpm_v2.c
index 4df8bd0e13..673a328842 100644
--- a/src/soc/mediatek/common/dpm_v2.c
+++ b/src/soc/mediatek/common/dpm_v2.c
@@ -4,14 +4,34 @@
 #include <soc/dpm_v2.h>
 #include <soc/mcu_common.h>
 
-static struct mtk_mcu dpm_mcu[] = {
+_Static_assert(!CONFIG(DPM_FOUR_CHANNEL),
+	       "DPM_FOUR_CHANNEL not implemented in dpm_v2");
+
+static struct mtk_mcu dpm_mcu_ch0[] = {
 	{
 		.firmware_name = CONFIG_DPM_DM_FIRMWARE,
 		.run_address = (void *)DPM_DM_SRAM_BASE,
+		.priv = (void *)DPM_CFG_CH0,
 	},
 	{
 		.firmware_name = CONFIG_DPM_PM_FIRMWARE,
 		.run_address = (void *)DPM_PM_SRAM_BASE,
+		.priv = (void *)DPM_CFG_CH0,
+		.reset = dpm_reset,
+	},
+	{},
+};
+
+static struct mtk_mcu dpm_mcu_ch1[] = {
+	{
+		.firmware_name = CONFIG_DPM_DM_FIRMWARE,
+		.run_address = (void *)DPM_DM_SRAM_BASE2,
+		.priv = (void *)DPM_CFG_CH1,
+	},
+	{
+		.firmware_name = CONFIG_DPM_PM_FIRMWARE,
+		.run_address = (void *)DPM_PM_SRAM_BASE2,
+		.priv = (void *)DPM_CFG_CH1,
 		.reset = dpm_reset,
 	},
 	{},
@@ -19,20 +39,30 @@ static struct mtk_mcu dpm_mcu[] = {
 
 void dpm_reset(struct mtk_mcu *mcu)
 {
+	uintptr_t dpm_cfg_reg = (uintptr_t)(mcu->priv);
 	/* free RST */
-	setbits32p(DPM_CFG_CH0 + DPM_RST_OFFSET, DPM_SW_RSTN);
+	setbits32p(dpm_cfg_reg + DPM_RST_OFFSET, DPM_SW_RSTN);
 }
 
 int dpm_init(void)
 {
-	u32 dramc_wbr_backup = read32p(DRAMC_WBR);
+	u32 dramc_wbr_backup;
 
-	setbits32p(DRAMC_WBR, ENABLE_DRAMC_WBR_MASK);
+	if (CONFIG(DPM_BROADCAST)) {
+		dramc_wbr_backup = read32p(DRAMC_WBR);
+		setbits32p(DRAMC_WBR, ENABLE_DRAMC_WBR_MASK);
+	}
 
-	if (dpm_init_mcu(dpm_mcu))
+	if (dpm_init_mcu(dpm_mcu_ch0))
 		return -1;
 
-	write32p(DRAMC_WBR, dramc_wbr_backup);
+	if (!CONFIG(DPM_BROADCAST)) {
+		if (dpm_init_mcu(dpm_mcu_ch1))
+			return -1;
+	}
+
+	if (CONFIG(DPM_BROADCAST))
+		write32p(DRAMC_WBR, dramc_wbr_backup);
 
 	return 0;
 }
diff --git a/src/soc/mediatek/common/include/soc/dpm_v2.h b/src/soc/mediatek/common/include/soc/dpm_v2.h
index 1588622d67..e4714906c7 100644
--- a/src/soc/mediatek/common/include/soc/dpm_v2.h
+++ b/src/soc/mediatek/common/include/soc/dpm_v2.h
@@ -10,6 +10,7 @@
 #define DPM_SW_RSTN		BIT(0)
 
 #define DPM_CFG_CH0		DPM_CFG_BASE
+#define DPM_CFG_CH1		DPM_CFG_BASE2
 #define DPM_BARGS_CH0_REG0	(DPM_CFG_BASE + 0x6004)
 #define DPM_BARGS_CH0_REG1	(DPM_CFG_BASE + 0x6008)
 #define DRAMC_WBR		(INFRACFG_AO_BASE + 0x0b4)
diff --git a/src/soc/mediatek/mt8196/Kconfig b/src/soc/mediatek/mt8196/Kconfig
index 9d27a5f77f..90c85007ef 100644
--- a/src/soc/mediatek/mt8196/Kconfig
+++ b/src/soc/mediatek/mt8196/Kconfig
@@ -13,6 +13,7 @@ config SOC_MEDIATEK_MT8196
 	select MEDIATEK_DRAM_BLOB_FAST_INIT
 	select USE_CBMEM_DRAM_INFO
 	select SOC_MEDIATEK_COMMON
+	select DPM_BROADCAST
 	select FLASH_DUAL_IO_READ
 	select ARM64_USE_ARCH_TIMER
 	select PCI

From 3f8702a0d6934d602b68cd718f565fd1e60b3ff7 Mon Sep 17 00:00:00 2001
From: Vince Liu <vince-wl.liu@mediatek.corp-partner.google.com>
Date: Thu, 26 Dec 2024 10:57:27 +0800
Subject: [PATCH 1065/3886] soc/mediatek/mt8189: Add DPM v2 driver
 configuration

MT8189 equips DPM hardware which is similar to MT8196.
Therefore, we use the same DPM v2 loader to run the blob.

BUG=b:379008996
BRANCH=none
TEST=Make & Boot up pass and see log
mtk_init_mcu: Loaded (and reset) dpm.dm in 19 msecs (1004 bytes)
mtk_init_mcu: Loaded (and reset) dpm.pm in 19 msecs (36588 bytes)
mtk_init_mcu: Loaded (and reset) dpm.dm in 7 msecs (1004 bytes)
mtk_init_mcu: Loaded (and reset) dpm.pm in 19 msecs (36588 bytes)

Signed-off-by: Mike.Lin <mike.lin@mediatek.corp-partner.google.com>
Change-Id: I616cc0880d2db3f94b2a960b11d04974af1e94ef
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87662
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
---
 src/soc/mediatek/mt8189/Kconfig     | 12 ++++++++++++
 src/soc/mediatek/mt8189/Makefile.mk | 13 +++++++++++++
 2 files changed, 25 insertions(+)

diff --git a/src/soc/mediatek/mt8189/Kconfig b/src/soc/mediatek/mt8189/Kconfig
index 1bbcb49344..8d5fcc69e0 100644
--- a/src/soc/mediatek/mt8189/Kconfig
+++ b/src/soc/mediatek/mt8189/Kconfig
@@ -24,4 +24,16 @@ config VBOOT
 	select VBOOT_SEPARATE_VERSTAGE
 	select VBOOT_RETURN_FROM_VERSTAGE
 
+config DPM_DM_FIRMWARE
+	string
+	default "dpm.dm"
+	help
+	  The file name of the MediaTek DPM DM firmware.
+
+config DPM_PM_FIRMWARE
+	string
+	default "dpm.pm"
+	help
+	  The file name of the MediaTek DPM PM firmware.
+
 endif
diff --git a/src/soc/mediatek/mt8189/Makefile.mk b/src/soc/mediatek/mt8189/Makefile.mk
index 915728ba1a..c870dec5c7 100644
--- a/src/soc/mediatek/mt8189/Makefile.mk
+++ b/src/soc/mediatek/mt8189/Makefile.mk
@@ -30,8 +30,10 @@ romstage-y += ../common/pmif_spmi.c pmif_spmi.c
 romstage-y += ../common/rtc.c ../common/rtc_osc_init.c ../common/rtc_mt6359p.c
 
 ramstage-$(CONFIG_ARM64_USE_ARM_TRUSTED_FIRMWARE) += ../common/bl31.c
+ramstage-y += ../common/dpm.c ../common/dpm_v2.c
 ramstage-y += ../common/dramc_info.c
 ramstage-y += ../common/emi.c
+ramstage-y += ../common/mcu.c
 ramstage-y += ../common/memory.c
 ramstage-y += ../common/mmu_operations.c ../common/mmu_cmops.c
 ramstage-y += ../common/mt6315.c mt6315.c
@@ -51,6 +53,17 @@ CPPFLAGS_common += -Isrc/soc/mediatek/common/include
 
 MT8189_BLOB_DIR := 3rdparty/blobs/soc/mediatek/mt8189
 
+firmware-files := \
+	$(CONFIG_DPM_DM_FIRMWARE) \
+	$(CONFIG_DPM_PM_FIRMWARE)
+
+$(foreach fw, $(call strip_quotes,$(firmware-files)), \
+	$(eval $(fw)-file := $(MT8189_BLOB_DIR)/$(fw)) \
+	$(eval $(fw)-type := raw) \
+	$(eval $(fw)-compression := LZ4) \
+	$(if $(wildcard $($(fw)-file)), $(eval cbfs-files-y += $(fw)), ) \
+)
+
 DRAM_CBFS := $(CONFIG_CBFS_PREFIX)/dram
 $(DRAM_CBFS)-file := $(MT8189_BLOB_DIR)/dram.elf
 $(DRAM_CBFS)-type := stage

From 61f043de4a6705a49a37abfb09b62c03461382a2 Mon Sep 17 00:00:00 2001
From: Vince Liu <vince-wl.liu@mediatek.corp-partner.google.com>
Date: Wed, 11 Dec 2024 15:12:07 +0800
Subject: [PATCH 1066/3886] mb/google/skywalker: Initialize DPM in ramstage

Add initialization of DPM driver for DRAM low power mode.

BUG=b:379008996
BRANCH=none
TEST=Boot up pass and see log
3200 LPDDR5 chan0(x16) rank0: memory test pass
3200 LPDDR5 chan0(x16) rank1: memory test pass
3200 LPDDR5 chan1(x16) rank0: memory test pass
3200 LPDDR5 chan1(x16) rank1: memory test pass

Signed-off-by: Mike Lin <mike.lin@mediatek.corp-partner.google.com>
Change-Id: I3b72b892d56623e7f3ec2dccfad073a908b51119
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87663
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
---
 src/mainboard/google/skywalker/mainboard.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/src/mainboard/google/skywalker/mainboard.c b/src/mainboard/google/skywalker/mainboard.c
index 257faa1f10..44549f46e5 100644
--- a/src/mainboard/google/skywalker/mainboard.c
+++ b/src/mainboard/google/skywalker/mainboard.c
@@ -1,10 +1,12 @@
 /* SPDX-License-Identifier: GPL-2.0-only OR MIT */
 
 #include <device/device.h>
+#include <soc/dpm_v2.h>
 #include <soc/usb.h>
 
 static void mainboard_init(struct device *dev)
 {
+	dpm_init();
 	setup_usb_host();
 }
 

From 0baf47e03b2231974ed4366c2bde47292e28ea13 Mon Sep 17 00:00:00 2001
From: alokagarwal <alok.agarwal@intel.corp-partner.google.com>
Date: Wed, 26 Mar 2025 09:52:57 +0530
Subject: [PATCH 1067/3886] vc/intel/fsp/ptl: Update header files from FSP
 3071_00 to FSP 3144_01
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Update header files for FSP for Panther Lake platform to version
3144_01, with the previous version being 3071_00.

Changes include:
- Update UPD Offset in FspmUpd.h and FspsUpd.h.
- Update MemInfoHob.h:
  - Update MEMORY_INFO_DATA_HOB, child structures and their data for
    SMBIOS type 16/17 design change.
  - Add new variable PprFailingChannelBitMask to
    MEMORY_INFO_DATA_HOB.
- Update soc/intel/pantherlake/romstage/romstage.c: Refactor coreboot
  to match MEMORY_INFO_DATA_HOB data structure.

BUG=b:414734316
TEST=Able to build google/fatcat. Verify that the updates to
MEMORY_INFO_DATA_HOB and its child structures for SMBIOS type 16/17
design changes are correctly integrated from FSP 3144_01 onwards.

Change-Id: I054e419ef23ada67347750e7a68014c2bb112199
Signed-off-by: Alok Agarwal <alok.agarwal@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87000
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: <srinivas.kulkarni@intel.com>
Reviewed-by: Jayvik Desai <jayvik@google.com>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Pranava Y N <pranavayn@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
---
 src/soc/intel/pantherlake/romstage/romstage.c |   4 +-
 .../intel/fsp/fsp2_0/pantherlake/FspmUpd.h    | 257 +++++++-----------
 .../intel/fsp/fsp2_0/pantherlake/FspsUpd.h    | 140 +++++-----
 .../intel/fsp/fsp2_0/pantherlake/MemInfoHob.h |  65 +++--
 4 files changed, 212 insertions(+), 254 deletions(-)

diff --git a/src/soc/intel/pantherlake/romstage/romstage.c b/src/soc/intel/pantherlake/romstage/romstage.c
index 46be7b96f9..a6fd887123 100644
--- a/src/soc/intel/pantherlake/romstage/romstage.c
+++ b/src/soc/intel/pantherlake/romstage/romstage.c
@@ -103,10 +103,10 @@ static void save_dimm_info(void)
 						dram_part_num,
 						dram_part_num_len,
 						serial_num,
-						meminfo_hob->DataWidth,
+						src_dimm->DataWidth,
 						meminfo_hob->VddVoltage[memProfNum],
 						meminfo_hob->EccSupport,
-					src_dimm->MfgId,
+					src_dimm->MfgId.Data,
 					src_dimm->SpdModuleType,
 					node,
 					meminfo_hob->MaximumMemoryClockSpeed);
diff --git a/src/vendorcode/intel/fsp/fsp2_0/pantherlake/FspmUpd.h b/src/vendorcode/intel/fsp/fsp2_0/pantherlake/FspmUpd.h
index 55dc43cdfa..b87b5a9ca7 100644
--- a/src/vendorcode/intel/fsp/fsp2_0/pantherlake/FspmUpd.h
+++ b/src/vendorcode/intel/fsp/fsp2_0/pantherlake/FspmUpd.h
@@ -747,77 +747,9 @@ typedef struct {
 **/
   UINT8                       RXUNMATCHEDCAL;
 
-/** Offset 0x0227 - Hard Post Package Repair
-  Enables/Disable Hard Post Package Repair
-  $EN_DIS
+/** Offset 0x0227 - Reserved
 **/
-  UINT8                       PPR;
-
-/** Offset 0x0228 - Reserved
-**/
-  UINT8                       Reserved17;
-
-/** Offset 0x0229 - PPR Run Once
-  When Eanble, PPR will run only once and then is disabled at next training cycle
-  $EN_DIS
-**/
-  UINT8                       PprRunOnce;
-
-/** Offset 0x022A - PPR Run During Fastboot
-  When Eanble, PPR will run during fastboot
-  $EN_DIS
-**/
-  UINT8                       PprRunAtFastboot;
-
-/** Offset 0x022B - PPR Repair Type
-  PPR Repair Type: 0:Do not Repair (Default), 1:Soft Repair, 2:Hard Repair
-  0:Do not Repair (Default), 1:Soft Repair, 2:Hard Repair
-**/
-  UINT8                       PprRepairType;
-
-/** Offset 0x022C - PPR Error Injection
-  When Eanble, PPR will inject bad rows during testing
-  $EN_DIS
-**/
-  UINT8                       PprErrorInjection;
-
-/** Offset 0x022D - PPR Repair Controller
-  PPR repair controller: User chooses to force repair specifc address
-**/
-  UINT8                       PprRepairController;
-
-/** Offset 0x022E - PPR Repair Channel
-  PPR repair Channel: User chooses to force repair specifc address
-**/
-  UINT8                       PprRepairChannel;
-
-/** Offset 0x022F - PPR Repair Dimm
-  PPR repair Dimm: User chooses to force repair specifc address
-**/
-  UINT8                       PprRepairDimm;
-
-/** Offset 0x0230 - PPR Repair Rank
-  PPR repair Rank: User chooses to force repair specifc address
-**/
-  UINT8                       PprRepairRank;
-
-/** Offset 0x0231 - Reserved
-**/
-  UINT8                       Reserved18[3];
-
-/** Offset 0x0234 - PPR Repair Row
-  PPR repair Row: User chooses to force repair specifc address
-**/
-  UINT32                      PprRepairRow;
-
-/** Offset 0x0238 - Reserved
-**/
-  UINT8                      Reserved19[8];
-
-/** Offset 0x0240 - PPR Repair BankGroup
-  PPR repair BankGroup: User chooses to force repair specifc address
-**/
-  UINT8                       PprRepairBankGroup;
+  UINT8                       Reserved17[26];
 
 /** Offset 0x0241 - LVR Auto Trim
   Enable/disable LVR Auto Trim
@@ -839,7 +771,7 @@ typedef struct {
 
 /** Offset 0x0244 - Reserved
 **/
-  UINT8                       Reserved20[3];
+  UINT8                       Reserved18[3];
 
 /** Offset 0x0247 - RDDQODTT
   Enable/disable Read DQ ODT Training
@@ -1051,7 +983,7 @@ typedef struct {
 
 /** Offset 0x026A - Reserved
 **/
-  UINT8                       Reserved21;
+  UINT8                       Reserved19;
 
 /** Offset 0x026B - DIMM SPD Alias Test
   Enables/Disable DIMM SPD Alias Test
@@ -1079,7 +1011,7 @@ typedef struct {
 
 /** Offset 0x026F - Reserved
 **/
-  UINT8                       Reserved22[2];
+  UINT8                       Reserved20[2];
 
 /** Offset 0x0271 - Ibecc
   In-Band ECC Support
@@ -1095,7 +1027,7 @@ typedef struct {
 
 /** Offset 0x0273 - Reserved
 **/
-  UINT8                       Reserved23;
+  UINT8                       Reserved21;
 
 /** Offset 0x0274 - IbeccOperationMode
   In-Band ECC Operation Mode
@@ -1111,7 +1043,7 @@ typedef struct {
 
 /** Offset 0x027D - Reserved
 **/
-  UINT8                       Reserved24;
+  UINT8                       Reserved22;
 
 /** Offset 0x027E - IbeccProtectedRegionBases
   IBECC Protected Region Bases per IBECC instance
@@ -1186,7 +1118,7 @@ typedef struct {
 
 /** Offset 0x02A8 - Reserved
 **/
-  UINT8                       Reserved25[2];
+  UINT8                       Reserved23[2];
 
 /** Offset 0x02AA - Read Voltage Centering 1D
   Enable/Disable Read Voltage Centering 1D
@@ -1274,7 +1206,7 @@ typedef struct {
 
 /** Offset 0x02B8 - Reserved
 **/
-  UINT8                       Reserved26;
+  UINT8                       Reserved24;
 
 /** Offset 0x02B9 - DDR5 MR7 WICA support
   Enable if DDR5 DRAM Device supports MR7 WICA 0.5 tCK offset alignment
@@ -1291,7 +1223,7 @@ typedef struct {
 
 /** Offset 0x02BB - Reserved
 **/
-  UINT8                       Reserved27;
+  UINT8                       Reserved25;
 
 /** Offset 0x02BC - Ch Hash Mask
   Set the BIT(s) to be included in the XOR function. NOTE BIT mask corresponds to
@@ -1301,7 +1233,7 @@ typedef struct {
 
 /** Offset 0x02BE - Reserved
 **/
-  UINT8                       Reserved28;
+  UINT8                       Reserved26;
 
 /** Offset 0x02BF - Throttler CKEMin Timer
   Timer value for CKEMin, range[255;0]. Req'd min of SC_ROUND_T + BYTE_LENGTH (4).
@@ -1380,7 +1312,7 @@ typedef struct {
 
 /** Offset 0x02CB - Reserved
 **/
-  UINT8                       Reserved29[5];
+  UINT8                       Reserved27[5];
 
 /** Offset 0x02D0 - DDR Phy Safe Mode Support
   DdrSafeMode[0]: Basic PM Features, DdrSafeMode[1]: Spine Gating, DdrSafeMode[2]:
@@ -1402,7 +1334,7 @@ typedef struct {
 
 /** Offset 0x02D6 - Reserved
 **/
-  UINT8                       Reserved30[8];
+  UINT8                       Reserved28[8];
 
 /** Offset 0x02DE - RMTLoopCount
   Specifies the Loop Count to be used during Rank Margin Tool Testing. 0 - AUTO
@@ -1438,7 +1370,7 @@ typedef struct {
 
 /** Offset 0x02E7 - Reserved
 **/
-  UINT8                       Reserved31;
+  UINT8                       Reserved29;
 
 /** Offset 0x02E8 - Margin limit check L2
   Margin limit check L2 threshold: <b>100=Default</b>
@@ -1453,7 +1385,7 @@ typedef struct {
 
 /** Offset 0x02EB - Reserved
 **/
-  UINT8                       Reserved32;
+  UINT8                       Reserved30;
 
 /** Offset 0x02EC - LP5 Command Pins Mapping
   BitMask where bits [3:0] are Controller 0 Channel [3:0] and bits [7:4] are Controller
@@ -1475,7 +1407,17 @@ typedef struct {
 
 /** Offset 0x02EF - Reserved
 **/
-  UINT8                       Reserved33[64];
+  UINT8                       Reserved31[43];
+
+/** Offset 0x031A - Read Vref Decap Training*
+  Enable/Disable Read Timing Centering Training with SR stress*
+  $EN_DIS
+**/
+  UINT8                       RDTCIDLE;
+
+/** Offset 0x031B - Reserved
+**/
+  UINT8                       Reserved32[20];
 
 /** Offset 0x032F - Board Type
   MrcBoardType, Options are 0=Mobile/Mobile Halo, 1=Desktop/DT Halo, 5=ULT/ULX/Mobile
@@ -1499,7 +1441,7 @@ typedef struct {
 
 /** Offset 0x0341 - Reserved
 **/
-  UINT8                       Reserved34;
+  UINT8                       Reserved33;
 
 /** Offset 0x0342 - Skip external display device scanning
   Enable: Do not scan for external display device, Disable (Default): Scan external
@@ -1627,7 +1569,7 @@ typedef struct {
 
 /** Offset 0x04D6 - Reserved
 **/
-  UINT8                       Reserved35[2];
+  UINT8                       Reserved34[2];
 
 /** Offset 0x04D8 - DMIC<N> ClkA Pin Muxing (N - DMIC number)
   Determines DMIC<N> ClkA Pin muxing. See  GPIO_*_MUXING_DMIC<N>_CLKA_*
@@ -1642,7 +1584,7 @@ typedef struct {
 
 /** Offset 0x04E1 - Reserved
 **/
-  UINT8                       Reserved36[3];
+  UINT8                       Reserved35[3];
 
 /** Offset 0x04E4 - DMIC<N> Data Pin Muxing
   Determines DMIC<N> Data Pin muxing. See GPIO_*_MUXING_DMIC<N>_DATA_*
@@ -1656,7 +1598,7 @@ typedef struct {
 
 /** Offset 0x04F3 - Reserved
 **/
-  UINT8                       Reserved37[117];
+  UINT8                       Reserved36[117];
 
 /** Offset 0x0568 - Enable HD Audio SoundWire#N Link
   Enable/disable HD Audio SNDW#N link. Muxed with HDA.
@@ -1677,7 +1619,7 @@ typedef struct {
 
 /** Offset 0x056F - Reserved
 **/
-  UINT8                       Reserved38[45];
+  UINT8                       Reserved37[45];
 
 /** Offset 0x059C - iDisplay Audio Codec disconnection
   0: Not disconnected, enumerable, 1: Disconnected SDI, not enumerable.
@@ -1687,7 +1629,7 @@ typedef struct {
 
 /** Offset 0x059D - Reserved
 **/
-  UINT8                       Reserved39[5];
+  UINT8                       Reserved38[5];
 
 /** Offset 0x05A2 - HDA Power/Clock Gating (PGD/CGD)
   Enable/Disable HD Audio Power and Clock Gating(POR: Enable). 0: PLATFORM_POR, 1:
@@ -1698,7 +1640,7 @@ typedef struct {
 
 /** Offset 0x05A3 - Reserved
 **/
-  UINT8                       Reserved40;
+  UINT8                       Reserved39;
 
 /** Offset 0x05A4 - Audio Sub System IDs
   Set default Audio Sub System IDs. If its set to 0 then value from Strap is used.
@@ -1707,7 +1649,7 @@ typedef struct {
 
 /** Offset 0x05A8 - Reserved
 **/
-  UINT8                       Reserved41;
+  UINT8                       Reserved40;
 
 /** Offset 0x05A9 - PCH LPC Enhance the port 8xh decoding
   Original LPC only decodes one byte of port 80h.
@@ -1727,7 +1669,7 @@ typedef struct {
 
 /** Offset 0x05CE - Reserved
 **/
-  UINT8                       Reserved42[46];
+  UINT8                       Reserved41[46];
 
 /** Offset 0x05FC - Enable PCIE RP Mask
   Enable/disable PCIE Root Ports. 0: disable, 1: enable. One bit for each port, bit0
@@ -1743,7 +1685,7 @@ typedef struct {
 
 /** Offset 0x0601 - Reserved
 **/
-  UINT8                       Reserved43[3];
+  UINT8                       Reserved42[3];
 
 /** Offset 0x0604 - Serial Io Uart Debug Mmio Base
   Select SerialIo Uart default MMIO resource in SEC/PEI phase when PcdLpssUartMode
@@ -1820,7 +1762,7 @@ typedef struct {
 
 /** Offset 0x061A - Reserved
 **/
-  UINT8                       Reserved44[2];
+  UINT8                       Reserved43[2];
 
 /** Offset 0x061C - HECI Timeouts
   0: Disable, 1: Enable (Default) timeout check for HECI
@@ -1873,7 +1815,7 @@ typedef struct {
 
 /** Offset 0x0624 - Reserved
 **/
-  UINT8                       Reserved45[2];
+  UINT8                       Reserved44[2];
 
 /** Offset 0x0626 - ISA Serial Base selection
   Select ISA Serial Base address. Default is 0x3F8.
@@ -1894,7 +1836,7 @@ typedef struct {
 
 /** Offset 0x062A - Reserved
 **/
-  UINT8                       Reserved46[26];
+  UINT8                       Reserved45[26];
 
 /** Offset 0x0644 - Enable SMBus
   Enable/disable SMBus controller.
@@ -1915,7 +1857,7 @@ typedef struct {
 
 /** Offset 0x0647 - Reserved
 **/
-  UINT8                       Reserved47;
+  UINT8                       Reserved46;
 
 /** Offset 0x0648 - SMBUS Base Address
   SMBUS Base Address (IO space).
@@ -1930,7 +1872,7 @@ typedef struct {
 
 /** Offset 0x064B - Reserved
 **/
-  UINT8                       Reserved48[13];
+  UINT8                       Reserved47[13];
 
 /** Offset 0x0658 - Smbus dynamic power gating
   Disable or Enable Smbus dynamic power gating.
@@ -1953,7 +1895,7 @@ typedef struct {
 
 /** Offset 0x065B - Reserved
 **/
-  UINT8                       Reserved49[18];
+  UINT8                       Reserved48[18];
 
 /** Offset 0x066D - Over clocking support
   Over clocking support; <b>0: Disable</b>; 1: Enable
@@ -1963,7 +1905,7 @@ typedef struct {
 
 /** Offset 0x066E - Reserved
 **/
-  UINT8                       Reserved50;
+  UINT8                       Reserved49;
 
 /** Offset 0x066F - Realtime Memory Timing
   0(Default): Disabled, 1: Enabled. When enabled, it will allow the system to perform
@@ -2026,7 +1968,7 @@ typedef struct {
 
 /** Offset 0x067B - Reserved
 **/
-  UINT8                       Reserved51[2];
+  UINT8                       Reserved50[2];
 
 /** Offset 0x067D - TjMax Offset
   TjMax offset.Specified value here is clipped by pCode (125 - TjMax Offset) to support
@@ -2036,7 +1978,7 @@ typedef struct {
 
 /** Offset 0x067E - Reserved
 **/
-  UINT8                      Reserved52[48];
+  UINT8                      Reserved51[48];
 
 /** Offset 0x06AE - Core VF Point Offset
   Array used to specifies the Core Voltage Offset applied to the each selected VF
@@ -2058,7 +2000,7 @@ typedef struct {
 
 /** Offset 0x06EA - Reserved
 **/
-  UINT8                       Reserved53[26];
+  UINT8                       Reserved52[26];
 
 /** Offset 0x0704 - Per Core Max Ratio override
   Enable or disable Per Core PState OC supported by writing OCMB 0x1D to program new
@@ -2069,7 +2011,7 @@ typedef struct {
 
 /** Offset 0x0705 - Reserved
 **/
-  UINT8                       Reserved54[25];
+  UINT8                       Reserved53[25];
 
 /** Offset 0x071E - Per Core Current Max Ratio
   Array for the Per Core Max Ratio
@@ -2078,7 +2020,7 @@ typedef struct {
 
 /** Offset 0x0726 - Reserved
 **/
-  UINT8                       Reserved55[8];
+  UINT8                       Reserved54[8];
 
 /** Offset 0x072E - Pvd Ratio Threshold for SOC/CPU die
   Array of Pvd Ratio Threshold for SOC/CPU die is the threshold value for input ratio
@@ -2091,7 +2033,7 @@ typedef struct {
 
 /** Offset 0x072F - Reserved
 **/
-  UINT8                       Reserved56[65];
+  UINT8                       Reserved55[65];
 
 /** Offset 0x0770 - CPU BCLK OC Frequency
   CPU BCLK OC Frequency in KHz units. 98000000Hz = 98MHz <b>0 - Auto</b>. Range is
@@ -2101,7 +2043,7 @@ typedef struct {
 
 /** Offset 0x0774 - Reserved
 **/
-  UINT8                      Reserved57[13];
+  UINT8                      Reserved56[13];
 
 /** Offset 0x0781 - Avx2 Voltage Guardband Scaling Factor
   AVX2 Voltage Guardband Scale factor applied to AVX2 workloads. Range is 0-200 in
@@ -2116,7 +2058,7 @@ typedef struct {
 
 /** Offset 0x0783 - Reserved
 **/
-  UINT8                       Reserved58[5];
+  UINT8                       Reserved57[5];
 
 /** Offset 0x0788 - Enable PCH ISH Controller
   0: Disable, 1: Enable (Default) ISH Controller
@@ -2126,7 +2068,7 @@ typedef struct {
 
 /** Offset 0x0789 - Reserved
 **/
-  UINT8                       Reserved59;
+  UINT8                       Reserved58;
 
 /** Offset 0x078A - BiosSize
   The size of the BIOS region of the IFWI. Used if FspmUpd->FspmConfig.BiosGuard !=
@@ -2161,7 +2103,7 @@ typedef struct {
 
 /** Offset 0x0790 - Reserved
 **/
-  UINT8                       Reserved60[3];
+  UINT8                       Reserved59[3];
 
 /** Offset 0x0793 - MKTME Key-Id Bits Override Enable
   Configure Trust Domain Extension (TDX) to isolate VMs from Virtual-Machine Manager
@@ -2172,7 +2114,7 @@ typedef struct {
 
 /** Offset 0x0794 - Reserved
 **/
-  UINT8                       Reserved61[4];
+  UINT8                       Reserved60[4];
 
 /** Offset 0x0798 - TME Exclude Base Address
   TME Exclude Base Address.
@@ -2186,7 +2128,7 @@ typedef struct {
 
 /** Offset 0x07A8 - Reserved
 **/
-  UINT8                      Reserved62[14];
+  UINT8                      Reserved61[14];
 
 /** Offset 0x07B6 - BIST on Reset
   Enable/Disable BIST (Built-In Self Test) on reset. <b>0: Disable</b>; 1: Enable.
@@ -2196,7 +2138,7 @@ typedef struct {
 
 /** Offset 0x07B7 - Reserved
 **/
-  UINT8                       Reserved63;
+  UINT8                       Reserved62;
 
 /** Offset 0x07B8 - Enable or Disable VMX
   Enable or Disable VMX, When enabled, a VMM can utilize the additional hardware capabilities
@@ -2266,7 +2208,7 @@ typedef struct {
 
 /** Offset 0x07C2 - Reserved
 **/
-  UINT8                       Reserved64[6];
+  UINT8                       Reserved63[6];
 
 /** Offset 0x07C8 - PrmrrSize
   Enable/Disable. 0: Disable, define default value of PrmrrSize , 1: enable
@@ -2294,7 +2236,7 @@ typedef struct {
 
 /** Offset 0x07D2 - Reserved
 **/
-  UINT8                       Reserved65[98];
+  UINT8                       Reserved64[98];
 
 /** Offset 0x0834 - SinitMemorySize
   Enable/Disable. 0: Disable, define default value of SinitMemorySize , 1: enable
@@ -2361,7 +2303,7 @@ typedef struct {
 
 /** Offset 0x086E - Reserved
 **/
-  UINT8                       Reserved66[2];
+  UINT8                       Reserved65[2];
 
 /** Offset 0x0870 - Platform Power Pmax
   PSYS PMax power, defined in 1/8 Watt increments. <b>0 - Auto</b> Specified in 1/8
@@ -2371,7 +2313,7 @@ typedef struct {
 
 /** Offset 0x0872 - Reserved
 **/
-  UINT8                      Reserved67[12];
+  UINT8                      Reserved66[12];
 
 /** Offset 0x087E - AcLoadline
   AC Loadline defined in 1/100 mOhms. A value of 100 = 1.00 mOhm, and 1255 = 12.55
@@ -2389,7 +2331,7 @@ typedef struct {
 
 /** Offset 0x0896 - Reserved
 **/
-  UINT8                      Reserved68[116];
+  UINT8                      Reserved67[116];
 
 /** Offset 0x090A - Thermal Design Current enable/disable
   Thermal Design Current enable/disable; <b>0: Disable</b>; 1: Enable. [0] for IA,
@@ -2399,7 +2341,7 @@ typedef struct {
 
 /** Offset 0x0910 - Reserved
 **/
-  UINT8                       Reserved69[6];
+  UINT8                       Reserved68[6];
 
 /** Offset 0x0916 - Disable Fast Slew Rate for Deep Package C States for VR domains
   This option needs to be configured to reduce acoustic noise during deeper C states.
@@ -2421,7 +2363,7 @@ typedef struct {
 
 /** Offset 0x0922 - Reserved
 **/
-  UINT8                       Reserved70[6];
+  UINT8                       Reserved69[6];
 
 /** Offset 0x0928 - Thermal Design Current time window
   Auto = 0 is default. Range is from 1ms to 448s. <b>0: Auto</b>. [0] for IA, [1]
@@ -2431,7 +2373,7 @@ typedef struct {
 
 /** Offset 0x0940 - Reserved
 **/
-  UINT8                       Reserved71[8];
+  UINT8                       Reserved70[8];
 
 /** Offset 0x0948 - DLVR RFI Enable
   Enable/Disable DLVR RFI frequency hopping. 0: Disable; <b>1: Enable</b>.
@@ -2441,7 +2383,7 @@ typedef struct {
 
 /** Offset 0x0949 - Reserved
 **/
-  UINT8                       Reserved72[13];
+  UINT8                       Reserved71[13];
 
 /** Offset 0x0956 - VR Fast Vmode ICC Limit support
   Voltage Regulator Fast Vmode ICC Limit. A value of 400 = 100A. A value of 0 corresponds
@@ -2466,7 +2408,7 @@ typedef struct {
 
 /** Offset 0x096E - Reserved
 **/
-  UINT8                       Reserved73[28];
+  UINT8                       Reserved72[28];
 
 /** Offset 0x098A - PCH Port80 Route
   Control where the Port 80h cycles are sent, 0: LPC; 1: PCI.
@@ -2483,7 +2425,7 @@ typedef struct {
 
 /** Offset 0x098C - Reserved
 **/
-  UINT8                       Reserved74[4];
+  UINT8                       Reserved73[4];
 
 /** Offset 0x0990 - PMR Size
   Size of PMR memory buffer. 0x400000 for normal boot and 0x200000 for S3 boot
@@ -2509,7 +2451,7 @@ typedef struct {
 
 /** Offset 0x0997 - Reserved
 **/
-  UINT8                       Reserved75;
+  UINT8                       Reserved74;
 
 /** Offset 0x0998 - Base addresses for VT-d function MMIO access
   Base addresses for VT-d MMIO access per VT-d engine
@@ -2518,7 +2460,7 @@ typedef struct {
 
 /** Offset 0x09BC - Reserved
 **/
-  UINT8                       Reserved76[20];
+  UINT8                       Reserved75[20];
 
 /** Offset 0x09D0 - MMIO Size
   Size of MMIO space reserved for devices. 0(Default)=Auto, non-Zero=size in MB
@@ -2533,7 +2475,7 @@ typedef struct {
 
 /** Offset 0x09D4 - Reserved
 **/
-  UINT8                      Reserved77[36];
+  UINT8                      Reserved76[36];
 
 /** Offset 0x09F8 - Enable above 4GB MMIO resource support
   Enable/disable above 4GB MMIO resource support
@@ -2549,7 +2491,7 @@ typedef struct {
 
 /** Offset 0x09FA - Reserved
 **/
-  UINT8                       Reserved78[10];
+  UINT8                       Reserved77[10];
 
 /** Offset 0x0A04 - Enable/Disable CrashLog Device
   Enable or Disable CrashLog/Telemetry Device  0- Disable, <b>1- Enable</b>
@@ -2559,7 +2501,7 @@ typedef struct {
 
 /** Offset 0x0A08 - Reserved
 **/
-  UINT8                      Reserved79[20];
+  UINT8                      Reserved78[20];
 
 /** Offset 0x0A1C - Platform Debug Option
   Enabled Trace active: TraceHub is enabled and trace is active, blocks s0ix.\n
@@ -2576,7 +2518,7 @@ typedef struct {
 
 /** Offset 0x0A1D - Reserved
 **/
-  UINT8                       Reserved80[14];
+  UINT8                       Reserved79[14];
 
 /** Offset 0x0A2B - Program GPIOs for LFP on DDI port-A device
   0=Disabled,1(Default)=eDP, 2=MIPI DSI
@@ -2586,7 +2528,7 @@ typedef struct {
 
 /** Offset 0x0A2C - Reserved
 **/
-  UINT8                      Reserved81[2];
+  UINT8                      Reserved80[2];
 
 /** Offset 0x0A2E - Program GPIOs for LFP on DDI port-B device
   0(Default)=Disabled,1=eDP, 2=MIPI DSI
@@ -2680,7 +2622,7 @@ typedef struct {
 
 /** Offset 0x0A3D - Reserved
 **/
-  UINT8                       Reserved82[3];
+  UINT8                       Reserved81[3];
 
 /** Offset 0x0A40 - Temporary MMIO address for GMADR
   The reference code will use this as Temporary MMIO address space to access GMADR
@@ -2699,7 +2641,7 @@ typedef struct {
 
 /** Offset 0x0A50 - Reserved
 **/
-  UINT8                      Reserved83[2];
+  UINT8                      Reserved82[2];
 
 /** Offset 0x0A52 - Enable/Disable Memory Bandwidth Compression
   0=Disable, 1(Default)=Enable
@@ -2729,7 +2671,7 @@ typedef struct {
 
 /** Offset 0x0A56 - Reserved
 **/
-  UINT8                       Reserved84[2];
+  UINT8                       Reserved83[2];
 
 /** Offset 0x0A58 - Intel Graphics VBT (Video BIOS Table) Size
   Size of Internal Graphics VBT Image
@@ -2738,7 +2680,7 @@ typedef struct {
 
 /** Offset 0x0A5C - Reserved
 **/
-  UINT8                       Reserved85[4];
+  UINT8                       Reserved84[4];
 
 /** Offset 0x0A60 - Graphics Configuration Ptr
   Points to VBT
@@ -2766,7 +2708,7 @@ typedef struct {
 
 /** Offset 0x0A72 - Reserved
 **/
-  UINT8                      Reserved86[16];
+  UINT8                      Reserved85[16];
 
 /** Offset 0x0A82 - TCSS USB HOST (xHCI) Enable
   Set TCSS XHCI. 0:Disabled  1:Enabled - Must be enabled if xDCI is enabled below
@@ -2776,7 +2718,7 @@ typedef struct {
 
 /** Offset 0x0A83 - Reserved
 **/
-  UINT8                       Reserved87[4];
+  UINT8                       Reserved86[4];
 
 /** Offset 0x0A87 - TCSS Type C Port 0
   Set TCSS Type C Port 0 Type, Options are 0=DISABLE, 1=DP_ONLY, 2=NO_TBT, 3=NO_PCIE,
@@ -2808,7 +2750,7 @@ typedef struct {
 
 /** Offset 0x0A8B - Reserved
 **/
-  UINT8                       Reserved88;
+  UINT8                       Reserved87;
 
 /** Offset 0x0A8C - TypeC port GPIO setting
   GPIO Pin number for Type C Aux orientation setting, use the GpioPad that is defined
@@ -2876,7 +2818,7 @@ typedef struct {
 
 /** Offset 0x0AC9 - Reserved
 **/
-  UINT8                       Reserved89;
+  UINT8                       Reserved88;
 
 /** Offset 0x0ACA - DLL Weak Lock Support
   Enables/Disable DLL Weak Lock Support
@@ -2886,7 +2828,7 @@ typedef struct {
 
 /** Offset 0x0ACB - Reserved
 **/
-  UINT8                       Reserved90;
+  UINT8                       Reserved89;
 
 /** Offset 0x0ACC - Rx DQS Delay Comp Support
   Enables/Disable Rx DQS Delay Comp Support
@@ -2896,7 +2838,17 @@ typedef struct {
 
 /** Offset 0x0ACD - Reserved
 **/
-  UINT8                       Reserved91[7];
+  UINT8                       Reserved90[2];
+
+/** Offset 0x0ACF - Mrc Failure On Unsupported Dimm
+  Enables/Disable Mrc Failure On Unsupported Dimm
+  $EN_DIS
+**/
+  UINT8                       MrcFailureOnUnsupportedDimm;
+
+/** Offset 0x0AD0 - Reserved
+**/
+  UINT8                      Reserved91[4];
 
 /** Offset 0x0AD4 - DynamicMemoryBoost
   Enable/Disable Dynamic Memory Boost Feature. Only valid if SpdProfileSelected is
@@ -3041,22 +2993,7 @@ typedef struct {
 
 /** Offset 0x0AF8 - Reserved
 **/
-  UINT8                       Reserved94[13];
-
-/** Offset 0x0B05 - PPR ForceRepair
-  When Eanble, PPR will force repair some rows many times (90)
-  $EN_DIS
-**/
-  UINT8                       PprForceRepair;
-
-/** Offset 0x0B06 - PPR Repair Bank
-  PPR repair Bank: User chooses to force repair specifc address
-**/
-  UINT8                       PprRepairBank;
-
-/** Offset 0x0B07 - Reserved
-**/
-  UINT8                       Reserved95[49];
+  UINT8                       Reserved94[112];
 } FSP_M_CONFIG;
 
 /** Fsp M UPD Configuration
@@ -3075,11 +3012,11 @@ typedef struct {
 **/
   FSP_M_CONFIG                FspmConfig;
 
-/** Offset 0x0B38
+/** Offset 0x0B68
 **/
   UINT8                       FspmRsvd3834[6];
 
-/** Offset 0x0B3E
+/** Offset 0x0B6E
 **/
   UINT16                      UpdTerminator;
 } FSPM_UPD;
diff --git a/src/vendorcode/intel/fsp/fsp2_0/pantherlake/FspsUpd.h b/src/vendorcode/intel/fsp/fsp2_0/pantherlake/FspsUpd.h
index 3dd46ff5c2..8e6541ba1c 100644
--- a/src/vendorcode/intel/fsp/fsp2_0/pantherlake/FspsUpd.h
+++ b/src/vendorcode/intel/fsp/fsp2_0/pantherlake/FspsUpd.h
@@ -2026,189 +2026,189 @@ typedef struct {
 
 /** Offset 0x1401 - Reserved
 **/
-  UINT8                       Reserved50[11];
+  UINT8                       Reserved50[67];
 
-/** Offset 0x140C - Address of PCH_DEVICE_INTERRUPT_CONFIG table.
+/** Offset 0x1444 - Address of PCH_DEVICE_INTERRUPT_CONFIG table.
   The address of the table of PCH_DEVICE_INTERRUPT_CONFIG.
 **/
   UINT32                      DevIntConfigPtr;
 
-/** Offset 0x1410 - Number of DevIntConfig Entry
+/** Offset 0x1448 - Number of DevIntConfig Entry
   Number of Device Interrupt Configuration Entry. If this is not zero, the DevIntConfigPtr
   must not be NULL.
 **/
   UINT8                       NumOfDevIntConfig;
 
-/** Offset 0x1411 - Select GPIO IRQ Route
+/** Offset 0x1449 - Select GPIO IRQ Route
   GPIO IRQ Select. The valid value is 14 or 15.
 **/
   UINT8                       GpioIrqRoute;
 
-/** Offset 0x1412 - Select SciIrqSelect
+/** Offset 0x144A - Select SciIrqSelect
   SCI IRQ Select. The valid value is 9, 10, 11, and 20, 21, 22, 23 for APIC only.
 **/
   UINT8                       SciIrqSelect;
 
-/** Offset 0x1413 - Select TcoIrqSelect
+/** Offset 0x144B - Select TcoIrqSelect
   TCO IRQ Select. The valid value is 9, 10, 11, 20, 21, 22, 23.
 **/
   UINT8                       TcoIrqSelect;
 
-/** Offset 0x1414 - Enable/Disable Tco IRQ
+/** Offset 0x144C - Enable/Disable Tco IRQ
   Enable/disable TCO IRQ
   $EN_DIS
 **/
   UINT8                       TcoIrqEnable;
 
-/** Offset 0x1415 - Reserved
+/** Offset 0x144D - Reserved
 **/
   UINT8                       Reserved51[5];
 
-/** Offset 0x141A - Mask to enable the usage of external V1p05 VR rail in specific S0ix or Sx states
+/** Offset 0x1452 - Mask to enable the usage of external V1p05 VR rail in specific S0ix or Sx states
   Enable External V1P05 Rail in: BIT0:S0i1/S0i2, BIT1:S0i3, BIT2:S3, BIT3:S4, BIT5:S5
 **/
   UINT8                       PchFivrExtV1p05RailEnabledStates;
 
-/** Offset 0x141B - Mask to enable the platform configuration of external V1p05 VR rail
+/** Offset 0x1453 - Mask to enable the platform configuration of external V1p05 VR rail
   External V1P05 Rail Supported Configuration
 **/
   UINT8                       PchFivrExtV1p05RailSupportedVoltageStates;
 
-/** Offset 0x141C - External V1P05 Voltage Value that will be used in S0i2/S0i3 states
+/** Offset 0x1454 - External V1P05 Voltage Value that will be used in S0i2/S0i3 states
   Value is given in 2.5mV increments (0=0mV, 1=2.5mV, 2=5mV...)
 **/
   UINT16                      PchFivrExtV1p05RailVoltage;
 
-/** Offset 0x141E - External V1P05 Icc Max Value
+/** Offset 0x1456 - External V1P05 Icc Max Value
   Granularity of this setting is 1mA and maximal possible value is 200mA
 **/
   UINT8                       PchFivrExtV1p05RailIccMax;
 
-/** Offset 0x141F - Mask to enable the usage of external Vnn VR rail in specific S0ix or Sx states
+/** Offset 0x1457 - Mask to enable the usage of external Vnn VR rail in specific S0ix or Sx states
   Enable External Vnn Rail in: BIT0:S0i1/S0i2, BIT1:S0i3, BIT2:S3, BIT3:S4, BIT5:S5
 **/
   UINT8                       PchFivrExtVnnRailEnabledStates;
 
-/** Offset 0x1420 - Mask to enable the platform configuration of external Vnn VR rail
+/** Offset 0x1458 - Mask to enable the platform configuration of external Vnn VR rail
   External Vnn Rail Supported Configuration
 **/
   UINT8                       PchFivrExtVnnRailSupportedVoltageStates;
 
-/** Offset 0x1421 - Reserved
+/** Offset 0x1459 - Reserved
 **/
   UINT8                       Reserved52;
 
-/** Offset 0x1422 - External Vnn Voltage Value that will be used in S0ix/Sx states
+/** Offset 0x145A - External Vnn Voltage Value that will be used in S0ix/Sx states
   Value is given in 2.5mV increments (0=0mV, 1=2.5mV, 2=5mV...), Default is set to 420
 **/
   UINT16                      PchFivrExtVnnRailVoltage;
 
-/** Offset 0x1424 - External Vnn Icc Max Value that will be used in S0ix/Sx states
+/** Offset 0x145C - External Vnn Icc Max Value that will be used in S0ix/Sx states
   Granularity of this setting is 1mA and maximal possible value is 200mA
 **/
   UINT8                       PchFivrExtVnnRailIccMax;
 
-/** Offset 0x1425 - Mask to enable the usage of external Vnn VR rail in Sx states
+/** Offset 0x145D - Mask to enable the usage of external Vnn VR rail in Sx states
   Use only if Ext Vnn Rail config is different in Sx. Enable External Vnn Rail in
   Sx: BIT0-1:Reserved, BIT2:S3, BIT3:S4, BIT5:S5
 **/
   UINT8                       PchFivrExtVnnRailSxEnabledStates;
 
-/** Offset 0x1426 - External Vnn Voltage Value that will be used in Sx states
+/** Offset 0x145E - External Vnn Voltage Value that will be used in Sx states
   Use only if Ext Vnn Rail config is different in Sx. Value is given in 2.5mV increments
   (0=0mV, 1=2.5mV, 2=5mV...)
 **/
   UINT16                      PchFivrExtVnnRailSxVoltage;
 
-/** Offset 0x1428 - External Vnn Icc Max Value that will be used in Sx states
+/** Offset 0x1460 - External Vnn Icc Max Value that will be used in Sx states
   Use only if Ext Vnn Rail config is different in Sx. Granularity of this setting
   is 1mA and maximal possible value is 200mA
 **/
   UINT8                       PchFivrExtVnnRailSxIccMax;
 
-/** Offset 0x1429 - Transition time in microseconds from Low Current Mode Voltage to High Current Mode Voltage
+/** Offset 0x1461 - Transition time in microseconds from Low Current Mode Voltage to High Current Mode Voltage
   This field has 1us resolution. When value is 0 PCH will not transition VCCIN_AUX
   to low current mode voltage.
 **/
   UINT8                       PchFivrVccinAuxLowToHighCurModeVolTranTime;
 
-/** Offset 0x142A - Transition time in microseconds from Retention Mode Voltage to High Current Mode Voltage
+/** Offset 0x1462 - Transition time in microseconds from Retention Mode Voltage to High Current Mode Voltage
   This field has 1us resolution. When value is 0 PCH will not transition VCCIN_AUX
   to retention mode voltage.
 **/
   UINT8                       PchFivrVccinAuxRetToHighCurModeVolTranTime;
 
-/** Offset 0x142B - Transition time in microseconds from Retention Mode Voltage to Low Current Mode Voltage
+/** Offset 0x1463 - Transition time in microseconds from Retention Mode Voltage to Low Current Mode Voltage
   This field has 1us resolution. When value is 0 PCH will not transition VCCIN_AUX
   to retention mode voltage.
 **/
   UINT8                       PchFivrVccinAuxRetToLowCurModeVolTranTime;
 
-/** Offset 0x142C - Transition time in microseconds from Off (0V) to High Current Mode Voltage
+/** Offset 0x1464 - Transition time in microseconds from Off (0V) to High Current Mode Voltage
   This field has 1us resolution. When value is 0 Transition to 0V is disabled.
 **/
   UINT16                      PchFivrVccinAuxOffToHighCurModeVolTranTime;
 
-/** Offset 0x142E - FIVR Dynamic Power Management
+/** Offset 0x1466 - FIVR Dynamic Power Management
   Enable/Disable FIVR Dynamic Power Management.
   $EN_DIS
 **/
   UINT8                       PchFivrDynPm;
 
-/** Offset 0x142F - Reserved
+/** Offset 0x1467 - Reserved
 **/
   UINT8                       Reserved53;
 
-/** Offset 0x1430 - External V1P05 Icc Max Value
+/** Offset 0x1468 - External V1P05 Icc Max Value
   Granularity of this setting is 1mA and maximal possible value is 500mA
 **/
   UINT16                      PchFivrExtV1p05RailIccMaximum;
 
-/** Offset 0x1432 - External Vnn Icc Max Value that will be used in S0ix/Sx states
+/** Offset 0x146A - External Vnn Icc Max Value that will be used in S0ix/Sx states
   Granularity of this setting is 1mA and maximal possible value is 500mA
 **/
   UINT16                      PchFivrExtVnnRailIccMaximum;
 
-/** Offset 0x1434 - External Vnn Icc Max Value that will be used in Sx states
+/** Offset 0x146C - External Vnn Icc Max Value that will be used in Sx states
   Use only if Ext Vnn Rail config is different in Sx. Granularity of this setting
   is 1mA and maximal possible value is 500mA
 **/
   UINT16                      PchFivrExtVnnRailSxIccMaximum;
 
-/** Offset 0x1436 - External V1P05 Control Ramp Timer value
+/** Offset 0x146E - External V1P05 Control Ramp Timer value
   Hold off time to be used when changing the v1p05_ctrl for external bypass value in us
 **/
   UINT8                       PchFivrExtV1p05RailCtrlRampTmr;
 
-/** Offset 0x1437 - External VNN Control Ramp Timer value
+/** Offset 0x146F - External VNN Control Ramp Timer value
   Hold off time to be used when changing the vnn_ctrl for external bypass value in us
 **/
   UINT8                       PchFivrExtVnnRailCtrlRampTmr;
 
-/** Offset 0x1438 - PCH Compatibility Revision ID
+/** Offset 0x1470 - PCH Compatibility Revision ID
   This member describes whether or not the CRID feature of PCH should be enabled.
   $EN_DIS
 **/
   UINT8                       PchCrid;
 
-/** Offset 0x1439 - PCH Legacy IO Low Latency Enable
+/** Offset 0x1471 - PCH Legacy IO Low Latency Enable
   Set to enable low latency of legacy IO. <b>0: Disable</b>, 1: Enable
   $EN_DIS
 **/
   UINT8                       PchLegacyIoLowLatency;
 
-/** Offset 0x143A - Reserved
+/** Offset 0x1472 - Reserved
 **/
   UINT8                       Reserved54;
 
-/** Offset 0x143B - PCH Unlock SideBand access
+/** Offset 0x1473 - PCH Unlock SideBand access
   The SideBand PortID mask for certain end point (e.g. PSFx) will be locked before
   3rd party code execution. 0: Lock SideBand access; 1: Unlock SideBand access.
   $EN_DIS
 **/
   UINT8                       PchSbAccessUnlock;
 
-/** Offset 0x143C - Enable 8254 Static Clock Gating
+/** Offset 0x1474 - Enable 8254 Static Clock Gating
   Set 8254CGE=1 is required for SLP_S0 support. However, set 8254CGE=1 in POST time
   might fail to boot legacy OS using 8254 timer. Make sure it is disabled to support
   legacy OS using 8254 timer. Also enable this while S0ix is enabled.
@@ -2216,7 +2216,7 @@ typedef struct {
 **/
   UINT8                       Enable8254ClockGating;
 
-/** Offset 0x143D - Enable 8254 Static Clock Gating On S3
+/** Offset 0x1475 - Enable 8254 Static Clock Gating On S3
   This is only applicable when Enable8254ClockGating is disabled. FSP will do the
   8254 CGE programming on S3 resume when Enable8254ClockGatingOnS3 is enabled. This
   avoids the SMI requirement for the programming.
@@ -2224,172 +2224,172 @@ typedef struct {
 **/
   UINT8                       Enable8254ClockGatingOnS3;
 
-/** Offset 0x143E - Enable PCH Io Apic Entry 24-119
+/** Offset 0x1476 - Enable PCH Io Apic Entry 24-119
   0: Disable; 1: Enable.
   $EN_DIS
 **/
   UINT8                       PchIoApicEntry24_119;
 
-/** Offset 0x143F - PCH Io Apic ID
+/** Offset 0x1477 - PCH Io Apic ID
   This member determines IOAPIC ID. Default is 0x02.
 **/
   UINT8                       PchIoApicId;
 
-/** Offset 0x1440 - CNVi Configuration
+/** Offset 0x1478 - CNVi Configuration
   This option allows for automatic detection of Connectivity Solution. [Auto Detection]
   assumes that CNVi will be enabled when available, [Disable] allows for disabling CNVi.
   0:Disable, 1:Auto
 **/
   UINT8                       CnviMode;
 
-/** Offset 0x1441 - CNVi Wi-Fi Core
+/** Offset 0x1479 - CNVi Wi-Fi Core
   Enable/Disable CNVi Wi-Fi Core, Default is ENABLE. 0: DISABLE, 1: ENABLE
   $EN_DIS
 **/
   UINT8                       CnviWifiCore;
 
-/** Offset 0x1442 - CNVi BT Core
+/** Offset 0x147A - CNVi BT Core
   Enable/Disable CNVi BT Core, Default is ENABLE. 0: DISABLE, 1: ENABLE
   $EN_DIS
 **/
   UINT8                       CnviBtCore;
 
-/** Offset 0x1443 - CNVi BT Interface
+/** Offset 0x147B - CNVi BT Interface
   This option configures BT device interface to either USB/PCI
   1:USB, 2:PCI
 **/
   UINT8                       CnviBtInterface;
 
-/** Offset 0x1444 - CNVi BT Audio Offload
+/** Offset 0x147C - CNVi BT Audio Offload
   Enable/Disable BT Audio Offload, Default is ENABLE. 0: DISABLE, 1: ENABLE
   $EN_DIS
 **/
   UINT8                       CnviBtAudioOffload;
 
-/** Offset 0x1445 - Reserved
+/** Offset 0x147D - Reserved
 **/
   UINT8                       Reserved55[3];
 
-/** Offset 0x1448 - CNVi RF_RESET pin muxing
+/** Offset 0x1480 - CNVi RF_RESET pin muxing
   Select CNVi RF_RESET# pin depending on board routing. LP/P/M: GPP_A8 = 0x2942E408(default)
   or GPP_F4 = 0x194CE404. H/S: 0. Refer to GPIO_*_MUXING_CNVI_RF_RESET_* in GpioPins*.h.
 **/
   UINT32                      CnviRfResetPinMux;
 
-/** Offset 0x144C - CNVi CLKREQ pin muxing
+/** Offset 0x1484 - CNVi CLKREQ pin muxing
   Select CNVi CLKREQ pin depending on board routing. LP/P/M: GPP_A9 = 0x3942E609(default)
   or GPP_F5 = 0x394CE605. H/S: 0. Refer to GPIO_*_MUXING_CNVI_CRF_XTAL_CLKREQ_* in
   GpioPins*.h.
 **/
   UINT32                      CnviClkreqPinMux;
 
-/** Offset 0x1450 - Reserved
+/** Offset 0x1488 - Reserved
 **/
   UINT8                       Reserved56;
 
-/** Offset 0x1451 - Enable Device 4
+/** Offset 0x1489 - Enable Device 4
   Enable/disable Device 4
   $EN_DIS
 **/
   UINT8                       Device4Enable;
 
-/** Offset 0x1452 - Skip PAM regsiter lock
+/** Offset 0x148A - Skip PAM regsiter lock
   Enable: PAM register will not be locked by RC, platform code should lock it, Disable(Default):
   PAM registers will be locked by RC
   $EN_DIS
 **/
   UINT8                       SkipPamLock;
 
-/** Offset 0x1453 - Reserved
+/** Offset 0x148B - Reserved
 **/
   UINT8                       Reserved57;
 
-/** Offset 0x1454 - PCH HDA Verb Table Entry Number
+/** Offset 0x148C - PCH HDA Verb Table Entry Number
   Number of Entries in Verb Table.
 **/
   UINT8                       PchHdaVerbTableEntryNum;
 
-/** Offset 0x1455 - Reserved
+/** Offset 0x148D - Reserved
 **/
   UINT8                       Reserved58[3];
 
-/** Offset 0x1458 - PCH HDA Verb Table Pointer
+/** Offset 0x1490 - PCH HDA Verb Table Pointer
   Pointer to Array of pointers to Verb Table.
 **/
   UINT64                      PchHdaVerbTablePtr;
 
-/** Offset 0x1460 - PCH HDA Codec Sx Wake Capability
+/** Offset 0x1498 - PCH HDA Codec Sx Wake Capability
   Capability to detect wake initiated by a codec in Sx
 **/
   UINT8                       PchHdaCodecSxWakeCapability;
 
-/** Offset 0x1461 - Enable Pme
+/** Offset 0x1499 - Enable Pme
   Enable Azalia wake-on-ring.
   $EN_DIS
 **/
   UINT8                       PchHdaPme;
 
-/** Offset 0x1462 - HD Audio Link Frequency
+/** Offset 0x149A - HD Audio Link Frequency
   HDA Link Freq (PCH_HDAUDIO_LINK_FREQUENCY enum): 0: 6MHz, 1: 12MHz, 2: 24MHz.
   0: 6MHz, 1: 12MHz, 2: 24MHz
 **/
   UINT8                       PchHdaLinkFrequency;
 
-/** Offset 0x1463 - Reserved
+/** Offset 0x149B - Reserved
 **/
   UINT8                       Reserved59[2];
 
-/** Offset 0x1465 - HD Audio Microphone Privacy applied for SoundWire Link number 0 in HW Mode
+/** Offset 0x149D - HD Audio Microphone Privacy applied for SoundWire Link number 0 in HW Mode
   HD Audio Microphone Privacy applied for SoundWire Link number 0 in HW Mode: 0: Disable, 1: Enable
   $EN_DIS
 **/
   UINT8                       PchHdaMicPrivacyHwModeSoundWire0;
 
-/** Offset 0x1466 - HD Audio Microphone Privacy applied for SoundWire Link number 1 in HW Mode
+/** Offset 0x149E - HD Audio Microphone Privacy applied for SoundWire Link number 1 in HW Mode
   HD Audio Microphone Privacy applied for SoundWire Link number 1 in HW Mode: 0: Disable, 1: Enable
   $EN_DIS
 **/
   UINT8                       PchHdaMicPrivacyHwModeSoundWire1;
 
-/** Offset 0x1467 - HD Audio Microphone Privacy applied for SoundWire Link number 2 in HW Mode
+/** Offset 0x149F - HD Audio Microphone Privacy applied for SoundWire Link number 2 in HW Mode
   HD Audio Microphone Privacy applied for SoundWire Link number 2 in HW Mode: 0: Disable, 1: Enable
   $EN_DIS
 **/
   UINT8                       PchHdaMicPrivacyHwModeSoundWire2;
 
-/** Offset 0x1468 - HD Audio Microphone Privacy applied for SoundWire Link number 3 in HW Mode
+/** Offset 0x14A0 - HD Audio Microphone Privacy applied for SoundWire Link number 3 in HW Mode
   HD Audio Microphone Privacy applied for SoundWire Link number 3 in HW Mode: 0: Disable, 1: Enable
   $EN_DIS
 **/
   UINT8                       PchHdaMicPrivacyHwModeSoundWire3;
 
-/** Offset 0x1469 - HD Audio Microphone Privacy applied for SoundWire Link number 4 in HW Mode
+/** Offset 0x14A1 - HD Audio Microphone Privacy applied for SoundWire Link number 4 in HW Mode
   HD Audio Microphone Privacy applied for SoundWire Link number 4 in HW Mode: 0: Disable, 1: Enable
   $EN_DIS
 **/
   UINT8                       PchHdaMicPrivacyHwModeSoundWire4;
 
-/** Offset 0x146A - HD Audio Microphone Privacy applied for Dmic in HW Mode
+/** Offset 0x14A2 - HD Audio Microphone Privacy applied for Dmic in HW Mode
   HD Audio Microphone Privacy applied for Dmic in HW Mode: 0: Disable, 1: Enable
   $EN_DIS
 **/
   UINT8                       PchHdaMicPrivacyHwModeDmic;
 
-/** Offset 0x146B - Reserved
+/** Offset 0x14A3 - Reserved
 **/
   UINT8                       Reserved60[13];
 
-/** Offset 0x1478 - Pointer to ChipsetInit Binary
+/** Offset 0x14B0 - Pointer to ChipsetInit Binary
   ChipsetInit Binary Pointer.
 **/
   UINT64                      ChipsetInitBinPtr;
 
-/** Offset 0x1480 - Length of ChipsetInit Binary
+/** Offset 0x14B8 - Length of ChipsetInit Binary
   ChipsetInit Binary Length.
 **/
   UINT32                      ChipsetInitBinLen;
 
-/** Offset 0x1484 - Reserved
+/** Offset 0x14BC - Reserved
 **/
   UINT8                       Reserved61[36];
 } FSP_S_CONFIG;
@@ -2410,11 +2410,11 @@ typedef struct {
 **/
   FSP_S_CONFIG                FspsConfig;
 
-/** Offset 0x14A8
+/** Offset 0x14E0
 **/
   UINT8                       FspsUpdRsvd36[6];
 
-/** Offset 0x14AE
+/** Offset 0x14E6
 **/
   UINT16                      UpdTerminator;
 } FSPS_UPD;
diff --git a/src/vendorcode/intel/fsp/fsp2_0/pantherlake/MemInfoHob.h b/src/vendorcode/intel/fsp/fsp2_0/pantherlake/MemInfoHob.h
index e8683927be..f36dc915e3 100644
--- a/src/vendorcode/intel/fsp/fsp2_0/pantherlake/MemInfoHob.h
+++ b/src/vendorcode/intel/fsp/fsp2_0/pantherlake/MemInfoHob.h
@@ -78,7 +78,7 @@ typedef struct _EFI_HOB_GUID_TYPE {
 // Matches MAX_SPD_SAVE define in MRC
 //
 #ifndef MAX_SPD_SAVE
-#define MAX_SPD_SAVE 29
+#define MAX_SPD_SAVE 39
 #endif
 
 //
@@ -203,28 +203,40 @@ typedef struct {
   UINT16 tRDPRE;     ///< Read CAS to Precharge cmd delay
 } MRC_IP_TIMING;
 
+typedef union {
+  struct {
+    UINT16 ContinuationCount                   :  7; ///< Bits 6:0
+    UINT16 ContinuationParity                  :  1; ///< Bits 7:7
+    UINT16 LastNonZeroByte                     :  8; ///< Bits 15:8
+  } Bits;
+  UINT16 Data;
+  UINT8  Data8[2];
+} HOB_MANUFACTURER_ID_CODE;
+
 ///
 /// Memory SMBIOS & OC Memory Data Hob
 ///
 typedef struct {
-  UINT8            Status;                  ///< See MrcDimmStatus for the definition of this field.
-  UINT8            DimmId;
-  UINT32           DimmCapacity;            ///< DIMM size in MBytes.
-  UINT16           MfgId;                   ///< Dram module manufacturer ID
-  UINT16           CkdMfgID;                ///< Clock Driver (CKD) Manufacturer ID
-  UINT8            CkdDeviceRev;            ///< Clock Driver (CKD) device revision
-  UINT16           DramMfgID;               ///< Manufacturer ID code for DRAM chip on the module
-  UINT8            ModulePartNum[20];       ///< Module part number for DDR3 is 18 bytes however for DDR4 20 bytes as per JEDEC Spec, so reserving 20 bytes
-  UINT8            RankInDimm;              ///< The number of ranks in this DIMM.
-  UINT8            SpdDramDeviceType;       ///< Save SPD DramDeviceType information needed for SMBIOS structure creation.
-  UINT8            SpdModuleType;           ///< Save SPD ModuleType information needed for SMBIOS structure creation.
-  UINT8            SpdModuleMemoryBusWidth; ///< Save SPD ModuleMemoryBusWidth information needed for SMBIOS structure creation.
-  UINT8            SpdSave[MAX_SPD_SAVE];   ///< Save SPD Manufacturing information needed for SMBIOS structure creation.
-  UINT16           Speed;                   ///< The maximum capable speed of the device, in MHz
-  UINT8            MdSocket;                ///< MdSocket: 0 = Memory Down, 1 = Socketed. Needed for SMBIOS structure creation.
-  UINT8            Banks;                   ///< Number of banks the DIMM contains.
-  UINT8            BankGroups;              ///< Number of bank groups the DIMM contains.
-  UINT8            DeviceDensity;           ///< Device Density in Gb
+  UINT8                     Status;                  ///< See MrcDimmStatus for the definition of this field.
+  UINT8                     DimmId;
+  UINT32                    DimmCapacity;            ///< DIMM size in MBytes.
+  HOB_MANUFACTURER_ID_CODE  MfgId;                   ///< Dram module manufacturer ID
+  HOB_MANUFACTURER_ID_CODE  CkdMfgID;                ///< Clock Driver (CKD) Manufacturer ID
+  UINT8                     CkdDeviceRev;            ///< Clock Driver (CKD) device revision
+  HOB_MANUFACTURER_ID_CODE  DramMfgID;               ///< Manufacturer ID code for DRAM chip on the module
+  UINT8                     ModulePartNum[30];       ///< Module part number in ASCII
+  UINT8                     RankInDimm;              ///< The number of ranks in this DIMM.
+  UINT8                     SpdDramDeviceType;       ///< Save SPD DramDeviceType information needed for SMBIOS structure creation.
+  UINT8                     SpdModuleType;           ///< Save SPD ModuleType information needed for SMBIOS structure creation.
+  UINT8                     SpdSave[MAX_SPD_SAVE];   ///< Save SPD Manufacturing information needed for SMBIOS structure creation.
+  UINT16                    Speed;                   ///< The maximum capable speed of the device, in MHz
+  UINT8                     MdSocket;                ///< MdSocket: 0 = Memory Down, 1 = Socketed. Needed for SMBIOS structure creation.
+  UINT8                     Banks;                   ///< Number of banks the DIMM contains.
+  UINT8                     BankGroups;              ///< Number of bank groups the DIMM contains.
+  UINT8                     DeviceDensity;           ///< Device Density in Gb
+  UINT32                    SerialNumber;            ///< DIMM Serial Number
+  UINT8                     TotalWidth;              ///< Total Data width in bits
+  UINT8                     DataWidth;               ///< Primary bus width in bits
 } DIMM_INFO;
 
 typedef struct {
@@ -291,16 +303,22 @@ typedef struct _PPR_RESULT_COLUMNS_HOB {
   - Initial version. (from MTL)
   <b>Revision 2:</b>
   - Added MopPackages, MopDensity, MopRanks, MopVendor fields
+  <b>Revision 3:</b>
+  - Added MaxRankCapacity
+  - Removed DataWidth
+  - DIMM_INFO: increased ModulePartNum from 20 to 30 chars
+  - DIMM_INFO: Added SerialNumber, TotalWidth and DataWidth
+  - DIMM_INFO: Removed SpdModuleMemoryBusWidth
+  - MFG ID fields: use HOB_MANUFACTURER_ID_CODE instead of UINT16 for easier parsing
 
 **/
 typedef struct {
   UINT8             Revision;
-  UINT16            DataWidth;              ///< Data width, in bits, of this memory device
   /** As defined in SMBIOS 3.0 spec
     Section 7.18.2 and Table 75
   **/
-  UINT8             MemoryType;             ///< DDR type: DDR3, DDR4, or LPDDR3
-  UINT16            MaximumMemoryClockSpeed;///< The maximum capable speed of the device, in megahertz (MHz)
+  UINT8             MemoryType;                 ///< DDR type: DDR5 or LPDDR5, uses SMBIOS MEMORY_DEVICE_TYPE encoding
+  UINT16            MaximumMemoryClockSpeed;    ///< The maximum capable speed of the device, in megahertz (MHz)
   UINT16            ConfiguredMemoryClockSpeed; ///< The configured clock speed to the memory device, in megahertz (MHz)
   /** As defined in SMBIOS 3.0 spec
     Section 7.17.3 and Table 72
@@ -339,6 +357,9 @@ typedef struct {
   UINT16            PprRepairsSuccessful;              ///< PPR: Counts of repair successes
   PPR_RESULT_COLUMNS_HOB PprErrorInfo;                 ///< PPR: Error location
   UINT8             PprAvailableResources[MAX_NODE][MAX_CH][_MAX_RANK_IN_CHANNEL][_MAX_SDRAM_IN_DIMM]; ///< PPR available resources per device
+  BOOLEAN           MixedEccDimms;                     ///< TRUE if both ECC and nonECC Dimms were detected in the system
+  UINT8             MaxRankCapacity;                   ///< Maximum possible rank capacity in [GB]
+  UINT16            PprFailingChannelBitMask;          ///< PPR failing channel mask
 } MEMORY_INFO_DATA_HOB;
 
 /**

From 8de02842d5965e761da0b71fc626efb4354d409d Mon Sep 17 00:00:00 2001
From: Subrata Banik <subratabanik@google.com>
Date: Fri, 16 May 2025 01:52:58 +0530
Subject: [PATCH 1068/3886] soc/intel/common/block/cpu: Execute post_cpus_init
 at BS_DEV_ENABLE

Move `post_cpus_init` to execute at the entry of the `BS_DEV_ENABLE`
boot state. This function is responsible for synchronizing
and finalizing MTRR (Memory Type Range Registers) settings across all threads.

This change ensures that MTRR configuration occurs at the correct
point in the boot sequence:
-   After main DRAM resources are determined and finalized (typically
    by the `BS_DEV_RESERVE_RESOURCES` state). MTRRs define
    attributes for these physical memory ranges.

Previously, `post_cpus_init` was hooked at `BS_WRITE_TABLES` (on exit)
or `BS_OS_RESUME` (on entry). Relocating to `BS_DEV_ENABLE` (on entry)
provides a more robust and correctly sequenced execution point for this
essential multi-processor (MP) MTRR setup.

BUG=b:413638298
TEST=Successfully built and booted google/fatcat. Verified that
     MTRR programming, which depends on DRAM resource determination
     (finalized by BS_DEV_RESERVE_RESOURCES), now correctly
     executes at BS_DEV_ENABLE, prior to full device initialization.

Change-Id: I1d2b3f11e4ac268c5b35bf9a8062a77a48a0601a
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87703
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
---
 src/soc/intel/common/block/cpu/mp_init.c | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/src/soc/intel/common/block/cpu/mp_init.c b/src/soc/intel/common/block/cpu/mp_init.c
index a8ee838710..16b77b0352 100644
--- a/src/soc/intel/common/block/cpu/mp_init.c
+++ b/src/soc/intel/common/block/cpu/mp_init.c
@@ -233,5 +233,4 @@ static void post_cpus_init(void *unused)
 
 /* Do CPU MP Init before FSP Silicon Init */
 BOOT_STATE_INIT_ENTRY(BS_DEV_INIT_CHIPS, BS_ON_ENTRY, coreboot_init_cpus, NULL);
-BOOT_STATE_INIT_ENTRY(BS_WRITE_TABLES, BS_ON_EXIT, post_cpus_init, NULL);
-BOOT_STATE_INIT_ENTRY(BS_OS_RESUME, BS_ON_ENTRY, post_cpus_init, NULL);
+BOOT_STATE_INIT_ENTRY(BS_DEV_ENABLE, BS_ON_ENTRY, post_cpus_init, NULL);

From 756d02f779a729822cc5f939283d41b1daf85547 Mon Sep 17 00:00:00 2001
From: Subrata Banik <subratabanik@google.com>
Date: Mon, 19 May 2025 14:54:58 +0000
Subject: [PATCH 1069/3886] mb/google/fatcat: Remove extraneous space in Felino
 Kconfig name

This commit removes an unnecessary space in the Kconfig name
for BOARD_GOOGLE_FELINO.

Change-Id: I49044a49fcef914b2e11d3c2eeefe6b6b082d8c1
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87749
Reviewed-by: Pranava Y N <pranavayn@google.com>
Reviewed-by: Jayvik Desai <jayvik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/google/fatcat/Kconfig.name | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/mainboard/google/fatcat/Kconfig.name b/src/mainboard/google/fatcat/Kconfig.name
index 786c0e7f4b..48844c6424 100644
--- a/src/mainboard/google/fatcat/Kconfig.name
+++ b/src/mainboard/google/fatcat/Kconfig.name
@@ -15,7 +15,7 @@ config BOARD_GOOGLE_FATCATNUVO
 	bool "-> Fatcatnuvo"
 
 config BOARD_GOOGLE_FELINO
-	bool "->  Felino"
+	bool "-> Felino"
 
 config BOARD_GOOGLE_FRANCKA
 	bool "-> Francka"

From a98511fd2301e5df3320608bec046aab7785c95d Mon Sep 17 00:00:00 2001
From: Kapil Porwal <kapilporwal@google.com>
Date: Tue, 20 May 2025 11:34:09 +0530
Subject: [PATCH 1070/3886] mb/google/bluey: Only select
 EC_GOOGLE_CHROMEEC_SWITCHES with VBOOT

EC_GOOGLE_CHROMEEC_SWITCHES depends on VBOOT, so only select it, if
VBOOT is selected.

BUG=b:417843479
TEST=Run `make menuconfig` for google/quenbi.
TEST=Able to build google/quenbi.

Change-Id: I449fe09fbc512e07635da819791834e8f4f674f8
Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87755
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Jayvik Desai <jayvik@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Pranava Y N <pranavayn@google.com>
---
 src/mainboard/google/bluey/Kconfig | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/mainboard/google/bluey/Kconfig b/src/mainboard/google/bluey/Kconfig
index 09f7cae5dd..392a5fae71 100644
--- a/src/mainboard/google/bluey/Kconfig
+++ b/src/mainboard/google/bluey/Kconfig
@@ -66,7 +66,7 @@ config MAINBOARD_HAS_CHROME_EC
 	select EC_GOOGLE_CHROMEEC
 	select EC_GOOGLE_CHROMEEC_RTC
 	select EC_GOOGLE_CHROMEEC_SPI
-	select EC_GOOGLE_CHROMEEC_SWITCHES
+	select EC_GOOGLE_CHROMEEC_SWITCHES if VBOOT
 	select RTC
 	help
 	  Enable this option if your mainboard is equipped with Chrome EC.

From e2baa9c7ed9e8471398d9a7b5695fbaadeb78378 Mon Sep 17 00:00:00 2001
From: Kapil Porwal <kapilporwal@google.com>
Date: Thu, 15 May 2025 08:21:33 +0530
Subject: [PATCH 1071/3886] mb/google/bluey: Create Quenbi variant

BUG=b:417843479
TEST=Build AP firmware image.

Change-Id: Ibc727593f3b849904dd4f7d791f764d5ac8b2572
Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87697
Reviewed-by: Jayvik Desai <jayvik@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Pranava Y N <pranavayn@google.com>
---
 src/mainboard/google/bluey/Kconfig      | 10 ++++++++++
 src/mainboard/google/bluey/Kconfig.name |  3 +++
 2 files changed, 13 insertions(+)

diff --git a/src/mainboard/google/bluey/Kconfig b/src/mainboard/google/bluey/Kconfig
index 392a5fae71..ed02ddf405 100644
--- a/src/mainboard/google/bluey/Kconfig
+++ b/src/mainboard/google/bluey/Kconfig
@@ -19,6 +19,12 @@ config BOARD_GOOGLE_BLUEY
 	select MAINBOARD_HAS_FINGERPRINT_VIA_USB
 	select MISSING_BOARD_RESET
 
+config BOARD_GOOGLE_QUENBI
+	select BOARD_GOOGLE_BASEBOARD_BLUEY
+	select MAINBOARD_HAS_CHROME_EC
+	select MAINBOARD_HAS_FINGERPRINT_VIA_SPI
+	select MAINBOARD_HAS_GOOGLE_TPM
+
 if BOARD_GOOGLE_BLUEY_COMMON
 
 config MAINBOARD_DIR
@@ -85,10 +91,12 @@ config VBOOT
 
 config MAINBOARD_PART_NUMBER
 	default "Bluey" if BOARD_GOOGLE_BLUEY
+	default "Quenbi" if BOARD_GOOGLE_QUENBI
 
 config DRIVER_TPM_I2C_BUS
 	depends on I2C_TPM
 	hex
+	default 0xa if BOARD_GOOGLE_QUENBI
 	default 0x10
 
 config DRIVER_TPM_I2C_ADDR
@@ -97,11 +105,13 @@ config DRIVER_TPM_I2C_ADDR
 config EC_GOOGLE_CHROMEEC_SPI_BUS
 	depends on EC_GOOGLE_CHROMEEC
 	hex
+	default 0xd if BOARD_GOOGLE_QUENBI
 	default 0xb
 
 config MAINBOARD_GPIO_PIN_FOR_GSC_AP_INTERRUPT
 	depends on TPM_GOOGLE_TI50
 	int
+	default 91 if BOARD_GOOGLE_QUENBI
 	default 34
 	help
 	  This option specifies the GPIO pin number on the mainboard that is
diff --git a/src/mainboard/google/bluey/Kconfig.name b/src/mainboard/google/bluey/Kconfig.name
index 19cb4b1e17..7196403480 100644
--- a/src/mainboard/google/bluey/Kconfig.name
+++ b/src/mainboard/google/bluey/Kconfig.name
@@ -4,3 +4,6 @@ comment "Bluey"
 
 config BOARD_GOOGLE_BLUEY
 	bool "->  Bluey"
+
+config BOARD_GOOGLE_QUENBI
+	bool "->  Quenbi"

From ccd4d1d1db26b95e622c665fc51a2c5d63f54877 Mon Sep 17 00:00:00 2001
From: John Su <john_su@compal.corp-partner.google.com>
Date: Fri, 16 May 2025 13:23:30 +0800
Subject: [PATCH 1072/3886] mb/var/uldrenite: Make two pins NC to reduce S0ix
 power consumption

Currently, it was found that the GPP_D2 and GPP_D18 pins affect power
consumption during S0ix. After discussion with the hardware team,
since the motherboard is shared across different platforms and these
two pins are unused on the Chrome platform, they will be set to NC.
Measurements have shown that this change effectively improves power
consumption.

Due to some pins changes for next phase, the modifications are listed
below for reference.

Follow the GPIO table updated on 05/19.

GPP_D2         : GPO -> NC
GPP_D14:
  Current phase: GPO -> NC
  Next phase   : FUNC1 (UART0_ISH)
GPP_D18:
  Current phase: FUNC2 (UART1_ISH)
  Next phase   : GPO -> NC

BUG=b:411554553
TEST=improve 375mW-->143mW

Change-Id: I3c788ed4e2ff3e5d49008c03a895d13549d5c79b
Signed-off-by: John Su <john_su@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87709
Reviewed-by: Ben Kao <ben.kao@intel.com>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/google/brya/variants/uldrenite/gpio.c    | 8 ++++----
 src/mainboard/google/brya/variants/uldrenite/variant.c | 6 +++---
 2 files changed, 7 insertions(+), 7 deletions(-)

diff --git a/src/mainboard/google/brya/variants/uldrenite/gpio.c b/src/mainboard/google/brya/variants/uldrenite/gpio.c
index 667a369604..d21b0ebde3 100644
--- a/src/mainboard/google/brya/variants/uldrenite/gpio.c
+++ b/src/mainboard/google/brya/variants/uldrenite/gpio.c
@@ -121,8 +121,8 @@ static const struct pad_config gpio_table[] = {
 	PAD_CFG_GPO(GPP_D0, 1, DEEP),
 	/* D1  : ISH_GP1 ==> SOC_GSEN2_INT# */
 	PAD_CFG_NF(GPP_D1, NONE, DEEP, NF1),
-	/* D2  : ISH_GP2 ==> TOUCH_SCREEN_DET# */
-	PAD_CFG_GPO_LOCK(GPP_D2, 1, LOCK_CONFIG),
+	/* D2  : ISH_GP2 ==> NC */
+	PAD_NC_LOCK(GPP_D2, NONE, LOCK_CONFIG),
 	/* D3  : NC ==> PHY_SHUTTER_DET */
 	PAD_CFG_GPO_LOCK(GPP_D3, 1, LOCK_CONFIG),
 	/* D4  : NC ==> WCAM_FW_PROTECT */
@@ -153,8 +153,8 @@ static const struct pad_config gpio_table[] = {
 	PAD_CFG_GPI_APIC(GPP_D16, NONE, PLTRST, LEVEL, INVERT),
 	/* D17 : NC */
 	PAD_NC(GPP_D17, NONE),
-	/* D18 : LCD_CBL_DET# */
-	PAD_CFG_GPO(GPP_D18, 1, DEEP),
+	/* D18 : LCD_CBL_DET# ==> NC */
+	PAD_NC(GPP_D18, NONE),
 	/* D19 : I2S_MCLK1_OUT ==> NC */
 	PAD_NC(GPP_D19, NONE),
 
diff --git a/src/mainboard/google/brya/variants/uldrenite/variant.c b/src/mainboard/google/brya/variants/uldrenite/variant.c
index 75809e233f..a7927eb0d3 100644
--- a/src/mainboard/google/brya/variants/uldrenite/variant.c
+++ b/src/mainboard/google/brya/variants/uldrenite/variant.c
@@ -61,11 +61,11 @@ static const struct pad_config ish_uart0_disable_pads[] = {
 static const struct pad_config switch_ish_uart1_pads[] = {
 	/* D13  : UART0_ISH_RXD ==> NC  */
 	PAD_NC(GPP_D13, NONE),
-	/* D14  : UART0_ISH_TXD ==> LCD_CBL_DET# */
-	PAD_CFG_GPO(GPP_D14, 1, DEEP),
+	/* D14  : UART0_ISH_TXD ==> NC */
+	PAD_NC(GPP_D14, NONE),
 	/* D17 : NC ==> UART1_ISH_RDX */
 	PAD_CFG_NF(GPP_D17, NONE, DEEP, NF2),
-	/* D18 : LCD_CBL_DET# ==> UART1_ISH_TDX */
+	/* D18 : NC ==> UART1_ISH_TDX */
 	PAD_CFG_NF(GPP_D18, NONE, DEEP, NF2),
 };
 

From a89406790a4adbc63bf8d819348351d149c21a44 Mon Sep 17 00:00:00 2001
From: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com>
Date: Thu, 15 May 2025 09:47:32 +0900
Subject: [PATCH 1073/3886] mb/google/nissa/var/meliks: Set
 vccin_aux_imon_iccmax to 25A

crrev/c/5828162 introduced vccin_aux_imon_iccmax parameter for each variant to override the VccInAuxImonIccImax FSP parameter to follow its VCCANA power rail design.

Since meliks adopts external VR design for VCCANA power rail, set it to 25A to follow the guidance in RDC#646929 Power Map.

BUG=b:409205469
TEST=Built and boot
     Verified maximum 5% of 3D mark score improvement on N250 SKU

Change-Id: I58786493098c787d402c85ce7167319285af7488
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87704
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/google/brya/variants/meliks/overridetree.cb | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/src/mainboard/google/brya/variants/meliks/overridetree.cb b/src/mainboard/google/brya/variants/meliks/overridetree.cb
index c98d31e6d6..203edb4686 100644
--- a/src/mainboard/google/brya/variants/meliks/overridetree.cb
+++ b/src/mainboard/google/brya/variants/meliks/overridetree.cb
@@ -77,6 +77,9 @@ chip soc/intel/alderlake
 		[PchSerialIoIndexI2C5] = PchSerialIoPci,
 	}"
 
+	# 25A of Vcc In Aux Imon Iccmax value for VCCANA MBVR design
+	register "vccin_aux_imon_iccmax" = "PD_TIER_PREMIUM" # 25A
+
 	# Enable the Cnvi BT Audio Offload
 	register "cnvi_bt_audio_offload" = "1"
 

From 2bec5a9d9a6fdadd72d28d68e25d14cf91b0e49c Mon Sep 17 00:00:00 2001
From: Zexin Wang <ot_zexin.wang@mediatek.corp-partner.google.com>
Date: Tue, 17 Dec 2024 19:32:58 +0800
Subject: [PATCH 1074/3886] soc/mediatek/mt8189: Check eFuse ECC in WDT init

When the number of eFuse reads exceeds a certain limit (with a maximum
of 20 million), a bit flip from 1 to 0 may happen. When that happens,
the bit flip will be automatically corrected by the eFuse hardware via
ECC (Error Correction Code), and the EFUSE_ECC_ERR register bit will be
set for the software to decide how to handle that.

Therefore, this patch adds a check for the EFUSE_ECC_ERR register bit.
If it's set due to a bit flip instead of a real error, we simply clear
it to avoid triggering a WDT reset.

BUG=b:379008996
BRANCH=none
TEST=build passed and check the WDT status debug log. This log is added
in local for test only.
[INFO ]  mtk_wdt_clear_efuse_ecc: wdt_sta = 0x0

Signed-off-by: Zexin Wang <ot_zexin.wang@mediatek.corp-partner.google.com>
Change-Id: Idd2763688c7ab6992a7c185e9e52b60bda88c94c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87744
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
---
 src/soc/mediatek/common/include/soc/wdt_common.h |  1 +
 src/soc/mediatek/common/wdt.c                    |  2 ++
 src/soc/mediatek/mt8189/Makefile.mk              |  1 +
 src/soc/mediatek/mt8189/efuse.c                  | 12 ++++++++++++
 src/soc/mediatek/mt8189/include/soc/addressmap.h |  1 +
 src/soc/mediatek/mt8189/include/soc/efuse.h      |  5 +++++
 src/soc/mediatek/mt8189/wdt.c                    | 12 +++++++++++-
 7 files changed, 33 insertions(+), 1 deletion(-)
 create mode 100644 src/soc/mediatek/mt8189/efuse.c

diff --git a/src/soc/mediatek/common/include/soc/wdt_common.h b/src/soc/mediatek/common/include/soc/wdt_common.h
index 6d6d2ba758..02574263ae 100644
--- a/src/soc/mediatek/common/include/soc/wdt_common.h
+++ b/src/soc/mediatek/common/include/soc/wdt_common.h
@@ -57,5 +57,6 @@ static struct mtk_wdt_regs *const mtk_wdt = (void *)RGU_BASE;
 int mtk_wdt_init(void);
 void mtk_wdt_clr_status(void);
 void mtk_wdt_set_req(void);
+void mtk_wdt_clear_efuse_ecc(void);
 
 #endif /* SOC_MEDIATEK_WDT_COMMON_H */
diff --git a/src/soc/mediatek/common/wdt.c b/src/soc/mediatek/common/wdt.c
index 663fc2fd30..e4038aae02 100644
--- a/src/soc/mediatek/common/wdt.c
+++ b/src/soc/mediatek/common/wdt.c
@@ -10,6 +10,7 @@
 
 __weak void mtk_wdt_clr_status(void) { /* do nothing */ }
 __weak void mtk_wdt_set_req(void) { /* do nothing */ }
+__weak void mtk_wdt_clear_efuse_ecc(void) { /* do nothing */ }
 
 static inline void mtk_wdt_swreset(void)
 {
@@ -36,6 +37,7 @@ int mtk_wdt_init(void)
 {
 	uint32_t wdt_sta;
 
+	mtk_wdt_clear_efuse_ecc();
 	mtk_wdt_set_req();
 
 	/* Writing mode register will clear status register */
diff --git a/src/soc/mediatek/mt8189/Makefile.mk b/src/soc/mediatek/mt8189/Makefile.mk
index c870dec5c7..237cbaab0e 100644
--- a/src/soc/mediatek/mt8189/Makefile.mk
+++ b/src/soc/mediatek/mt8189/Makefile.mk
@@ -10,6 +10,7 @@ all-y += ../common/timer_prepare.c timer.c
 all-y += ../common/uart.c
 
 bootblock-y += bootblock.c
+bootblock-y += efuse.c
 bootblock-y += ../common/mmu_operations.c
 bootblock-y += ../common/mtcmos.c mtcmos.c
 bootblock-y += ../common/pll.c pll.c
diff --git a/src/soc/mediatek/mt8189/efuse.c b/src/soc/mediatek/mt8189/efuse.c
new file mode 100644
index 0000000000..726b5474bf
--- /dev/null
+++ b/src/soc/mediatek/mt8189/efuse.c
@@ -0,0 +1,12 @@
+/* SPDX-License-Identifier: GPL-2.0-only OR MIT */
+
+#include <device/mmio.h>
+#include <soc/addressmap.h>
+#include <soc/efuse.h>
+
+#define MTK_EFUSE_ECC_ERROR_BIT BIT(7)
+
+bool mtk_efuse_ecc_has_error(void)
+{
+	return !!(read32(&mtk_efuse->ecc_status_reg) & MTK_EFUSE_ECC_ERROR_BIT);
+}
diff --git a/src/soc/mediatek/mt8189/include/soc/addressmap.h b/src/soc/mediatek/mt8189/include/soc/addressmap.h
index 0f257cc543..3f6fe3e598 100644
--- a/src/soc/mediatek/mt8189/include/soc/addressmap.h
+++ b/src/soc/mediatek/mt8189/include/soc/addressmap.h
@@ -91,6 +91,7 @@ enum {
 	IMP_IIC_WRAP_S_BASE		= IO_PHYS + 0x01D74000,
 	IOCFG_LT0_BASE			= IO_PHYS + 0x01E20000,
 	IOCFG_LT1_BASE			= IO_PHYS + 0x01E30000,
+	EFUSEC_BASE			= IO_PHYS + 0x01F10000,
 	IOCFG_RT_BASE			= IO_PHYS + 0x01F20000,
 	IMP_IIC_WRAP_EN_BASE		= IO_PHYS + 0x01F32000,
 	MFGCFG_BASE			= IO_PHYS + 0x03FBF000,
diff --git a/src/soc/mediatek/mt8189/include/soc/efuse.h b/src/soc/mediatek/mt8189/include/soc/efuse.h
index 031dd5ef78..2d872d46b5 100644
--- a/src/soc/mediatek/mt8189/include/soc/efuse.h
+++ b/src/soc/mediatek/mt8189/include/soc/efuse.h
@@ -11,10 +11,15 @@ struct efuse_regs {
 	u32 cpu_id_reg;
 	u32 reserved2[15];
 	u32 cpu_seg_id_reg;
+	u32 reserved3[14908];
+	u32 ecc_status_reg;
 };
 check_member(efuse_regs, cpu_id_reg, 0x7A0);
 check_member(efuse_regs, cpu_seg_id_reg, 0x7E0);
+check_member(efuse_regs, ecc_status_reg, 0xF0D4);
 
 static struct efuse_regs *const mtk_efuse = (void *)EFUSEC_BASE;
 
+bool mtk_efuse_ecc_has_error(void);
+
 #endif /*__SOC_MEDIATEK_MT8189_INCLUDE_SOC_EFUSE_H__*/
diff --git a/src/soc/mediatek/mt8189/wdt.c b/src/soc/mediatek/mt8189/wdt.c
index ca6518bc2e..ba991d2e96 100644
--- a/src/soc/mediatek/mt8189/wdt.c
+++ b/src/soc/mediatek/mt8189/wdt.c
@@ -7,11 +7,21 @@
 
 #include <device/mmio.h>
 #include <soc/addressmap.h>
+#include <soc/efuse.h>
 #include <soc/wdt.h>
 
-#define MTK_WDT_CLR_STATUS 0x230001FF
+#define MTK_WDT_CLR_STATUS		0x230001FF
+#define MTK_WDT_CLR_EFUSE_ECC_ERR	0x2300000A
+#define MTK_WDT_STA_EFUSE_ECC_ERR	BIT(23)
 
 void mtk_wdt_clr_status(void)
 {
 	write32(&mtk_wdt->wdt_mode, MTK_WDT_CLR_STATUS);
 }
+
+void mtk_wdt_clear_efuse_ecc(void)
+{
+	if ((read32(&mtk_wdt->wdt_status) & MTK_WDT_STA_EFUSE_ECC_ERR) &&
+	    !mtk_efuse_ecc_has_error())
+		write32(&mtk_wdt->wdt_mode, MTK_WDT_CLR_EFUSE_ECC_ERR);
+}

From 583bf972c52cc369195c680e44936a85cefa9131 Mon Sep 17 00:00:00 2001
From: Avi Uday <aviuday@google.com>
Date: Tue, 20 May 2025 10:37:46 +0530
Subject: [PATCH 1075/3886] mb/google/ocelot: Remove NPK device

This commit removes the `device ref npk on end` from the
`overridetree.cb` files for ocelot, similar to -
commit 85c65b0c20ad (mb/google/fatcat: Remove NPK device from fatcat and francka variants)

This effectively disables the NPK device for these configurations
(because `npk` is default set to disable).

Change-Id: Iee1509f44f6543c23f9633ccd8d35d4a7e37b89e
Signed-off-by: Avi Uday <aviuday@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87753
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Pranava Y N <pranavayn@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/google/ocelot/variants/ocelot/overridetree.cb | 1 -
 1 file changed, 1 deletion(-)

diff --git a/src/mainboard/google/ocelot/variants/ocelot/overridetree.cb b/src/mainboard/google/ocelot/variants/ocelot/overridetree.cb
index f0c1039c01..809e73054f 100644
--- a/src/mainboard/google/ocelot/variants/ocelot/overridetree.cb
+++ b/src/mainboard/google/ocelot/variants/ocelot/overridetree.cb
@@ -617,7 +617,6 @@ chip soc/intel/pantherlake
 		end
 
 		device ref smbus on end
-		device ref npk on end
 		device ref hda off end
 	end
 end

From 4d30d06637981c722a19687843e375ca75eb02a7 Mon Sep 17 00:00:00 2001
From: Avi Uday <aviuday@google.com>
Date: Tue, 20 May 2025 10:41:52 +0530
Subject: [PATCH 1076/3886] mainboard/google/ocelot: Configure middle logo
 vertical alignment

This commit overrides the `logo_valignment` setting in the
`common_soc_config` for the Ocelot board variant, similar to
https://review.coreboot.org/c/coreboot/+/87453.

The vertical alignment for the firmware splash screen logo is now set to
`FW_SPLASH_VALIGNMENT_MIDDLE`, which places the top edge of the logo at
the vertical midpoint of the screen.

Change-Id: I29f08d31d325304f7532ed37f9cf3d5ef0bb88ff
Signed-off-by: Avi Uday <aviuday@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87754
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Pranava Y N <pranavayn@google.com>
---
 src/mainboard/google/ocelot/variants/ocelot/overridetree.cb | 1 +
 1 file changed, 1 insertion(+)

diff --git a/src/mainboard/google/ocelot/variants/ocelot/overridetree.cb b/src/mainboard/google/ocelot/variants/ocelot/overridetree.cb
index 809e73054f..c4341c2a27 100644
--- a/src/mainboard/google/ocelot/variants/ocelot/overridetree.cb
+++ b/src/mainboard/google/ocelot/variants/ocelot/overridetree.cb
@@ -115,6 +115,7 @@ chip soc/intel/pantherlake
 	#| I2C5              | Touchpad                  |
 	#+-------------------+---------------------------+
 	register "common_soc_config" = "{
+		.logo_valignment = FW_SPLASH_VALIGNMENT_MIDDLE,
 		.chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT,
 		.i2c[1] = {
 			.speed = I2C_SPEED_FAST,

From 3155b2f64cd6eb401ffc57439f62d54bc7ceca58 Mon Sep 17 00:00:00 2001
From: Nicholas Chin <nic.c3.14@gmail.com>
Date: Sun, 11 May 2025 15:25:10 -0600
Subject: [PATCH 1077/3886] mb/dell/haswell_latitude: Correct
 BOARD_ROMSIZE_KB_* for E7240

The E7240 actually has a 8MiB + 4MiB flash configuration, not 8MiB.

Change-Id: I14f0c8f6f0c0dfebf41294812b1f4e131eaa18d0
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87635
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
---
 src/mainboard/dell/haswell_latitude/Kconfig | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/mainboard/dell/haswell_latitude/Kconfig b/src/mainboard/dell/haswell_latitude/Kconfig
index c01735d35d..8ad18fb0b5 100644
--- a/src/mainboard/dell/haswell_latitude/Kconfig
+++ b/src/mainboard/dell/haswell_latitude/Kconfig
@@ -13,7 +13,7 @@ config BOARD_DELL_HASWELL_LATITUDE_COMMON
 
 config BOARD_DELL_LATITUDE_E7240
 	select BOARD_DELL_HASWELL_LATITUDE_COMMON
-	select BOARD_ROMSIZE_KB_8192
+	select BOARD_ROMSIZE_KB_12288
 	select INTEL_LYNXPOINT_LP
 	select MAINBOARD_USES_IFD_GBE_REGION
 

From bd66b8cdd260f345f815a7e944e762d8a3707892 Mon Sep 17 00:00:00 2001
From: Pranava Y N <pranavayn@google.com>
Date: Wed, 21 May 2025 15:28:14 +0530
Subject: [PATCH 1078/3886] mb/google/nissa/var/rull: Enable VBOOT_EC_SYNC_ESOL
 for rull device

Enable `VBOOT_EC_SYNC_ESOL` config option to display early sign-of-life
(eSOL) during EC firmware updates for rull devices.

BUG=b:386920751
TEST=Verify that eSOL is displayed during EC firmware update.

Change-Id: Ibf6f88d7cf63b48c39300f4db981fe1a8efcefe9
Signed-off-by: Pranava Y N <pranavayn@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87773
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Jayvik Desai <jayvik@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/google/brya/Kconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/src/mainboard/google/brya/Kconfig b/src/mainboard/google/brya/Kconfig
index 4e9a0e6589..1f3867277d 100644
--- a/src/mainboard/google/brya/Kconfig
+++ b/src/mainboard/google/brya/Kconfig
@@ -1147,6 +1147,7 @@ config VARIANT_DIR
 
 config VBOOT
 	select VBOOT_EARLY_EC_SYNC if !(BOARD_GOOGLE_BASEBOARD_NISSA || BOARD_GOOGLE_BASEBOARD_TRULO) || BOARD_GOOGLE_RULL
+	select VBOOT_EC_SYNC_ESOL if BOARD_GOOGLE_RULL
 	select VBOOT_LID_SWITCH
 
 config UART_FOR_CONSOLE

From 9d878fc6c0a7316c8f33f1aac8507b900bc89f2c Mon Sep 17 00:00:00 2001
From: Felix Zimmer <felix.zimmer@student.kit.edu>
Date: Thu, 15 May 2025 16:25:49 +0200
Subject: [PATCH 1079/3886] soc/intel/xeon_sp: Add support for Emerald Rapids
 (5th Gen Xeon-SP) CPUs

TEST=build/boot ASRock SPC741D8-2L2T/BCM with Intel Xeon Silver 4514Y to
edk2 and Linux 6.12

Change-Id: Iefe3228dcf3626aa9a72d16a288751af47d526f6
Signed-off-by: Felix Zimmer <felix.zimmer@student.kit.edu>
Co-authored-by: Yussuf Khalil <yussuf.khalil@kit.edu>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87746
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
---
 src/include/cpu/intel/cpu_ids.h         | 1 +
 src/soc/intel/xeon_sp/report_platform.c | 1 +
 src/soc/intel/xeon_sp/spr/cpu.c         | 1 +
 3 files changed, 3 insertions(+)

diff --git a/src/include/cpu/intel/cpu_ids.h b/src/include/cpu/intel/cpu_ids.h
index e14cb797ab..59900077d9 100644
--- a/src/include/cpu/intel/cpu_ids.h
+++ b/src/include/cpu/intel/cpu_ids.h
@@ -57,6 +57,7 @@
 #define CPUID_SAPPHIRERAPIDS_SP_E3	0x806f6
 #define CPUID_SAPPHIRERAPIDS_SP_E4	0x806f7
 #define CPUID_SAPPHIRERAPIDS_SP_Ex	0x806f8
+#define CPUID_EMERALDRAPIDS		0xC06F2
 #define CPUID_GRANITERAPIDS		0xA06D0
 #define CPUID_SIERRAFOREST		0xA06F0
 #define CPUID_ELKHARTLAKE_A0		0x90660
diff --git a/src/soc/intel/xeon_sp/report_platform.c b/src/soc/intel/xeon_sp/report_platform.c
index 874ff45d81..8389532dd7 100644
--- a/src/soc/intel/xeon_sp/report_platform.c
+++ b/src/soc/intel/xeon_sp/report_platform.c
@@ -26,6 +26,7 @@ static struct {
 	{ CPUID_SAPPHIRERAPIDS_SP_E3, "Sapphire Rapids E3" },
 	{ CPUID_SAPPHIRERAPIDS_SP_E4, "Sapphire Rapids E4" },
 	{ CPUID_SAPPHIRERAPIDS_SP_Ex, "Sapphire Rapids Ex" },
+	{ CPUID_EMERALDRAPIDS, "Emerald Rapids" },
 };
 
 static void report_cpu_info(void)
diff --git a/src/soc/intel/xeon_sp/spr/cpu.c b/src/soc/intel/xeon_sp/spr/cpu.c
index 383bf5f512..ec369b2c5c 100644
--- a/src/soc/intel/xeon_sp/spr/cpu.c
+++ b/src/soc/intel/xeon_sp/spr/cpu.c
@@ -178,6 +178,7 @@ static const struct cpu_device_id cpu_table[] = {
 	{X86_VENDOR_INTEL, CPUID_SAPPHIRERAPIDS_SP_E3, CPUID_EXACT_MATCH_MASK},
 	{X86_VENDOR_INTEL, CPUID_SAPPHIRERAPIDS_SP_E4, CPUID_EXACT_MATCH_MASK},
 	{X86_VENDOR_INTEL, CPUID_SAPPHIRERAPIDS_SP_Ex, CPUID_EXACT_MATCH_MASK},
+	{X86_VENDOR_INTEL, CPUID_EMERALDRAPIDS, CPUID_EXACT_MATCH_MASK},
 	CPU_TABLE_END
 };
 

From cbbf380fa4699882dfc28556ca571f36dcfae775 Mon Sep 17 00:00:00 2001
From: Patrick Rudolph <patrick.rudolph@9elements.com>
Date: Sat, 22 Feb 2025 15:09:00 +0100
Subject: [PATCH 1080/3886] soc/amd/common/block/lpc: Use ROM3 window if
 possible

On x86_64 use the ROM3 window to access the SPI flash. Use the
same mechanism as on Intel, where the lower 16Mbyte are mapped
using ROM2 window and the upper pages are mapped using the ROM3
window. By default the ROM3 window resides in high MMIO and thus
needs 1024GiB of the address space to be identity mapped in the
page tables.

This allows legacy 32-bit code to work on mappings in the lower
16MiB of the flash chip.

Introduces new messages in coreboot log:
[INFO ]  ROM2 Decode Window: SPI flash base=0x0, Host base=0xff000000, Size=0x1000000
[INFO ]  ROM3 Decode Window: SPI flash base=0x1000000, Host base=0xfd01000000, Size=0x3000000

TEST: Disabled ROM2 mapping and booted from ROM3 mapping in x86_64
      on amd/birman+.

Change-Id: I8976273cfb31765d7f893b3fc137f117c63b6553
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86584
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Naresh <naresh.solanki.2011@gmail.com>
---
 src/soc/amd/common/block/spi/Kconfig          |  18 ++
 src/soc/amd/common/block/spi/Makefile.mk      |   3 +
 src/soc/amd/common/block/spi/mmap_boot_rom3.c | 163 ++++++++++++++++++
 src/soc/amd/glinda/Kconfig                    |   3 +
 4 files changed, 187 insertions(+)
 create mode 100644 src/soc/amd/common/block/spi/mmap_boot_rom3.c

diff --git a/src/soc/amd/common/block/spi/Kconfig b/src/soc/amd/common/block/spi/Kconfig
index 88b118276c..085c02a2f6 100644
--- a/src/soc/amd/common/block/spi/Kconfig
+++ b/src/soc/amd/common/block/spi/Kconfig
@@ -16,11 +16,29 @@ config SOC_AMD_COMMON_BLOCK_SPI_4DW_BURST
 	help
 	  Select this option to keep the 4 DWORD burst support enabled.
 
+config SOC_AMD_COMMON_BLOCK_SPI_MMAP_USE_ROM3
+	bool
+	default y if ROM_SIZE > 0x01000000
+	depends on !SOC_AMD_PICASSO && !SOC_AMD_STONEYRIDGE
+	depends on !SOC_AMD_COMMON_BLOCK_LPC_SPI_DMA
+	depends on USE_X86_64_SUPPORT
+	# Enable X86_CUSTOM_BOOTMEDIA because the fast SPI controller
+	# driver provides a custom boot media device when multiple decode
+	# windows are used for the BIOS region.
+	select X86_CUSTOM_BOOTMEDIA
+	help
+	  AMD specific SPI flash access. The lower 16MiB of the SPI flash are
+	  memory mapped on the ROM2 window and the upper SPI flash is mapped using
+	  the ROM3 window in high MMIO. The ROM3 window maps up to 64MiB of the
+	  SPI flash. The default address of ROM3 is below 1024GiB address boundary
+	  and thus can only be used in x86_64 mode.
+
 config SOC_AMD_COMMON_BLOCK_SPI_MMAP
 	def_bool y
 	select X86_CUSTOM_BOOTMEDIA
 	depends on SOC_AMD_COMMON_BLOCK_SPI
 	depends on !SOC_AMD_COMMON_BLOCK_LPC_SPI_DMA
+	depends on !SOC_AMD_COMMON_BLOCK_SPI_MMAP_USE_ROM3
 	help
 	  This option is required when CONFIG_ROM_SIZE is greater than 16 MiB.
 	  This flash driver still only mmaps 16 MiB of the flash (depending
diff --git a/src/soc/amd/common/block/spi/Makefile.mk b/src/soc/amd/common/block/spi/Makefile.mk
index b80e204ec3..0dc78d9f3b 100644
--- a/src/soc/amd/common/block/spi/Makefile.mk
+++ b/src/soc/amd/common/block/spi/Makefile.mk
@@ -4,6 +4,9 @@ ifeq ($(CONFIG_SOC_AMD_COMMON_BLOCK_SPI),y)
 all_x86-$(CONFIG_SOC_AMD_COMMON_BLOCK_SPI_MMAP) += mmap_boot.c
 smm-$(CONFIG_SOC_AMD_COMMON_BLOCK_SPI_MMAP) += mmap_boot.c
 
+all-$(CONFIG_SOC_AMD_COMMON_BLOCK_SPI_MMAP_USE_ROM3) += mmap_boot_rom3.c
+smm-$(CONFIG_SOC_AMD_COMMON_BLOCK_SPI_MMAP_USE_ROM3) += mmap_boot_rom3.c
+
 bootblock-y += fch_spi_ctrl.c
 romstage-y += fch_spi_ctrl.c
 verstage-y += fch_spi_ctrl.c
diff --git a/src/soc/amd/common/block/spi/mmap_boot_rom3.c b/src/soc/amd/common/block/spi/mmap_boot_rom3.c
new file mode 100644
index 0000000000..bda3a4d92e
--- /dev/null
+++ b/src/soc/amd/common/block/spi/mmap_boot_rom3.c
@@ -0,0 +1,163 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <boot_device.h>
+#include <spi_flash.h>
+#include <stdint.h>
+#include <amdblocks/lpc.h>
+
+enum window_type {
+	/* Fixed decode window of max 16MiB size just below 4G boundary */
+	ROM2_DECODE_WINDOW,
+	/* Additional decode window for mapping BIOS region greater than 16MiB */
+	ROM3_DECODE_WINDOW,
+	TOTAL_DECODE_WINDOWS,
+};
+
+static struct xlate_region_device real_dev;
+static struct mem_region_device shadow_devs[TOTAL_DECODE_WINDOWS];
+static struct xlate_window real_dev_windows[TOTAL_DECODE_WINDOWS];
+
+static void initialize_window(const size_t win_idx, const enum window_type type,
+			      uintptr_t host_base, uintptr_t flash_base, size_t size)
+{
+	mem_region_device_ro_init(&shadow_devs[win_idx], (void *)host_base, size);
+	xlate_window_init(&real_dev_windows[win_idx], &shadow_devs[win_idx].rdev,
+			  flash_base, size);
+	printk(BIOS_INFO, "ROM%d Decode Window: ",
+	       (type == ROM2_DECODE_WINDOW) ? 2 : 3);
+	printk(BIOS_INFO, "SPI flash base=0x%lx, Host base=0x%lx, Size=0x%zx\n",
+	       flash_base, host_base, size);
+}
+
+/*
+ *
+ * Note: This configuration assumes no flash remapping (fch_spi_rom_remapping() = 0).
+ *
+ *                                                                           +--------------+
+ *                                                                           |              |
+ *                                                                           |              |
+ *                                                                           |              |
+ * CONFIG_ROM_SIZE +------------+--------------------------+--------------------------------+- rom3_end
+ *                 |            |                          ^                 |              |
+ *                 |            |                          |                 |     ROM3     |
+ *                 |            |                          |                 |              |
+ *                 |            |                          |                 |              |
+ *                 |            |                          +                 |              |
+ *                 |            |                       rom3_size            |              |
+ *                 |            |                          +                 |              |
+ *                 |  SPI ROM   |                          |                 |              |
+ *                 |            |                     +----+-----------------+--------------+
+ *                 |            |                     |    |                 |              |
+ *                 |            |                     |    |                 |              |
+ *                 |            |                     |    V                 |              |
+ *                 |            |                     |    +---0xfd00000000--+--------------+- rom3_start
+ *                 |            |                     |                      |              |
+ *                 |            |                     |                      |              |
+ *                 |            |                     |                      | Other MMIO   |
+ *                 |            |                     |                      |              |
+ *                 +------------+ --------------------+---------0x100000000--+--------------+- rom2_end
+ *                 |            |              ^                             |              |
+ *                 |            |              |                             |              |
+ *                 |            |          rom2_size                         |     ROM2     |
+ *                 |            |              |                             |              |
+ *                 |            |              V                             |              |
+ *             0   +------------+ ------------------------------0xFF0000000--+--------------+- rom2_start
+ *                                                                           |              |
+ *                  SPI flash                                                |              |
+ *                  address                                                  |              |
+ *                  space                                                    |              |
+ *                                                                           +--------------+
+ *
+ *                                                                            Host address
+ *                                                                            space
+ */
+static void bios_mmap_init(void)
+{
+	static bool init_done;
+	size_t win_count = 0;
+	size_t map_win_size = 0;
+
+	if (init_done)
+		return;
+
+	/*
+	 * By default, fixed decode window (maximum size 16MiB) is mapped just
+	 * below the 4G boundary. This window maps the bottom part of the BIOS
+	 * region in the SPI flash address space to the host address space.
+	 */
+	size_t rom2_size = 0;
+	const uintptr_t rom2_start = lpc_get_rom2_region(&rom2_size);
+	if (rom2_start && rom2_size) {
+		initialize_window(win_count, ROM2_DECODE_WINDOW, rom2_start, 0, rom2_size);
+		win_count++;
+		map_win_size += rom2_size;
+	}
+
+	/*
+	 * Remaining portion of the BIOS region up to a maximum of 64MiB is
+	 * mapped at the bottom of the ROM3 if the BIOS region is greater than 16MiB.
+	 * The ROM3 window is only used when it's inside the identity mapped
+	 * page tables used by x86_64.
+	 *
+	 * If the BIOS region is not greater than 16MiB, then the ROM3 window is not
+	 * enabled.
+	 */
+	size_t rom3_size;
+	const uint64_t rom3_start = lpc_get_rom3_region(&rom3_size);
+	const uint64_t rom3_end = rom3_start + rom3_size;
+
+	if (CONFIG_ROM_SIZE > 16 * MiB) {
+		assert(rom3_start);
+		assert(rom3_size > 16 * MiB);
+		assert(DIV_ROUND_UP(rom3_end, GiB) < CONFIG_CPU_PT_ROM_MAP_GB);
+	}
+
+	if (CONFIG_ROM_SIZE > 16 * MiB &&
+	    rom3_start > 0 &&
+	    rom3_size > 16 * MiB &&
+	    DIV_ROUND_UP(rom3_end, GiB) < CONFIG_CPU_PT_ROM_MAP_GB) {
+
+		const size_t ext_win_size = MIN(rom3_size, CONFIG_ROM_SIZE - rom2_size);
+
+		initialize_window(win_count, ROM3_DECODE_WINDOW,
+				  rom3_start + rom2_size, rom2_size, ext_win_size);
+		win_count++;
+		map_win_size += ext_win_size;
+	}
+
+	assert(map_win_size == CONFIG_ROM_SIZE);
+	xlate_region_device_ro_init(&real_dev, win_count, real_dev_windows, map_win_size);
+
+	init_done = true;
+}
+
+const struct region_device *boot_device_ro(void)
+{
+	bios_mmap_init();
+
+	return &real_dev.rdev;
+}
+
+uint32_t spi_flash_get_mmap_windows(struct flash_mmap_window *table)
+{
+	int i;
+	uint32_t count = 0;
+
+	bios_mmap_init();
+
+	for (i = 0; i < TOTAL_DECODE_WINDOWS; i++) {
+		if (region_sz(&real_dev_windows[i].sub_region) == 0)
+			continue;
+
+		count++;
+		table->flash_base = region_offset(&real_dev_windows[i].sub_region);
+		/* FIXME: Allow SPI mmap in 64-bit address space */
+		if ((uintptr_t)rdev_mmap_full(&shadow_devs[i].rdev) < 4ULL * GiB)
+			table->host_base = (uintptr_t)rdev_mmap_full(&shadow_devs[i].rdev);
+		table->size = region_sz(&real_dev_windows[i].sub_region);
+
+		table++;
+	}
+
+	return count;
+}
diff --git a/src/soc/amd/glinda/Kconfig b/src/soc/amd/glinda/Kconfig
index cfee669184..868a984bcc 100644
--- a/src/soc/amd/glinda/Kconfig
+++ b/src/soc/amd/glinda/Kconfig
@@ -101,6 +101,9 @@ config CHIPSET_DEVICETREE
 	string
 	default "soc/amd/glinda/chipset.cb"
 
+config CPU_PT_ROM_MAP_GB
+	default 1024
+
 config EARLY_RESERVED_DRAM_BASE
 	hex
 	default 0x2000000

From e4fc00adbe5cc32fb366011aef1526bfbee901d8 Mon Sep 17 00:00:00 2001
From: Patrick Rudolph <patrick.rudolph@9elements.com>
Date: Thu, 27 Feb 2025 10:00:21 +0100
Subject: [PATCH 1081/3886] soc/amd/common/block: Enable MMCONF first

Enabling MMCONF is simple and should be done first to allow bootblock
code to access the PCI config space. Required to cache ROM3 in
early_cache_setup() that is now called directly after enabling MMCONF.

Change-Id: I5d5f533258985211afafd9bf748f8e26f6128bd4
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86619
Reviewed-by: Naresh <naresh.solanki.2011@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/soc/amd/common/block/cpu/noncar/bootblock.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/soc/amd/common/block/cpu/noncar/bootblock.c b/src/soc/amd/common/block/cpu/noncar/bootblock.c
index e32499de04..419510ee6c 100644
--- a/src/soc/amd/common/block/cpu/noncar/bootblock.c
+++ b/src/soc/amd/common/block/cpu/noncar/bootblock.c
@@ -12,9 +12,9 @@
 
 asmlinkage void bootblock_c_entry(uint64_t base_timestamp)
 {
+	enable_pci_mmconf();
 	early_cache_setup();
 	write_resume_eip();
-	enable_pci_mmconf();
 
 	if (CONFIG(VBOOT_STARTS_BEFORE_BOOTBLOCK))
 		boot_with_psp_timestamp(base_timestamp);

From 43f7c537f8fefee4babb354c45022518618538dd Mon Sep 17 00:00:00 2001
From: Lei Cao <caolei6@huaqin.corp-partner.google.com>
Date: Tue, 20 May 2025 14:29:35 +0800
Subject: [PATCH 1082/3886] mb/google/trulo/var/pujjocento: update
 GPP_R4/GPP_R5 setting

update GPP_R4/GPP_R5 setting based on pujjocento proto schematic.

BUG=b:409752486
TEST=emerge-nissa sys-boot/coreboot sys-boot/chromeos-bootimage

Change-Id: I5a2926a074e801162972d950c62002352fb5cf6e
Signed-off-by: Lei Cao <caolei6@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87756
Reviewed-by: Kun Liu <liukun11@huaqin.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
---
 src/mainboard/google/brya/variants/pujjocento/gpio.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/mainboard/google/brya/variants/pujjocento/gpio.c b/src/mainboard/google/brya/variants/pujjocento/gpio.c
index 488038b9aa..efa8249e88 100644
--- a/src/mainboard/google/brya/variants/pujjocento/gpio.c
+++ b/src/mainboard/google/brya/variants/pujjocento/gpio.c
@@ -314,9 +314,9 @@ static const struct pad_config gpio_table[] = {
 	/* R3 : HDA_SDI0 ==> HDA_SDIN0 */
 	PAD_CFG_NF(GPP_R3, NONE, DEEP, NF1),
 	/* R4 : HDA_RST# ==> HDA_RST# */
-	PAD_CFG_NF(GPP_R4, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_R4, NONE, DEEP, NF3),
 	/* R5 : HDA_SDI1 ==> HDA_SDIN1 */
-	PAD_CFG_NF(GPP_R5, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_R5, NONE, DEEP, NF3),
 	/* R6 : DMIC_CLK_A_1A ==> DMIC_WCAM_CLK_R */
 	PAD_CFG_NF(GPP_R6, NONE, DEEP, NF3),
 	/* R7 : DMIC_DATA_1A ==> DMIC_WCAM_DATA */

From 278a6d26822d61ca70e175543490e1f458490fc3 Mon Sep 17 00:00:00 2001
From: Lei Cao <caolei6@huaqin.corp-partner.google.com>
Date: Thu, 15 May 2025 15:57:40 +0800
Subject: [PATCH 1083/3886] mb/google/trulo/var/pujjocento: update hda_verb
 table for ALC257

update hda_verb table for pujjocento, provided by Realtek on 20250515.

BUG=b:409752486
TEST=emerge-nissa sys-boot/coreboot sys-boot/chromeos-bootimage

Device list:
cat /sys/bus/hdaudio/devices/ehdaudio0D0/chip_name
ALC257
cat /sys/bus/hdaudio/devices/ehdaudio0D0/vendor_name
Realtek

Headphone detection:
Event: type 5 (EV_SW), code 2 (SW_HEADPHONE_INSERT), value 0
Event: -------------- SYN_REPORT ------------
Event: type 5 (EV_SW), code 2 (SW_HEADPHONE_INSERT), value 1
Event: -------------- SYN_REPORT ------------
Event: type 1 (EV_KEY), code 164 (KEY_PLAYPAUSE), value 1
Event: type 1 (EV_KEY), code 115 (KEY_VOLUMEUP), value 1
Event: type 1 (EV_KEY), code 114 (KEY_VOLUMEDOWN), value 1

Change-Id: Ib0a22acdbcbe6643665f9f07469fba41e8027d7c
Signed-off-by: Lei Cao <caolei6@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87693
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kun Liu <liukun11@huaqin.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
---
 .../brya/variants/pujjocento/hda_verb.c       | 104 ++++++------------
 1 file changed, 31 insertions(+), 73 deletions(-)

diff --git a/src/mainboard/google/brya/variants/pujjocento/hda_verb.c b/src/mainboard/google/brya/variants/pujjocento/hda_verb.c
index bf998e1f0c..c995caf0f6 100644
--- a/src/mainboard/google/brya/variants/pujjocento/hda_verb.c
+++ b/src/mainboard/google/brya/variants/pujjocento/hda_verb.c
@@ -4,13 +4,13 @@
 
 const u32 cim_verb_data[] = {
 	/* coreboot specific header */
-	0x10ec0256,	// Codec Vendor / Device ID: Realtek ALC256
-	0x10ec12ac,	// Subsystem ID
-	0x00000013,	// Number of jacks (NID entries)
+	0x10ec0257,	// Codec Vendor / Device ID: Realtek ALC257
+	0x10ec0257,	// Subsystem ID
+	0x00000010,	// Number of jacks (NID entries)
 
 	AZALIA_RESET(0x1),
 	/* NID 0x01, HDA Codec Subsystem ID Verb table */
-	AZALIA_SUBVENDOR(0, 0x10ec12ac),
+	AZALIA_SUBVENDOR(0, 0x10ec3a2c),
 
 	/* Pin Widget Verb Table */
 
@@ -27,100 +27,58 @@ const u32 cim_verb_data[] = {
 	/* Pin widget 0x18 - NPC */
 	AZALIA_PIN_CFG(0, 0x18, 0x411111F0),
 	/* Pin widget 0x19 - MIC2 (Port-F) */
-	AZALIA_PIN_CFG(0, 0x19, 0x04A11040),
+	AZALIA_PIN_CFG(0, 0x19, 0x04A11030),
 	/* Pin widget 0x1A - LINE1 (Port-C) */
 	AZALIA_PIN_CFG(0, 0x1a, 0x411111F0),
 	/* Pin widget 0x1B - NPC */
 	AZALIA_PIN_CFG(0, 0x1b, 0x411111F0),
 	/* Pin widget 0x1D - BEEP-IN */
-	AZALIA_PIN_CFG(0, 0x1d, 0x40610041),
+	AZALIA_PIN_CFG(0, 0x1d, 0x40579A2D),
 	/* Pin widget 0x1E - NPC */
 	AZALIA_PIN_CFG(0, 0x1e, 0x411111F0),
 	/* Pin widget 0x21 - HP1-OUT (Port-I) */
 	AZALIA_PIN_CFG(0, 0x21, 0x04211020),
-	/*
-	 * Widget node 0x20 - 1
-	 * Codec hidden reset and speaker power 2W/4ohm
-	 */
+	/* Widget node 0x20 - 0 */
 	0x0205001A,
 	0x0204C003,
+	0x0205001A,
+	0x0204C003,
+	/* Widget node 0x20 - 1 */
 	0x02050038,
-	0x02047901,
-	/*
-	 * Widget node 0x20 - 2
-	 * Class D power on Reset
-	 */
-	0x0205003C,
-	0x02040354,
-	0x0205003C,
-	0x02040314,
-	/*
-	 * Widget node 0x20 - 3
-	 * Disable AGC and set AGC limit to -1.5dB
-	 */
-	0x02050016,
-	0x02040C50,
-	0x02050012,
-	0x0204EBC1,
-	/*
-	 * Widget node 0x20 - 4
-	 * Set AGC Post gain +1.5dB then Enable AGC
-	 */
-	0x02050013,
-	0x02044023,
-	0x02050016,
-	0x02040E50,
-	/*
-	 * Widget node 0x20 - 5
-	 * Silence detector enabling + Set EAPD to verb control
-	 */
-	0x02050037,
-	0x0204FE15,
-	0x02050010,
-	0x02040020,
-	/*
-	 * Widget node 0x20 - 6
-	 * Silence data mode Threshold (-90dB)
-	 */
-	0x02050030,
-	0x0204A000,
+	0x02046981,
 	0x0205001B,
 	0x02040A4B,
-	/*
-	 * Widget node 0x20 - 7
-	 * Default setting - 1
-	 */
-	0x05750003,
-	0x05740DA3,
+	/* Widget node 0x20 - 2 */
+	0x0205003C,
+	0x02043154,
+	0x0205003C,
+	0x02043114,
+	/* Widget node 0x20 - 3 */
 	0x02050046,
 	0x02040004,
-	/*
-	 * Widget node 0x20 - 8
-	 * support 1 pin detect two port
-	 */
+	0x05750003,
+	0x057409A3,
+	/* Widget node 0x20 - 4 */
 	0x02050009,
-	0x0204E003,
+	0x02044003,
 	0x0205000A,
-	0x02047770,
-	/*
-	 * Widget node 0x20 - 9
-	 * To set LDO1/LDO2 as default (used for headset)
-	 */
-	0x02050008,
-	0x02046A0C,
-	0x02050008,
-	0x02046A0C,
+	0x02047778,
+	/* Widget node 0x20 - 5 */
+	0x02050037,
+	0x0204FE15,
+	0x02050030,
+	0x02041000,
 };
 
 const u32 pc_beep_verbs[] = {
 	/* Dos beep path - 1 */
-	0x01470C00,
+	0x02050010,
+	0x02040020,
 	0x02050036,
 	0x02047151,
-	0x01470740,
 	/* Dos beep path - 2 */
-	0x0143b000,
-	0x01470C02,
+	0x01470740,
+	0x0143B000,
 	0x01470C02,
 	0x01470C02,
 };

From 918f21b72d6bc55bd9e43eebfd7e804752a8605e Mon Sep 17 00:00:00 2001
From: Keith Hui <buurin@gmail.com>
Date: Sat, 19 Apr 2025 22:48:02 -0400
Subject: [PATCH 1084/3886] drivers/spi/winbond.c: Add W25Q64JV signature

I am using a pair of Winbond W25Q64JVSSIM SPI flash chips for
coreboot development. While working on Asus P8x7x Series
autonomous soft strap update support, aka CB:85413 and CB:87334,
I found that without its signature (mfgr 0xef, dev 0x7017) added,
rdev_writeat() would fail to get anything into the flash chip
even though it reports success. Its other parameters are copied
from W25Q64_V as the two are almost the same.

Change-Id: I4af6268a2a1bde4d2ff9c76879c3bc59b91a916d
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87363
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
---
 src/drivers/spi/winbond.c | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/src/drivers/spi/winbond.c b/src/drivers/spi/winbond.c
index db93ff616c..2999676b08 100644
--- a/src/drivers/spi/winbond.c
+++ b/src/drivers/spi/winbond.c
@@ -157,6 +157,15 @@ static const struct spi_flash_part_id flash_table[] = {
 		.protection_granularity_shift	= 17,
 		.bp_bits			= 3,
 	},
+	{
+		/* W25Q64JV */
+		.id[0]				= 0x7017,
+		.nr_sectors_shift		= 11,
+		.fast_read_dual_output_support	= 1,
+		.fast_read_dual_io_support	= 1,
+		.protection_granularity_shift	= 17,
+		.bp_bits			= 3,
+	},
 	{
 		/* W25Q64JW */
 		.id[0]				= 0x8017,

From 71fb8f63e0f54bbdc9d60e9ad6e9173107cde7ee Mon Sep 17 00:00:00 2001
From: Werner Zeh <werner.zeh@siemens.com>
Date: Wed, 14 May 2025 10:17:57 +0200
Subject: [PATCH 1085/3886] mb/siemens/mc_rpl: Add new mainboard based on
 Intel's Alder Lake RVP

This patch adds a new mainboard called 'mc_rpl' which is based on the
Intel Alder Lake RVP. Only the needed changes are made in this patch in
order to make it compile with proper names. Follow-up patches will
tailor it more towards the real mainboard hardware.

Change-Id: Ic0caa621350848d459def6044ca0a6dfd88f873f
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87664
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/siemens/mc_rpl/Kconfig          | 137 +++++
 src/mainboard/siemens/mc_rpl/Kconfig.name     |   6 +
 src/mainboard/siemens/mc_rpl/Makefile.mk      |  34 ++
 src/mainboard/siemens/mc_rpl/board_id.c       |  15 +
 src/mainboard/siemens/mc_rpl/board_id.h       |  17 +
 src/mainboard/siemens/mc_rpl/board_info.txt   |   6 +
 src/mainboard/siemens/mc_rpl/bootblock.c      |   9 +
 src/mainboard/siemens/mc_rpl/chromeos.c       |  50 ++
 src/mainboard/siemens/mc_rpl/chromeos.fmd     |  54 ++
 src/mainboard/siemens/mc_rpl/devicetree.cb    | 469 ++++++++++++++++++
 src/mainboard/siemens/mc_rpl/devicetree_m.cb  | 406 +++++++++++++++
 src/mainboard/siemens/mc_rpl/devicetree_n.cb  | 403 +++++++++++++++
 src/mainboard/siemens/mc_rpl/dsdt.asl         |  39 ++
 src/mainboard/siemens/mc_rpl/early_gpio.c     | 148 ++++++
 src/mainboard/siemens/mc_rpl/early_gpio_m.c   | 142 ++++++
 src/mainboard/siemens/mc_rpl/early_gpio_n.c   |  30 ++
 src/mainboard/siemens/mc_rpl/ec.c             |  19 +
 src/mainboard/siemens/mc_rpl/fw_config.c      |  41 ++
 src/mainboard/siemens/mc_rpl/gpio.c           | 276 +++++++++++
 src/mainboard/siemens/mc_rpl/gpio_m.c         | 193 +++++++
 src/mainboard/siemens/mc_rpl/gpio_n.c         | 239 +++++++++
 .../siemens/mc_rpl/include/baseboard/ec.h     |  72 +++
 .../siemens/mc_rpl/include/baseboard/gpio.h   |  17 +
 .../mc_rpl/include/baseboard/variants.h       |  52 ++
 src/mainboard/siemens/mc_rpl/mainboard.c      |  91 ++++
 src/mainboard/siemens/mc_rpl/memory.c         | 381 ++++++++++++++
 src/mainboard/siemens/mc_rpl/memory_rpl.c     |  28 ++
 src/mainboard/siemens/mc_rpl/ramstage.c       | 103 ++++
 .../siemens/mc_rpl/romstage_fsp_params.c      | 112 +++++
 src/mainboard/siemens/mc_rpl/smihandler.c     |  30 ++
 src/mainboard/siemens/mc_rpl/spd/Makefile.mk  |  10 +
 .../siemens/mc_rpl/spd/adlrvp_ddr5_mr.spd.hex |  32 ++
 .../siemens/mc_rpl/spd/adlrvp_lp4.spd.hex     |  32 ++
 .../siemens/mc_rpl/spd/adlrvp_lp5.spd.hex     |  32 ++
 .../siemens/mc_rpl/spd/adlrvp_n_lp5.spd.hex   |  32 ++
 .../siemens/mc_rpl/spd/empty.spd.hex          |  32 ++
 .../mc_rpl/variants/mc_rpl1/overridetree.cb   |   7 +
 37 files changed, 3796 insertions(+)
 create mode 100644 src/mainboard/siemens/mc_rpl/Kconfig
 create mode 100644 src/mainboard/siemens/mc_rpl/Kconfig.name
 create mode 100644 src/mainboard/siemens/mc_rpl/Makefile.mk
 create mode 100644 src/mainboard/siemens/mc_rpl/board_id.c
 create mode 100644 src/mainboard/siemens/mc_rpl/board_id.h
 create mode 100644 src/mainboard/siemens/mc_rpl/board_info.txt
 create mode 100644 src/mainboard/siemens/mc_rpl/bootblock.c
 create mode 100644 src/mainboard/siemens/mc_rpl/chromeos.c
 create mode 100644 src/mainboard/siemens/mc_rpl/chromeos.fmd
 create mode 100644 src/mainboard/siemens/mc_rpl/devicetree.cb
 create mode 100644 src/mainboard/siemens/mc_rpl/devicetree_m.cb
 create mode 100644 src/mainboard/siemens/mc_rpl/devicetree_n.cb
 create mode 100644 src/mainboard/siemens/mc_rpl/dsdt.asl
 create mode 100644 src/mainboard/siemens/mc_rpl/early_gpio.c
 create mode 100644 src/mainboard/siemens/mc_rpl/early_gpio_m.c
 create mode 100644 src/mainboard/siemens/mc_rpl/early_gpio_n.c
 create mode 100644 src/mainboard/siemens/mc_rpl/ec.c
 create mode 100644 src/mainboard/siemens/mc_rpl/fw_config.c
 create mode 100644 src/mainboard/siemens/mc_rpl/gpio.c
 create mode 100644 src/mainboard/siemens/mc_rpl/gpio_m.c
 create mode 100644 src/mainboard/siemens/mc_rpl/gpio_n.c
 create mode 100644 src/mainboard/siemens/mc_rpl/include/baseboard/ec.h
 create mode 100644 src/mainboard/siemens/mc_rpl/include/baseboard/gpio.h
 create mode 100644 src/mainboard/siemens/mc_rpl/include/baseboard/variants.h
 create mode 100644 src/mainboard/siemens/mc_rpl/mainboard.c
 create mode 100644 src/mainboard/siemens/mc_rpl/memory.c
 create mode 100644 src/mainboard/siemens/mc_rpl/memory_rpl.c
 create mode 100644 src/mainboard/siemens/mc_rpl/ramstage.c
 create mode 100644 src/mainboard/siemens/mc_rpl/romstage_fsp_params.c
 create mode 100644 src/mainboard/siemens/mc_rpl/smihandler.c
 create mode 100644 src/mainboard/siemens/mc_rpl/spd/Makefile.mk
 create mode 100644 src/mainboard/siemens/mc_rpl/spd/adlrvp_ddr5_mr.spd.hex
 create mode 100644 src/mainboard/siemens/mc_rpl/spd/adlrvp_lp4.spd.hex
 create mode 100644 src/mainboard/siemens/mc_rpl/spd/adlrvp_lp5.spd.hex
 create mode 100644 src/mainboard/siemens/mc_rpl/spd/adlrvp_n_lp5.spd.hex
 create mode 100644 src/mainboard/siemens/mc_rpl/spd/empty.spd.hex
 create mode 100644 src/mainboard/siemens/mc_rpl/variants/mc_rpl1/overridetree.cb

diff --git a/src/mainboard/siemens/mc_rpl/Kconfig b/src/mainboard/siemens/mc_rpl/Kconfig
new file mode 100644
index 0000000000..698df3c4d0
--- /dev/null
+++ b/src/mainboard/siemens/mc_rpl/Kconfig
@@ -0,0 +1,137 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
+config BOARD_SIEMENS_BASEBOARD_MC_RPL
+	def_bool n
+	select BOARD_ROMSIZE_KB_32768
+	select CPU_INTEL_SOCKET_LGA1700
+	select DRIVERS_I2C_GENERIC
+	select DRIVERS_I2C_HID
+	select DRIVERS_I2C_MAX98373
+	select DRIVERS_INTEL_DPTF
+	select DRIVERS_INTEL_MIPI_CAMERA
+	select DRIVERS_INTEL_SOUNDWIRE
+	select DRIVERS_SOUNDWIRE_ALC_BASE_7XX
+	select DRIVERS_SPI_ACPI
+	select DRIVERS_USB_ACPI
+	select HAVE_ACPI_RESUME
+	select HAVE_ACPI_TABLES
+	select HAVE_SPD_IN_CBFS
+	select MAINBOARD_HAS_CHROMEOS
+	select SOC_INTEL_COMMON_BLOCK_IPU
+	select SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES
+
+
+config BOARD_SIEMENS_MC_RPL1
+	select BOARD_SIEMENS_BASEBOARD_MC_RPL
+	select DRIVERS_UART_8250IO
+	select GEN3_EXTERNAL_CLOCK_BUFFER
+	select MAINBOARD_USES_IFD_EC_REGION
+	select SOC_INTEL_ALDERLAKE_PCH_P
+	select SOC_INTEL_RAPTORLAKE
+
+if BOARD_SIEMENS_BASEBOARD_MC_RPL
+
+config SOC_INTEL_CSE_LITE_SKU
+	bool "Use CSE Lite firmware"
+	default y if MC_RPL_CHROME_EC
+	help
+	  Enable if CSE Lite firmware is used in your build. It is commonly
+	  used in Chrome boards (chromebooks, chromeboxes, ...).
+	  But since ADL RVP build can be used with or without CSE Lite firmware
+	  it is a configurable option. Alderlake RVP boards usually don't use
+	  an CSE Lite firmware, but are still very likely to use it in case
+	  ChromeEC is used.
+
+config CHROMEOS
+	select GBB_FLAG_FORCE_DEV_SWITCH_ON
+	select GBB_FLAG_FORCE_DEV_BOOT_USB
+	select GBB_FLAG_FORCE_DEV_BOOT_ALTFW
+	select GBB_FLAG_FORCE_MANUAL_RECOVERY
+	select GBB_FLAG_DISABLE_PD_SOFTWARE_SYNC
+	select HAS_RECOVERY_MRC_CACHE
+
+config MAINBOARD_DIR
+	default "siemens/mc_rpl"
+
+config VARIANT_DIR
+	default "mc_rpl1" if BOARD_SIEMENS_MC_RPL1
+
+config GBB_HWID
+	string
+	depends on CHROMEOS
+	default "ADLRVPN TEST 7673" if BOARD_INTEL_ADLRVP_N || BOARD_INTEL_ADLRVP_N_EXT_EC
+	default "ADLRVPP TEST 2418"
+
+config MAINBOARD_PART_NUMBER
+	default "MC RPL1" if BOARD_SIEMENS_MC_RPL1
+
+config MAINBOARD_VENDOR
+	string
+	default "Siemens"
+
+config MAINBOARD_FAMILY
+	string
+	default "MC RPL"
+
+config DEVICETREE
+	default "devicetree.cb"
+
+config OVERRIDE_DEVICETREE
+	default "variants/\$(CONFIG_VARIANT_DIR)/overridetree.cb"
+
+choice
+	prompt "ON BOARD EC"
+	default MC_RPL_CHROME_EC if BOARD_SIEMENS_MC_RPL1
+	help
+	  This option allows you to select the on board EC to use.
+	  Select whether the board has Intel EC or Chrome EC
+
+config MC_RPL_CHROME_EC
+	bool "Chrome EC"
+	select EC_GOOGLE_CHROMEEC
+	select EC_GOOGLE_CHROMEEC_ESPI
+	select EC_GOOGLE_CHROMEEC_BOARDID
+	select EC_ACPI
+	select EC_GOOGLE_CHROMEEC_LPC
+
+config MC_RPL_INTEL_EC
+	bool "Intel EC"
+	select EC_ACPI
+endchoice
+
+config VBOOT
+	select VBOOT_LID_SWITCH
+	select VBOOT_MOCK_SECDATA if BOARD_INTEL_ADLRVP_P_EXT_EC || BOARD_INTEL_ADLRVP_N_EXT_EC
+	select EC_GOOGLE_CHROMEEC_SWITCHES if MC_RPL_CHROME_EC
+	select VBOOT_EARLY_EC_SYNC if BOARD_INTEL_ADLRVP_N_EXT_EC
+
+config UART_FOR_CONSOLE
+	int
+	default 0
+
+config DRIVER_TPM_SPI_BUS
+	default 0x2 if BOARD_SIEMENS_MC_RPL1
+
+config USE_PM_ACPI_TIMER
+	default n if BOARD_SIEMENS_MC_RPL1
+
+config TPM_TIS_ACPI_INTERRUPT
+	int
+	default 67 if BOARD_INTEL_ADLRVP_RPL_EXT_EC # GPE0_DW2_3 (GPP_E3)
+
+config GEN3_EXTERNAL_CLOCK_BUFFER
+	bool
+	depends on SOC_INTEL_ALDERLAKE_PCH_P
+	default n
+	help
+	  Support external Gen-3 clock chip for ADL-P.
+	  `CONFIG_CLKSRC_FOR_EXTERNAL_BUFFER` provides feed clock to discrete buffer
+	  for further distribution to platform. SRCCLKREQB[7:9] maps to internal
+	  SRCCLKREQB[6]. If any of them asserted, SRC buffer
+	  `CONFIG_CLKSRC_FOR_EXTERNAL_BUFFER` gets enabled.
+
+config CLKSRC_FOR_EXTERNAL_BUFFER
+	depends on GEN3_EXTERNAL_CLOCK_BUFFER
+	int
+	default 6  # CLKSRC 6
+endif
diff --git a/src/mainboard/siemens/mc_rpl/Kconfig.name b/src/mainboard/siemens/mc_rpl/Kconfig.name
new file mode 100644
index 0000000000..8983c9e6d7
--- /dev/null
+++ b/src/mainboard/siemens/mc_rpl/Kconfig.name
@@ -0,0 +1,6 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
+comment "MC RPLx"
+
+config BOARD_SIEMENS_MC_RPL1
+	bool "-> MC RPL1"
diff --git a/src/mainboard/siemens/mc_rpl/Makefile.mk b/src/mainboard/siemens/mc_rpl/Makefile.mk
new file mode 100644
index 0000000000..b63953c0e0
--- /dev/null
+++ b/src/mainboard/siemens/mc_rpl/Makefile.mk
@@ -0,0 +1,34 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
+subdirs-y += spd
+
+bootblock-y += bootblock.c
+bootblock-$(CONFIG_CHROMEOS) += chromeos.c
+ifeq ($(CONFIG_SOC_INTEL_ALDERLAKE_PCH_N),y)
+bootblock-y += early_gpio_n.c
+ramstage-y += gpio_n.c
+else
+bootblock-y += early_gpio.c
+ramstage-y += gpio.c
+endif
+
+verstage-$(CONFIG_CHROMEOS) += chromeos.c
+
+romstage-$(CONFIG_CHROMEOS) += chromeos.c
+romstage-y += romstage_fsp_params.c
+romstage-y += board_id.c
+romstage-y += memory.c
+ifeq ($(CONFIG_BOARD_INTEL_ADLRVP_RPL_EXT_EC),y)
+romstage-y += memory_rpl.c
+endif
+
+ramstage-$(CONFIG_CHROMEOS) += chromeos.c
+ramstage-y += ec.c
+ramstage-y += mainboard.c
+ramstage-y += board_id.c
+ramstage-$(CONFIG_FW_CONFIG) += fw_config.c
+ramstage-y += ramstage.c
+
+CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/include
+
+subdirs-y += variants/$(VARIANT_DIR)
diff --git a/src/mainboard/siemens/mc_rpl/board_id.c b/src/mainboard/siemens/mc_rpl/board_id.c
new file mode 100644
index 0000000000..02445f2f3a
--- /dev/null
+++ b/src/mainboard/siemens/mc_rpl/board_id.c
@@ -0,0 +1,15 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <boardid.h>
+#include <ec/acpi/ec.h>
+#include <ec/google/chromeec/ec.h>
+#include <types.h>
+#include "board_id.h"
+
+/* Get Board ID via EC I/O port write/read */
+int get_board_id(void)
+{
+	static int id = 1;
+
+	return (id & BOARD_ID_MASK);
+}
diff --git a/src/mainboard/siemens/mc_rpl/board_id.h b/src/mainboard/siemens/mc_rpl/board_id.h
new file mode 100644
index 0000000000..2988127e9b
--- /dev/null
+++ b/src/mainboard/siemens/mc_rpl/board_id.h
@@ -0,0 +1,17 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef _MAINBOARD_COMMON_BOARD_ID_H_
+#define _MAINBOARD_COMMON_BOARD_ID_H_
+
+/* Board/FAB ID Command */
+#define EC_FAB_ID_CMD	0x0d
+/* Bit 5:0 for Board ID */
+#define BOARD_ID_MASK	0x3f
+
+/*
+ * Returns board information (board id[15:8] and
+ * Fab info[7:0]) on success and < 0 on error
+ */
+int get_board_id(void);
+
+#endif /* _MAINBOARD_COMMON_BOARD_ID_H_ */
diff --git a/src/mainboard/siemens/mc_rpl/board_info.txt b/src/mainboard/siemens/mc_rpl/board_info.txt
new file mode 100644
index 0000000000..1c0d6c8745
--- /dev/null
+++ b/src/mainboard/siemens/mc_rpl/board_info.txt
@@ -0,0 +1,6 @@
+Vendor name: Siemens
+Board name: MC RPL
+Category: misc
+ROM protocol: SPI
+ROM socketed: n
+Flashrom support: y
diff --git a/src/mainboard/siemens/mc_rpl/bootblock.c b/src/mainboard/siemens/mc_rpl/bootblock.c
new file mode 100644
index 0000000000..eeee406f12
--- /dev/null
+++ b/src/mainboard/siemens/mc_rpl/bootblock.c
@@ -0,0 +1,9 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <baseboard/variants.h>
+#include <bootblock_common.h>
+
+void bootblock_mainboard_early_init(void)
+{
+	variant_configure_early_gpio_pads();
+}
diff --git a/src/mainboard/siemens/mc_rpl/chromeos.c b/src/mainboard/siemens/mc_rpl/chromeos.c
new file mode 100644
index 0000000000..4c2d1e516f
--- /dev/null
+++ b/src/mainboard/siemens/mc_rpl/chromeos.c
@@ -0,0 +1,50 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <baseboard/gpio.h>
+#include <bootmode.h>
+#include <boot/coreboot_tables.h>
+#include <gpio.h>
+#include <types.h>
+
+void fill_lb_gpios(struct lb_gpios *gpios)
+{
+	struct lb_gpio chromeos_gpios[] = {
+		{-1, ACTIVE_HIGH, get_lid_switch(), "lid"},
+		{-1, ACTIVE_HIGH, 0, "power"},
+		{-1, ACTIVE_HIGH, gfx_get_init_done(), "oprom"},
+		{GPIO_EC_IN_RW, ACTIVE_HIGH, gpio_get(GPIO_EC_IN_RW), "EC in RW"},
+	};
+	if (CONFIG(BOARD_INTEL_ADLRVP_P_EXT_EC) || CONFIG(BOARD_INTEL_ADLRVP_N_EXT_EC) ||
+	    CONFIG(BOARD_INTEL_ADLRVP_RPL_EXT_EC))
+		lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios));
+	else
+		lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios) - 1);
+}
+
+#if !CONFIG(EC_GOOGLE_CHROMEEC_SWITCHES)
+int get_lid_switch(void)
+{
+	/* Lid always open */
+	return 1;
+}
+
+int get_recovery_mode_switch(void)
+{
+	return 0;
+}
+#endif /*!CONFIG(EC_GOOGLE_CHROMEEC_SWITCHES) */
+
+int get_write_protect_state(void)
+{
+	/* No write protect */
+	return 0;
+}
+
+#if (CONFIG(BOARD_INTEL_ADLRVP_P_EXT_EC) || CONFIG(BOARD_INTEL_ADLRVP_N_EXT_EC) ||\
+	 CONFIG(BOARD_INTEL_ADLRVP_RPL_EXT_EC))
+int get_ec_is_trusted(void)
+{
+	/* EC is trusted if not in RW. */
+	return !gpio_get(GPIO_EC_IN_RW);
+}
+#endif
diff --git a/src/mainboard/siemens/mc_rpl/chromeos.fmd b/src/mainboard/siemens/mc_rpl/chromeos.fmd
new file mode 100644
index 0000000000..0e8d321f85
--- /dev/null
+++ b/src/mainboard/siemens/mc_rpl/chromeos.fmd
@@ -0,0 +1,54 @@
+FLASH 32M {
+	SI_ALL 6M {
+		SI_DESC 4K
+		SI_EC 512K
+		SI_ME {
+			CSE_LAYOUT 8K
+			CSE_RO 1588K
+			CSE_DATA 512K
+			# 64-KiB aligned to optimize RW erases during CSE update.
+			CSE_RW 3520K
+		}
+	}
+	SI_BIOS 26M {
+		RW_SECTION_A 8M {
+			VBLOCK_A 64K
+			FW_MAIN_A(CBFS)
+			RW_FWID_A 64
+		}
+		RW_LEGACY(CBFS) 1M
+		RW_MISC 1M {
+			UNIFIED_MRC_CACHE(PRESERVE) 192K {
+				RECOVERY_MRC_CACHE 64K
+				RW_MRC_CACHE 128K
+			}
+			RW_ELOG(PRESERVE) 16K
+			RW_SHARED 16K {
+				SHARED_DATA 8K
+				VBLOCK_DEV 8K
+			}
+			RW_VPD(PRESERVE) 8K
+			RW_NVRAM(PRESERVE) 24K
+		}
+		# This section starts at the 16M boundary in SPI flash.
+		# ADL does not support a region crossing this boundary,
+		# because the SPI flash is memory-mapped into two non-
+		# contiguous windows.
+		RW_SECTION_B 8M {
+			VBLOCK_B 64K
+			FW_MAIN_B(CBFS)
+			RW_FWID_B 64
+		}
+		# Make WP_RO region align with SPI vendor
+		# memory protected range specification.
+		WP_RO 8M {
+			RO_VPD(PRESERVE) 16K
+			RO_SECTION {
+				FMAP 2K
+				RO_FRID 64
+				GBB@4K 448K
+				COREBOOT(CBFS)
+			}
+		}
+	}
+}
diff --git a/src/mainboard/siemens/mc_rpl/devicetree.cb b/src/mainboard/siemens/mc_rpl/devicetree.cb
new file mode 100644
index 0000000000..031b2f059b
--- /dev/null
+++ b/src/mainboard/siemens/mc_rpl/devicetree.cb
@@ -0,0 +1,469 @@
+chip soc/intel/alderlake
+
+	# This disables autonomous GPIO power management, otherwise
+	# old cr50 FW only supports short pulses.
+	register "gpio_override_pm" = "1"
+	register "gpio_pm[COMM_0]" = "0"
+	register "gpio_pm[COMM_1]" = "0"
+	register "gpio_pm[COMM_2]" = "0"
+	register "gpio_pm[COMM_4]" = "0"
+	register "gpio_pm[COMM_5]" = "0"
+
+	# GPE configuration
+	# Note that GPE events called out in ASL code rely on this
+	# route. i.e. If this route changes then the affected GPE
+	# offset bits also need to be changed.
+	register "pmc_gpe0_dw0" = "GPP_B"
+	register "pmc_gpe0_dw1" = "GPP_D"
+	register "pmc_gpe0_dw2" = "GPP_E"
+
+	# FSP configuration
+
+	# Enable CNVi BT
+	register "cnvi_bt_core" = "true"
+
+	# Sagv Configuration
+	register "sagv" = "SaGv_Enabled"
+
+	register "usb2_ports[0]" = "USB2_PORT_MID(OC0)"		# Type-C Port1
+	register "usb2_ports[1]" = "USB2_PORT_MID(OC0)"		# Type-C Port2
+	register "usb2_ports[2]" = "USB2_PORT_MID(OC3)"		# Type-C Port3
+	register "usb2_ports[3]" = "USB2_PORT_MID(OC_SKIP)"	# M.2 WWAN
+	register "usb2_ports[4]" = "USB2_PORT_MID(OC3)"		# Type-C Port4
+	register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)"	# FPS connector
+	register "usb2_ports[6]" = "USB2_PORT_MID(OC0)"		# USB3/2 Type A port1
+	register "usb2_ports[7]" = "USB2_PORT_MID(OC0)"		# USB3/2 Type A port2
+	register "usb2_ports[8]" = "USB2_PORT_MID(OC3)"		# USB3/2 Type A port3
+	register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)"	# M.2 WLAN
+
+	register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC3)"	# USB3/2 Type A port1
+	register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC0)"	# USB3/2 Type A port2
+	register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC0)"	# USB3/2 Type A port3
+	register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)"	# M.2 WWAN
+
+	# EC host command ranges are in 0x800-0x8ff & 0x200-0x20f
+	register "gen1_dec" = "0x00fc0801"
+	register "gen2_dec" = "0x000c0201"
+	# EC memory map range is 0x900-0x9ff
+	register "gen3_dec" = "0x00fc0901"
+
+	# Enable PCH PCIE RP 5 using CLK 2
+	register "pch_pcie_rp[PCH_RP(5)]" = "{
+		.clk_src = 2,
+		.clk_req = 2,
+		.flags = PCIE_RP_CLK_REQ_DETECT,
+	}"
+
+	# Enable PCH PCIE RP 6 using CLK 5
+	register "pch_pcie_rp[PCH_RP(6)]" = "{
+		.clk_src = 5,
+		.clk_req = 5,
+		.flags = PCIE_RP_CLK_REQ_DETECT,
+	}"
+
+	# NOTE: requires GPP_A7 set to Native Function 1 for SRCCLK_OE7
+	register "pch_pcie_rp[PCH_RP(8)]" = "{
+                .clk_src = 7,
+                .clk_req = 7,
+                .flags = PCIE_RP_CLK_REQ_DETECT | PCIE_RP_LTR,
+                .PcieRpL1Substates = L1_SS_L1_2,
+		.pcie_rp_detect_timeout_ms = 50,
+	}"
+
+	# Enable PCH PCIE RP 9 using CLK 1
+	register "pch_pcie_rp[PCH_RP(9)]" = "{
+		.clk_src = 1,
+		.clk_req = 1,
+		.flags = PCIE_RP_CLK_REQ_DETECT,
+	}"
+
+	# Enable PCH PCIE RP 11 for optane
+	register "pch_pcie_rp[PCH_RP(11)]" = "{
+		.flags = PCIE_RP_CLK_SRC_UNUSED,
+	}"
+
+	# Hybrid storage mode
+	register "hybrid_storage_mode" = "true"
+
+	# Enable CPU PCIE RP 1 using CLK 0
+	register "cpu_pcie_rp[CPU_RP(1)]" = "{
+		.clk_req = 0,
+		.clk_src = 0,
+		.flags = PCIE_RP_LTR | PCIE_RP_AER,
+	}"
+
+	# Enable CPU PCIE RP 2 using CLK 3
+	register "cpu_pcie_rp[CPU_RP(2)]" = "{
+		.clk_req = 3,
+		.clk_src = 3,
+		.flags = PCIE_RP_LTR | PCIE_RP_AER,
+	}"
+
+	# Enable CPU PCIE RP 3 using CLK 4
+	register "cpu_pcie_rp[CPU_RP(3)]" = "{
+		.clk_req = 4,
+		.clk_src = 4,
+		.flags = PCIE_RP_LTR | PCIE_RP_AER,
+	}"
+
+	register "sata_salp_support" = "1"
+
+	register "sata_ports_enable" = "{
+		[0] = 1,
+		[1] = 1,
+		[2] = 1,
+		[3] = 1,
+	}"
+
+	register "sata_ports_dev_slp" = "{
+		[0] = 1,
+		[1] = 1,
+		[2] = 1,
+		[3] = 1,
+	}"
+
+	# Enable EDP in PortA
+	register "ddi_portA_config" = "1"
+	# Enable HDMI in Port B
+	register "ddi_ports_config" = "{
+		[DDI_PORT_B] = DDI_ENABLE_HPD | DDI_ENABLE_DDC,
+	}"
+
+	# TCSS USB3
+	register "tcss_aux_ori" = "0"
+
+	register "s0ix_enable" = "true"
+	register "dptf_enable" = "true"
+
+	register "serial_io_i2c_mode" = "{
+		[PchSerialIoIndexI2C0] = PchSerialIoPci,
+		[PchSerialIoIndexI2C1] = PchSerialIoPci,
+		[PchSerialIoIndexI2C2] = PchSerialIoPci,
+		[PchSerialIoIndexI2C3] = PchSerialIoPci,
+		[PchSerialIoIndexI2C4] = PchSerialIoDisabled,
+		[PchSerialIoIndexI2C5] = PchSerialIoPci,
+	}"
+
+	register "serial_io_gspi_mode" = "{
+		[PchSerialIoIndexGSPI0] = PchSerialIoPci,
+		[PchSerialIoIndexGSPI1] = PchSerialIoPci,
+		[PchSerialIoIndexGSPI2] = PchSerialIoDisabled,
+		[PchSerialIoIndexGSPI3] = PchSerialIoDisabled,
+	}"
+
+	register "serial_io_gspi_cs_mode" = "{
+		[PchSerialIoIndexGSPI0] = 0,
+		[PchSerialIoIndexGSPI1] = 1,
+		[PchSerialIoIndexGSPI2] = 0,
+		[PchSerialIoIndexGSPI3] = 0,
+	}"
+
+	register "serial_io_gspi_cs_state" = "{
+		[PchSerialIoIndexGSPI0] = 0,
+		[PchSerialIoIndexGSPI1] = 0,
+		[PchSerialIoIndexGSPI2] = 0,
+		[PchSerialIoIndexGSPI3] = 0,
+	}"
+
+	register "serial_io_uart_mode" = "{
+		[PchSerialIoIndexUART0] = PchSerialIoSkipInit,
+		[PchSerialIoIndexUART1] = PchSerialIoDisabled,
+		[PchSerialIoIndexUART2] = PchSerialIoDisabled,
+	}"
+
+	# HD Audio
+	register "pch_hda_dsp_enable" = "1"
+	register "pch_hda_idisp_link_tmode" = "HDA_TMODE_8T"
+	register "pch_hda_idisp_link_frequency" = "HDA_LINKFREQ_96MHZ"
+	register "pch_hda_idisp_codec_enable" = "1"
+
+	register "cnvi_bt_audio_offload" = "true"
+
+	# Intel Common SoC Config
+	register "common_soc_config" = "{
+		.gspi[1] = {
+			.speed_mhz = 1,
+			.early_init = 1,
+		},
+		.i2c[0] = {
+			.speed = I2C_SPEED_FAST,
+		},
+		.i2c[1] = {
+			.speed = I2C_SPEED_FAST,
+		},
+		.i2c[2] = {
+			.speed = I2C_SPEED_FAST,
+		},
+		.i2c[3] = {
+			.speed = I2C_SPEED_FAST,
+		},
+		.i2c[5] = {
+			.speed = I2C_SPEED_FAST,
+		},
+	}"
+
+	device domain 0 on
+		device ref pcie5_0 on end
+		device ref igpu on end
+		device ref dtt on
+			chip drivers/intel/dptf
+
+				## sensor information
+				register "options.tsr[0].desc" = ""Ambient""
+				register "options.tsr[1].desc" = ""Battery""
+				register "options.tsr[2].desc" = ""DDR""
+				register "options.tsr[3].desc" = ""Skin""
+
+				## Active Policy
+				# TODO: below values are initial reference values only
+				register "policies.active" = "{
+					[0] = {
+							.target = DPTF_CPU,
+							.thresholds = {
+								TEMP_PCT(95, 90),
+								TEMP_PCT(90, 80),
+							}
+						},
+					[1] = {
+							.target = DPTF_TEMP_SENSOR_0,
+							.thresholds = {
+								TEMP_PCT(80, 90),
+								TEMP_PCT(70, 80),
+							}
+						}
+				}"
+
+				## Passive Policy
+				# TODO: below values are initial reference values only
+				register "policies.passive" = "{
+					[0] = DPTF_PASSIVE(CPU,		CPU,	       95, 10000),
+					[1] = DPTF_PASSIVE(CPU,		TEMP_SENSOR_0, 85, 50000),
+					[2] = DPTF_PASSIVE(CHARGER,	TEMP_SENSOR_1, 85, 50000),
+					[3] = DPTF_PASSIVE(CPU,		TEMP_SENSOR_2, 85, 50000),
+					[4] = DPTF_PASSIVE(CPU,		TEMP_SENSOR_3, 85, 50000),
+				}"
+
+				## Critical Policy
+				# TODO: below values are initial reference values only
+				register "policies.critical" = "{
+					[0] = DPTF_CRITICAL(CPU,	  105, SHUTDOWN),
+					[1] = DPTF_CRITICAL(TEMP_SENSOR_0, 95, SHUTDOWN),
+					[2] = DPTF_CRITICAL(TEMP_SENSOR_1, 95, SHUTDOWN),
+					[3] = DPTF_CRITICAL(TEMP_SENSOR_2, 95, SHUTDOWN),
+					[4] = DPTF_CRITICAL(TEMP_SENSOR_3, 95, SHUTDOWN),
+				}"
+
+				## Power Limits Control
+				register "controls.power_limits" = "{
+					.pl1 = {
+							.min_power = 35000,
+							.max_power = 45000,
+							.time_window_min = 28 * MSECS_PER_SEC,
+							.time_window_max = 32 * MSECS_PER_SEC,
+							.granularity = 200,
+					},
+					.pl2 = {
+							.min_power = 56000,
+							.max_power = 56000,
+							.time_window_min = 28 * MSECS_PER_SEC,
+							.time_window_max = 32 * MSECS_PER_SEC,
+							.granularity = 1000,
+					}
+				}"
+
+				## Charger Performance Control (Control, mA)
+				register "controls.charger_perf" = "{
+					[0] = { 255, 3000 },
+					[1] = {  24, 1500 },
+					[2] = {  16, 1000 },
+					[3] = {   8,  500 }
+				}"
+
+				## Fan Performance Control (Percent, Speed, Noise, Power)
+				register "controls.fan_perf" = "{
+					[0] = {  90, 6700, 220, 2200, },
+					[1] = {  80, 5800, 180, 1800, },
+					[2] = {  70, 5000, 145, 1450, },
+					[3] = {  60, 4900, 115, 1150, },
+					[4] = {  50, 3838,  90,  900, },
+					[5] = {  40, 2904,  55,  550, },
+					[6] = {  30, 2337,  30,  300, },
+					[7] = {  20, 1608,  15,  150, },
+					[8] = {  10,  800,  10,  100, },
+					[9] = {   0,    0,   0,   50, }
+				}"
+
+				## Fan options
+				register "options.fan.fine_grained_control" = "true"
+				register "options.fan.step_size" = "2"
+
+				device generic 0 alias dptf_policy on end
+			end
+		end
+		device ref ipu on
+			chip drivers/intel/mipi_camera
+				register "acpi_uid" = "0x50000"
+				register "acpi_name" = ""IPU0""
+				register "device_type" = "INTEL_ACPI_CAMERA_CIO2"
+
+				register "cio2_num_ports" = "2"
+				register "cio2_lanes_used" = "{2,2}"
+				register "cio2_lane_endpoint[0]" = ""^I2C5.CAM1""
+				register "cio2_lane_endpoint[1]" = ""^I2C1.CAM0""
+				register "cio2_prt[0]" = "2"
+				register "cio2_prt[1]" = "1"
+				device generic 0 on end
+			end
+		end
+		device ref pcie4_0 on end
+		device ref pcie4_1 on end
+		device ref tbt_pcie_rp0 on end
+		device ref tbt_pcie_rp1 on end
+		device ref tbt_pcie_rp2 on end
+		device ref tbt_pcie_rp3 on end
+		device ref crashlog off end
+		device ref tcss_xhci on end
+		device ref tcss_dma0 on end
+		device ref tcss_dma1 on end
+		device ref xhci on
+			chip drivers/usb/acpi
+				register "desc" = ""Root Hub""
+				register "type" = "UPC_TYPE_HUB"
+				device ref xhci_root_hub on
+					chip drivers/usb/acpi
+						register "desc" = ""Bluetooth""
+						register "type" = "UPC_TYPE_INTERNAL"
+						device ref usb2_port10 on end
+					end
+				end
+			end
+		end
+		device ref cnvi_wifi on
+			chip drivers/wifi/generic
+				register "wake" = "GPE0_PME_B0"
+				device generic 0 on end
+			end
+		end
+		device ref i2c0 on end
+		device ref i2c1 on
+			chip drivers/intel/mipi_camera
+				register "acpi_hid" = ""OVTI5675""
+				register "acpi_uid" = "0"
+				register "acpi_name" = ""CAM0""
+				register "chip_name" = ""Ov 5675 Camera""
+				register "device_type" = "INTEL_ACPI_CAMERA_SENSOR"
+
+				register "ssdb.lanes_used" = "2"
+				register "ssdb.vcm_type" = "0x0C"
+				register "vcm_name" = ""VCM0""
+				register "num_freq_entries" = "1"
+				register "link_freq[0]" = "450000000"
+				register "remote_name" = ""IPU0""
+
+				register "has_power_resource" = "true"
+				#Controls
+				register "clk_panel.clks[0].clknum" = "0" #IMGCLKOUT_0
+				register "clk_panel.clks[0].freq" = "1" #19.2 Mhz
+				register "gpio_panel.gpio[0].gpio_num" = "GPP_B23" #power_enable
+				register "gpio_panel.gpio[1].gpio_num" = "GPP_R5" #reset
+
+				#_ON
+				register "on_seq.ops_cnt" = "4"
+				register "on_seq.ops[0]" = "SEQ_OPS_CLK_ENABLE(0, 0)"
+				register "on_seq.ops[1]" = "SEQ_OPS_GPIO_ENABLE(0, 2)"
+				register "on_seq.ops[2]" = "SEQ_OPS_GPIO_DISABLE(1, 1)"
+				register "on_seq.ops[3]" = "SEQ_OPS_GPIO_ENABLE(1, 1)"
+
+				#_OFF
+				register "off_seq.ops_cnt" = "3"
+				register "off_seq.ops[0]" = "SEQ_OPS_CLK_DISABLE(0, 0)"
+				register "off_seq.ops[1]" = "SEQ_OPS_GPIO_DISABLE(1, 0)"
+				register "off_seq.ops[2]" = "SEQ_OPS_GPIO_DISABLE(0, 0)"
+
+				device i2c 36 on end
+			end
+			chip drivers/intel/mipi_camera
+				register "acpi_uid" = "3"
+				register "acpi_name" = ""VCM0""
+				register "chip_name" = ""DW AF VCM""
+				register "device_type" = "INTEL_ACPI_CAMERA_VCM"
+
+				register "pr0" = ""\\_SB.PCI0.I2C1.CAM0.PRIC""
+				register "vcm_compat" = ""dongwoon,dw9714""
+
+				device i2c 0C on end
+			end
+		end
+		device ref i2c2 on end
+		device ref i2c3 on end
+		device ref heci1 on end
+		device ref sata on end
+		device ref i2c5 on
+			chip drivers/intel/mipi_camera
+				register "acpi_hid" = ""OVTI5675""
+				register "acpi_uid" = "0"
+				register "acpi_name" = ""CAM1""
+				register "chip_name" = ""Ov 5675 Camera""
+				register "device_type" = "INTEL_ACPI_CAMERA_SENSOR"
+
+				register "ssdb.lanes_used" = "2"
+				register "num_freq_entries" = "1"
+				register "link_freq[0]" = "450000000"
+				register "remote_name" = ""IPU0""
+
+				register "has_power_resource" = "true"
+				#Controls
+				register "clk_panel.clks[0].clknum" = "1" #IMGCLKOUT_1
+				register "clk_panel.clks[0].freq" = "1" #19.2 Mhz
+				register "gpio_panel.gpio[0].gpio_num" = "GPP_E16" #power_enable
+				register "gpio_panel.gpio[1].gpio_num" = "GPP_E15" #reset
+
+				#_ON
+				register "on_seq.ops_cnt" = "4"
+				register "on_seq.ops[0]" = "SEQ_OPS_CLK_ENABLE(0, 0)"
+				register "on_seq.ops[1]" = "SEQ_OPS_GPIO_ENABLE(0, 2)"
+				register "on_seq.ops[2]" = "SEQ_OPS_GPIO_DISABLE(1, 1)"
+				register "on_seq.ops[3]" = "SEQ_OPS_GPIO_ENABLE(1, 1)"
+
+				#_OFF
+				register "off_seq.ops_cnt" = "3"
+				register "off_seq.ops[0]" = "SEQ_OPS_CLK_DISABLE(0, 0)"
+				register "off_seq.ops[1]" = "SEQ_OPS_GPIO_DISABLE(1, 0)"
+				register "off_seq.ops[2]" = "SEQ_OPS_GPIO_DISABLE(0, 0)"
+
+				device i2c 36 on end
+			end
+		end
+		device ref pcie_rp5 on end
+		device ref pcie_rp6 on end
+		device ref pcie_rp8 on end
+		device ref pcie_rp9 on end
+		device ref pcie_rp11 on end
+		device ref uart0 on end
+		device ref gspi0 on end
+		device ref p2sb on end
+		device ref gspi1 on
+			chip drivers/spi/acpi
+				register "hid" = "ACPI_DT_NAMESPACE_HID"
+				register "compat_string" = ""google,cr50""
+				register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_E3_IRQ)"
+				device spi 0 on end
+			end
+		end
+		device ref hda on
+			chip drivers/intel/soundwire
+				device generic 0 on
+					chip drivers/soundwire/alc711
+						# SoundWire Link 0 ID 1
+						register "desc" = ""Headset Codec""
+						register "alc711_address.version" = "SOUNDWIRE_VERSION_1_1"
+						register "alc711_address.class" = "MIPI_CLASS_NONE"
+						register "alc711_address.part_id" = "MIPI_DEV_ID_REALTEK_ALC711"
+						device generic 0.1 on end
+					end
+				end
+			end
+		end
+		device ref smbus on end
+	end
+end
diff --git a/src/mainboard/siemens/mc_rpl/devicetree_m.cb b/src/mainboard/siemens/mc_rpl/devicetree_m.cb
new file mode 100644
index 0000000000..1ee0f324dc
--- /dev/null
+++ b/src/mainboard/siemens/mc_rpl/devicetree_m.cb
@@ -0,0 +1,406 @@
+fw_config
+	field AUDIO 8 10
+		option NONE 0
+		option ADL_MAX98373_ALC5682I_I2S 1
+	end
+end
+chip soc/intel/alderlake
+
+	# GPE configuration
+	# Note that GPE events called out in ASL code rely on this
+	# route. i.e. If this route changes then the affected GPE
+	# offset bits also need to be changed.
+	register "pmc_gpe0_dw0" = "GPP_B"
+	register "pmc_gpe0_dw1" = "GPP_D"
+	register "pmc_gpe0_dw2" = "GPP_E"
+
+	# FSP configuration
+	register "usb2_ports[0]" = "USB2_PORT_MID(OC1)"	# Type-C port 0
+	register "usb2_ports[1]" = "USB2_PORT_MID(OC1)"	# Type-C port 1
+	register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # M.2 WLAN
+	register "usb2_ports[3]" = "USB2_PORT_MID(OC_SKIP)" # M.2 WWAN
+	register "usb2_ports[4]" = "USB2_PORT_MID(OC2)"	# Type-A port 1
+	register "usb2_ports[5]" = "USB2_PORT_MID(OC2)"	# Type-A port 2
+	register "usb2_ports[6]" = "USB2_PORT_MID(OC0)"	# USB3/2 Type A port1
+	register "usb2_ports[7]" = "USB2_PORT_MID(OC0)"	# USB3/2 Type A port2
+	register "usb2_ports[8]" = "USB2_PORT_MID(OC3)"	# USB3/2 Type A port3
+	register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth
+
+	register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC2)" # Type-A port 1
+	register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC2)" # Type-A port 2
+	register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # M.2 WWAN
+	register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # M.2 WLAN
+
+	# Sagv Configuration
+	register "sagv" = "SaGv_Enabled"
+
+	# Enable CNVi Bluetooth
+	register "cnvi_bt_core" = "true"
+
+	# EC host command ranges are in 0x800-0x8ff & 0x200-0x20f
+	register "gen1_dec" = "0x00fc0801"
+	register "gen2_dec" = "0x000c0201"
+	# EC memory map range is 0x900-0x9ff
+	register "gen3_dec" = "0x00fc0901"
+
+	#Enable PCH PCIE RP 4 using CLK 5
+	register "pch_pcie_rp[PCH_RP(4)]" = "{
+		.clk_src = 5,
+		.clk_req = 5,
+		.flags = PCIE_RP_CLK_REQ_DETECT | PCIE_RP_LTR,
+		.PcieRpL1Substates = L1_SS_L1_2,
+	}"
+
+	# Enable PCH PCIE RP 5 using CLK 2
+	register "pch_pcie_rp[PCH_RP(5)]" = "{
+		.clk_src = 2,
+		.clk_req = 2,
+		.flags = PCIE_RP_CLK_REQ_DETECT | PCIE_RP_LTR,
+		.PcieRpL1Substates = L1_SS_L1_2,
+	}"
+
+	# Enable PCH PCIE RP 9 using CLK 3
+	register "pch_pcie_rp[PCH_RP(9)]" = "{
+		.clk_src = 3,
+		.clk_req = 3,
+		.flags = PCIE_RP_CLK_REQ_DETECT | PCIE_RP_LTR,
+		.PcieRpL1Substates = L1_SS_L1_2,
+	}"
+
+	#Enable PCH PCIE RP 10 using CLK 1
+	register "pch_pcie_rp[PCH_RP(10)]" = "{
+		.clk_src = 1,
+		.clk_req = 1,
+		.flags = PCIE_RP_CLK_REQ_DETECT | PCIE_RP_LTR,
+		.PcieRpL1Substates = L1_SS_L1_2,
+	}"
+
+	# Hybrid storage mode
+	register "hybrid_storage_mode" = "true"
+
+	# Enable CPU PCIE RP 1 using CLK 0
+	register "cpu_pcie_rp[CPU_RP(1)]" = "{
+		.clk_req = 0,
+		.clk_src = 0,
+		.flags = PCIE_RP_LTR | PCIE_RP_AER,
+	}"
+
+	# Enable EDP in PortA
+	register "ddi_portA_config" = "1"
+	# Enable HDMI in Port B
+	register "ddi_ports_config" = "{
+		[DDI_PORT_B] = DDI_ENABLE_HPD | DDI_ENABLE_DDC,
+	}"
+
+	# TCSS USB3
+	register "tcss_aux_ori" = "0"
+
+	register "s0ix_enable" = "true"
+
+	register "serial_io_i2c_mode" = "{
+		[PchSerialIoIndexI2C0] = PchSerialIoPci,
+		[PchSerialIoIndexI2C1] = PchSerialIoPci,
+		[PchSerialIoIndexI2C2] = PchSerialIoDisabled,
+		[PchSerialIoIndexI2C3] = PchSerialIoDisabled,
+		[PchSerialIoIndexI2C4] = PchSerialIoDisabled,
+		[PchSerialIoIndexI2C5] = PchSerialIoPci,
+	}"
+
+	register "serial_io_gspi_mode" = "{
+		[PchSerialIoIndexGSPI0] = PchSerialIoPci,
+		[PchSerialIoIndexGSPI1] = PchSerialIoPci,
+		[PchSerialIoIndexGSPI2] = PchSerialIoDisabled,
+		[PchSerialIoIndexGSPI3] = PchSerialIoDisabled,
+	}"
+
+	register "serial_io_gspi_cs_mode" = "{
+		[PchSerialIoIndexGSPI0] = 0,
+		[PchSerialIoIndexGSPI1] = 1,
+		[PchSerialIoIndexGSPI2] = 0,
+		[PchSerialIoIndexGSPI3] = 0,
+	}"
+
+	register "serial_io_gspi_cs_state" = "{
+		[PchSerialIoIndexGSPI0] = 0,
+		[PchSerialIoIndexGSPI1] = 0,
+		[PchSerialIoIndexGSPI2] = 0,
+		[PchSerialIoIndexGSPI3] = 0,
+	}"
+
+	register "serial_io_uart_mode" = "{
+		[PchSerialIoIndexUART0] = PchSerialIoSkipInit,
+		[PchSerialIoIndexUART1] = PchSerialIoDisabled,
+		[PchSerialIoIndexUART2] = PchSerialIoDisabled,
+	}"
+
+	# HD Audio
+	register "pch_hda_dsp_enable" = "1"
+	register "pch_hda_idisp_link_tmode" = "HDA_TMODE_8T"
+	register "pch_hda_idisp_link_frequency" = "HDA_LINKFREQ_96MHZ"
+	register "pch_hda_idisp_codec_enable" = "1"
+
+	# Intel Common SoC Config
+	register "common_soc_config" = "{
+		.gspi[1] = {
+			.speed_mhz = 1,
+			.early_init = 1,
+		},
+		.i2c[0] = {
+			.speed = I2C_SPEED_FAST,
+		},
+		.i2c[1] = {
+			.speed = I2C_SPEED_FAST,
+		},
+		.i2c[2] = {
+			.speed = I2C_SPEED_FAST,
+		},
+		.i2c[3] = {
+			.speed = I2C_SPEED_FAST,
+		},
+		.i2c[5] = {
+			.speed = I2C_SPEED_FAST,
+		},
+	}"
+
+	device domain 0 on
+		device ref pcie5_0 on end
+		device ref igpu on end
+		device ref dtt on end
+		device ref ipu on
+			chip drivers/intel/mipi_camera
+				register "acpi_uid" = "0x50000"
+				register "acpi_name" = ""IPU0""
+				register "device_type" = "INTEL_ACPI_CAMERA_CIO2"
+
+				register "cio2_num_ports" = "2"
+				register "cio2_lanes_used" = "{2,2}"
+				register "cio2_lane_endpoint[0]" = ""^I2C5.CAM1""
+				register "cio2_lane_endpoint[1]" = ""^I2C1.CAM0""
+				register "cio2_prt[0]" = "2"
+				register "cio2_prt[1]" = "1"
+				device generic 0 on end
+			end
+		end
+		device ref pcie4_0 on end
+		device ref pcie4_1 on end
+		device ref tbt_pcie_rp0 on end
+		device ref tbt_pcie_rp1 on end
+		device ref tcss_xhci on
+			chip drivers/usb/acpi
+				register "type" = "UPC_TYPE_HUB"
+				device ref tcss_root_hub on
+					chip drivers/usb/acpi
+						register "desc" = ""TypeC Port 1""
+						device ref tcss_usb3_port1 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""TypeC Port 2""
+						device ref tcss_usb3_port2 on end
+					end
+				end
+			end
+		end
+		device ref tcss_dma0 on end
+		device ref xhci on
+			chip drivers/usb/acpi
+				register "desc" = ""Root Hub""
+				register "type" = "UPC_TYPE_HUB"
+				device ref xhci_root_hub on
+					chip drivers/usb/acpi
+						register "desc" = ""Bluetooth""
+						register "type" = "UPC_TYPE_INTERNAL"
+						device ref usb2_port10 on end
+					end
+				end
+			end
+		end
+		device ref cnvi_wifi on
+			chip drivers/wifi/generic
+				register "wake" = "GPE0_PME_B0"
+				device generic 0 on end
+			end
+		end
+		device ref i2c0 on
+			chip drivers/i2c/generic
+				register "hid" = ""10EC5682""
+				register "name" = ""RT58""
+				register "desc" = ""Headset Codec""
+				register "irq" = "ACPI_IRQ_EDGE_HIGH(GPP_H3_IRQ)"
+				# Set the jd_src to RT5668_JD1 for jack detection
+				register "property_count" = "1"
+				register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER"
+				register "property_list[0].name" = ""realtek,jd-src""
+				register "property_list[0].integer" = "1"
+				device i2c 1a on
+					probe AUDIO ADL_MAX98373_ALC5682I_I2S
+				end
+			end
+			chip drivers/i2c/max98373
+				register "vmon_slot_no" = "0"
+				register "imon_slot_no" = "1"
+				register "uid" = "0"
+				register "desc" = ""Right Speaker Amp""
+				register "name" = ""MAXR""
+				device i2c 31 on
+					probe AUDIO ADL_MAX98373_ALC5682I_I2S
+				end
+			end
+			chip drivers/i2c/max98373
+				register "vmon_slot_no" = "2"
+				register "imon_slot_no" = "3"
+				register "uid" = "1"
+				register "desc" = ""Left Speaker Amp""
+				register "name" = ""MAXL""
+				device i2c 32 on
+					probe AUDIO ADL_MAX98373_ALC5682I_I2S
+				end
+			end
+			chip drivers/i2c/hid
+				register "generic.hid" = ""WACOM PWB-D893""
+				register "generic.desc" = ""WACOM Touchscreen""
+				register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_F18_IRQ)"
+				register "generic.probed" = "1"
+				register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_F17)"
+				register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_F7)"
+				register "generic.enable_delay_ms" = "1"
+				register "generic.reset_delay_ms" = "300"
+				register "generic.has_power_resource" = "1"
+				register "hid_desc_reg_offset" = "0x01"
+				device i2c 0a on end
+			end
+			chip drivers/i2c/hid
+				register "generic.hid" = ""ELAN0000""
+				register "generic.desc" = ""ELAN Touchpad""
+				register "generic.irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_D11_IRQ)"
+				register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_H1)"
+				register "generic.wake" = "GPE0_DW1_11"
+				register "generic.detect" = "1"
+				register "generic.has_power_resource" = "1"
+				device i2c 15 on end
+			end
+		end
+		device ref i2c1 on
+			chip drivers/intel/mipi_camera
+				register "acpi_hid" = ""OVTI5675""
+				register "acpi_uid" = "0"
+				register "acpi_name" = ""CAM0""
+				register "chip_name" = ""Ov 5675 Camera""
+				register "device_type" = "INTEL_ACPI_CAMERA_SENSOR"
+
+				register "ssdb.lanes_used" = "2"
+				register "ssdb.vcm_type" = "0x0C"
+				register "vcm_name" = ""VCM0""
+				register "num_freq_entries" = "1"
+				register "link_freq[0]" = "450000000"
+				register "remote_name" = ""IPU0""
+
+				register "has_power_resource" = "true"
+				#Controls
+				register "clk_panel.clks[0].clknum" = "0" #IMGCLKOUT_0
+				register "clk_panel.clks[0].freq" = "1" #19.2 Mhz
+				register "gpio_panel.gpio[0].gpio_num" = "GPP_B23" #power_enable
+				register "gpio_panel.gpio[1].gpio_num" = "GPP_R5" #reset
+
+				#_ON
+				register "on_seq.ops_cnt" = "4"
+				register "on_seq.ops[0]" = "SEQ_OPS_CLK_ENABLE(0, 0)"
+				register "on_seq.ops[1]" = "SEQ_OPS_GPIO_ENABLE(0, 2)"
+				register "on_seq.ops[2]" = "SEQ_OPS_GPIO_DISABLE(1, 1)"
+				register "on_seq.ops[3]" = "SEQ_OPS_GPIO_ENABLE(1, 1)"
+
+				#_OFF
+				register "off_seq.ops_cnt" = "3"
+				register "off_seq.ops[0]" = "SEQ_OPS_CLK_DISABLE(0, 0)"
+				register "off_seq.ops[1]" = "SEQ_OPS_GPIO_DISABLE(1, 0)"
+				register "off_seq.ops[2]" = "SEQ_OPS_GPIO_DISABLE(0, 0)"
+
+				device i2c 36 on end
+			end
+			chip drivers/intel/mipi_camera
+				register "acpi_uid" = "3"
+				register "acpi_name" = ""VCM0""
+				register "chip_name" = ""DW AF VCM""
+				register "device_type" = "INTEL_ACPI_CAMERA_VCM"
+
+				register "pr0" = ""\\_SB.PCI0.I2C1.CAM0.PRIC""
+				register "vcm_compat" = ""dongwoon,dw9714""
+
+				device i2c 0C on end
+			end
+		end
+		device ref i2c2 on end
+		device ref i2c3 on end
+		device ref heci1 on end
+		device ref sata on end
+		device ref i2c5 on
+			chip drivers/intel/mipi_camera
+				register "acpi_hid" = ""OVTI5675""
+				register "acpi_uid" = "0"
+				register "acpi_name" = ""CAM1""
+				register "chip_name" = ""Ov 5675 Camera""
+				register "device_type" = "INTEL_ACPI_CAMERA_SENSOR"
+
+				register "ssdb.lanes_used" = "2"
+				register "num_freq_entries" = "1"
+				register "link_freq[0]" = "450000000"
+				register "remote_name" = ""IPU0""
+
+				register "has_power_resource" = "true"
+				#Controls
+				register "clk_panel.clks[0].clknum" = "1" #IMGCLKOUT_1
+				register "clk_panel.clks[0].freq" = "1" #19.2 Mhz
+				register "gpio_panel.gpio[0].gpio_num" = "GPP_E16" #power_enable
+				register "gpio_panel.gpio[1].gpio_num" = "GPP_E15" #reset
+
+				#_ON
+				register "on_seq.ops_cnt" = "4"
+				register "on_seq.ops[0]" = "SEQ_OPS_CLK_ENABLE(0, 0)"
+				register "on_seq.ops[1]" = "SEQ_OPS_GPIO_ENABLE(0, 2)"
+				register "on_seq.ops[2]" = "SEQ_OPS_GPIO_DISABLE(1, 1)"
+				register "on_seq.ops[3]" = "SEQ_OPS_GPIO_ENABLE(1, 1)"
+
+				#_OFF
+				register "off_seq.ops_cnt" = "3"
+				register "off_seq.ops[0]" = "SEQ_OPS_CLK_DISABLE(0, 0)"
+				register "off_seq.ops[1]" = "SEQ_OPS_GPIO_DISABLE(1, 0)"
+				register "off_seq.ops[2]" = "SEQ_OPS_GPIO_DISABLE(0, 0)"
+
+				device i2c 36 on end
+			end
+		end
+		device ref pcie_rp1 on end
+		device ref pcie_rp3 on end # W/A to FSP issue
+		device ref pcie_rp4 on end # W/A to FSP issue
+		device ref pcie_rp5 on end
+		device ref pcie_rp6 on end
+		device ref pcie_rp8 on end
+		device ref pcie_rp9 on end
+		device ref pcie_rp10 on end
+		device ref uart0 on end
+		device ref gspi0 on end
+		device ref p2sb on end
+		device pci 1e.3 on
+			chip drivers/spi/acpi
+				register "hid" = "ACPI_DT_NAMESPACE_HID"
+				register "compat_string" = ""google,cr50""
+				register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_E3_IRQ)"
+				device spi 0 on end
+			end
+		end # GSPI1
+		device ref hda on
+			chip drivers/intel/soundwire
+				device generic 0 on
+					chip drivers/soundwire/alc711
+						# SoundWire Link 0 ID 1
+						register "desc" = ""Headset Codec""
+						register "alc711_address.version" = "SOUNDWIRE_VERSION_1_1"
+						register "alc711_address.class" = "MIPI_CLASS_NONE"
+						register "alc711_address.part_id" = "MIPI_DEV_ID_REALTEK_ALC711"
+						device generic 0.1 on end
+					end
+				end
+			end
+		end
+		device ref smbus on end
+	end
+end
diff --git a/src/mainboard/siemens/mc_rpl/devicetree_n.cb b/src/mainboard/siemens/mc_rpl/devicetree_n.cb
new file mode 100644
index 0000000000..1eff9459d3
--- /dev/null
+++ b/src/mainboard/siemens/mc_rpl/devicetree_n.cb
@@ -0,0 +1,403 @@
+chip soc/intel/alderlake
+
+	# GPE configuration
+	# Note that GPE events called out in ASL code rely on this
+	# route. i.e. If this route changes then the affected GPE
+	# offset bits also need to be changed.
+	register "pmc_gpe0_dw0" = "GPP_B"
+	register "pmc_gpe0_dw1" = "GPP_D"
+	register "pmc_gpe0_dw2" = "GPP_E"
+
+	# FSP configuration
+
+	# Enable CNVi BT
+	register "cnvi_bt_core" = "true"
+
+	# Sagv Configuration
+	register "sagv" = "SaGv_Enabled"
+
+	# Enable DPTF
+	register "dptf_enable" = "true"
+
+	# eMMC HS400
+	register "emmc_enable_hs400_mode" = "true"
+
+	register "usb2_ports[0]" = "USB2_PORT_MID(OC3)"		# Type-C Port1
+	register "usb2_ports[1]" = "USB2_PORT_MID(OC3)"		# Type-C Port2
+	register "usb2_ports[2]" = "USB2_PORT_MID(OC3)"		# FPS connector
+	register "usb2_ports[3]" = "USB2_PORT_MID(OC_SKIP)"	# M.2 WWAN
+	register "usb2_ports[4]" = "USB2_PORT_MID(OC3)"		# USB3/2 Type A port1
+	register "usb2_ports[5]" = "USB2_PORT_MID(OC1)"		# USB3/2 Type A port2
+	register "usb2_ports[6]" = "USB2_PORT_MID(OC1)"		# USB3/2 Type A port3
+	register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)"	# Type A/ M.2 WLAN
+	register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)"	# Bluetooth
+
+	register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC3)"	# USB3/2 Type A port1
+	register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC1)"	# USB3/2 Type A port2
+	register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC1)"	# USB3/2 Type A port3
+	register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)"	# M.2 WWAN
+
+	# EC host command ranges are in 0x800-0x8ff & 0x200-0x20f
+	register "gen1_dec" = "0x00fc0801"
+	register "gen2_dec" = "0x000c0201"
+	# EC memory map range is 0x900-0x9ff
+	register "gen3_dec" = "0x00fc0901"
+
+	# Enable PCH PCIE RP 7 using CLK 3
+	register "pch_pcie_rp[PCH_RP(7)]" = "{
+		.clk_src = 3,
+		.clk_req = 3,
+		.flags = PCIE_RP_CLK_REQ_DETECT,
+	}"
+
+	# Enable PCH PCIE RP 9 using CLK 0
+	register "pch_pcie_rp[PCH_RP(9)]" = "{
+		.clk_src = 0,
+		.clk_req = 0,
+		.flags = PCIE_RP_CLK_REQ_DETECT,
+	}"
+
+	register "sata_salp_support" = "0"
+
+	# Enable EDP in PortA
+	register "ddi_portA_config" = "1"
+	# Enable HDMI in Port B
+	register "ddi_ports_config" = "{
+		[DDI_PORT_B] = DDI_ENABLE_HPD | DDI_ENABLE_DDC,
+	}"
+
+	# TCSS USB3
+	register "tcss_aux_ori" = "4"
+	register "typec_aux_bias_pads[1]" = "{.pad_auxp_dc = GPP_E20, .pad_auxn_dc = GPP_E21}"
+
+	register "s0ix_enable" = "true"
+
+	register "serial_io_i2c_mode" = "{
+		[PchSerialIoIndexI2C0] = PchSerialIoPci,
+		[PchSerialIoIndexI2C1] = PchSerialIoPci,
+		[PchSerialIoIndexI2C2] = PchSerialIoPci,
+		[PchSerialIoIndexI2C3] = PchSerialIoPci,
+		[PchSerialIoIndexI2C4] = PchSerialIoDisabled,
+		[PchSerialIoIndexI2C5] = PchSerialIoPci,
+	}"
+
+	register "serial_io_gspi_mode" = "{
+		[PchSerialIoIndexGSPI0] = PchSerialIoPci,
+		[PchSerialIoIndexGSPI1] = PchSerialIoDisabled,
+		[PchSerialIoIndexGSPI2] = PchSerialIoDisabled,
+		[PchSerialIoIndexGSPI3] = PchSerialIoDisabled,
+	}"
+
+	register "serial_io_gspi_cs_mode" = "{
+		[PchSerialIoIndexGSPI0] = 0,
+		[PchSerialIoIndexGSPI1] = 0,
+		[PchSerialIoIndexGSPI2] = 0,
+		[PchSerialIoIndexGSPI3] = 0,
+	}"
+
+	register "serial_io_gspi_cs_state" = "{
+		[PchSerialIoIndexGSPI0] = 0,
+		[PchSerialIoIndexGSPI1] = 0,
+		[PchSerialIoIndexGSPI2] = 0,
+		[PchSerialIoIndexGSPI3] = 0,
+	}"
+
+	register "serial_io_uart_mode" = "{
+		[PchSerialIoIndexUART0] = PchSerialIoSkipInit,
+		[PchSerialIoIndexUART1] = PchSerialIoDisabled,
+		[PchSerialIoIndexUART2] = PchSerialIoDisabled,
+	}"
+
+	# HD Audio
+	register "pch_hda_dsp_enable" = "1"
+	register "pch_hda_idisp_link_tmode" = "HDA_TMODE_8T"
+	register "pch_hda_idisp_link_frequency" = "HDA_LINKFREQ_96MHZ"
+	register "pch_hda_idisp_codec_enable" = "1"
+
+	register "cnvi_bt_audio_offload" = "true"
+
+	# Intel Common SoC Config
+	register "common_soc_config" = "{
+		.i2c[0] = {
+			.speed = I2C_SPEED_FAST,
+		},
+		.i2c[1] = {
+			.speed = I2C_SPEED_FAST,
+		},
+		.i2c[2] = {
+			.speed = I2C_SPEED_FAST,
+		},
+		.i2c[3] = {
+			.speed = I2C_SPEED_FAST,
+		},
+		.i2c[5] = {
+			.speed = I2C_SPEED_FAST,
+		},
+	}"
+
+	# Configure external V1P05/Vnn/VnnSx Rails
+	register "ext_fivr_settings" = "{
+		.configure_ext_fivr = 1,
+		.v1p05_enable_bitmap = FIVR_ENABLE_ALL_SX & ~FIVR_ENABLE_S0,
+		.vnn_enable_bitmap = FIVR_ENABLE_ALL_SX,
+		.vnn_sx_enable_bitmap = FIVR_ENABLE_ALL_SX,
+		.v1p05_supported_voltage_bitmap = FIVR_VOLTAGE_NORMAL,
+		.vnn_supported_voltage_bitmap = FIVR_VOLTAGE_MIN_ACTIVE,
+		.v1p05_voltage_mv = 1050,
+		.vnn_voltage_mv = 780,
+		.vnn_sx_voltage_mv = 1050,
+		.v1p05_icc_max_ma = 500,
+		.vnn_icc_max_ma = 500,
+	}"
+
+	device domain 0 on
+		device ref igpu on end
+		device ref dtt on
+			chip drivers/intel/dptf
+
+				## sensor information
+				register "options.tsr[0].desc" = ""Ambient""
+				register "options.tsr[1].desc" = ""Battery""
+				register "options.tsr[2].desc" = ""DDR""
+				register "options.tsr[3].desc" = ""Skin""
+				register "options.tsr[4].desc" = ""VR""
+
+				## Active Policy
+				# TODO: below values are initial reference values only
+				register "policies.active" = "{
+					[0] = {
+							.target = DPTF_CPU,
+							.thresholds = {
+								TEMP_PCT(95, 90),
+								TEMP_PCT(90, 80),
+							}
+						},
+					[1] = {
+							.target = DPTF_TEMP_SENSOR_0,
+							.thresholds = {
+								TEMP_PCT(80, 90),
+								TEMP_PCT(70, 80),
+							}
+						}
+				}"
+
+				## Passive Policy
+				# TODO: below values are initial reference values only
+				register "policies.passive" = "{
+					[0] = DPTF_PASSIVE(CPU,		CPU,	       95, 10000),
+					[1] = DPTF_PASSIVE(CPU,		TEMP_SENSOR_0, 85, 50000),
+					[2] = DPTF_PASSIVE(CHARGER,	TEMP_SENSOR_1, 85, 50000),
+					[3] = DPTF_PASSIVE(CPU,		TEMP_SENSOR_2, 85, 50000),
+					[4] = DPTF_PASSIVE(CPU,		TEMP_SENSOR_3, 85, 50000),
+					[5] = DPTF_PASSIVE(CPU,		TEMP_SENSOR_4, 85, 50000),
+				}"
+
+				## Critical Policy
+				# TODO: below values are initial reference values only
+				register "policies.critical" = "{
+					[0] = DPTF_CRITICAL(CPU,	  105, SHUTDOWN),
+					[1] = DPTF_CRITICAL(TEMP_SENSOR_0, 95, SHUTDOWN),
+					[2] = DPTF_CRITICAL(TEMP_SENSOR_1, 95, SHUTDOWN),
+					[3] = DPTF_CRITICAL(TEMP_SENSOR_2, 95, SHUTDOWN),
+					[4] = DPTF_CRITICAL(TEMP_SENSOR_3, 95, SHUTDOWN),
+					[5] = DPTF_CRITICAL(TEMP_SENSOR_4, 95, SHUTDOWN),
+				}"
+
+				## Power Limits Control
+				register "controls.power_limits" = "{
+					.pl1 = {
+							.min_power = 3000,
+							.max_power = 15000,
+							.time_window_min = 28 * MSECS_PER_SEC,
+							.time_window_max = 32 * MSECS_PER_SEC,
+							.granularity = 200,
+					},
+					.pl2 = {
+							.min_power = 25000,
+							.max_power = 35000,
+							.time_window_min = 28 * MSECS_PER_SEC,
+							.time_window_max = 32 * MSECS_PER_SEC,
+							.granularity = 1000,
+					}
+				}"
+
+				## Charger Performance Control (Control, mA)
+				register "controls.charger_perf" = "{
+					[0] = { 255, 3000 },
+					[1] = {  24, 1500 },
+					[2] = {  16, 1000 },
+					[3] = {   8,  500 }
+				}"
+
+				## Fan Performance Control (Percent, Speed, Noise, Power)
+				register "controls.fan_perf" = "{
+					[0] = {  90, 6700, 220, 2200, },
+					[1] = {  80, 5800, 180, 1800, },
+					[2] = {  70, 5000, 145, 1450, },
+					[3] = {  60, 4900, 115, 1150, },
+					[4] = {  50, 3838,  90,  900, },
+					[5] = {  40, 2904,  55,  550, },
+					[6] = {  30, 2337,  30,  300, },
+					[7] = {  20, 1608,  15,  150, },
+					[8] = {  10,  800,  10,  100, },
+					[9] = {   0,    0,   0,   50, }
+				}"
+
+				## Fan options
+				register "options.fan.fine_grained_control" = "true"
+				register "options.fan.step_size" = "2"
+
+				device generic 0 alias dptf_policy on end
+			end
+		end
+		device ref ipu on
+			chip drivers/intel/mipi_camera
+				register "acpi_uid" = "0x50000"
+				register "acpi_name" = ""IPU0""
+				register "device_type" = "INTEL_ACPI_CAMERA_CIO2"
+
+				register "cio2_num_ports" = "2"
+				register "cio2_lanes_used" = "{2,2}"
+				register "cio2_lane_endpoint[0]" = ""^I2C5.CAM1""
+				register "cio2_lane_endpoint[1]" = ""^I2C1.CAM0""
+				register "cio2_prt[0]" = "2"
+				register "cio2_prt[1]" = "1"
+				device generic 0 on end
+			end
+		end
+		device ref crashlog off end
+		device ref tcss_xhci on end
+		device ref xhci on
+			chip drivers/usb/acpi
+				register "desc" = ""Root Hub""
+				register "type" = "UPC_TYPE_HUB"
+				device ref xhci_root_hub on
+					chip drivers/usb/acpi
+						register "desc" = ""Bluetooth""
+						register "type" = "UPC_TYPE_INTERNAL"
+						device ref usb2_port10 on end
+					end
+				end
+			end
+		end
+		device ref cnvi_wifi on
+			chip drivers/wifi/generic
+				register "wake" = "GPE0_PME_B0"
+				device generic 0 on end
+			end
+		end
+		device ref i2c0 on end
+		device ref i2c1 on
+			chip drivers/intel/mipi_camera
+				register "acpi_hid" = ""OVTI5675""
+				register "acpi_uid" = "0"
+				register "acpi_name" = ""CAM0""
+				register "chip_name" = ""Ov 5675 Camera""
+				register "device_type" = "INTEL_ACPI_CAMERA_SENSOR"
+
+				register "ssdb.lanes_used" = "2"
+				register "ssdb.vcm_type" = "0x0C"
+				register "vcm_name" = ""VCM0""
+				register "num_freq_entries" = "1"
+				register "link_freq[0]" = "450000000"
+				register "remote_name" = ""IPU0""
+
+				register "has_power_resource" = "true"
+				#Controls
+				register "clk_panel.clks[0].clknum" = "0" #IMGCLKOUT_0
+				register "clk_panel.clks[0].freq" = "1" #19.2 Mhz
+				register "gpio_panel.gpio[0].gpio_num" = "GPP_B23" #power_enable
+				register "gpio_panel.gpio[1].gpio_num" = "GPP_R5" #reset
+
+				#_ON
+				register "on_seq.ops_cnt" = "4"
+				register "on_seq.ops[0]" = "SEQ_OPS_CLK_ENABLE(0, 0)"
+				register "on_seq.ops[1]" = "SEQ_OPS_GPIO_ENABLE(0, 2)"
+				register "on_seq.ops[2]" = "SEQ_OPS_GPIO_DISABLE(1, 1)"
+				register "on_seq.ops[3]" = "SEQ_OPS_GPIO_ENABLE(1, 1)"
+
+				#_OFF
+				register "off_seq.ops_cnt" = "3"
+				register "off_seq.ops[0]" = "SEQ_OPS_CLK_DISABLE(0, 0)"
+				register "off_seq.ops[1]" = "SEQ_OPS_GPIO_DISABLE(1, 0)"
+				register "off_seq.ops[2]" = "SEQ_OPS_GPIO_DISABLE(0, 0)"
+
+				device i2c 36 on end
+			end
+			chip drivers/intel/mipi_camera
+				register "acpi_uid" = "3"
+				register "acpi_name" = ""VCM0""
+				register "chip_name" = ""DW AF VCM""
+				register "device_type" = "INTEL_ACPI_CAMERA_VCM"
+
+				register "pr0" = ""\\_SB.PCI0.I2C1.CAM0.PRIC""
+				register "vcm_compat" = ""dongwoon,dw9714""
+
+				device i2c 0C on end
+			end
+		end
+		device ref i2c2 on end
+		device ref i2c3 on end
+		device ref heci1 on end
+		device ref sata off end
+		device ref i2c5 on
+			chip drivers/intel/mipi_camera
+				register "acpi_hid" = ""OVTI5675""
+				register "acpi_uid" = "0"
+				register "acpi_name" = ""CAM1""
+				register "chip_name" = ""Ov 5675 Camera""
+				register "device_type" = "INTEL_ACPI_CAMERA_SENSOR"
+
+				register "ssdb.lanes_used" = "2"
+				register "num_freq_entries" = "1"
+				register "link_freq[0]" = "450000000"
+				register "remote_name" = ""IPU0""
+
+				register "has_power_resource" = "true"
+				#Controls
+				register "clk_panel.clks[0].clknum" = "1" #IMGCLKOUT_1
+				register "clk_panel.clks[0].freq" = "1" #19.2 Mhz
+				register "gpio_panel.gpio[0].gpio_num" = "GPP_E16" #power_enable
+				register "gpio_panel.gpio[1].gpio_num" = "GPP_E15" #reset
+
+				#_ON
+				register "on_seq.ops_cnt" = "4"
+				register "on_seq.ops[0]" = "SEQ_OPS_CLK_ENABLE(0, 0)"
+				register "on_seq.ops[1]" = "SEQ_OPS_GPIO_ENABLE(0, 2)"
+				register "on_seq.ops[2]" = "SEQ_OPS_GPIO_DISABLE(1, 1)"
+				register "on_seq.ops[3]" = "SEQ_OPS_GPIO_ENABLE(1, 1)"
+
+				#_OFF
+				register "off_seq.ops_cnt" = "3"
+				register "off_seq.ops[0]" = "SEQ_OPS_CLK_DISABLE(0, 0)"
+				register "off_seq.ops[1]" = "SEQ_OPS_GPIO_DISABLE(1, 0)"
+				register "off_seq.ops[2]" = "SEQ_OPS_GPIO_DISABLE(0, 0)"
+
+				device i2c 36 on end
+			end
+		end
+		device ref pcie_rp7 on end
+		device ref pcie_rp9 on end
+		device ref uart0 on end
+		device ref gspi0 on end
+		device ref p2sb on end
+		device ref emmc on end
+		device ref ish on end
+		device ref ufs on end
+		device ref hda on
+			chip drivers/intel/soundwire
+				device generic 0 on
+					chip drivers/soundwire/alc711
+						# SoundWire Link 0 ID 1
+						register "desc" = ""Headset Codec""
+						register "alc711_address.version" = "SOUNDWIRE_VERSION_1_1"
+						register "alc711_address.class" = "MIPI_CLASS_NONE"
+						register "alc711_address.part_id" = "MIPI_DEV_ID_REALTEK_ALC711"
+						device generic 0.1 on end
+					end
+				end
+			end
+		end
+		device ref smbus on end
+	end
+end
diff --git a/src/mainboard/siemens/mc_rpl/dsdt.asl b/src/mainboard/siemens/mc_rpl/dsdt.asl
new file mode 100644
index 0000000000..f379610866
--- /dev/null
+++ b/src/mainboard/siemens/mc_rpl/dsdt.asl
@@ -0,0 +1,39 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <acpi/acpi.h>
+#include <baseboard/ec.h>
+#include <baseboard/gpio.h>
+
+DefinitionBlock(
+	"dsdt.aml",
+	"DSDT",
+	ACPI_DSDT_REV_2,
+	OEM_ID,
+	ACPI_TABLE_CREATOR,
+	0x20110725
+)
+{
+	#include <acpi/dsdt_top.asl>
+	#include <soc/intel/common/block/acpi/acpi/platform.asl>
+	#include <soc/intel/common/block/acpi/acpi/globalnvs.asl>
+	#include <cpu/intel/common/acpi/cpu.asl>
+
+	Device (\_SB.PCI0) {
+		#include <soc/intel/common/block/acpi/acpi/northbridge.asl>
+		#include <soc/intel/alderlake/acpi/southbridge.asl>
+		#include <soc/intel/alderlake/acpi/tcss.asl>
+	}
+
+#if CONFIG(EC_GOOGLE_CHROMEEC)
+	/* ChromeOS Embedded Controller */
+	Scope (\_SB.PCI0.LPCB)
+	{
+		/* ACPI code for EC SuperIO functions */
+		#include <ec/google/chromeec/acpi/superio.asl>
+		/* ACPI code for EC functions */
+		#include <ec/google/chromeec/acpi/ec.asl>
+	}
+#endif
+
+	#include <southbridge/intel/common/acpi/sleepstates.asl>
+}
diff --git a/src/mainboard/siemens/mc_rpl/early_gpio.c b/src/mainboard/siemens/mc_rpl/early_gpio.c
new file mode 100644
index 0000000000..c3b2e2a47c
--- /dev/null
+++ b/src/mainboard/siemens/mc_rpl/early_gpio.c
@@ -0,0 +1,148 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <baseboard/gpio.h>
+#include <baseboard/variants.h>
+#include <soc/gpio.h>
+
+/* Early pad configuration in bootblock */
+static const struct pad_config early_gpio_table[] = {
+	/* WWAN_RST# (updated in ramstage) */
+	PAD_CFG_GPO(GPP_F14, 0, DEEP),
+	/* WWAN_PERST_L (updated in ramstage) */
+	PAD_CFG_GPO(GPP_C5, 0, DEEP),
+	/* WWAN_FCPO_L (updated in romstage) */
+	PAD_CFG_GPO(GPP_F15, 0, DEEP),
+	/* WWAN_PWR_EN */
+	PAD_CFG_GPO(GPP_F21, 1, DEEP),
+	/* SMB_CLK */
+	PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1),
+	/* SMB_DATA */
+	PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1),
+
+	/* EC_IN_RW */
+	PAD_CFG_GPI(GPP_E7, NONE, DEEP),
+
+	/* x4 PCIE slot 1 RESET */
+	PAD_CFG_GPO(GPP_F10, 0, PLTRST),
+
+	/* Support external source clock via OEB6 and OEB7 */
+	/* SRCCLK_OEB6 for built-in LAN */
+	PAD_CFG_NF(GPP_E5, NONE, PLTRST, NF2),
+	/* SRCCLK_OEB7 for x4 slot */
+	PAD_CFG_NF(GPP_A7, NONE, PLTRST, NF1),
+
+	/* CPU PCIe VGPIO for RP0 */
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_0, NONE, PLTRST, NF1),
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_1, NONE, PLTRST, NF1),
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_3, NONE, PLTRST, NF1),
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_2, NONE, PLTRST, NF1),
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_4, NONE, PLTRST, NF1),
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_5, NONE, PLTRST, NF1),
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_6, NONE, PLTRST, NF1),
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_7, NONE, PLTRST, NF1),
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_8, NONE, PLTRST, NF1),
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_9, NONE, PLTRST, NF1),
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_10, NONE, PLTRST, NF1),
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_11, NONE, PLTRST, NF1),
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_12, NONE, PLTRST, NF1),
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_13, NONE, PLTRST, NF1),
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_14, NONE, PLTRST, NF1),
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_15, NONE, PLTRST, NF1),
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_64, NONE, PLTRST, NF1),
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_65, NONE, PLTRST, NF1),
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_66, NONE, PLTRST, NF1),
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_67, NONE, PLTRST, NF1),
+
+	/* CPU PCIe vGPIO for RP1 */
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_16, NONE, PLTRST, NF1),
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_17, NONE, PLTRST, NF1),
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_18, NONE, PLTRST, NF1),
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_19, NONE, PLTRST, NF1),
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_20, NONE, PLTRST, NF1),
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_21, NONE, PLTRST, NF1),
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_22, NONE, PLTRST, NF1),
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_23, NONE, PLTRST, NF1),
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_24, NONE, PLTRST, NF1),
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_25, NONE, PLTRST, NF1),
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_26, NONE, PLTRST, NF1),
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_27, NONE, PLTRST, NF1),
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_28, NONE, PLTRST, NF1),
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_29, NONE, PLTRST, NF1),
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_30, NONE, PLTRST, NF1),
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_31, NONE, PLTRST, NF1),
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_68, NONE, PLTRST, NF1),
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_69, NONE, PLTRST, NF1),
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_70, NONE, PLTRST, NF1),
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_71, NONE, PLTRST, NF1),
+
+	/* CPU PCIe vGPIO for RP2 */
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_32, NONE, PLTRST, NF1),
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_33, NONE, PLTRST, NF1),
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_34, NONE, PLTRST, NF1),
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_35, NONE, PLTRST, NF1),
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_36, NONE, PLTRST, NF1),
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_37, NONE, PLTRST, NF1),
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_38, NONE, PLTRST, NF1),
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_39, NONE, PLTRST, NF1),
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_40, NONE, PLTRST, NF1),
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_41, NONE, PLTRST, NF1),
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_42, NONE, PLTRST, NF1),
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_43, NONE, PLTRST, NF1),
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_44, NONE, PLTRST, NF1),
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_45, NONE, PLTRST, NF1),
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_46, NONE, PLTRST, NF1),
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_47, NONE, PLTRST, NF1),
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_72, NONE, PLTRST, NF1),
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_73, NONE, PLTRST, NF1),
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_74, NONE, PLTRST, NF1),
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_75, NONE, PLTRST, NF1),
+
+	/* CPU PCIe vGPIO for RP3 */
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_48, NONE, PLTRST, NF1),
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_49, NONE, PLTRST, NF1),
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_50, NONE, PLTRST, NF1),
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_51, NONE, PLTRST, NF1),
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_52, NONE, PLTRST, NF1),
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_53, NONE, PLTRST, NF1),
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_54, NONE, PLTRST, NF1),
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_55, NONE, PLTRST, NF1),
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_56, NONE, PLTRST, NF1),
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_57, NONE, PLTRST, NF1),
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_58, NONE, PLTRST, NF1),
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_59, NONE, PLTRST, NF1),
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_60, NONE, PLTRST, NF1),
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_61, NONE, PLTRST, NF1),
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_62, NONE, PLTRST, NF1),
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_63, NONE, PLTRST, NF1),
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_76, NONE, PLTRST, NF1),
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_77, NONE, PLTRST, NF1),
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_78, NONE, PLTRST, NF1),
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_79, NONE, PLTRST, NF1),
+
+	/*_TPM_*/
+	/* H1_PCH_INT_ODL */
+	PAD_CFG_GPI_APIC(GPP_E3, NONE, PLTRST, LEVEL, INVERT),
+	/* F16 : GSPI1_CS0N */
+	PAD_CFG_NF(GPP_F16, NONE, DEEP, NF4),
+	/* F11 : GSPI1_CLK */
+	PAD_CFG_NF(GPP_F11, NONE, DEEP, NF4),
+	/* F13 : GSPI1_MISO */
+	PAD_CFG_NF(GPP_F13, NONE, DEEP, NF4),
+	/* F12 : GSPI1_MOSI */
+	PAD_CFG_NF(GPP_F12, NONE, DEEP, NF4),
+};
+
+static const struct pad_config early_uart_gpio_table[] = {
+	/* UART0 RX */
+	PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2),
+	/* UART0 TX */
+	PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2),
+};
+
+void variant_configure_early_gpio_pads(void)
+{
+	if (CONFIG(INTEL_LPSS_UART_FOR_CONSOLE))
+		gpio_configure_pads(early_uart_gpio_table, ARRAY_SIZE(early_uart_gpio_table));
+
+	gpio_configure_pads(early_gpio_table, ARRAY_SIZE(early_gpio_table));
+}
diff --git a/src/mainboard/siemens/mc_rpl/early_gpio_m.c b/src/mainboard/siemens/mc_rpl/early_gpio_m.c
new file mode 100644
index 0000000000..fbc6467b46
--- /dev/null
+++ b/src/mainboard/siemens/mc_rpl/early_gpio_m.c
@@ -0,0 +1,142 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <baseboard/gpio.h>
+#include <baseboard/variants.h>
+#include <soc/gpio.h>
+
+/* Early pad configuration in bootblock */
+static const struct pad_config early_gpio_table[] = {
+	/* WWAN_RST# */
+	PAD_CFG_GPO(GPP_E5, 0, PLTRST),
+	/* WWAN_PWR_EN */
+	PAD_CFG_GPO(GPP_A8, 1, DEEP),
+
+	/* H0  : PCH_SSD_RST# */
+	PAD_CFG_GPO(GPP_H0, 0, PLTRST),
+	/* H13 : CPU_SSD_RST# */
+	PAD_CFG_GPO(GPP_H13, 0, PLTRST),
+
+	/* EC_IN_RW */
+	PAD_CFG_GPI(GPP_E7, NONE, DEEP),
+
+	/* CPU PCIe VGPIO for RP0 */
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_0, NONE, DEEP, NF1),
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_1, NONE, DEEP, NF1),
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_3, NONE, DEEP, NF1),
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_2, NONE, DEEP, NF1),
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_4, NONE, DEEP, NF1),
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_5, NONE, DEEP, NF1),
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_6, NONE, DEEP, NF1),
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_7, NONE, DEEP, NF1),
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_8, NONE, DEEP, NF1),
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_9, NONE, DEEP, NF1),
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_10, NONE, DEEP, NF1),
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_11, NONE, DEEP, NF1),
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_12, NONE, DEEP, NF1),
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_13, NONE, DEEP, NF1),
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_14, NONE, DEEP, NF1),
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_15, NONE, DEEP, NF1),
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_64, NONE, DEEP, NF1),
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_65, NONE, DEEP, NF1),
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_66, NONE, DEEP, NF1),
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_67, NONE, DEEP, NF1),
+
+	/* CPU PCIe vGPIO for RP1 */
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_16, NONE, DEEP, NF1),
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_17, NONE, DEEP, NF1),
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_18, NONE, DEEP, NF1),
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_19, NONE, DEEP, NF1),
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_20, NONE, DEEP, NF1),
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_21, NONE, DEEP, NF1),
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_22, NONE, DEEP, NF1),
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_23, NONE, DEEP, NF1),
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_24, NONE, DEEP, NF1),
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_25, NONE, DEEP, NF1),
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_26, NONE, DEEP, NF1),
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_27, NONE, DEEP, NF1),
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_28, NONE, DEEP, NF1),
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_29, NONE, DEEP, NF1),
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_30, NONE, DEEP, NF1),
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_31, NONE, DEEP, NF1),
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_68, NONE, DEEP, NF1),
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_69, NONE, DEEP, NF1),
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_70, NONE, DEEP, NF1),
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_71, NONE, DEEP, NF1),
+
+	/* CPU PCIe vGPIO for RP2 */
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_32, NONE, DEEP, NF1),
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_33, NONE, DEEP, NF1),
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_34, NONE, DEEP, NF1),
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_35, NONE, DEEP, NF1),
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_36, NONE, DEEP, NF1),
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_37, NONE, DEEP, NF1),
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_38, NONE, DEEP, NF1),
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_39, NONE, DEEP, NF1),
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_40, NONE, DEEP, NF1),
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_41, NONE, DEEP, NF1),
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_42, NONE, DEEP, NF1),
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_43, NONE, DEEP, NF1),
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_44, NONE, DEEP, NF1),
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_45, NONE, DEEP, NF1),
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_46, NONE, DEEP, NF1),
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_47, NONE, DEEP, NF1),
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_72, NONE, DEEP, NF1),
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_73, NONE, DEEP, NF1),
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_74, NONE, DEEP, NF1),
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_75, NONE, DEEP, NF1),
+
+	/* CPU PCIe vGPIO for RP3 */
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_48, NONE, DEEP, NF1),
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_49, NONE, DEEP, NF1),
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_50, NONE, DEEP, NF1),
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_51, NONE, DEEP, NF1),
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_52, NONE, DEEP, NF1),
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_53, NONE, DEEP, NF1),
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_54, NONE, DEEP, NF1),
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_55, NONE, DEEP, NF1),
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_56, NONE, DEEP, NF1),
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_57, NONE, DEEP, NF1),
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_58, NONE, DEEP, NF1),
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_59, NONE, DEEP, NF1),
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_60, NONE, DEEP, NF1),
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_61, NONE, DEEP, NF1),
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_62, NONE, DEEP, NF1),
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_63, NONE, DEEP, NF1),
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_76, NONE, DEEP, NF1),
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_77, NONE, DEEP, NF1),
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_78, NONE, DEEP, NF1),
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_79, NONE, DEEP, NF1),
+
+	/* H1_PCH_INT_ODL */
+	PAD_CFG_GPI_APIC(GPP_E3, NONE, PLTRST, LEVEL, INVERT),
+	/* TPM */
+	/* F16 : GSPI1_CS0N */
+	PAD_CFG_NF(GPP_F16, NONE, DEEP, NF4),
+	/* F11 : GSPI1_CLK */
+	PAD_CFG_NF(GPP_F11, NONE, DEEP, NF4),
+	/* F13 : GSPI1_MISO */
+	PAD_CFG_NF(GPP_F13, NONE, DEEP, NF4),
+	/* F12 : GSPI1_MOSI */
+	PAD_CFG_NF(GPP_F12, NONE, DEEP, NF4),
+
+	 /* D10 : PCH_SSD_PWR_EN */
+	PAD_CFG_GPO(GPP_D10, 1, PLTRST),
+	/* D16 : CPU_SSD_PWR_EN */
+	PAD_CFG_GPO(GPP_D16, 1, PLTRST),
+
+};
+
+static const struct pad_config early_uart_gpio_table[] = {
+	/* UART0 RX */
+	PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2),
+	/* UART0 TX */
+	PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2),
+};
+
+void variant_configure_early_gpio_pads(void)
+{
+	if (CONFIG(INTEL_LPSS_UART_FOR_CONSOLE))
+		gpio_configure_pads(early_uart_gpio_table, ARRAY_SIZE(early_uart_gpio_table));
+
+	gpio_configure_pads(early_gpio_table, ARRAY_SIZE(early_gpio_table));
+}
diff --git a/src/mainboard/siemens/mc_rpl/early_gpio_n.c b/src/mainboard/siemens/mc_rpl/early_gpio_n.c
new file mode 100644
index 0000000000..3eb1ceae52
--- /dev/null
+++ b/src/mainboard/siemens/mc_rpl/early_gpio_n.c
@@ -0,0 +1,30 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <baseboard/gpio.h>
+#include <baseboard/variants.h>
+#include <soc/gpio.h>
+
+/* Early pad configuration in bootblock */
+static const struct pad_config early_gpio_table[] = {
+	/* WWAN_RST# */
+	PAD_CFG_GPO(GPP_F14, 0, PLTRST),
+	/* WWAN_PWR_EN */
+	PAD_CFG_GPO(GPP_D17, 1, DEEP),
+	/* EC_IN_RW */
+	PAD_CFG_GPI(GPP_E7, NONE, DEEP),
+};
+
+static const struct pad_config early_uart_gpio_table[] = {
+	/* UART0 RX */
+	PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2),
+	/* UART0 TX */
+	PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2),
+};
+
+void variant_configure_early_gpio_pads(void)
+{
+	if (CONFIG(INTEL_LPSS_UART_FOR_CONSOLE))
+		gpio_configure_pads(early_uart_gpio_table, ARRAY_SIZE(early_uart_gpio_table));
+
+	gpio_configure_pads(early_gpio_table, ARRAY_SIZE(early_gpio_table));
+}
diff --git a/src/mainboard/siemens/mc_rpl/ec.c b/src/mainboard/siemens/mc_rpl/ec.c
new file mode 100644
index 0000000000..14760017ef
--- /dev/null
+++ b/src/mainboard/siemens/mc_rpl/ec.c
@@ -0,0 +1,19 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <acpi/acpi.h>
+#include <ec/ec.h>
+#include <ec/google/chromeec/ec.h>
+#include <baseboard/ec.h>
+
+void mainboard_ec_init(void)
+{
+	const struct google_chromeec_event_info info = {
+		.log_events = MAINBOARD_EC_LOG_EVENTS,
+		.sci_events = MAINBOARD_EC_SCI_EVENTS,
+		.s3_wake_events = MAINBOARD_EC_S3_WAKE_EVENTS,
+		.s5_wake_events = MAINBOARD_EC_S5_WAKE_EVENTS,
+		.s0ix_wake_events = MAINBOARD_EC_S0IX_WAKE_EVENTS,
+	};
+
+	google_chromeec_events_init(&info, acpi_is_wakeup_s3());
+}
diff --git a/src/mainboard/siemens/mc_rpl/fw_config.c b/src/mainboard/siemens/mc_rpl/fw_config.c
new file mode 100644
index 0000000000..8589bd8bdc
--- /dev/null
+++ b/src/mainboard/siemens/mc_rpl/fw_config.c
@@ -0,0 +1,41 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <bootstate.h>
+#include <console/console.h>
+#include <fw_config.h>
+#include <gpio.h>
+
+static const struct pad_config i2s_enable_pads[] = {
+	/* Audio Codec INT N */
+	PAD_CFG_GPI_APIC(GPP_H3, NONE, PLTRST, EDGE_BOTH, INVERT),
+
+	/* I2S0_SCLK */
+	PAD_CFG_NF(GPP_R0, NONE, DEEP, NF2),
+	/* I2S0_SFRM */
+	PAD_CFG_NF(GPP_R1, NONE, DEEP, NF2),
+	/* I2S0_TXD */
+	PAD_CFG_NF(GPP_R2, NONE, DEEP, NF2),
+	/* I2S0_RXD */
+	PAD_CFG_NF(GPP_R3, NONE, DEEP, NF2),
+
+	/* I2S2_SCLK */
+	PAD_CFG_NF(GPP_R4, NONE, DEEP, NF2),
+	/* I2S2_SFRM */
+	PAD_CFG_NF(GPP_R5, NONE, DEEP, NF2),
+	/* I2S2_TXD */
+	PAD_CFG_NF(GPP_R6, NONE, DEEP, NF2),
+	/* I2S2_RXD */
+	PAD_CFG_NF(GPP_R7, NONE, DEEP, NF2),
+
+	/* I2S_MCLK1_OUT */
+	PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1),
+};
+
+static void fw_config_handle(void *unused)
+{
+	if (fw_config_probe(FW_CONFIG(AUDIO, ADL_MAX98373_ALC5682I_I2S))) {
+		printk(BIOS_INFO, "Configure GPIOs for I2S audio.\n");
+		gpio_configure_pads(i2s_enable_pads, ARRAY_SIZE(i2s_enable_pads));
+	}
+}
+BOOT_STATE_INIT_ENTRY(BS_DEV_ENABLE, BS_ON_ENTRY, fw_config_handle, NULL);
diff --git a/src/mainboard/siemens/mc_rpl/gpio.c b/src/mainboard/siemens/mc_rpl/gpio.c
new file mode 100644
index 0000000000..d1ed7c7df1
--- /dev/null
+++ b/src/mainboard/siemens/mc_rpl/gpio.c
@@ -0,0 +1,276 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <baseboard/gpio.h>
+#include <baseboard/variants.h>
+#include <types.h>
+#include <vendorcode/google/chromeos/chromeos.h>
+
+/* Pad configuration in ramstage */
+static const struct pad_config gpio_table[] = {
+	/* GPIO A0-A6, A9-A10 default function is NF1 for eSPI interface when
+	  eSPI is enabled */
+
+	/* SSD1_PWREN  CPU SSD1 */
+	PAD_CFG_GPO(GPP_D14, 1, PLTRST),
+	/* SSD1_RESET  CPU SSD1 */
+	PAD_CFG_GPO(GPP_F20, 1, PLTRST),
+	/* BT_RF_KILL_N */
+	PAD_CFG_GPO(GPP_A13, 1, PLTRST),
+	/* WLAN RST# */
+	PAD_CFG_GPO(GPP_H2, 1, PLTRST),
+	/* WIFI_WAKE_N */
+	PAD_CFG_GPI_IRQ_WAKE(GPP_D13, NONE, DEEP, LEVEL, INVERT),
+	/* x4 PCIE slot1 PWREN */
+	PAD_CFG_GPO(GPP_H17, 0, PLTRST),
+	/* x4 PCIE slot 1 RESET */
+	PAD_CFG_GPO(GPP_F10, 1, PLTRST),
+	/* Retimer Force Power */
+	PAD_CFG_GPO(GPP_E4, 0, PLTRST),
+	/* PEG Slot RST# */
+	PAD_CFG_GPO(GPP_B2, 1, PLTRST),
+	/* M.2 SSD_2 Reset */
+	PAD_CFG_GPO(GPP_H0, 1, PLTRST),
+	/* CAM_STROBE */
+	PAD_CFG_GPO(GPP_B18, 0, PLTRST),
+	/* Audio Codec INT N */
+	PAD_CFG_GPI_APIC(GPP_H3, NONE, PLTRST, LEVEL, INVERT),
+	/* TCH PAD Power EN */
+	PAD_CFG_GPO(GPP_F7, 1, PLTRST),
+	/* THC1 SPI2 RST# */
+	PAD_CFG_GPO(GPP_F17, 1, PLTRST),
+	/* THC1_SPI2_INTB */
+	PAD_CFG_GPI_APIC(GPP_F18, NONE, PLTRST, EDGE_SINGLE, INVERT),
+	/* THC1_SPI2_INTB */
+	PAD_CFG_GPI(GPP_E17, NONE, PLTRST),
+	/* EC_SLP_S0_CS_N */
+	PAD_CFG_GPO(GPP_F9, 1, PLTRST),
+	/* DISP_AUX_N_BIAS_GPIO */
+	PAD_CFG_GPO(GPP_E23, 1, PLTRST),
+	/* WWAN WAKE N*/
+	PAD_CFG_GPI_IRQ_WAKE(GPP_D18, NONE, DEEP, LEVEL, INVERT),
+	/* WWAN_DISABLE_N */
+	PAD_CFG_GPO(GPP_D15, 1, DEEP),
+	/* WWAN_RST# */
+	PAD_CFG_GPO(GPP_F14, 1, DEEP),
+	/* WWAN_FCP_OFF_N */
+	PAD_CFG_GPO(GPP_F15, 1, DEEP),
+	/* WWAN_PWR_EN */
+	PAD_CFG_GPO(GPP_F21, 1, DEEP),
+	/* WWAN_PERST# */
+	PAD_CFG_GPO(GPP_C5, 1, DEEP),
+	/* PEG_SLOT_WAKE_N */
+	PAD_CFG_GPI(GPP_A20, NONE, PLTRST),
+	/* CAM CONN1 CLKEN */
+	PAD_CFG_GPO(GPP_H15, 1, PLTRST),
+	/* CPU SSD2 PWREN */
+	PAD_CFG_GPO(GPP_C2, 1, PLTRST),
+	/* CPU SSD2 RST# */
+	PAD_CFG_GPO(GPP_H1, 1, PLTRST),
+	/* Sata direct Power */
+	PAD_CFG_GPO(GPP_B4, 1, PLTRST),
+	/* M.2_PCH_SSD_PWREN */
+	PAD_CFG_GPO(GPP_D16, 1, PLTRST),
+
+	/* CAM1_RST */
+	PAD_CFG_GPO(GPP_R5, 1, PLTRST),
+	/* CAM2_RST */
+	PAD_CFG_GPO(GPP_E15, 1, PLTRST),
+	/* CAM1_PWR_EN */
+	PAD_CFG_GPO(GPP_B23, 1, PLTRST),
+	/* CAM2_PWR_EN */
+	PAD_CFG_GPO(GPP_E16, 1, PLTRST),
+	/* M.2_SSD_PDET_R */
+	PAD_CFG_NF(GPP_A12, NONE, DEEP, NF1),
+	/* THC0 SPI1 CLK */
+	PAD_CFG_NF(GPP_E11, NONE, DEEP, NF2),
+	/* THC0 SPI1 IO 1 */
+	PAD_CFG_NF(GPP_E12, NONE, DEEP, NF2),
+	/* THC0 SPI1 IO 2 */
+	PAD_CFG_NF(GPP_E1, NONE, DEEP, NF2),
+	/* THC0 SPI IO 3 */
+	PAD_CFG_NF(GPP_E2, NONE, DEEP, NF2),
+	/* THC1 SPI1 RSTB */
+	PAD_CFG_NF(GPP_E6, NONE, DEEP, NF2),
+	/* UART_RX(1) */
+	PAD_CFG_NF(GPP_C12, NONE, DEEP, NF1),
+	/* UART_RX(2) */
+	PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1),
+	/* UART_RX(4) */
+	PAD_CFG_NF(GPP_T4, NONE, DEEP, NF1),
+	/* UART_RX(5) */
+	PAD_CFG_NF(GPP_T8, NONE, DEEP, NF1),
+	/* UART_RX(6) */
+	PAD_CFG_NF(GPP_T12, NONE, DEEP, NF1),
+
+	/* UART_TX(1) */
+	PAD_CFG_NF(GPP_C13, NONE, DEEP, NF1),
+	/* UART_TX(2) */
+	PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1),
+	/* UART_TX(4) */
+	PAD_CFG_NF(GPP_T5, NONE, DEEP, NF1),
+	/* UART_TX(5) */
+	PAD_CFG_NF(GPP_T9, NONE, DEEP, NF1),
+	/* UART_TX(6) */
+	PAD_CFG_NF(GPP_T13, NONE, DEEP, NF1),
+
+	/* UART_RTS(1) */
+	PAD_CFG_NF(GPP_C14, NONE, DEEP, NF1),
+	/* UART_RTS(2) */
+	PAD_CFG_NF(GPP_C22, NONE, DEEP, NF1),
+	/* UART_RTS(4) */
+	PAD_CFG_NF(GPP_T6, NONE, DEEP, NF1),
+	/* UART_RTS(5) */
+	PAD_CFG_NF(GPP_T10, NONE, DEEP, NF1),
+	/* UART_RTS(6) */
+	PAD_CFG_NF(GPP_T14, NONE, DEEP, NF1),
+
+	/* UART_CTS(1) */
+	PAD_CFG_NF(GPP_C15, NONE, DEEP, NF1),
+	/* UART_CTS(2) */
+	PAD_CFG_NF(GPP_C23, NONE, DEEP, NF1),
+	/* UART_CTS(4) */
+	PAD_CFG_NF(GPP_T7, NONE, DEEP, NF1),
+	/* UART_CTS(5) */
+	PAD_CFG_NF(GPP_T11, NONE, DEEP, NF1),
+	/* UART_CTS(6) */
+	PAD_CFG_NF(GPP_T15, NONE, DEEP, NF1),
+
+	/* SPI_MOSI(1) */
+	PAD_CFG_NF(GPP_B22, NONE, DEEP, NF1),
+	/* SPI_MOSI(2) */
+	PAD_CFG_NF(GPP_D12, NONE, DEEP, NF2),
+
+	/* SPI_MIS0(1) */
+	PAD_CFG_NF(GPP_B21, NONE, DEEP, NF1),
+	/* SPI_MIS0(2) */
+	PAD_CFG_NF(GPP_D11, NONE, DEEP, NF2),
+
+	/* SPI_CLK(1) */
+	PAD_CFG_NF(GPP_B20, NONE, DEEP, NF1),
+	/* SPI_CLK(2) */
+	PAD_CFG_NF(GPP_D10, NONE, DEEP, NF2),
+
+	/* SPI_CS(0, 1) */
+	PAD_CFG_NF(GPP_B14, NONE, DEEP, NF1),
+	/* SPI_CS(1, 0) */
+	PAD_CFG_NF(GPP_B19, NONE, DEEP, NF1),
+	/* SPI_CS(2, 0) */
+	PAD_CFG_NF(GPP_D9, NONE, DEEP, NF2),
+
+	/* I2C_SCL(0) */
+	PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1),
+	/* I2C_SCL(1) */
+	PAD_CFG_NF(GPP_H7, NONE, DEEP, NF1),
+	/* I2C_SCL(2) */
+	PAD_CFG_NF(GPP_B6, NONE, DEEP, NF2),
+	/* I2C_SCL(3) */
+	PAD_CFG_NF(GPP_B8, NONE, DEEP, NF2),
+	/* I2C_SCL(5) */
+	PAD_CFG_NF(GPP_B17, NONE, DEEP, NF2),
+
+	/* I2C_SDA(0) */
+	PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1),
+	/* I2C_SDA(1) */
+	PAD_CFG_NF(GPP_H6, NONE, DEEP, NF1),
+	/* I2C_SDA(2) */
+	PAD_CFG_NF(GPP_B5, NONE, DEEP, NF2),
+	/* I2C_SDA(3) */
+	PAD_CFG_NF(GPP_B7, NONE, DEEP, NF2),
+	/* I2C_SDA(5) */
+	PAD_CFG_NF(GPP_B16, NONE, DEEP, NF2),
+
+	/* I2S0_SCLK */
+	PAD_CFG_NF(GPP_R0, NONE, DEEP, NF2),
+	/* I2S0_SFRM */
+	PAD_CFG_NF(GPP_R1, NONE, DEEP, NF2),
+	/* I2S0_TXD */
+	PAD_CFG_NF(GPP_R2, NONE, DEEP, NF2),
+	/* I2S0_RXD */
+	PAD_CFG_NF(GPP_R3, NONE, DEEP, NF2),
+
+	/* I2S_MCLK1_OUT */
+	PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1),
+	/* I2S_MCLK2_INOUT */
+	PAD_CFG_NF(GPP_F8, NONE, DEEP, NF1),
+
+	/* SNDW1_CLK */
+	PAD_CFG_NF(GPP_S0, NONE, DEEP, NF1),
+	/* SNDW1_DATA */
+	PAD_CFG_NF(GPP_S1, NONE, DEEP, NF1),
+	/* SNDW2_CLK */
+	PAD_CFG_NF(GPP_S2, NONE, DEEP, NF2),
+	/* SNDW2_DATA */
+	PAD_CFG_NF(GPP_S3, NONE, DEEP, NF2),
+	/* SNDW3_CLK */
+	PAD_CFG_NF(GPP_S4, NONE, DEEP, NF2),
+	/* SNDW3_DATA */
+	PAD_CFG_NF(GPP_S5, NONE, DEEP, NF2),
+	/* SNDW4_CLK */
+	PAD_CFG_NF(GPP_S6, NONE, DEEP, NF2),
+	/* SNDW4_DATA */
+	PAD_CFG_NF(GPP_S7, NONE, DEEP, NF2),
+
+	/* SMB_CLK */
+	PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1),
+	/* SMB_DATA */
+	PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1),
+
+	/* SATA DEVSLP */
+	PAD_CFG_NF(GPP_H12, NONE, DEEP, NF4),
+	PAD_CFG_NF(GPP_H13, NONE, DEEP, NF5),
+
+	/* SATA LED pin */
+	PAD_CFG_NF(GPP_E8, NONE, DEEP, NF1),
+
+	/* USB2 OC0 pins */
+	PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1),
+	/* USB2 OC3 pins */
+	PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1),
+
+	/* GPIO pin for PCIE SRCCLKREQB */
+	PAD_CFG_NF(GPP_D5, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_D6, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_D7, NONE, DEEP, NF1),
+	PAD_NC(GPP_D8, NONE),
+	PAD_CFG_NF(GPP_H19, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1),
+
+	/* DDP1/2/3/4/A/B/C  CTRLCLK and CTRLDATA pins */
+	PAD_CFG_NF(GPP_E18, NONE, DEEP, NF4),
+	PAD_CFG_NF(GPP_E19, NONE, DEEP, NF4),
+	PAD_CFG_NF(GPP_E20, NONE, DEEP, NF4),
+	PAD_CFG_NF(GPP_E21, NONE, DEEP, NF4),
+	PAD_CFG_NF(GPP_E22, NONE, DEEP, NF2),
+	PAD_CFG_NF(GPP_A21, NONE, DEEP, NF2),
+	PAD_CFG_NF(GPP_A22, NONE, DEEP, NF2),
+
+	/* HPD_1 (E14) and HPD_2 (A18) pins */
+	PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1),
+
+	/* IMGCLKOUT */
+	PAD_CFG_NF(GPP_D4, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_H20, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_H21, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_H22, NONE, DEEP, NF1),
+	/* H23 : CLKREQ5_WWAN_N */
+	PAD_CFG_NF(GPP_H23, NONE, DEEP, NF1),
+
+	/* A21 : HDMI CRLS CTRLCLK */
+	PAD_CFG_NF(GPP_A21, NONE, DEEP, NF1),
+	/* A22 : HDMI CRLS CTRLDATA */
+	PAD_CFG_NF(GPP_A22, NONE, DEEP, NF1),
+	/* H1_PCH_INT_ODL */
+	PAD_CFG_GPI_APIC(GPP_E3, NONE, PLTRST, LEVEL, INVERT)
+};
+
+void variant_configure_gpio_pads(void)
+{
+	gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table));
+}
+
+static const struct cros_gpio cros_gpios[] = {
+	CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME),
+};
+DECLARE_CROS_GPIOS(cros_gpios);
diff --git a/src/mainboard/siemens/mc_rpl/gpio_m.c b/src/mainboard/siemens/mc_rpl/gpio_m.c
new file mode 100644
index 0000000000..5d2366858e
--- /dev/null
+++ b/src/mainboard/siemens/mc_rpl/gpio_m.c
@@ -0,0 +1,193 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <baseboard/gpio.h>
+#include <baseboard/variants.h>
+#include <commonlib/helpers.h>
+#include <vendorcode/google/chromeos/chromeos.h>
+
+/* Pad configuration in ramstage */
+static const struct pad_config gpio_table[] = {
+	/* A12 : BT_RF_KILL_N */
+	PAD_CFG_GPO(GPP_A12, 1, PLTRST),
+
+	/* H2 : WLAN_RST_N */
+	PAD_CFG_GPO(GPP_H2, 1, PLTRST),
+	/* 8 : M.2_BTWIFI_SUS_CLK */
+	PAD_CFG_NF(GPD8, NONE, DEEP, NF1),
+	/* 9 : GPD_9_SLP_WLAN_N */
+	PAD_CFG_NF(GPD9, NONE, DEEP, NF1),
+	/* 10 : GPD_10_SLP_S5_N */
+	PAD_CFG_NF(GPD10, NONE, DEEP, NF1),
+
+	/* D12 : WIFI_RF_KILL_N */
+	PAD_CFG_GPO(GPP_D12, 1, PLTRST),
+	/* D13 : WIFI_WAKE_N */
+	PAD_CFG_NF(GPP_D13, NONE, DEEP, NF1),
+	/* D14 :  x1 PCIE slot1 PWREN / SML0B_CLK */
+	PAD_CFG_NF(GPP_D14, NONE, DEEP, NF1),
+	/* D15 : WWAN_DISABLE_N */
+	PAD_CFG_GPO(GPP_D15, 1, PLTRST),
+	/* D17 : PCIE SLOT1 WAKE N */
+	PAD_CFG_GPI_IRQ_WAKE(GPP_D17, NONE, DEEP, LEVEL, INVERT),
+	/* D18 : WWAN WAKE N*/
+	PAD_CFG_GPI_IRQ_WAKE(GPP_D18, NONE, DEEP, LEVEL, INVERT),
+	/* H23 : CLKREQ5_WWAN_N */
+	PAD_CFG_NF(GPP_H23, NONE, DEEP, NF2),
+
+	/* F0 : CNV_BRI_DT_BT_UART2_RTS_N */
+	PAD_CFG_NF(GPP_F0, NONE, DEEP, NF1),
+	/* F1 : CNV_BRI_RSP_BT_UART2_RXD */
+	PAD_CFG_NF(GPP_F1, NONE, DEEP, NF1),
+	/* F2 : CNV_RGI_DT_BT_UART2_TXD */
+	PAD_CFG_NF(GPP_F2, NONE, DEEP, NF1),
+	/* F3 : CNV_RGI_RSP_BT_UART2_CTS_N */
+	PAD_CFG_NF(GPP_F3, NONE, DEEP, NF1),
+	/* F4 : CNV_RF_RESET_R_N */
+	PAD_CFG_NF(GPP_F4, NONE, DEEP, NF1),
+	/* F5 : MODEM_CLKREQ_R */
+	PAD_CFG_NF(GPP_F5, NONE, DEEP, NF2),
+	/* F6 : GPPC_F6_CNV_PA_BLANKING */
+	PAD_CFG_NF(GPP_F6, NONE, DEEP, NF1),
+	/* F10 : GPPC_F10 X1_Slot_RESET */
+	PAD_CFG_GPO(GPP_F10, 1, PLTRST),
+	/* H8 : CNV_MFUART2_RXD */
+	PAD_CFG_NF(GPP_H8, NONE, DEEP, NF2),
+	/* H9 : CNV_MFUART2_TXD */
+	PAD_CFG_NF(GPP_H9, NONE, DEEP, NF2),
+
+	/* A14 : TCPC01_TYPEA23_OC1_N */
+	PAD_CFG_NF(GPP_A14, NONE, DEEP, NF1),
+	/* A15 :  USB_TYPEA_OC2_N */
+	PAD_CFG_NF(GPP_A15, NONE, DEEP, NF1),
+	/* E18 : TBT_LSX0_TXD */
+	PAD_CFG_NF(GPP_E18, NONE, DEEP, NF4),
+	/* E19 : TBT_LSX0_RXD */
+	PAD_CFG_NF(GPP_E19, NONE, DEEP, NF4),
+	/* E20 : TBT_LSX1_TXD */
+	PAD_CFG_NF(GPP_E20, NONE, DEEP, NF4),
+	/* E21 : TBT_LSX1_RXD */
+	PAD_CFG_NF(GPP_E21, NONE, DEEP, NF4),
+
+	/* H4  : I2C0 SDA */
+	PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1),
+	/* H6  : I2C1 SDA */
+	PAD_CFG_NF(GPP_H6, NONE, DEEP, NF1),
+	/* B16 : I2C5 SDA */
+	PAD_CFG_NF(GPP_B16, NONE, DEEP, NF2),
+
+	/* H5  : I2C0 SCL */
+	PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1),
+	/* H7  : I2C1 SCL */
+	PAD_CFG_NF(GPP_H7, NONE, DEEP, NF1),
+	/* B17 : I2C5 SCL */
+	PAD_CFG_NF(GPP_B17, NONE, DEEP, NF2),
+
+	/* C5  : WWAN_PERST_N */
+	PAD_CFG_GPO(GPP_C5, 1, PLTRST),
+	/* E5  : WWAN_PERST# */
+	PAD_CFG_GPO(GPP_E5, 1, PLTRST),
+	/* D15 : WWAN_DISABLE_N */
+	PAD_CFG_GPO(GPP_D15, 1, PLTRST),
+	/* D9  : WWAN_FCP_POWER_OFF_N */
+	PAD_CFG_GPO(GPP_D9, 1, PLTRST),
+
+	/* H0  : PCH_SSD_RST# */
+	PAD_CFG_GPO(GPP_H0, 1, PLTRST),
+	/* H13 : CPU_SSD_RST# */
+	PAD_CFG_GPO(GPP_H13, 1, PLTRST),
+
+	/* DDP1/2/A/B  CTRLCLK and CTRLDATA pins */
+	PAD_CFG_NF(GPP_E18, NONE, DEEP, NF4),
+	PAD_CFG_NF(GPP_E19, NONE, DEEP, NF4),
+	PAD_CFG_NF(GPP_E20, NONE, DEEP, NF4),
+	PAD_CFG_NF(GPP_E21, NONE, DEEP, NF4),
+	PAD_CFG_NF(GPP_E22, NONE, DEEP, NF2),
+	PAD_CFG_NF(GPP_E23, NONE, DEEP, NF2),
+	PAD_CFG_NF(GPP_A21, NONE, DEEP, NF2),
+	PAD_CFG_NF(GPP_A22, NONE, DEEP, NF2),
+	PAD_CFG_NF(GPP_H15, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_H17, NONE, DEEP, NF1),
+
+	/* HPD_1 (E14) and HPD_2 (A18) pins */
+	PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1),
+
+	PAD_NC(GPP_A19, NONE),
+	PAD_NC(GPP_A20, NONE),
+
+	/* GPIO pin for PCIE SRCCLKREQB */
+	PAD_CFG_NF(GPP_D5, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_D6, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_D7, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_D8, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_H19, NONE, DEEP, NF1),
+
+	/* CAM1_RST */
+	PAD_CFG_GPO(GPP_R5, 1, PLTRST),
+	/* CAM2_RST */
+	PAD_CFG_GPO(GPP_E15, 1, PLTRST),
+	/* CAM1_PWR_EN */
+	PAD_CFG_GPO(GPP_B23, 1, PLTRST),
+	/* CAM2_PWR_EN */
+	PAD_CFG_GPO(GPP_E16, 1, PLTRST),
+	/* IMGCLKOUT0 */
+	PAD_CFG_NF(GPP_D4, NONE, DEEP, NF1),
+	/* IMGCLKOUT1 */
+	PAD_CFG_NF(GPP_H20, NONE, DEEP, NF1),
+
+	/* C16 : I2C0 SDA */
+	PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1),
+
+	/* S0 : SNDW1_CLK */
+	PAD_CFG_NF(GPP_S0, NONE, DEEP, NF1),
+
+	/* S1 : SNDW1_DATA */
+	PAD_CFG_NF(GPP_S1, NONE, DEEP, NF1),
+
+	/* S2 : SNDW2_CLK */
+	PAD_CFG_NF(GPP_S2, NONE, DEEP, NF2),
+
+	/* S3 : SNDW2_DATA */
+	PAD_CFG_NF(GPP_S3, NONE, DEEP, NF2),
+
+	/* S4 : SNDW3_CLK */
+	PAD_CFG_NF(GPP_S4, NONE, DEEP, NF2),
+
+	/* S5 : SNDW3_DATA */
+	PAD_CFG_NF(GPP_S5, NONE, DEEP, NF2),
+
+	/* S6 : SNDW4_CLK */
+	PAD_CFG_NF(GPP_S6, NONE, DEEP, NF2),
+
+	/* S7 : SNDW4_DATA */
+	PAD_CFG_NF(GPP_S7, NONE, DEEP, NF2),
+
+	/* F7  : TCH_PNL_PWR_EN */
+	PAD_CFG_GPO(GPP_F7, 1, PLTRST),
+	/* F17 : RST_N_TCH_PNL2 */
+	PAD_CFG_GPO(GPP_F17, 1, PLTRST),
+	/* F18 : INT_N_TCH_PNL2 */
+	PAD_CFG_GPI_APIC(GPP_F18, NONE, PLTRST, LEVEL, NONE),
+
+	/* E3 : H1_PCH_INT_ODL */
+	PAD_CFG_GPI_APIC(GPP_E3, NONE, PLTRST, LEVEL, INVERT),
+
+	/* E4  : SATA_DEVSLP0 ==> USB4_BB_RT_FORCE_PWR */
+	PAD_CFG_GPO(GPP_E4, 0, DEEP),
+
+	/* H1 : GPPC_H1_TCH_PAD_TCH_PNL2_LS_EN */
+	PAD_CFG_GPO(GPP_H1, 0, PLTRST),
+
+	/* D11 : TCH_PAD_INT_N */
+	PAD_CFG_GPI_APIC(GPP_D11, NONE, PLTRST, LEVEL, INVERT)
+};
+
+void variant_configure_gpio_pads(void)
+{
+	gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table));
+}
+
+static const struct cros_gpio cros_gpios[] = {
+	CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME),
+};
+DECLARE_CROS_GPIOS(cros_gpios);
diff --git a/src/mainboard/siemens/mc_rpl/gpio_n.c b/src/mainboard/siemens/mc_rpl/gpio_n.c
new file mode 100644
index 0000000000..b985d53dd2
--- /dev/null
+++ b/src/mainboard/siemens/mc_rpl/gpio_n.c
@@ -0,0 +1,239 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <baseboard/gpio.h>
+#include <baseboard/variants.h>
+#include <commonlib/helpers.h>
+#include <vendorcode/google/chromeos/chromeos.h>
+
+/* Pad configuration in ramstage*/
+static const struct pad_config gpio_table[] = {
+	/* ESPI_IO0_EC_R / ESPI_IO0_HDR */
+	PAD_CFG_NF(GPP_A0, NONE, DEEP, NF1),
+	/* ESPI_IO1_EC_R / ESPI_IO1_HDR */
+	PAD_CFG_NF(GPP_A1, NONE, DEEP, NF1),
+	/* ESPI_IO2_EC_R / ESPI_IO2_HDR */
+	PAD_CFG_NF(GPP_A2, NONE, DEEP, NF1),
+	/* ESPI_IO3_EC_R / ESPI_IO3_HDR */
+	PAD_CFG_NF(GPP_A3, NONE, DEEP, NF1),
+	/* ESPI_CS0_EC_R_N / ESPI_CS0_HDR_N */
+	PAD_CFG_NF(GPP_A4, NONE, DEEP, NF1),
+	/* ESPI_ALERT0_EC_R_N / ESPI_ALERT0_HDR_N */
+	PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1),
+	/* ESPI_CLK_EC_R / ESPI_CLK_HDR */
+	PAD_CFG_NF(GPP_A9, NONE, DEEP, NF1),
+	/* ESPI_RST_EC_R_N / ESPI_RST_HDR_N */
+	PAD_CFG_NF(GPP_A10, NONE, DEEP, NF1),
+
+	/* EC_SLP_S0_CS_N */
+	PAD_CFG_GPO(GPP_E4, 1, PLTRST),
+
+	/* H15 : DDPB_CTRLCLK ==> DDIB_HDMI_CTRLCLK */
+	PAD_CFG_NF(GPP_H15, NONE, DEEP, NF1),
+	/* H17 : DDPB_CTRLDATA ==> DDIB_HDMI_CTRLDATA */
+	PAD_CFG_NF(GPP_H17, NONE, DEEP, NF1),
+
+	/* M.2_SSD_PDET_R */
+	PAD_CFG_NF(GPP_A12, NONE, DEEP, NF1),
+	/* CLKREQ0_M2_SSD_N */
+	PAD_CFG_NF(GPP_D5, NONE, DEEP, NF1),
+	/* M2_PCH_SSD_PWREN */
+	PAD_CFG_GPO(GPP_D16, 1, PLTRST),
+	/* M2_SSD_RST_N */
+	PAD_CFG_GPO(GPP_H0, 1, PLTRST),
+	/* M2_SSD_DEVSLP */
+	PAD_CFG_NF(GPP_H13, NONE, DEEP, NF5),
+
+	/* I5  : NC */
+	PAD_NC(GPP_I5, NONE),
+	/* I7  : EMMC_CMD ==> EMMC_CMD */
+	PAD_CFG_NF(GPP_I7, NONE, DEEP, NF1),
+	/* I8  : EMMC_DATA0 ==> EMMC_D0 */
+	PAD_CFG_NF(GPP_I8, NONE, DEEP, NF1),
+	/* I9  : EMMC_DATA1 ==> EMMC_D1 */
+	PAD_CFG_NF(GPP_I9, NONE, DEEP, NF1),
+	/* I10 : EMMC_DATA2 ==> EMMC_D2 */
+	PAD_CFG_NF(GPP_I10, NONE, DEEP, NF1),
+	/* I11 : EMMC_DATA3 ==> EMMC_D3 */
+	PAD_CFG_NF(GPP_I11, NONE, DEEP, NF1),
+	/* I12 : EMMC_DATA4 ==> EMMC_D4 */
+	PAD_CFG_NF(GPP_I12, NONE, DEEP, NF1),
+	/* I13 : EMMC_DATA5 ==> EMMC_D5 */
+	PAD_CFG_NF(GPP_I13, NONE, DEEP, NF1),
+	/* I14 : EMMC_DATA6 ==> EMMC_D6 */
+	PAD_CFG_NF(GPP_I14, NONE, DEEP, NF1),
+	/* I15 : EMMC_DATA7 ==> EMMC_D7 */
+	PAD_CFG_NF(GPP_I15, NONE, DEEP, NF1),
+	/* I16 : EMMC_RCLK ==> EMMC_RCLK */
+	PAD_CFG_NF(GPP_I16, NONE, DEEP, NF1),
+	/* I17 : EMMC_CLK ==> EMMC_CLK */
+	PAD_CFG_NF(GPP_I17, NONE, DEEP, NF1),
+	/* I18 : EMMC_RESET# ==> EMMC_RST_L */
+	PAD_CFG_NF(GPP_I18, NONE, DEEP, NF1),
+
+	/* TYPEA_CONN23_USB2_P8_OC1_N */
+	PAD_CFG_NF(GPP_A14, NONE, DEEP, NF1),
+	/* CRD1_PWREN */
+	PAD_CFG_GPO(GPP_B23, 1, PLTRST),
+	/* TCP1_DISP_AUX_P_BIAS_GPIO */
+	PAD_CFG_GPO(GPP_E20, 1, PLTRST),
+	/* TCP1_DISP_AUX_N_BIAS_GPIO */
+	PAD_CFG_GPO(GPP_E21, 0, PLTRST),
+	/* TCP0_DISP_AUX_P_BIAS_GPIO */
+	PAD_CFG_GPO(GPP_E22, 0, PLTRST),
+	/* TCP0_DISP_AUX_N_BIAS_GPIO */
+	PAD_CFG_GPO(GPP_E23, 1, PLTRST),
+
+	/* EDP1_HPD_MIPI_PNL_RST */
+	PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1),
+
+	/* X1_SLOT_PWREN */
+	PAD_CFG_GPO(GPP_A8, 0, PLTRST),
+	/* SML0_CLK */
+	PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1),
+	/* SML0_DATA */
+	PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1),
+	/* CLKREQ3_X1PCIE_SLOT_N */
+	PAD_CFG_NF(GPP_D8, NONE, DEEP, NF1),
+	/* X1_PCIE_SLOT_WAKE_N */
+	PAD_CFG_GPI_IRQ_WAKE(GPP_D11, NONE, DEEP, LEVEL, INVERT),
+	/* X1_Slot_RESET */
+	PAD_CFG_GPO(GPP_F10, 1, PLTRST),
+
+	/* WWAN_PERST_N */
+	PAD_CFG_GPO(GPP_C5, 1, PLTRST),
+	/* CLKREQ1_WWAN_N */
+	PAD_CFG_NF(GPP_D6, NONE, DEEP, NF1),
+	/* GPPC_D15_M.2_WWAN_DISABLE_N */
+	PAD_CFG_GPO(GPP_D15, 1, PLTRST),
+	/* WWAN_PWREN */
+	PAD_CFG_GPO(GPP_D17, 1, PLTRST),
+	/* WWAN WAKE N */
+	PAD_CFG_GPI_IRQ_WAKE(GPP_D18, NONE, DEEP, LEVEL, INVERT), //TODO SCI
+	/* SRCCLK_OEB6 */
+	PAD_CFG_NF(GPP_E5, NONE, DEEP, NF3),
+	/* GPPC_F6_CNV_PA_BLANKING */
+	PAD_CFG_NF(GPP_F6, NONE, DEEP, NF1),
+	/* WWAN_RST# */
+	PAD_CFG_GPO(GPP_F14, 1, PLTRST),
+	/* WWAN_FCP_OFF_N */
+	PAD_CFG_GPO(GPP_F15, 1, PLTRST),
+	/* CNV_MFUART2_RXD */
+	PAD_CFG_NF(GPP_H8, NONE, DEEP, NF2),
+	/* CNV_MFUART2_RXD */
+	PAD_CFG_NF(GPP_H9, NONE, DEEP, NF2),
+
+	/* PM_SLP_S0_N */
+	PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1),
+	/* PLT_RST_N */
+	PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1),
+	/* PM_SLP_DRAM_N */
+	PAD_CFG_NF(GPP_E8, NONE, DEEP, NF2),
+	/* CPU_C10_GATE_N_R */
+	PAD_CFG_NF(GPP_H18, NONE, DEEP, NF1),
+
+	/* CODEC_INT_N */
+	PAD_CFG_GPI_APIC(GPP_H3, NONE, PLTRST, LEVEL, INVERT),
+	/* SNDW0_CLK_HDR */
+	PAD_CFG_NF(GPP_S0, NONE, DEEP, NF1),
+	/* SNDW0_DATA_HDR */
+	PAD_CFG_NF(GPP_S1, NONE, DEEP, NF1),
+	/* SNDW1_CLK_DMIC_CLK_A_0 */
+	PAD_CFG_NF(GPP_S2, NONE, DEEP, NF2),
+	/* SNDW1_DATA_DMIC_DATA_0 */
+	PAD_CFG_NF(GPP_S3, NONE, DEEP, NF2),
+	/* SNDW2_CLK_R */
+	PAD_CFG_NF(GPP_S4, NONE, DEEP, NF1),
+	/* SNDW2_DATA_R */
+	PAD_CFG_NF(GPP_S5, NONE, DEEP, NF1),
+	/* SOC_DMIC0_SNDW3_CLK */
+	PAD_CFG_NF(GPP_S6, NONE, DEEP, NF2),
+	/* SOC_DMIC0_SNDW3_DATA */
+	PAD_CFG_NF(GPP_S7, NONE, DEEP, NF2),
+
+	/* I2C_SCL(0) */
+	PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1),
+	/* I2C_SDA(0) */
+	PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1),
+
+	/* DDIB_DP_HDMI_ALS_HDP */
+	PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1),
+
+	/* 8 : M.2_BTWIFI_SUS_CLK */
+	PAD_CFG_NF(GPD8, NONE, DEEP, NF1),
+	/* 9 : GPD_9_SLP_WLAN_N */
+	PAD_CFG_NF(GPD9, NONE, DEEP, NF1),
+
+	/* SRCCLK_OEB7 */
+	PAD_CFG_GPO(GPP_A7, 0, PLTRST),
+
+	/* GPIO pin for PCIE SRCCLKREQB_2 */
+	PAD_CFG_NF(GPP_D7, NONE, DEEP, NF1),
+
+	/* H2 : WLAN_RST_N */
+	PAD_CFG_GPO(GPP_H2, 1, PLTRST),
+	/* I2C_SDA(1) */
+	PAD_CFG_NF(GPP_H6, NONE, DEEP, NF1),
+	/* I2C_SCL(1) */
+	PAD_CFG_NF(GPP_H7, NONE, DEEP, NF1),
+
+	/* CAM_PRIVACY_LED */
+	PAD_CFG_GPO(GPP_B14, 1, PLTRST),
+
+	/* B16 : I2C5 SDA */
+	PAD_CFG_NF(GPP_B16, NONE, DEEP, NF2),
+	/* B17 : I2C5 SCL */
+	PAD_CFG_NF(GPP_B17, NONE, DEEP, NF2),
+
+	/* CAM_STROBE */
+	PAD_CFG_GPO(GPP_B18, 0, PLTRST),
+	/* CAM1_RST_N */
+	PAD_CFG_GPO(GPP_A21, 1, PLTRST),
+	/* CAM1_PWR_EN */
+	PAD_CFG_GPO(GPP_B23, 1, PLTRST),
+	/* CAM2_RST */
+	PAD_CFG_GPO(GPP_E15, 1, PLTRST),
+	/* CAM2_PWR_EN */
+	PAD_CFG_GPO(GPP_E16, 1, PLTRST),
+
+	/* IMGCLKOUT */
+	PAD_CFG_NF(GPP_D4, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_H20, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_H21, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_H22, NONE, DEEP, NF1),
+
+	/* BT_RF_KILL_N */
+	PAD_CFG_GPO(GPP_A13, 1, PLTRST),
+
+	/* D13 : WIFI_WAKE_N */
+	PAD_CFG_NF(GPP_D13, NONE, DEEP, NF1),
+	/* WIFI RF KILL */
+	PAD_CFG_GPO(GPP_E3, 1, PLTRST),
+
+	/* F0 : CNV_BRI_DT_BT_UART2_RTS_N */
+	PAD_CFG_NF(GPP_F0, NONE, DEEP, NF1),
+	/* F1 : CNV_BRI_RSP_BT_UART2_RXD */
+	PAD_CFG_NF(GPP_F1, NONE, DEEP, NF1),
+	/* F2 : CNV_RGI_DT_BT_UART2_TXD */
+	PAD_CFG_NF(GPP_F2, NONE, DEEP, NF1),
+	/* F3 : CNV_RGI_RSP_BT_UART2_CTS_N */
+	PAD_CFG_NF(GPP_F3, NONE, DEEP, NF1),
+	/* F4 : CNV_RF_RESET_R_N */
+	PAD_CFG_NF(GPP_F4, NONE, DEEP, NF1),
+	/* F5 : MODEM_CLKREQ_R */
+	PAD_CFG_NF(GPP_F5, NONE, DEEP, NF2),
+	/* TCH PAD Power EN */
+	PAD_CFG_GPO(GPP_F7, 1, PLTRST),
+
+	/* UART_BT_WAKE_N */
+	PAD_CFG_GPI_IRQ_WAKE(GPP_E0, NONE, DEEP, LEVEL, INVERT),
+};
+
+void variant_configure_gpio_pads(void)
+{
+	gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table));
+}
+
+static const struct cros_gpio cros_gpios[] = {
+	CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME),
+};
+DECLARE_CROS_GPIOS(cros_gpios);
diff --git a/src/mainboard/siemens/mc_rpl/include/baseboard/ec.h b/src/mainboard/siemens/mc_rpl/include/baseboard/ec.h
new file mode 100644
index 0000000000..6a5c72ceeb
--- /dev/null
+++ b/src/mainboard/siemens/mc_rpl/include/baseboard/ec.h
@@ -0,0 +1,72 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef __BASEBOARD_EC_H__
+#define __BASEBOARD_EC_H__
+
+#include <ec/ec.h>
+#include <ec/google/chromeec/ec_commands.h>
+#include <baseboard/gpio.h>
+
+#define MAINBOARD_EC_SCI_EVENTS \
+	(EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED)        |\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN)          |\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_CONNECTED)      |\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_DISCONNECTED)   |\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_LOW)       |\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_CRITICAL)  |\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY)           |\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_STATUS)    |\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_THRESHOLD) |\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_START)    |\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_STOP)     |\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_PD_MCU)            |\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_MODE_CHANGE)       |\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_MKBP)              |\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_USB_MUX))
+
+#define MAINBOARD_EC_SMI_EVENTS \
+	(EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED))
+
+/* EC can wake from S5 with lid or power button */
+#define MAINBOARD_EC_S5_WAKE_EVENTS \
+	(EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) |\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_POWER_BUTTON))
+
+/*
+ * EC can wake from S3 with lid or power button or key press or AC connect/disconnect or
+ * mode change event.
+ */
+#define MAINBOARD_EC_S3_WAKE_EVENTS \
+	(MAINBOARD_EC_S5_WAKE_EVENTS |\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_CONNECTED)    |\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_DISCONNECTED) |\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEY_PRESSED) |\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_MODE_CHANGE))
+
+#define MAINBOARD_EC_S0IX_WAKE_EVENTS	(MAINBOARD_EC_S3_WAKE_EVENTS)
+
+/* Log EC wake events plus EC shutdown events */
+#define MAINBOARD_EC_LOG_EVENTS \
+	(EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_SHUTDOWN) |\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_SHUTDOWN) |\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_PANIC))
+
+/*
+ * ACPI related definitions for ASL code.
+ */
+
+/* Enable EC backed ALS device in ACPI */
+#define EC_ENABLE_ALS_DEVICE
+
+/* Enable EC backed PD MCU device in ACPI */
+#define EC_ENABLE_PD_MCU_DEVICE
+
+/* Enable LID switch and provide wake pin for EC */
+#define EC_ENABLE_LID_SWITCH
+#define EC_ENABLE_WAKE_PIN	GPE_EC_WAKE
+
+#define SIO_EC_MEMMAP_ENABLE	/* EC Memory Map Resources */
+#define SIO_EC_HOST_ENABLE	/* EC Host Interface Resources */
+#define SIO_EC_ENABLE_PS2K      /* Enable PS/2 Keyboard */
+
+#endif /* __BASEBOARD_EC_H__ */
diff --git a/src/mainboard/siemens/mc_rpl/include/baseboard/gpio.h b/src/mainboard/siemens/mc_rpl/include/baseboard/gpio.h
new file mode 100644
index 0000000000..9a1c5851c0
--- /dev/null
+++ b/src/mainboard/siemens/mc_rpl/include/baseboard/gpio.h
@@ -0,0 +1,17 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef __BASEBOARD_GPIO_H__
+#define __BASEBOARD_GPIO_H__
+
+#include <soc/gpe.h>
+#include <soc/gpio.h>
+
+/* eSPI virtual wire reporting */
+#define EC_SCI_GPI	GPE0_ESPI
+
+/* EC wake is LAN_WAKE# which is a special DeepSX wake pin */
+#define GPE_EC_WAKE	GPE0_LAN_WAK
+
+#define GPIO_EC_IN_RW	GPP_E7
+
+#endif /* __BASEBOARD_GPIO_H__ */
diff --git a/src/mainboard/siemens/mc_rpl/include/baseboard/variants.h b/src/mainboard/siemens/mc_rpl/include/baseboard/variants.h
new file mode 100644
index 0000000000..bb2c3f62b0
--- /dev/null
+++ b/src/mainboard/siemens/mc_rpl/include/baseboard/variants.h
@@ -0,0 +1,52 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef __BASEBOARD_VARIANTS_H__
+#define __BASEBOARD_VARIANTS_H__
+
+#include <soc/gpio.h>
+#include <soc/meminit.h>
+#include <stdint.h>
+
+enum adl_boardid {
+	/* ADL-P LPDDR4 RVPs */
+	ADL_P_LP4_1 = 0x10,
+	ADL_P_LP4_2 = 0x11,
+	/* ADL-P DDR5 RVPs */
+	ADL_P_DDR5_1 = 0x12,
+	ADL_P_DDR5_2 = 0x16,
+	/* ADL-P LPDDR5 RVP */
+	ADL_P_LP5_1 = 0x13,
+	ADL_P_LP5_2 = 0x17,
+	/* ADL-P DDR4 RVPs */
+	ADL_P_DDR4_1 = 0x14,
+	ADL_P_DDR4_2 = 0x3F,
+	/* ADL-M LP4 and LP5 RVPs */
+	ADL_M_LP4 = 0x1,
+	ADL_M_LP5 = 0x2,
+	/* ADL-N LP5 RVP */
+	ADL_N_LP5 = 0x7,
+};
+
+/* Functions to configure GPIO as per variant schematics */
+void variant_configure_gpio_pads(void);
+void variant_configure_early_gpio_pads(void);
+
+size_t variant_memory_sku(void);
+const struct mb_cfg *variant_memory_params(void);
+void rpl_memory_params(FSPM_UPD *memupd);
+
+/* Modify devictree settings during ramstage */
+void variant_devtree_update(void);
+struct cpu_power_limits {
+	uint16_t mchid;
+	u8 cpu_tdp;
+	unsigned int pl1_min_power;
+	unsigned int pl1_max_power;
+	unsigned int pl2_min_power;
+	unsigned int pl2_max_power;
+	unsigned int pl4_power;
+};
+/* Modify Power Limit devictree settings during ramstage */
+void variant_update_power_limits(void);
+
+#endif /*__BASEBOARD_VARIANTS_H__ */
diff --git a/src/mainboard/siemens/mc_rpl/mainboard.c b/src/mainboard/siemens/mc_rpl/mainboard.c
new file mode 100644
index 0000000000..c02cbf9a58
--- /dev/null
+++ b/src/mainboard/siemens/mc_rpl/mainboard.c
@@ -0,0 +1,91 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <baseboard/gpio.h>
+#include <baseboard/variants.h>
+#include <cpu/cpu.h>
+#include <cpu/intel/cpu_ids.h>
+#include <device/device.h>
+#include <drivers/intel/gma/opregion.h>
+#include <ec/ec.h>
+#include <fw_config.h>
+#include <smbios.h>
+#include <soc/gpio.h>
+#include <stdint.h>
+#include <stdio.h>
+
+#include "board_id.h"
+
+const char *smbios_system_sku(void)
+{
+	static char sku_str[7] = "";
+	uint8_t sku_id = get_board_id();
+
+	snprintf(sku_str, sizeof(sku_str), "sku%u", sku_id);
+	return sku_str;
+}
+
+static void mainboard_init(void *chip_info)
+{
+	variant_configure_gpio_pads();
+
+	if (CONFIG(EC_GOOGLE_CHROMEEC))
+		mainboard_ec_init();
+
+	variant_devtree_update();
+}
+
+void __weak variant_devtree_update(void)
+{
+	/* Override dev tree settings per board */
+}
+
+#if CONFIG(BOARD_INTEL_ADLRVP_N_EXT_EC)
+static void add_fw_config_oem_string(const struct fw_config *config, void *arg)
+{
+	struct smbios_type11 *t;
+	char buffer[64];
+
+	t = (struct smbios_type11 *)arg;
+
+	snprintf(buffer, sizeof(buffer), "%s-%s", config->field_name, config->option_name);
+	t->count = smbios_add_string(t->eos, buffer);
+}
+
+static void mainboard_smbios_strings(struct device *dev, struct smbios_type11 *t)
+{
+	fw_config_for_each_found(add_fw_config_oem_string, t);
+}
+#endif
+
+static void mainboard_enable(struct device *dev)
+{
+#if CONFIG(BOARD_INTEL_ADLRVP_N_EXT_EC)
+	dev->ops->get_smbios_strings = mainboard_smbios_strings;
+#endif
+}
+
+struct chip_operations mainboard_ops = {
+	.init = mainboard_init,
+	.enable_dev = mainboard_enable,
+};
+
+const char *mainboard_vbt_filename(void)
+{
+	if (!CONFIG(CHROMEOS))
+		return "vbt.bin";
+
+	uint32_t cpu_id = cpu_get_cpuid();
+	uint8_t sku_id = get_board_id();
+	switch (sku_id) {
+	case ADL_P_LP5_1:
+	case ADL_P_LP5_2:
+		if (cpu_id == CPUID_RAPTORLAKE_J0)
+			return "vbt_adlrvp_rpl_lp5.bin";
+		return "vbt_adlrvp_lp5.bin";
+	case ADL_P_DDR5_1:
+	case ADL_P_DDR5_2:
+		return "vbt_adlrvp_ddr5.bin";
+	default:
+		return "vbt.bin";
+	}
+}
diff --git a/src/mainboard/siemens/mc_rpl/memory.c b/src/mainboard/siemens/mc_rpl/memory.c
new file mode 100644
index 0000000000..160059921b
--- /dev/null
+++ b/src/mainboard/siemens/mc_rpl/memory.c
@@ -0,0 +1,381 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <baseboard/variants.h>
+#include <console/console.h>
+#include <soc/romstage.h>
+
+#include "board_id.h"
+
+static const struct mb_cfg ddr4_mem_config = {
+	.type = MEM_TYPE_DDR4,
+
+	.rcomp = {
+		/* Baseboard uses only 100ohm Rcomp resistor */
+		.resistor = 100,
+
+		/* Baseboard Rcomp target values */
+		.targets = { 50, 20, 25, 25, 25 },
+	},
+
+	.ect = true, /* Early Command Training */
+
+	.UserBd = BOARD_TYPE_MOBILE,
+
+	.LpDdrDqDqsReTraining = 1,
+
+	.ddr_config = {
+		.dq_pins_interleaved = false,
+	},
+};
+
+static const struct mb_cfg lpddr4_mem_config = {
+	.type = MEM_TYPE_LP4X,
+
+	/* DQ byte map */
+	.lpx_dq_map = {
+		.ddr0 = {
+			.dq0 = {  0,  2,  3,  1,  6,  7,  5,  4, },
+			.dq1 = { 10,  8, 11,  9, 14, 12, 13, 15, },
+		},
+		.ddr1 = {
+			.dq0 = { 12,  8, 14, 10, 11, 13, 15,  9, },
+			.dq1 = {  5,  0,  7,  3,  6,  2,  1,  4, },
+		},
+		.ddr2 = {
+			.dq0 = {  3,  0,  2,  1,  6,  5,  4,  7, },
+			.dq1 = { 12, 13, 14, 15, 10,  9,  8, 11, },
+		},
+		.ddr3 = {
+			.dq0 = {  2,  6,  7,  1,  3,  4,  0,  5, },
+			.dq1 = {  9, 13,  8, 15, 14, 11, 12, 10, },
+		},
+		.ddr4 = {
+			.dq0 = {  3,  0,  1,  2,  7,  4,  6,  5, },
+			.dq1 = { 10,  8, 11,  9, 14, 13, 12, 15, },
+		},
+		.ddr5 = {
+			.dq0 = { 10, 12, 14,  8,  9, 13, 15, 11, },
+			.dq1 = {  3,  7,  6,  2,  0,  4,  5,  1, },
+		},
+		.ddr6 = {
+			.dq0 = { 12, 15, 14, 13,  9, 10, 11,  8, },
+			.dq1 = {  7,  4,  6,  5,  0,  1,  3,  2, },
+		},
+		.ddr7 = {
+			.dq0 = {  0,  2,  4,  3,  1,  6,  7,  5, },
+			.dq1 = { 13,  9, 10, 11,  8, 12, 14, 15, },
+		},
+	},
+
+	/* DQS CPU<>DRAM map */
+	.lpx_dqs_map = {
+		.ddr0 = { .dqs0 = 0, .dqs1 = 1 },
+		.ddr1 = { .dqs0 = 1, .dqs1 = 0 },
+		.ddr2 = { .dqs0 = 0, .dqs1 = 1 },
+		.ddr3 = { .dqs0 = 0, .dqs1 = 1 },
+		.ddr4 = { .dqs0 = 0, .dqs1 = 1 },
+		.ddr5 = { .dqs0 = 1, .dqs1 = 0 },
+		.ddr6 = { .dqs0 = 1, .dqs1 = 0 },
+		.ddr7 = { .dqs0 = 0, .dqs1 = 1 },
+	},
+
+	.LpDdrDqDqsReTraining = 1,
+
+	.ect = true, /* Early Command Training */
+
+	.UserBd = BOARD_TYPE_MOBILE,
+};
+
+static const struct mb_cfg lp5_mem_config = {
+	.type = MEM_TYPE_LP5X,
+
+	/* DQ byte map */
+	.lpx_dq_map = {
+		.ddr0 = {
+			.dq0 = {  3,  2,  1,  0,  5,  4,  6,  7, },
+			.dq1 = { 15, 14, 12, 13,  8,  9, 10, 11, },
+		},
+		.ddr1 = {
+			.dq0 = {  0,  2,  3,  1,  5,  7,  4,  6, },
+			.dq1 = { 14, 13, 15, 12,  8,  9, 11, 10, },
+		},
+		.ddr2 = {
+			.dq0 = {  1,  2,  0,  3,  4,  6,  5,  7, },
+			.dq1 = { 15, 13, 12, 14,  9, 10,  8, 11, },
+		},
+		.ddr3 = {
+			.dq0 = {  2,  1,  3,  0,  7,  4,  5,  6, },
+			.dq1 = { 13, 12, 15, 14,  9, 11,  8, 10, },
+		},
+		.ddr4 = {
+			.dq0 = {  1,  2,  3,  0,  6,  4,  5,  7, },
+			.dq1 = { 15, 13, 14, 12, 10,  9,  8, 11, },
+		},
+		.ddr5 = {
+			.dq0 = {  1,  0,  3,  2,  6,  7,  4,  5, },
+			.dq1 = { 14, 12, 15, 13,  8,  9, 10, 11, },
+		},
+		.ddr6 = {
+			.dq0 = {  0,  2,  1,  3,  4,  7,  5,  6, },
+			.dq1 = { 12, 13, 15, 14,  9, 11, 10,  8, },
+		},
+		.ddr7 = {
+			.dq0 = {  3,  2,  1,  0,  5,  4,  6,  7, },
+			.dq1 = { 13, 15, 11, 12, 10,  9, 14,  8, },
+		},
+	},
+
+	/* DQS CPU<>DRAM map */
+	.lpx_dqs_map = {
+		.ddr0 = { .dqs0 = 0, .dqs1 = 1 },
+		.ddr1 = { .dqs0 = 0, .dqs1 = 1 },
+		.ddr2 = { .dqs0 = 0, .dqs1 = 1 },
+		.ddr3 = { .dqs0 = 0, .dqs1 = 1 },
+		.ddr4 = { .dqs0 = 0, .dqs1 = 1 },
+		.ddr5 = { .dqs0 = 0, .dqs1 = 1 },
+		.ddr6 = { .dqs0 = 0, .dqs1 = 1 },
+		.ddr7 = { .dqs0 = 0, .dqs1 = 1 }
+	},
+
+	.ect = true, /* Early Command Training */
+
+	.LpDdrDqDqsReTraining = 1,
+
+	.UserBd = BOARD_TYPE_MOBILE,
+
+	.lp5x_config = {
+		.ccc_config = 0xff,
+	},
+};
+
+static const struct mb_cfg ddr5_mem_config = {
+	.type = MEM_TYPE_DDR5,
+
+	.rcomp = {
+		/* Baseboard uses only 100ohm Rcomp resistor */
+		.resistor = 100,
+
+		/* Baseboard Rcomp target values */
+		.targets = { 50, 30, 30, 30, 27 },
+	},
+
+	.ect = true, /* Early Command Training */
+
+	.UserBd = BOARD_TYPE_MOBILE,
+
+	.LpDdrDqDqsReTraining = 1,
+
+	.ddr_config = {
+		.dq_pins_interleaved = false,
+	}
+};
+
+static const struct mb_cfg adlm_lp4_mem_config = {
+	.type = MEM_TYPE_LP4X,
+
+	/* DQ byte map */
+	.lpx_dq_map = {
+		.ddr0 = {
+			.dq0 = { 13, 12, 14, 8, 11, 10, 9, 15, }, /* DDR0_DQ0[7:0] */
+			.dq1 = {  3,  2,  7, 6,  0,  1, 5,  4, }, /* DDR0_DQ1[7:0] */
+		},
+		.ddr1 = {
+			.dq0 = { 11, 15, 10, 9, 12, 8, 14, 13, },  /* DDR1_DQ0[7:0] */
+			.dq1 = {  0,  1,  7, 6,  2, 5,  4,  3, },  /* DDR1_DQ1[7:0] */
+		},
+		.ddr2 = {
+			.dq0 = {  6, 7,  3,  2,  0, 4,  1,  5, }, /* DDR2_DQ0[7:0] */
+			.dq1 = { 14, 8, 13, 12, 11, 9, 10, 15, }, /* DDR2_DQ1[7:0] */
+		},
+		.ddr3 = {
+			.dq0 = { 2,  6,  7,  3,  1,  5, 0,  4, }, /* DDR3_DQ0[7:0] */
+			.dq1 = { 8, 14, 13, 12, 10, 11, 9, 15, }, /* DDR3_DQ1[7:0] */
+		},
+		.ddr4 = {
+			.dq0 = { 8, 14, 13, 12, 10, 11, 9, 15, }, /* DDR3_DQ1[7:0] */
+			.dq1 = { 1,  0,  5,  4,  6,  2, 3,  7, }, /* DDR4_DQ1[7:0] */
+		},
+		.ddr5 = {
+			.dq0 = { 8, 10, 9, 12, 14, 11, 13, 15, }, /* DDR5_DQ0[7:0] */
+			.dq1 = { 0,  7, 2,  6,  3,  1,  4,  5, }, /* DDR5_DQ1[7:0] */
+		},
+		.ddr6 = {
+			.dq0 = { 14, 12, 9, 8, 15, 10, 13, 11, }, /* DDR6_DQ0[7:0] */
+			.dq1 = {  4,  0, 5, 6,  3,  2,  1,  7, }, /* DDR6_DQ1[7:0] */
+		},
+		.ddr7 = {
+			.dq0 = { 10, 15, 12, 11, 9, 14, 13, 8, }, /* DDR7_DQ0[7:0] */
+			.dq1 = {  7,  1,  2,  3, 6,  0,  5, 4, }, /* DDR7_DQ1[7:0] */
+		},
+	},
+
+	/* DQS CPU<>DRAM map */
+	.lpx_dqs_map = {
+		.ddr0 = { .dqs0 = 1, .dqs1 = 0 },
+		.ddr1 = { .dqs0 = 1, .dqs1 = 0 },
+		.ddr2 = { .dqs0 = 0, .dqs1 = 1 },
+		.ddr3 = { .dqs0 = 0, .dqs1 = 1 },
+		.ddr4 = { .dqs0 = 1, .dqs1 = 0 },
+		.ddr5 = { .dqs0 = 1, .dqs1 = 0 },
+		.ddr6 = { .dqs0 = 1, .dqs1 = 0 },
+		.ddr7 = { .dqs0 = 1, .dqs1 = 0 }
+	},
+
+	.ect = true, /* Early Command Training */
+
+	.CmdMirror = 0xCC,
+
+	.LpDdrDqDqsReTraining = 1,
+
+	.UserBd = BOARD_TYPE_ULT_ULX_T4,
+};
+
+static const struct mb_cfg adlm_lp5_mem_config = {
+	.type = MEM_TYPE_LP5X,
+
+	/* DQ byte map */
+	.lpx_dq_map = {
+		.ddr0 = {
+			.dq0 = {  4,  5,  7,  6,  3,  2,  1,  0, },
+			.dq1 = { 12, 10,  8, 15, 11,  9, 14, 13, },
+		},
+		.ddr1 = {
+			.dq0 = {  1,  0,  2,  3,  7,  4,  5,  6, },
+			.dq1 = { 14, 15, 10, 11, 13, 12,  8,  9, },
+		},
+		.ddr2 = {
+			.dq0 = {  7,  4,  2,  0,  3,  1,  6,  5, },
+			.dq1 = { 14, 13, 15, 12,  8,  9, 10, 11, },
+		},
+		.ddr3 = {
+			.dq0 = {  3,  2,  0,  1,  7,  5,  6,  4, },
+			.dq1 = { 12, 14, 15, 13, 11,  8, 10,  9, },
+		},
+		.ddr4 = {
+			.dq0 = {  2,  3,  0,  1,  6,  4,  7,  5, },
+			.dq1 = { 14,  9, 11, 13, 12,  8, 15, 10, },
+		},
+		.ddr5 = {
+			.dq0 = {  4,  7,  3,  1,  5,  2,  6,  0, },
+			.dq1 = { 14,  8, 11,  9, 12, 15, 10, 13, },
+		},
+		.ddr6 = {
+			.dq0 = { 10, 11, 13,  9, 15, 12,  8, 14, },
+			.dq1 = {  2,  4,  7,  0,  6,  3,  5,  1, },
+		},
+		.ddr7 = {
+			.dq0 = { 13, 15, 11, 14, 10, 12,  8,  9, },
+			.dq1 = {  6,  5,  4,  7,  3,  1,  2,  0, },
+		},
+	},
+
+	/* DQS CPU<>DRAM map */
+	.lpx_dqs_map = {
+		.ddr0 = { .dqs0 = 0, .dqs1 = 1 },
+		.ddr1 = { .dqs0 = 0, .dqs1 = 1 },
+		.ddr2 = { .dqs0 = 0, .dqs1 = 1 },
+		.ddr3 = { .dqs0 = 0, .dqs1 = 1 },
+		.ddr4 = { .dqs0 = 0, .dqs1 = 1 },
+		.ddr5 = { .dqs0 = 0, .dqs1 = 1 },
+		.ddr6 = { .dqs0 = 1, .dqs1 = 0 },
+		.ddr7 = { .dqs0 = 1, .dqs1 = 0 }
+	},
+
+	.ect = false, /* Early Command Training */
+
+	.UserBd = BOARD_TYPE_ULT_ULX_T4,
+
+	.lp5x_config = {
+		.ccc_config = 0xff,
+	},
+};
+
+static const struct mb_cfg adln_lp5_mem_config = {
+	.type = MEM_TYPE_LP5X,
+
+	/* DQ byte map */
+	.lpx_dq_map = {
+		.ddr0 = {
+			.dq0 = { 12,  9, 10, 11, 14, 13,  8, 15 },
+			.dq1 = {  3,  1,  2,  0,  4,  7,  5,  6 },
+		},
+		.ddr1 = {
+			.dq0 = {  3,  1,  2,  0,  4,  7,  5,  6 },
+			.dq1 = { 13,  9,  8, 11, 10, 14, 15, 12 },
+		},
+		.ddr2 = {
+			.dq0 = {  2,  1,  3,  0,  4,  6,  5,  7 },
+			.dq1 = {  8,  9, 10, 11, 13, 14, 12, 15 },
+		},
+		.ddr3 = {
+			.dq0 = {  3,  0,  1,  2,  5,  6,  4,  7 },
+			.dq1 = { 13,  9, 11,  8, 14, 15, 10, 12 },
+		},
+		.ddr4 = {
+			.dq0 = { 12,  9, 10, 11, 14, 13,  8, 15 },
+			.dq1 = {  3,  1,  2,  0,  4,  7,  5,  6 },
+		},
+		.ddr5 = {
+			.dq0 = {  3,  1,  2,  0,  4,  7,  5,  6 },
+			.dq1 = { 13,  9,  8, 11, 10, 14, 15, 12 },
+		},
+		.ddr6 = {
+			.dq0 = {  2,  1,  3,  0,  4,  6,  5,  7 },
+			.dq1 = {  8,  9, 10, 11, 13, 14, 12, 15 },
+		},
+		.ddr7 = {
+			.dq0 = {  3,  0,  1,  2,  5,  6,  4,  7 },
+			.dq1 = { 13,  9, 11,  8, 14, 15, 10, 12 },
+		},
+	},
+
+	/* DQS CPU<>DRAM map */
+	.lpx_dqs_map = {
+		.ddr0 = { .dqs0 = 1, .dqs1 = 0 },
+		.ddr1 = { .dqs0 = 0, .dqs1 = 1 },
+		.ddr2 = { .dqs0 = 0, .dqs1 = 1 },
+		.ddr3 = { .dqs0 = 0, .dqs1 = 1 },
+		.ddr4 = { .dqs0 = 1, .dqs1 = 0 },
+		.ddr5 = { .dqs0 = 0, .dqs1 = 1 },
+		.ddr6 = { .dqs0 = 0, .dqs1 = 1 },
+		.ddr7 = { .dqs0 = 0, .dqs1 = 1 }
+	},
+
+	.ect = true, /* Early Command Training */
+
+	.UserBd = BOARD_TYPE_ULT_ULX,
+
+	.LpDdrDqDqsReTraining = 1,
+
+	.lp5x_config = {
+		.ccc_config = 0xff,
+	},
+};
+
+const struct mb_cfg *variant_memory_params(void)
+{
+	int board_id = get_board_id();
+
+	switch (board_id) {
+	case ADL_P_LP4_1:
+	case ADL_P_LP4_2:
+		return &lpddr4_mem_config;
+	case ADL_P_DDR4_1:
+	case ADL_P_DDR4_2:
+		return &ddr4_mem_config;
+	case ADL_P_DDR5_1:
+	case ADL_P_DDR5_2:
+		return &ddr5_mem_config;
+	case ADL_P_LP5_1:
+	case ADL_P_LP5_2:
+		return &lp5_mem_config;
+	case ADL_M_LP4:
+		return &adlm_lp4_mem_config;
+	case ADL_M_LP5:
+		return &adlm_lp5_mem_config;
+	case ADL_N_LP5:
+		return &adln_lp5_mem_config;
+	default:
+		die("unsupported board id : 0x%x\n", board_id);
+	}
+}
diff --git a/src/mainboard/siemens/mc_rpl/memory_rpl.c b/src/mainboard/siemens/mc_rpl/memory_rpl.c
new file mode 100644
index 0000000000..8302a06d1f
--- /dev/null
+++ b/src/mainboard/siemens/mc_rpl/memory_rpl.c
@@ -0,0 +1,28 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <baseboard/variants.h>
+#include <soc/romstage.h>
+
+#include "board_id.h"
+
+void rpl_memory_params(FSPM_UPD *memupd)
+{
+	FSP_M_CONFIG *mem_cfg = &memupd->FspmConfig;
+
+	int board_id = get_board_id();
+
+	switch (board_id) {
+	case ADL_P_LP4_1:
+	case ADL_P_LP4_2:
+	case ADL_P_DDR4_1:
+	case ADL_P_DDR4_2:
+	case ADL_P_DDR5_1:
+	case ADL_P_DDR5_2:
+	default:
+		return;
+	case ADL_P_LP5_1:
+	case ADL_P_LP5_2:
+		mem_cfg->Lp5BankMode = 1;
+		return;
+	}
+}
diff --git a/src/mainboard/siemens/mc_rpl/ramstage.c b/src/mainboard/siemens/mc_rpl/ramstage.c
new file mode 100644
index 0000000000..fd8e20332b
--- /dev/null
+++ b/src/mainboard/siemens/mc_rpl/ramstage.c
@@ -0,0 +1,103 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <acpi/acpi_device.h>
+#include <baseboard/variants.h>
+#include <console/console.h>
+#include <device/pci_ids.h>
+#include <device/pci_ops.h>
+#include <soc/gpio_soc_defs.h>
+#include <soc/pci_devs.h>
+#include <soc/soc_chip.h>
+#include <static.h>
+#include <string.h>
+#include <drivers/intel/dptf/chip.h>
+#include "board_id.h"
+#include <intelblocks/power_limit.h>
+
+const struct cpu_power_limits limits[] = {
+	/* SKU_ID, TDP (Watts), pl1_min, pl1_max, pl2_min, pl2_max, PL4 */
+	/* PL2 values are for performance configuration */
+	{ PCI_DID_INTEL_ADL_P_ID_7, 15, 3000, 15000,  55000,  55000, 123000 },
+	{ PCI_DID_INTEL_ADL_P_ID_6, 15, 3000, 15000,  55000,  55000, 123000 },
+	{ PCI_DID_INTEL_ADL_P_ID_5, 28, 4000, 28000,  64000,  64000, 140000 },
+	{ PCI_DID_INTEL_ADL_P_ID_3, 28, 4000, 28000,  64000,  64000, 140000 },
+	{ PCI_DID_INTEL_ADL_P_ID_3, 45, 5000, 45000, 115000, 115000, 215000 },
+	{ PCI_DID_INTEL_ADL_N_ID_1, 15, 3000, 15000,  35000,  35000,  83000 },
+	{ PCI_DID_INTEL_ADL_N_ID_2,  6, 3000,  6000,  25000,  25000,  78000 },
+	{ PCI_DID_INTEL_ADL_N_ID_3,  6, 3000,  6000,  25000,  25000,  78000 },
+	{ PCI_DID_INTEL_ADL_N_ID_4,  6, 3000,  6000,  25000,  25000,  78000 },
+	{ PCI_DID_INTEL_ADL_N_ID_5,  6, 3000,  6000,  25000,  25000,  78000 },
+};
+
+WEAK_DEV_PTR(dptf_policy);
+void variant_update_power_limits(void)
+{
+	const struct device *policy_dev = DEV_PTR(dptf_policy);
+	if (!policy_dev)
+		return;
+
+	struct drivers_intel_dptf_config *config = config_of(policy_dev);
+
+	uint16_t mchid = pci_s_read_config16(PCI_DEV(0, 0, 0), PCI_DEVICE_ID);
+
+	u8 tdp = get_cpu_tdp();
+
+	for (size_t i = 0; i < ARRAY_SIZE(limits); i++) {
+		if (mchid == limits[i].mchid && tdp == limits[i].cpu_tdp) {
+			struct dptf_power_limits *settings = &config->controls.power_limits;
+			config_t *conf = config_of_soc();
+			struct soc_power_limits_config *soc_config = conf->power_limits_config;
+			settings->pl1.min_power = limits[i].pl1_min_power;
+			settings->pl1.max_power = limits[i].pl1_max_power;
+			settings->pl2.min_power = limits[i].pl2_min_power;
+			settings->pl2.max_power = limits[i].pl2_max_power;
+			soc_config->tdp_pl4 = DIV_ROUND_UP(limits[i].pl4_power,
+									MILLIWATTS_TO_WATTS);
+			printk(BIOS_INFO, "Overriding power limits PL1 (%u, %u) PL2 (%u, %u) PL4 (%u)\n",
+					limits[i].pl1_min_power,
+					limits[i].pl1_max_power,
+					limits[i].pl2_min_power,
+					limits[i].pl2_max_power,
+					limits[i].pl4_power);
+		}
+	}
+}
+
+static const struct typec_aux_bias_pads pad_config = { GPP_E23, GPP_E22 };
+
+static const struct board_id_iom_port_config {
+	int board_id;
+	enum typec_port_index port;
+} port_config[] = {
+	{ ADL_P_LP4_1,	TYPE_C_PORT_2 },
+	{ ADL_P_LP4_2,	TYPE_C_PORT_2 },
+	{ ADL_P_DDR4_1,	TYPE_C_PORT_2 },
+	{ ADL_P_DDR4_2,	TYPE_C_PORT_2 },
+	{ ADL_P_LP5_1,	TYPE_C_PORT_2 },
+	{ ADL_P_LP5_2,	TYPE_C_PORT_2 },
+	{ ADL_M_LP4,	TYPE_C_PORT_1 },
+	{ ADL_M_LP5,	TYPE_C_PORT_0 },
+};
+
+static void variant_update_typec_init_config(void)
+{
+	/* Skip filling aux bias gpio pads for Windows SKUs */
+	if (!(CONFIG(BOARD_INTEL_ADLRVP_P_EXT_EC) || CONFIG(BOARD_INTEL_ADLRVP_RPL_EXT_EC)))
+		return;
+
+	config_t *config = config_of_soc();
+	int board_id = get_board_id();
+	for (int i = 0; i < ARRAY_SIZE(port_config); i++) {
+		if (board_id != port_config[i].board_id)
+			continue;
+
+		memcpy(&config->typec_aux_bias_pads[port_config[i].port], &pad_config,
+			sizeof(pad_config));
+	}
+}
+
+void variant_devtree_update(void)
+{
+	variant_update_power_limits();
+	variant_update_typec_init_config();
+}
diff --git a/src/mainboard/siemens/mc_rpl/romstage_fsp_params.c b/src/mainboard/siemens/mc_rpl/romstage_fsp_params.c
new file mode 100644
index 0000000000..46640b6aad
--- /dev/null
+++ b/src/mainboard/siemens/mc_rpl/romstage_fsp_params.c
@@ -0,0 +1,112 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <console/console.h>
+#include <fsp/api.h>
+#include <soc/romstage.h>
+#include <spd_bin.h>
+#include <soc/meminit.h>
+#include <baseboard/variants.h>
+#include "board_id.h"
+
+#define SPD_ID_MASK 0x7
+
+static size_t get_spd_index(void)
+{
+	uint8_t board_id = get_board_id();
+	size_t spd_index;
+
+	printk(BIOS_INFO, "board id is 0x%x\n", board_id);
+
+	spd_index = board_id & SPD_ID_MASK;
+
+	printk(BIOS_INFO, "SPD index is 0x%x\n", (unsigned int)spd_index);
+	return spd_index;
+}
+
+/*
+ * ADL-P silicon can support 7 SRC CLK's and 10 CLKREQ signals. Out of 7 SRCCLK's
+ * 3 will be used for CPU, the rest are for PCH. If more than 4 PCH devices are
+ * connected on the platform, an external differential buffer chip needs to be placed at
+ * the platform level.
+ *
+ * GEN3_EXTERNAL_CLOCK_BUFFER Kconfig is selected for ADL-P RVP (not applicable for
+ * ADL-M/N RVP)
+ *
+ * CONFIG_CLKSRC_FOR_EXTERNAL_BUFFER provides the CLKSRC that feed clock to discrete
+ * buffer for further distribution to platform.
+ */
+static void configure_external_clksrc(FSP_M_CONFIG *m_cfg)
+{
+	for (unsigned int i = CONFIG_MAX_PCIE_CLOCK_SRC; i < CONFIG_MAX_PCIE_CLOCK_REQ; i++)
+		m_cfg->PcieClkSrcUsage[i] = CONFIG_CLKSRC_FOR_EXTERNAL_BUFFER;
+}
+
+__weak void rpl_memory_params(FSPM_UPD *memupd)
+{
+}
+
+void mainboard_memory_init_params(FSPM_UPD *memupd)
+{
+	FSP_M_CONFIG *m_cfg = &memupd->FspmConfig;
+	const struct mb_cfg *mem_config = variant_memory_params();
+	int board_id = get_board_id();
+
+	/*
+	 * Set Raptor Lake specific new upds that Alder Lake doesn't have.
+	 * This can be removed when Alder Lake and Raptor Lake FSP headers align.
+	 */
+	rpl_memory_params(memupd);
+
+	/*
+	 * Alder Lake common meminit block driver considers bus width to be 128-bit and
+	 * populates the meminit data accordingly. Alder Lake-N has single memory controller
+	 * with 64-bit bus width. By setting half_populated to true, only the bottom half is
+	 * populated.
+	 * TODO: Implement __weak variant_is_half_populated(void) function.
+	 */
+	const bool half_populated = (CONFIG(BOARD_INTEL_ADLRVP_N_EXT_EC)
+			 || CONFIG(BOARD_INTEL_ADLRVP_N));
+
+	const struct mem_spd memory_down_spd_info = {
+		.topo = MEM_TOPO_MEMORY_DOWN,
+		.cbfs_index = get_spd_index(),
+	};
+
+	const struct mem_spd dimm_module_spd_info = {
+		.topo = MEM_TOPO_DIMM_MODULE,
+		.smbus = {
+			[0] = {
+				.addr_dimm[0] = 0x50,
+				.addr_dimm[1] = 0x51,
+			},
+			[1] = {
+				.addr_dimm[0] = 0x52,
+				.addr_dimm[1] = 0x53,
+			},
+		},
+	};
+
+	switch (board_id) {
+	case ADL_P_DDR4_1:
+	case ADL_P_DDR4_2:
+	case ADL_P_DDR5_1:
+		memcfg_init(memupd, mem_config, &dimm_module_spd_info, half_populated);
+		break;
+	case ADL_P_DDR5_2:
+	case ADL_P_LP4_1:
+	case ADL_P_LP4_2:
+	case ADL_P_LP5_1:
+	case ADL_P_LP5_2:
+	case ADL_M_LP4:
+	case ADL_M_LP5:
+	case ADL_N_LP5:
+		memcfg_init(memupd, mem_config, &memory_down_spd_info, half_populated);
+		break;
+	default:
+		die("Unknown board id = 0x%x\n", board_id);
+		break;
+	}
+
+	if (CONFIG(GEN3_EXTERNAL_CLOCK_BUFFER))
+		configure_external_clksrc(m_cfg);
+}
diff --git a/src/mainboard/siemens/mc_rpl/smihandler.c b/src/mainboard/siemens/mc_rpl/smihandler.c
new file mode 100644
index 0000000000..a3b43231ec
--- /dev/null
+++ b/src/mainboard/siemens/mc_rpl/smihandler.c
@@ -0,0 +1,30 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <cpu/x86/smm.h>
+#include <ec/google/chromeec/smm.h>
+#include <intelblocks/smihandler.h>
+#include <baseboard/ec.h>
+
+void mainboard_smi_espi_handler(void)
+{
+	if (!CONFIG(EC_GOOGLE_CHROMEEC))
+		return;
+
+	chromeec_smi_process_events();
+}
+
+void mainboard_smi_sleep(u8 slp_typ)
+{
+	if (!CONFIG(EC_GOOGLE_CHROMEEC))
+		return;
+
+	chromeec_smi_sleep(slp_typ, MAINBOARD_EC_S3_WAKE_EVENTS, MAINBOARD_EC_S5_WAKE_EVENTS);
+}
+
+int mainboard_smi_apmc(u8 apmc)
+{
+	if (CONFIG(EC_GOOGLE_CHROMEEC))
+		chromeec_smi_apmc(apmc, MAINBOARD_EC_SCI_EVENTS, MAINBOARD_EC_SMI_EVENTS);
+
+	return 0;
+}
diff --git a/src/mainboard/siemens/mc_rpl/spd/Makefile.mk b/src/mainboard/siemens/mc_rpl/spd/Makefile.mk
new file mode 100644
index 0000000000..f503b6d959
--- /dev/null
+++ b/src/mainboard/siemens/mc_rpl/spd/Makefile.mk
@@ -0,0 +1,10 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
+SPD_SOURCES =  adlrvp_lp4	# 0b000
+SPD_SOURCES += empty		# 0b001
+SPD_SOURCES += empty		# 0b002
+SPD_SOURCES += adlrvp_lp5	# 0b003
+SPD_SOURCES += empty		# 0b004
+SPD_SOURCES += empty		# 0b005
+SPD_SOURCES += adlrvp_ddr5_mr	# 0b006
+SPD_SOURCES += adlrvp_n_lp5	# 0b007
diff --git a/src/mainboard/siemens/mc_rpl/spd/adlrvp_ddr5_mr.spd.hex b/src/mainboard/siemens/mc_rpl/spd/adlrvp_ddr5_mr.spd.hex
new file mode 100644
index 0000000000..80ef521cfa
--- /dev/null
+++ b/src/mainboard/siemens/mc_rpl/spd/adlrvp_ddr5_mr.spd.hex
@@ -0,0 +1,32 @@
+30 08 12 03 04 00 20 62 00 00 00 00 60 00 00 00
+00 00 00 00 A1 01 E8 03 72 15 00 00 00 00 1E 41
+1E 41 1E 41 00 7D 1E BE 30 75 27 01 A0 00 82 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 47 AE
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+08 00 C2 C4 80 00 80 B3 80 11 00 00 00 00 00 00
+00 00 80 B3 80 11 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 0F 10 00 01 01 22 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 9C AD
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
diff --git a/src/mainboard/siemens/mc_rpl/spd/adlrvp_lp4.spd.hex b/src/mainboard/siemens/mc_rpl/spd/adlrvp_lp4.spd.hex
new file mode 100644
index 0000000000..e1d338edbc
--- /dev/null
+++ b/src/mainboard/siemens/mc_rpl/spd/adlrvp_lp4.spd.hex
@@ -0,0 +1,32 @@
+23 11 11 0E 15 21 B5 08 00 40 00 00 0A 01 00 00
+48 00 04 FF 92 55 00 00 8C 00 90 A8 90 C0 08 60
+04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 7F E1 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 55 00 00 00 20 20 20 20 20 20 20
+20 20 20 20 20 20 20 20 20 20 20 20 20 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
diff --git a/src/mainboard/siemens/mc_rpl/spd/adlrvp_lp5.spd.hex b/src/mainboard/siemens/mc_rpl/spd/adlrvp_lp5.spd.hex
new file mode 100644
index 0000000000..2f2a31a33d
--- /dev/null
+++ b/src/mainboard/siemens/mc_rpl/spd/adlrvp_lp5.spd.hex
@@ -0,0 +1,32 @@
+23 10 13 0E 15 1A 95 08 00 40 00 00 02 01 00 00
+48 00 0A FF 92 55 05 00 AA 00 98 A8 90 90 06 C0
+03 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 7F 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 20 00 00 00 20 20 20 20 20 20 20
+20 20 20 20 20 20 20 20 20 20 20 20 20 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
diff --git a/src/mainboard/siemens/mc_rpl/spd/adlrvp_n_lp5.spd.hex b/src/mainboard/siemens/mc_rpl/spd/adlrvp_n_lp5.spd.hex
new file mode 100644
index 0000000000..88a1f1f473
--- /dev/null
+++ b/src/mainboard/siemens/mc_rpl/spd/adlrvp_n_lp5.spd.hex
@@ -0,0 +1,32 @@
+23 10 13 0E 15 1A B5 08 00 40 00 00 0A 01 00 00
+48 00 0A FF 92 55 05 00 AA 00 90 A8 90 90 06 C0
+03 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 7F 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 20 00 00 00 20 20 20 20 20 20 20
+20 20 20 20 20 20 20 20 20 20 20 20 20 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
diff --git a/src/mainboard/siemens/mc_rpl/spd/empty.spd.hex b/src/mainboard/siemens/mc_rpl/spd/empty.spd.hex
new file mode 100644
index 0000000000..67b46cd239
--- /dev/null
+++ b/src/mainboard/siemens/mc_rpl/spd/empty.spd.hex
@@ -0,0 +1,32 @@
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 80 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 80 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
diff --git a/src/mainboard/siemens/mc_rpl/variants/mc_rpl1/overridetree.cb b/src/mainboard/siemens/mc_rpl/variants/mc_rpl1/overridetree.cb
new file mode 100644
index 0000000000..8747164f32
--- /dev/null
+++ b/src/mainboard/siemens/mc_rpl/variants/mc_rpl1/overridetree.cb
@@ -0,0 +1,7 @@
+chip soc/intel/alderlake
+	# Disable package C state demotion on Raptorlake as a W/A for S0ix issues
+	# seen on J0 and Q0 SKUs
+	register "disable_package_c_state_demotion" = "true"
+
+	device domain 0 on end
+end

From e0209799932395a246d6b31d892cf49d51e85617 Mon Sep 17 00:00:00 2001
From: Werner Zeh <werner.zeh@siemens.com>
Date: Wed, 14 May 2025 10:37:11 +0200
Subject: [PATCH 1086/3886] mb/siemens/mc_rpl: Adjust the flash map file

Rename chromeos.fmd to mc_rpl.fmd and adjust the flash layout settings
to match the needs of this board. There is e.g. no A/B scheme used and
CSME stitching is done externally, therefore no detailed CSME partitions
are required at all.

Change-Id: I6389960d816c5f1a4690a965961301d3797305ff
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87665
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
---
 src/mainboard/siemens/mc_rpl/Kconfig      |  5 ++-
 src/mainboard/siemens/mc_rpl/chromeos.fmd | 54 -----------------------
 src/mainboard/siemens/mc_rpl/mc_rpl.fmd   | 14 ++++++
 3 files changed, 18 insertions(+), 55 deletions(-)
 delete mode 100644 src/mainboard/siemens/mc_rpl/chromeos.fmd
 create mode 100644 src/mainboard/siemens/mc_rpl/mc_rpl.fmd

diff --git a/src/mainboard/siemens/mc_rpl/Kconfig b/src/mainboard/siemens/mc_rpl/Kconfig
index 698df3c4d0..b1f7262681 100644
--- a/src/mainboard/siemens/mc_rpl/Kconfig
+++ b/src/mainboard/siemens/mc_rpl/Kconfig
@@ -2,7 +2,7 @@
 
 config BOARD_SIEMENS_BASEBOARD_MC_RPL
 	def_bool n
-	select BOARD_ROMSIZE_KB_32768
+	select BOARD_ROMSIZE_KB_16384
 	select CPU_INTEL_SOCKET_LGA1700
 	select DRIVERS_I2C_GENERIC
 	select DRIVERS_I2C_HID
@@ -79,6 +79,9 @@ config DEVICETREE
 config OVERRIDE_DEVICETREE
 	default "variants/\$(CONFIG_VARIANT_DIR)/overridetree.cb"
 
+config FMDFILE
+	default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/mc_rpl.fmd"
+
 choice
 	prompt "ON BOARD EC"
 	default MC_RPL_CHROME_EC if BOARD_SIEMENS_MC_RPL1
diff --git a/src/mainboard/siemens/mc_rpl/chromeos.fmd b/src/mainboard/siemens/mc_rpl/chromeos.fmd
deleted file mode 100644
index 0e8d321f85..0000000000
--- a/src/mainboard/siemens/mc_rpl/chromeos.fmd
+++ /dev/null
@@ -1,54 +0,0 @@
-FLASH 32M {
-	SI_ALL 6M {
-		SI_DESC 4K
-		SI_EC 512K
-		SI_ME {
-			CSE_LAYOUT 8K
-			CSE_RO 1588K
-			CSE_DATA 512K
-			# 64-KiB aligned to optimize RW erases during CSE update.
-			CSE_RW 3520K
-		}
-	}
-	SI_BIOS 26M {
-		RW_SECTION_A 8M {
-			VBLOCK_A 64K
-			FW_MAIN_A(CBFS)
-			RW_FWID_A 64
-		}
-		RW_LEGACY(CBFS) 1M
-		RW_MISC 1M {
-			UNIFIED_MRC_CACHE(PRESERVE) 192K {
-				RECOVERY_MRC_CACHE 64K
-				RW_MRC_CACHE 128K
-			}
-			RW_ELOG(PRESERVE) 16K
-			RW_SHARED 16K {
-				SHARED_DATA 8K
-				VBLOCK_DEV 8K
-			}
-			RW_VPD(PRESERVE) 8K
-			RW_NVRAM(PRESERVE) 24K
-		}
-		# This section starts at the 16M boundary in SPI flash.
-		# ADL does not support a region crossing this boundary,
-		# because the SPI flash is memory-mapped into two non-
-		# contiguous windows.
-		RW_SECTION_B 8M {
-			VBLOCK_B 64K
-			FW_MAIN_B(CBFS)
-			RW_FWID_B 64
-		}
-		# Make WP_RO region align with SPI vendor
-		# memory protected range specification.
-		WP_RO 8M {
-			RO_VPD(PRESERVE) 16K
-			RO_SECTION {
-				FMAP 2K
-				RO_FRID 64
-				GBB@4K 448K
-				COREBOOT(CBFS)
-			}
-		}
-	}
-}
diff --git a/src/mainboard/siemens/mc_rpl/mc_rpl.fmd b/src/mainboard/siemens/mc_rpl/mc_rpl.fmd
new file mode 100644
index 0000000000..ddb30df8aa
--- /dev/null
+++ b/src/mainboard/siemens/mc_rpl/mc_rpl.fmd
@@ -0,0 +1,14 @@
+FLASH CONFIG_ROM_SIZE {
+	SI_ALL 5M {
+		SI_DESC 4K
+		SI_ME 5116K
+	}
+	SI_BIOS 11M {
+		FMAP 2K
+		UNIFIED_MRC_CACHE(PRESERVE) 192K {
+			RECOVERY_MRC_CACHE 64K
+			RW_MRC_CACHE 128K
+		}
+		COREBOOT(CBFS)
+	}
+}

From 8fdf8694e3e270fc47f682a5587b1af03837372b Mon Sep 17 00:00:00 2001
From: Werner Zeh <werner.zeh@siemens.com>
Date: Wed, 14 May 2025 10:47:08 +0200
Subject: [PATCH 1087/3886] mb/siemens/mc_rpl: Remove Chrome OS and EC as they
 are not used

This mainboard neither uses Chrome OS nor has any embedded controller
available. This patch removes all references from the build in this
regard. This also requires some refactoring in board_id.c.

Change-Id: If834480fbdac4b4843c265a257d3a77678f56aab
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87666
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/siemens/mc_rpl/Kconfig       | 58 +---------------------
 src/mainboard/siemens/mc_rpl/Makefile.mk   |  6 ---
 src/mainboard/siemens/mc_rpl/board_id.c    |  8 +--
 src/mainboard/siemens/mc_rpl/board_id.h    |  5 --
 src/mainboard/siemens/mc_rpl/chromeos.c    | 50 -------------------
 src/mainboard/siemens/mc_rpl/devicetree.cb |  6 ---
 src/mainboard/siemens/mc_rpl/ec.c          | 19 -------
 7 files changed, 3 insertions(+), 149 deletions(-)
 delete mode 100644 src/mainboard/siemens/mc_rpl/chromeos.c
 delete mode 100644 src/mainboard/siemens/mc_rpl/ec.c

diff --git a/src/mainboard/siemens/mc_rpl/Kconfig b/src/mainboard/siemens/mc_rpl/Kconfig
index b1f7262681..4c04775b09 100644
--- a/src/mainboard/siemens/mc_rpl/Kconfig
+++ b/src/mainboard/siemens/mc_rpl/Kconfig
@@ -16,52 +16,26 @@ config BOARD_SIEMENS_BASEBOARD_MC_RPL
 	select HAVE_ACPI_RESUME
 	select HAVE_ACPI_TABLES
 	select HAVE_SPD_IN_CBFS
-	select MAINBOARD_HAS_CHROMEOS
 	select SOC_INTEL_COMMON_BLOCK_IPU
 	select SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES
+	select SOC_INTEL_CSE_LITE_SKU
 
 
 config BOARD_SIEMENS_MC_RPL1
 	select BOARD_SIEMENS_BASEBOARD_MC_RPL
 	select DRIVERS_UART_8250IO
 	select GEN3_EXTERNAL_CLOCK_BUFFER
-	select MAINBOARD_USES_IFD_EC_REGION
 	select SOC_INTEL_ALDERLAKE_PCH_P
 	select SOC_INTEL_RAPTORLAKE
 
 if BOARD_SIEMENS_BASEBOARD_MC_RPL
 
-config SOC_INTEL_CSE_LITE_SKU
-	bool "Use CSE Lite firmware"
-	default y if MC_RPL_CHROME_EC
-	help
-	  Enable if CSE Lite firmware is used in your build. It is commonly
-	  used in Chrome boards (chromebooks, chromeboxes, ...).
-	  But since ADL RVP build can be used with or without CSE Lite firmware
-	  it is a configurable option. Alderlake RVP boards usually don't use
-	  an CSE Lite firmware, but are still very likely to use it in case
-	  ChromeEC is used.
-
-config CHROMEOS
-	select GBB_FLAG_FORCE_DEV_SWITCH_ON
-	select GBB_FLAG_FORCE_DEV_BOOT_USB
-	select GBB_FLAG_FORCE_DEV_BOOT_ALTFW
-	select GBB_FLAG_FORCE_MANUAL_RECOVERY
-	select GBB_FLAG_DISABLE_PD_SOFTWARE_SYNC
-	select HAS_RECOVERY_MRC_CACHE
-
 config MAINBOARD_DIR
 	default "siemens/mc_rpl"
 
 config VARIANT_DIR
 	default "mc_rpl1" if BOARD_SIEMENS_MC_RPL1
 
-config GBB_HWID
-	string
-	depends on CHROMEOS
-	default "ADLRVPN TEST 7673" if BOARD_INTEL_ADLRVP_N || BOARD_INTEL_ADLRVP_N_EXT_EC
-	default "ADLRVPP TEST 2418"
-
 config MAINBOARD_PART_NUMBER
 	default "MC RPL1" if BOARD_SIEMENS_MC_RPL1
 
@@ -82,32 +56,6 @@ config OVERRIDE_DEVICETREE
 config FMDFILE
 	default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/mc_rpl.fmd"
 
-choice
-	prompt "ON BOARD EC"
-	default MC_RPL_CHROME_EC if BOARD_SIEMENS_MC_RPL1
-	help
-	  This option allows you to select the on board EC to use.
-	  Select whether the board has Intel EC or Chrome EC
-
-config MC_RPL_CHROME_EC
-	bool "Chrome EC"
-	select EC_GOOGLE_CHROMEEC
-	select EC_GOOGLE_CHROMEEC_ESPI
-	select EC_GOOGLE_CHROMEEC_BOARDID
-	select EC_ACPI
-	select EC_GOOGLE_CHROMEEC_LPC
-
-config MC_RPL_INTEL_EC
-	bool "Intel EC"
-	select EC_ACPI
-endchoice
-
-config VBOOT
-	select VBOOT_LID_SWITCH
-	select VBOOT_MOCK_SECDATA if BOARD_INTEL_ADLRVP_P_EXT_EC || BOARD_INTEL_ADLRVP_N_EXT_EC
-	select EC_GOOGLE_CHROMEEC_SWITCHES if MC_RPL_CHROME_EC
-	select VBOOT_EARLY_EC_SYNC if BOARD_INTEL_ADLRVP_N_EXT_EC
-
 config UART_FOR_CONSOLE
 	int
 	default 0
@@ -118,10 +66,6 @@ config DRIVER_TPM_SPI_BUS
 config USE_PM_ACPI_TIMER
 	default n if BOARD_SIEMENS_MC_RPL1
 
-config TPM_TIS_ACPI_INTERRUPT
-	int
-	default 67 if BOARD_INTEL_ADLRVP_RPL_EXT_EC # GPE0_DW2_3 (GPP_E3)
-
 config GEN3_EXTERNAL_CLOCK_BUFFER
 	bool
 	depends on SOC_INTEL_ALDERLAKE_PCH_P
diff --git a/src/mainboard/siemens/mc_rpl/Makefile.mk b/src/mainboard/siemens/mc_rpl/Makefile.mk
index b63953c0e0..00f7ea73e3 100644
--- a/src/mainboard/siemens/mc_rpl/Makefile.mk
+++ b/src/mainboard/siemens/mc_rpl/Makefile.mk
@@ -3,7 +3,6 @@
 subdirs-y += spd
 
 bootblock-y += bootblock.c
-bootblock-$(CONFIG_CHROMEOS) += chromeos.c
 ifeq ($(CONFIG_SOC_INTEL_ALDERLAKE_PCH_N),y)
 bootblock-y += early_gpio_n.c
 ramstage-y += gpio_n.c
@@ -12,9 +11,6 @@ bootblock-y += early_gpio.c
 ramstage-y += gpio.c
 endif
 
-verstage-$(CONFIG_CHROMEOS) += chromeos.c
-
-romstage-$(CONFIG_CHROMEOS) += chromeos.c
 romstage-y += romstage_fsp_params.c
 romstage-y += board_id.c
 romstage-y += memory.c
@@ -22,8 +18,6 @@ ifeq ($(CONFIG_BOARD_INTEL_ADLRVP_RPL_EXT_EC),y)
 romstage-y += memory_rpl.c
 endif
 
-ramstage-$(CONFIG_CHROMEOS) += chromeos.c
-ramstage-y += ec.c
 ramstage-y += mainboard.c
 ramstage-y += board_id.c
 ramstage-$(CONFIG_FW_CONFIG) += fw_config.c
diff --git a/src/mainboard/siemens/mc_rpl/board_id.c b/src/mainboard/siemens/mc_rpl/board_id.c
index 02445f2f3a..ba154243a9 100644
--- a/src/mainboard/siemens/mc_rpl/board_id.c
+++ b/src/mainboard/siemens/mc_rpl/board_id.c
@@ -1,15 +1,11 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
 #include <boardid.h>
-#include <ec/acpi/ec.h>
-#include <ec/google/chromeec/ec.h>
 #include <types.h>
 #include "board_id.h"
 
-/* Get Board ID via EC I/O port write/read */
+/* Get Board ID */
 int get_board_id(void)
 {
-	static int id = 1;
-
-	return (id & BOARD_ID_MASK);
+	return 1;
 }
diff --git a/src/mainboard/siemens/mc_rpl/board_id.h b/src/mainboard/siemens/mc_rpl/board_id.h
index 2988127e9b..1408573b1b 100644
--- a/src/mainboard/siemens/mc_rpl/board_id.h
+++ b/src/mainboard/siemens/mc_rpl/board_id.h
@@ -3,11 +3,6 @@
 #ifndef _MAINBOARD_COMMON_BOARD_ID_H_
 #define _MAINBOARD_COMMON_BOARD_ID_H_
 
-/* Board/FAB ID Command */
-#define EC_FAB_ID_CMD	0x0d
-/* Bit 5:0 for Board ID */
-#define BOARD_ID_MASK	0x3f
-
 /*
  * Returns board information (board id[15:8] and
  * Fab info[7:0]) on success and < 0 on error
diff --git a/src/mainboard/siemens/mc_rpl/chromeos.c b/src/mainboard/siemens/mc_rpl/chromeos.c
deleted file mode 100644
index 4c2d1e516f..0000000000
--- a/src/mainboard/siemens/mc_rpl/chromeos.c
+++ /dev/null
@@ -1,50 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <baseboard/gpio.h>
-#include <bootmode.h>
-#include <boot/coreboot_tables.h>
-#include <gpio.h>
-#include <types.h>
-
-void fill_lb_gpios(struct lb_gpios *gpios)
-{
-	struct lb_gpio chromeos_gpios[] = {
-		{-1, ACTIVE_HIGH, get_lid_switch(), "lid"},
-		{-1, ACTIVE_HIGH, 0, "power"},
-		{-1, ACTIVE_HIGH, gfx_get_init_done(), "oprom"},
-		{GPIO_EC_IN_RW, ACTIVE_HIGH, gpio_get(GPIO_EC_IN_RW), "EC in RW"},
-	};
-	if (CONFIG(BOARD_INTEL_ADLRVP_P_EXT_EC) || CONFIG(BOARD_INTEL_ADLRVP_N_EXT_EC) ||
-	    CONFIG(BOARD_INTEL_ADLRVP_RPL_EXT_EC))
-		lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios));
-	else
-		lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios) - 1);
-}
-
-#if !CONFIG(EC_GOOGLE_CHROMEEC_SWITCHES)
-int get_lid_switch(void)
-{
-	/* Lid always open */
-	return 1;
-}
-
-int get_recovery_mode_switch(void)
-{
-	return 0;
-}
-#endif /*!CONFIG(EC_GOOGLE_CHROMEEC_SWITCHES) */
-
-int get_write_protect_state(void)
-{
-	/* No write protect */
-	return 0;
-}
-
-#if (CONFIG(BOARD_INTEL_ADLRVP_P_EXT_EC) || CONFIG(BOARD_INTEL_ADLRVP_N_EXT_EC) ||\
-	 CONFIG(BOARD_INTEL_ADLRVP_RPL_EXT_EC))
-int get_ec_is_trusted(void)
-{
-	/* EC is trusted if not in RW. */
-	return !gpio_get(GPIO_EC_IN_RW);
-}
-#endif
diff --git a/src/mainboard/siemens/mc_rpl/devicetree.cb b/src/mainboard/siemens/mc_rpl/devicetree.cb
index 031b2f059b..9bd0d15cbd 100644
--- a/src/mainboard/siemens/mc_rpl/devicetree.cb
+++ b/src/mainboard/siemens/mc_rpl/devicetree.cb
@@ -41,12 +41,6 @@ chip soc/intel/alderlake
 	register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC0)"	# USB3/2 Type A port3
 	register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)"	# M.2 WWAN
 
-	# EC host command ranges are in 0x800-0x8ff & 0x200-0x20f
-	register "gen1_dec" = "0x00fc0801"
-	register "gen2_dec" = "0x000c0201"
-	# EC memory map range is 0x900-0x9ff
-	register "gen3_dec" = "0x00fc0901"
-
 	# Enable PCH PCIE RP 5 using CLK 2
 	register "pch_pcie_rp[PCH_RP(5)]" = "{
 		.clk_src = 2,
diff --git a/src/mainboard/siemens/mc_rpl/ec.c b/src/mainboard/siemens/mc_rpl/ec.c
deleted file mode 100644
index 14760017ef..0000000000
--- a/src/mainboard/siemens/mc_rpl/ec.c
+++ /dev/null
@@ -1,19 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <acpi/acpi.h>
-#include <ec/ec.h>
-#include <ec/google/chromeec/ec.h>
-#include <baseboard/ec.h>
-
-void mainboard_ec_init(void)
-{
-	const struct google_chromeec_event_info info = {
-		.log_events = MAINBOARD_EC_LOG_EVENTS,
-		.sci_events = MAINBOARD_EC_SCI_EVENTS,
-		.s3_wake_events = MAINBOARD_EC_S3_WAKE_EVENTS,
-		.s5_wake_events = MAINBOARD_EC_S5_WAKE_EVENTS,
-		.s0ix_wake_events = MAINBOARD_EC_S0IX_WAKE_EVENTS,
-	};
-
-	google_chromeec_events_init(&info, acpi_is_wakeup_s3());
-}

From 7fbea3175d7ed652a3711aa6130f36a64216a6fb Mon Sep 17 00:00:00 2001
From: Werner Zeh <werner.zeh@siemens.com>
Date: Wed, 14 May 2025 12:17:09 +0200
Subject: [PATCH 1088/3886] mb/siemens/mc_rpl: Remove unused gpio and
 devicetree files

Since this board comes with a fixed SoC (Raptor Lake with ADL-P PCH),
there is no need to have multiple different gpio configuration files and
devicetree files. This patch deletes the unneeded files and adopts
Makefile.mk to not use them.

Change-Id: Iced9d695e3f21dec260795bb651109ff9b2beb59
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87671
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
---
 src/mainboard/siemens/mc_rpl/Makefile.mk     |   7 +-
 src/mainboard/siemens/mc_rpl/devicetree_m.cb | 406 -------------------
 src/mainboard/siemens/mc_rpl/devicetree_n.cb | 403 ------------------
 src/mainboard/siemens/mc_rpl/early_gpio_m.c  | 142 -------
 src/mainboard/siemens/mc_rpl/early_gpio_n.c  |  30 --
 src/mainboard/siemens/mc_rpl/gpio_m.c        | 193 ---------
 src/mainboard/siemens/mc_rpl/gpio_n.c        | 239 -----------
 7 files changed, 1 insertion(+), 1419 deletions(-)
 delete mode 100644 src/mainboard/siemens/mc_rpl/devicetree_m.cb
 delete mode 100644 src/mainboard/siemens/mc_rpl/devicetree_n.cb
 delete mode 100644 src/mainboard/siemens/mc_rpl/early_gpio_m.c
 delete mode 100644 src/mainboard/siemens/mc_rpl/early_gpio_n.c
 delete mode 100644 src/mainboard/siemens/mc_rpl/gpio_m.c
 delete mode 100644 src/mainboard/siemens/mc_rpl/gpio_n.c

diff --git a/src/mainboard/siemens/mc_rpl/Makefile.mk b/src/mainboard/siemens/mc_rpl/Makefile.mk
index 00f7ea73e3..e13158b89f 100644
--- a/src/mainboard/siemens/mc_rpl/Makefile.mk
+++ b/src/mainboard/siemens/mc_rpl/Makefile.mk
@@ -3,14 +3,9 @@
 subdirs-y += spd
 
 bootblock-y += bootblock.c
-ifeq ($(CONFIG_SOC_INTEL_ALDERLAKE_PCH_N),y)
-bootblock-y += early_gpio_n.c
-ramstage-y += gpio_n.c
-else
 bootblock-y += early_gpio.c
-ramstage-y += gpio.c
-endif
 
+ramstage-y += gpio.c
 romstage-y += romstage_fsp_params.c
 romstage-y += board_id.c
 romstage-y += memory.c
diff --git a/src/mainboard/siemens/mc_rpl/devicetree_m.cb b/src/mainboard/siemens/mc_rpl/devicetree_m.cb
deleted file mode 100644
index 1ee0f324dc..0000000000
--- a/src/mainboard/siemens/mc_rpl/devicetree_m.cb
+++ /dev/null
@@ -1,406 +0,0 @@
-fw_config
-	field AUDIO 8 10
-		option NONE 0
-		option ADL_MAX98373_ALC5682I_I2S 1
-	end
-end
-chip soc/intel/alderlake
-
-	# GPE configuration
-	# Note that GPE events called out in ASL code rely on this
-	# route. i.e. If this route changes then the affected GPE
-	# offset bits also need to be changed.
-	register "pmc_gpe0_dw0" = "GPP_B"
-	register "pmc_gpe0_dw1" = "GPP_D"
-	register "pmc_gpe0_dw2" = "GPP_E"
-
-	# FSP configuration
-	register "usb2_ports[0]" = "USB2_PORT_MID(OC1)"	# Type-C port 0
-	register "usb2_ports[1]" = "USB2_PORT_MID(OC1)"	# Type-C port 1
-	register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # M.2 WLAN
-	register "usb2_ports[3]" = "USB2_PORT_MID(OC_SKIP)" # M.2 WWAN
-	register "usb2_ports[4]" = "USB2_PORT_MID(OC2)"	# Type-A port 1
-	register "usb2_ports[5]" = "USB2_PORT_MID(OC2)"	# Type-A port 2
-	register "usb2_ports[6]" = "USB2_PORT_MID(OC0)"	# USB3/2 Type A port1
-	register "usb2_ports[7]" = "USB2_PORT_MID(OC0)"	# USB3/2 Type A port2
-	register "usb2_ports[8]" = "USB2_PORT_MID(OC3)"	# USB3/2 Type A port3
-	register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth
-
-	register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC2)" # Type-A port 1
-	register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC2)" # Type-A port 2
-	register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # M.2 WWAN
-	register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # M.2 WLAN
-
-	# Sagv Configuration
-	register "sagv" = "SaGv_Enabled"
-
-	# Enable CNVi Bluetooth
-	register "cnvi_bt_core" = "true"
-
-	# EC host command ranges are in 0x800-0x8ff & 0x200-0x20f
-	register "gen1_dec" = "0x00fc0801"
-	register "gen2_dec" = "0x000c0201"
-	# EC memory map range is 0x900-0x9ff
-	register "gen3_dec" = "0x00fc0901"
-
-	#Enable PCH PCIE RP 4 using CLK 5
-	register "pch_pcie_rp[PCH_RP(4)]" = "{
-		.clk_src = 5,
-		.clk_req = 5,
-		.flags = PCIE_RP_CLK_REQ_DETECT | PCIE_RP_LTR,
-		.PcieRpL1Substates = L1_SS_L1_2,
-	}"
-
-	# Enable PCH PCIE RP 5 using CLK 2
-	register "pch_pcie_rp[PCH_RP(5)]" = "{
-		.clk_src = 2,
-		.clk_req = 2,
-		.flags = PCIE_RP_CLK_REQ_DETECT | PCIE_RP_LTR,
-		.PcieRpL1Substates = L1_SS_L1_2,
-	}"
-
-	# Enable PCH PCIE RP 9 using CLK 3
-	register "pch_pcie_rp[PCH_RP(9)]" = "{
-		.clk_src = 3,
-		.clk_req = 3,
-		.flags = PCIE_RP_CLK_REQ_DETECT | PCIE_RP_LTR,
-		.PcieRpL1Substates = L1_SS_L1_2,
-	}"
-
-	#Enable PCH PCIE RP 10 using CLK 1
-	register "pch_pcie_rp[PCH_RP(10)]" = "{
-		.clk_src = 1,
-		.clk_req = 1,
-		.flags = PCIE_RP_CLK_REQ_DETECT | PCIE_RP_LTR,
-		.PcieRpL1Substates = L1_SS_L1_2,
-	}"
-
-	# Hybrid storage mode
-	register "hybrid_storage_mode" = "true"
-
-	# Enable CPU PCIE RP 1 using CLK 0
-	register "cpu_pcie_rp[CPU_RP(1)]" = "{
-		.clk_req = 0,
-		.clk_src = 0,
-		.flags = PCIE_RP_LTR | PCIE_RP_AER,
-	}"
-
-	# Enable EDP in PortA
-	register "ddi_portA_config" = "1"
-	# Enable HDMI in Port B
-	register "ddi_ports_config" = "{
-		[DDI_PORT_B] = DDI_ENABLE_HPD | DDI_ENABLE_DDC,
-	}"
-
-	# TCSS USB3
-	register "tcss_aux_ori" = "0"
-
-	register "s0ix_enable" = "true"
-
-	register "serial_io_i2c_mode" = "{
-		[PchSerialIoIndexI2C0] = PchSerialIoPci,
-		[PchSerialIoIndexI2C1] = PchSerialIoPci,
-		[PchSerialIoIndexI2C2] = PchSerialIoDisabled,
-		[PchSerialIoIndexI2C3] = PchSerialIoDisabled,
-		[PchSerialIoIndexI2C4] = PchSerialIoDisabled,
-		[PchSerialIoIndexI2C5] = PchSerialIoPci,
-	}"
-
-	register "serial_io_gspi_mode" = "{
-		[PchSerialIoIndexGSPI0] = PchSerialIoPci,
-		[PchSerialIoIndexGSPI1] = PchSerialIoPci,
-		[PchSerialIoIndexGSPI2] = PchSerialIoDisabled,
-		[PchSerialIoIndexGSPI3] = PchSerialIoDisabled,
-	}"
-
-	register "serial_io_gspi_cs_mode" = "{
-		[PchSerialIoIndexGSPI0] = 0,
-		[PchSerialIoIndexGSPI1] = 1,
-		[PchSerialIoIndexGSPI2] = 0,
-		[PchSerialIoIndexGSPI3] = 0,
-	}"
-
-	register "serial_io_gspi_cs_state" = "{
-		[PchSerialIoIndexGSPI0] = 0,
-		[PchSerialIoIndexGSPI1] = 0,
-		[PchSerialIoIndexGSPI2] = 0,
-		[PchSerialIoIndexGSPI3] = 0,
-	}"
-
-	register "serial_io_uart_mode" = "{
-		[PchSerialIoIndexUART0] = PchSerialIoSkipInit,
-		[PchSerialIoIndexUART1] = PchSerialIoDisabled,
-		[PchSerialIoIndexUART2] = PchSerialIoDisabled,
-	}"
-
-	# HD Audio
-	register "pch_hda_dsp_enable" = "1"
-	register "pch_hda_idisp_link_tmode" = "HDA_TMODE_8T"
-	register "pch_hda_idisp_link_frequency" = "HDA_LINKFREQ_96MHZ"
-	register "pch_hda_idisp_codec_enable" = "1"
-
-	# Intel Common SoC Config
-	register "common_soc_config" = "{
-		.gspi[1] = {
-			.speed_mhz = 1,
-			.early_init = 1,
-		},
-		.i2c[0] = {
-			.speed = I2C_SPEED_FAST,
-		},
-		.i2c[1] = {
-			.speed = I2C_SPEED_FAST,
-		},
-		.i2c[2] = {
-			.speed = I2C_SPEED_FAST,
-		},
-		.i2c[3] = {
-			.speed = I2C_SPEED_FAST,
-		},
-		.i2c[5] = {
-			.speed = I2C_SPEED_FAST,
-		},
-	}"
-
-	device domain 0 on
-		device ref pcie5_0 on end
-		device ref igpu on end
-		device ref dtt on end
-		device ref ipu on
-			chip drivers/intel/mipi_camera
-				register "acpi_uid" = "0x50000"
-				register "acpi_name" = ""IPU0""
-				register "device_type" = "INTEL_ACPI_CAMERA_CIO2"
-
-				register "cio2_num_ports" = "2"
-				register "cio2_lanes_used" = "{2,2}"
-				register "cio2_lane_endpoint[0]" = ""^I2C5.CAM1""
-				register "cio2_lane_endpoint[1]" = ""^I2C1.CAM0""
-				register "cio2_prt[0]" = "2"
-				register "cio2_prt[1]" = "1"
-				device generic 0 on end
-			end
-		end
-		device ref pcie4_0 on end
-		device ref pcie4_1 on end
-		device ref tbt_pcie_rp0 on end
-		device ref tbt_pcie_rp1 on end
-		device ref tcss_xhci on
-			chip drivers/usb/acpi
-				register "type" = "UPC_TYPE_HUB"
-				device ref tcss_root_hub on
-					chip drivers/usb/acpi
-						register "desc" = ""TypeC Port 1""
-						device ref tcss_usb3_port1 on end
-					end
-					chip drivers/usb/acpi
-						register "desc" = ""TypeC Port 2""
-						device ref tcss_usb3_port2 on end
-					end
-				end
-			end
-		end
-		device ref tcss_dma0 on end
-		device ref xhci on
-			chip drivers/usb/acpi
-				register "desc" = ""Root Hub""
-				register "type" = "UPC_TYPE_HUB"
-				device ref xhci_root_hub on
-					chip drivers/usb/acpi
-						register "desc" = ""Bluetooth""
-						register "type" = "UPC_TYPE_INTERNAL"
-						device ref usb2_port10 on end
-					end
-				end
-			end
-		end
-		device ref cnvi_wifi on
-			chip drivers/wifi/generic
-				register "wake" = "GPE0_PME_B0"
-				device generic 0 on end
-			end
-		end
-		device ref i2c0 on
-			chip drivers/i2c/generic
-				register "hid" = ""10EC5682""
-				register "name" = ""RT58""
-				register "desc" = ""Headset Codec""
-				register "irq" = "ACPI_IRQ_EDGE_HIGH(GPP_H3_IRQ)"
-				# Set the jd_src to RT5668_JD1 for jack detection
-				register "property_count" = "1"
-				register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER"
-				register "property_list[0].name" = ""realtek,jd-src""
-				register "property_list[0].integer" = "1"
-				device i2c 1a on
-					probe AUDIO ADL_MAX98373_ALC5682I_I2S
-				end
-			end
-			chip drivers/i2c/max98373
-				register "vmon_slot_no" = "0"
-				register "imon_slot_no" = "1"
-				register "uid" = "0"
-				register "desc" = ""Right Speaker Amp""
-				register "name" = ""MAXR""
-				device i2c 31 on
-					probe AUDIO ADL_MAX98373_ALC5682I_I2S
-				end
-			end
-			chip drivers/i2c/max98373
-				register "vmon_slot_no" = "2"
-				register "imon_slot_no" = "3"
-				register "uid" = "1"
-				register "desc" = ""Left Speaker Amp""
-				register "name" = ""MAXL""
-				device i2c 32 on
-					probe AUDIO ADL_MAX98373_ALC5682I_I2S
-				end
-			end
-			chip drivers/i2c/hid
-				register "generic.hid" = ""WACOM PWB-D893""
-				register "generic.desc" = ""WACOM Touchscreen""
-				register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_F18_IRQ)"
-				register "generic.probed" = "1"
-				register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_F17)"
-				register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_F7)"
-				register "generic.enable_delay_ms" = "1"
-				register "generic.reset_delay_ms" = "300"
-				register "generic.has_power_resource" = "1"
-				register "hid_desc_reg_offset" = "0x01"
-				device i2c 0a on end
-			end
-			chip drivers/i2c/hid
-				register "generic.hid" = ""ELAN0000""
-				register "generic.desc" = ""ELAN Touchpad""
-				register "generic.irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_D11_IRQ)"
-				register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_H1)"
-				register "generic.wake" = "GPE0_DW1_11"
-				register "generic.detect" = "1"
-				register "generic.has_power_resource" = "1"
-				device i2c 15 on end
-			end
-		end
-		device ref i2c1 on
-			chip drivers/intel/mipi_camera
-				register "acpi_hid" = ""OVTI5675""
-				register "acpi_uid" = "0"
-				register "acpi_name" = ""CAM0""
-				register "chip_name" = ""Ov 5675 Camera""
-				register "device_type" = "INTEL_ACPI_CAMERA_SENSOR"
-
-				register "ssdb.lanes_used" = "2"
-				register "ssdb.vcm_type" = "0x0C"
-				register "vcm_name" = ""VCM0""
-				register "num_freq_entries" = "1"
-				register "link_freq[0]" = "450000000"
-				register "remote_name" = ""IPU0""
-
-				register "has_power_resource" = "true"
-				#Controls
-				register "clk_panel.clks[0].clknum" = "0" #IMGCLKOUT_0
-				register "clk_panel.clks[0].freq" = "1" #19.2 Mhz
-				register "gpio_panel.gpio[0].gpio_num" = "GPP_B23" #power_enable
-				register "gpio_panel.gpio[1].gpio_num" = "GPP_R5" #reset
-
-				#_ON
-				register "on_seq.ops_cnt" = "4"
-				register "on_seq.ops[0]" = "SEQ_OPS_CLK_ENABLE(0, 0)"
-				register "on_seq.ops[1]" = "SEQ_OPS_GPIO_ENABLE(0, 2)"
-				register "on_seq.ops[2]" = "SEQ_OPS_GPIO_DISABLE(1, 1)"
-				register "on_seq.ops[3]" = "SEQ_OPS_GPIO_ENABLE(1, 1)"
-
-				#_OFF
-				register "off_seq.ops_cnt" = "3"
-				register "off_seq.ops[0]" = "SEQ_OPS_CLK_DISABLE(0, 0)"
-				register "off_seq.ops[1]" = "SEQ_OPS_GPIO_DISABLE(1, 0)"
-				register "off_seq.ops[2]" = "SEQ_OPS_GPIO_DISABLE(0, 0)"
-
-				device i2c 36 on end
-			end
-			chip drivers/intel/mipi_camera
-				register "acpi_uid" = "3"
-				register "acpi_name" = ""VCM0""
-				register "chip_name" = ""DW AF VCM""
-				register "device_type" = "INTEL_ACPI_CAMERA_VCM"
-
-				register "pr0" = ""\\_SB.PCI0.I2C1.CAM0.PRIC""
-				register "vcm_compat" = ""dongwoon,dw9714""
-
-				device i2c 0C on end
-			end
-		end
-		device ref i2c2 on end
-		device ref i2c3 on end
-		device ref heci1 on end
-		device ref sata on end
-		device ref i2c5 on
-			chip drivers/intel/mipi_camera
-				register "acpi_hid" = ""OVTI5675""
-				register "acpi_uid" = "0"
-				register "acpi_name" = ""CAM1""
-				register "chip_name" = ""Ov 5675 Camera""
-				register "device_type" = "INTEL_ACPI_CAMERA_SENSOR"
-
-				register "ssdb.lanes_used" = "2"
-				register "num_freq_entries" = "1"
-				register "link_freq[0]" = "450000000"
-				register "remote_name" = ""IPU0""
-
-				register "has_power_resource" = "true"
-				#Controls
-				register "clk_panel.clks[0].clknum" = "1" #IMGCLKOUT_1
-				register "clk_panel.clks[0].freq" = "1" #19.2 Mhz
-				register "gpio_panel.gpio[0].gpio_num" = "GPP_E16" #power_enable
-				register "gpio_panel.gpio[1].gpio_num" = "GPP_E15" #reset
-
-				#_ON
-				register "on_seq.ops_cnt" = "4"
-				register "on_seq.ops[0]" = "SEQ_OPS_CLK_ENABLE(0, 0)"
-				register "on_seq.ops[1]" = "SEQ_OPS_GPIO_ENABLE(0, 2)"
-				register "on_seq.ops[2]" = "SEQ_OPS_GPIO_DISABLE(1, 1)"
-				register "on_seq.ops[3]" = "SEQ_OPS_GPIO_ENABLE(1, 1)"
-
-				#_OFF
-				register "off_seq.ops_cnt" = "3"
-				register "off_seq.ops[0]" = "SEQ_OPS_CLK_DISABLE(0, 0)"
-				register "off_seq.ops[1]" = "SEQ_OPS_GPIO_DISABLE(1, 0)"
-				register "off_seq.ops[2]" = "SEQ_OPS_GPIO_DISABLE(0, 0)"
-
-				device i2c 36 on end
-			end
-		end
-		device ref pcie_rp1 on end
-		device ref pcie_rp3 on end # W/A to FSP issue
-		device ref pcie_rp4 on end # W/A to FSP issue
-		device ref pcie_rp5 on end
-		device ref pcie_rp6 on end
-		device ref pcie_rp8 on end
-		device ref pcie_rp9 on end
-		device ref pcie_rp10 on end
-		device ref uart0 on end
-		device ref gspi0 on end
-		device ref p2sb on end
-		device pci 1e.3 on
-			chip drivers/spi/acpi
-				register "hid" = "ACPI_DT_NAMESPACE_HID"
-				register "compat_string" = ""google,cr50""
-				register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_E3_IRQ)"
-				device spi 0 on end
-			end
-		end # GSPI1
-		device ref hda on
-			chip drivers/intel/soundwire
-				device generic 0 on
-					chip drivers/soundwire/alc711
-						# SoundWire Link 0 ID 1
-						register "desc" = ""Headset Codec""
-						register "alc711_address.version" = "SOUNDWIRE_VERSION_1_1"
-						register "alc711_address.class" = "MIPI_CLASS_NONE"
-						register "alc711_address.part_id" = "MIPI_DEV_ID_REALTEK_ALC711"
-						device generic 0.1 on end
-					end
-				end
-			end
-		end
-		device ref smbus on end
-	end
-end
diff --git a/src/mainboard/siemens/mc_rpl/devicetree_n.cb b/src/mainboard/siemens/mc_rpl/devicetree_n.cb
deleted file mode 100644
index 1eff9459d3..0000000000
--- a/src/mainboard/siemens/mc_rpl/devicetree_n.cb
+++ /dev/null
@@ -1,403 +0,0 @@
-chip soc/intel/alderlake
-
-	# GPE configuration
-	# Note that GPE events called out in ASL code rely on this
-	# route. i.e. If this route changes then the affected GPE
-	# offset bits also need to be changed.
-	register "pmc_gpe0_dw0" = "GPP_B"
-	register "pmc_gpe0_dw1" = "GPP_D"
-	register "pmc_gpe0_dw2" = "GPP_E"
-
-	# FSP configuration
-
-	# Enable CNVi BT
-	register "cnvi_bt_core" = "true"
-
-	# Sagv Configuration
-	register "sagv" = "SaGv_Enabled"
-
-	# Enable DPTF
-	register "dptf_enable" = "true"
-
-	# eMMC HS400
-	register "emmc_enable_hs400_mode" = "true"
-
-	register "usb2_ports[0]" = "USB2_PORT_MID(OC3)"		# Type-C Port1
-	register "usb2_ports[1]" = "USB2_PORT_MID(OC3)"		# Type-C Port2
-	register "usb2_ports[2]" = "USB2_PORT_MID(OC3)"		# FPS connector
-	register "usb2_ports[3]" = "USB2_PORT_MID(OC_SKIP)"	# M.2 WWAN
-	register "usb2_ports[4]" = "USB2_PORT_MID(OC3)"		# USB3/2 Type A port1
-	register "usb2_ports[5]" = "USB2_PORT_MID(OC1)"		# USB3/2 Type A port2
-	register "usb2_ports[6]" = "USB2_PORT_MID(OC1)"		# USB3/2 Type A port3
-	register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)"	# Type A/ M.2 WLAN
-	register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)"	# Bluetooth
-
-	register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC3)"	# USB3/2 Type A port1
-	register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC1)"	# USB3/2 Type A port2
-	register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC1)"	# USB3/2 Type A port3
-	register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)"	# M.2 WWAN
-
-	# EC host command ranges are in 0x800-0x8ff & 0x200-0x20f
-	register "gen1_dec" = "0x00fc0801"
-	register "gen2_dec" = "0x000c0201"
-	# EC memory map range is 0x900-0x9ff
-	register "gen3_dec" = "0x00fc0901"
-
-	# Enable PCH PCIE RP 7 using CLK 3
-	register "pch_pcie_rp[PCH_RP(7)]" = "{
-		.clk_src = 3,
-		.clk_req = 3,
-		.flags = PCIE_RP_CLK_REQ_DETECT,
-	}"
-
-	# Enable PCH PCIE RP 9 using CLK 0
-	register "pch_pcie_rp[PCH_RP(9)]" = "{
-		.clk_src = 0,
-		.clk_req = 0,
-		.flags = PCIE_RP_CLK_REQ_DETECT,
-	}"
-
-	register "sata_salp_support" = "0"
-
-	# Enable EDP in PortA
-	register "ddi_portA_config" = "1"
-	# Enable HDMI in Port B
-	register "ddi_ports_config" = "{
-		[DDI_PORT_B] = DDI_ENABLE_HPD | DDI_ENABLE_DDC,
-	}"
-
-	# TCSS USB3
-	register "tcss_aux_ori" = "4"
-	register "typec_aux_bias_pads[1]" = "{.pad_auxp_dc = GPP_E20, .pad_auxn_dc = GPP_E21}"
-
-	register "s0ix_enable" = "true"
-
-	register "serial_io_i2c_mode" = "{
-		[PchSerialIoIndexI2C0] = PchSerialIoPci,
-		[PchSerialIoIndexI2C1] = PchSerialIoPci,
-		[PchSerialIoIndexI2C2] = PchSerialIoPci,
-		[PchSerialIoIndexI2C3] = PchSerialIoPci,
-		[PchSerialIoIndexI2C4] = PchSerialIoDisabled,
-		[PchSerialIoIndexI2C5] = PchSerialIoPci,
-	}"
-
-	register "serial_io_gspi_mode" = "{
-		[PchSerialIoIndexGSPI0] = PchSerialIoPci,
-		[PchSerialIoIndexGSPI1] = PchSerialIoDisabled,
-		[PchSerialIoIndexGSPI2] = PchSerialIoDisabled,
-		[PchSerialIoIndexGSPI3] = PchSerialIoDisabled,
-	}"
-
-	register "serial_io_gspi_cs_mode" = "{
-		[PchSerialIoIndexGSPI0] = 0,
-		[PchSerialIoIndexGSPI1] = 0,
-		[PchSerialIoIndexGSPI2] = 0,
-		[PchSerialIoIndexGSPI3] = 0,
-	}"
-
-	register "serial_io_gspi_cs_state" = "{
-		[PchSerialIoIndexGSPI0] = 0,
-		[PchSerialIoIndexGSPI1] = 0,
-		[PchSerialIoIndexGSPI2] = 0,
-		[PchSerialIoIndexGSPI3] = 0,
-	}"
-
-	register "serial_io_uart_mode" = "{
-		[PchSerialIoIndexUART0] = PchSerialIoSkipInit,
-		[PchSerialIoIndexUART1] = PchSerialIoDisabled,
-		[PchSerialIoIndexUART2] = PchSerialIoDisabled,
-	}"
-
-	# HD Audio
-	register "pch_hda_dsp_enable" = "1"
-	register "pch_hda_idisp_link_tmode" = "HDA_TMODE_8T"
-	register "pch_hda_idisp_link_frequency" = "HDA_LINKFREQ_96MHZ"
-	register "pch_hda_idisp_codec_enable" = "1"
-
-	register "cnvi_bt_audio_offload" = "true"
-
-	# Intel Common SoC Config
-	register "common_soc_config" = "{
-		.i2c[0] = {
-			.speed = I2C_SPEED_FAST,
-		},
-		.i2c[1] = {
-			.speed = I2C_SPEED_FAST,
-		},
-		.i2c[2] = {
-			.speed = I2C_SPEED_FAST,
-		},
-		.i2c[3] = {
-			.speed = I2C_SPEED_FAST,
-		},
-		.i2c[5] = {
-			.speed = I2C_SPEED_FAST,
-		},
-	}"
-
-	# Configure external V1P05/Vnn/VnnSx Rails
-	register "ext_fivr_settings" = "{
-		.configure_ext_fivr = 1,
-		.v1p05_enable_bitmap = FIVR_ENABLE_ALL_SX & ~FIVR_ENABLE_S0,
-		.vnn_enable_bitmap = FIVR_ENABLE_ALL_SX,
-		.vnn_sx_enable_bitmap = FIVR_ENABLE_ALL_SX,
-		.v1p05_supported_voltage_bitmap = FIVR_VOLTAGE_NORMAL,
-		.vnn_supported_voltage_bitmap = FIVR_VOLTAGE_MIN_ACTIVE,
-		.v1p05_voltage_mv = 1050,
-		.vnn_voltage_mv = 780,
-		.vnn_sx_voltage_mv = 1050,
-		.v1p05_icc_max_ma = 500,
-		.vnn_icc_max_ma = 500,
-	}"
-
-	device domain 0 on
-		device ref igpu on end
-		device ref dtt on
-			chip drivers/intel/dptf
-
-				## sensor information
-				register "options.tsr[0].desc" = ""Ambient""
-				register "options.tsr[1].desc" = ""Battery""
-				register "options.tsr[2].desc" = ""DDR""
-				register "options.tsr[3].desc" = ""Skin""
-				register "options.tsr[4].desc" = ""VR""
-
-				## Active Policy
-				# TODO: below values are initial reference values only
-				register "policies.active" = "{
-					[0] = {
-							.target = DPTF_CPU,
-							.thresholds = {
-								TEMP_PCT(95, 90),
-								TEMP_PCT(90, 80),
-							}
-						},
-					[1] = {
-							.target = DPTF_TEMP_SENSOR_0,
-							.thresholds = {
-								TEMP_PCT(80, 90),
-								TEMP_PCT(70, 80),
-							}
-						}
-				}"
-
-				## Passive Policy
-				# TODO: below values are initial reference values only
-				register "policies.passive" = "{
-					[0] = DPTF_PASSIVE(CPU,		CPU,	       95, 10000),
-					[1] = DPTF_PASSIVE(CPU,		TEMP_SENSOR_0, 85, 50000),
-					[2] = DPTF_PASSIVE(CHARGER,	TEMP_SENSOR_1, 85, 50000),
-					[3] = DPTF_PASSIVE(CPU,		TEMP_SENSOR_2, 85, 50000),
-					[4] = DPTF_PASSIVE(CPU,		TEMP_SENSOR_3, 85, 50000),
-					[5] = DPTF_PASSIVE(CPU,		TEMP_SENSOR_4, 85, 50000),
-				}"
-
-				## Critical Policy
-				# TODO: below values are initial reference values only
-				register "policies.critical" = "{
-					[0] = DPTF_CRITICAL(CPU,	  105, SHUTDOWN),
-					[1] = DPTF_CRITICAL(TEMP_SENSOR_0, 95, SHUTDOWN),
-					[2] = DPTF_CRITICAL(TEMP_SENSOR_1, 95, SHUTDOWN),
-					[3] = DPTF_CRITICAL(TEMP_SENSOR_2, 95, SHUTDOWN),
-					[4] = DPTF_CRITICAL(TEMP_SENSOR_3, 95, SHUTDOWN),
-					[5] = DPTF_CRITICAL(TEMP_SENSOR_4, 95, SHUTDOWN),
-				}"
-
-				## Power Limits Control
-				register "controls.power_limits" = "{
-					.pl1 = {
-							.min_power = 3000,
-							.max_power = 15000,
-							.time_window_min = 28 * MSECS_PER_SEC,
-							.time_window_max = 32 * MSECS_PER_SEC,
-							.granularity = 200,
-					},
-					.pl2 = {
-							.min_power = 25000,
-							.max_power = 35000,
-							.time_window_min = 28 * MSECS_PER_SEC,
-							.time_window_max = 32 * MSECS_PER_SEC,
-							.granularity = 1000,
-					}
-				}"
-
-				## Charger Performance Control (Control, mA)
-				register "controls.charger_perf" = "{
-					[0] = { 255, 3000 },
-					[1] = {  24, 1500 },
-					[2] = {  16, 1000 },
-					[3] = {   8,  500 }
-				}"
-
-				## Fan Performance Control (Percent, Speed, Noise, Power)
-				register "controls.fan_perf" = "{
-					[0] = {  90, 6700, 220, 2200, },
-					[1] = {  80, 5800, 180, 1800, },
-					[2] = {  70, 5000, 145, 1450, },
-					[3] = {  60, 4900, 115, 1150, },
-					[4] = {  50, 3838,  90,  900, },
-					[5] = {  40, 2904,  55,  550, },
-					[6] = {  30, 2337,  30,  300, },
-					[7] = {  20, 1608,  15,  150, },
-					[8] = {  10,  800,  10,  100, },
-					[9] = {   0,    0,   0,   50, }
-				}"
-
-				## Fan options
-				register "options.fan.fine_grained_control" = "true"
-				register "options.fan.step_size" = "2"
-
-				device generic 0 alias dptf_policy on end
-			end
-		end
-		device ref ipu on
-			chip drivers/intel/mipi_camera
-				register "acpi_uid" = "0x50000"
-				register "acpi_name" = ""IPU0""
-				register "device_type" = "INTEL_ACPI_CAMERA_CIO2"
-
-				register "cio2_num_ports" = "2"
-				register "cio2_lanes_used" = "{2,2}"
-				register "cio2_lane_endpoint[0]" = ""^I2C5.CAM1""
-				register "cio2_lane_endpoint[1]" = ""^I2C1.CAM0""
-				register "cio2_prt[0]" = "2"
-				register "cio2_prt[1]" = "1"
-				device generic 0 on end
-			end
-		end
-		device ref crashlog off end
-		device ref tcss_xhci on end
-		device ref xhci on
-			chip drivers/usb/acpi
-				register "desc" = ""Root Hub""
-				register "type" = "UPC_TYPE_HUB"
-				device ref xhci_root_hub on
-					chip drivers/usb/acpi
-						register "desc" = ""Bluetooth""
-						register "type" = "UPC_TYPE_INTERNAL"
-						device ref usb2_port10 on end
-					end
-				end
-			end
-		end
-		device ref cnvi_wifi on
-			chip drivers/wifi/generic
-				register "wake" = "GPE0_PME_B0"
-				device generic 0 on end
-			end
-		end
-		device ref i2c0 on end
-		device ref i2c1 on
-			chip drivers/intel/mipi_camera
-				register "acpi_hid" = ""OVTI5675""
-				register "acpi_uid" = "0"
-				register "acpi_name" = ""CAM0""
-				register "chip_name" = ""Ov 5675 Camera""
-				register "device_type" = "INTEL_ACPI_CAMERA_SENSOR"
-
-				register "ssdb.lanes_used" = "2"
-				register "ssdb.vcm_type" = "0x0C"
-				register "vcm_name" = ""VCM0""
-				register "num_freq_entries" = "1"
-				register "link_freq[0]" = "450000000"
-				register "remote_name" = ""IPU0""
-
-				register "has_power_resource" = "true"
-				#Controls
-				register "clk_panel.clks[0].clknum" = "0" #IMGCLKOUT_0
-				register "clk_panel.clks[0].freq" = "1" #19.2 Mhz
-				register "gpio_panel.gpio[0].gpio_num" = "GPP_B23" #power_enable
-				register "gpio_panel.gpio[1].gpio_num" = "GPP_R5" #reset
-
-				#_ON
-				register "on_seq.ops_cnt" = "4"
-				register "on_seq.ops[0]" = "SEQ_OPS_CLK_ENABLE(0, 0)"
-				register "on_seq.ops[1]" = "SEQ_OPS_GPIO_ENABLE(0, 2)"
-				register "on_seq.ops[2]" = "SEQ_OPS_GPIO_DISABLE(1, 1)"
-				register "on_seq.ops[3]" = "SEQ_OPS_GPIO_ENABLE(1, 1)"
-
-				#_OFF
-				register "off_seq.ops_cnt" = "3"
-				register "off_seq.ops[0]" = "SEQ_OPS_CLK_DISABLE(0, 0)"
-				register "off_seq.ops[1]" = "SEQ_OPS_GPIO_DISABLE(1, 0)"
-				register "off_seq.ops[2]" = "SEQ_OPS_GPIO_DISABLE(0, 0)"
-
-				device i2c 36 on end
-			end
-			chip drivers/intel/mipi_camera
-				register "acpi_uid" = "3"
-				register "acpi_name" = ""VCM0""
-				register "chip_name" = ""DW AF VCM""
-				register "device_type" = "INTEL_ACPI_CAMERA_VCM"
-
-				register "pr0" = ""\\_SB.PCI0.I2C1.CAM0.PRIC""
-				register "vcm_compat" = ""dongwoon,dw9714""
-
-				device i2c 0C on end
-			end
-		end
-		device ref i2c2 on end
-		device ref i2c3 on end
-		device ref heci1 on end
-		device ref sata off end
-		device ref i2c5 on
-			chip drivers/intel/mipi_camera
-				register "acpi_hid" = ""OVTI5675""
-				register "acpi_uid" = "0"
-				register "acpi_name" = ""CAM1""
-				register "chip_name" = ""Ov 5675 Camera""
-				register "device_type" = "INTEL_ACPI_CAMERA_SENSOR"
-
-				register "ssdb.lanes_used" = "2"
-				register "num_freq_entries" = "1"
-				register "link_freq[0]" = "450000000"
-				register "remote_name" = ""IPU0""
-
-				register "has_power_resource" = "true"
-				#Controls
-				register "clk_panel.clks[0].clknum" = "1" #IMGCLKOUT_1
-				register "clk_panel.clks[0].freq" = "1" #19.2 Mhz
-				register "gpio_panel.gpio[0].gpio_num" = "GPP_E16" #power_enable
-				register "gpio_panel.gpio[1].gpio_num" = "GPP_E15" #reset
-
-				#_ON
-				register "on_seq.ops_cnt" = "4"
-				register "on_seq.ops[0]" = "SEQ_OPS_CLK_ENABLE(0, 0)"
-				register "on_seq.ops[1]" = "SEQ_OPS_GPIO_ENABLE(0, 2)"
-				register "on_seq.ops[2]" = "SEQ_OPS_GPIO_DISABLE(1, 1)"
-				register "on_seq.ops[3]" = "SEQ_OPS_GPIO_ENABLE(1, 1)"
-
-				#_OFF
-				register "off_seq.ops_cnt" = "3"
-				register "off_seq.ops[0]" = "SEQ_OPS_CLK_DISABLE(0, 0)"
-				register "off_seq.ops[1]" = "SEQ_OPS_GPIO_DISABLE(1, 0)"
-				register "off_seq.ops[2]" = "SEQ_OPS_GPIO_DISABLE(0, 0)"
-
-				device i2c 36 on end
-			end
-		end
-		device ref pcie_rp7 on end
-		device ref pcie_rp9 on end
-		device ref uart0 on end
-		device ref gspi0 on end
-		device ref p2sb on end
-		device ref emmc on end
-		device ref ish on end
-		device ref ufs on end
-		device ref hda on
-			chip drivers/intel/soundwire
-				device generic 0 on
-					chip drivers/soundwire/alc711
-						# SoundWire Link 0 ID 1
-						register "desc" = ""Headset Codec""
-						register "alc711_address.version" = "SOUNDWIRE_VERSION_1_1"
-						register "alc711_address.class" = "MIPI_CLASS_NONE"
-						register "alc711_address.part_id" = "MIPI_DEV_ID_REALTEK_ALC711"
-						device generic 0.1 on end
-					end
-				end
-			end
-		end
-		device ref smbus on end
-	end
-end
diff --git a/src/mainboard/siemens/mc_rpl/early_gpio_m.c b/src/mainboard/siemens/mc_rpl/early_gpio_m.c
deleted file mode 100644
index fbc6467b46..0000000000
--- a/src/mainboard/siemens/mc_rpl/early_gpio_m.c
+++ /dev/null
@@ -1,142 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <baseboard/gpio.h>
-#include <baseboard/variants.h>
-#include <soc/gpio.h>
-
-/* Early pad configuration in bootblock */
-static const struct pad_config early_gpio_table[] = {
-	/* WWAN_RST# */
-	PAD_CFG_GPO(GPP_E5, 0, PLTRST),
-	/* WWAN_PWR_EN */
-	PAD_CFG_GPO(GPP_A8, 1, DEEP),
-
-	/* H0  : PCH_SSD_RST# */
-	PAD_CFG_GPO(GPP_H0, 0, PLTRST),
-	/* H13 : CPU_SSD_RST# */
-	PAD_CFG_GPO(GPP_H13, 0, PLTRST),
-
-	/* EC_IN_RW */
-	PAD_CFG_GPI(GPP_E7, NONE, DEEP),
-
-	/* CPU PCIe VGPIO for RP0 */
-	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_0, NONE, DEEP, NF1),
-	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_1, NONE, DEEP, NF1),
-	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_3, NONE, DEEP, NF1),
-	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_2, NONE, DEEP, NF1),
-	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_4, NONE, DEEP, NF1),
-	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_5, NONE, DEEP, NF1),
-	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_6, NONE, DEEP, NF1),
-	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_7, NONE, DEEP, NF1),
-	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_8, NONE, DEEP, NF1),
-	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_9, NONE, DEEP, NF1),
-	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_10, NONE, DEEP, NF1),
-	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_11, NONE, DEEP, NF1),
-	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_12, NONE, DEEP, NF1),
-	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_13, NONE, DEEP, NF1),
-	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_14, NONE, DEEP, NF1),
-	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_15, NONE, DEEP, NF1),
-	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_64, NONE, DEEP, NF1),
-	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_65, NONE, DEEP, NF1),
-	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_66, NONE, DEEP, NF1),
-	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_67, NONE, DEEP, NF1),
-
-	/* CPU PCIe vGPIO for RP1 */
-	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_16, NONE, DEEP, NF1),
-	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_17, NONE, DEEP, NF1),
-	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_18, NONE, DEEP, NF1),
-	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_19, NONE, DEEP, NF1),
-	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_20, NONE, DEEP, NF1),
-	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_21, NONE, DEEP, NF1),
-	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_22, NONE, DEEP, NF1),
-	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_23, NONE, DEEP, NF1),
-	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_24, NONE, DEEP, NF1),
-	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_25, NONE, DEEP, NF1),
-	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_26, NONE, DEEP, NF1),
-	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_27, NONE, DEEP, NF1),
-	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_28, NONE, DEEP, NF1),
-	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_29, NONE, DEEP, NF1),
-	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_30, NONE, DEEP, NF1),
-	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_31, NONE, DEEP, NF1),
-	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_68, NONE, DEEP, NF1),
-	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_69, NONE, DEEP, NF1),
-	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_70, NONE, DEEP, NF1),
-	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_71, NONE, DEEP, NF1),
-
-	/* CPU PCIe vGPIO for RP2 */
-	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_32, NONE, DEEP, NF1),
-	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_33, NONE, DEEP, NF1),
-	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_34, NONE, DEEP, NF1),
-	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_35, NONE, DEEP, NF1),
-	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_36, NONE, DEEP, NF1),
-	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_37, NONE, DEEP, NF1),
-	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_38, NONE, DEEP, NF1),
-	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_39, NONE, DEEP, NF1),
-	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_40, NONE, DEEP, NF1),
-	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_41, NONE, DEEP, NF1),
-	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_42, NONE, DEEP, NF1),
-	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_43, NONE, DEEP, NF1),
-	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_44, NONE, DEEP, NF1),
-	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_45, NONE, DEEP, NF1),
-	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_46, NONE, DEEP, NF1),
-	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_47, NONE, DEEP, NF1),
-	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_72, NONE, DEEP, NF1),
-	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_73, NONE, DEEP, NF1),
-	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_74, NONE, DEEP, NF1),
-	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_75, NONE, DEEP, NF1),
-
-	/* CPU PCIe vGPIO for RP3 */
-	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_48, NONE, DEEP, NF1),
-	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_49, NONE, DEEP, NF1),
-	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_50, NONE, DEEP, NF1),
-	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_51, NONE, DEEP, NF1),
-	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_52, NONE, DEEP, NF1),
-	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_53, NONE, DEEP, NF1),
-	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_54, NONE, DEEP, NF1),
-	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_55, NONE, DEEP, NF1),
-	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_56, NONE, DEEP, NF1),
-	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_57, NONE, DEEP, NF1),
-	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_58, NONE, DEEP, NF1),
-	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_59, NONE, DEEP, NF1),
-	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_60, NONE, DEEP, NF1),
-	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_61, NONE, DEEP, NF1),
-	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_62, NONE, DEEP, NF1),
-	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_63, NONE, DEEP, NF1),
-	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_76, NONE, DEEP, NF1),
-	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_77, NONE, DEEP, NF1),
-	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_78, NONE, DEEP, NF1),
-	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_79, NONE, DEEP, NF1),
-
-	/* H1_PCH_INT_ODL */
-	PAD_CFG_GPI_APIC(GPP_E3, NONE, PLTRST, LEVEL, INVERT),
-	/* TPM */
-	/* F16 : GSPI1_CS0N */
-	PAD_CFG_NF(GPP_F16, NONE, DEEP, NF4),
-	/* F11 : GSPI1_CLK */
-	PAD_CFG_NF(GPP_F11, NONE, DEEP, NF4),
-	/* F13 : GSPI1_MISO */
-	PAD_CFG_NF(GPP_F13, NONE, DEEP, NF4),
-	/* F12 : GSPI1_MOSI */
-	PAD_CFG_NF(GPP_F12, NONE, DEEP, NF4),
-
-	 /* D10 : PCH_SSD_PWR_EN */
-	PAD_CFG_GPO(GPP_D10, 1, PLTRST),
-	/* D16 : CPU_SSD_PWR_EN */
-	PAD_CFG_GPO(GPP_D16, 1, PLTRST),
-
-};
-
-static const struct pad_config early_uart_gpio_table[] = {
-	/* UART0 RX */
-	PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2),
-	/* UART0 TX */
-	PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2),
-};
-
-void variant_configure_early_gpio_pads(void)
-{
-	if (CONFIG(INTEL_LPSS_UART_FOR_CONSOLE))
-		gpio_configure_pads(early_uart_gpio_table, ARRAY_SIZE(early_uart_gpio_table));
-
-	gpio_configure_pads(early_gpio_table, ARRAY_SIZE(early_gpio_table));
-}
diff --git a/src/mainboard/siemens/mc_rpl/early_gpio_n.c b/src/mainboard/siemens/mc_rpl/early_gpio_n.c
deleted file mode 100644
index 3eb1ceae52..0000000000
--- a/src/mainboard/siemens/mc_rpl/early_gpio_n.c
+++ /dev/null
@@ -1,30 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <baseboard/gpio.h>
-#include <baseboard/variants.h>
-#include <soc/gpio.h>
-
-/* Early pad configuration in bootblock */
-static const struct pad_config early_gpio_table[] = {
-	/* WWAN_RST# */
-	PAD_CFG_GPO(GPP_F14, 0, PLTRST),
-	/* WWAN_PWR_EN */
-	PAD_CFG_GPO(GPP_D17, 1, DEEP),
-	/* EC_IN_RW */
-	PAD_CFG_GPI(GPP_E7, NONE, DEEP),
-};
-
-static const struct pad_config early_uart_gpio_table[] = {
-	/* UART0 RX */
-	PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2),
-	/* UART0 TX */
-	PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2),
-};
-
-void variant_configure_early_gpio_pads(void)
-{
-	if (CONFIG(INTEL_LPSS_UART_FOR_CONSOLE))
-		gpio_configure_pads(early_uart_gpio_table, ARRAY_SIZE(early_uart_gpio_table));
-
-	gpio_configure_pads(early_gpio_table, ARRAY_SIZE(early_gpio_table));
-}
diff --git a/src/mainboard/siemens/mc_rpl/gpio_m.c b/src/mainboard/siemens/mc_rpl/gpio_m.c
deleted file mode 100644
index 5d2366858e..0000000000
--- a/src/mainboard/siemens/mc_rpl/gpio_m.c
+++ /dev/null
@@ -1,193 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <baseboard/gpio.h>
-#include <baseboard/variants.h>
-#include <commonlib/helpers.h>
-#include <vendorcode/google/chromeos/chromeos.h>
-
-/* Pad configuration in ramstage */
-static const struct pad_config gpio_table[] = {
-	/* A12 : BT_RF_KILL_N */
-	PAD_CFG_GPO(GPP_A12, 1, PLTRST),
-
-	/* H2 : WLAN_RST_N */
-	PAD_CFG_GPO(GPP_H2, 1, PLTRST),
-	/* 8 : M.2_BTWIFI_SUS_CLK */
-	PAD_CFG_NF(GPD8, NONE, DEEP, NF1),
-	/* 9 : GPD_9_SLP_WLAN_N */
-	PAD_CFG_NF(GPD9, NONE, DEEP, NF1),
-	/* 10 : GPD_10_SLP_S5_N */
-	PAD_CFG_NF(GPD10, NONE, DEEP, NF1),
-
-	/* D12 : WIFI_RF_KILL_N */
-	PAD_CFG_GPO(GPP_D12, 1, PLTRST),
-	/* D13 : WIFI_WAKE_N */
-	PAD_CFG_NF(GPP_D13, NONE, DEEP, NF1),
-	/* D14 :  x1 PCIE slot1 PWREN / SML0B_CLK */
-	PAD_CFG_NF(GPP_D14, NONE, DEEP, NF1),
-	/* D15 : WWAN_DISABLE_N */
-	PAD_CFG_GPO(GPP_D15, 1, PLTRST),
-	/* D17 : PCIE SLOT1 WAKE N */
-	PAD_CFG_GPI_IRQ_WAKE(GPP_D17, NONE, DEEP, LEVEL, INVERT),
-	/* D18 : WWAN WAKE N*/
-	PAD_CFG_GPI_IRQ_WAKE(GPP_D18, NONE, DEEP, LEVEL, INVERT),
-	/* H23 : CLKREQ5_WWAN_N */
-	PAD_CFG_NF(GPP_H23, NONE, DEEP, NF2),
-
-	/* F0 : CNV_BRI_DT_BT_UART2_RTS_N */
-	PAD_CFG_NF(GPP_F0, NONE, DEEP, NF1),
-	/* F1 : CNV_BRI_RSP_BT_UART2_RXD */
-	PAD_CFG_NF(GPP_F1, NONE, DEEP, NF1),
-	/* F2 : CNV_RGI_DT_BT_UART2_TXD */
-	PAD_CFG_NF(GPP_F2, NONE, DEEP, NF1),
-	/* F3 : CNV_RGI_RSP_BT_UART2_CTS_N */
-	PAD_CFG_NF(GPP_F3, NONE, DEEP, NF1),
-	/* F4 : CNV_RF_RESET_R_N */
-	PAD_CFG_NF(GPP_F4, NONE, DEEP, NF1),
-	/* F5 : MODEM_CLKREQ_R */
-	PAD_CFG_NF(GPP_F5, NONE, DEEP, NF2),
-	/* F6 : GPPC_F6_CNV_PA_BLANKING */
-	PAD_CFG_NF(GPP_F6, NONE, DEEP, NF1),
-	/* F10 : GPPC_F10 X1_Slot_RESET */
-	PAD_CFG_GPO(GPP_F10, 1, PLTRST),
-	/* H8 : CNV_MFUART2_RXD */
-	PAD_CFG_NF(GPP_H8, NONE, DEEP, NF2),
-	/* H9 : CNV_MFUART2_TXD */
-	PAD_CFG_NF(GPP_H9, NONE, DEEP, NF2),
-
-	/* A14 : TCPC01_TYPEA23_OC1_N */
-	PAD_CFG_NF(GPP_A14, NONE, DEEP, NF1),
-	/* A15 :  USB_TYPEA_OC2_N */
-	PAD_CFG_NF(GPP_A15, NONE, DEEP, NF1),
-	/* E18 : TBT_LSX0_TXD */
-	PAD_CFG_NF(GPP_E18, NONE, DEEP, NF4),
-	/* E19 : TBT_LSX0_RXD */
-	PAD_CFG_NF(GPP_E19, NONE, DEEP, NF4),
-	/* E20 : TBT_LSX1_TXD */
-	PAD_CFG_NF(GPP_E20, NONE, DEEP, NF4),
-	/* E21 : TBT_LSX1_RXD */
-	PAD_CFG_NF(GPP_E21, NONE, DEEP, NF4),
-
-	/* H4  : I2C0 SDA */
-	PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1),
-	/* H6  : I2C1 SDA */
-	PAD_CFG_NF(GPP_H6, NONE, DEEP, NF1),
-	/* B16 : I2C5 SDA */
-	PAD_CFG_NF(GPP_B16, NONE, DEEP, NF2),
-
-	/* H5  : I2C0 SCL */
-	PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1),
-	/* H7  : I2C1 SCL */
-	PAD_CFG_NF(GPP_H7, NONE, DEEP, NF1),
-	/* B17 : I2C5 SCL */
-	PAD_CFG_NF(GPP_B17, NONE, DEEP, NF2),
-
-	/* C5  : WWAN_PERST_N */
-	PAD_CFG_GPO(GPP_C5, 1, PLTRST),
-	/* E5  : WWAN_PERST# */
-	PAD_CFG_GPO(GPP_E5, 1, PLTRST),
-	/* D15 : WWAN_DISABLE_N */
-	PAD_CFG_GPO(GPP_D15, 1, PLTRST),
-	/* D9  : WWAN_FCP_POWER_OFF_N */
-	PAD_CFG_GPO(GPP_D9, 1, PLTRST),
-
-	/* H0  : PCH_SSD_RST# */
-	PAD_CFG_GPO(GPP_H0, 1, PLTRST),
-	/* H13 : CPU_SSD_RST# */
-	PAD_CFG_GPO(GPP_H13, 1, PLTRST),
-
-	/* DDP1/2/A/B  CTRLCLK and CTRLDATA pins */
-	PAD_CFG_NF(GPP_E18, NONE, DEEP, NF4),
-	PAD_CFG_NF(GPP_E19, NONE, DEEP, NF4),
-	PAD_CFG_NF(GPP_E20, NONE, DEEP, NF4),
-	PAD_CFG_NF(GPP_E21, NONE, DEEP, NF4),
-	PAD_CFG_NF(GPP_E22, NONE, DEEP, NF2),
-	PAD_CFG_NF(GPP_E23, NONE, DEEP, NF2),
-	PAD_CFG_NF(GPP_A21, NONE, DEEP, NF2),
-	PAD_CFG_NF(GPP_A22, NONE, DEEP, NF2),
-	PAD_CFG_NF(GPP_H15, NONE, DEEP, NF1),
-	PAD_CFG_NF(GPP_H17, NONE, DEEP, NF1),
-
-	/* HPD_1 (E14) and HPD_2 (A18) pins */
-	PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1),
-	PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1),
-
-	PAD_NC(GPP_A19, NONE),
-	PAD_NC(GPP_A20, NONE),
-
-	/* GPIO pin for PCIE SRCCLKREQB */
-	PAD_CFG_NF(GPP_D5, NONE, DEEP, NF1),
-	PAD_CFG_NF(GPP_D6, NONE, DEEP, NF1),
-	PAD_CFG_NF(GPP_D7, NONE, DEEP, NF1),
-	PAD_CFG_NF(GPP_D8, NONE, DEEP, NF1),
-	PAD_CFG_NF(GPP_H19, NONE, DEEP, NF1),
-
-	/* CAM1_RST */
-	PAD_CFG_GPO(GPP_R5, 1, PLTRST),
-	/* CAM2_RST */
-	PAD_CFG_GPO(GPP_E15, 1, PLTRST),
-	/* CAM1_PWR_EN */
-	PAD_CFG_GPO(GPP_B23, 1, PLTRST),
-	/* CAM2_PWR_EN */
-	PAD_CFG_GPO(GPP_E16, 1, PLTRST),
-	/* IMGCLKOUT0 */
-	PAD_CFG_NF(GPP_D4, NONE, DEEP, NF1),
-	/* IMGCLKOUT1 */
-	PAD_CFG_NF(GPP_H20, NONE, DEEP, NF1),
-
-	/* C16 : I2C0 SDA */
-	PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1),
-
-	/* S0 : SNDW1_CLK */
-	PAD_CFG_NF(GPP_S0, NONE, DEEP, NF1),
-
-	/* S1 : SNDW1_DATA */
-	PAD_CFG_NF(GPP_S1, NONE, DEEP, NF1),
-
-	/* S2 : SNDW2_CLK */
-	PAD_CFG_NF(GPP_S2, NONE, DEEP, NF2),
-
-	/* S3 : SNDW2_DATA */
-	PAD_CFG_NF(GPP_S3, NONE, DEEP, NF2),
-
-	/* S4 : SNDW3_CLK */
-	PAD_CFG_NF(GPP_S4, NONE, DEEP, NF2),
-
-	/* S5 : SNDW3_DATA */
-	PAD_CFG_NF(GPP_S5, NONE, DEEP, NF2),
-
-	/* S6 : SNDW4_CLK */
-	PAD_CFG_NF(GPP_S6, NONE, DEEP, NF2),
-
-	/* S7 : SNDW4_DATA */
-	PAD_CFG_NF(GPP_S7, NONE, DEEP, NF2),
-
-	/* F7  : TCH_PNL_PWR_EN */
-	PAD_CFG_GPO(GPP_F7, 1, PLTRST),
-	/* F17 : RST_N_TCH_PNL2 */
-	PAD_CFG_GPO(GPP_F17, 1, PLTRST),
-	/* F18 : INT_N_TCH_PNL2 */
-	PAD_CFG_GPI_APIC(GPP_F18, NONE, PLTRST, LEVEL, NONE),
-
-	/* E3 : H1_PCH_INT_ODL */
-	PAD_CFG_GPI_APIC(GPP_E3, NONE, PLTRST, LEVEL, INVERT),
-
-	/* E4  : SATA_DEVSLP0 ==> USB4_BB_RT_FORCE_PWR */
-	PAD_CFG_GPO(GPP_E4, 0, DEEP),
-
-	/* H1 : GPPC_H1_TCH_PAD_TCH_PNL2_LS_EN */
-	PAD_CFG_GPO(GPP_H1, 0, PLTRST),
-
-	/* D11 : TCH_PAD_INT_N */
-	PAD_CFG_GPI_APIC(GPP_D11, NONE, PLTRST, LEVEL, INVERT)
-};
-
-void variant_configure_gpio_pads(void)
-{
-	gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table));
-}
-
-static const struct cros_gpio cros_gpios[] = {
-	CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME),
-};
-DECLARE_CROS_GPIOS(cros_gpios);
diff --git a/src/mainboard/siemens/mc_rpl/gpio_n.c b/src/mainboard/siemens/mc_rpl/gpio_n.c
deleted file mode 100644
index b985d53dd2..0000000000
--- a/src/mainboard/siemens/mc_rpl/gpio_n.c
+++ /dev/null
@@ -1,239 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <baseboard/gpio.h>
-#include <baseboard/variants.h>
-#include <commonlib/helpers.h>
-#include <vendorcode/google/chromeos/chromeos.h>
-
-/* Pad configuration in ramstage*/
-static const struct pad_config gpio_table[] = {
-	/* ESPI_IO0_EC_R / ESPI_IO0_HDR */
-	PAD_CFG_NF(GPP_A0, NONE, DEEP, NF1),
-	/* ESPI_IO1_EC_R / ESPI_IO1_HDR */
-	PAD_CFG_NF(GPP_A1, NONE, DEEP, NF1),
-	/* ESPI_IO2_EC_R / ESPI_IO2_HDR */
-	PAD_CFG_NF(GPP_A2, NONE, DEEP, NF1),
-	/* ESPI_IO3_EC_R / ESPI_IO3_HDR */
-	PAD_CFG_NF(GPP_A3, NONE, DEEP, NF1),
-	/* ESPI_CS0_EC_R_N / ESPI_CS0_HDR_N */
-	PAD_CFG_NF(GPP_A4, NONE, DEEP, NF1),
-	/* ESPI_ALERT0_EC_R_N / ESPI_ALERT0_HDR_N */
-	PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1),
-	/* ESPI_CLK_EC_R / ESPI_CLK_HDR */
-	PAD_CFG_NF(GPP_A9, NONE, DEEP, NF1),
-	/* ESPI_RST_EC_R_N / ESPI_RST_HDR_N */
-	PAD_CFG_NF(GPP_A10, NONE, DEEP, NF1),
-
-	/* EC_SLP_S0_CS_N */
-	PAD_CFG_GPO(GPP_E4, 1, PLTRST),
-
-	/* H15 : DDPB_CTRLCLK ==> DDIB_HDMI_CTRLCLK */
-	PAD_CFG_NF(GPP_H15, NONE, DEEP, NF1),
-	/* H17 : DDPB_CTRLDATA ==> DDIB_HDMI_CTRLDATA */
-	PAD_CFG_NF(GPP_H17, NONE, DEEP, NF1),
-
-	/* M.2_SSD_PDET_R */
-	PAD_CFG_NF(GPP_A12, NONE, DEEP, NF1),
-	/* CLKREQ0_M2_SSD_N */
-	PAD_CFG_NF(GPP_D5, NONE, DEEP, NF1),
-	/* M2_PCH_SSD_PWREN */
-	PAD_CFG_GPO(GPP_D16, 1, PLTRST),
-	/* M2_SSD_RST_N */
-	PAD_CFG_GPO(GPP_H0, 1, PLTRST),
-	/* M2_SSD_DEVSLP */
-	PAD_CFG_NF(GPP_H13, NONE, DEEP, NF5),
-
-	/* I5  : NC */
-	PAD_NC(GPP_I5, NONE),
-	/* I7  : EMMC_CMD ==> EMMC_CMD */
-	PAD_CFG_NF(GPP_I7, NONE, DEEP, NF1),
-	/* I8  : EMMC_DATA0 ==> EMMC_D0 */
-	PAD_CFG_NF(GPP_I8, NONE, DEEP, NF1),
-	/* I9  : EMMC_DATA1 ==> EMMC_D1 */
-	PAD_CFG_NF(GPP_I9, NONE, DEEP, NF1),
-	/* I10 : EMMC_DATA2 ==> EMMC_D2 */
-	PAD_CFG_NF(GPP_I10, NONE, DEEP, NF1),
-	/* I11 : EMMC_DATA3 ==> EMMC_D3 */
-	PAD_CFG_NF(GPP_I11, NONE, DEEP, NF1),
-	/* I12 : EMMC_DATA4 ==> EMMC_D4 */
-	PAD_CFG_NF(GPP_I12, NONE, DEEP, NF1),
-	/* I13 : EMMC_DATA5 ==> EMMC_D5 */
-	PAD_CFG_NF(GPP_I13, NONE, DEEP, NF1),
-	/* I14 : EMMC_DATA6 ==> EMMC_D6 */
-	PAD_CFG_NF(GPP_I14, NONE, DEEP, NF1),
-	/* I15 : EMMC_DATA7 ==> EMMC_D7 */
-	PAD_CFG_NF(GPP_I15, NONE, DEEP, NF1),
-	/* I16 : EMMC_RCLK ==> EMMC_RCLK */
-	PAD_CFG_NF(GPP_I16, NONE, DEEP, NF1),
-	/* I17 : EMMC_CLK ==> EMMC_CLK */
-	PAD_CFG_NF(GPP_I17, NONE, DEEP, NF1),
-	/* I18 : EMMC_RESET# ==> EMMC_RST_L */
-	PAD_CFG_NF(GPP_I18, NONE, DEEP, NF1),
-
-	/* TYPEA_CONN23_USB2_P8_OC1_N */
-	PAD_CFG_NF(GPP_A14, NONE, DEEP, NF1),
-	/* CRD1_PWREN */
-	PAD_CFG_GPO(GPP_B23, 1, PLTRST),
-	/* TCP1_DISP_AUX_P_BIAS_GPIO */
-	PAD_CFG_GPO(GPP_E20, 1, PLTRST),
-	/* TCP1_DISP_AUX_N_BIAS_GPIO */
-	PAD_CFG_GPO(GPP_E21, 0, PLTRST),
-	/* TCP0_DISP_AUX_P_BIAS_GPIO */
-	PAD_CFG_GPO(GPP_E22, 0, PLTRST),
-	/* TCP0_DISP_AUX_N_BIAS_GPIO */
-	PAD_CFG_GPO(GPP_E23, 1, PLTRST),
-
-	/* EDP1_HPD_MIPI_PNL_RST */
-	PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1),
-
-	/* X1_SLOT_PWREN */
-	PAD_CFG_GPO(GPP_A8, 0, PLTRST),
-	/* SML0_CLK */
-	PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1),
-	/* SML0_DATA */
-	PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1),
-	/* CLKREQ3_X1PCIE_SLOT_N */
-	PAD_CFG_NF(GPP_D8, NONE, DEEP, NF1),
-	/* X1_PCIE_SLOT_WAKE_N */
-	PAD_CFG_GPI_IRQ_WAKE(GPP_D11, NONE, DEEP, LEVEL, INVERT),
-	/* X1_Slot_RESET */
-	PAD_CFG_GPO(GPP_F10, 1, PLTRST),
-
-	/* WWAN_PERST_N */
-	PAD_CFG_GPO(GPP_C5, 1, PLTRST),
-	/* CLKREQ1_WWAN_N */
-	PAD_CFG_NF(GPP_D6, NONE, DEEP, NF1),
-	/* GPPC_D15_M.2_WWAN_DISABLE_N */
-	PAD_CFG_GPO(GPP_D15, 1, PLTRST),
-	/* WWAN_PWREN */
-	PAD_CFG_GPO(GPP_D17, 1, PLTRST),
-	/* WWAN WAKE N */
-	PAD_CFG_GPI_IRQ_WAKE(GPP_D18, NONE, DEEP, LEVEL, INVERT), //TODO SCI
-	/* SRCCLK_OEB6 */
-	PAD_CFG_NF(GPP_E5, NONE, DEEP, NF3),
-	/* GPPC_F6_CNV_PA_BLANKING */
-	PAD_CFG_NF(GPP_F6, NONE, DEEP, NF1),
-	/* WWAN_RST# */
-	PAD_CFG_GPO(GPP_F14, 1, PLTRST),
-	/* WWAN_FCP_OFF_N */
-	PAD_CFG_GPO(GPP_F15, 1, PLTRST),
-	/* CNV_MFUART2_RXD */
-	PAD_CFG_NF(GPP_H8, NONE, DEEP, NF2),
-	/* CNV_MFUART2_RXD */
-	PAD_CFG_NF(GPP_H9, NONE, DEEP, NF2),
-
-	/* PM_SLP_S0_N */
-	PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1),
-	/* PLT_RST_N */
-	PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1),
-	/* PM_SLP_DRAM_N */
-	PAD_CFG_NF(GPP_E8, NONE, DEEP, NF2),
-	/* CPU_C10_GATE_N_R */
-	PAD_CFG_NF(GPP_H18, NONE, DEEP, NF1),
-
-	/* CODEC_INT_N */
-	PAD_CFG_GPI_APIC(GPP_H3, NONE, PLTRST, LEVEL, INVERT),
-	/* SNDW0_CLK_HDR */
-	PAD_CFG_NF(GPP_S0, NONE, DEEP, NF1),
-	/* SNDW0_DATA_HDR */
-	PAD_CFG_NF(GPP_S1, NONE, DEEP, NF1),
-	/* SNDW1_CLK_DMIC_CLK_A_0 */
-	PAD_CFG_NF(GPP_S2, NONE, DEEP, NF2),
-	/* SNDW1_DATA_DMIC_DATA_0 */
-	PAD_CFG_NF(GPP_S3, NONE, DEEP, NF2),
-	/* SNDW2_CLK_R */
-	PAD_CFG_NF(GPP_S4, NONE, DEEP, NF1),
-	/* SNDW2_DATA_R */
-	PAD_CFG_NF(GPP_S5, NONE, DEEP, NF1),
-	/* SOC_DMIC0_SNDW3_CLK */
-	PAD_CFG_NF(GPP_S6, NONE, DEEP, NF2),
-	/* SOC_DMIC0_SNDW3_DATA */
-	PAD_CFG_NF(GPP_S7, NONE, DEEP, NF2),
-
-	/* I2C_SCL(0) */
-	PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1),
-	/* I2C_SDA(0) */
-	PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1),
-
-	/* DDIB_DP_HDMI_ALS_HDP */
-	PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1),
-
-	/* 8 : M.2_BTWIFI_SUS_CLK */
-	PAD_CFG_NF(GPD8, NONE, DEEP, NF1),
-	/* 9 : GPD_9_SLP_WLAN_N */
-	PAD_CFG_NF(GPD9, NONE, DEEP, NF1),
-
-	/* SRCCLK_OEB7 */
-	PAD_CFG_GPO(GPP_A7, 0, PLTRST),
-
-	/* GPIO pin for PCIE SRCCLKREQB_2 */
-	PAD_CFG_NF(GPP_D7, NONE, DEEP, NF1),
-
-	/* H2 : WLAN_RST_N */
-	PAD_CFG_GPO(GPP_H2, 1, PLTRST),
-	/* I2C_SDA(1) */
-	PAD_CFG_NF(GPP_H6, NONE, DEEP, NF1),
-	/* I2C_SCL(1) */
-	PAD_CFG_NF(GPP_H7, NONE, DEEP, NF1),
-
-	/* CAM_PRIVACY_LED */
-	PAD_CFG_GPO(GPP_B14, 1, PLTRST),
-
-	/* B16 : I2C5 SDA */
-	PAD_CFG_NF(GPP_B16, NONE, DEEP, NF2),
-	/* B17 : I2C5 SCL */
-	PAD_CFG_NF(GPP_B17, NONE, DEEP, NF2),
-
-	/* CAM_STROBE */
-	PAD_CFG_GPO(GPP_B18, 0, PLTRST),
-	/* CAM1_RST_N */
-	PAD_CFG_GPO(GPP_A21, 1, PLTRST),
-	/* CAM1_PWR_EN */
-	PAD_CFG_GPO(GPP_B23, 1, PLTRST),
-	/* CAM2_RST */
-	PAD_CFG_GPO(GPP_E15, 1, PLTRST),
-	/* CAM2_PWR_EN */
-	PAD_CFG_GPO(GPP_E16, 1, PLTRST),
-
-	/* IMGCLKOUT */
-	PAD_CFG_NF(GPP_D4, NONE, DEEP, NF1),
-	PAD_CFG_NF(GPP_H20, NONE, DEEP, NF1),
-	PAD_CFG_NF(GPP_H21, NONE, DEEP, NF1),
-	PAD_CFG_NF(GPP_H22, NONE, DEEP, NF1),
-
-	/* BT_RF_KILL_N */
-	PAD_CFG_GPO(GPP_A13, 1, PLTRST),
-
-	/* D13 : WIFI_WAKE_N */
-	PAD_CFG_NF(GPP_D13, NONE, DEEP, NF1),
-	/* WIFI RF KILL */
-	PAD_CFG_GPO(GPP_E3, 1, PLTRST),
-
-	/* F0 : CNV_BRI_DT_BT_UART2_RTS_N */
-	PAD_CFG_NF(GPP_F0, NONE, DEEP, NF1),
-	/* F1 : CNV_BRI_RSP_BT_UART2_RXD */
-	PAD_CFG_NF(GPP_F1, NONE, DEEP, NF1),
-	/* F2 : CNV_RGI_DT_BT_UART2_TXD */
-	PAD_CFG_NF(GPP_F2, NONE, DEEP, NF1),
-	/* F3 : CNV_RGI_RSP_BT_UART2_CTS_N */
-	PAD_CFG_NF(GPP_F3, NONE, DEEP, NF1),
-	/* F4 : CNV_RF_RESET_R_N */
-	PAD_CFG_NF(GPP_F4, NONE, DEEP, NF1),
-	/* F5 : MODEM_CLKREQ_R */
-	PAD_CFG_NF(GPP_F5, NONE, DEEP, NF2),
-	/* TCH PAD Power EN */
-	PAD_CFG_GPO(GPP_F7, 1, PLTRST),
-
-	/* UART_BT_WAKE_N */
-	PAD_CFG_GPI_IRQ_WAKE(GPP_E0, NONE, DEEP, LEVEL, INVERT),
-};
-
-void variant_configure_gpio_pads(void)
-{
-	gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table));
-}
-
-static const struct cros_gpio cros_gpios[] = {
-	CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME),
-};
-DECLARE_CROS_GPIOS(cros_gpios);

From c1df30db188378c9552eb334b80994ae98fc5b97 Mon Sep 17 00:00:00 2001
From: Werner Zeh <werner.zeh@siemens.com>
Date: Wed, 14 May 2025 12:21:47 +0200
Subject: [PATCH 1089/3886] mb/siemens/mc_rpl: Delete fw_config since it is not
 used

The FW_CONFIG feature is not used on mc_rpl. Delete the related source
file and the reference to it in Makefile.

Change-Id: Ifec1efc239801205f1aec2095082c8f744f84a55
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87672
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
---
 src/mainboard/siemens/mc_rpl/Makefile.mk |  1 -
 src/mainboard/siemens/mc_rpl/fw_config.c | 41 ------------------------
 2 files changed, 42 deletions(-)
 delete mode 100644 src/mainboard/siemens/mc_rpl/fw_config.c

diff --git a/src/mainboard/siemens/mc_rpl/Makefile.mk b/src/mainboard/siemens/mc_rpl/Makefile.mk
index e13158b89f..013a8f603e 100644
--- a/src/mainboard/siemens/mc_rpl/Makefile.mk
+++ b/src/mainboard/siemens/mc_rpl/Makefile.mk
@@ -15,7 +15,6 @@ endif
 
 ramstage-y += mainboard.c
 ramstage-y += board_id.c
-ramstage-$(CONFIG_FW_CONFIG) += fw_config.c
 ramstage-y += ramstage.c
 
 CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/include
diff --git a/src/mainboard/siemens/mc_rpl/fw_config.c b/src/mainboard/siemens/mc_rpl/fw_config.c
deleted file mode 100644
index 8589bd8bdc..0000000000
--- a/src/mainboard/siemens/mc_rpl/fw_config.c
+++ /dev/null
@@ -1,41 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <bootstate.h>
-#include <console/console.h>
-#include <fw_config.h>
-#include <gpio.h>
-
-static const struct pad_config i2s_enable_pads[] = {
-	/* Audio Codec INT N */
-	PAD_CFG_GPI_APIC(GPP_H3, NONE, PLTRST, EDGE_BOTH, INVERT),
-
-	/* I2S0_SCLK */
-	PAD_CFG_NF(GPP_R0, NONE, DEEP, NF2),
-	/* I2S0_SFRM */
-	PAD_CFG_NF(GPP_R1, NONE, DEEP, NF2),
-	/* I2S0_TXD */
-	PAD_CFG_NF(GPP_R2, NONE, DEEP, NF2),
-	/* I2S0_RXD */
-	PAD_CFG_NF(GPP_R3, NONE, DEEP, NF2),
-
-	/* I2S2_SCLK */
-	PAD_CFG_NF(GPP_R4, NONE, DEEP, NF2),
-	/* I2S2_SFRM */
-	PAD_CFG_NF(GPP_R5, NONE, DEEP, NF2),
-	/* I2S2_TXD */
-	PAD_CFG_NF(GPP_R6, NONE, DEEP, NF2),
-	/* I2S2_RXD */
-	PAD_CFG_NF(GPP_R7, NONE, DEEP, NF2),
-
-	/* I2S_MCLK1_OUT */
-	PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1),
-};
-
-static void fw_config_handle(void *unused)
-{
-	if (fw_config_probe(FW_CONFIG(AUDIO, ADL_MAX98373_ALC5682I_I2S))) {
-		printk(BIOS_INFO, "Configure GPIOs for I2S audio.\n");
-		gpio_configure_pads(i2s_enable_pads, ARRAY_SIZE(i2s_enable_pads));
-	}
-}
-BOOT_STATE_INIT_ENTRY(BS_DEV_ENABLE, BS_ON_ENTRY, fw_config_handle, NULL);

From dafd7d6eb936d19ebbe24e1efa87a3cc9468a198 Mon Sep 17 00:00:00 2001
From: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Date: Thu, 8 May 2025 11:17:06 +0800
Subject: [PATCH 1090/3886] mb/google/nissa/var/dirks: Deassert RTL8111H's
 ISOLATE_ODL earlier

RTL8111 was occasionally not detected after reboot. This change
moves the configuration of the ISOLATE_ODL pin to high earlier
in the sequence to ensure the device is properly visible during
PCIe bus enumeration.

BUG=b:407469351
TEST=Verified that the Ethernet NIC is enumerated after reboot.

before:
[DEBUG]  PCI: 00:1c.0 scanning...
[SPEW ]  do_pci_scan_bridge for PCI: 00:1c.0
[DEBUG]  PCI: pci_scan_bus for bus 01
[INFO ]  PCI: Static device PCI: 01:00.0 not found, disabling it.
[DEBUG]  GENERIC: 0.0 enabled
[WARN ]  PCI: Leftover static devices:
[WARN ]  PCI: 01:00.0
[WARN ]  PCI: Check your devicetree.cb.
[DEBUG]  scan_bus: bus PCI: 00:1c.0 finished in 34 msecs

after:
[DEBUG]  PCI: 00:1c.0 scanning...
[SPEW ]  do_pci_scan_bridge for PCI: 00:1c.0
[DEBUG]  PCI: pci_scan_bus for bus 01
[SPEW ]  PCI: 01:00.0 [10ec/0000] ops
[DEBUG]  PCI: 01:00.0 [10ec/8168] enabled
[DEBUG]  GENERIC: 0.0 enabled
[INFO ]  Enabling Common Clock Configuration
[INFO ]  L1 Sub-State supported from root port 28
[INFO ]  L1 Sub-State Support = 0xf
[INFO ]  CommonModeRestoreTime = 0x96
[INFO ]  Power On Value = 0xf, Power On Scale = 0x1
[INFO ]  ASPM: Enabled L1
[INFO ]  PCIe: Max_Payload_Size adjusted to 128
[INFO ]  PCI: 01:00.0: Enabled LTR
[INFO ]  PCI: 01:00.0: Programmed LTR max latencies
[DEBUG]  scan_bus: bus PCI: 00:1c.0 finished in 68 msecs

Change-Id: Idc0eb453c342828e0e8886ca5cacea8d7efcc437
Signed-off-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87734
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com>
---
 src/mainboard/google/brya/variants/dirks/gpio.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/src/mainboard/google/brya/variants/dirks/gpio.c b/src/mainboard/google/brya/variants/dirks/gpio.c
index 19e540a682..77ddade671 100644
--- a/src/mainboard/google/brya/variants/dirks/gpio.c
+++ b/src/mainboard/google/brya/variants/dirks/gpio.c
@@ -121,6 +121,8 @@ static const struct pad_config override_gpio_table[] = {
 
 /* Early pad configuration in bootblock */
 static const struct pad_config early_gpio_table[] = {
+	/* H21 : IMGCLKOUT2==> LAN_PE_ISOLATE_ODL */
+	PAD_CFG_GPO(GPP_H21, 1, DEEP),
 	/* GPP_B4 : [] ==> LAN_PERST_L */
 	PAD_CFG_GPO(GPP_B4, 0, DEEP),
 	/* H20 : IMGCLKOUT1 ==> WLAN_PERST_L */

From 2985af84c38c01be236564692ffac0246a384f44 Mon Sep 17 00:00:00 2001
From: lizheng <lizheng@huaqin.corp-partner.google.com>
Date: Tue, 20 May 2025 10:47:35 +0800
Subject: [PATCH 1091/3886] mb/google/trulo/var/pujjocento: Add Fn key scancode

The Fn key on pujjocento emits a scancode of 94 (0x5e).

BUG=b:417141058
TEST=Flash Pujjocento, boot to Linux kernel, and verify that KEY_FN is
generated when pressed using `evtest`.

Change-Id: If8ad29fccbd7c088ee793f3261df0b0999f25765
Signed-off-by: lizheng <lizheng@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87752
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
---
 src/mainboard/google/brya/Kconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/src/mainboard/google/brya/Kconfig b/src/mainboard/google/brya/Kconfig
index 1f3867277d..354d122465 100644
--- a/src/mainboard/google/brya/Kconfig
+++ b/src/mainboard/google/brya/Kconfig
@@ -516,6 +516,7 @@ config BOARD_GOOGLE_PUJJONIRU
 
 config BOARD_GOOGLE_PUJJOCENTO
 	select BOARD_GOOGLE_BASEBOARD_TRULO
+	select MAINBOARD_HAS_GOOGLE_STRAUSS_KEYBOARD
 	select SOC_INTEL_COMMON_BLOCK_HDA_VERB
 	select SOC_INTEL_TCSS_USE_PDC_PMC_USBC_MUX_CONFIGURATION
 	select USE_UNIFIED_AP_FIRMWARE_FOR_UFS_AND_NON_UFS

From d6fe379e9c4576ed27db829db1d6348755370366 Mon Sep 17 00:00:00 2001
From: "P, Usha" <usha.p@intel.com>
Date: Thu, 15 May 2025 01:28:54 +0530
Subject: [PATCH 1092/3886] mb/google/ocelot: Enable LP5 and DDR5 memory
 configuration

This commit introduces support for LP5 and DDR5 memory configurations
on ocelot. It adds board IDs for ocelot and integrates new memory
settings within the variant parameters. The new memory configuration
includes settings related to early command training and LP5/DDR5
specific training parameters.

LP5 memory configuration includes detailed DQ and DQS mapping for
different DDR channels. This facilitates accurate routing of signals
and initialization of memory. Additionally, SPD information retrieval
is adapted to accommodate DDR5-specific settings, such as DIMM module
topology and SMBus addresses.

BUG=b:394208231
TEST=Build Ocelot and verify it compiles without any error.

Change-Id: I828b1944d5a0d7f58aa8f545d567b1bb1b0da5ae
Signed-off-by: P, Usha <usha.p@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87684
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 .../baseboard/include/baseboard/variants.h    |  7 +-
 .../google/ocelot/variants/ocelot/memory.c    | 91 ++++++++++++-------
 2 files changed, 64 insertions(+), 34 deletions(-)

diff --git a/src/mainboard/google/ocelot/variants/baseboard/include/baseboard/variants.h b/src/mainboard/google/ocelot/variants/baseboard/include/baseboard/variants.h
index ad26ab8a67..d82877fe06 100644
--- a/src/mainboard/google/ocelot/variants/baseboard/include/baseboard/variants.h
+++ b/src/mainboard/google/ocelot/variants/baseboard/include/baseboard/variants.h
@@ -40,4 +40,9 @@ void baseboard_devtree_update(void);
 /* Modify devictree settings during ramstage by dedicated variant */
 void variant_devtree_update(void);
 
-#endif /*__BASEBOARD_VARIANTS_H__ */
+enum variant_board_id {
+	BOARD_ID_DDR5 = 0x20,
+	BOARD_ID_LP5X = 0x21,
+};
+
+#endif /* __BASEBOARD_VARIANTS_H__ */
diff --git a/src/mainboard/google/ocelot/variants/ocelot/memory.c b/src/mainboard/google/ocelot/variants/ocelot/memory.c
index e0908adabd..7ac5ce95fd 100644
--- a/src/mainboard/google/ocelot/variants/ocelot/memory.c
+++ b/src/mainboard/google/ocelot/variants/ocelot/memory.c
@@ -1,56 +1,40 @@
 /* SPDX-License-Identifier: GPL-2.0-or-later */
 
 #include <baseboard/variants.h>
-#include <soc/romstage.h>
+#include <boardid.h>
 #include <soc/meminit.h>
+#include <soc/romstage.h>
+
+#define BOARD_ID_MASK	0x3f
+#define SMBUS_ADDR_DIMM	0x50
 
 static const struct mb_cfg lp5_mem_config = {
 	.type = MEM_TYPE_LP5X,
 
 	.lpx_dq_map = {
 		.ddr0 = {
-			.dq0 = {  13,  14,  12,  15, 11,  10,  8,  9, },
-			.dq1 = {  7,  5,  4,  6,  0,  3,  1,  2 },
+			.dq0 = {  10,  11,  8,  9,  15,  14,  12,  13, },
+			.dq1 = {  7,  4,  5,  6,  3,  0,  2,  1 },
 		},
 		.ddr1 = {
-			.dq0 = {  1,  3,  0,  2,  7,  4,  6,  5, },
-			.dq1 = {  12,  13,  14,  15,  11,  10,  9,  8 },
+			.dq0 = {  8,  11,  10,  9,  15,  12,  13,  14, },
+			.dq1 = {  6,  7,  5,  4,  1,  3,  0,  2 },
 		},
 		.ddr2 = {
-			.dq0 = {  0,  2,  1,  3,  6,  4,  7,  5 },
-			.dq1 = {  14,  13,  15,  12,  8,  11,  10,  9, },
+			.dq0 = {  3,  2,  1,  0,  6,  7,  5,  4, },
+			.dq1 = {  9,  8,  10,  11,  15,  12,  13,  14 },
 		},
 		.ddr3 = {
-			.dq0 = {  6,  5,  7,  4,  2,  3,  1,  0, },
-			.dq1 = {  10,  8,  11,  9,  12,  15,  13,  14 },
-		},
-		.ddr4 = {
-			.dq0 = {  2,  1,  3,  0,  4,  7,  5,  6 },
-			.dq1 = {  15,  14,  12,  13,  9,  11,  10,  8, },
-		},
-		.ddr5 = {
-			.dq0 = {  6,  5,  7,  4,  3,  1,  0,  2, },
-			.dq1 = {  10,  9,  11,  8,  13,  14,  12,  15 },
-		},
-		.ddr6 = {
-			.dq0 = {  9,  10,  11,  8,  14,  12,  13, 15, },
-			.dq1 = {  0,  1,  2,  3,  5,  7,  4,  6 },
-		},
-		.ddr7 = {
-			.dq0 = {  0,  1,  2,  3,  7,  5,  6,  4, },
-			.dq1 = {  14,  13,  15,  12,  10,  8,  11,  9 },
+			.dq0 = {  8,  11,  10,  9,  15,  13,  12,  14, },
+			.dq1 = {  4,  5,  6,  7,  1,  3,  2,  0 },
 		},
 	},
 
 	.lpx_dqs_map = {
 		.ddr0 = { .dqs0 = 1, .dqs1 = 0 },
-		.ddr1 = { .dqs0 = 0, .dqs1 = 1 },
+		.ddr1 = { .dqs0 = 1, .dqs1 = 0 },
 		.ddr2 = { .dqs0 = 0, .dqs1 = 1 },
-		.ddr3 = { .dqs0 = 0, .dqs1 = 1 },
-		.ddr4 = { .dqs0 = 0, .dqs1 = 1 },
-		.ddr5 = { .dqs0 = 0, .dqs1 = 1 },
-		.ddr6 = { .dqs0 = 1, .dqs1 = 0 },
-		.ddr7 = { .dqs0 = 0, .dqs1 = 1 }
+		.ddr3 = { .dqs0 = 1, .dqs1 = 0 },
 	},
 
 	.ect = true, /* Early Command Training */
@@ -64,13 +48,54 @@ static const struct mb_cfg lp5_mem_config = {
 	},
 };
 
+static const struct mb_cfg ddr5_mem_config = {
+	.type = MEM_TYPE_DDR5,
+
+	.ect = true, /* Early Command Training */
+
+	.user_bd = BOARD_TYPE_ULT_ULX,
+
+	.lp_ddr_dq_dqs_re_training = 1,
+
+	.ddr_config = {
+		.dq_pins_interleaved = false,
+	},
+};
+
 const struct mb_cfg *variant_memory_params(void)
 {
-	return &lp5_mem_config;
+	uint32_t id = board_id() & BOARD_ID_MASK;
+	printk(BIOS_INFO, "Board ID: %u\n", id);
+
+	switch (id) {
+	case BOARD_ID_DDR5:
+		return &ddr5_mem_config;
+	case BOARD_ID_LP5X:
+		return &lp5_mem_config;
+	default:
+		printk(BIOS_INFO, "Valid Board IDs: DDR5 = %u, LP5X = %u\n", BOARD_ID_DDR5, BOARD_ID_LP5X);
+		die("Unknown Board ID: %u\n", id);
+		break;
+	}
 }
 
 void variant_get_spd_info(struct mem_spd *spd_info)
 {
-	spd_info->topo = MEM_TOPO_MEMORY_DOWN;
+	uint32_t id = board_id() & BOARD_ID_MASK;
 	spd_info->cbfs_index = 0;
+
+	switch (id) {
+	case BOARD_ID_DDR5:
+		spd_info->topo = MEM_TOPO_DIMM_MODULE;
+		spd_info->smbus[0].addr_dimm[0] = SMBUS_ADDR_DIMM;
+		spd_info->smbus[1].addr_dimm[0] = SMBUS_ADDR_DIMM;
+		break;
+	case BOARD_ID_LP5X:
+		spd_info->topo = MEM_TOPO_MEMORY_DOWN;
+		break;
+	default:
+		printk(BIOS_INFO, "Valid Board IDs: DDR5 = %u, LP5X = %u\n", BOARD_ID_DDR5, BOARD_ID_LP5X);
+		die("Unknown Board ID: %u\n", id);
+		break;
+	}
 }

From 87110309d48de13e8676b05f2fe7f8932cee3f19 Mon Sep 17 00:00:00 2001
From: Yidi Lin <yidilin@chromium.org>
Date: Wed, 21 May 2025 23:28:35 +0800
Subject: [PATCH 1093/3886] mt8196: Remove mcupm_plat.h header from
 mcupm_plat.h

A header file should not include itself.

BUG=none
TEST=none

Change-Id: I093396c9f848b3e82842d048e8e0d718971df11f
Signed-off-by: Yidi Lin <yidilin@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87775
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/soc/mediatek/mt8196/include/soc/mcupm_plat.h | 1 -
 1 file changed, 1 deletion(-)

diff --git a/src/soc/mediatek/mt8196/include/soc/mcupm_plat.h b/src/soc/mediatek/mt8196/include/soc/mcupm_plat.h
index 53ec2415da..6ce58e4799 100644
--- a/src/soc/mediatek/mt8196/include/soc/mcupm_plat.h
+++ b/src/soc/mediatek/mt8196/include/soc/mcupm_plat.h
@@ -4,7 +4,6 @@
 #define __SOC_MEDIATEK_MT8196_INCLUDE_SOC_MCUPM_PLAT_H__
 
 #include <soc/addressmap.h>
-#include <soc/mcupm_plat.h>
 #include <types.h>
 
 #define MCUPM_SW_RSTN				(MCUCFG_BASE + 0x00240000)

From 743e3a07f529c3c6886989d21d077692a89c0bc9 Mon Sep 17 00:00:00 2001
From: Simon Yang <simon1.yang@intel.com>
Date: Mon, 19 May 2025 17:53:33 +0800
Subject: [PATCH 1094/3886] mb/google/brya/var/nissa: Remove duplicate ACPI
 device GFX0

Per discussion in CB:87660, this is another approach to fix duplicate
ACPI device GFX0.

The following GFX ACPI device is already declared in nissa/devicetree
by CB:83071, it declare a ACPI gfx device as below:

	device ref igpu on
		register "panel_cfg" = "{
		    .up_delay_ms = 200,
		    .down_delay_ms = 50,
		    .cycle_delay_ms = 500,
		    .backlight_on_delay_ms = 1,
		    .backlight_off_delay_ms = 200,
		    .backlight_pwm_hz = 200,
		}"
		register "gfx" = "GMA_DEFAULT_PANEL(0)"
	end

It will generate an ACPI \_SB.PCI0.GFX0 device.

However, some Nissa projects re-select DRIVERS_GFX_GENERIC in their
overridetree, which results in the generation of a second
\_SB.PCI0.GFX0. This duplication causes iasl to fail when disassembling
the SSDT table.

Error message from iasl:

	File appears to be binary: found 7485 non-ASCII characters, disassembling
	Binary file appears to be a valid ACPI table, disassembling
	Input file SSDT, Length 0x4A03 (18947) bytes
	ACPI: SSDT 0x0000000000000000 004A03 (v02 COREv4 COREBOOT 00000000 CORE 20230628)
	Pass 1 parse of [SSDT]
	Firmware Error (ACPI): Failure creating named object [\_SB.PCI0.GFX0._DOD], AE_ALREADY_EXISTS (20200925/dswload-387)
	ACPI Error: AE_ALREADY_EXISTS, During name lookup/catalog (20200925/psobject-264)
	Could not parse ACPI tables, AE_ALREADY_EXISTS

BUG=none
TEST=disassembling SSDT on pujjoniru successfully

Change-Id: I16e9875c12b4e8e42214da5972bed6a02c5567f4
Signed-off-by: Simon Yang <simon1.yang@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87745
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
---
 src/mainboard/google/brya/Kconfig                          | 7 ++-----
 .../google/brya/variants/baseboard/nissa/devicetree.cb     | 6 +++++-
 2 files changed, 7 insertions(+), 6 deletions(-)

diff --git a/src/mainboard/google/brya/Kconfig b/src/mainboard/google/brya/Kconfig
index 354d122465..59895cc839 100644
--- a/src/mainboard/google/brya/Kconfig
+++ b/src/mainboard/google/brya/Kconfig
@@ -91,6 +91,7 @@ config BOARD_GOOGLE_BASEBOARD_NISSA
 	select BOARD_ROMSIZE_KB_16384 if !BOARD_ROMSIZE_KB_32768
 	select CHROMEOS_DRAM_PART_NUMBER_IN_CBI if CHROMEOS
 	select DRIVERS_AUDIO_SOF
+	select DRIVERS_GFX_GENERIC
 	select DRIVERS_INTEL_ISH
 	select FSP_TYPE_IOT if !CHROMEOS
 	select MAINBOARD_DISABLE_STAGE_CACHE
@@ -109,6 +110,7 @@ config BOARD_GOOGLE_BASEBOARD_TRULO
 	select BOARD_ROMSIZE_KB_16384 if !BOARD_ROMSIZE_KB_32768
 	select CHROMEOS_DRAM_PART_NUMBER_IN_CBI if CHROMEOS
 	select DRIVERS_AUDIO_SOF
+	select DRIVERS_GFX_GENERIC
 	select DRIVERS_INTEL_ISH
 	select DRIVER_INTEL_ISH_HAS_MAIN_FW
 	select MAINBOARD_DISABLE_STAGE_CACHE
@@ -152,7 +154,6 @@ config BOARD_GOOGLE_ANRAGGAR
 	select BOARD_ROMSIZE_KB_16384
 	select DRIVERS_GENERIC_BAYHUB_LV2
 	select DRIVERS_GENERIC_GPIO_KEYS
-	select DRIVERS_GFX_GENERIC
 	select DRIVERS_INTEL_MIPI_CAMERA
 	select HAVE_WWAN_POWER_SEQUENCE
 	select INTEL_GMA_HAVE_VBT
@@ -508,7 +509,6 @@ config BOARD_GOOGLE_PUJJONIRU
 	select CHROMEOS_WIFI_SAR if CHROMEOS
 	select DRIVERS_GENERIC_BAYHUB_LV2
 	select DRIVERS_GENERIC_GPIO_KEYS
-	select DRIVERS_GFX_GENERIC
 	select DRIVERS_AUDIO_SOF
 	select ENFORCE_MEM_CHANNEL_DISABLE
 	select MAINBOARD_HAS_GOOGLE_STRAUSS_KEYBOARD
@@ -579,7 +579,6 @@ config BOARD_GOOGLE_RULL
 	select CHROMEOS_WIFI_SAR if CHROMEOS
 	select DRIVERS_GENERIC_BAYHUB_LV2
 	select DRIVERS_GENERIC_GPIO_KEYS
-	select DRIVERS_GFX_GENERIC
 	select MAINBOARD_HAS_GOOGLE_STRAUSS_KEYBOARD
 	select SOC_INTEL_TWINLAKE
 
@@ -638,7 +637,6 @@ config BOARD_GOOGLE_TELIKS
 	select CHROMEOS_WIFI_SAR if CHROMEOS
 	select DRIVERS_GENERIC_BAYHUB_LV2
 	select DRIVERS_GENERIC_GPIO_KEYS
-	select DRIVERS_GFX_GENERIC
 	select DRIVERS_INTEL_MIPI_CAMERA
 	select HAVE_WWAN_POWER_SEQUENCE
 	select SOC_INTEL_TWINLAKE
@@ -650,7 +648,6 @@ config BOARD_GOOGLE_TELITH
 	select CHROMEOS_WIFI_SAR if CHROMEOS
 	select DRIVERS_GENERIC_BAYHUB_LV2
 	select DRIVERS_GENERIC_GPIO_KEYS
-	select DRIVERS_GFX_GENERIC
 	select DRIVERS_INTEL_MIPI_CAMERA
 	select MAINBOARD_HAS_GOOGLE_STRAUSS_KEYBOARD
 	select SOC_INTEL_TWINLAKE
diff --git a/src/mainboard/google/brya/variants/baseboard/nissa/devicetree.cb b/src/mainboard/google/brya/variants/baseboard/nissa/devicetree.cb
index 8b1cebd1a5..2804818261 100644
--- a/src/mainboard/google/brya/variants/baseboard/nissa/devicetree.cb
+++ b/src/mainboard/google/brya/variants/baseboard/nissa/devicetree.cb
@@ -189,7 +189,11 @@ chip soc/intel/alderlake
 			    .backlight_off_delay_ms = 200,
 			    .backlight_pwm_hz = 200,
 			}"
-			register "gfx" = "GMA_DEFAULT_PANEL(0)"
+			chip drivers/gfx/generic
+				register "device_count" = "1"
+				register "device[0].name" = ""LCD0""
+				device generic 0 on end
+			end
 		end
 		device ref dtt on end
 		device ref gna on end

From bbcb222f0b80ad5cc7f0f9463356e051366d63da Mon Sep 17 00:00:00 2001
From: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Date: Wed, 21 May 2025 09:44:48 +0800
Subject: [PATCH 1095/3886] mb/google/fatcat/var/kinmen: Update GPIO table

Configure GPIOs and related settings per schematic_20250520_v25.

BUG=b:409148565
TEST=emerge-fatcat coreboot

Change-Id: Ib18560de601b98f3b8f45adab5d81686ea236ac9
Signed-off-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87767
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
---
 src/mainboard/google/fatcat/Kconfig           |   3 +-
 .../baseboard/fatcat/include/baseboard/gpio.h |   3 +-
 .../google/fatcat/variants/kinmen/gpio.c      | 405 ++++++++++--------
 3 files changed, 223 insertions(+), 188 deletions(-)

diff --git a/src/mainboard/google/fatcat/Kconfig b/src/mainboard/google/fatcat/Kconfig
index b5f649c648..f822424e82 100644
--- a/src/mainboard/google/fatcat/Kconfig
+++ b/src/mainboard/google/fatcat/Kconfig
@@ -93,6 +93,7 @@ config BOARD_GOOGLE_FRANCKA
 
 config BOARD_GOOGLE_KINMEN
 	select BOARD_GOOGLE_BASEBOARD_FATCAT
+	select HAVE_SLP_S0_GATE
 
 if BOARD_GOOGLE_FATCAT_COMMON
 
@@ -161,7 +162,7 @@ config TPM_TIS_ACPI_INTERRUPT
 	default 47 if BOARD_GOOGLE_MODEL_FATCAT # GPE0_DW1_15 (GPP_D15)
 	default 79 if BOARD_GOOGLE_FELINO # GPE0_DW2_15 (GPP_F15)
 	default 11 if BOARD_GOOGLE_FRANCKA # GPE0_DW0_11 (GPP_H11)
-	default 47 if BOARD_GOOGLE_KINMEN # GPE0_DW1_15 (GPP_D15)
+	default 66 if BOARD_GOOGLE_KINMEN # GPE0_DW2_02 (GPP_E02)
 
 # FIXME: update as per board schematics
 config UART_FOR_CONSOLE
diff --git a/src/mainboard/google/fatcat/variants/baseboard/fatcat/include/baseboard/gpio.h b/src/mainboard/google/fatcat/variants/baseboard/fatcat/include/baseboard/gpio.h
index 65186d5a44..9adbb9212c 100644
--- a/src/mainboard/google/fatcat/variants/baseboard/fatcat/include/baseboard/gpio.h
+++ b/src/mainboard/google/fatcat/variants/baseboard/fatcat/include/baseboard/gpio.h
@@ -33,7 +33,8 @@
 #elif CONFIG(BOARD_GOOGLE_KINMEN)
  #define EC_SYNC_IRQ	GPP_E07_IRQ
  #define GPIO_PCH_WP	GPP_D02
-#define GPIO_SLP_S0_GATE	0 /* Not Connected */
+/* Used to gate SoC's SLP_S0# signal */
+#define GPIO_SLP_S0_GATE	GPP_V17
 #endif
 
 #endif /* __BASEBOARD_GPIO_H__ */
diff --git a/src/mainboard/google/fatcat/variants/kinmen/gpio.c b/src/mainboard/google/fatcat/variants/kinmen/gpio.c
index 6b67795410..ae339809e8 100644
--- a/src/mainboard/google/fatcat/variants/kinmen/gpio.c
+++ b/src/mainboard/google/fatcat/variants/kinmen/gpio.c
@@ -28,18 +28,20 @@ static const struct pad_config gpio_table[] = {
 	/* GPP_A06:     ESPI_RST_EC_R_N */
 	/*  GPP_A06 : GPP_A06 ==> ESPI_RST_HDR configured on reset, do not touch */
 
-	/* GPP_A09:     M.2_WWAN_FCP_OFF_N */
-	PAD_CFG_GPO(GPP_A09, 1, PLTRST),
-	/* GPP_A10:     M.2_WWAN_DISABLE_N */
-	PAD_CFG_GPO(GPP_A10, 1, PLTRST),
-	/* GPP_A11:     WLAN_RST_N */
-	PAD_CFG_GPO(GPP_A11, 1, PLTRST),
-	/* GPP_A12:     WIFI_WAKE_N */
-	PAD_CFG_GPI_SCI_LOW(GPP_A12, NONE, DEEP, LEVEL),
+	/* GPP_A08:     NC */
+	PAD_NC(GPP_A08, NONE),
+	/* GPP_A09:     NC */
+	PAD_NC(GPP_A09, NONE),
+	/* GPP_A10:     NC */
+	PAD_NC(GPP_A10, NONE),
+	/* GPP_A11:     NC */
+	PAD_NC(GPP_A11, NONE),
+	/* GPP_A12:     NC */
+	PAD_NC(GPP_A12, NONE),
 	/* GPP_A13:     MEM_STRAP_0 */
 	PAD_CFG_GPI(GPP_A13, NONE, DEEP),
-	/* GPP_A15:     GPP_A15_DNX_FORCE_RELOAD */
-	PAD_CFG_NF(GPP_A15, NONE, DEEP, NF1),
+	/* GPP_A15:     NC */
+	PAD_NC(GPP_A15, NONE),
 	/* GPP_A16:     BT_RF_KILL_N */
 	PAD_CFG_GPO(GPP_A16, 1, DEEP),
 	/* GPP_A17:     WIFI_RF_KILL_N */
@@ -49,39 +51,37 @@ static const struct pad_config gpio_table[] = {
 	PAD_CFG_NF(GPP_B00, NONE, DEEP, NF1),
 	/* GPP_B01:     USBC_SML_DATA_PD */
 	PAD_CFG_NF(GPP_B01, NONE, DEEP, NF1),
-	/* GPP_B02:     ISH_I2C0_SDA_SNSR_HDR */
-	/* NOTE: IOSSTAGE: 'Ignore' for S0ix */
-	PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_B02, NONE, DEEP, NF3),
-	/* GPP_B03:     ISH_I2C0_SCL_SNSR_HDR */
-	/* NOTE: IOSSTAGE: 'Ignore' for S0ix */
-	PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_B03, NONE, DEEP, NF3),
-	/* GPP_B04:     ISH_GP_0_SNSR_HDR */
-	PAD_CFG_NF(GPP_B04, NONE, DEEP, NF4),
+	/* GPP_B02:     NC */
+	PAD_NC(GPP_B02, NONE),
+	/* GPP_B03:     NC */
+	PAD_NC(GPP_B03, NONE),
+	/* GPP_B04:     NC */
+	PAD_NC(GPP_B04, NONE),
 	/* GPP_B05:     ISH_GP_1_SNSR_HDR */
 	PAD_CFG_NF(GPP_B05, NONE, DEEP, NF4),
-	/* GPP_B06:     ISH_GP_2_SNSR_HDR */
-	PAD_CFG_NF(GPP_B06, NONE, DEEP, NF4),
-	/* GPP_B07:     ISH_GP_3_SNSR_HDR */
-	PAD_CFG_NF(GPP_B07, NONE, DEEP, NF4),
-	/* GPP_B08:     ISH_GP_4_SNSR_HDR */
-	PAD_CFG_NF(GPP_B08, NONE, DEEP, NF4),
-	/* GPP_B09:     M2_GEN4_SSD_RESET_N */
-	PAD_CFG_GPO(GPP_B09, 1, PLTRST),
-	/* GPP_B10:     GEN4_SSD_PWREN */
-	PAD_CFG_GPO(GPP_B10, 1, PLTRST),
-	/* GPP_B11:     MOD_TCSS1_DISP_HPD3 */
-	PAD_CFG_NF(GPP_B11, NONE, DEEP, NF2),
+	/* GPP_B06:     NC */
+	PAD_NC(GPP_B06, NONE),
+	/* GPP_B07:     NC */
+	PAD_NC(GPP_B07, NONE),
+	/* GPP_B08:     NC */
+	PAD_NC(GPP_B08, NONE),
+	/* GPP_B09:     NC */
+	PAD_NC(GPP_B09, NONE),
+	/* GPP_B10:     NC */
+	PAD_NC(GPP_B10, NONE),
+	/* GPP_B11:     USB_OC1 */
+	PAD_CFG_NF(GPP_B11, NONE, DEEP, NF1),
 	/* GPP_B12:     PM_SLP_S0_N */
 	PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1),
 	/* GPP_B13:     PLT_RST_N */
 	PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1),
-	/* GPP_B14:     MOD_TCSS2_DISP_HPD4 */
+	/* GPP_B14:     DISP_HPD4 */
 	PAD_CFG_NF(GPP_B14, NONE, DEEP, NF2),
-	/* GPP_B15:     MOD_TCSS_USB_TYP_A_OC3_N */
-	PAD_CFG_NF(GPP_B15, NONE, DEEP, NF1),
+	/* GPP_B15:     NC */
+	PAD_NC(GPP_B15, NONE),
 	/* GPP_B16:     GEN5_SSD_PWREN */
 	PAD_CFG_GPO(GPP_B16, 1, PLTRST),
-	/* GPP_B17:     Not used */
+	/* GPP_B17:     NC */
 	PAD_NC(GPP_B17, NONE),
 	/* GPP_B18:     ISH_I2C2_SDA_SNSR_HDR */
 	/* NOTE: IOSSTAGE: 'Ignore' for S0ix */
@@ -89,78 +89,86 @@ static const struct pad_config gpio_table[] = {
 	/* GPP_B19:     ISH_I2C2_SCL_SNSR_HDR */
 	/* NOTE: IOSSTAGE: 'Ignore' for S0ix */
 	PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_B19, NONE, DEEP, NF1),
-	/* GPP_B20:     M.2_WWAN_RST_N */
-	PAD_CFG_GPO(GPP_B20, 1, PLTRST),
+	/* GPP_B20:     NC */
+	PAD_NC(GPP_B20, NONE),
 	/* GPP_B21:     TCP_RETIMER_FORCE_PWR */
 	PAD_CFG_GPO(GPP_B21, 0, DEEP),
 	/* GPP_B22:     ISH_GP_5_SNSR_HDR */
 	PAD_CFG_NF(GPP_B22, NONE, DEEP, NF4),
-	/* GPP_B23:     ISH_GP_6_SNSR_HDR */
-	PAD_CFG_NF(GPP_B23, NONE, DEEP, NF4),
+	/* GPP_B23:     NC */
+	PAD_NC(GPP_B23, NONE),
 	/* GPP_B24:     MEM_STRAP_3 */
 	PAD_CFG_GPI(GPP_B24, NONE, DEEP),
 	/* GPP_B25:     MEM_STRAP_2 */
 	PAD_CFG_GPI(GPP_B25, NONE, DEEP),
 
-	/* GPP_C00:     GPP_C0_SMBCLK */
-	PAD_CFG_NF(GPP_C00, NONE, DEEP, NF1),
-	/* GPP_C01:     GPP_C1_SMBDATA */
-	PAD_CFG_NF(GPP_C01, NONE, DEEP, NF1),
-	/* GPP_C02:     Not used */
+	/* GPP_C00:     NC */
+	PAD_NC(GPP_C00, NONE),
+	/* GPP_C01:     NC */
+	PAD_NC(GPP_C01, NONE),
+	/* GPP_C02:     NC */
 	PAD_NC(GPP_C02, NONE),
-	/* GPP_C03:     TCP_LAN_SML0_SCL_R */
-	PAD_CFG_NF(GPP_C03, NONE, DEEP, NF1),
-	/* GPP_C04:     TCP_LAN_SML0_SDA_R */
-	PAD_CFG_NF(GPP_C04, NONE, DEEP, NF1),
-	/* GPP_C06:     SML1_CLK */
-	PAD_CFG_NF(GPP_C06, NONE, DEEP, NF1),
+	/* GPP_C03:     NC */
+	PAD_NC(GPP_C03, NONE),
+	/* GPP_C04:     NC */
+	PAD_NC(GPP_C04, NONE),
+	/* GPP_C05:     NC */
+	PAD_NC(GPP_C05, NONE),
+	/* GPP_C06:     EN_FCAM_PWR */
+	PAD_CFG_GPO(GPP_C06, 1, DEEP),
 	/* GPP_C07:     MEM_CH_SEL */
 	PAD_CFG_GPI(GPP_C07, NONE, DEEP),
-	/* GPP_C09:     CLKREQ0_X8_GEN5_DT_CEM_SLOT_N */
-	PAD_CFG_NF(GPP_C09, NONE, DEEP, NF1),
+	/* GPP_C08:     NC */
+	PAD_NC(GPP_C08, NONE),
+	/* GPP_C09:     NC */
+	PAD_NC(GPP_C09, NONE),
 	/* GPP_C10:     CLKREQ1_X4_GEN5_M2_SSD_N */
 	PAD_CFG_NF(GPP_C10, NONE, DEEP, NF1),
-	/* GPP_C11:     CLKREQ2_X1_GEN4_DT_CEM_SLOT_N */
-	PAD_CFG_NF(GPP_C11, NONE, DEEP, NF1),
-	/* GPP_C12:     CLKREQ3_X1_GEN1_GBE_LAN_N */
-	PAD_CFG_NF(GPP_C12, NONE, DEEP, NF1),
+	/* GPP_C11:     NC */
+	PAD_NC(GPP_C11, NONE),
+	/* GPP_C12:     NC */
+	PAD_NC(GPP_C12, NONE),
 	/* GPP_C13:     CLKREQ4_X1_GEN4_M2_WLAN_N */
 	PAD_CFG_NF(GPP_C13, NONE, DEEP, NF1),
-	/* GPP_C14:     CLKREQ5_X1_GEN4_M2_WWAN_N */
-	PAD_CFG_NF(GPP_C14, NONE, DEEP, NF1),
+	/* GPP_C14:     NC */
+	PAD_NC(GPP_C14, NONE),
+	/* GPP_C15:     FPS_RST_N */
+	PAD_CFG_GPO_LOCK(GPP_C15, 1, LOCK_CONFIG),
 	/* GPP_C16:     TBT_LSX0_TXD  */
 	PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1),
 	/* GPP_C17:     TBT_LSX0_RXD  */
 	PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1),
-	/* GPP_C18:     TBT_LSX1_TXD  */
-	PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1),
-	/* GPP_C19:     TBT_LSX1_RXD */
-	PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1),
-	/* GPP_C20:     MOD_TCSS1_LS_TX_DDC_SCL */
+	/* GPP_C18:     NC */
+	PAD_NC(GPP_C18, NONE),
+	/* GPP_C19:     NC */
+	PAD_NC(GPP_C19, NONE),
+	/* GPP_C20:     TBT_LSX2_TXD */
 	PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1),
-	/* GPP_C21:     MOD_TCSS1_LS_RX_DDC_SDA */
+	/* GPP_C21:     TBT_LSX2_RXD */
 	PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1),
-	/* GPP_C22:     MOD_TCSS2_LS_TX_DDC_SCL */
+	/* GPP_C22:     DDP3_CTRLCLK */
 	PAD_CFG_NF(GPP_C22, NONE, DEEP, NF2),
-	/* GPP_C23:     MOD_TCSS2_LS_RX_DDC_SDA */
+	/* GPP_C23:     DDP3_CTRLDATA */
 	PAD_CFG_NF(GPP_C23, NONE, DEEP, NF2),
 
-	/* GPP_D00:     IMGCLKOUT_1 */
-	PAD_CFG_NF(GPP_D00, NONE, DEEP, NF1),
-	/* GPP_D02:     Not used */
-	PAD_NC(GPP_D02, NONE),
-	/* GPP_D03:     M.2_WWAN_PERST_GPIO_N */
-	PAD_CFG_GPO(GPP_D03, 1, PLTRST),
-	/* GPP_D04:     IMGCLKOUT_0 */
-	PAD_CFG_NF(GPP_D04, NONE, DEEP, NF1),
+	/* GPP_D00:     NC */
+	PAD_NC(GPP_D00, NONE),
+	/* GPP_D01:     NC */
+	PAD_NC(GPP_D01, NONE),
+	/* GPP_D02:     SOC_WP_OD */
+	PAD_CFG_GPI(GPP_D02, NONE, DEEP),
+	/* GPP_D03:     NC */
+	PAD_NC(GPP_D03, NONE),
+	/* GPP_D04:     NC */
+	PAD_NC(GPP_D04, NONE),
 	/* GPP_D05:     disable ISH_UART0_RXD */
 	PAD_NC(GPP_D05, NONE),
 	/* GPP_D07:     NC */
 	PAD_NC(GPP_D07, NONE),
 	/* GPP_D08:     NC */
 	PAD_NC(GPP_D08, NONE),
-	/* GPP_D09:     PEG_SLOT_RST_N */
-	PAD_CFG_GPO(GPP_D09, 1, PLTRST),
+	/* GPP_D09:     I2S_MCLK1_OUT */
+	PAD_CFG_NF(GPP_D09, NONE, DEEP, NF2),
 	/* GPP_D10:     HDA_BCLK */
 	PAD_CFG_NF(GPP_D10, NONE, DEEP, NF1),
 	/* GPP_D11:     HDA_SYNC */
@@ -169,64 +177,73 @@ static const struct pad_config gpio_table[] = {
 	PAD_CFG_NF(GPP_D12, NONE, DEEP, NF1),
 	/* GPP_D13:     HDA_SDI0 */
 	PAD_CFG_NF(GPP_D13, NONE, DEEP, NF1),
-	/* GPP_D14:     COINLESS_MODE_SELECT */
-	PAD_CFG_GPI_TRIG_OWN(GPP_D14, NONE, PLTRST, LEVEL, ACPI),
-	/* GPP_D15:     SPI_TPM_INT_N */
-	PAD_CFG_GPI_APIC_LOCK(GPP_D15, NONE, LEVEL, INVERT, LOCK_CONFIG),
-	/* GPP_D16:     HDA_RST_N_HDR */
-	PAD_CFG_NF(GPP_D16, NONE, DEEP, NF1),
-	/* GPP_D17:     HDA_SDI1_HDR */
-	PAD_CFG_NF(GPP_D17, NONE, DEEP, NF1),
-	/* GPP_D18:     CLKREQ6_X4_GEN4_M2_SSD_N */
-	PAD_CFG_NF(GPP_D18, NONE, DEEP, NF1),
+	/* GPP_D14:     NC */
+	PAD_NC(GPP_D14, NONE),
+	/* GPP_D15:     NC */
+	PAD_NC(GPP_D15, NONE),
+	/* GPP_D16:	DMIC_CLK */
+	PAD_CFG_NF(GPP_D16, NONE, DEEP, NF3),
+	/* GPP_D17:	DMIC_DATA */
+	PAD_CFG_NF(GPP_D17, NONE, DEEP, NF3),
+	/* GPP_D18:     NC */
+	PAD_NC(GPP_D18, NONE),
+	/* GPP_D19:     NC */
+	PAD_NC(GPP_D19, NONE),
 	/* GPP_D20:     CSE_EARLY_SW */
 	PAD_CFG_GPI_SCI_HIGH(GPP_D20, NONE, DEEP, LEVEL),
 	/* GPP_D21:     NC */
 	PAD_NC(GPP_D21, NONE),
-	/* GPP_D22:     BPKI3C_SDA */
-	PAD_CFG_NF(GPP_D22, NONE, DEEP, NF1),
-	/* GPP_D23:     BPKI3C_SCL */
-	PAD_CFG_NF(GPP_D23, NONE, DEEP, NF1),
+	/* GPP_D22:     NC */
+	PAD_NC(GPP_D22, NONE),
+	/* GPP_D23:     NC */
+	PAD_NC(GPP_D23, NONE),
 	/* GPP_D24:     MEM_STRAP_1 */
 	PAD_CFG_GPI(GPP_D24, NONE, DEEP),
-	/* GPP_D25:     X4_SLOT_WAKE_N */
-	PAD_CFG_GPI_SCI_LOW(GPP_D25, NONE, DEEP, LEVEL),
+	/* GPP_D25:     NC */
+	PAD_NC(GPP_D25, NONE),
 
-	/* GPP_E01:     CRD2_RST_N */
-	PAD_CFG_GPO(GPP_E01, 1, PLTRST),
-	/* GPP_E02:     WWAN_WAKE_GPIO_N  */
-	PAD_CFG_GPI_SCI_LOW(GPP_E02, NONE, DEEP, LEVEL),
-	/* GPP_E03:     M2_GEN5_SSD_RESET_N */
+	/* GPP_E01:     NC */
+	PAD_NC(GPP_E01, NONE),
+	/* GPP_E02:     GSC_SOC_INT_ODL */
+	PAD_CFG_GPI_APIC_LOCK(GPP_E02, NONE, LEVEL, INVERT, LOCK_CONFIG),
+	/* GPP_E03:     GEN5_SSD_RESET_N */
 	PAD_CFG_GPO(GPP_E03, 1, PLTRST),
-	/* GPP_E06:     SECURE_CAM_SW */
-	PAD_CFG_GPI_TRIG_OWN(GPP_E06, NONE, PLTRST, LEVEL, ACPI),
+	/* GPP_E05:     TCHSCR_RPT_EN */
+	PAD_CFG_GPO(GPP_E05, 0, PLTRST),
+	/* GPP_E06:     NC */
+	PAD_NC(GPP_E06, NONE),
 	/* GPP_E07 : [] ==> EC_SOC_INT_ODL */
 	PAD_CFG_GPI_APIC_LOCK(GPP_E07, NONE, LEVEL, INVERT, LOCK_CONFIG),
-	/* GPP_E08:     Not used */
+	/* GPP_E08:     NC */
 	PAD_NC(GPP_E08, NONE),
-	/* GPP_E09:     USB_RD_FP_CONN_12_OC0_N */
+	/* GPP_E09:     USB_OC0 */
 	PAD_CFG_NF(GPP_E09, NONE, DEEP, NF1),
-	/* GPP_E10:     CRD1_RST_N */
-	PAD_CFG_GPO(GPP_E10, 1, PLTRST),
-	/* GPP_E11:     THC0_SPI1_CLK_TCH_PNL1 */
-	PAD_CFG_NF(GPP_E11, NONE, DEEP, NF3),
-	/* GPP_E12:     THC0_SPI1_IO_0_I2C4_SCL_TCH_PNL1 */
-	PAD_CFG_NF(GPP_E12, NONE, DEEP, NF3),
-	/* GPP_E13:     THC0_SPI1_IO_1_I2C4_SDA_TCH_PNL1 */
-	PAD_CFG_NF(GPP_E13, NONE, DEEP, NF3),
-	/* GPP_E14:     THC0_SPI1_IO_2_TCH_PNL1 */
-	PAD_CFG_NF(GPP_E14, NONE, DEEP, NF3),
-	/* GPP_E15:     THC0_SPI1_IO_3_TCH_PNL1 */
-	PAD_CFG_NF(GPP_E15, NONE, DEEP, NF3),
-	/* GPP_E16:     THC0_SPI1_RST_N_TCH_PNL1 */
-	/* THC NOTE: use GPO instead of GPO for THC0 Rst */
-	PAD_CFG_GPO(GPP_E16, 1, DEEP),
-	/* GPP_E18:     THC0_SPI1_INT_N_TCH_PNL1 */
-	PAD_CFG_NF(GPP_E18, NONE, DEEP, NF3),
+	/* GPP_E10:     NC */
+	PAD_NC(GPP_E10, NONE),
+	/* GPP_E11:     GPSI0_CLK */
+	PAD_CFG_NF(GPP_E11, NONE, DEEP, NF5),
+	/* GPP_E12:     TCHPAD_I2C4_SCL */
+	PAD_CFG_NF(GPP_E12, NONE, DEEP, NF8),
+	/* GPP_E13:     TCHPAD_I2C4_SDA */
+	PAD_CFG_NF(GPP_E13, NONE, DEEP, NF8),
+	/* GPP_E14:     NC */
+	PAD_NC(GPP_E14, NONE),
+	/* GPP_E15:     NC */
+	PAD_NC(GPP_E15, NONE),
+	/* GPP_E16:     NC */
+	PAD_NC(GPP_E16, NONE),
+	/* GPP_E17:     GSPI0_CS0 */
+	PAD_CFG_NF(GPP_E17, NONE, DEEP, NF5),
+	/* GPP_E18:     TCHPAD_INT# */
+	PAD_CFG_GPI_APIC(GPP_E18, NONE, PLTRST, LEVEL, INVERT),
+	/* GPP_E19:     FPMCU_PWREN */
+	PAD_CFG_GPO(GPP_E19, 1, DEEP),
+	/* GPP_E20:     FPMCU_FW_UPDATE */
+	PAD_CFG_GPO_LOCK(GPP_E20, 0, LOCK_CONFIG),
 	/* GPP_E21:     I2C_PMC_PD_INT_N */
 	PAD_CFG_NF(GPP_E21, NONE, DEEP, NF1),
-	/* GPP_E22:     THC0_SPI1_DSYNC */
-	PAD_CFG_NF(GPP_E22, NONE, DEEP, NF3),
+	/* GPP_E22:     FPS_SOC_INT_L */
+	PAD_CFG_GPI_IRQ_WAKE(GPP_E22, NONE, PWROK, LEVEL, INVERT),
 
 	/* GPP_F00:     M.2_CNV_BRI_DT_BT_UART2_RTS_N */
 	/* NOTE: IOSSTAGE: 'Ignore' for S0ix */
@@ -246,46 +263,53 @@ static const struct pad_config gpio_table[] = {
 	/* GPP_F05:     CRF_CLKREQ_R */
 	/* NOTE: IOSSTAGE: 'Ignore' for S0ix */
 	PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_F05, NONE, DEEP, NF3),
-	/* GPP_F06:     WLAN_WWAN_COEX3 */
-	PAD_CFG_NF(GPP_F06, NONE, DEEP, NF1),
-	/* GPP_F07:     IMGCLKOUT_2 */
-	PAD_CFG_NF(GPP_F07, NONE, DEEP, NF2),
-	/* GPP_F08:     TCH_PNL1_PWR_EN */
-	PAD_CFG_GPO(GPP_F08, 1, PLTRST),
+	/* GPP_F06:     NC */
+	PAD_NC(GPP_F06, NONE),
+	/* GPP_F07:     NC */
+	PAD_NC(GPP_F07, NONE),
+	/* GPP_F08:     EN_TCHSCR_PWR */
+	PAD_CFG_GPO(GPP_F08, 1, DEEP),
 	/* GPP_F09:     NC */
 	PAD_NC(GPP_F09, NONE),
-	/* GPP_F10:     PEG_SLOT_PWR_EN_N */
-	PAD_CFG_GPO(GPP_F10, 0, PLTRST),
-	/* GPP_F11:     MOD_TCSS2_TYP_A_VBUS_EN */
-	PAD_CFG_GPO(GPP_F11, 1, DEEP),
-	/* GPP_F12:     THC_I2C1_SCL_TCH_PAD */
+	/* GPP_F10:     ISH_GP_6_SNSR_HDR */
+	PAD_CFG_NF(GPP_F10, NONE, DEEP, NF8),
+	/* GPP_F11:     NC */
+	PAD_NC(GPP_F11, NONE),
+	/* GPP_F12:     TCHSCR_I2C5_SCL */
 	PAD_CFG_NF(GPP_F12, NONE, DEEP, NF8),
-	/* GPP_F13:     THC_I2C1_SDA_TCH_PAD */
+	/* GPP_F13:     TCHSCR_I2C5_SDA */
 	PAD_CFG_NF(GPP_F13, NONE, DEEP, NF8),
-	/* GPP_F17:     Not used */
-	PAD_CFG_GPI_INT(GPP_F17, NONE, PLTRST, EDGE_BOTH),
-	/* GPP_F18:     TCH_PAD_INT_N */
-	/* NOTE: require rework to switch from GPP_A13 to GPP_F18 */
-	PAD_CFG_GPI_APIC(GPP_F18, NONE, PLTRST, LEVEL, INVERT),
-	/* GPP_F19:     GPP_PRIVACY_LED_CAM2 */
-	PAD_CFG_GPO(GPP_F19, 0, PLTRST),
-	/* GPP_F20:     GPP_PRIVACY_LED_CAM1_CVS_HST_WAKE */
-	PAD_CFG_GPO(GPP_F20, 0, PLTRST),
-	/* GPP_F22:     THC1_SPI2_DSYNC */
-	PAD_CFG_NF(GPP_F22, NONE, DEEP, NF3),
+	/* GPP_F14:     GPSI0A_MOSI */
+	PAD_CFG_NF(GPP_F14, NONE, DEEP, NF8),
+	/* GPP_F15:     GSPI0A_MISO */
+	PAD_CFG_NF(GPP_F15, NONE, DEEP, NF8),
+	/* GPP_F16:     TCHSCR_RST_L */
+	PAD_CFG_GPO(GPP_F16, 1, DEEP),
+	/* GPP_F17:     NC */
+	PAD_NC(GPP_F17, NONE),
+	/* GPP_F18:     TCHSCR_INT_L */
+	PAD_CFG_GPI_APIC(GPP_F18, NONE, PLTRST, LEVEL, NONE),
+	/* GPP_F19:     NC */
+	PAD_NC(GPP_F19, NONE),
+	/* GPP_F20:     NC */
+	PAD_NC(GPP_F20, NONE),
+	/* GPP_F22:     NC */
+	PAD_NC(GPP_F22, NONE),
+	/* GPP_F23:     NC */
+	PAD_NC(GPP_F23, NONE),
 
-	/* GPP_H00:     Not used */
+	/* GPP_H00:     NC */
 	PAD_NC(GPP_H00, NONE),
-	/* GPP_H01:     CRD_CAM_STROBE */
-	PAD_CFG_GPO(GPP_H01, 0, PLTRST),
-	/* GPP_H02:     DEBUG_TRACE_PNP */
-	PAD_CFG_GPO(GPP_H02, 1, PLTRST),
-	/* GPP_H03:     MIC MUTE */
-	PAD_CFG_NF(GPP_H03, NONE, DEEP, NF1),
-	/* GPP_H04:     I2C2_SDA_CAM_FLSH */
-	PAD_CFG_NF(GPP_H04, NONE, DEEP, NF1),
-	/* GPP_H05:     I2C2_SCL_CAM_FLSH */
-	PAD_CFG_NF(GPP_H05, NONE, DEEP, NF1),
+	/* GPP_H01:     NC */
+	PAD_NC(GPP_H01, NONE),
+	/* GPP_H02:     NC */
+	PAD_NC(GPP_H02, NONE),
+	/* GPP_H03:     NC */
+	PAD_NC(GPP_H03, NONE),
+	/* GPP_H04:     NC */
+	PAD_NC(GPP_H04, NONE),
+	/* GPP_H05:     NC */
+	PAD_NC(GPP_H05, NONE),
 	/* GPP_H06:     I2C3_SDA_PSS */
 	PAD_CFG_NF(GPP_H06, NONE, DEEP, NF1),
 	/* GPP_H07:     I2C3_SCL_PSS */
@@ -294,28 +318,28 @@ static const struct pad_config gpio_table[] = {
 	PAD_CFG_NF(GPP_H08, NONE, DEEP, NF1),
 	/* GPP_H09:     UART0_BUF_TXD */
 	PAD_CFG_NF(GPP_H09, NONE, DEEP, NF1),
-	/* GPP_H10:     UART0_BUF_RTS */
-	PAD_CFG_NF(GPP_H10, NONE, DEEP, NF1),
-	/* GPP_H11:     UART0_BUF_CTS */
-	PAD_CFG_NF(GPP_H11, NONE, DEEP, NF1),
+	/* GPP_H10:     NC */
+	PAD_NC(GPP_H10, NONE),
+	/* GPP_H11:     NC */
+	PAD_NC(GPP_H11, NONE),
 	/* GPP_H13:     CPU_C10_GATE_N_R */
 	PAD_CFG_NF(GPP_H13, NONE, DEEP, NF1),
 	/* GPP_H14:     NC */
 	PAD_NC(GPP_H14, NONE),
 	/* GPP_H15:     NC */
 	PAD_NC(GPP_H15, NONE),
-	/* GPP_H16:     WWAN_PWREN */
-	PAD_CFG_GPO(GPP_H16, 1, PLTRST),
-	/* GPP_H17:     MIC MUTE LED */
-	PAD_CFG_NF(GPP_H17, NONE, DEEP, NF1),
-	/* GPP_H19:     I3C0_SDA_HDR */
-	PAD_CFG_NF(GPP_H19, NONE, DEEP, NF2),
-	/* GPP_H20:     I3C0_SCL_HDR */
-	PAD_CFG_NF(GPP_H20, NONE, DEEP, NF2),
-	/* GPP_H21:     I2C1_SDA_I3C1_SDA_CAM_FLSH_CVS */
-	PAD_CFG_NF(GPP_H21, NONE, DEEP, NF1),
-	/* GPP_H22:     I2C1_SCL_I3C1_SCL_CAM_FLSH_CVS */
-	PAD_CFG_NF(GPP_H22, NONE, DEEP, NF1),
+	/* GPP_H16:     NC */
+	PAD_NC(GPP_H16, NONE),
+	/* GPP_H17:     NC */
+	PAD_NC(GPP_H17, NONE),
+	/* GPP_H19:     NC */
+	PAD_NC(GPP_H19, NONE),
+	/* GPP_H20:     NC */
+	PAD_NC(GPP_H20, NONE),
+	/* GPP_H21:     NC */
+	PAD_NC(GPP_H21, NONE),
+	/* GPP_H22:     NC */
+	PAD_NC(GPP_H22, NONE),
 
 	/* GPP_S00:     SNDW3_CLK_CODEC */
 	PAD_CFG_NF(GPP_S00, NONE, DEEP, NF1),
@@ -325,14 +349,14 @@ static const struct pad_config gpio_table[] = {
 	PAD_CFG_NF(GPP_S02, NONE, DEEP, NF1),
 	/* GPP_S03:     SNDW3_DATA2_CODEC */
 	PAD_CFG_NF(GPP_S03, NONE, DEEP, NF1),
-	/* GPP_S04:     SNDW2_CLK */
-	PAD_CFG_NF(GPP_S04, NONE, DEEP, NF2),
-	/* GPP_S05:     SNDW2_DATA0 */
-	PAD_CFG_NF(GPP_S05, NONE, DEEP, NF2),
-	/* GPP_S06:     SNDW1_CLK */
-	PAD_CFG_NF(GPP_S06, NONE, DEEP, NF3),
-	/* GPP_S07:     SNDW1_DATA0 */
-	PAD_CFG_NF(GPP_S07, NONE, DEEP, NF3),
+	/* GPP_S04:	DMIC_CLK_A0 */
+	PAD_CFG_NF(GPP_S04, NONE, DEEP, NF5),
+	/* GPP_S05:	DMIC_DATA_0 */
+	PAD_CFG_NF(GPP_S05, NONE, DEEP, NF5),
+	/* GPP_S06:     NC */
+	PAD_NC(GPP_S06, NONE),
+	/* GPP_S07:     NC */
+	PAD_NC(GPP_S07, NONE),
 
 	/* GPP_V00:     PM_BATLOW_N */
 	PAD_CFG_NF(GPP_V00, NONE, DEEP, NF1),
@@ -348,8 +372,8 @@ static const struct pad_config gpio_table[] = {
 	PAD_CFG_NF(GPP_V05, NONE, DEEP, NF1),
 	/* GPP_V06:     PM_SLP_A_N */
 	PAD_CFG_NF(GPP_V06, NONE, DEEP, NF1),
-	/* GPP_V07:     Not used */
-	PAD_NC(GPP_V07, NONE),
+	/* GPP_V07:     SUSCLK */
+	PAD_CFG_NF(GPP_V07, NONE, DEEP, NF1),
 	/* GPP_V08:     SLP_WLAN_N */
 	PAD_CFG_NF(GPP_V08, NONE, DEEP, NF1),
 	/* GPP_V09:     PM_SLP_S5_N */
@@ -368,8 +392,8 @@ static const struct pad_config gpio_table[] = {
 	PAD_CFG_NF(GPP_V15, NONE, DEEP, NF1),
 	/* GPP_V16:     GPP_V16_VCCST_EN */
 	PAD_CFG_NF(GPP_V16, NONE, DEEP, NF1),
-	/* GPP_V17:     TCP_RT_S0IX_ENTRY_EXIT_N */
-	PAD_CFG_GPO(GPP_V17, 1, DEEP),
+	/* GPP_V17:     SLP_S0_GATE_R */
+	PAD_CFG_GPO(GPP_V17, 1, PLTRST),
 };
 
 /* Early pad configuration in bootblock */
@@ -378,23 +402,32 @@ static const struct pad_config early_gpio_table[] = {
 	PAD_CFG_NF(GPP_H08, NONE, DEEP, NF1),
 	/* GPP_H09:     UART0_BUF_TXD */
 	PAD_CFG_NF(GPP_H09, NONE, DEEP, NF1),
-
 	/* GPP_H06: I2C3_SDA_PSS */
 	PAD_CFG_NF(GPP_H06, NONE, DEEP, NF1),
 	/* GPP_H07: I2C3_SCL_PSS */
 	PAD_CFG_NF(GPP_H07, NONE, DEEP, NF1),
-	/* GPP_D15: SPI_TPM_INT_N */
-	PAD_CFG_GPI_APIC(GPP_D15, NONE, PLTRST, LEVEL, INVERT),
+	/* GPP_E02: GSC_SOC_INT_ODL */
+	PAD_CFG_GPI_APIC(GPP_E02, NONE, PLTRST, LEVEL, INVERT),
 };
 
 /* Pad configuration in romstage */
 static const struct pad_config romstage_gpio_table[] = {
-	/* GPP_A08:     X1_PCIE_SLOT_PWR_EN */
-	PAD_CFG_GPO(GPP_A08, 0, PLTRST),
+	/* GPP_B16:     GEN5_SSD_PWREN */
+	PAD_CFG_GPO(GPP_B16, 1, PLTRST),
 	/* GPP_C00:     GPP_C0_SMBCLK */
 	PAD_CFG_NF(GPP_C00, NONE, DEEP, NF1),
 	/* GPP_C01:     GPP_C1_SMBDATA */
 	PAD_CFG_NF(GPP_C01, NONE, DEEP, NF1),
+	/* GPP_E03:     GEN5_SSD_RESET_N */
+	PAD_CFG_GPO(GPP_E03, 1, PLTRST),
+	/* GPP_E19:     FPMCU_PWREN */
+	PAD_CFG_GPO(GPP_E19, 0, DEEP),
+	/* GPP_C15:     FPS_RST_N */
+	PAD_CFG_GPO(GPP_C15, 0, DEEP),
+	/* GPP_F08:     EN_TCHSCR_PWR */
+	PAD_CFG_GPO(GPP_F08, 1, DEEP),
+	/* GPP_F16:     TCHSCR_RST_L */
+	PAD_CFG_GPO(GPP_F16, 0, DEEP),
 };
 
 const struct pad_config *variant_gpio_table(size_t *num)

From 98782a59e980830ce51495d85dd6c7d96543de9c Mon Sep 17 00:00:00 2001
From: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Date: Wed, 21 May 2025 09:46:49 +0800
Subject: [PATCH 1096/3886] mb/google/fatcat/var/kinmen: Add overridetree

Add override devicetree per schematic_20250520_v25.

BUG=b:409148565
TEST=emerge-fatcat coreboot

Change-Id: I05a89047331731321eae386076c6e4c2473d1a82
Signed-off-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87768
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
---
 .../fatcat/variants/kinmen/overridetree.cb    | 286 ++++++++++++++++++
 1 file changed, 286 insertions(+)

diff --git a/src/mainboard/google/fatcat/variants/kinmen/overridetree.cb b/src/mainboard/google/fatcat/variants/kinmen/overridetree.cb
index b012da9872..6f2b379ba0 100644
--- a/src/mainboard/google/fatcat/variants/kinmen/overridetree.cb
+++ b/src/mainboard/google/fatcat/variants/kinmen/overridetree.cb
@@ -1,8 +1,294 @@
 chip soc/intel/pantherlake
+
+	# The initial version temporarily uses the PTL-H,
+	# but the thermal design is based on the PTL-U.
+	# Apply PTL-U's thermal settings here to avoid thermal issues.
+	register "power_limits_config[PTL_H_1_CORE]" = "{
+		.tdp_pl1_override = 15,
+		.tdp_pl2_override = 55,
+		.tdp_pl4 = 152,
+	}"
+
+	register "power_limits_config[PTL_H_2_CORE]" = "{
+		.tdp_pl1_override = 15,
+		.tdp_pl2_override = 55,
+		.tdp_pl4 = 152,
+	}"
+
+	register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC_SKIP)"	# USB2_C0
+	register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC_SKIP)"	# USB2_C1
+	register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)"	# USB_CAMERA
+	register "usb2_ports[4]" = "USB2_PORT_MID(OC0)"		# Type-A Port A0
+	register "usb2_ports[5]" = "USB2_PORT_MID(OC1)"		# Type-A Port A1
+
+	register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)" # USB3.2 Type-A Port A0
+	register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC1)" # USB3.2 Type-A Port A1
+
+	register "tcss_ports[0]" = "TCSS_PORT_DEFAULT(OC_SKIP)" # USB3_C0
+	register "tcss_ports[2]" = "TCSS_PORT_DEFAULT(OC_SKIP)" # USB3_C1
+
+	register "tcss_cap_policy[0]" = "TCSS_TYPE_C_PORT_FULL_FUN"
+	register "tcss_cap_policy[2]" = "TCSS_TYPE_C_PORT_FULL_FUN"
+	register "tcss_cap_policy[3]" = "TCSS_TYPE_C_PORT_FULL_FUN"
+
+	# Enable EDP in PortA
+	register "ddi_port_A_config" = "1"
+	register "ddi_ports_config" = "{
+                [DDI_PORT_A] = DDI_ENABLE_HPD,
+	}"
+
+	# Enable CNVi Wi-Fi and Bluetooth
+	register "cnvi_wifi_core" = "true"
+	register "cnvi_bt_core" = "true"
+
+	register "serial_io_i2c_mode" = "{
+		[PchSerialIoIndexI2C0]  = PchSerialIoPci,
+		[PchSerialIoIndexI2C1] = PchSerialIoDisabled,
+		[PchSerialIoIndexI2C2] = PchSerialIoDisabled,
+		[PchSerialIoIndexI2C3]  = PchSerialIoPci,
+		[PchSerialIoIndexI2C4]  = PchSerialIoPci,
+		[PchSerialIoIndexI2C5]  = PchSerialIoPci,
+	}"
+
+	register "serial_io_gspi_mode" = "{
+		[PchSerialIoIndexGSPI0] = PchSerialIoPci,
+		[PchSerialIoIndexGSPI1] = PchSerialIoDisabled,
+		[PchSerialIoIndexGSPI0A] = PchSerialIoDisabled,
+	}"
+
+	# Intel Common SoC Config
+	#+-------------------+---------------------------+
+	#| Field             |  Value                    |
+	#+-------------------+---------------------------+
+	#| I2C3              | TPM(cr50)                 |
+	#| I2C4              | Touchpad                  |
+	#| I2C5              | Touchscreen               |
+	#+-------------------+---------------------------+
 	register "common_soc_config" = "{
 		.logo_valignment = FW_SPLASH_VALIGNMENT_MIDDLE,
+		.chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT,
+		.i2c[3] = {
+			.early_init = 1,
+			.speed = I2C_SPEED_FAST,
+		},
+		.i2c[4] = {
+			.speed = I2C_SPEED_FAST,
+		},
+		.i2c[5] = {
+			.speed = I2C_SPEED_FAST,
+		},
 	}"
 
 	device domain 0 on
+		device ref igpu on
+			chip drivers/gfx/generic
+				register "device_count" = "4"
+				# DDIA for eDP
+				register "device[0].name" = ""LCD0""
+				register "device[0].type" = "panel"
+				# HDMI
+				# If HDMI is not enumerated in the kernel, then no GFX device should be added for DDIB
+				register "device[1].name" = ""DD01""
+				# TCP0 (DP-1) for port C0
+				register "device[2].name" = ""DD02""
+				register "device[2].use_pld" = "true"
+				register "device[2].pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(1, 1))"
+				# TCP2 (DP-2) for port C1
+				register "device[3].name" = ""DD03""
+				register "device[3].use_pld" = "true"
+				register "device[3].pld" = "ACPI_PLD_TYPE_C(LEFT, RIGHT, ACPI_PLD_GROUP(2, 1))"
+				device generic 0 on end
+			end
+		end
+
+		device ref iaa off end
+		device ref tbt_pcie_rp0 on end
+		device ref tbt_pcie_rp2 on end
+		device ref tbt_pcie_rp3 on end
+		device ref tcss_xhci on
+			chip drivers/usb/acpi
+				device ref tcss_root_hub on
+					chip drivers/usb/acpi
+						register "desc" = ""USB3 Type-C Port C0""
+						register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
+						register "group" = "ACPI_PLD_GROUP(1, 2)"
+						device ref tcss_usb3_port0 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB3 Type-C Port C1""
+						register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
+						register "group" = "ACPI_PLD_GROUP(2, 2)"
+						device ref tcss_usb3_port2 on end
+					end
+				end
+			end
+		end
+
+		device ref tcss_dma0 on
+			chip drivers/intel/usb4/retimer
+				register "dfp[0].power_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B21)"
+				use tcss_usb3_port0 as dfp[0].typec_port
+				device generic 0 on end
+			end
+		end
+		device ref tcss_dma1 on
+			chip drivers/intel/usb4/retimer
+				register "dfp[0].power_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B21)"
+				use tcss_usb3_port2 as dfp[0].typec_port
+				device generic 0 on end
+			end
+		end
+
+		# ToDo: enable ISH b/415605634
+
+		device ref xhci on
+			chip drivers/usb/acpi
+				device ref xhci_root_hub on
+					chip drivers/usb/acpi
+						register "desc" = ""USB2 Type-C Port C0""
+						register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
+						register "group" = "ACPI_PLD_GROUP(1, 1)"
+						device ref usb2_port1 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB2 Type-C Port C1""
+						register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
+						register "group" = "ACPI_PLD_GROUP(2, 1)"
+						device ref usb2_port2 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB2 Camera""
+						register "type" = "UPC_TYPE_INTERNAL"
+						register "has_power_resource" = "true"
+						register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C06)"
+						device ref usb2_port3 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB2 Type-A Port 0""
+						register "type" = "UPC_TYPE_A"
+						register "group" = "ACPI_PLD_GROUP(3, 1)"
+						device ref usb2_port5 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB2 Type-A Port 1""
+						register "type" = "UPC_TYPE_A"
+						register "group" = "ACPI_PLD_GROUP(4, 1)"
+						device ref usb2_port6 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB3 Type-A Port 0""
+						register "type" = "UPC_TYPE_USB3_A"
+						register "group" = "ACPI_PLD_GROUP(3, 2)"
+						device ref usb3_port1 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB3 Type-A Port 1""
+						register "type" = "UPC_TYPE_USB3_A"
+						register "group" = "ACPI_PLD_GROUP(4, 2)"
+						device ref usb3_port2 on end
+					end
+				end
+			end
+		end
+
+		device ref pcie_rp9 on
+			register "pcie_rp[PCIE_RP(9)]" = "{
+			.clk_src = 1,
+			.clk_req = 1,
+			.flags = PCIE_RP_CLK_REQ_DETECT | PCIE_RP_LTR | PCIE_RP_AER,
+			}"
+			chip soc/intel/common/block/pcie/rtd3
+				register "is_storage" = "true"
+				register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B16)"
+				register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_E03)"
+				register "srcclk_pin" = "1"
+				device generic 0 on end
+			end
+		end # Gen5 M.2 SSD
+		device ref cnvi_wifi on
+			chip drivers/wifi/generic
+				register "wake" = "GPE0_PME_B0"
+				register "add_acpi_dma_property" = "true"
+				register "enable_cnvi_ddr_rfim" = "true"
+				use cnvi_bluetooth as bluetooth_companion
+				device generic 0 on end
+			end
+		end # CNVi
+
+		device ref cnvi_bluetooth on end
+
+		# NOTE: i2c0 is function 0; hence it needs to be enabled when any of i2c1-5 is enabled.
+		# TPM device is under i2c3. Therefore, i2c0 needs to be enabled anyways.
+		device ref i2c0 on end
+		device ref i2c3 on
+			chip drivers/i2c/tpm
+				register "hid" = ""GOOG0005""
+				register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_E02_IRQ)"
+				device i2c 50 on end
+			end
+		end # I2C3
+		device ref i2c4 on
+			chip drivers/i2c/hid
+				register "generic.hid" = ""PIXA2305""
+				register "generic.desc" = ""PIXA Touchpad""
+				register "generic.irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_E18_IRQ)"
+				# NOTE: pmc_gpe0_dw2 is GPP_E in baseboard devicetree.cb.
+				register "generic.wake" = "GPE0_DW2_18"
+				register "generic.detect" = "1"
+				register "hid_desc_reg_offset" = "0x20"
+				device i2c 68 on end
+			end
+		end # I2C4
+		device ref i2c5 on
+			chip drivers/i2c/hid
+				register "generic.hid" = ""ELAN9004""
+				register "generic.desc" = ""ELAN Touchscreen""
+				register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_F18)"
+				register "generic.detect" = "1"
+				register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_F16)"
+				register "generic.reset_delay_ms" = "150"
+				register "generic.reset_off_delay_ms" = "1"
+				register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_F08)"
+				register "generic.enable_delay_ms" = "6"
+				register "generic.enable_off_delay_ms" = "30"
+				register "generic.stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_E05)"
+				register "generic.stop_off_delay_ms" = "1"
+				register "generic.has_power_resource" = "1"
+				register "generic.use_gpio_for_status" = "true"
+				register "hid_desc_reg_offset" = "0x01"
+				device i2c 0x10 on end
+			end
+		end # I2C5
+		device ref gspi0 on
+			chip drivers/spi/acpi
+				register "name" = ""CRFP""
+				register "hid" = "ACPI_DT_NAMESPACE_HID"
+				register "uid" = "1"
+				register "compat_string" = ""google,cros-ec-spi""
+				register "irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_E22_IRQ)"
+				register "wake" = "GPE0_DW2_22"
+				register "has_power_resource" = "true"
+				register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C15)"
+				register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E19)"
+				register "enable_delay_ms" = "3"
+				device spi 0 on end
+			end
+		end
+
+		device ref smbus on end
+		device ref hda on
+			chip drivers/intel/soundwire
+				device generic 0 on
+					chip drivers/soundwire/alc711
+						register "desc" = ""Headset Codec""
+						register "alc711_address.version" = "SOUNDWIRE_VERSION_1_2"
+						register "alc711_address.class" = "MIPI_CLASS_SDCA"
+						register "alc711_address.part_id" = "MIPI_DEV_ID_REALTEK_ALC721"
+						# SoundWire Link 3 ID 1
+						device generic 3.1 on end
+					end
+				end
+			end
+		end
 	end
 end

From bc3af56fdddcfa727dd30915f2b769cafd63cba1 Mon Sep 17 00:00:00 2001
From: Zeroway Lin <zeroway.lin@mediatek.corp-partner.google.com>
Date: Tue, 3 Dec 2024 11:17:48 +0800
Subject: [PATCH 1097/3886] soc/mediatek/mt8189: Add SPM loader

Add support for loading SPM firmware from CBFS to SPM SRAM. SPM needs
its own firmware to enable SPM suspend/resume function which turns off
several resources such as DRAM/mainpll/26M clk when linux system
suspend.

coreboot log:
[INFO ]  CBFS: Found 'spm_firmware.pm' @0x197c0
size 0x2e56 in mcache @0xffffeb20
[DEBUG]  read SPI 0x41b7f8 0x2e56: 1793 us, 6615 KB/s,
52.920 Mbps
[DEBUG]  SPM: binary array size = 0xdd3
[DEBUG]  spm_kick_im_to_fetch: ptr = 0x4900001e
[DEBUG]  mtk_init_mcu: Loaded (and reset) spm_firmware.pm
 in 39 msecs (14224 bytes)

BUG=b:379008996
BRANCH=none
TEST=build pass

Signed-off-by: Zeroway Lin <zeroway.lin@mediatek.corp-partner.google.com>
Change-Id: Ia6731efbdf161353af537f3266edb578516fa92d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87759
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/soc/mediatek/mt8189/Kconfig           |   6 +
 src/soc/mediatek/mt8189/Makefile.mk       |   4 +-
 src/soc/mediatek/mt8189/include/soc/pll.h |   4 +-
 src/soc/mediatek/mt8189/include/soc/spm.h |  50 +-
 src/soc/mediatek/mt8189/spm.c             | 727 ++++++++++++++++++++++
 5 files changed, 786 insertions(+), 5 deletions(-)
 create mode 100644 src/soc/mediatek/mt8189/spm.c

diff --git a/src/soc/mediatek/mt8189/Kconfig b/src/soc/mediatek/mt8189/Kconfig
index 8d5fcc69e0..d6f4ca91dc 100644
--- a/src/soc/mediatek/mt8189/Kconfig
+++ b/src/soc/mediatek/mt8189/Kconfig
@@ -36,4 +36,10 @@ config DPM_PM_FIRMWARE
 	help
 	  The file name of the MediaTek DPM PM firmware.
 
+config SPM_FIRMWARE
+	string
+	default "spm_firmware.bin"
+	help
+	  The file name of the MediaTek SPM firmware.
+
 endif
diff --git a/src/soc/mediatek/mt8189/Makefile.mk b/src/soc/mediatek/mt8189/Makefile.mk
index 237cbaab0e..78d523b36e 100644
--- a/src/soc/mediatek/mt8189/Makefile.mk
+++ b/src/soc/mediatek/mt8189/Makefile.mk
@@ -45,6 +45,7 @@ ramstage-y += ../common/pmif_spi.c pmif_spi.c
 ramstage-y += ../common/pmif_spmi.c pmif_spmi.c
 ramstage-y += ../common/rtc.c ../common/rtc_mt6359p.c ../common/rtc_osc_init.c
 ramstage-y += soc.c
+ramstage-y += ../common/spm.c ../common/spm_v2.c spm.c
 ramstage-y += ../common/usb.c usb.c
 
 BL31_MAKEARGS += PLAT=mt8189
@@ -56,7 +57,8 @@ MT8189_BLOB_DIR := 3rdparty/blobs/soc/mediatek/mt8189
 
 firmware-files := \
 	$(CONFIG_DPM_DM_FIRMWARE) \
-	$(CONFIG_DPM_PM_FIRMWARE)
+	$(CONFIG_DPM_PM_FIRMWARE) \
+	$(CONFIG_SPM_FIRMWARE)
 
 $(foreach fw, $(call strip_quotes,$(firmware-files)), \
 	$(eval $(fw)-file := $(MT8189_BLOB_DIR)/$(fw)) \
diff --git a/src/soc/mediatek/mt8189/include/soc/pll.h b/src/soc/mediatek/mt8189/include/soc/pll.h
index e875663f9a..192bff5596 100644
--- a/src/soc/mediatek/mt8189/include/soc/pll.h
+++ b/src/soc/mediatek/mt8189/include/soc/pll.h
@@ -155,7 +155,8 @@ struct mtk_topckgen_regs {
 	struct mtk_clk_cfg clk_cfg_18;
 	u32 reserved5[24];
 	u32 clk_scp_cfg_0;
-	u32 reserved6[7];
+	u32 clk_scp_cfg_1;
+	u32 reserved6[6];
 	u32 clk26cali[2];
 	u32 reserved7[6];
 	struct mtk_clk_cfg clk_cfg_19;
@@ -175,6 +176,7 @@ check_member(mtk_topckgen_regs, clk_cfg_17.clr, 0x0188);
 check_member(mtk_topckgen_regs, clk_cfg_18.set, 0x0194);
 check_member(mtk_topckgen_regs, clk_cfg_18.clr, 0x0198);
 check_member(mtk_topckgen_regs, clk_scp_cfg_0, 0x0200);
+check_member(mtk_topckgen_regs, clk_scp_cfg_1, 0x0204);
 check_member(mtk_topckgen_regs, clk26cali, 0x0220);
 check_member(mtk_topckgen_regs, clk_cfg_19.set, 0x0244);
 check_member(mtk_topckgen_regs, clk_cfg_19.clr, 0x0248);
diff --git a/src/soc/mediatek/mt8189/include/soc/spm.h b/src/soc/mediatek/mt8189/include/soc/spm.h
index c504672b2a..b0be7d2990 100644
--- a/src/soc/mediatek/mt8189/include/soc/spm.h
+++ b/src/soc/mediatek/mt8189/include/soc/spm.h
@@ -13,6 +13,7 @@
 /* SPM READ/WRITE CFG */
 #define SPM_PROJECT_CODE			0xB16
 #define SPM_REGWR_CFG_KEY			(SPM_PROJECT_CODE << 16)
+#define SPM_SYSTEM_BASE_OFFSET			0x40000000
 
 /* POWERON_CONFIG_EN (0x1C001000 + 0x000) */
 #define BCLK_CG_EN_LSB				BIT(0)
@@ -66,6 +67,13 @@
 #define SYS_TIMER_ID_LSB			BIT(8)
 #define SYS_TIMER_VALID_LSB			BIT(31)
 
+#define AP_WDT_TIMEOUT_SUSPEND	5400 /* 90min */
+#define PCM_TIMER_SUSPEND	((AP_WDT_TIMEOUT_SUSPEND - 30) * 32768) /* 90min - 30sec */
+#define RG_AXI_DCM_DIS_EN	BIT(21)
+#define RG_PLLCK_SEL_NO_SPM	BIT(22)
+
+#define SPM_WAKEUP_EVENT_MASK_BIT0	BIT(0)
+
 /**************************************
  * Config and Parameter
  **************************************/
@@ -146,6 +154,28 @@ DEFINE_BIT(SPM_ACK_CHK_3_CON_EN_0, 4)
 DEFINE_BIT(SPM_ACK_CHK_3_CON_EN_1, 8)
 DEFINE_BIT(SPM_ACK_CHK_3_CON_HW_MODE_TRIG, 11)
 
+/* SPM Flags */
+#define SPM_FLAG_DISABLE_VCORE_DVS		BIT(8)
+#define SPM_FLAG_DISABLE_DDR_DFS		BIT(9)
+#define SPM_FLAG_DISABLE_EMI_DFS		BIT(10)
+#define SPM_FLAG_DISABLE_BUS_DFS		BIT(11)
+#define SPM_FLAG_RUN_COMMON_SCENARIO		BIT(19)
+
+/* SPM_EVENT_COUNTER_CLEAR (0x1C001000+0x8B8) */
+#define REG_SPM_EVENT_COUNTER_CLR_LSB		BIT(0)
+
+/* SYS_TIMER_CON (0x10006000+0x98C) */
+#define SYS_TIMER_START_EN_LSB			BIT(0)
+
+/* MD32PCM_CFGREG_SW_RSTN (0x10006000+0xA00) */
+DEFINE_BIT(MD32PCM_CFGREG_SW_RSTN_RESET, 0)
+
+/* MD32PCM_STA1 event */
+#define R12_CSYSPWREQ_B			BIT(24)
+
+/* SPM_EVENT_COUNTER_CLEAR (0x1C001000+0x8B8) */
+#define REG_SPM_EVENT_COUNTER_CLR_LSBBIT 0
+
 struct pwr_ctrl {
 	/* for SPM */
 	u32 pcm_flags;
@@ -856,8 +886,19 @@ struct mtk_spm_regs {
 	u32 spm_ack_chk_sta_2;
 	u32 spm_ack_chk_con_3;
 	u32 spm_ack_chk_sel_3;
-	u8 reserved23[1024];
-	u32 md1_pwr_con;
+	u32 md32pcm_cfgreg_sw_rstn; /* 0xA00 */
+	u8 reserved23[508];
+	u32 md32pcm_dma0_src; /* 0xC00 */
+	u32 md32pcm_dma0_dst;
+	u32 md32pcm_dma0_wppt;
+	u32 md32pcm_dma0_wpto;
+	u32 md32pcm_dma0_count;
+	u32 md32pcm_dma0_con;
+	u32 md32pcm_dma0_start; /* 0xC18 */
+	u8 reserved24[8];
+	u32 md32pcm_dma0_rlct; /* 0x0C24 */
+	u8 reserved25[472];
+	u32 md1_pwr_con; /* 0x0E00 */
 	u32 conn_pwr_con;
 	u32 ifr_pwr_con;
 	u32 peri_pwr_con;
@@ -952,7 +993,7 @@ struct mtk_spm_regs {
 	u32 edp_tx_pwr_con;
 	u32 pcie_pwr_con;
 	u32 pcie_phy_pwr_con;
-	u8 reserved24[4];
+	u8 reserved26[4];
 	u32 spm_twam_con;
 	u32 spm_twam_window_len;
 	u32 spm_twam_idle_sel;
@@ -969,6 +1010,9 @@ struct mtk_spm_regs {
 
 check_member(mtk_spm_regs, ap_mdsrc_req, 0x404);
 check_member(mtk_spm_regs, ulposc_con, 0x400);
+check_member(mtk_spm_regs, md32pcm_cfgreg_sw_rstn, 0xA00);
+check_member(mtk_spm_regs, md32pcm_dma0_src, 0xC00);
+check_member(mtk_spm_regs, md1_pwr_con, 0x0E00);
 check_member(mtk_spm_regs, conn_pwr_con, 0x0E04);
 check_member(mtk_spm_regs, ufs0_pwr_con, 0x0E10);
 check_member(mtk_spm_regs, audio_pwr_con, 0xe18);
diff --git a/src/soc/mediatek/mt8189/spm.c b/src/soc/mediatek/mt8189/spm.c
new file mode 100644
index 0000000000..90616495df
--- /dev/null
+++ b/src/soc/mediatek/mt8189/spm.c
@@ -0,0 +1,727 @@
+/* SPDX-License-Identifier: GPL-2.0-only OR MIT */
+
+#include <assert.h>
+#include <delay.h>
+#include <soc/mcu_common.h>
+#include <soc/pll.h>
+#include <soc/spm.h>
+#include <soc/spm_mtcmos.h>
+
+static const struct pwr_ctrl spm_init_ctrl = {
+	/* For SPM, this flag is not auto-gen. */
+	.pcm_flags = SPM_FLAG_DISABLE_VCORE_DVS
+		   | SPM_FLAG_DISABLE_DDR_DFS
+		   | SPM_FLAG_DISABLE_EMI_DFS
+		   | SPM_FLAG_DISABLE_BUS_DFS
+		   | SPM_FLAG_RUN_COMMON_SCENARIO,
+
+	/* SPM_SRC_REQ */
+	.reg_spm_adsp_mailbox_req = 0,
+	.reg_spm_apsrc_req = 0,
+	.reg_spm_ddren_req = 0,
+	.reg_spm_dvfs_req = 0,
+	.reg_spm_emi_req = 0,
+	.reg_spm_f26m_req = 0,
+	.reg_spm_infra_req = 0,
+	.reg_spm_pmic_req = 0,
+	.reg_spm_scp_mailbox_req = 0,
+	.reg_spm_sspm_mailbox_req = 0,
+	.reg_spm_sw_mailbox_req = 0,
+	.reg_spm_vcore_req = 1,
+	.reg_spm_vrf18_req = 0,
+	.adsp_mailbox_state = 0,
+	.apsrc_state = 0,
+	.ddren_state = 0,
+	.dvfs_state = 0,
+	.emi_state = 0,
+	.f26m_state = 0,
+	.infra_state = 0,
+	.pmic_state = 0,
+	.scp_mailbox_state = 0,
+	.sspm_mailbox_state = 0,
+	.sw_mailbox_state = 0,
+	.vcore_state = 0,
+	.vrf18_state = 0,
+
+	/* SPM_SRC_MASK_0 */
+	.reg_apu_apsrc_req_mask_b = 0x1,
+	.reg_apu_ddren_req_mask_b = 0x1,
+	.reg_apu_emi_req_mask_b = 0x1,
+	.reg_apu_infra_req_mask_b = 0x1,
+	.reg_apu_pmic_req_mask_b = 0x1,
+	.reg_apu_srcclkena_mask_b = 0x1,
+	.reg_apu_vrf18_req_mask_b = 0x1,
+	.reg_audio_dsp_apsrc_req_mask_b = 0x0,
+	.reg_audio_dsp_ddren_req_mask_b = 0x0,
+	.reg_audio_dsp_emi_req_mask_b = 0x0,
+	.reg_audio_dsp_infra_req_mask_b = 0x0,
+	.reg_audio_dsp_pmic_req_mask_b = 0x0,
+	.reg_audio_dsp_srcclkena_mask_b = 0x0,
+	.reg_audio_dsp_vcore_req_mask_b = 0x0,
+	.reg_audio_dsp_vrf18_req_mask_b = 0x0,
+	.reg_cam_apsrc_req_mask_b = 0x1,
+	.reg_cam_ddren_req_mask_b = 0x1,
+	.reg_cam_emi_req_mask_b = 0x1,
+	.reg_cam_infra_req_mask_b = 0x0,
+	.reg_cam_pmic_req_mask_b = 0x0,
+	.reg_cam_srcclkena_mask_b = 0x0,
+	.reg_cam_vrf18_req_mask_b = 0x0,
+	.reg_mdp_emi_req_mask_b = 0x1,
+
+	/* SPM_SRC_MASK_1 */
+	.reg_ccif_apsrc_req_mask_b = 0x0,
+	.reg_ccif_emi_req_mask_b = 0xfff,
+
+	/* SPM_SRC_MASK_2 */
+	.reg_ccif_infra_req_mask_b = 0x0,
+	.reg_ccif_pmic_req_mask_b = 0xfff,
+
+	/* SPM_SRC_MASK_3 */
+	.reg_ccif_srcclkena_mask_b = 0x0,
+	.reg_ccif_vrf18_req_mask_b = 0xfff,
+	.reg_ccu_apsrc_req_mask_b = 0x0,
+	.reg_ccu_ddren_req_mask_b = 0x0,
+	.reg_ccu_emi_req_mask_b = 0x0,
+	.reg_ccu_infra_req_mask_b = 0x0,
+	.reg_ccu_pmic_req_mask_b = 0x0,
+	.reg_ccu_srcclkena_mask_b = 0x0,
+	.reg_ccu_vrf18_req_mask_b = 0x0,
+	.reg_cg_check_apsrc_req_mask_b = 0x1,
+
+	/* SPM_SRC_MASK_4 */
+	.reg_cg_check_ddren_req_mask_b = 0x1,
+	.reg_cg_check_emi_req_mask_b = 0x1,
+	.reg_cg_check_infra_req_mask_b = 0x1,
+	.reg_cg_check_pmic_req_mask_b = 0x1,
+	.reg_cg_check_srcclkena_mask_b = 0x1,
+	.reg_cg_check_vcore_req_mask_b = 0x1,
+	.reg_cg_check_vrf18_req_mask_b = 0x1,
+	.reg_conn_apsrc_req_mask_b = 0x1,
+	.reg_conn_ddren_req_mask_b = 0x1,
+	.reg_conn_emi_req_mask_b = 0x1,
+	.reg_conn_infra_req_mask_b = 0x1,
+	.reg_conn_pmic_req_mask_b = 0x1,
+	.reg_conn_srcclkena_mask_b = 0x1,
+	.reg_conn_srcclkenb_mask_b = 0x1,
+	.reg_conn_vcore_req_mask_b = 0x1,
+	.reg_conn_vrf18_req_mask_b = 0x1,
+	.reg_cpueb_apsrc_req_mask_b = 0x1,
+	.reg_cpueb_ddren_req_mask_b = 0x1,
+	.reg_cpueb_emi_req_mask_b = 0x1,
+	.reg_cpueb_infra_req_mask_b = 0x1,
+	.reg_cpueb_pmic_req_mask_b = 0x1,
+	.reg_cpueb_srcclkena_mask_b = 0x1,
+	.reg_cpueb_vrf18_req_mask_b = 0x1,
+	.reg_disp0_apsrc_req_mask_b = 0x1,
+	.reg_disp0_ddren_req_mask_b = 0x1,
+	.reg_disp0_emi_req_mask_b = 0x1,
+	.reg_disp0_infra_req_mask_b = 0x1,
+	.reg_disp0_pmic_req_mask_b = 0x0,
+	.reg_disp0_srcclkena_mask_b = 0x0,
+	.reg_disp0_vrf18_req_mask_b = 0x1,
+	.reg_disp1_apsrc_req_mask_b = 0x0,
+	.reg_disp1_ddren_req_mask_b = 0x0,
+
+	/* SPM_SRC_MASK_5 */
+	.reg_disp1_emi_req_mask_b = 0x0,
+	.reg_disp1_infra_req_mask_b = 0x0,
+	.reg_disp1_pmic_req_mask_b = 0x0,
+	.reg_disp1_srcclkena_mask_b = 0x0,
+	.reg_disp1_vrf18_req_mask_b = 0x0,
+	.reg_dpm_apsrc_req_mask_b = 0xf,
+	.reg_dpm_ddren_req_mask_b = 0xf,
+	.reg_dpm_emi_req_mask_b = 0xf,
+	.reg_dpm_infra_req_mask_b = 0xf,
+	.reg_dpm_pmic_req_mask_b = 0xf,
+	.reg_dpm_srcclkena_mask_b = 0xf,
+
+	/* SPM_SRC_MASK_6 */
+	.reg_dpm_vcore_req_mask_b = 0xf,
+	.reg_dpm_vrf18_req_mask_b = 0xf,
+	.reg_dpmaif_apsrc_req_mask_b = 0x1,
+	.reg_dpmaif_ddren_req_mask_b = 0x1,
+	.reg_dpmaif_emi_req_mask_b = 0x1,
+	.reg_dpmaif_infra_req_mask_b = 0x1,
+	.reg_dpmaif_pmic_req_mask_b = 0x1,
+	.reg_dpmaif_srcclkena_mask_b = 0x1,
+	.reg_dpmaif_vrf18_req_mask_b = 0x1,
+	.reg_dvfsrc_level_req_mask_b = 0x1,
+	.reg_emisys_apsrc_req_mask_b = 0x0,
+	.reg_emisys_ddren_req_mask_b = 0x1,
+	.reg_emisys_emi_req_mask_b = 0x0,
+	.reg_gce_d_apsrc_req_mask_b = 0x1,
+	.reg_gce_d_ddren_req_mask_b = 0x1,
+	.reg_gce_d_emi_req_mask_b = 0x1,
+	.reg_gce_d_infra_req_mask_b = 0x0,
+	.reg_gce_d_pmic_req_mask_b = 0x0,
+	.reg_gce_d_srcclkena_mask_b = 0x0,
+	.reg_gce_d_vrf18_req_mask_b = 0x0,
+	.reg_gce_m_apsrc_req_mask_b = 0x1,
+	.reg_gce_m_ddren_req_mask_b = 0x1,
+	.reg_gce_m_emi_req_mask_b = 0x1,
+	.reg_gce_m_infra_req_mask_b = 0x0,
+	.reg_gce_m_pmic_req_mask_b = 0x0,
+	.reg_gce_m_srcclkena_mask_b = 0x0,
+
+	/* SPM_SRC_MASK_7 */
+	.reg_gce_m_vrf18_req_mask_b = 0x0,
+	.reg_gpueb_apsrc_req_mask_b = 0x0,
+	.reg_gpueb_ddren_req_mask_b = 0x0,
+	.reg_gpueb_emi_req_mask_b = 0x0,
+	.reg_gpueb_infra_req_mask_b = 0x0,
+	.reg_gpueb_pmic_req_mask_b = 0x0,
+	.reg_gpueb_srcclkena_mask_b = 0x0,
+	.reg_gpueb_vrf18_req_mask_b = 0x0,
+	.reg_hwccf_apsrc_req_mask_b = 0x1,
+	.reg_hwccf_ddren_req_mask_b = 0x1,
+	.reg_hwccf_emi_req_mask_b = 0x1,
+	.reg_hwccf_infra_req_mask_b = 0x1,
+	.reg_hwccf_pmic_req_mask_b = 0x1,
+	.reg_hwccf_srcclkena_mask_b = 0x1,
+	.reg_hwccf_vcore_req_mask_b = 0x1,
+	.reg_hwccf_vrf18_req_mask_b = 0x1,
+	.reg_img_apsrc_req_mask_b = 0x1,
+	.reg_img_ddren_req_mask_b = 0x1,
+	.reg_img_emi_req_mask_b = 0x1,
+	.reg_img_infra_req_mask_b = 0x0,
+	.reg_img_pmic_req_mask_b = 0x0,
+	.reg_img_srcclkena_mask_b = 0x0,
+	.reg_img_vrf18_req_mask_b = 0x0,
+	.reg_infrasys_apsrc_req_mask_b = 0x1,
+	.reg_infrasys_ddren_req_mask_b = 0x1,
+	.reg_infrasys_emi_req_mask_b = 0x1,
+	.reg_ipic_infra_req_mask_b = 0x1,
+	.reg_ipic_vrf18_req_mask_b = 0x1,
+	.reg_mcu_apsrc_req_mask_b = 0x0,
+	.reg_mcu_ddren_req_mask_b = 0x0,
+	.reg_mcu_emi_req_mask_b = 0x0,
+
+	/* SPM_SRC_MASK_8 */
+	.reg_mcusys_apsrc_req_mask_b = 0x7,
+	.reg_mcusys_ddren_req_mask_b = 0x7,
+	.reg_mcusys_emi_req_mask_b = 0x7,
+	.reg_mcusys_infra_req_mask_b = 0x0,
+
+	/* SPM_SRC_MASK_9 */
+	.reg_mcusys_pmic_req_mask_b = 0x0,
+	.reg_mcusys_srcclkena_mask_b = 0x0,
+	.reg_mcusys_vrf18_req_mask_b = 0x0,
+	.reg_md_apsrc_req_mask_b = 0x0,
+	.reg_md_ddren_req_mask_b = 0x0,
+	.reg_md_emi_req_mask_b = 0x0,
+	.reg_md_infra_req_mask_b = 0x0,
+	.reg_md_pmic_req_mask_b = 0x0,
+	.reg_md_srcclkena_mask_b = 0x0,
+	.reg_md_srcclkena1_mask_b = 0x0,
+	.reg_md_vcore_req_mask_b = 0x0,
+
+	/* SPM_SRC_MASK_10 */
+	.reg_md_vrf18_req_mask_b = 0x0,
+	.reg_mdp_apsrc_req_mask_b = 0x0,
+	.reg_mdp_ddren_req_mask_b = 0x0,
+	.reg_mm_proc_apsrc_req_mask_b = 0x0,
+	.reg_mm_proc_ddren_req_mask_b = 0x0,
+	.reg_mm_proc_emi_req_mask_b = 0x0,
+	.reg_mm_proc_infra_req_mask_b = 0x0,
+	.reg_mm_proc_pmic_req_mask_b = 0x0,
+	.reg_mm_proc_srcclkena_mask_b = 0x0,
+	.reg_mm_proc_vrf18_req_mask_b = 0x0,
+	.reg_mmsys_apsrc_req_mask_b = 0x0,
+	.reg_mmsys_ddren_req_mask_b = 0x0,
+	.reg_mmsys_vrf18_req_mask_b = 0x0,
+	.reg_pcie0_apsrc_req_mask_b = 0x0,
+	.reg_pcie0_ddren_req_mask_b = 0x0,
+	.reg_pcie0_infra_req_mask_b = 0x0,
+	.reg_pcie0_srcclkena_mask_b = 0x0,
+	.reg_pcie0_vrf18_req_mask_b = 0x0,
+	.reg_pcie1_apsrc_req_mask_b = 0x0,
+	.reg_pcie1_ddren_req_mask_b = 0x0,
+	.reg_pcie1_infra_req_mask_b = 0x0,
+	.reg_pcie1_srcclkena_mask_b = 0x0,
+	.reg_pcie1_vrf18_req_mask_b = 0x0,
+	.reg_perisys_apsrc_req_mask_b = 0x1,
+	.reg_perisys_ddren_req_mask_b = 0x1,
+	.reg_perisys_emi_req_mask_b = 0x1,
+	.reg_perisys_infra_req_mask_b = 0x1,
+	.reg_perisys_pmic_req_mask_b = 0x1,
+	.reg_perisys_srcclkena_mask_b = 0x1,
+	.reg_perisys_vcore_req_mask_b = 0x1,
+	.reg_perisys_vrf18_req_mask_b = 0x1,
+	.reg_scp_apsrc_req_mask_b = 0x1,
+
+	/* SPM_SRC_MASK_11 */
+	.reg_scp_ddren_req_mask_b = 0x1,
+	.reg_scp_emi_req_mask_b = 0x1,
+	.reg_scp_infra_req_mask_b = 0x1,
+	.reg_scp_pmic_req_mask_b = 0x1,
+	.reg_scp_srcclkena_mask_b = 0x1,
+	.reg_scp_vcore_req_mask_b = 0x1,
+	.reg_scp_vrf18_req_mask_b = 0x1,
+	.reg_srcclkeni_infra_req_mask_b = 0x1,
+	.reg_srcclkeni_pmic_req_mask_b = 0x1,
+	.reg_srcclkeni_srcclkena_mask_b = 0x1,
+	.reg_sspm_apsrc_req_mask_b = 0x1,
+	.reg_sspm_ddren_req_mask_b = 0x1,
+	.reg_sspm_emi_req_mask_b = 0x1,
+	.reg_sspm_infra_req_mask_b = 0x1,
+	.reg_sspm_pmic_req_mask_b = 0x1,
+	.reg_sspm_srcclkena_mask_b = 0x1,
+	.reg_sspm_vrf18_req_mask_b = 0x1,
+	.reg_ssr_apsrc_req_mask_b = 0x0,
+	.reg_ssr_ddren_req_mask_b = 0x0,
+	.reg_ssr_emi_req_mask_b = 0x0,
+	.reg_ssr_infra_req_mask_b = 0x0,
+	.reg_ssr_pmic_req_mask_b = 0x0,
+	.reg_ssr_srcclkena_mask_b = 0x0,
+	.reg_ssr_vrf18_req_mask_b = 0x0,
+	.reg_ufs_apsrc_req_mask_b = 0x1,
+	.reg_ufs_ddren_req_mask_b = 0x1,
+	.reg_ufs_emi_req_mask_b = 0x1,
+	.reg_ufs_infra_req_mask_b = 0x1,
+	.reg_ufs_pmic_req_mask_b = 0x1,
+
+	/* SPM_SRC_MASK_12 */
+	.reg_ufs_srcclkena_mask_b = 0x1,
+	.reg_ufs_vrf18_req_mask_b = 0x1,
+	.reg_vdec_apsrc_req_mask_b = 0x1,
+	.reg_vdec_ddren_req_mask_b = 0x1,
+	.reg_vdec_emi_req_mask_b = 0x1,
+	.reg_vdec_infra_req_mask_b = 0x0,
+	.reg_vdec_pmic_req_mask_b = 0x0,
+	.reg_vdec_srcclkena_mask_b = 0x0,
+	.reg_vdec_vrf18_req_mask_b = 0x0,
+	.reg_venc_apsrc_req_mask_b = 0x1,
+	.reg_venc_ddren_req_mask_b = 0x1,
+	.reg_venc_emi_req_mask_b = 0x1,
+	.reg_venc_infra_req_mask_b = 0x0,
+	.reg_venc_pmic_req_mask_b = 0x0,
+	.reg_venc_srcclkena_mask_b = 0x0,
+	.reg_venc_vrf18_req_mask_b = 0x0,
+	.reg_ipe_apsrc_req_mask_b = 0x1,
+	.reg_ipe_ddren_req_mask_b = 0x1,
+	.reg_ipe_emi_req_mask_b = 0x1,
+	.reg_ipe_infra_req_mask_b = 0x1,
+	.reg_ipe_pmic_req_mask_b = 0x1,
+	.reg_ipe_srcclkena_mask_b = 0x1,
+	.reg_ipe_vrf18_req_mask_b = 0x1,
+	.reg_ufs_vcore_req_mask_b = 0x1,
+
+	/* SPM_EVENT_CON_MISC */
+	.reg_srcclken_fast_resp = 0,
+	.reg_csyspwrup_ack_mask = 0,
+
+	/* Auto-gen End */
+
+	/* SPM_WAKEUP_EVENT_MASK */
+	.reg_wakeup_event_mask = 0xEFFFFFFF,
+
+	/* SPM_WAKEUP_EVENT_EXT_MASK */
+	.reg_ext_wakeup_event_mask = 0xFFFFFFFF,
+};
+
+static void spm_hw_s1_state_monitor_pause(void)
+{
+	SET32_BITFIELDS(&mtk_spm->spm_ack_chk_con_3,
+			SPM_ACK_CHK_3_CON_HW_MODE_TRIG, 1,
+			SPM_ACK_CHK_3_CON_CLR_ALL, 1,
+			SPM_ACK_CHK_3_CON_EN_0, 0,
+			SPM_ACK_CHK_3_CON_EN_1, 0);
+}
+
+void spm_set_power_control(const struct pwr_ctrl *pwrctrl)
+{
+	/* SPM_SRC_REQ */
+	write32(&mtk_spm->spm_src_req,
+		((pwrctrl->reg_spm_adsp_mailbox_req & 0x1) << 0) |
+		(((pwrctrl->reg_spm_apsrc_req) & 0x1) << 1) |
+		(((pwrctrl->reg_spm_ddren_req) & 0x1) << 2) |
+		((pwrctrl->reg_spm_dvfs_req & 0x1) << 3) |
+		(((pwrctrl->reg_spm_emi_req) & 0x1) << 4) |
+		(((pwrctrl->reg_spm_f26m_req) & 0x1) << 5) |
+		(((pwrctrl->reg_spm_infra_req) & 0x1) << 6) |
+		(((pwrctrl->reg_spm_pmic_req) & 0x1) << 7) |
+		((pwrctrl->reg_spm_scp_mailbox_req & 0x1) << 8) |
+		((pwrctrl->reg_spm_sspm_mailbox_req & 0x1) << 9) |
+		((pwrctrl->reg_spm_sw_mailbox_req & 0x1) << 10) |
+		(((pwrctrl->reg_spm_vcore_req) & 0x1) << 11) |
+		(((pwrctrl->reg_spm_vrf18_req) & 0x1) << 12) |
+		((pwrctrl->adsp_mailbox_state & 0x1) << 16) |
+		((pwrctrl->apsrc_state & 0x1) << 17) |
+		((pwrctrl->ddren_state & 0x1) << 18) |
+		((pwrctrl->dvfs_state & 0x1) << 19) |
+		((pwrctrl->emi_state & 0x1) << 20) |
+		((pwrctrl->f26m_state & 0x1) << 21) |
+		((pwrctrl->infra_state & 0x1) << 22) |
+		((pwrctrl->pmic_state & 0x1) << 23) |
+		((pwrctrl->scp_mailbox_state & 0x1) << 24) |
+		((pwrctrl->sspm_mailbox_state & 0x1) << 25) |
+		((pwrctrl->sw_mailbox_state & 0x1) << 26) |
+		((pwrctrl->vcore_state & 0x1) << 27) |
+		((pwrctrl->vrf18_state & 0x1) << 28));
+
+	/* SPM_SRC_MASK_0 */
+	write32(&mtk_spm->spm_src_mask_0,
+		((pwrctrl->reg_apu_apsrc_req_mask_b & 0x1) << 0) |
+		((pwrctrl->reg_apu_ddren_req_mask_b & 0x1) << 1) |
+		((pwrctrl->reg_apu_emi_req_mask_b & 0x1) << 2) |
+		((pwrctrl->reg_apu_infra_req_mask_b & 0x1) << 3) |
+		((pwrctrl->reg_apu_pmic_req_mask_b & 0x1) << 4) |
+		((pwrctrl->reg_apu_srcclkena_mask_b & 0x1) << 5) |
+		((pwrctrl->reg_apu_vrf18_req_mask_b & 0x1) << 6) |
+		((pwrctrl->reg_audio_dsp_apsrc_req_mask_b & 0x1) << 7) |
+		((pwrctrl->reg_audio_dsp_ddren_req_mask_b & 0x1) << 8) |
+		((pwrctrl->reg_audio_dsp_emi_req_mask_b & 0x1) << 9) |
+		((pwrctrl->reg_audio_dsp_infra_req_mask_b & 0x1) << 10) |
+		((pwrctrl->reg_audio_dsp_pmic_req_mask_b & 0x1) << 11) |
+		((pwrctrl->reg_audio_dsp_srcclkena_mask_b & 0x1) << 12) |
+		((pwrctrl->reg_audio_dsp_vcore_req_mask_b & 0x1) << 13) |
+		((pwrctrl->reg_audio_dsp_vrf18_req_mask_b & 0x1) << 14) |
+		((pwrctrl->reg_cam_apsrc_req_mask_b & 0x1) << 15) |
+		((pwrctrl->reg_cam_ddren_req_mask_b & 0x1) << 16) |
+		((pwrctrl->reg_cam_emi_req_mask_b & 0x1) << 17) |
+		((pwrctrl->reg_cam_infra_req_mask_b & 0x1) << 18) |
+		((pwrctrl->reg_cam_pmic_req_mask_b & 0x1) << 19) |
+		((pwrctrl->reg_cam_srcclkena_mask_b & 0x1) << 20) |
+		((pwrctrl->reg_cam_vrf18_req_mask_b & 0x1) << 21) |
+		((pwrctrl->reg_mdp_emi_req_mask_b & 0x1) << 22));
+
+	/* SPM_SRC_MASK_1 */
+	write32(&mtk_spm->spm_src_mask_1,
+		((pwrctrl->reg_ccif_apsrc_req_mask_b & 0xfff) << 0) |
+		((pwrctrl->reg_ccif_emi_req_mask_b & 0xfff) << 12));
+
+	/* SPM_SRC_MASK_2 */
+	write32(&mtk_spm->spm_src_mask_2,
+		((pwrctrl->reg_ccif_infra_req_mask_b & 0xfff) << 0) |
+		((pwrctrl->reg_ccif_pmic_req_mask_b & 0xfff) << 12));
+
+	/* SPM_SRC_MASK_3 */
+	write32(&mtk_spm->spm_src_mask_3,
+		((pwrctrl->reg_ccif_srcclkena_mask_b & 0xfff) << 0) |
+		((pwrctrl->reg_ccif_vrf18_req_mask_b & 0xfff) << 12) |
+		((pwrctrl->reg_ccu_apsrc_req_mask_b & 0x1) << 24) |
+		((pwrctrl->reg_ccu_ddren_req_mask_b & 0x1) << 25) |
+		((pwrctrl->reg_ccu_emi_req_mask_b & 0x1) << 26) |
+		((pwrctrl->reg_ccu_infra_req_mask_b & 0x1) << 27) |
+		((pwrctrl->reg_ccu_pmic_req_mask_b & 0x1) << 28) |
+		((pwrctrl->reg_ccu_srcclkena_mask_b & 0x1) << 29) |
+		((pwrctrl->reg_ccu_vrf18_req_mask_b & 0x1) << 30) |
+		((pwrctrl->reg_cg_check_apsrc_req_mask_b & 0x1) << 31));
+
+	/* SPM_SRC_MASK_4 */
+	write32(&mtk_spm->spm_src_mask_4,
+		((pwrctrl->reg_cg_check_ddren_req_mask_b & 0x1) << 0) |
+		((pwrctrl->reg_cg_check_emi_req_mask_b & 0x1) << 1) |
+		((pwrctrl->reg_cg_check_infra_req_mask_b & 0x1) << 2) |
+		((pwrctrl->reg_cg_check_pmic_req_mask_b & 0x1) << 3) |
+		((pwrctrl->reg_cg_check_srcclkena_mask_b & 0x1) << 4) |
+		((pwrctrl->reg_cg_check_vcore_req_mask_b & 0x1) << 5) |
+		((pwrctrl->reg_cg_check_vrf18_req_mask_b & 0x1) << 6) |
+		((pwrctrl->reg_conn_apsrc_req_mask_b & 0x1) << 7) |
+		((pwrctrl->reg_conn_ddren_req_mask_b & 0x1) << 8) |
+		((pwrctrl->reg_conn_emi_req_mask_b & 0x1) << 9) |
+		((pwrctrl->reg_conn_infra_req_mask_b & 0x1) << 10) |
+		((pwrctrl->reg_conn_pmic_req_mask_b & 0x1) << 11) |
+		((pwrctrl->reg_conn_srcclkena_mask_b & 0x1) << 12) |
+		((pwrctrl->reg_conn_srcclkenb_mask_b & 0x1) << 13) |
+		((pwrctrl->reg_conn_vcore_req_mask_b & 0x1) << 14) |
+		((pwrctrl->reg_conn_vrf18_req_mask_b & 0x1) << 15) |
+		((pwrctrl->reg_cpueb_apsrc_req_mask_b & 0x1) << 16) |
+		((pwrctrl->reg_cpueb_ddren_req_mask_b & 0x1) << 17) |
+		((pwrctrl->reg_cpueb_emi_req_mask_b & 0x1) << 18) |
+		((pwrctrl->reg_cpueb_infra_req_mask_b & 0x1) << 19) |
+		((pwrctrl->reg_cpueb_pmic_req_mask_b & 0x1) << 20) |
+		((pwrctrl->reg_cpueb_srcclkena_mask_b & 0x1) << 21) |
+		((pwrctrl->reg_cpueb_vrf18_req_mask_b & 0x1) << 22) |
+		((pwrctrl->reg_disp0_apsrc_req_mask_b & 0x1) << 23) |
+		((pwrctrl->reg_disp0_ddren_req_mask_b & 0x1) << 24) |
+		((pwrctrl->reg_disp0_emi_req_mask_b & 0x1) << 25) |
+		((pwrctrl->reg_disp0_infra_req_mask_b & 0x1) << 26) |
+		((pwrctrl->reg_disp0_pmic_req_mask_b & 0x1) << 27) |
+		((pwrctrl->reg_disp0_srcclkena_mask_b & 0x1) << 28) |
+		((pwrctrl->reg_disp0_vrf18_req_mask_b & 0x1) << 29) |
+		((pwrctrl->reg_disp1_apsrc_req_mask_b & 0x1) << 30) |
+		((pwrctrl->reg_disp1_ddren_req_mask_b & 0x1) << 31));
+
+	/* SPM_SRC_MASK_5 */
+	write32(&mtk_spm->spm_src_mask_5,
+		((pwrctrl->reg_disp1_emi_req_mask_b & 0x1) << 0) |
+		((pwrctrl->reg_disp1_infra_req_mask_b & 0x1) << 1) |
+		((pwrctrl->reg_disp1_pmic_req_mask_b & 0x1) << 2) |
+		((pwrctrl->reg_disp1_srcclkena_mask_b & 0x1) << 3) |
+		((pwrctrl->reg_disp1_vrf18_req_mask_b & 0x1) << 4) |
+		((pwrctrl->reg_dpm_apsrc_req_mask_b & 0xf) << 5) |
+		((pwrctrl->reg_dpm_ddren_req_mask_b & 0xf) << 9) |
+		((pwrctrl->reg_dpm_emi_req_mask_b & 0xf) << 13) |
+		((pwrctrl->reg_dpm_infra_req_mask_b & 0xf) << 17) |
+		((pwrctrl->reg_dpm_pmic_req_mask_b & 0xf) << 21) |
+		((pwrctrl->reg_dpm_srcclkena_mask_b & 0xf) << 25));
+
+	/* SPM_SRC_MASK_6 */
+	write32(&mtk_spm->spm_src_mask_6,
+		((pwrctrl->reg_dpm_vcore_req_mask_b & 0xf) << 0) |
+		((pwrctrl->reg_dpm_vrf18_req_mask_b & 0xf) << 4) |
+		((pwrctrl->reg_dpmaif_apsrc_req_mask_b & 0x1) << 8) |
+		((pwrctrl->reg_dpmaif_ddren_req_mask_b & 0x1) << 9) |
+		((pwrctrl->reg_dpmaif_emi_req_mask_b & 0x1) << 10) |
+		((pwrctrl->reg_dpmaif_infra_req_mask_b & 0x1) << 11) |
+		((pwrctrl->reg_dpmaif_pmic_req_mask_b & 0x1) << 12) |
+		((pwrctrl->reg_dpmaif_srcclkena_mask_b & 0x1) << 13) |
+		((pwrctrl->reg_dpmaif_vrf18_req_mask_b & 0x1) << 14) |
+		((pwrctrl->reg_dvfsrc_level_req_mask_b & 0x1) << 15) |
+		((pwrctrl->reg_emisys_apsrc_req_mask_b & 0x1) << 16) |
+		((pwrctrl->reg_emisys_ddren_req_mask_b & 0x1) << 17) |
+		((pwrctrl->reg_emisys_emi_req_mask_b & 0x1) << 18) |
+		((pwrctrl->reg_gce_d_apsrc_req_mask_b & 0x1) << 19) |
+		((pwrctrl->reg_gce_d_ddren_req_mask_b & 0x1) << 20) |
+		((pwrctrl->reg_gce_d_emi_req_mask_b & 0x1) << 21) |
+		((pwrctrl->reg_gce_d_infra_req_mask_b & 0x1) << 22) |
+		((pwrctrl->reg_gce_d_pmic_req_mask_b & 0x1) << 23) |
+		((pwrctrl->reg_gce_d_srcclkena_mask_b & 0x1) << 24) |
+		((pwrctrl->reg_gce_d_vrf18_req_mask_b & 0x1) << 25) |
+		((pwrctrl->reg_gce_m_apsrc_req_mask_b & 0x1) << 26) |
+		((pwrctrl->reg_gce_m_ddren_req_mask_b & 0x1) << 27) |
+		((pwrctrl->reg_gce_m_emi_req_mask_b & 0x1) << 28) |
+		((pwrctrl->reg_gce_m_infra_req_mask_b & 0x1) << 29) |
+		((pwrctrl->reg_gce_m_pmic_req_mask_b & 0x1) << 30) |
+		((pwrctrl->reg_gce_m_srcclkena_mask_b & 0x1) << 31));
+
+	/* SPM_SRC_MASK_7 */
+	write32(&mtk_spm->spm_src_mask_7,
+		((pwrctrl->reg_gce_m_vrf18_req_mask_b & 0x1) << 0) |
+		((pwrctrl->reg_gpueb_apsrc_req_mask_b & 0x1) << 1) |
+		((pwrctrl->reg_gpueb_ddren_req_mask_b & 0x1) << 2) |
+		((pwrctrl->reg_gpueb_emi_req_mask_b & 0x1) << 3) |
+		((pwrctrl->reg_gpueb_infra_req_mask_b & 0x1) << 4) |
+		((pwrctrl->reg_gpueb_pmic_req_mask_b & 0x1) << 5) |
+		((pwrctrl->reg_gpueb_srcclkena_mask_b & 0x1) << 6) |
+		((pwrctrl->reg_gpueb_vrf18_req_mask_b & 0x1) << 7) |
+		((pwrctrl->reg_hwccf_apsrc_req_mask_b & 0x1) << 8) |
+		((pwrctrl->reg_hwccf_ddren_req_mask_b & 0x1) << 9) |
+		((pwrctrl->reg_hwccf_emi_req_mask_b & 0x1) << 10) |
+		((pwrctrl->reg_hwccf_infra_req_mask_b & 0x1) << 11) |
+		((pwrctrl->reg_hwccf_pmic_req_mask_b & 0x1) << 12) |
+		((pwrctrl->reg_hwccf_srcclkena_mask_b & 0x1) << 13) |
+		((pwrctrl->reg_hwccf_vcore_req_mask_b & 0x1) << 14) |
+		((pwrctrl->reg_hwccf_vrf18_req_mask_b & 0x1) << 15) |
+		((pwrctrl->reg_img_apsrc_req_mask_b & 0x1) << 16) |
+		((pwrctrl->reg_img_ddren_req_mask_b & 0x1) << 17) |
+		((pwrctrl->reg_img_emi_req_mask_b & 0x1) << 18) |
+		((pwrctrl->reg_img_infra_req_mask_b & 0x1) << 19) |
+		((pwrctrl->reg_img_pmic_req_mask_b & 0x1) << 20) |
+		((pwrctrl->reg_img_srcclkena_mask_b & 0x1) << 21) |
+		((pwrctrl->reg_img_vrf18_req_mask_b & 0x1) << 22) |
+		((pwrctrl->reg_infrasys_apsrc_req_mask_b & 0x1) << 23) |
+		((pwrctrl->reg_infrasys_ddren_req_mask_b & 0x1) << 24) |
+		((pwrctrl->reg_infrasys_emi_req_mask_b & 0x1) << 25) |
+		((pwrctrl->reg_ipic_infra_req_mask_b & 0x1) << 26) |
+		((pwrctrl->reg_ipic_vrf18_req_mask_b & 0x1) << 27) |
+		((pwrctrl->reg_mcu_apsrc_req_mask_b & 0x1) << 28) |
+		((pwrctrl->reg_mcu_ddren_req_mask_b & 0x1) << 29) |
+		((pwrctrl->reg_mcu_emi_req_mask_b & 0x1) << 30));
+
+	/* SPM_SRC_MASK_8 */
+	write32(&mtk_spm->spm_src_mask_8,
+		((pwrctrl->reg_mcusys_apsrc_req_mask_b & 0xff) << 0) |
+		((pwrctrl->reg_mcusys_ddren_req_mask_b & 0xff) << 8) |
+		((pwrctrl->reg_mcusys_emi_req_mask_b & 0xff) << 16) |
+		((pwrctrl->reg_mcusys_infra_req_mask_b & 0xff) << 24));
+
+	/* SPM_SRC_MASK_9 */
+	write32(&mtk_spm->spm_src_mask_9,
+		((pwrctrl->reg_mcusys_pmic_req_mask_b & 0xff) << 0) |
+		((pwrctrl->reg_mcusys_srcclkena_mask_b & 0xff) << 8) |
+		((pwrctrl->reg_mcusys_vrf18_req_mask_b & 0xff) << 16) |
+		((pwrctrl->reg_md_apsrc_req_mask_b & 0x1) << 24) |
+		((pwrctrl->reg_md_ddren_req_mask_b & 0x1) << 25) |
+		((pwrctrl->reg_md_emi_req_mask_b & 0x1) << 26) |
+		((pwrctrl->reg_md_infra_req_mask_b & 0x1) << 27) |
+		((pwrctrl->reg_md_pmic_req_mask_b & 0x1) << 28) |
+		((pwrctrl->reg_md_srcclkena_mask_b & 0x1) << 29) |
+		((pwrctrl->reg_md_srcclkena1_mask_b & 0x1) << 30) |
+		((pwrctrl->reg_md_vcore_req_mask_b & 0x1) << 31));
+
+	/* SPM_SRC_MASK_10 */
+	write32(&mtk_spm->spm_src_mask_10,
+		((pwrctrl->reg_md_vrf18_req_mask_b & 0x1) << 0) |
+		((pwrctrl->reg_mdp_apsrc_req_mask_b & 0x1) << 1) |
+		((pwrctrl->reg_mdp_ddren_req_mask_b & 0x1) << 2) |
+		((pwrctrl->reg_mm_proc_apsrc_req_mask_b & 0x1) << 3) |
+		((pwrctrl->reg_mm_proc_ddren_req_mask_b & 0x1) << 4) |
+		((pwrctrl->reg_mm_proc_emi_req_mask_b & 0x1) << 5) |
+		((pwrctrl->reg_mm_proc_infra_req_mask_b & 0x1) << 6) |
+		((pwrctrl->reg_mm_proc_pmic_req_mask_b & 0x1) << 7) |
+		((pwrctrl->reg_mm_proc_srcclkena_mask_b & 0x1) << 8) |
+		((pwrctrl->reg_mm_proc_vrf18_req_mask_b & 0x1) << 9) |
+		((pwrctrl->reg_mmsys_apsrc_req_mask_b & 0x1) << 10) |
+		((pwrctrl->reg_mmsys_ddren_req_mask_b & 0x1) << 11) |
+		((pwrctrl->reg_mmsys_vrf18_req_mask_b & 0x1) << 12) |
+		((pwrctrl->reg_pcie0_apsrc_req_mask_b & 0x1) << 13) |
+		((pwrctrl->reg_pcie0_ddren_req_mask_b & 0x1) << 14) |
+		((pwrctrl->reg_pcie0_infra_req_mask_b & 0x1) << 15) |
+		((pwrctrl->reg_pcie0_srcclkena_mask_b & 0x1) << 16) |
+		((pwrctrl->reg_pcie0_vrf18_req_mask_b & 0x1) << 17) |
+		((pwrctrl->reg_pcie1_apsrc_req_mask_b & 0x1) << 18) |
+		((pwrctrl->reg_pcie1_ddren_req_mask_b & 0x1) << 19) |
+		((pwrctrl->reg_pcie1_infra_req_mask_b & 0x1) << 20) |
+		((pwrctrl->reg_pcie1_srcclkena_mask_b & 0x1) << 21) |
+		((pwrctrl->reg_pcie1_vrf18_req_mask_b & 0x1) << 22) |
+		((pwrctrl->reg_perisys_apsrc_req_mask_b & 0x1) << 23) |
+		((pwrctrl->reg_perisys_ddren_req_mask_b & 0x1) << 24) |
+		((pwrctrl->reg_perisys_emi_req_mask_b & 0x1) << 25) |
+		((pwrctrl->reg_perisys_infra_req_mask_b & 0x1) << 26) |
+		((pwrctrl->reg_perisys_pmic_req_mask_b & 0x1) << 27) |
+		((pwrctrl->reg_perisys_srcclkena_mask_b & 0x1) << 28) |
+		((pwrctrl->reg_perisys_vcore_req_mask_b & 0x1) << 29) |
+		((pwrctrl->reg_perisys_vrf18_req_mask_b & 0x1) << 30) |
+		((pwrctrl->reg_scp_apsrc_req_mask_b & 0x1) << 31));
+
+	/* SPM_SRC_MASK_11 */
+	write32(&mtk_spm->spm_src_mask_11,
+		((pwrctrl->reg_scp_ddren_req_mask_b & 0x1) << 0) |
+		((pwrctrl->reg_scp_emi_req_mask_b & 0x1) << 1) |
+		((pwrctrl->reg_scp_infra_req_mask_b & 0x1) << 2) |
+		((pwrctrl->reg_scp_pmic_req_mask_b & 0x1) << 3) |
+		((pwrctrl->reg_scp_srcclkena_mask_b & 0x1) << 4) |
+		((pwrctrl->reg_scp_vcore_req_mask_b & 0x1) << 5) |
+		((pwrctrl->reg_scp_vrf18_req_mask_b & 0x1) << 6) |
+		((pwrctrl->reg_srcclkeni_infra_req_mask_b & 0x3) << 7) |
+		((pwrctrl->reg_srcclkeni_pmic_req_mask_b & 0x3) << 9) |
+		((pwrctrl->reg_srcclkeni_srcclkena_mask_b & 0x3) << 11) |
+		((pwrctrl->reg_sspm_apsrc_req_mask_b & 0x1) << 13) |
+		((pwrctrl->reg_sspm_ddren_req_mask_b & 0x1) << 14) |
+		((pwrctrl->reg_sspm_emi_req_mask_b & 0x1) << 15) |
+		((pwrctrl->reg_sspm_infra_req_mask_b & 0x1) << 16) |
+		((pwrctrl->reg_sspm_pmic_req_mask_b & 0x1) << 17) |
+		((pwrctrl->reg_sspm_srcclkena_mask_b & 0x1) << 18) |
+		((pwrctrl->reg_sspm_vrf18_req_mask_b & 0x1) << 19) |
+		((pwrctrl->reg_ssr_apsrc_req_mask_b & 0x1) << 20) |
+		((pwrctrl->reg_ssr_ddren_req_mask_b & 0x1) << 21) |
+		((pwrctrl->reg_ssr_emi_req_mask_b & 0x1) << 22) |
+		((pwrctrl->reg_ssr_infra_req_mask_b & 0x1) << 23) |
+		((pwrctrl->reg_ssr_pmic_req_mask_b & 0x1) << 24) |
+		((pwrctrl->reg_ssr_srcclkena_mask_b & 0x1) << 25) |
+		((pwrctrl->reg_ssr_vrf18_req_mask_b & 0x1) << 26) |
+		((pwrctrl->reg_ufs_apsrc_req_mask_b & 0x1) << 27) |
+		((pwrctrl->reg_ufs_ddren_req_mask_b & 0x1) << 28) |
+		((pwrctrl->reg_ufs_emi_req_mask_b & 0x1) << 29) |
+		((pwrctrl->reg_ufs_infra_req_mask_b & 0x1) << 30) |
+		((pwrctrl->reg_ufs_pmic_req_mask_b & 0x1) << 31));
+
+	/* SPM_SRC_MASK_12 */
+	write32(&mtk_spm->spm_src_mask_12,
+		((pwrctrl->reg_ufs_srcclkena_mask_b & 0x1) << 0) |
+		((pwrctrl->reg_ufs_vrf18_req_mask_b & 0x1) << 1) |
+		((pwrctrl->reg_vdec_apsrc_req_mask_b & 0x1) << 2) |
+		((pwrctrl->reg_vdec_ddren_req_mask_b & 0x1) << 3) |
+		((pwrctrl->reg_vdec_emi_req_mask_b & 0x1) << 4) |
+		((pwrctrl->reg_vdec_infra_req_mask_b & 0x1) << 5) |
+		((pwrctrl->reg_vdec_pmic_req_mask_b & 0x1) << 6) |
+		((pwrctrl->reg_vdec_srcclkena_mask_b & 0x1) << 7) |
+		((pwrctrl->reg_vdec_vrf18_req_mask_b & 0x1) << 8) |
+		((pwrctrl->reg_venc_apsrc_req_mask_b & 0x1) << 9) |
+		((pwrctrl->reg_venc_ddren_req_mask_b & 0x1) << 10) |
+		((pwrctrl->reg_venc_emi_req_mask_b & 0x1) << 11) |
+		((pwrctrl->reg_venc_infra_req_mask_b & 0x1) << 12) |
+		((pwrctrl->reg_venc_pmic_req_mask_b & 0x1) << 13) |
+		((pwrctrl->reg_venc_srcclkena_mask_b & 0x1) << 14) |
+		((pwrctrl->reg_venc_vrf18_req_mask_b & 0x1) << 15) |
+		((pwrctrl->reg_ipe_apsrc_req_mask_b & 0x1) << 16) |
+		((pwrctrl->reg_ipe_ddren_req_mask_b & 0x1) << 17) |
+		((pwrctrl->reg_ipe_emi_req_mask_b & 0x1) << 18) |
+		((pwrctrl->reg_ipe_infra_req_mask_b & 0x1) << 19) |
+		((pwrctrl->reg_ipe_pmic_req_mask_b & 0x1) << 20) |
+		((pwrctrl->reg_ipe_srcclkena_mask_b & 0x1) << 21) |
+		((pwrctrl->reg_ipe_vrf18_req_mask_b & 0x1) << 22) |
+		((pwrctrl->reg_ufs_vcore_req_mask_b & 0x1) << 23));
+
+	/* SPM_EVENT_CON_MISC */
+	write32(&mtk_spm->spm_event_con_misc,
+		((pwrctrl->reg_srcclken_fast_resp & 0x1) << 0) |
+		((pwrctrl->reg_csyspwrup_ack_mask & 0x1) << 1));
+
+	/* SPM_WAKEUP_EVENT_MASK */
+	write32(&mtk_spm->spm_wakeup_event_mask,
+		((pwrctrl->reg_wakeup_event_mask & 0xffffffff) << 0));
+
+	/* SPM_WAKEUP_EVENT_EXT_MASK */
+	write32(&mtk_spm->spm_wakeup_event_ext_mask,
+		((pwrctrl->reg_ext_wakeup_event_mask & 0xffffffff) << 0));
+}
+
+void spm_register_init(void)
+{
+	/* SPM related clk setting  */
+	setbits32(&mtk_infracfg_ao->infra_bus_dcm_ctrl,
+		  RG_AXI_DCM_DIS_EN | RG_PLLCK_SEL_NO_SPM);
+
+	/* Enable scpsys(SPM) clock off control, 0: Topck AO */
+	setbits32(&mtk_topckgen->clk_scp_cfg_0, GENMASK(9, 0));
+	clrsetbits32(&mtk_topckgen->clk_scp_cfg_1, BIT(12) | GENMASK(3, 2), GENMASK(1, 0));
+
+	/* enable register control */
+	write32(&mtk_spm->poweron_config_set, SPM_REGWR_CFG_KEY | BCLK_CG_EN_LSB);
+
+	/* Power on spm sram */
+	clrbits32(&mtk_spm->spm_sram_con, GENMASK(19, 16));
+
+	/* SRAM Workaround for Sleep FSM */
+	setbits32(&mtk_spm->spm_sram_sleep_ctrl, BIT(9));
+
+	/* init power control register */
+	/* dram will set this register */
+	/* write32(SPM_POWER_ON_VAL0, POWER_ON_VAL0_DEF); */
+	write32(&mtk_spm->spm_power_on_val[1], POWER_ON_VAL1_DEF);
+
+	/* reset PCM */
+	write32(&mtk_spm->pcm_con0, SPM_REGWR_CFG_KEY | PCM_CK_EN_LSB | PCM_SW_RESET_LSB);
+	write32(&mtk_spm->pcm_con0, SPM_REGWR_CFG_KEY | PCM_CK_EN_LSB);
+	write32(&mtk_spm->pcm_con1, SPM_REGWR_CFG_KEY |
+		REG_SPM_APB_INTERNAL_EN_LSB | REG_SSPM_APB_P2P_EN_LSB);
+	/* initial SPM CLK control register */
+	clrsetbits32(&mtk_spm->spm_clk_con, GENMASK(23, 16), BIT(28) | GENMASK(6, 4));
+	setbits32(&mtk_spm->spm_clk_con1, BIT(0));
+
+	/* clean wakeup event raw status */
+	write32(&mtk_spm->spm_wakeup_event_mask, SPM_WAKEUP_EVENT_MASK_DEF);
+
+	/* clean ISR status */
+	write32(&mtk_spm->spm_irq_mask, ISRM_ALL);
+	write32(&mtk_spm->spm_irq_sta, ISRC_ALL);
+	write32(&mtk_spm->spm_swint_clr, PCM_SW_INT_ALL);
+
+	/* set SPM_AP_STANDBY_CON[5] csyspower_req_mask = 1 */
+	setbits32(&mtk_spm->spm_ap_standby_con, BIT(5));
+
+	/* disable r0 and r7 to control power */
+	write32(&mtk_spm->pcm_pwr_io_en, 0);
+
+	/* DDR EN de-bounce length to 5us */
+	write32(&mtk_spm->ddren_dbc_con, 0x154 | REG_DDREN_DBC_EN_LSB);
+
+	/* Init for SPM Resource ACK */
+	write32(&mtk_spm->spm_resource_ack_con0, 0xCC4E4ECC);
+	write32(&mtk_spm->spm_resource_ack_con1, 0x00CCCCCC);
+	write32(&mtk_spm->spm_resource_ack_mask0, 0x00000000);
+	write32(&mtk_spm->spm_resource_ack_mask1, 0x00000000);
+	write32(&mtk_spm->spm_resource_ack_mask2, 0x00000000);
+	write32(&mtk_spm->spm_resource_ack_mask3, 0x00000000);
+	write32(&mtk_spm->spm_resource_ack_mask4, 0x00000000);
+	write32(&mtk_spm->spm_resource_ack_mask5, 0x00000000);
+	write32(&mtk_spm->spm_resource_ack_mask6, 0x00000000);
+
+	/* Init VCORE DVFS Status */
+	clrsetbits32(&mtk_spm->spm_dvfs_con, SPM_DVFS_FORCE_ENABLE_LSB, SPM_DVFSRC_ENABLE_LSB);
+	write32(&mtk_spm->spm_dvfs_level, 0x00000001);
+	write32(&mtk_spm->spm_dvs_dfs_level, 0x00010001);
+
+	write32(&mtk_spm->spm_ack_chk_sel_3, SPM_ACK_CHK_3_SEL_HW_S1);
+	write32(&mtk_spm->spm_ack_chk_timer_3, SPM_ACK_CHK_3_HW_S1_CNT);
+
+	spm_hw_s1_state_monitor_pause();
+}
+
+const struct pwr_ctrl *get_pwr_ctrl(void)
+{
+	return &spm_init_ctrl;
+}

From 368eeb7da4ab7110bde3a8df9b2968a94f47360f Mon Sep 17 00:00:00 2001
From: Justin Yeh <justin.yeh@mediatek.corp-partner.google.com>
Date: Tue, 29 Oct 2024 16:41:00 +0800
Subject: [PATCH 1098/3886] soc/mediatek/mt8189: Add MCUPM loader

Add MCUPM loader for mt8189.

It takes 36 ms to load mcupm.bin.

coreboot logs:
CBFS: Found 'mcupm.bin' @0x10d00 size 0x7fd6 in mcache @0xffffeb20
mtk_init_mcu: Loaded (and reset) mcupm.bin in 36 msecs (84124 bytes)

BUG=b:379008996
BRANCH=none
TEST=build pass and we can see the mcupm logs after reset releases.

Signed-off-by: Justin Yeh <justin.yeh@mediatek.corp-partner.google.com>
Change-Id: I4f3a4eb63d801df123e45f46fc715c39d858c377
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87758
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
---
 src/soc/mediatek/mt8189/Kconfig               |   6 ++
 src/soc/mediatek/mt8189/Makefile.mk           |   3 +-
 .../mediatek/mt8189/include/soc/addressmap.h  |  11 +-
 .../mediatek/mt8189/include/soc/mcupm_plat.h  |  67 ++++++++++++
 src/soc/mediatek/mt8189/include/soc/spm.h     |   1 +
 src/soc/mediatek/mt8189/mcupm.c               | 100 ++++++++++++++++++
 src/soc/mediatek/mt8189/soc.c                 |   2 +
 7 files changed, 185 insertions(+), 5 deletions(-)
 create mode 100644 src/soc/mediatek/mt8189/include/soc/mcupm_plat.h
 create mode 100644 src/soc/mediatek/mt8189/mcupm.c

diff --git a/src/soc/mediatek/mt8189/Kconfig b/src/soc/mediatek/mt8189/Kconfig
index d6f4ca91dc..430b868582 100644
--- a/src/soc/mediatek/mt8189/Kconfig
+++ b/src/soc/mediatek/mt8189/Kconfig
@@ -36,6 +36,12 @@ config DPM_PM_FIRMWARE
 	help
 	  The file name of the MediaTek DPM PM firmware.
 
+config MCUPM_FIRMWARE
+	string
+	default "mcupm.bin"
+	help
+	  The file name of the MediaTek MCUPM firmware.
+
 config SPM_FIRMWARE
 	string
 	default "spm_firmware.bin"
diff --git a/src/soc/mediatek/mt8189/Makefile.mk b/src/soc/mediatek/mt8189/Makefile.mk
index 78d523b36e..fc1f8ff8f9 100644
--- a/src/soc/mediatek/mt8189/Makefile.mk
+++ b/src/soc/mediatek/mt8189/Makefile.mk
@@ -34,7 +34,7 @@ ramstage-$(CONFIG_ARM64_USE_ARM_TRUSTED_FIRMWARE) += ../common/bl31.c
 ramstage-y += ../common/dpm.c ../common/dpm_v2.c
 ramstage-y += ../common/dramc_info.c
 ramstage-y += ../common/emi.c
-ramstage-y += ../common/mcu.c
+ramstage-y += ../common/mcu.c mcupm.c
 ramstage-y += ../common/memory.c
 ramstage-y += ../common/mmu_operations.c ../common/mmu_cmops.c
 ramstage-y += ../common/mt6315.c mt6315.c
@@ -58,6 +58,7 @@ MT8189_BLOB_DIR := 3rdparty/blobs/soc/mediatek/mt8189
 firmware-files := \
 	$(CONFIG_DPM_DM_FIRMWARE) \
 	$(CONFIG_DPM_PM_FIRMWARE) \
+	$(CONFIG_MCUPM_FIRMWARE) \
 	$(CONFIG_SPM_FIRMWARE)
 
 $(foreach fw, $(call strip_quotes,$(firmware-files)), \
diff --git a/src/soc/mediatek/mt8189/include/soc/addressmap.h b/src/soc/mediatek/mt8189/include/soc/addressmap.h
index 3f6fe3e598..41d6557c7d 100644
--- a/src/soc/mediatek/mt8189/include/soc/addressmap.h
+++ b/src/soc/mediatek/mt8189/include/soc/addressmap.h
@@ -4,10 +4,13 @@
 #define __SOC_MEDIATEK_MT8189_INCLUDE_SOC_ADDRESSMAP_H__
 
 enum {
-	MCUCFG_BASE	= 0x0C530000,
-	DBGAO_BASE	= 0x0D01A000,
-	DEM_BASE	= 0x0D0A0000,
-	IO_PHYS		= 0x10000000,
+	GIC_BASE			= 0x0C000000,
+	MCUCFG_BASE			= 0x0C530000,
+	MCUPM_SRAM_BASE			= 0x0C540000,
+	MCUPM_CFG_BASE			= 0x0C580000,
+	DBGAO_BASE			= 0x0D01A000,
+	DEM_BASE			= 0x0D0A0000,
+	IO_PHYS				= 0x10000000,
 };
 
 enum {
diff --git a/src/soc/mediatek/mt8189/include/soc/mcupm_plat.h b/src/soc/mediatek/mt8189/include/soc/mcupm_plat.h
new file mode 100644
index 0000000000..4d8bc706e0
--- /dev/null
+++ b/src/soc/mediatek/mt8189/include/soc/mcupm_plat.h
@@ -0,0 +1,67 @@
+/* SPDX-License-Identifier: GPL-2.0-only OR MIT */
+
+#ifndef __SOC_MEDIATEK_MT8189_INCLUDE_SOC_MCUPM_PLAT_H__
+#define __SOC_MEDIATEK_MT8189_INCLUDE_SOC_MCUPM_PLAT_H__
+
+#include <soc/addressmap.h>
+
+#define MCUPM_SW_RSTN	MCUPM_CFG_BASE
+
+/*
+ * SPM config:
+ * Enable register access key, POWERON_CONFIG_EN = 0x0B160001
+ */
+#define DEVAPC_INFRA_SECU_AO_SEC_REPLACE_0	(DEVAPC_INFRA_SECU_AO_BASE + 0x0300)
+#define POLLING_ACK_RETRY_COUNTS	10
+#define POLLING_SRAM_RETRY_COUNTS	10
+
+/* CPUEB_PWR_CON (0x1C001000+0xEB4) */
+#define CPUEB_PWR_RST_B_LSB			BIT(0)
+#define CPUEB_PWR_ISO_LSB			BIT(1)
+#define CPUEB_PWR_ON_LSB			BIT(2)
+#define CPUEB_PWR_ON_2ND_LSB			BIT(3)
+#define CPUEB_PWR_CLK_DIS_LSB			BIT(4)
+#define CPUEB_SRAM_CKISO_LSB			BIT(5)
+#define CPUEB_SRAM_ISOINT_B_LSB			BIT(6)
+#define CPUEB_SRAM_PDN_LSB			BIT(8)
+#define CPUEB_SRAM_SLEEP_B_LSB			BIT(9)
+#define SC_CPUEB_SRAM_PDN_ACK_LSB		BIT(12)
+#define SC_CPUEB_SRAM_SLEEP_B_ACK_LSB		BIT(13)
+#define SC_CPUEB_PWR_ACK_LSB			BIT(30)
+#define SC_CPUEB_PWR_ACK_2ND_LSB		BIT(31)
+
+#define MCUPM_SRAM_SIZE		0x30000 /* 192K Bytes */
+
+#define MCUPM_LOADER_SIZE	0x2300 /* CFG_MTCMOS_OFF_SUPPORT */
+#define MCUPM_TCM_SZ		0x30000 /* 192K */
+#define MCUPM_IMG_OFS		0x2300 /* CFG_MTCMOS_OFF_SUPPORT */
+#define MCUPM_RDMP_OFS		0x30000
+
+#define ABNORMALBOOT_REG_STATUS			0x0
+#define WARMBOOT_REG_STATUS			0x0
+#define MCUPM_RSTN_RESET			0x1F
+#define MCUPM_RSTN_RSTN_INIT			0x0
+#define MCUPM_CFGREG_SW_RSTN_SW_RSTN		BIT(0)
+#define MCUPM_CFGREG_SW_RSTN_DMA_BUSY_MASK	BIT(1)
+
+#define MCUPM_GPR_SIZE		0x64
+#define SRAM_GPR_SIZE		0x4 /* 4 Bytes */
+#define IPI_NUMBER		8
+#define IPI_MBOX_TOTAL		IPI_NUMBER
+#define MBOX_SLOT_SIZE		0x4
+#define SRAM_SLOT_NUM		0x14 /* 0x14 = 20 slots = 20*4Bytes = 80 Bytes */
+#define PIN_S_NUM		SRAM_SLOT_NUM
+#define PIN_R_NUM		SRAM_SLOT_NUM
+#define MBOX_TABLE_NUM		(PIN_S_NUM + PIN_R_NUM)
+
+#define GPR_BASE_ADDR_MCU(x)	(MCUPM_SRAM_BASE + \
+				 MCUPM_SRAM_SIZE - \
+				 (IPI_MBOX_TOTAL * MBOX_TABLE_NUM * MBOX_SLOT_SIZE) - \
+				 MCUPM_GPR_SIZE + \
+				 ((x) * SRAM_GPR_SIZE))
+
+#define MCUPM_INFO				GPR_BASE_ADDR_MCU(0)
+#define ABNORMALBOOT_REG			GPR_BASE_ADDR_MCU(1)
+#define WARMBOOT_REG				GPR_BASE_ADDR_MCU(23)
+
+#endif
diff --git a/src/soc/mediatek/mt8189/include/soc/spm.h b/src/soc/mediatek/mt8189/include/soc/spm.h
index b0be7d2990..1e47d3a21c 100644
--- a/src/soc/mediatek/mt8189/include/soc/spm.h
+++ b/src/soc/mediatek/mt8189/include/soc/spm.h
@@ -1027,6 +1027,7 @@ check_member(mtk_spm_regs, dp_tx_pwr_con, 0x0E80);
 check_member(mtk_spm_regs, scp_peri_pwr_con, 0x0E88);
 check_member(mtk_spm_regs, csi_rx_pwr_con, 0x0E9C);
 check_member(mtk_spm_regs, ssusb_pwr_con, 0x0EA8);
+check_member(mtk_spm_regs, cpueb_pwr_con, 0x0EB0);
 check_member(mtk_spm_regs, mfg0_pwr_con, 0x0EB4);
 check_member(mtk_spm_regs, mfg3_pwr_con, 0x0EC0);
 check_member(mtk_spm_regs, pwr_status, 0x0F40);
diff --git a/src/soc/mediatek/mt8189/mcupm.c b/src/soc/mediatek/mt8189/mcupm.c
new file mode 100644
index 0000000000..cf4124f7bf
--- /dev/null
+++ b/src/soc/mediatek/mt8189/mcupm.c
@@ -0,0 +1,100 @@
+/* SPDX-License-Identifier: GPL-2.0-only OR MIT */
+
+#include <console/console.h>
+#include <delay.h>
+#include <device/mmio.h>
+#include <soc/addressmap.h>
+#include <soc/mcu_common.h>
+#include <soc/mcupm.h>
+#include <soc/mcupm_plat.h>
+#include <soc/spm.h>
+#include <soc/symbols.h>
+
+static void reset_mcupm(struct mtk_mcu *mcu)
+{
+	/* Clear abnormal boot register */
+	write32p(ABNORMALBOOT_REG, ABNORMALBOOT_REG_STATUS);
+	write32p(WARMBOOT_REG, WARMBOOT_REG_STATUS);
+	write32(&mcupm_reg->sw_rstn, MCUPM_RSTN_RESET);
+}
+
+static struct mtk_mcu mcupm = {
+	.firmware_name = CONFIG_MCUPM_FIRMWARE,
+	.run_address = (void *)MCUPM_SRAM_BASE,
+	.reset = reset_mcupm,
+};
+
+void mcupm_init(void)
+{
+	mcupm.load_buffer = _dram_dma;
+	mcupm.buffer_size = REGION_SIZE(dram_dma);
+
+	/* Set CPUEB as secure master */
+	setbits32(&mtk_spm->poweron_config_set, BIT(15));
+
+	/* Unlock SPM POWERON_CONFIG_EN */
+	setbits32(&mtk_spm->poweron_config_set, SPM_REGWR_CFG_KEY | BCLK_CG_EN_LSB);
+
+	/* Reinit CPUEB_PWR_CON */
+	/* (1) CPUEB MTCMOS */
+	setbits32(&mtk_spm->cpueb_pwr_con, CPUEB_PWR_ON_LSB);
+	setbits32(&mtk_spm->cpueb_pwr_con, CPUEB_PWR_ON_2ND_LSB);
+	u32 pwr_con_mask = SC_CPUEB_PWR_ACK_LSB | SC_CPUEB_PWR_ACK_2ND_LSB;
+	if (!retry(POLLING_ACK_RETRY_COUNTS,
+		   ((read32(&mtk_spm->cpueb_pwr_con) & pwr_con_mask) == pwr_con_mask),
+		   udelay(1))) {
+		printk(BIOS_ERR, "%s Polling ACK timeout, %#x\n", __func__,
+		       read32(&mtk_spm->cpueb_pwr_con));
+		return;
+	}
+
+	clrbits32(&mtk_spm->cpueb_pwr_con, CPUEB_PWR_CLK_DIS_LSB);
+	clrbits32(&mtk_spm->cpueb_pwr_con, CPUEB_PWR_ISO_LSB);
+	setbits32(&mtk_spm->cpueb_pwr_con, CPUEB_PWR_RST_B_LSB);
+
+	/* (2) SRAM leave DORMANT mode */
+	setbits32(&mtk_spm->cpueb_pwr_con, CPUEB_SRAM_SLEEP_B_LSB);
+	if (!retry(POLLING_ACK_RETRY_COUNTS,
+		   ((read32(&mtk_spm->cpueb_pwr_con) & SC_CPUEB_SRAM_SLEEP_B_ACK_LSB) != 0),
+		   udelay(1))) {
+		printk(BIOS_ERR, "%s Polling SRAM Sleep B ACK timeout, %#x\n", __func__,
+		       read32(&mtk_spm->cpueb_pwr_con));
+		return;
+	}
+
+	udelay(1);
+	setbits32(&mtk_spm->cpueb_pwr_con, CPUEB_SRAM_ISOINT_B_LSB);
+	clrbits32(&mtk_spm->cpueb_pwr_con, CPUEB_SRAM_CKISO_LSB);
+
+	/* Power on MCUPM sram */
+	clrbits32(&mtk_spm->cpueb_pwr_con, CPUEB_SRAM_PDN_LSB);
+	pwr_con_mask = SC_CPUEB_SRAM_PDN_ACK_LSB;
+	if (!retry(POLLING_SRAM_RETRY_COUNTS,
+		   (read32(&mtk_spm->cpueb_pwr_con) & pwr_con_mask) != pwr_con_mask,
+		   udelay(1))) {
+		printk(BIOS_ERR, "%s Polling SRAM Power on timeout, %#x\n", __func__,
+		       read32(&mtk_spm->cpueb_pwr_con));
+		return;
+	}
+
+	printk(BIOS_INFO, "%s Power on MCUPM SRAM success\n", __func__);
+
+	write32(&mcupm_reg->sw_rstn, MCUPM_RSTN_RSTN_INIT);
+	if (mtk_init_mcu(&mcupm))
+		die("%s() mtk_init_mcu failed\n", __func__);
+
+	setbits32p(MCUPM_SW_RSTN,
+		   MCUPM_CFGREG_SW_RSTN_SW_RSTN | MCUPM_CFGREG_SW_RSTN_DMA_BUSY_MASK);
+
+	printk(BIOS_DEBUG, "mcupm: MCUPM_SRAM_GPR0: %#x, %#x\n",
+	       MCUPM_INFO, read32p(MCUPM_INFO));
+	printk(BIOS_DEBUG, "mcupm: MCUPM_SRAM_GPR1: %#x, %#x\n",
+	       ABNORMALBOOT_REG, read32p(ABNORMALBOOT_REG));
+	printk(BIOS_DEBUG, "mcupm: MCUPM_SRAM_GPR23: %#x, %#x\n",
+	       WARMBOOT_REG, read32p(WARMBOOT_REG));
+	printk(BIOS_DEBUG, "mcupm: MCUPM_SW_RSTN: %#x, %#x\n",
+	       MCUPM_SW_RSTN, read32p(MCUPM_SW_RSTN));
+	printk(BIOS_DEBUG, "mcupm: MCUPM_SRAM_BASE: %#x, %#x\n",
+	       MCUPM_SRAM_BASE, read32p(MCUPM_SRAM_BASE));
+	printk(BIOS_DEBUG, "%s MCUPM part. load & reset finished\n", __func__);
+}
diff --git a/src/soc/mediatek/mt8189/soc.c b/src/soc/mediatek/mt8189/soc.c
index e53136d16b..93f6a4264c 100644
--- a/src/soc/mediatek/mt8189/soc.c
+++ b/src/soc/mediatek/mt8189/soc.c
@@ -4,6 +4,7 @@
 #include <device/device.h>
 #include <soc/dramc_info.h>
 #include <soc/emi.h>
+#include <soc/mcupm.h>
 #include <symbols.h>
 
 void bootmem_platform_add_ranges(void)
@@ -18,6 +19,7 @@ static void soc_read_resources(struct device *dev)
 
 static void soc_init(struct device *dev)
 {
+	mcupm_init();
 }
 
 static struct device_operations soc_ops = {

From 8ab9f5647004e03a9809634749b44f54d4f8064a Mon Sep 17 00:00:00 2001
From: Zeroway Lin <zeroway.lin@mediatek.corp-partner.google.com>
Date: Fri, 29 Nov 2024 15:33:05 +0800
Subject: [PATCH 1099/3886] mb/google/skywalker: Set up SPM in mainboard

Enable SPM booting process in mainboard.

BUG=b:379008996
BRANCH=none
TEST=build pass, spm init log:
[INFO ]  CBFS: Found 'spm_firmware.pm' @0x197c0 size
0x2e56 in mcache @0xffffeb20
[DEBUG]  read SPI 0x41b7f8 0x2e56: 1793 us, 6615 KB/s,
52.920 Mbps
[DEBUG]  SPM: binary array size = 0xdd3
[DEBUG]  spm_kick_im_to_fetch: ptr = 0x4900001e
[DEBUG]  mtk_init_mcu: Loaded (and reset) spm_firmware.pm
in 39 msecs (14224 bytes)

Signed-off-by: Zeroway Lin <zeroway.lin@mediatek.corp-partner.google.com>
Change-Id: Ie49cf0aea8bfaf507fff3cb8a8fc550634f83cbd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87760
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
---
 src/mainboard/google/skywalker/mainboard.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/src/mainboard/google/skywalker/mainboard.c b/src/mainboard/google/skywalker/mainboard.c
index 44549f46e5..d786f473d0 100644
--- a/src/mainboard/google/skywalker/mainboard.c
+++ b/src/mainboard/google/skywalker/mainboard.c
@@ -2,12 +2,14 @@
 
 #include <device/device.h>
 #include <soc/dpm_v2.h>
+#include <soc/spm_common.h>
 #include <soc/usb.h>
 
 static void mainboard_init(struct device *dev)
 {
 	dpm_init();
 	setup_usb_host();
+	spm_init();
 }
 
 static void mainboard_enable(struct device *dev)

From 8d25cf3ae719f8a4e85ec945ab9016feb023f02e Mon Sep 17 00:00:00 2001
From: "hailong.fan" <hailong.fan@mediatek.com>
Date: Wed, 9 Apr 2025 10:17:00 +0800
Subject: [PATCH 1100/3886] soc/mediatek/mt8189: Add SSPM loader

Secure System Power Manager (SSPM) provides power control in secure
domain. The initialization flow is to load SSPM firmware to its SRAM
space and then enable it. It takes 19 ms to load sspm.bin.

coreboot logs:
CBFS: Found 'sspm.bin' @0x26740 size 0x645b in mcache @0xfffdd1ec
mtk_init_mcu: Loaded (and reset) sspm.bin in 19 msecs (59392 bytes)

BUG=b:379008996
BRANCH=none
TEST=build pass and see SSPM firmware loading log

Signed-off-by: Hailong Fan <hailong.fan@mediatek.corp-partner.google.com>
Change-Id: I9be0e7ee3d003b5ee9e07e4f136795755a11c5bc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87761
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/soc/mediatek/mt8189/Kconfig                  | 6 ++++++
 src/soc/mediatek/mt8189/Makefile.mk              | 4 +++-
 src/soc/mediatek/mt8189/include/soc/addressmap.h | 2 ++
 src/soc/mediatek/mt8189/include/soc/spm.h        | 1 +
 src/soc/mediatek/mt8189/soc.c                    | 2 ++
 5 files changed, 14 insertions(+), 1 deletion(-)

diff --git a/src/soc/mediatek/mt8189/Kconfig b/src/soc/mediatek/mt8189/Kconfig
index 430b868582..f8ba8e4d26 100644
--- a/src/soc/mediatek/mt8189/Kconfig
+++ b/src/soc/mediatek/mt8189/Kconfig
@@ -48,4 +48,10 @@ config SPM_FIRMWARE
 	help
 	  The file name of the MediaTek SPM firmware.
 
+config SSPM_FIRMWARE
+	string
+	default "sspm.bin"
+	help
+	  The file name of the MediaTek SSPM firmware.
+
 endif
diff --git a/src/soc/mediatek/mt8189/Makefile.mk b/src/soc/mediatek/mt8189/Makefile.mk
index fc1f8ff8f9..b8ff8bff29 100644
--- a/src/soc/mediatek/mt8189/Makefile.mk
+++ b/src/soc/mediatek/mt8189/Makefile.mk
@@ -46,6 +46,7 @@ ramstage-y += ../common/pmif_spmi.c pmif_spmi.c
 ramstage-y += ../common/rtc.c ../common/rtc_mt6359p.c ../common/rtc_osc_init.c
 ramstage-y += soc.c
 ramstage-y += ../common/spm.c ../common/spm_v2.c spm.c
+ramstage-y += ../common/sspm.c ../common/sspm_sram.c
 ramstage-y += ../common/usb.c usb.c
 
 BL31_MAKEARGS += PLAT=mt8189
@@ -59,7 +60,8 @@ firmware-files := \
 	$(CONFIG_DPM_DM_FIRMWARE) \
 	$(CONFIG_DPM_PM_FIRMWARE) \
 	$(CONFIG_MCUPM_FIRMWARE) \
-	$(CONFIG_SPM_FIRMWARE)
+	$(CONFIG_SPM_FIRMWARE) \
+	$(CONFIG_SSPM_FIRMWARE)
 
 $(foreach fw, $(call strip_quotes,$(firmware-files)), \
 	$(eval $(fw)-file := $(MT8189_BLOB_DIR)/$(fw)) \
diff --git a/src/soc/mediatek/mt8189/include/soc/addressmap.h b/src/soc/mediatek/mt8189/include/soc/addressmap.h
index 41d6557c7d..61999e03b0 100644
--- a/src/soc/mediatek/mt8189/include/soc/addressmap.h
+++ b/src/soc/mediatek/mt8189/include/soc/addressmap.h
@@ -117,6 +117,8 @@ enum {
 	VLP_CK_BASE			= IO_PHYS + 0x0C012000,
 	PMICSPI_MST_BASE		= IO_PHYS + 0x0C013000,
 	DEVAPC_VLP_AO_BASE		= IO_PHYS + 0x0C018000,
+	SSPM_SRAM_BASE			= IO_PHYS + 0x0C300000,
+	SSPM_CFG_BASE			= IO_PHYS + 0x0C340000,
 	SCP_IIC_BASE			= IO_PHYS + 0x0C80A000,
 	SCP_BASE			= IO_PHYS + 0x0CB21000,
 	SPMI_MST_BASE			= IO_PHYS + 0x0CC00000,
diff --git a/src/soc/mediatek/mt8189/include/soc/spm.h b/src/soc/mediatek/mt8189/include/soc/spm.h
index 1e47d3a21c..2dea849ddf 100644
--- a/src/soc/mediatek/mt8189/include/soc/spm.h
+++ b/src/soc/mediatek/mt8189/include/soc/spm.h
@@ -1030,6 +1030,7 @@ check_member(mtk_spm_regs, ssusb_pwr_con, 0x0EA8);
 check_member(mtk_spm_regs, cpueb_pwr_con, 0x0EB0);
 check_member(mtk_spm_regs, mfg0_pwr_con, 0x0EB4);
 check_member(mtk_spm_regs, mfg3_pwr_con, 0x0EC0);
+check_member(mtk_spm_regs, sspm_sram_con, 0x0F04);
 check_member(mtk_spm_regs, pwr_status, 0x0F40);
 check_member(mtk_spm_regs, edp_tx_pwr_con, 0x0F70);
 
diff --git a/src/soc/mediatek/mt8189/soc.c b/src/soc/mediatek/mt8189/soc.c
index 93f6a4264c..697f4ddcf1 100644
--- a/src/soc/mediatek/mt8189/soc.c
+++ b/src/soc/mediatek/mt8189/soc.c
@@ -5,6 +5,7 @@
 #include <soc/dramc_info.h>
 #include <soc/emi.h>
 #include <soc/mcupm.h>
+#include <soc/sspm.h>
 #include <symbols.h>
 
 void bootmem_platform_add_ranges(void)
@@ -20,6 +21,7 @@ static void soc_read_resources(struct device *dev)
 static void soc_init(struct device *dev)
 {
 	mcupm_init();
+	sspm_init();
 }
 
 static struct device_operations soc_ops = {

From 3d40b7d018f5b6846afe2e46ce70621e9a934178 Mon Sep 17 00:00:00 2001
From: Wentao Qin <qinwentao@huaqin.corp-partner.google.com>
Date: Tue, 11 Feb 2025 15:18:34 +0800
Subject: [PATCH 1101/3886] soc/mediatek/mt8189: Increase bootblock size from
 60KB to 70KB

Increase the bootblock size to support TPM.

BUG=b:395784036
BRANCH=none
TEST=Build pass

Change-Id: Ieabb30b0458f6275bda14602126e0ccabbd7a714
Signed-off-by: Wentao Qin <qinwentao@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87771
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
---
 src/soc/mediatek/mt8189/include/soc/memlayout.ld | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/soc/mediatek/mt8189/include/soc/memlayout.ld b/src/soc/mediatek/mt8189/include/soc/memlayout.ld
index b3ca9b76a4..66705329d2 100644
--- a/src/soc/mediatek/mt8189/include/soc/memlayout.ld
+++ b/src/soc/mediatek/mt8189/include/soc/memlayout.ld
@@ -44,7 +44,7 @@ SECTIONS
 	 * is fixed at SRAM_L2C_START + 4K, and the 4K can be reused after bootblock is started.
 	 * To move the address, gen-bl-img.py also needs to be modified accordingly.
 	 */
-	BOOTBLOCK(0x02001000, 60K)
+	BOOTBLOCK(0x02001000, 70K)
 	#endif
 
 	OVERLAP_DECOMPRESSOR_VERSTAGE_ROMSTAGE(0x0207D000, 272K)

From bcbe17dea3c004f85abd0e56b51f0df0aab6bd67 Mon Sep 17 00:00:00 2001
From: Wentao Qin <qinwentao@huaqin.corp-partner.google.com>
Date: Tue, 11 Feb 2025 14:44:54 +0800
Subject: [PATCH 1102/3886] mb/google/skywalker: Configure TPM

Initialize I2C bus 3 for TPM control and enable vboot secdata.

BUG=b:395723580
BRANCH=none
TEST=check boot log

Change-Id: I34da1a494e71bdaac0223d1db918fffe12f68df4
Signed-off-by: Wentao Qin <qinwentao@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87772
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/google/skywalker/Kconfig     | 13 +++++++++++--
 src/mainboard/google/skywalker/bootblock.c |  4 ++++
 src/mainboard/google/skywalker/chromeos.c  |  8 ++++++++
 src/mainboard/google/skywalker/gpio.h      |  1 +
 4 files changed, 24 insertions(+), 2 deletions(-)

diff --git a/src/mainboard/google/skywalker/Kconfig b/src/mainboard/google/skywalker/Kconfig
index 4287636c82..2bdb0df18a 100644
--- a/src/mainboard/google/skywalker/Kconfig
+++ b/src/mainboard/google/skywalker/Kconfig
@@ -11,8 +11,6 @@ if BOARD_GOOGLE_SKYWALKER_COMMON
 config VBOOT
 	select EC_GOOGLE_CHROMEEC_SWITCHES
 	select VBOOT_VBNV_FLASH
-	select VBOOT_NO_BOARD_SUPPORT
-	select VBOOT_MOCK_SECDATA
 
 config BOARD_SPECIFIC_OPTIONS
 	def_bool y
@@ -26,6 +24,9 @@ config BOARD_SPECIFIC_OPTIONS
 	select EC_GOOGLE_CHROMEEC
 	select EC_GOOGLE_CHROMEEC_BOARDID
 	select EC_GOOGLE_CHROMEEC_SPI
+	select I2C_TPM if VBOOT
+	select MAINBOARD_HAS_TPM2 if VBOOT
+	select TPM_GOOGLE_TI50 if VBOOT
 	select FW_CONFIG
 	select FW_CONFIG_SOURCE_CHROMEEC_CBI
 	select RTC
@@ -48,4 +49,12 @@ config EC_GOOGLE_CHROMEEC_SPI_BUS
 	hex
 	default 0x0
 
+config DRIVER_TPM_I2C_BUS
+	hex
+	default 0x3
+
+config DRIVER_TPM_I2C_ADDR
+	hex
+	default 0x50
+
 endif
diff --git a/src/mainboard/google/skywalker/bootblock.c b/src/mainboard/google/skywalker/bootblock.c
index b090924b77..330bd6a541 100644
--- a/src/mainboard/google/skywalker/bootblock.c
+++ b/src/mainboard/google/skywalker/bootblock.c
@@ -2,6 +2,8 @@
 
 #include <bootblock_common.h>
 #include <gpio.h>
+#include <soc/gpio.h>
+#include <soc/i2c.h>
 #include <soc/spi.h>
 
 #include "gpio.h"
@@ -13,8 +15,10 @@ static void usb3_hub_reset(void)
 
 void bootblock_mainboard_init(void)
 {
+	mtk_i2c_bus_init(CONFIG_DRIVER_TPM_I2C_BUS, I2C_SPEED_FAST_PLUS);
 	mtk_spi_init(CONFIG_EC_GOOGLE_CHROMEEC_SPI_BUS, SPI_PAD0_MASK, 3 * MHz, 0);
 	mtk_snfc_init();
 	usb3_hub_reset();
 	setup_chromeos_gpios();
+	gpio_eint_configure(GPIO_GSC_AP_INT_ODL, IRQ_TYPE_EDGE_RISING);
 }
diff --git a/src/mainboard/google/skywalker/chromeos.c b/src/mainboard/google/skywalker/chromeos.c
index 6c7aca8917..eb310f3576 100644
--- a/src/mainboard/google/skywalker/chromeos.c
+++ b/src/mainboard/google/skywalker/chromeos.c
@@ -1,6 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0-only OR MIT */
 
 #include <boot/coreboot_tables.h>
+#include <drivers/tpm/cr50.h>
 #include <ec/google/chromeec/ec.h>
 #include <gpio.h>
 
@@ -9,6 +10,7 @@
 void setup_chromeos_gpios(void)
 {
 	gpio_input(GPIO_EC_AP_INT_ODL);
+	gpio_input(GPIO_GSC_AP_INT_ODL);
 	gpio_output(GPIO_AP_EC_WARM_RST_REQ, 0);
 	gpio_output(GPIO_XHCI_INIT_DONE, 0);
 }
@@ -18,6 +20,12 @@ void fill_lb_gpios(struct lb_gpios *gpios)
 	struct lb_gpio chromeos_gpios[] = {
 		{GPIO_XHCI_INIT_DONE.id, ACTIVE_HIGH, -1, "XHCI init done"},
 		{GPIO_EC_AP_INT_ODL.id, ACTIVE_LOW, -1, "EC interrupt"},
+		{GPIO_GSC_AP_INT_ODL.id, ACTIVE_HIGH, -1, "TPM interrupt"},
 	};
 	lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios));
 }
+
+int cr50_plat_irq_status(void)
+{
+	return gpio_eint_poll(GPIO_GSC_AP_INT_ODL);
+}
diff --git a/src/mainboard/google/skywalker/gpio.h b/src/mainboard/google/skywalker/gpio.h
index da1622edc0..1fc4674de5 100644
--- a/src/mainboard/google/skywalker/gpio.h
+++ b/src/mainboard/google/skywalker/gpio.h
@@ -9,6 +9,7 @@
 #define GPIO_USB3_HUB_RST_L	GPIO(GPIO07)
 #define GPIO_EC_AP_INT_ODL	GPIO(GBE_MDIO)
 #define GPIO_AP_EC_WARM_RST_REQ	GPIO(GBE_AUX_PPS0)
+#define GPIO_GSC_AP_INT_ODL	GPIO(GBE_AUX_PPS1)
 
 void setup_chromeos_gpios(void);
 

From 37513297d38967f6fc748dbaf357a1e83ac54b31 Mon Sep 17 00:00:00 2001
From: Julius Werner <jwerner@chromium.org>
Date: Tue, 20 May 2025 14:27:35 -0700
Subject: [PATCH 1103/3886] libpayload: Use Kconfig for architecture memcpy,
 not weak symbols

Our mechanism to override the default (pure C) memory function
implementations (memset, memcpy, memmove) with architecture-specific
optimized assembly versions doesn't actually work: it turns out that
weak functions don't work as you'd naively expect when you pack them
together with a strong definition from a different object into a static
library. When a linker tries to resolve a symbol from a static library,
it just picks the first one it finds, even if it is weak. It doesn't
evaluate all objects in the library to see if there are other strong
definitions.

To fix this, this patch gets rid of the weak symbols and uses Kconfigs
instead. It adds an optimized memmove() implementation for x86 because
that makes things easier (then all architectures either override all
three functions or none of them). Also remove memcmp() from the
functions that can be overridden for now because nobody ever needed that
anyway.

Change-Id: Iedf9898247f1999e56fde3233fad8b7cb36b1269
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87766
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 payloads/libpayload/Kconfig            |  7 +++++
 payloads/libpayload/arch/arm/Kconfig   |  1 +
 payloads/libpayload/arch/arm64/Kconfig |  1 +
 payloads/libpayload/arch/x86/Kconfig   |  1 +
 payloads/libpayload/arch/x86/string.c  | 42 ++++++++++++++++++++++++++
 payloads/libpayload/include/string.h   |  9 ++++++
 payloads/libpayload/libc/memory.c      | 25 +++++++--------
 7 files changed, 72 insertions(+), 14 deletions(-)

diff --git a/payloads/libpayload/Kconfig b/payloads/libpayload/Kconfig
index b5da2d9a4a..ea9189463b 100644
--- a/payloads/libpayload/Kconfig
+++ b/payloads/libpayload/Kconfig
@@ -505,6 +505,13 @@ config IO_ADDRESS_SPACE
 	  This option is turned on if the target system has a separate
 	  IO address space. This is typically only the case on x86.
 
+config ARCH_HAS_MEM_FUNCTIONS
+	default n
+	bool
+	help
+	  Architectures must select this when they want to override memset,
+	  memcpy and memmove with optimized assembly implementations.
+
 source "arch/arm/Kconfig"
 source "arch/arm64/Kconfig"
 source "arch/x86/Kconfig"
diff --git a/payloads/libpayload/arch/arm/Kconfig b/payloads/libpayload/arch/arm/Kconfig
index 4b88b18ce2..35095115d7 100644
--- a/payloads/libpayload/arch/arm/Kconfig
+++ b/payloads/libpayload/arch/arm/Kconfig
@@ -30,3 +30,4 @@
 
 config ARCH_ARM
 	select LITTLE_ENDIAN
+	select ARCH_HAS_MEM_FUNCTIONS if GPL
diff --git a/payloads/libpayload/arch/arm64/Kconfig b/payloads/libpayload/arch/arm64/Kconfig
index 60beb0bd5a..ea5cd3a48c 100644
--- a/payloads/libpayload/arch/arm64/Kconfig
+++ b/payloads/libpayload/arch/arm64/Kconfig
@@ -30,6 +30,7 @@
 
 config ARCH_ARM64
 	select LITTLE_ENDIAN
+	select ARCH_HAS_MEM_FUNCTIONS
 
 if ARCH_ARM64
 
diff --git a/payloads/libpayload/arch/x86/Kconfig b/payloads/libpayload/arch/x86/Kconfig
index e59bd7ef6a..00b0ad0e70 100644
--- a/payloads/libpayload/arch/x86/Kconfig
+++ b/payloads/libpayload/arch/x86/Kconfig
@@ -31,6 +31,7 @@
 config ARCH_X86
 	select LITTLE_ENDIAN
 	select IO_ADDRESS_SPACE
+	select ARCH_HAS_MEM_FUNCTIONS if GPL
 
 if ARCH_X86
 
diff --git a/payloads/libpayload/arch/x86/string.c b/payloads/libpayload/arch/x86/string.c
index 11bcae7acb..4c0716f446 100644
--- a/payloads/libpayload/arch/x86/string.c
+++ b/payloads/libpayload/arch/x86/string.c
@@ -103,3 +103,45 @@ void *memcpy(void *dest, const void *src, size_t n)
 
 	return dest;
 }
+
+void *memmove(void *dest, const void *src, size_t n)
+{
+	unsigned long d0, d1, d2;
+
+	if (dest < src)
+		return memcpy(dest, src, n);
+
+#if CONFIG(LP_ARCH_X86_64)
+	asm volatile(
+		"std\n\t"
+		"dec %%rdi\n\t"
+		"dec %%rsi\n\t"
+		"rep ; movsb\n\t"
+		"mov %4, %%rcx\n\t"
+		"sub $7, %%rdi\n\t"
+		"sub $7, %%rsi\n\t"
+		"rep ; movsq\n\t"
+		"cld\n\t"
+		: "=&c" (d0), "=&D" (d1), "=&S" (d2)
+		: "0" (n & 7), "g" (n >> 3), "1" (dest + n), "2" (src + n)
+		: "memory"
+	);
+#else
+	asm volatile(
+		"std\n\t"
+		"dec %%edi\n\t"
+		"dec %%esi\n\t"
+		"rep ; movsb\n\t"
+		"mov %4, %%ecx\n\t"
+		"sub $3, %%edi\n\t"
+		"sub $3, %%esi\n\t"
+		"rep ; movsl\n\t"
+		"cld\n\t"
+		: "=&c" (d0), "=&D" (d1), "=&S" (d2)
+		: "0" (n & 3), "g" (n >> 2), "1" (dest + n), "2" (src + n)
+		: "memory"
+	);
+#endif
+
+	return dest;
+}
diff --git a/payloads/libpayload/include/string.h b/payloads/libpayload/include/string.h
index b0028228eb..40776ff78e 100644
--- a/payloads/libpayload/include/string.h
+++ b/payloads/libpayload/include/string.h
@@ -43,6 +43,15 @@ void *memchr(const void *s, int c, size_t n);
 int memcmp(const void *s1, const void *s2, size_t len);
 /** @} */
 
+/**
+ * @defgroup default memory functions remain available under separate names, in
+ * case architecture implementations want to fall back to them in certain cases.
+ */
+void *default_memset(void *s, int c, size_t n);
+void *default_memcpy(void *dst, const void *src, size_t n);
+void *default_memmove(void *dst, const void *src, size_t n);
+/** @} */
+
 /**
  * @defgroup string String functions
  * @{
diff --git a/payloads/libpayload/libc/memory.c b/payloads/libpayload/libc/memory.c
index fff295e54c..80d7a5f507 100644
--- a/payloads/libpayload/libc/memory.c
+++ b/payloads/libpayload/libc/memory.c
@@ -32,7 +32,7 @@
 
 #include <libpayload.h>
 
-static void *default_memset(void *const s, const int c, size_t n)
+void *default_memset(void *const s, const int c, size_t n)
 {
 	size_t i;
 	u8 *dst = s;
@@ -57,10 +57,7 @@ static void *default_memset(void *const s, const int c, size_t n)
 	return s;
 }
 
-void *memset(void *s, int c, size_t n)
-	__attribute__((weak, alias("default_memset")));
-
-static void *default_memcpy(void *dst, const void *src, size_t n)
+void *default_memcpy(void *dst, const void *src, size_t n)
 {
 	size_t i;
 	void *ret = dst;
@@ -81,10 +78,7 @@ static void *default_memcpy(void *dst, const void *src, size_t n)
 	return ret;
 }
 
-void *memcpy(void *dst, const void *src, size_t n)
-	__attribute__((weak, alias("default_memcpy")));
-
-static void *default_memmove(void *dst, const void *src, size_t n)
+void *default_memmove(void *dst, const void *src, size_t n)
 {
 	size_t offs;
 	ssize_t i;
@@ -110,8 +104,14 @@ static void *default_memmove(void *dst, const void *src, size_t n)
 	return dst;
 }
 
+#if !CONFIG(LP_ARCH_HAS_MEM_FUNCTIONS)
+void *memcpy(void *dst, const void *src, size_t n)
+	__attribute__((alias("default_memcpy")));
+void *memset(void *s, int c, size_t n)
+	__attribute__((alias("default_memset")));
 void *memmove(void *dst, const void *src, size_t n)
-	__attribute__((weak, alias("default_memmove")));
+	__attribute__((alias("default_memmove")));
+#endif
 
 /**
  * Compare two memory areas.
@@ -124,7 +124,7 @@ void *memmove(void *dst, const void *src, size_t n)
  * 	   greater than s2 respectively.
  */
 
-static int default_memcmp(const void *s1, const void *s2, size_t n)
+int memcmp(const void *s1, const void *s2, size_t n)
 {
 	size_t i = 0;
 	const unsigned long *w1 = s1, *w2 = s2;
@@ -142,9 +142,6 @@ static int default_memcmp(const void *s1, const void *s2, size_t n)
 	return 0;
 }
 
-int memcmp(const void *s1, const void *s2, size_t n)
-	__attribute__((weak, alias("default_memcmp")));
-
 void *memchr(const void *s, int c, size_t n)
 {
 	unsigned char *p = (unsigned char *)s;

From 4ccb4a78c4c9e6924137e15f56be8ce890e181b6 Mon Sep 17 00:00:00 2001
From: Julius Werner <jwerner@chromium.org>
Date: Wed, 21 May 2025 13:36:05 -0700
Subject: [PATCH 1104/3886] libpayload: Use Kconfig instead of weak symbol for
 arch_ndelay()

Weak symbols don't work as expected when you want to override them from
within the same static library. This patch changes the arch_ndelay()
function so that instead of having a weak generic implementation, the
choice between generic implementation and an arch-specific override is
explicitly made by Kconfig. Let's also drop the "arch_" prefix and just
call this ndelay().

Change-Id: Ie4fe2734e0683fa3537e2ebcabfe067e7499463a
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87776
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Jakub "Kuba" Czapiga <czapiga@google.com>
---
 payloads/libpayload/Kconfig                      |  7 +++++++
 payloads/libpayload/arch/x86/Kconfig             |  1 +
 payloads/libpayload/arch/x86/apic.c              |  2 +-
 payloads/libpayload/arch/x86/delay.c             |  2 +-
 payloads/libpayload/include/delay.h              | 13 ++++---------
 payloads/libpayload/libc/time.c                  |  5 +++--
 payloads/libpayload/tests/drivers/Makefile.mk    |  2 +-
 payloads/libpayload/tests/drivers/speaker-test.c |  6 +++---
 8 files changed, 21 insertions(+), 17 deletions(-)

diff --git a/payloads/libpayload/Kconfig b/payloads/libpayload/Kconfig
index ea9189463b..44d656bcac 100644
--- a/payloads/libpayload/Kconfig
+++ b/payloads/libpayload/Kconfig
@@ -512,6 +512,13 @@ config ARCH_HAS_MEM_FUNCTIONS
 	  Architectures must select this when they want to override memset,
 	  memcpy and memmove with optimized assembly implementations.
 
+config ARCH_HAS_NDELAY
+	default n
+	bool
+	help
+	  Architectures must select this when they want to override the ndelay()
+	  function with a custom implementation.
+
 source "arch/arm/Kconfig"
 source "arch/arm64/Kconfig"
 source "arch/x86/Kconfig"
diff --git a/payloads/libpayload/arch/x86/Kconfig b/payloads/libpayload/arch/x86/Kconfig
index 00b0ad0e70..1107a3b016 100644
--- a/payloads/libpayload/arch/x86/Kconfig
+++ b/payloads/libpayload/arch/x86/Kconfig
@@ -32,6 +32,7 @@ config ARCH_X86
 	select LITTLE_ENDIAN
 	select IO_ADDRESS_SPACE
 	select ARCH_HAS_MEM_FUNCTIONS if GPL
+	select ARCH_HAS_NDELAY
 
 if ARCH_X86
 
diff --git a/payloads/libpayload/arch/x86/apic.c b/payloads/libpayload/arch/x86/apic.c
index e0671064c8..1e70812384 100644
--- a/payloads/libpayload/arch/x86/apic.c
+++ b/payloads/libpayload/arch/x86/apic.c
@@ -249,7 +249,7 @@ static void apic_init_timer(void)
 		apic_write32(APIC_TIMER_INIT_COUNT, UINT32_MAX);
 
 		/* This is safe because apic_initialized() returns false so
-		 * arch_ndelay() falls back to a busy loop. */
+		 * ndelay() falls back to a busy loop. */
 		mdelay(1);
 
 		ticks_per_ms =
diff --git a/payloads/libpayload/arch/x86/delay.c b/payloads/libpayload/arch/x86/delay.c
index 373c8417b3..90592181c7 100644
--- a/payloads/libpayload/arch/x86/delay.c
+++ b/payloads/libpayload/arch/x86/delay.c
@@ -38,7 +38,7 @@
 /* Let's assume APIC interrupts take at least 100us */
 #define APIC_INTERRUPT_LATENCY_NS	(100 * NSECS_PER_USEC)
 
-void arch_ndelay(uint64_t ns)
+void ndelay(uint64_t ns)
 {
 	uint64_t delta = ns * timer_hz() / NSECS_PER_SEC;
 	uint64_t pause_delta = 0;
diff --git a/payloads/libpayload/include/delay.h b/payloads/libpayload/include/delay.h
index 126bee66f8..cac759704e 100644
--- a/payloads/libpayload/include/delay.h
+++ b/payloads/libpayload/include/delay.h
@@ -14,17 +14,12 @@
 
 unsigned int get_cpu_speed(void);
 
-void arch_ndelay(uint64_t n);
-
 /**
  * Delay for a specified number of nanoseconds.
  *
  * @param ns Number of nanoseconds to delay for.
  */
-static inline void ndelay(unsigned int ns)
-{
-	arch_ndelay((uint64_t)ns);
-}
+void ndelay(uint64_t n);
 
 /**
  * Delay for a specified number of microseconds.
@@ -33,7 +28,7 @@ static inline void ndelay(unsigned int ns)
  */
 static inline void udelay(unsigned int us)
 {
-	arch_ndelay((uint64_t)us * NSECS_PER_USEC);
+	ndelay((uint64_t)us * NSECS_PER_USEC);
 }
 
 /**
@@ -43,7 +38,7 @@ static inline void udelay(unsigned int us)
  */
 static inline void mdelay(unsigned int ms)
 {
-	arch_ndelay((uint64_t)ms * NSECS_PER_MSEC);
+	ndelay((uint64_t)ms * NSECS_PER_MSEC);
 }
 
 /**
@@ -53,7 +48,7 @@ static inline void mdelay(unsigned int ms)
  */
 static inline void delay(unsigned int s)
 {
-	arch_ndelay((uint64_t)s * NSECS_PER_SEC);
+	ndelay((uint64_t)s * NSECS_PER_SEC);
 }
 
 #endif /* LIBPAYLOAD_DELAY_H */
diff --git a/payloads/libpayload/libc/time.c b/payloads/libpayload/libc/time.c
index 64de80049c..0d599644a7 100644
--- a/payloads/libpayload/libc/time.c
+++ b/payloads/libpayload/libc/time.c
@@ -161,13 +161,14 @@ int gettimeofday(struct timeval *tv, void *tz)
 	return 0;
 }
 
-__attribute__((weak))
-void arch_ndelay(uint64_t ns)
+#if !CONFIG(LP_ARCH_HAS_NDELAY)
+void ndelay(uint64_t ns)
 {
 	uint64_t delta = ns * timer_hz() / NSECS_PER_SEC;
 	uint64_t start = timer_raw_value();
 	while (timer_raw_value() - start < delta) ;
 }
+#endif
 
 u64 timer_us(u64 base)
 {
diff --git a/payloads/libpayload/tests/drivers/Makefile.mk b/payloads/libpayload/tests/drivers/Makefile.mk
index 8d668c2e42..f898278a3a 100644
--- a/payloads/libpayload/tests/drivers/Makefile.mk
+++ b/payloads/libpayload/tests/drivers/Makefile.mk
@@ -8,4 +8,4 @@ graphics-test-srcs += libc/fpmath.c
 speaker-test-srcs += tests/drivers/speaker-test.c
 speaker-test-mocks += inb
 speaker-test-mocks += outb
-speaker-test-mocks += arch_ndelay
+speaker-test-mocks += ndelay
diff --git a/payloads/libpayload/tests/drivers/speaker-test.c b/payloads/libpayload/tests/drivers/speaker-test.c
index a677fa46ca..eb907ce05d 100644
--- a/payloads/libpayload/tests/drivers/speaker-test.c
+++ b/payloads/libpayload/tests/drivers/speaker-test.c
@@ -104,7 +104,7 @@ static void test_speaker_disable(void **state)
 	speaker_disable();
 }
 
-void arch_ndelay(uint64_t ns)
+void ndelay(uint64_t ns)
 {
 	check_expected(ns);
 }
@@ -112,9 +112,9 @@ void arch_ndelay(uint64_t ns)
 static void setup_speaker_tone_calls(u16 freq, unsigned int duration)
 {
 	setup_speaker_enable_calls(freq, ~freq & 0xff);
-	expect_value(arch_ndelay, ns, (uint64_t)duration * NSECS_PER_MSEC);
+	expect_value(ndelay, ns, (uint64_t)duration * NSECS_PER_MSEC);
 	setup_speaker_disable_calls(0xff);
-	expect_any(arch_ndelay, ns);
+	expect_any(ndelay, ns);
 }
 
 static void test_speaker_tone(void **state)

From aedc177f000a3fd62c75f555c116ad956443ab1e Mon Sep 17 00:00:00 2001
From: Julius Werner <jwerner@chromium.org>
Date: Wed, 21 May 2025 16:51:26 -0700
Subject: [PATCH 1105/3886] libpayload: arm64: Reduce DMA allocator space to
 1MB

On arm64 device libpayload reserves 32MB of space for the DMA allocator.
DMA allocators are usually just used for small bounce buffers or DMA
descriptors for SPI, I2C or USB transfers, nothing that should get
anywhere near the size of megabytes.

Presumably the original number was just made arbitrarily large because
it didn't matter. But more recently we have had security applications
(guarding secrets that get received over SPI/I2C from firmware and must
not be visible to the OS after handoff) that made us want to erase the
entire DMA heap just to be sure no driver left a copy of any secret
lying around there. This means the size is no longer fully harmless
because erasing a larger heap takes more time.

Change the default to 1MB which should still be more than more than
enough for any real applications, but should bring the time required to
erase it back into negligible territory.

BUG=b:418942992
TEST=Booted Trogdor from USB.

Change-Id: Id56486203c512d7ff08909cac1a016adc44d8e68
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87780
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
---
 payloads/libpayload/include/arm64/arch/mmu.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/payloads/libpayload/include/arm64/arch/mmu.h b/payloads/libpayload/include/arm64/arch/mmu.h
index 2b1e9e120c..9ed951d336 100644
--- a/payloads/libpayload/include/arm64/arch/mmu.h
+++ b/payloads/libpayload/include/arm64/arch/mmu.h
@@ -161,7 +161,7 @@ extern char _start[], _end[];
 #define TCR_TBI_USED               (0x0 << TCR_TBI_SHIFT)
 #define TCR_TBI_IGNORED            (0x1 << TCR_TBI_SHIFT)
 
-#define DMA_DEFAULT_SIZE           (32 * MiB)
+#define DMA_DEFAULT_SIZE           (1 * MiB)
 #define TTB_DEFAULT_SIZE           0x100000
 
 #define MB_SIZE			   (1UL << 20)

From 7150c5e2feb45a8009a672958ba4a501280d5f2b Mon Sep 17 00:00:00 2001
From: Wentao Qin <qinwentao@huaqin.corp-partner.google.com>
Date: Thu, 22 May 2025 16:12:19 +0800
Subject: [PATCH 1106/3886] mb/google/skywalker: Create variant Anakin

Create the variant Anakin.

BUG=b:419419679
TEST=emerge-skywalker coreboot
BRANCH=None

Change-Id: I1f53b6a307934e6a1c58ee21dd0275c6a632e726
Signed-off-by: Wentao Qin <qinwentao@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87797
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yang Wu <wuyang5@huaqin.corp-partner.google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
---
 src/mainboard/google/skywalker/Kconfig      | 4 +++-
 src/mainboard/google/skywalker/Kconfig.name | 3 +++
 2 files changed, 6 insertions(+), 1 deletion(-)

diff --git a/src/mainboard/google/skywalker/Kconfig b/src/mainboard/google/skywalker/Kconfig
index 2bdb0df18a..b5134a529a 100644
--- a/src/mainboard/google/skywalker/Kconfig
+++ b/src/mainboard/google/skywalker/Kconfig
@@ -2,7 +2,8 @@
 
 # Umbrella option to be selected by variant boards.
 config BOARD_GOOGLE_SKYWALKER_COMMON
-	def_bool BOARD_GOOGLE_OBIWAN || \
+	def_bool BOARD_GOOGLE_ANAKIN || \
+		 BOARD_GOOGLE_OBIWAN || \
 		 BOARD_GOOGLE_SKYWALKER || \
 		 BOARD_GOOGLE_YODA
 
@@ -37,6 +38,7 @@ config MAINBOARD_DIR
 
 config MAINBOARD_PART_NUMBER
 	string
+	default "Anakin" if BOARD_GOOGLE_ANAKIN
 	default "Obiwan" if BOARD_GOOGLE_OBIWAN
 	default "Skywalker" if BOARD_GOOGLE_SKYWALKER
 	default "Yoda" if BOARD_GOOGLE_YODA
diff --git a/src/mainboard/google/skywalker/Kconfig.name b/src/mainboard/google/skywalker/Kconfig.name
index 1bef303a12..a7c8eb3088 100644
--- a/src/mainboard/google/skywalker/Kconfig.name
+++ b/src/mainboard/google/skywalker/Kconfig.name
@@ -2,6 +2,9 @@
 
 comment "Skywalker"
 
+config BOARD_GOOGLE_ANAKIN
+	bool "->  Anakin"
+
 config BOARD_GOOGLE_OBIWAN
 	bool "->  Obiwan"
 

From d281a3c559e7a0d58d07d2e47ed460576bb92387 Mon Sep 17 00:00:00 2001
From: Kun Liu <liukun11@huaqin.corp-partner.google.com>
Date: Tue, 20 May 2025 15:52:05 +0800
Subject: [PATCH 1107/3886] mb/google/trulo/var/pujjocento: Configure
 tcss_aux_ori

Resolve the issue that DP can only display on one side.

BUG=b:416842915
BRANCH=none
TEST=Build and boot to pujjocento. Verify typec works.

Change-Id: I55f2f28a0bdb052cafa05a98f51c8483fb343b8c
Signed-off-by: Kun Liu <liukun11@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87757
Reviewed-by: Derek Huang <derekhuang@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 .../google/brya/variants/pujjocento/overridetree.cb    | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/src/mainboard/google/brya/variants/pujjocento/overridetree.cb b/src/mainboard/google/brya/variants/pujjocento/overridetree.cb
index 4a9ae54d8a..991fdf054e 100644
--- a/src/mainboard/google/brya/variants/pujjocento/overridetree.cb
+++ b/src/mainboard/google/brya/variants/pujjocento/overridetree.cb
@@ -49,6 +49,16 @@ chip soc/intel/alderlake
 	register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)"	# USB3 WWAN(LTE)
 
 	register "tcss_ports[0]" = "TCSS_PORT_DEFAULT(OC_SKIP)"
+	register "tcss_ports[1]" = "TCSS_PORT_DEFAULT(OC_SKIP)"
+
+	# SOC Aux orientation override:
+	# This is a bitfield that corresponds to up to 4 TCSS ports.
+	# Bits (0,1) allocated for TCSS Port1 configuration and Bits (2,3)for TCSS Port2.
+	# TcssAuxOri = 0101b
+	# Bit0,Bit2 set to "1" indicates no retimer on USBC Ports
+	# Bit1,Bit3 set to "0" indicates Aux lines are not swapped on the
+	# motherboard to USBC connector
+	register "tcss_aux_ori" = "0"
 
 
 	# HD Audio

From f562992da1c39348547d9d0e2c9268cbdad3e68c Mon Sep 17 00:00:00 2001
From: Kun Liu <liukun11@huaqin.corp-partner.google.com>
Date: Wed, 21 May 2025 14:42:00 +0800
Subject: [PATCH 1108/3886] mb/google/trulo/var/pujjocento: Enable EC keyboard
 backlight

Enable EC keyboard backlight for pujjocento.

BUG=b:417141058
TEST=emerge-nissa coreboot chromeos-bootimage

Change-Id: Ibaffd70fc04cb7a42543684d2edaf1d3a5c2f4f6
Signed-off-by: Kun Liu <liukun11@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87770
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jayvik Desai <jayvik@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
---
 .../google/brya/variants/pujjocento/include/variant/ec.h        | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/src/mainboard/google/brya/variants/pujjocento/include/variant/ec.h b/src/mainboard/google/brya/variants/pujjocento/include/variant/ec.h
index 7a2a6ff8b7..9e4cb6035e 100644
--- a/src/mainboard/google/brya/variants/pujjocento/include/variant/ec.h
+++ b/src/mainboard/google/brya/variants/pujjocento/include/variant/ec.h
@@ -5,4 +5,6 @@
 
 #include <baseboard/ec.h>
 
+/* Enable EC backed Keyboard Backlight in ACPI */
+#define EC_ENABLE_KEYBOARD_BACKLIGHT
 #endif

From bb8d069dd305950ad53d20495ceadff695903d57 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Bart=C5=82omiej=20Grzesik?= <bgrzesik@google.com>
Date: Tue, 20 May 2025 13:10:13 +0200
Subject: [PATCH 1109/3886] vc/google/chromeos: Move pvmfw cbmem and enable
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

This change moves pvmfw cbmem implementation to chromeos directory and
under CHROMEOS kconfig. The kconfigs have been renamed accordingly and
with this change CHROMEOS_PVMFW_CBMEM is enabled by default for
CHROMEOS.

BUG=b:410735713
TEST=The build with CONFIG_CHROMEOS=y allocates buffer for pvmfw, the
depthcharge adds the location and size of the buffer to the kernel
command line

Change-Id: I024f21ceee1334ebd7ae9bf1b897ad670ddc9ef9
Signed-off-by: Bartłomiej Grzesik <bgrzesik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87763
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/vendorcode/google/Kconfig                     | 14 --------------
 src/vendorcode/google/Makefile.mk                 |  1 -
 src/vendorcode/google/chromeos/Kconfig            | 15 +++++++++++++++
 src/vendorcode/google/chromeos/Makefile.mk        |  1 +
 .../google/{ => chromeos}/pvmfw_cbmem.c           |  2 +-
 5 files changed, 17 insertions(+), 16 deletions(-)
 rename src/vendorcode/google/{ => chromeos}/pvmfw_cbmem.c (83%)

diff --git a/src/vendorcode/google/Kconfig b/src/vendorcode/google/Kconfig
index a846336c0b..2a1a327cec 100644
--- a/src/vendorcode/google/Kconfig
+++ b/src/vendorcode/google/Kconfig
@@ -38,17 +38,3 @@ config MAINBOARD_HAS_GOOGLE_STRAUSS_KEYBOARD
 config ACPI_FNKEY_GEN_SCANCODE
 	default 94 if MAINBOARD_HAS_GOOGLE_STRAUSS_KEYBOARD
 
-config GOOGLE_PVMFW_CBMEM
-	bool "Enable reserving memory for pvmfw using cbmem"
-	default n
-	help
-	  Select this config to enable allocating a region for Android protected
-	  virtual machine firmware within cbmem. The region shall be filled by
-	  the payload and the purpose is to just reserve the memory.
-	  cbmem is used to make sure that the region won't overlap with other
-	  reserved regions or device regions.
-
-config GOOGLE_PVMFW_CBMEM_SIZE
-	hex "Size of the pvmfw buffer to be reserved using cbmem"
-	depends on GOOGLE_PVMFW_CBMEM
-	default 0x400000
diff --git a/src/vendorcode/google/Makefile.mk b/src/vendorcode/google/Makefile.mk
index 32bb90ff74..c9e83897ff 100644
--- a/src/vendorcode/google/Makefile.mk
+++ b/src/vendorcode/google/Makefile.mk
@@ -4,4 +4,3 @@ subdirs-$(CONFIG_CHROMEOS) += chromeos
 
 ramstage-$(CONFIG_GOOGLE_DSM_CALIB) += dsm_calib.c
 ramstage-$(CONFIG_GOOGLE_SMBIOS_MAINBOARD_VERSION) += smbios.c
-ramstage-$(CONFIG_GOOGLE_PVMFW_CBMEM) += pvmfw_cbmem.c
diff --git a/src/vendorcode/google/chromeos/Kconfig b/src/vendorcode/google/chromeos/Kconfig
index 60f48fef33..5cfab094dc 100644
--- a/src/vendorcode/google/chromeos/Kconfig
+++ b/src/vendorcode/google/chromeos/Kconfig
@@ -123,5 +123,20 @@ config CHROMEOS_ENABLE_ESOL
 	  If your platform supports eSOL, enable it by selecting the
 	  appropriate option.
 
+config CHROMEOS_PVMFW_CBMEM
+	bool "Enable reserving memory for pvmfw using cbmem"
+	default y
+	help
+	  Select this config to enable allocating a region for Android protected
+	  virtual machine firmware within cbmem. The region shall be filled by
+	  the payload and the purpose is to just reserve the memory.
+	  cbmem is used to make sure that the region won't overlap with other
+	  reserved regions or device regions.
+
+config CHROMEOS_PVMFW_CBMEM_SIZE
+	hex "Size of the pvmfw buffer to be reserved using cbmem"
+	depends on CHROMEOS_PVMFW_CBMEM
+	default 0x400000
+
 endif # CHROMEOS
 endmenu
diff --git a/src/vendorcode/google/chromeos/Makefile.mk b/src/vendorcode/google/chromeos/Makefile.mk
index 6eb010e8eb..54673bcaf9 100644
--- a/src/vendorcode/google/chromeos/Makefile.mk
+++ b/src/vendorcode/google/chromeos/Makefile.mk
@@ -24,6 +24,7 @@ romstage-$(CONFIG_CHROMEOS_DRAM_PART_NUMBER_IN_CBI) += dram_part_num_override.c
 
 ramstage-$(CONFIG_PLATFORM_HAS_LOW_BATTERY_INDICATOR) += battery.c
 ramstage-$(CONFIG_CHROMEOS_FW_SPLASH_SCREEN) += splash.c
+ramstage-$(CONFIG_CHROMEOS_PVMFW_CBMEM) += pvmfw_cbmem.c
 
 # Add logo to the cbfs image
 BMP_LOGO_COMPRESS_FLAG := $(CBFS_COMPRESS_FLAG)
diff --git a/src/vendorcode/google/pvmfw_cbmem.c b/src/vendorcode/google/chromeos/pvmfw_cbmem.c
similarity index 83%
rename from src/vendorcode/google/pvmfw_cbmem.c
rename to src/vendorcode/google/chromeos/pvmfw_cbmem.c
index 15b0710645..dd0c0e5e57 100644
--- a/src/vendorcode/google/pvmfw_cbmem.c
+++ b/src/vendorcode/google/chromeos/pvmfw_cbmem.c
@@ -9,7 +9,7 @@ static void add_pvmfw_cbmem(void *unused)
 	(void)unused;
 	void *pvmfw;
 
-	pvmfw = cbmem_add(CBMEM_ID_PVMFW, CONFIG_GOOGLE_PVMFW_CBMEM_SIZE);
+	pvmfw = cbmem_add(CBMEM_ID_PVMFW, CONFIG_CHROMEOS_PVMFW_CBMEM_SIZE);
 	if (!pvmfw)
 		printk(BIOS_ERR, "Failed to add pvmfw info to CBMEM\n");
 }

From 0fba7354827531b3603a5974660c19d8c1f3b438 Mon Sep 17 00:00:00 2001
From: Dinesh Gehlot <digehlot@google.com>
Date: Sat, 25 Jan 2025 06:00:22 +0530
Subject: [PATCH 1110/3886] soc/intel/cmn/blk: Refactor CSE status flag and
 optimize forced sync

This patch enhances the forced CSE sync mechanism by eliminating the
boot partition check for RO. It uses the persistent CMOS flags to
preserve the forced CSE update status across boots.

This patch also replaces the CSE status boolean variable with a bit
field to optimize CMOS memory utilization. Consequently, the remaining
bits can potentially be utilized for additional CSE states in future.

BUG=b:380220737
TEST=Verified forced CSE sync on google/rex0.

Change-Id: If1e4180cb5fec3990fdee2b0e412173b1c8c6ded
Signed-off-by: Dinesh Gehlot <digehlot@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86153
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/soc/intel/common/block/cse/cse_lite.c     | 94 +++++++++++++++++--
 .../common/block/include/intelblocks/cse.h    |  9 +-
 2 files changed, 93 insertions(+), 10 deletions(-)

diff --git a/src/soc/intel/common/block/cse/cse_lite.c b/src/soc/intel/common/block/cse/cse_lite.c
index e4923ca376..ac2780056b 100644
--- a/src/soc/intel/common/block/cse/cse_lite.c
+++ b/src/soc/intel/common/block/cse/cse_lite.c
@@ -172,6 +172,9 @@ static void cse_store_rw_fw_version(void)
 	memcpy(&(cse_info_in_cbmem->cse_fwp_version.cur_cse_fw_version),
 		 &(cse_bp->fw_ver), sizeof(struct fw_version));
 
+	/* Update CBMEM cse sync status flag with CMOS stored information */
+	cse_info_in_cbmem->cse_sync_status = cse_info_in_cmos.cse_sync_status;
+
 	/* Update the CRC */
 	store_cse_info_crc(cse_info_in_cbmem);
 
@@ -743,17 +746,83 @@ static enum cb_err get_cse_ver_from_cbfs(struct fw_version *cbfs_rw_version)
 	return CB_SUCCESS;
 }
 
+static void cmos_update_cse_sync_performed(void)
+{
+	if (!CONFIG(VBOOT) || !vboot_is_gbb_flag_set(VB2_GBB_FLAG_FORCE_CSE_SYNC))
+		return;
+
+	struct cse_specific_info cse_info_in_cmos;
+	cmos_read_fw_partition_info(&cse_info_in_cmos);
+
+	/* Update CSE sync as performed */
+	cse_info_in_cmos.cse_sync_status |= CSE_ENFORCED_SYNC_PERFORMED;
+
+	/* Update the CRC */
+	store_cse_info_crc(&cse_info_in_cmos);
+
+	/* Update CSE specific info at CMOS */
+	cmos_write_fw_partition_info(&cse_info_in_cmos);
+}
+
+static void cmos_update_cse_sync_status(void)
+{
+	if (!CONFIG(VBOOT) || !vboot_is_gbb_flag_set(VB2_GBB_FLAG_FORCE_CSE_SYNC))
+		return;
+
+	/*
+	 * If the pertinent GBB flag is set, the Enforce CSE sync sequence proceeds as follows:
+	 *	1) Request forced sync (set CSE_FORCED_SYNC_REQUEST):
+	 *		CSE_FORCED_SYNC_REQUEST is set during the "CSE sync status check" only if CSE
+	 *		sync has not yet been performed.
+	 *		It is possible to have duplicate CSE status checks, for example, if eSOL tries
+	 *		to make an early decision to display a screen for the CSE update, or if the
+	 *		device switches from an RW partition to RO before sync. These duplicate
+	 *		requests will set the request flag again, effectively will not alter the state
+	 *		machines.
+	 *	2) Sync is performed (set CSE_FORCED_SYNC_PERFORMED):
+	 *		AP will set CSE_FORCED_SYNC_PERFORMED upon successful CSE sync.
+	 *	3) Reset forced sync Request (reset CSE_FORCED_SYNC_REQUEST):
+	 *		Once the CSE sync is performed and the CSE_FORCED_SYNC_PERFORMED flag is set.
+	 *		For eSOL decision, AP will request a "CSE sync status check" on the subsequent
+	 *		boot. As the CSE sync request is honoured, CSE_FORCED_SYNC_REQUEST is reset.
+	 *	4) Resert Sync performed flag (reset CSE_FORCED_SYNC_PERFORMED):
+	 *		Another "CSE sync status check" occurs during the CSE sync process itself. The
+	 *		AP then resets CSE_FORCED_SYNC_PERFORMED to signify the completion of the
+	 *		entire CSE sync cycle.
+	 *
+	 * It is important to avoid clearing both flags in step 3, as the process is not yet
+	 * finished. Doing so would cause boot loop as the AP will interpret a subsequent "CSE
+	 * sync status check" as a fresh sync request.
+*/
+
+	struct cse_specific_info cse_info_in_cmos;
+	cmos_read_fw_partition_info(&cse_info_in_cmos);
+
+	/* Reset flags if Enforced CSE sync is performed; else, request sync.*/
+	if (cse_info_in_cmos.cse_sync_status & CSE_ENFORCED_SYNC_PERFORMED) {
+		if (cse_info_in_cmos.cse_sync_status & CSE_ENFORCED_SYNC_REQUEST)
+			cse_info_in_cmos.cse_sync_status &= ~(CSE_ENFORCED_SYNC_REQUEST);
+		else
+			cse_info_in_cmos.cse_sync_status &= ~(CSE_ENFORCED_SYNC_PERFORMED);
+	} else {
+		cse_info_in_cmos.cse_sync_status |= CSE_ENFORCED_SYNC_REQUEST;
+	}
+
+	/* Update the CRC */
+	store_cse_info_crc(&cse_info_in_cmos);
+
+	/* Update CSE specific info at CMOS */
+	cmos_write_fw_partition_info(&cse_info_in_cmos);
+}
+
 static bool is_cse_sync_enforced(void)
 {
-	/*
-	 * Force test CSE firmware update scenario if below conditions are being met:
-	 *  - VB2_GBB_FLAG_FORCE_CSE_SYNC flag is set
-	 *  - CSE FW is in RO
-	 */
-	struct vb2_context *ctx = vboot_get_context();
-	if ((vb2api_gbb_get_flags(ctx) & VB2_GBB_FLAG_FORCE_CSE_SYNC) &&
-		 cse_get_current_bp() == RO) {
-		return true;
+	if (CONFIG(VBOOT) && vboot_is_gbb_flag_set(VB2_GBB_FLAG_FORCE_CSE_SYNC)) {
+
+		struct cse_specific_info cse_info_in_cmos;
+		cmos_read_fw_partition_info(&cse_info_in_cmos);
+
+		return cse_info_in_cmos.cse_sync_status & CSE_ENFORCED_SYNC_REQUEST;
 	}
 	return false;
 }
@@ -777,6 +846,9 @@ static enum cse_update_status cse_check_update_status(struct region_device *targ
 
 	ret = cse_compare_sub_part_version(&cbfs_rw_version, cse_get_rw_version());
 	if (ret == 0) {
+		/* Update the CMOS status flag enforced CSE sync */
+		cmos_update_cse_sync_status();
+
 		if (is_cse_sync_enforced()) {
 			printk(BIOS_WARNING, "Force CSE Firmware upgrade for Autotest\n");
 			return CSE_UPDATE_UPGRADE;
@@ -843,6 +915,7 @@ static enum csme_failure_reason cse_update_rw(const void *cse_cbfs_rw, const siz
 	if (cse_write_rw_region(target_rdev, cse_cbfs_rw, cse_blob_sz) != CB_SUCCESS)
 		return CSE_LITE_SKU_FW_UPDATE_ERROR;
 
+	cmos_update_cse_sync_performed();
 	return CSE_NO_ERROR;
 }
 
@@ -1039,6 +1112,9 @@ bool is_cse_fw_update_required(void)
 	if (get_cse_ver_from_cbfs(&cbfs_rw_version) == CB_ERR)
 		return false;
 
+	/* Update the CMOS status flag enforced CSE sync */
+	cmos_update_cse_sync_status();
+
 	/* Check if CSE sync is enforced */
 	if (is_cse_sync_enforced()) {
 		return true;
diff --git a/src/soc/intel/common/block/include/intelblocks/cse.h b/src/soc/intel/common/block/include/intelblocks/cse.h
index ac3f2cdcf9..8bed429da7 100644
--- a/src/soc/intel/common/block/include/intelblocks/cse.h
+++ b/src/soc/intel/common/block/include/intelblocks/cse.h
@@ -182,10 +182,17 @@ struct cse_fw_partition_info {
 	struct cse_fw_ish_version_info ish_partition_info;
 };
 
+/* CSE sync flags */
+enum cse_sync_flags {
+	CSE_DOWNGRADE_REQUEST		= 1 << 0,
+	CSE_ENFORCED_SYNC_REQUEST	= 1 << 1,
+	CSE_ENFORCED_SYNC_PERFORMED	= 1 << 2,
+};
+
 /* CSE Specific Information */
 struct cse_specific_info {
 	struct cse_fw_partition_info cse_fwp_version;
-	bool cse_downgrade_requested;
+	int8_t cse_sync_status;
 	uint32_t crc;
 };
 

From 5a947da94ec3a93b5a34d92d0c7a3fc75dd11eec Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Sat, 10 May 2025 10:19:12 -0500
Subject: [PATCH 1111/3886] mb/google/sarien: Update VBT from v221 to v228

Update VBTs for both sarien and arcada variants from v221 to v228.
The current public CFL FSP uses/expects v228, and the older v221
causes a 180* rotation of the display at boot. Updating the VBT
to v228 fixes the issue. Also disable the fixed mode at boot
setting, so that the native panel resolution can be used by
the payload.

Settings were exported from the v221 VBTs using the Intel BMP tool,
and imported/applied to the sample VBT provided in the FSP repo.

TEST=build/boot google sarien w/edk2 payload, verify screen orientation
correct and native panel resolution used.

Change-Id: Ib6669fc535a197f961abdfcd10616c97a0573df2
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87619
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 .../google/sarien/variants/arcada/data.vbt    | Bin 4608 -> 4608 bytes
 .../google/sarien/variants/sarien/data.vbt    | Bin 4608 -> 4608 bytes
 2 files changed, 0 insertions(+), 0 deletions(-)

diff --git a/src/mainboard/google/sarien/variants/arcada/data.vbt b/src/mainboard/google/sarien/variants/arcada/data.vbt
index 99968705ee185afa191c9b8d65bf794b04eaaaad..c3ab78ea6d06f3e9fd1faafa54aa8f45b345b0b7 100644
GIT binary patch
delta 409
zcmZorX;7IU!Maqii@{*BBa`q%0|C}23}Or=8(otaIfXbGz<_=721YqXmC5HB)ilhY
zVnB)+ENQ@~0A?@(c?t{yATa>}29L?IOdAyYIOQ1pnKc+{n3)*bm@OEzSWYk)a4Ika
za|$q|0deK#cT8SPjQ=NFvYue#VV<nW)->6kO>XjHHr>sa*kqX|2QVp3e$R1^QEu`+
zPU(7(*_u-rnA5owdbxz=b8)TYQaH~g^pK0|HJ5@Qw~#V7moB$LFt<=DH&;Hl!c=ad
z<=k8wxfQN+3%%s#`pm5$$s?rA!)3~&5X~c$%fnU9qcE38Xgv?tP9BB(JVGCNxPJ2}
zDDny!^K#kpDkSp?mGW}c^C~Rm723|rb&yv|;W@9+PhKu&J_SuaA!|M^S3ZSoKA~DZ
zuJ+A&Tyt2h%@}&zfKK#e;9>}62w+HI&|#d$@Pe7)KNK)PS!`%P&wz1qpg`;70|H_|
KJY%vGQwjh=uU*an

delta 377
zcmXAlPe@cz7{%|sZ{8d4ckg|3-xs_oqwyOVWE9i~Ey`6$q*RNDHVv(+l^bD}qTnl0
z1QC=kmoB1Zn~_<Di-^cgi3@SlzfHSpA-IaD=gfh_`JJ;oc_VLZT?`*5KSajU>cV#B
z!!IHg+1{-uQlAcpo+Ni<O_umjjx<x<---x&lu7DC(Mb67&3n=0E2>kU*EMl3Xo{sk
ziM8Om7%LqJuSs0hUd$A3b$_cnO8()g@Id`kT#r)qIpic-=U36Vl-;AKrnsU%$wB_A
zFE5Y25W!8LIlx7LRiM{^`v4z+egXai(1s=rP8+yusBLh?z^0+D!S@CZ4V@V*TSzQj
zvv}LW14|1QH!SQ}dSmgUg%eAEEmj;{a&*JteFu*mJ#)wob{)NQICSjbo1-wsY7F(5
yW@Bu{@HBQ~80PA`<hC2`?n672DNp)pFp)`q>sy@rhdh`(FH2D>-U;|9diftE-%U6G

diff --git a/src/mainboard/google/sarien/variants/sarien/data.vbt b/src/mainboard/google/sarien/variants/sarien/data.vbt
index 0fb57722a22d10198bc05e4fc2cc6c831b582723..145eeaaedfa80fbcd05506f11704e8bf96c79b23 100644
GIT binary patch
delta 372
zcmZ9GODKd<7>2)delz^vIp=SDN-mkc$t2^}l!zozgcOpMo$Er_kQ9-^!X-M$f-EFi
zp;^dA?5tQ?N-3mBO38vDD^ERd@9ur4!c*bpG~aIWJVb4^Oj(Hre0Puv!$-B9!X+1e
zNwkL|D8lwi<cL!H9?yE4B@aVOZV;NCTo`vG%sOR|mv8}5m!ZuKKyTc!*t2Yu;>(u%
zE~IvB$UkkX{K43cze(B_$@V4bQUvX(n>qQj6IlhP4|x%38*v}`3h5T{2{~C&w!%Wi
zZHjsn4k=z!w5RY$@wK8yg>Q<}HRWq8(cGbFK;x+9Elmd+Pc+|Xde!);Ib^8VV5Q+M
zLn8(!4euH{Hh69__}<WmLC52WM-?8{dfe~PgoksnLEQ9Jl)^$?{9*$jv_lJYLxEU_
c2M50XfWPMdM^RMR*1(KC3#7)~ur;##8|-{tGynhq

delta 338
zcmW-dPbh<79LJyMdG~JK-}5~0-u=|ZWPa1q>|iSgoV0}eDaplh!pTMLD9R8iDS9|M
z$kAomQ9DSo3(G++{+*m~P+TOIZ+$-Z&$o~$Bz79?>Cg+yn5?MZ&3N_$3$x5g{|t9N
z>e&CdDe@TinJRDNVe?gU(lm==eBOz%F)PWIEWtLcZkF;@nCB4dbUZdtBUgGC!-9XC
z9=jr5g^Bya;@&nP|7PjPKPpVnx#m&x=rk?2?=h<nXbx}@U>)cfunces^al6~;7CeK
z%t{!Ml$W?BVOvs3;)R5&q)&+f1tCRU3WpR-C|XdsrC?vtslqD-cZz-#1~oKl>eV=|
zVM^1AMx)_C)49f$TMbW|Y!@Rg#9bP6G3Uapt5awf#4|T}-C8O`-mc}Ry@=J3;pWWC
VnSwWIqM_9QXTI7|mbvjC{sEqYOrHP%


From 0121d0e3e005bb7e96ff3f3504c2ef51ab1aca9c Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Thu, 8 May 2025 10:59:25 -0500
Subject: [PATCH 1112/3886] ec/google/chromeec/smi: Clear events before
 enabling wake mask

On some older platforms (eg, google/link), setting the wake mask
before clearing the pending events will result in an immediate
wake from S3 sleep, so swap the ordering to ensure that doesn't
happen.

TEST=build/boot google/link, verify S3 sleep works properly.

Change-Id: I483dcfabd37a1f55fd0e56eed895f5b813f018d7
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87576
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
---
 src/ec/google/chromeec/smihandler.c | 14 +++++++-------
 1 file changed, 7 insertions(+), 7 deletions(-)

diff --git a/src/ec/google/chromeec/smihandler.c b/src/ec/google/chromeec/smihandler.c
index 91b42319d5..c1bb523f23 100644
--- a/src/ec/google/chromeec/smihandler.c
+++ b/src/ec/google/chromeec/smihandler.c
@@ -61,6 +61,13 @@ void chromeec_set_usb_charge_mode(int slp_type)
 
 void chromeec_smi_sleep(int slp_type, uint64_t s3_mask, uint64_t s5_mask)
 {
+	/* Disable SCI and SMI events */
+	google_chromeec_set_smi_mask(0);
+	google_chromeec_set_sci_mask(0);
+
+	/* Clear pending events that may trigger immediate wake */
+	clear_pending_events();
+
 	if (!google_chromeec_is_uhepi_supported()) {
 		switch (slp_type) {
 		case ACPI_S3:
@@ -74,13 +81,6 @@ void chromeec_smi_sleep(int slp_type, uint64_t s3_mask, uint64_t s5_mask)
 			break;
 		}
 	}
-
-	/* Disable SCI and SMI events */
-	google_chromeec_set_smi_mask(0);
-	google_chromeec_set_sci_mask(0);
-
-	/* Clear pending events that may trigger immediate wake */
-	clear_pending_events();
 }
 
 void chromeec_smi_device_event_sleep(int slp_type, uint64_t s3_mask,

From 7a703fc1fb83ffc206de2d6e96d1b88fc830d838 Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Tue, 11 Mar 2025 11:54:19 -0500
Subject: [PATCH 1113/3886] mb/google/rex: Select IOM_ACPI_DEVICE_VISIBLE

Needed for coolstar's IOM/TCSS drivers under Windows.

TEST=build/boot Win11 on google/screebo

Change-Id: Ib5a288d9b5d259c27f3b3b2b1b7b86e9c0e1f491
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86822
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
---
 src/mainboard/google/rex/Kconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/src/mainboard/google/rex/Kconfig b/src/mainboard/google/rex/Kconfig
index 42e551253f..b5f5c10b98 100644
--- a/src/mainboard/google/rex/Kconfig
+++ b/src/mainboard/google/rex/Kconfig
@@ -22,6 +22,7 @@ config BOARD_GOOGLE_REX_COMMON
 	select GOOGLE_SMBIOS_MAINBOARD_VERSION
 	select HAVE_ACPI_TABLES
 	select I2C_TPM
+	select IOM_ACPI_DEVICE_VISIBLE
 	select INTEL_LPSS_UART_FOR_CONSOLE
 	select MAINBOARD_DISABLE_STAGE_CACHE
 	select MAINBOARD_HAS_TPM2

From 71ae2c7366529ea1b0cc67d33fa8dec9bbd1f7e8 Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Wed, 21 May 2025 09:25:00 -0500
Subject: [PATCH 1114/3886] mb/google/octopus: Add VBTs for DOOD and FOOB
 variants

These variants were missing VBTs necessary for display init, so add
them. VBT files taken from the stock firmware images:
coreboot-Google_Dood.11297.368.0.bin
coreboot-Google_Foob.11297-169.0.bin

Since all variants other than the baseboard have VBTs, move the
selection of INTEL_GMA_HAVE_VBT to the baseboard and exclude the
octopus board.

TEST=build/boot various ocotpus variants, including dood/foob.

Change-Id: I67655b149de40e3e7f83971780f62cd7fce820c8
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87774
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/google/octopus/Kconfig             |  11 +----------
 .../google/octopus/variants/dood/data.vbt        | Bin 0 -> 5632 bytes
 .../google/octopus/variants/foob/data.vbt        | Bin 0 -> 5632 bytes
 3 files changed, 1 insertion(+), 10 deletions(-)
 create mode 100644 src/mainboard/google/octopus/variants/dood/data.vbt
 create mode 100644 src/mainboard/google/octopus/variants/foob/data.vbt

diff --git a/src/mainboard/google/octopus/Kconfig b/src/mainboard/google/octopus/Kconfig
index 9ae9e4c8e5..f5aed08225 100644
--- a/src/mainboard/google/octopus/Kconfig
+++ b/src/mainboard/google/octopus/Kconfig
@@ -19,6 +19,7 @@ config BOARD_GOOGLE_BASEBOARD_OCTOPUS
 	select GOOGLE_SMBIOS_MAINBOARD_VERSION
 	select HAVE_ACPI_RESUME
 	select HAVE_ACPI_TABLES
+	select INTEL_GMA_HAVE_VBT if !BOARD_GOOGLE_OCTOPUS
 	select INTEL_LPSS_UART_FOR_CONSOLE
 	select MAINBOARD_HAS_CHROMEOS
 	select MAINBOARD_HAS_TPM2
@@ -31,24 +32,20 @@ config BOARD_GOOGLE_BASEBOARD_OCTOPUS
 
 config BOARD_GOOGLE_AMPTON
 	select BOARD_GOOGLE_BASEBOARD_OCTOPUS
-	select INTEL_GMA_HAVE_VBT
 	select NHLT_RT5682 if INCLUDE_NHLT_BLOBS
 
 config BOARD_GOOGLE_BLOOG
 	select BOARD_GOOGLE_BASEBOARD_OCTOPUS
-	select INTEL_GMA_HAVE_VBT
 	select NHLT_DA7219 if INCLUDE_NHLT_BLOBS
 	select NHLT_RT5682 if INCLUDE_NHLT_BLOBS
 
 config BOARD_GOOGLE_BOBBA
 	select BOARD_GOOGLE_BASEBOARD_OCTOPUS
-	select INTEL_GMA_HAVE_VBT
 	select NHLT_DA7219 if INCLUDE_NHLT_BLOBS
 	select NHLT_RT5682 if INCLUDE_NHLT_BLOBS
 
 config BOARD_GOOGLE_CASTA
 	select BOARD_GOOGLE_BASEBOARD_OCTOPUS
-	select INTEL_GMA_HAVE_VBT
 	select NHLT_DA7219 if INCLUDE_NHLT_BLOBS
 
 config BOARD_GOOGLE_DOOD
@@ -57,7 +54,6 @@ config BOARD_GOOGLE_DOOD
 
 config BOARD_GOOGLE_FLEEX
 	select BOARD_GOOGLE_BASEBOARD_OCTOPUS
-	select INTEL_GMA_HAVE_VBT
 	select NHLT_DA7219 if INCLUDE_NHLT_BLOBS
 	select NHLT_RT5682 if INCLUDE_NHLT_BLOBS
 
@@ -67,18 +63,15 @@ config BOARD_GOOGLE_FOOB
 
 config BOARD_GOOGLE_GARG
 	select BOARD_GOOGLE_BASEBOARD_OCTOPUS
-	select INTEL_GMA_HAVE_VBT
 	select NHLT_DA7219 if INCLUDE_NHLT_BLOBS
 	select NHLT_RT5682 if INCLUDE_NHLT_BLOBS
 
 config BOARD_GOOGLE_LICK
 	select BOARD_GOOGLE_BASEBOARD_OCTOPUS
-	select INTEL_GMA_HAVE_VBT
 	select NHLT_DA7219 if INCLUDE_NHLT_BLOBS
 
 config BOARD_GOOGLE_MEEP
 	select BOARD_GOOGLE_BASEBOARD_OCTOPUS
-	select INTEL_GMA_HAVE_VBT
 	select NHLT_DA7219 if INCLUDE_NHLT_BLOBS
 	select NHLT_RT5682 if INCLUDE_NHLT_BLOBS
 
@@ -87,13 +80,11 @@ config BOARD_GOOGLE_OCTOPUS
 
 config BOARD_GOOGLE_PHASER
 	select BOARD_GOOGLE_BASEBOARD_OCTOPUS
-	select INTEL_GMA_HAVE_VBT
 	select NHLT_DA7219 if INCLUDE_NHLT_BLOBS
 	select NHLT_RT5682 if INCLUDE_NHLT_BLOBS
 
 config BOARD_GOOGLE_YORP
 	select BOARD_GOOGLE_BASEBOARD_OCTOPUS
-	select INTEL_GMA_HAVE_VBT
 	select NHLT_DA7219 if INCLUDE_NHLT_BLOBS
 
 if BOARD_GOOGLE_BASEBOARD_OCTOPUS
diff --git a/src/mainboard/google/octopus/variants/dood/data.vbt b/src/mainboard/google/octopus/variants/dood/data.vbt
new file mode 100644
index 0000000000000000000000000000000000000000..2848abe03352eaeedb9f8765343fc35d4577af87
GIT binary patch
literal 5632
zcmeHLYitx%6h5=F&pR{icFLnHwOk&SZGm=Lpp;teY_~04=wr7nwMLUZ*hLx(Ep5>v
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zqPs&i(>?j&@wdzM9z3Yn2FG2rp$LmOu54qIU$YK$y$p{!0QNdzqa3xqB3awi!DVF&
za5C7W%tfW8;4bXUt}5bSW#^tkTpq3dQo#Qs*jKU9=w8o>+}+Fe?O$ONocSA0zj-Y&
zGcz@(L7Qxx26#GXcqLAdHl>>T3I9CfnI;I3l9^jv)zs11^VI$W2M=j(4c>;&|2TW;
z?76e!{F#+!f~RAr50AY&_TJdVu_=^!6r+D7;l$ymzeUDzho{{f{j0a7|H;noxcn32
CN@6Ym

literal 0
HcmV?d00001

diff --git a/src/mainboard/google/octopus/variants/foob/data.vbt b/src/mainboard/google/octopus/variants/foob/data.vbt
new file mode 100644
index 0000000000000000000000000000000000000000..fbcf46e8494c759ef00a29bbd1b59c648a398994
GIT binary patch
literal 5632
zcmeHLYitx%6h1Sv&$~0*?UYAZYPmct+XC&hKq<A_*=}39(8q3DYK<m+u!}SnTH2yT
z1jbmBCPuSAe4rs(V~hs>kf^_m5r3#8L~Rq)@XHcnf&>y0G5P}-&z+feTT1DIprV}3
zx#!$7=YIE|bMKvdXIHdTG}BF0b>aGOZE#B!WfTJiUY~yo%b8RWZfI(&3^oVbDry@-
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zrfM(PX4-D#clT{Gvo@PW*V8SU&EvlP|DA!X8u-DjCFuAAK3DrPGZ)#nXIb(Dp1(W?
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zgMf>PA>8JgG!P^c!A?_%;=CV5B6Oi5Dk0X&$b*o;{fJ}GoF&G3V2gbARn3=bnY&BY
zsI6;~b0M&gAr=LG(agOsa#d*8Afw&qOJ}XjG2r_YNvy4ov_(30#k=b}cE<k$6&BRZ
zY1Q-K*n9%-=tr&coRHL~+W&(7@pZ&sN2?dWg=!pT7;o-dAp$X2&AkTa1TJ6UV0e=5
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zU2_<;f#)>9(?P>4agwx2)!a|`=b6AXj|aS2c_r1&on5`p?A^EjfacQR9r)spvzN}E
zJ3B6%S$-yTI)3`l*n4B|k6j#_M43Y|`d5-p9De#+WE^*R+Rf6xdPn-7=<Ke`KLM?q
BVlDsx

literal 0
HcmV?d00001


From 3ecaf04dad1bc5cec11ef9367fc9fc9992dc5e52 Mon Sep 17 00:00:00 2001
From: John Su <john_su@compal.corp-partner.google.com>
Date: Tue, 13 May 2025 13:28:54 +0800
Subject: [PATCH 1115/3886] mb/var/uldrenite: Use VBT with limited resolution
 for 4GBx32 memory

To have the best usage case on 4GBx32 memory sku, the external display
resolution must not exceed 2560x1700. So use the GPP_E13 signal level
to determine x32 memory configuration and apply the corresponding VBT
accordingly.

BUG=b:415850768
TEST=Check the log for the string "Use vbt-uldrenite_x32mem.bin"

Cq-Depend: chrome-internal:8258325
Change-Id: I82a7415b4c99de9278e04f07a9efb0dfa0bf753d
Signed-off-by: John Su <john_su@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87654
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/google/brya/Kconfig               |  1 +
 .../google/brya/variants/uldrenite/variant.c    | 17 +++++++++++++++++
 2 files changed, 18 insertions(+)

diff --git a/src/mainboard/google/brya/Kconfig b/src/mainboard/google/brya/Kconfig
index 59895cc839..07bbec852e 100644
--- a/src/mainboard/google/brya/Kconfig
+++ b/src/mainboard/google/brya/Kconfig
@@ -697,6 +697,7 @@ config BOARD_GOOGLE_ULDRENITE
 	select ENFORCE_MEM_CHANNEL_DISABLE
 	select HAVE_PCIE_WWAN
 	select HAVE_WWAN_POWER_SEQUENCE
+	select INTEL_GMA_HAVE_VBT
 	select MAINBOARD_HAS_GOOGLE_STRAUSS_KEYBOARD
 	select SOC_INTEL_COMMON_BLOCK_HDA_VERB
 	select SOC_INTEL_TCSS_USE_PDC_PMC_USBC_MUX_CONFIGURATION
diff --git a/src/mainboard/google/brya/variants/uldrenite/variant.c b/src/mainboard/google/brya/variants/uldrenite/variant.c
index a7927eb0d3..8f1a016fde 100644
--- a/src/mainboard/google/brya/variants/uldrenite/variant.c
+++ b/src/mainboard/google/brya/variants/uldrenite/variant.c
@@ -5,7 +5,9 @@
 #include <boardid.h>
 #include <console/console.h>
 #include <delay.h>
+#include <drivers/intel/gma/opregion.h>
 #include <fw_config.h>
+#include <gpio.h>
 #include <sar.h>
 #include <soc/bootblock.h>
 #include <stdlib.h>
@@ -172,6 +174,21 @@ void variant_update_descriptor(void)
 	}
 }
 
+const char *mainboard_vbt_filename(void)
+{
+	/*
+	 * GPP_E13 High -> One RAM Chip
+	 * GPP_E13 Low  -> Two RAM Chips
+	 */
+	if (gpio_get(GPP_E13)) {
+		printk(BIOS_INFO,
+			"x32 memory detected, so use vbt-uldrenite_x32mem.bin\n");
+		return "vbt-uldrenite_x32mem.bin";
+	}
+	printk(BIOS_INFO, "Non-x32 memory detected, so use vbt.bin\n");
+	return "vbt.bin";
+}
+
 void variant_configure_pads(void)
 {
 	const struct pad_config *base_pads;

From 643bba345c0f859c2a2db600778bd5dc3d0eccdb Mon Sep 17 00:00:00 2001
From: Zhongtian Wu <wuzhongtian@huaqin.corp-partner.google.com>
Date: Fri, 16 May 2025 15:42:55 +0800
Subject: [PATCH 1116/3886] mb/google/trulo/var/pujjocento: Enable touchscreen

Enable ELAN901C\PARA3406\PARA3408 touchscreen for pujjocento.

BUG=b:417106542
BRANCH=none
TEST=Build and boot to pujjocento. Verify touchscreen works.

Change-Id: I10b3234fc1656150c24750837f115e227221e039
Signed-off-by: Zhongtian Wu <wuzhongtian@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87710
Reviewed-by: Kun Liu <liukun11@huaqin.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 .../brya/variants/pujjocento/overridetree.cb  | 53 +++++++++++++++++++
 1 file changed, 53 insertions(+)

diff --git a/src/mainboard/google/brya/variants/pujjocento/overridetree.cb b/src/mainboard/google/brya/variants/pujjocento/overridetree.cb
index 991fdf054e..238f245acf 100644
--- a/src/mainboard/google/brya/variants/pujjocento/overridetree.cb
+++ b/src/mainboard/google/brya/variants/pujjocento/overridetree.cb
@@ -486,6 +486,59 @@ chip soc/intel/alderlake
 				device i2c 50 on end
 			end
 		end #I2C0
+		device ref i2c1 on
+			chip drivers/i2c/hid
+				register "generic.hid" = ""ELAN901C""
+				register "generic.desc" = ""ELAN Touchscreen""
+				register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_E11_IRQ)"
+				register "generic.detect" = "1"
+				register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C1)"
+				register "generic.reset_delay_ms" = "20"
+				register "generic.reset_off_delay_ms" = "2"
+				register "generic.stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C4)"
+				register "generic.stop_delay_ms" = "280"
+				register "generic.stop_off_delay_ms" = "2"
+				register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C0)"
+				register "generic.enable_delay_ms" = "1"
+				register "generic.has_power_resource" = "1"
+				register "hid_desc_reg_offset" = "0x01"
+				device i2c 10 on end
+			end
+			chip drivers/i2c/hid
+				register "generic.hid" = ""PARA3406""
+				register "generic.desc" = ""Parade Touchscreen""
+				register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_E11_IRQ)"
+				register "generic.detect" = "1"
+				register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C1)"
+				register "generic.reset_delay_ms" = "20"
+				register "generic.reset_off_delay_ms" = "2"
+				register "generic.stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C4)"
+				register "generic.stop_delay_ms" = "280"
+				register "generic.stop_off_delay_ms" = "2"
+				register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C0)"
+				register "generic.enable_delay_ms" = "1"
+				register "generic.has_power_resource" = "1"
+				register "hid_desc_reg_offset" = "0x01"
+				device i2c 24 on end
+			end
+			chip drivers/i2c/hid
+				register "generic.hid" = ""PARA3408""
+				register "generic.desc" = ""Parade Touchscreen""
+				register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_E11_IRQ)"
+				register "generic.detect" = "1"
+				register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C1)"
+				register "generic.reset_delay_ms" = "20"
+				register "generic.reset_off_delay_ms" = "2"
+				register "generic.stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C4)"
+				register "generic.stop_delay_ms" = "280"
+				register "generic.stop_off_delay_ms" = "2"
+				register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C0)"
+				register "generic.enable_delay_ms" = "1"
+				register "generic.has_power_resource" = "1"
+				register "hid_desc_reg_offset" = "0x01"
+				device i2c 24 on end
+			end
+		end #I2C1
 		device ref i2c5 on
 			chip drivers/i2c/generic
 				register "hid" = ""ELAN0000""

From 8c3e6ea319ff486fe93fd286cd3c6addaee70fdf Mon Sep 17 00:00:00 2001
From: Zhongtian Wu <wuzhongtian@huaqin.corp-partner.google.com>
Date: Fri, 16 May 2025 15:54:53 +0800
Subject: [PATCH 1117/3886] mb/google/nissa/var/pujjocento: Enable touchpad

Enable touchpad FTCS1000/GXTP5100/ELAN06FA for pujjocento.

BUG=b:417106542
BRANCH=none
TEST=Build and boot to pujjocento. Verify touchpad works.

Change-Id: I4c8cfdf9931282f366809b79198ec69c753b9814
Signed-off-by: Zhongtian Wu <wuzhongtian@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87711
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Kun Liu <liukun11@huaqin.corp-partner.google.com>
---
 .../brya/variants/pujjocento/overridetree.cb  | 35 ++++++++++++++-----
 1 file changed, 27 insertions(+), 8 deletions(-)

diff --git a/src/mainboard/google/brya/variants/pujjocento/overridetree.cb b/src/mainboard/google/brya/variants/pujjocento/overridetree.cb
index 238f245acf..c3753fac6f 100644
--- a/src/mainboard/google/brya/variants/pujjocento/overridetree.cb
+++ b/src/mainboard/google/brya/variants/pujjocento/overridetree.cb
@@ -83,7 +83,7 @@ chip soc/intel/alderlake
 		[PchSerialIoIndexI2C2] = PchSerialIoDisabled,
 		[PchSerialIoIndexI2C3] = PchSerialIoDisabled,
 		[PchSerialIoIndexI2C4] = PchSerialIoDisabled,
-		[PchSerialIoIndexI2C5] = PchSerialIoDisabled,
+		[PchSerialIoIndexI2C5] = PchSerialIoPci,
 	}"
 
 	register "serial_io_gspi_mode" = "{
@@ -540,13 +540,32 @@ chip soc/intel/alderlake
 			end
 		end #I2C1
 		device ref i2c5 on
-			chip drivers/i2c/generic
-				register "hid" = ""ELAN0000""
-				register "desc" = ""ELAN Touchpad""
-				register "irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_F14_IRQ)"
-				register "wake" = "GPE0_DW2_14"
-				register "detect" = "1"
-				device i2c 0x15 on end
+			chip drivers/i2c/hid
+				register "generic.hid" = ""FTCS1000""
+				register "generic.desc" = ""FocalTech Touchpad""
+				register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_F14_IRQ)"
+				register "generic.wake" = "GPE0_DW2_14"
+				register "generic.detect" = "1"
+				register "hid_desc_reg_offset" = "0x20"
+				device i2c 38 on end
+			end
+			chip drivers/i2c/hid
+				register "generic.hid" = ""GXTP5100""
+				register "generic.desc" = ""Goodix Touchpad""
+				register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_F14_IRQ)"
+				register "generic.wake" = "GPE0_DW2_14"
+				register "generic.detect" = "1"
+				register "hid_desc_reg_offset" = "0x20"
+				device i2c 2c on end
+			end
+			chip drivers/i2c/hid
+				register "generic.hid" = ""ELAN0000""
+				register "generic.desc" = ""ELAN Touchpad""
+				register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_F14_IRQ)"
+				register "generic.wake" = "GPE0_DW2_14"
+				register "generic.detect" = "1"
+				register "hid_desc_reg_offset" = "0x01"
+				device i2c 15 on end
 			end
 		end
 		device ref heci1 on end

From 0db4444446b0f6ad4d16ee758a69ad9316d9266f Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Mon, 5 May 2025 10:38:20 -0500
Subject: [PATCH 1118/3886] mb/google/byra/var/pujjo: Add VBT for pujjo1e

Extracted from coreboot-Google_Pujjo.15217.460.0.bin.

TEST=build/boot pujjo1e variant with working display.

Change-Id: I82425bdbbba93197fb7b6f7a866412dc49066cdf
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87555
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Reviewed-by: Eric Lai <ericllai@google.com>
---
 .../google/brya/variants/pujjo/Makefile.mk       |   2 ++
 .../google/brya/variants/pujjo/data-pujjo1e.vbt  | Bin 0 -> 9216 bytes
 2 files changed, 2 insertions(+)
 create mode 100644 src/mainboard/google/brya/variants/pujjo/data-pujjo1e.vbt

diff --git a/src/mainboard/google/brya/variants/pujjo/Makefile.mk b/src/mainboard/google/brya/variants/pujjo/Makefile.mk
index e04a887191..b24e2ab871 100644
--- a/src/mainboard/google/brya/variants/pujjo/Makefile.mk
+++ b/src/mainboard/google/brya/variants/pujjo/Makefile.mk
@@ -6,3 +6,5 @@ romstage-y += gpio.c
 ramstage-$(CONFIG_FW_CONFIG) += fw_config.c
 ramstage-y += variant.c
 ramstage-y += gpio.c
+
+$(call add_vbt_to_cbfs, vbt-pujjo1e.bin, data-pujjo1e.vbt)
diff --git a/src/mainboard/google/brya/variants/pujjo/data-pujjo1e.vbt b/src/mainboard/google/brya/variants/pujjo/data-pujjo1e.vbt
new file mode 100644
index 0000000000000000000000000000000000000000..81b3ac6304d62552164c4608e5f67e9139a966dd
GIT binary patch
literal 9216
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literal 0
HcmV?d00001


From 2ce777f178fd5d4185a79dbdc6ce5f69617123f4 Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Mon, 5 May 2025 10:43:54 -0500
Subject: [PATCH 1119/3886] mb/google/byra/var/yaviks: Add VBT for yavilla

Extracted from coreboot-Google_Yaviks.15217.552.0.bin

TEST=build/boot yaviks/yavilla variant with working display.

Change-Id: I775baf4216eef2a60bc1ac034cef3c5c7c38ea69
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87556
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
---
 .../google/brya/variants/yaviks/Makefile.mk      |   2 ++
 .../google/brya/variants/yaviks/data-yavilla.vbt | Bin 0 -> 9216 bytes
 2 files changed, 2 insertions(+)
 create mode 100644 src/mainboard/google/brya/variants/yaviks/data-yavilla.vbt

diff --git a/src/mainboard/google/brya/variants/yaviks/Makefile.mk b/src/mainboard/google/brya/variants/yaviks/Makefile.mk
index 86ba20d3c3..e0af3540b6 100644
--- a/src/mainboard/google/brya/variants/yaviks/Makefile.mk
+++ b/src/mainboard/google/brya/variants/yaviks/Makefile.mk
@@ -6,3 +6,5 @@ romstage-y += gpio.c
 ramstage-$(CONFIG_FW_CONFIG) += fw_config.c
 ramstage-$(CONFIG_FW_CONFIG) += variant.c
 ramstage-y += gpio.c
+
+$(call add_vbt_to_cbfs, vbt-yavilla.bin, data-yavilla.vbt)
diff --git a/src/mainboard/google/brya/variants/yaviks/data-yavilla.vbt b/src/mainboard/google/brya/variants/yaviks/data-yavilla.vbt
new file mode 100644
index 0000000000000000000000000000000000000000..abcb0f119e400cdac1d1e8d4fb54369eb08a56d8
GIT binary patch
literal 9216
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literal 0
HcmV?d00001


From 885aacf0046b9833b1f76b0c818a5c8580c4d7f4 Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Mon, 5 May 2025 10:56:33 -0500
Subject: [PATCH 1120/3886] mb/google/byra/var/teliks: Add VBT for 11" panel
 option

Extracted from coreboot-Google_Teliks.15217.734.0.bin

Change-Id: I2c6b00ab0fc67b651256ec32d4d983b987435010
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87557
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 .../google/brya/variants/teliks/Makefile.mk      |   2 ++
 .../teliks/data-teliks_panel_11_inch.vbt         | Bin 0 -> 9216 bytes
 2 files changed, 2 insertions(+)
 create mode 100644 src/mainboard/google/brya/variants/teliks/data-teliks_panel_11_inch.vbt

diff --git a/src/mainboard/google/brya/variants/teliks/Makefile.mk b/src/mainboard/google/brya/variants/teliks/Makefile.mk
index efe5002383..ce2f87618d 100644
--- a/src/mainboard/google/brya/variants/teliks/Makefile.mk
+++ b/src/mainboard/google/brya/variants/teliks/Makefile.mk
@@ -7,3 +7,5 @@ romstage-y += gpio.c
 ramstage-y += gpio.c
 
 ramstage-y += variant.c
+
+$(call add_vbt_to_cbfs, vbt-teliks_panel_11_inch.bin, data-teliks_panel_11_inch.vbt)
diff --git a/src/mainboard/google/brya/variants/teliks/data-teliks_panel_11_inch.vbt b/src/mainboard/google/brya/variants/teliks/data-teliks_panel_11_inch.vbt
new file mode 100644
index 0000000000000000000000000000000000000000..05130446f4b462d25ec6895209d91f9567b09e55
GIT binary patch
literal 9216
zcmeHMT}&KR6h3!mciFCsYz5mbR=kCV0u~sS7AYZNmIds#{475u+th?D-PIClK}wYx
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z6c{KlP+;I+WT5S1Wk0<zPGl%1UR6bCjXj<Ex+lJ366qfhag|sN85D*uv)<N9+pT+W
zu<6W83wV27jhAE&nTmnq+9!B7ZC_*>O~Xe+J3Pxm5>R2AvvcNwt=#6xv6(*z+Zqeg
zB5c(;w$(X>bcd$sKv}l=a%^||7>(MOSPz+qr2;nVjiQ16zF%czI^v`e2WCYk&ID}c
zX@!g;%eHK*LhjaQM`5$Y8O80ZEJW96UabVC^^7fSA_v{ELS7n#Eh@aBR(@OYl7RhS
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J$p4jr-vQI#dkO#m

literal 0
HcmV?d00001


From cdcbb719366ed8e36237bf4f5e78ddbdb17077ea Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= <kyosti.malkki@gmail.com>
Date: Thu, 5 Jan 2023 18:05:11 +0200
Subject: [PATCH 1121/3886] mb/google/link: Use chromeec_smi_sleep()
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

SMI handler previously did not evaluate input slp_typ parameter and
apparently always acted as S3 was requested.

With the change keyboard is no longer a wakeup source from S4/S5, it is assumed MAINBOARD_EC_S5_WAKE attribute defined in ec.h is correct.

Change-Id: I54c7d7455a6737f731c65e57c91b6457643c7cb2
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74603
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Boris Mittelberg <bmbm@google.com>
---
 src/mainboard/google/link/smihandler.c | 11 +----------
 1 file changed, 1 insertion(+), 10 deletions(-)

diff --git a/src/mainboard/google/link/smihandler.c b/src/mainboard/google/link/smihandler.c
index b75bd4aacb..3cbdfdced3 100644
--- a/src/mainboard/google/link/smihandler.c
+++ b/src/mainboard/google/link/smihandler.c
@@ -22,16 +22,7 @@ void mainboard_smi_sleep(u8 slp_typ)
 	/* Disable USB charging if required */
 	chromeec_set_usb_charge_mode(slp_typ);
 
-	/* Disable SCI and SMI events */
-	google_chromeec_set_smi_mask(0);
-	google_chromeec_set_sci_mask(0);
-
-	/* Clear pending events that may trigger immediate wake */
-	while (google_chromeec_get_event() != EC_HOST_EVENT_NONE)
-		;
-
-	/* Enable wake events */
-	google_chromeec_set_wake_mask(MAINBOARD_EC_S3_WAKE_EVENTS);
+	chromeec_smi_sleep(slp_typ, MAINBOARD_EC_S3_WAKE_EVENTS, MAINBOARD_EC_S5_WAKE_EVENTS);
 }
 
 int mainboard_smi_apmc(u8 apmc)

From da45a88dd33e88aa59c2669f64a4ae7490dfc199 Mon Sep 17 00:00:00 2001
From: Yu-Ping Wu <yupingso@chromium.org>
Date: Fri, 23 May 2025 12:58:19 +0800
Subject: [PATCH 1122/3886] util/abuild: Fix checking of missing_arches

The commit f66c7c1037e9 ("util/abuild: Update echo to printf for
consistency") accidentally added whitespaces to the missing_arches
variable, causing the [[ -n "${missing_arches}" ]] check to fail.

The commit c81b08c4bac7 ("util/abuild: Fix building ChromeOS boards")
intended to fix it, but did it the wrong way.

Now, really fix the problem from the Makefile snippet that is causing
the whitespace issue.

Change-Id: I5e417e851840bad000492bf737fc8e25063fe0c4
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87809
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
---
 util/abuild/abuild | 9 +++++----
 1 file changed, 5 insertions(+), 4 deletions(-)

diff --git a/util/abuild/abuild b/util/abuild/abuild
index 007ced4ed8..faac3eb347 100755
--- a/util/abuild/abuild
+++ b/util/abuild/abuild
@@ -586,10 +586,11 @@ build_config()
 	missing_arches="$(${MAKE} --no-print-directory -f - \
 		REQUIRED_ARCHES="${required_arches}" <<'EOF'
 include $(xcompile)
-.PHONY: missing_arches
-missing_arches:
+MISSING_ARCHES=$(foreach arch,$(REQUIRED_ARCHES),$(if $(filter $(arch),$(SUBARCH_SUPPORTED)),,$(arch)))
+.PHONY: check_missing_arches
+check_missing_arches:
 	$(if $(XCOMPILE_COMPLETE),,$(error $(xcompile) is invalid.))
-	@printf "%s\n" "$(foreach arch,$(REQUIRED_ARCHES),$(if $(filter $(arch),$(SUBARCH_SUPPORTED)),,$(arch)))"
+	@printf "%s\n" "$(strip $(MISSING_ARCHES))"
 EOF
 )"
 	# shellcheck disable=SC2181
@@ -598,7 +599,7 @@ EOF
 		exit 1
 	fi
 
-	if [[ -z "${missing_arches}" ]]; then
+	if [[ -n "${missing_arches}" ]]; then
 		printf "skipping %s because we're missing compilers for (%s)\n" "${BUILD_NAME}" "${missing_arches}"
 		return
 	fi

From d1f75654030711d84cf7756311c54e4b8f0fd35a Mon Sep 17 00:00:00 2001
From: Cong Yang <yangcong5@huaqin.corp-partner.google.com>
Date: Thu, 20 Feb 2025 10:07:18 +0800
Subject: [PATCH 1123/3886] mb/google/skywalker: Notify EC that AP is in S0

GPIO_AP_SUSPEND_L is supposed to be high in S0, and low in S3. EC uses
this pin to determine the AP power state. This pin should be set as
early as possible in bootblock.

BUG=b:396030112
BRANCH=none
TEST=reboot pass. `powerinfo` shows S0 in EC console.

Change-Id: Ib7e9eaa19d232a37b3793bcbe268ba021e456ac7
Signed-off-by: Cong Yang <yangcong5@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87793
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
---
 src/mainboard/google/skywalker/chromeos.c | 1 +
 src/mainboard/google/skywalker/gpio.h     | 1 +
 2 files changed, 2 insertions(+)

diff --git a/src/mainboard/google/skywalker/chromeos.c b/src/mainboard/google/skywalker/chromeos.c
index eb310f3576..ffc0e9550b 100644
--- a/src/mainboard/google/skywalker/chromeos.c
+++ b/src/mainboard/google/skywalker/chromeos.c
@@ -13,6 +13,7 @@ void setup_chromeos_gpios(void)
 	gpio_input(GPIO_GSC_AP_INT_ODL);
 	gpio_output(GPIO_AP_EC_WARM_RST_REQ, 0);
 	gpio_output(GPIO_XHCI_INIT_DONE, 0);
+	gpio_output(GPIO_AP_SUSPEND_L, 1);
 }
 
 void fill_lb_gpios(struct lb_gpios *gpios)
diff --git a/src/mainboard/google/skywalker/gpio.h b/src/mainboard/google/skywalker/gpio.h
index 1fc4674de5..22ee14d855 100644
--- a/src/mainboard/google/skywalker/gpio.h
+++ b/src/mainboard/google/skywalker/gpio.h
@@ -10,6 +10,7 @@
 #define GPIO_EC_AP_INT_ODL	GPIO(GBE_MDIO)
 #define GPIO_AP_EC_WARM_RST_REQ	GPIO(GBE_AUX_PPS0)
 #define GPIO_GSC_AP_INT_ODL	GPIO(GBE_AUX_PPS1)
+#define GPIO_AP_SUSPEND_L	GPIO(CONN_TOP_DATA)
 
 void setup_chromeos_gpios(void);
 

From c74610afae219d118b25d59479333f50e89da88d Mon Sep 17 00:00:00 2001
From: Wentao Qin <qinwentao@huaqin.corp-partner.google.com>
Date: Tue, 18 Feb 2025 14:25:02 +0800
Subject: [PATCH 1124/3886] soc/mediatek/mt8189: Shut down PMIC on power key
 long press

Currently on power key long press, PMIC will be reset. It would cause
an unwanted reset pulse in the power-off sequence. To match expected
sequence, change PMIC behavior to "force shutdown".

BUG=b:395848137
BRANCH=none
TEST=long-pressing power key doesn't trigger PMIC_AP_RST_L pulse

Change-Id: Ia8fb9f4a1ffe05955fca51a58468ba338ef8e12d
Signed-off-by: Haikun Zhou <zhouhaikun5@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87798
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
---
 src/soc/mediatek/mt8189/mt6359p.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/src/soc/mediatek/mt8189/mt6359p.c b/src/soc/mediatek/mt8189/mt6359p.c
index 0f899a337a..7b399abf0f 100644
--- a/src/soc/mediatek/mt8189/mt6359p.c
+++ b/src/soc/mediatek/mt8189/mt6359p.c
@@ -31,7 +31,8 @@ static const struct pmic_setting init_setting[] = {
 	{0xA08, 0x1, 0x1, 0},
 	{0xA0C, 0x300, 0x300, 0},
 	{0xA10, 0x0, 0x4000, 0},
-	{0xA12, 0x1E0, 0x1E0, 0},
+	/* Force shutdown on power key long press */
+	{0xA12, 0x1F2, 0x1F2, 0},
 	{0xA24, 0xFFFF, 0xFFFF, 0},
 	{0xA26, 0xFFE0, 0xFFE0, 0},
 	{0xA2C, 0xC0DF, 0xC0DF, 0},

From 090bce1042ff4225fabb5644f1a338374aacddbd Mon Sep 17 00:00:00 2001
From: Vince Liu <vince-wl.liu@mediatek.corp-partner.google.com>
Date: Fri, 28 Mar 2025 11:11:54 +0800
Subject: [PATCH 1125/3886] soc/mediatek/common: Add VMODEM and VSRAM_MD bucks
 support for MT6359

Add support for VMODEM and VSRAM_MD buck converters in MT6359. These
buck converters are required for MT8189 to adjust voltage and CPU
frequency.

BUG=b:379008996
BRANCH=none
TEST=build passed.

Signed-off-by: Zhigang Qin <zhigang.qin@mediatek.corp-partner.google.com>
Change-Id: Ifdf43748a139050ec9fba50f918e071dc622a670
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87799
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
---
 src/soc/mediatek/common/include/soc/mt6359p.h |  8 ++++++-
 src/soc/mediatek/common/mt6359p.c             | 22 +++++++++++++++++++
 2 files changed, 29 insertions(+), 1 deletion(-)

diff --git a/src/soc/mediatek/common/include/soc/mt6359p.h b/src/soc/mediatek/common/include/soc/mt6359p.h
index b829eb6e83..017e6c8d61 100644
--- a/src/soc/mediatek/common/include/soc/mt6359p.h
+++ b/src/soc/mediatek/common/include/soc/mt6359p.h
@@ -22,6 +22,8 @@ enum {
 	PMIC_VCORE_ELR0		= 0x152c,
 	PMIC_VGPU11_DBG0	= 0x15a6,
 	PMIC_VGPU11_ELR0	= 0x15b4,
+	PMIC_VMODEM_DBG0	= 0x16a6,
+	PMIC_VMODEM_ELR0	= 0x16ae,
 	PMIC_VS2_VOTER		= 0x18aa,
 	PMIC_VS2_VOTER_CFG	= 0x18b0,
 	PMIC_VS2_ELR0		= 0x18b4,
@@ -30,12 +32,14 @@ enum {
 	PMIC_VPA_DBG0		= 0x1914,
 	PMIC_BUCK_VPA_DLC_CON0	= 0x1918,
 	PMIC_BUCK_VPA_DLC_CON1	= 0x191a,
-	PMIC_VSIM1_CON0		= 0x1cd0,
 	PMIC_VSRAM_PROC1_ELR	= 0x1b44,
 	PMIC_VSRAM_PROC2_ELR	= 0x1b46,
+	PMIC_VSRAM_MD_ELR	= 0x1b4a,
+	PMIC_VSIM1_CON0		= 0x1cd0,
 	PMIC_VM18_CON0		= 0x1d88,
 	PMIC_VSRAM_PROC1_VOSEL1	= 0x1e90,
 	PMIC_VSRAM_PROC2_VOSEL1	= 0x1eb0,
+	PMIC_VSRAM_MD_VOSEL1	= 0x1f36,
 	PMIC_VSIM1_ANA_CON0	= 0x1fa2,
 	PMIC_VM18_ANA_CON0	= 0x2020,
 };
@@ -62,6 +66,8 @@ enum {
 	MT6359P_PA,
 	MT6359P_SIM1,
 	MT6359P_VM18,
+	MT6359P_VMODEM,
+	MT6359P_VSRAM_MD,
 	MT6359P_MAX,
 };
 
diff --git a/src/soc/mediatek/common/mt6359p.c b/src/soc/mediatek/common/mt6359p.c
index 6b09d57caa..8026f29915 100644
--- a/src/soc/mediatek/common/mt6359p.c
+++ b/src/soc/mediatek/common/mt6359p.c
@@ -190,6 +190,16 @@ void mt6359p_buck_set_voltage(u32 buck_id, u32 buck_uv)
 		vol_reg = PMIC_VPA_CON1;
 		vol_step = 50000;
 		break;
+	case MT6359P_VMODEM:
+		vol_offset = 400000;
+		vol_reg = PMIC_VMODEM_ELR0;
+		vol_step = 6250;
+		break;
+	case MT6359P_VSRAM_MD:
+		vol_offset = 500000;
+		vol_reg = PMIC_VSRAM_MD_ELR;
+		vol_step = 6250;
+		break;
 	default:
 		die("ERROR: Unknown buck_id %u", buck_id);
 		return;
@@ -237,6 +247,18 @@ u32 mt6359p_buck_get_voltage(u32 buck_id)
 		vol_reg = PMIC_VPA_DBG0;
 		vol_step = 50000;
 		break;
+	case MT6359P_VMODEM:
+		vol_shift = 0;
+		vol_offset = 400000;
+		vol_reg = PMIC_VMODEM_DBG0;
+		vol_step = 6250;
+		break;
+	case MT6359P_VSRAM_MD:
+		vol_shift = 8;
+		vol_offset = 500000;
+		vol_reg = PMIC_VSRAM_MD_VOSEL1;
+		vol_step = 6250;
+		break;
 	default:
 		die("ERROR: Unknown buck_id %u", buck_id);
 		return 0;

From 0ba0d03140941a558f2aa990a7489ab683822335 Mon Sep 17 00:00:00 2001
From: Vince Liu <vince-wl.liu@mediatek.corp-partner.google.com>
Date: Fri, 28 Mar 2025 11:34:15 +0800
Subject: [PATCH 1126/3886] mb/google/skywalker: Implement regulator interface

Control regulator more easily with regulator interface.

BUG=b:379008996
BRANCH=none
TEST=build passed.

Signed-off-by: Zhigang Qin <zhigang.qin@mediatek.corp-partner.google.com>
Change-Id: Ie7bfc9c3fb4e5f50cdf1ed8174366bdafaf3c49a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87794
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
---
 src/mainboard/google/skywalker/Makefile.mk |   2 +
 src/mainboard/google/skywalker/regulator.c | 102 +++++++++++++++++++++
 2 files changed, 104 insertions(+)
 create mode 100644 src/mainboard/google/skywalker/regulator.c

diff --git a/src/mainboard/google/skywalker/Makefile.mk b/src/mainboard/google/skywalker/Makefile.mk
index 6c863fe287..3e5bad3f37 100644
--- a/src/mainboard/google/skywalker/Makefile.mk
+++ b/src/mainboard/google/skywalker/Makefile.mk
@@ -7,6 +7,8 @@ all-y += reset.c
 bootblock-y += bootblock.c
 
 romstage-y += romstage.c
+romstage-y += regulator.c
 
 ramstage-y += boardid.c
 ramstage-y += mainboard.c
+ramstage-y += regulator.c
diff --git a/src/mainboard/google/skywalker/regulator.c b/src/mainboard/google/skywalker/regulator.c
new file mode 100644
index 0000000000..46d0e2b8a2
--- /dev/null
+++ b/src/mainboard/google/skywalker/regulator.c
@@ -0,0 +1,102 @@
+/* SPDX-License-Identifier: GPL-2.0-only OR MIT */
+
+#include <console/console.h>
+#include <soc/mt6359p.h>
+#include <soc/regulator.h>
+
+#define MTK_REGULATOR_INVALID -1
+
+static int get_mt6359p_regulator_id(enum mtk_regulator regulator)
+{
+	switch (regulator) {
+	case MTK_REGULATOR_VPROC12:
+		return MT6359P_VMODEM;
+	case MTK_REGULATOR_VSRAM_PROC12:
+		return MT6359P_VSRAM_MD;
+	case MTK_REGULATOR_VMCH:
+		return MT6359P_PA;
+	case MTK_REGULATOR_VMC:
+		return MT6359P_SIM1;
+	default:
+		return MTK_REGULATOR_INVALID;
+	}
+}
+
+void mainboard_set_regulator_voltage(enum mtk_regulator regulator, uint32_t voltage_uv)
+{
+	int id;
+
+	id = get_mt6359p_regulator_id(regulator);
+	if (id < 0) {
+		printk(BIOS_ERR, "%s: Invalid regulator ID: %d\n", __func__, regulator);
+		return;
+	}
+
+	switch (id) {
+	case MT6359P_VMODEM:
+		mt6359p_buck_set_voltage(MT6359P_VMODEM, voltage_uv);
+		break;
+	case MT6359P_VSRAM_MD:
+		mt6359p_buck_set_voltage(MT6359P_VSRAM_MD, voltage_uv);
+		break;
+	case MT6359P_PA:
+		mt6359p_buck_set_voltage(MT6359P_PA, voltage_uv);
+		break;
+	case MT6359P_SIM1:
+		mt6359p_set_vsim1_voltage(voltage_uv);
+		break;
+	default:
+		printk(BIOS_ERR, "%s: Regulator ID %d: not supported\n", __func__, regulator);
+		break;
+	}
+}
+
+uint32_t mainboard_get_regulator_voltage(enum mtk_regulator regulator)
+{
+	int id;
+
+	id = get_mt6359p_regulator_id(regulator);
+	if (id < 0) {
+		printk(BIOS_ERR, "%s: Invalid regulator ID: %d\n", __func__, regulator);
+		return 0;
+	}
+
+	switch (id) {
+	case MT6359P_VMODEM:
+		return mt6359p_buck_get_voltage(MT6359P_VMODEM);
+	case MT6359P_VSRAM_MD:
+		return mt6359p_buck_get_voltage(MT6359P_VSRAM_MD);
+	case MT6359P_PA:
+		return mt6359p_buck_get_voltage(MT6359P_PA);
+	case MT6359P_SIM1:
+		return mt6359p_get_vsim1_voltage();
+	default:
+		printk(BIOS_ERR, "%s: Regulator ID %d: not supported\n", __func__, regulator);
+		return 0;
+	}
+}
+
+int mainboard_enable_regulator(enum mtk_regulator regulator, bool enable)
+{
+	int id;
+
+	id = get_mt6359p_regulator_id(regulator);
+	if (id < 0) {
+		printk(BIOS_ERR, "%s: Invalid regulator ID: %d\n", __func__, regulator);
+		return -1;
+	}
+
+	switch (id) {
+	case MT6359P_PA:
+		mt6359p_enable_vpa(enable);
+		break;
+	case MT6359P_SIM1:
+		mt6359p_enable_vsim1(enable);
+		break;
+	default:
+		printk(BIOS_ERR, "%s: Regulator ID %d: not supported\n", __func__, regulator);
+		break;
+	}
+
+	return 0;
+}

From 0f2942b513ab38e06cb29c740d36756159e572d7 Mon Sep 17 00:00:00 2001
From: Zhigang Qin <zhigang.qin@mediatek.corp-partner.google.com>
Date: Thu, 13 Mar 2025 16:29:32 +0800
Subject: [PATCH 1127/3886] mb/google/skywalker: Raise little core CPU
 frequency to 2.0 GHz
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Increase the CPU little core frequency from 1.6 GHz to 2.0 GHz to
speed up the boot process.

BUG=b:379008996
BRANCH=none
TEST=check little core cpu frequency is 2GHz in kernel by commands
clkdbg() { echo $@ > /proc/clkdbg ; cat /proc/clkdbg ; }
clkdbg fmeter

See the little core CPU frequency:
fm_armpll_ll_ck          	: 1999968

Signed-off-by: Zhigang Qin <zhigang.qin@mediatek.corp-partner.google.com>
Change-Id: I979f44e9340ea5bd733dc7f0fe47af47a4f403b7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87795
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/google/skywalker/romstage.c | 13 +++++++++++++
 1 file changed, 13 insertions(+)

diff --git a/src/mainboard/google/skywalker/romstage.c b/src/mainboard/google/skywalker/romstage.c
index 1ba948ee9e..3b6de958d1 100644
--- a/src/mainboard/google/skywalker/romstage.c
+++ b/src/mainboard/google/skywalker/romstage.c
@@ -1,17 +1,30 @@
 /* SPDX-License-Identifier: GPL-2.0-only OR MIT */
 
 #include <arch/stages.h>
+#include <delay.h>
 #include <soc/emi.h>
 #include <soc/mt6315.h>
 #include <soc/mt6359p.h>
+#include <soc/pll.h>
 #include <soc/pmif.h>
+#include <soc/regulator.h>
 #include <soc/rtc.h>
 
+static void raise_little_cpu_freq(void)
+{
+	mainboard_set_regulator_voltage(MTK_REGULATOR_VSRAM_PROC12, 1050000);
+	mainboard_set_regulator_voltage(MTK_REGULATOR_VPROC12, 1050000);
+	udelay(200);
+	mt_pll_raise_little_cpu_freq(2000 * MHz);
+	mt_pll_raise_cci_freq(1540 * MHz);
+}
+
 void platform_romstage_main(void)
 {
 	mtk_pmif_init();
 	mt6315_init();
 	mt6359p_init();
+	raise_little_cpu_freq();
 	rtc_boot();
 	mtk_dram_init();
 }

From 1a00629ae205c90b612568703da92ea74a2f45d8 Mon Sep 17 00:00:00 2001
From: Haikun Zhou <zhouhaikun5@huaqin.corp-partner.google.com>
Date: Mon, 24 Feb 2025 16:22:45 +0800
Subject: [PATCH 1128/3886] mb/google/skywalker: Set up open-drain ChromeOS
 pins

Set open-drain GPIOs for ChromeOS as input and bias-disable mode. Also
set AP_HDMI_RST_ODL to low, which is the only open-drain output pin.

BUG=b:397102113
BRANCH=none
TEST=build pass

Change-Id: I4375c25768de8f1462c491b2c84b9cf31f118126
Signed-off-by: Haikun Zhou <zhouhaikun5@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87796
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/google/skywalker/chromeos.c | 14 +++++++++++++
 src/mainboard/google/skywalker/gpio.h     | 25 +++++++++++++++++------
 2 files changed, 33 insertions(+), 6 deletions(-)

diff --git a/src/mainboard/google/skywalker/chromeos.c b/src/mainboard/google/skywalker/chromeos.c
index ffc0e9550b..02abb5f899 100644
--- a/src/mainboard/google/skywalker/chromeos.c
+++ b/src/mainboard/google/skywalker/chromeos.c
@@ -11,9 +11,23 @@ void setup_chromeos_gpios(void)
 {
 	gpio_input(GPIO_EC_AP_INT_ODL);
 	gpio_input(GPIO_GSC_AP_INT_ODL);
+	gpio_input(GPIO_HP_INT_ODL);
+	gpio_input(GPIO_SPKR_INT_ODL);
+	gpio_input(GPIO_SAR_INT_ODL);
+	gpio_input(GPIO_PEN_EJECT_OD);
+	gpio_input(GPIO_TCHSCR_INT_1V8_ODL);
+	gpio_input(GPIO_AP_WP_ODL);
+	gpio_input(GPIO_EC_AP_DPOC_EN_ODL);
+	gpio_input(GPIO_TCHPAD_INT_ODL);
+	gpio_input(GPIO_HDMI_AP_INT_ODL);
+	gpio_input(GPIO_FP_AP_INT_1V8_S3_ODL);
+	gpio_input(GPIO_SD_CD_ODL);
+	gpio_input(GPIO_HDMI_HPD_1V8_ODL);
+
 	gpio_output(GPIO_AP_EC_WARM_RST_REQ, 0);
 	gpio_output(GPIO_XHCI_INIT_DONE, 0);
 	gpio_output(GPIO_AP_SUSPEND_L, 1);
+	gpio_output(GPIO_AP_HDMI_RST_ODL, 0);
 }
 
 void fill_lb_gpios(struct lb_gpios *gpios)
diff --git a/src/mainboard/google/skywalker/gpio.h b/src/mainboard/google/skywalker/gpio.h
index 22ee14d855..5bd8744126 100644
--- a/src/mainboard/google/skywalker/gpio.h
+++ b/src/mainboard/google/skywalker/gpio.h
@@ -5,12 +5,25 @@
 
 #include <soc/gpio.h>
 
-#define GPIO_XHCI_INIT_DONE	GPIO(GBE_MDC)
-#define GPIO_USB3_HUB_RST_L	GPIO(GPIO07)
-#define GPIO_EC_AP_INT_ODL	GPIO(GBE_MDIO)
-#define GPIO_AP_EC_WARM_RST_REQ	GPIO(GBE_AUX_PPS0)
-#define GPIO_GSC_AP_INT_ODL	GPIO(GBE_AUX_PPS1)
-#define GPIO_AP_SUSPEND_L	GPIO(CONN_TOP_DATA)
+#define GPIO_XHCI_INIT_DONE		GPIO(GBE_MDC)
+#define GPIO_USB3_HUB_RST_L		GPIO(GPIO07)
+#define GPIO_EC_AP_INT_ODL		GPIO(GBE_MDIO)
+#define GPIO_AP_EC_WARM_RST_REQ		GPIO(GBE_AUX_PPS0)
+#define GPIO_GSC_AP_INT_ODL		GPIO(GBE_AUX_PPS1)
+#define GPIO_AP_SUSPEND_L		GPIO(CONN_TOP_DATA)
+#define GPIO_HP_INT_ODL			GPIO(GPIO04)
+#define GPIO_SPKR_INT_ODL		GPIO(GPIO08)
+#define GPIO_SAR_INT_ODL		GPIO(GPIO09)
+#define GPIO_PEN_EJECT_OD		GPIO(GPIO11)
+#define GPIO_TCHSCR_INT_1V8_ODL		GPIO(GPIO15)
+#define GPIO_AP_WP_ODL			GPIO(GPIO16)
+#define GPIO_EC_AP_DPOC_EN_ODL		GPIO(GPIO17)
+#define GPIO_TCHPAD_INT_ODL		GPIO(GBE_RXD1)
+#define GPIO_HDMI_AP_INT_ODL		GPIO(GBE_RXC)
+#define GPIO_FP_AP_INT_1V8_S3_ODL	GPIO(GBE_RXDV)
+#define GPIO_SD_CD_ODL			GPIO(GBE_INTR)
+#define GPIO_HDMI_HPD_1V8_ODL		GPIO(CONN_TOP_CLK)
+#define GPIO_AP_HDMI_RST_ODL		GPIO(GBE_TXC)
 
 void setup_chromeos_gpios(void);
 

From ccb8b34194f6ea516e9424b305da185a6601a698 Mon Sep 17 00:00:00 2001
From: Kapil Porwal <kapilporwal@google.com>
Date: Sat, 24 May 2025 22:15:31 +0530
Subject: [PATCH 1129/3886] Revert "mb/var/uldrenite: Use VBT with limited
 resolution for 4GBx32 memory"

This reverts commit 3ecaf04dad1bc5cec11ef9367fc9fc9992dc5e52.

Reason for revert: Build failure

```
make[2]: *** No rule to make target 'src/mainboard/google/brya/variants/uldrenite/data.vbt', needed by '/cb-build/coreboot-gerrit.0/gcc-chromeos/GOOGLE_ULDRENITE/coreboot.pre'.  Stop.
```

Change-Id: Ibc1c887c38950d22c91b0ecc76167c2ab7e6ae33
Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87816
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
---
 src/mainboard/google/brya/Kconfig               |  1 -
 .../google/brya/variants/uldrenite/variant.c    | 17 -----------------
 2 files changed, 18 deletions(-)

diff --git a/src/mainboard/google/brya/Kconfig b/src/mainboard/google/brya/Kconfig
index 07bbec852e..59895cc839 100644
--- a/src/mainboard/google/brya/Kconfig
+++ b/src/mainboard/google/brya/Kconfig
@@ -697,7 +697,6 @@ config BOARD_GOOGLE_ULDRENITE
 	select ENFORCE_MEM_CHANNEL_DISABLE
 	select HAVE_PCIE_WWAN
 	select HAVE_WWAN_POWER_SEQUENCE
-	select INTEL_GMA_HAVE_VBT
 	select MAINBOARD_HAS_GOOGLE_STRAUSS_KEYBOARD
 	select SOC_INTEL_COMMON_BLOCK_HDA_VERB
 	select SOC_INTEL_TCSS_USE_PDC_PMC_USBC_MUX_CONFIGURATION
diff --git a/src/mainboard/google/brya/variants/uldrenite/variant.c b/src/mainboard/google/brya/variants/uldrenite/variant.c
index 8f1a016fde..a7927eb0d3 100644
--- a/src/mainboard/google/brya/variants/uldrenite/variant.c
+++ b/src/mainboard/google/brya/variants/uldrenite/variant.c
@@ -5,9 +5,7 @@
 #include <boardid.h>
 #include <console/console.h>
 #include <delay.h>
-#include <drivers/intel/gma/opregion.h>
 #include <fw_config.h>
-#include <gpio.h>
 #include <sar.h>
 #include <soc/bootblock.h>
 #include <stdlib.h>
@@ -174,21 +172,6 @@ void variant_update_descriptor(void)
 	}
 }
 
-const char *mainboard_vbt_filename(void)
-{
-	/*
-	 * GPP_E13 High -> One RAM Chip
-	 * GPP_E13 Low  -> Two RAM Chips
-	 */
-	if (gpio_get(GPP_E13)) {
-		printk(BIOS_INFO,
-			"x32 memory detected, so use vbt-uldrenite_x32mem.bin\n");
-		return "vbt-uldrenite_x32mem.bin";
-	}
-	printk(BIOS_INFO, "Non-x32 memory detected, so use vbt.bin\n");
-	return "vbt.bin";
-}
-
 void variant_configure_pads(void)
 {
 	const struct pad_config *base_pads;

From 4c446751c63bb6b7e7c2c3f79c3eeb1b91d2c8f9 Mon Sep 17 00:00:00 2001
From: Subrata Banik <subratabanik@google.com>
Date: Fri, 23 May 2025 06:26:16 +0000
Subject: [PATCH 1130/3886] {commonlib, drivers}: Track firmware splash screen
 rendering completion

This commit adds a new timestamp, `TS_FIRMWARE_SPLASH_RENDERED`
(ID 557), to precisely mark the moment the firmware splash screen has
finished displaying.

The timestamp is recorded in `src/drivers/intel/fsp2_0/silicon_init.c`
within the `do_silicon_init` function. It's conditionally added based on
the platform's configuration:

- For platforms using FSP's native BMP rendering (prior to FSP 2.2, with
  `CONFIG(BMP_LOGO)` and without
  `CONFIG(USE_COREBOOT_FOR_BMP_RENDERING)`).
- For platforms where coreboot handles BMP rendering (`CONFIG(BMP_LOGO)`
  and `CONFIG(USE_COREBOOT_FOR_BMP_RENDERING)`).

This enhancement provides better visibility into the boot process and
allows for more accurate performance analysis related to splash screen
display time.

BUG=b:418935715
TEST=Able to build and boot google/fatcat. Verified below details in
`cbmem -t`.

```
557:Firmware splash screen rendering finished    47,193,590 (2,235)
```

Change-Id: Ibef967dbc6e224741438e9708b42486ba03d0104
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87812
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 .../include/commonlib/timestamp_serialized.h  |  2 +
 src/drivers/intel/fsp2_0/silicon_init.c       | 43 +++++++++++--------
 2 files changed, 27 insertions(+), 18 deletions(-)

diff --git a/src/commonlib/include/commonlib/timestamp_serialized.h b/src/commonlib/include/commonlib/timestamp_serialized.h
index 6bcbabc890..2af574c088 100644
--- a/src/commonlib/include/commonlib/timestamp_serialized.h
+++ b/src/commonlib/include/commonlib/timestamp_serialized.h
@@ -87,6 +87,7 @@ enum timestamp_id {
 	TS_TPM_ENABLE_UPDATE_END = 554,
 	TS_ESOL_START = 555,
 	TS_ESOL_END = 556,
+	TS_FIRMWARE_SPLASH_RENDERED = 557,
 
 	/* 900-940 reserved for vendorcode extensions (900-940: AMD) */
 	TS_AGESA_INIT_RESET_START = 900,
@@ -273,6 +274,7 @@ static const struct timestamp_id_to_name {
 	TS_NAME_DEF(TS_TPM_ENABLE_UPDATE_END, 0, "finished TPM enable update"),
 	TS_NAME_DEF(TS_ESOL_START, 0, "started early sign-off life (eSOL) notification"),
 	TS_NAME_DEF(TS_ESOL_END, 0, "finished early sign-off life (eSOL) notification"),
+	TS_NAME_DEF(TS_FIRMWARE_SPLASH_RENDERED, 0, "finished rendering splash screen"),
 
 	/* AMD related timestamps */
 	TS_NAME_DEF(TS_AGESA_INIT_RESET_START, TS_AGESA_INIT_RESET_END, "calling AmdInitReset"),
diff --git a/src/drivers/intel/fsp2_0/silicon_init.c b/src/drivers/intel/fsp2_0/silicon_init.c
index 76636dd7a8..f6ed00be4d 100644
--- a/src/drivers/intel/fsp2_0/silicon_init.c
+++ b/src/drivers/intel/fsp2_0/silicon_init.c
@@ -157,16 +157,16 @@ static void do_silicon_init(struct fsp_header *hdr)
 	fsp_debug_after_silicon_init(status);
 	fsps_return_value_handler(FSP_SILICON_INIT_API, status);
 
-	/*
-	 * Only applies for SoC platforms prior to FSP 2.2 specification:
-	 * If a BMP logo is enabled (`BMP_LOGO`) and the platform is
-	 * configured to skip the FSP for rendering logo bitmap
-	 * (`USE_COREBOOT_FOR_BMP_RENDERING`), then call the coreboot
-	 * native function to handle BMP logo loading and display.
-	 */
-	if (!CONFIG(PLATFORM_USES_FSP2_2) && CONFIG(BMP_LOGO) &&
-			 CONFIG(USE_COREBOOT_FOR_BMP_RENDERING))
-		soc_load_logo_by_coreboot();
+	/* Only applies for SoC platforms prior to FSP 2.2 specification. */
+	if (!CONFIG(PLATFORM_USES_FSP2_2) && CONFIG(BMP_LOGO)) {
+		if (CONFIG(USE_COREBOOT_FOR_BMP_RENDERING))
+			soc_load_logo_by_coreboot();
+		/*
+		 * This applies regardless of whether FSP or coreboot handled
+		 * the rendering.
+		 */
+		timestamp_add_now(TS_FIRMWARE_SPLASH_RENDERED);
+	}
 
 	/* Reinitialize CPUs if FSP-S has done MP Init */
 	if (CONFIG(USE_INTEL_FSP_MP_INIT) && !fsp_is_multi_phase_init_enabled())
@@ -216,14 +216,21 @@ static void do_silicon_init(struct fsp_header *hdr)
 	timestamp_add_now(TS_FSP_MULTI_PHASE_SI_INIT_END);
 	post_code(POSTCODE_FSP_MULTI_PHASE_SI_INIT_EXIT);
 
-	/*
-	 * If a BMP logo is enabled (`BMP_LOGO`) and the platform is
-	 * configured to skip the FSP for rendering logo bitmap
-	 * (`USE_COREBOOT_FOR_BMP_RENDERING`), then call the coreboot
-	 * native function to handle BMP logo loading and display.
-	 */
-	if (CONFIG(BMP_LOGO) && CONFIG(USE_COREBOOT_FOR_BMP_RENDERING))
-		soc_load_logo_by_coreboot();
+	if (CONFIG(BMP_LOGO)) {
+		/*
+		 * If a BMP logo is enabled (`BMP_LOGO`) and the platform is
+		 * configured to skip the FSP for rendering logo bitmap
+		 * (`USE_COREBOOT_FOR_BMP_RENDERING`), then call the coreboot
+		 * native function to handle BMP logo loading and display.
+		 */
+		if (CONFIG(USE_COREBOOT_FOR_BMP_RENDERING))
+			soc_load_logo_by_coreboot();
+		/*
+		 * This applies regardless of whether FSP or coreboot handled
+		 * the rendering.
+		 */
+		timestamp_add_now(TS_FIRMWARE_SPLASH_RENDERED);
+	}
 
 	/* Reinitialize CPUs if FSP-S has done MP Init */
 	if (CONFIG(USE_INTEL_FSP_MP_INIT))

From 1f47b0e018f3b0b14d170e46e08a8aaeec2591f3 Mon Sep 17 00:00:00 2001
From: Felix Singer <felixsinger@posteo.net>
Date: Sun, 25 May 2025 02:54:15 +0000
Subject: [PATCH 1131/3886] 3rdparty/intel-microcode: Update submodule to
 upstream main

Updating from commit id 8a62de41c011:
2025-02-11 11:03:17 -0600 - (microcode-20250211 Release)

to commit id eeb93b7a818b:
2025-05-12 11:40:14 -0600 - (microcode-20250512 Release)

This brings in 1 new commits:
eeb93b7a818b microcode-20250512 Release

Change-Id: I472ec5b516b17be05f10847bd873076f5e9c9805
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87817
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
---
 3rdparty/intel-microcode | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/3rdparty/intel-microcode b/3rdparty/intel-microcode
index 8a62de41c0..eeb93b7a81 160000
--- a/3rdparty/intel-microcode
+++ b/3rdparty/intel-microcode
@@ -1 +1 @@
-Subproject commit 8a62de41c011615d749f8e72bb906dddc72e56a8
+Subproject commit eeb93b7a818bb27cb6b7a2be0454f8a0a75f1bd6

From dc36a725d67205679fa1b0725725641ba41e6e54 Mon Sep 17 00:00:00 2001
From: Felix Singer <felixsinger@posteo.net>
Date: Sun, 25 May 2025 02:55:13 +0000
Subject: [PATCH 1132/3886] 3rdparty/fsp: Update submodule to upstream master

Updating from commit id 86c9111639d3:
2025-03-03 16:14:02 +0800 - (Edge Platforms RPL-P IPU 2025.2 (5402_02) FSP)

to commit id 04728fbd192f:
2025-05-07 15:20:18 +0800 - (Edge Platforms ADL-S IPU 2025.3 (6073_02) FSP)

This brings in 8 new commits:
04728fbd192f Edge Platforms ADL-S IPU 2025.3 (6073_02) FSP
d4e342ac36b9 Edge Platforms ADL-PS IPU 2025.3 (6073_02) FSP
b5b65158d01b Edge Platforms ADL-P IPU 2025.3 (6073_02) FSP
54792daf4384 Edge Platforms RPL-P IPU 2025.3 (6073_03) FSP
ce3297e53c2c IoT ADL-N MR7 (6023_00)
d965fe778e7b IoT ADL-N MR7 (6023_00)
dd1c93bf0af4 ECG BTL-S Hybrid PV (5401_04) FSP
98a458e77195 ECG BTL-S Hybrid PV (5401_04) FSP

Change-Id: Ib1b78ccc26d19749494a131d537ee41aa0ff5544
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87818
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
---
 3rdparty/fsp | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/3rdparty/fsp b/3rdparty/fsp
index 86c9111639..04728fbd19 160000
--- a/3rdparty/fsp
+++ b/3rdparty/fsp
@@ -1 +1 @@
-Subproject commit 86c9111639d357e0f369c14248097b119112a71c
+Subproject commit 04728fbd192fe92abe8df6545a062de3b45dfc42

From 8408bd4863044019644f645dedc326bfab5f43bb Mon Sep 17 00:00:00 2001
From: Subrata Banik <subratabanik@google.com>
Date: Fri, 23 May 2025 08:32:18 +0530
Subject: [PATCH 1133/3886] soc/intel/pantherlake: Add TME configuration

This commit moves the TME configuration into its own static function,
`fill_tme_params`, which is then called from
`fill_fspm_security_params`.

The `TME_KEY_REGENERATION_ON_WARM_BOOT` option is now supported,
allowing a new TME key to be generated on warm reboots.

This feature leverages the `SOC_INTEL_COMMON_BASECODE_RAMTOP`
configuration to determine a memory exclusion range for the new key.

Additionally, disable the `BIOS Guard` UPD as part of security FSP
UPD configuration.

TEST=Able to build and boot google/fatcat. S0ix also works with this
patch.

Change-Id: I1030a25262f1c3c24cf9f4886718689ee2c8155e
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87808
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 .../intel/pantherlake/romstage/fsp_params.c   | 25 +++++++++++++++++--
 1 file changed, 23 insertions(+), 2 deletions(-)

diff --git a/src/soc/intel/pantherlake/romstage/fsp_params.c b/src/soc/intel/pantherlake/romstage/fsp_params.c
index 3f13be2735..44875679ca 100644
--- a/src/soc/intel/pantherlake/romstage/fsp_params.c
+++ b/src/soc/intel/pantherlake/romstage/fsp_params.c
@@ -2,10 +2,12 @@
 
 #include <cpu/intel/common/common.h>
 #include <cpu/x86/msr.h>
+#include <cpu/x86/mtrr.h>
 #include <elog.h>
 #include <fsp/debug.h>
 #include <fsp/fsp_debug_event.h>
 #include <fsp/util.h>
+#include <intelbasecode/ramtop.h>
 #include <intelblocks/cpulib.h>
 #include <soc/iomap.h>
 #include <soc/msr.h>
@@ -106,10 +108,29 @@ static void fill_fspm_cpu_params(FSP_M_CONFIG *m_cfg,
 	m_cfg->SmmRelocationEnable = 0;
 }
 
-static void fill_fspm_security_params(FSP_M_CONFIG *m_cfg,
-				      const struct soc_intel_pantherlake_config *config)
+static void fill_tme_params(FSP_M_CONFIG *m_cfg)
 {
 	m_cfg->TmeEnable = CONFIG(INTEL_TME) && is_tme_supported();
+	if (!m_cfg->TmeEnable || acpi_is_wakeup_s3())
+		return;
+	m_cfg->GenerateNewTmeKey = CONFIG(TME_KEY_REGENERATION_ON_WARM_BOOT);
+	if (m_cfg->GenerateNewTmeKey) {
+		uint32_t ram_top = get_ramtop_addr();
+		if (!ram_top) {
+			printk(BIOS_WARNING, "Invalid exclusion range start address. "
+						"Full memory encryption is enabled.\n");
+			return;
+		}
+		m_cfg->TmeExcludeBase = (ram_top - CACHE_TMP_RAMTOP);
+		m_cfg->TmeExcludeSize = CACHE_TMP_RAMTOP;
+	}
+}
+
+static void fill_fspm_security_params(FSP_M_CONFIG *m_cfg,
+				  const struct soc_intel_pantherlake_config *config)
+{
+	m_cfg->BiosGuard = 0;
+	fill_tme_params(m_cfg);
 }
 
 static void fill_fspm_uart_params(FSP_M_CONFIG *m_cfg,

From 3b975f92c7f4f7d9de3bd4fb1966e2ad779aa2f8 Mon Sep 17 00:00:00 2001
From: Subrata Banik <subratabanik@google.com>
Date: Thu, 22 May 2025 18:18:55 +0530
Subject: [PATCH 1134/3886] soc/intel/pantherlake: Select TME support for the
 SoC

Enables CPU_SUPPORTS_INTEL_TME and TME_KEY_REGENERATION_ON_WARM_BOOT
for Panther Lake, providing hardware memory encryption capabilities.

TEST=Able to build and boot google/francka. Verified TME related
settings inside FSP are now enabled with this patch.

Change-Id: Iedc0d72d00e7e3c5b85916e2de4f020efd5ef024
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87801
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
---
 src/soc/intel/pantherlake/Kconfig | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/src/soc/intel/pantherlake/Kconfig b/src/soc/intel/pantherlake/Kconfig
index 6787642f24..c4b8e011bb 100644
--- a/src/soc/intel/pantherlake/Kconfig
+++ b/src/soc/intel/pantherlake/Kconfig
@@ -9,6 +9,7 @@ config SOC_INTEL_PANTHERLAKE_BASE
 	select CPU_INTEL_COMMON
 	select CPU_INTEL_COMMON_VOLTAGE
 	select CPU_INTEL_FIRMWARE_INTERFACE_TABLE
+	select CPU_SUPPORTS_INTEL_TME
 	select CPU_SUPPORTS_PM_TIMER_EMULATION
 	select DEFAULT_SOFTWARE_CONNECTION_MANAGER if MAINBOARD_HAS_CHROMEOS
 	select DEFAULT_X2APIC_LATE_WORKAROUND
@@ -101,6 +102,7 @@ config SOC_INTEL_PANTHERLAKE_BASE
 	select SOC_QDF_DYNAMIC_READ_PMC
 	select SSE2
 	select SUPPORT_CPU_UCODE_IN_CBFS
+	select TME_KEY_REGENERATION_ON_WARM_BOOT
 	select TSC_MONOTONIC_TIMER
 	select UDELAY_TSC
 	select UDK_202302_BINDING

From 48fbd992232a686356b2a9715f5e6115901146be Mon Sep 17 00:00:00 2001
From: Ian Feng <ian_feng@compal.corp-partner.google.com>
Date: Fri, 23 May 2025 11:01:02 +0800
Subject: [PATCH 1135/3886] mb/google/fatcat/var/francka: Set the default HDA
 GPIO pin to an NC pin

This modification sets the HDA GPIO pin to NC by default.
Different audio configurations can be enabled via fw_config.

BUG=b:417133565
TEST=emerge-fatcat coreboot, HDA sound cards can be detected.

Change-Id: I0090a68d86de1067697d7efbb64c4638476c64ca
Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87810
Reviewed-by: Pranava Y N <pranavayn@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 .../fatcat/variants/francka/fw_config.c       | 31 ++++---------------
 .../google/fatcat/variants/francka/gpio.c     |  8 ++---
 2 files changed, 10 insertions(+), 29 deletions(-)

diff --git a/src/mainboard/google/fatcat/variants/francka/fw_config.c b/src/mainboard/google/fatcat/variants/francka/fw_config.c
index f9049742e1..17901220b5 100644
--- a/src/mainboard/google/fatcat/variants/francka/fw_config.c
+++ b/src/mainboard/google/fatcat/variants/francka/fw_config.c
@@ -12,37 +12,20 @@
 #define GPIO_CONFIGURE_PADS(t) gpio_configure_pads(t, ARRAY_SIZE(t))
 
 static const struct pad_config hda_enable_pads[] = {
-	/* HDA_BIT_CLK */
+	/* GPP_D10:     HDA_BIT_CLK */
 	PAD_CFG_NF(GPP_D10, NONE, DEEP, NF1),
-	/* HDA_SYNC */
+	/* GPP_D11:     HDA_SYNC */
 	PAD_CFG_NF(GPP_D11, NATIVE, DEEP, NF1),
-	/* HDA_SDOUT */
+	/* GPP_D12:     HDA_SDOUT */
 	PAD_CFG_NF(GPP_D12, NATIVE, DEEP, NF1),
-	/* HDA_SDIN0 */
+	/* GPP_D13:     HDA_SDIN0 */
 	PAD_CFG_NF(GPP_D13, NATIVE, DEEP, NF1),
-	/* SOC_DMIC_CLK1 */
+	/* GPP_S06:     SOC_DMIC_CLK1 */
 	PAD_CFG_NF(GPP_S06, NONE, DEEP, NF5),
-	/* SOC_DMIC_DATA1 */
+	/* GPP_S07:     SOC_DMIC_DATA1 */
 	PAD_CFG_NF(GPP_S07, NONE, DEEP, NF5),
 };
 
-static const struct pad_config audio_disable_pads[] = {
-	PAD_NC(GPP_D09, NONE),
-	PAD_NC(GPP_D10, NONE),
-	PAD_NC(GPP_D11, NONE),
-	PAD_NC(GPP_D12, NONE),
-	PAD_NC(GPP_D13, NONE),
-	PAD_NC(GPP_D16, NONE),
-	PAD_NC(GPP_S00, NONE),
-	PAD_NC(GPP_S01, NONE),
-	PAD_NC(GPP_S02, NONE),
-	PAD_NC(GPP_S03, NONE),
-	PAD_NC(GPP_S04, NONE),
-	PAD_NC(GPP_S05, NONE),
-	PAD_NC(GPP_S06, NONE),
-	PAD_NC(GPP_S07, NONE),
-};
-
 /*
  * WWAN: power sequence requires three stages:
  * step 1: 3.3V power, FCP# (Full Card Power), RST#, and PERST# off
@@ -125,8 +108,6 @@ void fw_config_gpio_padbased_override(struct pad_config *padbased_table)
 
 	if (fw_config_probe(FW_CONFIG(AUDIO, AUDIO_ALC256M_CG_HDA))) {
 		GPIO_PADBASED_OVERRIDE(padbased_table, hda_enable_pads);
-	} else {
-		GPIO_PADBASED_OVERRIDE(padbased_table, audio_disable_pads);
 	}
 
 	if (fw_config_probe(FW_CONFIG(WWAN, WWAN_PRESENT))) {
diff --git a/src/mainboard/google/fatcat/variants/francka/gpio.c b/src/mainboard/google/fatcat/variants/francka/gpio.c
index baf272e3e3..7163e3927f 100644
--- a/src/mainboard/google/fatcat/variants/francka/gpio.c
+++ b/src/mainboard/google/fatcat/variants/francka/gpio.c
@@ -172,13 +172,13 @@ static const struct pad_config gpio_table[] = {
 	/* GPP_D09:     PCH_DGPU_HOLD_RST#_R */
 	PAD_NC(GPP_D09, NONE),
 	/* GPP_D10:     HDA_BIT_CLK */
-	PAD_CFG_NF(GPP_D10, NONE, DEEP, NF1),
+	PAD_NC(GPP_D10, NONE),
 	/* GPP_D11:     HDA_SYNC */
-	PAD_CFG_NF(GPP_D11, NONE, DEEP, NF1),
+	PAD_NC(GPP_D11, NONE),
 	/* GPP_D12:     HDA_SDOUT */
-	PAD_CFG_NF(GPP_D12, NONE, DEEP, NF1),
+	PAD_NC(GPP_D12, NONE),
 	/* GPP_D13:     HDA_SDIN0 */
-	PAD_CFG_NF(GPP_D13, NONE, DEEP, NF1),
+	PAD_NC(GPP_D13, NONE),
 	/* GPP_D14:     SOC_HDMI_STRAP */
 	PAD_CFG_GPI(GPP_D14, NONE, DEEP),
 	/* GPP_D15:     Not used */

From d9bd7ce89f0eed73ddbd995d83015ce0c6e2fd37 Mon Sep 17 00:00:00 2001
From: Ian Feng <ian_feng@compal.corp-partner.google.com>
Date: Fri, 23 May 2025 12:09:03 +0800
Subject: [PATCH 1136/3886] mb/google/fatcat/var/francka: Enable audio codec
 ALC721

Enable Realtek ALC721 soundwire codec for francka.

BUG=b:417133565
TEST=Build and boot to OS in francka and SoundWire driver
probe successfully.

Output Devices:
	ID	MaxCha	LastOpen	Name
	13	0	UNK		sof-soundwire: :0,7
	12	0	UNK		sof-soundwire: :0,6
	11	0	UNK		sof-soundwire: :0,5
	8	2	UNK		sof-soundwire: :0,0
	7	2	UNK		sof-soundwire: :0,2
Output Nodes:
Stable Id	ID	Type		MaxCha Name
(8c7788a4)	13:0	HDMI            0 sof-soundwire HDMI/DP,pcm=7
(40acdf7f)	12:0	HDMI            0 sof-soundwire HDMI/DP,pcm=6
(742af104)	11:0	HDMI            0 sof-soundwire HDMI/DP,pcm=5
(db5babbe)	8:0	HEADPHONE       2 Headphone
(5c5b2998)	7:0    INTERNAL_SPEAKER 2*Speaker

Change-Id: I52890fb331f54c48a280a0e3210762a5c66c8bba
Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87811
Reviewed-by: Jayvik Desai <jayvik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
---
 .../google/fatcat/variants/francka/fw_config.c   | 15 +++++++++++++++
 .../google/fatcat/variants/francka/gpio.c        | 16 ++++++++--------
 .../fatcat/variants/francka/overridetree.cb      | 14 ++++++++++++++
 3 files changed, 37 insertions(+), 8 deletions(-)

diff --git a/src/mainboard/google/fatcat/variants/francka/fw_config.c b/src/mainboard/google/fatcat/variants/francka/fw_config.c
index 17901220b5..c722725f0b 100644
--- a/src/mainboard/google/fatcat/variants/francka/fw_config.c
+++ b/src/mainboard/google/fatcat/variants/francka/fw_config.c
@@ -26,6 +26,17 @@ static const struct pad_config hda_enable_pads[] = {
 	PAD_CFG_NF(GPP_S07, NONE, DEEP, NF5),
 };
 
+static const struct pad_config sndw_alc721_enable_pads[] = {
+	/* GPP_S02:     SNDW0_CLK */
+	PAD_CFG_NF(GPP_S02, NONE, DEEP, NF3),
+	/* GPP_S03:     SNDW0_DATA0 */
+	PAD_CFG_NF(GPP_S03, NONE, DEEP, NF3),
+	/* GPP_S06:     SOC_DMIC_CLK1 */
+	PAD_CFG_NF(GPP_S06, NONE, DEEP, NF5),
+	/* GPP_S07:     SOC_DMIC_DATA1 */
+	PAD_CFG_NF(GPP_S07, NONE, DEEP, NF5),
+};
+
 /*
  * WWAN: power sequence requires three stages:
  * step 1: 3.3V power, FCP# (Full Card Power), RST#, and PERST# off
@@ -107,7 +118,11 @@ void fw_config_gpio_padbased_override(struct pad_config *padbased_table)
 	}
 
 	if (fw_config_probe(FW_CONFIG(AUDIO, AUDIO_ALC256M_CG_HDA))) {
+		printk(BIOS_INFO, "Configure GPIOs for HDA ALC256 mode.\n");
 		GPIO_PADBASED_OVERRIDE(padbased_table, hda_enable_pads);
+	} else if (fw_config_probe(FW_CONFIG(AUDIO, AUDIO_ALC721_SNDW))) {
+		printk(BIOS_INFO, "Configure GPIOs for Soundwire ALC721 mode.\n");
+		GPIO_PADBASED_OVERRIDE(padbased_table, sndw_alc721_enable_pads);
 	}
 
 	if (fw_config_probe(FW_CONFIG(WWAN, WWAN_PRESENT))) {
diff --git a/src/mainboard/google/fatcat/variants/francka/gpio.c b/src/mainboard/google/fatcat/variants/francka/gpio.c
index 7163e3927f..880f8afaad 100644
--- a/src/mainboard/google/fatcat/variants/francka/gpio.c
+++ b/src/mainboard/google/fatcat/variants/francka/gpio.c
@@ -344,21 +344,21 @@ static const struct pad_config gpio_table[] = {
 	/* GPP_H22:     SOC_I2C_1_SCL */
 	PAD_CFG_NF(GPP_H22, NONE, DEEP, NF1),
 
-	/* GPP_S00:     Not used */
+	/* GPP_S00:     SNDW_3_SCL */
 	PAD_NC(GPP_S00, NONE),
-	/* GPP_S01:     Not used */
+	/* GPP_S01:     SNDW_3_SDA */
 	PAD_NC(GPP_S01, NONE),
-	/* GPP_S02:     Not used */
+	/* GPP_S02:     SNDW_0_SCL_R / SOC_DMIC_CLK0 */
 	PAD_NC(GPP_S02, NONE),
-	/* GPP_S03:     Not used */
+	/* GPP_S03:     SNDW_0_SDA_R / SOC_DMIC_DATA0 */
 	PAD_NC(GPP_S03, NONE),
-	/* GPP_S04:     Not used */
+	/* GPP_S04:     SNDW_2_SCL */
 	PAD_NC(GPP_S04, NONE),
-	/* GPP_S05:     Not used */
+	/* GPP_S05:     SNDW_2_SDA */
 	PAD_NC(GPP_S05, NONE),
-	/* GPP_S06:     Not used */
+	/* GPP_S06:     SOC_DMIC_CLK1 */
 	PAD_NC(GPP_S06, NONE),
-	/* GPP_S07:     Not used */
+	/* GPP_S07:     SOC_DMIC_DATA1 */
 	PAD_NC(GPP_S07, NONE),
 
 	/* GPP_V00:     PM_BATLOW# */
diff --git a/src/mainboard/google/fatcat/variants/francka/overridetree.cb b/src/mainboard/google/fatcat/variants/francka/overridetree.cb
index d11ff4ab62..983cb91487 100644
--- a/src/mainboard/google/fatcat/variants/francka/overridetree.cb
+++ b/src/mainboard/google/fatcat/variants/francka/overridetree.cb
@@ -283,6 +283,20 @@ chip soc/intel/pantherlake
 					probe AUDIO AUDIO_ALC256M_CG_HDA
 				end
 			end
+			chip drivers/intel/soundwire
+				device generic 0 on
+					chip drivers/soundwire/alc711
+						register "desc" = ""Headset Codec""
+						register "alc711_address.version" = "SOUNDWIRE_VERSION_1_2"
+						register "alc711_address.class" = "MIPI_CLASS_SDCA"
+						register "alc711_address.part_id" = "MIPI_DEV_ID_REALTEK_ALC721"
+						# SoundWire Link 0 ID 0
+						device generic 0.0 on
+							probe AUDIO AUDIO_ALC721_SNDW
+						end
+					end
+				end
+			end
 		end
 		device ref gspi1 on
 			chip drivers/spi/acpi

From d27e8ef4603757cba336ae26ed3738c98a077cc5 Mon Sep 17 00:00:00 2001
From: Felix Singer <felixsinger@posteo.net>
Date: Sun, 25 May 2025 14:02:56 +0200
Subject: [PATCH 1137/3886] update_submodules: Add an empty log line between
 each iteration

For better readability of the log output, add an empty line between each
iteration of the submodules.

Change-Id: I626b609e9833bffde0f7a5eb101877c6cd83a173
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87822
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
---
 util/scripts/update_submodules | 1 +
 1 file changed, 1 insertion(+)

diff --git a/util/scripts/update_submodules b/util/scripts/update_submodules
index 9eeb3836e6..fccc3f6ae2 100755
--- a/util/scripts/update_submodules
+++ b/util/scripts/update_submodules
@@ -96,6 +96,7 @@ main() {
 	fi
 
 	for submodule in "${submodule_dirs[@]}"; do
+		echo ""
 		echo "Checking submodule ${submodule}"
 		if ! cd "$submodule"; then
  			echo "Error: could not cd to $submodule"

From df0221e62ab056b48d5ca0c5d518ee2e7393b968 Mon Sep 17 00:00:00 2001
From: Julius Werner <jwerner@chromium.org>
Date: Wed, 21 May 2025 13:38:58 -0700
Subject: [PATCH 1138/3886] libpayload: Protect against trying to use weak
 symbols in the wrong way

Weak symbols don't work as expected when you try to override them from
within the same static library. Static libraries are just archives of
individual objects, and when the linker tries to resolve a symbol
against it it simply uses the implementation from the first object that
has one, weak or not. It does not search through all remaining objects
to see if there's also a strong implementation.

We've had multiple cases in libpayload where builds were incorrectly
using the default implementation rather than an optimized arch-specific
implementation for years due to this issue. To prevent it from
recurring, this patch adds some postprocessing script to the Makefile
that checks for this situation and makes the build fail if it creeps in
again.

Change-Id: I9fcbc9b873901d126322b12954c349c08300369f
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87777
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
---
 payloads/libpayload/Makefile.mk | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/payloads/libpayload/Makefile.mk b/payloads/libpayload/Makefile.mk
index 079fa325fe..8c6b28767c 100644
--- a/payloads/libpayload/Makefile.mk
+++ b/payloads/libpayload/Makefile.mk
@@ -110,6 +110,14 @@ includes-handler= \
 $(obj)/libpayload.a: $(foreach class,$(libraries),$$($(class)-objs))
 	printf "    AR         $(subst $(CURDIR)/,,$(@))\n"
 	printf "create $@\n$(foreach objc,$(filter-out %.a,$^),addmod $(objc)\n)$(foreach lib,$(filter %.a,$^),addlib $(lib)\n)save\nend\n" | $(AR) -M
+	for func in $$(nm $@ | awk '/ (w|W) / { print $$NF }'); do \
+		if nm --no-weak --defined-only $@ | grep -Eq " $$func$$"; then \
+			printf "\nERROR: Function '$$func' appears as both weak and strong symbol in libpayload.\n"; \
+			printf "       Weak symbol overrides don't work reliably from within the same library.\n\n"; \
+			rm $@; \
+			exit 1; \
+		fi \
+	done
 
 $(obj)/%.a: $$(%-objs)
 	printf "    AR         $(subst $(CURDIR)/,,$(@))\n"

From f59ced2c7c9683c518a521ff61c6f7dc5002b088 Mon Sep 17 00:00:00 2001
From: Frank Wu <frank_wu@compal.corp-partner.google.com>
Date: Fri, 23 May 2025 10:55:37 +0800
Subject: [PATCH 1139/3886] mb/google/fatcat/var/francka: boot up by pressing
 power button in S5

Currently Francka cannot boot up immediately by pressing power button
when its power state is S5.
This patch fixes the power on process for this scenario.

BUG=b:419406610
BRANCH=none
TEST=Francka boots up immediately by pressing power button in S5.

Change-Id: I52fba7f58faa890955cd07728a6790520df29321
Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87807
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Reviewed-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
---
 src/mainboard/google/fatcat/variants/francka/gpio.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/mainboard/google/fatcat/variants/francka/gpio.c b/src/mainboard/google/fatcat/variants/francka/gpio.c
index 880f8afaad..0c8ab35d0f 100644
--- a/src/mainboard/google/fatcat/variants/francka/gpio.c
+++ b/src/mainboard/google/fatcat/variants/francka/gpio.c
@@ -272,8 +272,8 @@ static const struct pad_config gpio_table[] = {
 	PAD_NC(GPP_F07, NONE),
 	/* GPP_F08:     Not used */
 	PAD_NC(GPP_F08, NONE),
-	/* GPP_F09:     SX_EXIT_HOLDOFF# */
-	PAD_CFG_NF(GPP_F09, NONE, DEEP, NF2),
+	/* GPP_F09:     Not used */
+	PAD_NC(GPP_F09, NONE),
 	/* GPP_F10:     Not used */
 	PAD_NC(GPP_F10, NONE),
 	/* GPP_F11:     SOC_THC_1_CLK */

From c4fe5e2483706544fa964d6a21db4c7897033e59 Mon Sep 17 00:00:00 2001
From: Vince Liu <vince-wl.liu@mediatek.corp-partner.google.com>
Date: Mon, 17 Feb 2025 15:07:10 +0800
Subject: [PATCH 1140/3886] mb/google/skywalker: Pass reset GPIO parameter to
 BL31

Pass the reset GPIO parameter to BL31 to support SoC reset.

BUG=b:395795640
BRANCH=none
TEST=run reboot command in depthcharge

Signed-off-by: Vince Liu <vince-wl.liu@mediatek.corp-partner.google.com>
Change-Id: I87063d58d04ea6437195a59abab9c54f2da7eac0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87814
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
---
 src/mainboard/google/skywalker/mainboard.c | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/src/mainboard/google/skywalker/mainboard.c b/src/mainboard/google/skywalker/mainboard.c
index d786f473d0..686fd55e2e 100644
--- a/src/mainboard/google/skywalker/mainboard.c
+++ b/src/mainboard/google/skywalker/mainboard.c
@@ -1,15 +1,21 @@
 /* SPDX-License-Identifier: GPL-2.0-only OR MIT */
 
 #include <device/device.h>
+#include <soc/bl31.h>
 #include <soc/dpm_v2.h>
 #include <soc/spm_common.h>
 #include <soc/usb.h>
 
+#include "gpio.h"
+
 static void mainboard_init(struct device *dev)
 {
 	dpm_init();
 	setup_usb_host();
 	spm_init();
+
+	if (CONFIG(ARM64_USE_ARM_TRUSTED_FIRMWARE))
+		register_reset_to_bl31(GPIO_AP_EC_WARM_RST_REQ.id, true);
 }
 
 static void mainboard_enable(struct device *dev)

From 99b6ff25d4989e3b58606d2ae328ee4679bfb725 Mon Sep 17 00:00:00 2001
From: Vince Liu <vince-wl.liu@mediatek.corp-partner.google.com>
Date: Thu, 9 Jan 2025 13:38:31 +0800
Subject: [PATCH 1141/3886] soc/mediatek/mt8189: Add MTK FSP loader in ramstage

To support the MTK firmware support package (FSP), reserve a 2MB region
in DRAM for loading `mtk_fsp_ramstage.elf` during ramstage.

BUG=b:379008996
BRANCH=none
TEST=build passed

Signed-off-by: Vince Liu <vince-wl.liu@mediatek.corp-partner.google.com>
Change-Id: If153d9746bea8c7faa8f9787029b44192c18899d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87813
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
---
 src/soc/mediatek/mt8189/Makefile.mk              | 9 +++++++++
 src/soc/mediatek/mt8189/include/soc/memlayout.ld | 1 +
 2 files changed, 10 insertions(+)

diff --git a/src/soc/mediatek/mt8189/Makefile.mk b/src/soc/mediatek/mt8189/Makefile.mk
index b8ff8bff29..7f9b86834b 100644
--- a/src/soc/mediatek/mt8189/Makefile.mk
+++ b/src/soc/mediatek/mt8189/Makefile.mk
@@ -40,6 +40,7 @@ ramstage-y += ../common/mmu_operations.c ../common/mmu_cmops.c
 ramstage-y += ../common/mt6315.c mt6315.c
 ramstage-y += ../common/mt6359p.c mt6359p.c
 ramstage-y += ../common/mtcmos.c mtcmos.c
+ramstage-y += ../common/mtk_fsp.c
 ramstage-y += ../common/pmif.c ../common/pmif_clk.c ../common/pmif_init.c pmif_clk.c
 ramstage-y += ../common/pmif_spi.c pmif_spi.c
 ramstage-y += ../common/pmif_spmi.c pmif_spmi.c
@@ -81,3 +82,11 @@ $(objcbfs)/bootblock.bin: $(objcbfs)/bootblock.raw.bin
 	./util/mediatek/gen-bl-img.py mt8189 sf $< $@
 
 endif
+
+FSP_CBFS := $(CONFIG_CBFS_PREFIX)/mtk_fsp_ramstage
+$(FSP_CBFS)-file := $(MT8189_BLOB_DIR)/mtk_fsp_ramstage.elf
+$(FSP_CBFS)-type := stage
+$(FSP_CBFS)-compression := $(CBFS_COMPRESS_FLAG)
+ifneq ($(wildcard $($(FSP_CBFS)-file)),)
+	cbfs-files-y += $(FSP_CBFS)
+endif
diff --git a/src/soc/mediatek/mt8189/include/soc/memlayout.ld b/src/soc/mediatek/mt8189/include/soc/memlayout.ld
index 66705329d2..7e77a816ed 100644
--- a/src/soc/mediatek/mt8189/include/soc/memlayout.ld
+++ b/src/soc/mediatek/mt8189/include/soc/memlayout.ld
@@ -65,6 +65,7 @@ SECTIONS
 	DRAM_DMA(0x40000000, 1M)
 	POSTRAM_CBFS_CACHE(0x40100000, 2M)
 	RAMSTAGE(0x40300000, 2M)
+	FSP_RAMSTAGE_INIT_CODE(0x40500000, 2M)
 
 	BL31(0x54600000, 0x60000)
 }

From 6602a4462ba93f6ca019a763325b2ee5fbf04fd2 Mon Sep 17 00:00:00 2001
From: Nick Vaccaro <nvaccaro@google.com>
Date: Mon, 19 May 2025 14:03:51 -0700
Subject: [PATCH 1142/3886] mb/google/ocelot/var/ocelot: Enable hda device for
 AUDIO_ALC721_SNDW.

BUG=b:412736286
BRANCH=None
TEST=`emerge-ocelot coreboot` and verify it compiles without error.

Change-Id: I0c3d2c30af8839540a7c6d53dc11c83782b92d25
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87751
Reviewed-by: Pranava Y N <pranavayn@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 .../ocelot/variants/ocelot/overridetree.cb      | 17 ++++++++++++++++-
 1 file changed, 16 insertions(+), 1 deletion(-)

diff --git a/src/mainboard/google/ocelot/variants/ocelot/overridetree.cb b/src/mainboard/google/ocelot/variants/ocelot/overridetree.cb
index c4341c2a27..f80ac8973a 100644
--- a/src/mainboard/google/ocelot/variants/ocelot/overridetree.cb
+++ b/src/mainboard/google/ocelot/variants/ocelot/overridetree.cb
@@ -618,6 +618,21 @@ chip soc/intel/pantherlake
 		end
 
 		device ref smbus on end
-		device ref hda off end
+		device ref hda on
+			chip drivers/intel/soundwire
+				device generic 0 on
+					chip drivers/soundwire/alc711
+						register "desc" = ""Headset Codec""
+						register "alc711_address.version" = "SOUNDWIRE_VERSION_1_2"
+						register "alc711_address.class" = "MIPI_CLASS_SDCA"
+						register "alc711_address.part_id" = "MIPI_DEV_ID_REALTEK_ALC721"
+						# SoundWire Link 3 ID 1
+						device generic 3.1 on
+							probe AUDIO AUDIO_ALC721_SNDW
+						end
+					end
+				end
+			end
+		end
 	end
 end

From c5488c0d6d9841a4a7dd308b1477421a2e9e36ef Mon Sep 17 00:00:00 2001
From: Nick Vaccaro <nvaccaro@google.com>
Date: Mon, 19 May 2025 13:58:34 -0700
Subject: [PATCH 1143/3886] mb/google/ocelot/var/ocelot: update gpios

Update gpio configuration for GPP_A08, GPP_E17, and GPP_F18 to
match ocelot schematic.

Change GPP_H16 (WWAN_PWR_EN) to GPP_E01 (EN_WWAN_PWR) in fw_config.c.

Change GPP_V06 and GPP_V11 to "No Connect" as they are test points.

Change trace names from "SNDW3_" to "SDW3_" to match names on ocelot
schematic.

BUG=b:412736286
BRANCH=None
TEST=`emerge-ocelot coreboot` and verify it compiles without error.

Change-Id: I8996dc1b2b0f85490d55a86dc2ca6a90c1604638
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87750
Reviewed-by: Pranava Y N <pranavayn@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 .../google/ocelot/variants/ocelot/fw_config.c |  8 ++---
 .../google/ocelot/variants/ocelot/gpio.c      | 32 +++++++------------
 2 files changed, 16 insertions(+), 24 deletions(-)

diff --git a/src/mainboard/google/ocelot/variants/ocelot/fw_config.c b/src/mainboard/google/ocelot/variants/ocelot/fw_config.c
index 511ec7e421..954ec712e0 100644
--- a/src/mainboard/google/ocelot/variants/ocelot/fw_config.c
+++ b/src/mainboard/google/ocelot/variants/ocelot/fw_config.c
@@ -138,8 +138,8 @@ static const struct pad_config x1slot_disable_pads[] = {
  * at much later time and time between RST# and PERSET# is guaranteed.
  */
 static const struct pad_config pre_mem_wwan_pwr_seq1_pads[] = {
-	/* GPP_H16:     WWAN_PWREN */
-	PAD_CFG_GPO(GPP_H16, 1, PLTRST),
+	/* GPP_E01:     EN_WWAN_PWR */
+	PAD_CFG_GPO(GPP_E01, 1, PLTRST),
 	/* GPP_A09:  M.2_WWAN_FCP_OFF_N */
 	PAD_CFG_GPO(GPP_A09, 0, PLTRST),
 	/* GPP_B20:     M.2_WWAN_RST_N */
@@ -169,8 +169,8 @@ static const struct pad_config wwan_disable_pads[] = {
 	PAD_NC(GPP_D03, NONE),
 	/* GPP_B20:     M.2_WWAN_RST_N */
 	PAD_NC(GPP_B20, NONE),
-	/* GPP_H16:     WWAN_PWREN */
-	PAD_NC(GPP_H16, NONE),
+	/* GPP_E01:     EN_WWAN_PWR */
+	PAD_NC(GPP_E01, NONE),
 	/* GPP_A10:     M.2_WWAN_DISABLE_N */
 	PAD_NC(GPP_A10, NONE),
 	/* GPP_E02:     WWAN_WAKE_GPIO_N */
diff --git a/src/mainboard/google/ocelot/variants/ocelot/gpio.c b/src/mainboard/google/ocelot/variants/ocelot/gpio.c
index c22de38f2f..43e5232e21 100644
--- a/src/mainboard/google/ocelot/variants/ocelot/gpio.c
+++ b/src/mainboard/google/ocelot/variants/ocelot/gpio.c
@@ -22,7 +22,7 @@ static const struct pad_config gpio_table[] = {
 	/* GPP_A06:     ESPI_SOC_RST_L # */
 	PAD_CFG_NF(GPP_A06, NONE, DEEP, NF1),
 	/* GPP_A08:     SSD_PERST_L # */
-	PAD_CFG_GPO(GPP_A08, 1, PLTRST),
+	PAD_CFG_GPO(GPP_A08, 0, PLTRST),
 	/* GPP_A09:     WWAN_EN */
 	PAD_CFG_GPO(GPP_A09, 0, PLTRST),
 	/* GPP_A10:     WWAN_RF_DISABLE_ODL */
@@ -198,6 +198,8 @@ static const struct pad_config gpio_table[] = {
 	PAD_NC(GPP_E15, NONE),
 	/* GPP_E16:     NC */
 	PAD_NC(GPP_E16, NONE),
+	/* GPP_E17:     SPI_SOC_CS_FP_R_L */
+	PAD_CFG_NF(GPP_E17, NONE, DEEP, NF5),
 	/* GPP_E18:     SOC_TCHPAD_INT_ODL */
 	PAD_CFG_NF(GPP_E18, NONE, DEEP, NF3),
 	/* GPP_E19:     FP_SOC_INT_L */
@@ -245,9 +247,8 @@ static const struct pad_config gpio_table[] = {
 	PAD_CFG_NF(GPP_F16, NONE, DEEP, NF3),
 	/* GPP_F17:     SPI_THCSCR_CS_L */
 	PAD_CFG_NF(GPP_F17, NONE, DEEP, NF3),
-	/* GPP_F18:     TCH_PAD_INT_N */
-	/* NOTE: require rework to switch from GPP_A13 to GPP_F18 */
-	PAD_CFG_GPI_APIC(GPP_F18, NONE, PLTRST, LEVEL, INVERT),
+	/* GPP_F18:     TCHSCR_INT_ODL */
+	PAD_CFG_NF(GPP_F19, NONE, DEEP, NF3),
 	/* GPP_F19:     GPP_F19_STRAP */
 	PAD_NC(GPP_F19, NONE),
 	/* GPP_F20:     EC_SOC_REC_SWITCH_ODL */
@@ -302,11 +303,11 @@ static const struct pad_config gpio_table[] = {
 
 	/* GPP_S00:     SDW3_CLK_I2S1_TXD */
 	PAD_CFG_NF(GPP_S00, NONE, DEEP, NF1),
-	/* GPP_S01:     SNDW3_DAT0 */
+	/* GPP_S01:     SDW3_DAT0 */
 	PAD_CFG_NF(GPP_S01, NONE, DEEP, NF1),
-	/* GPP_S02:     SNDW3_DAT1_I2S1_SCLK */
+	/* GPP_S02:     SDW3_DAT1_I2S1_SCLK */
 	PAD_CFG_NF(GPP_S02, NONE, DEEP, NF1),
-	/* GPP_S03:     SNDW3_DAT2_I2S1_SFRM */
+	/* GPP_S03:     SDW3_DAT2_I2S1_SFRM */
 	PAD_CFG_NF(GPP_S03, NONE, DEEP, NF1),
 	/* GPP_S04:     DMIC_CLK0_R */
 	PAD_CFG_NF(GPP_S04, NONE, DEEP, NF5),
@@ -322,7 +323,6 @@ static const struct pad_config gpio_table[] = {
 	/* GPP_V01:     EC_AC_PRESENT_OD */
 	PAD_CFG_NF(GPP_V01, NONE, DEEP, NF1),
 	/* GPP_V02:     EC_SOC_WAKE_ODL */
-	/* FIXME */
 	PAD_CFG_GPI_IRQ_WAKE(GPP_V02, NONE, PLTRST, LEVEL, INVERT),
 	/* GPP_V03:     EC_SOC_PWR_BTN_ODL */
 	PAD_CFG_NF(GPP_V03, NONE, DEEP, NF1),
@@ -331,7 +331,7 @@ static const struct pad_config gpio_table[] = {
 	/* GPP_V05:     SLP_S4_L */
 	PAD_CFG_NF(GPP_V05, NONE, DEEP, NF1),
 	/* GPP_V06:     TP_SLP_A_L */
-	PAD_CFG_NF(GPP_V06, NONE, DEEP, NF1),
+	PAD_NC(GPP_V06, NONE),
 	/* GPP_V07:     SOC_WLAN_SUSCLK */
 	PAD_CFG_NF(GPP_V07, NONE, DEEP, NF1),
 	/* GPP_V08:     NC */
@@ -341,7 +341,7 @@ static const struct pad_config gpio_table[] = {
 	/* GPP_V10:     NC */
 	PAD_NC(GPP_V10, NONE),
 	/* GPP_V11:     TP_SLP_LAN_L */
-	PAD_CFG_NF(GPP_V11, NONE, DEEP, NF1),
+	PAD_NC(GPP_V11, NONE),
 	/* GPP_V12:     PCH_WAKE_L */
 	PAD_CFG_NF(GPP_V12, NONE, DEEP, NF1),
 	/* GPP_V16:     EN_VCCST */
@@ -377,20 +377,12 @@ static const struct pad_config early_gpio_table[] = {
 	PAD_CFG_NF(GPP_H21, NONE, DEEP, NF1),
 	/* GPP_H22:     SOC_I2C_GSC_SCL */
 	PAD_CFG_NF(GPP_H22, NONE, DEEP, NF1),
-
-	/* GPP_V01:     EC_AC_PRESENT_OD */
-	PAD_CFG_NF(GPP_V01, NONE, DEEP, NF1),
-	/* GPP_V02:     EC_SOC_WAKE_ODL */
-	/* FIXME */
-	PAD_CFG_GPI_IRQ_WAKE(GPP_V02, NONE, PLTRST, LEVEL, INVERT),
-	/* GPP_V03:     EC_SOC_PWR_BTN_ODL */
-	PAD_CFG_NF(GPP_V03, NONE, DEEP, NF1),
 };
 
 /* Pad configuration in romstage */
 static const struct pad_config romstage_gpio_table[] = {
-	/* GPP_A08:     X1_PCIE_SLOT_PWR_EN */
-	PAD_CFG_GPO(GPP_A08, 0, PLTRST),
+	/* GPP_A08:     SSD_PERST_L */
+	PAD_CFG_GPO(GPP_A08, 1, PLTRST),
 };
 
 const struct pad_config *variant_gpio_table(size_t *num)

From 2117ed850f320c85ee87e6f1b195eafa4dc6fcf8 Mon Sep 17 00:00:00 2001
From: Avi Uday <aviuday@google.com>
Date: Fri, 23 May 2025 12:43:55 +0530
Subject: [PATCH 1144/3886] mb/google/ocelot/var/ocelot: fix storage configs
 for ocelot

Ocelot does not support GEN5 NVME Storage. However since ocelot code
was forked from fatcat, these configs exist in coreboot.

Furthermore, the GEN4 NVME GPIOs have changed for ocelot -
1. GPP_B10 to GPP_H18 - GEN4_SSD_PWREN renamed to EN_PP3300_SSD
2. GPP_B09 to GPP_A08 - M2_GEN4_SSD_RESET_N renamed to SSD_PERST_L

BUG=b:419731962

Change-Id: I005d1188138ac7b4bbffa1437bba9aea39aff117
Signed-off-by: Avi Uday <aviuday@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87804
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Pranava Y N <pranavayn@google.com>
---
 .../google/ocelot/variants/ocelot/fw_config.c | 31 ++++---------------
 .../ocelot/variants/ocelot/overridetree.cb    |  7 ++---
 2 files changed, 9 insertions(+), 29 deletions(-)

diff --git a/src/mainboard/google/ocelot/variants/ocelot/fw_config.c b/src/mainboard/google/ocelot/variants/ocelot/fw_config.c
index 954ec712e0..affde9dce4 100644
--- a/src/mainboard/google/ocelot/variants/ocelot/fw_config.c
+++ b/src/mainboard/google/ocelot/variants/ocelot/fw_config.c
@@ -179,15 +179,15 @@ static const struct pad_config wwan_disable_pads[] = {
 
 /* Gen4 NVME: at the top M.2 slot */
 static const struct pad_config pre_mem_gen4_ssd_pwr_pads[] = {
-	/* GPP_B10:     GEN4_SSD_PWREN */
-	PAD_CFG_GPO(GPP_B10, 0, PLTRST),
+	/* GPP_H18:     EN_PP3300_SSD */
+	PAD_CFG_GPO(GPP_H18, 0, PLTRST),
 };
 
 static const struct pad_config gen4_ssd_pads[] = {
-	/* GPP_B10:     GEN4_SSD_PWREN */
-	PAD_CFG_GPO(GPP_B10, 1, PLTRST),
-	/* GPP_B09:     M2_GEN4_SSD_RESET_N */
-	PAD_CFG_GPO(GPP_B09, 1, PLTRST),
+	/* GPP_B10:     EN_PP3300_SSD */
+	PAD_CFG_GPO(GPP_H18, 1, PLTRST),
+	/* GPP_B09:     SSD_PERST_L */
+	PAD_CFG_GPO(GPP_A08, 1, PLTRST),
 };
 
 static const struct pad_config ufs_enable_pads[] = {
@@ -195,19 +195,6 @@ static const struct pad_config ufs_enable_pads[] = {
 	PAD_CFG_NF(GPP_D21, NONE, DEEP, NF1),
 };
 
-/* Gen5 NVME: at the bottom M.2 slot */
-static const struct pad_config pre_mem_gen5_ssd_pwr_pads[] = {
-	/* GPP_B16:     GEN5_SSD_PWREN */
-	PAD_CFG_GPO(GPP_B16, 0, PLTRST),
-};
-
-static const struct pad_config gen5_ssd_pads[] = {
-	/* GPP_B16:     GEN5_SSD_PWREN */
-	PAD_CFG_GPO(GPP_B16, 1, PLTRST),
-	/* GPP_E03:     M2_GEN5_SSD_RESET_N */
-	PAD_CFG_GPO(GPP_E03, 1, PLTRST),
-};
-
 static const struct pad_config peg_x4slot_wake_disable_pads[] = {
 	/* GPP_D24:     PEG_SLOT_WAKE_N */
 	PAD_NC(GPP_D24, NONE),
@@ -459,11 +446,8 @@ void fw_config_configure_pre_mem_gpio(void)
 
 	if (fw_config_probe(FW_CONFIG(STORAGE, STORAGE_NVME_GEN4))) {
 		GPIO_CONFIGURE_PADS(pre_mem_gen4_ssd_pwr_pads);
-	} else if (fw_config_probe(FW_CONFIG(STORAGE, STORAGE_NVME_GEN5))) {
-		GPIO_CONFIGURE_PADS(pre_mem_gen5_ssd_pwr_pads);
 	} else if (fw_config_probe(FW_CONFIG(STORAGE, STORAGE_UNKNOWN))) {
 		GPIO_CONFIGURE_PADS(pre_mem_gen4_ssd_pwr_pads);
-		GPIO_CONFIGURE_PADS(pre_mem_gen5_ssd_pwr_pads);
 	}
 
 	/*
@@ -495,13 +479,10 @@ void fw_config_gpio_padbased_override(struct pad_config *padbased_table)
 
 	if (fw_config_probe(FW_CONFIG(STORAGE, STORAGE_NVME_GEN4))) {
 		GPIO_PADBASED_OVERRIDE(padbased_table, gen4_ssd_pads);
-	} else if (fw_config_probe(FW_CONFIG(STORAGE, STORAGE_NVME_GEN5))) {
-		GPIO_PADBASED_OVERRIDE(padbased_table, gen5_ssd_pads);
 	} else if (fw_config_probe(FW_CONFIG(STORAGE, STORAGE_UFS))) {
 		GPIO_PADBASED_OVERRIDE(padbased_table, ufs_enable_pads);
 	} else if (fw_config_probe(FW_CONFIG(STORAGE, STORAGE_UNKNOWN))) {
 		GPIO_PADBASED_OVERRIDE(padbased_table, gen4_ssd_pads);
-		GPIO_PADBASED_OVERRIDE(padbased_table, gen5_ssd_pads);
 		GPIO_PADBASED_OVERRIDE(padbased_table, ufs_enable_pads);
 	}
 
diff --git a/src/mainboard/google/ocelot/variants/ocelot/overridetree.cb b/src/mainboard/google/ocelot/variants/ocelot/overridetree.cb
index f80ac8973a..e692c080c0 100644
--- a/src/mainboard/google/ocelot/variants/ocelot/overridetree.cb
+++ b/src/mainboard/google/ocelot/variants/ocelot/overridetree.cb
@@ -34,8 +34,7 @@ fw_config
 	field STORAGE 13 14
 		option STORAGE_UNKNOWN		0
 		option STORAGE_NVME_GEN4	1
-		option STORAGE_NVME_GEN5	2
-		option STORAGE_UFS		3
+		option STORAGE_UFS		2
 	end
 	field FP 15
 		option FP_ABSENT		0
@@ -546,8 +545,8 @@ chip soc/intel/pantherlake
 			}"
 			chip soc/intel/common/block/pcie/rtd3
 				register "is_storage" = "true"
-				register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B10)"
-				register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B09)"
+				register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_H18)"
+				register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A08)"
 				register "srcclk_pin" = "6"
 				device generic 0 on end
 			end

From ddce240d3498dbcfc2f07847a3c36e6601456bd0 Mon Sep 17 00:00:00 2001
From: Angel Pons <th3fanbus@gmail.com>
Date: Sun, 25 May 2025 09:37:17 +0200
Subject: [PATCH 1145/3886] cpu/intel/haswell: Clean up Makefile

Group entries by stage and sort groups by stage execution order.

Change-Id: I6e2a53d6555700b48fd3aececdfdb8983554a75a
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87826
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
---
 src/cpu/intel/haswell/Makefile.mk | 15 +++++++--------
 1 file changed, 7 insertions(+), 8 deletions(-)

diff --git a/src/cpu/intel/haswell/Makefile.mk b/src/cpu/intel/haswell/Makefile.mk
index 7323ed97f0..8b8e98600a 100644
--- a/src/cpu/intel/haswell/Makefile.mk
+++ b/src/cpu/intel/haswell/Makefile.mk
@@ -1,22 +1,21 @@
 ## SPDX-License-Identifier: GPL-2.0-only
 
-ramstage-y += haswell_init.c
+bootblock-y += bootblock.c
+bootblock-y += ../car/non-evict/cache_as_ram.S
+bootblock-y += ../car/bootblock.c
+bootblock-y += ../../x86/early_reset.S
 
 romstage-y += romstage.c
 romstage-y += ../car/romstage.c
 
+postcar-y += ../car/non-evict/exit_car.S
+
 ramstage-y += acpi.c
+ramstage-y += haswell_init.c
 ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smmrelocate.c
 
 smm-y += finalize.c
 
-bootblock-y += ../car/non-evict/cache_as_ram.S
-bootblock-y += ../car/bootblock.c
-bootblock-y += ../../x86/early_reset.S
-bootblock-y += bootblock.c
-
-postcar-y += ../car/non-evict/exit_car.S
-
 subdirs-y += ../microcode
 subdirs-y += ../turbo
 

From ae68ef36848626e1d128359d12c31a66bbdb1b98 Mon Sep 17 00:00:00 2001
From: Angel Pons <th3fanbus@gmail.com>
Date: Sun, 25 May 2025 09:55:18 +0200
Subject: [PATCH 1146/3886] cpu/intel/haswell: Export PCODE mailbox functions

The PCODE mailbox is primarily used by CPU code in ramstage. However,
it is also used as part of enabling DDR 2x refresh rate, which is now
implemented in coreboot as part of NRI (native RAM init).

The PCODE mailbox functions in CPU code were not exported at the time
NRI was being developed, so I chose to temporarily copy the functions
into NRI code to make it easier to rebase NRI patches since it avoids
potential merge conflicts. After a few years of rebasing patches, NRI
finally got submitted, so there's no reason to keep duplicate code in
the tree anymore.

Put the relevant PCODE functions into a new file, which gets compiled
for both ramstage (CPU init) and romstage (NRI). The BCLK calibration
function is only used in ramstage so there's no need to move it.

Change-Id: I340625fabc072139b8def254f1ce6b19f360adcd
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87827
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
---
 src/cpu/intel/haswell/Makefile.mk     |  2 +
 src/cpu/intel/haswell/haswell.h       |  5 +++
 src/cpu/intel/haswell/haswell_init.c  | 64 +++------------------------
 src/cpu/intel/haswell/pcode_mailbox.c | 63 ++++++++++++++++++++++++++
 4 files changed, 75 insertions(+), 59 deletions(-)
 create mode 100644 src/cpu/intel/haswell/pcode_mailbox.c

diff --git a/src/cpu/intel/haswell/Makefile.mk b/src/cpu/intel/haswell/Makefile.mk
index 8b8e98600a..41ca9c9d98 100644
--- a/src/cpu/intel/haswell/Makefile.mk
+++ b/src/cpu/intel/haswell/Makefile.mk
@@ -5,6 +5,7 @@ bootblock-y += ../car/non-evict/cache_as_ram.S
 bootblock-y += ../car/bootblock.c
 bootblock-y += ../../x86/early_reset.S
 
+romstage-y += pcode_mailbox.c
 romstage-y += romstage.c
 romstage-y += ../car/romstage.c
 
@@ -12,6 +13,7 @@ postcar-y += ../car/non-evict/exit_car.S
 
 ramstage-y += acpi.c
 ramstage-y += haswell_init.c
+ramstage-y += pcode_mailbox.c
 ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smmrelocate.c
 
 smm-y += finalize.c
diff --git a/src/cpu/intel/haswell/haswell.h b/src/cpu/intel/haswell/haswell.h
index f63b0ef4b3..f42199de0a 100644
--- a/src/cpu/intel/haswell/haswell.h
+++ b/src/cpu/intel/haswell/haswell.h
@@ -171,6 +171,11 @@ int cpu_config_tdp_levels(void);
 
 void set_max_freq(void);
 
+/* pcode_mailbox.c */
+int pcode_ready(void);
+u32 pcode_mailbox_read(u32 command);
+int pcode_mailbox_write(u32 command, u32 data);
+
 /* CPU identification */
 static inline u32 cpu_family_model(void)
 {
diff --git a/src/cpu/intel/haswell/haswell_init.c b/src/cpu/intel/haswell/haswell_init.c
index 86dcbea177..8232453a57 100644
--- a/src/cpu/intel/haswell/haswell_init.c
+++ b/src/cpu/intel/haswell/haswell_init.c
@@ -77,25 +77,11 @@ static const u8 power_limit_time_msr_to_sec[] = {
 	[0x11] = 128,
 };
 
-/* The core 100MHz BCLK is disabled in deeper c-states. One needs to calibrate
+/*
+ * The core 100MHz BCLK is disabled in deeper c-states. One needs to calibrate
  * the 100MHz BCLK against the 24MHz BCLK to restore the clocks properly
- * when a core is woken up. */
-static int pcode_ready(void)
-{
-	int wait_count;
-	const int delay_step = 10;
-
-	wait_count = 0;
-	do {
-		if (!(mchbar_read32(BIOS_MAILBOX_INTERFACE) & MAILBOX_RUN_BUSY))
-			return 0;
-		wait_count += delay_step;
-		udelay(delay_step);
-	} while (wait_count < 1000);
-
-	return -1;
-}
-
+ * when a core is woken up.
+ */
 static void calibrate_24mhz_bclk(void)
 {
 	int err_code;
@@ -117,8 +103,7 @@ static void calibrate_24mhz_bclk(void)
 
 	err_code = mchbar_read32(BIOS_MAILBOX_INTERFACE) & 0xff;
 
-	printk(BIOS_DEBUG, "PCODE: 24MHz BCLK calibration response: %d\n",
-	       err_code);
+	printk(BIOS_DEBUG, "PCODE: 24MHz BCLK calibration response: %d\n", err_code);
 
 	/* Read the calibrated value. */
 	mchbar_write32(BIOS_MAILBOX_INTERFACE,
@@ -133,45 +118,6 @@ static void calibrate_24mhz_bclk(void)
 	       mchbar_read32(BIOS_MAILBOX_DATA));
 }
 
-static u32 pcode_mailbox_read(u32 command)
-{
-	if (pcode_ready() < 0) {
-		printk(BIOS_ERR, "PCODE: mailbox timeout on wait ready.\n");
-		return 0;
-	}
-
-	/* Send command and start transaction */
-	mchbar_write32(BIOS_MAILBOX_INTERFACE, command | MAILBOX_RUN_BUSY);
-
-	if (pcode_ready() < 0) {
-		printk(BIOS_ERR, "PCODE: mailbox timeout on completion.\n");
-		return 0;
-	}
-
-	/* Read mailbox */
-	return mchbar_read32(BIOS_MAILBOX_DATA);
-}
-
-static int pcode_mailbox_write(u32 command, u32 data)
-{
-	if (pcode_ready() < 0) {
-		printk(BIOS_ERR, "PCODE: mailbox timeout on wait ready.\n");
-		return -1;
-	}
-
-	mchbar_write32(BIOS_MAILBOX_DATA, data);
-
-	/* Send command and start transaction */
-	mchbar_write32(BIOS_MAILBOX_INTERFACE, command | MAILBOX_RUN_BUSY);
-
-	if (pcode_ready() < 0) {
-		printk(BIOS_ERR, "PCODE: mailbox timeout on completion.\n");
-		return -1;
-	}
-
-	return 0;
-}
-
 static struct device *cpu_cluster;
 
 static void initialize_vr_config(void)
diff --git a/src/cpu/intel/haswell/pcode_mailbox.c b/src/cpu/intel/haswell/pcode_mailbox.c
new file mode 100644
index 0000000000..7d866466e7
--- /dev/null
+++ b/src/cpu/intel/haswell/pcode_mailbox.c
@@ -0,0 +1,63 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <console/console.h>
+#include <delay.h>
+#include <northbridge/intel/haswell/haswell.h>
+#include <types.h>
+
+#include "haswell.h"
+
+int pcode_ready(void)
+{
+	int wait_count;
+	const int delay_step = 10;
+
+	wait_count = 0;
+	do {
+		if (!(mchbar_read32(BIOS_MAILBOX_INTERFACE) & MAILBOX_RUN_BUSY))
+			return 0;
+		wait_count += delay_step;
+		udelay(delay_step);
+	} while (wait_count < 1000);
+
+	return -1;
+}
+
+u32 pcode_mailbox_read(u32 command)
+{
+	if (pcode_ready() < 0) {
+		printk(BIOS_ERR, "PCODE: mailbox timeout on wait ready.\n");
+		return 0;
+	}
+
+	/* Send command and start transaction */
+	mchbar_write32(BIOS_MAILBOX_INTERFACE, command | MAILBOX_RUN_BUSY);
+
+	if (pcode_ready() < 0) {
+		printk(BIOS_ERR, "PCODE: mailbox timeout on completion.\n");
+		return 0;
+	}
+
+	/* Read mailbox */
+	return mchbar_read32(BIOS_MAILBOX_DATA);
+}
+
+int pcode_mailbox_write(u32 command, u32 data)
+{
+	if (pcode_ready() < 0) {
+		printk(BIOS_ERR, "PCODE: mailbox timeout on wait ready.\n");
+		return -1;
+	}
+
+	mchbar_write32(BIOS_MAILBOX_DATA, data);
+
+	/* Send command and start transaction */
+	mchbar_write32(BIOS_MAILBOX_INTERFACE, command | MAILBOX_RUN_BUSY);
+
+	if (pcode_ready() < 0) {
+		printk(BIOS_ERR, "PCODE: mailbox timeout on completion.\n");
+		return -1;
+	}
+
+	return 0;
+}

From 776622879878ef22baed3d3ce1b07dbd1ed4542a Mon Sep 17 00:00:00 2001
From: Angel Pons <th3fanbus@gmail.com>
Date: Sun, 25 May 2025 11:41:04 +0200
Subject: [PATCH 1147/3886] Haswell NRI: Deduplicate PCODE mailbox functions

Now that the CPU code exports these PCODE mailbox functions, there is no
reason to retain a copy of them in NRI.

Change-Id: Ic9853cfd6793ecdadf8d2bd15b268f9cf95ba32d
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87828
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 .../haswell/native_raminit/configure_mc.c     | 43 +------------------
 1 file changed, 1 insertion(+), 42 deletions(-)

diff --git a/src/northbridge/intel/haswell/native_raminit/configure_mc.c b/src/northbridge/intel/haswell/native_raminit/configure_mc.c
index 5562dbdf2e..8ff81727ec 100644
--- a/src/northbridge/intel/haswell/native_raminit/configure_mc.c
+++ b/src/northbridge/intel/haswell/native_raminit/configure_mc.c
@@ -3,6 +3,7 @@
 #include <assert.h>
 #include <commonlib/bsd/clamp.h>
 #include <console/console.h>
+#include <cpu/intel/haswell/haswell.h>
 #include <delay.h>
 #include <lib.h>
 #include <northbridge/intel/haswell/haswell.h>
@@ -583,48 +584,6 @@ static void program_ls_comp(struct sysinfo *ctrl)
 	mchbar_write32(DDR_COMP_CTL_0, ctrl->comp_ctl_0.raw);
 }
 
-/** TODO: Deduplicate PCODE stuff, it's already implemented in CPU code **/
-static bool pcode_ready(void)
-{
-	const unsigned int delay_step = 10;
-	for (unsigned int i = 0; i < 1000; i += delay_step) {
-		if (!(mchbar_read32(BIOS_MAILBOX_INTERFACE) & MAILBOX_RUN_BUSY))
-			return true;
-
-		udelay(delay_step);
-	};
-	return false;
-}
-
-static uint32_t pcode_mailbox_read(const uint32_t command)
-{
-	if (!pcode_ready()) {
-		printk(BIOS_ERR, "PCODE: mailbox timeout on wait ready\n");
-		return 0;
-	}
-	mchbar_write32(BIOS_MAILBOX_INTERFACE, command | MAILBOX_RUN_BUSY);
-	if (!pcode_ready()) {
-		printk(BIOS_ERR, "PCODE: mailbox timeout on completion\n");
-		return 0;
-	}
-	return mchbar_read32(BIOS_MAILBOX_DATA);
-}
-
-static int pcode_mailbox_write(const uint32_t command, const uint32_t data)
-{
-	if (!pcode_ready()) {
-		printk(BIOS_ERR, "PCODE: mailbox timeout on wait ready\n");
-		return -1;
-	}
-	mchbar_write32(BIOS_MAILBOX_DATA, data);
-	mchbar_write32(BIOS_MAILBOX_INTERFACE, command | MAILBOX_RUN_BUSY);
-	if (!pcode_ready()) {
-		printk(BIOS_ERR, "PCODE: mailbox timeout on completion\n");
-		return -1;
-	}
-	return 0;
-}
-
 static void enable_2x_refresh(struct sysinfo *ctrl)
 {
 	if (!CONFIG(ENABLE_DDR_2X_REFRESH)) {

From 0c5286ba34f005d08d316dbaa792c01747fb050c Mon Sep 17 00:00:00 2001
From: Angel Pons <th3fanbus@gmail.com>
Date: Sun, 25 May 2025 12:18:39 +0200
Subject: [PATCH 1148/3886] Haswell NRI: Tidy up REUT subsequence programming

The REUT subsequence control register had a different layout in the
Haswell A0 stepping, so it was initially programmed using bitmasks.
However, NRI does not implement support for the A0 stepping because
it is early pre-production silicon that no one should be using, but
the code kept using the bitmasks approach. But we can do better.

Introduce a bitfield for the REUT subsequence control register, and
use it instead of bitmasks. Put the enum for subsequence types next
to the code using it (no reason to have it in the common header, it
is not used anywhere else). And make a helper function that encodes
the number of cachelines in the format expected by the REUT (7 bits
of value, 1 bit for exponential/linear).

Change-Id: I1609ad010e714b0fc47403df7a71e5fc5ae0f5ac
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87829
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 .../haswell/native_raminit/raminit_native.h   |  10 --
 .../haswell/native_raminit/reg_structs.h      |  14 +++
 .../intel/haswell/native_raminit/testing_io.c | 104 +++++++++---------
 3 files changed, 64 insertions(+), 64 deletions(-)

diff --git a/src/northbridge/intel/haswell/native_raminit/raminit_native.h b/src/northbridge/intel/haswell/native_raminit/raminit_native.h
index 07eea98831..2841ff6e1a 100644
--- a/src/northbridge/intel/haswell/native_raminit/raminit_native.h
+++ b/src/northbridge/intel/haswell/native_raminit/raminit_native.h
@@ -118,16 +118,6 @@ enum reut_cmd_pat {
 	PAT_ODT_TA,
 };
 
-/* REUT subsequence types (B = Base, O = Offset) */
-enum {
-	SUBSEQ_B_RD	= 0 << 22,
-	SUBSEQ_B_WR	= 1 << 22,
-	SUBSEQ_B_RD_WR	= 2 << 22,
-	SUBSEQ_B_WR_RD	= 3 << 22,
-	SUBSEQ_O_RD	= 4 << 22,
-	SUBSEQ_O_WR	= 5 << 22,
-};
-
 /* REUT mux control */
 enum {
 	REUT_MUX_LMN      = 0,
diff --git a/src/northbridge/intel/haswell/native_raminit/reg_structs.h b/src/northbridge/intel/haswell/native_raminit/reg_structs.h
index 0d9aaa1f7c..8a1586b49a 100644
--- a/src/northbridge/intel/haswell/native_raminit/reg_structs.h
+++ b/src/northbridge/intel/haswell/native_raminit/reg_structs.h
@@ -478,6 +478,20 @@ union reut_pat_cadb_mrs_reg {
 	uint32_t raw;
 };
 
+union reut_subseq_ctl_reg {
+	struct __packed {
+		uint32_t num_cachelines_with_scale        :  8; // Bits  7:0
+		uint32_t subseq_wait                      : 14; // Bits 21:8
+		uint32_t subseq_type                      :  4; // Bits 25:22
+		uint32_t save_curr_base_addr_to_start     :  1; // Bits 26:26
+		uint32_t reset_curr_base_addr_to_start    :  1; // Bits 27:27
+		uint32_t data_and_ecc_addr_inversion      :  2; // Bits 29:28
+		uint32_t invert_data_and_ecc              :  1; // Bits 30:30
+		uint32_t stop_base_subseq_on_wrap_trigger :  1; // Bits 31:31
+	};
+	uint32_t raw;
+};
+
 union reut_seq_cfg_reg {
 	struct __packed {
 		uint32_t                               :  3; // Bits  2:0
diff --git a/src/northbridge/intel/haswell/native_raminit/testing_io.c b/src/northbridge/intel/haswell/native_raminit/testing_io.c
index 2632c238f8..05cd5d019b 100644
--- a/src/northbridge/intel/haswell/native_raminit/testing_io.c
+++ b/src/northbridge/intel/haswell/native_raminit/testing_io.c
@@ -172,42 +172,63 @@ void program_loop_count(const struct sysinfo *ctrl, const uint8_t channel, const
 	}
 }
 
-static inline void write_subseq(const uint8_t channel, const uint8_t idx, const uint32_t ssq)
+/* REUT subsequence types (B = Base, O = Offset) */
+enum {
+	SUBSEQ_B_RD	= 0,
+	SUBSEQ_B_WR	= 1,
+	SUBSEQ_B_RD_WR	= 2,
+	SUBSEQ_B_WR_RD	= 3,
+	SUBSEQ_O_RD	= 4,
+	SUBSEQ_O_WR	= 5,
+};
+
+static void write_subseq(uint8_t ch, uint8_t idx, union reut_subseq_ctl_reg ssq, uint8_t type)
 {
-	mchbar_write32(REUT_ch_SUBSEQ_x_CTL(channel, idx), ssq);
+	ssq.subseq_type = type;
+	mchbar_write32(REUT_ch_SUBSEQ_x_CTL(ch, idx), ssq.raw);
 }
 
 static void program_subseq(
 	struct sysinfo *const ctrl,
 	const uint8_t channel,
 	const enum reut_cmd_pat cmd_pat,
-	const uint32_t ss_a,
-	const uint32_t ss_b)
+	const union reut_subseq_ctl_reg ss_a,
+	const union reut_subseq_ctl_reg ss_b)
 {
 	switch (cmd_pat) {
 	case PAT_WR_RD_TA:
-		write_subseq(channel, 0, ss_a | SUBSEQ_B_WR);
-		for (uint8_t i = 1; i < 7; i++)
-			write_subseq(channel, i, ss_b | SUBSEQ_B_RD_WR);
-
-		write_subseq(channel, 7, ss_a | SUBSEQ_B_RD);
+		write_subseq(channel, 0, ss_a, SUBSEQ_B_WR);
+		for (uint8_t i = 1; i < 7; i++) {
+			write_subseq(channel, i, ss_b, SUBSEQ_B_RD_WR);
+		}
+		write_subseq(channel, 7, ss_a, SUBSEQ_B_RD);
 		break;
 	case PAT_RD_WR_TA:
-		write_subseq(channel, 0, ss_b | SUBSEQ_B_WR_RD);
+		write_subseq(channel, 0, ss_b, SUBSEQ_B_WR_RD);
 		break;
 	case PAT_ODT_TA:
-		write_subseq(channel, 0, ss_a | SUBSEQ_B_WR);
-		write_subseq(channel, 1, ss_b | SUBSEQ_B_RD_WR);
-		write_subseq(channel, 2, ss_a | SUBSEQ_B_RD);
-		write_subseq(channel, 3, ss_b | SUBSEQ_B_WR_RD);
+		write_subseq(channel, 0, ss_a, SUBSEQ_B_WR);
+		write_subseq(channel, 1, ss_b, SUBSEQ_B_RD_WR);
+		write_subseq(channel, 2, ss_a, SUBSEQ_B_RD);
+		write_subseq(channel, 3, ss_b, SUBSEQ_B_WR_RD);
 		break;
 	default:
-		write_subseq(channel, 0, ss_a | SUBSEQ_B_WR);
-		write_subseq(channel, 1, ss_a | SUBSEQ_B_RD);
+		write_subseq(channel, 0, ss_a, SUBSEQ_B_WR);
+		write_subseq(channel, 1, ss_a, SUBSEQ_B_RD);
 		break;
 	}
 }
 
+static uint8_t encode_num_cl(const uint16_t number_of_cachelines)
+{
+	/* Low 7 bits are the value, high bit means exponential/linear value */
+	if (number_of_cachelines > 127) {
+		return log2_ceil(number_of_cachelines);	/* Assume exponential/pow2 number */
+	} else {
+		return number_of_cachelines | BIT(7);	/* Small, treat as linear number */
+	}
+}
+
 void setup_io_test(
 	struct sysinfo *ctrl,
 	const uint8_t chanmask,
@@ -234,24 +255,8 @@ void setup_io_test(
 	if (cmd_pat == PAT_WR_RD_TA || cmd_pat == PAT_ODT_TA)
 		lc_exp = 0;
 
-	uint8_t num_clcr;
-	if (num_cl > 127) {
-		/* Assume exponential number */
-		num_clcr = log2_ceil(num_cl);
-	} else {
-		/* Set number of cache lines as linear number */
-		num_clcr = num_cl | BIT(7);
-	}
-
-	const uint16_t num_cl2 = 2 * num_cl;
-	uint8_t num_cl2cr;
-	if (num_cl2 > 127) {
-		/* Assume exponential number */
-		num_cl2cr = log2_ceil(num_cl2);
-	} else {
-		/* Set number of cache lines as linear number */
-		num_cl2cr = num_cl2 | BIT(7);
-	}
+	const uint8_t num_cl_cr = encode_num_cl(num_cl);
+	const uint8_t num_cl2_cr = encode_num_cl(2 * num_cl);
 
 	for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
 		if (!(chanmask & BIT(channel))) {
@@ -309,26 +314,17 @@ void setup_io_test(
 			.clear_errors = 1,
 		}.raw);
 
-		/*
-		 * Program subsequences
-		 */
-		uint32_t subseq_a = 0;
-
-		/* Number of cachelines and scale */
-		subseq_a |= (num_clcr    & 0x00ff) << 0;
-		subseq_a |= (subseq_wait & 0x3fff) << 8;
-
-		/* Reset current base address to start */
-		subseq_a |= BIT(27);
-
-		uint32_t subseq_b = 0;
-
-		/* Number of cachelines and scale */
-		subseq_b |= (num_cl2cr   & 0x00ff) << 0;
-		subseq_b |= (subseq_wait & 0x3fff) << 8;
-
-		/* Reset current base address to start */
-		subseq_b |= BIT(27);
+		/* Program subsequences */
+		const union reut_subseq_ctl_reg subseq_a = {
+			.num_cachelines_with_scale     = num_cl_cr,
+			.subseq_wait                   = subseq_wait,
+			.reset_curr_base_addr_to_start = 1,
+		};
+		const union reut_subseq_ctl_reg subseq_b = {
+			.num_cachelines_with_scale     = num_cl2_cr,
+			.subseq_wait                   = subseq_wait,
+			.reset_curr_base_addr_to_start = 1,
+		};
 
 		program_subseq(ctrl, channel, cmd_pat, subseq_a, subseq_b);
 

From 4ae9a79d8deff010c8235025039f683dcf4f1a42 Mon Sep 17 00:00:00 2001
From: Angel Pons <th3fanbus@gmail.com>
Date: Sun, 25 May 2025 13:54:13 +0200
Subject: [PATCH 1149/3886] Haswell NRI: Remove unused `SPD_LEN` define

This was kept around to avoid build issues back when the NRI patches
were awaiting review. It is no longer used and to-be-upstreamed code
does not use this define either, so now is a good time to get rid of
it.

Change-Id: Id10d81774b0d679b54d5dc4a15dab5996e3a68c5
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87832
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/northbridge/intel/haswell/native_raminit/raminit_native.h | 3 ---
 1 file changed, 3 deletions(-)

diff --git a/src/northbridge/intel/haswell/native_raminit/raminit_native.h b/src/northbridge/intel/haswell/native_raminit/raminit_native.h
index 2841ff6e1a..82ecb1c03d 100644
--- a/src/northbridge/intel/haswell/native_raminit/raminit_native.h
+++ b/src/northbridge/intel/haswell/native_raminit/raminit_native.h
@@ -11,9 +11,6 @@
 
 #include "reg_structs.h"
 
-/** TODO (Angel): Remove this after in-review patches are submitted **/
-#define SPD_LEN SPD_SIZE_MAX_DDR3
-
 /* Each channel has 4 ranks, spread across 2 slots */
 #define NUM_SLOTRANKS		4
 

From 99af85ad364318839111e33423d2ec536eddc34f Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Wed, 21 May 2025 17:52:46 -0500
Subject: [PATCH 1150/3886] mb/google/puff: Add VBTs for Moonbuggy and Scout
 variants

These variants were missing VBTs necessary for display init, so add
them. VBT files taken from the stock firmware images:
coreboot-Google_Moonbuggy.13324.803.0.bin
coreboot-Google_Scout.13324.645.0.bin

Since all variants now have VBTs, move the selection of
INTEL_GMA_HAVE_VBT to the baseboard.

TEST=build/boot various puff variants, including scout.

Change-Id: I2bb06894fc4df358cc38a4627de9f95289c2c5e0
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87779
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
---
 src/mainboard/google/puff/Kconfig                |  12 +-----------
 .../google/puff/variants/moonbuggy/data.vbt      | Bin 0 -> 4608 bytes
 .../google/puff/variants/scout/data.vbt          | Bin 0 -> 4608 bytes
 3 files changed, 1 insertion(+), 11 deletions(-)
 create mode 100644 src/mainboard/google/puff/variants/moonbuggy/data.vbt
 create mode 100644 src/mainboard/google/puff/variants/scout/data.vbt

diff --git a/src/mainboard/google/puff/Kconfig b/src/mainboard/google/puff/Kconfig
index c35cf6b188..2ec9d996b9 100644
--- a/src/mainboard/google/puff/Kconfig
+++ b/src/mainboard/google/puff/Kconfig
@@ -24,6 +24,7 @@ config BOARD_GOOGLE_BASEBOARD_PUFF
 	select GOOGLE_SMBIOS_MAINBOARD_VERSION
 	select HAVE_ACPI_RESUME
 	select HAVE_ACPI_TABLES
+	select INTEL_GMA_HAVE_VBT
 	select INTEL_LPSS_UART_FOR_CONSOLE
 	select MAINBOARD_HAS_CHROMEOS
 	select MAINBOARD_HAS_TPM2
@@ -41,50 +42,40 @@ config BOARD_GOOGLE_BASEBOARD_PUFF
 
 config BOARD_GOOGLE_AMBASSADOR
 	select BOARD_GOOGLE_BASEBOARD_PUFF
-	select INTEL_GMA_HAVE_VBT
 
 config BOARD_GOOGLE_DOOLY
 	select BOARD_GOOGLE_BASEBOARD_PUFF
-	select INTEL_GMA_HAVE_VBT
 	select SYSTEM_TYPE_ALL_IN_ONE
 
 config BOARD_GOOGLE_DUFFY_LEGACY
 	select BOARD_GOOGLE_BASEBOARD_PUFF
 	select BOARD_ROMSIZE_KB_32768
-	select INTEL_GMA_HAVE_VBT
 
 config BOARD_GOOGLE_DUFFY
 	select BOARD_GOOGLE_BASEBOARD_PUFF
-	select INTEL_GMA_HAVE_VBT
 
 config BOARD_GOOGLE_FAFFY
 	select BOARD_GOOGLE_BASEBOARD_PUFF
-	select INTEL_GMA_HAVE_VBT
 
 config BOARD_GOOGLE_GENESIS
 	select BOARD_GOOGLE_BASEBOARD_PUFF
-	select INTEL_GMA_HAVE_VBT
 
 config BOARD_GOOGLE_KAISA_LEGACY
 	select BOARD_GOOGLE_BASEBOARD_PUFF
 	select BOARD_ROMSIZE_KB_32768
-	select INTEL_GMA_HAVE_VBT
 
 config BOARD_GOOGLE_KAISA
 	select BOARD_GOOGLE_BASEBOARD_PUFF
-	select INTEL_GMA_HAVE_VBT
 
 config BOARD_GOOGLE_MOONBUGGY
 	select BOARD_GOOGLE_BASEBOARD_PUFF
 
 config BOARD_GOOGLE_NOIBAT
 	select BOARD_GOOGLE_BASEBOARD_PUFF
-	select INTEL_GMA_HAVE_VBT
 
 config BOARD_GOOGLE_PUFF
 	select BOARD_GOOGLE_BASEBOARD_PUFF
 	select BOARD_ROMSIZE_KB_32768
-	select INTEL_GMA_HAVE_VBT
 
 config BOARD_GOOGLE_SCOUT
 	select BOARD_GOOGLE_BASEBOARD_PUFF
@@ -92,7 +83,6 @@ config BOARD_GOOGLE_SCOUT
 
 config BOARD_GOOGLE_WYVERN
 	select BOARD_GOOGLE_BASEBOARD_PUFF
-	select INTEL_GMA_HAVE_VBT
 
 if BOARD_GOOGLE_BASEBOARD_PUFF
 
diff --git a/src/mainboard/google/puff/variants/moonbuggy/data.vbt b/src/mainboard/google/puff/variants/moonbuggy/data.vbt
new file mode 100644
index 0000000000000000000000000000000000000000..a25cfde012547b8e89c9fb1d88248a431e65ab28
GIT binary patch
literal 4608
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literal 0
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diff --git a/src/mainboard/google/puff/variants/scout/data.vbt b/src/mainboard/google/puff/variants/scout/data.vbt
new file mode 100644
index 0000000000000000000000000000000000000000..ca387a5a70ae53c9bc579a013b549d21da22f3ca
GIT binary patch
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zK3qR}u_v(F7&u;uK`6O6g5f$-MGRd}8v33yt%h;7g5a`lNpiolnx5RZy#I6$H0oPR
z_E?xbS>op_g;GsF9BC=dWCM+cj`mp4Xx5bYEmkhNtH~nRUYr>@vyu>+%-jJ8!CB&W
z8F|JzUB!HOH#Bp;XL^O6erM?%f(ZNyEgP<C5cDSFTy{FA*Y{X=Ml%MHrX$ha&Pk4-
zSO`w6B8$rbm`USOUDjijEK0N<DTbnZGoKIUB)|QvcC;1ipWobU3^Z59LWEi?1`oIv
zUl$<*vPG!Ns;a*d18t;c49TtO!SwD!`NEFf2lM}fik0ABm1|!C*S2$Xk3VgfKZzB6
zzWs0L<ptzeK<gs#`c?`uLAU#zbb#exo$xkLAhX}my_l100k!A?9G#>4L$wBD_Rq^d
QE;pFlmbn4YD!YgDC;WEU9{>OV

literal 0
HcmV?d00001


From dcc8400e270b5e90f880013efef7348d1a3d4c51 Mon Sep 17 00:00:00 2001
From: Tongtong Pan <pantongtong@huaqin.corp-partner.google.com>
Date: Fri, 23 May 2025 10:29:55 +0800
Subject: [PATCH 1151/3886] mb/google/fatcat/var/felino: Modify GPIOs config

Make some GPIOs corrections, refer to the schematic revision
 NB7501A_WSCH_MB_V4P_0427.

disable MIPI config
disable ISH
modify HW_ID config
nc some strap pin to default
modify sx related pins

BUG=NONE
TEST=emerge-fatcat coreboot

Change-Id: I075efda3044ffe45d7db3d225b10e96e084483aa
Signed-off-by: Tongtong Pan <pantongtong@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87806
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
---
 .../google/fatcat/variants/felino/gpio.c      | 164 +++++++++---------
 1 file changed, 82 insertions(+), 82 deletions(-)

diff --git a/src/mainboard/google/fatcat/variants/felino/gpio.c b/src/mainboard/google/fatcat/variants/felino/gpio.c
index fd16fa6de5..5a317f1491 100644
--- a/src/mainboard/google/fatcat/variants/felino/gpio.c
+++ b/src/mainboard/google/fatcat/variants/felino/gpio.c
@@ -28,12 +28,12 @@ static const struct pad_config gpio_table[] = {
 	/* GPP_A06:     ESPI_RST_EC_R_N */
 	/*  GPP_A06 : GPP_A06 ==> ESPI_RST_HDR configured on reset, do not touch */
 
-	/* GPP_A08:     MIPI_RGB_XSHUTDN */
-	PAD_CFG_GPO(GPP_A08, 1, PLTRST),
-	/* GPP_A09:     MIPI_RGB_OSC_EN */
-	PAD_CFG_GPO(GPP_A09, 1, PLTRST),
-	/* GPP_A10:     WWAN_RF_DISABLE_ODL */
-	PAD_CFG_GPO(GPP_A10, 1, PLTRST),
+	/* GPP_A08:     Not used */
+	PAD_NC(GPP_A08, NONE),
+	/* GPP_A09:     Not used */
+	PAD_NC(GPP_A09, NONE),
+	/* GPP_A10:     Not used */
+	PAD_NC(GPP_A10, NONE),
 	/* GPP_A11:     WLAN_SOC_RST_N */
 	PAD_CFG_GPO(GPP_A11, 1, PLTRST),
 	/* GPP_A12:     WAKE_PCIE_N_SOC */
@@ -41,7 +41,7 @@ static const struct pad_config gpio_table[] = {
 	/* GPP_A13:     Not used */
 	PAD_NC(GPP_A13, NONE),
 	/* GPP_A15:     HW_ID1 */
-	PAD_CFG_NF(GPP_A15, NONE, DEEP, NF1),
+	PAD_CFG_GPI(GPP_A15, NONE, PLTRST),
 	/* GPP_A16:     BT_RF_KILL_N */
 	PAD_CFG_GPO(GPP_A16, 1, DEEP),
 	/* GPP_A17:     PCH_WLAN_OFF_N */
@@ -51,14 +51,14 @@ static const struct pad_config gpio_table[] = {
 	PAD_CFG_NF(GPP_B00, NONE, DEEP, NF1),
 	/* GPP_B01:     TYPEC_PD_SOC_DAT */
 	PAD_CFG_NF(GPP_B01, NONE, DEEP, NF1),
-	/* GPP_B02:     I2C_SDA_E3_SOC */
-	PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_B02, NONE, DEEP, NF3),
-	/* GPP_B03:     I2C_SCL_E3_SOC */
-	PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_B03, NONE, DEEP, NF3),
+	/* GPP_B02:     Not used */
+	PAD_NC(GPP_B02, NONE),
+	/* GPP_B03:     Not used */
+	PAD_NC(GPP_B03, NONE),
 	/* GPP_B04:     NC */
 	PAD_NC(GPP_B04, NONE),
-	/* GPP_B05:     MIPI_IR_LED_PWM */
-	PAD_CFG_NF(GPP_B05, NONE, DEEP, NF4),
+	/* GPP_B05:     Not used */
+	PAD_NC(GPP_B05, NONE),
 	/* GPP_B06:     NC */
 	PAD_NC(GPP_B06, NONE),
 	/* GPP_B07:     NC */
@@ -70,7 +70,7 @@ static const struct pad_config gpio_table[] = {
 	/* GPP_B10:     SOC_DP1_HDMI_HPD */
 	PAD_CFG_NF(GPP_B10, NONE, DEEP, NF2),
 	/* GPP_B11:     PD1_OC_P0_P1_N */
-	PAD_NC(GPP_B11, NONE),
+	PAD_CFG_NF(GPP_B11, NONE, DEEP, NF1),
 	/* GPP_B12:     SLP_S0_SOC_N */
 	PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1),
 	/* GPP_B13:     PLT_RST_N */
@@ -83,22 +83,22 @@ static const struct pad_config gpio_table[] = {
 	PAD_NC(GPP_B16, NONE),
 	/* GPP_B17:     NC */
 	PAD_NC(GPP_B17, NONE),
-	/* GPP_B18:     ISH_I2C_EC_SDA */
-	PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_B18, NONE, DEEP, NF1),
-	/* GPP_B19:     ISH_I2C_EC_SCL */
-	PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_B19, NONE, DEEP, NF1),
+	/* GPP_B18:     Not used */
+	PAD_NC(GPP_B18, NONE),
+	/* GPP_B19:     Not used */
+	PAD_NC(GPP_B19, NONE),
 	/* GPP_B20:     I2C2_SOC_SDA */
 	PAD_CFG_GPO(GPP_B20, 1, PLTRST),
 	/* GPP_B21:     I2C2_SOC_SCL */
 	PAD_CFG_GPO(GPP_B21, 0, DEEP),
-	/* GPP_B22:     Cable_INT_N */
-	PAD_CFG_NF(GPP_B22, NONE, DEEP, NF4),
+	/* GPP_B22:     Not used */
+	PAD_NC(GPP_B22, NONE),
 	/* GPP_B23:     HW_ID0 */
-	PAD_CFG_NF(GPP_B23, NONE, DEEP, NF4),
+	PAD_CFG_GPI(GPP_B23, NONE, PLTRST),
 	/* GPP_B24:     ESPI_ALERT0_N */
-	PAD_NC(GPP_B24, NONE),
-	/* GPP_B25:     MIPI_RGB_LDO_EN */
-	PAD_CFG_GPI_SCI_LOW(GPP_B25, NONE, DEEP, LEVEL),
+	PAD_CFG_NF_IOSSTATE(GPP_B24, UP_20K, DEEP, NF1, IGNORE),
+	/* GPP_B25:     Not used */
+	PAD_NC(GPP_B25, NONE),
 
 	/* GPP_C00:     NC */
 	PAD_NC(GPP_C00, NONE),
@@ -111,7 +111,7 @@ static const struct pad_config gpio_table[] = {
 	PAD_CFG_NF(GPP_C03, UP_20K, DEEP, NF1),
 	/* GPP_C04:     SMBUS_DAT0 */
 	PAD_CFG_NF(GPP_C04, UP_20K, DEEP, NF1),
-	/* GPP_C05:     GPPC_C5 */
+	/* GPP_C05:     Not used */
 	PAD_NC(GPP_C05, NONE),
 	/* GPP_C06:     NC */
 	PAD_NC(GPP_C06, NONE),
@@ -132,7 +132,7 @@ static const struct pad_config gpio_table[] = {
 	/* GPP_C14:     NC */
 	PAD_NC(GPP_C14, NONE),
 	/* GPP_C15:     GPP_C15 */
-	PAD_CFG_GPO(GPP_C15, 1, PLTRST),
+	PAD_NC(GPP_C15, NONE),
 	/* GPP_C16:     NC  */
 	PAD_NC(GPP_C16, NONE),
 	/* GPP_C17:     NC  */
@@ -150,26 +150,26 @@ static const struct pad_config gpio_table[] = {
 	/* GPP_C23:     TBT_LSX0_RXD */
 	PAD_CFG_NF(GPP_C23, NONE, DEEP, NF1),
 
-	/* GPP_D00:     MIPI_RGB_IR_MCLK */
-	PAD_CFG_NF(GPP_D00, NONE, DEEP, NF1),
-	/* GPP_D01:     ALS_I2C_SDA */
-	PAD_CFG_NF(GPP_D01, NONE, DEEP, NF3),
-	/* GPP_D02:     ALS_I2C_SCL */
-	PAD_CFG_NF(GPP_D02, NONE, DEEP, NF3),
+	/* GPP_D00:     Not used */
+	PAD_NC(GPP_D00, NONE),
+	/* GPP_D01:     Not used */
+	PAD_NC(GPP_D01, NONE),
+	/* GPP_D02:     Not used */
+	PAD_NC(GPP_D02, NONE),
 	/* GPP_D03:     SLP_S0_GATE_R */
-	PAD_CFG_GPO(GPP_D03, 1, PLTRST),
-	/* GPP_D04:     MIPI_RGB_MCLK */
-	PAD_CFG_NF(GPP_D04, NONE, DEEP, NF1),
-	/* GPP_D05:     UART0_ISH_RX_DBG_TX_U */
-	PAD_CFG_NF(GPP_D05, NONE, DEEP, NF1),
-	/* GPP_D06:     UART0_ISH_TX_DBG_RX_U */
-	PAD_CFG_NF(GPP_D06, NONE, DEEP, NF1),
-	/* GPP_D07:     CAM_VDD_EN_SOC */
-	PAD_CFG_GPO(GPP_D07, 1, PLTRST),
+	PAD_CFG_GPO(GPP_D03, 1, DEEP),
+	/* GPP_D04:     Not used*/
+	PAD_NC(GPP_D04, NONE),
+	/* GPP_D05:     Not used */
+	PAD_NC(GPP_D05, NONE),
+	/* GPP_D06:     Not used */
+	PAD_NC(GPP_D06, NONE),
+	/* GPP_D07:     Not used */
+	PAD_NC(GPP_D07, NONE),
 	/* GPP_D08:     NC */
 	PAD_NC(GPP_D08, NONE),
-	/* GPP_D09:     USB_MUX_SEL */
-	PAD_CFG_GPO(GPP_D09, 1, PLTRST),
+	/* GPP_D09:     Not used */
+	PAD_NC(GPP_D09, NONE),
 	/* GPP_D10:     PMC_WLAN_CLK ==> NC */
 	PAD_NC_LOCK(GPP_D10, NONE, LOCK_CONFIG),
 	/* GPP_D11:     CNV_PCM_SYNC ==> NC */
@@ -199,20 +199,20 @@ static const struct pad_config gpio_table[] = {
 	/* GPP_D23:     DG_I3C_SCL */
 	PAD_CFG_NF(GPP_D23, NONE, DEEP, NF1),
 	/* GPP_D24:     MIPI_IR_LDO_EN */
-	PAD_CFG_GPI_SCI_LOW(GPP_D24, NONE, DEEP, LEVEL),
+	PAD_NC(GPP_D24, NONE),
 	/* GPP_D25:     MIPI_IR_OSC_EN */
-	PAD_CFG_GPI_SCI_LOW(GPP_D25, NONE, DEEP, LEVEL),
+	PAD_NC(GPP_D25, NONE),
 
 	/* GPP_E01:     SLOW_R */
-	PAD_CFG_GPI(GPP_E01, NONE, PLTRST),
-	/* GPP_E02:     NC  */
-	PAD_NC(GPP_E02, NONE),
+	PAD_NC(GPP_E01, NONE),
+	/* GPP_E02:     VRALERT_N */
+	PAD_CFG_NF(GPP_E02, NONE, DEEP, NF2),
 	/* GPP_E03:     EC_SYNC_IRQ */
 	PAD_CFG_GPI_APIC(GPP_E03, NONE, PLTRST, LEVEL, INVERT),
 	/* GPP_E05:     NC */
 	PAD_NC(GPP_E05, NONE),
 	/* GPP_E06:     GPP_E06 */
-	PAD_CFG_GPI_TRIG_OWN(GPP_E06, NONE, PLTRST, LEVEL, ACPI),
+	PAD_NC(GPP_E06, NONE),
 	/* GPP_E07:     NC */
 	PAD_NC(GPP_E07, NONE),
 	/* GPP_E08:     NC */
@@ -238,13 +238,13 @@ static const struct pad_config gpio_table[] = {
 	/* GPP_E18:     TOUCHPAD_INT_N */
 	PAD_CFG_GPI_APIC(GPP_E18, NONE, PLTRST, LEVEL, NONE),
 	/* GPP_E19:     HW_ID5 */
-	PAD_CFG_GPO(GPP_E19, 1, PLTRST),
+	PAD_CFG_GPI(GPP_E19, NONE, PLTRST),
 	/* GPP_E20:     HW_ID4 */
-	PAD_CFG_GPO(GPP_E20, 1, PLTRST),
+	PAD_CFG_GPI(GPP_E20, NONE, PLTRST),
 	/* GPP_E21:     TYPEC_PD_SOC_INT */
 	PAD_CFG_NF(GPP_E21, NONE, DEEP, NF1),
 	/* GPP_E22:     MIPI_IR_XSHUTDN */
-	PAD_CFG_NF(GPP_E22, NONE, DEEP, NF3),
+	PAD_NC(GPP_E22, NONE),
 
 	/* GPP_F00:     CNV_BRI_DT */
 	PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_F00, NONE, DEEP, NF1),
@@ -269,7 +269,7 @@ static const struct pad_config gpio_table[] = {
 	/* GPP_F09:     SX_EXIT_HOLDOFF# */
 	PAD_CFG_NF(GPP_F09, NONE, DEEP, NF2),
 	/* GPP_F10:     HW_ID7 */
-	PAD_CFG_GPO(GPP_F10, 0, PLTRST),
+	PAD_CFG_GPI(GPP_F10, NONE, PLTRST),
 	/* GPP_F11:     TC_RETIMER_FORCE_PWR */
 	PAD_CFG_GPO(GPP_F11, 1, DEEP),
 	/* GPP_F12:     NC */
@@ -287,7 +287,7 @@ static const struct pad_config gpio_table[] = {
 	/* GPP_F18:     NC */
 	PAD_NC(GPP_F18, NONE),
 	/* GPP_F19:     GPP_F19 */
-	PAD_CFG_GPO(GPP_F19, 0, PLTRST),
+	PAD_NC(GPP_F19, NONE),
 	/* GPP_F20:     NC */
 	PAD_NC(GPP_F20, NONE),
 	/* GPP_F22:     NC */
@@ -304,35 +304,35 @@ static const struct pad_config gpio_table[] = {
 	/* GPP_H03:     NC */
 	PAD_NC(GPP_H03, NONE),
 	/* GPP_H04:     MIPI_IR_SDA */
-	PAD_CFG_NF(GPP_H04, NONE, DEEP, NF1),
+	PAD_NC(GPP_H04, NONE),
 	/* GPP_H05:     MIPI_IR_SCL */
-	PAD_CFG_NF(GPP_H05, NONE, DEEP, NF1),
+	PAD_NC(GPP_H05, NONE),
 	/* GPP_H06:     CAM_I2C_DAT_CONN */
-	PAD_CFG_NF(GPP_H06, NONE, DEEP, NF1),
+	PAD_NC(GPP_H06, NONE),
 	/* GPP_H07:     CAM_I2C_CLK_CONN */
-	PAD_CFG_NF(GPP_H07, NONE, DEEP, NF1),
+	PAD_NC(GPP_H07, NONE),
 	/* GPP_H08:     UART0_BUF_RXD */
 	PAD_CFG_NF(GPP_H08, NONE, DEEP, NF1),
 	/* GPP_H09:     UART0_BUF_TXD */
 	PAD_CFG_NF(GPP_H09, NONE, DEEP, NF1),
 	/* GPP_H10:     HW_ID6 */
-	PAD_CFG_NF(GPP_H10, NONE, DEEP, NF1),
+	PAD_CFG_GPI(GPP_H10, NONE, PLTRST),
 	/* GPP_H11:     NC */
 	PAD_NC(GPP_H11, NONE),
 	/* GPP_H13:     CPU_C10_GATE_N */
 	PAD_CFG_NF(GPP_H13, NONE, DEEP, NF1),
-	/* GPP_H14:     AUTOOPEN_ALS_I2C_SDA */
-	PAD_CFG_NF(GPP_H14, NONE, DEEP, NF3),
-	/* GPP_H15:     AUTOOPEN_ALS_I2C_SCL */
-	PAD_CFG_NF(GPP_H15, NONE, DEEP, NF3),
+	/* GPP_H14:     Not used */
+	PAD_NC(GPP_H14, NONE),
+	/* GPP_H15:     Not used */
+	PAD_NC(GPP_H15, NONE),
 	/* GPP_H16:     NC */
 	PAD_NC(GPP_H16, NONE),
-	/* GPP_H17:     SOC_SCI_N */
-	PAD_CFG_NF(GPP_H17, NONE, DEEP, NF1),
+	/* GPP_H17:     Not used */
+	PAD_NC(GPP_H17, NONE),
 	/* GPP_H19:     HW_ID3 */
-	PAD_CFG_NF(GPP_H19, NONE, DEEP, NF2),
+	PAD_CFG_GPI(GPP_H19, NONE, PLTRST),
 	/* GPP_H20:     HW_ID2 */
-	PAD_CFG_NF(GPP_H20, NONE, DEEP, NF2),
+	PAD_CFG_GPI(GPP_H20, NONE, PLTRST),
 	/* GPP_H21:     PCH_I2C_GSC_SDA */
 	PAD_CFG_NF(GPP_H21, NONE, DEEP, NF1),
 	/* GPP_H22:     PCH_I2C_GSC_SCL */
@@ -367,26 +367,26 @@ static const struct pad_config gpio_table[] = {
 	PAD_CFG_NF(GPP_V04, NONE, DEEP, NF1),
 	/* GPP_V05:     PM_SLP_S4_N */
 	PAD_CFG_NF(GPP_V05, NONE, DEEP, NF1),
-	/* GPP_V06:     NC */
-	PAD_NC(GPP_V06, NONE),
-	/* GPP_V07:     Not used */
+	/* GPP_V06:     GPD_6_SLP_A_N */
+	PAD_CFG_NF(GPP_V06, NONE, DEEP, NF1),
+	/* GPP_V07:     SUS_CLK */
 	PAD_CFG_NF(GPP_V07, NONE, DEEP, NF1),
 	/* GPP_V08:     SLP_WLAN_N */
 	PAD_CFG_NF(GPP_V08, NONE, DEEP, NF1),
-	/* GPP_V09:     NC */
-	PAD_NC(GPP_V09, NONE),
-	/* GPP_V10:     NC */
-	PAD_NC(GPP_V10, NONE),
-	/* GPP_V11:     NC */
-	PAD_NC(GPP_V11, NONE),
+	/* GPP_V09:     PM_SLP_S5# */
+	PAD_CFG_NF(GPP_V09, NONE, DEEP, NF1),
+	/* GPP_V10:     LAN_PWR_DISABLE */
+	PAD_CFG_NF(GPP_V10, NONE, DEEP, NF1),
+	/* GPP_V11:     SLP_LAN_N */
+	PAD_CFG_NF(GPP_V11, NONE, DEEP, NF1),
 	/* GPP_V12:     WAKE# */
 	PAD_CFG_NF(GPP_V12, NONE, DEEP, NF1),
-	/* GPP_V13:     NC */
-	PAD_NC(GPP_V13, NONE),
-	/* GPP_V14:     NC */
-	PAD_NC(GPP_V14, NONE),
-	/* GPP_V15:     NC */
-	PAD_NC(GPP_V15, NONE),
+	/* GPP_V13:     GPP_V13_CATERR_N */
+	PAD_CFG_NF(GPP_V13, NONE, DEEP, NF1),
+	/* GPP_V14:     GPP_V14_FORCEPR_N */
+	PAD_CFG_NF(GPP_V14, NONE, DEEP, NF1),
+	/* GPP_V15:     GPP_V15_THERMTRIP_N */
+	PAD_CFG_NF(GPP_V15, NONE, DEEP, NF1),
 	/* GPP_V16:     VCCST_EN */
 	PAD_CFG_NF(GPP_V16, NONE, DEEP, NF1),
 	/* GPP_V17:     GPP_V17 */

From 7cbbf786cc2d513bc742f46ae7028d3fc5bd2192 Mon Sep 17 00:00:00 2001
From: Felix Singer <felixsinger@posteo.net>
Date: Sun, 25 May 2025 12:33:30 +0200
Subject: [PATCH 1152/3886] update_submodules: Use relative paths to submodules

There doesn't seem to be much reason to use absolute paths to the
submodules, other than that it's not needed to change to the original
directory.

In preparation for CB:87824, make use of relative paths and change to
the original directory at the start of each iteration.

Change-Id: Ic74b589d933e6acd882fb9a09461bf7c01952a6f
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87823
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
---
 util/scripts/update_submodules | 7 +++++--
 1 file changed, 5 insertions(+), 2 deletions(-)

diff --git a/util/scripts/update_submodules b/util/scripts/update_submodules
index fccc3f6ae2..7d36549c4d 100755
--- a/util/scripts/update_submodules
+++ b/util/scripts/update_submodules
@@ -65,7 +65,7 @@ get_args() {
 			exit 0
 			;;
 		-R | --repo)
-			submodule_dirs=("$(readlink -f "${1}")")
+			submodule_dirs="${1}"
 			shift
 			if [[ ! -d "${submodule_dirs[0]}" ]]; then
 				echo "Error: ${submodule_dirs[0]} is not valid."
@@ -92,12 +92,15 @@ main() {
 	get_args "$@"
 
 	if (( ${#submodule_dirs[@]} == 0 )); then
-		readarray -t submodule_dirs < <(git submodule foreach pwd | grep -v "Entering")
+		readarray -t submodule_dirs < <(git submodule status | cut -d ' ' -f 3)
 	fi
 
 	for submodule in "${submodule_dirs[@]}"; do
+		cd "${TOP}"
+
 		echo ""
 		echo "Checking submodule ${submodule}"
+
 		if ! cd "$submodule"; then
  			echo "Error: could not cd to $submodule"
 			exit 1

From ba8be191229838204dbd3cf21695d375c5d34137 Mon Sep 17 00:00:00 2001
From: Zhixing Ma <zhixing.ma@intel.com>
Date: Wed, 14 May 2025 15:49:23 -0700
Subject: [PATCH 1153/3886] mb/intel/ptlrvp: Update Kconfig for PTLRVP_CHROMEEC
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Update the MAINBOARD_PART_NUMBER config to support PTLRVP_CHROMEEC
variant.

BUG=NONE
TEST=boot ptlrvp_chromeec variant and verify correct mainboard name
in depthcharge.

Change-Id: Ic8208b4ee2c9055671d426cb4b4fdc2a494ad2d8
Signed-off-by: Zhixing Ma <zhixing.ma@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87688
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Reviewed-by: Jamie Ryu <jamie.m.ryu@intel.com>
---
 src/mainboard/intel/ptlrvp/Kconfig | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/src/mainboard/intel/ptlrvp/Kconfig b/src/mainboard/intel/ptlrvp/Kconfig
index 096821f885..476313f60d 100644
--- a/src/mainboard/intel/ptlrvp/Kconfig
+++ b/src/mainboard/intel/ptlrvp/Kconfig
@@ -119,7 +119,8 @@ config MAINBOARD_FAMILY
 	default "Intel_Ptlrvp"
 
 config MAINBOARD_PART_NUMBER
-	default "Ptlrvp"
+	default "Ptlrvp" if BOARD_INTEL_PTLRVP
+	default "Ptlrvp_chromeec" if BOARD_INTEL_PTLRVP_CHROMEEC
 
 config MEMORY_SOLDERDOWN
 	def_bool n

From 96ac0224ab1099067449a9927127306fc21d2c56 Mon Sep 17 00:00:00 2001
From: Stephen Douthit <stephend@silicom-usa.com>
Date: Mon, 29 Jul 2019 16:09:50 -0400
Subject: [PATCH 1154/3886] pci: Add support for assigning resources to SR-IOV
 VF BARs

This ensures that bridge windows allocate enough space to cover
SR-IOV BARs. Without this Linux will print messages, these messages
may differ depending on the kernel version used.

Debian GNU/Linux 12 (kernel 6.1.0-28-amd64):
pci 0000:06:00.0: BAR 7: no space for [mem size 0x00200000 64bit pref]
pci 0000:06:00.0: BAR 7: failed to assign [mem size 0x00200000 64bit
pref]

Ubuntu 22.04.5 LTS (kernel 6.8.0-52-generic):
pci 0000:06:00.0: VF BAR 0 [mem size 0x00200000 64bit pref]: can't
assign; no space
pci 0000:06:00.0: VF BAR 0 [mem size 0x00200000 64bit pref]: failed to
assign

TEST=Raptorlake-P

Change-Id: Ib169efe5a6b998a8342a895f1456a280669c719d
Signed-off-by: Stephen Douthit <stephend@silicom-usa.com>
Signed-off-by: Harrie Paijmans <hpaijmans@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34620
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/device/pci_device.c     |  5 +++
 src/device/pciexp_device.c  | 74 +++++++++++++++++++++++++++++++++++++
 src/include/device/pciexp.h |  2 +
 3 files changed, 81 insertions(+)

diff --git a/src/device/pci_device.c b/src/device/pci_device.c
index 29fde7ca6c..baa7a48ff9 100644
--- a/src/device/pci_device.c
+++ b/src/device/pci_device.c
@@ -543,6 +543,11 @@ void pci_dev_read_resources(struct device *dev)
 {
 	pci_read_bases(dev, 6);
 	pci_get_rom_resource(dev, PCI_ROM_ADDRESS);
+
+#if CONFIG(PCIEXP_PLUGIN_SUPPORT)
+	/* Check for SR-IOV BARs if we have PCIe support */
+	pciexp_dev_read_resources(dev);
+#endif
 }
 
 void pci_bus_read_resources(struct device *dev)
diff --git a/src/device/pciexp_device.c b/src/device/pciexp_device.c
index 8686e38a86..a5f162e8ac 100644
--- a/src/device/pciexp_device.c
+++ b/src/device/pciexp_device.c
@@ -764,6 +764,80 @@ static void pciexp_sync_max_payload_size(struct bus *bus, unsigned int max_paylo
 	}
 }
 
+/*
+ * Check if this is an SR-IOV capable device and add resources for all VF bars
+ *
+ * @param dev Pointer to the dev structure.
+ */
+void pciexp_dev_read_resources(struct device *dev)
+{
+	unsigned long sriovpos;
+	u16 numvfs, i;
+
+	sriovpos = pci_find_capability(dev, PCI_CAP_ID_PCIE);
+	if (!sriovpos)
+		return;
+
+	sriovpos = pciexp_find_extended_cap(dev, PCIE_EXT_CAP_SRIOV_ID, PCIE_EXT_CAP_OFFSET);
+	if (!sriovpos)
+		return;
+
+	numvfs = pci_read_config16(dev, sriovpos + PCIE_EXT_CAP_SRIOV_TOTAL_VFS);
+	printk(BIOS_DEBUG, "%s: supports %d SR-IOV VFs\n", dev_path(dev), numvfs);
+
+	/* The spec allows this to be 0 for some reason.  Nothing to do. */
+	if (numvfs == 0)
+		return;
+
+	for (int off = 0; off < 6; off++) {
+		unsigned long res_ix = sriovpos + PCIE_EXT_CAP_SRIOV_VF_BAR0 + off * 4;
+		struct resource *resource;
+
+		resource = pci_get_resource(dev, res_ix);
+
+		/* VF BARs aren't necessarily contiguous, skip the unused ones */
+		if (resource->size == 0)
+			continue;
+
+		printk(BIOS_DEBUG, "%s: found %dbit SR-IOV BAR, size 0x%llx @ index %lx\n",
+			dev_path(dev), (resource->flags & IORESOURCE_PCI64) ? 64 : 32,
+			resource->size,	resource->index);
+
+		if (resource->flags & IORESOURCE_PCI64)
+			off++;
+
+		/*
+		 * SR-IOV BARs break the resource allocator assumption for PCI
+		 * dev resources that size = gran = alignment.
+		 *
+		 * alignment = gran = pci_get_resource() result, but...
+		 * size is pci_get_resource()->size * numvfs, and there's no
+		 * power of two guarantee on size either since numvfs is just
+		 * an integer.
+		 *
+		 * Rather than add code to handle this as a special case in the
+		 * resource allocator, just round up the size.  In practice
+		 * MaxVfs tends to be 2^n or 2^n - 1, so the holes produced
+		 * should only be the size of a single VF BAR
+		 */
+		for (i = 1; i < numvfs; i <<= 1) {
+			resource->size <<= 1;
+			resource->align += 1;
+			resource->gran += 1;
+		}
+
+		if (resource->size >= 16 * MiB)
+			resource->flags |= IORESOURCE_ABOVE_4G;
+
+		if ((i != numvfs) && ((i-1) != numvfs)) {
+			printk(BIOS_DEBUG, "%s: VFs != 2^n or VFs != (2^n)-1, wasting MMIO space...\n",
+				dev_path(dev));
+		}
+	}
+
+	compact_resources(dev);
+}
+
 void pciexp_scan_bus(struct bus *bus, unsigned int min_devfn,
 			     unsigned int max_devfn)
 {
diff --git a/src/include/device/pciexp.h b/src/include/device/pciexp.h
index 2618c02f32..2afa813bb2 100644
--- a/src/include/device/pciexp.h
+++ b/src/include/device/pciexp.h
@@ -22,6 +22,8 @@ enum aspm_type {
 /* Latency tolerance reporting, max snoop latency value 3.14ms */
 #define PCIE_LTR_MAX_SNOOP_LATENCY_3146US 0x1003
 
+void pciexp_dev_read_resources(struct device *dev);
+
 void pciexp_scan_bus(struct bus *bus, unsigned int min_devfn,
 			     unsigned int max_devfn);
 

From 508d910ed4b8072d903ecc35504e863946fdb312 Mon Sep 17 00:00:00 2001
From: Yu-Ping Wu <yupingso@chromium.org>
Date: Tue, 27 May 2025 14:40:24 +0800
Subject: [PATCH 1155/3886] libpayload/arch/mock: Select ARCH_HAS_NDELAY for
 ARCH_MOCK

Unit tests should always use a mock ndelay() defined within each test.
Therefore, select ARCH_HAS_NDELAY for ARCH_MOCK.

Change-Id: I2680e37034d4d13058b3e778d72e63fc6ed18313
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87855
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
---
 payloads/libpayload/arch/mock/Kconfig         | 1 +
 payloads/libpayload/tests/drivers/Makefile.mk | 1 -
 2 files changed, 1 insertion(+), 1 deletion(-)

diff --git a/payloads/libpayload/arch/mock/Kconfig b/payloads/libpayload/arch/mock/Kconfig
index 030f310337..81794ea74b 100644
--- a/payloads/libpayload/arch/mock/Kconfig
+++ b/payloads/libpayload/arch/mock/Kconfig
@@ -3,6 +3,7 @@
 config ARCH_MOCK
 	select LITTLE_ENDIAN if !ARCH_MOCK_BIG_ENDIAN
 	select BIG_ENDIAN if ARCH_MOCK_BIG_ENDIAN
+	select ARCH_HAS_NDELAY
 
 if ARCH_MOCK
 
diff --git a/payloads/libpayload/tests/drivers/Makefile.mk b/payloads/libpayload/tests/drivers/Makefile.mk
index f898278a3a..087043dcd6 100644
--- a/payloads/libpayload/tests/drivers/Makefile.mk
+++ b/payloads/libpayload/tests/drivers/Makefile.mk
@@ -8,4 +8,3 @@ graphics-test-srcs += libc/fpmath.c
 speaker-test-srcs += tests/drivers/speaker-test.c
 speaker-test-mocks += inb
 speaker-test-mocks += outb
-speaker-test-mocks += ndelay

From dcf403e43a5c20b8684801f9b1e01cc6770ab65e Mon Sep 17 00:00:00 2001
From: Wen Zhang <zhangwen6@huaqin.corp-partner.google.com>
Date: Fri, 7 Mar 2025 14:37:05 +0800
Subject: [PATCH 1156/3886] mb/google/skywalker: Configure fingerprint pins

There is no powering-on control in the fingerprint kernel driver.
Follow Rauru to power-on FP MCU in the FW.

BUG=b:401396071
BRANCH=none
TEST=ectool --name=cros_fp version can get the FP FW version.

Signed-off-by: Haikun Zhou <zhouhaikun5@huaqin.corp-partner.google.com>
Change-Id: I20ff175ee4874c4188b7d07ee57330a9275dcb3d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87852
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
---
 src/mainboard/google/skywalker/chromeos.c  | 3 +++
 src/mainboard/google/skywalker/gpio.h      | 3 +++
 src/mainboard/google/skywalker/mainboard.c | 9 +++++++++
 3 files changed, 15 insertions(+)

diff --git a/src/mainboard/google/skywalker/chromeos.c b/src/mainboard/google/skywalker/chromeos.c
index 02abb5f899..c5b9f8ee16 100644
--- a/src/mainboard/google/skywalker/chromeos.c
+++ b/src/mainboard/google/skywalker/chromeos.c
@@ -28,6 +28,9 @@ void setup_chromeos_gpios(void)
 	gpio_output(GPIO_XHCI_INIT_DONE, 0);
 	gpio_output(GPIO_AP_SUSPEND_L, 1);
 	gpio_output(GPIO_AP_HDMI_RST_ODL, 0);
+	gpio_output(GPIO_AP_FP_FW_UP_STRAP, 0);
+	gpio_output(GPIO_EN_PWR_FP, 0);
+	gpio_output(GPIO_FP_RST_1V8_S3_L, 0);
 }
 
 void fill_lb_gpios(struct lb_gpios *gpios)
diff --git a/src/mainboard/google/skywalker/gpio.h b/src/mainboard/google/skywalker/gpio.h
index 5bd8744126..8a1925a635 100644
--- a/src/mainboard/google/skywalker/gpio.h
+++ b/src/mainboard/google/skywalker/gpio.h
@@ -11,6 +11,9 @@
 #define GPIO_AP_EC_WARM_RST_REQ		GPIO(GBE_AUX_PPS0)
 #define GPIO_GSC_AP_INT_ODL		GPIO(GBE_AUX_PPS1)
 #define GPIO_AP_SUSPEND_L		GPIO(CONN_TOP_DATA)
+#define GPIO_FP_RST_1V8_S3_L		GPIO(GBE_RXER)
+#define GPIO_AP_FP_FW_UP_STRAP		GPIO(GBE_TXER)
+#define GPIO_EN_PWR_FP			GPIO(GPIO12)
 #define GPIO_HP_INT_ODL			GPIO(GPIO04)
 #define GPIO_SPKR_INT_ODL		GPIO(GPIO08)
 #define GPIO_SAR_INT_ODL		GPIO(GPIO09)
diff --git a/src/mainboard/google/skywalker/mainboard.c b/src/mainboard/google/skywalker/mainboard.c
index 686fd55e2e..af27c8268c 100644
--- a/src/mainboard/google/skywalker/mainboard.c
+++ b/src/mainboard/google/skywalker/mainboard.c
@@ -1,6 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0-only OR MIT */
 
 #include <device/device.h>
+#include <gpio.h>
 #include <soc/bl31.h>
 #include <soc/dpm_v2.h>
 #include <soc/spm_common.h>
@@ -8,11 +9,19 @@
 
 #include "gpio.h"
 
+static void power_on_fpmcu(void)
+{
+	/* Power on the fingerprint MCU */
+	gpio_output(GPIO_EN_PWR_FP, 1);
+	gpio_output(GPIO_FP_RST_1V8_S3_L, 1);
+}
+
 static void mainboard_init(struct device *dev)
 {
 	dpm_init();
 	setup_usb_host();
 	spm_init();
+	power_on_fpmcu();
 
 	if (CONFIG(ARM64_USE_ARM_TRUSTED_FIRMWARE))
 		register_reset_to_bl31(GPIO_AP_EC_WARM_RST_REQ.id, true);

From 80149f55f7c9fac8fab03c307fbc0a7fc293fd57 Mon Sep 17 00:00:00 2001
From: Vince Liu <vince-wl.liu@mediatek.corp-partner.google.com>
Date: Thu, 10 Apr 2025 13:15:29 +0800
Subject: [PATCH 1157/3886] soc/mediatek/common: Convert spmi_dev_cnt to a
 function

In some SoCs, such as MT8189G/H, different numbers of PMICs are
required. To ensure code reusability and compatibility, it is
necessary to dynamically set this variable. Therefore, spmi_dev_cnt
is changed to a function.

BUG=b:379008996
BRANCH=none
TEST=build passed

Signed-off-by: Vince Liu <vince-wl.liu@mediatek.corp-partner.google.com>
Change-Id: Ib8d6306a81c276dceb021ddadec40803fd85019b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87853
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
---
 src/soc/mediatek/common/include/soc/pmif_spmi.h | 2 +-
 src/soc/mediatek/common/mt6315.c                | 2 +-
 src/soc/mediatek/common/pmif_spmi.c             | 2 +-
 src/soc/mediatek/mt8186/pmif_spmi.c             | 7 +++++--
 src/soc/mediatek/mt8188/pmif_spmi.c             | 7 +++++--
 src/soc/mediatek/mt8189/pmif_spmi.c             | 9 +++++----
 src/soc/mediatek/mt8192/pmif_spmi.c             | 7 +++++--
 src/soc/mediatek/mt8195/pmif_spmi.c             | 7 +++++--
 src/soc/mediatek/mt8196/pmif_spmi.c             | 9 ++++++---
 9 files changed, 34 insertions(+), 18 deletions(-)

diff --git a/src/soc/mediatek/common/include/soc/pmif_spmi.h b/src/soc/mediatek/common/include/soc/pmif_spmi.h
index 8610c54e3b..2160e9edca 100644
--- a/src/soc/mediatek/common/include/soc/pmif_spmi.h
+++ b/src/soc/mediatek/common/include/soc/pmif_spmi.h
@@ -90,10 +90,10 @@ enum {
 #define MT6315_DEFAULT_VALUE_READ 0x15
 
 extern const struct spmi_device spmi_dev[];
-extern const size_t spmi_dev_cnt;
 
 int pmif_spmi_init(struct pmif *arb);
 int spmi_config_master(void);
+size_t spmi_dev_cnt(void);
 void pmif_spmi_iocfg(void);
 void pmif_spmi_config(struct pmif *arb);
 #endif /* __SOC_MEDIATEK_PMIF_SPMI_H__ */
diff --git a/src/soc/mediatek/common/mt6315.c b/src/soc/mediatek/common/mt6315.c
index 35567d1316..a9efb0c975 100644
--- a/src/soc/mediatek/common/mt6315.c
+++ b/src/soc/mediatek/common/mt6315.c
@@ -101,7 +101,7 @@ void mt6315_init(void)
 
 	init_pmif_arb();
 
-	for (i = 0; i < spmi_dev_cnt; i++)
+	for (i = 0; i < spmi_dev_cnt(); i++)
 		mt6315_wdt_enable(spmi_dev[i].slvid);
 
 	mt6315_init_setting();
diff --git a/src/soc/mediatek/common/pmif_spmi.c b/src/soc/mediatek/common/pmif_spmi.c
index e4c4e82daa..b39103aa4a 100644
--- a/src/soc/mediatek/common/pmif_spmi.c
+++ b/src/soc/mediatek/common/pmif_spmi.c
@@ -63,7 +63,7 @@ static int spmi_cali_rd_clock_polarity(struct pmif *pmif_arb)
 		bool success = true;
 		SET32_BITFIELDS(&mtk_spmi_mst->mst_sampl, SAMPL_CK_DLY,
 				cali_data[i].dly, SAMPL_CK_POL, cali_data[i].pol);
-		for (j = 0; j < spmi_dev_cnt; j++) {
+		for (j = 0; j < spmi_dev_cnt(); j++) {
 			if (spmi_read_check(pmif_arb, spmi_dev[j].slvid) != 0) {
 				success = false;
 				break;
diff --git a/src/soc/mediatek/mt8186/pmif_spmi.c b/src/soc/mediatek/mt8186/pmif_spmi.c
index 614985b94d..7a93784c4c 100644
--- a/src/soc/mediatek/mt8186/pmif_spmi.c
+++ b/src/soc/mediatek/mt8186/pmif_spmi.c
@@ -37,8 +37,6 @@ const struct spmi_device spmi_dev[] = {
 	},
 };
 
-const size_t spmi_dev_cnt = ARRAY_SIZE(spmi_dev);
-
 int spmi_config_master(void)
 {
 	/* Software reset */
@@ -59,3 +57,8 @@ int spmi_config_master(void)
 
 	return 0;
 }
+
+size_t spmi_dev_cnt(void)
+{
+	return ARRAY_SIZE(spmi_dev);
+}
diff --git a/src/soc/mediatek/mt8188/pmif_spmi.c b/src/soc/mediatek/mt8188/pmif_spmi.c
index 006f74424f..4167e3e776 100644
--- a/src/soc/mediatek/mt8188/pmif_spmi.c
+++ b/src/soc/mediatek/mt8188/pmif_spmi.c
@@ -38,8 +38,6 @@ const struct spmi_device spmi_dev[] = {
 	},
 };
 
-const size_t spmi_dev_cnt = ARRAY_SIZE(spmi_dev);
-
 int spmi_config_master(void)
 {
 	/* Software reset */
@@ -97,3 +95,8 @@ void pmif_spmi_iocfg(void)
 	SET32_BITFIELDS(&mtk_iocfg_lt->drv_cfg3_clr, SPMI_DRI, 0x07);
 	SET32_BITFIELDS(&mtk_iocfg_lt->drv_cfg3_set, SPMI_DRI, 0x02);
 }
+
+size_t spmi_dev_cnt(void)
+{
+	return ARRAY_SIZE(spmi_dev);
+}
diff --git a/src/soc/mediatek/mt8189/pmif_spmi.c b/src/soc/mediatek/mt8189/pmif_spmi.c
index 1b0005947a..2cc4e114a3 100644
--- a/src/soc/mediatek/mt8189/pmif_spmi.c
+++ b/src/soc/mediatek/mt8189/pmif_spmi.c
@@ -1,7 +1,5 @@
 /* SPDX-License-Identifier: GPL-2.0-only OR MIT */
 
-#include <console/console.h>
-#include <delay.h>
 #include <device/mmio.h>
 #include <gpio.h>
 #include <soc/pll.h>
@@ -20,8 +18,6 @@ const struct spmi_device spmi_dev[] = {
 	},
 };
 
-const size_t spmi_dev_cnt = ARRAY_SIZE(spmi_dev);
-
 int spmi_config_master(void)
 {
 	/* Enable SPMI */
@@ -44,3 +40,8 @@ void pmif_spmi_iocfg(void)
 	gpio_set_driving(GPIO(SPMI_P_SCL), GPIO_DRV_10_MA);
 	gpio_set_driving(GPIO(SPMI_P_SDA), GPIO_DRV_10_MA);
 }
+
+size_t spmi_dev_cnt(void)
+{
+	return ARRAY_SIZE(spmi_dev);
+}
diff --git a/src/soc/mediatek/mt8192/pmif_spmi.c b/src/soc/mediatek/mt8192/pmif_spmi.c
index fb1dad0396..f1dec6d5be 100644
--- a/src/soc/mediatek/mt8192/pmif_spmi.c
+++ b/src/soc/mediatek/mt8192/pmif_spmi.c
@@ -34,8 +34,6 @@ const struct spmi_device spmi_dev[] = {
 	},
 };
 
-const size_t spmi_dev_cnt = ARRAY_SIZE(spmi_dev);
-
 int spmi_config_master(void)
 {
 	/* Software reset */
@@ -81,3 +79,8 @@ void pmif_spmi_iocfg(void)
 {
 	SET32_BITFIELDS(&mtk_iocfg_bm->drv_cfg2, SPMI_SCL, 0x2, SPMI_SDA, 0x2);
 }
+
+size_t spmi_dev_cnt(void)
+{
+	return ARRAY_SIZE(spmi_dev);
+}
diff --git a/src/soc/mediatek/mt8195/pmif_spmi.c b/src/soc/mediatek/mt8195/pmif_spmi.c
index 4d5f06f734..15eaf80921 100644
--- a/src/soc/mediatek/mt8195/pmif_spmi.c
+++ b/src/soc/mediatek/mt8195/pmif_spmi.c
@@ -43,8 +43,6 @@ const struct spmi_device spmi_dev[] = {
 	},
 };
 
-const size_t spmi_dev_cnt = ARRAY_SIZE(spmi_dev);
-
 int spmi_config_master(void)
 {
 	/* Software reset */
@@ -103,3 +101,8 @@ void pmif_spmi_iocfg(void)
 	SET32_BITFIELDS(&mtk_iocfg_bm->drv_cfg3_clr, SPMI_DRI, 0x2D);
 	SET32_BITFIELDS(&mtk_iocfg_bm->drv_cfg3_set, SPMI_DRI, 0x12);
 }
+
+size_t spmi_dev_cnt(void)
+{
+	return ARRAY_SIZE(spmi_dev);
+}
diff --git a/src/soc/mediatek/mt8196/pmif_spmi.c b/src/soc/mediatek/mt8196/pmif_spmi.c
index 665c64c7f6..8baff6ac99 100644
--- a/src/soc/mediatek/mt8196/pmif_spmi.c
+++ b/src/soc/mediatek/mt8196/pmif_spmi.c
@@ -114,8 +114,6 @@ static const uint32_t lat_limit[2][23] = {
 			    0x1e, 0x0, 0x3e6 },
 };
 
-const size_t spmi_dev_cnt = ARRAY_SIZE(spmi_dev);
-
 static struct mtk_spmi_mst_reg *get_mst_reg(struct pmif *arb)
 {
 	if (arb->mstid == SPMI_MASTER_1)
@@ -256,7 +254,7 @@ static int spmi_mst_init(struct pmif *arb)
 	if (pmif_spmi_config_master(arb))
 		return -1;
 
-	for (i = 0; i < spmi_dev_cnt; i++) {
+	for (i = 0; i < spmi_dev_cnt(); i++) {
 		if ((arb->mstid % 2) == spmi_dev[i].mstid) {
 			spmi_cali_rd_clock_polarity(arb, &spmi_dev[i]); /* spmi_cali */
 			spmi_config_slave(arb, &spmi_dev[i]);
@@ -351,3 +349,8 @@ int pmif_spmi_init(struct pmif *arb)
 
 	return 0;
 }
+
+size_t spmi_dev_cnt(void)
+{
+	return ARRAY_SIZE(spmi_dev);
+}

From 04c0527aba2ffcf84c10abca29198ebc1b2ded6d Mon Sep 17 00:00:00 2001
From: Zhigang Qin <zhigang.qin@mediatek.corp-partner.google.com>
Date: Thu, 22 May 2025 20:21:01 +0800
Subject: [PATCH 1158/3886] soc/mediatek/mt8189: Support different PMIC
 soluitons for MT8189(G/H)

The MT8189 chipset comes in two variants: MT8189G and MT8189H. The
MT8189G variant uses a single PMIC IC (MT6315), whereas the MT8189H
variant uses two PMIC ICs. To ensure driver compatibility, we utilize
the CPU ID and segment ID to accurately determine the required number
of SPMIF instances.

BUG=b:379008996
BRANCH=none
TEST=build pass and boot up normally.

Signed-off-by: Zhigang Qin <zhigang.qin@mediatek.corp-partner.google.com>
Change-Id: I07bc21a2026803e76861b27a178d229deca2090a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87854
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
---
 src/soc/mediatek/mt8189/Makefile.mk |  1 +
 src/soc/mediatek/mt8189/pmif_spmi.c | 13 ++++++++++++-
 2 files changed, 13 insertions(+), 1 deletion(-)

diff --git a/src/soc/mediatek/mt8189/Makefile.mk b/src/soc/mediatek/mt8189/Makefile.mk
index 7f9b86834b..32c76cc6d5 100644
--- a/src/soc/mediatek/mt8189/Makefile.mk
+++ b/src/soc/mediatek/mt8189/Makefile.mk
@@ -17,6 +17,7 @@ bootblock-y += ../common/pll.c pll.c
 bootblock-y += ../common/wdt.c ../common/wdt_req.c wdt.c
 
 romstage-y += ../common/cbmem.c
+romstage-y += ../common/cpu_id.c ../common/cpu_segment_id.c
 romstage-y += ../common/dram_init.c
 romstage-y += ../common/dramc_param.c
 romstage-y += ../common/emi.c
diff --git a/src/soc/mediatek/mt8189/pmif_spmi.c b/src/soc/mediatek/mt8189/pmif_spmi.c
index 2cc4e114a3..aeda6e6f71 100644
--- a/src/soc/mediatek/mt8189/pmif_spmi.c
+++ b/src/soc/mediatek/mt8189/pmif_spmi.c
@@ -2,6 +2,7 @@
 
 #include <device/mmio.h>
 #include <gpio.h>
+#include <soc/cpu_id.h>
 #include <soc/pll.h>
 #include <soc/pmif_spmi.h>
 
@@ -43,5 +44,15 @@ void pmif_spmi_iocfg(void)
 
 size_t spmi_dev_cnt(void)
 {
-	return ARRAY_SIZE(spmi_dev);
+	static size_t cached_cnt;
+
+	if (cached_cnt)
+		return cached_cnt;
+
+	cached_cnt = ARRAY_SIZE(spmi_dev);
+	if (get_cpu_id() == MTK_CPU_ID_MT8189 &&
+	    get_cpu_segment_id() == MTK_CPU_SEG_ID_MT8189G)
+		cached_cnt = 1;
+
+	return cached_cnt;
 }

From 47133a716d70a15a39a550d406e2c1381c0edcf8 Mon Sep 17 00:00:00 2001
From: Zhaoxiong Lv <lvzhaoxiong@huaqin.corp-partner.google.com>
Date: Fri, 16 May 2025 14:51:55 +0800
Subject: [PATCH 1159/3886] mb/google/trulo/var/pujjocento: Add P-sensor
 support

Apply DRIVERS_I2C_SX9324
Apply DRIVERS_I2C_SX9324_SUPPORT_LEGACY_LINUX_DRIVER

GPIO changes:
GPP_B7	==>	I2C_P_SENSOR_SDA
GPP_B8	==>	I2C_P_SENSOR_SCL
GPP_H19	==>	P_SENSOR_INT_L

BUG=b:417176908
TEST=Build and verify on pujjocento

Device list:
cat /sys/bus/iio/devices/iio\:device0/name
sx9324

The value of register 01 when away:
i2cget -f -y 13 0x28 01
0x00

The value of register 01 when approaching:
i2cget -f -y 13 0x28 01
0x01

Change-Id: Ie5543f592876c1ebfbb39049f00fe7fe171c8e2f
Signed-off-by: Zhaoxiong Lv <lvzhaoxiong@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87743
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
---
 src/mainboard/google/brya/Kconfig             |  2 +
 .../google/brya/variants/pujjocento/gpio.c    |  4 +-
 .../brya/variants/pujjocento/overridetree.cb  | 75 ++++++++++++++++++-
 3 files changed, 78 insertions(+), 3 deletions(-)

diff --git a/src/mainboard/google/brya/Kconfig b/src/mainboard/google/brya/Kconfig
index 59895cc839..a02f06f48d 100644
--- a/src/mainboard/google/brya/Kconfig
+++ b/src/mainboard/google/brya/Kconfig
@@ -516,6 +516,8 @@ config BOARD_GOOGLE_PUJJONIRU
 
 config BOARD_GOOGLE_PUJJOCENTO
 	select BOARD_GOOGLE_BASEBOARD_TRULO
+	select DRIVERS_I2C_SX9324
+	select DRIVERS_I2C_SX9324_SUPPORT_LEGACY_LINUX_DRIVER
 	select MAINBOARD_HAS_GOOGLE_STRAUSS_KEYBOARD
 	select SOC_INTEL_COMMON_BLOCK_HDA_VERB
 	select SOC_INTEL_TCSS_USE_PDC_PMC_USBC_MUX_CONFIGURATION
diff --git a/src/mainboard/google/brya/variants/pujjocento/gpio.c b/src/mainboard/google/brya/variants/pujjocento/gpio.c
index efa8249e88..ea8d9bbe2d 100644
--- a/src/mainboard/google/brya/variants/pujjocento/gpio.c
+++ b/src/mainboard/google/brya/variants/pujjocento/gpio.c
@@ -66,9 +66,9 @@ static const struct pad_config gpio_table[] = {
 	/* B6  : GPP_B6 ==> ISH_I2C0_SENSOR_SDA */
 	PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_B6, NONE, DEEP, NF1),
 	/* B7  : I2C3_SDA ==> SOC_I2C_SAR_SDA */
-	PAD_CFG_NF_LOCK(GPP_B7, NONE, NF2, LOCK_CONFIG),
+	PAD_CFG_NF(GPP_B7, NONE, DEEP, NF2),
 	/* B8  : I2C3_SCL ==> SOC_I2C_SAR_SCL */
-	PAD_CFG_NF_LOCK(GPP_B8, NONE, NF2, LOCK_CONFIG),
+	PAD_CFG_NF(GPP_B8, NONE, DEEP, NF2),
 	/* B9  : Not available */
 	PAD_NC(GPP_B9, NONE),
 	/* B10 : Not available */
diff --git a/src/mainboard/google/brya/variants/pujjocento/overridetree.cb b/src/mainboard/google/brya/variants/pujjocento/overridetree.cb
index c3753fac6f..68a7526fb7 100644
--- a/src/mainboard/google/brya/variants/pujjocento/overridetree.cb
+++ b/src/mainboard/google/brya/variants/pujjocento/overridetree.cb
@@ -81,7 +81,7 @@ chip soc/intel/alderlake
 		[PchSerialIoIndexI2C0] = PchSerialIoPci,
 		[PchSerialIoIndexI2C1] = PchSerialIoPci,
 		[PchSerialIoIndexI2C2] = PchSerialIoDisabled,
-		[PchSerialIoIndexI2C3] = PchSerialIoDisabled,
+		[PchSerialIoIndexI2C3] = PchSerialIoPci,
 		[PchSerialIoIndexI2C4] = PchSerialIoDisabled,
 		[PchSerialIoIndexI2C5] = PchSerialIoPci,
 	}"
@@ -109,6 +109,7 @@ chip soc/intel/alderlake
 	#|                   | required to set up a BAR  |
 	#|                   | for TPM communication     |
 	#| I2C1              | Trackpad                  |
+	#| I2C3              | P-sensor                  |
 	#+-------------------+---------------------------+
 	register "common_soc_config" = "{
 		.i2c[0] = {
@@ -130,6 +131,15 @@ chip soc/intel/alderlake
 				.sda_hold = 7,
 			}
 		},
+		.i2c[3] = {
+			.speed = I2C_SPEED_FAST,
+			.speed_config[0] = {
+				.speed = I2C_SPEED_FAST,
+				.scl_lcnt = 158,
+				.scl_hcnt = 79,
+				.sda_hold = 7,
+			}
+		},
 		.i2c[5] = {
 			.speed = I2C_SPEED_FAST,
 			.speed_config[0] = {
@@ -539,6 +549,69 @@ chip soc/intel/alderlake
 				device i2c 24 on end
 			end
 		end #I2C1
+		device ref i2c3 on
+			chip drivers/i2c/sx9324
+				register "desc" = ""SAR Proximity Sensor""
+				register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_H19_IRQ)"
+				register "speed" = "I2C_SPEED_FAST"
+				register "uid" = "1"
+				register "reg_irq_cfg0" = "0x00"
+				register "reg_irq_cfg1" = "0x80"
+				register "reg_irq_cfg2" = "0x00"
+				register "reg_gnrl_ctrl0" = "0x16"
+				register "reg_gnrl_ctrl1" = "0x25"
+				register "reg_afe_ctrl0" = "0x20"
+				register "reg_afe_ctrl1" = "0x10"
+				register "reg_afe_ctrl2" = "0x00"
+				register "reg_afe_ctrl3" = "0x00"
+				register "reg_afe_ctrl4" = "0x86"
+				register "reg_afe_ctrl5" = "0x00"
+				register "reg_afe_ctrl6" = "0x00"
+				register "reg_afe_ctrl7" = "0x86"
+				register "reg_afe_ctrl8" = "0x12"
+				register "reg_afe_ctrl9" = "0x0F"
+				register "reg_prox_ctrl0" = "0x09"
+				register "reg_prox_ctrl1" = "0x09"
+				register "reg_prox_ctrl2" = "0x20"
+				register "reg_prox_ctrl3" = "0x60"
+				register "reg_prox_ctrl4" = "0x0c"
+				register "reg_prox_ctrl5" = "0x00"
+				register "reg_prox_ctrl6" = "0x2C"
+				register "reg_prox_ctrl7" = "0xFF"
+				register "reg_adv_ctrl0" = "0x00"
+				register "reg_adv_ctrl1" = "0x00"
+				register "reg_adv_ctrl2" = "0x04"
+				register "reg_adv_ctrl3" = "0x00"
+				register "reg_adv_ctrl4" = "0x00"
+				register "reg_adv_ctrl5" = "0x05"
+				register "reg_adv_ctrl6" = "0x00"
+				register "reg_adv_ctrl7" = "0x00"
+				register "reg_adv_ctrl8" = "0x00"
+				register "reg_adv_ctrl9" = "0x00"
+				register "reg_adv_ctrl10" = "0x00"
+				register "reg_adv_ctrl11" = "0x00"
+				register "reg_adv_ctrl12" = "0x00"
+				register "reg_adv_ctrl16" = "0x00"
+				register "reg_adv_ctrl17" = "0x00"
+				register "reg_adv_ctrl18" = "0x00"
+
+				register "ph0_pin" = "{3, 1, 3}"
+				register "ph1_pin" = "{1, 3, 3}"
+				register "ph2_pin" = "{3, 3, 1}"
+				register "ph3_pin" = "{3, 3, 3}"
+				register "ph01_resolution" = "512"
+				register "ph23_resolution" = "512"
+				register "startup_sensor" = "1"
+				register "ph01_proxraw_strength" = "1"
+				register "ph23_proxraw_strength" = "1"
+				register "avg_pos_strength" = "256"
+				register "cs_idle_sleep" = ""gnd""
+				register "int_comp_resistor" = ""lowest""
+				register "input_precharge_resistor_ohms" = "4000"
+				register "input_analog_gain" = "3"
+				device i2c 28 on end
+			end
+		end
 		device ref i2c5 on
 			chip drivers/i2c/hid
 				register "generic.hid" = ""FTCS1000""

From aea05e51a7c4ed7d0eadd103e3dcb8ca6493b9bf Mon Sep 17 00:00:00 2001
From: Zhaoxiong Lv <lvzhaoxiong@huaqin.corp-partner.google.com>
Date: Mon, 26 May 2025 09:48:38 +0800
Subject: [PATCH 1160/3886] mb/google/trulo/var/pujjocento: Enable WWAN
 function

WWAN_FCPO == GPP_D6
WWAN_RST == GPP_E17
spec reuqest: 0 < toff <10ms

LTE is controlled by bits 14 and 15 in fw_config, and P sensor
and LTE modules exist at the same time, so we use the same bit
to control whether to load the driver.

BUG=b:419325064,b:417105553
TEST=Confirm the measured WWAN power sequence

Change-Id: Ia978aef2cc721b65618ac78c13930447d1557797
Signed-off-by: Zhaoxiong Lv <lvzhaoxiong@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87841
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/google/brya/Kconfig                      |  1 +
 .../brya/variants/pujjocento/include/variant/gpio.h    |  3 ++-
 .../google/brya/variants/pujjocento/overridetree.cb    | 10 +++++++++-
 3 files changed, 12 insertions(+), 2 deletions(-)

diff --git a/src/mainboard/google/brya/Kconfig b/src/mainboard/google/brya/Kconfig
index a02f06f48d..7da805504f 100644
--- a/src/mainboard/google/brya/Kconfig
+++ b/src/mainboard/google/brya/Kconfig
@@ -518,6 +518,7 @@ config BOARD_GOOGLE_PUJJOCENTO
 	select BOARD_GOOGLE_BASEBOARD_TRULO
 	select DRIVERS_I2C_SX9324
 	select DRIVERS_I2C_SX9324_SUPPORT_LEGACY_LINUX_DRIVER
+	select HAVE_WWAN_POWER_SEQUENCE
 	select MAINBOARD_HAS_GOOGLE_STRAUSS_KEYBOARD
 	select SOC_INTEL_COMMON_BLOCK_HDA_VERB
 	select SOC_INTEL_TCSS_USE_PDC_PMC_USBC_MUX_CONFIGURATION
diff --git a/src/mainboard/google/brya/variants/pujjocento/include/variant/gpio.h b/src/mainboard/google/brya/variants/pujjocento/include/variant/gpio.h
index be080eb46e..66cfef0274 100644
--- a/src/mainboard/google/brya/variants/pujjocento/include/variant/gpio.h
+++ b/src/mainboard/google/brya/variants/pujjocento/include/variant/gpio.h
@@ -5,7 +5,8 @@
 
 #include <baseboard/gpio.h>
 
+#define WWAN_FCPO	GPP_D6 /* FULL_CARD_POWER_OFF# */
 #define WWAN_RST	GPP_E17
-#define T2_OFF_MS	20
+#define T2_OFF_MS	5      /*spec request: 0 < t_off < 10ms*/
 #define SLP_S0_HDMI_EN	GPP_A7
 #endif
diff --git a/src/mainboard/google/brya/variants/pujjocento/overridetree.cb b/src/mainboard/google/brya/variants/pujjocento/overridetree.cb
index 68a7526fb7..9c913d2ae4 100644
--- a/src/mainboard/google/brya/variants/pujjocento/overridetree.cb
+++ b/src/mainboard/google/brya/variants/pujjocento/overridetree.cb
@@ -13,6 +13,11 @@ fw_config
 		option PDC_RTS_BYPASS		1
 		option PDC_TI_BYPASS		2
 	end
+	field LTE 14 15
+		option LTE_ABSENT		0
+		option LTE_PRESENT_101		1
+		option LTE_PRESENT_135		2
+	end
 end
 
 chip soc/intel/alderlake
@@ -609,7 +614,10 @@ chip soc/intel/alderlake
 				register "int_comp_resistor" = ""lowest""
 				register "input_precharge_resistor_ohms" = "4000"
 				register "input_analog_gain" = "3"
-				device i2c 28 on end
+				device i2c 28 on
+					probe LTE LTE_PRESENT_101
+					probe LTE LTE_PRESENT_135
+				end
 			end
 		end
 		device ref i2c5 on

From 91ebbb8d3582c4883d1ab3a56e3fbd858a12bc38 Mon Sep 17 00:00:00 2001
From: Luca Lai <luca.lai@lcfc.corp-partner.google.com>
Date: Mon, 26 May 2025 22:00:57 +0800
Subject: [PATCH 1161/3886] mb/trulo/var/pujjolo: Modify pujjolo variant

Modify pujjolo vairant codes for type-c port1 display, parade
touch screen, especially for gpio to fit Trulo. Follow the setting of pujjocento.

BUG=b:395763555
BRANCH=none
TEST=Build and boot to pujjolo. Verify functions work.

Change-Id: I285cd33de6e18a2ffb30eb6401c03f6a4b20dc4a
Signed-off-by: Luca Lai <luca.lai@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87843
Reviewed-by: Talal Sadak <tsadak@google.com>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 .../google/brya/variants/pujjolo/Makefile.mk  |   4 +-
 .../google/brya/variants/pujjolo/gpio.c       | 373 +++++++++++++++---
 .../google/brya/variants/pujjolo/memory.c     | 111 ++++++
 .../brya/variants/pujjolo/overridetree.cb     |  55 ++-
 4 files changed, 477 insertions(+), 66 deletions(-)
 create mode 100644 src/mainboard/google/brya/variants/pujjolo/memory.c

diff --git a/src/mainboard/google/brya/variants/pujjolo/Makefile.mk b/src/mainboard/google/brya/variants/pujjolo/Makefile.mk
index 902b65c59d..98cf9a8419 100644
--- a/src/mainboard/google/brya/variants/pujjolo/Makefile.mk
+++ b/src/mainboard/google/brya/variants/pujjolo/Makefile.mk
@@ -2,8 +2,8 @@
 bootblock-y += gpio.c
 
 romstage-y += gpio.c
+romstage-y += memory.c
+
 ramstage-y += gpio.c
-
 ramstage-y += variant.c
-
 ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_HDA_VERB) += hda_verb.c
diff --git a/src/mainboard/google/brya/variants/pujjolo/gpio.c b/src/mainboard/google/brya/variants/pujjolo/gpio.c
index 8d60e59cb2..017407c0c2 100644
--- a/src/mainboard/google/brya/variants/pujjolo/gpio.c
+++ b/src/mainboard/google/brya/variants/pujjolo/gpio.c
@@ -8,68 +8,138 @@
 
 /* Pad configuration in ramstage for Pujjolo */
 static const struct pad_config override_gpio_table[] = {
-	/* E17 : WWAN_RST_L */
-	PAD_CFG_GPO_LOCK(GPP_E17, 1, LOCK_CONFIG),
-	/* A7  : SLP_S0_GATE */
+	/* A0 thru A4, A9 and A10 come configured out of reset, do not touch */
+	/* A0  : ESPI_IO0 ==> ESPI_SOC_D0_EC */
+	/* A1  : ESPI_IO1 ==> ESPI_SOC_D1_EC */
+	/* A2  : ESPI_IO2 ==> ESPI_SOC_D2_EC */
+	/* A3  : ESPI_IO3 ==> ESPI_SOC_D3_EC */
+	/* A4  : ESPI_CS0# ==> ESPI_SOC_CS_EC_L */
+	/* A5  : ESPI_ALERT0# ==> NC */
+	PAD_NC(GPP_A5, NONE),
+	/* A6  : ESPI_ALERT1# ==> NC */
+	PAD_NC(GPP_A6, NONE),
+	/* A7  : NC ==> SLP_S0_GATE_R */
 	PAD_CFG_GPO(GPP_A7, 1, DEEP),
-	/* A8  : WWAN_RF_DISABLE_ODL */
+	/* A8  : GPP_A8 ==> WWAN_RF_DISABLE_ODL */
 	PAD_CFG_GPO(GPP_A8, 1, DEEP),
+	/* A9  : ESPI_CLK ==> ESPI_SOC_CLK */
+	/* A10 : ESPI_RESET# ==> ESPI_SOC_RST_EC_L */
 	/* A11 : EN_SPK_PA ==> NC */
 	PAD_NC(GPP_A11, NONE),
-	/* A12 : NC# ==> SOC_PEN_DETECT_ODL */
-	PAD_CFG_GPI_SCI_HIGH(GPP_A12, NONE, PLTRST, EDGE_SINGLE),
+	/* A12 : SOC_PEN_DETECT_ODL */
+	PAD_CFG_GPI_SCI_HIGH(GPP_A12, NONE, PLTRST, EDGE_BOTH),
 	/* A13 : GPP_A13 ==> GSC_SOC_INT_ODL */
 	PAD_CFG_GPI_APIC(GPP_A13, NONE, PLTRST, LEVEL, INVERT),
-	/* A18 : DDSP_HPDB ==> DDI2_HPD */
+	/* A14 : USB_OC1# */
+	PAD_CFG_NF(GPP_A14, NONE, DEEP, NF1),
+	/* A15 : USB_OC2# */
+	PAD_CFG_NF(GPP_A15, NONE, DEEP, NF1),
+	/* A16 : USB_OC3# ==> NC */
+	PAD_NC_LOCK(GPP_A16, NONE, LOCK_CONFIG),
+	/* A17 : NC */
+	PAD_NC(GPP_A17, NONE),
+	/* A18 : NC ==> HDMI_HPD_SRC*/
+	PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1),
 	/* A19 : NC */
 	PAD_NC(GPP_A19, NONE),
-	PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1),
-	/* A20  : HDMI_HPD */
+	/* A20 : DDSP_HPD2 ==> NC */
 	PAD_NC(GPP_A20, NONE),
-	/* A21 : USB_C1_AUX_DC_P */
+	/* A21 : GPP_A21 ==> USB_C1_AUX_DC_P */
 	PAD_CFG_NF(GPP_A21, NONE, DEEP, NF6),
-	/* A22 : USB_C1_AUX_DC_N */
+	/* A22 : GPP_A22 ==> USB_C1_AUX_DC_N */
 	PAD_CFG_NF(GPP_A22, NONE, DEEP, NF6),
-	/* A23 :  NC */
+	/* A23 : GPP_A23 ==> NC */
 	PAD_NC(GPP_A23, NONE),
+	/* B0  : CORE_VID0 ==> VCCIN_AUX_VID0 */
+	PAD_CFG_NF(GPP_B0, NONE, DEEP, NF1),
+	/* B1  : CORE_VID1 ==> VCCIN_AUX_VID1 */
+	PAD_CFG_NF(GPP_B1, NONE, DEEP, NF1),
 	/* B2  : NC */
 	PAD_NC(GPP_B2, NONE),
-	/* B5  : SOC_I2C_SUB_SDA */
-	PAD_CFG_NF(GPP_B5, NONE, DEEP, NF2),
-	/* B6  : SOC_I2C_SUB_SCL */
-	PAD_CFG_NF(GPP_B6, NONE, DEEP, NF2),
-	/* D6  : SRCCLKREQ1# ==> WWAN_EN */
-	PAD_CFG_GPO(GPP_D6, 1, DEEP),
+	/* B3  : CPU_GP2 ==> GYRO_SENSOR_INT */
+	PAD_CFG_GPI_APIC(GPP_B3, NONE, PWROK, LEVEL, INVERT),
+	/* B4  : PROC_GP3 ==> ACC_SENSOR_INT */
+	PAD_CFG_GPI_APIC(GPP_B4, NONE, PWROK, LEVEL, INVERT),
+	/* B5  : GPP_B5 ==> ISH_I2C0_SENSOR_SCL */
+	PAD_CFG_NF(GPP_B5, NONE, DEEP, NF1),
+	/* B6  : GPP_B6 ==> ISH_I2C0_SENSOR_SDA */
+	PAD_CFG_NF(GPP_B6, NONE, DEEP, NF1),
 	/* B7  : GPP_B7 ==> NC */
-	PAD_NC_LOCK(GPP_B7, NONE, LOCK_CONFIG),
+	PAD_CFG_NF(GPP_B7, NONE, DEEP, NF2),
 	/* B8  : WWAN_SAR_DETECT_2_ODL */
-	PAD_NC_LOCK(GPP_B8, NONE, LOCK_CONFIG),
-	/* B11 : SOC_PMC_PD0_INT_ODL */
+	PAD_CFG_NF(GPP_B8, NONE, DEEP, NF2),
+	/* B9  : Not available */
+	PAD_NC(GPP_B9, NONE),
+	/* B10 : Not available */
+	PAD_NC(GPP_B10, NONE),
+	/* B11 : SOC_PD0_INT# */
 	PAD_CFG_NF(GPP_B11, NONE, DEEP, NF1),
-	/* B16  : GPP_B16 ==> I2C_5_SDA */
+	/* B12 : SLP_S0# ==> PM_SLP_S0# */
+	PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1),
+	/* B13 : PLTRST# ==> PLT_RST_L */
+	PAD_CFG_NF_LOCK(GPP_B13, NONE, NF1, LOCK_CONFIG),
+	/* B14 : ACZ_SPKR */
+	PAD_CFG_NF(GPP_B14, NONE, DEEP, NF1),
+	/* B15 : NC */
+	PAD_NC_LOCK(GPP_B15, NONE, LOCK_CONFIG),
+	/* B16  : GPP_B16 ==> I2C_TOUCHPAD_SDA */
 	PAD_CFG_NF_LOCK(GPP_B16, NONE, NF2, LOCK_CONFIG),
-	/* B17  : GPP_B17 ==> I2C_5_SCL */
+	/* B17  : GPP_B17 ==> I2C_TOUCHPAD_SCL */
 	PAD_CFG_NF_LOCK(GPP_B17, NONE, NF2, LOCK_CONFIG),
-	/* C1  : SMBDATA ==> USI_RST_L */
+	/* B18 : GPP_B18 ==> GPP_B18_STRAP */
+	PAD_NC(GPP_B18, NONE),
+	/* B19 : Not available */
+	PAD_NC(GPP_B19, NONE),
+	/* B20 : Not available */
+	PAD_NC(GPP_B20, NONE),
+	/* B21 : Not available */
+	PAD_NC(GPP_B21, NONE),
+	/* B22 : Not available */
+	PAD_NC(GPP_B22, NONE),
+	/* B23 : SML1ALERT# ==> PCHHOT_ODL_STRAP */
+	PAD_NC(GPP_B23, NONE),
+	/* C0  : SMBCLK ==> EN_PP3300_TCHSCR_X */
+	PAD_CFG_GPO(GPP_C0, 1, DEEP),
+	/* C1  : SMBDATA ==> TCHSCR_RST_L */
 	PAD_CFG_GPO(GPP_C1, 1, DEEP),
+	/* C2  : SMBALERT# ==> GPP_C2_STRAP */
+	PAD_NC(GPP_C2, NONE),
+	/* C3  : EN_PP3300_UCAM_X */
+	PAD_CFG_GPO_LOCK(GPP_C3, 1, LOCK_CONFIG),
 	/* C4  : TCHSCR_REPORT_EN */
 	PAD_CFG_GPO(GPP_C4, 0, DEEP),
-	/* C6  : I2C_SOC_PMC_PD_SCL */
+	/* C5  : SML0ALERT# ==> GPP_C5_STRAP */
+	PAD_NC(GPP_C5, NONE),
+	/* C6  : SML1_SMBCLK */
 	PAD_CFG_NF(GPP_C6, NONE, DEEP, NF1),
-	/* C7  : I2C_SOC_PMC_PD_SDA */
+	/* C7  : SML1_SMBDATA */
 	PAD_CFG_NF(GPP_C7, NONE, DEEP, NF1),
-	/* D1  : SEN_MODE2_EC_ISH_INT_ODL */
-	PAD_CFG_NF(GPP_D1, NONE, DEEP, NF1),
 	/* D0  : ISH_GP0 ==> PCH_FP_BOOT0 */
 	PAD_CFG_GPO_LOCK(GPP_D0, 0, LOCK_CONFIG),
-	/* E7  : NC ==> FP_RST_ODL */
-	PAD_CFG_GPO_LOCK(GPP_E7, 1, LOCK_CONFIG),
-	/* D2 : NC ==> EN_FP_PWR */
-	PAD_CFG_GPO_LOCK(GPP_D2, 1, LOCK_CONFIG),
-	/* D3  : WCAM_RST_L ==> NC */
+	/* D1  : ISH_GP1 ==> SOC_GSEN2_INT# */
+	PAD_CFG_NF(GPP_D1, NONE, DEEP, NF1),
+	/* D2  : NC */
+	PAD_NC_LOCK(GPP_D2, NONE, LOCK_CONFIG),
+	/* D3  : ISH_GP3 ==> WCAM_RST_L */
 	PAD_CFG_GPO_LOCK(GPP_D3, 0, LOCK_CONFIG),
-	/* D5  : SRCCLKREQ2# ==> WWAN_CLKREQ_ODL */
-	//PAD_CFG_NF(GPP_D5, NONE, DEEP, NF1),
+	/* D4  : IMGCLKOUT0 ==> BT_DISABLE_L */
+	PAD_CFG_GPO(GPP_D4, 1, DEEP),
+	/* D5  : NC */
+	PAD_NC(GPP_D5, NONE),
+	/* D6  : SRCCLKREQ1# ==> WWAN_EN */
+	PAD_CFG_GPO(GPP_D6, 1, DEEP),
+	/* D7  : SRCCLKREQ2# ==> WLAN_CLKREQ_ODL */
+	PAD_CFG_NF(GPP_D7, NONE, DEEP, NF1),
+	/* D8  : SRCCLKREQ3# ==> NC */
+	PAD_NC_LOCK(GPP_D8, NONE, LOCK_CONFIG),
+	/* D9  : NC */
+	PAD_NC_LOCK(GPP_D9, NONE, LOCK_CONFIG),
+	/* D10 : ISH_SPI_CLK ==> GPP_D10_STRAP */
+	PAD_NC_LOCK(GPP_D10, NONE, LOCK_CONFIG),
+	/* D11 : NC */
+	PAD_NC_LOCK(GPP_D11, NONE, LOCK_CONFIG),
+	/* D12 : ISH_SPI_MOSI ==> GPP_D12_STRAP */
+	PAD_NC_LOCK(GPP_D12, NONE, LOCK_CONFIG),
 	/* D13 : UART0_ISH_RX_DBG_TX */
 	PAD_CFG_NF(GPP_D13, NONE, DEEP, NF1),
 	/* D14 : UART0_ISH_TX_DBG_RX */
@@ -82,54 +152,152 @@ static const struct pad_config override_gpio_table[] = {
 	PAD_CFG_NF(GPP_D17, NONE, DEEP, NF1),
 	/* D18  : NC ==> UART_AP_TX_FP_RX */
 	PAD_CFG_NF(GPP_D18, NONE, DEEP, NF1),
-	/* D19 : NC */
+	/* D19 : WWAN_SAR_DETECT_2_ODL ==> NC */
 	PAD_NC(GPP_D19, NONE),
-	/* E0 : NC ==> SOC_PEN_DETECT_R_ODL */
+	/* E0  : SOC_PEN_DETECT_R_ODL */
 	PAD_CFG_GPI_INT(GPP_E0, NONE, PLTRST, EDGE_BOTH),
+	/* E1  : THC0_SPI1_IO2 ==> MEM_STRAP_0 */
+	PAD_CFG_GPI_LOCK(GPP_E1, NONE, LOCK_CONFIG),
+	/* E2  : THC0_SPI1_IO3 ==> MEM_STRAP_1 */
+	PAD_CFG_GPI_LOCK(GPP_E2, NONE, LOCK_CONFIG),
+	/* E3  : PROC_GP0 ==> MEM_STRAP_2 */
+	PAD_CFG_GPI(GPP_E3, NONE, DEEP),
 	/* E4  : WLAN_WWAN_COEX_1 temp out high*/
 	PAD_CFG_GPO(GPP_E4, 0, DEEP),
 	/* E5  : WLAN_WWAN_COEX_2 temp out high */
 	PAD_CFG_GPO(GPP_E5, 0, DEEP),
-	/* E11  : TCHSCR_INT_ODL */
+	/* E6  : THC0_SPI1_RST# ==> GPP_E6_STRAP */
+	PAD_NC_LOCK(GPP_E6, NONE, LOCK_CONFIG),
+	/* E7  : NC ==> FP_RST_ODL */
+	PAD_CFG_GPO_LOCK(GPP_E7, 1, LOCK_CONFIG),
+	/* E8  : GPP_E8 ==> WLAN_DISABLE_L */
+	PAD_CFG_GPO(GPP_E8, 1, DEEP),
+	/* E9  : NC */
+	PAD_NC_LOCK(GPP_E9, NONE, LOCK_CONFIG),
+	/* E10 : EN_PP3300_WLAN_X */
+	PAD_CFG_GPO(GPP_E10, 0, DEEP),
+	/* E11 : TCHSCR_INT_ODL */
 	PAD_CFG_GPI_APIC(GPP_E11, NONE, PLTRST, LEVEL, INVERT),
-	/* E13 : SD_WAKE_N */
+	/* E12 : THC0_SPI1_IO1 ==> SOC_WP_OD */
+	PAD_CFG_GPI_GPIO_DRIVER_LOCK(GPP_E12, NONE, LOCK_CONFIG),
+	/* E13 : SD_WAKE_N*/
 	PAD_CFG_GPI_LOCK(GPP_E13, NONE, LOCK_CONFIG),
+	/* E14 : DDSP_HPDA ==> EDP_HPD */
+	PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1),
+	/* E15 : NC */
+	PAD_NC(GPP_E15, NONE),
+	/* E16 : NC */
+	PAD_NC(GPP_E16, NONE),
+	/* E17  : WWAN_RST_L */
+	PAD_CFG_GPO_LOCK(GPP_E17, 1, LOCK_CONFIG),
+	/* E18 : NC */
+	PAD_NC(GPP_E18, NONE),
+	/* E19 : DDP1_CTRLDATA ==> GPP_E19_STRAP */
+	PAD_NC(GPP_E19, NONE),
 	/* E20 : DDP2_CTRLCLK ==> HDMI_DDC_SCL */
 	PAD_NC(GPP_E20, NONE),
-	/* E21 : DDP2_CTRLDATA ==> HDMI_DDC_SDA_STRAP */
+	/* E21 : DDP2_CTRLDATA ==> NC */
 	PAD_NC(GPP_E21, NONE),
-	/* E22 : USB_C0_AUX_DC_P */
+	/* E22 : DDPA_CTRLCLK ==> USB_C0_AUX_DC_P */
 	PAD_CFG_NF(GPP_E22, NONE, DEEP, NF6),
-	/* E23 : USB_C0_AUX_DC_N */
+	/* E23 : DDPA_CTRLDATA ==> USB_C0_AUX_DC_N */
 	PAD_CFG_NF(GPP_E23, NONE, DEEP, NF6),
+	/* F0  : CNV_BRI_DT ==> CNV_BRI_DT_STRAP */
+	PAD_CFG_NF(GPP_F0, NONE, DEEP, NF1),
+	/* F1  : CNV_BRI_RSP ==> CNV_BRI_RSP */
+	PAD_CFG_NF(GPP_F1, UP_20K, DEEP, NF1),
+	/* F2  : CNV_RGI_DT ==> CNV_RGI_DT_STRAP */
+	PAD_CFG_NF(GPP_F2, NONE, DEEP, NF1),
+	/* F3  : CNV_RGI_RSP ==> CNV_RGI_RSP */
+	PAD_CFG_NF(GPP_F3, UP_20K, DEEP, NF1),
+	/* F4  : CNV_RF_RESET# ==> CNV_RF_RST_L */
+	PAD_CFG_NF(GPP_F4, NONE, DEEP, NF1),
+	/* F5  : CRF_XTAL_CLKREQ ==> CNV_CLKREQ0 */
+	PAD_CFG_NF(GPP_F5, NONE, DEEP, NF3),
+	/* F6  : CNV_PA_BLANKING ==> WLAN_WWAN_COEX_3 */
+	PAD_CFG_NF(GPP_F6, NONE, DEEP, NF1),
+	/* F7  : GPP_F7 ==> GPP_F7_STRAP */
+	PAD_NC(GPP_F7, NONE),
+	/* F8  : Not available */
+	PAD_NC(GPP_F8, NONE),
+	/* F9  : Not available */
+	PAD_NC(GPP_F9, NONE),
+	/* F10 : GPP_F10 ==> GPP_F10_STRAP */
+	PAD_NC(GPP_F10, NONE),
 	/* F11 : NC ==> GSPI_PCH_CLK_FPMCU */
 	PAD_CFG_NF(GPP_F11, NONE, DEEP, NF4),
 	/* F12 : WWAN_RST_L ==> GSPI_PCH_DO_FPMCU_DI_R */
 	PAD_CFG_NF(GPP_F12, NONE, DEEP, NF4),
 	/* F13 : SOC_PEN_DETECT_R_ODL ==> GSPI_PCH_DI_FPMCU_DO */
 	PAD_CFG_NF(GPP_F13, NONE, DEEP, NF4),
+	/* F14 : GSXDIN ==> TCHPAD_INT_ODL */
+	PAD_CFG_GPI_IRQ_WAKE(GPP_F14, NONE, PWROK, LEVEL, INVERT),
 	/* F15 : SOC_PEN_DETECT_ODL ==> FPMCU_INT_L */
 	PAD_CFG_GPI_IRQ_WAKE(GPP_F15, NONE, PWROK, LEVEL, INVERT),
 	/* F16  : NC ==> GSPI_PCH_CS_FPMCU_R_L */
 	PAD_CFG_NF(GPP_F16, NONE, DEEP, NF4),
-	/* H8 : I2C_1_SDA */
+	/* F17 : THC1_SPI2_RST# ==> EC_SOC_WAKE_ODL */
+	PAD_CFG_GPI_IRQ_WAKE_LOCK(GPP_F17, NONE, EDGE_SINGLE, INVERT, LOCK_CONFIG),
+	/* F18 : THC1_SPI2_INT# ==> EC_IN_RW_OD */
+	PAD_CFG_GPI_LOCK(GPP_F18, NONE, LOCK_CONFIG),
+	/* F19 : Not available */
+	PAD_NC(GPP_F19, NONE),
+	/* F20 : Not available */
+	PAD_NC(GPP_F20, NONE),
+	/* F21 : Not available */
+	PAD_NC(GPP_F21, NONE),
+	/* F22 : NC */
+	PAD_NC(GPP_F22, NONE),
+	/* F23 : V1P05_CTRL ==> V1P05EXT_CTRL */
+	PAD_CFG_NF(GPP_F23, NONE, DEEP, NF1),
+	/* H0  : GPP_H0_STRAP */
+	PAD_NC(GPP_H0, NONE),
+	/* H1  : GPP_H1_STRAP */
+	PAD_NC(GPP_H1, NONE),
+	/* H2  : GPP_H2_STRAP */
+	PAD_NC(GPP_H2, NONE),
+	/* H3  : SX_EXIT_HOLDOFF# ==> WLAN_PCIE_WAKE_ODL */
+	PAD_CFG_GPI_SCI_LOW_LOCK(GPP_H3, NONE, EDGE_SINGLE, LOCK_CONFIG),
+	/* H4  : I2C0_SDA ==> SOC_I2C_GSC_SDA */
+	PAD_CFG_NF_LOCK(GPP_H4, NONE, NF1, LOCK_CONFIG),
+	/* H5  : I2C0_SCL ==> SOC_I2C_GSC_SCL */
+	PAD_CFG_NF_LOCK(GPP_H5, NONE, NF1, LOCK_CONFIG),
+	/* H6  : I2C1_SDA ==> SOC_I2C_TCHSCR_SDA */
+	PAD_CFG_NF(GPP_H6, NONE, DEEP, NF1),
+	/* H7  : I2C1_SCL ==> SOC_I2C_TCHSCR_SCL */
+	PAD_CFG_NF(GPP_H7, NONE, DEEP, NF1),
+	/* H8  : MIPI_WCAM_SDA */
 	PAD_CFG_NF(GPP_H8, NONE, DEEP, NF1),
-	/* H9 : I2C_1_SCL */
+	/* H9  : MIPI_WCAM_SCL */
 	PAD_CFG_NF(GPP_H9, NONE, DEEP, NF1),
-	/* H15  : PD0_SOC_DBG_L */
+	/* H10 : UART0_RXD ==> UART_SOC_RX_DBG_TX */
+	PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2),
+	/* H11 : UART0_TXD ==> UART_SOC_TX_DBG_RX */
+	PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2),
+	/* H12 : GPP_H12 ==> NC */
+	PAD_NC_LOCK(GPP_H12, NONE, LOCK_CONFIG),
+	/* H13 : GPP_H13 ==> NC */
+	PAD_NC_LOCK(GPP_H13, NONE, LOCK_CONFIG),
+	/* H14 : Not available */
+	PAD_NC(GPP_H14, NONE),
+	/* H15 : DDPB_CTRLCLK ==> HDMI_DDC_SCL */
 	PAD_CFG_NF(GPP_H15, NONE, DEEP, NF1),
-	//PAD_CFG_GPI_LOCK(GPP_H15, NONE, LOCK_CONFIG),
-	/* H17  : PD1_SOC_DBG_L*/
-	//PAD_CFG_GPI_LOCK(GPP_H17, NONE, LOCK_CONFIG),
+	/* H16 : Not available */
+	PAD_NC(GPP_H16, NONE),
+	/* H17 : DDPB_CTRLDATA ==> HDMI_DDC_SDA */
 	PAD_CFG_NF(GPP_H17, NONE, DEEP, NF1),
-	/* H18 : CPU_C10_GATE_L */
+	/* H18 : PROC_C10_GATE# ==> CPU_C10_GATE# */
 	PAD_CFG_NF(GPP_H18, NONE, DEEP, NF1),
-	/* H19 : SOC_I2C_SUB_INT_ODL */
+	/* H19 : SAR_INT_L */
 	PAD_CFG_GPI_APIC(GPP_H19, NONE, PLTRST, LEVEL, NONE),
+	/* H20 : IMGCLKOUT1 ==> WLAN_PERST_L */
+	PAD_CFG_GPO(GPP_H20, 1, DEEP),
 	/* H21  : WWAN_PERST_L */
 	PAD_NC_LOCK(GPP_H21, NONE, LOCK_CONFIG),
-	/* H23 : WWAN_SAR_DETECT_ODL ==> NC */
-	PAD_NC_LOCK(GPP_H23, NONE, LOCK_CONFIG),
+	/* H22 : IMGCLKOUT3 ==> WCAM_MCLK_R */
+	PAD_CFG_NF(GPP_H22, NONE, DEEP, NF1),
+	/* H23 : GPP_H23 ==> WWAN_SAR_DETECT_ODL */
+	PAD_CFG_GPO(GPP_H23, 1, DEEP),
 	/* R0  : HDA_HP_BCLK_R */
 	PAD_CFG_NF(GPP_R0, NONE, DEEP, NF1),
 	/* R1  : HDA_HP_SYNC_R */
@@ -146,12 +314,107 @@ static const struct pad_config override_gpio_table[] = {
 	PAD_CFG_NF(GPP_R6, NONE, DEEP, NF3),
 	/* R7 : DMIC_DATA_1A ==> DMIC_WCAM_DATA */
 	PAD_CFG_NF(GPP_R7, NONE, DEEP, NF3),
-	/* S0  : NC */
+	/* S0  : I2S_SPK_BCLK_R ==> NC */
 	PAD_NC(GPP_S0, NONE),
-	/* S1  : NC */
+	/* S1  : I2S_SPK_LRCK_R ==> NC */
 	PAD_NC(GPP_S1, NONE),
-	/* S2 :  NC */
+	/* S2 : DMIC_CKL_A0 ==> NC */
 	PAD_NC(GPP_S2, NONE),
+	/* S3 : DMIC_DATA0 ==> NC */
+	PAD_NC(GPP_S3, NONE),
+	/* S4  : NC */
+	PAD_NC(GPP_S4, NONE),
+	/* S5  : NC */
+	PAD_NC(GPP_S5, NONE),
+	/* S6  : NC */
+	PAD_NC(GPP_S6, NONE),
+	/* S7  : NC */
+	PAD_NC(GPP_S7, NONE),
+	/* I5  : NC */
+	PAD_NC(GPP_I5, NONE),
+	/* I7  : EMMC_CMD ==> NC */
+	PAD_NC(GPP_I7, NONE),
+	/* I8  : EMMC_DATA0 ==> NC */
+	PAD_NC(GPP_I8, NONE),
+	/* I9  : EMMC_DATA1 ==> NC */
+	PAD_NC(GPP_I9, NONE),
+	/* I10 : EMMC_DATA2 ==> NC */
+	PAD_NC(GPP_I10, NONE),
+	/* I11 : EMMC_DATA3 ==> NC */
+	PAD_NC(GPP_I11, NONE),
+	/* I12 : EMMC_DATA4 ==> NC */
+	PAD_NC(GPP_I12, NONE),
+	/* I13 : EMMC_DATA5 ==> NC */
+	PAD_NC(GPP_I13, NONE),
+	/* I14 : EMMC_DATA6 ==> NC */
+	PAD_NC(GPP_I14, NONE),
+	/* I15 : EMMC_DATA7 ==> NC */
+	PAD_NC(GPP_I15, NONE),
+	/* I16 : EMMC_RCLK ==> NC */
+	PAD_NC(GPP_I16, NONE),
+	/* I17 : EMMC_CLK ==> NC */
+	PAD_NC(GPP_I17, NONE),
+	/* I18 : EMMC_RESET# ==> NC */
+	PAD_NC(GPP_I18, NONE),
+	/* GPD0  : BATLOW# ==> SOC_BATLOW_L */
+	PAD_CFG_NF(GPD0, NONE, DEEP, NF1),
+	/* GPD1  : ACPRESENT ==> SOC_ACPRESENT */
+	PAD_CFG_NF(GPD1, NONE, DEEP, NF1),
+	/* GPD2  : EC_SOC_INT_ODL */
+	PAD_CFG_GPI_APIC(GPD2, NONE, PLTRST, LEVEL, INVERT),
+	/* GPD3  : PWRBTN# ==> EC_SOC_PWR_BTN_ODL */
+	PAD_CFG_NF(GPD3, NONE, DEEP, NF1),
+	/* GPD4  : SLP_S3# ==> SLP_S3_L */
+	PAD_CFG_NF(GPD4, NONE, DEEP, NF1),
+	/* GPD5  : SLP_S4# ==> SLP_S4_L */
+	PAD_CFG_NF(GPD5, NONE, DEEP, NF1),
+	/* GPD6  : SLP_A# ==> NC */
+	PAD_NC(GPD6, NONE),
+	/* GPD7  : GPD7_STRAP */
+	PAD_NC(GPD7, NONE),
+	/* GPD8  : SUSCLK ==> PCH_SUSCLK */
+	PAD_CFG_NF(GPD8, NONE, DEEP, NF1),
+	/* GPD9  : NC */
+	PAD_NC(GPD9, NONE),
+	/* GPD10 : SLP_S5# ==> NC */
+	PAD_NC(GPD10, NONE),
+	/* GPD11 : NC */
+	PAD_NC(GPD11, NONE),
+	/* Configure the unused virtual CNVi Bluetooth UART pads to NC mode. */
+	/* vCNV_BT_UART_TXD */
+	PAD_NC(GPP_VGPIO_6, NONE),
+	/* vCNV_BT_UART_RXD */
+	PAD_NC(GPP_VGPIO_7, NONE),
+	/* vCNV_BT_UART_CTS_B */
+	PAD_NC(GPP_VGPIO_8, NONE),
+	/* vCNV_BT_UART_RTS_B */
+	PAD_NC(GPP_VGPIO_9, NONE),
+	/* Configure the unused vUART for Bluetooth pads to NC mode. */
+	/* vUART0_TXD */
+	PAD_NC(GPP_VGPIO_18, NONE),
+	/* vUART0_RXD */
+	PAD_NC(GPP_VGPIO_19, NONE),
+	/* vUART0_CTS_B */
+	PAD_NC(GPP_VGPIO_20, NONE),
+	/* vUART0_RTS_B */
+	PAD_NC(GPP_VGPIO_21, NONE),
+	/* Configure the virtual CNVi Bluetooth I2S GPIO Pads.*/
+	/* BT_I2S_BCLK */
+	PAD_CFG_NF(GPP_VGPIO_30, NONE, DEEP, NF3),
+	/* BT_I2S_SYNC */
+	PAD_CFG_NF(GPP_VGPIO_31, NONE, DEEP, NF3),
+	/* BT_I2S_SDO */
+	PAD_CFG_NF(GPP_VGPIO_32, NONE, DEEP, NF3),
+	/* BT_I2S_SDI */
+	PAD_CFG_NF(GPP_VGPIO_33, NONE, DEEP, NF3),
+	/* SSP2_SCLK */
+	PAD_CFG_NF(GPP_VGPIO_34, NONE, DEEP, NF1),
+	/* SSP2_SFRM */
+	PAD_CFG_NF(GPP_VGPIO_35, NONE, DEEP, NF1),
+	/* SSP_TXD */
+	PAD_CFG_NF(GPP_VGPIO_36, NONE, DEEP, NF1),
+	/* SSP_RXD */
+	PAD_CFG_NF(GPP_VGPIO_37, NONE, DEEP, NF1),
 
 };
 
diff --git a/src/mainboard/google/brya/variants/pujjolo/memory.c b/src/mainboard/google/brya/variants/pujjolo/memory.c
new file mode 100644
index 0000000000..bb80ee15ec
--- /dev/null
+++ b/src/mainboard/google/brya/variants/pujjolo/memory.c
@@ -0,0 +1,111 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <baseboard/variants.h>
+#include <gpio.h>
+#include <soc/romstage.h>
+
+static const struct mb_cfg variant_memcfg = {
+	.type = MEM_TYPE_LP5X,
+
+	.rcomp = {
+		/* Baseboard uses only 100ohm Rcomp resistors */
+		.resistor = 100,
+	},
+
+	/* DQ byte map */
+	.lpx_dq_map = {
+		.ddr0 = {
+			.dq0 = { 12,  9, 10, 11, 14, 13,  8, 15 },
+			.dq1 = {  3,  1,  2,  0,  4,  7,  5,  6 },
+		},
+		.ddr1 = {
+			.dq0 = {  3,  1,  2,  0,  4,  7,  5,  6 },
+			.dq1 = { 13,  9,  8, 11, 10, 14, 15, 12 },
+		},
+		.ddr2 = {
+			.dq0 = {  2,  1,  3,  0,  4,  6,  5,  7 },
+			.dq1 = {  8,  9, 10, 11, 13, 14, 12, 15 },
+		},
+		.ddr3 = {
+			.dq0 = {  3,  0,  1,  2,  5,  6,  4,  7 },
+			.dq1 = { 13,  9, 11,  8, 14, 15, 10, 12 },
+		},
+		.ddr4 = {
+			.dq0 = { 12,  9, 10, 11, 14, 13,  8, 15 },
+			.dq1 = {  3,  1,  2,  0,  4,  7,  5,  6 },
+		},
+		.ddr5 = {
+			.dq0 = {  3,  1,  2,  0,  4,  7,  5,  6 },
+			.dq1 = { 13,  9,  8, 11, 10, 14, 15, 12 },
+		},
+		.ddr6 = {
+			.dq0 = {  2,  1,  3,  0,  4,  6,  5,  7 },
+			.dq1 = {  8,  9, 10, 11, 13, 14, 12, 15 },
+		},
+		.ddr7 = {
+			.dq0 = {  3,  0,  1,  2,  5,  6,  4,  7 },
+			.dq1 = { 13,  9, 11,  8, 14, 15, 10, 12 },
+		},
+	},
+
+	/* DQS CPU<>DRAM map */
+	.lpx_dqs_map = {
+		.ddr0 = { .dqs0 = 1, .dqs1 = 0 },
+		.ddr1 = { .dqs0 = 0, .dqs1 = 1 },
+		.ddr2 = { .dqs0 = 0, .dqs1 = 1 },
+		.ddr3 = { .dqs0 = 0, .dqs1 = 1 },
+		.ddr4 = { .dqs0 = 1, .dqs1 = 0 },
+		.ddr5 = { .dqs0 = 0, .dqs1 = 1 },
+		.ddr6 = { .dqs0 = 0, .dqs1 = 1 },
+		.ddr7 = { .dqs0 = 0, .dqs1 = 1 },
+	},
+
+	.lp5x_config = {
+		.ccc_config = 0xff,
+	},
+
+	.ect = 1, /* Early Command Training */
+
+	.UserBd = BOARD_TYPE_MOBILE,
+};
+
+const struct mb_cfg *variant_memory_params(void)
+{
+	return &variant_memcfg;
+}
+
+int variant_memory_sku(void)
+{
+	/*
+	 * Memory configuration board straps
+	 * GPIO_MEM_CONFIG_0	GPP_E1
+	 * GPIO_MEM_CONFIG_1	GPP_E2
+	 * GPIO_MEM_CONFIG_2	GPP_E3
+	 */
+	gpio_t spd_gpios[] = {
+		GPP_E1,
+		GPP_E2,
+		GPP_E3,
+	};
+
+	return gpio_base2_value(spd_gpios, ARRAY_SIZE(spd_gpios));
+}
+
+bool variant_is_half_populated(void)
+{
+	/*
+	 * Ideally half_populated is used in platforms with multiple channels to
+	 * enable only one half of the channel. Alder Lake N has single channel,
+	 * and it would require for new structures to be defined in meminit block
+	 * driver for LPx memory configurations. In order to avoid adding new
+	 * structures, set half_populated to true. This has the same effect as
+	 * having single channel with 64-bit width.
+	*/
+	return true;
+}
+
+void variant_get_spd_info(struct mem_spd *spd_info)
+{
+	spd_info->topo = MEM_TOPO_MEMORY_DOWN;
+	spd_info->cbfs_index = variant_memory_sku();
+}
diff --git a/src/mainboard/google/brya/variants/pujjolo/overridetree.cb b/src/mainboard/google/brya/variants/pujjolo/overridetree.cb
index 9a3b1a0b46..2f89d72859 100644
--- a/src/mainboard/google/brya/variants/pujjolo/overridetree.cb
+++ b/src/mainboard/google/brya/variants/pujjolo/overridetree.cb
@@ -163,6 +163,23 @@ chip soc/intel/alderlake
 				register "hid_desc_reg_offset" = "0x01"
 				device i2c 5d on end
 			end
+			chip drivers/i2c/hid
+				register "generic.hid" = ""PARA3408""
+				register "generic.desc" = ""Parade Touchscreen""
+				register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_E11_IRQ)"
+				register "generic.detect" = "1"
+				register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C1)"
+				register "generic.reset_delay_ms" = "20"
+				register "generic.reset_off_delay_ms" = "2"
+				register "generic.stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C4)"
+				register "generic.stop_delay_ms" = "280"
+				register "generic.stop_off_delay_ms" = "2"
+				register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C0)"
+				register "generic.enable_delay_ms" = "1"
+				register "generic.has_power_resource" = "1"
+				register "hid_desc_reg_offset" = "0x01"
+				device i2c 24 on end
+			end
 			chip drivers/generic/gpio_keys
 				register "name" = ""PENH""
 				register "gpio" = "ACPI_GPIO_INPUT_ACTIVE_LOW(GPP_E0)"
@@ -287,8 +304,7 @@ chip soc/intel/alderlake
 				register "off_seq.ops[2]" = "SEQ_OPS_GPIO_DISABLE(1, 0)"
 				register "off_seq.ops[3]" = "SEQ_OPS_GPIO_DISABLE(0, 0)"
 
-				device i2c 10 on
-				end
+				device i2c 10 on end
 			end
 			chip drivers/intel/mipi_camera
 				register "acpi_uid" = "3"
@@ -314,8 +330,7 @@ chip soc/intel/alderlake
 				register "off_seq.ops[0]" = "SEQ_OPS_GPIO_DISABLE(1, 0)"
 				register "off_seq.ops[1]" = "SEQ_OPS_GPIO_DISABLE(0, 0)"
 
-				device i2c 0C on
-				end
+				device i2c 0C on end
 			end
 			chip drivers/intel/mipi_camera
 				register "acpi_hid" = "ACPI_DT_NAMESPACE_HID"
@@ -343,8 +358,7 @@ chip soc/intel/alderlake
 				register "nvm_width" = "0x10"
 				register "nvm_compat" = ""atmel,24c08""
 
-				device i2c 50 on
-				end
+				device i2c 50 on end
 			end
 		end
 		device ref i2c5 on
@@ -385,6 +399,25 @@ chip soc/intel/alderlake
 		end
 		device ref ufs on end
 		device ref igpu on
+			chip drivers/gfx/generic
+				register "device_count" = "4"
+				# DDIA for eDP
+				register "device[0].name" = ""LCD0""
+				# Internal panel on the first port of the graphics chip
+				register "device[0].type" = "panel"
+				# DDIB for HDMI
+				# If HDMI is not enumerated in the kernel, then no GFX device should be added for DDIB
+				register "device[1].name" = ""DD01""
+				# TCP0 (DP-1) for port C0
+				register "device[2].name" = ""DD02""
+				register "device[2].use_pld" = "true"
+				register "device[2].pld" = "ACPI_PLD_TYPE_C(LEFT, RIGHT, ACPI_PLD_GROUP(1, 1))"
+				# TCP1 (DP-2) for port C1
+				register "device[3].name" = ""DD03""
+				register "device[3].use_pld" = "true"
+				register "device[3].pld" = "ACPI_PLD_TYPE_C(RIGHT, LEFT, ACPI_PLD_GROUP(2, 1))"
+				device generic 0 on end
+			end
 		end
 		device ref pcie_rp4 on
 			# PCIe 4 WLAN
@@ -416,6 +449,7 @@ chip soc/intel/alderlake
 		device ref pch_espi on
 			chip ec/google/chromeec
 				use conn0 as mux_conn[0]
+				use conn1 as mux_conn[1]
 				device pnp 0c09.0 on end
 			end
 		end
@@ -427,6 +461,11 @@ chip soc/intel/alderlake
 						use tcss_usb3_port1 as usb3_port
 						device generic 0 alias conn0 on end
 					end
+					chip drivers/intel/pmc_mux/conn
+						use usb2_port2 as usb2_port
+						use tcss_usb3_port2 as usb3_port
+						device generic 1 alias conn1 on end
+					end
 				end
 			end
 		end
@@ -475,7 +514,6 @@ chip soc/intel/alderlake
 						register "custom_pld" = "ACPI_PLD_TYPE_A(RIGHT, LEFT, ACPI_PLD_GROUP(4, 1))"
 						device ref usb2_port4 on end
 					end
-
 					chip drivers/usb/acpi
 						register "desc" = ""USB2 WWAN""
 						register "type" = "UPC_TYPE_INTERNAL"
@@ -535,8 +573,7 @@ chip soc/intel/alderlake
 				register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_E7)"
 				register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D2)"
 				register "enable_delay_ms" = "3"
-				device spi 0 on
-				end
+				device spi 0 on end
 			end # FPMCU
 		end
 	end

From ae435c014c48517c0a89e04cac629ad681703e44 Mon Sep 17 00:00:00 2001
From: Mengqi Zhang <mengqi.zhang@mediatek.corp-partner.google.com>
Date: Sun, 22 Dec 2024 16:32:30 +0800
Subject: [PATCH 1162/3886] soc/mediatek/mt8189: Configure and early initialize
 eMMC

Some eMMCs need 80+ms for CMD1 to complete. And the payload may need to
access eMMC in the very early stage (for example, depthcharge needs it
20ms after started) so we have to start initialization in coreboot.

BUG=b:379008996
BRANCH=none
TEST=build pass and run "storage init" in depthcharge shell on MTK EVB
firmware-shell: storage init
*  0: mtk_mmc
1 devices total

Signed-off-by: Mengqi Zhang <mengqi.zhang@mediatek.corp-partner.google.com>
Change-Id: I82f2a155b810a8b9608d70fe0c015e6054d0be00
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87862
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
---
 src/soc/mediatek/mt8189/Makefile.mk           |  1 +
 .../mediatek/mt8189/include/soc/addressmap.h  |  2 +
 src/soc/mediatek/mt8189/msdc.c                | 40 +++++++++++++++++++
 3 files changed, 43 insertions(+)
 create mode 100644 src/soc/mediatek/mt8189/msdc.c

diff --git a/src/soc/mediatek/mt8189/Makefile.mk b/src/soc/mediatek/mt8189/Makefile.mk
index 32c76cc6d5..2890564792 100644
--- a/src/soc/mediatek/mt8189/Makefile.mk
+++ b/src/soc/mediatek/mt8189/Makefile.mk
@@ -38,6 +38,7 @@ ramstage-y += ../common/emi.c
 ramstage-y += ../common/mcu.c mcupm.c
 ramstage-y += ../common/memory.c
 ramstage-y += ../common/mmu_operations.c ../common/mmu_cmops.c
+ramstage-$(CONFIG_COMMONLIB_STORAGE_MMC) += ../common/msdc.c msdc.c
 ramstage-y += ../common/mt6315.c mt6315.c
 ramstage-y += ../common/mt6359p.c mt6359p.c
 ramstage-y += ../common/mtcmos.c mtcmos.c
diff --git a/src/soc/mediatek/mt8189/include/soc/addressmap.h b/src/soc/mediatek/mt8189/include/soc/addressmap.h
index 61999e03b0..5a127f65aa 100644
--- a/src/soc/mediatek/mt8189/include/soc/addressmap.h
+++ b/src/soc/mediatek/mt8189/include/soc/addressmap.h
@@ -58,6 +58,7 @@ enum {
 	PERICFG_AO_BASE			= IO_PHYS + 0x01036000,
 	DEVAPC_PERI_PAR_AO_BASE		= IO_PHYS + 0x0103C000,
 	AUDIO_BASE			= IO_PHYS + 0x01050000,
+	MSDC0_BASE			= IO_PHYS + 0x01230000,
 	SSUSB_IPPC_BASE			= IO_PHYS + 0x01263E00,
 	UFSHCI_BASE			= IO_PHYS + 0x012B0000,
 	UFS0_AO_CFG_BASE		= IO_PHYS + 0x012B8000,
@@ -94,6 +95,7 @@ enum {
 	IMP_IIC_WRAP_S_BASE		= IO_PHYS + 0x01D74000,
 	IOCFG_LT0_BASE			= IO_PHYS + 0x01E20000,
 	IOCFG_LT1_BASE			= IO_PHYS + 0x01E30000,
+	MSDC0_TOP_BASE			= IO_PHYS + 0x01E70000,
 	EFUSEC_BASE			= IO_PHYS + 0x01F10000,
 	IOCFG_RT_BASE			= IO_PHYS + 0x01F20000,
 	IMP_IIC_WRAP_EN_BASE		= IO_PHYS + 0x01F32000,
diff --git a/src/soc/mediatek/mt8189/msdc.c b/src/soc/mediatek/mt8189/msdc.c
new file mode 100644
index 0000000000..1ebb78ef41
--- /dev/null
+++ b/src/soc/mediatek/mt8189/msdc.c
@@ -0,0 +1,40 @@
+/* SPDX-License-Identifier: GPL-2.0-only OR MIT */
+
+/*
+ * This file is created based on MT8189 Functional Specification
+ * Chapter number: 9.8
+ */
+
+#include <device/mmio.h>
+#include <gpio.h>
+#include <soc/addressmap.h>
+#include <soc/msdc.h>
+#include <soc/regulator.h>
+
+static const struct pad_func emmc_pins[] = {
+	PAD_FUNC_DOWN(EMMC_CLK, MSDC0_CLK),
+	PAD_FUNC_DOWN(EMMC_DSL, MSDC0_DSL),
+	PAD_FUNC_UP(EMMC_CMD, MSDC0_CMD),
+	PAD_FUNC_UP(EMMC_DAT0, MSDC0_DAT0),
+	PAD_FUNC_UP(EMMC_DAT1, MSDC0_DAT1),
+	PAD_FUNC_UP(EMMC_DAT2, MSDC0_DAT2),
+	PAD_FUNC_UP(EMMC_DAT3, MSDC0_DAT3),
+	PAD_FUNC_UP(EMMC_DAT4, MSDC0_DAT4),
+	PAD_FUNC_UP(EMMC_DAT5, MSDC0_DAT5),
+	PAD_FUNC_UP(EMMC_DAT6, MSDC0_DAT6),
+	PAD_FUNC_UP(EMMC_DAT7, MSDC0_DAT7),
+};
+
+void mtk_msdc_configure_emmc(bool is_early_init)
+{
+	size_t i;
+
+	for (i = 0; i < ARRAY_SIZE(emmc_pins); i++) {
+		gpio_set_mode(emmc_pins[i].gpio, emmc_pins[i].func);
+		gpio_set_pull(emmc_pins[i].gpio, GPIO_PULL_ENABLE, emmc_pins[i].select);
+		gpio_set_driving(emmc_pins[i].gpio, GPIO_DRV_6_MA);
+	}
+
+	if (is_early_init)
+		mtk_emmc_early_init((void *)MSDC0_BASE, (void *)MSDC0_TOP_BASE);
+}

From f3254097844540ee6de9ff1b95740194cf2c2031 Mon Sep 17 00:00:00 2001
From: Mengqi Zhang <mengqi.zhang@mediatek.corp-partner.google.com>
Date: Fri, 28 Feb 2025 15:13:40 +0800
Subject: [PATCH 1163/3886] soc/mediatek/mt8189: Add SD card support

Add GPIO configuration of SD card.

BUG=b:379008996
BRANCH=none
TEST=build pass

Signed-off-by: Mengqi Zhang <mengqi.zhang@mediatek.corp-partner.google.com>
Change-Id: If34841dddeb93a8622dda8e011cd1f29ec9c541d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87863
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
---
 src/soc/mediatek/mt8189/msdc.c | 28 ++++++++++++++++++++++++++++
 1 file changed, 28 insertions(+)

diff --git a/src/soc/mediatek/mt8189/msdc.c b/src/soc/mediatek/mt8189/msdc.c
index 1ebb78ef41..3454a75b3a 100644
--- a/src/soc/mediatek/mt8189/msdc.c
+++ b/src/soc/mediatek/mt8189/msdc.c
@@ -9,6 +9,7 @@
 #include <gpio.h>
 #include <soc/addressmap.h>
 #include <soc/msdc.h>
+#include <soc/mt6359p.h>
 #include <soc/regulator.h>
 
 static const struct pad_func emmc_pins[] = {
@@ -25,6 +26,15 @@ static const struct pad_func emmc_pins[] = {
 	PAD_FUNC_UP(EMMC_DAT7, MSDC0_DAT7),
 };
 
+static const struct pad_func sdcard_pins[] = {
+	PAD_FUNC_DOWN(MSDC1_CLK, MSDC1_CLK),
+	PAD_FUNC_UP(MSDC1_CMD, MSDC1_CMD),
+	PAD_FUNC_UP(MSDC1_DAT0, MSDC1_DAT0),
+	PAD_FUNC_UP(MSDC1_DAT1, MSDC1_DAT1),
+	PAD_FUNC_UP(MSDC1_DAT2, MSDC1_DAT2),
+	PAD_FUNC_UP(MSDC1_DAT3, MSDC1_DAT3),
+};
+
 void mtk_msdc_configure_emmc(bool is_early_init)
 {
 	size_t i;
@@ -38,3 +48,21 @@ void mtk_msdc_configure_emmc(bool is_early_init)
 	if (is_early_init)
 		mtk_emmc_early_init((void *)MSDC0_BASE, (void *)MSDC0_TOP_BASE);
 }
+
+void mtk_msdc_configure_sdcard(void)
+{
+	size_t i;
+
+	for (i = 0; i < ARRAY_SIZE(sdcard_pins); i++) {
+		gpio_set_mode(sdcard_pins[i].gpio, sdcard_pins[i].func);
+		gpio_set_pull(sdcard_pins[i].gpio, GPIO_PULL_ENABLE, sdcard_pins[i].select);
+		gpio_set_driving(sdcard_pins[i].gpio, GPIO_DRV_8_MA);
+	}
+
+	mt6359p_init_pmif_arb();
+	/* enable SD card power */
+	mainboard_set_regulator_voltage(MTK_REGULATOR_VMCH, 3000000);
+	mainboard_set_regulator_voltage(MTK_REGULATOR_VMC, 3000000);
+	mainboard_enable_regulator(MTK_REGULATOR_VMCH, true);
+	mainboard_enable_regulator(MTK_REGULATOR_VMC, true);
+}

From c34baacc728a317c3efaefcbe356db3bb8c26d2b Mon Sep 17 00:00:00 2001
From: Vince Liu <vince-wl.liu@mediatek.corp-partner.google.com>
Date: Tue, 13 May 2025 21:07:47 +0800
Subject: [PATCH 1164/3886] soc/mediatek/common: Add UFS2.2 and eMMC
 definitions to storage.h

Add support for projects with UFS2.2 and eMMC storage.

BUG=b:379008996
BRANCH=none
TEST=build pass

Signed-off-by: Vince Liu <vince-wl.liu@mediatek.corp-partner.google.com>
Change-Id: Ie8d76920417c7708117e3492152d3d4e87dd87ca
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87864
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
---
 src/soc/mediatek/common/include/soc/storage.h | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/src/soc/mediatek/common/include/soc/storage.h b/src/soc/mediatek/common/include/soc/storage.h
index 8df4075271..427218dd33 100644
--- a/src/soc/mediatek/common/include/soc/storage.h
+++ b/src/soc/mediatek/common/include/soc/storage.h
@@ -10,13 +10,16 @@
 
 #define _BASE_TYPE_UFS _BASE_TYPE(0x1)
 #define _BASE_TYPE_NVME _BASE_TYPE(0x2)
+#define _BASE_TYPE_EMMC _BASE_TYPE(0x3)
 
 enum mtk_storage_type {
 	STORAGE_UNKNOWN		= 0,
+	STORAGE_UFS_22		= _BASE_TYPE_UFS | 0x220,
 	STORAGE_UFS_31		= _BASE_TYPE_UFS | 0x310,
 	STORAGE_UFS_40		= _BASE_TYPE_UFS | 0x400,
 	STORAGE_UFS_40_HS	= _BASE_TYPE_UFS | 0x401,
 	STORAGE_NVME		= _BASE_TYPE_NVME,
+	STORAGE_EMMC		= _BASE_TYPE_EMMC,
 };
 
 enum mtk_storage_type mainboard_get_storage_type(void);

From 0e5757bfa72cf8a31ba2d3115c247767957cb01e Mon Sep 17 00:00:00 2001
From: Kun Liu <liukun11@huaqin.corp-partner.google.com>
Date: Wed, 28 May 2025 15:35:06 +0800
Subject: [PATCH 1165/3886] mb/google/trulo/var/pujjocento: Update DTT settings
 for thermal control

The DPTF parameters were defined by the thermal team.
Based on thermal table in b:419161631#comment1

BUG=b:419161631
TEST=emerge-nissa coreboot chromeos-bootimage

Change-Id: If79e58fa52ecb4626fdd6a25e8e3bf6e3c556c6b
Signed-off-by: Kun Liu <liukun11@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87878
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 .../brya/variants/pujjocento/overridetree.cb  | 189 ++++++++----------
 1 file changed, 79 insertions(+), 110 deletions(-)

diff --git a/src/mainboard/google/brya/variants/pujjocento/overridetree.cb b/src/mainboard/google/brya/variants/pujjocento/overridetree.cb
index 9c913d2ae4..e362c2ddaf 100644
--- a/src/mainboard/google/brya/variants/pujjocento/overridetree.cb
+++ b/src/mainboard/google/brya/variants/pujjocento/overridetree.cb
@@ -161,187 +161,156 @@ chip soc/intel/alderlake
 		device ref dtt on
 			chip drivers/intel/dptf
 				## sensor information
-				register "options.tsr[0].desc" = ""DDR""
-				register "options.tsr[1].desc" = ""charger""
-				register "options.tsr[2].desc" = ""ambient""
-
-				## Active Policy
-				register "policies.active" = "{
-					[0] = {
-						.target = DPTF_CPU,
-						.thresholds = {
-								TEMP_PCT(70, 100),
-								TEMP_PCT(60, 65),
-								TEMP_PCT(42, 60),
-								TEMP_PCT(39, 55),
-								TEMP_PCT(38, 50),
-								TEMP_PCT(35, 43),
-								TEMP_PCT(31, 30),
-						}
-					},
-					[1] = {
-						.target = DPTF_TEMP_SENSOR_0,
-						.thresholds = {
-								TEMP_PCT(60, 100),
-								TEMP_PCT(55, 65),
-								TEMP_PCT(52, 60),
-								TEMP_PCT(50, 55),
-								TEMP_PCT(48, 50),
-								TEMP_PCT(45, 43),
-								TEMP_PCT(41, 30),
-						}
-					}
-				}"
-
+				register "options.tsr[0].desc" = ""CPU_VR""
+				register "options.tsr[1].desc" = ""CPU""
+				register "options.tsr[2].desc" = ""Ambient""
+				register "options.tsr[3].desc" = ""Charger""
 				## Passive Policy
 				register "policies.passive" = "{
-					[0] = DPTF_PASSIVE(CPU,         CPU,           95, 5000),
-					[1] = DPTF_PASSIVE(CPU,         TEMP_SENSOR_0, 70, 5000),
-					[2] = DPTF_PASSIVE(CHARGER,     TEMP_SENSOR_1, 70, 5000),
-					[3] = DPTF_PASSIVE(CPU,         TEMP_SENSOR_2, 70, 5000),
+					[0] = DPTF_PASSIVE(CPU,         CPU,           85, 4000),
+					[1] = DPTF_PASSIVE(CPU,         TEMP_SENSOR_0, 85, 4000),
+					[2] = DPTF_PASSIVE(CPU,     TEMP_SENSOR_1, 85, 4000),
+					[3] = DPTF_PASSIVE(CPU,         TEMP_SENSOR_2, 85, 4000),
+					[4] = DPTF_PASSIVE(CHARGER,         TEMP_SENSOR_3, 85, 4000),
 				}"
 
 				## Critical Policy
 				register "policies.critical" = "{
-					[0] = DPTF_CRITICAL(CPU,               100, SHUTDOWN),
-					[1] = DPTF_CRITICAL(TEMP_SENSOR_0,     95, SHUTDOWN),
-					[2] = DPTF_CRITICAL(TEMP_SENSOR_1,     95, SHUTDOWN),
-					[3] = DPTF_CRITICAL(TEMP_SENSOR_2,     95, SHUTDOWN),
+					[0] = DPTF_CRITICAL(TEMP_SENSOR_1,     90, SHUTDOWN),
+					[1] = DPTF_CRITICAL(TEMP_SENSOR_2,     90, SHUTDOWN),
 				}"
 
 				register "controls.power_limits" = "{
 					.pl1 = {
-						.min_power = 5000,
-						.max_power = 6000,
+						.min_power = 6000,
+						.max_power = 13000,
 						.time_window_min = 28 * MSECS_PER_SEC,
-						.time_window_max = 28 * MSECS_PER_SEC,
-						.granularity = 500
+						.time_window_max = 32 * MSECS_PER_SEC,
+						.granularity = 200
 					},
 					.pl2 = {
 						.min_power = 25000,
 						.max_power = 25000,
-						.time_window_min = 32 * MSECS_PER_SEC,
+						.time_window_min = 28 * MSECS_PER_SEC,
 						.time_window_max = 32 * MSECS_PER_SEC,
-						.granularity = 500
+						.granularity = 1000
 					}
 				}"
 
 				## Charger Performance Control (Control, mA)
 				register "controls.charger_perf" = "{
-					[0] = { 255, 1700 },
-					[1] = {  24, 1500 },
+					[0] = { 255, 4700 },
+					[1] = {  40, 2500 },
 					[2] = {  16, 1000 },
 					[3] = {   8,  500 }
 				}"
 
-				## Fan Performance Control (Percent, Speed, Noise, Power)
-				register "controls.fan_perf" = "{
-					[0] = { 100, 6000, 220, 2200, },
-					[1] = {  92, 5500, 180, 1800, },
-					[2] = {  85, 5000, 145, 1450, },
-					[3] = {  70, 4400, 115, 1150, },
-					[4] = {  56, 3900,  90,  900, },
-					[5] = {  45, 3300,  55,  550, },
-					[6] = {  38, 3000,  30,  300, },
-					[7] = {  33, 2900,  15,  150, },
-					[8] = {  10,  800,  10,  100, },
-					[9] = {   0,    0,   0,   50, }
-				}"
-
-				## Fan options
-				register "options.fan.fine_grained_control" = "true"
-				register "options.fan.step_size" = "2"
-
 				device generic 0 on
 					probe THERMAL_SOLUTION THERMAL_SOLUTION_6W
 				end
 			end
 			chip drivers/intel/dptf
 				## sensor information
-				register "options.tsr[0].desc" = ""DDR""
-				register "options.tsr[1].desc" = ""charger""
-				register "options.tsr[2].desc" = ""ambient""
+				register "options.tsr[0].desc" = ""CPU_VR""
+				register "options.tsr[1].desc" = ""CPU""
+				register "options.tsr[2].desc" = ""Ambient""
+				register "options.tsr[3].desc" = ""Charger""
 
 				## Active Policy
 				register "policies.active" = "{
 					[0] = {
-						.target = DPTF_CPU,
+						.target = DPTF_TEMP_SENSOR_0,
 						.thresholds = {
-								TEMP_PCT(70, 100),
-								TEMP_PCT(60, 65),
-								TEMP_PCT(42, 58),
-								TEMP_PCT(39, 53),
-								TEMP_PCT(38, 47),
-								TEMP_PCT(35, 43),
-								TEMP_PCT(31, 30),
+								TEMP_PCT(85, 90),
+								TEMP_PCT(44, 61),
+								TEMP_PCT(42, 54),
+								TEMP_PCT(40, 45),
+								TEMP_PCT(38, 38),
+								TEMP_PCT(36, 25),
 						}
 					},
 					[1] = {
-						.target = DPTF_TEMP_SENSOR_0,
+						.target = DPTF_TEMP_SENSOR_1,
 						.thresholds = {
-								TEMP_PCT(60, 100),
-								TEMP_PCT(55, 65),
-								TEMP_PCT(52, 58),
-								TEMP_PCT(50, 53),
-								TEMP_PCT(48, 47),
-								TEMP_PCT(45, 43),
-								TEMP_PCT(41, 30),
+								TEMP_PCT(75, 90),
+								TEMP_PCT(70, 80),
+								TEMP_PCT(65, 70),
+								TEMP_PCT(60, 60),
+								TEMP_PCT(55, 50),
+								TEMP_PCT(50, 40),
+						}
+					},
+					[2] = {
+						.target = DPTF_TEMP_SENSOR_2,
+						.thresholds = {
+								TEMP_PCT(90, 90),
+								TEMP_PCT(85, 80),
+								TEMP_PCT(75, 70),
+								TEMP_PCT(70, 50),
+						}
+					},
+					[3] = {
+						.target = DPTF_TEMP_SENSOR_3,
+						.thresholds = {
+								TEMP_PCT(80, 90),
+								TEMP_PCT(75, 80),
+								TEMP_PCT(70, 70),
+								TEMP_PCT(65, 50),
 						}
 					}
 				}"
 
 				## Passive Policy
 				register "policies.passive" = "{
-					[0] = DPTF_PASSIVE(CPU,         CPU,           95, 5000),
-					[1] = DPTF_PASSIVE(CPU,         TEMP_SENSOR_0, 70, 5000),
-					[2] = DPTF_PASSIVE(CHARGER,     TEMP_SENSOR_1, 70, 5000),
-					[3] = DPTF_PASSIVE(CPU,         TEMP_SENSOR_2, 70, 5000),
+					[0] = DPTF_PASSIVE(CPU,         CPU,           85, 6000),
+					[1] = DPTF_PASSIVE(CPU,         TEMP_SENSOR_0, 85, 6000),
+					[2] = DPTF_PASSIVE(CPU,         TEMP_SENSOR_1, 85, 6000),
+					[3] = DPTF_PASSIVE(CPU,         TEMP_SENSOR_2, 85, 6000),
+					[4] = DPTF_PASSIVE(CHARGER,     TEMP_SENSOR_3, 85, 6000),
 				}"
 
 				## Critical Policy
 				register "policies.critical" = "{
-					[0] = DPTF_CRITICAL(CPU,               100, SHUTDOWN),
-					[1] = DPTF_CRITICAL(TEMP_SENSOR_0,     95, SHUTDOWN),
-					[2] = DPTF_CRITICAL(TEMP_SENSOR_1,     95, SHUTDOWN),
-					[3] = DPTF_CRITICAL(TEMP_SENSOR_2,     95, SHUTDOWN),
+					[0] = DPTF_CRITICAL(TEMP_SENSOR_1,     90, SHUTDOWN),
+					[1] = DPTF_CRITICAL(TEMP_SENSOR_2,     90, SHUTDOWN),
 				}"
 
 				register "controls.power_limits" = "{
 					.pl1 = {
-						.min_power = 14000,
-						.max_power = 15000,
+						.min_power = 15000,
+						.max_power = 22000,
 						.time_window_min = 28 * MSECS_PER_SEC,
-						.time_window_max = 28 * MSECS_PER_SEC,
-						.granularity = 500
+						.time_window_max = 32 * MSECS_PER_SEC,
+						.granularity = 200
 					},
 					.pl2 = {
 						.min_power = 35000,
 						.max_power = 35000,
-						.time_window_min = 32 * MSECS_PER_SEC,
+						.time_window_min = 28 * MSECS_PER_SEC,
 						.time_window_max = 32 * MSECS_PER_SEC,
-						.granularity = 500
+						.granularity = 1000
 					}
 				}"
 
 				## Charger Performance Control (Control, mA)
 				register "controls.charger_perf" = "{
-					[0] = { 255, 1700 },
-					[1] = {  24, 1500 },
+					[0] = { 255, 4700 },
+					[1] = {  40, 2500 },
 					[2] = {  16, 1000 },
 					[3] = {   8,  500 }
 				}"
 
 				## Fan Performance Control (Percent, Speed, Noise, Power)
 				register "controls.fan_perf" = "{
-					[0] = { 100, 6000, 220, 2200, },
-					[1] = {  92, 5500, 180, 1800, },
-					[2] = {  85, 5000, 145, 1450, },
-					[3] = {  70, 4400, 115, 1150, },
-					[4] = {  56, 3900,  90,  900, },
-					[5] = {  45, 3300,  55,  550, },
-					[6] = {  38, 3000,  30,  300, },
-					[7] = {  33, 2900,  15,  150, },
-					[8] = {  10,  800,  10,  100, },
+					[0] = { 100, 4400, 220, 1640, },
+					[1] = {  90, 4100, 220, 1640, },
+					[2] = {  80, 3800, 180, 1310, },
+					[3] = {  70, 3500, 145, 1030, },
+					[4] = {  60, 3100, 115,  765, },
+					[5] = {  50, 2800,  90,  545, },
+					[6] = {  40, 2400,  55,  365, },
+					[7] = {  30, 1900,  30,  220, },
+					[8] = {  20, 1400,  15,  120, },
 					[9] = {   0,    0,   0,   50, }
 				}"
 

From 4d5b32f7f71be1789ea1ee1a4f77724ec5fac796 Mon Sep 17 00:00:00 2001
From: Nick Vaccaro <nvaccaro@google.com>
Date: Mon, 19 May 2025 13:58:34 -0700
Subject: [PATCH 1166/3886] mb/google/ocelot/var/ocelot: remove unused gpios

Remove GPP_D16, GPP_D17, and GPP_B25 as they aren't used in ocelot.

Change GPP_A08 polarity in gpio_table and rom_gpio_table.

BUG=b:412736286
BRANCH=None
TEST=`emerge-ocelot coreboot` and verify it compiles without error.

Change-Id: Ife444cef816ca2b69db466661c63935f72836554
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87870
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Avi Uday <aviuday@google.com>
---
 .../google/ocelot/variants/ocelot/fw_config.c     | 15 ---------------
 .../google/ocelot/variants/ocelot/gpio.c          |  4 ++--
 2 files changed, 2 insertions(+), 17 deletions(-)

diff --git a/src/mainboard/google/ocelot/variants/ocelot/fw_config.c b/src/mainboard/google/ocelot/variants/ocelot/fw_config.c
index affde9dce4..49de442e7d 100644
--- a/src/mainboard/google/ocelot/variants/ocelot/fw_config.c
+++ b/src/mainboard/google/ocelot/variants/ocelot/fw_config.c
@@ -20,10 +20,6 @@ static const struct pad_config hda_enable_pads[] = {
 	PAD_CFG_NF(GPP_D12, NATIVE, DEEP, NF1),
 	/* HDA_SDI_0 */
 	PAD_CFG_NF(GPP_D13, NATIVE, DEEP, NF1),
-	/* HDA_RST_B */
-	PAD_CFG_NF(GPP_D16, NONE, DEEP, NF1),
-	/* HDA_SDI_1 */
-	PAD_CFG_NF(GPP_D17, NATIVE, DEEP, NF1),
 
 	/* DMIC_CLK */
 	PAD_CFG_NF(GPP_S04, NONE, DEEP, NF5),
@@ -86,11 +82,6 @@ static const struct pad_config sndw_alc721_enable_pads[] = {
 	PAD_CFG_NF(GPP_S06, NONE, DEEP, NF3),
 	/* SNDW1_DATA  */
 	PAD_CFG_NF(GPP_S07, NONE, DEEP, NF3),
-
-	/* DMIC_CLK */
-	PAD_CFG_NF(GPP_D16, NONE, DEEP, NF3),
-	/* DMIC_DATA */
-	PAD_CFG_NF(GPP_D17, NONE, DEEP, NF3),
 };
 
 static const struct pad_config audio_disable_pads[] = {
@@ -107,8 +98,6 @@ static const struct pad_config audio_disable_pads[] = {
 	PAD_NC(GPP_D11, NONE),
 	PAD_NC(GPP_D12, NONE),
 	PAD_NC(GPP_D13, NONE),
-	PAD_NC(GPP_D16, NONE),
-	PAD_NC(GPP_D17, NONE),
 };
 
 static const struct pad_config x1slot_pads[] = {
@@ -116,8 +105,6 @@ static const struct pad_config x1slot_pads[] = {
 	PAD_CFG_GPO(GPP_A08, 1, PLTRST),
 	/* GPP_D19:     X1_DT_PCIE_RST_N */
 	PAD_CFG_GPO(GPP_D19, 1, PLTRST),
-	/* GPP_B25:     X1_SLOT_WAKE_N */
-	PAD_CFG_GPI_SCI_LOW(GPP_B25, NONE, DEEP, LEVEL),
 };
 
 static const struct pad_config x1slot_disable_pads[] = {
@@ -125,8 +112,6 @@ static const struct pad_config x1slot_disable_pads[] = {
 	PAD_CFG_GPO(GPP_A08, 0, PLTRST),
 	/* GPP_D19:     X1_DT_PCIE_RST_N */
 	PAD_NC(GPP_D19, NONE),
-	/* GPP_B25:     X1_SLOT_WAKE_N */
-	PAD_NC(GPP_B25, NONE)
 };
 
 /*
diff --git a/src/mainboard/google/ocelot/variants/ocelot/gpio.c b/src/mainboard/google/ocelot/variants/ocelot/gpio.c
index 43e5232e21..58f1cb256e 100644
--- a/src/mainboard/google/ocelot/variants/ocelot/gpio.c
+++ b/src/mainboard/google/ocelot/variants/ocelot/gpio.c
@@ -22,7 +22,7 @@ static const struct pad_config gpio_table[] = {
 	/* GPP_A06:     ESPI_SOC_RST_L # */
 	PAD_CFG_NF(GPP_A06, NONE, DEEP, NF1),
 	/* GPP_A08:     SSD_PERST_L # */
-	PAD_CFG_GPO(GPP_A08, 0, PLTRST),
+	PAD_CFG_GPO(GPP_A08, 1, PLTRST),
 	/* GPP_A09:     WWAN_EN */
 	PAD_CFG_GPO(GPP_A09, 0, PLTRST),
 	/* GPP_A10:     WWAN_RF_DISABLE_ODL */
@@ -382,7 +382,7 @@ static const struct pad_config early_gpio_table[] = {
 /* Pad configuration in romstage */
 static const struct pad_config romstage_gpio_table[] = {
 	/* GPP_A08:     SSD_PERST_L */
-	PAD_CFG_GPO(GPP_A08, 1, PLTRST),
+	PAD_CFG_GPO(GPP_A08, 0, PLTRST),
 };
 
 const struct pad_config *variant_gpio_table(size_t *num)

From ab160ca301e430bce4f7109e8aff9015bb757855 Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Tue, 27 May 2025 10:48:40 -0500
Subject: [PATCH 1167/3886] mb/google/byra/var/teliks: Add default VBT

Extracted from coreboot-Google_Teliks.15217.734.0.bin

Change-Id: Ib9f077cdd0536e6315b05775337bf30555562cc8
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87866
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
---
 .../google/brya/variants/teliks/Makefile.mk      |   1 +
 .../google/brya/variants/teliks/data-teliks.vbt  | Bin 0 -> 9216 bytes
 2 files changed, 1 insertion(+)
 create mode 100644 src/mainboard/google/brya/variants/teliks/data-teliks.vbt

diff --git a/src/mainboard/google/brya/variants/teliks/Makefile.mk b/src/mainboard/google/brya/variants/teliks/Makefile.mk
index ce2f87618d..8a686ccc28 100644
--- a/src/mainboard/google/brya/variants/teliks/Makefile.mk
+++ b/src/mainboard/google/brya/variants/teliks/Makefile.mk
@@ -8,4 +8,5 @@ ramstage-y += gpio.c
 
 ramstage-y += variant.c
 
+$(call add_vbt_to_cbfs, vbt-teliks.bin, data-teliks.vbt)
 $(call add_vbt_to_cbfs, vbt-teliks_panel_11_inch.bin, data-teliks_panel_11_inch.vbt)
diff --git a/src/mainboard/google/brya/variants/teliks/data-teliks.vbt b/src/mainboard/google/brya/variants/teliks/data-teliks.vbt
new file mode 100644
index 0000000000000000000000000000000000000000..aa0ccac1131f430d6397f684a47bd3cf897b0c31
GIT binary patch
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HuMGSS4R?A9

literal 0
HcmV?d00001


From 58165618da7e97776656a05e1ae1877cd7d7745b Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Tue, 27 May 2025 10:50:44 -0500
Subject: [PATCH 1168/3886] mb/google/byra/var/craask: Add VBT for HDMI variant

Extracted from coreboot-Google_Craask.15217-841-0.bin

Change-Id: I07d4e7fe63ff6ad43806d73d9e31ffe0aa8807c5
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87867
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 .../google/brya/variants/craask/Makefile.mk      |   2 ++
 .../brya/variants/craask/data-craask_hdmi.vbt    | Bin 0 -> 9216 bytes
 2 files changed, 2 insertions(+)
 create mode 100644 src/mainboard/google/brya/variants/craask/data-craask_hdmi.vbt

diff --git a/src/mainboard/google/brya/variants/craask/Makefile.mk b/src/mainboard/google/brya/variants/craask/Makefile.mk
index 86ba20d3c3..b90c74cd7f 100644
--- a/src/mainboard/google/brya/variants/craask/Makefile.mk
+++ b/src/mainboard/google/brya/variants/craask/Makefile.mk
@@ -6,3 +6,5 @@ romstage-y += gpio.c
 ramstage-$(CONFIG_FW_CONFIG) += fw_config.c
 ramstage-$(CONFIG_FW_CONFIG) += variant.c
 ramstage-y += gpio.c
+
+$(call add_vbt_to_cbfs, vbt-craask_hdmi.bin, data-craask_hdmi.vbt)
diff --git a/src/mainboard/google/brya/variants/craask/data-craask_hdmi.vbt b/src/mainboard/google/brya/variants/craask/data-craask_hdmi.vbt
new file mode 100644
index 0000000000000000000000000000000000000000..8a43cb0a13cf113a11d564979ebc2d793d54ab0f
GIT binary patch
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literal 0
HcmV?d00001


From 394dfcaa7b162f28d7b0a92428d688ef59ac82cb Mon Sep 17 00:00:00 2001
From: Bora Guvendik <bora.guvendik@intel.com>
Date: Tue, 27 May 2025 14:12:52 -0700
Subject: [PATCH 1169/3886] mb/intel/ptlrvp: Handle GPIO support for DDR5
 configuration
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

This commit addresses the GPIO configuration for DDR5 on Intel's
PTLRVP mainboard. Specifically, it extends support for the DDR5
configuration by adding a case for PTLP_DDR5_RVP in the GPIO
differential table function. This modification ensures proper handling
of GPIO settings when DDR5 memory is configured, thereby improving
system stability and compatibility.

BUG=none
TEST=Boot with DDR5 configuration.

Change-Id: I3745c0a25e84a0f41dced44613cfd638c12fb1d3
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87872
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Reviewed-by: Jamie Ryu <jamie.m.ryu@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Zhixing Ma <zhixing.ma@intel.com>
---
 src/mainboard/intel/ptlrvp/variants/ptlrvp/gpio.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/src/mainboard/intel/ptlrvp/variants/ptlrvp/gpio.c b/src/mainboard/intel/ptlrvp/variants/ptlrvp/gpio.c
index 7b4dbe3c9f..7dcf6d7873 100644
--- a/src/mainboard/intel/ptlrvp/variants/ptlrvp/gpio.c
+++ b/src/mainboard/intel/ptlrvp/variants/ptlrvp/gpio.c
@@ -461,6 +461,7 @@ const struct pad_config *variant_board_gpio_diff_table(size_t *num)
 		return t4_gpio_diff_table;
 	case GCS_32GB:
 	case GCS_64GB:
+	case PTLP_DDR5_RVP:
 		return NULL;
 	default:
 		die("Unknown board ID = 0x%x\n", board_id);

From c16891ecbd17200f303a5e57eaa6240f8f8065b4 Mon Sep 17 00:00:00 2001
From: Jeremy Compostella <jeremy.compostella@intel.com>
Date: Tue, 27 May 2025 08:59:39 -0700
Subject: [PATCH 1170/3886] soc/intel/meteorlake: Use CACHE_TMP_RAMTOP for TME
 exclusion range

This commit updates the fill_tme_params() function to utilize the
CACHE_TMP_RAMTOP constant instead of hardcoded values for calculating
the TME exclusion range.

Change-Id: I199182de8b8b219b0c45b27746b7415527cb9976
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87868
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
---
 src/soc/intel/meteorlake/romstage/fsp_params.c | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/src/soc/intel/meteorlake/romstage/fsp_params.c b/src/soc/intel/meteorlake/romstage/fsp_params.c
index 190cb73085..57e56595a9 100644
--- a/src/soc/intel/meteorlake/romstage/fsp_params.c
+++ b/src/soc/intel/meteorlake/romstage/fsp_params.c
@@ -7,6 +7,7 @@
 #include <cpu/intel/common/common.h>
 #include <cpu/intel/cpu_ids.h>
 #include <cpu/x86/msr.h>
+#include <cpu/x86/mtrr.h>
 #include <device/device.h>
 #include <device/pci.h>
 #include <drivers/wifi/generic/wifi.h>
@@ -202,8 +203,8 @@ static void fill_tme_params(FSP_M_CONFIG *m_cfg)
 						"Full memory encryption is enabled.\n");
 			return;
 		}
-		m_cfg->TmeExcludeBase = (ram_top - 16*MiB);
-		m_cfg->TmeExcludeSize = 16*MiB;
+		m_cfg->TmeExcludeBase = (ram_top - CACHE_TMP_RAMTOP);
+		m_cfg->TmeExcludeSize = CACHE_TMP_RAMTOP;
 	}
 }
 

From 715e7e51c599eea144013fc9a73e6371882673e1 Mon Sep 17 00:00:00 2001
From: Mac Chiang <mac.chiang@intel.com>
Date: Tue, 4 Mar 2025 13:35:14 +0800
Subject: [PATCH 1171/3886] mb/google/fatcat/var/francka: Add support for DMIC0

This patch enables DMIC_CLK0 and DMIC_DATA0 for
internal board DMIC recording.

BUG=b:392007428
TEST=emerge-fatcat coreboot

Change-Id: Idcc18a6a605694bc5c1a2994453717887814e897
Signed-off-by: Mac Chiang <mac.chiang@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86699
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
---
 src/mainboard/google/fatcat/variants/francka/fw_config.c | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/src/mainboard/google/fatcat/variants/francka/fw_config.c b/src/mainboard/google/fatcat/variants/francka/fw_config.c
index c722725f0b..2ec7c4481b 100644
--- a/src/mainboard/google/fatcat/variants/francka/fw_config.c
+++ b/src/mainboard/google/fatcat/variants/francka/fw_config.c
@@ -37,6 +37,13 @@ static const struct pad_config sndw_alc721_enable_pads[] = {
 	PAD_CFG_NF(GPP_S07, NONE, DEEP, NF5),
 };
 
+static const struct pad_config enable_dmic_0_pads[] = {
+	/* GPP_S02:     SOC_DMIC_CLK0 */
+	PAD_CFG_NF(GPP_S02, NONE, DEEP, NF5),
+	/* GPP_S03:     SOC_DMIC_DATA0 */
+	PAD_CFG_NF(GPP_S03, NONE, DEEP, NF5),
+};
+
 /*
  * WWAN: power sequence requires three stages:
  * step 1: 3.3V power, FCP# (Full Card Power), RST#, and PERST# off
@@ -120,6 +127,7 @@ void fw_config_gpio_padbased_override(struct pad_config *padbased_table)
 	if (fw_config_probe(FW_CONFIG(AUDIO, AUDIO_ALC256M_CG_HDA))) {
 		printk(BIOS_INFO, "Configure GPIOs for HDA ALC256 mode.\n");
 		GPIO_PADBASED_OVERRIDE(padbased_table, hda_enable_pads);
+		GPIO_PADBASED_OVERRIDE(padbased_table, enable_dmic_0_pads);
 	} else if (fw_config_probe(FW_CONFIG(AUDIO, AUDIO_ALC721_SNDW))) {
 		printk(BIOS_INFO, "Configure GPIOs for Soundwire ALC721 mode.\n");
 		GPIO_PADBASED_OVERRIDE(padbased_table, sndw_alc721_enable_pads);

From 77c610464548ded89bdf73c8a7cc7c6c78cbc63f Mon Sep 17 00:00:00 2001
From: Momoko Hattori <momohatt@google.com>
Date: Wed, 28 May 2025 23:46:03 +0900
Subject: [PATCH 1172/3886] Revert "mb/google/rex: Enable use_gpio_for_status
 for touchscreen"

This reverts commit 81f396ec2faefeda33b7e23d9cef380fce11a22c.

Reason for revert: Reported to have broken touchscreen for screebo.

BUG=b:420550351
BUG=b:397355818
TEST=FW_NAME=screebo cros build-packages --board=rex chromeos-bootimage
TEST=FW_NAME=karis cros build-packages --board=rex chromeos-bootimage
TEST=karis boots successfully and touchscreen remains to work.

Change-Id: I75dad8cd07c900f963888b0a34bf18d893f20d71
Signed-off-by: Momoko Hattori <momohatt@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87893
Reviewed-by: YH Lin <yueherngl@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/google/rex/variants/kanix/overridetree.cb   | 1 -
 src/mainboard/google/rex/variants/karis/overridetree.cb   | 1 -
 src/mainboard/google/rex/variants/rex0/overridetree.cb    | 1 -
 src/mainboard/google/rex/variants/screebo/overridetree.cb | 2 --
 4 files changed, 5 deletions(-)

diff --git a/src/mainboard/google/rex/variants/kanix/overridetree.cb b/src/mainboard/google/rex/variants/kanix/overridetree.cb
index 31fbf555a6..f0d57b3046 100644
--- a/src/mainboard/google/rex/variants/kanix/overridetree.cb
+++ b/src/mainboard/google/rex/variants/kanix/overridetree.cb
@@ -459,7 +459,6 @@ chip soc/intel/meteorlake
 				register "generic.stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C06)"
 				register "generic.stop_off_delay_ms" = "1"
 				register "generic.has_power_resource" = "1"
-				register "generic.use_gpio_for_status" = "true"
 				register "hid_desc_reg_offset" = "0x01"
 				device i2c 0x10 on end
 			end
diff --git a/src/mainboard/google/rex/variants/karis/overridetree.cb b/src/mainboard/google/rex/variants/karis/overridetree.cb
index 2607ad776f..ea45d61981 100644
--- a/src/mainboard/google/rex/variants/karis/overridetree.cb
+++ b/src/mainboard/google/rex/variants/karis/overridetree.cb
@@ -404,7 +404,6 @@ chip soc/intel/meteorlake
 				register "generic.stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C06)"
 				register "generic.stop_off_delay_ms" = "1"
 				register "generic.has_power_resource" = "1"
-				register "generic.use_gpio_for_status" = "true"
 				register "hid_desc_reg_offset" = "0x01"
 				device i2c 0x10 on end
 			end
diff --git a/src/mainboard/google/rex/variants/rex0/overridetree.cb b/src/mainboard/google/rex/variants/rex0/overridetree.cb
index 177e88781c..66b2bc9528 100644
--- a/src/mainboard/google/rex/variants/rex0/overridetree.cb
+++ b/src/mainboard/google/rex/variants/rex0/overridetree.cb
@@ -579,7 +579,6 @@ chip soc/intel/meteorlake
 				register "generic.stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C06)"
 				register "generic.stop_off_delay_ms" = "2"
 				register "generic.has_power_resource" = "1"
-				register "generic.use_gpio_for_status" = "true"
 				register "hid_desc_reg_offset" = "0x01"
 				device i2c 10 on
 					probe TOUCHSCREEN TOUCHSCREEN_I2C
diff --git a/src/mainboard/google/rex/variants/screebo/overridetree.cb b/src/mainboard/google/rex/variants/screebo/overridetree.cb
index 6e8f5fc028..d46d7c91ef 100644
--- a/src/mainboard/google/rex/variants/screebo/overridetree.cb
+++ b/src/mainboard/google/rex/variants/screebo/overridetree.cb
@@ -451,7 +451,6 @@ chip soc/intel/meteorlake
 				register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B17)"
 				register "generic.enable_delay_ms" = "12"
 				register "generic.has_power_resource" = "1"
-				register "generic.use_gpio_for_status" = "true"
 				register "hid_desc_reg_offset" = "0x01"
 				device i2c 41 on
 					probe TOUCHSCREEN TOUCHSCREEN_ILITEK
@@ -468,7 +467,6 @@ chip soc/intel/meteorlake
 				register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B17)"
 				register "generic.enable_delay_ms" = "1"
 				register "generic.has_power_resource" = "1"
-				register "generic.use_gpio_for_status" = "true"
 				register "hid_desc_reg_offset" = "0x01"
 				device i2c 10 on
 					probe TOUCHSCREEN TOUCHSCREEN_ELAN

From 481001e13b5b0c22d5bb8b88cd65d561c0110f01 Mon Sep 17 00:00:00 2001
From: Subrata Banik <subratabanik@google.com>
Date: Tue, 27 May 2025 03:47:13 +0000
Subject: [PATCH 1173/3886] soc/qualcomm/x1p42100: Add placeholder for early
 clock initialization

This commit adds the `clock_init()` function for the Qualcomm x1p42100
SoC. This function is now called at the beginning of
`bootblock_soc_init()` to enable SoC-specific clock setup early in the
boot process.

The `clock_init()` function definition is currently a placeholder
and will be populated with the required clock configurations in
subsequent changes.

BUG=b:404985109
TEST=Able to build google/bluey

Change-Id: Ifb856ea4132def9cd3a36b081d24037a1a4efaba
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87850
Reviewed-by: Pranava Y N <pranavayn@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/soc/qualcomm/x1p42100/bootblock.c         | 1 +
 src/soc/qualcomm/x1p42100/clock.c             | 5 +++++
 src/soc/qualcomm/x1p42100/include/soc/clock.h | 1 +
 3 files changed, 7 insertions(+)

diff --git a/src/soc/qualcomm/x1p42100/bootblock.c b/src/soc/qualcomm/x1p42100/bootblock.c
index 32a958b687..c6d8b9e4c5 100644
--- a/src/soc/qualcomm/x1p42100/bootblock.c
+++ b/src/soc/qualcomm/x1p42100/bootblock.c
@@ -9,6 +9,7 @@
 
 void bootblock_soc_init(void)
 {
+	clock_init();
 	if (!CONFIG(COMPRESS_BOOTBLOCK))
 		soc_mmu_init();
 
diff --git a/src/soc/qualcomm/x1p42100/clock.c b/src/soc/qualcomm/x1p42100/clock.c
index 9a4b16d810..5e9706f698 100644
--- a/src/soc/qualcomm/x1p42100/clock.c
+++ b/src/soc/qualcomm/x1p42100/clock.c
@@ -16,3 +16,8 @@ void clock_configure_dfsr(int qup)
 {
 	/* placeholder */
 }
+
+void clock_init(void)
+{
+	/* placeholder */
+}
diff --git a/src/soc/qualcomm/x1p42100/include/soc/clock.h b/src/soc/qualcomm/x1p42100/include/soc/clock.h
index c6b01f8f91..bb327709af 100644
--- a/src/soc/qualcomm/x1p42100/include/soc/clock.h
+++ b/src/soc/qualcomm/x1p42100/include/soc/clock.h
@@ -37,6 +37,7 @@ enum clk_qup {
 };
 
 /* TODO: update as per datasheet */
+void clock_init(void);
 void clock_configure_qspi(uint32_t hz);
 void clock_enable_qup(int qup);
 void clock_configure_dfsr(int qup);

From a5d99a814a802aba6ed3331f8836f5453f3828c3 Mon Sep 17 00:00:00 2001
From: Subrata Banik <subratabanik@google.com>
Date: Tue, 27 May 2025 08:06:28 +0000
Subject: [PATCH 1174/3886] soc/qc/x1p42100: Perform `soc_mmu_init` inside
 early bootblock init

This commit introduces `bootblock_soc_early_init` API for early SoC
initialization sequence in the bootblock.

- `bootblock_soc_early_init()`: This function now handles very early
  initialization steps (before console init), specifically
  `soc_mmu_init()` when the bootblock is not compressed.

- `bootblock_soc_init()`: This function retains the subsequent
  initialization tasks including `clock_init()`, `quadspi_init()`,
  and `qupv3_fw_init()`.

This change ensures MMU setup to occur before other peripheral and
clock initializations.

TEST=Able to get bootblock console log in proper.

Change-Id: I8bbcdb9c39e13fac81ef6a34647c4f343a619561
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87857
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Pranava Y N <pranavayn@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
---
 src/soc/qualcomm/x1p42100/bootblock.c | 8 ++++++--
 1 file changed, 6 insertions(+), 2 deletions(-)

diff --git a/src/soc/qualcomm/x1p42100/bootblock.c b/src/soc/qualcomm/x1p42100/bootblock.c
index c6d8b9e4c5..d106912de7 100644
--- a/src/soc/qualcomm/x1p42100/bootblock.c
+++ b/src/soc/qualcomm/x1p42100/bootblock.c
@@ -7,11 +7,15 @@
 
 #define SPI_BUS_CLOCK_FREQ (50 * MHz)
 
+void bootblock_soc_early_init(void)
+{
+	if (!CONFIG(COMPRESS_BOOTBLOCK))
+		soc_mmu_init();
+}
+
 void bootblock_soc_init(void)
 {
 	clock_init();
-	if (!CONFIG(COMPRESS_BOOTBLOCK))
-		soc_mmu_init();
 
 	quadspi_init(SPI_BUS_CLOCK_FREQ);
 	qupv3_fw_init();

From 891c208835bb8cedb0007034090b7e0f0efe5460 Mon Sep 17 00:00:00 2001
From: Subrata Banik <subratabanik@google.com>
Date: Tue, 27 May 2025 09:33:33 +0000
Subject: [PATCH 1175/3886] soc/qualcomm/x1p42100: Enable basic PCIe support

This commit introduces initial support for PCI Express on the
Qualcomm x1p42100 SoC.

Key changes include:
- Selecting `CONFIG_PCI` in Kconfig to enable general PCI subsystem
  support for this SoC.
- Selecting `CONFIG_NO_ECAM_MMCONF_SUPPORT`, indicating that this
  platform will not use the standard MMCONFIG ECAM for PCI
  configuration space access. An alternative mechanism will be required.
- Adding `../common/pcie_common.c` to the ramstage build if `CONFIG_PCI`
  is enabled, incorporating common PCIe helper functions.

BUG=b:404985109
TEST=Able to build google/bluey.

Change-Id: I53e8bb3ce8551e8fa8c4b1cd39d89e12226c32f1
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87858
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Pranava Y N <pranavayn@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/soc/qualcomm/x1p42100/Kconfig     | 2 ++
 src/soc/qualcomm/x1p42100/Makefile.mk | 1 +
 2 files changed, 3 insertions(+)

diff --git a/src/soc/qualcomm/x1p42100/Kconfig b/src/soc/qualcomm/x1p42100/Kconfig
index 52f270b6d9..d9d6a939af 100644
--- a/src/soc/qualcomm/x1p42100/Kconfig
+++ b/src/soc/qualcomm/x1p42100/Kconfig
@@ -21,6 +21,8 @@ config SOC_QUALCOMM_X1P42100
 	select HAVE_UART_SPECIAL
 	select MAINBOARD_FORCE_NATIVE_VGA_INIT
 	select MAINBOARD_HAS_NATIVE_VGA_INIT
+	select PCI
+	select NO_ECAM_MMCONF_SUPPORT
 	select SDHCI_CONTROLLER
 	select SOC_QUALCOMM_COMMON
 
diff --git a/src/soc/qualcomm/x1p42100/Makefile.mk b/src/soc/qualcomm/x1p42100/Makefile.mk
index 0135f9bf57..f75fdd4f7f 100644
--- a/src/soc/qualcomm/x1p42100/Makefile.mk
+++ b/src/soc/qualcomm/x1p42100/Makefile.mk
@@ -38,6 +38,7 @@ romstage-$(CONFIG_DRIVERS_UART) += ../common/qupv3_uart.c
 ramstage-y += soc.c
 ramstage-y += cbmem.c
 ramstage-$(CONFIG_DRIVERS_UART) += ../common/qupv3_uart.c
+ramstage-$(CONFIG_PCI) += ../common/pcie_common.c
 ramstage-y += cpucp_load_reset.c
 
 ################################################################################

From 830a887ecb713ebddd3a4220f1389f00c64204c8 Mon Sep 17 00:00:00 2001
From: Subrata Banik <subratabanik@google.com>
Date: Tue, 27 May 2025 09:36:52 +0000
Subject: [PATCH 1176/3886] mb/google/bluey: Add WLAN and SSD PCI devices to
 devicetree

This commit updates the devicetree for the Google Bluey mainboard
to include entries for the WLAN and SSD PCI devices.

These devices are located on the x1p42100 SoC's PCI domain 0:
- WLAN: device pci 04.0
- SSD:  device pci 06.0

BUG=b:404985109
TEST=Able to build google/bluey.

Change-Id: If0a9491f4178ee9a44c04aea1330b6522dfd9bf0
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87859
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/google/bluey/devicetree.cb | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/src/mainboard/google/bluey/devicetree.cb b/src/mainboard/google/bluey/devicetree.cb
index 7aed490a72..69d0533e0e 100644
--- a/src/mainboard/google/bluey/devicetree.cb
+++ b/src/mainboard/google/bluey/devicetree.cb
@@ -3,5 +3,7 @@
 chip soc/qualcomm/x1p42100
 	device cpu_cluster 0 on end
 	device domain 0 on
+		device pci 04.0 on end # WLAN
+		device pci 06.0 on end # SSD
 	end
 end

From 6c87853a83835c731808c90dc1e93315ee0cff40 Mon Sep 17 00:00:00 2001
From: Subrata Banik <subratabanik@google.com>
Date: Tue, 27 May 2025 10:20:04 +0000
Subject: [PATCH 1177/3886] mb/google/bluey: Implement board and SKU ID
 retrieval

This commit populates the `board_id()` and `sku_id()` functions
for the Google Bluey mainboard, replacing the previous placeholder
implementations.

- The Board ID (`board_id()`) is now determined by reading a set of
  four GPIO pins (GPIO138 as MSB, GPIO137, GPIO136, GPIO135 as LSB)
  and interpreting their states as a base-3 encoded value using
  the `gpio_base3_value()` helper.

- The SKU ID (`sku_id()`) is retrieved from the Google ChromeEC
  by calling `google_chromeec_get_board_sku()` when a ChromeEC
  is configured (`CONFIG(EC_GOOGLE_CHROMEEC)`).

Both ID values are cached after their initial determination to
avoid redundant reads.

BUG=b:404985109
TEST=Able to build google/bluey

Change-Id: Ic5a084e35b33a82fef76f33c2663aba7a48c16a7
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87861
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Pranava Y N <pranavayn@google.com>
---
 src/mainboard/google/bluey/boardid.c | 22 ++++++++++++++++++++--
 1 file changed, 20 insertions(+), 2 deletions(-)

diff --git a/src/mainboard/google/bluey/boardid.c b/src/mainboard/google/bluey/boardid.c
index b529ff1ec1..c893fdbea5 100644
--- a/src/mainboard/google/bluey/boardid.c
+++ b/src/mainboard/google/bluey/boardid.c
@@ -1,17 +1,35 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
 #include <boardid.h>
+#include <ec/google/chromeec/ec.h>
+#include <gpio.h>
 
 uint32_t board_id(void)
 {
 	static uint32_t id = UNDEFINED_STRAPPING_ID;
-	/* Placeholder */
+	if (id != UNDEFINED_STRAPPING_ID)
+		return id;
+
+	const gpio_t pins[] = {
+		[3] = GPIO(138),
+		[2] = GPIO(137),
+		[1] = GPIO(136),
+		[0] = GPIO(135)
+	};
+
+	id = gpio_base3_value(pins, ARRAY_SIZE(pins));
+
 	return id;
 }
 
 uint32_t sku_id(void)
 {
 	static uint32_t id = UNDEFINED_STRAPPING_ID;
-	/* Placeholder */
+	if (id != UNDEFINED_STRAPPING_ID)
+		return id;
+
+	if (CONFIG(EC_GOOGLE_CHROMEEC))
+		id = google_chromeec_get_board_sku();
+
 	return id;
 }

From 3b684086939ec40a9317ce96601b2178d8e48422 Mon Sep 17 00:00:00 2001
From: Kun Liu <liukun11@huaqin.corp-partner.google.com>
Date: Mon, 26 May 2025 10:09:44 +0800
Subject: [PATCH 1178/3886] mb/google/trulo/var/pujjocento: Configure USB
 related settings

Modify USB related settings according to the proto schematic diagram.

BUG=b:409254508
BRANCH=none
TEST=emerge-nissa coreboot chromeos-bootimage,tested USBA and TYPEC function is ok.

Change-Id: I48ec269b612602578b35eeaedffd1a3d311bb97e
Signed-off-by: Kun Liu <liukun11@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87834
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 .../brya/variants/pujjocento/overridetree.cb  | 67 ++++++++++++++-----
 1 file changed, 51 insertions(+), 16 deletions(-)

diff --git a/src/mainboard/google/brya/variants/pujjocento/overridetree.cb b/src/mainboard/google/brya/variants/pujjocento/overridetree.cb
index e362c2ddaf..517d210598 100644
--- a/src/mainboard/google/brya/variants/pujjocento/overridetree.cb
+++ b/src/mainboard/google/brya/variants/pujjocento/overridetree.cb
@@ -42,15 +42,15 @@ chip soc/intel/alderlake
 
 	register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC_SKIP)"	# Type-C MB (7.5 inch)
 	register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC_SKIP)"	# Type-C DB (7.1 inch)
-	register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)"		# Type-A MB (6.4 inch)
-	register "usb2_ports[3]" = "USB2_PORT_MID(OC_SKIP)"		# Type-A DB (6.2 inch)
+	register "usb2_ports[2]" = "USB2_PORT_MID(OC1)"		# Type-A MB (6.4 inch)
+	register "usb2_ports[3]" = "USB2_PORT_MID(OC2)"		# Type-A DB (6.2 inch)
 	register "usb2_ports[4]" = "USB2_PORT_SHORT(OC_SKIP)"	# LTE (3.3 inch)
 	register "usb2_ports[5]" = "USB2_PORT_SHORT(OC_SKIP)"	# UFC (3.7 inch)
 	register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)"	# Bluetooth port for PCIe WLAN (2.5 inch)
 	register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)"	# Bluetooth port for CNVi WLAN
 
-	register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)"	# USB3 Type-A port A0(MLB))
-	register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)"	# USB3 Type-A port A1(DB)
+	register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC1)"	# USB3 Type-A port A0(MLB))
+	register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC2)"	# USB3 Type-A port A1(DB)
 	register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)"	# USB3 WWAN(LTE)
 
 	register "tcss_ports[0]" = "TCSS_PORT_DEFAULT(OC_SKIP)"
@@ -157,7 +157,6 @@ chip soc/intel/alderlake
 	}"
 
 	device domain 0 on
-		device ref igpu on end
 		device ref dtt on
 			chip drivers/intel/dptf
 				## sensor information
@@ -323,6 +322,43 @@ chip soc/intel/alderlake
 				end
 			end
 		end
+		device ref igpu on
+			chip drivers/gfx/generic
+				register "device_count" = "4"
+				# DDIA for eDP
+				register "device[0].name" = ""LCD0""
+				# Internal panel on the first port of the graphics chip
+				register "device[0].type" = "panel"
+				# DDIB for HDMI
+				# If HDMI is not enumerated in the kernel, then no GFX device should be added for DDIB
+				register "device[1].name" = ""DD01""
+				# TCP0 (DP-1) for port C0
+				register "device[2].name" = ""DD02""
+				register "device[2].use_pld" = "true"
+				register "device[2].pld" = "ACPI_PLD_TYPE_C(RIGHT, LEFT, ACPI_PLD_GROUP(1, 1))"
+				# TCP1 (DP-2) for port C1
+				register "device[3].name" = ""DD03""
+				register "device[3].use_pld" = "true"
+				register "device[3].pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(2, 1))"
+				device generic 0 on end
+			end
+		end
+		device ref pmc hidden
+			chip drivers/intel/pmc_mux
+				device generic 0 on
+					chip drivers/intel/pmc_mux/conn
+						use usb2_port1 as usb2_port
+						use tcss_usb3_port1 as usb3_port
+						device generic 0 alias conn0 on end
+					end
+					chip drivers/intel/pmc_mux/conn
+						use usb2_port2 as usb2_port
+						use tcss_usb3_port2 as usb3_port
+						device generic 1 alias conn1 on end
+					end
+				end
+			end
+		end
 		device ref tcss_xhci on
 			chip drivers/usb/acpi
 				device ref tcss_root_hub on
@@ -330,14 +366,14 @@ chip soc/intel/alderlake
 						register "desc" = ""USB3 Type-C Port C0 (MLB)""
 						register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
 						register "use_custom_pld" = "true"
-						register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(1, 1))"
+						register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, LEFT, ACPI_PLD_GROUP(1, 1))"
 						device ref tcss_usb3_port1 on end
 					end
 					chip drivers/usb/acpi
-						register "desc" = ""USB3 Type-C Port C1 (MLB)""
+						register "desc" = ""USB3 Type-C Port C1 (DB)""
 						register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
 						register "use_custom_pld" = "true"
-						register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, RIGHT, ACPI_PLD_GROUP(2, 1))"
+						register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(2, 1))"
 						device ref tcss_usb3_port2 on end
 					end
 				end
@@ -350,28 +386,28 @@ chip soc/intel/alderlake
 						register "desc" = ""USB2 Type-C Port C0 (MLB)""
 						register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
 						register "use_custom_pld" = "true"
-						register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(1, 1))"
+						register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, LEFT, ACPI_PLD_GROUP(1, 1))"
 						device ref usb2_port1 on end
 					end
 					chip drivers/usb/acpi
-						register "desc" = ""USB2 Type-C Port C1 (MLB)""
+						register "desc" = ""USB2 Type-C Port C1 (DB)""
 						register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
 						register "use_custom_pld" = "true"
-						register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, RIGHT, ACPI_PLD_GROUP(2, 1))"
+						register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(2, 1))"
 						device ref usb2_port2 on end
 					end
 					chip drivers/usb/acpi
 						register "desc" = ""USB2 Type-A Port A0 (MLB)""
 						register "type" = "UPC_TYPE_A"
 						register "use_custom_pld" = "true"
-						register "custom_pld" = "ACPI_PLD_TYPE_A(LEFT, RIGHT, ACPI_PLD_GROUP(3, 1))"
+						register "custom_pld" = "ACPI_PLD_TYPE_A(RIGHT, RIGHT, ACPI_PLD_GROUP(3, 1))"
 						device ref usb2_port3 on end
 					end
 					chip drivers/usb/acpi
 						register "desc" = ""USB2 Type-A Port A1 (DB)""
 						register "type" = "UPC_TYPE_A"
 						register "use_custom_pld" = "true"
-						register "custom_pld" = "ACPI_PLD_TYPE_A(RIGHT, LEFT, ACPI_PLD_GROUP(4, 1))"
+						register "custom_pld" = "ACPI_PLD_TYPE_A(LEFT, CENTER, ACPI_PLD_GROUP(4, 1))"
 						device ref usb2_port4 on end
 					end
 					chip drivers/usb/acpi
@@ -406,14 +442,14 @@ chip soc/intel/alderlake
 						register "desc" = ""USB3 Type-A Port A0 (MLB)""
 						register "type" = "UPC_TYPE_USB3_A"
 						register "use_custom_pld" = "true"
-						register "custom_pld" = "ACPI_PLD_TYPE_A(LEFT, RIGHT, ACPI_PLD_GROUP(3, 1))"
+						register "custom_pld" = "ACPI_PLD_TYPE_A(RIGHT, RIGHT, ACPI_PLD_GROUP(3, 1))"
 						device ref usb3_port1 on end
 					end
 					chip drivers/usb/acpi
 						register "desc" = ""USB3 Type-A Port A1 (DB)""
 						register "type" = "UPC_TYPE_USB3_A"
 						register "use_custom_pld" = "true"
-						register "custom_pld" = "ACPI_PLD_TYPE_A(RIGHT, LEFT, ACPI_PLD_GROUP(4, 1))"
+						register "custom_pld" = "ACPI_PLD_TYPE_A(LEFT, CENTER, ACPI_PLD_GROUP(4, 1))"
 						device ref usb3_port2 on end
 					end
 					chip drivers/usb/acpi
@@ -632,7 +668,6 @@ chip soc/intel/alderlake
 				device pnp 0c09.0 on end
 			end
 		end
-		device ref pmc hidden end
 		device ref hda on
 			chip drivers/sof
 				register "spkr_tplg" = "max98360a"

From 16ff3b33cec7d598be47102e157d8d7d2dadc222 Mon Sep 17 00:00:00 2001
From: Mengqi Zhang <mengqi.zhang@mediatek.corp-partner.google.com>
Date: Mon, 3 Mar 2025 16:20:06 +0800
Subject: [PATCH 1179/3886] mb/google/skywalker: Add SD card configurations

Pass SD card detect GPIO to payloads for SD card detection and configure
SD card in ramstage. Currently, only Skywalker supports the SD card.

BUG=b:379008996
BRANCH=none
TEST=Build pass. Check storage in depthcharge.
firmware-shell: storage init
*  0: UFS LUN 0
   1: removable mtk_mmc

Signed-off-by: Mengqi Zhang <mengqi.zhang@mediatek.corp-partner.google.com>
Change-Id: I3b198d5e237006c299581ab4a5da8577dbcca7a6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87884
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/google/skywalker/Kconfig     | 5 +++++
 src/mainboard/google/skywalker/chromeos.c  | 7 +++++++
 src/mainboard/google/skywalker/mainboard.c | 5 +++++
 3 files changed, 17 insertions(+)

diff --git a/src/mainboard/google/skywalker/Kconfig b/src/mainboard/google/skywalker/Kconfig
index b5134a529a..49b3d21718 100644
--- a/src/mainboard/google/skywalker/Kconfig
+++ b/src/mainboard/google/skywalker/Kconfig
@@ -9,6 +9,9 @@ config BOARD_GOOGLE_SKYWALKER_COMMON
 
 if BOARD_GOOGLE_SKYWALKER_COMMON
 
+config SKYWALKER_SDCARD_INIT
+	def_bool BOARD_GOOGLE_SKYWALKER
+
 config VBOOT
 	select EC_GOOGLE_CHROMEEC_SWITCHES
 	select VBOOT_VBNV_FLASH
@@ -31,6 +34,8 @@ config BOARD_SPECIFIC_OPTIONS
 	select FW_CONFIG
 	select FW_CONFIG_SOURCE_CHROMEEC_CBI
 	select RTC
+	select COMMONLIB_STORAGE
+	select COMMONLIB_STORAGE_MMC
 
 config MAINBOARD_DIR
 	string
diff --git a/src/mainboard/google/skywalker/chromeos.c b/src/mainboard/google/skywalker/chromeos.c
index c5b9f8ee16..26f06442d9 100644
--- a/src/mainboard/google/skywalker/chromeos.c
+++ b/src/mainboard/google/skywalker/chromeos.c
@@ -41,6 +41,13 @@ void fill_lb_gpios(struct lb_gpios *gpios)
 		{GPIO_GSC_AP_INT_ODL.id, ACTIVE_HIGH, -1, "TPM interrupt"},
 	};
 	lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios));
+
+	if (CONFIG(SKYWALKER_SDCARD_INIT)) {
+		struct lb_gpio sd_card_gpios[] = {
+			{ GPIO_SD_CD_ODL.id, ACTIVE_LOW, -1, "SD card detect" },
+		};
+		lb_add_gpios(gpios, sd_card_gpios, ARRAY_SIZE(sd_card_gpios));
+	}
 }
 
 int cr50_plat_irq_status(void)
diff --git a/src/mainboard/google/skywalker/mainboard.c b/src/mainboard/google/skywalker/mainboard.c
index af27c8268c..74c3ea715f 100644
--- a/src/mainboard/google/skywalker/mainboard.c
+++ b/src/mainboard/google/skywalker/mainboard.c
@@ -4,6 +4,8 @@
 #include <gpio.h>
 #include <soc/bl31.h>
 #include <soc/dpm_v2.h>
+#include <soc/msdc.h>
+#include <soc/mt6359p.h>
 #include <soc/spm_common.h>
 #include <soc/usb.h>
 
@@ -23,6 +25,9 @@ static void mainboard_init(struct device *dev)
 	spm_init();
 	power_on_fpmcu();
 
+	if (CONFIG(SKYWALKER_SDCARD_INIT))
+		mtk_msdc_configure_sdcard();
+
 	if (CONFIG(ARM64_USE_ARM_TRUSTED_FIRMWARE))
 		register_reset_to_bl31(GPIO_AP_EC_WARM_RST_REQ.id, true);
 }

From 623caa537ff33c08aa8c242fb4b1d7e901f47e45 Mon Sep 17 00:00:00 2001
From: Cyril Chao <cyril.chao@mediatek.corp-partner.google.com>
Date: Sat, 29 Mar 2025 14:05:12 +0800
Subject: [PATCH 1180/3886] mb/google/skywalker: Add RT9123 support for beep
 sound

Derive the audio amplifier from FW_CONFIG, and set up I2S for RT9123.
Also pass the corresponding GPIO to the payload.

BUG=b:359705470
BRANCH=none
TEST=Build pass and test with Depthcahrge change:
https://chromium-review.googlesource.com/c/chromiumos/platform/depthcharge/+/6437675
https://chromium-review.googlesource.com/c/chromiumos/platform/depthcharge/+/6437676
Check audio cmd in depthcharge with:
firmware-shell: AUDIO CMD=audio 500 100 1

Signed-off-by: Cyril Chao <cyril.chao@mediatek.corp-partner.google.com>
Change-Id: I3b9b347ad8b754cbc02d942da9a7b0886c4c3cc4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87885
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
---
 src/mainboard/google/skywalker/chromeos.c    |  9 ++++++
 src/mainboard/google/skywalker/devicetree.cb |  6 ++++
 src/mainboard/google/skywalker/gpio.h        |  4 +++
 src/mainboard/google/skywalker/mainboard.c   | 30 ++++++++++++++++++++
 4 files changed, 49 insertions(+)

diff --git a/src/mainboard/google/skywalker/chromeos.c b/src/mainboard/google/skywalker/chromeos.c
index 26f06442d9..9b5a9c0745 100644
--- a/src/mainboard/google/skywalker/chromeos.c
+++ b/src/mainboard/google/skywalker/chromeos.c
@@ -3,6 +3,7 @@
 #include <boot/coreboot_tables.h>
 #include <drivers/tpm/cr50.h>
 #include <ec/google/chromeec/ec.h>
+#include <fw_config.h>
 #include <gpio.h>
 
 #include "gpio.h"
@@ -31,6 +32,7 @@ void setup_chromeos_gpios(void)
 	gpio_output(GPIO_AP_FP_FW_UP_STRAP, 0);
 	gpio_output(GPIO_EN_PWR_FP, 0);
 	gpio_output(GPIO_FP_RST_1V8_S3_L, 0);
+	gpio_output(GPIO_EN_SPKR, 0);
 }
 
 void fill_lb_gpios(struct lb_gpios *gpios)
@@ -48,6 +50,13 @@ void fill_lb_gpios(struct lb_gpios *gpios)
 		};
 		lb_add_gpios(gpios, sd_card_gpios, ARRAY_SIZE(sd_card_gpios));
 	}
+
+	if (fw_config_probe(FW_CONFIG(AUDIO_AMP, AMP_RT9123))) {
+		struct lb_gpio rt9123_gpios[] = {
+			{GPIO_EN_SPKR.id, ACTIVE_HIGH, -1, "rt9123_spk_en"},
+		};
+		lb_add_gpios(gpios, rt9123_gpios, ARRAY_SIZE(rt9123_gpios));
+	}
 }
 
 int cr50_plat_irq_status(void)
diff --git a/src/mainboard/google/skywalker/devicetree.cb b/src/mainboard/google/skywalker/devicetree.cb
index c76b4e6141..6ec4e25c37 100644
--- a/src/mainboard/google/skywalker/devicetree.cb
+++ b/src/mainboard/google/skywalker/devicetree.cb
@@ -3,3 +3,9 @@
 chip soc/mediatek/mt8189
 	device cpu_cluster 0 on end
 end
+
+fw_config
+	field AUDIO_AMP 25 27
+		option AMP_RT9123 0
+	end
+end
diff --git a/src/mainboard/google/skywalker/gpio.h b/src/mainboard/google/skywalker/gpio.h
index 8a1925a635..208a3d9ef0 100644
--- a/src/mainboard/google/skywalker/gpio.h
+++ b/src/mainboard/google/skywalker/gpio.h
@@ -27,6 +27,10 @@
 #define GPIO_SD_CD_ODL			GPIO(GBE_INTR)
 #define GPIO_HDMI_HPD_1V8_ODL		GPIO(CONN_TOP_CLK)
 #define GPIO_AP_HDMI_RST_ODL		GPIO(GBE_TXC)
+#define GPIO_EN_SPKR			GPIO(GPIO05)
+#define GPIO_I2SOUT1_BCK		GPIO(DMIC0_DAT0)
+#define GPIO_I2SOUT1_LRCK		GPIO(DMIC1_CLK)
+#define GPIO_I2SOUT1_DOUT		GPIO(DMIC1_DAT0)
 
 void setup_chromeos_gpios(void);
 
diff --git a/src/mainboard/google/skywalker/mainboard.c b/src/mainboard/google/skywalker/mainboard.c
index 74c3ea715f..f6dc5cafa2 100644
--- a/src/mainboard/google/skywalker/mainboard.c
+++ b/src/mainboard/google/skywalker/mainboard.c
@@ -1,16 +1,45 @@
 /* SPDX-License-Identifier: GPL-2.0-only OR MIT */
 
 #include <device/device.h>
+#include <device/mmio.h>
+#include <fw_config.h>
 #include <gpio.h>
 #include <soc/bl31.h>
 #include <soc/dpm_v2.h>
 #include <soc/msdc.h>
 #include <soc/mt6359p.h>
+#include <soc/mtcmos.h>
 #include <soc/spm_common.h>
 #include <soc/usb.h>
 
 #include "gpio.h"
 
+#define AFE_SE_SECURE_CON1	(AUDIO_BASE + 0x5634)
+
+static void configure_rt9123(void)
+{
+	/* SoC I2S */
+	gpio_set_mode(GPIO_I2SOUT1_BCK, GPIO_FUNC(DMIC0_DAT0, I2SOUT1_BCK));
+	gpio_set_mode(GPIO_I2SOUT1_LRCK, GPIO_FUNC(DMIC1_CLK, I2SOUT1_LRCK));
+	gpio_set_mode(GPIO_I2SOUT1_DOUT, GPIO_FUNC(DMIC1_DAT0, I2SOUT1_DO));
+
+	printk(BIOS_INFO, "%s: AMP configuration done\n", __func__);
+}
+
+static void configure_audio(void)
+{
+	mtcmos_audio_power_on();
+	mtcmos_protect_audio_bus();
+
+	/* Switch to normal mode */
+	write32p(AFE_SE_SECURE_CON1, 0x0);
+
+	if (fw_config_probe(FW_CONFIG(AUDIO_AMP, AMP_RT9123)))
+		configure_rt9123();
+	else
+		printk(BIOS_WARNING, "Unknown amp\n");
+}
+
 static void power_on_fpmcu(void)
 {
 	/* Power on the fingerprint MCU */
@@ -24,6 +53,7 @@ static void mainboard_init(struct device *dev)
 	setup_usb_host();
 	spm_init();
 	power_on_fpmcu();
+	configure_audio();
 
 	if (CONFIG(SKYWALKER_SDCARD_INIT))
 		mtk_msdc_configure_sdcard();

From 4caf5131b96b40fbe0357ce5b69b2131c3f5a83d Mon Sep 17 00:00:00 2001
From: Cyril Chao <cyril.chao@mediatek.corp-partner.google.com>
Date: Sat, 29 Mar 2025 14:21:25 +0800
Subject: [PATCH 1181/3886] mb/google/skywalker: Add ALC5645 support for beep
 sound

Derive the audio amplifier from FW_CONFIG, and set up I2C and I2S
for ALC5645. Also pass the corresponding GPIO to the payload.

BUG=b:359705470
BRANCH=none
TEST=build ok and test audio cmd ok
AUDIO CMD=audio 500 100 1

Signed-off-by: Cyril Chao <cyril.chao@mediatek.corp-partner.google.com>
Change-Id: Ib53175f559eecb3d8b5104b12dabfd4793f65d08
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87886
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
---
 src/mainboard/google/skywalker/chromeos.c    |  5 +++++
 src/mainboard/google/skywalker/devicetree.cb |  1 +
 src/mainboard/google/skywalker/gpio.h        |  4 ++++
 src/mainboard/google/skywalker/mainboard.c   | 17 +++++++++++++++++
 4 files changed, 27 insertions(+)

diff --git a/src/mainboard/google/skywalker/chromeos.c b/src/mainboard/google/skywalker/chromeos.c
index 9b5a9c0745..36be542606 100644
--- a/src/mainboard/google/skywalker/chromeos.c
+++ b/src/mainboard/google/skywalker/chromeos.c
@@ -56,6 +56,11 @@ void fill_lb_gpios(struct lb_gpios *gpios)
 			{GPIO_EN_SPKR.id, ACTIVE_HIGH, -1, "rt9123_spk_en"},
 		};
 		lb_add_gpios(gpios, rt9123_gpios, ARRAY_SIZE(rt9123_gpios));
+	} else if (fw_config_probe(FW_CONFIG(AUDIO_AMP, AMP_ALC5645))) {
+		struct lb_gpio alc5645_gpios[] = {
+			{GPIO_EN_SPKR.id, ACTIVE_HIGH, -1, "alc5645_spk_en"},
+		};
+		lb_add_gpios(gpios, alc5645_gpios, ARRAY_SIZE(alc5645_gpios));
 	}
 }
 
diff --git a/src/mainboard/google/skywalker/devicetree.cb b/src/mainboard/google/skywalker/devicetree.cb
index 6ec4e25c37..bb54417867 100644
--- a/src/mainboard/google/skywalker/devicetree.cb
+++ b/src/mainboard/google/skywalker/devicetree.cb
@@ -7,5 +7,6 @@ end
 fw_config
 	field AUDIO_AMP 25 27
 		option AMP_RT9123 0
+		option AMP_ALC5645 3
 	end
 end
diff --git a/src/mainboard/google/skywalker/gpio.h b/src/mainboard/google/skywalker/gpio.h
index 208a3d9ef0..4398a6cbf3 100644
--- a/src/mainboard/google/skywalker/gpio.h
+++ b/src/mainboard/google/skywalker/gpio.h
@@ -31,6 +31,10 @@
 #define GPIO_I2SOUT1_BCK		GPIO(DMIC0_DAT0)
 #define GPIO_I2SOUT1_LRCK		GPIO(DMIC1_CLK)
 #define GPIO_I2SOUT1_DOUT		GPIO(DMIC1_DAT0)
+#define GPIO_I2SOUT0_MCK		GPIO(I2SOUT0_MCK)
+#define GPIO_I2SOUT0_BCK		GPIO(I2SOUT0_BCK)
+#define GPIO_I2SOUT0_LRCK		GPIO(I2SOUT0_LRCK)
+#define GPIO_I2SOUT0_DOUT		GPIO(I2SOUT0_DO)
 
 void setup_chromeos_gpios(void);
 
diff --git a/src/mainboard/google/skywalker/mainboard.c b/src/mainboard/google/skywalker/mainboard.c
index f6dc5cafa2..bd1829904a 100644
--- a/src/mainboard/google/skywalker/mainboard.c
+++ b/src/mainboard/google/skywalker/mainboard.c
@@ -6,6 +6,7 @@
 #include <gpio.h>
 #include <soc/bl31.h>
 #include <soc/dpm_v2.h>
+#include <soc/i2c.h>
 #include <soc/msdc.h>
 #include <soc/mt6359p.h>
 #include <soc/mtcmos.h>
@@ -26,6 +27,20 @@ static void configure_rt9123(void)
 	printk(BIOS_INFO, "%s: AMP configuration done\n", __func__);
 }
 
+static void configure_alc5645(void)
+{
+	/* SoC I2S */
+	gpio_set_mode(GPIO_I2SOUT0_MCK, GPIO_FUNC(I2SOUT0_MCK, I2SOUT0_MCK));
+	gpio_set_mode(GPIO_I2SOUT0_BCK, GPIO_FUNC(I2SOUT0_BCK, I2SOUT0_BCK));
+	gpio_set_mode(GPIO_I2SOUT0_LRCK, GPIO_FUNC(I2SOUT0_LRCK, I2SOUT0_LRCK));
+	gpio_set_mode(GPIO_I2SOUT0_DOUT, GPIO_FUNC(I2SOUT0_DO, I2SOUT0_DO));
+
+	/* Init I2C bus timing register for audio codecs */
+	mtk_i2c_bus_init(I2C2, I2C_SPEED_STANDARD);
+
+	printk(BIOS_INFO, "%s: AMP configuration done\n", __func__);
+}
+
 static void configure_audio(void)
 {
 	mtcmos_audio_power_on();
@@ -36,6 +51,8 @@ static void configure_audio(void)
 
 	if (fw_config_probe(FW_CONFIG(AUDIO_AMP, AMP_RT9123)))
 		configure_rt9123();
+	else if (fw_config_probe(FW_CONFIG(AUDIO_AMP, AMP_ALC5645)))
+		configure_alc5645();
 	else
 		printk(BIOS_WARNING, "Unknown amp\n");
 }

From 69a067a9d62c8ec25dfa1da0410d1b78871e6531 Mon Sep 17 00:00:00 2001
From: Rui Zhou <zhourui@huaqin.corp-partner.google.com>
Date: Tue, 20 May 2025 16:30:01 +0800
Subject: [PATCH 1182/3886] mb/google/skywalker: Add RT1019 support for beep
 sound

Derive the audio amplifier from FW_CONFIG, and set up I2C and I2S for
RT1019.RT1019 and RT9123 use the same GPIOs on the Skywalker reference
design, so the same function is used to improve code reusability. Also
pass the corresponding GPIO to the payload.

BUG=b:417083722
BRANCH=none
TEST=Build pass and test with Depthcharge change:
https://chromium-review.googlesource.com/c/chromiumos/platform/depthcharge/+/6437675
Check audio cmd in depthcharge with:
firmware-shell: AUDIO CMD=audio 500 100 1

Change-Id: I512cd5c8635d08c6b6c54f04d11bf87c64d1b843
Signed-off-by: Rui Zhou <zhourui@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87887
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
---
 src/mainboard/google/skywalker/chromeos.c    | 5 +++++
 src/mainboard/google/skywalker/devicetree.cb | 1 +
 src/mainboard/google/skywalker/mainboard.c   | 7 ++++---
 3 files changed, 10 insertions(+), 3 deletions(-)

diff --git a/src/mainboard/google/skywalker/chromeos.c b/src/mainboard/google/skywalker/chromeos.c
index 36be542606..700d815c68 100644
--- a/src/mainboard/google/skywalker/chromeos.c
+++ b/src/mainboard/google/skywalker/chromeos.c
@@ -56,6 +56,11 @@ void fill_lb_gpios(struct lb_gpios *gpios)
 			{GPIO_EN_SPKR.id, ACTIVE_HIGH, -1, "rt9123_spk_en"},
 		};
 		lb_add_gpios(gpios, rt9123_gpios, ARRAY_SIZE(rt9123_gpios));
+	} else if (fw_config_probe(FW_CONFIG(AUDIO_AMP, AMP_RT1019))) {
+		struct lb_gpio rt1019_gpios[] = {
+			{GPIO_EN_SPKR.id, ACTIVE_HIGH, -1, "rt1019_spk_en"},
+		};
+		lb_add_gpios(gpios, rt1019_gpios, ARRAY_SIZE(rt1019_gpios));
 	} else if (fw_config_probe(FW_CONFIG(AUDIO_AMP, AMP_ALC5645))) {
 		struct lb_gpio alc5645_gpios[] = {
 			{GPIO_EN_SPKR.id, ACTIVE_HIGH, -1, "alc5645_spk_en"},
diff --git a/src/mainboard/google/skywalker/devicetree.cb b/src/mainboard/google/skywalker/devicetree.cb
index bb54417867..92f9c5d9e3 100644
--- a/src/mainboard/google/skywalker/devicetree.cb
+++ b/src/mainboard/google/skywalker/devicetree.cb
@@ -7,6 +7,7 @@ end
 fw_config
 	field AUDIO_AMP 25 27
 		option AMP_RT9123 0
+		option AMP_RT1019 1
 		option AMP_ALC5645 3
 	end
 end
diff --git a/src/mainboard/google/skywalker/mainboard.c b/src/mainboard/google/skywalker/mainboard.c
index bd1829904a..652d81253f 100644
--- a/src/mainboard/google/skywalker/mainboard.c
+++ b/src/mainboard/google/skywalker/mainboard.c
@@ -17,7 +17,7 @@
 
 #define AFE_SE_SECURE_CON1	(AUDIO_BASE + 0x5634)
 
-static void configure_rt9123(void)
+static void configure_rt9123_rt1019(void)
 {
 	/* SoC I2S */
 	gpio_set_mode(GPIO_I2SOUT1_BCK, GPIO_FUNC(DMIC0_DAT0, I2SOUT1_BCK));
@@ -49,8 +49,9 @@ static void configure_audio(void)
 	/* Switch to normal mode */
 	write32p(AFE_SE_SECURE_CON1, 0x0);
 
-	if (fw_config_probe(FW_CONFIG(AUDIO_AMP, AMP_RT9123)))
-		configure_rt9123();
+	if (fw_config_probe(FW_CONFIG(AUDIO_AMP, AMP_RT9123)) ||
+	    fw_config_probe(FW_CONFIG(AUDIO_AMP, AMP_RT1019)))
+		configure_rt9123_rt1019();
 	else if (fw_config_probe(FW_CONFIG(AUDIO_AMP, AMP_ALC5645)))
 		configure_alc5645();
 	else

From 1840fb49e07ba4b3c3345b9099376727f98d05a7 Mon Sep 17 00:00:00 2001
From: Kun Liu <liukun11@huaqin.corp-partner.google.com>
Date: Fri, 30 May 2025 16:47:56 +0800
Subject: [PATCH 1183/3886] mb/google/trulo/var/pujjocento: Update gpio setting
 for DDI-B

Modify according to the hardware schematic(MB-0529A) as follows:

GPP_A20 ---> GPP_A18
GPP_E20 ---> GPP_H15
GPP_E21 ---> GPP_H17

BUG=b:409254508
BRANCH=none
TEST=emerge-nissa coreboot chromeos-bootimage.

Change-Id: I61ef761df7936fb42d4fe68a2b5cd2fa649b7b33
Signed-off-by: Kun Liu <liukun11@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87900
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
---
 .../google/brya/variants/pujjocento/gpio.c       | 16 ++++++++--------
 1 file changed, 8 insertions(+), 8 deletions(-)

diff --git a/src/mainboard/google/brya/variants/pujjocento/gpio.c b/src/mainboard/google/brya/variants/pujjocento/gpio.c
index ea8d9bbe2d..3df21e79b6 100644
--- a/src/mainboard/google/brya/variants/pujjocento/gpio.c
+++ b/src/mainboard/google/brya/variants/pujjocento/gpio.c
@@ -38,12 +38,12 @@ static const struct pad_config gpio_table[] = {
 	PAD_NC_LOCK(GPP_A16, NONE, LOCK_CONFIG),
 	/* A17 : NC */
 	PAD_NC(GPP_A17, NONE),
-	/* A18 : NC */
-	PAD_NC(GPP_A18, NONE),
+	/* A18 : NC ==> HDMI_HPD_SRC*/
+	PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1),
 	/* A19 : NC */
 	PAD_NC(GPP_A19, NONE),
-	/* A20 : DDSP_HPD2 ==> SOC_HDMI_HPD */
-	PAD_CFG_NF(GPP_A20, NONE, DEEP, NF1),
+	/* A20 : DDSP_HPD2 ==> NC */
+	PAD_NC(GPP_A20, NONE),
 	/* A21 : GPP_A21 ==> USB_C1_AUX_DC_P */
 	PAD_CFG_NF(GPP_A21, NONE, DEEP, NF6),
 	/* A22 : GPP_A22 ==> USB_C1_AUX_DC_N */
@@ -198,10 +198,10 @@ static const struct pad_config gpio_table[] = {
 	PAD_NC(GPP_E18, NONE),
 	/* E19 : DDP1_CTRLDATA ==> GPP_E19_STRAP */
 	PAD_NC(GPP_E19, NONE),
-	/* E20 : DDP2_CTRLCLK ==> HDMI_DDC_SCL */
-	PAD_CFG_NF(GPP_E20, NONE, DEEP, NF1),
-	/* E21 : DDP2_CTRLDATA ==> HDMI_DDC_SDA_STRAP */
-	PAD_CFG_NF(GPP_E21, NONE, DEEP, NF1),
+	/* E20 : DDP2_CTRLCLK ==> NC */
+	PAD_NC(GPP_E20, NONE),
+	/* E21 : DDP2_CTRLDATA ==> NC */
+	PAD_NC(GPP_E21, NONE),
 	/* E22 : DDPA_CTRLCLK ==> USB_C0_AUX_DC_P */
 	PAD_CFG_NF(GPP_E22, NONE, DEEP, NF6),
 	/* E23 : DDPA_CTRLDATA ==> USB_C0_AUX_DC_N */

From 99e0484000953aeb661a071ec9fa92586fcce694 Mon Sep 17 00:00:00 2001
From: Subrata Banik <subratabanik@google.com>
Date: Fri, 30 May 2025 20:56:40 +0530
Subject: [PATCH 1184/3886] mb/google/bluey: Increase bootblock size to 120KB

The bootblock size for the Google Bluey mainboard has been increased
from 96KB to 120KB.

This change is necessary to accommodate the growing size of the
bootblock image, which now exceeds the previous 96KB limit. This
expansion ensures that the complete bootblock code, including critical
initialization routines and potentially new features, fits within its
allocated flash region.

TEST=Able to build google/quenbi.

Change-Id: I7bf2c8c6c540327f1b4233ee5ba4e0703d1200f9
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87903
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/google/bluey/chromeos.fmd | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/mainboard/google/bluey/chromeos.fmd b/src/mainboard/google/bluey/chromeos.fmd
index 0ad818b6db..1bea2f9397 100644
--- a/src/mainboard/google/bluey/chromeos.fmd
+++ b/src/mainboard/google/bluey/chromeos.fmd
@@ -3,7 +3,7 @@
 FLASH@0x0 CONFIG_ROM_SIZE {
 	WP_RO 4M {
 		RO_SECTION 0x3c4000 {
-			BOOTBLOCK 96K
+			BOOTBLOCK 120K
 			COREBOOT(CBFS)
 			FMAP@0x3c0000 0x1000
 			GBB 0x2f00

From 0cdd4125bea28bdf150fd13067cc8abce0410869 Mon Sep 17 00:00:00 2001
From: Luca Lai <luca.lai@lcfc.corp-partner.google.com>
Date: Mon, 2 Jun 2025 13:27:09 +0800
Subject: [PATCH 1185/3886] mb/trulo/var/pujjolo: Fix touchscreen function and
 boot up issue

1. Add serial_io_i2c_mode to fix can not boot up to OS issue.
2. Change level from low to high to fix parade touchscreen issue.

BUG=b:395763555
BRANCH=none
TEST=Build and boot to pujjolo. Verify functions work.

Change-Id: Ic0a02daa39f4d1d0287115ecab12f45201704227
Signed-off-by: Luca Lai <luca.lai@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87909
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 .../google/brya/variants/pujjolo/overridetree.cb   | 14 ++++++++++++--
 1 file changed, 12 insertions(+), 2 deletions(-)

diff --git a/src/mainboard/google/brya/variants/pujjolo/overridetree.cb b/src/mainboard/google/brya/variants/pujjolo/overridetree.cb
index 2f89d72859..7588a8bfb5 100644
--- a/src/mainboard/google/brya/variants/pujjolo/overridetree.cb
+++ b/src/mainboard/google/brya/variants/pujjolo/overridetree.cb
@@ -62,7 +62,8 @@ chip soc/intel/alderlake
 	#|                   | required to set up a BAR  |
 	#|                   | for TPM communication     |
 	#| I2C1              | Touchscreen               |
-	#| I2C2              | Sub-board(PSensor)/WCAM   |
+	#| I2C2              | Psensor                   |
+	#| I2C4              | Mipi camera               |
 	#| I2C5              | Trackpad                  |
 	#+-------------------+---------------------------+
 	register "common_soc_config" = "{
@@ -114,6 +115,15 @@ chip soc/intel/alderlake
 		},
 	}"
 
+	register "serial_io_i2c_mode" = "{
+		[PchSerialIoIndexI2C0] = PchSerialIoPci,
+		[PchSerialIoIndexI2C1] = PchSerialIoPci,
+		[PchSerialIoIndexI2C2] = PchSerialIoPci,
+		[PchSerialIoIndexI2C3] = PchSerialIoDisabled,
+		[PchSerialIoIndexI2C4] = PchSerialIoPci,
+		[PchSerialIoIndexI2C5] = PchSerialIoPci,
+	}"
+
 	register "serial_io_gspi_mode" = "{
 		[PchSerialIoIndexGSPI0] = PchSerialIoPci,
 		[PchSerialIoIndexGSPI1] = PchSerialIoPci,
@@ -166,7 +176,7 @@ chip soc/intel/alderlake
 			chip drivers/i2c/hid
 				register "generic.hid" = ""PARA3408""
 				register "generic.desc" = ""Parade Touchscreen""
-				register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_E11_IRQ)"
+				register "generic.irq" = "ACPI_IRQ_LEVEL_HIGH(GPP_E11_IRQ)"
 				register "generic.detect" = "1"
 				register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C1)"
 				register "generic.reset_delay_ms" = "20"

From 8e3adf778baeb43f6e582bc227de19229df646db Mon Sep 17 00:00:00 2001
From: Yu-Ping Wu <yupingso@chromium.org>
Date: Mon, 2 Jun 2025 15:09:34 +0800
Subject: [PATCH 1186/3886] soc/mediatek: Add data_version to ddr_base_info
 struct

To sync with the dramc_param_common.h change [1] from MediaTek's DRAM
blob, change the u32 config_dvfs field to u16 and add a new field
data_version. As all MediaTek SoCs using the structure are little endian
and currently only bit 0 is used for the config_dvfs field, this change
is backward compatible. Therefore, each SoC's DRAMC_PARAM_HEADER_VERSION
doesn't need to be bumped.

[1] commit a39b473a0a7d ("common/cros: Support storing data version in
    full-k cached data")

FIXED=415715491
TEST=emerge-skywalker coreboot
BRANCH=none

Change-Id: Ifcda7d360aefe083fc08c974e6dc62d1c9c12b5e
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87912
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/soc/mediatek/common/include/soc/dramc_param_common.h | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/src/soc/mediatek/common/include/soc/dramc_param_common.h b/src/soc/mediatek/common/include/soc/dramc_param_common.h
index f7cf83abae..3c72cb55d3 100644
--- a/src/soc/mediatek/common/include/soc/dramc_param_common.h
+++ b/src/soc/mediatek/common/include/soc/dramc_param_common.h
@@ -90,7 +90,8 @@ enum SDRAM_VOLTAGE_TYPE {
 };
 
 struct ddr_base_info {
-	u32 config_dvfs;		/* SDRAM_DVFS_FLAG */
+	u16 config_dvfs;		/* SDRAM_DVFS_FLAG */
+	u16 data_version;
 	struct sdram_info sdram;
 	u16 lpddr_type;
 	u16 voltage_type;		/* SDRAM_VOLTAGE_TYPE */

From ab8339770eb1418c60660b36202cf4eb2a29cbc8 Mon Sep 17 00:00:00 2001
From: Felix Singer <felix.singer@secunet.com>
Date: Mon, 2 Jun 2025 13:15:40 +0000
Subject: [PATCH 1187/3886] 3rdparty/fsp: Update submodule to upstream master

Updating from commit id 04728fbd192f:
2025-05-07 15:20:18 +0800 - (Edge Platforms ADL-S IPU 2025.3 (6073_02) FSP)

to commit id cc36ae2b5775:
2025-05-28 10:49:43 +0800 - (Edge Platforms RPL-S/RPL-S Refresh IPU 2025.3 (6073_04) FSP)

This brings in 1 new commits:
cc36ae2b5775 Edge Platforms RPL-S/RPL-S Refresh IPU 2025.3 (6073_04) FSP

Change-Id: Ia7d7de0db0669a52890442b3e54ebb1043880ef7
Signed-off-by: Felix Singer <felix.singer@secunet.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87914
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
---
 3rdparty/fsp | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/3rdparty/fsp b/3rdparty/fsp
index 04728fbd19..cc36ae2b57 160000
--- a/3rdparty/fsp
+++ b/3rdparty/fsp
@@ -1 +1 @@
-Subproject commit 04728fbd192fe92abe8df6545a062de3b45dfc42
+Subproject commit cc36ae2b5775fa7400cb3282680afc0f6cb37a3c

From 7690442d88b940fcee8cf280d98bd178fd211623 Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Wed, 28 May 2025 20:21:05 +0100
Subject: [PATCH 1188/3886] mb/starlabs/byte_adl: Tidy the Kconfig selections

This are a bit illogical, so tidy them up.

Change-Id: Idd4f616181949780c042142344b3bbbccc4f15f6
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87894
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/starlabs/byte_adl/Kconfig | 27 +++++++++++++------------
 1 file changed, 14 insertions(+), 13 deletions(-)

diff --git a/src/mainboard/starlabs/byte_adl/Kconfig b/src/mainboard/starlabs/byte_adl/Kconfig
index 0da8f59f40..c1b7121194 100644
--- a/src/mainboard/starlabs/byte_adl/Kconfig
+++ b/src/mainboard/starlabs/byte_adl/Kconfig
@@ -1,33 +1,34 @@
 config BOARD_STARLABS_BYTE_SERIES
 	def_bool n
+	select BOARD_ROMSIZE_KB_16384
+	select CRB_TPM
 	select DRIVERS_EFI_VARIABLE_STORE
+	select DRIVERS_INTEL_PMC
 	select DRIVERS_OPTION_CFR_ENABLED
 	select EC_STARLABS_ITE
+	select EC_STARLABS_MERLIN
+	select EC_STARLABS_NEED_ITE_BIN
+	select FSP_TYPE_IOT
 	select HAVE_ACPI_RESUME
 	select HAVE_ACPI_TABLES
+	select HAVE_INTEL_PTT
 	select HAVE_OPTION_TABLE
 	select INTEL_GMA_HAVE_VBT
 	select INTEL_LPSS_UART_FOR_CONSOLE
 	select NO_UART_ON_SUPERIO
 	select PMC_IPC_ACPI_INTERFACE
 	select SOC_INTEL_COMMON_BLOCK_HDA_VERB
-	select SYSTEM_TYPE_MINIPC
-	select VALIDATE_INTEL_DESCRIPTOR
-
-config BOARD_STARLABS_BYTE_ADL
-	select BOARD_ROMSIZE_KB_16384
-	select BOARD_STARLABS_BYTE_SERIES
-	select CRB_TPM
-	select DRIVERS_INTEL_PMC
-	select EC_STARLABS_MERLIN
-	select EC_STARLABS_NEED_ITE_BIN
-	select HAVE_INTEL_PTT
-	select SOC_INTEL_ALDERLAKE
-	select SOC_INTEL_ALDERLAKE_PCH_N
 	select SOC_INTEL_COMMON_BLOCK_TCSS
 	select SOC_INTEL_CRASHLOG
 	select SPI_FLASH_WINBOND
+	select SYSTEM_TYPE_MINIPC
 	select TPM2
+	select VALIDATE_INTEL_DESCRIPTOR
+
+config BOARD_STARLABS_BYTE_ADL
+	select BOARD_STARLABS_BYTE_SERIES
+	select SOC_INTEL_ALDERLAKE
+	select SOC_INTEL_ALDERLAKE_PCH_N
 
 if BOARD_STARLABS_BYTE_SERIES
 

From 0b1bc3df2c9070b69f89593ce54148e88598b89f Mon Sep 17 00:00:00 2001
From: lizheng <lizheng@huaqin.corp-partner.google.com>
Date: Tue, 3 Jun 2025 11:09:56 +0800
Subject: [PATCH 1189/3886] mb/trulo/var/pujjocento: Support x32 memory
 configuration

Use the GPP_E13 level to determine whether x32 memory configuration
is supported.

BUG=b:422001335
BRANCH=firmware-trulo-15217.771.B
TEST=emerge-nissa coreboot chromeos-bootimage

Change-Id: If1dcffaeb358093f06c4c349a83152a2bdcc16f6
Signed-off-by: lizheng <lizheng@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87925
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kun Liu <liukun11@huaqin.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
---
 src/mainboard/google/brya/Kconfig                  |  1 +
 .../google/brya/variants/pujjocento/gpio.c         |  2 +-
 .../google/brya/variants/pujjocento/memory.c       | 14 ++++++++++++++
 3 files changed, 16 insertions(+), 1 deletion(-)

diff --git a/src/mainboard/google/brya/Kconfig b/src/mainboard/google/brya/Kconfig
index 7da805504f..06adc7f346 100644
--- a/src/mainboard/google/brya/Kconfig
+++ b/src/mainboard/google/brya/Kconfig
@@ -518,6 +518,7 @@ config BOARD_GOOGLE_PUJJOCENTO
 	select BOARD_GOOGLE_BASEBOARD_TRULO
 	select DRIVERS_I2C_SX9324
 	select DRIVERS_I2C_SX9324_SUPPORT_LEGACY_LINUX_DRIVER
+	select ENFORCE_MEM_CHANNEL_DISABLE
 	select HAVE_WWAN_POWER_SEQUENCE
 	select MAINBOARD_HAS_GOOGLE_STRAUSS_KEYBOARD
 	select SOC_INTEL_COMMON_BLOCK_HDA_VERB
diff --git a/src/mainboard/google/brya/variants/pujjocento/gpio.c b/src/mainboard/google/brya/variants/pujjocento/gpio.c
index 3df21e79b6..e079b19981 100644
--- a/src/mainboard/google/brya/variants/pujjocento/gpio.c
+++ b/src/mainboard/google/brya/variants/pujjocento/gpio.c
@@ -451,7 +451,7 @@ static const struct pad_config early_gpio_table[] = {
 	/* H11 : UART0_TXD ==> UART_SOC_TX_DBG_RX */
 	PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2),
 	/* E13 : THC0_SPI1_IO0 ==> SINGLE CHANNEL */
-	PAD_CFG_GPI(GPP_E13, NONE, DEEP),
+	PAD_CFG_GPI_LOCK(GPP_E13, NONE, LOCK_CONFIG),
 	/* H20 : IMGCLKOUT1 ==> WLAN_PERST_L */
 	PAD_CFG_GPO(GPP_H20, 0, DEEP),
 };
diff --git a/src/mainboard/google/brya/variants/pujjocento/memory.c b/src/mainboard/google/brya/variants/pujjocento/memory.c
index bb80ee15ec..2a56efbbf5 100644
--- a/src/mainboard/google/brya/variants/pujjocento/memory.c
+++ b/src/mainboard/google/brya/variants/pujjocento/memory.c
@@ -3,6 +3,7 @@
 #include <baseboard/variants.h>
 #include <gpio.h>
 #include <soc/romstage.h>
+#include <soc/meminit.h>
 
 static const struct mb_cfg variant_memcfg = {
 	.type = MEM_TYPE_LP5X,
@@ -109,3 +110,16 @@ void variant_get_spd_info(struct mem_spd *spd_info)
 	spd_info->topo = MEM_TOPO_MEMORY_DOWN;
 	spd_info->cbfs_index = variant_memory_sku();
 }
+
+uint8_t mb_get_channel_disable_mask(void)
+{
+	/*
+	 * GPP_E13 High -> One RAM Chip
+	 * GPP_E13 Low  -> Two RAM Chip
+	 */
+	if (gpio_get(GPP_E13)) {
+		/* Disable all other channels except first two on each controller */
+		return (BIT(2) | BIT(3));
+	}
+	return 0;
+}

From 096ce4b24453331a1f0719a149e2cb2ac0bd99f2 Mon Sep 17 00:00:00 2001
From: Hope Wang <hope.wang@mediatek.corp-partner.google.com>
Date: Wed, 30 Apr 2025 10:53:28 +0800
Subject: [PATCH 1190/3886] soc/mediatek/mt8196: Move dvfs_init() declaration
 to dvfs_common.h

To promote code reuse and maintainability, move dvfs_init() declaration
to dvfs_common.h.

BUG=b:410763782
BRANCH=none
TEST=Build pass.

Signed-off-by: Hope Wang <hope.wang@mediatek.corp-partner.google.com>
Change-Id: If9778a13a4664bdaf4cad65c8daa78c10748466d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87915
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/soc/mediatek/common/include/soc/dvfs_common.h | 8 ++++++++
 src/soc/mediatek/mt8196/include/soc/dvfs.h        | 4 +---
 2 files changed, 9 insertions(+), 3 deletions(-)
 create mode 100644 src/soc/mediatek/common/include/soc/dvfs_common.h

diff --git a/src/soc/mediatek/common/include/soc/dvfs_common.h b/src/soc/mediatek/common/include/soc/dvfs_common.h
new file mode 100644
index 0000000000..71068f4c41
--- /dev/null
+++ b/src/soc/mediatek/common/include/soc/dvfs_common.h
@@ -0,0 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0-only OR MIT */
+
+#ifndef __SOC_MEDIATEK_DVFS_COMMON_H__
+#define __SOC_MEDIATEK_DVFS_COMMON_H__
+
+void dvfs_init(void);
+
+#endif
diff --git a/src/soc/mediatek/mt8196/include/soc/dvfs.h b/src/soc/mediatek/mt8196/include/soc/dvfs.h
index 76634bf00b..6bd6db5ac5 100644
--- a/src/soc/mediatek/mt8196/include/soc/dvfs.h
+++ b/src/soc/mediatek/mt8196/include/soc/dvfs.h
@@ -4,11 +4,9 @@
 #define __SOC_MEDIATEK_MT8196_DVFS_H__
 
 #include <soc/addressmap.h>
+#include <soc/dvfs_common.h>
 
-#define CACHE_LINE	64
 #define CSRAM_OFFSET	0x0001BC00
 #define CSRAM_BASE	(SRAM_BASE + CSRAM_OFFSET)
 
-void dvfs_init(void);
-
 #endif

From 8ede4bc67b8222b844c3da5c5ed67b8f93c5a157 Mon Sep 17 00:00:00 2001
From: Hope Wang <hope.wang@mediatek.corp-partner.google.com>
Date: Tue, 29 Apr 2025 21:07:24 +0800
Subject: [PATCH 1191/3886] soc/mediatek/mt8189: Add DVFS driver

Add the initialization code for CPU Dynamic Voltage and Frequency
Scaling (DVFS) for MCUPM.

BUG=b:410763782
BRANCH=none
TEST=Check the CPU frequencies are changing and not fixed values by
using the following commands in kernel:
1) set policy*/scaling_governor as "ondemand"
"echo ondemand > /sys/devices/system/cpu/cpufreq/policy0/scaling_governor"
"echo ondemand > /sys/devices/system/cpu/cpufreq/policy6/scaling_governor"
2) Check the CPU frequencies by repeating the command
"grep . /sys/devices/system/cpu/cpufreq/policy*/scaling_cur_freq"
The result is like
/sys/devices/system/cpu/cpufreq/policy0/scaling_cur_freq:650000
/sys/devices/system/cpu/cpufreq/policy6/scaling_cur_freq:2350000

Signed-off-by: Hope Wang <hope.wang@mediatek.corp-partner.google.com>
Change-Id: I001d7a02d86892478b456f1c5ab3a6433434a19b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87916
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
---
 src/soc/mediatek/common/include/soc/symbols.h |  1 +
 src/soc/mediatek/mt8189/Makefile.mk           |  1 +
 src/soc/mediatek/mt8189/dvfs.c                | 20 +++++++++++++++++++
 src/soc/mediatek/mt8189/include/soc/dvfs.h    |  8 ++++++++
 4 files changed, 30 insertions(+)
 create mode 100644 src/soc/mediatek/mt8189/dvfs.c
 create mode 100644 src/soc/mediatek/mt8189/include/soc/dvfs.h

diff --git a/src/soc/mediatek/common/include/soc/symbols.h b/src/soc/mediatek/common/include/soc/symbols.h
index 33914678b3..ae0c7932a4 100644
--- a/src/soc/mediatek/common/include/soc/symbols.h
+++ b/src/soc/mediatek/common/include/soc/symbols.h
@@ -9,6 +9,7 @@ DECLARE_REGION(dram_dma)
 DECLARE_REGION(resv_mem_optee)
 DECLARE_REGION(resv_mem_gpu)
 DECLARE_REGION(resv_mem_gpueb)
+DECLARE_REGION(dvfs2_reserved)
 DECLARE_OPTIONAL_REGION(mcufw_reserved)
 
 #endif /* _SOC_MEDIATEK_COMMON_SYMBOLS_H_ */
diff --git a/src/soc/mediatek/mt8189/Makefile.mk b/src/soc/mediatek/mt8189/Makefile.mk
index 2890564792..e00e42cd20 100644
--- a/src/soc/mediatek/mt8189/Makefile.mk
+++ b/src/soc/mediatek/mt8189/Makefile.mk
@@ -20,6 +20,7 @@ romstage-y += ../common/cbmem.c
 romstage-y += ../common/cpu_id.c ../common/cpu_segment_id.c
 romstage-y += ../common/dram_init.c
 romstage-y += ../common/dramc_param.c
+romstage-y += dvfs.c
 romstage-y += ../common/emi.c
 romstage-y += ../common/memory.c ../common/memory_test.c
 romstage-y += ../common/mmu_operations.c ../common/mmu_cmops.c
diff --git a/src/soc/mediatek/mt8189/dvfs.c b/src/soc/mediatek/mt8189/dvfs.c
new file mode 100644
index 0000000000..f34586ea46
--- /dev/null
+++ b/src/soc/mediatek/mt8189/dvfs.c
@@ -0,0 +1,20 @@
+/* SPDX-License-Identifier: GPL-2.0-only OR MIT */
+
+#include <arch/cache.h>
+#include <device/mmio.h>
+#include <soc/cpu_id.h>
+#include <soc/dvfs.h>
+#include <soc/symbols.h>
+
+void dvfs_init(void)
+{
+	u32 id, val;
+
+	id = get_cpu_segment_id();
+	val = (id << 8) | BIT(0);
+
+	write32(_dvfs2_reserved + 0x8, 0x55AA55AA);
+	write32(_dvfs2_reserved + 0xC, val);
+
+	dcache_clean_invalidate_by_mva(_dvfs2_reserved, 0x10);
+}
diff --git a/src/soc/mediatek/mt8189/include/soc/dvfs.h b/src/soc/mediatek/mt8189/include/soc/dvfs.h
new file mode 100644
index 0000000000..aa44b1a2ac
--- /dev/null
+++ b/src/soc/mediatek/mt8189/include/soc/dvfs.h
@@ -0,0 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0-only OR MIT */
+
+#ifndef __SOC_MEDIATEK_MT8189_INCLUDE_SOC_DVFS_H__
+#define __SOC_MEDIATEK_MT8189_INCLUDE_SOC_DVFS_H__
+
+#include <soc/dvfs_common.h>
+
+#endif /* __SOC_MEDIATEK_MT8189_INCLUDE_SOC_DVFS_H__ */

From 94686e581af08a7cfc172169ad23bfc7d1150495 Mon Sep 17 00:00:00 2001
From: Hope Wang <hope.wang@mediatek.corp-partner.google.com>
Date: Tue, 29 Apr 2025 21:08:25 +0800
Subject: [PATCH 1192/3886] mb/google/skywalker: Add DVFS support in romstage

Add the initialization in romstage.

BUG=b:410763782
BRANCH=none
TEST=Check the CPU frequencies are changing and not fixed values by
using the following commands in kernel:
1) set policy*/scaling_governor as "ondemand"
"echo ondemand > /sys/devices/system/cpu/cpufreq/policy0/scaling_governor"
"echo ondemand > /sys/devices/system/cpu/cpufreq/policy6/scaling_governor"
2) Check the CPU frequencies by repeating the command
"grep . /sys/devices/system/cpu/cpufreq/policy*/scaling_cur_freq"
The result is like
/sys/devices/system/cpu/cpufreq/policy0/scaling_cur_freq:650000
/sys/devices/system/cpu/cpufreq/policy6/scaling_cur_freq:2350000

Signed-off-by: Hope Wang <hope.wang@mediatek.corp-partner.google.com>
Change-Id: Ie64ebd1b78096c38c4398572cbed3e2e9ac6b8b6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87917
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
---
 src/mainboard/google/skywalker/romstage.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/src/mainboard/google/skywalker/romstage.c b/src/mainboard/google/skywalker/romstage.c
index 3b6de958d1..f8643061bf 100644
--- a/src/mainboard/google/skywalker/romstage.c
+++ b/src/mainboard/google/skywalker/romstage.c
@@ -2,6 +2,7 @@
 
 #include <arch/stages.h>
 #include <delay.h>
+#include <soc/dvfs.h>
 #include <soc/emi.h>
 #include <soc/mt6315.h>
 #include <soc/mt6359p.h>
@@ -26,5 +27,6 @@ void platform_romstage_main(void)
 	mt6359p_init();
 	raise_little_cpu_freq();
 	rtc_boot();
+	dvfs_init();
 	mtk_dram_init();
 }

From a283246ef779b6d47e10d4946f924fcf7de601d6 Mon Sep 17 00:00:00 2001
From: Yidi Lin <yidilin@google.com>
Date: Mon, 2 Jun 2025 13:21:45 +0800
Subject: [PATCH 1193/3886] soc/mediatek/common: Refactor auxadc driver to
 support new platform

The method for reading AUXDAC on mt8189 differs from previous methods.
To enhance code modularity and maintain compatibility, the differing
parts are moved to auxad_v1.h  to supports legacy platforms.

BUG=b:379008996
BRANCH=none
TEST=emerge-geralt coreboot -j

Change-Id: Ib4bf0f593cab0480b7c78df7916f721f2e0833c7
Signed-off-by: Yidi Lin <yidilin@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87919
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
---
 src/soc/mediatek/common/auxadc.c                |  8 ++------
 src/soc/mediatek/common/include/soc/auxadc_v1.h | 15 +++++++++++++++
 src/soc/mediatek/mt8183/include/soc/auxadc.h    |  1 +
 src/soc/mediatek/mt8186/include/soc/auxadc.h    |  1 +
 src/soc/mediatek/mt8188/include/soc/auxadc.h    |  1 +
 src/soc/mediatek/mt8192/include/soc/auxadc.h    |  1 +
 src/soc/mediatek/mt8195/include/soc/auxadc.h    |  1 +
 7 files changed, 22 insertions(+), 6 deletions(-)
 create mode 100644 src/soc/mediatek/common/include/soc/auxadc_v1.h

diff --git a/src/soc/mediatek/common/auxadc.c b/src/soc/mediatek/common/auxadc.c
index 6dbf12bbe9..7e296e3e59 100644
--- a/src/soc/mediatek/common/auxadc.c
+++ b/src/soc/mediatek/common/auxadc.c
@@ -10,10 +10,6 @@
 
 static struct mtk_auxadc_regs *const mtk_auxadc = (void *)AUXADC_BASE;
 
-#define ADC_GE_A_SHIFT		10
-#define ADC_GE_A_MASK		(0x3ff << ADC_GE_A_SHIFT)
-#define ADC_OE_A_SHIFT		0
-#define ADC_OE_A_MASK		(0x3ff << ADC_OE_A_SHIFT)
 #define ADC_CALI_EN_A_SHIFT	20
 #define ADC_CALI_EN_A_MASK	(0x1 << ADC_CALI_EN_A_SHIFT)
 
@@ -38,7 +34,7 @@ static void mt_auxadc_update_cali(void)
 
 static uint32_t auxadc_get_rawdata(int channel)
 {
-	setbits32(&mtk_infracfg->module_sw_cg_1_clr, 1 << 10);
+	setbits32(&AUXADC_SWCG_CLR_REG, BIT(AUXADC_SWCG_EN_BIT));
 	assert(wait_ms(300, !(read32(&mtk_auxadc->con2) & 0x1)));
 
 	clrbits32(&mtk_auxadc->con1, 1 << channel);
@@ -50,7 +46,7 @@ static uint32_t auxadc_get_rawdata(int channel)
 
 	uint32_t value = read32(&mtk_auxadc->data[channel]) & 0x0FFF;
 
-	setbits32(&mtk_infracfg->module_sw_cg_1_set, 1 << 10);
+	setbits32(&AUXADC_SWCG_SET_REG, BIT(AUXADC_SWCG_EN_BIT));
 
 	return value;
 }
diff --git a/src/soc/mediatek/common/include/soc/auxadc_v1.h b/src/soc/mediatek/common/include/soc/auxadc_v1.h
new file mode 100644
index 0000000000..f6cbc7b693
--- /dev/null
+++ b/src/soc/mediatek/common/include/soc/auxadc_v1.h
@@ -0,0 +1,15 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef __SOC_MEDIATEK_COMMON_INCLUDE_SOC_AUXADC_V1_H__
+#define __SOC_MEDIATEK_COMMON_INCLUDE_SOC_AUXADC_V1_H__
+
+#define ADC_GE_A_SHIFT		10
+#define ADC_GE_A_MASK		(0x3ff << ADC_GE_A_SHIFT)
+#define ADC_OE_A_SHIFT		0
+#define ADC_OE_A_MASK		(0x3ff << ADC_OE_A_SHIFT)
+
+#define AUXADC_SWCG_CLR_REG	(mtk_infracfg->module_sw_cg_1_clr)
+#define AUXADC_SWCG_SET_REG	(mtk_infracfg->module_sw_cg_1_set)
+#define AUXADC_SWCG_EN_BIT	10
+
+#endif
diff --git a/src/soc/mediatek/mt8183/include/soc/auxadc.h b/src/soc/mediatek/mt8183/include/soc/auxadc.h
index 326261af32..1f2a0e5f32 100644
--- a/src/soc/mediatek/mt8183/include/soc/auxadc.h
+++ b/src/soc/mediatek/mt8183/include/soc/auxadc.h
@@ -4,6 +4,7 @@
 #define _MTK_ADC_H
 
 #include <soc/auxadc_common.h>
+#include <soc/auxadc_v1.h>
 #include <soc/infracfg.h>
 #include <stdint.h>
 
diff --git a/src/soc/mediatek/mt8186/include/soc/auxadc.h b/src/soc/mediatek/mt8186/include/soc/auxadc.h
index d5f41a6b7c..faa0f035c2 100644
--- a/src/soc/mediatek/mt8186/include/soc/auxadc.h
+++ b/src/soc/mediatek/mt8186/include/soc/auxadc.h
@@ -9,6 +9,7 @@
 #define SOC_MEDIATEK_MT8186_AUXADC_H
 
 #include <soc/auxadc_common.h>
+#include <soc/auxadc_v1.h>
 #include <soc/infracfg.h>
 #include <stdint.h>
 
diff --git a/src/soc/mediatek/mt8188/include/soc/auxadc.h b/src/soc/mediatek/mt8188/include/soc/auxadc.h
index d332873a21..8c173630d8 100644
--- a/src/soc/mediatek/mt8188/include/soc/auxadc.h
+++ b/src/soc/mediatek/mt8188/include/soc/auxadc.h
@@ -9,6 +9,7 @@
 #define SOC_MEDIATEK_MT8188_AUXADC_H
 
 #include <soc/auxadc_common.h>
+#include <soc/auxadc_v1.h>
 #include <soc/infracfg.h>
 #include <stdint.h>
 
diff --git a/src/soc/mediatek/mt8192/include/soc/auxadc.h b/src/soc/mediatek/mt8192/include/soc/auxadc.h
index 94702bd141..d4ec7d957e 100644
--- a/src/soc/mediatek/mt8192/include/soc/auxadc.h
+++ b/src/soc/mediatek/mt8192/include/soc/auxadc.h
@@ -4,6 +4,7 @@
 #define _MTK_ADC_H
 
 #include <soc/auxadc_common.h>
+#include <soc/auxadc_v1.h>
 #include <soc/infracfg.h>
 #include <stdint.h>
 
diff --git a/src/soc/mediatek/mt8195/include/soc/auxadc.h b/src/soc/mediatek/mt8195/include/soc/auxadc.h
index 326b3722fd..c0b2f1e734 100644
--- a/src/soc/mediatek/mt8195/include/soc/auxadc.h
+++ b/src/soc/mediatek/mt8195/include/soc/auxadc.h
@@ -4,6 +4,7 @@
 #define SOC_MEDIATEK_MT8195_AUXADC_H
 
 #include <soc/auxadc_common.h>
+#include <soc/auxadc_v1.h>
 #include <soc/infracfg.h>
 #include <stdint.h>
 

From de251dd677ea54a9e578b3fd9074170f1c174869 Mon Sep 17 00:00:00 2001
From: Vince Liu <vince-wl.liu@mediatek.corp-partner.google.com>
Date: Mon, 12 May 2025 11:18:31 +0800
Subject: [PATCH 1194/3886] soc/mediatek/mt8189: Add support AUXADC

Add Auxiliary Analog-to-Digital Converter (AUXADC) driver for mt8189.

BUG=b:379008996
BRANCH=none
TEST=Check log on Skywalker SKU1
[DEBUG]  ADC[2]: Raw value=73782 ID=0

Change-Id: I7288003c1c90a93697b7c838cf4db0fd1de4d73a
Signed-off-by: Vince Liu <vince-wl.liu@mediatek.corp-partner.google.com>
Signed-off-by: Yidi Lin <yidilin@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87920
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/soc/mediatek/common/include/soc/auxadc_v2.h  | 15 +++++++++++++++
 src/soc/mediatek/mt8189/Makefile.mk              |  1 +
 src/soc/mediatek/mt8189/include/soc/addressmap.h |  1 +
 src/soc/mediatek/mt8189/include/soc/auxadc.h     | 16 ++++++++++++++++
 src/soc/mediatek/mt8189/include/soc/efuse.h      |  9 ++++++---
 src/soc/mediatek/mt8189/include/soc/pll.h        |  2 ++
 6 files changed, 41 insertions(+), 3 deletions(-)
 create mode 100644 src/soc/mediatek/common/include/soc/auxadc_v2.h
 create mode 100644 src/soc/mediatek/mt8189/include/soc/auxadc.h

diff --git a/src/soc/mediatek/common/include/soc/auxadc_v2.h b/src/soc/mediatek/common/include/soc/auxadc_v2.h
new file mode 100644
index 0000000000..cac784f027
--- /dev/null
+++ b/src/soc/mediatek/common/include/soc/auxadc_v2.h
@@ -0,0 +1,15 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef __SOC_MEDIATEK_COMMON_INCLUDE_SOC_AUXADC_V2_H__
+#define __SOC_MEDIATEK_COMMON_INCLUDE_SOC_AUXADC_V2_H__
+
+#define ADC_GE_A_SHIFT		0
+#define ADC_GE_A_MASK		(0x3ff << ADC_GE_A_SHIFT)
+#define ADC_OE_A_SHIFT		10
+#define ADC_OE_A_MASK		(0x3ff << ADC_OE_A_SHIFT)
+
+#define AUXADC_SWCG_CLR_REG	(mtk_pericfg_ao->pericfg_ao_peri_cg_2_clr)
+#define AUXADC_SWCG_SET_REG	(mtk_pericfg_ao->pericfg_ao_peri_cg_2_set)
+#define AUXADC_SWCG_EN_BIT	27
+
+#endif
diff --git a/src/soc/mediatek/mt8189/Makefile.mk b/src/soc/mediatek/mt8189/Makefile.mk
index e00e42cd20..2051622bb5 100644
--- a/src/soc/mediatek/mt8189/Makefile.mk
+++ b/src/soc/mediatek/mt8189/Makefile.mk
@@ -32,6 +32,7 @@ romstage-y += ../common/pmif_spi.c pmif_spi.c
 romstage-y += ../common/pmif_spmi.c pmif_spmi.c
 romstage-y += ../common/rtc.c ../common/rtc_osc_init.c ../common/rtc_mt6359p.c
 
+ramstage-y += ../common/auxadc.c
 ramstage-$(CONFIG_ARM64_USE_ARM_TRUSTED_FIRMWARE) += ../common/bl31.c
 ramstage-y += ../common/dpm.c ../common/dpm_v2.c
 ramstage-y += ../common/dramc_info.c
diff --git a/src/soc/mediatek/mt8189/include/soc/addressmap.h b/src/soc/mediatek/mt8189/include/soc/addressmap.h
index 5a127f65aa..1f91d03ff9 100644
--- a/src/soc/mediatek/mt8189/include/soc/addressmap.h
+++ b/src/soc/mediatek/mt8189/include/soc/addressmap.h
@@ -54,6 +54,7 @@ enum {
 	SPI4_BASE			= IO_PHYS + 0x01014800,
 	SPI5_BASE			= IO_PHYS + 0x01015800,
 	SFLASH_REG_BASE			= IO_PHYS + 0x01018000,
+	AUXADC_BASE			= IO_PHYS + 0x01019000,
 	PERI_AO_BCRM_BASE		= IO_PHYS + 0x01035000,
 	PERICFG_AO_BASE			= IO_PHYS + 0x01036000,
 	DEVAPC_PERI_PAR_AO_BASE		= IO_PHYS + 0x0103C000,
diff --git a/src/soc/mediatek/mt8189/include/soc/auxadc.h b/src/soc/mediatek/mt8189/include/soc/auxadc.h
new file mode 100644
index 0000000000..85d29574c7
--- /dev/null
+++ b/src/soc/mediatek/mt8189/include/soc/auxadc.h
@@ -0,0 +1,16 @@
+/* SPDX-License-Identifier: GPL-2.0-only OR MIT */
+
+/*
+ * This file is created based on MT8189 Functional Specification
+ * Chapter number: 9.9
+ */
+
+#ifndef SOC_MEDIATEK_MT8189_AUXADC_H
+#define SOC_MEDIATEK_MT8189_AUXADC_H
+
+#include <soc/auxadc_common.h>
+#include <soc/auxadc_v2.h>
+#include <soc/pll.h>
+#include <stdint.h>
+
+#endif
diff --git a/src/soc/mediatek/mt8189/include/soc/efuse.h b/src/soc/mediatek/mt8189/include/soc/efuse.h
index 2d872d46b5..47cc54af4f 100644
--- a/src/soc/mediatek/mt8189/include/soc/efuse.h
+++ b/src/soc/mediatek/mt8189/include/soc/efuse.h
@@ -7,13 +7,16 @@
 #include <stdint.h>
 
 struct efuse_regs {
-	u32 reserved1[488];
+	u32 reserved1[96];
+	u32 adc_cali_reg;
+	u32 reserved2[391];
 	u32 cpu_id_reg;
-	u32 reserved2[15];
+	u32 reserved3[15];
 	u32 cpu_seg_id_reg;
-	u32 reserved3[14908];
+	u32 reserved4[14908];
 	u32 ecc_status_reg;
 };
+check_member(efuse_regs, adc_cali_reg, 0x180);
 check_member(efuse_regs, cpu_id_reg, 0x7A0);
 check_member(efuse_regs, cpu_seg_id_reg, 0x7E0);
 check_member(efuse_regs, ecc_status_reg, 0xF0D4);
diff --git a/src/soc/mediatek/mt8189/include/soc/pll.h b/src/soc/mediatek/mt8189/include/soc/pll.h
index 192bff5596..a3b474cab0 100644
--- a/src/soc/mediatek/mt8189/include/soc/pll.h
+++ b/src/soc/mediatek/mt8189/include/soc/pll.h
@@ -267,6 +267,8 @@ struct mtk_pericfg_ao_regs {
 };
 check_member(mtk_pericfg_ao_regs, pericfg_ao_peri_cg_0, 0x0010);
 check_member(mtk_pericfg_ao_regs, pericfg_ao_peri_cg_0_set, 0x0024);
+check_member(mtk_pericfg_ao_regs, pericfg_ao_peri_cg_2_set, 0x0034);
+check_member(mtk_pericfg_ao_regs, pericfg_ao_peri_cg_2_clr, 0x0038);
 
 struct mtk_afe_regs {
 	u32 audio_audio_top[5];

From 3e6b47980af120f9b94fad2fb7111a199f9302c9 Mon Sep 17 00:00:00 2001
From: Vince Liu <vince-wl.liu@mediatek.corp-partner.google.com>
Date: Fri, 9 May 2025 22:23:32 +0800
Subject: [PATCH 1195/3886] mb/google/skywalker: Add support for getting
 storage id

Add storage_id() to read the storage id from AUXADC.

BUG=b:379008996
BRANCH=none
TEST=check log on Skywalker SKU1
[DEBUG]  ADC[2]: Raw value=73782 ID=0

Signed-off-by: Vince Liu <vince-wl.liu@mediatek.corp-partner.google.com>
Change-Id: I83cb52df1f25c5106fbe213e8a0185ae764fd7dc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87921
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
---
 src/mainboard/google/skywalker/boardid.c   | 58 ++++++++++++++++++++++
 src/mainboard/google/skywalker/mainboard.c | 19 +++++++
 src/mainboard/google/skywalker/storage.h   |  8 +++
 3 files changed, 85 insertions(+)
 create mode 100644 src/mainboard/google/skywalker/storage.h

diff --git a/src/mainboard/google/skywalker/boardid.c b/src/mainboard/google/skywalker/boardid.c
index cfac4d5d4d..437f64e302 100644
--- a/src/mainboard/google/skywalker/boardid.c
+++ b/src/mainboard/google/skywalker/boardid.c
@@ -1,8 +1,66 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
+#include <assert.h>
 #include <boardid.h>
 #include <console/console.h>
 #include <ec/google/chromeec/ec.h>
+#include <soc/auxadc_common.h>
+
+#include "storage.h"
+
+#define ADC_LEVELS 8
+
+enum {
+	/* STORAGE IDs */
+	STORAGE_ID_CHANNEL = 2,
+};
+
+static const unsigned int storage_voltages[ADC_LEVELS] = {
+	/* ID : Voltage (unit: uV) */
+	[0] =   74300,
+	[1] =  211400,
+	[2] =  365100,
+	[3] =  524300,
+	[4] =  706300,
+	[5] =  899100,
+	[6] = 1108900,
+	[7] = 1342600,
+};
+
+static const unsigned int *adc_voltages[] = {
+	[STORAGE_ID_CHANNEL] = storage_voltages,
+};
+
+static uint32_t get_adc_index(unsigned int channel)
+{
+	unsigned int value = auxadc_get_voltage_uv(channel);
+	const unsigned int *voltages;
+
+	assert(channel < ARRAY_SIZE(adc_voltages));
+	voltages = adc_voltages[channel];
+
+	assert(voltages);
+
+	/* Find the closest voltage */
+	uint32_t id;
+	for (id = 0; id < ADC_LEVELS - 1; id++)
+		if (value < (voltages[id] + voltages[id + 1]) / 2)
+			break;
+
+	printk(BIOS_DEBUG, "ADC[%u]: Raw value=%u ID=%u\n", channel, value, id);
+	return id;
+}
+
+uint32_t storage_id(void)
+{
+	static uint32_t cached_storage_id = BOARD_ID_INIT;
+
+	if (cached_storage_id == BOARD_ID_INIT)
+		cached_storage_id = get_adc_index(STORAGE_ID_CHANNEL);
+
+	printk(BIOS_DEBUG, "Storage ID: %#02x\n", cached_storage_id);
+	return cached_storage_id;
+}
 
 uint32_t sku_id(void)
 {
diff --git a/src/mainboard/google/skywalker/mainboard.c b/src/mainboard/google/skywalker/mainboard.c
index 652d81253f..bf430bc497 100644
--- a/src/mainboard/google/skywalker/mainboard.c
+++ b/src/mainboard/google/skywalker/mainboard.c
@@ -11,9 +11,11 @@
 #include <soc/mt6359p.h>
 #include <soc/mtcmos.h>
 #include <soc/spm_common.h>
+#include <soc/storage.h>
 #include <soc/usb.h>
 
 #include "gpio.h"
+#include "storage.h"
 
 #define AFE_SE_SECURE_CON1	(AUDIO_BASE + 0x5634)
 
@@ -65,6 +67,23 @@ static void power_on_fpmcu(void)
 	gpio_output(GPIO_FP_RST_1V8_S3_L, 1);
 }
 
+enum mtk_storage_type mainboard_get_storage_type(void)
+{
+	uint32_t index = storage_id();
+
+	switch (index) {
+	case 0:
+		return STORAGE_UFS_31;
+	case 1:
+		return STORAGE_UFS_22;
+	case 2:
+		return STORAGE_EMMC;
+	default:
+		printk(BIOS_WARNING, "unsupported storage id %u\n", index);
+	}
+	return STORAGE_UNKNOWN;
+}
+
 static void mainboard_init(struct device *dev)
 {
 	dpm_init();
diff --git a/src/mainboard/google/skywalker/storage.h b/src/mainboard/google/skywalker/storage.h
new file mode 100644
index 0000000000..dbdf2f3c54
--- /dev/null
+++ b/src/mainboard/google/skywalker/storage.h
@@ -0,0 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0-only OR MIT */
+
+#ifndef __MAINBOARD_GOOGLE_SKYWALKER_STORAGE_H__
+#define __MAINBOARD_GOOGLE_SKYWALKER_STORAGE_H__
+
+uint32_t storage_id(void);
+
+#endif

From 0a41779e2e7c3629f29015e8829e1b8d23e631be Mon Sep 17 00:00:00 2001
From: Vince Liu <vince-wl.liu@mediatek.corp-partner.google.com>
Date: Thu, 22 May 2025 17:09:01 +0800
Subject: [PATCH 1196/3886] mb/google/skywalker: Add eMMC configuration

Skywalker reference design supports multiple storage types, such as UFS
and eMMC. We only need to configure eMMC if the board storage type is
eMMC.

BUG=b:379008996
BRANCH=none
TEST=build pass

Signed-off-by: Vince Liu <vince-wl.liu@mediatek.corp-partner.google.com>
Change-Id: I7c3a2e3f7acf75d57d72cda3c9d2e83b77c72f0e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87922
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
---
 src/mainboard/google/skywalker/mainboard.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/src/mainboard/google/skywalker/mainboard.c b/src/mainboard/google/skywalker/mainboard.c
index bf430bc497..61aa2794e9 100644
--- a/src/mainboard/google/skywalker/mainboard.c
+++ b/src/mainboard/google/skywalker/mainboard.c
@@ -86,6 +86,9 @@ enum mtk_storage_type mainboard_get_storage_type(void)
 
 static void mainboard_init(struct device *dev)
 {
+	if (mainboard_get_storage_type() == STORAGE_EMMC)
+		mtk_msdc_configure_emmc(true);
+
 	dpm_init();
 	setup_usb_host();
 	spm_init();

From be6787a55e34c3aa9cd73652f24e332cc7510541 Mon Sep 17 00:00:00 2001
From: xuxinxiong <xuxinxiong@huaqin.corp-partner.google.com>
Date: Mon, 19 May 2025 16:57:53 +0800
Subject: [PATCH 1197/3886] mb/google/skywalker: Add storage types to fw_config

Use the storage type from fw_config to determine which types of storage
need to be set up in the payload.

BUG=b:379008996
BRANCH=none
TEST=input "cbi set 6 0x40000000 4" in ec console, and see the
following log:

fw_config match found: STORAGE=STORAGE_UFS2X
storage_setup: eMMC: no, UFS: yes

Signed-off-by: Vince Liu <vince-wl.liu@mediatek.corp-partner.google.com>
Change-Id: Ieada3c56b0f69cc1ea3dab4e64641bfc2ba2a0fe
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87923
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
---
 src/mainboard/google/skywalker/devicetree.cb | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/src/mainboard/google/skywalker/devicetree.cb b/src/mainboard/google/skywalker/devicetree.cb
index 92f9c5d9e3..16f2a688ba 100644
--- a/src/mainboard/google/skywalker/devicetree.cb
+++ b/src/mainboard/google/skywalker/devicetree.cb
@@ -10,4 +10,10 @@ fw_config
 		option AMP_RT1019 1
 		option AMP_ALC5645 3
 	end
+
+	field STORAGE 30 31
+		option STORAGE_UFS3X 0
+		option STORAGE_UFS2X 1
+		option STORAGE_EMMC 2
+	end
 end

From b3776e23a7748a8e350f83af4877544a1cf20e4f Mon Sep 17 00:00:00 2001
From: Subrata Banik <subratabanik@google.com>
Date: Fri, 30 May 2025 21:03:50 +0530
Subject: [PATCH 1198/3886] ec/google/chromeec: Add SPI/I2C EC communication
 files to bootblock

This commit updates `ec/google/chromeec/Makefile.mk` to properly
include source files for SPI and I2C Embedded Controller (EC)
communication in the bootblock.

Previously, essential APIs (e.g., `google_chromeec_command` and
`crosec_command_proto`) were missing during EC code compilation
in the bootblock, leading to linker errors.

This patch resolves these compilation issues by ensuring:
* `ec_spi.c` is included when `CONFIG_EC_GOOGLE_CHROMEEC_SPI` is
  enabled.
* `ec_i2c.c` is included when `CONFIG_EC_GOOGLE_CHROMEEC_I2C` is
  enabled.
* `crosec_proto.c` is included if either
  `CONFIG_EC_GOOGLE_CHROMEEC_SPI` or `CONFIG_EC_GOOGLE_CHROMEEC_I2C`
  is enabled.

This ensures all required EC communication components are part of the
bootblock, allowing systems like `google/quenbi` that use the SPI EC
interface to build successfully.

Change-Id: I1d05f582a1685503118797e1788c9bc2ac191168
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87904
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/ec/google/chromeec/Makefile.mk | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/src/ec/google/chromeec/Makefile.mk b/src/ec/google/chromeec/Makefile.mk
index 54d404003e..10b6203e5d 100644
--- a/src/ec/google/chromeec/Makefile.mk
+++ b/src/ec/google/chromeec/Makefile.mk
@@ -21,7 +21,12 @@ ramstage-$(CONFIG_EC_GOOGLE_CHROMEEC_SMBIOS) += ec_smbios.c
 endif
 
 bootblock-y += ec.c
+bootblock-$(CONFIG_EC_GOOGLE_CHROMEEC_I2C) += ec_i2c.c
 bootblock-$(CONFIG_EC_GOOGLE_CHROMEEC_LPC) += ec_lpc.c
+bootblock-$(CONFIG_EC_GOOGLE_CHROMEEC_SPI) += ec_spi.c
+ifeq ($(CONFIG_EC_GOOGLE_CHROMEEC_SPI)$(CONFIG_EC_GOOGLE_CHROMEEC_I2C),y)
+bootblock-y += crosec_proto.c
+endif
 ramstage-y += ec.c crosec_proto.c vstore.c usbc_mux.c
 ramstage-$(CONFIG_EC_GOOGLE_CHROMEEC_I2C) += ec_i2c.c
 ramstage-$(CONFIG_EC_GOOGLE_CHROMEEC_LPC) += ec_lpc.c

From bba9d271458103b65af63e6d4bd640f8cfb2dbe0 Mon Sep 17 00:00:00 2001
From: Avi Uday <aviuday@google.com>
Date: Mon, 2 Jun 2025 12:31:00 +0530
Subject: [PATCH 1199/3886] mb/google/ocelot: Remove power limit override
 functionality

This patch removes the power limit override code from google/ocelot until the power limits for WCL are known. It is left as a TODO till then.

Change-Id: I15bd1a1c8397957df96a97b4f9f3de0fd5f5c7f6
Signed-off-by: Avi Uday <aviuday@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87911
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Pranava Y N <pranavayn@google.com>
---
 .../variants/baseboard/ocelot/ramstage.c      | 51 +------------------
 1 file changed, 2 insertions(+), 49 deletions(-)

diff --git a/src/mainboard/google/ocelot/variants/baseboard/ocelot/ramstage.c b/src/mainboard/google/ocelot/variants/baseboard/ocelot/ramstage.c
index 69d0d67cd0..43a82d12c3 100644
--- a/src/mainboard/google/ocelot/variants/baseboard/ocelot/ramstage.c
+++ b/src/mainboard/google/ocelot/variants/baseboard/ocelot/ramstage.c
@@ -3,53 +3,6 @@
 #include <baseboard/variants.h>
 #include <ec/google/chromeec/ec.h>
 
-/*
- * SKU_ID, TDP (Watts), pl1_min (milliWatts), pl1_max (milliWatts),
- * pl2_min (milliWatts), pl2_max (milliWatts), pl4 (milliWatts)
- */
-const struct cpu_tdp_power_limits power_optimized_limits[] = {
-	{
-		.mch_id = PCI_DID_INTEL_PTL_H_ID_1,
-		.cpu_tdp = TDP_25W,
-		.power_limits_index = PTL_H_1_CORE,
-		.pl1_min_power = 10000,
-		.pl1_max_power = 25000,
-		.pl2_min_power = 50000,
-		.pl2_max_power = 50000,
-		.pl4_power = 65000
-	},
-	{
-		.mch_id = PCI_DID_INTEL_PTL_H_ID_2,
-		.cpu_tdp = TDP_25W,
-		.power_limits_index = PTL_H_1_CORE,
-		.pl1_min_power = 10000,
-		.pl1_max_power = 25000,
-		.pl2_min_power = 50000,
-		.pl2_max_power = 50000,
-		.pl4_power = 65000
-	},
-	{
-		.mch_id = PCI_DID_INTEL_PTL_H_ID_3,
-		.cpu_tdp = TDP_25W,
-		.power_limits_index = PTL_H_2_CORE,
-		.pl1_min_power = 10000,
-		.pl1_max_power = 25000,
-		.pl2_min_power = 50000,
-		.pl2_max_power = 50000,
-		.pl4_power = 65000
-	},
-	{
-		.mch_id = PCI_DID_INTEL_PTL_H_ID_4,
-		.cpu_tdp = TDP_25W,
-		.power_limits_index = PTL_H_2_CORE,
-		.pl1_min_power = 10000,
-		.pl1_max_power = 25000,
-		.pl2_min_power = 50000,
-		.pl2_max_power = 50000,
-		.pl4_power = 65000
-	},
-};
-
 /*
  * Placeholder to check if variant has support for barrel jack for powering
  * on the device.
@@ -68,7 +21,7 @@ void baseboard_devtree_update(void)
 	if (variant_is_barrel_charger_present())
 		return;
 
+	/* TODO: Add power limit override code for Wildcat Lake */
 	if (!google_chromeec_is_battery_present())
-		variant_update_cpu_power_limits(power_optimized_limits,
-						ARRAY_SIZE(power_optimized_limits));
+		printk(BIOS_DEBUG, "TODO: Add support for power optimized boot configuration limits\n");
 }

From 0af68855c09d454a41e7769e1a31c651c9ff6278 Mon Sep 17 00:00:00 2001
From: Jianeng Ceng <cengjianeng@huaqin.corp-partner.google.com>
Date: Fri, 30 May 2025 12:59:26 +0800
Subject: [PATCH 1200/3886] mb/google/nissa/var/pujjoniru: Config AUX gpio to
 correct TCSS port

In TWL, Type-C0 corresponds to TCSS port1, and Type-C1 corresponds
to TCSS port0. In order for the DP functions of the two Type-C ports
to operate normally, the corresponding relationship needs to be
configured correctly.

BUG=b:418106736
TEST=DP function of Type-C0/C1 workable

Change-Id: I4aa406e72d1e5f0434866b105f20df6362f3d304
Signed-off-by: Jianeng Ceng <cengjianeng@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87899
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: hualin wei <weihualin@huaqin.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
---
 src/mainboard/google/brya/variants/pujjoniru/overridetree.cb | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/mainboard/google/brya/variants/pujjoniru/overridetree.cb b/src/mainboard/google/brya/variants/pujjoniru/overridetree.cb
index 60d3117d05..cc3d1dcefc 100644
--- a/src/mainboard/google/brya/variants/pujjoniru/overridetree.cb
+++ b/src/mainboard/google/brya/variants/pujjoniru/overridetree.cb
@@ -27,12 +27,12 @@ chip soc/intel/alderlake
 	# motherboard to USBC connector
 	register "tcss_aux_ori" = "5"
 
-	register "typec_aux_bias_pads[0]" = "{
+	register "typec_aux_bias_pads[1]" = "{
 		.pad_auxp_dc = GPP_E22,
 		.pad_auxn_dc = GPP_E23
 	}"
 
-	register "typec_aux_bias_pads[1]" = "{
+	register "typec_aux_bias_pads[0]" = "{
 		.pad_auxp_dc = GPP_A21,
 		.pad_auxn_dc = GPP_A22
 	}"

From 0251e98e9e1dd4aae898725b060ee06693a20930 Mon Sep 17 00:00:00 2001
From: Benjamin Doron <benjamin.doron@9elements.com>
Date: Tue, 27 May 2025 12:30:07 -0400
Subject: [PATCH 1201/3886] util/amdfwtool: Do not attempt to continue
 processing `--help`

If the `--help` argument is passed, print the usage and immediately
return. This avoids printing errors about 'invalid config,' which
users don't specify when getting the usage information, and potentially
printing the usage a second time before exiting.

Change-Id: I18bf154ff5177fa0e0aa6a41f0d71980fed7ce55
Signed-off-by: Benjamin Doron <benjamin.doron@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87869
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
---
 util/amdfwtool/opts.c | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/util/amdfwtool/opts.c b/util/amdfwtool/opts.c
index 15bc7ca3a5..158eb656aa 100644
--- a/util/amdfwtool/opts.c
+++ b/util/amdfwtool/opts.c
@@ -601,8 +601,7 @@ int amdfwtool_getopt(int argc, char *argv[], amd_cb_config *cb_config, context *
 			break;
 		case AMDFW_OPT_HELP:
 			usage();
-			retval = 1;
-			break;
+			return 1;
 		case AMDFW_OPT_BODY_LOCATION:
 			cb_config->body_location = (uint32_t)strtoul(optarg, &tmp, 16);
 			if (*tmp != '\0') {

From c615de7248f9e22ff565517125f6e5d88706bd89 Mon Sep 17 00:00:00 2001
From: Patrick Rudolph <patrick.rudolph@9elements.com>
Date: Thu, 22 May 2025 15:36:43 +0200
Subject: [PATCH 1202/3886] soc/amd/glinda: Don't let OS put debug UART into D3

When using CONFIG_CONSOLE_SERIAL prevent the OS from putting the
debug uart into D3 state. In the D3 state it's not operating any
more, and the user cannot read debug messages on early kernel boot
or on shutdown any more.

For release builds CONFIG_CONSOLE_SERIAL should not be set and the
device can be put into powersave mode.

Change-Id: Id6b6a4d0a053a5e14e54cf623974376992f0abd8
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87803
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/soc/amd/glinda/acpi/mmio.asl | 12 ++++++++----
 1 file changed, 8 insertions(+), 4 deletions(-)

diff --git a/src/soc/amd/glinda/acpi/mmio.asl b/src/soc/amd/glinda/acpi/mmio.asl
index 3d7b882efd..7323427b08 100644
--- a/src/soc/amd/glinda/acpi/mmio.asl
+++ b/src/soc/amd/glinda/acpi/mmio.asl
@@ -94,8 +94,9 @@ Device (FUR0)
 	{
 		Return (STAT)
 	}
-
+#if (!CONFIG(CONSOLE_SERIAL) || !CONFIG(AMD_SOC_CONSOLE_UART) || CONFIG_UART_FOR_CONSOLE != 0)
 	AOAC_DEVICE(FCH_AOAC_DEV_UART0, 0)
+#endif
 }
 
 Device (FUR1) {
@@ -131,8 +132,9 @@ Device (FUR1) {
 	{
 		Return (STAT)
 	}
-
+#if (!CONFIG(CONSOLE_SERIAL) || !CONFIG(AMD_SOC_CONSOLE_UART) || CONFIG_UART_FOR_CONSOLE != 1)
 	AOAC_DEVICE(FCH_AOAC_DEV_UART1, 0)
+#endif
 }
 
 Device (FUR2) {
@@ -168,8 +170,9 @@ Device (FUR2) {
 	{
 		Return (STAT)
 	}
-
+#if (!CONFIG(CONSOLE_SERIAL) || !CONFIG(AMD_SOC_CONSOLE_UART) || CONFIG_UART_FOR_CONSOLE != 2)
 	AOAC_DEVICE(FCH_AOAC_DEV_UART2, 0)
+#endif
 }
 
 Device (FUR3) {
@@ -205,8 +208,9 @@ Device (FUR3) {
 	{
 		Return (STAT)
 	}
-
+#if (!CONFIG(CONSOLE_SERIAL) || !CONFIG(AMD_SOC_CONSOLE_UART) || CONFIG_UART_FOR_CONSOLE != 3)
 	AOAC_DEVICE(FCH_AOAC_DEV_UART3, 0)
+#endif
 }
 
 Device (FUR4) {

From ad8ccf48225f1ba5c32a12096f2d391c6b5a5303 Mon Sep 17 00:00:00 2001
From: Yidi Lin <yidilin@google.com>
Date: Tue, 3 Jun 2025 23:15:46 +0000
Subject: [PATCH 1203/3886] Update arm-trusted-firmware submodule to upstream
 master

Updating from commit id 57ac3f74b34a:
2025-04-09 20:07:35 +0200 - (Merge "feat(stm32mp15-fdts): add Linux Automation GmbH TAC" into integration)

to commit id b68861c7298d:
2025-05-15 14:26:57 +0000 - (Merge "docs(changelog): add missing scopes" into integration)

This brings in 224 new commits.

Change-Id: I0fb2d05cd763ac1f36ffb5b8e485da931bd86aa8
Signed-off-by: Yidi Lin <yidilin@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87926
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 3rdparty/arm-trusted-firmware | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/3rdparty/arm-trusted-firmware b/3rdparty/arm-trusted-firmware
index 57ac3f74b3..b68861c729 160000
--- a/3rdparty/arm-trusted-firmware
+++ b/3rdparty/arm-trusted-firmware
@@ -1 +1 @@
-Subproject commit 57ac3f74b34a3303f03deee264a1f2247c68008d
+Subproject commit b68861c7298d981545f89bb95a468c23420b49bb

From 2cb9c3ee46acc4721afeb88b575e87985a888eb4 Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Wed, 28 May 2025 20:23:27 +0100
Subject: [PATCH 1204/3886] mb/starlabs/byte_adl: Update the VBT to the Twin
 Lake version

This version of the VBT works for Alder Lake N and Twin Lake.

Change-Id: Ia2161a04018ec3e222a2751b42fe63637b05e6dd
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87895
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 .../starlabs/byte_adl/variants/mk_ii/data.vbt | Bin 9216 -> 9216 bytes
 1 file changed, 0 insertions(+), 0 deletions(-)

diff --git a/src/mainboard/starlabs/byte_adl/variants/mk_ii/data.vbt b/src/mainboard/starlabs/byte_adl/variants/mk_ii/data.vbt
index aa4ea41575c2d078c54535db011da581d6f931e0..657e3a4918a2058955aa86c291d576f3532c055a 100644
GIT binary patch
delta 365
zcmZqhXz-XI!K$bv%wRA%kx_V}fdDH5qZq@7g|3VqEDQ_`4nWKZ#4JD-3y|di#2{J$
zC=3yYr~&dB1b~<ch(Y2Yf@vxv6VMEe$-Ru~jQ=KYVN|dG$HH(afk8lk!BG*Unt_2G
zqU8Wkg92C|NRWZyp990O43N55s5)K-24<l60fq#qIuH-2P64W}5~_|L<W!Kl0#tQi
z+XR>e7^Y5+WRm0h2XZIK{Ed?vKwL(KYhY)coxB{x1$zM~`*QL*COM$f6WKH-3o~m9
zUu8Z4(uWKt2Q%9;{+`^+oW}7V2)Ir&a7}h(Y1v%Q@|KG+X>u;V|KtKjk<EMf)kFYi
CCOswq

delta 282
zcmZqhXz-XI!OE=kn89E&BeU>C0|D0G3}OtI7P>NuJ1{UXumCY5n05fN85tZH7$+yP
zX>u@iGcp0?)F<~cs!!g^s4mFDa4CU7K!8D6Q2?kMsA=*$MlntYhGQ8ZQTxe!OcG`w
zgBTbTpkmQbmHZG}4loojDu7i$l!1)_YAv4}$0Wze1kwrQO`hBa<S{~xSU-6kkOy`k
zQ10~PYfN&J)7aD}%Q9<<pJqM*(t`q`S-B=hGTSn7rc6G-Y&&^9vkJ>9AlS^vQp(Nf
SH@TeOfAcMVHIc~$Y;pi9Br%-;


From c589142c28908cf9326a83282cf65c2f123ed36a Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Wed, 28 May 2025 20:25:12 +0100
Subject: [PATCH 1205/3886] mb/starlabs/byte_adl: Add the Byte Mk III variant

The Byte Mk III is the same, apart from using the Twin Lane N355 instead
of the N200, which means 99.99% of the code is the same.

Change-Id: Ia31f905bea7a6efdad1ed4e36361059ceea2a1ed
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87896
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
---
 src/mainboard/starlabs/byte_adl/Kconfig              | 12 ++++++++++++
 src/mainboard/starlabs/byte_adl/Kconfig.name         |  3 +++
 .../starlabs/byte_adl/variants/mk_ii/devtree.c       |  8 +++++++-
 3 files changed, 22 insertions(+), 1 deletion(-)

diff --git a/src/mainboard/starlabs/byte_adl/Kconfig b/src/mainboard/starlabs/byte_adl/Kconfig
index c1b7121194..a2d7c047b8 100644
--- a/src/mainboard/starlabs/byte_adl/Kconfig
+++ b/src/mainboard/starlabs/byte_adl/Kconfig
@@ -30,6 +30,11 @@ config BOARD_STARLABS_BYTE_ADL
 	select SOC_INTEL_ALDERLAKE
 	select SOC_INTEL_ALDERLAKE_PCH_N
 
+config BOARD_STARLABS_BYTE_TWL
+	select BOARD_STARLABS_BYTE_SERIES
+	select SOC_INTEL_ALDERLAKE
+	select SOC_INTEL_TWINLAKE
+
 if BOARD_STARLABS_BYTE_SERIES
 
 config CONSOLE_SERIAL
@@ -68,9 +73,11 @@ config MAINBOARD_DIR
 
 config MAINBOARD_FAMILY
 	string
+	default "Y3" if BOARD_STARLABS_BYTE_TWL
 	default "Y2"
 
 config MAINBOARD_PART_NUMBER
+	default "Byte Mk III" if BOARD_STARLABS_BYTE_TWL
 	default "Byte Mk II"
 
 config MAINBOARD_SMBIOS_PRODUCT_NAME
@@ -80,6 +87,11 @@ config ME_BIN_PATH
 	string
 	default "3rdparty/blobs/mainboard/\$(MAINBOARDDIR)/\$(CONFIG_VARIANT_DIR)/intel_me.bin"
 
+config PL4_WATTS
+	int
+	default 84 if BOARD_STARLABS_BYTE_TWL
+	default 36
+
 config POWER_STATE_DEFAULT_ON_AFTER_FAILURE
 	default n
 
diff --git a/src/mainboard/starlabs/byte_adl/Kconfig.name b/src/mainboard/starlabs/byte_adl/Kconfig.name
index f46e376980..bb393c0daa 100644
--- a/src/mainboard/starlabs/byte_adl/Kconfig.name
+++ b/src/mainboard/starlabs/byte_adl/Kconfig.name
@@ -2,3 +2,6 @@ comment "Star Labs Byte Series"
 
 config BOARD_STARLABS_BYTE_ADL
 	bool "Star Labs Byte Mk II (N200)"
+
+config BOARD_STARLABS_BYTE_TWL
+	bool "Star Labs Byte Mk III (N355)"
diff --git a/src/mainboard/starlabs/byte_adl/variants/mk_ii/devtree.c b/src/mainboard/starlabs/byte_adl/variants/mk_ii/devtree.c
index f10cfed870..eb1710dc4a 100644
--- a/src/mainboard/starlabs/byte_adl/variants/mk_ii/devtree.c
+++ b/src/mainboard/starlabs/byte_adl/variants/mk_ii/devtree.c
@@ -18,6 +18,8 @@ void devtree_update(void)
 
 	struct soc_power_limits_config *soc_conf_4core =
 		&cfg->power_limits_config[ADL_N_041_6W_CORE];
+	struct soc_power_limits_config *soc_conf_8core =
+		&cfg->power_limits_config[ADL_N_041_15W_CORE];
 
 	struct device *nic_dev = pcidev_on_root(0x14, 3);
 	struct device *gna_dev = pcidev_on_root(0x08, 0);
@@ -25,10 +27,11 @@ void devtree_update(void)
 	uint8_t performance_scale = 100;
 
 	/* Set PL4 to 1.0C */
-	soc_conf_4core->tdp_pl4				= 36;
+	soc_conf_4core->tdp_pl4				= CONFIG_PL4_WATTS;
 
 	/* Set PL1 to 50% of PL2 */
 	soc_conf_4core->tdp_pl1_override = (soc_conf_4core->tdp_pl2_override / 2) & ~1;
+	soc_conf_8core->tdp_pl1_override = (soc_conf_8core->tdp_pl2_override / 2) & ~1;
 
 	/* Scale PL1 & PL2 based on CMOS settings */
 	switch (get_power_profile(PP_POWER_SAVER)) {
@@ -49,6 +52,9 @@ void devtree_update(void)
 	soc_conf_4core->tdp_pl1_override = (soc_conf_4core->tdp_pl1_override * performance_scale) / 100;
 	soc_conf_4core->tdp_pl2_override = (soc_conf_4core->tdp_pl2_override * performance_scale) / 100;
 
+	soc_conf_8core->tdp_pl1_override = (soc_conf_8core->tdp_pl1_override * performance_scale) / 100;
+	soc_conf_8core->tdp_pl2_override = (soc_conf_8core->tdp_pl2_override * performance_scale) / 100;
+
 	/* Enable/Disable Bluetooth based on CMOS settings */
 	if (get_uint_option("wireless", 1) == 0) {
 		cfg->usb2_ports[9].enable = 0;

From 5f9046cbb4dca00f08a806f5cde4d1dd35c718bf Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Wed, 4 Jun 2025 11:08:06 +0100
Subject: [PATCH 1206/3886] mb/starlabs/byte_adl: Remove vGPIO configuration

Remove the configuration for the vGPIOs, as it is not needed because
FSP handles it.

Change-Id: I8831379ffd8c9df00736cb62512e023592d0d301
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87936
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
---
 .../starlabs/byte_adl/variants/mk_ii/gpio.c   | 31 -------------------
 1 file changed, 31 deletions(-)

diff --git a/src/mainboard/starlabs/byte_adl/variants/mk_ii/gpio.c b/src/mainboard/starlabs/byte_adl/variants/mk_ii/gpio.c
index 6b9fb5be6e..5c692691d3 100644
--- a/src/mainboard/starlabs/byte_adl/variants/mk_ii/gpio.c
+++ b/src/mainboard/starlabs/byte_adl/variants/mk_ii/gpio.c
@@ -430,37 +430,6 @@ const struct pad_config gpio_table[] = {
 	PAD_NC(GPP_R6, NONE),
 	/* R7:		Not Connected					*/
 	PAD_NC(GPP_R7, NONE),
-
-	/* CNV_BTEN */
-	PAD_CFG_GPO(GPP_VGPIO_0, 1, DEEP),
-	/* CNV_BT_HOST_WAKEB */
-	PAD_NC(GPP_VGPIO_4, NONE),
-	/* CNV_BT_IF_SELECT */
-	PAD_CFG_GPO(GPP_VGPIO_5, 1, DEEP),
-	/* vCNV_BT_UART_TXD */
-	PAD_NC(GPP_VGPIO_6, NONE),
-	/* vCNV_BT_UART_RXD */
-	PAD_NC(GPP_VGPIO_7, NONE),
-	/* vCNV_BT_UART_CTS_B */
-	PAD_NC(GPP_VGPIO_8, NONE),
-	/* vCNV_BT_UART_RTS_B */
-	PAD_NC(GPP_VGPIO_9, NONE),
-	/* vUART0_TXD */
-	PAD_NC(GPP_VGPIO_18, NONE),
-	/* vUART0_RXD */
-	PAD_NC(GPP_VGPIO_19, NONE),
-	/* vUART0_CTS_B */
-	PAD_NC(GPP_VGPIO_20, NONE),
-	/* vUART0_RTS_B */
-	PAD_NC(GPP_VGPIO_21, NONE),
-	/* BT_I2S_BCLK */
-	PAD_NC(GPP_VGPIO_30, NONE),
-	/* BT_I2S_SYNC */
-	PAD_NC(GPP_VGPIO_31, NONE),
-	/* BT_I2S_SDO */
-	PAD_NC(GPP_VGPIO_32, NONE),
-	/* BT_I2S_SDI */
-	PAD_NC(GPP_VGPIO_33, NONE),
 };
 
 const struct pad_config *variant_gpio_table(size_t *num)

From 6aeebc4b4b6055b3638b19a9cd933c005757f748 Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Wed, 4 Jun 2025 11:13:18 +0100
Subject: [PATCH 1207/3886] mb/starlabs/byte_adl: Reconfigure PCH Strap GPIOs

Configure all strap GPIOs as outputs, rather than some being not
connected. This doesn't change anything, but is more explicit.

Set these all to sample on RSMRST.

Change-Id: I693cfecdb73a20b76fa040500eed5d904b857710
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87937
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
---
 .../starlabs/byte_adl/variants/mk_ii/gpio.c   | 51 ++++++-------------
 1 file changed, 15 insertions(+), 36 deletions(-)

diff --git a/src/mainboard/starlabs/byte_adl/variants/mk_ii/gpio.c b/src/mainboard/starlabs/byte_adl/variants/mk_ii/gpio.c
index 5c692691d3..fc963f7645 100644
--- a/src/mainboard/starlabs/byte_adl/variants/mk_ii/gpio.c
+++ b/src/mainboard/starlabs/byte_adl/variants/mk_ii/gpio.c
@@ -75,16 +75,26 @@ const struct pad_config gpio_table[] = {
 	PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1),				/* Data */
 	PAD_CFG_GPO(GPP_E8, 1, DEEP),					/* DRAM Sleep */
 
+	/* Config Straps 									[ Low      / High     ] */
+	PAD_CFG_GPO(GPP_B14, 0, RSMRST),				/* Top Swap		[ Disabled / Enabled  ] */
+	PAD_CFG_GPO(GPP_B18, 0, RSMRST),				/* Reboot Support	[ Enabled  / Disabled ] */
+	PAD_CFG_GPO(GPP_C2, 1, RSMRST),					/* TLS Confidentiality	[ Disabled / Enabled  ] */
+	PAD_CFG_GPO(GPP_C5, 0, RSMRST),					/* eSPI			[ Enabled  / Disabled ] */
+	PAD_CFG_GPO(GPP_E6, 0, RSMRST),					/* JTAG ODT		[ Disabled / Enabled  ] */
+	PAD_CFG_GPO(GPP_H1, 0, RSMRST),					/* BFX Strap 2 Bit 3	[ Disabled / Enabled  ] */
+	PAD_CFG_GPO(GPP_E19, 0, RSMRST),				/* TBT LSX #0		[ 1.8V     / 3.3V     ] */
+	PAD_CFG_GPO(GPP_E21, 0, RSMRST),				/* TBT LSX #1           [ 1.8V     / 3.3V     ] */
+	PAD_CFG_GPO(GPP_D10, 0, RSMRST),				/* TBT LSX #2		[ 1.8V     / 3.3V     ] */
+	PAD_CFG_GPO(GPP_D12, 0, RSMRST),				/* TBT LSX #3		[ 1.8V     / 3.3V     ] */
+	PAD_CFG_GPO(GPP_F7, 0, RSMRST),					/* MCRO LDO		[ Disabled / Bypass   ] */
+	PAD_CFG_GPO(GPD7, 0, RSMRST),					/* RTC Clock Delay	[ Disabled / 95ms     ] */
+
 	/* GPD2:	LAN Wake					*/
 	PAD_NC(GPD2, NONE),
 	/* GPD6:	Sleep A						*/
 	PAD_NC(GPD6, NONE),
-	/* GPD7:	Power Adapter Disable				*/
-	PAD_CFG_GPO(GPD7, 0, PWROK),
 	/* GPD9:	Wireless LAN Sleep				*/
 	PAD_NC(GPD9, NONE),
-	/* GPD10:	Sleep S5					*/
-	PAD_NC(GPD10, NONE),
 	/* GPD11:	LAN PHY Enable					*/
 	PAD_NC(GPD11, NONE),
 
@@ -138,20 +148,12 @@ const struct pad_config gpio_table[] = {
 	PAD_CFG_NF(GPP_B11, NONE, DEEP, NF1),
 	/* B12:		PM SLP S0					*/
 	PAD_NC(GPP_B12, NONE),
-	/* B14:		Top Swap Override	Weak Internal PD 20K
-				High:	Enabled
-				Low:	Disabled			*/
-	PAD_CFG_GPO(GPP_B14, 0, PLTRST),
 	/* B15:		Not Connected					*/
 	PAD_NC(GPP_B15, NONE),
 	/* B16:		Not Connected					*/
 	PAD_NC(GPP_B16, NONE),
 	/* B17:		Not Connected					*/
 	PAD_NC(GPP_B17, NONE),
-	/* B18:		Reboot Support		Weak Internal PD 20K
-				High:	Disabled
-				Low:	Enabled				*/
-	PAD_NC(GPP_B18, NONE),
 	/* B19:		Not Connected					*/
 	PAD_NC(GPP_B19, NONE),
 	/* B20:		Not Connected					*/
@@ -167,18 +169,10 @@ const struct pad_config gpio_table[] = {
 	/* B25:		Not Connected					*/
 	PAD_NC(GPP_B25, NONE),
 
-	/* C2:		TLS Confidentiality	Weak Internal PD 20K
-				Low:	Disabled
-				High:	Enabled				*/
-	PAD_CFG_GPO(GPP_C2, 1, PLTRST),
 	/* C3:		SML 0 Clock					*/
 	PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1),
 	/* C4:		SML 0 Data					*/
 	PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1),
-	/* C5:		Boot Strap		Weak Internal PD 20K
-				Low:	ESPI
-				High:	Disabled			*/
-	PAD_CFG_GPO(GPP_C5, 0, DEEP),
 	/* C6:		SML 1 Clock					*/
 	PAD_CFG_NF(GPP_C6, NONE, DEEP, NF1),
 	/* C7:		SML 1 Data					*/
@@ -238,8 +232,6 @@ const struct pad_config gpio_table[] = {
 	PAD_NC(GPP_D10, NONE),
 	/* D11:		GSPI 2 MISO FPS					*/
 	PAD_NC(GPP_D11, NONE),
-	/* D12:		GSPI 2 MOSI FPS					*/
-	PAD_NC(GPP_D12, NONE),
 	/* D13:		Wireless LAN Wake				*/
 	PAD_NC(GPP_D13, NONE),
 	/* D14:		Test Point 10					*/
@@ -263,10 +255,7 @@ const struct pad_config gpio_table[] = {
 	PAD_NC(GPP_E4, NONE),
 	/* E5:		Not Connected					*/
 	PAD_NC(GPP_E5, NONE),
-	/* E6:		JTAG ODT		No internal PD
-				Low:	Disabled
-				High:	Enabled				*/
-	PAD_CFG_GPO(GPP_E6, 0, DEEP),
+
 	/* E7:		Embedded Controller SMI				*/
 	PAD_NC(GPP_E7, NONE),
 	/* E9:		USB OverCurrent 0				*/
@@ -287,12 +276,8 @@ const struct pad_config gpio_table[] = {
 	PAD_NC(GPP_E17, NONE),
 	/* E18:		Not Connected					*/
 	PAD_NC(GPP_E18, NONE),
-	/* E19:		Thunderbolt LSX RXD				*/
-	PAD_NC(GPP_E19, NONE),
 	/* E20:		Not Connected					*/
 	PAD_NC(GPP_E20, NONE),
-	/* E21:		Not Connected					*/
-	PAD_NC(GPP_E21, NONE),
 	/* E22:		Not Connected					*/
 	PAD_NC(GPP_E22, NONE),
 	/* E23:		Not Connected					*/
@@ -300,10 +285,6 @@ const struct pad_config gpio_table[] = {
 
 	/* F6:		CNV PA Blanking					*/
 	PAD_NC(GPP_F6, NONE),
-	/* F7:		TBT LSX VCCIO		Weak Internal PD 20K
-				Low:	1.8V
-				High:	3.3V				*/
-	PAD_CFG_GPO(GPP_F7, 0, DEEP),
 	/* F8:		Not Connected					*/
 	PAD_NC(GPP_F8, NONE),
 	/* F9:								*/
@@ -337,8 +318,6 @@ const struct pad_config gpio_table[] = {
 	/* F23:		Not Connected					*/
 	PAD_NC(GPP_F23, NONE),
 
-	/* H1:		BFX Strap 2 Bit 3	Weak Internal PD 20K	*/
-	PAD_CFG_GPO(GPP_H1, 0, DEEP),
 	/* H2:		Wireless LAN Reset				*/
 	PAD_CFG_GPO(GPP_H2, 1, PLTRST),
 	/* H3:		Not Connected					*/

From 63f781b508057c332dbdd4840e846ed3bb8e472b Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Wed, 4 Jun 2025 11:20:09 +0100
Subject: [PATCH 1208/3886] mb/starlabs/byte_adl: Disconnect unused GPIOs

GPIOs, like the USB overcurrent ones, are not used so configure them accordingly.

Change-Id: If5138ccd6048f006408d5335439e7a0143c9cc28
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87938
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
---
 .../starlabs/byte_adl/variants/mk_ii/gpio.c   | 21 ++++++++++---------
 1 file changed, 11 insertions(+), 10 deletions(-)

diff --git a/src/mainboard/starlabs/byte_adl/variants/mk_ii/gpio.c b/src/mainboard/starlabs/byte_adl/variants/mk_ii/gpio.c
index fc963f7645..5380a6be2b 100644
--- a/src/mainboard/starlabs/byte_adl/variants/mk_ii/gpio.c
+++ b/src/mainboard/starlabs/byte_adl/variants/mk_ii/gpio.c
@@ -54,7 +54,6 @@ const struct pad_config gpio_table[] = {
 	PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1),				/* HDMI Hot Plug */
 	PAD_CFG_NF(GPP_H15, NONE, DEEP, NF1),				/* HDMI Clock */
 	PAD_CFG_NF(GPP_H17, NONE, DEEP, NF1),				/* HDMI Data */
-	PAD_CFG_NF(GPP_A19, NONE, DEEP, NF1),				/* TCP0 Hot Plug */
 
 	/* High-Definition Audio */
 	PAD_CFG_NF(GPP_R0, NATIVE, DEEP, NF1),				/* Clock */
@@ -109,15 +108,17 @@ const struct pad_config gpio_table[] = {
 	/* A11:		Webcam Camera Reset				*/
 	PAD_NC(GPP_A11, NONE),
 	/* A12:		PCH M.2 SSD PEDET				*/
-	PAD_CFG_NF(GPP_A12, NONE, DEEP, NF1),
+	PAD_NC(GPP_A12, NONE),
 	/* A14:		Type C VBUS OverCurrent				*/
-	PAD_CFG_NF(GPP_A14, NONE, DEEP, NF1),
+	PAD_NC(GPP_A14, NONE),
 	/* A15:		Test Point 3					*/
 	PAD_NC(GPP_A15, NONE),
 	/* A16:		USB 2 OverCurrent B				*/
-	PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1),
+	PAD_NC(GPP_A16, NONE),
 	/* A17:		Not Connected					*/
 	PAD_NC(GPP_A17, NONE),
+	/* A19:		TCP0 Hot Plug					*/
+	PAD_NC(GPP_A19, NONE),
 	/* A20:		Test Point 2					*/
 	PAD_NC(GPP_A20, NONE),
 	/* A21:		Fingerprint Reader Interrupt			*/
@@ -170,9 +171,9 @@ const struct pad_config gpio_table[] = {
 	PAD_NC(GPP_B25, NONE),
 
 	/* C3:		SML 0 Clock					*/
-	PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1),
+	PAD_NC(GPP_C3, NONE),
 	/* C4:		SML 0 Data					*/
-	PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1),
+	PAD_NC(GPP_C4, NONE),
 	/* C6:		SML 1 Clock					*/
 	PAD_CFG_NF(GPP_C6, NONE, DEEP, NF1),
 	/* C7:		SML 1 Data					*/
@@ -259,7 +260,7 @@ const struct pad_config gpio_table[] = {
 	/* E7:		Embedded Controller SMI				*/
 	PAD_NC(GPP_E7, NONE),
 	/* E9:		USB OverCurrent 0				*/
-	PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1),
+	PAD_NC(GPP_E9, NONE),
 	/* E10:		Not Connected					*/
 	PAD_NC(GPP_E10, NONE),
 	/* E11:		Not Connected					*/
@@ -290,7 +291,7 @@ const struct pad_config gpio_table[] = {
 	/* F9:								*/
 	PAD_NC(GPP_F9, NONE),
 	/* F10:		Weak Internal PD 20K				*/
-	PAD_CFG_GPO(GPP_F10, 1, PLTRST),
+	PAD_NC(GPP_F10, NONE),
 	/* F11:		Not Connected					*/
 	PAD_NC(GPP_F11, NONE),
 	/* F12:		Not Connected					*/
@@ -312,14 +313,14 @@ const struct pad_config gpio_table[] = {
 	/* F20:		CPU M.2 SSD Reset				*/
 	PAD_NC(GPP_F20, NONE),
 	/* F21:		GPPC_F21					*/
-	PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1),
+	PAD_NC(GPP_F21, NONE),
 	/* F22:		Not Connected					*/
 	PAD_NC(GPP_F22, NONE),
 	/* F23:		Not Connected					*/
 	PAD_NC(GPP_F23, NONE),
 
 	/* H2:		Wireless LAN Reset				*/
-	PAD_CFG_GPO(GPP_H2, 1, PLTRST),
+	PAD_NC(GPP_H2, NONE),
 	/* H3:		Not Connected					*/
 	PAD_NC(GPP_H3, NONE),
 	/* H4:		I2C 0 SDA		GSensor			*/

From f6a45f6856900a02be3b1d38afb536c5d88de5d8 Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Wed, 4 Jun 2025 11:24:25 +0100
Subject: [PATCH 1209/3886] mb/starlabs/byte_adl: Re-organise GPIOs

Put the GPIOs into groups with clear comments.

Change-Id: I7246fee8bdf111bc08c1335a90609e94356fc611
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87939
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
---
 .../starlabs/byte_adl/variants/mk_ii/gpio.c   | 19 +++++++++----------
 1 file changed, 9 insertions(+), 10 deletions(-)

diff --git a/src/mainboard/starlabs/byte_adl/variants/mk_ii/gpio.c b/src/mainboard/starlabs/byte_adl/variants/mk_ii/gpio.c
index 5380a6be2b..883776dde8 100644
--- a/src/mainboard/starlabs/byte_adl/variants/mk_ii/gpio.c
+++ b/src/mainboard/starlabs/byte_adl/variants/mk_ii/gpio.c
@@ -49,11 +49,20 @@ const struct pad_config gpio_table[] = {
 	PAD_CFG_GPO(GPP_E3, 1, DEEP),					/* WiFi RF Kill */
 	PAD_CFG_GPO(GPP_A13, 1, DEEP),					/* Bluetooth RF Kill */
 
+	/* LAN 1 */
+	PAD_CFG_NF(GPP_D7, NONE, DEEP, NF1),				/* Clock Request 2 */
+
+	/* LAN 2 */
+	PAD_CFG_NF(GPP_D8, NONE, DEEP, NF1),				/* Clock Request 3 */
+
 	/* Display */
 	PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1),				/* eDP Hot Plug */
 	PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1),				/* HDMI Hot Plug */
 	PAD_CFG_NF(GPP_H15, NONE, DEEP, NF1),				/* HDMI Clock */
 	PAD_CFG_NF(GPP_H17, NONE, DEEP, NF1),				/* HDMI Data */
+	PAD_CFG_NF(GPP_B11, NONE, DEEP, NF1),				/* PMC Interrupt */
+	PAD_CFG_NF(GPP_C6, NONE, DEEP, NF1),				/* SML Clock */
+	PAD_CFG_NF(GPP_C7, NONE, DEEP, NF1),				/* SML Data */
 
 	/* High-Definition Audio */
 	PAD_CFG_NF(GPP_R0, NATIVE, DEEP, NF1),				/* Clock */
@@ -145,8 +154,6 @@ const struct pad_config gpio_table[] = {
 	PAD_NC(GPP_B9, NONE),
 	/* B10:		Not Connected					*/
 	PAD_NC(GPP_B10, NONE),
-	/* B11:		I2C PMC PD Interrupt	Test Point 28		*/
-	PAD_CFG_NF(GPP_B11, NONE, DEEP, NF1),
 	/* B12:		PM SLP S0					*/
 	PAD_NC(GPP_B12, NONE),
 	/* B15:		Not Connected					*/
@@ -174,10 +181,6 @@ const struct pad_config gpio_table[] = {
 	PAD_NC(GPP_C3, NONE),
 	/* C4:		SML 0 Data					*/
 	PAD_NC(GPP_C4, NONE),
-	/* C6:		SML 1 Clock					*/
-	PAD_CFG_NF(GPP_C6, NONE, DEEP, NF1),
-	/* C7:		SML 1 Data					*/
-	PAD_CFG_NF(GPP_C7, NONE, DEEP, NF1),
 	/* C8:		Not Connected					*/
 	PAD_NC(GPP_C8, NONE),
 	/* C9:		Not Connected					*/
@@ -223,10 +226,6 @@ const struct pad_config gpio_table[] = {
 	PAD_NC(GPP_D4, NONE),
 	/* D6:		Clock Request 1		Wireless LAN		*/
 	PAD_NC(GPP_D6, NONE),
-	/* D7:		Clock Request 2		LAN 1			*/
-	PAD_CFG_NF(GPP_D7, NONE, DEEP, NF1),
-	/* D8:		Clock Request 3		LAN 2			*/
-	PAD_CFG_NF(GPP_D8, NONE, DEEP, NF1),
 	/* D9:		GSPI 2 FPS					*/
 	PAD_NC(GPP_D9, NONE),
 	/* D10:		GSPI 2 Clock					*/

From 6d079d45d1321ebda75f798326fe42df9acde5aa Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Wed, 4 Jun 2025 11:31:16 +0100
Subject: [PATCH 1210/3886] mb/starlabs/byte_adl: Remove comments for
 disconnected GPIOs

Change-Id: I0ea02d7290533cf33d9b793bfbd18ec9915c975e
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87940
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
---
 .../starlabs/byte_adl/variants/mk_ii/gpio.c   | 151 ------------------
 1 file changed, 151 deletions(-)

diff --git a/src/mainboard/starlabs/byte_adl/variants/mk_ii/gpio.c b/src/mainboard/starlabs/byte_adl/variants/mk_ii/gpio.c
index 883776dde8..b6aa4dbdbc 100644
--- a/src/mainboard/starlabs/byte_adl/variants/mk_ii/gpio.c
+++ b/src/mainboard/starlabs/byte_adl/variants/mk_ii/gpio.c
@@ -97,317 +97,166 @@ const struct pad_config gpio_table[] = {
 	PAD_CFG_GPO(GPP_F7, 0, RSMRST),					/* MCRO LDO		[ Disabled / Bypass   ] */
 	PAD_CFG_GPO(GPD7, 0, RSMRST),					/* RTC Clock Delay	[ Disabled / 95ms     ] */
 
-	/* GPD2:	LAN Wake					*/
 	PAD_NC(GPD2, NONE),
-	/* GPD6:	Sleep A						*/
 	PAD_NC(GPD6, NONE),
-	/* GPD9:	Wireless LAN Sleep				*/
 	PAD_NC(GPD9, NONE),
-	/* GPD11:	LAN PHY Enable					*/
 	PAD_NC(GPD11, NONE),
 
-	/* A5:		Not Connected					*/
 	PAD_NC(GPP_A5, NONE),
-	/* A6:		Not Connected					*/
 	PAD_NC(GPP_A6, NONE),
-	/* A7:		Embedded Controller SCI				*/
 	PAD_NC(GPP_A7, NONE),
-	/* A8:		Not Connected					*/
 	PAD_NC(GPP_A8, NONE),
-	/* A11:		Webcam Camera Reset				*/
 	PAD_NC(GPP_A11, NONE),
-	/* A12:		PCH M.2 SSD PEDET				*/
 	PAD_NC(GPP_A12, NONE),
-	/* A14:		Type C VBUS OverCurrent				*/
 	PAD_NC(GPP_A14, NONE),
-	/* A15:		Test Point 3					*/
 	PAD_NC(GPP_A15, NONE),
-	/* A16:		USB 2 OverCurrent B				*/
 	PAD_NC(GPP_A16, NONE),
-	/* A17:		Not Connected					*/
 	PAD_NC(GPP_A17, NONE),
-	/* A19:		TCP0 Hot Plug					*/
 	PAD_NC(GPP_A19, NONE),
-	/* A20:		Test Point 2					*/
 	PAD_NC(GPP_A20, NONE),
-	/* A21:		Fingerprint Reader Interrupt			*/
 	PAD_NC(GPP_A21, NONE),
-	/* A22:		Fingerprint Reader Reset			*/
 	PAD_NC(GPP_A22, NONE),
-	/* A23:		Not Connected					*/
 	PAD_NC(GPP_A23, NONE),
 
-
-	/* B3:		Not Connected					*/
 	PAD_NC(GPP_B3, NONE),
-	/* B4:		Not Connected					*/
 	PAD_NC(GPP_B4, NONE),
-	/* B5:		I2C 2 SDA		Touch Panel SDA		*/
 	PAD_NC(GPP_B5, NONE),
-	/* B6:		I2C 2 SCL		Touch Panel Clock	*/
 	PAD_NC(GPP_B6, NONE),
-	/* B7:		I2C 3 SDA		Touchpad SDA		*/
 	PAD_NC(GPP_B7, NONE),
-	/* B8:		I2C 3 SCL		Touchpad Clock		*/
 	PAD_NC(GPP_B8, NONE),
-	/* B9:		Not Connected					*/
 	PAD_NC(GPP_B9, NONE),
-	/* B10:		Not Connected					*/
 	PAD_NC(GPP_B10, NONE),
-	/* B12:		PM SLP S0					*/
 	PAD_NC(GPP_B12, NONE),
-	/* B15:		Not Connected					*/
 	PAD_NC(GPP_B15, NONE),
-	/* B16:		Not Connected					*/
 	PAD_NC(GPP_B16, NONE),
-	/* B17:		Not Connected					*/
 	PAD_NC(GPP_B17, NONE),
-	/* B19:		Not Connected					*/
 	PAD_NC(GPP_B19, NONE),
-	/* B20:		Not Connected					*/
 	PAD_NC(GPP_B20, NONE),
-	/* B21:		Not Connected					*/
 	PAD_NC(GPP_B21, NONE),
-	/* B22:		Not Connected					*/
 	PAD_NC(GPP_B22, NONE),
-	/* B23:		Not used	MiPi Camera			*/
 	PAD_NC(GPP_B23, NONE),
-	/* B24:		Not Connected					*/
 	PAD_NC(GPP_B24, NONE),
-	/* B25:		Not Connected					*/
 	PAD_NC(GPP_B25, NONE),
 
-	/* C3:		SML 0 Clock					*/
 	PAD_NC(GPP_C3, NONE),
-	/* C4:		SML 0 Data					*/
 	PAD_NC(GPP_C4, NONE),
-	/* C8:		Not Connected					*/
 	PAD_NC(GPP_C8, NONE),
-	/* C9:		Not Connected					*/
 	PAD_NC(GPP_C9, NONE),
-	/* C10:		Not Connected					*/
 	PAD_NC(GPP_C10, NONE),
-	/* C11:		Not Connected					*/
 	PAD_NC(GPP_C11, NONE),
-	/* C12:		Not Connected					*/
 	PAD_NC(GPP_C12, NONE),
-	/* C13:		Not Connected					*/
 	PAD_NC(GPP_C13, NONE),
-	/* C14:		Not Connected					*/
 	PAD_NC(GPP_C14, NONE),
-	/* C15:		Not Connected					*/
 	PAD_NC(GPP_C15, NONE),
-	/* C16:		Not Connected					*/
 	PAD_NC(GPP_C16, NONE),
-	/* C17:		Not Connected					*/
 	PAD_NC(GPP_C17, NONE),
-	/* C18:		Not Connected					*/
 	PAD_NC(GPP_C18, NONE),
-	/* C19:		Not Connected					*/
 	PAD_NC(GPP_C19, NONE),
-	/* C20:		Not Connected					*/
 	PAD_NC(GPP_C20, NONE),
-	/* C21:		Not Connected					*/
 	PAD_NC(GPP_C21, NONE),
-	/* C22:		Not Connected					*/
 	PAD_NC(GPP_C22, NONE),
-	/* C23:		Not Connected					*/
 	PAD_NC(GPP_C23, NONE),
 
-	/* D0:		Not used		Audio ID 0		*/
 	PAD_NC(GPP_D0, NONE),
-	/* D1:		Not used		Audio ID 1		*/
 	PAD_NC(GPP_D1, NONE),
-	/* D2:		Not used		Audio ID 2		*/
 	PAD_NC(GPP_D2, NONE),
-	/* D3:		Not Connected					*/
 	PAD_NC(GPP_D3, NONE),
-	/* D4:		Not Connected					*/
 	PAD_NC(GPP_D4, NONE),
-	/* D6:		Clock Request 1		Wireless LAN		*/
 	PAD_NC(GPP_D6, NONE),
-	/* D9:		GSPI 2 FPS					*/
 	PAD_NC(GPP_D9, NONE),
-	/* D10:		GSPI 2 Clock					*/
 	PAD_NC(GPP_D10, NONE),
-	/* D11:		GSPI 2 MISO FPS					*/
 	PAD_NC(GPP_D11, NONE),
-	/* D13:		Wireless LAN Wake				*/
 	PAD_NC(GPP_D13, NONE),
-	/* D14:		Test Point 10					*/
 	PAD_NC(GPP_D14, NONE),
-	/* D15:		Not Connected					*/
 	PAD_NC(GPP_D15, NONE),
-	/* D17:		Not Connected					*/
 	PAD_NC(GPP_D17, NONE),
-	/* D18:		Not Connected					*/
 	PAD_NC(GPP_D18, NONE),
-	/* D19:		Test Point 6					*/
 	PAD_NC(GPP_D19, NONE),
 
-	/* E0:		SATA x PCIe					*/
 	PAD_NC(GPP_E0, NONE),
-	/* E1:		Not used		Accelerometer Interrupt	*/
 	PAD_NC(GPP_E1, NONE),
-	/* E2:		Not Connected					*/
 	PAD_NC(GPP_E2, NONE),
-	/* E4:		Test Point 7					*/
 	PAD_NC(GPP_E4, NONE),
-	/* E5:		Not Connected					*/
 	PAD_NC(GPP_E5, NONE),
 
-	/* E7:		Embedded Controller SMI				*/
 	PAD_NC(GPP_E7, NONE),
-	/* E9:		USB OverCurrent 0				*/
 	PAD_NC(GPP_E9, NONE),
-	/* E10:		Not Connected					*/
 	PAD_NC(GPP_E10, NONE),
-	/* E11:		Not Connected					*/
 	PAD_NC(GPP_E11, NONE),
-	/* E12:		Touchpad Interrupt				*/
 	PAD_NC(GPP_E12, NONE),
-	/* E13:		Not connected					*/
 	PAD_NC(GPP_E13, NONE),
-	/* E15:		Not Connected		LAN RESET		*/
 	PAD_NC(GPP_E15, NONE),
-	/* E16:		Not Connected					*/
 	PAD_NC(GPP_E16, NONE),
-	/* E17:		Test Point 1					*/
 	PAD_NC(GPP_E17, NONE),
-	/* E18:		Not Connected					*/
 	PAD_NC(GPP_E18, NONE),
-	/* E20:		Not Connected					*/
 	PAD_NC(GPP_E20, NONE),
-	/* E22:		Not Connected					*/
 	PAD_NC(GPP_E22, NONE),
-	/* E23:		Not Connected					*/
 	PAD_NC(GPP_E23, NONE),
 
-	/* F6:		CNV PA Blanking					*/
 	PAD_NC(GPP_F6, NONE),
-	/* F8:		Not Connected					*/
 	PAD_NC(GPP_F8, NONE),
-	/* F9:								*/
 	PAD_NC(GPP_F9, NONE),
-	/* F10:		Weak Internal PD 20K				*/
 	PAD_NC(GPP_F10, NONE),
-	/* F11:		Not Connected					*/
 	PAD_NC(GPP_F11, NONE),
-	/* F12:		Not Connected					*/
 	PAD_NC(GPP_F12, NONE),
-	/* F13:		Not Connected					*/
 	PAD_NC(GPP_F13, NONE),
-	/* F14:		Not Connected					*/
 	PAD_NC(GPP_F14, NONE),
-	/* F15:		Not Connected					*/
 	PAD_NC(GPP_F15, NONE),
-	/* F16:		Not Connected					*/
 	PAD_NC(GPP_F16, NONE),
-	/* F17:		Not used		Touch Panel Reset	*/
 	PAD_NC(GPP_F17, NONE),
-	/* F18:		Not used		Touch Panel Interrupt	*/
 	PAD_NC(GPP_F18, NONE),
-	/* F19:		Not Connected					*/
 	PAD_NC(GPP_F19, NONE),
-	/* F20:		CPU M.2 SSD Reset				*/
 	PAD_NC(GPP_F20, NONE),
-	/* F21:		GPPC_F21					*/
 	PAD_NC(GPP_F21, NONE),
-	/* F22:		Not Connected					*/
 	PAD_NC(GPP_F22, NONE),
-	/* F23:		Not Connected					*/
 	PAD_NC(GPP_F23, NONE),
 
-	/* H2:		Wireless LAN Reset				*/
 	PAD_NC(GPP_H2, NONE),
-	/* H3:		Not Connected					*/
 	PAD_NC(GPP_H3, NONE),
-	/* H4:		I2C 0 SDA		GSensor			*/
 	PAD_NC(GPP_H4, NONE),
-	/* H5:		I2C 0 SDL		GSensor			*/
 	PAD_NC(GPP_H5, NONE),
-	/* H6:		Test Point 4					*/
 	PAD_NC(GPP_H6, NONE),
-	/* H7:		Test Point 5					*/
 	PAD_NC(GPP_H7, NONE),
-	/* H8:		Not Connected					*/
 	PAD_NC(GPP_H8, NONE),
-	/* H9:		Not Connected					*/
 	PAD_NC(GPP_H9, NONE),
-	/* H12:		Not Connected					*/
 	PAD_NC(GPP_H12, NONE),
-	/* H13:		PCH M.2 SSD Device Sleep			*/
 	PAD_NC(GPP_H13, NONE),
-	/* H14:		Not Connected					*/
 	PAD_NC(GPP_H14, NONE),
-	/* H16:		Not Connected					*/
 	PAD_NC(GPP_H16, NONE),
-	/* H19:		Clock Request 4					*/
 	PAD_NC(GPP_H19, NONE),
-	/* H20:		Not Connected					*/
 	PAD_NC(GPP_H20, NONE),
-	/* H21:		Not Connected					*/
 	PAD_NC(GPP_H21, NONE),
-	/* H22:		Not Connected					*/
 	PAD_NC(GPP_H22, NONE),
-	/* H23:		Clock Request 5					*/
 	PAD_NC(GPP_H23, NONE),
 
-	/* S0:		Not Connected					*/
 	PAD_NC(GPP_S0, NONE),
-	/* S1:		Not Connected					*/
 	PAD_NC(GPP_S1, NONE),
-	/* S2:		Not Connected					*/
 	PAD_NC(GPP_S2, NONE),
-	/* S3:		Not Connected					*/
 	PAD_NC(GPP_S3, NONE),
-	/* S4:		Not Connected					*/
 	PAD_NC(GPP_S4, NONE),
-	/* S5:		Not Connected					*/
 	PAD_NC(GPP_S5, NONE),
-	/* S6:		DMIC Clock					*/
 	PAD_NC(GPP_S6, NONE),
-	/* S7:		DMIC Data					*/
 	PAD_NC(GPP_S7, NONE),
 
-	/* T0:		 Not Connected					*/
 	PAD_NC(GPP_T0, NONE),
-	/* T1:		 Not Connected					*/
 	PAD_NC(GPP_T1, NONE),
-	/* T2:		 Not Connected					*/
 	PAD_NC(GPP_T2, NONE),
-	/* T3:		 Not Connected					*/
 	PAD_NC(GPP_T3, NONE),
-	/* T4:		 Not Connected					*/
 	PAD_NC(GPP_T4, NONE),
-	/* T5:		 Not Connected					*/
 	PAD_NC(GPP_T5, NONE),
-	/* T6:		 Not Connected					*/
 	PAD_NC(GPP_T6, NONE),
-	/* T7:		 Not Connected					*/
 	PAD_NC(GPP_T7, NONE),
-	/* T8:		 Not Connected					*/
 	PAD_NC(GPP_T8, NONE),
-	/* T9:		 Not Connected					*/
 	PAD_NC(GPP_T9, NONE),
-	/* T10:		 Not Connected					*/
 	PAD_NC(GPP_T10, NONE),
-	/* T11:		 Not Connected					*/
 	PAD_NC(GPP_T11, NONE),
-	/* T12:		 Not Connected					*/
 	PAD_NC(GPP_T12, NONE),
-	/* T13:		 Not Connected					*/
 	PAD_NC(GPP_T13, NONE),
-	/* T14:		 Not Connected					*/
 	PAD_NC(GPP_T14, NONE),
-	/* T15:		 Not Connected					*/
 	PAD_NC(GPP_T15, NONE),
 
-	/* R5:		Not Connected					*/
 	PAD_NC(GPP_R5, NONE),
-	/* R6:		Not Connected					*/
 	PAD_NC(GPP_R6, NONE),
-	/* R7:		Not Connected					*/
 	PAD_NC(GPP_R7, NONE),
 };
 

From 9950825a2bd6f39b66479a0c15c7e1c33962e90e Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Wed, 4 Jun 2025 11:34:57 +0100
Subject: [PATCH 1211/3886] mb/starlabs/starlite_adl: Remove extra lines

Change-Id: Iede45ea92ee669a5d1d45f65b3bf23b5fa6d996b
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87941
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
---
 src/mainboard/starlabs/starlite_adl/mainboard.c          | 1 -
 src/mainboard/starlabs/starlite_adl/variants/mk_v/gpio.c | 1 -
 2 files changed, 2 deletions(-)

diff --git a/src/mainboard/starlabs/starlite_adl/mainboard.c b/src/mainboard/starlabs/starlite_adl/mainboard.c
index 99b59253a5..98a4ea0506 100644
--- a/src/mainboard/starlabs/starlite_adl/mainboard.c
+++ b/src/mainboard/starlabs/starlite_adl/mainboard.c
@@ -38,7 +38,6 @@ static void enable_mainboard(struct device *dev)
 	dev->ops->acpi_fill_ssdt = mainboard_fill_ssdt;
 }
 
-
 struct chip_operations mainboard_ops = {
 	.init = init_mainboard,
 	.enable_dev = enable_mainboard,
diff --git a/src/mainboard/starlabs/starlite_adl/variants/mk_v/gpio.c b/src/mainboard/starlabs/starlite_adl/variants/mk_v/gpio.c
index 40cdafa3aa..8e2466f47c 100644
--- a/src/mainboard/starlabs/starlite_adl/variants/mk_v/gpio.c
+++ b/src/mainboard/starlabs/starlite_adl/variants/mk_v/gpio.c
@@ -124,7 +124,6 @@ const struct pad_config gpio_table[] = {
 	PAD_NC(GPP_A22, NONE),
 	PAD_NC(GPP_A23, NONE),
 
-
 	PAD_NC(GPP_B3, NONE),
 	PAD_NC(GPP_B4, NONE),
 	PAD_NC(GPP_B7, NONE),

From cfdf5906fd524423806c52e8624d061c33efcb07 Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Wed, 4 Jun 2025 11:36:47 +0100
Subject: [PATCH 1212/3886] mb/starlabs/starfighter: Tidy comments for board ID
 GPIOs

Change-Id: I5c9af7dd35fd32d1c35fee40a853411af284acaa
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87942
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/starlabs/starfighter/variants/rpl/gpio.c | 6 +-----
 1 file changed, 1 insertion(+), 5 deletions(-)

diff --git a/src/mainboard/starlabs/starfighter/variants/rpl/gpio.c b/src/mainboard/starlabs/starfighter/variants/rpl/gpio.c
index ab97afe180..82872e8413 100644
--- a/src/mainboard/starlabs/starfighter/variants/rpl/gpio.c
+++ b/src/mainboard/starlabs/starfighter/variants/rpl/gpio.c
@@ -8,15 +8,11 @@ const struct pad_config early_gpio_table[] = {
 	PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2),				/* RXD */
 	PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2),				/* TXD */
 
-	/* F12:		Board ID 0					*/
+	/* Board ID */
 	PAD_CFG_GPI_LOCK(GPP_F12, NONE, LOCK_CONFIG),
-	/* F13:		Board ID 1					*/
 	PAD_CFG_GPI_LOCK(GPP_F13, NONE, LOCK_CONFIG),
-	/* F14:		Board ID 2					*/
 	PAD_CFG_GPI_LOCK(GPP_F14, NONE, LOCK_CONFIG),
-	/* F15:		Board ID 3					*/
 	PAD_CFG_GPI_LOCK(GPP_F15, NONE, LOCK_CONFIG),
-
 };
 
 const struct pad_config *variant_early_gpio_table(size_t *num)

From b872c50f9051d09fae71e15c47ed5b2bad63738d Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Wed, 4 Jun 2025 11:45:11 +0100
Subject: [PATCH 1213/3886] mb/starlabs/starfighter: Add generic Graphics
 driver config

This provides entries in the SSDT for all display devices, which
allows the kernel to enumerate them.

Change-Id: Ic6c5578d6995aacfff548d10083a712a0faca622
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87943
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/starlabs/starfighter/Kconfig    |  1 +
 .../starfighter/variants/rpl/devicetree.cb    | 39 +++++++++++++++----
 2 files changed, 33 insertions(+), 7 deletions(-)

diff --git a/src/mainboard/starlabs/starfighter/Kconfig b/src/mainboard/starlabs/starfighter/Kconfig
index 4013bb6e91..19e0161abc 100644
--- a/src/mainboard/starlabs/starfighter/Kconfig
+++ b/src/mainboard/starlabs/starfighter/Kconfig
@@ -5,6 +5,7 @@ config BOARD_STARLABS_STARFIGHTER_SERIES
 	select BOARD_ROMSIZE_KB_32768
 	select DRIVERS_EFI_VARIABLE_STORE
 	select DRIVERS_OPTION_CFR_ENABLED
+	select DRIVERS_GFX_GENERIC
 	select DRIVERS_INTEL_PMC
 	select DRIVERS_INTEL_USB4_RETIMER
 	select DRIVERS_I2C_HID
diff --git a/src/mainboard/starlabs/starfighter/variants/rpl/devicetree.cb b/src/mainboard/starlabs/starfighter/variants/rpl/devicetree.cb
index a73c4f69f2..5074917d38 100644
--- a/src/mainboard/starlabs/starfighter/variants/rpl/devicetree.cb
+++ b/src/mainboard/starlabs/starfighter/variants/rpl/devicetree.cb
@@ -30,11 +30,32 @@ chip soc/intel/alderlake
 
 	device domain 0 on
 		device ref igpu		on
-			register "gfx"				= "GMA_DEFAULT_PANEL(0)"
+			chip drivers/gfx/generic
+				register "device_count"		= "6"
+				# [DDIA] eDP
+				register "device[0].name"	= ""LCD0""
+				register "device[0].type"	= "panel"
+				# [DDIB] HDMI
+				register "device[1].name"	= ""DD01""
+				# [TCP0] Type-C
+				register "device[2].name"	= ""DD02""
+				register "device[2].use_pld"	= "true"
+				register "device[2].pld"	= "ACPI_PLD_TYPE_C(LEFT, CENTER, ACPI_PLD_GROUP(0, 0))"
+				# [TCP1] Type-C
+				register "device[3].name"	= ""DD03""
+				register "device[3].use_pld"	= "true"
+				register "device[3].pld"	= "ACPI_PLD_TYPE_C(LEFT, CENTER, ACPI_PLD_GROUP(0, 1))"
+				# [TCP2] N/A
+				register "device[4].name"	= ""DD04""
+				# [TCP3] N/A
+				register "device[5].name"	= ""DD05""
+				device generic 0 on end
+			end
+
 			register "ddi_portA_config"		= "1"
 			register "ddi_ports_config" = "{
-				[DDI_PORT_A]				= DDI_ENABLE_HPD | DDI_ENABLE_DDC,
-				[DDI_PORT_B]				= DDI_ENABLE_HPD | DDI_ENABLE_DDC,
+				[DDI_PORT_A]			= DDI_ENABLE_HPD | DDI_ENABLE_DDC,
+				[DDI_PORT_B]			= DDI_ENABLE_HPD | DDI_ENABLE_DDC,
 			}"
 		end
 		device ref pcie4_0	on				# SSD x4
@@ -71,13 +92,15 @@ chip soc/intel/alderlake
 					chip drivers/usb/acpi
 						register "desc" = ""Left Back USB Type-C""
 						register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
-						register "group"	= "ACPI_PLD_GROUP(0, 0)"
+						register "use_custom_pld"	= "true"
+						register "custom_pld"		= "ACPI_PLD_TYPE_C(LEFT, CENTER, ACPI_PLD_GROUP(0, 0))"
 						device ref tcss_usb3_port1 on end
 					end
 					chip drivers/usb/acpi
 						register "desc" = ""Left Front USB Type-C""
 						register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
-						register "group"	= "ACPI_PLD_GROUP(0, 1)"
+						register "use_custom_pld"	= "true"
+						register "custom_pld"		= "ACPI_PLD_TYPE_C(LEFT, CENTER, ACPI_PLD_GROUP(0, 1))"
 						device ref tcss_usb3_port2 on end
 					end
 				end
@@ -124,13 +147,15 @@ chip soc/intel/alderlake
 					chip drivers/usb/acpi
 						register "desc"		= ""Left Back USB Type-C""
 						register "type"		= "UPC_TYPE_C_USB2_SS_SWITCH"
-						register "group"	= "ACPI_PLD_GROUP(0, 0)"
+						register "use_custom_pld" = "true"
+						register "custom_pld"	= "ACPI_PLD_TYPE_C(LEFT, CENTER, ACPI_PLD_GROUP(0, 0))"
 						device ref usb2_port1 on end
 					end
 					chip drivers/usb/acpi
 						register "desc"		= ""Left Front USB Type-C""
 						register "type"		= "UPC_TYPE_C_USB2_SS_SWITCH"
-						register "group"	= "ACPI_PLD_GROUP(0, 1)"
+						register "use_custom_pld"	= "true"
+						register "custom_pld"	= "ACPI_PLD_TYPE_C(LEFT, CENTER, ACPI_PLD_GROUP(0, 1))"
 						device ref usb2_port2 on end
 					end
 					chip drivers/usb/acpi

From 902df45eab0b23606b5dd900413165cabf6b9610 Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Wed, 4 Jun 2025 11:49:42 +0100
Subject: [PATCH 1214/3886] mb/starlabs/starfighter: Remove the overcurrent
 config

This is not used, so remove it.

Change-Id: I5d576833c634cc4d2e9eb01627f9bdb61d764b13
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87944
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
---
 src/mainboard/starlabs/starfighter/variants/rpl/devicetree.cb | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/mainboard/starlabs/starfighter/variants/rpl/devicetree.cb b/src/mainboard/starlabs/starfighter/variants/rpl/devicetree.cb
index 5074917d38..7148e7280a 100644
--- a/src/mainboard/starlabs/starfighter/variants/rpl/devicetree.cb
+++ b/src/mainboard/starlabs/starfighter/variants/rpl/devicetree.cb
@@ -129,14 +129,14 @@ chip soc/intel/alderlake
 			register "tcss_ports[1]"		= "TCSS_PORT_DEFAULT(OC_SKIP)"
 
 			# Motherboard USB 3.0 Type-A
-			register "usb2_ports[2]"		= "USB2_PORT_MID(OC0)"
+			register "usb2_ports[2]"		= "USB2_PORT_MID(OC_SKIP)"
 			register "usb3_ports[0]"		= "USB3_PORT_DEFAULT(OC_SKIP)"
 
 			# Removable Webcam
 			register "usb2_ports[4]"		= "USB2_PORT_MID(OC_SKIP)"
 
 			# Daughterboard USB 3.0 Type-A + USB 3.0 Type-A
-			register "usb2_ports[6]"		= "USB2_PORT_MID(OC0)"
+			register "usb2_ports[6]"		= "USB2_PORT_MID(OC_SKIP)"
 			register "usb3_ports[1]"		= "USB3_PORT_DEFAULT(OC_SKIP)"
 
 			# Internal Bluetooth

From 644ebf5ebc867e937f1b30adc250aec032c64ea4 Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Wed, 4 Jun 2025 12:22:06 +0100
Subject: [PATCH 1215/3886] mb/starlabs/starbook/{adl,rpl}: Add generic
 Graphics driver config

This provides entries in the SSDT for all display devices, which
allows the kernel to enumerate them.

Change-Id: Idfa688c3497aa91a9fa5c7923cff04a7ec4892ed
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87947
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/starlabs/starbook/Kconfig       |  2 +-
 .../starbook/variants/adl/devicetree.cb       | 31 +++++++++++++---
 .../starbook/variants/rpl/devicetree.cb       | 37 +++++++++++++++----
 3 files changed, 56 insertions(+), 14 deletions(-)

diff --git a/src/mainboard/starlabs/starbook/Kconfig b/src/mainboard/starlabs/starbook/Kconfig
index a948e45c76..723f10e1de 100644
--- a/src/mainboard/starlabs/starbook/Kconfig
+++ b/src/mainboard/starlabs/starbook/Kconfig
@@ -73,6 +73,7 @@ config BOARD_STARLABS_STARBOOK_ADL_COMMON
 	select EC_STARLABS_MAX_CHARGE
 	select EC_STARLABS_MERLIN
 	select EC_STARLABS_NEED_ITE_BIN
+	select DRIVERS_GFX_GENERIC
 	select MAINBOARD_HAS_TPM2
 	select MEMORY_MAPPED_TPM
 	select PMC_IPC_ACPI_INTERFACE
@@ -90,7 +91,6 @@ config BOARD_STARLABS_STARBOOK_ADL
 config BOARD_STARLABS_STARBOOK_ADL_N
 	select BOARD_ROMSIZE_KB_16384
 	select BOARD_STARLABS_STARBOOK_ADL_COMMON
-	select DRIVERS_GFX_GENERIC
 	select FSP_TYPE_IOT
 	select SOC_INTEL_ALDERLAKE_PCH_N
 
diff --git a/src/mainboard/starlabs/starbook/variants/adl/devicetree.cb b/src/mainboard/starlabs/starbook/variants/adl/devicetree.cb
index c11cc71789..3212ee584a 100644
--- a/src/mainboard/starlabs/starbook/variants/adl/devicetree.cb
+++ b/src/mainboard/starlabs/starbook/variants/adl/devicetree.cb
@@ -29,11 +29,30 @@ chip soc/intel/alderlake
 	# Device Tree
 	device domain 0 on
 		device ref igpu		on
-			register "gfx"				= "GMA_DEFAULT_PANEL(0)"
+			chip drivers/gfx/generic
+				register "device_count"		= "6"
+				# [DDIA] eDP
+				register "device[0].name"	= ""LCD0""
+				register "device[0].type"	= "panel"
+				# [DDIB] HDMI
+				register "device[1].name"	= ""DD01""
+				# [TCP0] Type-C
+				register "device[2].name"	= ""DD02""
+				register "device[2].use_pld"	= "true"
+				register "device[2].pld"	= "ACPI_PLD_TYPE_C(LEFT, CENTER, ACPI_PLD_GROUP(0, 0))"
+				# [TCP1] Type-C
+				register "device[3].name"	= ""DD03""
+				# [TCP2] N/A
+				register "device[4].name"	= ""DD04""
+				# [TCP3] N/A
+				register "device[5].name"	= ""DD05""
+				device generic 0 on end
+			end
+
 			register "ddi_portA_config"		= "1"
 			register "ddi_ports_config" = "{
-				[DDI_PORT_A]				= DDI_ENABLE_HPD | DDI_ENABLE_DDC,
-				[DDI_PORT_B]				= DDI_ENABLE_HPD | DDI_ENABLE_DDC,
+				[DDI_PORT_A]			= DDI_ENABLE_HPD | DDI_ENABLE_DDC,
+				[DDI_PORT_B]			= DDI_ENABLE_HPD | DDI_ENABLE_DDC,
 			}"
 		end
 		device ref gna		on  end
@@ -67,13 +86,15 @@ chip soc/intel/alderlake
 					chip drivers/usb/acpi
 						register "desc"		= ""USB Type-C""
 						register "type"		= "UPC_TYPE_C_USB2_SS_SWITCH"
-						register "group"	= "ACPI_PLD_GROUP(0, 0)"
+						register "use_custom_pld" = "true"
+						register "custom_pld"	= "ACPI_PLD_TYPE_C(LEFT, CENTER, ACPI_PLD_GROUP(0, 0))"
 						device ref usb2_port1 on end
 					end
 					chip drivers/usb/acpi
 						register "desc"		= ""USB Type-C""
 						register "type"		= "UPC_TYPE_C_USB2_SS_SWITCH"
-						register "group"	= "ACPI_PLD_GROUP(0, 0)"
+						register "use_custom_pld" = "true"
+						register "custom_pld"	= "ACPI_PLD_TYPE_C(LEFT, CENTER, ACPI_PLD_GROUP(0, 0))"
 						device ref usb3_port3 on end
 					end
 					chip drivers/usb/acpi
diff --git a/src/mainboard/starlabs/starbook/variants/rpl/devicetree.cb b/src/mainboard/starlabs/starbook/variants/rpl/devicetree.cb
index 645bd5009e..7637af896b 100644
--- a/src/mainboard/starlabs/starbook/variants/rpl/devicetree.cb
+++ b/src/mainboard/starlabs/starbook/variants/rpl/devicetree.cb
@@ -31,11 +31,30 @@ chip soc/intel/alderlake
 	# Device Tree
 	device domain 0 on
 		device ref igpu		on
-			register "gfx"					= "GMA_DEFAULT_PANEL(0)"
-			register "ddi_portA_config"			= "1"
+			chip drivers/gfx/generic
+				register "device_count"		= "6"
+				# [DDIA] eDP
+				register "device[0].name"	= ""LCD0""
+				register "device[0].type"	= "panel"
+				# [DDIB] HDMI
+				register "device[1].name"	= ""DD01""
+				# [TCP0] Type-C
+				register "device[2].name"	= ""DD02""
+				register "device[2].use_pld"	= "true"
+				register "device[2].pld"	= "ACPI_PLD_TYPE_C(LEFT, CENTER, ACPI_PLD_GROUP(0, 0))"
+				# [TCP1] Type-C
+				register "device[3].name"	= ""DD03""
+				# [TCP2] N/A
+				register "device[4].name"	= ""DD04""
+				# [TCP3] N/A
+				register "device[5].name"	= ""DD05""
+				device generic 0 on end
+			end
+
+			register "ddi_portA_config"		= "1"
 			register "ddi_ports_config" = "{
-				[DDI_PORT_A]				= DDI_ENABLE_HPD | DDI_ENABLE_DDC,
-				[DDI_PORT_B]				= DDI_ENABLE_HPD | DDI_ENABLE_DDC,
+				[DDI_PORT_A]			= DDI_ENABLE_HPD | DDI_ENABLE_DDC,
+				[DDI_PORT_B]			= DDI_ENABLE_HPD | DDI_ENABLE_DDC,
 			}"
 		end
 		device ref pcie4_0	on				# SSD x4
@@ -68,9 +87,10 @@ chip soc/intel/alderlake
 			chip drivers/usb/acpi
 				device ref tcss_root_hub on
 					chip drivers/usb/acpi
-						register "desc"		= ""USB Type-C""
-						register "type"		= "UPC_TYPE_C_USB2_SS_SWITCH"
-						register "group"	= "ACPI_PLD_GROUP(0, 0)"
+						register "desc"			= ""USB Type-C""
+						register "type"			= "UPC_TYPE_C_USB2_SS_SWITCH"
+						register "use_custom_pld"	= "true"
+						register "custom_pld"		= "ACPI_PLD_TYPE_C(LEFT, CENTER, ACPI_PLD_GROUP(0, 0))"
 						device ref tcss_usb3_port1 on end
 					end
 				end
@@ -114,7 +134,8 @@ chip soc/intel/alderlake
 					chip drivers/usb/acpi
 						register "desc"		= ""USB Type-C""
 						register "type"		= "UPC_TYPE_C_USB2_SS_SWITCH"
-						register "group"	= "ACPI_PLD_GROUP(0, 0)"
+						register "use_custom_pld" = "true"
+						register "custom_pld"	= "ACPI_PLD_TYPE_C(LEFT, CENTER, ACPI_PLD_GROUP(0, 0))"
 						device ref usb2_port1 on end
 					end
 					chip drivers/usb/acpi

From a9a51f991624e20e3d440e6951f3cef2188f7714 Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Wed, 4 Jun 2025 12:24:09 +0100
Subject: [PATCH 1216/3886] mb/starlabs/starfighter: Add missing ASPM config
 for the SSD

Change-Id: I66694cf0594a2e684fbdbc7c25cbeb984a553c43
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87948
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/starlabs/starfighter/variants/rpl/devicetree.cb | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/src/mainboard/starlabs/starfighter/variants/rpl/devicetree.cb b/src/mainboard/starlabs/starfighter/variants/rpl/devicetree.cb
index 7148e7280a..57a73276a1 100644
--- a/src/mainboard/starlabs/starfighter/variants/rpl/devicetree.cb
+++ b/src/mainboard/starlabs/starfighter/variants/rpl/devicetree.cb
@@ -241,6 +241,8 @@ chip soc/intel/alderlake
 				.clk_src				= 1,
 				.clk_req				= 1,
 				.flags					= PCIE_RP_LTR | PCIE_RP_AER,
+				.pcie_rp_aspm				= ASPM_L0S_L1,
+				.PcieRpL1Substates			= L1_SS_L1_2,
 				.pcie_rp_detect_timeout_ms		= 50,
 			}"
 

From 45febdec26b1a3506404f433a6fd3aeb6c69baf5 Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Wed, 4 Jun 2025 12:28:39 +0100
Subject: [PATCH 1217/3886] mb/starlabs/starfighter: Add reset GPIO for the USB
 Bluetooth

Change-Id: Ie68713f12830275b5e07efb230af74c277185f54
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87950
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/starlabs/starfighter/variants/rpl/devicetree.cb | 1 +
 1 file changed, 1 insertion(+)

diff --git a/src/mainboard/starlabs/starfighter/variants/rpl/devicetree.cb b/src/mainboard/starlabs/starfighter/variants/rpl/devicetree.cb
index 57a73276a1..a9221cae48 100644
--- a/src/mainboard/starlabs/starfighter/variants/rpl/devicetree.cb
+++ b/src/mainboard/starlabs/starfighter/variants/rpl/devicetree.cb
@@ -193,6 +193,7 @@ chip soc/intel/alderlake
 						register "group"	= "ACPI_PLD_GROUP(0, 5)"
 						register "is_intel_bluetooth" = "1"
 						register "enable_gpio"	= "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A13)"
+						register "reset_gpio"	= "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A13)"
 						device ref usb2_port10 on end
 					end
 				end

From bf330f2dd0d961db4de087fe6b773b44b0fe12dd Mon Sep 17 00:00:00 2001
From: Wonkyu Kim <wonkyu.kim@intel.com>
Date: Fri, 16 May 2025 01:39:36 -0700
Subject: [PATCH 1218/3886] security/vboot: Back up CMOS data later boot phase

Introduce POSTPONE_SPI_ACCESS to save CMOS data in a later boot phase
to avoid flash access delay by other boot controllers.

Intel has pre-CPU boot controllers (e.g. CSE) which load non-CPU
firmwares. Boot-critical firmwares are loaded before CPU reset and
non-boot-critical firmwares are loaded during CPU boot. If another
controller accesses SPI to load firmwares, reading SPI by CPU is ok,
but writing to SPI for saving CMOS data can take ~30ms sometimes.
Saving CMOS data usually takes less than 1ms.


Before this change, sometimes it delays like below:
BS: callback (0x7386f908) @ src/security/vboot/vbnv_cmos.c:122 (32 ms)
After this change, the delay is less than 1 ms:
BS: callback (0x7386f908) @ src/security/vboot/vbnv_cmos.c:122 (0 ms)

TEST
1. Enable DEBUG_BOOT_STATE
2. Check time
BS: callback (0x7386f908) @ src/security/vboot/vbnv_cmos.c:120 (0 ms)

Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com>
Change-Id: I8836c14601beb56c614605b9840c8506d6d8536c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87738
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/Kconfig                    | 9 +++++++++
 src/security/vboot/vbnv_cmos.c | 5 +++++
 2 files changed, 14 insertions(+)

diff --git a/src/Kconfig b/src/Kconfig
index 58c2e07ea9..1a49a8ba55 100644
--- a/src/Kconfig
+++ b/src/Kconfig
@@ -1563,3 +1563,12 @@ config HAVE_RAMSTAGE
 
 config SEPARATE_ROMSTAGE
 	default y
+
+config POSTPONE_SPI_ACCESS
+	bool
+	help
+	  Enable this option to postpone SPI access to later boot phase
+	  (BS_PAYLOAD_BOOT) to prevent flash write access delays caused by
+	  simultaneous accesses from other SPI masters like CSE. This symptom
+	  was found in Intel SoCs (Panther Lake and Wildcat Lake) but it can be
+	  used other SOCs.
diff --git a/src/security/vboot/vbnv_cmos.c b/src/security/vboot/vbnv_cmos.c
index 5073509fc9..916e1ca03e 100644
--- a/src/security/vboot/vbnv_cmos.c
+++ b/src/security/vboot/vbnv_cmos.c
@@ -115,5 +115,10 @@ static void back_up_vbnv_cmos(void *unused)
 	/* Save to flash, will only be saved if different. */
 	save_vbnv_flash(vbnv_cmos);
 }
+
+#if CONFIG(POSTPONE_SPI_ACCESS)
+BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_LOAD, BS_ON_EXIT, back_up_vbnv_cmos, NULL);
+#else
 BOOT_STATE_INIT_ENTRY(BS_POST_DEVICE, BS_ON_EXIT, back_up_vbnv_cmos, NULL);
 #endif
+#endif

From 359ae676686bae6d7eae127ac5a769906ba7e50c Mon Sep 17 00:00:00 2001
From: Wonkyu Kim <wonkyu.kim@intel.com>
Date: Fri, 16 May 2025 01:46:58 -0700
Subject: [PATCH 1219/3886] elog: Handle elog in later boot phase

Use POSTPONE_SPI_ACCESS to handle elog data later boot phase to avoid
flash access delay by other boot controllers.

Intel has pre-CPU boot controllers (e.g. CSE) which load non-CPU
firmwares. Boot-critical firmwares are loaded before CPU reset and
non-boot-critical firmwares are loaded during CPU boot. If another
controller accesses SPI to load firmwares, reading SPI by CPU is ok,
but writing to SPI for saving elog data can take ~32ms sometimes.
Saving elog data usually takes less than 1ms.

There are three elog handling sequences that need to move together
under the Kconfig:
- Soc folder
- Elog driver folder
- ChromeOS folder

Before this change, sometimes it delays like below:
BS: callback (0x7386d428) @ src/soc/intel/pantherlake/elog.c:216 (32 ms)
After this change, the delay is less than 1 ms:
BS: callback (0x7386d3e8) @ src/soc/intel/pantherlake/elog.c:213 (0 ms)

TEST
1. Enable DEBUG_BOOT_STATE
2. Check time
BS: callback (0x7386d3e8) @ src/soc/intel/pantherlake/elog.c:213 (0 ms))

Change-Id: I3f5e7acf5204e213179664d0d77151d415d00896
Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87740
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
---
 src/drivers/elog/elog.c               | 5 +++++
 src/soc/intel/pantherlake/elog.c      | 4 ++++
 src/vendorcode/google/chromeos/elog.c | 4 ++++
 3 files changed, 13 insertions(+)

diff --git a/src/drivers/elog/elog.c b/src/drivers/elog/elog.c
index ecee145e31..54674ce9fb 100644
--- a/src/drivers/elog/elog.c
+++ b/src/drivers/elog/elog.c
@@ -898,4 +898,9 @@ int elog_add_extended_event(u8 type, u32 complement)
 
 /* Make sure elog_init() runs at least once to log System Boot event. */
 static void elog_bs_init(void *unused) { elog_init(); }
+
+#if CONFIG(POSTPONE_SPI_ACCESS)
+BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_LOAD, BS_ON_EXIT, elog_bs_init, NULL);
+#else
 BOOT_STATE_INIT_ENTRY(BS_POST_DEVICE, BS_ON_ENTRY, elog_bs_init, NULL);
+#endif
diff --git a/src/soc/intel/pantherlake/elog.c b/src/soc/intel/pantherlake/elog.c
index 5abf766fc7..e5a6a9a3cf 100644
--- a/src/soc/intel/pantherlake/elog.c
+++ b/src/soc/intel/pantherlake/elog.c
@@ -210,7 +210,11 @@ static void pch_log_state(void *unused)
 		pch_log_wake_source(ps);
 }
 
+#if CONFIG(POSTPONE_SPI_ACCESS)
+BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_LOAD, BS_ON_ENTRY, pch_log_state, NULL);
+#else
 BOOT_STATE_INIT_ENTRY(BS_DEV_INIT, BS_ON_EXIT, pch_log_state, NULL);
+#endif
 
 void elog_gsmi_cb_platform_log_wake_source(void)
 {
diff --git a/src/vendorcode/google/chromeos/elog.c b/src/vendorcode/google/chromeos/elog.c
index e60cec83b0..5dabb3cf7f 100644
--- a/src/vendorcode/google/chromeos/elog.c
+++ b/src/vendorcode/google/chromeos/elog.c
@@ -31,4 +31,8 @@ static void elog_add_vboot_info(void *unused)
 	elog_add_event_raw(ELOG_TYPE_FW_VBOOT_INFO, &data, width);
 }
 
+#if CONFIG(POSTPONE_SPI_ACCESS)
+BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_LOAD, BS_ON_EXIT, elog_add_vboot_info, NULL);
+#else
 BOOT_STATE_INIT_ENTRY(BS_POST_DEVICE, BS_ON_ENTRY, elog_add_vboot_info, NULL);
+#endif

From a1738e87b5d029e1002448dd833f3d06ceb78f2f Mon Sep 17 00:00:00 2001
From: Wonkyu Kim <wonkyu.kim@intel.com>
Date: Mon, 19 May 2025 00:12:02 -0700
Subject: [PATCH 1220/3886] soc/intel/panterlake: avoid SPI access delay

Enable POSTPONE_SPI_ACCESS to back up CMOS data and ELOG data in the
later boot phase to avoid flash access delay by another boot controller.

TEST=
1. Enable DEBUG_BOOT_STATE
2. Check time
BS: callback (0x7386f908) @ src/security/vboot/vbnv_cmos.c:120 (0 ms)
BS: callback (0x7386d3e8) @ src/soc/intel/pantherlake/elog.c:213 (0 ms)

Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com>
Change-Id: I6b1b091dc60e6b20d39b90feebc8309306d6493e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87739
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
---
 src/soc/intel/pantherlake/Kconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/src/soc/intel/pantherlake/Kconfig b/src/soc/intel/pantherlake/Kconfig
index c4b8e011bb..452591667b 100644
--- a/src/soc/intel/pantherlake/Kconfig
+++ b/src/soc/intel/pantherlake/Kconfig
@@ -13,6 +13,7 @@ config SOC_INTEL_PANTHERLAKE_BASE
 	select CPU_SUPPORTS_PM_TIMER_EMULATION
 	select DEFAULT_SOFTWARE_CONNECTION_MANAGER if MAINBOARD_HAS_CHROMEOS
 	select DEFAULT_X2APIC_LATE_WORKAROUND
+	select POSTPONE_SPI_ACCESS
 	select DISPLAY_FSP_VERSION_INFO_2
 	select DRIVERS_USB_ACPI
 	select FAST_SPI_SUPPORTS_EXT_BIOS_WINDOW

From 033810a7dbad39bd8236beb0c6edb51a8aea6006 Mon Sep 17 00:00:00 2001
From: NyeonWoo Kim <knw0507@naver.com>
Date: Sat, 31 May 2025 18:09:22 +0900
Subject: [PATCH 1221/3886] payloads/libpayload/Makefile.mk: Replace nm with
 $(NM)

I got 'nm' usage error when i built coreinfo payload.
	nm: unrecognized option '--no-weak'

it seems that this is occurred by using nm for host, not for coreboot.

So, I replace nm with $(NM)

Change-Id: I0a0a04b351c9131b1238e8cc7e63e396820494d9
Signed-off-by: NyeonWoo Kim <knw0507@naver.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87906
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
---
 payloads/libpayload/Makefile.mk | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/payloads/libpayload/Makefile.mk b/payloads/libpayload/Makefile.mk
index 8c6b28767c..08249c2648 100644
--- a/payloads/libpayload/Makefile.mk
+++ b/payloads/libpayload/Makefile.mk
@@ -110,8 +110,8 @@ includes-handler= \
 $(obj)/libpayload.a: $(foreach class,$(libraries),$$($(class)-objs))
 	printf "    AR         $(subst $(CURDIR)/,,$(@))\n"
 	printf "create $@\n$(foreach objc,$(filter-out %.a,$^),addmod $(objc)\n)$(foreach lib,$(filter %.a,$^),addlib $(lib)\n)save\nend\n" | $(AR) -M
-	for func in $$(nm $@ | awk '/ (w|W) / { print $$NF }'); do \
-		if nm --no-weak --defined-only $@ | grep -Eq " $$func$$"; then \
+	for func in $$($(NM) $@ | awk '/ (w|W) / { print $$NF }'); do \
+		if $(NM) --no-weak --defined-only $@ | grep -Eq " $$func$$"; then \
 			printf "\nERROR: Function '$$func' appears as both weak and strong symbol in libpayload.\n"; \
 			printf "       Weak symbol overrides don't work reliably from within the same library.\n\n"; \
 			rm $@; \

From 99e5a386c23241b8859c5503c861c15e3a6804cf Mon Sep 17 00:00:00 2001
From: Patrick Rudolph <patrick.rudolph@9elements.com>
Date: Tue, 18 Feb 2025 15:11:16 +0100
Subject: [PATCH 1222/3886] mb/amd/birman_plus/glinda: Add onboard devices

Add SD Express and GBE PCIe devices.

Change-Id: Ia589f115fc5c16540daa6210e2624572767ad12e
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86496
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
---
 src/mainboard/amd/birman_plus/devicetree_glinda.cb | 8 ++++++--
 1 file changed, 6 insertions(+), 2 deletions(-)

diff --git a/src/mainboard/amd/birman_plus/devicetree_glinda.cb b/src/mainboard/amd/birman_plus/devicetree_glinda.cb
index 07642aa557..5a7dd163f4 100644
--- a/src/mainboard/amd/birman_plus/devicetree_glinda.cb
+++ b/src/mainboard/amd/birman_plus/devicetree_glinda.cb
@@ -187,9 +187,13 @@ chip soc/amd/glinda
 	device domain 0 on
 		device ref iommu on end
 		device ref gpp_bridge_2_1 on end # NVME SSD0
-		device ref gpp_bridge_2_2 on end # SD
+		device ref gpp_bridge_2_2 on # SD Express
+			device pci 0.0 on end # RTS5261
+		end
 		device ref gpp_bridge_2_3 on end # WLAN
-		device ref gpp_bridge_2_4 on end # GBE
+		device ref gpp_bridge_2_4 on # GBE
+			device pci 0.0 on end # RTL8111
+		end
 		device ref gpp_bridge_2_5 on end # WWAN
 		device ref gpp_bridge_3_1 on end # PCIe x4/x8 (ENABLE_SSD1_BIRMANPLUS)
 		device ref gpp_bridge_3_2 on end # NVME SSD1 (ENABLE_SSD1_BIRMANPLUS)

From c24a12db860f33cee2a8ff4c7fd66af3775fba5d Mon Sep 17 00:00:00 2001
From: Jakub Czapiga <czapiga@google.com>
Date: Wed, 12 Feb 2025 16:46:08 +0000
Subject: [PATCH 1223/3886] util/cbmem: Consolidate CBMEM and coreboot table
 access

Provide common functions for accessing CBMEM and coreboot table entries
instead of mapping them manually in each function. New functions return
a copy of requested region as a heap-allocated buffer thus avoiding a
need for aligned memory access.
Remove global variables wherever possible to make code easier to read
and to isolate responsibilities of functions.
Use CBMEM entries instead of coreboot table records directly, but
provide fallback for old systems in case the correcponding CBMEM entry
does not exist.

BUG=b:391874512
TEST=cbmem -l; cbmem -x; cbmem -r 434f4e53; cbmem -t; cbmem -a 1200

Change-Id: I89b371e27ab3840cfbbd44880c32383b77f65e5c
Signed-off-by: Jakub Czapiga <czapiga@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87417
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
---
 util/cbmem/cbmem.c | 683 +++++++++++++++++++++++----------------------
 1 file changed, 353 insertions(+), 330 deletions(-)

diff --git a/util/cbmem/cbmem.c b/util/cbmem/cbmem.c
index bdb6794dbf..9fc4060302 100644
--- a/util/cbmem/cbmem.c
+++ b/util/cbmem/cbmem.c
@@ -35,9 +35,6 @@
 #include <x86intrin.h>
 #endif
 
-/* Return < 0 on error, 0 on success. */
-static int parse_cbtable(uint64_t address, size_t table_size);
-
 struct mapping {
 	void *virt;
 	size_t offset;
@@ -56,9 +53,6 @@ static int verbose = 0;
 static int mem_fd;
 static struct mapping lbtable_mapping;
 
-/* TSC frequency from the LB_TAG_TSC_INFO record. 0 if not present. */
-static uint32_t tsc_freq_khz = 0;
-
 static void die(const char *msg)
 {
 	if (msg)
@@ -195,57 +189,6 @@ static void *aligned_memcpy(void *dest, const void *src, size_t n)
 	return dest;
 }
 
-/* Find the first cbmem entry filling in the details. */
-static int find_cbmem_entry(uint32_t id, uint64_t *addr, size_t *size)
-{
-	const uint8_t *table;
-	size_t offset;
-	int ret = -1;
-
-	table = mapping_virt(&lbtable_mapping);
-
-	if (table == NULL)
-		return -1;
-
-	offset = 0;
-
-	while (offset < mapping_size(&lbtable_mapping)) {
-		const struct lb_record *lbr;
-		struct lb_cbmem_entry lbe;
-
-		lbr = (const void *)(table + offset);
-		offset += lbr->size;
-
-		if (lbr->tag != LB_TAG_CBMEM_ENTRY)
-			continue;
-
-		aligned_memcpy(&lbe, lbr, sizeof(lbe));
-		if (lbe.id != id)
-			continue;
-
-		*addr = lbe.address;
-		*size = lbe.entry_size;
-		ret = 0;
-		break;
-	}
-
-	return ret;
-}
-
-/*
- * Try finding the timestamp table and coreboot cbmem console starting from the
- * passed in memory offset.  Could be called recursively in case a forwarding
- * entry is found.
- *
- * Returns pointer to a memory buffer containing the timestamp table or zero if
- * none found.
- */
-
-static struct lb_cbmem_ref timestamps;
-static struct lb_cbmem_ref console;
-static struct lb_cbmem_ref tpm_cb_log;
-static struct lb_memory_range cbmem;
-
 /* This is a work-around for a nasty problem introduced by initially having
  * pointer sized entries in the lb_cbmem_ref structures. This caused problems
  * on 64bit x86 systems because coreboot is 32bit on those systems.
@@ -267,90 +210,168 @@ static struct lb_cbmem_ref parse_cbmem_ref(const struct lb_cbmem_ref *cbmem_ref)
 	return ret;
 }
 
-static void parse_memory_tags(const struct lb_memory *mem)
+static uint32_t cbmem_id_to_lb_tag(uint32_t tag)
 {
-	int num_entries;
-	int i;
-
-	/* Peel off the header size and calculate the number of entries. */
-	num_entries = (mem->size - sizeof(*mem)) / sizeof(mem->map[0]);
-
-	for (i = 0; i < num_entries; i++) {
-		if (mem->map[i].type != LB_MEM_TABLE)
-			continue;
-		debug("      LB_MEM_TABLE found.\n");
-		/* The last one found is CBMEM */
-		aligned_memcpy(&cbmem, &mem->map[i], sizeof(cbmem));
+	/* Minimal subset. Expand based on the CBMEM to coreboot table
+	   records mapping in lib/coreboot_table.c */
+	switch (tag) {
+	case CBMEM_ID_TIMESTAMP:
+		return LB_TAG_TIMESTAMPS;
+	case CBMEM_ID_CONSOLE:
+		return LB_TAG_CBMEM_CONSOLE;
+	case CBMEM_ID_TPM_CB_LOG:
+		return LB_TAG_TPM_CB_LOG;
 	}
+	return LB_TAG_UNUSED;
 }
 
-/* Return < 0 on error, 0 on success, 1 if forwarding table entry found. */
-static int parse_cbtable_entries(const struct mapping *table_mapping)
+struct cbmem_console {
+	uint32_t size;
+	uint32_t cursor;
+	uint8_t body[];
+} __packed;
+
+#define CBMC_CURSOR_MASK ((1 << 28) - 1)
+#define CBMC_OVERFLOW    (1 << 31)
+
+
+/* Find the first cbmem entry filling in the details. */
+static int find_cbmem_entry(uint32_t id, uint64_t *addr, size_t *size)
 {
-	size_t i;
-	const struct lb_record *lbr_p;
-	size_t table_size = mapping_size(table_mapping);
-	const void *lbtable = mapping_virt(table_mapping);
-	int forwarding_table_found = 0;
+	const uint8_t *table;
+	size_t offset = 0;
+	const uint32_t legacy_tag = cbmem_id_to_lb_tag(id);
+	struct lb_cbmem_ref *ref = NULL;
 
-	for (i = 0; i < table_size; i += lbr_p->size) {
-		lbr_p = lbtable + i;
-		debug("  coreboot table entry 0x%02x\n", lbr_p->tag);
-		switch (lbr_p->tag) {
-		case LB_TAG_MEMORY:
-			debug("    Found memory map.\n");
-			parse_memory_tags(lbtable + i);
-			continue;
-		case LB_TAG_TIMESTAMPS: {
-			debug("    Found timestamp table.\n");
-			timestamps =
-			    parse_cbmem_ref((struct lb_cbmem_ref *)lbr_p);
-			continue;
-		}
-		case LB_TAG_CBMEM_CONSOLE: {
-			debug("    Found cbmem console.\n");
-			console = parse_cbmem_ref((struct lb_cbmem_ref *)lbr_p);
-			continue;
-		}
-		case LB_TAG_TPM_CB_LOG: {
-			debug("    Found TPM CB log table.\n");
-			tpm_cb_log =
-			    parse_cbmem_ref((struct lb_cbmem_ref *)lbr_p);
-			continue;
-		}
-		case LB_TAG_TSC_INFO:
-			debug("    Found TSC info.\n");
-			tsc_freq_khz = ((struct lb_tsc_info *)lbr_p)->freq_khz;
-			continue;
-		case LB_TAG_FORWARD: {
-			int ret;
-			/*
-			 * This is a forwarding entry - repeat the
-			 * search at the new address.
-			 */
-			struct lb_forward lbf_p =
-			    *(const struct lb_forward *)lbr_p;
-			debug("    Found forwarding entry.\n");
-			ret = parse_cbtable(lbf_p.forward, 0);
+	table = mapping_virt(&lbtable_mapping);
 
-			/* Assume the forwarding entry is valid. If this fails
-			 * then there's a total failure. */
-			if (ret < 0)
-				return -1;
-			forwarding_table_found = 1;
-		}
-		default:
-			break;
-		}
+	if (table == NULL)
+		return -1;
+
+	const struct lb_record *lbr = NULL;
+	while (offset < mapping_size(&lbtable_mapping)) {
+		lbr = (const void *)(table + offset);
+		offset += lbr->size;
+
+		/* Store coreboot table entry for later if CBMEM entry does not exist.
+		   CBMEM entry stores size including the reserved area, so prefer it,
+		   so more potential data and/or space is available. */
+		if (legacy_tag != LB_TAG_UNUSED && lbr->tag == legacy_tag)
+			ref = (struct lb_cbmem_ref *)lbr;
+
+		if (lbr->tag != LB_TAG_CBMEM_ENTRY)
+			continue;
+
+		struct lb_cbmem_entry lbe;
+		aligned_memcpy(&lbe, lbr, sizeof(lbe));
+		if (lbe.id != id)
+			continue;
+
+		*addr = lbe.address;
+		*size = lbe.entry_size;
+		return 0;
 	}
 
-	return forwarding_table_found;
+	/* No mapping and/or no potential reference means that
+	   the requested entry does not exit. */
+	if (legacy_tag == LB_TAG_UNUSED || ref == NULL)
+		return -1;
+
+	debug("Found coreboot table record equivalent of CBMEM entry id: %#x, tag: %#x\n", id,
+	      legacy_tag);
+
+	const struct lb_cbmem_ref lbc = parse_cbmem_ref(ref);
+	size_t header_map_size = 0;
+
+	/* Process legacy coreboot table entries */
+	switch (lbc.tag) {
+	case LB_TAG_TIMESTAMPS:
+		header_map_size = sizeof(struct timestamp_table);
+		break;
+	case LB_TAG_CBMEM_CONSOLE:
+		header_map_size = sizeof(struct cbmem_console);
+		break;
+	case LB_TAG_TPM_CB_LOG:
+		header_map_size = sizeof(struct tpm_cb_log_table);
+		break;
+	}
+
+	struct mapping entry_mapping;
+	const void *entry_header = NULL;
+
+	entry_header = map_memory(&entry_mapping, lbc.cbmem_addr, header_map_size);
+	if (!entry_header) {
+		fprintf(stderr, "Unable to map header for coreboot table entry id: %#x\n",
+			legacy_tag);
+		abort();
+	}
+
+	*addr = lbc.cbmem_addr;
+
+	switch (legacy_tag) {
+	case LB_TAG_TIMESTAMPS: {
+		const struct timestamp_table *tst_p = entry_header;
+		*size = sizeof(*tst_p) + tst_p->num_entries * sizeof(tst_p->entries[0]);
+		break;
+	}
+	case LB_TAG_CBMEM_CONSOLE: {
+		const struct cbmem_console *console_p = entry_header;
+		*size = sizeof(*console_p) + console_p->size;
+		break;
+	}
+	case LB_TAG_TPM_CB_LOG: {
+		const struct tpm_cb_log_table *tclt_p = entry_header;
+		*size = sizeof(*tclt_p) + tclt_p->num_entries * sizeof(tclt_p->entries[0]);
+		break;
+	}
+	}
+
+	unmap_memory(&entry_mapping);
+
+	return 0;
+}
+
+/**
+ * Returns pointer to allocated buffer and size of the buffer in parameters.
+ * Returns zero on success.
+ * free() buffer after use.
+ */
+static int get_cbmem_entry(uint32_t id, uint8_t **buf_out, size_t *size_out)
+{
+	uint64_t addr;
+	size_t size;
+	struct mapping cbmem_mapping;
+
+	if (find_cbmem_entry(id, &addr, &size)) {
+		debug("CBMEM entry not found. CBMEM id: %#x\n", id);
+		return -1;
+	}
+
+	const uint8_t *buf = map_memory(&cbmem_mapping, addr, size);
+	if (!buf) {
+		fprintf(stderr, "Unable to map CBMEM entry id: %#x, size: %zu\n", id, size);
+		abort();
+	}
+
+	*buf_out = malloc(size);
+	if (!*buf_out) {
+		unmap_memory(&cbmem_mapping);
+		fprintf(stderr,
+			"Unable to allocate memory for CBMEM entry id: %#x, size: %zu\n", id,
+			size);
+		abort();
+	}
+
+	aligned_memcpy(*buf_out, buf, size);
+	unmap_memory(&cbmem_mapping);
+	*size_out = size;
+	return 0;
 }
 
 /* Return < 0 on error, 0 on success. */
 static int parse_cbtable(uint64_t address, size_t table_size)
 {
-	const void *buf;
+	const uint8_t *buf;
 	struct mapping header_mapping;
 	size_t req_size;
 	size_t i;
@@ -360,8 +381,7 @@ static int parse_cbtable(uint64_t address, size_t table_size)
 	if (req_size == 0)
 		req_size = 4 * 1024;
 
-	debug("Looking for coreboot table at %" PRIx64 " %zd bytes.\n",
-		address, req_size);
+	debug("Looking for coreboot table at %" PRIx64 " %zd bytes.\n", address, req_size);
 
 	buf = map_memory(&header_mapping, address, req_size);
 
@@ -370,11 +390,10 @@ static int parse_cbtable(uint64_t address, size_t table_size)
 
 	/* look at every 16 bytes */
 	for (i = 0; i <= req_size - sizeof(struct lb_header); i += 16) {
-		int ret;
 		const struct lb_header *lbh;
 		struct mapping table_mapping;
 
-		lbh = buf + i;
+		lbh = (const struct lb_header *)&buf[i];
 		if (memcmp(lbh->signature, "LBIO", sizeof(lbh->signature)) ||
 		    !lbh->header_bytes ||
 		    ipchksum(lbh, sizeof(*lbh))) {
@@ -395,27 +414,32 @@ static int parse_cbtable(uint64_t address, size_t table_size)
 			continue;
 		}
 
-		debug("Found!\n");
+		debug("Found at %#lx\n", address + i);
 
-		ret = parse_cbtable_entries(&table_mapping);
+		const struct lb_record *lbr_p;
+		const uint8_t *lbtable = mapping_virt(&table_mapping);
 
-		/* Table parsing failed. */
-		if (ret < 0) {
+		for (size_t offset = 0; offset < lbh->table_bytes; offset += lbr_p->size) {
+			lbr_p = (const struct lb_record *)&lbtable[offset];
+			debug("  coreboot table entry 0x%02x\n", lbr_p->tag);
+
+			if (lbr_p->tag != LB_TAG_FORWARD)
+				continue;
+
+			/* This is a forwarding entry. Repeat the search at the new address. */
+			struct lb_forward lbf_p = *(const struct lb_forward *)lbr_p;
+			debug("    Found forwarding entry.\n");
+
+			const uint64_t next_addr = lbf_p.forward;
+			unmap_memory(&header_mapping);
 			unmap_memory(&table_mapping);
-			continue;
+
+			return parse_cbtable(next_addr, 0);
 		}
 
-		/* Succeeded in parsing the table. Header not needed anymore. */
+		debug("correct coreboot table found.\n");
 		unmap_memory(&header_mapping);
-
-		/*
-		 * Table parsing succeeded. If forwarding table not found update
-		 * coreboot table mapping for future use.
-		 */
-		if (ret == 0)
-			lbtable_mapping = table_mapping;
-		else
-			unmap_memory(&table_mapping);
+		lbtable_mapping = table_mapping;
 
 		return 0;
 	}
@@ -425,6 +449,78 @@ static int parse_cbtable(uint64_t address, size_t table_size)
 	return -1;
 }
 
+static void lb_table_get_entry(uint32_t tag, uint8_t **buf_out, size_t *size_out)
+{
+	const struct lb_record *lbr_p;
+	const uint8_t *lbtable_raw;
+	size_t table_size;
+	bool tag_found = false;
+
+	if (get_cbmem_entry(CBMEM_ID_CBTABLE, (uint8_t **)&lbtable_raw, &table_size)) {
+		fprintf(stderr, "coreboot table not found.\n");
+		abort();
+	}
+
+	const struct lb_header *lbh = (const struct lb_header *)lbtable_raw;
+
+	for (size_t i = 0; i < lbh->table_bytes; i += lbr_p->size) {
+		lbr_p = (const struct lb_record *)(&lbtable_raw[lbh->header_bytes + i]);
+		if (lbr_p->tag == tag) {
+			tag_found = true;
+			break;
+		}
+	}
+
+	if (!tag_found) {
+		fprintf(stderr, "coreboot table entry %#x not found.\n", tag);
+		free((void *)lbtable_raw);
+		abort();
+	}
+
+	debug("coreboot table entry %#x found.\n", tag);
+
+	*buf_out = malloc(lbr_p->size);
+	if (!*buf_out) {
+		fprintf(stderr,
+			"Unable to allocate memory for coreboot table entry %#x, size: %d\n",
+			tag, lbr_p->size);
+		free((void *)lbtable_raw);
+		abort();
+	}
+	memcpy(*buf_out, lbr_p, lbr_p->size);
+	*size_out = lbr_p->size;
+	free((void *)lbtable_raw);
+}
+
+
+/**
+ * Returns mapping, mapped buffer pointer and its size by parameters.
+ * Returns zero on success.
+ * unmap_mempry() after use.
+ */
+static int map_cbmem_entry_rw(uint32_t id, struct mapping *mapping, uint8_t **buf_out,
+			       size_t *size_out)
+{
+	uint64_t addr;
+	size_t size;
+
+	if (find_cbmem_entry(id, &addr, &size)) {
+		debug("CBMEM entry not found. CBMEM id: %#x\n", id);
+		return -1;
+	}
+
+	*buf_out = map_memory_with_prot(mapping, addr, size, PROT_READ | PROT_WRITE);
+	if (!*buf_out) {
+		fprintf(stderr,
+			"Unable to map CBMEM entry id: %#x, size: %zu for read-write access.\n",
+			id, size);
+		abort();
+	}
+
+	*size_out = size;
+	return 0;
+}
+
 #if defined(linux) && (defined(__i386__) || defined(__x86_64__))
 /*
  * read CPU frequency from a sysfs file, return an frequency in Megahertz as
@@ -528,11 +624,19 @@ static uint64_t timestamp_get(uint64_t table_tick_freq_mhz)
 {
 #if defined(__i386__) || defined(__x86_64__)
 	uint64_t tsc = __rdtsc();
+	struct lb_tsc_info *tsc_info;
+	size_t size;
 
 	/* No tick frequency specified means raw TSC values. */
 	if (!table_tick_freq_mhz)
 		return tsc;
 
+	lb_table_get_entry(LB_TAG_TSC_INFO, (uint8_t **)&tsc_info, &size);
+
+	const uint32_t tsc_freq_khz = tsc_info->freq_khz;
+
+	free(tsc_info);
+
 	if (tsc_freq_khz)
 		return tsc * table_tick_freq_mhz * 1000 / tsc_freq_khz;
 #else
@@ -679,34 +783,23 @@ static void dump_timestamps(enum timestamps_print_type output_type)
 	size_t size;
 	uint64_t prev_stamp = 0;
 	uint64_t total_time = 0;
-	struct mapping timestamp_mapping;
 
-	if (timestamps.tag != LB_TAG_TIMESTAMPS) {
-		fprintf(stderr, "No timestamps found in coreboot table.\n");
-		return;
+	if (get_cbmem_entry(CBMEM_ID_TIMESTAMP, (uint8_t **)&tst_p, &size)) {
+		fprintf(stderr, "Timestamps not found.\n");
+		abort();
 	}
 
-	size = sizeof(*tst_p);
-	tst_p = map_memory(&timestamp_mapping, timestamps.cbmem_addr, size);
-	if (!tst_p)
-		die("Unable to map timestamp header\n");
-
 	timestamp_set_tick_freq(tst_p->tick_freq_mhz);
 
 	if (output_type == TIMESTAMPS_PRINT_NORMAL)
 		printf("%d entries total:\n\n", tst_p->num_entries);
-	size += tst_p->num_entries * sizeof(tst_p->entries[0]);
-
-	unmap_memory(&timestamp_mapping);
-
-	tst_p = map_memory(&timestamp_mapping, timestamps.cbmem_addr, size);
-	if (!tst_p)
-		die("Unable to map full timestamp table\n");
 
 	sorted_tst_p = malloc(size + sizeof(struct timestamp_entry));
-	if (!sorted_tst_p)
+	if (!sorted_tst_p) {
+		free((void *)tst_p);
 		die("Failed to allocate memory");
-	aligned_memcpy(sorted_tst_p, tst_p, size);
+	}
+	memcpy(sorted_tst_p, tst_p, size);
 
 	/*
 	 * Insert a timestamp to represent the base time (start of coreboot),
@@ -783,8 +876,8 @@ static void dump_timestamps(enum timestamps_print_type output_type)
 		printf("\n");
 	}
 
-	unmap_memory(&timestamp_mapping);
 	free(sorted_tst_p);
+	free((void *)tst_p);
 }
 
 /* add a timestamp entry */
@@ -792,16 +885,14 @@ static void timestamp_add_now(uint32_t timestamp_id)
 {
 	struct timestamp_table *tst_p;
 	struct mapping timestamp_mapping;
+	size_t tst_size;
 
-	if (timestamps.tag != LB_TAG_TIMESTAMPS) {
-		die("No timestamps found in coreboot table.\n");
+	if (map_cbmem_entry_rw(CBMEM_ID_TIMESTAMP, &timestamp_mapping, (uint8_t **)&tst_p,
+			       &tst_size)) {
+		fprintf(stderr, "Unable to find timestamps.\n");
+		abort();
 	}
 
-	tst_p = map_memory_with_prot(&timestamp_mapping, timestamps.cbmem_addr,
-				     timestamps.size, PROT_READ | PROT_WRITE);
-	if (!tst_p)
-		die("Unable to map timestamp table\n");
-
 	/*
 	 * Note that coreboot sizes the cbmem entry in the table according to
 	 * max_entries, so it's OK to just add more entries if there's room.
@@ -995,32 +1086,24 @@ static void parse_tpm2_log(const struct tcg_efi_spec_id_event *tpm2_log)
 }
 
 /* Dump the TPM log table in format defined by specifications */
-static void dump_tpm_std_log(uint64_t addr, size_t size)
+static void dump_tpm_std_log(void *buf)
 {
-	const void *event_log;
 	const struct tcpa_spec_entry *tspec_entry;
 	const struct tcg_efi_spec_id_event *tcg_spec_entry;
-	struct mapping log_mapping;
 
-	event_log = map_memory(&log_mapping, addr, size);
-	if (!event_log)
-		die("Unable to map TPM eventlog\n");
-
-	tspec_entry = event_log;
+	tspec_entry = buf;
 	if (!strcmp((const char *)tspec_entry->signature, TCPA_SPEC_ID_EVENT_SIGNATURE)) {
 		if (tspec_entry->spec_version_major == 1 &&
-		    tspec_entry->spec_version_minor == 2 &&
-		    tspec_entry->spec_errata >= 1 &&
+		    tspec_entry->spec_version_minor == 2 && tspec_entry->spec_errata >= 1 &&
 		    le32toh(tspec_entry->entry.event_type) == EV_NO_ACTION) {
 			parse_tpm12_log(tspec_entry);
 		} else {
 			fprintf(stderr, "Unknown TPM1.2 log specification\n");
 		}
-		unmap_memory(&log_mapping);
 		return;
 	}
 
-	tcg_spec_entry = event_log;
+	tcg_spec_entry = buf;
 	if (!strcmp((const char *)tcg_spec_entry->signature, TCG_EFI_SPEC_ID_EVENT_SIGNATURE)) {
 		if (tcg_spec_entry->spec_version_major == 2 &&
 		    tcg_spec_entry->spec_version_minor == 0 &&
@@ -1029,42 +1112,25 @@ static void dump_tpm_std_log(uint64_t addr, size_t size)
 		} else {
 			fprintf(stderr, "Unknown TPM2 log specification.\n");
 		}
-		unmap_memory(&log_mapping);
 		return;
 	}
 
 	fprintf(stderr, "Unknown TPM log specification: %.*s\n",
 		(int)sizeof(tcg_spec_entry->signature),
 		(const char *)tcg_spec_entry->signature);
-
-	unmap_memory(&log_mapping);
 }
 
 /* dump the TPM CB log table */
 static void dump_tpm_cb_log(void)
 {
 	const struct tpm_cb_log_table *tclt_p;
-	size_t size;
-	struct mapping log_mapping;
+	size_t tclt_size;
 
-	if (tpm_cb_log.tag != LB_TAG_TPM_CB_LOG) {
-		fprintf(stderr, "No TPM log found in coreboot table.\n");
-		return;
+	if (get_cbmem_entry(CBMEM_ID_TPM_CB_LOG, (uint8_t **)&tclt_p, &tclt_size)) {
+		fprintf(stderr, "coreboot TPM log not found.\n");
+		abort();
 	}
 
-	size = sizeof(*tclt_p);
-	tclt_p = map_memory(&log_mapping, tpm_cb_log.cbmem_addr, size);
-	if (!tclt_p)
-		die("Unable to map TPM log header\n");
-
-	size += tclt_p->num_entries * sizeof(tclt_p->entries[0]);
-
-	unmap_memory(&log_mapping);
-
-	tclt_p = map_memory(&log_mapping, tpm_cb_log.cbmem_addr, size);
-	if (!tclt_p)
-		die("Unable to map full TPM log table\n");
-
 	printf("coreboot TPM log:\n\n");
 
 	for (uint16_t i = 0; i < tclt_p->num_entries; i++) {
@@ -1075,30 +1141,22 @@ static void dump_tpm_cb_log(void)
 		printf(" %s [%s]\n", tce->digest_type, tce->name);
 	}
 
-	unmap_memory(&log_mapping);
+	free((void *)tclt_p);
 }
 
 static void dump_tpm_log(void)
 {
-	uint64_t start;
+	uint8_t *buf;
 	size_t size;
 
-	if (!find_cbmem_entry(CBMEM_ID_TCPA_TCG_LOG, &start, &size) ||
-	    !find_cbmem_entry(CBMEM_ID_TPM2_TCG_LOG, &start, &size))
-		dump_tpm_std_log(start, size);
-	else
+	if (!get_cbmem_entry(CBMEM_ID_TCPA_TCG_LOG, &buf, &size) ||
+	    !get_cbmem_entry(CBMEM_ID_TPM2_TCG_LOG, &buf, &size)) {
+		dump_tpm_std_log(buf);
+		free(buf);
+	} else
 		dump_tpm_cb_log();
 }
 
-struct cbmem_console {
-	uint32_t size;
-	uint32_t cursor;
-	uint8_t  body[];
-}  __attribute__ ((__packed__));
-
-#define CBMC_CURSOR_MASK ((1 << 28) - 1)
-#define CBMC_OVERFLOW (1 << 31)
-
 enum console_print_type {
 	CONSOLE_PRINT_FULL = 0,
 	CONSOLE_PRINT_LAST,
@@ -1134,50 +1192,37 @@ static void dump_console(enum console_print_type type, int max_loglevel, int pri
 	const struct cbmem_console *console_p;
 	char *console_c;
 	size_t size, cursor, previous;
-	struct mapping console_mapping;
+	size_t console_buf_size;
 
-	if (console.tag != LB_TAG_CBMEM_CONSOLE) {
-		fprintf(stderr, "No console found in coreboot table.\n");
-		return;
+	if (get_cbmem_entry(CBMEM_ID_CONSOLE, (uint8_t **)&console_p, &console_buf_size)) {
+		fprintf(stderr, "CBMEM console not found.\n");
+		abort();
 	}
 
-	size = sizeof(*console_p);
-	console_p = map_memory(&console_mapping, console.cbmem_addr, size);
-	if (!console_p)
-		die("Unable to map console object.\n");
-
 	cursor = console_p->cursor & CBMC_CURSOR_MASK;
 	if (!(console_p->cursor & CBMC_OVERFLOW) && cursor < console_p->size)
 		size = cursor;
 	else
 		size = console_p->size;
-	unmap_memory(&console_mapping);
 
 	console_c = malloc(size + 1);
 	if (!console_c) {
 		fprintf(stderr, "Not enough memory for console.\n");
-		exit(1);
+		free((void *)console_p);
+		abort();
 	}
 	console_c[size] = '\0';
 
-	console_p = map_memory(&console_mapping, console.cbmem_addr,
-		size + sizeof(*console_p));
-
-	if (!console_p)
-		die("Unable to map full console object.\n");
-
 	if (console_p->cursor & CBMC_OVERFLOW) {
 		if (cursor >= size) {
 			printf("cbmem: ERROR: CBMEM console struct is illegal, "
 			       "output may be corrupt or out of order!\n\n");
 			cursor = 0;
 		}
-		aligned_memcpy(console_c, console_p->body + cursor,
-			       size - cursor);
-		aligned_memcpy(console_c + size - cursor,
-			       console_p->body, cursor);
+		memcpy(console_c, console_p->body + cursor, size - cursor);
+		memcpy(console_c + size - cursor, console_p->body, cursor);
 	} else {
-		aligned_memcpy(console_c, console_p->body, size);
+		memcpy(console_c, console_p->body, size);
 	}
 
 	/* Slight memory corruption may occur between reboots and give us a few
@@ -1252,109 +1297,88 @@ static void dump_console(enum console_print_type type, int max_loglevel, int pri
 		printf(BIOS_LOG_ESCAPE_RESET);
 
 	free(console_c);
-	unmap_memory(&console_mapping);
+	free((void *)console_p);
 }
 
-static void hexdump(unsigned long memory, int length)
+/* Hexdump provided buffer using start_address as an offset in the output. */
+static void hexdump(const uintptr_t start_address, const uint8_t *buf, const int length)
 {
 	int i;
-	const uint8_t *m;
 	int all_zero = 0;
-	struct mapping hexdump_mapping;
-
-	m = map_memory(&hexdump_mapping, memory, length);
-	if (!m)
-		die("Unable to map hexdump memory.\n");
 
 	for (i = 0; i < length; i += 16) {
 		int j;
 
 		all_zero++;
 		for (j = 0; j < 16; j++) {
-			if(m[i+j] != 0) {
+			if (buf[i + j] != 0) {
 				all_zero = 0;
 				break;
 			}
 		}
 
 		if (all_zero < 2) {
-			printf("%08lx:", memory + i);
+			printf("%08lx:", start_address + i);
 			for (j = 0; j < 16; j++)
-				printf(" %02x", m[i+j]);
+				printf(" %02x", buf[i + j]);
 			printf("  ");
 			for (j = 0; j < 16; j++)
-				printf("%c", isprint(m[i+j]) ? m[i+j] : '.');
+				printf("%c", isprint(buf[i + j]) ? buf[i + j] : '.');
 			printf("\n");
 		} else if (all_zero == 2) {
 			printf("...\n");
 		}
 	}
-
-	unmap_memory(&hexdump_mapping);
 }
 
 static void dump_cbmem_hex(void)
 {
-	if (cbmem.type != LB_MEM_TABLE) {
-		fprintf(stderr, "No coreboot CBMEM area found!\n");
-		return;
+	struct mapping cbmem_mapping;
+	struct lb_memory *memory;
+	const uint8_t *buf = NULL;
+	size_t size = 0;
+
+	lb_table_get_entry(LB_TAG_MEMORY, (uint8_t **)&memory, &size);
+
+	if (!memory)
+		die("No memory entries available.\n");
+
+	const int entries = (memory->size - sizeof(*memory)) / sizeof(memory->map[0]);
+	/* First from the end is CBMEM */
+	for (int i = entries - 1; i >= 0; --i) {
+		if (memory->map[i].type != LB_MEM_TABLE)
+			continue;
+
+		buf = map_memory(&cbmem_mapping, memory->map[i].start, memory->map[i].size);
+		if (!buf)
+			die("Unable to map CBMEM area memory.\n");
+
+		size = memory->map[i].size;
+		break;
 	}
 
-	hexdump(cbmem.start, cbmem.size);
-}
+	if (!buf)
+		die("Unable to find CBMEM area memory entry.\n");
 
-static void rawdump(uint64_t base, uint64_t size)
-{
-	const uint8_t *m;
-	struct mapping dump_mapping;
+	hexdump(cbmem_mapping.phys, buf, size);
 
-	m = map_memory(&dump_mapping, base, size);
-	if (!m)
-		die("Unable to map rawdump memory\n");
-
-	for (uint64_t i = 0 ; i < size; i++)
-		printf("%c", m[i]);
-
-	unmap_memory(&dump_mapping);
+	unmap_memory(&cbmem_mapping);
+	free(memory);
 }
 
 static void dump_cbmem_raw(unsigned int id)
 {
-	const uint8_t *table;
-	size_t offset;
-	uint64_t base = 0;
-	uint64_t size = 0;
+	uint8_t *buf;
+	size_t size;
 
-	table = mapping_virt(&lbtable_mapping);
-
-	if (table == NULL)
-		return;
-
-	offset = 0;
-
-	while (offset < mapping_size(&lbtable_mapping)) {
-		const struct lb_record *lbr;
-		struct lb_cbmem_entry lbe;
-
-		lbr = (const void *)(table + offset);
-		offset += lbr->size;
-
-		if (lbr->tag != LB_TAG_CBMEM_ENTRY)
-			continue;
-
-		aligned_memcpy(&lbe, lbr, sizeof(lbe));
-		if (lbe.id == id) {
-			debug("found id for raw dump %0x", lbe.id);
-			base = lbe.address;
-			size = lbe.entry_size;
-			break;
-		}
+	if (get_cbmem_entry(id, &buf, &size)) {
+		fprintf(stderr, "cbmem entry id: %#x not found.\n", id);
+		abort();
 	}
 
-	if (!base)
-		fprintf(stderr, "id %0x not found in cbtable\n", id);
-	else
-		rawdump(base, size);
+	fwrite(buf, 1, size, stdout);
+
+	free(buf);
 }
 
 struct cbmem_id_to_name {
@@ -1399,34 +1423,31 @@ static void cbmem_print_entry(int n, uint32_t id, uint64_t base, uint64_t size)
 
 static void dump_cbmem_toc(void)
 {
-	int i;
-	const uint8_t *table;
-	size_t offset;
+	int i = 0;
+	const uint8_t *table = NULL;
+	size_t table_size = 0;
 
-	table = mapping_virt(&lbtable_mapping);
+	if (get_cbmem_entry(CBMEM_ID_CBTABLE, (uint8_t **)&table, &table_size)) {
+		fprintf(stderr, "coreboot table not found.\n");
+		abort();
+	}
 
-	if (table == NULL)
-		return;
+	const struct lb_header *lbh = (const struct lb_header *)table;
 
 	printf("CBMEM table of contents:\n");
-	printf("    %-20s  %-8s  %-8s  %-8s\n", "NAME", "ID", "START",
-			"LENGTH");
+	printf("    %-20s  %-8s  %-8s  %-8s\n", "NAME", "ID", "START", "LENGTH");
 
-	i = 0;
-	offset = 0;
-
-	while (offset < mapping_size(&lbtable_mapping)) {
-		const struct lb_record *lbr;
-		struct lb_cbmem_entry lbe;
-
-		lbr = (const void *)(table + offset);
-		offset += lbr->size;
+	const struct lb_record *lbr = NULL;
+	for (size_t offset = lbh->header_bytes;
+	     offset < lbh->table_bytes + lbh->header_bytes - sizeof(struct lb_cbmem_entry);
+	     offset += lbr->size) {
+		lbr = (const struct lb_record *)&table[offset];
 
 		if (lbr->tag != LB_TAG_CBMEM_ENTRY)
 			continue;
 
-		aligned_memcpy(&lbe, lbr, sizeof(lbe));
-		cbmem_print_entry(i, lbe.id, lbe.address, lbe.entry_size);
+		const struct lb_cbmem_entry *lbe = (const struct lb_cbmem_entry *)lbr;
+		cbmem_print_entry(i, lbe->id, lbe->address, lbe->entry_size);
 		i++;
 	}
 }
@@ -1461,21 +1482,23 @@ static int mkpath(char *path, mode_t mode)
 static void dump_coverage(void)
 {
 	uint64_t start;
+	uint8_t *coverage;
 	size_t size;
-	const void *coverage;
-	struct mapping coverage_mapping;
 	unsigned long phys_offset;
 #define phys_to_virt(x) ((void *)(unsigned long)(x) + phys_offset)
 
+	if (get_cbmem_entry(CBMEM_ID_COVERAGE, &coverage, &size)) {
+		fprintf(stderr, "No coverage information found\n");
+		return;
+	}
+
+	// Physical address is needed for pointer translation
 	if (find_cbmem_entry(CBMEM_ID_COVERAGE, &start, &size)) {
 		fprintf(stderr, "No coverage information found\n");
 		return;
 	}
 
 	/* Map coverage area */
-	coverage = map_memory(&coverage_mapping, start, size);
-	if (!coverage)
-		die("Unable to map coverage area.\n");
 	phys_offset = (unsigned long)coverage - (unsigned long)start;
 
 	printf("Dumping coverage data...\n");
@@ -1512,7 +1535,7 @@ static void dump_coverage(void)
 		else
 			file = NULL;
 	}
-	unmap_memory(&coverage_mapping);
+	free(coverage);
 }
 
 static void print_version(void)

From 471df8ca5e9cea6099e23e7c373c7e72a16c5cf5 Mon Sep 17 00:00:00 2001
From: Maximilian Brune <maximilian.brune@9elements.com>
Date: Mon, 12 May 2025 20:25:55 +0200
Subject: [PATCH 1224/3886] util/crossgcc/buildgcc: Fix GMP build on GCC 15

Currently building GMP with GCC 15 causes this error:
"configure: error: could not find a working compiler, see config.log
for details"

GCC 15 by default uses std=gnu23 but that causes the build of GMP to
fail. So hardcode it to always build GMP using std=gnu17.

Once GMP is fixed in their next release, we can remove this again.

source:
https://gmplib.org/list-archives/gmp-bugs/2024-November/005550.html

Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: I7813ff18e8e486bece503652af69de1db93958b2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87650
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 util/crossgcc/buildgcc | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc
index 1b0c89ae1c..57aeb96ab5 100755
--- a/util/crossgcc/buildgcc
+++ b/util/crossgcc/buildgcc
@@ -654,7 +654,9 @@ build_GMP() {
 	fi
 
 	# shellcheck disable=SC2086
-	CC="$(hostcc host)" CXX="$(hostcxx host)" \
+	# Bug: GMP currently does not support being build by GCC 15 (--std=gnu23)
+	#      Remove CFLAGS once it works again.
+	CC="$(hostcc host)" CXX="$(hostcxx host)" CFLAGS="-std=gnu17" \
 	../${GMP_DIR}/configure \
 		--disable-shared \
 		--enable-fat \

From 8961f6681f37b699827f291d3cbfa101f4bbb4b9 Mon Sep 17 00:00:00 2001
From: Jeremy Compostella <jeremy.compostella@intel.com>
Date: Tue, 3 Jun 2025 15:43:52 -0700
Subject: [PATCH 1225/3886] soc/intel/common/acpi/pcie_clk: Fix ACPI
 conditional compilation error

This commit addresses a compilation error in the PCIe ClkReq SPCO method
due to incorrect conditional compilation logic. The previous
implementation lacked the necessary preprocessor directives to
differentiate between configurations when
SOC_INTEL_COMMON_BLOCK_IOE_P2SB is not defined.

BUG=b:422284273

Change-Id: Ie7b70babd279f7241f6e76113a6694a5bd0d782d
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87930
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
---
 src/soc/intel/common/acpi/pcie_clk.asl | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/src/soc/intel/common/acpi/pcie_clk.asl b/src/soc/intel/common/acpi/pcie_clk.asl
index e7e311fe9c..b74d601a1a 100644
--- a/src/soc/intel/common/acpi/pcie_clk.asl
+++ b/src/soc/intel/common/acpi/pcie_clk.asl
@@ -14,6 +14,7 @@
  * Arg1: Enable(1)/Disable(0) Clock
  */
 Method (SPCO, 2, Serialized) {
+#if CONFIG(SOC_INTEL_COMMON_BLOCK_IOE_P2SB)
 	If (LEqual (Arg1,1)) {
 		If (LGreaterEqual (Arg0, CONFIG_IOE_DIE_CLOCK_START)) {
 			\_SB.ECLK.CLKE (Subtract (Arg0, CONFIG_IOE_DIE_CLOCK_START))
@@ -27,4 +28,11 @@ Method (SPCO, 2, Serialized) {
 			\_SB.ICLK.CLKD (Arg0)
 		}
 	}
+#else
+	If (LEqual (Arg1,1)) {
+		\_SB.ICLK.CLKE (Arg0)
+	} Else {
+		\_SB.ICLK.CLKD (Arg0)
+	}
+#endif
 }

From 61ac238bb5e5d3d52a4ee425fa5b8feaa55d9484 Mon Sep 17 00:00:00 2001
From: Sowmya Aralguppe <sowmya.aralguppe@intel.com>
Date: Tue, 15 Apr 2025 10:28:56 +0530
Subject: [PATCH 1226/3886] soc/intel/common/block/p2sb: Add driver for second
 P2SB device

This commit introduces a driver for a second P2SB (Primary to SideBand)
device to support certain Intel SoC configurations. The new driver
offers new functions, such as p2sb2_enable_bar(), p2sb2_sbi_read(), and
p2sb2_sbi_write(), for accessing and managing the second P2SB
interface (P2SB2). This interface is essential for managing sideband
communications in some Intel SoCs, such as Panther Lake.

BUG=b:422284273
TEST=Successful communication with the P2SB2 device during Fatcat board
     boot.

Change-Id: I33941c85243e2529d1dd931b2afd7ab4814d9549
Signed-off-by: Sowmya Aralguppe <sowmya.aralguppe@intel.com>
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87929
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
---
 .../common/block/include/intelblocks/p2sb.h   |  8 +++
 src/soc/intel/common/block/p2sb/Kconfig       |  7 +++
 src/soc/intel/common/block/p2sb/Makefile.mk   |  6 +++
 src/soc/intel/common/block/p2sb/p2sb2.c       | 50 +++++++++++++++++++
 4 files changed, 71 insertions(+)
 create mode 100644 src/soc/intel/common/block/p2sb/p2sb2.c

diff --git a/src/soc/intel/common/block/include/intelblocks/p2sb.h b/src/soc/intel/common/block/include/intelblocks/p2sb.h
index bf2fc670c6..e587a4d25e 100644
--- a/src/soc/intel/common/block/include/intelblocks/p2sb.h
+++ b/src/soc/intel/common/block/include/intelblocks/p2sb.h
@@ -37,6 +37,14 @@ void ioe_p2sb_enable_bar(void);
 uint32_t ioe_p2sb_sbi_read(uint8_t pid, uint16_t reg);
 void ioe_p2sb_sbi_write(uint8_t pid, uint16_t reg, uint32_t val);
 
+/*
+ * Functions to access SoC P2SB2.
+ * pid argument: SBI port Id
+ */
+void p2sb2_enable_bar(void);
+uint32_t p2sb2_sbi_read(uint8_t pid, uint16_t reg);
+void p2sb2_sbi_write(uint8_t pid, uint16_t reg, uint32_t val);
+
 union p2sb_bdf {
 	struct {
 		uint16_t fn  : 3;
diff --git a/src/soc/intel/common/block/p2sb/Kconfig b/src/soc/intel/common/block/p2sb/Kconfig
index d67c968941..2e38932bc0 100644
--- a/src/soc/intel/common/block/p2sb/Kconfig
+++ b/src/soc/intel/common/block/p2sb/Kconfig
@@ -12,6 +12,13 @@ config SOC_INTEL_COMMON_BLOCK_P2SB
 	help
 	  Intel Processor common P2SB driver for PCH or SoC die
 
+config SOC_INTEL_COMMON_BLOCK_P2SB2
+	bool
+	select SOC_INTEL_COMMON_BLOCK_BASE_P2SB
+	help
+	  Intel Processor common driver for a second P2SB (Primary to
+	  SideBand) interface to PCH or SoC die
+
 config SOC_INTEL_COMMON_BLOCK_IOE_P2SB
 	bool
 	select SOC_INTEL_COMMON_BLOCK_BASE_P2SB
diff --git a/src/soc/intel/common/block/p2sb/Makefile.mk b/src/soc/intel/common/block/p2sb/Makefile.mk
index bcdd5a2752..dc425f0807 100644
--- a/src/soc/intel/common/block/p2sb/Makefile.mk
+++ b/src/soc/intel/common/block/p2sb/Makefile.mk
@@ -10,6 +10,12 @@ romstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_P2SB) += p2sb.c
 ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_P2SB) += p2sb.c
 smm-$(CONFIG_SOC_INTEL_COMMON_BLOCK_P2SB) += p2sb.c
 
+# p2sb2.c for SoC die P2SB2 IP
+bootblock-$(CONFIG_SOC_INTEL_COMMON_BLOCK_P2SB2) += p2sb2.c
+romstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_P2SB2) += p2sb2.c
+ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_P2SB2) += p2sb2.c
+smm-$(CONFIG_SOC_INTEL_COMMON_BLOCK_P2SB2) += p2sb2.c
+
 # ioe_p2sb.c for IOE die P2SB IP
 bootblock-$(CONFIG_SOC_INTEL_COMMON_BLOCK_IOE_P2SB) += ioe_p2sb.c
 romstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_IOE_P2SB) += ioe_p2sb.c
diff --git a/src/soc/intel/common/block/p2sb/p2sb2.c b/src/soc/intel/common/block/p2sb/p2sb2.c
new file mode 100644
index 0000000000..2627a7182c
--- /dev/null
+++ b/src/soc/intel/common/block/p2sb/p2sb2.c
@@ -0,0 +1,50 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#define __SIMPLE_DEVICE__
+
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <intelblocks/p2sb.h>
+#include <intelblocks/p2sblib.h>
+#include <intelblocks/pcr.h>
+#include <soc/iomap.h>
+#include <soc/pci_devs.h>
+
+uint32_t p2sb2_sbi_read(uint8_t pid, uint16_t reg)
+{
+	return p2sb_dev_sbi_read(PCI_DEV_P2SB2, pid, reg);
+}
+
+void p2sb2_sbi_write(uint8_t pid, uint16_t reg, uint32_t val)
+{
+	p2sb_dev_sbi_write(PCI_DEV_P2SB2, pid, reg, val);
+}
+
+void p2sb2_enable_bar(void)
+{
+	p2sb_dev_enable_bar(PCI_DEV_P2SB2, P2SB2_BAR);
+}
+
+static void read_resources(struct device *dev)
+{
+	mmio_range(dev, PCI_BASE_ADDRESS_0, P2SB2_BAR, P2SB2_SIZE);
+}
+
+struct device_operations p2sb2_ops = {
+	.read_resources   = read_resources,
+	.set_resources    = noop_set_resources,
+	.ops_pci          = &pci_dev_ops_pci,
+};
+
+static const unsigned short pci_device_ids[] = {
+	PCI_DID_INTEL_WCL_P2SB2,
+	PCI_DID_INTEL_PTL_H_P2SB2,
+	PCI_DID_INTEL_PTL_U_H_P2SB2,
+	0,
+};
+
+static const struct pci_driver p2sb2 __pci_driver = {
+	.ops     = &p2sb2_ops,
+	.vendor  = PCI_VID_INTEL,
+	.devices = pci_device_ids,
+};

From 5277bc4efcaaa747721b55a1f134a19010214549 Mon Sep 17 00:00:00 2001
From: Jeremy Compostella <jeremy.compostella@intel.com>
Date: Tue, 3 Jun 2025 15:50:11 -0700
Subject: [PATCH 1227/3886] soc/intel/pantherlake: Resolve memory corruption by
 using P2SB2 driver

This commit fixes memory corruption observed during stress
suspend-resume tests on the Fatcat board using Panther Lake U and H
SoCs. The issue stemmed from incorrect routing in the SPCO ACPI method
due to the use of SOC_INTEL_COMMON_BLOCK_IOE_P2SB, which was not
suitable as these SoCs lack an IOE die.

To address this, the commit switches from the IOE driver to the P2SB2
driver, aligning with the appropriate SOC_INTEL_COMMON_BLOCK_P2SB2
selection. The related function calls in the Panther Lake codebase have
been updated to use P2SB2-specific operations.

Panther Lake H and U SoC identifiers have been moved from the IOE driver
to the P2SB2 driver.

BUG=b:422284273
TEST=Memory corruption does not reproduce on the Fatcat board.

Change-Id: If678846b6285aea8cd53b0f7aebe3e75812a9330
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87931
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
---
 src/soc/intel/common/block/p2sb/ioe_p2sb.c | 3 ---
 src/soc/intel/pantherlake/Kconfig          | 2 +-
 src/soc/intel/pantherlake/bootblock/pcd.c  | 2 +-
 src/soc/intel/pantherlake/chip.c           | 2 +-
 4 files changed, 3 insertions(+), 6 deletions(-)

diff --git a/src/soc/intel/common/block/p2sb/ioe_p2sb.c b/src/soc/intel/common/block/p2sb/ioe_p2sb.c
index a27a23dd74..769b853af2 100644
--- a/src/soc/intel/common/block/p2sb/ioe_p2sb.c
+++ b/src/soc/intel/common/block/p2sb/ioe_p2sb.c
@@ -37,9 +37,6 @@ struct device_operations device_ops = {
 };
 
 static const unsigned short pci_device_ids[] = {
-	PCI_DID_INTEL_WCL_P2SB2,
-	PCI_DID_INTEL_PTL_H_P2SB2,
-	PCI_DID_INTEL_PTL_U_H_P2SB2,
 	PCI_DID_INTEL_MTL_IOE_M_P2SB,
 	PCI_DID_INTEL_MTL_IOE_P_P2SB,
 	0,
diff --git a/src/soc/intel/pantherlake/Kconfig b/src/soc/intel/pantherlake/Kconfig
index 452591667b..089e8a7c34 100644
--- a/src/soc/intel/pantherlake/Kconfig
+++ b/src/soc/intel/pantherlake/Kconfig
@@ -73,11 +73,11 @@ config SOC_INTEL_PANTHERLAKE_BASE
 	select SOC_INTEL_COMMON_BLOCK_HDA
 	select SOC_INTEL_COMMON_BLOCK_HECI1_DISABLE_USING_PMC_IPC
 	select SOC_INTEL_COMMON_BLOCK_IOC
-	select SOC_INTEL_COMMON_BLOCK_IOE_P2SB
 	select SOC_INTEL_COMMON_BLOCK_IPU if SOC_INTEL_PANTHERLAKE
 	select SOC_INTEL_COMMON_BLOCK_IRQ
 	select SOC_INTEL_COMMON_BLOCK_ME_SPEC_21
 	select SOC_INTEL_COMMON_BLOCK_MEMINIT
+	select SOC_INTEL_COMMON_BLOCK_P2SB2
 	select SOC_INTEL_COMMON_BLOCK_PCIE_RTD3
 	select SOC_INTEL_COMMON_BLOCK_PMC_EPOC
 	select SOC_INTEL_COMMON_BLOCK_POWER_LIMIT
diff --git a/src/soc/intel/pantherlake/bootblock/pcd.c b/src/soc/intel/pantherlake/bootblock/pcd.c
index a630f9013f..50e6ebd73d 100644
--- a/src/soc/intel/pantherlake/bootblock/pcd.c
+++ b/src/soc/intel/pantherlake/bootblock/pcd.c
@@ -69,7 +69,7 @@ static void pcd_die_early_ip_init(void)
 	 * controller might want to perform PCR settings.
 	 */
 	p2sb_enable_bar();
-	ioe_p2sb_enable_bar();
+	p2sb2_enable_bar();
 	p2sb_configure_hpet();
 
 	fast_spi_early_init(SPI_BASE_ADDRESS);
diff --git a/src/soc/intel/pantherlake/chip.c b/src/soc/intel/pantherlake/chip.c
index 317fa5fa0e..24c6fc33ee 100644
--- a/src/soc/intel/pantherlake/chip.c
+++ b/src/soc/intel/pantherlake/chip.c
@@ -177,7 +177,7 @@ void soc_init_pre_device(void *chip_info)
 		return;
 	}
 	/* Validate TBT image authentication */
-	config->tbt_authentication = ioe_p2sb_sbi_read(PID_IOM,
+	config->tbt_authentication = p2sb2_sbi_read(PID_IOM,
 					IOM_CSME_IMR_TBT_STATUS) & TBT_VALID_AUTHENTICATION;
 
 	if (CONFIG(SOC_INTEL_COMMON_BLOCK_TRACEHUB))

From beafbfd29ae09b8fc7a10545de9927bd998fba4f Mon Sep 17 00:00:00 2001
From: Jeremy Compostella <jeremy.compostella@intel.com>
Date: Tue, 3 Jun 2025 20:10:48 -0700
Subject: [PATCH 1228/3886] soc/intel/pantherlake: Remove IOE support and
 references

Panther Lake H and U variants do not include any IOE die, making IOE
support unnecessary. This commit removes references to IOE support
across the Panther Lake SoC configuration and related files, simplifying
the codebase and avoiding potential misconfigurations.

These changes reduce unnecessary complexity and potential confusion
regarding IOE functionality in Panther Lake H and U SoCs, ensuring
configurations accurately reflect hardware capabilities.

BUG=b:422284273

Change-Id: I0ede4e1157c473763d53a9a3e6ab913ab470dc42
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87933
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/soc/intel/pantherlake/Kconfig                |  1 -
 src/soc/intel/pantherlake/acpi/southbridge.asl   |  2 --
 src/soc/intel/pantherlake/include/soc/iomap.h    |  2 --
 src/soc/intel/pantherlake/include/soc/pci_devs.h |  1 -
 src/soc/intel/pantherlake/p2sb.c                 |  2 +-
 src/soc/intel/pantherlake/tcss.c                 | 12 ++++++------
 6 files changed, 7 insertions(+), 13 deletions(-)

diff --git a/src/soc/intel/pantherlake/Kconfig b/src/soc/intel/pantherlake/Kconfig
index 089e8a7c34..03865b2ddf 100644
--- a/src/soc/intel/pantherlake/Kconfig
+++ b/src/soc/intel/pantherlake/Kconfig
@@ -98,7 +98,6 @@ config SOC_INTEL_PANTHERLAKE_BASE
 	select SOC_INTEL_CSE_SEND_EOP_LATE if !MAINBOARD_HAS_CHROMEOS
 	select SOC_INTEL_CSE_SET_EOP
 	select SOC_INTEL_GFX_NON_PREFETCHABLE_MMIO
-	select SOC_INTEL_IOE_DIE_SUPPORT
 	select SOC_INTEL_MEM_MAPPED_PM_CONFIGURATION
 	select SOC_QDF_DYNAMIC_READ_PMC
 	select SSE2
diff --git a/src/soc/intel/pantherlake/acpi/southbridge.asl b/src/soc/intel/pantherlake/acpi/southbridge.asl
index 20e23122fb..bf30363b0f 100644
--- a/src/soc/intel/pantherlake/acpi/southbridge.asl
+++ b/src/soc/intel/pantherlake/acpi/southbridge.asl
@@ -6,8 +6,6 @@
 
 /* PCR access */
 #include <soc/intel/common/acpi/pch_pcr.asl>
-/* IOE PCR access */
-#include <soc/intel/common/acpi/ioe_pcr.asl>
 
 /* PCIE src clock control */
 #include <soc/intel/common/acpi/pcie_clk.asl>
diff --git a/src/soc/intel/pantherlake/include/soc/iomap.h b/src/soc/intel/pantherlake/include/soc/iomap.h
index fac9c03f1c..fce3140544 100644
--- a/src/soc/intel/pantherlake/include/soc/iomap.h
+++ b/src/soc/intel/pantherlake/include/soc/iomap.h
@@ -74,8 +74,6 @@
 /* PCH P2SB2 256MB */
 #define P2SB2_BAR		CONFIG_P2SB_2_PCR_BASE_ADDRESS
 #define P2SB2_SIZE		(256 * MiB)
-#define IOE_P2SB_BAR		P2SB2_BAR
-#define IOE_P2SB_SIZE		P2SB2_SIZE
 
 /* IOM_BASE_ADDR = ((long int) Ps2bMmioBase | (int) (((Offset) & 0x0F0000) << 8) \
  * | ((unsigned char)(Pid) << 16) | (short int) ((Offset) & 0xFFFF))
diff --git a/src/soc/intel/pantherlake/include/soc/pci_devs.h b/src/soc/intel/pantherlake/include/soc/pci_devs.h
index dc7130cbb5..7dc55e1045 100644
--- a/src/soc/intel/pantherlake/include/soc/pci_devs.h
+++ b/src/soc/intel/pantherlake/include/soc/pci_devs.h
@@ -247,7 +247,6 @@
 #define PCH_DEV_SPI		PCI_DEV_SPI
 #define PCH_DEV_LPC		PCI_DEV_ESPI
 #define PCH_DEV_P2SB		PCI_DEV_P2SB
-#define PCI_DEV_IOE_P2SB	PCI_DEV_P2SB2
 #define PCH_DEV_SMBUS		PCI_DEV_SMBUS
 #define PCH_DEV_XHCI		PCI_DEV_XHCI
 #define PCH_DEVFN_XHCI		PCI_DEVFN_XHCI
diff --git a/src/soc/intel/pantherlake/p2sb.c b/src/soc/intel/pantherlake/p2sb.c
index 52b36903d6..6915463937 100644
--- a/src/soc/intel/pantherlake/p2sb.c
+++ b/src/soc/intel/pantherlake/p2sb.c
@@ -35,7 +35,7 @@ void p2sb_soc_get_sb_mask(uint32_t *ep_mask, size_t count)
 static void p2sb2_read_resources(struct device *dev)
 {
 	/* Add the fixed MMIO resource for P2SB#2 */
-	mmio_range(dev, PCI_BASE_ADDRESS_0, IOE_P2SB_BAR, IOE_P2SB_SIZE);
+	mmio_range(dev, PCI_BASE_ADDRESS_0, P2SB2_BAR, P2SB2_SIZE);
 }
 
 static void p2sb_read_resources(struct device *dev)
diff --git a/src/soc/intel/pantherlake/tcss.c b/src/soc/intel/pantherlake/tcss.c
index c66a5c68ce..1b7a34acc9 100644
--- a/src/soc/intel/pantherlake/tcss.c
+++ b/src/soc/intel/pantherlake/tcss.c
@@ -4,13 +4,13 @@
 #include <soc/soc_chip.h>
 #include <static.h>
 
-const struct soc_tcss_ops tcss_ops = {
-	.configure_aux_bias_pads = NULL,
-	.valid_tbt_auth = ioe_tcss_valid_tbt_auth,
-};
-
-bool ioe_tcss_valid_tbt_auth(void)
+static bool soc_tcss_valid_tbt_auth(void)
 {
 	const config_t *config = config_of_soc();
 	return config->tbt_authentication;
 }
+
+const struct soc_tcss_ops tcss_ops = {
+	.configure_aux_bias_pads = NULL,
+	.valid_tbt_auth = soc_tcss_valid_tbt_auth,
+};

From 619699648fd47e4bc0146c94be2650e9e05f5fec Mon Sep 17 00:00:00 2001
From: Jeremy Compostella <jeremy.compostella@intel.com>
Date: Wed, 4 Jun 2025 12:05:35 -0700
Subject: [PATCH 1229/3886] soc/intel/pantherlake: Simplify P2SB and P2SB2
 device operations

This commit refactors the Pantherlake SOC code by leveraging existing
P2SB device operations, thereby removing redundant definitions. The
change eliminates unnecessary device operation structures (pcd_p2sb_ops
and pcd_p2sb_2_ops) and replaces them with references to already defined
operations (p2sb_ops and p2sb2_ops). This is similar to how it is
handled in the Alder Lake codebase.

BUG=b:422284273
TEST=Boot on Fatcat with and without this commit, compare the logs, and
     verify that the I/O memory resources for P2SB and P2SB2 devices are
     accounted for and are identical.

Change-Id: I9304b6aa16f07fdc7d927cc2e27879db549ac774
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87955
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
---
 src/soc/intel/pantherlake/chip.c             |  7 +++--
 src/soc/intel/pantherlake/include/soc/p2sb.h |  4 +--
 src/soc/intel/pantherlake/p2sb.c             | 28 +-------------------
 3 files changed, 8 insertions(+), 31 deletions(-)

diff --git a/src/soc/intel/pantherlake/chip.c b/src/soc/intel/pantherlake/chip.c
index 24c6fc33ee..8005240475 100644
--- a/src/soc/intel/pantherlake/chip.c
+++ b/src/soc/intel/pantherlake/chip.c
@@ -247,6 +247,9 @@ static struct device_operations cpu_bus_ops = {
 
 static void soc_enable(struct device *dev)
 {
+	struct device_operations *soc_p2sb_ops = (struct device_operations *)&p2sb_ops;
+	struct device_operations *soc_p2sb2_ops = (struct device_operations *)&p2sb2_ops;
+
 	/*
 	 * Set the operations if it is a special bus type or a hidden PCI
 	 * device.
@@ -260,10 +263,10 @@ static void soc_enable(struct device *dev)
 		dev->ops = &pmc_ops;
 	else if (dev->path.type == DEVICE_PATH_PCI &&
 		 dev->path.pci.devfn == PCI_DEVFN_P2SB)
-		dev->ops = &pcd_p2sb_ops;
+		dev->ops = soc_p2sb_ops;
 	else if (dev->path.type == DEVICE_PATH_PCI &&
 		 dev->path.pci.devfn == PCI_DEVFN_P2SB2)
-		dev->ops = &pcd_p2sb_2_ops;
+		dev->ops = soc_p2sb2_ops;
 	else if (dev->path.type == DEVICE_PATH_GPIO)
 		block_gpio_enable(dev);
 }
diff --git a/src/soc/intel/pantherlake/include/soc/p2sb.h b/src/soc/intel/pantherlake/include/soc/p2sb.h
index 9bf7e2d4b8..36ffd2957b 100644
--- a/src/soc/intel/pantherlake/include/soc/p2sb.h
+++ b/src/soc/intel/pantherlake/include/soc/p2sb.h
@@ -8,7 +8,7 @@
 
 #define PCH_P2SB_EPMASK0		0x220
 
-extern struct device_operations pcd_p2sb_ops;
-extern struct device_operations pcd_p2sb_2_ops;
+extern const struct device_operations p2sb_ops;
+extern const struct device_operations p2sb2_ops;
 
 #endif
diff --git a/src/soc/intel/pantherlake/p2sb.c b/src/soc/intel/pantherlake/p2sb.c
index 6915463937..3b86bb07e8 100644
--- a/src/soc/intel/pantherlake/p2sb.c
+++ b/src/soc/intel/pantherlake/p2sb.c
@@ -1,10 +1,8 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
 #include <console/console.h>
-#include <device/device.h>
-#include <device/pci_def.h>
 #include <intelblocks/p2sb.h>
-#include <soc/iomap.h>
+#include <types.h>
 
 void p2sb_soc_get_sb_mask(uint32_t *ep_mask, size_t count)
 {
@@ -31,27 +29,3 @@ void p2sb_soc_get_sb_mask(uint32_t *ep_mask, size_t count)
 
 	ep_mask[P2SB_EP_MASK_7_REG] = mask;
 }
-
-static void p2sb2_read_resources(struct device *dev)
-{
-	/* Add the fixed MMIO resource for P2SB#2 */
-	mmio_range(dev, PCI_BASE_ADDRESS_0, P2SB2_BAR, P2SB2_SIZE);
-}
-
-static void p2sb_read_resources(struct device *dev)
-{
-	/* Add the fixed MMIO resource for P2SB#1 */
-	mmio_range(dev, PCI_BASE_ADDRESS_0, P2SB_BAR, P2SB_SIZE);
-}
-
-struct device_operations pcd_p2sb_2_ops = {
-	.read_resources   = p2sb2_read_resources,
-	.set_resources    = noop_set_resources,
-	.scan_bus         = scan_static_bus,
-};
-
-struct device_operations pcd_p2sb_ops = {
-	.read_resources   = p2sb_read_resources,
-	.set_resources    = noop_set_resources,
-	.scan_bus         = scan_static_bus,
-};

From 24778a25decbcfaa2e8e5daf8c9819d388d86927 Mon Sep 17 00:00:00 2001
From: Luca Lai <luca.lai@lcfc.corp-partner.google.com>
Date: Thu, 5 Jun 2025 13:06:28 +0800
Subject: [PATCH 1230/3886] mb/trulo/var/pujjolo: Fix gtx functions.
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Add gtx flag in Kconfig and delete the gtx property to fix build error in below
coreboot-0.0.1-r5710: /build/nissa/tmp/portage/sys-boot/coreboot-0.0.1-r5710/work/build/pujjolo/mainboard/google/brya/static.c:213:20: error: 'struct drivers_gfx_generic_device_config' has no member named 'type'
coreboot-0.0.1-r5710:   213 |         .device[0].type = panel,
coreboot-0.0.1-r5710:       |                    ^~~~
coreboot-0.0.1-r5710: /build/nissa/tmp/portage/sys-boot/coreboot-0.0.1-r5710/work/build/pujjolo/mainboard/google/brya/static.c:213:27: error: 'panel' undeclared here (not in a function)
coreboot-0.0.1-r5710:   213 |         .device[0].type = panel,
coreboot-0.0.1-r5710:       |                           ^~~~~

BUG=b:395763555
BRANCH=none
TEST=Build pujjolo

Change-Id: I4e85f3c9acbee66226d8dd195615d9c9dd212709
Signed-off-by: Luca Lai <luca.lai@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87956
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
---
 src/mainboard/google/brya/Kconfig                          | 1 +
 src/mainboard/google/brya/variants/pujjolo/overridetree.cb | 3 ---
 2 files changed, 1 insertion(+), 3 deletions(-)

diff --git a/src/mainboard/google/brya/Kconfig b/src/mainboard/google/brya/Kconfig
index 06adc7f346..938bbe220e 100644
--- a/src/mainboard/google/brya/Kconfig
+++ b/src/mainboard/google/brya/Kconfig
@@ -497,6 +497,7 @@ config BOARD_GOOGLE_PUJJOLO
 	select DRIVERS_GENERIC_GPIO_KEYS
 	select DRIVERS_INTEL_MIPI_CAMERA
 	select DRIVERS_I2C_SX9324
+	select DRIVERS_GFX_GENERIC
 	select DRIVERS_I2C_SX9324_SUPPORT_LEGACY_LINUX_DRIVER
 	select HAVE_WWAN_POWER_SEQUENCE
 	select SOC_INTEL_COMMON_BLOCK_HDA_VERB
diff --git a/src/mainboard/google/brya/variants/pujjolo/overridetree.cb b/src/mainboard/google/brya/variants/pujjolo/overridetree.cb
index 7588a8bfb5..5a42d3fcef 100644
--- a/src/mainboard/google/brya/variants/pujjolo/overridetree.cb
+++ b/src/mainboard/google/brya/variants/pujjolo/overridetree.cb
@@ -413,8 +413,6 @@ chip soc/intel/alderlake
 				register "device_count" = "4"
 				# DDIA for eDP
 				register "device[0].name" = ""LCD0""
-				# Internal panel on the first port of the graphics chip
-				register "device[0].type" = "panel"
 				# DDIB for HDMI
 				# If HDMI is not enumerated in the kernel, then no GFX device should be added for DDIB
 				register "device[1].name" = ""DD01""
@@ -515,7 +513,6 @@ chip soc/intel/alderlake
 						register "use_custom_pld" = "true"
 						register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, LEFT, ACPI_PLD_GROUP(2, 1))"
 						device ref usb2_port2 on end
-
 					end
 					chip drivers/usb/acpi
 						register "desc" = ""USB2 Type-A Port A1 (DB)""

From 5fcbc709ec98df3bd0ef4e0b69299f282e7dcc8e Mon Sep 17 00:00:00 2001
From: Pranava Y N <pranavayn@google.com>
Date: Tue, 27 May 2025 15:28:47 +0530
Subject: [PATCH 1231/3886] mb/google/fatcat/fmap: Add 1 MB from SI_BIOS to
 SI_All

This patch updates the flash layout for the fatcat variants. The changes
are as follows,

SI_ALL:      8MB --> 9MB
SI_BIOS:     24MB --> 23MB
  FW_A/B:    7.5MB --> 8.5MB
  RW_UNUSED: 2MB --> 0MB

BUG=b:419831198
TEST=Able to build and boot google/fatcat

Change-Id: I615b26ccdbbf3cfcc18dfb5917e13f0700ba673c
Signed-off-by: Pranava Y N <pranavayn@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87860
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
---
 src/mainboard/google/fatcat/chromeos.fmd | 34 ++++++++++++------------
 1 file changed, 17 insertions(+), 17 deletions(-)

diff --git a/src/mainboard/google/fatcat/chromeos.fmd b/src/mainboard/google/fatcat/chromeos.fmd
index 0ff14e3691..0cc9a2fee3 100644
--- a/src/mainboard/google/fatcat/chromeos.fmd
+++ b/src/mainboard/google/fatcat/chromeos.fmd
@@ -1,23 +1,9 @@
 FLASH 32M {
-	SI_ALL 8M {
+	SI_ALL 9M {
 		SI_DESC 16K
 		SI_ME
 	}
-	SI_BIOS 24M {
-		RW_SECTION_A 8M {
-			VBLOCK_A 8K
-			FW_MAIN_A(CBFS)
-			RW_FWID_A 64
-		}
-		# This section starts at the 16M boundary in SPI flash.
-		# PTL does not support a region crossing this boundary,
-		# because the SPI flash is memory-mapped into two non-
-		# contiguous windows.
-		RW_SECTION_B 8M {
-			VBLOCK_B 8K
-			FW_MAIN_B(CBFS)
-			RW_FWID_B 64
-		}
+	SI_BIOS 23M {
 		RW_MISC 1M {
 			UNIFIED_MRC_CACHE(PRESERVE) 128K {
 				RECOVERY_MRC_CACHE 64K
@@ -31,8 +17,22 @@ FLASH 32M {
 			RW_VPD(PRESERVE) 8K
 			RW_NVRAM(PRESERVE) 24K
 		}
+		RW_SECTION_A 8704K {
+			VBLOCK_A 8K
+			FW_MAIN_A(CBFS)
+			RW_FWID_A 64
+		}
+		# FIXME: b/419831198
+		# This section starts at the 16M boundary in SPI flash.
+		# PTL does not support a region crossing this boundary,
+		# because the SPI flash is memory-mapped into two non-
+		# contiguous windows.
+		RW_SECTION_B 8704K {
+			VBLOCK_B 8K
+			FW_MAIN_B(CBFS)
+			RW_FWID_B 64
+		}
 		RW_LEGACY(CBFS) 1M
-		RW_UNUSED 2M
 		# Make WP_RO region align with SPI vendor
 		# memory protected range specification.
 		WP_RO 4M {

From f2310ab35efb030a3953a709152f1d083e2eaef8 Mon Sep 17 00:00:00 2001
From: Felix Singer <felixsinger@posteo.net>
Date: Sun, 25 May 2025 14:19:33 +0200
Subject: [PATCH 1232/3886] update_submodules: Prefix commit title with
 relative path

It's common for coreboot commits to prefix the commit title with a
topic, which is often the path to the files or directories. So adjust
this commit title accordingly.

Change-Id: Ice267719a08b289b0d996fd20c993d616c812d00
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87824
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
---
 util/scripts/update_submodules | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/util/scripts/update_submodules b/util/scripts/update_submodules
index 7d36549c4d..be3273b4a2 100755
--- a/util/scripts/update_submodules
+++ b/util/scripts/update_submodules
@@ -136,7 +136,7 @@ main() {
 			cd "${TOP}" || exit 1
 			git add "${submodule}" > /dev/null 2>&1 || exit 1
 			git commit -s -F- > /dev/null 2>&1 <<-EOF
-	Update ${submodule##*/} submodule to upstream ${branch_name##*/}
+	${submodule}: Update to upstream ${branch_name##*/}
 
 	Updating from commit id ${initial_commit_id}:
 	$initial_commit_description

From f6dd8f534fc82da9b2ef9f97f51930124e5640b7 Mon Sep 17 00:00:00 2001
From: Dinesh Gehlot <digehlot@google.com>
Date: Wed, 4 Jun 2025 16:42:52 +0530
Subject: [PATCH 1233/3886] MAINTAINERS: Add Dinesh as intel/pantherlake and
 google/fatcat maintainer

Change-Id: I175d2e193265d4e472c91a25a184e5852fee6c8a
Signed-off-by: Dinesh Gehlot <digehlot@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87946
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
---
 MAINTAINERS | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/MAINTAINERS b/MAINTAINERS
index 98fe4f2ee8..f87502a74d 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -360,6 +360,7 @@ M:	Kapil Porwal <kapilporwal@google.com>
 M:	Pranava Y N <pranavayn@google.com>
 M:	Jayvik Desai <jayvik@google.com>
 M:	Avi Uday <aviuday@google.com>
+M:	Dinesh Gehlot <digehlot@google.com>
 F:	src/mainboard/google/fatcat/
 
 GOOGLE HATCH MAINBOARDS
@@ -935,6 +936,7 @@ M:	Kapil Porwal <kapilporwal@google.com>
 M:	Pranava Y N <pranavayn@google.com>
 M:	Jayvik Desai <jayvik@google.com>
 M:	Avi Uday <aviuday@google.com>
+M:	Dinesh Gehlot <digehlot@google.com>
 S:	Maintained
 F:	src/soc/intel/pantherlake/
 

From 581af941154db8113036eee3f2a5c78fd3625c61 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Micha=C5=82=20Kope=C4=87?= <michal.kopec@3mdeb.com>
Date: Tue, 11 Mar 2025 17:40:55 +0100
Subject: [PATCH 1234/3886] ec/dasharo/ec: Add DTT power and battery
 participants
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Add DTT Power and Battery participants. These are used by DTT drivers to
more efficiently split power between SoC and dGPU and determine their
power limits.

Change-Id: I1e215366a79c0dd0f8a5d54c33fc718ba6b1302b
Signed-off-by: Michał Kopeć <michal.kopec@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86820
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Sumeet R.P. <sumeet4linux@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com>
---
 src/ec/dasharo/ec/acpi/dtt.asl    | 55 +++++++++++++++++++++++++++++++
 src/ec/dasharo/ec/acpi/ec.asl     |  3 +-
 src/ec/dasharo/ec/acpi/ec_ram.asl |  3 ++
 3 files changed, 60 insertions(+), 1 deletion(-)
 create mode 100644 src/ec/dasharo/ec/acpi/dtt.asl

diff --git a/src/ec/dasharo/ec/acpi/dtt.asl b/src/ec/dasharo/ec/acpi/dtt.asl
new file mode 100644
index 0000000000..1dd85c5896
--- /dev/null
+++ b/src/ec/dasharo/ec/acpi/dtt.asl
@@ -0,0 +1,55 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <soc/dptf.h>
+
+Device (TPWR)
+{
+	Name (_HID, DPTF_TPWR_DEVICE)
+	Name (_UID, "TPWR")
+	Name (_STR, Unicode("Intel DTT Power Participant"))
+
+	Method (_STA, 0, NotSerialized)
+	{
+		Return (0x0F)
+	}
+
+	Name (PTYP, 0x11) // Device is a platform power device
+
+	Method (PSRC, 0) // Power source
+	{
+		Return (^^AC.ACFG)
+	}
+
+	Method (ARTG, 0) // Adapter rating
+	{
+		If (^^PCI0.LPCB.EC0.ECOK)
+		{
+			Return (^^PCI0.LPCB.EC0.APWR)
+		}
+		Else
+		{
+			Return (0)
+		}
+	}
+
+	Method (PBOK, 1) // Power Boss OK
+	{
+		// Notify EC to de-assert PROCHOT#
+		// Required by DTT, but N/A on this hardware, PROCHOT#
+		// is de-asserted by board logic upon AC plug-in
+	}
+}
+
+Device (TBAT)
+{
+	Name (_HID, DPTF_BAT1_DEVICE)
+	Name (_STR, Unicode("Intel DTT Battery Participant"))
+
+	Method (_STA, 0, NotSerialized)
+	{
+		Return (^^BAT0._STA)
+	}
+
+	Name (PTYP, 0x0c) // Device is a platform battery device
+	Name (CTYP, 0x02) // Hybrid Power Boost architecture
+}
diff --git a/src/ec/dasharo/ec/acpi/ec.asl b/src/ec/dasharo/ec/acpi/ec.asl
index e13c52dc39..9044de3240 100644
--- a/src/ec/dasharo/ec/acpi/ec.asl
+++ b/src/ec/dasharo/ec/acpi/ec.asl
@@ -4,9 +4,10 @@ Scope (\_SB) {
 	#include "ac.asl"
 	#include "battery.asl"
 	#include "buttons.asl"
+	#include "dasharo.asl"
+	#include "dtt.asl"
 	#include "hid.asl"
 	#include "lid.asl"
-	#include "dasharo.asl"
 }
 
 Device (\_SB.PCI0.LPCB.EC0)
diff --git a/src/ec/dasharo/ec/acpi/ec_ram.asl b/src/ec/dasharo/ec/acpi/ec_ram.asl
index 008737785b..8cd565cbd4 100644
--- a/src/ec/dasharo/ec/acpi/ec_ram.asl
+++ b/src/ec/dasharo/ec/acpi/ec_ram.asl
@@ -42,6 +42,9 @@ Field (ERAM, ByteAcc, Lock, Preserve)
 	DUT2, 8,	// Fan 2 duty
 	RPM1, 16,	// Fan 1 RPM
 	RPM2, 16,	// Fan 2 RPM
+	Offset (0xD4),
+	GPUD, 8,	// GPU D-notify level
+	APWR, 32,	// AC adapter power
 	Offset (0xD9),
 	AIRP, 8,	// Airplane mode LED
 	WINF, 8,	// Enable ACPI brightness controls

From c4eb645a0bce470aefea9b5c9cbb878095451d8a Mon Sep 17 00:00:00 2001
From: Yidi Lin <yidilin@google.com>
Date: Fri, 6 Jun 2025 08:40:25 +0800
Subject: [PATCH 1235/3886] update_submodules: Fix submodule path handling

There are two regressions introduced by CB:87823.

1. If the specified repo path has a tailing slash, `submodule` becames a
   empty variable due to `${submodule##*/}`, e.g.,

   `./util/scripts/update_submodules -R 3rdparty/arm-trusted-firmware/`

2. CB:87823 uses `git submodule status | cut -d ' ' -f 3` to retrieve
   all submodule paths. The script gets the wrong path if the format is
   wrong, e.g.,

-26c572974bcf7255930b0e9a51da3144ed0104b5 3rdparty/amd_blobs
 57ac3f74b34a3303f03deee264a1f2247c68008d 3rdparty/arm-trusted-firmware (v2.12.0-908-g57ac3f74b)
+5b7492979fc139efdfdc7f97ae53a2349798f160 3rdparty/cmocka (cmocka-1.1.5-263-g5b74929)

   The script gets the empty path for 3rdparty/amd_blobs and get
   cmocka-1.1.5-263-g5b74929 for 3rdparty/cmocka.

This patch fixes 1 by removing the tailing slash for the input directory
and fixes 2 by the below command.
   `git submodule foreach 'echo ${sm_path}'|grep -v Entering`

Note that `smp_path` is an environment variable[1] set by
`git submodule` when travelling the submodule directory.

[1]: https://git-scm.com/docs/git-submodule

Change-Id: I0016f3a867e2b4594788d71a790ff9a938121da5
Signed-off-by: Yidi Lin <yidilin@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87972
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
---
 util/scripts/update_submodules | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/util/scripts/update_submodules b/util/scripts/update_submodules
index be3273b4a2..9438e756d9 100755
--- a/util/scripts/update_submodules
+++ b/util/scripts/update_submodules
@@ -65,7 +65,7 @@ get_args() {
 			exit 0
 			;;
 		-R | --repo)
-			submodule_dirs="${1}"
+			submodule_dirs="${1%/}"
 			shift
 			if [[ ! -d "${submodule_dirs[0]}" ]]; then
 				echo "Error: ${submodule_dirs[0]} is not valid."
@@ -92,7 +92,7 @@ main() {
 	get_args "$@"
 
 	if (( ${#submodule_dirs[@]} == 0 )); then
-		readarray -t submodule_dirs < <(git submodule status | cut -d ' ' -f 3)
+		readarray -t submodule_dirs < <(git submodule foreach 'echo ${sm_path}'|grep -v Entering)
 	fi
 
 	for submodule in "${submodule_dirs[@]}"; do

From cb7d2ebe5c7f34d84d22f0e1f5cf66c5d1c08bda Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Wed, 4 Jun 2025 12:26:20 +0100
Subject: [PATCH 1236/3886] mb/starlabs/starbook/{kbl,cml,tgl}: Remove
 generic.detect from the touchpad

These boards only ever used one trackpad, so there is no need for this
to be set.

Change-Id: Ibabb663a83eea5f06c683cf2854ceed0487baf51
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87949
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
---
 src/mainboard/starlabs/starbook/variants/cml/devicetree.cb | 1 -
 src/mainboard/starlabs/starbook/variants/kbl/devicetree.cb | 1 -
 src/mainboard/starlabs/starbook/variants/tgl/devicetree.cb | 1 -
 3 files changed, 3 deletions(-)

diff --git a/src/mainboard/starlabs/starbook/variants/cml/devicetree.cb b/src/mainboard/starlabs/starbook/variants/cml/devicetree.cb
index 4d04df714f..0fb641be36 100644
--- a/src/mainboard/starlabs/starbook/variants/cml/devicetree.cb
+++ b/src/mainboard/starlabs/starbook/variants/cml/devicetree.cb
@@ -148,7 +148,6 @@ chip soc/intel/cannonlake
 				register "generic.hid"		= ""STAR0001""
 				register "generic.desc"		= ""Touchpad""
 				register "generic.irq"		= "ACPI_IRQ_LEVEL_LOW(GPP_B3_IRQ)"
-				register "generic.detect"	= "1"
 				register "hid_desc_reg_offset"	= "0x20"
 				device i2c 2c on end
 			end
diff --git a/src/mainboard/starlabs/starbook/variants/kbl/devicetree.cb b/src/mainboard/starlabs/starbook/variants/kbl/devicetree.cb
index 0f1c922acd..f80003f05a 100644
--- a/src/mainboard/starlabs/starbook/variants/kbl/devicetree.cb
+++ b/src/mainboard/starlabs/starbook/variants/kbl/devicetree.cb
@@ -75,7 +75,6 @@ chip soc/intel/skylake
 				register "generic.hid"		= ""STAR0001""
 				register "generic.desc"		= ""Touchpad""
 				register "generic.irq"		= "ACPI_IRQ_LEVEL_LOW(GPP_C23_IRQ)"
-				register "generic.detect"	= "1"
 				register "hid_desc_reg_offset"	= "0x20"
 				device i2c 2c on end
 			end
diff --git a/src/mainboard/starlabs/starbook/variants/tgl/devicetree.cb b/src/mainboard/starlabs/starbook/variants/tgl/devicetree.cb
index 69a9c1af33..9f660d5cb2 100644
--- a/src/mainboard/starlabs/starbook/variants/tgl/devicetree.cb
+++ b/src/mainboard/starlabs/starbook/variants/tgl/devicetree.cb
@@ -175,7 +175,6 @@ chip soc/intel/tigerlake
 				register "generic.hid"		= ""STAR0001""
 				register "generic.desc"		= ""Touchpad""
 				register "generic.irq"		= "ACPI_IRQ_LEVEL_LOW(GPP_C8_IRQ)"
-				register "generic.detect"	= "1"
 				register "hid_desc_reg_offset"	= "0x20"
 				device i2c 2c on end
 			end

From 40c84c25775b88c7cc2a86d1d286af4f9b703785 Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Wed, 4 Jun 2025 12:47:21 +0100
Subject: [PATCH 1237/3886] mb/starlabs/*: Tidy up the devicetree files

Nit-pick tidy up, for things like indentation and using true/false for bools.

Change-Id: Icae88494306b48695e69fd878e11e648327b443d
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87951
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
---
 .../starbook/variants/adl/devicetree.cb       | 100 +++++++++---------
 .../starbook/variants/mtl/devicetree.cb       |  66 ++++++------
 .../starbook/variants/rpl/devicetree.cb       |  82 +++++++-------
 .../starbook/variants/tgl/devicetree.cb       |  88 +++++++--------
 .../starfighter/variants/rpl/devicetree.cb    |  98 ++++++++---------
 .../starlite_adl/variants/mk_v/devicetree.cb  |  55 +++++-----
 6 files changed, 240 insertions(+), 249 deletions(-)

diff --git a/src/mainboard/starlabs/starbook/variants/adl/devicetree.cb b/src/mainboard/starlabs/starbook/variants/adl/devicetree.cb
index 3212ee584a..63d8e6a4d7 100644
--- a/src/mainboard/starlabs/starbook/variants/adl/devicetree.cb
+++ b/src/mainboard/starlabs/starbook/variants/adl/devicetree.cb
@@ -1,13 +1,13 @@
 chip soc/intel/alderlake
 	# FSP UPDs
-	register "eist_enable"			= "true"
-	register "enable_c6dram"		= "1"
-	register "energy_efficient_turbo"	= "true"
-	register "sagv"				= "SaGv_Enabled"
+	register "eist_enable"				= "true"
+	register "enable_c6dram"			= "1"
+	register "energy_efficient_turbo"		= "true"
+	register "sagv"					= "SaGv_Enabled"
 
 	# Serial I/O
 	register "serial_io_i2c_mode" = "{
-		[PchSerialIoIndexI2C0]		= PchSerialIoPci,
+		[PchSerialIoIndexI2C0]			= PchSerialIoPci,
 	}"
 
 	register "common_soc_config" = "{
@@ -17,7 +17,7 @@ chip soc/intel/alderlake
 	}"
 
 	register "serial_io_uart_mode" = "{
-		[PchSerialIoIndexUART0]		= PchSerialIoSkipInit,
+		[PchSerialIoIndexUART0]			= PchSerialIoSkipInit,
 	}"
 
 	# Power
@@ -26,7 +26,6 @@ chip soc/intel/alderlake
 	register "pch_slp_sus_min_assertion_width"	= "SLP_SUS_ASSERTION_1_S"
 	register "pch_slp_a_min_assertion_width"	= "SLP_A_ASSERTION_98_MS"
 
-	# Device Tree
 	device domain 0 on
 		device ref igpu		on
 			chip drivers/gfx/generic
@@ -84,68 +83,68 @@ chip soc/intel/alderlake
 			chip drivers/usb/acpi
 				device ref xhci_root_hub on
 					chip drivers/usb/acpi
-						register "desc"		= ""USB Type-C""
-						register "type"		= "UPC_TYPE_C_USB2_SS_SWITCH"
-						register "use_custom_pld" = "true"
-						register "custom_pld"	= "ACPI_PLD_TYPE_C(LEFT, CENTER, ACPI_PLD_GROUP(0, 0))"
+						register "desc"			= ""USB Type-C""
+						register "type"			= "UPC_TYPE_C_USB2_SS_SWITCH"
+						register "use_custom_pld"	= "true"
+						register "custom_pld"		= "ACPI_PLD_TYPE_C(LEFT, CENTER, ACPI_PLD_GROUP(0, 0))"
 						device ref usb2_port1 on end
 					end
 					chip drivers/usb/acpi
-						register "desc"		= ""USB Type-C""
-						register "type"		= "UPC_TYPE_C_USB2_SS_SWITCH"
-						register "use_custom_pld" = "true"
-						register "custom_pld"	= "ACPI_PLD_TYPE_C(LEFT, CENTER, ACPI_PLD_GROUP(0, 0))"
+						register "desc"			= ""USB Type-C""
+						register "type"			= "UPC_TYPE_C_USB2_SS_SWITCH"
+						register "use_custom_pld"	= "true"
+						register "custom_pld"		= "ACPI_PLD_TYPE_C(LEFT, CENTER, ACPI_PLD_GROUP(0, 0))"
 						device ref usb3_port3 on end
 					end
 					chip drivers/usb/acpi
-						register "desc"		= ""Left USB Type-A""
-						register "type"		= "UPC_TYPE_USB3_A"
-						register "group"	= "ACPI_PLD_GROUP(0, 1)"
+						register "desc"			= ""Left USB Type-A""
+						register "type"			= "UPC_TYPE_USB3_A"
+						register "group"		= "ACPI_PLD_GROUP(0, 1)"
 						device ref usb2_port3 on end
 					end
 					chip drivers/usb/acpi
-						register "desc"		= ""Left USB Type-A""
-						register "type"		= "UPC_TYPE_USB3_A"
-						register "group"	= "ACPI_PLD_GROUP(0, 1)"
+						register "desc"			= ""Left USB Type-A""
+						register "type"			= "UPC_TYPE_USB3_A"
+						register "group"		= "ACPI_PLD_GROUP(0, 1)"
 						device ref usb3_port1 on end
 					end
 					chip drivers/usb/acpi
-						register "desc"		= ""Right USB Type-A""
-						register "type"		= "UPC_TYPE_USB3_A"
-						register "group"	= "ACPI_PLD_GROUP(0, 2)"
+						register "desc"			= ""Right USB Type-A""
+						register "type"			= "UPC_TYPE_USB3_A"
+						register "group"		= "ACPI_PLD_GROUP(0, 2)"
 						device ref usb2_port7 on end
 					end
 					chip drivers/usb/acpi
-						register "desc"		= ""Right USB Type-A""
-						register "type"		= "UPC_TYPE_USB3_A"
-						register "group"	= "ACPI_PLD_GROUP(0, 2)"
+						register "desc"			= ""Right USB Type-A""
+						register "type"			= "UPC_TYPE_USB3_A"
+						register "group"		= "ACPI_PLD_GROUP(0, 2)"
 						device ref usb3_port2 on end
 					end
 					chip drivers/usb/acpi
-						register "desc"		= ""Internal Webcam""
-						register "type"		= "UPC_TYPE_INTERNAL"
-						register "group"	= "ACPI_PLD_GROUP(0, 3)"
+						register "desc"			= ""Internal Webcam""
+						register "type"			= "UPC_TYPE_INTERNAL"
+						register "group"		= "ACPI_PLD_GROUP(0, 3)"
 						device ref usb2_port5 on end
 					end
 					chip drivers/usb/acpi
-						register "desc"		= ""Fingerprint Reader""
-						register "type"		= "UPC_TYPE_INTERNAL"
-						register "group"	= "ACPI_PLD_GROUP(0, 4)"
+						register "desc"			= ""Fingerprint Reader""
+						register "type"			= "UPC_TYPE_INTERNAL"
+						register "group"		= "ACPI_PLD_GROUP(0, 4)"
 						device ref usb2_port6 on end
 					end
 					chip drivers/usb/acpi
-						register "desc"		= ""USB 2.0 Hub""
-						register "type"		= "UPC_TYPE_HUB"
-						register "group"	= "ACPI_PLD_GROUP(0, 5)"
+						register "desc"			= ""USB 2.0 Hub""
+						register "type"			= "UPC_TYPE_HUB"
+						register "group"		= "ACPI_PLD_GROUP(0, 5)"
 						device ref usb2_port4 on end
 					end
 					chip drivers/usb/acpi
-						register "desc"		= ""Internal Bluetooth""
-						register "type"		= "UPC_TYPE_INTERNAL"
-						register "group"	= "ACPI_PLD_GROUP(0, 6)"
-						register "is_intel_bluetooth" = "1"
-						register "enable_gpio"	= "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A13)"
-						register "reset_gpio"	= "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A13)"
+						register "desc"			= ""Internal Bluetooth""
+						register "type"			= "UPC_TYPE_INTERNAL"
+						register "group"		= "ACPI_PLD_GROUP(0, 6)"
+						register "is_intel_bluetooth"	= "1"
+						register "enable_gpio"		= "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A13)"
+						register "reset_gpio"		= "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A13)"
 						device ref usb2_port10 on end
 					end
 				end
@@ -187,9 +186,9 @@ chip soc/intel/alderlake
 				register "reset_gpio"			= "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_H2)"
 				register "srcclk_pin"			= "2"
 				register "add_acpi_dma_property"	= "true"
-				register "skip_on_off_support"		= "1"
+				register "skip_on_off_support"		= "true"
 				register "ext_pm_support"		= "ACPI_PCIE_RP_EMIT_ALL"
-				register "use_rp_mutex"			= "1"
+				register "use_rp_mutex"			= "true"
 				device generic 0 on end
 			end
 		end
@@ -207,15 +206,16 @@ chip soc/intel/alderlake
 									"SlotLengthLong"
 									"M.2/M 2280"
 									"SlotDataBusWidth4X"
+
 			chip soc/intel/common/block/pcie/rtd3
 				register "enable_gpio"			= "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D16)"
 				register "reset_gpio"			= "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_H0)"
 				register "srcclk_pin"			= "1"
-				register "is_storage"			= "1"
-				register "add_acpi_dma_property"	= "1"
-				register "skip_on_off_support"		= "1"
+				register "is_storage"			= "true"
+				register "add_acpi_dma_property"	= "true"
+				register "skip_on_off_support"		= "true"
 				register "ext_pm_support"		= "ACPI_PCIE_RP_EMIT_ALL"
-				register "use_rp_mutex"			= "1"
+				register "use_rp_mutex"			= "true"
 				device generic 0 on end
 			end
 		end
@@ -267,8 +267,8 @@ chip soc/intel/alderlake
 			subsystemid 0x1e50 0x7007
 			register "pch_hda_sdi_enable[0]"		= "true"
 			register "pch_hda_dsp_enable"			= "true"
-			register "pch_hda_audio_link_hda_enable"	= "1"
-			register "pch_hda_idisp_codec_enable"		= "1"
+			register "pch_hda_audio_link_hda_enable"	= "true"
+			register "pch_hda_idisp_codec_enable"		= "true"
 			register "pch_hda_idisp_link_frequency"		= "HDA_LINKFREQ_96MHZ"
 			register "pch_hda_idisp_link_tmode"		= "HDA_TMODE_8T"
 		end
diff --git a/src/mainboard/starlabs/starbook/variants/mtl/devicetree.cb b/src/mainboard/starlabs/starbook/variants/mtl/devicetree.cb
index 11b969fd26..dbb7dca439 100644
--- a/src/mainboard/starlabs/starbook/variants/mtl/devicetree.cb
+++ b/src/mainboard/starlabs/starbook/variants/mtl/devicetree.cb
@@ -24,7 +24,6 @@ chip soc/intel/meteorlake
 	register "pch_slp_sus_min_assertion_width"	= "SLP_SUS_ASSERTION_1_S"
 	register "pch_slp_a_min_assertion_width"	= "SLP_A_ASSERTION_98_MS"
 
-	# Device Tree
 	device domain 0 on
 		device ref igpu		on
 			chip drivers/gfx/generic
@@ -107,62 +106,62 @@ chip soc/intel/meteorlake
 			chip drivers/usb/acpi
 				device ref xhci_root_hub on
 					chip drivers/usb/acpi
-						register "desc"		= ""Back USB Type-C""
-						register "type"		= "UPC_TYPE_C_USB2_SS_SWITCH"
-						register "use_custom_pld" = "true"
-						register "custom_pld"	= "ACPI_PLD_TYPE_C(LEFT, CENTER, ACPI_PLD_GROUP(0, 0))"
+						register "desc"			= ""Back USB Type-C""
+						register "type"			= "UPC_TYPE_C_USB2_SS_SWITCH"
+						register "use_custom_pld"	= "true"
+						register "custom_pld"		= "ACPI_PLD_TYPE_C(LEFT, CENTER, ACPI_PLD_GROUP(0, 0))"
 						device ref usb2_port1 on end
 					end
 					chip drivers/usb/acpi
-						register "desc"		= ""Front USB Type-C""
-						register "type"		= "UPC_TYPE_C_USB2_SS_SWITCH"
+						register "desc"			= ""Front USB Type-C""
+						register "type"			= "UPC_TYPE_C_USB2_SS_SWITCH"
 						register "use_custom_pld"	= "true"
-						register "custom_pld"	= "ACPI_PLD_TYPE_C(LEFT, CENTER, ACPI_PLD_GROUP(0, 1))"
+						register "custom_pld"		= "ACPI_PLD_TYPE_C(LEFT, CENTER, ACPI_PLD_GROUP(0, 1))"
 						device ref usb2_port3 on end
 					end
 					chip drivers/usb/acpi
-						register "desc"		= ""Left USB Type-A""
-						register "type"		= "UPC_TYPE_USB3_A"
-						register "group"	= "ACPI_PLD_GROUP(0, 2)"
+						register "desc"			= ""Left USB Type-A""
+						register "type"			= "UPC_TYPE_USB3_A"
+						register "group"		= "ACPI_PLD_GROUP(0, 2)"
 						device ref usb2_port2 on end
 					end
 					chip drivers/usb/acpi
-						register "desc"		= ""Left USB Type-A""
-						register "type"		= "UPC_TYPE_USB3_A"
-						register "group"	= "ACPI_PLD_GROUP(0, 2)"
+						register "desc"			= ""Left USB Type-A""
+						register "type"			= "UPC_TYPE_USB3_A"
+						register "group"		= "ACPI_PLD_GROUP(0, 2)"
 						device ref usb3_port1 on end
 					end
 					chip drivers/usb/acpi
-						register "desc"		= ""Right Rear USB Type-A""
-						register "type"		= "UPC_TYPE_USB3_A"
-						register "group"	= "ACPI_PLD_GROUP(0, 3)"
+						register "desc"			= ""Right Rear USB Type-A""
+						register "type"			= "UPC_TYPE_USB3_A"
+						register "group"		= "ACPI_PLD_GROUP(0, 3)"
 						device ref usb2_port7 on end
 					end
 					chip drivers/usb/acpi
-						register "desc"		= ""Right Rear USB Type-A""
-						register "type"		= "UPC_TYPE_USB3_A"
-						register "group"	= "ACPI_PLD_GROUP(0, 3)"
+						register "desc"			= ""Right Rear USB Type-A""
+						register "type"			= "UPC_TYPE_USB3_A"
+						register "group"		= "ACPI_PLD_GROUP(0, 3)"
 						device ref usb3_port2 on end
 					end
 					chip drivers/usb/acpi
-						register "desc"		= ""Internal Webcam""
-						register "type"		= "UPC_TYPE_INTERNAL"
-						register "group"	= "ACPI_PLD_GROUP(0, 4)"
+						register "desc"			= ""Internal Webcam""
+						register "type"			= "UPC_TYPE_INTERNAL"
+						register "group"		= "ACPI_PLD_GROUP(0, 4)"
 						device ref usb2_port5 on end
 					end
 					chip drivers/usb/acpi
-						register "desc"		= ""USB 2.0 Hub""
-						register "type"		= "UPC_TYPE_HUB"
-						register "group"	= "ACPI_PLD_GROUP(0, 5)"
+						register "desc"			= ""USB 2.0 Hub""
+						register "type"			= "UPC_TYPE_HUB"
+						register "group"		= "ACPI_PLD_GROUP(0, 5)"
 						device ref usb2_port8 on end
 					end
 					chip drivers/usb/acpi
-						register "desc"		= ""Internal Bluetooth""
-						register "type"		= "UPC_TYPE_INTERNAL"
-						register "is_intel_bluetooth" = "true"
-						register "enable_gpio"	= "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B18)"
-						register "reset_gpio"	= "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B18)"
-						register "group"	= "ACPI_PLD_GROUP(0, 6)"
+						register "desc"			= ""Internal Bluetooth""
+						register "type"			= "UPC_TYPE_INTERNAL"
+						register "is_intel_bluetooth"	= "true"
+						register "enable_gpio"		= "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B18)"
+						register "reset_gpio"		= "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B18)"
+						register "group"		= "ACPI_PLD_GROUP(0, 6)"
 						device ref usb2_port10 on end
 					end
 				end
@@ -188,6 +187,7 @@ chip soc/intel/meteorlake
 				.pcie_rp_aspm				= ASPM_L0S_L1,
 				.PcieRpL1Substates			= L1_SS_L1_2,
 			}"
+
 			smbios_slot_desc				"SlotTypePciExpressGen3X1"
 									"SlotLengthShort"
 									"M.2/M 2230"
@@ -211,8 +211,8 @@ chip soc/intel/meteorlake
 				.flags					= PCIE_RP_LTR | PCIE_RP_AER,
 				.pcie_rp_aspm				= ASPM_L0S_L1,
 				.PcieRpL1Substates			= L1_SS_L1_2,
-
 			}"
+
 			smbios_slot_desc				"SlotTypeM2Socket3"
 									"SlotLengthLong"
 									"M.2/M 2280"
diff --git a/src/mainboard/starlabs/starbook/variants/rpl/devicetree.cb b/src/mainboard/starlabs/starbook/variants/rpl/devicetree.cb
index 7637af896b..8a7652f278 100644
--- a/src/mainboard/starlabs/starbook/variants/rpl/devicetree.cb
+++ b/src/mainboard/starlabs/starbook/variants/rpl/devicetree.cb
@@ -28,7 +28,6 @@ chip soc/intel/alderlake
 	register "pch_slp_sus_min_assertion_width"	= "SLP_SUS_ASSERTION_1_S"
 	register "pch_slp_a_min_assertion_width"	= "SLP_A_ASSERTION_98_MS"
 
-	# Device Tree
 	device domain 0 on
 		device ref igpu		on
 			chip drivers/gfx/generic
@@ -70,15 +69,16 @@ chip soc/intel/alderlake
 									"SlotLengthLong"
 									"M.2/M 2280"
 									"SlotDataBusWidth4X"
+
 			chip soc/intel/common/block/pcie/rtd3
 				register "enable_gpio"			= "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D14)"
 				register "reset_gpio"			= "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_F20)"
 				register "srcclk_pin"			= "4"
-				register "is_storage"			= "1"
-				register "add_acpi_dma_property"	= "1"
-				register "skip_on_off_support"		= "1"
+				register "is_storage"			= "true"
+				register "add_acpi_dma_property"	= "true"
+				register "skip_on_off_support"		= "true"
 				register "ext_pm_support"		= "ACPI_PCIE_RP_EMIT_ALL"
-				register "use_rp_mutex"			= "1"
+				register "use_rp_mutex"			= "true"
 				device generic 0 on end
 			end
 		end
@@ -132,66 +132,65 @@ chip soc/intel/alderlake
 			chip drivers/usb/acpi
 				device ref xhci_root_hub on
 					chip drivers/usb/acpi
-						register "desc"		= ""USB Type-C""
-						register "type"		= "UPC_TYPE_C_USB2_SS_SWITCH"
-						register "use_custom_pld" = "true"
-						register "custom_pld"	= "ACPI_PLD_TYPE_C(LEFT, CENTER, ACPI_PLD_GROUP(0, 0))"
+						register "desc"			= ""USB Type-C""
+						register "type"			= "UPC_TYPE_C_USB2_SS_SWITCH"
+						register "use_custom_pld"	= "true"
+						register "custom_pld"		= "ACPI_PLD_TYPE_C(LEFT, CENTER, ACPI_PLD_GROUP(0, 0))"
 						device ref usb2_port1 on end
 					end
 					chip drivers/usb/acpi
-						register "desc"		= ""Left USB Type-A""
-						register "type"		= "UPC_TYPE_USB3_A"
-						register "group"	= "ACPI_PLD_GROUP(0, 1)"
+						register "desc"			= ""Left USB Type-A""
+						register "type"			= "UPC_TYPE_USB3_A"
+						register "group"		= "ACPI_PLD_GROUP(0, 1)"
 						device ref usb2_port3 on end
 					end
 					chip drivers/usb/acpi
-						register "desc"		= ""Left USB Type-A""
-						register "type"		= "UPC_TYPE_USB3_A"
-						register "group"	= "ACPI_PLD_GROUP(0, 1)"
+						register "desc"			= ""Left USB Type-A""
+						register "type"			= "UPC_TYPE_USB3_A"
+						register "group"		= "ACPI_PLD_GROUP(0, 1)"
 						device ref usb3_port1 on end
 					end
 					chip drivers/usb/acpi
-						register "desc"		= ""Right USB Type-A""
-						register "type"		= "UPC_TYPE_USB3_A"
-						register "group"	= "ACPI_PLD_GROUP(0, 2)"
+						register "desc"			= ""Right USB Type-A""
+						register "type"			= "UPC_TYPE_USB3_A"
+						register "group"		= "ACPI_PLD_GROUP(0, 2)"
 						device ref usb2_port7 on end
 					end
 					chip drivers/usb/acpi
-						register "desc"		= ""Right USB Type-A""
-						register "type"		= "UPC_TYPE_USB3_A"
-						register "group"	= "ACPI_PLD_GROUP(0, 2)"
+						register "desc"			= ""Right USB Type-A""
+						register "type"			= "UPC_TYPE_USB3_A"
+						register "group"		= "ACPI_PLD_GROUP(0, 2)"
 						device ref usb3_port2 on end
 					end
 					chip drivers/usb/acpi
-						register "desc"		= ""Internal Webcam""
-						register "type"		= "UPC_TYPE_INTERNAL"
-						register "group"	= "ACPI_PLD_GROUP(0, 3)"
+						register "desc"			= ""Internal Webcam""
+						register "type"			= "UPC_TYPE_INTERNAL"
+						register "group"		= "ACPI_PLD_GROUP(0, 3)"
 						device ref usb2_port5 on end
 					end
 					chip drivers/usb/acpi
-						register "desc"		= ""Fingerprint Reader""
-						register "type"		= "UPC_TYPE_INTERNAL"
-						register "group"	= "ACPI_PLD_GROUP(0, 4)"
+						register "desc"			= ""Fingerprint Reader""
+						register "type"			= "UPC_TYPE_INTERNAL"
+						register "group"		= "ACPI_PLD_GROUP(0, 4)"
 						device ref usb2_port6 on end
 					end
 					chip drivers/usb/acpi
-						register "desc"		= ""USB 2.0 Hub""
-						register "type"		= "UPC_TYPE_HUB"
-						register "group"	= "ACPI_PLD_GROUP(0, 5)"
+						register "desc"			= ""USB 2.0 Hub""
+						register "type"			= "UPC_TYPE_HUB"
+						register "group"		= "ACPI_PLD_GROUP(0, 5)"
 						device ref usb2_port4 on end
 					end
 					chip drivers/usb/acpi
-						register "desc"		= ""Internal Bluetooth""
-						register "type"		= "UPC_TYPE_INTERNAL"
-						register "group"	= "ACPI_PLD_GROUP(0, 6)"
-						register "is_intel_bluetooth" = "1"
-						register "enable_gpio"	= "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A13)"
-						register "reset_gpio"	= "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A13)"
+						register "desc"			= ""Internal Bluetooth""
+						register "type"			= "UPC_TYPE_INTERNAL"
+						register "group"		= "ACPI_PLD_GROUP(0, 6)"
+						register "is_intel_bluetooth"	= "1"
+						register "enable_gpio"		= "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A13)"
+						register "reset_gpio"		= "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A13)"
 						device ref usb2_port10 on end
 					end
 				end
 			end
-
 		end
 		device ref i2c0		on
 			chip drivers/i2c/hid
@@ -215,6 +214,7 @@ chip soc/intel/alderlake
 				.pcie_rp_aspm				= ASPM_L0S_L1,
 				.PcieRpL1Substates			= L1_SS_L1_2,
 			}"
+
 			smbios_slot_desc				"SlotTypePciExpressGen3X1"
 									"SlotLengthShort"
 									"M.2/M 2230"
@@ -223,10 +223,10 @@ chip soc/intel/alderlake
 				register "enable_gpio"			= "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E3)"
 				register "reset_gpio"			= "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_H2)"
 				register "srcclk_pin"			= "2"
-				register "skip_on_off_support"		= "1"
 				register "add_acpi_dma_property"	= "true"
+				register "skip_on_off_support"		= "true"
 				register "ext_pm_support"		= "ACPI_PCIE_RP_EMIT_ALL"
-				register "use_rp_mutex"			= "1"
+				register "use_rp_mutex"			= "true"
 				device generic 0 on end
 			end
 		end
@@ -278,8 +278,8 @@ chip soc/intel/alderlake
 			subsystemid 0x1e50 0x7007
 			register "pch_hda_sdi_enable[0]"		= "true"
 			register "pch_hda_dsp_enable"			= "true"
-			register "pch_hda_audio_link_hda_enable"	= "1"
-			register "pch_hda_idisp_codec_enable"		= "1"
+			register "pch_hda_audio_link_hda_enable"	= "true"
+			register "pch_hda_idisp_codec_enable"		= "true"
 			register "pch_hda_idisp_link_frequency"		= "HDA_LINKFREQ_96MHZ"
 			register "pch_hda_idisp_link_tmode"		= "HDA_TMODE_8T"
 		end
diff --git a/src/mainboard/starlabs/starbook/variants/tgl/devicetree.cb b/src/mainboard/starlabs/starbook/variants/tgl/devicetree.cb
index 9f660d5cb2..3808aca17b 100644
--- a/src/mainboard/starlabs/starbook/variants/tgl/devicetree.cb
+++ b/src/mainboard/starlabs/starbook/variants/tgl/devicetree.cb
@@ -1,26 +1,15 @@
 chip soc/intel/tigerlake
 	# FSP UPDs
-	register "eist_enable"			= "true"
-	register "enable_c6dram"		= "1"
-	register "CnviBtCore"			= "true"
-	register "CnviBtAudioOffload"		= "1"
-	register "SaGv"				= "SaGv_Enabled"
-
-	# Graphics
-	# Not used but timings left for reference
-	# register "panel_cfg" = "{
-	#	.up_delay_ms			= 2000,				// T3
-	#	.backlight_on_delay_ms		= 0,				// T7
-	#	.backlight_off_delay_ms		= 2000,				// T9
-	#	.down_delay_ms			= 500,				// T10
-	#	.cycle_delay_ms			= 500,				// T12
-	#	.backlight_pwm_hz		= 200,				// PWM
-	# }"
+	register "eist_enable"				= "true"
+	register "enable_c6dram"			= "true"
+	register "CnviBtCore"				= "true"
+	register "CnviBtAudioOffload"			= "true"
+	register "SaGv"					= "SaGv_Enabled"
 
 	# Serial I/O
 	register "SerialIoI2cMode" = "{
-		[PchSerialIoIndexI2C0]		= PchSerialIoPci,
-		[PchSerialIoIndexI2C4]		= PchSerialIoSkipInit,
+		[PchSerialIoIndexI2C0]			= PchSerialIoPci,
+		[PchSerialIoIndexI2C4]			= PchSerialIoSkipInit,
 	}"
 
 	register "common_soc_config" = "{
@@ -30,14 +19,14 @@ chip soc/intel/tigerlake
 	}"
 
 	register "SerialIoUartMode" = "{
-		[PchSerialIoIndexUART2]		= PchSerialIoSkipInit,
+		[PchSerialIoIndexUART2]			= PchSerialIoSkipInit,
 	}"
 
 	# Power
-	register "PchPmSlpS3MinAssert"		= "2"				# 1ms
-	register "PchPmSlpS4MinAssert"		= "3"				# 3s
-	register "PchPmSlpSusMinAssert"		= "3"				# 1s
-	register "PchPmSlpAMinAssert"		= "3"				# 98ms
+	register "PchPmSlpS3MinAssert"			= "2"	# 1ms
+	register "PchPmSlpS4MinAssert"			= "3"	# 3s
+	register "PchPmSlpSusMinAssert"			= "3"	# 1s
+	register "PchPmSlpAMinAssert"			= "3"	# 98ms
 
 	# Enable the correct decode ranges on the LPC bus.
 	register "lpc_ioe"			= "LPC_IOE_EC_4E_4F |
@@ -109,54 +98,54 @@ chip soc/intel/tigerlake
 			chip drivers/usb/acpi
 				device ref xhci_root_hub on
 					chip drivers/usb/acpi
-						register "desc"		= ""USB Type-C""
-						register "type"		= "UPC_TYPE_C_USB2_SS_SWITCH"
-						register "group"	= "ACPI_PLD_GROUP(0, 0)"
+						register "desc"			= ""USB Type-C""
+						register "type"			= "UPC_TYPE_C_USB2_SS_SWITCH"
+						register "group"		= "ACPI_PLD_GROUP(0, 0)"
 						device ref usb2_port1 on end
 					end
 					chip drivers/usb/acpi
-						register "desc"		= ""Left USB Type-A""
-						register "type"		= "UPC_TYPE_USB3_A"
-						register "group"	= "ACPI_PLD_GROUP(0, 1)"
+						register "desc"			= ""Left USB Type-A""
+						register "type"			= "UPC_TYPE_USB3_A"
+						register "group"		= "ACPI_PLD_GROUP(0, 1)"
 						device ref usb2_port2 on end
 					end
 					chip drivers/usb/acpi
-						register "desc"		= ""Left USB Type-A""
-						register "type"		= "UPC_TYPE_USB3_A"
-						register "group"	= "ACPI_PLD_GROUP(0, 1)"
+						register "desc"			= ""Left USB Type-A""
+						register "type"			= "UPC_TYPE_USB3_A"
+						register "group"		= "ACPI_PLD_GROUP(0, 1)"
 						device ref usb3_port1 on end
 					end
 					chip drivers/usb/acpi
-						register "desc"		= ""Right USB Type-A""
-						register "type"		= "UPC_TYPE_USB3_A"
-						register "group"	= "ACPI_PLD_GROUP(0, 2)"
+						register "desc"			= ""Right USB Type-A""
+						register "type"			= "UPC_TYPE_USB3_A"
+						register "group"		= "ACPI_PLD_GROUP(0, 2)"
 						device ref usb2_port3 on end
 					end
 					chip drivers/usb/acpi
-						register "desc"		= ""Right USB Type-A""
-						register "type"		= "UPC_TYPE_USB3_A"
-						register "group"	= "ACPI_PLD_GROUP(0, 2)"
+						register "desc"			= ""Right USB Type-A""
+						register "type"			= "UPC_TYPE_USB3_A"
+						register "group"		= "ACPI_PLD_GROUP(0, 2)"
 						device ref usb3_port2 on end
 					end
 					chip drivers/usb/acpi
-						register "desc"		= ""Internal Webcam""
-						register "type"		= "UPC_TYPE_INTERNAL"
-						register "group"	= "ACPI_PLD_GROUP(0, 3)"
+						register "desc"			= ""Internal Webcam""
+						register "type"			= "UPC_TYPE_INTERNAL"
+						register "group"		= "ACPI_PLD_GROUP(0, 3)"
 						device ref usb2_port4 on end
 					end
 					chip drivers/usb/acpi
-						register "desc"		= ""USB 2.0 Hub""
-						register "type"		= "UPC_TYPE_HUB"
-						register "group"	= "ACPI_PLD_GROUP(0, 4)"
+						register "desc"			= ""USB 2.0 Hub""
+						register "type"			= "UPC_TYPE_HUB"
+						register "group"		= "ACPI_PLD_GROUP(0, 4)"
 						device ref usb2_port6 on end
 					end
 					chip drivers/usb/acpi
-						register "desc"		= ""Internal Bluetooth""
-						register "type"		= "UPC_TYPE_INTERNAL"
-						register "group"	= "ACPI_PLD_GROUP(0, 5)"
-						register "is_intel_bluetooth" = "1"
+						register "desc"			= ""Internal Bluetooth""
+						register "type"			= "UPC_TYPE_INTERNAL"
+						register "group"		= "ACPI_PLD_GROUP(0, 5)"
+						register "is_intel_bluetooth"	= "1"
 						register "cnvi_bt_audio_offload" = "1"
-						register "enable_gpio"	= "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(CNV_BTEN)"
+						register "enable_gpio"		= "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(CNV_BTEN)"
 						device ref usb2_port10 on end
 					end
 				end
@@ -217,6 +206,7 @@ chip soc/intel/tigerlake
 			register "gen1_dec"			= "0x00040069"
 			register "gen2_dec"			= "0x00fc0201"
 			register "gen3_dec"			= "0x000c0081"
+
 			chip drivers/pc80/tpm
 				device pnp 0c31.0 on end
 			end
diff --git a/src/mainboard/starlabs/starfighter/variants/rpl/devicetree.cb b/src/mainboard/starlabs/starfighter/variants/rpl/devicetree.cb
index a9221cae48..c82bc9aaf0 100644
--- a/src/mainboard/starlabs/starfighter/variants/rpl/devicetree.cb
+++ b/src/mainboard/starlabs/starfighter/variants/rpl/devicetree.cb
@@ -76,11 +76,11 @@ chip soc/intel/alderlake
 				register "enable_gpio"			= "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D14)"
 				register "reset_gpio"			= "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_F20)"
 				register "srcclk_pin"			= "4"
-				register "is_storage"			= "1"
-				register "add_acpi_dma_property"	= "1"
-				register "skip_on_off_support"		= "1"
+				register "is_storage"			= "true"
+				register "add_acpi_dma_property"	= "true"
+				register "skip_on_off_support"		= "true"
 				register "ext_pm_support"		= "ACPI_PCIE_RP_EMIT_ALL"
-				register "use_rp_mutex"			= "1"
+				register "use_rp_mutex"			= "true"
 				device generic 0 on end
 			end
 		end
@@ -90,15 +90,15 @@ chip soc/intel/alderlake
 			chip drivers/usb/acpi
 				device ref tcss_root_hub on
 					chip drivers/usb/acpi
-						register "desc" = ""Left Back USB Type-C""
-						register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
+						register "desc"			= ""Left Back USB Type-C""
+						register "type"			= "UPC_TYPE_C_USB2_SS_SWITCH"
 						register "use_custom_pld"	= "true"
 						register "custom_pld"		= "ACPI_PLD_TYPE_C(LEFT, CENTER, ACPI_PLD_GROUP(0, 0))"
 						device ref tcss_usb3_port1 on end
 					end
 					chip drivers/usb/acpi
-						register "desc" = ""Left Front USB Type-C""
-						register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
+						register "desc"			= ""Left Front USB Type-C""
+						register "type"			= "UPC_TYPE_C_USB2_SS_SWITCH"
 						register "use_custom_pld"	= "true"
 						register "custom_pld"		= "ACPI_PLD_TYPE_C(LEFT, CENTER, ACPI_PLD_GROUP(0, 1))"
 						device ref tcss_usb3_port2 on end
@@ -145,55 +145,55 @@ chip soc/intel/alderlake
 			chip drivers/usb/acpi
 				device ref xhci_root_hub on
 					chip drivers/usb/acpi
-						register "desc"		= ""Left Back USB Type-C""
-						register "type"		= "UPC_TYPE_C_USB2_SS_SWITCH"
-						register "use_custom_pld" = "true"
-						register "custom_pld"	= "ACPI_PLD_TYPE_C(LEFT, CENTER, ACPI_PLD_GROUP(0, 0))"
+						register "desc"			= ""Left Back USB Type-C""
+						register "type"			= "UPC_TYPE_C_USB2_SS_SWITCH"
+						register "use_custom_pld"	= "true"
+						register "custom_pld"		= "ACPI_PLD_TYPE_C(LEFT, CENTER, ACPI_PLD_GROUP(0, 0))"
 						device ref usb2_port1 on end
 					end
 					chip drivers/usb/acpi
-						register "desc"		= ""Left Front USB Type-C""
-						register "type"		= "UPC_TYPE_C_USB2_SS_SWITCH"
+						register "desc"			= ""Left Front USB Type-C""
+						register "type"			= "UPC_TYPE_C_USB2_SS_SWITCH"
 						register "use_custom_pld"	= "true"
-						register "custom_pld"	= "ACPI_PLD_TYPE_C(LEFT, CENTER, ACPI_PLD_GROUP(0, 1))"
+						register "custom_pld"		= "ACPI_PLD_TYPE_C(LEFT, CENTER, ACPI_PLD_GROUP(0, 1))"
 						device ref usb2_port2 on end
 					end
 					chip drivers/usb/acpi
-						register "desc"		= ""Left USB Type-A""
-						register "type"		= "UPC_TYPE_USB3_A"
-						register "group"	= "ACPI_PLD_GROUP(0, 2)"
+						register "desc"			= ""Left USB Type-A""
+						register "type"			= "UPC_TYPE_USB3_A"
+						register "group"		= "ACPI_PLD_GROUP(0, 2)"
 						device ref usb2_port3 on end
 					end
 					chip drivers/usb/acpi
-						register "desc"		= ""Left USB Type-A""
-						register "type"		= "UPC_TYPE_USB3_A"
-						register "group"	= "ACPI_PLD_GROUP(0, 2)"
+						register "desc"			= ""Left USB Type-A""
+						register "type"			= "UPC_TYPE_USB3_A"
+						register "group"		= "ACPI_PLD_GROUP(0, 2)"
 						device ref usb3_port1 on end
 					end
 					chip drivers/usb/acpi
-						register "desc"		= ""USB 3.0 Hub""
-						register "type"		= "UPC_TYPE_HUB"
-						register "group"	= "ACPI_PLD_GROUP(0, 3)"
+						register "desc"			= ""USB 3.0 Hub""
+						register "type"			= "UPC_TYPE_HUB"
+						register "group"		= "ACPI_PLD_GROUP(0, 3)"
 						device ref usb2_port6 on end
 					end
 					chip drivers/usb/acpi
-						register "desc"		= ""USB 3.0 Hub""
-						register "type"		= "UPC_TYPE_HUB"
-						register "group"	= "ACPI_PLD_GROUP(0, 3)"
+						register "desc"			= ""USB 3.0 Hub""
+						register "type"			= "UPC_TYPE_HUB"
+						register "group"		= "ACPI_PLD_GROUP(0, 3)"
 						device ref usb3_port2 on end
 					end
 					chip drivers/usb/acpi
-						register "desc"		= ""Internal Webcam""
-						register "group"	= "ACPI_PLD_GROUP(0, 4)"
+						register "desc"			= ""Internal Webcam""
+						register "group"		= "ACPI_PLD_GROUP(0, 4)"
 						device ref usb2_port5 on end
 					end
 					chip drivers/usb/acpi
-						register "desc"		= ""Internal Bluetooth""
-						register "type"		= "UPC_TYPE_INTERNAL"
-						register "group"	= "ACPI_PLD_GROUP(0, 5)"
-						register "is_intel_bluetooth" = "1"
-						register "enable_gpio"	= "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A13)"
-						register "reset_gpio"	= "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A13)"
+						register "desc"			= ""Internal Bluetooth""
+						register "type"			= "UPC_TYPE_INTERNAL"
+						register "group"		= "ACPI_PLD_GROUP(0, 5)"
+						register "is_intel_bluetooth"	= "1"
+						register "enable_gpio"		= "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A13)"
+						register "reset_gpio"		= "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A13)"
 						device ref usb2_port10 on end
 					end
 				end
@@ -201,15 +201,15 @@ chip soc/intel/alderlake
 		end
 		device ref i2c0		on
 			chip drivers/i2c/hid
-				register "generic.hid"			= ""STAR0001""
-				register "generic.desc"			= ""Touchpad""
-				register "generic.irq"			= "ACPI_IRQ_LEVEL_LOW(GPP_D11_IRQ)"
-				register "hid_desc_reg_offset"		= "0x20"
+				register "generic.hid"		= ""STAR0001""
+				register "generic.desc"		= ""Touchpad""
+				register "generic.irq"		= "ACPI_IRQ_LEVEL_LOW(GPP_D11_IRQ)"
+				register "hid_desc_reg_offset"	= "0x20"
 				device i2c 2c on end
 			end
 		end
 		device ref shared_sram	on  end
-		device ref pcie_rp5	on			# WiFi
+		device ref pcie_rp5	on				# WiFi
 			chip drivers/wifi/generic
 				register "enable_cnvi_ddr_rfim"		= "true"
 				device generic 0 on end
@@ -230,9 +230,9 @@ chip soc/intel/alderlake
 				register "reset_gpio"			= "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_H2)"
 				register "srcclk_pin"			= "2"
 				register "add_acpi_dma_property"	= "true"
-				register "skip_on_off_support"		= "1"
+				register "skip_on_off_support"		= "true"
 				register "ext_pm_support"		= "ACPI_PCIE_RP_EMIT_ALL"
-				register "use_rp_mutex"			= "1"
+				register "use_rp_mutex"			= "true"
 				device generic 0 on end
 			end
 		end
@@ -256,11 +256,11 @@ chip soc/intel/alderlake
 				register "enable_gpio"			= "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D16)"
 				register "reset_gpio"			= "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_H0)"
 				register "srcclk_pin"			= "1"
-				register "is_storage"			= "1"
-				register "add_acpi_dma_property"	= "1"
-				register "skip_on_off_support"		= "1"
+				register "is_storage"			= "true"
+				register "add_acpi_dma_property"	= "true"
+				register "skip_on_off_support"		= "true"
 				register "ext_pm_support"		= "ACPI_PCIE_RP_EMIT_ALL"
-				register "use_rp_mutex"			= "1"
+				register "use_rp_mutex"			= "true"
 				device generic 0 on end
 			end
 		end
@@ -315,10 +315,10 @@ chip soc/intel/alderlake
 		end
 		device ref hda		on
 			subsystemid 0x10ec 0x1200
-			register "pch_hda_sdi_enable[0]"		= "1"
+			register "pch_hda_sdi_enable[0]"		= "true"
 			register "pch_hda_dsp_enable"			= "true"
-			register "pch_hda_audio_link_hda_enable"	= "1"
-			register "pch_hda_idisp_codec_enable"		= "1"
+			register "pch_hda_audio_link_hda_enable"	= "true"
+			register "pch_hda_idisp_codec_enable"		= "true"
 			register "pch_hda_idisp_link_frequency"		= "HDA_LINKFREQ_96MHZ"
 			register "pch_hda_idisp_link_tmode"		= "HDA_TMODE_8T"
 		end
diff --git a/src/mainboard/starlabs/starlite_adl/variants/mk_v/devicetree.cb b/src/mainboard/starlabs/starlite_adl/variants/mk_v/devicetree.cb
index d9996caf29..bb9ab534b2 100644
--- a/src/mainboard/starlabs/starlite_adl/variants/mk_v/devicetree.cb
+++ b/src/mainboard/starlabs/starlite_adl/variants/mk_v/devicetree.cb
@@ -60,30 +60,30 @@ chip soc/intel/alderlake
 				device generic 0 on end
 			end
 
-			register "ddi_portA_config"			= "1"
+			register "ddi_portA_config"		= "1"
 			register "ddi_ports_config" = "{
-				[DDI_PORT_A]				= DDI_ENABLE_HPD | DDI_ENABLE_DDC,
-				[DDI_PORT_B]				= DDI_ENABLE_HPD | DDI_ENABLE_DDC,
+				[DDI_PORT_A]			= DDI_ENABLE_HPD | DDI_ENABLE_DDC,
+				[DDI_PORT_B]			= DDI_ENABLE_HPD | DDI_ENABLE_DDC,
 			}"
 		end
 		device ref gna		on  end
 		device ref xhci		on
-			# Bottom USB 3.0 Type-C				3289 mil
-			register "usb2_ports[0]"			= "USB2_PORT_SHORT(OC_SKIP)"
-			register "usb3_ports[2]"			= "USB3_PORT_DEFAULT(OC_SKIP)"
+			# Bottom USB 3.0 Type-C			3289 mil
+			register "usb2_ports[0]"		= "USB2_PORT_SHORT(OC_SKIP)"
+			register "usb3_ports[2]"		= "USB3_PORT_DEFAULT(OC_SKIP)"
 
-			# Top USB 3.0 Type-C				4237 mil
-			register "usb2_ports[1]"			= "USB2_PORT_SHORT(OC_SKIP)"
-			register "usb3_ports[0]"			= "USB3_PORT_DEFAULT(OC_SKIP)"
+			# Top USB 3.0 Type-C			4237 mil
+			register "usb2_ports[1]"		= "USB2_PORT_SHORT(OC_SKIP)"
+			register "usb3_ports[0]"		= "USB3_PORT_DEFAULT(OC_SKIP)"
 
-			# Detachable Keyboard + SD Card Reader		6418 mil
-			register "usb2_ports[2]"			= "USB2_PORT_SHORT(OC_SKIP)"
+			# Detachable Keyboard + SD Card Reader	6418 mil
+			register "usb2_ports[2]"		= "USB2_PORT_SHORT(OC_SKIP)"
 
-			# Camera + Webcam				3249 mil
-			register "usb2_ports[CONFIG_CCD_PORT]"		= "USB2_PORT_SHORT(OC_SKIP)"
+			# Camera + Webcam			3249 mil
+			register "usb2_ports[CONFIG_CCD_PORT]"	= "USB2_PORT_SHORT(OC_SKIP)"
 
-			# Internal Bluetooth				1874 mil
-			register "usb2_ports[9]"			= "USB2_PORT_SHORT(OC_SKIP)"
+			# Internal Bluetooth			1874 mil
+			register "usb2_ports[9]"		= "USB2_PORT_SHORT(OC_SKIP)"
 
 			chip drivers/usb/acpi
 				device ref xhci_root_hub on
@@ -187,23 +187,24 @@ chip soc/intel/alderlake
 									"SlotLengthLong"
 									"M.2/M 2242"
 									"SlotDataBusWidth4X"
+
 			chip soc/intel/common/block/pcie/rtd3
 				register "enable_gpio"			= "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D16)"
 				register "reset_gpio"			= "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_H0)"
 				register "srcclk_pin"			= "0"
-				register "is_storage"			= "1"
-				register "add_acpi_dma_property"	= "1"
-				register "skip_on_off_support"		= "1"
+				register "is_storage"			= "true"
+				register "add_acpi_dma_property"	= "true"
+				register "skip_on_off_support"		= "true"
 				register "ext_pm_support"		= "ACPI_PCIE_RP_EMIT_ALL"
-				register "use_rp_mutex"			= "1"
+				register "use_rp_mutex"			= "true"
 				device generic 0 on end
 			end
 		end
 		device ref uart0	on  end
 		device ref pch_espi	on
-			register "gen1_dec"				= "0x00040069"
-			register "gen2_dec"				= "0x00fc0201"
-			register "gen3_dec"				= "0x000c0081"
+			register "gen1_dec"			= "0x00040069"
+			register "gen2_dec"			= "0x00fc0201"
+			register "gen3_dec"			= "0x000c0081"
 
 			chip ec/starlabs/merlin
 				# Port pair 4Eh/4Fh
@@ -212,9 +213,9 @@ chip soc/intel/alderlake
 				device pnp 4e.04 off end			# System Wake-Up
 				device pnp 4e.05 off end			# PS/2 Mouse
 				device pnp 4e.06 on				# PS/2 Keyboard
-					io 0x60				= 0x0060
-					io 0x62				= 0x0064
-					irq 0x70			= 1
+					io 0x60			= 0x0060
+					io 0x62			= 0x0064
+					irq 0x70		= 1
 				end
 				device pnp 4e.0a off end			# Consumer IR
 				device pnp 4e.0f off end			# Shared Memory/Flash Interface
@@ -248,8 +249,8 @@ chip soc/intel/alderlake
 			subsystemid 0x1e50 0x7038
 			register "pch_hda_sdi_enable[0]"		= "true"
 			register "pch_hda_dsp_enable"			= "true"
-			register "pch_hda_audio_link_hda_enable"	= "1"
-			register "pch_hda_idisp_codec_enable"		= "1"
+			register "pch_hda_audio_link_hda_enable"	= "true"
+			register "pch_hda_idisp_codec_enable"		= "true"
 			register "pch_hda_idisp_link_frequency"		= "HDA_LINKFREQ_96MHZ"
 			register "pch_hda_idisp_link_tmode"		= "HDA_TMODE_8T"
 		end

From da54093bb9c391942d5a28a289be1b785b0b207e Mon Sep 17 00:00:00 2001
From: Yidi Lin <yidilin@google.com>
Date: Fri, 6 Jun 2025 12:55:06 +0000
Subject: [PATCH 1238/3886] Update arm-trusted-firmware submodule to upstream
 master

Updating from commit id b68861c7298d:
2025-05-15 14:26:57 +0000 - (Merge "docs(changelog): add missing scopes" into integration)

to commit id 9109143417b2:
2025-06-05 22:03:35 +0000 - (Merge "feat(cpus): update cpu_check_csv2 check" into integration)

This brings in 55 new commits:
9109143417b2 Merge "feat(cpus): update cpu_check_csv2 check" into integration
470404b8b02f Merge "fix(xlat): change MT_DEVICE to map to nGnRnE" into integration
08b11700e781 Merge "fix(fvp): avoid stack usage in check_cpupwrctrl_el1_is_available()" into integration
2b43216593f1 feat(cpus): update cpu_check_csv2 check
36ceead86b06 fix(fvp): avoid stack usage in check_cpupwrctrl_el1_is_available()
9526ad605872 Merge changes from topic "st_fixes" into integration
adbcd85eec11 Merge changes from topic "xlnx_versal_custom_sip" into integration
a0aec93934cf Merge "fix(qemu): fix variable may be used uninitialized error" into integration
8681f772fb53 Merge "feat(intel): update CPUECTLR_EL1 to boost ethernet performance" into integration
4902381ac01a Merge "feat(mt8189): add IOMMU enable control in SiP service" into integration
02309a84fbfb Merge changes Ia29fd72f,I31b359ce,I1296aaff,I30e1ee7f,Ib4a3593e, ... into integration
fbab861f7f73 Merge "feat(smcc): introduce a new vendor_el3 service for ACS SMC handler" into integration
db0d5350af03 fix(qemu): fix variable may be used uninitialized error
fe524532e345 Merge "docs(versal-net): update documentation for SDEI" into integration
0d003ff58d98 Merge "chore(fvp): remove unused macro definition" into integration
bc11248abbcd Merge changes from topic "xlnx_versal_misra_fixes_series_3" into integration
236422ad7a17 Merge "fix(xilinx): resolve violations generated with IPI_CRC_CHECK enabled" into integration
a335cd91179a fix(xilinx): resolve misra rule 16.3 violations
93db9e6161d5 fix(xilinx): resolve misra rule 2.5 violations
6df7184e5ae0 fix(xilinx): resolve misra rule 4.6 violations
f78c597041fc fix(xilinx): resolve misra rule 12.2 violations
7d0eb0e1e544 fix(xilinx): resolve violations generated with IPI_CRC_CHECK enabled
c314a0b3fe24 fix(xilinx): resolve misra rule 10.1 violations
cd60ab793e22 fix(xilinx): resolve misra rule 8.13 violations
2993166d498b fix(xilinx): resolve misra rule 4.5 violations
ea3ec86552d3 fix(xilinx): resolve misra rule 16.4 violations
00669dcd96b9 fix(xlat): change MT_DEVICE to map to nGnRnE
5be0e22591d7 feat(mt8196): add SMMU SID stub implementation
e86fb819834f feat(mt8196): add SLBC SiP handler
4488b229e573 feat(mt8196): add CPU QoS stub implementation
001058820482 refactor(mediatek): update EMI stub implementation
97881aacebc2 feat(mediatek): add APIs exposed to the static library
c33b98d7b84d feat(mt8196): add MMinfra support
31a69d9ae79c feat(mt8196): add UFS functions used by the static library
22c454d464cf Merge "docs: remove Chris from LTS maintainers" into integration
c17351450c8a Merge "docs(changelog): changelog for v2.13 release" into integration
a6f0886076d1 Merge "fix(fvp): increase EventLog size for OP-TEE with multiple SPs" into integration
9c1201887340 docs: remove Chris from LTS maintainers
97a6de9e9b62 docs(changelog): changelog for v2.13 release
d1a824ea0e88 fix(fvp): increase EventLog size for OP-TEE with multiple SPs
bb9e34f99ca7 feat(intel): update CPUECTLR_EL1 to boost ethernet performance
4c449fcad3c5 feat(mt8189): add IOMMU enable control in SiP service
f69f551269f1 feat(smcc): introduce a new vendor_el3 service for ACS SMC handler
9adc42705a63 fix(st-iwdg): remove num_irq
adeee68b8a08 fix(st-drivers): remove useless field in fixed regul
b43afb7fe16c fix(st-bsec): remove useless defines in BSEC3
6fede181224f fix(st-bsec): rename OTPSR field
6bc7c5b70eba fix(st-crypto): do not set IPRST if BUSY flag is present
6851fd9ecccd fix(st-ddr): bad refresh update level toggle sequence
fd5e5e7b7184 fix(st-ddr): remove TODO in STM32MP2 driver
f53f260f7b78 fix(stm32mp2): correct typo in definition header
72b9f52d373b feat(versal): add hooks for mmap and early setup
55f6ea4dadb2 refactor(zynqmp): refactor custom sip service
48afc8e5ecee chore(fvp): remove unused macro definition
da2c9e58d00c docs(versal-net): update documentation for SDEI

Change-Id: I8720c180141549a2c075455174ac475381a35997
Signed-off-by: Yidi Lin <yidilin@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87976
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
---
 3rdparty/arm-trusted-firmware | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/3rdparty/arm-trusted-firmware b/3rdparty/arm-trusted-firmware
index b68861c729..9109143417 160000
--- a/3rdparty/arm-trusted-firmware
+++ b/3rdparty/arm-trusted-firmware
@@ -1 +1 @@
-Subproject commit b68861c7298d981545f89bb95a468c23420b49bb
+Subproject commit 9109143417b24337d39a2a9583828a44996f8aac

From 7b1eac4192e4e49f16d7d1d2db67988a5b8acdb9 Mon Sep 17 00:00:00 2001
From: Irving-CH Lin <irving-ch.lin@mediatek.corp-partner.google.com>
Date: Mon, 26 May 2025 13:52:22 +0800
Subject: [PATCH 1239/3886] soc/mediatek/mt8189: Enable MUXes for improved
 peripheral stability

Enabling the mem_sub_sel and emi_n_sel MUXes in coreboot ensures proper
connectivity for multiple peripheral modules. Without these MUXes
enabled, some devices may experience communication failures or system
instability.

BUG=b:379008996
BRANCH=none
TEST=build pass and driver init ok.

Signed-off-by: Irving-CH Lin <irving-ch.lin@mediatek.corp-partner.google.com>
Change-Id: I3ee0432ac1f102343e49a51008b3ea552b3f2857
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87974
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
---
 src/soc/mediatek/mt8189/pll.c | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/src/soc/mediatek/mt8189/pll.c b/src/soc/mediatek/mt8189/pll.c
index 24c7cc59e9..84fb16347d 100644
--- a/src/soc/mediatek/mt8189/pll.c
+++ b/src/soc/mediatek/mt8189/pll.c
@@ -66,7 +66,9 @@ enum mux_id {
 	CLK_TOP_AUDIO_H_SEL,
 	CLK_TOP_MCUPM_SEL,
 	CLK_TOP_MEM_SUB_SEL,
+	CLK_TOP_MEM_SUB_PERI_SEL,
 	CLK_TOP_MEM_SUB_U_SEL,
+	CLK_TOP_EMI_N_SEL,
 	CLK_TOP_DXCC_SEL,
 	CLK_TOP_DP_SEL,
 	CLK_TOP_EDP_SEL,
@@ -192,7 +194,9 @@ static const struct mux muxes[] = {
 	CKSYS_MUX_UPD(CLK_TOP_AUDIO_H_SEL, clk_cfg[12], 8, 2, clk_cfg_update[1], 18),
 	CKSYS_MUX_UPD(CLK_TOP_MCUPM_SEL, clk_cfg[12], 16, 2, clk_cfg_update[1], 19),
 	CKSYS_MUX_UPD(CLK_TOP_MEM_SUB_SEL, clk_cfg[12], 24, 4, clk_cfg_update[1], 20),
+	CKSYS_MUX_UPD(CLK_TOP_MEM_SUB_PERI_SEL, clk_cfg[13], 0, 3, clk_cfg_update[1], 21),
 	CKSYS_MUX_UPD(CLK_TOP_MEM_SUB_U_SEL, clk_cfg[13], 8, 3, clk_cfg_update[1], 22),
+	CKSYS_MUX_UPD(CLK_TOP_EMI_N_SEL, clk_cfg[13], 16, 3, clk_cfg_update[1], 23),
 	CKSYS_MUX_UPD(CLK_TOP_DXCC_SEL, clk_cfg[15], 24, 2, clk_cfg_update[2], 1),
 	CKSYS_MUX_UPD(CLK_TOP_DP_SEL, clk_cfg[16], 16, 3, clk_cfg_update[2], 4),
 	CKSYS_MUX_UPD(CLK_TOP_EDP_SEL, clk_cfg[16], 24, 3, clk_cfg_update[2], 5),
@@ -250,7 +254,9 @@ static const struct mux_sel mux_sels[] = {
 	{ .id = CLK_TOP_AUDIO_H_SEL, .sel = 3 },
 	{ .id = CLK_TOP_MCUPM_SEL, .sel = 2 },
 	{ .id = CLK_TOP_MEM_SUB_SEL, .sel = 9 },
+	{ .id = CLK_TOP_MEM_SUB_PERI_SEL, .sel = 7 },
 	{ .id = CLK_TOP_MEM_SUB_U_SEL, .sel = 7 },
+	{ .id = CLK_TOP_EMI_N_SEL, .sel = 2 },
 	{ .id = CLK_TOP_DXCC_SEL, .sel = 1 },
 	{ .id = CLK_TOP_DP_SEL, .sel = 4 },
 	{ .id = CLK_TOP_EDP_SEL, .sel = 4 },

From c2496bc62e6ce4ff7e54d0985b0167246bdeb7d8 Mon Sep 17 00:00:00 2001
From: Xin Ji <xji@analogix.corp-partner.google.com>
Date: Mon, 26 May 2025 14:56:17 +0800
Subject: [PATCH 1240/3886] drivers/analogix/anx7625: Add a retry mechanism to
 decode EDID

Anx7625 reads EDID through AUX channel with I2C Over Aux operation,
reading 16-byte chunk a time. Sometimes, panel(CSOT MNB601LS1-3)
does not returns EDID raw data in time or returns OK without providing
data.

Root cause:
The measured difference between two adjacent UI signals of the AUX
signal is 36ns (518 - 482ns), it meets the VESA DP1.2/1.3 spec < 0.08UI
(48ns) requirement. However, this value exceeds the VESA DP1.1a spec
supported by the panel: max < 0.04UI (24ns) requirement, which exceeds
the tolerance value of the panel and leads to EDID communication
failure.

To address this issue, determined by tests, so that the issue did not
reproduce in over 200 tests

Test result:
Verified on 12pcs panels(8pcs issue panels, 4pcs new panels), 10pcs
tested 300 cycles, 2pcs tested 400 cycles, issue cannot be reproduced.

BUG=b:415946451
TEST=Tested on corsola over 200 times
BRANCH=corsola

Change-Id: I2d4f6b65b8f663ea9b9459e0343897a1223d631a
Signed-off-by: Xin Ji <xji@analogix.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87961
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
---
 src/drivers/analogix/anx7625/anx7625.c | 27 +++++++++++++++-----------
 src/drivers/analogix/anx7625/anx7625.h |  1 +
 2 files changed, 17 insertions(+), 11 deletions(-)

diff --git a/src/drivers/analogix/anx7625/anx7625.c b/src/drivers/analogix/anx7625/anx7625.c
index 4792d07296..ed5000fb75 100644
--- a/src/drivers/analogix/anx7625/anx7625.c
+++ b/src/drivers/analogix/anx7625/anx7625.c
@@ -830,20 +830,25 @@ int anx7625_dp_get_edid(uint8_t bus, struct edid *out)
 	int block_num;
 	int ret;
 	u8 edid[FOUR_BLOCK_SIZE];
+	int i;
 
-	block_num = sp_tx_edid_read(bus, edid, FOUR_BLOCK_SIZE);
-	if (block_num < 0) {
-		ANXERROR("Failed to get eDP EDID.\n");
-		return -1;
+	for (i = 0; i < EDID_RETRY; i++) {
+		block_num = sp_tx_edid_read(bus, edid, FOUR_BLOCK_SIZE);
+		if (block_num < 0) {
+			ANXERROR("Failed to get eDP EDID(retry %d).\n", i);
+			continue;
+		}
+
+		ret = decode_edid(edid, (block_num + 1) * ONE_BLOCK_SIZE, out);
+		if (ret == EDID_CONFORMANT) {
+			ANXINFO("Success read out EDID(retry %d).\n", i);
+			return 0;
+		}
+
+		ANXERROR("Failed to decode EDID(retry %d).\n", i);
 	}
 
-	ret = decode_edid(edid, (block_num + 1) * ONE_BLOCK_SIZE, out);
-	if (ret != EDID_CONFORMANT) {
-		ANXERROR("Failed to decode EDID.\n");
-		return -1;
-	}
-
-	return 0;
+	return -1;
 }
 
 int anx7625_init(uint8_t bus)
diff --git a/src/drivers/analogix/anx7625/anx7625.h b/src/drivers/analogix/anx7625/anx7625.h
index f14f8bd0a6..51973ffbd8 100644
--- a/src/drivers/analogix/anx7625/anx7625.h
+++ b/src/drivers/analogix/anx7625/anx7625.h
@@ -339,6 +339,7 @@ enum AudioWdLen {
 
 #define ONE_BLOCK_SIZE      128
 #define FOUR_BLOCK_SIZE     (128*4)
+#define EDID_RETRY          3
 
 struct display_timing {
 	unsigned int pixelclock;

From 2060f24d60122f8f67bbdc7bd6fb588cb614e628 Mon Sep 17 00:00:00 2001
From: Jeremy Soller <jeremy@system76.com>
Date: Wed, 14 May 2025 09:35:38 -0600
Subject: [PATCH 1241/3886] mb/system76/mtl: Add Darter Pro 11 variants

darp11 is an ArrowLake-H refresh of the previous model.

Change-Id: I1ac692a6591e0c7df89c5ba76a83764694145762
Signed-off-by: Jeremy Soller <jeremy@system76.com>
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87675
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/system76/mtl/Kconfig            |  21 +-
 src/mainboard/system76/mtl/Kconfig.name       |   6 +
 .../system76/mtl/variants/darp11/board.fmd    |  13 ++
 .../mtl/variants/darp11/board_info.txt        |   2 +
 .../system76/mtl/variants/darp11/data.vbt     | Bin 0 -> 7680 bytes
 .../system76/mtl/variants/darp11/gpio.c       | 216 ++++++++++++++++++
 .../system76/mtl/variants/darp11/gpio_early.c |  16 ++
 .../system76/mtl/variants/darp11/hda_verb.c   |  59 +++++
 .../mtl/variants/darp11/overridetree.cb       | 115 ++++++++++
 .../system76/mtl/variants/darp11/ramstage.c   |  18 ++
 .../system76/mtl/variants/darp11/romstage.c   |  25 ++
 11 files changed, 490 insertions(+), 1 deletion(-)
 create mode 100644 src/mainboard/system76/mtl/variants/darp11/board.fmd
 create mode 100644 src/mainboard/system76/mtl/variants/darp11/board_info.txt
 create mode 100644 src/mainboard/system76/mtl/variants/darp11/data.vbt
 create mode 100644 src/mainboard/system76/mtl/variants/darp11/gpio.c
 create mode 100644 src/mainboard/system76/mtl/variants/darp11/gpio_early.c
 create mode 100644 src/mainboard/system76/mtl/variants/darp11/hda_verb.c
 create mode 100644 src/mainboard/system76/mtl/variants/darp11/overridetree.cb
 create mode 100644 src/mainboard/system76/mtl/variants/darp11/ramstage.c
 create mode 100644 src/mainboard/system76/mtl/variants/darp11/romstage.c

diff --git a/src/mainboard/system76/mtl/Kconfig b/src/mainboard/system76/mtl/Kconfig
index 81558aa34c..2a0bada34e 100644
--- a/src/mainboard/system76/mtl/Kconfig
+++ b/src/mainboard/system76/mtl/Kconfig
@@ -38,6 +38,20 @@ config BOARD_SYSTEM76_DARP10_B
 	select SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES
 	select SOC_INTEL_METEORLAKE_U_H
 
+config BOARD_SYSTEM76_DARP11
+	select BOARD_SYSTEM76_MTL_COMMON
+	select EC_SYSTEM76_EC_FAN2
+	select MAINBOARD_USES_IFD_GBE_REGION
+	select SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES
+	select SOC_INTEL_METEORLAKE_U_H
+
+config BOARD_SYSTEM76_DARP11_B
+	select BOARD_SYSTEM76_MTL_COMMON
+	select EC_SYSTEM76_EC_FAN2
+	select MAINBOARD_USES_IFD_GBE_REGION
+	select SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES
+	select SOC_INTEL_METEORLAKE_U_H
+
 config BOARD_SYSTEM76_LEMP13
 	select BOARD_SYSTEM76_MTL_COMMON
 	select DRIVERS_I2C_TAS5825M
@@ -59,6 +73,7 @@ config MAINBOARD_DIR
 
 config VARIANT_DIR
 	default "darp10" if BOARD_SYSTEM76_DARP10 || BOARD_SYSTEM76_DARP10_B
+	default "darp11" if BOARD_SYSTEM76_DARP11 || BOARD_SYSTEM76_DARP11_B
 	default "lemp13" if BOARD_SYSTEM76_LEMP13 || BOARD_SYSTEM76_LEMP13_B
 
 config OVERRIDE_DEVICETREE
@@ -67,16 +82,20 @@ config OVERRIDE_DEVICETREE
 config MAINBOARD_PART_NUMBER
 	default "darp10" if BOARD_SYSTEM76_DARP10
 	default "darp10-b" if BOARD_SYSTEM76_DARP10_B
+	default "darp11" if BOARD_SYSTEM76_DARP11
+	default "darp11-b" if BOARD_SYSTEM76_DARP11_B
 	default "lemp13" if BOARD_SYSTEM76_LEMP13
 	default "lemp13-b" if BOARD_SYSTEM76_LEMP13_B
 
 config MAINBOARD_SMBIOS_PRODUCT_NAME
-	default "Darter Pro" if BOARD_SYSTEM76_DARP10 || BOARD_SYSTEM76_DARP10_B
+	default "Darter Pro" if BOARD_SYSTEM76_DARP10 || BOARD_SYSTEM76_DARP10_B || BOARD_SYSTEM76_DARP11 || BOARD_SYSTEM76_DARP11_B
 	default "Lemur Pro" if BOARD_SYSTEM76_LEMP13 || BOARD_SYSTEM76_LEMP13_B
 
 config MAINBOARD_VERSION
 	default "darp10" if BOARD_SYSTEM76_DARP10
 	default "darp10-b" if BOARD_SYSTEM76_DARP10_B
+	default "darp11" if BOARD_SYSTEM76_DARP11
+	default "darp11-b" if BOARD_SYSTEM76_DARP11_B
 	default "lemp13" if BOARD_SYSTEM76_LEMP13
 	default "lemp13-b" if BOARD_SYSTEM76_LEMP13_B
 
diff --git a/src/mainboard/system76/mtl/Kconfig.name b/src/mainboard/system76/mtl/Kconfig.name
index 299c834f82..b0e214e866 100644
--- a/src/mainboard/system76/mtl/Kconfig.name
+++ b/src/mainboard/system76/mtl/Kconfig.name
@@ -6,6 +6,12 @@ config BOARD_SYSTEM76_DARP10
 config BOARD_SYSTEM76_DARP10_B
 	bool "darp10-b"
 
+config BOARD_SYSTEM76_DARP11
+	bool "darp11"
+
+config BOARD_SYSTEM76_DARP11_B
+	bool "darp11-b"
+
 config BOARD_SYSTEM76_LEMP13
 	bool "lemp13"
 
diff --git a/src/mainboard/system76/mtl/variants/darp11/board.fmd b/src/mainboard/system76/mtl/variants/darp11/board.fmd
new file mode 100644
index 0000000000..2b8860d67f
--- /dev/null
+++ b/src/mainboard/system76/mtl/variants/darp11/board.fmd
@@ -0,0 +1,13 @@
+FLASH 32M {
+	SI_DESC 16K
+	SI_GBE 8K
+	SI_ME 8612K
+	SI_BIOS@16M 16M {
+		RW_MRC_CACHE 64K
+		SMMSTORE(PRESERVE) 256K
+		WP_RO {
+			FMAP 4K
+			COREBOOT(CBFS)
+		}
+	}
+}
diff --git a/src/mainboard/system76/mtl/variants/darp11/board_info.txt b/src/mainboard/system76/mtl/variants/darp11/board_info.txt
new file mode 100644
index 0000000000..a2b32815ed
--- /dev/null
+++ b/src/mainboard/system76/mtl/variants/darp11/board_info.txt
@@ -0,0 +1,2 @@
+Board name: darp11
+Release year: 2025
diff --git a/src/mainboard/system76/mtl/variants/darp11/data.vbt b/src/mainboard/system76/mtl/variants/darp11/data.vbt
new file mode 100644
index 0000000000000000000000000000000000000000..4976c93dbafeaef061073c31a6265bbe52506e09
GIT binary patch
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HcmV?d00001

diff --git a/src/mainboard/system76/mtl/variants/darp11/gpio.c b/src/mainboard/system76/mtl/variants/darp11/gpio.c
new file mode 100644
index 0000000000..3d57ee2052
--- /dev/null
+++ b/src/mainboard/system76/mtl/variants/darp11/gpio.c
@@ -0,0 +1,216 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <mainboard/gpio.h>
+#include <soc/gpio.h>
+
+static const struct pad_config gpio_table[] = {
+	PAD_CFG_NF(GPP_A00, UP_20K, DEEP, NF1), // ESPI_IO0_EC
+	PAD_CFG_NF(GPP_A01, UP_20K, DEEP, NF1), // ESPI_IO1_EC
+	PAD_CFG_NF(GPP_A02, UP_20K, DEEP, NF1), // ESPI_IO2_EC
+	PAD_CFG_NF(GPP_A03, UP_20K, DEEP, NF1), // ESPI_IO3_EC
+	PAD_CFG_NF(GPP_A04, UP_20K, DEEP, NF1), // ESPI_CS_EC#
+	PAD_CFG_NF(GPP_A05, UP_20K, DEEP, NF1), // ESPI_CLK_EC
+	PAD_CFG_NF(GPP_A06, NONE, DEEP, NF1), // ESPI_RESET_N
+	// GPP_A07 missing
+	// GPP_A08 missing
+	// GPP_A09 missing
+	// GPP_A10 missing
+	PAD_CFG_GPO(GPP_A11, 0, DEEP), // ADDS_CODE
+	PAD_CFG_GPI(GPP_A12, NONE, DEEP), // WLAN_WAKEUP#
+	PAD_CFG_TERM_GPO(GPP_A13, 1, UP_20K, PLTRST), // M2_SSD2_RST#
+	PAD_NC(GPP_A14, NONE),
+	PAD_NC(GPP_A15, NONE), // CPU_SWI# (test point)
+	PAD_CFG_NF(GPP_A16, UP_20K, DEEP, NF1), // ESPI_ALRT0#
+	PAD_NC(GPP_A17, NONE), // TP_ATTN#_A17
+	PAD_NC(GPP_A18, NONE),
+	PAD_NC(GPP_A19, NONE),
+	PAD_NC(GPP_A20, NONE),
+	PAD_CFG_NF(GPP_A21, NATIVE, DEEP, NF1), // PMC_I2C_INT
+
+	PAD_CFG_GPI_INT(GPP_B00, NONE, PLTRST, LEVEL), // TP_ATTN#_B00
+	PAD_NC(GPP_B01, NONE),
+	PAD_NC(GPP_B02, NONE),
+	PAD_NC(GPP_B03, NONE),
+	PAD_CFG_GPO(GPP_B04, 0, DEEP), // NO REBOOT strap
+	PAD_CFG_GPO(GPP_B05, 0, DEEP), // CPU_KBCRST# (test point)
+	PAD_CFG_GPO(GPP_B06, 0, DEEP), // ROM_I2C_EN
+	PAD_NC(GPP_B07, NONE),
+	PAD_NC(GPP_B08, NONE),
+	PAD_NC(GPP_B09, NONE),
+	PAD_NC(GPP_B10, NONE),
+	PAD_CFG_NF(GPP_B11, NONE, DEEP, NF2), // HDMI_HPD
+	PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), // SLP_S0#
+	PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), // PLTRST#
+	PAD_CFG_GPI(GPP_B14, NONE, DEEP), // Top swap override strap
+	PAD_CFG_GPI(GPP_B15, NONE, DEEP), // GPP_B15_USB2_OC0_N
+	PAD_NC(GPP_B16, NONE),
+	PAD_NC(GPP_B17, NONE),
+	PAD_CFG_GPO(GPP_B18, 1, DEEP), // PCH_BT_EN
+	PAD_CFG_GPO(GPP_B19, 1, DEEP), // WIFI_RF_EN
+	PAD_NC(GPP_B20, NONE),
+	PAD_CFG_GPO(GPP_B21, 0, PLTRST), // TCP_RETIMER_FORCE_PWR
+	PAD_NC(GPP_B22, NONE),
+	PAD_NC(GPP_B23, NONE),
+
+	PAD_CFG_NF(GPP_C00, NONE, DEEP, NF1), // SMB_CLK
+	PAD_CFG_NF(GPP_C01, NONE, DEEP, NF1), // SMB_DATA
+	PAD_CFG_NF(GPP_C02, NONE, DEEP, NF1), // TLS confidentiality strap
+	PAD_CFG_NF(GPP_C03, UP_20K, DEEP, NF1), // SML0_CLK
+	PAD_CFG_NF(GPP_C04, UP_20K, DEEP, NF1), // SML0_DATA
+	PAD_CFG_NF(GPP_C05, UP_20K, DEEP, NF1), // eSPI disabled strap
+	PAD_CFG_NF(GPP_C06, UP_20K, DEEP, NF1), // PMC_I2C_SCL
+	PAD_CFG_NF(GPP_C07, UP_20K, DEEP, NF1), // PMC_I2C_SDA
+	PAD_NC(GPP_C08, NONE),
+	PAD_NC(GPP_C09, NONE),
+	PAD_NC(GPP_C10, NONE),
+	PAD_CFG_NF(GPP_C11, NONE, PWROK, NF1), // CPU_LAN_CLKREQ#
+	PAD_CFG_NF(GPP_C12, NONE, PWROK, NF1), // CPU_CARD_CLKREQ#
+	PAD_NC(GPP_C13, NONE),
+	// GPP_C14 missing
+	PAD_CFG_GPO(GPP_C15, 0, DEEP), // GPP_C15_STRAP
+	PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1), // TBT_LSX0_TXD
+	PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1), // TBT_LSX0_RXD
+	PAD_NC(GPP_C18, NONE),
+	PAD_NC(GPP_C19, NONE),
+	PAD_CFG_NF(GPP_C20, NONE, DEEP, NF2), // HDMI_CTRLCLK
+	PAD_CFG_NF(GPP_C21, NONE, DEEP, NF2), // HDMI_CTRLDATA
+	PAD_NC(GPP_C22, NONE),
+	PAD_NC(GPP_C23, NONE),
+
+	PAD_CFG_GPO(GPP_D00, 1, DEEP), // SB_BLON
+	PAD_CFG_GPO(GPP_D01, 1, DEEP), // SSD2_PWR_EN
+	PAD_CFG_GPO(GPP_D02, 1, DEEP), // M2_SSD1_RST#
+	PAD_NC(GPP_D03, NONE),
+	PAD_NC(GPP_D04, NONE),
+	PAD_CFG_GPO(GPP_D05, 1, DEEP), // SSD1_PWR_EN
+	PAD_NC(GPP_D06, NONE),
+	PAD_NC(GPP_D07, NONE),
+	PAD_NC(GPP_D08, NONE),
+	PAD_NC(GPP_D09, NONE),
+	PAD_CFG_NF(GPP_D10, NONE, DEEP, NF1), // HDA_BITCLK
+	PAD_CFG_NF(GPP_D11, NATIVE, DEEP, NF1), // HDA_SYNC
+	PAD_CFG_NF(GPP_D12, NATIVE, DEEP, NF1), // HDA_SDOUT / ME_WE
+	PAD_CFG_NF(GPP_D13, NATIVE, DEEP, NF1), // HDA_SDI0
+	PAD_NC(GPP_D14, NONE),
+	PAD_NC(GPP_D15, NONE),
+	PAD_CFG_GPO(GPP_D16, 0, DEEP), // GPIO_SPK_MUTE
+	PAD_CFG_NF(GPP_D17, NONE, DEEP, NF1), // HDA_RST#
+	PAD_NC(GPP_D18, NONE),
+	PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1), // CPU_SSD1_CLKREQ#
+	PAD_CFG_NF(GPP_D20, NONE, DEEP, NF1), // CPU_SSD2_CLKREQ#
+	PAD_CFG_NF(GPP_D21, NONE, DEEP, NF2), // CPU_WLAN_CLKREQ#
+	PAD_CFG_NF(GPP_D22, NATIVE, DEEP, NF1),
+	PAD_CFG_NF(GPP_D23, NATIVE, DEEP, NF1),
+
+	PAD_NC(GPP_E00, NONE),
+	_PAD_CFG_STRUCT(GPP_E01, 0x40100100, 0x3000), // TPM_PIRQ#
+	PAD_CFG_GPI(GPP_E02, NONE, DEEP), // BOARD_ID4
+	PAD_CFG_GPI(GPP_E03, NONE, DEEP), // CNVI_WAKE#
+	PAD_NC(GPP_E04, NONE),
+	PAD_NC(GPP_E05, NONE),
+	PAD_CFG_GPO(GPP_E06, 0, DEEP), // JTAG ODT disable strap
+	PAD_NC(GPP_E07, NONE),
+	PAD_NC(GPP_E08, NONE),
+	PAD_CFG_GPI(GPP_E09, NONE, DEEP), // GPP_E9_USB2_OC0_N
+	PAD_NC(GPP_E10, NONE),
+	PAD_CFG_GPI(GPP_E11, NONE, DEEP), // BOARD_ID6
+	PAD_NC(GPP_E12, NONE),
+	PAD_NC(GPP_E13, NONE),
+	PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), // EDP_HPD
+	PAD_NC(GPP_E15, NONE),
+	PAD_CFG_NF(GPP_E16, NONE, DEEP, NF2), // VRALERT#
+	PAD_CFG_GPO(GPP_E17, 0, DEEP), // BOARD_ID5
+	// GPP_E18 missing
+	// GPP_E19 missing
+	// GPP_E20 missing
+	// GPP_E21 missing
+	PAD_CFG_GPO(GPP_E22, 0, DEEP), // DNX_FORCE_RELOAD
+
+	PAD_CFG_NF(GPP_F00, NONE, DEEP, NF1), // CNVI_BRI_DT
+	PAD_CFG_NF(GPP_F01, UP_20K, DEEP, NF1), // CNVI_BRI_RSP
+	PAD_CFG_NF(GPP_F02, NONE, DEEP, NF1), // CNVI_RGI_DT
+	PAD_CFG_NF(GPP_F03, UP_20K, DEEP, NF1), // CNVI_RGI_RSP
+	PAD_CFG_NF(GPP_F04, NONE, DEEP, NF1), // CNVI_RST#
+	PAD_CFG_NF(GPP_F05, NONE, DEEP, NF3), // CNVI_CLKREQ
+	PAD_CFG_GPO(GPP_F06, 0, DEEP), // CNVI_GNSS_PA_BLANKING
+	PAD_NC(GPP_F07, NONE),
+	PAD_NC(GPP_F08, NONE),
+	PAD_CFG_GPI(GPP_F09, NONE, DEEP), // TPM_DET
+	PAD_NC(GPP_F10, NONE),
+	PAD_CFG_GPO(GPP_F11, 0, DEEP), // BOARD_ID3
+	PAD_NC(GPP_F12, NONE), // I2C_SCL_CODEC
+	PAD_NC(GPP_F13, NONE), // I2C_SDA_CODEC
+	PAD_CFG_GPO(GPP_F14, 0, DEEP), // BOARD_ID1
+	PAD_CFG_GPO(GPP_F15, 0, DEEP), // BOARD_ID2
+	PAD_NC(GPP_F16, NONE),
+	PAD_NC(GPP_F17, NONE),
+	PAD_CFG_GPO(GPP_F18, 0, DEEP), // CPU_CCD_WP#
+	PAD_NC(GPP_F19, NONE),
+	PAD_CFG_GPO(GPP_F20, 0, DEEP), // SVID support strap
+	PAD_NC(GPP_F21, NONE),
+	PAD_NC(GPP_F22, NONE),
+	PAD_NC(GPP_F23, NONE),
+
+	PAD_CFG_GPO(GPP_H00, 0, DEEP), // eSPI flash sharing mode strap
+	PAD_CFG_GPO(GPP_H01, 0, DEEP), // SPI flash descriptor recovery strap
+	PAD_NC(GPP_H02, NONE),
+	// GPP_H03 missing
+	PAD_CFG_GPO(GPP_H04, 0, DEEP), // CNVI_MFUART2_RXD
+	PAD_CFG_GPO(GPP_H05, 0, DEEP), // CNVI_MFUART2_TXD
+	PAD_CFG_NF(GPP_H06, NONE, DEEP, NF1), // I2C3_SDA (Pantone)
+	PAD_CFG_NF(GPP_H07, NONE, DEEP, NF1), // I2C3_SCL (Pantone)
+	// GPP_H08 (UART0_RXD) configured in bootblock
+	// GPP_H09 (UART0_TXD) configured in bootblock
+	PAD_CFG_GPO(GPP_H10, 0, DEEP),
+	PAD_CFG_GPO(GPP_H11, 0, DEEP),
+	PAD_CFG_GPO(GPP_H12, 0, DEEP),
+	PAD_NC(GPP_H13, NONE),
+	PAD_NC(GPP_H14, NONE),
+	PAD_NC(GPP_H15, NONE),
+	PAD_NC(GPP_H16, NONE),
+	PAD_NC(GPP_H17, NONE),
+	// GPP_H18 missing
+	PAD_CFG_NF(GPP_H19, NONE, DEEP, NF1), // I2C_SDA_TP
+	PAD_CFG_NF(GPP_H20, NONE, DEEP, NF1), // I2C_SCL_TP
+	PAD_CFG_NF(GPP_H21, NONE, DEEP, NF1), // PCH_I2C_SDA
+	PAD_CFG_NF(GPP_H22, NONE, DEEP, NF1), // PCH_I2C_SCL
+
+	PAD_NC(GPP_S00, NONE),
+	PAD_NC(GPP_S01, NONE),
+	PAD_NC(GPP_S02, NONE), // DMIC_CLK_A1
+	PAD_NC(GPP_S03, NONE), // DMIC_DATA_A1
+	PAD_NC(GPP_S04, NONE),
+	PAD_NC(GPP_S05, NONE),
+	PAD_NC(GPP_S06, NONE),
+	PAD_NC(GPP_S07, NONE),
+
+	PAD_CFG_NF(GPP_V00, NONE, DEEP, NF1), // PM_BATLOW#
+	PAD_CFG_NF(GPP_V01, NONE, DEEP, NF1), // AC_PRESENT
+	PAD_CFG_NF(GPP_V02, NONE, DEEP, NF1), // LAN_WAKEUP#
+	PAD_CFG_NF(GPP_V03, NONE, DEEP, NF1), // PWR_BTN#
+	PAD_CFG_NF(GPP_V04, NONE, DEEP, NF1), // SUSB#_PCH
+	PAD_CFG_NF(GPP_V05, UP_20K, DEEP, NF1), // SUSC#_PCH
+	PAD_CFG_NF(GPP_V06, NATIVE, DEEP, NF1), // SLP_A#
+	// GPP_V07 missing
+	PAD_CFG_NF(GPP_V08, UP_20K, DEEP, NF1), // SUS_CLK
+	PAD_CFG_NF(GPP_V09, NONE, DEEP, NF1), // SLP_WLAN#
+	PAD_NC(GPP_V10, NONE),
+	PAD_CFG_NF(GPP_V11, NONE, DEEP, NF1), // LANPHYPC
+	PAD_CFG_GPO(GPP_V12, 0, DEEP), // SLP_LAN#
+	// GPP_V13 missing
+	PAD_CFG_NF(GPP_V14, NONE, DEEP, NF1), // PCIE_WAKE#
+	// GPP_V15 missing
+	// GPP_V16 missing
+	// GPP_V17 missing
+	// GPP_V18 missing
+	// GPP_V19 missing
+	// GPP_V20 missing
+	// GPP_V21 missing
+	PAD_NC(GPP_V22, NONE),
+	PAD_NC(GPP_V23, NONE),
+};
+
+void mainboard_configure_gpios(void)
+{
+	gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table));
+}
diff --git a/src/mainboard/system76/mtl/variants/darp11/gpio_early.c b/src/mainboard/system76/mtl/variants/darp11/gpio_early.c
new file mode 100644
index 0000000000..f17db26f3e
--- /dev/null
+++ b/src/mainboard/system76/mtl/variants/darp11/gpio_early.c
@@ -0,0 +1,16 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <mainboard/gpio.h>
+#include <soc/gpio.h>
+
+static const struct pad_config early_gpio_table[] = {
+	PAD_CFG_NF(GPP_C00, NONE, DEEP, NF1), // SMB_CLK
+	PAD_CFG_NF(GPP_C01, NONE, DEEP, NF1), // SMB_DATA
+	PAD_CFG_NF(GPP_H08, NONE, DEEP, NF1), // UART0_RX
+	PAD_CFG_NF(GPP_H09, NONE, DEEP, NF1), // UART0_TX
+};
+
+void mainboard_configure_early_gpios(void)
+{
+	gpio_configure_pads(early_gpio_table, ARRAY_SIZE(early_gpio_table));
+}
diff --git a/src/mainboard/system76/mtl/variants/darp11/hda_verb.c b/src/mainboard/system76/mtl/variants/darp11/hda_verb.c
new file mode 100644
index 0000000000..2915f4d9eb
--- /dev/null
+++ b/src/mainboard/system76/mtl/variants/darp11/hda_verb.c
@@ -0,0 +1,59 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <device/azalia_device.h>
+
+const u32 cim_verb_data[] = {
+	/* Realtek, ALC245 */
+	0x10ec0245, /* Vendor ID */
+	0x1558a763, /* Subsystem ID */
+	40, /* Number of entries */
+	//AZALIA_SUBVENDOR(0, 0x1558a763),
+	AZALIA_SUBVENDOR(0, 0x1558a743),
+	AZALIA_RESET(1),
+	AZALIA_PIN_CFG(0, 0x12, 0x90a60130),
+	AZALIA_PIN_CFG(0, 0x13, 0x40000000),
+	AZALIA_PIN_CFG(0, 0x14, 0x90170110),
+	AZALIA_PIN_CFG(0, 0x17, 0x411111f0),
+	AZALIA_PIN_CFG(0, 0x18, 0x411111f0),
+	AZALIA_PIN_CFG(0, 0x19, 0x411111f0),
+	AZALIA_PIN_CFG(0, 0x1a, 0x411111f0),
+	AZALIA_PIN_CFG(0, 0x1b, 0x411111f0),
+	AZALIA_PIN_CFG(0, 0x1d, 0x40789b2d),
+	AZALIA_PIN_CFG(0, 0x1e, 0x411111f0),
+	AZALIA_PIN_CFG(0, 0x21, 0x04211020),
+
+	0x05b50006, 0x05b40011, 0x0205001a, 0x0204810b,
+	0x0205004a, 0x02042010, 0x02050038, 0x02047909,
+	0x05c50000, 0x05c43d82, 0x05c50000, 0x05c43d82,
+	0x05350000, 0x0534201a, 0x05350000, 0x0534201a,
+	0x0535001d, 0x05340800, 0x0535001e, 0x05340800,
+	0x05350003, 0x05341ec4, 0x05350004, 0x05340000,
+	0x05450000, 0x05442000, 0x0545001d, 0x05440800,
+	0x0545001e, 0x05440800, 0x05450003, 0x05441ec4,
+	0x05450004, 0x05440000, 0x05350000, 0x0534a01a,
+	0x0205003c, 0x0204f175, 0x0205003c, 0x0204f135,
+	0x02050040, 0x02048800, 0x05a50001, 0x05a4001f,
+	0x02050010, 0x02040020, 0x02050010, 0x02040020,
+	0x0205006b, 0x0204a390, 0x0205006b, 0x0204a390,
+	0x0205006c, 0x02040c9e, 0x0205006d, 0x02040c00,
+	0x00170500, 0x00170500, 0x05a50004, 0x05a40113,
+	0x02050008, 0x02046a8c, 0x02050076, 0x0204f000,
+	0x0205000e, 0x020465c0, 0x02050033, 0x02048580,
+	0x02050069, 0x0204fda8, 0x02050068, 0x02040000,
+	0x02050003, 0x02040002, 0x02050069, 0x02040000,
+	0x02050068, 0x02040001, 0x0205002e, 0x0204290e,
+	0x02236100, 0x02235100, 0x00920011, 0x00970610,
+	0x00936000, 0x00935000, 0x0205000d, 0x0204a020,
+	0x00220011, 0x00270610, 0x0023a046, 0x00239046,
+	0x0173b000, 0x01770740, 0x05a50001, 0x05a4001f,
+	0x05c5000f, 0x05c40003, 0x02050036, 0x020437d7,
+	0x0143b000, 0x01470740, 0x02050010, 0x02040020,
+	0x01470c02, 0x01470c02,
+
+	// XXX: Duplicate last 2 u32s to keep in 4-dword blocks
+	0x01470c02, 0x01470c02,
+};
+
+const u32 pc_beep_verbs[] = {};
+
+AZALIA_ARRAY_SIZES;
diff --git a/src/mainboard/system76/mtl/variants/darp11/overridetree.cb b/src/mainboard/system76/mtl/variants/darp11/overridetree.cb
new file mode 100644
index 0000000000..6c2467a76b
--- /dev/null
+++ b/src/mainboard/system76/mtl/variants/darp11/overridetree.cb
@@ -0,0 +1,115 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
+chip soc/intel/meteorlake
+	device domain 0 on
+		subsystemid 0x1558 0xa743 inherit
+
+		device ref tbt_pcie_rp0 on end
+		device ref tcss_xhci on
+			register "tcss_ports[0]" = "TCSS_PORT_DEFAULT(OC_SKIP)"
+			register "tcss_ports[1]" = "TCSS_PORT_DEFAULT(OC_SKIP)"
+			# TCP2 is used as HDMI
+			# TCP3 is not used
+			chip drivers/usb/acpi
+				device ref tcss_root_hub on
+					chip drivers/usb/acpi
+						register "desc" = ""TBT Type-C""
+						register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
+						device ref tcss_usb3_port0 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB Type-C""
+						register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
+						device ref tcss_usb3_port1 on end
+					end
+				end
+			end
+		end
+		device ref tcss_dma0 on end
+		device ref xhci on
+			register "usb2_ports" = "{
+				[0] = USB2_PORT_MID(OC_SKIP),	/* J_AUD1 / AJ_USB3_1 */
+				[1] = USB2_PORT_MID(OC_SKIP),	/* J_TYPEC1 */
+				[2] = USB2_PORT_MID(OC_SKIP),	/* J_USB3_1 */
+				[5] = USB2_PORT_MID(OC_SKIP),	/* TBT */
+				[6] = USB2_PORT_MID(OC_SKIP),	/* Camera */
+				[9] = USB2_PORT_MID(OC_SKIP),	/* Bluetooth */
+			}"
+			register "usb3_ports" = "{
+				[0] = USB3_PORT_DEFAULT(OC_SKIP),	/* J_AUD1 / AJ_USB3_1 */
+				[1] = USB3_PORT_DEFAULT(OC_SKIP),	/* J_USB3_1 */
+			}"
+		end
+		device ref i2c0 on
+			# Touchpad I2C bus
+			register "serial_io_i2c_mode[PchSerialIoIndexI2C0]" = "PchSerialIoPci"
+			chip drivers/i2c/hid
+				register "generic.hid" = ""ELAN0412""
+				register "generic.desc" = ""ELAN Touchpad""
+				register "generic.irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPP_B00)"
+				register "generic.detect" = "1"
+				register "hid_desc_reg_offset" = "0x01"
+				device i2c 15 on end
+			end
+			chip drivers/i2c/hid
+				register "generic.hid" = ""FTCS1000""
+				register "generic.desc" = ""FocalTech Touchpad""
+				register "generic.irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPP_B00)"
+				register "generic.detect" = "1"
+				register "hid_desc_reg_offset" = "0x01"
+				device i2c 38 on end
+			end
+		end
+		device ref pcie_rp5 on
+			# GLAN
+			register "pcie_rp[PCH_RP(5)]" = "{
+				.clk_src = 2,
+				.clk_req = 2,
+				.flags = PCIE_RP_LTR | PCIE_RP_AER | PCIE_RP_CLK_SRC_UNUSED,
+			}"
+			register "pcie_clk_config_flag[2]" = "PCIE_CLK_FREE_RUNNING"
+			device pci 00.0 on end
+		end
+		device ref pcie_rp6 on
+			# Card Reader
+			register "pcie_rp[PCH_RP(6)]" = "{
+				.clk_src = 3,
+				.clk_req = 3,
+				.flags = PCIE_RP_LTR | PCIE_RP_AER,
+			}"
+		end
+		device ref pcie_rp8 on
+			# WLAN
+			register "pcie_rp[PCH_RP(8)]" = "{
+				.clk_src = 5,
+				.clk_req = 5,
+				.flags = PCIE_RP_LTR | PCIE_RP_AER,
+			}"
+			smbios_slot_desc "SlotTypeM2Socket1_SD" "SlotLengthOther" "M.2/E 2230 (J_WLAN1)" "SlotDataBusWidth1X"
+		end
+		device ref pcie_rp10 on
+			# SSD2
+			# XXX: Schematics show RP[13:16] used
+			register "pcie_rp[PCH_RP(10)]" = "{
+				.clk_src = 8,
+				.clk_req = 8,
+				.flags = PCIE_RP_LTR | PCIE_RP_AER,
+			}"
+			smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M.2/M 2280 (J_SSD2)" "SlotDataBusWidth4X"
+		end
+		device ref pcie_rp11 on
+			# SSD1
+			# XXX: Schematics show RP[17:20] used
+			register "pcie_rp[PCH_RP(11)]" = "{
+				.clk_src = 7,
+				.clk_req = 7,
+				.flags = PCIE_RP_LTR | PCIE_RP_AER,
+			}"
+			smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M.2/M 2280 (J_SSD1)" "SlotDataBusWidth4X"
+		end
+		device ref hda on
+			subsystemid 0x1558 0xa763
+		end
+		device ref gbe on end
+	end
+end
diff --git a/src/mainboard/system76/mtl/variants/darp11/ramstage.c b/src/mainboard/system76/mtl/variants/darp11/ramstage.c
new file mode 100644
index 0000000000..0e3baf2ad6
--- /dev/null
+++ b/src/mainboard/system76/mtl/variants/darp11/ramstage.c
@@ -0,0 +1,18 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <soc/ramstage.h>
+
+void mainboard_silicon_init_params(FSP_S_CONFIG *params)
+{
+	// Enable TCP1 USB-A conversion
+	// BIT 0:3 is mapping to PCH XHCI USB2 port
+	// BIT 4:5 is reserved
+	// BIT 6 is orientational
+	// BIT 7 is enable
+	// TODO: Add to coreboot FSP headers as no Client FSP release will be made.
+	//params->EnableTcssCovTypeA[1] = 0x82;
+
+	// XXX: Enabling C10 reporting causes system to constantly enter and
+	// exit opportunistic suspend when idle.
+	params->PchEspiHostC10ReportEnable = 0;
+}
diff --git a/src/mainboard/system76/mtl/variants/darp11/romstage.c b/src/mainboard/system76/mtl/variants/darp11/romstage.c
new file mode 100644
index 0000000000..b047f523ac
--- /dev/null
+++ b/src/mainboard/system76/mtl/variants/darp11/romstage.c
@@ -0,0 +1,25 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <soc/meminit.h>
+#include <soc/romstage.h>
+
+void mainboard_memory_init_params(FSPM_UPD *mupd)
+{
+	const struct mb_cfg board_cfg = {
+		.type = MEM_TYPE_DDR5,
+		.ect = true,
+	};
+	const struct mem_spd spd_info = {
+		.topo = MEM_TOPO_DIMM_MODULE,
+		.smbus = {
+			[0] = { .addr_dimm[0] = 0x50, },
+			[1] = { .addr_dimm[0] = 0x52, },
+		},
+	};
+	const bool half_populated = false;
+
+	mupd->FspmConfig.DmiMaxLinkSpeed = 4;
+	mupd->FspmConfig.GpioOverride = 0;
+
+	memcfg_init(mupd, &board_cfg, &spd_info, half_populated);
+}

From 8b5442820072d04cd4705be784345d1f272c4296 Mon Sep 17 00:00:00 2001
From: Zhongtian Wu <wuzhongtian@huaqin.corp-partner.google.com>
Date: Thu, 5 Jun 2025 20:52:10 +0800
Subject: [PATCH 1242/3886] mb/google/nissa: Override GPIO_PCH_WP for
 pujjocento variant

According to the circuit schematic diagram, pujjocento uses GPP_E12
as a write-protected gpio,so it is necessary to add the GPIO_PCH_WP
definition for GPP_E12 in gpio.h.

BUG=b:422656149
BRANCH=none
TEST=wp status update verified by toggling it on and off.

Change-Id: I91081f1b0ce5cb2fb3a29b96c1dcc18774f70f09
Signed-off-by: Zhongtian Wu <wuzhongtian@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87967
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
---
 src/mainboard/google/brya/variants/pujjocento/gpio.c           | 2 +-
 .../google/brya/variants/pujjocento/include/variant/gpio.h     | 3 +++
 2 files changed, 4 insertions(+), 1 deletion(-)

diff --git a/src/mainboard/google/brya/variants/pujjocento/gpio.c b/src/mainboard/google/brya/variants/pujjocento/gpio.c
index e079b19981..517eb495b4 100644
--- a/src/mainboard/google/brya/variants/pujjocento/gpio.c
+++ b/src/mainboard/google/brya/variants/pujjocento/gpio.c
@@ -1,6 +1,6 @@
 /* SPDX-License-Identifier: GPL-2.0-or-later */
 
-#include <baseboard/gpio.h>
+#include <variant/gpio.h>
 #include <baseboard/variants.h>
 #include <soc/gpio.h>
 #include <types.h>
diff --git a/src/mainboard/google/brya/variants/pujjocento/include/variant/gpio.h b/src/mainboard/google/brya/variants/pujjocento/include/variant/gpio.h
index 66cfef0274..351bb879c3 100644
--- a/src/mainboard/google/brya/variants/pujjocento/include/variant/gpio.h
+++ b/src/mainboard/google/brya/variants/pujjocento/include/variant/gpio.h
@@ -4,6 +4,9 @@
 #define VARIANT_GPIO_H
 
 #include <baseboard/gpio.h>
+#undef GPIO_PCH_WP
+/* WP signal to PCH */
+#define GPIO_PCH_WP		GPP_E12
 
 #define WWAN_FCPO	GPP_D6 /* FULL_CARD_POWER_OFF# */
 #define WWAN_RST	GPP_E17

From c776d2dbd6a6c7739402e13b3d0301e643f72e76 Mon Sep 17 00:00:00 2001
From: Jhan Bo Chao <jhan_bo_chao@realtek.com>
Date: Thu, 15 May 2025 21:49:55 +0800
Subject: [PATCH 1243/3886] ec/google: Add support for Realtek EC in ChromeOS
 EC

This commit adds the necessary infrastructure to support Realtek EC
controllers RTS5912/RTS5915 within the ChromeOS EC framework.

TEST=With this commit and 87702, flash to brox(rework realtek rts5915)
     Boot normally and got those message from ap console:

[DEBUG]  Google Chrome EC uptime: 698.137 seconds
[DEBUG]  Google Chrome AP resets since EC boot: 6
[DEBUG]  Google Chrome most recent AP reset causes:
[DEBUG]  	635.380: 8 reset: during EC initialization
[DEBUG]  	645.374: 32775 shutdown: entering G3
[DEBUG]  	680.284: 8 reset: during EC initialization
[DEBUG]  	684.586: 8 reset: during EC initialization
[DEBUG]  Google Chrome EC reset flags at last EC boot: soft
[DEBUG]  PNP: 0c09.0 init finished in 284 msecs

Change-Id: I44118c7b61a7efcee81acdd04be90b5022007a41
Signed-off-by: Jhan Bo Chao <jhan_bo_chao@realtek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87544
Reviewed-by: Keith Short <keithshort@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/ec/google/chromeec/Kconfig     | 11 ++++
 src/ec/google/chromeec/Makefile.mk | 10 +++
 src/ec/google/chromeec/ec.h        | 52 +++++++++++++---
 src/ec/google/chromeec/ec_lpc.c    | 97 ++++++++++++++++--------------
 src/ec/google/chromeec/mec.c       | 47 +++++++++++++++
 src/ec/google/chromeec/rtk.c       | 94 +++++++++++++++++++++++++++++
 src/ec/google/common/Kconfig       |  5 ++
 7 files changed, 261 insertions(+), 55 deletions(-)
 create mode 100644 src/ec/google/chromeec/mec.c
 create mode 100644 src/ec/google/chromeec/rtk.c

diff --git a/src/ec/google/chromeec/Kconfig b/src/ec/google/chromeec/Kconfig
index bcd2b13351..8e037f2496 100644
--- a/src/ec/google/chromeec/Kconfig
+++ b/src/ec/google/chromeec/Kconfig
@@ -99,6 +99,13 @@ config EC_GOOGLE_CHROMEEC_MEC
 	help
 	  Microchip EC variant for LPC register access.
 
+config EC_GOOGLE_CHROMEEC_RTK
+	depends on EC_GOOGLE_CHROMEEC_LPC
+	def_bool n
+	select EC_GOOGLE_COMMON_RTK
+	help
+	  Realtek EC variant for LPC register access.
+
 config EC_GOOGLE_CHROMEEC_EC_HOST_CMD_DEBUG
 	depends on EC_GOOGLE_CHROMEEC_LPC && HAVE_MONOTONIC_TIMER
 	def_bool n
@@ -211,6 +218,10 @@ config EC_GOOGLE_CHROMEEC_LPC_GENERIC_MEMORY_RANGE
 	  Select this option to access LPC GMR (Generic Memory Range) Register to
 	  implement MMIO based communication between EC and AP firmware.
 
+config EC_GOOGLE_CHROMEEC_LPC_GENERIC_MEMORY_BASE
+	hex
+	default 0xfe0b0000
+
 endif # EC_GOOGLE_CHROMEEC
 
 source "src/ec/google/chromeec/*/Kconfig"
diff --git a/src/ec/google/chromeec/Makefile.mk b/src/ec/google/chromeec/Makefile.mk
index 10b6203e5d..659daf23a0 100644
--- a/src/ec/google/chromeec/Makefile.mk
+++ b/src/ec/google/chromeec/Makefile.mk
@@ -27,22 +27,32 @@ bootblock-$(CONFIG_EC_GOOGLE_CHROMEEC_SPI) += ec_spi.c
 ifeq ($(CONFIG_EC_GOOGLE_CHROMEEC_SPI)$(CONFIG_EC_GOOGLE_CHROMEEC_I2C),y)
 bootblock-y += crosec_proto.c
 endif
+bootblock-$(CONFIG_EC_GOOGLE_CHROMEEC_MEC) += mec.c
+bootblock-$(CONFIG_EC_GOOGLE_CHROMEEC_RTK) += rtk.c
 ramstage-y += ec.c crosec_proto.c vstore.c usbc_mux.c
 ramstage-$(CONFIG_EC_GOOGLE_CHROMEEC_I2C) += ec_i2c.c
 ramstage-$(CONFIG_EC_GOOGLE_CHROMEEC_LPC) += ec_lpc.c
 ramstage-$(CONFIG_EC_GOOGLE_CHROMEEC_SPI) += ec_spi.c
+ramstage-$(CONFIG_EC_GOOGLE_CHROMEEC_MEC) += mec.c
+ramstage-$(CONFIG_EC_GOOGLE_CHROMEEC_RTK) += rtk.c
 smm-y += ec.c crosec_proto.c smihandler.c vstore.c
 smm-$(CONFIG_EC_GOOGLE_CHROMEEC_I2C) += ec_i2c.c
 smm-$(CONFIG_EC_GOOGLE_CHROMEEC_LPC) += ec_lpc.c
 smm-$(CONFIG_EC_GOOGLE_CHROMEEC_SPI) += ec_spi.c
+smm-$(CONFIG_EC_GOOGLE_CHROMEEC_MEC) += mec.c
+smm-$(CONFIG_EC_GOOGLE_CHROMEEC_RTK) += rtk.c
 romstage-y += ec.c crosec_proto.c vstore.c
 romstage-$(CONFIG_EC_GOOGLE_CHROMEEC_I2C) += ec_i2c.c
 romstage-$(CONFIG_EC_GOOGLE_CHROMEEC_LPC) += ec_lpc.c
 romstage-$(CONFIG_EC_GOOGLE_CHROMEEC_SPI) += ec_spi.c
+romstage-$(CONFIG_EC_GOOGLE_CHROMEEC_MEC) += mec.c
+romstage-$(CONFIG_EC_GOOGLE_CHROMEEC_RTK) += rtk.c
 verstage-y += ec.c crosec_proto.c vstore.c
 verstage-$(CONFIG_EC_GOOGLE_CHROMEEC_I2C) += ec_i2c.c
 verstage-$(CONFIG_EC_GOOGLE_CHROMEEC_LPC) += ec_lpc.c
 verstage-$(CONFIG_EC_GOOGLE_CHROMEEC_SPI) += ec_spi.c
+verstage-$(CONFIG_EC_GOOGLE_CHROMEEC_MEC) += mec.c
+verstage-$(CONFIG_EC_GOOGLE_CHROMEEC_RTK) += rtk.c
 ramstage-$(CONFIG_HAVE_ACPI_TABLES) += ec_acpi.c
 
 ramstage-$(CONFIG_VBOOT) += vboot_storage.c
diff --git a/src/ec/google/chromeec/ec.h b/src/ec/google/chromeec/ec.h
index b11b7a834a..957adb4089 100644
--- a/src/ec/google/chromeec/ec.h
+++ b/src/ec/google/chromeec/ec.h
@@ -116,14 +116,6 @@ int google_chromeec_cbi_get_ssfc(uint32_t *ssfc);
 uint32_t google_chromeec_get_board_sku(void);
 const char *google_chromeec_smbios_system_sku(void);
 
-/* MEC uses 0x800/0x804 as register/index pair, thus an 8-byte resource. */
-#define MEC_EMI_BASE		0x800
-#define MEC_EMI_SIZE		8
-
-/* For MEC, access ranges 0x800 thru 0x9ff using EMI interface instead of LPC */
-#define MEC_EMI_RANGE_START EC_HOST_CMD_REGION0
-#define MEC_EMI_RANGE_END   (EC_LPC_ADDR_MEMMAP + EC_MEMMAP_SIZE)
-
 int google_chromeec_set_usb_charge_mode(uint8_t port_id, enum usb_charge_mode mode);
 int google_chromeec_set_usb_pd_role(uint8_t port, enum usb_pd_control_role role);
 /*
@@ -263,8 +255,7 @@ int google_chromeec_start_vboot_hash(enum ec_vboot_hash_type hash_type,
  * @return		0 on success, -1 on error
  *
  */
-int google_chromeec_get_vboot_hash(uint32_t offset,
-				   struct ec_response_vboot_hash *resp);
+int google_chromeec_get_vboot_hash(uint32_t offset, struct ec_response_vboot_hash *resp);
 
 /**
  * Get offset and size of the specified EC flash region.
@@ -495,4 +486,45 @@ const char *google_chromeec_acpi_name(const struct device *dev);
 
 #endif /* HAVE_ACPI_TABLES */
 
+/**
+ * Initialize the EC.
+ */
+void chipset_init(void);
+
+/**
+ * Read bytes from the EMI.
+ *
+ * @param port		IO port number
+ * @param length	Length of the data to read
+ * @param dest		Pointer to the destination buffer
+ * @param csum		Pointer to the checksum buffer
+ *
+ * @return true indicates that the EC processes the read through the EMI interface
+ * and does not need to handle it through the IO port; otherwise, an IO read operation
+ * should be issued.
+ */
+bool chipset_emi_read_bytes(u16 port, size_t length, u8 *dest, u8 *csum);
+
+/**
+ * Write bytes to the EMI.
+ *
+ * @param port		IO port number
+ * @param length	Length of the data to write
+ * @param msg		Pointer to the message buffer
+ * @param csum		Pointer to the checksum buffer
+ *
+ * @return true indicates that the EC processes the write through the EMI interface
+ * and does not need to handle it through the IO port; otherwise, an IO write operation
+ * should be issued.
+ */
+bool chipset_emi_write_bytes(u16 port, size_t length, u8 *msg, u8 *csum);
+
+/**
+ * Get the IO port range. implement this function if the EC requires different IO ports.
+ *
+ * @param base		Pointer to the base of the IO port range
+ * @param size		Pointer to the size of the IO port range
+ */
+void chipset_ioport_range(uint16_t *base, size_t *size);
+
 #endif /* _EC_GOOGLE_CHROMEEC_EC_H */
diff --git a/src/ec/google/chromeec/ec_lpc.c b/src/ec/google/chromeec/ec_lpc.c
index b32d25c6a8..19139ccc07 100644
--- a/src/ec/google/chromeec/ec_lpc.c
+++ b/src/ec/google/chromeec/ec_lpc.c
@@ -5,7 +5,6 @@
 #include <console/console.h>
 #include <delay.h>
 #include <device/pnp.h>
-#include <ec/google/common/mec.h>
 #include <stdint.h>
 #include <timer.h>
 
@@ -13,6 +12,12 @@
 #include "ec.h"
 #include "ec_commands.h"
 
+/* Return true if data read from EMI interface, false if no bytes transferred */
+__weak bool chipset_emi_read_bytes(u16 port, size_t length, u8 *dest, u8 *csum)
+{
+	return false;
+}
+
 /*
  * Read bytes from a given LPC-mapped address.
  *
@@ -21,21 +26,14 @@
  * @dest: Destination buffer
  * @csum: Optional parameter, sums data read
  */
-static void read_bytes(u16 port, unsigned int length, u8 *dest, u8 *csum)
+static void read_bytes(u16 port, size_t length, u8 *dest, u8 *csum)
 {
-	int i;
+	size_t i;
 
-#if CONFIG(EC_GOOGLE_CHROMEEC_MEC)
-	/* Access desired range though EMI interface */
-	if (port >= MEC_EMI_RANGE_START && port <= MEC_EMI_RANGE_END) {
-		u8 ret = mec_io_bytes(MEC_IO_READ, MEC_EMI_BASE,
-				     port - MEC_EMI_RANGE_START,
-				     dest, length);
-		if (csum)
-			*csum += ret;
+	if (chipset_emi_read_bytes(port, length, dest, csum)) {
+		/* Access through EMI interface successful */
 		return;
 	}
-#endif
 
 	for (i = 0; i < length; ++i) {
 		dest[i] = inb(port + i);
@@ -61,6 +59,11 @@ static inline u8 read_byte_indexed_io(u8 offset)
 }
 #endif
 
+__weak bool chipset_emi_write_bytes(u16 port, size_t length, u8 *msg, u8 *csum)
+{
+	return false;
+}
+
 /*
  * Write bytes to a given LPC-mapped address.
  *
@@ -69,21 +72,14 @@ static inline u8 read_byte_indexed_io(u8 offset)
  * @msg: Write data buffer
  * @csum: Optional parameter, sums data written
  */
-static void write_bytes(u16 port, unsigned int length, u8 *msg, u8 *csum)
+static void write_bytes(u16 port, size_t length, u8 *msg, u8 *csum)
 {
-	int i;
+	size_t i;
 
-#if CONFIG(EC_GOOGLE_CHROMEEC_MEC)
-	/* Access desired range though EMI interface */
-	if (port >= MEC_EMI_RANGE_START && port <= MEC_EMI_RANGE_END) {
-		u8 ret = mec_io_bytes(MEC_IO_WRITE, MEC_EMI_BASE,
-				     port - MEC_EMI_RANGE_START,
-				     msg, length);
-		if (csum)
-			*csum += ret;
+	if (chipset_emi_write_bytes(port, length, msg, csum)) {
+		/* Access through EMI interface successful */
 		return;
 	}
-#endif
 
 	for (i = 0; i < length; ++i) {
 		outb(msg[i], port + i);
@@ -127,6 +123,11 @@ static int google_chromeec_wait_ready(u16 port)
 					    EC_LPC_CMDR_BUSY, 0);
 }
 
+static int google_chromeec_data_ready(u16 port)
+{
+	return google_chromeec_status_check(port, EC_LPC_CMDR_DATA, EC_LPC_CMDR_DATA);
+}
+
 #if CONFIG(EC_GOOGLE_CHROMEEC_ACPI_MEMMAP)
 /* Read memmap data through ACPI port 66/62 */
 static int read_memmap(u8 *data, u8 offset)
@@ -152,6 +153,13 @@ static int read_memmap(u8 *data, u8 offset)
 		return -1;
 	}
 
+	/* ap should wait b0 (OBF) */
+	if (CONFIG(EC_GOOGLE_CHROMEEC_RTK) &&
+	    google_chromeec_data_ready(EC_LPC_ADDR_ACPI_CMD)) {
+		printk(BIOS_ERR, "Timeout waiting for EC DATA!\n");
+		return -1;
+	}
+
 	*data = read_byte(EC_LPC_ADDR_ACPI_DATA);
 	return 0;
 }
@@ -252,6 +260,14 @@ static int google_chromeec_command_v3(struct chromeec_command *cec_command)
 		return -1;
 	}
 
+	/* RTS5915: acpi port should wait status reg bit 0 (OBF),
+	   and then take data from data register */
+	if (CONFIG(EC_GOOGLE_CHROMEEC_RTK) &&
+	    google_chromeec_data_ready(EC_LPC_ADDR_HOST_CMD)) {
+		printk(BIOS_ERR, "Timeout waiting for EC DATA!\n");
+		return -1;
+	}
+
 	/* Check result */
 	cec_command->cmd_code = read_byte(EC_LPC_ADDR_HOST_DATA);
 	if (cec_command->cmd_code) {
@@ -381,24 +397,18 @@ uint8_t google_chromeec_get_switches(void)
 #endif
 }
 
+void __weak chipset_ioport_range(uint16_t *base, size_t *size)
+{
+	*base = EC_HOST_CMD_REGION0;
+	*size = 2 * EC_HOST_CMD_REGION_SIZE;
+	/* Make sure MEMMAP region follows host cmd region. */
+	assert(*base + *size == EC_LPC_ADDR_MEMMAP);
+	*size += EC_MEMMAP_SIZE;
+}
+
 void google_chromeec_ioport_range(uint16_t *out_base, size_t *out_size)
 {
-	uint16_t base;
-	size_t size;
-
-	if (CONFIG(EC_GOOGLE_CHROMEEC_MEC)) {
-		base = MEC_EMI_BASE;
-		size = MEC_EMI_SIZE;
-	} else {
-		base = EC_HOST_CMD_REGION0;
-		size = 2 * EC_HOST_CMD_REGION_SIZE;
-		/* Make sure MEMMAP region follows host cmd region. */
-		assert(base + size == EC_LPC_ADDR_MEMMAP);
-		size += EC_MEMMAP_SIZE;
-	}
-
-	*out_base = base;
-	*out_size = size;
+	chipset_ioport_range(out_base, out_size);
 }
 
 int google_chromeec_command(struct chromeec_command *cec_command)
@@ -436,11 +446,14 @@ int google_chromeec_command(struct chromeec_command *cec_command)
 	return result;
 }
 
+void __weak chipset_init(void) {}
+
 static void lpc_ec_init(struct device *dev)
 {
 	if (!dev->enabled)
 		return;
 
+	chipset_init();
 	google_chromeec_init();
 }
 
@@ -494,12 +507,6 @@ struct chip_operations ec_google_chromeec_ops = {
 	.enable_dev = enable_dev,
 };
 
-static int google_chromeec_data_ready(u16 port)
-{
-	return google_chromeec_status_check(port, EC_LPC_CMDR_DATA,
-					    EC_LPC_CMDR_DATA);
-}
-
 enum host_event_code google_chromeec_get_event(void)
 {
 	if (google_chromeec_wait_ready(EC_LPC_ADDR_ACPI_CMD)) {
diff --git a/src/ec/google/chromeec/mec.c b/src/ec/google/chromeec/mec.c
new file mode 100644
index 0000000000..1ad7ba182d
--- /dev/null
+++ b/src/ec/google/chromeec/mec.c
@@ -0,0 +1,47 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <arch/io.h>
+#include <ec/google/common/mec.h>
+#include <stdint.h>
+
+#include "ec.h"
+
+/* MEC uses 0x800/0x804 as register/index pair, thus an 8-byte resource. */
+#define MEC_EMI_BASE		0x800
+#define MEC_EMI_SIZE		8
+
+/* For MEC, access ranges 0x800 thru 0x9ff using EMI interface instead of LPC */
+#define MEC_EMI_RANGE_START EC_HOST_CMD_REGION0
+#define MEC_EMI_RANGE_END   (EC_LPC_ADDR_MEMMAP + EC_MEMMAP_SIZE)
+
+bool chipset_emi_read_bytes(u16 port, size_t length, u8 *dest, u8 *csum)
+{
+	/* Access desired range though EMI interface */
+	if (port >= MEC_EMI_RANGE_START && port <= MEC_EMI_RANGE_END) {
+		u8 ret = mec_io_bytes(MEC_IO_READ, MEC_EMI_BASE, port - MEC_EMI_RANGE_START,
+				      dest, length);
+		if (csum)
+			*csum += ret;
+		return true;
+	}
+	return false;
+}
+
+bool chipset_emi_write_bytes(u16 port, size_t length, u8 *msg, u8 *csum)
+{
+	/* Access desired range though EMI interface */
+	if (port >= MEC_EMI_RANGE_START && port <= MEC_EMI_RANGE_END) {
+		u8 ret = mec_io_bytes(MEC_IO_WRITE, MEC_EMI_BASE, port - MEC_EMI_RANGE_START,
+				      msg, length);
+		if (csum)
+			*csum += ret;
+		return true;
+	}
+	return false;
+}
+
+void chipset_ioport_range(uint16_t *base, size_t *size)
+{
+	*base = MEC_EMI_BASE;
+	*size = MEC_EMI_SIZE;
+}
diff --git a/src/ec/google/chromeec/rtk.c b/src/ec/google/chromeec/rtk.c
new file mode 100644
index 0000000000..6779d422f2
--- /dev/null
+++ b/src/ec/google/chromeec/rtk.c
@@ -0,0 +1,94 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <arch/io.h>
+#include <stdint.h>
+
+#include "ec.h"
+
+/* For RTK, access ranges 0x800 thru 0x9ff using EMI interface instead of LPC */
+#define EMI_RANGE_START EC_HOST_CMD_REGION0
+#define EMI_RANGE_END   (EC_LPC_ADDR_MEMMAP + EC_MEMMAP_SIZE)
+
+#define HOSTCMD_PARAM_MEM_BASE CONFIG_EC_GOOGLE_CHROMEEC_LPC_GENERIC_MEMORY_BASE
+#define ACPI_MEM_BASE          (HOSTCMD_PARAM_MEM_BASE + 0x100)
+
+#define SIO_CONFIG_PORT 0x2e
+#define SIO_DATA_PORT   0x2f
+#define SIO_LDN         0x07
+#define EMI0_LDN        0x06
+#define EMI1_LDN        0x07 /* EMI1 LDN */
+
+#define EMI_ADDR3 0xf0 /* The EMI base address 31-24*/
+#define EMI_ADDR2 0xf1 /* The EMI base address 23-16*/
+#define EMI_ADDR1 0xf2 /* The EMI base address 15-8*/
+#define EMI_CTRL  0x30
+
+bool chipset_emi_read_bytes(u16 port, size_t length, u8 *dest, u8 *csum)
+{
+	size_t i;
+
+	printk(BIOS_DEBUG, "RTS5915: read port 0x%x, size %ld\n", port, length);
+
+	if (port >= EMI_RANGE_START && port <= EMI_RANGE_END) {
+		uint8_t *p = (uint8_t *)(HOSTCMD_PARAM_MEM_BASE + (port - EMI_RANGE_START));
+		for (i = 0; i < length; ++i) {
+			dest[i] = p[i];
+			if (csum)
+				*csum += dest[i];
+		}
+		return true;
+	}
+	return false;
+}
+
+bool chipset_emi_write_bytes(u16 port, size_t length, u8 *msg, u8 *csum)
+{
+	size_t i;
+
+	printk(BIOS_DEBUG, "RTS5915: write port 0x%x, size %ld\n", port, length);
+
+	if (port >= EMI_RANGE_START && port <= EMI_RANGE_END) {
+		uint8_t *p = (uint8_t *)(HOSTCMD_PARAM_MEM_BASE + (port - EMI_RANGE_START));
+		for (i = 0; i < length; ++i) {
+			p[i] = msg[i];
+			if (csum)
+				*csum += msg[i];
+		}
+		return true;
+	}
+
+	return false;
+}
+
+static inline void sio_write_config(uint8_t reg, uint8_t value)
+{
+	outb(reg, SIO_CONFIG_PORT);
+	outb(value, SIO_DATA_PORT);
+}
+
+void chipset_init(void)
+{
+	/*
+	 * Due the hardware design, the RTS5915 EMI should be initiated by host sio command,
+	 * The EMI range is 256 bytes, chromeec needs two region for host command and ACPI
+	 * shared memory.
+	 */
+
+	printk(BIOS_INFO, "RTS5915 EMI: start init ...\n");
+
+	/* Configure the EMI0 to 0xfe0b0000 for host command parameters */
+	sio_write_config(SIO_LDN, EMI0_LDN);
+	sio_write_config(EMI_ADDR3, HOSTCMD_PARAM_MEM_BASE >> 24 & 0xff);
+	sio_write_config(EMI_ADDR2, HOSTCMD_PARAM_MEM_BASE >> 16 & 0xff);
+	sio_write_config(EMI_ADDR1, HOSTCMD_PARAM_MEM_BASE >> 8 & 0xff);
+	sio_write_config(EMI_CTRL, 0x01); /* Enable EMI */
+
+	/* Configure the EMI1 to 0xfe0b0100 for ACPI shared memory */
+	sio_write_config(SIO_LDN, EMI1_LDN);
+	sio_write_config(EMI_ADDR3, ACPI_MEM_BASE >> 24 & 0xff);
+	sio_write_config(EMI_ADDR2, ACPI_MEM_BASE >> 16 & 0xff);
+	sio_write_config(EMI_ADDR1, ACPI_MEM_BASE >> 8 & 0xff);
+	sio_write_config(EMI_CTRL, 0x01); /* Enable EMI */
+
+	printk(BIOS_INFO, "RTS5915 EMI: done\n");
+}
diff --git a/src/ec/google/common/Kconfig b/src/ec/google/common/Kconfig
index 2005ddbfb9..324c4d9da8 100644
--- a/src/ec/google/common/Kconfig
+++ b/src/ec/google/common/Kconfig
@@ -4,3 +4,8 @@ config EC_GOOGLE_COMMON_MEC
 	bool
 	help
 	  Google common EC functions for Microchip EMI region.
+
+config EC_GOOGLE_COMMON_RTK
+	bool
+	help
+	  Google common EC functions for Realtek EMI region.

From b66b7f7860a12edbfa8afbedc78f4bce8bd02470 Mon Sep 17 00:00:00 2001
From: Benjamin Doron <benjamin.doron@9elements.com>
Date: Tue, 17 Dec 2024 15:46:14 -0500
Subject: [PATCH 1244/3886] commonlib/device_tree.c: Add a function that reads
 FDT ints

Follow the recommendation at
https://review.coreboot.org/c/coreboot/+/84796/comment/21f615a2_99a41147/
and implement support for reading integer properties generically, using
their size to determine how much to read. This will be used for reading
`load`, `entry` and perhaps others.

Change-Id: I02d27eb5e23dfbfc1404d209ee8d60968e22bb80
Signed-off-by: Benjamin Doron <benjamin.doron@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85643
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/commonlib/device_tree.c                   | 20 +++++++++++++++++++
 src/commonlib/include/commonlib/device_tree.h |  2 ++
 2 files changed, 22 insertions(+)

diff --git a/src/commonlib/device_tree.c b/src/commonlib/device_tree.c
index c4fbae986d..fb1e78f590 100644
--- a/src/commonlib/device_tree.c
+++ b/src/commonlib/device_tree.c
@@ -259,6 +259,26 @@ static u32 fdt_read_cell_props(const void *blob, u32 node_offset, u32 *addrcp, u
 	return offset;
 }
 
+uint64_t fdt_read_int_prop(struct fdt_property *prop, u32 cells)
+{
+	if (cells == 0)
+		cells = prop->size / 4;
+
+	if (cells * 4 != prop->size) {
+		printk(BIOS_ERR, "FDT integer property of size %u @%p doesn't match expected cell count %u\n",
+		       prop->size, prop->data, cells);
+		return 0;
+	}
+
+	if (cells == 2)
+		return be64dec(prop->data);
+	else if (cells == 1)
+		return be32dec(prop->data);
+
+	printk(BIOS_ERR, "Illegal FDT integer property size %u @%p\n", prop->size, prop);
+	return 0;
+}
+
 /*
  * fdt_find_node searches for a node relative to another node
  *
diff --git a/src/commonlib/include/commonlib/device_tree.h b/src/commonlib/include/commonlib/device_tree.h
index f51f827593..5ab5fbf294 100644
--- a/src/commonlib/include/commonlib/device_tree.h
+++ b/src/commonlib/include/commonlib/device_tree.h
@@ -118,6 +118,8 @@ u32 fdt_read_prop(const void *blob, u32 node_offset, const char *prop_name,
 /* Read reg property and save regions inside 'regions'. Returns number of regions read */
 u32 fdt_read_reg_prop(const void *blob, u32 node_offset, u32 addr_cells, u32 size_cells,
 		      struct device_tree_region regions[], size_t regions_count);
+/* Reads value for a fdt_prop, considering the cells */
+uint64_t fdt_read_int_prop(struct fdt_property *prop, u32 cells);
 /* Find a node by a given path and return the offset */
 u32 fdt_find_node_by_path(const void *blob, const char *path, u32 *addrcp, u32 *sizecp);
 /* Find multiple nodes matching a given pattern. Returns number of nodes found */

From 4247128e39d06d31b4a298b9d23ad7a0f899b4f0 Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Fri, 6 Jun 2025 11:55:21 -0500
Subject: [PATCH 1245/3886] soc/intel/cmn/block/aspm: Fix ASPM control for CPU
 root ports

ASPM_AUTO is not a valid value for the CpuPcieRpAspm[x] UPD; setting
it will result in the CPU root port having ASPM disabled by FSP.
Fix this by modifying aspm_control_to_upd() to take into account
whether it's being called for a PCH RP or a CPU RP, and setting
the default value appropriately.

TEST=build/boot starlabs/starfighter_rpl, verify CPU-attached RP
and downstream attached device have ASPM L1 enabled.

Change-Id: Ia89744fcae1294671061fb80be61b927a1578d4d
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87979
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/soc/intel/common/block/aspm/aspm.c | 10 +++++-----
 1 file changed, 5 insertions(+), 5 deletions(-)

diff --git a/src/soc/intel/common/block/aspm/aspm.c b/src/soc/intel/common/block/aspm/aspm.c
index afdf3f6fae..0a1196c569 100644
--- a/src/soc/intel/common/block/aspm/aspm.c
+++ b/src/soc/intel/common/block/aspm/aspm.c
@@ -40,15 +40,15 @@
  * +-------------------+--------------------------+-----------+-----------+
  */
 
-static unsigned int aspm_control_to_upd(enum ASPM_control aspm_control)
+static unsigned int aspm_control_to_upd(enum ASPM_control aspm_control, bool is_cpu_rp)
 {
 	/* Disable without Kconfig selected */
 	if (!CONFIG(PCIEXP_ASPM))
 		return UPD_INDEX(ASPM_DISABLE);
 
-	/* Use auto unless overwritten */
+	/* Use default unless overwritten */
 	if (!aspm_control)
-		return UPD_INDEX(ASPM_AUTO);
+		return is_cpu_rp ? UPD_INDEX(ASPM_L0S_L1) : UPD_INDEX(ASPM_AUTO);
 
 	return UPD_INDEX(aspm_control);
 }
@@ -90,7 +90,7 @@ void configure_pch_rp_power_management(FSP_S_CONFIG *s_cfg,
 	s_cfg->PcieRpEnableCpm[index] =
 		get_uint_option("pciexp_clk_pm", CONFIG(PCIEXP_CLK_PM));
 	s_cfg->PcieRpAspm[index] =
-		aspm_control_to_upd(get_uint_option("pciexp_aspm", rp_cfg->pcie_rp_aspm));
+		aspm_control_to_upd(get_uint_option("pciexp_aspm", rp_cfg->pcie_rp_aspm), false);
 	s_cfg->PcieRpL1Substates[index] =
 		l1ss_control_to_upd(get_uint_option("pciexp_l1ss", rp_cfg->PcieRpL1Substates));
 	s_cfg->PcieRpPcieSpeed[index] =
@@ -120,7 +120,7 @@ void configure_cpu_rp_power_management(FSP_S_CONFIG *s_cfg,
 	s_cfg->CpuPcieClockGating[index] = pciexp_clk_pm;
 	s_cfg->CpuPciePowerGating[index] = pciexp_clk_pm;
 	s_cfg->CpuPcieRpAspm[index] =
-		aspm_control_to_upd(get_uint_option("pciexp_aspm", rp_cfg->pcie_rp_aspm));
+		aspm_control_to_upd(get_uint_option("pciexp_aspm", rp_cfg->pcie_rp_aspm), true);
 	s_cfg->CpuPcieRpL1Substates[index] =
 		l1ss_control_to_upd(get_uint_option("pciexp_l1ss", rp_cfg->PcieRpL1Substates));
 }

From 9f8e5ab661a9d7c00f20fa229c1ed6e48270a8d7 Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Fri, 6 Jun 2025 12:04:09 -0500
Subject: [PATCH 1246/3886] soc/intel/cmn/block/aspm: Use separate option
 variable for CPU RP

Since the default ASPM UPD value (and valid values) differ between CPU
and PCH-attached root ports, add a new option variable for CPU-attached
RPs so that they are not inadvertently set to an invalid value, leading
ASPM to be disabled on those RPs.

Change-Id: I66ec77a3774a96cfe11f5827f5ba711ec826b236
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87980
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
---
 src/soc/intel/common/block/aspm/aspm.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/soc/intel/common/block/aspm/aspm.c b/src/soc/intel/common/block/aspm/aspm.c
index 0a1196c569..595de84d0d 100644
--- a/src/soc/intel/common/block/aspm/aspm.c
+++ b/src/soc/intel/common/block/aspm/aspm.c
@@ -120,7 +120,7 @@ void configure_cpu_rp_power_management(FSP_S_CONFIG *s_cfg,
 	s_cfg->CpuPcieClockGating[index] = pciexp_clk_pm;
 	s_cfg->CpuPciePowerGating[index] = pciexp_clk_pm;
 	s_cfg->CpuPcieRpAspm[index] =
-		aspm_control_to_upd(get_uint_option("pciexp_aspm", rp_cfg->pcie_rp_aspm), true);
+		aspm_control_to_upd(get_uint_option("pciexp_aspm_cpu", rp_cfg->pcie_rp_aspm), true);
 	s_cfg->CpuPcieRpL1Substates[index] =
 		l1ss_control_to_upd(get_uint_option("pciexp_l1ss", rp_cfg->PcieRpL1Substates));
 }

From b3ac5ecdac1c604f75f383c25ecf54eca1213856 Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Fri, 6 Jun 2025 12:04:55 -0500
Subject: [PATCH 1247/3886] soc/intel/cmn/block/cfr: Add CFR form for
 pciexp_aspm_cpu

Add a new CFR form to configure ASPM on CPU-attached PCIe root ports,
with the correct default and range of values for the associated UPD.
Adjust the verbiage on the existing ASPM CFR form so that it is clear
that form is used to configure PCH-attached root ports.

Change-Id: I73dd98fc09bf095da15cf4beb2c282e4c91400cd
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87981
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
---
 .../common/block/include/intelblocks/cfr.h    | 20 +++++++++++++++++--
 1 file changed, 18 insertions(+), 2 deletions(-)

diff --git a/src/soc/intel/common/block/include/intelblocks/cfr.h b/src/soc/intel/common/block/include/intelblocks/cfr.h
index fe9af039a6..24ddf47a65 100644
--- a/src/soc/intel/common/block/include/intelblocks/cfr.h
+++ b/src/soc/intel/common/block/include/intelblocks/cfr.h
@@ -44,10 +44,10 @@ static const struct sm_object power_on_after_fail = SM_DECLARE_ENUM({
 				SM_ENUM_VALUE_END					},
 });
 
-/* PCIe RP ASPM */
+/* PCIe PCH RP ASPM */
 static const struct sm_object pciexp_aspm = SM_DECLARE_ENUM({
 	.opt_name	= "pciexp_aspm",
-	.ui_name	= "PCIe RP ASPM",
+	.ui_name	= "PCIe PCH RP ASPM",
 	.ui_helptext	= "Controls the Active State Power Management for PCIe devices."
 			  " Enabling this feature can reduce power consumption of"
 			  " PCIe-connected devices during idle times.",
@@ -61,6 +61,22 @@ static const struct sm_object pciexp_aspm = SM_DECLARE_ENUM({
 				SM_ENUM_VALUE_END		},
 });
 
+/* PCIe CPU RP ASPM */
+static const struct sm_object pciexp_aspm_cpu = SM_DECLARE_ENUM({
+	.opt_name	= "pciexp_aspm_cpu",
+	.ui_name	= "PCIe CPU RP ASPM",
+	.ui_helptext	= "Controls the Active State Power Management for PCIe devices."
+			  " Enabling this feature can reduce power consumption of"
+			  " PCIe-connected devices during idle times.",
+	.default_value	= ASPM_L0S_L1,
+	.values		= (const struct sm_enum_value[]) {
+				{ "Disabled",	ASPM_DISABLE	},
+				{ "L0s",	ASPM_L0S	},
+				{ "L1",		ASPM_L1		},
+				{ "L0sL1",	ASPM_L0S_L1	},
+				SM_ENUM_VALUE_END		},
+});
+
 /* PCIe Clock PM */
 static const struct sm_object pciexp_clk_pm = SM_DECLARE_BOOL({
 	.opt_name	= "pciexp_clk_pm",

From c3be703b717f2c9931b69480875cb6f3ef2e9827 Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Fri, 9 May 2025 12:24:15 -0500
Subject: [PATCH 1248/3886] soc/intel/common/cfr: Add bool option for auto
 power on

The tri-state power-on-after-failure options don't make sense
for all boards, so add a CFR option which allows for a simple
toggle for powering on after power loss

Change-Id: I7624f16f74c46b7b487da00d0ff669ff4c187dd6
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87982
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
---
 .../common/block/include/intelblocks/cfr.h     | 18 ++++++++++++++++--
 1 file changed, 16 insertions(+), 2 deletions(-)

diff --git a/src/soc/intel/common/block/include/intelblocks/cfr.h b/src/soc/intel/common/block/include/intelblocks/cfr.h
index 24ddf47a65..7828e1f359 100644
--- a/src/soc/intel/common/block/include/intelblocks/cfr.h
+++ b/src/soc/intel/common/block/include/intelblocks/cfr.h
@@ -31,10 +31,13 @@ static const struct sm_object me_state_counter = SM_DECLARE_NUMBER({
 	.default_value	= 0,
 });
 
-/* Power state after power loss */
+/*
+ * Power state after power loss
+ * Use this option or the one below, but not both
+ */
 static const struct sm_object power_on_after_fail = SM_DECLARE_ENUM({
 	.opt_name	= "power_on_after_fail",
-	.ui_name	= "Restore AC Power Loss",
+	.ui_name	= "Restore AC power after loss",
 	.ui_helptext	= "Specify what to do when power is re-applied after a power loss.",
 	.default_value	= CONFIG_MAINBOARD_POWER_FAILURE_STATE,
 	.values		= (const struct sm_enum_value[]) {
@@ -44,6 +47,17 @@ static const struct sm_object power_on_after_fail = SM_DECLARE_ENUM({
 				SM_ENUM_VALUE_END					},
 });
 
+/*
+ * Automatic power-on toggle
+ * Use this option or the one above, but not both
+ */
+static const struct sm_object power_on_after_fail_bool = SM_DECLARE_BOOL({
+	.opt_name	= "power_on_after_fail",
+	.ui_name	= "Power on after failure",
+	.ui_helptext	= "Automatically turn on after a power failure",
+	.default_value	= CONFIG_MAINBOARD_POWER_FAILURE_STATE,
+});
+
 /* PCIe PCH RP ASPM */
 static const struct sm_object pciexp_aspm = SM_DECLARE_ENUM({
 	.opt_name	= "pciexp_aspm",

From 3f16609ba211257752d7e2d6431dbe2c282484bf Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Fri, 2 May 2025 13:24:08 -0500
Subject: [PATCH 1249/3886] mb/starlabs/byte: Use SoC common CFR forms

Use SoC common CFR forms; select CSE_DEFAULT_OPTION_STATE_DISABLED
to keep existing behavior.

Change-Id: I5aa0d6e5a59a1f4a1fdc379d2eaf13f7acb6fa91
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87983
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/starlabs/byte_adl/Kconfig |  1 +
 src/mainboard/starlabs/byte_adl/cfr.c   | 73 +------------------------
 2 files changed, 3 insertions(+), 71 deletions(-)

diff --git a/src/mainboard/starlabs/byte_adl/Kconfig b/src/mainboard/starlabs/byte_adl/Kconfig
index a2d7c047b8..6c7250e39f 100644
--- a/src/mainboard/starlabs/byte_adl/Kconfig
+++ b/src/mainboard/starlabs/byte_adl/Kconfig
@@ -2,6 +2,7 @@ config BOARD_STARLABS_BYTE_SERIES
 	def_bool n
 	select BOARD_ROMSIZE_KB_16384
 	select CRB_TPM
+	select CSE_DEFAULT_CFR_OPTION_STATE_DISABLED
 	select DRIVERS_EFI_VARIABLE_STORE
 	select DRIVERS_INTEL_PMC
 	select DRIVERS_OPTION_CFR_ENABLED
diff --git a/src/mainboard/starlabs/byte_adl/cfr.c b/src/mainboard/starlabs/byte_adl/cfr.c
index 7dfacd6fa3..52f887bd32 100644
--- a/src/mainboard/starlabs/byte_adl/cfr.c
+++ b/src/mainboard/starlabs/byte_adl/cfr.c
@@ -1,13 +1,9 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
 #include <boot/coreboot_tables.h>
-#include <commonlib/coreboot_tables.h>
 #include <console/cfr.h>
 #include <drivers/option/cfr_frontend.h>
-#include <inttypes.h>
-#include <intelblocks/pcie_rp.h>
-#include <string.h>
-#include <types.h>
+#include <intelblocks/cfr.h>
 #include <variants.h>
 
 static const struct sm_object gna = SM_DECLARE_BOOL({
@@ -17,31 +13,6 @@ static const struct sm_object gna = SM_DECLARE_BOOL({
 	.default_value	= false,
 });
 
-static const struct sm_object me_state = SM_DECLARE_ENUM({
-	.opt_name	= "me_state",
-	.ui_name	= "Intel Management Engine",
-	.ui_helptext	= "Enable or disable the Intel Management Engine",
-	.default_value	= 1,
-	.values		= (const struct sm_enum_value[]) {
-				{ "Disabled",		1		},
-				{ "Enabled",		0		},
-				SM_ENUM_VALUE_END			},
-});
-
-static const struct sm_object me_state_counter = SM_DECLARE_NUMBER({
-	.opt_name	= "me_state_counter",
-	.ui_name	= "ME State Counter",
-	.flags		= CFR_OPTFLAG_SUPPRESS,
-	.default_value	= 0,
-});
-
-static const struct sm_object power_on_after_fail = SM_DECLARE_BOOL({
-	.opt_name	= "power_on_after_fail",
-	.ui_name	= "Power on after failure",
-	.ui_helptext	= "Automatically turn on after a power failure",
-	.default_value	= false,
-});
-
 static const struct sm_object power_profile = SM_DECLARE_ENUM({
 	.opt_name	= "power_profile",
 	.ui_name	= "Power Profile",
@@ -54,46 +25,6 @@ static const struct sm_object power_profile = SM_DECLARE_ENUM({
 				SM_ENUM_VALUE_END			},
 });
 
-static const struct sm_object pciexp_aspm = SM_DECLARE_ENUM({
-	.opt_name	= "pciexp_aspm",
-	.ui_name	= "PCI ASPM",
-	.ui_helptext	= "Controls the Active State Power Management for PCI devices."
-			  " Enabling this feature can reduce power consumption of"
-			  " PCI-connected devices during idle times.",
-	.default_value	= ASPM_L0S_L1,
-	.values		= (const struct sm_enum_value[]) {
-				{ "Disabled",		ASPM_DISABLE	},
-				{ "L0s",		ASPM_L0S	},
-				{ "L1",			ASPM_L1		},
-				{ "L0sL1",		ASPM_L0S_L1	},
-				SM_ENUM_VALUE_END			},
-});
-
-static const struct sm_object pciexp_clk_pm = SM_DECLARE_BOOL({
-	.opt_name	= "pciexp_clk_pm",
-	.ui_name	= "PCI Clock Power Management",
-	.ui_helptext	= "Enables or disables power management for the PCI clock. When"
-			  " enabled, it reduces power consumption during idle states."
-			  " This can help lower overall energy use but may impact"
-			  " performance in power-sensitive tasks.",
-	.default_value	= true,
-});
-
-static const struct sm_object pciexp_l1ss = SM_DECLARE_ENUM({
-	.opt_name	= "pciexp_l1ss",
-	.ui_name	= "PCI L1 Substates",
-	.ui_helptext	= "Controls deeper power-saving states for PCI devices."
-			  " Enabling this feature allows supported devices to achieve"
-			  " lower power states at the cost of slightly increased"
-			  " latency when exiting these states.",
-	.default_value	= L1_SS_L1_2,
-	.values		= (const struct sm_enum_value[]) {
-				{ "Disabled",		L1_SS_DISABLED	},
-				{ "L1.1",		L1_SS_L1_1	},
-				{ "L1.2",		L1_SS_L1_2	},
-				SM_ENUM_VALUE_END			},
-});
-
 static const struct sm_object vtd = SM_DECLARE_BOOL({
 	.opt_name	= "vtd",
 	.ui_name	= "VT-d",
@@ -131,7 +62,7 @@ static struct sm_obj_form processor = {
 static struct sm_obj_form power = {
 	.ui_name = "Power",
 	.obj_list = (const struct sm_object *[]) {
-		&power_on_after_fail,
+		&power_on_after_fail_bool,
 		NULL
 	},
 };

From c7a1539d8706d511fa96c3a660f1d654065d6684 Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Fri, 9 May 2025 12:38:55 -0500
Subject: [PATCH 1250/3886] mb/starlabs/lite: Use SoC common CFR forms

Use SoC common CFR forms where available.

Change-Id: I05106aca4402ec977a4593a4523dd7f30156b96c
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87984
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
---
 src/mainboard/starlabs/lite/cfr.c | 15 ++-------------
 1 file changed, 2 insertions(+), 13 deletions(-)

diff --git a/src/mainboard/starlabs/lite/cfr.c b/src/mainboard/starlabs/lite/cfr.c
index 8cfedf8224..00acbb07b7 100644
--- a/src/mainboard/starlabs/lite/cfr.c
+++ b/src/mainboard/starlabs/lite/cfr.c
@@ -1,14 +1,10 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
 #include <boot/coreboot_tables.h>
-#include <commonlib/coreboot_tables.h>
 #include <console/cfr.h>
 #include <drivers/option/cfr_frontend.h>
 #include <ec/starlabs/merlin/cfr.h>
-#include <inttypes.h>
-#include <intelblocks/pcie_rp.h>
-#include <string.h>
-#include <types.h>
+#include <intelblocks/cfr.h>
 #include <variants.h>
 
 static const struct sm_object card_reader = SM_DECLARE_BOOL({
@@ -27,13 +23,6 @@ static const struct sm_object fast_charge = SM_DECLARE_BOOL({
 });
 #endif
 
-static const struct sm_object power_on_after_fail = SM_DECLARE_BOOL({
-	.opt_name	= "power_on_after_fail",
-	.ui_name	= "Power on after failure",
-	.ui_helptext	= "Automatically turn on after a power failure",
-	.default_value	= false,
-});
-
 static const struct sm_object power_profile = SM_DECLARE_ENUM({
 	.opt_name	= "power_profile",
 	.ui_name	= "Power Profile",
@@ -96,7 +85,7 @@ static struct sm_obj_form power = {
 		#if CONFIG(EC_STARLABS_FAST_CHARGE)
 		&fast_charge,
 		#endif
-		&power_on_after_fail,
+		&power_on_after_fail_bool,
 		NULL
 	},
 };

From 644fd7b7f567e028d2340987b14d1ffd25f74448 Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Fri, 9 May 2025 12:44:43 -0500
Subject: [PATCH 1251/3886] mb/starlabs/starbook: Use SoC common CFR forms

Use SoC common CFR forms; select CSE_DEFAULT_OPTION_STATE_DISABLED
to keep existing behavior.

Change-Id: Iaf7d826ec17b7d0c4f17f6314f00537c5ca87d46
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87985
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
---
 src/mainboard/starlabs/starbook/Kconfig |  1 +
 src/mainboard/starlabs/starbook/cfr.c   | 10 ++--
 src/mainboard/starlabs/starbook/cfr.h   | 67 -------------------------
 3 files changed, 6 insertions(+), 72 deletions(-)

diff --git a/src/mainboard/starlabs/starbook/Kconfig b/src/mainboard/starlabs/starbook/Kconfig
index 723f10e1de..5abde68ec3 100644
--- a/src/mainboard/starlabs/starbook/Kconfig
+++ b/src/mainboard/starlabs/starbook/Kconfig
@@ -2,6 +2,7 @@
 
 config BOARD_STARLABS_STARBOOK_SERIES
 	def_bool n
+	select CSE_DEFAULT_CFR_OPTION_STATE_DISABLED
 	select DRIVERS_EFI_VARIABLE_STORE
 	select DRIVERS_OPTION_CFR_ENABLED
 	select DRIVERS_I2C_HID
diff --git a/src/mainboard/starlabs/starbook/cfr.c b/src/mainboard/starlabs/starbook/cfr.c
index de8ad2eeb0..de532918e4 100644
--- a/src/mainboard/starlabs/starbook/cfr.c
+++ b/src/mainboard/starlabs/starbook/cfr.c
@@ -1,13 +1,10 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
 #include <boot/coreboot_tables.h>
-#include <commonlib/coreboot_tables.h>
 #include <console/cfr.h>
 #include <drivers/option/cfr_frontend.h>
 #include <ec/starlabs/merlin/cfr.h>
-#include <inttypes.h>
-#include <string.h>
-#include <types.h>
+#include <intelblocks/cfr.h>
 #include "cfr.h"
 
 static struct sm_obj_form performance = {
@@ -40,7 +37,7 @@ static struct sm_obj_form power = {
 		#if CONFIG(EC_STARLABS_CHARGING_SPEED)
 		&charging_speed,
 		#endif
-		&power_on_after_fail,
+		&power_on_after_fail_bool,
 		NULL
 	},
 };
@@ -92,6 +89,9 @@ static struct sm_obj_form pci = {
 		#if CONFIG(SOC_INTEL_COMMON_BLOCK_ASPM)
 		&pciexp_clk_pm,
 		&pciexp_aspm,
+		#if CONFIG(HAS_INTEL_CPU_ROOT_PORTS)
+		&pciexp_aspm_cpu,
+		#endif
 		&pciexp_l1ss,
 		#endif
 		NULL
diff --git a/src/mainboard/starlabs/starbook/cfr.h b/src/mainboard/starlabs/starbook/cfr.h
index fe1a01e93c..0496ef08a4 100644
--- a/src/mainboard/starlabs/starbook/cfr.h
+++ b/src/mainboard/starlabs/starbook/cfr.h
@@ -5,7 +5,6 @@
 #define _STARBOOK_CFR_H_
 
 #include <drivers/option/cfr_frontend.h>
-#include <intelblocks/pcie_rp.h>
 #include <variants.h>
 
 static const struct sm_object card_reader = SM_DECLARE_BOOL({
@@ -36,31 +35,6 @@ static const struct sm_object hyper_threading = SM_DECLARE_BOOL({
 	.default_value	= true,
 });
 
-static const struct sm_object me_state = SM_DECLARE_ENUM({
-	.opt_name	= "me_state",
-	.ui_name	= "Intel Management Engine",
-	.ui_helptext	= "Enable or disable the Intel Management Engine",
-	.default_value	= 1,
-	.values		= (const struct sm_enum_value[]) {
-				{ "Disabled",		1		},
-				{ "Enabled",		0		},
-				SM_ENUM_VALUE_END			},
-});
-
-static const struct sm_object me_state_counter = SM_DECLARE_NUMBER({
-	.opt_name	= "me_state_counter",
-	.ui_name	= "ME State Counter",
-	.flags		= CFR_OPTFLAG_SUPPRESS,
-	.default_value	= 0,
-});
-
-static const struct sm_object power_on_after_fail = SM_DECLARE_BOOL({
-	.opt_name	= "power_on_after_fail",
-	.ui_name	= "Power on after failure",
-	.ui_helptext	= "Automatically turn on after a power failure",
-	.default_value	= false,
-});
-
 static const struct sm_object power_profile = SM_DECLARE_ENUM({
 	.opt_name	= "power_profile",
 	.ui_name	= "Power Profile",
@@ -88,46 +62,6 @@ static const struct sm_object pci_hot_plug = SM_DECLARE_BOOL({
 	.default_value	= false,
 });
 
-static const struct sm_object pciexp_aspm = SM_DECLARE_ENUM({
-	.opt_name	= "pciexp_aspm",
-	.ui_name	= "PCI ASPM",
-	.ui_helptext	= "Controls the Active State Power Management for PCI devices."
-			  " Enabling this feature can reduce power consumption of"
-			  " PCI-connected devices during idle times.",
-	.default_value	= ASPM_L0S_L1,
-	.values		= (const struct sm_enum_value[]) {
-				{ "Disabled",		ASPM_DISABLE	},
-				{ "L0s",		ASPM_L0S	},
-				{ "L1",			ASPM_L1		},
-				{ "L0sL1",		ASPM_L0S_L1	},
-				SM_ENUM_VALUE_END			},
-});
-
-static const struct sm_object pciexp_clk_pm = SM_DECLARE_BOOL({
-	.opt_name	= "pciexp_clk_pm",
-	.ui_name	= "PCI Clock Power Management",
-	.ui_helptext	= "Enables or disables power management for the PCI clock. When"
-			  " enabled, it reduces power consumption during idle states."
-			  " This can help lower overall energy use but may impact"
-			  " performance in power-sensitive tasks.",
-	.default_value	= true,
-});
-
-static const struct sm_object pciexp_l1ss = SM_DECLARE_ENUM({
-	.opt_name	= "pciexp_l1ss",
-	.ui_name	= "PCI L1 Substates",
-	.ui_helptext	= "Controls deeper power-saving states for PCI devices."
-			  " Enabling this feature allows supported devices to achieve"
-			  " lower power states at the cost of slightly increased"
-			  " latency when exiting these states.",
-	.default_value	= L1_SS_L1_2,
-	.values		= (const struct sm_enum_value[]) {
-				{ "Disabled",		L1_SS_DISABLED	},
-				{ "L1.1",		L1_SS_L1_1	},
-				{ "L1.2",		L1_SS_L1_2	},
-				SM_ENUM_VALUE_END			},
-});
-
 static const struct sm_object thunderbolt = SM_DECLARE_BOOL({
 	.opt_name	= "thunderbolt",
 	.ui_name	= "Thunderbolt",
@@ -135,7 +69,6 @@ static const struct sm_object thunderbolt = SM_DECLARE_BOOL({
 	.default_value	= true,
 });
 
-
 static const struct sm_object vpu = SM_DECLARE_BOOL({
 	.opt_name	= "vpu",
 	.ui_name	= "VPU",

From 808c98210418468ca55bfdfb9303aa51a8ee8934 Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Fri, 9 May 2025 12:54:37 -0500
Subject: [PATCH 1252/3886] mb/starlabs/starfighter: Use SoC common CFR forms

Use SoC common CFR forms; select CSE_DEFAULT_OPTION_STATE_DISABLED
to keep existing behavior.

Change-Id: I66ce9a10fa4560949d196730f7adb2dc4d46cef5
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87986
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
---
 src/mainboard/starlabs/starfighter/Kconfig |  1 +
 src/mainboard/starlabs/starfighter/cfr.c   | 79 ++--------------------
 2 files changed, 7 insertions(+), 73 deletions(-)

diff --git a/src/mainboard/starlabs/starfighter/Kconfig b/src/mainboard/starlabs/starfighter/Kconfig
index 19e0161abc..2d9d0bead6 100644
--- a/src/mainboard/starlabs/starfighter/Kconfig
+++ b/src/mainboard/starlabs/starfighter/Kconfig
@@ -3,6 +3,7 @@
 config BOARD_STARLABS_STARFIGHTER_SERIES
 	def_bool n
 	select BOARD_ROMSIZE_KB_32768
+	select CSE_DEFAULT_CFR_OPTION_STATE_DISABLED
 	select DRIVERS_EFI_VARIABLE_STORE
 	select DRIVERS_OPTION_CFR_ENABLED
 	select DRIVERS_GFX_GENERIC
diff --git a/src/mainboard/starlabs/starfighter/cfr.c b/src/mainboard/starlabs/starfighter/cfr.c
index bb0c34b83f..b69ff2b134 100644
--- a/src/mainboard/starlabs/starfighter/cfr.c
+++ b/src/mainboard/starlabs/starfighter/cfr.c
@@ -1,14 +1,10 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
 #include <boot/coreboot_tables.h>
-#include <commonlib/coreboot_tables.h>
 #include <console/cfr.h>
 #include <drivers/option/cfr_frontend.h>
 #include <ec/starlabs/merlin/cfr.h>
-#include <inttypes.h>
-#include <intelblocks/pcie_rp.h>
-#include <string.h>
-#include <types.h>
+#include <intelblocks/cfr.h>
 #include <variants.h>
 
 #if CONFIG(SOC_INTEL_TIGERLAKE) || CONFIG(SOC_INTEL_ALDERLAKE) || CONFIG(SOC_INTEL_RAPTORLAKE)
@@ -27,30 +23,6 @@ static const struct sm_object hyper_threading = SM_DECLARE_BOOL({
 	.default_value	= true,
 });
 
-static const struct sm_object me_state = SM_DECLARE_ENUM({
-	.opt_name	= "me_state",
-	.ui_name	= "Intel Management Engine",
-	.ui_helptext	= "Enable or disable the Intel Management Engine",
-	.default_value	= 1,
-	.values		= (const struct sm_enum_value[]) {
-				{ "Disabled",		1		},
-				{ "Enabled",		0		},
-				SM_ENUM_VALUE_END			},
-});
-
-static const struct sm_object me_state_counter = SM_DECLARE_NUMBER({
-	.opt_name	= "me_state_counter",
-	.ui_name	= "ME State Counter",
-	.flags		= CFR_OPTFLAG_SUPPRESS,
-	.default_value	= 0,
-});
-
-static const struct sm_object power_on_after_fail = SM_DECLARE_BOOL({
-	.opt_name	= "power_on_after_fail",
-	.ui_name	= "Power on after failure",
-	.ui_helptext	= "Automatically turn on after a power failure",
-	.default_value	= false,
-});
 
 static const struct sm_object power_profile = SM_DECLARE_ENUM({
 	.opt_name	= "power_profile",
@@ -64,48 +36,6 @@ static const struct sm_object power_profile = SM_DECLARE_ENUM({
 				SM_ENUM_VALUE_END			},
 });
 
-#if CONFIG(SOC_INTEL_ALDERLAKE)
-static const struct sm_object pciexp_aspm = SM_DECLARE_ENUM({
-	.opt_name	= "pciexp_aspm",
-	.ui_name	= "PCI ASPM",
-	.ui_helptext	= "Controls the Active State Power Management for PCI devices."
-			  " Enabling this feature can reduce power consumption of"
-			  " PCI-connected devices during idle times.",
-	.default_value	= ASPM_L0S_L1,
-	.values		= (const struct sm_enum_value[]) {
-				{ "Disabled",		ASPM_DISABLE	},
-				{ "L0s",		ASPM_L0S	},
-				{ "L1",			ASPM_L1		},
-				{ "L0sL1",		ASPM_L0S_L1	},
-				SM_ENUM_VALUE_END			},
-});
-
-static const struct sm_object pciexp_clk_pm = SM_DECLARE_BOOL({
-	.opt_name	= "pciexp_clk_pm",
-	.ui_name	= "PCI Clock Power Management",
-	.ui_helptext	= "Enables or disables power management for the PCI clock. When"
-			  " enabled, it reduces power consumption during idle states."
-			  " This can help lower overall energy use but may impact"
-			  " performance in power-sensitive tasks.",
-	.default_value	= true,
-});
-
-static const struct sm_object pciexp_l1ss = SM_DECLARE_ENUM({
-	.opt_name	= "pciexp_l1ss",
-	.ui_name	= "PCI L1 Substates",
-	.ui_helptext	= "Controls deeper power-saving states for PCI devices."
-			  " Enabling this feature allows supported devices to achieve"
-			  " lower power states at the cost of slightly increased"
-			  " latency when exiting these states.",
-	.default_value	= L1_SS_L1_2,
-	.values		= (const struct sm_enum_value[]) {
-				{ "Disabled",		L1_SS_DISABLED	},
-				{ "L1.1",		L1_SS_L1_1	},
-				{ "L1.2",		L1_SS_L1_2	},
-				SM_ENUM_VALUE_END			},
-});
-#endif
-
 #if CONFIG(DRIVERS_INTEL_USB4_RETIMER)
 static const struct sm_object thunderbolt = SM_DECLARE_BOOL({
 	.opt_name	= "thunderbolt",
@@ -166,7 +96,7 @@ static struct sm_obj_form power = {
 		#if CONFIG(EC_STARLABS_CHARGING_SPEED)
 		&charging_speed,
 		#endif
-		&power_on_after_fail,
+		&power_on_after_fail_bool,
 		NULL
 	},
 };
@@ -200,9 +130,12 @@ static struct sm_obj_form devices = {
 static struct sm_obj_form pci = {
 	.ui_name = "PCI",
 	.obj_list = (const struct sm_object *[]) {
-		#if CONFIG(SOC_INTEL_ALDERLAKE)
+		#if CONFIG(SOC_INTEL_COMMON_BLOCK_ASPM)
 		&pciexp_clk_pm,
 		&pciexp_aspm,
+		#if CONFIG(HAS_INTEL_CPU_ROOT_PORTS)
+		&pciexp_aspm_cpu,
+		#endif
 		&pciexp_l1ss,
 		#endif
 		NULL

From dc3d524d19c11a076c9751927e05e09802e6c558 Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Mon, 12 May 2025 15:22:14 -0500
Subject: [PATCH 1253/3886] mb/starlabs/starlite_adl: Use SoC common CFR forms

Use SoC common CFR forms; select CSE_DEFAULT_OPTION_STATE_DISABLED
to keep existing behavior.

Change-Id: I63cea721e5678a979bdb51c935b36d3149e067c9
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87987
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/starlabs/starlite_adl/Kconfig |  1 +
 src/mainboard/starlabs/starlite_adl/cfr.c   | 77 +--------------------
 2 files changed, 4 insertions(+), 74 deletions(-)

diff --git a/src/mainboard/starlabs/starlite_adl/Kconfig b/src/mainboard/starlabs/starlite_adl/Kconfig
index 897b5a28fd..c228a22d5d 100644
--- a/src/mainboard/starlabs/starlite_adl/Kconfig
+++ b/src/mainboard/starlabs/starlite_adl/Kconfig
@@ -2,6 +2,7 @@ config BOARD_STARLABS_STARLITE_SERIES
 	def_bool n
 	select BOARD_ROMSIZE_KB_16384
 	select CRB_TPM
+	select CSE_DEFAULT_CFR_OPTION_STATE_DISABLED
 	select DRIVERS_EFI_VARIABLE_STORE
 	select DRIVERS_GFX_GENERIC
 	select DRIVERS_I2C_HID
diff --git a/src/mainboard/starlabs/starlite_adl/cfr.c b/src/mainboard/starlabs/starlite_adl/cfr.c
index e1c86cf17f..4f0c6672d7 100644
--- a/src/mainboard/starlabs/starlite_adl/cfr.c
+++ b/src/mainboard/starlabs/starlite_adl/cfr.c
@@ -1,14 +1,10 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
 #include <boot/coreboot_tables.h>
-#include <commonlib/coreboot_tables.h>
 #include <console/cfr.h>
 #include <drivers/option/cfr_frontend.h>
 #include <ec/starlabs/merlin/cfr.h>
-#include <inttypes.h>
-#include <intelblocks/pcie_rp.h>
-#include <string.h>
-#include <types.h>
+#include <intelblocks/cfr.h>
 #include <variants.h>
 
 static const struct sm_object accelerometer = SM_DECLARE_BOOL({
@@ -27,24 +23,6 @@ static const struct sm_object gna = SM_DECLARE_BOOL({
 });
 #endif
 
-static const struct sm_object me_state = SM_DECLARE_ENUM({
-	.opt_name	= "me_state",
-	.ui_name	= "Intel Management Engine",
-	.ui_helptext	= "Enable or disable the Intel Management Engine",
-	.default_value	= 1,
-	.values		= (const struct sm_enum_value[]) {
-				{ "Disabled",		1		},
-				{ "Enabled",		0		},
-				SM_ENUM_VALUE_END			},
-});
-
-static const struct sm_object me_state_counter = SM_DECLARE_NUMBER({
-	.opt_name	= "me_state_counter",
-	.ui_name	= "ME State Counter",
-	.flags		= CFR_OPTFLAG_SUPPRESS,
-	.default_value	= 0,
-});
-
 static const struct sm_object memory_speed = SM_DECLARE_ENUM({
 	.opt_name	= "memory_speed",
 	.ui_name	= "Memory Speed",
@@ -58,13 +36,6 @@ static const struct sm_object memory_speed = SM_DECLARE_ENUM({
 	}
 });
 
-static const struct sm_object power_on_after_fail = SM_DECLARE_BOOL({
-	.opt_name	= "power_on_after_fail",
-	.ui_name	= "Power on after failure",
-	.ui_helptext	= "Automatically turn on after a power failure",
-	.default_value	= false,
-});
-
 static const struct sm_object power_profile = SM_DECLARE_ENUM({
 	.opt_name	= "power_profile",
 	.ui_name	= "Power Profile",
@@ -84,48 +55,6 @@ static const struct sm_object microphone = SM_DECLARE_BOOL({
 	.default_value	= true,
 });
 
-#if CONFIG(SOC_INTEL_ALDERLAKE)
-static const struct sm_object pciexp_aspm = SM_DECLARE_ENUM({
-	.opt_name	= "pciexp_aspm",
-	.ui_name	= "PCI ASPM",
-	.ui_helptext	= "Controls the Active State Power Management for PCI devices."
-			  " Enabling this feature can reduce power consumption of"
-			  " PCI-connected devices during idle times.",
-	.default_value	= ASPM_L0S_L1,
-	.values		= (const struct sm_enum_value[]) {
-				{ "Disabled",		ASPM_DISABLE	},
-				{ "L0s",		ASPM_L0S	},
-				{ "L1",			ASPM_L1		},
-				{ "L0sL1",		ASPM_L0S_L1	},
-				SM_ENUM_VALUE_END			},
-});
-
-static const struct sm_object pciexp_clk_pm = SM_DECLARE_BOOL({
-	.opt_name	= "pciexp_clk_pm",
-	.ui_name	= "PCI Clock Power Management",
-	.ui_helptext	= "Enables or disables power management for the PCI clock. When"
-			  " enabled, it reduces power consumption during idle states."
-			  " This can help lower overall energy use but may impact"
-			  " performance in power-sensitive tasks.",
-	.default_value	= true,
-});
-
-static const struct sm_object pciexp_l1ss = SM_DECLARE_ENUM({
-	.opt_name	= "pciexp_l1ss",
-	.ui_name	= "PCI L1 Substates",
-	.ui_helptext	= "Controls deeper power-saving states for PCI devices."
-			  " Enabling this feature allows supported devices to achieve"
-			  " lower power states at the cost of slightly increased"
-			  " latency when exiting these states.",
-	.default_value	= L1_SS_L1_2,
-	.values		= (const struct sm_enum_value[]) {
-				{ "Disabled",		L1_SS_DISABLED	},
-				{ "L1.1",		L1_SS_L1_1	},
-				{ "L1.2",		L1_SS_L1_2	},
-				SM_ENUM_VALUE_END			},
-});
-#endif
-
 static const struct sm_object touchscreen = SM_DECLARE_BOOL({
 	.opt_name	= "touchscreen",
 	.ui_name	= "Touchscreen",
@@ -198,7 +127,7 @@ static struct sm_obj_form power = {
 		&charging_speed,
 		#endif
 		&power_led,
-		&power_on_after_fail,
+		&power_on_after_fail_bool,
 		NULL
 	},
 };
@@ -225,7 +154,7 @@ static struct sm_obj_form devices = {
 static struct sm_obj_form pci = {
 	.ui_name = "PCI",
 	.obj_list = (const struct sm_object *[]) {
-		#if CONFIG(SOC_INTEL_ALDERLAKE)
+		#if CONFIG(SOC_INTEL_COMMON_BLOCK_ASPM)
 		&pciexp_clk_pm,
 		&pciexp_aspm,
 		&pciexp_l1ss,

From 47f2c179619f6901820d3b4effb21a30747125b9 Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Fri, 9 May 2025 13:00:51 -0500
Subject: [PATCH 1254/3886] mb/starlabs/*: Add CFR option to enable/disable
 S0ix

The option hooks are already set up at the SoC level, so
just add a new CFR form to expose the configuration.

Change-Id: I423e6b617ba60d7e44064ad9f4c3fec7e3e3fe75
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87988
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
---
 src/mainboard/starlabs/byte_adl/cfr.c     | 11 +++++++++++
 src/mainboard/starlabs/lite/cfr.c         | 11 +++++++++++
 src/mainboard/starlabs/starbook/cfr.c     |  1 +
 src/mainboard/starlabs/starbook/cfr.h     | 10 ++++++++++
 src/mainboard/starlabs/starfighter/cfr.c  | 11 +++++++++++
 src/mainboard/starlabs/starlite_adl/cfr.c | 11 +++++++++++
 6 files changed, 55 insertions(+)

diff --git a/src/mainboard/starlabs/byte_adl/cfr.c b/src/mainboard/starlabs/byte_adl/cfr.c
index 52f887bd32..3e22595079 100644
--- a/src/mainboard/starlabs/byte_adl/cfr.c
+++ b/src/mainboard/starlabs/byte_adl/cfr.c
@@ -40,6 +40,16 @@ static const struct sm_object bluetooth_rtd3 = SM_DECLARE_BOOL({
 	.default_value	= true,
 });
 
+static const struct sm_object s0ix_enable = SM_DECLARE_BOOL({
+	.opt_name	= "s0ix_enable",
+	.ui_name	= "Modern Standby (S0ix)",
+	.ui_helptext	= "Enabled: Use S0ix for device sleep.\n"
+			  "Disabled: Use ACPI S3 for device sleep.\n"
+			  "Requires Intel ME to be enabled.\n"
+			  "Recommended: Enabled when booting Windows, disabled otherwise.",
+	.default_value	= false,
+});
+
 static struct sm_obj_form performance = {
 	.ui_name = "Performance",
 	.obj_list = (const struct sm_object *[]) {
@@ -54,6 +64,7 @@ static struct sm_obj_form processor = {
 	.obj_list = (const struct sm_object *[]) {
 		&me_state,
 		&me_state_counter,
+		&s0ix_enable,
 		&vtd,
 		NULL
 	},
diff --git a/src/mainboard/starlabs/lite/cfr.c b/src/mainboard/starlabs/lite/cfr.c
index 00acbb07b7..8423a04afa 100644
--- a/src/mainboard/starlabs/lite/cfr.c
+++ b/src/mainboard/starlabs/lite/cfr.c
@@ -63,6 +63,16 @@ static const struct sm_object vtd = SM_DECLARE_BOOL({
 	.default_value	= true,
 });
 
+static const struct sm_object s0ix_enable = SM_DECLARE_BOOL({
+	.opt_name	= "s0ix_enable",
+	.ui_name	= "Modern Standby (S0ix)",
+	.ui_helptext	= "Enabled: Use S0ix for device sleep.\n"
+			  "Disabled: Use ACPI S3 for device sleep.\n"
+			  "Requires Intel ME to be enabled.\n"
+			  "Recommended: Enabled when booting Windows, disabled otherwise.",
+	.default_value	= false,
+});
+
 static struct sm_obj_form performance = {
 	.ui_name = "Performance",
 	.obj_list = (const struct sm_object *[]) {
@@ -74,6 +84,7 @@ static struct sm_obj_form performance = {
 static struct sm_obj_form processor = {
 	.ui_name = "Processor",
 	.obj_list = (const struct sm_object *[]) {
+		&s0ix_enable,
 		&vtd,
 		NULL
 	},
diff --git a/src/mainboard/starlabs/starbook/cfr.c b/src/mainboard/starlabs/starbook/cfr.c
index de532918e4..fb3605cfdd 100644
--- a/src/mainboard/starlabs/starbook/cfr.c
+++ b/src/mainboard/starlabs/starbook/cfr.c
@@ -25,6 +25,7 @@ static struct sm_obj_form processor = {
 		#if CONFIG(BOARD_SUPPORTS_HT)
 		&hyper_threading,
 		#endif
+		&s0ix_enable,
 		&vtd,
 		NULL
 	},
diff --git a/src/mainboard/starlabs/starbook/cfr.h b/src/mainboard/starlabs/starbook/cfr.h
index 0496ef08a4..ddf1d15e1b 100644
--- a/src/mainboard/starlabs/starbook/cfr.h
+++ b/src/mainboard/starlabs/starbook/cfr.h
@@ -113,4 +113,14 @@ static const struct sm_object display_native_res = SM_DECLARE_BOOL({
 	.default_value	= false,
 });
 
+static const struct sm_object s0ix_enable = SM_DECLARE_BOOL({
+	.opt_name	= "s0ix_enable",
+	.ui_name	= "Modern Standby (S0ix)",
+	.ui_helptext	= "Enabled: Use S0ix for device sleep.\n"
+			  "Disabled: Use ACPI S3 for device sleep.\n"
+			  "Requires Intel ME to be enabled.\n"
+			  "Recommended: Enabled when booting Windows, disabled otherwise.",
+	.default_value	= false,
+});
+
 #endif /* _STARBOOK_CFR_H_ */
diff --git a/src/mainboard/starlabs/starfighter/cfr.c b/src/mainboard/starlabs/starfighter/cfr.c
index b69ff2b134..d54ff0de07 100644
--- a/src/mainboard/starlabs/starfighter/cfr.c
+++ b/src/mainboard/starlabs/starfighter/cfr.c
@@ -68,6 +68,16 @@ static const struct sm_object display_native_res = SM_DECLARE_BOOL({
 	.default_value	= false,
 });
 
+static const struct sm_object s0ix_enable = SM_DECLARE_BOOL({
+	.opt_name	= "s0ix_enable",
+	.ui_name	= "Modern Standby (S0ix)",
+	.ui_helptext	= "Enabled: Use S0ix for device sleep.\n"
+			  "Disabled: Use ACPI S3 for device sleep.\n"
+			  "Requires Intel ME to be enabled.\n"
+			  "Recommended: Enabled when booting Windows, disabled otherwise.",
+	.default_value	= false,
+});
+
 static struct sm_obj_form performance = {
 	.ui_name = "Performance",
 	.obj_list = (const struct sm_object *[]) {
@@ -84,6 +94,7 @@ static struct sm_obj_form processor = {
 		&me_state,
 		&me_state_counter,
 		&hyper_threading,
+		&s0ix_enable,
 		&vtd,
 		NULL
 	},
diff --git a/src/mainboard/starlabs/starlite_adl/cfr.c b/src/mainboard/starlabs/starlite_adl/cfr.c
index 4f0c6672d7..2e36e99b6f 100644
--- a/src/mainboard/starlabs/starlite_adl/cfr.c
+++ b/src/mainboard/starlabs/starlite_adl/cfr.c
@@ -99,6 +99,16 @@ static const struct sm_object display_native_res = SM_DECLARE_BOOL({
 	.default_value	= false,
 });
 
+static const struct sm_object s0ix_enable = SM_DECLARE_BOOL({
+	.opt_name	= "s0ix_enable",
+	.ui_name	= "Modern Standby (S0ix)",
+	.ui_helptext	= "Enabled: Use S0ix for device sleep.\n"
+			  "Disabled: Use ACPI S3 for device sleep.\n"
+			  "Requires Intel ME to be enabled.\n"
+			  "Recommended: Enabled when booting Windows, disabled otherwise.",
+	.default_value	= false,
+});
+
 static struct sm_obj_form performance = {
 	.ui_name = "Performance",
 	.obj_list = (const struct sm_object *[]) {
@@ -114,6 +124,7 @@ static struct sm_obj_form processor = {
 	.obj_list = (const struct sm_object *[]) {
 		&me_state,
 		&me_state_counter,
+		&s0ix_enable,
 		&vtd,
 		NULL
 	},

From 7e711a5bef7fe6fa53d7564bf9003718cbc8b20d Mon Sep 17 00:00:00 2001
From: Yidi Lin <yidilin@google.com>
Date: Sat, 7 Jun 2025 07:10:59 +0000
Subject: [PATCH 1255/3886] Reland "soc/mediatek/mt8196: Specify MTKLIB_PATH
 for building BL31"

This reverts commit 7814b8a6bec6e7777033bfd9785b9012b52a73f6.

Reason for revert: The dependent patches are landed.
CB:87976 da54093bb9  "Update arm-trusted-firmware submodule to upstream master"
CB:87882 5dc4b47 "soc/mediatek/mt8196: Update libbl31.a to version 16297.0.0"

BUG=b:412560091, b:414543140

Change-Id: Ie34683118f99940185f9d637f5e1953b5250cde0
Signed-off-by: Yidi Lin <yidilin@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87994
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
---
 src/soc/mediatek/mt8196/Makefile.mk | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/src/soc/mediatek/mt8196/Makefile.mk b/src/soc/mediatek/mt8196/Makefile.mk
index 5240fbb2bb..9cf46ac809 100644
--- a/src/soc/mediatek/mt8196/Makefile.mk
+++ b/src/soc/mediatek/mt8196/Makefile.mk
@@ -96,6 +96,12 @@ CPPFLAGS_common += -Isrc/soc/mediatek/common/dp/include
 
 MT8196_BLOB_DIR := 3rdparty/blobs/soc/mediatek/mt8196
 
+BL31_LIB := $(top)/$(MT8196_BLOB_DIR)/libbl31.a
+
+ifneq ($(wildcard $(BL31_LIB)),)
+BL31_MAKEARGS += MTKLIB_PATH=$(BL31_LIB)
+endif
+
 PI_IMG := $(MT8196_BLOB_DIR)/$(call strip_quotes,$(CONFIG_PI_IMG_FIRMWARE))
 
 .PHONY: check_pi_img

From 2c0417ea06f361e39f6a17208d42d65afa524f52 Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Thu, 5 Jun 2025 17:22:15 +0100
Subject: [PATCH 1256/3886] mb/starlabs/starlite_adl: Remove duplicate GPP_E12
 entry

Was masking the correct value set previously.

Change-Id: Ibe88fe4ad0de68b1188ec6a526497d5c0d75e56f
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87990
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/starlabs/starlite_adl/variants/mk_v/gpio.c | 1 -
 1 file changed, 1 deletion(-)

diff --git a/src/mainboard/starlabs/starlite_adl/variants/mk_v/gpio.c b/src/mainboard/starlabs/starlite_adl/variants/mk_v/gpio.c
index 8e2466f47c..09cd782f54 100644
--- a/src/mainboard/starlabs/starlite_adl/variants/mk_v/gpio.c
+++ b/src/mainboard/starlabs/starlite_adl/variants/mk_v/gpio.c
@@ -190,7 +190,6 @@ const struct pad_config gpio_table[] = {
 	PAD_NC(GPP_E9, NONE),
 	PAD_NC(GPP_E10, NONE),
 	PAD_NC(GPP_E11, NONE),
-	PAD_NC(GPP_E12, NONE),
 	PAD_NC(GPP_E13, NONE),
 	PAD_NC(GPP_E15, NONE),
 	PAD_NC(GPP_E16, NONE),

From d14a3e23dad0b25613a70448952254d96ac3d87b Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Fri, 6 Jun 2025 18:38:35 -0500
Subject: [PATCH 1257/3886] mb/starlabs/starlite_adl: Clarify pmc_gpe0_dw0
 mapping in devicetree

PMC_GPP_F and GPP_F resolve to the same thing, but use the latter for
consistency and clarity. Non-functional change.

Change-Id: I005221cf7289ad2090b4231755d2eb4766bf67fe
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87992
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/starlabs/starlite_adl/variants/mk_v/devicetree.cb | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/mainboard/starlabs/starlite_adl/variants/mk_v/devicetree.cb b/src/mainboard/starlabs/starlite_adl/variants/mk_v/devicetree.cb
index bb9ab534b2..862f31fa5c 100644
--- a/src/mainboard/starlabs/starlite_adl/variants/mk_v/devicetree.cb
+++ b/src/mainboard/starlabs/starlite_adl/variants/mk_v/devicetree.cb
@@ -32,7 +32,7 @@ chip soc/intel/alderlake
 	register "pch_slp_a_min_assertion_width"	= "SLP_A_ASSERTION_98_MS"
 
 	# PM Util
-	register "pmc_gpe0_dw0"			= "PMC_GPP_F"
+	register "pmc_gpe0_dw0"			= "GPP_F"
 	register "pmc_gpe0_dw1"			= "GPP_A"
 	register "pmc_gpe0_dw2"			= "GPP_B"
 

From 26fd33a92aff0096abf56de9a8675d6f0d1a84c1 Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Fri, 6 Jun 2025 18:42:35 -0500
Subject: [PATCH 1258/3886] mb/starlabs/starlite_adl/acpi: Fix _GPE callback
 type

The GPIO which is used to determine whether the keyboard is connected
or not is dual-edge triggered, not level triggered, so adjust the
method name to reflect that. This ensures that the keyboard status
is updated on both connection and disconnection.

TEST=build/boot starlite_adl, verify tablet mode is correctly detected
when the keyboard is detached under both Windows and Linux.

Change-Id: I6c539fa264a2910589846e58d851acbe7c00900e
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87993
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
---
 src/mainboard/starlabs/starlite_adl/acpi/mainboard.asl | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/mainboard/starlabs/starlite_adl/acpi/mainboard.asl b/src/mainboard/starlabs/starlite_adl/acpi/mainboard.asl
index de4f6f6807..f9d095244a 100644
--- a/src/mainboard/starlabs/starlite_adl/acpi/mainboard.asl
+++ b/src/mainboard/starlabs/starlite_adl/acpi/mainboard.asl
@@ -6,7 +6,7 @@ Scope (\_SB) {
 
 Scope (_GPE)
 {
-	Method (_L0F, 0, NotSerialized)
+	Method (_E0F, 0, NotSerialized)
 	{
 		\_SB.PCI0.LPCB.EC.VBTN.UPDK()
 	}

From 40bf6c28f8274fcac73c77221b065eb78a3d6303 Mon Sep 17 00:00:00 2001
From: Liu Liu <ot_liu.liu@mediatek.corp-partner.google.com>
Date: Thu, 5 Jun 2025 17:14:41 +0800
Subject: [PATCH 1259/3886] soc/mediatek/mt8189: Add support for USB port 0
 reset

USB port 0 (P0) is force_suspended during the BootROM stage, and this
state won't be cleared in subsequent stages, causing P0 to become
unusable. Adding the P0 controller in coreboot ensures that the
force_suspended state is cleared, restoring P0 functionality. This
action requires setting the necessary register addresses, which is
handled by setup_usb_secondary_host().

BUG=b:417079837
BRANCH=None
TEST=Build passes and insert a USB device into USB port 0 can enumerate
     the USB device.

Signed-off-by: Liu Liu <ot_liu.liu@mediatek.corp-partner.google.com>
Change-Id: I98534a833b344156a0e76e76ad7be88f98b2a967
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87977
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
---
 src/soc/mediatek/mt8189/Makefile.mk              | 2 +-
 src/soc/mediatek/mt8189/include/soc/addressmap.h | 2 ++
 2 files changed, 3 insertions(+), 1 deletion(-)

diff --git a/src/soc/mediatek/mt8189/Makefile.mk b/src/soc/mediatek/mt8189/Makefile.mk
index 2051622bb5..1014d1959c 100644
--- a/src/soc/mediatek/mt8189/Makefile.mk
+++ b/src/soc/mediatek/mt8189/Makefile.mk
@@ -52,7 +52,7 @@ ramstage-y += ../common/rtc.c ../common/rtc_mt6359p.c ../common/rtc_osc_init.c
 ramstage-y += soc.c
 ramstage-y += ../common/spm.c ../common/spm_v2.c spm.c
 ramstage-y += ../common/sspm.c ../common/sspm_sram.c
-ramstage-y += ../common/usb.c usb.c
+ramstage-y += ../common/usb.c ../common/usb_secondary.c usb.c
 
 BL31_MAKEARGS += PLAT=mt8189
 
diff --git a/src/soc/mediatek/mt8189/include/soc/addressmap.h b/src/soc/mediatek/mt8189/include/soc/addressmap.h
index 1f91d03ff9..2e24c1dde6 100644
--- a/src/soc/mediatek/mt8189/include/soc/addressmap.h
+++ b/src/soc/mediatek/mt8189/include/soc/addressmap.h
@@ -59,6 +59,7 @@ enum {
 	PERICFG_AO_BASE			= IO_PHYS + 0x01036000,
 	DEVAPC_PERI_PAR_AO_BASE		= IO_PHYS + 0x0103C000,
 	AUDIO_BASE			= IO_PHYS + 0x01050000,
+	SSUSB_IPPC_BASE_P0		= IO_PHYS + 0x01203E00,
 	MSDC0_BASE			= IO_PHYS + 0x01230000,
 	SSUSB_IPPC_BASE			= IO_PHYS + 0x01263E00,
 	UFSHCI_BASE			= IO_PHYS + 0x012B0000,
@@ -85,6 +86,7 @@ enum {
 	I2C4_BASE			= IO_PHYS + 0x01D71000,
 	I2C5_BASE			= IO_PHYS + 0x01D72000,
 	I2C6_BASE			= IO_PHYS + 0x01D73000,
+	SSUSB_SIF_BASE_P0		= IO_PHYS + 0x01E80300,
 	I2C7_BASE			= IO_PHYS + 0x01F30000,
 	I2C8_BASE			= IO_PHYS + 0x01F31000,
 	IMP_IIC_WRAP_E_BASE		= IO_PHYS + 0x01C22000,

From d00f5c2d8cc41168aa3479b27e18b604cd3bc303 Mon Sep 17 00:00:00 2001
From: Liu Liu <ot_liu.liu@mediatek.corp-partner.google.com>
Date: Thu, 5 Jun 2025 17:36:55 +0800
Subject: [PATCH 1260/3886] mb/google/skywalker: Reset xsphy0 in mainboard_init

USB port 0 (P0) is force_suspended during the BootROM stage, and this
state won't be cleared in subsequent stages, causing P0 to become
unusable. Adding the P0 controller in coreboot ensures that the
force_suspended state is cleared, restoring P0 functionality.

BUG=b:417079837
BRANCH=None
TEST=Build passes and insert a USB device into USB port 0 can enumerate
     the USB device.

Signed-off-by: Liu Liu <ot_liu.liu@mediatek.corp-partner.google.com>
Change-Id: Ibe8649297d3236a8896d1045cdf23cb4b1313e43
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87978
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
---
 src/mainboard/google/skywalker/mainboard.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/src/mainboard/google/skywalker/mainboard.c b/src/mainboard/google/skywalker/mainboard.c
index 61aa2794e9..3327c038d1 100644
--- a/src/mainboard/google/skywalker/mainboard.c
+++ b/src/mainboard/google/skywalker/mainboard.c
@@ -91,6 +91,7 @@ static void mainboard_init(struct device *dev)
 
 	dpm_init();
 	setup_usb_host();
+	setup_usb_secondary_host();
 	spm_init();
 	power_on_fpmcu();
 	configure_audio();

From 73cc8a413aa960154c4a4d95af84dc26e2b75019 Mon Sep 17 00:00:00 2001
From: Angel Pons <th3fanbus@gmail.com>
Date: Sun, 25 May 2025 10:23:17 +0200
Subject: [PATCH 1261/3886] treewide: Work around GCC 15
 Werror=unterminated-string-initialization

GCC 15 added a new `unterminated-string-initialization` warning. Even
though crossgcc is still using GCC 14, some Linux distributions (e.g.
Arch Linux) already started shipping GCC 15. Given that coreboot uses
`-Werror` (warnings are errors), this new warning causes build errors
for things built using the host toolchain, such as utilities. In this
case, cbfstool is affected, which prevents building coreboot images.

The nonstring attribute is used to tell the compiler whether or not a
string is intentionally not null terminated. Since the attribute is
only included in GCC 15 for multidimensional character arrays (and even
later for clang) we need to check the GCC version before using the
attribute.

On GCC version prior to GCC 15 the nonstring attribute will not be used,
but that is not a problem since the unterminated-string-initialization
warning only exists since GCC 15. So you can still build on all GCC
versions as before. This way it also works if your host toolchain is GCC
15 (which builds commonlib code for cbfstool) and your coreboot cross
toolchain is GCC 14 (which builds commonlib code for coreboot).
Clang is a diffent matter. According to the documentation, the nonstring
attribute only exists in version 21 which is not yet released by LLVM.

TEST=Build qemu/Q35 successfully

Change-Id: I919d71cb2811e91869ba1ff493a0719ddcc86c36
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87825
Reviewed-by: Benjamin Doron <benjamin.doron00@gmail.com>
Reviewed-by: Nicholas Chin <nic.c3.14@gmail.com>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/commonlib/bsd/include/commonlib/bsd/compiler.h | 7 +++++++
 src/commonlib/include/commonlib/loglevel.h         | 2 +-
 util/cbfstool/common.c                             | 2 +-
 3 files changed, 9 insertions(+), 2 deletions(-)

diff --git a/src/commonlib/bsd/include/commonlib/bsd/compiler.h b/src/commonlib/bsd/include/commonlib/bsd/compiler.h
index 2d77c49ab5..79e0c812da 100644
--- a/src/commonlib/bsd/include/commonlib/bsd/compiler.h
+++ b/src/commonlib/bsd/include/commonlib/bsd/compiler.h
@@ -66,6 +66,13 @@
 #define __printf(a, b) __attribute__((format(printf, a, b)))
 #endif
 
+// This checks the support for the nonstring attribute on multidimensional character arrays.
+#if (defined(__GNUC__) && __GNUC__ >= 15) || (defined(__clang__) && __clang_major__ >= 21)
+#define __nonstring __attribute__((__nonstring__))
+#else
+#define __nonstring
+#endif
+
 /*
  * This evaluates to the type of the first expression, unless that is constant
  * in which case it evaluates to the type of the second. This is useful when
diff --git a/src/commonlib/include/commonlib/loglevel.h b/src/commonlib/include/commonlib/loglevel.h
index 79fbcfc6d9..c4c1b4b011 100644
--- a/src/commonlib/include/commonlib/loglevel.h
+++ b/src/commonlib/include/commonlib/loglevel.h
@@ -165,7 +165,7 @@
  */
 #define BIOS_LOG_PREFIX_PATTERN "[%.5s]  "
 #define BIOS_LOG_PREFIX_MAX_LEVEL BIOS_SPEW
-static const char bios_log_prefix[BIOS_LOG_PREFIX_MAX_LEVEL + 1][5] = {
+static const char __nonstring bios_log_prefix[BIOS_LOG_PREFIX_MAX_LEVEL + 1][5] = {
 	/* Note: These strings are *not* null-terminated to save space. */
 	[BIOS_EMERG]   = "EMERG",
 	[BIOS_ALERT]   = "ALERT",
diff --git a/util/cbfstool/common.c b/util/cbfstool/common.c
index 7154bc9d54..d5eb87ca25 100644
--- a/util/cbfstool/common.c
+++ b/util/cbfstool/common.c
@@ -192,7 +192,7 @@ uint64_t intfiletype(const char *name)
 
 char *bintohex(uint8_t *data, size_t len)
 {
-	static const char translate[16] = "0123456789abcdef";
+	static const char __nonstring translate[16] = "0123456789abcdef";
 
 	char *result = malloc(len * 2 + 1);
 	if (result == NULL)

From b42842bbe5ecd722d468b8d625fbd82417d3d961 Mon Sep 17 00:00:00 2001
From: Bob Moragues <moragues@google.com>
Date: Wed, 4 Jun 2025 16:14:44 +0000
Subject: [PATCH 1262/3886] mb/google/brox: Add brox_rtk_ec variant

This variant of coreboot pairs with the brtk EC target.
This target enables development of the RTK EC on a Brox device.

BUG=b:421434445
TEST=cros build-packages --board brox coreboot
BRANCH=none

Change-Id: Ieaa3de6c30d0a0978506f23d927a4e96de71b16d
Signed-off-by: Bob Moragues <moragues@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87957
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Keith Short <keithshort@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: YH Lin <yueherngl@google.com>
---
 src/mainboard/google/brox/Kconfig      | 12 +++++++++++-
 src/mainboard/google/brox/Kconfig.name |  3 +++
 2 files changed, 14 insertions(+), 1 deletion(-)

diff --git a/src/mainboard/google/brox/Kconfig b/src/mainboard/google/brox/Kconfig
index 3b5d335935..d48b342782 100644
--- a/src/mainboard/google/brox/Kconfig
+++ b/src/mainboard/google/brox/Kconfig
@@ -59,6 +59,11 @@ config BOARD_GOOGLE_BROX
 	select CHROMEOS_WIFI_SAR if CHROMEOS
 	select USE_UNIFIED_AP_FIRMWARE_FOR_UFS_AND_NON_UFS
 
+config BOARD_GOOGLE_BROX_RTK_EC
+	select BOARD_GOOGLE_BASEBOARD_BROX
+	select CHROMEOS_WIFI_SAR if CHROMEOS
+	select USE_UNIFIED_AP_FIRMWARE_FOR_UFS_AND_NON_UFS
+
 config BOARD_GOOGLE_BROX_TI_PDC
 	select BOARD_GOOGLE_BASEBOARD_BROX
 	select CHROMEOS_WIFI_SAR if CHROMEOS
@@ -154,12 +159,17 @@ config MAINBOARD_PART_NUMBER
 	default "Brox" if BOARD_GOOGLE_BROX
 	default "Brox_Ec_Ish" if BOARD_GOOGLE_BROX_EC_ISH
 	default "Brox_Ti_Pdc" if BOARD_GOOGLE_BROX_TI_PDC
+	default "Brox_Rtk_Ec" if BOARD_GOOGLE_BROX_RTK_EC
 	default "Greenbayupoc" if BOARD_GOOGLE_GREENBAYUPOC
 	default "Jubilant" if BOARD_GOOGLE_JUBILANT
 	default "Lotso" if BOARD_GOOGLE_LOTSO
 
 config VARIANT_DIR
-	default "brox" if BOARD_GOOGLE_BROX || BOARD_GOOGLE_BROX_EC_ISH || BOARD_GOOGLE_BROX_TI_PDC
+	default "brox" if \
+		BOARD_GOOGLE_BROX || \
+		BOARD_GOOGLE_BROX_EC_ISH || \
+		BOARD_GOOGLE_BROX_TI_PDC || \
+		BOARD_GOOGLE_BROX_RTK_EC
 	default "lotso" if BOARD_GOOGLE_LOTSO
 	default "greenbayupoc" if BOARD_GOOGLE_GREENBAYUPOC
 	default "jubilant" if BOARD_GOOGLE_JUBILANT
diff --git a/src/mainboard/google/brox/Kconfig.name b/src/mainboard/google/brox/Kconfig.name
index 10f89f431a..7820878bd2 100644
--- a/src/mainboard/google/brox/Kconfig.name
+++ b/src/mainboard/google/brox/Kconfig.name
@@ -5,6 +5,9 @@ comment "Brox"
 config BOARD_GOOGLE_BROX
 	bool "->  Brox"
 
+config BOARD_GOOGLE_BROX_RTK_EC
+	bool "->  Brox RTK EC"
+
 config BOARD_GOOGLE_BROX_EC_ISH
 	bool "->  Brox EC ISH"
 

From b879342fe6d10b11f25689476281bddab48980b8 Mon Sep 17 00:00:00 2001
From: Jeremy Compostella <jeremy.compostella@intel.com>
Date: Wed, 4 Jun 2025 09:56:21 -0700
Subject: [PATCH 1263/3886] soc/intel/pantherlake: Add support for the H204 SKU

The definitions added are based on the following reference documents:

1. Document #815002 Panther Lake H External Design Specification
   Rev. 1.52
2. Document #813278 Panther Lake H Power Map Rev 1.6

Change-Id: I4545e0d48e49ac9a1c7df9b74384bf063455845c
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87953
Reviewed-by: Vidya Gopalakrishnan <vidya.gopalakrishnan@intel.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Jamie Ryu <jamie.m.ryu@intel.com>
---
 src/include/device/pci_ids.h                          | 1 +
 src/soc/intel/common/block/systemagent/systemagent.c  | 1 +
 src/soc/intel/pantherlake/bootblock/report_platform.c | 1 +
 src/soc/intel/pantherlake/chip.h                      | 2 ++
 src/soc/intel/pantherlake/chipset_ptl.cb              | 6 ++++++
 5 files changed, 11 insertions(+)

diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h
index 01854a51a2..85de6a5cfb 100644
--- a/src/include/device/pci_ids.h
+++ b/src/include/device/pci_ids.h
@@ -4556,6 +4556,7 @@
 #define PCI_DID_INTEL_LNL_M_ID			0x6400
 #define PCI_DID_INTEL_LNL_M_ID_1		0x6410
 #define PCI_DID_INTEL_PTL_U_ID_1		0xb000
+#define PCI_DID_INTEL_PTL_U_ID_2		0xb003
 #define PCI_DID_INTEL_PTL_H_ID_1		0xb001
 #define PCI_DID_INTEL_PTL_H_ID_2		0xb002
 #define PCI_DID_INTEL_PTL_H_ID_3		0xb004
diff --git a/src/soc/intel/common/block/systemagent/systemagent.c b/src/soc/intel/common/block/systemagent/systemagent.c
index b3f8c0c695..8b623fc9e7 100644
--- a/src/soc/intel/common/block/systemagent/systemagent.c
+++ b/src/soc/intel/common/block/systemagent/systemagent.c
@@ -428,6 +428,7 @@ static const unsigned short systemagent_ids[] = {
 	PCI_DID_INTEL_WCL_ID_1,
 	PCI_DID_INTEL_WCL_ID_2,
 	PCI_DID_INTEL_PTL_U_ID_1,
+	PCI_DID_INTEL_PTL_U_ID_2,
 	PCI_DID_INTEL_PTL_H_ID_1,
 	PCI_DID_INTEL_PTL_H_ID_2,
 	PCI_DID_INTEL_PTL_H_ID_3,
diff --git a/src/soc/intel/pantherlake/bootblock/report_platform.c b/src/soc/intel/pantherlake/bootblock/report_platform.c
index 07e1261916..0cca50669b 100644
--- a/src/soc/intel/pantherlake/bootblock/report_platform.c
+++ b/src/soc/intel/pantherlake/bootblock/report_platform.c
@@ -28,6 +28,7 @@ static struct {
 	const char *name;
 } mch_table[] = {
 	{ PCI_DID_INTEL_PTL_U_ID_1, "Pantherlake U" },
+	{ PCI_DID_INTEL_PTL_U_ID_2, "Pantherlake U" },
 	{ PCI_DID_INTEL_PTL_H_ID_1, "Pantherlake H" },
 	{ PCI_DID_INTEL_PTL_H_ID_2, "Pantherlake H" },
 	{ PCI_DID_INTEL_PTL_H_ID_3, "Pantherlake H" },
diff --git a/src/soc/intel/pantherlake/chip.h b/src/soc/intel/pantherlake/chip.h
index eb702b7eca..47a20fe7d8 100644
--- a/src/soc/intel/pantherlake/chip.h
+++ b/src/soc/intel/pantherlake/chip.h
@@ -54,6 +54,7 @@ enum soc_intel_pantherlake_sagv_gears {
 
 enum soc_intel_pantherlake_power_limits {
 	PTL_U_1_CORE,
+	PTL_U_2_CORE,
 	PTL_H_1_CORE,
 	PTL_H_2_CORE,
 	PTL_H_3_CORE,
@@ -74,6 +75,7 @@ static const struct {
 	enum soc_intel_pantherlake_cpu_tdps cpu_tdp;
 } cpuid_to_ptl[] = {
 	{ PCI_DID_INTEL_PTL_U_ID_1, PTL_U_1_CORE, TDP_15W },
+	{ PCI_DID_INTEL_PTL_U_ID_2, PTL_U_2_CORE, TDP_15W },
 	{ PCI_DID_INTEL_PTL_H_ID_1, PTL_H_1_CORE, TDP_25W },
 	{ PCI_DID_INTEL_PTL_H_ID_2, PTL_H_1_CORE, TDP_25W },
 	{ PCI_DID_INTEL_PTL_H_ID_3, PTL_H_2_CORE, TDP_25W },
diff --git a/src/soc/intel/pantherlake/chipset_ptl.cb b/src/soc/intel/pantherlake/chipset_ptl.cb
index 0c57a7def6..79666cbb3b 100644
--- a/src/soc/intel/pantherlake/chipset_ptl.cb
+++ b/src/soc/intel/pantherlake/chipset_ptl.cb
@@ -8,6 +8,12 @@ chip soc/intel/pantherlake
 		.tdp_pl4 = 152,
 	}"
 
+	register "power_limits_config[PTL_U_2_CORE]" = "{
+		.tdp_pl1_override = 15,
+		.tdp_pl2_override = 45,
+		.tdp_pl4 = 105,
+	}"
+
 	register "power_limits_config[PTL_H_1_CORE]" = "{
 		.tdp_pl1_override = 25,
 		.tdp_pl2_override = 95,

From d9c5cef7f0132ae4129b12efc936f9820247f8fd Mon Sep 17 00:00:00 2001
From: Jeremy Compostella <jeremy.compostella@intel.com>
Date: Wed, 4 Jun 2025 10:07:06 -0700
Subject: [PATCH 1264/3886] soc/intel/pantherlake: Add Fast VMode PL4 Power
 Limit configuration

This commit introduces a new power limit configuration for Fast VMode in
Panther Lake SoC. The changes include the addition of a
`tdp_pl4_fastvmode` field to the `soc_power_limits_config` structure,
allowing distinct PL4 power limit values when Fast VMode is enabled.

The values come from document #813278 Panther Lake H Power Map Rev 1.6.

Change-Id: I971d1aa7dd22a8135272577712283b4565810799
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87954
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Jamie Ryu <jamie.m.ryu@intel.com>
Reviewed-by: Vidya Gopalakrishnan <vidya.gopalakrishnan@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 .../common/block/include/intelblocks/power_limit.h  |  2 ++
 src/soc/intel/pantherlake/chipset_ptl.cb            | 13 ++++++++++---
 src/soc/intel/pantherlake/systemagent.c             |  3 +++
 3 files changed, 15 insertions(+), 3 deletions(-)

diff --git a/src/soc/intel/common/block/include/intelblocks/power_limit.h b/src/soc/intel/common/block/include/intelblocks/power_limit.h
index d02eaa1352..8e517caed0 100644
--- a/src/soc/intel/common/block/include/intelblocks/power_limit.h
+++ b/src/soc/intel/common/block/include/intelblocks/power_limit.h
@@ -32,6 +32,8 @@ struct soc_power_limits_config {
 	uint32_t tdp_psyspl3_dutycycle;
 	/* PL4 Value in Watts */
 	uint16_t tdp_pl4;
+	/* PL4 Value in Watts when Fast VMode is enabled */
+	uint16_t tdp_pl4_fastvmode;
 	/* Estimated maximum platform power in Watts */
 	uint16_t psys_pmax;
 };
diff --git a/src/soc/intel/pantherlake/chipset_ptl.cb b/src/soc/intel/pantherlake/chipset_ptl.cb
index 79666cbb3b..838fdfa30a 100644
--- a/src/soc/intel/pantherlake/chipset_ptl.cb
+++ b/src/soc/intel/pantherlake/chipset_ptl.cb
@@ -2,24 +2,31 @@ chip soc/intel/pantherlake
 
 	device cpu_cluster 0 on end
 
+	# H404
 	register "power_limits_config[PTL_U_1_CORE]" = "{
 		.tdp_pl1_override = 15,
 		.tdp_pl2_override = 55,
-		.tdp_pl4 = 152,
+		.tdp_pl4 = 163,
+		.tdp_pl4_fastvmode = 150,
 	}"
 
+	# H204
 	register "power_limits_config[PTL_U_2_CORE]" = "{
 		.tdp_pl1_override = 15,
 		.tdp_pl2_override = 45,
 		.tdp_pl4 = 105,
+		.tdp_pl4_fastvmode = 95,
 	}"
 
+	# H12Xe and H484
 	register "power_limits_config[PTL_H_1_CORE]" = "{
 		.tdp_pl1_override = 25,
-		.tdp_pl2_override = 95,
-		.tdp_pl4 = 239,
+		.tdp_pl2_override = 64,
+		.tdp_pl4 = 175,
+		.tdp_pl4_fastvmode = 160,
 	}"
 
+	# H444
 	register "power_limits_config[PTL_H_2_CORE]" = "{
 		.tdp_pl1_override = 25,
 		.tdp_pl2_override = 64,
diff --git a/src/soc/intel/pantherlake/systemagent.c b/src/soc/intel/pantherlake/systemagent.c
index a5a734f02d..82e5d244c7 100644
--- a/src/soc/intel/pantherlake/systemagent.c
+++ b/src/soc/intel/pantherlake/systemagent.c
@@ -171,6 +171,9 @@ static void configure_tdp(struct device *dev)
 		if (sa_pci_id == cpuid_to_ptl[i].cpu_id &&
 				tdp == cpuid_to_ptl[i].cpu_tdp) {
 			soc_config = &config->power_limits_config[cpuid_to_ptl[i].limits];
+			if (config->enable_fast_vmode[VR_DOMAIN_IA] &&
+			    soc_config->tdp_pl4_fastvmode)
+				soc_config->tdp_pl4 = soc_config->tdp_pl4_fastvmode;
 			set_power_limits(MOBILE_SKU_PL1_TIME_SEC, soc_config);
 			config_tdp = true;
 			printk(BIOS_DEBUG, "Configured power limits for SA PCI ID: 0x%4x\n",

From 1537c89e8d7c321b3e8e6cf5d00c28e981a798a9 Mon Sep 17 00:00:00 2001
From: Jeremy Compostella <jeremy.compostella@intel.com>
Date: Wed, 4 Jun 2025 22:21:25 -0700
Subject: [PATCH 1265/3886] soc/intel/cmn/block/power_limit: Enforce variant
 PL4 for Fast VMode

Adds a new assignment in variant_update_cpu_power_limits() to enforce
the desired PL4 power limit regardless of whether Fast VMode is enabled
or not.

Change-Id: I8b376d283b2a28333c8efc932bc2f776dfb5584a
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87958
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/soc/intel/common/block/power_limit/power_limit.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/src/soc/intel/common/block/power_limit/power_limit.c b/src/soc/intel/common/block/power_limit/power_limit.c
index 5f71d2eb95..16917835cd 100644
--- a/src/soc/intel/common/block/power_limit/power_limit.c
+++ b/src/soc/intel/common/block/power_limit/power_limit.c
@@ -283,6 +283,7 @@ void variant_update_cpu_power_limits(const struct cpu_tdp_power_limits *limits,
 			settings->pl2.min_power = limits[index].pl2_min_power;
 			settings->pl2.max_power = limits[index].pl2_max_power;
 			soc_config->tdp_pl4 = DIV_ROUND_UP(limits[index].pl4_power, MILLIWATTS_TO_WATTS);
+			soc_config->tdp_pl4_fastvmode = soc_config->tdp_pl4;
 			printk(BIOS_INFO, "Overriding power limits PL1 (mW) (%u, %u) PL2 (mW) (%u, %u) PL4 (W) (%u)\n",
 				settings->pl1.min_power,
 				settings->pl1.max_power,

From f2e488cfbf50a69c70b7a97e4fd578caec41e970 Mon Sep 17 00:00:00 2001
From: Jeremy Compostella <jeremy.compostella@intel.com>
Date: Wed, 4 Jun 2025 22:27:38 -0700
Subject: [PATCH 1266/3886] mb/google/fatcat: Add power limit overrides for
 H204 and H404 SKUs

In the factory setting, when a type-C charger is connected and the
battery is disconnected, it guarantees that the power limits are reduced
to avoid any unexpected shutdown or reset.

Change-Id: Ibe37c303149bbc253c5734664e8f17ee7005aca1
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87959
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jamie Ryu <jamie.m.ryu@intel.com>
---
 .../variants/baseboard/fatcat/ramstage.c      | 20 +++++++++++++++++++
 1 file changed, 20 insertions(+)

diff --git a/src/mainboard/google/fatcat/variants/baseboard/fatcat/ramstage.c b/src/mainboard/google/fatcat/variants/baseboard/fatcat/ramstage.c
index 69d0d67cd0..84111619ad 100644
--- a/src/mainboard/google/fatcat/variants/baseboard/fatcat/ramstage.c
+++ b/src/mainboard/google/fatcat/variants/baseboard/fatcat/ramstage.c
@@ -48,6 +48,26 @@ const struct cpu_tdp_power_limits power_optimized_limits[] = {
 		.pl2_max_power = 50000,
 		.pl4_power = 65000
 	},
+	{
+		.mch_id = PCI_DID_INTEL_PTL_U_ID_1,
+		.cpu_tdp = TDP_15W,
+		.power_limits_index = PTL_U_1_CORE,
+		.pl1_min_power = 10000,
+		.pl1_max_power = 15000,
+		.pl2_min_power = 50000,
+		.pl2_max_power = 50000,
+		.pl4_power = 65000
+	},
+	{
+		.mch_id = PCI_DID_INTEL_PTL_U_ID_2,
+		.cpu_tdp = TDP_15W,
+		.power_limits_index = PTL_U_2_CORE,
+		.pl1_min_power = 10000,
+		.pl1_max_power = 15000,
+		.pl2_min_power = 50000,
+		.pl2_max_power = 50000,
+		.pl4_power = 65000
+	},
 };
 
 /*

From 30865c2fb1bacdb17c4109f5f82df2278187427b Mon Sep 17 00:00:00 2001
From: Patrick Rudolph <patrick.rudolph@9elements.com>
Date: Thu, 5 Jun 2025 10:04:25 +0200
Subject: [PATCH 1267/3886] mb/amd/birman_plus: Skip i2c_early init

Early init is only required for I2C2 since the DDI1 connector type
must be probed in romstage. The other I2C busses aren't used at the
moment and there's no need for early init.

TEST=Display init on amd/birman_plus still works. I2C0, I2C1 and I2C3
     are initialized in ramstage after FSPS.

Change-Id: I0491d03464b675d18e42324580c91642aae4e727
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87963
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
---
 src/mainboard/amd/birman_plus/devicetree_glinda.cb  |  4 ----
 src/mainboard/amd/birman_plus/devicetree_phoenix.cb |  4 ----
 src/mainboard/amd/birman_plus/early_gpio.c          | 12 ------------
 3 files changed, 20 deletions(-)

diff --git a/src/mainboard/amd/birman_plus/devicetree_glinda.cb b/src/mainboard/amd/birman_plus/devicetree_glinda.cb
index 5a7dd163f4..9ec3c8fd71 100644
--- a/src/mainboard/amd/birman_plus/devicetree_glinda.cb
+++ b/src/mainboard/amd/birman_plus/devicetree_glinda.cb
@@ -23,11 +23,7 @@ chip soc/amd/glinda
 
 	register "i2c_scl_reset" = "GPIO_I2C0_SCL | GPIO_I2C1_SCL |
 					GPIO_I2C2_SCL | GPIO_I2C3_SCL"
-
-	register "i2c[0].early_init" = "1"
-	register "i2c[1].early_init" = "1"
 	register "i2c[2].early_init" = "1"
-	register "i2c[3].early_init" = "1"
 
 	# I2C Pad Control RX Select Configuration
 	register "i2c_pad[0].rx_level" = "I2C_PAD_RX_1_8V"
diff --git a/src/mainboard/amd/birman_plus/devicetree_phoenix.cb b/src/mainboard/amd/birman_plus/devicetree_phoenix.cb
index 2490c9b93b..a6d5503118 100644
--- a/src/mainboard/amd/birman_plus/devicetree_phoenix.cb
+++ b/src/mainboard/amd/birman_plus/devicetree_phoenix.cb
@@ -25,11 +25,7 @@ chip soc/amd/phoenix
 
 	register "i2c_scl_reset" = "GPIO_I2C0_SCL | GPIO_I2C1_SCL |
 					GPIO_I2C2_SCL | GPIO_I2C3_SCL"
-
-	register "i2c[0].early_init" = "1"
-	register "i2c[1].early_init" = "1"
 	register "i2c[2].early_init" = "1"
-	register "i2c[3].early_init" = "1"
 
 	# I2C Pad Control RX Select Configuration
 	register "i2c_pad[0].rx_level" = "I2C_PAD_RX_1_8V"
diff --git a/src/mainboard/amd/birman_plus/early_gpio.c b/src/mainboard/amd/birman_plus/early_gpio.c
index 4915996881..b7dcff175a 100644
--- a/src/mainboard/amd/birman_plus/early_gpio.c
+++ b/src/mainboard/amd/birman_plus/early_gpio.c
@@ -54,22 +54,10 @@ static const struct soc_amd_gpio gpio_set_stage_reset[] = {
 	/* FANOUT0 */
 	PAD_NF(GPIO_85, FANOUT0, PULL_NONE),
 
-	/* I2C0 SCL */
-	PAD_NF(GPIO_145, I2C0_SCL, PULL_NONE),
-	/* I2C0 SDA */
-	PAD_NF(GPIO_146, I2C0_SDA, PULL_NONE),
-	/* I2C1 SCL */
-	PAD_NF(GPIO_147, I2C1_SCL, PULL_NONE),
-	/* I2C1 SDA */
-	PAD_NF(GPIO_148, I2C1_SDA, PULL_NONE),
 	/* I2C2_SCL */
 	PAD_NF(GPIO_113, I2C2_SCL, PULL_NONE),
 	/* I2C2_SDA */
 	PAD_NF(GPIO_114, I2C2_SDA, PULL_NONE),
-	/* I2C3_SCL */
-	PAD_NF(GPIO_19, I2C3_SCL, PULL_NONE),
-	/* I2C3_SDA */
-	PAD_NF(GPIO_20, I2C3_SDA, PULL_NONE),
 };
 
 void mainboard_program_early_gpios(void)

From 712dfb376136a9d69451624c59c0dd6b880a3597 Mon Sep 17 00:00:00 2001
From: Jon Murphy <jpmurphy@google.com>
Date: Mon, 9 Jun 2025 17:39:48 +0000
Subject: [PATCH 1268/3886] Revert "util/cbmem: Consolidate CBMEM and coreboot
 table access"

This reverts commit c24a12db860f33cee2a8ff4c7fd66af3775fba5d.

Reason for revert: can't assume uint64_t or uintptr_t is a long. use proper printf modifiers instead.

```
cbmem.c:417:28: error: format specifies type 'unsigned long' but the argument
      has type 'uint64_t' (aka 'unsigned long long') [-Werror,-Wformat]
  417 |                 debug("Found at %#lx\n", address + i);
      |                                 ~~~~     ^~~~~~~~~~~
      |                                 %#llx
cbmem.c:50:40: note: expanded from macro 'debug'
   50 | #define debug(x...) if(verbose) printf(x)
      |                                        ^
cbmem.c:1321:21: error: format specifies type 'unsigned long' but the argument
      has type 'uintptr_t' (aka 'unsigned int') [-Werror,-Wformat]
 1321 |                         printf("%08lx:", start_address + i);
      |                                 ~~~~~    ^~~~~~~~~~~~~~~~~
      |                                 %08x
2 errors generated.
make: *** [<builtin>: cbmem.o] Error 1
```

Signed-off-by: Jon Murphy <jpmurphy@google.com>
Change-Id: I6e074b0c6c8247f85cd69d64c0e8584c5826e35a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88016
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Jakub "Kuba" Czapiga <czapiga@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 util/cbmem/cbmem.c | 679 ++++++++++++++++++++++-----------------------
 1 file changed, 328 insertions(+), 351 deletions(-)

diff --git a/util/cbmem/cbmem.c b/util/cbmem/cbmem.c
index 9fc4060302..bdb6794dbf 100644
--- a/util/cbmem/cbmem.c
+++ b/util/cbmem/cbmem.c
@@ -35,6 +35,9 @@
 #include <x86intrin.h>
 #endif
 
+/* Return < 0 on error, 0 on success. */
+static int parse_cbtable(uint64_t address, size_t table_size);
+
 struct mapping {
 	void *virt;
 	size_t offset;
@@ -53,6 +56,9 @@ static int verbose = 0;
 static int mem_fd;
 static struct mapping lbtable_mapping;
 
+/* TSC frequency from the LB_TAG_TSC_INFO record. 0 if not present. */
+static uint32_t tsc_freq_khz = 0;
+
 static void die(const char *msg)
 {
 	if (msg)
@@ -189,6 +195,57 @@ static void *aligned_memcpy(void *dest, const void *src, size_t n)
 	return dest;
 }
 
+/* Find the first cbmem entry filling in the details. */
+static int find_cbmem_entry(uint32_t id, uint64_t *addr, size_t *size)
+{
+	const uint8_t *table;
+	size_t offset;
+	int ret = -1;
+
+	table = mapping_virt(&lbtable_mapping);
+
+	if (table == NULL)
+		return -1;
+
+	offset = 0;
+
+	while (offset < mapping_size(&lbtable_mapping)) {
+		const struct lb_record *lbr;
+		struct lb_cbmem_entry lbe;
+
+		lbr = (const void *)(table + offset);
+		offset += lbr->size;
+
+		if (lbr->tag != LB_TAG_CBMEM_ENTRY)
+			continue;
+
+		aligned_memcpy(&lbe, lbr, sizeof(lbe));
+		if (lbe.id != id)
+			continue;
+
+		*addr = lbe.address;
+		*size = lbe.entry_size;
+		ret = 0;
+		break;
+	}
+
+	return ret;
+}
+
+/*
+ * Try finding the timestamp table and coreboot cbmem console starting from the
+ * passed in memory offset.  Could be called recursively in case a forwarding
+ * entry is found.
+ *
+ * Returns pointer to a memory buffer containing the timestamp table or zero if
+ * none found.
+ */
+
+static struct lb_cbmem_ref timestamps;
+static struct lb_cbmem_ref console;
+static struct lb_cbmem_ref tpm_cb_log;
+static struct lb_memory_range cbmem;
+
 /* This is a work-around for a nasty problem introduced by initially having
  * pointer sized entries in the lb_cbmem_ref structures. This caused problems
  * on 64bit x86 systems because coreboot is 32bit on those systems.
@@ -210,168 +267,90 @@ static struct lb_cbmem_ref parse_cbmem_ref(const struct lb_cbmem_ref *cbmem_ref)
 	return ret;
 }
 
-static uint32_t cbmem_id_to_lb_tag(uint32_t tag)
+static void parse_memory_tags(const struct lb_memory *mem)
 {
-	/* Minimal subset. Expand based on the CBMEM to coreboot table
-	   records mapping in lib/coreboot_table.c */
-	switch (tag) {
-	case CBMEM_ID_TIMESTAMP:
-		return LB_TAG_TIMESTAMPS;
-	case CBMEM_ID_CONSOLE:
-		return LB_TAG_CBMEM_CONSOLE;
-	case CBMEM_ID_TPM_CB_LOG:
-		return LB_TAG_TPM_CB_LOG;
+	int num_entries;
+	int i;
+
+	/* Peel off the header size and calculate the number of entries. */
+	num_entries = (mem->size - sizeof(*mem)) / sizeof(mem->map[0]);
+
+	for (i = 0; i < num_entries; i++) {
+		if (mem->map[i].type != LB_MEM_TABLE)
+			continue;
+		debug("      LB_MEM_TABLE found.\n");
+		/* The last one found is CBMEM */
+		aligned_memcpy(&cbmem, &mem->map[i], sizeof(cbmem));
 	}
-	return LB_TAG_UNUSED;
 }
 
-struct cbmem_console {
-	uint32_t size;
-	uint32_t cursor;
-	uint8_t body[];
-} __packed;
-
-#define CBMC_CURSOR_MASK ((1 << 28) - 1)
-#define CBMC_OVERFLOW    (1 << 31)
-
-
-/* Find the first cbmem entry filling in the details. */
-static int find_cbmem_entry(uint32_t id, uint64_t *addr, size_t *size)
+/* Return < 0 on error, 0 on success, 1 if forwarding table entry found. */
+static int parse_cbtable_entries(const struct mapping *table_mapping)
 {
-	const uint8_t *table;
-	size_t offset = 0;
-	const uint32_t legacy_tag = cbmem_id_to_lb_tag(id);
-	struct lb_cbmem_ref *ref = NULL;
+	size_t i;
+	const struct lb_record *lbr_p;
+	size_t table_size = mapping_size(table_mapping);
+	const void *lbtable = mapping_virt(table_mapping);
+	int forwarding_table_found = 0;
 
-	table = mapping_virt(&lbtable_mapping);
-
-	if (table == NULL)
-		return -1;
-
-	const struct lb_record *lbr = NULL;
-	while (offset < mapping_size(&lbtable_mapping)) {
-		lbr = (const void *)(table + offset);
-		offset += lbr->size;
-
-		/* Store coreboot table entry for later if CBMEM entry does not exist.
-		   CBMEM entry stores size including the reserved area, so prefer it,
-		   so more potential data and/or space is available. */
-		if (legacy_tag != LB_TAG_UNUSED && lbr->tag == legacy_tag)
-			ref = (struct lb_cbmem_ref *)lbr;
-
-		if (lbr->tag != LB_TAG_CBMEM_ENTRY)
+	for (i = 0; i < table_size; i += lbr_p->size) {
+		lbr_p = lbtable + i;
+		debug("  coreboot table entry 0x%02x\n", lbr_p->tag);
+		switch (lbr_p->tag) {
+		case LB_TAG_MEMORY:
+			debug("    Found memory map.\n");
+			parse_memory_tags(lbtable + i);
 			continue;
-
-		struct lb_cbmem_entry lbe;
-		aligned_memcpy(&lbe, lbr, sizeof(lbe));
-		if (lbe.id != id)
+		case LB_TAG_TIMESTAMPS: {
+			debug("    Found timestamp table.\n");
+			timestamps =
+			    parse_cbmem_ref((struct lb_cbmem_ref *)lbr_p);
 			continue;
+		}
+		case LB_TAG_CBMEM_CONSOLE: {
+			debug("    Found cbmem console.\n");
+			console = parse_cbmem_ref((struct lb_cbmem_ref *)lbr_p);
+			continue;
+		}
+		case LB_TAG_TPM_CB_LOG: {
+			debug("    Found TPM CB log table.\n");
+			tpm_cb_log =
+			    parse_cbmem_ref((struct lb_cbmem_ref *)lbr_p);
+			continue;
+		}
+		case LB_TAG_TSC_INFO:
+			debug("    Found TSC info.\n");
+			tsc_freq_khz = ((struct lb_tsc_info *)lbr_p)->freq_khz;
+			continue;
+		case LB_TAG_FORWARD: {
+			int ret;
+			/*
+			 * This is a forwarding entry - repeat the
+			 * search at the new address.
+			 */
+			struct lb_forward lbf_p =
+			    *(const struct lb_forward *)lbr_p;
+			debug("    Found forwarding entry.\n");
+			ret = parse_cbtable(lbf_p.forward, 0);
 
-		*addr = lbe.address;
-		*size = lbe.entry_size;
-		return 0;
+			/* Assume the forwarding entry is valid. If this fails
+			 * then there's a total failure. */
+			if (ret < 0)
+				return -1;
+			forwarding_table_found = 1;
+		}
+		default:
+			break;
+		}
 	}
 
-	/* No mapping and/or no potential reference means that
-	   the requested entry does not exit. */
-	if (legacy_tag == LB_TAG_UNUSED || ref == NULL)
-		return -1;
-
-	debug("Found coreboot table record equivalent of CBMEM entry id: %#x, tag: %#x\n", id,
-	      legacy_tag);
-
-	const struct lb_cbmem_ref lbc = parse_cbmem_ref(ref);
-	size_t header_map_size = 0;
-
-	/* Process legacy coreboot table entries */
-	switch (lbc.tag) {
-	case LB_TAG_TIMESTAMPS:
-		header_map_size = sizeof(struct timestamp_table);
-		break;
-	case LB_TAG_CBMEM_CONSOLE:
-		header_map_size = sizeof(struct cbmem_console);
-		break;
-	case LB_TAG_TPM_CB_LOG:
-		header_map_size = sizeof(struct tpm_cb_log_table);
-		break;
-	}
-
-	struct mapping entry_mapping;
-	const void *entry_header = NULL;
-
-	entry_header = map_memory(&entry_mapping, lbc.cbmem_addr, header_map_size);
-	if (!entry_header) {
-		fprintf(stderr, "Unable to map header for coreboot table entry id: %#x\n",
-			legacy_tag);
-		abort();
-	}
-
-	*addr = lbc.cbmem_addr;
-
-	switch (legacy_tag) {
-	case LB_TAG_TIMESTAMPS: {
-		const struct timestamp_table *tst_p = entry_header;
-		*size = sizeof(*tst_p) + tst_p->num_entries * sizeof(tst_p->entries[0]);
-		break;
-	}
-	case LB_TAG_CBMEM_CONSOLE: {
-		const struct cbmem_console *console_p = entry_header;
-		*size = sizeof(*console_p) + console_p->size;
-		break;
-	}
-	case LB_TAG_TPM_CB_LOG: {
-		const struct tpm_cb_log_table *tclt_p = entry_header;
-		*size = sizeof(*tclt_p) + tclt_p->num_entries * sizeof(tclt_p->entries[0]);
-		break;
-	}
-	}
-
-	unmap_memory(&entry_mapping);
-
-	return 0;
-}
-
-/**
- * Returns pointer to allocated buffer and size of the buffer in parameters.
- * Returns zero on success.
- * free() buffer after use.
- */
-static int get_cbmem_entry(uint32_t id, uint8_t **buf_out, size_t *size_out)
-{
-	uint64_t addr;
-	size_t size;
-	struct mapping cbmem_mapping;
-
-	if (find_cbmem_entry(id, &addr, &size)) {
-		debug("CBMEM entry not found. CBMEM id: %#x\n", id);
-		return -1;
-	}
-
-	const uint8_t *buf = map_memory(&cbmem_mapping, addr, size);
-	if (!buf) {
-		fprintf(stderr, "Unable to map CBMEM entry id: %#x, size: %zu\n", id, size);
-		abort();
-	}
-
-	*buf_out = malloc(size);
-	if (!*buf_out) {
-		unmap_memory(&cbmem_mapping);
-		fprintf(stderr,
-			"Unable to allocate memory for CBMEM entry id: %#x, size: %zu\n", id,
-			size);
-		abort();
-	}
-
-	aligned_memcpy(*buf_out, buf, size);
-	unmap_memory(&cbmem_mapping);
-	*size_out = size;
-	return 0;
+	return forwarding_table_found;
 }
 
 /* Return < 0 on error, 0 on success. */
 static int parse_cbtable(uint64_t address, size_t table_size)
 {
-	const uint8_t *buf;
+	const void *buf;
 	struct mapping header_mapping;
 	size_t req_size;
 	size_t i;
@@ -381,7 +360,8 @@ static int parse_cbtable(uint64_t address, size_t table_size)
 	if (req_size == 0)
 		req_size = 4 * 1024;
 
-	debug("Looking for coreboot table at %" PRIx64 " %zd bytes.\n", address, req_size);
+	debug("Looking for coreboot table at %" PRIx64 " %zd bytes.\n",
+		address, req_size);
 
 	buf = map_memory(&header_mapping, address, req_size);
 
@@ -390,10 +370,11 @@ static int parse_cbtable(uint64_t address, size_t table_size)
 
 	/* look at every 16 bytes */
 	for (i = 0; i <= req_size - sizeof(struct lb_header); i += 16) {
+		int ret;
 		const struct lb_header *lbh;
 		struct mapping table_mapping;
 
-		lbh = (const struct lb_header *)&buf[i];
+		lbh = buf + i;
 		if (memcmp(lbh->signature, "LBIO", sizeof(lbh->signature)) ||
 		    !lbh->header_bytes ||
 		    ipchksum(lbh, sizeof(*lbh))) {
@@ -414,32 +395,27 @@ static int parse_cbtable(uint64_t address, size_t table_size)
 			continue;
 		}
 
-		debug("Found at %#lx\n", address + i);
+		debug("Found!\n");
 
-		const struct lb_record *lbr_p;
-		const uint8_t *lbtable = mapping_virt(&table_mapping);
+		ret = parse_cbtable_entries(&table_mapping);
 
-		for (size_t offset = 0; offset < lbh->table_bytes; offset += lbr_p->size) {
-			lbr_p = (const struct lb_record *)&lbtable[offset];
-			debug("  coreboot table entry 0x%02x\n", lbr_p->tag);
-
-			if (lbr_p->tag != LB_TAG_FORWARD)
-				continue;
-
-			/* This is a forwarding entry. Repeat the search at the new address. */
-			struct lb_forward lbf_p = *(const struct lb_forward *)lbr_p;
-			debug("    Found forwarding entry.\n");
-
-			const uint64_t next_addr = lbf_p.forward;
-			unmap_memory(&header_mapping);
+		/* Table parsing failed. */
+		if (ret < 0) {
 			unmap_memory(&table_mapping);
-
-			return parse_cbtable(next_addr, 0);
+			continue;
 		}
 
-		debug("correct coreboot table found.\n");
+		/* Succeeded in parsing the table. Header not needed anymore. */
 		unmap_memory(&header_mapping);
-		lbtable_mapping = table_mapping;
+
+		/*
+		 * Table parsing succeeded. If forwarding table not found update
+		 * coreboot table mapping for future use.
+		 */
+		if (ret == 0)
+			lbtable_mapping = table_mapping;
+		else
+			unmap_memory(&table_mapping);
 
 		return 0;
 	}
@@ -449,78 +425,6 @@ static int parse_cbtable(uint64_t address, size_t table_size)
 	return -1;
 }
 
-static void lb_table_get_entry(uint32_t tag, uint8_t **buf_out, size_t *size_out)
-{
-	const struct lb_record *lbr_p;
-	const uint8_t *lbtable_raw;
-	size_t table_size;
-	bool tag_found = false;
-
-	if (get_cbmem_entry(CBMEM_ID_CBTABLE, (uint8_t **)&lbtable_raw, &table_size)) {
-		fprintf(stderr, "coreboot table not found.\n");
-		abort();
-	}
-
-	const struct lb_header *lbh = (const struct lb_header *)lbtable_raw;
-
-	for (size_t i = 0; i < lbh->table_bytes; i += lbr_p->size) {
-		lbr_p = (const struct lb_record *)(&lbtable_raw[lbh->header_bytes + i]);
-		if (lbr_p->tag == tag) {
-			tag_found = true;
-			break;
-		}
-	}
-
-	if (!tag_found) {
-		fprintf(stderr, "coreboot table entry %#x not found.\n", tag);
-		free((void *)lbtable_raw);
-		abort();
-	}
-
-	debug("coreboot table entry %#x found.\n", tag);
-
-	*buf_out = malloc(lbr_p->size);
-	if (!*buf_out) {
-		fprintf(stderr,
-			"Unable to allocate memory for coreboot table entry %#x, size: %d\n",
-			tag, lbr_p->size);
-		free((void *)lbtable_raw);
-		abort();
-	}
-	memcpy(*buf_out, lbr_p, lbr_p->size);
-	*size_out = lbr_p->size;
-	free((void *)lbtable_raw);
-}
-
-
-/**
- * Returns mapping, mapped buffer pointer and its size by parameters.
- * Returns zero on success.
- * unmap_mempry() after use.
- */
-static int map_cbmem_entry_rw(uint32_t id, struct mapping *mapping, uint8_t **buf_out,
-			       size_t *size_out)
-{
-	uint64_t addr;
-	size_t size;
-
-	if (find_cbmem_entry(id, &addr, &size)) {
-		debug("CBMEM entry not found. CBMEM id: %#x\n", id);
-		return -1;
-	}
-
-	*buf_out = map_memory_with_prot(mapping, addr, size, PROT_READ | PROT_WRITE);
-	if (!*buf_out) {
-		fprintf(stderr,
-			"Unable to map CBMEM entry id: %#x, size: %zu for read-write access.\n",
-			id, size);
-		abort();
-	}
-
-	*size_out = size;
-	return 0;
-}
-
 #if defined(linux) && (defined(__i386__) || defined(__x86_64__))
 /*
  * read CPU frequency from a sysfs file, return an frequency in Megahertz as
@@ -624,19 +528,11 @@ static uint64_t timestamp_get(uint64_t table_tick_freq_mhz)
 {
 #if defined(__i386__) || defined(__x86_64__)
 	uint64_t tsc = __rdtsc();
-	struct lb_tsc_info *tsc_info;
-	size_t size;
 
 	/* No tick frequency specified means raw TSC values. */
 	if (!table_tick_freq_mhz)
 		return tsc;
 
-	lb_table_get_entry(LB_TAG_TSC_INFO, (uint8_t **)&tsc_info, &size);
-
-	const uint32_t tsc_freq_khz = tsc_info->freq_khz;
-
-	free(tsc_info);
-
 	if (tsc_freq_khz)
 		return tsc * table_tick_freq_mhz * 1000 / tsc_freq_khz;
 #else
@@ -783,23 +679,34 @@ static void dump_timestamps(enum timestamps_print_type output_type)
 	size_t size;
 	uint64_t prev_stamp = 0;
 	uint64_t total_time = 0;
+	struct mapping timestamp_mapping;
 
-	if (get_cbmem_entry(CBMEM_ID_TIMESTAMP, (uint8_t **)&tst_p, &size)) {
-		fprintf(stderr, "Timestamps not found.\n");
-		abort();
+	if (timestamps.tag != LB_TAG_TIMESTAMPS) {
+		fprintf(stderr, "No timestamps found in coreboot table.\n");
+		return;
 	}
 
+	size = sizeof(*tst_p);
+	tst_p = map_memory(&timestamp_mapping, timestamps.cbmem_addr, size);
+	if (!tst_p)
+		die("Unable to map timestamp header\n");
+
 	timestamp_set_tick_freq(tst_p->tick_freq_mhz);
 
 	if (output_type == TIMESTAMPS_PRINT_NORMAL)
 		printf("%d entries total:\n\n", tst_p->num_entries);
+	size += tst_p->num_entries * sizeof(tst_p->entries[0]);
+
+	unmap_memory(&timestamp_mapping);
+
+	tst_p = map_memory(&timestamp_mapping, timestamps.cbmem_addr, size);
+	if (!tst_p)
+		die("Unable to map full timestamp table\n");
 
 	sorted_tst_p = malloc(size + sizeof(struct timestamp_entry));
-	if (!sorted_tst_p) {
-		free((void *)tst_p);
+	if (!sorted_tst_p)
 		die("Failed to allocate memory");
-	}
-	memcpy(sorted_tst_p, tst_p, size);
+	aligned_memcpy(sorted_tst_p, tst_p, size);
 
 	/*
 	 * Insert a timestamp to represent the base time (start of coreboot),
@@ -876,8 +783,8 @@ static void dump_timestamps(enum timestamps_print_type output_type)
 		printf("\n");
 	}
 
+	unmap_memory(&timestamp_mapping);
 	free(sorted_tst_p);
-	free((void *)tst_p);
 }
 
 /* add a timestamp entry */
@@ -885,14 +792,16 @@ static void timestamp_add_now(uint32_t timestamp_id)
 {
 	struct timestamp_table *tst_p;
 	struct mapping timestamp_mapping;
-	size_t tst_size;
 
-	if (map_cbmem_entry_rw(CBMEM_ID_TIMESTAMP, &timestamp_mapping, (uint8_t **)&tst_p,
-			       &tst_size)) {
-		fprintf(stderr, "Unable to find timestamps.\n");
-		abort();
+	if (timestamps.tag != LB_TAG_TIMESTAMPS) {
+		die("No timestamps found in coreboot table.\n");
 	}
 
+	tst_p = map_memory_with_prot(&timestamp_mapping, timestamps.cbmem_addr,
+				     timestamps.size, PROT_READ | PROT_WRITE);
+	if (!tst_p)
+		die("Unable to map timestamp table\n");
+
 	/*
 	 * Note that coreboot sizes the cbmem entry in the table according to
 	 * max_entries, so it's OK to just add more entries if there's room.
@@ -1086,24 +995,32 @@ static void parse_tpm2_log(const struct tcg_efi_spec_id_event *tpm2_log)
 }
 
 /* Dump the TPM log table in format defined by specifications */
-static void dump_tpm_std_log(void *buf)
+static void dump_tpm_std_log(uint64_t addr, size_t size)
 {
+	const void *event_log;
 	const struct tcpa_spec_entry *tspec_entry;
 	const struct tcg_efi_spec_id_event *tcg_spec_entry;
+	struct mapping log_mapping;
 
-	tspec_entry = buf;
+	event_log = map_memory(&log_mapping, addr, size);
+	if (!event_log)
+		die("Unable to map TPM eventlog\n");
+
+	tspec_entry = event_log;
 	if (!strcmp((const char *)tspec_entry->signature, TCPA_SPEC_ID_EVENT_SIGNATURE)) {
 		if (tspec_entry->spec_version_major == 1 &&
-		    tspec_entry->spec_version_minor == 2 && tspec_entry->spec_errata >= 1 &&
+		    tspec_entry->spec_version_minor == 2 &&
+		    tspec_entry->spec_errata >= 1 &&
 		    le32toh(tspec_entry->entry.event_type) == EV_NO_ACTION) {
 			parse_tpm12_log(tspec_entry);
 		} else {
 			fprintf(stderr, "Unknown TPM1.2 log specification\n");
 		}
+		unmap_memory(&log_mapping);
 		return;
 	}
 
-	tcg_spec_entry = buf;
+	tcg_spec_entry = event_log;
 	if (!strcmp((const char *)tcg_spec_entry->signature, TCG_EFI_SPEC_ID_EVENT_SIGNATURE)) {
 		if (tcg_spec_entry->spec_version_major == 2 &&
 		    tcg_spec_entry->spec_version_minor == 0 &&
@@ -1112,25 +1029,42 @@ static void dump_tpm_std_log(void *buf)
 		} else {
 			fprintf(stderr, "Unknown TPM2 log specification.\n");
 		}
+		unmap_memory(&log_mapping);
 		return;
 	}
 
 	fprintf(stderr, "Unknown TPM log specification: %.*s\n",
 		(int)sizeof(tcg_spec_entry->signature),
 		(const char *)tcg_spec_entry->signature);
+
+	unmap_memory(&log_mapping);
 }
 
 /* dump the TPM CB log table */
 static void dump_tpm_cb_log(void)
 {
 	const struct tpm_cb_log_table *tclt_p;
-	size_t tclt_size;
+	size_t size;
+	struct mapping log_mapping;
 
-	if (get_cbmem_entry(CBMEM_ID_TPM_CB_LOG, (uint8_t **)&tclt_p, &tclt_size)) {
-		fprintf(stderr, "coreboot TPM log not found.\n");
-		abort();
+	if (tpm_cb_log.tag != LB_TAG_TPM_CB_LOG) {
+		fprintf(stderr, "No TPM log found in coreboot table.\n");
+		return;
 	}
 
+	size = sizeof(*tclt_p);
+	tclt_p = map_memory(&log_mapping, tpm_cb_log.cbmem_addr, size);
+	if (!tclt_p)
+		die("Unable to map TPM log header\n");
+
+	size += tclt_p->num_entries * sizeof(tclt_p->entries[0]);
+
+	unmap_memory(&log_mapping);
+
+	tclt_p = map_memory(&log_mapping, tpm_cb_log.cbmem_addr, size);
+	if (!tclt_p)
+		die("Unable to map full TPM log table\n");
+
 	printf("coreboot TPM log:\n\n");
 
 	for (uint16_t i = 0; i < tclt_p->num_entries; i++) {
@@ -1141,22 +1075,30 @@ static void dump_tpm_cb_log(void)
 		printf(" %s [%s]\n", tce->digest_type, tce->name);
 	}
 
-	free((void *)tclt_p);
+	unmap_memory(&log_mapping);
 }
 
 static void dump_tpm_log(void)
 {
-	uint8_t *buf;
+	uint64_t start;
 	size_t size;
 
-	if (!get_cbmem_entry(CBMEM_ID_TCPA_TCG_LOG, &buf, &size) ||
-	    !get_cbmem_entry(CBMEM_ID_TPM2_TCG_LOG, &buf, &size)) {
-		dump_tpm_std_log(buf);
-		free(buf);
-	} else
+	if (!find_cbmem_entry(CBMEM_ID_TCPA_TCG_LOG, &start, &size) ||
+	    !find_cbmem_entry(CBMEM_ID_TPM2_TCG_LOG, &start, &size))
+		dump_tpm_std_log(start, size);
+	else
 		dump_tpm_cb_log();
 }
 
+struct cbmem_console {
+	uint32_t size;
+	uint32_t cursor;
+	uint8_t  body[];
+}  __attribute__ ((__packed__));
+
+#define CBMC_CURSOR_MASK ((1 << 28) - 1)
+#define CBMC_OVERFLOW (1 << 31)
+
 enum console_print_type {
 	CONSOLE_PRINT_FULL = 0,
 	CONSOLE_PRINT_LAST,
@@ -1192,37 +1134,50 @@ static void dump_console(enum console_print_type type, int max_loglevel, int pri
 	const struct cbmem_console *console_p;
 	char *console_c;
 	size_t size, cursor, previous;
-	size_t console_buf_size;
+	struct mapping console_mapping;
 
-	if (get_cbmem_entry(CBMEM_ID_CONSOLE, (uint8_t **)&console_p, &console_buf_size)) {
-		fprintf(stderr, "CBMEM console not found.\n");
-		abort();
+	if (console.tag != LB_TAG_CBMEM_CONSOLE) {
+		fprintf(stderr, "No console found in coreboot table.\n");
+		return;
 	}
 
+	size = sizeof(*console_p);
+	console_p = map_memory(&console_mapping, console.cbmem_addr, size);
+	if (!console_p)
+		die("Unable to map console object.\n");
+
 	cursor = console_p->cursor & CBMC_CURSOR_MASK;
 	if (!(console_p->cursor & CBMC_OVERFLOW) && cursor < console_p->size)
 		size = cursor;
 	else
 		size = console_p->size;
+	unmap_memory(&console_mapping);
 
 	console_c = malloc(size + 1);
 	if (!console_c) {
 		fprintf(stderr, "Not enough memory for console.\n");
-		free((void *)console_p);
-		abort();
+		exit(1);
 	}
 	console_c[size] = '\0';
 
+	console_p = map_memory(&console_mapping, console.cbmem_addr,
+		size + sizeof(*console_p));
+
+	if (!console_p)
+		die("Unable to map full console object.\n");
+
 	if (console_p->cursor & CBMC_OVERFLOW) {
 		if (cursor >= size) {
 			printf("cbmem: ERROR: CBMEM console struct is illegal, "
 			       "output may be corrupt or out of order!\n\n");
 			cursor = 0;
 		}
-		memcpy(console_c, console_p->body + cursor, size - cursor);
-		memcpy(console_c + size - cursor, console_p->body, cursor);
+		aligned_memcpy(console_c, console_p->body + cursor,
+			       size - cursor);
+		aligned_memcpy(console_c + size - cursor,
+			       console_p->body, cursor);
 	} else {
-		memcpy(console_c, console_p->body, size);
+		aligned_memcpy(console_c, console_p->body, size);
 	}
 
 	/* Slight memory corruption may occur between reboots and give us a few
@@ -1297,88 +1252,109 @@ static void dump_console(enum console_print_type type, int max_loglevel, int pri
 		printf(BIOS_LOG_ESCAPE_RESET);
 
 	free(console_c);
-	free((void *)console_p);
+	unmap_memory(&console_mapping);
 }
 
-/* Hexdump provided buffer using start_address as an offset in the output. */
-static void hexdump(const uintptr_t start_address, const uint8_t *buf, const int length)
+static void hexdump(unsigned long memory, int length)
 {
 	int i;
+	const uint8_t *m;
 	int all_zero = 0;
+	struct mapping hexdump_mapping;
+
+	m = map_memory(&hexdump_mapping, memory, length);
+	if (!m)
+		die("Unable to map hexdump memory.\n");
 
 	for (i = 0; i < length; i += 16) {
 		int j;
 
 		all_zero++;
 		for (j = 0; j < 16; j++) {
-			if (buf[i + j] != 0) {
+			if(m[i+j] != 0) {
 				all_zero = 0;
 				break;
 			}
 		}
 
 		if (all_zero < 2) {
-			printf("%08lx:", start_address + i);
+			printf("%08lx:", memory + i);
 			for (j = 0; j < 16; j++)
-				printf(" %02x", buf[i + j]);
+				printf(" %02x", m[i+j]);
 			printf("  ");
 			for (j = 0; j < 16; j++)
-				printf("%c", isprint(buf[i + j]) ? buf[i + j] : '.');
+				printf("%c", isprint(m[i+j]) ? m[i+j] : '.');
 			printf("\n");
 		} else if (all_zero == 2) {
 			printf("...\n");
 		}
 	}
+
+	unmap_memory(&hexdump_mapping);
 }
 
 static void dump_cbmem_hex(void)
 {
-	struct mapping cbmem_mapping;
-	struct lb_memory *memory;
-	const uint8_t *buf = NULL;
-	size_t size = 0;
-
-	lb_table_get_entry(LB_TAG_MEMORY, (uint8_t **)&memory, &size);
-
-	if (!memory)
-		die("No memory entries available.\n");
-
-	const int entries = (memory->size - sizeof(*memory)) / sizeof(memory->map[0]);
-	/* First from the end is CBMEM */
-	for (int i = entries - 1; i >= 0; --i) {
-		if (memory->map[i].type != LB_MEM_TABLE)
-			continue;
-
-		buf = map_memory(&cbmem_mapping, memory->map[i].start, memory->map[i].size);
-		if (!buf)
-			die("Unable to map CBMEM area memory.\n");
-
-		size = memory->map[i].size;
-		break;
+	if (cbmem.type != LB_MEM_TABLE) {
+		fprintf(stderr, "No coreboot CBMEM area found!\n");
+		return;
 	}
 
-	if (!buf)
-		die("Unable to find CBMEM area memory entry.\n");
+	hexdump(cbmem.start, cbmem.size);
+}
 
-	hexdump(cbmem_mapping.phys, buf, size);
+static void rawdump(uint64_t base, uint64_t size)
+{
+	const uint8_t *m;
+	struct mapping dump_mapping;
 
-	unmap_memory(&cbmem_mapping);
-	free(memory);
+	m = map_memory(&dump_mapping, base, size);
+	if (!m)
+		die("Unable to map rawdump memory\n");
+
+	for (uint64_t i = 0 ; i < size; i++)
+		printf("%c", m[i]);
+
+	unmap_memory(&dump_mapping);
 }
 
 static void dump_cbmem_raw(unsigned int id)
 {
-	uint8_t *buf;
-	size_t size;
+	const uint8_t *table;
+	size_t offset;
+	uint64_t base = 0;
+	uint64_t size = 0;
 
-	if (get_cbmem_entry(id, &buf, &size)) {
-		fprintf(stderr, "cbmem entry id: %#x not found.\n", id);
-		abort();
+	table = mapping_virt(&lbtable_mapping);
+
+	if (table == NULL)
+		return;
+
+	offset = 0;
+
+	while (offset < mapping_size(&lbtable_mapping)) {
+		const struct lb_record *lbr;
+		struct lb_cbmem_entry lbe;
+
+		lbr = (const void *)(table + offset);
+		offset += lbr->size;
+
+		if (lbr->tag != LB_TAG_CBMEM_ENTRY)
+			continue;
+
+		aligned_memcpy(&lbe, lbr, sizeof(lbe));
+		if (lbe.id == id) {
+			debug("found id for raw dump %0x", lbe.id);
+			base = lbe.address;
+			size = lbe.entry_size;
+			break;
+		}
 	}
 
-	fwrite(buf, 1, size, stdout);
-
-	free(buf);
+	if (!base)
+		fprintf(stderr, "id %0x not found in cbtable\n", id);
+	else
+		rawdump(base, size);
 }
 
 struct cbmem_id_to_name {
@@ -1423,31 +1399,34 @@ static void cbmem_print_entry(int n, uint32_t id, uint64_t base, uint64_t size)
 
 static void dump_cbmem_toc(void)
 {
-	int i = 0;
-	const uint8_t *table = NULL;
-	size_t table_size = 0;
+	int i;
+	const uint8_t *table;
+	size_t offset;
 
-	if (get_cbmem_entry(CBMEM_ID_CBTABLE, (uint8_t **)&table, &table_size)) {
-		fprintf(stderr, "coreboot table not found.\n");
-		abort();
-	}
+	table = mapping_virt(&lbtable_mapping);
 
-	const struct lb_header *lbh = (const struct lb_header *)table;
+	if (table == NULL)
+		return;
 
 	printf("CBMEM table of contents:\n");
-	printf("    %-20s  %-8s  %-8s  %-8s\n", "NAME", "ID", "START", "LENGTH");
+	printf("    %-20s  %-8s  %-8s  %-8s\n", "NAME", "ID", "START",
+			"LENGTH");
 
-	const struct lb_record *lbr = NULL;
-	for (size_t offset = lbh->header_bytes;
-	     offset < lbh->table_bytes + lbh->header_bytes - sizeof(struct lb_cbmem_entry);
-	     offset += lbr->size) {
-		lbr = (const struct lb_record *)&table[offset];
+	i = 0;
+	offset = 0;
+
+	while (offset < mapping_size(&lbtable_mapping)) {
+		const struct lb_record *lbr;
+		struct lb_cbmem_entry lbe;
+
+		lbr = (const void *)(table + offset);
+		offset += lbr->size;
 
 		if (lbr->tag != LB_TAG_CBMEM_ENTRY)
 			continue;
 
-		const struct lb_cbmem_entry *lbe = (const struct lb_cbmem_entry *)lbr;
-		cbmem_print_entry(i, lbe->id, lbe->address, lbe->entry_size);
+		aligned_memcpy(&lbe, lbr, sizeof(lbe));
+		cbmem_print_entry(i, lbe.id, lbe.address, lbe.entry_size);
 		i++;
 	}
 }
@@ -1482,23 +1461,21 @@ static int mkpath(char *path, mode_t mode)
 static void dump_coverage(void)
 {
 	uint64_t start;
-	uint8_t *coverage;
 	size_t size;
+	const void *coverage;
+	struct mapping coverage_mapping;
 	unsigned long phys_offset;
 #define phys_to_virt(x) ((void *)(unsigned long)(x) + phys_offset)
 
-	if (get_cbmem_entry(CBMEM_ID_COVERAGE, &coverage, &size)) {
-		fprintf(stderr, "No coverage information found\n");
-		return;
-	}
-
-	// Physical address is needed for pointer translation
 	if (find_cbmem_entry(CBMEM_ID_COVERAGE, &start, &size)) {
 		fprintf(stderr, "No coverage information found\n");
 		return;
 	}
 
 	/* Map coverage area */
+	coverage = map_memory(&coverage_mapping, start, size);
+	if (!coverage)
+		die("Unable to map coverage area.\n");
 	phys_offset = (unsigned long)coverage - (unsigned long)start;
 
 	printf("Dumping coverage data...\n");
@@ -1535,7 +1512,7 @@ static void dump_coverage(void)
 		else
 			file = NULL;
 	}
-	free(coverage);
+	unmap_memory(&coverage_mapping);
 }
 
 static void print_version(void)

From de259ad970763ccf8aa421e8dd28d6e216ba7837 Mon Sep 17 00:00:00 2001
From: Luca Lai <luca.lai@lcfc.corp-partner.google.com>
Date: Tue, 10 Jun 2025 09:14:40 +0800
Subject: [PATCH 1269/3886] mb/trulo/var/pujjolo: Enable s0ix function

Set s0ix_enable to true.

BUG=b:395763555
BRANCH=none
TEST=Build and boot to pujjolo. Verify functions work.

Change-Id: I69eff7c54e3c46549cd47e7c9413a9c0b978783d
Signed-off-by: Luca Lai <luca.lai@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88020
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jayvik Desai <jayvik@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
---
 src/mainboard/google/brya/variants/pujjolo/overridetree.cb | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/src/mainboard/google/brya/variants/pujjolo/overridetree.cb b/src/mainboard/google/brya/variants/pujjolo/overridetree.cb
index 5a42d3fcef..6eb057b30d 100644
--- a/src/mainboard/google/brya/variants/pujjolo/overridetree.cb
+++ b/src/mainboard/google/brya/variants/pujjolo/overridetree.cb
@@ -11,6 +11,9 @@ fw_config
 end
 chip soc/intel/alderlake
 
+	# S0ix enable
+	register "s0ix_enable" = "true"
+
 	# Acoustic settings
 	register "acoustic_noise_mitigation" = "1"
 	register "slow_slew_rate[VR_DOMAIN_IA]" = "SLEW_FAST_8"

From 317affb0ad0f8c175b9dcde5e6e37943a6506de1 Mon Sep 17 00:00:00 2001
From: Luca Lai <luca.lai@lcfc.corp-partner.google.com>
Date: Tue, 10 Jun 2025 10:51:11 +0800
Subject: [PATCH 1270/3886] mb/trulo/var/pujjolo: Enable Elan touchscreen
 function.

Add Elan touchscreen setting to let funtion work fine.

BUG=b:395763555
BRANCH=none
TEST=Build and boot to pujjolo. Verify functions work.

Change-Id: I7a6f56d46347f680f80feb691fc5104f8acf3f29
Signed-off-by: Luca Lai <luca.lai@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88021
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Jayvik Desai <jayvik@google.com>
---
 .../brya/variants/pujjolo/overridetree.cb       | 17 +++++++++++++++++
 1 file changed, 17 insertions(+)

diff --git a/src/mainboard/google/brya/variants/pujjolo/overridetree.cb b/src/mainboard/google/brya/variants/pujjolo/overridetree.cb
index 6eb057b30d..1b4ebb4cd3 100644
--- a/src/mainboard/google/brya/variants/pujjolo/overridetree.cb
+++ b/src/mainboard/google/brya/variants/pujjolo/overridetree.cb
@@ -160,6 +160,23 @@ chip soc/intel/alderlake
 			end
 		end #I2C0
 		device ref i2c1 on
+			chip drivers/i2c/hid
+				register "generic.hid" = ""ELAN901C""
+				register "generic.desc" = ""ELAN Touchscreen""
+				register "generic.irq" = "ACPI_IRQ_LEVEL_HIGH(GPP_E11_IRQ)"
+				register "generic.detect" = "1"
+				register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C1)"
+				register "generic.reset_delay_ms" = "20"
+				register "generic.reset_off_delay_ms" = "2"
+				register "generic.stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C4)"
+				register "generic.stop_delay_ms" = "280"
+				register "generic.stop_off_delay_ms" = "2"
+				register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C0)"
+				register "generic.enable_delay_ms" = "1"
+				register "generic.has_power_resource" = "1"
+				register "hid_desc_reg_offset" = "0x01"
+				device i2c 10 on end
+			end
 			chip drivers/i2c/hid
 				register "generic.hid" = ""GDIX0000""
 				register "generic.desc" = ""Goodix Touchscreen""

From 08c8a74170d49c19311aa266e09c864863a0437b Mon Sep 17 00:00:00 2001
From: Luca Lai <luca.lai@lcfc.corp-partner.google.com>
Date: Sun, 8 Jun 2025 23:01:25 +0800
Subject: [PATCH 1271/3886] mb/trulo/var/pujjolo: Add MB usb-a port3 function.

Add usb-a port3 setting to let funtion work fine.

BUG=b:395763555
BRANCH=none
TEST=Build and boot to pujjolo. Verify functions work.

Change-Id: I132f34a5c341f64d829bb78be9d400a77889f291
Signed-off-by: Luca Lai <luca.lai@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87998
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
---
 .../google/brya/variants/pujjolo/overridetree.cb          | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/src/mainboard/google/brya/variants/pujjolo/overridetree.cb b/src/mainboard/google/brya/variants/pujjolo/overridetree.cb
index 1b4ebb4cd3..d3c938252a 100644
--- a/src/mainboard/google/brya/variants/pujjolo/overridetree.cb
+++ b/src/mainboard/google/brya/variants/pujjolo/overridetree.cb
@@ -38,6 +38,7 @@ chip soc/intel/alderlake
 
 	register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC_SKIP)"	# USB2_C0
 	register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC_SKIP)"	# USB2_C1
+	register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)"	# USB-A0
 	register "usb2_ports[3]" = "USB2_PORT_MID(OC_SKIP)"	# USB-A1
 	register "usb2_ports[4]" = "USB2_PORT_MID(OC_SKIP)"	# WWAN
 	register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)"	# UF Camera
@@ -534,6 +535,13 @@ chip soc/intel/alderlake
 						register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, LEFT, ACPI_PLD_GROUP(2, 1))"
 						device ref usb2_port2 on end
 					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB2 Type-A Port A0 (DB)""
+						register "type" = "UPC_TYPE_A"
+						register "use_custom_pld" = "true"
+						register "custom_pld" = "ACPI_PLD_TYPE_A(RIGHT, LEFT, ACPI_PLD_GROUP(3, 1))"
+						device ref usb2_port3 on end
+					end
 					chip drivers/usb/acpi
 						register "desc" = ""USB2 Type-A Port A1 (DB)""
 						register "type" = "UPC_TYPE_A"

From 881fe9cef612da32d226be920018352fd513ccca Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Mon, 9 Jun 2025 16:21:27 -0500
Subject: [PATCH 1272/3886] soc/intel/alderlake: Add cpuid_to_adl mapping for
 Core 3 N350 SoC
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Add a mapping for the Core 3 N350 SoC, which has a MCH with PCI DID
0x4617, 8 efficiency cores, and a 7W TDP. This eliminates an error when
setting power limits due to the missing entry:

[ERROR] unknown SA ID: 0x4617, skipped power limits configuration

TEST=build/boot starlabs/starlite_adl with ADL-N Core 3 N350 SoC.

Change-Id: Ibd701ec5589a9a023a5538f470ff234a23249b45
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88018
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
---
 src/soc/intel/alderlake/chip.h | 1 +
 1 file changed, 1 insertion(+)

diff --git a/src/soc/intel/alderlake/chip.h b/src/soc/intel/alderlake/chip.h
index 3473b0643a..25e0f6ed28 100644
--- a/src/soc/intel/alderlake/chip.h
+++ b/src/soc/intel/alderlake/chip.h
@@ -162,6 +162,7 @@ static const struct {
 	{ PCI_DID_INTEL_ADL_M_ID_1, ADL_M_282_15W_CORE, TDP_15W },
 	{ PCI_DID_INTEL_ADL_M_ID_2, ADL_M_242_CORE, TDP_9W },
 	{ PCI_DID_INTEL_ADL_N_ID_1, ADL_N_081_15W_CORE, TDP_15W },
+	{ PCI_DID_INTEL_ADL_N_ID_1, ADL_N_081_7W_CORE, TDP_7W },
 	{ PCI_DID_INTEL_ADL_N_ID_2, ADL_N_041_6W_CORE, TDP_6W },
 	{ PCI_DID_INTEL_ADL_N_ID_3, ADL_N_041_6W_CORE, TDP_6W },
 	{ PCI_DID_INTEL_ADL_N_ID_4, ADL_N_021_6W_CORE, TDP_6W },

From 4d3dc433f9695ac7641e76ae12a952063298969a Mon Sep 17 00:00:00 2001
From: Jincheng Li <jincheng.li@intel.com>
Date: Thu, 15 May 2025 10:17:31 +0800
Subject: [PATCH 1273/3886] mb/intel/avenuecity_crb: Use host address for
 BiosRegionBase

FMAP_SECTION_SI_BIOS_START is used to pass host address for UPD
BiosRegionBase. It changes to flash address after:
commit 2efe4df5227a ("treewide: Assume FMAP_SECTION_FLASH_START = 0")

Convert FMAP_SECTION_SI_BIOS_START to host address to set
BiosRegionBase.

TESTED=Build and boot on intel/avenuecity CRB, check boot log with:
[INFO ]  BiosRegionBase is set to ff000000
[INFO ]  BiosRegionSize is set to 1000000

Change-Id: I92589253915ad88bbb73736e10e7524b6be82499
Signed-off-by: Jincheng Li <jincheng.li@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87689
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
---
 src/mainboard/intel/avenuecity_crb/romstage.c | 6 +++++-
 1 file changed, 5 insertions(+), 1 deletion(-)

diff --git a/src/mainboard/intel/avenuecity_crb/romstage.c b/src/mainboard/intel/avenuecity_crb/romstage.c
index ef91b39f93..a77819955c 100644
--- a/src/mainboard/intel/avenuecity_crb/romstage.c
+++ b/src/mainboard/intel/avenuecity_crb/romstage.c
@@ -10,6 +10,7 @@
 #include <soc/dimm_slot.h>
 #include <soc/iio.h>
 #include <soc/romstage.h>
+#include <spi_flash.h>
 #include <static.h>
 
 #include "chip.h"
@@ -32,7 +33,10 @@ void mainboard_memory_init_params(FSPM_UPD *mupd)
 			CONFIG_BMC_KCS_BASE);
 
 	/* Set BIOS regeion UPD, otherwise MTRR might set incorrectly during TempRamExit API */
-	m_cfg->BiosRegionBase = FMAP_SECTION_SI_BIOS_START;
+	struct flash_mmap_window table;
+	spi_flash_get_mmap_windows(&table);
+
+	m_cfg->BiosRegionBase = table.host_base + FMAP_SECTION_SI_BIOS_START;
 	m_cfg->BiosRegionSize = FMAP_SECTION_SI_BIOS_SIZE;
 	printk(BIOS_INFO, "BiosRegionBase is set to %x\n", mupd->FspmConfig.BiosRegionBase);
 	printk(BIOS_INFO, "BiosRegionSize is set to %x\n", mupd->FspmConfig.BiosRegionSize);

From f85f7d7aed975e0ae3d06fc4a24384ab2ddecabd Mon Sep 17 00:00:00 2001
From: Jincheng Li <jincheng.li@intel.com>
Date: Thu, 15 May 2025 10:22:46 +0800
Subject: [PATCH 1274/3886] mb/intel/beechnutcity_crb: Use host address for
 BiosRegionBase

FMAP_SECTION_SI_BIOS_START is used to pass host address for UPD
BiosRegionBase. It changes to flash address after:
commit 2efe4df5227a ("treewide: Assume FMAP_SECTION_FLASH_START = 0")

Convert FMAP_SECTION_SI_BIOS_START to host address to set
BiosRegionBase.

TESTED=Build and boot on intel/beechnutcity CRB, check boot log with:
[INFO ]  BiosRegionBase is set to ff000000
[INFO ]  BiosRegionSize is set to 1000000

Change-Id: Ie115bd8e9044455185f82885a306849c509157bb
Signed-off-by: Jincheng Li <jincheng.li@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87690
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/intel/beechnutcity_crb/romstage.c | 6 +++++-
 1 file changed, 5 insertions(+), 1 deletion(-)

diff --git a/src/mainboard/intel/beechnutcity_crb/romstage.c b/src/mainboard/intel/beechnutcity_crb/romstage.c
index ef91b39f93..a77819955c 100644
--- a/src/mainboard/intel/beechnutcity_crb/romstage.c
+++ b/src/mainboard/intel/beechnutcity_crb/romstage.c
@@ -10,6 +10,7 @@
 #include <soc/dimm_slot.h>
 #include <soc/iio.h>
 #include <soc/romstage.h>
+#include <spi_flash.h>
 #include <static.h>
 
 #include "chip.h"
@@ -32,7 +33,10 @@ void mainboard_memory_init_params(FSPM_UPD *mupd)
 			CONFIG_BMC_KCS_BASE);
 
 	/* Set BIOS regeion UPD, otherwise MTRR might set incorrectly during TempRamExit API */
-	m_cfg->BiosRegionBase = FMAP_SECTION_SI_BIOS_START;
+	struct flash_mmap_window table;
+	spi_flash_get_mmap_windows(&table);
+
+	m_cfg->BiosRegionBase = table.host_base + FMAP_SECTION_SI_BIOS_START;
 	m_cfg->BiosRegionSize = FMAP_SECTION_SI_BIOS_SIZE;
 	printk(BIOS_INFO, "BiosRegionBase is set to %x\n", mupd->FspmConfig.BiosRegionBase);
 	printk(BIOS_INFO, "BiosRegionSize is set to %x\n", mupd->FspmConfig.BiosRegionSize);

From b322d309442c0ae11e407a1a1727cefdbdc205cd Mon Sep 17 00:00:00 2001
From: David Wu <david_wu@quanta.corp-partner.google.com>
Date: Mon, 9 Jun 2025 09:28:20 +0800
Subject: [PATCH 1275/3886] mb/google/brya/var/moxie: Enable RTD3 for SSD to
 resolve S0ix issue

Some SSDs block the CPU from reaching C10 during the S0ix suspend
without the RTD3 configuration. Add PCIe RTD3 support so NVMe gets
placed into D3 state when entering S0ix.

Enable and reset GPIOs are configured as per pin mapping in gpio.c.

BUG=b:391612392 b:421064225
TEST=Run suspend_stress_test on moxie and verify that the device
suspends to S0ix.

Change-Id: I6b2c264fd7244ab84e82919354afb2b49a22177a
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88000
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Pranava Y N <pranavayn@google.com>
---
 src/mainboard/google/brya/variants/moxie/overridetree.cb | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/src/mainboard/google/brya/variants/moxie/overridetree.cb b/src/mainboard/google/brya/variants/moxie/overridetree.cb
index 19a20a14ec..9733305b69 100644
--- a/src/mainboard/google/brya/variants/moxie/overridetree.cb
+++ b/src/mainboard/google/brya/variants/moxie/overridetree.cb
@@ -148,6 +148,13 @@ chip soc/intel/alderlake
 				.clk_src = 0,
 				.flags = PCIE_RP_LTR | PCIE_RP_AER,
 			}"
+			chip soc/intel/common/block/pcie/rtd3
+				register "is_storage" = "true"
+				register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_F14)"
+				register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B4)"
+				register "srcclk_pin" = "0"
+				device generic 0 on end
+			end
 		end
 		device ref tbt_pcie_rp0 on
 			probe MB_USBC TC_USB4

From c796c68dec6681195afdbd1a32a1893cf404ed2d Mon Sep 17 00:00:00 2001
From: "P, Usha" <usha.p@intel.com>
Date: Thu, 5 Jun 2025 13:36:28 +0530
Subject: [PATCH 1276/3886] mb/google/ocelot: Update MAINBOARD_PART_NUMBER

BUG=b:394208231
TEST=Build Ocelot and verify it compiles without any error.

Change-Id: I29070d871666f42615ba7afae9b9adb07e089fdc
Signed-off-by: P, Usha <usha.p@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87966
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Pranava Y N <pranavayn@google.com>
---
 src/mainboard/google/ocelot/Kconfig | 4 +---
 1 file changed, 1 insertion(+), 3 deletions(-)

diff --git a/src/mainboard/google/ocelot/Kconfig b/src/mainboard/google/ocelot/Kconfig
index a4b042235c..0a0e7fba3d 100644
--- a/src/mainboard/google/ocelot/Kconfig
+++ b/src/mainboard/google/ocelot/Kconfig
@@ -108,9 +108,8 @@ config MAINBOARD_FAMILY
 	string
 	default "Google_Ocelot"
 
-# FIXME: update once Ocelot config is available
 config MAINBOARD_PART_NUMBER
-	default "Fatcat" if BOARD_GOOGLE_OCELOT
+	default "Ocelot" if BOARD_GOOGLE_OCELOT
 
 config MEMORY_SOLDERDOWN
 	def_bool n
@@ -121,7 +120,6 @@ config TPM_TIS_ACPI_INTERRUPT
 	int
 	default 47 if BOARD_GOOGLE_OCELOT # GPE0_DW1_15 (GPP_D15)
 
-# FIXME: update as per board schematics
 config UART_FOR_CONSOLE
 	int
 	default 0

From 925845c38cd029b2eb40c05fc194951c7c2c037f Mon Sep 17 00:00:00 2001
From: "P, Usha" <usha.p@intel.com>
Date: Mon, 9 Jun 2025 08:50:32 +0530
Subject: [PATCH 1277/3886] mb/google/ocelot: Update Kconfig

Update TPM related default values for DRIVER_TPM_I2C_BUS and
TPM_TIS_ACPI_INTERRUPT based on schematic_1433518.

BUG=b:394208231
TEST=Build Ocelot and verify it compiles without any error.

Change-Id: Ifbd99265a36602b7d820cc088317579496144c9d
Signed-off-by: P, Usha <usha.p@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88003
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Pranava Y N <pranavayn@google.com>
---
 src/mainboard/google/ocelot/Kconfig | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/mainboard/google/ocelot/Kconfig b/src/mainboard/google/ocelot/Kconfig
index 0a0e7fba3d..319f7d2c33 100644
--- a/src/mainboard/google/ocelot/Kconfig
+++ b/src/mainboard/google/ocelot/Kconfig
@@ -96,7 +96,7 @@ config DRIVER_TPM_I2C_ADDR
 
 config DRIVER_TPM_I2C_BUS
 	hex
-	default 0x03 if BOARD_GOOGLE_OCELOT
+	default 0x01 if BOARD_GOOGLE_OCELOT
 
 config HAVE_SLP_S0_GATE
 	def_bool n
@@ -118,7 +118,7 @@ config MEMORY_SOLDERDOWN
 
 config TPM_TIS_ACPI_INTERRUPT
 	int
-	default 47 if BOARD_GOOGLE_OCELOT # GPE0_DW1_15 (GPP_D15)
+	default 17 if BOARD_GOOGLE_OCELOT # GPE0_DW0_17 (GPP_B17)
 
 config UART_FOR_CONSOLE
 	int

From ab29f52ee2c816c62edc0eff2df576370abe3a09 Mon Sep 17 00:00:00 2001
From: Angel Pons <th3fanbus@gmail.com>
Date: Sun, 25 May 2025 13:03:04 +0200
Subject: [PATCH 1278/3886] Haswell NRI: Measure per-task execution time

Add some simple execution time measurement code. It only logs execution
times if `DEBUG_RAM_SETUP` is selected. Note that this will fill things
like pre-RAM CBMEM console, but NRI's debug output is already extremely
verbose, and will become even more verbose as additional training steps
get added.

Future plans include measuring the time spent waiting for REUT hardware
to finish testing, as that is what takes most time for complex training
algorithms (which are yet to be published).

Tested on Asrock B85M Pro4, still boots to Arch Linux. Output example:

    +------------------+------------+
    | Task             |      msecs |
    +------------------+------------+
    | PROCSPD          |        503 |
    | INITMPLL         |         33 |
    | CONVTIM          |         43 |
    | CONFMC           |          1 |
    | MEMMAP           |         39 |
    | JEDECINIT        |          1 |
    | PRETRAIN         |         23 |
    | SOT              |        394 |
    | RCVET            |       1448 |
    | RDMPRT           |       1088 |
    | JWRL             |       1975 |
    | OPTCOMP          |          0 |
    | POSTTRAIN        |          0 |
    | ACTIVATE         |          0 |
    | SAVE_TRAIN       |          0 |
    | SAVE_NONT        |          0 |
    | RAMINITEND       |          4 |
    +------------------+------------+
    | Total            |       5558 |
    +------------------+------------+

Note: the board had 4x dual-rank DIMMs installed, which gives the worst
possible boot time (more ranks to train, and that means more log output
to push through 115200 baud serial). Without debug logging, training is
substantially faster.

Change-Id: Ie4b6f6246e54f23d03babdb6fa0271538f69984e
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87830
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 .../haswell/native_raminit/raminit_main.c     | 35 ++++++++++++++++++-
 1 file changed, 34 insertions(+), 1 deletion(-)

diff --git a/src/northbridge/intel/haswell/native_raminit/raminit_main.c b/src/northbridge/intel/haswell/native_raminit/raminit_main.c
index 21c953b332..d211bfb20a 100644
--- a/src/northbridge/intel/haswell/native_raminit/raminit_main.c
+++ b/src/northbridge/intel/haswell/native_raminit/raminit_main.c
@@ -10,6 +10,7 @@
 #include <northbridge/intel/haswell/raminit.h>
 #include <static.h>
 #include <string.h>
+#include <timer.h>
 #include <types.h>
 
 #include "raminit_native.h"
@@ -85,6 +86,9 @@ static const struct task_entry fast_boot[] = {
 	{ raminit_done,                                           true, "RAMINITEND", },
 };
 
+_Static_assert(ARRAY_SIZE(cold_boot) >= ARRAY_SIZE(fast_boot),
+		"Code assumes cold boot task list is the longest one");
+
 /* Return a generic stepping value to make stepping checks simpler */
 static enum generic_stepping get_stepping(const uint32_t cpuid)
 {
@@ -120,6 +124,9 @@ static void initialize_ctrl(struct sysinfo *ctrl)
 	ctrl->bootmode = bootmode;
 }
 
+/** TODO: Adjust unit scale dynamically? **/
+#define T_SCALE 1000 /* 1 = usecs, 1000 = msecs */
+
 static enum raminit_status try_raminit(
 	struct sysinfo *ctrl,
 	const struct task_entry *const schedule,
@@ -127,7 +134,11 @@ static enum raminit_status try_raminit(
 {
 	enum raminit_status status = RAMINIT_STATUS_UNSPECIFIED_ERROR;
 
-	for (size_t i = 0; i < length; i++) {
+	long spent_time[ARRAY_SIZE(cold_boot)] = { 0 };
+	long total = 0;
+
+	size_t i;
+	for (i = 0; i < length; i++) {
 		const struct task_entry *const entry = &schedule[i];
 		assert(entry);
 		assert(entry->name);
@@ -136,14 +147,36 @@ static enum raminit_status try_raminit(
 
 		assert(entry->task);
 		printk(RAM_DEBUG, "\nExecuting raminit task %s\n", entry->name);
+		struct mono_time prev, curr;
+		timer_monotonic_get(&prev);
 		status = entry->task(ctrl);
+		timer_monotonic_get(&curr);
+		spent_time[i] = mono_time_diff_microseconds(&prev, &curr);
 		printk(RAM_DEBUG, "\n");
 		if (status) {
+			i++;
 			printk(BIOS_ERR, "raminit failed on step %s\n", entry->name);
 			break;
 		}
 	}
 
+	if (CONFIG(DEBUG_RAM_SETUP)) {
+		const char unit_multiplier = T_SCALE == 1 ? 'u' : 'm';
+		printk(RAM_DEBUG, "+------------------+------------+\n");
+		printk(RAM_DEBUG, "| Task             |      %csecs |\n", unit_multiplier);
+		printk(RAM_DEBUG, "+------------------+------------+\n");
+		assert(i <= length);
+		for (size_t j = 0; j < i; j++) {
+			char buf[] = "                ";
+			strncpy(buf, schedule[j].name, strlen(schedule[j].name));
+			printk(RAM_DEBUG, "| %s | % 10ld |\n", buf, spent_time[j] / T_SCALE);
+			total += spent_time[j];
+		}
+		printk(RAM_DEBUG, "+------------------+------------+\n");
+		printk(RAM_DEBUG, "| Total            | % 10ld |\n", total / T_SCALE);
+		printk(RAM_DEBUG, "+------------------+------------+\n");
+	}
+
 	return status;
 }
 

From 4569adeedce0f5032f2c72b2dea92ae2147d934e Mon Sep 17 00:00:00 2001
From: Schumi Chu <schumi.chu@mitaccomputing.com>
Date: Thu, 8 May 2025 13:05:10 +0800
Subject: [PATCH 1279/3886] mainboard: Add 1S Intel Birch Stream MiTAC
 Computing SC513G6
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

The SC513G6 is a high-performance single-socket server motherboard
designed for AI, HPC, cloud, and data center applications.
Featuring Intel® Xeon® 6 Processors(LGA4710) support with up to
350W TDP, it delivers exceptional compute power, high-speed
networking, and versatile storage options in a compact SSI CEB
form factor.

Tested:
 - USB: 4 USB ports
 - PCIe: PCIE#1, PCIE#2, PCIE#3, PCIE#5 (with PCIe SATA controller,
   and PCIE#4 is only available on CPU R1S SKU)
 - M.2: M.2#1 and M.2#2
 - LAN: 2 RJ45 GbE ports
 - Graphic VGA Port
 - - Flash firmware from BMC's redfish interface (Out-of-band)

Installed with Intel® Xeon® 6756E and boots to
Ubuntu 22.04.5 LTS (6.8.0-57-generic).

Change-Id: I7b85e8548cfbdf9e52dc1956bd33e829020c052c
Signed-off-by: Schumi Chu <schumi.chu@mitaccomputing.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87571
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
---
 configs/builder/config.mitaccomputing.sc513g6 |  54 +++++++++
 src/mainboard/mitaccomputing/sc513g6/Kconfig  |  42 +++++++
 .../mitaccomputing/sc513g6/Kconfig.name       |   4 +
 .../mitaccomputing/sc513g6/Makefile.mk        |   8 ++
 .../mitaccomputing/sc513g6/board.fmd          |  12 ++
 .../mitaccomputing/sc513g6/board_info.txt     |   6 +
 .../mitaccomputing/sc513g6/bootblock.c        |  25 +++++
 .../mitaccomputing/sc513g6/config/dimm_slot.c |  22 ++++
 .../mitaccomputing/sc513g6/config/iio.c       | 105 ++++++++++++++++++
 .../mitaccomputing/sc513g6/devicetree.cb      |  42 +++++++
 src/mainboard/mitaccomputing/sc513g6/dsdt.asl |  22 ++++
 .../mitaccomputing/sc513g6/ramstage.c         |  58 ++++++++++
 .../mitaccomputing/sc513g6/romstage.c         |  57 ++++++++++
 13 files changed, 457 insertions(+)
 create mode 100644 configs/builder/config.mitaccomputing.sc513g6
 create mode 100644 src/mainboard/mitaccomputing/sc513g6/Kconfig
 create mode 100644 src/mainboard/mitaccomputing/sc513g6/Kconfig.name
 create mode 100644 src/mainboard/mitaccomputing/sc513g6/Makefile.mk
 create mode 100644 src/mainboard/mitaccomputing/sc513g6/board.fmd
 create mode 100644 src/mainboard/mitaccomputing/sc513g6/board_info.txt
 create mode 100644 src/mainboard/mitaccomputing/sc513g6/bootblock.c
 create mode 100644 src/mainboard/mitaccomputing/sc513g6/config/dimm_slot.c
 create mode 100644 src/mainboard/mitaccomputing/sc513g6/config/iio.c
 create mode 100644 src/mainboard/mitaccomputing/sc513g6/devicetree.cb
 create mode 100644 src/mainboard/mitaccomputing/sc513g6/dsdt.asl
 create mode 100644 src/mainboard/mitaccomputing/sc513g6/ramstage.c
 create mode 100644 src/mainboard/mitaccomputing/sc513g6/romstage.c

diff --git a/configs/builder/config.mitaccomputing.sc513g6 b/configs/builder/config.mitaccomputing.sc513g6
new file mode 100644
index 0000000000..63334687b9
--- /dev/null
+++ b/configs/builder/config.mitaccomputing.sc513g6
@@ -0,0 +1,54 @@
+# Type this in coreboot root directory to get a working .config:
+#   make defconfig KBUILD_DEFCONFIG=configs/builder/config.mitaccomputing.sc513g6
+
+#
+# [RO] Board Configurations
+#
+CONFIG_VENDOR_MITAC_COMPUTING=y
+CONFIG_BOARD_MITAC_COMPUTING_SC513G6=y
+
+CONFIG_HAVE_CONFIGURABLE_RAMSTAGE=y
+CONFIG_CONFIGURABLE_RAMSTAGE=y
+
+CONFIG_NO_GFX_INIT=y
+
+CONFIG_HAVE_IFD_BIN=y
+CONFIG_HAVE_PBP_BIN=n
+CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION=y
+CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y
+CONFIG_ADD_FSP_BINARIES=y
+CONFIG_PAYLOAD_LINUX=y
+
+CONFIG_UART_FOR_CONSOLE=0
+CONFIG_CONSOLE_SERIAL_115200=y
+
+CONFIG_COREBOOT_ROMSIZE_KB_65536=y
+
+#
+# [RW] IFWI Ingredients
+#
+CONFIG_IFD_BIN_PATH="site-local/sc513g6/descriptor.bin"
+CONFIG_PBP_BIN_PATH=""
+CONFIG_CPU_UCODE_BINARIES="site-local/sc513g6/ucode.mcb"
+CONFIG_FSP_T_FILE="site-local/sc513g6/Server_T.fd"
+CONFIG_FSP_M_FILE="site-local/sc513g6/Server_M.fd"
+CONFIG_FSP_S_FILE="site-local/sc513g6/Server_S.fd"
+CONFIG_FSP_HEADER_PATH="src/vendorcode/intel/fsp/fsp2_0/graniterapids/sp/"
+
+CONFIG_PAYLOAD_FILE="site-local/sc513g6/bzImage"
+CONFIG_LINUX_COMMAND_LINE="loglevel=7 earlyprintk=serial,ttyS0,115200 console=ttyS0,115200"
+
+#
+# [RW] Debug Settings
+#
+CONFIG_CONSOLE_POST=y
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8=y
+
+CONFIG_VERIFY_HOBS=y
+CONFIG_DISPLAY_MTRRS=y
+
+CONFIG_DISPLAY_FSP_CALLS_AND_STATUS=y
+CONFIG_DISPLAY_FSP_HEADER=y
+
+CONFIG_HAVE_DEBUG_GPIO=y
+CONFIG_DEBUG_GPIO=y
diff --git a/src/mainboard/mitaccomputing/sc513g6/Kconfig b/src/mainboard/mitaccomputing/sc513g6/Kconfig
new file mode 100644
index 0000000000..a201c8b6bc
--- /dev/null
+++ b/src/mainboard/mitaccomputing/sc513g6/Kconfig
@@ -0,0 +1,42 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
+if BOARD_MITAC_COMPUTING_SC513G6
+
+config BOARD_SPECIFIC_OPTIONS
+	def_bool y
+	select BOARD_ROMSIZE_KB_65536
+	select SOC_INTEL_GRANITERAPIDS
+	select SUPERIO_ASPEED_AST2400
+	select CONSOLE_OVERRIDE_LOGLEVEL
+	select HAVE_ACPI_TABLES
+	select IPMI_KCS
+	select IPMI_KCS_ROMSTAGE
+	select VPD
+	select OCP_VPD
+	select MEMORY_MAPPED_TPM
+
+config CARDBUS_PLUGIN_SUPPORT
+	bool
+	default n
+
+config MAINBOARD_DIR
+	string
+	default "mitaccomputing/sc513g6"
+
+config MAINBOARD_PART_NUMBER
+	string
+	default "SC513G6"
+
+config FMDFILE
+	string
+	default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/board.fmd"
+
+config DIMM_MAX
+	int
+	default 8
+
+config MAX_SOCKET
+	int
+	default 1
+
+endif
diff --git a/src/mainboard/mitaccomputing/sc513g6/Kconfig.name b/src/mainboard/mitaccomputing/sc513g6/Kconfig.name
new file mode 100644
index 0000000000..34c26ea7bb
--- /dev/null
+++ b/src/mainboard/mitaccomputing/sc513g6/Kconfig.name
@@ -0,0 +1,4 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
+config BOARD_MITAC_COMPUTING_SC513G6
+	bool "SC513G6"
diff --git a/src/mainboard/mitaccomputing/sc513g6/Makefile.mk b/src/mainboard/mitaccomputing/sc513g6/Makefile.mk
new file mode 100644
index 0000000000..cfff6d3851
--- /dev/null
+++ b/src/mainboard/mitaccomputing/sc513g6/Makefile.mk
@@ -0,0 +1,8 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
+bootblock-y += bootblock.c
+romstage-y += romstage.c
+romstage-y += config/dimm_slot.c
+romstage-y += config/iio.c
+ramstage-y += config/dimm_slot.c
+ramstage-y += ramstage.c
diff --git a/src/mainboard/mitaccomputing/sc513g6/board.fmd b/src/mainboard/mitaccomputing/sc513g6/board.fmd
new file mode 100644
index 0000000000..d5a34a2b04
--- /dev/null
+++ b/src/mainboard/mitaccomputing/sc513g6/board.fmd
@@ -0,0 +1,12 @@
+FLASH 64M {
+	SI_ALL 48M {
+		SI_DESC@0x0 0x1000
+	}
+	SI_BIOS 16M {
+		RW_MRC_CACHE 0x10000
+		FMAP 0x800
+		RW_VPD(PRESERVE) 0x4000
+		RO_VPD(PRESERVE) 0x4000
+		COREBOOT(CBFS)
+	}
+}
diff --git a/src/mainboard/mitaccomputing/sc513g6/board_info.txt b/src/mainboard/mitaccomputing/sc513g6/board_info.txt
new file mode 100644
index 0000000000..8621a60cc8
--- /dev/null
+++ b/src/mainboard/mitaccomputing/sc513g6/board_info.txt
@@ -0,0 +1,6 @@
+Vendor name: MiTAC Computing
+Board name: SC513G6
+Category: eval
+ROM protocol: SPI
+ROM socketed: y
+Flashrom support: y
diff --git a/src/mainboard/mitaccomputing/sc513g6/bootblock.c b/src/mainboard/mitaccomputing/sc513g6/bootblock.c
new file mode 100644
index 0000000000..4b2406048a
--- /dev/null
+++ b/src/mainboard/mitaccomputing/sc513g6/bootblock.c
@@ -0,0 +1,25 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <bootblock_common.h>
+#include <console/console.h>
+#include <intelblocks/lpc_lib.h>
+#include <soc/intel/common/block/lpc/lpc_def.h>
+#include <superio/aspeed/ast2400/ast2400.h>
+#include <superio/aspeed/common/aspeed.h>
+
+#define ASPEED_SIO_PORT 0x2E
+
+void bootblock_mainboard_early_init(void)
+{
+	/* Enable eSPI decoding for com1 (0x3f8), com2 (0x2f8) and superio (0x2e) */
+	lpc_io_setup_comm_a_b();
+	lpc_enable_fixed_io_ranges(LPC_IOE_SUPERIO_2E_2F);
+
+	if (CONFIG_UART_FOR_CONSOLE == 0 || CONFIG_UART_FOR_CONSOLE == 1) {
+		/* Set up Super I/O com1 or com2 */
+		const pnp_devfn_t serial_dev = PNP_DEV(ASPEED_SIO_PORT, AST2400_SUART1);
+		aspeed_enable_serial(serial_dev, CONFIG_TTYS0_BASE);
+	} else {
+		die("COMs other than COM1/COM2 not supported\n");
+	}
+}
diff --git a/src/mainboard/mitaccomputing/sc513g6/config/dimm_slot.c b/src/mainboard/mitaccomputing/sc513g6/config/dimm_slot.c
new file mode 100644
index 0000000000..15b8c5f5dd
--- /dev/null
+++ b/src/mainboard/mitaccomputing/sc513g6/config/dimm_slot.c
@@ -0,0 +1,22 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <commonlib/helpers.h>
+#include <soc/dimm_slot.h>
+
+static const struct dimm_slot_config dimm_slot_config_table[] = {
+	/* socket, channel, dimm, dev_locator, bank_locator, asset_tag */
+	{0, 0, 0, "CPU0_DIMM_A", "BANK 0", "CPU0_DIMM_A_AssetTag"},
+	{0, 1, 0, "CPU0_DIMM_B", "BANK 1", "CPU0_DIMM_B_AssetTag"},
+	{0, 2, 0, "CPU0_DIMM_C", "BANK 2", "CPU0_DIMM_C_AssetTag"},
+	{0, 3, 0, "CPU0_DIMM_D", "BANK 3", "CPU0_DIMM_D_AssetTag"},
+	{0, 4, 0, "CPU0_DIMM_E", "BANK 4", "CPU0_DIMM_E_AssetTag"},
+	{0, 5, 0, "CPU0_DIMM_F", "BANK 5", "CPU0_DIMM_F_AssetTag"},
+	{0, 6, 0, "CPU0_DIMM_G", "BANK 6", "CPU0_DIMM_G_AssetTag"},
+	{0, 7, 0, "CPU0_DIMM_H", "BANK 7", "CPU0_DIMM_H_AssetTag"},
+};
+
+const struct dimm_slot_config *get_dimm_slot_config_table(int *size)
+{
+	*size = ARRAY_SIZE(dimm_slot_config_table);
+	return dimm_slot_config_table;
+}
diff --git a/src/mainboard/mitaccomputing/sc513g6/config/iio.c b/src/mainboard/mitaccomputing/sc513g6/config/iio.c
new file mode 100644
index 0000000000..0b3d92800f
--- /dev/null
+++ b/src/mainboard/mitaccomputing/sc513g6/config/iio.c
@@ -0,0 +1,105 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <soc/iio.h>
+
+static const struct iio_pe_config iio_config_table[] = {
+	{_IIO_PE_CFG_STRUCT(0x0, PE0, CB_IIO_BIFURCATE_x16xxxxx, PE_TYPE_PCIE) {
+		/* _IIO_PORT_CFG_STRUCT_BASIC(sltpls, sltplv, psn) */
+		_IIO_PORT_CFG_STRUCT_BASIC_X16(0x0, 0x4B, 0x1),
+		_IIO_PORT_CFG_STRUCT_DISABLED,
+		_IIO_PORT_CFG_STRUCT_DISABLED,
+		_IIO_PORT_CFG_STRUCT_DISABLED,
+		_IIO_PORT_CFG_STRUCT_DISABLED,
+		_IIO_PORT_CFG_STRUCT_DISABLED,
+		_IIO_PORT_CFG_STRUCT_DISABLED,
+		_IIO_PORT_CFG_STRUCT_DISABLED,
+	}},
+
+	/*
+	 * CB_IIO_BIFURCATE_x8x4x2x2 is first set to indicate how the IIO is bifurcated
+	 * then port settings are listed accordingly. The minimal port elements are x2.
+	 * If an x8 port is enabled, the neighboring 3 x2 port elements needs to be
+	 * disabled.
+	 */
+	{_IIO_PE_CFG_STRUCT(0x0, PE1, CB_IIO_BIFURCATE_x8x4x2x2, PE_TYPE_PCIE) {
+		/* _IIO_PORT_CFG_STRUCT_BASIC(sltpls, sltplv, psn) */
+		_IIO_PORT_CFG_STRUCT_BASIC_X8(0x0, 0x4B, 0x2),
+		_IIO_PORT_CFG_STRUCT_DISABLED,
+		_IIO_PORT_CFG_STRUCT_DISABLED,
+		_IIO_PORT_CFG_STRUCT_DISABLED,
+		_IIO_PORT_CFG_STRUCT_BASIC_X4(0x0, 0x4B, 0x3),
+		_IIO_PORT_CFG_STRUCT_DISABLED,
+		_IIO_PORT_CFG_STRUCT_BASIC_X2(0x0, 0x4B, 0x4),
+		_IIO_PORT_CFG_STRUCT_BASIC_X2(0x0, 0x4B, 0x5),
+	}},
+
+	{_IIO_PE_CFG_STRUCT(0x0, PE2, CB_IIO_BIFURCATE_x16xxxxx, PE_TYPE_PCIE) {
+		/* _IIO_PORT_CFG_STRUCT_BASIC(sltpls, sltplv, psn) */
+		_IIO_PORT_CFG_STRUCT_BASIC_X16(0x0, 0x4B, 0x6),
+		_IIO_PORT_CFG_STRUCT_DISABLED,
+		_IIO_PORT_CFG_STRUCT_DISABLED,
+		_IIO_PORT_CFG_STRUCT_DISABLED,
+		_IIO_PORT_CFG_STRUCT_DISABLED,
+		_IIO_PORT_CFG_STRUCT_DISABLED,
+		_IIO_PORT_CFG_STRUCT_DISABLED,
+		_IIO_PORT_CFG_STRUCT_DISABLED,
+	}},
+
+	{_IIO_PE_CFG_STRUCT(0x0, PE3, CB_IIO_BIFURCATE_x16xxxxx, PE_TYPE_PCIE) {
+		/* _IIO_PORT_CFG_STRUCT_BASIC(sltpls, sltplv, psn) */
+		_IIO_PORT_CFG_STRUCT_BASIC_X16(0x0, 0x4B, 0x7),
+		_IIO_PORT_CFG_STRUCT_DISABLED,
+		_IIO_PORT_CFG_STRUCT_DISABLED,
+		_IIO_PORT_CFG_STRUCT_DISABLED,
+		_IIO_PORT_CFG_STRUCT_DISABLED,
+		_IIO_PORT_CFG_STRUCT_DISABLED,
+		_IIO_PORT_CFG_STRUCT_DISABLED,
+		_IIO_PORT_CFG_STRUCT_DISABLED,
+	}},
+
+	{_IIO_PE_CFG_STRUCT(0x0, PE4, CB_IIO_BIFURCATE_x2x2x2x2x2x2x2x2, PE_TYPE_PCIE) {
+		/* _IIO_PORT_CFG_STRUCT_BASIC(sltpls, sltplv, psn) */
+		_IIO_PORT_CFG_STRUCT_BASIC_X2(0x0, 0x4B, 0x8),
+		_IIO_PORT_CFG_STRUCT_BASIC_X2(0x0, 0x4B, 0x9),
+		_IIO_PORT_CFG_STRUCT_BASIC_X2(0x0, 0x4B, 0xA),
+		_IIO_PORT_CFG_STRUCT_BASIC_X2(0x0, 0x4B, 0xB),
+		_IIO_PORT_CFG_STRUCT_BASIC_X2(0x0, 0x4B, 0xC),
+		_IIO_PORT_CFG_STRUCT_BASIC_X2(0x0, 0x4B, 0xD),
+		_IIO_PORT_CFG_STRUCT_BASIC_X2(0x0, 0x4B, 0xE),
+		_IIO_PORT_CFG_STRUCT_BASIC_X2(0x0, 0x4B, 0xF),
+	}},
+
+	{_IIO_PE_CFG_STRUCT(0x0, PE5, CB_IIO_BIFURCATE_x16xxxxx, PE_TYPE_PCIE) {
+		/* _IIO_PORT_CFG_STRUCT_BASIC(sltpls, sltplv, psn) */
+		_IIO_PORT_CFG_STRUCT_BASIC_X16(0x0, 0x4B, 0x10),
+		_IIO_PORT_CFG_STRUCT_DISABLED,
+		_IIO_PORT_CFG_STRUCT_DISABLED,
+		_IIO_PORT_CFG_STRUCT_DISABLED,
+		_IIO_PORT_CFG_STRUCT_DISABLED,
+		_IIO_PORT_CFG_STRUCT_DISABLED,
+		_IIO_PORT_CFG_STRUCT_DISABLED,
+		_IIO_PORT_CFG_STRUCT_DISABLED,
+	}},
+
+	_IIO_PE_CFG_DISABLED(0x0, PEa),
+	_IIO_PE_CFG_DISABLED(0x0, PEb),
+	_IIO_PE_CFG_DISABLED(0x0, PEc),
+	_IIO_PE_CFG_DISABLED(0x0, PEd),
+
+	_IIO_PE_CFG_DISABLED(0x1, PE0),
+	_IIO_PE_CFG_DISABLED(0x1, PE1),
+	_IIO_PE_CFG_DISABLED(0x1, PE2),
+	_IIO_PE_CFG_DISABLED(0x1, PE3),
+	_IIO_PE_CFG_DISABLED(0x1, PE4),
+	_IIO_PE_CFG_DISABLED(0x1, PE5),
+	_IIO_PE_CFG_DISABLED(0x1, PEa),
+	_IIO_PE_CFG_DISABLED(0x1, PEb),
+	_IIO_PE_CFG_DISABLED(0x1, PEc),
+	_IIO_PE_CFG_DISABLED(0x1, PEd),
+};
+
+const struct iio_pe_config *get_iio_config_table(int *size)
+{
+	*size = ARRAY_SIZE(iio_config_table);
+	return iio_config_table;
+}
diff --git a/src/mainboard/mitaccomputing/sc513g6/devicetree.cb b/src/mainboard/mitaccomputing/sc513g6/devicetree.cb
new file mode 100644
index 0000000000..e79eb10743
--- /dev/null
+++ b/src/mainboard/mitaccomputing/sc513g6/devicetree.cb
@@ -0,0 +1,42 @@
+## SPDX-License-Identifier: GPL-2.0-or-later
+
+chip soc/intel/xeon_sp/gnr
+
+	# configure LPC generic IO decode ranges
+	# 	[bits 31..24: reserved]
+	# 	[bits 23..18: io decode address mask <7..2>]
+	# 	[bits 17..16: reserved]
+	# 	[bits 15..2 : io decode dword aligned address <15..2>]
+	#	[bit 1      : reserved]
+	#	[bit 0      : enabled]
+	register "gen1_dec" = "0x00000CA1" # IPMI KCS
+
+	# configure FSP debug settings
+	register "serial_io_uart_debug_io_base" = CONFIG_TTYS0_BASE
+
+	device domain 0 on
+		device pci 1f.0 on
+			chip superio/common
+				device pnp 2e.0 on
+					chip superio/aspeed/ast2400
+						register "use_espi" = "1"
+						device pnp 2e.2 on # SUART1
+							io 0x60 = 0x3f8 # PNP_IDX_IO0
+							irq 0x70 = 4 # PNP_IDX_IRQ0
+						end
+						device pnp 2e.3 on # SUART2
+							io 0x60 = 0x2f8
+							irq 0x70 = 3
+						end
+
+					end
+				end
+			end
+			chip drivers/ipmi
+				device pnp ca2.0 on end # BMC KCS
+				register "wait_for_bmc" = "1"
+				register "bmc_boot_timeout" = "60"
+			end
+		end
+	end
+end
diff --git a/src/mainboard/mitaccomputing/sc513g6/dsdt.asl b/src/mainboard/mitaccomputing/sc513g6/dsdt.asl
new file mode 100644
index 0000000000..8f84bbe6fd
--- /dev/null
+++ b/src/mainboard/mitaccomputing/sc513g6/dsdt.asl
@@ -0,0 +1,22 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <acpi/acpi.h>
+
+DefinitionBlock(
+	"dsdt.aml",
+	"DSDT",
+	ACPI_DSDT_REV_2,
+	OEM_ID,
+	ACPI_TABLE_CREATOR,
+	0x20110725
+)
+{
+	#include <acpi/dsdt_top.asl>
+	#include <soc/intel/common/block/acpi/acpi/globalnvs.asl>
+	#include <soc/intel/xeon_sp/gnr/acpi/uncore.asl>
+	#include <soc/intel/xeon_sp/gnr/acpi/gpe.asl>
+	#include <southbridge/intel/common/acpi/sleepstates.asl>
+	#include <commonlib/include/commonlib/console/post_codes.h>
+	#include <arch/x86/acpi/post.asl>
+	#include <arch/x86/acpi/debug.asl>
+}
diff --git a/src/mainboard/mitaccomputing/sc513g6/ramstage.c b/src/mainboard/mitaccomputing/sc513g6/ramstage.c
new file mode 100644
index 0000000000..25d12e07c7
--- /dev/null
+++ b/src/mainboard/mitaccomputing/sc513g6/ramstage.c
@@ -0,0 +1,58 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <smbios.h>
+#include <soc/dimm_slot.h>
+#include <soc/ramstage.h>
+
+void mainboard_silicon_init_params(FSPS_UPD *params)
+{
+
+}
+
+/*
+ * TODO: SMBIOS info in src/lib/smbios_defaults.c could be overridden based on needs
+ */
+smbios_wakeup_type smbios_system_wakeup_type(void)
+{
+	return SMBIOS_WAKEUP_TYPE_POWER_SWITCH;
+}
+
+u8 smbios_mainboard_feature_flags(void)
+{
+	return SMBIOS_FEATURE_FLAGS_HOSTING_BOARD | SMBIOS_FEATURE_FLAGS_REPLACEABLE;
+}
+
+smbios_enclosure_type smbios_mainboard_enclosure_type(void)
+{
+	return SMBIOS_ENCLOSURE_RACK_MOUNT_CHASSIS;
+}
+
+void smbios_fill_dimm_locator(const struct dimm_info *dimm, struct smbios_type17 *t)
+{
+	int size;
+	const struct dimm_slot_config *dimm_slot_config_table = get_dimm_slot_config_table(&size);
+
+	for (int i = 0; i < size; i++) {
+		if (DIMM_SLOT_EQUAL(dimm_slot_config_table[i],
+		    dimm->soc_num, dimm->channel_num, dimm->dimm_num)) {
+			const char *locator = dimm_slot_config_table[i].dev_locator;
+			t->device_locator = smbios_add_string(t->eos, locator);
+			locator = dimm_slot_config_table[i].bank_locator;
+			t->bank_locator = smbios_add_string(t->eos, locator);
+		}
+	}
+}
+
+void smbios_fill_dimm_asset_tag(const struct dimm_info *dimm, struct smbios_type17 *t)
+{
+	int size;
+	const struct dimm_slot_config *dimm_slot_config_table = get_dimm_slot_config_table(&size);
+
+	for (int i = 0; i < size; i++) {
+		if (DIMM_SLOT_EQUAL(dimm_slot_config_table[i],
+		    dimm->soc_num, dimm->channel_num, dimm->dimm_num)) {
+			const char *asset_tag = dimm_slot_config_table[i].asset_tag;
+			t->asset_tag = smbios_add_string(t->eos, asset_tag);
+		}
+	}
+}
diff --git a/src/mainboard/mitaccomputing/sc513g6/romstage.c b/src/mainboard/mitaccomputing/sc513g6/romstage.c
new file mode 100644
index 0000000000..7e0bbd8a1b
--- /dev/null
+++ b/src/mainboard/mitaccomputing/sc513g6/romstage.c
@@ -0,0 +1,57 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <console/console.h>
+#include <drivers/ipmi/ipmi_if.h>
+#include <drivers/ocp/include/vpd.h>
+#include <drivers/vpd/vpd.h>
+#include <fmap_config.h>
+#include <device/device.h>
+#include <soc/ddr.h>
+#include <soc/dimm_slot.h>
+#include <soc/iio.h>
+#include <soc/romstage.h>
+#include <static.h>
+
+#include "chip.h"
+
+void mainboard_memory_init_params(FSPM_UPD *mupd)
+{
+	FSP_M_CONFIG *m_cfg = &mupd->FspmConfig;
+
+	/* FSP log outputs */
+	const config_t *config = config_of_soc();
+	m_cfg->SerialIoUartDebugIoBase = config->serial_io_uart_debug_io_base;
+	m_cfg->SerialIoUartDebugEnable = get_bool_from_vpd(FSP_LOG, FSP_LOG_DEFAULT);
+	m_cfg->DebugPrintLevel = config->debug_print_level;
+	m_cfg->serialDebugMsgLvl = get_int_from_vpd_range(FSP_MEM_LOG_LEVEL,
+		FSP_MEM_LOG_LEVEL_DEFAULT, 0, 4);
+
+	/* Early connect BMC, e.g. to query configuration parameters */
+	if (ipmi_premem_init(CONFIG_BMC_KCS_BASE, 0) == CB_SUCCESS)
+		printk(BIOS_INFO, "IPMI at 0x%04x initialized successfully\n",
+			CONFIG_BMC_KCS_BASE);
+
+	/* Set BIOS region UPD, otherwise MTRR might set incorrectly during TempRamExit API */
+	m_cfg->BiosRegionBase = FMAP_SECTION_SI_BIOS_START;
+	m_cfg->BiosRegionSize = FMAP_SECTION_SI_BIOS_SIZE;
+	printk(BIOS_INFO, "BiosRegionBase is set to %x\n", mupd->FspmConfig.BiosRegionBase);
+	printk(BIOS_INFO, "BiosRegionSize is set to %x\n", mupd->FspmConfig.BiosRegionSize);
+
+	/* IIO init */
+	int size;
+	const struct iio_pe_config *iio_config_table = get_iio_config_table(&size);
+	soc_config_iio_pe_ports(mupd, iio_config_table, size);
+}
+
+bool mainboard_dimm_slot_exists(uint8_t socket, uint8_t channel, uint8_t dimm)
+{
+	int size;
+	const struct dimm_slot_config *dimm_slot_config_table = get_dimm_slot_config_table(&size);
+
+	for (int i = 0; i < size; i++) {
+		if (DIMM_SLOT_EQUAL(dimm_slot_config_table[i], socket, channel, dimm))
+			return true;
+	}
+
+	return false;
+}

From ace18dea15a55763426c2e663d8271fe720342f6 Mon Sep 17 00:00:00 2001
From: Schumi Chu <schumi.chu@mitaccomputing.com>
Date: Thu, 8 May 2025 13:59:20 +0800
Subject: [PATCH 1280/3886] mainboard: Add 2S Intel Birch Stream MiTAC
 Computing R520G6SB
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

The R520G6SB server represents the next generation of the M50FCP2UR
Intel Server System, delivering cutting-edge performance and
versatility tailored for demanding data center and enterprise
workloads. Designed as a 2U dual-socket (2S) Birch Stream SP server
system, it integrates advanced features to meet demanding computing,
networking, and AI-driven application requirements.

Tested:
 - USB: Front Panel 2 USB ports and 1 USB port on DCSCM
 - PCIe: J1_MXIO_SLOT1 ~ J1_MXIO_SLOT5 (with PCIe SATA controller)
 - M.2: M2_CN1, M2_CN2
 - Mini Display Port
 - Flash firmware from BMC's redfish interface (Out-of-band)

Build with Linux payload and Intel proprietary FSP.
Installed with dual Intel® Xeon® 6756E, one Micron 64GB DDR5
RDIMM 4800 and boots to Ubuntu 22.04.5 LTS (6.8.0-57-generic).

Change-Id: I0590c82c9763bd07348bd86b134007ea4ed71d7a
Signed-off-by: Schumi Chu <schumi.chu@mitaccomputing.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87574
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 .../builder/config.mitaccomputing.r520g6sb    |  54 ++++++
 src/mainboard/mitaccomputing/r520g6sb/Kconfig |  38 ++++
 .../mitaccomputing/r520g6sb/Kconfig.name      |   4 +
 .../mitaccomputing/r520g6sb/Makefile.mk       |   8 +
 .../mitaccomputing/r520g6sb/board.fmd         |  12 ++
 .../mitaccomputing/r520g6sb/board_info.txt    |   6 +
 .../mitaccomputing/r520g6sb/bootblock.c       |  25 +++
 .../r520g6sb/config/dimm_slot.c               |  46 +++++
 .../mitaccomputing/r520g6sb/config/iio.c      | 171 ++++++++++++++++++
 .../mitaccomputing/r520g6sb/devicetree.cb     |  42 +++++
 .../mitaccomputing/r520g6sb/dsdt.asl          |  22 +++
 .../mitaccomputing/r520g6sb/ramstage.c        |  58 ++++++
 .../mitaccomputing/r520g6sb/romstage.c        |  57 ++++++
 13 files changed, 543 insertions(+)
 create mode 100644 configs/builder/config.mitaccomputing.r520g6sb
 create mode 100644 src/mainboard/mitaccomputing/r520g6sb/Kconfig
 create mode 100644 src/mainboard/mitaccomputing/r520g6sb/Kconfig.name
 create mode 100644 src/mainboard/mitaccomputing/r520g6sb/Makefile.mk
 create mode 100644 src/mainboard/mitaccomputing/r520g6sb/board.fmd
 create mode 100644 src/mainboard/mitaccomputing/r520g6sb/board_info.txt
 create mode 100644 src/mainboard/mitaccomputing/r520g6sb/bootblock.c
 create mode 100644 src/mainboard/mitaccomputing/r520g6sb/config/dimm_slot.c
 create mode 100644 src/mainboard/mitaccomputing/r520g6sb/config/iio.c
 create mode 100644 src/mainboard/mitaccomputing/r520g6sb/devicetree.cb
 create mode 100644 src/mainboard/mitaccomputing/r520g6sb/dsdt.asl
 create mode 100644 src/mainboard/mitaccomputing/r520g6sb/ramstage.c
 create mode 100644 src/mainboard/mitaccomputing/r520g6sb/romstage.c

diff --git a/configs/builder/config.mitaccomputing.r520g6sb b/configs/builder/config.mitaccomputing.r520g6sb
new file mode 100644
index 0000000000..cf1f9402c0
--- /dev/null
+++ b/configs/builder/config.mitaccomputing.r520g6sb
@@ -0,0 +1,54 @@
+# Type this in coreboot root directory to get a working .config:
+#   make defconfig KBUILD_DEFCONFIG=configs/builder/config.mitaccomputing.sc513g6
+
+#
+# [RO] Board Configurations
+#
+CONFIG_VENDOR_MITAC_COMPUTING=y
+CONFIG_BOARD_MITAC_COMPUTING_R520G6SB=y
+
+CONFIG_HAVE_CONFIGURABLE_RAMSTAGE=y
+CONFIG_CONFIGURABLE_RAMSTAGE=y
+
+CONFIG_NO_GFX_INIT=y
+
+CONFIG_HAVE_IFD_BIN=y
+CONFIG_HAVE_PBP_BIN=n
+CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION=y
+CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y
+CONFIG_ADD_FSP_BINARIES=y
+CONFIG_PAYLOAD_LINUX=y
+
+CONFIG_UART_FOR_CONSOLE=0
+CONFIG_CONSOLE_SERIAL_115200=y
+
+CONFIG_COREBOOT_ROMSIZE_KB_65536=y
+
+#
+# [RW] IFWI Ingredients
+#
+CONFIG_IFD_BIN_PATH="site-local/r520g6sb/descriptor.bin"
+CONFIG_PBP_BIN_PATH=""
+CONFIG_CPU_UCODE_BINARIES="site-local/r520g6sb/ucode.mcb"
+CONFIG_FSP_T_FILE="site-local/r520g6sb/Server_T.fd"
+CONFIG_FSP_M_FILE="site-local/r520g6sb/Server_M.fd"
+CONFIG_FSP_S_FILE="site-local/r520g6sb/Server_S.fd"
+CONFIG_FSP_HEADER_PATH="src/vendorcode/intel/fsp/fsp2_0/graniterapids/sp/"
+
+CONFIG_PAYLOAD_FILE="site-local/r520g6sb/bzImage"
+CONFIG_LINUX_COMMAND_LINE="loglevel=7 earlyprintk=serial,ttyS0,115200 console=ttyS0,115200"
+
+#
+# [RW] Debug Settings
+#
+CONFIG_CONSOLE_POST=y
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8=y
+
+CONFIG_VERIFY_HOBS=y
+CONFIG_DISPLAY_MTRRS=y
+
+CONFIG_DISPLAY_FSP_CALLS_AND_STATUS=y
+CONFIG_DISPLAY_FSP_HEADER=y
+
+CONFIG_HAVE_DEBUG_GPIO=y
+CONFIG_DEBUG_GPIO=y
diff --git a/src/mainboard/mitaccomputing/r520g6sb/Kconfig b/src/mainboard/mitaccomputing/r520g6sb/Kconfig
new file mode 100644
index 0000000000..c88c310c61
--- /dev/null
+++ b/src/mainboard/mitaccomputing/r520g6sb/Kconfig
@@ -0,0 +1,38 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
+if BOARD_MITAC_COMPUTING_R520G6SB
+
+config BOARD_SPECIFIC_OPTIONS
+	def_bool y
+	select BOARD_ROMSIZE_KB_65536
+	select SOC_INTEL_GRANITERAPIDS
+	select SUPERIO_ASPEED_AST2400
+	select CONSOLE_OVERRIDE_LOGLEVEL
+	select HAVE_ACPI_TABLES
+	select IPMI_KCS
+	select IPMI_KCS_ROMSTAGE
+	select VPD
+	select OCP_VPD
+	select MEMORY_MAPPED_TPM
+
+config CARDBUS_PLUGIN_SUPPORT
+	bool
+	default n
+
+config MAINBOARD_DIR
+	string
+	default "mitaccomputing/r520g6sb"
+
+config MAINBOARD_PART_NUMBER
+	string
+	default "R520G6SB"
+
+config FMDFILE
+	string
+	default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/board.fmd"
+
+config DIMM_MAX
+	int
+	default 32
+
+endif
diff --git a/src/mainboard/mitaccomputing/r520g6sb/Kconfig.name b/src/mainboard/mitaccomputing/r520g6sb/Kconfig.name
new file mode 100644
index 0000000000..6838e60f8b
--- /dev/null
+++ b/src/mainboard/mitaccomputing/r520g6sb/Kconfig.name
@@ -0,0 +1,4 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
+config BOARD_MITAC_COMPUTING_R520G6SB
+	bool "R520G6SB"
diff --git a/src/mainboard/mitaccomputing/r520g6sb/Makefile.mk b/src/mainboard/mitaccomputing/r520g6sb/Makefile.mk
new file mode 100644
index 0000000000..cfff6d3851
--- /dev/null
+++ b/src/mainboard/mitaccomputing/r520g6sb/Makefile.mk
@@ -0,0 +1,8 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
+bootblock-y += bootblock.c
+romstage-y += romstage.c
+romstage-y += config/dimm_slot.c
+romstage-y += config/iio.c
+ramstage-y += config/dimm_slot.c
+ramstage-y += ramstage.c
diff --git a/src/mainboard/mitaccomputing/r520g6sb/board.fmd b/src/mainboard/mitaccomputing/r520g6sb/board.fmd
new file mode 100644
index 0000000000..d5a34a2b04
--- /dev/null
+++ b/src/mainboard/mitaccomputing/r520g6sb/board.fmd
@@ -0,0 +1,12 @@
+FLASH 64M {
+	SI_ALL 48M {
+		SI_DESC@0x0 0x1000
+	}
+	SI_BIOS 16M {
+		RW_MRC_CACHE 0x10000
+		FMAP 0x800
+		RW_VPD(PRESERVE) 0x4000
+		RO_VPD(PRESERVE) 0x4000
+		COREBOOT(CBFS)
+	}
+}
diff --git a/src/mainboard/mitaccomputing/r520g6sb/board_info.txt b/src/mainboard/mitaccomputing/r520g6sb/board_info.txt
new file mode 100644
index 0000000000..c7d4148a56
--- /dev/null
+++ b/src/mainboard/mitaccomputing/r520g6sb/board_info.txt
@@ -0,0 +1,6 @@
+Vendor name: MiTAC Computing
+Board name: R520G6SB
+Category: eval
+ROM protocol: SPI
+ROM socketed: y
+Flashrom support: y
diff --git a/src/mainboard/mitaccomputing/r520g6sb/bootblock.c b/src/mainboard/mitaccomputing/r520g6sb/bootblock.c
new file mode 100644
index 0000000000..4b2406048a
--- /dev/null
+++ b/src/mainboard/mitaccomputing/r520g6sb/bootblock.c
@@ -0,0 +1,25 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <bootblock_common.h>
+#include <console/console.h>
+#include <intelblocks/lpc_lib.h>
+#include <soc/intel/common/block/lpc/lpc_def.h>
+#include <superio/aspeed/ast2400/ast2400.h>
+#include <superio/aspeed/common/aspeed.h>
+
+#define ASPEED_SIO_PORT 0x2E
+
+void bootblock_mainboard_early_init(void)
+{
+	/* Enable eSPI decoding for com1 (0x3f8), com2 (0x2f8) and superio (0x2e) */
+	lpc_io_setup_comm_a_b();
+	lpc_enable_fixed_io_ranges(LPC_IOE_SUPERIO_2E_2F);
+
+	if (CONFIG_UART_FOR_CONSOLE == 0 || CONFIG_UART_FOR_CONSOLE == 1) {
+		/* Set up Super I/O com1 or com2 */
+		const pnp_devfn_t serial_dev = PNP_DEV(ASPEED_SIO_PORT, AST2400_SUART1);
+		aspeed_enable_serial(serial_dev, CONFIG_TTYS0_BASE);
+	} else {
+		die("COMs other than COM1/COM2 not supported\n");
+	}
+}
diff --git a/src/mainboard/mitaccomputing/r520g6sb/config/dimm_slot.c b/src/mainboard/mitaccomputing/r520g6sb/config/dimm_slot.c
new file mode 100644
index 0000000000..1e8a4123ae
--- /dev/null
+++ b/src/mainboard/mitaccomputing/r520g6sb/config/dimm_slot.c
@@ -0,0 +1,46 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <commonlib/helpers.h>
+#include <soc/dimm_slot.h>
+
+static const struct dimm_slot_config dimm_slot_config_table[] = {
+	/* socket, channel, dimm, dev_locator, bank_locator, asset_tag */
+	{0, 0, 0, "CPU0_DIMM_A1", "BANK 0", "CPU0_DIMM_A1_AssetTag"},
+	{0, 0, 1, "CPU0_DIMM_A2", "BANK 1", "CPU0_DIMM_A2_AssetTag"},
+	{0, 1, 0, "CPU0_DIMM_B1", "BANK 2", "CPU0_DIMM_B1_AssetTag"},
+	{0, 1, 1, "CPU0_DIMM_B2", "BANK 3", "CPU0_DIMM_B2_AssetTag"},
+	{0, 2, 0, "CPU0_DIMM_C1", "BANK 4", "CPU0_DIMM_C1_AssetTag"},
+	{0, 2, 1, "CPU0_DIMM_C2", "BANK 5", "CPU0_DIMM_C2_AssetTag"},
+	{0, 3, 0, "CPU0_DIMM_D1", "BANK 6", "CPU0_DIMM_D1_AssetTag"},
+	{0, 3, 1, "CPU0_DIMM_D2", "BANK 7", "CPU0_DIMM_D2_AssetTag"},
+	{0, 4, 0, "CPU0_DIMM_E1", "BANK 8", "CPU0_DIMM_E1_AssetTag"},
+	{0, 4, 1, "CPU0_DIMM_E2", "BANK 9", "CPU0_DIMM_E2_AssetTag"},
+	{0, 5, 0, "CPU0_DIMM_F1", "BANK 10", "CPU0_DIMM_F1_AssetTag"},
+	{0, 5, 1, "CPU0_DIMM_F2", "BANK 11", "CPU0_DIMM_F2_AssetTag"},
+	{0, 6, 0, "CPU0_DIMM_G1", "BANK 12", "CPU0_DIMM_G1_AssetTag"},
+	{0, 6, 1, "CPU0_DIMM_G2", "BANK 13", "CPU0_DIMM_G2_AssetTag"},
+	{0, 7, 0, "CPU0_DIMM_H1", "BANK 14", "CPU0_DIMM_H1_AssetTag"},
+	{0, 7, 1, "CPU0_DIMM_H2", "BANK 15", "CPU0_DIMM_H2_AssetTag"},
+	{1, 0, 0, "CPU1_DIMM_A1", "BANK 16", "CPU1_DIMM_A1_AssetTag"},
+	{1, 0, 1, "CPU1_DIMM_A2", "BANK 17", "CPU1_DIMM_A2_AssetTag"},
+	{1, 1, 0, "CPU1_DIMM_B1", "BANK 18", "CPU1_DIMM_B1_AssetTag"},
+	{1, 1, 1, "CPU1_DIMM_B2", "BANK 19", "CPU1_DIMM_B2_AssetTag"},
+	{1, 2, 0, "CPU1_DIMM_C1", "BANK 20", "CPU1_DIMM_C1_AssetTag"},
+	{1, 2, 1, "CPU1_DIMM_C2", "BANK 21", "CPU1_DIMM_C2_AssetTag"},
+	{1, 3, 0, "CPU1_DIMM_D1", "BANK 22", "CPU1_DIMM_D1_AssetTag"},
+	{1, 3, 1, "CPU1_DIMM_D2", "BANK 23", "CPU1_DIMM_D2_AssetTag"},
+	{1, 4, 0, "CPU1_DIMM_E1", "BANK 24", "CPU1_DIMM_E1_AssetTag"},
+	{1, 4, 1, "CPU1_DIMM_E2", "BANK 25", "CPU1_DIMM_E2_AssetTag"},
+	{1, 5, 0, "CPU1_DIMM_F1", "BANK 26", "CPU1_DIMM_F1_AssetTag"},
+	{1, 5, 1, "CPU1_DIMM_F2", "BANK 27", "CPU1_DIMM_F2_AssetTag"},
+	{1, 6, 0, "CPU1_DIMM_G1", "BANK 28", "CPU1_DIMM_G1_AssetTag"},
+	{1, 6, 1, "CPU1_DIMM_G2", "BANK 29", "CPU1_DIMM_G2_AssetTag"},
+	{1, 7, 0, "CPU1_DIMM_H1", "BANK 30", "CPU1_DIMM_H1_AssetTag"},
+	{1, 7, 1, "CPU1_DIMM_H2", "BANK 31", "CPU1_DIMM_H2_AssetTag"},
+};
+
+const struct dimm_slot_config *get_dimm_slot_config_table(int *size)
+{
+	*size = ARRAY_SIZE(dimm_slot_config_table);
+	return dimm_slot_config_table;
+}
diff --git a/src/mainboard/mitaccomputing/r520g6sb/config/iio.c b/src/mainboard/mitaccomputing/r520g6sb/config/iio.c
new file mode 100644
index 0000000000..2e2b28bfe4
--- /dev/null
+++ b/src/mainboard/mitaccomputing/r520g6sb/config/iio.c
@@ -0,0 +1,171 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <soc/iio.h>
+
+static const struct iio_pe_config iio_config_table[] = {
+	{_IIO_PE_CFG_STRUCT(0x0, PE0, CB_IIO_BIFURCATE_x16xxxxx, PE_TYPE_PCIE) {
+		/* _IIO_PORT_CFG_STRUCT_BASIC(sltpls, sltplv, psn) */
+		_IIO_PORT_CFG_STRUCT_BASIC_X16(0x0, 0x4B, 0x1),
+		_IIO_PORT_CFG_STRUCT_DISABLED,
+		_IIO_PORT_CFG_STRUCT_DISABLED,
+		_IIO_PORT_CFG_STRUCT_DISABLED,
+		_IIO_PORT_CFG_STRUCT_DISABLED,
+		_IIO_PORT_CFG_STRUCT_DISABLED,
+		_IIO_PORT_CFG_STRUCT_DISABLED,
+		_IIO_PORT_CFG_STRUCT_DISABLED,
+	}},
+
+	/*
+	 * CB_IIO_BIFURCATE_x8x2x2x2x2 is first set to indicate how the IIO is bifurcated
+	 * then port settings are listed accordingly. The minimal port elements are x2.
+	 * If an x8 port is enabled, the neighboring 3 x2 port elements needs to be
+	 * disabled.
+	 */
+	{_IIO_PE_CFG_STRUCT(0x0, PE1, CB_IIO_BIFURCATE_x8x2x2x2x2, PE_TYPE_PCIE) {
+		/* _IIO_PORT_CFG_STRUCT_BASIC(sltpls, sltplv, psn) */
+		_IIO_PORT_CFG_STRUCT_BASIC_X8(0x0, 0x4B, 0x2),
+		_IIO_PORT_CFG_STRUCT_DISABLED,
+		_IIO_PORT_CFG_STRUCT_DISABLED,
+		_IIO_PORT_CFG_STRUCT_DISABLED,
+		_IIO_PORT_CFG_STRUCT_BASIC_X2(0x0, 0x4B, 0x3),
+		_IIO_PORT_CFG_STRUCT_BASIC_X2(0x0, 0x4B, 0x4),
+		_IIO_PORT_CFG_STRUCT_BASIC_X2(0x0, 0x4B, 0x5),
+		_IIO_PORT_CFG_STRUCT_BASIC_X2(0x0, 0x4B, 0x6),
+	}},
+
+	{_IIO_PE_CFG_STRUCT(0x0, PE2, CB_IIO_BIFURCATE_x16xxxxx, PE_TYPE_PCIE) {
+		/* _IIO_PORT_CFG_STRUCT_BASIC(sltpls, sltplv, psn) */
+		_IIO_PORT_CFG_STRUCT_BASIC_X16(0x0, 0x4B, 0x7),
+		_IIO_PORT_CFG_STRUCT_DISABLED,
+		_IIO_PORT_CFG_STRUCT_DISABLED,
+		_IIO_PORT_CFG_STRUCT_DISABLED,
+		_IIO_PORT_CFG_STRUCT_DISABLED,
+		_IIO_PORT_CFG_STRUCT_DISABLED,
+		_IIO_PORT_CFG_STRUCT_DISABLED,
+		_IIO_PORT_CFG_STRUCT_DISABLED,
+	}},
+
+	{_IIO_PE_CFG_STRUCT(0x0, PE3, CB_IIO_BIFURCATE_x16xxxxx, PE_TYPE_PCIE) {
+		/* _IIO_PORT_CFG_STRUCT_BASIC(sltpls, sltplv, psn) */
+		_IIO_PORT_CFG_STRUCT_BASIC_X16(0x0, 0x4B, 0x8),
+		_IIO_PORT_CFG_STRUCT_DISABLED,
+		_IIO_PORT_CFG_STRUCT_DISABLED,
+		_IIO_PORT_CFG_STRUCT_DISABLED,
+		_IIO_PORT_CFG_STRUCT_DISABLED,
+		_IIO_PORT_CFG_STRUCT_DISABLED,
+		_IIO_PORT_CFG_STRUCT_DISABLED,
+		_IIO_PORT_CFG_STRUCT_DISABLED,
+	}},
+
+	{_IIO_PE_CFG_STRUCT(0x0, PE4, CB_IIO_BIFURCATE_x8xxx8xx, PE_TYPE_PCIE) {
+		/* _IIO_PORT_CFG_STRUCT_BASIC(sltpls, sltplv, psn) */
+		_IIO_PORT_CFG_STRUCT_BASIC_X8(0x0, 0x4B, 0x9),
+		_IIO_PORT_CFG_STRUCT_DISABLED,
+		_IIO_PORT_CFG_STRUCT_DISABLED,
+		_IIO_PORT_CFG_STRUCT_DISABLED,
+		_IIO_PORT_CFG_STRUCT_BASIC_X8(0x0, 0x4B, 0xA),
+		_IIO_PORT_CFG_STRUCT_DISABLED,
+		_IIO_PORT_CFG_STRUCT_DISABLED,
+		_IIO_PORT_CFG_STRUCT_DISABLED,
+	}},
+
+	{_IIO_PE_CFG_STRUCT(0x0, PE5, CB_IIO_BIFURCATE_x8xxx8xx, PE_TYPE_PCIE) {
+		/* _IIO_PORT_CFG_STRUCT_BASIC(sltpls, sltplv, psn) */
+		_IIO_PORT_CFG_STRUCT_BASIC_X8(0x0, 0x4B, 0xB),
+		_IIO_PORT_CFG_STRUCT_DISABLED,
+		_IIO_PORT_CFG_STRUCT_DISABLED,
+		_IIO_PORT_CFG_STRUCT_DISABLED,
+		_IIO_PORT_CFG_STRUCT_BASIC_X8(0x0, 0x4B, 0xC),
+		_IIO_PORT_CFG_STRUCT_DISABLED,
+		_IIO_PORT_CFG_STRUCT_DISABLED,
+		_IIO_PORT_CFG_STRUCT_DISABLED,
+	}},
+
+	_IIO_PE_CFG_DISABLED(0x0, PEa),
+	_IIO_PE_CFG_DISABLED(0x0, PEb),
+	_IIO_PE_CFG_DISABLED(0x0, PEc),
+	_IIO_PE_CFG_DISABLED(0x0, PEd),
+
+	{_IIO_PE_CFG_STRUCT(0x1, PE0, CB_IIO_BIFURCATE_x16xxxxx, PE_TYPE_PCIE) {
+		/* _IIO_PORT_CFG_STRUCT_BASIC(sltpls, sltplv, psn) */
+		_IIO_PORT_CFG_STRUCT_BASIC_X16(0x0, 0x4B, 0x1),
+		_IIO_PORT_CFG_STRUCT_DISABLED,
+		_IIO_PORT_CFG_STRUCT_DISABLED,
+		_IIO_PORT_CFG_STRUCT_DISABLED,
+		_IIO_PORT_CFG_STRUCT_DISABLED,
+		_IIO_PORT_CFG_STRUCT_DISABLED,
+		_IIO_PORT_CFG_STRUCT_DISABLED,
+		_IIO_PORT_CFG_STRUCT_DISABLED,
+	}},
+
+	{_IIO_PE_CFG_STRUCT(0x1, PE1, CB_IIO_BIFURCATE_x8xxx8xx, PE_TYPE_PCIE) {
+		/* _IIO_PORT_CFG_STRUCT_BASIC(sltpls, sltplv, psn) */
+		_IIO_PORT_CFG_STRUCT_BASIC_X8(0x0, 0x4B, 0x2),
+		_IIO_PORT_CFG_STRUCT_DISABLED,
+		_IIO_PORT_CFG_STRUCT_DISABLED,
+		_IIO_PORT_CFG_STRUCT_DISABLED,
+		_IIO_PORT_CFG_STRUCT_BASIC_X8(0x0, 0x4B, 0x3),
+		_IIO_PORT_CFG_STRUCT_DISABLED,
+		_IIO_PORT_CFG_STRUCT_DISABLED,
+		_IIO_PORT_CFG_STRUCT_DISABLED,
+	}},
+
+	{_IIO_PE_CFG_STRUCT(0x1, PE2, CB_IIO_BIFURCATE_x16xxxxx, PE_TYPE_PCIE) {
+		/* _IIO_PORT_CFG_STRUCT_BASIC(sltpls, sltplv, psn) */
+		_IIO_PORT_CFG_STRUCT_BASIC_X16(0x0, 0x4B, 0x4),
+		_IIO_PORT_CFG_STRUCT_DISABLED,
+		_IIO_PORT_CFG_STRUCT_DISABLED,
+		_IIO_PORT_CFG_STRUCT_DISABLED,
+		_IIO_PORT_CFG_STRUCT_DISABLED,
+		_IIO_PORT_CFG_STRUCT_DISABLED,
+		_IIO_PORT_CFG_STRUCT_DISABLED,
+		_IIO_PORT_CFG_STRUCT_DISABLED,
+	}},
+
+	{_IIO_PE_CFG_STRUCT(0x1, PE3, CB_IIO_BIFURCATE_x16xxxxx, PE_TYPE_PCIE) {
+		/* _IIO_PORT_CFG_STRUCT_BASIC(sltpls, sltplv, psn) */
+		_IIO_PORT_CFG_STRUCT_BASIC_X16(0x0, 0x4B, 0x5),
+		_IIO_PORT_CFG_STRUCT_DISABLED,
+		_IIO_PORT_CFG_STRUCT_DISABLED,
+		_IIO_PORT_CFG_STRUCT_DISABLED,
+		_IIO_PORT_CFG_STRUCT_DISABLED,
+		_IIO_PORT_CFG_STRUCT_DISABLED,
+		_IIO_PORT_CFG_STRUCT_DISABLED,
+		_IIO_PORT_CFG_STRUCT_DISABLED,
+	}},
+
+	{_IIO_PE_CFG_STRUCT(0x1, PE4, CB_IIO_BIFURCATE_x8xxx8xx, PE_TYPE_PCIE) {
+		/* _IIO_PORT_CFG_STRUCT_BASIC(sltpls, sltplv, psn) */
+		_IIO_PORT_CFG_STRUCT_BASIC_X8(0x0, 0x4B, 0x6),
+		_IIO_PORT_CFG_STRUCT_DISABLED,
+		_IIO_PORT_CFG_STRUCT_DISABLED,
+		_IIO_PORT_CFG_STRUCT_DISABLED,
+		_IIO_PORT_CFG_STRUCT_BASIC_X8(0x0, 0x4B, 0x7),
+		_IIO_PORT_CFG_STRUCT_DISABLED,
+		_IIO_PORT_CFG_STRUCT_DISABLED,
+		_IIO_PORT_CFG_STRUCT_DISABLED,
+	}},
+
+	{_IIO_PE_CFG_STRUCT(0x1, PE5, CB_IIO_BIFURCATE_x8xxx8xx, PE_TYPE_PCIE) {
+		/* _IIO_PORT_CFG_STRUCT_BASIC(sltpls, sltplv, psn) */
+		_IIO_PORT_CFG_STRUCT_BASIC_X8(0x0, 0x4B, 0x8),
+		_IIO_PORT_CFG_STRUCT_DISABLED,
+		_IIO_PORT_CFG_STRUCT_DISABLED,
+		_IIO_PORT_CFG_STRUCT_DISABLED,
+		_IIO_PORT_CFG_STRUCT_BASIC_X8(0x0, 0x4B, 0x9),
+		_IIO_PORT_CFG_STRUCT_DISABLED,
+		_IIO_PORT_CFG_STRUCT_DISABLED,
+		_IIO_PORT_CFG_STRUCT_DISABLED,
+	}},
+
+	_IIO_PE_CFG_DISABLED(0x1, PEa),
+	_IIO_PE_CFG_DISABLED(0x1, PEb),
+	_IIO_PE_CFG_DISABLED(0x1, PEc),
+	_IIO_PE_CFG_DISABLED(0x1, PEd),
+};
+
+const struct iio_pe_config *get_iio_config_table(int *size)
+{
+	*size = ARRAY_SIZE(iio_config_table);
+	return iio_config_table;
+}
diff --git a/src/mainboard/mitaccomputing/r520g6sb/devicetree.cb b/src/mainboard/mitaccomputing/r520g6sb/devicetree.cb
new file mode 100644
index 0000000000..e79eb10743
--- /dev/null
+++ b/src/mainboard/mitaccomputing/r520g6sb/devicetree.cb
@@ -0,0 +1,42 @@
+## SPDX-License-Identifier: GPL-2.0-or-later
+
+chip soc/intel/xeon_sp/gnr
+
+	# configure LPC generic IO decode ranges
+	# 	[bits 31..24: reserved]
+	# 	[bits 23..18: io decode address mask <7..2>]
+	# 	[bits 17..16: reserved]
+	# 	[bits 15..2 : io decode dword aligned address <15..2>]
+	#	[bit 1      : reserved]
+	#	[bit 0      : enabled]
+	register "gen1_dec" = "0x00000CA1" # IPMI KCS
+
+	# configure FSP debug settings
+	register "serial_io_uart_debug_io_base" = CONFIG_TTYS0_BASE
+
+	device domain 0 on
+		device pci 1f.0 on
+			chip superio/common
+				device pnp 2e.0 on
+					chip superio/aspeed/ast2400
+						register "use_espi" = "1"
+						device pnp 2e.2 on # SUART1
+							io 0x60 = 0x3f8 # PNP_IDX_IO0
+							irq 0x70 = 4 # PNP_IDX_IRQ0
+						end
+						device pnp 2e.3 on # SUART2
+							io 0x60 = 0x2f8
+							irq 0x70 = 3
+						end
+
+					end
+				end
+			end
+			chip drivers/ipmi
+				device pnp ca2.0 on end # BMC KCS
+				register "wait_for_bmc" = "1"
+				register "bmc_boot_timeout" = "60"
+			end
+		end
+	end
+end
diff --git a/src/mainboard/mitaccomputing/r520g6sb/dsdt.asl b/src/mainboard/mitaccomputing/r520g6sb/dsdt.asl
new file mode 100644
index 0000000000..8f84bbe6fd
--- /dev/null
+++ b/src/mainboard/mitaccomputing/r520g6sb/dsdt.asl
@@ -0,0 +1,22 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <acpi/acpi.h>
+
+DefinitionBlock(
+	"dsdt.aml",
+	"DSDT",
+	ACPI_DSDT_REV_2,
+	OEM_ID,
+	ACPI_TABLE_CREATOR,
+	0x20110725
+)
+{
+	#include <acpi/dsdt_top.asl>
+	#include <soc/intel/common/block/acpi/acpi/globalnvs.asl>
+	#include <soc/intel/xeon_sp/gnr/acpi/uncore.asl>
+	#include <soc/intel/xeon_sp/gnr/acpi/gpe.asl>
+	#include <southbridge/intel/common/acpi/sleepstates.asl>
+	#include <commonlib/include/commonlib/console/post_codes.h>
+	#include <arch/x86/acpi/post.asl>
+	#include <arch/x86/acpi/debug.asl>
+}
diff --git a/src/mainboard/mitaccomputing/r520g6sb/ramstage.c b/src/mainboard/mitaccomputing/r520g6sb/ramstage.c
new file mode 100644
index 0000000000..25d12e07c7
--- /dev/null
+++ b/src/mainboard/mitaccomputing/r520g6sb/ramstage.c
@@ -0,0 +1,58 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <smbios.h>
+#include <soc/dimm_slot.h>
+#include <soc/ramstage.h>
+
+void mainboard_silicon_init_params(FSPS_UPD *params)
+{
+
+}
+
+/*
+ * TODO: SMBIOS info in src/lib/smbios_defaults.c could be overridden based on needs
+ */
+smbios_wakeup_type smbios_system_wakeup_type(void)
+{
+	return SMBIOS_WAKEUP_TYPE_POWER_SWITCH;
+}
+
+u8 smbios_mainboard_feature_flags(void)
+{
+	return SMBIOS_FEATURE_FLAGS_HOSTING_BOARD | SMBIOS_FEATURE_FLAGS_REPLACEABLE;
+}
+
+smbios_enclosure_type smbios_mainboard_enclosure_type(void)
+{
+	return SMBIOS_ENCLOSURE_RACK_MOUNT_CHASSIS;
+}
+
+void smbios_fill_dimm_locator(const struct dimm_info *dimm, struct smbios_type17 *t)
+{
+	int size;
+	const struct dimm_slot_config *dimm_slot_config_table = get_dimm_slot_config_table(&size);
+
+	for (int i = 0; i < size; i++) {
+		if (DIMM_SLOT_EQUAL(dimm_slot_config_table[i],
+		    dimm->soc_num, dimm->channel_num, dimm->dimm_num)) {
+			const char *locator = dimm_slot_config_table[i].dev_locator;
+			t->device_locator = smbios_add_string(t->eos, locator);
+			locator = dimm_slot_config_table[i].bank_locator;
+			t->bank_locator = smbios_add_string(t->eos, locator);
+		}
+	}
+}
+
+void smbios_fill_dimm_asset_tag(const struct dimm_info *dimm, struct smbios_type17 *t)
+{
+	int size;
+	const struct dimm_slot_config *dimm_slot_config_table = get_dimm_slot_config_table(&size);
+
+	for (int i = 0; i < size; i++) {
+		if (DIMM_SLOT_EQUAL(dimm_slot_config_table[i],
+		    dimm->soc_num, dimm->channel_num, dimm->dimm_num)) {
+			const char *asset_tag = dimm_slot_config_table[i].asset_tag;
+			t->asset_tag = smbios_add_string(t->eos, asset_tag);
+		}
+	}
+}
diff --git a/src/mainboard/mitaccomputing/r520g6sb/romstage.c b/src/mainboard/mitaccomputing/r520g6sb/romstage.c
new file mode 100644
index 0000000000..7e0bbd8a1b
--- /dev/null
+++ b/src/mainboard/mitaccomputing/r520g6sb/romstage.c
@@ -0,0 +1,57 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <console/console.h>
+#include <drivers/ipmi/ipmi_if.h>
+#include <drivers/ocp/include/vpd.h>
+#include <drivers/vpd/vpd.h>
+#include <fmap_config.h>
+#include <device/device.h>
+#include <soc/ddr.h>
+#include <soc/dimm_slot.h>
+#include <soc/iio.h>
+#include <soc/romstage.h>
+#include <static.h>
+
+#include "chip.h"
+
+void mainboard_memory_init_params(FSPM_UPD *mupd)
+{
+	FSP_M_CONFIG *m_cfg = &mupd->FspmConfig;
+
+	/* FSP log outputs */
+	const config_t *config = config_of_soc();
+	m_cfg->SerialIoUartDebugIoBase = config->serial_io_uart_debug_io_base;
+	m_cfg->SerialIoUartDebugEnable = get_bool_from_vpd(FSP_LOG, FSP_LOG_DEFAULT);
+	m_cfg->DebugPrintLevel = config->debug_print_level;
+	m_cfg->serialDebugMsgLvl = get_int_from_vpd_range(FSP_MEM_LOG_LEVEL,
+		FSP_MEM_LOG_LEVEL_DEFAULT, 0, 4);
+
+	/* Early connect BMC, e.g. to query configuration parameters */
+	if (ipmi_premem_init(CONFIG_BMC_KCS_BASE, 0) == CB_SUCCESS)
+		printk(BIOS_INFO, "IPMI at 0x%04x initialized successfully\n",
+			CONFIG_BMC_KCS_BASE);
+
+	/* Set BIOS region UPD, otherwise MTRR might set incorrectly during TempRamExit API */
+	m_cfg->BiosRegionBase = FMAP_SECTION_SI_BIOS_START;
+	m_cfg->BiosRegionSize = FMAP_SECTION_SI_BIOS_SIZE;
+	printk(BIOS_INFO, "BiosRegionBase is set to %x\n", mupd->FspmConfig.BiosRegionBase);
+	printk(BIOS_INFO, "BiosRegionSize is set to %x\n", mupd->FspmConfig.BiosRegionSize);
+
+	/* IIO init */
+	int size;
+	const struct iio_pe_config *iio_config_table = get_iio_config_table(&size);
+	soc_config_iio_pe_ports(mupd, iio_config_table, size);
+}
+
+bool mainboard_dimm_slot_exists(uint8_t socket, uint8_t channel, uint8_t dimm)
+{
+	int size;
+	const struct dimm_slot_config *dimm_slot_config_table = get_dimm_slot_config_table(&size);
+
+	for (int i = 0; i < size; i++) {
+		if (DIMM_SLOT_EQUAL(dimm_slot_config_table[i], socket, channel, dimm))
+			return true;
+	}
+
+	return false;
+}

From 3c23d7b3a9a8dbc4418fe0e503332f6f19572700 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Micha=C5=82=20=C5=BBygowski?= <michal.zygowski@3mdeb.com>
Date: Sun, 10 Sep 2023 14:26:59 +0200
Subject: [PATCH 1281/3886] src/superio/nuvoton: Add HWM initialization code
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Based on similar NCT6687D chip. Obtained the NCT6686D EC Space
Specification datasheet from Nuvoton via email request. Most of
the register definitions come from the EC Space Specification,
the rest has been figured out from MSI MS-7D25 BIOS.

Change-Id: I162f9d4067f0cba1d22d6cb5f98b68987719c038
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87476
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
---
 src/superio/nuvoton/nct6687d/Makefile.mk    |   5 +
 src/superio/nuvoton/nct6687d/chip.h         | 361 ++++++++
 src/superio/nuvoton/nct6687d/nct6687d_ec.c  |  77 ++
 src/superio/nuvoton/nct6687d/nct6687d_ec.h  |  27 +
 src/superio/nuvoton/nct6687d/nct6687d_hwm.c | 960 ++++++++++++++++++++
 src/superio/nuvoton/nct6687d/nct6687d_hwm.h | 922 +++++++++++++++++++
 src/superio/nuvoton/nct6687d/superio.c      |  10 +
 7 files changed, 2362 insertions(+)
 create mode 100644 src/superio/nuvoton/nct6687d/chip.h
 create mode 100644 src/superio/nuvoton/nct6687d/nct6687d_ec.c
 create mode 100644 src/superio/nuvoton/nct6687d/nct6687d_ec.h
 create mode 100644 src/superio/nuvoton/nct6687d/nct6687d_hwm.c
 create mode 100644 src/superio/nuvoton/nct6687d/nct6687d_hwm.h

diff --git a/src/superio/nuvoton/nct6687d/Makefile.mk b/src/superio/nuvoton/nct6687d/Makefile.mk
index d4785f726e..899cf5daec 100644
--- a/src/superio/nuvoton/nct6687d/Makefile.mk
+++ b/src/superio/nuvoton/nct6687d/Makefile.mk
@@ -1,3 +1,8 @@
 # SPDX-License-Identifier: GPL-2.0-or-later
 
+bootblock-$(CONFIG_SUPERIO_NUVOTON_NCT6687D) += nct6687d_ec.c
+romstage-$(CONFIG_SUPERIO_NUVOTON_NCT6687D) += nct6687d_ec.c
+ramstage-$(CONFIG_SUPERIO_NUVOTON_NCT6687D) += nct6687d_ec.c
+
+ramstage-$(CONFIG_SUPERIO_NUVOTON_NCT6687D) += nct6687d_hwm.c
 ramstage-$(CONFIG_SUPERIO_NUVOTON_NCT6687D) += superio.c
diff --git a/src/superio/nuvoton/nct6687d/chip.h b/src/superio/nuvoton/nct6687d/chip.h
new file mode 100644
index 0000000000..44e28b6d19
--- /dev/null
+++ b/src/superio/nuvoton/nct6687d/chip.h
@@ -0,0 +1,361 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#ifndef SUPERIO_NUVOTON_NCT6687D_CHIP_H
+#define SUPERIO_NUVOTON_NCT6687D_CHIP_H
+
+#include <stdbool.h>
+
+#define MAX_TEMP_SPEED_LEVELS 7
+#define MAX_TEMP_SRC 4
+#define MAX_NUM_FANS 10
+#define MAX_NUM_SENSORS 32
+#define MAX_WEIGHT_POINTS 8
+#define MAX_DTS_CTL_POINTS 5
+
+enum nct6687d_sensor_src_select {
+	/* TIN sources */
+	SENSOR_DISABLE = 0x00,
+	SENSOR_LOCAL = 0x01,
+	TD0P_CURRENT_MODE = 0x02,
+	TD1P_CURRENT_MODE = 0x03,
+	TD2P_CURRENT_MODE = 0x04,
+	TD0P_VOLTAGE_MODE = 0x05,
+	TD1P_VOLTAGE_MODE = 0x06,
+	TD2P_VOLTAGE_MODE = 0x07,
+	THERMISTOR14 = 0x08,
+	THERMISTOR15 = 0x09,
+	THERMISTOR16 = 0x0A,
+	THERMISTOR0 = 0x0B,
+	THERMISTOR1 = 0x0C,
+	THERMISTOR2 = 0x0D,
+	THERMISTOR3 = 0x0E,
+	THERMISTOR4 = 0x0F,
+	THERMISTOR5 = 0x10,
+	THERMISTOR6 = 0x11,
+	THERMISTOR7 = 0x12,
+	THERMISTOR8 = 0x13,
+	THERMISTOR9 = 0x14,
+	THERMISTOR10 = 0x15,
+	THERMISTOR11 = 0x16,
+	THERMISTOR12 = 0x17,
+	THERMISTOR13 = 0x18,
+	PECI_AGENT0_DOMAIN0 = 0x20,
+	PECI_AGENT1_DOMAIN0 = 0x21,
+	PECI_AGENT2_DOMAIN0 = 0x22,
+	PECI_AGENT3_DOMAIN0 = 0x23,
+	PECI_AGENT0_DOMAIN1 = 0x24,
+	PECI_AGENT1_DOMAIN1 = 0x25,
+	PECI_AGENT2_DOMAIN1 = 0x26,
+	PECI_AGENT3_DOMAIN1 = 0x27,
+	PECI_DIMM_TMP0 = 0x28,
+	PECI_DIMM_TMP1 = 0x29,
+	PECI_DIMM_TMP2 = 0x2A,
+	PECI_DIMM_TMP3 = 0x2B,
+	PCH_CPU = 0x30,
+	PCH_CHIP = 0x31,
+	PCH_CHIP_CPU_MAX = 0x32,
+	PCH_MCH = 0x33,
+	PCH_DIMM0 = 0x34,
+	PCH_DIMM1 = 0x35,
+	PCH_DIMM2 = 0x36,
+	PCH_DIMM3 = 0x37,
+	SMBUS_THERMAL_SENSOR0 = 0x38,
+	SMBUS_THERMAL_SENSOR1 = 0x39,
+	SMBUS_THERMAL_SENSOR2 = 0x3A,
+	SMBUS_THERMAL_SENSOR3 = 0x3B,
+	SMBUS_THERMAL_SENSOR4 = 0x3C,
+	SMBUS_THERMAL_SENSOR5 = 0x3D,
+	DIMM_THERMAL_SENSOR0 = 0x3E,
+	DIMM_THERMAL_SENSOR1 = 0x3F,
+	DIMM_THERMAL_SENSOR2 = 0x40,
+	DIMM_THERMAL_SENSOR3 = 0x41,
+	AMD_TSI_ADDRESS_0x90 = 0x42,
+	AMD_TSI_ADDRESS_0x92 = 0x43,
+	AMD_TSI_ADDRESS_0x94 = 0x44,
+	AMD_TSI_ADDRESS_0x96 = 0x45,
+	AMD_TSI_ADDRESS_0x98 = 0x46,
+	AMD_TSI_ADDRESS_0x9A = 0x47,
+	AMD_TSI_ADDRESS_0x9C = 0x48,
+	AMD_TSI_ADDRESS_0x9D = 0x49,
+	VIRTUAL_TEMPIN0 = 0x50,
+	VIRTUAL_TEMPIN1 = 0x51,
+	VIRTUAL_TEMPIN2 = 0x52,
+	VIRTUAL_TEMPIN3 = 0x53,
+	VIRTUAL_TEMPIN4 = 0x54,
+	VIRTUAL_TEMPIN5 = 0x55,
+	VIRTUAL_TEMPIN6 = 0x56,
+	VIRTUAL_TEMPIN7 = 0x57,
+	/* VIN sources */
+	VCC = 0x60,
+	VSB = 0x61,
+	AVSB = 0x62,
+	VTT = 0x63,
+	VBAT = 0x64,
+	VREF = 0x65,
+	VIN0 = 0x66,
+	VIN1 = 0x67,
+	VIN2 = 0x68,
+	VIN3 = 0x69,
+	VIN4 = 0x6A,
+	VIN5 = 0x6B,
+	VIN6 = 0x6C,
+	VIN7 = 0x6D,
+	VIN8 = 0x6E,
+	VIN9 = 0x6F,
+	VIN10 = 0x70,
+	VIN11 = 0x71,
+	VIN12 = 0x72,
+	VIN13 = 0x73,
+	VIN14 = 0x74,
+	VIN15 = 0x75,
+	VIN16 = 0x76,
+};
+
+enum nct6687d_peci_speed {
+	PECI_2MHZ = 0,
+	PECI_1200KHZ,
+	PECI_800KHZ,
+	PECI_400KHZ,
+};
+
+enum nct6687d_baud_rate {
+	BAUD_12_5K = 0,
+	BAUD_25K,
+	BAUD_50K,
+	BAUD_100K,
+	BAUD_200K,
+	BAUD_400K,
+	BAUD_800K,
+	BAUD_1200K,
+};
+
+enum nct6687d_fan_mode {
+	FAN_IGNORE = 0,
+	FAN_THERMAL_CRUISE,
+	FAN_SPEED_CRUISE,
+	FAN_SMART_FAN_IV,
+	FAN_PID_CONTROL,
+	FAN_MODE_MANUAL,
+};
+
+enum nct6687d_tach_pwm_sel {
+	TACH_PWM0 = 0,
+	TACH_PWM1,
+	TACH_PWM2,
+	TACH_PWM3,
+	TACH_PWM4,
+	TACH_PWM5,
+	TACH_PWM6,
+	TACH_PWM7,
+	TACH_PWM8,
+	TACH_PWM9,
+	TACH_PWM10,
+	TACH_PWM11,
+	TACH_PWM12,
+	TACH_PWM13,
+	TACH_PWM14,
+	TACH_PWM15,
+	TACH_PWM16,
+	TACH_PWM17,
+	TACH_PWM18,
+	TACH_PWM19,
+	TACH_PWM20,
+	TACH_PWM21,
+	TACH_PWM22,
+	TACH_PWM23,
+};
+
+enum nct6687d_fan_unit_sel {
+	FAN_PWM = 0,
+	FAN_RPM,
+};
+
+enum nct6687d_fast_track_weight {
+	WEIGHT_DIV_1 = 0,
+	WEIGHT_DIV_2,
+	WEIGHT_DIV_4,
+	WEIGHT_DIV_8,
+	WEIGHT_DIV_16,
+	WEIGHT_DIV_32,
+	WEIGHT_DIV_64,
+};
+
+struct nct6687d_pch_smbus_sensor {
+	bool	sensor_en;
+	uint8_t	sensor_idx;
+	bool	report_one_byte;
+	uint8_t port_sel;
+	enum	nct6687d_baud_rate baud_rate;
+	uint8_t	sensor_addr;
+	uint8_t	sensor_cmd;
+};
+
+struct nct6687d_dts_sensor_config {
+	uint8_t ambient_temp[MAX_DTS_CTL_POINTS];
+	uint16_t rpm_start_point[MAX_DTS_CTL_POINTS];
+	uint16_t rpm_end_point[MAX_DTS_CTL_POINTS];
+	uint8_t	temp_start;
+	uint8_t	temp_end;
+	uint16_t max_speed;
+	bool peci_adjust;
+	uint8_t peci_agent_idx;
+};
+
+struct nct6687d_dts2_sensor_config {
+	int8_t	target_margin;
+	uint8_t	target_margin_tolerance;
+	int8_t	t_control;
+	int8_t	t_control_offset;
+	uint16_t step_speed;
+	uint16_t min_speed;
+	/* Unit is 1s */
+	uint8_t delay_time;
+	uint8_t divisor;
+};
+
+struct nct6687d_smart_fan_iv_config {
+	uint8_t temp_src[MAX_TEMP_SRC];
+	uint8_t temp_levels[MAX_TEMP_SPEED_LEVELS];
+	uint16_t speed_levels[MAX_TEMP_SPEED_LEVELS];
+	uint8_t temp_hystheresis;
+	uint8_t temp_cut_off;
+	uint8_t cut_off_delay;
+	/* Time in 100ms units */
+	uint8_t step_up_time;
+	uint8_t step_down_time;
+};
+
+struct nct6687d_manual_fan_config {
+	uint8_t manual_duty;
+};
+
+struct nct6687d_fan_thermal_cruise_config {
+	bool keep_min_fan_output;
+	uint8_t target_temp;
+	uint8_t temp_tolerance;
+	uint8_t initial_value;
+	uint8_t stop_value;
+	/* Time in 100ms units */
+	uint8_t stop_time;
+	uint8_t step_up_time;
+	uint8_t step_down_time;
+};
+
+struct nct6687d_fan_speed_cruise_config {
+	uint16_t target_rpm;
+	uint16_t rpm_tolerance;
+	/* Time in 100ms units */
+	uint8_t step_up_time;
+	uint8_t step_down_time;
+};
+
+struct nct6687d_ambient_floor_fan_config {
+	/* Units is RPM */
+	uint16_t minout_start;
+	uint16_t minout_end;
+	uint16_t minout_max;
+};
+
+struct nct6687d_ambient_floor_config {
+	uint8_t temp_start;
+	uint8_t temp_end;
+};
+
+struct nct6687d_smart_tracking_config {
+	uint8_t rpm_tolerance_low;
+	uint8_t rpm_tolerance_mid;
+	uint8_t rpm_tolerance_high;
+
+	uint16_t speed_boundary_low;
+	uint16_t speed_boundary_high;
+
+	/* Step tracking setting */
+	uint8_t step_up;
+	uint8_t step_down;
+
+	/* Fast tracking settings */
+	uint8_t temp_boundary;
+
+	enum nct6687d_fast_track_weight weight_up_low;
+	enum nct6687d_fast_track_weight weight_up_mid;
+	enum nct6687d_fast_track_weight weight_up_high;
+	enum nct6687d_fast_track_weight weight_down_low;
+	enum nct6687d_fast_track_weight weight_down_mid;
+	enum nct6687d_fast_track_weight weight_down_high;
+
+	uint8_t duty_step_low;
+	uint8_t duty_step_mid;
+	uint8_t duty_step_high;
+
+	/* Markup tracking setting */
+	uint8_t ambient_temp_boundary;
+	uint8_t weight_val;
+};
+
+
+struct nct6687d_fan_config {
+	enum nct6687d_fan_mode mode;
+	enum nct6687d_fan_unit_sel unit_sel;
+	enum nct6687d_tach_pwm_sel fanin_sel;
+	enum nct6687d_tach_pwm_sel fanout_sel;
+
+	struct nct6687d_smart_fan_iv_config smart_fan;
+	struct nct6687d_manual_fan_config manual_fan;
+	struct nct6687d_fan_thermal_cruise_config thermal_cruise_fan;
+	struct nct6687d_fan_speed_cruise_config speed_cruise_fan;
+
+	/* Fan ALG_FUNCTRL */
+	uint8_t fan_alg_weight;
+
+	uint8_t crit_temp;
+	uint8_t crit_temp_tolerance;
+
+	uint8_t temp_err_duty;
+
+	bool dts1_en;
+	bool dts2_en;
+	bool dts_ub_en;
+
+	/* Fan FUN_CTRL */
+	bool smart_tracking_en;
+	bool fast_tracking_en;
+	bool markup_tracking_en;
+
+	bool ambient_floor_en;
+	struct nct6687d_ambient_floor_fan_config amb_floor_fan_cfg;
+
+	uint8_t startup_duty;
+	uint8_t manual_offset;
+	uint8_t min_duty;
+};
+
+struct superio_nuvoton_nct6687d_config {
+	struct nct6687d_fan_config fans[MAX_NUM_FANS];
+	enum nct6687d_sensor_src_select sensors[MAX_NUM_SENSORS];
+
+	enum nct6687d_peci_speed peci_speed;
+
+	struct nct6687d_pch_smbus_sensor smbus_sensor;
+	struct nct6687d_dts_sensor_config dts_sensor;
+	struct nct6687d_dts2_sensor_config dts2_sensor;
+
+	struct nct6687d_ambient_floor_config ambient_floor;
+	struct nct6687d_smart_tracking_config smart_tracking;
+
+	uint8_t fan_default_val;
+};
+
+#define FAN1	fans[0]
+#define FAN2	fans[1]
+#define FAN3	fans[2]
+#define FAN4	fans[3]
+#define FAN5	fans[4]
+#define FAN6	fans[5]
+#define FAN7	fans[6]
+#define FAN8	fans[7]
+#define FAN9	fans[8]
+#define FAN10	fans[9]
+
+void nct6687d_hwm_init(uint16_t hwm_base, const struct superio_nuvoton_nct6687d_config *conf);
+
+#endif /* SUPERIO_NUVOTON_NCT6687D_CHIP_H */
diff --git a/src/superio/nuvoton/nct6687d/nct6687d_ec.c b/src/superio/nuvoton/nct6687d/nct6687d_ec.c
new file mode 100644
index 0000000000..0b25b164b4
--- /dev/null
+++ b/src/superio/nuvoton/nct6687d/nct6687d_ec.c
@@ -0,0 +1,77 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <arch/io.h>
+
+#include "nct6687d_ec.h"
+
+void nct6687d_ec_write_page(uint16_t iobase, uint8_t page, uint8_t index, uint8_t value)
+{
+	/* Need to write 0xff first to set the page */
+	outb(0xff, iobase + EC_PORT0_PAGE);
+	outb(page, iobase + EC_PORT0_PAGE);
+	outb(index, iobase + EC_PORT0_INDEX);
+	outb(value, iobase + EC_PORT0_DATA);
+	/* Need to write 0xff at the end of transaction */
+	outb(0xff, iobase + EC_PORT0_PAGE);
+}
+
+void nct6687d_ec_write_page_ff(uint16_t iobase, uint8_t page, uint8_t index, uint8_t value)
+{
+	/* Need to write 0xff first to set the page */
+	outb(0xff, iobase + EC_PORT0_PAGE);
+	outb(page, iobase + EC_PORT0_PAGE);
+	/* Extra 0xff to the index register */
+	outb(0xff, iobase + EC_PORT0_INDEX);
+	outb(index, iobase + EC_PORT0_INDEX);
+	outb(value, iobase + EC_PORT0_DATA);
+	/* Need to write 0xff at the end of transaction */
+	outb(0xff, iobase + EC_PORT0_PAGE);
+}
+
+void nct6687d_ec_and_or_page(uint16_t iobase, uint8_t page, uint8_t index,
+			     uint8_t and_mask, uint8_t or_mask)
+{
+	uint8_t val;
+	/* Need to write 0xff first to set the page */
+	outb(0xff, iobase + EC_PORT0_PAGE);
+	outb(page, iobase + EC_PORT0_PAGE);
+	outb(index, iobase + EC_PORT0_INDEX);
+	val = inb(iobase + EC_PORT0_DATA);
+	val &= and_mask;
+	val |= or_mask;
+	outb(val, iobase + EC_PORT0_DATA);
+	/* Need to write 0xff at the end of transaction */
+	outb(0xff, iobase + EC_PORT0_PAGE);
+}
+
+void nct6687d_ec_and_or_page_ff(uint16_t iobase, uint8_t page, uint8_t index,
+			     uint8_t and_mask, uint8_t or_mask)
+{
+	uint8_t val;
+	/* Need to write 0xff first to set the page */
+	outb(0xff, iobase + EC_PORT0_PAGE);
+	outb(page, iobase + EC_PORT0_PAGE);
+	/* Extra 0xff to the index register */
+	outb(0xff, iobase + EC_PORT0_INDEX);
+	outb(index, iobase + EC_PORT0_INDEX);
+	val = inb(iobase + EC_PORT0_DATA);
+	val &= and_mask;
+	val |= or_mask;
+	outb(val, iobase + EC_PORT0_DATA);
+	/* Need to write 0xff at the end of transaction */
+	outb(0xff, iobase + EC_PORT0_PAGE);
+}
+
+uint8_t nct6687d_ec_read_page(uint16_t iobase, uint8_t page, uint8_t index)
+{
+	uint8_t value;
+	/* Need to write 0xff first to set the page */
+	outb(0xff, iobase + EC_PORT0_PAGE);
+	outb(page, iobase + EC_PORT0_PAGE);
+	outb(index, iobase + EC_PORT0_INDEX);
+	value = inb(iobase + EC_PORT0_DATA);
+	/* Need to write 0xff at the end of transaction */
+	outb(0xff, iobase + EC_PORT0_PAGE);
+
+	return value;
+}
diff --git a/src/superio/nuvoton/nct6687d/nct6687d_ec.h b/src/superio/nuvoton/nct6687d/nct6687d_ec.h
new file mode 100644
index 0000000000..d32f32c467
--- /dev/null
+++ b/src/superio/nuvoton/nct6687d/nct6687d_ec.h
@@ -0,0 +1,27 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#ifndef SUPERIO_NUVOTON_NCT6687D_EC_H
+#define SUPERIO_NUVOTON_NCT6687D_EC_H
+
+#include <types.h>
+
+/* Offsets in the EC IO base. Port0 for firmware use, Port1 for software use */
+#define EC_PORT0_PAGE 0
+#define EC_PORT0_INDEX 1
+#define EC_PORT0_DATA 2
+#define EC_PORT0_HOST_IF_EVENT 3
+
+#define EC_PORT1_PAGE 4
+#define EC_PORT1_INDEX 5
+#define EC_PORT1_DATA 6
+#define EC_PORT1_HOST_IF_EVENT 7
+
+void nct6687d_ec_write_page(uint16_t iobase, uint8_t page, uint8_t index, uint8_t value);
+void nct6687d_ec_write_page_ff(uint16_t iobase, uint8_t page, uint8_t index, uint8_t value);
+void nct6687d_ec_and_or_page(uint16_t iobase, uint8_t page, uint8_t index,
+			     uint8_t and_mask, uint8_t or_mask);
+void nct6687d_ec_and_or_page_ff(uint16_t iobase, uint8_t page, uint8_t index,
+			     uint8_t and_mask, uint8_t or_mask);
+uint8_t nct6687d_ec_read_page(uint16_t iobase, uint8_t page, uint8_t index);
+
+#endif /* SUPERIO_NUVOTON_NCT6687D_EC_H */
diff --git a/src/superio/nuvoton/nct6687d/nct6687d_hwm.c b/src/superio/nuvoton/nct6687d/nct6687d_hwm.c
new file mode 100644
index 0000000000..e7d80f493d
--- /dev/null
+++ b/src/superio/nuvoton/nct6687d/nct6687d_hwm.c
@@ -0,0 +1,960 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <console/console.h>
+#include <delay.h>
+
+#include "chip.h"
+#include "nct6687d_hwm.h"
+
+uint16_t nct6687d_hwm_base = 0;
+
+static bool check_cond(const bool cond, const char *error)
+{
+	if (!cond)
+		printk(BIOS_ERR, "NCT6687D: %s\n", error);
+
+	return !cond;
+}
+
+static inline void print_status_bit(const char *status, const bool cond)
+{
+	printk(BIOS_DEBUG, "\t%-45s: %s\n", status, cond ? "yes" : "no");
+}
+
+static void print_fan_engine_status(void)
+{
+	uint8_t fan_eng_sts = hwm_reg_read(FAN_ENGINE_STS_REG);
+
+	printk(BIOS_DEBUG, "NCT6687D: Fan Engine Status:\n");
+	print_status_bit("PECI configuration adjusted", fan_eng_sts & FAN_PECI_CFG_ADJUSTED);
+	print_status_bit("All enabled fan channels processed",
+			 fan_eng_sts & FAN_UNFINISHED_FLAG);
+	print_status_bit("Configuration phase", fan_eng_sts & FAN_CFG_PHASE);
+	print_status_bit("Configuration invalid", fan_eng_sts & FAN_CFG_INVALID);
+	print_status_bit("Configuration check done", fan_eng_sts & FAN_CFG_CHECK_DONE);
+	print_status_bit("Configuration locked", fan_eng_sts & FAN_CFG_LOCK);
+	printk(BIOS_DEBUG, "Fans in automatic mode driven by %s register\n",
+	       (fan_eng_sts & FAN_DRIVE_BY_DEFAULT_VAL) ? "DEFAULT_VAL" : "MOD_SEL");
+}
+
+static bool unlock_fan_register_set(void)
+{
+	uint8_t fan_eng_sts;
+	bool done = false;
+	unsigned int i;
+
+	fan_eng_sts = hwm_reg_read(FAN_ENGINE_STS_REG);
+
+	if (!(fan_eng_sts & FAN_CFG_LOCK) && (fan_eng_sts & FAN_CFG_PHASE))
+		return true;
+
+	for (i = 1000; i > 0; i--) {
+		/* Wait until EC exits config phase and config request is clear */
+		if ((hwm_reg_read(FAN_ENGINE_STS_REG) & FAN_CFG_PHASE) == 0 &&
+		    (hwm_reg_read(FAN_CFG_CTRL_REG) & FAN_CFG_REQUEST) == 0) {
+			done = true;
+			break;
+		}
+		mdelay(1);
+	}
+
+	if (!done) {
+		printk(BIOS_WARNING, "Timeout waiting for EC to exit config phase or clear"
+				     "config request\n");
+		print_fan_engine_status();
+		return false;
+	}
+
+	done = false;
+
+	hwm_reg_write(FAN_CFG_CTRL_REG, FAN_CFG_REQUEST);
+
+	for (i = 1000; i > 0; i--) {
+		/* Wait until EC unlock the register set */
+		if ((hwm_reg_read(FAN_ENGINE_STS_REG) & FAN_CFG_LOCK) == 0) {
+			done = true;
+			break;
+		}
+		mdelay(1);
+	}
+
+	if (!done) {
+		printk(BIOS_WARNING, "Timeout waiting for EC to unlock the fan registers\n");
+		print_fan_engine_status();
+		return false;
+	}
+
+	return true;
+}
+
+static void print_last_err(uint8_t error_code)
+{
+	uint8_t debug_level = BIOS_WARNING;
+	uint8_t last_err_code = hwm_reg_read(FAN_LAST_ERROR_CODE_REG);
+
+	if (last_err_code == FAN_NO_ERROR) {
+		printk(BIOS_DEBUG, "No error occurred.\n");
+		return;
+	}
+
+	/* Lower the debug level if it is an error we care about */
+	if (last_err_code == error_code)
+		debug_level = BIOS_ERR;
+
+	switch (last_err_code) {
+	case FAN_ERR_MODE_SELECT:
+		printk(debug_level, "Mode Select invalid configuration\n");
+		break;
+	case FAN_ERR_CRIT_TEMP_PROTECT:
+		printk(debug_level, "Critical Temperature Protection invalid configuration\n");
+		break;
+	case FAN_ERR_ITL_FAN_CONTROL:
+		printk(debug_level, "Intel DTS Sensor invalid configuration\n");
+		break;
+	case FAN_ERR_SMART_TRACKING:
+		printk(debug_level, "Smart Tracking invalid configuration\n");
+		break;
+	case FAN_ERR_THERMAL_CRUISE:
+		printk(debug_level, "Thermal Cruise invalid configuration\n");
+		break;
+	case FAN_ERR_SPEED_CRUISE:
+		printk(debug_level, "Speed Cruise invalid configuration\n");
+		break;
+	case FAN_ERR_SMART_FAN_IV:
+		printk(debug_level, "Smart Fan IV invalid configuration\n");
+		break;
+	case FAN_ERR_PID_CONTROL:
+		printk(debug_level, "PID control invalid configuration\n");
+		break;
+	default:
+		printk(debug_level, "Unknown fan configuration error %02x\n", last_err_code);
+		break;
+	}
+}
+
+static void lock_fan_register_set_and_check(uint8_t error_code)
+{
+	uint8_t fan_eng_sts;
+	bool done = false;
+	unsigned int i;
+
+	fan_eng_sts = hwm_reg_read(FAN_ENGINE_STS_REG);
+
+	if (fan_eng_sts & FAN_CFG_LOCK || !(fan_eng_sts & FAN_CFG_PHASE)) {
+		printk(BIOS_DEBUG, "Fan register set already locked or not in config phase\n");
+		return;
+	}
+
+	hwm_reg_write(FAN_CFG_CTRL_REG, FAN_CFG_DONE);
+
+	for (i = 1000; i > 0; i--) {
+		fan_eng_sts = hwm_reg_read(FAN_ENGINE_STS_REG);
+		/* Wait until EC checks the configuration */
+		if (fan_eng_sts & FAN_CFG_CHECK_DONE) {
+			done = true;
+			break;
+		}
+		mdelay(1);
+	}
+
+	if (!done) {
+		printk(BIOS_WARNING, "Timeout waiting for configuration check done\n");
+		print_fan_engine_status();
+		return;
+	}
+
+	fan_eng_sts = hwm_reg_read(FAN_ENGINE_STS_REG);
+
+	if (fan_eng_sts & FAN_CFG_INVALID) {
+		printk(BIOS_WARNING, "NCT6687D: Configuration error ocurred\n");
+		print_last_err(error_code);
+	}
+
+	if (!(fan_eng_sts & FAN_CFG_LOCK)) {
+		printk(BIOS_WARNING, "NCT6687D: Configuration registers did not lock\n");
+		print_fan_engine_status();
+	}
+}
+
+static void init_pch_smbus_sensor(const struct nct6687d_pch_smbus_sensor *smbus_sensor)
+{
+	if (!smbus_sensor->sensor_addr || !smbus_sensor->sensor_cmd) {
+		printk(BIOS_ERR, "NCT6687D SMBus sensor CMD or ADDR missing!\n");
+		return;
+	}
+
+	/* Enable SMBUS first */
+	hwm_reg_write(SMBUS_MASTER_CFG2_REG, 0x04);
+	hwm_reg_write(SMBUS_MASTER_BAUD_RATE_SEL_REG, SMB_MASTER_BAUD_100K);
+	hwm_reg_set_bits(SMBUS_MASTER_CFG1_REG, SMB_MASTER_EN);
+
+	hwm_reg_and_or(PCH_THERMAL_DATA_CFG_REG, ~PCH_BAUD_SEL_MASK,
+		       smbus_sensor->baud_rate & PCH_BAUD_SEL_MASK);
+	hwm_reg_and_or(PCH_THERMAL_DATA_CFG_REG, ~PCH_PORT_SEL_MASK,
+		       PCH_THERMAL_PORT(smbus_sensor->port_sel) & PCH_PORT_SEL_MASK);
+
+	if (smbus_sensor->report_one_byte)
+		hwm_reg_set_bits(PCH_THERMAL_DATA_CFG_REG, PCH_ONE_BYTE_REPORT);
+	else
+		hwm_reg_and_or(PCH_THERMAL_DATA_CFG_REG, ~PCH_ONE_BYTE_REPORT & 0xff, 0);
+
+
+	hwm_reg_write(PCH_DEVICE_ADDR_REG, smbus_sensor->sensor_addr);
+	hwm_reg_write(PCH_THERMAL_CMD_REG, smbus_sensor->sensor_cmd);
+}
+
+static void init_sensors(const struct superio_nuvoton_nct6687d_config *conf)
+{
+	unsigned int i;
+	bool peci_en = false;
+	const enum nct6687d_sensor_src_select *sensors = conf->sensors;
+
+	if (!unlock_fan_register_set()) {
+		printk(BIOS_ERR, "NCT6687D failed to unlock registers, "
+				 "skipping sensors programming\n");
+		return;
+	}
+
+	printk(BIOS_DEBUG, "NCT6687D programming sensors\n");
+	/* Start monitoring */
+	hwm_reg_set_bits(HWM_CONFIG_REG, HWM_EN);
+
+	for (i = 0; i < MAX_NUM_SENSORS; i++) {
+		hwm_reg_write(SENSOR_CFG_REG(i), sensors[i] & SENSOR_SRC_SEL_MASK);
+
+		if (sensors[i] >= PECI_AGENT0_DOMAIN0 &&
+		    sensors[i] <= PECI_AGENT3_DOMAIN1) {
+			hwm_reg_and_or(PECI_AGENT_EN_REG, ~PECI_AGENT_EN_MASK,
+				       PECI_AGENT_EN(sensors[i] & 0x3));
+			peci_en = true;
+		}
+
+		/* Only PCH SMBus sensor supported right now */
+		if (sensors[i] >= PCH_CPU && sensors[i] <= PCH_DIMM3 &&
+		    i == conf->smbus_sensor.sensor_idx &&
+		    conf->smbus_sensor.sensor_en) {
+			init_pch_smbus_sensor(&conf->smbus_sensor);
+		}
+	}
+
+	if (peci_en) {
+		hwm_reg_and_or(PECI_CFG_REG, PECI_SPEED_SEL_MASK,
+			       conf->peci_speed & PECI_SPEED_SEL_MASK);
+		hwm_reg_set_bits(PECI_CFG_REG, PECI_AGENT_INIT | PECI_EN);
+	}
+
+	lock_fan_register_set_and_check(FAN_NO_ERROR);
+}
+
+static bool intel_dts_sensor_control_point_check(const struct nct6687d_dts_sensor_config *dts,
+						 unsigned int i)
+{
+	bool failure = false;
+
+	failure |= check_cond(dts->ambient_temp[i] <= 127,
+			      "DTS Sensor Ambient Temperature Levels should be <= 127");
+
+	if (i < MAX_DTS_CTL_POINTS - 1) {
+		failure |= check_cond(dts->ambient_temp[i + 1] >= dts->ambient_temp[i],
+				      "DTS Sensor next Ambient Temperature Level must be "
+				      "higher or equal to previous Ambient Temperature Level");
+		failure |= check_cond(dts->rpm_start_point[i + 1] >  dts->rpm_start_point[i],
+				      "DTS Sensor next RPM Start Point must be higher than "
+				      "previous RPM Start Point");
+		failure |= check_cond(dts->rpm_end_point[i + 1] >  dts->rpm_end_point[i],
+				      "DTS Sensor next RPM End Point must be higher than "
+				      "previous RPM End Point");
+	}
+
+	failure |= check_cond(dts->rpm_end_point[i] > dts->rpm_start_point[i],
+			      "DTS Sensor RPM End Point must be higher than corresponding RPM "
+			      "Start Point");
+
+	return failure;
+}
+
+static bool intel_dts_sensor_config_check(const struct nct6687d_dts_sensor_config *dts)
+{
+	bool failure = false;
+	unsigned int i;
+
+	failure |= check_cond(dts->temp_end > dts->temp_start,
+			      "DTS Sensor Temperature End Point should be > "
+			      "Temperature End Point");
+	failure |= check_cond(dts->temp_start <= 127,
+			      "DTS Sensor Temperature Start Point should be <= 127");
+	failure |= check_cond(dts->temp_end <= 127,
+			      "DTS Sensor Temperature End Point should be <= 127");
+
+	if (dts->peci_adjust) {
+		failure |= check_cond(dts->peci_agent_idx < 8,
+				      "DTS Sensor PECI Agent Index should be < 8");
+	}
+
+	for (i = 0; i < MAX_DTS_CTL_POINTS; i++)
+		failure |= intel_dts_sensor_control_point_check(dts, i);
+
+	return failure;
+}
+
+static void init_intel_dts_sensor(const struct nct6687d_dts_sensor_config *dts)
+{
+	static int init_once = 0;
+	unsigned int i;
+
+	if (init_once)
+		return;
+
+	if (intel_dts_sensor_config_check(dts)) {
+		printk(BIOS_ERR, "NCT6687D DTS Sensor invalid config, "
+				 "skipping sensor programming\n");
+		return;
+	}
+
+	printk(BIOS_DEBUG, "NCT6687D programming DTS sensor\n");
+
+	hwm_reg_write(ITL_TEMP_START_POINT_REG, dts->temp_start);
+	hwm_reg_write(ITL_TEMP_END_POINT_REG, dts->temp_end);
+
+	hwm_reg_write(ITL_RPM_MAX_SPEED_HI_REG, dts->max_speed >> 8);
+	hwm_reg_write(ITL_RPM_MAX_SPEED_LO_REG, dts->max_speed & 0xff);
+
+	for (i = 0; i < MAX_DTS_CTL_POINTS; i++) {
+		hwm_reg_write(ITL_AMB_TEMP_START_POINT_REG(i), dts->ambient_temp[i]);
+		hwm_reg_write(ITL_RPM_START_POINT_HI_REG(i), dts->rpm_start_point[i] >> 8);
+		hwm_reg_write(ITL_RPM_START_POINT_LO_REG(i), dts->rpm_start_point[i] & 0xff);
+		hwm_reg_write(ITL_RPM_END_POINT_HI_REG(i), dts->rpm_end_point[i] >> 8);
+		hwm_reg_write(ITL_RPM_END_POINT_LO_REG(i), dts->rpm_end_point[i] & 0xff);
+	}
+
+	if (dts->peci_adjust) {
+		hwm_reg_and_or(ITL_DTS_CFG_REG, ~ITL_DTS_PECI_AGENT_IDX_SEL_MASK,
+			       dts->peci_agent_idx & ITL_DTS_PECI_AGENT_IDX_SEL_MASK);
+		hwm_reg_set_bits(ITL_DTS_CFG_REG, ITL_DTS_PECI_CFG_ADJUSTMENT);
+	}
+
+	init_once = 1;
+}
+
+static void init_intel_dts2_sensor(const struct nct6687d_dts2_sensor_config *dts2)
+{
+	static int init_once = 0;
+
+	if (init_once)
+		return;
+
+	printk(BIOS_DEBUG, "NCT6687D programming DTS2 sensor\n");
+
+	hwm_reg_write(DTS2_TARGET_MARGIN_REG, (uint8_t)dts2->target_margin);
+	hwm_reg_write(DTS2_TCONTROL_REG, (uint8_t)dts2->t_control);
+	hwm_reg_write(DTS2_TCONTROL_OFFSET_REG, (uint8_t)dts2->t_control_offset);
+	hwm_reg_write(DTS2_TARGET_TOLERANCE_REG, dts2->target_margin_tolerance);
+
+	hwm_reg_write(DTS2_STEP_SPEED_HI_REG, dts2->step_speed >> 8);
+	hwm_reg_write(DTS2_STEP_SPEED_LO_REG, dts2->step_speed & 0xff);
+	hwm_reg_write(DTS2_MIN_SPEED_HI_REG, dts2->min_speed >> 8);
+	hwm_reg_write(DTS2_MIN_SPEED_LO_REG, dts2->min_speed & 0xff);
+
+	hwm_reg_write(DTS2_DELAY_TIME_COUNTER_REG, dts2->delay_time);
+	hwm_reg_write(DTS2_DIVISOR_REG, dts2->divisor);
+
+	init_once = 1;
+}
+
+static void lock_sensor_config(void)
+{
+	if (!unlock_fan_register_set()) {
+		printk(BIOS_ERR, "NCT6687D failed to unlock registers, "
+				 "skipping misc fan config programming\n");
+		return;
+	}
+	hwm_reg_set_bits(HWM_CONFIG_REG, LOCK_SENSOR_CFG);
+	lock_fan_register_set_and_check(FAN_NO_ERROR);
+}
+
+static void init_ambient_floor_alg(const struct superio_nuvoton_nct6687d_config *conf,
+				   unsigned int idx)
+{
+	static int init_once = 0;
+	const struct nct6687d_ambient_floor_fan_config *amb_floor_fan;
+	const struct nct6687d_ambient_floor_config *amb_floor_cfg = &conf->ambient_floor;
+
+	amb_floor_fan = &conf->fans[idx - 1].amb_floor_fan_cfg;
+
+	printk(BIOS_DEBUG, "NCT6687D initializing ambient floor algorithm\n");
+
+	if (!init_once) {
+		hwm_reg_write(AMBIENT_FLOOR_TEMP_START_POINT_REG, amb_floor_cfg->temp_start);
+		hwm_reg_write(AMBIENT_FLOOR_TEMP_END_POINT_REG, amb_floor_cfg->temp_end);
+		init_once = 1;
+	}
+
+	hwm_reg_write(FAN_AMB_FLOOR_MIN_OUT_START_REG(idx),
+		      FAN_AMB_FLOOR_RPM_TO_REG(amb_floor_fan->minout_start));
+	hwm_reg_write(FAN_AMB_FLOOR_MIN_OUT_END_REG(idx),
+		      FAN_AMB_FLOOR_RPM_TO_REG(amb_floor_fan->minout_end));
+	hwm_reg_write(FAN_AMB_FLOOR_MAX_OUT_REG(idx),
+		      FAN_AMB_FLOOR_RPM_TO_REG(amb_floor_fan->minout_max));
+}
+
+static void init_smart_tracking_alg(const struct superio_nuvoton_nct6687d_config *conf,
+				    unsigned int idx)
+{
+	static int init_once = 0;
+	const struct nct6687d_fan_config *fan = &conf->fans[idx - 1];
+	const struct nct6687d_smart_tracking_config *smart_track = &conf->smart_tracking;
+
+	printk(BIOS_DEBUG, "NCT6687D initializing smart tracking algorithm\n");
+
+	if (!init_once) {
+		hwm_reg_write(FAN_LOW_RPM_SPEED_BOUNDARY_HI_REG,
+			      smart_track->speed_boundary_low >> 8);
+		hwm_reg_write(FAN_LOW_RPM_SPEED_BOUNDARY_LO_REG,
+			      smart_track->speed_boundary_low & 0xff);
+		hwm_reg_write(FAN_HIGH_RPM_SPEED_BOUNDARY_HI_REG,
+			      smart_track->speed_boundary_high >> 8);
+		hwm_reg_write(FAN_HIGH_RPM_SPEED_BOUNDARY_LO_REG,
+			      smart_track->speed_boundary_high & 0xff);
+		hwm_reg_write(FAN_LOW_RPM_TOLERANCE_REG, smart_track->rpm_tolerance_low);
+		hwm_reg_write(FAN_MID_RPM_TOLERANCE_REG, smart_track->rpm_tolerance_mid);
+		hwm_reg_write(FAN_HIGH_RPM_TOLERANCE_REG, smart_track->rpm_tolerance_high);
+
+		hwm_reg_write(FAN_TRACKING_STEP_REG, ((smart_track->step_up & 0xf) << 4) |
+						     (smart_track->step_down & 0xf));
+
+		hwm_reg_write(FAN_FAST_TRACK_TEMP_BOUNDARY_REG, smart_track->temp_boundary);
+
+		hwm_reg_write(FAN_LOW_RPM_FAST_TRACK_WEIGHT_REG,
+			      ((smart_track->weight_up_low & 7) << 4) |
+			      (smart_track->weight_down_low & 7));
+		hwm_reg_write(FAN_MID_RPM_FAST_TRACK_WEIGHT_REG,
+			      ((smart_track->weight_up_mid & 7) << 4) |
+			      (smart_track->weight_down_mid & 7));
+		hwm_reg_write(FAN_HIGH_RPM_FAST_TRACK_WEIGHT_REG,
+			      ((smart_track->weight_up_high & 7) << 4) |
+			      (smart_track->weight_down_high & 7));
+
+		hwm_reg_write(FAN_LOW_RPM_FAST_TRACK_DUTY_STEP_REG,
+			      smart_track->duty_step_low & 0xf);
+		hwm_reg_write(FAN_MID_RPM_FAST_TRACK_DUTY_STEP_REG,
+			      smart_track->duty_step_mid & 0xf);
+		hwm_reg_write(FAN_HIGH_RPM_FAST_TRACK_DUTY_STEP_REG,
+			      smart_track->duty_step_high & 0xf);
+
+		hwm_reg_write(FAN_MARKUP_TRACK_AMB_TEMP_BOUNDARY_REG,
+			      smart_track->ambient_temp_boundary);
+
+		hwm_reg_write(FAN_MARKUP_TRACK_WEIGHT_REG, smart_track->weight_val & 7);
+
+		init_once = 1;
+	}
+
+	if (fan->fast_tracking_en)
+		hwm_reg_set_bits(FAN_FUNCTION_CTRL(idx), FAN_FUN_FAST_TRACK_EN);
+
+
+	if (fan->markup_tracking_en)
+		hwm_reg_set_bits(FAN_FUNCTION_CTRL(idx), FAN_FUN_MARKUP_TRACK_EN);
+}
+
+static void misc_fan_config(const struct superio_nuvoton_nct6687d_config *conf,
+			    unsigned int idx)
+{
+	const struct nct6687d_fan_config *fan = &conf->fans[idx - 1];
+
+	if (!unlock_fan_register_set()) {
+		printk(BIOS_ERR, "NCT6687D failed to unlock registers, "
+				 "skipping misc fan config programming\n");
+		return;
+	}
+
+	if (fan->fan_alg_weight) {
+		printk(BIOS_DEBUG, "Programming algorithm weight for FAN%d\n", idx);
+		hwm_reg_and_or(FAN_ALG_ENGINE_WEIGHT_VAL_REG(idx),
+			       ~FAN_ALG_ENGINE_WEIGHT_MASK(idx),
+			       (fan->fan_alg_weight & 0xf) <<
+					FAN_ALG_ENGINE_WEIGHT_SHIFT(idx));
+		hwm_reg_set_bits(FAN_ALG_ENGINE_WEIGHT_EN_REG(idx),
+				 FAN_ALG_ENGINE_WEIGHT_CHANNEL_EN(idx));
+		hwm_reg_set_bits(FAN_ALG_FUNCTRL_REG(idx), FAN_ALG_FUNCTRL_ALG_EN);
+	}
+
+	if (fan->crit_temp) {
+		if (!check_cond(fan->crit_temp >= fan->crit_temp_tolerance,
+				"Fan Critical Temperature should be >= "
+				"Critical Temperature Tolerance")) {
+			printk(BIOS_DEBUG, "Enabling critical temperature for FAN%d\n", idx);
+			hwm_reg_write(FAN_CRIT_TEMP_CFG_REG(idx), fan->crit_temp & 0x7f);
+			if (fan->crit_temp_tolerance)
+				hwm_reg_write(FAN_CRIT_TEMP_TOLERANCE_REG(idx),
+					      fan->crit_temp_tolerance & 0xf);
+
+			hwm_reg_set_bits(FAN_ALG_FUNCTRL_REG(idx),
+					 FAN_ALG_FUNCTRL_CRIT_TEMP_EN);
+		}
+	}
+
+	if (fan->temp_err_duty) {
+		hwm_reg_write(FAN_TEMP_ERR_DUTY_VAL_REG(idx), fan->temp_err_duty);
+		hwm_reg_set_bits(FAN_ALG_FUNCTRL_REG(idx), FAN_ALG_FUNCTRL_TEMP_ERR);
+	}
+
+	if (fan->dts1_en && fan->dts2_en) {
+		printk(BIOS_ERR, "DTS and DTS2 sensors can't coexist!\n");
+		printk(BIOS_ERR, "Skipping DTS configuration\n");
+	} else {
+		if (fan->dts1_en) {
+			init_intel_dts_sensor(&conf->dts_sensor);
+			hwm_reg_set_bits(FAN_ALG_FUNCTRL_REG(idx), FAN_ALG_FUNCTRL_DTS1_EN);
+		}
+
+		if (fan->dts2_en) {
+			init_intel_dts2_sensor(&conf->dts2_sensor);
+			hwm_reg_set_bits(FAN_ALG_FUNCTRL_REG(idx), FAN_ALG_FUNCTRL_DTS2_EN);
+		}
+	}
+
+	if (fan->dts_ub_en)
+		hwm_reg_set_bits(FAN_ALG_FUNCTRL_REG(idx), FAN_ALG_FUNCTRL_DTS_UB_EN);
+
+
+	if (fan->smart_tracking_en) {
+		init_smart_tracking_alg(conf, idx);
+		hwm_reg_set_bits(FAN_FUNCTION_CTRL(idx), FAN_FUN_SMART_TRACK_EN);
+	}
+
+	if (conf->fan_default_val && conf->fan_default_val <= 100)
+		hwm_reg_write(FAN_DEFAULT_VAL_REG,
+			      FAN_PWM_PERCENT_TO_HEX(conf->fan_default_val));
+
+	/* Some registers for functionalities below are missing for fan 9 and 10 */
+	if (idx > 8) {
+		lock_fan_register_set_and_check(FAN_NO_ERROR);
+		return;
+	}
+
+	if (fan->ambient_floor_en) {
+		init_ambient_floor_alg(conf, idx);
+		hwm_reg_set_bits(FAN_FUNCTION_CTRL(idx), FAN_FUN_AMBIENT_FLOOR_EN);
+	}
+
+	if (fan->startup_duty && fan->startup_duty <= 100) {
+		hwm_reg_write(FAN_STARTUP_DUTY_REG(idx),
+			      FAN_PWM_PERCENT_TO_HEX(fan->startup_duty));
+		hwm_reg_set_bits(FAN_FUNCTION_CTRL(idx), FAN_FUN_STARTUP_EN);
+	}
+
+	if (fan->manual_offset) {
+		hwm_reg_write(FAN_MANUAL_OFFSET_REG(idx), fan->manual_offset);
+		hwm_reg_set_bits(FAN_FUNCTION_CTRL(idx), FAN_FUN_MANUAL_OFFSET_EN);
+	}
+
+	if (fan->min_duty && fan->min_duty <= 100) {
+		hwm_reg_write(FAN_MIN_DUTY_REG(idx), FAN_PWM_PERCENT_TO_HEX(fan->min_duty));
+		hwm_reg_set_bits(FAN_FUNCTION_CTRL(idx), FAN_FUN_MINDUTY_EN);
+	}
+
+	lock_fan_register_set_and_check(FAN_NO_ERROR);
+}
+
+static void set_fan_pins_and_mode(const struct nct6687d_fan_config *fan, unsigned int idx)
+{
+	enum nct6687d_fan_mode mode = fan->mode;
+
+	/* FAN_IGNORE takes the mapping of manual mode to detect uninitialized fans */
+	if (mode == FAN_MODE_MANUAL)
+		mode = 0;
+
+	hwm_reg_and_or(FAN_MODE_SEL_REG(idx), ~FAN_MODE_SEL_MASK, mode & FAN_MODE_SEL_MASK);
+	hwm_reg_and_or(FANIN_CFG_REG(idx), ~FANIN_PIN_SEL_MASK,
+		       fan->fanin_sel & FANIN_PIN_SEL_MASK);
+	hwm_reg_set_bits(FANIN_CFG_REG(idx), FANIN_MONITOR_EN);
+
+	hwm_reg_and_or(FANOUT_CFG_REG(idx), ~FANOUT_PIN_SEL_MASK,
+		       fan->fanout_sel & FANOUT_PIN_SEL_MASK);
+	hwm_reg_set_bits(FANOUT_CFG_REG(idx), FANOUT_EN);
+}
+
+static bool smart_fan_level_check(const struct nct6687d_fan_config *fan,
+				  const struct nct6687d_smart_fan_iv_config *s_fan,
+				  int i)
+{
+	bool failure = false;
+
+	failure |= check_cond(s_fan->temp_levels[i] <= 127,
+			      "Smart Fan IV Temperature Levels should be <= 127");
+	if (i < MAX_TEMP_SPEED_LEVELS - 1) {
+		failure |= check_cond(s_fan->temp_levels[i + 1] >= s_fan->temp_levels[i],
+				      "Smart Fan IV next Temperature Level must be higher"
+				      " or equal to previous Temperature Level");
+		failure |= check_cond(s_fan->speed_levels[i + 1] >=  s_fan->speed_levels[i],
+				      "Smart Fan IV next Speed Level must be higher or "
+				      "equal to previous Speed Level");
+	}
+
+	if (fan->unit_sel == FAN_PWM) {
+		failure |= check_cond(s_fan->speed_levels[i] <= 100,
+				      "Smart Fan IV PWM Speed Levels should be <= 100");
+	} else if (fan->unit_sel == FAN_RPM) {
+		failure |= check_cond(s_fan->speed_levels[i] <= 0x3fff,
+				      "Smart Fan IV RPM Speed Levels should be"
+				      "<= 16383 RPM");
+	} else {
+		failure |= check_cond(false, "Smart Fan IV invalid Fan Unit Selection");
+	}
+
+	return failure;
+
+}
+
+static bool smart_fan_config_check(const struct nct6687d_fan_config *fan,
+				   const struct nct6687d_smart_fan_iv_config *s_fan)
+{
+	bool failure = false;
+	unsigned int i;
+
+	for (i = 0; i < MAX_TEMP_SPEED_LEVELS; i++)
+		failure |= smart_fan_level_check(fan, s_fan, i);
+
+	failure |= check_cond(s_fan->temp_levels[0] >= s_fan->temp_cut_off,
+			      "Smart Fan IV Temperature Level 1 should be >= "
+			      "Temperature Cut Off");
+	failure |= check_cond(s_fan->temp_levels[0] >=
+			      (s_fan->temp_cut_off + s_fan->temp_hystheresis),
+			      "Smart Fan IV Temperature Level 1 should be >= "
+			      "Temperature Cut Off + Temperature Hysteresis");
+
+	return failure;
+}
+
+static void init_smart_fan(const struct superio_nuvoton_nct6687d_config *conf, unsigned int idx)
+{
+	unsigned int i;
+	const struct nct6687d_fan_config *fan = &conf->fans[idx - 1];
+	const struct nct6687d_smart_fan_iv_config *sfan = &fan->smart_fan;
+
+	if (smart_fan_config_check(fan, sfan)) {
+		printk(BIOS_ERR, "NCT6687D Smart Fan IV invalid config, "
+				 "skipping fan programming\n");
+		return;
+	}
+
+	if (!unlock_fan_register_set()) {
+		printk(BIOS_ERR, "NCT6687D failed to unlock registers, "
+				 "skipping Smart Fan IV config programming\n");
+		return;
+	}
+
+	set_fan_pins_and_mode(fan, idx);
+
+	if (fan->unit_sel == FAN_PWM)
+		hwm_reg_and_or(FAN_FUNCTION_CTRL(idx), ~FAN_FUN_UNIT_RPM & 0xff,
+			       FAN_FUN_UNIT_PWM_DUTY);
+	else if (fan->unit_sel == FAN_RPM)
+		hwm_reg_set_bits(FAN_FUNCTION_CTRL(idx), FAN_FUN_UNIT_RPM);
+
+	/* Registers start from MSB */
+	for (i = 0; i < MAX_TEMP_SRC; i++) {
+		hwm_reg_write(FAN_MTZ_DCS_DATA_REG(MAX_TEMP_SRC - 1 - i, idx),
+			      sfan->temp_src[i]);
+	}
+
+	for (i = 0; i < MAX_TEMP_SPEED_LEVELS; i++) {
+		if (sfan->temp_levels[i])
+			hwm_reg_write(FAN_SF4_TEMP_LVL_REG(idx, i),
+				      sfan->temp_levels[i]);
+		if (sfan->speed_levels[i]) {
+			if (fan->unit_sel == FAN_PWM) {
+				hwm_reg_write(FAN_SF4_PWM_RPM_LVL_HI_REG(idx, i), 0);
+				hwm_reg_write(FAN_SF4_PWM_RPM_LVL_LO_REG(idx, i),
+					      FAN_PWM_PERCENT_TO_HEX(sfan->speed_levels[i]));
+			}
+
+			if (fan->unit_sel == FAN_RPM) {
+				hwm_reg_write(FAN_SF4_PWM_RPM_LVL_HI_REG(idx, i),
+					      sfan->speed_levels[i] >> 8);
+				hwm_reg_write(FAN_SF4_PWM_RPM_LVL_LO_REG(idx, i),
+					      sfan->speed_levels[i] & 0xff);
+			}
+		}
+	}
+
+	hwm_reg_write(FAN_SF4_TEMP_OFF_HYSTHERESIS_REG(idx), sfan->temp_hystheresis);
+	hwm_reg_write(FAN_SF4_TEMP_CUT_OFF_REG(idx), sfan->temp_cut_off);
+	hwm_reg_write(FAN_SF4_TEMP_OFF_DELAY_REG(idx), sfan->cut_off_delay);
+
+	hwm_reg_write(FAN_STEP_UP_TIME_REG(idx), sfan->step_up_time);
+	hwm_reg_write(FAN_STEP_DOWN_TIME_REG(idx), sfan->step_down_time);
+
+	/* Set fan mode to automatic */
+	hwm_reg_and_or(FAN_MANUAL_EN_REG(idx), ~FAN_MANUAL_EN(idx), 0x00);
+
+	hwm_reg_set_bits(FAN_CHANNEL_EN_REG(idx), FAN_CHANNEL_EN(idx));
+
+	lock_fan_register_set_and_check(FAN_ERR_SMART_FAN_IV);
+
+	misc_fan_config(conf, idx);
+}
+
+static void init_manual_fan(const struct superio_nuvoton_nct6687d_config *conf,
+			    unsigned int idx)
+{
+	const struct nct6687d_fan_config *fan = &conf->fans[idx - 1];
+	const struct nct6687d_manual_fan_config *manual_fan = &fan->manual_fan;
+
+	if (manual_fan->manual_duty || manual_fan->manual_duty > 100) {
+		printk(BIOS_ERR, "NCT6687D: invalid duty cycle for manual fan mode\n");
+		return;
+	}
+
+	if (!unlock_fan_register_set()) {
+		printk(BIOS_ERR, "NCT6687D failed to unlock registers, "
+				 "skipping manual fan config programming\n");
+		return;
+	}
+
+	set_fan_pins_and_mode(fan, idx);
+
+	if (fan->unit_sel == FAN_PWM)
+		hwm_reg_and_or(FAN_FUNCTION_CTRL(idx), ~FAN_FUN_UNIT_RPM & 0xff,
+			       FAN_FUN_UNIT_PWM_DUTY);
+	else if (fan->unit_sel == FAN_RPM)
+		hwm_reg_set_bits(FAN_FUNCTION_CTRL(idx), FAN_FUN_UNIT_RPM);
+
+	hwm_reg_write(FAN_MANUAL_VALUE_REG(idx),
+		      FAN_PWM_PERCENT_TO_HEX(manual_fan->manual_duty));
+
+	hwm_reg_set_bits(FAN_MANUAL_EN_REG(idx), FAN_MANUAL_EN(idx));
+
+	hwm_reg_set_bits(FAN_CHANNEL_EN_REG(idx), FAN_CHANNEL_EN(idx));
+
+	lock_fan_register_set_and_check(FAN_NO_ERROR);
+
+	misc_fan_config(conf, idx);
+}
+
+static bool thermal_cruise_config_check(const struct nct6687d_fan_thermal_cruise_config *tc_fan)
+{
+	bool failure = false;
+
+	failure |= check_cond(tc_fan->step_down_time > 0,
+			      "Thermal Cruise Step-Down Time should be > 0");
+	failure |= check_cond(tc_fan->step_up_time > 0,
+			      "Thermal Cruise Step-Up Time should be > 0");
+	failure |= check_cond(tc_fan->initial_value > tc_fan->stop_value,
+			      "Thermal Cruise Initial value should be > Stop Value");
+	failure |= check_cond(tc_fan->target_temp >= tc_fan->temp_tolerance,
+			      "Thermal Cruise Target Temperature should be"
+			      " >= Temperature Tolerance");
+	if (tc_fan->keep_min_fan_output) {
+		failure |= check_cond(tc_fan->stop_value > 0,
+				      "Thermal Cruise Stop Value should be > 0");
+	} else {
+		failure |= check_cond(tc_fan->stop_time > 0,
+				      "Thermal Cruise Stop Time should be > 0");
+	}
+
+	return failure;
+}
+
+static void init_thermal_cruise_fan(const struct superio_nuvoton_nct6687d_config *conf,
+				    unsigned int idx)
+{
+	const struct nct6687d_fan_config *fan = &conf->fans[idx - 1];
+	const struct nct6687d_fan_thermal_cruise_config *tc_fan = &fan->thermal_cruise_fan;
+
+	if (thermal_cruise_config_check(tc_fan)) {
+		printk(BIOS_ERR, "NCT6687D Thermal Cruise invalid config, "
+				 "skipping fan programming\n");
+		return;
+	}
+
+	if (!unlock_fan_register_set()) {
+		printk(BIOS_ERR, "NCT6687D failed to unlock registers, "
+				 "skipping Thermal Cruise fan config programming\n");
+		return;
+	}
+
+	set_fan_pins_and_mode(fan, idx);
+
+	hwm_reg_write(FAN_TC_TARGET_TEMP_REG(idx),
+		      tc_fan->target_temp & FAN_TC_TARGET_TEMP_MASK);
+
+	if (tc_fan->keep_min_fan_output) {
+		hwm_reg_set_bits(FAN_TC_TARGET_TEMP_REG(idx), FAN_TC_KEEP_MIN_OUTPUT);
+		hwm_reg_write(FAN_TC_STOP_VALUE_REG(idx), tc_fan->stop_value);
+	}
+
+	hwm_reg_write(FAN_TC_TARGET_TEMP_TOLERANCE_REG(idx),
+		      tc_fan->temp_tolerance & FAN_TC_TEMP_TOLERANCE_MASK);
+
+	hwm_reg_write(FAN_INITIAL_VALUE_REG(idx), tc_fan->initial_value);
+
+	hwm_reg_write(FAN_TC_STOP_TIME_REG(idx), tc_fan->stop_time);
+	hwm_reg_write(FAN_TC_STEP_DOWN_TIME_REG(idx), tc_fan->step_up_time);
+	hwm_reg_write(FAN_TC_STEP_UP_TIME_REG(idx), tc_fan->step_down_time);
+
+	/* Set fan mode to automatic */
+	hwm_reg_and_or(FAN_MANUAL_EN_REG(idx), ~FAN_MANUAL_EN(idx), 0);
+
+	hwm_reg_set_bits(FAN_CHANNEL_EN_REG(idx), FAN_CHANNEL_EN(idx));
+
+	lock_fan_register_set_and_check(FAN_ERR_THERMAL_CRUISE);
+
+	misc_fan_config(conf, idx);
+}
+
+static bool speed_cruise_config_check(const struct nct6687d_fan_speed_cruise_config *sc_fan)
+{
+	bool failure = false;
+
+	failure |= check_cond(sc_fan->target_rpm <= 0x3fff,
+			      "Speed Cruise Target RPM should be <= 16838 RPM");
+	failure |= check_cond(sc_fan->target_rpm >= sc_fan->rpm_tolerance,
+			      "Speed Cruise Target RPM should be >= RPM Tolerance");
+	failure |= check_cond(sc_fan->step_down_time > 0,
+			      "Speed Cruise Step-Down Time should be > 0");
+	failure |= check_cond(sc_fan->step_up_time > 0,
+			      "Speed Cruise Step-Up Time should be > 0");
+
+	return failure;
+}
+
+static void init_speed_cruise_fan(const struct superio_nuvoton_nct6687d_config *conf,
+				  unsigned int idx)
+{
+	const struct nct6687d_fan_config *fan = &conf->fans[idx - 1];
+	const struct nct6687d_fan_speed_cruise_config *sc_fan = &fan->speed_cruise_fan;
+
+	if (speed_cruise_config_check(sc_fan)) {
+		printk(BIOS_ERR, "NCT6687D Speed Cruise invalid config, "
+				 "skipping fan programming\n");
+		return;
+	}
+
+	if (!unlock_fan_register_set()) {
+		printk(BIOS_ERR, "NCT6687D failed to unlock registers, "
+				 "skipping Speed Cruise fan config programming\n");
+		return;
+	}
+
+	set_fan_pins_and_mode(fan, idx);
+
+	/* Speed cruise should only enable RPM units */
+	hwm_reg_set_bits(FAN_FUNCTION_CTRL(idx), FAN_FUN_UNIT_RPM);
+
+	hwm_reg_write(FAN_SC_TARGET_RPM_HI_REG(idx), sc_fan->target_rpm >> 8);
+	hwm_reg_write(FAN_SC_TARGET_RPM_LO_REG(idx), sc_fan->target_rpm & 0xff);
+
+	hwm_reg_write(FAN_SC_TARGET_RPM_TOLERANCE_HI_REG(idx), sc_fan->rpm_tolerance >> 8);
+	hwm_reg_write(FAN_SC_TARGET_RPM_TOLERANCE_LO_REG(idx), sc_fan->rpm_tolerance & 0xff);
+
+	hwm_reg_write(FAN_SC_STEP_DOWN_TIME_REG(idx), sc_fan->step_up_time);
+	hwm_reg_write(FAN_SC_STEP_UP_TIME_REG(idx), sc_fan->step_down_time);
+
+	/* Set fan mode to automatic */
+	hwm_reg_and_or(FAN_MANUAL_EN_REG(idx), ~FAN_MANUAL_EN(idx), 0x00);
+
+	hwm_reg_set_bits(FAN_CHANNEL_EN_REG(idx), FAN_CHANNEL_EN(idx));
+
+	lock_fan_register_set_and_check(FAN_ERR_SPEED_CRUISE);
+
+	misc_fan_config(conf, idx);
+};
+
+static void init_one_fan(const struct superio_nuvoton_nct6687d_config *conf, unsigned int idx)
+{
+	const struct nct6687d_fan_config *fan = &conf->fans[idx - 1];
+
+	switch (fan->mode) {
+	case FAN_THERMAL_CRUISE:
+		printk(BIOS_DEBUG, "Initializing Thermal Cruise for FAN%d\n", idx);
+		init_thermal_cruise_fan(conf, idx);
+		break;
+	case FAN_SPEED_CRUISE:
+		printk(BIOS_DEBUG, "Initializing Speed Cruise for FAN%d\n", idx);
+		init_speed_cruise_fan(conf, idx);
+		break;
+	case FAN_SMART_FAN_IV:
+		printk(BIOS_DEBUG, "Initializing Smart FAN IV for FAN%d\n", idx);
+		init_smart_fan(conf, idx);
+		break;
+	case FAN_PID_CONTROL:
+		printk(BIOS_WARNING, "NCT6687D: PID Control fan mode not yet supported\n");
+		break;
+	case FAN_MODE_MANUAL:
+		printk(BIOS_DEBUG, "Initializing manual fan mode for FAN%d\n", idx);
+		init_manual_fan(conf, idx);
+		break;
+	default:
+		printk(BIOS_ERR, "NCT6687D: unknown fan mode detected!\n");
+	}
+}
+
+static void init_fans(const struct superio_nuvoton_nct6687d_config *conf)
+{
+	unsigned int i;
+	const struct nct6687d_fan_config *fans = conf->fans;
+
+	for (i = 1; i <= MAX_NUM_FANS; i++) {
+		if (fans[i - 1].mode == FAN_IGNORE)
+			continue;
+
+		init_one_fan(conf, i);
+	}
+}
+
+static void report_ec_info(void)
+{
+	unsigned int i;
+
+	printk(BIOS_DEBUG, "NCT6687D EC info:\n");
+	printk(BIOS_DEBUG, "\tChip ID: %04x\n",
+	       (uint16_t)hwm_reg_read(CHIP_ID0_REG) |
+	       (uint16_t)(hwm_reg_read(CHIP_ID1_REG) << 8));
+	printk(BIOS_DEBUG, "\tCustomer ID: %04x\n",
+	       (uint16_t)hwm_reg_read(CUSTOMER_ID0_REG) |
+	       (uint16_t)(hwm_reg_read(CUSTOMER_ID1_REG) << 8));
+	printk(BIOS_DEBUG, "\tFW build date: %02d/%02d/20%02d\n",
+	       hwm_reg_read(FW_BUILD_DAY_REG),
+	       hwm_reg_read(FW_BUILD_MONTH_REG),
+	       hwm_reg_read(FW_BUILD_YEAR_REG));
+	printk(BIOS_DEBUG, "\tFW build serial number: %d\n",
+	       hwm_reg_read(FW_BUILD_SERIALNUM_REG));
+	printk(BIOS_DEBUG, "\tFW version: %d.%d\n",
+	       hwm_reg_read(FW_VER0_REG),
+	       hwm_reg_read(FW_VER1_REG));
+	printk(BIOS_DEBUG, "\tProfile version: %d\n",
+	       hwm_reg_read(PROFILE_VER_REG));
+	printk(BIOS_DEBUG, "\tROM version: %d.%d.%d.%d\n",
+	       hwm_reg_read(ROM_VER0_REG), hwm_reg_read(ROM_VER1_REG),
+	       hwm_reg_read(ROM_VER2_REG), hwm_reg_read(ROM_VER3_REG));
+	printk(BIOS_DEBUG, "\tISP build date: %02d/%02d/20%02d\n",
+	       hwm_reg_read(ISP_BUILD_DAY_REG),
+	       hwm_reg_read(ISP_BUILD_MONTH_REG),
+	       hwm_reg_read(ISP_BUILD_YEAR_REG));
+	printk(BIOS_DEBUG, "\tISP build serial number: %d\n",
+	       hwm_reg_read(ISP_BUILD_SERIALNUM_REG));
+	printk(BIOS_DEBUG, "\tISP version: %d.%d\n",
+	       hwm_reg_read(ISP_VER0_REG),
+	       hwm_reg_read(ISP_VER1_REG));
+	printk(BIOS_DEBUG, "\tOEM version:");
+
+	for (i = 0; i < OEM_VER_LEN; i++)
+		printk(BIOS_DEBUG, "%02x", hwm_reg_read(OEM_VER_REG + i));
+
+	printk(BIOS_DEBUG, "\n");
+}
+
+void nct6687d_hwm_init(uint16_t hwm_base, const struct superio_nuvoton_nct6687d_config *conf)
+{
+	nct6687d_hwm_base = hwm_base;
+
+	report_ec_info();
+
+	init_sensors(conf);
+	init_fans(conf);
+
+	lock_sensor_config();
+	print_fan_engine_status();
+}
diff --git a/src/superio/nuvoton/nct6687d/nct6687d_hwm.h b/src/superio/nuvoton/nct6687d/nct6687d_hwm.h
new file mode 100644
index 0000000000..0037909262
--- /dev/null
+++ b/src/superio/nuvoton/nct6687d/nct6687d_hwm.h
@@ -0,0 +1,922 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#ifndef SUPERIO_NUVOTON_NCT6687D_HWM_H
+#define SUPERIO_NUVOTON_NCT6687D_HWM_H
+
+#include <assert.h>
+#include <types.h>
+
+#include "chip.h"
+#include "nct6687d_ec.h"
+
+/*
+ * EC page number will be concatenated with the register offset to mark
+ * which page the register belongs to.
+ */
+#define EC_PAGE(page)				((page) << 8)
+#define EC_PAGE_REG(page, reg)			(EC_PAGE(page) + (reg))
+
+/* EC page 1 */
+#define SENSOR_READ_HI_REG(x)			EC_PAGE_REG(1, 0x00 + 2*(x))
+#define SENSOR_READ_LO_REG(x)			EC_PAGE_REG(1, 0x01 + 2*(x))
+#define FAN_RPM_READ_HI_REG(x)			EC_PAGE_REG(1, 0x40 + 2*((x) - 1))
+#define FAN_RPM_READ_LO_REG(x)			EC_PAGE_REG(1, 0x41 + 2*((x) - 1))
+
+#define FAN_DUTY_REG(fan) \
+	(((fan) > 8)	? EC_PAGE_REG(8, 0xf0 + ((fan)-8)) \
+			: EC_PAGE_REG(1, 0x60 + 2*((fan) - 1)))
+
+#define SENSOR_MON_STS_REG			EC_PAGE_REG(1, 0x70)
+#define   TEMP_OVERLOAD				(1 << 1)
+#define   VOLT_OVERLOAD				(1 << 1)
+#define   FAN_OVERLOAD				(1 << 2)
+
+/* Errors and statuses */
+#define PROCHOT_MON_STS_REG			EC_PAGE_REG(1, 0x71)
+#define SENSOR_ERROR_STS_REG(x)			EC_PAGE_REG(1, 0x74 + (x))
+#define TMPIN_IDLE_STS_REG(x)			EC_PAGE_REG(1, 0x78 + (x))
+#define FANIN_ERROR_STS_REG(x)			EC_PAGE_REG(1, 0x7C + (x))
+#define FANOUT_ERROR_STS_REG			EC_PAGE_REG(1, 0x7e)
+#define FAN_INIT_STS_REG			EC_PAGE_REG(1, 0x7f)
+
+#define HWM_CONFIG_REG				EC_PAGE_REG(1, 0x80)
+#define   SMI_SCI_SEL				(1 << 2)
+#define   LOCK_SENSOR_CFG			(1 << 5)
+#define   HWM_EN				(1 << 7)
+
+#define SENSOR_MON_VCC_DELAY_REG		EC_PAGE_REG(1, 0x81)
+#define TEMPIN_IDLE_COUNTER_REG			EC_PAGE_REG(1, 0x82)
+#define VIRTUAL_INPUT_CFG_REG			EC_PAGE_REG(1, 0x83)
+#define TMPIN_POLLING_RATE_REG			EC_PAGE_REG(1, 0x85)
+#define VIN_POLLING_RATE_REG			EC_PAGE_REG(1, 0x86)
+#define FAN_POLLING_RATE_REG			EC_PAGE_REG(1, 0x87)
+
+#define ADC_CLOCKK_DIV_REG			EC_PAGE_REG(1, 0x88)
+#define ADC_AVG_NUM_REG				EC_PAGE_REG(1, 0x89)
+#define ADC_SLOPE_HI_REG			EC_PAGE_REG(1, 0x8a)
+#define ADC_SLOPE_LO_REG			EC_PAGE_REG(1, 0x8b)
+
+#define PROCHOT_CFG_REG				EC_PAGE_REG(1, 0x8e)
+#define   REFRESH_RATE_MASK			(3 << 0)
+#define     REFRESH_RATE_100MS			(0 << 0)
+#define     REFRESH_RATE_200MS			(1 << 0)
+#define     REFRESH_RATE_500MS			(2 << 0)
+#define     REFRESH_RATE_1S			(3 << 0)
+#define   AVG_TIME_MASK				(3 << 2)
+#define     AVG_TIME_1				(0 << 2)
+#define     AVG_TIME_2				(1 << 2)
+#define     AVG_TIME_4				(2 << 2)
+#define     AVG_TIME_8				(3 << 2)
+#define   MONITOR_MODE_MASK			(3 << 4)
+#define     MONITOR_MODE_CAPTURE		(0 << 4)
+#define     MONITOR_MODE_8BIT			(1 << 4)
+#define     MONITOR_MODE_12BIT			(2 << 4)
+#define     MONITOR_MODE_16BIT			(3 << 4)
+#define   CLK_SRC_40K				(0 << 6)
+#define   CLK_SRC_MCLK				(1 << 6)
+#define   PROCHOT_EN				(1 << 7)
+
+#define PROCHOT_OUT_REG				EC_PAGE_REG(1, 0x8f)
+
+#define VIRTUAL_SENSOR_INPUT_REG(x)		EC_PAGE_REG(1, 0x90 + (x))
+
+#define SENSOR_CFG_REG(x)			EC_PAGE_REG(1, 0xa0 + (x))
+#define  FILTER_EN				(1 << 7)
+#define  SENSOR_SRC_SEL_MASK			0x7f
+
+#define FANIN_CFG_REG(fan)			EC_PAGE_REG(1, 0xc0 + ((fan) - 1))
+#define   FANIN_PIN_SEL_MASK			0x1f
+#define   FANIN_PULSE_REV_MASK			(3 << 5)
+#define   FANIN_PULSE_REV_SHIFT			5
+#define   FANIN_MONITOR_EN			(1 << 7)
+
+#define FANOUT_CFG_REG(fan) \
+	(((fan) > 8)	? EC_PAGE_REG(8, 0xf4 + ((fan) - 9)) \
+			: EC_PAGE_REG(1, 0xd0 + ((fan) - 1)))
+#define   FANOUT_PIN_SEL_MASK			0x1f
+#define   FANOUT_TYPE_PP			(0 << 5)
+#define   FANOUT_TYPE_OD			(1 << 5)
+#define   FANOUT_INV_EN				(1 << 6)
+#define   FANOUT_EN				(1 << 7)
+
+#define FAN_INIT_RPM_HI_REG(fan)		EC_PAGE_REG(1, 0xe0 + 2*((fan) - 1))
+#define FAN_INIT_RPM_LO_REG(fan)		EC_PAGE_REG(1, 0xe1 + 2*((fan) - 1))
+#define FAN_INIT_DUTY_VAL_REG(fan)		EC_PAGE_REG(1, 0xf0 + ((fan) - 1))
+#define FAN_INIT_MODE_REG			EC_PAGE_REG(1, 0xf8)
+#define   FAN_INIT_MODE_RPM(fan)		(1 << ((fan) - 1))
+#define   FAN_INIT_MODE_PWM(fan)		(0 << ((fan) - 1))
+
+#define FAN_RPM_INIT_UNIT_REG			EC_PAGE_REG(1, 0xf9)
+#define FAN_RPM_INIT_TOLERANCE_REG		EC_PAGE_REG(1, 0xfa)
+#define FAN_RPM_INIT_STABLE_COUNTER_REG		EC_PAGE_REG(1, 0xfb)
+#define FAN_RPM_INIT_TIME_COUNTER_REG		EC_PAGE_REG(1, 0xfc)
+
+/* EC Page 2 - GPIO */
+
+#define TIN_OFFSET_REG(x)			EC_PAGE_REG(2, 0x00 + (x))
+
+#define GPI_FALLING_TRIG_EN_HI_REG		EC_PAGE_REG(2, 0xb0)
+#define GPI_FALLING_TRIG_EN_LO_REG		EC_PAGE_REG(2, 0xb1)
+#define GPI_RISING_TRIG_EN_HI_REG		EC_PAGE_REG(2, 0xb2)
+#define GPI_RISING_TRIG_EN_LO_REG		EC_PAGE_REG(2, 0xb3)
+#define GPI_DATA_HI_REG				EC_PAGE_REG(2, 0xb4)
+#define GPI_DATA_LO_REG				EC_PAGE_REG(2, 0xb5)
+#define GPI_SEL_REG(x)				EC_PAGE_REG(2, 0xc0 + (x))
+#define GPO_TYPE_HI_REG				EC_PAGE_REG(2, 0xd0)
+#define GPO_TYPE_LO_REG				EC_PAGE_REG(2, 0xd1)
+#define GPO_DATA_HI_REG				EC_PAGE_REG(2, 0xd4)
+#define GPO_DATA_LO_REG				EC_PAGE_REG(2, 0xd5)
+#define GPO_SEL_REG(x)				EC_PAGE_REG(2, 0xe0 + (x))
+
+/* EC page 3 */
+
+#define SENSOR_INT_CFG_REG(x)			EC_PAGE_REG(3, 0x10 + (x))
+#define   TMPIN_INT_SEL_MASK			(7 << 0)
+#define   TMPIN_INT_DISABLE			(0 << 0)
+#define   TMPIN_INT_SHUTDOWN_MODE		(1 << 0)
+#define   TMPIN_INT_SYST_FAN_COMP_MODE		(2 << 0)
+#define   TMPIN_INT_CPUT_FAN_COMP_MODE		(3 << 0)
+#define   TMPIN_INT_TWO_TIMES_MODE		(4 << 0)
+#define   TMPIN_INT_ONE_TIME_MODE		(5 << 0)
+#define   TMPIN_INT_OVT_COMP_MODE		(6 << 0)
+#define   TMPIN_INT_OVT_MODE			(7 << 0)
+#define   VIN_INT_EN				(1 << 7)
+
+#define TMPIN_HYSTERSIS_REG(x)			EC_PAGE_REG(3, 0x30 + (x))
+#define TMPIN_OVERTEMP_REG(x)			EC_PAGE_REG(3, 0x50 + (x))
+#define TIN_SHUTDOWN_VIN_LIMIT_HI_REG(x)	EC_PAGE_REG(3, 0x70 + 2*(x))
+#define TIN_SHUTDOWN_VIN_LIMIT_LO_REG(x)	EC_PAGE_REG(3, 0x71 + 2*(x))
+
+#define FAN_RPM_INT_EN1_REG			EC_PAGE_REG(3, 0xb0)
+#define FAN_RPM_INT_EN2_REG			EC_PAGE_REG(3, 0xb1)
+
+#define FAN_RPM_LIMIT_HI_REG(fan)		EC_PAGE_REG(3, 0xb8 + 2*(fan))
+#define FAN_RPM_LIMIT_LO_REG(fan)		EC_PAGE_REG(3, 0xb9 + 2*(fan))
+
+/* EC Page 4 - SMBus */
+
+#define PCH_ERR_STS_REG				EC_PAGE_REG(4, 0x00)
+#define TSI_ERR_STS_REG				EC_PAGE_REG(4, 0x01)
+#define SMBUS_MASTER_ERR_STS_REG		EC_PAGE_REG(4, 0x04)
+#define SMBUS_THERM_SENSOR_ERR_STS_REG(x)	EC_PAGE_REG(4, 0x06 + (x))
+#define SMBUS_DIMM_SENSOR_ERR_STS_REG(x)	EC_PAGE_REG(4, 0x0c + (x))
+
+#define PCH_THERMAL_DATA_CFG_REG		EC_PAGE_REG(4, 0x10)
+#define   PCH_BAUD_SEL_MASK			(7 << 0)
+#define      PCH_BAUD_12_5K			(0  << 0)
+#define      PCH_BAUD_25K			(1  << 0)
+#define      PCH_BAUD_50K			(2  << 0)
+#define      PCH_BAUD_100K			(3  << 0)
+#define      PCH_BAUD_200K			(4  << 0)
+#define      PCH_BAUD_400K			(5  << 0)
+#define      PCH_BAUD_800K			(6  << 0)
+#define      PCH_BAUD_1200K			(7  << 0)
+#define   PCH_PORT_SEL_MASK			(3 << 4)
+#define     PCH_THERMAL_PORT(x)			((x) << 4)
+#define   PCH_ONE_BYTE_REPORT			(1 << 7)
+
+#define PCH_DEVICE_ADDR_REG			EC_PAGE_REG(4, 0x11)
+#define PCH_THERMAL_CMD_REG			EC_PAGE_REG(4, 0x12)
+
+#define TSI_THERMAL_DATA_CFG_REG		EC_PAGE_REG(4, 0x14)
+#define   TSI_BAUD_SEL_MASK			(7 << 0)
+#define      TSI_BAUD_12_5K			(0  << 0)
+#define      TSI_BAUD_25K			(1  << 0)
+#define      TSI_BAUD_50K			(2  << 0)
+#define      TSI_BAUD_100K			(3  << 0)
+#define      TSI_BAUD_200K			(4  << 0)
+#define      TSI_BAUD_400K			(5  << 0)
+#define      TSI_BAUD_800K			(6  << 0)
+#define      TSI_BAUD_1200K			(7  << 0)
+#define   TSI_PORT_SEL_MASK			(3 << 4)
+#define     TSI_THERMAL_PORT(x)			((x) << 4)
+
+#define SMBUS_SENSOR_CFG_REG(x)			EC_PAGE_REG(4, 0x1a + 5*(x))
+#define   SMB_BAUD_SEL_MASK			(7 << 0)
+#define      SMB_BAUD_12_5K			(0  << 0)
+#define      SMB_BAUD_25K			(1  << 0)
+#define      SMB_BAUD_50K			(2  << 0)
+#define      SMB_BAUD_100K			(3  << 0)
+#define      SMB_BAUD_200K			(4  << 0)
+#define      SMB_BAUD_400K			(5  << 0)
+#define      SMB_BAUD_800K			(6  << 0)
+#define      SMB_BAUD_1200K			(7  << 0)
+#define   SMB_PORT_SEL_MASK			(3 << 4)
+#define     SMB_SENSOR_PORT(x)			((x) << 4)
+#define   SMB_SENSOR_DATA_LEN_1B		(0 << 6)
+#define   SMB_SENSOR_DATA_LEN_2B		(1 << 6)
+#define   SMB_SENSOR_DIRECT_ACCESS		(1 << 7)
+
+#define SMBUS_SENSOR_ADDR_REG(x)		EC_PAGE_REG(4, 0x1b + 5*(x))
+#define SMBUS_SENSOR_CMD_REG(x)			EC_PAGE_REG(4, 0x1c + 5*(x))
+#define SMBUS_SENSOR_DATA_REG(x)		EC_PAGE_REG(4, 0x1d + 5*(x))
+#define SMBUS_SENSOR_READ_CMD_REG(x)		EC_PAGE_REG(4, 0x1e + 5*(x))
+
+#define SMBUS_DIMM_SENSOR_CFG0(x)		EC_PAGE_REG(4, 0x3a + 4*(x))
+#define   SMB_DIMM_ADDR_MASK			0x07
+#define   SMB_DIMM_BAUD_SEL_MASK		(7 << 4)
+#define      SMB_DIMM_BAUD_12_5K		(0  << 0)
+#define      SMB_DIMM_BAUD_25K			(1  << 0)
+#define      SMB_DIMM_BAUD_50K			(2  << 0)
+#define      SMB_DIMM_BAUD_100K			(3  << 0)
+#define      SMB_DIMM_BAUD_200K			(4  << 0)
+#define      SMB_DIMM_BAUD_400K			(5  << 0)
+#define      SMB_DIMM_BAUD_800K			(6  << 0)
+#define      SMB_DIMM_BAUD_1200K		(7  << 0)
+#define   SMBUS_DIMM_SENSOR_EN			(1 << 7)
+
+#define SMBUS_DIMM_SENSOR_CFG1_REG(x)		EC_PAGE_REG(4, 0x3b + 4*(x))
+/* Bits 0-2 is address as in CFG0, bit 7 is DIMM sensor enable */
+#define   SMD_DIMM_ADDR_MASK			0x07
+#define   SMB_PORT_SEL_MASK			(3 << 4)
+#define     SMB_SENSOR_PORT(x)			((x) << 4)
+
+#define SMBUS_DIMM_SENSOR_CFG2_REG(x)		EC_PAGE_REG(4, 0x3c + 4*(x))
+/* Bits 0-2 is address as in CFG0, bit 7 is DIMM sensor enable */
+
+#define SMBUS_DIMM_SENSOR_CFG3_REG(x)		EC_PAGE_REG(4, 0x3d + 4*(x))
+/* Bits 0-2 is address as in CFG0, bit 7 is DIMM sensor enable */
+
+#define SMBUS_MASTER_CFG1_REG			EC_PAGE_REG(4, 0x60)
+#define   SMB_MASTER_POLLRATE_MASK		0x07
+#define     SMB_MASTER_POLLRATE_ONCE		(0 << 0)
+#define     SMB_MASTER_POLLRATE_100MS		(0 << 0)
+#define     SMB_MASTER_POLLRATE_200MS		(0 << 0)
+#define     SMB_MASTER_POLLRATE_400MS		(0 << 0)
+#define     SMB_MASTER_POLLRATE_800MS		(0 << 0)
+#define     SMB_MASTER_POLLRATE_1S		(0 << 0)
+#define     SMB_MASTER_POLLRATE_2S		(0 << 0)
+#define     SMB_MASTER_POLLRATE_4S		(0 << 0)
+#define   SMB_MASTER_CLEAR_BUF			(1 << 3)
+#define   SMB_MASTER_HOLD_RDY			(1 << 5)
+#define   SMB_MASTER_START			(1 << 6)
+#define   SMB_MASTER_EN				(1 << 7)
+
+#define SMBUS_MASTER_CFG2_REG			EC_PAGE_REG(4, 0x61)
+#define   SMB_MASTER_PORT_SEL_MASK		0x03
+#define     SMB_MASTER_PORT(x)			((x) << 0)
+#define     SMB_MASTER_PEC_EN			(1 << 3)
+
+#define SMBUS_MASTER_BAUD_RATE_SEL_REG		EC_PAGE_REG(4, 0x62)
+#define   SMB_MASTER_BAUD_SEL_MASK		(7 << 4)
+#define      SMB_MASTER_BAUD_12_5K		(0  << 0)
+#define      SMB_MASTER_BAUD_25K		(1  << 0)
+#define      SMB_MASTER_BAUD_50K		(2  << 0)
+#define      SMB_MASTER_BAUD_100K		(3  << 0)
+#define      SMB_MASTER_BAUD_200K		(4  << 0)
+#define      SMB_MASTER_BAUD_400K		(5  << 0)
+#define      SMB_MASTER_BAUD_800K		(6  << 0)
+#define      SMB_MASTER_BAUD_1200K		(7  << 0)
+
+#define SMBUS_MASTER_PROTOCOL_SEL_REG		EC_PAGE_REG(4, 0x63)
+#define   SMBUS_MASTER_QUICK_WRITE		0x00
+#define   SMBUS_MASTER_SEND_BYTE		0x01
+#define   SMBUS_MASTER_WRITE_BYTE		0x02
+#define   SMBUS_MASTER_WRITE_WORD		0x03
+#define   SMBUS_MASTER_BLOCK_WRITE		0x04
+#define   SMBUS_MASTER_PROCESS_CALL		0x05
+#define   SMBUS_MASTER_BLOCK_WRITE_READ		0x06
+#define   SMBUS_MASTER_RECEIVE_BYTE		0x81
+#define   SMBUS_MASTER_READ_BYTE		0x82
+#define   SMBUS_MASTER_READ_WORD		0x83
+#define   SMBUS_MASTER_BLOCK_READ		0x84
+
+#define SMBUS_MASTER_BLOCK_WR_LEN_REG		EC_PAGE_REG(4, 0x64)
+#define SMBUS_MASTER_DEV_ADDR_REG		EC_PAGE_REG(4, 0x65)
+#define SMBUS_MASTER_CMD_REG			EC_PAGE_REG(4, 0x66)
+
+#define SMBUS_MASTER_WRITE_BUFFER(x)		EC_PAGE_REG(4, 0x70 + (x))
+#define SMBUS_MASTER_WRITE_BUFFER_LEN		64
+#define SMBUS_MASTER_READ_BUFFER(x)		EC_PAGE_REG(4, 0xb0 + (x))
+#define SMBUS_MASTER_READ_BUFFER_LEN		64
+
+/* EC page 5 - PECI */
+
+#define PECI_PING_INFO_REG			EC_PAGE_REG(5, 0x00)
+#define   PECI_AGENT_ALIVE(agent)		(1 << (agent))
+#define   PECI_OVER_SMBUS			(1 << 7)
+
+#define PECI_INFO_STS_REG			EC_PAGE_REG(5, 0x01)
+#define   PECI_AGENT_INFO_RDY(agent)		(1 << (agent))
+
+#define PECI_DEVICE_INFO_REG			EC_PAGE_REG(5, 0x02)
+#define   PECI_AGENT_TWO_DOMAIN_SUPPORT		(1 << 2)
+
+#define PECI_REVISION_INFO_REG			EC_PAGE_REG(5, 0x03)
+#define   PECI_REV_MINOR_MASK			0x0f
+#define   PECI_REV_MINOR_SHIFT			0
+#define   PECI_REV_MAJOR_MASK			0xf0
+#define   PECI_REV_MAJOR_SHIFT			4
+
+#define PECI_DOM0_MARGIN_HI_REG(agent)		EC_PAGE_REG(5, 0x20 + 2*(agent))
+#define PECI_DOM0_MARGIN_LO_REG(agent)		EC_PAGE_REG(5, 0x21 + 2*(agent))
+#define PECI_DOM1_MARGIN_HI_REG(agent)		EC_PAGE_REG(5, 0x28 + 2*(agent))
+#define PECI_DOM1_MARGIN_LO_REG(agent)		EC_PAGE_REG(5, 0x29 + 2*(agent))
+
+#define PECI_DOM0_TEMP_HI_REG(agent)		EC_PAGE_REG(5, 0x30 + 2*(agent))
+#define PECI_DOM0_TEMP_LO_REG(agent)		EC_PAGE_REG(5, 0x31 + 2*(agent))
+#define PECI_DOM1_TEMP_HI_REG(agent)		EC_PAGE_REG(5, 0x38 + 2*(agent))
+#define PECI_DOM1_TEMP_LO_REG(agent)		EC_PAGE_REG(5, 0x39 + 2*(agent))
+
+#define PECI_TCONTROL_REG(dom, agent)		EC_PAGE_REG(5, 0x40 + 4*(dom) + (agent))
+#define PECI_TJMAX_REG(dom, agent)		EC_PAGE_REG(5, 0x48 + 4*(dom) + (agent))
+
+#define PECI_PCS_ERR_STS_REG			EC_PAGE_REG(5, 0x52)
+#define PECI_MASTER_ERR_STS_REG			EC_PAGE_REG(5, 0x53)
+
+#define PECI_CFG_REG				EC_PAGE_REG(5, 0x60)
+#define   PECI_SPEED_SEL_MASK			(3 << 0)
+#define     PECI_SPEED_2MHZ			(0 << 0)
+#define     PECI_SPEED_1_2MHZ			(1 << 0)
+#define     PECI_SPEED_800KHZ			(2 << 0)
+#define     PECI_SPEED_400KHZ			(3 << 0)
+#define   PECI_USER_TJMAX_FROM_CPU		(0 << 5)
+#define   PECI_USER_TJMAX_FROM_EC		(1 << 5)
+#define   PECI_AGENT_INIT			(1 << 6)
+#define   PECI_EN				(1 << 7)
+
+#define PECI_AGENT_EN_REG			EC_PAGE_REG(5, 0x61)
+#define   PECI_AGENT_EN_MASK			0xf
+#define   PECI_AGENT_EN(agent)			(1 << (agent))
+
+#define PECI_HOSTID_REG				EC_PAGE_REG(5, 0x62)
+#define PECI_ERR_RETRY_CFG_REG			EC_PAGE_REG(5, 0x63)
+#define PECI_MARGIN_CFG_REG			EC_PAGE_REG(5, 0x64)
+#define   PECI_MARGIN_POLLRATE_MASK		0x07
+#define     PECI_MARGIN_POLLRATE_ONCE		(0 << 0)
+#define     PECI_MARGIN_POLLRATE_100MS		(1 << 0)
+#define     PECI_MARGIN_POLLRATE_200MS		(2 << 0)
+#define     PECI_MARGIN_POLLRATE_400MS		(3 << 0)
+#define     PECI_MARGIN_POLLRATE_800MS		(4 << 0)
+#define     PECI_MARGIN_POLLRATE_1S		(5 << 0)
+#define     PECI_MARGIN_POLLRATE_2S		(6 << 0)
+#define     PECI_MARGIN_POLLRATE_4S		(7 << 0)
+#define   PECI_GET_MARGIN_EN			(1 << 7)
+
+#define PECI_USER_TJMAX_REG(dom, agent)		EC_PAGE_REG(5, 0x68 + 4*(dom) + (agent))
+#define PECI_PCS_CFG_REG			0x70
+#define   PECI_PCS_POLLRATE_MASK		0x07
+#define     PECI_PCS_POLLRATE_ONCE		(0 << 0)
+#define     PECI_PCS_POLLRATE_100MS		(1 << 0)
+#define     PECI_PCS_POLLRATE_200MS		(2 << 0)
+#define     PECI_PCS_POLLRATE_400MS		(3 << 0)
+#define     PECI_PCS_POLLRATE_800MS		(4 << 0)
+#define     PECI_PCS_POLLRATE_1S		(5 << 0)
+#define     PECI_PCS_POLLRATE_2S		(6 << 0)
+#define     PECI_PCS_POLLRATE_4S		(7 << 0)
+#define   PECI_PCS_STOP_ERR			(1 << 4)
+#define   PECI_PCS_HOLD_RDY			(1 << 5)
+#define   PECI_PCS_START			(1 << 6)
+#define   PECI_PCS_EN				(1 << 7)
+
+#define PECI_PCS_CFG2_REG			EC_PAGE_REG(5, 0x71)
+#define   PECI_PCS_AGENT_SEL_MASK		0x03
+#define   PECI_PCS_SEL_DOM0			(0 << 4)
+#define   PECI_PCS_SEL_DOM1			(1 << 4)
+#define   PECI_PCS_WRITE_PKG_CFG		(1 << 7)
+
+#define PECI_PCS_IDX_REG			EC_PAGE_REG(5, 0x72)
+#define PECI_PCS_PARAM_LO_REG			EC_PAGE_REG(5, 0x73)
+#define PECI_PCS_PARAM_HI_REG			EC_PAGE_REG(5, 0x74)
+
+#define PECI_PCS_COMPLETION_CODE_REG		EC_PAGE_REG(5, 0x75)
+#define   PECI_PCS_DATA_VALID			0x40
+#define   PECI_PCS_RESP_TIMEOUT_RETRY		0x80
+#define   PECI_PCS_RESP_TIMEOUT			0x81
+#define   PECI_PCS_INVALID_REQUEST		0x90
+#define   PECI_PCS_PECI_CONTROL_HW		0x91
+
+#define PECI_PCS_BUF_REG(x)			EC_PAGE_REG(5, 0x76 + (x))
+#define PECI_PCS_BUF_LEN			4
+
+#define PECI_MASTER_CFG_REG			EC_PAGE_REG(5, 0x7a)
+#define   PECI_MASTER_POLLRATE_MASK		0x07
+#define     PECI_MASTER_POLLRATE_ONCE		(0 << 0)
+#define     PECI_MASTER_POLLRATE_100MS		(1 << 0)
+#define     PECI_MASTER_POLLRATE_200MS		(2 << 0)
+#define     PECI_MASTER_POLLRATE_400MS		(3 << 0)
+#define     PECI_MASTER_POLLRATE_800MS		(4 << 0)
+#define     PECI_MASTER_POLLRATE_1S		(5 << 0)
+#define     PECI_MASTER_POLLRATE_2S		(6 << 0)
+#define     PECI_MASTER_POLLRATE_4S		(7 << 0)
+#define   PECI_MASTER_STOP_ERR			(1 << 4)
+#define   PECI_MASTER_HOLD_RDY			(1 << 5)
+#define   PECI_MASTER_START			(1 << 6)
+#define   PECI_MASTER_EN			(1 << 7)
+
+#define PECI_MASTER_CFG2_REG			EC_PAGE_REG(5, 0x7b)
+#define   PECI_MASTER_CPL_CODE_SUPP		(1 << 6)
+#define   PECI_MASTER_AWFCS_EN			(1 << 7)
+
+#define PECI_MASTER_CLIENT_ADDR_REG		EC_PAGE_REG(5, 0x7c)
+#define PECI_MASTER_CMD_CODE_REG		EC_PAGE_REG(5, 0x7d)
+#define PECI_MASTER_WRITE_LEN_REG		EC_PAGE_REG(5, 0x7e)
+#define PECI_MASTER_READ_LEN_REG		EC_PAGE_REG(5, 0x7f)
+
+#define PECI_MASTER_WRITE_BUF(x)		EC_PAGE_REG(5, 0x80 + (x))
+#define PECI_MASTER_WRITE_BUF_LEN		12
+#define PECI_MASTER_READ_BUF(x)			EC_PAGE_REG(5, 0x90 + (x))
+#define PECI_MASTER_READ_BUF_LEN		12
+
+#define PECI_DRAM_TEMP_WR_STS_REG(x)		EC_PAGE_REG(5, 0xa0 + (x))
+#define PECI_DIMM_AMB_TEMP_WR_STS_REG(x)	EC_PAGE_REG(5, 0xa4 + (x))
+#define PECI_DIMM_TEMP_RD_STS_REG(x)		EC_PAGE_REG(5, 0xa8 + (x))
+#define PECI_ACC_ENERGRY_RD_STS_REG(x)		EC_PAGE_REG(5, 0xac + (x))
+
+#define PECI_DRAM_TEMP_WR_POLL_RATE_REG		EC_PAGE_REG(5, 0xb0)
+#define   PECI_DRAM_POLLRATE_MASK		0x07
+#define     PECI_DRAM_POLLRATE_ONCE		(0 << 0)
+#define     PECI_DRAM_POLLRATE_100MS		(1 << 0)
+#define     PECI_DRAM_POLLRATE_200MS		(2 << 0)
+#define     PECI_DRAM_POLLRATE_400MS		(3 << 0)
+#define     PECI_DRAM_POLLRATE_800MS		(4 << 0)
+#define     PECI_DRAM_POLLRATE_1S		(5 << 0)
+#define     PECI_DRAM_POLLRATE_2S		(6 << 0)
+#define     PECI_DRAM_POLLRATE_4S		(7 << 0)
+
+#define PECI_DIMM_AMB_TEMP_WR_POLL_RATE_REG	EC_PAGE_REG(5, 0xb1)
+#define   PECI_DIMM_AMB_POLLRATE_MASK		0x07
+#define     PECI_DIMM_AMB_POLLRATE_ONCE		(0 << 0)
+#define     PECI_DIMM_AMB_POLLRATE_100MS	(1 << 0)
+#define     PECI_DIMM_AMB_POLLRATE_200MS	(2 << 0)
+#define     PECI_DIMM_AMB_POLLRATE_400MS	(3 << 0)
+#define     PECI_DIMM_AMB_POLLRATE_800MS	(4 << 0)
+#define     PECI_DIMM_AMB_POLLRATE_1S		(5 << 0)
+#define     PECI_DIMM_AMB_POLLRATE_2S		(6 << 0)
+#define     PECI_DIMM_AMB_POLLRATE_4S		(7 << 0)
+
+#define PECI_ACC_ENERGRY_RD_POLL_RATE_REG	EC_PAGE_REG(5, 0xb2)
+#define   PECI_ACC_ENERGRY_RD_POLLRATE_MASK	0x07
+#define     PECI_ACC_ENERGRY_RD_POLLRATE_ONCE	(0 << 0)
+#define     PECI_ACC_ENERGRY_RD_POLLRATE_100MS	(1 << 0)
+#define     PECI_ACC_ENERGRY_RD_POLLRATE_200MS	(2 << 0)
+#define     PECI_ACC_ENERGRY_RD_POLLRATE_400MS	(3 << 0)
+#define     PECI_ACC_ENERGRY_RD_POLLRATE_800MS	(4 << 0)
+#define     PECI_ACC_ENERGRY_RD_POLLRATE_1S	(5 << 0)
+#define     PECI_ACC_ENERGRY_RD_POLLRATE_2S	(6 << 0)
+#define     PECI_ACC_ENERGRY_RD_POLLRATE_4S	(7 << 0)
+
+#define PECI_DRAM_TEMP_WR_CFG1_REG(x)		EC_PAGE_REG(5, 0xb8 + 2*(x))
+#define   PECI_DRAM_TEMP_WR_CH_IDX_MASK		(7 << 0)
+#define   PECI_DRAM_TEMP_WR_CH_IDX_SHIFT	0
+#define   PECI_DRAM_TEMP_WR_DIMM_IDX_MASK	(7 << 3)
+#define   PECI_DRAM_TEMP_WR_DIMM_IDX_SHIFT	3
+#define   PECI_DRAM_TEMP_WR_POLLING		(1 << 6)
+#define   PECI_DRAM_TEMP_WR_START		(1 << 7)
+
+#define PECI_DRAM_TEMP_WR_CFG2_REG(x)		EC_PAGE_REG(5, 0xb9 + 2*(x))
+#define   PECI_DRAM_TEMP_WR_AGENT_IDX_MASK	(3 << 1)
+#define   PECI_DRAM_TEMP_WR_AGENT_IDX_SHIFT	1
+#define   PECI_DRAM_TEMP_WR_DOM0		(0 << 6)
+#define   PECI_DRAM_TEMP_WR_DOM1		(1 << 6)
+#define   PECI_DRAM_TEMP_WR_CH_SEL		(1 << 7)
+
+#define PECI_DIMM_AMB_TEMP_WR_CFG1_REG(x)	EC_PAGE_REG(5, 0xc0 + 2*(x))
+#define   PECI_DIMM_AMB_TEMP_WR_CH_IDX_MASK	(7 << 0)
+#define   PECI_DIMM_AMB_TEMP_WR_CH_IDX_SHIFT	0
+#define   PECI_DIMM_AMB_TEMP_WR_POLLING		(1 << 6)
+#define   PECI_DIMM_AMB_TEMP_WR_START		(1 << 7)
+
+#define PECI_DIMM_AMB_TEMP_WR_CFG2_REG(x)	EC_PAGE_REG(5, 0xc1 + 2*(x))
+#define   PECI_DIMM_AMB_TEMP_WR_AGENT_IDX_MASK	(3 << 1)
+#define   PECI_DIMM_AMB_TEMP_WR_AGENT_IDX_SHIFT	1
+#define   PECI_DIMM_AMB_TEMP_WR_DOM0		(0 << 6)
+#define   PECI_DIMM_AMB_TEMP_WR_DOM1		(1 << 6)
+#define   PECI_DIMM_AMB_TEMP_WR_CH_SEL		(1 << 7)
+
+#define PECI_DIMM_TEMP_RD_CFG1_REG(x)		EC_PAGE_REG(5, 0xc8 + (x))
+#define   PECI_DIMM_TEMP_RD_AGENT_IDX_MASK	(3 << 0)
+#define   PECI_DIMM_TEMP_RD_AGENT_IDX_SHIFT	0
+#define   PECI_DIMM_TEMP_RD_DOM0		(0 << 2)
+#define   PECI_DIMM_TEMP_RD_DOM1		(1 << 2)
+#define   PECI_DIMM_TEMP_RD_DIMM_SEL_MASK	(3 << 4)
+#define     PECI_DIMM_TEMP_RD_DIMM0		(0 << 4)
+#define     PECI_DIMM_TEMP_RD_DIMM1		(1 << 4)
+#define     PECI_DIMM_TEMP_RD_DIMM0_MAX		(2 << 4)
+#define     PECI_DIMM_TEMP_RD_DIMM1_MAX		(3 << 4)
+#define   PECI_DIMM_TEMP_RD_DIMM_CH0		(0 << 6)
+#define   PECI_DIMM_TEMP_RD_DIMM_CH1		(1 << 6)
+
+#define PECI_ACC_ENERGRY_RD_CFG_REG(x)		EC_PAGE_REG(5, 0xcc + (x))
+#define   PECI_ACC_ENERGRY_RD_AGENT_IDX_MASK	(3 << 0)
+#define   PECI_ACC_ENERGRY_RD_AGENT_IDX_SHIFT	0
+#define   PECI_ACC_ENERGRY_RD_DOM0		(0 << 2)
+#define   PECI_ACC_ENERGRY_RD_DOM1		(1 << 2)
+#define   PECI_ACC_ENERGRY_RD_REPORT_CURR	(0 << 3)
+#define   PECI_ACC_ENERGRY_RD_REPORT_INCR	(1 << 3)
+#define   PECI_DIMM_TEMP_RD_PWR_PLANE_SEL_MASK	(3 << 4)
+#define     PECI_DIMM_TEMP_RD_PWR_PLANE0	(0 << 4)
+#define     PECI_DIMM_TEMP_RD_PWR_PLANE1	(1 << 4)
+#define     PECI_DIMM_TEMP_RD_PKG_PWR_PLANE0	(2 << 4)
+#define     PECI_DIMM_TEMP_RD_PKG_PWR_PLANE1	(3 << 4)
+#define     PECI_ACC_ENERGRY_RD_POLLING		(1 << 6)
+#define     PECI_ACC_ENERGRY_RD_START		(1 << 7)
+
+#define PECI_ACC_ENERGRY_RD_VAL_B0_REG(x)	EC_PAGE_REG(5, 0xd0 + 4*(x))
+#define PECI_ACC_ENERGRY_RD_VAL_B1_REG(x)	EC_PAGE_REG(5, 0xd1 + 4*(x))
+#define PECI_ACC_ENERGRY_RD_VAL_B2_REG(x)	EC_PAGE_REG(5, 0xd2 + 4*(x))
+#define PECI_ACC_ENERGRY_RD_VAL_B3_REG(x)	EC_PAGE_REG(5, 0xd3 + 4*(x))
+
+/* EC Page 6 - EC FW Information and Configuration */
+
+#define CHIP_ID0_REG				EC_PAGE_REG(6, 0x00)
+#define CHIP_ID1_REG				EC_PAGE_REG(6, 0x01)
+#define CUSTOMER_ID0_REG			EC_PAGE_REG(6, 0x02)
+#define CUSTOMER_ID1_REG			EC_PAGE_REG(6, 0x03)
+#define FW_BUILD_YEAR_REG			EC_PAGE_REG(6, 0x04)
+#define FW_BUILD_MONTH_REG			EC_PAGE_REG(6, 0x05)
+#define FW_BUILD_DAY_REG			EC_PAGE_REG(6, 0x06)
+#define FW_BUILD_SERIALNUM_REG			EC_PAGE_REG(6, 0x07)
+#define FW_VER0_REG				EC_PAGE_REG(6, 0x08)
+#define FW_VER1_REG				EC_PAGE_REG(6, 0x09)
+#define PROFILE_VER_REG				EC_PAGE_REG(6, 0x0a)
+#define ROM_VER0_REG				EC_PAGE_REG(6, 0x0c)
+#define ROM_VER1_REG				EC_PAGE_REG(6, 0x0d)
+#define ROM_VER2_REG				EC_PAGE_REG(6, 0x0e)
+#define ROM_VER3_REG				EC_PAGE_REG(6, 0x0f)
+#define ISP_BUILD_YEAR_REG			EC_PAGE_REG(6, 0x12)
+#define ISP_BUILD_MONTH_REG			EC_PAGE_REG(6, 0x13)
+#define ISP_BUILD_DAY_REG			EC_PAGE_REG(6, 0x14)
+#define ISP_BUILD_SERIALNUM_REG			EC_PAGE_REG(6, 0x15)
+#define ISP_VER0_REG				EC_PAGE_REG(6, 0x16)
+#define ISP_VER1_REG				EC_PAGE_REG(6, 0x17)
+
+#define OEM_VER_REG				EC_PAGE_REG(6, 0x18)
+#define   OEM_VER_LEN				8
+
+#define EC_ALIVE_COUNTER_REG			EC_PAGE_REG(6, 0x20)
+
+#define EC_HEARTBEAT_CFG_REG			EC_PAGE_REG(6, 0x2e)
+#define   EC_HEARBEAT_TOGGLE_RATE_MASK		0x0f
+#define   EC_HEARBEAT_TYPE_OD			(0 << 6)
+#define   EC_HEARBEAT_TYPE_PP			(1 << 6)
+#define   EC_HEARBEAT_EN			(1 << 7)
+
+#define EC_HEARTBEAT_GPSEL_REG			EC_PAGE_REG(6, 0x2f)
+#define   EC_HEARBEAT_GPIO_PIN_MASK		0x0f
+#define   EC_HEARBEAT_GPIO_PIN_SHIFT		0
+#define   EC_HEARBEAT_GPIO_GROUP_MASK		0xf0
+#define   EC_HEARBEAT_GPIO_GROUP_SHIFT		4
+
+#define EC_MCU_SPEED_REG			EC_PAGE_REG(6, 0x38)
+#define   EC_MCU_SPEED_MCLK_MASK		0x0f
+#define     EC_MCU_SPEED_MCLK_10KHZ		(0 << 0)
+#define     EC_MCU_SPEED_MCLK_160KHZ		(1 << 0)
+#define     EC_MCU_SPEED_MCLK_1MHZ		(2 << 0)
+#define     EC_MCU_SPEED_MCLK_4MHZ		(3 << 0)
+#define     EC_MCU_SPEED_MCLK_8MHZ		(4 << 0)
+#define     EC_MCU_SPEED_MCLK_16MHZ		(5 << 0)
+#define     EC_MCU_SPEED_MCLK_24MHZ		(6 << 0)
+#define     EC_MCU_SPEED_MCLK_48MHZ		(7 << 0)
+#define   EC_MCU_CACHE_EN			(1 << 6)
+
+#define EC_FLASH_SPEED_REG			EC_PAGE_REG(6, 0x39)
+#define   EC_FLASH_CLK_DIV_MASK			(3 << 4)
+#define     EC_FLASH_CLK_DIV_1			(0 << 4)
+#define     EC_FLASH_CLK_DIV_2			(1 << 4)
+#define     EC_FLASH_CLK_DIV_4			(2 << 4)
+#define     EC_FLASH_CLK_DIV_16			(3 << 4)
+#define   EC_FLASH_FETCH_MODE_MASK		(3 << 6)
+#define     EC_FLASH_FETCH_MODE_READ		(0 << 6)
+#define     EC_FLASH_FETCH_MODE_FAST_READ	(1 << 6)
+#define     EC_FLASH_FETCH_MODE_DUAL_OUT	(2 << 6)
+#define     EC_FLASH_FETCH_MODE_DUAL_IN_OUT	(3 << 6)
+
+#define EC_FLASH_MANUFACTURE_REG		EC_PAGE_REG(6, 0x3a)
+#define EC_FLASH_MEMORY_TYPE_REG		EC_PAGE_REG(6, 0x3b)
+#define EC_FLASH_CAPACITY_REG			EC_PAGE_REG(6, 0x3c)
+
+#define EC_MCU_SPEED_CTL_VSB_REG		EC_PAGE_REG(6, 0x40)
+#define   EC_FLASH_CLK_VSB_DIV_MASK		(3 << 0)
+#define     EC_FLASH_CLK_VSB_DIV_1		(0 << 0)
+#define     EC_FLASH_CLK_VSB_DIV_2		(1 << 0)
+#define     EC_FLASH_CLK_VSB_DIV_4		(2 << 0)
+#define     EC_FLASH_CLK_VSB_DIV_16		(3 << 0)
+#define   EC_FLASH_FETCH_MODE_VSB_MASK		(3 << 2)
+#define     EC_FLASH_FETCH_MODE_VSB_READ	(0 << 2)
+#define     EC_FLASH_FETCH_MODE_VSB_FAST_READ	(1 << 2)
+#define     EC_FLASH_FETCH_MODE_VSB_DUAL_OUT	(2 << 2)
+#define     EC_FLASH_FETCH_MODE_VSB_DUAL_IN_OUT	(3 << 2)
+#define   EC_MCU_SPEED_MCLK_VSB_MASK		(3 << 4)
+#define     EC_MCU_SPEED_MCLK_VSB_1MHZ		(0 << 4)
+#define     EC_MCU_SPEED_MCLK_VSB_4MHZ		(1 << 4)
+#define     EC_MCU_SPEED_MCLK_VSB_24MHZ		(2 << 4)
+#define     EC_MCU_SPEED_MCLK_VSB_48MHZ		(3 << 4)
+#define   EC_MCU_CACHE_VSB_EN			(1 << 6)
+
+#define EC_MCU_SPEED_CTL_VCC_REG		EC_PAGE_REG(6, 0x42)
+#define   EC_MCU_SPEED_MCLK_VCC_MASK		0x0f
+#define     EC_MCU_SPEED_MCLK_VCC_10KHZ		(0 << 0)
+#define     EC_MCU_SPEED_MCLK_VCC_160KHZ	(1 << 0)
+#define     EC_MCU_SPEED_MCLK_VCC_1MHZ		(2 << 0)
+#define     EC_MCU_SPEED_MCLK_VCC_4MHZ		(3 << 0)
+#define     EC_MCU_SPEED_MCLK_VCC_8MHZ		(4 << 0)
+#define     EC_MCU_SPEED_MCLK_VCC_16MHZ		(5 << 0)
+#define     EC_MCU_SPEED_MCLK_VCC_24MHZ		(6 << 0)
+#define     EC_MCU_SPEED_MCLK_VCC_48MHZ		(7 << 0)
+#define   EC_MCU_CACHE_VCC_EN			(1 << 6)
+#define   EC_MCU_SPEED_VCC_LOAD_CFG		(1 << 7)
+
+#define EC_FLASH_SPEED_CTL_VCC_REG		EC_PAGE_REG(6, 0x43)
+#define   EC_FLASH_CLK_VCC_DIV_MASK		(3 << 2)
+#define     EC_FLASH_CLK_VCC_DIV_1		(0 << 2)
+#define     EC_FLASH_CLK_VCC_DIV_2		(1 << 2)
+#define     EC_FLASH_CLK_VCC_DIV_4		(2 << 2)
+#define     EC_FLASH_CLK_VCC_DIV_16		(3 << 2)
+#define   EC_FLASH_FETCH_MODE_VCC_MASK		(3 << 4)
+#define     EC_FLASH_FETCH_MODE_VCC_READ	(0 << 4)
+#define     EC_FLASH_FETCH_MODE_VCC_FAST_READ	(1 << 4)
+#define     EC_FLASH_FETCH_MODE_VCC_DUAL_OUT	(2 << 4)
+#define     EC_FLASH_FETCH_MODE_VCC_DUAL_IN_OUT	(3 << 4)
+#define   EC_FLASH_SPEED_VCC_LOAD_CFG		(1 << 7)
+
+#define EC_FLASH_WREN_CMD_REG			EC_PAGE_REG(6, 0x47)
+
+#define EC_FLASH_WRITE_LOCK_REG			EC_PAGE_REG(6, 0x4f)
+#define   EC_FLASH_WRITE_LOCK			(1 << 0)
+#define   EC_FLASH_WRITE_LOCK_EN		(1 << 7)
+
+/* EC Page 8 - NCT6687D specific, not present in NCT6686D */
+
+#define FAN9_FAN10_MANUAL_EN_REG		EC_PAGE_REG(8, 0x0f)
+
+#define FAN_STEP_UP_TIME_REG(fan)		EC_PAGE_REG(8, 0x1a + ((fan) - 1))
+#define FAN_STEP_DOWN_TIME_REG(fan)		EC_PAGE_REG(8, 0x24 + ((fan) - 1))
+
+/* These are also included in macros in page 1, 10 and 12 */
+#define FAN9_FUNCTION_CTL_REG			EC_PAGE_REG(8, 0xe0)
+#define FAN10_FUNCTION_CTL_REG			EC_PAGE_REG(8, 0xe1)
+#define FAN9_MANUAL_OUTPUT_VAL_REG		EC_PAGE_REG(8, 0xe8)
+#define FAN10_MANUAL_OUTPUT_VAL_REG		EC_PAGE_REG(8, 0xe9)
+#define FAN9_DUTY_REG				EC_PAGE_REG(8, 0xf0)
+#define FAN10_DUTY_REG				EC_PAGE_REG(8, 0xf1)
+#define	FAN9OUT_CFG_REG				EC_PAGE_REG(8, 0xf4)
+#define	FAN10OUT_CFG_REG			EC_PAGE_REG(8, 0xf5)
+
+/* EC Page 9 - Fan Algorithm Function Control */
+
+#define FAN_ALG_FUNCTRL_REG(fan)		EC_PAGE_REG(9, 0x00 + ((fan) - 1))
+#define   FAN_ALG_FUNCTRL_DTS_UB_EN		(1 << 2)
+#define   FAN_ALG_FUNCTRL_DTS2_EN		(1 << 3)
+#define   FAN_ALG_FUNCTRL_DTS1_EN		(1 << 4)
+#define   FAN_ALG_FUNCTRL_TEMP_ERR		(1 << 5)
+#define   FAN_ALG_FUNCTRL_CRIT_TEMP_EN		(1 << 6)
+#define   FAN_ALG_FUNCTRL_ALG_EN		(1 << 7)
+
+/* Main temperature zone decision */
+#define FAN_MTZ_DCS_DATA_REG(x, fan)		EC_PAGE_REG(9, 0x10 + (x) + 4*((fan) - 1))
+/* Ambient temperature zone decision */
+#define FAN_ATZ_DCS_DATA_REG(x, fan)		EC_PAGE_REG(9, 0x50 + (x) 4*((fan) - 1))
+
+#define FAN_INITIAL_VALUE_REG(fan)		EC_PAGE_REG(9, 0x90 + ((fan) - 1))
+#define FAN_CRIT_TEMP_CFG_REG(fan)		EC_PAGE_REG(9, 0xA0 + ((fan) - 1))
+#define FAN_CRIT_TEMP_TOLERANCE_REG(fan)	EC_PAGE_REG(9, 0xB0 + ((fan) - 1))
+#define FAN_TEMP_ERR_DUTY_VAL_REG(fan)		EC_PAGE_REG(9, 0xC0 + ((fan) - 1))
+
+#define FAN_MODE_SEL_REG(fan)			EC_PAGE_REG(9, 0xD0 + ((fan) - 1))
+#define   FAN_MODE_SEL_MASK			0xf
+#define     FAN_MODE_MODE_MANUAL		(0 << 0)
+#define     FAN_MODE_THERMAL_CRUISE		(1 << 0)
+#define     FAN_MODE_SPEED_CRUISE		(2 << 0)
+#define     FAN_MODE_SMART_FAN_IV		(3 << 0)
+#define     FAN_MODE_PID_CONTROL		(4 << 0)
+
+/* EC Page 10 - Fan Function Control & Weight Matrix */
+
+#define FAN_MANUAL_EN_REG(fan) \
+	(((fan) > 8)	? EC_PAGE_REG(8, 0x0f) \
+			: EC_PAGE_REG(10, 0x00))
+#define   FAN_MANUAL_EN(fan)			(1 << (((fan) - 1) % 8))
+
+#define FAN_CFG_CTRL_REG			EC_PAGE_REG(10, 0x01)
+#define   FAN_CFG_DONE				(1 << 6)
+#define   FAN_CFG_REQUEST			(1 << 7)
+
+#define FAN_FUNCTION_CTRL(fan) \
+	(((fan) > 8)	? EC_PAGE_REG(8, 0xe0 + ((fan) - 9)) \
+			: EC_PAGE_REG(10, 0x08 + ((fan) - 1)))
+#define   FAN_FUN_MINDUTY_EN			(1 << 0)
+#define   FAN_FUN_MANUAL_OFFSET_EN		(1 << 1)
+#define   FAN_FUN_STARTUP_EN			(1 << 2)
+#define   FAN_FUN_AMBIENT_FLOOR_EN		(1 << 3)
+#define   FAN_FUN_MARKUP_TRACK_EN		(1 << 4)
+#define   FAN_FUN_FAST_TRACK_EN			(1 << 5)
+#define   FAN_FUN_SMART_TRACK_EN		(1 << 6)
+#define   FAN_FUN_UNIT_PWM_DUTY			(0 << 7)
+#define   FAN_FUN_UNIT_RPM			(1 << 7)
+
+/* The unit for below Ambient Floor register is 100 RPM */
+#define FAN_AMB_FLOOR_RPM_TO_REG(rpm)		((rpm) ? (rpm) / 100 : 1)
+#define FAN_AMB_FLOOR_MIN_OUT_START_REG(fan)	EC_PAGE_REG(10, 0x10 + ((fan) - 1))
+#define FAN_AMB_FLOOR_MIN_OUT_END_REG(fan)	EC_PAGE_REG(10, 0x18 + ((fan) - 1))
+#define FAN_AMB_FLOOR_MAX_OUT_REG(fan)		EC_PAGE_REG(10, 0x20 + ((fan) - 1))
+
+#define FAN_MANUAL_VALUE_REG(fan) \
+	(((fan) > 8)	? EC_PAGE_REG(8, 0xe8 + ((fan) - 9)) \
+			: EC_PAGE_REG(10, 0x28 + ((fan) - 1)))
+
+#define FAN_MANUAL_OFFSET_REG(fan)		EC_PAGE_REG(10, 0x30 + ((fan) - 1))
+#define FAN_MIN_DUTY_REG(fan)			EC_PAGE_REG(10, 0x38 + ((fan) - 1))
+#define FAN_STARTUP_DUTY_REG(fan)		EC_PAGE_REG(10, 0x40 + ((fan) - 1))
+
+/* Smart Tracking registers */
+
+#define FAN_LOW_RPM_SPEED_BOUNDARY_HI_REG	EC_PAGE_REG(10, 0x48)
+#define FAN_LOW_RPM_SPEED_BOUNDARY_LO_REG	EC_PAGE_REG(10, 0x49)
+#define FAN_HIGH_RPM_SPEED_BOUNDARY_HI_REG	EC_PAGE_REG(10, 0x4a)
+#define FAN_HIGH_RPM_SPEED_BOUNDARY_LO_REG	EC_PAGE_REG(10, 0x4b)
+
+#define FAN_LOW_RPM_TOLERANCE_REG		EC_PAGE_REG(10, 0x4c)
+#define FAN_MID_RPM_TOLERANCE_REG		EC_PAGE_REG(10, 0x4d)
+#define FAN_HIGH_RPM_TOLERANCE_REG		EC_PAGE_REG(10, 0x4e)
+
+#define FAN_TRACKING_STEP_REG			EC_PAGE_REG(10, 0x4f)
+#define   FAN_TRACK_STEP_DOWN_MASK		0x0f
+#define   FAN_TRACK_STEP_DOWN_SHIFT		0
+#define   FAN_TRACK_STEP_UP_MASK		0x0f
+#define   FAN_TRACK_STEP_UP_SHIFT		4
+
+#define FAN_FAST_TRACK_TEMP_BOUNDARY_REG	EC_PAGE_REG(10, 0x50)
+
+/* Below definitions are dividers for fast tracking weight registers */
+#define FAN_FAST_TRACK_WEIGHT_DIV_1		1
+#define FAN_FAST_TRACK_WEIGHT_DIV_2		2
+#define FAN_FAST_TRACK_WEIGHT_DIV_4		3
+#define FAN_FAST_TRACK_WEIGHT_DIV_8		4
+#define FAN_FAST_TRACK_WEIGHT_DIV_16		5
+#define FAN_FAST_TRACK_WEIGHT_DIV_32		6
+#define FAN_FAST_TRACK_WEIGHT_DIV_64		7
+
+/* Below definitions are shifts and masks for fast tracking weight registers */
+#define FAN_FAST_TRACK_WEIGHT_DOWN_MASK		0x07
+#define FAN_FAST_TRACK_WEIGHT_DOWN_SHIFT	0
+#define FAN_FAST_TRACK_WEIGHT_UP_MASK		0x07
+#define FAN_FAST_TRACK_WEIGHT_UP_SHIFT		4
+
+#define FAN_LOW_RPM_FAST_TRACK_WEIGHT_REG	EC_PAGE_REG(10, 0x51)
+#define FAN_MID_RPM_FAST_TRACK_WEIGHT_REG	EC_PAGE_REG(10, 0x52)
+#define FAN_HIGH_RPM_FAST_TRACK_WEIGHT_REG	EC_PAGE_REG(10, 0x53)
+
+/* Below definitions are shifts and masks for fast tracking duty step registers */
+#define   FAN_FAST_TRACK_DUTY_STEP_MASK		0x0f
+#define   FAN_FAST_TRACK_DUTY_STEP_SHIFT	0
+
+#define FAN_LOW_RPM_FAST_TRACK_DUTY_STEP_REG	EC_PAGE_REG(10, 0x54)
+#define FAN_MID_RPM_FAST_TRACK_DUTY_STEP_REG	EC_PAGE_REG(10, 0x55)
+#define FAN_HIGH_RPM_FAST_TRACK_DUTY_STEP_REG	EC_PAGE_REG(10, 0x56)
+
+#define FAN_MARKUP_TRACK_AMB_TEMP_BOUNDARY_REG	EC_PAGE_REG(10, 0x57)
+#define FAN_MARKUP_TRACK_WEIGHT_REG		EC_PAGE_REG(10, 0x58)
+#define   FAN_MARKUP_TRACK_WEIGHT_MASK		0x07
+#define   FAN_MARKUP_TRACK_WEIGHT_SHIFT		0
+
+/* Intel Sensor Based (DTS) Fan Control registers */
+
+#define ITL_TEMP_START_POINT_REG		EC_PAGE_REG(10, 0x59)
+#define ITL_TEMP_END_POINT_REG			EC_PAGE_REG(10, 0x5a)
+#define ITL_AMB_TEMP_START_POINT_REG(x)		EC_PAGE_REG(10, 0x5b + (x))
+
+#define ITL_RPM_START_POINT_HI_REG(x)		EC_PAGE_REG(10, 0x60 + 2*(x))
+#define ITL_RPM_START_POINT_LO_REG(x)		EC_PAGE_REG(10, 0x61 + 2*(x))
+#define ITL_RPM_END_POINT_HI_REG(x)		EC_PAGE_REG(10, 0x6a + 2*(x))
+#define ITL_RPM_END_POINT_LO_REG(x)		EC_PAGE_REG(10, 0x6a + 2*(x))
+#define ITL_RPM_MAX_SPEED_HI_REG		EC_PAGE_REG(10, 0x74)
+#define ITL_RPM_MAX_SPEED_LO_REG		EC_PAGE_REG(10, 0x75)
+
+#define ITL_DTS_CFG_REG				EC_PAGE_REG(10, 0x76)
+#define   ITL_DTS_PECI_AGENT_IDX_SEL_MASK	0x0f
+#define   ITL_DTS_PECI_AGENT_IDX_SEL_SHIFT	0
+#define   ITL_DTS_PECI_CFG_ADJUSTMENT		(1 << 7)
+
+#define AMBIENT_FLOOR_TEMP_START_POINT_REG	EC_PAGE_REG(10, 0x77)
+#define AMBIENT_FLOOR_TEMP_END_POINT_REG	EC_PAGE_REG(10, 0x78)
+
+/* DTS 2.0 sensor registers */
+
+#define DTS2_TARGET_MARGIN_REG			EC_PAGE_REG(10, 0x59)
+#define DTS2_TCONTROL_REG			EC_PAGE_REG(10, 0x5a)
+#define DTS2_TCONTROL_OFFSET_REG		EC_PAGE_REG(10, 0x5b)
+#define DTS2_TARGET_TOLERANCE_REG		EC_PAGE_REG(10, 0x5c)
+#define DTS2_DIVISOR_REG			EC_PAGE_REG(10, 0x5d)
+#define DTS2_STEP_SPEED_HI_REG			EC_PAGE_REG(10, 0x5e)
+#define DTS2_STEP_SPEED_LO_REG			EC_PAGE_REG(10, 0x5f)
+#define DTS2_MIN_SPEED_HI_REG			EC_PAGE_REG(10, 0x60)
+#define DTS2_MIN_SPEED_LO_REG			EC_PAGE_REG(10, 0x61)
+#define DTS2_DELAY_TIME_COUNTER_REG		EC_PAGE_REG(10, 0x62)
+
+/* Weight Matrix Configuration */
+
+#define FAN_ALG_ENGINE_WEIGHT_EN_REG(fan) \
+	(((fan) > 8)	? EC_PAGE_REG(10, 0xC1 + 8*((fan) - 9)) \
+			: EC_PAGE_REG(10, 0x80 + 8*((fan) - 1)))
+#define   FAN_ALG_ENGINE_WEIGHT_CHANNEL_EN(fan)	(1 << (((fan) - 1) % 8))
+
+#define FAN_ALG_ENGINE_WEIGHT_VAL_REG(fan) \
+	(((fan) > 8)	? EC_PAGE_REG(10, 0xC3 + ((fan) - 9)/2 + 8*((fan) - 9)) \
+			: EC_PAGE_REG(10, 0x84 + ((fan) - 1)/2 + 8*((fan) - 1)))
+#define   FAN_ALG_ENGINE_WEIGHT_MASK(fan)	(0xf << (4 * (((fan) - 1) % 2)))
+#define   FAN_ALG_ENGINE_WEIGHT_SHIFT(fan)	(4 * (((fan) - 1) % 2))
+
+/* EC Page 11 - Thermal Cruise, Speed Cruise, Smart Fan IV */
+
+#define FAN_PWM_PERCENT_TO_HEX(x)		((x) * 255 / 100)
+
+
+/* For x larger than 10, the registers are placed in page 12 */
+/* Thermal Cruise (TC) Registers */
+
+#define FAN_TC_TARGET_TEMP_TOLERANCE_REG(fan)	EC_PAGE_REG(11, 0x00 + 24*((fan) - 1))
+#define   FAN_TC_TEMP_TOLERANCE_MASK		0xf
+#define   FAN_TC_TEMP_TOLERANCE_SHIFT		0
+
+#define FAN_TC_TARGET_TEMP_REG(fan)		EC_PAGE_REG(11, 0x01 + 24*((fan) - 1))
+#define   FAN_TC_TARGET_TEMP_MASK		0x7f
+#define   FAN_TC_TARGET_TEMP_SHIFT		0
+#define   FAN_TC_KEEP_MIN_OUTPUT		(1 << 7)
+
+#define FAN_TC_STOP_VALUE_REG(fan)		EC_PAGE_REG(11, 0x02 + 24*((fan) - 1))
+
+#define FAN_TC_TIME_TO_SECONDS(x)		((x)*10)
+#define FAN_TC_STOP_TIME_REG(fan)		EC_PAGE_REG(11, 0x03 + 24*((fan) - 1))
+#define FAN_TC_STEP_DOWN_TIME_REG(fan)		EC_PAGE_REG(11, 0x04 + 24*((fan) - 1))
+#define FAN_TC_STEP_UP_TIME_REG(fan)		EC_PAGE_REG(11, 0x05 + 24*((fan) - 1))
+
+/* Speed Cruise (SC) Registers */
+
+#define FAN_SC_TARGET_RPM_HI_REG(fan)		EC_PAGE_REG(11, 0x00 + 24*((fan) - 1))
+#define FAN_SC_TARGET_RPM_LO_REG(fan)		EC_PAGE_REG(11, 0x01 + 24*((fan) - 1))
+#define FAN_SC_TARGET_RPM_TOLERANCE_HI_REG(fan)	EC_PAGE_REG(11, 0x02 + 24*((fan) - 1))
+#define FAN_SC_TARGET_RPM_TOLERANCE_LO_REG(fan)	EC_PAGE_REG(11, 0x03 + 24*((fan) - 1))
+
+#define FAN_SC_TIME_TO_SECONDS(x)		((x)*10)
+#define FAN_SC_STEP_DOWN_TIME_REG(fan)		EC_PAGE_REG(11, 0x04 + 24*((fan) - 1))
+#define FAN_SC_STEP_UP_TIME_REG(fan)		EC_PAGE_REG(11, 0x05 + 24*((fan) - 1))
+
+/* Smart Fan IV (SF4) Registers */
+
+#define FAN_SF4_TEMP_LVL_REG(fan, level)	EC_PAGE_REG(11, 0x00 + (level) + 24*((fan) - 1))
+#define FAN_SF4_PWM_RPM_LVL_HI_REG(fan, level)	EC_PAGE_REG(11, 0x07 + (level)*2 + 24*((fan) - 1))
+#define FAN_SF4_PWM_RPM_LVL_LO_REG(fan, level)	EC_PAGE_REG(11, 0x08 + (level)*2 + 24*((fan) - 1))
+#define FAN_SF4_TEMP_OFF_HYSTHERESIS_REG(fan)	EC_PAGE_REG(11, 0x15 + 24*((fan) - 1))
+#define FAN_SF4_TEMP_CUT_OFF_REG(fan)		EC_PAGE_REG(11, 0x16 + 24*((fan) - 1))
+#define FAN_SF4_TEMP_OFF_DELAY_REG(fan)		EC_PAGE_REG(11, 0x17 + 24*((fan) - 1))
+
+/* EC Page 12 - Fan Function Control */
+
+#define FAN_ENGINE_STS_REG			EC_PAGE_REG(12, 0xf8)
+#define   FAN_PECI_CFG_ADJUSTED			(1 << 1)
+#define   FAN_UNFINISHED_FLAG			(1 << 2)
+#define   FAN_CFG_PHASE				(1 << 3)
+#define   FAN_CFG_INVALID			(1 << 4)
+#define   FAN_CFG_CHECK_DONE			(1 << 5)
+#define   FAN_CFG_LOCK				(1 << 6)
+#define   FAN_DRIVE_BY_MOD_SEL			(0 << 7)
+#define   FAN_DRIVE_BY_DEFAULT_VAL		(1 << 7)
+
+#define FAN_LAST_ERROR_CODE_REG			EC_PAGE_REG(12, 0xf9)
+#define   FAN_NO_ERROR				0x00
+#define   FAN_ERR_MODE_SELECT			0x01
+#define   FAN_ERR_CRIT_TEMP_PROTECT		0x02
+#define   FAN_ERR_ITL_FAN_CONTROL		0x04
+#define   FAN_ERR_SMART_TRACKING		0x05
+#define   FAN_ERR_THERMAL_CRUISE		0x10
+#define   FAN_ERR_SPEED_CRUISE			0x20
+#define   FAN_ERR_SMART_FAN_IV			0x40
+#define   FAN_ERR_PID_CONTROL			0x50
+
+#define FAN_CHANNEL_EN_REG(fan) \
+	(((fan) > 8)	? EC_PAGE_REG(12, 0xfb) \
+			: EC_PAGE_REG(12, 0xfc))
+#define   FAN_CHANNEL_EN(fan)			(1 << (((fan) - 1) % 8))
+
+#define FAN_DEFAULT_VAL_REG			EC_PAGE_REG(12, 0xfd)
+
+extern uint16_t nct6687d_hwm_base;
+
+static __always_inline void hwm_reg_and_or(uint16_t page_reg, uint8_t and_mask, uint8_t or_mask)
+{
+	assert(nct6687d_hwm_base != 0);
+	nct6687d_ec_and_or_page(nct6687d_hwm_base, page_reg >> 8, page_reg & 0xff,
+				and_mask, or_mask);
+}
+
+static __always_inline void hwm_reg_set_bits(uint16_t page_reg, uint8_t bits)
+{
+	assert(nct6687d_hwm_base != 0);
+	nct6687d_ec_and_or_page(nct6687d_hwm_base, page_reg >> 8, page_reg & 0xff,
+				~bits, bits);
+}
+
+static __always_inline void hwm_reg_write(uint16_t page_reg, uint8_t value)
+{
+	assert(nct6687d_hwm_base != 0);
+	nct6687d_ec_write_page(nct6687d_hwm_base, page_reg >> 8, page_reg & 0xff, value);
+}
+
+static __always_inline uint8_t hwm_reg_read(uint16_t page_reg)
+{
+	assert(nct6687d_hwm_base != 0);
+	return nct6687d_ec_read_page(nct6687d_hwm_base, page_reg >> 8, page_reg & 0xff);
+}
+
+#endif /* SUPERIO_NUVOTON_NCT6687D_HWM_H */
diff --git a/src/superio/nuvoton/nct6687d/superio.c b/src/superio/nuvoton/nct6687d/superio.c
index c28092736f..7c3c496635 100644
--- a/src/superio/nuvoton/nct6687d/superio.c
+++ b/src/superio/nuvoton/nct6687d/superio.c
@@ -7,6 +7,7 @@
 #include <option.h>
 #include <superio/conf_mode.h>
 
+#include "chip.h"
 #include "nct6687d.h"
 
 #define MAINBOARD_POWER_OFF	0
@@ -23,6 +24,9 @@
 
 static void nct6687d_init(struct device *dev)
 {
+	const struct superio_nuvoton_nct6687d_config *conf;
+	const struct resource *res;
+
 	if (!dev->enabled)
 		return;
 
@@ -50,6 +54,12 @@ static void nct6687d_init(struct device *dev)
 		printk(BIOS_INFO, "set power %s after power fail\n",
 		       power_status ? "on" : "off");
 		break;
+	case NCT6687D_EC:
+		conf = dev->chip_info;
+		res = probe_resource(dev, PNP_IDX_IO0);
+		if (!conf || !res)
+			break;
+		nct6687d_hwm_init(res->base, conf);
 	}
 }
 

From a069c920f5aef07710ec121bf69511f8e209c277 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Micha=C5=82=20=C5=BBygowski?= <michal.zygowski@3mdeb.com>
Date: Sun, 10 Sep 2023 14:30:34 +0200
Subject: [PATCH 1282/3886] mb/msi/{ms7d25,ms7e06}: Mimic the vendor BIOS early
 SIO init
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Add early EC space configuration as done in the vendor BIOS.

Change-Id: I058560733e3f5bb8c6df7d5401efad87911d3f4a
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87477
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
---
 src/mainboard/msi/ms7d25/bootblock.c | 77 +++++++++++++++++++--------
 src/mainboard/msi/ms7e06/bootblock.c | 78 ++++++++++++++++++++--------
 2 files changed, 111 insertions(+), 44 deletions(-)

diff --git a/src/mainboard/msi/ms7d25/bootblock.c b/src/mainboard/msi/ms7d25/bootblock.c
index 110d6828a6..1b192eb8d1 100644
--- a/src/mainboard/msi/ms7d25/bootblock.c
+++ b/src/mainboard/msi/ms7d25/bootblock.c
@@ -4,42 +4,75 @@
 #include <device/pnp_ops.h>
 #include <superio/nuvoton/common/nuvoton.h>
 #include <superio/nuvoton/nct6687d/nct6687d.h>
+#include <superio/nuvoton/nct6687d/nct6687d_ec.h>
 
+#define GPIO_DEV PNP_DEV(0x4e, NCT6687D_GPIO_0_7)
 #define SERIAL_DEV PNP_DEV(0x4e, NCT6687D_SP1)
 #define POWER_DEV PNP_DEV(0x4e, NCT6687D_SLEEP_PWR)
+#define P80_UART_DEV PNP_DEV(0x4e, NCT6687D_P80_UART)
+#define EC_DEV PNP_DEV(0x4e, NCT6687D_EC)
+
+#define EC_IO_BASE 0xa20
 
 void bootblock_mainboard_early_init(void)
 {
 	/* Replicate vendor settings for multi-function pins in global config LDN */
-	nuvoton_pnp_enter_conf_state(SERIAL_DEV);
-	pnp_write_config(SERIAL_DEV, 0x13, 0xff); // IRQ8-15 level triggered, low
-	pnp_write_config(SERIAL_DEV, 0x14, 0xff); // IRQ0-7 level triggered, low
+	nuvoton_pnp_enter_conf_state(GPIO_DEV);
+	pnp_write_config(GPIO_DEV, 0x13, 0xff); // IRQ8-15 level triggered, low
+	pnp_write_config(GPIO_DEV, 0x14, 0xff); // IRQ0-7 level triggered, low
 
 	/* Below are multi-pin function */
-	pnp_write_config(SERIAL_DEV, 0x15, 0xaa);
-	pnp_write_config(SERIAL_DEV, 0x1a, 0x02);
-	pnp_write_config(SERIAL_DEV, 0x1b, 0x02);
-	pnp_write_config(SERIAL_DEV, 0x1d, 0x00);
-	pnp_write_config(SERIAL_DEV, 0x1e, 0xaa);
-	pnp_write_config(SERIAL_DEV, 0x1f, 0xb2);
-	pnp_write_config(SERIAL_DEV, 0x22, 0xbd);
-	pnp_write_config(SERIAL_DEV, 0x23, 0xdf);
-	pnp_write_config(SERIAL_DEV, 0x24, 0x39);
-	pnp_write_config(SERIAL_DEV, 0x25, 0xfe);
-	pnp_write_config(SERIAL_DEV, 0x26, 0x40);
-	pnp_write_config(SERIAL_DEV, 0x27, 0x77);
-	pnp_write_config(SERIAL_DEV, 0x28, 0x00);
-	pnp_write_config(SERIAL_DEV, 0x29, 0xfb);
-	pnp_write_config(SERIAL_DEV, 0x2a, 0x80);
-	pnp_write_config(SERIAL_DEV, 0x2b, 0x20);
-	pnp_write_config(SERIAL_DEV, 0x2c, 0x8a);
-	pnp_write_config(SERIAL_DEV, 0x2d, 0xaa);
+	pnp_write_config(GPIO_DEV, 0x15, 0xaa);
+	pnp_write_config(GPIO_DEV, 0x1a, 0x02);
+	pnp_write_config(GPIO_DEV, 0x1b, 0x02);
+	pnp_write_config(GPIO_DEV, 0x1d, 0x00);
+	pnp_write_config(GPIO_DEV, 0x1e, 0xaa);
+	pnp_write_config(GPIO_DEV, 0x1f, 0xb2);
+	pnp_write_config(GPIO_DEV, 0x22, 0xbd);
+	pnp_write_config(GPIO_DEV, 0x23, 0xdf);
+	pnp_write_config(GPIO_DEV, 0x24, 0x39);
+	pnp_write_config(GPIO_DEV, 0x25, 0xfe);
+	pnp_write_config(GPIO_DEV, 0x26, 0x40);
+	pnp_write_config(GPIO_DEV, 0x27, 0x77);
+	pnp_write_config(GPIO_DEV, 0x28, 0x00);
+	pnp_write_config(GPIO_DEV, 0x29, 0xfb);
+	pnp_write_config(GPIO_DEV, 0x2a, 0x80);
+	pnp_write_config(GPIO_DEV, 0x2b, 0x20);
+	pnp_write_config(GPIO_DEV, 0x2c, 0x8a);
+	pnp_write_config(GPIO_DEV, 0x2d, 0xaa);
+
+	/* Set GPIO 06 as high output */
+	pnp_write_config(GPIO_DEV, 0xF0, 0x00);
+	pnp_unset_and_set_config(GPIO_DEV, 0xe0, 0x40, 0x40);
+	pnp_unset_and_set_config(GPIO_DEV, 0xe3, 0x40, 0x00);
 
 	pnp_set_logical_device(POWER_DEV);
 	/* Configure pin for PECI */
 	pnp_write_config(POWER_DEV, 0xf3, 0x80);
 
-	nuvoton_pnp_exit_conf_state(POWER_DEV);
+	/* Configure power fault detection */
+	pnp_unset_and_set_config(POWER_DEV, 0xf0, 0xF2, 0x30);
+	pnp_unset_and_set_config(POWER_DEV, 0xf0, 0x03, 0x01);
+
+	/* Configure yellow and green LED */
+	pnp_write_config(POWER_DEV, 0xe7, 0x88);
+	pnp_write_config(POWER_DEV, 0xe8, 0x07);
+	pnp_set_logical_device(P80_UART_DEV);
+	pnp_write_config(P80_UART_DEV, 0xe5, 0x0f);
+
+	/* Configure EC */
+	pnp_set_logical_device(EC_DEV);
+	pnp_set_iobase(EC_DEV, PNP_IDX_IO0, EC_IO_BASE);
+	pnp_set_enable(EC_DEV, 1);
+
+	nct6687d_ec_and_or_page_ff(EC_IO_BASE, 6, 0x61, 0x3f, 0xC0);
+	nct6687d_ec_and_or_page(EC_IO_BASE, 0, 0x34, 0xc0, 0x00);
+	nct6687d_ec_and_or_page_ff(EC_IO_BASE, 8, 0x07, 0xff, 0x03);
+	nct6687d_ec_and_or_page(EC_IO_BASE, 0, 0x3d, 0xbf, 0x40);
+	nct6687d_ec_and_or_page_ff(EC_IO_BASE, 8, 0x00, 0xff, 0x01);
+	nct6687d_ec_and_or_page_ff(EC_IO_BASE, 0, 0x34, 0xfb, 0x04);
+
+	nuvoton_pnp_exit_conf_state(EC_DEV);
 
 	if (CONFIG(CONSOLE_SERIAL))
 		nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
diff --git a/src/mainboard/msi/ms7e06/bootblock.c b/src/mainboard/msi/ms7e06/bootblock.c
index 110d6828a6..55c2a88dec 100644
--- a/src/mainboard/msi/ms7e06/bootblock.c
+++ b/src/mainboard/msi/ms7e06/bootblock.c
@@ -4,42 +4,76 @@
 #include <device/pnp_ops.h>
 #include <superio/nuvoton/common/nuvoton.h>
 #include <superio/nuvoton/nct6687d/nct6687d.h>
+#include <superio/nuvoton/nct6687d/nct6687d_ec.h>
 
+#define GPIO_DEV PNP_DEV(0x4e, NCT6687D_GPIO_0_7)
 #define SERIAL_DEV PNP_DEV(0x4e, NCT6687D_SP1)
 #define POWER_DEV PNP_DEV(0x4e, NCT6687D_SLEEP_PWR)
+#define P80_UART_DEV PNP_DEV(0x4e, NCT6687D_P80_UART)
+#define EC_DEV PNP_DEV(0x4e, NCT6687D_EC)
+
+#define EC_IO_BASE 0xa20
 
 void bootblock_mainboard_early_init(void)
 {
 	/* Replicate vendor settings for multi-function pins in global config LDN */
-	nuvoton_pnp_enter_conf_state(SERIAL_DEV);
-	pnp_write_config(SERIAL_DEV, 0x13, 0xff); // IRQ8-15 level triggered, low
-	pnp_write_config(SERIAL_DEV, 0x14, 0xff); // IRQ0-7 level triggered, low
+	nuvoton_pnp_enter_conf_state(GPIO_DEV);
+	pnp_write_config(GPIO_DEV, 0x13, 0xff); // IRQ8-15 level triggered, low
+	pnp_write_config(GPIO_DEV, 0x14, 0xff); // IRQ0-7 level triggered, low
 
 	/* Below are multi-pin function */
-	pnp_write_config(SERIAL_DEV, 0x15, 0xaa);
-	pnp_write_config(SERIAL_DEV, 0x1a, 0x02);
-	pnp_write_config(SERIAL_DEV, 0x1b, 0x02);
-	pnp_write_config(SERIAL_DEV, 0x1d, 0x00);
-	pnp_write_config(SERIAL_DEV, 0x1e, 0xaa);
-	pnp_write_config(SERIAL_DEV, 0x1f, 0xb2);
-	pnp_write_config(SERIAL_DEV, 0x22, 0xbd);
-	pnp_write_config(SERIAL_DEV, 0x23, 0xdf);
-	pnp_write_config(SERIAL_DEV, 0x24, 0x39);
-	pnp_write_config(SERIAL_DEV, 0x25, 0xfe);
-	pnp_write_config(SERIAL_DEV, 0x26, 0x40);
-	pnp_write_config(SERIAL_DEV, 0x27, 0x77);
-	pnp_write_config(SERIAL_DEV, 0x28, 0x00);
-	pnp_write_config(SERIAL_DEV, 0x29, 0xfb);
-	pnp_write_config(SERIAL_DEV, 0x2a, 0x80);
-	pnp_write_config(SERIAL_DEV, 0x2b, 0x20);
-	pnp_write_config(SERIAL_DEV, 0x2c, 0x8a);
-	pnp_write_config(SERIAL_DEV, 0x2d, 0xaa);
+	pnp_write_config(GPIO_DEV, 0x15, 0xaa);
+	pnp_write_config(GPIO_DEV, 0x1a, 0x02);
+	pnp_write_config(GPIO_DEV, 0x1b, 0x02);
+	pnp_write_config(GPIO_DEV, 0x1d, 0x00);
+	pnp_write_config(GPIO_DEV, 0x1e, 0xaa);
+	pnp_write_config(GPIO_DEV, 0x1f, 0xb2);
+	pnp_write_config(GPIO_DEV, 0x22, 0xbd);
+	pnp_write_config(GPIO_DEV, 0x23, 0xdf);
+	pnp_write_config(GPIO_DEV, 0x24, 0x39);
+	pnp_write_config(GPIO_DEV, 0x25, 0xfe);
+	pnp_write_config(GPIO_DEV, 0x26, 0x40);
+	pnp_write_config(GPIO_DEV, 0x27, 0x77);
+	pnp_write_config(GPIO_DEV, 0x28, 0x00);
+	pnp_write_config(GPIO_DEV, 0x29, 0xfb);
+	pnp_write_config(GPIO_DEV, 0x2a, 0x80);
+	pnp_write_config(GPIO_DEV, 0x2b, 0x20);
+	pnp_write_config(GPIO_DEV, 0x2c, 0x8a);
+	pnp_write_config(GPIO_DEV, 0x2d, 0xaa);
+
+	/* Set GPIO 06 as high output */
+	pnp_write_config(GPIO_DEV, 0xF0, 0x00);
+	pnp_unset_and_set_config(GPIO_DEV, 0xe0, 0x40, 0x40);
+	pnp_unset_and_set_config(GPIO_DEV, 0xe3, 0x40, 0x00);
 
 	pnp_set_logical_device(POWER_DEV);
 	/* Configure pin for PECI */
 	pnp_write_config(POWER_DEV, 0xf3, 0x80);
 
-	nuvoton_pnp_exit_conf_state(POWER_DEV);
+	/* Configure power fault detection */
+	pnp_unset_and_set_config(POWER_DEV, 0xf0, 0xF2, 0x30);
+	pnp_unset_and_set_config(POWER_DEV, 0xf0, 0x03, 0x01);
+
+	/* Configure yellow and green LED */
+	pnp_write_config(POWER_DEV, 0xe7, 0x88);
+	pnp_write_config(POWER_DEV, 0xe8, 0x07);
+	pnp_set_logical_device(P80_UART_DEV);
+	pnp_write_config(P80_UART_DEV, 0xe5, 0x0f);
+
+	/* Configure EC */
+	pnp_set_logical_device(EC_DEV);
+	pnp_set_iobase(EC_DEV, PNP_IDX_IO0, EC_IO_BASE);
+	pnp_set_enable(EC_DEV, 1);
+
+	nct6687d_ec_and_or_page_ff(EC_IO_BASE, 6, 0x61, 0x3f, 0xC0);
+	nct6687d_ec_and_or_page(EC_IO_BASE, 0, 0x34, 0xc0, 0x00);
+	nct6687d_ec_and_or_page_ff(EC_IO_BASE, 8, 0x07, 0xff, 0x03);
+	nct6687d_ec_and_or_page(EC_IO_BASE, 0, 0x3d, 0xbf, 0x40);
+	nct6687d_ec_and_or_page_ff(EC_IO_BASE, 8, 0x00, 0xff, 0x01);
+	nct6687d_ec_and_or_page_ff(EC_IO_BASE, 0, 0x34, 0xfb, 0x04);
+
+
+	nuvoton_pnp_exit_conf_state(EC_DEV);
 
 	if (CONFIG(CONSOLE_SERIAL))
 		nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);

From a11eacc204690558e7268343ff9490397dbea8a7 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Micha=C5=82=20=C5=BBygowski?= <michal.zygowski@3mdeb.com>
Date: Fri, 22 Sep 2023 16:30:05 +0200
Subject: [PATCH 1283/3886] mb/msi/{ms7d25,ms7e06}/devicetree.cb: Add fan
 control config
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Add the default configuration for fans as seen in the OS with
superiotool.

Change-Id: Iba142c2ad683962ee2c007f387e87adc77352dad
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87478
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
---
 src/mainboard/msi/ms7d25/devicetree.cb | 157 +++++++++++++++++++++++++
 src/mainboard/msi/ms7e06/devicetree.cb | 157 +++++++++++++++++++++++++
 2 files changed, 314 insertions(+)

diff --git a/src/mainboard/msi/ms7d25/devicetree.cb b/src/mainboard/msi/ms7d25/devicetree.cb
index 73d871d346..7604776d44 100644
--- a/src/mainboard/msi/ms7d25/devicetree.cb
+++ b/src/mainboard/msi/ms7d25/devicetree.cb
@@ -213,6 +213,163 @@ chip soc/intel/alderlake
 		end
 		device ref pch_espi on
 			chip superio/nuvoton/nct6687d
+				register "sensors[0]" = "PECI_AGENT0_DOMAIN0"
+				register "sensors[1]" = "TD0P_CURRENT_MODE"
+				register "sensors[2]" = "THERMISTOR15"
+				register "sensors[3]" = "PCH_CHIP"
+				register "sensors[4]" = "THERMISTOR16"
+				register "sensors[5]" = "THERMISTOR0"
+				register "sensors[6]" = "THERMISTOR1"
+				register "sensors[16]" = "VIN0"
+				register "sensors[17]" = "VIN1"
+				register "sensors[18]" = "VIN2"
+				register "sensors[19]" = "VIN3"
+				register "sensors[20]" = "VIN4"
+				register "sensors[21]" = "VIN5"
+				register "sensors[22]" = "VIN6"
+				register "sensors[23]" = "VIN7"
+				register "sensors[24]" = "VCC"
+
+				register "smbus_sensor.sensor_idx" = "3"
+				register "smbus_sensor.sensor_en" = "true"
+				register "smbus_sensor.sensor_cmd" = "0x40"
+				register "smbus_sensor.sensor_addr" = "0x96"
+				register "smbus_sensor.baud_rate" = "BAUD_100K"
+				register "smbus_sensor.report_one_byte" = "true"
+				register "smbus_sensor.port_sel" = "1"
+
+				register "peci_speed" = "PECI_1200KHZ"
+
+				register "fan_default_val" = "60"
+
+				register "smart_tracking.speed_boundary_low" = "1500"
+				register "smart_tracking.speed_boundary_high" = "2500"
+				register "smart_tracking.rpm_tolerance_low" = "100"
+				register "smart_tracking.rpm_tolerance_mid" = "100"
+				register "smart_tracking.rpm_tolerance_high" = "100"
+				register "smart_tracking.step_up" = "1"
+				register "smart_tracking.step_down" = "1"
+
+				# CPU_FAN
+				register "FAN1.mode" = "FAN_SMART_FAN_IV"
+				register "FAN1.unit_sel" = "FAN_PWM"
+				register "FAN1.fanin_sel" = "TACH_PWM1"
+				register "FAN1.fanout_sel" = "TACH_PWM0"
+				register "FAN1.fan_alg_weight" = "10"
+				register "FAN1.smart_tracking_en" = "true"
+				register "FAN1.crit_temp" = "101"
+				register "FAN1.smart_fan.temp_src" = "{ 1, 0, 0, 0 }"
+				register "FAN1.smart_fan.temp_levels" = "{ 40, 55, 70, 85, 90, 95, 100 }"
+				register "FAN1.smart_fan.speed_levels" = "{ 13, 38, 63, 85, 90, 95, 100 }"
+				register "FAN1.smart_fan.cut_off_delay" = "5"
+				register "FAN1.smart_fan.step_up_time" = "1"
+				register "FAN1.smart_fan.step_down_time" = "1"
+
+				# PUMP_FAN
+				register "FAN2.mode" = "FAN_SMART_FAN_IV"
+				register "FAN2.unit_sel" = "FAN_PWM"
+				register "FAN2.fanin_sel" = "TACH_PWM3"
+				register "FAN2.fanout_sel" = "TACH_PWM2"
+				register "FAN2.fan_alg_weight" = "10"
+				register "FAN2.smart_tracking_en" = "true"
+				register "FAN2.crit_temp" = "101"
+				register "FAN2.smart_fan.temp_src" = "{ 1, 0, 0, 0 }"
+				register "FAN2.smart_fan.temp_levels" = "{ 32, 32, 32, 32, 32, 32, 32 }"
+				register "FAN2.smart_fan.speed_levels" = "{ 100, 100, 100, 100, 100, 100, 100 }"
+				register "FAN2.smart_fan.cut_off_delay" = "5"
+				register "FAN2.smart_fan.step_up_time" = "1"
+				register "FAN2.smart_fan.step_down_time" = "1"
+
+				# SYS_FAN1
+				register "FAN3.mode" = "FAN_SMART_FAN_IV"
+				register "FAN3.unit_sel" = "FAN_PWM"
+				register "FAN3.fanin_sel" = "TACH_PWM11"
+				register "FAN3.fanout_sel" = "TACH_PWM10"
+				register "FAN3.fan_alg_weight" = "10"
+				register "FAN3.smart_tracking_en" = "true"
+				register "FAN3.crit_temp" = "101"
+				register "FAN3.smart_fan.temp_src" = "{ 1, 0, 0, 0 }"
+				register "FAN3.smart_fan.temp_levels" = "{ 10, 20, 30, 40, 50, 60, 70 }"
+				register "FAN3.smart_fan.speed_levels" = "{ 60, 60, 60, 60, 60, 60, 60 }"
+				register "FAN3.smart_fan.cut_off_delay" = "5"
+				register "FAN3.smart_fan.step_up_time" = "1"
+				register "FAN3.smart_fan.step_down_time" = "1"
+
+				# SYS_FAN2
+				register "FAN4.mode" = "FAN_SMART_FAN_IV"
+				register "FAN4.unit_sel" = "FAN_PWM"
+				register "FAN4.fanin_sel" = "TACH_PWM13"
+				register "FAN4.fanout_sel" = "TACH_PWM12"
+				register "FAN4.fan_alg_weight" = "10"
+				register "FAN4.smart_tracking_en" = "true"
+				register "FAN4.crit_temp" = "101"
+				register "FAN4.smart_fan.temp_src" = "{ 1, 0, 0, 0 }"
+				register "FAN4.smart_fan.temp_levels" = "{ 10, 20, 30, 40, 50, 60, 70 }"
+				register "FAN4.smart_fan.speed_levels" = "{ 60, 60, 60, 60, 60, 60, 60 }"
+				register "FAN4.smart_fan.cut_off_delay" = "5"
+				register "FAN4.smart_fan.step_up_time" = "1"
+				register "FAN4.smart_fan.step_down_time" = "1"
+
+				# SYS_FAN3
+				register "FAN5.mode" = "FAN_SMART_FAN_IV"
+				register "FAN5.unit_sel" = "FAN_PWM"
+				register "FAN5.fanin_sel" = "TACH_PWM15"
+				register "FAN5.fanout_sel" = "TACH_PWM14"
+				register "FAN5.fan_alg_weight" = "10"
+				register "FAN5.smart_tracking_en" = "true"
+				register "FAN5.crit_temp" = "101"
+				register "FAN5.smart_fan.temp_src" = "{ 1, 0, 0, 0 }"
+				register "FAN5.smart_fan.temp_levels" = "{ 10, 20, 30, 40, 50, 60, 70 }"
+				register "FAN5.smart_fan.speed_levels" = "{ 60, 60, 60, 60, 60, 60, 60 }"
+				register "FAN5.smart_fan.cut_off_delay" = "5"
+				register "FAN5.smart_fan.step_up_time" = "1"
+				register "FAN5.smart_fan.step_down_time" = "1"
+
+				# SYS_FAN4
+				register "FAN6.mode" = "FAN_SMART_FAN_IV"
+				register "FAN6.unit_sel" = "FAN_PWM"
+				register "FAN6.fanin_sel" = "TACH_PWM17"
+				register "FAN6.fanout_sel" = "TACH_PWM16"
+				register "FAN6.fan_alg_weight" = "10"
+				register "FAN6.smart_tracking_en" = "true"
+				register "FAN6.crit_temp" = "101"
+				register "FAN6.smart_fan.temp_src" = "{ 1, 0, 0, 0 }"
+				register "FAN6.smart_fan.temp_levels" = "{ 10, 20, 30, 40, 50, 60, 70 }"
+				register "FAN6.smart_fan.speed_levels" = "{ 60, 60, 60, 60, 60, 60, 60 }"
+				register "FAN6.smart_fan.cut_off_delay" = "5"
+				register "FAN6.smart_fan.step_up_time" = "1"
+				register "FAN6.smart_fan.step_down_time" = "1"
+
+				# SYS_FAN5
+				register "FAN7.mode" = "FAN_SMART_FAN_IV"
+				register "FAN7.unit_sel" = "FAN_PWM"
+				register "FAN7.fanin_sel" = "TACH_PWM19"
+				register "FAN7.fanout_sel" = "TACH_PWM18"
+				register "FAN7.fan_alg_weight" = "10"
+				register "FAN7.smart_tracking_en" = "true"
+				register "FAN7.crit_temp" = "101"
+				register "FAN7.smart_fan.temp_src" = "{ 1, 0, 0, 0 }"
+				register "FAN7.smart_fan.temp_levels" = "{ 10, 20, 30, 40, 50, 60, 70 }"
+				register "FAN7.smart_fan.speed_levels" = "{ 60, 60, 60, 60, 60, 60, 60 }"
+				register "FAN7.smart_fan.cut_off_delay" = "5"
+				register "FAN7.smart_fan.step_up_time" = "1"
+				register "FAN7.smart_fan.step_down_time" = "1"
+
+				# SYS_FAN6
+				register "FAN8.mode" = "FAN_SMART_FAN_IV"
+				register "FAN8.unit_sel" = "FAN_PWM"
+				register "FAN8.fanin_sel" = "TACH_PWM6"
+				register "FAN8.fanout_sel" = "TACH_PWM4"
+				register "FAN8.fan_alg_weight" = "10"
+				register "FAN8.smart_tracking_en" = "true"
+				register "FAN8.crit_temp" = "101"
+				register "FAN8.smart_fan.temp_src" = "{ 1, 0, 0, 0 }"
+				register "FAN8.smart_fan.temp_levels" = "{ 10, 20, 30, 40, 50, 60, 70 }"
+				register "FAN8.smart_fan.speed_levels" = "{ 60, 60, 60, 60, 60, 60, 60 }"
+				register "FAN8.smart_fan.cut_off_delay" = "5"
+				register "FAN8.smart_fan.step_up_time" = "1"
+				register "FAN8.smart_fan.step_down_time" = "1"
+
 				device pnp 4e.1 off end		# Parallel port
 				device pnp 4e.2 on		# COM1
 					io 0x60 = 0x3f8
diff --git a/src/mainboard/msi/ms7e06/devicetree.cb b/src/mainboard/msi/ms7e06/devicetree.cb
index eb179885c1..5885f2ab27 100644
--- a/src/mainboard/msi/ms7e06/devicetree.cb
+++ b/src/mainboard/msi/ms7e06/devicetree.cb
@@ -203,6 +203,163 @@ chip soc/intel/alderlake
 			register "gen4_dec" = "0x000c0081"
 
 			chip superio/nuvoton/nct6687d
+				register "sensors[0]" = "PECI_AGENT0_DOMAIN0"
+				register "sensors[1]" = "TD0P_CURRENT_MODE"
+				register "sensors[2]" = "THERMISTOR15"
+				register "sensors[3]" = "PCH_CHIP"
+				register "sensors[4]" = "THERMISTOR16"
+				register "sensors[5]" = "THERMISTOR0"
+				register "sensors[6]" = "THERMISTOR1"
+				register "sensors[16]" = "VIN0"
+				register "sensors[17]" = "VIN1"
+				register "sensors[18]" = "VIN2"
+				register "sensors[19]" = "VIN3"
+				register "sensors[20]" = "VIN4"
+				register "sensors[21]" = "VIN5"
+				register "sensors[22]" = "VIN6"
+				register "sensors[23]" = "VIN7"
+				register "sensors[24]" = "VCC"
+
+				register "smbus_sensor.sensor_idx" = "3"
+				register "smbus_sensor.sensor_en" = "true"
+				register "smbus_sensor.sensor_cmd" = "0x40"
+				register "smbus_sensor.sensor_addr" = "0x96"
+				register "smbus_sensor.baud_rate" = "BAUD_100K"
+				register "smbus_sensor.report_one_byte" = "true"
+				register "smbus_sensor.port_sel" = "1"
+
+				register "peci_speed" = "PECI_1200KHZ"
+
+				register "fan_default_val" = "60"
+
+				register "smart_tracking.speed_boundary_low" = "1500"
+				register "smart_tracking.speed_boundary_high" = "2500"
+				register "smart_tracking.rpm_tolerance_low" = "100"
+				register "smart_tracking.rpm_tolerance_mid" = "100"
+				register "smart_tracking.rpm_tolerance_high" = "100"
+				register "smart_tracking.step_up" = "1"
+				register "smart_tracking.step_down" = "1"
+
+				# CPU_FAN
+				register "FAN1.mode" = "FAN_SMART_FAN_IV"
+				register "FAN1.unit_sel" = "FAN_PWM"
+				register "FAN1.fanin_sel" = "TACH_PWM1"
+				register "FAN1.fanout_sel" = "TACH_PWM0"
+				register "FAN1.fan_alg_weight" = "10"
+				register "FAN1.smart_tracking_en" = "true"
+				register "FAN1.crit_temp" = "101"
+				register "FAN1.smart_fan.temp_src" = "{ 1, 0, 0, 0 }"
+				register "FAN1.smart_fan.temp_levels" = "{ 40, 55, 70, 85, 90, 95, 100 }"
+				register "FAN1.smart_fan.speed_levels" = "{ 13, 38, 63, 85, 90, 95, 100 }"
+				register "FAN1.smart_fan.cut_off_delay" = "5"
+				register "FAN1.smart_fan.step_up_time" = "1"
+				register "FAN1.smart_fan.step_down_time" = "1"
+
+				# PUMP_FAN
+				register "FAN2.mode" = "FAN_SMART_FAN_IV"
+				register "FAN2.unit_sel" = "FAN_PWM"
+				register "FAN2.fanin_sel" = "TACH_PWM3"
+				register "FAN2.fanout_sel" = "TACH_PWM2"
+				register "FAN2.fan_alg_weight" = "10"
+				register "FAN2.smart_tracking_en" = "true"
+				register "FAN2.crit_temp" = "101"
+				register "FAN2.smart_fan.temp_src" = "{ 1, 0, 0, 0 }"
+				register "FAN2.smart_fan.temp_levels" = "{ 32, 32, 32, 32, 32, 32, 32 }"
+				register "FAN2.smart_fan.speed_levels" = "{ 100, 100, 100, 100, 100, 100, 100 }"
+				register "FAN2.smart_fan.cut_off_delay" = "5"
+				register "FAN2.smart_fan.step_up_time" = "1"
+				register "FAN2.smart_fan.step_down_time" = "1"
+
+				# SYS_FAN1
+				register "FAN3.mode" = "FAN_SMART_FAN_IV"
+				register "FAN3.unit_sel" = "FAN_PWM"
+				register "FAN3.fanin_sel" = "TACH_PWM11"
+				register "FAN3.fanout_sel" = "TACH_PWM10"
+				register "FAN3.fan_alg_weight" = "10"
+				register "FAN3.smart_tracking_en" = "true"
+				register "FAN3.crit_temp" = "101"
+				register "FAN3.smart_fan.temp_src" = "{ 1, 0, 0, 0 }"
+				register "FAN3.smart_fan.temp_levels" = "{ 10, 20, 30, 40, 50, 60, 70 }"
+				register "FAN3.smart_fan.speed_levels" = "{ 60, 60, 60, 60, 60, 60, 60 }"
+				register "FAN3.smart_fan.cut_off_delay" = "5"
+				register "FAN3.smart_fan.step_up_time" = "1"
+				register "FAN3.smart_fan.step_down_time" = "1"
+
+				# SYS_FAN2
+				register "FAN4.mode" = "FAN_SMART_FAN_IV"
+				register "FAN4.unit_sel" = "FAN_PWM"
+				register "FAN4.fanin_sel" = "TACH_PWM13"
+				register "FAN4.fanout_sel" = "TACH_PWM12"
+				register "FAN4.fan_alg_weight" = "10"
+				register "FAN4.smart_tracking_en" = "true"
+				register "FAN4.crit_temp" = "101"
+				register "FAN4.smart_fan.temp_src" = "{ 1, 0, 0, 0 }"
+				register "FAN4.smart_fan.temp_levels" = "{ 10, 20, 30, 40, 50, 60, 70 }"
+				register "FAN4.smart_fan.speed_levels" = "{ 60, 60, 60, 60, 60, 60, 60 }"
+				register "FAN4.smart_fan.cut_off_delay" = "5"
+				register "FAN4.smart_fan.step_up_time" = "1"
+				register "FAN4.smart_fan.step_down_time" = "1"
+
+				# SYS_FAN3
+				register "FAN5.mode" = "FAN_SMART_FAN_IV"
+				register "FAN5.unit_sel" = "FAN_PWM"
+				register "FAN5.fanin_sel" = "TACH_PWM15"
+				register "FAN5.fanout_sel" = "TACH_PWM14"
+				register "FAN5.fan_alg_weight" = "10"
+				register "FAN5.smart_tracking_en" = "true"
+				register "FAN5.crit_temp" = "101"
+				register "FAN5.smart_fan.temp_src" = "{ 1, 0, 0, 0 }"
+				register "FAN5.smart_fan.temp_levels" = "{ 10, 20, 30, 40, 50, 60, 70 }"
+				register "FAN5.smart_fan.speed_levels" = "{ 60, 60, 60, 60, 60, 60, 60 }"
+				register "FAN5.smart_fan.cut_off_delay" = "5"
+				register "FAN5.smart_fan.step_up_time" = "1"
+				register "FAN5.smart_fan.step_down_time" = "1"
+
+				# SYS_FAN4
+				register "FAN6.mode" = "FAN_SMART_FAN_IV"
+				register "FAN6.unit_sel" = "FAN_PWM"
+				register "FAN6.fanin_sel" = "TACH_PWM17"
+				register "FAN6.fanout_sel" = "TACH_PWM16"
+				register "FAN6.fan_alg_weight" = "10"
+				register "FAN6.smart_tracking_en" = "true"
+				register "FAN6.crit_temp" = "101"
+				register "FAN6.smart_fan.temp_src" = "{ 1, 0, 0, 0 }"
+				register "FAN6.smart_fan.temp_levels" = "{ 10, 20, 30, 40, 50, 60, 70 }"
+				register "FAN6.smart_fan.speed_levels" = "{ 60, 60, 60, 60, 60, 60, 60 }"
+				register "FAN6.smart_fan.cut_off_delay" = "5"
+				register "FAN6.smart_fan.step_up_time" = "1"
+				register "FAN6.smart_fan.step_down_time" = "1"
+
+				# SYS_FAN5
+				register "FAN7.mode" = "FAN_SMART_FAN_IV"
+				register "FAN7.unit_sel" = "FAN_PWM"
+				register "FAN7.fanin_sel" = "TACH_PWM19"
+				register "FAN7.fanout_sel" = "TACH_PWM18"
+				register "FAN7.fan_alg_weight" = "10"
+				register "FAN7.smart_tracking_en" = "true"
+				register "FAN7.crit_temp" = "101"
+				register "FAN7.smart_fan.temp_src" = "{ 1, 0, 0, 0 }"
+				register "FAN7.smart_fan.temp_levels" = "{ 10, 20, 30, 40, 50, 60, 70 }"
+				register "FAN7.smart_fan.speed_levels" = "{ 60, 60, 60, 60, 60, 60, 60 }"
+				register "FAN7.smart_fan.cut_off_delay" = "5"
+				register "FAN7.smart_fan.step_up_time" = "1"
+				register "FAN7.smart_fan.step_down_time" = "1"
+
+				# SYS_FAN6
+				register "FAN8.mode" = "FAN_SMART_FAN_IV"
+				register "FAN8.unit_sel" = "FAN_PWM"
+				register "FAN8.fanin_sel" = "TACH_PWM6"
+				register "FAN8.fanout_sel" = "TACH_PWM4"
+				register "FAN8.fan_alg_weight" = "10"
+				register "FAN8.smart_tracking_en" = "true"
+				register "FAN8.crit_temp" = "101"
+				register "FAN8.smart_fan.temp_src" = "{ 1, 0, 0, 0 }"
+				register "FAN8.smart_fan.temp_levels" = "{ 10, 20, 30, 40, 50, 60, 70 }"
+				register "FAN8.smart_fan.speed_levels" = "{ 60, 60, 60, 60, 60, 60, 60 }"
+				register "FAN8.smart_fan.cut_off_delay" = "5"
+				register "FAN8.smart_fan.step_up_time" = "1"
+				register "FAN8.smart_fan.step_down_time" = "1"
+
 				device pnp 4e.1 off end		# Parallel port
 				device pnp 4e.2 on		# COM1
 					io 0x60 = 0x3f8

From 4199351c1b29fad6c8b1d4ed916de3aa44c03924 Mon Sep 17 00:00:00 2001
From: "Jakub \"Kuba\" Czapiga" <czapiga@google.com>
Date: Wed, 11 Jun 2025 10:19:33 +0000
Subject: [PATCH 1284/3886] Revert "libpayload: arm64: Reduce DMA allocator
 space to 1MB"
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

This reverts commit aedc177f000a3fd62c75f555c116ad956443ab1e.

Reason for revert: With this change depthchange clears parts of cbmem on Google/Corsola when display is cleared.

BUG=b:424107889

Change-Id: I6cc21693ddcaed59e41e333b773e0baeb29d3b40
Signed-off-by: Bartłomiej Grzesik <bgrzesik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88051
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
---
 payloads/libpayload/include/arm64/arch/mmu.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/payloads/libpayload/include/arm64/arch/mmu.h b/payloads/libpayload/include/arm64/arch/mmu.h
index 9ed951d336..2b1e9e120c 100644
--- a/payloads/libpayload/include/arm64/arch/mmu.h
+++ b/payloads/libpayload/include/arm64/arch/mmu.h
@@ -161,7 +161,7 @@ extern char _start[], _end[];
 #define TCR_TBI_USED               (0x0 << TCR_TBI_SHIFT)
 #define TCR_TBI_IGNORED            (0x1 << TCR_TBI_SHIFT)
 
-#define DMA_DEFAULT_SIZE           (1 * MiB)
+#define DMA_DEFAULT_SIZE           (32 * MiB)
 #define TTB_DEFAULT_SIZE           0x100000
 
 #define MB_SIZE			   (1UL << 20)

From b9754131a689313011314ac897ea8586054f7f99 Mon Sep 17 00:00:00 2001
From: "P, Usha" <usha.p@intel.com>
Date: Mon, 2 Jun 2025 10:49:29 +0530
Subject: [PATCH 1285/3886] mb/google/ocelot/var/ocelot: Update initial
 overridetree settings

Update override devicetree based on schematic_1433518.

BUG=b:394208231
TEST=Build Ocelot and verify it compiles  without any error.

Change-Id: I88a3729ff2a61a383a4715a335062310cba01f24
Signed-off-by: P, Usha <usha.p@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87910
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
---
 .../ocelot/variants/ocelot/overridetree.cb    | 164 +++++++-----------
 1 file changed, 59 insertions(+), 105 deletions(-)

diff --git a/src/mainboard/google/ocelot/variants/ocelot/overridetree.cb b/src/mainboard/google/ocelot/variants/ocelot/overridetree.cb
index e692c080c0..31959f5a27 100644
--- a/src/mainboard/google/ocelot/variants/ocelot/overridetree.cb
+++ b/src/mainboard/google/ocelot/variants/ocelot/overridetree.cb
@@ -61,32 +61,33 @@ end
 
 chip soc/intel/pantherlake
 
-	register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC_SKIP)" # USB2_C0
-	register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC_SKIP)" # USB2_C1
-	register "usb2_ports[2]" = "USB2_PORT_TYPE_C(OC_SKIP)" # USB2_C2
-	register "usb2_ports[3]" = "USB2_PORT_TYPE_C(OC_SKIP)" # USB2_C3
-	register "usb2_ports[4]" = "USB2_PORT_MID(OC0)" # Type-A Port A0
-	register "usb2_ports[5]" = "USB2_PORT_MID(OC0)" # Type-A Port A1 / WWAN with rework
-	register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # Discrete Bluetooth
+	register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Type C port - various configurations - TCP0
+	register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Type C port - various configurations - TCP1
+	register "usb2_ports[2]" = "USB2_PORT_MID(OC0)" # USB3.2 Gen2x1 Type-A Port - TAP1 Vertical CONN
+	register "usb2_ports[3]" = "USB2_PORT_MID(OC0)" # USB3.2 Gen2x1 Type-A Port - TAP2 (redriver topology)
+	register "usb2_ports[4]" = "USB2_PORT_MID(OC0)" # 2x5 USB2 HDR
+	register "usb2_ports[5]" = "USB2_PORT_MID(OC0)" # 2x5 USB2 HDR
+	register "usb2_ports[6]" = "USB2_PORT_MID(OC0)" # FPS
+	register "usb2_ports[7]" = "USB2_PORT_MID(OC0)" # M.2 WLAN
 
-	register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)" # USB3.2 x1 Type-A Con #1
-	register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC0)" # USB3.2 x1 Type-A Con #2 / M.2 WWAN with rework
+	register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)" # USB 3.2 Gen2 x1 Type-A Con - # 1
+	register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC0)" # USB 3.2 Gen2 x1 Type-A Con - # 2 (redriver topology)
+	#register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC0)" # TCSS Module - Type-A over TCP module
 
-	register "tcss_ports[0]" = "TCSS_PORT_DEFAULT(OC_SKIP)"
+	register "tcss_ports[0]" = "TCSS_PORT_DEFAULT(OC0)"
 	register "tcss_ports[1]" = "TCSS_PORT_DEFAULT(OC_SKIP)"
-	register "tcss_ports[2]" = "TCSS_PORT_DEFAULT(OC_SKIP)"
-	register "tcss_ports[3]" = "TCSS_PORT_DEFAULT(OC_SKIP)"
 
 	register "tcss_cap_policy[0]" = "TCSS_TYPE_C_PORT_FULL_FUN"
 	register "tcss_cap_policy[1]" = "TCSS_TYPE_C_PORT_FULL_FUN"
-	register "tcss_cap_policy[2]" = "TCSS_TYPE_C_PORT_FULL_FUN"
-	register "tcss_cap_policy[3]" = "TCSS_TYPE_C_PORT_FULL_FUN"
 
-	# Enable EDP in PortA
+
+	# Enable EDP in PortA & HDMI in Port B
 	register "ddi_port_A_config" = "1"
+	register "ddi_port_B_config" = "1"
 	register "ddi_ports_config" = "{
-                [DDI_PORT_A] = DDI_ENABLE_HPD,
-        }"
+		[DDI_PORT_A] = DDI_ENABLE_HPD,
+		[DDI_PORT_B] = DDI_ENABLE_HPD,
+	}"
 
 	register "serial_io_i2c_mode" = "{
 		[PchSerialIoIndexI2C0]  = PchSerialIoPci,
@@ -107,10 +108,7 @@ chip soc/intel/pantherlake
 	#+-------------------+---------------------------+
 	#| Field             |  Value                    |
 	#+-------------------+---------------------------+
-	#| I2C1              | Camera(CRD1)              |
-	#| I2C2              | Camera(CRD2)              |
-	#| I2C3              | Audio, TPM(cr50)          |
-	#| I2C4              | Touchscreen               |
+	#| I2C1              | TPM(cr50)                 |
 	#| I2C5              | Touchpad                  |
 	#+-------------------+---------------------------+
 	register "common_soc_config" = "{
@@ -118,12 +116,12 @@ chip soc/intel/pantherlake
 		.chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT,
 		.i2c[1] = {
 			.speed = I2C_SPEED_FAST,
+			.early_init = 1,
 		},
 		.i2c[2] = {
 			.speed = I2C_SPEED_FAST,
 		},
 		.i2c[3] = {
-			.early_init = 1,
 			.speed = I2C_SPEED_FAST,
 		},
 		.i2c[4] = {
@@ -412,31 +410,31 @@ chip soc/intel/pantherlake
 						device ref usb2_port2 on end
 					end
 					chip drivers/usb/acpi
-						register "desc" = ""USB2 Type-C Port C2""
-						register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
+						register "desc" = ""USB2 Type-A Port 1""
+						register "type" = "UPC_TYPE_A"
 						register "group" = "ACPI_PLD_GROUP(3, 1)"
 						device ref usb2_port3 on end
 					end
 					chip drivers/usb/acpi
-						register "desc" = ""USB2 Type-C Port C3""
-						register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
+						register "desc" = ""USB2 Type-A Port 2""
+						register "type" = "UPC_TYPE_A"
 						register "group" = "ACPI_PLD_GROUP(4, 1)"
 						device ref usb2_port4 on end
 					end
 					chip drivers/usb/acpi
-						register "desc" = ""USB2 Type-A Port 1""
+						register "desc" = ""USB2 Type-A Port 3""
 						register "type" = "UPC_TYPE_A"
 						register "group" = "ACPI_PLD_GROUP(5, 1)"
 						device ref usb2_port5 on end
 					end
 					chip drivers/usb/acpi
-						register "desc" = ""USB2 Type-A Port 2""
+						register "desc" = ""USB2 Type-A Port 4""
 						register "type" = "UPC_TYPE_A"
 						register "group" = "ACPI_PLD_GROUP(6, 1)"
 						device ref usb2_port6 on end
 					end
 					chip drivers/usb/acpi
-						register "desc" = ""USB2 Type-A Port 3""
+						register "desc" = ""USB2 Type-A Port 5""
 						register "type" = "UPC_TYPE_A"
 						register "group" = "ACPI_PLD_GROUP(7, 1)"
 						device ref usb2_port7 on end
@@ -444,7 +442,7 @@ chip soc/intel/pantherlake
 					chip drivers/usb/acpi
 						register "desc" = ""USB2 Bluetooth""
 						register "type" = "UPC_TYPE_INTERNAL"
-						register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A16)"
+						register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B09)"
 						device ref usb2_port8 on
 							probe WIFI WIFI_PCIE_6
 							probe WIFI WIFI_PCIE_7
@@ -471,86 +469,41 @@ chip soc/intel/pantherlake
 			probe STORAGE STORAGE_UNKNOWN
 		end
 
-		device ref pcie_rp2 on
-			probe CELLULAR CELLULAR_PCIE
-			register "pcie_rp[PCIE_RP(2)]" = "{
-				.clk_src = 5,
-				.clk_req = 5,
-				.flags = PCIE_RP_CLK_REQ_DETECT | PCIE_RP_LTR | PCIE_RP_AER,
-			}"
-			chip soc/intel/common/block/pcie/rtd3
-				register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D03)"
-				register "reset_off_delay_ms" = "20"
-				register "srcclk_pin" = "5"
-				register "ext_pm_support" = "ACPI_PCIE_RP_EMIT_ALL"
-				register "skip_on_off_support" = "true"
-				register "use_rp_mutex" = "true"
-				device generic 0 alias rp2_rtd3 on end
-			end
-			chip drivers/wwan/fm
-				register "fcpo_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A09)"
-				register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B20)"
-				register "perst_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D03)"
-				register "wake_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_E02)"
-				register "add_acpi_dma_property" = "true"
-				use rp2_rtd3 as rtd3dev
-				device generic 0 on end
-			end
-		end # WWAN
-		device ref pcie_rp3 on
-			probe SD SD_GENSYS
-			probe SD SD_BAYHUB
-			# Enable PCH PCIE x1 slot using CLK 3
-			register "pcie_rp[PCIE_RP(3)]" = "{
-				.clk_src = 2,
-				.clk_req = 2,
-				.flags = PCIE_RP_CLK_REQ_DETECT | PCIE_RP_LTR | PCIE_RP_AER,
-			}"
-			chip soc/intel/common/block/pcie/rtd3
-				register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A08)"
-				register "enable_delay_ms" = "100"
-				register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D19)"
-				register "reset_delay_ms" = "20"
-				register "srcclk_pin" = "2"
-				device generic 0 on end
-			end
-		end # PCIE x1 slot
-		device ref pcie_rp4 on
-			probe WIFI WIFI_PCIE_6
-			probe WIFI WIFI_PCIE_7
-			register "pcie_rp[PCH_RP(4)]" = "{
-				.clk_src = 4,
-				.clk_req = 4,
-				.flags = PCIE_RP_CLK_REQ_DETECT | PCIE_RP_LTR | PCIE_RP_AER,
-			}"
-			chip soc/intel/common/block/pcie/rtd3
-				register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A11)"
-				register "srcclk_pin" = "4"
-				device pci 00.0 on end
-			end
-			chip drivers/wifi/generic
-				register "add_acpi_dma_property" = "true"
-				register "wake" = "GPE0_DW0_12" # GPP_A12
-				use usb2_port7 as bluetooth_companion
-				device pci 00.0 on end
-			end
-		end # discrete WLAN
-		device ref pcie_rp5 on
+		device ref pcie_rp1 on
 			probe STORAGE STORAGE_NVME_GEN4
 			probe STORAGE STORAGE_UNKNOWN
-			register "pcie_rp[PCIE_RP(5)]" = "{
-			.clk_src = 6,
-			.clk_req = 6,
+			register "pcie_rp[PCIE_RP(1)]" = "{
+			.clk_src = 3,
+			.clk_req = 3,
 			.flags = PCIE_RP_CLK_REQ_DETECT | PCIE_RP_LTR | PCIE_RP_AER,
 			}"
 			chip soc/intel/common/block/pcie/rtd3
 				register "is_storage" = "true"
 				register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_H18)"
 				register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A08)"
-				register "srcclk_pin" = "6"
+				register "srcclk_pin" = "3"
 				device generic 0 on end
 			end
 		end # Gen4 M.2 SSD
+
+		device ref pcie_rp5 on
+			probe SD SD_GENSYS
+			probe SD SD_BAYHUB
+			register "pcie_rp[PCIE_RP(5)]" = "{
+			.clk_src = 2,
+			.clk_req = 2,
+			.flags = PCIE_RP_CLK_REQ_DETECT | PCIE_RP_LTR | PCIE_RP_AER,
+			}"
+			chip soc/intel/common/block/pcie/rtd3
+				register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_F10)"
+				register "enable_delay_ms" = "100"
+				register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_E03)"
+				register "reset_delay_ms" = "20"
+				register "srcclk_pin" = "2"
+				device generic 0 on end
+			end
+		end # PCIE x1 slot
+
 		device ref cnvi_wifi on
 			probe WIFI WIFI_CNVI_6
 			probe WIFI WIFI_CNVI_7
@@ -569,16 +522,17 @@ chip soc/intel/pantherlake
 		end
 
 		# NOTE: i2c0 is function 0; hence it needs to be enabled when any of i2c1-5 is enabled.
-		# TPM device is under i2c3. Therefore, i2c0 needs to be enabled anyways.
+		# TPM device is under i2c1. Therefore, i2c0 needs to be enabled anyways.
 		device ref i2c0 on end
-		device ref i2c1 on end
-		device ref i2c2 on end
-		device ref i2c3 on
+		device ref i2c1 on
 			chip drivers/i2c/tpm
 				register "hid" = ""GOOG0005""
-				register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_D15_IRQ)"
+				register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_B17_IRQ)"
 				device i2c 50 on end
 			end
+		end
+		device ref i2c2 on end
+		device ref i2c3 on
 		end # I2C3
 		device ref i2c4 off
 		end # I2C4
@@ -588,7 +542,7 @@ chip soc/intel/pantherlake
 				register "generic.desc" = ""Hynitron TOUCHPAD""
 				register "generic.irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_F18_IRQ)"
 				# NOTE: pmc_gpe0_dw0 will be overridden to GPP_F in variant.c.
-				register "generic.wake" = "GPE0_DW0_18"
+				register "generic.wake" = "GPE0_DW0_13"
 				register "generic.uid" = "5"
 				register "generic.detect" = "1"
 				register "hid_desc_reg_offset" = "0x20"

From 99c138ec5007ae5ca4775a103b63ceac490cca79 Mon Sep 17 00:00:00 2001
From: Ingo Reitz <9l@9lo.re>
Date: Tue, 10 Jun 2025 05:31:07 +0200
Subject: [PATCH 1286/3886] soc/mediatek: Don't attempt de-assert PERST#
 without pci_root_bus

Since CB:84118 / 3d5ff65b27 (mb/google/cherry: Complete PCIe reset in
romstage) google-cherry mainboards do an early PERST# de-assert in
romstage. Since cherry does not have a pci_domain, `pci_root_bus()` will
return null, causing an assertion failure later in `find_dev_path()`.

Return if `pci_root_bus()` is NULL.

TEST=Successful boot on google/tomato

Change-Id: Icc35a53e38eef0088371592d8216ac74f9542166
Signed-off-by: Ingo Reitz <9l@9lo.re>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88035
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
---
 src/soc/mediatek/common/pcie.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/src/soc/mediatek/common/pcie.c b/src/soc/mediatek/common/pcie.c
index 9269fbd7d3..339b3d7411 100644
--- a/src/soc/mediatek/common/pcie.c
+++ b/src/soc/mediatek/common/pcie.c
@@ -333,6 +333,9 @@ static void wait_perst_done(uintptr_t base)
 
 void mtk_pcie_deassert_perst(void)
 {
+	if (!pci_root_bus())
+		return;
+
 	uintptr_t base = mtk_pcie_get_controller_base(0);
 
 	wait_perst_done(base);

From 4ef125843612131948cb3f2318fef8fa80df0446 Mon Sep 17 00:00:00 2001
From: Hualin Wei <weihualin@huaqin.corp-partner.google.com>
Date: Mon, 9 Jun 2025 14:38:20 +0800
Subject: [PATCH 1287/3886] spd/lp4x: Add Nanya memory part

Add Nanya memory part NT6AP1024T32BL-J1 in lp4 list.

BUG=b:422906387
TEST=util/spd_tools/bin/spd_gen spd/lp4x/memory_parts.json lp4x

Change-Id: Ie40c591872fe5d6a0251ca53fb60f3bf8d5c4e84
Signed-off-by: Hualin Wei <weihualin@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88004
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com>
---
 spd/lp4x/memory_parts.json                    | 14 ++++++++
 .../set-0/parts_spd_manifest.generated.txt    |  1 +
 spd/lp4x/set-0/spd-9.hex                      | 32 +++++++++++++++++++
 .../set-1/parts_spd_manifest.generated.txt    |  1 +
 spd/lp4x/set-1/spd-12.hex                     | 32 +++++++++++++++++++
 5 files changed, 80 insertions(+)
 create mode 100644 spd/lp4x/set-0/spd-9.hex
 create mode 100644 spd/lp4x/set-1/spd-12.hex

diff --git a/spd/lp4x/memory_parts.json b/spd/lp4x/memory_parts.json
index a6cee87e10..9c90229311 100644
--- a/spd/lp4x/memory_parts.json
+++ b/spd/lp4x/memory_parts.json
@@ -423,6 +423,20 @@
                 "ranksPerChannel": 1,
                 "speedMbps": 4267
             }
+        },
+        {
+            "name": "NT6AP1024F32BL-J1",
+            "attribs": {
+                "densityPerChannelGb": 8,
+                "banks": 8,
+                "channelsPerDie": 4,
+                "diesPerPackage": 1,
+                "bitWidthPerChannel": 16,
+                "ranksPerChannel": 1,
+                "speedMbps": 4267,
+                "tckMaxPs": 468,
+                "casLatencies": "6 10 14 20 24 28 32 36"
+            }
         }
 
     ]
diff --git a/spd/lp4x/set-0/parts_spd_manifest.generated.txt b/spd/lp4x/set-0/parts_spd_manifest.generated.txt
index 8b2eb7bfb0..e7ea7cf3af 100644
--- a/spd/lp4x/set-0/parts_spd_manifest.generated.txt
+++ b/spd/lp4x/set-0/parts_spd_manifest.generated.txt
@@ -36,3 +36,4 @@ CXDB4ABAM-ML,spd-8.hex
 CXDB4CBAM-ML-A,spd-8.hex
 SDVB8D8A34XGCL3N3T,spd-1.hex
 NT6AP512T32BL-J1,spd-8.hex
+NT6AP1024F32BL-J1,spd-9.hex
diff --git a/spd/lp4x/set-0/spd-9.hex b/spd/lp4x/set-0/spd-9.hex
new file mode 100644
index 0000000000..94a317f807
--- /dev/null
+++ b/spd/lp4x/set-0/spd-9.hex
@@ -0,0 +1,32 @@
+23 11 11 0E 15 21 B8 08 00 00 00 00 02 01 00 00
+00 00 04 04 92 54 05 00 87 00 90 A8 90 C0 08 60
+04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 E5 E0 E0 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 20 20 20 20 20 20 20
+20 20 20 20 20 20 20 20 20 20 20 20 20 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
diff --git a/spd/lp4x/set-1/parts_spd_manifest.generated.txt b/spd/lp4x/set-1/parts_spd_manifest.generated.txt
index 7dc50f92e6..85d892e237 100644
--- a/spd/lp4x/set-1/parts_spd_manifest.generated.txt
+++ b/spd/lp4x/set-1/parts_spd_manifest.generated.txt
@@ -36,3 +36,4 @@ CXDB4ABAM-ML,spd-11.hex
 CXDB4CBAM-ML-A,spd-11.hex
 SDVB8D8A34XGCL3N3T,spd-5.hex
 NT6AP512T32BL-J1,spd-11.hex
+NT6AP1024F32BL-J1,spd-12.hex
diff --git a/spd/lp4x/set-1/spd-12.hex b/spd/lp4x/set-1/spd-12.hex
new file mode 100644
index 0000000000..e3d97d5c2f
--- /dev/null
+++ b/spd/lp4x/set-1/spd-12.hex
@@ -0,0 +1,32 @@
+23 11 11 0E 17 21 08 08 00 00 00 00 02 22 00 00
+00 00 04 04 92 54 05 00 87 00 90 A8 90 C0 08 60
+04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 E5 E0 E0 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 20 20 20 20 20 20 20
+20 20 20 20 20 20 20 20 20 20 20 20 20 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00

From bb022f18d5f68f2681c566ffa240bf88b87521d9 Mon Sep 17 00:00:00 2001
From: Hualin Wei <weihualin@huaqin.corp-partner.google.com>
Date: Mon, 9 Jun 2025 16:33:32 +0800
Subject: [PATCH 1288/3886] mb/google/dedede/var/awasuki: Add 2 NANYA modules
 to RAM id table

Add NANYA NT6AP512T32BL-J1 as id 2, and add NANYA NT6AP1024T32BL-J1
as id 3, resulting in the list below:

DRAM Part Name                 ID to assign
K4U6E3S4AB-MGCL                0 (0000)
K4UBE3D4AB-MGCL                1 (0001)
MT53E1G32D2NP-046 WT:B         1 (0001)
NT6AP512T32BL-J1               2 (0010)
NT6AP1024F32BL-J1              3 (0011)

BUG=422906387
TEST=Use part_id_gen to generate related settings

Change-Id: Ifd60e629eb606c7ce06f478cf7cc8b8b3ec77f74
Signed-off-by: Hualin Wei <weihualin@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88005
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
---
 src/mainboard/google/dedede/variants/awasuki/memory/Makefile.mk | 2 ++
 .../google/dedede/variants/awasuki/memory/dram_id.generated.txt | 2 ++
 .../google/dedede/variants/awasuki/memory/mem_parts_used.txt    | 2 ++
 3 files changed, 6 insertions(+)

diff --git a/src/mainboard/google/dedede/variants/awasuki/memory/Makefile.mk b/src/mainboard/google/dedede/variants/awasuki/memory/Makefile.mk
index 5348e2f9a1..be392405ee 100644
--- a/src/mainboard/google/dedede/variants/awasuki/memory/Makefile.mk
+++ b/src/mainboard/google/dedede/variants/awasuki/memory/Makefile.mk
@@ -6,3 +6,5 @@
 SPD_SOURCES =
 SPD_SOURCES += spd/lp4x/set-1/spd-1.hex      # ID = 0(0b0000)  Parts = K4U6E3S4AB-MGCL
 SPD_SOURCES += spd/lp4x/set-1/spd-3.hex      # ID = 1(0b0001)  Parts = K4UBE3D4AB-MGCL, MT53E1G32D2NP-046 WT:B
+SPD_SOURCES += spd/lp4x/set-1/spd-11.hex      # ID = 2(0b0010)  Parts = NT6AP512T32BL-J1
+SPD_SOURCES += spd/lp4x/set-1/spd-12.hex      # ID = 3(0b0011)  Parts = NT6AP1024F32BL-J1
diff --git a/src/mainboard/google/dedede/variants/awasuki/memory/dram_id.generated.txt b/src/mainboard/google/dedede/variants/awasuki/memory/dram_id.generated.txt
index 495df98d27..dfcf164835 100644
--- a/src/mainboard/google/dedede/variants/awasuki/memory/dram_id.generated.txt
+++ b/src/mainboard/google/dedede/variants/awasuki/memory/dram_id.generated.txt
@@ -7,3 +7,5 @@ DRAM Part Name                 ID to assign
 K4U6E3S4AB-MGCL                0 (0000)
 K4UBE3D4AB-MGCL                1 (0001)
 MT53E1G32D2NP-046 WT:B         1 (0001)
+NT6AP512T32BL-J1               2 (0010)
+NT6AP1024F32BL-J1              3 (0011)
diff --git a/src/mainboard/google/dedede/variants/awasuki/memory/mem_parts_used.txt b/src/mainboard/google/dedede/variants/awasuki/memory/mem_parts_used.txt
index ca9e5c11c1..44e5720a69 100644
--- a/src/mainboard/google/dedede/variants/awasuki/memory/mem_parts_used.txt
+++ b/src/mainboard/google/dedede/variants/awasuki/memory/mem_parts_used.txt
@@ -13,3 +13,5 @@
 K4U6E3S4AB-MGCL
 K4UBE3D4AB-MGCL
 MT53E1G32D2NP-046 WT:B
+NT6AP512T32BL-J1
+NT6AP1024F32BL-J1

From f6926dc8a5a93c37f475b33f6eec9fade607d871 Mon Sep 17 00:00:00 2001
From: Qinghong Zeng <zengqinghong@huaqin.corp-partner.google.com>
Date: Tue, 6 May 2025 15:24:57 +0800
Subject: [PATCH 1289/3886] mb/google/nissa/var/pujjoniru: Update DTT settings
 for thermal control

update DTT settings for thermal control, according to
b:395802079#comment37.

BUG=b:395802079
TEST=emerge-nissa coreboot

Change-Id: Ia3d27baf31f2ba684d3bd8f84e19ce802c3b68d1
Signed-off-by: Qinghong Zeng <zengqinghong@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87545
Reviewed-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 .../google/brya/variants/pujjoniru/overridetree.cb   | 12 ++++++------
 1 file changed, 6 insertions(+), 6 deletions(-)

diff --git a/src/mainboard/google/brya/variants/pujjoniru/overridetree.cb b/src/mainboard/google/brya/variants/pujjoniru/overridetree.cb
index cc3d1dcefc..418ac6db60 100644
--- a/src/mainboard/google/brya/variants/pujjoniru/overridetree.cb
+++ b/src/mainboard/google/brya/variants/pujjoniru/overridetree.cb
@@ -102,8 +102,8 @@ chip soc/intel/alderlake
 	}"
 
 	register "power_limits_config[ADL_N_081_15W_CORE]" = "{
-			.tdp_pl1_override = 15,
-			.tdp_pl2_override = 25,
+			.tdp_pl1_override = 22,
+			.tdp_pl2_override = 35,
 			.tdp_pl4 = 114,
 	}"
 
@@ -279,15 +279,15 @@ chip soc/intel/alderlake
 
 				register "controls.power_limits" = "{
 					.pl1 = {
-							.min_power = 12000,
-							.max_power = 15000,
+							.min_power = 15000,
+							.max_power = 22000,
 							.time_window_min = 28 * MSECS_PER_SEC,
 							.time_window_max = 32 * MSECS_PER_SEC,
 							.granularity = 200
 						},
 					.pl2 = {
-							.min_power = 25000,
-							.max_power = 25000,
+							.min_power = 35000,
+							.max_power = 35000,
 							.time_window_min = 28 * MSECS_PER_SEC,
 							.time_window_max = 32 * MSECS_PER_SEC,
 							.granularity = 1000

From 486604360c70ae201a46427b0d4a1bdbdbcc310d Mon Sep 17 00:00:00 2001
From: Nick Vaccaro <nvaccaro@google.com>
Date: Wed, 11 Jun 2025 13:03:09 -0700
Subject: [PATCH 1290/3886] mb/google/ocelot: add BOARD_GOOGLE_MODEL_OCELOT

Create an ocelot model for the various ocelot variants to use.

BUG=b:419857124, b:419856369
BRANCH=none
TEST=`emerge-ocelot coreboot` and verify it compiles without error.

Change-Id: I61e636beb74c3b1ef36e1b9737aefe0b0ef104c5
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88058
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Avi Uday <aviuday@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Pranava Y N <pranavayn@google.com>
---
 src/mainboard/google/ocelot/Kconfig | 6 +++++-
 1 file changed, 5 insertions(+), 1 deletion(-)

diff --git a/src/mainboard/google/ocelot/Kconfig b/src/mainboard/google/ocelot/Kconfig
index 319f7d2c33..669b0ea83f 100644
--- a/src/mainboard/google/ocelot/Kconfig
+++ b/src/mainboard/google/ocelot/Kconfig
@@ -56,13 +56,17 @@ config BOARD_GOOGLE_BASEBOARD_OCELOT
 	select SYSTEM_TYPE_LAPTOP
 	select TPM_GOOGLE_TI50
 
-config BOARD_GOOGLE_OCELOT
+config BOARD_GOOGLE_MODEL_OCELOT
+	def_bool n
 	select BOARD_GOOGLE_BASEBOARD_OCELOT
 	select DRIVERS_GENERIC_BAYHUB_LV2
 	select DRIVERS_GENERIC_MAX98357A
 	select DRIVERS_INTEL_TOUCH
 	select FSP_UGOP_EARLY_SIGN_OF_LIFE
 
+config BOARD_GOOGLE_OCELOT
+	select BOARD_GOOGLE_MODEL_OCELOT
+
 if BOARD_GOOGLE_OCELOT_COMMON
 
 config BASEBOARD_DIR

From 22861340021f999f114db5752a934b5ad9a99191 Mon Sep 17 00:00:00 2001
From: Tongtong Pan <pantongtong@huaqin.corp-partner.google.com>
Date: Tue, 10 Jun 2025 19:27:36 +0800
Subject: [PATCH 1291/3886] mb/google/fatcat/var/felino: Configure
 CAM_VDD_EN_SOC GPIO to restore camera function

GPP_D07 was modified in CB:87806, which resulted in the dut having no camera function. Now we need to restore the configuration of GPP_D07.

BUG=NONE
TEST=emerge-fatcat coreboot and find that the camera function is good.

CB:87806: mb/google/fatcat/var/felino: Modify GPIOs config: I075efda3044ffe45d7db3d225b10e96e084483aa
Change-Id: I085c98753614a0b72f191a863b68990775832c98
Signed-off-by: Tongtong Pan <pantongtong@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88025
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
---
 src/mainboard/google/fatcat/variants/felino/gpio.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/mainboard/google/fatcat/variants/felino/gpio.c b/src/mainboard/google/fatcat/variants/felino/gpio.c
index 5a317f1491..87f4edddc8 100644
--- a/src/mainboard/google/fatcat/variants/felino/gpio.c
+++ b/src/mainboard/google/fatcat/variants/felino/gpio.c
@@ -164,8 +164,8 @@ static const struct pad_config gpio_table[] = {
 	PAD_NC(GPP_D05, NONE),
 	/* GPP_D06:     Not used */
 	PAD_NC(GPP_D06, NONE),
-	/* GPP_D07:     Not used */
-	PAD_NC(GPP_D07, NONE),
+	/* GPP_D07:     CAM_VDD_EN_SOC */
+	PAD_CFG_GPO(GPP_D07, 1, PLTRST),
 	/* GPP_D08:     NC */
 	PAD_NC(GPP_D08, NONE),
 	/* GPP_D09:     Not used */

From 25385df0179fac2b28148a63737c937b674fb057 Mon Sep 17 00:00:00 2001
From: Alok <alok.agarwal@intel.corp-partner.google.com>
Date: Wed, 28 May 2025 13:16:33 +0530
Subject: [PATCH 1292/3886] vc/intel/fsp/ptl: Update PTL header files to FSP
 3182_01

Update header files for FSP for Panther Lake platform to version
3182.01, previous version being 3144.01.

Changes include:
- Update FspmUpd.h
- Add PprRetryLimit and Use1p5ReadPostamble variable

BUG=b:421287370
TEST=Able to build google/fatcat with the partial header changes

Change-Id: I14e8c3c8751ae6aa0718d0015a1611ced6a2cdd4
Signed-off-by: Alok Agarwal <alok.agarwal@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87879
Reviewed-by: Pranava Y N <pranavayn@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
---
 .../intel/fsp/fsp2_0/pantherlake/FspmUpd.h    | 20 +++++++++++++++----
 1 file changed, 16 insertions(+), 4 deletions(-)

diff --git a/src/vendorcode/intel/fsp/fsp2_0/pantherlake/FspmUpd.h b/src/vendorcode/intel/fsp/fsp2_0/pantherlake/FspmUpd.h
index b87b5a9ca7..c5b16d6dce 100644
--- a/src/vendorcode/intel/fsp/fsp2_0/pantherlake/FspmUpd.h
+++ b/src/vendorcode/intel/fsp/fsp2_0/pantherlake/FspmUpd.h
@@ -1415,9 +1415,21 @@ typedef struct {
 **/
   UINT8                       RDTCIDLE;
 
-/** Offset 0x031B - Reserved
+/** Offset 0x031B - PPR Retry Limit
+  Sets a limit on the number of times Memory Testing will be retried after attempting
+  to repair using PPR.
 **/
-  UINT8                       Reserved32[20];
+  UINT8                       PprRetryLimit;
+
+/** Offset 0x031C - Use 1p5 Read Postamble
+  Enables/Disable using 1p5 tCK Read Postamble for higher freqencies
+  $EN_DIS
+**/
+  UINT8                       Use1p5ReadPostamble;
+
+/** Offset 0x031D - Reserved
+**/
+  UINT8                       Reserved32[18];
 
 /** Offset 0x032F - Board Type
   MrcBoardType, Options are 0=Mobile/Mobile Halo, 1=Desktop/DT Halo, 5=ULT/ULX/Mobile
@@ -2811,8 +2823,8 @@ typedef struct {
   UINT16                      IgdDvmt50PreAlloc;
 
 /** Offset 0x0AC8 - Internal Graphics
-  Enable/disable internal graphics.
-  $EN_DIS
+  Expect 3 values from 0 to 2
+  2:AUTO, 1:Enable, 0:Disable
 **/
   UINT8                       InternalGraphics;
 

From 2ee72eaab12f578caedaf69c950b57800e547ec4 Mon Sep 17 00:00:00 2001
From: Subrata Banik <subratabanik@google.com>
Date: Thu, 12 Jun 2025 17:27:02 +0530
Subject: [PATCH 1293/3886] soc/intel/pantherlake: Update
 CONSOLE_UART_BASE_ADDRESS Kconfig value

The console UART base address for Panther Lake is being updated from
0xfe02c000 to 0xfe036000 (as per FSP version 3182). This correction
ensures the console initializes with the correct UART base address.

Additionally, now the UART base address is in sync between coreboot,
FSP and GFX PEIM.

BUG=b:423878608
TEST=Able to get FSP debug log while building google/fatcat.

```
dw-apb-uart.3: ttyS0 at MMIO 0xfe036000
```
Change-Id: I0caae8b5ea34561d88f5a4aa0cb12481db6f9417
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88073
Reviewed-by: <srinivas.kulkarni@intel.com>
Reviewed-by: Pranava Y N <pranavayn@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/soc/intel/pantherlake/Kconfig | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/soc/intel/pantherlake/Kconfig b/src/soc/intel/pantherlake/Kconfig
index 03865b2ddf..87d78b85a2 100644
--- a/src/soc/intel/pantherlake/Kconfig
+++ b/src/soc/intel/pantherlake/Kconfig
@@ -308,7 +308,7 @@ config SOC_INTEL_USB3_DEV_MAX
 
 config CONSOLE_UART_BASE_ADDRESS
 	hex
-	default 0xfe02c000
+	default 0xfe036000
 	depends on INTEL_LPSS_UART_FOR_CONSOLE
 
 # Clock divider parameters for 115200 baud rate

From d4a33638f5d000d450b69508ec09c972cb94a2ab Mon Sep 17 00:00:00 2001
From: Luca Lai <luca.lai@lcfc.corp-partner.google.com>
Date: Thu, 12 Jun 2025 04:21:10 +0800
Subject: [PATCH 1294/3886] mb/trulo/var/pujjolo: Change dram id table

Alter dram from H9JCNNNCP3MLYR-N6E to H9JCNNNBK3MLYR-N6E

BUG=b:395763555
BRANCH=none
TEST=Could boot to OS.

Change-Id: Id2b024286b3699015be3a25341389db353d1ab8f
Signed-off-by: Luca Lai <luca.lai@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88061
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
---
 src/mainboard/google/brya/variants/pujjolo/memory/Makefile.mk   | 2 +-
 .../google/brya/variants/pujjolo/memory/dram_id.generated.txt   | 2 +-
 .../google/brya/variants/pujjolo/memory/mem_parts_used.txt      | 2 +-
 3 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/src/mainboard/google/brya/variants/pujjolo/memory/Makefile.mk b/src/mainboard/google/brya/variants/pujjolo/memory/Makefile.mk
index 07e09804c1..b4d593dccf 100644
--- a/src/mainboard/google/brya/variants/pujjolo/memory/Makefile.mk
+++ b/src/mainboard/google/brya/variants/pujjolo/memory/Makefile.mk
@@ -7,4 +7,4 @@ SPD_SOURCES =
 SPD_SOURCES += spd/lp5/set-0/spd-9.hex      # ID = 0(0b0000)  Parts = K3KL6L60GM-MGCT
 SPD_SOURCES += spd/lp5/set-0/spd-7.hex      # ID = 1(0b0001)  Parts = K3KL8L80CM-MGCT
 SPD_SOURCES += spd/lp5/set-0/spd-11.hex      # ID = 2(0b0010)  Parts = H58G56CK8BX146
-SPD_SOURCES += spd/lp5/set-0/spd-2.hex      # ID = 3(0b0011)  Parts = H9JCNNNCP3MLYR-N6E
+SPD_SOURCES += spd/lp5/set-0/spd-1.hex      # ID = 3(0b0011)  Parts = H9JCNNNBK3MLYR-N6E
diff --git a/src/mainboard/google/brya/variants/pujjolo/memory/dram_id.generated.txt b/src/mainboard/google/brya/variants/pujjolo/memory/dram_id.generated.txt
index cf61f227ff..3d03fa66a3 100644
--- a/src/mainboard/google/brya/variants/pujjolo/memory/dram_id.generated.txt
+++ b/src/mainboard/google/brya/variants/pujjolo/memory/dram_id.generated.txt
@@ -7,4 +7,4 @@ DRAM Part Name                 ID to assign
 K3KL6L60GM-MGCT                0 (0000)
 K3KL8L80CM-MGCT                1 (0001)
 H58G56CK8BX146                 2 (0010)
-H9JCNNNCP3MLYR-N6E             3 (0011)
+H9JCNNNBK3MLYR-N6E             3 (0011)
diff --git a/src/mainboard/google/brya/variants/pujjolo/memory/mem_parts_used.txt b/src/mainboard/google/brya/variants/pujjolo/memory/mem_parts_used.txt
index c8815ed13e..e1102d6c26 100644
--- a/src/mainboard/google/brya/variants/pujjolo/memory/mem_parts_used.txt
+++ b/src/mainboard/google/brya/variants/pujjolo/memory/mem_parts_used.txt
@@ -12,4 +12,4 @@
 K3KL6L60GM-MGCT
 K3KL8L80CM-MGCT
 H58G56CK8BX146
-H9JCNNNCP3MLYR-N6E
+H9JCNNNBK3MLYR-N6E

From a0e6fd9a95f52b45d45d61a0219a3992ad0766da Mon Sep 17 00:00:00 2001
From: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com>
Date: Thu, 12 Jun 2025 01:44:17 -0700
Subject: [PATCH 1295/3886] Documentation: Add coreboot release 25.09 template

This adds the release notes template for the upcoming September release
of coreboot.

Change-Id: I9033b107f148b4b40bb1243d2d0eb0b7e7f7b6dc
Signed-off-by: Jason Glenesk <jason.glenesk@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88071
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
---
 .../releases/coreboot-25.09-relnotes.md       | 96 +++++++++++++++++++
 Documentation/releases/index.md               |  3 +-
 2 files changed, 98 insertions(+), 1 deletion(-)
 create mode 100644 Documentation/releases/coreboot-25.09-relnotes.md

diff --git a/Documentation/releases/coreboot-25.09-relnotes.md b/Documentation/releases/coreboot-25.09-relnotes.md
new file mode 100644
index 0000000000..485f9cd412
--- /dev/null
+++ b/Documentation/releases/coreboot-25.09-relnotes.md
@@ -0,0 +1,96 @@
+Upcoming release - coreboot 25.09
+========================================================================
+
+The 25.09 release is scheduled for the end of September, 2025
+
+
+Update this document with changes that should be in the release notes.
+
+* Please use Markdown.
+* See the past few release notes for the general format.
+* The chip and board additions and removals will be updated right
+  before the release, so those do not need to be added.
+* Note that all changes before the release are done are marked upcoming.
+  A final version of the notes are done after the release.
+
+
+
+Significant or interesting changes
+----------------------------------
+
+* Add changes that need a full description here
+
+* This section should have full descriptions and can or should have
+  a link to the referenced commits.
+
+
+
+Additional coreboot changes
+---------------------------
+
+The following are changes across a number of patches, or changes worth
+noting, but not needing a full description.
+
+* Changes that only need a line or two of description go here.
+
+
+
+Changes to external resources
+-----------------------------
+
+### Toolchain updates
+
+
+
+### Git submodule pointers
+
+
+### External payloads
+
+
+
+Platform Updates
+----------------
+
+### Added mainboards:
+* To be filled in immediately before the release by the release team
+
+
+### Removed Mainboards
+* To be filled in immediately before the release by the release team
+
+
+### Updated SoCs
+* To be filled in immediately before the release by the release team
+
+
+
+Plans to move platform support to a branch
+------------------------------------------
+* To be filled in immediately before the release by the release team
+
+
+
+Statistics from the 25.03 to the 25.06 release
+--------------------------------------------
+* To be filled in immediately before the release by the release team
+
+
+
+Significant Known and Open Issues
+---------------------------------
+
+Issues from the coreboot bugtracker: <https://ticket.coreboot.org/>
+* To be filled in immediately before the release by the release team
+
+
+
+coreboot Links and Contact Information
+--------------------------------------
+
+* Main Web site: <https://www.coreboot.org>
+* Downloads: <https://coreboot.org/downloads.html>
+* Source control: <https://review.coreboot.org>
+* Documentation: <https://doc.coreboot.org>
+* Issue tracker: <https://ticket.coreboot.org/projects/coreboot>
+* Donations: <https://coreboot.org/donate.html>
diff --git a/Documentation/releases/index.md b/Documentation/releases/index.md
index aec897eaf5..b587ebcc36 100644
--- a/Documentation/releases/index.md
+++ b/Documentation/releases/index.md
@@ -6,7 +6,7 @@ Please add to the release notes as changes are added:
 ```{toctree}
 :maxdepth: 1
 
-25.06  - June 2025 <coreboot-25.06-relnotes.md>
+25.09  - September 2025 <coreboot-25.09-relnotes.md>
 ```
 
 The [checklist] contains instructions to ensure that a release covers all
@@ -22,6 +22,7 @@ important is taken care of.
 ```{toctree}
 :maxdepth: 1
 
+25.06  - June 2025 <coreboot-25.06-relnotes.md>
 25.03  - March 2025 <coreboot-25.03-relnotes.md>
 24.12  - December 2024 <coreboot-24.12-relnotes.md>
 24.08  - August 2024 <coreboot-24.08-relnotes.md>

From 6da913bd463005d112ff5cf2e906cb7200d4ea9b Mon Sep 17 00:00:00 2001
From: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com>
Date: Thu, 12 Jun 2025 01:22:19 -0700
Subject: [PATCH 1296/3886] docs/security/vboot: Update supported board list

Generated by util/vboot_list/vboot_list.sh.

Change-Id: I8f706ac70a40dd83eca9701d99bec364f6d8e22c
Signed-off-by: Jason Glenesk <jason.glenesk@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88070
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 Documentation/security/vboot/list_vboot.md | 18 ++++++++++++++++--
 1 file changed, 16 insertions(+), 2 deletions(-)

diff --git a/Documentation/security/vboot/list_vboot.md b/Documentation/security/vboot/list_vboot.md
index 14a6a2348c..c42352ddf5 100644
--- a/Documentation/security/vboot/list_vboot.md
+++ b/Documentation/security/vboot/list_vboot.md
@@ -37,7 +37,10 @@
 - Panther (ASUS Chromebox CN60)
 - Tricky (Dell Chromebox 3010)
 - Zako (HP Chromebox G1)
+- Bluey
+- Quenbi
 - Brox
+- Brox RTK EC
 - Brox EC ISH
 - Brox TI PDC
 - Greenbayupoc
@@ -115,9 +118,12 @@
 - Sundance
 - Pujjoga
 - Pujjogatwin
+- Pujjolo
 - Orisa
 - Telith
 - Meliks
+- Epic
+- Pujjocento
 - Butterfly (HP Pavilion Chromebook 14)
 - Cherry
 - Dojo
@@ -156,6 +162,7 @@
 - Fatcatnuvo
 - Felino
 - Francka
+- Kinmen
 - Fizz
 - Karma
 - Endeavour
@@ -289,7 +296,10 @@
 - Markarth (Acer Chromebook Plus 514)
 - Skyrim
 - Winterhold (Dell Latitude 3445 Chromebook)
+- Anakin
+- Obiwan
 - Skywalker
+- Yoda
 - Falco (HP Chromebook 14)
 - Leon (Toshiba Chromebook)
 - Peppy (Acer C720/C720P Chromebook)
@@ -383,6 +393,7 @@
 - Meteorlake-P RVP with Chrome EC for non-Prod Silicon
 - Meteorlake-P RVP with Microchip EC
 - Ptlrvp
+- Google Chrome EC
 - shadowmountain
 - Strago
 - Tigerlake UP3 RVP
@@ -428,8 +439,10 @@
 - PRO Z790-P (WIFI)
 
 ## NovaCustom
-- V540TU (14\")
-- V560TU (16\")
+- V540TNx (14\", discrete graphics)
+- V560TNx (16\", discrete graphics)
+- V540TU (14\", integrated graphics)
+- V560TU (16\", integrated graphics)
 
 ## OpenCellular
 - Elgon (GBCv2)
@@ -454,6 +467,7 @@
 
 ## Star Labs
 - Star Labs Byte Mk II (N200)
+- Star Labs Byte Mk III (N355)
 - Star Labs Lite Mk III (N5000)
 - Star Labs Lite Mk IV (N5030)
 - Star Labs LabTop Mk III (i7-8550u)

From b4f2a515331734bfbce2ec0867042d760d972c15 Mon Sep 17 00:00:00 2001
From: Yu-Ping Wu <yupingso@chromium.org>
Date: Thu, 12 Jun 2025 09:43:12 +0800
Subject: [PATCH 1297/3886] libpayload/arch/arm64/mmu: Fix missing CBMEM in
 used ranges
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

We use mmu_ranges to track the list of memory ranges and their types for
MMU initialization. We also keep track of used memory ranges in
usedmem_ranges, to avoid them from being re-allocated in
mmu_alloc_range().

The problem is, the CBMEM range (CB_MEM_TABLE) is added to mmu_ranges,
but is never marked as "used" in usedmem_ranges. This potentially causes
any allocation (for example the framebuffer) to overlap with CBMEM. This
issue is observed when DMA_DEFAULT_SIZE is reduced from 32MB to 1MB [1].
Prior to that change, because there isn't enough space above the
coreboot table (with the 4GB upper limit) to fit the 32MB requested
region, the DMA heap is always allocated *below* the coreboot table. And
because the coreboot table is usually the lowest within CBMEM, the DMA
heap region is allocated *below* the whole CBMEM, which happens the
avoid the issue.

Fix the bug by adding CB_MEM_TABLE ranges to usedmem_ranges. The ranges
in usedmem_ranges don't need to be combined because they are not for MMU
initialization (and there's only one CB_MEM_TABLE range).

[1] commit aedc177f000a ("libpayload: arm64: Reduce DMA allocator space to 1MB")

BUG=b:424107889
TEST=emerge-skywalker libpayload
BRANCH=none

Change-Id: Ie9ecafc17546e524253c60ab684ec10ff3495998
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88063
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Bartłomiej Grzesik <bgrzesik@google.com>
Reviewed-by: Jakub "Kuba" Czapiga <czapiga@google.com>
---
 payloads/libpayload/arch/arm64/mmu.c | 19 +++++++++++++------
 1 file changed, 13 insertions(+), 6 deletions(-)

diff --git a/payloads/libpayload/arch/arm64/mmu.c b/payloads/libpayload/arch/arm64/mmu.c
index 3822a891cf..e99fa37c5d 100644
--- a/payloads/libpayload/arch/arm64/mmu.c
+++ b/payloads/libpayload/arch/arm64/mmu.c
@@ -606,16 +606,23 @@ static void mmu_extract_ranges(struct memrange *cb_ranges,
 
 	/* Extract memory ranges to be mapped */
 	for (; i < ncb; i++) {
+		uint64_t base = cb_ranges[i].base;
+		uint64_t size = cb_ranges[i].size;
+
 		switch (cb_ranges[i].type) {
-		case CB_MEM_RAM:
 		case CB_MEM_TABLE:
-			if (prev_range && (prev_range->base + prev_range->size
-					   == cb_ranges[i].base)) {
-				prev_range->size += cb_ranges[i].size;
+			/* Mark this memrange as used memory */
+			if (mmu_add_memrange(&usedmem_ranges, base, size,
+					     TYPE_NORMAL_MEM) == NULL)
+				mmu_error();
+			__fallthrough;
+		case CB_MEM_RAM:
+			if (prev_range &&
+			    prev_range->base + prev_range->size == base) {
+				prev_range->size += size;
 			} else {
 				prev_range = mmu_add_memrange(mmu_ranges,
-							      cb_ranges[i].base,
-							      cb_ranges[i].size,
+							      base, size,
 							      TYPE_NORMAL_MEM);
 				if (prev_range == NULL)
 					mmu_error();

From ad05c65d723b893c890ada12b16bc5c77d79ebae Mon Sep 17 00:00:00 2001
From: Jincheng Li <jincheng.li@intel.com>
Date: Thu, 15 May 2025 14:43:49 +0800
Subject: [PATCH 1298/3886] soc/intel/xeon_sp: Initialize SPI before using it

fast_spi_cache_bios_region() refers to the SPI BAR before it is
initialized. Therefore, move the initialization before this function
to obtain the correct value.

If SPI is not initialized before use, an incorrect MTRR item is observed:
[DEBUG]  0x00000000fffff005: PHYBASE2: Address = 0x00000000fffff000, WP
[DEBUG]  0x000ffffffffff800: PHYMASK2: Length  = 0x0000000000001000, Valid

TESTED=Build and boot on intel/avenuecity CRB, with below log:
[DEBUG]  0x00000000ff000005: PHYBASE2: Address = 0x00000000ff000000, WP
[DEBUG]  0x000fffffff000800: PHYMASK2: Length  = 0x0000000001000000, Valid

Change-Id: I8a755d2d18a567c09c5a66b03d4fdda5ba603133
Signed-off-by: Jincheng Li <jincheng.li@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88046
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
---
 src/soc/intel/xeon_sp/bootblock.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/soc/intel/xeon_sp/bootblock.c b/src/soc/intel/xeon_sp/bootblock.c
index 3e9922f6e9..49548ed9ef 100644
--- a/src/soc/intel/xeon_sp/bootblock.c
+++ b/src/soc/intel/xeon_sp/bootblock.c
@@ -73,6 +73,7 @@ asmlinkage void bootblock_c_entry(uint64_t base_timestamp)
 	 */
 	assembly_timestamp = base_timestamp;
 	bootblock_timestamp = timestamp_get();
+	fast_spi_early_init(SPI_BASE_ADDRESS);
 	fast_spi_cache_bios_region();
 
 	bootblock_main_with_basetime(MIN(assembly_timestamp, bootblock_timestamp));
@@ -80,7 +81,6 @@ asmlinkage void bootblock_c_entry(uint64_t base_timestamp)
 
 void bootblock_soc_early_init(void)
 {
-	fast_spi_early_init(SPI_BASE_ADDRESS);
 	pch_enable_lpc();
 
 	/* Set up P2SB BAR. This is needed for PCR to work */

From 3711be4e18e621d3d5b6c373493fd81f2305708d Mon Sep 17 00:00:00 2001
From: Jincheng Li <jincheng.li@intel.com>
Date: Fri, 16 May 2025 11:25:59 +0800
Subject: [PATCH 1299/3886] soc/intel/xeon_sp: Use Kconfig to define
 SPI_BASE_ADDRESS

SPI_BASE_ADDRESS is a fixed value to align with SoC and FSP usage.
Use Kconfig to define it so that SoC could override it per their needs.

Change-Id: If5e5338106deb18d108a70f5ffcd96dcb1e5e25a
Signed-off-by: Jincheng Li <jincheng.li@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88047
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
---
 src/soc/intel/xeon_sp/Kconfig             | 6 ++++++
 src/soc/intel/xeon_sp/include/soc/iomap.h | 2 +-
 2 files changed, 7 insertions(+), 1 deletion(-)

diff --git a/src/soc/intel/xeon_sp/Kconfig b/src/soc/intel/xeon_sp/Kconfig
index f61de56105..24923a5a29 100644
--- a/src/soc/intel/xeon_sp/Kconfig
+++ b/src/soc/intel/xeon_sp/Kconfig
@@ -64,6 +64,12 @@ config MAX_CPUS
 	int
 	default 80
 
+config INTEL_SPI_BASE_ADDRESS
+	hex
+	default 0xfe010000
+	help
+	  SPI BAR0 Base address.
+
 config INTEL_ACPI_BASE_ADDRESS
 	hex
 	default 0x500
diff --git a/src/soc/intel/xeon_sp/include/soc/iomap.h b/src/soc/intel/xeon_sp/include/soc/iomap.h
index ccc7e44d23..baeb7556f7 100644
--- a/src/soc/intel/xeon_sp/include/soc/iomap.h
+++ b/src/soc/intel/xeon_sp/include/soc/iomap.h
@@ -15,7 +15,7 @@
 #define MAP_ENTRY_LIMIT_32(reg_, mask_bits_, desc_) MAP_ENTRY(reg_, 0, 1, mask_bits_, desc_)
 
 // SPI BAR0 MMIO base address
-#define SPI_BASE_ADDRESS             0xfe010000
+#define SPI_BASE_ADDRESS             CONFIG_INTEL_SPI_BASE_ADDRESS
 #define SPI_BASE_SIZE                0x1000
 
 #define TCO_BASE_ADDRESS             0x400

From 98f1886c895ea6eb68ba38a5c8ca2d186fa57a0c Mon Sep 17 00:00:00 2001
From: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Date: Thu, 12 Jun 2025 14:13:42 +0800
Subject: [PATCH 1300/3886] mb/google/nissa/var/yaviks: Add H58G56CK8BX146 to
 RAM ID table

DRAM Part Name                 ID to assign
H58G56CK8BX146                 7 (0111)

BUG=b:424334614
BRANCH=firmware-nissa-15217.B
TEST=emerge-nissa coreboot

Change-Id: I9ca77d07908502649f3bc5380071ca1edceba997
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88066
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/google/brya/variants/yaviks/memory/Makefile.mk     | 1 +
 .../google/brya/variants/yaviks/memory/dram_id.generated.txt     | 1 +
 .../google/brya/variants/yaviks/memory/mem_parts_used.txt        | 1 +
 3 files changed, 3 insertions(+)

diff --git a/src/mainboard/google/brya/variants/yaviks/memory/Makefile.mk b/src/mainboard/google/brya/variants/yaviks/memory/Makefile.mk
index 36b337a136..8f38bca9de 100644
--- a/src/mainboard/google/brya/variants/yaviks/memory/Makefile.mk
+++ b/src/mainboard/google/brya/variants/yaviks/memory/Makefile.mk
@@ -11,3 +11,4 @@ SPD_SOURCES += spd/lp5/set-0/spd-7.hex      # ID = 3(0b0011)  Parts = H58G56BK7B
 SPD_SOURCES += spd/lp5/set-0/spd-8.hex      # ID = 4(0b0100)  Parts = H58G66BK7BX067, MT62F2G32D4DS-026 WT:B, K3KL9L90CM-MGCT
 SPD_SOURCES += spd/lp5/set-0/spd-6.hex      # ID = 5(0b0101)  Parts = H58G66AK6BX070
 SPD_SOURCES += spd/lp5/set-0/spd-9.hex      # ID = 6(0b0110)  Parts = K3KL6L60GM-MGCT
+SPD_SOURCES += spd/lp5/set-0/spd-11.hex      # ID = 7(0b0111)  Parts = H58G56CK8BX146
diff --git a/src/mainboard/google/brya/variants/yaviks/memory/dram_id.generated.txt b/src/mainboard/google/brya/variants/yaviks/memory/dram_id.generated.txt
index cd1c5a1450..d0e3dfe8de 100644
--- a/src/mainboard/google/brya/variants/yaviks/memory/dram_id.generated.txt
+++ b/src/mainboard/google/brya/variants/yaviks/memory/dram_id.generated.txt
@@ -17,3 +17,4 @@ MT62F2G32D4DS-026 WT:B         4 (0100)
 K3KL9L90CM-MGCT                4 (0100)
 H58G66AK6BX070                 5 (0101)
 K3KL6L60GM-MGCT                6 (0110)
+H58G56CK8BX146                 7 (0111)
diff --git a/src/mainboard/google/brya/variants/yaviks/memory/mem_parts_used.txt b/src/mainboard/google/brya/variants/yaviks/memory/mem_parts_used.txt
index bf50ea472b..d9e4129cba 100644
--- a/src/mainboard/google/brya/variants/yaviks/memory/mem_parts_used.txt
+++ b/src/mainboard/google/brya/variants/yaviks/memory/mem_parts_used.txt
@@ -22,3 +22,4 @@ MT62F2G32D4DS-026 WT:B
 K3KL9L90CM-MGCT
 H58G66AK6BX070
 K3KL6L60GM-MGCT
+H58G56CK8BX146

From 3a065dbbfcfae48a764ad3696a52957054c707f0 Mon Sep 17 00:00:00 2001
From: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Date: Thu, 12 Jun 2025 14:26:20 +0800
Subject: [PATCH 1301/3886] mb/google/nissa/var/yavilla: Add H58G56CK8BX146 to
 RAM ID table

DRAM Part Name                 ID to assign
H58G56CK8BX146                 7 (0111)

BUG=b:424334614
BRANCH=firmware-nissa-15217.B
TEST=emerge-nissa coreboot

Change-Id: I35aa833372eced9b7906b4c46b9e3389fcb364f5
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88067
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/google/brya/variants/yavilla/memory/Makefile.mk    | 1 +
 .../google/brya/variants/yavilla/memory/dram_id.generated.txt    | 1 +
 .../google/brya/variants/yavilla/memory/mem_parts_used.txt       | 1 +
 3 files changed, 3 insertions(+)

diff --git a/src/mainboard/google/brya/variants/yavilla/memory/Makefile.mk b/src/mainboard/google/brya/variants/yavilla/memory/Makefile.mk
index 95bafeaf7d..5cdc7f3809 100644
--- a/src/mainboard/google/brya/variants/yavilla/memory/Makefile.mk
+++ b/src/mainboard/google/brya/variants/yavilla/memory/Makefile.mk
@@ -11,3 +11,4 @@ SPD_SOURCES += spd/lp5/set-0/spd-7.hex      # ID = 3(0b0011)  Parts = H58G56BK7B
 SPD_SOURCES += spd/lp5/set-0/spd-8.hex      # ID = 4(0b0100)  Parts = H58G66BK7BX067, MT62F2G32D4DS-026 WT:B, K3KL9L90CM-MGCT
 SPD_SOURCES += spd/lp5/set-0/spd-6.hex      # ID = 5(0b0101)  Parts = H58G66AK6BX070
 SPD_SOURCES += spd/lp5/set-0/spd-9.hex      # ID = 6(0b0110)  Parts = K3KL6L60GM-MGCT
+SPD_SOURCES += spd/lp5/set-0/spd-11.hex      # ID = 7(0b0111)  Parts = H58G56CK8BX146
diff --git a/src/mainboard/google/brya/variants/yavilla/memory/dram_id.generated.txt b/src/mainboard/google/brya/variants/yavilla/memory/dram_id.generated.txt
index 28d43a6813..98aee2de2d 100644
--- a/src/mainboard/google/brya/variants/yavilla/memory/dram_id.generated.txt
+++ b/src/mainboard/google/brya/variants/yavilla/memory/dram_id.generated.txt
@@ -17,3 +17,4 @@ MT62F2G32D4DS-026 WT:B         4 (0100)
 K3KL9L90CM-MGCT                4 (0100)
 H58G66AK6BX070                 5 (0101)
 K3KL6L60GM-MGCT                6 (0110)
+H58G56CK8BX146                 7 (0111)
diff --git a/src/mainboard/google/brya/variants/yavilla/memory/mem_parts_used.txt b/src/mainboard/google/brya/variants/yavilla/memory/mem_parts_used.txt
index bf50ea472b..d9e4129cba 100644
--- a/src/mainboard/google/brya/variants/yavilla/memory/mem_parts_used.txt
+++ b/src/mainboard/google/brya/variants/yavilla/memory/mem_parts_used.txt
@@ -22,3 +22,4 @@ MT62F2G32D4DS-026 WT:B
 K3KL9L90CM-MGCT
 H58G66AK6BX070
 K3KL6L60GM-MGCT
+H58G56CK8BX146

From fad0064377fbd1e6d403044f71de28db21e555dd Mon Sep 17 00:00:00 2001
From: Appukuttan V K <appukuttan.vk@intel.com>
Date: Wed, 28 May 2025 19:40:29 +0530
Subject: [PATCH 1302/3886] soc/intel/ptl: Add UFS support for Wildcat Lake SOC
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Key changes:
   - Updated ACPI southbridge configuration to include UFS support
     for Wildcat Lake.
   - Modified FSP parameters to enable UFS controllers for
     Wildcat Lake.

References:
- Wildcat Lake Processor EDS Volume 1 (#842271)
- Wildcat Lake External Design Specification (EDS) Volume 2 (#829345)

BUG=b:394208231
TEST=Build Ocelot and Fatcat and verify it compiles  without any error.

Change-Id: I3878b4a54a7be2565b37b0f885af5d55a6778795
Signed-off-by: Appukuttan V K <appukuttan.vk@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87891
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Reviewed-by: Pranava Y N <pranavayn@google.com>
Reviewed-by: Usha P <usha.p@intel.com>
---
 src/soc/intel/pantherlake/acpi/southbridge.asl | 2 +-
 src/soc/intel/pantherlake/fsp_params.c         | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/soc/intel/pantherlake/acpi/southbridge.asl b/src/soc/intel/pantherlake/acpi/southbridge.asl
index bf30363b0f..302099373d 100644
--- a/src/soc/intel/pantherlake/acpi/southbridge.asl
+++ b/src/soc/intel/pantherlake/acpi/southbridge.asl
@@ -54,6 +54,6 @@
 #endif
 
 /* UFS 0:17:0 */
-#if CONFIG(SOC_INTEL_PANTHERLAKE_U_H)
+#if (CONFIG(SOC_INTEL_PANTHERLAKE_U_H) || CONFIG(SOC_INTEL_WILDCATLAKE))
 #include <soc/intel/common/block/acpi/acpi/ufs.asl>
 #endif
diff --git a/src/soc/intel/pantherlake/fsp_params.c b/src/soc/intel/pantherlake/fsp_params.c
index f45d333032..47d135a321 100644
--- a/src/soc/intel/pantherlake/fsp_params.c
+++ b/src/soc/intel/pantherlake/fsp_params.c
@@ -695,7 +695,7 @@ static void fill_fsps_iax_params(FSP_S_CONFIG *s_cfg,
 static void fill_fsps_ufs_params(FSP_S_CONFIG *s_cfg,
 		const struct soc_intel_pantherlake_config *config)
 {
-#if CONFIG(SOC_INTEL_PANTHERLAKE_U_H)
+#if (CONFIG(SOC_INTEL_PANTHERLAKE_U_H) || CONFIG(SOC_INTEL_WILDCATLAKE))
 	/* Setting FSP UPD (1,0) to enable controller 0 */
 	s_cfg->UfsEnable[0] = is_devfn_enabled(PCI_DEVFN_UFS);
 	s_cfg->UfsEnable[1] = 0;

From f44b19f2dc4fd7a1f8b6894f6d3062d7630d8927 Mon Sep 17 00:00:00 2001
From: Simon Yang <simon1.yang@intel.corp-partner.google.com>
Date: Thu, 12 Jun 2025 13:44:01 +0800
Subject: [PATCH 1303/3886] soc/intel/pantherlake: Fix ACPI can't tag data node
 error

On the Fatcat board, the following ACPI error message was observed.
After applying the modification, the issue no longer appears.

ACPI error message via dmesg:
[    0.209800] ACPI: Enabled 2 GPEs in block 00 to 7F
[    0.210654] ACPI: \: Can't tag data node
[    0.211039] ACPI: \: Can't tag data node
[    0.211430] ACPI: \: Can't tag data node
[    0.211672] ACPI: \: Can't tag data node
[    0.212052] ACPI: \: Can't tag data node

BUG:None
TEST:Run 'dmesg | grep -i "Can't tag data node" -A 10 -B 10' and cannot see the error messages anymore.

Change-Id: I3da251b3c1950611fa0b4c125823f89d91dcd804
Signed-off-by: Simon Yang <simon1.yang@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88065
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
---
 src/soc/intel/pantherlake/acpi/gpio.asl | 34 ++++++++++++-------------
 1 file changed, 17 insertions(+), 17 deletions(-)

diff --git a/src/soc/intel/pantherlake/acpi/gpio.asl b/src/soc/intel/pantherlake/acpi/gpio.asl
index 5aea294e61..06630109a7 100644
--- a/src/soc/intel/pantherlake/acpi/gpio.asl
+++ b/src/soc/intel/pantherlake/acpi/gpio.asl
@@ -229,13 +229,13 @@ Device (GPI0)
 			Package (0x02)
 			{
 				"intc-gpio-group-0-subproperties",
-				GPPV
+				"GPPV"
 			},
 
 			Package (0x02)
 			{
 				"intc-gpio-group-1-subproperties",
-				GPPC
+				"GPPC"
 			}
 		}
 	})
@@ -371,13 +371,13 @@ Device (GPI1)
 			Package (0x02)
 			{
 				"intc-gpio-group-0-subproperties",
-				GPPF
+				"GPPF"
 			},
 
 			Package (0x02)
 			{
 				"intc-gpio-group-1-subproperties",
-				GPPE
+				"GPPE"
 			},
 
 		}
@@ -512,19 +512,19 @@ Device (GPI3)
 			Package (0x02)
 			{
 				"intc-gpio-group-0-subproperties",
-				GPPH
+				"GPPH"
 			},
 
 			Package (0x02)
 			{
 				"intc-gpio-group-1-subproperties",
-				GPPA
+				"GPPA"
 			},
 
 			Package (0x02)
 			{
 				"intc-gpio-group-2-subproperties",
-				VGP3
+				"VGP3"
 			}
 		}
 #else
@@ -533,25 +533,25 @@ Device (GPI3)
 			Package (0x02)
 			{
 				"intc-gpio-group-0-subproperties",
-				RSVD
+				"RSVD"
 			},
 
 			Package (0x02)
 			{
 				"intc-gpio-group-1-subproperties",
-				GPPH
+				"GPPH"
 			},
 
 			Package (0x02)
 			{
 				"intc-gpio-group-2-subproperties",
-				GPPA
+				"GPPA"
 			},
 
 			Package (0x02)
 			{
 				"intc-gpio-group-3-subproperties",
-				VGP3
+				"VGP3"
 			}
 		}
 #endif
@@ -741,13 +741,13 @@ Device (GPI4)
 			Package (0x02)
 			{
 				"intc-gpio-group-0-subproperties",
-				GPPS
+				"GPPS"
 			},
 
 			Package (0x02)
 			{
 				"intc-gpio-group-1-subproperties",
-				RSVD
+				"RSVD"
 			}
 		}
 #else
@@ -756,7 +756,7 @@ Device (GPI4)
 			Package (0x02)
 			{
 				"intc-gpio-group-0-subproperties",
-				GPPS
+				"GPPS"
 			}
 		}
 #endif
@@ -893,19 +893,19 @@ Device (GPI5)
 			Package (0x02)
 			{
 				"intc-gpio-group-0-subproperties",
-				GPPB
+				"GPPB"
 			},
 
 			Package (0x02)
 			{
 				"intc-gpio-group-1-subproperties",
-				GPPD
+				"GPPD"
 			},
 
 			Package (0x02)
 			{
 				"intc-gpio-group-2-subproperties",
-				VGP0
+				"VGP0"
 			}
 		}
 	})

From 9b91d50fc1797e4d84ddfc7c18085de3a14c3f7e Mon Sep 17 00:00:00 2001
From: Kilian Krause <kilian.krause@siemens.com>
Date: Tue, 27 May 2025 15:29:11 +0200
Subject: [PATCH 1304/3886] mb/siemens/mc_rpl1: Add GPIO configuration

Provide a valid GPIO configuration based on the mainboard wiring.

BUG=none
TEST=Checked output of verbose GPIO debug messages.

Change-Id: I75570acf2bb11a99b99fe70b9d639837daee125c
Signed-off-by: Kilian Krause <kilian.krause@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87913
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/siemens/mc_rpl/Makefile.mk      |   2 -
 src/mainboard/siemens/mc_rpl/early_gpio.c     | 148 ----------
 src/mainboard/siemens/mc_rpl/gpio.c           | 276 ------------------
 .../mc_rpl/variants/mc_rpl1/Makefile.mk       |   4 +
 .../mc_rpl/variants/mc_rpl1/early_gpio.c      |  26 ++
 .../siemens/mc_rpl/variants/mc_rpl1/gpio.c    |  81 +++++
 6 files changed, 111 insertions(+), 426 deletions(-)
 delete mode 100644 src/mainboard/siemens/mc_rpl/early_gpio.c
 delete mode 100644 src/mainboard/siemens/mc_rpl/gpio.c
 create mode 100644 src/mainboard/siemens/mc_rpl/variants/mc_rpl1/Makefile.mk
 create mode 100644 src/mainboard/siemens/mc_rpl/variants/mc_rpl1/early_gpio.c
 create mode 100644 src/mainboard/siemens/mc_rpl/variants/mc_rpl1/gpio.c

diff --git a/src/mainboard/siemens/mc_rpl/Makefile.mk b/src/mainboard/siemens/mc_rpl/Makefile.mk
index 013a8f603e..e6c0dd62d1 100644
--- a/src/mainboard/siemens/mc_rpl/Makefile.mk
+++ b/src/mainboard/siemens/mc_rpl/Makefile.mk
@@ -3,9 +3,7 @@
 subdirs-y += spd
 
 bootblock-y += bootblock.c
-bootblock-y += early_gpio.c
 
-ramstage-y += gpio.c
 romstage-y += romstage_fsp_params.c
 romstage-y += board_id.c
 romstage-y += memory.c
diff --git a/src/mainboard/siemens/mc_rpl/early_gpio.c b/src/mainboard/siemens/mc_rpl/early_gpio.c
deleted file mode 100644
index c3b2e2a47c..0000000000
--- a/src/mainboard/siemens/mc_rpl/early_gpio.c
+++ /dev/null
@@ -1,148 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <baseboard/gpio.h>
-#include <baseboard/variants.h>
-#include <soc/gpio.h>
-
-/* Early pad configuration in bootblock */
-static const struct pad_config early_gpio_table[] = {
-	/* WWAN_RST# (updated in ramstage) */
-	PAD_CFG_GPO(GPP_F14, 0, DEEP),
-	/* WWAN_PERST_L (updated in ramstage) */
-	PAD_CFG_GPO(GPP_C5, 0, DEEP),
-	/* WWAN_FCPO_L (updated in romstage) */
-	PAD_CFG_GPO(GPP_F15, 0, DEEP),
-	/* WWAN_PWR_EN */
-	PAD_CFG_GPO(GPP_F21, 1, DEEP),
-	/* SMB_CLK */
-	PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1),
-	/* SMB_DATA */
-	PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1),
-
-	/* EC_IN_RW */
-	PAD_CFG_GPI(GPP_E7, NONE, DEEP),
-
-	/* x4 PCIE slot 1 RESET */
-	PAD_CFG_GPO(GPP_F10, 0, PLTRST),
-
-	/* Support external source clock via OEB6 and OEB7 */
-	/* SRCCLK_OEB6 for built-in LAN */
-	PAD_CFG_NF(GPP_E5, NONE, PLTRST, NF2),
-	/* SRCCLK_OEB7 for x4 slot */
-	PAD_CFG_NF(GPP_A7, NONE, PLTRST, NF1),
-
-	/* CPU PCIe VGPIO for RP0 */
-	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_0, NONE, PLTRST, NF1),
-	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_1, NONE, PLTRST, NF1),
-	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_3, NONE, PLTRST, NF1),
-	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_2, NONE, PLTRST, NF1),
-	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_4, NONE, PLTRST, NF1),
-	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_5, NONE, PLTRST, NF1),
-	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_6, NONE, PLTRST, NF1),
-	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_7, NONE, PLTRST, NF1),
-	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_8, NONE, PLTRST, NF1),
-	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_9, NONE, PLTRST, NF1),
-	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_10, NONE, PLTRST, NF1),
-	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_11, NONE, PLTRST, NF1),
-	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_12, NONE, PLTRST, NF1),
-	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_13, NONE, PLTRST, NF1),
-	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_14, NONE, PLTRST, NF1),
-	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_15, NONE, PLTRST, NF1),
-	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_64, NONE, PLTRST, NF1),
-	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_65, NONE, PLTRST, NF1),
-	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_66, NONE, PLTRST, NF1),
-	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_67, NONE, PLTRST, NF1),
-
-	/* CPU PCIe vGPIO for RP1 */
-	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_16, NONE, PLTRST, NF1),
-	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_17, NONE, PLTRST, NF1),
-	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_18, NONE, PLTRST, NF1),
-	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_19, NONE, PLTRST, NF1),
-	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_20, NONE, PLTRST, NF1),
-	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_21, NONE, PLTRST, NF1),
-	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_22, NONE, PLTRST, NF1),
-	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_23, NONE, PLTRST, NF1),
-	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_24, NONE, PLTRST, NF1),
-	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_25, NONE, PLTRST, NF1),
-	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_26, NONE, PLTRST, NF1),
-	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_27, NONE, PLTRST, NF1),
-	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_28, NONE, PLTRST, NF1),
-	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_29, NONE, PLTRST, NF1),
-	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_30, NONE, PLTRST, NF1),
-	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_31, NONE, PLTRST, NF1),
-	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_68, NONE, PLTRST, NF1),
-	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_69, NONE, PLTRST, NF1),
-	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_70, NONE, PLTRST, NF1),
-	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_71, NONE, PLTRST, NF1),
-
-	/* CPU PCIe vGPIO for RP2 */
-	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_32, NONE, PLTRST, NF1),
-	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_33, NONE, PLTRST, NF1),
-	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_34, NONE, PLTRST, NF1),
-	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_35, NONE, PLTRST, NF1),
-	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_36, NONE, PLTRST, NF1),
-	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_37, NONE, PLTRST, NF1),
-	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_38, NONE, PLTRST, NF1),
-	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_39, NONE, PLTRST, NF1),
-	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_40, NONE, PLTRST, NF1),
-	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_41, NONE, PLTRST, NF1),
-	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_42, NONE, PLTRST, NF1),
-	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_43, NONE, PLTRST, NF1),
-	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_44, NONE, PLTRST, NF1),
-	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_45, NONE, PLTRST, NF1),
-	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_46, NONE, PLTRST, NF1),
-	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_47, NONE, PLTRST, NF1),
-	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_72, NONE, PLTRST, NF1),
-	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_73, NONE, PLTRST, NF1),
-	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_74, NONE, PLTRST, NF1),
-	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_75, NONE, PLTRST, NF1),
-
-	/* CPU PCIe vGPIO for RP3 */
-	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_48, NONE, PLTRST, NF1),
-	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_49, NONE, PLTRST, NF1),
-	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_50, NONE, PLTRST, NF1),
-	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_51, NONE, PLTRST, NF1),
-	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_52, NONE, PLTRST, NF1),
-	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_53, NONE, PLTRST, NF1),
-	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_54, NONE, PLTRST, NF1),
-	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_55, NONE, PLTRST, NF1),
-	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_56, NONE, PLTRST, NF1),
-	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_57, NONE, PLTRST, NF1),
-	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_58, NONE, PLTRST, NF1),
-	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_59, NONE, PLTRST, NF1),
-	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_60, NONE, PLTRST, NF1),
-	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_61, NONE, PLTRST, NF1),
-	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_62, NONE, PLTRST, NF1),
-	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_63, NONE, PLTRST, NF1),
-	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_76, NONE, PLTRST, NF1),
-	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_77, NONE, PLTRST, NF1),
-	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_78, NONE, PLTRST, NF1),
-	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_79, NONE, PLTRST, NF1),
-
-	/*_TPM_*/
-	/* H1_PCH_INT_ODL */
-	PAD_CFG_GPI_APIC(GPP_E3, NONE, PLTRST, LEVEL, INVERT),
-	/* F16 : GSPI1_CS0N */
-	PAD_CFG_NF(GPP_F16, NONE, DEEP, NF4),
-	/* F11 : GSPI1_CLK */
-	PAD_CFG_NF(GPP_F11, NONE, DEEP, NF4),
-	/* F13 : GSPI1_MISO */
-	PAD_CFG_NF(GPP_F13, NONE, DEEP, NF4),
-	/* F12 : GSPI1_MOSI */
-	PAD_CFG_NF(GPP_F12, NONE, DEEP, NF4),
-};
-
-static const struct pad_config early_uart_gpio_table[] = {
-	/* UART0 RX */
-	PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2),
-	/* UART0 TX */
-	PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2),
-};
-
-void variant_configure_early_gpio_pads(void)
-{
-	if (CONFIG(INTEL_LPSS_UART_FOR_CONSOLE))
-		gpio_configure_pads(early_uart_gpio_table, ARRAY_SIZE(early_uart_gpio_table));
-
-	gpio_configure_pads(early_gpio_table, ARRAY_SIZE(early_gpio_table));
-}
diff --git a/src/mainboard/siemens/mc_rpl/gpio.c b/src/mainboard/siemens/mc_rpl/gpio.c
deleted file mode 100644
index d1ed7c7df1..0000000000
--- a/src/mainboard/siemens/mc_rpl/gpio.c
+++ /dev/null
@@ -1,276 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <baseboard/gpio.h>
-#include <baseboard/variants.h>
-#include <types.h>
-#include <vendorcode/google/chromeos/chromeos.h>
-
-/* Pad configuration in ramstage */
-static const struct pad_config gpio_table[] = {
-	/* GPIO A0-A6, A9-A10 default function is NF1 for eSPI interface when
-	  eSPI is enabled */
-
-	/* SSD1_PWREN  CPU SSD1 */
-	PAD_CFG_GPO(GPP_D14, 1, PLTRST),
-	/* SSD1_RESET  CPU SSD1 */
-	PAD_CFG_GPO(GPP_F20, 1, PLTRST),
-	/* BT_RF_KILL_N */
-	PAD_CFG_GPO(GPP_A13, 1, PLTRST),
-	/* WLAN RST# */
-	PAD_CFG_GPO(GPP_H2, 1, PLTRST),
-	/* WIFI_WAKE_N */
-	PAD_CFG_GPI_IRQ_WAKE(GPP_D13, NONE, DEEP, LEVEL, INVERT),
-	/* x4 PCIE slot1 PWREN */
-	PAD_CFG_GPO(GPP_H17, 0, PLTRST),
-	/* x4 PCIE slot 1 RESET */
-	PAD_CFG_GPO(GPP_F10, 1, PLTRST),
-	/* Retimer Force Power */
-	PAD_CFG_GPO(GPP_E4, 0, PLTRST),
-	/* PEG Slot RST# */
-	PAD_CFG_GPO(GPP_B2, 1, PLTRST),
-	/* M.2 SSD_2 Reset */
-	PAD_CFG_GPO(GPP_H0, 1, PLTRST),
-	/* CAM_STROBE */
-	PAD_CFG_GPO(GPP_B18, 0, PLTRST),
-	/* Audio Codec INT N */
-	PAD_CFG_GPI_APIC(GPP_H3, NONE, PLTRST, LEVEL, INVERT),
-	/* TCH PAD Power EN */
-	PAD_CFG_GPO(GPP_F7, 1, PLTRST),
-	/* THC1 SPI2 RST# */
-	PAD_CFG_GPO(GPP_F17, 1, PLTRST),
-	/* THC1_SPI2_INTB */
-	PAD_CFG_GPI_APIC(GPP_F18, NONE, PLTRST, EDGE_SINGLE, INVERT),
-	/* THC1_SPI2_INTB */
-	PAD_CFG_GPI(GPP_E17, NONE, PLTRST),
-	/* EC_SLP_S0_CS_N */
-	PAD_CFG_GPO(GPP_F9, 1, PLTRST),
-	/* DISP_AUX_N_BIAS_GPIO */
-	PAD_CFG_GPO(GPP_E23, 1, PLTRST),
-	/* WWAN WAKE N*/
-	PAD_CFG_GPI_IRQ_WAKE(GPP_D18, NONE, DEEP, LEVEL, INVERT),
-	/* WWAN_DISABLE_N */
-	PAD_CFG_GPO(GPP_D15, 1, DEEP),
-	/* WWAN_RST# */
-	PAD_CFG_GPO(GPP_F14, 1, DEEP),
-	/* WWAN_FCP_OFF_N */
-	PAD_CFG_GPO(GPP_F15, 1, DEEP),
-	/* WWAN_PWR_EN */
-	PAD_CFG_GPO(GPP_F21, 1, DEEP),
-	/* WWAN_PERST# */
-	PAD_CFG_GPO(GPP_C5, 1, DEEP),
-	/* PEG_SLOT_WAKE_N */
-	PAD_CFG_GPI(GPP_A20, NONE, PLTRST),
-	/* CAM CONN1 CLKEN */
-	PAD_CFG_GPO(GPP_H15, 1, PLTRST),
-	/* CPU SSD2 PWREN */
-	PAD_CFG_GPO(GPP_C2, 1, PLTRST),
-	/* CPU SSD2 RST# */
-	PAD_CFG_GPO(GPP_H1, 1, PLTRST),
-	/* Sata direct Power */
-	PAD_CFG_GPO(GPP_B4, 1, PLTRST),
-	/* M.2_PCH_SSD_PWREN */
-	PAD_CFG_GPO(GPP_D16, 1, PLTRST),
-
-	/* CAM1_RST */
-	PAD_CFG_GPO(GPP_R5, 1, PLTRST),
-	/* CAM2_RST */
-	PAD_CFG_GPO(GPP_E15, 1, PLTRST),
-	/* CAM1_PWR_EN */
-	PAD_CFG_GPO(GPP_B23, 1, PLTRST),
-	/* CAM2_PWR_EN */
-	PAD_CFG_GPO(GPP_E16, 1, PLTRST),
-	/* M.2_SSD_PDET_R */
-	PAD_CFG_NF(GPP_A12, NONE, DEEP, NF1),
-	/* THC0 SPI1 CLK */
-	PAD_CFG_NF(GPP_E11, NONE, DEEP, NF2),
-	/* THC0 SPI1 IO 1 */
-	PAD_CFG_NF(GPP_E12, NONE, DEEP, NF2),
-	/* THC0 SPI1 IO 2 */
-	PAD_CFG_NF(GPP_E1, NONE, DEEP, NF2),
-	/* THC0 SPI IO 3 */
-	PAD_CFG_NF(GPP_E2, NONE, DEEP, NF2),
-	/* THC1 SPI1 RSTB */
-	PAD_CFG_NF(GPP_E6, NONE, DEEP, NF2),
-	/* UART_RX(1) */
-	PAD_CFG_NF(GPP_C12, NONE, DEEP, NF1),
-	/* UART_RX(2) */
-	PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1),
-	/* UART_RX(4) */
-	PAD_CFG_NF(GPP_T4, NONE, DEEP, NF1),
-	/* UART_RX(5) */
-	PAD_CFG_NF(GPP_T8, NONE, DEEP, NF1),
-	/* UART_RX(6) */
-	PAD_CFG_NF(GPP_T12, NONE, DEEP, NF1),
-
-	/* UART_TX(1) */
-	PAD_CFG_NF(GPP_C13, NONE, DEEP, NF1),
-	/* UART_TX(2) */
-	PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1),
-	/* UART_TX(4) */
-	PAD_CFG_NF(GPP_T5, NONE, DEEP, NF1),
-	/* UART_TX(5) */
-	PAD_CFG_NF(GPP_T9, NONE, DEEP, NF1),
-	/* UART_TX(6) */
-	PAD_CFG_NF(GPP_T13, NONE, DEEP, NF1),
-
-	/* UART_RTS(1) */
-	PAD_CFG_NF(GPP_C14, NONE, DEEP, NF1),
-	/* UART_RTS(2) */
-	PAD_CFG_NF(GPP_C22, NONE, DEEP, NF1),
-	/* UART_RTS(4) */
-	PAD_CFG_NF(GPP_T6, NONE, DEEP, NF1),
-	/* UART_RTS(5) */
-	PAD_CFG_NF(GPP_T10, NONE, DEEP, NF1),
-	/* UART_RTS(6) */
-	PAD_CFG_NF(GPP_T14, NONE, DEEP, NF1),
-
-	/* UART_CTS(1) */
-	PAD_CFG_NF(GPP_C15, NONE, DEEP, NF1),
-	/* UART_CTS(2) */
-	PAD_CFG_NF(GPP_C23, NONE, DEEP, NF1),
-	/* UART_CTS(4) */
-	PAD_CFG_NF(GPP_T7, NONE, DEEP, NF1),
-	/* UART_CTS(5) */
-	PAD_CFG_NF(GPP_T11, NONE, DEEP, NF1),
-	/* UART_CTS(6) */
-	PAD_CFG_NF(GPP_T15, NONE, DEEP, NF1),
-
-	/* SPI_MOSI(1) */
-	PAD_CFG_NF(GPP_B22, NONE, DEEP, NF1),
-	/* SPI_MOSI(2) */
-	PAD_CFG_NF(GPP_D12, NONE, DEEP, NF2),
-
-	/* SPI_MIS0(1) */
-	PAD_CFG_NF(GPP_B21, NONE, DEEP, NF1),
-	/* SPI_MIS0(2) */
-	PAD_CFG_NF(GPP_D11, NONE, DEEP, NF2),
-
-	/* SPI_CLK(1) */
-	PAD_CFG_NF(GPP_B20, NONE, DEEP, NF1),
-	/* SPI_CLK(2) */
-	PAD_CFG_NF(GPP_D10, NONE, DEEP, NF2),
-
-	/* SPI_CS(0, 1) */
-	PAD_CFG_NF(GPP_B14, NONE, DEEP, NF1),
-	/* SPI_CS(1, 0) */
-	PAD_CFG_NF(GPP_B19, NONE, DEEP, NF1),
-	/* SPI_CS(2, 0) */
-	PAD_CFG_NF(GPP_D9, NONE, DEEP, NF2),
-
-	/* I2C_SCL(0) */
-	PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1),
-	/* I2C_SCL(1) */
-	PAD_CFG_NF(GPP_H7, NONE, DEEP, NF1),
-	/* I2C_SCL(2) */
-	PAD_CFG_NF(GPP_B6, NONE, DEEP, NF2),
-	/* I2C_SCL(3) */
-	PAD_CFG_NF(GPP_B8, NONE, DEEP, NF2),
-	/* I2C_SCL(5) */
-	PAD_CFG_NF(GPP_B17, NONE, DEEP, NF2),
-
-	/* I2C_SDA(0) */
-	PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1),
-	/* I2C_SDA(1) */
-	PAD_CFG_NF(GPP_H6, NONE, DEEP, NF1),
-	/* I2C_SDA(2) */
-	PAD_CFG_NF(GPP_B5, NONE, DEEP, NF2),
-	/* I2C_SDA(3) */
-	PAD_CFG_NF(GPP_B7, NONE, DEEP, NF2),
-	/* I2C_SDA(5) */
-	PAD_CFG_NF(GPP_B16, NONE, DEEP, NF2),
-
-	/* I2S0_SCLK */
-	PAD_CFG_NF(GPP_R0, NONE, DEEP, NF2),
-	/* I2S0_SFRM */
-	PAD_CFG_NF(GPP_R1, NONE, DEEP, NF2),
-	/* I2S0_TXD */
-	PAD_CFG_NF(GPP_R2, NONE, DEEP, NF2),
-	/* I2S0_RXD */
-	PAD_CFG_NF(GPP_R3, NONE, DEEP, NF2),
-
-	/* I2S_MCLK1_OUT */
-	PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1),
-	/* I2S_MCLK2_INOUT */
-	PAD_CFG_NF(GPP_F8, NONE, DEEP, NF1),
-
-	/* SNDW1_CLK */
-	PAD_CFG_NF(GPP_S0, NONE, DEEP, NF1),
-	/* SNDW1_DATA */
-	PAD_CFG_NF(GPP_S1, NONE, DEEP, NF1),
-	/* SNDW2_CLK */
-	PAD_CFG_NF(GPP_S2, NONE, DEEP, NF2),
-	/* SNDW2_DATA */
-	PAD_CFG_NF(GPP_S3, NONE, DEEP, NF2),
-	/* SNDW3_CLK */
-	PAD_CFG_NF(GPP_S4, NONE, DEEP, NF2),
-	/* SNDW3_DATA */
-	PAD_CFG_NF(GPP_S5, NONE, DEEP, NF2),
-	/* SNDW4_CLK */
-	PAD_CFG_NF(GPP_S6, NONE, DEEP, NF2),
-	/* SNDW4_DATA */
-	PAD_CFG_NF(GPP_S7, NONE, DEEP, NF2),
-
-	/* SMB_CLK */
-	PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1),
-	/* SMB_DATA */
-	PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1),
-
-	/* SATA DEVSLP */
-	PAD_CFG_NF(GPP_H12, NONE, DEEP, NF4),
-	PAD_CFG_NF(GPP_H13, NONE, DEEP, NF5),
-
-	/* SATA LED pin */
-	PAD_CFG_NF(GPP_E8, NONE, DEEP, NF1),
-
-	/* USB2 OC0 pins */
-	PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1),
-	/* USB2 OC3 pins */
-	PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1),
-
-	/* GPIO pin for PCIE SRCCLKREQB */
-	PAD_CFG_NF(GPP_D5, NONE, DEEP, NF1),
-	PAD_CFG_NF(GPP_D6, NONE, DEEP, NF1),
-	PAD_CFG_NF(GPP_D7, NONE, DEEP, NF1),
-	PAD_NC(GPP_D8, NONE),
-	PAD_CFG_NF(GPP_H19, NONE, DEEP, NF1),
-	PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1),
-	PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1),
-
-	/* DDP1/2/3/4/A/B/C  CTRLCLK and CTRLDATA pins */
-	PAD_CFG_NF(GPP_E18, NONE, DEEP, NF4),
-	PAD_CFG_NF(GPP_E19, NONE, DEEP, NF4),
-	PAD_CFG_NF(GPP_E20, NONE, DEEP, NF4),
-	PAD_CFG_NF(GPP_E21, NONE, DEEP, NF4),
-	PAD_CFG_NF(GPP_E22, NONE, DEEP, NF2),
-	PAD_CFG_NF(GPP_A21, NONE, DEEP, NF2),
-	PAD_CFG_NF(GPP_A22, NONE, DEEP, NF2),
-
-	/* HPD_1 (E14) and HPD_2 (A18) pins */
-	PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1),
-	PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1),
-
-	/* IMGCLKOUT */
-	PAD_CFG_NF(GPP_D4, NONE, DEEP, NF1),
-	PAD_CFG_NF(GPP_H20, NONE, DEEP, NF1),
-	PAD_CFG_NF(GPP_H21, NONE, DEEP, NF1),
-	PAD_CFG_NF(GPP_H22, NONE, DEEP, NF1),
-	/* H23 : CLKREQ5_WWAN_N */
-	PAD_CFG_NF(GPP_H23, NONE, DEEP, NF1),
-
-	/* A21 : HDMI CRLS CTRLCLK */
-	PAD_CFG_NF(GPP_A21, NONE, DEEP, NF1),
-	/* A22 : HDMI CRLS CTRLDATA */
-	PAD_CFG_NF(GPP_A22, NONE, DEEP, NF1),
-	/* H1_PCH_INT_ODL */
-	PAD_CFG_GPI_APIC(GPP_E3, NONE, PLTRST, LEVEL, INVERT)
-};
-
-void variant_configure_gpio_pads(void)
-{
-	gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table));
-}
-
-static const struct cros_gpio cros_gpios[] = {
-	CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME),
-};
-DECLARE_CROS_GPIOS(cros_gpios);
diff --git a/src/mainboard/siemens/mc_rpl/variants/mc_rpl1/Makefile.mk b/src/mainboard/siemens/mc_rpl/variants/mc_rpl1/Makefile.mk
new file mode 100644
index 0000000000..45c478178a
--- /dev/null
+++ b/src/mainboard/siemens/mc_rpl/variants/mc_rpl1/Makefile.mk
@@ -0,0 +1,4 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
+bootblock-y += early_gpio.c
+ramstage-y += gpio.c
diff --git a/src/mainboard/siemens/mc_rpl/variants/mc_rpl1/early_gpio.c b/src/mainboard/siemens/mc_rpl/variants/mc_rpl1/early_gpio.c
new file mode 100644
index 0000000000..c5c19ddabc
--- /dev/null
+++ b/src/mainboard/siemens/mc_rpl/variants/mc_rpl1/early_gpio.c
@@ -0,0 +1,26 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <baseboard/gpio.h>
+#include <baseboard/variants.h>
+#include <soc/gpio.h>
+
+/* Early pad configuration in bootblock */
+static const struct pad_config early_gpio_table[] = {
+	PAD_CFG_GPI(GPP_F11, NONE, DEEP),
+	PAD_CFG_GPI(GPP_F12, NONE, DEEP),
+	PAD_CFG_GPI(GPP_F13, NONE, DEEP),
+	PAD_CFG_GPI(GPP_F14, NONE, DEEP),
+};
+
+static const struct pad_config early_uart_gpio_table[] = {
+	PAD_CFG_NF(GPP_F1, NONE, DEEP, NF2),	/* UART2_RXD */
+	PAD_CFG_NF(GPP_F2, NONE, DEEP, NF2),	/* UART2_TXD */
+};
+
+void variant_configure_early_gpio_pads(void)
+{
+	if (CONFIG(INTEL_LPSS_UART_FOR_CONSOLE))
+		gpio_configure_pads(early_uart_gpio_table, ARRAY_SIZE(early_uart_gpio_table));
+
+	gpio_configure_pads(early_gpio_table, ARRAY_SIZE(early_gpio_table));
+}
diff --git a/src/mainboard/siemens/mc_rpl/variants/mc_rpl1/gpio.c b/src/mainboard/siemens/mc_rpl/variants/mc_rpl1/gpio.c
new file mode 100644
index 0000000000..8b10b57040
--- /dev/null
+++ b/src/mainboard/siemens/mc_rpl/variants/mc_rpl1/gpio.c
@@ -0,0 +1,81 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <baseboard/gpio.h>
+#include <baseboard/variants.h>
+#include <types.h>
+
+/* Pad configuration in ramstage */
+static const struct pad_config gpio_table[] = {
+	/* GPIO A0-A6, A9-A10 default function is NF1 for eSPI interface when
+	  eSPI is enabled */
+
+	/* Community 0 - Gpio Group GPP_B */
+	PAD_CFG_NF(GPP_B2, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_B14, NONE, DEEP, NF4),
+	PAD_CFG_GPI(GPP_B23, NONE, PLTRST),
+
+	/* Community 0 - Gpio Group GPP_A */
+	PAD_CFG_NF(GPP_A0, NONE, DEEP, NF1),	/* eSPI */
+	PAD_CFG_NF(GPP_A1, NONE, DEEP, NF1),	/* eSPI */
+	PAD_CFG_NF(GPP_A2, NONE, DEEP, NF1),	/* eSPI */
+	PAD_CFG_NF(GPP_A3, NONE, DEEP, NF1),	/* eSPI */
+	PAD_CFG_NF(GPP_A4, NONE, DEEP, NF1),	/* eSPI */
+	PAD_CFG_NF(GPP_A14, NONE, DEEP, NF1),	/* USB2 OC1 pin */
+	PAD_CFG_NF(GPP_A15, NONE, DEEP, NF1),	/* USB2 OC2 pin */
+	PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1),	/* USB2 OC3 pin */
+	PAD_CFG_NF(GPP_A23, NONE, DEEP, NF1),	/* eSPI */
+
+	/* Community 1 - Gpio Group GPP_H */
+	PAD_CFG_GPI(GPP_H0, NONE, PLTRST),
+	PAD_CFG_GPI(GPP_H1, NONE, PLTRST),
+	PAD_CFG_GPI(GPP_H2, NONE, PLTRST),
+	PAD_CFG_NF(GPP_H3, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_H6, NONE, DEEP, NF1),	/* I2C1_SDA */
+	PAD_CFG_NF(GPP_H7, NONE, DEEP, NF1),	/* I2C1_SCL */
+	PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2),	/* UART0_RXD */
+	PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2),	/* UART0_TXD */
+	PAD_CFG_NF(GPP_H19, NONE, DEEP, NF1),	/* PCIE_XCLKREQ4 */
+	PAD_CFG_NF(GPP_H23, NONE, DEEP, NF1),	/* PCIE_XCLKREQ5 */
+
+	/* Community 1 - Gpio Group GPP_D */
+	PAD_CFG_NF(GPP_D5, NONE, DEEP, NF1),	/* PCIE_XCLKREQ0 */
+	PAD_CFG_NF(GPP_D6, NONE, DEEP, NF1),	/* PCIE_XCLKREQ1 */
+	PAD_CFG_NF(GPP_D7, NONE, DEEP, NF1),	/* PCIE_XCLKREQ2 */
+	PAD_CFG_NF(GPP_D8, NONE, DEEP, NF1),	/* PCIE_XCLKREQ3 */
+	PAD_CFG_GPI(GPP_D10, NONE, PLTRST),
+	PAD_CFG_GPI(GPP_D12, NONE, PLTRST),
+	PAD_CFG_NF(GPP_D17, NONE, DEEP, NF1),	/* UART1_RXD */
+	PAD_CFG_NF(GPP_D18, NONE, DEEP, NF1),	/* UART1_TXD */
+
+	/* Community 2 - Gpio Group GPD */
+	PAD_CFG_GPI(GPD7, NONE, PLTRST),
+
+	/* Community 4 - Gpio Group GPP_C */
+	PAD_CFG_GPI(GPP_C2, NONE, PLTRST),
+	PAD_CFG_GPI(GPP_C5, NONE, DEEP),
+
+	/* Community 4 - Gpio Group GPP_F */
+	PAD_CFG_GPI(GPP_F0, NONE, PLTRST),
+	PAD_CFG_GPO(GPP_F4, 0, PLTRST),
+	PAD_CFG_GPI(GPP_F7, NONE, PLTRST),
+	PAD_CFG_GPO(GPP_F17, 1, PLTRST),
+	PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1),	/* PCIE_XCLKREQ6 */
+
+	/* Community 4 - Gpio Group GPP_E */
+	PAD_CFG_GPI(GPP_E6, NONE, PLTRST),
+	PAD_CFG_GPI(GPP_E8, NONE, PLTRST),
+	PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1),	/* USB2 OC0 pin */
+	PAD_CFG_GPI(GPP_E14, NONE, PLTRST),
+	PAD_CFG_GPI(GPP_E19, NONE, PLTRST),
+	PAD_CFG_GPI(GPP_E21, NONE, PLTRST),
+	PAD_CFG_GPO(GPP_E22, 0, PLTRST),
+
+	/* Community 5 - Gpio Group GPP_R */
+	PAD_CFG_GPI(GPP_R2, NONE, PLTRST),
+
+};
+
+void variant_configure_gpio_pads(void)
+{
+	gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table));
+}

From 9381dd0cbfb1cd3479410e714107750ad12c8763 Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Wed, 11 Jun 2025 09:11:44 -0500
Subject: [PATCH 1305/3886] soc/intel/meteorlake: Make
 TME_KEY_REGENERATION_ON_WARM_BOOT selectable
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Rather than always enabling TME_KEY_REGENERATION_ON_WARM_BOOT, allow it
to be deselected but default to Y. Enabling it causes issues on boards
which use S3 suspend (vs S0ix), so allow it to be deselected so those
boards don't have to disable TME entirely.

TEST=build/boot starlabs/starbook_mtl, verify S3 resume works properly
with TME_KEY_REGENERATION_ON_WARM_BOOT deselected.

Change-Id: I60de19eddf7c2d8bc390b718b7cb1bf7d0267d47
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88054
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
---
 src/soc/intel/meteorlake/Kconfig | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/src/soc/intel/meteorlake/Kconfig b/src/soc/intel/meteorlake/Kconfig
index cbab6a7f7c..050ddfcd3f 100644
--- a/src/soc/intel/meteorlake/Kconfig
+++ b/src/soc/intel/meteorlake/Kconfig
@@ -99,7 +99,6 @@ config SOC_INTEL_METEORLAKE
 	select SOC_INTEL_MEM_MAPPED_PM_CONFIGURATION
 	select SSE2
 	select SUPPORT_CPU_UCODE_IN_CBFS
-	select TME_KEY_REGENERATION_ON_WARM_BOOT if INTEL_TME
 	select TSC_MONOTONIC_TIMER
 	select UDELAY_TSC
 	select UDK_202302_BINDING
@@ -470,4 +469,7 @@ config SKIP_SEND_CONNECT_TOPOLOGY_CMD
 	  Mainboards which use firmware connection manager may also wish to select this
 	  as needed.
 
+config TME_KEY_REGENERATION_ON_WARM_BOOT
+	default y if INTEL_TME
+
 endif

From cc1f0e5c9056d480cbf70f95d617f3e9f1580dbd Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Wed, 11 Jun 2025 15:31:22 +0100
Subject: [PATCH 1306/3886] mb/starlabs/starbook: Disable
 TME_KEY_REGENERATION_ON_WARM_BOOT

This breaks S3 exit.

Change-Id: I3cb637a2c835b2ba6109f3806e3c27269ad111b3
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88056
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/starlabs/starbook/Kconfig | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/src/mainboard/starlabs/starbook/Kconfig b/src/mainboard/starlabs/starbook/Kconfig
index 5abde68ec3..c9ce050e49 100644
--- a/src/mainboard/starlabs/starbook/Kconfig
+++ b/src/mainboard/starlabs/starbook/Kconfig
@@ -221,6 +221,9 @@ config POWER_STATE_DEFAULT_ON_AFTER_FAILURE
 config SOC_INTEL_CSE_SEND_EOP_EARLY
 	default n
 
+config TME_KEY_REGENERATION_ON_WARM_BOOT
+	default n
+
 config TPM_PIRQ
 	depends on MAINBOARD_HAS_TPM2
 	default 0x56 if BOARD_STARLABS_STARBOOK_TGL

From b1759c9bd69077bd91f97b848400d6b7c1cb71ab Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Wed, 11 Jun 2025 09:41:37 +0100
Subject: [PATCH 1307/3886] mb/starlabs/starlite: Adjust the Flash Map to match
 the Twin Lake IFD

The ME region is 0x1000 smaller for Twin Lake, so adjust it
accordingly.

Change-Id: I8d4a279597b31f05c6181218c4a07acdfc676920
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88057
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
---
 src/mainboard/starlabs/starlite_adl/variants/mk_v/board.fmd | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/mainboard/starlabs/starlite_adl/variants/mk_v/board.fmd b/src/mainboard/starlabs/starlite_adl/variants/mk_v/board.fmd
index bc72a6098d..3c64b27134 100644
--- a/src/mainboard/starlabs/starlite_adl/variants/mk_v/board.fmd
+++ b/src/mainboard/starlabs/starlite_adl/variants/mk_v/board.fmd
@@ -1,7 +1,7 @@
 FLASH	0x1000000 {
 	SI_ALL	0x600000 {
 		SI_DESC			0x1000
-		SI_ME			0x412000
+		SI_ME			0x411000
 	}
 	SI_BIOS 0xa00000 {
 		EC@0x0			0x20000

From c740786f120960b891f0a2e99160a181c3fd8696 Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Mon, 9 Jun 2025 12:12:32 -0500
Subject: [PATCH 1308/3886] drivers/gfx/generic: Use 'noop_read_resources'

The generic device attached to this driver doesn't have resources
separate from the parent device to which it's attached, so
use 'noop_read_resources' to suppress a false-positive error in
the cbmem console log (GENERIC: 0.0 missing read_resources).

Change-Id: I985318dcc7cc32aaa3f6a599ade95e065900031e
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88012
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/drivers/gfx/generic/generic.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/src/drivers/gfx/generic/generic.c b/src/drivers/gfx/generic/generic.c
index f3c12d14a2..01129313a0 100644
--- a/src/drivers/gfx/generic/generic.c
+++ b/src/drivers/gfx/generic/generic.c
@@ -189,6 +189,7 @@ static const char *gfx_acpi_name(const struct device *dev)
 static struct device_operations gfx_ops = {
 	.acpi_name	= gfx_acpi_name,
 	.acpi_fill_ssdt	= gfx_fill_ssdt_generator,
+	.read_resources = noop_read_resources
 };
 
 static void gfx_enable(struct device *dev)

From 7f03e3bd6c8e421eec2d7df02b05007089b0050f Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Mon, 9 Jun 2025 11:42:25 -0500
Subject: [PATCH 1309/3886] drivers/efi/efivars: Change printk level from ERROR
 to DEBUG

This case doesn't reflect an error condition, so adjust the printk
level accordingly.

Change-Id: I3afa818447d3e7c9d08968ffc6b57a663af45c3e
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88011
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
---
 src/drivers/efi/efivars.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/drivers/efi/efivars.c b/src/drivers/efi/efivars.c
index 2591eab730..a9139b197d 100644
--- a/src/drivers/efi/efivars.c
+++ b/src/drivers/efi/efivars.c
@@ -605,7 +605,7 @@ enum cb_err efi_fv_set_option(struct region_device *rdev,
 	found_existing = ret == CB_SUCCESS;
 
 	if (found_existing) {
-		printk(BIOS_ERR, "found existing variable %s, match =%d\n", name, args.match);
+		printk(BIOS_DEBUG, "found existing variable %s, match = %d\n", name, args.match);
 
 		if (args.match)
 			return CB_SUCCESS;

From da122fe8f523bf85dedc9799b9aebe1a2d2b64e6 Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Wed, 11 Jun 2025 11:48:58 +0100
Subject: [PATCH 1310/3886] mb/starlabs/*: Use PLTRST for PCH Strap GPIOs

Replace RSMRST with PLTRST, for the PCH Strap GPIOs. RSMRST introduced
programming errors in cbmem (gpio_pad_reset_config_override: logical
to chipset  mapping not found) and broke tablet mode rotation.

Change-Id: Ia2b655450558a9de98ce1a92c93820ab3da57ca0
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88053
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 .../starlabs/byte_adl/variants/mk_ii/gpio.c   | 24 ++++++++---------
 .../starlabs/starbook/variants/adl_n/gpio.c   | 26 +++++++++----------
 .../starlabs/starbook/variants/mtl/gpio.c     | 18 ++++++-------
 .../starlabs/starbook/variants/tgl/gpio.c     | 24 ++++++++---------
 .../starlabs/starfighter/variants/rpl/gpio.c  | 18 ++++++-------
 .../starlite_adl/variants/mk_v/gpio.c         | 24 ++++++++---------
 6 files changed, 67 insertions(+), 67 deletions(-)

diff --git a/src/mainboard/starlabs/byte_adl/variants/mk_ii/gpio.c b/src/mainboard/starlabs/byte_adl/variants/mk_ii/gpio.c
index b6aa4dbdbc..01a4d5dcd0 100644
--- a/src/mainboard/starlabs/byte_adl/variants/mk_ii/gpio.c
+++ b/src/mainboard/starlabs/byte_adl/variants/mk_ii/gpio.c
@@ -84,18 +84,18 @@ const struct pad_config gpio_table[] = {
 	PAD_CFG_GPO(GPP_E8, 1, DEEP),					/* DRAM Sleep */
 
 	/* Config Straps 									[ Low      / High     ] */
-	PAD_CFG_GPO(GPP_B14, 0, RSMRST),				/* Top Swap		[ Disabled / Enabled  ] */
-	PAD_CFG_GPO(GPP_B18, 0, RSMRST),				/* Reboot Support	[ Enabled  / Disabled ] */
-	PAD_CFG_GPO(GPP_C2, 1, RSMRST),					/* TLS Confidentiality	[ Disabled / Enabled  ] */
-	PAD_CFG_GPO(GPP_C5, 0, RSMRST),					/* eSPI			[ Enabled  / Disabled ] */
-	PAD_CFG_GPO(GPP_E6, 0, RSMRST),					/* JTAG ODT		[ Disabled / Enabled  ] */
-	PAD_CFG_GPO(GPP_H1, 0, RSMRST),					/* BFX Strap 2 Bit 3	[ Disabled / Enabled  ] */
-	PAD_CFG_GPO(GPP_E19, 0, RSMRST),				/* TBT LSX #0		[ 1.8V     / 3.3V     ] */
-	PAD_CFG_GPO(GPP_E21, 0, RSMRST),				/* TBT LSX #1           [ 1.8V     / 3.3V     ] */
-	PAD_CFG_GPO(GPP_D10, 0, RSMRST),				/* TBT LSX #2		[ 1.8V     / 3.3V     ] */
-	PAD_CFG_GPO(GPP_D12, 0, RSMRST),				/* TBT LSX #3		[ 1.8V     / 3.3V     ] */
-	PAD_CFG_GPO(GPP_F7, 0, RSMRST),					/* MCRO LDO		[ Disabled / Bypass   ] */
-	PAD_CFG_GPO(GPD7, 0, RSMRST),					/* RTC Clock Delay	[ Disabled / 95ms     ] */
+	PAD_CFG_GPO(GPP_B14, 0, PLTRST),				/* Top Swap		[ Disabled / Enabled  ] */
+	PAD_CFG_GPO(GPP_B18, 0, PLTRST),				/* Reboot Support	[ Enabled  / Disabled ] */
+	PAD_CFG_GPO(GPP_C2, 1, PLTRST),					/* TLS Confidentiality	[ Disabled / Enabled  ] */
+	PAD_CFG_GPO(GPP_C5, 0, PLTRST),					/* eSPI			[ Enabled  / Disabled ] */
+	PAD_CFG_GPO(GPP_E6, 0, PLTRST),					/* JTAG ODT		[ Disabled / Enabled  ] */
+	PAD_CFG_GPO(GPP_H1, 0, PLTRST),					/* BFX Strap 2 Bit 3	[ Disabled / Enabled  ] */
+	PAD_CFG_GPO(GPP_E19, 0, PLTRST),				/* TBT LSX #0		[ 1.8V     / 3.3V     ] */
+	PAD_CFG_GPO(GPP_E21, 0, PLTRST),				/* TBT LSX #1           [ 1.8V     / 3.3V     ] */
+	PAD_CFG_GPO(GPP_D10, 0, PLTRST),				/* TBT LSX #2		[ 1.8V     / 3.3V     ] */
+	PAD_CFG_GPO(GPP_D12, 0, PLTRST),				/* TBT LSX #3		[ 1.8V     / 3.3V     ] */
+	PAD_CFG_GPO(GPP_F7, 0, PLTRST),					/* MCRO LDO		[ Disabled / Bypass   ] */
+	PAD_CFG_GPO(GPD7, 0, PLTRST),					/* RTC Clock Delay	[ Disabled / 95ms     ] */
 
 	PAD_NC(GPD2, NONE),
 	PAD_NC(GPD6, NONE),
diff --git a/src/mainboard/starlabs/starbook/variants/adl_n/gpio.c b/src/mainboard/starlabs/starbook/variants/adl_n/gpio.c
index 1e4899b59a..fb82f3edf3 100644
--- a/src/mainboard/starlabs/starbook/variants/adl_n/gpio.c
+++ b/src/mainboard/starlabs/starbook/variants/adl_n/gpio.c
@@ -80,19 +80,19 @@ const struct pad_config gpio_table[] = {
 	PAD_CFG_GPO(GPP_E8, 1, DEEP),					/* DRAM Sleep */
 
 	/* Config Straps 									[ Low      / High     ] */
-	PAD_CFG_GPO(GPP_B14, 0, RSMRST),				/* Top Swap		[ Disabled / Enabled  ] */
-	PAD_CFG_GPO(GPP_B18, 0, RSMRST),				/* Reboot Support	[ Enabled  / Disabled ] */
-	PAD_CFG_GPO(GPP_C2, 1, RSMRST),					/* TLS Confidentiality	[ Disabled / Enabled  ] */
-	PAD_CFG_GPO(GPP_C5, 0, RSMRST),					/* eSPI			[ Enabled  / Disabled ] */
-	PAD_CFG_GPO(GPP_E6, 0, RSMRST),					/* JTAG ODT		[ Disabled / Enabled  ] */
-	PAD_CFG_GPO(GPP_H1, 0, RSMRST),					/* BFX Strap 2 Bit 3	[ Disabled / Enabled  ] */
-	PAD_CFG_GPO(GPP_F2, 1, RSMRST),					/* M.2 CNVi		[ Enabled  / Disabled ] */
-	PAD_CFG_GPO(GPP_E19, 0, RSMRST),				/* TBT LSX #0		[ 1.8V     / 3.3V     ] */
-	PAD_CFG_GPO(GPP_E21, 0, RSMRST),				/* TBT LSX #1           [ 1.8V     / 3.3V     ] */
-	PAD_CFG_GPO(GPP_D10, 0, RSMRST),				/* TBT LSX #2		[ 1.8V     / 3.3V     ] */
-	PAD_CFG_GPO(GPP_D12, 0, RSMRST),				/* TBT LSX #3		[ 1.8V     / 3.3V     ] */
-	PAD_CFG_GPO(GPP_F7, 0, RSMRST),					/* MCRO LDO		[ Disabled / Bypass   ] */
-	PAD_CFG_GPO(GPD7, 0, RSMRST),					/* RTC Clock Delay	[ Disabled / 95ms     ] */
+	PAD_CFG_GPO(GPP_B14, 0, PLTRST),				/* Top Swap		[ Disabled / Enabled  ] */
+	PAD_CFG_GPO(GPP_B18, 0, PLTRST),				/* Reboot Support	[ Enabled  / Disabled ] */
+	PAD_CFG_GPO(GPP_C2, 1, PLTRST),					/* TLS Confidentiality	[ Disabled / Enabled  ] */
+	PAD_CFG_GPO(GPP_C5, 0, PLTRST),					/* eSPI			[ Enabled  / Disabled ] */
+	PAD_CFG_GPO(GPP_E6, 0, PLTRST),					/* JTAG ODT		[ Disabled / Enabled  ] */
+	PAD_CFG_GPO(GPP_H1, 0, PLTRST),					/* BFX Strap 2 Bit 3	[ Disabled / Enabled  ] */
+	PAD_CFG_GPO(GPP_F2, 1, PLTRST),					/* M.2 CNVi		[ Enabled  / Disabled ] */
+	PAD_CFG_GPO(GPP_E19, 0, PLTRST),				/* TBT LSX #0		[ 1.8V     / 3.3V     ] */
+	PAD_CFG_GPO(GPP_E21, 0, PLTRST),				/* TBT LSX #1           [ 1.8V     / 3.3V     ] */
+	PAD_CFG_GPO(GPP_D10, 0, PLTRST),				/* TBT LSX #2		[ 1.8V     / 3.3V     ] */
+	PAD_CFG_GPO(GPP_D12, 0, PLTRST),				/* TBT LSX #3		[ 1.8V     / 3.3V     ] */
+	PAD_CFG_GPO(GPP_F7, 0, PLTRST),					/* MCRO LDO		[ Disabled / Bypass   ] */
+	PAD_CFG_GPO(GPD7, 0, PLTRST),					/* RTC Clock Delay	[ Disabled / 95ms     ] */
 
 	PAD_NC(GPD2, NONE),
 	PAD_NC(GPD6, NONE),
diff --git a/src/mainboard/starlabs/starbook/variants/mtl/gpio.c b/src/mainboard/starlabs/starbook/variants/mtl/gpio.c
index 618df01b19..435840cf8e 100644
--- a/src/mainboard/starlabs/starbook/variants/mtl/gpio.c
+++ b/src/mainboard/starlabs/starbook/variants/mtl/gpio.c
@@ -79,15 +79,15 @@ const struct pad_config gpio_table[] = {
 	PAD_CFG_GPI_APIC_LOW(GPP_F13, NONE, PLTRST),			/* Interrupt */
 
 	/* Config Straps									[ Low      / High     ] */
-	PAD_CFG_GPO(GPP_B14, 0, RSMRST),				/* Top Swap		[ Disabled / Enabled  ] */
-	PAD_CFG_GPO(GPP_B04, 0, RSMRST),				/* Reboot Support	[ Enabled  / Disabled ] */
-	PAD_CFG_GPO(GPP_C02, 1, RSMRST),				/* TLS Confidentiality	[ Disabled / Enabled  ] */
-	PAD_CFG_GPO(GPP_C05, 0, RSMRST),				/* eSPI			[ Enabled  / Disabled ] */
-	PAD_CFG_GPO(GPP_E06, 0, RSMRST),				/* JTAG ODT		[ Disabled / Enabled  ] */
-	PAD_CFG_GPO(GPP_F02, 0, RSMRST),				/* M.2 CNVi		[ Enabled  / Disabled ] */
-	PAD_CFG_GPO(GPP_H01, 0, RSMRST),				/* Flash Recovery	[ Disabled / Enabled  ] */
-	PAD_CFG_GPO(GPP_F20, 0, RSMRST),				/* SVID			[ Present  / Disabled ] */
-	PAD_CFG_GPO(GPP_F21, 0, RSMRST),				/* CCD			[ BSSB-LS  / BALTIC   ] */
+	PAD_CFG_GPO(GPP_B14, 0, PLTRST),				/* Top Swap		[ Disabled / Enabled  ] */
+	PAD_CFG_GPO(GPP_B04, 0, PLTRST),				/* Reboot Support	[ Enabled  / Disabled ] */
+	PAD_CFG_GPO(GPP_C02, 1, PLTRST),				/* TLS Confidentiality	[ Disabled / Enabled  ] */
+	PAD_CFG_GPO(GPP_C05, 0, PLTRST),				/* eSPI			[ Enabled  / Disabled ] */
+	PAD_CFG_GPO(GPP_E06, 0, PLTRST),				/* JTAG ODT		[ Disabled / Enabled  ] */
+	PAD_CFG_GPO(GPP_F02, 0, PLTRST),				/* M.2 CNVi		[ Enabled  / Disabled ] */
+	PAD_CFG_GPO(GPP_H01, 0, PLTRST),				/* Flash Recovery	[ Disabled / Enabled  ] */
+	PAD_CFG_GPO(GPP_F20, 0, PLTRST),				/* SVID			[ Present  / Disabled ] */
+	PAD_CFG_GPO(GPP_F21, 0, PLTRST),				/* CCD			[ BSSB-LS  / BALTIC   ] */
 
 	PAD_NC(GPP_V02, NONE),
 	PAD_NC(GPP_V06, NONE),
diff --git a/src/mainboard/starlabs/starbook/variants/tgl/gpio.c b/src/mainboard/starlabs/starbook/variants/tgl/gpio.c
index 0bb71f4130..f36b9a3ba3 100644
--- a/src/mainboard/starlabs/starbook/variants/tgl/gpio.c
+++ b/src/mainboard/starlabs/starbook/variants/tgl/gpio.c
@@ -94,18 +94,18 @@ const struct pad_config gpio_table[] = {
 	PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1),				/* Data */
 
 	/* Config Straps 									[ Low      / High     ] */
-	PAD_CFG_GPO(GPP_B14, 0, RSMRST),				/* Top Swap		[ Disabled / Enabled  ] */
-	PAD_CFG_GPO(GPP_B18, 0, RSMRST),				/* Reboot Support	[ Enabled  / Disabled ] */
-	PAD_CFG_GPO(GPP_C2, 1, RSMRST),					/* TLS Confidentiality	[ Disabled / Enabled  ] */
-	PAD_CFG_GPO(GPP_B22, 0, RSMRST),				/* eSPI			[ Enabled  / Disabled ] */
-	PAD_CFG_GPO(GPP_E6, 0, RSMRST),					/* JTAG ODT		[ Disabled / Enabled  ] */
-	PAD_CFG_GPO(GPP_C5, 0, RSMRST),					/* BFX Strap 2 Bit 1	[ Disabled / Enabled  ] */
-	PAD_CFG_GPO(GPP_H0, 0, RSMRST),					/* BFX Strap 2 Bit 2	[ Disabled / Enabled  ] */
-	PAD_CFG_GPO(GPP_H1, 0, RSMRST),					/* BFX Strap 2 Bit 3	[ Disabled / Enabled  ] */
-	PAD_CFG_GPO(GPP_H2, 0, RSMRST),					/* BFX Strap 2 Bit 4	[ Disabled / Enabled  ] */
-	PAD_CFG_GPO(GPP_E21, 0, RSMRST),				/* TBT LSX #1		[ 1,8V     / 3.3V     ] */
-	PAD_CFG_GPO(GPP_F7, 0, RSMRST),					/* MCRO LDO		[ Disabled / Bypass   ] */
-	PAD_CFG_GPO(GPD7, 0, RSMRST),					/* RTC Clock Delay	[ Disabled / 95ms     ] */
+	PAD_CFG_GPO(GPP_B14, 0, PLTRST),				/* Top Swap		[ Disabled / Enabled  ] */
+	PAD_CFG_GPO(GPP_B18, 0, PLTRST),				/* Reboot Support	[ Enabled  / Disabled ] */
+	PAD_CFG_GPO(GPP_C2, 1, PLTRST),					/* TLS Confidentiality	[ Disabled / Enabled  ] */
+	PAD_CFG_GPO(GPP_B22, 0, PLTRST),				/* eSPI			[ Enabled  / Disabled ] */
+	PAD_CFG_GPO(GPP_E6, 0, PLTRST),					/* JTAG ODT		[ Disabled / Enabled  ] */
+	PAD_CFG_GPO(GPP_C5, 0, PLTRST),					/* BFX Strap 2 Bit 1	[ Disabled / Enabled  ] */
+	PAD_CFG_GPO(GPP_H0, 0, PLTRST),					/* BFX Strap 2 Bit 2	[ Disabled / Enabled  ] */
+	PAD_CFG_GPO(GPP_H1, 0, PLTRST),					/* BFX Strap 2 Bit 3	[ Disabled / Enabled  ] */
+	PAD_CFG_GPO(GPP_H2, 0, PLTRST),					/* BFX Strap 2 Bit 4	[ Disabled / Enabled  ] */
+	PAD_CFG_GPO(GPP_E21, 0, PLTRST),				/* TBT LSX #1		[ 1,8V     / 3.3V     ] */
+	PAD_CFG_GPO(GPP_F7, 0, PLTRST),					/* MCRO LDO		[ Disabled / Bypass   ] */
+	PAD_CFG_GPO(GPD7, 0, PLTRST),					/* RTC Clock Delay	[ Disabled / 95ms     ] */
 	PAD_CFG_GPO(GPP_B23, 0, DEEP),					/* CPUNSSC		[ 19.2MHz  / 38.4MHz  ] */
 	PAD_CFG_GPO(GPP_F10, 0, DEEP),					/* XTAL Mode		[ Attached / Single   ] */
 
diff --git a/src/mainboard/starlabs/starfighter/variants/rpl/gpio.c b/src/mainboard/starlabs/starfighter/variants/rpl/gpio.c
index 82872e8413..0195ac9033 100644
--- a/src/mainboard/starlabs/starfighter/variants/rpl/gpio.c
+++ b/src/mainboard/starlabs/starfighter/variants/rpl/gpio.c
@@ -100,15 +100,15 @@ const struct pad_config gpio_table[] = {
 	PAD_CFG_GPO(GPP_E8, 1, DEEP),					/* DRAM Sleep */
 
 	/* Config Straps 									[ Low      / High     ] */
-	PAD_CFG_GPO(GPP_B14, 0, RSMRST),				/* Top Swap		[ Disabled / Enabled  ] */
-	PAD_CFG_GPO(GPP_B18, 0, RSMRST),				/* Reboot Support	[ Enabled  / Disabled ] */
-	PAD_CFG_GPO(GPP_C2, 1, RSMRST),					/* TLS Confidentiality	[ Disabled / Enabled  ] */
-	PAD_CFG_GPO(GPP_C5, 0, RSMRST),					/* eSPI			[ Enabled  / Disabled ] */
-	PAD_CFG_GPO(GPP_E6, 0, RSMRST),					/* JTAG ODT		[ Disabled / Enabled  ] */
-	PAD_CFG_GPO(GPP_H1, 0, RSMRST),					/* BFX Strap 2 Bit 3	[ Disabled / Enabled  ] */
-	PAD_CFG_GPO(GPP_F2, 1, RSMRST),					/* M.2 CNVi		[ Enabled  / Disabled ] */
-	PAD_CFG_GPO(GPP_F7, 0, RSMRST),					/* MCRO LDO		[ Disabled / Bypass   ] */
-	PAD_CFG_GPO(GPD7, 0, RSMRST),					/* RTC Clock Delay	[ Disabled / 95ms     ] */
+	PAD_CFG_GPO(GPP_B14, 0, PLTRST),				/* Top Swap		[ Disabled / Enabled  ] */
+	PAD_CFG_GPO(GPP_B18, 0, PLTRST),				/* Reboot Support	[ Enabled  / Disabled ] */
+	PAD_CFG_GPO(GPP_C2, 1, PLTRST),					/* TLS Confidentiality	[ Disabled / Enabled  ] */
+	PAD_CFG_GPO(GPP_C5, 0, PLTRST),					/* eSPI			[ Enabled  / Disabled ] */
+	PAD_CFG_GPO(GPP_E6, 0, PLTRST),					/* JTAG ODT		[ Disabled / Enabled  ] */
+	PAD_CFG_GPO(GPP_H1, 0, PLTRST),					/* BFX Strap 2 Bit 3	[ Disabled / Enabled  ] */
+	PAD_CFG_GPO(GPP_F2, 1, PLTRST),					/* M.2 CNVi		[ Enabled  / Disabled ] */
+	PAD_CFG_GPO(GPP_F7, 0, PLTRST),					/* MCRO LDO		[ Disabled / Bypass   ] */
+	PAD_CFG_GPO(GPD7, 0, PLTRST),					/* RTC Clock Delay	[ Disabled / 95ms     ] */
 
 	PAD_NC(GPD2, NONE),
 	PAD_NC(GPD6, NONE),
diff --git a/src/mainboard/starlabs/starlite_adl/variants/mk_v/gpio.c b/src/mainboard/starlabs/starlite_adl/variants/mk_v/gpio.c
index 09cd782f54..9cf3a3e2bd 100644
--- a/src/mainboard/starlabs/starlite_adl/variants/mk_v/gpio.c
+++ b/src/mainboard/starlabs/starlite_adl/variants/mk_v/gpio.c
@@ -91,18 +91,18 @@ const struct pad_config gpio_table[] = {
 	PAD_CFG_GPO(GPP_E8, 1, DEEP),					/* DRAM Sleep */
 
 	/* Config Straps 									[ Low      / High     ] */
-	PAD_CFG_GPO(GPP_B14, 0, RSMRST),				/* Top Swap		[ Disabled / Enabled  ] */
-	PAD_CFG_GPO(GPP_B18, 0, RSMRST),				/* Reboot Support	[ Enabled  / Disabled ] */
-	PAD_CFG_GPO(GPP_C2, 1, RSMRST),					/* TLS Confidentiality	[ Disabled / Enabled  ] */
-	PAD_CFG_GPO(GPP_C5, 0, RSMRST),					/* eSPI			[ Enabled  / Disabled ] */
-	PAD_CFG_GPO(GPP_E6, 0, RSMRST),					/* JTAG ODT		[ Disabled / Enabled  ] */
-	PAD_CFG_GPO(GPP_H1, 0, RSMRST),					/* BFX Strap 2 Bit 3	[ Disabled / Enabled  ] */
-	PAD_CFG_GPO(GPP_E19, 0, RSMRST),				/* TBT LSX #0		[ 1.8V     / 3.3V     ] */
-	PAD_CFG_GPO(GPP_E21, 0, RSMRST),				/* TBT LSX #1           [ 1.8V     / 3.3V     ] */
-	PAD_CFG_GPO(GPP_D10, 0, RSMRST),				/* TBT LSX #2		[ 1.8V     / 3.3V     ] */
-	PAD_CFG_GPO(GPP_D12, 0, RSMRST),				/* TBT LSX #3		[ 1.8V     / 3.3V     ] */
-	PAD_CFG_GPO(GPP_F7, 0, RSMRST),					/* MCRO LDO		[ Disabled / Bypass   ] */
-	PAD_CFG_GPO(GPD7, 0, RSMRST),					/* RTC Clock Delay	[ Disabled / 95ms     ] */
+	PAD_CFG_GPO(GPP_B14, 0, PLTRST),				/* Top Swap		[ Disabled / Enabled  ] */
+	PAD_CFG_GPO(GPP_B18, 0, PLTRST),				/* Reboot Support	[ Enabled  / Disabled ] */
+	PAD_CFG_GPO(GPP_C2, 1, PLTRST),					/* TLS Confidentiality	[ Disabled / Enabled  ] */
+	PAD_CFG_GPO(GPP_C5, 0, PLTRST),					/* eSPI			[ Enabled  / Disabled ] */
+	PAD_CFG_GPO(GPP_E6, 0, PLTRST),					/* JTAG ODT		[ Disabled / Enabled  ] */
+	PAD_CFG_GPO(GPP_H1, 0, PLTRST),					/* BFX Strap 2 Bit 3	[ Disabled / Enabled  ] */
+	PAD_CFG_GPO(GPP_E19, 0, PLTRST),				/* TBT LSX #0		[ 1.8V     / 3.3V     ] */
+	PAD_CFG_GPO(GPP_E21, 0, PLTRST),				/* TBT LSX #1           [ 1.8V     / 3.3V     ] */
+	PAD_CFG_GPO(GPP_D10, 0, PLTRST),				/* TBT LSX #2		[ 1.8V     / 3.3V     ] */
+	PAD_CFG_GPO(GPP_D12, 0, PLTRST),				/* TBT LSX #3		[ 1.8V     / 3.3V     ] */
+	PAD_CFG_GPO(GPP_F7, 0, PLTRST),					/* MCRO LDO		[ Disabled / Bypass   ] */
+	PAD_CFG_GPO(GPD7, 0, PLTRST),					/* RTC Clock Delay	[ Disabled / 95ms     ] */
 
 	PAD_NC(GPD2, NONE),
 	PAD_NC(GPD6, NONE),

From 6ebd30bf7d147801d05eb851be5c20ca6179c895 Mon Sep 17 00:00:00 2001
From: Nick Vaccaro <nvaccaro@google.com>
Date: Wed, 11 Jun 2025 13:04:07 -0700
Subject: [PATCH 1311/3886] mb/google/ocelot: add BOARD_GOOGLE_OCELOTITE

Ocelotite is the same as the ocelot veriant except that it uses the
ITE EC.

BUG=b:419856369
BRANCH=None
TEST=`emerge-ocelot coreboot` and verify it builds without error.

Change-Id: I1871d5772ea1a73d55d49bdac5b00a17f524eeeb
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88059
Reviewed-by: Pranava Y N <pranavayn@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/google/ocelot/Kconfig                       | 8 +++++++-
 src/mainboard/google/ocelot/Kconfig.name                  | 3 +++
 .../variants/baseboard/ocelot/include/baseboard/gpio.h    | 2 +-
 3 files changed, 11 insertions(+), 2 deletions(-)

diff --git a/src/mainboard/google/ocelot/Kconfig b/src/mainboard/google/ocelot/Kconfig
index 669b0ea83f..e87eaaef00 100644
--- a/src/mainboard/google/ocelot/Kconfig
+++ b/src/mainboard/google/ocelot/Kconfig
@@ -67,6 +67,9 @@ config BOARD_GOOGLE_MODEL_OCELOT
 config BOARD_GOOGLE_OCELOT
 	select BOARD_GOOGLE_MODEL_OCELOT
 
+config BOARD_GOOGLE_OCELOTITE
+	select BOARD_GOOGLE_MODEL_OCELOT
+
 if BOARD_GOOGLE_OCELOT_COMMON
 
 config BASEBOARD_DIR
@@ -114,6 +117,7 @@ config MAINBOARD_FAMILY
 
 config MAINBOARD_PART_NUMBER
 	default "Ocelot" if BOARD_GOOGLE_OCELOT
+	default "Ocelotite" if BOARD_GOOGLE_OCELOTITE
 
 config MEMORY_SOLDERDOWN
 	def_bool n
@@ -133,7 +137,9 @@ config USE_PM_ACPI_TIMER
 
 config VARIANT_DIR
 	string
-	default "ocelot" if BOARD_GOOGLE_OCELOT
+	default "ocelot" if \
+		BOARD_GOOGLE_OCELOT || \
+		BOARD_GOOGLE_OCELOTITE
 
 config OVERRIDE_DEVICETREE
 	default "variants/\$(CONFIG_VARIANT_DIR)/overridetree.cb"
diff --git a/src/mainboard/google/ocelot/Kconfig.name b/src/mainboard/google/ocelot/Kconfig.name
index e79c4b484a..8c025619fe 100644
--- a/src/mainboard/google/ocelot/Kconfig.name
+++ b/src/mainboard/google/ocelot/Kconfig.name
@@ -4,3 +4,6 @@ comment "Ocelot"
 
 config BOARD_GOOGLE_OCELOT
 	bool "-> Ocelot"
+
+config BOARD_GOOGLE_OCELOTITE
+	bool "-> Ocelotite"
diff --git a/src/mainboard/google/ocelot/variants/baseboard/ocelot/include/baseboard/gpio.h b/src/mainboard/google/ocelot/variants/baseboard/ocelot/include/baseboard/gpio.h
index 2cc9e7407a..126b2a764d 100644
--- a/src/mainboard/google/ocelot/variants/baseboard/ocelot/include/baseboard/gpio.h
+++ b/src/mainboard/google/ocelot/variants/baseboard/ocelot/include/baseboard/gpio.h
@@ -13,7 +13,7 @@
  * GPIO_PCH_WP - WP signal to PCH
  */
 //TODO for Nuvo: #define EC_SYNC_IRQ	GPP_E07_IRQ
-#if CONFIG(BOARD_GOOGLE_OCELOT)
+#if CONFIG(BOARD_GOOGLE_OCELOT) || CONFIG(BOARD_GOOGLE_OCELOTITE)
  #define EC_SYNC_IRQ	0 /* Not Connected */
 #endif
 #define GPIO_PCH_WP	GPP_D02

From 3696fea4e064ddeb301d33ec0086ac6646c7507c Mon Sep 17 00:00:00 2001
From: Nick Vaccaro <nvaccaro@google.com>
Date: Wed, 11 Jun 2025 13:05:22 -0700
Subject: [PATCH 1312/3886] mb/google/ocelot: add BOARD_GOOGLE_OCELOTMCHP

Ocelotmchp is the same as the ocelot variant except that it uses the
Microchip EC.

BUG=b:419857124
BRANCH=none
TEST=`emerge-ocelot coreboot` and verify it builds without error.

Change-Id: I9088a57289d9ef489a7773a8d828d5f945440757
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88060
Reviewed-by: Pranava Y N <pranavayn@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/google/ocelot/Kconfig                        | 7 ++++++-
 src/mainboard/google/ocelot/Kconfig.name                   | 3 +++
 .../variants/baseboard/ocelot/include/baseboard/gpio.h     | 4 +++-
 3 files changed, 12 insertions(+), 2 deletions(-)

diff --git a/src/mainboard/google/ocelot/Kconfig b/src/mainboard/google/ocelot/Kconfig
index e87eaaef00..582084ee83 100644
--- a/src/mainboard/google/ocelot/Kconfig
+++ b/src/mainboard/google/ocelot/Kconfig
@@ -70,6 +70,9 @@ config BOARD_GOOGLE_OCELOT
 config BOARD_GOOGLE_OCELOTITE
 	select BOARD_GOOGLE_MODEL_OCELOT
 
+config BOARD_GOOGLE_OCELOTMCHP
+	select BOARD_GOOGLE_MODEL_OCELOT
+
 if BOARD_GOOGLE_OCELOT_COMMON
 
 config BASEBOARD_DIR
@@ -118,6 +121,7 @@ config MAINBOARD_FAMILY
 config MAINBOARD_PART_NUMBER
 	default "Ocelot" if BOARD_GOOGLE_OCELOT
 	default "Ocelotite" if BOARD_GOOGLE_OCELOTITE
+	default "Ocelotmchp" if BOARD_GOOGLE_OCELOTMCHP
 
 config MEMORY_SOLDERDOWN
 	def_bool n
@@ -139,7 +143,8 @@ config VARIANT_DIR
 	string
 	default "ocelot" if \
 		BOARD_GOOGLE_OCELOT || \
-		BOARD_GOOGLE_OCELOTITE
+		BOARD_GOOGLE_OCELOTITE || \
+		BOARD_GOOGLE_OCELOTMCHP
 
 config OVERRIDE_DEVICETREE
 	default "variants/\$(CONFIG_VARIANT_DIR)/overridetree.cb"
diff --git a/src/mainboard/google/ocelot/Kconfig.name b/src/mainboard/google/ocelot/Kconfig.name
index 8c025619fe..3be6f46017 100644
--- a/src/mainboard/google/ocelot/Kconfig.name
+++ b/src/mainboard/google/ocelot/Kconfig.name
@@ -7,3 +7,6 @@ config BOARD_GOOGLE_OCELOT
 
 config BOARD_GOOGLE_OCELOTITE
 	bool "-> Ocelotite"
+
+config BOARD_GOOGLE_OCELOTMCHP
+	bool "-> Ocelotmchp"
diff --git a/src/mainboard/google/ocelot/variants/baseboard/ocelot/include/baseboard/gpio.h b/src/mainboard/google/ocelot/variants/baseboard/ocelot/include/baseboard/gpio.h
index 126b2a764d..6a43d70708 100644
--- a/src/mainboard/google/ocelot/variants/baseboard/ocelot/include/baseboard/gpio.h
+++ b/src/mainboard/google/ocelot/variants/baseboard/ocelot/include/baseboard/gpio.h
@@ -13,7 +13,9 @@
  * GPIO_PCH_WP - WP signal to PCH
  */
 //TODO for Nuvo: #define EC_SYNC_IRQ	GPP_E07_IRQ
-#if CONFIG(BOARD_GOOGLE_OCELOT) || CONFIG(BOARD_GOOGLE_OCELOTITE)
+#if CONFIG(BOARD_GOOGLE_OCELOT) || \
+	CONFIG(BOARD_GOOGLE_OCELOTITE) || \
+	CONFIG(BOARD_GOOGLE_OCELOTMCHP)
  #define EC_SYNC_IRQ	0 /* Not Connected */
 #endif
 #define GPIO_PCH_WP	GPP_D02

From 4d9dfb63bd534d5eb5257a9e4c2321b39bb875c6 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Rapha=C3=ABl=20M=C3=A9lotte?= <raphael.melotte@mind.be>
Date: Thu, 12 Jun 2025 12:02:07 +0200
Subject: [PATCH 1313/3886] Documentation: fix broken flashrom.org link
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

The old wiki no longer exists (see the announcement at [1]), the
current URLs lead to an HTTP 404.

To fix it, replace the URLs with the main page URL, which contains
links to the current documentation, manual, etc.

[1]: https://mail.coreboot.org/hyperkitty/list/flashrom@flashrom.org/thread/GNT23GQEQ5I5JCJ6YKUSRXD7JORSG4RV/

Change-Id: Ifb430a033d12f8064893f75315d577b5e78ffc9e
Signed-off-by: Raphaël Mélotte <raphael.melotte@mind.be>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88072
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
---
 Documentation/mainboard/asrock/h110m-dvs.md                     | 2 +-
 Documentation/mainboard/asrock/h81m-hds.md                      | 2 +-
 Documentation/mainboard/asrock/imb-1222.md                      | 2 +-
 Documentation/mainboard/asus/a88xm-e.md                         | 2 +-
 Documentation/mainboard/asus/f2a85-m.md                         | 2 +-
 Documentation/mainboard/asus/p2b-ls.md                          | 2 +-
 Documentation/mainboard/asus/p3b-f.md                           | 2 +-
 Documentation/mainboard/asus/p8c_ws.md                          | 2 +-
 Documentation/mainboard/asus/p8h61-m_lx.md                      | 2 +-
 Documentation/mainboard/asus/p8h61-m_pro.md                     | 2 +-
 Documentation/mainboard/asus/p8h77-v.md                         | 2 +-
 Documentation/mainboard/asus/p8z77-m.md                         | 2 +-
 Documentation/mainboard/asus/p8z77-m_pro.md                     | 2 +-
 Documentation/mainboard/asus/p8z77-v.md                         | 2 +-
 Documentation/mainboard/asus/p8z77-v_le_plus.md                 | 2 +-
 Documentation/mainboard/dell/optiplex_9010.md                   | 2 +-
 Documentation/mainboard/erying/tgl/tgl_matx.md                  | 2 +-
 Documentation/mainboard/facebook/fbg1701.md                     | 2 +-
 Documentation/mainboard/facebook/monolith.md                    | 2 +-
 Documentation/mainboard/foxconn/d41s.md                         | 2 +-
 Documentation/mainboard/gigabyte/ga-h61m-s2pv.md                | 2 +-
 Documentation/mainboard/hp/compaq_8200_sff.md                   | 2 +-
 Documentation/mainboard/hp/compaq_8300_sff.md                   | 2 +-
 Documentation/mainboard/hp/pro_3x00_series.md                   | 2 +-
 Documentation/mainboard/hp/z220_sff.md                          | 2 +-
 Documentation/mainboard/intel/dg43gt.md                         | 2 +-
 Documentation/mainboard/intel/kblrvp11.md                       | 2 +-
 Documentation/mainboard/kontron/mal10.md                        | 2 +-
 Documentation/mainboard/lenovo/m920q.md                         | 2 +-
 Documentation/mainboard/libretrend/lt1000.md                    | 2 +-
 Documentation/mainboard/ocp/deltalake.md                        | 2 +-
 Documentation/mainboard/ocp/tiogapass.md                        | 2 +-
 Documentation/mainboard/opencellular/elgon.md                   | 2 +-
 Documentation/mainboard/pcengines/apu1.md                       | 2 +-
 Documentation/mainboard/pcengines/apu2.md                       | 2 +-
 Documentation/mainboard/portwell/pq7-m107.md                    | 2 +-
 Documentation/mainboard/prodrive/hermes.md                      | 2 +-
 Documentation/mainboard/protectli/fw2b_fw4b.md                  | 2 +-
 Documentation/mainboard/protectli/fw6.md                        | 2 +-
 Documentation/mainboard/protectli/vp2420.md                     | 2 +-
 Documentation/mainboard/protectli/vp46xx.md                     | 2 +-
 Documentation/mainboard/purism/librem_14.md                     | 2 +-
 Documentation/mainboard/purism/librem_mini.md                   | 2 +-
 Documentation/mainboard/sifive/hifive-unleashed.md              | 2 +-
 Documentation/mainboard/supermicro/x10slm-f.md                  | 2 +-
 .../supermicro/x11-lga1151-series/x11-lga1151-series.md         | 2 +-
 Documentation/mainboard/supermicro/x9sae.md                     | 2 +-
 Documentation/mainboard/topton/adl/x2f-n100.md                  | 2 +-
 48 files changed, 48 insertions(+), 48 deletions(-)

diff --git a/Documentation/mainboard/asrock/h110m-dvs.md b/Documentation/mainboard/asrock/h110m-dvs.md
index b3c484ef94..ef9d164bc1 100644
--- a/Documentation/mainboard/asrock/h110m-dvs.md
+++ b/Documentation/mainboard/asrock/h110m-dvs.md
@@ -130,5 +130,5 @@ facing towards the bottom of the board.
 
 [ASRock H110M-DVS]: https://www.asrock.com/mb/Intel/H110M-DVS%20R2.0/
 [MX25L6473E]: http://www.macronix.com/Lists/Datasheet/Attachments/7380/MX25L6473E,%203V,%2064Mb,%20v1.4.pdf
-[flashrom]: https://flashrom.org/Flashrom
+[flashrom]: https://flashrom.org/
 [H110M-DVS manual]: https://web.archive.org/web/20191023230631/http://asrock.pc.cdn.bitgravity.com/Manual/H110M-DVS%20R2.0.pdf
diff --git a/Documentation/mainboard/asrock/h81m-hds.md b/Documentation/mainboard/asrock/h81m-hds.md
index 5cbaa7fc55..0ba17b2735 100644
--- a/Documentation/mainboard/asrock/h81m-hds.md
+++ b/Documentation/mainboard/asrock/h81m-hds.md
@@ -129,5 +129,5 @@ Please also see :doc:`../../northbridge/intel/haswell/known-issues`.
 
 [ASRock H81M-HDS]: https://www.asrock.com/mb/Intel/H81M-HDS/
 [W25Q32FV]: https://www.winbond.com/resource-files/w25q32fv%20revi%2010202015.pdf
-[flashrom]: https://flashrom.org/Flashrom
+[flashrom]: https://flashrom.org/
 [Board manual]: https://web.archive.org/web/20191231093418/http://asrock.pc.cdn.bitgravity.com/Manual/H81M-HDS.pdf
diff --git a/Documentation/mainboard/asrock/imb-1222.md b/Documentation/mainboard/asrock/imb-1222.md
index 5ef934753e..dcc891c5b5 100644
--- a/Documentation/mainboard/asrock/imb-1222.md
+++ b/Documentation/mainboard/asrock/imb-1222.md
@@ -239,7 +239,7 @@ information about this [here](../../tutorial/flashing_firmware/index.md).
 
 [ASRock IMB-1222]: https://web.archive.org/web/20220924171403/https://www.asrockind.com/en-gb/IMB-1222
 [vendor's firmware]: https://web.archive.org/web/20250413105432/https://download.asrock.com/IPC/BIOS/IMB-1222(1.80)ROM.zip
-[flashrom]: https://flashrom.org/Flashrom
+[flashrom]: https://flashrom.org/
 [MrChromebox fork]: https://github.com/MrChromebox/edk2
 [XutaxKamay fork]: https://github.com/XutaxKamay/me_cleaner
 [Bliss OS]: https://blissos.org/
diff --git a/Documentation/mainboard/asus/a88xm-e.md b/Documentation/mainboard/asus/a88xm-e.md
index dbfb99c9f7..628635f184 100644
--- a/Documentation/mainboard/asus/a88xm-e.md
+++ b/Documentation/mainboard/asus/a88xm-e.md
@@ -162,7 +162,7 @@ Tested even with/without the Bolton and Hudson blobs.
 
 [ASUS A88XM-E]: https://www.asus.com/Motherboards/A88XME/
 [Board manual]: https://dlcdnets.asus.com/pub/ASUS/mb/SocketFM2/A88XM-E/E9125_A88XM-E.pdf
-[flashrom]: https://flashrom.org/Flashrom
+[flashrom]: https://flashrom.org/
 [GD25Q64]: http://www.elm-tech.com/ja/products/spi-flash-memory/gd25q64/gd25q64.pdf
 [Piledriver]: https://en.wikipedia.org/wiki/Piledriver_%28microarchitecture%29#APU_lines
 [Sea Islands]: https://en.wikipedia.org/wiki/Graphics_Core_Next#GCN_2nd_generation
diff --git a/Documentation/mainboard/asus/f2a85-m.md b/Documentation/mainboard/asus/f2a85-m.md
index 790a2f7592..61b5b86c56 100644
--- a/Documentation/mainboard/asus/f2a85-m.md
+++ b/Documentation/mainboard/asus/f2a85-m.md
@@ -192,7 +192,7 @@ This version is usable for all the GPUs.
 
 [ASUS F2A85-M]: https://web.archive.org/web/20160320065008/http://www.asus.com/Motherboards/F2A85M/
 [Board manual]: https://web.archive.org/web/20211028063105/https://dlcdnets.asus.com/pub/ASUS/mb/SocketFM2/F2A85-M/E8005_F2A85-M.pdf
-[flashrom]: https://flashrom.org/Flashrom
+[flashrom]: https://flashrom.org/
 [Piledriver]: https://en.wikipedia.org/wiki/Piledriver_%28microarchitecture%29#APU_lines
 [TeraScale 3]: https://en.wikipedia.org/wiki/TeraScale_%28microarchitecture%29#TeraScale_3
 [W25Q64FV]: https://web.archive.org/web/20220127184640/https://www.winbond.com/resource-files/w25q64fv%20revs%2007182017.pdf
diff --git a/Documentation/mainboard/asus/p2b-ls.md b/Documentation/mainboard/asus/p2b-ls.md
index c1bb1c4bd9..e633bf9326 100644
--- a/Documentation/mainboard/asus/p2b-ls.md
+++ b/Documentation/mainboard/asus/p2b-ls.md
@@ -105,4 +105,4 @@ for only CPU models that the board will actually be run with.
 
 ## Extra resources
 
-[flashrom]: https://flashrom.org/Flashrom
+[flashrom]: https://flashrom.org/
diff --git a/Documentation/mainboard/asus/p3b-f.md b/Documentation/mainboard/asus/p3b-f.md
index addc7d9cef..13d068e517 100644
--- a/Documentation/mainboard/asus/p3b-f.md
+++ b/Documentation/mainboard/asus/p3b-f.md
@@ -103,4 +103,4 @@ for only CPU models that the board will actually be run with.
 
 ## Extra resources
 
-[flashrom]: https://flashrom.org/Flashrom
+[flashrom]: https://flashrom.org/
diff --git a/Documentation/mainboard/asus/p8c_ws.md b/Documentation/mainboard/asus/p8c_ws.md
index 63f80acde2..6b0c2bc26f 100644
--- a/Documentation/mainboard/asus/p8c_ws.md
+++ b/Documentation/mainboard/asus/p8c_ws.md
@@ -91,4 +91,4 @@ flash externally.
 
 [ASUS P8C WS]: https://www.asus.com/supportonly/p8c_ws/helpdesk_knowledge/
 [W25Q64FVA1Q]: https://www.winbond.com/resource-files/w25q64fv%20revs%2007182017.pdf
-[flashrom]: https://flashrom.org/Flashrom
+[flashrom]: https://flashrom.org/
diff --git a/Documentation/mainboard/asus/p8h61-m_lx.md b/Documentation/mainboard/asus/p8h61-m_lx.md
index cc0dfb132f..a2adcdbec9 100644
--- a/Documentation/mainboard/asus/p8h61-m_lx.md
+++ b/Documentation/mainboard/asus/p8h61-m_lx.md
@@ -107,5 +107,5 @@ region is not readable even by the host.
 
 [ASUS P8H61-M LX]: https://www.asus.com/Motherboards/P8H61M_LX/
 [W25Q32BV]: https://web.archive.org/web/20211002141814/https://www.winbond.com/resource-files/w25q32bv_revi_100413_wo_automotive.pdf
-[flashrom]: https://flashrom.org/Flashrom
+[flashrom]: https://flashrom.org/
 [Board manual]: http://dlcdnet.asus.com/pub/ASUS/mb/LGA1155/P8H61_M_LX/E6803_P8H61-M_LX.zip
diff --git a/Documentation/mainboard/asus/p8h61-m_pro.md b/Documentation/mainboard/asus/p8h61-m_pro.md
index 3f9bf366f8..cb6d812824 100644
--- a/Documentation/mainboard/asus/p8h61-m_pro.md
+++ b/Documentation/mainboard/asus/p8h61-m_pro.md
@@ -100,4 +100,4 @@ region is not readable even by the host.
 
 [ASUS P8H61-M Pro]: https://www.asus.com/Motherboards/P8H61M_Pro/
 [W25Q32BV]: https://www.winbond.com/resource-files/w25q32bv_revi_100413_wo_automotive.pdf
-[flashrom]: https://flashrom.org/Flashrom
+[flashrom]: https://flashrom.org/
diff --git a/Documentation/mainboard/asus/p8h77-v.md b/Documentation/mainboard/asus/p8h77-v.md
index 7aec6c3c8f..ed0b3daff5 100644
--- a/Documentation/mainboard/asus/p8h77-v.md
+++ b/Documentation/mainboard/asus/p8h77-v.md
@@ -78,4 +78,4 @@ work. The flash chip is socketed, so it's easy to remove and reflash.
 
 [ASUS P8H77-V]: https://www.asus.com/supportonly/p8h77v/helpdesk_knowledge/
 [W25Q64FVA1Q]: https://www.winbond.com/resource-files/w25q64fv%20revs%2007182017.pdf
-[flashrom]: https://flashrom.org/Flashrom
+[flashrom]: https://flashrom.org/
diff --git a/Documentation/mainboard/asus/p8z77-m.md b/Documentation/mainboard/asus/p8z77-m.md
index 0929cb01c1..48490b60ff 100644
--- a/Documentation/mainboard/asus/p8z77-m.md
+++ b/Documentation/mainboard/asus/p8z77-m.md
@@ -169,4 +169,4 @@ The board has two onboard buttons, each with a related LED nearby.
 
 [ASUS P8Z77-M]: https://www.asus.com/supportonly/p8z77-m/helpdesk_manual/
 [W25Q64FVA1Q]: https://www.winbond.com/resource-files/w25q64fv%20revs%2007182017.pdf
-[flashrom]: https://flashrom.org/Flashrom
+[flashrom]: https://flashrom.org/
diff --git a/Documentation/mainboard/asus/p8z77-m_pro.md b/Documentation/mainboard/asus/p8z77-m_pro.md
index 93400bc0d1..94d12537c9 100644
--- a/Documentation/mainboard/asus/p8z77-m_pro.md
+++ b/Documentation/mainboard/asus/p8z77-m_pro.md
@@ -165,4 +165,4 @@ easy to remove and reflash.
 
 [ASUS P8Z77-M PRO]: https://www.asus.com/Motherboards/P8Z77M_PRO/
 [W25Q64FVA1Q]: https://www.winbond.com/resource-files/w25q64fv%20revs%2007182017.pdf
-[flashrom]: https://flashrom.org/Flashrom
+[flashrom]: https://flashrom.org/
diff --git a/Documentation/mainboard/asus/p8z77-v.md b/Documentation/mainboard/asus/p8z77-v.md
index e6ae9a8018..6b4d0accb1 100644
--- a/Documentation/mainboard/asus/p8z77-v.md
+++ b/Documentation/mainboard/asus/p8z77-v.md
@@ -108,5 +108,5 @@ See [Asus Wi-Fi Go! v1].
 
 [ASUS P8Z77-V]: https://www.asus.com/supportonly/p8z77v/helpdesk_knowledge/
 [W25Q64FVA1Q]: https://www.winbond.com/resource-files/w25q64fv%20revs%2007182017.pdf
-[flashrom]: https://flashrom.org/Flashrom
+[flashrom]: https://flashrom.org/
 [Asus Wi-Fi Go! v1]: ./wifigo_v1.md
diff --git a/Documentation/mainboard/asus/p8z77-v_le_plus.md b/Documentation/mainboard/asus/p8z77-v_le_plus.md
index dc80eeb8c3..3c4c977ef6 100644
--- a/Documentation/mainboard/asus/p8z77-v_le_plus.md
+++ b/Documentation/mainboard/asus/p8z77-v_le_plus.md
@@ -254,5 +254,5 @@ Pins 2, 4, 6, 8 have 1M ohm pulldowns.
 
 [ASUS P8Z77-V LE PLUS]: https://www.asus.com/supportonly/p8z77-v%20le%20plus/helpdesk_manual/
 [W25Q64FVA1Q]: https://www.winbond.com/resource-files/w25q64fv%20revs%2007182017.pdf
-[flashrom]: https://flashrom.org/Flashrom
+[flashrom]: https://flashrom.org/
 [rtnicpg]: https://github.com/redchenjs/rtnicpg
diff --git a/Documentation/mainboard/dell/optiplex_9010.md b/Documentation/mainboard/dell/optiplex_9010.md
index 31685913c0..a14406337c 100644
--- a/Documentation/mainboard/dell/optiplex_9010.md
+++ b/Documentation/mainboard/dell/optiplex_9010.md
@@ -142,6 +142,6 @@ the cables or not being populated on the board case.
 - Intruder detection
 - Wake-on-Lan from ACPI S3
 
-[flashrom]: https://flashrom.org/Flashrom
+[flashrom]: https://flashrom.org/
 [Dell OptiPlex 9010 specifications]: https://www.dell.com/downloads/global/products/optix/en/dell_optiplex_9010_spec_sheet.pdf
 [UEFITool]: https://github.com/LongSoft/UEFITool
diff --git a/Documentation/mainboard/erying/tgl/tgl_matx.md b/Documentation/mainboard/erying/tgl/tgl_matx.md
index 1234a1c0ee..76437fb607 100644
--- a/Documentation/mainboard/erying/tgl/tgl_matx.md
+++ b/Documentation/mainboard/erying/tgl/tgl_matx.md
@@ -199,5 +199,5 @@ corrupted framebuffer before modprobing with ReBAR enabled
 [MrChromebox's EDK2]: https://github.com/MrChromebox/edk2
 [elly's EDK2]: https://github.com/ellyq/edk2
 [GOP driver]: https://github.com/MrChromebox/blobs/blob/master/soc/intel/tgl/IntelGopDriver.efi
-[flashrom]: https://flashrom.org/Flashrom
+[flashrom]: https://flashrom.org/
 [flashprog]: https://flashprog.org/wiki/Flashprog
diff --git a/Documentation/mainboard/facebook/fbg1701.md b/Documentation/mainboard/facebook/fbg1701.md
index 0fa3db3efd..7aac686b12 100644
--- a/Documentation/mainboard/facebook/fbg1701.md
+++ b/Documentation/mainboard/facebook/fbg1701.md
@@ -77,4 +77,4 @@ Specifically, it's a Winbond W25Q64FV (3.3V), whose datasheet can be found
 
 [W25Q64FW]: https://www.winbond.com/resource-files/w25q64fw%20revn%2005182017%20sfdp.pdf
 [W25Q64FV]: https://www.winbond.com/resource-files/w25q64fv%20revs%2007182017.pdf
-[flashrom]: https://flashrom.org/Flashrom
+[flashrom]: https://flashrom.org/
diff --git a/Documentation/mainboard/facebook/monolith.md b/Documentation/mainboard/facebook/monolith.md
index da72e48148..48da864ec7 100644
--- a/Documentation/mainboard/facebook/monolith.md
+++ b/Documentation/mainboard/facebook/monolith.md
@@ -130,4 +130,4 @@ output.
 
 [W25Q128JVSIQ]: https://www.winbond.com/resource-files/w25q128jv%20revf%2003272018%20plus.pdf
 [W25Q128JVSIM]: https://www.winbond.com/resource-files/w25q128jv%20dtr%20revb%2011042016.pdf
-[flashrom]: https://flashrom.org/Flashrom
+[flashrom]: https://flashrom.org/
diff --git a/Documentation/mainboard/foxconn/d41s.md b/Documentation/mainboard/foxconn/d41s.md
index 45a86d4548..6c94af2f8a 100644
--- a/Documentation/mainboard/foxconn/d41s.md
+++ b/Documentation/mainboard/foxconn/d41s.md
@@ -72,4 +72,4 @@ To do this gently take the SPI flash out of its socket and flash with your progr
 
 [FOXCONN D41S]: http://www.foxconnchannel.com/ProductDetail.aspx?T=motherboard&U=en-us0000481
 [FOXCONN]: http://www.foxconnchannel.com
-[Flashrom]: https://flashrom.org/Flashrom
+[Flashrom]: https://flashrom.org/
diff --git a/Documentation/mainboard/gigabyte/ga-h61m-s2pv.md b/Documentation/mainboard/gigabyte/ga-h61m-s2pv.md
index 824026fe72..f8af48ae09 100644
--- a/Documentation/mainboard/gigabyte/ga-h61m-s2pv.md
+++ b/Documentation/mainboard/gigabyte/ga-h61m-s2pv.md
@@ -77,4 +77,4 @@ However, this makes DualBIOS unable to recover from a bad flash for some reason.
 
 [Gigabyte GA-H61M-S2PV]: https://www.gigabyte.com/us/Motherboard/GA-H61M-S2PV-rev-10
 [Gigabyte]: https://www.gigabyte.com
-[flashrom]: https://flashrom.org/Flashrom
+[flashrom]: https://flashrom.org/
diff --git a/Documentation/mainboard/hp/compaq_8200_sff.md b/Documentation/mainboard/hp/compaq_8200_sff.md
index f0783975dd..6fd4aab626 100644
--- a/Documentation/mainboard/hp/compaq_8200_sff.md
+++ b/Documentation/mainboard/hp/compaq_8200_sff.md
@@ -146,4 +146,4 @@ as otherwise there's not enough space near the flash.
 [IFD Hack]: https://review.coreboot.org/plugins/gitiles/coreboot/+/refs/changes/70/38770/4/Documentation/flash_tutorial/int_macbook.md/
 [Compaq 8200 Elite SFF]: https://support.hp.com/us-en/document/c03414707
 [HP]: https://www.hp.com/
-[flashrom]: https://flashrom.org/Flashrom
+[flashrom]: https://flashrom.org/
diff --git a/Documentation/mainboard/hp/compaq_8300_sff.md b/Documentation/mainboard/hp/compaq_8300_sff.md
index 3d1ae444e9..1a9d945eb2 100644
--- a/Documentation/mainboard/hp/compaq_8300_sff.md
+++ b/Documentation/mainboard/hp/compaq_8300_sff.md
@@ -70,4 +70,4 @@ as otherwise there's not enough space near the flash.
 
 [Compaq 8300 Elite SFF]: https://support.hp.com/us-en/document/c03345460
 [HP]: https://www.hp.com/
-[flashrom]: https://flashrom.org/Flashrom
+[flashrom]: https://flashrom.org/
diff --git a/Documentation/mainboard/hp/pro_3x00_series.md b/Documentation/mainboard/hp/pro_3x00_series.md
index a92c4f5c3f..a77ecc7a6a 100644
--- a/Documentation/mainboard/hp/pro_3x00_series.md
+++ b/Documentation/mainboard/hp/pro_3x00_series.md
@@ -106,4 +106,4 @@ until cleanly power cycled.
 [Pro 3400 Series]: https://support.hp.com/us-en/product/details/hp-pro-3400-microtower-pc/5160137
 [Pro 3500 Series]: https://support.hp.com/us-en/product/details/hp-pro-3500-microtower-pc/5270849
 [HP]: https://www.hp.com/
-[flashrom]: https://flashrom.org/Flashrom
+[flashrom]: https://flashrom.org/
diff --git a/Documentation/mainboard/hp/z220_sff.md b/Documentation/mainboard/hp/z220_sff.md
index 303b59aecf..cab98cfcc2 100644
--- a/Documentation/mainboard/hp/z220_sff.md
+++ b/Documentation/mainboard/hp/z220_sff.md
@@ -77,4 +77,4 @@ even interchangeable, so should do coreboot images built for them.
 [HP Z220 SFF Workstation]: https://support.hp.com/za-en/document/c03386950
 [HP Compaq Elite 8300 SFF]: https://support.hp.com/us-en/document/c03345460
 [HP]: https://www.hp.com/
-[flashrom]: https://flashrom.org/Flashrom
+[flashrom]: https://flashrom.org/
diff --git a/Documentation/mainboard/intel/dg43gt.md b/Documentation/mainboard/intel/dg43gt.md
index fe488a42d5..ee8a612016 100644
--- a/Documentation/mainboard/intel/dg43gt.md
+++ b/Documentation/mainboard/intel/dg43gt.md
@@ -96,4 +96,4 @@ The layout of the header is:
 ```
 
 [Intel DG43GT]: https://ark.intel.com/products/41036/Intel-Desktop-Board-DG43GT
-[flashrom]: https://flashrom.org/Flashrom
+[flashrom]: https://flashrom.org/
diff --git a/Documentation/mainboard/intel/kblrvp11.md b/Documentation/mainboard/intel/kblrvp11.md
index 32cc5dec28..9568732b27 100644
--- a/Documentation/mainboard/intel/kblrvp11.md
+++ b/Documentation/mainboard/intel/kblrvp11.md
@@ -76,4 +76,4 @@ $ flashrom -p internal --ifd -i bios -w coreboot.rom --noverify-all
 ```
 
 [W25Q128FV]: https://www.winbond.com/resource-files/w25q128fv%20rev.m%2005132016%20kms.pdf
-[flashrom]: https://flashrom.org/Flashrom
+[flashrom]: https://flashrom.org/
diff --git a/Documentation/mainboard/kontron/mal10.md b/Documentation/mainboard/kontron/mal10.md
index 62ef521a76..dc413f3aba 100644
--- a/Documentation/mainboard/kontron/mal10.md
+++ b/Documentation/mainboard/kontron/mal10.md
@@ -95,6 +95,6 @@ close to the CPU.
 
 [mAL10]: https://www.kontron.com/products/iot/iot-industry-4.0/iot-ready-boards-and-modules/com-express/com-express-mini/come-mal10-e2-.html
 [W25Q128FV]: https://www.winbond.com/resource-files/w25q128fv%20rev.m%2005132016%20kms.pdf
-[flashrom]: https://flashrom.org/Flashrom
+[flashrom]: https://flashrom.org/
 [NCT7802Y]: https://www.nuvoton.com/products/cloud-computing/hardware-monitors/desktop-server-series/nct7802y/?__locale=en
 [crashes]: https://pastebin.com/cpCfrPCL
diff --git a/Documentation/mainboard/lenovo/m920q.md b/Documentation/mainboard/lenovo/m920q.md
index 092aebf1b3..dac43d03bd 100644
--- a/Documentation/mainboard/lenovo/m920q.md
+++ b/Documentation/mainboard/lenovo/m920q.md
@@ -98,5 +98,5 @@ Tested with edk2 payload (mrchromebox) and Ubuntu 22.04 (Linux 6.2.0):
   - another riser with PCIe x4 connector remains untested - please modify this
     page if you do test it!
 
-[flashrom]: https://flashrom.org/Flashrom
+[flashrom]: https://flashrom.org/
 [Lenovo M920 Tiny specifications]: https://psref.lenovo.com/syspool/Sys/PDF/ThinkCentre/ThinkCentre_M920_Tiny/ThinkCentre_M920_Tiny_Spec.PDF
diff --git a/Documentation/mainboard/libretrend/lt1000.md b/Documentation/mainboard/libretrend/lt1000.md
index 4b13d469e0..fd48a045fd 100644
--- a/Documentation/mainboard/libretrend/lt1000.md
+++ b/Documentation/mainboard/libretrend/lt1000.md
@@ -112,6 +112,6 @@ not publicly available.
 
 [Libretrend LT1000]: https://libretrend.com/specs/librebox/
 [W25Q64FV]: https://www.winbond.com/resource-files/w25q64fv%20revs%2007182017.pdf
-[flashrom]: https://flashrom.org/Flashrom
+[flashrom]: https://flashrom.org/
 [baseboard site]: http://www.minicase.net/product_LR-i7S65T1.html
 [custom module]: https://shop.3mdeb.com/product/tpm2-module-for-librebox/
diff --git a/Documentation/mainboard/ocp/deltalake.md b/Documentation/mainboard/ocp/deltalake.md
index 05df4f2dc4..03882c1c5f 100644
--- a/Documentation/mainboard/ocp/deltalake.md
+++ b/Documentation/mainboard/ocp/deltalake.md
@@ -219,7 +219,7 @@ and [u-root] as initramfs.
 [The Wiwynn's Yosemite-V3 product in OCP market place]: https://www.opencompute.org/products/423/wiwynn-yosemite-v3-server
 [osf-builder]: https://github.com/facebookincubator/osf-builder
 [OCP virtual summit 2020]: https://www.opencompute.org/summit/virtual-summit/schedule
-[flashrom]: https://flashrom.org/Flashrom
+[flashrom]: https://flashrom.org/
 [All about u-root]: https://github.com/linuxboot/book/tree/master/u-root
 [u-root]: https://u-root.org/
 [ChromeOS VPD]: https://chromium.googlesource.com/chromiumos/platform/vpd/+/master/README.md
diff --git a/Documentation/mainboard/ocp/tiogapass.md b/Documentation/mainboard/ocp/tiogapass.md
index 1790f58e20..d84619d2f7 100644
--- a/Documentation/mainboard/ocp/tiogapass.md
+++ b/Documentation/mainboard/ocp/tiogapass.md
@@ -90,7 +90,7 @@ u-root.
 +------------------------+---------------------------------------------+
 ```
 
-[flashrom]: https://flashrom.org/Flashrom
+[flashrom]: https://flashrom.org/
 [OCP]: https://www.opencompute.org/
 [OCP Tioga Pass]: http://files.opencompute.org/oc/public.php?service=files&t=6fc3033e64fb029b0f84be5a8faf47e8
 [OCP Market Place]: https://www.opencompute.org/products/109/wiwynn-tioga-pass-advanced-2u-ocp-server-up-to-768gb-12-dimm-slots-4-ssds-for-io-performance
diff --git a/Documentation/mainboard/opencellular/elgon.md b/Documentation/mainboard/opencellular/elgon.md
index 9fd30e859d..ab85d5f85b 100644
--- a/Documentation/mainboard/opencellular/elgon.md
+++ b/Documentation/mainboard/opencellular/elgon.md
@@ -81,4 +81,4 @@ Dediprog compatible pinout.
 
 [Elgon]: https://github.com/Telecominfraproject/OpenCellular
 [OpenCellular]: https://code.fb.com/connectivity/introducing-opencellular-an-open-source-wireless-access-platform/
-[flashrom]: https://flashrom.org/Flashrom
+[flashrom]: https://flashrom.org/
diff --git a/Documentation/mainboard/pcengines/apu1.md b/Documentation/mainboard/pcengines/apu1.md
index fa59801ad0..020dc8dfdf 100644
--- a/Documentation/mainboard/pcengines/apu1.md
+++ b/Documentation/mainboard/pcengines/apu1.md
@@ -94,4 +94,4 @@ site. Depending on the configuration:
 
 [apu1c1_flash]: apu1c1.jpg
 [spi_header]: apu1_spi.jpg
-[flashrom]: https://flashrom.org/Flashrom
+[flashrom]: https://flashrom.org/
diff --git a/Documentation/mainboard/pcengines/apu2.md b/Documentation/mainboard/pcengines/apu2.md
index caa26cc3e5..fb1afec4ed 100644
--- a/Documentation/mainboard/pcengines/apu2.md
+++ b/Documentation/mainboard/pcengines/apu2.md
@@ -113,4 +113,4 @@ are available for free on PC Engines official site. Both configurations
 
 [apu2_flash]: apu2.jpg
 [spi_header]: apu2_spi.jpg
-[flashrom]: https://flashrom.org/Flashrom
+[flashrom]: https://flashrom.org/
diff --git a/Documentation/mainboard/portwell/pq7-m107.md b/Documentation/mainboard/portwell/pq7-m107.md
index 5d719eaac0..7ef5a5646c 100644
--- a/Documentation/mainboard/portwell/pq7-m107.md
+++ b/Documentation/mainboard/portwell/pq7-m107.md
@@ -75,5 +75,5 @@ serial/video/pcie ports might be available.
 
 [Portwell PQ7-M107]: http://portwell.com/products/detail.php?CUSTCHAR1=PQ7-M107
 [W25Q64FW]: https://www.winbond.com/resource-files/w25q64fw%20revn%2005182017%20sfdp.pdf
-[flashrom]: https://flashrom.org/Flashrom
+[flashrom]: https://flashrom.org/
 [Board manual]: www.portwell.com/pdf/embedded/PQ7-M107.pdf
diff --git a/Documentation/mainboard/prodrive/hermes.md b/Documentation/mainboard/prodrive/hermes.md
index db86130c6f..bb2e97df50 100644
--- a/Documentation/mainboard/prodrive/hermes.md
+++ b/Documentation/mainboard/prodrive/hermes.md
@@ -48,7 +48,7 @@ The board features:
 
 ## Extra links
 
-[flashrom]: https://flashrom.org/Flashrom
+[flashrom]: https://flashrom.org/
 [flashing tutorial]: ../../tutorial/flashing_firmware/ext_power.md
 [Intel FSP2.0]: ../../soc/intel/fsp/index.md
 [AST2500]: https://www.aspeedtech.com/products.php?fPath=20&rId=440
diff --git a/Documentation/mainboard/protectli/fw2b_fw4b.md b/Documentation/mainboard/protectli/fw2b_fw4b.md
index dec990906d..0fac4fe2fe 100644
--- a/Documentation/mainboard/protectli/fw2b_fw4b.md
+++ b/Documentation/mainboard/protectli/fw2b_fw4b.md
@@ -125,4 +125,4 @@ connected via [FE1.1 USB 2.0 hub].
 [Protectli FW4B]: https://protectli.com/product/fw4b/
 [MX25U6435F]: https://www.macronix.com/Lists/Datasheet/Attachments/7411/MX25U6435F,%201.8V,%2064Mb,%20v1.5.pdf
 [FE1.1 USB 2.0 hub]: https://cdn-shop.adafruit.com/product-files/2991/FE1.1s+Data+Sheet+(Rev.+1.0).pdf
-[flashrom]: https://flashrom.org/Flashrom
+[flashrom]: https://flashrom.org/
diff --git a/Documentation/mainboard/protectli/fw6.md b/Documentation/mainboard/protectli/fw6.md
index 309ca3a884..df61ee364b 100644
--- a/Documentation/mainboard/protectli/fw6.md
+++ b/Documentation/mainboard/protectli/fw6.md
@@ -154,5 +154,5 @@ should be able to compile and boot with no modifications required.
 [Protectli FW6]: https://protectli.com/vault-6-port/
 [website]: https://protectli.com/kb/coreboot-on-the-vault/
 [MX25L6406E]: https://www.macronix.com/Lists/Datasheet/Attachments/7370/MX25L6406E,%203V,%2064Mb,%20v1.9.pdf
-[flashrom]: https://flashrom.org/Flashrom
+[flashrom]: https://flashrom.org/
 [Yanling]: http://www.ylgkdn.cn/
diff --git a/Documentation/mainboard/protectli/vp2420.md b/Documentation/mainboard/protectli/vp2420.md
index b4ec5970c2..c7661d3e45 100644
--- a/Documentation/mainboard/protectli/vp2420.md
+++ b/Documentation/mainboard/protectli/vp2420.md
@@ -84,4 +84,4 @@ MX25L12835F - [datasheet][MX25L12835F].
 - [VP2420 Product Page](https://protectli.com/product/vp2420/)
 - [Protectli TPM module](https://protectli.com/product/tpm-module/)
 - [MX25L12835F](https://www.mxic.com.tw/Lists/Datasheet/Attachments/8653/MX25L12835F,%203V,%20128Mb,%20v1.6.pdf)
-- [flashrom](https://flashrom.org/Flashrom)
+- [flashrom](https://flashrom.org/)
diff --git a/Documentation/mainboard/protectli/vp46xx.md b/Documentation/mainboard/protectli/vp46xx.md
index f86f93159e..3540e13763 100644
--- a/Documentation/mainboard/protectli/vp46xx.md
+++ b/Documentation/mainboard/protectli/vp46xx.md
@@ -132,4 +132,4 @@ ITE IT8786E or IT8784E, but the configuration is the same on this platform.
 
 [Protectli VP46xx]: https://protectli.com/vault-6-port/
 [MX25L12835F]: https://www.mxic.com.tw/Lists/Datasheet/Attachments/8653/MX25L12835F,%203V,%20128Mb,%20v1.6.pdf
-[flashrom]: https://flashrom.org/Flashrom
+[flashrom]: https://flashrom.org/
diff --git a/Documentation/mainboard/purism/librem_14.md b/Documentation/mainboard/purism/librem_14.md
index 22bb183e0d..d7abbd0462 100644
--- a/Documentation/mainboard/purism/librem_14.md
+++ b/Documentation/mainboard/purism/librem_14.md
@@ -110,4 +110,4 @@ located underneath the Wi-Fi module, below the left cooling fan.
 [Purism Librem 14]: https://puri.sm/products/librem-14/
 [purism-blobs]: https://source.puri.sm/coreboot/purism-blobs
 [GD25Q127C]: https://www.gigadevice.com/datasheet/gd25q127c/
-[flashrom]: https://flashrom.org/Flashrom
+[flashrom]: https://flashrom.org/
diff --git a/Documentation/mainboard/purism/librem_mini.md b/Documentation/mainboard/purism/librem_mini.md
index 39cfca9710..27b67a98aa 100644
--- a/Documentation/mainboard/purism/librem_mini.md
+++ b/Documentation/mainboard/purism/librem_mini.md
@@ -126,4 +126,4 @@ desoldering it from the mainboard.
 [Purism Librem Mini]: https://puri.sm/products/librem-mini/
 [purism-blobs]: https://source.puri.sm/coreboot/purism-blobs
 [W25Q128JV]: https://www.winbond.com/resource-files/w25q128jv%20revf%2003272018%20plus.pdf
-[flashrom]: https://flashrom.org/Flashrom
+[flashrom]: https://flashrom.org/
diff --git a/Documentation/mainboard/sifive/hifive-unleashed.md b/Documentation/mainboard/sifive/hifive-unleashed.md
index 4dbbf0e073..3c818de2a3 100644
--- a/Documentation/mainboard/sifive/hifive-unleashed.md
+++ b/Documentation/mainboard/sifive/hifive-unleashed.md
@@ -96,5 +96,5 @@ console in certain situations.
 [Getting Started Guide]: https://sifive.cdn.prismic.io/sifive%2Ffa3a584a-a02f-4fda-b758-a2def05f49f9_hifive-unleashed-getting-started-guide-v1p1.pdf
 [RISC-V fork of OpenOCD]: https://github.com/riscv/riscv-openocd
 [OpenOCD script]: https://github.com/sifive/freedom-u-sdk/blob/057a47f657fa33e2c60df7f183884a68e90381cc/bsp/env/freedom-u500-unleashed/openocd.cfg
-[flashrom]: https://flashrom.org/Flashrom
+[flashrom]: https://flashrom.org/
 [schematics]: https://sifive.cdn.prismic.io/sifive%2Ff7173056-bf37-4407-87cb-d5ab76abf61a_hifive-unleashed-a00-schematics.pdf
diff --git a/Documentation/mainboard/supermicro/x10slm-f.md b/Documentation/mainboard/supermicro/x10slm-f.md
index 70e6e0ac14..27bf6b4340 100644
--- a/Documentation/mainboard/supermicro/x10slm-f.md
+++ b/Documentation/mainboard/supermicro/x10slm-f.md
@@ -196,7 +196,7 @@ Please also see :doc:`../../northbridge/intel/haswell/known-issues`.
 
 [AST2400]: https://www.aspeedtech.com/products.php?fPath=20&rId=376
 [Board manual]: https://www.supermicro.com/manuals/motherboard/C224/MNL-1500.pdf
-[flashrom]: https://flashrom.org/Flashrom
+[flashrom]: https://flashrom.org/
 [MX25L25635F]: https://media.digikey.com/pdf/Data%20Sheets/Macronix/MX25L25635F.pdf
 [N25Q128A]: https://www.micron.com/~/media/Documents/Products/Data%20Sheet/NOR%20Flash/Serial%20NOR/N25Q/n25q_128mb_3v_65nm.pdf
 [Supermicro X10SLM+-F]: https://www.supermicro.com/products/motherboard/xeon/c220/x10slm_-f.cfm
diff --git a/Documentation/mainboard/supermicro/x11-lga1151-series/x11-lga1151-series.md b/Documentation/mainboard/supermicro/x11-lga1151-series/x11-lga1151-series.md
index 91a0985cb4..06947f3484 100644
--- a/Documentation/mainboard/supermicro/x11-lga1151-series/x11-lga1151-series.md
+++ b/Documentation/mainboard/supermicro/x11-lga1151-series/x11-lga1151-series.md
@@ -60,7 +60,7 @@ These issues apply to all boards. Have a look at the board-specific issues, too.
 
 [Supermicro X11 LGA1151 series]: https://www.supermicro.com/products/motherboard/Xeon3000/#1151
 [OpenBMC]: https://www.openbmc.org/
-[flashrom]: https://flashrom.org/Flashrom
+[flashrom]: https://flashrom.org/
 [flashing tutorial]: ../../../tutorial/flashing_firmware/ext_power.md
 [Intel FSP2.0]: ../../../soc/intel/fsp/index.md
 [AST2400]: https://www.aspeedtech.com/products.php?fPath=20&rId=376
diff --git a/Documentation/mainboard/supermicro/x9sae.md b/Documentation/mainboard/supermicro/x9sae.md
index df5595012a..775927b3ec 100644
--- a/Documentation/mainboard/supermicro/x9sae.md
+++ b/Documentation/mainboard/supermicro/x9sae.md
@@ -104,5 +104,5 @@ seems that it shall not appear on X9SAE even if it is defined.
 [X9SAE]: https://www.supermicro.com/products/motherboard/xeon/c216/x9sae.cfm
 [X9SAE-V]:  https://www.supermicro.com/products/motherboard/xeon/c216/x9sae-v.cfm
 [W25Q128FVSG]: https://static.chipdip.ru/lib/093/DOC001093213.pdf
-[flashrom]: https://flashrom.org/Flashrom
+[flashrom]: https://flashrom.org/
 [flash internally]: ../../tutorial/flashing_firmware/int_flashrom.md
diff --git a/Documentation/mainboard/topton/adl/x2f-n100.md b/Documentation/mainboard/topton/adl/x2f-n100.md
index 941c8a7cb0..492ba111cf 100644
--- a/Documentation/mainboard/topton/adl/x2f-n100.md
+++ b/Documentation/mainboard/topton/adl/x2f-n100.md
@@ -102,4 +102,4 @@ using an internal programmer, other than the `programmer` argument:
 ```
 
 [flashprog]: https://flashprog.org/wiki/Flashprog
-[flashrom]: https://flashrom.org/Flashrom
+[flashrom]: https://flashrom.org/

From 8269a89d324453bfa867ae1b10ad15ef01325d7c Mon Sep 17 00:00:00 2001
From: Tongtong Pan <pantongtong@huaqin.corp-partner.google.com>
Date: Thu, 12 Jun 2025 20:23:11 +0800
Subject: [PATCH 1314/3886] mb/google/fatcat/var/felino: Add Synaptics touchpad
 to devicetree

Update device tree to support Synaptics touchpad.

BUG=b:414734334
TEST=emerge-fatcat coreboot and Synaptics touchpad can work well.

Change-Id: I5decb88cc37923e80a619899df66d47ec1579914
Signed-off-by: Tongtong Pan <pantongtong@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88074
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 .../google/fatcat/variants/felino/overridetree.cb      | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/src/mainboard/google/fatcat/variants/felino/overridetree.cb b/src/mainboard/google/fatcat/variants/felino/overridetree.cb
index 979583d67f..08224e0078 100644
--- a/src/mainboard/google/fatcat/variants/felino/overridetree.cb
+++ b/src/mainboard/google/fatcat/variants/felino/overridetree.cb
@@ -355,6 +355,16 @@ device ref tbt_pcie_rp0 on end
 				register "hid_desc_reg_offset" = "0x20"
 				device i2c 0x38 on end
 			end
+			chip drivers/i2c/hid
+				register "generic.hid" = ""SYNA0000""
+				register "generic.cid" = ""ACPI0C50""
+				register "generic.desc" = ""Synaptics Touchpad""
+				register "generic.irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_E18_IRQ)"
+				register "generic.wake" = "GPE0_DW2_18"
+				register "generic.detect" = "1"
+				register "hid_desc_reg_offset" = "0x20"
+				device i2c 0x2c on end
+			end
 		end # I2C4
 
 	end

From 4bf0f4fab33c7fd88174c08eb00fc32bae7d3743 Mon Sep 17 00:00:00 2001
From: Tongtong Pan <pantongtong@huaqin.corp-partner.google.com>
Date: Fri, 13 Jun 2025 09:26:52 +0800
Subject: [PATCH 1315/3886] mb/google/fatcat/var/felino: Add PIXART touchpad to
 devicetree

Update device tree to support PIXART touchpad.

BUG=b:414734334
TEST=emerge-fatcat coreboot and PIXART touchpad can work well.

Change-Id: I0eaab274e870f45f3cad16805580a968fc4b4aae
Signed-off-by: Tongtong Pan <pantongtong@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88089
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
---
 .../google/fatcat/variants/felino/overridetree.cb        | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/src/mainboard/google/fatcat/variants/felino/overridetree.cb b/src/mainboard/google/fatcat/variants/felino/overridetree.cb
index 08224e0078..ee19c1ed5b 100644
--- a/src/mainboard/google/fatcat/variants/felino/overridetree.cb
+++ b/src/mainboard/google/fatcat/variants/felino/overridetree.cb
@@ -365,6 +365,15 @@ device ref tbt_pcie_rp0 on end
 				register "hid_desc_reg_offset" = "0x20"
 				device i2c 0x2c on end
 			end
+			chip drivers/i2c/hid
+				register "generic.hid" = ""PNP0C50""
+				register "generic.desc" = ""PIXART Touchpad""
+				register "generic.irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_E18_IRQ)"
+				register "generic.wake" = "GPE0_DW2_18"
+				register "generic.detect" = "1"
+				register "hid_desc_reg_offset" = "0x20"
+				device i2c 0x68 on end
+			end
 		end # I2C4
 
 	end

From bc84e1ba4226ea8a7220883500d033024f6c3611 Mon Sep 17 00:00:00 2001
From: Subrata Banik <subratabanik@google.com>
Date: Fri, 6 Jun 2025 15:35:49 +0530
Subject: [PATCH 1316/3886] soc/intel/cmn/acpi: Refactor `SPCO` ASL method

This patch refactors `SPCO` ASL with helpers to remove macros.
1. Avoid inclusion of macros in ASL code.
2. Ensure runtime check can call appropriate clock routine either
for IOE die or PCH/SoC die.

This ensures runtime calls to correct clock routines for IOE,
PCH/SoC. Includes IOE PCR and IOE CLK ASL for compilation.
This inclusion increases the DSDT binary size by 250 bytes.

TEST=Able to build and boot google/fatcat.

w/ this patch:

```
fallback/dsdt.aml    0x94140    raw    25594 none
```

w/o this patch:

```
fallback/dsdt.aml    0x94140    raw    25350 none
```

Change-Id: Iee254e1766ca90662eb04548db26a408ce3c3d88
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87975
Reviewed-by: Pranava Y N <pranavayn@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/soc/intel/common/acpi/ioe_clk.asl         |  3 +
 src/soc/intel/common/acpi/pcie_clk.asl        | 68 +++++++++++++------
 src/soc/intel/meteorlake/acpi/southbridge.asl |  4 --
 3 files changed, 50 insertions(+), 25 deletions(-)

diff --git a/src/soc/intel/common/acpi/ioe_clk.asl b/src/soc/intel/common/acpi/ioe_clk.asl
index 9aa1aba4f5..572b293b1a 100644
--- a/src/soc/intel/common/acpi/ioe_clk.asl
+++ b/src/soc/intel/common/acpi/ioe_clk.asl
@@ -2,6 +2,9 @@
 
 #define PCR_BIOS_BUFFEN 0x8080
 
+/* IOE PCR access */
+#include <soc/intel/common/acpi/ioe_pcr.asl>
+
 Scope (\_SB)
 {
 	/* MTL IOE CLK */
diff --git a/src/soc/intel/common/acpi/pcie_clk.asl b/src/soc/intel/common/acpi/pcie_clk.asl
index b74d601a1a..f9d5132120 100644
--- a/src/soc/intel/common/acpi/pcie_clk.asl
+++ b/src/soc/intel/common/acpi/pcie_clk.asl
@@ -4,9 +4,33 @@
 #include <soc/intel/common/acpi/pch_clk.asl>
 
 /* IOE clock by P2SB */
-#if CONFIG(SOC_INTEL_COMMON_BLOCK_IOE_P2SB)
-	#include <soc/intel/common/acpi/ioe_clk.asl>
-#endif
+#include <soc/intel/common/acpi/ioe_clk.asl>
+
+/*
+ * CLKM (Clock Manager): Helper Method to manage clock enable/disable
+ * This method handles the enabling or disabling of clocks for either the
+ * Integrated Controller (ICLK) or the IOE Die (ECLK) based on the provided
+ * parameters.
+ *
+ * Arg0: Clock number
+ * Arg1: Clock source, IOE Die Clock (1)/Integrated Controller Clock (0)
+ * Arg2: Enable(1)/Disable(0) Clock
+ */
+Method (CLKM, 3, Serialized) {
+	If (LEqual (Arg1, 1)) {
+		If (LEqual (Arg2, 1)) {
+			\_SB.ECLK.CLKE (Arg0)
+		} Else {
+			\_SB.ECLK.CLKD (Arg0)
+		}
+	} Else {
+		If (LEqual (Arg2, 1)) {
+			\_SB.ICLK.CLKE (Arg0)
+		} Else {
+			\_SB.ICLK.CLKD (Arg0)
+		}
+	}
+}
 
 /*
  * Configure PCIe ClkReq Override
@@ -14,25 +38,27 @@
  * Arg1: Enable(1)/Disable(0) Clock
  */
 Method (SPCO, 2, Serialized) {
-#if CONFIG(SOC_INTEL_COMMON_BLOCK_IOE_P2SB)
-	If (LEqual (Arg1,1)) {
-		If (LGreaterEqual (Arg0, CONFIG_IOE_DIE_CLOCK_START)) {
-			\_SB.ECLK.CLKE (Subtract (Arg0, CONFIG_IOE_DIE_CLOCK_START))
-		} Else {
-			\_SB.ICLK.CLKE (Arg0)
-		}
-	} Else {
-		If (LGreaterEqual (Arg0, CONFIG_IOE_DIE_CLOCK_START)) {
-			\_SB.ECLK.CLKD (Subtract (Arg0, CONFIG_IOE_DIE_CLOCK_START))
-		} Else {
-			\_SB.ICLK.CLKD (Arg0)
-		}
+	/* Flag to indicate presence of IOE Die (1 = Present, 0 = Not Present) */
+	Local0 = CONFIG(SOC_INTEL_COMMON_BLOCK_IOE_P2SB)
+	/* Clock start index */
+	Local1 = 0
+
+	/* Override clock start index if SOC_INTEL_COMMON_BLOCK_IOE_P2SB Kconfig is present. */
+	If (LEqual (Local0, 1)) {
+		Local1 = CONFIG_IOE_DIE_CLOCK_START
 	}
-#else
-	If (LEqual (Arg1,1)) {
-		\_SB.ICLK.CLKE (Arg0)
+
+	/* Clock number */
+	Local2 = Arg0
+	If (LGreaterEqual (Arg0, Local1)) {
+		Local2 = Subtract (Arg0, Local1)
 	} Else {
-		\_SB.ICLK.CLKD (Arg0)
+		/*
+		 * Override IOE die indicator if clock number is less than the IOE die clock
+		 * start index. Refer as clock number from non-IOE die.
+		 */
+		Local0 = 0;
 	}
-#endif
+
+	CLKM (Local2, Local0, Arg1)
 }
diff --git a/src/soc/intel/meteorlake/acpi/southbridge.asl b/src/soc/intel/meteorlake/acpi/southbridge.asl
index b205aff568..06227920a7 100644
--- a/src/soc/intel/meteorlake/acpi/southbridge.asl
+++ b/src/soc/intel/meteorlake/acpi/southbridge.asl
@@ -6,10 +6,6 @@
 
 /* SoC PCR access */
 #include <soc/intel/common/acpi/pch_pcr.asl>
-/* IOE PCR access */
-#if CONFIG(SOC_INTEL_COMMON_BLOCK_IOE_P2SB)
-#include <soc/intel/common/acpi/ioe_pcr.asl>
-#endif
 
 /* PCIE src clock control */
 #include <soc/intel/common/acpi/pcie_clk.asl>

From 1bdf89d78c34e87a936d0c707a431d02a605ee09 Mon Sep 17 00:00:00 2001
From: NyeonWoo Kim <knw0507@naver.com>
Date: Sun, 1 Jun 2025 14:04:26 +0900
Subject: [PATCH 1317/3886] device/device_util.c: Complete function
 documentation

I've found some TODOs in comment in device_util.c,
so I replaced them with descriptions for readability.

Change-Id: I429ce0b2a1b56a60fdb4127591ec219768c2c044
Signed-off-by: NyeonWoo Kim <knw0507@naver.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87907
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/device/device_util.c | 17 ++++++++---------
 1 file changed, 8 insertions(+), 9 deletions(-)

diff --git a/src/device/device_util.c b/src/device/device_util.c
index fc585a0414..864e64c4bb 100644
--- a/src/device/device_util.c
+++ b/src/device/device_util.c
@@ -293,7 +293,7 @@ bool is_dev_on_domain0(const struct device *dev)
 /**
  * Allocate 64 more resources to the free list.
  *
- * @return TODO.
+ * @return Return 0 for allocation failure, Return 1 for allocation success.
  */
 static int allocate_more_resources(void)
 {
@@ -317,10 +317,9 @@ static int allocate_more_resources(void)
 /**
  * Remove resource res from the device's list and add it to the free list.
  *
- * @param dev TODO
- * @param res TODO
- * @param prev TODO
- * @return TODO.
+ * @param dev The device which contains a resource to be freed(detached).
+ * @param res The resource to be freed(detached) which is part of 'dev'.
+ * @param prev The resource for 'dev' to be linked to next resource after 'res' is removed.
  */
 static void free_resource(struct device *dev, struct resource *res,
 			  struct resource *prev)
@@ -383,7 +382,7 @@ struct resource *probe_resource(const struct device *dev, unsigned int index)
  *
  * @param dev The device to find the resource on.
  * @param index The index of the resource on the device.
- * @return TODO.
+ * @return The resource. if it exists, then return existing one, else return new one.
  */
 struct resource *new_resource(struct device *dev, unsigned int index)
 {
@@ -431,7 +430,7 @@ struct resource *new_resource(struct device *dev, unsigned int index)
  *
  * @param dev The device to find the resource on.
  * @param index The index of the resource on the device.
- * return TODO.
+ * @return The resource found in 'dev' for 'index'.
  */
 struct resource *find_resource(const struct device *dev, unsigned int index)
 {
@@ -520,7 +519,7 @@ resource_t resource_max(const struct resource *resource)
  * Return the resource type of a resource.
  *
  * @param resource The resource type to decode.
- * @return TODO.
+ * @return The string representation of type.
  */
 const char *resource_type(const struct resource *resource)
 {
@@ -542,7 +541,7 @@ const char *resource_type(const struct resource *resource)
  *
  * @param dev The device the stored resource lives on.
  * @param resource The resource that was just stored.
- * @param comment TODO
+ * @param comment The comment just for additional information.
  */
 void report_resource_stored(struct device *dev, const struct resource *resource,
 			    const char *comment)

From 3c88e629d9666be84fb100dfd05329d186834ca2 Mon Sep 17 00:00:00 2001
From: Zhongtian Wu <wuzhongtian@huaqin.corp-partner.google.com>
Date: Wed, 4 Jun 2025 16:48:49 +0800
Subject: [PATCH 1318/3886] mb/google/brox/var/lotso: Generate RAM IDs for
 lotso

Generate RAM ID for H58G56CK8BX146 and K3KL8L80EM-MGCU

BUG=b:424306040
BRANCH=None
TEST=boot to kernel success

Change-Id: I4f2808a1258de674ec0b75f11409fd1c8dc4cb06
Signed-off-by: Zhongtian Wu <wuzhongtian@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87965
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Jian Tong <tongjian@huaqin.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
---
 src/mainboard/google/brox/variants/lotso/memory/Makefile.mk     | 2 +-
 .../google/brox/variants/lotso/memory/dram_id.generated.txt     | 2 ++
 .../google/brox/variants/lotso/memory/mem_parts_used.txt        | 2 ++
 3 files changed, 5 insertions(+), 1 deletion(-)

diff --git a/src/mainboard/google/brox/variants/lotso/memory/Makefile.mk b/src/mainboard/google/brox/variants/lotso/memory/Makefile.mk
index 72cccf0c38..64f4e227ba 100644
--- a/src/mainboard/google/brox/variants/lotso/memory/Makefile.mk
+++ b/src/mainboard/google/brox/variants/lotso/memory/Makefile.mk
@@ -6,5 +6,5 @@
 SPD_SOURCES =
 SPD_SOURCES += spd/lp5/set-0/spd-9.hex      # ID = 0(0b0000)  Parts = K3KL6L60GM-MGCT
 SPD_SOURCES += spd/lp5/set-0/spd-1.hex      # ID = 1(0b0001)  Parts = H9JCNNNBK3MLYR-N6E
-SPD_SOURCES += spd/lp5/set-0/spd-11.hex      # ID = 2(0b0010)  Parts = K3KL8L80DM-MGCU, MT62F1G32D2DS-023 WT:C, H58G56BK8BX068
+SPD_SOURCES += spd/lp5/set-0/spd-11.hex      # ID = 2(0b0010)  Parts = K3KL8L80DM-MGCU, MT62F1G32D2DS-023 WT:C, H58G56BK8BX068, H58G56CK8BX146, K3KL8L80EM-MGCU
 SPD_SOURCES += spd/lp5/set-0/spd-7.hex      # ID = 3(0b0011)  Parts = H58G56BK7BX068
diff --git a/src/mainboard/google/brox/variants/lotso/memory/dram_id.generated.txt b/src/mainboard/google/brox/variants/lotso/memory/dram_id.generated.txt
index bb1b802be8..a4824fd008 100644
--- a/src/mainboard/google/brox/variants/lotso/memory/dram_id.generated.txt
+++ b/src/mainboard/google/brox/variants/lotso/memory/dram_id.generated.txt
@@ -10,3 +10,5 @@ K3KL8L80DM-MGCU                2 (0010)
 MT62F1G32D2DS-023 WT:C         2 (0010)
 H58G56BK8BX068                 2 (0010)
 H58G56BK7BX068                 3 (0011)
+H58G56CK8BX146                 2 (0010)
+K3KL8L80EM-MGCU                2 (0010)
diff --git a/src/mainboard/google/brox/variants/lotso/memory/mem_parts_used.txt b/src/mainboard/google/brox/variants/lotso/memory/mem_parts_used.txt
index 0175ae74d4..dac8c9957c 100644
--- a/src/mainboard/google/brox/variants/lotso/memory/mem_parts_used.txt
+++ b/src/mainboard/google/brox/variants/lotso/memory/mem_parts_used.txt
@@ -15,3 +15,5 @@ K3KL8L80DM-MGCU
 MT62F1G32D2DS-023 WT:C
 H58G56BK8BX068
 H58G56BK7BX068
+H58G56CK8BX146
+K3KL8L80EM-MGCU

From bb3a484e36ef594c2870ce355d560089af2fee06 Mon Sep 17 00:00:00 2001
From: Jeremy Compostella <jeremy.compostella@intel.com>
Date: Thu, 12 Jun 2025 10:15:11 -0700
Subject: [PATCH 1319/3886] soc/intel/*/acpi: Move the BASE ACPI method to
 northbridge

The BASE method, previously located within USB Type-C Subsystem (TCSS)
ASL (ACPI Source Language) scope across multiple Intel System on Chip
(SoC) files, has been moved to the northbridge module. This refactoring
allows the BASE method to be utilized beyond the USB Type-C Subsystem
use-case.

The BASE method calculates the PCIe device base address using function
and device numbers.

Note: the BASE method is now under the \SB.PCI0 scope. It used to be
under the \_SB scope while only consumed by devices under the \SB.PCI0
scope.

TEST=On a Fatcat board, we verified that the BASE method returns
     0xE00A3000 for the "./acpidbg -b 'evaluate \_SB.PCI0.BASE
     0x140003'" command. We performed a non-regression test as well on
     the TCSS DMA TDM0 device, which uses the BASE method, by verifying
     that "./acpidbg -b 'evaluate \_SB.PCI0.TDM0.DMAD'" and "./acpidbg
     -b 'evaluate \_SB.PCI0.TDM0.VDID'" return 0x22 and 0xE4338086,
     respectively.

Change-Id: I431206e9f38a2a5695c90d4ae6d823fb231814aa
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88084
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-by: Subrata Banik <subratabanik@google.com>
---
 src/soc/intel/alderlake/acpi/tcss.asl                | 10 ----------
 src/soc/intel/apollolake/acpi/northbridge.asl        | 10 ++++++++++
 src/soc/intel/common/block/acpi/acpi/northbridge.asl | 10 ++++++++++
 src/soc/intel/meteorlake/acpi/tcss.asl               | 10 ----------
 src/soc/intel/pantherlake/acpi/tcss.asl              | 10 ----------
 src/soc/intel/tigerlake/acpi/tcss.asl                | 10 ----------
 6 files changed, 20 insertions(+), 40 deletions(-)

diff --git a/src/soc/intel/alderlake/acpi/tcss.asl b/src/soc/intel/alderlake/acpi/tcss.asl
index b8b9fa4175..f184016f59 100644
--- a/src/soc/intel/alderlake/acpi/tcss.asl
+++ b/src/soc/intel/alderlake/acpi/tcss.asl
@@ -42,16 +42,6 @@
 
 Scope (\_SB)
 {
-	/* Device base address */
-	Method (BASE, 1)
-	{
-		Local0 = Arg0 & 0x7             /* Function number */
-		Local1 = (Arg0 >> 16) & 0x1F    /* Device number */
-		Local2 = (Local0 << 12) + (Local1 << 15)
-		Local3 = \_SB.PCI0.GPCB() + Local2
-		Return (Local3)
-	}
-
 	/*
 	 * Define PCH ACPIBASE IO as an ACPI operating region. The base address can be
 	 * found in Device 31, Function 2, Offset 40h.
diff --git a/src/soc/intel/apollolake/acpi/northbridge.asl b/src/soc/intel/apollolake/acpi/northbridge.asl
index fcbd1d0494..3e3f177b97 100644
--- a/src/soc/intel/apollolake/acpi/northbridge.asl
+++ b/src/soc/intel/apollolake/acpi/northbridge.asl
@@ -131,5 +131,15 @@ Method (GPCB, 0, Serialized)
 	Return (Local0)
 }
 
+/* Device base address */
+Method (BASE, 1)
+{
+	Local0 = Arg0 & 0x7             /* Function number */
+	Local1 = (Arg0 >> 16) & 0x1F    /* Device number */
+	Local2 = (Local0 << 12) + (Local1 << 15)
+	Local3 = \_SB.PCI0.GPCB() + Local2
+	Return (Local3)
+}
+
 /* GFX 00:02.0 */
 #include <drivers/intel/gma/acpi/gfx.asl>
diff --git a/src/soc/intel/common/block/acpi/acpi/northbridge.asl b/src/soc/intel/common/block/acpi/acpi/northbridge.asl
index dd176e600a..3b2fb85933 100644
--- a/src/soc/intel/common/block/acpi/acpi/northbridge.asl
+++ b/src/soc/intel/common/block/acpi/acpi/northbridge.asl
@@ -277,6 +277,16 @@ Method (GDMB, 0, Serialized)
 	Return (Local0)
 }
 
+/* Device base address */
+Method (BASE, 1)
+{
+	Local0 = Arg0 & 0x7             /* Function number */
+	Local1 = (Arg0 >> 16) & 0x1F    /* Device number */
+	Local2 = (Local0 << 12) + (Local1 << 15)
+	Local3 = \_SB.PCI0.GPCB() + Local2
+	Return (Local3)
+}
+
 /* PCI Device Resource Consumption */
 Device (PDRC)
 {
diff --git a/src/soc/intel/meteorlake/acpi/tcss.asl b/src/soc/intel/meteorlake/acpi/tcss.asl
index b765f0c738..27785ea5bb 100644
--- a/src/soc/intel/meteorlake/acpi/tcss.asl
+++ b/src/soc/intel/meteorlake/acpi/tcss.asl
@@ -42,16 +42,6 @@
 
 Scope (\_SB)
 {
-	/* Device base address */
-	Method (BASE, 1)
-	{
-		Local0 = Arg0 & 0x7             /* Function number */
-		Local1 = (Arg0 >> 16) & 0x1F    /* Device number */
-		Local2 = (Local0 << 12) + (Local1 << 15)
-		Local3 = \_SB.PCI0.GPCB() + Local2
-		Return (Local3)
-	}
-
 	/*
 	 * Define PCH ACPIBASE IO as an ACPI operating region. The base address can be
 	 * found in Device 31, Function 2, Offset 40h.
diff --git a/src/soc/intel/pantherlake/acpi/tcss.asl b/src/soc/intel/pantherlake/acpi/tcss.asl
index a89d26fb25..88c3ea7ba5 100644
--- a/src/soc/intel/pantherlake/acpi/tcss.asl
+++ b/src/soc/intel/pantherlake/acpi/tcss.asl
@@ -42,16 +42,6 @@
 
 Scope (\_SB)
 {
-	/* Device base address */
-	Method (BASE, 1)
-	{
-		Local0 = Arg0 & 0x7             /* Function number */
-		Local1 = (Arg0 >> 16) & 0x1F    /* Device number */
-		Local2 = (Local0 << 12) + (Local1 << 15)
-		Local3 = \_SB.PCI0.GPCB() + Local2
-		Return (Local3)
-	}
-
 	/*
 	 * Define PCH ACPIBASE IO as an ACPI operating region. The base address can be
 	 * found in Device 31, Function 2, Offset 40h.
diff --git a/src/soc/intel/tigerlake/acpi/tcss.asl b/src/soc/intel/tigerlake/acpi/tcss.asl
index d01cf250aa..56a0e55fbd 100644
--- a/src/soc/intel/tigerlake/acpi/tcss.asl
+++ b/src/soc/intel/tigerlake/acpi/tcss.asl
@@ -42,16 +42,6 @@
 
 Scope (\_SB)
 {
-	/* Device base address */
-	Method (BASE, 1)
-	{
-		Local0 = Arg0 & 0x7             /* Function number */
-		Local1 = (Arg0 >> 16) & 0x1F    /* Device number */
-		Local2 = (Local0 << 12) + (Local1 << 15)
-		Local3 = \_SB.PCI0.GPCB() + Local2
-		Return (Local3)
-	}
-
 	/*
 	 * Define PCH ACPIBASE IO as an ACPI operating region. The base address can be
 	 * found in Device 31, Function 2, Offset 40h.

From d17ace2c1b6d064e2c0ec563aa4db190caae036d Mon Sep 17 00:00:00 2001
From: Jeremy Compostella <jeremy.compostella@intel.com>
Date: Wed, 11 Jun 2025 17:14:10 -0700
Subject: [PATCH 1320/3886] soc/intel/cmn/blk/cnvi: Remove hardcoded offset in
 OperationRegion

The commit leverages the \_SB.PCI0.BASE() ACPI method to remove the
hardcoded offset in the definition of the ACPI OperationRegion for CNVI
devices. Instead of using a fixed memory address addition, the code now
dynamically calculates the RegionOffset using the device's base address
(_ADR). This change enhances flexibility and adaptability for different
configurations and devices.

TEST=acpidbg -b 'evaluate \_SB.PCI0.CNVW.VDID' returns 0xE4408086 on a
     Fatcat device.

Change-Id: Ia329aef0291c31862d002cb9bfa35930dab83fe5
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88085
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
---
 src/soc/intel/common/block/cnvi/cnvi.c | 10 +++++-----
 1 file changed, 5 insertions(+), 5 deletions(-)

diff --git a/src/soc/intel/common/block/cnvi/cnvi.c b/src/soc/intel/common/block/cnvi/cnvi.c
index 7aada20079..f155cde5fd 100644
--- a/src/soc/intel/common/block/cnvi/cnvi.c
+++ b/src/soc/intel/common/block/cnvi/cnvi.c
@@ -21,7 +21,7 @@ static void cnvw_fill_ssdt(const struct device *dev)
 
 	acpigen_write_scope(scope);
 /*
- *	OperationRegion(CWAR, SystemMemory, Add(\_SB.PCI0.GPCB(), 0xa3000), 0x100)
+ *	OperationRegion(CWAR, SystemMemory, \_SB_.PCI0.BASE(_ADR), 0x100)
  *	Field(CWAR, WordAcc, NoLock, Preserve) {
  *		VDID, 32,	// 0x00, VID DID
  *		Offset(CNVI_DEV_CAP),
@@ -36,10 +36,10 @@ static void cnvw_fill_ssdt(const struct device *dev)
  */
 
 	/* RegionOffset stored in Local0 */
-	/* Local0 = \_SB_.PCI0.GPCB() + 0xa3000 */
-	acpigen_emit_byte(ADD_OP);
-	acpigen_write_integer(0xa3000);
-	acpigen_emit_namestring("\\_SB_.PCI0.GPCB()");
+	/* Local0 = \_SB_.PCI0.BASE(_ADR) */
+	acpigen_write_store();
+	acpigen_emit_namestring("\\_SB_.PCI0.BASE");
+	acpigen_emit_namestring("_ADR");
 	acpigen_emit_byte(LOCAL0_OP);
 
 	/* OperationRegion */

From ea8a3e685f6c083bead7d387747ae756f4140005 Mon Sep 17 00:00:00 2001
From: Jeremy Compostella <jeremy.compostella@intel.com>
Date: Thu, 12 Jun 2025 10:19:15 -0700
Subject: [PATCH 1321/3886] soc/intel/cmn/blk/cnvi: Add descriptive comments
 for PRRS and RSTT

Enhance the readability and maintainability of the code by adding
detailed comments for the ACPI names "PRRS" and "RSTT" in the
`cnvw_fill_ssdt` function. These comments clarify the possible status
values for "PRRS" and the reset types for "RSTT", aiding developers in
understanding the function's logic and expected behavior.

Change-Id: I94486476cf2f95b8e1744ee369a9d9d6c734bba8
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88086
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
---
 src/soc/intel/common/block/cnvi/cnvi.c | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/src/soc/intel/common/block/cnvi/cnvi.c b/src/soc/intel/common/block/cnvi/cnvi.c
index f155cde5fd..2a1eadb912 100644
--- a/src/soc/intel/common/block/cnvi/cnvi.c
+++ b/src/soc/intel/common/block/cnvi/cnvi.c
@@ -93,11 +93,20 @@ static void cnvw_fill_ssdt(const struct device *dev)
 
 /*
  *	Name (PRRS, Zero)
+ *	Last _PRR Status
+ *	0: Non-Platform-Level Device Reset (PLDR) executed [Default]
+ *	1: Core PLDR Completed successfully
+ *	2: Product PLDR Completed successfully
+ *	3: Previous PLDR Not Completed
+ *	4: Product PLDR timeout
  */
 	acpigen_write_name_integer("PRRS", 0);
 
 /*
  *	Name (RSTT, Zero)
+ *	Reset Type
+ *	0: Core Reset
+ *	1: Product Reset
  */
 	acpigen_write_name_integer("RSTT", 0);
 

From 29dd511628a6137b4c050a054cea4c10661099bd Mon Sep 17 00:00:00 2001
From: Jeremy Compostella <jeremy.compostella@intel.com>
Date: Thu, 12 Jun 2025 12:01:58 -0700
Subject: [PATCH 1322/3886] soc/intel: Move CNVI sideband definitions to
 SoC-specific files

The Connectivity Integrated (CNVi) sideband port ID or Platform-Level
Device Reset (PLDR) register are specific to each SoC platform,
necessitating its relocation to respective SoC codebases. This change
enhances maintainability and readability by ensuring the port IDs are
defined within the context of the SoC they pertain to, removing
redundancy and potential misconfigurations across different SoCs.

Change-Id: I6ef1e077b8ffc076b7dc33ea90cc6ea92e819438
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88087
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/soc/intel/alderlake/include/soc/cnvi.h         | 12 ++++++++++++
 src/soc/intel/alderlake/include/soc/pcr_ids.h      |  1 +
 src/soc/intel/apollolake/include/soc/cnvi.h        |  8 ++++++++
 src/soc/intel/apollolake/include/soc/pcr_ids.h     |  1 +
 src/soc/intel/cannonlake/include/soc/cnvi.h        |  8 ++++++++
 src/soc/intel/cannonlake/include/soc/pcr_ids.h     |  1 +
 src/soc/intel/common/block/cnvi/cnvi.c             |  8 +++++---
 .../intel/common/block/include/intelblocks/cnvi.h  | 14 --------------
 src/soc/intel/jasperlake/include/soc/cnvi.h        |  8 ++++++++
 src/soc/intel/jasperlake/include/soc/pcr_ids.h     |  1 +
 src/soc/intel/meteorlake/include/soc/cnvi.h        | 12 ++++++++++++
 src/soc/intel/meteorlake/include/soc/pcr_ids.h     |  1 +
 src/soc/intel/pantherlake/include/soc/cnvi.h       |  8 ++++++++
 src/soc/intel/pantherlake/include/soc/pcr_ids.h    |  1 +
 src/soc/intel/tigerlake/include/soc/cnvi.h         |  8 ++++++++
 src/soc/intel/tigerlake/include/soc/pcr_ids.h      |  1 +
 16 files changed, 76 insertions(+), 17 deletions(-)
 create mode 100644 src/soc/intel/alderlake/include/soc/cnvi.h
 create mode 100644 src/soc/intel/apollolake/include/soc/cnvi.h
 create mode 100644 src/soc/intel/cannonlake/include/soc/cnvi.h
 create mode 100644 src/soc/intel/jasperlake/include/soc/cnvi.h
 create mode 100644 src/soc/intel/meteorlake/include/soc/cnvi.h
 create mode 100644 src/soc/intel/pantherlake/include/soc/cnvi.h
 create mode 100644 src/soc/intel/tigerlake/include/soc/cnvi.h

diff --git a/src/soc/intel/alderlake/include/soc/cnvi.h b/src/soc/intel/alderlake/include/soc/cnvi.h
new file mode 100644
index 0000000000..7a9c30d960
--- /dev/null
+++ b/src/soc/intel/alderlake/include/soc/cnvi.h
@@ -0,0 +1,12 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef _SOC_ALDERLAKE_CNVI_H_
+#define _SOC_ALDERLAKE_CNVI_H_
+
+#if CONFIG(SOC_INTEL_ALDERLAKE_PCH_S)
+#define CNVI_ABORT_PLDR		0x44
+#else
+#define CNVI_ABORT_PLDR		0x80
+#endif
+
+#endif /* _SOC_ALDERLAKE_CNVI_H_ */
diff --git a/src/soc/intel/alderlake/include/soc/pcr_ids.h b/src/soc/intel/alderlake/include/soc/pcr_ids.h
index 7f0ec00f5d..3bef44fa4a 100644
--- a/src/soc/intel/alderlake/include/soc/pcr_ids.h
+++ b/src/soc/intel/alderlake/include/soc/pcr_ids.h
@@ -20,6 +20,7 @@
 #define PID_GPIOCOM5	0x69
 
 #define PID_ESPI	0x72
+#define PID_CNVI	0x73
 #define PID_DMI		0x88
 #define PID_PSTH	0x89
 #define PID_CSME0	0x90
diff --git a/src/soc/intel/apollolake/include/soc/cnvi.h b/src/soc/intel/apollolake/include/soc/cnvi.h
new file mode 100644
index 0000000000..309c3ab0a9
--- /dev/null
+++ b/src/soc/intel/apollolake/include/soc/cnvi.h
@@ -0,0 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef _SOC_APOLLOLAKE_CNVI_H_
+#define _SOC_APOLLOLAKE_CNVI_H_
+
+#define CNVI_ABORT_PLDR		0x80
+
+#endif /* _SOC_APOLLOLAKE_CNVI_H_ */
diff --git a/src/soc/intel/apollolake/include/soc/pcr_ids.h b/src/soc/intel/apollolake/include/soc/pcr_ids.h
index b81d700da4..7176eed973 100644
--- a/src/soc/intel/apollolake/include/soc/pcr_ids.h
+++ b/src/soc/intel/apollolake/include/soc/pcr_ids.h
@@ -6,6 +6,7 @@
 /*
  * Port ids.
  */
+#define PID_CNVI	0x73
 #if CONFIG(SOC_INTEL_GEMINILAKE)
 #define PID_GPIO_AUDIO	0xC9
 #define PID_GPIO_SCC	0xC8
diff --git a/src/soc/intel/cannonlake/include/soc/cnvi.h b/src/soc/intel/cannonlake/include/soc/cnvi.h
new file mode 100644
index 0000000000..c847f64201
--- /dev/null
+++ b/src/soc/intel/cannonlake/include/soc/cnvi.h
@@ -0,0 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef _SOC_CANNONLAKE_CNVI_H_
+#define _SOC_CANNONLAKE_CNVI_H_
+
+#define CNVI_ABORT_PLDR		0x80
+
+#endif /* _SOC_CANNONLAKE_CNVI_H_ */
diff --git a/src/soc/intel/cannonlake/include/soc/pcr_ids.h b/src/soc/intel/cannonlake/include/soc/pcr_ids.h
index f57a2efb82..3ddcaf5a9b 100644
--- a/src/soc/intel/cannonlake/include/soc/pcr_ids.h
+++ b/src/soc/intel/cannonlake/include/soc/pcr_ids.h
@@ -12,6 +12,7 @@
 #define PID_GPIOCOM2	0x6c
 #define PID_GPIOCOM1	0x6d
 #define PID_GPIOCOM0	0x6e
+#define PID_CNVI	0x73
 #define PID_DMI		0x88
 #define PID_PSTH	0x89
 #define PID_CSME0	0x90
diff --git a/src/soc/intel/common/block/cnvi/cnvi.c b/src/soc/intel/common/block/cnvi/cnvi.c
index 2a1eadb912..743b248476 100644
--- a/src/soc/intel/common/block/cnvi/cnvi.c
+++ b/src/soc/intel/common/block/cnvi/cnvi.c
@@ -7,6 +7,8 @@
 #include <device/pci.h>
 #include <device/pci_ids.h>
 #include <intelblocks/cnvi.h>
+#include <soc/cnvi.h>
+#include <soc/pcr_ids.h>
 
 static const char *cnvi_wifi_acpi_name(const struct device *dev)
 {
@@ -256,7 +258,7 @@ static void cnvw_fill_ssdt(const struct device *dev)
 				{
 					acpigen_write_store();
 					acpigen_emit_namestring("\\_SB.PCI0.PCRR");
-					acpigen_write_integer(CNVI_SIDEBAND_ID);
+					acpigen_write_integer(PID_CNVI);
 					acpigen_write_integer(CNVI_ABORT_PLDR);
 					acpigen_emit_byte(LOCAL0_OP);
 
@@ -284,7 +286,7 @@ static void cnvw_fill_ssdt(const struct device *dev)
 						acpigen_pop_len();
 
 						acpigen_emit_namestring("\\_SB.PCI0.PCRO");
-						acpigen_write_integer(CNVI_SIDEBAND_ID);
+						acpigen_write_integer(PID_CNVI);
 						acpigen_write_integer(CNVI_ABORT_PLDR);
 						acpigen_write_integer(CNVI_ABORT_REQUEST | CNVI_ABORT_ENABLE);
 
@@ -292,7 +294,7 @@ static void cnvw_fill_ssdt(const struct device *dev)
 
 						acpigen_write_store();
 						acpigen_emit_namestring("\\_SB.PCI0.PCRR");
-						acpigen_write_integer(CNVI_SIDEBAND_ID);
+						acpigen_write_integer(PID_CNVI);
 						acpigen_write_integer(CNVI_ABORT_PLDR);
 						acpigen_emit_byte(LOCAL0_OP);
 
diff --git a/src/soc/intel/common/block/include/intelblocks/cnvi.h b/src/soc/intel/common/block/include/intelblocks/cnvi.h
index 52f9238206..c6fe131d97 100644
--- a/src/soc/intel/common/block/include/intelblocks/cnvi.h
+++ b/src/soc/intel/common/block/include/intelblocks/cnvi.h
@@ -13,22 +13,8 @@
 #define CNVI_PLDR_NOT_COMPLETE	0x03
 #define CNVI_PLDR_TIMEOUT	0x04
 
-/* CNVi PLDR Control */
-#if CONFIG(SOC_INTEL_ALDERLAKE_PCH_S)
-#define CNVI_ABORT_PLDR		0x44
-#else
-#define CNVI_ABORT_PLDR		0x80
-#endif
-
 #define CNVI_ABORT_ENABLE	BIT(0)
 #define CNVI_ABORT_REQUEST	BIT(1)
 #define CNVI_READY		BIT(2)
 
-/* CNVi Sideband Port ID */
-#if CONFIG(SOC_INTEL_METEORLAKE)
-#define CNVI_SIDEBAND_ID	0x29
-#else
-#define CNVI_SIDEBAND_ID	0x73
-#endif
-
 #endif	// _SOC_INTEL_COMMON_CNVI_H_
diff --git a/src/soc/intel/jasperlake/include/soc/cnvi.h b/src/soc/intel/jasperlake/include/soc/cnvi.h
new file mode 100644
index 0000000000..7c79b3cd5b
--- /dev/null
+++ b/src/soc/intel/jasperlake/include/soc/cnvi.h
@@ -0,0 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef _SOC_JASPERLAKE_CNVI_H_
+#define _SOC_JASPERLAKE_CNVI_H_
+
+#define CNVI_ABORT_PLDR		0x80
+
+#endif /* _SOC_JASPERLAKE_CNVI_H_ */
diff --git a/src/soc/intel/jasperlake/include/soc/pcr_ids.h b/src/soc/intel/jasperlake/include/soc/pcr_ids.h
index c74d1f9fc3..152cedaf60 100644
--- a/src/soc/intel/jasperlake/include/soc/pcr_ids.h
+++ b/src/soc/intel/jasperlake/include/soc/pcr_ids.h
@@ -14,6 +14,7 @@
 #define PID_GPIOCOM4	0x6a
 #define PID_GPIOCOM5	0x69
 
+#define PID_CNVI	0x73
 #define PID_DMI		0x88
 #define PID_PSTH	0x89
 #define PID_CSME0	0x90
diff --git a/src/soc/intel/meteorlake/include/soc/cnvi.h b/src/soc/intel/meteorlake/include/soc/cnvi.h
new file mode 100644
index 0000000000..90079d4c72
--- /dev/null
+++ b/src/soc/intel/meteorlake/include/soc/cnvi.h
@@ -0,0 +1,12 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef _SOC_METEORLAKE_CNVI_H_
+#define _SOC_METEORLAKE_CNVI_H_
+
+#if CONFIG(SOC_INTEL_METEORLAKE_S)
+#define CNVI_ABORT_PLDR		0x44
+#else
+#define CNVI_ABORT_PLDR		0x80
+#endif
+
+#endif /* _SOC_METEORLAKE_CNVI_H_ */
diff --git a/src/soc/intel/meteorlake/include/soc/pcr_ids.h b/src/soc/intel/meteorlake/include/soc/pcr_ids.h
index 1b0eda3a5d..d7e894a7ac 100644
--- a/src/soc/intel/meteorlake/include/soc/pcr_ids.h
+++ b/src/soc/intel/meteorlake/include/soc/pcr_ids.h
@@ -16,6 +16,7 @@
 #define PID_PSF8	0x08
 #define PID_PSF7	0x07
 #define PID_PSF6	0x06
+#define PID_CNVI	0x29
 #define PID_PSF5	0x8F
 #define PID_PSF4	0xBD
 #define PID_PSF3	0xBC
diff --git a/src/soc/intel/pantherlake/include/soc/cnvi.h b/src/soc/intel/pantherlake/include/soc/cnvi.h
new file mode 100644
index 0000000000..b921f3559c
--- /dev/null
+++ b/src/soc/intel/pantherlake/include/soc/cnvi.h
@@ -0,0 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef _SOC_PANTHERLAKE_CNVI_H_
+#define _SOC_PANTHERLAKE_CNVI_H_
+
+#define CNVI_ABORT_PLDR		0x80
+
+#endif /* _SOC_PANTHERLAKE_CNVI_H_ */
diff --git a/src/soc/intel/pantherlake/include/soc/pcr_ids.h b/src/soc/intel/pantherlake/include/soc/pcr_ids.h
index 8e655540bc..4fc5a397a0 100644
--- a/src/soc/intel/pantherlake/include/soc/pcr_ids.h
+++ b/src/soc/intel/pantherlake/include/soc/pcr_ids.h
@@ -8,6 +8,7 @@
 #define PID_XHCI	0x09
 #define PID_DMI		0x2F
 #define PID_CSME0	0x40
+#define PID_CNVI	0x51
 #define PID_GPIOCOM0	0x59
 #define PID_GPIOCOM1	0x5A
 #define PID_GPIOCOM3	0x5B
diff --git a/src/soc/intel/tigerlake/include/soc/cnvi.h b/src/soc/intel/tigerlake/include/soc/cnvi.h
new file mode 100644
index 0000000000..ae57de3cdf
--- /dev/null
+++ b/src/soc/intel/tigerlake/include/soc/cnvi.h
@@ -0,0 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef _SOC_TIGERLAKE_CNVI_H_
+#define _SOC_TIGERLAKE_CNVI_H_
+
+#define CNVI_ABORT_PLDR		0x80
+
+#endif /* _SOC_TIGERLAKE_CNVI_H_ */
diff --git a/src/soc/intel/tigerlake/include/soc/pcr_ids.h b/src/soc/intel/tigerlake/include/soc/pcr_ids.h
index 22f08d73d1..168a6985e8 100644
--- a/src/soc/intel/tigerlake/include/soc/pcr_ids.h
+++ b/src/soc/intel/tigerlake/include/soc/pcr_ids.h
@@ -18,6 +18,7 @@
 #define PID_GPIOCOM4	0x6a
 #define PID_GPIOCOM5	0x69
 
+#define PID_CNVI	0x73
 #define PID_DMI		0x88
 #define PID_PSTH	0x89
 #define PID_CSME0	0x90

From ea6f150d9d11fef8f56ca8565de48c9944592e2b Mon Sep 17 00:00:00 2001
From: Jeremy Compostella <jeremy.compostella@intel.com>
Date: Thu, 12 Jun 2025 10:21:10 -0700
Subject: [PATCH 1323/3886] soc/intel/cmd/blk/cnvi: Correct conditional logic
 for CNVI readiness

This commit fixes a bug in the conditional logic for determining
Connectivity Integrated (CNVi) readiness in the `cnvw_fill_ssdt()`
function. The comparison previously checked if `LOCAL3_OP` was equal to
`1`, but it should instead verify if `LOCAL3_OP` equals
`CNVI_READY`. This adjustment ensures the accurate assessment of CNVI's
readiness state.

TEST=Running the following "acpidbg -b 'set N \_SB.PCI0.CNVW.RSTT 1'",
     "acpidbg -b 'evaluate \_SB.PCI0.CNVW.CNVP._RST'" and "acpidbg -b
     'evaluate \_SB.PCI0.CNVW.PRRS'" commands result in PRRS being read
     as 2 (expected) instead of 1.

Change-Id: Ia6db833f3118e6975298aff4bd7c40657e4fcff7
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88088
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/soc/intel/common/block/cnvi/cnvi.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/soc/intel/common/block/cnvi/cnvi.c b/src/soc/intel/common/block/cnvi/cnvi.c
index 743b248476..5c5be9e1dd 100644
--- a/src/soc/intel/common/block/cnvi/cnvi.c
+++ b/src/soc/intel/common/block/cnvi/cnvi.c
@@ -310,7 +310,7 @@ static void cnvw_fill_ssdt(const struct device *dev)
 
 						acpigen_write_if_lequal_op_int(LOCAL1_OP, 0);
 						{
-							acpigen_write_if_lequal_op_int(LOCAL3_OP, 1);
+							acpigen_write_if_lequal_op_int(LOCAL3_OP, CNVI_READY);
 							{
 								acpigen_write_store_int_to_namestr(CNVI_PLDR_COMPLETE, "PRRS");
 

From 686dea9883f700575b4c02e60c6a823c94e93eda Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Thu, 12 Jun 2025 13:03:03 -0500
Subject: [PATCH 1324/3886] mb/google/glados: Correct channel count for DMIC

These boards only have 2 DMIC physically connected, and attempting to
record from 4 channels vs 2 results in a large amount of background
noise which drowns out the recording. Selecting the 2 channel DMIC
shows audio on both channels and no noise.

TEST=build/boot glados variants, test built-in mic under Windows
and Linux.

Change-Id: I68b7d1425c18d070dd75bc42d40ee30701f9704a
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88079
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
---
 src/mainboard/google/glados/Kconfig | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/mainboard/google/glados/Kconfig b/src/mainboard/google/glados/Kconfig
index 287d938341..779dc48bac 100644
--- a/src/mainboard/google/glados/Kconfig
+++ b/src/mainboard/google/glados/Kconfig
@@ -53,7 +53,7 @@ config BOARD_GOOGLE_CHELL
 
 config BOARD_GOOGLE_GLADOS
 	select BOARD_GOOGLE_BASEBOARD_GLADOS
-	select NHLT_DMIC_4CH if INCLUDE_NHLT_BLOBS
+	select NHLT_DMIC_2CH if INCLUDE_NHLT_BLOBS
 	select NHLT_SSM4567 if INCLUDE_NHLT_BLOBS
 
 config BOARD_GOOGLE_LARS
@@ -69,7 +69,7 @@ config BOARD_GOOGLE_SENTRY
 	select DRIVERS_GENERIC_MAX98357A
 	select INTEL_GMA_HAVE_VBT
 	select MAINBOARD_NO_FSP_GOP
-	select NHLT_DMIC_4CH if INCLUDE_NHLT_BLOBS
+	select NHLT_DMIC_2CH if INCLUDE_NHLT_BLOBS
 	select NHLT_MAX98357 if INCLUDE_NHLT_BLOBS
 	select NHLT_SSM4567 if INCLUDE_NHLT_BLOBS
 

From fed7ad967a0bb12d5ae85759a63f40297bbd03fd Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Thu, 12 Jun 2025 13:11:06 -0500
Subject: [PATCH 1325/3886] mb/google/reef: Correct channel count for DMIC

These boards only have 2 DMIC physically connected, and attempting to
record from 4 channels vs 2 results in a large amount of background
noise which drowns out the recording. Selecting the 2 channel DMIC
shows audio on both channels and no noise.

TEST=build/boot reef variants, test built-in mic under Windows
and Linux.

Change-Id: Ie7c422f4bd205b0388ee8efea7cf4f3cfa83ef05
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88080
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/google/reef/Kconfig | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/mainboard/google/reef/Kconfig b/src/mainboard/google/reef/Kconfig
index 76a8119b5a..d27feb2b49 100644
--- a/src/mainboard/google/reef/Kconfig
+++ b/src/mainboard/google/reef/Kconfig
@@ -99,7 +99,7 @@ config UART_FOR_CONSOLE
 
 config INCLUDE_NHLT_BLOBS
 	bool "Include blobs for audio."
-	select NHLT_DMIC_4CH_16B
+	select NHLT_DMIC_2CH_16B
 	select NHLT_DA7219
 	select NHLT_MAX98357
 

From 41e09a5c5961cbc7a1b73f495c5c12560fa8a857 Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Thu, 12 Jun 2025 13:12:50 -0500
Subject: [PATCH 1326/3886] mb/google/fizz/var/karma: Correct channel count for
 DMIC

This board only has 2 DMIC physically connected, and attempting to
record from 4 channels vs 2 results in a large amount of background
noise which drowns out the recording. Selecting the 2 channel DMIC
shows audio on both channels and no noise.

TEST=build/boot fizz/karma, test built-in mic under Windows and Linux.

Change-Id: I48162ff25d8c7f413e651c07a7f8e9604bee224c
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88081
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
---
 src/mainboard/google/fizz/Kconfig               | 2 +-
 src/mainboard/google/fizz/variants/karma/nhlt.c | 6 +++---
 2 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/src/mainboard/google/fizz/Kconfig b/src/mainboard/google/fizz/Kconfig
index 635170cc4c..d07ce2ff10 100644
--- a/src/mainboard/google/fizz/Kconfig
+++ b/src/mainboard/google/fizz/Kconfig
@@ -95,7 +95,7 @@ config INCLUDE_NHLT_BLOBS
 config INCLUDE_NHLT_BLOBS_KARMA
 	bool "Include blobs for karma audio."
 	select NHLT_DA7219
-	select NHLT_DMIC_4CH
+	select NHLT_DMIC_2CH
 	select NHLT_MAX98357
 
 config UART_FOR_CONSOLE
diff --git a/src/mainboard/google/fizz/variants/karma/nhlt.c b/src/mainboard/google/fizz/variants/karma/nhlt.c
index b0f4527ad6..f0ac84168a 100644
--- a/src/mainboard/google/fizz/variants/karma/nhlt.c
+++ b/src/mainboard/google/fizz/variants/karma/nhlt.c
@@ -7,9 +7,9 @@
 
 void variant_nhlt_init(struct nhlt *nhlt)
 {
-	/* 4 Channel DMIC array. */
-	if (nhlt_soc_add_dmic_array(nhlt, 4))
-		printk(BIOS_ERR, "Couldn't add 4CH DMIC array.\n");
+	/* 2 Channel DMIC array. */
+	if (nhlt_soc_add_dmic_array(nhlt, 2))
+		printk(BIOS_ERR, "Couldn't add 2CH DMIC array.\n");
 
 	/* Dialog DA7219 Headset codec. */
 	if (nhlt_soc_add_da7219(nhlt, AUDIO_LINK_SSP1))

From 9accaa72386f1682113e4a27aa5e4f6472f0f212 Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Thu, 12 Jun 2025 13:14:20 -0500
Subject: [PATCH 1327/3886] mb/google/poppy: Correct channel count for DMIC

These boards only have 2 DMIC physically connected, and attempting to
record from 4 channels vs 2 results in a large amount of background
noise which drowns out the recording. Selecting the 2 channel DMIC
shows audio on both channels and no noise.

TEST=build/boot poppy variants, test built-in mic under Windows
and Linux.

Change-Id: I30d97fa1a25e8cefe05cedac5176bb74dad7f318
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88082
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
---
 src/mainboard/google/poppy/Kconfig                   | 11 +++++------
 src/mainboard/google/poppy/variants/atlas/nhlt.c     |  6 +++---
 src/mainboard/google/poppy/variants/baseboard/nhlt.c |  4 ----
 src/mainboard/google/poppy/variants/nami/nhlt.c      |  6 +++---
 src/mainboard/google/poppy/variants/nautilus/nhlt.c  |  6 +++---
 src/mainboard/google/poppy/variants/nocturne/nhlt.c  |  6 +++---
 src/mainboard/google/poppy/variants/rammus/nhlt.c    |  6 +++---
 7 files changed, 20 insertions(+), 25 deletions(-)

diff --git a/src/mainboard/google/poppy/Kconfig b/src/mainboard/google/poppy/Kconfig
index 3bc24a58d5..fea28b4f25 100644
--- a/src/mainboard/google/poppy/Kconfig
+++ b/src/mainboard/google/poppy/Kconfig
@@ -138,37 +138,36 @@ config DRIVER_TPM_SPI_BUS
 config INCLUDE_NHLT_BLOBS
 	bool "Include blobs for audio."
 	select NHLT_DMIC_2CH
-	select NHLT_DMIC_4CH
 	select NHLT_MAX98927
 	select NHLT_RT5663
 
 config INCLUDE_NHLT_BLOBS_ATLAS
 	bool "Include blobs for atlas audio."
 	select NHLT_DA7219
-	select NHLT_DMIC_4CH
+	select NHLT_DMIC_2CH
 	select NHLT_MAX98373
 
 config INCLUDE_NHLT_BLOBS_NAUTILUS
 	bool "Include blobs for nautilus audio."
 	select NHLT_DA7219
-	select NHLT_DMIC_4CH
+	select NHLT_DMIC_2CH
 	select NHLT_MAX98357
 
 config INCLUDE_NHLT_BLOBS_NAMI
 	bool "Include blobs for nami audio."
 	select NHLT_DA7219
-	select NHLT_DMIC_4CH
+	select NHLT_DMIC_2CH
 	select NHLT_MAX98357
 
 config INCLUDE_NHLT_BLOBS_NOCTURNE
 	bool "Include blobs for nocturne audio."
-	select NHLT_DMIC_4CH
+	select NHLT_DMIC_2CH
 	select NHLT_MAX98373
 
 config INCLUDE_NHLT_BLOBS_RAMMUS
 	bool "Include blobs for rammus audio."
 	select NHLT_DA7219
-	select NHLT_DMIC_4CH
+	select NHLT_DMIC_2CH
 	select NHLT_MAX98927
 
 config MAINBOARD_DIR
diff --git a/src/mainboard/google/poppy/variants/atlas/nhlt.c b/src/mainboard/google/poppy/variants/atlas/nhlt.c
index ee642c0fc6..b9b7c20ffb 100644
--- a/src/mainboard/google/poppy/variants/atlas/nhlt.c
+++ b/src/mainboard/google/poppy/variants/atlas/nhlt.c
@@ -7,9 +7,9 @@
 
 void variant_nhlt_init(struct nhlt *nhlt)
 {
-	/* 4 Channel DMIC array. */
-	if (nhlt_soc_add_dmic_array(nhlt, 4))
-		printk(BIOS_ERR, "Couldn't add 4CH DMIC arrays.\n");
+	/* 2 Channel DMIC array. */
+	if (nhlt_soc_add_dmic_array(nhlt, 2))
+		printk(BIOS_ERR, "Couldn't add 2CH DMIC arrays.\n");
 
 	/* Dialog DA7219 Headset codec. */
 	if (nhlt_soc_add_da7219(nhlt, AUDIO_LINK_SSP1))
diff --git a/src/mainboard/google/poppy/variants/baseboard/nhlt.c b/src/mainboard/google/poppy/variants/baseboard/nhlt.c
index b3ead3b3de..c281096e95 100644
--- a/src/mainboard/google/poppy/variants/baseboard/nhlt.c
+++ b/src/mainboard/google/poppy/variants/baseboard/nhlt.c
@@ -11,10 +11,6 @@ void __weak variant_nhlt_init(struct nhlt *nhlt)
 	if (nhlt_soc_add_dmic_array(nhlt, 2))
 		printk(BIOS_ERR, "Couldn't add 2CH DMIC array.\n");
 
-	/* 4 Channel DMIC array. */
-	if (nhlt_soc_add_dmic_array(nhlt, 4))
-		printk(BIOS_ERR, "Couldn't add 4CH DMIC arrays.\n");
-
 	/* Maxim MAX98927 Smart Amps for left and right channel */
 	/* Render time_slot is 0 and feedback time_slot is 2 */
 	if (nhlt_soc_add_max98927(nhlt, AUDIO_LINK_SSP0, 0, 2))
diff --git a/src/mainboard/google/poppy/variants/nami/nhlt.c b/src/mainboard/google/poppy/variants/nami/nhlt.c
index 5cd8e5ab60..1fc379efb3 100644
--- a/src/mainboard/google/poppy/variants/nami/nhlt.c
+++ b/src/mainboard/google/poppy/variants/nami/nhlt.c
@@ -7,9 +7,9 @@
 
 void variant_nhlt_init(struct nhlt *nhlt)
 {
-	/* 4 Channel DMIC array. */
-	if (nhlt_soc_add_dmic_array(nhlt, 4))
-		printk(BIOS_ERR, "Couldn't add 4CH DMIC array.\n");
+	/* 2 Channel DMIC array. */
+	if (nhlt_soc_add_dmic_array(nhlt, 2))
+		printk(BIOS_ERR, "Couldn't add 2CH DMIC array.\n");
 
 	/* Dialog DA7219 Headset codec. */
 	if (nhlt_soc_add_da7219(nhlt, AUDIO_LINK_SSP1))
diff --git a/src/mainboard/google/poppy/variants/nautilus/nhlt.c b/src/mainboard/google/poppy/variants/nautilus/nhlt.c
index ed44b8466c..fb4e466c26 100644
--- a/src/mainboard/google/poppy/variants/nautilus/nhlt.c
+++ b/src/mainboard/google/poppy/variants/nautilus/nhlt.c
@@ -7,9 +7,9 @@
 
 void variant_nhlt_init(struct nhlt *nhlt)
 {
-	/* 4 Channel DMIC array. */
-	if (nhlt_soc_add_dmic_array(nhlt, 4))
-		printk(BIOS_ERR, "Couldn't add 4CH DMIC array.\n");
+	/* 2 Channel DMIC array. */
+	if (nhlt_soc_add_dmic_array(nhlt, 2))
+		printk(BIOS_ERR, "Couldn't add 2CH DMIC array.\n");
 
 	/* Dialog DA7219 Headset codec. */
 	if (nhlt_soc_add_da7219(nhlt, AUDIO_LINK_SSP1))
diff --git a/src/mainboard/google/poppy/variants/nocturne/nhlt.c b/src/mainboard/google/poppy/variants/nocturne/nhlt.c
index a3b239932c..03a14f4128 100644
--- a/src/mainboard/google/poppy/variants/nocturne/nhlt.c
+++ b/src/mainboard/google/poppy/variants/nocturne/nhlt.c
@@ -7,9 +7,9 @@
 
 void variant_nhlt_init(struct nhlt *nhlt)
 {
-	/* 4 Channel DMIC array. */
-	if (nhlt_soc_add_dmic_array(nhlt, 4))
-		printk(BIOS_ERR, "Couldn't add 4CH DMIC array.\n");
+	/* 2 Channel DMIC array. */
+	if (nhlt_soc_add_dmic_array(nhlt, 2))
+		printk(BIOS_ERR, "Couldn't add 2CH DMIC array.\n");
 
 	/* MAXIM Smart Amps for left and right speakers. */
 	/* Render time_slot is 0 and feedback time_slot is 2 */
diff --git a/src/mainboard/google/poppy/variants/rammus/nhlt.c b/src/mainboard/google/poppy/variants/rammus/nhlt.c
index 49a3f7a11a..0f92728b42 100644
--- a/src/mainboard/google/poppy/variants/rammus/nhlt.c
+++ b/src/mainboard/google/poppy/variants/rammus/nhlt.c
@@ -7,9 +7,9 @@
 
 void variant_nhlt_init(struct nhlt *nhlt)
 {
-	/* 4 Channel DMIC array. */
-	if (nhlt_soc_add_dmic_array(nhlt, 4))
-		printk(BIOS_ERR, "Couldn't add 4CH DMIC array.\n");
+	/* 2 Channel DMIC array. */
+	if (nhlt_soc_add_dmic_array(nhlt, 2))
+		printk(BIOS_ERR, "Couldn't add 2CH DMIC array.\n");
 
 	/* Dialog DA7219 Headset codec. */
 	if (nhlt_soc_add_da7219(nhlt, AUDIO_LINK_SSP1))

From b3b18097649b1b569c4b363d664c0383b9417151 Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Thu, 12 Jun 2025 13:15:17 -0500
Subject: [PATCH 1328/3886] mb/google/octopus: Correct channel count for DMIC

These boards only have 2 DMIC physically connected, and attempting to
record from 4 channels vs 2 results in a large amount of background
noise which drowns out the recording. Selecting the 2 channel DMIC
shows audio on both channels and no noise.

TEST=build/boot octopus variants, test built-in mic under Windows
and Linux.

Change-Id: I70c4b3a8f1ece16cb1c134c6b4c786eb4a685bc5
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88083
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
---
 src/mainboard/google/octopus/Kconfig                   | 1 -
 src/mainboard/google/octopus/variants/baseboard/nhlt.c | 4 ----
 2 files changed, 5 deletions(-)

diff --git a/src/mainboard/google/octopus/Kconfig b/src/mainboard/google/octopus/Kconfig
index f5aed08225..3078224cc9 100644
--- a/src/mainboard/google/octopus/Kconfig
+++ b/src/mainboard/google/octopus/Kconfig
@@ -152,7 +152,6 @@ config UART_FOR_CONSOLE
 config INCLUDE_NHLT_BLOBS
 	bool "Include blobs for audio"
 	select NHLT_DMIC_2CH_16B
-	select NHLT_DMIC_4CH_16B
 	select NHLT_MAX98357
 
 config DRIVER_TPM_SPI_BUS
diff --git a/src/mainboard/google/octopus/variants/baseboard/nhlt.c b/src/mainboard/google/octopus/variants/baseboard/nhlt.c
index 320e470c91..89f16c7b46 100644
--- a/src/mainboard/google/octopus/variants/baseboard/nhlt.c
+++ b/src/mainboard/google/octopus/variants/baseboard/nhlt.c
@@ -14,10 +14,6 @@ void __weak variant_nhlt_init(struct nhlt *nhlt)
 	if (!nhlt_soc_add_dmic_array(nhlt, 2))
 		printk(BIOS_INFO, "Added 2CH DMIC array.\n");
 
-	/* 4 Channel DMIC array. */
-	if (!nhlt_soc_add_dmic_array(nhlt, 4))
-		printk(BIOS_INFO, "Added 4CH DMIC arrays.\n");
-
 	/*
 	 * Headset codec is bi-directional but uses the same configuration
 	 * settings for render and capture endpoints.

From afbc9126f9a722728b8ef85a006e71750ccdd1b5 Mon Sep 17 00:00:00 2001
From: Luca Lai <luca.lai@lcfc.corp-partner.google.com>
Date: Wed, 11 Jun 2025 17:00:40 +0800
Subject: [PATCH 1329/3886] mb/trulo/var/pujjolo: Update GPIOs and probe SD
 card to fix S0ix suspend

Now we face the suspend could not enter s0ix issue.
So according to the schematics 627075_TWL PCH GPIO_Pujjolo_1th version
_20250527.xlsx to change gpio setting and hook up the SD card reader
via fwconfig to fix the issue.

Change :
1. gpio GPP_D8(SD_CLKREQ_ODL) to native function 1
2. add probe sd card.

BUG=b:422600523
BRANCH=none
TEST=Build and boot to OS. Verify powerd_dbus_suspend could enter S0ix

Change-Id: Iaa5a653608316ca8cb1e34429d30a2ebfdf7a1e9
Signed-off-by: Luca Lai <luca.lai@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88050
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/google/brya/variants/pujjolo/gpio.c          | 4 ++--
 src/mainboard/google/brya/variants/pujjolo/overridetree.cb | 5 +++++
 2 files changed, 7 insertions(+), 2 deletions(-)

diff --git a/src/mainboard/google/brya/variants/pujjolo/gpio.c b/src/mainboard/google/brya/variants/pujjolo/gpio.c
index 017407c0c2..7717efe1ac 100644
--- a/src/mainboard/google/brya/variants/pujjolo/gpio.c
+++ b/src/mainboard/google/brya/variants/pujjolo/gpio.c
@@ -130,8 +130,8 @@ static const struct pad_config override_gpio_table[] = {
 	PAD_CFG_GPO(GPP_D6, 1, DEEP),
 	/* D7  : SRCCLKREQ2# ==> WLAN_CLKREQ_ODL */
 	PAD_CFG_NF(GPP_D7, NONE, DEEP, NF1),
-	/* D8  : SRCCLKREQ3# ==> NC */
-	PAD_NC_LOCK(GPP_D8, NONE, LOCK_CONFIG),
+	/* D8  : SRCCLKREQ3# ==> SD_CLKREQ_ODL */
+	PAD_CFG_NF(GPP_D8, NONE, DEEP, NF1),
 	/* D9  : NC */
 	PAD_NC_LOCK(GPP_D9, NONE, LOCK_CONFIG),
 	/* D10 : ISH_SPI_CLK ==> GPP_D10_STRAP */
diff --git a/src/mainboard/google/brya/variants/pujjolo/overridetree.cb b/src/mainboard/google/brya/variants/pujjolo/overridetree.cb
index d3c938252a..7bb97140a6 100644
--- a/src/mainboard/google/brya/variants/pujjolo/overridetree.cb
+++ b/src/mainboard/google/brya/variants/pujjolo/overridetree.cb
@@ -8,6 +8,10 @@ fw_config
 		option WIFI_SAR_TABLE_AX211	0
 		option WIFI_SAR_TABLE_AX203	1
 	end
+	field SD_CARD 22
+		option SD_ABSENT	0
+		option SD_PRESENT	1
+	end
 end
 chip soc/intel/alderlake
 
@@ -474,6 +478,7 @@ chip soc/intel/alderlake
 				register "srcclk_pin" = "3"
 				device generic 0 on end
 			end
+			probe SD_CARD SD_PRESENT
 		end	#PCIE7 SD card
 		device ref pch_espi on
 			chip ec/google/chromeec

From 992ba781422ffc4956b30f1b9a943e8a25a810e0 Mon Sep 17 00:00:00 2001
From: Pranava Y N <pranavayn@google.com>
Date: Fri, 13 Jun 2025 21:30:36 +0530
Subject: [PATCH 1330/3886] mb/google/fatcat: Create `felino` model for easier
 variant integration

This patch creates a felino model Kconfig `BOARD_GOOGLE_MODEL_FELINO`
so that different variants can easily select the configs without any
duplication.

This change is made to support `felino` and `felino4es` variants.

BUG=b:424355826
TEST=Able to build google/felino

Change-Id: I38d72eada28734ed26427dbd85ab603cddab258c
Signed-off-by: Pranava Y N <pranavayn@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88095
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/google/fatcat/Kconfig | 20 ++++++++++++--------
 1 file changed, 12 insertions(+), 8 deletions(-)

diff --git a/src/mainboard/google/fatcat/Kconfig b/src/mainboard/google/fatcat/Kconfig
index f822424e82..d599e8228f 100644
--- a/src/mainboard/google/fatcat/Kconfig
+++ b/src/mainboard/google/fatcat/Kconfig
@@ -64,6 +64,14 @@ config BOARD_GOOGLE_MODEL_FATCAT
 	select DRIVERS_INTEL_TOUCH
 	select FSP_UGOP_EARLY_SIGN_OF_LIFE
 
+config BOARD_GOOGLE_MODEL_FELINO
+	def_bool n
+	select BOARD_GOOGLE_BASEBOARD_FATCAT
+	select FSP_UGOP_EARLY_SIGN_OF_LIFE
+	select HAVE_SLP_S0_GATE
+	select DRIVERS_SOUNDWIRE_ALC1320
+	select MAINBOARD_HAS_GOOGLE_STRAUSS_KEYBOARD
+
 config BOARD_GOOGLE_FATCAT
 	select BOARD_GOOGLE_MODEL_FATCAT
 	select EC_GOOGLE_CHROMEEC_MEC
@@ -81,11 +89,7 @@ config BOARD_GOOGLE_FATCATITE
 	select BOARD_GOOGLE_MODEL_FATCAT
 
 config BOARD_GOOGLE_FELINO
-	select BOARD_GOOGLE_BASEBOARD_FATCAT
-	select FSP_UGOP_EARLY_SIGN_OF_LIFE
-	select HAVE_SLP_S0_GATE
-	select DRIVERS_SOUNDWIRE_ALC1320
-	select MAINBOARD_HAS_GOOGLE_STRAUSS_KEYBOARD
+	select BOARD_GOOGLE_MODEL_FELINO
 
 config BOARD_GOOGLE_FRANCKA
 	select BOARD_GOOGLE_BASEBOARD_FATCAT
@@ -130,7 +134,7 @@ config DRIVER_TPM_I2C_BUS
 	hex
 	default 0x03 if BOARD_GOOGLE_MODEL_FATCAT
 	default 0x01 if BOARD_GOOGLE_FRANCKA
-	default 0x01 if BOARD_GOOGLE_FELINO
+	default 0x01 if BOARD_GOOGLE_MODEL_FELINO
 	default 0x03 if BOARD_GOOGLE_KINMEN
 
 config HAVE_SLP_S0_GATE
@@ -160,7 +164,7 @@ config MEMORY_SOLDERDOWN
 config TPM_TIS_ACPI_INTERRUPT
 	int
 	default 47 if BOARD_GOOGLE_MODEL_FATCAT # GPE0_DW1_15 (GPP_D15)
-	default 79 if BOARD_GOOGLE_FELINO # GPE0_DW2_15 (GPP_F15)
+	default 79 if BOARD_GOOGLE_MODEL_FELINO # GPE0_DW2_15 (GPP_F15)
 	default 11 if BOARD_GOOGLE_FRANCKA # GPE0_DW0_11 (GPP_H11)
 	default 66 if BOARD_GOOGLE_KINMEN # GPE0_DW2_02 (GPP_E02)
 
@@ -176,7 +180,7 @@ config VARIANT_DIR
 	string
 	default "fatcat" if BOARD_GOOGLE_MODEL_FATCAT
 	default "francka" if BOARD_GOOGLE_FRANCKA
-	default "felino" if BOARD_GOOGLE_FELINO
+	default "felino" if BOARD_GOOGLE_MODEL_FELINO
 	default "kinmen" if BOARD_GOOGLE_KINMEN
 
 config OVERRIDE_DEVICETREE

From f18420b6a9d6f4ada5c7c13eec5c2c02e78451cc Mon Sep 17 00:00:00 2001
From: Pranava Y N <pranavayn@google.com>
Date: Fri, 13 Jun 2025 21:40:02 +0530
Subject: [PATCH 1331/3886] mb/google/fatcat: Create new felino4es variant

This patch creates a new variant `felino4es`.

The new variant will support PTL ES1 samples. This existing `felino`
variant will support ES2 and QS samples.

BUG=b:424355826
TEST=Able to build google/felino4es

Change-Id: I9da7ad9fcdd4467d5b7ab5c31ffba6f3c8b3a943
Signed-off-by: Pranava Y N <pranavayn@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88096
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/google/fatcat/Kconfig                           | 4 ++++
 src/mainboard/google/fatcat/Kconfig.name                      | 3 +++
 .../fatcat/variants/baseboard/fatcat/include/baseboard/gpio.h | 2 +-
 3 files changed, 8 insertions(+), 1 deletion(-)

diff --git a/src/mainboard/google/fatcat/Kconfig b/src/mainboard/google/fatcat/Kconfig
index d599e8228f..7b9dcf5335 100644
--- a/src/mainboard/google/fatcat/Kconfig
+++ b/src/mainboard/google/fatcat/Kconfig
@@ -91,6 +91,9 @@ config BOARD_GOOGLE_FATCATITE
 config BOARD_GOOGLE_FELINO
 	select BOARD_GOOGLE_MODEL_FELINO
 
+config BOARD_GOOGLE_FELINO4ES
+	select BOARD_GOOGLE_MODEL_FELINO
+
 config BOARD_GOOGLE_FRANCKA
 	select BOARD_GOOGLE_BASEBOARD_FATCAT
 	select HAVE_SLP_S0_GATE
@@ -154,6 +157,7 @@ config MAINBOARD_PART_NUMBER
 	default "Fatcatnuvo" if BOARD_GOOGLE_FATCATNUVO
 	default "Francka" if BOARD_GOOGLE_FRANCKA
 	default "Felino" if BOARD_GOOGLE_FELINO
+	default "Felino4ES" if BOARD_GOOGLE_FELINO4ES
 	default "Kinmen" if BOARD_GOOGLE_KINMEN
 
 config MEMORY_SOLDERDOWN
diff --git a/src/mainboard/google/fatcat/Kconfig.name b/src/mainboard/google/fatcat/Kconfig.name
index 48844c6424..e9bf37e570 100644
--- a/src/mainboard/google/fatcat/Kconfig.name
+++ b/src/mainboard/google/fatcat/Kconfig.name
@@ -17,6 +17,9 @@ config BOARD_GOOGLE_FATCATNUVO
 config BOARD_GOOGLE_FELINO
 	bool "-> Felino"
 
+config BOARD_GOOGLE_FELINO4ES
+	bool "-> Felino4ES"
+
 config BOARD_GOOGLE_FRANCKA
 	bool "-> Francka"
 
diff --git a/src/mainboard/google/fatcat/variants/baseboard/fatcat/include/baseboard/gpio.h b/src/mainboard/google/fatcat/variants/baseboard/fatcat/include/baseboard/gpio.h
index 9adbb9212c..56f57f9950 100644
--- a/src/mainboard/google/fatcat/variants/baseboard/fatcat/include/baseboard/gpio.h
+++ b/src/mainboard/google/fatcat/variants/baseboard/fatcat/include/baseboard/gpio.h
@@ -25,7 +25,7 @@
  #define GPIO_PCH_WP	GPP_E22
 /* Used to gate SoC's SLP_S0# signal */
 #define GPIO_SLP_S0_GATE	GPP_F23
-#elif CONFIG(BOARD_GOOGLE_FELINO)
+#elif CONFIG(BOARD_GOOGLE_MODEL_FELINO)
  #define EC_SYNC_IRQ	GPP_E03_IRQ
  #define GPIO_PCH_WP	GPP_C08
 /* Used to gate SoC's SLP_S0# signal */

From 6e58c0148bc1778798b30e55798fce1b8b3bed51 Mon Sep 17 00:00:00 2001
From: Julius Werner <jwerner@chromium.org>
Date: Fri, 13 Jun 2025 23:10:22 +0000
Subject: [PATCH 1332/3886] Reland "libpayload: arm64: Reduce DMA allocator
 space to 1MB"

This reverts commit 4199351c1b29fad6c8b1d4ed916de3aa44c03924 which
originally reverted aedc177f000a3fd62c75f555c116ad956443ab1e.

Reason for revert: CB:88063 fixed the bug that this patch exposed.

Change-Id: Ic7a798b4b9236b8c0c7ad8568562d11071ae96a9
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88097
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
---
 payloads/libpayload/include/arm64/arch/mmu.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/payloads/libpayload/include/arm64/arch/mmu.h b/payloads/libpayload/include/arm64/arch/mmu.h
index 2b1e9e120c..9ed951d336 100644
--- a/payloads/libpayload/include/arm64/arch/mmu.h
+++ b/payloads/libpayload/include/arm64/arch/mmu.h
@@ -161,7 +161,7 @@ extern char _start[], _end[];
 #define TCR_TBI_USED               (0x0 << TCR_TBI_SHIFT)
 #define TCR_TBI_IGNORED            (0x1 << TCR_TBI_SHIFT)
 
-#define DMA_DEFAULT_SIZE           (32 * MiB)
+#define DMA_DEFAULT_SIZE           (1 * MiB)
 #define TTB_DEFAULT_SIZE           0x100000
 
 #define MB_SIZE			   (1UL << 20)

From b9aae6180b41277bcd989766ed63091f4b3eb2b9 Mon Sep 17 00:00:00 2001
From: Simon Yang <simon1.yang@intel.com>
Date: Tue, 20 May 2025 19:10:46 +0800
Subject: [PATCH 1333/3886] mb/google/nissa/var/meliks: Link touchscreen device
 with display panel

In some panels, the power supply for the display and the I2C touch
screen comes from the same source. As a result, if the display is not
powered on, the I2C bus will also be unpowered. This leads to a problem
: if the Intel DRM driver has not yet reached the stage where it powers
on the display, the I2C touch screen device integrated into the panel
will remain unpowered as well. A similar issue can also occur after
resuming from s0ix.

In Linux-like systems, the Intel DRM driver and the generic I2C driver
operate independently, so their execution order in the kernel cannot be
guaranteed.

Kernel patchsets link:
https://lore.kernel.org/all/cover.1749199013.git.jani.nikula@intel.com/

Due to the required kernel changes mentioned above, an ACPI device LCD0
needs to be declared under GFX0, and a _DSD declaration must be added
to the I2C touch screen device.

An example that clearly illustrates the required ACPI change:

    Scope (\_SB.PCI0.GFX0)
    {
        ...

        Device (LCD0)
        {
            Name (_STA, 0x0F)  // _STA: Status

            ...
        }
    }

    Scope (\_SB.PCI0.I2C1)
    {
        ....

        Name (_DSD, Package (0x02)  // _DSD: Device-Specific Data
        {
            ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301") /* Device Properties for _DSD */,
            Package (0x02)
            {
                ...

                Package (0x02)
                {
                    "panel",
                    \_SB.PCI0.GFX0.LCD0
                }
            }
        })
    }

BUG=b:398703068
TEST=Extracted SSDT contains a required _DSD entry within the I2C1
touchscreen device scope

Cq-Depend: chromium:6626797
Change-Id: I73058851c35a7190d70a51a554cccf21253fc59b
Signed-off-by: Simon Yang <simon1.yang@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87762
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
---
 src/mainboard/google/brya/variants/meliks/overridetree.cb | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/src/mainboard/google/brya/variants/meliks/overridetree.cb b/src/mainboard/google/brya/variants/meliks/overridetree.cb
index 203edb4686..9595616aaf 100644
--- a/src/mainboard/google/brya/variants/meliks/overridetree.cb
+++ b/src/mainboard/google/brya/variants/meliks/overridetree.cb
@@ -240,6 +240,10 @@ chip soc/intel/alderlake
 				register "generic.reset_off_delay_ms" = "2"
 				register "generic.has_power_resource" = "1"
 				register "generic.use_gpio_for_status" = "true"
+				register "generic.property_count" = "1"
+				register "generic.property_list[0].type" = "ACPI_DP_TYPE_REFERENCE"
+				register "generic.property_list[0].name" = ""panel""
+				register "generic.property_list[0].string" = ""\\_SB.PCI0.GFX0.LCD0""
 				register "hid_desc_reg_offset" = "0x1"
 				device i2c 4F on end
 			end

From 19d1604fd72804303b706efec3c98a1af64bbc39 Mon Sep 17 00:00:00 2001
From: Subrata Banik <subratabanik@google.com>
Date: Thu, 12 Jun 2025 06:51:04 +0000
Subject: [PATCH 1334/3886] mb/google/bluey: Update flash layout

This patch updates flash layout for Bluey as below:

WP_RO:  4MB -> 12MB
 |
 |----> bootblock: 120KB -> 512KB
 |
 |----> FMAP: Start offset 0x3c0000 -> Start offset post bootblock
 |
 |----> CBFS: Start offset post bootblock -> Start offset post FMAP
 |
 |----> RO_VPD: Limit size to 16KB

RW_MISC: 128KB -> 120KB

RW_SECTION_A/B: 1536KB -> 1984KB

This patch allows COREBOOT CBFS to grow beyond 3.75MB as per
planned growth in CBFS (inside WP_RO) due to the addition of SoC
firmware binaries.

TEST=Able to build AP FW image for google/bluey.

Change-Id: I2f3b4b44960dfb24287cc62758323b18647bd621
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88069
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
---
 src/mainboard/google/bluey/chromeos.fmd | 16 ++++++++--------
 1 file changed, 8 insertions(+), 8 deletions(-)

diff --git a/src/mainboard/google/bluey/chromeos.fmd b/src/mainboard/google/bluey/chromeos.fmd
index 1bea2f9397..2396097aae 100644
--- a/src/mainboard/google/bluey/chromeos.fmd
+++ b/src/mainboard/google/bluey/chromeos.fmd
@@ -1,19 +1,19 @@
 ## SPDX-License-Identifier: GPL-2.0-only
 
 FLASH@0x0 CONFIG_ROM_SIZE {
-	WP_RO 4M {
-		RO_SECTION 0x3c4000 {
-			BOOTBLOCK 120K
+	WP_RO 12M {
+		RO_SECTION {
+			BOOTBLOCK 512K
+			FMAP 4K
 			COREBOOT(CBFS)
-			FMAP@0x3c0000 0x1000
 			GBB 0x2f00
 			RO_FRID 0x100
 		}
 		RO_GSCVD 8K
-		RO_VPD(PRESERVE)
+		RO_VPD(PRESERVE) 16K
 	}
 
-	RW_MISC 128K {
+	RW_MISC 120K {
 		UNIFIED_MRC_CACHE(PRESERVE) 64K {
 			RECOVERY_MRC_CACHE 32K
 			RW_MRC_CACHE 32K
@@ -26,13 +26,13 @@ FLASH@0x0 CONFIG_ROM_SIZE {
 		RW_NVRAM(PRESERVE) 16K
 	}
 
-	RW_SECTION_A 1536K {
+	RW_SECTION_A 1984K {
 		VBLOCK_A 8K
 		FW_MAIN_A(CBFS)
 		RW_FWID_A 256
 	}
 
-	RW_SECTION_B 1536K {
+	RW_SECTION_B 1984K {
 		VBLOCK_B 8K
 		FW_MAIN_B(CBFS)
 		RW_FWID_B 256

From b36975668055ae229351d638954be688f462fbc7 Mon Sep 17 00:00:00 2001
From: Kapil Porwal <kapilporwal@google.com>
Date: Wed, 28 May 2025 12:50:39 +0530
Subject: [PATCH 1335/3886] util/qualcomm: Add script to extract a segment from
 ELF

Create a new script to extract
- ELF header
- Program header table (PHT)
- A given segment number
- Hash table segment with type as NULL and p_flags as 0x02000000
from an ELF.

Usage:

```
elf_segment_extractor.py [--eh] [--pht] [--segment <index>] [--hashtable]  <elf_file> <output_file>
```

BUG=b:419213272
TEST=Extract first segment alongwith ELF header and PHT.
TEST=Extract a segment with an index number.
TEST=Extract the last segment if index is 'N'.
TEST=Extract hash table segment alongwith ELF header and PHT.

e.g.
elf_segment_extractor.py --eh --pht --segment 0 cpucp.elf cpucp_meta
elf_segment_extractor.py --segment 0 cpucp.elf cpucp_meta
elf_segment_extractor.py --segment N cpucp.elf cpucp_meta
elf_segment_extractor.py --eh --pht --hashtable cpucp.elf cpucp_meta

Change-Id: I1ea58d0ca17ad66463ffe7345a27e91dc0d22d2f
Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87888
Reviewed-by: Pranava Y N <pranavayn@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 util/qualcomm/elf_segment_extractor.py | 381 +++++++++++++++++++++++++
 1 file changed, 381 insertions(+)
 create mode 100755 util/qualcomm/elf_segment_extractor.py

diff --git a/util/qualcomm/elf_segment_extractor.py b/util/qualcomm/elf_segment_extractor.py
new file mode 100755
index 0000000000..7ba6e8aabf
--- /dev/null
+++ b/util/qualcomm/elf_segment_extractor.py
@@ -0,0 +1,381 @@
+#!/usr/bin/env python
+import sys
+import os
+import struct
+import argparse # Import the argparse module
+
+# --- Constants for ELF parsing ---
+
+# e_ident (first 16 bytes of ELF header)
+EI_MAG0 = 0   # File identifier
+EI_MAG1 = 1
+EI_MAG2 = 2
+EI_MAG3 = 3
+EI_CLASS = 4  # File class (32-bit or 64-bit)
+EI_DATA = 5   # Data encoding (endianness)
+EI_VERSION = 6 # ELF header version
+EI_OSABI = 7  # OS/ABI identification
+EI_ABIVERSION = 8 # ABI version
+EI_PAD = 9    # Start of padding bytes
+
+# ELF Class definitions
+ELFCLASSNONE = 0
+ELFCLASS32 = 1 # 32-bit ELF
+ELFCLASS64 = 2 # 64-bit ELF
+
+# ELF Data encoding definitions
+ELFDATANONE = 0
+ELFDATA2LSB = 1 # Little-endian
+ELFDATA2MSB = 2 # Big-endian
+
+# ELF Header offsets and sizes (for 32-bit and 64-bit)
+# All values are in bytes
+ELF_HEADER_SIZE_32 = 52
+ELF_HEADER_SIZE_64 = 64
+
+# Program Header (Phdr) offsets and sizes (relative to start of Phdr entry)
+# These vary based on ELF class (32-bit or 64-bit)
+
+# 32-bit Program Header (Elf32_Phdr) structure
+# typedef struct {
+#     Elf32_Word  p_type;    /* Segment type */
+#     Elf32_Off   p_offset;  /* Segment file offset */
+#     Elf32_Addr  p_vaddr;   /* Segment virtual address */
+#     Elf32_Addr  p_paddr;   /* Segment physical address */
+#     Elf32_Word  p_filesz;  /* Segment size in file */
+#     Elf32_Word  p_memsz;   /* Segment size in memory */
+#     Elf32_Word  p_flags;   /* Segment flags */
+#     Elf32_Word  p_align;   /* Segment alignment */
+# } Elf32_Phdr;
+PHDR_32_FMT = '<IIIIIIII' # Little-endian, 8 unsigned ints (4 bytes each)
+PHDR_32_SIZE = 32 # Total size of 32-bit program header entry
+
+# 64-bit Program Header (Elf64_Phdr) structure
+# typedef struct {
+#     Elf64_Word  p_type;    /* Segment type */
+#     Elf64_Word  p_flags;   /* Segment flags */
+#     Elf64_Off   p_offset;  /* Segment file offset */
+#     Elf64_Addr  p_vaddr;   /* Segment virtual address */
+#     Elf64_Addr  p_paddr;   /* Segment physical address */
+#     Elf64_Xword p_filesz;  /* Segment size in file */
+#     Elf64_Xword p_memsz;   /* Segment size in memory */
+#     Elf64_Xword p_align;   /* Segment alignment */
+# } Elf64_Phdr;
+# Note: p_type and p_flags are 4 bytes, others are 8 bytes
+PHDR_64_FMT = '<IIQQQQQQ' # Little-endian, 2 unsigned ints (4 bytes), 6 unsigned long longs (8 bytes)
+PHDR_64_SIZE = 56 # Total size of 64-bit program header entry
+
+def parse_elf_header(f):
+    """
+    Parses the ELF header from the given file object and returns both parsed info and raw header bytes.
+
+    Args:
+        f (file): The file object opened in binary read mode.
+
+    Returns:
+        tuple: A tuple containing (dict: parsed ELF header information, bytes: raw ELF header data).
+               Returns (None, None) if the file is not a valid ELF or unsupported.
+    """
+    f.seek(0)
+    e_ident = f.read(16)
+
+    # Check ELF magic bytes
+    if not (e_ident[EI_MAG0] == 0x7F and
+            e_ident[EI_MAG1] == ord('E') and
+            e_ident[EI_MAG2] == ord('L') and
+            e_ident[EI_MAG3] == ord('F')):
+        print("Error: Not an ELF file (invalid magic bytes).")
+        return None, None
+
+    elf_class = e_ident[EI_CLASS]
+    elf_data_encoding = e_ident[EI_DATA]
+
+    endian_char = ''
+    if elf_data_encoding == ELFDATA2LSB:
+        endian_char = '<' # Little-endian
+    elif elf_data_encoding == ELFDATA2MSB:
+        endian_char = '>' # Big-endian
+    else:
+        print("Error: Unsupported ELF data encoding.")
+        return None, None
+
+    raw_header_bytes = b'' # To store the entire raw ELF header
+
+    if elf_class == ELFCLASS32:
+        # 32-bit ELF header format: 2xH, 5xI, 6xH (Total 36 bytes for remaining header)
+        header_fmt = f"{endian_char}HHI IIII HHHHHH"
+        header_data_rest = f.read(ELF_HEADER_SIZE_32 - 16)
+        raw_header_bytes = e_ident + header_data_rest # Concatenate e_ident with the rest
+
+        (e_type, e_machine, e_version, e_entry, e_phoff, e_shoff,
+         e_flags, e_ehsize, e_phentsize, e_phnum, e_shentsize, e_shnum, e_shstrndx) = \
+            struct.unpack(header_fmt, header_data_rest)
+        elf_header = {
+            'class': elf_class,
+            'endian': endian_char,
+            'e_phoff': e_phoff,
+            'e_phentsize': e_phentsize,
+            'e_phnum': e_phnum,
+            'ehsize': ELF_HEADER_SIZE_32
+        }
+    elif elf_class == ELFCLASS64:
+        # 64-bit ELF header format: 2xH, 1xI, 3xQ, 1xI, 6xH (Total 48 bytes for remaining header)
+        header_fmt = f"{endian_char}HHI QQQ I HHHHHH"
+        header_data_rest = f.read(ELF_HEADER_SIZE_64 - 16)
+        raw_header_bytes = e_ident + header_data_rest # Concatenate e_ident with the rest
+
+        (e_type, e_machine, e_version, e_entry, e_phoff, e_shoff,
+         e_flags, e_ehsize, e_phentsize, e_phnum, e_shentsize, e_shnum, e_shstrndx) = \
+            struct.unpack(header_fmt, header_data_rest)
+        elf_header = {
+            'class': elf_class,
+            'endian': endian_char,
+            'e_phoff': e_phoff,
+            'e_phentsize': e_phentsize,
+            'e_phnum': e_phnum,
+            'ehsize': ELF_HEADER_SIZE_64
+        }
+    else:
+        print("Error: Unsupported ELF class.")
+        return None, None
+
+    return elf_header, raw_header_bytes
+
+def parse_program_header(f, elf_header, segment_index):
+    """
+    Parses a specific program header (segment) from the ELF file.
+
+    Args:
+        f (file): The file object.
+        elf_header (dict): Parsed ELF header information.
+        segment_index (int): The 0-based index of the program header to parse.
+
+    Returns:
+        dict: A dictionary containing parsed program header information (p_offset, p_filesz, p_type, p_flags).
+              Returns None if the index is out of bounds or parsing fails.
+    """
+    e_phoff = elf_header['e_phoff']
+    e_phentsize = elf_header['e_phentsize']
+    e_phnum = elf_header['e_phnum']
+    endian_char = elf_header['endian']
+    elf_class = elf_header['class']
+
+    if not (0 <= segment_index < e_phnum):
+        print(f"Error: Segment index {segment_index} is out of bounds.")
+        print(f"This ELF file has {e_phnum} segments (0 to {e_phnum - 1}).")
+        return None
+
+    # Calculate the offset to the desired program header entry
+    phdr_offset = e_phoff + (segment_index * e_phentsize)
+    f.seek(phdr_offset)
+
+    if elf_class == ELFCLASS32:
+        if e_phentsize != PHDR_32_SIZE:
+            print(f"Warning: Unexpected phentsize for 32-bit ELF: {e_phentsize}. Expected {PHDR_32_SIZE}.")
+        phdr_data = f.read(PHDR_32_SIZE)
+        (p_type, p_offset, p_vaddr, p_paddr, p_filesz, p_memsz, p_flags, p_align) = \
+            struct.unpack(f"{endian_char}{PHDR_32_FMT[1:]}", phdr_data)
+    elif elf_class == ELFCLASS64:
+        if e_phentsize != PHDR_64_SIZE:
+            print(f"Warning: Unexpected phentsize for 64-bit ELF: {e_phentsize}. Expected {PHDR_64_SIZE}.")
+        phdr_data = f.read(PHDR_64_SIZE)
+        (p_type, p_flags, p_offset, p_vaddr, p_paddr, p_filesz, p_memsz, p_align) = \
+            struct.unpack(f"{endian_char}{PHDR_64_FMT[1:]}", phdr_data)
+    else:
+        print("Error: Unsupported ELF class for parsing program header.")
+        return None
+
+    return {
+        'p_type': p_type,
+        'p_offset': p_offset,
+        'p_vaddr': p_vaddr,
+        'p_paddr': p_paddr,
+        'p_filesz': p_filesz,
+        'p_memsz': p_memsz,
+        'p_flags': p_flags,
+        'p_align': p_align
+    }
+
+
+def extract_elf_data(elf_file_path: str, output_file_path: str, extract_eh: bool, extract_pht: bool, segment_args_str: str = None, extract_hashtable: bool = False):
+    """
+    Extracts specified components from an ELF file (ELF Header, Program Headers, a specific Segment)
+    and concatenates them into a single output binary file.
+
+    Args:
+        elf_file_path (str): The path to the ELF file.
+        output_file_path (str): The path to the output binary file.
+        extract_eh (bool): True to extract the ELF header, False otherwise.
+        extract_pht (bool): True to extract all Program Headers, False otherwise.
+        segment_args_str (str, optional): A comma-separated string of 0-based segment indices,
+                                     or '$' / 'N' for the last segment. None if not extracting segments.
+        extract_hashtable (bool): True to extract segments where p_type is NULL (0) and p_flags is 0x02000000.
+    """
+    try:
+        with open(elf_file_path, 'rb') as f:
+            elf_header_info, raw_elf_header_bytes = parse_elf_header(f)
+            if elf_header_info is None:
+                return
+
+            output_data = b''
+
+            # 1. Extract ELF Header if requested
+            if extract_eh:
+                output_data += raw_elf_header_bytes
+                print(f"Included ELF Header ({len(raw_elf_header_bytes)} bytes).")
+
+            # 2. Extract Program Header Table (PHT) if requested
+            num_segments = elf_header_info['e_phnum']
+            all_program_headers_bytes = b''
+            if extract_pht:
+                if num_segments > 0:
+                    f.seek(elf_header_info['e_phoff'])
+                    all_program_headers_bytes = f.read(elf_header_info['e_phentsize'] * num_segments)
+                    output_data += all_program_headers_bytes
+                    print(f"Included all {num_segments} Program Headers ({len(all_program_headers_bytes)} bytes).")
+                else:
+                    print("Warning: No Program Headers found in ELF file to extract for PHT.")
+
+            # 3. Extract specific Segment data if requested via --segment
+            if segment_args_str is not None:
+                segments_to_extract_indices = []
+                # Split the comma-separated string and process each segment argument
+                for seg_arg in segment_args_str.split(','):
+                    seg_arg = seg_arg.strip() # Remove any whitespace
+                    if not seg_arg: # Skip empty strings from multiple commas (e.g., "0,,1")
+                        continue
+
+                    actual_segment_index = None
+                    if seg_arg == "$" or seg_arg.upper() == "N":
+                        if num_segments == 0:
+                            print(f"Error: No segments found in ELF file '{elf_file_path}'. Cannot extract last segment for '{seg_arg}'.")
+                            return
+                        actual_segment_index = num_segments - 1
+                        print(f"'{seg_arg}' detected. Auto-selecting last segment (index {actual_segment_index}).")
+                    else:
+                        try:
+                            actual_segment_index = int(seg_arg)
+                        except ValueError:
+                            print(f"Error: Invalid segment index or alias '{seg_arg}'. Segment index must be an integer, '$', or 'N'.")
+                            return
+
+                    if not (0 <= actual_segment_index < num_segments):
+                        print(f"Error: Segment index {actual_segment_index} is out of bounds for '{elf_file_path}'.")
+                        print(f"This ELF file has {num_segments} segments (0 to {num_segments - 1}).")
+                        return
+
+                    segments_to_extract_indices.append(actual_segment_index)
+
+                # Now extract data for each resolved segment index
+                for current_segment_index in segments_to_extract_indices:
+                    segment_info = parse_program_header(f, elf_header_info, current_segment_index)
+                    if segment_info is None:
+                        # Error message already printed by parse_program_header
+                        return
+
+                    p_offset = segment_info['p_offset']
+                    p_filesz = segment_info['p_filesz']
+
+                    if p_filesz > 0:
+                        f.seek(p_offset)
+                        segment_data_bytes = f.read(p_filesz)
+                        output_data += segment_data_bytes
+                        print(f"Included Segment {current_segment_index} data ({len(segment_data_bytes)} bytes) via --segment.")
+                    else:
+                        print(f"Warning: Segment {current_segment_index} has no data in the file (p_filesz is 0). Skipping via --segment.")
+
+            # 4. Extract segments based on --hashtable criteria
+            if extract_hashtable:
+                print("\nSearching for segments with p_type = 0 (NULL) and p_flags = 0x02000000...")
+                found_hashtable_segments = False
+                for i in range(num_segments):
+                    segment_info = parse_program_header(f, elf_header_info, i)
+                    if segment_info is None:
+                        continue # Skip if parsing failed for this segment
+
+                    if segment_info['p_type'] == 0 and segment_info['p_flags'] == 0x02000000:
+                        found_hashtable_segments = True
+                        p_offset = segment_info['p_offset']
+                        p_filesz = segment_info['p_filesz']
+
+                        if p_filesz > 0:
+                            f.seek(p_offset)
+                            segment_data_bytes = f.read(p_filesz)
+                            output_data += segment_data_bytes
+                            print(f"Included Segment {i} (Type: NULL, Flags: 0x{segment_info['p_flags']:x}) data ({len(segment_data_bytes)} bytes) via --hashtable.")
+                        else:
+                            print(f"Warning: Segment {i} (Type: NULL, Flags: 0x{segment_info['p_flags']:x}) has no data in the file (p_filesz is 0). Skipping via --hashtable.")
+                if not found_hashtable_segments:
+                    print("No segments found matching --hashtable criteria.")
+
+            # Write the concatenated data to the output file
+            if output_data:
+                try:
+                    with open(output_file_path, 'wb') as out_f:
+                        out_f.write(output_data)
+                    print(f"\nSuccessfully wrote {len(output_data)} bytes to '{output_file_path}'")
+                except IOError as io_e:
+                    print(f"Error writing to output file '{output_file_path}': {io_e}")
+                except Exception as write_e:
+                    print(f"An unexpected error occurred while writing: {write_e}")
+            else:
+                print("No data extracted based on the provided options. Output file was not created.")
+
+
+    except FileNotFoundError:
+        print(f"Error: ELF file not found at '{elf_file_path}'")
+    except Exception as e:
+        print(f"An error occurred: {e}")
+
+if __name__ == "__main__":
+    parser = argparse.ArgumentParser(
+        description="Extracts ELF Header, Program Headers, and/or specific Segments from an ELF file.",
+        formatter_class=argparse.RawTextHelpFormatter
+    )
+
+    parser.add_argument(
+        '--eh',
+        action='store_true',
+        help='Extract the ELF Header.'
+    )
+    parser.add_argument(
+        '--pht',
+        action='store_true',
+        help='Extract all Program Headers (Program Header Table).'
+    )
+    parser.add_argument(
+        '--segment',
+        type=str,
+        help='Specify a comma-separated list of 0-based segment indices to extract (e.g., "0,1,2").\n'
+             'Use "$" or "N" for the last segment (e.g., "0,N"). Segments will be concatenated in order.'
+    )
+    parser.add_argument(
+        '--hashtable',
+        action='store_true',
+        help='Extract all segments where p_type is NULL (0) and p_flags is 0x02000000.'
+    )
+    parser.add_argument(
+        'elf_file_path',
+        type=str,
+        help='Path to the input ELF file.'
+    )
+    parser.add_argument(
+        'output_file_path',
+        type=str,
+        help='Path to the output binary file where extracted data will be concatenated.'
+    )
+
+    args = parser.parse_args()
+
+    # Ensure at least one extraction option is provided
+    if not args.eh and not args.pht and args.segment is None and not args.hashtable:
+        parser.error("At least one extraction option (--eh, --pht, --segment, or --hashtable) must be provided.")
+
+    extract_elf_data(
+        args.elf_file_path,
+        args.output_file_path,
+        args.eh,
+        args.pht,
+        args.segment,
+        args.hashtable # Pass the new argument to the function
+    )

From a1d9b69f47637c2bc7a5ca6a2e4ede6fb9c37a06 Mon Sep 17 00:00:00 2001
From: Kapil Porwal <kapilporwal@google.com>
Date: Wed, 28 May 2025 14:13:53 +0530
Subject: [PATCH 1336/3886] soc/qc/x1p42100: Add metadata files for shrm and
 cpucp

Add shrm_meta and cpucp_meta as raw files to the CBFS.

BUG=b:419213272
TEST=Verify presence of metadata files in the CBFS.

Change-Id: If97e2d6395ef108f405a3b66727fb19648ddf03d
Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87889
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Varadarajan Narayanan <vnarayan@qualcomm.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
---
 src/soc/qualcomm/x1p42100/Makefile.mk | 29 +++++++++++++++++++++++++++
 1 file changed, 29 insertions(+)

diff --git a/src/soc/qualcomm/x1p42100/Makefile.mk b/src/soc/qualcomm/x1p42100/Makefile.mk
index f75fdd4f7f..7627320dbc 100644
--- a/src/soc/qualcomm/x1p42100/Makefile.mk
+++ b/src/soc/qualcomm/x1p42100/Makefile.mk
@@ -142,6 +142,21 @@ $(CPUCP_CBFS)-type := payload
 $(CPUCP_CBFS)-compression := $(CBFS_COMPRESS_FLAG)
 cbfs-files-y += $(CPUCP_CBFS)
 
+################################################################################
+# Rule to create cpucp_meta from cpucp.elf
+# This rule depends on cpucp.elf being built and the extractor script existing.
+$(obj)/mainboard/$(MAINBOARDDIR)/cpucp_meta: $(X1P42100_BLOB)/cpucp/cpucp.elf util/qualcomm/elf_segment_extractor.py
+	@echo "Extracting ELF headers and hash table segment from $< to $@"
+	@util/qualcomm/elf_segment_extractor.py --eh --pht --hashtable $< $@
+
+CPUCP_META_FILE := $(obj)/mainboard/$(MAINBOARDDIR)/cpucp_meta
+CPUCP_META_CBFS := $(CONFIG_CBFS_PREFIX)/cpucp_meta
+$(CPUCP_META_CBFS)-file := $(CPUCP_META_FILE)
+$(CPUCP_META_CBFS)-type := raw
+$(CPUCP_META_CBFS)-compression := $(CBFS_COMPRESS_FLAG)
+cbfs-files-y += $(CPUCP_META_CBFS)
+
+
 ################################################################################
 SHRM_FILE := $(X1P42100_BLOB)/shrm/shrm.elf
 SHRM_CBFS := $(CONFIG_CBFS_PREFIX)/shrm
@@ -150,6 +165,20 @@ $(SHRM_CBFS)-type := payload
 $(SHRM_CBFS)-compression := $(CBFS_PRERAM_COMPRESS_FLAG)
 cbfs-files-y += $(SHRM_CBFS)
 
+################################################################################
+# Rule to create shrm_meta from shrm.elf
+# This rule depends on shrm.elf being built and the extractor script existing.
+$(obj)/mainboard/$(MAINBOARDDIR)/shrm_meta: $(X1P42100_BLOB)/shrm/shrm.elf util/qualcomm/elf_segment_extractor.py
+	@echo "Extracting ELF headers and hash table segment from $< to $@"
+	@util/qualcomm/elf_segment_extractor.py --eh --pht --hashtable $< $@
+
+SHRM_META_FILE := $(obj)/mainboard/$(MAINBOARDDIR)/shrm_meta
+SHRM_META_CBFS := $(CONFIG_CBFS_PREFIX)/shrm_meta
+$(SHRM_META_CBFS)-file := $(SHRM_META_FILE)
+$(SHRM_META_CBFS)-type := raw
+$(SHRM_META_CBFS)-compression := $(CBFS_PRERAM_COMPRESS_FLAG)
+cbfs-files-y += $(SHRM_META_CBFS)
+
 ################################################################################
 GSI_FW_FILE := $(X1P42100_BLOB)/qup_fw/gsi_fw.bin
 GSI_FW_CBFS := $(CONFIG_CBFS_PREFIX)/gsi_fw

From f941b51e0e3cb2570a855984edfdd134a48f9d3f Mon Sep 17 00:00:00 2001
From: Irving-CH Lin <irving-ch.lin@mediatek.com>
Date: Wed, 11 Jun 2025 11:58:15 +0800
Subject: [PATCH 1337/3886] soc/mediatek/mt8189: Correct MFG MUX OPP init
 setting

Set the default MFG MUX OPP (Operating Performance Point) from 0
(mfg_sel) to 1 (mfgpll), as mfgpll is used in normal operation and
mfg_sel is only needed during DVFS transitions. Also enable glitch-free
configuration for mfgpll to improve PLL stability.

BUG=b:399571996
BRANCH=none
TEST=Change GPU DVFS by below commands:
echo 880000000 > /sys/devices/platform/soc/13000000.gpu/devfreq/13000000.gpu/min_freq
echo 880000000 > /sys/devices/platform/soc/13000000.gpu/devfreq/13000000.gpu/max_freq
And then check PLL and MUX register values are correct.

Signed-off-by: Irving-CH lin <irving-ch.lin@mediatek.corp-partner.google.com>
Change-Id: I285cc5f07facbb23a448151ceb6c1d037753432c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88090
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
---
 src/soc/mediatek/mt8189/pll.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/src/soc/mediatek/mt8189/pll.c b/src/soc/mediatek/mt8189/pll.c
index 84fb16347d..ffd48987e4 100644
--- a/src/soc/mediatek/mt8189/pll.c
+++ b/src/soc/mediatek/mt8189/pll.c
@@ -559,6 +559,7 @@ void mt_pll_init(void)
 	write32(&mtk_apmixed->apll1_tuner_con0, 0x6F28BD4D);
 	write32(&mtk_apmixed->apll2_tuner_con0, 0x78FD5266);
 	setbits32(&mtk_apmixed->emipll_con[0], BIT(8));
+	setbits32(&mtk_apmixed->mfgpll_con[0], BIT(8));
 
 	/* PLL all enable */
 	write32(&mtk_apmixed->pllen_all_set, 0x0007FFFC);
@@ -622,7 +623,7 @@ void mt_pll_post_init(void)
 
 	/* TOPCKGEN CG Clear */
 	write32(&mtk_topckgen->clk_misc_cfg_3.clr, 0x00010000);
-	write32(&mtk_topckgen->clk_misc_cfg_3.set, 0xDF3CFCFF);
+	write32(&mtk_topckgen->clk_misc_cfg_3.set, 0xDF3DFCFF);
 	/* INFRACFG_AO CG Clear */
 	write32(&mtk_infracfg_ao->infracfg_ao_module_cg_0_clr, 0x10000000);
 	write32(&mtk_infracfg_ao->infracfg_ao_module_cg_1_clr, 0x21000000);

From ad78fc535a551fee3fb476fa44efff42272d2683 Mon Sep 17 00:00:00 2001
From: Luca Lai <luca.lai@lcfc.corp-partner.google.com>
Date: Tue, 10 Jun 2025 21:31:02 +0800
Subject: [PATCH 1338/3886] mb/trulo/var/pujjolo: Add single ram configuration

Pujjolo project is going to have single RAM devices,so add single
ram configuration.

BUG=b:395763555
BRANCH=none
TEST=Build and boot to OS. Verify functions work.

Change-Id: I92b0bd1e05276c170d35ce20508cc6f439104442
Signed-off-by: Luca Lai <luca.lai@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88027
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
---
 src/mainboard/google/brya/Kconfig                  |  1 +
 src/mainboard/google/brya/variants/pujjolo/gpio.c  | 12 +++++++-----
 .../google/brya/variants/pujjolo/memory.c          | 14 ++++++++++++++
 3 files changed, 22 insertions(+), 5 deletions(-)

diff --git a/src/mainboard/google/brya/Kconfig b/src/mainboard/google/brya/Kconfig
index 938bbe220e..8051ba989a 100644
--- a/src/mainboard/google/brya/Kconfig
+++ b/src/mainboard/google/brya/Kconfig
@@ -499,6 +499,7 @@ config BOARD_GOOGLE_PUJJOLO
 	select DRIVERS_I2C_SX9324
 	select DRIVERS_GFX_GENERIC
 	select DRIVERS_I2C_SX9324_SUPPORT_LEGACY_LINUX_DRIVER
+	select ENFORCE_MEM_CHANNEL_DISABLE
 	select HAVE_WWAN_POWER_SEQUENCE
 	select SOC_INTEL_COMMON_BLOCK_HDA_VERB
 	select SOC_INTEL_TCSS_USE_PDC_PMC_USBC_MUX_CONFIGURATION
diff --git a/src/mainboard/google/brya/variants/pujjolo/gpio.c b/src/mainboard/google/brya/variants/pujjolo/gpio.c
index 7717efe1ac..96a0ef48f5 100644
--- a/src/mainboard/google/brya/variants/pujjolo/gpio.c
+++ b/src/mainboard/google/brya/variants/pujjolo/gpio.c
@@ -172,8 +172,8 @@ static const struct pad_config override_gpio_table[] = {
 	PAD_CFG_GPO_LOCK(GPP_E7, 1, LOCK_CONFIG),
 	/* E8  : GPP_E8 ==> WLAN_DISABLE_L */
 	PAD_CFG_GPO(GPP_E8, 1, DEEP),
-	/* E9  : NC */
-	PAD_NC_LOCK(GPP_E9, NONE, LOCK_CONFIG),
+	/* E9  : NC ==> DIMM_CHANNEL_SELECT */
+	PAD_CFG_GPI_LOCK(GPP_E9, DN_20K, LOCK_CONFIG),
 	/* E10 : EN_PP3300_WLAN_X */
 	PAD_CFG_GPO(GPP_E10, 0, DEEP),
 	/* E11 : TCHSCR_INT_ODL */
@@ -440,9 +440,11 @@ static const struct pad_config early_gpio_table[] = {
 	 * later on in ramstage. Since reset signal is asserted in bootblock, it results in
 	 * FPMCU not working after a S3 resume. This is a known issue.
 	 */
-	 PAD_CFG_GPO(GPP_E7, 0, DEEP),
-	 /* D2  : ISH_GP2 ==> EN_FP_PWR */
-	 PAD_CFG_GPO(GPP_D2, 1, DEEP),
+	PAD_CFG_GPO(GPP_E7, 0, DEEP),
+	/* D2  : ISH_GP2 ==> EN_FP_PWR */
+	PAD_CFG_GPO(GPP_D2, 1, DEEP),
+	/* E9  : DIMM_CHANNEL_SELECT */
+	PAD_CFG_GPI_LOCK(GPP_E9, DN_20K, LOCK_CONFIG),
 	/* E17 : WWAN_RST_L */
 	PAD_CFG_GPO(GPP_E17, 0, DEEP),
 	/* H4  : I2C0_SDA ==> SOC_I2C_GSC_SDA */
diff --git a/src/mainboard/google/brya/variants/pujjolo/memory.c b/src/mainboard/google/brya/variants/pujjolo/memory.c
index bb80ee15ec..876e96782c 100644
--- a/src/mainboard/google/brya/variants/pujjolo/memory.c
+++ b/src/mainboard/google/brya/variants/pujjolo/memory.c
@@ -109,3 +109,17 @@ void variant_get_spd_info(struct mem_spd *spd_info)
 	spd_info->topo = MEM_TOPO_MEMORY_DOWN;
 	spd_info->cbfs_index = variant_memory_sku();
 }
+
+uint8_t mb_get_channel_disable_mask(void)
+{
+	/*
+	 * GPP_E9 High -> One RAM Chip
+	 * GPP_E9 Low  -> Two RAM Chip
+	 */
+	if (gpio_get(GPP_E9)) {
+		/* Disable all other channels except first two on each controller */
+		printk(BIOS_INFO, "Device only supports one DIMM.\n");
+		return (BIT(2) | BIT(3));
+	}
+	return 0;
+}

From 2c53151c0c6e7366112f0f8d68dffe57cc360ca7 Mon Sep 17 00:00:00 2001
From: Luca Lai <luca.lai@lcfc.corp-partner.google.com>
Date: Fri, 13 Jun 2025 17:43:07 +0800
Subject: [PATCH 1339/3886] mb/trulo/var/pujjolo: Enable Ax211 wifi function

Add Ax211 wifi card setting to let wifi function work.

BUG=b:395763555
BRANCH=none
TEST=Insert Ax211 wifi card to MB and boot to OS to connect wifi
successfully.

Change-Id: I061ca0ad54bef23861ad8c937cece72902afff47
Signed-off-by: Luca Lai <luca.lai@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88092
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
---
 .../google/brya/variants/pujjolo/overridetree.cb      | 11 +++++++++++
 1 file changed, 11 insertions(+)

diff --git a/src/mainboard/google/brya/variants/pujjolo/overridetree.cb b/src/mainboard/google/brya/variants/pujjolo/overridetree.cb
index 7bb97140a6..7e53c3b2e9 100644
--- a/src/mainboard/google/brya/variants/pujjolo/overridetree.cb
+++ b/src/mainboard/google/brya/variants/pujjolo/overridetree.cb
@@ -18,6 +18,9 @@ chip soc/intel/alderlake
 	# S0ix enable
 	register "s0ix_enable" = "true"
 
+	# Enable CNVi BT
+	register "cnvi_bt_core" = "true"
+
 	# Acoustic settings
 	register "acoustic_noise_mitigation" = "1"
 	register "slow_slew_rate[VR_DOMAIN_IA]" = "SLEW_FAST_8"
@@ -616,5 +619,13 @@ chip soc/intel/alderlake
 				device spi 0 on end
 			end # FPMCU
 		end
+		device ref cnvi_wifi on
+			chip drivers/wifi/generic
+				register "wake" = "GPE0_PME_B0"
+				register "enable_cnvi_ddr_rfim" = "true"
+				register "add_acpi_dma_property" = "true"
+				device generic 0 on end
+			end
+		end
 	end
 end

From a7cd5c8c6b49f55e7526f406bd4c0638c7571673 Mon Sep 17 00:00:00 2001
From: Luca Lai <luca.lai@lcfc.corp-partner.google.com>
Date: Thu, 12 Jun 2025 04:33:29 +0800
Subject: [PATCH 1340/3886] mb/trulo/var/pujjolo: Enable USB3 functions

Enable USB3 related functions like usb-a, wwan, wlan.

BUG=b:395763555
BRANCH=none
TEST=Boot to OS and verify output of lsusb contains:
us 004 Device 002: ID 8564:4100 Transcend Information, Inc. USB3.1 Hub
Bus 004 Device 001: ID 1d6b:0003 Linux Foundation 3.0 root hub
Bus 003 Device 003: ID 33f8:01a2 Rolling Wireless S.a.r.l. Rolling RW101R-GL Module
Bus 003 Device 005: ID 093a:2516 Pixart Imaging, Inc. USB OPTICAL MOUSE
Bus 003 Device 004: ID 258a:002a SINO WEALTH Thunderobot KG3089
Bus 003 Device 002: ID 8564:4100 Transcend Information, Inc. USB2.1 Hub
Bus 003 Device 001: ID 1d6b:0002 Linux Foundation 2.0 root hub
Bus 002 Device 001: ID 1d6b:0003 Linux Foundation 3.0 root hub
Bus 001 Device 001: ID 1d6b:0002 Linux Foundation 2.0 root hub


Change-Id: Ia9cb6a394169530eb660023998dd92d8691a1607
Signed-off-by: Luca Lai <luca.lai@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88062
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
---
 .../brya/variants/pujjolo/overridetree.cb     | 22 ++++++++++++++++++-
 1 file changed, 21 insertions(+), 1 deletion(-)

diff --git a/src/mainboard/google/brya/variants/pujjolo/overridetree.cb b/src/mainboard/google/brya/variants/pujjolo/overridetree.cb
index 7e53c3b2e9..ee1e7eeb8b 100644
--- a/src/mainboard/google/brya/variants/pujjolo/overridetree.cb
+++ b/src/mainboard/google/brya/variants/pujjolo/overridetree.cb
@@ -53,6 +53,9 @@ chip soc/intel/alderlake
 	register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)"	# Bluetooth port for PCIe WLAN
 	register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)"	# Bluetooth port for CNVi WLAN
 
+	register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC1)"	# USB3 Type-A port A0(MLB))
+	register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC2)"	# USB3 Type-A port A1(DB)
+
 	#register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)"	# USB3 port for WWAN
 
 	# HD Audio
@@ -586,13 +589,30 @@ chip soc/intel/alderlake
 							"ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D4)"
 						device ref usb2_port10 on end
 					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB3 Type-A Port A0 (MLB)""
+						register "type" = "UPC_TYPE_USB3_A"
+						register "use_custom_pld" = "true"
+						register "custom_pld" = "ACPI_PLD_TYPE_A(RIGHT, LEFT, ACPI_PLD_GROUP(3, 1))"
+						device ref usb3_port1 on end
+					end
 					chip drivers/usb/acpi
 						register "desc" = ""USB3 Type-A Port A1 (DB)""
 						register "type" = "UPC_TYPE_USB3_A"
 						register "use_custom_pld" = "true"
-						register "custom_pld" = "ACPI_PLD_TYPE_A(RIGHT, LEFT, ACPI_PLD_GROUP(4, 1))"
+						register "custom_pld" = "ACPI_PLD_TYPE_A(LEFT, RIGHT, ACPI_PLD_GROUP(4, 1))"
 						device ref usb3_port2 on end
 					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB3 WWAN""
+						register "type" = "UPC_TYPE_INTERNAL"
+						device ref usb3_port3 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB3 WLAN""
+						register "type" = "UPC_TYPE_INTERNAL"
+						device ref usb3_port4 on end
+					end
 				end
 			end
 		end

From fb2c834f7c7e57e336e9aa75b03eb94586226e2f Mon Sep 17 00:00:00 2001
From: Luca Lai <luca.lai@lcfc.corp-partner.google.com>
Date: Mon, 16 Jun 2025 14:50:49 +0800
Subject: [PATCH 1341/3886] mb/trulo/var/pujjolo: Fix p-sensor function

Because the pujjolo motherboard p-sensor could not recognize, so
I modify the below changes.

1. Update P-sensor I2C bus from 2 to 3.
2. Copy P-sensor parameters from pujjocento.

BUG=b:395763555
BRANCH=none
TEST=Build and verify on pujjolo

    Device list:
    cat /sys/bus/iio/devices/iio\:device0/name
    sx9324

    The value of register 01 when away:
    i2cget -f -y 13 0x28 01
    0x00

    The value of register 01 when approaching:
    i2cget -f -y 13 0x28 01
    0x01

Change-Id: Ia5685ad790949001da7ba793759eb286b8cce1e8
Signed-off-by: Luca Lai <luca.lai@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88104
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 .../brya/variants/pujjolo/overridetree.cb     | 70 +++++++++----------
 1 file changed, 32 insertions(+), 38 deletions(-)

diff --git a/src/mainboard/google/brya/variants/pujjolo/overridetree.cb b/src/mainboard/google/brya/variants/pujjolo/overridetree.cb
index ee1e7eeb8b..71ac951e6d 100644
--- a/src/mainboard/google/brya/variants/pujjolo/overridetree.cb
+++ b/src/mainboard/google/brya/variants/pujjolo/overridetree.cb
@@ -76,7 +76,7 @@ chip soc/intel/alderlake
 	#|                   | required to set up a BAR  |
 	#|                   | for TPM communication     |
 	#| I2C1              | Touchscreen               |
-	#| I2C2              | Psensor                   |
+	#| I2C3              | Psensor                   |
 	#| I2C4              | Mipi camera               |
 	#| I2C5              | Trackpad                  |
 	#+-------------------+---------------------------+
@@ -100,11 +100,11 @@ chip soc/intel/alderlake
 				.sda_hold = 7,
 			}
 		},
-		.i2c[2] = {
+		.i2c[3] = {
 			.speed = I2C_SPEED_FAST,
 			.speed_config[0] = {
 				.speed = I2C_SPEED_FAST,
-				.scl_lcnt = 157,
+				.scl_lcnt = 158,
 				.scl_hcnt = 79,
 				.sda_hold = 7,
 			}
@@ -132,8 +132,8 @@ chip soc/intel/alderlake
 	register "serial_io_i2c_mode" = "{
 		[PchSerialIoIndexI2C0] = PchSerialIoPci,
 		[PchSerialIoIndexI2C1] = PchSerialIoPci,
-		[PchSerialIoIndexI2C2] = PchSerialIoPci,
-		[PchSerialIoIndexI2C3] = PchSerialIoDisabled,
+		[PchSerialIoIndexI2C2] = PchSerialIoDisabled,
+		[PchSerialIoIndexI2C3] = PchSerialIoPci,
 		[PchSerialIoIndexI2C4] = PchSerialIoPci,
 		[PchSerialIoIndexI2C5] = PchSerialIoPci,
 	}"
@@ -234,39 +234,38 @@ chip soc/intel/alderlake
 				device generic 0 on end
 			end
 		end
-		device ref i2c2 on
+		device ref i2c3 on
 			chip drivers/i2c/sx9324
 				register "desc" = ""SAR Proximity Sensor""
 				register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_H19_IRQ)"
 				register "speed" = "I2C_SPEED_FAST"
 				register "uid" = "1"
+				register "reg_irq_cfg0" = "0x00"
+				register "reg_irq_cfg1" = "0x80"
+				register "reg_irq_cfg2" = "0x00"
 				register "reg_gnrl_ctrl0" = "0x16"
-				register "reg_gnrl_ctrl1" = "0x21"
-				register "reg_afe_ctrl0" = "0x00"
+				register "reg_gnrl_ctrl1" = "0x25"
+				register "reg_afe_ctrl0" = "0x20"
 				register "reg_afe_ctrl1" = "0x10"
 				register "reg_afe_ctrl2" = "0x00"
 				register "reg_afe_ctrl3" = "0x00"
-				register "reg_afe_ctrl4" = "0x47"
+				register "reg_afe_ctrl4" = "0x86"
 				register "reg_afe_ctrl5" = "0x00"
 				register "reg_afe_ctrl6" = "0x00"
-				register "reg_afe_ctrl7" = "0x47"
+				register "reg_afe_ctrl7" = "0x86"
 				register "reg_afe_ctrl8" = "0x12"
-				register "reg_afe_ctrl9" = "0x08"
-				register "reg_afe_ph0" = "0x3d"
-				register "reg_afe_ph1" = "0x1b"
-				register "reg_afe_ph2" = "0x1f"
-				register "reg_afe_ph3" = "0x3d"
-				register "reg_prox_ctrl0" = "0x0b"
-				register "reg_prox_ctrl1" = "0x0a"
-				register "reg_prox_ctrl2" = "0x90"
+				register "reg_afe_ctrl9" = "0x0F"
+				register "reg_prox_ctrl0" = "0x09"
+				register "reg_prox_ctrl1" = "0x09"
+				register "reg_prox_ctrl2" = "0x20"
 				register "reg_prox_ctrl3" = "0x60"
 				register "reg_prox_ctrl4" = "0x0c"
 				register "reg_prox_ctrl5" = "0x00"
-				register "reg_prox_ctrl6" = "0x19"
-				register "reg_prox_ctrl7" = "0x58"
+				register "reg_prox_ctrl6" = "0x2C"
+				register "reg_prox_ctrl7" = "0xFF"
 				register "reg_adv_ctrl0" = "0x00"
 				register "reg_adv_ctrl1" = "0x00"
-				register "reg_adv_ctrl2" = "0x00"
+				register "reg_adv_ctrl2" = "0x04"
 				register "reg_adv_ctrl3" = "0x00"
 				register "reg_adv_ctrl4" = "0x00"
 				register "reg_adv_ctrl5" = "0x05"
@@ -277,29 +276,24 @@ chip soc/intel/alderlake
 				register "reg_adv_ctrl10" = "0x00"
 				register "reg_adv_ctrl11" = "0x00"
 				register "reg_adv_ctrl12" = "0x00"
-				register "reg_adv_ctrl13" = "0x00"
-				register "reg_adv_ctrl14" = "0x80"
-				register "reg_adv_ctrl15" = "0x0c"
-				register "reg_adv_ctrl16" = "0x08"
-				register "reg_adv_ctrl17" = "0x56"
-				register "reg_adv_ctrl18" = "0x33"
-				register "reg_adv_ctrl19" = "0x00"
-				register "reg_adv_ctrl20" = "0x00"
+				register "reg_adv_ctrl16" = "0x00"
+				register "reg_adv_ctrl17" = "0x00"
+				register "reg_adv_ctrl18" = "0x00"
 
-				register "ph0_pin" = "{1, 3, 3}"
-				register "ph1_pin" = "{3, 2, 1}"
+				register "ph0_pin" = "{3, 1, 3}"
+				register "ph1_pin" = "{1, 3, 3}"
 				register "ph2_pin" = "{3, 3, 1}"
-				register "ph3_pin" = "{1, 3, 3}"
-				register "ph01_resolution" = "1024"
-				register "ph23_resolution" = "1024"
+				register "ph3_pin" = "{3, 3, 3}"
+				register "ph01_resolution" = "512"
+				register "ph23_resolution" = "512"
 				register "startup_sensor" = "1"
-				register "ph01_proxraw_strength" = "3"
-				register "ph23_proxraw_strength" = "2"
+				register "ph01_proxraw_strength" = "1"
+				register "ph23_proxraw_strength" = "1"
 				register "avg_pos_strength" = "256"
-				register "cs_idle_sleep" = ""hi-z""
+				register "cs_idle_sleep" = ""gnd""
 				register "int_comp_resistor" = ""lowest""
 				register "input_precharge_resistor_ohms" = "4000"
-				register "input_analog_gain" = "1"
+				register "input_analog_gain" = "3"
 				device i2c 28 on end
 			end
 		end

From bcd569faf1bf7f1fa992e13e4169c5fe31df61bb Mon Sep 17 00:00:00 2001
From: David Wu <david_wu@quanta.corp-partner.google.com>
Date: Mon, 16 Jun 2025 17:33:03 +0800
Subject: [PATCH 1342/3886] mb/google/skywalker: Create variant Baze

Create the variant Baze.

BUG=b:425277682
TEST=emerge-skywalker coreboot
BRANCH=None

Change-Id: Idc37e980d66d7e12ae7a1df9c1806b5f09f0c5fe
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88108
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
---
 src/mainboard/google/skywalker/Kconfig      | 2 ++
 src/mainboard/google/skywalker/Kconfig.name | 3 +++
 2 files changed, 5 insertions(+)

diff --git a/src/mainboard/google/skywalker/Kconfig b/src/mainboard/google/skywalker/Kconfig
index 49b3d21718..a868258643 100644
--- a/src/mainboard/google/skywalker/Kconfig
+++ b/src/mainboard/google/skywalker/Kconfig
@@ -3,6 +3,7 @@
 # Umbrella option to be selected by variant boards.
 config BOARD_GOOGLE_SKYWALKER_COMMON
 	def_bool BOARD_GOOGLE_ANAKIN || \
+		 BOARD_GOOGLE_BAZE || \
 		 BOARD_GOOGLE_OBIWAN || \
 		 BOARD_GOOGLE_SKYWALKER || \
 		 BOARD_GOOGLE_YODA
@@ -44,6 +45,7 @@ config MAINBOARD_DIR
 config MAINBOARD_PART_NUMBER
 	string
 	default "Anakin" if BOARD_GOOGLE_ANAKIN
+	default "Baze" if BOARD_GOOGLE_BAZE
 	default "Obiwan" if BOARD_GOOGLE_OBIWAN
 	default "Skywalker" if BOARD_GOOGLE_SKYWALKER
 	default "Yoda" if BOARD_GOOGLE_YODA
diff --git a/src/mainboard/google/skywalker/Kconfig.name b/src/mainboard/google/skywalker/Kconfig.name
index a7c8eb3088..d79033d744 100644
--- a/src/mainboard/google/skywalker/Kconfig.name
+++ b/src/mainboard/google/skywalker/Kconfig.name
@@ -5,6 +5,9 @@ comment "Skywalker"
 config BOARD_GOOGLE_ANAKIN
 	bool "->  Anakin"
 
+config BOARD_GOOGLE_BAZE
+	bool "->  Baze"
+
 config BOARD_GOOGLE_OBIWAN
 	bool "->  Obiwan"
 

From 7c0da94aebfe5d5f1af622ecc3daa9e43da4d91c Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Fri, 13 Jun 2025 09:57:56 -0500
Subject: [PATCH 1343/3886] mb/google/brya/var/pujjoga: Add and select VBT

Vbt extracted from coreboot-Google_Pujjoga.15217.834.0.bin.
Pujjoga/Pujjogatwin both use same variant dir/same VBT.

TEST=build/boot pujjoga

Change-Id: Ie2054f53563372e9ce7e6692513340a53c35b565
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88094
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/google/brya/Kconfig                |   2 ++
 .../google/brya/variants/pujjoga/data.vbt        | Bin 0 -> 9216 bytes
 2 files changed, 2 insertions(+)
 create mode 100644 src/mainboard/google/brya/variants/pujjoga/data.vbt

diff --git a/src/mainboard/google/brya/Kconfig b/src/mainboard/google/brya/Kconfig
index 8051ba989a..0acb11c8ef 100644
--- a/src/mainboard/google/brya/Kconfig
+++ b/src/mainboard/google/brya/Kconfig
@@ -481,6 +481,7 @@ config BOARD_GOOGLE_PUJJOGA
 	select DRIVERS_I2C_SX9324
 	select DRIVERS_I2C_SX9324_SUPPORT_LEGACY_LINUX_DRIVER
 	select HAVE_WWAN_POWER_SEQUENCE
+	select INTEL_GMA_HAVE_VBT
 
 config BOARD_GOOGLE_PUJJOGATWIN
 	select BOARD_GOOGLE_BASEBOARD_NISSA
@@ -489,6 +490,7 @@ config BOARD_GOOGLE_PUJJOGATWIN
 	select DRIVERS_I2C_SX9324
 	select DRIVERS_I2C_SX9324_SUPPORT_LEGACY_LINUX_DRIVER
 	select HAVE_WWAN_POWER_SEQUENCE
+	select INTEL_GMA_HAVE_VBT
 	select SOC_INTEL_TWINLAKE
 
 config BOARD_GOOGLE_PUJJOLO
diff --git a/src/mainboard/google/brya/variants/pujjoga/data.vbt b/src/mainboard/google/brya/variants/pujjoga/data.vbt
new file mode 100644
index 0000000000000000000000000000000000000000..6a480b63e598f31edd5069b920a63450c4476ce7
GIT binary patch
literal 9216
zcmeHMT}&KR6h3!mciFCsYz5mbQoKMz0SgREi<FQs%b(qrpJkzBo0_ntyILYGNU2g|
z(lPQtVoWA6QQDZenwS`TkQblbCxht=sfqDH6W(kZUrhRD>-yb0!{X8+tF>C{p3RxP
zbI+OYp7Y&1_uiQ~Fxol7gMHmSk-p%Gp87C{#7QHyGJ@m1(is{Y9_tQ{1jjo22D?u1
zUuh5BsQB#`QJk@T-X=|J3SF2@Ox8qddH>Y-#AKqeJ8|)q*{NwB?h5hX*|Uks#LSu5
zM4S(gz7XUBuh7$ZX<{<Y2QHl-Pt3G&fN1dMO@|wr4|5)PzENv#3}{V9U}<Y=X*+VX
z(9_-1HP{~x^#w;lg9Cgp!n;Gm!QtVa{?5KrJRBK37U~R*^mG?`vQp@pn!Y?U@$$J@
zUei^}18ApS;>wVD*VN2(0}oD4@`&)c$Rml1iJ8|D@rFW=07{YD!HAfLic*Avkh`7a
zBR4sqI+R1jxdLTSVo)-m4yX?0P#;u*N(>y7cbEeEK{vVlsLlx5RB@8Rg*;QqC0ynd
zg#zm&1zet~=V<XpjC{UiRfT9zwk8^d8{@KNSqtp1&%up4Y`4PoMq{>{<;!ii)3#fY
zl~RhPv)p7;KzrSG+fC$@jT%{QA`sE&d$wCKkxROnS#GjvxP4)}iK`%+8<j-D?fPan
zve5*KIm?|l;A#`ZhzTKjn(6ldTvu1_sXOiTPy#vyy$pRD`Y!YX=*Q5{p<hD3f_?-2
z7WyOfC+IKGU2#Ava&$bb;}XPkoicYuI=!C7PAz$h={SbF>TaJeBcq_zagr$gQOOdy
z%IwtI*HgUD|07|0ra@gT@X%_(ZMIPSXqN6n-4<0CNA~@*g+snN&%gsRP*X{Y+MER<
zCN?1(m35;|Ls?_S?kDA<=AQB54vQ*Y`G1@F@b4@-Na^%<y9|@B?f1E3mDbheEmtu2
zi?WxiQDu9CWD%#PXc@0DN-_x63{GA#H*Jp)-$#0osx|*Yi-q8CxuVJq01%wy5D4v9
z$+pfytE0ss(sXSa>!}cAfeS^+JLfFT31N;8mHKqw9}t)+R`6UAK5Lv?8!D~Vql+6c
zFjFk<<kelvImB?RL)XTa1G=8tKyX=`9Pg+z7bah-7+o5oa;?|2`$8~jik%oClw5dt
zv%yTpO3QVP+kF8h9p)~Xg;9`87B%fga(cN62zBBrt1nEs=z5dR`5eZ>wc6zB(0rv9
zzPdMqpwbhf3?_3y(CYM+*nC{`56LkgV^A@e1j64Oli)!mY!L;5ljo4dtx`&c`CiSd
zb&0F27);!cKoCpy_V<O-X82!it=FUV8-1Y?_MajKY?-&eFKTs)8B`qe`LG=oBD0WN
zRc~K!cr1M8LSk~@%=yG)aAGC+aF6Nqb4|>3e1%-mrH6M+ZxTgOo`PmXY+D~h#hmmY
z>fR*Vaeioke(r@+2wU%y6s9;GV(-&U70Zt$NJq+^O(N>=2i~ADTFA)GC|Y@}r}MA>
zH_Iv93gU1J7E=?mfSeFF5u8qUNY=&FE23PrAF{<nT6E>vjuLdD=*+F8y`9{FiR#`K
zMpY9R0(ejyt7)eI+~wmW{_`zwaF=KMpC4hjne|&J{_CZUp2;q`q_p0!b^zJ79e#E+
z;&I8n)eg@iAAX*JJOg<K@(kn|$TN^<AkV;m$UxgCN*TR4PGl%1URA|tjqSI;?uoCM
zMEZwBTqRaR21Vh^thcq&cJnSA96IyU0^VL%<4v$jreff@_9@;?I~SQo)9}%79iC+&
zDX6f`IXUyeR_gF&*~}k=ZH+}~5w_|q+v=P`x=T}Zpe#EAS++a<j7FVHtd~s0QVyH-
zM$tff->)(<T}jf21G796X9_m+l!6a(mTlQlh1{*rj>6_hGD<pES(vWUyjlrN>ls_v
zL=L)Zh5R%GTU>ZUt^Bs)B?bF|LcvQCkMxK}-HWR>cq!=?vG|dDJ+(UOv*Nt=7QRTk
d@wps7aup*M`R-rx`Dgw2IM_g2UjDBP{0>>=cM1Ri

literal 0
HcmV?d00001


From 57b12d2171a753f923abc9ca0817ad17cd6b6c2f Mon Sep 17 00:00:00 2001
From: Shon Wang <shon.wang@quanta.corp-partner.google.com>
Date: Wed, 28 May 2025 16:11:51 +0800
Subject: [PATCH 1344/3886] spd/lp4x: Generate initial SPD for B3221XM3BDGVI

Generate initial SPD for Kingston B3221XM3BDGVI

BUG=b:420797833
BRANCH=firmware-brya-14505.B
TEST=util/spd_tools/bin/spd_gen spd/lp4x/memory_parts.json lp4x

Change-Id: Id411ace4a6d535fcbe5be5317e0ec7fd0052b82f
Signed-off-by: Shon Wang <shon.wang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87881
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Jayvik Desai <jayvik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 spd/lp4x/memory_parts.json                    | 12 +++++++
 .../set-0/parts_spd_manifest.generated.txt    |  1 +
 spd/lp4x/set-0/spd-10.hex                     | 32 +++++++++++++++++++
 .../set-1/parts_spd_manifest.generated.txt    |  1 +
 spd/lp4x/set-1/spd-13.hex                     | 32 +++++++++++++++++++
 5 files changed, 78 insertions(+)
 create mode 100644 spd/lp4x/set-0/spd-10.hex
 create mode 100644 spd/lp4x/set-1/spd-13.hex

diff --git a/spd/lp4x/memory_parts.json b/spd/lp4x/memory_parts.json
index 9c90229311..fc3fd83c1e 100644
--- a/spd/lp4x/memory_parts.json
+++ b/spd/lp4x/memory_parts.json
@@ -437,6 +437,18 @@
                 "tckMaxPs": 468,
                 "casLatencies": "6 10 14 20 24 28 32 36"
             }
+	},
+        {
+            "name": "B3221XM3BDGVI",
+            "attribs": {
+                "densityPerChannelGb": 16,
+                "banks": 8,
+                "channelsPerDie": 1,
+                "diesPerPackage": 2,
+                "bitWidthPerChannel": 16,
+                "ranksPerChannel": 1,
+                "speedMbps": 4267
+            }
         }
 
     ]
diff --git a/spd/lp4x/set-0/parts_spd_manifest.generated.txt b/spd/lp4x/set-0/parts_spd_manifest.generated.txt
index e7ea7cf3af..e60c68e5e7 100644
--- a/spd/lp4x/set-0/parts_spd_manifest.generated.txt
+++ b/spd/lp4x/set-0/parts_spd_manifest.generated.txt
@@ -37,3 +37,4 @@ CXDB4CBAM-ML-A,spd-8.hex
 SDVB8D8A34XGCL3N3T,spd-1.hex
 NT6AP512T32BL-J1,spd-8.hex
 NT6AP1024F32BL-J1,spd-9.hex
+B3221XM3BDGVI,spd-10.hex
diff --git a/spd/lp4x/set-0/spd-10.hex b/spd/lp4x/set-0/spd-10.hex
new file mode 100644
index 0000000000..22aa6e43f3
--- /dev/null
+++ b/spd/lp4x/set-0/spd-10.hex
@@ -0,0 +1,32 @@
+23 11 11 0E 16 29 00 08 00 00 00 00 02 01 00 00
+00 00 04 FF 92 54 05 00 87 00 90 A8 90 E0 0B F0
+05 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 E5 00 E0 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 20 20 20 20 20 20 20
+20 20 20 20 20 20 20 20 20 20 20 20 20 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
diff --git a/spd/lp4x/set-1/parts_spd_manifest.generated.txt b/spd/lp4x/set-1/parts_spd_manifest.generated.txt
index 85d892e237..0844ba9f58 100644
--- a/spd/lp4x/set-1/parts_spd_manifest.generated.txt
+++ b/spd/lp4x/set-1/parts_spd_manifest.generated.txt
@@ -37,3 +37,4 @@ CXDB4CBAM-ML-A,spd-11.hex
 SDVB8D8A34XGCL3N3T,spd-5.hex
 NT6AP512T32BL-J1,spd-11.hex
 NT6AP1024F32BL-J1,spd-12.hex
+B3221XM3BDGVI,spd-13.hex
diff --git a/spd/lp4x/set-1/spd-13.hex b/spd/lp4x/set-1/spd-13.hex
new file mode 100644
index 0000000000..d5ccb1bd3b
--- /dev/null
+++ b/spd/lp4x/set-1/spd-13.hex
@@ -0,0 +1,32 @@
+23 11 11 0E 16 29 90 08 00 00 00 00 02 22 00 00
+00 00 04 FF 92 54 05 00 87 00 90 A8 90 E0 0B F0
+05 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 E5 00 E0 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 20 20 20 20 20 20 20
+20 20 20 20 20 20 20 20 20 20 20 20 20 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00

From 620c8d9f712b389f94993a24b2b7d013011bb883 Mon Sep 17 00:00:00 2001
From: Shon Wang <shon.wang@quanta.corp-partner.google.com>
Date: Wed, 28 May 2025 16:28:36 +0800
Subject: [PATCH 1345/3886] mb/google/brask/var/constitution: Generate RAM ID
 for B3221XM3BDGVI

Generate RAM ID for Kingston B3221XM3BDGVI

DRAM Part Name                 ID to assign
B3221XM3BDGVI                  2 (0010)

BUG=b:420797833
BRANCH=firmware-brya-14505.B
TEST=emerge-constitution coreboot

Change-Id: Ic4f92cb7d597a877b693906dee23e1b277fcf122
Signed-off-by: Shon Wang <shon.wang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87883
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com>
---
 .../google/brya/variants/constitution/memory/Makefile.mk         | 1 +
 .../brya/variants/constitution/memory/dram_id.generated.txt      | 1 +
 .../google/brya/variants/constitution/memory/mem_parts_used.txt  | 1 +
 3 files changed, 3 insertions(+)

diff --git a/src/mainboard/google/brya/variants/constitution/memory/Makefile.mk b/src/mainboard/google/brya/variants/constitution/memory/Makefile.mk
index a6a5ab7b39..da2ad15bbc 100644
--- a/src/mainboard/google/brya/variants/constitution/memory/Makefile.mk
+++ b/src/mainboard/google/brya/variants/constitution/memory/Makefile.mk
@@ -6,3 +6,4 @@
 SPD_SOURCES =
 SPD_SOURCES += spd/lp4x/set-0/spd-1.hex      # ID = 0(0b0000)  Parts = K4U6E3S4AB-MGCL
 SPD_SOURCES += spd/lp4x/set-0/spd-3.hex      # ID = 1(0b0001)  Parts = MT53E1G32D2NP-046 WT:B, K4UBE3D4AB-MGCL, H54G56CYRBX247
+SPD_SOURCES += spd/lp4x/set-0/spd-10.hex      # ID = 2(0b0010)  Parts = B3221XM3BDGVI
diff --git a/src/mainboard/google/brya/variants/constitution/memory/dram_id.generated.txt b/src/mainboard/google/brya/variants/constitution/memory/dram_id.generated.txt
index 9013dd8383..f7b781c8cb 100644
--- a/src/mainboard/google/brya/variants/constitution/memory/dram_id.generated.txt
+++ b/src/mainboard/google/brya/variants/constitution/memory/dram_id.generated.txt
@@ -8,3 +8,4 @@ K4U6E3S4AB-MGCL                0 (0000)
 MT53E1G32D2NP-046 WT:B         1 (0001)
 K4UBE3D4AB-MGCL                1 (0001)
 H54G56CYRBX247                 1 (0001)
+B3221XM3BDGVI                  2 (0010)
diff --git a/src/mainboard/google/brya/variants/constitution/memory/mem_parts_used.txt b/src/mainboard/google/brya/variants/constitution/memory/mem_parts_used.txt
index ee55088daa..2fc4149f79 100644
--- a/src/mainboard/google/brya/variants/constitution/memory/mem_parts_used.txt
+++ b/src/mainboard/google/brya/variants/constitution/memory/mem_parts_used.txt
@@ -2,3 +2,4 @@ K4U6E3S4AB-MGCL
 MT53E1G32D2NP-046 WT:B
 K4UBE3D4AB-MGCL
 H54G56CYRBX247
+B3221XM3BDGVI

From 89e4fff2d35dd8a2f9b6c021f309b49d883fb3b6 Mon Sep 17 00:00:00 2001
From: Elyes Haouas <ehaouas@noos.fr>
Date: Wed, 23 Apr 2025 19:15:24 +0200
Subject: [PATCH 1346/3886] crossgcc/buildgcc: introduce RISCV_ISA_SPEC for
 RISC-V ISA specification
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Add RISCV_ISA_SPEC variable and replace hardcoded “20191213”.

Change-Id: I35c01a01998066dcafbd262cebd2f0c544983fa2
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87433
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
---
 util/crossgcc/buildgcc | 7 +++++--
 1 file changed, 5 insertions(+), 2 deletions(-)

diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc
index 57aeb96ab5..0e29fbfa10 100755
--- a/util/crossgcc/buildgcc
+++ b/util/crossgcc/buildgcc
@@ -47,6 +47,9 @@ CLANG_VERSION=18.1.8
 CMAKE_VERSION=3.31.3
 NASM_VERSION=2.16.03
 
+# Architecture-specific options
+RISCV_ISA_SPEC=20191213
+
 # Filename for each package
 GMP_ARCHIVE="gmp-${GMP_VERSION}.tar.xz"
 MPFR_ARCHIVE="mpfr-${MPFR_VERSION}.tar.xz"
@@ -1042,8 +1045,8 @@ case "$TARGETARCH" in
 	i386-mingw32)		;;
 	riscv-elf | riscv64-elf)
 				TARGETARCH=riscv64-elf
-				TARGET_GCC_OPTIONS="$TARGET_GCC_OPTIONS --with-isa-spec=20191213"
-				TARGET_BINUTILS_OPTIONS="$TARGET_BINUTILS_OPTIONS --with-isa-spec=20191213";;
+				TARGET_GCC_OPTIONS="$TARGET_GCC_OPTIONS --with-isa-spec=${RISCV_ISA_SPEC}"
+				TARGET_BINUTILS_OPTIONS="$TARGET_BINUTILS_OPTIONS --with-isa-spec=${RISCV_ISA_SPEC}";;
 	powerpc64*-linux*)	;;
 	i386*)			TARGETARCH=i386-elf;;
 	arm*)			TARGETARCH=arm-eabi;;

From 7c19b1fa58ed887487d60ad45459decdefb83883 Mon Sep 17 00:00:00 2001
From: Vince Liu <vince-wl.liu@mediatek.corp-partner.google.com>
Date: Wed, 18 Jun 2025 19:03:47 +0800
Subject: [PATCH 1347/3886] mb/google/skywalker: Run MTK FSP binary in ramstage

Load and run mtk_fsp_ramstage.elf in ramstage.

BUG=b:379008996
BRANCH=none
TEST=See coreboot log:
[INFO ]  CBFS: Found 'fallback/mtk_fsp_ramstage' @0x5e8c0 size 0x359
in mcache @0xfffdd298
[INFO ]  _start: MediaTek FSP_RAMSTAGE interface version: 1.0
[INFO ]  [mtk-fsp] RAMSTAGE_SOC_INIT
[INFO ]  _start: status 0
[INFO ]  mtk_fsp_load_and_run: run fallback/mtk_fsp_ramstage at phase
0x50 done

Signed-off-by: Vince Liu <vince-wl.liu@mediatek.corp-partner.google.com>
Change-Id: I1ed5dbeea8fbf08730c5ecc5720b6e1f7677296c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88124
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/soc/mediatek/mt8189/soc.c | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/src/soc/mediatek/mt8189/soc.c b/src/soc/mediatek/mt8189/soc.c
index 697f4ddcf1..5ee602f1dc 100644
--- a/src/soc/mediatek/mt8189/soc.c
+++ b/src/soc/mediatek/mt8189/soc.c
@@ -5,6 +5,7 @@
 #include <soc/dramc_info.h>
 #include <soc/emi.h>
 #include <soc/mcupm.h>
+#include <soc/mtk_fsp.h>
 #include <soc/sspm.h>
 #include <symbols.h>
 
@@ -20,6 +21,9 @@ static void soc_read_resources(struct device *dev)
 
 static void soc_init(struct device *dev)
 {
+	mtk_fsp_init(RAMSTAGE_SOC_INIT);
+	mtk_fsp_load_and_run();
+
 	mcupm_init();
 	sspm_init();
 }

From 812379f5007346d440ce86926e1e610231eabcff Mon Sep 17 00:00:00 2001
From: Crystal Guo <crystal.guo@mediatek.corp-partner.google.com>
Date: Mon, 16 Jun 2025 14:00:30 +0800
Subject: [PATCH 1348/3886] soc/mediatek/common: Move map_to_lpddr_dram_type()
 to common for reuse

Relocate map_to_lpddr_dram_type() to the common directory to enable
sharing across MT8189, MT8196, and other SoCs with the same
DRAM_DRAM_TYPE_T values.

BUG=b:417001336
BRANCH=none
TEST=Check boot log
LPDDR5 chan0(x16) rank0: density 16384mbits x16, MF ff rev 0800
LPDDR5 chan0(x16) rank1: density 16384mbits x16, MF ff rev 0800
LPDDR5 chan1(x16) rank0: density 16384mbits x16, MF ff rev 0800
LPDDR5 chan1(x16) rank1: density 16384mbits x16, MF ff rev 0800

Signed-off-by: Crystal Guo <crystal.guo@mediatek.corp-partner.google.com>
Change-Id: I53d70aa26991f89ef05e56f8b7d972f8208d2484
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88123
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
---
 src/soc/mediatek/{mt8196/memory.c => common/memory_type.c} | 0
 src/soc/mediatek/mt8189/Makefile.mk                        | 2 +-
 src/soc/mediatek/mt8196/Makefile.mk                        | 2 +-
 3 files changed, 2 insertions(+), 2 deletions(-)
 rename src/soc/mediatek/{mt8196/memory.c => common/memory_type.c} (100%)

diff --git a/src/soc/mediatek/mt8196/memory.c b/src/soc/mediatek/common/memory_type.c
similarity index 100%
rename from src/soc/mediatek/mt8196/memory.c
rename to src/soc/mediatek/common/memory_type.c
diff --git a/src/soc/mediatek/mt8189/Makefile.mk b/src/soc/mediatek/mt8189/Makefile.mk
index 1014d1959c..eb1ce41b48 100644
--- a/src/soc/mediatek/mt8189/Makefile.mk
+++ b/src/soc/mediatek/mt8189/Makefile.mk
@@ -22,7 +22,7 @@ romstage-y += ../common/dram_init.c
 romstage-y += ../common/dramc_param.c
 romstage-y += dvfs.c
 romstage-y += ../common/emi.c
-romstage-y += ../common/memory.c ../common/memory_test.c
+romstage-y += ../common/memory.c ../common/memory_test.c ../common/memory_type.c
 romstage-y += ../common/mmu_operations.c ../common/mmu_cmops.c
 romstage-y += ../common/mt6315.c mt6315.c
 romstage-y += ../common/mt6359p.c mt6359p.c
diff --git a/src/soc/mediatek/mt8196/Makefile.mk b/src/soc/mediatek/mt8196/Makefile.mk
index 9cf46ac809..2e47a0e970 100644
--- a/src/soc/mediatek/mt8196/Makefile.mk
+++ b/src/soc/mediatek/mt8196/Makefile.mk
@@ -36,7 +36,7 @@ romstage-y += ../common/emi.c
 romstage-y += irq2axi.c
 romstage-y += l2c_ops.c
 romstage-y += modem_power_ctrl.c
-romstage-y += ../common/memory.c memory.c
+romstage-y += ../common/memory.c ../common/memory_type.c
 romstage-y += ../common/memory_test.c
 romstage-y += ../common/mmu_operations.c ../common/mmu_cmops.c
 romstage-y += ../common/mt6316.c mt6316.c

From e2ac46bcc77029622a0ff3e5cf6b2fc15b60b9c3 Mon Sep 17 00:00:00 2001
From: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Date: Tue, 17 Jun 2025 14:45:04 +0800
Subject: [PATCH 1349/3886] spd/lp5: Add SPD for hynix H58G66CK8BX147

Add H58G66CK8BX147 in the memory_parts.json and re-generate the SPD.

BUG=b:425545256
TEST=util/spd_tools/bin/spd_gen spd/lp5/memory_parts.json lp5

Change-Id: Iab55914d5cc2b188a122d4a1ee4468d0aa759938
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88120
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 spd/lp5/memory_parts.json                      | 11 +++++++++++
 spd/lp5/set-0/parts_spd_manifest.generated.txt |  1 +
 spd/lp5/set-1/parts_spd_manifest.generated.txt |  1 +
 3 files changed, 13 insertions(+)

diff --git a/spd/lp5/memory_parts.json b/spd/lp5/memory_parts.json
index e13ffec930..3f2d32e055 100644
--- a/spd/lp5/memory_parts.json
+++ b/spd/lp5/memory_parts.json
@@ -306,6 +306,17 @@
                 "speedMbps": 8533,
                 "lp5x": true
             }
+        },
+        {
+            "name":  "H58G66CK8BX147",
+            "attribs": {
+                "densityPerDieGb": 16,
+                "diesPerPackage": 4,
+                "bitWidthPerChannel": 16,
+                "ranksPerChannel": 2,
+                "speedMbps": 8533,
+                "lp5x": true
+            }
         }
     ]
 }
diff --git a/spd/lp5/set-0/parts_spd_manifest.generated.txt b/spd/lp5/set-0/parts_spd_manifest.generated.txt
index f28554c4e9..2a550bfa6a 100644
--- a/spd/lp5/set-0/parts_spd_manifest.generated.txt
+++ b/spd/lp5/set-0/parts_spd_manifest.generated.txt
@@ -30,3 +30,4 @@ MT62F2G32D4DS-020 WT:F,spd-10.hex
 H58G56CK8BX146,spd-11.hex
 K3KL8L80EM-MGCU,spd-11.hex
 K3KL9L90EM-MGCU,spd-10.hex
+H58G66CK8BX147,spd-10.hex
diff --git a/spd/lp5/set-1/parts_spd_manifest.generated.txt b/spd/lp5/set-1/parts_spd_manifest.generated.txt
index f28554c4e9..2a550bfa6a 100644
--- a/spd/lp5/set-1/parts_spd_manifest.generated.txt
+++ b/spd/lp5/set-1/parts_spd_manifest.generated.txt
@@ -30,3 +30,4 @@ MT62F2G32D4DS-020 WT:F,spd-10.hex
 H58G56CK8BX146,spd-11.hex
 K3KL8L80EM-MGCU,spd-11.hex
 K3KL9L90EM-MGCU,spd-10.hex
+H58G66CK8BX147,spd-10.hex

From c8eb52c10c82893a928f1470ad7cb6ff37d89c30 Mon Sep 17 00:00:00 2001
From: Elmo Lan <elmo_lan@realtek.corp-partner.google.com>
Date: Tue, 17 Jun 2025 17:15:42 +0800
Subject: [PATCH 1350/3886] ec/google/chromeec: Modify Realtek EC
 initialization timing

The host must initialize necessary settings before
accessing the Realtek EC via EMI.

BUG=b:414474440
TEST=FW_NAME=brox_rtk_ec emerge-brox coreboot chromeos-bootimage
     flash to brox board with realtek rts5915
     Boot normally and got those message from ap console:

[DEBUG]	Google Chrome EC uptime: 107.108 seconds
[DEBUG]	Google Chrome AP resets since EC boot: 2
[DEBUG]	Google Chrome most recent AP reset causes:
[DEBUG]		10.479: 32775 shutdown: entering G3
[DEBUG]		92.102: 8 reset: during EC initialization
[DEBUG]	Google Chrome EC reset flags at last EC boot: watchdog | sysjump
[DEBUG]	PNP: 0c09.0 init finished in 81 msecs

Change-Id: I85ad210ccd40097dff552f7e72fe712e33cfd95f
Signed-off-by: Elmo Lan <elmo_lan@realtek.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88127
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Reviewed-by: Jayvik Desai <jayvik@google.com>
---
 src/ec/google/chromeec/ec.h     |  5 --
 src/ec/google/chromeec/ec_lpc.c |  3 --
 src/ec/google/chromeec/rtk.c    | 84 ++++++++++++++++++---------------
 3 files changed, 47 insertions(+), 45 deletions(-)

diff --git a/src/ec/google/chromeec/ec.h b/src/ec/google/chromeec/ec.h
index 957adb4089..4b8d0958c3 100644
--- a/src/ec/google/chromeec/ec.h
+++ b/src/ec/google/chromeec/ec.h
@@ -486,11 +486,6 @@ const char *google_chromeec_acpi_name(const struct device *dev);
 
 #endif /* HAVE_ACPI_TABLES */
 
-/**
- * Initialize the EC.
- */
-void chipset_init(void);
-
 /**
  * Read bytes from the EMI.
  *
diff --git a/src/ec/google/chromeec/ec_lpc.c b/src/ec/google/chromeec/ec_lpc.c
index 19139ccc07..f16d528833 100644
--- a/src/ec/google/chromeec/ec_lpc.c
+++ b/src/ec/google/chromeec/ec_lpc.c
@@ -446,14 +446,11 @@ int google_chromeec_command(struct chromeec_command *cec_command)
 	return result;
 }
 
-void __weak chipset_init(void) {}
-
 static void lpc_ec_init(struct device *dev)
 {
 	if (!dev->enabled)
 		return;
 
-	chipset_init();
 	google_chromeec_init();
 }
 
diff --git a/src/ec/google/chromeec/rtk.c b/src/ec/google/chromeec/rtk.c
index 6779d422f2..96ffbe5364 100644
--- a/src/ec/google/chromeec/rtk.c
+++ b/src/ec/google/chromeec/rtk.c
@@ -23,42 +23,7 @@
 #define EMI_ADDR1 0xf2 /* The EMI base address 15-8*/
 #define EMI_CTRL  0x30
 
-bool chipset_emi_read_bytes(u16 port, size_t length, u8 *dest, u8 *csum)
-{
-	size_t i;
-
-	printk(BIOS_DEBUG, "RTS5915: read port 0x%x, size %ld\n", port, length);
-
-	if (port >= EMI_RANGE_START && port <= EMI_RANGE_END) {
-		uint8_t *p = (uint8_t *)(HOSTCMD_PARAM_MEM_BASE + (port - EMI_RANGE_START));
-		for (i = 0; i < length; ++i) {
-			dest[i] = p[i];
-			if (csum)
-				*csum += dest[i];
-		}
-		return true;
-	}
-	return false;
-}
-
-bool chipset_emi_write_bytes(u16 port, size_t length, u8 *msg, u8 *csum)
-{
-	size_t i;
-
-	printk(BIOS_DEBUG, "RTS5915: write port 0x%x, size %ld\n", port, length);
-
-	if (port >= EMI_RANGE_START && port <= EMI_RANGE_END) {
-		uint8_t *p = (uint8_t *)(HOSTCMD_PARAM_MEM_BASE + (port - EMI_RANGE_START));
-		for (i = 0; i < length; ++i) {
-			p[i] = msg[i];
-			if (csum)
-				*csum += msg[i];
-		}
-		return true;
-	}
-
-	return false;
-}
+static bool is_emi_inited;
 
 static inline void sio_write_config(uint8_t reg, uint8_t value)
 {
@@ -66,13 +31,15 @@ static inline void sio_write_config(uint8_t reg, uint8_t value)
 	outb(value, SIO_DATA_PORT);
 }
 
-void chipset_init(void)
+static void host_emi_init(void)
 {
 	/*
 	 * Due the hardware design, the RTS5915 EMI should be initiated by host sio command,
 	 * The EMI range is 256 bytes, chromeec needs two region for host command and ACPI
 	 * shared memory.
 	 */
+	if (is_emi_inited)
+		return;
 
 	printk(BIOS_INFO, "RTS5915 EMI: start init ...\n");
 
@@ -91,4 +58,47 @@ void chipset_init(void)
 	sio_write_config(EMI_CTRL, 0x01); /* Enable EMI */
 
 	printk(BIOS_INFO, "RTS5915 EMI: done\n");
+
+	is_emi_inited = true;
+}
+
+bool chipset_emi_read_bytes(u16 port, size_t length, u8 *dest, u8 *csum)
+{
+	size_t i;
+
+	host_emi_init();
+
+	printk(BIOS_DEBUG, "RTS5915: read port 0x%x, size %zu\n", port, length);
+
+	if (port >= EMI_RANGE_START && port <= EMI_RANGE_END) {
+		uint8_t *p = (uint8_t *)(HOSTCMD_PARAM_MEM_BASE + (port - EMI_RANGE_START));
+		for (i = 0; i < length; ++i) {
+			dest[i] = p[i];
+			if (csum)
+				*csum += dest[i];
+		}
+		return true;
+	}
+	return false;
+}
+
+bool chipset_emi_write_bytes(u16 port, size_t length, u8 *msg, u8 *csum)
+{
+	size_t i;
+
+	host_emi_init();
+
+	printk(BIOS_DEBUG, "RTS5915: write port 0x%x, size %zu\n", port, length);
+
+	if (port >= EMI_RANGE_START && port <= EMI_RANGE_END) {
+		uint8_t *p = (uint8_t *)(HOSTCMD_PARAM_MEM_BASE + (port - EMI_RANGE_START));
+		for (i = 0; i < length; ++i) {
+			p[i] = msg[i];
+			if (csum)
+				*csum += msg[i];
+		}
+		return true;
+	}
+
+	return false;
 }

From 03fca0f0b4c328cc1bf336e4eb74c0235cb2f1da Mon Sep 17 00:00:00 2001
From: Elmo Lan <elmo_lan@realtek.corp-partner.google.com>
Date: Tue, 17 Jun 2025 14:46:29 +0800
Subject: [PATCH 1351/3886] mb/google/brox: Enable support for Realtek EC

Add support for Realtek EC on brox_rtk_ec board.

BUG=b:414474440
TEST=FW_NAME=brox_rtk_ec emerge-brox coreboot chromeos-bootimage
     flash to brox board with realtek rts5915
     Boot normally and got those message from ap console:

[DEBUG]	Google Chrome EC uptime: 107.108 seconds
[DEBUG]	Google Chrome AP resets since EC boot: 2
[DEBUG]	Google Chrome most recent AP reset causes:
[DEBUG]		10.479: 32775 shutdown: entering G3
[DEBUG]		92.102: 8 reset: during EC initialization
[DEBUG]	Google Chrome EC reset flags at last EC boot: watchdog | sysjump
[DEBUG]	PNP: 0c09.0 init finished in 81 msecs

Change-Id: I65eaff78b6260548e8f30051a97ffadb69ec69c9
Signed-off-by: Elmo Lan <elmo_lan@realtek.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88122
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Jayvik Desai <jayvik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/ec/google/chromeec/Kconfig        | 4 ++++
 src/mainboard/google/brox/Kconfig     | 2 ++
 src/mainboard/google/brox/bootblock.c | 5 +++++
 3 files changed, 11 insertions(+)

diff --git a/src/ec/google/chromeec/Kconfig b/src/ec/google/chromeec/Kconfig
index 8e037f2496..fbd4758e71 100644
--- a/src/ec/google/chromeec/Kconfig
+++ b/src/ec/google/chromeec/Kconfig
@@ -222,6 +222,10 @@ config EC_GOOGLE_CHROMEEC_LPC_GENERIC_MEMORY_BASE
 	hex
 	default 0xfe0b0000
 
+config EC_GOOGLE_CHROMEEC_LPC_GENERIC_MEMORY_SIZE
+	hex
+	default 0x10000
+
 endif # EC_GOOGLE_CHROMEEC
 
 source "src/ec/google/chromeec/*/Kconfig"
diff --git a/src/mainboard/google/brox/Kconfig b/src/mainboard/google/brox/Kconfig
index d48b342782..a94995a168 100644
--- a/src/mainboard/google/brox/Kconfig
+++ b/src/mainboard/google/brox/Kconfig
@@ -63,6 +63,8 @@ config BOARD_GOOGLE_BROX_RTK_EC
 	select BOARD_GOOGLE_BASEBOARD_BROX
 	select CHROMEOS_WIFI_SAR if CHROMEOS
 	select USE_UNIFIED_AP_FIRMWARE_FOR_UFS_AND_NON_UFS
+	select EC_GOOGLE_CHROMEEC_RTK
+	select EC_GOOGLE_CHROMEEC_LPC_GENERIC_MEMORY_RANGE
 
 config BOARD_GOOGLE_BROX_TI_PDC
 	select BOARD_GOOGLE_BASEBOARD_BROX
diff --git a/src/mainboard/google/brox/bootblock.c b/src/mainboard/google/brox/bootblock.c
index 3a5f785582..31309ad411 100644
--- a/src/mainboard/google/brox/bootblock.c
+++ b/src/mainboard/google/brox/bootblock.c
@@ -4,6 +4,7 @@
 #include <baseboard/variants.h>
 #include <bootblock_common.h>
 #include <bootmode.h>
+#include <intelblocks/lpc_lib.h>
 #include <reset.h>
 #include <security/vboot/vboot_common.h>
 
@@ -25,6 +26,10 @@ void bootblock_mainboard_init(void)
 		board_reset();
 	}
 	variant_update_descriptor();
+
+	if (CONFIG(EC_GOOGLE_CHROMEEC_LPC_GENERIC_MEMORY_RANGE))
+		lpc_open_mmio_window(CONFIG_EC_GOOGLE_CHROMEEC_LPC_GENERIC_MEMORY_BASE,
+			CONFIG_EC_GOOGLE_CHROMEEC_LPC_GENERIC_MEMORY_SIZE);
 }
 
 void __weak variant_update_descriptor(void) {}

From df91698b112851400592098f3d40e14935d7174e Mon Sep 17 00:00:00 2001
From: Vince Liu <vince-wl.liu@mediatek.corp-partner.google.com>
Date: Tue, 10 Jun 2025 10:14:46 +0800
Subject: [PATCH 1352/3886] soc/mediatek/mt8196: Refactor mt8196 eDP driver for
 better code sharing

Refactor the MT8196 eDP driver to improve code reusability:
- Move common parts of dp_intf.h to dp_intf_v2.h
- Move common parts of dptx_hal.h to dptx_hal_v2.h
- Move common parts of dptx_reg.h to dptx_v2.h
- Extract shared code from dptx.c to dptx_v2.c
- Extract shared code from dptx_hal.c to dptx_hal_v2.c
- Rename dp_intf.c to dp_intf_v2.c

SoC-specific parts remain in its respective .c and .h files.

BUG=b:400886838
BRANCH=none
TEST=Check the display function on Navi

Signed-off-by: Vince Liu <vince-wl.liu@mediatek.corp-partner.google.com>
Change-Id: Ia41f62c0f5f7b5a38d7c5650e6f3a06963cc84a7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88149
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
---
 .../common/dp/{dp_intf.c => dp_intf_v1.c}     |   0
 .../dp_intf.c => common/dp/dp_intf_v2.c}      |   0
 .../common/dp/{dptx_hal.c => dptx_hal_v1.c}   |   0
 src/soc/mediatek/common/dp/dptx_hal_v2.c      | 358 +++++++++++++++
 .../mediatek/common/dp/{dptx.c => dptx_v1.c}  |   0
 src/soc/mediatek/common/dp/dptx_v2.c          | 412 ++++++++++++++++++
 .../soc/{dp_intf_common.h => dp_intf_v1.h}    |   6 +-
 .../common/dp/include/soc/dp_intf_v2.h        | 208 +++++++++
 .../common/dp/include/soc/dptx_common.h       |   4 +
 .../common/dp/include/soc/dptx_hal_v1.h       |   8 +
 .../common/dp/include/soc/dptx_hal_v2.h       |  30 ++
 .../common/dp/include/soc/dptx_reg_v1.h       |   8 +
 .../common/dp/include/soc/dptx_reg_v2.h       | 210 +++++++++
 src/soc/mediatek/mt8188/Makefile.mk           |   5 +-
 src/soc/mediatek/mt8188/include/soc/dp_intf.h |   2 +-
 .../mediatek/mt8188/include/soc/dptx_hal.h    |   2 +-
 .../mediatek/mt8188/include/soc/dptx_reg.h    |   2 +-
 src/soc/mediatek/mt8195/Makefile.mk           |   5 +-
 src/soc/mediatek/mt8195/include/soc/dp_intf.h |   2 +-
 .../mediatek/mt8195/include/soc/dptx_hal.h    |   2 +-
 .../mediatek/mt8195/include/soc/dptx_reg.h    |   2 +-
 src/soc/mediatek/mt8196/Makefile.mk           |   5 +-
 src/soc/mediatek/mt8196/dptx.c                | 410 +----------------
 src/soc/mediatek/mt8196/dptx_hal.c            | 350 +--------------
 src/soc/mediatek/mt8196/include/soc/dp_intf.h | 201 +--------
 .../mediatek/mt8196/include/soc/dptx_hal.h    |  24 +-
 .../mediatek/mt8196/include/soc/dptx_reg.h    | 203 +--------
 27 files changed, 1273 insertions(+), 1186 deletions(-)
 rename src/soc/mediatek/common/dp/{dp_intf.c => dp_intf_v1.c} (100%)
 rename src/soc/mediatek/{mt8196/dp_intf.c => common/dp/dp_intf_v2.c} (100%)
 rename src/soc/mediatek/common/dp/{dptx_hal.c => dptx_hal_v1.c} (100%)
 create mode 100644 src/soc/mediatek/common/dp/dptx_hal_v2.c
 rename src/soc/mediatek/common/dp/{dptx.c => dptx_v1.c} (100%)
 create mode 100644 src/soc/mediatek/common/dp/dptx_v2.c
 rename src/soc/mediatek/common/dp/include/soc/{dp_intf_common.h => dp_intf_v1.h} (97%)
 create mode 100644 src/soc/mediatek/common/dp/include/soc/dp_intf_v2.h
 create mode 100644 src/soc/mediatek/common/dp/include/soc/dptx_hal_v1.h
 create mode 100644 src/soc/mediatek/common/dp/include/soc/dptx_hal_v2.h
 create mode 100644 src/soc/mediatek/common/dp/include/soc/dptx_reg_v1.h
 create mode 100644 src/soc/mediatek/common/dp/include/soc/dptx_reg_v2.h

diff --git a/src/soc/mediatek/common/dp/dp_intf.c b/src/soc/mediatek/common/dp/dp_intf_v1.c
similarity index 100%
rename from src/soc/mediatek/common/dp/dp_intf.c
rename to src/soc/mediatek/common/dp/dp_intf_v1.c
diff --git a/src/soc/mediatek/mt8196/dp_intf.c b/src/soc/mediatek/common/dp/dp_intf_v2.c
similarity index 100%
rename from src/soc/mediatek/mt8196/dp_intf.c
rename to src/soc/mediatek/common/dp/dp_intf_v2.c
diff --git a/src/soc/mediatek/common/dp/dptx_hal.c b/src/soc/mediatek/common/dp/dptx_hal_v1.c
similarity index 100%
rename from src/soc/mediatek/common/dp/dptx_hal.c
rename to src/soc/mediatek/common/dp/dptx_hal_v1.c
diff --git a/src/soc/mediatek/common/dp/dptx_hal_v2.c b/src/soc/mediatek/common/dp/dptx_hal_v2.c
new file mode 100644
index 0000000000..7000d89472
--- /dev/null
+++ b/src/soc/mediatek/common/dp/dptx_hal_v2.c
@@ -0,0 +1,358 @@
+/* SPDX-License-Identifier: GPL-2.0-only OR MIT */
+
+#include <assert.h>
+#include <console/console.h>
+#include <device/mmio.h>
+#include <delay.h>
+#include <edid.h>
+#include <soc/dptx.h>
+#include <soc/dptx_hal.h>
+#include <soc/dptx_reg.h>
+#include <types.h>
+
+const int dptx_hal_driving_offset[] = {
+	PHYD_DIG_LAN0_OFFSET + DRIVING_FORCE,
+	PHYD_DIG_LAN1_OFFSET + DRIVING_FORCE,
+	PHYD_DIG_LAN2_OFFSET + DRIVING_FORCE,
+	PHYD_DIG_LAN3_OFFSET + DRIVING_FORCE,
+};
+
+const int dptx_hal_driving_offset_size = ARRAY_SIZE(dptx_hal_driving_offset);
+
+void dptx_hal_init_setting(struct mtk_dp *mtk_dp)
+{
+	mtk_dp_mask(mtk_dp, 0x2000, GENMASK(1, 0), GENMASK(1, 0));
+
+	mtk_dp_mask(mtk_dp, REG_3540_DP_TRANS_P0, BIT(3), BIT(3));
+	mtk_dp_mask(mtk_dp, REG_342C_DP_TRANS_P0, 0x68, 0xFF);
+	mtk_dp_mask(mtk_dp, REG_31EC_DP_ENCODER0_P0, BIT(4), BIT(4));
+	mtk_dp_mask(mtk_dp, REG_304C_DP_ENCODER0_P0, 0, BIT(8));
+	mtk_dp_mask(mtk_dp, REG_304C_DP_ENCODER0_P0, BIT(3), BIT(3));
+
+	/* default marker */
+	mtk_dp_mask(mtk_dp, REG_3F04_DP_ENC_4P_3, 0, 0xFFFF);
+	mtk_dp_mask(mtk_dp, REG_3F08_DP_ENC_4P_3, BIT(3), BIT(3));
+	mtk_dp_mask(mtk_dp, REG_3F0C_DP_ENC_4P_3, BIT(1), BIT(1));
+	mtk_dp_mask(mtk_dp, REG_3F10_DP_ENC_4P_3, BIT(3), BIT(3));
+
+	mtk_dp_mask(mtk_dp, REG_33C0_DP_ENCODER1_P0, 0, 0xF000);
+	mtk_dp_mask(mtk_dp, REG_33C0_DP_ENCODER1_P0, 0x80, 0x80);
+	mtk_dp_mask(mtk_dp, REG_33C4_DP_ENCODER1_P0, BIT(5), BIT(6) | BIT(5));
+	mtk_dp_mask(mtk_dp, REG_3F28_DP_ENC_4P_3, 0xA << 2, GENMASK(5, 2));
+	mtk_dp_mask(mtk_dp, DP_TX_TOP_RESET_AND_PROBE, 0x9100FF, 0x9100FF);
+
+	mtk_dp_mask(mtk_dp, MTK_DP_TOP_IRQ_MASK, ENCODER_IRQ_MSK | TRANS_IRQ_MSK,
+		    ENCODER_IRQ_MSK | TRANS_IRQ_MSK);
+}
+
+void dptx_hal_set_color_format(struct mtk_dp *mtk_dp, u8 out_format)
+{
+	u32 val;
+
+	/* MISC0 */
+	mtk_dp_mask(mtk_dp, REG_3034_DP_ENCODER0_P0, out_format << DP_TEST_COLOR_FORMAT_SHIFT,
+		    DP_TEST_COLOR_FORMAT_MASK);
+	mtk_dp_mask(mtk_dp, REG_3034_DP_ENCODER0_P0, BIT(3), BIT(3));
+
+	switch (out_format) {
+	case DP_COLOR_FORMAT_RGB_444:
+	case DP_COLOR_FORMAT_YUV_444:
+		val = 0;
+		break;
+	case DP_COLOR_FORMAT_YUV_422:
+		val = 0x1;
+		break;
+	case DP_COLOR_FORMAT_YUV_420:
+		val = 0x2;
+		break;
+	default:
+		printk(BIOS_ERR, "Unsupported color format: %u\n", out_format);
+		return;
+	}
+	mtk_dp_mask(mtk_dp, REG_303C_DP_ENCODER0_P0, val << 12, 0x7 << 12);
+}
+
+void dptx_hal_settu_setencoder(struct mtk_dp *mtk_dp)
+{
+	mtk_dp_mask(mtk_dp, REG_303C_DP_ENCODER0_P0, BIT(15), BIT(15));
+	DP_WRITE2BYTE(mtk_dp, REG_3040_DP_ENCODER0_P0, 0x2020);
+	DP_WRITE2BYTE(mtk_dp, REG_3364_DP_ENCODER1_P0, 0x2020);
+	mtk_dp_mask(mtk_dp, REG_3300_DP_ENCODER1_P0, 0x2 << 8, 0x3 << 8);
+	mtk_dp_mask(mtk_dp, REG_3364_DP_ENCODER1_P0, 0x40 << 8, 0x70 << 8);
+}
+
+bool dptx_hal_hpd_high(struct mtk_dp *mtk_dp)
+{
+	return mtk_dp_read(mtk_dp, REG_364C_AUX_TX_P0) & BIT(15);
+}
+
+bool dptx_hal_setswing_preemphasis(struct mtk_dp *mtk_dp, int lane_num, u8 swing_value,
+				   u8 preemphasis)
+{
+	assert(lane_num <= DPTX_LANE_MAX);
+
+	for (int i = 0; i < lane_num; ++i) {
+		mtk_dp_phy_mask(mtk_dp, dptx_hal_driving_offset[i],
+				swing_value << EDP_TX_LN_VOLT_SWING_VAL_SHIFT |
+				preemphasis << EDP_TX_LN_PRE_EMPH_VAL_SHIFT,
+				EDP_TX_LN_VOLT_SWING_VAL_MASK | EDP_TX_LN_PRE_EMPH_VAL_MASK);
+		printk(BIOS_DEBUG, "lane(%d), set swing(%u), emp(%u)\n",
+		       i, swing_value, preemphasis);
+	}
+	mtk_dp_mask(mtk_dp, 0x2000, GENMASK(1, 0), GENMASK(1, 0));
+	return true;
+}
+
+void dptx_hal_hpd_detect_setting(struct mtk_dp *mtk_dp)
+{
+	mtk_dp_mask(mtk_dp, REG_364C_AUX_TX_P0, HPD_INT_THD_FLDMASK_VAL << 4,
+		    HPD_INT_THD_FLDMASK);
+}
+
+void dptx_hal_phy_init(struct mtk_dp *mtk_dp)
+{
+	mtk_dp_phy_mask(mtk_dp, IPMUX_CONTROL, 0 << EDPTX_DSI_PHYD_SEL_FLDMASK_POS,
+			EDPTX_DSI_PHYD_SEL_FLDMASK);
+
+	mtk_dp_phy_mask(mtk_dp, PHYD_DIG_GLB_OFFSET + 0x10, GENMASK(2, 0), GENMASK(2, 0));
+	dptx_hal_ssc_en(mtk_dp, false);
+}
+
+void dptx_hal_set_txrate(struct mtk_dp *mtk_dp, u8 value)
+{
+	printk(BIOS_INFO, "Link rate = 0x%x\n", value);
+	switch (value) {
+	case DP_LINKRATE_RBR:
+		mtk_dp_phy_write(mtk_dp, 0x143C, DP_LINKRATE_RBR_VAL);
+		break;
+	case DP_LINKRATE_HBR:
+		mtk_dp_phy_write(mtk_dp, 0x143C, DP_LINKRATE_HBR_VAL);
+		break;
+	case DP_LINKRATE_HBR2:
+		mtk_dp_phy_write(mtk_dp, 0x143C, DP_LINKRATE_HBR2_VAL);
+		break;
+	case DP_LINKRATE_HBR3:
+		mtk_dp_phy_write(mtk_dp, 0x143C, DP_LINKRATE_HBR3_VAL);
+		break;
+	default:
+		printk(BIOS_ERR, "Link rate not support(%d)\n", value);
+		return;
+	}
+}
+
+void dptx_hal_phy_setting(struct mtk_dp *mtk_dp)
+{
+	u8 link_rate = mtk_dp->train_info.linkrate;
+	u8 lane_count = mtk_dp->train_info.linklane_count;
+
+	dptx_hal_phy_set_lanes(mtk_dp, lane_count);
+	dptx_hal_set_txrate(mtk_dp, link_rate);
+
+	/* Turn on phy power after phy configure */
+	mtk_dp_mask(mtk_dp, REG_3FF8_DP_ENC_4P_3, PHY_STATE_W_1_DP_ENC_4P_3,
+		    PHY_STATE_W_1_DP_ENC_4P_3_MASK);
+	mtk_dp_mask(mtk_dp, 0x2000, GENMASK(1, 0), GENMASK(1, 0));
+	printk(BIOS_DEBUG, "[eDPTX] DP_PHY_DIG_PLL_CTL_1:%#x\n",
+	       mtk_dp_phy_read(mtk_dp, DP_PHY_DIG_PLL_CTL_1));
+}
+
+void dptx_hal_ssc_en(struct mtk_dp *mtk_dp, bool enable)
+{
+	if (enable) {
+		printk(BIOS_DEBUG, "[eDPTX] enable ssc\n");
+		mtk_dp_phy_mask(mtk_dp, DP_PHY_DIG_PLL_CTL_1, BIT(8), BIT(8));
+	} else {
+		printk(BIOS_DEBUG, "[eDPTX] disable ssc\n");
+		mtk_dp_phy_mask(mtk_dp, DP_PHY_DIG_PLL_CTL_1, 0x0, BIT(8));
+	}
+	printk(BIOS_DEBUG, "[eDPTX] DP_PHY_DIG_PLL_CTL_1:%#x\n",
+	       mtk_dp_phy_read(mtk_dp, DP_PHY_DIG_PLL_CTL_1));
+
+	mdelay(1);
+}
+
+void dptx_hal_aux_setting(struct mtk_dp *mtk_dp)
+{
+	/* Modify timeout threshold = 1595 [12 : 8] */
+	mtk_dp_mask(mtk_dp, REG_360C_AUX_TX_P0, 0x1D0C, 0x1FFF);
+	mtk_dp_mask(mtk_dp, REG_3658_AUX_TX_P0, 0, BIT(0));
+	/* [0]mtk_dp, REG_aux_tx_ov_en */
+	mtk_dp_mask(mtk_dp, REG_36A0_AUX_TX_4P, 0xFFFC, 0xFFFC);
+
+	/* 26M */
+	mtk_dp_mask(mtk_dp, REG_3634_AUX_TX_P0, AUX_TX_OVER_SAMPLE_RATE_FOR_26M << 8,
+		    0xff << 8);
+	mtk_dp_mask(mtk_dp, REG_3614_AUX_TX_P0, AUX_RX_UI_CNT_THR_AUX_FOR_26M, 0x7f);
+
+	/* Modify, 13 for 26M */
+	mtk_dp_mask(mtk_dp, REG_37C8_AUX_TX_P0, MTK_ATOP_EN_AUX_TX_4P, MTK_ATOP_EN_AUX_TX_4P);
+	/* Disable aux sync_stop detect function */
+	mtk_dp_mask(mtk_dp, REG_3690_AUX_TX_P0, RX_REPLY_COMPLETE_MODE_AUX_TX_4P,
+		    RX_REPLY_COMPLETE_MODE_AUX_TX_4P);
+
+	mtk_dp_mask(mtk_dp, REG_367C_AUX_TX_P0, HPD_CONN_THD_AUX_TX_P0_FLDMASK_POS << 6,
+		    HPD_CONN_THD_AUX_TX_P0_FLDMASK);
+
+	mtk_dp_mask(mtk_dp, REG_37A0_AUX_TX_P0, HPD_DISC_THD_AUX_TX_P0_FLDMASK_POS << 4,
+		    HPD_DISC_THD_AUX_TX_P0_FLDMASK);
+	mtk_dp_mask(mtk_dp, REG_3690_AUX_TX_P0, RX_REPLY_COMPLETE_MODE_AUX_TX_4P,
+		    RX_REPLY_COMPLETE_MODE_AUX_TX_4P);
+	mtk_dp_mask(mtk_dp, REG_3FF8_DP_ENC_4P_3, XTAL_FREQ_FOR_PSR_DP_ENC_4P_3_VALUE << 9,
+		    XTAL_FREQ_FOR_PSR_DP_ENC_4P_3_MASK);
+	mtk_dp_mask(mtk_dp, REG_366C_AUX_TX_P0, XTAL_FREQ_DP_TX_AUX_366C_VALUE << 8,
+		    XTAL_FREQ_DP_TX_AUX_366C_MASK);
+}
+
+void dptx_hal_digital_setting(struct mtk_dp *mtk_dp)
+{
+	mtk_dp_mask(mtk_dp, REG_304C_DP_ENCODER0_P0, 0, VBID_VIDEO_MUTE_DP_ENC0_4P_MASK);
+	mtk_dp_mask(mtk_dp, REG_3368_DP_ENCODER1_P0, BS2BS_MODE_DP_ENC1_4P_VAL << 12,
+		    0x3 << 12);
+	mtk_dp_mask(mtk_dp, REG_3030_DP_ENCODER0_P0, BIT(11), BIT(11));
+
+	/* dp I-mode enable */
+	mtk_dp_mask(mtk_dp, BS2BS_MODE_DP_ENCODER1_P0_FLDMASK, DP_I_MODE_ENABLE,
+		    DP_I_MODE_ENABLE);
+	mtk_dp_mask(mtk_dp, REG_3030_DP_ENCODER0_P0, 0x3ff, 0x3ff);
+	mtk_dp_mask(mtk_dp, REG_3028_DP_ENCODER0_P0, 0, BIT(15));
+	mtk_dp_mask(mtk_dp, REG_302C_DP_ENCODER0_P0, 0, BIT(15));
+
+	/* set color format */
+	dptx_hal_set_color_format(mtk_dp, DP_COLOR_FORMAT_RGB_444);
+
+	/* set color depth */
+	dptx_hal_set_color_depth(mtk_dp, DP_COLOR_DEPTH_8BIT);
+
+	/* reg_bs)symbol_cnt_reset */
+	mtk_dp_mask(mtk_dp, REG_3000_DP_ENCODER0_P0, REG_BS_SYMBOL_CNT_RESET,
+		    REG_BS_SYMBOL_CNT_RESET);
+	mtk_dp_mask(mtk_dp, REG_3004_DP_ENCODER0_P0, BIT(14), BIT(14));
+	printk(BIOS_DEBUG, "[eDPTX] REG_3004_DP_ENCODER0_P0:%#x\n",
+	       mtk_dp_read(mtk_dp, REG_3004_DP_ENCODER0_P0));
+
+	mtk_dp_mask(mtk_dp, REG_3368_DP_ENCODER1_P0, 0x2, BIT(1) | BIT(2));
+	mtk_dp_mask(mtk_dp, REG_3368_DP_ENCODER1_P0, BIT(15), BIT(15));
+	mtk_dp_mask(mtk_dp, REG_304C_DP_ENCODER0_P0, 0, BIT(8));
+
+	/* [5:0]video sram start address */
+	mtk_dp_mask(mtk_dp, REG_303C_DP_ENCODER0_P0, 0x8, 0x3F);
+
+	/* reg_psr_patgen_avt_en patch */
+	mtk_dp_mask(mtk_dp, REG_3F80_DP_ENC_4P_3, 0, PSR_PATGEN_AVT_EN_FLDMASK);
+
+	/* phy D enable */
+	mtk_dp_mask(mtk_dp, REG_3FF8_DP_ENC_4P_3, PHY_STATE_W_1_DP_ENC_4P_3,
+		    PHY_STATE_W_1_DP_ENC_4P_3_MASK);
+
+	/* reg_dvo_on_ow_en */
+	mtk_dp_mask(mtk_dp, REG_3FF8_DP_ENC_4P_3, DVO_ON_W_1_FLDMASK, DVO_ON_W_1_FLDMASK);
+
+	/* dp tx encoder reset all sw */
+	mtk_dp_mask(mtk_dp, REG_3004_DP_ENCODER0_P0, DP_TX_ENCODER_4P_RESET_SW_DP_ENC0_P0,
+		    DP_TX_ENCODER_4P_RESET_SW_DP_ENC0_P0);
+	printk(BIOS_DEBUG, "[eDPTX] REG_3004_DP_ENCODER0_P0:%#x\n",
+	       mtk_dp_read(mtk_dp, REG_3004_DP_ENCODER0_P0));
+
+	mtk_dp_mask(mtk_dp, REG_3004_DP_ENCODER0_P0, 0, BIT(9));
+	printk(BIOS_DEBUG, "[eDPTX] REG_3004_DP_ENCODER0_P0:%#x\n",
+	       mtk_dp_read(mtk_dp, REG_3004_DP_ENCODER0_P0));
+
+	mtk_dp_mask(mtk_dp, REG_3FF8_DP_ENC_4P_3, 0xff, 0xff);
+
+	/* Wait for sw reset to complete */
+	mdelay(1);
+}
+
+void dptx_hal_digital_swreset(struct mtk_dp *mtk_dp)
+{
+	printk(BIOS_DEBUG, "[eDPTX] DP_PHY_DIG_TX_CTL_0:%#x\n",
+	       mtk_dp_phy_read(mtk_dp, DP_PHY_DIG_TX_CTL_0));
+	mtk_dp_mask(mtk_dp, REG_340C_DP_TRANS_P0, BIT(13), BIT(13));
+	mdelay(1);
+	mtk_dp_mask(mtk_dp, REG_340C_DP_TRANS_P0, 0, BIT(13));
+
+	mtk_dp_mask(mtk_dp, EDP_TX_TOP_CLKGEN_0, 0xF, 0xF);
+	printk(BIOS_DEBUG, "[eDPTX] DP_PHY_DIG_TX_CTL_0:%#x\n",
+	       mtk_dp_phy_read(mtk_dp, DP_PHY_DIG_TX_CTL_0));
+}
+
+void dptx_hal_swing_emp_reset(struct mtk_dp *mtk_dp)
+{
+	mtk_dp_mask(mtk_dp, REG_2004_TOP_SWING_EMP, 0,
+		    DP_TX0_VOLT_SWING_MASK | DP_TX1_VOLT_SWING_MASK | DP_TX2_VOLT_SWING_MASK |
+		    DP_TX3_VOLT_SWING_MASK | DP_TX0_PRE_EMPH_MASK | DP_TX1_PRE_EMPH_MASK |
+		    DP_TX2_PRE_EMPH_MASK | DP_TX3_PRE_EMPH_MASK);
+}
+
+void dptx_hal_phy_wait_aux_ldo_ready(struct mtk_dp *mtk_dp)
+{
+	u32 mask = RGS_BG_CORE_EN_READY_MASK | RGS_AUX_LDO_EN_READY_MASK;
+
+	if (!retry(WAIT_AUX_READY_RETRY_TIMES,
+		   (mtk_dp_phy_read(mtk_dp, DP_PHY_DIG_GLB_STATUS_02_OFSSET) & mask) == mask,
+		   mdelay(2))) {
+		printk(BIOS_ERR, "Wait AUX LDO ready timeout!\n");
+	}
+}
+
+void dptx_hal_set_txlane(struct mtk_dp *mtk_dp, u8 value)
+{
+	/* Turn off phy power before phy configure */
+	mtk_dp_mask(mtk_dp, REG_3F44_DP_ENC_4P_3, PHY_PWR_STATE_OW_EN_DP_ENC_4P_3,
+		    PHY_PWR_STATE_OW_EN_DP_ENC_4P_3_MASK);
+	mtk_dp_mask(mtk_dp, REG_3F44_DP_ENC_4P_3, BIAS_POWER_ON,
+		    PHY_PWR_STATE_OW_VALUE_DP_ENC_4P_3_MASK);
+	dptx_hal_phy_wait_aux_ldo_ready(mtk_dp);
+	mtk_dp_mask(mtk_dp, REG_3F44_DP_ENC_4P_3, 0 << 2, PHY_PWR_STATE_OW_EN_DP_ENC_4P_3_MASK);
+
+	if (value == 0)
+		mtk_dp_mask(mtk_dp, REG_35F0_DP_TRANS_P0, 0, BIT(3) | BIT(2));
+	else
+		mtk_dp_mask(mtk_dp, REG_35F0_DP_TRANS_P0, BIT(3), BIT(3) | BIT(2));
+
+	assert((value << 2) <= UINT8_MAX);
+	mtk_dp_mask(mtk_dp, REG_3000_DP_ENCODER0_P0, value, BIT(1) | BIT(0));
+	mtk_dp_mask(mtk_dp, REG_34A4_DP_TRANS_P0, value << 2, BIT(3) | BIT(2));
+}
+
+void dptx_hal_phy_set_swing_preemphasis(struct mtk_dp *mtk_dp, u8 lane_count, u8 *swing_val,
+					 u8 *preemphasis)
+{
+	assert(lane_count <= DPTX_LANE_MAX);
+
+	for (int i = 0; i < lane_count; ++i) {
+		mtk_dp_phy_mask(mtk_dp, dptx_hal_driving_offset[i],
+				swing_val[i] << EDP_TX_LN_VOLT_SWING_VAL_SHIFT |
+				preemphasis[i] << EDP_TX_LN_PRE_EMPH_VAL_SHIFT,
+				EDP_TX_LN_VOLT_SWING_VAL_MASK | EDP_TX_LN_PRE_EMPH_VAL_MASK);
+		printk(BIOS_DEBUG, "lane(%d), set swing(%u), emp(%u)\n",
+		       i, swing_val[i], preemphasis[i]);
+	}
+}
+
+void dptx_hal_phy_set_idle_pattern(struct mtk_dp *mtk_dp, u8 lane_count, bool enable)
+{
+	u32 val = 0x0;
+
+	printk(BIOS_INFO, "lane_count: %x idle pattern enable: %d\n", lane_count, enable);
+	switch (lane_count) {
+	case 1:
+		val = POST_MISC_DATA_LANE0_OV_DP_TRANS_4P_MASK;
+		break;
+	case 2:
+		val = POST_MISC_DATA_LANE0_OV_DP_TRANS_4P_MASK |
+		      POST_MISC_DATA_LANE1_OV_DP_TRANS_4P_MASK;
+		break;
+	case 4:
+		val = POST_MISC_DATA_LANE0_OV_DP_TRANS_4P_MASK |
+		      POST_MISC_DATA_LANE1_OV_DP_TRANS_4P_MASK |
+		      POST_MISC_DATA_LANE2_OV_DP_TRANS_4P_MASK |
+		      POST_MISC_DATA_LANE3_OV_DP_TRANS_4P_MASK;
+		break;
+	default:
+		printk(BIOS_ERR, "%s: Unexpected lane count %d\n", __func__, lane_count);
+		return;
+	}
+	mtk_dp_mask(mtk_dp, REG_3580_DP_TRANS_P0, (enable ? val : 0x0) << 8,
+		    POST_MISC_DATA_LANE_OV_DP_TRANS_4P_MASK);
+}
diff --git a/src/soc/mediatek/common/dp/dptx.c b/src/soc/mediatek/common/dp/dptx_v1.c
similarity index 100%
rename from src/soc/mediatek/common/dp/dptx.c
rename to src/soc/mediatek/common/dp/dptx_v1.c
diff --git a/src/soc/mediatek/common/dp/dptx_v2.c b/src/soc/mediatek/common/dp/dptx_v2.c
new file mode 100644
index 0000000000..80e1f7c33e
--- /dev/null
+++ b/src/soc/mediatek/common/dp/dptx_v2.c
@@ -0,0 +1,412 @@
+/* SPDX-License-Identifier: GPL-2.0-only OR MIT */
+
+#include <assert.h>
+#include <commonlib/bsd/helpers.h>
+#include <console/console.h>
+#include <delay.h>
+#include <device/mmio.h>
+#include <edid.h>
+#include <soc/addressmap.h>
+#include <soc/dp_intf.h>
+#include <soc/dptx.h>
+#include <soc/dptx_hal.h>
+#include <soc/dptx_reg.h>
+
+static void mtk_edp_pattern(struct mtk_dp *mtk_dp, u8 lane_count, u8 pattern)
+{
+	u8 aux_offset;
+
+	switch (pattern) {
+	case DPTX_PATTERN_TPS1:
+		aux_offset = DP_TRAINING_PATTERN_1 | DP_LINK_SCRAMBLING_DISABLE;
+		dptx_hal_phy_set_idle_pattern(mtk_dp, lane_count, false);
+		mtk_dp_mask(mtk_dp, REG_3400_DP_TRANS_P0, PATTERN1_EN_DP_TRANS_4P_TPS1,
+			    PATTERN_EN_DP_TRANS_4P_MASK);
+		break;
+	case DPTX_PATTERN_TPS2:
+		aux_offset = DP_TRAINING_PATTERN_2 | DP_LINK_SCRAMBLING_DISABLE;
+		mtk_dp_mask(mtk_dp, REG_3400_DP_TRANS_P0, PATTERN2_EN_DP_TRANS_4P_TPS2,
+			    PATTERN_EN_DP_TRANS_4P_MASK);
+		break;
+	case DPTX_PATTERN_TPS3:
+		aux_offset = DP_TRAINING_PATTERN_3 | DP_LINK_SCRAMBLING_DISABLE;
+		mtk_dp_mask(mtk_dp, REG_3400_DP_TRANS_P0, PATTERN3_EN_DP_TRANS_4P_TPS3,
+			    PATTERN_EN_DP_TRANS_4P_MASK);
+		break;
+	case DPTX_PATTERN_TPS4:
+		aux_offset = DP_TRAINING_PATTERN_4;
+		mtk_dp_mask(mtk_dp, REG_3400_DP_TRANS_P0, PATTERN4_EN_DP_TRANS_4P_TPS4,
+			    PATTERN_EN_DP_TRANS_4P_MASK);
+		break;
+	case DPTX_PATTERN_UNKNOWN:
+	default:
+		printk(BIOS_ERR, "Set default or unknown pattern\n");
+		mtk_dp_mask(mtk_dp, REG_3400_DP_TRANS_P0, 0x0, PATTERN_EN_DP_TRANS_4P_MASK);
+		return;
+	}
+
+	dptx_auxwrite_dpcd(mtk_dp, DP_AUX_NATIVE_WRITE, DPCD_00102, 0x1, &aux_offset);
+}
+
+static void update_swing_preemphasis(struct mtk_dp *mtk_dp, u8 lane_count,
+				     u8 dpcd_adjust_req[DP_LANSE_ADJUST_SIZE])
+{
+	u8 swing_val[MAX_LANECOUNT];
+	u8 preemphasis[MAX_LANECOUNT];
+
+	for (int lane = 0; lane < lane_count; lane++) {
+		u8 val;
+		int index = lane / 2;
+		assert(index < DP_LANSE_ADJUST_SIZE);
+		int shift = lane % 2 ? DP_ADJUST_VOLTAGE_SWING_LANE1_SHIFT : 0;
+		u8 swing_value = dpcd_adjust_req[index] >> shift;
+
+		if (mtk_dp->force_max_swing) {
+			swing_val[lane] = DPTX_SWING3;
+			printk(BIOS_INFO, "%s: Force swing setting to %u (500 mV)\n",
+			       __func__, swing_val[lane]);
+		} else {
+			swing_val[lane] = swing_value & DP_ADJUST_VOLTAGE_SWING_LANE0_MASK;
+		}
+		preemphasis[lane] = swing_value & DP_ADJUST_PRE_EMPHASIS_LANE0_MASK;
+		preemphasis[lane] >>= DP_ADJUST_PRE_EMPHASIS_LANE0_SHIFT;
+		val = swing_val[lane] << DP_TRAIN_VOLTAGE_SWING_SHIFT |
+		      preemphasis[lane] << DP_TRAIN_PRE_EMPHASIS_SHIFT;
+
+		if (swing_val[lane] == DPTX_SWING3)
+			val |= DP_TRAIN_MAX_SWING_REACHED;
+		if (preemphasis[lane] == DPTX_PREEMPHASIS3)
+			val |= DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
+
+		dptx_auxwrite_dpcd(mtk_dp, DP_AUX_NATIVE_WRITE, DPCD_00103 + lane, 0x1, &val);
+	}
+
+	dptx_hal_phy_set_swing_preemphasis(mtk_dp, lane_count, swing_val, preemphasis);
+}
+
+static void dptx_training_changemode(struct mtk_dp *mtk_dp)
+{
+	dptx_hal_phyd_reset(mtk_dp);
+	dptx_hal_swing_emp_reset(mtk_dp);
+
+	mdelay(2);
+}
+
+static void mtk_edp_train_setting(struct mtk_dp *mtk_dp,
+				  u8 linkrate, u8 lanecount)
+{
+	u8 lanecount_enhanced_frame;
+	u8 dpcd_data;
+
+	lanecount_enhanced_frame = lanecount | DP_LANE_COUNT_ENHANCED_FRAME_EN;
+
+	dptx_auxwrite_dpcd(mtk_dp, DP_AUX_NATIVE_WRITE, DPCD_00100, 0x1, &linkrate);
+	dptx_auxwrite_dpcd(mtk_dp, DP_AUX_NATIVE_WRITE, DPCD_00101, 0x1,
+			   &lanecount_enhanced_frame);
+	if (mtk_dp->train_info.sink_ssc_en) {
+		dpcd_data = DP_SPREAD_AMP_0_5;
+		dptx_auxwrite_dpcd(mtk_dp, DP_AUX_NATIVE_WRITE, DPCD_00107, 0x1, &dpcd_data);
+		dptx_hal_ssc_en(mtk_dp, true);
+	} else {
+		dpcd_data = 0x0;
+		dptx_auxwrite_dpcd(mtk_dp, DP_AUX_NATIVE_WRITE, DPCD_00107, 0x1, &dpcd_data);
+		dptx_hal_ssc_en(mtk_dp, false);
+	}
+	dptx_hal_set_txlane(mtk_dp, lanecount / 2);
+	dptx_hal_phy_setting(mtk_dp);
+
+	printk(BIOS_INFO, "Link train linkrate = %#x, lanecount = %#x\n",
+	       linkrate, lanecount);
+}
+
+static void drm_dp_dpcd_read_link_status(struct mtk_dp *mtk_dp, u8 status[DP_LINK_STATUS_SIZE])
+{
+	dptx_auxread_dpcd(mtk_dp, DP_AUX_NATIVE_READ, DPCD_00202, DP_LINK_STATUS_SIZE, status);
+}
+
+static int mtk_edp_train_cr(struct mtk_dp *mtk_dp, u8 lane_count)
+{
+	u8 lane_adjust[DP_LANSE_ADJUST_SIZE];
+	u8 link_status[DP_LINK_STATUS_SIZE];
+	u8 prev_lane_adjust = 0xff;
+	int train_retries = 0;
+	int voltage_retries = 0;
+	u8 buff;
+
+	mtk_edp_pattern(mtk_dp, lane_count, DPTX_PATTERN_TPS1);
+
+	/* In DP spec 1.4, the retry count of CR is defined as 10. */
+	do {
+		train_retries++;
+		if (!dptx_hal_hpd_high(mtk_dp)) {
+			mtk_edp_pattern(mtk_dp, lane_count, DPTX_PATTERN_UNKNOWN);
+			return DPTX_TRANING_FAIL;
+		}
+
+		dptx_auxread_dpcd(mtk_dp, DP_AUX_NATIVE_READ, DPCD_00206, sizeof(lane_adjust),
+				  lane_adjust);
+		printk(BIOS_DEBUG, "[aux_read] dpcd206 lane_adjust[0]=%#x\n", lane_adjust[0]);
+		printk(BIOS_DEBUG, "[aux_read] dpcd207 lane_adjust[1]=%#x\n", lane_adjust[1]);
+		update_swing_preemphasis(mtk_dp, lane_count, lane_adjust);
+
+		dptx_link_train_clock_recovery_delay(mtk_dp->rx_cap);
+
+		/* Check link status from sink device */
+		drm_dp_dpcd_read_link_status(mtk_dp, link_status);
+		if (dptx_clock_recovery_ok(link_status, lane_count)) {
+			printk(BIOS_INFO, "Link train CR pass\n");
+			return 0;
+		}
+
+		/*
+		 * In DP spec 1.4, if current voltage level is the same
+		 * with previous voltage level, we need to retry 5 times.
+		 */
+		if (prev_lane_adjust == link_status[4]) {
+			voltage_retries++;
+			/*
+			 * Condition of CR fail:
+			 * 1. Failed to pass CR using the same voltage
+			 *    level over five times.
+			 * 2. Failed to pass CR when the current voltage
+			 *    level is the same with previous voltage
+			 *    level and reach max voltage level (3).
+			 */
+			if (voltage_retries > MTK_DP_TRAIN_VOLTAGE_LEVEL_RETRY ||
+			    (prev_lane_adjust & DP_ADJUST_VOLTAGE_SWING_LANE0_MASK) == 3) {
+				printk(BIOS_ERR, "Link train CR fail\n");
+				break;
+			}
+		} else {
+			/*
+			 * If the voltage level is changed, we need to
+			 * re-calculate this retry count.
+			 */
+			voltage_retries = 0;
+		}
+		prev_lane_adjust = link_status[4];
+		printk(BIOS_INFO, "CR training retries %d\n", voltage_retries);
+	} while (train_retries < MTK_DP_TRAIN_DOWNSCALE_RETRY);
+
+	/* Failed to train CR, and disable pattern. */
+	buff = DP_TRAINING_PATTERN_DISABLE;
+	dptx_auxwrite_dpcd(mtk_dp, DP_AUX_NATIVE_WRITE, DPCD_00102, 0x1, &buff);
+	mtk_edp_pattern(mtk_dp, lane_count, DPTX_PATTERN_UNKNOWN);
+
+	return DPTX_TRANING_FAIL;
+}
+
+static int mtk_edp_train_eq(struct mtk_dp *mtk_dp, u8 lane_count)
+{
+	u8 lane_adjust[2];
+	u8 link_status[DP_LINK_STATUS_SIZE];
+	int train_retries = 0;
+	u8 buff;
+
+	if (mtk_dp->train_info.tps4)
+		mtk_edp_pattern(mtk_dp, lane_count, DPTX_PATTERN_TPS4);
+	else if (mtk_dp->train_info.tps3)
+		mtk_edp_pattern(mtk_dp, lane_count, DPTX_PATTERN_TPS3);
+	else
+		mtk_edp_pattern(mtk_dp, lane_count, DPTX_PATTERN_TPS2);
+
+	do {
+		train_retries++;
+		if (!dptx_hal_hpd_high(mtk_dp)) {
+			mtk_edp_pattern(mtk_dp, lane_count, DPTX_PATTERN_UNKNOWN);
+			return DPTX_TRANING_FAIL;
+		}
+
+		dptx_auxread_dpcd(mtk_dp, DP_AUX_NATIVE_READ, DPCD_00206, sizeof(lane_adjust),
+				  lane_adjust);
+		printk(BIOS_DEBUG, "[aux_read] dpcd206 lane_adjust[0]=%#x\n", lane_adjust[0]);
+		printk(BIOS_DEBUG, "[aux_read] dpcd207 lane_adjust[1]=%#x\n", lane_adjust[1]);
+		update_swing_preemphasis(mtk_dp, lane_count, lane_adjust);
+
+		dptx_link_train_channel_eq_delay(mtk_dp->rx_cap);
+
+		/* check link status from sink device */
+		drm_dp_dpcd_read_link_status(mtk_dp, link_status);
+		if (dptx_channel_eq_ok(link_status, lane_count)) {
+			printk(BIOS_DEBUG, "Link train EQ pass\n");
+
+			/* Training done, and disable pattern. */
+			buff = DP_TRAINING_PATTERN_DISABLE;
+			dptx_auxwrite_dpcd(mtk_dp, DP_AUX_NATIVE_WRITE, DPCD_00102, 0x1, &buff);
+			mtk_edp_pattern(mtk_dp, lane_count, DPTX_PATTERN_UNKNOWN);
+			return 0;
+		}
+		printk(BIOS_INFO, "Link train EQ fail retry:%d\n", train_retries);
+	} while (train_retries < MTK_DP_TRAIN_DOWNSCALE_RETRY);
+
+	/* Failed to train EQ, and disable pattern. */
+	buff = DP_TRAINING_PATTERN_DISABLE;
+	dptx_auxwrite_dpcd(mtk_dp, DP_AUX_NATIVE_WRITE, DPCD_00102, 0x1, &buff);
+	mtk_edp_pattern(mtk_dp, lane_count, DPTX_PATTERN_UNKNOWN);
+
+	return DPTX_TIMEOUT;
+}
+
+static int dptx_set_trainingstart(struct mtk_dp *mtk_dp)
+{
+	u8 lanecount;
+	u8 linkrate;
+	u8 buffer;
+	u8 train_limit;
+	u8 max_linkrate;
+	int ret;
+
+	buffer = 0x1;
+	dptx_auxwrite_dpcd(mtk_dp, DP_AUX_NATIVE_WRITE, DPCD_00600, 0x1, &buffer);
+
+	linkrate = mtk_dp->rx_cap[1];
+	lanecount = mtk_dp->rx_cap[2] & 0x1F;
+
+	printk(BIOS_INFO, "RX support linkrate = %#x, lanecount = %#x\n", linkrate, lanecount);
+
+	if (mtk_dp->train_info.sink_extcap_en)
+		dptx_auxread_dpcd(mtk_dp, DP_AUX_NATIVE_READ, DPCD_02002, 0x1, &buffer);
+	else
+		dptx_auxread_dpcd(mtk_dp, DP_AUX_NATIVE_READ, DPCD_00200, 0x1, &buffer);
+
+	if ((buffer & 0xBF) != 0)
+		mtk_dp->train_info.sink_count_num = buffer & 0xBF;
+
+	dptx_hal_setscramble(mtk_dp, false);
+	switch (linkrate) {
+	case DP_LINKRATE_RBR:
+	case DP_LINKRATE_HBR:
+	case DP_LINKRATE_HBR2:
+	case DP_LINKRATE_HBR25:
+	case DP_LINKRATE_HBR3:
+		break;
+	default:
+		mtk_dp->train_info.linkrate = DP_LINKRATE_HBR3;
+		break;
+	};
+
+	max_linkrate = linkrate;
+	printk(BIOS_INFO, "[eDPTX] linkrate = %#x, lanecount = %#x\n", linkrate, lanecount);
+	for (train_limit = 6; train_limit > 0; train_limit--) {
+		dptx_training_changemode(mtk_dp);
+
+		mtk_edp_train_setting(mtk_dp, linkrate, lanecount);
+		ret = mtk_edp_train_cr(mtk_dp, lanecount);
+		if (ret == DPTX_TRANING_FAIL) {
+			return ret;
+		} else if (ret) {
+			/* Reduce link rate */
+			switch (linkrate) {
+			case DP_LINKRATE_RBR:
+				lanecount = lanecount / 2;
+				linkrate = max_linkrate;
+
+				if (lanecount == 0)
+					return DPTX_TRANING_FAIL;
+				break;
+			case DP_LINKRATE_HBR:
+				linkrate = DP_LINKRATE_RBR;
+				break;
+			case DP_LINKRATE_HBR2:
+				linkrate = DP_LINKRATE_HBR;
+				break;
+			case DP_LINKRATE_HBR3:
+				linkrate = DP_LINKRATE_HBR2;
+				break;
+			default:
+				return DPTX_TRANING_FAIL;
+			}
+			continue;
+		}
+
+		ret = mtk_edp_train_eq(mtk_dp, lanecount);
+		if (ret == DPTX_TIMEOUT) {
+			return DPTX_TIMEOUT;
+		} else if (ret) {
+			/* Reduce lane count */
+			if (lanecount == DP_LANECOUNT_4)
+				lanecount = DP_LANECOUNT_2;
+			else if (lanecount == DP_LANECOUNT_2)
+				lanecount = DP_LANECOUNT_1;
+			else
+				return DPTX_TRANING_FAIL;
+			continue;
+		}
+		printk(BIOS_INFO, "[eDPTX] EQ training pass\n");
+		/* If we reach here, training is done. */
+		break;
+	}
+
+	if (train_limit == 0)
+		return DPTX_TRANING_FAIL;
+
+	mtk_dp->train_info.linkrate = linkrate;
+	mtk_dp->train_info.linklane_count = lanecount;
+	/*
+	 * After training done, we need to output normal stream instead of TPS,
+	 * so we need to enable scramble.
+	 */
+	dptx_hal_setscramble(mtk_dp, true);
+	dptx_hal_set_ef_mode(mtk_dp, ENABLE_DPTX_EF_MODE);
+
+	printk(BIOS_INFO, "%s: done\n", __func__);
+
+	return DPTX_PASS;
+}
+
+static void dptx_init_port(struct mtk_dp *mtk_dp)
+{
+	dptx_hal_phy_setidlepattern(mtk_dp, true);
+	dptx_hal_init_setting(mtk_dp);
+	dptx_hal_aux_setting(mtk_dp);
+	dptx_hal_digital_setting(mtk_dp);
+	dptx_hal_phy_init(mtk_dp);
+	dptx_hal_phy_setting(mtk_dp);
+	dptx_hal_hpd_detect_setting(mtk_dp);
+
+	dptx_hal_digital_swreset(mtk_dp);
+
+	dptx_hal_analog_power_en(mtk_dp, true);
+	dptx_hal_hpd_int_en(mtk_dp, true);
+}
+
+int mtk_edp_init(struct mtk_dp *mtk_dp, struct edid *edid)
+{
+	dptx_set_tx_power_con();
+	dptx_set_26mhz_clock();
+	udelay(50);
+	dptx_init_variable(mtk_dp);
+	dptx_init_port(mtk_dp);
+
+	if (!dptx_hal_hpd_high(mtk_dp)) {
+		printk(BIOS_ERR, "HPD is low\n");
+		return -1;
+	}
+
+	dptx_check_sinkcap(mtk_dp);
+
+	if (dptx_get_edid(mtk_dp, edid) != 0) {
+		printk(BIOS_ERR, "Failed to get EDID\n");
+		return -1;
+	}
+
+	if (dptx_set_trainingstart(mtk_dp) != DPTX_PASS) {
+		printk(BIOS_ERR, "%s: Failed to set training start\n", __func__);
+		return -1;
+	}
+
+	dp_intf_config(edid);
+	dptx_video_config(mtk_dp);
+
+	return 0;
+}
+
+int mtk_edp_enable(struct mtk_dp *mtk_dp)
+{
+	if (!mtk_dp) {
+		printk(BIOS_ERR, "%s: eDP is not initialized\n", __func__);
+		return -1;
+	}
+	dptx_video_enable(mtk_dp, true);
+	return 0;
+}
diff --git a/src/soc/mediatek/common/dp/include/soc/dp_intf_common.h b/src/soc/mediatek/common/dp/include/soc/dp_intf_v1.h
similarity index 97%
rename from src/soc/mediatek/common/dp/include/soc/dp_intf_common.h
rename to src/soc/mediatek/common/dp/include/soc/dp_intf_v1.h
index fceeb6d2f3..18f7c76c9e 100644
--- a/src/soc/mediatek/common/dp/include/soc/dp_intf_common.h
+++ b/src/soc/mediatek/common/dp/include/soc/dp_intf_v1.h
@@ -1,7 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
-#ifndef SOC_MEDIATEK_COMMON_DP_DP_INTF_COMMON_H
-#define SOC_MEDIATEK_COMMON_DP_DP_INTF_COMMON_H
+#ifndef SOC_MEDIATEK_COMMON_DP_DP_INTF_V1_H
+#define SOC_MEDIATEK_COMMON_DP_DP_INTF_V1_H
 
 #include <edid.h>
 #include <types.h>
@@ -264,4 +264,4 @@ extern const struct mtk_dpintf dpintf_data;
 
 void dp_intf_config(const struct edid *edid);
 
-#endif /* SOC_MEDIATEK_COMMON_DP_DP_INTF_COMMON_H */
+#endif /* SOC_MEDIATEK_COMMON_DP_DP_INTF_V1_H */
diff --git a/src/soc/mediatek/common/dp/include/soc/dp_intf_v2.h b/src/soc/mediatek/common/dp/include/soc/dp_intf_v2.h
new file mode 100644
index 0000000000..293d5ead7a
--- /dev/null
+++ b/src/soc/mediatek/common/dp/include/soc/dp_intf_v2.h
@@ -0,0 +1,208 @@
+/* SPDX-License-Identifier: GPL-2.0-only OR MIT */
+
+#ifndef SOC_MEDIATEK_COMMON_DP_DP_INTF_V2_H
+#define SOC_MEDIATEK_COMMON_DP_DP_INTF_V2_H
+
+#include <edid.h>
+#include <soc/addressmap.h>
+#include <types.h>
+
+#define DVO_EN		0x00
+#define EN		BIT(0)
+#define DVO_FORCE_ON	BIT(4)
+#define LINK_OFF	BIT(8)
+
+#define MMSYS1_CG_CLR0		0x108
+#define MMSYS1_CG_CLR1		0x118
+#define DISP_EDPTX_PWR_CON	0x74
+
+#define DVO_RET		0x04
+#define SWRST		BIT(0)
+#define SWRST_SEL	BIT(4)
+
+#define DVO_INTEN		0x08
+#define INT_VFP_START_EN	BIT(0)
+#define INT_VSYNC_START_EN	BIT(1)
+#define INT_VSYNC_END_EN	BIT(2)
+#define INT_VDE_START_EN	BIT(3)
+#define INT_VDE_END_EN		BIT(4)
+#define INT_WR_INFOQ_REG_EN	BIT(5)
+#define INT_TARGET_LINE0_EN	BIT(6)
+#define INT_TARGET_LINE1_EN	BIT(7)
+#define INT_TARGET_LINE2_EN	BIT(8)
+#define INT_TARGET_LINE3_EN	BIT(9)
+#define INT_WR_INFOQ_START_EN	BIT(10)
+#define INT_WR_INFOQ_END_EN	BIT(11)
+#define EXT_VSYNC_START_EN	BIT(12)
+#define EXT_VSYNC_END_EN	BIT(13)
+#define EXT_VDE_START_EN	BIT(14)
+#define EXT_VDE_END_EN		BIT(15)
+#define EXT_VBLANK_END_EN	BIT(16)
+#define UNDERFLOW_EN		BIT(17)
+#define INFOQ_ABORT_EN		BIT(18)
+
+#define DVO_INTSTA		0x0C
+#define INT_VFP_START_STA	BIT(0)
+#define INT_VSYNC_START_STA	BIT(1)
+#define INT_VSYNC_END_STA	BIT(2)
+#define INT_VDE_START_STA	BIT(3)
+#define INT_VDE_END_STA		BIT(4)
+#define INT_WR_INFOQ_REG_STA	BIT(5)
+#define INT_TARGET_LINE0_STA	BIT(6)
+#define INT_TARGET_LINE1_STA	BIT(7)
+#define INT_TARGET_LINE2_STA	BIT(8)
+#define INT_TARGET_LINE3_STA	BIT(9)
+#define INT_WR_INFOQ_START_STA	BIT(10)
+#define INT_WR_INFOQ_END_STA	BIT(11)
+#define EXT_VSYNC_START_STA	BIT(12)
+#define EXT_VSYNC_END_STA	BIT(13)
+#define EXT_VDE_START_STA	BIT(14)
+#define EXT_VDE_END_STA		BIT(15)
+#define EXT_VBLANK_END_STA	BIT(16)
+#define INT_UNDERFLOW_STA	BIT(17)
+#define INFOQ_ABORT_STA		BIT(18)
+
+#define DVO_CON		0x10
+#define INTL_EN		BIT(0)
+
+#define DVO_OUTPUT_SET	0x18
+#define OUT_NP_SEL	(0x3 <<	0)
+
+#define BIT_SWAP	BIT(4)
+#define CH_SWAP_MASK	(0x7 << 5)
+#define SWAP_RGB	0x00
+#define SWAP_GBR	0x01
+#define SWAP_BRG	0x02
+#define SWAP_RBG	0x03
+#define SWAP_GRB	0x04
+#define SWAP_BGR	0x05
+#define PXL_SWAP	BIT(8)
+#define R_MASK		BIT(12)
+#define G_MASK		BIT(13)
+#define B_MASK		BIT(14)
+#define DE_MASK		BIT(16)
+#define HS_MASK		BIT(17)
+#define VS_MASK		BIT(18)
+#define HS_INV		BIT(19)
+#define VS_INV		BIT(20)
+
+#define DVO_SRC_SIZE	0x20
+#define SRC_HSIZE_SHIFT	0
+#define SRC_HSIZE_MASK	(0xFFFF << 0)
+#define SRC_VSIZE_SHIFT	16
+#define SRC_VSIZE_MASK	(0xFFFF << 16)
+
+#define DVO_PIC_SIZE	0x24
+#define PIC_HSIZE_SHIFT	0
+#define PIC_HSIZE_MASK	(0xFFFF << 0)
+#define PIC_VSIZE_SHIFT	16
+#define PIC_VSIZE_MASK	(0xFFFF << 16)
+
+#define DVO_TGEN_H0	0x50
+#define HFP_SHIFT	0
+#define HFP_MASK	(0xFFFF << 0)
+#define HSYNC_SHIFT	16
+#define HSYNC_MASK	(0xFFFF << 16)
+
+#define DVO_TGEN_H1	0x54
+#define HSYNC2ACT_SHIFT	0
+#define HSYNC2ACT_MASK	(0xFFFF << 0)
+#define HACT_SHIFT	16
+#define HACT_MASK	(0xFFFF << 16)
+
+#define DVO_TGEN_V0	0x58
+#define VFP_SHIFT	0
+#define VFP_MASK	(0xFFFF << 0)
+#define VSYNC_SHIFT	16
+#define VSYNC_MASK	(0xFFFF << 16)
+
+#define DVO_TGEN_V1	0x5C
+#define VSYNC2ACT_SHIFT	0
+#define VSYNC2ACT_MASK	(0xFFFF << 0)
+#define VACT_SHIFT	16
+#define VACT_MASK	(0xFFFF << 16)
+
+#define DVO_TGEN_INFOQ_LATENCY		0x80
+#define INFOQ_START_LATENCY		0
+#define INFOQ_START_LATENCY_MASK	(0xFFFF << 0)
+#define INFOQ_END_LATENCY		16
+#define INFOQ_END_LATENCY_MASK		(0xFFFF << 16)
+
+#define DVO_BUF_CON0			0x220
+#define DISP_BUF_EN			BIT(0)
+#define FIFO_UNDERFLOW_DONE_BLOCK	BIT(4)
+
+#define DVO_TGEN_V_LAST_TRAILING_BLANK	0x6C
+#define V_LAST_TRAILING_BLANK		0
+#define V_LAST_TRAILING_BLANK_MASK	(0xFFFF << 0)
+
+#define DVO_TGEN_OUTPUT_DELAY_LINE	0x7C
+#define EXT_TG_DLY_LINE			0
+#define EXT_TG_DLY_LINE_MASK		(0xFFFF << 0)
+
+#define DVO_PATTERN_CTRL	0x100
+#define PRE_PAT_EN		BIT(0)
+#define PRE_PAT_SEL_MASK	(0x7 << 4)
+#define COLOR_BAR		(0x4 << 4)
+#define PRE_PAT_FORCE_ON	BIT(8)
+
+#define DVO_PATTERN_COLOR	0x104
+#define PAT_R			(0x3FF << 0)
+#define PAT_G			(0x3FF << 10)
+#define PAT_B			(0x3FF << 20)
+
+#define DVO_SHADOW_CTRL	0x190
+#define FORCE_COMMIT	BIT(0)
+#define BYPASS_SHADOW	BIT(1)
+#define READ_WRK_REG	BIT(2)
+
+#define DVO_SIZE	0x18
+#define DVO_TGEN_VWIDTH	0x28
+#define DVO_TGEN_VPORCH	0x2C
+#define DVO_TGEN_HPORCH	0x24
+#define DVO_TGEN_HWIDTH	0x20
+
+#define DVO_BUF_SODI_HIGHT	0x230
+#define DVO_BUF_SODI_LOW	0x234
+
+enum mtk_dvo_golden_setting_level {
+	MTK_DVO_FHD_60FPS_1920 = 0,
+	MTK_DVO_FHD_60FPS_2180,
+	MTK_DVO_FHD_60FPS_2400,
+	MTK_DVO_FHD_60FPS_2520,
+	MTK_DVO_FHD_90FPS,
+	MTK_DVO_FHD_120FPS,
+	MTK_DVO_WQHD_60FPS,
+	MTK_DVO_WQHD_120FPS,
+	MTK_DVO_8K_30FPS,
+	MTK_DVO_GSL_MAX,
+};
+
+struct mtk_dvo_gs_info {
+	u32 dvo_buf_sodi_high;
+	u32 dvo_buf_sodi_low;
+};
+
+enum TVDPLL_CLK {
+	TVDPLL_PLL = 0,
+	TVDPLL_D16 = 1,
+	TVDPLL_D8 = 2,
+	TVDPLL_D4 = 3,
+};
+
+struct mtk_dvo {
+	void *regs;
+	void *regs_ck;
+	void *regs_mm;
+	enum mtk_dvo_golden_setting_level gs_level;
+};
+
+struct mtk_dvo_sync_param {
+	u32 sync_width;
+	u32 front_porch;
+	u32 back_porch;
+};
+
+void dp_intf_config(const struct edid *edid);
+
+#endif /* SOC_MEDIATEK_COMMON_DP_DP_INTF__V2_H */
diff --git a/src/soc/mediatek/common/dp/include/soc/dptx_common.h b/src/soc/mediatek/common/dp/include/soc/dptx_common.h
index af8c9dce6d..8f4f8e0011 100644
--- a/src/soc/mediatek/common/dp/include/soc/dptx_common.h
+++ b/src/soc/mediatek/common/dp/include/soc/dptx_common.h
@@ -3,6 +3,8 @@
 #ifndef SOC_MEDIATEK_COMMON_DP_DPTX_COMMON_H
 #define SOC_MEDIATEK_COMMON_DP_DPTX_COMMON_H
 
+#include <types.h>
+
 #define DP_LANSE_ADJUST_SIZE		2
 #define DPTX_TBC_BUF_READSTARTADRTHRD	0x08
 #define ENABLE_DPTX_EF_MODE		0x1
@@ -218,6 +220,8 @@ struct mtk_dp {
 int mtk_edp_init(struct mtk_dp *mtk_dp, struct edid *edid);
 int mtk_edp_enable(struct mtk_dp *mtk_dp);
 
+void dptx_set_tx_power_con(void);
+void dptx_set_26mhz_clock(void);
 bool dptx_auxread_dpcd(struct mtk_dp *mtk_dp, u8 cmd, u32 dpcd_addr,
 		       size_t length, u8 *rxbuf);
 bool dptx_auxwrite_dpcd(struct mtk_dp *mtk_dp, u8 cmd, u32 dpcd_addr,
diff --git a/src/soc/mediatek/common/dp/include/soc/dptx_hal_v1.h b/src/soc/mediatek/common/dp/include/soc/dptx_hal_v1.h
new file mode 100644
index 0000000000..5537376809
--- /dev/null
+++ b/src/soc/mediatek/common/dp/include/soc/dptx_hal_v1.h
@@ -0,0 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef SOC_MEDIATEK_COMMON_DP_DPTX_HAL_V1_H
+#define SOC_MEDIATEK_COMMON_DP_DPTX_HAL_V1_H
+
+#include <soc/dptx_hal_common.h>
+
+#endif /* SOC_MEDIATEK_COMMON_DP_DPTX_HAL_V1_H */
diff --git a/src/soc/mediatek/common/dp/include/soc/dptx_hal_v2.h b/src/soc/mediatek/common/dp/include/soc/dptx_hal_v2.h
new file mode 100644
index 0000000000..e076915e92
--- /dev/null
+++ b/src/soc/mediatek/common/dp/include/soc/dptx_hal_v2.h
@@ -0,0 +1,30 @@
+/* SPDX-License-Identifier: GPL-2.0-only OR MIT */
+
+#ifndef SOC_MEDIATEK_COMMON_DP_DPTX_HAL_V2_H
+#define SOC_MEDIATEK_COMMON_DP_DPTX_HAL_V2_H
+
+#include <soc/dptx_hal_common.h>
+
+#define MTK_DP_TRAIN_VOLTAGE_LEVEL_RETRY	5
+#define MTK_DP_TRAIN_DOWNSCALE_RETRY		10
+
+enum {
+	DPTX_PATTERN_TPS1 = 1,
+	DPTX_PATTERN_TPS2,
+	DPTX_PATTERN_TPS3,
+	DPTX_PATTERN_TPS4,
+	DPTX_PATTERN_UNKNOWN,
+};
+
+extern const int dptx_hal_driving_offset[];
+extern const int dptx_hal_driving_offset_size;
+
+void dptx_hal_swing_emp_reset(struct mtk_dp *mtk_dp);
+void dptx_hal_phy_init(struct mtk_dp *mtk_dp);
+void dptx_hal_phy_wait_aux_ldo_ready(struct mtk_dp *mtk_dp);
+void dptx_hal_phy_set_idle_pattern(struct mtk_dp *mtk_dp, u8 lane_count, bool enable);
+void dptx_hal_phy_set_lanes(struct mtk_dp *mtk_dp, u8 lane_count);
+void dptx_hal_phy_set_swing_preemphasis(struct mtk_dp *mtk_dp, u8 lane_count, u8 *swing_val,
+					u8 *preemphasis);
+
+#endif /* SOC_MEDIATEK_COMMON_DP_DPTX_HAL_V2_H */
diff --git a/src/soc/mediatek/common/dp/include/soc/dptx_reg_v1.h b/src/soc/mediatek/common/dp/include/soc/dptx_reg_v1.h
new file mode 100644
index 0000000000..6217bfd7ea
--- /dev/null
+++ b/src/soc/mediatek/common/dp/include/soc/dptx_reg_v1.h
@@ -0,0 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef SOC_MEDIATEK_COMMON_DP_DPTX_REG_V1_H
+#define SOC_MEDIATEK_COMMON_DP_DPTX_REG_V1_H
+
+#include <soc/dptx_reg_common.h>
+
+#endif /* SOC_MEDIATEK_COMMON_DP_DPTX_REG_V1_H */
diff --git a/src/soc/mediatek/common/dp/include/soc/dptx_reg_v2.h b/src/soc/mediatek/common/dp/include/soc/dptx_reg_v2.h
new file mode 100644
index 0000000000..762295d25e
--- /dev/null
+++ b/src/soc/mediatek/common/dp/include/soc/dptx_reg_v2.h
@@ -0,0 +1,210 @@
+/* SPDX-License-Identifier: GPL-2.0-only OR MIT */
+
+#ifndef SOC_MEDIATEK_COMMON_DP_DPTX_REG_V2_H
+#define SOC_MEDIATEK_COMMON_DP_DPTX_REG_V2_H
+
+#include <soc/dptx_reg_common.h>
+
+#define WAIT_AUX_READY_RETRY_TIMES			5
+#define PHYD_DIG_GLB_OFFSET				0x1400
+#define SEC_OFFSET					0x4000
+#define IPMUX_CONTROL					(PHYD_DIG_GLB_OFFSET + 0x98)
+#define EDPTX_DSI_PHYD_SEL_FLDMASK			0x1
+#define EDPTX_DSI_PHYD_SEL_FLDMASK_POS			0
+#define TOP_OFFSET					0x2000
+#define MTK_DP_TOP_IRQ_MASK				0x202C
+#define ENCODER_IRQ_MSK					BIT(0)
+#define TRANS_IRQ_MSK					BIT(1)
+#define EDP_TX_TOP_CLKGEN_0				0x2074
+#define DP_PHY_DIG_PLL_CTL_1				0x1414
+#define DP_PHY_DIG_SW_RST				0x1438
+#define RGS_BG_CORE_EN_READY_MASK			BIT(0)
+#define REG_2004_TOP_SWING_EMP				0x2004
+#define DP_TX0_VOLT_SWING_MASK				GENMASK(1, 0)
+#define DP_TX0_PRE_EMPH_MASK				GENMASK(3, 2)
+#define DP_TX1_VOLT_SWING_MASK				GENMASK(9, 8)
+#define DP_TX1_PRE_EMPH_MASK				GENMASK(11, 10)
+#define DP_TX2_VOLT_SWING_MASK				GENMASK(17, 16)
+#define DP_TX2_PRE_EMPH_MASK				GENMASK(19, 18)
+#define DP_TX3_VOLT_SWING_MASK				GENMASK(25, 24)
+#define DP_TX3_PRE_EMPH_MASK				GENMASK(27, 26)
+#define REG_3000_DP_ENCODER0_P0				0x3000
+#define REG_BS_SYMBOL_CNT_RESET				BIT(7)
+#define REG_3004_DP_ENCODER0_P0				0x3004
+#define DP_TX_ENCODER_4P_RESET_SW_DP_ENC0_P0		BIT(9)
+#define REG_3008_DP_ENCODER0_P0				0x3008
+#define REG_300C_DP_ENCODER0_P0				0x300C
+#define REG_3010_DP_ENCODER0_P0				0x3010
+#define REG_3014_DP_ENCODER0_P0				0x3014
+#define REG_3018_DP_ENCODER0_P0				0x3018
+#define REG_301C_DP_ENCODER0_P0				0x301C
+#define REG_3020_DP_ENCODER0_P0				0x3020
+#define REG_3024_DP_ENCODER0_P0				0x3024
+#define REG_3028_DP_ENCODER0_P0				0x3028
+#define HSP_SW_DP_ENCODER0_P0_FLDMASK			0x8000
+#define HSP_SW_DP_ENCODER0_P0_FLDMASK_POS		15
+#define REG_302C_DP_ENCODER0_P0				0x302C
+#define REG_3030_DP_ENCODER0_P0				0x3030
+#define REG_3034_DP_ENCODER0_P0				0x3034
+#define DP_TEST_COLOR_FORMAT_MASK			(3 << 1)
+#define DP_TEST_COLOR_FORMAT_SHIFT			1
+#define REG_303C_DP_ENCODER0_P0				0x303C
+#define REG_3040_DP_ENCODER0_P0				0x3040
+#define REG_3044_DP_ENCODER0_P0				0x3044
+#define REG_3048_DP_ENCODER0_P0				0x3048
+#define REG_304C_DP_ENCODER0_P0				0x304C
+#define VBID_VIDEO_MUTE_DP_ENC0_4P_MASK			BIT(2)
+#define REG_3050_DP_ENCODER0_P0				0x3050
+#define REG_3054_DP_ENCODER0_P0				0x3054
+#define REG_3064_DP_ENCODER0_P0				0x3064
+#define REG_3154_DP_ENCODER0_P0				0x3154
+#define REG_3158_DP_ENCODER0_P0				0x3158
+#define REG_315C_DP_ENCODER0_P0				0x315C
+#define REG_3160_DP_ENCODER0_P0				0x3160
+#define REG_3164_DP_ENCODER0_P0				0x3164
+#define REG_3168_DP_ENCODER0_P0				0x3168
+#define REG_316C_DP_ENCODER0_P0				0x316C
+#define REG_3170_DP_ENCODER0_P0				0x3170
+#define REG_3174_DP_ENCODER0_P0				0x3174
+#define REG_3178_DP_ENCODER0_P0				0x3178
+#define REG_31EC_DP_ENCODER0_P0				0x31EC
+#define REG_3300_DP_ENCODER1_P0				0x3300
+#define REG_3364_DP_ENCODER1_P0				0x3364
+#define REG_3368_DP_ENCODER1_P0				0x3368
+#define BS2BS_MODE_DP_ENC1_4P_VAL			1
+#define BS2BS_MODE_DP_ENCODER1_P0_FLDMASK		0x3000
+#define DP_I_MODE_ENABLE				BIT(6)
+#define REG_33C0_DP_ENCODER1_P0				0x33C0
+#define REG_33C4_DP_ENCODER1_P0				0x33C4
+#define REG_33C8_DP_ENCODER1_P0				0x33C8
+#define REG_3400_DP_TRANS_P0				0x3400
+#define PATTERN1_EN_DP_TRANS_4P_TPS1			BIT(12)
+#define PATTERN2_EN_DP_TRANS_4P_TPS2			BIT(13)
+#define PATTERN3_EN_DP_TRANS_4P_TPS3			BIT(14)
+#define PATTERN4_EN_DP_TRANS_4P_TPS4			BIT(15)
+#define PATTERN_EN_DP_TRANS_4P_MASK			GENMASK(15, 12)
+#define REG_3404_DP_TRANS_P0				0x3404
+#define REG_340C_DP_TRANS_P0				0x340C
+#define REG_3418_DP_TRANS_P0				0x3418
+#define REG_342C_DP_TRANS_P0				0x342C
+#define REG_34A4_DP_TRANS_P0				0x34A4
+#define REG_3540_DP_TRANS_P0				0x3540
+#define REG_3580_DP_TRANS_P0				0x3580
+#define POST_MISC_DATA_LANE0_OV_DP_TRANS_4P_MASK	BIT(8)
+#define POST_MISC_DATA_LANE1_OV_DP_TRANS_4P_MASK	BIT(9)
+#define POST_MISC_DATA_LANE2_OV_DP_TRANS_4P_MASK	BIT(10)
+#define POST_MISC_DATA_LANE3_OV_DP_TRANS_4P_MASK	BIT(11)
+#define POST_MISC_DATA_LANE_OV_DP_TRANS_4P_MASK		GENMASK(11, 8)
+#define REG_35F0_DP_TRANS_P0				0x35F0
+#define REG_360C_AUX_TX_P0				0x360C
+#define REG_3614_AUX_TX_P0				0x3614
+#define AUX_RX_UI_CNT_THR_AUX_FOR_26M			13
+#define REG_3618_AUX_TX_P0				0x3618
+#define AUX_RX_FIFO_FULL_AUX_TX_P0_FLDMASK		0x200
+#define REG_3620_AUX_TX_P0				0x3620
+#define AUX_RD_MODE_AUX_TX_P0_FLDMASK			0x200
+#define AUX_RD_MODE_AUX_TX_P0_FLDMASK_POS		9
+#define AUX_RX_FIFO_READ_PULSE_TX_P0_FLDMASK		0x100
+#define AUX_RX_FIFO_R_PULSE_TX_P0_FLDMASK_POS		8
+#define REG_3624_AUX_TX_P0				0x3624
+#define REG_3628_AUX_TX_P0				0x3628
+#define REG_362C_AUX_TX_P0				0x362C
+#define AUX_NO_LENGTH_AUX_TX_P0_FLDMASK			0x1
+#define AUX_NO_LENGTH_AUX_TX_P0_FLDMASK_POS		0
+#define REG_3630_AUX_TX_P0				0x3630
+#define AUX_TX_REQUEST_READY_AUX_TX_P0_FLDMASK		0x8
+#define AUX_TX_REQUEST_READY_AUX_TX_P0_FLDMASK_POS	3
+#define REG_3634_AUX_TX_P0				0x3634
+#define AUX_TX_OVER_SAMPLE_RATE_FOR_26M			25
+#define REG_3640_AUX_TX_P0				0x3640
+#define AUX_RX_RECV_COMPLETE_IRQ_TX_P0_FLDMASK		0x40
+#define AUX_400US_TIMEOUT_IRQ_AUX_TX_P0_FLDMASK		0x1
+#define REG_3644_AUX_TX_P0				0x3644
+#define REG_3648_AUX_TX_P0				0x3648
+#define REG_364C_AUX_TX_P0				0x364C
+#define HPD_INT_THD_FLDMASK_VAL				0x32
+#define HPD_INT_THD_FLDMASK				0x3F0
+#define REG_3650_AUX_TX_P0				0x3650
+#define MCU_REQUEST_DATA_NUM_AUX_TX_P0_FLDMASK		0xf000
+#define MCU_REQ_DATA_NUM_AUX_TX_P0_FLDMASK_POS		12
+#define MCU_ACK_TRANSACTION_COMPLETE_AUX_TX_P0_FLDMASK	0x100
+#define MCU_ACK_TRAN_COMPLETE_AUX_TX_P0_FLDMASK_POS	8
+#define REG_3658_AUX_TX_P0				0x3658
+#define REG_366C_AUX_TX_P0				0x366C
+#define XTAL_FREQ_DP_TX_AUX_366C_VALUE			0x68
+#define XTAL_FREQ_DP_TX_AUX_366C_MASK			0xFF00
+#define REG_367C_AUX_TX_P0				0x367C
+#define HPD_CONN_THD_AUX_TX_P0_FLDMASK_POS		5
+#define HPD_CONN_THD_AUX_TX_P0_FLDMASK			0x3c0
+#define REG_3690_AUX_TX_P0				0x3690
+#define RX_REPLY_COMPLETE_MODE_AUX_TX_4P		BIT(8)
+#define REG_36A0_AUX_TX_4P				0x36A0
+#define REG_3704_AUX_TX_P0				0x3704
+#define AUX_TX_FIFO_WRITE_DATA_TOGGLE_AUX_TX_P0_FLDMASK 0x2
+#define AUX_TX_FIFO_NEW_MODE_EN_AUX_TX_P0_FLDMASK	0x4
+#define AUX_TX_FIFO_NEW_MODE_EN_AUX_TX_P0_FLDMASK_POS	2
+#define REG_3708_AUX_TX_P0				0x3708
+#define REG_37A0_AUX_TX_P0				0x37A0
+#define HPD_DISC_THD_AUX_TX_P0_FLDMASK_POS		5
+#define HPD_DISC_THD_AUX_TX_P0_FLDMASK			0xF0
+#define REG_37C8_AUX_TX_P0				0x37C8
+#define MTK_ATOP_EN_AUX_TX_4P				BIT(0)
+#define REG_3F04_DP_ENC_4P_3				0x3F04
+#define REG_3F08_DP_ENC_4P_3				0x3F08
+#define REG_3F0C_DP_ENC_4P_3				0x3F0C
+#define REG_3F10_DP_ENC_4P_3				0x3F10
+#define REG_3F28_DP_ENC_4P_3				0x3F28
+#define REG_3F44_DP_ENC_4P_3				0x3F44
+#define PHY_PWR_STATE_OW_EN_DP_ENC_4P_3			BIT(2)
+#define PHY_PWR_STATE_OW_EN_DP_ENC_4P_3_MASK		BIT(2)
+#define BIAS_POWER_ON					(0x01 << 3)
+#define PHY_PWR_STATE_OW_VALUE_DP_ENC_4P_3_MASK		GENMASK(4, 3)
+#define REG_3F80_DP_ENC_4P_3				0x3F80
+#define PSR_PATGEN_AVT_EN_FLDMASK			0x20
+#define REG_3FF8_DP_ENC_4P_3				0x3FF8
+#define PHY_STATE_W_1_DP_ENC_4P_3			BIT(6)
+#define PHY_STATE_W_1_DP_ENC_4P_3_MASK			BIT(6)
+#define DVO_ON_W_1_FLDMASK				0x20
+#define XTAL_FREQ_FOR_PSR_DP_ENC_4P_3_VALUE		25
+#define XTAL_FREQ_FOR_PSR_DP_ENC_4P_3_MASK		0x3E00
+#define PHYD_DIG_LAN0_OFFSET				0x1000
+#define PHYD_DIG_LAN1_OFFSET				0x1100
+#define PHYD_DIG_LAN2_OFFSET				0x1200
+#define PHYD_DIG_LAN3_OFFSET				0x1300
+#define EDP_TX_LN_VOLT_SWING_VAL_MASK			GENMASK(2, 1)
+#define EDP_TX_LN_VOLT_SWING_VAL_SHIFT			1
+#define DP_TX_TOP_APB_WSTRB				(TOP_OFFSET + 0x10)
+#define DP_TX_TOP_RESET_AND_PROBE			(TOP_OFFSET + 0x20)
+#define DP_TX_SECURE_REG11				(SEC_OFFSET + 0x2C)
+#define DP_LANE_COUNT_ENHANCED_FRAME_EN			(1 << 7)
+#define DPCD_00000					0x00000
+#define DPCD_0000E					0x0000E
+#define DPCD_00021					0x00021
+#define DPCD_00100					0x00100
+#define DPCD_00101					0x00101
+#define DPCD_00102					0x00102
+#define DP_TRAINING_PATTERN_DISABLE			0
+#define DP_TRAINING_PATTERN_1				1
+#define DP_TRAINING_PATTERN_2				2
+#define DP_TRAINING_PATTERN_3				3 /* 1.2 */
+#define DP_TRAINING_PATTERN_4				7 /* 1.4 */
+#define DP_LINK_SCRAMBLING_DISABLE			BIT(5)
+#define DPCD_00103					0x00103
+#define DP_TRAIN_VOLTAGE_SWING_SHIFT			0
+#define DP_TRAIN_MAX_SWING_REACHED			BIT(2)
+#define DP_TRAIN_PRE_EMPHASIS_SHIFT			3
+#define DP_TRAIN_MAX_PRE_EMPHASIS_REACHED		BIT(5)
+#define DPCD_00107					0x00107
+#define DP_SPREAD_AMP_0_5				BIT(4)
+#define DPCD_00200					0x00200
+#define DPCD_00202					0x00202
+#define DPCD_00206					0x00206
+#define DP_ADJUST_VOLTAGE_SWING_LANE0_MASK		0x03
+#define DP_ADJUST_PRE_EMPHASIS_LANE0_MASK		0x0C
+#define DP_ADJUST_PRE_EMPHASIS_LANE0_SHIFT		2
+#define DP_ADJUST_VOLTAGE_SWING_LANE1_SHIFT		4
+#define DPCD_00600					0x00600
+#define DPCD_02002					0x02002
+#define DPCD_02003					0x02003
+
+#endif /* SOC_MEDIATEK_COMMON_DP_DPTX_REG_V2_H */
diff --git a/src/soc/mediatek/mt8188/Makefile.mk b/src/soc/mediatek/mt8188/Makefile.mk
index 3c77664cfc..0cd05b94ce 100644
--- a/src/soc/mediatek/mt8188/Makefile.mk
+++ b/src/soc/mediatek/mt8188/Makefile.mk
@@ -39,8 +39,9 @@ ramstage-y += ../common/ddp.c ddp.c
 ramstage-y += ../common/devapc.c devapc.c
 ramstage-y += ../common/dfd.c
 ramstage-y += ../common/display.c
-ramstage-y += ../common/dp/dptx_common.c ../common/dp/dptx_hal_common.c
-ramstage-y += ../common/dp/dp_intf.c ../common/dp/dptx.c ../common/dp/dptx_hal.c dp_intf.c
+ramstage-y += ../common/dp/dp_intf_v1.c dp_intf.c
+ramstage-y += ../common/dp/dptx_common.c ../common/dp/dptx_v1.c
+ramstage-y += ../common/dp/dptx_hal_common.c ../common/dp/dptx_hal_v1.c
 ramstage-y += ../common/dpm.c
 ramstage-y += ../common/dpm_v1.c
 ramstage-$(CONFIG_DPM_FOUR_CHANNEL) += ../common/dpm_4ch.c
diff --git a/src/soc/mediatek/mt8188/include/soc/dp_intf.h b/src/soc/mediatek/mt8188/include/soc/dp_intf.h
index bb310c7a54..e8324a052a 100644
--- a/src/soc/mediatek/mt8188/include/soc/dp_intf.h
+++ b/src/soc/mediatek/mt8188/include/soc/dp_intf.h
@@ -3,6 +3,6 @@
 #ifndef __SOC_MEDIATEK_MT8188_INCLUDE_SOC_DP_INTF_H__
 #define __SOC_MEDIATEK_MT8188_INCLUDE_SOC_DP_INTF_H__
 
-#include <soc/dp_intf_common.h>
+#include <soc/dp_intf_v1.h>
 
 #endif /* __SOC_MEDIATEK_MT8188_INCLUDE_SOC_DP_INTF_H__ */
diff --git a/src/soc/mediatek/mt8188/include/soc/dptx_hal.h b/src/soc/mediatek/mt8188/include/soc/dptx_hal.h
index d6dcea60e6..f183d2a014 100644
--- a/src/soc/mediatek/mt8188/include/soc/dptx_hal.h
+++ b/src/soc/mediatek/mt8188/include/soc/dptx_hal.h
@@ -3,6 +3,6 @@
 #ifndef __SOC_MEDIATEK_MT8188_INCLUDE_SOC_DPTX_HAL_H__
 #define __SOC_MEDIATEK_MT8188_INCLUDE_SOC_DPTX_HAL_H__
 
-#include <soc/dptx_hal_common.h>
+#include <soc/dptx_hal_v1.h>
 
 #endif /* __SOC_MEDIATEK_MT8188_INCLUDE_SOC_DPTX_HAL_H__ */
diff --git a/src/soc/mediatek/mt8188/include/soc/dptx_reg.h b/src/soc/mediatek/mt8188/include/soc/dptx_reg.h
index 57cb853d0a..549321a4d7 100644
--- a/src/soc/mediatek/mt8188/include/soc/dptx_reg.h
+++ b/src/soc/mediatek/mt8188/include/soc/dptx_reg.h
@@ -3,6 +3,6 @@
 #ifndef __SOC_MEDIATEK_MT8188_INCLUDE_SOC_DPTX_REG_H__
 #define __SOC_MEDIATEK_MT8188_INCLUDE_SOC_DPTX_REG_H__
 
-#include <soc/dptx_reg_common.h>
+#include <soc/dptx_reg_v1.h>
 
 #endif /* __SOC_MEDIATEK_MT8188_INCLUDE_SOC_DPTX_REG_H__ */
diff --git a/src/soc/mediatek/mt8195/Makefile.mk b/src/soc/mediatek/mt8195/Makefile.mk
index b960f8955b..1f26419f02 100644
--- a/src/soc/mediatek/mt8195/Makefile.mk
+++ b/src/soc/mediatek/mt8195/Makefile.mk
@@ -51,8 +51,9 @@ ramstage-y += ../common/display.c
 ramstage-y += ../common/dpm.c
 ramstage-y += ../common/dpm_v1.c
 ramstage-$(CONFIG_DPM_FOUR_CHANNEL) += ../common/dpm_4ch.c
-ramstage-y += ../common/dp/dptx_common.c ../common/dp/dptx_hal_common.c
-ramstage-y += ../common/dp/dp_intf.c ../common/dp/dptx.c ../common/dp/dptx_hal.c dp_intf.c
+ramstage-y += ../common/dp/dp_intf_v1.c dp_intf.c
+ramstage-y += ../common/dp/dptx_common.c ../common/dp/dptx_v1.c
+ramstage-y += ../common/dp/dptx_hal_common.c ../common/dp/dptx_hal_v1.c
 ramstage-y += emi.c
 ramstage-y += hdmi.c
 ramstage-y += ../common/l2c_ops.c
diff --git a/src/soc/mediatek/mt8195/include/soc/dp_intf.h b/src/soc/mediatek/mt8195/include/soc/dp_intf.h
index d6a000f1b4..d49c79ff45 100644
--- a/src/soc/mediatek/mt8195/include/soc/dp_intf.h
+++ b/src/soc/mediatek/mt8195/include/soc/dp_intf.h
@@ -3,6 +3,6 @@
 #ifndef __SOC_MEDIATEK_MT8195_INCLUDE_SOC_DP_INTF_H__
 #define __SOC_MEDIATEK_MT8195_INCLUDE_SOC_DP_INTF_H__
 
-#include <soc/dp_intf_common.h>
+#include <soc/dp_intf_v1.h>
 
 #endif /* __SOC_MEDIATEK_MT8195_INCLUDE_SOC_DP_INTF_H__ */
diff --git a/src/soc/mediatek/mt8195/include/soc/dptx_hal.h b/src/soc/mediatek/mt8195/include/soc/dptx_hal.h
index 17dbf25389..6d95e3df16 100644
--- a/src/soc/mediatek/mt8195/include/soc/dptx_hal.h
+++ b/src/soc/mediatek/mt8195/include/soc/dptx_hal.h
@@ -3,6 +3,6 @@
 #ifndef __SOC_MEDIATEK_MT8195_INCLUDE_SOC_DPTX_HAL_H__
 #define __SOC_MEDIATEK_MT8195_INCLUDE_SOC_DPTX_HAL_H__
 
-#include <soc/dptx_hal_common.h>
+#include <soc/dptx_hal_v1.h>
 
 #endif /* __SOC_MEDIATEK_MT8195_INCLUDE_SOC_DPTX_HAL_H__ */
diff --git a/src/soc/mediatek/mt8195/include/soc/dptx_reg.h b/src/soc/mediatek/mt8195/include/soc/dptx_reg.h
index 9196005e0e..9a276df99b 100644
--- a/src/soc/mediatek/mt8195/include/soc/dptx_reg.h
+++ b/src/soc/mediatek/mt8195/include/soc/dptx_reg.h
@@ -3,6 +3,6 @@
 #ifndef __SOC_MEDIATEK_MT8195_INCLUDE_SOC_DPTX_REG_H__
 #define __SOC_MEDIATEK_MT8195_INCLUDE_SOC_DPTX_REG_H__
 
-#include <soc/dptx_reg_common.h>
+#include <soc/dptx_reg_v1.h>
 
 #endif /* __SOC_MEDIATEK_MT8195_INCLUDE_SOC_DPTX_REG_H__ */
diff --git a/src/soc/mediatek/mt8196/Makefile.mk b/src/soc/mediatek/mt8196/Makefile.mk
index 2e47a0e970..3d8e50baa7 100644
--- a/src/soc/mediatek/mt8196/Makefile.mk
+++ b/src/soc/mediatek/mt8196/Makefile.mk
@@ -60,8 +60,9 @@ ramstage-y += ddp.c
 ramstage-y += ../common/display.c
 ramstage-y += ../common/dpm.c
 ramstage-y += ../common/dpm_v2.c
-ramstage-y += ../common/dp/dptx_common.c ../common/dp/dptx_hal_common.c
-ramstage-y += dptx.c dptx_hal.c dp_intf.c
+ramstage-y += ../common/dp/dp_intf_v2.c
+ramstage-y += ../common/dp/dptx_common.c ../common/dp/dptx_v2.c dptx.c
+ramstage-y += ../common/dp/dptx_hal_common.c ../common/dp/dptx_hal_v2.c dptx_hal.c
 ramstage-y += ../common/dramc_info.c
 ramstage-y += ../common/early_init.c
 ramstage-y += ../common/emi.c
diff --git a/src/soc/mediatek/mt8196/dptx.c b/src/soc/mediatek/mt8196/dptx.c
index b892b1a562..115eb987fe 100644
--- a/src/soc/mediatek/mt8196/dptx.c
+++ b/src/soc/mediatek/mt8196/dptx.c
@@ -1,415 +1,17 @@
 /* SPDX-License-Identifier: GPL-2.0-only OR MIT */
 
-#include <assert.h>
-#include <commonlib/bsd/helpers.h>
-#include <console/console.h>
-#include <delay.h>
 #include <device/mmio.h>
-#include <edid.h>
 #include <soc/addressmap.h>
-#include <soc/dp_intf.h>
 #include <soc/dptx.h>
-#include <soc/dptx_hal.h>
-#include <soc/dptx_reg.h>
+#include <soc/dp_intf.h>
 
-static void mtk_edp_pattern(struct mtk_dp *mtk_dp, u8 lane_count, u8 pattern)
-{
-	u8 aux_offset;
-
-	switch (pattern) {
-	case DPTX_PATTERN_TPS1:
-		aux_offset = DP_TRAINING_PATTERN_1 | DP_LINK_SCRAMBLING_DISABLE;
-		dptx_hal_phy_set_idle_pattern(mtk_dp, lane_count, false);
-		mtk_dp_mask(mtk_dp, REG_3400_DP_TRANS_P0, PATTERN1_EN_DP_TRANS_4P_TPS1,
-			    PATTERN_EN_DP_TRANS_4P_MASK);
-		break;
-	case DPTX_PATTERN_TPS2:
-		aux_offset = DP_TRAINING_PATTERN_2 | DP_LINK_SCRAMBLING_DISABLE;
-		mtk_dp_mask(mtk_dp, REG_3400_DP_TRANS_P0, PATTERN2_EN_DP_TRANS_4P_TPS2,
-			    PATTERN_EN_DP_TRANS_4P_MASK);
-		break;
-	case DPTX_PATTERN_TPS3:
-		aux_offset = DP_TRAINING_PATTERN_3 | DP_LINK_SCRAMBLING_DISABLE;
-		mtk_dp_mask(mtk_dp, REG_3400_DP_TRANS_P0, PATTERN3_EN_DP_TRANS_4P_TPS3,
-			    PATTERN_EN_DP_TRANS_4P_MASK);
-		break;
-	case DPTX_PATTERN_TPS4:
-		aux_offset = DP_TRAINING_PATTERN_4;
-		mtk_dp_mask(mtk_dp, REG_3400_DP_TRANS_P0, PATTERN4_EN_DP_TRANS_4P_TPS4,
-			    PATTERN_EN_DP_TRANS_4P_MASK);
-		break;
-	case DPTX_PATTERN_UNKNOWN:
-	default:
-		printk(BIOS_ERR, "Set default or unknown pattern\n");
-		mtk_dp_mask(mtk_dp, REG_3400_DP_TRANS_P0, 0x0, PATTERN_EN_DP_TRANS_4P_MASK);
-		return;
-	}
-
-	dptx_auxwrite_dpcd(mtk_dp, DP_AUX_NATIVE_WRITE, DPCD_00102, 0x1, &aux_offset);
-}
-
-static void update_swing_preemphasis(struct mtk_dp *mtk_dp, u8 lane_count,
-				     u8 dpcd_adjust_req[DP_LANSE_ADJUST_SIZE])
-{
-	u8 swing_val[MAX_LANECOUNT];
-	u8 preemphasis[MAX_LANECOUNT];
-
-	for (int lane = 0; lane < lane_count; lane++) {
-		u8 val;
-		int index = lane / 2;
-		assert(index < DP_LANSE_ADJUST_SIZE);
-		int shift = lane % 2 ? DP_ADJUST_VOLTAGE_SWING_LANE1_SHIFT : 0;
-		u8 swing_value = dpcd_adjust_req[index] >> shift;
-
-		if (mtk_dp->force_max_swing) {
-			swing_val[lane] = DPTX_SWING3;
-			printk(BIOS_INFO, "%s: Force swing setting to %u (500 mV)\n",
-			       __func__, swing_val[lane]);
-		} else {
-			swing_val[lane] = swing_value & DP_ADJUST_VOLTAGE_SWING_LANE0_MASK;
-		}
-		preemphasis[lane] = swing_value & DP_ADJUST_PRE_EMPHASIS_LANE0_MASK;
-		preemphasis[lane] >>= DP_ADJUST_PRE_EMPHASIS_LANE0_SHIFT;
-		val = swing_val[lane] << DP_TRAIN_VOLTAGE_SWING_SHIFT |
-		      preemphasis[lane] << DP_TRAIN_PRE_EMPHASIS_SHIFT;
-
-		if (swing_val[lane] == DPTX_SWING3)
-			val |= DP_TRAIN_MAX_SWING_REACHED;
-		if (preemphasis[lane] == DPTX_PREEMPHASIS3)
-			val |= DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
-
-		dptx_auxwrite_dpcd(mtk_dp, DP_AUX_NATIVE_WRITE, DPCD_00103 + lane, 0x1, &val);
-	}
-
-	dptx_hal_phy_set_swing_preemphasis(mtk_dp, lane_count, swing_val, preemphasis);
-}
-
-static void dptx_training_changemode(struct mtk_dp *mtk_dp)
-{
-	dptx_hal_phyd_reset(mtk_dp);
-	dptx_hal_swing_emp_reset(mtk_dp);
-
-	mdelay(2);
-}
-
-static void mtk_edp_train_setting(struct mtk_dp *mtk_dp,
-				  u8 linkrate, u8 lanecount)
-{
-	u8 lanecount_enhanced_frame;
-	u8 dpcd_data;
-
-	lanecount_enhanced_frame = lanecount | DP_LANE_COUNT_ENHANCED_FRAME_EN;
-
-	dptx_auxwrite_dpcd(mtk_dp, DP_AUX_NATIVE_WRITE, DPCD_00100, 0x1, &linkrate);
-	dptx_auxwrite_dpcd(mtk_dp, DP_AUX_NATIVE_WRITE, DPCD_00101, 0x1,
-			   &lanecount_enhanced_frame);
-	if (mtk_dp->train_info.sink_ssc_en) {
-		dpcd_data = DP_SPREAD_AMP_0_5;
-		dptx_auxwrite_dpcd(mtk_dp, DP_AUX_NATIVE_WRITE, DPCD_00107, 0x1, &dpcd_data);
-		dptx_hal_ssc_en(mtk_dp, true);
-	} else {
-		dpcd_data = 0x0;
-		dptx_auxwrite_dpcd(mtk_dp, DP_AUX_NATIVE_WRITE, DPCD_00107, 0x1, &dpcd_data);
-		dptx_hal_ssc_en(mtk_dp, false);
-	}
-	dptx_hal_set_txlane(mtk_dp, lanecount / 2);
-	dptx_hal_phy_setting(mtk_dp);
-
-	printk(BIOS_INFO, "Link train linkrate = %#x, lanecount = %#x\n",
-	       linkrate, lanecount);
-}
-
-static void drm_dp_dpcd_read_link_status(struct mtk_dp *mtk_dp, u8 status[DP_LINK_STATUS_SIZE])
-{
-	dptx_auxread_dpcd(mtk_dp, DP_AUX_NATIVE_READ, DPCD_00202, DP_LINK_STATUS_SIZE, status);
-}
-
-static int mtk_edp_train_cr(struct mtk_dp *mtk_dp, u8 lane_count)
-{
-	u8 lane_adjust[DP_LANSE_ADJUST_SIZE];
-	u8 link_status[DP_LINK_STATUS_SIZE];
-	u8 prev_lane_adjust = 0xff;
-	int train_retries = 0;
-	int voltage_retries = 0;
-	u8 buff;
-
-	mtk_edp_pattern(mtk_dp, lane_count, DPTX_PATTERN_TPS1);
-
-	/* In DP spec 1.4, the retry count of CR is defined as 10. */
-	do {
-		train_retries++;
-		if (!dptx_hal_hpd_high(mtk_dp)) {
-			mtk_edp_pattern(mtk_dp, lane_count, DPTX_PATTERN_UNKNOWN);
-			return DPTX_TRANING_FAIL;
-		}
-
-		dptx_auxread_dpcd(mtk_dp, DP_AUX_NATIVE_READ, DPCD_00206, sizeof(lane_adjust),
-				  lane_adjust);
-		printk(BIOS_DEBUG, "[aux_read] dpcd206 lane_adjust[0]=%#x\n", lane_adjust[0]);
-		printk(BIOS_DEBUG, "[aux_read] dpcd207 lane_adjust[1]=%#x\n", lane_adjust[1]);
-		update_swing_preemphasis(mtk_dp, lane_count, lane_adjust);
-
-		dptx_link_train_clock_recovery_delay(mtk_dp->rx_cap);
-
-		/* Check link status from sink device */
-		drm_dp_dpcd_read_link_status(mtk_dp, link_status);
-		if (dptx_clock_recovery_ok(link_status, lane_count)) {
-			printk(BIOS_INFO, "Link train CR pass\n");
-			return 0;
-		}
-
-		/*
-		 * In DP spec 1.4, if current voltage level is the same
-		 * with previous voltage level, we need to retry 5 times.
-		 */
-		if (prev_lane_adjust == link_status[4]) {
-			voltage_retries++;
-			/*
-			 * Condition of CR fail:
-			 * 1. Failed to pass CR using the same voltage
-			 *    level over five times.
-			 * 2. Failed to pass CR when the current voltage
-			 *    level is the same with previous voltage
-			 *    level and reach max voltage level (3).
-			 */
-			if (voltage_retries > MTK_DP_TRAIN_VOLTAGE_LEVEL_RETRY ||
-			    (prev_lane_adjust & DP_ADJUST_VOLTAGE_SWING_LANE0_MASK) == 3) {
-				printk(BIOS_ERR, "Link train CR fail\n");
-				break;
-			}
-		} else {
-			/*
-			 * If the voltage level is changed, we need to
-			 * re-calculate this retry count.
-			 */
-			voltage_retries = 0;
-		}
-		prev_lane_adjust = link_status[4];
-		printk(BIOS_INFO, "CR training retries %d\n", voltage_retries);
-	} while (train_retries < MTK_DP_TRAIN_DOWNSCALE_RETRY);
-
-	/* Failed to train CR, and disable pattern. */
-	buff = DP_TRAINING_PATTERN_DISABLE;
-	dptx_auxwrite_dpcd(mtk_dp, DP_AUX_NATIVE_WRITE, DPCD_00102, 0x1, &buff);
-	mtk_edp_pattern(mtk_dp, lane_count, DPTX_PATTERN_UNKNOWN);
-
-	return DPTX_TRANING_FAIL;
-}
-
-static int mtk_edp_train_eq(struct mtk_dp *mtk_dp, u8 lane_count)
-{
-	u8 lane_adjust[2];
-	u8 link_status[DP_LINK_STATUS_SIZE];
-	int train_retries = 0;
-	u8 buff;
-
-	if (mtk_dp->train_info.tps4)
-		mtk_edp_pattern(mtk_dp, lane_count, DPTX_PATTERN_TPS4);
-	else if (mtk_dp->train_info.tps3)
-		mtk_edp_pattern(mtk_dp, lane_count, DPTX_PATTERN_TPS3);
-	else
-		mtk_edp_pattern(mtk_dp, lane_count, DPTX_PATTERN_TPS2);
-
-	do {
-		train_retries++;
-		if (!dptx_hal_hpd_high(mtk_dp)) {
-			mtk_edp_pattern(mtk_dp, lane_count, DPTX_PATTERN_UNKNOWN);
-			return DPTX_TRANING_FAIL;
-		}
-
-		dptx_auxread_dpcd(mtk_dp, DP_AUX_NATIVE_READ, DPCD_00206, sizeof(lane_adjust),
-				  lane_adjust);
-		printk(BIOS_DEBUG, "[aux_read] dpcd206 lane_adjust[0]=%#x\n", lane_adjust[0]);
-		printk(BIOS_DEBUG, "[aux_read] dpcd207 lane_adjust[1]=%#x\n", lane_adjust[1]);
-		update_swing_preemphasis(mtk_dp, lane_count, lane_adjust);
-
-		dptx_link_train_channel_eq_delay(mtk_dp->rx_cap);
-
-		/* check link status from sink device */
-		drm_dp_dpcd_read_link_status(mtk_dp, link_status);
-		if (dptx_channel_eq_ok(link_status, lane_count)) {
-			printk(BIOS_DEBUG, "Link train EQ pass\n");
-
-			/* Training done, and disable pattern. */
-			buff = DP_TRAINING_PATTERN_DISABLE;
-			dptx_auxwrite_dpcd(mtk_dp, DP_AUX_NATIVE_WRITE, DPCD_00102, 0x1, &buff);
-			mtk_edp_pattern(mtk_dp, lane_count, DPTX_PATTERN_UNKNOWN);
-			return 0;
-		}
-		printk(BIOS_INFO, "Link train EQ fail retry:%d\n", train_retries);
-	} while (train_retries < MTK_DP_TRAIN_DOWNSCALE_RETRY);
-
-	/* Failed to train EQ, and disable pattern. */
-	buff = DP_TRAINING_PATTERN_DISABLE;
-	dptx_auxwrite_dpcd(mtk_dp, DP_AUX_NATIVE_WRITE, DPCD_00102, 0x1, &buff);
-	mtk_edp_pattern(mtk_dp, lane_count, DPTX_PATTERN_UNKNOWN);
-
-	return DPTX_TIMEOUT;
-}
-
-static int dptx_set_trainingstart(struct mtk_dp *mtk_dp)
-{
-	u8 lanecount;
-	u8 linkrate;
-	u8 buffer;
-	u8 train_limit;
-	u8 max_linkrate;
-	int ret;
-
-	buffer = 0x1;
-	dptx_auxwrite_dpcd(mtk_dp, DP_AUX_NATIVE_WRITE, DPCD_00600, 0x1, &buffer);
-
-	linkrate = mtk_dp->rx_cap[1];
-	lanecount = mtk_dp->rx_cap[2] & 0x1F;
-
-	printk(BIOS_INFO, "RX support linkrate = %#x, lanecount = %#x\n", linkrate, lanecount);
-
-	if (mtk_dp->train_info.sink_extcap_en)
-		dptx_auxread_dpcd(mtk_dp, DP_AUX_NATIVE_READ, DPCD_02002, 0x1, &buffer);
-	else
-		dptx_auxread_dpcd(mtk_dp, DP_AUX_NATIVE_READ, DPCD_00200, 0x1, &buffer);
-
-	if ((buffer & 0xBF) != 0)
-		mtk_dp->train_info.sink_count_num = buffer & 0xBF;
-
-	dptx_hal_setscramble(mtk_dp, false);
-	switch (linkrate) {
-	case DP_LINKRATE_RBR:
-	case DP_LINKRATE_HBR:
-	case DP_LINKRATE_HBR2:
-	case DP_LINKRATE_HBR25:
-	case DP_LINKRATE_HBR3:
-		break;
-	default:
-		mtk_dp->train_info.linkrate = DP_LINKRATE_HBR3;
-		break;
-	};
-
-	max_linkrate = linkrate;
-	printk(BIOS_INFO, "[eDPTX] linkrate = %#x, lanecount = %#x\n", linkrate, lanecount);
-	for (train_limit = 6; train_limit > 0; train_limit--) {
-		dptx_training_changemode(mtk_dp);
-
-		mtk_edp_train_setting(mtk_dp, linkrate, lanecount);
-		ret = mtk_edp_train_cr(mtk_dp, lanecount);
-		if (ret == DPTX_TRANING_FAIL) {
-			return ret;
-		} else if (ret) {
-			/* Reduce link rate */
-			switch (linkrate) {
-			case DP_LINKRATE_RBR:
-				lanecount = lanecount / 2;
-				linkrate = max_linkrate;
-
-				if (lanecount == 0)
-					return DPTX_TRANING_FAIL;
-				break;
-			case DP_LINKRATE_HBR:
-				linkrate = DP_LINKRATE_RBR;
-				break;
-			case DP_LINKRATE_HBR2:
-				linkrate = DP_LINKRATE_HBR;
-				break;
-			case DP_LINKRATE_HBR3:
-				linkrate = DP_LINKRATE_HBR2;
-				break;
-			default:
-				return DPTX_TRANING_FAIL;
-			}
-			continue;
-		}
-
-		ret = mtk_edp_train_eq(mtk_dp, lanecount);
-		if (ret == DPTX_TIMEOUT) {
-			return DPTX_TIMEOUT;
-		} else if (ret) {
-			/* Reduce lane count */
-			if (lanecount == DP_LANECOUNT_4)
-				lanecount = DP_LANECOUNT_2;
-			else if (lanecount == DP_LANECOUNT_2)
-				lanecount = DP_LANECOUNT_1;
-			else
-				return DPTX_TRANING_FAIL;
-			continue;
-		}
-		printk(BIOS_INFO, "[eDPTX] EQ training pass\n");
-		/* If we reach here, training is done. */
-		break;
-	}
-
-	if (train_limit == 0)
-		return DPTX_TRANING_FAIL;
-
-	mtk_dp->train_info.linkrate = linkrate;
-	mtk_dp->train_info.linklane_count = lanecount;
-	/*
-	 * After training done, we need to output normal stream instead of TPS,
-	 * so we need to enable scramble.
-	 */
-	dptx_hal_setscramble(mtk_dp, true);
-	dptx_hal_set_ef_mode(mtk_dp, ENABLE_DPTX_EF_MODE);
-
-	printk(BIOS_INFO, "%s: done\n", __func__);
-
-	return DPTX_PASS;
-}
-
-static void dptx_init_port(struct mtk_dp *mtk_dp)
-{
-	dptx_hal_phy_setidlepattern(mtk_dp, true);
-	dptx_hal_init_setting(mtk_dp);
-	dptx_hal_aux_setting(mtk_dp);
-	dptx_hal_digital_setting(mtk_dp);
-	dptx_hal_phy_init(mtk_dp);
-	dptx_hal_phy_setting(mtk_dp);
-	dptx_hal_hpd_detect_setting(mtk_dp);
-
-	dptx_hal_digital_swreset(mtk_dp);
-
-	dptx_hal_analog_power_en(mtk_dp, true);
-	dptx_hal_hpd_int_en(mtk_dp, true);
-}
-
-int mtk_edp_init(struct mtk_dp *mtk_dp, struct edid *edid)
+void dptx_set_tx_power_con(void)
 {
 	write32p(EDP_CLK_BASE + DISP_EDPTX_PWR_CON, 0xC2FC224D);
-	/* Add 26Mhz clock */
+}
+
+void dptx_set_26mhz_clock(void)
+{
 	write32p(CKSYS_GP2_BASE + CKSYS2_CLK_CFG_3_CLR, 0xFF000000);
 	write32p(CKSYS_GP2_BASE + CKSYS2_CLK_CFG_UPDATE, 0x00008000);
-	udelay(50);
-	dptx_init_variable(mtk_dp);
-	dptx_init_port(mtk_dp);
-
-	if (!dptx_hal_hpd_high(mtk_dp)) {
-		printk(BIOS_ERR, "HPD is low\n");
-		return -1;
-	}
-
-	dptx_check_sinkcap(mtk_dp);
-
-	if (dptx_get_edid(mtk_dp, edid) != 0) {
-		printk(BIOS_ERR, "Failed to get EDID\n");
-		return -1;
-	}
-
-	if (dptx_set_trainingstart(mtk_dp) != DPTX_PASS) {
-		printk(BIOS_ERR, "%s: Failed to set training start\n", __func__);
-		return -1;
-	}
-
-	dp_intf_config(edid);
-	dptx_video_config(mtk_dp);
-
-	return 0;
-}
-
-
-int mtk_edp_enable(struct mtk_dp *mtk_dp)
-{
-	if (!mtk_dp) {
-		printk(BIOS_ERR, "%s: eDP is not initialized\n", __func__);
-		return -1;
-	}
-	dptx_video_enable(mtk_dp, true);
-	return 0;
 }
diff --git a/src/soc/mediatek/mt8196/dptx_hal.c b/src/soc/mediatek/mt8196/dptx_hal.c
index e6078aea88..f2ec6541b3 100644
--- a/src/soc/mediatek/mt8196/dptx_hal.c
+++ b/src/soc/mediatek/mt8196/dptx_hal.c
@@ -1,299 +1,24 @@
 /* SPDX-License-Identifier: GPL-2.0-only OR MIT */
 
-#include <assert.h>
 #include <console/console.h>
-#include <device/mmio.h>
 #include <delay.h>
-#include <edid.h>
 #include <soc/dptx.h>
 #include <soc/dptx_hal.h>
 #include <soc/dptx_reg.h>
-#include <types.h>
-
-static const int driving_offset[] = {
-	PHYD_DIG_LAN0_OFFSET + DRIVING_FORCE,
-	PHYD_DIG_LAN1_OFFSET + DRIVING_FORCE,
-	PHYD_DIG_LAN2_OFFSET + DRIVING_FORCE,
-	PHYD_DIG_LAN3_OFFSET + DRIVING_FORCE,
-};
-
-void dptx_hal_init_setting(struct mtk_dp *mtk_dp)
-{
-	mtk_dp_mask(mtk_dp, 0x2000, GENMASK(1, 0), GENMASK(1, 0));
-
-	mtk_dp_mask(mtk_dp, REG_3540_DP_TRANS_P0, BIT(3), BIT(3));
-	mtk_dp_mask(mtk_dp, REG_342C_DP_TRANS_P0, 0x68, 0xFF);
-	mtk_dp_mask(mtk_dp, REG_31EC_DP_ENCODER0_P0, BIT(4), BIT(4));
-	mtk_dp_mask(mtk_dp, REG_304C_DP_ENCODER0_P0, 0, BIT(8));
-	mtk_dp_mask(mtk_dp, REG_304C_DP_ENCODER0_P0, BIT(3), BIT(3));
-
-	/* default marker */
-	mtk_dp_mask(mtk_dp, REG_3F04_DP_ENC_4P_3, 0, 0xFFFF);
-	mtk_dp_mask(mtk_dp, REG_3F08_DP_ENC_4P_3, BIT(3), BIT(3));
-	mtk_dp_mask(mtk_dp, REG_3F0C_DP_ENC_4P_3, BIT(1), BIT(1));
-	mtk_dp_mask(mtk_dp, REG_3F10_DP_ENC_4P_3, BIT(3), BIT(3));
-
-	mtk_dp_mask(mtk_dp, REG_33C0_DP_ENCODER1_P0, 0, 0xF000);
-	mtk_dp_mask(mtk_dp, REG_33C0_DP_ENCODER1_P0, 0x80, 0x80);
-	mtk_dp_mask(mtk_dp, REG_33C4_DP_ENCODER1_P0, BIT(5), BIT(6) | BIT(5));
-	mtk_dp_mask(mtk_dp, REG_3F28_DP_ENC_4P_3, 0xA << 2, GENMASK(5, 2));
-	mtk_dp_mask(mtk_dp, DP_TX_TOP_RESET_AND_PROBE, 0x9100FF, 0x9100FF);
-
-	mtk_dp_mask(mtk_dp, MTK_DP_TOP_IRQ_MASK, ENCODER_IRQ_MSK | TRANS_IRQ_MSK,
-		    ENCODER_IRQ_MSK | TRANS_IRQ_MSK);
-}
-
-void dptx_hal_set_color_format(struct mtk_dp *mtk_dp, u8 out_format)
-{
-	u32 val;
-
-	/* MISC0 */
-	mtk_dp_mask(mtk_dp, REG_3034_DP_ENCODER0_P0, out_format << DP_TEST_COLOR_FORMAT_SHIFT,
-		    DP_TEST_COLOR_FORMAT_MASK);
-	mtk_dp_mask(mtk_dp, REG_3034_DP_ENCODER0_P0, BIT(3), BIT(3));
-
-	switch (out_format) {
-	case DP_COLOR_FORMAT_RGB_444:
-	case DP_COLOR_FORMAT_YUV_444:
-		val = 0;
-		break;
-	case DP_COLOR_FORMAT_YUV_422:
-		val = 0x1;
-		break;
-	case DP_COLOR_FORMAT_YUV_420:
-		val = 0x2;
-		break;
-	default:
-		printk(BIOS_ERR, "Unsupported color format: %u\n", out_format);
-		return;
-	}
-	mtk_dp_mask(mtk_dp, REG_303C_DP_ENCODER0_P0, val << 12, 0x7 << 12);
-}
-
-void dptx_hal_settu_setencoder(struct mtk_dp *mtk_dp)
-{
-	mtk_dp_mask(mtk_dp, REG_303C_DP_ENCODER0_P0, BIT(15), BIT(15));
-	DP_WRITE2BYTE(mtk_dp, REG_3040_DP_ENCODER0_P0, 0x2020);
-	DP_WRITE2BYTE(mtk_dp, REG_3364_DP_ENCODER1_P0, 0x2020);
-	mtk_dp_mask(mtk_dp, REG_3300_DP_ENCODER1_P0, 0x2 << 8, 0x3 << 8);
-	mtk_dp_mask(mtk_dp, REG_3364_DP_ENCODER1_P0, 0x40 << 8, 0x70 << 8);
-}
-
-bool dptx_hal_hpd_high(struct mtk_dp *mtk_dp)
-{
-	return mtk_dp_read(mtk_dp, REG_364C_AUX_TX_P0) & BIT(15);
-}
-
-bool dptx_hal_setswing_preemphasis(struct mtk_dp *mtk_dp, int lane_num, u8 swing_value,
-				   u8 preemphasis)
-{
-	assert(lane_num <= DPTX_LANE_MAX);
-
-	for (int i = 0; i < lane_num; ++i) {
-		mtk_dp_phy_mask(mtk_dp, driving_offset[i],
-				swing_value << 1 | preemphasis << 3,
-				EDP_TX_LN_VOLT_SWING_VAL_MASK | EDP_TX_LN_PRE_EMPH_VAL_MASK);
-		printk(BIOS_DEBUG, "lane(%d), set swing(%u), emp(%u)\n",
-		       i, swing_value, preemphasis);
-	}
-	mtk_dp_mask(mtk_dp, 0x2000, GENMASK(1, 0), GENMASK(1, 0));
-	return true;
-}
 
 static void dptx_hal_phy_reset_swing_preemphasis(struct mtk_dp *mtk_dp)
 {
-	for (int i = 0; i < ARRAY_SIZE(driving_offset); i++)
-		mtk_dp_phy_mask(mtk_dp, driving_offset[i], 0,
+	for (int i = 0; i < dptx_hal_driving_offset_size; i++)
+		mtk_dp_phy_mask(mtk_dp, dptx_hal_driving_offset[i], 0,
 				EDP_TX_LN_VOLT_SWING_VAL_MASK | EDP_TX_LN_PRE_EMPH_VAL_MASK);
 }
 
-void dptx_hal_hpd_detect_setting(struct mtk_dp *mtk_dp)
-{
-	mtk_dp_mask(mtk_dp, REG_364C_AUX_TX_P0, HPD_INT_THD_FLDMASK_VAL << 4,
-		    HPD_INT_THD_FLDMASK);
-}
-
-void dptx_hal_phy_init(struct mtk_dp *mtk_dp)
-{
-	mtk_dp_phy_mask(mtk_dp, IPMUX_CONTROL, 0 << EDPTX_DSI_PHYD_SEL_FLDMASK_POS,
-			EDPTX_DSI_PHYD_SEL_FLDMASK);
-
-	mtk_dp_phy_mask(mtk_dp, PHYD_DIG_GLB_OFFSET + 0x10, GENMASK(2, 0), GENMASK(2, 0));
-	dptx_hal_ssc_en(mtk_dp, false);
-}
-
-void dptx_hal_set_txrate(struct mtk_dp *mtk_dp, u8 value)
-{
-	printk(BIOS_INFO, "Link rate = 0x%x\n", value);
-	switch (value) {
-	case DP_LINKRATE_RBR:
-		mtk_dp_phy_write(mtk_dp, 0x143C, 0x1);
-		break;
-	case DP_LINKRATE_HBR:
-		mtk_dp_phy_write(mtk_dp, 0x143C, 0x4);
-		break;
-	case DP_LINKRATE_HBR2:
-		mtk_dp_phy_write(mtk_dp, 0x143C, 0x7);
-		break;
-	case DP_LINKRATE_HBR3:
-		mtk_dp_phy_write(mtk_dp, 0x143C, 0x9);
-		break;
-	default:
-		printk(BIOS_ERR, "Link rate not support(%d)\n", value);
-		return;
-	}
-}
-
 void dptx_hal_phy_set_lanes(struct mtk_dp *mtk_dp, u8 lane_count)
 {
 	for (int i = 0; i < lane_count; i++)
 		mtk_dp_phy_mask(mtk_dp, PHYD_DIG_GLB_OFFSET + 0x74, BIT(i), BIT(i));
 }
 
-void dptx_hal_phy_setting(struct mtk_dp *mtk_dp)
-{
-	u8 link_rate = mtk_dp->train_info.linkrate;
-	u8 lane_count = mtk_dp->train_info.linklane_count;
-
-	dptx_hal_phy_set_lanes(mtk_dp, lane_count);
-	dptx_hal_set_txrate(mtk_dp, link_rate);
-
-	/* Turn on phy power after phy configure */
-	mtk_dp_mask(mtk_dp, REG_3FF8_DP_ENC_4P_3, PHY_STATE_W_1_DP_ENC_4P_3,
-		    PHY_STATE_W_1_DP_ENC_4P_3_MASK);
-	mtk_dp_mask(mtk_dp, 0x2000, GENMASK(1, 0), GENMASK(1, 0));
-	printk(BIOS_DEBUG, "[eDPTX] DP_PHY_DIG_PLL_CTL_1:%#x\n",
-	       mtk_dp_phy_read(mtk_dp, DP_PHY_DIG_PLL_CTL_1));
-}
-
-void dptx_hal_ssc_en(struct mtk_dp *mtk_dp, bool enable)
-{
-	if (enable) {
-		printk(BIOS_DEBUG, "[eDPTX] enable ssc\n");
-		mtk_dp_phy_mask(mtk_dp, DP_PHY_DIG_PLL_CTL_1, BIT(8), BIT(8));
-	} else {
-		printk(BIOS_DEBUG, "[eDPTX] disable ssc\n");
-		mtk_dp_phy_mask(mtk_dp, DP_PHY_DIG_PLL_CTL_1, 0x0, BIT(8));
-	}
-	printk(BIOS_DEBUG, "[eDPTX] DP_PHY_DIG_PLL_CTL_1:%#x\n",
-	       mtk_dp_phy_read(mtk_dp, DP_PHY_DIG_PLL_CTL_1));
-
-	mdelay(1);
-}
-
-void dptx_hal_aux_setting(struct mtk_dp *mtk_dp)
-{
-	/* Modify timeout threshold = 1595 [12 : 8] */
-	mtk_dp_mask(mtk_dp, REG_360C_AUX_TX_P0, 0x1D0C, 0x1FFF);
-	mtk_dp_mask(mtk_dp, REG_3658_AUX_TX_P0, 0, BIT(0));
-	/* [0]mtk_dp, REG_aux_tx_ov_en */
-	mtk_dp_mask(mtk_dp, REG_36A0_AUX_TX_4P, 0xFFFC, 0xFFFC);
-
-	/* 26M */
-	mtk_dp_mask(mtk_dp, REG_3634_AUX_TX_P0, AUX_TX_OVER_SAMPLE_RATE_FOR_26M << 8,
-		    0xff << 8);
-	mtk_dp_mask(mtk_dp, REG_3614_AUX_TX_P0, AUX_RX_UI_CNT_THR_AUX_FOR_26M, 0x7f);
-
-	/* Modify, 13 for 26M */
-	mtk_dp_mask(mtk_dp, REG_37C8_AUX_TX_P0, MTK_ATOP_EN_AUX_TX_4P, MTK_ATOP_EN_AUX_TX_4P);
-	/* Disable aux sync_stop detect function */
-	mtk_dp_mask(mtk_dp, REG_3690_AUX_TX_P0, RX_REPLY_COMPLETE_MODE_AUX_TX_4P,
-		    RX_REPLY_COMPLETE_MODE_AUX_TX_4P);
-
-	mtk_dp_mask(mtk_dp, REG_367C_AUX_TX_P0, HPD_CONN_THD_AUX_TX_P0_FLDMASK_POS << 6,
-		    HPD_CONN_THD_AUX_TX_P0_FLDMASK);
-
-	mtk_dp_mask(mtk_dp, REG_37A0_AUX_TX_P0, HPD_DISC_THD_AUX_TX_P0_FLDMASK_POS << 4,
-		    HPD_DISC_THD_AUX_TX_P0_FLDMASK);
-	mtk_dp_mask(mtk_dp, REG_3690_AUX_TX_P0, RX_REPLY_COMPLETE_MODE_AUX_TX_4P,
-		    RX_REPLY_COMPLETE_MODE_AUX_TX_4P);
-	mtk_dp_mask(mtk_dp, REG_3FF8_DP_ENC_4P_3, XTAL_FREQ_FOR_PSR_DP_ENC_4P_3_VALUE << 9,
-		    XTAL_FREQ_FOR_PSR_DP_ENC_4P_3_MASK);
-	mtk_dp_mask(mtk_dp, REG_366C_AUX_TX_P0, XTAL_FREQ_DP_TX_AUX_366C_VALUE << 8,
-		    XTAL_FREQ_DP_TX_AUX_366C_MASK);
-}
-
-void dptx_hal_digital_setting(struct mtk_dp *mtk_dp)
-{
-	mtk_dp_mask(mtk_dp, REG_304C_DP_ENCODER0_P0, 0, VBID_VIDEO_MUTE_DP_ENC0_4P_MASK);
-	mtk_dp_mask(mtk_dp, REG_3368_DP_ENCODER1_P0, BS2BS_MODE_DP_ENC1_4P_VAL << 12,
-		    0x3 << 12);
-	mtk_dp_mask(mtk_dp, REG_3030_DP_ENCODER0_P0, BIT(11), BIT(11));
-
-	/* dp I-mode enable */
-	mtk_dp_mask(mtk_dp, BS2BS_MODE_DP_ENCODER1_P0_FLDMASK, DP_I_MODE_ENABLE,
-		    DP_I_MODE_ENABLE);
-	mtk_dp_mask(mtk_dp, REG_3030_DP_ENCODER0_P0, 0x3ff, 0x3ff);
-	mtk_dp_mask(mtk_dp, REG_3028_DP_ENCODER0_P0, 0, BIT(15));
-	mtk_dp_mask(mtk_dp, REG_302C_DP_ENCODER0_P0, 0, BIT(15));
-
-	/* set color format */
-	dptx_hal_set_color_format(mtk_dp, DP_COLOR_FORMAT_RGB_444);
-
-	/* set color depth */
-	dptx_hal_set_color_depth(mtk_dp, DP_COLOR_DEPTH_8BIT);
-
-	/* reg_bs)symbol_cnt_reset */
-	mtk_dp_mask(mtk_dp, REG_3000_DP_ENCODER0_P0, REG_BS_SYMBOL_CNT_RESET,
-		    REG_BS_SYMBOL_CNT_RESET);
-	mtk_dp_mask(mtk_dp, REG_3004_DP_ENCODER0_P0, BIT(14), BIT(14));
-	printk(BIOS_DEBUG, "[eDPTX] REG_3004_DP_ENCODER0_P0:%#x\n",
-	       mtk_dp_read(mtk_dp, REG_3004_DP_ENCODER0_P0));
-
-	mtk_dp_mask(mtk_dp, REG_3368_DP_ENCODER1_P0, 0x2, BIT(1) | BIT(2));
-	mtk_dp_mask(mtk_dp, REG_3368_DP_ENCODER1_P0, BIT(15), BIT(15));
-	mtk_dp_mask(mtk_dp, REG_304C_DP_ENCODER0_P0, 0, BIT(8));
-
-	/* [5:0]video sram start address */
-	mtk_dp_mask(mtk_dp, REG_303C_DP_ENCODER0_P0, 0x8, 0x3F);
-
-	/* reg_psr_patgen_avt_en patch */
-	mtk_dp_mask(mtk_dp, REG_3F80_DP_ENC_4P_3, 0, PSR_PATGEN_AVT_EN_FLDMASK);
-
-	/* phy D enable */
-	mtk_dp_mask(mtk_dp, REG_3FF8_DP_ENC_4P_3, PHY_STATE_W_1_DP_ENC_4P_3,
-		    PHY_STATE_W_1_DP_ENC_4P_3_MASK);
-
-	/* reg_dvo_on_ow_en */
-	mtk_dp_mask(mtk_dp, REG_3FF8_DP_ENC_4P_3, DVO_ON_W_1_FLDMASK, DVO_ON_W_1_FLDMASK);
-
-	/* dp tx encoder reset all sw */
-	mtk_dp_mask(mtk_dp, REG_3004_DP_ENCODER0_P0, DP_TX_ENCODER_4P_RESET_SW_DP_ENC0_P0,
-		    DP_TX_ENCODER_4P_RESET_SW_DP_ENC0_P0);
-	printk(BIOS_DEBUG, "[eDPTX] REG_3004_DP_ENCODER0_P0:%#x\n",
-	       mtk_dp_read(mtk_dp, REG_3004_DP_ENCODER0_P0));
-
-	mtk_dp_mask(mtk_dp, REG_3004_DP_ENCODER0_P0, 0, BIT(9));
-	printk(BIOS_DEBUG, "[eDPTX] REG_3004_DP_ENCODER0_P0:%#x\n",
-	       mtk_dp_read(mtk_dp, REG_3004_DP_ENCODER0_P0));
-
-	mtk_dp_mask(mtk_dp, REG_3FF8_DP_ENC_4P_3, 0xff, 0xff);
-
-	/* Wait for sw reset to complete */
-	mdelay(1);
-}
-
-void dptx_hal_digital_swreset(struct mtk_dp *mtk_dp)
-{
-	printk(BIOS_DEBUG, "[eDPTX] DP_PHY_DIG_TX_CTL_0:%#x\n",
-	       mtk_dp_phy_read(mtk_dp, DP_PHY_DIG_TX_CTL_0));
-	mtk_dp_mask(mtk_dp, REG_340C_DP_TRANS_P0, BIT(13), BIT(13));
-	mdelay(1);
-	mtk_dp_mask(mtk_dp, REG_340C_DP_TRANS_P0, 0, BIT(13));
-
-	mtk_dp_mask(mtk_dp, EDP_TX_TOP_CLKGEN_0, 0xF, 0xF);
-	printk(BIOS_DEBUG, "[eDPTX] DP_PHY_DIG_TX_CTL_0:%#x\n",
-	       mtk_dp_phy_read(mtk_dp, DP_PHY_DIG_TX_CTL_0));
-}
-
-void dptx_hal_swing_emp_reset(struct mtk_dp *mtk_dp)
-{
-	mtk_dp_mask(mtk_dp, REG_2004_TOP_SWING_EMP, 0,
-		    DP_TX0_VOLT_SWING_MASK | DP_TX1_VOLT_SWING_MASK | DP_TX2_VOLT_SWING_MASK |
-		    DP_TX3_VOLT_SWING_MASK | DP_TX0_PRE_EMPH_MASK | DP_TX1_PRE_EMPH_MASK |
-		    DP_TX2_PRE_EMPH_MASK | DP_TX3_PRE_EMPH_MASK);
-}
-
 void dptx_hal_phyd_reset(struct mtk_dp *mtk_dp)
 {
 	u32 val;
@@ -314,74 +39,3 @@ void dptx_hal_phyd_reset(struct mtk_dp *mtk_dp)
 
 	dptx_hal_phy_reset_swing_preemphasis(mtk_dp);
 }
-
-void dptx_hal_phy_wait_aux_ldo_ready(struct mtk_dp *mtk_dp)
-{
-	u32 mask = RGS_BG_CORE_EN_READY_MASK | RGS_AUX_LDO_EN_READY_MASK;
-
-	if (!retry(WAIT_AUX_READY_RETRY_TIMES, (mtk_dp_phy_read(mtk_dp, 0x146C) & mask) == mask,
-						mdelay(2))) {
-		printk(BIOS_ERR, "Wait AUX LDO ready timeout!\n");
-	}
-}
-
-void dptx_hal_set_txlane(struct mtk_dp *mtk_dp, u8 value)
-{
-	/* Turn off phy power before phy configure */
-	mtk_dp_mask(mtk_dp, REG_3F44_DP_ENC_4P_3, PHY_PWR_STATE_OW_EN_DP_ENC_4P_3,
-		    PHY_PWR_STATE_OW_EN_DP_ENC_4P_3_MASK);
-	mtk_dp_mask(mtk_dp, REG_3F44_DP_ENC_4P_3, BIAS_POWER_ON,
-		    PHY_PWR_STATE_OW_VALUE_DP_ENC_4P_3_MASK);
-	dptx_hal_phy_wait_aux_ldo_ready(mtk_dp);
-	mtk_dp_mask(mtk_dp, REG_3F44_DP_ENC_4P_3, 0 << 2, PHY_PWR_STATE_OW_EN_DP_ENC_4P_3_MASK);
-
-	if (value == 0)
-		mtk_dp_mask(mtk_dp, REG_35F0_DP_TRANS_P0, 0, BIT(3) | BIT(2));
-	else
-		mtk_dp_mask(mtk_dp, REG_35F0_DP_TRANS_P0, BIT(3), BIT(3) | BIT(2));
-
-	assert((value << 2) <= UINT8_MAX);
-	mtk_dp_mask(mtk_dp, REG_3000_DP_ENCODER0_P0, value, BIT(1) | BIT(0));
-	mtk_dp_mask(mtk_dp, REG_34A4_DP_TRANS_P0, value << 2, BIT(3) | BIT(2));
-}
-
-void dptx_hal_phy_set_swing_preemphasis(struct mtk_dp *mtk_dp, u8 lane_count, u8 *swing_val,
-					 u8 *preemphasis)
-{
-	assert(lane_count <= DPTX_LANE_MAX);
-
-	for (int i = 0; i < lane_count; ++i) {
-		mtk_dp_phy_mask(mtk_dp, driving_offset[i],
-				swing_val[i] << 1 | preemphasis[i] << 3,
-				EDP_TX_LN_VOLT_SWING_VAL_MASK | EDP_TX_LN_PRE_EMPH_VAL_MASK);
-		printk(BIOS_DEBUG, "lane(%d), set swing(%u), emp(%u)\n",
-		       i, swing_val[i], preemphasis[i]);
-	}
-}
-
-void dptx_hal_phy_set_idle_pattern(struct mtk_dp *mtk_dp, u8 lane_count, bool enable)
-{
-	u32 val = 0x0;
-
-	printk(BIOS_INFO, "lane_count: %x idle pattern enable: %d\n", lane_count, enable);
-	switch (lane_count) {
-	case 1:
-		val = POST_MISC_DATA_LANE0_OV_DP_TRANS_4P_MASK;
-		break;
-	case 2:
-		val = POST_MISC_DATA_LANE0_OV_DP_TRANS_4P_MASK |
-		      POST_MISC_DATA_LANE1_OV_DP_TRANS_4P_MASK;
-		break;
-	case 4:
-		val = POST_MISC_DATA_LANE0_OV_DP_TRANS_4P_MASK |
-		      POST_MISC_DATA_LANE1_OV_DP_TRANS_4P_MASK |
-		      POST_MISC_DATA_LANE2_OV_DP_TRANS_4P_MASK |
-		      POST_MISC_DATA_LANE3_OV_DP_TRANS_4P_MASK;
-		break;
-	default:
-		printk(BIOS_ERR, "%s: Unexpected lane count %d\n", __func__, lane_count);
-		return;
-	}
-	mtk_dp_mask(mtk_dp, REG_3580_DP_TRANS_P0, (enable ? val : 0x0) << 8,
-		    POST_MISC_DATA_LANE_OV_DP_TRANS_4P_MASK);
-}
diff --git a/src/soc/mediatek/mt8196/include/soc/dp_intf.h b/src/soc/mediatek/mt8196/include/soc/dp_intf.h
index 989cb90609..a85143ce55 100644
--- a/src/soc/mediatek/mt8196/include/soc/dp_intf.h
+++ b/src/soc/mediatek/mt8196/include/soc/dp_intf.h
@@ -3,208 +3,9 @@
 #ifndef __SOC_MEDIATEK_MT8196_DP_DP_INTF_H__
 #define __SOC_MEDIATEK_MT8196_DP_DP_INTF_H__
 
-#include <edid.h>
-#include <soc/addressmap.h>
-#include <types.h>
+#include <soc/dp_intf_v2.h>
 
-#define DVO_EN		0x00
-#define EN		BIT(0)
-#define DVO_FORCE_ON	BIT(4)
-#define LINK_OFF	BIT(8)
-
-#define MMSYS1_CG_CLR0		0x108
-#define MMSYS1_CG_CLR1		0x118
 #define CKSYS2_CLK_CFG_3_CLR	0x48
 #define CKSYS2_CLK_CFG_UPDATE	0x4
-#define DISP_EDPTX_PWR_CON	0x74
-
-#define DVO_RET		0x04
-#define SWRST		BIT(0)
-#define SWRST_SEL	BIT(4)
-
-#define DVO_INTEN		0x08
-#define INT_VFP_START_EN	BIT(0)
-#define INT_VSYNC_START_EN	BIT(1)
-#define INT_VSYNC_END_EN	BIT(2)
-#define INT_VDE_START_EN	BIT(3)
-#define INT_VDE_END_EN		BIT(4)
-#define INT_WR_INFOQ_REG_EN	BIT(5)
-#define INT_TARGET_LINE0_EN	BIT(6)
-#define INT_TARGET_LINE1_EN	BIT(7)
-#define INT_TARGET_LINE2_EN	BIT(8)
-#define INT_TARGET_LINE3_EN	BIT(9)
-#define INT_WR_INFOQ_START_EN	BIT(10)
-#define INT_WR_INFOQ_END_EN	BIT(11)
-#define EXT_VSYNC_START_EN	BIT(12)
-#define EXT_VSYNC_END_EN	BIT(13)
-#define EXT_VDE_START_EN	BIT(14)
-#define EXT_VDE_END_EN		BIT(15)
-#define EXT_VBLANK_END_EN	BIT(16)
-#define UNDERFLOW_EN		BIT(17)
-#define INFOQ_ABORT_EN		BIT(18)
-
-#define DVO_INTSTA		0x0C
-#define INT_VFP_START_STA	BIT(0)
-#define INT_VSYNC_START_STA	BIT(1)
-#define INT_VSYNC_END_STA	BIT(2)
-#define INT_VDE_START_STA	BIT(3)
-#define INT_VDE_END_STA		BIT(4)
-#define INT_WR_INFOQ_REG_STA	BIT(5)
-#define INT_TARGET_LINE0_STA	BIT(6)
-#define INT_TARGET_LINE1_STA	BIT(7)
-#define INT_TARGET_LINE2_STA	BIT(8)
-#define INT_TARGET_LINE3_STA	BIT(9)
-#define INT_WR_INFOQ_START_STA	BIT(10)
-#define INT_WR_INFOQ_END_STA	BIT(11)
-#define EXT_VSYNC_START_STA	BIT(12)
-#define EXT_VSYNC_END_STA	BIT(13)
-#define EXT_VDE_START_STA	BIT(14)
-#define EXT_VDE_END_STA		BIT(15)
-#define EXT_VBLANK_END_STA	BIT(16)
-#define INT_UNDERFLOW_STA	BIT(17)
-#define INFOQ_ABORT_STA		BIT(18)
-
-#define DVO_CON		0x10
-#define INTL_EN		BIT(0)
-
-#define DVO_OUTPUT_SET	0x18
-#define OUT_NP_SEL	(0x3 <<	0)
-
-#define BIT_SWAP	BIT(4)
-#define CH_SWAP_MASK	(0x7 << 5)
-#define SWAP_RGB	0x00
-#define SWAP_GBR	0x01
-#define SWAP_BRG	0x02
-#define SWAP_RBG	0x03
-#define SWAP_GRB	0x04
-#define SWAP_BGR	0x05
-#define PXL_SWAP	BIT(8)
-#define R_MASK		BIT(12)
-#define G_MASK		BIT(13)
-#define B_MASK		BIT(14)
-#define DE_MASK		BIT(16)
-#define HS_MASK		BIT(17)
-#define VS_MASK		BIT(18)
-#define HS_INV		BIT(19)
-#define VS_INV		BIT(20)
-
-#define DVO_SRC_SIZE	0x20
-#define SRC_HSIZE_SHIFT	0
-#define SRC_HSIZE_MASK	(0xFFFF << 0)
-#define SRC_VSIZE_SHIFT	16
-#define SRC_VSIZE_MASK	(0xFFFF << 16)
-
-#define DVO_PIC_SIZE	0x24
-#define PIC_HSIZE_SHIFT	0
-#define PIC_HSIZE_MASK	(0xFFFF << 0)
-#define PIC_VSIZE_SHIFT	16
-#define PIC_VSIZE_MASK	(0xFFFF << 16)
-
-#define DVO_TGEN_H0	0x50
-#define HFP_SHIFT	0
-#define HFP_MASK	(0xFFFF << 0)
-#define HSYNC_SHIFT	16
-#define HSYNC_MASK	(0xFFFF << 16)
-
-#define DVO_TGEN_H1	0x54
-#define HSYNC2ACT_SHIFT	0
-#define HSYNC2ACT_MASK	(0xFFFF << 0)
-#define HACT_SHIFT	16
-#define HACT_MASK	(0xFFFF << 16)
-
-#define DVO_TGEN_V0	0x58
-#define VFP_SHIFT	0
-#define VFP_MASK	(0xFFFF << 0)
-#define VSYNC_SHIFT	16
-#define VSYNC_MASK	(0xFFFF << 16)
-
-#define DVO_TGEN_V1	0x5C
-#define VSYNC2ACT_SHIFT	0
-#define VSYNC2ACT_MASK	(0xFFFF << 0)
-#define VACT_SHIFT	16
-#define VACT_MASK	(0xFFFF << 16)
-
-#define DVO_TGEN_INFOQ_LATENCY		0x80
-#define INFOQ_START_LATENCY		0
-#define INFOQ_START_LATENCY_MASK	(0xFFFF << 0)
-#define INFOQ_END_LATENCY		16
-#define INFOQ_END_LATENCY_MASK		(0xFFFF << 16)
-
-#define DVO_BUF_CON0			0x220
-#define DISP_BUF_EN			BIT(0)
-#define FIFO_UNDERFLOW_DONE_BLOCK	BIT(4)
-
-#define DVO_TGEN_V_LAST_TRAILING_BLANK	0x6C
-#define V_LAST_TRAILING_BLANK		0
-#define V_LAST_TRAILING_BLANK_MASK	(0xFFFF << 0)
-
-#define DVO_TGEN_OUTPUT_DELAY_LINE	0x7C
-#define EXT_TG_DLY_LINE			0
-#define EXT_TG_DLY_LINE_MASK		(0xFFFF << 0)
-
-#define DVO_PATTERN_CTRL	0x100
-#define PRE_PAT_EN		BIT(0)
-#define PRE_PAT_SEL_MASK	(0x7 << 4)
-#define COLOR_BAR		(0x4 << 4)
-#define PRE_PAT_FORCE_ON	BIT(8)
-
-#define DVO_PATTERN_COLOR	0x104
-#define PAT_R			(0x3FF << 0)
-#define PAT_G			(0x3FF << 10)
-#define PAT_B			(0x3FF << 20)
-
-#define DVO_SHADOW_CTRL	0x190
-#define FORCE_COMMIT	BIT(0)
-#define BYPASS_SHADOW	BIT(1)
-#define READ_WRK_REG	BIT(2)
-
-#define DVO_SIZE	0x18
-#define DVO_TGEN_VWIDTH	0x28
-#define DVO_TGEN_VPORCH	0x2C
-#define DVO_TGEN_HPORCH	0x24
-#define DVO_TGEN_HWIDTH	0x20
-
-#define DVO_BUF_SODI_HIGHT	0x230
-#define DVO_BUF_SODI_LOW	0x234
-
-enum mtk_dvo_golden_setting_level {
-	MTK_DVO_FHD_60FPS_1920 = 0,
-	MTK_DVO_FHD_60FPS_2180,
-	MTK_DVO_FHD_60FPS_2400,
-	MTK_DVO_FHD_60FPS_2520,
-	MTK_DVO_FHD_90FPS,
-	MTK_DVO_FHD_120FPS,
-	MTK_DVO_WQHD_60FPS,
-	MTK_DVO_WQHD_120FPS,
-	MTK_DVO_8K_30FPS,
-	MTK_DVO_GSL_MAX,
-};
-
-struct mtk_dvo_gs_info {
-	u32 dvo_buf_sodi_high;
-	u32 dvo_buf_sodi_low;
-};
-
-enum TVDPLL_CLK {
-	TVDPLL_PLL = 0,
-	TVDPLL_D16 = 1,
-	TVDPLL_D8 = 2,
-	TVDPLL_D4 = 3,
-};
-
-struct mtk_dvo {
-	void *regs;
-	void *regs_ck;
-	void *regs_mm;
-	enum mtk_dvo_golden_setting_level gs_level;
-};
-
-struct mtk_dvo_sync_param {
-	u32 sync_width;
-	u32 front_porch;
-	u32 back_porch;
-};
-
-void dp_intf_config(const struct edid *edid);
 
 #endif /* __SOC_MEDIATEK_MT8196_DP_DP_INTF_H__ */
diff --git a/src/soc/mediatek/mt8196/include/soc/dptx_hal.h b/src/soc/mediatek/mt8196/include/soc/dptx_hal.h
index 57ce17e2b8..5b052c4e52 100644
--- a/src/soc/mediatek/mt8196/include/soc/dptx_hal.h
+++ b/src/soc/mediatek/mt8196/include/soc/dptx_hal.h
@@ -3,25 +3,13 @@
 #ifndef __SOC_MEDIATEK_MT8196_DP_DPTX_HAL_H__
 #define __SOC_MEDIATEK_MT8196_DP_DPTX_HAL_H__
 
-#include <soc/dptx_hal_common.h>
+#include <soc/dptx_hal_v2.h>
 
-#define MTK_DP_TRAIN_VOLTAGE_LEVEL_RETRY	5
-#define MTK_DP_TRAIN_DOWNSCALE_RETRY		10
+#define DP_LINKRATE_RBR_VAL	0x1
+#define DP_LINKRATE_HBR_VAL	0x4
+#define DP_LINKRATE_HBR2_VAL	0x7
+#define DP_LINKRATE_HBR3_VAL	0x9
 
-enum {
-	DPTX_PATTERN_TPS1 = 1,
-	DPTX_PATTERN_TPS2,
-	DPTX_PATTERN_TPS3,
-	DPTX_PATTERN_TPS4,
-	DPTX_PATTERN_UNKNOWN,
-};
-
-void dptx_hal_swing_emp_reset(struct mtk_dp *mtk_dp);
-void dptx_hal_phy_init(struct mtk_dp *mtk_dp);
-void dptx_hal_phy_set_lanes(struct mtk_dp *mtk_dp, u8 lane_count);
-void dptx_hal_phy_wait_aux_ldo_ready(struct mtk_dp *mtk_dp);
-void dptx_hal_phy_set_idle_pattern(struct mtk_dp *mtk_dp, u8 lane_count, bool enable);
-void dptx_hal_phy_set_swing_preemphasis(struct mtk_dp *mtk_dp, u8 lane_count, u8 *swing_val,
-					u8 *preemphasis);
+#define DP_PHY_DIG_GLB_STATUS_02_OFSSET	0x146C
 
 #endif /* __SOC_MEDIATEK_MT8196_DP_DPTX_HAL_H__ */
diff --git a/src/soc/mediatek/mt8196/include/soc/dptx_reg.h b/src/soc/mediatek/mt8196/include/soc/dptx_reg.h
index 994e7cd591..df7a29630a 100644
--- a/src/soc/mediatek/mt8196/include/soc/dptx_reg.h
+++ b/src/soc/mediatek/mt8196/include/soc/dptx_reg.h
@@ -3,211 +3,12 @@
 #ifndef __SOC_MEDIATEK_MT8196_DP_DPTX_REG_H__
 #define __SOC_MEDIATEK_MT8196_DP_DPTX_REG_H__
 
-#include <soc/dptx_reg_common.h>
+#include <soc/dptx_reg_v2.h>
 
-#define WAIT_AUX_READY_RETRY_TIMES			5
-#define PHYD_DIG_GLB_OFFSET				0x1400
-#define SEC_OFFSET					0x4000
-#define IPMUX_CONTROL					(PHYD_DIG_GLB_OFFSET + 0x98)
-#define EDPTX_DSI_PHYD_SEL_FLDMASK			0x1
-#define EDPTX_DSI_PHYD_SEL_FLDMASK_POS			0
-#define TOP_OFFSET					0x2000
-#define MTK_DP_TOP_IRQ_MASK				0x202C
-#define ENCODER_IRQ_MSK					BIT(0)
-#define TRANS_IRQ_MSK					BIT(1)
-#define EDP_TX_TOP_CLKGEN_0				0x2074
-#define DP_PHY_DIG_PLL_CTL_1				0x1414
-#define DP_PHY_DIG_SW_RST				0x1438
 #define DP_PHY_DIG_TX_CTL_0				0x1474
-#define RGS_BG_CORE_EN_READY_MASK			BIT(0)
 #define RGS_AUX_LDO_EN_READY_MASK			BIT(1)
-#define REG_2004_TOP_SWING_EMP				0x2004
-#define DP_TX0_VOLT_SWING_MASK				GENMASK(1, 0)
-#define DP_TX0_PRE_EMPH_MASK				GENMASK(3, 2)
-#define DP_TX1_VOLT_SWING_MASK				GENMASK(9, 8)
-#define DP_TX1_PRE_EMPH_MASK				GENMASK(11, 10)
-#define DP_TX2_VOLT_SWING_MASK				GENMASK(17, 16)
-#define DP_TX2_PRE_EMPH_MASK				GENMASK(19, 18)
-#define DP_TX3_VOLT_SWING_MASK				GENMASK(25, 24)
-#define DP_TX3_PRE_EMPH_MASK				GENMASK(27, 26)
-#define REG_3000_DP_ENCODER0_P0				0x3000
-#define REG_BS_SYMBOL_CNT_RESET				BIT(7)
-#define REG_3004_DP_ENCODER0_P0				0x3004
-#define DP_TX_ENCODER_4P_RESET_SW_DP_ENC0_P0		BIT(9)
-#define REG_3008_DP_ENCODER0_P0				0x3008
-#define REG_300C_DP_ENCODER0_P0				0x300C
-#define REG_3010_DP_ENCODER0_P0				0x3010
-#define REG_3014_DP_ENCODER0_P0				0x3014
-#define REG_3018_DP_ENCODER0_P0				0x3018
-#define REG_301C_DP_ENCODER0_P0				0x301C
-#define REG_3020_DP_ENCODER0_P0				0x3020
-#define REG_3024_DP_ENCODER0_P0				0x3024
-#define REG_3028_DP_ENCODER0_P0				0x3028
-#define HSP_SW_DP_ENCODER0_P0_FLDMASK			0x8000
-#define HSP_SW_DP_ENCODER0_P0_FLDMASK_POS		15
-#define REG_302C_DP_ENCODER0_P0				0x302C
-#define REG_3030_DP_ENCODER0_P0				0x3030
-#define REG_3034_DP_ENCODER0_P0				0x3034
-#define DP_TEST_COLOR_FORMAT_MASK			(3 << 1)
-#define DP_TEST_COLOR_FORMAT_SHIFT			1
-#define REG_303C_DP_ENCODER0_P0				0x303C
-#define REG_3040_DP_ENCODER0_P0				0x3040
-#define REG_3044_DP_ENCODER0_P0				0x3044
-#define REG_3048_DP_ENCODER0_P0				0x3048
-#define REG_304C_DP_ENCODER0_P0				0x304C
-#define VBID_VIDEO_MUTE_DP_ENC0_4P_MASK			BIT(2)
-#define REG_3050_DP_ENCODER0_P0				0x3050
-#define REG_3054_DP_ENCODER0_P0				0x3054
-#define REG_3064_DP_ENCODER0_P0				0x3064
-#define REG_3154_DP_ENCODER0_P0				0x3154
-#define REG_3158_DP_ENCODER0_P0				0x3158
-#define REG_315C_DP_ENCODER0_P0				0x315C
-#define REG_3160_DP_ENCODER0_P0				0x3160
-#define REG_3164_DP_ENCODER0_P0				0x3164
-#define REG_3168_DP_ENCODER0_P0				0x3168
-#define REG_316C_DP_ENCODER0_P0				0x316C
-#define REG_3170_DP_ENCODER0_P0				0x3170
-#define REG_3174_DP_ENCODER0_P0				0x3174
-#define REG_3178_DP_ENCODER0_P0				0x3178
-#define REG_31EC_DP_ENCODER0_P0				0x31EC
-#define REG_3300_DP_ENCODER1_P0				0x3300
-#define REG_3364_DP_ENCODER1_P0				0x3364
-#define REG_3368_DP_ENCODER1_P0				0x3368
-#define BS2BS_MODE_DP_ENC1_4P_VAL			1
-#define BS2BS_MODE_DP_ENCODER1_P0_FLDMASK		0x3000
-#define DP_I_MODE_ENABLE				BIT(6)
-#define REG_33C0_DP_ENCODER1_P0				0x33C0
-#define REG_33C4_DP_ENCODER1_P0				0x33C4
-#define REG_33C8_DP_ENCODER1_P0				0x33C8
-#define REG_3400_DP_TRANS_P0				0x3400
-#define PATTERN1_EN_DP_TRANS_4P_TPS1			BIT(12)
-#define PATTERN2_EN_DP_TRANS_4P_TPS2			BIT(13)
-#define PATTERN3_EN_DP_TRANS_4P_TPS3			BIT(14)
-#define PATTERN4_EN_DP_TRANS_4P_TPS4			BIT(15)
-#define PATTERN_EN_DP_TRANS_4P_MASK			GENMASK(15, 12)
-#define REG_3404_DP_TRANS_P0				0x3404
-#define REG_340C_DP_TRANS_P0				0x340C
-#define REG_3418_DP_TRANS_P0				0x3418
-#define REG_342C_DP_TRANS_P0				0x342C
-#define REG_34A4_DP_TRANS_P0				0x34A4
-#define REG_3540_DP_TRANS_P0				0x3540
-#define REG_3580_DP_TRANS_P0				0x3580
-#define POST_MISC_DATA_LANE0_OV_DP_TRANS_4P_MASK	BIT(8)
-#define POST_MISC_DATA_LANE1_OV_DP_TRANS_4P_MASK	BIT(9)
-#define POST_MISC_DATA_LANE2_OV_DP_TRANS_4P_MASK	BIT(10)
-#define POST_MISC_DATA_LANE3_OV_DP_TRANS_4P_MASK	BIT(11)
-#define POST_MISC_DATA_LANE_OV_DP_TRANS_4P_MASK		GENMASK(11, 8)
-#define REG_35F0_DP_TRANS_P0				0x35F0
-#define REG_360C_AUX_TX_P0				0x360C
-#define REG_3614_AUX_TX_P0				0x3614
-#define AUX_RX_UI_CNT_THR_AUX_FOR_26M			13
-#define REG_3618_AUX_TX_P0				0x3618
-#define AUX_RX_FIFO_FULL_AUX_TX_P0_FLDMASK		0x200
-#define REG_3620_AUX_TX_P0				0x3620
-#define AUX_RD_MODE_AUX_TX_P0_FLDMASK			0x200
-#define AUX_RD_MODE_AUX_TX_P0_FLDMASK_POS		9
-#define AUX_RX_FIFO_READ_PULSE_TX_P0_FLDMASK		0x100
-#define AUX_RX_FIFO_R_PULSE_TX_P0_FLDMASK_POS		8
-#define REG_3624_AUX_TX_P0				0x3624
-#define REG_3628_AUX_TX_P0				0x3628
-#define REG_362C_AUX_TX_P0				0x362C
-#define AUX_NO_LENGTH_AUX_TX_P0_FLDMASK			0x1
-#define AUX_NO_LENGTH_AUX_TX_P0_FLDMASK_POS		0
-#define REG_3630_AUX_TX_P0				0x3630
-#define AUX_TX_REQUEST_READY_AUX_TX_P0_FLDMASK		0x8
-#define AUX_TX_REQUEST_READY_AUX_TX_P0_FLDMASK_POS	3
-#define REG_3634_AUX_TX_P0				0x3634
-#define AUX_TX_OVER_SAMPLE_RATE_FOR_26M			25
-#define REG_3640_AUX_TX_P0				0x3640
-#define AUX_RX_RECV_COMPLETE_IRQ_TX_P0_FLDMASK		0x40
-#define AUX_400US_TIMEOUT_IRQ_AUX_TX_P0_FLDMASK		0x1
-#define REG_3644_AUX_TX_P0				0x3644
-#define REG_3648_AUX_TX_P0				0x3648
-#define REG_364C_AUX_TX_P0				0x364C
-#define HPD_INT_THD_FLDMASK_VAL				0x32
-#define HPD_INT_THD_FLDMASK				0x3F0
-#define REG_3650_AUX_TX_P0				0x3650
-#define MCU_REQUEST_DATA_NUM_AUX_TX_P0_FLDMASK		0xf000
-#define MCU_REQ_DATA_NUM_AUX_TX_P0_FLDMASK_POS		12
-#define MCU_ACK_TRANSACTION_COMPLETE_AUX_TX_P0_FLDMASK	0x100
-#define MCU_ACK_TRAN_COMPLETE_AUX_TX_P0_FLDMASK_POS	8
-#define REG_3658_AUX_TX_P0				0x3658
-#define REG_366C_AUX_TX_P0				0x366C
-#define XTAL_FREQ_DP_TX_AUX_366C_VALUE			0x68
-#define XTAL_FREQ_DP_TX_AUX_366C_MASK			0xFF00
-#define REG_367C_AUX_TX_P0				0x367C
-#define HPD_CONN_THD_AUX_TX_P0_FLDMASK_POS		5
-#define HPD_CONN_THD_AUX_TX_P0_FLDMASK			0x3c0
-#define REG_3690_AUX_TX_P0				0x3690
-#define RX_REPLY_COMPLETE_MODE_AUX_TX_4P		BIT(8)
-#define REG_36A0_AUX_TX_4P				0x36A0
-#define REG_3704_AUX_TX_P0				0x3704
-#define AUX_TX_FIFO_WRITE_DATA_TOGGLE_AUX_TX_P0_FLDMASK 0x2
-#define AUX_TX_FIFO_NEW_MODE_EN_AUX_TX_P0_FLDMASK	0x4
-#define AUX_TX_FIFO_NEW_MODE_EN_AUX_TX_P0_FLDMASK_POS	2
-#define REG_3708_AUX_TX_P0				0x3708
-#define REG_37A0_AUX_TX_P0				0x37A0
-#define HPD_DISC_THD_AUX_TX_P0_FLDMASK_POS		5
-#define HPD_DISC_THD_AUX_TX_P0_FLDMASK			0xF0
-#define REG_37C8_AUX_TX_P0				0x37C8
-#define MTK_ATOP_EN_AUX_TX_4P				BIT(0)
-#define REG_3F04_DP_ENC_4P_3				0x3F04
-#define REG_3F08_DP_ENC_4P_3				0x3F08
-#define REG_3F0C_DP_ENC_4P_3				0x3F0C
-#define REG_3F10_DP_ENC_4P_3				0x3F10
-#define REG_3F28_DP_ENC_4P_3				0x3F28
-#define REG_3F44_DP_ENC_4P_3				0x3F44
-#define PHY_PWR_STATE_OW_EN_DP_ENC_4P_3			BIT(2)
-#define PHY_PWR_STATE_OW_EN_DP_ENC_4P_3_MASK		BIT(2)
-#define BIAS_POWER_ON					(0x01 << 3)
-#define PHY_PWR_STATE_OW_VALUE_DP_ENC_4P_3_MASK		GENMASK(4, 3)
-#define REG_3F80_DP_ENC_4P_3				0x3F80
-#define PSR_PATGEN_AVT_EN_FLDMASK			0x20
-#define REG_3FF8_DP_ENC_4P_3				0x3FF8
-#define PHY_STATE_W_1_DP_ENC_4P_3			BIT(6)
-#define PHY_STATE_W_1_DP_ENC_4P_3_MASK			BIT(6)
-#define DVO_ON_W_1_FLDMASK				0x20
-#define XTAL_FREQ_FOR_PSR_DP_ENC_4P_3_VALUE		25
-#define XTAL_FREQ_FOR_PSR_DP_ENC_4P_3_MASK		0x3E00
-#define PHYD_DIG_LAN0_OFFSET				0x1000
-#define PHYD_DIG_LAN1_OFFSET				0x1100
-#define PHYD_DIG_LAN2_OFFSET				0x1200
-#define PHYD_DIG_LAN3_OFFSET				0x1300
 #define DRIVING_FORCE					0x30
-#define EDP_TX_LN_VOLT_SWING_VAL_MASK			GENMASK(2, 1)
 #define EDP_TX_LN_PRE_EMPH_VAL_MASK			GENMASK(4, 3)
-#define DP_TX_TOP_APB_WSTRB				(TOP_OFFSET + 0x10)
-#define DP_TX_TOP_RESET_AND_PROBE			(TOP_OFFSET + 0x20)
-#define DP_TX_SECURE_REG11				(SEC_OFFSET + 0x2C)
-#define DP_LANE_COUNT_ENHANCED_FRAME_EN			(1 << 7)
-#define DPCD_00000					0x00000
-#define DPCD_0000E					0x0000E
-#define DPCD_00021					0x00021
-#define DPCD_00100					0x00100
-#define DPCD_00101					0x00101
-#define DPCD_00102					0x00102
-#define DP_TRAINING_PATTERN_DISABLE			0
-#define DP_TRAINING_PATTERN_1				1
-#define DP_TRAINING_PATTERN_2				2
-#define DP_TRAINING_PATTERN_3				3 /* 1.2 */
-#define DP_TRAINING_PATTERN_4				7 /* 1.4 */
-#define DP_LINK_SCRAMBLING_DISABLE			BIT(5)
-#define DPCD_00103					0x00103
-#define DP_TRAIN_VOLTAGE_SWING_SHIFT			0
-#define DP_TRAIN_MAX_SWING_REACHED			BIT(2)
-#define DP_TRAIN_PRE_EMPHASIS_SHIFT			3
-#define DP_TRAIN_MAX_PRE_EMPHASIS_REACHED		BIT(5)
-#define DPCD_00107					0x00107
-#define DP_SPREAD_AMP_0_5				BIT(4)
-#define DPCD_00200					0x00200
-#define DPCD_00202					0x00202
-#define DPCD_00206					0x00206
-#define DP_ADJUST_VOLTAGE_SWING_LANE0_MASK		0x03
-#define DP_ADJUST_PRE_EMPHASIS_LANE0_MASK		0x0C
-#define DP_ADJUST_PRE_EMPHASIS_LANE0_SHIFT		2
-#define DP_ADJUST_VOLTAGE_SWING_LANE1_SHIFT		4
-#define DPCD_00600					0x00600
-#define DPCD_02002					0x02002
-#define DPCD_02003					0x02003
+#define EDP_TX_LN_PRE_EMPH_VAL_SHIFT			3
 
 #endif /* __SOC_MEDIATEK_MT8196_DP_DPTX_REG_H__ */

From f63016c36f9ee41269bd8e3a96e6dfd09f50e956 Mon Sep 17 00:00:00 2001
From: Vince Liu <vince-wl.liu@mediatek.corp-partner.google.com>
Date: Fri, 20 Jun 2025 10:44:12 +0800
Subject: [PATCH 1353/3886] soc/mediatek: Unify DPTX swing/preemphasis API

Right now dptx_hal_v2 has defined its own
dptx_hal_phy_set_swing_preemphasis, without utilizing the existing
dptx_hal_setswing_preemphasis defined in dptx_hal_common.h.
dptx_hal_v2.c also implements dptx_hal_setswing_preemphasis, but it's
never used.

To reduce duplicate code, rename dptx_hal_setswing_preemphasis in the
common API to dptx_hal_set_swing_preemphasis, and use it for the
dptx_hal_v2 code. Also fix the type for the `lane_count` argument, and
change variable names to make dptx_hal_v1 and dptx_hal_v2 more
consistent.

BUG=none
TEST=emerge-rauru coreboot
BRANCH=none

Change-Id: Id252d29fd1205a949c903d5560f44efc2ff7f477
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88150
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
---
 src/soc/mediatek/common/dp/dptx_hal_v1.c      | 28 ++++---
 src/soc/mediatek/common/dp/dptx_hal_v2.c      | 35 +++------
 src/soc/mediatek/common/dp/dptx_v1.c          | 74 ++++++++-----------
 src/soc/mediatek/common/dp/dptx_v2.c          |  2 +-
 .../common/dp/include/soc/dptx_hal_common.h   |  6 +-
 .../common/dp/include/soc/dptx_hal_v2.h       |  2 -
 src/soc/mediatek/mt8196/dptx_hal.c            |  4 +-
 7 files changed, 60 insertions(+), 91 deletions(-)

diff --git a/src/soc/mediatek/common/dp/dptx_hal_v1.c b/src/soc/mediatek/common/dp/dptx_hal_v1.c
index 91fbddf692..1bf9b71bb4 100644
--- a/src/soc/mediatek/common/dp/dptx_hal_v1.c
+++ b/src/soc/mediatek/common/dp/dptx_hal_v1.c
@@ -1,5 +1,6 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
+#include <assert.h>
 #include <console/console.h>
 #include <device/mmio.h>
 #include <delay.h>
@@ -78,24 +79,21 @@ bool dptx_hal_hpd_high(struct mtk_dp *mtk_dp)
 	return mtk_dp_read(mtk_dp, REG_3414_DP_TRANS_P0) & BIT(2);
 }
 
-bool dptx_hal_setswing_preemphasis(struct mtk_dp *mtk_dp, int lane_num,
-				   u8 swing_value, u8 preemphasis)
+void dptx_hal_set_swing_preemphasis(struct mtk_dp *mtk_dp, size_t lane_count,
+				    u8 *swing_value, u8 *preemphasis)
 {
-	printk(BIOS_DEBUG, "lane(%d), set swing(%#x), emp(%#x)\n",
-	       lane_num, swing_value, preemphasis);
+	assert(lane_count <= DPTX_LANE_MAX);
 
-	if (lane_num >= DPTX_LANE_MAX) {
-		printk(BIOS_ERR, "invalid lane number: %d\n", lane_num);
-		return false;
+	for (int lane = 0; lane < lane_count; lane++) {
+		printk(BIOS_DEBUG, "lane(%d), set swing(%#x), emp(%#x)\n",
+		       lane, swing_value[lane], preemphasis[lane]);
+		mtk_dp_mask(mtk_dp, DP_TX_TOP_SWING_EMP,
+			    swing_value[lane] << volt_swing[lane].shift,
+			    volt_swing[lane].mask);
+		mtk_dp_mask(mtk_dp, DP_TX_TOP_SWING_EMP,
+			    preemphasis[lane] << volt_preemphasis[lane].shift,
+			    volt_preemphasis[lane].mask);
 	}
-
-	mtk_dp_mask(mtk_dp, DP_TX_TOP_SWING_EMP,
-		    swing_value << volt_swing[lane_num].shift,
-		    volt_swing[lane_num].mask);
-	mtk_dp_mask(mtk_dp, DP_TX_TOP_SWING_EMP,
-		    preemphasis << volt_preemphasis[lane_num].shift,
-		    volt_preemphasis[lane_num].mask);
-	return true;
 }
 
 void dptx_hal_reset_swing_preemphasis(struct mtk_dp *mtk_dp)
diff --git a/src/soc/mediatek/common/dp/dptx_hal_v2.c b/src/soc/mediatek/common/dp/dptx_hal_v2.c
index 7000d89472..0833f2de62 100644
--- a/src/soc/mediatek/common/dp/dptx_hal_v2.c
+++ b/src/soc/mediatek/common/dp/dptx_hal_v2.c
@@ -86,21 +86,19 @@ bool dptx_hal_hpd_high(struct mtk_dp *mtk_dp)
 	return mtk_dp_read(mtk_dp, REG_364C_AUX_TX_P0) & BIT(15);
 }
 
-bool dptx_hal_setswing_preemphasis(struct mtk_dp *mtk_dp, int lane_num, u8 swing_value,
-				   u8 preemphasis)
+void dptx_hal_set_swing_preemphasis(struct mtk_dp *mtk_dp, size_t lane_count,
+				    u8 *swing_value, u8 *preemphasis)
 {
-	assert(lane_num <= DPTX_LANE_MAX);
+	assert(lane_count <= DPTX_LANE_MAX);
 
-	for (int i = 0; i < lane_num; ++i) {
-		mtk_dp_phy_mask(mtk_dp, dptx_hal_driving_offset[i],
-				swing_value << EDP_TX_LN_VOLT_SWING_VAL_SHIFT |
-				preemphasis << EDP_TX_LN_PRE_EMPH_VAL_SHIFT,
-				EDP_TX_LN_VOLT_SWING_VAL_MASK | EDP_TX_LN_PRE_EMPH_VAL_MASK);
+	for (int lane = 0; lane < lane_count; lane++) {
 		printk(BIOS_DEBUG, "lane(%d), set swing(%u), emp(%u)\n",
-		       i, swing_value, preemphasis);
+		       lane, swing_value[lane], preemphasis[lane]);
+		mtk_dp_phy_mask(mtk_dp, dptx_hal_driving_offset[lane],
+				swing_value[lane] << EDP_TX_LN_VOLT_SWING_VAL_SHIFT |
+				preemphasis[lane] << EDP_TX_LN_PRE_EMPH_VAL_SHIFT,
+				EDP_TX_LN_VOLT_SWING_VAL_MASK | EDP_TX_LN_PRE_EMPH_VAL_MASK);
 	}
-	mtk_dp_mask(mtk_dp, 0x2000, GENMASK(1, 0), GENMASK(1, 0));
-	return true;
 }
 
 void dptx_hal_hpd_detect_setting(struct mtk_dp *mtk_dp)
@@ -315,21 +313,6 @@ void dptx_hal_set_txlane(struct mtk_dp *mtk_dp, u8 value)
 	mtk_dp_mask(mtk_dp, REG_34A4_DP_TRANS_P0, value << 2, BIT(3) | BIT(2));
 }
 
-void dptx_hal_phy_set_swing_preemphasis(struct mtk_dp *mtk_dp, u8 lane_count, u8 *swing_val,
-					 u8 *preemphasis)
-{
-	assert(lane_count <= DPTX_LANE_MAX);
-
-	for (int i = 0; i < lane_count; ++i) {
-		mtk_dp_phy_mask(mtk_dp, dptx_hal_driving_offset[i],
-				swing_val[i] << EDP_TX_LN_VOLT_SWING_VAL_SHIFT |
-				preemphasis[i] << EDP_TX_LN_PRE_EMPH_VAL_SHIFT,
-				EDP_TX_LN_VOLT_SWING_VAL_MASK | EDP_TX_LN_PRE_EMPH_VAL_MASK);
-		printk(BIOS_DEBUG, "lane(%d), set swing(%u), emp(%u)\n",
-		       i, swing_val[i], preemphasis[i]);
-	}
-}
-
 void dptx_hal_phy_set_idle_pattern(struct mtk_dp *mtk_dp, u8 lane_count, bool enable)
 {
 	u32 val = 0x0;
diff --git a/src/soc/mediatek/common/dp/dptx_v1.c b/src/soc/mediatek/common/dp/dptx_v1.c
index 6cf590d417..7001282128 100644
--- a/src/soc/mediatek/common/dp/dptx_v1.c
+++ b/src/soc/mediatek/common/dp/dptx_v1.c
@@ -1,5 +1,6 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
+#include <assert.h>
 #include <commonlib/bsd/helpers.h>
 #include <console/console.h>
 #include <delay.h>
@@ -12,112 +13,101 @@
 #include <soc/dp_intf.h>
 #include <string.h>
 
-static bool dptx_training_checkswingpre(struct mtk_dp *mtk_dp,
+static void dptx_training_checkswingpre(struct mtk_dp *mtk_dp,
 					u8 target_lane_count,
 					const u8 *dpcp202_x, u8 *dpcp_buf)
 {
-	bool ret = true;
-	u8 swing_value, preemphasis;
+	u8 swing_value[DPTX_LANE_MAX] = {0}, preemphasis[DPTX_LANE_MAX] = {0};
+
+	assert(target_lane_count <= DPTX_LANE_MAX);
 
 	/* Lane 0 */
 	if (target_lane_count >= 0x1) {
-		swing_value = (dpcp202_x[4] & 0x3);
-		preemphasis = (dpcp202_x[4] & 0xc) >> 2;
-
-		/* Adjust the swing and pre-emphasis */
-		ret &= dptx_hal_setswing_preemphasis(mtk_dp, DPTX_LANE0,
-						     swing_value, preemphasis);
+		swing_value[0] = (dpcp202_x[4] & 0x3);
+		preemphasis[0] = (dpcp202_x[4] & 0xc) >> 2;
 
 		/*
 		 * Adjust the swing and pre-emphasis done,
 		 * and notify sink side.
 		 */
-		dpcp_buf[0] = swing_value | (preemphasis << 3);
+		dpcp_buf[0] = swing_value[0] | (preemphasis[0] << 3);
 
 		/* Max swing reached. */
-		if (swing_value == DPTX_SWING3)
+		if (swing_value[0] == DPTX_SWING3)
 			dpcp_buf[0] |= BIT(2);
 
 		/* Max pre-emphasis reached. */
-		if (preemphasis == DPTX_PREEMPHASIS3)
+		if (preemphasis[0] == DPTX_PREEMPHASIS3)
 			dpcp_buf[0] |= BIT(5);
 	}
 
 	/* Lane 1 */
 	if (target_lane_count >= 0x2) {
-		swing_value = (dpcp202_x[4] & 0x30) >> 4;
-		preemphasis = (dpcp202_x[4] & 0xc0) >> 6;
-
-		/* Adjust the swing and pre-emphasis */
-		ret &= dptx_hal_setswing_preemphasis(mtk_dp, DPTX_LANE1,
-						     swing_value, preemphasis);
+		swing_value[1] = (dpcp202_x[4] & 0x30) >> 4;
+		preemphasis[1] = (dpcp202_x[4] & 0xc0) >> 6;
 
 		/*
 		 * Adjust the swing and pre-emphasis done,
 		 * and notify sink side.
 		 */
-		dpcp_buf[1] = swing_value | (preemphasis << 3);
+		dpcp_buf[1] = swing_value[1] | (preemphasis[1] << 3);
 
 		/* Max swing reached. */
-		if (swing_value == DPTX_SWING3)
+		if (swing_value[1] == DPTX_SWING3)
 			dpcp_buf[1] |= BIT(2);
 
 		/* Max pre-emphasis reached. */
-		if (preemphasis == DPTX_PREEMPHASIS3)
+		if (preemphasis[1] == DPTX_PREEMPHASIS3)
 			dpcp_buf[1] |= BIT(5);
 	}
 
 	/* Lane 2 and Lane 3 */
-	if (target_lane_count == 0x4) {
-		/* Lane 2 */
-		swing_value = (dpcp202_x[5] & 0x3);
-		preemphasis = (dpcp202_x[5] & 0x0c) >> 2;
+	if (target_lane_count >= 0x3) {
+		assert(target_lane_count == 0x4);
 
-		/* Adjust the swing and pre-emphasis */
-		ret &= dptx_hal_setswing_preemphasis(mtk_dp, DPTX_LANE2,
-						     swing_value, preemphasis);
+		/* Lane 2 */
+		swing_value[2] = (dpcp202_x[5] & 0x3);
+		preemphasis[2] = (dpcp202_x[5] & 0x0c) >> 2;
 
 		/*
 		 * Adjust the swing and pre-emphasis done,
 		 * and notify sink side.
 		 */
-		dpcp_buf[2] = swing_value | (preemphasis << 3);
+		dpcp_buf[2] = swing_value[2] | (preemphasis[2] << 3);
 
 		/* Max swing reached. */
-		if (swing_value == DPTX_SWING3)
+		if (swing_value[2] == DPTX_SWING3)
 			dpcp_buf[2] |= BIT(2);
 
 		/* Max pre-emphasis reached. */
-		if (preemphasis == DPTX_PREEMPHASIS3)
+		if (preemphasis[2] == DPTX_PREEMPHASIS3)
 			dpcp_buf[2] |= BIT(5);
 
 		/* Lane 3 */
-		swing_value = (dpcp202_x[5] & 0x30) >> 4;
-		preemphasis = (dpcp202_x[5] & 0xc0) >> 6;
-
-		/* Adjust the swing and pre-emphasis */
-		ret &= dptx_hal_setswing_preemphasis(mtk_dp, DPTX_LANE3,
-						     swing_value, preemphasis);
+		swing_value[3] = (dpcp202_x[5] & 0x30) >> 4;
+		preemphasis[3] = (dpcp202_x[5] & 0xc0) >> 6;
 
 		/*
 		 * Adjust the swing and pre-emphasis done,
 		 * and notify sink side.
 		 */
-		dpcp_buf[0x3] = swing_value | (preemphasis << 3);
+		dpcp_buf[0x3] = swing_value[3] | (preemphasis[3] << 3);
 
 		/* Max swing reached. */
-		if (swing_value == DPTX_SWING3)
+		if (swing_value[3] == DPTX_SWING3)
 			dpcp_buf[3] |= BIT(2);
 
 		/* Max pre-emphasis reached. */
-		if (preemphasis == DPTX_PREEMPHASIS3)
+		if (preemphasis[3] == DPTX_PREEMPHASIS3)
 			dpcp_buf[3] |= BIT(5);
 	}
 
+	/* Adjust the swing and pre-emphasis */
+	dptx_hal_set_swing_preemphasis(mtk_dp, target_lane_count,
+				       swing_value, preemphasis);
+
 	/* Wait signal stable enough */
 	mdelay(2);
-
-	return ret;
 }
 
 static int dptx_train_tps1(struct mtk_dp *mtk_dp, u8 target_lanecount,
diff --git a/src/soc/mediatek/common/dp/dptx_v2.c b/src/soc/mediatek/common/dp/dptx_v2.c
index 80e1f7c33e..ab41b86ed2 100644
--- a/src/soc/mediatek/common/dp/dptx_v2.c
+++ b/src/soc/mediatek/common/dp/dptx_v2.c
@@ -81,7 +81,7 @@ static void update_swing_preemphasis(struct mtk_dp *mtk_dp, u8 lane_count,
 		dptx_auxwrite_dpcd(mtk_dp, DP_AUX_NATIVE_WRITE, DPCD_00103 + lane, 0x1, &val);
 	}
 
-	dptx_hal_phy_set_swing_preemphasis(mtk_dp, lane_count, swing_val, preemphasis);
+	dptx_hal_set_swing_preemphasis(mtk_dp, lane_count, swing_val, preemphasis);
 }
 
 static void dptx_training_changemode(struct mtk_dp *mtk_dp)
diff --git a/src/soc/mediatek/common/dp/include/soc/dptx_hal_common.h b/src/soc/mediatek/common/dp/include/soc/dptx_hal_common.h
index 9c553181c7..ecd1132bdf 100644
--- a/src/soc/mediatek/common/dp/include/soc/dptx_hal_common.h
+++ b/src/soc/mediatek/common/dp/include/soc/dptx_hal_common.h
@@ -62,8 +62,9 @@ bool dptx_hal_auxread_bytes(struct mtk_dp *mtk_dp, u8 cmd,
 			    u32 dpcd_addr, size_t length, u8 *rx_buf);
 bool dptx_hal_auxwrite_bytes(struct mtk_dp *mtk_dp, u8 cmd,
 			     u32 dpcd_addr, size_t length, u8 *data);
-bool dptx_hal_setswing_preemphasis(struct mtk_dp *mtk_dp, int lane_num,
-				   u8 swing_value, u8 preemphasis);
+void dptx_hal_set_swing_preemphasis(struct mtk_dp *mtk_dp, size_t lane_count,
+				    u8 *swing_value, u8 *preemphasis);
+void dptx_hal_reset_swing_preemphasis(struct mtk_dp *mtk_dp);
 u8 dptx_hal_get_colorbpp(struct mtk_dp *mtk_dp);
 u32 mtk_dp_phy_read(struct mtk_dp *mtk_dp, u32 offset);
 void mtk_dp_phy_mask(struct mtk_dp *mtk_dp, u32 offset, u32 val, u32 mask);
@@ -73,7 +74,6 @@ void mtk_dp_write_byte(struct mtk_dp *mtk_dp, u32 addr, u8 val, u8 mask);
 void mtk_dp_mask(struct mtk_dp *mtk_dp, u32 offset, u32 val, u32 mask);
 void mtk_dp_write(struct mtk_dp *mtk_dp, u32 offset, u32 val);
 void dptx_hal_verify_clock(struct mtk_dp *mtk_dp);
-void dptx_hal_reset_swing_preemphasis(struct mtk_dp *mtk_dp);
 void dptx_hal_digital_swreset(struct mtk_dp *mtk_dp);
 void dptx_hal_ssc_en(struct mtk_dp *mtk_dp, bool enable);
 void dptx_hal_hpd_int_en(struct mtk_dp *mtk_dp, bool enable);
diff --git a/src/soc/mediatek/common/dp/include/soc/dptx_hal_v2.h b/src/soc/mediatek/common/dp/include/soc/dptx_hal_v2.h
index e076915e92..7f49e5608b 100644
--- a/src/soc/mediatek/common/dp/include/soc/dptx_hal_v2.h
+++ b/src/soc/mediatek/common/dp/include/soc/dptx_hal_v2.h
@@ -24,7 +24,5 @@ void dptx_hal_phy_init(struct mtk_dp *mtk_dp);
 void dptx_hal_phy_wait_aux_ldo_ready(struct mtk_dp *mtk_dp);
 void dptx_hal_phy_set_idle_pattern(struct mtk_dp *mtk_dp, u8 lane_count, bool enable);
 void dptx_hal_phy_set_lanes(struct mtk_dp *mtk_dp, u8 lane_count);
-void dptx_hal_phy_set_swing_preemphasis(struct mtk_dp *mtk_dp, u8 lane_count, u8 *swing_val,
-					u8 *preemphasis);
 
 #endif /* SOC_MEDIATEK_COMMON_DP_DPTX_HAL_V2_H */
diff --git a/src/soc/mediatek/mt8196/dptx_hal.c b/src/soc/mediatek/mt8196/dptx_hal.c
index f2ec6541b3..110f5f1ada 100644
--- a/src/soc/mediatek/mt8196/dptx_hal.c
+++ b/src/soc/mediatek/mt8196/dptx_hal.c
@@ -6,7 +6,7 @@
 #include <soc/dptx_hal.h>
 #include <soc/dptx_reg.h>
 
-static void dptx_hal_phy_reset_swing_preemphasis(struct mtk_dp *mtk_dp)
+void dptx_hal_reset_swing_preemphasis(struct mtk_dp *mtk_dp)
 {
 	for (int i = 0; i < dptx_hal_driving_offset_size; i++)
 		mtk_dp_phy_mask(mtk_dp, dptx_hal_driving_offset[i], 0,
@@ -37,5 +37,5 @@ void dptx_hal_phyd_reset(struct mtk_dp *mtk_dp)
 	printk(BIOS_DEBUG, "[eDPTX] DP_PHY_DIG_TX_CTL_0:%#x\n",
 	       mtk_dp_phy_read(mtk_dp, DP_PHY_DIG_TX_CTL_0));
 
-	dptx_hal_phy_reset_swing_preemphasis(mtk_dp);
+	dptx_hal_reset_swing_preemphasis(mtk_dp);
 }

From 43b6f44e22fd59b62f02539ea58533b52cfd7b01 Mon Sep 17 00:00:00 2001
From: Zhigang Qin <zhigang.qin@mediatek.corp-partner.google.com>
Date: Wed, 18 Jun 2025 14:00:20 +0800
Subject: [PATCH 1354/3886] soc/mediatek/mt8189: Remove ulposc1 hardware
 calibration

Skywalker board with MT8189 uses software calibration for ulposc1 (ultra
low power oscillator) and does not support hardware calibration. Remove
the hardware calibration code accordingly.

BUG=b:423516707
BRANCH=none
TEST=build pass and boot up normally.

Signed-off-by: Zhigang Qin <zhigang.qin@mediatek.corp-partner.google.com>
Change-Id: Iea4a0fd8f2c41b54880cef6647e90e0dd1d2bcf1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88151
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
---
 src/soc/mediatek/mt8189/pmif_clk.c | 36 ++++--------------------------
 1 file changed, 4 insertions(+), 32 deletions(-)

diff --git a/src/soc/mediatek/mt8189/pmif_clk.c b/src/soc/mediatek/mt8189/pmif_clk.c
index 8a38f8568f..5e4bbe3e15 100644
--- a/src/soc/mediatek/mt8189/pmif_clk.c
+++ b/src/soc/mediatek/mt8189/pmif_clk.c
@@ -13,9 +13,6 @@
 #include <soc/spm.h>
 #include <soc/spm_mtcmos.h>
 
-#define ULPOSC1_CHECK_RETRY_COUNT 5
-#define ULPOSC1_HW_CALI_VAL 0x11f10054
-
 DEFINE_BITFIELD(CLK_EN, 18, 0)
 
 /* APMIXED, ULPOSC1_CON0 */
@@ -112,35 +109,10 @@ static int pmif_init_ulposc(void)
 
 int pmif_clk_init(void)
 {
-	bool sw_cali = false;
-	u32 cali_val;
-
-	for (int i = 0; i < ULPOSC1_CHECK_RETRY_COUNT; i++) {
-		cali_val = mt_get_vlpck_freq(FREQ_METER_VLP_OSC_CK) / 1000;
-		if (pmif_ulposc_check(cali_val, PMIF_TARGET_FREQ_MHZ) != 0) {
-			sw_cali = true;
-			break;
-		}
-	}
-
-	if (sw_cali) {
-		/* initialize pmif clock */
-		printk(BIOS_INFO, "Using SW calibration!\n");
-		if (pmif_init_ulposc())
-			return E_NODEV;
-	} else {
-		printk(BIOS_INFO, "Using HW calibration!\n");
-		/* set calibration value */
-		cali_val = read32p(ULPOSC1_HW_CALI_VAL);
-		printk(BIOS_INFO, "calibration pre value: %#x, PLL_ULPOSC1_CON0 value: %#x\n",
-		       cali_val, read32(&mtk_vlpsys->vlp_ulposc1_con0));
-		SET32_BITFIELDS(&mtk_vlpsys->vlp_ulposc1_con0, OSC1_CALI,
-				(cali_val >> 1) & 0x7F);
-		SET32_BITFIELDS(&mtk_vlpsys->vlp_clk_cfg_30_set, CLK_EN, 0x70000);
-		pmif_turn_on_ulposc();
-		printk(BIOS_INFO, "PLL_ULPOSC1_CON0: 0x%x\n",
-		       read32(&mtk_vlpsys->vlp_ulposc1_con0));
-	}
+	/* initialize pmif clock */
+	printk(BIOS_INFO, "Using SW calibration!\n");
+	if (pmif_init_ulposc())
+		return E_NODEV;
 
 	/* turn off pmic_cg_tmr, cg_ap, cg_md, cg_conn clock */
 	SET32_BITFIELDS(&mtk_vlpsys->vlp_clk_cfg[0].clr, CLK_PWRAP_ULPOSC_SEL, 0x7,

From ba715b3d25ab8bc0440f94a4c5c9947344a99b1c Mon Sep 17 00:00:00 2001
From: Brian Hsu <Brian_Hsu@pegatron.corp-partner.google.com>
Date: Sat, 17 May 2025 15:51:38 +0800
Subject: [PATCH 1355/3886] mb/google/nissa/var/guren: Add SPD ID for
 MT62F512M32D2DR-031 WT:B

Support memory of Micron MT62F512M32D2DR-031 WT:B in mem_parts_used list, and generate SPD ID for this part.

DRAM Part Name            Vendor  Model Spec        ID to assign
MT62F512M32D2DR-031 WT:B  Micron  LPDDR5 6400 16GB  3 (0011)

BUG=424688292
BRANCH=firmware-nissa-15217.B
TEST=Run command "go run ./util/spd_tools/src/part_id_gen/part_id_gen.go ADL lp5 src/mainboard/google/brya/variants/guren/memory/ src/mainboard/google/brya/variants/guren/memory/mem_parts_used.txt"

Change-Id: I310e48a8f240646ec631f0cbc8c0ad0b57e26e0d
Signed-off-by: Brian Hsu <Brian_Hsu@pegatron.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88091
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/google/brya/variants/guren/memory/Makefile.mk   | 4 ++--
 .../google/brya/variants/guren/memory/dram_id.generated.txt   | 3 ++-
 .../google/brya/variants/guren/memory/mem_parts_used.txt      | 1 +
 3 files changed, 5 insertions(+), 3 deletions(-)

diff --git a/src/mainboard/google/brya/variants/guren/memory/Makefile.mk b/src/mainboard/google/brya/variants/guren/memory/Makefile.mk
index 87fd132c6f..ccbfe532f5 100644
--- a/src/mainboard/google/brya/variants/guren/memory/Makefile.mk
+++ b/src/mainboard/google/brya/variants/guren/memory/Makefile.mk
@@ -1,13 +1,13 @@
 # SPDX-License-Identifier: GPL-2.0-or-later
 # This is an auto-generated file. Do not edit!!
 # Generated by:
-# /tmp/go-build3837031112/b001/exe/part_id_gen ADL lp5 src/mainboard/google/brya/variants/guren/memory/ src/mainboard/google/brya/variants/guren/memory/mem_parts_used.txt
+# /tmp/go-build3687052440/b001/exe/part_id_gen ADL lp5 src/mainboard/google/brya/variants/guren/memory/ src/mainboard/google/brya/variants/guren/memory/mem_parts_used.txt
 
 SPD_SOURCES =
 SPD_SOURCES += spd/lp5/set-0/spd-7.hex      # ID = 0(0b0000)  Parts = K3KL8L80CM-MGCT
 SPD_SOURCES += spd/lp5/set-0/spd-9.hex      # ID = 1(0b0001)  Parts = K3KL6L60GM-MGCT
 SPD_SOURCES += spd/lp5/set-0/spd-3.hex      # ID = 2(0b0010)  Parts = H58G56AK6BX069, K3LKBKB0BM-MGCP
-SPD_SOURCES += spd/lp5/set-0/spd-1.hex      # ID = 3(0b0011)  Parts = H9JCNNNBK3MLYR-N6E
+SPD_SOURCES += spd/lp5/set-0/spd-1.hex      # ID = 3(0b0011)  Parts = H9JCNNNBK3MLYR-N6E, MT62F512M32D2DR-031 WT:B
 SPD_SOURCES += spd/lp5/set-0/spd-6.hex      # ID = 4(0b0100)  Parts = H58G66AK6BX070
 SPD_SOURCES += spd/lp5/set-0/spd-8.hex      # ID = 5(0b0101)  Parts = K3KL9L90CM-MGCT
 SPD_SOURCES += spd/lp5/set-0/spd-11.hex      # ID = 6(0b0110)  Parts = H58G56CK8BX146
diff --git a/src/mainboard/google/brya/variants/guren/memory/dram_id.generated.txt b/src/mainboard/google/brya/variants/guren/memory/dram_id.generated.txt
index cb4da42345..0ab5c7dc33 100644
--- a/src/mainboard/google/brya/variants/guren/memory/dram_id.generated.txt
+++ b/src/mainboard/google/brya/variants/guren/memory/dram_id.generated.txt
@@ -1,7 +1,7 @@
 # SPDX-License-Identifier: GPL-2.0-or-later
 # This is an auto-generated file. Do not edit!!
 # Generated by:
-# /tmp/go-build3837031112/b001/exe/part_id_gen ADL lp5 src/mainboard/google/brya/variants/guren/memory/ src/mainboard/google/brya/variants/guren/memory/mem_parts_used.txt
+# /tmp/go-build3687052440/b001/exe/part_id_gen ADL lp5 src/mainboard/google/brya/variants/guren/memory/ src/mainboard/google/brya/variants/guren/memory/mem_parts_used.txt
 
 DRAM Part Name                 ID to assign
 K3KL8L80CM-MGCT                0 (0000)
@@ -12,3 +12,4 @@ H58G66AK6BX070                 4 (0100)
 K3KL9L90CM-MGCT                5 (0101)
 K3LKBKB0BM-MGCP                2 (0010)
 H58G56CK8BX146                 6 (0110)
+MT62F512M32D2DR-031 WT:B       3 (0011)
diff --git a/src/mainboard/google/brya/variants/guren/memory/mem_parts_used.txt b/src/mainboard/google/brya/variants/guren/memory/mem_parts_used.txt
index 796d10a21c..7f045dd656 100644
--- a/src/mainboard/google/brya/variants/guren/memory/mem_parts_used.txt
+++ b/src/mainboard/google/brya/variants/guren/memory/mem_parts_used.txt
@@ -17,3 +17,4 @@ H58G66AK6BX070
 K3KL9L90CM-MGCT
 K3LKBKB0BM-MGCP
 H58G56CK8BX146
+MT62F512M32D2DR-031 WT:B

From f3f9c0bd8e2e86f305469b0bb376e17010f90e38 Mon Sep 17 00:00:00 2001
From: Appukuttan V K <appukuttan.vk@intel.com>
Date: Mon, 16 Jun 2025 13:08:11 +0530
Subject: [PATCH 1356/3886] soc/intel/ptl: Add PCIe ACPI support for Wildcat
 Lake SoC

This commit introduces PCI device details specific to Wildcat Lake
within the Panther Lake ACPI code, using conditional compilation
to differentiate configurations.

Key changes:
 - Create separate ASL files for Panther Lake (`ptl_pcie.asl`) and
   Wildcat Lake (`wcl_pcie.asl`) PCIe port configurations.
 - Introduce conditional compilation to include Panther Lake or
   Wildcat Lake ASL files.
 - Wildcat Lake-specific changes compared to Panther Lake:
       - Remove following
         - PCIe RP : 00:1c.4 to 00:1c.7
                   : 00:06.2 & 00:06.3
References:
- Wildcat Lake Processor EDS Volume 1 (#842271)
- Wildcat Lake External Design Specification (EDS) Volume 2 (#829345)

BUG=b:394208231
TEST=Build Ocelot and Fatcat and verify it compiles  without any error.

Change-Id: I7f6c4f80a811c596824734d749b8d1c4864ccb9b
Signed-off-by: Appukuttan V K <appukuttan.vk@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88109
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/soc/intel/pantherlake/acpi/pcie.asl     | 209 +-------------------
 src/soc/intel/pantherlake/acpi/ptl_pcie.asl | 207 +++++++++++++++++++
 src/soc/intel/pantherlake/acpi/wcl_pcie.asl | 103 ++++++++++
 3 files changed, 315 insertions(+), 204 deletions(-)
 create mode 100644 src/soc/intel/pantherlake/acpi/ptl_pcie.asl
 create mode 100644 src/soc/intel/pantherlake/acpi/wcl_pcie.asl

diff --git a/src/soc/intel/pantherlake/acpi/pcie.asl b/src/soc/intel/pantherlake/acpi/pcie.asl
index 3321335a63..5c92095c5a 100644
--- a/src/soc/intel/pantherlake/acpi/pcie.asl
+++ b/src/soc/intel/pantherlake/acpi/pcie.asl
@@ -96,208 +96,9 @@ Method (IRQM, 1, Serialized) {
 	}
 }
 
-Device (RP01)
-{
-	Name (_ADR, 0x001C0000)
-
-	OperationRegion (RPCS, PCI_Config, 0x4c, 4)
-	Field (RPCS, AnyAcc, NoLock, Preserve)
-	{
-		, 24,
-		RPPN, 8,	/* Root Port Number */
-	}
-
-	Method (_PRT)
-	{
-		Return (IRQM (RPPN))
-	}
-}
-
-Device (RP02)
-{
-	Name (_ADR, 0x001C0001)
-
-	OperationRegion (RPCS, PCI_Config, 0x4c, 4)
-	Field (RPCS, AnyAcc, NoLock, Preserve)
-	{
-		, 24,
-		RPPN, 8,	/* Root Port Number */
-	}
-
-	Method (_PRT)
-	{
-		Return (IRQM (RPPN))
-	}
-}
-
-Device (RP03)
-{
-	Name (_ADR, 0x001C0002)
-
-	OperationRegion (RPCS, PCI_Config, 0x4c, 4)
-	Field (RPCS, AnyAcc, NoLock, Preserve)
-	{
-		, 24,
-		RPPN, 8,	/* Root Port Number */
-	}
-
-	Method (_PRT)
-	{
-		Return (IRQM (RPPN))
-	}
-}
-
-Device (RP04)
-{
-	Name (_ADR, 0x001C0003)
-
-	OperationRegion (RPCS, PCI_Config, 0x4c, 4)
-	Field (RPCS, AnyAcc, NoLock, Preserve)
-	{
-		, 24,
-		RPPN, 8,	/* Root Port Number */
-	}
-
-	Method (_PRT)
-	{
-		Return (IRQM (RPPN))
-	}
-}
-
-Device (RP05)
-{
-	Name (_ADR, 0x001C0004)
-
-	OperationRegion (RPCS, PCI_Config, 0x4c, 4)
-	Field (RPCS, AnyAcc, NoLock, Preserve)
-	{
-		, 24,
-		RPPN, 8,	/* Root Port Number */
-	}
-
-	Method (_PRT)
-	{
-		Return (IRQM (RPPN))
-	}
-}
-
-Device (RP06)
-{
-	Name (_ADR, 0x001C0005)
-
-	OperationRegion (RPCS, PCI_Config, 0x4c, 4)
-	Field (RPCS, AnyAcc, NoLock, Preserve)
-	{
-		, 24,
-		RPPN, 8,	/* Root Port Number */
-	}
-
-	Method (_PRT)
-	{
-		Return (IRQM (RPPN))
-	}
-}
-
-Device (RP07)
-{
-	Name (_ADR, 0x001C0006)
-
-	OperationRegion (RPCS, PCI_Config, 0x4c, 4)
-	Field (RPCS, AnyAcc, NoLock, Preserve)
-	{
-		, 24,
-		RPPN, 8,	/* Root Port Number */
-	}
-
-	Method (_PRT)
-	{
-		Return (IRQM (RPPN))
-	}
-}
-
-Device (RP08)
-{
-	Name (_ADR, 0x001C0007)
-
-	OperationRegion (RPCS, PCI_Config, 0x4c, 4)
-	Field (RPCS, AnyAcc, NoLock, Preserve)
-	{
-		, 24,
-		RPPN, 8,	/* Root Port Number */
-	}
-
-	Method (_PRT)
-	{
-		Return (IRQM (RPPN))
-	}
-}
-
-Device (RP09)
-{
-	Name (_ADR, 0x00060000)
-
-	OperationRegion (RPCS, PCI_Config, 0x4c, 4)
-	Field (RPCS, AnyAcc, NoLock, Preserve)
-	{
-		, 24,
-		RPPN, 8,	/* Root Port Number */
-	}
-
-	Method (_PRT)
-	{
-		Return (IRQM (RPPN))
-	}
-}
-
-Device (RP10)
-{
-	Name (_ADR, 0x00060001)
-
-	OperationRegion (RPCS, PCI_Config, 0x4c, 4)
-	Field (RPCS, AnyAcc, NoLock, Preserve)
-	{
-		, 24,
-		RPPN, 8,	/* Root Port Number */
-	}
-
-	Method (_PRT)
-	{
-		Return (IRQM (RPPN))
-	}
-}
-
-#if CONFIG(SOC_INTEL_PANTHERLAKE_H)
-Device (RP11)
-{
-	Name (_ADR, 0x00060002)
-
-	OperationRegion (RPCS, PCI_Config, 0x4c, 4)
-	Field (RPCS, AnyAcc, NoLock, Preserve)
-	{
-		, 24,
-		RPPN, 8,	/* Root Port Number */
-	}
-
-	Method (_PRT)
-	{
-		Return (IRQM (RPPN))
-	}
-}
-
-Device (RP12)
-{
-	Name (_ADR, 0x00060003)
-
-	OperationRegion (RPCS, PCI_Config, 0x4c, 4)
-	Field (RPCS, AnyAcc, NoLock, Preserve)
-	{
-		, 24,
-		RPPN, 8,	/* Root Port Number */
-	}
-
-	Method (_PRT)
-	{
-		Return (IRQM (RPPN))
-	}
-}
+/* PCIE Ports */
+#if (CONFIG(SOC_INTEL_WILDCATLAKE))
+#include "wcl_pcie.asl"
+#else
+#include "ptl_pcie.asl"
 #endif
diff --git a/src/soc/intel/pantherlake/acpi/ptl_pcie.asl b/src/soc/intel/pantherlake/acpi/ptl_pcie.asl
new file mode 100644
index 0000000000..6e831c7a9a
--- /dev/null
+++ b/src/soc/intel/pantherlake/acpi/ptl_pcie.asl
@@ -0,0 +1,207 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+Device (RP01)
+{
+	Name (_ADR, 0x001C0000)
+
+	OperationRegion (RPCS, PCI_Config, 0x4c, 4)
+	Field (RPCS, AnyAcc, NoLock, Preserve)
+	{
+		, 24,
+		RPPN, 8,	/* Root Port Number */
+	}
+
+	Method (_PRT)
+	{
+		Return (IRQM (RPPN))
+	}
+}
+
+Device (RP02)
+{
+	Name (_ADR, 0x001C0001)
+
+	OperationRegion (RPCS, PCI_Config, 0x4c, 4)
+	Field (RPCS, AnyAcc, NoLock, Preserve)
+	{
+		, 24,
+		RPPN, 8,	/* Root Port Number */
+	}
+
+	Method (_PRT)
+	{
+		Return (IRQM (RPPN))
+	}
+}
+
+Device (RP03)
+{
+	Name (_ADR, 0x001C0002)
+
+	OperationRegion (RPCS, PCI_Config, 0x4c, 4)
+	Field (RPCS, AnyAcc, NoLock, Preserve)
+	{
+		, 24,
+		RPPN, 8,	/* Root Port Number */
+	}
+
+	Method (_PRT)
+	{
+		Return (IRQM (RPPN))
+	}
+}
+
+Device (RP04)
+{
+	Name (_ADR, 0x001C0003)
+
+	OperationRegion (RPCS, PCI_Config, 0x4c, 4)
+	Field (RPCS, AnyAcc, NoLock, Preserve)
+	{
+		, 24,
+		RPPN, 8,	/* Root Port Number */
+	}
+
+	Method (_PRT)
+	{
+		Return (IRQM (RPPN))
+	}
+}
+
+Device (RP05)
+{
+	Name (_ADR, 0x001C0004)
+
+	OperationRegion (RPCS, PCI_Config, 0x4c, 4)
+	Field (RPCS, AnyAcc, NoLock, Preserve)
+	{
+		, 24,
+		RPPN, 8,	/* Root Port Number */
+	}
+
+	Method (_PRT)
+	{
+		Return (IRQM (RPPN))
+	}
+}
+
+Device (RP06)
+{
+	Name (_ADR, 0x001C0005)
+
+	OperationRegion (RPCS, PCI_Config, 0x4c, 4)
+	Field (RPCS, AnyAcc, NoLock, Preserve)
+	{
+		, 24,
+		RPPN, 8,	/* Root Port Number */
+	}
+
+	Method (_PRT)
+	{
+		Return (IRQM (RPPN))
+	}
+}
+
+Device (RP07)
+{
+	Name (_ADR, 0x001C0006)
+
+	OperationRegion (RPCS, PCI_Config, 0x4c, 4)
+	Field (RPCS, AnyAcc, NoLock, Preserve)
+	{
+		, 24,
+		RPPN, 8,	/* Root Port Number */
+	}
+
+	Method (_PRT)
+	{
+		Return (IRQM (RPPN))
+	}
+}
+
+Device (RP08)
+{
+	Name (_ADR, 0x001C0007)
+
+	OperationRegion (RPCS, PCI_Config, 0x4c, 4)
+	Field (RPCS, AnyAcc, NoLock, Preserve)
+	{
+		, 24,
+		RPPN, 8,	/* Root Port Number */
+	}
+
+	Method (_PRT)
+	{
+		Return (IRQM (RPPN))
+	}
+}
+
+Device (RP09)
+{
+	Name (_ADR, 0x00060000)
+
+	OperationRegion (RPCS, PCI_Config, 0x4c, 4)
+	Field (RPCS, AnyAcc, NoLock, Preserve)
+	{
+		, 24,
+		RPPN, 8,	/* Root Port Number */
+	}
+
+	Method (_PRT)
+	{
+		Return (IRQM (RPPN))
+	}
+}
+
+Device (RP10)
+{
+	Name (_ADR, 0x00060001)
+
+	OperationRegion (RPCS, PCI_Config, 0x4c, 4)
+	Field (RPCS, AnyAcc, NoLock, Preserve)
+	{
+		, 24,
+		RPPN, 8,	/* Root Port Number */
+	}
+
+	Method (_PRT)
+	{
+		Return (IRQM (RPPN))
+	}
+}
+
+#if CONFIG(SOC_INTEL_PANTHERLAKE_H)
+Device (RP11)
+{
+	Name (_ADR, 0x00060002)
+
+	OperationRegion (RPCS, PCI_Config, 0x4c, 4)
+	Field (RPCS, AnyAcc, NoLock, Preserve)
+	{
+		, 24,
+		RPPN, 8,	/* Root Port Number */
+	}
+
+	Method (_PRT)
+	{
+		Return (IRQM (RPPN))
+	}
+}
+
+Device (RP12)
+{
+	Name (_ADR, 0x00060003)
+
+	OperationRegion (RPCS, PCI_Config, 0x4c, 4)
+	Field (RPCS, AnyAcc, NoLock, Preserve)
+	{
+		, 24,
+		RPPN, 8,	/* Root Port Number */
+	}
+
+	Method (_PRT)
+	{
+		Return (IRQM (RPPN))
+	}
+}
+#endif
diff --git a/src/soc/intel/pantherlake/acpi/wcl_pcie.asl b/src/soc/intel/pantherlake/acpi/wcl_pcie.asl
new file mode 100644
index 0000000000..1adb0d4fa2
--- /dev/null
+++ b/src/soc/intel/pantherlake/acpi/wcl_pcie.asl
@@ -0,0 +1,103 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+Device (RP01)
+{
+	Name (_ADR, 0x001C0000)
+
+	OperationRegion (RPCS, PCI_Config, 0x4c, 4)
+	Field (RPCS, AnyAcc, NoLock, Preserve)
+	{
+		, 24,
+		RPPN, 8,	/* Root Port Number */
+	}
+
+	Method (_PRT)
+	{
+		Return (IRQM (RPPN))
+	}
+}
+
+Device (RP02)
+{
+	Name (_ADR, 0x001C0001)
+
+	OperationRegion (RPCS, PCI_Config, 0x4c, 4)
+	Field (RPCS, AnyAcc, NoLock, Preserve)
+	{
+		, 24,
+		RPPN, 8,	/* Root Port Number */
+	}
+
+	Method (_PRT)
+	{
+		Return (IRQM (RPPN))
+	}
+}
+
+Device (RP03)
+{
+	Name (_ADR, 0x001C0002)
+
+	OperationRegion (RPCS, PCI_Config, 0x4c, 4)
+	Field (RPCS, AnyAcc, NoLock, Preserve)
+	{
+		, 24,
+		RPPN, 8,	/* Root Port Number */
+	}
+
+	Method (_PRT)
+	{
+		Return (IRQM (RPPN))
+	}
+}
+
+Device (RP04)
+{
+	Name (_ADR, 0x001C0003)
+
+	OperationRegion (RPCS, PCI_Config, 0x4c, 4)
+	Field (RPCS, AnyAcc, NoLock, Preserve)
+	{
+		, 24,
+		RPPN, 8,	/* Root Port Number */
+	}
+
+	Method (_PRT)
+	{
+		Return (IRQM (RPPN))
+	}
+}
+
+Device (RP05)
+{
+	Name (_ADR, 0x00060000)
+
+	OperationRegion (RPCS, PCI_Config, 0x4c, 4)
+	Field (RPCS, AnyAcc, NoLock, Preserve)
+	{
+		, 24,
+		RPPN, 8,	/* Root Port Number */
+	}
+
+	Method (_PRT)
+	{
+		Return (IRQM (RPPN))
+	}
+}
+
+Device (RP06)
+{
+	Name (_ADR, 0x00060001)
+
+	OperationRegion (RPCS, PCI_Config, 0x4c, 4)
+	Field (RPCS, AnyAcc, NoLock, Preserve)
+	{
+		, 24,
+		RPPN, 8,	/* Root Port Number */
+	}
+
+	Method (_PRT)
+	{
+		Return (IRQM (RPPN))
+	}
+}

From f48865ab9a6b22dbf626f6d6b83b6cbc2c52a58e Mon Sep 17 00:00:00 2001
From: Subrata Banik <subratabanik@google.com>
Date: Mon, 9 Jun 2025 22:44:24 +0530
Subject: [PATCH 1357/3886] drivers/intel/fsp2_0: Refactor bitmap loading and
 GOP BLT conversion

This commit refactors the bitmap handling in the FSP2.0 driver to
enhance flexibility. Previously, `fsp_convert_bmp_to_gop_blt()`
directly called `bmp_load_logo()`, tying it to specific, predefined
bitmaps like low-battery or OEM splash logos. This prevented its
use for dynamic bitmap files (e.g., brand logos) at runtime.

To address this, `fsp_convert_bmp_to_gop_blt()` no longer handles
bitmap loading. Instead, a new unified API,
`fsp_load_and_convert_bmp_to_gop_blt()`, is introduced for scenarios
where FSP needs to load and convert a bitmap in a single step
(e.g., via its entrypoint).

This change makes `fsp_convert_bmp_to_gop_blt()` a generic API capable
of converting any provided bitmap into a BLT buffer. SoC layers
(like Alder Lake, Meteor Lake, Panther Lake) can now explicitly load
bitmaps and then pass them to `fsp_convert_bmp_to_gop_blt()`, or use
the new `fsp_load_and_convert_bmp_to_gop_blt()` for combined
operations.

Before:
- `soc_load_logo_by_coreboot()` -> `fsp_convert_bmp_to_gop_blt()`
      (loads logo internally)
- `soc_load_logo_by_fsp()` -> `fsp_convert_bmp_to_gop_blt()`
      (loads logo internally)

**After:**
- `soc_load_logo_by_coreboot()` -> loads logo
      -> `fsp_convert_bmp_to_gop_blt()`
- `soc_load_logo_by_fsp()` -> `fsp_load_and_convert_bmp_to_gop_blt()`

BUG=b:423591644
TEST=Able to build and boot google/fatcat. FW splash screen looks
proper.

Change-Id: Ia20e8d42bca6f40c4eb652eb69e3fce84409fc35
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88014
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
---
 src/drivers/intel/fsp2_0/cb_logo.c            | 19 +++--
 src/drivers/intel/fsp2_0/fsp_gop_blt.c        | 73 +++++++++++++------
 .../intel/fsp2_0/include/fsp/fsp_gop_blt.h    |  7 +-
 src/soc/intel/alderlake/fsp_params.c          |  2 +-
 src/soc/intel/meteorlake/fsp_params.c         |  2 +-
 src/soc/intel/pantherlake/fsp_params.c        |  2 +-
 6 files changed, 73 insertions(+), 32 deletions(-)

diff --git a/src/drivers/intel/fsp2_0/cb_logo.c b/src/drivers/intel/fsp2_0/cb_logo.c
index cc62a1c553..4eaf343323 100644
--- a/src/drivers/intel/fsp2_0/cb_logo.c
+++ b/src/drivers/intel/fsp2_0/cb_logo.c
@@ -3,6 +3,7 @@
 #define __SIMPLE_DEVICE__
 
 #include <bootmode.h>
+#include <bootsplash.h>
 #include <console/console.h>
 #include <cpu/x86/mtrr.h>
 #include <device/pci_ops.h>
@@ -112,12 +113,12 @@ static void copy_logo_to_framebuffer(
 
 void soc_load_logo_by_coreboot(void)
 {
-	size_t size;
 	const struct hob_graphics_info *ginfo;
 	struct soc_intel_common_config *config = chip_get_common_soc_structure();
-	efi_uintn_t logo, blt_size;
-	efi_uintn_t blt_buffer_addr;
-	uint32_t logo_size, logo_height, logo_width;
+	uintptr_t logo_ptr;
+	size_t size, logo_ptr_size;
+	efi_uintn_t blt_size, blt_buffer_addr;
+	uint32_t logo_height, logo_width;
 	int temp_mtrr_index = -1;
 
 	/* Find the graphics information HOB */
@@ -154,8 +155,16 @@ void soc_load_logo_by_coreboot(void)
 	if (CONFIG(VBOOT_LID_SWITCH) ? !get_lid_switch() : !CONFIG(RUN_FSP_GOP))
 		config->panel_orientation = LB_FB_ORIENTATION_NORMAL;
 
+	logo_ptr = (uintptr_t)bmp_load_logo(&logo_ptr_size);
+
+	if (!logo_ptr || logo_ptr_size < sizeof(efi_bmp_image_header)) {
+		printk(BIOS_ERR, "%s: BMP image (%zu) is less than expected minimum size (%zu).\n",
+				 __func__, logo_ptr_size, sizeof(efi_bmp_image_header));
+		return;
+	}
+
 	/* Convert BMP logo to GOP BLT format */
-	fsp_convert_bmp_to_gop_blt(&logo, &logo_size, &blt_buffer_addr, &blt_size,
+	fsp_convert_bmp_to_gop_blt(logo_ptr, logo_ptr_size, &blt_buffer_addr, &blt_size,
 			   &logo_height, &logo_width, config->panel_orientation);
 
 	/* Override logo alignment if the default screen orientation is not normal */
diff --git a/src/drivers/intel/fsp2_0/fsp_gop_blt.c b/src/drivers/intel/fsp2_0/fsp_gop_blt.c
index 32d28e873c..bc37ca6baa 100644
--- a/src/drivers/intel/fsp2_0/fsp_gop_blt.c
+++ b/src/drivers/intel/fsp2_0/fsp_gop_blt.c
@@ -398,42 +398,69 @@ static void *fill_blt_buffer(efi_bmp_image_header *header,
 	return gop_blt_ptr;
 }
 
+/* Helper function to perform the common BMP to GOP BLT conversion logic */
+static bool convert_bmp_to_gop_blt_common(uintptr_t logo_ptr, size_t logo_ptr_size,
+	efi_uintn_t *blt_ptr, efi_uintn_t *blt_size, uint32_t *pixel_height,
+	uint32_t *pixel_width, enum lb_fb_orientation orientation)
+{
+	size_t blt_buffer_size;
+	efi_bmp_image_header *bmp_header;
+
+	bmp_header = (efi_bmp_image_header *)logo_ptr;
+
+	/* Authenticate BMP header and validate size against provided logo_ptr_size */
+	if (!do_bmp_image_authentication(bmp_header) || (bmp_header->Size != logo_ptr_size))
+		return false;
+
+	blt_buffer_size = calculate_blt_buffer_size(bmp_header);
+	if (!blt_buffer_size)
+		return false;
+
+	if (get_color_map_num(bmp_header) < 0)
+		return false;
+
+	bool is_standard_orientation = (orientation == LB_FB_ORIENTATION_NORMAL ||
+					orientation == LB_FB_ORIENTATION_BOTTOM_UP);
+
+	*blt_size = blt_buffer_size;
+	*pixel_height = is_standard_orientation ? bmp_header->PixelHeight : bmp_header->PixelWidth;
+	*pixel_width = is_standard_orientation ? bmp_header->PixelWidth : bmp_header->PixelHeight;
+	*blt_ptr = (uintptr_t)fill_blt_buffer(bmp_header, logo_ptr, blt_buffer_size, orientation);
+
+	return true;
+}
+
 /* Convert a *.BMP graphics image to a GOP blt buffer */
-void fsp_convert_bmp_to_gop_blt(efi_uintn_t *logo, uint32_t *logo_size,
+void fsp_load_and_convert_bmp_to_gop_blt(efi_uintn_t *logo, uint32_t *logo_size,
 	efi_uintn_t *blt_ptr, efi_uintn_t *blt_size, uint32_t *pixel_height, uint32_t *pixel_width,
 	enum lb_fb_orientation orientation)
 {
 	uintptr_t logo_ptr;
-	size_t logo_ptr_size, blt_buffer_size;
-	efi_bmp_image_header *bmp_header;
+	size_t logo_ptr_size;
 
 	if (!logo || !logo_size || !blt_ptr || !blt_size || !pixel_height || !pixel_width)
 		return;
 
 	logo_ptr = (uintptr_t)bmp_load_logo(&logo_ptr_size);
 
-	if (!logo_ptr || logo_ptr_size < sizeof(efi_bmp_image_header)) {
-		printk(BIOS_ERR, "%s: BMP Image size is too small.\n", __func__);
-		return;
-	}
-
-	bmp_header = (efi_bmp_image_header *)logo_ptr;
-	if (!do_bmp_image_authentication(bmp_header) || (bmp_header->Size != logo_ptr_size))
+	if (!logo_ptr || logo_ptr_size < sizeof(efi_bmp_image_header))
 		return;
 
-	blt_buffer_size = calculate_blt_buffer_size(bmp_header);
-	if (!blt_buffer_size)
-		return;
-
-	if (get_color_map_num(bmp_header) < 0)
-		return;
-
-	bool is_standard_orientation = (orientation == LB_FB_ORIENTATION_NORMAL ||
-			orientation == LB_FB_ORIENTATION_BOTTOM_UP);
 	*logo = logo_ptr;
 	*logo_size = logo_ptr_size;
-	*blt_size = blt_buffer_size;
-	*pixel_height = is_standard_orientation ? bmp_header->PixelHeight : bmp_header->PixelWidth;
-	*pixel_width = is_standard_orientation ? bmp_header->PixelWidth : bmp_header->PixelHeight;
-	*blt_ptr = (uintptr_t)fill_blt_buffer(bmp_header, logo_ptr, blt_buffer_size, orientation);
+
+	convert_bmp_to_gop_blt_common(logo_ptr, logo_ptr_size, blt_ptr, blt_size,
+				      pixel_height, pixel_width, orientation);
+}
+
+/* Convert a *.BMP graphics image (as per input `logo_ptr`) to a GOP blt buffer */
+void fsp_convert_bmp_to_gop_blt(uintptr_t logo_ptr, size_t logo_ptr_size,
+	efi_uintn_t *blt_ptr, efi_uintn_t *blt_size, uint32_t *pixel_height, uint32_t *pixel_width,
+	enum lb_fb_orientation orientation)
+{
+	if (!blt_ptr || !blt_size || !pixel_height || !pixel_width)
+		return;
+
+	convert_bmp_to_gop_blt_common(logo_ptr, logo_ptr_size, blt_ptr, blt_size,
+				      pixel_height, pixel_width, orientation);
 }
diff --git a/src/drivers/intel/fsp2_0/include/fsp/fsp_gop_blt.h b/src/drivers/intel/fsp2_0/include/fsp/fsp_gop_blt.h
index 377607929a..8a80930d0d 100644
--- a/src/drivers/intel/fsp2_0/include/fsp/fsp_gop_blt.h
+++ b/src/drivers/intel/fsp2_0/include/fsp/fsp_gop_blt.h
@@ -8,7 +8,12 @@
 #include <types.h>
 
 /* Convert a *.BMP graphics image to a GOP blt buffer */
-void fsp_convert_bmp_to_gop_blt(efi_uintn_t *logo, uint32_t *logo_size,
+void fsp_load_and_convert_bmp_to_gop_blt(efi_uintn_t *logo, uint32_t *logo_size,
+	efi_uintn_t *blt_ptr, efi_uintn_t *blt_size, uint32_t *pixel_height, uint32_t *pixel_width,
+	enum lb_fb_orientation orientation);
+
+/* Convert a *.BMP graphics image (as per input `logo_ptr`) to a GOP blt buffer */
+void fsp_convert_bmp_to_gop_blt(uintptr_t logo_ptr, size_t logo_ptr_size,
 	efi_uintn_t *blt_ptr, efi_uintn_t *blt_size, uint32_t *pixel_height, uint32_t *pixel_width,
 	enum lb_fb_orientation orientation);
 
diff --git a/src/soc/intel/alderlake/fsp_params.c b/src/soc/intel/alderlake/fsp_params.c
index a788319efc..3368b3642b 100644
--- a/src/soc/intel/alderlake/fsp_params.c
+++ b/src/soc/intel/alderlake/fsp_params.c
@@ -1397,7 +1397,7 @@ void soc_load_logo_by_fsp(FSPS_UPD *supd)
 	if (s_cfg->LidStatus == 0)
 		config->panel_orientation = LB_FB_ORIENTATION_NORMAL;
 
-	fsp_convert_bmp_to_gop_blt(&supd->FspsConfig.LogoPtr,
+	fsp_load_and_convert_bmp_to_gop_blt(&supd->FspsConfig.LogoPtr,
 			 &supd->FspsConfig.LogoSize,
 			 &supd->FspsConfig.BltBufferAddress,
 			 &supd->FspsConfig.BltBufferSize,
diff --git a/src/soc/intel/meteorlake/fsp_params.c b/src/soc/intel/meteorlake/fsp_params.c
index 9adee42f7f..0ad32a3e5e 100644
--- a/src/soc/intel/meteorlake/fsp_params.c
+++ b/src/soc/intel/meteorlake/fsp_params.c
@@ -913,7 +913,7 @@ void soc_load_logo_by_fsp(FSPS_UPD *supd)
 	if (s_cfg->LidStatus == 0)
 		config->panel_orientation = LB_FB_ORIENTATION_NORMAL;
 
-	fsp_convert_bmp_to_gop_blt(&supd->FspsConfig.LogoPtr,
+	fsp_load_and_convert_bmp_to_gop_blt(&supd->FspsConfig.LogoPtr,
 			 &supd->FspsConfig.LogoSize,
 			 &supd->FspsConfig.BltBufferAddress,
 			 &supd->FspsConfig.BltBufferSize,
diff --git a/src/soc/intel/pantherlake/fsp_params.c b/src/soc/intel/pantherlake/fsp_params.c
index 47d135a321..01ec0860a6 100644
--- a/src/soc/intel/pantherlake/fsp_params.c
+++ b/src/soc/intel/pantherlake/fsp_params.c
@@ -818,7 +818,7 @@ void soc_load_logo_by_fsp(FSPS_UPD *supd)
 	if (s_cfg->LidStatus == 0)
 		config->panel_orientation = LB_FB_ORIENTATION_NORMAL;
 
-	fsp_convert_bmp_to_gop_blt(&logo, &logo_size,
+	fsp_load_and_convert_bmp_to_gop_blt(&logo, &logo_size,
 				   &supd->FspsConfig.BltBufferAddress,
 				   &blt_size,
 				   &supd->FspsConfig.LogoPixelHeight,

From a1dbb4076cdb0356279fd1adda7ae731ab0e3f7b Mon Sep 17 00:00:00 2001
From: Subrata Banik <subratabanik@google.com>
Date: Wed, 11 Jun 2025 14:29:16 +0530
Subject: [PATCH 1358/3886] lib: Add support for different bootsplash types

This commit introduces an enumerated type `bootsplash_type` to
differentiate between various bootsplash logos, such as
`BOOTSPLASH_LOW_BATTERY` and `BOOTSPLASH_CENTER`.

A `bootsplash_list` array is added to map these types to their
corresponding default filenames. A new function,
`bmp_get_logo_filename`, is provided to retrieve the correct logo
filename based on the specified bootsplash type. This function also
handles overriding the `BOOTSPLASH_CENTER` logo name if
`CONFIG(HAVE_CUSTOM_BMP_LOGO)` is enabled.

The `bmp_load_logo` function is updated to utilize the new
`bootsplash_type` and `bmp_get_logo_filename` to dynamically select the
appropriate logo for display. This change streamlines logo management
and improves flexibility for different boot scenarios.

BUG=b:423591644
TEST=Able to build and boot google/fatcat. FW splash screen looks
proper.

Change-Id: I882deda56b5d30bb15cc7def408c4ea479ffd6ba
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88052
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
---
 src/include/bootsplash.h | 10 ++++++++++
 src/lib/bmp_logo.c       | 28 +++++++++++++++++++++-------
 2 files changed, 31 insertions(+), 7 deletions(-)

diff --git a/src/include/bootsplash.h b/src/include/bootsplash.h
index 7a57cd91f4..f935476e44 100644
--- a/src/include/bootsplash.h
+++ b/src/include/bootsplash.h
@@ -5,6 +5,16 @@
 
 #include <types.h>
 
+enum bootsplash_type {
+	/* Indicates a low battery bootsplash logo. */
+	BOOTSPLASH_LOW_BATTERY,
+	/* Indicates a Main OEM defined bootsplash logo for center of the splash screen. */
+	BOOTSPLASH_CENTER,
+
+	/* It's used to determine the total number of bootsplash types. */
+	BOOTSPLASH_MAX_NUM,
+};
+
 /**
  * Sets up the framebuffer with the bootsplash.jpg from cbfs.
  * Returns 0 on success
diff --git a/src/lib/bmp_logo.c b/src/lib/bmp_logo.c
index bc636a6755..9822ca00f3 100644
--- a/src/lib/bmp_logo.c
+++ b/src/lib/bmp_logo.c
@@ -9,17 +9,31 @@
 
 static const struct cbmem_entry *logo_entry;
 
-#if !CONFIG(HAVE_CUSTOM_BMP_LOGO)
-const char *bmp_logo_filename(void)
+/* Mapping of different bootsplash logo name based on bootsplash type */
+static const char *bootsplash_list[BOOTSPLASH_MAX_NUM] = {
+	[BOOTSPLASH_LOW_BATTERY] = "low_battery.bmp",
+	[BOOTSPLASH_CENTER] = "logo.bmp"
+};
+
+/*
+ * Return the appropriate logo filename based on the bootsplash type.
+ * This will be the default filename from 'bootsplash_list' or the
+ * custom one if it was overridden for BOOTSPLASH_OEM.
+ */
+static const char *bmp_get_logo_filename(enum bootsplash_type type)
 {
-	return "logo.bmp";
+	/* Override `BOOTSPLASH_CENTER` logo name if required */
+	if ((type == BOOTSPLASH_CENTER) && CONFIG(HAVE_CUSTOM_BMP_LOGO))
+		return bmp_logo_filename();
+
+	return bootsplash_list[type];
 }
-#endif
 
 void *bmp_load_logo(size_t *logo_size)
 {
 	void *logo_buffer;
 	const char *logo_name;
+	enum bootsplash_type type = BOOTSPLASH_CENTER;
 
 	/* CBMEM is locked for S3 resume path. */
 	if (acpi_is_wakeup_s3())
@@ -34,9 +48,9 @@ void *bmp_load_logo(size_t *logo_size)
 		return NULL;
 
 	if (platform_is_low_battery_shutdown_needed())
-		logo_name = "low_battery.bmp";
-	else
-		logo_name = bmp_logo_filename();
+		type = BOOTSPLASH_LOW_BATTERY;
+
+	logo_name = bmp_get_logo_filename(type);
 
 	*logo_size = cbfs_load(logo_name, logo_buffer, 1 * MiB);
 	if (*logo_size == 0)

From be5609bdaf082295a7b9f49a4f0d14a201f96fb9 Mon Sep 17 00:00:00 2001
From: Subrata Banik <subratabanik@google.com>
Date: Mon, 9 Jun 2025 21:01:49 +0530
Subject: [PATCH 1359/3886] lib: Introduce a new function
 `bmp_load_logo_by_type()`
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

This patch introduces `bmp_load_logo_by_type()` to allow loading a
specific BMP logo from CBFS based on `enum bootsplash_type`.

Now, bmp_load_logo() leverages bmp_load_logo_by_type() with the
system-determined logo type. The new bmp_load_logo_by_type() function
provides a direct interface to load any specified BMP by `enum
bootsplash_type`, which is beneficial for scenarios requiring explicit
logo selection.

BUG=b:423591644
TEST=Able to build and boot google/fatcat. Ensure FW splash screen looks
proper.

Change-Id: I2473f7d48ca2d196ced89d81391cf387627a2f86
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88013
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/include/bootsplash.h |  1 +
 src/lib/bmp_logo.c       | 21 ++++++++++++---------
 2 files changed, 13 insertions(+), 9 deletions(-)

diff --git a/src/include/bootsplash.h b/src/include/bootsplash.h
index f935476e44..9dffc28eb8 100644
--- a/src/include/bootsplash.h
+++ b/src/include/bootsplash.h
@@ -31,6 +31,7 @@ void set_bootsplash(unsigned char *framebuffer, unsigned int x_resolution,
  */
 const char *bmp_logo_filename(void);
 void *bmp_load_logo(size_t *logo_size);
+void *bmp_load_logo_by_type(enum bootsplash_type type, size_t *logo_size);
 void bmp_release_logo(void);
 /*
  * Platform specific callbacks for power-off handling.
diff --git a/src/lib/bmp_logo.c b/src/lib/bmp_logo.c
index 9822ca00f3..b62cb867fa 100644
--- a/src/lib/bmp_logo.c
+++ b/src/lib/bmp_logo.c
@@ -29,11 +29,9 @@ static const char *bmp_get_logo_filename(enum bootsplash_type type)
 	return bootsplash_list[type];
 }
 
-void *bmp_load_logo(size_t *logo_size)
+void *bmp_load_logo_by_type(enum bootsplash_type type, size_t *logo_size)
 {
 	void *logo_buffer;
-	const char *logo_name;
-	enum bootsplash_type type = BOOTSPLASH_CENTER;
 
 	/* CBMEM is locked for S3 resume path. */
 	if (acpi_is_wakeup_s3())
@@ -47,18 +45,23 @@ void *bmp_load_logo(size_t *logo_size)
 	if (!logo_buffer)
 		return NULL;
 
-	if (platform_is_low_battery_shutdown_needed())
-		type = BOOTSPLASH_LOW_BATTERY;
-
-	logo_name = bmp_get_logo_filename(type);
-
-	*logo_size = cbfs_load(logo_name, logo_buffer, 1 * MiB);
+	*logo_size = cbfs_load(bmp_get_logo_filename(type), logo_buffer, 1 * MiB);
 	if (*logo_size == 0)
 		return NULL;
 
 	return logo_buffer;
 }
 
+void *bmp_load_logo(size_t *logo_size)
+{
+	enum bootsplash_type type = BOOTSPLASH_CENTER;
+
+	if (platform_is_low_battery_shutdown_needed())
+		type = BOOTSPLASH_LOW_BATTERY;
+
+	return bmp_load_logo_by_type(type, logo_size);
+}
+
 void bmp_release_logo(void)
 {
 	if (logo_entry)

From 4373eea5d82ef1ae9a57799e1d560d5d1b90c704 Mon Sep 17 00:00:00 2001
From: Subrata Banik <subratabanik@google.com>
Date: Tue, 10 Jun 2025 19:29:56 +0530
Subject: [PATCH 1360/3886] {lib, drivers/intel}: Add splash screen footer

This commit introduces the `SPLASH_SCREEN_FOOTER` Kconfig option,
enabling a custom footer image or logo on the firmware splash screen.
This provides an additional branding opportunity for device
manufacturers.

`soc_load_logo_by_coreboot()` now conditionally loads and renders
`footer_logo.bmp` when this option is enabled. The footer logo is
positioned at the bottom of the screen.

A new `SPLASH_SCREEN_FOOTER_LOGO_PATH` Kconfig option is added to
define the footer logo's file path. It defaults to a mainboard-specific
location. `Makefile.mk` is updated to ensure this logo is included in
the CBFS.

This additional branding is made possible by rendering bitmaps using
coreboot's native implementation (`USE_COREBOOT_FOR_BMP_RENDERING`).
FSP currently lacks the necessary callbacks to support this feature.

Currently, the OEM footer branding will appear even when the
system is booting in low-battery mode. A planned update will fix this
by exiting early from the boot process, preventing the footer from
showing and conserving power.

BUG=b:423591644
TEST=Able to display custom footer logo on boot.

Change-Id: I57f8af910e8b8f56e8a4a88f8cca6d60fad380b6
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88029
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
---
 src/drivers/intel/fsp2_0/cb_logo.c | 21 +++++++++++++++++++++
 src/include/bootsplash.h           |  2 ++
 src/lib/Kconfig                    | 15 +++++++++++++++
 src/lib/Makefile.mk                |  2 ++
 src/lib/bmp_logo.c                 |  3 ++-
 5 files changed, 42 insertions(+), 1 deletion(-)

diff --git a/src/drivers/intel/fsp2_0/cb_logo.c b/src/drivers/intel/fsp2_0/cb_logo.c
index 4eaf343323..e132432401 100644
--- a/src/drivers/intel/fsp2_0/cb_logo.c
+++ b/src/drivers/intel/fsp2_0/cb_logo.c
@@ -179,6 +179,27 @@ void soc_load_logo_by_coreboot(void)
 	copy_logo_to_framebuffer(framebuffer_bar, bytes_per_scanline, blt_buffer_addr, logo_width,
 			 logo_height, logo_coords.x, logo_coords.y);
 
+	if (CONFIG(SPLASH_SCREEN_FOOTER)) {
+		bmp_release_logo();
+		logo_ptr = (uintptr_t)bmp_load_logo_by_type(BOOTSPLASH_FOOTER, &logo_ptr_size);
+		if (!logo_ptr || logo_ptr_size < sizeof(efi_bmp_image_header)) {
+			printk(BIOS_ERR, "%s: BMP image (%zu) is less than expected minimum size (%zu).\n",
+				 __func__, logo_ptr_size, sizeof(efi_bmp_image_header));
+			return;
+		}
+
+		/* Convert BMP logo to GOP BLT format */
+		fsp_convert_bmp_to_gop_blt(logo_ptr, logo_ptr_size, &blt_buffer_addr, &blt_size,
+				   &logo_height, &logo_width, config->panel_orientation);
+
+		logo_coords = calculate_logo_coordinates(horizontal_resolution,
+				 vertical_resolution, logo_width, logo_height, FW_SPLASH_VALIGNMENT_BOTTOM);
+
+		/* Copy the logo to the framebuffer */
+		copy_logo_to_framebuffer(framebuffer_bar, bytes_per_scanline, blt_buffer_addr,
+				 logo_width, logo_height, logo_coords.x, logo_coords.y);
+	}
+
 	/* Clear temporary Write Combine (WC) MTRR */
 	clear_var_mtrr(temp_mtrr_index);
 }
diff --git a/src/include/bootsplash.h b/src/include/bootsplash.h
index 9dffc28eb8..a8e51cf1ba 100644
--- a/src/include/bootsplash.h
+++ b/src/include/bootsplash.h
@@ -10,6 +10,8 @@ enum bootsplash_type {
 	BOOTSPLASH_LOW_BATTERY,
 	/* Indicates a Main OEM defined bootsplash logo for center of the splash screen. */
 	BOOTSPLASH_CENTER,
+	/* Indicates an optional OEM defined bootsplash logo for footer of the splash screen. */
+	BOOTSPLASH_FOOTER,
 
 	/* It's used to determine the total number of bootsplash types. */
 	BOOTSPLASH_MAX_NUM,
diff --git a/src/lib/Kconfig b/src/lib/Kconfig
index be3a19866f..ea6852d601 100644
--- a/src/lib/Kconfig
+++ b/src/lib/Kconfig
@@ -254,6 +254,21 @@ config PLATFORM_LOW_BATTERY_INDICATOR_LOGO_PATH
 	default "3rdparty/blobs/mainboard/\$(MAINBOARDDIR)/low_battery.bmp"
 endif
 
+config SPLASH_SCREEN_FOOTER
+	bool "Enable custom footer on firmware splash screen"
+	depends on BMP_LOGO
+	help
+	  Enable this option to display a custom footer image or logo on the
+	  firmware splash screen during the boot process. This provides an
+	  additional branding opportunity for device manufacturers, allowing
+	  them to display a logo or other graphic at the bottom of the
+	  splash screen, complementing the main OEM splash image.
+
+config SPLASH_SCREEN_FOOTER_LOGO_PATH
+	string "Path to splash screen footer logo file"
+	depends on SPLASH_SCREEN_FOOTER
+	default "3rdparty/blobs/mainboard/\$(MAINBOARDDIR)/logo.bmp"
+
 endmenu
 
 config HAVE_EARLY_POWEROFF_SUPPORT
diff --git a/src/lib/Makefile.mk b/src/lib/Makefile.mk
index e0bec03427..f13bb66f79 100644
--- a/src/lib/Makefile.mk
+++ b/src/lib/Makefile.mk
@@ -447,3 +447,5 @@ endif
 
 $(eval $(call add_bmp_logo_file_to_cbfs,CONFIG_PLATFORM_HAS_LOW_BATTERY_INDICATOR, \
 	      low_battery.bmp,CONFIG_PLATFORM_LOW_BATTERY_INDICATOR_LOGO_PATH))
+$(eval $(call add_bmp_logo_file_to_cbfs,CONFIG_SPLASH_SCREEN_FOOTER, \
+	      footer_logo.bmp,CONFIG_SPLASH_SCREEN_FOOTER_LOGO_PATH))
diff --git a/src/lib/bmp_logo.c b/src/lib/bmp_logo.c
index b62cb867fa..9dfe15a085 100644
--- a/src/lib/bmp_logo.c
+++ b/src/lib/bmp_logo.c
@@ -12,7 +12,8 @@ static const struct cbmem_entry *logo_entry;
 /* Mapping of different bootsplash logo name based on bootsplash type */
 static const char *bootsplash_list[BOOTSPLASH_MAX_NUM] = {
 	[BOOTSPLASH_LOW_BATTERY] = "low_battery.bmp",
-	[BOOTSPLASH_CENTER] = "logo.bmp"
+	[BOOTSPLASH_CENTER] = "logo.bmp",
+	[BOOTSPLASH_FOOTER] = "footer_logo.bmp"
 };
 
 /*

From d309a9dfa8bb55e596e115fc319c75cb47372e4a Mon Sep 17 00:00:00 2001
From: Subrata Banik <subratabanik@google.com>
Date: Mon, 9 Jun 2025 23:02:08 +0530
Subject: [PATCH 1361/3886] drivers/intel/fsp2_0: Suppress OEM footer in
 low-battery mode

This patch modifies the low-battery shutdown logic to bail out early
when the system is in a low-power state. This prevents the display of
the OEM footer logo, ensuring power conservation and avoiding
unnecessary rendering alongside the low-battery icon.

BUG=b:423591644
TEST=Boot platform with `CONFIG(USE_COREBOOT_FOR_BMP_RENDERING)`
    and low battery. Verify splash appears before shutdown w/o OEM
    footer logo.

Change-Id: Ie9a23c0fe9d6b7d314cf4bbe8a8a90eb5689568e
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88015
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
---
 src/drivers/intel/fsp2_0/cb_logo.c | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/src/drivers/intel/fsp2_0/cb_logo.c b/src/drivers/intel/fsp2_0/cb_logo.c
index e132432401..3bf07790bc 100644
--- a/src/drivers/intel/fsp2_0/cb_logo.c
+++ b/src/drivers/intel/fsp2_0/cb_logo.c
@@ -179,6 +179,13 @@ void soc_load_logo_by_coreboot(void)
 	copy_logo_to_framebuffer(framebuffer_bar, bytes_per_scanline, blt_buffer_addr, logo_width,
 			 logo_height, logo_coords.x, logo_coords.y);
 
+	/*
+	 * If the device is in low-battery mode and the low-battery splash screen is being
+	 * displayed, prevent further operation and bail out early.
+	 */
+	if (platform_is_low_battery_shutdown_needed())
+		return;
+
 	if (CONFIG(SPLASH_SCREEN_FOOTER)) {
 		bmp_release_logo();
 		logo_ptr = (uintptr_t)bmp_load_logo_by_type(BOOTSPLASH_FOOTER, &logo_ptr_size);

From ced9f91ae9cbfc6230677a74f03c1c985ba84812 Mon Sep 17 00:00:00 2001
From: Subrata Banik <subratabanik@google.com>
Date: Sat, 21 Jun 2025 11:13:26 +0530
Subject: [PATCH 1362/3886] soc/intel/cmn: Improve comments for
 fw_splash_vertical_alignment enum

This commit refines the comments for the fw_splash_vertical_alignment
enum members in src/soc/intel/common/block/include/intelblocks/cfg.h.

The redundant enum member names (e.g., FW_SPLASH_VALIGNMENT_CENTER:)
have been removed from the start of each comment block. This makes
the comments cleaner and more direct, focusing on the explanation of
the alignment behavior rather than re-stating the enum member's name.

Change-Id: Ife7a39622df1981adc09db82fecb5adc72d52d8d
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88157
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
---
 src/soc/intel/common/block/include/intelblocks/cfg.h | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/src/soc/intel/common/block/include/intelblocks/cfg.h b/src/soc/intel/common/block/include/intelblocks/cfg.h
index 299e923d85..95ca8ccf7d 100644
--- a/src/soc/intel/common/block/include/intelblocks/cfg.h
+++ b/src/soc/intel/common/block/include/intelblocks/cfg.h
@@ -22,7 +22,7 @@ enum {
  * within the display's height.
  */
 enum fw_splash_vertical_alignment {
-	/* FW_SPLASH_VALIGNMENT_CENTER:
+	/*
 	 * The splash image is centered vertically `(Y-axis - logo_height)/2` on the screen.
 	 * The center of the [LOGO] aligns with the vertical center of the screen.
 	 *
@@ -36,7 +36,7 @@ enum fw_splash_vertical_alignment {
 	 */
 	FW_SPLASH_VALIGNMENT_CENTER = 0,
 
-	/* FW_SPLASH_VALIGNMENT_TOP:
+	/*
 	 * The splash image is aligned to the top edge of the screen.
 	 *
 	 * +---------------+
@@ -49,7 +49,7 @@ enum fw_splash_vertical_alignment {
 	 */
 	FW_SPLASH_VALIGNMENT_TOP = 1,
 
-	/* FW_SPLASH_VALIGNMENT_BOTTOM:
+	/*
 	 * The splash image is aligned to the bottom edge of the screen.
 	 *
 	 * +---------------+
@@ -62,7 +62,7 @@ enum fw_splash_vertical_alignment {
 	 */
 	FW_SPLASH_VALIGNMENT_BOTTOM = 2,
 
-	/* FW_SPLASH_VALIGNMENT_MIDDLE:
+	/*
 	 * The splash image is placed in the vertical middle `(Y-axis/2)` of the screen
 	 * (without considering the `logo height`). This means the TOP EDGE of the
 	 * [LOGO] aligns with the screen's vertical midpoint line.

From dfeaead9f267cc02b0f339eed82e8b4aec538e8d Mon Sep 17 00:00:00 2001
From: Subrata Banik <subratabanik@google.com>
Date: Tue, 10 Jun 2025 19:39:22 +0530
Subject: [PATCH 1363/3886] drivers/intel: Add horizontal logo alignment for
 splash screen

This commit adds horizontal alignment support for splash screen
logos into the existing helper function `calculate_logo_coordinates()`.
Updated helper function determines the X-coordinate for
logo placement based on specified horizontal alignment (left, right,
or center).

The `soc_load_logo_by_coreboot()` function is updated to utilize this
helper for footer logo placement when the panel orientation is
rotated (`LB_FB_ORIENTATION_RIGHT_UP`, `LB_FB_ORIENTATION_LEFT_UP`,
or `LB_FB_ORIENTATION_BOTTOM_UP`).

A new enum, `fw_splash_horizontal_alignment`, is defined in
`intelblocks/cfg.h` to explicitly represent these horizontal alignment
options, complete with descriptive comments and ASCII art.

This enhancement provides greater flexibility in positioning splash
screen elements, especially useful for rotated displays (for the footer
firmware splash screen).

BUG=b:423591644
TEST=Able to rotate the firmware splash screen (including footer logo)
while using portrait panel.

Change-Id: I23ae6d06e1df9cad1b2907a5c02b619dc831d468
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88030
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/drivers/intel/fsp2_0/cb_logo.c            | 52 ++++++++++++++++---
 .../common/block/include/intelblocks/cfg.h    | 30 +++++++++++
 2 files changed, 75 insertions(+), 7 deletions(-)

diff --git a/src/drivers/intel/fsp2_0/cb_logo.c b/src/drivers/intel/fsp2_0/cb_logo.c
index 3bf07790bc..9aab893d13 100644
--- a/src/drivers/intel/fsp2_0/cb_logo.c
+++ b/src/drivers/intel/fsp2_0/cb_logo.c
@@ -45,25 +45,43 @@ static void program_igd_lmembar(uint32_t base)
 }
 
 /*
- * Calculates the destination coordinates for the logo based on alignment settings.
+ * Calculates the destination coordinates for the logo based on both horizontal and
+ * vertical alignment settings.
  *
  * horizontal_resolution: The horizontal resolution of the display panel.
  * vertical_resolution: The vertical resolution of the display panel.
  * logo_width: The width of the logo bitmap.
  * logo_height: The height of the logo bitmap.
- * valignment: The vertical alignment setting.
+ * halignment: The horizontal alignment setting. Use FW_SPLASH_HALIGNMENT_NONE
+ *             if only vertical alignment is specified.
+ * valignment: The vertical alignment setting. Use FW_SPLASH_VALIGNMENT_NONE
+ *             if only horizontal alignment is specified.
  *
  * Returning `struct logo_coordinates` that contains the calculated x and y coordinates
  * for rendering the logo.
  */
 static struct logo_coordinates calculate_logo_coordinates(
 	uint32_t horizontal_resolution, uint32_t vertical_resolution,
-	uint32_t logo_width, uint32_t logo_height, enum fw_splash_vertical_alignment valignment)
+	uint32_t logo_width, uint32_t logo_height,
+	enum fw_splash_vertical_alignment valignment,
+	enum fw_splash_horizontal_alignment halignment)
 {
 	struct logo_coordinates coords;
-	/* Always horizontally centered */
-	coords.x = (horizontal_resolution - logo_width) / 2;
 
+	/* Calculate X coordinate */
+	switch (halignment) {
+	case FW_SPLASH_HALIGNMENT_LEFT:
+		coords.x = 0;
+		break;
+	case FW_SPLASH_HALIGNMENT_RIGHT:
+		coords.x = horizontal_resolution - logo_width;
+		break;
+	default: /* FW_SPLASH_HALIGNMENT_CENTER (default) */
+		coords.x = (horizontal_resolution - logo_width) / 2;
+		break;
+	}
+
+	/* Calculate Y coordinate */
 	switch (valignment) {
 	case FW_SPLASH_VALIGNMENT_MIDDLE:
 		coords.y = vertical_resolution / 2;
@@ -173,7 +191,8 @@ void soc_load_logo_by_coreboot(void)
 
 	/* Calculate logo destination coordinates */
 	struct logo_coordinates logo_coords = calculate_logo_coordinates(horizontal_resolution,
-			 vertical_resolution, logo_width, logo_height, config->logo_valignment);
+			 vertical_resolution, logo_width, logo_height, config->logo_valignment,
+			 FW_SPLASH_HALIGNMENT_CENTER);
 
 	/* Copy the logo to the framebuffer */
 	copy_logo_to_framebuffer(framebuffer_bar, bytes_per_scanline, blt_buffer_addr, logo_width,
@@ -199,8 +218,27 @@ void soc_load_logo_by_coreboot(void)
 		fsp_convert_bmp_to_gop_blt(logo_ptr, logo_ptr_size, &blt_buffer_addr, &blt_size,
 				   &logo_height, &logo_width, config->panel_orientation);
 
+		enum fw_splash_horizontal_alignment halignment = FW_SPLASH_HALIGNMENT_CENTER;
+		enum fw_splash_vertical_alignment valignment = FW_SPLASH_VALIGNMENT_CENTER;
+
+		/* Calculate logo destination coordinates */
+		switch (config->panel_orientation) {
+		case LB_FB_ORIENTATION_RIGHT_UP:
+			halignment = FW_SPLASH_HALIGNMENT_LEFT;
+			break;
+		case LB_FB_ORIENTATION_LEFT_UP:
+			halignment = FW_SPLASH_HALIGNMENT_RIGHT;
+			break;
+		case LB_FB_ORIENTATION_BOTTOM_UP:
+			valignment = FW_SPLASH_VALIGNMENT_TOP;
+			break;
+		default: /* LB_FB_ORIENTATION_NORMAL (default) */
+			valignment = FW_SPLASH_VALIGNMENT_BOTTOM;
+			break;
+		}
+
 		logo_coords = calculate_logo_coordinates(horizontal_resolution,
-				 vertical_resolution, logo_width, logo_height, FW_SPLASH_VALIGNMENT_BOTTOM);
+			 vertical_resolution, logo_width, logo_height, valignment, halignment);
 
 		/* Copy the logo to the framebuffer */
 		copy_logo_to_framebuffer(framebuffer_bar, bytes_per_scanline, blt_buffer_addr,
diff --git a/src/soc/intel/common/block/include/intelblocks/cfg.h b/src/soc/intel/common/block/include/intelblocks/cfg.h
index 95ca8ccf7d..ee75dcfc48 100644
--- a/src/soc/intel/common/block/include/intelblocks/cfg.h
+++ b/src/soc/intel/common/block/include/intelblocks/cfg.h
@@ -83,6 +83,36 @@ enum fw_splash_vertical_alignment {
 	FW_SPLASH_VALIGNMENT_MIDDLE = 3,
 };
 
+enum fw_splash_horizontal_alignment {
+	/*
+	 * The splash image is centered horizontally `(X-axis - logo_width)/2` on the screen.
+	 * The center of the [LOGO] aligns with the horizontal center of the screen.
+	 *
+	 * +-----------------+
+	 * |      [LOGO]     |
+	 * +-----------------+
+	 */
+	FW_SPLASH_HALIGNMENT_CENTER = 0,
+
+	/*
+	 * The splash image is aligned to the left edge of the screen.
+	 *
+	 * +-----------------+
+	 * |[LOGO]           |
+	 * +-----------------+
+	 */
+	FW_SPLASH_HALIGNMENT_LEFT = 1,
+
+	/*
+	 * The splash image is aligned to the right edge of the screen.
+	 *
+	 * +-----------------+
+	 * |           [LOGO]|
+	 * +-----------------+
+	 */
+	FW_SPLASH_HALIGNMENT_RIGHT = 2,
+};
+
 /*
  * This structure will hold data required by common blocks.
  * These are soc specific configurations which will be filled by soc.

From ef051256dc2825cb151b2d4b18223f28fc5942b6 Mon Sep 17 00:00:00 2001
From: Subrata Banik <subratabanik@google.com>
Date: Tue, 10 Jun 2025 19:52:06 +0530
Subject: [PATCH 1364/3886] mainboard/google/fatcat: Drop logo_valignment
 selection
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

This commit removes the explicit `logo_valignment` setting from the
`common_soc_config` for all Fatcat mainboard variants (fatcat, felino,
francka, and kinmen).

The default vertical alignment for the splash screen logo is
`FW_SPLASH_VALIGNMENT_CENTER`, which is the desired behavior for these
boards (in presence of footer logo).

BUG=b:423591644
TEST=Able to show OEM splash screen on google/fatcat at center of the
screen.

Change-Id: I3a9e86a928cdd76f13157eff2a29f209167613a8
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88031
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
---
 src/mainboard/google/fatcat/variants/fatcat/overridetree.cb  | 1 -
 src/mainboard/google/fatcat/variants/felino/overridetree.cb  | 1 -
 src/mainboard/google/fatcat/variants/francka/overridetree.cb | 1 -
 src/mainboard/google/fatcat/variants/kinmen/overridetree.cb  | 1 -
 4 files changed, 4 deletions(-)

diff --git a/src/mainboard/google/fatcat/variants/fatcat/overridetree.cb b/src/mainboard/google/fatcat/variants/fatcat/overridetree.cb
index 858205902d..565aad6f98 100644
--- a/src/mainboard/google/fatcat/variants/fatcat/overridetree.cb
+++ b/src/mainboard/google/fatcat/variants/fatcat/overridetree.cb
@@ -128,7 +128,6 @@ chip soc/intel/pantherlake
 	#| I2C5              | Touchpad                  |
 	#+-------------------+---------------------------+
 	register "common_soc_config" = "{
-		.logo_valignment = FW_SPLASH_VALIGNMENT_MIDDLE,
 		.chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT,
 		.i2c[1] = {
 			.speed = I2C_SPEED_FAST,
diff --git a/src/mainboard/google/fatcat/variants/felino/overridetree.cb b/src/mainboard/google/fatcat/variants/felino/overridetree.cb
index ee19c1ed5b..9184f1d62a 100644
--- a/src/mainboard/google/fatcat/variants/felino/overridetree.cb
+++ b/src/mainboard/google/fatcat/variants/felino/overridetree.cb
@@ -102,7 +102,6 @@ chip soc/intel/pantherlake
 	#| I2C4              | CLICK PAD                 |
 	#+-------------------+---------------------------+
 	register "common_soc_config" = "{
-		.logo_valignment = FW_SPLASH_VALIGNMENT_MIDDLE,
 		.i2c[1] = {
 			.early_init=1,
 			.speed = I2C_SPEED_FAST,
diff --git a/src/mainboard/google/fatcat/variants/francka/overridetree.cb b/src/mainboard/google/fatcat/variants/francka/overridetree.cb
index 983cb91487..bbf6654068 100644
--- a/src/mainboard/google/fatcat/variants/francka/overridetree.cb
+++ b/src/mainboard/google/fatcat/variants/francka/overridetree.cb
@@ -78,7 +78,6 @@ chip soc/intel/pantherlake
 	#| I2C4              | Touchscreen, Touchpad     |
 	#+-------------------+---------------------------+
 	register "common_soc_config" = "{
-		.logo_valignment = FW_SPLASH_VALIGNMENT_MIDDLE,
 		.chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT,
 		.i2c[1] = {
 			.early_init = 1,
diff --git a/src/mainboard/google/fatcat/variants/kinmen/overridetree.cb b/src/mainboard/google/fatcat/variants/kinmen/overridetree.cb
index 6f2b379ba0..8299b42f97 100644
--- a/src/mainboard/google/fatcat/variants/kinmen/overridetree.cb
+++ b/src/mainboard/google/fatcat/variants/kinmen/overridetree.cb
@@ -65,7 +65,6 @@ chip soc/intel/pantherlake
 	#| I2C5              | Touchscreen               |
 	#+-------------------+---------------------------+
 	register "common_soc_config" = "{
-		.logo_valignment = FW_SPLASH_VALIGNMENT_MIDDLE,
 		.chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT,
 		.i2c[3] = {
 			.early_init = 1,

From 57d29ebd74f43a195d4b71b621ae856dc69cae85 Mon Sep 17 00:00:00 2001
From: Subrata Banik <subratabanik@google.com>
Date: Sat, 14 Jun 2025 23:23:46 +0530
Subject: [PATCH 1365/3886] vc/google/chromeos: Don't pack `cb_plus_logo.bmp`
 if footer is present

When a ChromeOS device has `SPLASH_SCREEN_FOOTER` Kconfig enabled and
provides a logo path for an OEM-defined boot splash logo in the footer,
it indicates that the device doesn't need to render
`cb_plus_logo.bmp` logo (hence, avoid packing this bitmap for platforms
that select `SPLASH_SCREEN_FOOTER` Kconfig).

In such cases, only the main OEM logo should be displayed at the center
of the splash screen along with custom bitmap at footer of the splash
screen.

BUG=b:423591644
TEST=Able to show OEM splash screen on google/fatcat.

Change-Id: Ie5085babe2f8373058ce1aa18b7071260f2aef7f
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88099
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/vendorcode/google/chromeos/Makefile.mk |  2 ++
 src/vendorcode/google/chromeos/splash.c    | 16 +++++++++++-----
 2 files changed, 13 insertions(+), 5 deletions(-)

diff --git a/src/vendorcode/google/chromeos/Makefile.mk b/src/vendorcode/google/chromeos/Makefile.mk
index 54673bcaf9..cfb4af45de 100644
--- a/src/vendorcode/google/chromeos/Makefile.mk
+++ b/src/vendorcode/google/chromeos/Makefile.mk
@@ -43,5 +43,7 @@ endef
 
 $(eval $(call add_bmp_logo_file_to_cbfs,CONFIG_CHROMEOS_FW_SPLASH_SCREEN, \
 	      cb_logo.bmp,CONFIG_CHROMEOS_LOGO_PATH))
+ifneq ($(CONFIG_SPLASH_SCREEN_FOOTER),y)
 $(eval $(call add_bmp_logo_file_to_cbfs,CONFIG_CHROMEOS_FW_SPLASH_SCREEN, \
 	      cb_plus_logo.bmp,CONFIG_CHROMEBOOK_PLUS_LOGO_PATH))
+endif
diff --git a/src/vendorcode/google/chromeos/splash.c b/src/vendorcode/google/chromeos/splash.c
index f63f52615c..5923513473 100644
--- a/src/vendorcode/google/chromeos/splash.c
+++ b/src/vendorcode/google/chromeos/splash.c
@@ -5,10 +5,16 @@
 
 const char *bmp_logo_filename(void)
 {
-	if (chromeos_device_branded_plus_hard())
-		return "cb_plus_logo.bmp";
-	else if (chromeos_device_branded_plus_soft())
-		return "cb_plus_logo.bmp";
-	else
+	/*
+	 * If the device has a custom boot splash footer logo (SPLASH_SCREEN_FOOTER Kconfig
+	 * is enabled and a logo path is provided), we only return the main OEM logo, which
+	 * will be displayed in the center of the splash screen.
+	 */
+	if (CONFIG(SPLASH_SCREEN_FOOTER))
 		return "cb_logo.bmp";
+
+	if (chromeos_device_branded_plus_hard() || chromeos_device_branded_plus_soft())
+		return "cb_plus_logo.bmp";
+
+	return "cb_logo.bmp";
 }

From 2a09db3c29bc2ad940ff46f5661a0687a6cefd38 Mon Sep 17 00:00:00 2001
From: Subrata Banik <subratabanik@google.com>
Date: Tue, 10 Jun 2025 20:27:00 +0530
Subject: [PATCH 1366/3886] drivers/intel: Refactor logo rendering with helper
 functions

This commit refactors the `soc_load_logo_by_coreboot()` function by
extracting common logo rendering logic into a new helper function:
`render_logo_to_framebuffer()`.

The `render_logo_to_framebuffer()` helper is responsible for:
- Loading the BMP image (by type).
- Checking the image size.
- Converting the BMP to GOP BLT format.
- Calculating the appropriate logo coordinates based on vertical
  or horizontal alignment, considering panel orientation for the
  footer logo.
- Copying the logo data to the framebuffer.
- Releasing the allocated logo buffer.

This refactoring significantly reduces code duplication within
`soc_load_logo_by_coreboot()`, making it more concise and readable.
It also centralizes the logo rendering process, improving
maintainability and simplifying future modifications.

The `soc_load_logo_by_coreboot()` function now focuses on
higher-level orchestration: graphics info initialization, MTRR
setup, panel orientation adjustment, and sequential calls to
`render_logo_to_framebuffer()` for the main and optional footer logos.
Error handling for MTRR and logo rendering failures is streamlined
with a `cleanup` goto label.

BUG=b:423591644
TEST=Able to show OEM splash screen on google/fatcat at center of the
screen.

Change-Id: I10f84fd1c2081efcf787d00ab7cfc6bb24feca21
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88032
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/drivers/intel/fsp2_0/cb_logo.c | 154 ++++++++++++++++-------------
 1 file changed, 85 insertions(+), 69 deletions(-)

diff --git a/src/drivers/intel/fsp2_0/cb_logo.c b/src/drivers/intel/fsp2_0/cb_logo.c
index 9aab893d13..d86e9e3ff0 100644
--- a/src/drivers/intel/fsp2_0/cb_logo.c
+++ b/src/drivers/intel/fsp2_0/cb_logo.c
@@ -129,15 +129,76 @@ static void copy_logo_to_framebuffer(
 	}
 }
 
+/*
+ * Loads, converts, and renders a BMP logo to the framebuffer.
+ *
+ * Returns 0 on success, -1 on failure.
+ */
+static int render_logo_to_framebuffer(uintptr_t framebuffer_base, uint32_t bytes_per_scanline,
+	uint32_t horizontal_resolution, uint32_t vertical_resolution,
+	struct soc_intel_common_config *config, enum bootsplash_type logo_type)
+{
+	uintptr_t logo_ptr;
+	size_t logo_ptr_size;
+	efi_uintn_t blt_size, blt_buffer_addr;
+	uint32_t logo_height, logo_width;
+	struct logo_coordinates logo_coords;
+
+	logo_ptr = (uintptr_t)bmp_load_logo_by_type(logo_type, &logo_ptr_size);
+
+	if (!logo_ptr || logo_ptr_size < sizeof(efi_bmp_image_header)) {
+		printk(BIOS_ERR, "%s: BMP image (%zu) is less than expected minimum size (%zu).\n",
+				 __func__, logo_ptr_size, sizeof(efi_bmp_image_header));
+		return -1;
+	}
+
+	fsp_convert_bmp_to_gop_blt(logo_ptr, logo_ptr_size, &blt_buffer_addr, &blt_size,
+				   &logo_height, &logo_width, config->panel_orientation);
+
+	enum fw_splash_horizontal_alignment halignment = FW_SPLASH_HALIGNMENT_CENTER;
+	enum fw_splash_vertical_alignment valignment = FW_SPLASH_VALIGNMENT_CENTER;
+	/* Determine logo coordinates based on context (main logo vs. footer) */
+	if (logo_type == BOOTSPLASH_LOW_BATTERY || logo_type == BOOTSPLASH_CENTER) {
+		/* Override logo alignment if the default screen orientation is not normal */
+		if (config->panel_orientation != LB_FB_ORIENTATION_NORMAL)
+			config->logo_valignment = FW_SPLASH_VALIGNMENT_CENTER;
+
+		valignment = config->logo_valignment;
+	} else {
+		/* Calculate logo destination coordinates */
+		switch (config->panel_orientation) {
+		case LB_FB_ORIENTATION_RIGHT_UP:
+			halignment = FW_SPLASH_HALIGNMENT_LEFT;
+			break;
+		case LB_FB_ORIENTATION_LEFT_UP:
+			halignment = FW_SPLASH_HALIGNMENT_RIGHT;
+			break;
+		case LB_FB_ORIENTATION_BOTTOM_UP:
+			valignment = FW_SPLASH_VALIGNMENT_TOP;
+			break;
+		default: /* LB_FB_ORIENTATION_NORMAL (default) */
+			valignment = FW_SPLASH_VALIGNMENT_BOTTOM;
+			break;
+		}
+	}
+
+	logo_coords = calculate_logo_coordinates(horizontal_resolution,
+		 vertical_resolution, logo_width, logo_height, valignment, halignment);
+
+	copy_logo_to_framebuffer(framebuffer_base, bytes_per_scanline, blt_buffer_addr,
+				 logo_width, logo_height, logo_coords.x, logo_coords.y);
+
+	bmp_release_logo();
+
+	return 0;
+}
+
 void soc_load_logo_by_coreboot(void)
 {
 	const struct hob_graphics_info *ginfo;
 	struct soc_intel_common_config *config = chip_get_common_soc_structure();
-	uintptr_t logo_ptr;
-	size_t size, logo_ptr_size;
-	efi_uintn_t blt_size, blt_buffer_addr;
-	uint32_t logo_height, logo_width;
 	int temp_mtrr_index = -1;
+	size_t size;
 
 	/* Find the graphics information HOB */
 	ginfo = fsp_find_extension_hob_by_guid(fsp_graphics_info_guid, &size);
@@ -173,78 +234,33 @@ void soc_load_logo_by_coreboot(void)
 	if (CONFIG(VBOOT_LID_SWITCH) ? !get_lid_switch() : !CONFIG(RUN_FSP_GOP))
 		config->panel_orientation = LB_FB_ORIENTATION_NORMAL;
 
-	logo_ptr = (uintptr_t)bmp_load_logo(&logo_ptr_size);
-
-	if (!logo_ptr || logo_ptr_size < sizeof(efi_bmp_image_header)) {
-		printk(BIOS_ERR, "%s: BMP image (%zu) is less than expected minimum size (%zu).\n",
-				 __func__, logo_ptr_size, sizeof(efi_bmp_image_header));
-		return;
-	}
-
-	/* Convert BMP logo to GOP BLT format */
-	fsp_convert_bmp_to_gop_blt(logo_ptr, logo_ptr_size, &blt_buffer_addr, &blt_size,
-			   &logo_height, &logo_width, config->panel_orientation);
-
-	/* Override logo alignment if the default screen orientation is not normal */
-	if (config->panel_orientation != LB_FB_ORIENTATION_NORMAL)
-		config->logo_valignment = FW_SPLASH_VALIGNMENT_CENTER;
-
-	/* Calculate logo destination coordinates */
-	struct logo_coordinates logo_coords = calculate_logo_coordinates(horizontal_resolution,
-			 vertical_resolution, logo_width, logo_height, config->logo_valignment,
-			 FW_SPLASH_HALIGNMENT_CENTER);
-
-	/* Copy the logo to the framebuffer */
-	copy_logo_to_framebuffer(framebuffer_bar, bytes_per_scanline, blt_buffer_addr, logo_width,
-			 logo_height, logo_coords.x, logo_coords.y);
-
 	/*
 	 * If the device is in low-battery mode and the low-battery splash screen is being
 	 * displayed, prevent further operation and bail out early.
 	 */
-	if (platform_is_low_battery_shutdown_needed())
-		return;
-
-	if (CONFIG(SPLASH_SCREEN_FOOTER)) {
-		bmp_release_logo();
-		logo_ptr = (uintptr_t)bmp_load_logo_by_type(BOOTSPLASH_FOOTER, &logo_ptr_size);
-		if (!logo_ptr || logo_ptr_size < sizeof(efi_bmp_image_header)) {
-			printk(BIOS_ERR, "%s: BMP image (%zu) is less than expected minimum size (%zu).\n",
-				 __func__, logo_ptr_size, sizeof(efi_bmp_image_header));
-			return;
+	if (platform_is_low_battery_shutdown_needed()) {
+		if (render_logo_to_framebuffer(framebuffer_bar, bytes_per_scanline,
+				 horizontal_resolution, vertical_resolution, config,
+				 BOOTSPLASH_LOW_BATTERY) != 0) {
+			printk(BIOS_ERR, "%s: Failed to render low-battery logo.\n", __func__);
 		}
-
-		/* Convert BMP logo to GOP BLT format */
-		fsp_convert_bmp_to_gop_blt(logo_ptr, logo_ptr_size, &blt_buffer_addr, &blt_size,
-				   &logo_height, &logo_width, config->panel_orientation);
-
-		enum fw_splash_horizontal_alignment halignment = FW_SPLASH_HALIGNMENT_CENTER;
-		enum fw_splash_vertical_alignment valignment = FW_SPLASH_VALIGNMENT_CENTER;
-
-		/* Calculate logo destination coordinates */
-		switch (config->panel_orientation) {
-		case LB_FB_ORIENTATION_RIGHT_UP:
-			halignment = FW_SPLASH_HALIGNMENT_LEFT;
-			break;
-		case LB_FB_ORIENTATION_LEFT_UP:
-			halignment = FW_SPLASH_HALIGNMENT_RIGHT;
-			break;
-		case LB_FB_ORIENTATION_BOTTOM_UP:
-			valignment = FW_SPLASH_VALIGNMENT_TOP;
-			break;
-		default: /* LB_FB_ORIENTATION_NORMAL (default) */
-			valignment = FW_SPLASH_VALIGNMENT_BOTTOM;
-			break;
-		}
-
-		logo_coords = calculate_logo_coordinates(horizontal_resolution,
-			 vertical_resolution, logo_width, logo_height, valignment, halignment);
-
-		/* Copy the logo to the framebuffer */
-		copy_logo_to_framebuffer(framebuffer_bar, bytes_per_scanline, blt_buffer_addr,
-				 logo_width, logo_height, logo_coords.x, logo_coords.y);
+		goto cleanup;
 	}
 
+	/* Render the main logo */
+	if (render_logo_to_framebuffer(framebuffer_bar, bytes_per_scanline,
+				 horizontal_resolution, vertical_resolution, config,
+				 BOOTSPLASH_CENTER) != 0) {
+		printk(BIOS_ERR, "%s: Failed to render main splash screen logo.\n", __func__);
+	} else if (CONFIG(SPLASH_SCREEN_FOOTER)) {
+		/* Render the footer logo */
+		if (render_logo_to_framebuffer(framebuffer_bar, bytes_per_scanline,
+				 horizontal_resolution, vertical_resolution, config,
+				 BOOTSPLASH_FOOTER) != 0)
+			printk(BIOS_ERR, "%s: Failed to render footer logo.\n", __func__);
+	}
+
+cleanup:
 	/* Clear temporary Write Combine (WC) MTRR */
 	clear_var_mtrr(temp_mtrr_index);
 }

From 4a2c61a8a09bd5023fac6a297218b364698b0877 Mon Sep 17 00:00:00 2001
From: Subrata Banik <subratabanik@google.com>
Date: Sat, 21 Jun 2025 07:16:09 +0000
Subject: [PATCH 1367/3886] soc/qc/x1p42100: Allow building QC platform without
 upstream blobs

Qualcomm's latest SoC, the x1p42100, lacks upstreamed blobs. This
prevents coreboot builds because the default setting marks
CONFIG_USE_QC_BLOBS=y. As a result, build errors occur when the new
Qualcomm SoC blobs aren't in the upstream.

This change introduces `QC_BLOBS_UPSTREAM` Kconfig and set to default
`N` to build QC platform without relying on upstream blob support.
This is necessary for bringing up a new QC SoC-based platform, as
public QC blobs won't be available until later in the year. This
ensures that early QC development can proceed for QC SoC based
without depending on upstream blobs.

Override this Kconfig when QC blobs are available in upstream for
latest X1P42100 SoC.

TEST=Able to build google/bluey.

Change-Id: I04fde6e8917fb3f88c58eb2b55b47de1c2d33518
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88137
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
---
 src/soc/qualcomm/x1p42100/Kconfig     | 8 +++++++-
 src/soc/qualcomm/x1p42100/Makefile.mk | 9 ++++++---
 2 files changed, 13 insertions(+), 4 deletions(-)

diff --git a/src/soc/qualcomm/x1p42100/Kconfig b/src/soc/qualcomm/x1p42100/Kconfig
index d9d6a939af..7aa6481581 100644
--- a/src/soc/qualcomm/x1p42100/Kconfig
+++ b/src/soc/qualcomm/x1p42100/Kconfig
@@ -3,7 +3,6 @@
 config SOC_QUALCOMM_X1P42100
 	bool
 	default n
-	depends on USE_QC_BLOBS
 	select ARCH_BOOTBLOCK_ARMV8_64
 	select ARCH_RAMSTAGE_ARMV8_64
 	select ARCH_ROMSTAGE_ARMV8_64
@@ -28,6 +27,13 @@ config SOC_QUALCOMM_X1P42100
 
 if SOC_QUALCOMM_X1P42100
 
+config QC_BLOBS_UPSTREAM
+	bool "QC blobs are available in upstream repository"
+	select USE_QC_BLOBS
+	default n
+	help
+	  Select based on availability of QC blobs in upstream coreboot `3rdparty/qc_blobs`.
+
 config MEMLAYOUT_LD_FILE
 	string
 	default "src/soc/qualcomm/x1p42100/memlayout.ld"
diff --git a/src/soc/qualcomm/x1p42100/Makefile.mk b/src/soc/qualcomm/x1p42100/Makefile.mk
index 7627320dbc..7a8b928930 100644
--- a/src/soc/qualcomm/x1p42100/Makefile.mk
+++ b/src/soc/qualcomm/x1p42100/Makefile.mk
@@ -47,9 +47,11 @@ CPPFLAGS_common += -Isrc/soc/qualcomm/x1p42100/include
 CPPFLAGS_common += -Isrc/soc/qualcomm/common/include
 
 ################################################################################
+# look for QC blobs if QC SoC blobs are only available in upstream else ignore
+ifeq ($(CONFIG_QC_BLOBS_UPSTREAM),y)
 ifeq ($(CONFIG_USE_QC_BLOBS),y)
 # TODO: Upload X1P42100 SoC blobs
-X1P42100_BLOB := $(top)/3rdparty/qc_blobs/sc7280
+X1P42100_BLOB := $(top)/3rdparty/qc_blobs/x1p42100
 
 ifeq ($(CONFIG_QC_SDI_ENABLE),y)
 BL31_MAKEARGS += QTI_SDI_BUILD=1
@@ -187,6 +189,7 @@ $(GSI_FW_CBFS)-type := raw
 $(GSI_FW_CBFS)-compression := $(CBFS_COMPRESS_FLAG)
 cbfs-files-y += $(GSI_FW_CBFS)
 
-endif
+endif # ifeq ($(CONFIG_USE_QC_BLOBS),y)
 
-endif
+endif # ifeq ($(CONFIG_QC_BLOBS_UPSTREAM),y)
+endif # ifeq ($(CONFIG_SOC_QUALCOMM_X1P42100),y)

From 23f5df6eaefe7c23f5ff99d63e90a916a9736ba3 Mon Sep 17 00:00:00 2001
From: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Date: Tue, 17 Jun 2025 14:51:30 +0800
Subject: [PATCH 1368/3886] mb/google/nissa/var/yavilla: Add H58G66CK8BX147 to
 RAM ID table

DRAM Part Name                 ID to assign
H58G66CK8BX147                 1 (0001)

Yavilla use three memory strap pins for RAM_ID definition and it's consumed.
Since the MT62F1G32D4DR-031 WT:B was never used so it's safe to remove.
This CL make the H58G66CK8BX147 to set for RAM_ID1.

BUG=b:425545256
BRANCH=firmware-nissa-15217.B
TEST=emerge-nissa coreboot

Change-Id: I9df2710ceb77e4ace6de8976adc1285ef9784c03
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88121
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/google/brya/variants/yavilla/memory/Makefile.mk   | 2 +-
 .../google/brya/variants/yavilla/memory/dram_id.generated.txt   | 2 +-
 .../google/brya/variants/yavilla/memory/mem_parts_used.txt      | 2 +-
 3 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/src/mainboard/google/brya/variants/yavilla/memory/Makefile.mk b/src/mainboard/google/brya/variants/yavilla/memory/Makefile.mk
index 5cdc7f3809..26c31d4ef3 100644
--- a/src/mainboard/google/brya/variants/yavilla/memory/Makefile.mk
+++ b/src/mainboard/google/brya/variants/yavilla/memory/Makefile.mk
@@ -5,7 +5,7 @@
 
 SPD_SOURCES =
 SPD_SOURCES += spd/lp5/set-0/spd-1.hex      # ID = 0(0b0000)  Parts = MT62F512M32D2DR-031 WT:B, H9JCNNNBK3MLYR-N6E
-SPD_SOURCES += spd/lp5/set-0/spd-2.hex      # ID = 1(0b0001)  Parts = MT62F1G32D4DR-031 WT:B
+SPD_SOURCES += spd/lp5/set-0/spd-10.hex      # ID = 1(0b0001)  Parts = H58G66CK8BX147
 SPD_SOURCES += spd/lp5/set-0/spd-3.hex      # ID = 2(0b0010)  Parts = H58G56AK6BX069, K3LKBKB0BM-MGCP
 SPD_SOURCES += spd/lp5/set-0/spd-7.hex      # ID = 3(0b0011)  Parts = H58G56BK7BX068, MT62F1G32D2DS-026 WT:B, K3KL8L80CM-MGCT
 SPD_SOURCES += spd/lp5/set-0/spd-8.hex      # ID = 4(0b0100)  Parts = H58G66BK7BX067, MT62F2G32D4DS-026 WT:B, K3KL9L90CM-MGCT
diff --git a/src/mainboard/google/brya/variants/yavilla/memory/dram_id.generated.txt b/src/mainboard/google/brya/variants/yavilla/memory/dram_id.generated.txt
index 98aee2de2d..1264f20e91 100644
--- a/src/mainboard/google/brya/variants/yavilla/memory/dram_id.generated.txt
+++ b/src/mainboard/google/brya/variants/yavilla/memory/dram_id.generated.txt
@@ -5,7 +5,7 @@
 
 DRAM Part Name                 ID to assign
 MT62F512M32D2DR-031 WT:B       0 (0000)
-MT62F1G32D4DR-031 WT:B         1 (0001)
+H58G66CK8BX147                 1 (0001)
 H9JCNNNBK3MLYR-N6E             0 (0000)
 H58G56AK6BX069                 2 (0010)
 K3LKBKB0BM-MGCP                2 (0010)
diff --git a/src/mainboard/google/brya/variants/yavilla/memory/mem_parts_used.txt b/src/mainboard/google/brya/variants/yavilla/memory/mem_parts_used.txt
index d9e4129cba..76efa2cd44 100644
--- a/src/mainboard/google/brya/variants/yavilla/memory/mem_parts_used.txt
+++ b/src/mainboard/google/brya/variants/yavilla/memory/mem_parts_used.txt
@@ -10,7 +10,7 @@
 
 # Part Name
 MT62F512M32D2DR-031 WT:B
-MT62F1G32D4DR-031 WT:B
+H58G66CK8BX147
 H9JCNNNBK3MLYR-N6E
 H58G56AK6BX069
 K3LKBKB0BM-MGCP

From 782ae11bc7ac6570cc0d8a27c62eaa6b393de105 Mon Sep 17 00:00:00 2001
From: Jeremy Compostella <jeremy.compostella@intel.com>
Date: Fri, 13 Jun 2025 16:02:53 -0700
Subject: [PATCH 1369/3886] soc/intel/cmn/blk/cnvi: Add _PRR method for
 Bluetooth CNVi Reset

The change introduces new Advanced Configuration and Power Interface
(ACPI) methods to handle Bluetooth device states, including status
checks and device reset procedures. Specifically, it adds a Power
Resource for Reset (_PRR) method and the associated power resources to
enable Operating System (OS)-level resets for Connectivity Integrated
(CNVi) Bluetooth devices as specified in Intel document
number 559910. This allows the OS to perform Bluetooth hardware recovery
in case of errors, ensuring compliance with Intel's standards. The Power
Resource ACPI code was adapted from Panther Lake (PTL) Firmware Support
Package (FSP) revision 3144.01.

The new ACPI Bluetooth code introduces the CNMT mutex, similar to the
USB Bluetooth ACPI code, to avoid simultaneous CNVi resets when
executing Wi-Fi and Bluetooth power resource _RST methods.

TEST=The following two use cases were verified using acpidbg on a Fatcat
     device.
     1. Test CNVi Bluetooth _RST() completion.
        acpidbg -b 'evaluate \_SB.PCI0.CNVB.PRRS' # 0x0
        acpidbg -b 'evaluate \_SB.PCI0.CNVB.RSTT' # 0x0
        acpidbg -b 'set N \_SB.PCI0.CNVB.RSTT 1'  # 0x1
        acpidbg -b 'evaluate \_SB.PCI0.CNVB.CNVP._RST'
        acpidbg -b 'evaluate \_SB.PCI0.CNVB.PRRS' # 0x2
     2. Test that CNVi Wi-Fi _RST calls CNVi Bluetooth CFLR method.
        acpidbg -b 'evaluate \_SB.PCI0.CNVB.PRRS' # 0x0
        acpidbg -b 'evaluate \_SB.PCI0.CNVW.RSTT' # 0x0
        acpidbg -b 'set N \_SB.PCI0.CNVW.RSTT 1'  # 0x0
        acpidbg -b 'evaluate \_SB.PCI0.CNVW.CNVP._RST'
        acpidbg -b 'evaluate \_SB.PCI0.CNVB.PRRS' # 0x1

Change-Id: I2389901faf4fad131bb7226e356b47f4b1a4ddac
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88111
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Bora Guvendik <bora.guvendik@intel.corp-partner.google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
---
 src/soc/intel/common/block/cnvi/cnvi.c        | 313 +++++++++++++++++-
 .../common/block/include/intelblocks/cnvi.h   |   4 +-
 2 files changed, 315 insertions(+), 2 deletions(-)

diff --git a/src/soc/intel/common/block/cnvi/cnvi.c b/src/soc/intel/common/block/cnvi/cnvi.c
index 5c5be9e1dd..76d023f5f5 100644
--- a/src/soc/intel/common/block/cnvi/cnvi.c
+++ b/src/soc/intel/common/block/cnvi/cnvi.c
@@ -285,6 +285,12 @@ static void cnvw_fill_ssdt(const struct device *dev)
 						}
 						acpigen_pop_len();
 
+						acpigen_write_if_cond_ref_of("\\_SB.PCI0.CNVB");
+						{
+							acpigen_emit_namestring("\\_SB.PCI0.CNVB.CFLR");
+						}
+						acpigen_pop_len();
+
 						acpigen_emit_namestring("\\_SB.PCI0.PCRO");
 						acpigen_write_integer(PID_CNVI);
 						acpigen_write_integer(CNVI_ABORT_PLDR);
@@ -501,6 +507,311 @@ static const char *cnvi_bt_acpi_name(const struct device *dev)
 	return "CNVB";
 }
 
+static void cnvb_fill_ssdt(const struct device *dev)
+{
+	const char *scope = acpi_device_path(dev);
+
+/*
+ *	Mutex (CNMT, 0)
+ */
+	acpigen_write_scope("\\_SB.PCI0");
+	acpigen_write_mutex("CNMT", 0);
+	acpigen_write_scope_end();
+
+	acpi_device_write_pci_dev(dev);
+
+	acpigen_write_scope(scope);
+
+/*
+ *	OperationRegion (CBTR, SystemMemory, \_SB_.PCI0.BASE(_ADR), 0x100)
+ *	Field (CBTR, WordAcc, NoLock, Preserve) {
+ *	  VDID, 32, // 0x00, VID DID
+ *	  Offset(R_CNVI_CFG_GIO_DEV_CAP),
+ *	      , 28,
+ *	  BFLR,  1, // Function Level Reset Capable
+ *	  Offset(R_CNVI_CFG_GIO_DEV),
+ *	      , 15,
+ *	  BIFR,  1, // Init Function Level Reset
+ *	  Offset (R_CNVI_CFG_GIO_DEV_CAP_2),
+ *	      , 11,
+ *	  BLTS,  1, // LTR Mechanism Supported
+ *	  Offset (R_CNVI_CFG_GIO_DEV_2),
+ *	      , 10,
+ *	  BLTE,  1, // LTR Mechanism Enable
+ *	}
+ */
+
+	/* RegionOffset stored in Local0 */
+	/* Local0 = \_SB_.PCI0.BASE(_ADR) */
+	acpigen_write_store();
+	acpigen_emit_namestring("BASE");
+	acpigen_emit_namestring("_ADR");
+	acpigen_emit_byte(LOCAL0_OP);
+
+	acpigen_emit_ext_op(OPREGION_OP);
+	acpigen_emit_namestring("CBTR");
+	acpigen_emit_byte(SYSTEMMEMORY);
+	acpigen_emit_byte(LOCAL0_OP);
+	acpigen_write_integer(0x100);
+
+	struct fieldlist fields[] = {
+		FIELDLIST_OFFSET(0),
+		FIELDLIST_NAMESTR("VDID", 32),
+		FIELDLIST_OFFSET(CNVI_DEV_CAP),
+		FIELDLIST_RESERVED(28),
+		FIELDLIST_NAMESTR("BFLR", 1),
+		FIELDLIST_OFFSET(CNVI_DEV_CONTROL),
+		FIELDLIST_RESERVED(15),
+		FIELDLIST_NAMESTR("BIFR", 1),
+		FIELDLIST_OFFSET(CNVI_DEV_CAP_2),
+		FIELDLIST_RESERVED(11),
+		FIELDLIST_NAMESTR("BLTS", 1),
+		FIELDLIST_OFFSET(CNVI_DEV_CONTROL_2),
+		FIELDLIST_RESERVED(10),
+		FIELDLIST_NAMESTR("BLTE", 1),
+	};
+	acpigen_write_field("CBTR", fields, ARRAY_SIZE(fields),
+			    FIELD_WORDACC | FIELD_NOLOCK | FIELD_PRESERVE);
+
+/*
+ *	Name (_S0W, 3)
+ */
+	acpigen_write_name_integer("_S0W", ACPI_DEVICE_SLEEP_D3_HOT);
+
+/*
+ *	Name (PRRS, Zero)
+ *	Last _PRR Status
+ *	0: Non-Platform-Level Device Reset (PLDR) executed [Default]
+ *	1: Core PLDR Completed successfully
+ *	2: Product PLDR Completed successfully
+ *	3: Previous PLDR Not Completed
+ *	4: Product PLDR timeout
+ */
+	acpigen_write_name_integer("PRRS", 0);
+
+/*
+ *	Name (RSTT, Zero)
+ *	Reset Type
+ *	0: Core Reset
+ *	1: Product Reset
+ */
+	acpigen_write_name_integer("RSTT", 0);
+
+/*
+ *	Bluetooth PLDR request delay (default 50 ms)
+ */
+	acpigen_write_name_integer("BTDL", 50);
+
+/*
+ *	PowerResource (CNVP, 0x05, 0x0000)
+ *	{
+ *		Method (_STA, 0, NotSerialized)  // _STA: Status
+ *		{
+ *			Return (One)
+ *		}
+ *
+ *		Method (_ON, 0, NotSerialized)  // _ON_: Power On
+ *		{
+ *		}
+ *
+ *		Method (_OFF, 0, NotSerialized)  // _OFF: Power Off
+ *		{
+ *		}
+ *
+ *		Method (_RST, 0, NotSerialized)  // _RST: Device Reset
+ *		{
+ *			Local0 = Acquire (\_SB.PCI0.CNMT, 0x03E8)
+ *			If ((Local0 == Zero))
+ *			{
+ *				CFLR ()
+ *				If ((RSTT == One))
+ *				{
+ *					Local0 = \_SB.PCI0.PCRR(PID_CNVI, CNVI_ABORT_PLDR)
+ *					Local0 &= CNVI_ABORT_REQUEST
+ *					If ((Local0 == Zero))
+ *					{
+ *						\_SB.PCI0.PCRO (PID_CNVI, CNVI_ABORT_PLDR, 0x03)
+ *						Sleep (BTDL)
+ *						Local0 = \_SB.PCI0.PCRR(PID_CNVI, CNVI_ABORT_PLDR)
+ *						Local1 = (Local0 & CNVI_ABORT_REQUEST)
+ *						Local3 = (Local0 & CNVI_READY)
+ *						If ((Local1 == Zero))
+ *						{
+ *							If ((Local3 == CNVI_READY))
+ *							{
+ *								PRRS = CNVI_PLDR_COMPLETE
+ *							}
+ *						}
+ *						Else
+ *						{
+ *							PRRS = CNVI_PLDR_TIMEOUT
+ *						}
+ *					}
+ *					Else
+ *					{
+ *						PRRS = CNVI_PLDR_NOT_COMPLETE
+ *					}
+ *				}
+ *
+ *				If ((BLTS == One))
+ *				{
+ *					If ((BLTE == Zero))
+ *					{
+ *						BLTE = One
+ *					}
+ *				}
+ *
+ *				Release (\_SB.PCI0.CNMT)
+ *			}
+ *		}
+ *	}
+ */
+	acpigen_write_power_res("CNVP", 5, 0, NULL, 0);
+	{
+		acpigen_write_method("_STA", 0);
+		{
+			acpigen_write_return_integer(1);
+		}
+		acpigen_pop_len();
+
+		acpigen_write_method("_ON", 0);
+		{
+			// Empty method body
+		}
+		acpigen_pop_len();
+
+		acpigen_write_method("_OFF", 0);
+		{
+			// Empty method body
+		}
+		acpigen_pop_len();
+
+		acpigen_write_method("_RST", 0);
+		{
+			acpigen_write_store();
+			acpigen_write_acquire("\\_SB.PCI0.CNMT", 1000);
+			acpigen_emit_byte(LOCAL0_OP);
+
+			acpigen_write_if_lequal_op_int(LOCAL0_OP, 0);
+			{
+				acpigen_emit_namestring("CFLR");
+
+				acpigen_write_if_lequal_namestr_int("RSTT", 1);
+				{
+					acpigen_write_store();
+					acpigen_emit_namestring("\\_SB.PCI0.PCRR");
+					acpigen_write_integer(PID_CNVI);
+					acpigen_write_integer(CNVI_ABORT_PLDR);
+					acpigen_emit_byte(LOCAL0_OP);
+
+					acpigen_emit_byte(AND_OP);
+					acpigen_emit_byte(LOCAL0_OP);
+					acpigen_write_integer(CNVI_ABORT_REQUEST);
+					acpigen_emit_byte(LOCAL0_OP);
+
+					acpigen_write_if_lequal_op_int(LOCAL0_OP, 0);
+					{
+						acpigen_emit_namestring("\\_SB.PCI0.PCRO");
+						acpigen_write_integer(PID_CNVI);
+						acpigen_write_integer(CNVI_ABORT_PLDR);
+						acpigen_write_integer(CNVI_ABORT_REQUEST | CNVI_ABORT_ENABLE);
+
+						acpigen_emit_ext_op(SLEEP_OP);
+						acpigen_emit_namestring("BTDL");
+
+						acpigen_write_store();
+						acpigen_emit_namestring("\\_SB.PCI0.PCRR");
+						acpigen_write_integer(PID_CNVI);
+						acpigen_write_integer(CNVI_ABORT_PLDR);
+						acpigen_emit_byte(LOCAL0_OP);
+
+						acpigen_emit_byte(AND_OP);
+						acpigen_emit_byte(LOCAL0_OP);
+						acpigen_write_integer(CNVI_ABORT_REQUEST);
+						acpigen_emit_byte(LOCAL1_OP);
+
+						acpigen_emit_byte(AND_OP);
+						acpigen_emit_byte(LOCAL0_OP);
+						acpigen_write_integer(CNVI_READY);
+						acpigen_emit_byte(LOCAL3_OP);
+
+						acpigen_write_if_lequal_op_int(LOCAL1_OP, 0);
+						{
+							acpigen_write_if_lequal_op_int(LOCAL3_OP, CNVI_READY);
+							{
+								acpigen_write_store_int_to_namestr(CNVI_PLDR_COMPLETE, "PRRS");
+							}
+							acpigen_pop_len();
+						}
+						acpigen_write_else();
+						{
+							acpigen_write_store_int_to_namestr(CNVI_PLDR_TIMEOUT, "PRRS");
+						}
+						acpigen_pop_len();
+					}
+					acpigen_write_else();
+					{
+						acpigen_write_store_int_to_namestr(CNVI_PLDR_NOT_COMPLETE, "PRRS");
+					}
+					acpigen_pop_len();
+				}
+				acpigen_pop_len();
+
+				acpigen_write_if_lequal_namestr_int("BLTS", 1);
+				{
+					acpigen_write_if_lequal_namestr_int("BLTE", 0);
+					{
+						acpigen_write_store_int_to_namestr(1, "BLTE");
+					}
+					acpigen_pop_len();
+				}
+				acpigen_pop_len();
+
+				acpigen_write_release("\\_SB.PCI0.CNMT");
+			}
+			acpigen_pop_len();
+		}
+		acpigen_pop_len();
+	}
+	acpigen_write_power_res_end();
+
+/*
+ *	Name (_PRR, Package (0x01)  // _PRR: Power Resource for Reset
+ *	{
+ *		CNVP
+ *	})
+*/
+	acpigen_write_name("_PRR");
+	{
+		acpigen_write_package(1);
+		acpigen_emit_namestring("CNVP");
+	}
+	acpigen_pop_len();
+
+/*
+ *	Method (CFLR, 0, NotSerialized)
+ *	{
+ *		If ((BFLR == One))
+ *		{
+ *			BIFR = One
+ *			PRRS = One
+ *		}
+ *	}
+*/
+	acpigen_write_method("CFLR", 0);
+	{
+		acpigen_write_if_lequal_namestr_int("BFLR", 1);
+		{
+			acpigen_write_store_int_to_namestr(1, "BIFR");
+			acpigen_write_store_int_to_namestr(1, "PRRS");
+		}
+		acpigen_pop_len();
+	}
+	acpigen_pop_len();
+
+	acpigen_write_scope_end();
+}
+
 static struct device_operations cnvi_bt_ops = {
 	.read_resources		= pci_dev_read_resources,
 	.set_resources		= pci_dev_set_resources,
@@ -508,7 +819,7 @@ static struct device_operations cnvi_bt_ops = {
 	.ops_pci		= &pci_dev_ops_pci,
 	.scan_bus		= scan_static_bus,
 	.acpi_name		= cnvi_bt_acpi_name,
-	.acpi_fill_ssdt		= acpi_device_write_pci_dev,
+	.acpi_fill_ssdt		= cnvb_fill_ssdt,
 };
 
 static const unsigned short bt_pci_device_ids[] = {
diff --git a/src/soc/intel/common/block/include/intelblocks/cnvi.h b/src/soc/intel/common/block/include/intelblocks/cnvi.h
index c6fe131d97..478bdaad1e 100644
--- a/src/soc/intel/common/block/include/intelblocks/cnvi.h
+++ b/src/soc/intel/common/block/include/intelblocks/cnvi.h
@@ -3,10 +3,12 @@
 #ifndef _SOC_INTEL_COMMON_CNVI_H_
 #define _SOC_INTEL_COMMON_CNVI_H_
 
-/* CNVi WiFi Register */
+/* CNVi PCI configuration Registers */
 #define CNVI_DEV_CAP		0x44
 #define CNVI_DEV_CONTROL	0x48
 #define CNVI_POWER_STATUS	0xcc
+#define CNVI_DEV_CAP_2		0x64
+#define CNVI_DEV_CONTROL_2	0x68
 
 /* CNVi PLDR Results */
 #define CNVI_PLDR_COMPLETE	0x02

From ff46501d6d9dfb4b6a81198e21d66b774f2c69d2 Mon Sep 17 00:00:00 2001
From: Jeremy Compostella <jeremy.compostella@intel.com>
Date: Mon, 16 Jun 2025 11:02:14 -0700
Subject: [PATCH 1370/3886] soc/intel/cmn/blk/cnvi: Correct generated ACPI code
 in comments

Align the ACPI code comments with the actual generated code for Wi-Fi
power resource management. This change enhances the maintainability and
readability of the code by ensuring that comments accurately reflect the
runtime SSDT code.

Change-Id: Ie33c716305251356a462b086fa8c61ec8d16c3cb
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88112
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
---
 src/soc/intel/common/block/cnvi/cnvi.c | 75 +++++++++++++++++---------
 1 file changed, 49 insertions(+), 26 deletions(-)

diff --git a/src/soc/intel/common/block/cnvi/cnvi.c b/src/soc/intel/common/block/cnvi/cnvi.c
index 76d023f5f5..4c1c0f228d 100644
--- a/src/soc/intel/common/block/cnvi/cnvi.c
+++ b/src/soc/intel/common/block/cnvi/cnvi.c
@@ -113,64 +113,87 @@ static void cnvw_fill_ssdt(const struct device *dev)
 	acpigen_write_name_integer("RSTT", 0);
 
 /*
- *	PowerResource(CNVP, 0, 0)
+ *	PowerResource (CNVP, 0x00, 0x0000)
  *	{
- *		Method(_STA)
+ *		Method (_STA, 0, NotSerialized)  // _STA: Status
  *		{
- *			If (CondRefOf (\_SB.PCI0.CNVS)) {
+ *			If (CondRefOf (\_SB.PCI0.CNVS))
+ *			{
  *				Local0 = \_SB.PCI0.CNVS()
  *				Return (Local0)
  *			}
  *			Else
  *			{
- *				Return (0x01)
+ *				Return (One)
  *			}
  *		}
- *		Method(_ON, 0)
+ *
+ *		Method (_ON, 0, NotSerialized)  // _ON_: Power On
  *		{
- *			If (CondRefOf (\_SB.PCI0.CNVC)) {
- *				If ((\_SB.PCI0.CNVS() == 1)) {
- *					Return (1)
+ *			If (CondRefOf (\_SB.PCI0.CNVC))
+ *			{
+ *				Local0 = \_SB.PCI0.CNVS()
+ *				If ((Local0 == One))
+ *				{
+ *					Return (One)
  *				}
- *				\_SB.PCI0.CNVS(1)
+ *
+ *				\_SB.PCI0.CNVC (One)
  *			}
  *		}
- *		Method(_OFF, 0)
+ *
+ *		Method (_OFF, 0, NotSerialized)  // _OFF: Power Off
  *		{
- *			If (CondRefOf (\_SB.PCI0.CNVC)) {
- *				\_SB.PCI0.CNVS(0)
+ *			If (CondRefOf (\_SB.PCI0.CNVC))
+ *			{
+ *				\_SB.PCI0.CNVC (Zero)
  *			}
  *		}
- *		Method(_RST, 0, NotSerialized)
+ *
+ *		Method (_RST, 0, NotSerialized)  // _RST: Device Reset
  *		{
- *			Local0 = Acquire (\_SB.PCI0.CNMT, 1000)
+ *			Local0 = Acquire (\_SB.PCI0.CNMT, 0x03E8)
  *			If ((Local0 == Zero))
  *			{
  *				CFLR ()
  *				PRRS = One
  *				If ((RSTT == One))
  *				{
- *					If (((PCRR (CNVI_SIDEBAND_ID, CNVI_ABORT_PLDR) & CNVI_ABORT_REQUEST) == Zero))
+ *					Local0 = \_SB.PCI0.PCRR(PID_CNVI, CNVI_ABORT_PLDR)
+ *					Local0 &= CNVI_ABORT_REQUEST
+ *					If ((Local0 == Zero))
  *					{
  *						Local2 = Zero
- *						If (CondRefOf (\_SB.PCI0.GBTR)) {
- *							If ((\_SB.PCI0.GBTR() == One))
+ *						If (CondRefOf (\_SB.PCI0.GBTR))
+ *						{
+ *							If ((\_SB.PCI0.GBTR == One))
  *							{
  *								\_SB.PCI0.BTRK (Zero)
- *								Sleep (160)
+ *								Sleep (0xA0)
  *								Local2 = One
  *							}
  *						}
- *						PCRO (CNVI_SIDEBAND_ID, CNVI_ABORT_PLDR, CNVI_ABORT_REQUEST | CNVI_ABORT_ENABLE)
- *						Sleep (10)
- *						Local1 = PCRR (CNVI_SIDEBAND_ID, CNVI_ABORT_PLDR)
- *						If ((((Local1 & CNVI_ABORT_REQUEST) == Zero) && (Local1 & CNVI_READY)))
+ *
+ *						If (CondRefOf (\_SB.PCI0.CNVB))
  *						{
- *							PRRS = CNVI_PLDR_COMPLETE
- *							If ((Local2 == One))
+ *							\_SB.PCI0.CNVB.CFLR ()
+ *						}
+ *
+ *						\_SB.PCI0.PCRO (PID_CNVI, CNVI_ABORT_PLDR, 0x03)
+ *						Sleep (0x0A)
+ *						Local0 = \_SB.PCI0.PCRR(PID_CNVI, CNVI_ABORT_PLDR)
+ *						Local1 = (Local0 & CNVI_ABORT_REQUEST)
+ *						Local3 = (Local0 & CNVI_READY)
+ *						If ((Local1 == Zero))
+ *						{
+ *							If ((Local3 == CNVI_READY))
  *							{
- *								\_SB.PCI0.BTRK (One)
- *								Sleep (160)
+ *								PRRS = CNVI_PLDR_COMPLETE
+ *								If ((Local2 == One))
+ *								{
+ *									\_SB.PCI0.BTRK (One)
+ *									Sleep (0xA0)
+ *								}
  *							}
  *						}
  *						Else

From 1be1ccb42efcf121cd2c6661f501cb89671ee67b Mon Sep 17 00:00:00 2001
From: Jeremy Compostella <jeremy.compostella@intel.com>
Date: Mon, 16 Jun 2025 17:15:34 -0700
Subject: [PATCH 1371/3886] soc/intel/cmn/blk/cnvi: Use WFDL field for Wi-Fi
 PLDR reset delay

Introduce a new ACPI field, "WFDL", to specify the Power Level Device
Reset (PLDR) delay for Wi-Fi operations. This replaces the previously
hardcoded delay value, allowing for easier adjustment and configuration
of the PLDR timing in the future. By utilizing a named field, this
change facilitates potential updates to delay configurations.

Change-Id: I0f243ccf404afb83554136a3a310a98d6100d8ff
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88116
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Bora Guvendik <bora.guvendik@intel.corp-partner.google.com>
---
 src/soc/intel/common/block/cnvi/cnvi.c | 10 ++++++++--
 1 file changed, 8 insertions(+), 2 deletions(-)

diff --git a/src/soc/intel/common/block/cnvi/cnvi.c b/src/soc/intel/common/block/cnvi/cnvi.c
index 4c1c0f228d..d1d959aaa9 100644
--- a/src/soc/intel/common/block/cnvi/cnvi.c
+++ b/src/soc/intel/common/block/cnvi/cnvi.c
@@ -112,6 +112,11 @@ static void cnvw_fill_ssdt(const struct device *dev)
  */
 	acpigen_write_name_integer("RSTT", 0);
 
+/*
+ *	Wi-Fi PLDR request delay (default 10 ms)
+ */
+	acpigen_write_name_integer("WFDL", 10);
+
 /*
  *	PowerResource (CNVP, 0x00, 0x0000)
  *	{
@@ -180,7 +185,7 @@ static void cnvw_fill_ssdt(const struct device *dev)
  *						}
  *
  *						\_SB.PCI0.PCRO (PID_CNVI, CNVI_ABORT_PLDR, 0x03)
- *						Sleep (0x0A)
+ *						Sleep (WFDL)
  *						Local0 = \_SB.PCI0.PCRR(PID_CNVI, CNVI_ABORT_PLDR)
  *						Local1 = (Local0 & CNVI_ABORT_REQUEST)
  *						Local3 = (Local0 & CNVI_READY)
@@ -319,7 +324,8 @@ static void cnvw_fill_ssdt(const struct device *dev)
 						acpigen_write_integer(CNVI_ABORT_PLDR);
 						acpigen_write_integer(CNVI_ABORT_REQUEST | CNVI_ABORT_ENABLE);
 
-						acpigen_write_sleep(10);
+						acpigen_emit_ext_op(SLEEP_OP);
+						acpigen_emit_namestring("WFDL");
 
 						acpigen_write_store();
 						acpigen_emit_namestring("\\_SB.PCI0.PCRR");

From 81d7bc386ec639991fbd49a29e8e045c49c74195 Mon Sep 17 00:00:00 2001
From: Jeremy Compostella <jeremy.compostella@intel.com>
Date: Tue, 17 Jun 2025 16:21:45 -0700
Subject: [PATCH 1372/3886] soc/intel/cmn/blk/cnvi: Set WFDL default value to
 50 ms

The previous default value of 10 milliseconds is being updated to 50
milliseconds to comply with the latest guidelines (Panther Lake FSP
release 3144.01 CnviWifi.asl file).

TEST=Invoke the following set of acpidbg commands to verify that the
     _RST method still reaches state 2.
     acpidbg -b 'evaluate \_SB.PCI0.CNVW.PRRS' # 0x0
     acpidbg -b 'set N  \_SB.PCI0.CNVW.RSTT 1'
     acpidbg -b 'evaluate \_SB.PCI0.CNVW.CNVP._RST'
     acpidbg -b 'evaluate \_SB.PCI0.CNVW.PRRS' # 0x2

Change-Id: I2b0236c17117d368c1ee98e56c4c1b6525d63e27
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88135
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Bora Guvendik <bora.guvendik@intel.corp-partner.google.com>
---
 src/soc/intel/common/block/cnvi/cnvi.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/soc/intel/common/block/cnvi/cnvi.c b/src/soc/intel/common/block/cnvi/cnvi.c
index d1d959aaa9..cb19abc2e5 100644
--- a/src/soc/intel/common/block/cnvi/cnvi.c
+++ b/src/soc/intel/common/block/cnvi/cnvi.c
@@ -113,9 +113,9 @@ static void cnvw_fill_ssdt(const struct device *dev)
 	acpigen_write_name_integer("RSTT", 0);
 
 /*
- *	Wi-Fi PLDR request delay (default 10 ms)
+ *	Wi-Fi PLDR request delay (default 50 ms)
  */
-	acpigen_write_name_integer("WFDL", 10);
+	acpigen_write_name_integer("WFDL", 50);
 
 /*
  *	PowerResource (CNVP, 0x00, 0x0000)

From d92b6163e72d2cfb016067bcabe79d71ab348251 Mon Sep 17 00:00:00 2001
From: Jeremy Compostella <jeremy.compostella@intel.com>
Date: Mon, 16 Jun 2025 14:41:39 -0700
Subject: [PATCH 1373/3886] drivers/wifi/generic: Implement Wi-Fi PRR DSM
 functions

This commit introduces Power Resource for Reset (PRR) Device-Specific
Methods (DSM) "7266172c-220b-4b29-814f-75e4dd26b5fd" functions 2 and 5,
enabling access to the Power Resource Reset mode, status and delay. It
meets the DSM requirements listed in Intel Document number 559910. The
Power Resource Advanced Configuration and Power Interface (ACPI) code
was adapted from Panther Lake (PTL) Firmware Support Package (FSP)
revision 3144.01 (IntelWifiDsmFunc2.asl and IntelWifiDsmFunc5.dsl).

TEST=The following sequence of acpidbg commands was used to verify
     functions 2 and 5 behavior on a Fatcat device.
     acpidbg -b "evaluate \_SB.PCI0.CNVW._DSM \
             (2c 17 66 72 0b 22 29 4b 81 4f 75 e4 dd 26 b5 fd) \
             0 2 (01 00 00 00)" # Get PRR mode (type): 0x0
     acpidbg -b "evaluate \_SB.PCI0.CNVW._DSM \
             (2c 17 66 72 0b 22 29 4b 81 4f 75 e4 dd 26 b5 fd) \
             0 2 (02 00 01 00)" # Set PRR mode (type) to 0x1
     acpidbg -b "evaluate \_SB.PCI0.CNVW._DSM \
             (2c 17 66 72 0b 22 29 4b 81 4f 75 e4 dd 26 b5 fd) \
             0 2 (01 00 00 00)" # Get PRR mode (type): 0x1
     acpidbg -b "evaluate \_SB.PCI0.CNVW._DSM \
             (2c 17 66 72 0b 22 29 4b 81 4f 75 e4 dd 26 b5 fd) \
             0 2 (03 00 00 00)" # Get PRR status: 0x0
     acpidbg -b "evaluate \_SB.PCI0.CNVW.CNVP._RST"
     acpidbg -b "evaluate \_SB.PCI0.CNVW._DSM \
             (2c 17 66 72 0b 22 29 4b 81 4f 75 e4 dd 26 b5 fd) \
             0 2 (03 00 00 00)" # Get PRR status: 0x2
     acpidbg -b 'evaluate \_SB.PCI0.CNVW.WFDL' # 0x32
     acpidbg -b "evaluate \_SB.PCI0.CNVW._DSM \
           (2c 17 66 72 0b 22 29 4b 81 4f 75 e4 dd 26 b5 fd) \
           0 5 60"
     acpidbg -b 'evaluate \_SB.PCI0.CNVW.WFDL' # 0x3C

Change-Id: I6b9d3b2d407d458a94cc2a1695c84f5dc00f9d1a
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88114
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/drivers/wifi/generic/acpi.c | 102 +++++++++++++++++++++++++++-----
 1 file changed, 87 insertions(+), 15 deletions(-)

diff --git a/src/drivers/wifi/generic/acpi.c b/src/drivers/wifi/generic/acpi.c
index e64ff01a59..7c53b247ab 100644
--- a/src/drivers/wifi/generic/acpi.c
+++ b/src/drivers/wifi/generic/acpi.c
@@ -261,6 +261,82 @@ static void wifi_dsm_ddrrfim_func3_cb(void *ptr)
 	acpigen_write_return_integer(is_cnvi_ddr_rfim_enabled ? 0 : 1);
 }
 
+/*
+ * Function 2: Power Resource for Reset (PRR) for Wi-Fi
+ *
+ * Args3 is a buffer comparable to the following C structure:
+ * struct pldr_mode {
+ *	uint16_t cmd_type;
+ *	uint16_t cmd_payload;
+ * };
+ *
+ * cmd_type can take one of the following values:
+ * 1 - Get PRR mode;
+ * 2 - Set PRR mode to cmd_payload;
+ * 3 - Get PRR status;
+ */
+static void wifi_dsm_power_resource_for_reset(__always_unused void *args)
+{
+	acpigen_write_create_word_field(ARG3_OP, 0, "CMDT");
+	acpigen_write_create_word_field(ARG3_OP, 2, "CMDP");
+
+	/* Get PRR mode */
+	acpigen_write_if_lequal_namestr_int("CMDT", 1);
+	{
+		acpigen_write_if_cond_ref_of("RSTT");
+		{
+			acpigen_write_return_namestr("RSTT");
+
+		}
+		acpigen_pop_len();
+		acpigen_write_return_integer(0);
+	}
+	acpigen_pop_len();
+
+	/* Set PRR mode */
+	acpigen_write_if_lequal_namestr_int("CMDT", 2);
+	{
+		acpigen_write_if_cond_ref_of("RSTT");
+		{
+			acpigen_write_store();
+			acpigen_emit_namestring("CMDP");
+			acpigen_emit_namestring("RSTT");
+
+		}
+		acpigen_pop_len();
+		acpigen_write_return_integer(0);
+	}
+	acpigen_pop_len();
+
+	/* Get last PRR status */
+	acpigen_write_if_lequal_namestr_int("CMDT", 3);
+	{
+		acpigen_write_if_cond_ref_of("PRRS");
+		{
+			acpigen_write_return_namestr("PRRS");
+		}
+		acpigen_pop_len();
+		acpigen_write_return_integer(0);
+	}
+	acpigen_pop_len();
+
+	acpigen_write_return_integer(0);
+}
+
+/*
+ * Function 5: Set Power Resource for Reset (PRR) reset delay for Wi-Fi
+ */
+static void wifi_dsm_set_prr_reset_delay(__always_unused void *args)
+{
+	acpigen_write_if_cond_ref_of("WFDL");
+	{
+		acpigen_write_store();
+		acpigen_emit_byte(ARG3_OP);
+		acpigen_emit_namestring("WFDL");
+	}
+	acpigen_pop_len();
+}
+
 static void (*wifi_dsm_callbacks[])(void *) = {
 	NULL,					/* Function 0 */
 	wifi_dsm_srd_active_channels,		/* Function 1 */
@@ -277,15 +353,13 @@ static void (*wifi_dsm_callbacks[])(void *) = {
 	wifi_dsm_11be_country_enablement,	/* Function 12 */
 };
 
-/*
- * The current DSM2 table is only exporting one function (function 3), some more
- * functions are reserved so marking them NULL.
-*/
 static void (*wifi_dsm2_callbacks[])(void *) = {
-	NULL,				/* Function 0 */
-	NULL,				/* Function 1 */
-	NULL,				/* Function 2 */
-	wifi_dsm_ddrrfim_func3_cb,	/* Function 3 */
+	NULL,					/* Function 0 */
+	NULL,					/* Function 1 */
+	wifi_dsm_power_resource_for_reset,	/* Function 2 */
+	wifi_dsm_ddrrfim_func3_cb,		/* Function 3 */
+	NULL,					/* Function 4 */
+	wifi_dsm_set_prr_reset_delay,		/* Function 5 */
 };
 
 static const uint8_t *sar_fetch_set(const struct sar_profile *sar, size_t set_num)
@@ -1117,13 +1191,11 @@ static void wifi_ssdt_write_properties(const struct device *dev, const char *sco
 		}
 	}
 
-	if (is_cnvi_ddr_rfim_enabled) {
-		dsm_ids[dsm_count].uuid = ACPI_DSM_RFIM_WIFI_UUID;
-		dsm_ids[dsm_count].callbacks = &wifi_dsm2_callbacks[0];
-		dsm_ids[dsm_count].count = ARRAY_SIZE(wifi_dsm2_callbacks);
-		dsm_ids[dsm_count].arg = &is_cnvi_ddr_rfim_enabled;
-		dsm_count++;
-	}
+	dsm_ids[dsm_count].uuid = ACPI_DSM_RFIM_WIFI_UUID;
+	dsm_ids[dsm_count].callbacks = &wifi_dsm2_callbacks[0];
+	dsm_ids[dsm_count].count = ARRAY_SIZE(wifi_dsm2_callbacks);
+	dsm_ids[dsm_count].arg = &is_cnvi_ddr_rfim_enabled;
+	dsm_count++;
 
 	acpigen_write_dsm_uuid_arr(dsm_ids, dsm_count);
 

From efa24540b09c1e70f6b3110f5f56bdd023efb85a Mon Sep 17 00:00:00 2001
From: Jeremy Compostella <jeremy.compostella@intel.com>
Date: Mon, 16 Jun 2025 15:42:50 -0700
Subject: [PATCH 1374/3886] drivers/wifi/generic: Implement Bluetooth PRR DSM
 functions

This commit introduces Bluetooth Device-Specific Methods (DSM)
"7266172c-220b-4b29-814f-75e4dd26b5fd" functions 5, 6 and 7, enabling
access to the Power Resource for Reset (PRR) mode, status and reset
delay. It meets the DSM requirements listed in Intel Document number
559910. The Power Resource Advanced Configuration and Power
Interface (ACPI) code was adapted from Panther Lake (PTL) Firmware
Support Package (FSP) revision 3144.01 (IntelBtDsmFunc5.asl,
IntelBtDsmFunc6.asl and IntelBtDsmFunc7.asl).

TEST=The following sequence of acpidbg commands was used to verify
     functions 5, 6 and 7 behavior on a Fatcat device.
     acpidbg -b "evaluate \_SB.PCI0.CNVB._DSM \
           (2c 17 66 72 0b 22 29 4b 81 4f 75 e4 dd 26 b5 fd) \
           0 6 0" # Get PRR mode and status: [0x0 0x0]
     acpidbg -b "evaluate \_SB.PCI0.CNVB._DSM \
           (2c 17 66 72 0b 22 29 4b 81 4f 75 e4 dd 26 b5 fd) \
           0 5 (01 00 01 00)" # Set PRR mode (type) to 0x1
     acpidbg -b "evaluate \_SB.PCI0.CNVB._DSM \
           (2c 17 66 72 0b 22 29 4b 81 4f 75 e4 dd 26 b5 fd) \
           0 6 0" # Get PRR mode and status: [0x1 0x0]
     acpidbg -b 'evaluate \_SB.PCI0.CNVB.BTDL' # 0x32
     acpidbg -b "evaluate \_SB.PCI0.CNVB._DSM \
           (2c 17 66 72 0b 22 29 4b 81 4f 75 e4 dd 26 b5 fd) \
           0 7 60"
     acpidbg -b 'evaluate \_SB.PCI0.CNVB.BTDL' # 0x3C

Change-Id: I3b0a77f3c2b7bec5dcb909a1266c7d5f4d5a8d1e
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88115
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Bora Guvendik <bora.guvendik@intel.corp-partner.google.com>
---
 src/drivers/wifi/generic/acpi.c | 96 ++++++++++++++++++++++++++++++++-
 1 file changed, 95 insertions(+), 1 deletion(-)

diff --git a/src/drivers/wifi/generic/acpi.c b/src/drivers/wifi/generic/acpi.c
index 7c53b247ab..753492abad 100644
--- a/src/drivers/wifi/generic/acpi.c
+++ b/src/drivers/wifi/generic/acpi.c
@@ -362,6 +362,89 @@ static void (*wifi_dsm2_callbacks[])(void *) = {
 	wifi_dsm_set_prr_reset_delay,		/* Function 5 */
 };
 
+/*
+ * Function 5: Set Power Resource for Reset (PRR) mode for Bluetooth
+ *
+ * Args3 is a buffer comparable to the following C structure:
+ * struct pldr_mode {
+ *	uint16_t cmd_type;
+ *	uint16_t cmd_payload;
+ * };
+ *
+ * cmd_type can take one of the following values:
+ * 1 - Set PRR mode to cmd_payload;
+ */
+static void bluetooth_dsm_set_power_resource_for_reset(__always_unused void *args)
+{
+	acpigen_write_create_word_field(ARG3_OP, 0, "BCMT");
+	acpigen_write_create_word_field(ARG3_OP, 2, "BCMP");
+
+	/* Set PRR mode */
+	acpigen_write_if_lequal_namestr_int("BCMT", 1);
+	{
+		acpigen_write_if_cond_ref_of("RSTT");
+		{
+			acpigen_write_store();
+			acpigen_emit_namestring("BCMP");
+			acpigen_emit_namestring("RSTT");
+
+		}
+		acpigen_pop_len();
+	}
+	acpigen_pop_len();
+
+	acpigen_write_return_integer(0);
+}
+
+/*
+ * Function 6: Get Power Resource for Reset (PRR) mode and status for Bluetooth
+ */
+static void bluetooth_dsm_get_power_resource_for_reset(__always_unused void *args)
+{
+	/* Get PRR mode and status */
+	acpigen_write_if_cond_ref_of("RSTT");
+	{
+		acpigen_write_if_cond_ref_of("PRRS");
+		{
+			acpigen_emit_byte(RETURN_OP);
+			acpigen_write_package(2);
+			acpigen_emit_namestring("RSTT");
+			acpigen_emit_namestring("PRRS");
+			acpigen_pop_len();
+		}
+		acpigen_pop_len();
+	}
+	acpigen_pop_len();
+
+	acpigen_write_return_integer(0);
+}
+
+/*
+ * Function 7: Set Power Resource for Reset (PRR) reset delay for Bluetooth
+ */
+static void bluetooth_dsm_set_prr_reset_delay(__always_unused void *args)
+{
+	acpigen_write_if_cond_ref_of("BTDL");
+	{
+		acpigen_write_store();
+		acpigen_emit_byte(ARG3_OP);
+		acpigen_emit_namestring("BTDL");
+	}
+	acpigen_pop_len();
+}
+
+
+static void (*bluetooth_dsm_callbacks[])(void *) = {
+	NULL,						/* Function 0 */
+	NULL,						/* Function 1 */
+	NULL,						/* Function 2 */
+	NULL,						/* Function 3 */
+	NULL,						/* Function 4 */
+	bluetooth_dsm_set_power_resource_for_reset,	/* Function 5 */
+	bluetooth_dsm_get_power_resource_for_reset,	/* Function 6 */
+	bluetooth_dsm_set_prr_reset_delay,		/* Function 7 */
+};
+
 static const uint8_t *sar_fetch_set(const struct sar_profile *sar, size_t set_num)
 {
 	const uint8_t *sar_table = &sar->sar_table[0];
@@ -1212,7 +1295,7 @@ static void wifi_ssdt_write_properties(const struct device *dev, const char *sco
 
 	acpigen_write_scope_end(); /* Scope */
 
-	/* Fill Bluetooth companion SAR related ACPI structures */
+	/* Fill Bluetooth companion SAR related ACPI structures and DSM functions. */
 	if (sar_loaded && is_dev_enabled(config->bluetooth_companion)) {
 		const char *path = acpi_device_path(config->bluetooth_companion);
 		if (path) {	/* Bluetooth device under USB Hub scope or PCIe root port */
@@ -1226,6 +1309,17 @@ static void wifi_ssdt_write_properties(const struct device *dev, const char *sco
 			sar_emit_bdmm(sar_limits.bdmm);
 			sar_emit_ebrd(sar_limits.ebrd);
 			sar_emit_dsbr(sar_limits.dsbr, DOMAIN_TYPE_BLUETOOTH);
+
+			if (config->bluetooth_companion->path.type == DEVICE_PATH_PCI &&
+			    config->bluetooth_companion->vendor == PCI_VID_INTEL) {
+				struct dsm_uuid bt_dsm_ids = {
+					.uuid = ACPI_DSM_RFIM_WIFI_UUID,
+					.callbacks = bluetooth_dsm_callbacks,
+					.count = ARRAY_SIZE(bluetooth_dsm_callbacks)
+				};
+				acpigen_write_dsm_uuid_arr(&bt_dsm_ids, 1);
+			}
+
 			acpigen_write_scope_end();
 		} else {
 			printk(BIOS_ERR, "Failed to get %s Bluetooth companion ACPI path\n",

From 2207a4b59ae120348f60328b085a0a006646e58c Mon Sep 17 00:00:00 2001
From: Jeremy Compostella <jeremy.compostella@intel.com>
Date: Tue, 10 Jun 2025 14:03:37 -0700
Subject: [PATCH 1375/3886] vc/intel/fsp/fsp2_0/pantherlake: Add TDC current
 limit configuration

This commit exposes the Thermal Design Current (TDC) limit in the
FSP_M_CONFIG structure. The TDC Current Limit is defined in 1/8A
increments. This allows for more precise control over the thermal design
current settings, enhancing power management capabilities.

Change-Id: Ie35611d5cdc14114542ac1a61611aa333c4bb1c9
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88037
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Zhixing Ma <zhixing.ma@intel.com>
---
 .../intel/fsp/fsp2_0/pantherlake/FspmUpd.h    | 63 ++++++++++---------
 1 file changed, 33 insertions(+), 30 deletions(-)

diff --git a/src/vendorcode/intel/fsp/fsp2_0/pantherlake/FspmUpd.h b/src/vendorcode/intel/fsp/fsp2_0/pantherlake/FspmUpd.h
index c5b16d6dce..2e420cbec8 100644
--- a/src/vendorcode/intel/fsp/fsp2_0/pantherlake/FspmUpd.h
+++ b/src/vendorcode/intel/fsp/fsp2_0/pantherlake/FspmUpd.h
@@ -2323,9 +2323,12 @@ typedef struct {
 **/
   UINT16                      PsysPmax;
 
-/** Offset 0x0872 - Reserved
+/** Offset 0x0872 - Thermal Design Current current limit
+  TDC Current Limit, defined in 1/8A increments. Range 0-32767. For a TDC Current
+  Limit of 125A, enter 1000. 0 = 0 Amps. <b>0: Auto</b>. [0] for IA, [1] for GT,
+  [2] for SA, [3] for atom, [4]-[5] are Reserved.
 **/
-  UINT8                      Reserved66[12];
+  UINT16                      TdcCurrentLimit[6];
 
 /** Offset 0x087E - AcLoadline
   AC Loadline defined in 1/100 mOhms. A value of 100 = 1.00 mOhm, and 1255 = 12.55
@@ -2343,7 +2346,7 @@ typedef struct {
 
 /** Offset 0x0896 - Reserved
 **/
-  UINT8                      Reserved67[116];
+  UINT8                      Reserved66[116];
 
 /** Offset 0x090A - Thermal Design Current enable/disable
   Thermal Design Current enable/disable; <b>0: Disable</b>; 1: Enable. [0] for IA,
@@ -2353,7 +2356,7 @@ typedef struct {
 
 /** Offset 0x0910 - Reserved
 **/
-  UINT8                       Reserved68[6];
+  UINT8                       Reserved67[6];
 
 /** Offset 0x0916 - Disable Fast Slew Rate for Deep Package C States for VR domains
   This option needs to be configured to reduce acoustic noise during deeper C states.
@@ -2375,7 +2378,7 @@ typedef struct {
 
 /** Offset 0x0922 - Reserved
 **/
-  UINT8                       Reserved69[6];
+  UINT8                       Reserved68[6];
 
 /** Offset 0x0928 - Thermal Design Current time window
   Auto = 0 is default. Range is from 1ms to 448s. <b>0: Auto</b>. [0] for IA, [1]
@@ -2385,7 +2388,7 @@ typedef struct {
 
 /** Offset 0x0940 - Reserved
 **/
-  UINT8                       Reserved70[8];
+  UINT8                       Reserved69[8];
 
 /** Offset 0x0948 - DLVR RFI Enable
   Enable/Disable DLVR RFI frequency hopping. 0: Disable; <b>1: Enable</b>.
@@ -2395,7 +2398,7 @@ typedef struct {
 
 /** Offset 0x0949 - Reserved
 **/
-  UINT8                       Reserved71[13];
+  UINT8                       Reserved70[13];
 
 /** Offset 0x0956 - VR Fast Vmode ICC Limit support
   Voltage Regulator Fast Vmode ICC Limit. A value of 400 = 100A. A value of 0 corresponds
@@ -2420,7 +2423,7 @@ typedef struct {
 
 /** Offset 0x096E - Reserved
 **/
-  UINT8                       Reserved72[28];
+  UINT8                       Reserved71[28];
 
 /** Offset 0x098A - PCH Port80 Route
   Control where the Port 80h cycles are sent, 0: LPC; 1: PCI.
@@ -2437,7 +2440,7 @@ typedef struct {
 
 /** Offset 0x098C - Reserved
 **/
-  UINT8                       Reserved73[4];
+  UINT8                       Reserved72[4];
 
 /** Offset 0x0990 - PMR Size
   Size of PMR memory buffer. 0x400000 for normal boot and 0x200000 for S3 boot
@@ -2463,7 +2466,7 @@ typedef struct {
 
 /** Offset 0x0997 - Reserved
 **/
-  UINT8                       Reserved74;
+  UINT8                       Reserved73;
 
 /** Offset 0x0998 - Base addresses for VT-d function MMIO access
   Base addresses for VT-d MMIO access per VT-d engine
@@ -2472,7 +2475,7 @@ typedef struct {
 
 /** Offset 0x09BC - Reserved
 **/
-  UINT8                       Reserved75[20];
+  UINT8                       Reserved74[20];
 
 /** Offset 0x09D0 - MMIO Size
   Size of MMIO space reserved for devices. 0(Default)=Auto, non-Zero=size in MB
@@ -2487,7 +2490,7 @@ typedef struct {
 
 /** Offset 0x09D4 - Reserved
 **/
-  UINT8                      Reserved76[36];
+  UINT8                      Reserved75[36];
 
 /** Offset 0x09F8 - Enable above 4GB MMIO resource support
   Enable/disable above 4GB MMIO resource support
@@ -2503,7 +2506,7 @@ typedef struct {
 
 /** Offset 0x09FA - Reserved
 **/
-  UINT8                       Reserved77[10];
+  UINT8                       Reserved76[10];
 
 /** Offset 0x0A04 - Enable/Disable CrashLog Device
   Enable or Disable CrashLog/Telemetry Device  0- Disable, <b>1- Enable</b>
@@ -2513,7 +2516,7 @@ typedef struct {
 
 /** Offset 0x0A08 - Reserved
 **/
-  UINT8                      Reserved78[20];
+  UINT8                      Reserved77[20];
 
 /** Offset 0x0A1C - Platform Debug Option
   Enabled Trace active: TraceHub is enabled and trace is active, blocks s0ix.\n
@@ -2530,7 +2533,7 @@ typedef struct {
 
 /** Offset 0x0A1D - Reserved
 **/
-  UINT8                       Reserved79[14];
+  UINT8                       Reserved78[14];
 
 /** Offset 0x0A2B - Program GPIOs for LFP on DDI port-A device
   0=Disabled,1(Default)=eDP, 2=MIPI DSI
@@ -2540,7 +2543,7 @@ typedef struct {
 
 /** Offset 0x0A2C - Reserved
 **/
-  UINT8                      Reserved80[2];
+  UINT8                      Reserved79[2];
 
 /** Offset 0x0A2E - Program GPIOs for LFP on DDI port-B device
   0(Default)=Disabled,1=eDP, 2=MIPI DSI
@@ -2634,7 +2637,7 @@ typedef struct {
 
 /** Offset 0x0A3D - Reserved
 **/
-  UINT8                       Reserved81[3];
+  UINT8                       Reserved80[3];
 
 /** Offset 0x0A40 - Temporary MMIO address for GMADR
   The reference code will use this as Temporary MMIO address space to access GMADR
@@ -2653,7 +2656,7 @@ typedef struct {
 
 /** Offset 0x0A50 - Reserved
 **/
-  UINT8                      Reserved82[2];
+  UINT8                      Reserved81[2];
 
 /** Offset 0x0A52 - Enable/Disable Memory Bandwidth Compression
   0=Disable, 1(Default)=Enable
@@ -2683,7 +2686,7 @@ typedef struct {
 
 /** Offset 0x0A56 - Reserved
 **/
-  UINT8                       Reserved83[2];
+  UINT8                       Reserved82[2];
 
 /** Offset 0x0A58 - Intel Graphics VBT (Video BIOS Table) Size
   Size of Internal Graphics VBT Image
@@ -2692,7 +2695,7 @@ typedef struct {
 
 /** Offset 0x0A5C - Reserved
 **/
-  UINT8                       Reserved84[4];
+  UINT8                       Reserved83[4];
 
 /** Offset 0x0A60 - Graphics Configuration Ptr
   Points to VBT
@@ -2720,7 +2723,7 @@ typedef struct {
 
 /** Offset 0x0A72 - Reserved
 **/
-  UINT8                      Reserved85[16];
+  UINT8                      Reserved84[16];
 
 /** Offset 0x0A82 - TCSS USB HOST (xHCI) Enable
   Set TCSS XHCI. 0:Disabled  1:Enabled - Must be enabled if xDCI is enabled below
@@ -2730,7 +2733,7 @@ typedef struct {
 
 /** Offset 0x0A83 - Reserved
 **/
-  UINT8                       Reserved86[4];
+  UINT8                       Reserved85[4];
 
 /** Offset 0x0A87 - TCSS Type C Port 0
   Set TCSS Type C Port 0 Type, Options are 0=DISABLE, 1=DP_ONLY, 2=NO_TBT, 3=NO_PCIE,
@@ -2762,7 +2765,7 @@ typedef struct {
 
 /** Offset 0x0A8B - Reserved
 **/
-  UINT8                       Reserved87;
+  UINT8                       Reserved86;
 
 /** Offset 0x0A8C - TypeC port GPIO setting
   GPIO Pin number for Type C Aux orientation setting, use the GpioPad that is defined
@@ -2830,7 +2833,7 @@ typedef struct {
 
 /** Offset 0x0AC9 - Reserved
 **/
-  UINT8                       Reserved88;
+  UINT8                       Reserved87;
 
 /** Offset 0x0ACA - DLL Weak Lock Support
   Enables/Disable DLL Weak Lock Support
@@ -2840,7 +2843,7 @@ typedef struct {
 
 /** Offset 0x0ACB - Reserved
 **/
-  UINT8                       Reserved89;
+  UINT8                       Reserved88;
 
 /** Offset 0x0ACC - Rx DQS Delay Comp Support
   Enables/Disable Rx DQS Delay Comp Support
@@ -2850,7 +2853,7 @@ typedef struct {
 
 /** Offset 0x0ACD - Reserved
 **/
-  UINT8                       Reserved90[2];
+  UINT8                       Reserved89[2];
 
 /** Offset 0x0ACF - Mrc Failure On Unsupported Dimm
   Enables/Disable Mrc Failure On Unsupported Dimm
@@ -2860,7 +2863,7 @@ typedef struct {
 
 /** Offset 0x0AD0 - Reserved
 **/
-  UINT8                      Reserved91[4];
+  UINT8                      Reserved90[4];
 
 /** Offset 0x0AD4 - DynamicMemoryBoost
   Enable/Disable Dynamic Memory Boost Feature. Only valid if SpdProfileSelected is
@@ -2878,7 +2881,7 @@ typedef struct {
 
 /** Offset 0x0ADC - Reserved
 **/
-  UINT8                      Reserved92[9];
+  UINT8                      Reserved91[9];
 
 /** Offset 0x0AE5 - Vref Offset
   Offset to be applied to DDRDATACH0_CR_DDRCRDATAOFFSETTRAIN.VrefOffset
@@ -2889,7 +2892,7 @@ typedef struct {
 
 /** Offset 0x0AE6 - Reserved
 **/
-  UINT8                       Reserved93[2];
+  UINT8                       Reserved92[2];
 
 /** Offset 0x0AE8 - tRRSG Delta
   Delay between Read-to-Read commands in the same Bank Group. 0 - Auto. Signed TAT
@@ -3005,7 +3008,7 @@ typedef struct {
 
 /** Offset 0x0AF8 - Reserved
 **/
-  UINT8                       Reserved94[112];
+  UINT8                       Reserved93[112];
 } FSP_M_CONFIG;
 
 /** Fsp M UPD Configuration

From 5a2de49baa761d0d2bdc5ac446d1db1fbc92ec39 Mon Sep 17 00:00:00 2001
From: Jeremy Compostella <jeremy.compostella@intel.com>
Date: Tue, 10 Jun 2025 13:18:52 -0700
Subject: [PATCH 1376/3886] soc/intel/cmn/blk/power_limit: Add helper functions
 to romstage

This commit makes power limit helper functions accessible during
romstage by updating the Makefile to include `power_limit.c` for both
ramstage and romstage.

It also modifies a preprocessor directive to ensure
`variant_update_cpu_power_limits()` is not compiled in romstage as it is
only intended for late-in-the-boot usage and will not compile properly
in romstage.

This change enables power management configuration identification early
in the boot process, allowing for better control over power settings at
this stage.

TEST=Successfully compile the Fatcat board target.

Change-Id: Ibf4d85c71dd8963063ca014d151438b68ea918db
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88038
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/soc/intel/common/block/power_limit/Makefile.mk   | 1 +
 src/soc/intel/common/block/power_limit/power_limit.c | 2 +-
 2 files changed, 2 insertions(+), 1 deletion(-)

diff --git a/src/soc/intel/common/block/power_limit/Makefile.mk b/src/soc/intel/common/block/power_limit/Makefile.mk
index 8211eb7a4f..8168bd942c 100644
--- a/src/soc/intel/common/block/power_limit/Makefile.mk
+++ b/src/soc/intel/common/block/power_limit/Makefile.mk
@@ -1,2 +1,3 @@
 ## SPDX-License-Identifier: GPL-2.0-only
 ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_POWER_LIMIT) += power_limit.c
+romstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_POWER_LIMIT) += power_limit.c
diff --git a/src/soc/intel/common/block/power_limit/power_limit.c b/src/soc/intel/common/block/power_limit/power_limit.c
index 16917835cd..4758f09f82 100644
--- a/src/soc/intel/common/block/power_limit/power_limit.c
+++ b/src/soc/intel/common/block/power_limit/power_limit.c
@@ -243,7 +243,7 @@ u8 get_cpu_tdp(void)
 
 WEAK_DEV_PTR(dptf_policy);
 
-#if CONFIG(SOC_INTEL_COMMON_BLOCK_VARIANT_POWER_LIMIT)
+#if ENV_RAMSTAGE && CONFIG(SOC_INTEL_COMMON_BLOCK_VARIANT_POWER_LIMIT)
 void variant_update_cpu_power_limits(const struct cpu_tdp_power_limits *limits,
 		size_t num_entries)
 {

From 59fce656b1906c43d3144445afcdf6f1a29aaed4 Mon Sep 17 00:00:00 2001
From: Jeremy Compostella <jeremy.compostella@intel.com>
Date: Tue, 10 Jun 2025 13:27:20 -0700
Subject: [PATCH 1377/3886] soc/intel/pantherlake: Enable Thermal Design
 Current for various SKUs

This commit introduces the configuration and enabling of Thermal Design
Current (TDC) settings for various Panther Lake (PTL) SKUs. TDC values
are essential for managing thermal constraints, specifying the maximum
allowable current for specific Voltage Regulator (VR) domains under
given power limit scenarios. This enhancement provides tailored power
management for different SKUs, extracted from the Power Map Document
(#813278) which the Firmware Support Package (FSP) is not aligned with.

It introduces a new enum `soc_intel_pantherlake_sku` to represent
various SKUs as the current `soc_intel_pantherlake_power_limits` does
not meet the need for TDC settings. `cpuid_to_ptl` is updated to include
SKU mapping.

The VR romstage FSP params function implements logic to read SKU
information based on PCI device ID and CPU TDP, ensuring accurate
configuration.

TEST=FSP logs confirm TDC enablement at the specified values on a Fatcat
     device operating an H12Xe Panther Lake SoC.

Change-Id: I889d5f08b0c75b950e5a30d25d6a370cccd295aa
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88039
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/soc/intel/pantherlake/chip.h              | 41 +++++++++++++++----
 src/soc/intel/pantherlake/chipset_ptl.cb      | 18 +++++++-
 .../intel/pantherlake/romstage/fsp_params.c   | 31 ++++++++++++++
 3 files changed, 82 insertions(+), 8 deletions(-)

diff --git a/src/soc/intel/pantherlake/chip.h b/src/soc/intel/pantherlake/chip.h
index 47a20fe7d8..94c91a8e1c 100644
--- a/src/soc/intel/pantherlake/chip.h
+++ b/src/soc/intel/pantherlake/chip.h
@@ -68,18 +68,28 @@ enum soc_intel_pantherlake_cpu_tdps {
 	TDP_45W = 45,
 };
 
+enum soc_intel_pantherlake_sku {
+	PTL_H404_SKU,
+	PTL_H12XE_SKU,
+	PTL_H484_SKU,
+	PTL_H4XE_SKU,
+	PTL_H204_SKU,
+	MAX_PTL_SKUS
+};
+
 /* Mapping of different SKUs based on CPU ID and TDP values */
-static const struct {
+static const struct soc_intel_pantherlake_power_map {
 	unsigned int cpu_id;
 	enum soc_intel_pantherlake_power_limits limits;
 	enum soc_intel_pantherlake_cpu_tdps cpu_tdp;
+	enum soc_intel_pantherlake_sku sku;
 } cpuid_to_ptl[] = {
-	{ PCI_DID_INTEL_PTL_U_ID_1, PTL_U_1_CORE, TDP_15W },
-	{ PCI_DID_INTEL_PTL_U_ID_2, PTL_U_2_CORE, TDP_15W },
-	{ PCI_DID_INTEL_PTL_H_ID_1, PTL_H_1_CORE, TDP_25W },
-	{ PCI_DID_INTEL_PTL_H_ID_2, PTL_H_1_CORE, TDP_25W },
-	{ PCI_DID_INTEL_PTL_H_ID_3, PTL_H_2_CORE, TDP_25W },
-	{ PCI_DID_INTEL_PTL_H_ID_4, PTL_H_2_CORE, TDP_25W },
+	{ PCI_DID_INTEL_PTL_U_ID_1, PTL_U_1_CORE, TDP_15W, PTL_H404_SKU },
+	{ PCI_DID_INTEL_PTL_U_ID_2, PTL_U_2_CORE, TDP_15W, PTL_H204_SKU },
+	{ PCI_DID_INTEL_PTL_H_ID_1, PTL_H_1_CORE, TDP_25W, PTL_H12XE_SKU },
+	{ PCI_DID_INTEL_PTL_H_ID_2, PTL_H_1_CORE, TDP_25W, PTL_H484_SKU },
+	{ PCI_DID_INTEL_PTL_H_ID_3, PTL_H_2_CORE, TDP_25W, PTL_H12XE_SKU },
+	{ PCI_DID_INTEL_PTL_H_ID_4, PTL_H_2_CORE, TDP_25W, PTL_H12XE_SKU },
 };
 
 /* Types of display ports */
@@ -361,6 +371,23 @@ struct soc_intel_pantherlake_config {
 	 */
 	uint16_t ps_cur_3_threshold[NUM_VR_DOMAINS];
 
+	/*
+	 * Thermal Design Current (TDC) settings for various SKUs.
+	 *
+	 * This multidimensional array stores the Thermal Design Current (TDC)
+	 * values for different power limit configurations across multiple SKUs
+	 * and Voltage Regulator (VR) domains. TDC values indicate the maximum
+	 * allowable current for a given thermal configuration, which helps in
+	 * managing thermal constraints for each VR domain under specific power
+	 * limit scenarios.
+	 *
+	 * Each entry in the array is indexed by SKU and VR domain, providing
+	 * tailored TDC values for specific power management requirements.
+	 *
+	 * The TDC unit is defined 1/8A increments.
+	 */
+	uint16_t thermal_design_current[MAX_PTL_SKUS][NUM_VR_DOMAINS];
+
 	/*
 	 * SerialIO device mode selection:
 	 * PchSerialIoDisabled,
diff --git a/src/soc/intel/pantherlake/chipset_ptl.cb b/src/soc/intel/pantherlake/chipset_ptl.cb
index 838fdfa30a..1b81b739bb 100644
--- a/src/soc/intel/pantherlake/chipset_ptl.cb
+++ b/src/soc/intel/pantherlake/chipset_ptl.cb
@@ -9,6 +9,10 @@ chip soc/intel/pantherlake
 		.tdp_pl4 = 163,
 		.tdp_pl4_fastvmode = 150,
 	}"
+	register "thermal_design_current[PTL_H404_SKU]" = "{
+		[VR_DOMAIN_IA] = 34 * 8,
+		[VR_DOMAIN_GT] = 23 * 8
+	}"
 
 	# H204
 	register "power_limits_config[PTL_U_2_CORE]" = "{
@@ -17,6 +21,10 @@ chip soc/intel/pantherlake
 		.tdp_pl4 = 105,
 		.tdp_pl4_fastvmode = 95,
 	}"
+	register "thermal_design_current[PTL_H204_SKU]" = "{
+		[VR_DOMAIN_IA] = 23 * 8,
+		[VR_DOMAIN_GT] = 23 * 8
+	}"
 
 	# H12Xe and H484
 	register "power_limits_config[PTL_H_1_CORE]" = "{
@@ -25,8 +33,16 @@ chip soc/intel/pantherlake
 		.tdp_pl4 = 175,
 		.tdp_pl4_fastvmode = 160,
 	}"
+	register "thermal_design_current[PTL_H12XE_SKU]" = "{
+		[VR_DOMAIN_IA] = 39 * 8,
+		[VR_DOMAIN_GT] = 44 * 8
+	}"
+	register "thermal_design_current[PTL_H484_SKU]" = "{
+		[VR_DOMAIN_IA] = 39 * 8,
+		[VR_DOMAIN_GT] = 23 * 8
+	}"
 
-	# H444
+	# H4XE
 	register "power_limits_config[PTL_H_2_CORE]" = "{
 		.tdp_pl1_override = 25,
 		.tdp_pl2_override = 64,
diff --git a/src/soc/intel/pantherlake/romstage/fsp_params.c b/src/soc/intel/pantherlake/romstage/fsp_params.c
index 44875679ca..bcdda8ed55 100644
--- a/src/soc/intel/pantherlake/romstage/fsp_params.c
+++ b/src/soc/intel/pantherlake/romstage/fsp_params.c
@@ -3,6 +3,7 @@
 #include <cpu/intel/common/common.h>
 #include <cpu/x86/msr.h>
 #include <cpu/x86/mtrr.h>
+#include <device/pci.h>
 #include <elog.h>
 #include <fsp/debug.h>
 #include <fsp/fsp_debug_event.h>
@@ -303,6 +304,25 @@ static void fill_fspm_thermal_params(FSP_M_CONFIG *m_cfg,
 	m_cfg->TccActivationOffset = config->tcc_offset;
 }
 
+static const struct soc_intel_pantherlake_power_map *get_map(const struct soc_intel_pantherlake_config *config)
+{
+	uint16_t sa_pci_id = pci_read_config16(PCI_DEVFN_ROOT, PCI_DEVICE_ID);
+	if (sa_pci_id == 0xffff) {
+		printk(BIOS_WARNING, "Unknown SA PCI Device!\n");
+		return NULL;
+	}
+
+	uint8_t tdp = get_cpu_tdp();
+	for (size_t i = 0; i < ARRAY_SIZE(cpuid_to_ptl); i++) {
+		const struct soc_intel_pantherlake_power_map *current = &cpuid_to_ptl[i];
+		if (current->cpu_id == sa_pci_id && current->cpu_tdp == tdp)
+			return current;
+	}
+
+	printk(BIOS_ERR, "Could not find the SKU power map\n");
+	return NULL;
+}
+
 static void fill_fspm_vr_config_params(FSP_M_CONFIG *m_cfg,
 				       const struct soc_intel_pantherlake_config *config)
 {
@@ -315,6 +335,17 @@ static void fill_fspm_vr_config_params(FSP_M_CONFIG *m_cfg,
 			}
 		}
 	}
+
+	const struct soc_intel_pantherlake_power_map *map = get_map(config);
+	if (!map)
+		return;
+
+	for (size_t i = 0; i < ARRAY_SIZE(config->thermal_design_current[0]); i++) {
+		if (!config->thermal_design_current[map->sku][i])
+			continue;
+		m_cfg->TdcEnable[i] = 1;
+		m_cfg->TdcCurrentLimit[i] = config->thermal_design_current[map->sku][i];
+	}
 }
 
 #if CONFIG(PLATFORM_HAS_EARLY_LOW_BATTERY_INDICATOR)

From 57bffed89357b6af563e8514e25e8605a99c5b85 Mon Sep 17 00:00:00 2001
From: Jamie Ryu <jamie.m.ryu@intel.com>
Date: Tue, 17 Jun 2025 13:08:32 -0700
Subject: [PATCH 1378/3886] soc/intel/pantherlake: Add new PCI and CPU IDs

This commit adds the relevant IDs to support new Panther Lake (PTL)
System on Chips (SoCs). The CPU profiles are aligned with the matching
definition from Panther Lake Firmware Support Package (FSP) revision
3144.01.

TEST=A Fatcat device with CPUID 0xc06c1 and MCH_ID 0xb003 booted with
     the relevant information printed in corebot logs.
     [DEBUG]  CPU: ID c06c1, Pantherlake B0, ucode: 00000105
     [DEBUG]  MCH: device id b003 (rev 06) is Pantherlake U
     [DEBUG]  PCH: device id e401 (rev 01) is Pantherlake SOC-H SuperSKU
     [DEBUG]  IGD: device id b090 (rev 00) is Pantherlake-U GT2

Change-Id: I66efe51a94edfffc2546817d06a63a9c4b51aa81
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com>
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88130
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Bora Guvendik <bora.guvendik@intel.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Cliff Huang <cliff.huang@intel.com>
---
 src/include/cpu/intel/cpu_ids.h                       | 2 ++
 src/include/device/pci_ids.h                          | 6 ++++++
 src/soc/intel/common/block/cpu/mp_init.c              | 2 ++
 src/soc/intel/common/block/graphics/graphics.c        | 1 +
 src/soc/intel/common/block/systemagent/systemagent.c  | 5 +++++
 src/soc/intel/pantherlake/bootblock/report_platform.c | 8 ++++++++
 src/soc/intel/pantherlake/chip.h                      | 5 +++++
 7 files changed, 29 insertions(+)

diff --git a/src/include/cpu/intel/cpu_ids.h b/src/include/cpu/intel/cpu_ids.h
index 59900077d9..70e5b7b0c3 100644
--- a/src/include/cpu/intel/cpu_ids.h
+++ b/src/include/cpu/intel/cpu_ids.h
@@ -87,6 +87,8 @@
 #define CPUID_LUNARLAKE_A0_2		0xb06d1
 #define CPUID_ARROWLAKE_H_A0		0xc0652
 #define CPUID_PANTHERLAKE_A0		0xc06c0
+#define CPUID_PANTHERLAKE_B0_1		0xc06c1
+#define CPUID_PANTHERLAKE_B0_2		0xc06c2
 #define CPUID_SNOWRIDGE_A0		0x80660
 #define CPUID_SNOWRIDGE_A1		0x80661
 #define CPUID_SNOWRIDGE_A2		0x80662
diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h
index 85de6a5cfb..93d2e81e61 100644
--- a/src/include/device/pci_ids.h
+++ b/src/include/device/pci_ids.h
@@ -4401,6 +4401,7 @@
 #define PCI_DID_INTEL_PTL_H_GT2_1			0xb080
 #define PCI_DID_INTEL_PTL_H_GT2_2			0xb0a0
 #define PCI_DID_INTEL_PTL_H_GT2_3			0xb0b0
+#define PCI_DID_INTEL_PTL_H_GT2_4			0xb08f
 #define PCI_DID_INTEL_WCL_GT2_1				0xfd80
 #define PCI_DID_INTEL_WCL_GT2_2				0xfd81
 
@@ -4557,10 +4558,15 @@
 #define PCI_DID_INTEL_LNL_M_ID_1		0x6410
 #define PCI_DID_INTEL_PTL_U_ID_1		0xb000
 #define PCI_DID_INTEL_PTL_U_ID_2		0xb003
+#define PCI_DID_INTEL_PTL_U_ID_3		0xb01a
 #define PCI_DID_INTEL_PTL_H_ID_1		0xb001
 #define PCI_DID_INTEL_PTL_H_ID_2		0xb002
 #define PCI_DID_INTEL_PTL_H_ID_3		0xb004
 #define PCI_DID_INTEL_PTL_H_ID_4		0xb00a
+#define PCI_DID_INTEL_PTL_H_ID_5		0xb00b
+#define PCI_DID_INTEL_PTL_H_ID_6		0xb00c
+#define PCI_DID_INTEL_PTL_H_ID_7		0xb005
+#define PCI_DID_INTEL_PTL_H_ID_8		0xb009
 #define PCI_DID_INTEL_SNR_ID			0x09a2
 #define PCI_DID_INTEL_WCL_ID_1			0xfd00
 #define PCI_DID_INTEL_WCL_ID_2			0xfd01
diff --git a/src/soc/intel/common/block/cpu/mp_init.c b/src/soc/intel/common/block/cpu/mp_init.c
index 16b77b0352..638aa07f29 100644
--- a/src/soc/intel/common/block/cpu/mp_init.c
+++ b/src/soc/intel/common/block/cpu/mp_init.c
@@ -34,6 +34,8 @@ static struct device_operations cpu_dev_ops = {
 static const struct cpu_device_id cpu_table[] = {
 	{ X86_VENDOR_INTEL, CPUID_WILDCATLAKE_A0, CPUID_EXACT_MATCH_MASK },
 	{ X86_VENDOR_INTEL, CPUID_PANTHERLAKE_A0, CPUID_EXACT_MATCH_MASK },
+	{ X86_VENDOR_INTEL, CPUID_PANTHERLAKE_B0_1, CPUID_EXACT_MATCH_MASK },
+	{ X86_VENDOR_INTEL, CPUID_PANTHERLAKE_B0_2, CPUID_EXACT_MATCH_MASK },
 	{ X86_VENDOR_INTEL, CPUID_LUNARLAKE_A0_1, CPUID_EXACT_MATCH_MASK },
 	{ X86_VENDOR_INTEL, CPUID_LUNARLAKE_A0_2, CPUID_EXACT_MATCH_MASK },
 	{ X86_VENDOR_INTEL, CPUID_METEORLAKE_A0_1, CPUID_EXACT_MATCH_MASK },
diff --git a/src/soc/intel/common/block/graphics/graphics.c b/src/soc/intel/common/block/graphics/graphics.c
index 165727ef0e..9666c49f96 100644
--- a/src/soc/intel/common/block/graphics/graphics.c
+++ b/src/soc/intel/common/block/graphics/graphics.c
@@ -348,6 +348,7 @@ static const unsigned short pci_device_ids[] = {
 	PCI_DID_INTEL_PTL_H_GT2_1,
 	PCI_DID_INTEL_PTL_H_GT2_2,
 	PCI_DID_INTEL_PTL_H_GT2_3,
+	PCI_DID_INTEL_PTL_H_GT2_4,
 	PCI_DID_INTEL_LNL_M_GT2,
 	PCI_DID_INTEL_RPL_U_GT1,
 	PCI_DID_INTEL_RPL_U_GT2,
diff --git a/src/soc/intel/common/block/systemagent/systemagent.c b/src/soc/intel/common/block/systemagent/systemagent.c
index 8b623fc9e7..f98606a18d 100644
--- a/src/soc/intel/common/block/systemagent/systemagent.c
+++ b/src/soc/intel/common/block/systemagent/systemagent.c
@@ -429,10 +429,15 @@ static const unsigned short systemagent_ids[] = {
 	PCI_DID_INTEL_WCL_ID_2,
 	PCI_DID_INTEL_PTL_U_ID_1,
 	PCI_DID_INTEL_PTL_U_ID_2,
+	PCI_DID_INTEL_PTL_U_ID_3,
 	PCI_DID_INTEL_PTL_H_ID_1,
 	PCI_DID_INTEL_PTL_H_ID_2,
 	PCI_DID_INTEL_PTL_H_ID_3,
 	PCI_DID_INTEL_PTL_H_ID_4,
+	PCI_DID_INTEL_PTL_H_ID_5,
+	PCI_DID_INTEL_PTL_H_ID_6,
+	PCI_DID_INTEL_PTL_H_ID_7,
+	PCI_DID_INTEL_PTL_H_ID_8,
 	PCI_DID_INTEL_LNL_M_ID,
 	PCI_DID_INTEL_LNL_M_ID_1,
 	PCI_DID_INTEL_MTL_M_ID,
diff --git a/src/soc/intel/pantherlake/bootblock/report_platform.c b/src/soc/intel/pantherlake/bootblock/report_platform.c
index 0cca50669b..099075417e 100644
--- a/src/soc/intel/pantherlake/bootblock/report_platform.c
+++ b/src/soc/intel/pantherlake/bootblock/report_platform.c
@@ -21,6 +21,8 @@ static struct {
 	const char *name;
 } cpu_table[] = {
 	{ CPUID_PANTHERLAKE_A0, "Pantherlake A0" },
+	{ CPUID_PANTHERLAKE_B0_1, "Pantherlake B0" },
+	{ CPUID_PANTHERLAKE_B0_2, "Pantherlake B0" },
 };
 
 static struct {
@@ -29,10 +31,15 @@ static struct {
 } mch_table[] = {
 	{ PCI_DID_INTEL_PTL_U_ID_1, "Pantherlake U" },
 	{ PCI_DID_INTEL_PTL_U_ID_2, "Pantherlake U" },
+	{ PCI_DID_INTEL_PTL_U_ID_3, "Pantherlake U" },
 	{ PCI_DID_INTEL_PTL_H_ID_1, "Pantherlake H" },
 	{ PCI_DID_INTEL_PTL_H_ID_2, "Pantherlake H" },
 	{ PCI_DID_INTEL_PTL_H_ID_3, "Pantherlake H" },
 	{ PCI_DID_INTEL_PTL_H_ID_4, "Pantherlake H" },
+	{ PCI_DID_INTEL_PTL_H_ID_5, "Pantherlake H" },
+	{ PCI_DID_INTEL_PTL_H_ID_6, "Pantherlake H" },
+	{ PCI_DID_INTEL_PTL_H_ID_7, "Pantherlake H" },
+	{ PCI_DID_INTEL_PTL_H_ID_8, "Pantherlake H" },
 	{ PCI_DID_INTEL_WCL_ID_1, "Wildcatlake" },
 	{ PCI_DID_INTEL_WCL_ID_2, "Wildcatlake" },
 };
@@ -147,6 +154,7 @@ static struct {
 	{ PCI_DID_INTEL_PTL_H_GT2_1, "Pantherlake-H GT2" },
 	{ PCI_DID_INTEL_PTL_H_GT2_2, "Pantherlake-H GT2" },
 	{ PCI_DID_INTEL_PTL_H_GT2_3, "Pantherlake-H GT2" },
+	{ PCI_DID_INTEL_PTL_H_GT2_4, "Pantherlake-H GT2" },
 	{ PCI_DID_INTEL_WCL_GT2_1, "Wildcatlake GT2" },
 	{ PCI_DID_INTEL_WCL_GT2_2, "Wildcatlake GT2" },
 };
diff --git a/src/soc/intel/pantherlake/chip.h b/src/soc/intel/pantherlake/chip.h
index 94c91a8e1c..92f561d6bf 100644
--- a/src/soc/intel/pantherlake/chip.h
+++ b/src/soc/intel/pantherlake/chip.h
@@ -86,10 +86,15 @@ static const struct soc_intel_pantherlake_power_map {
 } cpuid_to_ptl[] = {
 	{ PCI_DID_INTEL_PTL_U_ID_1, PTL_U_1_CORE, TDP_15W, PTL_H404_SKU },
 	{ PCI_DID_INTEL_PTL_U_ID_2, PTL_U_2_CORE, TDP_15W, PTL_H204_SKU },
+	{ PCI_DID_INTEL_PTL_U_ID_3, PTL_U_2_CORE, TDP_15W, PTL_H404_SKU },
 	{ PCI_DID_INTEL_PTL_H_ID_1, PTL_H_1_CORE, TDP_25W, PTL_H12XE_SKU },
 	{ PCI_DID_INTEL_PTL_H_ID_2, PTL_H_1_CORE, TDP_25W, PTL_H484_SKU },
 	{ PCI_DID_INTEL_PTL_H_ID_3, PTL_H_2_CORE, TDP_25W, PTL_H12XE_SKU },
 	{ PCI_DID_INTEL_PTL_H_ID_4, PTL_H_2_CORE, TDP_25W, PTL_H12XE_SKU },
+	{ PCI_DID_INTEL_PTL_H_ID_5, PTL_H_2_CORE, TDP_25W, PTL_H4XE_SKU },
+	{ PCI_DID_INTEL_PTL_H_ID_6, PTL_H_2_CORE, TDP_25W, PTL_H4XE_SKU },
+	{ PCI_DID_INTEL_PTL_H_ID_7, PTL_H_2_CORE, TDP_25W, PTL_H4XE_SKU },
+	{ PCI_DID_INTEL_PTL_H_ID_8, PTL_H_2_CORE, TDP_25W, PTL_H12XE_SKU },
 };
 
 /* Types of display ports */

From abbf549558ba6b423b603442208d17208362fdf7 Mon Sep 17 00:00:00 2001
From: Jeremy Compostella <jeremy.compostella@intel.com>
Date: Tue, 17 Jun 2025 13:13:28 -0700
Subject: [PATCH 1379/3886] mb/google/fatcat: Add support for new Panther Lake
 IDs

This commit introduces support for additional Intel Panther Lake CPU IDs
in the `power_optimized_limits` structure, enhancing compatibility with
newer hardware. It also introduces macros for common power limit values,
streamlining the code and reducing repetition.

Change-Id: I6d7c24441ce6ed78c366f18627c237a2f4984cd5
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88131
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 .../variants/baseboard/fatcat/ramstage.c      | 80 ++++++++++++-------
 1 file changed, 50 insertions(+), 30 deletions(-)

diff --git a/src/mainboard/google/fatcat/variants/baseboard/fatcat/ramstage.c b/src/mainboard/google/fatcat/variants/baseboard/fatcat/ramstage.c
index 84111619ad..f83d9bdd48 100644
--- a/src/mainboard/google/fatcat/variants/baseboard/fatcat/ramstage.c
+++ b/src/mainboard/google/fatcat/variants/baseboard/fatcat/ramstage.c
@@ -7,66 +7,86 @@
  * SKU_ID, TDP (Watts), pl1_min (milliWatts), pl1_max (milliWatts),
  * pl2_min (milliWatts), pl2_max (milliWatts), pl4 (milliWatts)
  */
+/* Define a macro for the common power limit values for PTL_H */
+#define COMMON_PTL_H_POWER_LIMITS	\
+	.pl1_min_power = 10000,		\
+	.pl1_max_power = 25000,		\
+	.pl2_min_power = 50000,		\
+	.pl2_max_power = 50000,		\
+	.pl4_power = 65000
+/* Define a macro for the common power limit values for PTL_U */
+#define COMMON_PTL_U_POWER_LIMITS	\
+	.pl1_min_power = 10000,		\
+	.pl1_max_power = 15000,		\
+	.pl2_min_power = 50000,		\
+	.pl2_max_power = 50000,		\
+	.pl4_power = 65000
 const struct cpu_tdp_power_limits power_optimized_limits[] = {
 	{
 		.mch_id = PCI_DID_INTEL_PTL_H_ID_1,
 		.cpu_tdp = TDP_25W,
 		.power_limits_index = PTL_H_1_CORE,
-		.pl1_min_power = 10000,
-		.pl1_max_power = 25000,
-		.pl2_min_power = 50000,
-		.pl2_max_power = 50000,
-		.pl4_power = 65000
+		COMMON_PTL_H_POWER_LIMITS
 	},
 	{
 		.mch_id = PCI_DID_INTEL_PTL_H_ID_2,
 		.cpu_tdp = TDP_25W,
 		.power_limits_index = PTL_H_1_CORE,
-		.pl1_min_power = 10000,
-		.pl1_max_power = 25000,
-		.pl2_min_power = 50000,
-		.pl2_max_power = 50000,
-		.pl4_power = 65000
+		COMMON_PTL_H_POWER_LIMITS
 	},
 	{
 		.mch_id = PCI_DID_INTEL_PTL_H_ID_3,
 		.cpu_tdp = TDP_25W,
 		.power_limits_index = PTL_H_2_CORE,
-		.pl1_min_power = 10000,
-		.pl1_max_power = 25000,
-		.pl2_min_power = 50000,
-		.pl2_max_power = 50000,
-		.pl4_power = 65000
+		COMMON_PTL_H_POWER_LIMITS
 	},
 	{
 		.mch_id = PCI_DID_INTEL_PTL_H_ID_4,
 		.cpu_tdp = TDP_25W,
 		.power_limits_index = PTL_H_2_CORE,
-		.pl1_min_power = 10000,
-		.pl1_max_power = 25000,
-		.pl2_min_power = 50000,
-		.pl2_max_power = 50000,
-		.pl4_power = 65000
+		COMMON_PTL_H_POWER_LIMITS
+	},
+	{
+		.mch_id = PCI_DID_INTEL_PTL_H_ID_5,
+		.cpu_tdp = TDP_25W,
+		.power_limits_index = PTL_H_2_CORE,
+		COMMON_PTL_H_POWER_LIMITS
+	},
+	{
+		.mch_id = PCI_DID_INTEL_PTL_H_ID_6,
+		.cpu_tdp = TDP_25W,
+		.power_limits_index = PTL_H_2_CORE,
+		COMMON_PTL_H_POWER_LIMITS
+	},
+	{
+		.mch_id = PCI_DID_INTEL_PTL_H_ID_7,
+		.cpu_tdp = TDP_25W,
+		.power_limits_index = PTL_H_2_CORE,
+		COMMON_PTL_H_POWER_LIMITS
+	},
+	{
+		.mch_id = PCI_DID_INTEL_PTL_H_ID_8,
+		.cpu_tdp = TDP_25W,
+		.power_limits_index = PTL_H_2_CORE,
+		COMMON_PTL_H_POWER_LIMITS
 	},
 	{
 		.mch_id = PCI_DID_INTEL_PTL_U_ID_1,
 		.cpu_tdp = TDP_15W,
 		.power_limits_index = PTL_U_1_CORE,
-		.pl1_min_power = 10000,
-		.pl1_max_power = 15000,
-		.pl2_min_power = 50000,
-		.pl2_max_power = 50000,
-		.pl4_power = 65000
+		COMMON_PTL_U_POWER_LIMITS
 	},
 	{
 		.mch_id = PCI_DID_INTEL_PTL_U_ID_2,
 		.cpu_tdp = TDP_15W,
 		.power_limits_index = PTL_U_2_CORE,
-		.pl1_min_power = 10000,
-		.pl1_max_power = 15000,
-		.pl2_min_power = 50000,
-		.pl2_max_power = 50000,
-		.pl4_power = 65000
+		COMMON_PTL_U_POWER_LIMITS
+	},
+	{
+		.mch_id = PCI_DID_INTEL_PTL_U_ID_3,
+		.cpu_tdp = TDP_15W,
+		.power_limits_index = PTL_U_2_CORE,
+		COMMON_PTL_U_POWER_LIMITS
 	},
 };
 

From e58883aaceae3527510a9773cc635aa5c1c08d66 Mon Sep 17 00:00:00 2001
From: Jeremy Compostella <jeremy.compostella@intel.com>
Date: Tue, 10 Jun 2025 16:36:30 -0700
Subject: [PATCH 1380/3886] soc/intel/pantherlake: Refactor VR Fast Vmode
 I_TRIP threshold settings

A need arose to perform power and performance analysis on various SoC
SKUs with Fast VMode enabled, which the current chipset data structure
does not allow.

This commit refactors the configuration of Fast VMode I_TRIP thresholds
for Voltage Regulator (VR) domains across different power limit
configurations in Pantherlake SoCs. Previously, the I_TRIP threshold
values were statically set for each VR domain, but now they are defined
within a two-dimensional array that considers various power limit
scenarios.

This commit adds the I_TRIP values for different Power Limit SKUs
currently operated on Fatcat devices.

As part of this commit, the following two changes are being undone
because the previous code structure is now incompatible and lacks
purpose:

- commit 4b765fdd9886 ("mb/google/fatcat: Disable EnableFastVmode on
  Panther Lake H SoC")

- commit 5d7e2b4c0cf0 ("mb/google/fatcat: Disable VR settings on Panther
  Lake H SoC")

Change-Id: Iff21a9b0b230e08b99e032400cbe0021b8a4af43
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88042
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
---
 src/mainboard/google/fatcat/romstage.c        | 49 -------------------
 .../variants/baseboard/fatcat/devicetree.cb   | 29 +++++++----
 src/soc/intel/pantherlake/chip.h              | 13 ++++-
 .../intel/pantherlake/romstage/fsp_params.c   | 20 ++++----
 4 files changed, 40 insertions(+), 71 deletions(-)

diff --git a/src/mainboard/google/fatcat/romstage.c b/src/mainboard/google/fatcat/romstage.c
index 7a509384b2..8f0000c2ce 100644
--- a/src/mainboard/google/fatcat/romstage.c
+++ b/src/mainboard/google/fatcat/romstage.c
@@ -1,7 +1,6 @@
 /* SPDX-License-Identifier: GPL-2.0-or-later */
 
 #include <baseboard/variants.h>
-#include <device/pci_ops.h>
 #include <fsp/api.h>
 #include <soc/romstage.h>
 #include <soc/soc_chip.h>
@@ -23,51 +22,6 @@ __weak void variant_update_soc_memory_init_params(FSPM_UPD *memupd)
 	/* Nothing to do */
 }
 
-static bool soc_is_pantherlake_h(void)
-{
-	uint16_t mch_id = pci_s_read_config16(PCI_DEV(0, 0, 0), PCI_DEVICE_ID);
-
-	if (mch_id == 0xffff) {
-		printk(BIOS_ERR, "No matching PCI DID present\n");
-		return false;
-	}
-
-	/*
-	 * Identify Panther Lake H by testing all Memory Controller Hub (MCH) IDs utilized on fatcat
-	 * devices.
-	 */
-	switch (mch_id) {
-	case PCI_DID_INTEL_PTL_H_ID_1:
-	case PCI_DID_INTEL_PTL_H_ID_2:
-	case PCI_DID_INTEL_PTL_H_ID_3:
-	case PCI_DID_INTEL_PTL_H_ID_4:
-		return true;
-	default:
-		return false;
-	}
-}
-
-static void disable_vr_settings_on_pantherlake_h(FSP_M_CONFIG *m_cfg)
-{
-	if (!soc_is_pantherlake_h())
-		return;
-
-	/*
-	 * The board operates a Panther Lake H SoC; disable the PTL-U VR settings.
-	 *
-	 * The Voltage Regulator (VR) configurations supplied by the device tree are
-	 * specifically adjusted for a Panther Lake U SoC, which is intended for fatcat board
-	 * designs. When these settings are applied to a board equipped with a Panther Lake H
-	 * SoC, it may experience performance problems under high-stress conditions. This is
-	 * because the I_TRIP value is set lower than the device's actual capability.
-	 */
-	printk(BIOS_INFO, "Disabling VR settings on PTL-H.\n");
-	for (size_t i = 0; i < NUM_VR_DOMAINS; i++) {
-		m_cfg->CepEnable[i] = false;
-		m_cfg->EnableFastVmode[i] = false;
-	}
-}
-
 void mainboard_memory_init_params(FSPM_UPD *memupd)
 {
 	const struct pad_config *pads;
@@ -86,9 +40,6 @@ void mainboard_memory_init_params(FSPM_UPD *memupd)
 
 	memcfg_init(memupd, mem_config, &spd_info, half_populated);
 
-	/* Override FSP-M Voltage Regulator settings on Panther Lake H. */
-	disable_vr_settings_on_pantherlake_h(&memupd->FspmConfig);
-
 	/* Override FSP-M UPD per board if required. */
 	variant_update_soc_memory_init_params(memupd);
 }
diff --git a/src/mainboard/google/fatcat/variants/baseboard/fatcat/devicetree.cb b/src/mainboard/google/fatcat/variants/baseboard/fatcat/devicetree.cb
index 6f04713ae3..00b4ea4506 100644
--- a/src/mainboard/google/fatcat/variants/baseboard/fatcat/devicetree.cb
+++ b/src/mainboard/google/fatcat/variants/baseboard/fatcat/devicetree.cb
@@ -62,22 +62,31 @@ chip soc/intel/pantherlake
 	# Enable Energy Reporting
 	register "pch_pm_energy_report_enable" = "true"
 
-	# As per document 813278, the Intel PTL-U 15W SoC supports
-	# Fast V-Mode (FVM) on cores (IA), Graphics (GT), and System
-	# Agent (SA). The ICC Limit is represented in 1/4 A
-	# increments, i.e., a value of 400 = 100A.
-	# IA VR configuration
+	# As per document 813278, the following PTL SoC supports Fast
+	# V-Mode (FVM) on cores (IA), Graphics (GT), and System Agent
+	# (SA). The ICC Limit is represented in 1/4 A increments,
+	# i.e., a value of 400 = 100A.
 	register "enable_fast_vmode[VR_DOMAIN_IA]" = "true"
 	register "cep_enable[VR_DOMAIN_IA]" = "true"
-	register "fast_vmode_i_trip[VR_DOMAIN_IA]" = "252" # 63A
-	# GT VR configuration
 	register "enable_fast_vmode[VR_DOMAIN_GT]" = "true"
 	register "cep_enable[VR_DOMAIN_GT]" = "true"
-	register "fast_vmode_i_trip[VR_DOMAIN_GT]" = "152" # 38A
-	# SA VR configuration
 	register "enable_fast_vmode[VR_DOMAIN_SA]" = "true"
 	register "cep_enable[VR_DOMAIN_SA]" = "true"
-	register "fast_vmode_i_trip[VR_DOMAIN_SA]" = "152" # 38A
+	register "fast_vmode_i_trip[PTL_U_1_CORE]" = "{
+		[VR_DOMAIN_IA] = 63 * 4,
+		[VR_DOMAIN_GT] = 38 * 4,
+		[VR_DOMAIN_SA] = 38 * 4
+	}"
+	register "fast_vmode_i_trip[PTL_U_2_CORE]" = "{
+		[VR_DOMAIN_IA] = 38 * 4,
+		[VR_DOMAIN_GT] = 38 * 4,
+		[VR_DOMAIN_SA] = 38 * 4
+	}"
+	register "fast_vmode_i_trip[PTL_H_1_CORE]" = "{
+		[VR_DOMAIN_IA] = 75 * 4,
+		[VR_DOMAIN_GT] = 75 * 4,
+		[VR_DOMAIN_SA] = 38 * 4
+	}"
 
 	# Enable CNVi BT
 	register "cnvi_bt_core" = "true"
diff --git a/src/soc/intel/pantherlake/chip.h b/src/soc/intel/pantherlake/chip.h
index 92f561d6bf..53168ff662 100644
--- a/src/soc/intel/pantherlake/chip.h
+++ b/src/soc/intel/pantherlake/chip.h
@@ -345,12 +345,21 @@ struct soc_intel_pantherlake_config {
 	bool cep_enable[NUM_VR_DOMAINS];
 
 	/*
-	 * VR Fast Vmode I_TRIP threshold.
+	 * Fast Vmode I_TRIP Thresholds for VR Domains
+	 *
+	 * This two-dimensional array represents the Fast Vmode I_TRIP thresholds
+	 * for various Voltage Regulator (VR) domains across different power limit
+	 * configurations in Panther Lake SoCs.
+	 *
+	 * The Fast Vmode I_TRIP threshold is used to override the default current
+	 * threshold settings, ensuring optimal power management by adapting to
+	 * specific VR domain requirements under different power limit scenarios.
+	 *
 	 * 0-255A in 1/4 A units. Example: 400 = 100A
 	 * This setting overrides the default value set by FSPs when Fast VMode
 	 * is enabled.
 	 */
-	uint16_t fast_vmode_i_trip[NUM_VR_DOMAINS];
+	uint16_t fast_vmode_i_trip[PTL_POWER_LIMITS_COUNT][NUM_VR_DOMAINS];
 
 	/*
 	 * Power state current threshold 1.
diff --git a/src/soc/intel/pantherlake/romstage/fsp_params.c b/src/soc/intel/pantherlake/romstage/fsp_params.c
index bcdda8ed55..13401eb125 100644
--- a/src/soc/intel/pantherlake/romstage/fsp_params.c
+++ b/src/soc/intel/pantherlake/romstage/fsp_params.c
@@ -326,20 +326,20 @@ static const struct soc_intel_pantherlake_power_map *get_map(const struct soc_in
 static void fill_fspm_vr_config_params(FSP_M_CONFIG *m_cfg,
 				       const struct soc_intel_pantherlake_config *config)
 {
-	for (size_t i = 0; i < ARRAY_SIZE(config->enable_fast_vmode); i++) {
-		if (config->cep_enable[i]) {
-			m_cfg->CepEnable[i] = config->cep_enable[i];
-			if (config->enable_fast_vmode[i]) {
-				m_cfg->EnableFastVmode[i] = config->enable_fast_vmode[i];
-				m_cfg->IccLimit[i] = config->fast_vmode_i_trip[i];
-			}
-		}
-	}
-
 	const struct soc_intel_pantherlake_power_map *map = get_map(config);
 	if (!map)
 		return;
 
+	for (size_t i = 0; i < ARRAY_SIZE(config->enable_fast_vmode); i++) {
+		if (!config->cep_enable[i])
+			continue;
+		m_cfg->CepEnable[i] = config->cep_enable[i];
+		if (config->enable_fast_vmode[i]) {
+			m_cfg->EnableFastVmode[i] = config->enable_fast_vmode[i];
+			m_cfg->IccLimit[i] = config->fast_vmode_i_trip[map->limits][i];
+		}
+	}
+
 	for (size_t i = 0; i < ARRAY_SIZE(config->thermal_design_current[0]); i++) {
 		if (!config->thermal_design_current[map->sku][i])
 			continue;

From cae47dfd44d845aa1ebe840a5655a6318f7f8bce Mon Sep 17 00:00:00 2001
From: Cliff Huang <cliff.huang@intel.com>
Date: Tue, 17 Jun 2025 16:04:45 -0700
Subject: [PATCH 1381/3886] soc/intel/pantherlake: Correct DRHC and SATC in
 DMAR table
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

This commit addresses an issue within the DMAR (DMA Remapping) table
configuration for Intel Panther Lake (PTL) SoC. Specifically, it
introduces telemetry support to the DRHC structure. In addition, the
unnecessary Dynamic Platform and Thermal Framework (DPTF) entry is
removed from the SATC structure, aligning with the BIOS Requirements.
For detailed specifications, refer to the 812562 PTL Firmware
Architecture Specification (FAS).

BUG=b:423943431
TEST=Boot Fatcat board to ALOS. Disassemble the DMAR table using 2023+
version of iasl and check the DMAR for the telemetry entry in the DRHC
structure. There should not be a DPTF entry in the SATC structure.

Signed-off-by: Cliff Huang <cliff.huang@intel.com>
Change-Id: I289f2520e4449a6aa33f53040b6c8f66faa4f2d7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88136
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/soc/intel/pantherlake/acpi.c | 11 ++++++-----
 1 file changed, 6 insertions(+), 5 deletions(-)

diff --git a/src/soc/intel/pantherlake/acpi.c b/src/soc/intel/pantherlake/acpi.c
index 0252e1c503..bf769d952a 100644
--- a/src/soc/intel/pantherlake/acpi.c
+++ b/src/soc/intel/pantherlake/acpi.c
@@ -253,6 +253,7 @@ static unsigned long soc_fill_dmar(unsigned long current)
 	bool is_dptf_enabled = is_devfn_enabled(PCI_DEVFN_DPTF);
 	bool is_npu_enabled = is_devfn_enabled(PCI_DEVFN_NPU);
 	bool is_iaa_enabled = is_devfn_enabled(PCI_DEVFN_IAA);
+	bool is_telemetry_enabled = is_devfn_enabled(PCI_DEVFN_TELEMETRY);
 
 	printk(BIOS_DEBUG, "%s - gfxvtbar:0x%llx  0x%x\n", __func__, gfxvtbar, MCHBAR32(GFXVTBAR));
 	if (vtd_engine_enabled & GFXVT_ENABLED) {
@@ -263,8 +264,8 @@ static unsigned long soc_fill_dmar(unsigned long current)
 		acpi_dmar_drhd_fixup(tmp, current);
 	}
 
-	if ((is_ipu_enabled || is_dptf_enabled || is_npu_enabled || is_iaa_enabled) &&
-		(vtd_engine_enabled & NONGFXVT_ENABLED)) {
+	if ((is_ipu_enabled || is_dptf_enabled || is_telemetry_enabled || is_npu_enabled ||
+		is_iaa_enabled) && (vtd_engine_enabled & NONGFXVT_ENABLED)) {
 		const unsigned long tmp = current;
 		current += acpi_create_dmar_drhd(current,
 			0, 0, (uint64_t)VTVC0_BASE_ADDRESS, VTVC0_BASE_SIZE);
@@ -272,6 +273,8 @@ static unsigned long soc_fill_dmar(unsigned long current)
 			current += acpi_create_dmar_ds_pci(current, 0, PCI_DEV_SLOT_IPU, 0);
 		if (is_dptf_enabled)
 			current += acpi_create_dmar_ds_pci(current, 0, PCI_DEV_SLOT_DPTF, 0);
+		if (is_telemetry_enabled)
+			current += acpi_create_dmar_ds_pci(current, 0, PCI_DEV_SLOT_TELEMETRY, 0);
 		if (is_npu_enabled)
 			current += acpi_create_dmar_ds_pci(current, 0, PCI_DEV_SLOT_NPU, 0);
 		if (is_iaa_enabled)
@@ -302,12 +305,10 @@ static unsigned long soc_fill_dmar(unsigned long current)
 		acpi_dmar_rmrr_fixup(tmp, current);
 	}
 
-	if (is_ipu_enabled || is_dptf_enabled || is_npu_enabled || is_iaa_enabled) {
+	if (is_ipu_enabled || is_npu_enabled || is_iaa_enabled) {
 		const unsigned long tmp = current;
 		current += acpi_create_dmar_satc(current, ATC_REQUIRED, 0);
 			current += acpi_create_dmar_ds_pci(current, 0, PCI_DEV_SLOT_IGD, 0);
-		if (is_dptf_enabled)
-			current += acpi_create_dmar_ds_pci(current, 0, PCI_DEV_SLOT_DPTF, 0);
 		if (is_ipu_enabled)
 			current += acpi_create_dmar_ds_pci(current, 0, PCI_DEV_SLOT_IPU, 0);
 		if (is_npu_enabled)

From ea3cc3231c0b74afd03b74a49a7f2a13eba0bc21 Mon Sep 17 00:00:00 2001
From: Jeremy Compostella <jeremy.compostella@intel.com>
Date: Tue, 17 Jun 2025 13:15:20 -0700
Subject: [PATCH 1382/3886] mb/intel/ptlrvp: Remove power limit constraints

This commit eliminates the power limit constraints initially adopted
from the Fatcat board's codebase. These constraints are tailored for
factory-specific scenarios, which are irrelevant to the Intel Panther
Lake RVP (PTLRVP) board's use case.

Change-Id: I3e4dfe85a2677ad3998fd6c0f9a59fa966587c59
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88132
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 .../variants/baseboard/ptlrvp/Makefile.mk     |  1 -
 .../variants/baseboard/ptlrvp/ramstage.c      | 62 -------------------
 2 files changed, 63 deletions(-)
 delete mode 100644 src/mainboard/intel/ptlrvp/variants/baseboard/ptlrvp/ramstage.c

diff --git a/src/mainboard/intel/ptlrvp/variants/baseboard/ptlrvp/Makefile.mk b/src/mainboard/intel/ptlrvp/variants/baseboard/ptlrvp/Makefile.mk
index ff6ed05ded..be05cd4e5c 100644
--- a/src/mainboard/intel/ptlrvp/variants/baseboard/ptlrvp/Makefile.mk
+++ b/src/mainboard/intel/ptlrvp/variants/baseboard/ptlrvp/Makefile.mk
@@ -1,4 +1,3 @@
 ## SPDX-License-Identifier: GPL-2.0-only
 
 romstage-y += memory.c
-ramstage-$(CONFIG_EC_GOOGLE_CHROMEEC) += ramstage.c
diff --git a/src/mainboard/intel/ptlrvp/variants/baseboard/ptlrvp/ramstage.c b/src/mainboard/intel/ptlrvp/variants/baseboard/ptlrvp/ramstage.c
deleted file mode 100644
index 6c7668fa4b..0000000000
--- a/src/mainboard/intel/ptlrvp/variants/baseboard/ptlrvp/ramstage.c
+++ /dev/null
@@ -1,62 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-or-later */
-
-#include <baseboard/variants.h>
-#include <ec/google/chromeec/ec.h>
-
-/*
- * SKU_ID, TDP (Watts), pl1_min (milliWatts), pl1_max (milliWatts),
- * pl2_min (milliWatts), pl2_max (milliWatts), pl4 (milliWatts)
- */
-const struct cpu_tdp_power_limits power_optimized_limits[] = {
-	{
-		.mch_id = PCI_DID_INTEL_PTL_H_ID_1,
-		.cpu_tdp = TDP_25W,
-		.power_limits_index = PTL_H_1_CORE,
-		.pl1_min_power = 10000,
-		.pl1_max_power = 25000,
-		.pl2_min_power = 50000,
-		.pl2_max_power = 50000,
-		.pl4_power = 65000
-	},
-	{
-		.mch_id = PCI_DID_INTEL_PTL_H_ID_2,
-		.cpu_tdp = TDP_25W,
-		.power_limits_index = PTL_H_1_CORE,
-		.pl1_min_power = 10000,
-		.pl1_max_power = 25000,
-		.pl2_min_power = 50000,
-		.pl2_max_power = 50000,
-		.pl4_power = 65000
-	},
-	{
-		.mch_id = PCI_DID_INTEL_PTL_H_ID_3,
-		.cpu_tdp = TDP_25W,
-		.power_limits_index = PTL_H_2_CORE,
-		.pl1_min_power = 10000,
-		.pl1_max_power = 25000,
-		.pl2_min_power = 50000,
-		.pl2_max_power = 50000,
-		.pl4_power = 65000
-	},
-	{
-		.mch_id = PCI_DID_INTEL_PTL_H_ID_4,
-		.cpu_tdp = TDP_25W,
-		.power_limits_index = PTL_H_2_CORE,
-		.pl1_min_power = 10000,
-		.pl1_max_power = 25000,
-		.pl2_min_power = 50000,
-		.pl2_max_power = 50000,
-		.pl4_power = 65000
-	},
-};
-
-void baseboard_devtree_update(void)
-{
-	/* Don't optimize the power limit if booting with barrel attached */
-	if (CONFIG(BOARD_INTEL_MODEL_PTLRVP) && google_chromeec_is_barrel_charger_present())
-		return;
-
-	if (!google_chromeec_is_battery_present())
-		variant_update_cpu_power_limits(power_optimized_limits,
-						ARRAY_SIZE(power_optimized_limits));
-}

From 68ede7b8600038ac41d17ba1362280cb300e36a1 Mon Sep 17 00:00:00 2001
From: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com>
Date: Tue, 17 Jun 2025 16:58:01 +0900
Subject: [PATCH 1383/3886] mb/google/nissa/var/meliks: Configure Acoustic
 noise mitigation

Set slow_slew_rate for VCCIA and VCCGT to SLEW_FAST_8 to improve EE
noise for meliks.

BRANCH=nissa
TEST=built firmware and got pass for EE noise test.

Change-Id: Ie1a9147736e3effa465134854ecd34554bee6906
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88126
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Edward Doan <edoan@chromium.org>
---
 src/mainboard/google/brya/variants/meliks/overridetree.cb | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/src/mainboard/google/brya/variants/meliks/overridetree.cb b/src/mainboard/google/brya/variants/meliks/overridetree.cb
index 9595616aaf..057bc74309 100644
--- a/src/mainboard/google/brya/variants/meliks/overridetree.cb
+++ b/src/mainboard/google/brya/variants/meliks/overridetree.cb
@@ -7,6 +7,13 @@ chip soc/intel/alderlake
 
 	register "sagv" = "SaGv_Enabled"
 
+	# Acoustic settings
+	register "acoustic_noise_mitigation" = "1"
+	register "slow_slew_rate[VR_DOMAIN_IA]" = "SLEW_FAST_8"
+	register "slow_slew_rate[VR_DOMAIN_GT]" = "SLEW_FAST_8"
+	register "fast_pkg_c_ramp_disable[VR_DOMAIN_IA]" = "1"
+	register "fast_pkg_c_ramp_disable[VR_DOMAIN_GT]" = "1"
+
 	# SOC Aux orientation override:
 	# This is a bitfield that corresponds to up to 4 TCSS ports.
 	# Bits (0,1) allocated for TCSS Port1 configuration and Bits (2,3)for TCSS Port2.

From cf7159af64d8b7b322aa6183fff721c785624f22 Mon Sep 17 00:00:00 2001
From: Mario Scheithauer <mario.scheithauer@siemens.com>
Date: Mon, 16 Jun 2025 13:19:04 +0200
Subject: [PATCH 1384/3886] mb/siemens/mc_ehl3: Limit eMMC speed mode to DDR50

Due to layout restrictions on mc_ehl3, the eMMC interface is limited to
operate in DDR50 mode. The alternative modes SDR104 and SDR50 are not
supported. Limit the capabilities in the eMMC controller to DDR50 mode
only so that the eMMC driver in OS will choose the right mode for
operation even if the attached eMMC card supports higher modes.

BUG=none
TEST=Boot into Linux and check dmesg output for mmc modes

Change-Id: Id84d34e7abd4bf73648d453182345bc2e4676d62
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88110
Reviewed-by: Uwe Poeche <uwe.poeche@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
---
 src/mainboard/siemens/mc_ehl/variants/mc_ehl3/mainboard.c | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/src/mainboard/siemens/mc_ehl/variants/mc_ehl3/mainboard.c b/src/mainboard/siemens/mc_ehl/variants/mc_ehl3/mainboard.c
index c68ecdae0d..01349687b8 100644
--- a/src/mainboard/siemens/mc_ehl/variants/mc_ehl3/mainboard.c
+++ b/src/mainboard/siemens/mc_ehl/variants/mc_ehl3/mainboard.c
@@ -42,6 +42,13 @@ void variant_mainboard_final(void)
 					HOSTCTRL2_PRESET);
 		}
 	}
+
+	dev = pcidev_path_on_root(PCH_DEVFN_EMMC);
+	if (dev) {
+		struct resource *res = probe_resource(dev, PCI_BASE_ADDRESS_0);
+		if (res)
+			disable_sdr_modes(res);
+	}
 }
 
 static void finalize_boot(void *unused)

From 24d8e6f35e1d22b50602b202d16255115160f87e Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Micha=C5=82=20=C5=BBygowski?= <michal.zygowski@3mdeb.com>
Date: Wed, 30 Apr 2025 14:18:07 +0200
Subject: [PATCH 1385/3886] Revert "mb/google/brox: Handle GPI_INT pin lower to
 GPI_WAKE"
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

This partially reverts commit 32ebaef73c8e
("mb/google/brox: Handle GPI_INT pin lower to GPI_WAKE")
as google/brox board has moved away from the PAD_CFG_GPI_INT_SWAPPED
usage. The revert simply removes the PAD_CFG_GPI_INT_SWAPPED solution,
which is not used anywhere anymore.

PAD_CFG0_ROUTE_SWAPPED bit can not be found in any PCH datasheet nor
EDS. Furthermore, the definition conflicts with PAD_CFG0_NAFVWE_ENABLE
bit, which, on the contrary, is defined in the datasheets and PCH EDS.

The conflict results in boards printing:
"GPIO XX doesn't support APIC routing," (where XX is pad number)
for each pad having the NAFVWE bit set.

Currently, none of the boards use PAD_CFG0_ROUTE_SWAPPED bit, and due
to the bit field conflict I assume it was mistakenly added.

Change-Id: I71299c9729f294cfafaec02222ef01e96b575740
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87485
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
---
 src/soc/intel/common/block/gpio/gpio.c        |  6 ++----
 .../block/include/intelblocks/gpio_defs.h     | 21 -------------------
 2 files changed, 2 insertions(+), 25 deletions(-)

diff --git a/src/soc/intel/common/block/gpio/gpio.c b/src/soc/intel/common/block/gpio/gpio.c
index 625c3f4355..d74e01da62 100644
--- a/src/soc/intel/common/block/gpio/gpio.c
+++ b/src/soc/intel/common/block/gpio/gpio.c
@@ -294,8 +294,7 @@ static void gpio_configure_itss(const struct pad_config *cfg, uint16_t port,
 	 * in the GPIO pad configuration so that a hardware active low
 	 * signal looks that way to the APIC (double inversion).
 	 */
-	if (!(cfg->pad_config[0] & PAD_CFG0_ROUTE_SWAPPED) &&
-	    !(cfg->pad_config[0] & PAD_CFG0_ROUTE_IOAPIC))
+	if (!(cfg->pad_config[0] & PAD_CFG0_ROUTE_IOAPIC))
 		return;
 
 	irq = pcr_read32(port, PAD_CFG1_OFFSET(pad_cfg_offset));
@@ -306,8 +305,7 @@ static void gpio_configure_itss(const struct pad_config *cfg, uint16_t port,
 		return;
 	}
 
-	if (CONFIG(SOC_INTEL_COMMON_BLOCK_GPIO_ITSS_POL_CFG) &&
-	    !(cfg->pad_config[0] & PAD_CFG0_ROUTE_SWAPPED))
+	if (CONFIG(SOC_INTEL_COMMON_BLOCK_GPIO_ITSS_POL_CFG))
 		itss_set_irq_polarity(irq, !!(cfg->pad_config[0] &
 					      PAD_CFG0_RX_POL_INVERT));
 
diff --git a/src/soc/intel/common/block/include/intelblocks/gpio_defs.h b/src/soc/intel/common/block/include/intelblocks/gpio_defs.h
index bcf8e73f7e..411b1acca1 100644
--- a/src/soc/intel/common/block/include/intelblocks/gpio_defs.h
+++ b/src/soc/intel/common/block/include/intelblocks/gpio_defs.h
@@ -44,7 +44,6 @@
 #define  PAD_CFG0_ROUTE_SMI		(1 << 18)
 #define  PAD_CFG0_ROUTE_SCI		(1 << 19)
 #define  PAD_CFG0_ROUTE_IOAPIC		(1 << 20)
-#define  PAD_CFG0_ROUTE_SWAPPED		(1 << 27)
 #define PAD_CFG0_RXTENCFG_MASK		(3 << 21)
 #define PAD_CFG0_RXINV_MASK		(1 << 23)
 #define  PAD_CFG0_RX_POL_INVERT		(1 << 23)
@@ -337,26 +336,12 @@
 		PAD_TRIG(trig) | PAD_RX_POL(NONE) | PAD_BUF(TX_DISABLE),	\
 		PAD_PULL(pull) | PAD_CFG_OWN_GPIO(own))
 
-#define PAD_CFG_GPI_TRIG_OWN_SWAPPED(pad, pull, rst, trig, own)				\
-	_PAD_CFG_STRUCT(pad,							\
-		PAD_FUNC(GPIO) | PAD_RESET(rst) |				\
-		PAD_TRIG(trig) | PAD_RX_POL(NONE) | PAD_BUF(TX_DISABLE) |	\
-		PAD_IRQ_ROUTE(SWAPPED),	\
-		PAD_PULL(pull) | PAD_CFG_OWN_GPIO(own))
-
 #define PAD_CFG_GPI_TRIG_OWN_LOCK(pad, pull, rst, trig, own, lock_action)	\
 	_PAD_CFG_STRUCT_LOCK(pad,						\
 		PAD_FUNC(GPIO) | PAD_RESET(rst) |				\
 		PAD_TRIG(trig) | PAD_RX_POL(NONE) | PAD_BUF(TX_DISABLE),	\
 		PAD_PULL(pull) | PAD_CFG_OWN_GPIO(own), PAD_LOCK(lock_action))
 
-#define PAD_CFG_GPI_TRIG_OWN_LOCK_SWAPPED(pad, pull, rst, trig, own, lock_action)	\
-	_PAD_CFG_STRUCT_LOCK(pad,						\
-		PAD_FUNC(GPIO) | PAD_RESET(rst) |				\
-		PAD_TRIG(trig) | PAD_RX_POL(NONE) | PAD_BUF(TX_DISABLE) |	\
-		PAD_IRQ_ROUTE(SWAPPED),	\
-		PAD_PULL(pull) | PAD_CFG_OWN_GPIO(own), PAD_LOCK(lock_action))
-
 #define PAD_CFG_GPI_GPIO_DRIVER(pad, pull, rst)					\
 	_PAD_CFG_STRUCT(pad,							\
 		PAD_FUNC(GPIO) | PAD_RESET(rst) |				\
@@ -385,16 +370,10 @@
 #define PAD_CFG_GPI_INT(pad, pull, rst, trig)	\
 		PAD_CFG_GPI_TRIG_OWN(pad, pull, rst, trig, DRIVER)
 
-#define PAD_CFG_GPI_INT_SWAPPED(pad, pull, rst, trig)	\
-		PAD_CFG_GPI_TRIG_OWN_SWAPPED(pad, pull, rst, trig, DRIVER)
-
 /* GPIO Interrupt with lock */
 #define PAD_CFG_GPI_INT_LOCK(pad, pull, trig, lock_action)	\
 		PAD_CFG_GPI_TRIG_OWN_LOCK(pad, pull, PWROK, trig, DRIVER, lock_action)
 
-#define PAD_CFG_GPI_INT_LOCK_SWAPPED(pad, pull, trig, lock_action)	\
-		PAD_CFG_GPI_TRIG_OWN_LOCK_SWAPPED(pad, pull, PWROK, trig, DRIVER, lock_action)
-
 /* Bidirectional GPIO port when both RX and TX buffer is enabled */
 #define PAD_CFG_GPIO_BIDIRECT_IOS(pad, val, pull, rst, trig, iosstate, iosterm, own) \
 	_PAD_CFG_STRUCT(pad,						\

From c7fe47148242729ff87d8a3d6b3d17184d69fa67 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Micha=C5=82=20Kope=C4=87?= <michal.kopec@3mdeb.com>
Date: Tue, 11 Mar 2025 18:33:08 +0100
Subject: [PATCH 1386/3886] mb/novacustom/mtl-h/var/dgpu: Add NVIDIA dGPU ASL
 code
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Add ACPI ASL code for the discrete NVIDIA GN21 GPU. Based on
google/brya, but adapted for Meteor Lake and the specific GPU found in
Clevo V5x0TNx.

NVIDIA did not provide us with the required documentation, so this
driver is entirely based on the Brya implementation, and poking Clevo
ACPI from Linux.

Without this patch, the NVIDIA driver would not load at all under
Windows, while Ubuntu would load the driver, but would be unable to
power off the dGPU, causing increased power draw.

TEST=Boot to Windows 11 via MrChromebox uefipayload_2502 and observe
that the NVIDIA Driver loads correctly, that the dGPU powers off when
unused and powers on while needed. Do the same in Ubuntu 24.04 under a
Gnome X11 session.

Change-Id: I9e5715cb4129a005cc9374fd53eaacd7d1a7f68e
Signed-off-by: Michał Kopeć <michal.kopec@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86824
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com>
---
 .../novacustom/mtl-h/acpi/dgpu/gps.asl        |  96 ++++++
 .../novacustom/mtl-h/acpi/dgpu/gpu_defines.h  |  60 ++++
 .../novacustom/mtl-h/acpi/dgpu/gpu_ec.asl     |  11 +
 .../novacustom/mtl-h/acpi/dgpu/gpu_top.asl    |  92 +++++
 .../novacustom/mtl-h/acpi/dgpu/nbci.asl       |  27 ++
 .../novacustom/mtl-h/acpi/dgpu/nvjt.asl       | 128 +++++++
 .../novacustom/mtl-h/acpi/dgpu/nvop.asl       |  68 ++++
 .../novacustom/mtl-h/acpi/dgpu/peg.asl        |  99 ++++++
 .../novacustom/mtl-h/acpi/dgpu/power.asl      | 315 ++++++++++++++++++
 .../novacustom/mtl-h/acpi/dgpu/utility.asl    |  58 ++++
 src/mainboard/novacustom/mtl-h/dsdt.asl       |   4 +
 11 files changed, 958 insertions(+)
 create mode 100644 src/mainboard/novacustom/mtl-h/acpi/dgpu/gps.asl
 create mode 100644 src/mainboard/novacustom/mtl-h/acpi/dgpu/gpu_defines.h
 create mode 100644 src/mainboard/novacustom/mtl-h/acpi/dgpu/gpu_ec.asl
 create mode 100644 src/mainboard/novacustom/mtl-h/acpi/dgpu/gpu_top.asl
 create mode 100644 src/mainboard/novacustom/mtl-h/acpi/dgpu/nbci.asl
 create mode 100644 src/mainboard/novacustom/mtl-h/acpi/dgpu/nvjt.asl
 create mode 100644 src/mainboard/novacustom/mtl-h/acpi/dgpu/nvop.asl
 create mode 100644 src/mainboard/novacustom/mtl-h/acpi/dgpu/peg.asl
 create mode 100644 src/mainboard/novacustom/mtl-h/acpi/dgpu/power.asl
 create mode 100644 src/mainboard/novacustom/mtl-h/acpi/dgpu/utility.asl

diff --git a/src/mainboard/novacustom/mtl-h/acpi/dgpu/gps.asl b/src/mainboard/novacustom/mtl-h/acpi/dgpu/gps.asl
new file mode 100644
index 0000000000..8bf8954b82
--- /dev/null
+++ b/src/mainboard/novacustom/mtl-h/acpi/dgpu/gps.asl
@@ -0,0 +1,96 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#define GPS_FUNC_SUPPORT	0
+#define GPS_FUNC_GETCALLBACKS	0x13
+#define GPS_FUNC_PSHARESTATUS	0x20
+#define GPS_FUNC_PSHAREPARAMS	0x2a
+#define GPS_FUNC_REQUESTDXSTATE	0x12
+
+#define QUERY_GET_STATUS		0
+#define QUERY_GET_SUPPORTED_FIELDS	1
+#define QUERY_GET_CURRENT_LIMITS	2
+
+/* GPS return Package */
+Name (GPSP, Buffer (0x24) {0x0})
+CreateDWordField (GPSP, 0, RETN)
+CreateDWordField (GPSP, 4, VRV1)
+CreateDWordField (GPSP, 8, TGPU)
+
+/* GETCALLBACKS return value
+   [0]: Callback for post-mode set
+   [1]: Callback for pre-mode set
+   [2]: Callback for post power state transition */
+Name (GPSR, Buffer (4) { 0x4, 0x0, 0x0, 0x0 })
+
+Method (GPS, 2, Serialized)
+{
+	Switch (ToInteger (Arg0))
+	{
+		Case (GPS_FUNC_SUPPORT)
+		{
+			Return (LTOB(
+				(1 << GPS_FUNC_SUPPORT) |
+				(1 << GPS_FUNC_GETCALLBACKS) |
+				(1 << GPS_FUNC_PSHARESTATUS) |
+				(1 << GPS_FUNC_PSHAREPARAMS) |
+				(1 << GPS_FUNC_REQUESTDXSTATE)))
+		}
+		Case (GPS_FUNC_GETCALLBACKS)
+		{
+			CreateDWordField (Arg1, 0, QURY)
+
+			/* Driver querying for which callbacks the ACPI code
+			   wants callbacks for. */
+			If (QURY == 0)
+			{
+				Return (GPSR)
+			}
+
+			If (QURY & 0x4)
+			{
+				Printf("GPS: Kernel driver callback post power state transition")
+				Return (GPSR)
+			}
+		}
+		Case (GPS_FUNC_PSHARESTATUS)
+		{
+			Return (ITOB(0))
+		}
+		Case (GPS_FUNC_PSHAREPARAMS)
+		{
+			CreateField (Arg1, 0, 4, QUTY)	 /* Query type */
+
+			/* Version of return value */
+			VRV1 = 0x10000
+			RETN = QUTY
+
+			Switch (ToInteger (QUTY))
+			{
+				Case (QUERY_GET_STATUS)
+				{
+					Return (GPSP)
+				}
+				Case (QUERY_GET_SUPPORTED_FIELDS)
+				{
+					RETN = 0x300 | ToInteger (QUTY)
+					CreateDWordField (GPSP, 0x0C, PDTS)
+					PDTS = 0x03e8
+					Return (GPSP)
+				}
+				Case (QUERY_GET_CURRENT_LIMITS)
+				{
+					/* No limits */
+					Return (GPSP)
+				}
+			}
+		}
+		Case (GPS_FUNC_REQUESTDXSTATE)
+		{
+			Local0 = ToInteger(\_SB.PCI0.LPCB.EC0.GPUD)
+			\_SB.PCI0.RP12.PXSX.DNOT (Local0, 1)
+			Return (NV_ERROR_SUCCESS)
+		}
+	}
+
+	Return (NV_ERROR_UNSUPPORTED)
+}
diff --git a/src/mainboard/novacustom/mtl-h/acpi/dgpu/gpu_defines.h b/src/mainboard/novacustom/mtl-h/acpi/dgpu/gpu_defines.h
new file mode 100644
index 0000000000..1cb03145b0
--- /dev/null
+++ b/src/mainboard/novacustom/mtl-h/acpi/dgpu/gpu_defines.h
@@ -0,0 +1,60 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#define NV_ERROR_SUCCESS		0x0
+#define NV_ERROR_UNSPECIFIED		0x80000001
+#define NV_ERROR_UNSUPPORTED		0x80000002
+
+#define PCI_OWNER_SBIOS			0x0
+#define PCI_OWNER_DRIVER		0x1
+
+#define OPTIMUS_POWER_CONTROL_DISABLE	0x2
+#define OPTIMUS_POWER_CONTROL_ENABLE	0x3
+
+#define OPTIMUS_CONTROL_NO_RUN_PS0	0x0
+#define OPTIMUS_CONTROL_RUN_PS0		0x1
+
+#define GC6_STATE_EXITED		0x0
+#define GC6_STATE_ENTERED		0x1
+#define GC6_STATE_TRANSITION		0x2
+
+#define GC6_DEFER_DISABLE		0x0
+#define GC6_DEFER_ENABLE		0x1
+
+#define NOTIFY_GPS_EVENT_STATUS_CHANGE	0xc0
+#define NOTIFY_GPS_NVPCF_STATUS_CHANGE	0xc5
+#define NOTIFY_GPS_EVENT_LIMIT_POWER_0	0xd1
+#define NOTIFY_GPS_EVENT_LIMIT_POWER_1	0xd2
+#define NOTIFY_GPS_EVENT_LIMIT_POWER_2	0xd3
+#define NOTIFY_GPS_EVENT_LIMIT_POWER_3	0xd4
+#define NOTIFY_GPS_EVENT_LIMIT_POWER_4	0xd5
+
+/* Defines for NVJT subfunction */
+#define NVJT_GPC_GSS		0
+#define NVJT_GPC_EGNS		1
+#define NVJT_GPC_EGIS		2
+#define NVJT_GPS_XGXS		3
+#define NVJT_GPS_XGIS		4
+
+#define UUID_NVOP		"a486d8f8-0bda-471b-a72b-6042a6b5bee0"
+#define UUID_NVJT		"cbeca351-067b-4924-9cbd-b46b00b86f34"
+#define UUID_NBCI		"d4a50b75-65c7-46f7-bfb7-41514cea0244"
+#define UUID_NVPCF		"36b49710-2483-11e7-9598-0800200c9a66"
+#define UUID_GPS		"a3132d01-8cda-49ba-a52e-bc9d46df6b81"
+
+#define REVISION_MIN_NVOP	0x100
+#define REVISION_MIN_NVJT	0x100
+#define REVISION_MIN_NBCI	0x102
+#define REVISION_MIN_NVPCF	0x200
+#define REVISION_MIN_GPS	0x200
+
+#define D1_EC	0
+#define D2_EC	1
+#define D3_EC	2
+#define D4_EC	3
+#define D5_EC	4
+
+#define D1_GPU	0xD1
+#define D2_GPU	0xD2
+#define D3_GPU	0xD3
+#define D4_GPU	0xD4
+#define D5_GPU	0xD5
diff --git a/src/mainboard/novacustom/mtl-h/acpi/dgpu/gpu_ec.asl b/src/mainboard/novacustom/mtl-h/acpi/dgpu/gpu_ec.asl
new file mode 100644
index 0000000000..13b04294b6
--- /dev/null
+++ b/src/mainboard/novacustom/mtl-h/acpi/dgpu/gpu_ec.asl
@@ -0,0 +1,11 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+Scope (\_SB.PCI0.LPCB.EC0)
+{
+	/* EC has data for GPU in memmap */
+	Method (_QA0, 0, Serialized)
+	{
+		Local0 = ToInteger(GPUD)
+		\_SB.PCI0.RP12.PXSX.DNOT (Local0, 0)
+	}
+}
diff --git a/src/mainboard/novacustom/mtl-h/acpi/dgpu/gpu_top.asl b/src/mainboard/novacustom/mtl-h/acpi/dgpu/gpu_top.asl
new file mode 100644
index 0000000000..baee47dcca
--- /dev/null
+++ b/src/mainboard/novacustom/mtl-h/acpi/dgpu/gpu_top.asl
@@ -0,0 +1,92 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include "gpu_defines.h"
+
+Scope (\_SB.PCI0.RP12)
+{
+	#include "peg.asl"
+
+	Device (PXSX)
+	{
+		Name (_ADR, 0x0)
+		OperationRegion (PCIC, PCI_Config, 0x00, 0x100)
+		Field (PCIC, DWordAcc, NoLock, Preserve)
+		{
+			NVID,	16,
+			NDID,	16,
+			Offset (0x40),
+			NVSS,	32
+		}
+
+		#include "utility.asl"
+		#include "power.asl"
+		#include "nvop.asl"
+		#include "nvjt.asl"
+		#include "nbci.asl"
+		#include "gps.asl"
+		#include "gpu_ec.asl"
+
+		/* Convert D Notify from EC to GPU */
+		Method (CNVD, 1, NotSerialized)
+		{
+			Switch (ToInteger(Arg0)) {
+				Case (D1_EC) { Return (D1_GPU) }
+				Case (D2_EC) { Return (D2_GPU) }
+				Case (D3_EC) { Return (D3_GPU) }
+				Case (D4_EC) { Return (D4_GPU) }
+				Case (D5_EC) { Return (D5_GPU) }
+				Default { Return (D5_GPU) }
+			}
+		}
+
+		/* Current D Notify Value, defaults to D1
+		 * Arg0 == Shared value
+		 * Arg1 == force notification if no change (0 or 1)
+		 */
+		Name (CDNV, D1_EC)
+		Method (DNOT, 2, Serialized)
+		{
+			Printf ("EC: GPU D-Notify, %o", Arg0)
+			If ((Arg0 != CDNV) || (Arg1 == 1))
+			{
+				CDNV = Arg0
+				Local0 = CNVD (Arg0)
+				Notify (\_SB.PCI0.RP12.PXSX, Local0)
+			}
+		}
+
+		Method (_DSM, 4, Serialized)
+		{
+			If (Arg0 == ToUUID (UUID_NVOP))
+			{
+				If (ToInteger(Arg1) >= REVISION_MIN_NVOP)
+				{
+					Return (NVOP (Arg2, Arg3))
+				}
+			}
+			ElseIf (Arg0 == ToUUID (UUID_NVJT))
+			{
+				If (ToInteger (Arg1) >= REVISION_MIN_NVJT)
+				{
+					Return (NVJT (Arg2, Arg3))
+				}
+			}
+			ElseIf (Arg0 == ToUUID (UUID_NBCI))
+			{
+				If (ToInteger (Arg1) >= REVISION_MIN_NBCI)
+				{
+					Return (NBCI (Arg2, Arg3))
+				}
+			}
+			ElseIf (Arg0 == ToUUID (UUID_GPS))
+			{
+				If (ToInteger (Arg1) >= REVISION_MIN_GPS)
+				{
+					Return (GPS (Arg2, Arg3))
+				}
+			}
+
+			Return (NV_ERROR_UNSUPPORTED)
+		}
+	}
+}
diff --git a/src/mainboard/novacustom/mtl-h/acpi/dgpu/nbci.asl b/src/mainboard/novacustom/mtl-h/acpi/dgpu/nbci.asl
new file mode 100644
index 0000000000..1546928aef
--- /dev/null
+++ b/src/mainboard/novacustom/mtl-h/acpi/dgpu/nbci.asl
@@ -0,0 +1,27 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#define NBCI_FUNC_SUPPORT	0
+#define NBCI_FUNC_GETOBJBYTYPE	16
+#define NBCI_FUNC_GETCALLBACKS	19
+
+#define GPS_FUNC_GETCALLBACKS	0x13
+
+Method (NBCI, 2, Serialized)
+{
+	Switch (ToInteger (Arg0))
+	{
+		Case (NBCI_FUNC_SUPPORT)
+		{
+			Return (ITOB(
+				(1 << NBCI_FUNC_SUPPORT) |
+				(1 << NBCI_FUNC_GETCALLBACKS)))
+		}
+		Case (NBCI_FUNC_GETCALLBACKS)
+		{
+			/* Re-use the GPS subfunction's GETCALLBACKS Method */
+			Return (GPS (GPS_FUNC_GETCALLBACKS, Arg1))
+		}
+	}
+
+	Return (NV_ERROR_UNSUPPORTED)
+}
diff --git a/src/mainboard/novacustom/mtl-h/acpi/dgpu/nvjt.asl b/src/mainboard/novacustom/mtl-h/acpi/dgpu/nvjt.asl
new file mode 100644
index 0000000000..0526dc92a4
--- /dev/null
+++ b/src/mainboard/novacustom/mtl-h/acpi/dgpu/nvjt.asl
@@ -0,0 +1,128 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#define JT_FUNC_SUPPORT		0
+#define JT_FUNC_CAPS		1
+#define JT_FUNC_POWERCONTROL	3
+#define JT_FUNC_PLATPOLICY	4
+
+Method (NVJT, 2, Serialized)
+{
+	Switch (ToInteger(Arg0))
+	{
+		Case (JT_FUNC_SUPPORT)
+		{
+			Return (ITOB(
+				(1 << JT_FUNC_SUPPORT) |
+				(1 << JT_FUNC_CAPS) |
+				(1 << JT_FUNC_POWERCONTROL)))
+		}
+		Case (JT_FUNC_CAPS)
+		{
+			Return (ITOB(
+				(1 << 0) |		/* JTE: G-Sync NVSR Power Features Enabled */
+				(1 << 1) |		/* NVSE: NVSR Disabled */
+				(2 << 3) |		/* PPR: Panel Power Rail */
+				(0 << 5) |		/* SRPR: Self-Refresh Controller Power Rail */
+				(0 << 6) |		/* FBPR: FB Power Rail */
+				(0 << 8) |		/* GPR: GPU Power Rail */
+				(0 << 10) |		/* GCR: GC6 ROM */
+				(1 << 11) |		/* PTH: No SMI Handler */
+				(0 << 12) |		/* NOT: Supports Notify on GC6 State done */
+				(1 << 13) |		/* MHYB: MS Hybrid Support (deferred GC6) */
+				(1 << 14) |		/* RPC: Root Port Control */
+				(2 << 15) |		/* GC6 Version (GC6-R) */
+				(0 << 17) |		/* GEI: GC6 Exit ISR Support */
+				(0 << 18) |		/* GSW: GC6 Self Wakeup */
+				(0x200 << 20)))		/* MXRV: Highest Revision */
+		}
+		Case (JT_FUNC_POWERCONTROL)
+		{
+			CreateField (Arg1, 0, 3, GPC)	/* GPU Power Control */
+			CreateField (Arg1, 4, 1, PPC)	/* Panel Power Control */
+			CreateField (Arg1, 14, 2, DFGC)	/* Defer GC6 enter/exit */
+			CreateField (Arg1, 16, 3, GPCX) /* Deferred GC6 exit */
+
+			/* Deferred GC6 entry/exit is requested */
+			If (ToInteger(GPC) != 0 || ToInteger(DFGC) != 0)
+			{
+				DFEN = ToInteger(DFGC)
+				DFCI = ToInteger(GPC)
+				DFCO = ToInteger(GPCX)
+			}
+
+			Local0 = Buffer (4) { 0x0 }
+			CreateField (Local0, 0, 3, CGCS)	/* Current GC State */
+			CreateField (Local0, 3, 1, CGPS)	/* Current GPU power status */
+			CreateField (Local0, 7, 1, CPSS)	/* Current panel and SRC state */
+
+			/* Leave early if deferred GC6 is requested */
+			If (DFEN != 0)
+			{
+				CGCS = 1
+				CGPS = 1
+				Return (Local0)
+			}
+
+			Switch (ToInteger(GPC))
+			{
+				/* Get GCU GCx Sleep Status */
+				Case (NVJT_GPC_GSS)
+				{
+					If (PSTA () != 0)
+					{
+						CGPS = 1
+						CGCS = 1
+					}
+					Else
+					{
+						CGPS = 0
+						CGCS = 3
+					}
+				}
+				Case (NVJT_GPC_EGNS)
+				{
+					/* Enter GC6; no self-refresh */
+					GC6I ()
+					CPSS = 1
+					CGCS = 0
+				}
+				Case (NVJT_GPC_EGIS)
+				{
+					/* Enter GC6; enable self-refresh */
+					GC6I ()
+					If (ToInteger (PPC) == 0)
+					{
+						CPSS = 0
+					}
+					CGCS = 0
+				}
+				Case (NVJT_GPS_XGXS)
+				{
+					/* Exit GC6; stop self-refresh */
+					GC6O ()
+					CGCS = 1
+					CGPS = 1
+					If (ToInteger (PPC) != 0)
+					{
+						CPSS = 0
+					}
+				}
+				Case (NVJT_GPS_XGIS)
+				{
+					/* Exit GC6 for self-refresh */
+					GC6O ()
+					CGCS = 1
+					CGPS = 1
+					If (ToInteger (PPC) != 0)
+					{
+						CPSS = 0
+					}
+				}
+			}
+
+			Return (Local0)
+		}
+	}
+
+	Return (NV_ERROR_UNSUPPORTED)
+}
diff --git a/src/mainboard/novacustom/mtl-h/acpi/dgpu/nvop.asl b/src/mainboard/novacustom/mtl-h/acpi/dgpu/nvop.asl
new file mode 100644
index 0000000000..1f534be549
--- /dev/null
+++ b/src/mainboard/novacustom/mtl-h/acpi/dgpu/nvop.asl
@@ -0,0 +1,68 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#define NVOP_FUNC_SUPPORT		0x00
+#define NVOP_FUNC_OPTIMUS_CAPS		0x1a
+#define NVOP_FUNC_OPTIMUS_STATUS	0x1b
+
+Method (NVOP, 2, Serialized)
+{
+	Switch (ToInteger (Arg0))
+	{
+		Case (NVOP_FUNC_SUPPORT)
+		{
+			Return (ITOB (
+				(1 << NVOP_FUNC_SUPPORT) |
+				(1 << NVOP_FUNC_OPTIMUS_CAPS) |
+				(1 << NVOP_FUNC_OPTIMUS_STATUS)))
+		}
+		Case (NVOP_FUNC_OPTIMUS_CAPS)
+		{
+			CreateField(Arg1, 0, 1, FLUP)	/* Flag Update */
+			CreateField(Arg1, 1, 1, CSOT)	/* Change configuration Space Owner Target */
+			CreateField(Arg1, 2, 1, CSOW)	/* Change configuration Space Owner Write */
+			CreateField(Arg1, 24, 2, NPCE)	/* New Power Control Enable setting */
+
+			/* Change Optimus power control capabilities */
+			If (ToInteger (FLUP) != 0 && ToInteger (NPCE) != 0)
+			{
+				OPCS = NPCE
+			}
+
+			/* Change PCI configuration space save/restore owner */
+			If (ToInteger (CSOW) == 1)
+			{
+				PCIO = CSOT
+			}
+
+			/* Current GPU Control Status */
+			If (PSTA () == 1)
+			{
+				Local0 = 3
+			}
+			Else
+			{
+				Local0 = 0
+			}
+
+			Return (ITOB (
+				(1 << 0) |	/* Optimus Enabled */
+				(Local0 << 3) |	/* Current GPU Control Status */
+				(1 << 6) |	/* Shared Discrete GPU Hotplug Capabilities */
+				(0 << 7) |	/* MUXed DDC/Aux Capabilities */
+				(PCIO << 8) |	/* PCIe Configuration Space Owner */
+				(1 << 24) |	/* Platform Optimus Power Capabilities */
+				(3 << 27)))	/* Optimus HD Audio Codec Capabilities */
+		}
+		Case (NVOP_FUNC_OPTIMUS_STATUS)
+		{
+			Return (ITOB (
+				(1 << 0) |	/* Optimus Audio Codec Control */
+				(0 << 2) |	/* Request GPU Power State */
+				(0 << 4) |	/* Evaluate Requested GPU Power State */
+				(0 << 5) |	/* Request Optimus Adapter Policy */
+				(0 << 7)))	/* Evaluate Requested Optimus Adapter Selection */
+		}
+	}
+
+	Return (NV_ERROR_UNSUPPORTED)
+}
diff --git a/src/mainboard/novacustom/mtl-h/acpi/dgpu/peg.asl b/src/mainboard/novacustom/mtl-h/acpi/dgpu/peg.asl
new file mode 100644
index 0000000000..ac0c17cbb2
--- /dev/null
+++ b/src/mainboard/novacustom/mtl-h/acpi/dgpu/peg.asl
@@ -0,0 +1,99 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+External (\_SB.PCI0.RP12.PXSX.NPON, MethodObj)
+External (\_SB.PCI0.RP12.PXSX.NPOF, MethodObj)
+
+OperationRegion (PCIC, PCI_Config, 0x00, 0x100)
+Field (PCIC, AnyAcc, NoLock, Preserve)
+{
+	Offset (0x4a),
+	CEDR,   1,		/* Correctable Error Detected, RW/1C/V */
+	Offset (0x52),
+	,	13,
+	LASX,	1,		/* Link Active Status */
+	Offset (0x69),
+	,       2,
+	LREN,   1,		/* LTR Enabled */
+	Offset (0xe0),
+	,	7,
+	NCB7,	1,		/* Scratch bit to save L2/3 state */
+	Offset (0xe2),
+	,	2,
+	L23E,	1,		/* L23_Rdy Entry request */
+	L23R,	1		/* L23_Rdy Detect Transition */
+}
+
+/* L2/3 Entry sequence */
+Method (DL23, 0, Serialized)
+{
+	L23E = 1
+	Local0 = 8
+	While (Local0 > 0)
+	{
+		If (!L23E)
+		{
+			Break
+		}
+
+		Sleep (2)
+		Local0--
+	}
+	NCB7 = 1
+}
+
+/* L2/3 exit seqeuence */
+Method (LD23, 0, Serialized)
+{
+	If (!NCB7)
+	{
+		Return
+	}
+
+	L23R = 1
+	Local0 = 20
+	While (Local0 > 0)
+	{
+		If (!L23R)
+		{
+			Break
+		}
+
+		Sleep (2)
+		Local0--
+	}
+
+	NCB7 = 0
+	Local0 = 8
+	While (Local0 > 0)
+	{
+		If (LASX == 1)
+		{
+			Break
+		}
+
+		Sleep (2)
+		Local0--
+	}
+}
+
+/* PEG Power Resource */
+PowerResource (PGPR, 0, 0)
+{
+	Method (_ON, 0, Serialized)
+	{
+		/* Power up GPU from GCOFF (or GC6 exit if deferred) */
+		\_SB.PCI0.RP12.PXSX.NPON ()
+		_STA = 1
+	}
+	Method (_OFF, 0, Serialized)
+	{
+		/* Power down GPU to GCOFF (or GC6 entry if deferred) */
+		_STA = 0
+		\_SB.PCI0.RP12.PXSX.NPOF ()
+	}
+	Name (_STA, 0)
+}
+
+Name (_PR0, Package() { PGPR })
+Name (_PR2, Package() { PGPR })
+Name (_PR3, Package() { PGPR })
diff --git a/src/mainboard/novacustom/mtl-h/acpi/dgpu/power.asl b/src/mainboard/novacustom/mtl-h/acpi/dgpu/power.asl
new file mode 100644
index 0000000000..496fd2c147
--- /dev/null
+++ b/src/mainboard/novacustom/mtl-h/acpi/dgpu/power.asl
@@ -0,0 +1,315 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <device/pci_ids.h>
+
+External (\_SB.PCI0.SPCO, MethodObj)
+
+
+/* Board specific defines */
+
+/* PCI Subsystem ID to restore after wake */
+#define GPU_SSID 0xa7611558
+
+/* Power control signals */
+#define GPIO_GPU_PERST_L	GPP_B09
+#define GPIO_GPU_PWR_EN		GPP_D03
+#define GPIO_GPU_PWR_GD		GPP_C15
+#define GPIO_GPU_NVVDD_EN	GPP_F16
+
+/* GPU clock pin */
+#define GPU_SRCCLK_PIN		0x6
+
+#define GC6_DEFER_TYPE_EXIT_GC6	3
+
+/* 250ms in "Timer" units (i.e. 100ns increments) */
+#define MIN_OFF_TIME_TIMERS	2500000
+
+#define SRCCLK_DISABLE		0
+#define SRCCLK_ENABLE		1
+
+#define GPU_POWER_STATE_OFF	0
+#define GPU_POWER_STATE_ON	1
+
+/* Optimus Power Control State */
+Name (OPCS, OPTIMUS_POWER_CONTROL_DISABLE)
+
+/* PCI configuration space Owner */
+Name (PCIO, PCI_OWNER_SBIOS)
+
+/* Deferred GPU State */
+Name (OPS0, OPTIMUS_CONTROL_NO_RUN_PS0)
+
+/* GC6 Entry/Exit state */
+Name (GC6E, GC6_STATE_EXITED)
+
+/* Power State, GCOFF, GCON */
+Name (GPPS, GPU_POWER_STATE_ON)
+
+/* Defer GC6 entry / exit until D3-cold request */
+Name (DFEN, 0)
+/* Deferred GC6 Enter control */
+Name (DFCI, 0)
+/* Deferred GC6 Exit control */
+Name (DFCO, 0)
+/* GCOFF Timer */
+Name (GCOT, 0)
+
+/* Copy of LTR enable bit from PEG port */
+Name (SLTR, 0)
+
+/* Control the PCIe SRCCLK# for dGPU */
+Method (SRCC, 1, Serialized)
+{
+	/* Control clock via P2SB interface */
+	\_SB.PCI0.SPCO (GPU_SRCCLK_PIN, Arg0)
+}
+
+/* "GC6 In", i.e. GC6 Entry Sequence */
+Method (GC6I, 0, Serialized)
+{
+	GC6E = GC6_STATE_TRANSITION
+
+	/* Save the PEG port's LTR setting */
+	SLTR = LREN
+
+	/* Put PCIe link into L2/3 */
+	\_SB.PCI0.RP12.DL23 ()
+
+	/* Wait for GPU to deassert its GPIO4, i.e. GPU_NVVDD_EN */
+	GPPL (GPIO_GPU_NVVDD_EN, 0, 20)
+
+	/* Assert GPU_PERST_L */
+	CTXS (GPIO_GPU_PERST_L)
+
+	/* Disable PCIe SRCCLK# */
+	SRCC (SRCCLK_DISABLE)
+
+	GC6E = GC6_STATE_ENTERED
+}
+
+/* "GC6 Out", i.e. GC6 Exit Sequence */
+Method (GC6O, 0, Serialized)
+{
+	GC6E = GC6_STATE_TRANSITION
+
+	/* Re-enable PCIe SRCCLK# */
+	SRCC (SRCCLK_ENABLE)
+
+	/* Deassert GPU_PERST_L */
+	STXS (GPIO_GPU_PERST_L)
+
+	/* Wait for GPU to assert GPU_NVVDD_EN */
+	GPPL (GPIO_GPU_NVVDD_EN, 1, 20)
+
+	/* Restore PCIe link back to L0 state */
+	\_SB.PCI0.RP12.LD23 ()
+
+	/* Wait for dGPU to reappear on the bus */
+	Local0 = 50
+	While (NVID != PCI_VID_NVIDIA)
+	{
+		Stall (100)
+		Local0--
+		If (Local0 == 0)
+		{
+			Break
+		}
+	}
+
+	/* Restore the PEG LTR enable bit */
+	LREN = SLTR
+
+	/* Clear recoverable errors detected bit */
+	CEDR = 1
+
+	GC6E = GC6_STATE_EXITED
+}
+
+/* GCOFF exit sequence */
+Method (PGON, 0, Serialized)
+{
+	Local0 = Timer - GCOT
+	If (Local0 < MIN_OFF_TIME_TIMERS)
+	{
+		Local1 = (MIN_OFF_TIME_TIMERS - Local0) / 10000
+		Printf("Sleeping %o to ensure min GCOFF time", Local1)
+		Sleep (Local1)
+	}
+
+	/* Assert PERST# */
+	CTXS (GPIO_GPU_PERST_L)
+
+	/* Enable power rails */
+	STXS (GPIO_GPU_PWR_EN)
+
+	/* Wait 200ms for PWRGD */
+	GPPL (GPIO_GPU_PWR_GD, 1, 200)
+
+	/* Deassert PERST# */
+	STXS (GPIO_GPU_PERST_L)
+
+	GC6E = GC6_STATE_EXITED
+	GPPS = GPU_POWER_STATE_ON
+}
+
+/* GCOFF entry sequence */
+Method (PGOF, 0, Serialized)
+{
+	/* Assert PERST# */
+	CTXS (GPIO_GPU_PERST_L)
+
+	/* Disable power rails */
+	CTXS (GPIO_GPU_PWR_EN)
+
+	GCOT = Timer
+
+	GPPS = GPU_POWER_STATE_OFF
+}
+
+/* GCOFF Out, i.e. full power-on sequence */
+Method (GCOO, 0, Serialized)
+{
+	If (GPPS == GPU_POWER_STATE_ON)
+	{
+		Printf ("PGON: GPU already on")
+		Return
+	}
+
+	SRCC (SRCCLK_ENABLE)
+	PGON ()
+	\_SB.PCI0.RP12.LD23 ()
+
+	/* Wait for dGPU to reappear on the bus */
+	Local0 = 50
+	While (NVID != PCI_VID_NVIDIA)
+	{
+		Stall (100)
+		Local0--
+		If (Local0 == 0)
+		{
+			Break
+		}
+	}
+
+	/* Restore the PEG LTR enable bit */
+	LREN = SLTR
+
+	/* Clear recoverable errors detected bit */
+	CEDR = 1
+
+	/* Restore the PEG LTR enable bit */
+	LREN = SLTR
+
+	/* Clear recoverable errors detected bit */
+	CEDR = 1
+}
+
+/* GCOFF In, i.e. full power-off sequence */
+Method (GCOI, 0, Serialized)
+{
+	If (GPPS == GPU_POWER_STATE_OFF)
+	{
+		Printf ("GPU already off")
+		Return
+	}
+
+	/* Save the PEG port's LTR setting */
+	SLTR = LREN
+	\_SB.PCI0.RP12.DL23 ()
+	PGOF ()
+	SRCC (SRCCLK_DISABLE)
+}
+
+/* Handle deferred GC6 vs. poweron request */
+Method (NPON, 0, Serialized)
+{
+	If (DFEN == GC6_DEFER_ENABLE)
+	{
+		If (DFCO == GC6_DEFER_TYPE_EXIT_GC6)
+		{
+			GC6O ()
+		}
+
+		DFEN = GC6_DEFER_DISABLE
+	}
+	Else
+	{
+		GCOO ()
+	}
+	NVSS = GPU_SSID
+}
+
+/* Handle deferred GC6 vs. poweroff request */
+Method (NPOF, 0, Serialized)
+{
+	/* Don't touch the `DFEN` flag until the GC6 exit. */
+	If (DFEN == GC6_DEFER_ENABLE)
+	{
+		/* Deferred GC6 entry */
+		If (DFCI == NVJT_GPC_EGNS || DFCI == NVJT_GPC_EGIS)
+		{
+			GC6I ()
+		}
+	}
+	Else
+	{
+		GCOI ()
+	}
+}
+
+Method (_ON, 0, Serialized)
+{
+	PGON ()
+	NVSS = GPU_SSID
+}
+
+Method (_OFF, 0, Serialized)
+{
+	PGOF ()
+}
+
+/* Put device into D0 */
+Method (_PS0, 0, NotSerialized)
+{
+	If (OPS0 == OPTIMUS_CONTROL_RUN_PS0)
+	{
+		/* Poweron or deferred GC6 exit */
+		NPON ()
+
+		OPS0 = OPTIMUS_CONTROL_NO_RUN_PS0
+	}
+}
+
+/* Put device into D3 */
+Method (_PS3, 0,  NotSerialized)
+{
+	If (OPCS == OPTIMUS_POWER_CONTROL_ENABLE)
+	{
+		/* Poweroff or deferred GC6 entry */
+		NPOF ()
+
+		/* Because _PS3 ran NPOF, _PS0 must run NPON */
+		OPS0 = OPTIMUS_CONTROL_RUN_PS0
+
+		/* OPCS is one-shot, so reset it */
+		OPCS = OPTIMUS_POWER_CONTROL_DISABLE
+	}
+}
+
+Method (PSTA, 0, Serialized)
+{
+	If (GC6E == GC6_STATE_EXITED &&
+	    \_SB.PCI0.GTXS(GPIO_GPU_PWR_GD) == 1)
+	{
+		Return (1)
+	}
+	Else
+	{
+		Return (0)
+	}
+}
+
+Method (_STA, 0, Serialized)
+{
+	Return (0xF)
+}
diff --git a/src/mainboard/novacustom/mtl-h/acpi/dgpu/utility.asl b/src/mainboard/novacustom/mtl-h/acpi/dgpu/utility.asl
new file mode 100644
index 0000000000..7bf97d4af4
--- /dev/null
+++ b/src/mainboard/novacustom/mtl-h/acpi/dgpu/utility.asl
@@ -0,0 +1,58 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+/*
+ * Poll a GPIO until it goes to the specified state
+ * Arg0 == GPIO #
+ * Arg1 == state (0 or 1)
+ * Arg2 == timeout in ms
+ */
+Method (GPPL, 3, Serialized)
+{
+	Local0 = 0
+	Local1 = Arg2 * 10
+	While (Local0 < Local1)
+	{
+		If (\_SB.PCI0.GRXS (Arg0) == Arg1)
+		{
+			Return (0)
+		}
+		Else
+		{
+			Local0++
+		}
+		Stall (100)
+	}
+
+	If (Local0 == Arg2)
+	{
+		Printf("[ERROR] GPPL for %o timed out", Arg0)
+	}
+
+	Return (0xFF)
+}
+
+/* Convert from 32-bit integer to 4-byte buffer (little-endian) */
+Method (ITOB, 1)
+{
+	Local0 = Buffer(4) { 0, 0, 0, 0 }
+	Local0[0] = Arg0 & 0xFF
+	Local0[1] = (Arg0 >> 8) & 0xFF
+	Local0[2] = (Arg0 >> 16) & 0xFF
+	Local0[3] = (Arg0 >> 24) & 0xFF
+	Return (Local0)
+}
+
+/* Convert from 64-bit integer to 8-byte buffer (little-endian) */
+Method (LTOB, 1)
+{
+	Local0 = Buffer(8) { 0, 0, 0, 0, 0, 0, 0, 0 }
+	Local0[0] = Arg0 & 0xFF
+	Local0[1] = (Arg0 >> 8) & 0xFF
+	Local0[2] = (Arg0 >> 16) & 0xFF
+	Local0[3] = (Arg0 >> 24) & 0xFF
+	Local0[4] = (Arg0 >> 32) & 0xFF
+	Local0[5] = (Arg0 >> 40) & 0xFF
+	Local0[6] = (Arg0 >> 48) & 0xFF
+	Local0[7] = (Arg0 >> 56) & 0xFF
+	Return (Local0)
+}
diff --git a/src/mainboard/novacustom/mtl-h/dsdt.asl b/src/mainboard/novacustom/mtl-h/dsdt.asl
index 06e7263d07..2b2bcb8fc8 100644
--- a/src/mainboard/novacustom/mtl-h/dsdt.asl
+++ b/src/mainboard/novacustom/mtl-h/dsdt.asl
@@ -31,4 +31,8 @@ DefinitionBlock(
 	}
 
 	#include "acpi/mainboard.asl"
+
+#if CONFIG(BOARD_NOVACUSTOM_V5X0TNX_BASE)
+	#include "acpi/dgpu/gpu_top.asl"
+#endif
 }

From 47f1b798e4a6042d3162a790d511e6e5055feb6e Mon Sep 17 00:00:00 2001
From: Maximilian Brune <maximilian.brune@9elements.com>
Date: Sat, 12 Apr 2025 20:35:33 +0200
Subject: [PATCH 1387/3886] util/amdfwtool/amdfwtool.c: Remove APOB_NV src
 address check

The current approach has two problems:
- Just because the source address is 0 does not mean it is no
  specifically set. A bunch of mainboards specify their APOB_NV base
  address at 0 in their FMAP files.
- There is no AMD SOC that has support for this binary, but doesn't give
  AMDFWTOOL the base address. It would also not work considering that
  AMD common/block/apob code gets the region from the FMAP.

Therefore just remove the check since no mainboard will ever enter the
else branch.

tested: binary identical for at least 1 mainboard on each SOC
generation.

Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: Ic85d6b25c95ab12dbcc72d17158591891dd04e97
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87292
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
---
 util/amdfwtool/amdfwtool.c | 22 ++++------------------
 1 file changed, 4 insertions(+), 18 deletions(-)

diff --git a/util/amdfwtool/amdfwtool.c b/util/amdfwtool/amdfwtool.c
index 73a13c3a8a..c28c734721 100644
--- a/util/amdfwtool/amdfwtool.c
+++ b/util/amdfwtool/amdfwtool.c
@@ -1410,24 +1410,10 @@ static void integrate_bios_firmwares(context *ctx,
 			biosdir->entries[count].address_mode = SET_ADDR_MODE_BY_TABLE(biosdir);
 			break;
 		case AMD_BIOS_APOB_NV:
-			if (fw_table[i].src) {
-				/* If source is given, use that and its size */
-				biosdir->entries[count].source = fw_table[i].src;
-				biosdir->entries[count].address_mode =
-						SET_ADDR_MODE(biosdir, AMD_ADDR_REL_BIOS);
-				biosdir->entries[count].size = fw_table[i].size;
-			} else {
-				/* Else reserve size bytes within amdfw.rom */
-				adjust_current_pointer(ctx, 0, ERASE_ALIGNMENT);
-				biosdir->entries[count].source = RUN_CURRENT(*ctx);
-				biosdir->entries[count].address_mode =
-						SET_ADDR_MODE(biosdir, AMD_ADDR_REL_BIOS);
-				biosdir->entries[count].size = ALIGN_UP(
-						fw_table[i].size, ERASE_ALIGNMENT);
-				memset(BUFF_CURRENT(*ctx), 0xff,
-						biosdir->entries[count].size);
-				adjust_current_pointer(ctx, biosdir->entries[count].size, 1);
-			}
+			biosdir->entries[count].source = fw_table[i].src;
+			biosdir->entries[count].address_mode =
+					SET_ADDR_MODE(biosdir, AMD_ADDR_REL_BIOS);
+			biosdir->entries[count].size = fw_table[i].size;
 			break;
 		case AMD_BIOS_BIN:
 			/* Don't make a 2nd copy, point to the same one */

From 912161e52de644eb1ede751620adef50651e10a7 Mon Sep 17 00:00:00 2001
From: Hualin Wei <weihualin@huaqin.corp-partner.google.com>
Date: Thu, 19 Jun 2025 19:05:13 +0800
Subject: [PATCH 1388/3886] spd/lp4x: Modify parameters of SPD for
 NT6AP1024F32BL-J1
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

According to the latest SPD parameters provided by the manufacturer,
combined with the document 8Gb_LPDDR4X_B_Die_component_Datasheet(S).pdf
we correct channelsPerDie, diesPerPackage, ranksPerChannel of SPD
for Nanya NT6AP1024F32BL-J1; merged the parameters into the BIOS and
flashed it into the machine. The machine can boot and read the normal
size of memory.

BUG=b.422906387
TEST=util/spd_tools/bin/spd_gen spd/lp4x/memory_parts.json lp4x
     Use the dmidecode -t memory command to read the size of memory.

Output results：
awasuki-rev2  # dmidecode -t memory
# dmidecode 3.4
Getting SMBIOS data from sysfs.
SMBIOS 3.0 present.

Handle 0x000A, DMI type 16, 23 bytes
Physical Memory Array
	Location: System Board Or Motherboard
	Use: System Memory
	Error Correction Type: None
	Maximum Capacity: 64 GB
	Error Information Handle: Not Provided
	Number Of Devices: 4

Handle 0x000B, DMI type 17, 40 bytes
Memory Device
	Array Handle: 0x000A
	Error Information Handle: Not Provided
	Total Width: 32 bits
	Data Width: 32 bits
	Size: 8 GB
	Form Factor: Unknown
	Set: None
	Locator: Channel-0-DIMM-0
	Bank Locator: BANK 0
	Type: LPDDR4
	Type Detail: Synchronous
	Speed: 2933 MT/s
	Manufacturer: Unknown (b03)
	Serial Number: 00000000
	Asset Tag: Not Specified
	Part Number: NT6AP1024F32BL-J1
	Rank: 2
	Configured Memory Speed: 2933 MT/s
	Minimum Voltage: 0.6 V
	Maximum Voltage: 0.6 V
	Configured Voltage: 0.6 V

Change-Id: I35823ce87b5d8d67894528e4a8781dd91247eb6c
Signed-off-by: Hualin Wei <weihualin@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88146
Reviewed-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 spd/lp4x/memory_parts.json | 6 +++---
 spd/lp4x/set-0/spd-9.hex   | 2 +-
 spd/lp4x/set-1/spd-12.hex  | 2 +-
 3 files changed, 5 insertions(+), 5 deletions(-)

diff --git a/spd/lp4x/memory_parts.json b/spd/lp4x/memory_parts.json
index fc3fd83c1e..094dcf3c96 100644
--- a/spd/lp4x/memory_parts.json
+++ b/spd/lp4x/memory_parts.json
@@ -429,10 +429,10 @@
             "attribs": {
                 "densityPerChannelGb": 8,
                 "banks": 8,
-                "channelsPerDie": 4,
-                "diesPerPackage": 1,
+                "channelsPerDie": 2,
+                "diesPerPackage": 2,
                 "bitWidthPerChannel": 16,
-                "ranksPerChannel": 1,
+                "ranksPerChannel": 2,
                 "speedMbps": 4267,
                 "tckMaxPs": 468,
                 "casLatencies": "6 10 14 20 24 28 32 36"
diff --git a/spd/lp4x/set-0/spd-9.hex b/spd/lp4x/set-0/spd-9.hex
index 94a317f807..b4cdcf612f 100644
--- a/spd/lp4x/set-0/spd-9.hex
+++ b/spd/lp4x/set-0/spd-9.hex
@@ -1,4 +1,4 @@
-23 11 11 0E 15 21 B8 08 00 00 00 00 02 01 00 00
+23 11 11 0E 15 21 B4 08 00 00 00 00 0A 01 00 00
 00 00 04 04 92 54 05 00 87 00 90 A8 90 C0 08 60
 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
diff --git a/spd/lp4x/set-1/spd-12.hex b/spd/lp4x/set-1/spd-12.hex
index e3d97d5c2f..014037a5d3 100644
--- a/spd/lp4x/set-1/spd-12.hex
+++ b/spd/lp4x/set-1/spd-12.hex
@@ -1,4 +1,4 @@
-23 11 11 0E 17 21 08 08 00 00 00 00 02 22 00 00
+23 11 11 0E 16 21 94 08 00 00 00 00 0A 22 00 00
 00 00 04 04 92 54 05 00 87 00 90 A8 90 C0 08 60
 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00

From 1c2978dba6af07724d8facf9702d249588ac804b Mon Sep 17 00:00:00 2001
From: Hualin Wei <weihualin@huaqin.corp-partner.google.com>
Date: Thu, 19 Jun 2025 19:40:37 +0800
Subject: [PATCH 1389/3886] mb/google/dedede/var/awasuki: Add ChangXin modules
 to RAM id table

Add ChangXin CXDB4CBAM-ML-A as id 2, resulting in the list below:

DRAM Part Name                 ID to assign
K4U6E3S4AB-MGCL                0 (0000)
K4UBE3D4AB-MGCL                1 (0001)
MT53E1G32D2NP-046 WT:B         1 (0001)
NT6AP512T32BL-J1               2 (0010)
NT6AP1024F32BL-J1              3 (0011)
CXDB4CBAM-ML-A                 2 (0010)

BUG=422906387
TEST=Use part_id_gen to generate related settings

Change-Id: Ia9c091975cca6442833d374d40e98299ed5f0f0d
Signed-off-by: Hualin Wei <weihualin@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88147
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com>
---
 src/mainboard/google/dedede/variants/awasuki/memory/Makefile.mk | 2 +-
 .../google/dedede/variants/awasuki/memory/dram_id.generated.txt | 1 +
 .../google/dedede/variants/awasuki/memory/mem_parts_used.txt    | 1 +
 3 files changed, 3 insertions(+), 1 deletion(-)

diff --git a/src/mainboard/google/dedede/variants/awasuki/memory/Makefile.mk b/src/mainboard/google/dedede/variants/awasuki/memory/Makefile.mk
index be392405ee..5fc455609e 100644
--- a/src/mainboard/google/dedede/variants/awasuki/memory/Makefile.mk
+++ b/src/mainboard/google/dedede/variants/awasuki/memory/Makefile.mk
@@ -6,5 +6,5 @@
 SPD_SOURCES =
 SPD_SOURCES += spd/lp4x/set-1/spd-1.hex      # ID = 0(0b0000)  Parts = K4U6E3S4AB-MGCL
 SPD_SOURCES += spd/lp4x/set-1/spd-3.hex      # ID = 1(0b0001)  Parts = K4UBE3D4AB-MGCL, MT53E1G32D2NP-046 WT:B
-SPD_SOURCES += spd/lp4x/set-1/spd-11.hex      # ID = 2(0b0010)  Parts = NT6AP512T32BL-J1
+SPD_SOURCES += spd/lp4x/set-1/spd-11.hex      # ID = 2(0b0010)  Parts = NT6AP512T32BL-J1, CXDB4CBAM-ML-A
 SPD_SOURCES += spd/lp4x/set-1/spd-12.hex      # ID = 3(0b0011)  Parts = NT6AP1024F32BL-J1
diff --git a/src/mainboard/google/dedede/variants/awasuki/memory/dram_id.generated.txt b/src/mainboard/google/dedede/variants/awasuki/memory/dram_id.generated.txt
index dfcf164835..81011e157a 100644
--- a/src/mainboard/google/dedede/variants/awasuki/memory/dram_id.generated.txt
+++ b/src/mainboard/google/dedede/variants/awasuki/memory/dram_id.generated.txt
@@ -9,3 +9,4 @@ K4UBE3D4AB-MGCL                1 (0001)
 MT53E1G32D2NP-046 WT:B         1 (0001)
 NT6AP512T32BL-J1               2 (0010)
 NT6AP1024F32BL-J1              3 (0011)
+CXDB4CBAM-ML-A                 2 (0010)
diff --git a/src/mainboard/google/dedede/variants/awasuki/memory/mem_parts_used.txt b/src/mainboard/google/dedede/variants/awasuki/memory/mem_parts_used.txt
index 44e5720a69..21c1901980 100644
--- a/src/mainboard/google/dedede/variants/awasuki/memory/mem_parts_used.txt
+++ b/src/mainboard/google/dedede/variants/awasuki/memory/mem_parts_used.txt
@@ -15,3 +15,4 @@ K4UBE3D4AB-MGCL
 MT53E1G32D2NP-046 WT:B
 NT6AP512T32BL-J1
 NT6AP1024F32BL-J1
+CXDB4CBAM-ML-A

From 1f28803dcd072f5dc1437155e849e3ec1084c2a4 Mon Sep 17 00:00:00 2001
From: "wu.garen" <wu.garen@inventec.corp-partner.google.com>
Date: Mon, 9 Jun 2025 23:28:58 +0800
Subject: [PATCH 1390/3886] mb/trulo/var/kaladin: Create kaladin variant

Create the kaladin variant of trulo reference board by copying the
template files to a new directory named for the variant.

Due to new_variant.py limitation that repo can no longer be used in
inside, created this CL manually following google suggestion.

BUG=b:420836320
TEST=util/abuild/abuild -p none -t google/brya -x -a
make sure the build includes GOOGLE_KALADIN

Change-Id: Ib0cbe8c4c0d988aec1bab0f272d1abd532cbc54f
Signed-off-by: wu.garen <wu.garen@inventec.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88009
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
---
 src/mainboard/google/brya/Kconfig             |  12 +
 src/mainboard/google/brya/Kconfig.name        |   3 +
 .../google/brya/variants/kaladin/Makefile.mk  |   7 +
 .../google/brya/variants/kaladin/gpio.c       | 487 ++++++++++++++++++
 .../google/brya/variants/kaladin/hda_verb.c   | 118 +++++
 .../variants/kaladin/include/variant/ec.h     |   8 +
 .../variants/kaladin/include/variant/gpio.h   |   8 +
 .../google/brya/variants/kaladin/memory.c     | 111 ++++
 .../brya/variants/kaladin/memory/Makefile.mk  |   9 +
 .../kaladin/memory/dram_id.generated.txt      |   9 +
 .../kaladin/memory/mem_parts_used.txt         |  14 +
 .../brya/variants/kaladin/overridetree.cb     | 473 +++++++++++++++++
 12 files changed, 1259 insertions(+)
 create mode 100644 src/mainboard/google/brya/variants/kaladin/Makefile.mk
 create mode 100644 src/mainboard/google/brya/variants/kaladin/gpio.c
 create mode 100644 src/mainboard/google/brya/variants/kaladin/hda_verb.c
 create mode 100644 src/mainboard/google/brya/variants/kaladin/include/variant/ec.h
 create mode 100644 src/mainboard/google/brya/variants/kaladin/include/variant/gpio.h
 create mode 100644 src/mainboard/google/brya/variants/kaladin/memory.c
 create mode 100644 src/mainboard/google/brya/variants/kaladin/memory/Makefile.mk
 create mode 100644 src/mainboard/google/brya/variants/kaladin/memory/dram_id.generated.txt
 create mode 100644 src/mainboard/google/brya/variants/kaladin/memory/mem_parts_used.txt
 create mode 100644 src/mainboard/google/brya/variants/kaladin/overridetree.cb

diff --git a/src/mainboard/google/brya/Kconfig b/src/mainboard/google/brya/Kconfig
index 0acb11c8ef..c1f65ef00d 100644
--- a/src/mainboard/google/brya/Kconfig
+++ b/src/mainboard/google/brya/Kconfig
@@ -321,6 +321,14 @@ config BOARD_GOOGLE_HADES
 	select RT8168_GET_MAC_FROM_VPD
 	select RT8168_SET_LED_MODE
 
+config BOARD_GOOGLE_KALADIN
+	select BOARD_GOOGLE_BASEBOARD_TRULO
+	select CHROMEOS_WIFI_SAR if CHROMEOS
+	select DRIVERS_GENERIC_GPIO_KEYS
+	select SOC_INTEL_COMMON_BLOCK_HDA_VERB
+	select SOC_INTEL_TCSS_USE_PDC_PMC_USBC_MUX_CONFIGURATION
+	select SOC_INTEL_TWINLAKE
+
 config BOARD_GOOGLE_KANO
 	select BOARD_GOOGLE_BASEBOARD_BRYA
 	select CHROMEOS_WIFI_SAR if CHROMEOS
@@ -841,6 +849,7 @@ config DRIVER_TPM_I2C_BUS
 	default 0x3 if BOARD_GOOGLE_HADES
 	default 0x0 if BOARD_GOOGLE_JOXER
 	default 0x1 if BOARD_GOOGLE_KANO
+	default 0x0 if BOARD_GOOGLE_KALADIN
 	default 0x1 if BOARD_GOOGLE_KINOX
 	default 0x1 if BOARD_GOOGLE_KULDAX
 	default 0x1 if BOARD_GOOGLE_LISBON
@@ -928,6 +937,7 @@ config TPM_TIS_ACPI_INTERRUPT
 	default 20 if BOARD_GOOGLE_HADES # GPE0_DW0_20 (GPP_A20_IRQ)
 	default 13 if BOARD_GOOGLE_JOXER
 	default 13 if BOARD_GOOGLE_KANO
+	default 13 if BOARD_GOOGLE_KALADIN
 	default 13 if BOARD_GOOGLE_KINOX
 	default 13 if BOARD_GOOGLE_KULDAX
 	default 13 if BOARD_GOOGLE_LISBON
@@ -1019,6 +1029,7 @@ config MAINBOARD_PART_NUMBER
 	default "Hades" if BOARD_GOOGLE_HADES
 	default "Joxer" if BOARD_GOOGLE_JOXER
 	default "Kano" if BOARD_GOOGLE_KANO
+	default "Kaladin" if BOARD_GOOGLE_KALADIN
 	default "Kinox" if BOARD_GOOGLE_KINOX
 	default "Kuldax" if BOARD_GOOGLE_KULDAX
 	default "Lisbon" if BOARD_GOOGLE_LISBON
@@ -1099,6 +1110,7 @@ config VARIANT_DIR
 	default "hades" if BOARD_GOOGLE_HADES
 	default "joxer" if BOARD_GOOGLE_JOXER
 	default "kano" if BOARD_GOOGLE_KANO
+	default "kaladin" if BOARD_GOOGLE_KALADIN
 	default "kinox" if BOARD_GOOGLE_KINOX
 	default "kuldax" if BOARD_GOOGLE_KULDAX
 	default "lisbon" if BOARD_GOOGLE_LISBON
diff --git a/src/mainboard/google/brya/Kconfig.name b/src/mainboard/google/brya/Kconfig.name
index acc21afc28..58bcb74157 100644
--- a/src/mainboard/google/brya/Kconfig.name
+++ b/src/mainboard/google/brya/Kconfig.name
@@ -77,6 +77,9 @@ config BOARD_GOOGLE_HADES
 config BOARD_GOOGLE_KANO
 	bool "->  Kano"
 
+config BOARD_GOOGLE_KALADIN
+	bool "->  Kaladin"
+
 config BOARD_GOOGLE_KINOX
 	bool "->  Kinox"
 
diff --git a/src/mainboard/google/brya/variants/kaladin/Makefile.mk b/src/mainboard/google/brya/variants/kaladin/Makefile.mk
new file mode 100644
index 0000000000..cc61780e02
--- /dev/null
+++ b/src/mainboard/google/brya/variants/kaladin/Makefile.mk
@@ -0,0 +1,7 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
+bootblock-y += gpio.c
+romstage-y += gpio.c
+romstage-y += memory.c
+ramstage-y += gpio.c
+ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_HDA_VERB) += hda_verb.c
diff --git a/src/mainboard/google/brya/variants/kaladin/gpio.c b/src/mainboard/google/brya/variants/kaladin/gpio.c
new file mode 100644
index 0000000000..c43caf380c
--- /dev/null
+++ b/src/mainboard/google/brya/variants/kaladin/gpio.c
@@ -0,0 +1,487 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <variant/gpio.h>
+#include <baseboard/variants.h>
+#include <soc/gpio.h>
+#include <types.h>
+#include <vendorcode/google/chromeos/chromeos.h>
+
+/* Pad configuration in ramstage */
+static const struct pad_config gpio_table[] = {
+	/* A0 thru A4, A9 and A10 come configured out of reset, do not touch */
+	/* A0  : ESPI_IO0 ==> ESPI_SOC_D0_EC */
+	/* A1  : ESPI_IO1 ==> ESPI_SOC_D1_EC */
+	/* A2  : ESPI_IO2 ==> ESPI_SOC_D2_EC */
+	/* A3  : ESPI_IO3 ==> ESPI_SOC_D3_EC */
+	/* A4  : ESPI_CS0# ==> ESPI_SOC_CS_EC_L */
+	/* A5  : ESPI_ALERT0# ==> NC */
+	PAD_NC(GPP_A5, NONE),
+	/* A6  : ESPI_ALERT1# ==> NC */
+	PAD_NC(GPP_A6, NONE),
+	/* A7  : NC */
+	PAD_NC(GPP_A7, NONE),
+	/* A8  : GPP_A8 ==> NC */
+	PAD_NC(GPP_A8, NONE),
+	/* A9  : ESPI_CLK ==> ESPI_SOC_CLK */
+	/* A10 : ESPI_RESET# ==> ESPI_SOC_RST_EC_L */
+	/* A11 : SSD_PERST_L */
+	PAD_CFG_GPO(GPP_A11, 1, DEEP),
+	/* A12 : NC */
+	PAD_NC(GPP_A12, NONE),
+	/* A13 : GPP_A13 ==> GSC_SOC_INT_ODL */
+	PAD_CFG_GPI_APIC(GPP_A13, NONE, PLTRST, LEVEL, INVERT),
+	/* A14 : USB_A0_FAULT_ODL */
+	PAD_CFG_NF(GPP_A14, NONE, DEEP, NF1),
+	/* A15 : NC */
+	PAD_NC(GPP_A15, NONE),
+	/* A16 : USB_OC3# */
+	PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1),
+	/* A17 : NC */
+	PAD_NC(GPP_A17, NONE),
+	/* A18 : NC */
+	PAD_NC(GPP_A18, NONE),
+	/* A19 : NC */
+	PAD_NC(GPP_A19, NONE),
+	/* A20 : NC */
+	PAD_NC(GPP_A20, NONE),
+	/* A21 : USB_C1_AUX_DC_P */
+	PAD_CFG_NF(GPP_A21, NONE, DEEP, NF6),
+	/* A22 : USB_C1_AUX_DC_N */
+	PAD_CFG_NF(GPP_A22, NONE, DEEP, NF6),
+	/* A23 : GPP_A23 ==> NC */
+	PAD_NC(GPP_A23, NONE),
+
+	/* B0  : VCCIN_AUX_VID0 */
+	PAD_CFG_NF(GPP_B0, NONE, DEEP, NF1),
+	/* B1  : VCCIN_AUX_VID1 */
+	PAD_CFG_NF(GPP_B1, NONE, DEEP, NF1),
+	/* B2  : NC */
+	PAD_NC(GPP_B2, NONE),
+	/* B3  : IMU_INT_L */
+	PAD_CFG_GPI_APIC(GPP_B3, NONE, PWROK, LEVEL, INVERT),
+	/* B4  : ACC_INT_L */
+	PAD_CFG_GPI_APIC(GPP_B4, NONE, PWROK, LEVEL, INVERT),
+	/* B5  : GPP_B5 ==> ISH_I2C0_SENSOR_SDA */
+	PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_B5, NONE, DEEP, NF1),
+	/* B6  : GPP_B6 ==> ISH_I2C0_SENSOR_SCL */
+	PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_B6, NONE, DEEP, NF1),
+	/* B7  : I2C3_SDA ==> NC */
+	PAD_NC(GPP_B7, NONE),
+	/* B8  : I2C3_SCL ==> NC */
+	PAD_NC(GPP_B8, NONE),
+	/* B9  : Not available */
+	PAD_NC(GPP_B9, NONE),
+	/* B10 : Not available */
+	PAD_NC(GPP_B10, NONE),
+	/* B11 : SOC_PD0_INT# */
+	PAD_CFG_NF(GPP_B11, NONE, DEEP, NF1),
+	/* B12 : SLP_S0# ==> PM_SLP_S0# */
+	PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1),
+	/* B13 : PLTRST# ==> PLT_RST_L */
+	PAD_CFG_NF_LOCK(GPP_B13, NONE, NF1, LOCK_CONFIG),
+	/* B14 : GPP_B14_STRAP */
+	PAD_NC(GPP_B14, NONE),
+	/* B15 : NC */
+	PAD_NC_LOCK(GPP_B15, NONE, LOCK_CONFIG),
+	/* B16  : GPP_B16 ==> I2C_TOUCHPAD_SDA */
+	PAD_CFG_NF_LOCK(GPP_B16, NONE, NF2, LOCK_CONFIG),
+	/* B17  : GPP_B17 ==> I2C_TOUCHPAD_SCL */
+	PAD_CFG_NF_LOCK(GPP_B17, NONE, NF2, LOCK_CONFIG),
+	/* B18 : GPP_B18 ==> GPP_B18_STRAP */
+	PAD_NC(GPP_B18, NONE),
+	/* B19 : Not available */
+	PAD_NC(GPP_B19, NONE),
+	/* B20 : Not available */
+	PAD_NC(GPP_B20, NONE),
+	/* B21 : Not available */
+	PAD_NC(GPP_B21, NONE),
+	/* B22 : Not available */
+	PAD_NC(GPP_B22, NONE),
+	/* B23 : SML1ALERT# ==> PCHHOT_ODL_STRAP */
+	PAD_NC(GPP_B23, NONE),
+
+	/* C0  : SMBCLK ==> EN_PP3300_TCHSCR_X */
+	PAD_CFG_GPO(GPP_C0, 1, DEEP),
+	/* C1  : SMBDATA ==> TCHSCR_RST_L */
+	PAD_CFG_GPO(GPP_C1, 1, DEEP),
+	/* C2  : SMBALERT# ==> GPP_C2_STRAP */
+	PAD_NC(GPP_C2, NONE),
+	/* C3  : EN_PP3300_UCAM_X */
+	PAD_CFG_GPO_LOCK(GPP_C3, 1, LOCK_CONFIG),
+	/* C4  : TCHSCR_REPORT_EN */
+	PAD_CFG_GPO(GPP_C4, 0, DEEP),
+	/* C5  : SML0ALERT# ==> GPP_C5_STRAP */
+	PAD_NC(GPP_C5, NONE),
+	/* C6  : I2C_SOC_PMC_PD_SCL */
+	PAD_CFG_NF(GPP_C6, NONE, DEEP, NF1),
+	/* C7  : I2C_SOC_PMC_PD_SDA */
+	PAD_CFG_NF(GPP_C7, NONE, DEEP, NF1),
+
+	/* D0  : SEN_MODE2_EC_PCH_INT_ODL */
+	PAD_CFG_NF(GPP_D0, NONE, DEEP, NF1),
+	/* D1  : ISH_GP1 ==> SEN_MODE2_EC_ISH_INT_ODL */
+	PAD_CFG_NF(GPP_D1, NONE, DEEP, NF1),
+	/* D2  : NC */
+	PAD_NC_LOCK(GPP_D2, NONE, LOCK_CONFIG),
+	/* D3  : ISH_GP3 ==> NC */
+	PAD_NC_LOCK(GPP_D3, NONE, LOCK_CONFIG),
+	/* D4  : IMGCLKOUT0 ==> BT_DISABLE_L */
+	PAD_CFG_GPO(GPP_D4, 1, DEEP),
+	/* D5  : SSD_CLKREQ_ODL */
+	PAD_CFG_NF(GPP_D5, NONE, DEEP, NF1),
+	/* D6  : SRCCLKREQ1# ==> NC */
+	PAD_NC_LOCK(GPP_D6, NONE, LOCK_CONFIG),
+	/* D7  : SRCCLKREQ2# ==> WLAN_CLKREQ_ODL */
+	PAD_CFG_NF(GPP_D7, NONE, DEEP, NF1),
+	/* D8  : SRCCLKREQ3# ==> NC */
+	PAD_NC_LOCK(GPP_D8, NONE, LOCK_CONFIG),
+	/* D9  : NC */
+	PAD_NC_LOCK(GPP_D9, NONE, LOCK_CONFIG),
+	/* D10 : ISH_SPI_CLK ==> GPP_D10_STRAP */
+	PAD_NC_LOCK(GPP_D10, NONE, LOCK_CONFIG),
+	/* D11 : NC */
+	PAD_NC_LOCK(GPP_D11, NONE, LOCK_CONFIG),
+	/* D12 : ISH_SPI_MOSI ==> GPP_D12_STRAP */
+	PAD_NC_LOCK(GPP_D12, NONE, LOCK_CONFIG),
+	/* D13 : UART0_ISH_RX_DBG_TX */
+	PAD_CFG_NF(GPP_D13, NONE, DEEP, NF1),
+	/* D14 : UART0_ISH_TX_DBG_RX */
+	PAD_CFG_NF(GPP_D14, NONE, DEEP, NF1),
+	/* D15 : ISH_UART0_RTS# ==> NC */
+	PAD_NC_LOCK(GPP_D15, NONE, LOCK_CONFIG),
+	/* D16 : ISH_UART0_CTS# ==> NC */
+	PAD_NC_LOCK(GPP_D16, NONE, LOCK_CONFIG),
+	/* D17 : NC */
+	PAD_NC_LOCK(GPP_D17, NONE, LOCK_CONFIG),
+	/* D18 : NC */
+	PAD_NC_LOCK(GPP_D18, NONE, LOCK_CONFIG),
+	/* D19 : I2S_MCLK1_OUT ==> CPUID */
+	PAD_CFG_GPI(GPP_D19, NONE, DEEP),
+
+	/* E0  : NC */
+	PAD_NC_LOCK(GPP_E0, NONE, LOCK_CONFIG),
+	/* E1  : THC0_SPI1_IO2 ==> MEM_STRAP_0 */
+	PAD_CFG_GPI_LOCK(GPP_E1, NONE, LOCK_CONFIG),
+	/* E2  : THC0_SPI1_IO3 ==> MEM_STRAP_1 */
+	PAD_CFG_GPI_LOCK(GPP_E2, NONE, LOCK_CONFIG),
+	/* E3  : PROC_GP0 ==> MEM_STRAP_2 */
+	PAD_CFG_GPI(GPP_E3, NONE, DEEP),
+	/* E4  : NC */
+	PAD_NC(GPP_E4, NONE),
+	/* E5  : NC */
+	PAD_NC(GPP_E5, NONE),
+	/* E6  : THC0_SPI1_RST# ==> GPP_E6_STRAP */
+	PAD_NC_LOCK(GPP_E6, NONE, LOCK_CONFIG),
+	/* E7  : NC */
+	PAD_NC(GPP_E7, NONE),
+	/* E8  : GPP_E8 ==> WLAN_DISABLE_L */
+	PAD_CFG_GPO(GPP_E8, 1, DEEP),
+	/* E9  : SOC_USB_OC0 */
+	PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1),
+	/* E10 : EN_PP3300_WLAN_X */
+	PAD_CFG_GPO(GPP_E10, 1, DEEP),
+	/* E11 : TCHSCR_INT_ODL */
+	PAD_CFG_GPI_APIC(GPP_E11, NONE, PLTRST, LEVEL, INVERT),
+	/* E12 : THC0_SPI1_IO1 ==> SOC_WP_OD */
+	PAD_CFG_GPI_GPIO_DRIVER_LOCK(GPP_E12, NONE, LOCK_CONFIG),
+	/* E13 : THC0_SPI1_IO0 ==> NC*/
+	PAD_NC_LOCK(GPP_E13, NONE, LOCK_CONFIG),
+	/* E14 : DDSP_HPDA ==> EDP_HPD */
+	PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1),
+	/* E15 : NC */
+	PAD_NC(GPP_E15, NONE),
+	/* E16 : NC */
+	PAD_NC(GPP_E16, NONE),
+	/* E17  : MEM_STRAP_3 */
+	PAD_CFG_GPI_LOCK(GPP_E17, NONE, LOCK_CONFIG),
+	/* E18 : NC */
+	PAD_NC(GPP_E18, NONE),
+	/* E19 : DDP1_CTRLDATA ==> GPP_E19_STRAP */
+	PAD_NC(GPP_E19, NONE),
+	/* E20 : DDP2_CTRLCLK ==> NC */
+	PAD_NC(GPP_E20, NONE),
+	/* E21 : DDP2_CTRLDATA ==> NC */
+	PAD_NC(GPP_E21, NONE),
+	/* E22 : DDPA_CTRLCLK ==> USB_C0_AUX_DC_P */
+	PAD_CFG_NF(GPP_E22, NONE, DEEP, NF6),
+	/* E23 : DDPA_CTRLDATA ==> USB_C0_AUX_DC_N */
+	PAD_CFG_NF(GPP_E23, NONE, DEEP, NF6),
+
+	/* F0  : CNV_BRI_DT ==> CNV_BRI_DT_STRAP */
+	PAD_CFG_NF(GPP_F0, NONE, DEEP, NF1),
+	/* F1  : CNV_BRI_RSP ==> CNV_BRI_RSP */
+	PAD_CFG_NF(GPP_F1, UP_20K, DEEP, NF1),
+	/* F2  : CNV_RGI_DT ==> CNV_RGI_DT_STRAP */
+	PAD_CFG_NF(GPP_F2, NONE, DEEP, NF1),
+	/* F3  : CNV_RGI_RSP ==> CNV_RGI_RSP */
+	PAD_CFG_NF(GPP_F3, UP_20K, DEEP, NF1),
+	/* F4  : CNV_RF_RESET# ==> CNV_RF_RST_L */
+	PAD_CFG_NF(GPP_F4, NONE, DEEP, NF1),
+	/* F5  : CRF_XTAL_CLKREQ ==> CNV_CLKREQ0 */
+	PAD_CFG_NF(GPP_F5, NONE, DEEP, NF3),
+	/* F6  : CNV_PA_BLANKING ==> NC */
+	PAD_NC(GPP_F6, NONE),
+	/* F7  : GPP_F7 ==> GPP_F7_STRAP */
+	PAD_NC(GPP_F7, NONE),
+	/* F8  : Not available */
+	PAD_NC(GPP_F8, NONE),
+	/* F9  : Not available */
+	PAD_NC(GPP_F9, NONE),
+	/* F10 : GPP_F10 ==> GPP_F10_STRAP */
+	PAD_NC(GPP_F10, NONE),
+	/* F11 : NC */
+	PAD_NC_LOCK(GPP_F11, NONE, LOCK_CONFIG),
+	/* F12 : NC */
+	PAD_NC_LOCK(GPP_F12, NONE, LOCK_CONFIG),
+	/* F13 : NC */
+	PAD_NC(GPP_F13, NONE),
+	/* F14 : GSXDIN ==> TCHPAD_INT_ODL */
+	PAD_CFG_GPI_IRQ_WAKE(GPP_F14, NONE, PWROK, LEVEL, INVERT),
+	/* F15 : NC */
+	PAD_NC_LOCK(GPP_F15, NONE, LOCK_CONFIG),
+	/* F16 : NC */
+	PAD_NC_LOCK(GPP_F16, NONE, LOCK_CONFIG),
+	/* F17 : THC1_SPI2_RST# ==> EC_SOC_WAKE_ODL */
+	PAD_CFG_GPI_IRQ_WAKE_LOCK(GPP_F17, NONE, EDGE_SINGLE, INVERT, LOCK_CONFIG),
+	/* F18 : THC1_SPI2_INT# ==> NC */
+	PAD_NC(GPP_F18, NONE),
+	/* F19 : Not available */
+	PAD_NC(GPP_F19, NONE),
+	/* F20 : Not available */
+	PAD_NC(GPP_F20, NONE),
+	/* F21 : Not available */
+	PAD_NC(GPP_F21, NONE),
+	/* F22 : NC */
+	PAD_NC(GPP_F22, NONE),
+	/* F23 : V1P05_CTRL ==> V1P05EXT_CTRL */
+	PAD_CFG_NF(GPP_F23, NONE, DEEP, NF1),
+
+	/* H0  : GPP_H0_STRAP */
+	PAD_NC(GPP_H0, NONE),
+	/* H1  : GPP_H1_STRAP */
+	PAD_NC(GPP_H1, NONE),
+	/* H2  : GPP_H2_STRAP */
+	PAD_NC(GPP_H2, NONE),
+	/* H3  : SX_EXIT_HOLDOFF# ==> WLAN_PCIE_WAKE_ODL */
+	PAD_CFG_GPI_SCI_LOW_LOCK(GPP_H3, NONE, EDGE_SINGLE, LOCK_CONFIG),
+	/* H4  : I2C0_SDA ==> SOC_I2C_GSC_SDA */
+	PAD_CFG_NF_LOCK(GPP_H4, NONE, NF1, LOCK_CONFIG),
+	/* H5  : I2C0_SCL ==> SOC_I2C_GSC_SCL */
+	PAD_CFG_NF_LOCK(GPP_H5, NONE, NF1, LOCK_CONFIG),
+	/* H6  : I2C1_SDA ==> SOC_I2C_TCHSCR_SDA */
+	PAD_CFG_NF(GPP_H6, NONE, DEEP, NF1),
+	/* H7  : I2C1_SCL ==> SOC_I2C_TCHSCR_SCL */
+	PAD_CFG_NF(GPP_H7, NONE, DEEP, NF1),
+	/* H8  : NC */
+	PAD_NC(GPP_H8, NONE),
+	/* H9  : NC */
+	PAD_NC(GPP_H9, NONE),
+	/* H10 : UART0_RXD ==> UART_SOC_RX_DBG_TX */
+	PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2),
+	/* H11 : UART0_TXD ==> UART_SOC_TX_DBG_RX */
+	PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2),
+	/* H12 : GPP_H12 ==> NC */
+	PAD_NC_LOCK(GPP_H12, NONE, LOCK_CONFIG),
+	/* H13 : GPP_H13 ==> NC */
+	PAD_NC_LOCK(GPP_H13, NONE, LOCK_CONFIG),
+	/* H14 : Not available */
+	PAD_NC(GPP_H14, NONE),
+	/* H15  : DDPB_CTRLCLK ==> NC */
+	PAD_NC_LOCK(GPP_H15, NONE, LOCK_CONFIG),
+	/* H16 : Not available */
+	PAD_NC(GPP_H16, NONE),
+	/* H17  : DDPB_CTRLDATA ==> PD_SOC_DBG_L */
+	PAD_CFG_NF(GPP_H17, NONE, DEEP, NF1),
+	/* H18 : PROC_C10_GATE# ==> CPU_C10_GATE# */
+	PAD_CFG_NF(GPP_H18, NONE, DEEP, NF1),
+	/* H19 : SOC_I2C_SUB_INT_ODL */
+	PAD_NC(GPP_H19, NONE),
+	/* H20 : IMGCLKOUT1 ==> WLAN_PERST_L */
+	PAD_CFG_GPO(GPP_H20, 1, DEEP),
+	/* H21 : NC */
+	PAD_NC(GPP_H21, NONE),
+	/* H22 : IMGCLKOUT3 ==> NC */
+	PAD_NC(GPP_H22, NONE),
+	/* H23 : GPP_H23 ==> X360_CS_SKU_ID */
+	PAD_CFG_GPI(GPP_H23, NONE, DEEP),
+
+	/* R0  : HDA_BCLK ==> HDA_HP_BCLK */
+	PAD_CFG_NF(GPP_R0, NONE, DEEP, NF1),
+	/* R1  : HDA_SYNC ==> HDA_HP_SYNC */
+	PAD_CFG_NF(GPP_R1, NONE, DEEP, NF1),
+	/* R2 : HDA_SDO ==> HDA_HP_SDO */
+	PAD_CFG_NF(GPP_R2, NONE, DEEP, NF1),
+	/* R3 : HDA_SDI0 ==> HDA_HP_SDIN0_R */
+	PAD_CFG_NF(GPP_R3, NONE, DEEP, NF1),
+	/* R4 : HDA_RST# ==> DMIC_UCAM_CLK */
+	PAD_CFG_NF(GPP_R4, NONE, DEEP, NF3),
+	/* R5 : HDA_SDI1 ==> DMIC_UCAM_DATA */
+	PAD_CFG_NF(GPP_R5, NONE, DEEP, NF3),
+	/* R6 : DMIC_CLK_A_1A ==> NC */
+	PAD_NC(GPP_R6, NONE),
+	/* R7 : DMIC_DATA_1A ==> NC */
+	PAD_NC(GPP_R7, NONE),
+
+	/* S0  : I2S_SPK_BCLK_R ==> NC */
+	PAD_NC(GPP_S0, NONE),
+	/* S1  : I2S_SPK_LRCK_R ==> NC */
+	PAD_NC(GPP_S1, NONE),
+	/* S2 : DMIC_CKL_A0 ==> NC */
+	PAD_NC(GPP_S2, NONE),
+	/* S3 : DMIC_DATA0 ==> NC */
+	PAD_NC(GPP_S3, NONE),
+	/* S4  : NC */
+	PAD_NC(GPP_S4, NONE),
+	/* S5  : NC */
+	PAD_NC(GPP_S5, NONE),
+	/* S6  : NC */
+	PAD_NC(GPP_S6, NONE),
+	/* S7  : NC */
+	PAD_NC(GPP_S7, NONE),
+
+	/* I5  : NC */
+	PAD_NC(GPP_I5, NONE),
+	/* I7  : EMMC_CMD */
+	PAD_CFG_NF(GPP_I7, NONE, DEEP, NF1),
+	/* I8  : EMMC_DATA0 */
+	PAD_CFG_NF(GPP_I8, NONE, DEEP, NF1),
+	/* I9  : EMMC_DATA1 */
+	PAD_CFG_NF(GPP_I9, NONE, DEEP, NF1),
+	/* I10 : EMMC_DATA2 */
+	PAD_CFG_NF(GPP_I10, NONE, DEEP, NF1),
+	/* I11 : EMMC_DATA3 */
+	PAD_CFG_NF(GPP_I11, NONE, DEEP, NF1),
+	/* I12 : EMMC_DATA4 */
+	PAD_CFG_NF(GPP_I12, NONE, DEEP, NF1),
+	/* I13 : EMMC_DATA5 */
+	PAD_CFG_NF(GPP_I13, NONE, DEEP, NF1),
+	/* I14 : EMMC_DATA6 */
+	PAD_CFG_NF(GPP_I14, NONE, DEEP, NF1),
+	/* I15 : EMMC_DATA7 */
+	PAD_CFG_NF(GPP_I15, NONE, DEEP, NF1),
+	/* I16 : EMMC_RCLK */
+	PAD_CFG_NF(GPP_I16, NONE, DEEP, NF1),
+	/* I17 : EMMC_CLK */
+	PAD_CFG_NF(GPP_I17, NONE, DEEP, NF1),
+	/* I18 : EMMC_RESET# */
+	PAD_CFG_NF(GPP_I18, NONE, DEEP, NF1),
+
+	/* GPD0  : BATLOW# ==> SOC_BATLOW_L */
+	PAD_CFG_NF(GPD0, NONE, DEEP, NF1),
+	/* GPD1  : ACPRESENT ==> SOC_ACPRESENT */
+	PAD_CFG_NF(GPD1, NONE, DEEP, NF1),
+	/* GPD2  : EC_SOC_INT_ODL */
+	PAD_CFG_GPI_APIC(GPD2, NONE, PLTRST, LEVEL, INVERT),
+	/* GPD3  : PWRBTN# ==> EC_SOC_PWR_BTN_ODL */
+	PAD_CFG_NF(GPD3, NONE, DEEP, NF1),
+	/* GPD4  : SLP_S3# ==> SLP_S3_L */
+	PAD_CFG_NF(GPD4, NONE, DEEP, NF1),
+	/* GPD5  : SLP_S4# ==> SLP_S4_L */
+	PAD_CFG_NF(GPD5, NONE, DEEP, NF1),
+	/* GPD6  : SLP_A# ==> NC */
+	PAD_NC(GPD6, NONE),
+	/* GPD7  : GPD7_STRAP */
+	PAD_NC(GPD7, NONE),
+	/* GPD8  : SUSCLK ==> PCH_SUSCLK */
+	PAD_CFG_NF(GPD8, NONE, DEEP, NF1),
+	/* GPD9  : NC */
+	PAD_NC(GPD9, NONE),
+	/* GPD10 : SLP_S5# ==> NC */
+	PAD_NC(GPD10, NONE),
+	/* GPD11 : NC */
+	PAD_NC(GPD11, NONE),
+
+	/* Configure the unused virtual CNVi Bluetooth UART pads to NC mode. */
+	/* vCNV_BT_UART_TXD */
+	PAD_NC(GPP_VGPIO_6, NONE),
+	/* vCNV_BT_UART_RXD */
+	PAD_NC(GPP_VGPIO_7, NONE),
+	/* vCNV_BT_UART_CTS_B */
+	PAD_NC(GPP_VGPIO_8, NONE),
+	/* vCNV_BT_UART_RTS_B */
+	PAD_NC(GPP_VGPIO_9, NONE),
+
+	/* Configure the unused vUART for Bluetooth pads to NC mode. */
+	/* vUART0_TXD */
+	PAD_NC(GPP_VGPIO_18, NONE),
+	/* vUART0_RXD */
+	PAD_NC(GPP_VGPIO_19, NONE),
+	/* vUART0_CTS_B */
+	PAD_NC(GPP_VGPIO_20, NONE),
+	/* vUART0_RTS_B */
+	PAD_NC(GPP_VGPIO_21, NONE),
+
+	/* Configure the virtual CNVi Bluetooth I2S GPIO Pads.*/
+	/* BT_I2S_BCLK */
+	PAD_CFG_NF(GPP_VGPIO_30, NONE, DEEP, NF3),
+	/* BT_I2S_SYNC */
+	PAD_CFG_NF(GPP_VGPIO_31, NONE, DEEP, NF3),
+	/* BT_I2S_SDO */
+	PAD_CFG_NF(GPP_VGPIO_32, NONE, DEEP, NF3),
+	/* BT_I2S_SDI */
+	PAD_CFG_NF(GPP_VGPIO_33, NONE, DEEP, NF3),
+	/* SSP2_SCLK */
+	PAD_CFG_NF(GPP_VGPIO_34, NONE, DEEP, NF1),
+	/* SSP2_SFRM */
+	PAD_CFG_NF(GPP_VGPIO_35, NONE, DEEP, NF1),
+	/* SSP_TXD */
+	PAD_CFG_NF(GPP_VGPIO_36, NONE, DEEP, NF1),
+	/* SSP_RXD */
+	PAD_CFG_NF(GPP_VGPIO_37, NONE, DEEP, NF1),
+};
+
+/* Early pad configuration in bootblock */
+static const struct pad_config early_gpio_table[] = {
+	/* C0  : SMBCLK ==> EN_PP3300_TCHSCR_X */
+	PAD_CFG_GPO(GPP_C0, 1, DEEP),
+	/* C1  : SMBDATA ==> TCHSCR_RST_L */
+	PAD_CFG_GPO(GPP_C1, 1, DEEP),
+	/* A13 : GPP_A13 ==> GSC_SOC_INT_ODL */
+	PAD_CFG_GPI_APIC(GPP_A13, NONE, PLTRST, LEVEL, INVERT),
+	/* E12 : THC0_SPI1_IO1 ==> SOC_WP_OD */
+	PAD_CFG_GPI_GPIO_DRIVER(GPP_E12, NONE, DEEP),
+	/* H4  : I2C0_SDA ==> SOC_I2C_GSC_SDA */
+	PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1),
+	/* H5  : I2C0_SCL ==> SOC_I2C_GSC_SCL */
+	PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1),
+	/* H10 : UART0_RXD ==> UART_SOC_RX_DBG_TX */
+	PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2),
+	/* H11 : UART0_TXD ==> UART_SOC_TX_DBG_RX */
+	PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2),
+	/* H20 : IMGCLKOUT1 ==> WLAN_PERST_L */
+	PAD_CFG_GPO(GPP_H20, 0, DEEP),
+};
+
+/* Fill romstage gpio configuration */
+static const struct pad_config romstage_gpio_table[] = {
+};
+
+const struct pad_config *variant_gpio_table(size_t *num)
+{
+	*num = ARRAY_SIZE(gpio_table);
+	return gpio_table;
+}
+
+const struct pad_config *variant_gpio_override_table(size_t *num)
+{
+	*num = 0;
+	return NULL;
+}
+
+const struct pad_config *variant_early_gpio_table(size_t *num)
+{
+	*num = ARRAY_SIZE(early_gpio_table);
+	return early_gpio_table;
+}
+
+static const struct cros_gpio cros_gpios[] = {
+	CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME),
+	CROS_GPIO_WP_AH(GPIO_PCH_WP, CROS_GPIO_DEVICE_NAME),
+};
+DECLARE_CROS_GPIOS(cros_gpios);
+
+const struct pad_config *variant_romstage_gpio_table(size_t *num)
+{
+	*num = ARRAY_SIZE(romstage_gpio_table);
+	return romstage_gpio_table;
+}
diff --git a/src/mainboard/google/brya/variants/kaladin/hda_verb.c b/src/mainboard/google/brya/variants/kaladin/hda_verb.c
new file mode 100644
index 0000000000..d2b9f33f7a
--- /dev/null
+++ b/src/mainboard/google/brya/variants/kaladin/hda_verb.c
@@ -0,0 +1,118 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <device/azalia_device.h>
+
+const u32 cim_verb_data[] = {
+	/* coreboot specific header */
+	0x10ec0236,	// Codec Vendor / Device ID: Realtek ALC236
+	0x103C8C60,	// Subsystem ID
+	0x00000017,	// Number of jacks (NID entries)
+
+	AZALIA_RESET(0x1),
+	/* NID 0x01, HDA Codec Subsystem ID Verb table */
+	AZALIA_SUBVENDOR(0, 0x103C8C60),
+
+	/* Pin Widget Verb Table */
+
+	/*
+	 * DMIC
+	 * Requirement is to use PCH DMIC. Hence,
+	 * commented out codec's Internal DMIC.
+	 * AZALIA_PIN_CFG(0, 0x12, 0x90A60130),
+	 * AZALIA_PIN_CFG(0, 0x13, 0x40000000),
+	 */
+
+	/* Pin widget 0x14 - Front (Port-D) */
+	AZALIA_PIN_CFG(0, 0x14, 0x90170110),
+	/* Pin widget 0x18 - NPC */
+	AZALIA_PIN_CFG(0, 0x18, 0x411111F0),
+	/* Pin widget 0x19 - MIC2 (Port-F) */
+	AZALIA_PIN_CFG(0, 0x19, 0x03A11020),
+	/* Pin widget 0x1A - LINE1 (Port-C) */
+	AZALIA_PIN_CFG(0, 0x1a, 0x411111F0),
+	/* Pin widget 0x1B - NPC */
+	AZALIA_PIN_CFG(0, 0x1b, 0x411111F0),
+	/* Pin widget 0x1D - BEEP-IN */
+	AZALIA_PIN_CFG(0, 0x1d, 0x40600001),
+	/* Pin widget 0x1E - NPC */
+	AZALIA_PIN_CFG(0, 0x1e, 0x411111F0),
+	/* Pin widget 0x21 - HP1-OUT (Port-I) */
+	AZALIA_PIN_CFG(0, 0x21, 0x03211040),
+
+	/*
+	 * Widget node 0x20 - 1
+	 */
+	0x0205003C,
+	0x02040354,
+	0x0205003C,
+	0x02040314,
+	/*
+	 * Widget node 0x20 - 2
+	 * Set JD2 pull high
+	 */
+	0x0205001B,
+	0x02040A4B,
+	0x0205000B,
+	0x02047778,
+	/*
+	 * Widget node 0x20 - 3
+	 */
+	0x02050046,
+	0x02040004,
+	0x05750003,
+	0x057409A3,
+	/* disable EQ first */
+	0x05350000,
+	0x0534201A,
+	/* Left Channel */
+	0x0535001d,
+	0x05340800,
+	0x0535001e,
+	0x05340800,
+	0x05350003,
+	0x05341F7B,
+	0x05350004,
+	0x05340000,
+	/* Right Channel */
+	0x05450000,
+	0x05442000,
+	0x0545001d,
+	0x05440800,
+	0x0545001e,
+	0x05440800,
+	0x05450003,
+	0x05441F7B,
+	0x05450004,
+	0x05440000,
+	/* enable EQ */
+	0x05350000,
+	0x0534E01A,
+	/* 1.8W/4ohm */
+	0x02050038,
+	0x02047901,
+	/* AGC Enable */
+	0x0205004C,
+	0x0204465C,
+	0x02050016,
+	0x02044E50,
+	0x02050020,
+	0x020451FF,
+	/* Headphone Pop */
+	0x05750007,
+	0x057412B2,
+};
+
+const u32 pc_beep_verbs[] = {
+	/* Dos beep path - 1 */
+	0x02050036,
+	0x02047151,
+	0x02050010,
+	0x02040020,
+	/* Dos beep path - 2 */
+	0x0143B000,
+	0x01470740,
+	0x01470C02,
+	0x01470C02,
+};
+
+AZALIA_ARRAY_SIZES;
diff --git a/src/mainboard/google/brya/variants/kaladin/include/variant/ec.h b/src/mainboard/google/brya/variants/kaladin/include/variant/ec.h
new file mode 100644
index 0000000000..7a2a6ff8b7
--- /dev/null
+++ b/src/mainboard/google/brya/variants/kaladin/include/variant/ec.h
@@ -0,0 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#ifndef __VARIANT_EC_H__
+#define __VARIANT_EC_H__
+
+#include <baseboard/ec.h>
+
+#endif
diff --git a/src/mainboard/google/brya/variants/kaladin/include/variant/gpio.h b/src/mainboard/google/brya/variants/kaladin/include/variant/gpio.h
new file mode 100644
index 0000000000..c4fe342621
--- /dev/null
+++ b/src/mainboard/google/brya/variants/kaladin/include/variant/gpio.h
@@ -0,0 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#ifndef VARIANT_GPIO_H
+#define VARIANT_GPIO_H
+
+#include <baseboard/gpio.h>
+
+#endif
diff --git a/src/mainboard/google/brya/variants/kaladin/memory.c b/src/mainboard/google/brya/variants/kaladin/memory.c
new file mode 100644
index 0000000000..bb80ee15ec
--- /dev/null
+++ b/src/mainboard/google/brya/variants/kaladin/memory.c
@@ -0,0 +1,111 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <baseboard/variants.h>
+#include <gpio.h>
+#include <soc/romstage.h>
+
+static const struct mb_cfg variant_memcfg = {
+	.type = MEM_TYPE_LP5X,
+
+	.rcomp = {
+		/* Baseboard uses only 100ohm Rcomp resistors */
+		.resistor = 100,
+	},
+
+	/* DQ byte map */
+	.lpx_dq_map = {
+		.ddr0 = {
+			.dq0 = { 12,  9, 10, 11, 14, 13,  8, 15 },
+			.dq1 = {  3,  1,  2,  0,  4,  7,  5,  6 },
+		},
+		.ddr1 = {
+			.dq0 = {  3,  1,  2,  0,  4,  7,  5,  6 },
+			.dq1 = { 13,  9,  8, 11, 10, 14, 15, 12 },
+		},
+		.ddr2 = {
+			.dq0 = {  2,  1,  3,  0,  4,  6,  5,  7 },
+			.dq1 = {  8,  9, 10, 11, 13, 14, 12, 15 },
+		},
+		.ddr3 = {
+			.dq0 = {  3,  0,  1,  2,  5,  6,  4,  7 },
+			.dq1 = { 13,  9, 11,  8, 14, 15, 10, 12 },
+		},
+		.ddr4 = {
+			.dq0 = { 12,  9, 10, 11, 14, 13,  8, 15 },
+			.dq1 = {  3,  1,  2,  0,  4,  7,  5,  6 },
+		},
+		.ddr5 = {
+			.dq0 = {  3,  1,  2,  0,  4,  7,  5,  6 },
+			.dq1 = { 13,  9,  8, 11, 10, 14, 15, 12 },
+		},
+		.ddr6 = {
+			.dq0 = {  2,  1,  3,  0,  4,  6,  5,  7 },
+			.dq1 = {  8,  9, 10, 11, 13, 14, 12, 15 },
+		},
+		.ddr7 = {
+			.dq0 = {  3,  0,  1,  2,  5,  6,  4,  7 },
+			.dq1 = { 13,  9, 11,  8, 14, 15, 10, 12 },
+		},
+	},
+
+	/* DQS CPU<>DRAM map */
+	.lpx_dqs_map = {
+		.ddr0 = { .dqs0 = 1, .dqs1 = 0 },
+		.ddr1 = { .dqs0 = 0, .dqs1 = 1 },
+		.ddr2 = { .dqs0 = 0, .dqs1 = 1 },
+		.ddr3 = { .dqs0 = 0, .dqs1 = 1 },
+		.ddr4 = { .dqs0 = 1, .dqs1 = 0 },
+		.ddr5 = { .dqs0 = 0, .dqs1 = 1 },
+		.ddr6 = { .dqs0 = 0, .dqs1 = 1 },
+		.ddr7 = { .dqs0 = 0, .dqs1 = 1 },
+	},
+
+	.lp5x_config = {
+		.ccc_config = 0xff,
+	},
+
+	.ect = 1, /* Early Command Training */
+
+	.UserBd = BOARD_TYPE_MOBILE,
+};
+
+const struct mb_cfg *variant_memory_params(void)
+{
+	return &variant_memcfg;
+}
+
+int variant_memory_sku(void)
+{
+	/*
+	 * Memory configuration board straps
+	 * GPIO_MEM_CONFIG_0	GPP_E1
+	 * GPIO_MEM_CONFIG_1	GPP_E2
+	 * GPIO_MEM_CONFIG_2	GPP_E3
+	 */
+	gpio_t spd_gpios[] = {
+		GPP_E1,
+		GPP_E2,
+		GPP_E3,
+	};
+
+	return gpio_base2_value(spd_gpios, ARRAY_SIZE(spd_gpios));
+}
+
+bool variant_is_half_populated(void)
+{
+	/*
+	 * Ideally half_populated is used in platforms with multiple channels to
+	 * enable only one half of the channel. Alder Lake N has single channel,
+	 * and it would require for new structures to be defined in meminit block
+	 * driver for LPx memory configurations. In order to avoid adding new
+	 * structures, set half_populated to true. This has the same effect as
+	 * having single channel with 64-bit width.
+	*/
+	return true;
+}
+
+void variant_get_spd_info(struct mem_spd *spd_info)
+{
+	spd_info->topo = MEM_TOPO_MEMORY_DOWN;
+	spd_info->cbfs_index = variant_memory_sku();
+}
diff --git a/src/mainboard/google/brya/variants/kaladin/memory/Makefile.mk b/src/mainboard/google/brya/variants/kaladin/memory/Makefile.mk
new file mode 100644
index 0000000000..1b7204365d
--- /dev/null
+++ b/src/mainboard/google/brya/variants/kaladin/memory/Makefile.mk
@@ -0,0 +1,9 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+# This is an auto-generated file. Do not edit!!
+# Generated by:
+# /tmp/go-build1397538409/b001/exe/part_id_gen ADL lp5 src/mainboard/google/brya/variants/kaladin/memory/ src/mainboard/google/brya/variants/kaladin/memory/mem_parts_used.txt
+
+SPD_SOURCES =
+SPD_SOURCES += spd/lp5/set-0/spd-1.hex      # ID = 0(0b0000)  Parts = H9JCNNNBK3MLYR-N6E
+SPD_SOURCES += spd/lp5/set-0/spd-9.hex      # ID = 1(0b0001)  Parts = K3KL6L60GM-MGCT
+SPD_SOURCES += spd/lp5/set-0/spd-7.hex      # ID = 2(0b0010)  Parts = K3KL8L80CM-MGCT
diff --git a/src/mainboard/google/brya/variants/kaladin/memory/dram_id.generated.txt b/src/mainboard/google/brya/variants/kaladin/memory/dram_id.generated.txt
new file mode 100644
index 0000000000..aade5a77ef
--- /dev/null
+++ b/src/mainboard/google/brya/variants/kaladin/memory/dram_id.generated.txt
@@ -0,0 +1,9 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+# This is an auto-generated file. Do not edit!!
+# Generated by:
+# /tmp/go-build1397538409/b001/exe/part_id_gen ADL lp5 src/mainboard/google/brya/variants/kaladin/memory/ src/mainboard/google/brya/variants/kaladin/memory/mem_parts_used.txt
+
+DRAM Part Name                 ID to assign
+H9JCNNNBK3MLYR-N6E             0 (0000)
+K3KL6L60GM-MGCT                1 (0001)
+K3KL8L80CM-MGCT                2 (0010)
diff --git a/src/mainboard/google/brya/variants/kaladin/memory/mem_parts_used.txt b/src/mainboard/google/brya/variants/kaladin/memory/mem_parts_used.txt
new file mode 100644
index 0000000000..e6fb0b2562
--- /dev/null
+++ b/src/mainboard/google/brya/variants/kaladin/memory/mem_parts_used.txt
@@ -0,0 +1,14 @@
+# This is a CSV file containing a list of memory parts used by this variant.
+# One part per line with an optional fixed ID in column 2.
+# Only include a fixed ID if it is required for legacy reasons!
+# Generated IDs are dependent on the order of parts in this file,
+# so new parts must always be added at the end of the file!
+#
+# Generate an updated Makefile.mk and dram_id.generated.txt by running the
+# part_id_gen tool from util/spd_tools.
+# See util/spd_tools/README.md for more details and instructions.
+
+# Part Name
+H9JCNNNBK3MLYR-N6E
+K3KL6L60GM-MGCT
+K3KL8L80CM-MGCT
diff --git a/src/mainboard/google/brya/variants/kaladin/overridetree.cb b/src/mainboard/google/brya/variants/kaladin/overridetree.cb
new file mode 100644
index 0000000000..4e97a62f6a
--- /dev/null
+++ b/src/mainboard/google/brya/variants/kaladin/overridetree.cb
@@ -0,0 +1,473 @@
+fw_config
+	field THERMAL_SOLUTION 1 1
+		option THERMAL_SOLUTION_6W	0
+		option THERMAL_SOLUTION_15W	1
+	end
+	field STORAGE 30 31
+		option STORAGE_EMMC		0
+		option STORAGE_NVME		1
+		option STORAGE_UFS		2
+		option STORAGE_UNKNOWN		3
+	end
+end
+
+chip soc/intel/alderlake
+	register "sagv" = "SaGv_Enabled"
+
+	# GPE configuration
+	register "pmc_gpe0_dw0" = "GPP_A"
+	register "pmc_gpe0_dw1" = "GPP_H"
+	register "pmc_gpe0_dw2" = "GPP_F"
+
+	# S0ix enable
+	register "s0ix_enable" = "true"
+
+	# DPTF enable
+	register "dptf_enable" = "true"
+
+	register "tcc_offset" = "10"     # TCC of 90
+
+	# Enable CNVi BT
+	register "cnvi_bt_core" = "true"
+
+	# eMMC HS400
+	register "emmc_enable_hs400_mode" = "true"
+
+	register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC_SKIP)"	# Type-C MB (7.5 inch)
+	register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC_SKIP)"	# Type-C DB (7.1 inch)
+	register "usb2_ports[2]" = "USB2_PORT_MID(OC1)"		# Type-A MB (6.4 inch)
+	register "usb2_ports[5]" = "USB2_PORT_SHORT(OC_SKIP)"	# UFC (3.7 inch)
+	register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)"	# Bluetooth port for PCIe WLAN (2.5 inch)
+	register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)"	# Bluetooth port for CNVi WLAN
+
+	register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC1)"	# USB3 Type-A port A0(MLB))
+
+	register "tcss_ports[0]" = "TCSS_PORT_DEFAULT(OC_SKIP)"
+	register "tcss_ports[1]" = "TCSS_PORT_DEFAULT(OC_SKIP)"
+
+	# SOC Aux orientation override:
+	# This is a bitfield that corresponds to up to 4 TCSS ports.
+	# Bits (0,1) allocated for TCSS Port1 configuration and Bits (2,3)for TCSS Port2.
+	# TcssAuxOri = 0101b
+	# Bit0,Bit2 set to "1" indicates no retimer on USBC Ports
+	# Bit1,Bit3 set to "0" indicates Aux lines are not swapped on the
+	# motherboard to USBC connector
+	register "tcss_aux_ori" = "0"
+
+
+	# HD Audio
+	register "pch_hda_dsp_enable" = "1"
+	register "pch_hda_audio_link_hda_enable" = "1"
+	register "pch_hda_idisp_link_tmode" = "HDA_TMODE_8T"
+	register "pch_hda_idisp_link_frequency" = "HDA_LINKFREQ_96MHZ"
+	register "pch_hda_idisp_codec_enable" = "1"
+
+	# Configure external V1P05/Vnn/VnnSx Rails
+	register "ext_fivr_settings" = "{
+		.configure_ext_fivr = 1,
+		.v1p05_enable_bitmap = FIVR_ENABLE_ALL_SX & ~FIVR_ENABLE_S0,
+		.vnn_enable_bitmap = FIVR_ENABLE_ALL_SX,
+		.vnn_sx_enable_bitmap = FIVR_ENABLE_ALL_SX,
+		.v1p05_supported_voltage_bitmap = FIVR_VOLTAGE_NORMAL,
+		.vnn_supported_voltage_bitmap = FIVR_VOLTAGE_MIN_ACTIVE,
+		.v1p05_voltage_mv = 1050,
+		.vnn_voltage_mv = 780,
+		.vnn_sx_voltage_mv = 1050,
+		.v1p05_icc_max_ma = 500,
+		.vnn_icc_max_ma = 500,
+	}"
+
+	# Enable CNVi BT Audio offload
+	register "cnvi_bt_audio_offload" = "1"
+
+	register "serial_io_i2c_mode" = "{
+		[PchSerialIoIndexI2C0] = PchSerialIoPci,
+		[PchSerialIoIndexI2C1] = PchSerialIoPci,
+		[PchSerialIoIndexI2C2] = PchSerialIoDisabled,
+		[PchSerialIoIndexI2C3] = PchSerialIoDisabled,
+		[PchSerialIoIndexI2C4] = PchSerialIoDisabled,
+		[PchSerialIoIndexI2C5] = PchSerialIoPci,
+	}"
+
+	register "serial_io_gspi_mode" = "{
+		[PchSerialIoIndexGSPI0] = PchSerialIoDisabled,
+		[PchSerialIoIndexGSPI1] = PchSerialIoDisabled,
+	}"
+
+	register "serial_io_uart_mode" = "{
+		[PchSerialIoIndexUART0] = PchSerialIoPci,
+		[PchSerialIoIndexUART1] = PchSerialIoDisabled,
+		[PchSerialIoIndexUART2] = PchSerialIoDisabled,
+	}"
+
+	# FIXME: To be enabled in future based on PNP impact data.
+	# Disable Package C-state demotion for nissa baseboard.
+	register "disable_package_c_state_demotion" = "true"
+
+	# Intel Common SoC Config
+	#+-------------------+---------------------------+
+	#| Field             |  Value                    |
+	#+-------------------+---------------------------+
+	#| I2C0              | TPM. Early init is        |
+	#|                   | required to set up a BAR  |
+	#|                   | for TPM communication     |
+	#| I2C1              | TouchScreen               |
+	#| I2C5              | Trackpad                  |
+	#+-------------------+---------------------------+
+	register "common_soc_config" = "{
+		.i2c[0] = {
+			.early_init = 1,
+			.speed = I2C_SPEED_FAST_PLUS,
+			.speed_config[0] = {
+				.speed = I2C_SPEED_FAST_PLUS,
+				.scl_lcnt = 55,
+				.scl_hcnt = 30,
+				.sda_hold = 7,
+			}
+		},
+		.i2c[1] = {
+			.speed = I2C_SPEED_FAST,
+			.speed_config[0] = {
+				.speed = I2C_SPEED_FAST,
+				.scl_lcnt = 158,
+				.scl_hcnt = 79,
+				.sda_hold = 30,
+			}
+		},
+		.i2c[5] = {
+			.speed = I2C_SPEED_FAST,
+			.speed_config[0] = {
+				.speed = I2C_SPEED_FAST,
+				.scl_lcnt = 158,
+				.scl_hcnt = 79,
+				.sda_hold = 40,
+			}
+		},
+	}"
+
+	device domain 0 on
+		device ref dtt on
+			chip drivers/intel/dptf
+				## sensor information
+				register "options.tsr[0].desc" = ""CPU_VR""
+				register "options.tsr[1].desc" = ""CPU""
+				register "options.tsr[2].desc" = ""Ambient""
+				register "options.tsr[3].desc" = ""Charger""
+				## Passive Policy
+				register "policies.passive" = "{
+					[0] = DPTF_PASSIVE(CPU,         CPU,           85, 4000),
+					[1] = DPTF_PASSIVE(CPU,         TEMP_SENSOR_0, 85, 4000),
+					[2] = DPTF_PASSIVE(CPU,         TEMP_SENSOR_1, 85, 4000),
+					[3] = DPTF_PASSIVE(CPU,         TEMP_SENSOR_2, 85, 4000),
+				}"
+
+				## Critical Policy
+				register "policies.critical" = "{
+					[0] = DPTF_CRITICAL(TEMP_SENSOR_1,     90, SHUTDOWN),
+					[1] = DPTF_CRITICAL(TEMP_SENSOR_2,     90, SHUTDOWN),
+				}"
+
+				register "controls.power_limits" = "{
+					.pl1 = {
+						.min_power = 6000,
+						.max_power = 13000,
+						.time_window_min = 28 * MSECS_PER_SEC,
+						.time_window_max = 32 * MSECS_PER_SEC,
+						.granularity = 200
+					},
+					.pl2 = {
+						.min_power = 25000,
+						.max_power = 25000,
+						.time_window_min = 28 * MSECS_PER_SEC,
+						.time_window_max = 32 * MSECS_PER_SEC,
+						.granularity = 1000
+					}
+				}"
+
+				## Charger Performance Control (Control, mA)
+				register "controls.charger_perf" = "{
+					[0] = { 255, 4700 },
+					[1] = {  40, 2500 },
+					[2] = {  16, 1000 },
+					[3] = {   8,  500 }
+				}"
+
+				device generic 0 on
+					probe THERMAL_SOLUTION THERMAL_SOLUTION_6W
+				end
+			end
+			chip drivers/intel/dptf
+				## sensor information
+				register "options.tsr[0].desc" = ""CPU_VR""
+				register "options.tsr[1].desc" = ""CPU""
+				register "options.tsr[2].desc" = ""Ambient""
+				register "options.tsr[3].desc" = ""Charger""
+
+				## Passive Policy
+				register "policies.passive" = "{
+					[0] = DPTF_PASSIVE(CPU,         CPU,           85, 6000),
+					[1] = DPTF_PASSIVE(CPU,         TEMP_SENSOR_0, 85, 6000),
+					[2] = DPTF_PASSIVE(CPU,         TEMP_SENSOR_1, 85, 6000),
+					[3] = DPTF_PASSIVE(CPU,         TEMP_SENSOR_2, 85, 6000),
+				}"
+
+				## Critical Policy
+				register "policies.critical" = "{
+					[0] = DPTF_CRITICAL(TEMP_SENSOR_1,     90, SHUTDOWN),
+					[1] = DPTF_CRITICAL(TEMP_SENSOR_2,     90, SHUTDOWN),
+				}"
+
+				register "controls.power_limits" = "{
+					.pl1 = {
+						.min_power = 15000,
+						.max_power = 22000,
+						.time_window_min = 28 * MSECS_PER_SEC,
+						.time_window_max = 32 * MSECS_PER_SEC,
+						.granularity = 200
+					},
+					.pl2 = {
+						.min_power = 35000,
+						.max_power = 35000,
+						.time_window_min = 28 * MSECS_PER_SEC,
+						.time_window_max = 32 * MSECS_PER_SEC,
+						.granularity = 1000
+					}
+				}"
+
+				## Charger Performance Control (Control, mA)
+				register "controls.charger_perf" = "{
+					[0] = { 255, 4700 },
+					[1] = {  40, 2500 },
+					[2] = {  16, 1000 },
+					[3] = {   8,  500 }
+				}"
+				device generic 1 on
+					probe THERMAL_SOLUTION THERMAL_SOLUTION_15W
+				end
+			end
+		end
+		device ref igpu on
+			chip drivers/gfx/generic
+				register "device_count" = "4"
+				# DDIA for eDP
+				register "device[0].name" = ""LCD0""
+				# Internal panel on the first port of the graphics chip
+				register "device[0].type" = "panel"
+				# DDIB for HDMI
+				# If HDMI is not enumerated in the kernel, then no GFX device should be added for DDIB
+				register "device[1].name" = ""DD01""
+				# TCP0 (DP-1) for port C0
+				register "device[2].name" = ""DD02""
+				register "device[2].use_pld" = "true"
+				register "device[2].pld" = "ACPI_PLD_TYPE_C(RIGHT, LEFT, ACPI_PLD_GROUP(1, 1))"
+				# TCP1 (DP-2) for port C1
+				register "device[3].name" = ""DD03""
+				register "device[3].use_pld" = "true"
+				register "device[3].pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(2, 1))"
+				device generic 0 on end
+			end
+		end
+		device ref pmc hidden
+			chip drivers/intel/pmc_mux
+				device generic 0 on
+					chip drivers/intel/pmc_mux/conn
+						use usb2_port1 as usb2_port
+						use tcss_usb3_port1 as usb3_port
+						device generic 0 alias conn0 on end
+					end
+					chip drivers/intel/pmc_mux/conn
+						use usb2_port2 as usb2_port
+						use tcss_usb3_port2 as usb3_port
+						device generic 1 alias conn1 on end
+					end
+				end
+			end
+		end
+		device ref tcss_xhci on
+			chip drivers/usb/acpi
+				device ref tcss_root_hub on
+					chip drivers/usb/acpi
+						register "desc" = ""USB3 Type-C Port C0 (MLB)""
+						register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
+						register "use_custom_pld" = "true"
+						register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, LEFT, ACPI_PLD_GROUP(1, 1))"
+						device ref tcss_usb3_port1 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB3 Type-C Port C1 (DB)""
+						register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
+						register "use_custom_pld" = "true"
+						register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(2, 1))"
+						device ref tcss_usb3_port2 on end
+					end
+				end
+			end
+		end
+		device ref xhci on
+			chip drivers/usb/acpi
+				device ref xhci_root_hub on
+					chip drivers/usb/acpi
+						register "desc" = ""USB2 Type-C Port C0 (MLB)""
+						register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
+						register "use_custom_pld" = "true"
+						register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, LEFT, ACPI_PLD_GROUP(1, 1))"
+						device ref usb2_port1 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB2 Type-C Port C1 (DB)""
+						register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
+						register "use_custom_pld" = "true"
+						register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(2, 1))"
+						device ref usb2_port2 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB2 Type-A Port A0 (MLB)""
+						register "type" = "UPC_TYPE_A"
+						register "use_custom_pld" = "true"
+						register "custom_pld" = "ACPI_PLD_TYPE_A(RIGHT, RIGHT, ACPI_PLD_GROUP(3, 1))"
+						device ref usb2_port3 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB2 Camera""
+						register "type" = "UPC_TYPE_INTERNAL"
+						device ref usb2_port6 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""PCIe Bluetooth""
+						register "type" = "UPC_TYPE_INTERNAL"
+						register "reset_gpio" =	"ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D4)"
+						device ref usb2_port8 on
+						end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""CNVi Bluetooth""
+						register "type" = "UPC_TYPE_INTERNAL"
+						register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D4)"
+						device ref usb2_port10 on
+						end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB3 Type-A Port A0 (MLB)""
+						register "type" = "UPC_TYPE_USB3_A"
+						register "use_custom_pld" = "true"
+						register "custom_pld" = "ACPI_PLD_TYPE_A(RIGHT, RIGHT, ACPI_PLD_GROUP(3, 1))"
+						device ref usb3_port1 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB3 WLAN""
+						register "type" = "UPC_TYPE_INTERNAL"
+						device ref usb3_port4 on end
+					end
+				end
+			end
+		end
+		device ref shared_sram on end
+		device ref cnvi_wifi on
+			chip drivers/wifi/generic
+				register "wake" = "GPE0_PME_B0"
+				register "enable_cnvi_ddr_rfim" = "true"
+				register "add_acpi_dma_property" = "true"
+				device generic 0 on end
+			end
+		end
+		device ref emmc on end
+		device ref pcie_rp4 on
+			# PCIe 4 WLAN
+			register "pch_pcie_rp[PCH_RP(4)]" = "{
+				.clk_src = 2,
+				.clk_req = 2,
+				.flags = PCIE_RP_LTR | PCIE_RP_AER,
+			}"
+			chip drivers/wifi/generic
+				register "wake" = "GPE0_DW1_03"
+				register "add_acpi_dma_property" = "true"
+				device pci 00.0 on end
+			end
+			chip soc/intel/common/block/pcie/rtd3
+				# # enable_gpio is controlled by the EC with EC_EN_PP3300_WLAN
+				register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E10)"
+				register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_H20)"
+				register "srcclk_pin" = "2"
+				device generic 0 on end
+			end
+		end
+		device ref pcie_rp11 on
+			# Enable NVMe SSD PCIE 11-12 using CLK 0
+			register "pch_pcie_rp[PCH_RP(11)]" = "{
+				.clk_src = 0,
+				.clk_req = 0,
+				.flags = PCIE_RP_LTR | PCIE_RP_AER,
+			}"
+		end
+
+		device ref i2c0 on
+			chip drivers/i2c/tpm
+				register "hid" = ""GOOG0005""
+				register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_A13_IRQ)"
+				device i2c 50 on end
+			end
+		end #I2C0
+		device ref i2c1 on
+			chip drivers/i2c/hid
+				register "generic.hid" = ""ELAN901C""
+				register "generic.desc" = ""ELAN Touchscreen""
+				register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_E11_IRQ)"
+				register "generic.detect" = "1"
+				register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C1)"
+				register "generic.reset_delay_ms" = "20"
+				register "generic.reset_off_delay_ms" = "2"
+				register "generic.stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C4)"
+				register "generic.stop_delay_ms" = "280"
+				register "generic.stop_off_delay_ms" = "2"
+				register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C0)"
+				register "generic.enable_delay_ms" = "1"
+				register "generic.has_power_resource" = "1"
+				register "hid_desc_reg_offset" = "0x01"
+				device i2c 10 on end
+			end
+		end #I2C1
+		device ref i2c5 on
+			chip drivers/i2c/hid
+				register "generic.hid" = ""ELAN0000""
+				register "generic.desc" = ""ELAN Touchpad""
+				register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_F14_IRQ)"
+				register "generic.wake" = "GPE0_DW2_14"
+				register "generic.detect" = "1"
+				register "hid_desc_reg_offset" = "0x01"
+				device i2c 15 on end
+			end
+			chip drivers/i2c/hid
+				register "generic.hid" = ""SYNA0000""
+				register "generic.cid" = ""ACPI0C50""
+				register "generic.desc" = ""Synaptics Touchpad""
+				register "generic.irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_F14_IRQ)"
+				register "generic.wake" = "GPE0_DW2_14"
+				register "generic.detect" = "1"
+				register "hid_desc_reg_offset" = "0x20"
+				device i2c 0x2c on end
+			end
+		end
+		device ref heci1 on end
+		device ref ish on
+			chip drivers/intel/ish
+				register "add_acpi_dma_property" = "true"
+				device generic 0 on end
+			end
+		end
+		device ref ufs on end
+		device ref uart0 on end
+		device ref pch_espi on
+			chip ec/google/chromeec
+				device pnp 0c09.0 on end
+			end
+		end
+		device ref hda on
+			chip drivers/sof
+				register "spkr_tplg" = "max98360a"
+				register "jack_tplg" = "rt5682"
+				register "mic_tplg" = "_2ch_pdm0"
+				device generic 0 on end
+			end
+		end
+	end
+end

From 0e5d1d29bde9b401b5035a66310a4854b85587da Mon Sep 17 00:00:00 2001
From: Nicholas Chin <nic.c3.14@gmail.com>
Date: Sat, 21 Jun 2025 08:53:17 -0600
Subject: [PATCH 1391/3886] soc/intel/skylake: Expand USB OC pins enum to OC7
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Currently, the overcurrent pin enum is only defined up to OC5. However,
PCH-H chips support up to OC7 according to the 100 and 200 Series PCH
datasheets [1][2].

[1] Intel document 332690
[2] Intel document 335192

Change-Id: Ie35612eeaed2196caccc514429c7d80f84cf09a8
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88159
Reviewed-by: Michał Kopeć <michal.kopec@3mdeb.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/soc/intel/skylake/include/soc/usb.h | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/src/soc/intel/skylake/include/soc/usb.h b/src/soc/intel/skylake/include/soc/usb.h
index 612ad5fa2e..de288e774e 100644
--- a/src/soc/intel/skylake/include/soc/usb.h
+++ b/src/soc/intel/skylake/include/soc/usb.h
@@ -38,6 +38,8 @@ enum {
 	OC3,
 	OC4,
 	OC5,
+	OC6,
+	OC7,
 	OC_SKIP = 8, /* Skip OC programming */
 };
 

From f14880934b8c0224b300946af541f00c3db199d9 Mon Sep 17 00:00:00 2001
From: Angel Pons <th3fanbus@gmail.com>
Date: Sun, 25 May 2025 13:39:34 +0200
Subject: [PATCH 1392/3886] Haswell NRI: Use final timings after basic training

For "basic" (initial) memory training, we use larger-than-usual timings
for a few things, namely tCMD and tXP. After basic training is done, we
can switch to the final timings for the training steps that follow (not
many at the moment). Without this, NRI keeps using the training timings
at all times, which results in slightly lower performance (likely to go
unnoticed unless benchmarking the system).

Tested on Asrock B85M Pro4, still boots to Arch Linux.

Change-Id: I625f35adb02b36b1087cd758f983118d0a60b815
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87831
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Benjamin Doron <benjamin.doron00@gmail.com>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
---
 .../haswell/native_raminit/raminit_main.c     | 64 +++++++++++++++++++
 .../haswell/native_raminit/raminit_native.h   |  3 +-
 .../haswell/native_raminit/reg_structs.h      | 15 +++++
 .../native_raminit/train_receive_enable.c     |  2 +-
 4 files changed, 82 insertions(+), 2 deletions(-)

diff --git a/src/northbridge/intel/haswell/native_raminit/raminit_main.c b/src/northbridge/intel/haswell/native_raminit/raminit_main.c
index d211bfb20a..0e72ae66aa 100644
--- a/src/northbridge/intel/haswell/native_raminit/raminit_main.c
+++ b/src/northbridge/intel/haswell/native_raminit/raminit_main.c
@@ -1,6 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0-or-later */
 
 #include <assert.h>
+#include <commonlib/bsd/clamp.h>
 #include <console/console.h>
 #include <cpu/intel/haswell/haswell.h>
 #include <delay.h>
@@ -48,6 +49,68 @@ static enum raminit_status pre_training(struct sysinfo *ctrl)
 	return RAMINIT_STATUS_SUCCESS;
 }
 
+
+static uint8_t get_cmd_stretch(const uint8_t tCMD)
+{
+	switch (tCMD) {
+	case 1:
+		return 0;
+	case 2:
+		return 2;
+	case 3:
+		return 3;
+	default:
+		return 2;
+	}
+}
+
+/** TODO: Why do we re-read the MCHBAR registers? Is the cached value outdated? **/
+static void update_command_rate(struct sysinfo *const ctrl, const uint8_t channel)
+{
+	const uint8_t old_n = clamp_s32(1, ctrl->tc_bankrank_a[channel].cmd_stretch, 3);
+	const uint8_t new_n = ctrl->tCMD;
+
+	/* Update CmdN timing */
+	ctrl->tc_bankrank_a[channel].raw = mchbar_read32(TC_BANK_RANK_A_ch(channel));
+	ctrl->tc_bankrank_a[channel].cmd_stretch = get_cmd_stretch(ctrl->tCMD);
+	mchbar_write32(TC_BANK_RANK_A_ch(channel), ctrl->tc_bankrank_a[channel].raw);
+
+	/* Switch to regular tXP value */
+	ctrl->tc_bankrank_c[channel].raw = mchbar_read32(TC_BANK_RANK_C_ch(channel));
+	ctrl->tc_bankrank_c[channel].tXP = ctrl->tXP;
+	mchbar_write32(TC_BANK_RANK_C_ch(channel), ctrl->tc_bankrank_c[channel].raw);
+
+	/* Adjust RT values to compensate */
+	const int8_t delta = new_n - old_n;
+	for (uint8_t rank = 0; rank < NUM_SLOTRANKS; rank++) {
+		if (!rank_in_ch(ctrl, rank, channel))
+			continue;
+
+		/*
+		 * RT (roundtrip) latency is the time it takes for signals to go
+		 * from the memory controller to the DRAM and back to the memory
+		 * controller. It's likely the delta is doubled for this reason.
+		 */
+		ctrl->rt_latency[channel].rank[rank] += delta * 2;
+	}
+	mchbar_write32(SC_ROUNDT_LAT_ch(channel), ctrl->rt_latency[channel].raw);
+}
+
+static enum raminit_status post_training(struct sysinfo *const ctrl)
+{
+	/* Command rate is always 1N for LPDDR3 */
+	if (ctrl->lpddr) {
+		return RAMINIT_STATUS_SUCCESS;
+	}
+	for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
+		if (!does_ch_exist(ctrl, channel))
+			continue;
+
+		update_command_rate(ctrl, channel);
+	}
+	return RAMINIT_STATUS_SUCCESS;
+}
+
 struct task_entry {
 	enum raminit_status (*task)(struct sysinfo *);
 	bool is_enabled;
@@ -66,6 +129,7 @@ static const struct task_entry cold_boot[] = {
 	{ train_receive_enable,                                   true, "RCVET",      },
 	{ train_read_mpr,                                         true, "RDMPRT",     },
 	{ train_jedec_write_leveling,                             true, "JWRL",       },
+	{ post_training,                                          true, "POSTTRAIN",  },
 	{ activate_mc,                                            true, "ACTIVATE",   },
 	{ save_training_values,                                   true, "SAVE_TRAIN", },
 	{ save_non_training,                                      true, "SAVE_NONT",  },
diff --git a/src/northbridge/intel/haswell/native_raminit/raminit_native.h b/src/northbridge/intel/haswell/native_raminit/raminit_native.h
index 82ecb1c03d..097b6411b3 100644
--- a/src/northbridge/intel/haswell/native_raminit/raminit_native.h
+++ b/src/northbridge/intel/haswell/native_raminit/raminit_native.h
@@ -306,8 +306,9 @@ struct sysinfo {
 
 	union ddr_data_vref_adjust_reg dimm_vref;
 
+	union sc_roundt_lat_reg rt_latency[NUM_CHANNELS];
+
 	uint8_t io_latency[NUM_CHANNELS][NUM_SLOTRANKS];
-	uint8_t rt_latency[NUM_CHANNELS][NUM_SLOTRANKS];
 	uint32_t rt_io_comp[NUM_CHANNELS];
 
 	uint32_t data_offset_train[NUM_CHANNELS][NUM_LANES];
diff --git a/src/northbridge/intel/haswell/native_raminit/reg_structs.h b/src/northbridge/intel/haswell/native_raminit/reg_structs.h
index 8a1586b49a..b9043e8883 100644
--- a/src/northbridge/intel/haswell/native_raminit/reg_structs.h
+++ b/src/northbridge/intel/haswell/native_raminit/reg_structs.h
@@ -321,6 +321,21 @@ union ddr_scram_misc_control_reg {
 	uint32_t raw;
 };
 
+union sc_roundt_lat_reg {
+	struct __packed {
+		uint32_t R0D0 : 6; // Bits  5:0
+		uint32_t      : 2; // Bits  7:6
+		uint32_t R1D0 : 6; // Bits 13:8
+		uint32_t      : 2; // Bits 15:14
+		uint32_t R0D1 : 6; // Bits 21:16
+		uint32_t      : 2; // Bits 23:22
+		uint32_t R1D1 : 6; // Bits 29:24
+		uint32_t      : 2; // Bits 31:30
+	};
+	uint8_t rank[4];
+	uint32_t raw;
+};
+
 union sc_io_latency_reg {
 	struct __packed {
 		uint32_t iolat_rank0     : 4; // Bits  3:0
diff --git a/src/northbridge/intel/haswell/native_raminit/train_receive_enable.c b/src/northbridge/intel/haswell/native_raminit/train_receive_enable.c
index 576c6bc21e..72885f84b8 100644
--- a/src/northbridge/intel/haswell/native_raminit/train_receive_enable.c
+++ b/src/northbridge/intel/haswell/native_raminit/train_receive_enable.c
@@ -254,7 +254,7 @@ enum raminit_status train_receive_enable(struct sysinfo *ctrl)
 
 			ctrl->io_latency[channel][rank] = 0;
 			mchbar_write8(SC_ROUNDT_LAT_ch(channel) + rank, initial_rt_latency);
-			ctrl->rt_latency[channel][rank] = initial_rt_latency;
+			ctrl->rt_latency[channel].rank[rank] = initial_rt_latency;
 		}
 
 		printk(BIOS_DEBUG, "Rank %u\n", rank);

From a66d2d41f5e79b5e9715d85bcbf251c3a4029c63 Mon Sep 17 00:00:00 2001
From: Nicholas Chin <nic.c3.14@gmail.com>
Date: Sat, 21 Jun 2025 09:05:43 -0600
Subject: [PATCH 1393/3886] mb/lenovo/m900/devicetree.cb: Use OC6 enum
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Commit 0e5d1d29bde9 ("soc/intel/skylake: Expand USB OC pins enum to
OC7") added the missing OC6 and OC7 enums for PCH-H, so use those
instead of a bare integer to map USB2 ports 10 and 11 to overcurrent
pin 6.

TEST=Timeless build did not change

Change-Id: I3680fae39e96783e4434b36a8dfd751888541cbb
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88160
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michał Kopeć <michal.kopec@3mdeb.com>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
---
 src/mainboard/lenovo/m900/devicetree.cb | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/mainboard/lenovo/m900/devicetree.cb b/src/mainboard/lenovo/m900/devicetree.cb
index 8b550a74d3..b5c02cca0f 100644
--- a/src/mainboard/lenovo/m900/devicetree.cb
+++ b/src/mainboard/lenovo/m900/devicetree.cb
@@ -54,8 +54,8 @@ chip soc/intel/skylake
 				[7] = USB2_PORT_MID(OC3), /* Rear port 4 */
 				[8] = USB2_PORT_MID(OC5), /* FUSB_1 Header */
 				[9] = USB2_PORT_MID(OC5), /* FUSB_1 Header */
-				[10] = USB2_PORT_MID(6), /* FUSB_2 Header */
-				[11] = USB2_PORT_MID(6), /* FUSB_2 Header */
+				[10] = USB2_PORT_MID(OC6), /* FUSB_2 Header */
+				[11] = USB2_PORT_MID(OC6), /* FUSB_2 Header */
 				[12] = USB2_PORT_MID(OC1), /* Rear port 7 */
 				[13] = USB2_PORT_MID(OC1), /* Rear port 8 */
 			}"

From 5568bee055388040b8d88b3b6b2a49263c2a2281 Mon Sep 17 00:00:00 2001
From: Subrata Banik <subratabanik@google.com>
Date: Sat, 21 Jun 2025 03:25:17 +0000
Subject: [PATCH 1394/3886] drivers/spi: Support forced 4-byte address mode via
 0xB7 command

Many high-capacity SPI flashes (e.g., >16MB) default to 3-byte
addressing and require a specific command to enter 4-byte address mode.

This commit introduces support for sending the
CMD_FORCE_4BYTE_ADDR_MODE (0xB7) command during flash probing. When
Kconfig option `SPI_FLASH_FORCE_4_BYTE_ADDR_MODE` is enabled, this
ensures the flash chip is immediately switched to 4-byte addressing
after power-on.

This addresses issues with flashes like GigaDevice (GD25LQ128D) and
Winbond (W25Q256JWxx) that mandate this command for proper 4-byte
addressing. The new command definition is in `spi_flash_internal.h`.

BUG=b:417900125
TEST=Able to build google/bluey.

Change-Id: I935a0e1d6214d73c8ea487418adc93f016790432
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88156
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/drivers/spi/spi_flash.c          | 5 +++++
 src/drivers/spi/spi_flash_internal.h | 2 ++
 2 files changed, 7 insertions(+)

diff --git a/src/drivers/spi/spi_flash.c b/src/drivers/spi/spi_flash.c
index b7a024c4c2..80e937a724 100644
--- a/src/drivers/spi/spi_flash.c
+++ b/src/drivers/spi/spi_flash.c
@@ -564,6 +564,11 @@ int spi_flash_probe(unsigned int bus, unsigned int cs, struct spi_flash *flash)
 			CONFIG_ROM_SIZE);
 	}
 
+	if (CONFIG(SPI_FLASH_FORCE_4_BYTE_ADDR_MODE)) {
+		printk(BIOS_DEBUG, "SF: Force 4-byte addressing mode\n");
+		spi_flash_cmd(&flash->spi, CMD_FORCE_4BYTE_ADDR_MODE, NULL, 0);
+	}
+
 	if (CONFIG(SPI_FLASH_EXIT_4_BYTE_ADDR_MODE) && SPI_FLASH_EXIT_4BYTE_STAGE) {
 		printk(BIOS_DEBUG, "SF: Exiting 4-byte addressing mode\n");
 		spi_flash_cmd(&flash->spi, CMD_EXIT_4BYTE_ADDR_MODE, NULL, 0);
diff --git a/src/drivers/spi/spi_flash_internal.h b/src/drivers/spi/spi_flash_internal.h
index a30f58f9a5..163b6181b7 100644
--- a/src/drivers/spi/spi_flash_internal.h
+++ b/src/drivers/spi/spi_flash_internal.h
@@ -22,6 +22,8 @@
 #define CMD_READ_STATUS			0x05
 #define CMD_WRITE_ENABLE		0x06
 
+#define CMD_FORCE_4BYTE_ADDR_MODE	0xb7
+
 #define CMD_BLOCK_ERASE			0xD8
 
 #define CMD_EXIT_4BYTE_ADDR_MODE	0xe9

From 3e0d8a2f2c85a637b75d97cea692f2ef3832a9c3 Mon Sep 17 00:00:00 2001
From: Subrata Banik <subratabanik@google.com>
Date: Fri, 13 Jun 2025 12:23:46 +0000
Subject: [PATCH 1395/3886] mb/google/bluey: Enable 4-byte addressing mode

This patch selects `SPI_FLASH_FORCE_4_BYTE_ADDR_MODE` Kconfig option,
to enable 4-byte addressing for SPI flash devices.

BUG=b:417900125
TEST=Able to build google/bluey.

Change-Id: If7f651c2a59637c12ab07367f2680359446d823d
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88093
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/google/bluey/Kconfig | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/mainboard/google/bluey/Kconfig b/src/mainboard/google/bluey/Kconfig
index ed02ddf405..812b792797 100644
--- a/src/mainboard/google/bluey/Kconfig
+++ b/src/mainboard/google/bluey/Kconfig
@@ -7,7 +7,7 @@ config BOARD_GOOGLE_BLUEY_COMMON
 	select MAINBOARD_HAS_CHROMEOS
 	select SOC_QUALCOMM_X1P42100
 	select SPI_FLASH
-	select SPI_FLASH_EXIT_4_BYTE_ADDR_MODE
+	select SPI_FLASH_FORCE_4_BYTE_ADDR_MODE
 	select SPI_FLASH_WINBOND
 
 config BOARD_GOOGLE_BASEBOARD_BLUEY

From 97f92d5c698b48d97e65ae12c561c778ba625ba5 Mon Sep 17 00:00:00 2001
From: Subrata Banik <subratabanik@google.com>
Date: Sun, 22 Jun 2025 18:50:17 +0530
Subject: [PATCH 1396/3886] drivers/intel: Add support for configurable footer
 logo bottom margin

Introduces logo_bottom_margin to soc_intel_common_config to allow
adjusting the vertical (or horizontal, based on orientation) offset of
the footer logo from the screen edge. This provides flexibility for
OEM branding placement.

BUG=b:423591644
TEST=Able to show OEM splash screen on google/fatcat.

Change-Id: Ie3942d9eee07091286118ac488d1cc85ecc96c4c
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88163
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
---
 src/drivers/intel/fsp2_0/cb_logo.c                   | 9 +++++++++
 src/soc/intel/common/block/include/intelblocks/cfg.h | 2 ++
 2 files changed, 11 insertions(+)

diff --git a/src/drivers/intel/fsp2_0/cb_logo.c b/src/drivers/intel/fsp2_0/cb_logo.c
index d86e9e3ff0..d533806656 100644
--- a/src/drivers/intel/fsp2_0/cb_logo.c
+++ b/src/drivers/intel/fsp2_0/cb_logo.c
@@ -185,6 +185,15 @@ static int render_logo_to_framebuffer(uintptr_t framebuffer_base, uint32_t bytes
 	logo_coords = calculate_logo_coordinates(horizontal_resolution,
 		 vertical_resolution, logo_width, logo_height, valignment, halignment);
 
+	/* Adjust the logo axis for rendering footer bootsplash if any override is available */
+	if (logo_type == BOOTSPLASH_FOOTER && config->logo_bottom_margin) {
+		if (config->panel_orientation == LB_FB_ORIENTATION_BOTTOM_UP ||
+				 config->panel_orientation == LB_FB_ORIENTATION_NORMAL)
+			logo_coords.y -= config->logo_bottom_margin;
+		else
+			logo_coords.x -= config->logo_bottom_margin;
+	}
+
 	copy_logo_to_framebuffer(framebuffer_base, bytes_per_scanline, blt_buffer_addr,
 				 logo_width, logo_height, logo_coords.x, logo_coords.y);
 
diff --git a/src/soc/intel/common/block/include/intelblocks/cfg.h b/src/soc/intel/common/block/include/intelblocks/cfg.h
index ee75dcfc48..8aac699525 100644
--- a/src/soc/intel/common/block/include/intelblocks/cfg.h
+++ b/src/soc/intel/common/block/include/intelblocks/cfg.h
@@ -127,6 +127,8 @@ struct soc_intel_common_config {
 	struct mmc_dll_params emmc_dll;
 	enum lb_fb_orientation panel_orientation;
 	enum fw_splash_vertical_alignment logo_valignment;
+	/* Implies spacing from an edge for rendering footer logo */
+	uint8_t logo_bottom_margin;
 };
 
 /* This function to retrieve soc config structure required by common code */

From f846ec1e370fa12f5ab4d01df0ed7a5e0cbcd4ae Mon Sep 17 00:00:00 2001
From: Subrata Banik <subratabanik@google.com>
Date: Sun, 22 Jun 2025 19:10:40 +0530
Subject: [PATCH 1397/3886] mainboard/google/fatcat: Set OEM footer logo bottom
 margin

Applies a `logo_bottom_margin` of 100 pixels to the `common_soc_config`
for the Fatcat mainboard and its variants (Felino, Francka, Kinmen).
This configures the OEM footer logo to be rendered 100 pixels above
the bottom edge of the screen.

BUG=b:423591644
TEST=Verified OEM footer logo displays 100px above the bottom edge on
google/fatcat builds.

Change-Id: I30a63b6ecccd20380d7f0b402891e286967284c3
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88164
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
---
 src/mainboard/google/fatcat/variants/fatcat/overridetree.cb  | 2 ++
 src/mainboard/google/fatcat/variants/felino/overridetree.cb  | 2 ++
 src/mainboard/google/fatcat/variants/francka/overridetree.cb | 2 ++
 src/mainboard/google/fatcat/variants/kinmen/overridetree.cb  | 2 ++
 4 files changed, 8 insertions(+)

diff --git a/src/mainboard/google/fatcat/variants/fatcat/overridetree.cb b/src/mainboard/google/fatcat/variants/fatcat/overridetree.cb
index 565aad6f98..69c00ee8de 100644
--- a/src/mainboard/google/fatcat/variants/fatcat/overridetree.cb
+++ b/src/mainboard/google/fatcat/variants/fatcat/overridetree.cb
@@ -128,6 +128,8 @@ chip soc/intel/pantherlake
 	#| I2C5              | Touchpad                  |
 	#+-------------------+---------------------------+
 	register "common_soc_config" = "{
+		/* Render OEM footer logo 100px above from the edge */
+		.logo_bottom_margin = 100,
 		.chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT,
 		.i2c[1] = {
 			.speed = I2C_SPEED_FAST,
diff --git a/src/mainboard/google/fatcat/variants/felino/overridetree.cb b/src/mainboard/google/fatcat/variants/felino/overridetree.cb
index 9184f1d62a..743877db5a 100644
--- a/src/mainboard/google/fatcat/variants/felino/overridetree.cb
+++ b/src/mainboard/google/fatcat/variants/felino/overridetree.cb
@@ -102,6 +102,8 @@ chip soc/intel/pantherlake
 	#| I2C4              | CLICK PAD                 |
 	#+-------------------+---------------------------+
 	register "common_soc_config" = "{
+		/* Render OEM footer logo 100px above from the edge */
+		.logo_bottom_margin = 100,
 		.i2c[1] = {
 			.early_init=1,
 			.speed = I2C_SPEED_FAST,
diff --git a/src/mainboard/google/fatcat/variants/francka/overridetree.cb b/src/mainboard/google/fatcat/variants/francka/overridetree.cb
index bbf6654068..f61c8dddaf 100644
--- a/src/mainboard/google/fatcat/variants/francka/overridetree.cb
+++ b/src/mainboard/google/fatcat/variants/francka/overridetree.cb
@@ -78,6 +78,8 @@ chip soc/intel/pantherlake
 	#| I2C4              | Touchscreen, Touchpad     |
 	#+-------------------+---------------------------+
 	register "common_soc_config" = "{
+		/* Render OEM footer logo 100px above from the edge */
+		.logo_bottom_margin = 100,
 		.chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT,
 		.i2c[1] = {
 			.early_init = 1,
diff --git a/src/mainboard/google/fatcat/variants/kinmen/overridetree.cb b/src/mainboard/google/fatcat/variants/kinmen/overridetree.cb
index 8299b42f97..1944d148a5 100644
--- a/src/mainboard/google/fatcat/variants/kinmen/overridetree.cb
+++ b/src/mainboard/google/fatcat/variants/kinmen/overridetree.cb
@@ -65,6 +65,8 @@ chip soc/intel/pantherlake
 	#| I2C5              | Touchscreen               |
 	#+-------------------+---------------------------+
 	register "common_soc_config" = "{
+		/* Render OEM footer logo 100px above from the edge */
+		.logo_bottom_margin = 100,
 		.chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT,
 		.i2c[3] = {
 			.early_init = 1,

From a60c5d205bf70af00ed2f5075079fd0c2f9aadc3 Mon Sep 17 00:00:00 2001
From: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com>
Date: Mon, 16 Jun 2025 18:08:03 +0900
Subject: [PATCH 1398/3886] mb/google/nissa/var/meliks: Initialize display
 signals on user mode

Meliks uses panel-built-in touch screen, it needs to set panel power
and reset signal to high for touch screen to work.

On user mode, coreboot doesn't initialize graphics since there is no
screen display before OS. So we would add a WA to initialize required
signals on user mode. It takes under 30 ms delay on booting time.

Bugzzy has fixed the same issue, copied the WA code from bugzzy.
- 1106bcce0df6: `bugzzy: Initialize display signals on user mode`

Reference: HX83121-A panel specification (Page 60 - 64):
https://drive.google.com/file/d/1Q0wjzHmSOa_r2FwiNe4PtKWmhhacBw4W/view?pli=1&resourcekey=0-pnGgp8yzf68UpyqNE1Caew

BUG=b:412584604, b:398703068
BRANCH=nissa
TEST=Verified touch screen worked with test coreboot without FW splash
     screen. (crrev/c/6647126)

- A part of `cbmem -t` result before this change:
```
 115:finished elog init     914,227 (2,679)
  70:device setup done      915,121 (893)
    ...
1101:jumping to kernel      1,055,074 (9,849)

Total Time: 1,055,039
```

- A part of `cbmem -t` result after this change:
```
 115:finished elog init     911,708 (2,674)
  70:device setup done      936,680 (24,971)
    ...
1101:jumping to kernel      1,073,415 (9,360)

Total Time: 1,073,379
```

Change-Id: I92c7754cfbdf73e84a25b6d45b062ba9cafb04ab
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88107
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
---
 .../google/brya/variants/meliks/ramstage.c    | 58 ++++++++++++++++++-
 1 file changed, 57 insertions(+), 1 deletion(-)

diff --git a/src/mainboard/google/brya/variants/meliks/ramstage.c b/src/mainboard/google/brya/variants/meliks/ramstage.c
index d2a9b5c667..473fc63ecd 100644
--- a/src/mainboard/google/brya/variants/meliks/ramstage.c
+++ b/src/mainboard/google/brya/variants/meliks/ramstage.c
@@ -2,10 +2,17 @@
 
 #define __SIMPLE_DEVICE__
 
-#include <soc/ramstage.h>
+#include <bootmode.h>
+#include <bootstate.h>
+#include <delay.h>
+#include <device/device.h>
+#include <device/pci.h>
 #include <device/pci_def.h>
 #include <device/pci_ops.h>
 #include <device/mmio.h>
+#include <drivers/intel/gma/i915_reg.h>
+#include <soc/pci_devs.h>
+#include <soc/ramstage.h>
 
 #define DPHY_0_CLOCK_LANE_TIMING	0x162180
 #define RESET_DPHY_0_CLOCK_LANE_TIMING	0
@@ -54,3 +61,52 @@ void mainboard_silicon_init_params(FSP_S_CONFIG *params)
 	   the HW default */
 	reset_display_dphy_clock();
 }
+
+static void panel_power_on(uintptr_t igd_bar)
+{
+	setbits32((void *)(igd_bar + PCH_PP_CONTROL), PANEL_POWER_ON);
+}
+
+static void panel_reset_assert(uintptr_t igd_bar)
+{
+	clrsetbits32((void *)(igd_bar + PCH_GPIOB),
+		GPIO_CLOCK_VAL_OUT,
+		GPIO_CLOCK_DIR_MASK | GPIO_CLOCK_DIR_OUT | GPIO_CLOCK_VAL_MASK);
+}
+
+static void panel_reset_deassert(uintptr_t igd_bar)
+{
+	const uint32_t data32 = GPIO_CLOCK_VAL_OUT |
+		GPIO_CLOCK_DIR_MASK | GPIO_CLOCK_DIR_OUT | GPIO_CLOCK_VAL_MASK;
+	setbits32((void *)(igd_bar + PCH_GPIOB), data32);
+}
+
+/*
+ * Meliks uses panel-built-in touch screen, it needs to set panel power and
+ * reset signal to high for touch screen to work.
+ * On user mode, coreboot doesn't initialize graphics since there is no screen
+ * display before OS. We would add this WA to initialize required signals on
+ * user mode.
+ */
+static void wa_init_display_signal(void *unused)
+{
+	struct device *igd_dev = pcidev_path_on_root(SA_DEVFN_IGD);
+	uintptr_t igd_bar;
+
+	if (display_init_required() || !igd_dev)
+		return;
+
+	igd_bar = find_resource(igd_dev, PCI_BASE_ADDRESS_0)->base;
+	if (!igd_bar)
+		return;
+
+	panel_power_on(igd_bar);
+	mdelay(20);
+	panel_reset_deassert(igd_bar);
+	mdelay(2);
+	panel_reset_assert(igd_bar);
+	mdelay(2);
+	panel_reset_deassert(igd_bar);
+}
+
+BOOT_STATE_INIT_ENTRY(BS_POST_DEVICE, BS_ON_ENTRY, wa_init_display_signal, NULL);

From cfd0b4dd2049fe94ecd2d22db659bf04604685a8 Mon Sep 17 00:00:00 2001
From: Irving-CH Lin <irving-ch.lin@mediatek.corp-partner.google.com>
Date: Wed, 30 Apr 2025 10:57:10 +0800
Subject: [PATCH 1399/3886] soc/mediatek/mt8189: Change msdcpll default freq to
 384MHz

According to the eMMC specification, the maximum allowed source clock
frequency is 200MHz. Currently, a 416MHz source clock is used, which
after division results in 208MHz. This exceeds the spec limit.

Additionally, considering possible frequency fluctuations and desense
issues, 384MHz is a more reasonable and safer value. Limit the source
clock frequency to 384MHz to ensure compliance with the eMMC
specification and improve system stability.

BUG=b:396258620
BRANCH=none
TEST=echo fmeter > /proc/clkdbg ; cat /proc/clkdbg |grep msdcpll
30: fm_msdcpll_ck                : 383500

Signed-off-by: Irving-CH Lin <irving-ch.lin@mediatek.corp-partner.google.com>
Change-Id: I3c704b1200dd89a05476a5b14b75950aead51f30
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88166
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
---
 src/soc/mediatek/mt8189/include/soc/pll.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/soc/mediatek/mt8189/include/soc/pll.h b/src/soc/mediatek/mt8189/include/soc/pll.h
index a3b474cab0..0a7c2a8417 100644
--- a/src/soc/mediatek/mt8189/include/soc/pll.h
+++ b/src/soc/mediatek/mt8189/include/soc/pll.h
@@ -524,7 +524,7 @@ enum {
 	TVDPLL1_HZ	= 594 * MHz,
 	TVDPLL2_HZ	= 594 * MHz,
 	ETHPLL_HZ	= 500 * MHz,
-	MSDCPLL_HZ	= 416 * MHz,
+	MSDCPLL_HZ	= 384 * MHz,
 	UFSPLL_HZ	= 594 * MHz,
 };
 

From d8fc5eba2d8434fbc81575f30ff6b3d90fb6d850 Mon Sep 17 00:00:00 2001
From: Vince Liu <vince-wl.liu@mediatek.corp-partner.google.com>
Date: Wed, 11 Jun 2025 11:30:23 +0800
Subject: [PATCH 1400/3886] soc/mediatek/mt8189: Add eDP driver

Based on the dptx_v2 common driver, add eDP driver to adjust training
flow and turn off PHY power before PHY configuration to prevent
potential link training failures. Also correct the DISP_DVO0 address
since the initial value is not thoroughly checked during early bring-up.

DISP_DVO is a highly advanced variant of DP_INTF block for eDP or HDMI
or simply digital video output. DISP represents "display", while DVO is
the abbreviation of "digital video output". This version of DISP_DVO is
mainly designed for eDP1.5 protocol.

BUG=b:400886838,b:422095960
BRANCH=none
TEST=Check the display function on Skywalker. Check the log for
    "EQ training pass".

Signed-off-by: Bincai Liu <bincai.liu@mediatek.corp-partner.google.com>
Signed-off-by: Vince Liu <vince-wl.liu@mediatek.corp-partner.google.com>
Change-Id: I59cfdae1d13cf7fb9627a4d534602cb309df3d67
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88168
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
---
 src/soc/mediatek/mt8189/Makefile.mk           |  4 ++
 src/soc/mediatek/mt8189/dptx.c                | 21 +++++++++++
 src/soc/mediatek/mt8189/dptx_hal.c            | 37 +++++++++++++++++++
 .../mediatek/mt8189/include/soc/addressmap.h  |  3 +-
 src/soc/mediatek/mt8189/include/soc/dp_intf.h | 11 ++++++
 src/soc/mediatek/mt8189/include/soc/dptx.h    |  8 ++++
 .../mediatek/mt8189/include/soc/dptx_hal.h    | 15 ++++++++
 .../mediatek/mt8189/include/soc/dptx_reg.h    | 16 ++++++++
 8 files changed, 114 insertions(+), 1 deletion(-)
 create mode 100644 src/soc/mediatek/mt8189/dptx.c
 create mode 100644 src/soc/mediatek/mt8189/dptx_hal.c
 create mode 100644 src/soc/mediatek/mt8189/include/soc/dp_intf.h
 create mode 100644 src/soc/mediatek/mt8189/include/soc/dptx.h
 create mode 100644 src/soc/mediatek/mt8189/include/soc/dptx_hal.h
 create mode 100644 src/soc/mediatek/mt8189/include/soc/dptx_reg.h

diff --git a/src/soc/mediatek/mt8189/Makefile.mk b/src/soc/mediatek/mt8189/Makefile.mk
index eb1ce41b48..4f74401cbc 100644
--- a/src/soc/mediatek/mt8189/Makefile.mk
+++ b/src/soc/mediatek/mt8189/Makefile.mk
@@ -35,6 +35,9 @@ romstage-y += ../common/rtc.c ../common/rtc_osc_init.c ../common/rtc_mt6359p.c
 ramstage-y += ../common/auxadc.c
 ramstage-$(CONFIG_ARM64_USE_ARM_TRUSTED_FIRMWARE) += ../common/bl31.c
 ramstage-y += ../common/dpm.c ../common/dpm_v2.c
+ramstage-y += ../common/dp/dp_intf_v2.c
+ramstage-y += ../common/dp/dptx_common.c ../common/dp/dptx_v2.c dptx.c
+ramstage-y += ../common/dp/dptx_hal_common.c ../common/dp/dptx_hal_v2.c  dptx_hal.c
 ramstage-y += ../common/dramc_info.c
 ramstage-y += ../common/emi.c
 ramstage-y += ../common/mcu.c mcupm.c
@@ -58,6 +61,7 @@ BL31_MAKEARGS += PLAT=mt8189
 
 CPPFLAGS_common += -Isrc/soc/mediatek/mt8189/include
 CPPFLAGS_common += -Isrc/soc/mediatek/common/include
+CPPFLAGS_common += -Isrc/soc/mediatek/common/dp/include
 
 MT8189_BLOB_DIR := 3rdparty/blobs/soc/mediatek/mt8189
 
diff --git a/src/soc/mediatek/mt8189/dptx.c b/src/soc/mediatek/mt8189/dptx.c
new file mode 100644
index 0000000000..c07195ff06
--- /dev/null
+++ b/src/soc/mediatek/mt8189/dptx.c
@@ -0,0 +1,21 @@
+/* SPDX-License-Identifier: GPL-2.0-only OR MIT */
+
+/*
+ * This file is created based on MT8189 Functional Specification
+ * Chapter number: 10.28
+ */
+
+#include <device/mmio.h>
+#include <soc/addressmap.h>
+#include <soc/dptx.h>
+#include <soc/dp_intf.h>
+
+void dptx_set_tx_power_con(void)
+{
+}
+
+void dptx_set_26mhz_clock(void)
+{
+	write32p(CKSYS_BASE + CKSYS_CLK_CFG_16_CLR, 0xFF000000);
+	write32p(CKSYS_BASE + CKSYS_CLK_CFG_UPDATE, 0x00000020);
+}
diff --git a/src/soc/mediatek/mt8189/dptx_hal.c b/src/soc/mediatek/mt8189/dptx_hal.c
new file mode 100644
index 0000000000..552f79b7cd
--- /dev/null
+++ b/src/soc/mediatek/mt8189/dptx_hal.c
@@ -0,0 +1,37 @@
+/* SPDX-License-Identifier: GPL-2.0-only OR MIT */
+
+/*
+ * This file is created based on MT8189 Functional Specification
+ * Chapter number: 10.28
+ */
+
+#include <console/console.h>
+#include <delay.h>
+#include <soc/dptx.h>
+#include <soc/dptx_hal.h>
+#include <soc/dptx_reg.h>
+
+void dptx_hal_reset_swing_preemphasis(struct mtk_dp *mtk_dp)
+{
+	u32 mask = EDP_TX_LN_VOLT_SWING_VAL_MASK | EDP_TX_LN_PRE_EMPH_VAL_MASK |
+		   EDP_TX_LN_VOLT_SWING_EN_MASK | EDP_TX_LN_PRE_EMPH_EN_MASK;
+	u32 value = EDP_TX_LN_VOLT_SWING_EN_MASK | EDP_TX_LN_PRE_EMPH_EN_MASK;
+
+	for (int i = 0; i < dptx_hal_driving_offset_size; i++)
+		mtk_dp_phy_mask(mtk_dp, dptx_hal_driving_offset[i], value, mask);
+}
+
+void dptx_hal_phy_set_lanes(struct mtk_dp *mtk_dp, u8 lane_count)
+{
+	mtk_dp_phy_mask(mtk_dp, PHYD_DIG_GLB_OFFSET + 0x44,
+			GENMASK(4 + lane_count - 1, 4), GENMASK(7, 4));
+}
+
+void dptx_hal_phyd_reset(struct mtk_dp *mtk_dp)
+{
+	mtk_dp_phy_mask(mtk_dp, DP_PHY_DIG_SW_RST, 0, BIT(0));
+	udelay(10);
+	mtk_dp_phy_mask(mtk_dp, DP_PHY_DIG_SW_RST, BIT(0), BIT(0));
+
+	dptx_hal_reset_swing_preemphasis(mtk_dp);
+}
diff --git a/src/soc/mediatek/mt8189/include/soc/addressmap.h b/src/soc/mediatek/mt8189/include/soc/addressmap.h
index 2e24c1dde6..fc8bf3f03a 100644
--- a/src/soc/mediatek/mt8189/include/soc/addressmap.h
+++ b/src/soc/mediatek/mt8189/include/soc/addressmap.h
@@ -96,6 +96,7 @@ enum {
 	IOCFG_BM1_BASE			= IO_PHYS + 0x01D30000,
 	IOCFG_BM2_BASE			= IO_PHYS + 0x01D40000,
 	IMP_IIC_WRAP_S_BASE		= IO_PHYS + 0x01D74000,
+	EDP_PHY_BASE			= IO_PHYS + 0x01E10000,
 	IOCFG_LT0_BASE			= IO_PHYS + 0x01E20000,
 	IOCFG_LT1_BASE			= IO_PHYS + 0x01E30000,
 	MSDC0_TOP_BASE			= IO_PHYS + 0x01E70000,
@@ -105,7 +106,7 @@ enum {
 	MFGCFG_BASE			= IO_PHYS + 0x03FBF000,
 	MMSYS_CONFIG_BASE		= IO_PHYS + 0x04000000,
 	DSI0_BASE			= IO_PHYS + 0x04016000,
-	DISP_DVO0			= IO_PHYS + 0x04019000,
+	DISP_DVO0			= IO_PHYS + 0x04017000,
 	IMGSYS1_BASE			= IO_PHYS + 0x05020000,
 	IMGSYS2_BASE			= IO_PHYS + 0x05820000,
 	VDEC_CORE_BASE			= IO_PHYS + 0x0602F000,
diff --git a/src/soc/mediatek/mt8189/include/soc/dp_intf.h b/src/soc/mediatek/mt8189/include/soc/dp_intf.h
new file mode 100644
index 0000000000..11d0129267
--- /dev/null
+++ b/src/soc/mediatek/mt8189/include/soc/dp_intf.h
@@ -0,0 +1,11 @@
+/* SPDX-License-Identifier: GPL-2.0-only OR MIT */
+
+#ifndef __SOC_MEDIATEK_MT8189_DP_DP_INTF_H__
+#define __SOC_MEDIATEK_MT8189_DP_DP_INTF_H__
+
+#include <soc/dp_intf_v2.h>
+
+#define CKSYS_CLK_CFG_16_CLR	0x118
+#define CKSYS_CLK_CFG_UPDATE	0xC
+
+#endif /* __SOC_MEDIATEK_MT8189_DP_DP_INTF_H__ */
diff --git a/src/soc/mediatek/mt8189/include/soc/dptx.h b/src/soc/mediatek/mt8189/include/soc/dptx.h
new file mode 100644
index 0000000000..04ce124534
--- /dev/null
+++ b/src/soc/mediatek/mt8189/include/soc/dptx.h
@@ -0,0 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef __SOC_MEDIATEK_MT8189_INCLUDE_SOC_DPTX_H__
+#define __SOC_MEDIATEK_MT8189_INCLUDE_SOC_DPTX_H__
+
+#include <soc/dptx_common.h>
+
+#endif /* __SOC_MEDIATEK_MT8189_INCLUDE_SOC_DPTX_H__ */
diff --git a/src/soc/mediatek/mt8189/include/soc/dptx_hal.h b/src/soc/mediatek/mt8189/include/soc/dptx_hal.h
new file mode 100644
index 0000000000..38c8644886
--- /dev/null
+++ b/src/soc/mediatek/mt8189/include/soc/dptx_hal.h
@@ -0,0 +1,15 @@
+/* SPDX-License-Identifier: GPL-2.0-only OR MIT */
+
+#ifndef __SOC_MEDIATEK_MT8189_DP_DPTX_HAL_H__
+#define __SOC_MEDIATEK_MT8189_DP_DPTX_HAL_H__
+
+#include <soc/dptx_hal_v2.h>
+
+#define DP_LINKRATE_RBR_VAL	0
+#define DP_LINKRATE_HBR_VAL	1
+#define DP_LINKRATE_HBR2_VAL	2
+#define DP_LINKRATE_HBR3_VAL	3
+
+#define DP_PHY_DIG_GLB_STATUS_02_OFSSET	0x1488
+
+#endif /* __SOC_MEDIATEK_MT8189_DP_DPTX_HAL_H__ */
diff --git a/src/soc/mediatek/mt8189/include/soc/dptx_reg.h b/src/soc/mediatek/mt8189/include/soc/dptx_reg.h
new file mode 100644
index 0000000000..02366dc8d4
--- /dev/null
+++ b/src/soc/mediatek/mt8189/include/soc/dptx_reg.h
@@ -0,0 +1,16 @@
+/* SPDX-License-Identifier: GPL-2.0-only OR MIT */
+
+#ifndef __SOC_MEDIATEK_MT8189_DP_DPTX_REG_H__
+#define __SOC_MEDIATEK_MT8189_DP_DPTX_REG_H__
+
+#include <soc/dptx_reg_v2.h>
+
+#define DP_PHY_DIG_TX_CTL_0			0x1444
+#define RGS_AUX_LDO_EN_READY_MASK		BIT(2)
+#define DRIVING_FORCE				0x18
+#define EDP_TX_LN_PRE_EMPH_VAL_MASK		GENMASK(6, 5)
+#define EDP_TX_LN_PRE_EMPH_VAL_SHIFT		5
+#define EDP_TX_LN_VOLT_SWING_EN_MASK		BIT(0)
+#define EDP_TX_LN_PRE_EMPH_EN_MASK		BIT(4)
+
+#endif /* __SOC_MEDIATEK_MT8189_DP_DPTX_REG_H__ */

From cdb49c4d2e2bf2490df4dfabb8d2f361d9eec1c4 Mon Sep 17 00:00:00 2001
From: Vince Liu <vince-wl.liu@mediatek.corp-partner.google.com>
Date: Fri, 13 Jun 2025 16:32:55 +0800
Subject: [PATCH 1401/3886] soc/mediatek/mt8189: Add ddp driver to support eDP
 output

Add DDP (display controller) driver that supports main path to eDP
panel. The output goes to display interface DSI.

BUG=b:400886838
BRANCH=none
TEST=Build pass and firmware display ok

Signed-off-by: Xiandong Wang <xiandong.wang@mediatek.corp-partner.google.com>
Signed-off-by: Vince Liu <vince-wl.liu@mediatek.corp-partner.google.com>
Change-Id: Id6c942fc60d7fdd21981198dbd416acb235f6b27
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88169
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/soc/mediatek/mt8189/Makefile.mk           |   5 +-
 src/soc/mediatek/mt8189/ddp.c                 | 151 +++++++++
 .../mediatek/mt8189/include/soc/addressmap.h  |  12 +
 src/soc/mediatek/mt8189/include/soc/ddp.h     | 303 ++++++++++++++++++
 src/soc/mediatek/mt8189/include/soc/dsi.h     |   8 +
 5 files changed, 477 insertions(+), 2 deletions(-)
 create mode 100644 src/soc/mediatek/mt8189/ddp.c
 create mode 100644 src/soc/mediatek/mt8189/include/soc/ddp.h
 create mode 100644 src/soc/mediatek/mt8189/include/soc/dsi.h

diff --git a/src/soc/mediatek/mt8189/Makefile.mk b/src/soc/mediatek/mt8189/Makefile.mk
index 4f74401cbc..50c576b4f1 100644
--- a/src/soc/mediatek/mt8189/Makefile.mk
+++ b/src/soc/mediatek/mt8189/Makefile.mk
@@ -5,6 +5,7 @@ ifeq ($(CONFIG_SOC_MEDIATEK_MT8189),y)
 all-y += ../common/flash_controller.c
 all-y += ../common/gpio.c ../common/gpio_op.c ../common/gpio_eint_v2.c gpio.c gpio_eint.c
 all-y += ../common/i2c.c ../common/i2c_common.c i2c.c
+all-y += ../common/pll.c pll.c
 all-$(CONFIG_SPI_FLASH) += ../common/spi.c spi.c
 all-y += ../common/timer_prepare.c timer.c
 all-y += ../common/uart.c
@@ -13,7 +14,6 @@ bootblock-y += bootblock.c
 bootblock-y += efuse.c
 bootblock-y += ../common/mmu_operations.c
 bootblock-y += ../common/mtcmos.c mtcmos.c
-bootblock-y += ../common/pll.c pll.c
 bootblock-y += ../common/wdt.c ../common/wdt_req.c wdt.c
 
 romstage-y += ../common/cbmem.c
@@ -26,7 +26,6 @@ romstage-y += ../common/memory.c ../common/memory_test.c ../common/memory_type.c
 romstage-y += ../common/mmu_operations.c ../common/mmu_cmops.c
 romstage-y += ../common/mt6315.c mt6315.c
 romstage-y += ../common/mt6359p.c mt6359p.c
-romstage-y += ../common/pll.c pll.c
 romstage-y += ../common/pmif.c ../common/pmif_clk.c ../common/pmif_init.c pmif_clk.c
 romstage-y += ../common/pmif_spi.c pmif_spi.c
 romstage-y += ../common/pmif_spmi.c pmif_spmi.c
@@ -34,6 +33,8 @@ romstage-y += ../common/rtc.c ../common/rtc_osc_init.c ../common/rtc_mt6359p.c
 
 ramstage-y += ../common/auxadc.c
 ramstage-$(CONFIG_ARM64_USE_ARM_TRUSTED_FIRMWARE) += ../common/bl31.c
+ramstage-y += ../common/ddp.c ddp.c
+ramstage-y += ../common/display.c
 ramstage-y += ../common/dpm.c ../common/dpm_v2.c
 ramstage-y += ../common/dp/dp_intf_v2.c
 ramstage-y += ../common/dp/dptx_common.c ../common/dp/dptx_v2.c dptx.c
diff --git a/src/soc/mediatek/mt8189/ddp.c b/src/soc/mediatek/mt8189/ddp.c
new file mode 100644
index 0000000000..32c3b5b12f
--- /dev/null
+++ b/src/soc/mediatek/mt8189/ddp.c
@@ -0,0 +1,151 @@
+/* SPDX-License-Identifier: GPL-2.0-only OR MIT */
+
+#include <console/console.h>
+#include <edid.h>
+#include <soc/addressmap.h>
+#include <soc/ddp.h>
+#include <device/mmio.h>
+
+static void disp_config_main_path_connection(enum disp_path_sel path)
+{
+	/* Main path: OVL0->RDMA0->DVO0 */
+	write32(&mmsys_cfg->disp_ovl0_bgclr_mout_en, 0x1);
+	write32(&mmsys_cfg->disp_ovl0_out0_mout_en, 0x2);
+	write32(&mmsys_cfg->disp_rdma0_sel_in, 0x1);
+	write32(&mmsys_cfg->disp_rdma0_rsz0_sout_sel, 0x0);
+	write32(&mmsys_cfg->ovl_pq_out_cross1_mout_en, 0x10);
+	write32(&mmsys_cfg->comp_out_cross4_mout_en, 0x02);
+	printk(BIOS_DEBUG,
+	       "%s: bgclr_mout_en: %#x ovl0_mout_en: %#x sel_in: %#x sout_sel: %#x"
+	       "cross1_mout_en: %#x cross4_mout_en: %#x\n",
+	       __func__, read32(&mmsys_cfg->disp_ovl0_bgclr_mout_en),
+	       read32(&mmsys_cfg->disp_ovl0_out0_mout_en),
+	       read32(&mmsys_cfg->disp_rdma0_sel_in),
+	       read32(&mmsys_cfg->disp_rdma0_rsz0_sout_sel),
+	       read32(&mmsys_cfg->ovl_pq_out_cross1_mout_en),
+	       read32(&mmsys_cfg->comp_out_cross4_mout_en));
+}
+
+static void disp_config_main_path_mutex(enum disp_path_sel path)
+{
+	write32(&disp_mutex->mutex[0].mod, MUTEX_MOD_MAIN_PATH);
+
+	/* Clock source from DVO0 */
+	write32(&disp_mutex->mutex[0].ctl,
+		MUTEX_SOF_DVO | (MUTEX_SOF_DVO << 7));
+	write32(&disp_mutex->mutex[0].en, BIT(0));
+	printk(BIOS_DEBUG, "%s: mutex_mod: %#x ctl %#x\n",
+	       __func__, read32(&disp_mutex->mutex[0].mod), read32(&disp_mutex->mutex[0].ctl));
+}
+
+static void ovl_layer_smi_id_en(u32 idx)
+{
+	setbits32(&disp_ovl[idx]->datapath_con, BIT(0));
+}
+
+static void ovl_layer_gclast_en(u32 idx)
+{
+	setbits32(&disp_ovl[idx]->datapath_con, BIT(24));
+	setbits32(&disp_ovl[idx]->datapath_con, BIT(25));
+}
+
+static void ovl_layer_output_clamp_en(u32 idx)
+{
+	setbits32(&disp_ovl[idx]->datapath_con, BIT(26));
+}
+
+static void ovl_layer_en(u32 idx)
+{
+	setbits32(&disp_ovl[idx]->en, BIT(0));
+}
+
+static void main_disp_path_setup(u32 width, u32 height, u32 vrefresh, enum disp_path_sel path)
+{
+	u32 idx;
+	const u32 pixel_clk = width * height * vrefresh;
+
+	for (idx = 0; idx < MAIN_PATH_OVL_NR; idx++) {
+		/* Set OVL background color to blue */
+		ovl_set_roi(idx, width, height, idx ? 0 : 0xff0000ff);
+		ovl_layer_smi_id_en(idx);
+		ovl_layer_gclast_en(idx);
+		ovl_layer_output_clamp_en(idx);
+		ovl_layer_en(idx);
+	}
+
+	rdma_config(width, height, pixel_clk, 5 * KiB);
+	disp_config_main_path_connection(path);
+	disp_config_main_path_mutex(path);
+}
+
+static void disp_clock_on(void)
+{
+	clrbits32(&mmsys_cfg->mmsys_cg_con0, CG_CON0_ALL);
+	clrbits32(&mmsys_cfg->mmsys_cg_con1, CG_CON0_ALL);
+	printk(BIOS_DEBUG, "%s: disp_clock: [%#x %#x]\n",
+	       __func__, read32(&mmsys_cfg->mmsys_cg_con0), read32(&mmsys_cfg->mmsys_cg_con1));
+}
+
+void mtk_ddp_init(void)
+{
+	int i;
+
+	disp_clock_on();
+
+	printk(BIOS_DEBUG, "%s: shadow: %#x %#x, secure before: [%#x %#x %#x] larb: %x\n",
+	       __func__,
+	       read32(&mmsys_cfg->disp_bypass_mux_shadow),
+	       read32(&mmsys_cfg->disp_crossbar_con),
+	       read32(&mmsys_cfg->mmsys_security_disable),
+	       read32(&mmsys_cfg->mmsys_security_disable1),
+	       read32(&mmsys_cfg->mmsys_security_disable2),
+	       read32(&smi_larb0->port_l0_ovl_rdma[0]));
+
+	/* Turn off M4U port */
+	for (i = 0; i < RDMA_PORT_NR; i++) {
+		write32(&smi_larb0->port_l0_ovl_rdma[i], 0);
+		write32(&smi_larb1->port_l0_ovl_rdma[i], 0);
+	}
+	/* disable shadow */
+	write32(&mmsys_cfg->disp_bypass_mux_shadow, 0x1);
+	write32(&mmsys_cfg->disp_crossbar_con, 0x00FF0000);
+	/* disable secure mode */
+	write32(&mmsys_cfg->mmsys_security_disable, 0xFFFFFFFF);
+	write32(&mmsys_cfg->mmsys_security_disable1, 0xFFFFFFFF);
+	write32(&mmsys_cfg->mmsys_security_disable2, 0xFFFFFFFF);
+	printk(BIOS_DEBUG, "%s: shadow: %#x %#x, secure: [%#x %#x %#x] larb: %#x\n",
+	       __func__,
+	       read32(&mmsys_cfg->disp_bypass_mux_shadow),
+	       read32(&mmsys_cfg->disp_crossbar_con),
+	       read32(&mmsys_cfg->mmsys_security_disable),
+	       read32(&mmsys_cfg->mmsys_security_disable1),
+	       read32(&mmsys_cfg->mmsys_security_disable2),
+	       read32(&smi_larb0->port_l0_ovl_rdma[0]));
+}
+
+void mtk_ddp_mode_set(const struct edid *edid, enum disp_path_sel path)
+{
+	u32 fmt = OVL_INFMT_RGBA8888;
+	u32 bpp = edid->framebuffer_bits_per_pixel / 8;
+	u32 width = edid->mode.ha;
+	u32 height = edid->mode.va;
+	u32 vrefresh_hz = edid->mode.refresh;
+
+	printk(BIOS_INFO, "%s: display resolution: %dx%d@%d bpp %d\n",
+	       __func__, width, height, vrefresh_hz, bpp);
+
+	if (!vrefresh_hz) {
+		if (!width || !height)
+			vrefresh_hz = 60;
+		else
+			vrefresh_hz = edid->mode.pixel_clock * 1000 /
+				   ((width + edid->mode.hbl) * (height + edid->mode.vbl));
+
+		printk(BIOS_WARNING, "%s: vrefresh is not provided; using %d\n",
+		       __func__, vrefresh_hz);
+	}
+
+	main_disp_path_setup(width, height, vrefresh_hz, path);
+	rdma_start();
+	ovl_layer_config(fmt, bpp, width, height);
+}
diff --git a/src/soc/mediatek/mt8189/include/soc/addressmap.h b/src/soc/mediatek/mt8189/include/soc/addressmap.h
index fc8bf3f03a..b591d1c294 100644
--- a/src/soc/mediatek/mt8189/include/soc/addressmap.h
+++ b/src/soc/mediatek/mt8189/include/soc/addressmap.h
@@ -105,8 +105,20 @@ enum {
 	IMP_IIC_WRAP_EN_BASE		= IO_PHYS + 0x01F32000,
 	MFGCFG_BASE			= IO_PHYS + 0x03FBF000,
 	MMSYS_CONFIG_BASE		= IO_PHYS + 0x04000000,
+	DISP_MUTEX_BASE			= IO_PHYS + 0x04001000,
+	DISP_OVL0_BASE			= IO_PHYS + 0x04002000,
+	DISP_OVL1_BASE			= IO_PHYS + 0x04003000,
+	DISP_RDMA0_BASE			= IO_PHYS + 0x04006000,
+	DISP_COLOR0_BASE		= IO_PHYS + 0x04008000,
+	DISP_CCORR0_BASE		= IO_PHYS + 0x0400A000,
+	DISP_CCORR2_BASE		= IO_PHYS + 0x0400C000,
+	DISP_AAL0_BASE			= IO_PHYS + 0x0400E000,
+	DISP_GAMMA0_BASE		= IO_PHYS + 0x04010000,
+	DISP_DITHER0_BASE		= IO_PHYS + 0x04012000,
 	DSI0_BASE			= IO_PHYS + 0x04016000,
 	DISP_DVO0			= IO_PHYS + 0x04017000,
+	SMI_LARB0			= IO_PHYS + 0x0401C000,
+	SMI_LARB1			= IO_PHYS + 0x0401D000,
 	IMGSYS1_BASE			= IO_PHYS + 0x05020000,
 	IMGSYS2_BASE			= IO_PHYS + 0x05820000,
 	VDEC_CORE_BASE			= IO_PHYS + 0x0602F000,
diff --git a/src/soc/mediatek/mt8189/include/soc/ddp.h b/src/soc/mediatek/mt8189/include/soc/ddp.h
new file mode 100644
index 0000000000..feb975af8b
--- /dev/null
+++ b/src/soc/mediatek/mt8189/include/soc/ddp.h
@@ -0,0 +1,303 @@
+/* SPDX-License-Identifier: GPL-2.0-only OR MIT */
+
+#ifndef _SOC_MEDIATEK_MT8189_DDP_H_
+#define _SOC_MEDIATEK_MT8189_DDP_H_
+
+#include <device/mmio.h>
+#include <soc/addressmap.h>
+#include <soc/ddp_common.h>
+#include <soc/display.h>
+#include <types.h>
+
+#define MAIN_PATH_OVL_NR	1
+#define RDMA_PORT_NR		5
+
+struct smi_larbx_regs {
+	u32 reserved[992];
+	u32 port_l0_ovl_rdma[RDMA_PORT_NR];
+};
+check_member(smi_larbx_regs, port_l0_ovl_rdma[0], 0xF80);
+
+struct mmsys_cfg_regs {
+	u32 reserved_0x000[64];
+	u32 mmsys_cg_con0;
+	u32 mmsys_cg_set0;
+	u32 mmsys_cg_clr0;
+	u32 reserved_0x10c;
+	u32 mmsys_cg_con1;
+	u32 mmsys_cg_set1;
+	u32 mmsys_cg_clr1;
+	u32 reserved_0x11c[569];
+	u32 mmsys_security_disable;
+	u32 mmsys_security_disable1;
+	u32 mmsys_security_disable2;
+	u32 reserved_0xa0c[125];
+	u32 disp_bypass_mux_shadow;
+	u32 disp_mout_rst;
+	u32 reserved_0xc08;
+	u32 disp_crossbar_con;
+	u32 disp_ovl0_out0_mout_en;
+	u32 disp_ovl1_out0_mout_en;
+	u32 disp_rsz0_mout_en;
+	u32 disp_rsz1_mout_en;
+	u32 reserved_0xc20[21];
+	u32 ovl_pq_out_cross0_mout_en;
+	u32 ovl_pq_out_cross1_mout_en;
+	u32 ovl_pq_out_cross2_mout_en;
+	u32 ovl_pq_out_cross3_mout_en;
+	u32 ovl_pq_out_cross4_mout_en;
+	u32 ovl_pq_out_cross5_mout_en;
+	u32 ovl_pq_out_cross0_sel_in;
+	u32 ovl_pq_out_cross1_sel_in;
+	u32 ovl_pq_out_cross2_sel_in;
+	u32 ovl_pq_out_cross3_sel_in;
+	u32 ovl_pq_out_cross4_sel_in;
+	u32 ovl_pq_out_cross5_sel_in;
+	u32 reserved_0xca4[51];
+	u32 comp_out_cross0_mout_en;
+	u32 comp_out_cross1_mout_en;
+	u32 comp_out_cross2_mout_en;
+	u32 comp_out_cross3_mout_en;
+	u32 comp_out_cross4_mout_en;
+	u32 comp_out_cross5_mout_en;
+	u32 comp_out_cross0_sel_in;
+	u32 comp_out_cross1_sel_in;
+	u32 comp_out_cross2_sel_in;
+	u32 comp_out_cross3_sel_in;
+	u32 comp_out_cross4_sel_in;
+	u32 comp_out_cross5_sel_in;
+	u32 reserved_0xda0[24];
+	u32 disp_rdma0_rsz0_sout_sel;
+	u32 disp_rdma0_sel_in;
+	u32 disp_rdma1_rsz1_sout_sel;
+	u32 disp_rdma1_sel_in;
+	u32 disp_rsz0_sel_in;
+	u32 disp_rsz1_sel_in;
+	u32 reserved_0xe18[3];
+	u32 disp_ovl0_bgclr_mout_en;
+	u32 disp_ovl1_bgclr_mout_en;
+};
+check_member(mmsys_cfg_regs, mmsys_cg_con0, 0x100);
+check_member(mmsys_cfg_regs, mmsys_cg_set0, 0x104);
+check_member(mmsys_cfg_regs, mmsys_cg_clr0, 0x108);
+check_member(mmsys_cfg_regs, mmsys_cg_con1, 0x110);
+check_member(mmsys_cfg_regs, mmsys_cg_set1, 0x114);
+check_member(mmsys_cfg_regs, mmsys_cg_clr1, 0x118);
+check_member(mmsys_cfg_regs, mmsys_security_disable, 0xA00);
+check_member(mmsys_cfg_regs, mmsys_security_disable1, 0xA04);
+check_member(mmsys_cfg_regs, mmsys_security_disable2, 0xA08);
+check_member(mmsys_cfg_regs, disp_bypass_mux_shadow, 0xC00);
+check_member(mmsys_cfg_regs, disp_crossbar_con, 0xC0C);
+check_member(mmsys_cfg_regs, disp_ovl0_out0_mout_en, 0xC10);
+check_member(mmsys_cfg_regs, ovl_pq_out_cross1_mout_en, 0xC78);
+check_member(mmsys_cfg_regs, comp_out_cross4_mout_en, 0xD80);
+check_member(mmsys_cfg_regs, disp_rdma0_rsz0_sout_sel, 0xE00);
+check_member(mmsys_cfg_regs, disp_rdma0_sel_in, 0xE04);
+check_member(mmsys_cfg_regs, disp_ovl0_bgclr_mout_en, 0xE24);
+
+struct disp_mutex_regs {
+	u32 inten;
+	u32 intsta;
+	u32 reserved0[6];
+	struct {
+		u32 en;
+		u32 dummy;
+		u32 rst;
+		u32 ctl;
+		u32 mod;
+		u32 reserved[3];
+	} mutex[16];
+};
+
+struct disp_ccorr_regs {
+	u32 en;
+	u32 reset;
+	u32 inten;
+	u32 intsta;
+	u32 status;
+	u32 reserved0[3];
+	u32 cfg;
+	u32 reserved1[3];
+	u32 size;
+	u32 reserved2[27];
+	u32 shadow;
+};
+check_member(disp_ccorr_regs, shadow, 0xA0);
+
+struct disp_gamma_regs {
+	u32 en;
+	u32 reset;
+	u32 inten;
+	u32 intsta;
+	u32 status;
+	u32 reserved0[3];
+	u32 cfg;
+	u32 reserved1[3];
+	u32 size;
+};
+check_member(disp_gamma_regs, size, 0x30);
+
+struct disp_aal_regs {
+	u32 en;
+	u32 reset;
+	u32 inten;
+	u32 intsta;
+	u32 status;
+	u32 reserved0[3];
+	u32 cfg;
+	u32 reserved1[3];
+	u32 size;
+	u32 reserved2[47];
+	u32 shadow;
+	u32 reserved3[249];
+	u32 output_size;
+};
+check_member(disp_aal_regs, shadow, 0xF0);
+check_member(disp_aal_regs, output_size, 0x4D8);
+
+struct disp_postmask_regs {
+	u32 en;
+	u32 reset;
+	u32 inten;
+	u32 intsta;
+	u32 reserved0[4];
+	u32 cfg;
+	u32 reserved1[3];
+	u32 size;
+};
+check_member(disp_postmask_regs, size, 0x30);
+
+struct disp_dither_regs {
+	u32 en;
+	u32 reset;
+	u32 inten;
+	u32 intsta;
+	u32 status;
+	u32 reserved0[3];
+	u32 cfg;
+	u32 reserved1[3];
+	u32 size;
+	u32 reserved2[51];
+	u32 disp_dither_0;
+};
+check_member(disp_dither_regs, disp_dither_0, 0x100);
+
+/*
+ * DISP_REG_CONFIG_MMSYS_CG_CON0
+ * Configures free-run clock gating 0
+ * 0: Enable clock
+ * 1: Clock gating
+ */
+enum {
+	CG_CON0_DISP_OVL0	= BIT(0),
+	CG_CON0_DISP_RSZ0	= BIT(2),
+	CG_CON0_DISP_RDMA0	= BIT(4),
+	CG_CON0_DISP_COLOR0	= BIT(6),
+	CG_CON0_DISP_CCORR0	= BIT(8),
+	CG_CON0_DISP_CCORR2	= BIT(10),
+	CG_CON0_DISP_AAL0	= BIT(12),
+	CG_CON0_DISP_GAMMA0	= BIT(14),
+	CG_CON0_DISP_DITHER0	= BIT(16),
+	CG_CON0_DISP_DSC_WRAP0	= BIT(18),
+	CG_CON0_DISP_MERGE0	= BIT(19),
+	CG_CON0_DISP_DVO0	= BIT(20),
+	CG_CON0_DISP_WDMA0	= BIT(24),
+	CG_CON0_DISP_FAKE_ENG0	= BIT(26),
+	CG_CON0_SMI_LARB	= BIT(28),
+	CG_CON0_DISP_MUTEX0	= BIT(29),
+	CG_CON0_DISPSYS_CONFIG	= BIT(30),
+	CG_CON0_DISP_ALL	= CG_CON0_DISP_OVL0 |
+				  CG_CON0_DISP_RSZ0 |
+				  CG_CON0_DISP_RDMA0 |
+				  CG_CON0_DISP_COLOR0 |
+				  CG_CON0_DISP_CCORR0 |
+				  CG_CON0_DISP_CCORR2 |
+				  CG_CON0_DISP_AAL0 |
+				  CG_CON0_DISP_GAMMA0 |
+				  CG_CON0_DISP_DITHER0 |
+				  CG_CON0_DISP_DVO0 |
+				  CG_CON0_SMI_LARB |
+				  CG_CON0_DISP_MUTEX0 |
+				  CG_CON0_DISPSYS_CONFIG,
+	CG_CON0_ALL		= 0xFFFFFFFF,
+};
+
+enum {
+	CG_CON1_DISP_DSI0		= BIT(0),
+	CG_CON1_LVDS_ENCODER		= BIT(1),
+	CG_CON1_DPI_DPI0		= BIT(2),
+	CG_CON1_DISP_DVO		= BIT(3),
+	CG_CON1_DP_INTF			= BIT(4),
+	CG_CON1_LVDS_ENCODER1		= BIT(5),
+	CG_CON1_DISP_DVO1		= BIT(6),
+	CG_CON1_DISP_ALL		= CG_CON1_DISP_DSI0 |
+					  CG_CON1_LVDS_ENCODER |
+					  CG_CON1_DPI_DPI0 |
+					  CG_CON1_DISP_DVO |
+					  CG_CON1_DP_INTF |
+					  CG_CON1_LVDS_ENCODER1 |
+					  CG_CON1_DISP_DVO1,
+	CG_CON1_ALL			= 0xFFFFFFFF,
+};
+
+DEFINE_BITFIELD(DISP_OVL0_BGCLR_MOUT_EN, 1, 0)
+DEFINE_BITFIELD(DISP_OVL0_OUT0_MOUT_EN, 2, 0)
+DEFINE_BITFIELD(DISP_RDMA0_SEL_IN, 0, 0)
+DEFINE_BITFIELD(DISP_OVL0_MOUT_EN, 2, 0)
+DEFINE_BITFIELD(DISP_RDMA0_SOUT_SEL, 1, 0)
+DEFINE_BITFIELD(DISP_OVL0_PQ_OUT_CROSSBAR_EN, 5, 0)
+DEFINE_BITFIELD(DISP_COMP_OUT_CROSSBAR, 5, 0)
+
+DEFINE_BIT(SMI_ID_EN, 0)
+DEFINE_BIT(PQ_CFG_RELAY_MODE, 0)
+DEFINE_BIT(PQ_CFG_ENGINE_EN, 1)
+
+#define DISP_MOUT_OVL_TO_BLENDOUT	BIT(0)
+#define DISP_OVL0_MOUT_TO_RDMA0		BIT(1)
+#define DISP_RDMA0_FROM_OVL0		BIT(0)
+#define DISP_OVL0_GO_BLEND		BIT(0)
+#define DISP_RDMA0_SOUT_TO_COLOR0	1
+#define DISP_RDMA0_SOUT_TO_CROSSBAR	0
+#define DISP_PQ_OUT_CROSSBAR_TO_DVO0	BIT(0)
+#define DISP_PQ_OUT_CROSSBAR_TO_CROSSBAR4	BIT(4)
+#define DISP_DVO0_FROM_DITHER0		1
+#define DISP_DVO0_FROM_CROSSBAR4		BIT(1)
+
+#define SMI_ID_EN_VAL			BIT(0)
+
+enum {
+	MUTEX_MOD_DISP_OVL0		= BIT(0),
+	MUTEX_MOD_DISP_RDMA0		= BIT(4),
+	MUTEX_MOD_DISP_COLOR0		= BIT(4),
+	MUTEX_MOD_DISP_CCORR0		= BIT(5),
+	MUTEX_MOD_DISP_CCORR2		= BIT(6),
+	MUTEX_MOD_DISP_AAL0		= BIT(7),
+	MUTEX_MOD_DISP_GAMMA0		= BIT(8),
+	MUTEX_MOD_DISP_DITHER0		= BIT(10),
+
+	MUTEX_MOD_MAIN_PATH		= MUTEX_MOD_DISP_OVL0 |
+					  MUTEX_MOD_DISP_RDMA0,
+};
+
+enum {
+	MUTEX_SOF_SINGLE_MODE = 0,
+	MUTEX_SOF_DSI0 = 1,
+	MUTEX_SOF_DPI0 = 2,
+	MUTEX_SOF_DVO = 5,
+};
+
+#define PQ_EN		BIT(0)
+#define PQ_RELAY_MODE	BIT(0)
+#define PQ_ENGINE_EN	BIT(1)
+
+static struct smi_larbx_regs *const smi_larb0 = (void *)SMI_LARB0;
+static struct smi_larbx_regs *const smi_larb1 = (void *)SMI_LARB1;
+static struct mmsys_cfg_regs *const mmsys_cfg = (void *)MMSYS_CONFIG_BASE;
+static struct disp_mutex_regs *const disp_mutex = (void *)DISP_MUTEX_BASE;
+static struct disp_ccorr_regs *const disp_ccorr = (void *)DISP_CCORR0_BASE;
+static struct disp_ccorr_regs *const disp_ccorr2 = (void *)DISP_CCORR2_BASE;
+static struct disp_aal_regs *const disp_aal = (void *)DISP_AAL0_BASE;
+static struct disp_gamma_regs *const disp_gamma = (void *)DISP_GAMMA0_BASE;
+static struct disp_dither_regs *const disp_dither = (void *)DISP_DITHER0_BASE;
+
+#endif
diff --git a/src/soc/mediatek/mt8189/include/soc/dsi.h b/src/soc/mediatek/mt8189/include/soc/dsi.h
new file mode 100644
index 0000000000..443e743b87
--- /dev/null
+++ b/src/soc/mediatek/mt8189/include/soc/dsi.h
@@ -0,0 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef SOC_MEDIATEK_MT8189_DSI_H
+#define SOC_MEDIATEK_MT8189_DSI_H
+
+#include <soc/dsi_common.h>
+
+#endif

From 4ef51ffbd7e0437de15011929257b6286da7f8f9 Mon Sep 17 00:00:00 2001
From: Vince Liu <vince-wl.liu@mediatek.corp-partner.google.com>
Date: Mon, 16 Jun 2025 22:43:58 +0800
Subject: [PATCH 1402/3886] mb/google/skywalker: Add panel driver in mainboard

Add panel driver in mainboard for skywalker project.

BUG=b:400886838,b:425272330
BRANCH=none
TEST=check edp training pass and show log:
EQ training pass

Change-Id: I7352a6728237842a6819b7129c61a1d4c7646fcb
Signed-off-by: Bincai Liu <bincai.liu@mediatek.corp-partner.google.com>
Signed-off-by: Cong Yang <yangcong5@huaqin.corp-partner.google.com>
Signed-off-by: Vince Liu <vince-wl.liu@mediatek.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88170
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/google/skywalker/Makefile.mk |  1 +
 src/mainboard/google/skywalker/chromeos.c  |  6 ++++
 src/mainboard/google/skywalker/gpio.h      |  4 +++
 src/mainboard/google/skywalker/panel.c     | 32 ++++++++++++++++++++++
 4 files changed, 43 insertions(+)
 create mode 100644 src/mainboard/google/skywalker/panel.c

diff --git a/src/mainboard/google/skywalker/Makefile.mk b/src/mainboard/google/skywalker/Makefile.mk
index 3e5bad3f37..ff3c1701de 100644
--- a/src/mainboard/google/skywalker/Makefile.mk
+++ b/src/mainboard/google/skywalker/Makefile.mk
@@ -11,4 +11,5 @@ romstage-y += regulator.c
 
 ramstage-y += boardid.c
 ramstage-y += mainboard.c
+ramstage-y += panel.c
 ramstage-y += regulator.c
diff --git a/src/mainboard/google/skywalker/chromeos.c b/src/mainboard/google/skywalker/chromeos.c
index 700d815c68..2bf47ed797 100644
--- a/src/mainboard/google/skywalker/chromeos.c
+++ b/src/mainboard/google/skywalker/chromeos.c
@@ -67,6 +67,12 @@ void fill_lb_gpios(struct lb_gpios *gpios)
 		};
 		lb_add_gpios(gpios, alc5645_gpios, ARRAY_SIZE(alc5645_gpios));
 	}
+
+	struct lb_gpio edp_pwm_backlight_gpios[] = {
+		{GPIO_BL_PWM_1V8.id, ACTIVE_HIGH, -1, "PWM control"},
+		{GPIO_AP_EDP_BKLTEN.id, ACTIVE_HIGH, -1, "backlight enable"},
+	};
+	lb_add_gpios(gpios, edp_pwm_backlight_gpios, ARRAY_SIZE(edp_pwm_backlight_gpios));
 }
 
 int cr50_plat_irq_status(void)
diff --git a/src/mainboard/google/skywalker/gpio.h b/src/mainboard/google/skywalker/gpio.h
index 4398a6cbf3..a55a01aab1 100644
--- a/src/mainboard/google/skywalker/gpio.h
+++ b/src/mainboard/google/skywalker/gpio.h
@@ -35,6 +35,10 @@
 #define GPIO_I2SOUT0_BCK		GPIO(I2SOUT0_BCK)
 #define GPIO_I2SOUT0_LRCK		GPIO(I2SOUT0_LRCK)
 #define GPIO_I2SOUT0_DOUT		GPIO(I2SOUT0_DO)
+#define GPIO_BL_PWM_1V8			GPIO(DISP_PWM0)
+#define GPIO_AP_EDP_BKLTEN		GPIO(GPIO13)
+#define GPIO_EN_PP3300_EDP_X		GPIO(DSI_LCM_RST)
+#define GPIO_EDP_HPD_1V8		GPIO(EDP_TX_HPD)
 
 void setup_chromeos_gpios(void);
 
diff --git a/src/mainboard/google/skywalker/panel.c b/src/mainboard/google/skywalker/panel.c
new file mode 100644
index 0000000000..b0cb052881
--- /dev/null
+++ b/src/mainboard/google/skywalker/panel.c
@@ -0,0 +1,32 @@
+/* SPDX-License-Identifier: GPL-2.0-only OR MIT */
+
+#include <gpio.h>
+#include <soc/display.h>
+
+#include "gpio.h"
+
+/* Set up backlight control pins as output pins, and set them to power off by default */
+static void configure_backlight(void)
+{
+	gpio_output(GPIO_AP_EDP_BKLTEN, 0);
+	gpio_output(GPIO_BL_PWM_1V8, 0);
+}
+
+static void power_on_panel(void)
+{
+	gpio_output(GPIO_EN_PP3300_EDP_X, 1);
+	gpio_set_mode(GPIO_EDP_HPD_1V8, GPIO_FUNC(EDP_TX_HPD, EDP_TX_HPD));
+	gpio_set_pull(GPIO_EDP_HPD_1V8, GPIO_PULL_DISABLE, GPIO_PULL_UP);
+}
+
+static struct panel_description panel = {
+	.configure_backlight = configure_backlight,
+	.power_on = power_on_panel,
+	.disp_path = DISP_PATH_EDP,
+	.orientation = LB_FB_ORIENTATION_NORMAL,
+};
+
+struct panel_description *get_active_panel(void)
+{
+	return &panel;
+}

From 056405a10d94483141e3beb6a9b590be802fb608 Mon Sep 17 00:00:00 2001
From: Nick Vaccaro <nvaccaro@google.com>
Date: Tue, 17 Jun 2025 14:35:59 -0700
Subject: [PATCH 1403/3886] mb/google/ocelot: convert variants for use with ES
 silicon

The Ocelot variants must support ES silicon as well as QS silicon.  This
CL changes ocelot to ocelot4es, changes ocelotite to ocelotite4es, and
changes ocelotmchp to ocelotmchp4es.

BUG=b:425397790
TEST=`emerge-ocelot` and verify it builds without errors.

Change-Id: Iac0700688e7f616477bf462c5734a70110f9d6d7
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88134
Reviewed-by: Avi Uday <aviuday@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/google/ocelot/Kconfig             | 17 +++++++++++++----
 src/mainboard/google/ocelot/Kconfig.name        |  9 +++++++++
 .../baseboard/ocelot/include/baseboard/gpio.h   |  4 +---
 3 files changed, 23 insertions(+), 7 deletions(-)

diff --git a/src/mainboard/google/ocelot/Kconfig b/src/mainboard/google/ocelot/Kconfig
index 582084ee83..5e8a60b96f 100644
--- a/src/mainboard/google/ocelot/Kconfig
+++ b/src/mainboard/google/ocelot/Kconfig
@@ -73,6 +73,15 @@ config BOARD_GOOGLE_OCELOTITE
 config BOARD_GOOGLE_OCELOTMCHP
 	select BOARD_GOOGLE_MODEL_OCELOT
 
+config BOARD_GOOGLE_OCELOT4ES
+	select BOARD_GOOGLE_MODEL_OCELOT
+
+config BOARD_GOOGLE_OCELOTITE4ES
+	select BOARD_GOOGLE_MODEL_OCELOT
+
+config BOARD_GOOGLE_OCELOTMCHP4ES
+	select BOARD_GOOGLE_MODEL_OCELOT
+
 if BOARD_GOOGLE_OCELOT_COMMON
 
 config BASEBOARD_DIR
@@ -120,6 +129,9 @@ config MAINBOARD_FAMILY
 
 config MAINBOARD_PART_NUMBER
 	default "Ocelot" if BOARD_GOOGLE_OCELOT
+	default "Ocelot4ES" if BOARD_GOOGLE_OCELOT4ES
+	default "Ocelotite4ES" if BOARD_GOOGLE_OCELOTITE4ES
+	default "Ocelotmchp4ES" if BOARD_GOOGLE_OCELOTMCHP4ES
 	default "Ocelotite" if BOARD_GOOGLE_OCELOTITE
 	default "Ocelotmchp" if BOARD_GOOGLE_OCELOTMCHP
 
@@ -141,10 +153,7 @@ config USE_PM_ACPI_TIMER
 
 config VARIANT_DIR
 	string
-	default "ocelot" if \
-		BOARD_GOOGLE_OCELOT || \
-		BOARD_GOOGLE_OCELOTITE || \
-		BOARD_GOOGLE_OCELOTMCHP
+	default "ocelot" if BOARD_GOOGLE_MODEL_OCELOT
 
 config OVERRIDE_DEVICETREE
 	default "variants/\$(CONFIG_VARIANT_DIR)/overridetree.cb"
diff --git a/src/mainboard/google/ocelot/Kconfig.name b/src/mainboard/google/ocelot/Kconfig.name
index 3be6f46017..71a69cb31a 100644
--- a/src/mainboard/google/ocelot/Kconfig.name
+++ b/src/mainboard/google/ocelot/Kconfig.name
@@ -10,3 +10,12 @@ config BOARD_GOOGLE_OCELOTITE
 
 config BOARD_GOOGLE_OCELOTMCHP
 	bool "-> Ocelotmchp"
+
+config BOARD_GOOGLE_OCELOT4ES
+	bool "-> Ocelot4ES"
+
+config BOARD_GOOGLE_OCELOTITE4ES
+	bool "-> Ocelotite4ES"
+
+config BOARD_GOOGLE_OCELOTMCHP4ES
+	bool "-> Ocelotmchp4ES"
diff --git a/src/mainboard/google/ocelot/variants/baseboard/ocelot/include/baseboard/gpio.h b/src/mainboard/google/ocelot/variants/baseboard/ocelot/include/baseboard/gpio.h
index 6a43d70708..ddc771eed8 100644
--- a/src/mainboard/google/ocelot/variants/baseboard/ocelot/include/baseboard/gpio.h
+++ b/src/mainboard/google/ocelot/variants/baseboard/ocelot/include/baseboard/gpio.h
@@ -13,9 +13,7 @@
  * GPIO_PCH_WP - WP signal to PCH
  */
 //TODO for Nuvo: #define EC_SYNC_IRQ	GPP_E07_IRQ
-#if CONFIG(BOARD_GOOGLE_OCELOT) || \
-	CONFIG(BOARD_GOOGLE_OCELOTITE) || \
-	CONFIG(BOARD_GOOGLE_OCELOTMCHP)
+#if CONFIG(BOARD_GOOGLE_MODEL_OCELOT)
  #define EC_SYNC_IRQ	0 /* Not Connected */
 #endif
 #define GPIO_PCH_WP	GPP_D02

From cc0a410ff509017990857dbc9106152f6f47f999 Mon Sep 17 00:00:00 2001
From: Vince Liu <vince-wl.liu@mediatek.corp-partner.google.com>
Date: Fri, 20 Jun 2025 16:08:00 +0800
Subject: [PATCH 1404/3886] soc/mediatek/dp: Correct eDP register settings for
 dptx_v2

SoCs with dptx_v2 (such as MT8196) use a different eDP MAC design from
old SoCs with dptx_v1. The formulas for register calculation are
different:
- The horizontal blanking (REG_3160_DP_ENCODER0_P0) is hsync + hbp + hfp
on MT8196, while on older SoCs it is hsync + hbp.
- The vertical blanking (REG_3174_DP_ENCODER0_P0) is vsync + vbp + vfp
on MT8196, but vsync + vbp on earlier SoCs.
The current formula for MT8196 only works correctly when ha/va are
multiples of 4 and hfp/vfp are 0. The new formula fixes display errors
at resolutions like 1366x768 (ha=1366, hfp=48).
To distinguish these differences, an edp_version parameter is added.

Also update the following settings for correct configuration:
- Set AUX_RX_UI_CNT_THR_AUX_FOR_26M to 14 to correct the previous
incorrect setting.
- Fix DVO_TGEN_H1 calculation for the case where ha is not a multiple
of 4 (such as 1366).

BUG=b:400886838
BRANCH=rauru
TEST=Check the display function on Navi

Signed-off-by: Bincai Liu <bincai.liu@mediatek.corp-partner.google.com>
Signed-off-by: Vince Liu <vince-wl.liu@mediatek.corp-partner.google.com>
Change-Id: Id0ae6845ce6a06cdcbc3dd9b1f8a63e2890c3b24
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88188
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
---
 src/soc/mediatek/common/dp/dp_intf_v2.c              | 2 +-
 src/soc/mediatek/common/dp/dptx_common.c             | 1 +
 src/soc/mediatek/common/dp/dptx_hal_common.c         | 8 +++++---
 src/soc/mediatek/common/dp/include/soc/dp_intf_v1.h  | 2 ++
 src/soc/mediatek/common/dp/include/soc/dp_intf_v2.h  | 2 ++
 src/soc/mediatek/common/dp/include/soc/dptx_common.h | 1 +
 src/soc/mediatek/common/dp/include/soc/dptx_reg_v2.h | 2 +-
 7 files changed, 13 insertions(+), 5 deletions(-)

diff --git a/src/soc/mediatek/common/dp/dp_intf_v2.c b/src/soc/mediatek/common/dp/dp_intf_v2.c
index 38bac4eb26..a659723042 100644
--- a/src/soc/mediatek/common/dp/dp_intf_v2.c
+++ b/src/soc/mediatek/common/dp/dp_intf_v2.c
@@ -68,7 +68,7 @@ static void mtk_dvo_config_fb_size(const struct mtk_dvo *dvo, u32 width, u32 hei
 	mtk_dvo_mask(dvo, DVO_PIC_SIZE, width << PIC_HSIZE_SHIFT, PIC_HSIZE_MASK);
 	mtk_dvo_mask(dvo, DVO_PIC_SIZE, height << PIC_VSIZE_SHIFT, PIC_VSIZE_MASK);
 
-	mtk_dvo_mask(dvo, DVO_TGEN_H1, (width / 4) << HACT_SHIFT, HACT_MASK);
+	mtk_dvo_mask(dvo, DVO_TGEN_H1, DIV_ROUND_UP(width, 4) << HACT_SHIFT, HACT_MASK);
 	mtk_dvo_mask(dvo, DVO_TGEN_V1, height << VACT_SHIFT, VACT_MASK);
 }
 
diff --git a/src/soc/mediatek/common/dp/dptx_common.c b/src/soc/mediatek/common/dp/dptx_common.c
index ac8f4527c2..d6747f78bc 100644
--- a/src/soc/mediatek/common/dp/dptx_common.c
+++ b/src/soc/mediatek/common/dp/dptx_common.c
@@ -253,6 +253,7 @@ void dptx_init_variable(struct mtk_dp *mtk_dp)
 	mtk_dp->has_dsc = false;
 	mtk_dp->has_fec = false;
 	mtk_dp->dsc_enable = false;
+	mtk_dp->edp_version = EDP_VERSION;
 }
 
 static inline bool dptx_check_res_sample_rate(const struct edid *edid)
diff --git a/src/soc/mediatek/common/dp/dptx_hal_common.c b/src/soc/mediatek/common/dp/dptx_hal_common.c
index 43fe2f5440..3e2a0b374a 100644
--- a/src/soc/mediatek/common/dp/dptx_hal_common.c
+++ b/src/soc/mediatek/common/dp/dptx_hal_common.c
@@ -107,7 +107,7 @@ void dptx_hal_bypassmsa_en(struct mtk_dp *mtk_dp, bool enable)
 
 void dptx_hal_set_msa(struct mtk_dp *mtk_dp)
 {
-	u32 va, vsync, vbp, vfp, vtotal, ha, hsync, hbp, hfp, htotal;
+	u32 va, vsync, vbp, vfp, vtotal, ha, hsync, hbp, hfp, htotal, val;
 	struct edid *edid = mtk_dp->edid;
 
 	va = edid->mode.va;
@@ -150,13 +150,15 @@ void dptx_hal_set_msa(struct mtk_dp *mtk_dp)
 	DP_WRITE2BYTE(mtk_dp, REG_3154_DP_ENCODER0_P0, htotal);
 	DP_WRITE2BYTE(mtk_dp, REG_3158_DP_ENCODER0_P0, hfp);
 	DP_WRITE2BYTE(mtk_dp, REG_315C_DP_ENCODER0_P0, hsync);
-	DP_WRITE2BYTE(mtk_dp, REG_3160_DP_ENCODER0_P0, hsync + hbp);
+	val = mtk_dp->edp_version == 1 ? hsync + hbp : hsync + hbp + hfp;
+	DP_WRITE2BYTE(mtk_dp, REG_3160_DP_ENCODER0_P0, val);
 	DP_WRITE2BYTE(mtk_dp, REG_3164_DP_ENCODER0_P0, ha);
 	/* vertical */
 	DP_WRITE2BYTE(mtk_dp, REG_3168_DP_ENCODER0_P0, vtotal);
 	DP_WRITE2BYTE(mtk_dp, REG_316C_DP_ENCODER0_P0, vfp);
 	DP_WRITE2BYTE(mtk_dp, REG_3170_DP_ENCODER0_P0, vsync);
-	DP_WRITE2BYTE(mtk_dp, REG_3174_DP_ENCODER0_P0, vsync + vbp);
+	val = mtk_dp->edp_version == 1 ? vsync + vbp : vsync + vbp + vfp;
+	DP_WRITE2BYTE(mtk_dp, REG_3174_DP_ENCODER0_P0, val);
 	DP_WRITE2BYTE(mtk_dp, REG_3178_DP_ENCODER0_P0, va);
 
 	printk(BIOS_INFO, "MSA:Htt(%d), Vtt(%d), Hact(%d), Vact(%d), FPS(%d)\n",
diff --git a/src/soc/mediatek/common/dp/include/soc/dp_intf_v1.h b/src/soc/mediatek/common/dp/include/soc/dp_intf_v1.h
index 18f7c76c9e..11dfb097a9 100644
--- a/src/soc/mediatek/common/dp/include/soc/dp_intf_v1.h
+++ b/src/soc/mediatek/common/dp/include/soc/dp_intf_v1.h
@@ -178,6 +178,8 @@
 #define MATRIX_BIT_MASK			(0x3 << 8)
 #define EXT_MATRIX_EN			BIT(12)
 
+#define EDP_VERSION			1
+
 enum mtk_dpintf_out_bit_num {
 	MTK_DPINTF_OUT_BIT_NUM_8BITS,
 	MTK_DPINTF_OUT_BIT_NUM_10BITS,
diff --git a/src/soc/mediatek/common/dp/include/soc/dp_intf_v2.h b/src/soc/mediatek/common/dp/include/soc/dp_intf_v2.h
index 293d5ead7a..9d40dcecff 100644
--- a/src/soc/mediatek/common/dp/include/soc/dp_intf_v2.h
+++ b/src/soc/mediatek/common/dp/include/soc/dp_intf_v2.h
@@ -165,6 +165,8 @@
 #define DVO_BUF_SODI_HIGHT	0x230
 #define DVO_BUF_SODI_LOW	0x234
 
+#define EDP_VERSION		2
+
 enum mtk_dvo_golden_setting_level {
 	MTK_DVO_FHD_60FPS_1920 = 0,
 	MTK_DVO_FHD_60FPS_2180,
diff --git a/src/soc/mediatek/common/dp/include/soc/dptx_common.h b/src/soc/mediatek/common/dp/include/soc/dptx_common.h
index 8f4f8e0011..6dcd6adb73 100644
--- a/src/soc/mediatek/common/dp/include/soc/dptx_common.h
+++ b/src/soc/mediatek/common/dp/include/soc/dptx_common.h
@@ -215,6 +215,7 @@ struct mtk_dp {
 	bool enabled;
 	bool powered;
 	bool force_max_swing;
+	u8 edp_version;
 };
 
 int mtk_edp_init(struct mtk_dp *mtk_dp, struct edid *edid);
diff --git a/src/soc/mediatek/common/dp/include/soc/dptx_reg_v2.h b/src/soc/mediatek/common/dp/include/soc/dptx_reg_v2.h
index 762295d25e..da0654ab9d 100644
--- a/src/soc/mediatek/common/dp/include/soc/dptx_reg_v2.h
+++ b/src/soc/mediatek/common/dp/include/soc/dptx_reg_v2.h
@@ -98,7 +98,7 @@
 #define REG_35F0_DP_TRANS_P0				0x35F0
 #define REG_360C_AUX_TX_P0				0x360C
 #define REG_3614_AUX_TX_P0				0x3614
-#define AUX_RX_UI_CNT_THR_AUX_FOR_26M			13
+#define AUX_RX_UI_CNT_THR_AUX_FOR_26M			14
 #define REG_3618_AUX_TX_P0				0x3618
 #define AUX_RX_FIFO_FULL_AUX_TX_P0_FLDMASK		0x200
 #define REG_3620_AUX_TX_P0				0x3620

From 03be570994e262a778c4af0a76d5e293a350d54c Mon Sep 17 00:00:00 2001
From: Yidi Lin <yidilin@google.com>
Date: Wed, 18 Jun 2025 17:24:55 +0800
Subject: [PATCH 1405/3886] mb/google/rauru: Remove unused get_oled_description

get_oled_description is a wrong function declaration. Remove
get_oled_description function declaration and include soc/display.h
for get_active_panel.

Change-Id: Id321882d5b4b00f4114ef7282d13af9003019f62
Signed-off-by: Yidi Lin <yidilin@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88139
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/google/rauru/panel.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/mainboard/google/rauru/panel.h b/src/mainboard/google/rauru/panel.h
index 9b18f1d4fd..0fa2877789 100644
--- a/src/mainboard/google/rauru/panel.h
+++ b/src/mainboard/google/rauru/panel.h
@@ -3,6 +3,6 @@
 #ifndef __MAINBOARD_GOOGLE_RAURU_PANEL_H__
 #define __MAINBOARD_GOOGLE_RAURU_PANEL_H__
 
-struct panel_description *get_oled_description(void);
+#include <soc/display.h>
 
 #endif /* __MAINBOARD_GOOGLE_RAURU_PANEL_H__ */

From 35648dc37bddf4d85f8fec1443155443f5eba969 Mon Sep 17 00:00:00 2001
From: Maximilian Brune <maximilian.brune@9elements.com>
Date: Tue, 10 Jun 2025 17:10:15 +0200
Subject: [PATCH 1406/3886] acpi: Add _func suffix for callback functions

It causes some name clashes (and therefore overshadowing) of function
names defined in xeon SOC code in later patches of the patch train.

We don't really have a standard naming scheme for callback functions, so
I just added a _func suffix/postfix to indicate the function is a
callback function and to prevent name clashes.

Change-Id: I21811f75ef6e7642a7e4f69997737cd7b8b1cef9
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88033
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Anand Vaikar <a.vaikar2021@gmail.com>
---
 src/acpi/acpi.c         | 28 ++++++++++++++--------------
 src/include/acpi/acpi.h | 16 ++++++++--------
 2 files changed, 22 insertions(+), 22 deletions(-)

diff --git a/src/acpi/acpi.c b/src/acpi/acpi.c
index 6c463c93d4..84e314c8e9 100644
--- a/src/acpi/acpi.c
+++ b/src/acpi/acpi.c
@@ -386,7 +386,7 @@ int acpi_create_srat_gia_pci(acpi_srat_gia_t *gia, u32 proximity_domain,
 
 /* http://www.microsoft.com/whdc/system/sysinternals/sratdwn.mspx */
 void acpi_create_srat(acpi_srat_t *srat,
-		      unsigned long (*acpi_fill_srat)(unsigned long current))
+		      unsigned long (*acpi_fill_srat_func)(unsigned long current))
 {
 	acpi_header_t *header = &(srat->header);
 	unsigned long current = (unsigned long)srat + sizeof(acpi_srat_t);
@@ -398,7 +398,7 @@ void acpi_create_srat(acpi_srat_t *srat,
 
 	srat->resv = 1; /* Spec: Reserved to 1 for backwards compatibility. */
 
-	current = acpi_fill_srat(current);
+	current = acpi_fill_srat_func(current);
 
 	/* (Re)calculate length and checksum. */
 	header->length = current - (unsigned long)srat;
@@ -462,7 +462,7 @@ int acpi_create_cedt_cfmws(acpi_cedt_cfmws_t *cfmws, u64 base_hpa, u64 window_si
 	return cfmws->length;
 }
 
-void acpi_create_cedt(acpi_cedt_t *cedt, unsigned long (*acpi_fill_cedt)(unsigned long current))
+void acpi_create_cedt(acpi_cedt_t *cedt, unsigned long (*acpi_fill_cedt_func)(unsigned long current))
 {
 	acpi_header_t *header = &(cedt->header);
 	unsigned long current = (unsigned long)cedt + sizeof(acpi_cedt_t);
@@ -472,7 +472,7 @@ void acpi_create_cedt(acpi_cedt_t *cedt, unsigned long (*acpi_fill_cedt)(unsigne
 	if (acpi_fill_header(header, "CEDT", CEDT, sizeof(acpi_cedt_t)) != CB_SUCCESS)
 		return;
 
-	current = acpi_fill_cedt(current);
+	current = acpi_fill_cedt_func(current);
 
 	/* (Re)calculate length and checksum. */
 	header->length = current - (unsigned long)cedt;
@@ -497,7 +497,7 @@ int acpi_create_hmat_mpda(acpi_hmat_mpda_t *mpda, u32 initiator, u32 memory)
 }
 
 void acpi_create_hmat(acpi_hmat_t *hmat,
-		 unsigned long (*acpi_fill_hmat)(unsigned long current))
+		 unsigned long (*acpi_fill_hmat_func)(unsigned long current))
 {
 	acpi_header_t *header = &(hmat->header);
 	unsigned long current = (unsigned long)hmat + sizeof(acpi_hmat_t);
@@ -507,7 +507,7 @@ void acpi_create_hmat(acpi_hmat_t *hmat,
 	if (acpi_fill_header(header, "HMAT", HMAT, sizeof(acpi_hmat_t)) != CB_SUCCESS)
 		return;
 
-	current = acpi_fill_hmat(current);
+	current = acpi_fill_hmat_func(current);
 
 	/* (Re)calculate length and checksum. */
 	header->length = current - (unsigned long)hmat;
@@ -516,7 +516,7 @@ void acpi_create_hmat(acpi_hmat_t *hmat,
 
 /* http://h21007.www2.hp.com/portal/download/files/unprot/Itanium/slit.pdf */
 void acpi_create_slit(acpi_slit_t *slit,
-		      unsigned long (*acpi_fill_slit)(unsigned long current))
+		      unsigned long (*acpi_fill_slit_func)(unsigned long current))
 {
 	acpi_header_t *header = &(slit->header);
 	unsigned long current = (unsigned long)slit + sizeof(acpi_slit_t);
@@ -526,7 +526,7 @@ void acpi_create_slit(acpi_slit_t *slit,
 	if (acpi_fill_header(header, "SLIT", SLIT, sizeof(acpi_slit_t)) != CB_SUCCESS)
 		return;
 
-	current = acpi_fill_slit(current);
+	current = acpi_fill_slit_func(current);
 
 	/* (Re)calculate length and checksum. */
 	header->length = current - (unsigned long)slit;
@@ -675,7 +675,7 @@ void acpi_create_einj(acpi_einj_t *einj, uintptr_t addr, u8 actions)
 
 void acpi_create_vfct(const struct device *device,
 		      acpi_vfct_t *vfct,
-		      unsigned long (*acpi_fill_vfct)(const struct device *device,
+		      unsigned long (*acpi_fill_vfct_func)(const struct device *device,
 		      acpi_vfct_t *vfct_struct, unsigned long current))
 {
 	acpi_header_t *header = &(vfct->header);
@@ -686,7 +686,7 @@ void acpi_create_vfct(const struct device *device,
 	if (acpi_fill_header(header, "VFCT", VFCT, sizeof(acpi_vfct_t)) != CB_SUCCESS)
 		return;
 
-	current = acpi_fill_vfct(device, vfct, current);
+	current = acpi_fill_vfct_func(device, vfct, current);
 
 	/* If no BIOS image, return with header->length == 0. */
 	if (!vfct->VBIOSImageOffset)
@@ -743,7 +743,7 @@ void acpi_create_ipmi(const struct device *device,
 }
 
 void acpi_create_ivrs(acpi_ivrs_t *ivrs,
-		      unsigned long (*acpi_fill_ivrs)(acpi_ivrs_t *ivrs_struct,
+		      unsigned long (*acpi_fill_ivrs_func)(acpi_ivrs_t *ivrs_struct,
 		      unsigned long current))
 {
 	acpi_header_t *header = &(ivrs->header);
@@ -754,7 +754,7 @@ void acpi_create_ivrs(acpi_ivrs_t *ivrs,
 	if (acpi_fill_header(header, "IVRS", IVRS, sizeof(acpi_ivrs_t)) != CB_SUCCESS)
 		return;
 
-	current = acpi_fill_ivrs(ivrs, current);
+	current = acpi_fill_ivrs_func(ivrs, current);
 
 	/* (Re)calculate length and checksum. */
 	header->length = current - (unsigned long)ivrs;
@@ -762,7 +762,7 @@ void acpi_create_ivrs(acpi_ivrs_t *ivrs,
 }
 
 void acpi_create_crat(struct acpi_crat_header *crat,
-		      unsigned long (*acpi_fill_crat)(struct acpi_crat_header *crat_struct,
+		      unsigned long (*acpi_fill_crat_func)(struct acpi_crat_header *crat_struct,
 		      unsigned long current))
 {
 	acpi_header_t *header = &(crat->header);
@@ -773,7 +773,7 @@ void acpi_create_crat(struct acpi_crat_header *crat,
 	if (acpi_fill_header(header, "CRAT", CRAT, sizeof(struct acpi_crat_header)) != CB_SUCCESS)
 		return;
 
-	current = acpi_fill_crat(crat, current);
+	current = acpi_fill_crat_func(crat, current);
 
 	/* (Re)calculate length and checksum. */
 	header->length = current - (unsigned long)crat;
diff --git a/src/include/acpi/acpi.h b/src/include/acpi/acpi.h
index 3b0aa626e2..4d9599dac7 100644
--- a/src/include/acpi/acpi.h
+++ b/src/include/acpi/acpi.h
@@ -1762,7 +1762,7 @@ void acpi_add_table(acpi_rsdp_t *rsdp, void *table);
 
 /* Create CXL Early Discovery Table */
 void acpi_create_cedt(acpi_cedt_t *cedt,
-	unsigned long (*acpi_fill_cedt)(unsigned long current));
+	unsigned long (*acpi_fill_cedt_func)(unsigned long current));
 /* Create a CXL Host Bridge Structure for CEDT */
 int acpi_create_cedt_chbs(acpi_cedt_chbs_t *chbs, u32 uid, u32 cxl_ver, u64 base);
 /* Create a CXL Fixed Memory Window Structure for CEDT */
@@ -1796,10 +1796,10 @@ int acpi_create_srat_gia_pci(acpi_srat_gia_t *gia, u32 proximity_domain,
 			     struct device *dev, u32 flags);
 unsigned long acpi_create_srat_lapics(unsigned long current);
 void acpi_create_srat(acpi_srat_t *srat,
-		      unsigned long (*acpi_fill_srat)(unsigned long current));
+		      unsigned long (*acpi_fill_srat_func)(unsigned long current));
 
 void acpi_create_slit(acpi_slit_t *slit,
-		      unsigned long (*acpi_fill_slit)(unsigned long current));
+		      unsigned long (*acpi_fill_slit_func)(unsigned long current));
 
 /*
  * Create a Memory Proximity Domain Attributes structure for HMAT,
@@ -1809,11 +1809,11 @@ void acpi_create_slit(acpi_slit_t *slit,
 int acpi_create_hmat_mpda(acpi_hmat_mpda_t *mpda, u32 initiator, u32 memory);
 /* Create Heterogeneous Memory Attribute Table */
 void acpi_create_hmat(acpi_hmat_t *hmat,
-		      unsigned long (*acpi_fill_hmat)(unsigned long current));
+		      unsigned long (*acpi_fill_hmat_func)(unsigned long current));
 
 void acpi_create_vfct(const struct device *device,
 		      acpi_vfct_t *vfct,
-		      unsigned long (*acpi_fill_vfct)(const struct device *device,
+		      unsigned long (*acpi_fill_vfct_func)(const struct device *device,
 				acpi_vfct_t *vfct_struct,
 				unsigned long current));
 
@@ -1827,11 +1827,11 @@ void acpi_create_ipmi(const struct device *device,
 		      const u32 uid);
 
 void acpi_create_ivrs(acpi_ivrs_t *ivrs,
-		      unsigned long (*acpi_fill_ivrs)(acpi_ivrs_t *ivrs_struct,
+		      unsigned long (*acpi_fill_ivrs_func)(acpi_ivrs_t *ivrs_struct,
 		      unsigned long current));
 
 void acpi_create_crat(struct acpi_crat_header *crat,
-		      unsigned long (*acpi_fill_crat)(struct acpi_crat_header *crat_struct,
+		      unsigned long (*acpi_fill_crat_func)(struct acpi_crat_header *crat_struct,
 		      unsigned long current));
 
 unsigned long acpi_write_hpet(const struct device *device, unsigned long start,
@@ -1848,7 +1848,7 @@ unsigned long acpi_16550_mmio32_write_dbg2_uart(acpi_rsdp_t *rsdp, unsigned long
 					 uint64_t base, const char *name);
 
 void acpi_create_dmar(acpi_dmar_t *dmar, enum dmar_flags flags,
-		      unsigned long (*acpi_fill_dmar)(unsigned long));
+		      unsigned long (*acpi_fill_dmar_func)(unsigned long));
 unsigned long acpi_create_dmar_drhd_4k(unsigned long current, u8 flags,
 				    u16 segment, u64 bar);
 unsigned long acpi_create_dmar_drhd(unsigned long current, u8 flags,

From cc116e08aacc22623263466e3a2b92ca46765648 Mon Sep 17 00:00:00 2001
From: Shon Wang <shon.wang@quanta.corp-partner.google.com>
Date: Wed, 11 Jun 2025 16:48:19 +0800
Subject: [PATCH 1407/3886] mb/google/nissa/var/quandiso: Add touchscreen
 FTSC1000 support

New Touchscreen function for Quandiso project.
Touchscreen panel: HKO RB116AS01-4
Datasheet : Product%20Spec_RB116AS01-4_ver1.0.pdf

BUG=b:424332291
BRANCH=firmware-nissa-15217.B
TEST=1. emerge-nissa coreboot chromeos-bootimage
     2. Confirm command evtest and touchscreen function is workable.

Change-Id: I6b1f9929fc63c056d7714c9ed67bcaffeebdab8b
Signed-off-by: Shon Wang <shon.wang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88064
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
---
 .../brya/variants/quandiso/overridetree.cb     | 18 ++++++++++++++++++
 1 file changed, 18 insertions(+)

diff --git a/src/mainboard/google/brya/variants/quandiso/overridetree.cb b/src/mainboard/google/brya/variants/quandiso/overridetree.cb
index 72b9a77dd0..d4f98c9a55 100644
--- a/src/mainboard/google/brya/variants/quandiso/overridetree.cb
+++ b/src/mainboard/google/brya/variants/quandiso/overridetree.cb
@@ -276,6 +276,24 @@ chip soc/intel/alderlake
 				register "hid_desc_reg_offset" = "0x01"
 				device i2c 40 on end
 			end
+			chip drivers/i2c/hid
+				register "generic.hid" = ""FTSC1000""
+				register "generic.desc" = ""FOCAL Touchscreen""
+				register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_C7_IRQ)"
+				register "generic.detect" = "1"
+				register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C1)"
+				register "generic.reset_delay_ms" = "150"
+				register "generic.reset_off_delay_ms" = "5"
+				register "generic.stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C6)"
+				register "generic.stop_delay_ms" = "30"
+				register "generic.stop_off_delay_ms" = "10"
+				register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C0)"
+				register "generic.enable_delay_ms" = "45"
+				register "generic.has_power_resource" = "1"
+				register "generic.use_gpio_for_status" = "true"
+				register "hid_desc_reg_offset" = "0x01"
+				device i2c 38 on end
+			end
 			chip drivers/generic/gpio_keys
 				register "name" = ""PENH""
 				register "gpio" = "ACPI_GPIO_INPUT_ACTIVE_LOW(GPP_F13)"

From 64d488834964f864d136ea8ad6ef43e2c5778fa2 Mon Sep 17 00:00:00 2001
From: David Wu <david_wu@quanta.corp-partner.google.com>
Date: Mon, 23 Jun 2025 13:18:01 +0800
Subject: [PATCH 1408/3886] mb/google/dedede/var/magolor: Generate SPD ID for
 CXMT CXDB4CBAM-ML-A

Add support for the new memory CXMT CXDB4CBAM-ML-A.

BUG=b:427090130
TEST=Use part_id_gen to generate related settings

Change-Id: I176fb49c17379fcf454f5a4d3ab4b057b50d34ce
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88167
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/google/dedede/variants/magolor/memory/Makefile.mk  | 1 +
 .../google/dedede/variants/magolor/memory/dram_id.generated.txt  | 1 +
 .../google/dedede/variants/magolor/memory/mem_parts_used.txt     | 1 +
 3 files changed, 3 insertions(+)

diff --git a/src/mainboard/google/dedede/variants/magolor/memory/Makefile.mk b/src/mainboard/google/dedede/variants/magolor/memory/Makefile.mk
index eadd6ee9bd..199e34a632 100644
--- a/src/mainboard/google/dedede/variants/magolor/memory/Makefile.mk
+++ b/src/mainboard/google/dedede/variants/magolor/memory/Makefile.mk
@@ -7,3 +7,4 @@ SPD_SOURCES =
 SPD_SOURCES += spd/lp4x/set-1/spd-1.hex      # ID = 0(0b0000)  Parts = MT53E512M32D2NP-046 WT:E, K4U6E3S4AA-MGCR, H9HCNNNBKMMLXR-NEE, MT53E512M32D1NP-046 WT:B, K4U6E3S4AB-MGCL, H54G46CYRBX267
 SPD_SOURCES += spd/lp4x/set-1/spd-4.hex      # ID = 1(0b0001)  Parts = MT53E1G32D2NP-046 WT:A
 SPD_SOURCES += spd/lp4x/set-1/spd-3.hex      # ID = 2(0b0010)  Parts = K4UBE3D4AA-MGCR
+SPD_SOURCES += spd/lp4x/set-1/spd-11.hex      # ID = 3(0b0011)  Parts = CXDB4CBAM-ML-A
diff --git a/src/mainboard/google/dedede/variants/magolor/memory/dram_id.generated.txt b/src/mainboard/google/dedede/variants/magolor/memory/dram_id.generated.txt
index bda04d320e..52baea7e74 100644
--- a/src/mainboard/google/dedede/variants/magolor/memory/dram_id.generated.txt
+++ b/src/mainboard/google/dedede/variants/magolor/memory/dram_id.generated.txt
@@ -12,3 +12,4 @@ K4UBE3D4AA-MGCR                2 (0010)
 MT53E512M32D1NP-046 WT:B       0 (0000)
 K4U6E3S4AB-MGCL                0 (0000)
 H54G46CYRBX267                 0 (0000)
+CXDB4CBAM-ML-A                 3 (0011)
diff --git a/src/mainboard/google/dedede/variants/magolor/memory/mem_parts_used.txt b/src/mainboard/google/dedede/variants/magolor/memory/mem_parts_used.txt
index 2cde0751c4..e159796f46 100644
--- a/src/mainboard/google/dedede/variants/magolor/memory/mem_parts_used.txt
+++ b/src/mainboard/google/dedede/variants/magolor/memory/mem_parts_used.txt
@@ -6,3 +6,4 @@ K4UBE3D4AA-MGCR
 MT53E512M32D1NP-046 WT:B
 K4U6E3S4AB-MGCL
 H54G46CYRBX267
+CXDB4CBAM-ML-A

From bc8876d56da5fb79555f9b660c7557c3e5d1b515 Mon Sep 17 00:00:00 2001
From: Jincheng Li <jincheng.li@intel.com>
Date: Mon, 23 Jun 2025 11:29:47 +0800
Subject: [PATCH 1409/3886] Revert "soc/intel/xeon_sp/uncore.c: mark TSEG/SMM
 region as reserved"
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

This reverts commit 2e495b09d52f83622c83258059de8f5c92b3ef6b.

Reason for revert: mmio_tseg is reserved twice in
mc_add_dram_resources, where the duplication is introduced by
commit 43b0ed708963 ("soc/intel/xeon_sp: Improve final MTRR solution")

Change-Id: I0f1bf757d8d1fc449e4efc0ec171c6f982f79e9e
Signed-off-by: Jincheng Li <jincheng.li@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88165
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
---
 src/soc/intel/xeon_sp/uncore.c | 5 -----
 1 file changed, 5 deletions(-)

diff --git a/src/soc/intel/xeon_sp/uncore.c b/src/soc/intel/xeon_sp/uncore.c
index 85e45db63d..681542e901 100644
--- a/src/soc/intel/xeon_sp/uncore.c
+++ b/src/soc/intel/xeon_sp/uncore.c
@@ -277,11 +277,6 @@ static void mc_add_dram_resources(struct device *dev, int *res_count)
 	res = ram_from_to(dev, index++, top_of_ram, cbmem_top());
 	LOG_RESOURCE("cbmem_ram", dev, res);
 
-	/* Mark TSEG/SMM region as reserved */
-	res = reserved_ram_from_to(dev, index++, mc_values[TSEG_BASE_REG],
-				   mc_values[TSEG_LIMIT_REG] + 1);
-	LOG_RESOURCE("mmio_tseg", dev, res);
-
 	/* Reserve DPR region */
 	union dpr_register dpr = { .raw = pci_read_config32(dev, VTD_LTDPR) };
 	if (dpr.size) {

From 110aebb4d20d2ce695e9149b45e06379010473b8 Mon Sep 17 00:00:00 2001
From: David Wu <david_wu@quanta.corp-partner.google.com>
Date: Mon, 23 Jun 2025 17:25:17 +0800
Subject: [PATCH 1410/3886] mb/google/nissa/var/riven: Add focaltech
 touchscreen support

This change adds the necessary configuration for the focaltech
touchscreen (FTSC1000) device, connected to I2C bus 38.

It includes settings for:
* HID descriptor
* Device description
* IRQ configuration
* Detection
* Reset and enable GPIOs with their respective delays
* Power resource handling
* HID descriptor register offset

Datasheet: FT8112_Data_Sheet_V0.2_HKC20240415.pdf

BUG=b:426038745
TEST=emerge-nissa coreboot and focaltech touchscreen can work well.

Change-Id: I478924fbebf2a5ecd60bad48b37bfa6581100601
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88174
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
---
 .../google/brya/variants/riven/overridetree.cb     | 14 ++++++++++++++
 1 file changed, 14 insertions(+)

diff --git a/src/mainboard/google/brya/variants/riven/overridetree.cb b/src/mainboard/google/brya/variants/riven/overridetree.cb
index 842074c9eb..ee3afa616b 100644
--- a/src/mainboard/google/brya/variants/riven/overridetree.cb
+++ b/src/mainboard/google/brya/variants/riven/overridetree.cb
@@ -289,6 +289,20 @@ chip soc/intel/alderlake
 				register "hid_desc_reg_offset" = "0x01"
 				device i2c 40 on end
 			end
+			chip drivers/i2c/hid
+				register "generic.hid" = ""FTSC1000""
+				register "generic.desc" = ""Focal Touchscreen""
+				register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_C7_IRQ)"
+				register "generic.detect" = "1"
+				register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C1)"
+				register "generic.reset_delay_ms" = "20"
+				register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C0)"
+				register "generic.enable_delay_ms" = "6"
+				register "generic.has_power_resource" = "1"
+				register "generic.use_gpio_for_status" = "true"
+				register "hid_desc_reg_offset" = "0x01"
+				device i2c 38 on end
+			end
 			chip drivers/generic/gpio_keys
 				register "name" = ""PENH""
 				register "gpio" = "ACPI_GPIO_INPUT_ACTIVE_LOW(GPP_F13)"

From 8e5bdde028c39c40aa1cd41f1b82d6621a8d1286 Mon Sep 17 00:00:00 2001
From: Bora Guvendik <bora.guvendik@intel.corp-partner.google.com>
Date: Mon, 23 Jun 2025 14:04:32 -0700
Subject: [PATCH 1411/3886] mb/intel/ptlrvp: Add support for H58G66BK7BX067
 memory
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

This commit introduces support for the H58G66BK7BX067 memory module
within the Intel PTLRVP mainboard variant. The changes include updates
to several configuration files to recognize and utilize this specific
memory module. The SPD source files and DRAM ID assignments have been
updated accordingly to integrate the new memory module into the build
system. This addition ensures compatibility and functionality with
the H58G66BK7BX067 memory module, allowing for expanded hardware
support and flexibility in memory configurations.

BUG=none
TEST=Build and verify memory module detection and initialization
on supported hardware configuration.

Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Change-Id: Ic281125dd40bbcef50d138e912e7557d6552eb9f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88177
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/intel/ptlrvp/variants/ptlrvp/memory/Makefile.mk    | 1 +
 .../intel/ptlrvp/variants/ptlrvp/memory/dram_id.generated.txt    | 1 +
 .../intel/ptlrvp/variants/ptlrvp/memory/mem_parts_used.txt       | 1 +
 3 files changed, 3 insertions(+)

diff --git a/src/mainboard/intel/ptlrvp/variants/ptlrvp/memory/Makefile.mk b/src/mainboard/intel/ptlrvp/variants/ptlrvp/memory/Makefile.mk
index 5575815d1b..bc9fd85a3d 100644
--- a/src/mainboard/intel/ptlrvp/variants/ptlrvp/memory/Makefile.mk
+++ b/src/mainboard/intel/ptlrvp/variants/ptlrvp/memory/Makefile.mk
@@ -7,3 +7,4 @@ SPD_SOURCES =
 SPD_SOURCES += spd/lp5/set-0/spd-7.hex      # ID = 0(0b0000)  Parts = H58G56BK7BX068
 SPD_SOURCES += spd/lp5/set-0/spd-10.hex      # ID = 1(0b0001)  Parts = H58G66BK8BX067
 SPD_SOURCES += spd/lp5/set-0/spd-11.hex      # ID = 2(0b0010)  Parts = H58G56BK8BX068
+SPD_SOURCES += spd/lp5/set-0/spd-8.hex      # ID = 3(0b0011)  Parts = H58G66BK7BX067
diff --git a/src/mainboard/intel/ptlrvp/variants/ptlrvp/memory/dram_id.generated.txt b/src/mainboard/intel/ptlrvp/variants/ptlrvp/memory/dram_id.generated.txt
index 244c063804..c0426069d9 100644
--- a/src/mainboard/intel/ptlrvp/variants/ptlrvp/memory/dram_id.generated.txt
+++ b/src/mainboard/intel/ptlrvp/variants/ptlrvp/memory/dram_id.generated.txt
@@ -7,3 +7,4 @@ DRAM Part Name                 ID to assign
 H58G56BK7BX068                 0 (0000)
 H58G66BK8BX067                 1 (0001)
 H58G56BK8BX068                 2 (0010)
+H58G66BK7BX067                 3 (0011)
diff --git a/src/mainboard/intel/ptlrvp/variants/ptlrvp/memory/mem_parts_used.txt b/src/mainboard/intel/ptlrvp/variants/ptlrvp/memory/mem_parts_used.txt
index 98255ad4d3..61b2b2eff7 100644
--- a/src/mainboard/intel/ptlrvp/variants/ptlrvp/memory/mem_parts_used.txt
+++ b/src/mainboard/intel/ptlrvp/variants/ptlrvp/memory/mem_parts_used.txt
@@ -12,3 +12,4 @@
 H58G56BK7BX068
 H58G66BK8BX067
 H58G56BK8BX068
+H58G66BK7BX067

From cdf0c76dc88f7abc5ba4fe8397cf8c57a05939ed Mon Sep 17 00:00:00 2001
From: Pranava Y N <pranavayn@google.com>
Date: Mon, 23 Jun 2025 12:39:34 +0530
Subject: [PATCH 1412/3886] mb/google/fatcat: Create new fatcat4es variant

This new variant created will support PTL pre-production silicon. The
existing `fatcat` variant will support production silicon.

BUG=b:424355826
TEST=Able to build google/fatcat4es.

Change-Id: I0f925a73a42aaf6d3ae6980169d912374b12d8ae
Signed-off-by: Pranava Y N <pranavayn@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88171
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
---
 src/mainboard/google/fatcat/Kconfig                         | 6 ++++++
 src/mainboard/google/fatcat/Kconfig.name                    | 3 +++
 .../variants/baseboard/fatcat/include/baseboard/gpio.h      | 3 ++-
 3 files changed, 11 insertions(+), 1 deletion(-)

diff --git a/src/mainboard/google/fatcat/Kconfig b/src/mainboard/google/fatcat/Kconfig
index 7b9dcf5335..66ca58e761 100644
--- a/src/mainboard/google/fatcat/Kconfig
+++ b/src/mainboard/google/fatcat/Kconfig
@@ -77,6 +77,11 @@ config BOARD_GOOGLE_FATCAT
 	select EC_GOOGLE_CHROMEEC_MEC
 	select MAINBOARD_USES_IFD_EC_REGION
 
+config BOARD_GOOGLE_FATCAT4ES
+	select BOARD_GOOGLE_MODEL_FATCAT
+	select EC_GOOGLE_CHROMEEC_MEC
+	select MAINBOARD_USES_IFD_EC_REGION
+
 config BOARD_GOOGLE_FATCATISH
 	select BOARD_GOOGLE_MODEL_FATCAT
 	select EC_GOOGLE_CHROMEEC_MEC
@@ -152,6 +157,7 @@ config MAINBOARD_FAMILY
 
 config MAINBOARD_PART_NUMBER
 	default "Fatcat" if BOARD_GOOGLE_FATCAT
+	default "Fatcat4ES" if BOARD_GOOGLE_FATCAT4ES
 	default "Fatcat_ish" if BOARD_GOOGLE_FATCATISH
 	default "Fatcatite" if BOARD_GOOGLE_FATCATITE
 	default "Fatcatnuvo" if BOARD_GOOGLE_FATCATNUVO
diff --git a/src/mainboard/google/fatcat/Kconfig.name b/src/mainboard/google/fatcat/Kconfig.name
index e9bf37e570..26d9ec7dd2 100644
--- a/src/mainboard/google/fatcat/Kconfig.name
+++ b/src/mainboard/google/fatcat/Kconfig.name
@@ -5,6 +5,9 @@ comment "Fatcat"
 config BOARD_GOOGLE_FATCAT
 	bool "-> Fatcat"
 
+config BOARD_GOOGLE_FATCAT4ES
+	bool "-> Fatcat4ES"
+
 config BOARD_GOOGLE_FATCATISH
 	bool "-> Fatcat_ish"
 
diff --git a/src/mainboard/google/fatcat/variants/baseboard/fatcat/include/baseboard/gpio.h b/src/mainboard/google/fatcat/variants/baseboard/fatcat/include/baseboard/gpio.h
index 56f57f9950..3d5cece486 100644
--- a/src/mainboard/google/fatcat/variants/baseboard/fatcat/include/baseboard/gpio.h
+++ b/src/mainboard/google/fatcat/variants/baseboard/fatcat/include/baseboard/gpio.h
@@ -16,7 +16,8 @@
  #define EC_SYNC_IRQ	GPP_E07_IRQ
  #define GPIO_PCH_WP	GPP_D02
 #define GPIO_SLP_S0_GATE	0 /* Not Connected */
-#elif CONFIG(BOARD_GOOGLE_FATCAT) || CONFIG(BOARD_GOOGLE_FATCATISH)
+#elif (CONFIG(BOARD_GOOGLE_FATCAT) || CONFIG(BOARD_GOOGLE_FATCAT4ES) \
+	|| CONFIG(BOARD_GOOGLE_FATCATISH))
  #define EC_SYNC_IRQ	0 /* Not Connected */
  #define GPIO_PCH_WP	GPP_D02
 #define GPIO_SLP_S0_GATE	0 /* Not Connected */

From e7984f39eb55686530bf772267c0e260ab5889fb Mon Sep 17 00:00:00 2001
From: Pranava Y N <pranavayn@google.com>
Date: Tue, 17 Jun 2025 20:22:22 +0530
Subject: [PATCH 1413/3886] mb/google/fatcat: Create new fatcatnuvo4es variant

This new variant will support PTL pre-production silicon. The existing
`fatcatnuvo` variant will support production silicon.

BUG=b:424355826
TEST=Able to build google/fatcatnuvo4es.

Change-Id: I079f9bbf0be9c3149b3f583102bec32f328ab44d
Signed-off-by: Pranava Y N <pranavayn@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88129
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/google/fatcat/Kconfig                           | 4 ++++
 src/mainboard/google/fatcat/Kconfig.name                      | 3 +++
 .../fatcat/variants/baseboard/fatcat/include/baseboard/gpio.h | 3 ++-
 3 files changed, 9 insertions(+), 1 deletion(-)

diff --git a/src/mainboard/google/fatcat/Kconfig b/src/mainboard/google/fatcat/Kconfig
index 66ca58e761..82d6298438 100644
--- a/src/mainboard/google/fatcat/Kconfig
+++ b/src/mainboard/google/fatcat/Kconfig
@@ -90,6 +90,9 @@ config BOARD_GOOGLE_FATCATISH
 config BOARD_GOOGLE_FATCATNUVO
 	select BOARD_GOOGLE_MODEL_FATCAT
 
+config BOARD_GOOGLE_FATCATNUVO4ES
+	select BOARD_GOOGLE_MODEL_FATCAT
+
 config BOARD_GOOGLE_FATCATITE
 	select BOARD_GOOGLE_MODEL_FATCAT
 
@@ -161,6 +164,7 @@ config MAINBOARD_PART_NUMBER
 	default "Fatcat_ish" if BOARD_GOOGLE_FATCATISH
 	default "Fatcatite" if BOARD_GOOGLE_FATCATITE
 	default "Fatcatnuvo" if BOARD_GOOGLE_FATCATNUVO
+	default "Fatcatnuvo4ES" if BOARD_GOOGLE_FATCATNUVO4ES
 	default "Francka" if BOARD_GOOGLE_FRANCKA
 	default "Felino" if BOARD_GOOGLE_FELINO
 	default "Felino4ES" if BOARD_GOOGLE_FELINO4ES
diff --git a/src/mainboard/google/fatcat/Kconfig.name b/src/mainboard/google/fatcat/Kconfig.name
index 26d9ec7dd2..ad765cebfa 100644
--- a/src/mainboard/google/fatcat/Kconfig.name
+++ b/src/mainboard/google/fatcat/Kconfig.name
@@ -17,6 +17,9 @@ config BOARD_GOOGLE_FATCATITE
 config BOARD_GOOGLE_FATCATNUVO
 	bool "-> Fatcatnuvo"
 
+config BOARD_GOOGLE_FATCATNUVO4ES
+	bool "-> Fatcatnuvo4ES"
+
 config BOARD_GOOGLE_FELINO
 	bool "-> Felino"
 
diff --git a/src/mainboard/google/fatcat/variants/baseboard/fatcat/include/baseboard/gpio.h b/src/mainboard/google/fatcat/variants/baseboard/fatcat/include/baseboard/gpio.h
index 3d5cece486..709e94f1ee 100644
--- a/src/mainboard/google/fatcat/variants/baseboard/fatcat/include/baseboard/gpio.h
+++ b/src/mainboard/google/fatcat/variants/baseboard/fatcat/include/baseboard/gpio.h
@@ -12,7 +12,8 @@
  * EC_SYNC_IRQ - GPIO IRQ for tight timestamps / wake support
  * GPIO_PCH_WP - WP signal to PCH
  */
-#if CONFIG(BOARD_GOOGLE_FATCATNUVO) || CONFIG(BOARD_GOOGLE_FATCATITE)
+#if (CONFIG(BOARD_GOOGLE_FATCATNUVO) || CONFIG(BOARD_GOOGLE_FATCATNUVO4ES) \
+	|| CONFIG(BOARD_GOOGLE_FATCATITE))
  #define EC_SYNC_IRQ	GPP_E07_IRQ
  #define GPIO_PCH_WP	GPP_D02
 #define GPIO_SLP_S0_GATE	0 /* Not Connected */

From b726a9c7e9ddd5875012c7034131ce4cc8255420 Mon Sep 17 00:00:00 2001
From: Pranava Y N <pranavayn@google.com>
Date: Tue, 17 Jun 2025 19:48:13 +0530
Subject: [PATCH 1414/3886] mb/google/fatcat: Create new fatcatite4es variant

This new variant will support PTL pre-production silicon. The existing
`fatcatite` variant will support production silicon.

BUG=b:424355826
TEST=Able to build google/fatcatite4es.

Change-Id: I9c51c1720a354f80edcf8c8ef75bd564dd6a5b5d
Signed-off-by: Pranava Y N <pranavayn@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88128
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/google/fatcat/Kconfig                           | 4 ++++
 src/mainboard/google/fatcat/Kconfig.name                      | 3 +++
 .../fatcat/variants/baseboard/fatcat/include/baseboard/gpio.h | 2 +-
 3 files changed, 8 insertions(+), 1 deletion(-)

diff --git a/src/mainboard/google/fatcat/Kconfig b/src/mainboard/google/fatcat/Kconfig
index 82d6298438..af277c8ac9 100644
--- a/src/mainboard/google/fatcat/Kconfig
+++ b/src/mainboard/google/fatcat/Kconfig
@@ -96,6 +96,9 @@ config BOARD_GOOGLE_FATCATNUVO4ES
 config BOARD_GOOGLE_FATCATITE
 	select BOARD_GOOGLE_MODEL_FATCAT
 
+config BOARD_GOOGLE_FATCATITE4ES
+	select BOARD_GOOGLE_MODEL_FATCAT
+
 config BOARD_GOOGLE_FELINO
 	select BOARD_GOOGLE_MODEL_FELINO
 
@@ -163,6 +166,7 @@ config MAINBOARD_PART_NUMBER
 	default "Fatcat4ES" if BOARD_GOOGLE_FATCAT4ES
 	default "Fatcat_ish" if BOARD_GOOGLE_FATCATISH
 	default "Fatcatite" if BOARD_GOOGLE_FATCATITE
+	default "Fatcatite4ES" if BOARD_GOOGLE_FATCATITE4ES
 	default "Fatcatnuvo" if BOARD_GOOGLE_FATCATNUVO
 	default "Fatcatnuvo4ES" if BOARD_GOOGLE_FATCATNUVO4ES
 	default "Francka" if BOARD_GOOGLE_FRANCKA
diff --git a/src/mainboard/google/fatcat/Kconfig.name b/src/mainboard/google/fatcat/Kconfig.name
index ad765cebfa..14ad4c1f6a 100644
--- a/src/mainboard/google/fatcat/Kconfig.name
+++ b/src/mainboard/google/fatcat/Kconfig.name
@@ -14,6 +14,9 @@ config BOARD_GOOGLE_FATCATISH
 config BOARD_GOOGLE_FATCATITE
 	bool "-> Fatcatite"
 
+config BOARD_GOOGLE_FATCATITE4ES
+	bool "-> Fatcatite4ES"
+
 config BOARD_GOOGLE_FATCATNUVO
 	bool "-> Fatcatnuvo"
 
diff --git a/src/mainboard/google/fatcat/variants/baseboard/fatcat/include/baseboard/gpio.h b/src/mainboard/google/fatcat/variants/baseboard/fatcat/include/baseboard/gpio.h
index 709e94f1ee..8c7121c1d8 100644
--- a/src/mainboard/google/fatcat/variants/baseboard/fatcat/include/baseboard/gpio.h
+++ b/src/mainboard/google/fatcat/variants/baseboard/fatcat/include/baseboard/gpio.h
@@ -13,7 +13,7 @@
  * GPIO_PCH_WP - WP signal to PCH
  */
 #if (CONFIG(BOARD_GOOGLE_FATCATNUVO) || CONFIG(BOARD_GOOGLE_FATCATNUVO4ES) \
-	|| CONFIG(BOARD_GOOGLE_FATCATITE))
+	|| CONFIG(BOARD_GOOGLE_FATCATITE) || CONFIG(BOARD_GOOGLE_FATCATITE4ES))
  #define EC_SYNC_IRQ	GPP_E07_IRQ
  #define GPIO_PCH_WP	GPP_D02
 #define GPIO_SLP_S0_GATE	0 /* Not Connected */

From 64a79d23e8e0c2126bf035e5e7804dcd72e1a629 Mon Sep 17 00:00:00 2001
From: Luca Lai <luca.lai@lcfc.corp-partner.google.com>
Date: Wed, 25 Jun 2025 09:47:47 +0800
Subject: [PATCH 1415/3886] mb/trulo/var/pujjoquince: Add SD card function

1. This change is based on the fact that the code for the pujjolo
and pujjoquince projects is shared.
2. Add SD card function and use proto board to verify the
functionality.

Schematic version: 500E_S3A0_TWL_MB_FVT_20250527

BUG=b:395763555
BRANCH=none
TEST=Boot to OS and verify the mmcblk0 shown which use lsblk
command, and check if sd card could store file in desktop.

Change-Id: Ib7f854d9c902ba3f257d154ae6b95ea443fa78f5
Signed-off-by: Luca Lai <luca.lai@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88184
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/google/brya/variants/pujjolo/gpio.c      | 10 ++++++----
 .../google/brya/variants/pujjolo/overridetree.cb       |  2 +-
 2 files changed, 7 insertions(+), 5 deletions(-)

diff --git a/src/mainboard/google/brya/variants/pujjolo/gpio.c b/src/mainboard/google/brya/variants/pujjolo/gpio.c
index 96a0ef48f5..a3856d4a1a 100644
--- a/src/mainboard/google/brya/variants/pujjolo/gpio.c
+++ b/src/mainboard/google/brya/variants/pujjolo/gpio.c
@@ -274,10 +274,6 @@ static const struct pad_config override_gpio_table[] = {
 	PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2),
 	/* H11 : UART0_TXD ==> UART_SOC_TX_DBG_RX */
 	PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2),
-	/* H12 : GPP_H12 ==> NC */
-	PAD_NC_LOCK(GPP_H12, NONE, LOCK_CONFIG),
-	/* H13 : GPP_H13 ==> NC */
-	PAD_NC_LOCK(GPP_H13, NONE, LOCK_CONFIG),
 	/* H14 : Not available */
 	PAD_NC(GPP_H14, NONE),
 	/* H15 : DDPB_CTRLCLK ==> HDMI_DDC_SCL */
@@ -455,6 +451,10 @@ static const struct pad_config early_gpio_table[] = {
 	PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2),
 	/* H11 : UART0_TXD ==> UART_SOC_TX_DBG_RX */
 	PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2),
+	/* H12 : UART0_RTS# ==> SD_PERST_L */
+	PAD_CFG_GPO(GPP_H12, 0, DEEP),
+	/* H13 : UART0_CTS# ==> EN_PP3300_SD_X */
+	PAD_CFG_GPO(GPP_H13, 1, DEEP),
 };
 
 /* Pad configuration in romstage for Sundance */
@@ -477,6 +477,8 @@ static const struct pad_config romstage_gpio_table[] = {
 	 PAD_CFG_GPO(GPP_E7, 0, DEEP),
 	 /* D2  : ISH_GP2 ==> EN_FP_PWR */
 	 PAD_CFG_GPO(GPP_D2, 0, DEEP),
+	/* H12 : UART0_RTS# ==> SD_PERST_L */
+	PAD_CFG_GPO(GPP_H12, 1, DEEP),
 };
 
 const struct pad_config *variant_gpio_override_table(size_t *num)
diff --git a/src/mainboard/google/brya/variants/pujjolo/overridetree.cb b/src/mainboard/google/brya/variants/pujjolo/overridetree.cb
index 71ac951e6d..1ffcf7aadc 100644
--- a/src/mainboard/google/brya/variants/pujjolo/overridetree.cb
+++ b/src/mainboard/google/brya/variants/pujjolo/overridetree.cb
@@ -8,7 +8,7 @@ fw_config
 		option WIFI_SAR_TABLE_AX211	0
 		option WIFI_SAR_TABLE_AX203	1
 	end
-	field SD_CARD 22
+	field SD_CARD 25
 		option SD_ABSENT	0
 		option SD_PRESENT	1
 	end

From 3a0b6f625aee29e6c6025084afcd7ced1e4188a2 Mon Sep 17 00:00:00 2001
From: Kun Liu <liukun11@huaqin.corp-partner.google.com>
Date: Mon, 23 Jun 2025 16:14:17 +0800
Subject: [PATCH 1416/3886] mb/google/trulo/var/pujjocento: Enable WiFi SAR
 table

Enable WiFi SAR table for pujjocento.

BUG=b:409254508
BRANCH=none
TEST=emerge-nissa coreboot chromeos-bootimage,wifi.SetTXPower test pass.

Change-Id: Icafe49b7ff1e2ad867412bdec41362f8cbb87e48
Signed-off-by: Kun Liu <liukun11@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88172
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
---
 src/mainboard/google/brya/Kconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/src/mainboard/google/brya/Kconfig b/src/mainboard/google/brya/Kconfig
index c1f65ef00d..399f1de409 100644
--- a/src/mainboard/google/brya/Kconfig
+++ b/src/mainboard/google/brya/Kconfig
@@ -528,6 +528,7 @@ config BOARD_GOOGLE_PUJJONIRU
 
 config BOARD_GOOGLE_PUJJOCENTO
 	select BOARD_GOOGLE_BASEBOARD_TRULO
+	select CHROMEOS_WIFI_SAR if CHROMEOS
 	select DRIVERS_I2C_SX9324
 	select DRIVERS_I2C_SX9324_SUPPORT_LEGACY_LINUX_DRIVER
 	select ENFORCE_MEM_CHANNEL_DISABLE

From 6a02f2d4a79be16bb5e74401df0c710e94dac54d Mon Sep 17 00:00:00 2001
From: Sasirekaa Madhesu <smadhesu@qualcomm.corp-partner.google.com>
Date: Thu, 19 Jun 2025 15:10:11 +0530
Subject: [PATCH 1417/3886] util/qualcomm: Add script to concatenate ELF images

The PBL of QCOM X1P42100 SoC loads image in multi ELF format, which is
a concatenation of TME SEQ, TME FW, QC-SEC and Bootblock binaries.
This script stitches the binaries together into multi ELF image.

Usage: create_multielf.py [-h] -f IN_FILES [-o [OUT_FILE]]
Example: python create_multielf.py -f image1,image2,image3 -o output.bin

Change-Id: I9cdbdf6b5c62663491ccd7d42ab270742760aa0b
Signed-off-by: Sasirekaa Madhesu <smadhesu@qualcomm.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88145
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
---
 util/qualcomm/create_multielf.py | 133 +++++++++++++++++++++++++++++++
 1 file changed, 133 insertions(+)
 create mode 100644 util/qualcomm/create_multielf.py

diff --git a/util/qualcomm/create_multielf.py b/util/qualcomm/create_multielf.py
new file mode 100644
index 0000000000..2660cf68e0
--- /dev/null
+++ b/util/qualcomm/create_multielf.py
@@ -0,0 +1,133 @@
+#!/usr/bin/env python3
+# ============================================================================
+#
+# @file create_multielf.py
+#
+# GENERAL DESCRIPTION
+#   This tool takes in files and concatenates all the files in a single blob output.
+#   Files are appended sequentially in order as provided in the arguments.
+#
+#  SPDX-License-Identifier: BSD-3-Clause
+#
+# ----------------------------------------------------------------------------
+#
+#                          EDIT HISTORY FOR MODULE
+#
+# This section contains comments describing changes made to the module.
+# Notice that changes are listed in reverse chronological order.
+#
+# when       who     what, where, why
+# --------   ---     -----------------------------------------------------------
+# 05/09/20   ds     Initial revision
+
+
+import sys
+import argparse
+import os
+import os.path
+from datetime import datetime as dt
+
+# default output filename is "multibin_<current time>.melf"
+outfile_name = "multibin_" + ((dt.now()).strftime("%H_%M_%S")) + ".melf"
+# default output path is current working directory
+outfile_path = os.getcwd()
+
+
+def check_outfile_path(dir_path):
+    try:
+        return os.makedirs(dir_path, exist_ok=True)
+    except Exception as e:
+        if type(e) == TypeError:
+        # exception if we use python2
+            pass
+        else:
+            print(e)
+            sys.exit("invalid path provided for output file \n absolute path required")
+
+    if not os.path.isdir(dir_path):
+        try:
+        #python2 compatible
+            return os.makedirs(dir_path)
+        except Exception as e:
+            print(e)
+            sys.exit("invalid path provided for output file \n absolute path required")
+
+
+def process_out_file_arg(outfile_arg):
+    global outfile_name
+    global outfile_path
+
+    if outfile_arg == os.path.join(outfile_path, outfile_name):
+        return
+
+    out_path, file_name = os.path.split(outfile_arg)
+
+    if out_path and file_name and os.path.splitext(file_name)[1]:
+        outfile_name = file_name
+        check_outfile_path(out_path)
+        outfile_path = os.path.abspath(out_path)
+    elif str(outfile_arg).endswith(os.path.sep):
+        check_outfile_path(outfile_arg)
+        outfile_path = os.path.abspath(out_path)
+    elif os.path.split(outfile_arg)[1] and os.path.splitext(os.path.split(outfile_arg)[1])[1]:
+        outfile_name = file_name
+    else:
+        sys.exit("invalid output path or output file. use --help for help menu")
+
+
+def get_abs_path_input_files(in_files):
+    abs_path_list = []
+    for infile in in_files:
+        if not os.path.isfile(infile):
+            sys.exit("-f OR --in_files argument error. {} is missing. use --help for help menu".format(infile))
+        abs_path_list.append(os.path.abspath(infile))
+    return abs_path_list
+
+
+def make_concatenated_binary(input_file_list):
+    infiles_abs_path_list = get_abs_path_input_files(input_file_list)
+    out_file = os.path.join(outfile_path, outfile_name)
+    if os.path.exists(out_file):
+        os.remove(out_file)
+    output_bin = open(out_file, mode='ab')
+    for file in infiles_abs_path_list:
+        in_file = open(file, mode='rb')
+        output_bin.write(in_file.read())
+        in_file.close()
+    output_bin.close()
+
+
+# main function for the tool
+def main():
+    parser = argparse.ArgumentParser(formatter_class=argparse.RawTextHelpFormatter)
+
+    # input file argument
+    parser.add_argument('-f', '--in_files', help=r'comma separated absolute paths of files to be concatenated'
+                                                 r'\neg: "-f C:\Temp\myelf1.elf,C:\Temp\myelf2.elf"',
+                        type=lambda s: [str(item).strip() for item in s.split(',')],
+                        required=True)
+
+    # optional output file argument
+    parser.add_argument('-o', '--out_file', help=r'* give file name OR absolute path OR file name with absolute path *'
+                                                 r'\neg: "-o C:\Temp\\" OR "-o C:\Temp\myelf.melf" OR "-o myelf.melf"'
+                                                 r'\n(if only giving output path - terminate by path separator)',
+                        type=str,
+                        nargs='?',
+                        default=os.path.join(outfile_path, outfile_name))
+    args = parser.parse_args()
+
+    # check if minimum two input files are given to concatenate
+    if len(args.in_files) < 2:
+        sys.exit("minimum 2 input files are required for concatenating")
+
+    # process the output path and file argument
+    process_out_file_arg(args.out_file)
+
+    # create the concatenated binary from the list of input files
+    make_concatenated_binary(args.in_files)
+
+    print("\n\n *** Created concatenated binary: " + outfile_name + " at " + outfile_path + os.path.sep + " ***")
+
+
+if __name__ == "__main__":
+    main()

From 0dcea61e7c98d8380adce60dbc5402c8fb9c2a03 Mon Sep 17 00:00:00 2001
From: Varadarajan Narayanan <vnarayan@qualcomm.corp-partner.google.com>
Date: Thu, 19 Jun 2025 15:05:27 +0530
Subject: [PATCH 1418/3886] cbfstool: Add multi ELF support

The current QCOM fixup function qualcomm_find_hash() assumes only one
ELF will be loaded by the primary boot loader and the bootblock is one
of the segments of that ELF.

However, the primary boot loader for QCOM X1P42100 SoC loads multiple
ELFs for QC_SEC, TME Sequencer, TME FW and bootblock. This change
updates the fixup functionality to handle bootblock being a separate
ELF.

If the bootblock offset does not fit within the first ELF, then the
fixup function understands that it is a multi ELF.

Additionally, it ensures the bootblock ELF uses MBN v7 format.

BUG=b:420542130

TEST=1. Create a image.serial.bin and ensure it boots on X1P42100
2. Used the following script to verify the hash
#! /bin/bash

image=/build/bluey/firmware/image-bluey.serial.bin
bin=/tmp/bb.bin
seg=/tmp/bb.seg
hash=/tmp/bb.hash

#
# Bootblock is the final ELF of the multi ELF. Hopefully
# there is no other ELF in ${image}. Get the offset of the
# final ELF in ${image} and get it out
#

bb_offset=`od -Ad -w4 -tx4 ${image} | grep 464c457f | tail -1 | cut -f1 -d ' '`

dd if=${image} of=${bin} skip=1 bs=${bb_offset} &> /dev/null

#
# The last two segments of the bootblock ELF have the actual
# executable and the hash. 'LOAD' is the executable segment and
# the other is the hash segment. Get their offsets and convert
# to decimal.
#
offs=`readelf -lW ${bin} | tail -2 | awk '{print $1" "$2" "$5}'`
offs=(`printf "%s %u %u %s %u %u" ${offs}`)

#
# Get the executable and hash segments
#
if [ ${offs[0]} = "LOAD" ]; then
        first=${seg}
        second=${hash}
else
        first=${hash}
        second=${seg}
fi

dd if=${bin} skip=${offs[1]} bs=1 count=${offs[2]} of=${first} &> /dev/null
dd if=${bin} skip=${offs[4]} bs=1 count=${offs[5]} of=${second} &> /dev/null

#
# Find the SHA384 hash for the executable segment
#
sha=`sha384sum ${seg} | cut -f1 -d ' ' | sed 's/../& /g'`

echo ===================================================
echo Expected hash:
echo
echo ${sha} | fold -w48
echo ===================================================
echo
hexdump -C ${hash} | grep -A4 "`echo ${sha} | cut -f1-4 -d ' '`"


Change-Id: If57ba0cc9a4f08b69d7712f27c215339307e73d4
Signed-off-by: Varadarajan Narayanan <vnarayan@qualcomm.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88148
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 util/cbfstool/platform_fixups.c | 112 +++++++++++++++++++++++++++++++-
 1 file changed, 111 insertions(+), 1 deletion(-)

diff --git a/util/cbfstool/platform_fixups.c b/util/cbfstool/platform_fixups.c
index 74035bbcd8..7e29cd7e2b 100644
--- a/util/cbfstool/platform_fixups.c
+++ b/util/cbfstool/platform_fixups.c
@@ -7,6 +7,105 @@
 #include "cbfs_sections.h"
 #include "elfparsing.h"
 
+#define	MBN_V7 7
+
+struct mbnv7_hashtbl_seg {
+	uint32_t reserved;
+	uint32_t version;
+	uint32_t common_metadata_size;
+	uint32_t qti_metadata_size;
+	uint32_t oem_metadata_size;
+	uint32_t hash_table_size;
+	uint32_t qti_signature_size;
+	uint32_t qti_certificate_chain_size;
+	uint32_t oem_signature_size;
+	uint32_t oem_certificate_chain_size;
+};
+
+enum hash_table_algo {
+	QUALCOMM_HASH_TABLE_ALGO_SHA384 = 3,
+};
+
+struct common_metadata {
+	uint32_t major;
+	uint32_t minor;
+	uint32_t software_id;
+	uint32_t secondary_software_id;
+	uint32_t hash_table_algorithm;
+	uint32_t measurement_register_target;
+};
+
+static void *qualcomm_find_hash_mbnv7(struct buffer *elf, size_t bb_offset,
+				      struct vb2_hash *real_hash)
+{
+	void *hashtable = NULL, *bb_hash = NULL;
+	struct common_metadata *cmn = NULL;
+	struct mbnv7_hashtbl_seg *mbn;
+	struct parsed_elf pelf;
+	int bb_segment = -1;
+	Elf64_Phdr *ph;
+
+	while (true) {
+		size_t tmp;
+
+		if (!buffer_check_magic(elf, ELFMAG, 4) ||
+		     parse_elf(elf, &pelf, ELF_PARSE_PHDR))
+			return NULL;	/* Not an ELF -- guess not a Qualcomm MBN after all? */
+
+		ph = &pelf.phdr[pelf.ehdr.e_phnum - 1];
+
+		tmp = ph->p_offset + ph->p_filesz;
+
+		if (buffer_offset(elf) < bb_offset &&
+		    bb_offset < (buffer_offset(elf) + tmp)) /* found BB */
+			break;
+
+		parsed_elf_destroy(&pelf);
+
+		buffer_seek(elf, tmp);
+	}
+
+	/* Qualcomm stores an array of SHA-384 hashes in a special ELF segment,
+	   one for each segment in order. */
+	for (int i = 0; i < pelf.ehdr.e_phnum; i++) {
+		ph = &pelf.phdr[i];
+		mbn = buffer_get(elf) + ph->p_offset;
+
+		if (((ph->p_flags & PF_QC_SG_MASK) == PF_QC_SG_HASH) &&
+		    (mbn->version == MBN_V7)) {
+			cmn = buffer_get(elf) + ph->p_offset +
+			      sizeof(*mbn);
+
+			hashtable = buffer_get(elf) + ph->p_offset +
+				    sizeof(*mbn) + mbn->common_metadata_size +
+				    mbn->qti_metadata_size +
+				    mbn->oem_metadata_size;
+		} else if (ph->p_type == PT_LOAD && ph->p_flags == (PF_X | PF_W | PF_R)) {
+			bb_segment = i; /* Found the bootblock segment -- store its index. */
+		}
+	}
+
+	if (!hashtable || !cmn)
+		goto destroy_elf;
+
+	/* MBNv7 supports only SHA384, ensure that. */
+	if (cmn->hash_table_algorithm != QUALCOMM_HASH_TABLE_ALGO_SHA384)
+		goto destroy_elf;
+
+	bb_hash = hashtable + bb_segment * VB2_SHA384_DIGEST_SIZE;
+
+	/* Pass out the actual hash of the current bootblock segment in |real_hash|. */
+	if (vb2_hash_calculate(false, buffer_get(elf) + pelf.phdr[bb_segment].p_offset,
+			       pelf.phdr[bb_segment].p_filesz, VB2_HASH_SHA384, real_hash)) {
+		ERROR("fixups: vboot digest error\n");
+		goto destroy_elf;
+	} /* Return pointer to where the bootblock hash needs to go in Qualcomm's table. */
+
+destroy_elf:
+	parsed_elf_destroy(&pelf);
+	return bb_hash;
+}
+
 /*
  * NOTE: This currently only implements support for MBN version 6 (as used by sc7180). Support
  * for other MBN versions could probably be added but may require more parsing to tell them
@@ -14,6 +113,7 @@
  */
 static void *qualcomm_find_hash(struct buffer *in, size_t bb_offset, struct vb2_hash *real_hash)
 {
+	Elf64_Phdr *ph;
 	struct buffer elf;
 	buffer_clone(&elf, in);
 
@@ -38,6 +138,16 @@ static void *qualcomm_find_hash(struct buffer *in, size_t bb_offset, struct vb2_
 	if (parse_elf(&elf, &pelf, ELF_PARSE_PHDR))
 		return NULL;	/* Not an ELF -- guess not a Qualcomm MBN after all? */
 
+	/*
+	 * Check if it is a multi ELF or single ELF. If bb_offset is beyond the
+	 * final segment of first ELF, it is a multi ELF.
+	 */
+	ph = &pelf.phdr[pelf.ehdr.e_phnum - 1];
+	if (bb_offset > (ph->p_offset + ph->p_filesz)) { /* MBNv7 multi ELF */
+		parsed_elf_destroy(&pelf);
+		return qualcomm_find_hash_mbnv7(&elf, bb_offset, real_hash);
+	}
+
 	/* Qualcomm stores an array of SHA-384 hashes in a special ELF segment. One special one
 	   to start with, and then one for each segment in order. */
 	void *bb_hash = NULL;
@@ -45,7 +155,7 @@ static void *qualcomm_find_hash(struct buffer *in, size_t bb_offset, struct vb2_
 	int i;
 	int bb_segment = -1;
 	for (i = 0; i < pelf.ehdr.e_phnum; i++) {
-		Elf64_Phdr *ph = &pelf.phdr[i];
+		ph = &pelf.phdr[i];
 		if ((ph->p_flags & PF_QC_SG_MASK) == PF_QC_SG_HASH) {
 			if ((int)ph->p_filesz !=
 			    (pelf.ehdr.e_phnum + 1) * VB2_SHA384_DIGEST_SIZE) {

From e5e79de8cc71c75e08fc615c6b27ca754e6f6f09 Mon Sep 17 00:00:00 2001
From: Luca Lai <luca.lai@lcfc.corp-partner.google.com>
Date: Wed, 25 Jun 2025 10:29:25 +0800
Subject: [PATCH 1419/3886] mb/trulo/var/pujjoquince: Add Fingerprint function

1. This change is based on the fact that the code for the pujjolo
and pujjoquince projects is shared.
2. Add fingerprint function and use proto board to verify the
functionality.

Schematic version: 500E_S3A0_TWL_MB_FVT_20250527

BUG=b:395763555
BRANCH=none
TEST=Use ectool --name=cros_fp version will return fingerprint
version information and check the functionality works.

Change-Id: I557c7b6a10b137604ff4abae81c7a231c48b099d
Signed-off-by: Luca Lai <luca.lai@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88186
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/google/brya/variants/pujjolo/gpio.c         | 4 ++--
 .../google/brya/variants/pujjolo/overridetree.cb          | 8 +++++++-
 2 files changed, 9 insertions(+), 3 deletions(-)

diff --git a/src/mainboard/google/brya/variants/pujjolo/gpio.c b/src/mainboard/google/brya/variants/pujjolo/gpio.c
index a3856d4a1a..ac14f0d22f 100644
--- a/src/mainboard/google/brya/variants/pujjolo/gpio.c
+++ b/src/mainboard/google/brya/variants/pujjolo/gpio.c
@@ -118,8 +118,8 @@ static const struct pad_config override_gpio_table[] = {
 	PAD_CFG_GPO_LOCK(GPP_D0, 0, LOCK_CONFIG),
 	/* D1  : ISH_GP1 ==> SOC_GSEN2_INT# */
 	PAD_CFG_NF(GPP_D1, NONE, DEEP, NF1),
-	/* D2  : NC */
-	PAD_NC_LOCK(GPP_D2, NONE, LOCK_CONFIG),
+	/* D2  : NC => EN_FP_PWR */
+	PAD_CFG_GPO_LOCK(GPP_D2, 1, LOCK_CONFIG),
 	/* D3  : ISH_GP3 ==> WCAM_RST_L */
 	PAD_CFG_GPO_LOCK(GPP_D3, 0, LOCK_CONFIG),
 	/* D4  : IMGCLKOUT0 ==> BT_DISABLE_L */
diff --git a/src/mainboard/google/brya/variants/pujjolo/overridetree.cb b/src/mainboard/google/brya/variants/pujjolo/overridetree.cb
index 1ffcf7aadc..c726761fae 100644
--- a/src/mainboard/google/brya/variants/pujjolo/overridetree.cb
+++ b/src/mainboard/google/brya/variants/pujjolo/overridetree.cb
@@ -8,6 +8,10 @@ fw_config
 		option WIFI_SAR_TABLE_AX211	0
 		option WIFI_SAR_TABLE_AX203	1
 	end
+	field FP 24
+		option FP_ABSENT	0
+		option FP_PRESENT	1
+	end
 	field SD_CARD 25
 		option SD_ABSENT	0
 		option SD_PRESENT	1
@@ -630,7 +634,9 @@ chip soc/intel/alderlake
 				register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_E7)"
 				register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D2)"
 				register "enable_delay_ms" = "3"
-				device spi 0 on end
+				device spi 0 on
+					probe FP FP_PRESENT
+				end
 			end # FPMCU
 		end
 		device ref cnvi_wifi on

From 5c281529ea53f1ea706fdd3f3a4c4df0289a0904 Mon Sep 17 00:00:00 2001
From: Luca Lai <luca.lai@lcfc.corp-partner.google.com>
Date: Tue, 17 Jun 2025 14:09:53 +0800
Subject: [PATCH 1420/3886] mb/trulo/var/pujjolo: Add FW_CONFIG for mipi camera

Add FW_CONFIG probe based on pujjolo boxster of below devices:
Mipi camera

Schematic version: 500E_S3A0_TWL_MB_FVT_20250527

BUG=b:395763555
BRANCH=none
TEST=Boot to OS and verify the mipi camera device are set based on
     fw_config.

Change-Id: I8760585d5012073fb3ca1d2636474a07b8eea97a
Signed-off-by: Luca Lai <luca.lai@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88119
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
---
 .../google/brya/variants/pujjolo/overridetree.cb | 16 +++++++++++++---
 1 file changed, 13 insertions(+), 3 deletions(-)

diff --git a/src/mainboard/google/brya/variants/pujjolo/overridetree.cb b/src/mainboard/google/brya/variants/pujjolo/overridetree.cb
index c726761fae..3fca8c3d8f 100644
--- a/src/mainboard/google/brya/variants/pujjolo/overridetree.cb
+++ b/src/mainboard/google/brya/variants/pujjolo/overridetree.cb
@@ -16,6 +16,10 @@ fw_config
 		option SD_ABSENT	0
 		option SD_PRESENT	1
 	end
+	field WFC 26 27
+		option WFC_ABSENT               0
+		option WFC_MIPI_OVTI8856        2
+	end
 end
 chip soc/intel/alderlake
 
@@ -343,7 +347,9 @@ chip soc/intel/alderlake
 				register "off_seq.ops[2]" = "SEQ_OPS_GPIO_DISABLE(1, 0)"
 				register "off_seq.ops[3]" = "SEQ_OPS_GPIO_DISABLE(0, 0)"
 
-				device i2c 10 on end
+				device i2c 10 on
+					probe WFC WFC_MIPI_OVTI8856
+				end
 			end
 			chip drivers/intel/mipi_camera
 				register "acpi_uid" = "3"
@@ -369,7 +375,9 @@ chip soc/intel/alderlake
 				register "off_seq.ops[0]" = "SEQ_OPS_GPIO_DISABLE(1, 0)"
 				register "off_seq.ops[1]" = "SEQ_OPS_GPIO_DISABLE(0, 0)"
 
-				device i2c 0C on end
+				device i2c 0C on
+					probe WFC WFC_MIPI_OVTI8856
+				end
 			end
 			chip drivers/intel/mipi_camera
 				register "acpi_hid" = "ACPI_DT_NAMESPACE_HID"
@@ -397,7 +405,9 @@ chip soc/intel/alderlake
 				register "nvm_width" = "0x10"
 				register "nvm_compat" = ""atmel,24c08""
 
-				device i2c 50 on end
+				device i2c 50 on
+					probe WFC WFC_MIPI_OVTI8856
+				end
 			end
 		end
 		device ref i2c5 on

From 9fe1546ffe29d00a82e1a99d94beccf2ad3c26dc Mon Sep 17 00:00:00 2001
From: Martin Roth <gaumless@gmail.com>
Date: Thu, 26 Jun 2025 18:24:55 -0600
Subject: [PATCH 1421/3886] Docs/releases: Update 25.06 release notes

These are the release notes planned to go out with the 25.06 release.

Note that we've removed the bugs section. We may look at adding
"Fixed Bugs" and "New Bugs" in the future, but it was depressing not
seeing changes between the releases.

Change-Id: I8cedbdb7b05605d1904446590fb25552a7e0c727
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88206
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 .../releases/coreboot-25.06-relnotes.md       | 263 +++++++++++++++---
 1 file changed, 220 insertions(+), 43 deletions(-)

diff --git a/Documentation/releases/coreboot-25.06-relnotes.md b/Documentation/releases/coreboot-25.06-relnotes.md
index 585af8bcf2..50ac305cc7 100644
--- a/Documentation/releases/coreboot-25.06-relnotes.md
+++ b/Documentation/releases/coreboot-25.06-relnotes.md
@@ -1,37 +1,183 @@
 Upcoming release - coreboot 25.06
 ========================================================================
 
-The 25.06 release is scheduled for the end of June, 2025
+The coreboot project is pleased to announce the release of coreboot
+25.06, another milestone in our work promoting the use of open-source
+firmware. This release incorporates almost 900 commits from more than
+120 contributors, bringing enhanced boot splash screen capabilities,
+improved build tooling with GCC 15 support, and expanded wireless power
+management features. Along with these headline improvements, we've
+delivered numerous stability enhancements and infrastructure updates
+that strengthen coreboot's foundation across all supported platforms.
 
+As always, the coreboot project extends our appreciation to everyone who
+contributed to this release. From seasoned developers submitting complex
+patches to newcomers providing valuable feedback and testing, your
+collective efforts make each coreboot release better than the last. The
+continued growth of our contributor base demonstrates the strength and
+vitality of the open firmware community.
 
-Update this document with changes that should be in the release notes.
-
-* Please use Markdown.
-* See the past few release notes for the general format.
-* The chip and board additions and removals will be updated right
-  before the release, so those do not need to be added.
-* Note that all changes before the release are done are marked upcoming.
-  A final version of the notes are done after the release.
-
+The next coreboot release, 25.09, is scheduled for the end of September
+2025.
 
 
 Significant or interesting changes
 ----------------------------------
 
-* Add changes that need a full description here
+### {lib, drivers/intel}: Enhanced boot splash screen framework
 
-* This section should have full descriptions and can or should have
-  a link to the referenced commits.
+A comprehensive overhaul of the boot splash screen infrastructure
+introduces support for multiple logo types and improved rendering
+capabilities. The new framework adds `bmp_load_logo_by_type()` function
+(be5609bdaf, 4373eea5d8) to enable platform-specific logo selection,
+while introducing splash screen footer support for better brand
+presentation.
 
+The enhanced system includes horizontal logo alignment controls
+(dfeaead9f2) and configurable footer bottom margins (97f92d5c69),
+providing OEMs with greater flexibility in customizing the boot
+experience. Additionally, the framework now tracks splash screen
+rendering completion (4c446751c6) through commonlib, enabling better
+coordination between firmware phases and payload handoff.
+
+Low-battery mode detection has been integrated into the splash screen
+system, automatically suppressing OEM footers when battery levels are
+critical (d309a9dfa8). This ensures essential power information takes
+precedence during low-power boot scenarios, improving user experience on
+battery-powered devices.
+
+
+### util/cbfstool: Multi-ELF support for advanced payload configurations
+
+The cbfstool utility has been extended with multi-ELF support
+(0dcea61e7c), enabling more sophisticated payload packaging and
+deployment scenarios. This enhancement allows firmware developers to
+bundle multiple ELF binaries within a single CBFS entry, facilitating
+complex boot scenarios where multiple components need to be loaded
+simultaneously.
+
+The implementation provides better flexibility for hypervisor
+deployments, multi-stage bootloaders, and security-enhanced boot
+configurations where isolation between components is critical. This
+feature particularly benefits platforms requiring trusted execution
+environments or compartmentalized boot processes.
+
+
+### drivers/wifi/generic: Advanced Power Reduction Features
+
+Implementation of both Wi-Fi and Bluetooth Power Reduction Request (PRR)
+DSM functions (d92b6163e7, efa24540b0) significantly improves power
+management capabilities for wireless subsystems. These ACPI methods
+enable operating systems to request aggressive power savings during
+idle periods or when specific wireless functions are not required.
+
+The PRR implementation follows Microsoft's Modern Standby
+specifications, allowing Windows and other operating systems to achieve
+deeper sleep states by coordinating with wireless hardware. This results
+in improved battery life on mobile platforms and better thermal
+management on passively cooled systems.
+
+
+### security/vboot: Enhanced boot phase integrity management
+
+The vboot subsystem now includes CMOS data backup during later boot
+phases (bf330f2dd0), providing additional protection against unexpected
+power events during firmware execution. This change ensures that
+critical configuration data remains consistent even if power is lost
+during complex initialization sequences.
+
+A new VBOOT_EC_SYNC_ESOL Kconfig option (ac4503d0dd) has been introduced
+to provide finer control over Embedded Controller synchronization
+behavior. This allows platforms to optimize EC update procedures based
+on their specific hardware requirements and boot time constraints.
+
+Additionally, MRC cache measurements as runtime data (b5581d556b) have
+been integrated into the trusted boot chain, ensuring that memory
+training data integrity is verified as part of the overall system
+attestation process.
+
+
+### Build system improvements: GCC 15 compatibility and toolchain updates
+
+Comprehensive work has been completed to ensure compatibility with GCC
+15, including fixes for the new -Werror=unterminated-string-initialization
+warning (73cc8a413a). The build system now properly handles modern
+compiler requirements while maintaining backward compatibility with
+existing toolchain versions.
+
+The crossgcc build system has been enhanced with RISC-V ISA
+specification support (89e4fff2d3), enabling more precise control over
+RISC-V target architectures. This improvement allows developers to build
+optimized firmware for specific RISC-V implementations while ensuring
+compatibility across the diverse RISC-V ecosystem.
+
+Submodule management has been significantly improved with better path
+handling (c4eb645a0b) and enhanced logging (f2310ab35e), making it
+easier for developers to track third-party component updates and
+maintain consistent build environments.
+
+
+### Enhanced SoC support: Emerald Rapids and Panther Lake
+
+Support for Intel's 5th Generation Xeon Scalable Processors (Emerald
+Rapids) has been added (9d878fc6c0), bringing coreboot to Intel's latest
+server and workstation platforms. This implementation includes support
+for the expanded feature set and improved power management capabilities
+of the Emerald Rapids architecture.
+
+Panther Lake support continues to evolve with new SKU additions
+(b879342fe6) and VR Fast Vmode threshold optimizations (e58883aace).
+The refactored SoC configuration (cf5696834b) provides a cleaner
+foundation for supporting the full range of Panther Lake variants as
+they become available.
+
+
+### Documentation: Clarification of contributor responsibilities and AI tool usage
+
+A significant policy clarification has been added to the project
+documentation (9ddc9cbfc9) addressing contributor responsibilities,
+particularly in the context of modern development practices including
+the use of AI-assisted tools. This addition reinforces that submitters
+bear full responsibility for ensuring their contributions meet coreboot's
+quality standards and comply with all applicable licensing requirements,
+regardless of how the code was generated or authored.
+
+The new documentation explicitly states that contributors must have all
+necessary rights to submit their work under coreboot's licenses, and
+that violations of third-party rights will result in code removal or
+replacement. This policy applies universally, encompassing contributions
+created through various means including generative AI tooling, ensuring
+the project maintains clear legal standing and quality expectations.
+
+This clarification provides important guidance to the growing coreboot
+community as development practices evolve, establishing clear
+expectations while allowing contributors the flexibility to use whatever
+tools help them create high-quality firmware code.
 
 
 Additional coreboot changes
 ---------------------------
 
-The following are changes across a number of patches, or changes worth
-noting, but not needing a full description.
-
-* Changes that only need a line or two of description go here.
+* Exposed ALWAYS_ALLOW_ABOVE_4G_ALLOCATION in Kconfig for x86 to fix
+  Resizable BAR support on modern GPUs.
+* Enhanced PCI support with SR-IOV Virtual Function BAR resource
+  assignment capabilities
+* Improved SPI driver support for forced 4-byte address mode operation
+  via 0xB7 command sequences
+* Numerous MediaTek MT8189 and MT8196 platform enhancements including
+  eDP, DDP, and AUXADC driver improvements
+* Enhanced memory initialization support across multiple Intel platforms
+  with improved timing and reliability
+* Expanded superio support with addition of Fintek f81966d controller
+* Improved ELOG handling for later boot phase operations
+* Enhanced SMMSTORE driver with 64-bit MMIO address support
+* Comprehensive timing infrastructure improvements with early chip
+  initialization timestamps
+* Libpayload updates focused on ARM64 DMA and MMU fixes, build system
+  improvements, and support for large USB mass storage devices.
+* Add documentation on devicetree, sconfig, cbmem and device operations.
+* Contributor guides updated with new commit message policy, Gerrit
+  instructions, and collaboration details.
 
 
 
@@ -39,50 +185,80 @@ Changes to external resources
 -----------------------------
 
 ### Toolchain updates
-
+* Fix GMP build on GCC 15
+* Add a `RISCV_ISA_SPEC` variable to the toolchain build script to allow
+  for specifying the RISC-V ISA version.
 
 
 ### Git submodule pointers
+* arm-trusted-firmware: Update from commit id e5a1f4abee to 9109143417
+  (523 commits)
+* fsp: Update from commit id 86c9111639 to cc36ae2b57 (9 commits)
+* intel-microcode: Update from commit id 8a62de41c0 to eeb93b7a81 (1
+  commit)
 
 
 ### External payloads
 
+* edk2: Update default branch for MrChromebox repo to 2025-02
 
 
 Platform Updates
 ----------------
 
 ### Added mainboards:
-* To be filled in immediately before the release by the release team
-
-
-### Removed Mainboards
-* To be filled in immediately before the release by the release team
-
+* ASUS H61M-A/USB3
+* CWWK CW-ADL-4L-V1.0
+* CWWK CW-ADLNTB-1C2L-V3.0
+* Google Anakin
+* Google Baze
+* Google Bluey
+* Google Brox RTK EC
+* Google Epic
+* Google Fatcat4ES
+* Google Fatcatite4ES
+* Google Fatcatnuvo4ES
+* Google Felino4ES
+* Google Kaladin
+* Google Kinmen
+* Google Obiwan
+* Google Ocelot4ES
+* Google Ocelotite
+* Google Ocelotite4ES
+* Google Ocelotmchp
+* Google Ocelotmchp4ES
+* Google Pujjocento
+* Google Pujjolo
+* Google Quenbi
+* Google Yoda
+* Intel Google Chrome EC
+* MiTAC Computing R520G6SB
+* MiTAC Computing SC513G6
+* NovaCustom V540TNx (14")
+* NovaCustom V560TNx (16")
+* Siemens MC RPL1
+* Star Labs Byte Mk III (N355)
+* System76 darp11
+* System76 lemp13
 
 ### Updated SoCs
-* To be filled in immediately before the release by the release team
+
+* Added qualcomm/x1p42100
 
 
-
-Plans to move platform support to a branch
-------------------------------------------
-* To be filled in immediately before the release by the release team
-
-
-
-Statistics from the 24.12 to the 25.03 release
+Statistics from the 25.03 to the 25.06 release
 --------------------------------------------
-* To be filled in immediately before the release by the release team
-
-
-
-Significant Known and Open Issues
----------------------------------
-
-Issues from the coreboot bugtracker: <https://ticket.coreboot.org/>
-* To be filled in immediately before the release by the release team
-
+* Total Commits: 879
+* Average Commits per day: 9.95
+* Total lines added: 73596
+* Average lines added per commit: 83.73
+* Number of patches adding more than 100 lines: 84
+* Average lines added per small commit: 40.40
+* Total lines removed: 15717
+* Average lines removed per commit: 17.88
+* Total difference between added and removed: 57879
+* Total authors: 128
+* New authors: 34
 
 
 coreboot Links and Contact Information
@@ -94,3 +270,4 @@ coreboot Links and Contact Information
 * Documentation: <https://doc.coreboot.org>
 * Issue tracker: <https://ticket.coreboot.org/projects/coreboot>
 * Donations: <https://coreboot.org/donate.html>
+

From 30e7e604fb36b153a79d0d83cfc0cc324ff1823f Mon Sep 17 00:00:00 2001
From: Subrata Banik <subratabanik@google.com>
Date: Tue, 24 Jun 2025 11:28:00 +0530
Subject: [PATCH 1422/3886] mb/google/fatcat/var/fatcat Align I2S and DMIC pad
 configuration

This commit aligns the I2S and DMIC pad configurations in `fw_config.c`
and `gpio.c` for the Fatcat mainboard.

The changes include:
- Reordering I2S1 pad configurations in `fw_config.c` to match their
  intended functions (TXD, RXD, SCLK, SFRM).
- Adding I2S2 pad configurations (SCLK, SFRM, TXD, RXD) to
  `fw_config.c`.
- Removing duplicate DMIC_CLK and DMIC_DATA pad configurations from
  `fw_config.c`.
- Moving the CODEC_EN pad configuration from `fp_disable_pads` and
  `fp_enable_pads` in `fw_config.c` to `gpio_table` in `gpio.c`, and
  changing its power state to DEEP (as applicable)
- Updating GPP_F17 to CODEC_INT_N with GPI configuration in `gpio.c`.

These adjustments ensure correct and consistent pad assignments
for audio functionality.

TEST=Able to hear devbeep while booting google/fatcat.

Change-Id: I477ffeef113e2f3a4d0e759b9416f9e7e5427ec3
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88180
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
---
 .../google/fatcat/variants/fatcat/fw_config.c | 31 ++++++++-----------
 .../google/fatcat/variants/fatcat/gpio.c      | 10 ++++--
 2 files changed, 21 insertions(+), 20 deletions(-)

diff --git a/src/mainboard/google/fatcat/variants/fatcat/fw_config.c b/src/mainboard/google/fatcat/variants/fatcat/fw_config.c
index b02878b1b6..75a7a06007 100644
--- a/src/mainboard/google/fatcat/variants/fatcat/fw_config.c
+++ b/src/mainboard/google/fatcat/variants/fatcat/fw_config.c
@@ -22,24 +22,27 @@ static const struct pad_config i2s_enable_pads[] = {
 	PAD_CFG_NF(GPP_D12, NONE, DEEP, NF2),
 	/* I2S0_RXD_HDR */
 	PAD_CFG_NF(GPP_D13, NONE, DEEP, NF2),
-	/* I2S1_SCLK_HDR */
-	PAD_CFG_NF(GPP_S00, NONE, DEEP, NF6),
-	/* I2S1_SFRM_HDR */
-	PAD_CFG_NF(GPP_S01, NONE, DEEP, NF6),
 	/* I2S1_TXD_HDR */
-	PAD_CFG_NF(GPP_S02, NONE, DEEP, NF6),
+	PAD_CFG_NF(GPP_S00, NONE, DEEP, NF6),
 	/* I2S1_RXD_HDR */
+	PAD_CFG_NF(GPP_S01, NONE, DEEP, NF6),
+	/* I2S1_SCLK_HDR */
+	PAD_CFG_NF(GPP_S02, NONE, DEEP, NF6),
+	/* I2S1_SFRM_HDR */
 	PAD_CFG_NF(GPP_S03, NONE, DEEP, NF6),
+	/* I2S2_SCLK_HDR */
+	PAD_CFG_NF(GPP_S04, NONE, DEEP, NF6),
+	/* I2S2_SFRM_HDR */
+	PAD_CFG_NF(GPP_S05, NONE, DEEP, NF6),
+	/* I2S2_TXD_HDR */
+	PAD_CFG_NF(GPP_S06, NONE, DEEP, NF6),
+	/* I2S2_RXD_HDR */
+	PAD_CFG_NF(GPP_S07, NONE, DEEP, NF6),
 
 	/* DMIC_CLK */
 	PAD_CFG_NF(GPP_D16, NONE, DEEP, NF3),
 	/* DMIC_DATA */
 	PAD_CFG_NF(GPP_D17, NONE, DEEP, NF3),
-
-	/* DMIC_CLK */
-	PAD_CFG_NF(GPP_S04, NONE, DEEP, NF5),
-	/* DMIC_DATA */
-	PAD_CFG_NF(GPP_S05, NONE, DEEP, NF5),
 };
 
 static const struct pad_config hda_enable_pads[] = {
@@ -507,12 +510,6 @@ static const struct pad_config fp_disable_pads[] = {
 	/* GPP_D01:     MOD_TCSS1_TYP_A_VBUS_EN */
 	PAD_CFG_GPO(GPP_D01, 1, DEEP),
 	PAD_NC(GPP_E17, NONE),
-	/* FIXME: b/390031369
-	 * use dedicated GPIO PIN for codec enable
-	 * when FPS is enabled.
-	 */
-	/* GPP_E19:     CODEC_EN */
-	PAD_CFG_GPO(GPP_E19, 1, PLTRST),
 	PAD_NC(GPP_E20, NONE),
 	PAD_NC(GPP_F14, NONE),
 	PAD_NC(GPP_F15, NONE),
@@ -526,8 +523,6 @@ static const struct pad_config fp_enable_pads[] = {
 	PAD_CFG_GPI_IRQ_WAKE(GPP_D01, NONE, PWROK, LEVEL, INVERT),
 	/* GPP_E17:     GSPI0A_CS0 */
 	PAD_CFG_NF(GPP_E17, NONE, DEEP, NF5),
-	/* GPP_E19:     FPMCU_PWREN */
-	PAD_CFG_GPO(GPP_E19, 1, DEEP),
 	/* GPP_E20:     FPMCU_FW_UPDATE */
 	PAD_CFG_GPO_LOCK(GPP_E20, 0, LOCK_CONFIG),
 	/* GPP_F14:     GPSI0A_MOSI */
diff --git a/src/mainboard/google/fatcat/variants/fatcat/gpio.c b/src/mainboard/google/fatcat/variants/fatcat/gpio.c
index 6b71c65c5c..6f551f2f18 100644
--- a/src/mainboard/google/fatcat/variants/fatcat/gpio.c
+++ b/src/mainboard/google/fatcat/variants/fatcat/gpio.c
@@ -224,6 +224,12 @@ static const struct pad_config gpio_table[] = {
 	PAD_CFG_GPO(GPP_E16, 1, DEEP),
 	/* GPP_E18:     THC0_SPI1_INT_N_TCH_PNL1 */
 	PAD_CFG_NF(GPP_E18, NONE, DEEP, NF3),
+	/* FIXME: b/390031369
+	 * use dedicated GPIO PIN for codec enable
+	 * when FPS is enabled.
+	 */
+	/* GPP_E19:     CODEC_EN */
+	PAD_CFG_GPO(GPP_E19, 1, DEEP),
 	/* GPP_E21:     I2C_PMC_PD_INT_N */
 	PAD_CFG_NF(GPP_E21, NONE, DEEP, NF1),
 	/* GPP_E22:     THC0_SPI1_DSYNC */
@@ -263,8 +269,8 @@ static const struct pad_config gpio_table[] = {
 	PAD_CFG_NF(GPP_F12, NONE, DEEP, NF8),
 	/* GPP_F13:     THC_I2C1_SDA_TCH_PAD */
 	PAD_CFG_NF(GPP_F13, NONE, DEEP, NF8),
-	/* GPP_F17:     Not used */
-	PAD_CFG_GPI_INT(GPP_F17, NONE, PLTRST, EDGE_BOTH),
+	/* GPP_F17:     CODEC_INT_N */
+	PAD_CFG_GPI(GPP_F17, NONE, DEEP),
 	/* GPP_F18:     TCH_PAD_INT_N */
 	/* NOTE: require rework to switch from GPP_A13 to GPP_F18 */
 	PAD_CFG_GPI_APIC(GPP_F18, NONE, PLTRST, LEVEL, INVERT),

From a01c368a8a55992600db34029b24d753d710b2a8 Mon Sep 17 00:00:00 2001
From: Subrata Banik <subratabanik@google.com>
Date: Thu, 26 Jun 2025 06:36:08 +0000
Subject: [PATCH 1423/3886] drivers/spi: Refactor 4-byte addressing mode
 handling in SPI flash

This commit refactors the logic for entering and exiting 4-byte
addressing mode in the SPI flash driver.

Changes include:
 - Renaming SPI_FLASH_EXIT_4BYTE_STAGE to SPI_FIRST_STAGE to better
   reflect its broader applicability to initial boot stages.
 - Applying SPI_FIRST_STAGE to both the force 4-byte address mode
   and exit 4-byte address mode configurations, ensuring these
   operations are only attempted during the appropriate early boot
   phases.
 - Renaming CMD_FORCE_4BYTE_ADDR_MODE to CMD_ENTER_4BYTE_ADDR_MODE for
   consistency and clearer semantics, as 0xb7 is typically used to enter
   this mode.

BUG=b:417900125
TEST=Able to build google/bluey.

Change-Id: I79e2c7bbd222fd0d76072860bdf3feba7e7d587d
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88203
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
---
 src/drivers/spi/spi_flash.c          | 10 +++++-----
 src/drivers/spi/spi_flash_internal.h |  2 +-
 2 files changed, 6 insertions(+), 6 deletions(-)

diff --git a/src/drivers/spi/spi_flash.c b/src/drivers/spi/spi_flash.c
index 80e937a724..88ed2abda2 100644
--- a/src/drivers/spi/spi_flash.c
+++ b/src/drivers/spi/spi_flash.c
@@ -18,7 +18,7 @@
 #define ADDR_MOD 0
 #endif
 
-#define SPI_FLASH_EXIT_4BYTE_STAGE	\
+#define SPI_FIRST_STAGE	\
 	(ENV_INITIAL_STAGE || CONFIG(BOOT_DEVICE_MEMORY_MAPPED))
 
 static void spi_flash_addr(u32 addr, u8 *cmd)
@@ -564,12 +564,12 @@ int spi_flash_probe(unsigned int bus, unsigned int cs, struct spi_flash *flash)
 			CONFIG_ROM_SIZE);
 	}
 
-	if (CONFIG(SPI_FLASH_FORCE_4_BYTE_ADDR_MODE)) {
-		printk(BIOS_DEBUG, "SF: Force 4-byte addressing mode\n");
-		spi_flash_cmd(&flash->spi, CMD_FORCE_4BYTE_ADDR_MODE, NULL, 0);
+	if (CONFIG(SPI_FLASH_FORCE_4_BYTE_ADDR_MODE) && SPI_FIRST_STAGE) {
+		printk(BIOS_DEBUG, "SF: Entering 4-byte addressing mode\n");
+		spi_flash_cmd(&flash->spi, CMD_ENTER_4BYTE_ADDR_MODE, NULL, 0);
 	}
 
-	if (CONFIG(SPI_FLASH_EXIT_4_BYTE_ADDR_MODE) && SPI_FLASH_EXIT_4BYTE_STAGE) {
+	if (CONFIG(SPI_FLASH_EXIT_4_BYTE_ADDR_MODE) && SPI_FIRST_STAGE) {
 		printk(BIOS_DEBUG, "SF: Exiting 4-byte addressing mode\n");
 		spi_flash_cmd(&flash->spi, CMD_EXIT_4BYTE_ADDR_MODE, NULL, 0);
 	}
diff --git a/src/drivers/spi/spi_flash_internal.h b/src/drivers/spi/spi_flash_internal.h
index 163b6181b7..c20369cdf4 100644
--- a/src/drivers/spi/spi_flash_internal.h
+++ b/src/drivers/spi/spi_flash_internal.h
@@ -22,7 +22,7 @@
 #define CMD_READ_STATUS			0x05
 #define CMD_WRITE_ENABLE		0x06
 
-#define CMD_FORCE_4BYTE_ADDR_MODE	0xb7
+#define CMD_ENTER_4BYTE_ADDR_MODE	0xb7
 
 #define CMD_BLOCK_ERASE			0xD8
 

From 8dec5fcaf8d4821103eb66246bee817e987fc7f8 Mon Sep 17 00:00:00 2001
From: Subrata Banik <subratabanik@google.com>
Date: Tue, 24 Jun 2025 10:21:45 +0000
Subject: [PATCH 1424/3886] drivers/spi: Add 4-byte address mode flag to
 lb_spi_flash

Adds a new flags field to the lb_spi_flash coreboot table to indicate
if the SPI flash is operating in 4-byte address mode.

This allows payloads to query the current address mode directly from the
coreboot table, preventing redundant checks or re-enforcement of the
mode. The flag is set based on the
CONFIG_SPI_FLASH_FORCE_4_BYTE_ADDR_MODE configuration.

Important: `erase_cmd` was reduced from uint32_t to uint8_t.
Only the least significant byte was ever relevant, so this change
ensures accurate type representation, maintains backward compatibility
with existing coreboot table structures, and frees up space.

BUG=b:417900125
TEST=Able to build google/bluey.

Change-Id: I406536432b2a0c7f4108e5b33d5a20c272d917b0
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88181
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
---
 src/commonlib/include/commonlib/coreboot_tables.h | 10 +++++++++-
 src/drivers/spi/spi_flash.c                       |  4 ++++
 2 files changed, 13 insertions(+), 1 deletion(-)

diff --git a/src/commonlib/include/commonlib/coreboot_tables.h b/src/commonlib/include/commonlib/coreboot_tables.h
index 7860a413ce..fefafb87e1 100644
--- a/src/commonlib/include/commonlib/coreboot_tables.h
+++ b/src/commonlib/include/commonlib/coreboot_tables.h
@@ -359,7 +359,15 @@ struct lb_spi_flash {
 	uint32_t size;
 	uint32_t flash_size;
 	uint32_t sector_size;
-	uint32_t erase_cmd;
+	/*
+	 * Note: `erase_cmd` was previously a uint32_t. It's now uint8_t because only
+	 * the lowest byte was used, ensuring backward compatibility with older coreboot
+	 * tables and allowing reuse of the remaining bytes.
+	 */
+	uint8_t erase_cmd;
+#define LB_SPI_FLASH_FLAG_IN_4BYTE_ADDR_MODE    (1 << 0)
+	uint8_t flags;
+	uint16_t reserved;
 	/*
 	 * Number of mmap windows used by the platform to decode addresses between SPI flash
 	 * space and host address space. This determines the number of entries in mmap_table.
diff --git a/src/drivers/spi/spi_flash.c b/src/drivers/spi/spi_flash.c
index 88ed2abda2..dda089e917 100644
--- a/src/drivers/spi/spi_flash.c
+++ b/src/drivers/spi/spi_flash.c
@@ -768,6 +768,10 @@ void lb_spi_flash(struct lb_header *header)
 		flash->mmap_count = spi_flash_get_mmap_windows(table);
 		flash->size += flash->mmap_count * sizeof(*table);
 	}
+
+	/* Pass 4-byte address mode information to payload */
+	if (CONFIG(SPI_FLASH_FORCE_4_BYTE_ADDR_MODE))
+		flash->flags = LB_SPI_FLASH_FLAG_IN_4BYTE_ADDR_MODE;
 }
 
 int spi_flash_ctrlr_protect_region(const struct spi_flash *flash,

From 61d74dc8f7175f004c859e52d37615bc7ae8ad4d Mon Sep 17 00:00:00 2001
From: Subrata Banik <subratabanik@google.com>
Date: Tue, 24 Jun 2025 10:28:00 +0000
Subject: [PATCH 1425/3886] payloads: Propagate SPI flash address mode flag to
 libpayload

This commit extends libpayload's understanding of SPI flash devices by
adding a flags field to both struct cb_spi_flash and struct
sysinfo_t.spi_flash.

The new CB_SPI_FLASH_FLAG_IN_4BYTE_ADDR_MODE flag will be populated
from the coreboot table's lb_spi_flash entry. This allows payloads to
reliably determine if the SPI flash is currently configured for 4-byte
addressing, enabling more robust flash operations without needing to
re-probe or re-enforce the mode.

Note: `erase_cmd` type was changed from uint32_t to uint8_t. This is
because only the lowest byte of the original uint32_t was ever used.
The change ensures proper sizing, maintains compatibility with older
coreboot tables, and makes the remaining space available for new fields.

BUG=b:417900125
TEST=Able to build google/bluey.

Change-Id: I101a50f899e82e9412024a049a9df59c5813313a
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88182
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 payloads/libpayload/include/coreboot_tables.h | 10 +++++++++-
 payloads/libpayload/include/sysinfo.h         |  9 ++++++++-
 payloads/libpayload/libc/coreboot.c           |  1 +
 3 files changed, 18 insertions(+), 2 deletions(-)

diff --git a/payloads/libpayload/include/coreboot_tables.h b/payloads/libpayload/include/coreboot_tables.h
index 5b19ca8422..b43a558b49 100644
--- a/payloads/libpayload/include/coreboot_tables.h
+++ b/payloads/libpayload/include/coreboot_tables.h
@@ -306,7 +306,15 @@ struct cb_spi_flash {
 	uint32_t size;
 	uint32_t flash_size;
 	uint32_t sector_size;
-	uint32_t erase_cmd;
+	/*
+	 * Note: `erase_cmd` was previously a uint32_t. It's now uint8_t because only
+	 * the lowest byte was used, ensuring backward compatibility with older coreboot
+	 * tables and allowing reuse of the remaining bytes.
+	 */
+	uint8_t erase_cmd;
+#define CB_SPI_FLASH_FLAG_IN_4BYTE_ADDR_MODE    (1 << 0)
+	uint8_t flags;
+	uint16_t reserved;
 	/*
 	 * Number of mmap windows used by the platform to decode addresses between SPI flash
 	 * space and host address space. This determines the number of entries in mmap_table.
diff --git a/payloads/libpayload/include/sysinfo.h b/payloads/libpayload/include/sysinfo.h
index 2eb0da32dd..2db306eba9 100644
--- a/payloads/libpayload/include/sysinfo.h
+++ b/payloads/libpayload/include/sysinfo.h
@@ -135,7 +135,14 @@ struct sysinfo_t {
 	struct {
 		uint32_t size;
 		uint32_t sector_size;
-		uint32_t erase_cmd;
+		/*
+		 * Note: `erase_cmd` was previously a uint32_t. It's now uint8_t because only
+		 * the lowest byte was used, ensuring backward compatibility with older coreboot
+		 * tables and allowing reuse of the remaining bytes.
+		 */
+		uint8_t erase_cmd;
+		uint8_t flags;
+		uint16_t reserved;
 		uint32_t mmap_window_count;
 		struct flash_mmap_window mmap_table[SYSINFO_MAX_MMAP_WINDOWS];
 	} spi_flash;
diff --git a/payloads/libpayload/libc/coreboot.c b/payloads/libpayload/libc/coreboot.c
index 7a9f997054..2788f870be 100644
--- a/payloads/libpayload/libc/coreboot.c
+++ b/payloads/libpayload/libc/coreboot.c
@@ -177,6 +177,7 @@ static void cb_parse_spi_flash(void *ptr, struct sysinfo_t *info)
 	info->spi_flash.size = flash->flash_size;
 	info->spi_flash.sector_size = flash->sector_size;
 	info->spi_flash.erase_cmd = flash->erase_cmd;
+	info->spi_flash.flags = flash->flags;
 
 	if (flash->mmap_count == 0)
 		return;

From 1222c704b582fa3283e2b36979d1862298fe85de Mon Sep 17 00:00:00 2001
From: Tongtong Pan <pantongtong@huaqin.corp-partner.google.com>
Date: Fri, 27 Jun 2025 16:45:31 +0800
Subject: [PATCH 1426/3886] mb/google/fatcat/var/felino: Add pull high setting
 on GPP_V12 and NC_LOCK GPP_F09

To ensure that poweroff is normal and DUT can boot to S0
when press power button or lid open in S5 state, the WAKE pin
GPP_V12 needs to be pulled high on soc side and GPP_F09 needs
to be configured as NC_LOCK.

BUG=413283383
TEST=emege-fatcat coreboot and poweroff and
s5 boot functions are normal

Change-Id: Iea8e44aa263dda7e447be1c9e53ffabf93c95a80
Signed-off-by: Tongtong Pan <pantongtong@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88211
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/google/fatcat/variants/felino/gpio.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/src/mainboard/google/fatcat/variants/felino/gpio.c b/src/mainboard/google/fatcat/variants/felino/gpio.c
index 87f4edddc8..8b05f1dfc8 100644
--- a/src/mainboard/google/fatcat/variants/felino/gpio.c
+++ b/src/mainboard/google/fatcat/variants/felino/gpio.c
@@ -266,8 +266,8 @@ static const struct pad_config gpio_table[] = {
 	PAD_NC(GPP_F07, NONE),
 	/* GPP_F08:     NC */
 	PAD_NC(GPP_F08, NONE),
-	/* GPP_F09:     SX_EXIT_HOLDOFF# */
-	PAD_CFG_NF(GPP_F09, NONE, DEEP, NF2),
+	/* GPP_F09:     NC */
+	PAD_NC_LOCK(GPP_F09, NONE, LOCK_CONFIG),
 	/* GPP_F10:     HW_ID7 */
 	PAD_CFG_GPI(GPP_F10, NONE, PLTRST),
 	/* GPP_F11:     TC_RETIMER_FORCE_PWR */
@@ -380,7 +380,7 @@ static const struct pad_config gpio_table[] = {
 	/* GPP_V11:     SLP_LAN_N */
 	PAD_CFG_NF(GPP_V11, NONE, DEEP, NF1),
 	/* GPP_V12:     WAKE# */
-	PAD_CFG_NF(GPP_V12, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_V12, UP_1K, DEEP, NF1),
 	/* GPP_V13:     GPP_V13_CATERR_N */
 	PAD_CFG_NF(GPP_V13, NONE, DEEP, NF1),
 	/* GPP_V14:     GPP_V14_FORCEPR_N */

From dd7956bfc5c8a64a47e82dde06e410c389faf34f Mon Sep 17 00:00:00 2001
From: Sowmya Aralguppe <sowmya.aralguppe@intel.com>
Date: Sun, 15 Jun 2025 23:34:27 +0530
Subject: [PATCH 1427/3886] mb/google/ocelot: Update GPIO table

Configure GPIOs and related settings to align with the specifications
provided in the schematic_1433518 and platform mapping document
version Rev0p85.

BUG=b:394208231
TEST=Build Ocelot and verify it compiles without any error.

Change-Id: Id63c52ffa2d111bd1f7c51831aa7087bef6006d9
Signed-off-by: Sowmya Aralguppe <sowmya.aralguppe@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88102
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Avi Uday <aviuday@google.com>
---
 .../google/ocelot/variants/ocelot/gpio.c      | 568 +++++++++---------
 1 file changed, 289 insertions(+), 279 deletions(-)

diff --git a/src/mainboard/google/ocelot/variants/ocelot/gpio.c b/src/mainboard/google/ocelot/variants/ocelot/gpio.c
index 58f1cb256e..6b11af063e 100644
--- a/src/mainboard/google/ocelot/variants/ocelot/gpio.c
+++ b/src/mainboard/google/ocelot/variants/ocelot/gpio.c
@@ -7,382 +7,392 @@
 
 /* Pad configuration in ramstage*/
 static const struct pad_config gpio_table[] = {
-	/* GPP_A00:     ESPI_ASOC_IO0_R */
-	PAD_CFG_NF(GPP_A00, NONE, DEEP, NF1),
-	/* GPP_A01:     ESPI_SOC_IO1_R */
-	PAD_CFG_NF(GPP_A01, NONE, DEEP, NF1),
-	/* GPP_A02:     ESPI_SOC_IO2_R */
-	PAD_CFG_NF(GPP_A02, NONE, DEEP, NF1),
-	/* GPP_A03:     ESPI_SOC_IO3_R */
-	PAD_CFG_NF(GPP_A03, NONE, DEEP, NF1),
-	/* GPP_A04:     ESPI_SOC_CS_R_L */
-	PAD_CFG_NF(GPP_A04, NONE, DEEP, NF1),
-	/* GPP_A05:     ESPI_SOC_CLK_R */
-	PAD_CFG_NF(GPP_A05, NONE, DEEP, NF1),
-	/* GPP_A06:     ESPI_SOC_RST_L # */
-	PAD_CFG_NF(GPP_A06, NONE, DEEP, NF1),
-	/* GPP_A08:     SSD_PERST_L # */
+	/* GPP_A */
+	/* GPP_A00:     ESPI_IO0_AIC */
+	/*  GPP_A00 : GPP_A00 ==> ESPI_IO0_EC_R configured on reset, do not touch */
+
+	/* GPP_A01:     ESPI_IO1_AIC */
+	/*  GPP_A01 : GPP_A01 ==> ESPI_IO1_EC_R configured on reset, do not touch */
+
+	/* GPP_A02:     ESPI_IO2_AIC */
+	/*  GPP_A02 : GPP_A02 ==> ESPI_IO2_EC_R configured on reset, do not touch */
+
+	/* GPP_A03:     ESPI_IO3_AIC */
+	/*  GPP_A03 : GPP_A03 ==> ESPI_IO3_EC_R configured on reset, do not touch */
+
+	/* GPP_A04:     ESPI_CS0_AIC_N */
+	/*  GPP_A04 : GPP_A04 ==> ESPI_CS0_HDR_L configured on reset, do not touch */
+
+	/* GPP_A05:     ESPI_CLK_AIC */
+	/*  GPP_A05 : GPP_A05 ==> ESPI_CLK_HDR configured on reset, do not touch */
+
+	/* GPP_A06:     ESPI_RST_AIC_N */
+	/*  GPP_A06 : GPP_A06 ==> ESPI_RST_HDR configured on reset, do not touch */
+
+	/* GPP_A08:     M2_GEN4_SSD_RESET_N */
 	PAD_CFG_GPO(GPP_A08, 1, PLTRST),
-	/* GPP_A09:     WWAN_EN */
-	PAD_CFG_GPO(GPP_A09, 0, PLTRST),
-	/* GPP_A10:     WWAN_RF_DISABLE_ODL */
+	/* GPP_A09:     M.2_WWAN_FCP_OFF_N */
+	PAD_CFG_GPO(GPP_A09, 1, PLTRST),
+	/* GPP_A10:     WWAN_DISABLE_N */
 	PAD_CFG_GPO(GPP_A10, 1, PLTRST),
-	/* GPP_A11:     WLAN_PERST_L */
+	/* GPP_A11:     WLAN_RST_N */
 	PAD_CFG_GPO(GPP_A11, 1, PLTRST),
-	/* GPP_A12:     WLAN_PCIE_WAKE_ODL */
+	/* GPP_A12:     WIFI_WAKE_N */
 	PAD_CFG_GPI_SCI_LOW(GPP_A12, NONE, DEEP, LEVEL),
-	/* GPP_A13:     NC */
-	PAD_NC(GPP_A13, NONE),
-	/* GPP_A15:     EN_SPK_PA */
+	/* GPP_A13:     PCIE_LNK_DOWN */
+	PAD_CFG_NF_OWNERSHIP(GPP_A13, NONE, DEEP, NF2, ACPI),
+	/* GPP_A15:     CODEC_GPIO_EN */
 	PAD_CFG_GPO(GPP_A15, 1, DEEP),
 
-	/* GPP_B00:     PMC_I2C_PD_SCL */
+	/* GPP_B */
+	/* GPP_B00:     USBC_SML_CLK_PD */
 	PAD_CFG_NF(GPP_B00, NONE, DEEP, NF1),
-	/* GPP_B01:     PMC_I2C_PD_SDA */
+	/* GPP_B01:     USBC_SML_DATA_PD */
 	PAD_CFG_NF(GPP_B01, NONE, DEEP, NF1),
-	/* GPP_B02:     SOC_I2C_AUDIO_SDA */
-	PAD_CFG_NF(GPP_B02, NONE, DEEP, NF8),
-	/* GPP_B03:     SOC_I2C_AUDIO_SCL */
-	PAD_CFG_NF(GPP_B03, NONE, DEEP, NF8),
-	/* GPP_B04:     GPP_B04_STRAP */
-	PAD_NC(GPP_B04, NONE),
-	/* GPP_B05:     EC_ISH_INT_ODL */
-	PAD_CFG_NF(GPP_B05, NONE, DEEP, NF4),
-	/* GPP_B06:     MEM_STRAP_2 */
-	PAD_CFG_GPI(GPP_B06, NONE, DEEP),
-	/* GPP_B07:     WWAN_SAR_DETECT_ODL */
-	/* FIXME */
-	PAD_CFG_GPI(GPP_B07, NONE, DEEP),
-	/* GPP_B08:     MEM_STRAP_3 */
-	PAD_CFG_GPI(GPP_B08, NONE, DEEP),
-	/* GPP_B09:     BT_DISABLE_L */
-	PAD_CFG_GPO(GPP_B09, 1, PLTRST),
+	/* GPP_B02:     ISH_I2C0_SDA_SNSR_HDR */
+	PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_B02, NONE, DEEP, NF3),
+	/* GPP_B03:     ISH_I2C0_SCL_SNSR_HDR */
+	PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_B03, NONE, DEEP, NF3),
+	/* GPP_B04:     ISH_GP_0_SNSR_HDR */
+	PAD_CFG_NF(GPP_B04, NONE, DEEP, NF4),
+	/* GPP_B06:     SOC_PDB_CTRL */
+	PAD_CFG_GPO(GPP_B06, 0, DEEP),
+	/* GPP_B07:     SLATEMODE_HALLOUT_SNSR_R */
+	PAD_CFG_NF(GPP_B07, NONE, DEEP, NF4),
+	/* GPP_B08:     ISH_GP_4_SNSR_HDR */
+	PAD_CFG_NF(GPP_B08, NONE, DEEP, NF4),
+	/* GPP_B09:     BT_RF_KILL_N */
+	PAD_CFG_GPO(GPP_B09, 1, DEEP),
 	/* GPP_B10:     NC */
 	PAD_NC(GPP_B10, NONE),
-	/* GPP_B12:     SLR_SO_R_L */
+	/* GPP_B12:     PM_SLP_S0_N */
 	PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1),
-	/* GPP_B13:     PLT_RST_L */
+	/* GPP_B13:     PLT_RST_N */
 	PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1),
-	/* GPP_B14:     HDMI_HPD_STRAP */
+	/* GPP_B14:     GPP_B14_DDSP_HPDB */
 	PAD_CFG_NF(GPP_B14, NONE, DEEP, NF2),
-	/* GPP_B16:     NC */
-	PAD_NC(GPP_B16, NONE),
-	/* GPP_B17:     GSC_SOC_INT_ODL */
-	PAD_CFG_GPI(GPP_B17, NONE, DEEP),
-	/* GPP_B18:     ISH_I2C_SENSOR_SDA */
-	PAD_CFG_NF(GPP_B18, NONE, DEEP, NF1),
-	/* GPP_B19:     ISH_I2C_SENSOR_SCL */
-	PAD_CFG_NF(GPP_B19, NONE, DEEP, NF1),
-	/* GPP_B20:     WWAN_RST_ODL */
+	/* GPP_B16:     COINLESS_MODE_SELECT */
+	PAD_CFG_GPI(GPP_B16, NONE, DEEP),
+	/* GPP_B17:     SPI_TPM_INT_N */
+	PAD_CFG_GPI_APIC_LOCK(GPP_B17, NONE, LEVEL, INVERT, LOCK_CONFIG),
+	/* GPP_B18:     ISH_I2C2_SDA_SNSR_HDR */
+	PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_B18, NONE, DEEP, NF1),
+	/* GPP_B19:     ISH_I2C2_SCL_SNSR_HDR */
+	PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_B19, NONE, DEEP, NF1),
+	/* GPP_B20:     WWAN_RST_N */
 	PAD_CFG_GPO(GPP_B20, 1, PLTRST),
-	/* GPP_B21:     USB_RT_FORCE_PWR */
-	/* FIXME */
+	/* GPP_B21:     TCP_RETIMER_FORCE_PWR */
 	PAD_CFG_GPO(GPP_B21, 0, DEEP),
-	/* GPP_B22:     ISH_ACCEL_DB_INT_L */
+	/* GPP_B22:     ISH_GP_5_SNSR_HDR */
 	PAD_CFG_NF(GPP_B22, NONE, DEEP, NF4),
-	/* GPP_B23:     GPP_B23_STRAP */
-	PAD_NC(GPP_B23, NONE),
-	/* GPP_B24:     EC_SOC_INT_ODL */
-	PAD_CFG_GPI(GPP_B24, NONE, DEEP),
-	/* GPP_B25:     GPP_B23_STRAP */
+	/* GPP_B23:     ISH_GP_6_SNSR_HDR */
+	PAD_CFG_NF(GPP_B23, NONE, DEEP, NF4),
+	/* GPP_B24:     ESPI_ALERT0_EC_R_N */
+	PAD_NC(GPP_B24, NONE),
+	/* GPP_B25:     None */
 	PAD_NC(GPP_B25, NONE),
 
-	/* GPP_C00:     NC */
-	PAD_NC(GPP_C00, NONE),
-	/* GPP_C01:     NC */
-	PAD_NC(GPP_C01, NONE),
-	/* GPP_C02:     GPP_C02_STRAP */
+	/* GPP_C */
+	/* GPP_C00:     SPD_SMB_CLK */
+	PAD_CFG_NF(GPP_C00, NONE, DEEP, NF1),
+	/* GPP_C01:     SPD_SMB_DATA */
+	PAD_CFG_NF(GPP_C01, NONE, DEEP, NF1),
+	/* GPP_C02:     NC */
 	PAD_NC(GPP_C02, NONE),
-	/* GPP_C03:     TP_SMB_SML0_CLK */
+	/* GPP_C03:     TCP_LAN_SML0_SCL_R */
 	PAD_CFG_NF(GPP_C03, NONE, DEEP, NF1),
-	/* GPP_C04:     TP_SMB_SML0_DAT */
+	/* GPP_C04:     TCP_LAN_SML0_SDA_R */
 	PAD_CFG_NF(GPP_C04, NONE, DEEP, NF1),
-	/* GPP_C05:     GPP_C05_STRAP */
+	/* GPP_C05:     NC */
 	PAD_NC(GPP_C05, NONE),
 	/* GPP_C06:     NC */
 	PAD_NC(GPP_C06, NONE),
 	/* GPP_C07:     NC */
 	PAD_NC(GPP_C07, NONE),
-	/* GPP_C08:     ASLP_S0_GATE_R */
-	/* FIXME */
-	PAD_CFG_GPO(GPP_C08, 0, DEEP),
-	/* GPP_C09:     WLAN_PCIE_CLKREQ_ODL */
+	/* GPP_C08:     PM_SLP_S0_N_GPP_CNTRL */
+	PAD_CFG_GPO(GPP_C08, 1, PLTRST),
+	/* GPP_C09:     CLKREQ0_X1_GEN4_M2_WLAN_N */
 	PAD_CFG_NF(GPP_C09, NONE, DEEP, NF1),
-	/* GPP_C10:     WIFI_DISABLE_L */
-	PAD_CFG_GPO(GPP_C10, 1, PLTRST),
-	/* GPP_C11:     OPT_PCIE_CLKREQ_ODL */
+	/* GPP_C10:     WIFI_RF_KILL_N */
+	PAD_CFG_GPO(GPP_C10, 1, DEEP),
+	/* GPP_C11:     CLKREQ2_X4_GEN4_DT_CEM_SLOT1_N */
 	PAD_CFG_NF(GPP_C11, NONE, DEEP, NF1),
-	/* GPP_C12:     SSD_PCIE_CLKREQ_ODL */
+	/* GPP_C12:     CLKREQ3_X4_GEN4_M2_SSD_N */
 	PAD_CFG_NF(GPP_C12, NONE, DEEP, NF1),
-	/* GPP_C13:     NC */
-	PAD_NC(GPP_C13, NONE),
-	/* GPP_C14:     NC */
-	PAD_NC(GPP_C14, NONE),
-	/* GPP_C15:     SOC_FP_RST_STRAP_L */
-	PAD_CFG_GPO(GPP_C15, 1, DEEP),
-	/* GPP_C16:     USB_C0_LSX_TX  */
+	/* GPP_C13:     CLKREQ4_X4_GEN4_DT_CEM_SLOT2_N */
+	PAD_CFG_NF(GPP_C13, NONE, DEEP, NF1),
+	/* GPP_C14:     CLKREQ5_X1_GEN1_GBE_LAN_N */
+	PAD_CFG_NF(GPP_C14, NONE, DEEP, NF1),
+	/* GPP_C15:     FPS_RST_N */
+	PAD_CFG_GPO_LOCK(GPP_C15, 1, LOCK_CONFIG),
+	/* GPP_C16:     MOD_TCSS1_LS_TX_DDC_SCL */
 	PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1),
-	/* GPP_C17:     USB_C0_LSX_RX  */
+	/* GPP_C17:     MOD_TCSS1_LS_RX_DDC_SDA */
 	PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1),
-	/* GPP_C18:     USB_C1_LSX_TX  */
+	/* GPP_C18:     MOD_TCSS2_LS_TX_DDC_SCL */
 	PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1),
-	/* GPP_C19:     USB_C1_LSX_TX */
+	/* GPP_C19:     MOD_TCSS2_LS_RX_DDC_SDA */
 	PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1),
-	/* GPP_C20:     USB_C1_LSX_RX */
-	PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1),
-	/* GPP_C22:     DDIB_HDMI_CTRLCLK */
+	/* GPP_C22:     DDPB_HDMI_CTRLCLK */
 	PAD_CFG_NF(GPP_C22, NONE, DEEP, NF2),
-	/* GPP_C23:     DDIB_HDMI_CTRLDATA */
+	/* GPP_C23:     DDPB_HDMI_CTRLDATA */
 	PAD_CFG_NF(GPP_C23, NONE, DEEP, NF2),
 
-	/* GPP_D01:     NC */
-	PAD_NC(GPP_D01, NONE),
+	/* GPP_D */
+	/* GPP_D01:     MOD_TCSS1_TYP_A_VBUS_EN */
+	PAD_CFG_GPO(GPP_D01, 1, DEEP),
 	/* GPP_D02:     SOC_WP_OD */
-	PAD_CFG_GPI(GPP_D02, NONE, DEEP),
-	/* GPP_D03:     OPT_PCIE_WAKE_ODL */
+	PAD_CFG_GPO(GPP_D02, 0, DEEP),
+	/* GPP_D03:     X4_SLOT_WAKE_N */
 	PAD_CFG_GPI_SCI_LOW(GPP_D03, NONE, DEEP, LEVEL),
-	/* GPP_D05:     UART_ISH_RX_DBG_TX */
+	/* GPP_D05:     ISH_UART0_ECAIC_RXD */
 	PAD_CFG_NF(GPP_D05, NONE, DEEP, NF2),
-	/* GPP_D06:     UART_ISH_TX_DBG_RX */
+	/* GPP_D06:     ISH_UART0_ECAIC_TXD */
 	PAD_CFG_NF(GPP_D06, NONE, DEEP, NF2),
-	/* GPP_D07:     NC */
-	PAD_NC(GPP_D07, NONE),
-	/* GPP_D08:     NC */
-	PAD_NC(GPP_D08, NONE),
-	/* GPP_D09:     I2S0_MCLK_R */
-	PAD_CFG_NF(GPP_D09, NONE, DEEP, NF2),
-	/* GPP_D10:     HDA_BCLK_I2S0_SCLK */
+	/* GPP_D07:     ISH_UART0_RTS_N_SNSR_HDR */
+	PAD_CFG_NF(GPP_D07, NONE, DEEP, NF3),
+	/* GPP_D08:     ISH_UART0_CTS_N_SNSR_HDR */
+	PAD_CFG_NF(GPP_D08, NONE, DEEP, NF3),
+	/* GPP_D09:     I2S_MCLK_HDR */
+	PAD_CFG_NF(GPP_D09, NONE, DEEP, NF1),
+	/* GPP_D10:     HDA_BCLK (HDR) */
 	PAD_CFG_NF(GPP_D10, NONE, DEEP, NF1),
-	/* GPP_D11:     HDA_SYNC_I2S0_SFRM */
+	/* GPP_D11:     HDA_SYNC (HDR) */
 	PAD_CFG_NF(GPP_D11, NONE, DEEP, NF1),
-	/* GPP_D12:     HDA_SD0_I2S0_TXD_STRAP */
+	/* GPP_D12:     HDA_SDO (HDR) */
 	PAD_CFG_NF(GPP_D12, NONE, DEEP, NF1),
-	/* GPP_D13:     HDA_SDI0_I2S0_RDX */
+	/* GPP_D13:     HDA_SDI0 (HDR) */
 	PAD_CFG_NF(GPP_D13, NONE, DEEP, NF1),
-	/* GPP_D16:     NC */
-	PAD_NC(GPP_D16, NONE),
-	/* GPP_D17:     NC */
-	PAD_NC(GPP_D17, NONE),
-	/* GPP_D19:     SOC_TCHSCR_REPORT_EN */
-	PAD_CFG_GPO(GPP_D18, 0, DEEP),
-	/* GPP_D21:     SOC_UFS_REFCLK */
+	/* GPP_D16:     HDA_RST_N (HDR) */
+	PAD_CFG_NF(GPP_D16, NONE, DEEP, NF1),
+	/* GPP_D17:     HDA_SDI1 (HDR) */
+	PAD_CFG_NF(GPP_D17, NONE, DEEP, NF1),
+	/* GPP_D19:     NC */
+	PAD_NC(GPP_D19, NONE),
+	/* GPP_D21:     GPP_D21_UFS_REFCLK_R */
 	PAD_CFG_NF(GPP_D21, NONE, DEEP, NF1),
 
-	/* GPP_E01:     EN_WWAN_PWR */
-	PAD_CFG_GPO(GPP_E01, 1, PLTRST),
+	/* GPP_E */
+	/* GPP_E01:     PM_SLP_DRAM_N */
+	PAD_CFG_NF(GPP_E01, NONE, DEEP, NF2),
 	/* GPP_E02:     NC */
 	PAD_NC(GPP_E02, NONE),
-	/* GPP_E03:     OPT_PERST_L */
-	PAD_CFG_GPO(GPP_E03, 1, DEEP),
-	/* GPP_E05:     EN_PWR_FP */
-	PAD_CFG_GPO(GPP_E05, 0, PLTRST),
-	/* GPP_E06:     GPP_E06_STRAP */
-	PAD_NC(GPP_E06, NONE),
-	/* GPP_E07:     NC */
-	PAD_NC(GPP_E07, NONE),
-	/* GPP_E08:     NC */
-	PAD_NC(GPP_E08, NONE),
-	/* GPP_E09:     USB_A_OC_ODL */
+	/* GPP_E03:     X4_DT_PCIE_RST_N */
+	PAD_CFG_GPO(GPP_E03, 1, PLTRST),
+	/* GPP_E05:     GPP_E5_FPS_PWREN */
+	PAD_CFG_GPO(GPP_E05, 1, DEEP),
+	/* GPP_E06:     GPP_E6_PEN_DETECT */
+	PAD_CFG_GPI_TRIG_OWN(GPP_E06, NONE, DEEP, LEVEL, ACPI),
+	/* GPP_E07:     LAN_GPIO_RST_N */
+	PAD_CFG_GPO(GPP_E07, 1, PLTRST),
+	/* GPP_E08:     EC_SOC_INT_ODL */
+	PAD_CFG_GPI(GPP_E08, NONE, DEEP),
+	/* GPP_E09:     USB_FP_CONN_1_CONN_2_OC0_N */
 	PAD_CFG_NF(GPP_E09, NONE, DEEP, NF1),
-	/* GPP_E10:     SD_PE_PRSNT_L */
+	/* GPP_E10:     M2_UFS_DET_SEL_N */
 	PAD_CFG_GPI(GPP_E10, NONE, DEEP),
-	/* GPP_E11:     SPI_SOC_CLK_FP_R */
-	PAD_CFG_NF(GPP_E11, NONE, DEEP, NF5),
-	/* GPP_E12:     SOC_I2C_TCHPAD_SCL */
-	PAD_CFG_NF(GPP_E12, NONE, DEEP, NF1),
-	/* GPP_E13:     SOC_I2C_TCHPAD_SCL */
-	PAD_CFG_NF(GPP_E13, NONE, DEEP, NF1),
-	/* GPP_E14:     NC */
-	PAD_NC(GPP_E14, NONE),
-	/* GPP_E15:     NC */
-	PAD_NC(GPP_E15, NONE),
-	/* GPP_E16:     NC */
-	PAD_NC(GPP_E16, NONE),
-	/* GPP_E17:     SPI_SOC_CS_FP_R_L */
+	/* GPP_E11:     THC0_SPI1_CLK_TCH_PNL1 */
+	PAD_CFG_NF(GPP_E11, NONE, DEEP, NF3),
+	/* GPP_E12:     THC_I2C0_SCL_TCH_PNL1 */
+	PAD_CFG_NF(GPP_E12, NONE, DEEP, NF3),
+	/* GPP_E13:     THC_I2C0_SDA_TCH_PNL1 */
+	PAD_CFG_NF(GPP_E13, NONE, DEEP, NF3),
+	/* GPP_E14:     THC0_SPI1_IO_2_TCH_PNL1 */
+	PAD_CFG_NF(GPP_E14, NONE, DEEP, NF3),
+	/* GPP_E15:     THC0_SPI1_IO_3_TCH_PNL1 */
+	PAD_CFG_NF(GPP_E15, NONE, DEEP, NF3),
+	/* GPP_E16:     THC0_SPI1_RST_N_TCH_PNL1 */
+	PAD_CFG_NF(GPP_E16, NONE, PLTRST, NF1),
+	/* GPP_E17:     GPP_E17_GSPI0A_CS0 */
 	PAD_CFG_NF(GPP_E17, NONE, DEEP, NF5),
-	/* GPP_E18:     SOC_TCHPAD_INT_ODL */
+	/* GPP_E18:     THC0_SPI1_INT_N_TCH_PNL1 */
 	PAD_CFG_NF(GPP_E18, NONE, DEEP, NF3),
-	/* GPP_E19:     FP_SOC_INT_L */
-	PAD_CFG_GPI_SCI_LOW(GPP_E19, NONE, DEEP, LEVEL),
-	/* GPP_E20:     SOC_FP_FW_UP */
-	PAD_CFG_GPO(GPP_E20, 0, DEEP),
-	/* GPP_E21:     PMC_I2C_PD_INT_ODL */
+	/* GPP_E19:     FPS_INT_N */
+	PAD_CFG_GPI_IRQ_WAKE(GPP_E19, NONE, PWROK, LEVEL, INVERT),
+	/* GPP_E20:     FPS_FW_UPDATE */
+	PAD_CFG_GPO_LOCK(GPP_E20, 0, LOCK_CONFIG),
+	/* GPP_E21:     I2C_PMC_PD_INT_N */
 	PAD_CFG_NF(GPP_E21, NONE, DEEP, NF1),
 	/* GPP_E22:     NC */
 	PAD_NC(GPP_E22, NONE),
 
-	/* GPP_F00:     CNV_BRI_DT_R */
-	PAD_CFG_NF(GPP_F00, NONE, DEEP, NF1),
-	/* GPP_F01:     CNV_BRI_RSP */
-	PAD_CFG_NF(GPP_F01, NONE, DEEP, NF1),
-	/* GPP_F02:     WLAN_CNVI_RGI_DT_STRAP_R */
-	PAD_CFG_NF(GPP_F02, NONE, DEEP, NF1),
-	/* GPP_F03:     CNV_RGI_RSP */
-	PAD_CFG_NF(GPP_F03, NONE, DEEP, NF1),
-	/* GPP_F04:     CNV_RF_RST_L */
-	PAD_CFG_NF(GPP_F04, NONE, DEEP, NF1),
-	/* GPP_F05:     CNV_CLKREQ0 */
-	PAD_CFG_NF(GPP_F05, NONE, DEEP, NF3),
-	/* GPP_F06:     COEX3_WWAN_WLAN */
+	/* GPP_F */
+	/* GPP_F00:     M.2_CNV_BRI_DT_BT_UART2_RTS_N */
+	PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_F00, NONE, DEEP, NF1),
+	/* GPP_F01:     M.2_CNV_BRI_RSP_BT_UART2_RXD */
+	PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_F01, NONE, DEEP, NF1),
+	/* GPP_F02:     M.2_CNV_RGI_DT_BT_UART2_TXD */
+	PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_F02, NONE, DEEP, NF1),
+	/* GPP_F03:     M.2_CNV_RGI_RSP_BT_UART2_CTS_N */
+	PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_F03, NONE, DEEP, NF1),
+	/* GPP_F04:     CNV_RF_RESET_R_N */
+	PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_F04, NONE, DEEP, NF1),
+	/* GPP_F05:     CRF_CLKREQ_R */
+	PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_F05, NONE, DEEP, NF3),
+	/* GPP_F06:     DISC_WLAN_WWAN_COEX3 */
 	PAD_CFG_NF(GPP_F06, NONE, DEEP, NF1),
-	/* GPP_F07:     EN_PP3300_SD */
-	PAD_CFG_GPO(GPP_F07, 1, PLTRST),
-	/* GPP_F08:     EN_PP3300_TCHSCR */
+	/* GPP_F07:     FUSA_DIAGTEST_EN_HDR */
+	PAD_CFG_NF(GPP_F07, NONE, DEEP, NF2),
+	/* GPP_F08:     TCH_PNL1_PWR_EN */
 	PAD_CFG_GPO(GPP_F08, 1, PLTRST),
-	/* GPP_F09:     SOC_UFS_RST_L */
-	PAD_CFG_GPO(GPP_F09, 0, PLTRST),
-	/* GPP_F10:     ISH_ACCEL_MB_INT_L */
-	PAD_CFG_NF(GPP_F10, NONE, PLTRST, NF8),
-	/* GPP_F11:     SPI_TCHSCR_CLK */
-	PAD_CFG_NF(GPP_F11, NONE, DEEP, NF3),
-	/* GPP_F12:     SPI_I2C_TCHSCR_MOSI_SCL */
-	PAD_CFG_NF(GPP_F12, NONE, DEEP, NF3),
-	/* GPP_F13:     SPI_I2C_TCHSCR_MISO_SDA */
-	PAD_CFG_NF(GPP_F13, NONE, DEEP, NF3),
-	/* GPP_F14:     SPI_SOC_D0_FP_D1_R */
+	/* GPP_F09:     M2_UFS_RST_N */
+	PAD_CFG_GPO(GPP_F09, 1, DEEP),
+	/* GPP_F10:     X4_PCIE_SLOT1_PWR_EN */
+	PAD_CFG_GPO(GPP_F10, 1, PLTRST),
+	/* GPP_F11:     THC1_SPI2_CLK_TCH_PNL2 */
+	PAD_CFG_NF(GPP_F11, NONE, DEEP, NF11),
+	/* GPP_F12:     THC_I2C1_SCL_TCH_PAD */
+	PAD_CFG_NF(GPP_F12, NONE, DEEP, NF8),
+	/* GPP_F13:     THC_I2C1_SDA_TCH_PAD */
+	PAD_CFG_NF(GPP_F13, NONE, DEEP, NF8),
+	/* GPP_F14:     GPP_F14_GPSI0A_MOSI */
 	PAD_CFG_NF(GPP_F14, NONE, DEEP, NF8),
-	/* GPP_F15:     SPI_SOC_D1_FP_D0 */
+	/* GPP_F15:     GPP_F15_GSPI0A_MISO */
 	PAD_CFG_NF(GPP_F15, NONE, DEEP, NF8),
-	/* GPP_F16:     THCSCR_RST_L */
-	PAD_CFG_NF(GPP_F16, NONE, DEEP, NF3),
-	/* GPP_F17:     SPI_THCSCR_CS_L */
-	PAD_CFG_NF(GPP_F17, NONE, DEEP, NF3),
-	/* GPP_F18:     TCHSCR_INT_ODL */
-	PAD_CFG_NF(GPP_F19, NONE, DEEP, NF3),
-	/* GPP_F19:     GPP_F19_STRAP */
+	/* GPP_F16:     GPP_F16_GSPI0A_CLK */
+	PAD_CFG_NF(GPP_F16, NONE, DEEP, NF8),
+	/* GPP_F17:     CODEC_IRQ_HDR */
+	PAD_CFG_GPI(GPP_F17, NONE, DEEP),
+	/* GPP_F18:     TCH_PAD_INT_N */
+	PAD_CFG_GPI_APIC_DRIVER(GPP_F18, NONE, PLTRST, EDGE_SINGLE, INVERT),
+	/* GPP_F19:     NC */
 	PAD_NC(GPP_F19, NONE),
-	/* GPP_F20:     EC_SOC_REC_SWITCH_ODL */
-	PAD_CFG_GPO(GPP_F20, 0, PLTRST),
-	/* GPP_F22:     NC */
-	PAD_NC(GPP_F22, NONE),
-	/* GPP_F23:     TP_ISH_LID_OPEN */
-	PAD_CFG_NF(GPP_F23, NONE, PLTRST, NF8),
+	/* GPP_F20:     CSE_EARLY_SW */
+	PAD_CFG_GPI(GPP_F20, NONE, DEEP),
+	/* GPP_F22:     THC1_SPI2_DSYNC */
+	PAD_CFG_NF(GPP_F22, NONE, DEEP, NF3),
+	/* GPP_F23:     SMC_LID */
+	PAD_CFG_GPI_SCI_LOW(GPP_F23, NONE, DEEP, LEVEL),
 
-	/* GPP_H02:     GPP_H02_STRAP */
-	PAD_NC(GPP_H02, NONE),
-	/* GPP_H03:     NC */
-	PAD_NC(GPP_H03, NONE),
-	/* GPP_H04:     COEX1_SOC_RX_WWAN_RX_WLAN_TX */
-	PAD_CFG_NF(GPP_H04, NONE, DEEP, NF2),
-	/* GPP_H05:     COEX1_SOC_TX_WWAN_TX_WLAN_RX */
-	PAD_CFG_NF(GPP_H05, NONE, DEEP, NF2),
-	/* GPP_H06:     UART_SOC_RX_FP_TX */
-	PAD_CFG_NF(GPP_H06, NONE, DEEP, NF2),
-	/* GPP_H07:     UART_SOC_TX_FP_RX */
-	PAD_CFG_NF(GPP_H07, NONE, DEEP, NF2),
-	/* GPP_H08:     UART_SOC_RX_DBG_TX */
+	/* GPP_H */
+	/* GPP_H00:     NC */
+	PAD_NC(GPP_H00, NONE),
+	/* GPP_H01:     M2_UFS_SLP_N */
+	PAD_CFG_GPO(GPP_H01, 1, DEEP),
+	/* GPP_H02:     DEBUG_TRACE_PNP */
+	PAD_CFG_GPO(GPP_H02, 1, PLTRST),
+	/* GPP_H03:     MIC MUTE */
+	PAD_CFG_NF(GPP_H03, NONE, DEEP, NF1),
+	/* GPP_H04:     CNV_MFUART2_RXD */
+	PAD_CFG_NF(GPP_H04, NONE, DEEP, NF1),
+	/* GPP_H05:     CNV_MFUART2_TXD */
+	PAD_CFG_NF(GPP_H05, NONE, DEEP, NF1),
+	/* GPP_H06:     I2C3_SCL_AUDIO_HDR */
+	PAD_CFG_NF(GPP_H06, NONE, DEEP, NF1),
+	/* GPP_H07:     I2C3_SDA_AUDIO_HDR */
+	PAD_CFG_NF(GPP_H07, NONE, DEEP, NF1),
+	/* GPP_H08:     SOC_BIOS_LOG_TTK_UART_RX */
 	PAD_CFG_NF(GPP_H08, NONE, DEEP, NF1),
-	/* GPP_H09:     UART_SOC_TX_DBG_RX */
+	/* GPP_H09:     SOC_BIOS_LOG_TTK_UART_TX */
 	PAD_CFG_NF(GPP_H09, NONE, DEEP, NF1),
-	/* GPP_H10:     TP_ISH_TABLET_MODE */
-	PAD_CFG_NF(GPP_H10, NONE, DEEP, NF8),
-	/* GPP_H11:     TP_ISH_GP11 */
-	PAD_CFG_NF(GPP_H11, NONE, DEEP, NF8),
-	/* GPP_H13:     TP_PROC_C10_GATE_L */
+	/* GPP_H10:     UART0_BUF_RTS */
+	PAD_CFG_NF(GPP_H10, NONE, DEEP, NF1),
+	/* GPP_H11:     UART0_BUF_CTS */
+	PAD_CFG_NF(GPP_H11, NONE, DEEP, NF1),
+	/* GPP_H13:     CPU_C10_GATE_N_R */
 	PAD_CFG_NF(GPP_H13, NONE, DEEP, NF1),
-	/* GPP_H14:     NC */
-	PAD_NC(GPP_H14, NONE),
-	/* GPP_H15:     NC */
-	PAD_NC(GPP_H15, NONE),
-	/* GPP_H17:     HP_INT_L */
-	PAD_CFG_GPI_SCI_LOW(GPP_H17, NONE, DEEP, LEVEL),
-	/* GPP_H18:     EN_PP3300_SSD */
+	/* GPP_H14:     ISH_I3C1_SDA_SNSR_HDR */
+	PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_H14, NONE, DEEP, NF4),
+	/* GPP_H15:     ISH_I3C1_SCL_SNSR_HDR */
+	PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_H15, NONE, DEEP, NF4),
+	/* GPP_H17:     MIC MUTE LED */
+	PAD_CFG_NF(GPP_H17, NONE, DEEP, NF1),
+	/* GPP_H18:     GEN4_SSD_PWREN */
 	PAD_CFG_GPO(GPP_H18, 1, DEEP),
-	/* GPP_H19:     TP_SOC_I2C0_I3C0SDA */
-	PAD_CFG_NF(GPP_H19, NONE, DEEP, NF1),
-	/* GPP_H20:     TP_SOC_I2C0_I3C0SCL */
-	PAD_CFG_NF(GPP_H20, NONE, DEEP, NF1),
-	/* GPP_H21:     SOC_I2C_GSC_SDA */
+	/* GPP_H19:     I3C0_SDA_HDR */
+	PAD_CFG_NF(GPP_H19, NONE, DEEP, NF2),
+	/* GPP_H20:     I3C0_SCL_HDR */
+	PAD_CFG_NF(GPP_H20, NONE, DEEP, NF2),
+	/* GPP_H21:     I2C1_SDA_TTK_CHROME */
 	PAD_CFG_NF(GPP_H21, NONE, DEEP, NF1),
-	/* GPP_H22:     SOC_I2C_GSC_SCL */
+	/* GPP_H22:     I2C1_SCL_TTK_CHROME */
 	PAD_CFG_NF(GPP_H22, NONE, DEEP, NF1),
-	/* GPP_H23:     MEM_STRAP_0 */
-	PAD_CFG_GPI(GPP_H23, NONE, DEEP),
-	/* GPP_H24:     MEM_STRAP_1 */
-	PAD_CFG_GPI(GPP_H24, NONE, DEEP),
+	/* GPP_H23:     TP */
+	PAD_CFG_NF(GPP_H23, NONE, DEEP, NF1),
+	/* GPP_H24:     TP */
+	PAD_CFG_NF(GPP_H24, NONE, DEEP, NF1),
 
-	/* GPP_S00:     SDW3_CLK_I2S1_TXD */
+	/* GPP_S */
+	/* GPP_S00:     SNDW3_CLK_CODEC (HDR) */
 	PAD_CFG_NF(GPP_S00, NONE, DEEP, NF1),
-	/* GPP_S01:     SDW3_DAT0 */
+	/* GPP_S01:     SNDW3_DATA0_CODEC (HDR) */
 	PAD_CFG_NF(GPP_S01, NONE, DEEP, NF1),
-	/* GPP_S02:     SDW3_DAT1_I2S1_SCLK */
+	/* GPP_S02:     SNDW3_DATA1_CODEC (HDR) */
 	PAD_CFG_NF(GPP_S02, NONE, DEEP, NF1),
-	/* GPP_S03:     SDW3_DAT2_I2S1_SFRM */
+	/* GPP_S03:     SNDW3_DATA2_CODEC (HDR) */
 	PAD_CFG_NF(GPP_S03, NONE, DEEP, NF1),
-	/* GPP_S04:     DMIC_CLK0_R */
+	/* GPP_S04:     DMIC0_CLK (HDR) */
 	PAD_CFG_NF(GPP_S04, NONE, DEEP, NF5),
-	/* GPP_S05:     DMIC_DATA0_EDP */
+	/* GPP_S05:     DMIC0_DATA (HDR) */
 	PAD_CFG_NF(GPP_S05, NONE, DEEP, NF5),
-	/* GPP_S06:     NC */
-	PAD_NC(GPP_S06, NONE),
-	/* GPP_S07:     NC */
-	PAD_NC(GPP_S07, NONE),
+	/* GPP_S06:     DMIC1_CLK (HDR) */
+	PAD_CFG_NF(GPP_S06, NONE, DEEP, NF5),
+	/* GPP_S07:     DMIC1_DATA (HDR) */
+	PAD_CFG_NF(GPP_S07, NONE, DEEP, NF5),
 
-	/* GPP_V00:     BATLOW_L */
+	/* GPP_V */
+	/* GPP_V00:     PM_BATLOW_N */
 	PAD_CFG_NF(GPP_V00, NONE, DEEP, NF1),
-	/* GPP_V01:     EC_AC_PRESENT_OD */
+	/* GPP_V01:     BC_ACOK_MCP */
 	PAD_CFG_NF(GPP_V01, NONE, DEEP, NF1),
-	/* GPP_V02:     EC_SOC_WAKE_ODL */
-	PAD_CFG_GPI_IRQ_WAKE(GPP_V02, NONE, PLTRST, LEVEL, INVERT),
-	/* GPP_V03:     EC_SOC_PWR_BTN_ODL */
+	/* GPP_V02:     LANWAKE_N_R */
+	PAD_CFG_NF(GPP_V02, NONE, DEEP, NF1),
+	/* GPP_V03:     PWRBTN_MCP_N */
 	PAD_CFG_NF(GPP_V03, NONE, DEEP, NF1),
-	/* GPP_V04:     SLP_S3_L */
+	/* GPP_V04:     PM_SLP_S3_N */
 	PAD_CFG_NF(GPP_V04, NONE, DEEP, NF1),
-	/* GPP_V05:     SLP_S4_L */
+	/* GPP_V05:     PM_SLP_S4_N */
 	PAD_CFG_NF(GPP_V05, NONE, DEEP, NF1),
-	/* GPP_V06:     TP_SLP_A_L */
-	PAD_NC(GPP_V06, NONE),
-	/* GPP_V07:     SOC_WLAN_SUSCLK */
+	/* GPP_V06:     PM_SLP_A_N */
+	PAD_CFG_NF(GPP_V06, NONE, DEEP, NF1),
+	/* GPP_V07:     M.2_BTWIFI_SUS_CLK_LS */
 	PAD_CFG_NF(GPP_V07, NONE, DEEP, NF1),
-	/* GPP_V08:     NC */
-	PAD_NC(GPP_V08, NONE),
-	/* GPP_V09:     SLP_S5_L */
+	/* GPP_V08:     SLP_WLAN_N */
+	PAD_CFG_NF(GPP_V08, NONE, DEEP, NF1),
+	/* GPP_V09:     PM_SLP_S5_N */
 	PAD_CFG_NF(GPP_V09, NONE, DEEP, NF1),
-	/* GPP_V10:     NC */
-	PAD_NC(GPP_V10, NONE),
-	/* GPP_V11:     TP_SLP_LAN_L */
-	PAD_NC(GPP_V11, NONE),
-	/* GPP_V12:     PCH_WAKE_L */
+	/* GPP_V10:     LANPHYPC_R_N */
+	PAD_CFG_NF(GPP_V10, NONE, DEEP, NF1),
+	/* GPP_V11:     PM_SLP_LAN_N */
+	PAD_CFG_NF(GPP_V11, NONE, DEEP, NF1),
+	/* GPP_V12:     WAKE_N */
 	PAD_CFG_NF(GPP_V12, NONE, DEEP, NF1),
-	/* GPP_V16:     EN_VCCST */
+	/* GPP_V13:     GPP_V13_CATERR_N */
+	PAD_CFG_NF(GPP_V13, NONE, DEEP, NF1),
+	/* GPP_V14:     GPP_V14_FORCEPR_N */
+	PAD_CFG_NF(GPP_V14, NONE, DEEP, NF1),
+	/* GPP_V15:     GPP_V15_THERMTRIP_N */
+	PAD_CFG_NF(GPP_V15, NONE, DEEP, NF1),
+	/* GPP_V16:     GPP_V16_VCCST_EN */
 	PAD_CFG_NF(GPP_V16, NONE, DEEP, NF1),
 };
 
 /* Early pad configuration in bootblock */
 static const struct pad_config early_gpio_table[] = {
-	/* GPP_B05:     EC_ISH_INT_ODL */
-	PAD_CFG_NF(GPP_B05, NONE, DEEP, NF4),
-	/* GPP_B17:     GSC_SOC_INT_ODL */
-	PAD_CFG_GPI(GPP_B17, NONE, DEEP),
-	/* GPP_B24:     EC_SOC_INT_ODL */
-	PAD_CFG_GPI(GPP_B24, NONE, DEEP),
-
-	/* GPP_D05:     UART_ISH_RX_DBG_TX */
-	PAD_CFG_NF(GPP_D05, NONE, DEEP, NF2),
-	/* GPP_D06:     UART_ISH_TX_DBG_RX */
-	PAD_CFG_NF(GPP_D06, NONE, DEEP, NF2),
-
-	/* GPP_F20:     EC_SOC_REC_SWITCH_ODL */
-	PAD_CFG_GPO(GPP_F20, 0, PLTRST),
-
-	/* GPP_H06:     UART_SOC_RX_FP_TX */
-	PAD_CFG_NF(GPP_H06, NONE, DEEP, NF2),
-	/* GPP_H07:     UART_SOC_TX_FP_RX */
-	PAD_CFG_NF(GPP_H07, NONE, DEEP, NF2),
-	/* GPP_H08:     UART_SOC_RX_DBG_TX */
+	/* GPP_B17:     SPI_TPM_INT_N */
+	PAD_CFG_GPI_APIC(GPP_B17, NONE, DEEP, LEVEL, INVERT),
+	/* GPP_H06: I2C3_SDA_PSS */
+	PAD_CFG_NF(GPP_H06, NONE, DEEP, NF1),
+	/* GPP_H07: I2C3_SCL_PSS */
+	PAD_CFG_NF(GPP_H07, NONE, DEEP, NF1),
+	/* GPP_H08:     SOC_BIOS_LOG_TTK_UART_RX */
 	PAD_CFG_NF(GPP_H08, NONE, DEEP, NF1),
-	/* GPP_H09:     UART_SOC_TX_DBG_RX */
+	/* GPP_H09:     SOC_BIOS_LOG_TTK_UART_TX */
 	PAD_CFG_NF(GPP_H09, NONE, DEEP, NF1),
-	/* GPP_H21:     SOC_I2C_GSC_SDA */
+	/* GPP_H21:     I2C1_SDA_TTK_CHROME */
 	PAD_CFG_NF(GPP_H21, NONE, DEEP, NF1),
-	/* GPP_H22:     SOC_I2C_GSC_SCL */
+	/* GPP_H22:     I2C1_SCL_TTK_CHROME */
 	PAD_CFG_NF(GPP_H22, NONE, DEEP, NF1),
 };
 
 /* Pad configuration in romstage */
 static const struct pad_config romstage_gpio_table[] = {
-	/* GPP_A08:     SSD_PERST_L */
-	PAD_CFG_GPO(GPP_A08, 0, PLTRST),
+	/* GPP_C00:     SPD_SMB_CLK */
+	PAD_CFG_NF(GPP_C00, NONE, DEEP, NF1),
+	/* GPP_C01:     SPD_SMB_DATA */
+	PAD_CFG_NF(GPP_C01, NONE, DEEP, NF1),
+	/* GPP_C15:     FPS_RST_N */
+	PAD_CFG_GPO(GPP_C15, 0, PLTRST),
 };
 
 const struct pad_config *variant_gpio_table(size_t *num)

From 6fa44461e789d2dc3a55fef772819d69ecbe93a4 Mon Sep 17 00:00:00 2001
From: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Date: Wed, 25 Jun 2025 17:33:30 +0800
Subject: [PATCH 1428/3886] mb/google/fatcat/var/kinmen: Add Fn key scancode

The Fn key on kinmen emits a scancode of 94 (0x5e).

BUG=b:409148565
TEST=Flash kinmen, boot to Linux kernel, and verify that KEY_FN is
generated when pressed using `evtest`

Change-Id: If919c6f421719e06399620b17e1f4f5a161a7de2
Signed-off-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88207
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/google/fatcat/Kconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/src/mainboard/google/fatcat/Kconfig b/src/mainboard/google/fatcat/Kconfig
index af277c8ac9..7a7748dc03 100644
--- a/src/mainboard/google/fatcat/Kconfig
+++ b/src/mainboard/google/fatcat/Kconfig
@@ -112,6 +112,7 @@ config BOARD_GOOGLE_FRANCKA
 config BOARD_GOOGLE_KINMEN
 	select BOARD_GOOGLE_BASEBOARD_FATCAT
 	select HAVE_SLP_S0_GATE
+	select MAINBOARD_HAS_GOOGLE_STRAUSS_KEYBOARD
 
 if BOARD_GOOGLE_FATCAT_COMMON
 

From d0355cb6475551380288f1c331313b61296cfe2c Mon Sep 17 00:00:00 2001
From: Maximilian Brune <maximilian.brune@9elements.com>
Date: Sat, 12 Apr 2025 16:23:57 +0200
Subject: [PATCH 1429/3886] util/amdfwtool: Move APOB_NV quirk to amdfwtool.c

This moves the code to amdfwtool.c, because the subsequent patch needs
it to be there in order to properly update the address_mode.

This patch should not change the binary in ANY way on any platform.

tested: Check that the binary is identical on guybrush, birman_plus,
frostflow, bilby, crater, grunt, myst, onyx_poc, morphius

Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: I9c64c67ff8b9656516344fdafbfd2254abfceeef
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87294
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
---
 util/amdfwtool/amdfwtool.c  | 43 ++++++++++++++++++++++++++++++++++++-
 util/amdfwtool/data_parse.c | 34 -----------------------------
 2 files changed, 42 insertions(+), 35 deletions(-)

diff --git a/util/amdfwtool/amdfwtool.c b/util/amdfwtool/amdfwtool.c
index c28c734721..695a9b7c76 100644
--- a/util/amdfwtool/amdfwtool.c
+++ b/util/amdfwtool/amdfwtool.c
@@ -533,6 +533,30 @@ static void *new_combo_dir(context *ctx, uint32_t cookie)
 	return ptr;
 }
 
+/*
+ * For some SOC generations the APOB_NV binary seems to be treated special regarding the
+ * interpretaion of the source address. No matter the address_mode specified for the address
+ * the memory ABL always seems to the interpret the source address as MMIO address even if
+ * AMD_ADDR_REL_BIOS is specified. So for them we need to always use an MMIO address.
+ * This seems to be a bug which affects all SOCs before phoenix generation.
+ */
+static bool has_apob_nv_quirk(enum platform platform_type)
+{
+	switch (platform_type) {
+	case PLATFORM_CARRIZO:
+	case PLATFORM_STONEYRIDGE:
+	case PLATFORM_RAVEN:
+	case PLATFORM_PICASSO:
+	case PLATFORM_RENOIR:
+	case PLATFORM_CEZANNE:
+	case PLATFORM_MENDOCINO:
+	case PLATFORM_LUCIENNE:
+		return true;
+	default:
+		return false;
+	}
+}
+
 static void copy_psp_header(void *bak, void *orig)
 {
 	uint32_t count = ((psp_directory_header *)orig)->num_entries;
@@ -1410,7 +1434,24 @@ static void integrate_bios_firmwares(context *ctx,
 			biosdir->entries[count].address_mode = SET_ADDR_MODE_BY_TABLE(biosdir);
 			break;
 		case AMD_BIOS_APOB_NV:
-			biosdir->entries[count].source = fw_table[i].src;
+			if (has_apob_nv_quirk(cb_config->soc_id)) {
+				/*
+				 * once ROM3 mapping (>16MiB) is used on any SOC that
+				 * has the apob quirk, this needs to be updated, since
+				 * using an MMIO address is then not as simply as adding
+				 * the SPI_ROM_BASE offset anymore.
+				 */
+				if (fw_table[i].src + fw_table[i].size >= 16*MiB) {
+					fprintf(stderr,
+						"APOB_NV location too high (0x%lx + 0x%lx)\n",
+						fw_table[i].src, fw_table[i].size);
+					amdfwtool_cleanup(ctx);
+					exit(1);
+				}
+				biosdir->entries[count].source = fw_table[i].src + SPI_ROM_BASE; // convert to MMIO address
+			} else {
+				biosdir->entries[count].source = fw_table[i].src;
+			}
 			biosdir->entries[count].address_mode =
 					SET_ADDR_MODE(biosdir, AMD_ADDR_REL_BIOS);
 			biosdir->entries[count].size = fw_table[i].size;
diff --git a/util/amdfwtool/data_parse.c b/util/amdfwtool/data_parse.c
index 4a368f8b3c..154d34dc6a 100644
--- a/util/amdfwtool/data_parse.c
+++ b/util/amdfwtool/data_parse.c
@@ -734,30 +734,6 @@ bool needs_ish(enum platform platform_type)
 		return false;
 }
 
-/*
- * For some SOC generations the APOB_NV binary seems to be treated special regarding the
- * interpretaion of the source address. No matter the address_mode specified for the address
- * the memory ABL always seems to the interpret the source address as MMIO address even if
- * AMD_ADDR_REL_BIOS is specified. So for them we need to always use an MMIO address.
- * This seems to be a bug which affects all SOCs before phoenix generation.
- */
-static bool has_apob_nv_quirk(enum platform platform_type)
-{
-	switch (platform_type) {
-	case PLATFORM_CARRIZO:
-	case PLATFORM_STONEYRIDGE:
-	case PLATFORM_RAVEN:
-	case PLATFORM_PICASSO:
-	case PLATFORM_RENOIR:
-	case PLATFORM_CEZANNE:
-	case PLATFORM_MENDOCINO:
-	case PLATFORM_LUCIENNE:
-		return true;
-	default:
-		return false;
-	}
-}
-
 static bool is_second_gen(enum platform platform_type)
 {
 	switch (platform_type) {
@@ -828,16 +804,6 @@ uint8_t process_config(FILE *config, amd_cb_config *cb_config)
 
 	cb_config->second_gen = is_second_gen(cb_config->soc_id);
 
-	if (has_apob_nv_quirk(cb_config->soc_id)) {
-		for (int i = 0; amd_bios_table[i].type != AMD_BIOS_INVALID; i++) {
-			amd_bios_entry *entry = &amd_bios_table[i];
-			//TODO once ROM3 mapping (>16MiB) is possible, this needs to be updated.
-			if (entry->type == AMD_BIOS_APOB_NV && entry->size > 0) {
-				entry->src += SPI_ROM_BASE; // convert to MMIO address
-			}
-		}
-	}
-
 	if (needs_ish(cb_config->soc_id))
 		cb_config->need_ish = true;
 

From 000ac2cc3814a1edd4ad5908394054b724edefed Mon Sep 17 00:00:00 2001
From: Maximilian Brune <maximilian.brune@9elements.com>
Date: Sat, 12 Apr 2025 23:18:41 +0200
Subject: [PATCH 1430/3886] util/amdfwtool/amdfwtool.c: Use physical address
 for APOB_NV

In order to not change the actual binaries in too many ways,
commit a7eb390796ef ("mb/*/*/*.fmd: Start flash at 0") kept the current
behaviour in which the address mode was set to ADDR_REL_BIOS, but the
address itself was actually a physical address. It has probably only
worked all these years, because PSP/ABL code did apparently ignore the
address mode for this specific binary for generations previous to
phoenix.

Assuming the address mode is actually ignored we might as well use the
right address mode corresponding to the address that is set. That way
tooling that is used to inspect this image is not completely confused.

This sets the ADDR_PHYSICAL address mode to all generations that have
the APOB NV quirk. It therefore only affects these generations (previous
to phoenix).

tested:
Check that the binary is identical on bilby, morphius, kahlee, onyx and
birman_plus. bilby, kahlee, onyx don't have an APOB_NV region. morphius
uses a physical address anyway and birman_plus doesn't have the
apob_nv_quirk.
Check that only the address mode is changed to ADDR_PHYSICAL (and the
checksum of the table) on guybrush, frostflow, crater, chausie.

Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: Ib2edfb27ba0fa316f1fbe31bc0ad8e2060a70f48
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87296
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 util/amdfwtool/amdfwtool.c | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/util/amdfwtool/amdfwtool.c b/util/amdfwtool/amdfwtool.c
index 695a9b7c76..36b205c355 100644
--- a/util/amdfwtool/amdfwtool.c
+++ b/util/amdfwtool/amdfwtool.c
@@ -1449,11 +1449,12 @@ static void integrate_bios_firmwares(context *ctx,
 					exit(1);
 				}
 				biosdir->entries[count].source = fw_table[i].src + SPI_ROM_BASE; // convert to MMIO address
+				biosdir->entries[count].address_mode = AMD_ADDR_PHYSICAL;
 			} else {
 				biosdir->entries[count].source = fw_table[i].src;
-			}
-			biosdir->entries[count].address_mode =
+				biosdir->entries[count].address_mode =
 					SET_ADDR_MODE(biosdir, AMD_ADDR_REL_BIOS);
+			}
 			biosdir->entries[count].size = fw_table[i].size;
 			break;
 		case AMD_BIOS_BIN:

From 4a99023e0fcf3000ec89f7bf4cce2c0ae53d51b2 Mon Sep 17 00:00:00 2001
From: Maximilian Brune <maximilian.brune@9elements.com>
Date: Sat, 12 Apr 2025 16:37:30 +0200
Subject: [PATCH 1431/3886] util/amdfwtool/amdfwread.c: Remove APOB_NV special
 case

There is no need to treat the APOB_NV binary special anymore, as
the mode and address should now always match for the APOB_NV address.
Since phoenix SOC generation this code even errors out on VBOOT
platforms, because APOB_NV address is actually a BIOS relative address.

Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: I64d43e654e3694d7590edcba9a87c98367a7256c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87297
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
---
 util/amdfwtool/amdfwread.c | 5 -----
 1 file changed, 5 deletions(-)

diff --git a/util/amdfwtool/amdfwread.c b/util/amdfwtool/amdfwread.c
index ca61571602..4dd3b0f770 100644
--- a/util/amdfwtool/amdfwread.c
+++ b/util/amdfwtool/amdfwread.c
@@ -262,11 +262,6 @@ static int amdfw_bios_dir_walk(FILE *fw, uint32_t bios_offset, uint32_t cookie,
 			printf("%sBIOS%s: 0x%02x 0x%lx(DRAM-Address)\n",
 				indent, cookie == BHD_COOKIE ? "L1" : "L2",
 				type, current_entries[i].dest);
-		else if (type == AMD_BIOS_APOB_NV)
-			printf("%sBIOS%s: 0x%02x 0x%08lx 0x%08x\n",
-				indent, cookie == BHD_COOKIE ? "L1" : "L2",
-				type, relative_offset(bios_offset, addr, AMD_ADDR_PHYSICAL),
-				current_entries[i].size);
 		else
 			printf("%sBIOS%s: 0x%02x 0x%08lx 0x%08x\n",
 				indent, cookie == BHD_COOKIE ? "L1" : "L2",

From 6b7f697309c3fd2051d6752aca883310ca7759f0 Mon Sep 17 00:00:00 2001
From: Maximilian Brune <maximilian.brune@9elements.com>
Date: Sat, 12 Apr 2025 16:41:28 +0200
Subject: [PATCH 1432/3886] util/amdfwtool/amdfwread.c: Properly error out in
 relative_offset()

The addresses and their modes should now all be correct and we can
therefore treat the case where `addr` and `mode` do not match as an
actual error.

Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: Id12c29648c0437dd082b471689ec3649314dee1c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87298
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
---
 util/amdfwtool/amdfwread.c | 5 +----
 1 file changed, 1 insertion(+), 4 deletions(-)

diff --git a/util/amdfwtool/amdfwread.c b/util/amdfwtool/amdfwread.c
index 4dd3b0f770..f581c1b8d3 100644
--- a/util/amdfwtool/amdfwread.c
+++ b/util/amdfwtool/amdfwread.c
@@ -30,10 +30,7 @@ static uint64_t relative_offset(uint32_t header_offset, uint64_t addr, uint64_t
 	case AMD_ADDR_PHYSICAL:
 		if (addr < SPI_ROM_BASE || addr > (SPI_ROM_BASE + FILE_REL_MASK)) {
 			ERR("Invalid address(%lx) or mode(%lx)\n", addr, mode);
-			/* TODO: fix amdfwtool to program the right address/mode. In guybrush,
-			 * lots of addresses are marked as physical, but they are relative to
-			 * BIOS. Until that is fixed, just leave an error message. */
-			// exit(1);
+			exit(1);
 		}
 		return addr & FILE_REL_MASK;
 

From 731bea2fc146bc96e8bb280b08f5e6bcf05edee2 Mon Sep 17 00:00:00 2001
From: Kun-Yi Chen <kunyi.chen@gmail.com>
Date: Wed, 25 Jun 2025 20:56:22 +0800
Subject: [PATCH 1433/3886] mb/lattepanda/mu: Make VBT compatible with ADL-N
 FSP IPU25.3

Replace `data.vbt` with version from Intel FSP repository to match
the updated FSP release used in this platform.

This change is required when using 3rdparty/fsp/AlderLakeFspBinPkg
commit: 15848ee4934acbd94069454f369e9869bb0f1295
which introduces the "IoT ADL-N IPU25.3 (6114_00)" release.

With the previous VBT, the system boots but fails to display
any graphics output (HDMI) during firmware POST and OS boot.
This updated VBT resolves the display initialization issue.

Source:
https://github.com/intel/FSP/blob/15848ee4934acbd94069454f369e9869bb0f1295/AlderLakeFspBinPkg/IoT/AlderLakeN/Vbt/Vbt_ADLN.bin

Change-Id: If948d3bbef02f516067db0bad07167bdf7c81ce2
Signed-off-by: Kun-Yi Chen <kunyi.chen@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88191
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
---
 src/mainboard/lattepanda/mu/data.vbt | Bin 9216 -> 9216 bytes
 1 file changed, 0 insertions(+), 0 deletions(-)

diff --git a/src/mainboard/lattepanda/mu/data.vbt b/src/mainboard/lattepanda/mu/data.vbt
index fc35e8faf61ab04fe38665d0104af395c1ad9d8b..43dc8b87a897e49d09ed97b15713106881872acd 100644
GIT binary patch
delta 347
zcmZqhXz-XI!K$ca$Y3zJkWqM|fdDH5qZq@7g|3X6EDRh#2qGPTSOJIyfS3u08G)FA
z5r~1Z3=9sFKQf7PFimA-0`fE__cE$8{+qmoQN8{j3&XVp1_1#EM@0dkItB)I2B3BZ
zh64-&j0%ik5is%3f#FyNNL?&c9WMg|Ggw^$R2_)N!0=B2s;&~MjvwNH0}KVI>cF-M
zFbgnDogB#|$Mp|nDaibdlN&%>u+>2B*~!a6T%dQrvM(o}W0C_pJ&{dgvM{rz@Kxp$
zAbrSSaxk+k<L}A6%xN6|fq?5Y1J`6nmX^)+EN{6OlP2f#`%iXY6WP3nUrhu6))GA@

delta 282
zcmZqhXz-XI!OE=E%wRCNkWqM|fdK1o1~G<93tbsiIT%<NI2as&SOLg#074KA!VEw*
z1CYhQz%iMTS(<~Xn~@19sy?}wQGN1OMs-dWhD!+y0s;)mlb<ol88|?A3igTuKrIXm
zd<+cCK<WTP0;2*WNC3nGnRgAONg;Z&8Iv3*SSiqm^2u>P9ur6bkT-d98;}Rq1mvxs
zybj1?0C9o5)03|;$xTjUQ=cr$tSNq)`2<K03W#RqnjFb&%fy*7`2e%+<n_!dEUSQE
ZGb2kWH>2O=a(@5KxA@gWCKs^D0RX0dF(d#0


From eb749f241666acd9b768dc7ae270478918ddb955 Mon Sep 17 00:00:00 2001
From: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Date: Tue, 24 Jun 2025 11:12:46 +0800
Subject: [PATCH 1434/3886] spd/lp5: Add SPD for MT62F2G32D4DS-023 WT:C

Add MT62F2G32D4DS-023 WT:C in the memory_parts.json and re-generate the
SPD.

BUG=b:427327667
TEST=util/spd_tools/bin/spd_gen spd/lp5/memory_parts.json lp5

Change-Id: I8f244c2f91d66ffcbc1ec2642304f77b522da09f
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88178
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
---
 spd/lp5/memory_parts.json                      | 11 +++++++++++
 spd/lp5/set-0/parts_spd_manifest.generated.txt |  1 +
 spd/lp5/set-1/parts_spd_manifest.generated.txt |  1 +
 3 files changed, 13 insertions(+)

diff --git a/spd/lp5/memory_parts.json b/spd/lp5/memory_parts.json
index 3f2d32e055..9f11ee5e61 100644
--- a/spd/lp5/memory_parts.json
+++ b/spd/lp5/memory_parts.json
@@ -317,6 +317,17 @@
                 "speedMbps": 8533,
                 "lp5x": true
             }
+        },
+        {
+            "name": "MT62F2G32D4DS-023 WT:C",
+            "attribs": {
+                "densityPerDieGb": 16,
+                "diesPerPackage": 4,
+                "bitWidthPerChannel": 16,
+                "ranksPerChannel": 2,
+                "speedMbps": 8533,
+                "lp5x": true
+            }
         }
     ]
 }
diff --git a/spd/lp5/set-0/parts_spd_manifest.generated.txt b/spd/lp5/set-0/parts_spd_manifest.generated.txt
index 2a550bfa6a..f2f396099a 100644
--- a/spd/lp5/set-0/parts_spd_manifest.generated.txt
+++ b/spd/lp5/set-0/parts_spd_manifest.generated.txt
@@ -31,3 +31,4 @@ H58G56CK8BX146,spd-11.hex
 K3KL8L80EM-MGCU,spd-11.hex
 K3KL9L90EM-MGCU,spd-10.hex
 H58G66CK8BX147,spd-10.hex
+MT62F2G32D4DS-023 WT:C,spd-10.hex
diff --git a/spd/lp5/set-1/parts_spd_manifest.generated.txt b/spd/lp5/set-1/parts_spd_manifest.generated.txt
index 2a550bfa6a..f2f396099a 100644
--- a/spd/lp5/set-1/parts_spd_manifest.generated.txt
+++ b/spd/lp5/set-1/parts_spd_manifest.generated.txt
@@ -31,3 +31,4 @@ H58G56CK8BX146,spd-11.hex
 K3KL8L80EM-MGCU,spd-11.hex
 K3KL9L90EM-MGCU,spd-10.hex
 H58G66CK8BX147,spd-10.hex
+MT62F2G32D4DS-023 WT:C,spd-10.hex

From baf28f86686984c54e33871faa851669fe94b7a0 Mon Sep 17 00:00:00 2001
From: Luca Lai <luca.lai@lcfc.corp-partner.google.com>
Date: Thu, 26 Jun 2025 10:20:52 +0800
Subject: [PATCH 1435/3886] mb/trulo/var/pujjolo: Add GPE configuration

Follow baseboard nissa and project pujjocento project to setting
GPE configuration.

BUG=b:395763555
BRANCH=none
TEST=Build and boot to OS.

Change-Id: I75deadd0c1b7218c2d0820d637cc2ec02bf9154f
Signed-off-by: Luca Lai <luca.lai@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88199
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/google/brya/variants/pujjolo/overridetree.cb | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/src/mainboard/google/brya/variants/pujjolo/overridetree.cb b/src/mainboard/google/brya/variants/pujjolo/overridetree.cb
index 3fca8c3d8f..9fbff83aa2 100644
--- a/src/mainboard/google/brya/variants/pujjolo/overridetree.cb
+++ b/src/mainboard/google/brya/variants/pujjolo/overridetree.cb
@@ -23,6 +23,11 @@ fw_config
 end
 chip soc/intel/alderlake
 
+	# GPE configuration
+	register "pmc_gpe0_dw0" = "GPP_A"
+	register "pmc_gpe0_dw1" = "GPP_H"
+	register "pmc_gpe0_dw2" = "GPP_F"
+
 	# S0ix enable
 	register "s0ix_enable" = "true"
 

From 58d450d2dc88b77f91780cff8b2fd13dd6b2255f Mon Sep 17 00:00:00 2001
From: Elyes Haouas <ehaouas@noos.fr>
Date: Sat, 28 Jun 2025 08:33:37 +0200
Subject: [PATCH 1436/3886] util/crossgcc/buildgcc: Reorganize toolchain
 version variables

Group the variables by toolchain (GCC vs Clang) and order them by
build sequence.

Change-Id: Ifd911b719882adf1d2e9211f6009b579f8177abe
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88227
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 util/crossgcc/buildgcc | 17 +++++++++++------
 1 file changed, 11 insertions(+), 6 deletions(-)

diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc
index 0e29fbfa10..21c340ca42 100755
--- a/util/crossgcc/buildgcc
+++ b/util/crossgcc/buildgcc
@@ -34,18 +34,23 @@ FETCH_ONLY=0
 USE_COREBOOT_MIRROR=0
 COREBOOT_MIRROR_URL="https://www.coreboot.org/releases/crossgcc-sources"
 
-# GCC toolchain version numbers
+# GCC Toolchain (built first)
+# Math libraries (GCC dependencies)
 GMP_VERSION=6.3.0
 MPFR_VERSION=4.2.1
 MPC_VERSION=1.3.1
+# Core GCC components
 GCC_VERSION=14.2.0
-LIBSTDCXX_VERSION="${GCC_VERSION}"
 BINUTILS_VERSION=2.43.1
-IASL_VERSION=20241212
-# CLANG version number
+LIBSTDCXX_VERSION="${GCC_VERSION}"	# GCC-specific C++ library
+
+# Low-level Tools (built after GCC)
+NASM_VERSION=2.16.03	# x86 assembly
+IASL_VERSION=20241212	# ACPI compiler
+
+# Clang/LLVM Toolchain (alternative to GCC, built separately)
 CLANG_VERSION=18.1.8
-CMAKE_VERSION=3.31.3
-NASM_VERSION=2.16.03
+CMAKE_VERSION=3.31.3	# Required for building Clang
 
 # Architecture-specific options
 RISCV_ISA_SPEC=20191213

From 5228b3ef7b1d380d566edd2ddcf70ccc792c742c Mon Sep 17 00:00:00 2001
From: Martin Roth <gaumless@gmail.com>
Date: Sat, 28 Jun 2025 10:05:35 -0600
Subject: [PATCH 1437/3886] util/lint: Ignore binary files for cb lowercase
 linter

The binary files were not being correctly filtered. This tells grep to
just ignore binary files. This isn't particularly important inside the
git tree, but for releases where we can't use git grep, it becomes an
issue.

Change-Id: I2852ea1e8b0f337aa5c78daa5e9dbd0c3d6768a9
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88234
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
---
 util/lint/lint-stable-021-coreboot-lowercase | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/util/lint/lint-stable-021-coreboot-lowercase b/util/lint/lint-stable-021-coreboot-lowercase
index 33ade6ded3..3b19358e3c 100755
--- a/util/lint/lint-stable-021-coreboot-lowercase
+++ b/util/lint/lint-stable-021-coreboot-lowercase
@@ -12,7 +12,7 @@ LINTDIR="$(
 # shellcheck source=helper_functions.sh
 . "${LINTDIR}/helper_functions.sh"
 
-EXCLUDE='^3rdparty/\|util/crossgcc/xgcc\|Binary file\|coreboot\|COREBOOT\|CorebootPayload\|CorebootModule\|minnowboard.org/Coreboot\|.*\.patch$\|CorebootBdsLib\|^payloads/external'
+EXCLUDE='^3rdparty/\|util/crossgcc/xgcc\|coreboot\|COREBOOT\|CorebootPayload\|CorebootModule\|minnowboard.org/Coreboot\|.*\.patch$\|CorebootBdsLib\|^payloads/external'
 
 # # Check last commit message if the code is in a git repo
 if [ "${IN_GIT_TREE}" -eq 1 ]; then
@@ -21,4 +21,4 @@ if [ "${IN_GIT_TREE}" -eq 1 ]; then
 	fi
 fi
 
-${GREP_FILES} -in "coreboot" | grep -v "$EXCLUDE";
+${GREP_FILES} -inI "coreboot" | grep -v "$EXCLUDE";

From 6cb9efa19a3d5889ff3397911d15afc35a12aff3 Mon Sep 17 00:00:00 2001
From: Martin Roth <gaumless@gmail.com>
Date: Sat, 28 Jun 2025 10:09:44 -0600
Subject: [PATCH 1438/3886] util/lint: Ignore opensil for Kconfig linter

The Kconfig linter was browsing into the openSIL tree and reporting
issues for the release because it can't use git grep there. This change
explicitly tells the Kconfig linter to ignore the openSIL submodule.

Change-Id: Ia0399225cced9f199a6d2a90bc6c2af905ff4e99
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88235
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
---
 util/lint/kconfig_lint | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/util/lint/kconfig_lint b/util/lint/kconfig_lint
index 21e40c6aa4..551faabdbb 100755
--- a/util/lint/kconfig_lint
+++ b/util/lint/kconfig_lint
@@ -33,7 +33,7 @@ my $root_dir       = "src";           # Directory of the top level Kconfig file
 my $errors_found   = 0;               # count of errors
 my $warnings_found = 0;
 my $exclude_dirs_and_files =
-  '^build/\|^coreboot-builds/\|^configs/\|^util/\|^\.git/\|^payloads\|^Documentation\|^3rdparty'
+  '^build/\|^coreboot-builds/\|^configs/\|^util/\|^\.git/\|^payloads\|^Documentation\|^3rdparty\|^src/vendorcode/amd/opensil/genoa_poc/opensil'
   . '\|' .                            # directories to exclude when searching for used symbols
   '\.config\|\.txt$\|\.tex$\|\.tags\|/kconfig.h\|\.fmd'; #files to exclude when looking for symbols
 my $payload_files_to_check='payloads/Makefile.mk payloads/external/Makefile.mk';

From a0f2e428799b306f8e2f969f839b9fc1fd3ebbdb Mon Sep 17 00:00:00 2001
From: Martin Roth <gaumless@gmail.com>
Date: Sat, 28 Jun 2025 10:24:45 -0600
Subject: [PATCH 1439/3886] util/lint: Improve final newline check

- Change .inc to .mk. This was missed when renaming the makefiles.
- Verify that dirs/files exist before checking.
- Use $FINDOPTS to control search when not in a git repo.

Change-Id: If0d80403a3e799b8103164cc075601a50c33a8d9
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88238
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
---
 util/lint/lint-extended-015-final-newlines | 16 +++++++++-------
 1 file changed, 9 insertions(+), 7 deletions(-)

diff --git a/util/lint/lint-extended-015-final-newlines b/util/lint/lint-extended-015-final-newlines
index 7324213034..e67943e133 100755
--- a/util/lint/lint-extended-015-final-newlines
+++ b/util/lint/lint-extended-015-final-newlines
@@ -13,7 +13,7 @@ LINTDIR="$(
 . "${LINTDIR}/helper_functions.sh"
 
 PIDS=""
-INCLUDED_DIRS_AND_FILES='util/* src/* payloads/* configs/* Makefile *.inc'
+INCLUDED_DIRS_AND_FILES='util/* src/* payloads/* configs/* Makefile *.mk'
 EXCLUDED_DIRS="\
 src/vendorcode/\|\
 cbfstool/lzma/\|\
@@ -64,12 +64,14 @@ test_for_final_newline() {
 	done
 }
 
-for directory in $INCLUDED_DIRS_AND_FILES ; do
-	${FIND_FILES} "${directory}" | sed 's|^\./||' | sort | \
-		grep -v "$EXCLUDED_DIRS" | \
-		grep -v "$EXCLUDED_FILES" | \
-		test_for_final_newline &
-	PIDS="$PIDS $!"
+for dir_or_file in $INCLUDED_DIRS_AND_FILES; do
+	if [ -e "${dir_or_file}" ] || [ -d "${dir_or_file}" ]; then
+		${FIND_FILES} "${dir_or_file}" ${FINDOPTS} | sed 's|^\./||' | sort | \
+			grep -v "$EXCLUDED_DIRS" | \
+			grep -v "$EXCLUDED_FILES" | \
+			test_for_final_newline &
+		PIDS="$PIDS $!"
+	fi
 done
 
 # wait for tests to finish.

From bd36a4a465d503e0b7c26074ab884c5704c15c9a Mon Sep 17 00:00:00 2001
From: Martin Roth <gaumless@gmail.com>
Date: Sat, 28 Jun 2025 10:16:55 -0600
Subject: [PATCH 1440/3886] util/lint: Remove missing dirs from checkpatch
 linter

The mb/adlink directory no longer exists, so remove it from the list of
checked directories.
Add a check to make sure that the directory exists before trying to lint
it in the future.

Change-Id: I59874cb7356c2e8eeb8fc216f2930b3d8ef513c7
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88237
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 util/lint/lint-extended-007-checkpatch | 8 +++++---
 1 file changed, 5 insertions(+), 3 deletions(-)

diff --git a/util/lint/lint-extended-007-checkpatch b/util/lint/lint-extended-007-checkpatch
index 24d505be78..193fb17b6a 100755
--- a/util/lint/lint-extended-007-checkpatch
+++ b/util/lint/lint-extended-007-checkpatch
@@ -10,13 +10,15 @@ src/cpu/armltd src/cpu/qemu-power8 src/cpu/qemu-x86 \
 src/drivers/ti \
 src/ec/purism \
 src/include/boot src/include/superio src/include/sys \
-src/mainboard/adlink src/mainboard/purism src/mainboard/ti \
+src/mainboard/purism src/mainboard/ti \
 src/superio/acpi src/superio/common \
 "
 
 for directory in $DIRS; do
-	util/lint/lint-007-checkpatch "$directory" &
-	PIDS="$PIDS $!"
+	if [ -d "$directory" ]; then
+		util/lint/lint-007-checkpatch "$directory" &
+		PIDS="$PIDS $!"
+	fi
 done
 
 # wait for tests to finish.

From 35d6ee92238477740f8e48ca4c6934989bfc0c65 Mon Sep 17 00:00:00 2001
From: Elyes Haouas <ehaouas@noos.fr>
Date: Sat, 28 Jun 2025 11:12:33 +0200
Subject: [PATCH 1441/3886] crossgcc/buildgcc: Remove invalid option for CMake

"--parallel" is not a valid option for CMake.

Change-Id: Idba76ce6a29e5d582ce49aa91ce4013aebc6d835
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88230
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
---
 util/crossgcc/buildgcc | 1 -
 1 file changed, 1 deletion(-)

diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc
index 21c340ca42..3d570e009c 100755
--- a/util/crossgcc/buildgcc
+++ b/util/crossgcc/buildgcc
@@ -941,7 +941,6 @@ build_LLVM() {
 build_CMAKE() {
 	CC="$(hostcc host)" CXX="$(hostcxx host)" CFLAGS="$HOSTCFLAGS" \
 	../${CMAKE_DIR}/configure \
-		--parallel=${THREADS} \
 		--prefix="$TARGETDIR" || touch .failed
 	# shellcheck disable=SC2086
 	$MAKE $JOBS || touch .failed

From f9cde87f5a4fbe5081304444261fa0e706429da3 Mon Sep 17 00:00:00 2001
From: Elyes Haouas <ehaouas@noos.fr>
Date: Sat, 7 Jun 2025 08:49:39 +0200
Subject: [PATCH 1442/3886] crossgcc/buildgcc: Fix GMP-6.3.0 build with GCC 15
 using proper prototypes

The old test code used outdated function declarations that break with
C23 in GCC 15. Instead of forcing C17 standard:

1. Add full prototype for g() function
2. Use 'void' for empty parameters
3. Clean up messy formatting

This keeps C23 compatibility while fixing the build.

Tested with GCC 15.1.0

The -std=gnu17 workaround is no longer needed.

Change-Id: I718a5ed5c11742b1c3448abf7198c96ac78bc98a
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87995
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
---
 util/crossgcc/buildgcc                        |   4 +-
 .../gmp-6.3.0_fix-c23-prototypes.patch        | 100 ++++++++++++++++++
 2 files changed, 101 insertions(+), 3 deletions(-)
 create mode 100644 util/crossgcc/patches/gmp-6.3.0_fix-c23-prototypes.patch

diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc
index 3d570e009c..66fdf91c07 100755
--- a/util/crossgcc/buildgcc
+++ b/util/crossgcc/buildgcc
@@ -662,9 +662,7 @@ build_GMP() {
 	fi
 
 	# shellcheck disable=SC2086
-	# Bug: GMP currently does not support being build by GCC 15 (--std=gnu23)
-	#      Remove CFLAGS once it works again.
-	CC="$(hostcc host)" CXX="$(hostcxx host)" CFLAGS="-std=gnu17" \
+	CC="$(hostcc host)" CXX="$(hostcxx host)" \
 	../${GMP_DIR}/configure \
 		--disable-shared \
 		--enable-fat \
diff --git a/util/crossgcc/patches/gmp-6.3.0_fix-c23-prototypes.patch b/util/crossgcc/patches/gmp-6.3.0_fix-c23-prototypes.patch
new file mode 100644
index 0000000000..4d8105bcfb
--- /dev/null
+++ b/util/crossgcc/patches/gmp-6.3.0_fix-c23-prototypes.patch
@@ -0,0 +1,100 @@
+Resolves compilation errors with GCC 15+ in C23 mode by:
+. Adding explicit function prototypes for `g()`
+. Modernizing K&R-style function declarations
+. Fixing void parameter signatures
+--- gmp-6.3.0/configure
++++ gmp-6.3.0/configure
+@@ -6567,13 +6567,39 @@
+    1666 to segfault with e.g., -O2 -mpowerpc64.  */
+ 
+ #if defined (__GNUC__) && ! defined (__cplusplus)
+-typedef unsigned long long t1;typedef t1*t2;
+-void g(){}
+-void h(){}
+-static __inline__ t1 e(t2 rp,t2 up,int n,t1 v0)
+-{t1 c,x,r;int i;if(v0){c=1;for(i=1;i<n;i++){x=up[i];r=x+1;rp[i]=r;}}return c;}
+-void f(){static const struct{t1 n;t1 src[9];t1 want[9];}d[]={{1,{0},{1}},};t1 got[9];int i;
+-for(i=0;i<1;i++){if(e(got,got,9,d[i].n)==0)h();g(i,d[i].src,d[i].n,got,d[i].want,9);if(d[i].n)h();}}
++typedef unsigned long long t1;
++typedef t1 *t2;
++void g(void) { }
++void h(void) { }
++static __inline__ t1 e(t2 rp, t2 up, int n, t1 v0)
++{
++  t1 c, x, r;
++  int i;
++  if (v0) {
++    c = 1;
++    for (i = 1; i < n; i++) {
++      x = up[i];
++      r = x + 1;
++      rp[i] = r;
++    }
++  }
++  return c;
++}
++void f(void)
++{
++  static const struct { t1 n; t1 src[9]; t1 want[9]; } d[] = {
++    { 1, { 0 }, { 1 } },
++  };
++  t1 got[9];
++  int i;
++  for (i = 0; i < 1; i++) {
++    if (e(got, got, 9, d[i].n) == 0)
++      h();
++    g();
++    if (d[i].n)
++      h();
++  }
++}
+ #else
+ int dummy;
+ #endif
+@@ -8186,13 +8212,39 @@
+    1666 to segfault with e.g., -O2 -mpowerpc64.  */
+ 
+ #if defined (__GNUC__) && ! defined (__cplusplus)
+-typedef unsigned long long t1;typedef t1*t2;
+-void g(){}
+-void h(){}
+-static __inline__ t1 e(t2 rp,t2 up,int n,t1 v0)
+-{t1 c,x,r;int i;if(v0){c=1;for(i=1;i<n;i++){x=up[i];r=x+1;rp[i]=r;}}return c;}
+-void f(){static const struct{t1 n;t1 src[9];t1 want[9];}d[]={{1,{0},{1}},};t1 got[9];int i;
+-for(i=0;i<1;i++){if(e(got,got,9,d[i].n)==0)h();g(i,d[i].src,d[i].n,got,d[i].want,9);if(d[i].n)h();}}
++typedef unsigned long long t1;
++typedef t1 *t2;
++void g(void) { }
++void h(void) { }
++static __inline__ t1 e(t2 rp, t2 up, int n, t1 v0)
++{
++  t1 c, x, r;
++  int i;
++  if (v0) {
++    c = 1;
++    for (i = 1; i < n; i++) {
++      x = up[i];
++      r = x + 1;
++      rp[i] = r;
++    }
++  }
++  return c;
++}
++void f(void)
++{
++  static const struct { t1 n; t1 src[9]; t1 want[9]; } d[] = {
++    { 1, { 0 }, { 1 } },
++  };
++  t1 got[9];
++  int i;
++  for (i = 0; i < 1; i++) {
++    if (e(got, got, 9, d[i].n) == 0)
++      h();
++    g();
++    if (d[i].n)
++      h();
++  }
++}
+ #else
+ int dummy;
+ #endif

From a3ea1cb542883b2d6c07eda83e94be5e4ad7d686 Mon Sep 17 00:00:00 2001
From: Elyes Haouas <ehaouas@noos.fr>
Date: Sun, 29 Jun 2025 14:53:58 +0200
Subject: [PATCH 1443/3886] util/crossgcc: Upgrade CMake from 3.31.3 to 4.0.3

Change-Id: I46f63e0b6c41f871ccff2454b2db8b99b765d4f5
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86975
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
---
 util/crossgcc/buildgcc                      | 2 +-
 util/crossgcc/sum/cmake-3.31.3.tar.gz.cksum | 1 -
 util/crossgcc/sum/cmake-4.0.3.tar.gz.cksum  | 1 +
 3 files changed, 2 insertions(+), 2 deletions(-)
 delete mode 100644 util/crossgcc/sum/cmake-3.31.3.tar.gz.cksum
 create mode 100644 util/crossgcc/sum/cmake-4.0.3.tar.gz.cksum

diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc
index 66fdf91c07..8dd25b5410 100755
--- a/util/crossgcc/buildgcc
+++ b/util/crossgcc/buildgcc
@@ -50,7 +50,7 @@ IASL_VERSION=20241212	# ACPI compiler
 
 # Clang/LLVM Toolchain (alternative to GCC, built separately)
 CLANG_VERSION=18.1.8
-CMAKE_VERSION=3.31.3	# Required for building Clang
+CMAKE_VERSION=4.0.3	# Required for building Clang
 
 # Architecture-specific options
 RISCV_ISA_SPEC=20191213
diff --git a/util/crossgcc/sum/cmake-3.31.3.tar.gz.cksum b/util/crossgcc/sum/cmake-3.31.3.tar.gz.cksum
deleted file mode 100644
index cef715c2d6..0000000000
--- a/util/crossgcc/sum/cmake-3.31.3.tar.gz.cksum
+++ /dev/null
@@ -1 +0,0 @@
-7ce645495d3c79e0a5763fff08c5a78aea877258  tarballs/cmake-3.31.3.tar.gz
diff --git a/util/crossgcc/sum/cmake-4.0.3.tar.gz.cksum b/util/crossgcc/sum/cmake-4.0.3.tar.gz.cksum
new file mode 100644
index 0000000000..627deeef6e
--- /dev/null
+++ b/util/crossgcc/sum/cmake-4.0.3.tar.gz.cksum
@@ -0,0 +1 @@
+6899c8d69ba2bf1f24c6f27bcea4162e1488694b  tarballs/cmake-4.0.3.tar.gz

From c3f5d7c1eecbe0790c9aabd66e81071d1bda4bd4 Mon Sep 17 00:00:00 2001
From: Elyes Haouas <ehaouas@noos.fr>
Date: Tue, 25 Mar 2025 20:57:50 +0100
Subject: [PATCH 1444/3886] crossgcc: Upgrade MPFR from 4.2.1 to 4.2.2

Change-Id: I5e8d8daa40d05652cacd1a5e355dff10e289d9d0
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86995
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
---
 util/crossgcc/buildgcc                    | 2 +-
 util/crossgcc/sum/mpfr-4.2.1.tar.xz.cksum | 1 -
 util/crossgcc/sum/mpfr-4.2.2.tar.xz.cksum | 1 +
 3 files changed, 2 insertions(+), 2 deletions(-)
 delete mode 100644 util/crossgcc/sum/mpfr-4.2.1.tar.xz.cksum
 create mode 100644 util/crossgcc/sum/mpfr-4.2.2.tar.xz.cksum

diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc
index 8dd25b5410..c961947d9b 100755
--- a/util/crossgcc/buildgcc
+++ b/util/crossgcc/buildgcc
@@ -37,7 +37,7 @@ COREBOOT_MIRROR_URL="https://www.coreboot.org/releases/crossgcc-sources"
 # GCC Toolchain (built first)
 # Math libraries (GCC dependencies)
 GMP_VERSION=6.3.0
-MPFR_VERSION=4.2.1
+MPFR_VERSION=4.2.2
 MPC_VERSION=1.3.1
 # Core GCC components
 GCC_VERSION=14.2.0
diff --git a/util/crossgcc/sum/mpfr-4.2.1.tar.xz.cksum b/util/crossgcc/sum/mpfr-4.2.1.tar.xz.cksum
deleted file mode 100644
index b74dc6257e..0000000000
--- a/util/crossgcc/sum/mpfr-4.2.1.tar.xz.cksum
+++ /dev/null
@@ -1 +0,0 @@
-31ffb4244cb469e2b4937cce1f50150300971dfb  tarballs/mpfr-4.2.1.tar.xz
diff --git a/util/crossgcc/sum/mpfr-4.2.2.tar.xz.cksum b/util/crossgcc/sum/mpfr-4.2.2.tar.xz.cksum
new file mode 100644
index 0000000000..10c2ffc20c
--- /dev/null
+++ b/util/crossgcc/sum/mpfr-4.2.2.tar.xz.cksum
@@ -0,0 +1 @@
+a63a264b273a652e27518443640e69567da498ce  tarballs/mpfr-4.2.2.tar.xz

From ad9bfd4243b290036771f68da4ddf384a7298588 Mon Sep 17 00:00:00 2001
From: Elyes Haouas <ehaouas@noos.fr>
Date: Sat, 28 Jun 2025 11:26:12 +0200
Subject: [PATCH 1445/3886] crossgcc: Always update HOSTCFLAGS from GMP headers
 if already built

Change-Id: I332cdec6d56cf09b0380dbf43575ed2d5d45461a
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88232
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
---
 util/crossgcc/buildgcc | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc
index c961947d9b..b76bcff693 100755
--- a/util/crossgcc/buildgcc
+++ b/util/crossgcc/buildgcc
@@ -512,6 +512,10 @@ generic_build()
 
 	mkdir -p "$builddir"
 
+	if [ "$package" = "GMP" ] && [ -f "$DESTDIR$TARGETDIR/include/gmp.h" ]; then
+		set_hostcflags_from_gmp
+	fi
+
 	if [ -f "$success" ]; then
 		printf "Skipping $package v$version for $host_target as it is already built\n"
 	else

From 07a8737cbd687dc90f961a41271c008a49a52379 Mon Sep 17 00:00:00 2001
From: Elyes Haouas <ehaouas@noos.fr>
Date: Sat, 28 Jun 2025 11:28:49 +0200
Subject: [PATCH 1446/3886] crossgcc:Initialize OPT_LDFLAGS to avoid unset
 variable in IASL build

Change-Id: Ibdad41baee8bb245112160be237f1081fbfc89c8
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88233
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
---
 util/crossgcc/buildgcc | 1 +
 1 file changed, 1 insertion(+)

diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc
index b76bcff693..b1609f11e4 100755
--- a/util/crossgcc/buildgcc
+++ b/util/crossgcc/buildgcc
@@ -897,6 +897,7 @@ build_IASL() {
 	RDIR=$PWD
 	cd ../$IASL_DIR/generate/unix || exit 1
 	CFLAGS="$HOSTCFLAGS"
+	OPT_LDFLAGS=""
 	HOST="_LINUX"
 	test "$UNAME" = "Darwin" && HOST="_APPLE" && OPT_LDFLAGS="-Wl,-no_fixup_chains"
 	test "$UNAME" = "FreeBSD" && HOST="_FreeBSD"

From f2fed71533216458dd0c32acf5a7fc7b133185d5 Mon Sep 17 00:00:00 2001
From: Elyes Haouas <ehaouas@noos.fr>
Date: Sun, 29 Jun 2025 14:38:50 +0200
Subject: [PATCH 1447/3886] crossgcc: Upgrade acpica from 20241212 to 20250404

Change-Id: Iddd9c6f3510e80ee3ae39d86a10cd23e77dc0a05
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87342
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
---
 util/crossgcc/buildgcc                                          | 2 +-
 ...unix-20241212_iasl.patch => acpica-unix-20250404_iasl.patch} | 0
 util/crossgcc/sum/acpica-unix-20241212.tar.gz.cksum             | 1 -
 util/crossgcc/sum/acpica-unix-20250404.tar.gz.cksum             | 1 +
 4 files changed, 2 insertions(+), 2 deletions(-)
 rename util/crossgcc/patches/{acpica-unix-20241212_iasl.patch => acpica-unix-20250404_iasl.patch} (100%)
 delete mode 100644 util/crossgcc/sum/acpica-unix-20241212.tar.gz.cksum
 create mode 100644 util/crossgcc/sum/acpica-unix-20250404.tar.gz.cksum

diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc
index b1609f11e4..b5c8beeff2 100755
--- a/util/crossgcc/buildgcc
+++ b/util/crossgcc/buildgcc
@@ -46,7 +46,7 @@ LIBSTDCXX_VERSION="${GCC_VERSION}"	# GCC-specific C++ library
 
 # Low-level Tools (built after GCC)
 NASM_VERSION=2.16.03	# x86 assembly
-IASL_VERSION=20241212	# ACPI compiler
+IASL_VERSION=20250404	# ACPI compiler
 
 # Clang/LLVM Toolchain (alternative to GCC, built separately)
 CLANG_VERSION=18.1.8
diff --git a/util/crossgcc/patches/acpica-unix-20241212_iasl.patch b/util/crossgcc/patches/acpica-unix-20250404_iasl.patch
similarity index 100%
rename from util/crossgcc/patches/acpica-unix-20241212_iasl.patch
rename to util/crossgcc/patches/acpica-unix-20250404_iasl.patch
diff --git a/util/crossgcc/sum/acpica-unix-20241212.tar.gz.cksum b/util/crossgcc/sum/acpica-unix-20241212.tar.gz.cksum
deleted file mode 100644
index 6e69219baa..0000000000
--- a/util/crossgcc/sum/acpica-unix-20241212.tar.gz.cksum
+++ /dev/null
@@ -1 +0,0 @@
-7f30cb188e46567527bc733c169ed2b4e18b825f  tarballs/acpica-unix-20241212.tar.gz
diff --git a/util/crossgcc/sum/acpica-unix-20250404.tar.gz.cksum b/util/crossgcc/sum/acpica-unix-20250404.tar.gz.cksum
new file mode 100644
index 0000000000..83d38deb24
--- /dev/null
+++ b/util/crossgcc/sum/acpica-unix-20250404.tar.gz.cksum
@@ -0,0 +1 @@
+aeff4d1254e73263b4f2c6f7d1e96af47fa219e0  tarballs/acpica-unix-20250404.tar.gz

From b0e0c688c8a116afe0729c4cce3f615ae79fe36a Mon Sep 17 00:00:00 2001
From: Elyes Haouas <ehaouas@noos.fr>
Date: Sat, 28 Jun 2025 11:18:37 +0200
Subject: [PATCH 1448/3886] buildgcc: Use -d to check libstdc++ include
 directory

Change-Id: I3d8519557d99f6cb910e721643c1b4b2eab6bb05
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88231
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
---
 util/crossgcc/buildgcc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc
index b5c8beeff2..d72ac54c88 100755
--- a/util/crossgcc/buildgcc
+++ b/util/crossgcc/buildgcc
@@ -868,7 +868,7 @@ build_cross_GCC() {
 }
 
 build_LIBSTDCXX() {
-	if [ ! -e "${LIBSTDCXX_INCLUDE_PATH}" ]; then
+	if [ ! -d "${LIBSTDCXX_INCLUDE_PATH}" ]; then
 		touch .failed
 		printf "libstdcxx include path \"%s\" does not exist" "${LIBSTDCXX_INCLUDE_PATH}"
 		return

From f1aa0a175b146f9f1bae8d1d4638a312d8f6acb2 Mon Sep 17 00:00:00 2001
From: Elyes Haouas <ehaouas@noos.fr>
Date: Tue, 29 Oct 2024 09:28:31 +0100
Subject: [PATCH 1449/3886] util/crossgcc: Build compiler-rt using runtimes

compiler-rt is not a variable used by the LLVM_ENABLE_PROJECTS config,
but has a separate configuration option.

Change-Id: Iacd9b5f1fc1444b3dd1a785b91510f346e7a2f51
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80737
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 util/crossgcc/buildgcc                            | 15 ++++++++++-----
 .../crossgcc/sum/runtimes-18.1.8.src.tar.xz.cksum |  1 +
 2 files changed, 11 insertions(+), 5 deletions(-)
 create mode 100644 util/crossgcc/sum/runtimes-18.1.8.src.tar.xz.cksum

diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc
index d72ac54c88..a4a998536b 100755
--- a/util/crossgcc/buildgcc
+++ b/util/crossgcc/buildgcc
@@ -71,6 +71,7 @@ CRT_ARCHIVE="compiler-rt-${CLANG_VERSION}.src.tar.xz"
 CTE_ARCHIVE="clang-tools-extra-${CLANG_VERSION}.src.tar.xz"
 LLVMCMAKE_ARCHIVE="cmake-${CLANG_VERSION}.src.tar.xz"
 LIBUNWIND_ARCHIVE="libunwind-${CLANG_VERSION}.src.tar.xz"
+RUNTIMES_ARCHIVE="runtimes-${CLANG_VERSION}.src.tar.xz"
 CMAKE_ARCHIVE="cmake-${CMAKE_VERSION}.tar.gz"
 NASM_ARCHIVE="nasm-${NASM_VERSION}.tar.bz2"
 
@@ -94,6 +95,7 @@ CTE_BASE_URL="https://github.com/llvm/llvm-project/releases/download/llvmorg-${C
 LLVMCMAKE_BASE_URL="https://github.com/llvm/llvm-project/releases/download/llvmorg-${CLANG_VERSION}"
 LLD_BASE_URL="https://github.com/llvm/llvm-project/releases/download/llvmorg-${CLANG_VERSION}"
 LIBUNWIND_BASE_URL="https://github.com/llvm/llvm-project/releases/download/llvmorg-${CLANG_VERSION}"
+RUNTIMES_BASE_URL="https://github.com/llvm/llvm-project/releases/download/llvmorg-${CLANG_VERSION}"
 CMAKE_BASE_URL="https://cmake.org/files/v${CMAKE_VERSION%.*}"
 NASM_BASE_URL="https://www.nasm.us/pub/nasm/releasebuilds/${NASM_VERSION}"
 
@@ -101,8 +103,8 @@ ALL_ARCHIVES="$GMP_BASE_URL/$GMP_ARCHIVE $MPFR_BASE_URL/$MPFR_ARCHIVE $MPC_BASE_
 	$GCC_BASE_URL/$GCC_ARCHIVE $BINUTILS_BASE_URL/$BINUTILS_ARCHIVE $IASL_BASE_URL/$IASL_ARCHIVE \
 	$LLD_BASE_URL/$LLD_ARCHIVE $LLVM_BASE_URL/$LLVM_ARCHIVE $CLANG_BASE_URL/$CLANG_ARCHIVE \
 	$LLVMCMAKE_BASE_URL/$LLVMCMAKE_ARCHIVE $CRT_BASE_URL/$CRT_ARCHIVE $CTE_BASE_URL/$CTE_ARCHIVE \
-	$LIBUNWIND_BASE_URL/$LIBUNWIND_ARCHIVE $CMAKE_BASE_URL/$CMAKE_ARCHIVE $NASM_BASE_URL/$NASM_ARCHIVE \
-	$LIBSTDCXX_BASE_URL/$LIBSTDCXX_ARCHIVE"
+	$LIBUNWIND_BASE_URL/$LIBUNWIND_ARCHIVE $RUNTIMES_BASE_URL/$RUNTIMES_ARCHIVE \
+	$CMAKE_BASE_URL/$CMAKE_ARCHIVE $NASM_BASE_URL/$NASM_ARCHIVE $LIBSTDCXX_BASE_URL/$LIBSTDCXX_ARCHIVE"
 
 # GCC toolchain directories
 GMP_DIR="gmp-${GMP_VERSION}"
@@ -122,6 +124,7 @@ CRT_DIR="compiler-rt-${CLANG_VERSION}.src"
 CTE_DIR="clang-tools-extra-${CLANG_VERSION}.src"
 LLVMCMAKE_DIR="cmake-${CLANG_VERSION}.src"
 LIBUNWIND_DIR="libunwind-${CLANG_VERSION}.src"
+RUNTIMES_DIR="runtimes-${CLANG_VERSION}.src"
 CMAKE_DIR="cmake-${CMAKE_VERSION}"
 NASM_DIR="nasm-${NASM_VERSION}"
 
@@ -920,22 +923,24 @@ build_LLVM() {
 	ln -nsf "$CRT_DIR" ../compiler-rt
 	ln -nsf "$LLVMCMAKE_DIR" ../cmake
 	ln -nsf "$LIBUNWIND_DIR" ../libunwind
+	ln -nsf "$RUNTIMES_DIR" ../runtimes
 
 	$CMAKE -G "Unix Makefiles" \
 		-DCMAKE_INSTALL_PREFIX="$DESTDIR$TARGETDIR" \
 		-DCLANG_VENDOR="coreboot toolchain v$CROSSGCC_VERSION - " \
-		-DLLVM_ENABLE_PROJECTS="clang;clang-tools-extra;compiler-rt;lld" \
+		-DLLVM_ENABLE_PROJECTS="clang;clang-tools-extra;lld" \
 		-DLLVM_INCLUDE_BENCHMARKS="OFF" \
 		-DLLVM_INCLUDE_TESTS="OFF" \
 		-DLLVM_INCLUDE_EXAMPLES="OFF" \
 		-DCMAKE_BUILD_TYPE=Release \
 		-DLLVM_TARGETS_TO_BUILD="AArch64;ARM;PowerPC;RISCV;X86" \
+		-DLLVM_ENABLE_RUNTIMES="compiler-rt" \
 		../llvm || touch .failed
 	# shellcheck disable=SC2086
 	$MAKE $JOBS || touch .failed
 	$MAKE install || touch .failed
 
-	rm -f ../llvm ../clang ../clang-tools-extra ../compiler-rt ../cmake ../lld ../libunwind
+	rm -f ../llvm ../clang ../clang-tools-extra ../compiler-rt ../cmake ../lld ../libunwind ../runtimes
 
 	cp -a ../$CLANG_DIR/tools/scan-build/* "$DESTDIR$TARGETDIR/bin"
 	cp -a ../$CLANG_DIR/tools/scan-view/* "$DESTDIR$TARGETDIR/bin"
@@ -1078,7 +1083,7 @@ case "$PACKAGE" in
 	CLANG|clang)
 		NAME="LLVM clang"
 		LLVM_VERSION=${CLANG_VERSION}
-		PACKAGES="CMAKE LLVM CLANG CRT CTE LLVMCMAKE LLD LIBUNWIND"
+		PACKAGES="CMAKE LLVM CLANG CRT CTE LLVMCMAKE LLD LIBUNWIND RUNTIMES"
 		CMAKE=${DESTDIR}${TARGETDIR}/bin/cmake
 		;;
 	IASL|iasl)
diff --git a/util/crossgcc/sum/runtimes-18.1.8.src.tar.xz.cksum b/util/crossgcc/sum/runtimes-18.1.8.src.tar.xz.cksum
new file mode 100644
index 0000000000..fbee9941d1
--- /dev/null
+++ b/util/crossgcc/sum/runtimes-18.1.8.src.tar.xz.cksum
@@ -0,0 +1 @@
+4a5ea2f22b2d81467e739f4b070cf7ff52785856  tarballs/runtimes-18.1.8.src.tar.xz

From 6707e9281cf8c7e36be5b4d5a230f5619d3e1c4f Mon Sep 17 00:00:00 2001
From: Elmo Lan <elmo_lan@realtek.corp-partner.google.com>
Date: Fri, 27 Jun 2025 20:28:30 +0800
Subject: [PATCH 1450/3886] mb/google/brox: Update cpu power limits

brox_rtk_ec share the same power design with brox,
so follow brox set as 9W.

BUG=b:414474440
TEST=system can boot when AC only.

Change-Id: Ia05b331f229127b898f4549d5ba1ac2771ac8b7b
Signed-off-by: Elmo Lan <elmo_lan@realtek.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88213
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Keith Short <keithshort@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
---
 src/mainboard/google/brox/Kconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/src/mainboard/google/brox/Kconfig b/src/mainboard/google/brox/Kconfig
index a94995a168..9a22731a94 100644
--- a/src/mainboard/google/brox/Kconfig
+++ b/src/mainboard/google/brox/Kconfig
@@ -124,6 +124,7 @@ config DRIVER_TPM_I2C_BUS
 config PL4_LIMIT_FOR_CRITICAL_BAT_BOOT
 	int
 	default 9 if BOARD_GOOGLE_BROX
+	default 9 if BOARD_GOOGLE_BROX_RTK_EC
 	default 14 if BOARD_GOOGLE_JUBILANT
 	default 40 if BOARD_GOOGLE_LOTSO
 	help

From ef10e93e0afd6d584d1307b607a4e767fdc05cbb Mon Sep 17 00:00:00 2001
From: Elyes Haouas <ehaouas@noos.fr>
Date: Sun, 1 Jun 2025 15:54:13 +0200
Subject: [PATCH 1451/3886] tree: Replace scan-build by clang-tidy

Change-Id: I0e59a1667759723bbf8d76232e7e5375837d2e9a
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87908
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
---
 Makefile.mk                  |  4 +-
 payloads/libpayload/Makefile | 25 +++++-------
 src/arch/riscv/Makefile.mk   |  2 +-
 toolchain.mk                 | 10 ++---
 util/abuild/abuild           | 78 +++++++++++++++++++++++-------------
 util/cbfstool/lz4/Makefile   |  2 +-
 util/crossgcc/buildgcc       |  3 --
 util/testing/Makefile.mk     |  6 +--
 8 files changed, 71 insertions(+), 59 deletions(-)

diff --git a/Makefile.mk b/Makefile.mk
index 3969bfbd05..218e388bb5 100644
--- a/Makefile.mk
+++ b/Makefile.mk
@@ -532,8 +532,8 @@ CFLAGS_common += -Wstring-compare
 ifeq ($(CONFIG_COMPILER_GCC),y)
 CFLAGS_common += -Wold-style-declaration
 CFLAGS_common += -Wcast-function-type
-# Don't add these GCC specific flags when running scan-build
-ifeq ($(CCC_ANALYZER_OUTPUT_FORMAT),)
+# Don't add these GCC specific flags when running clang-tidy
+ifeq ($(CLANG_TIDY),)
 CFLAGS_common += -Wno-packed-not-aligned
 CFLAGS_common += -fconserve-stack
 CFLAGS_common += -Wnull-dereference
diff --git a/payloads/libpayload/Makefile b/payloads/libpayload/Makefile
index afe38dc6e7..a8c2641dc6 100644
--- a/payloads/libpayload/Makefile
+++ b/payloads/libpayload/Makefile
@@ -33,7 +33,7 @@ ifneq ($(words $(CURDIR)),1)
 	$(error ERROR: Path to the main directory cannot contain spaces)
 endif
 
-ifeq ($(INNER_SCANBUILD),y)
+ifeq ($(INNER_STATIC_ANALYSIS),y)
 CC_real:=$(CC)
 endif
 
@@ -95,7 +95,7 @@ DOXYGEN_OUTPUT_DIR := doxygen
 
 all: real-all
 
-ifeq ($(INNER_SCANBUILD),y)
+ifeq ($(INNER_STATIC_ANALYSIS),y)
 CC:=$(CC_real)
 HOSTCC:=$(CC_real) --hostcc
 HOSTCXX:=$(CC_real) --hostcxx
@@ -218,7 +218,6 @@ endif
 
 CFLAGS += -std=gnu11 $(CFLAGS_$(ARCH-y))
 
-ifneq ($(INNER_SCANBUILD),y)
 ifeq ($(CONFIG_LP_COMPILER_LLVM_CLANG),y)
 CC:=clang
 ifneq ($(CONFIG_LP_ARCH_MOCK),y)
@@ -226,7 +225,6 @@ CC += -m32
 endif
 HOSTCC:=clang
 endif
-endif
 
 ifeq ($(CONFIG_LP_CCACHE),y)
 CCACHE:=$(word 1,$(wildcard $(addsuffix /ccache,$(subst :, ,$(PATH)))))
@@ -244,22 +242,17 @@ strip_quotes = $(subst ",,$(subst \",,$(1)))
 # The primary target needs to be here before we include the
 # other files
 
-ifeq ($(INNER_SCANBUILD),y)
-CONFIG_LP_SCANBUILD_ENABLE:=
+ifeq ($(INNER_STATIC_ANALYSIS),y)
+CONFIG_LP_STATIC_ANALYSIS__ENABLE:=
 endif
 
-ifeq ($(CONFIG_LP_SCANBUILD_ENABLE),y)
-ifneq ($(CONFIG_LP_SCANBUILD_REPORT_LOCATION),)
-CONFIG_LP_SCANBUILD_REPORT_LOCATION:=-o $(CONFIG_LP_SCANBUILD_REPORT_LOCATION)
+ifeq ($(CONFIG_LP_STATIC_ANALYSIS_ENABLE),y)
+ifneq ($(CONFIG_LP_STATIC_ANALYSIS_REPORT_LOCATION),)
+CONFIG_LP_STATIC_ANALYSIS_LOCATION:=-o $(CONFIG_LP_STATIC_ANALYSIS_REPORT_LOCATION)
 endif
 real-all:
-	echo '#!/bin/sh' > .ccwrap
-	echo 'CC="$(CC)"' >> .ccwrap
-	echo 'if [ "$$1" = "--hostcc" ]; then shift; CC="$(HOSTCC)"; fi' >> .ccwrap
-	echo 'if [ "$$1" = "--hostcxx" ]; then shift; CC="$(HOSTCXX)"; fi' >> .ccwrap
-	echo 'eval $$CC $$*' >> .ccwrap
-	chmod +x .ccwrap
-	scan-build $(CONFIG_LP_SCANBUILD_REPORT_LOCATION) -analyze-headers --use-cc=$(top)/.ccwrap --use-c++=$(top)/.ccwrap $(MAKE) INNER_SCANBUILD=y
+	find src -name '*.c' -o -name '*.h' | xargs clang-tidy $(CONFIG_LP_CLANG_TIDY_CHECKS)
+	$(MAKE) INNER_STATIC_ANALYSIS=y
 else
 real-all: real-target
 endif
diff --git a/src/arch/riscv/Makefile.mk b/src/arch/riscv/Makefile.mk
index 3efd8959cc..95e439d5a9 100644
--- a/src/arch/riscv/Makefile.mk
+++ b/src/arch/riscv/Makefile.mk
@@ -31,7 +31,7 @@ else
 MARCH_SUFFIX=
 endif
 
-ifeq ($(CCC_ANALYZER_OUTPUT_FORMAT),)
+ifeq ($(CLANG_TIDY),)
 riscv_flags += -march=$(CONFIG_RISCV_ARCH)$(MARCH_SUFFIX) -mabi=$(CONFIG_RISCV_ABI) -mcmodel=$(CONFIG_RISCV_CODEMODEL)
 simple_riscv_flags += -march=$(CONFIG_RISCV_ARCH) -mabi=$(CONFIG_RISCV_ABI) -mcmodel=$(CONFIG_RISCV_CODEMODEL)
 else
diff --git a/toolchain.mk b/toolchain.mk
index 8d6d4496a2..dada31daf4 100644
--- a/toolchain.mk
+++ b/toolchain.mk
@@ -19,12 +19,10 @@ HOSTCC:=$(CCACHE) $(HOSTCC)
 HOSTCXX:=$(CCACHE) $(HOSTCXX)
 endif
 
-# scan-build integration
-ifneq ($(CCC_ANALYZER_OUTPUT_FORMAT),)
-
-ifeq ($(CCC_ANALYZER_ANALYSIS),)
-export CCC_ANALYZER_ANALYSIS := -analyzer-opt-analyze-headers
-endif
+# clang-tidy integration
+ifneq ($(CLANG_TIDY),)
+CLANG_TIDY_CHECKS ?= -checks=*
+CLANG_TIDY_ARGS ?= -extra-arg=-Wno-packed-not-aligned
 
 $(foreach arch,$(ARCH_SUPPORTED), \
 	$(eval CC_$(arch):=CCC_CC="$(CC_$(arch))" $(CC) ))
diff --git a/util/abuild/abuild b/util/abuild/abuild
index faac3eb347..8483942aed 100755
--- a/util/abuild/abuild
+++ b/util/abuild/abuild
@@ -85,8 +85,8 @@ mode=text
 # quiet mode: only print pass, failure, and 'skipped' messages
 quiet=false
 
-# clang mode enabled by -sb option.
-scanbuild=false
+# clang-tidy mode enabled by -sb option.
+clangtidy=false
 
 # Mark whether abuild was called recursively
 recursive=false
@@ -417,6 +417,35 @@ ts_delta_string()
 	fi
 }
 
+run_clang_tidy()
+{
+	local build_dir="$1"
+	local log_file="$2"
+	local clang_tidy_args=""
+
+	if [[ -n "${CLANG_TIDY_CHECKS}" ]]; then
+		clang_tidy_args+="-checks=${CLANG_TIDY_CHECKS} "
+	fi
+
+	# Generate compilation database
+	printf "Generating compilation database for clang-tidy...\n"
+	${MAKE} -C "${ROOT}" DOTCONFIG="${build_dir}/config.build" obj="${build_dir}" \
+		objutil="${TARGET}/sharedutils" BUILD_TIMELESS=${TIMELESS} \
+		compiledb >/dev/null 2>&1
+
+	if [[ ! -f "${build_dir}/compile_commands.json" ]]; then
+		printf "Error: Failed to generate compilation database\n" >> "${log_file}"
+		return 1
+	fi
+
+	# Run clang-tidy on all source files
+	find "${ROOT}/src" -type f \( -name "*.c" -o -name "*.h" \) | while read -r src_file; do
+		clang-tidy ${clang_tidy_args} "${src_file}" >> "${log_file}" 2>&1
+	done
+
+	return 0
+}
+
 compile_target()
 {
 	local BUILD_NAME=$1
@@ -453,6 +482,17 @@ compile_target()
 		printf "ok\n" > compile.status
 		printf "%s built successfully. (took %s)\n" "${BUILD_NAME}" "${duration_str}"
 		echo "${BUILD_NAME}" >> "${PASSED_BOARDS}"
+
+		# Run clang-tidy after successful build
+		if [[ "${clangtidy}" = "true" ]]; then
+			printf "Running clang-tidy for %s...\n" "${BUILD_NAME}"
+			run_clang_tidy "${build_dir}" "${build_dir}/clang-tidy.log"
+			if [[ $? -eq 0 ]]; then
+				printf "clang-tidy completed for %s\n" "${BUILD_NAME}"
+			else
+				printf "clang-tidy failed for %s (see %s/clang-tidy.log)\n" "${BUILD_NAME}" "${build_dir}"
+			fi
+		fi
 	else
 		junit "<failure type='BuildFailed'>"
 		junitfile make.log
@@ -606,16 +646,10 @@ EOF
 
 	if [[ ${BUILDENV_CREATED} -eq 0 ]] && [[ ${configureonly} -eq 0 ]]; then
 		BUILDPREFIX=
-		if [[ "${scanbuild}" = "true" ]]; then
-			scanbuild_out="${TARGET}/${BUILD_NAME}-scanbuild"
-			rm -rf "${scanbuild_out}"
-			BUILDPREFIX="scan-build ${SCANBUILD_ARGS} -o ${scanbuild_out}tmp"
+		if [[ "${clangtidy}" = "true" ]]; then
+			printf "Enabling clang-tidy for static analysis\n"
 		fi
 		compile_target "${BUILD_NAME}"
-		if [[ "${scanbuild}" = "true" ]]; then
-			mv "${scanbuild_out}tmp"/* "${scanbuild_out}"
-			rmdir "${scanbuild_out}tmp"
-		fi
 	fi
 
 	junit "</testcase>"
@@ -720,7 +754,7 @@ Options:\n
     [-r|--remove]                 Remove output dir after build
     [-R|--root <path>]            Absolute path to coreboot sources
                                   (defaults to ${ROOT})
-    [--scan-build]                Use clang's static analyzer
+    [--static-analysis]            Run clang-tidy for static code analysis
     [--skip_set <value>]          Skip building boards with this Kconfig set
     [--skip_unset <value>]        Skip building boards with this Kconfig not set
     [--timeless]                  Generate timeless builds
@@ -780,7 +814,7 @@ getoptbrand="$(getopt -V)"
 # shellcheck disable=SC2086
 if [[ "${getoptbrand:0:6}" == "getopt" ]]; then
 	# Detected GNU getopt that supports long options.
-	args=$(getopt -l version,verbose,quiet,help,all,target:,board-variant:,payloads:,cpus:,silent,junit,config,loglevel:,remove,prefix:,update,scan-build,ccache,blobs,clang,any-toolchain,clean,clean-somewhat,outdir:,chromeos,xmlfile:,kconfig:,dir:,root:,recursive,checksum:,timeless,exitcode,asserts,name:,skip_set:,skip_unset: -o Vvqhat:b:p:c:sJCl:rP:uyBLAzZo:xX:K:d:R:Ien: -- "$@") || exit 1
+	args=$(getopt -l version,verbose,quiet,help,all,target:,board-variant:,payloads:,cpus:,silent,junit,config,loglevel:,remove,prefix:,update,static-analysis,ccache,blobs,clang,any-toolchain,clean,clean-somewhat,outdir:,chromeos,xmlfile:,kconfig:,dir:,root:,recursive,checksum:,timeless,exitcode,asserts,name:,skip_set:,skip_unset: -o Vvqhat:b:p:c:sJCl:rP:uyBLAzZo:xX:K:d:R:Ien: -- "$@") || exit 1
 	eval set -- ${args}
 	retval=$?
 else
@@ -828,10 +862,9 @@ while true ; do
 			shift;;
 		# obsolete option
 		-s|--silent)    shift;;
-		--scan-build)   shift
-			scanbuild=true
-			customizing="${customizing}, scan-build"
-			SCANBUILD_ARGS=${SCANBUILD_ARGS:-'-k'}
+		--static-analysis)   shift
+			clangtidy=true
+			customizing="${customizing}, static-analysis"
 			configoptions="${configoptions}CONFIG_FATAL_ASSERTS=y\n"
 			;;
 		--skip_set)	shift
@@ -1008,17 +1041,12 @@ build_targets()
 	printf "%s" "${configoptions}" > "${TMPCFG}"
 	${MAKE} -j "${cpus}" DOTCONFIG="${TMPCFG}" obj="${TARGET}/temp" objutil="${TARGET}/sharedutils" olddefconfig 2>/dev/null
 	BUILDPREFIX=
-	if [[ "${scanbuild}" = "true" ]]; then
-		scanbuild_out="${TARGET}/sharedutils-scanbuild"
-		rm -rf "${scanbuild_out}"
-		BUILDPREFIX="scan-build -o ${scanbuild_out}tmp"
-	fi
 	mkdir -p "${TARGET}/abuild"
 	ABSPATH="$(cd "${TARGET}/abuild" && pwd)"
 	XMLFILE="${ABSPATH}/__util.xml"
 	rm -f "${XMLFILE}"
 	stime=$(add_timestamp)
-	${BUILDPREFIX} "${MAKE}" -j "${cpus}" DOTCONFIG="${TMPCFG}" obj="${TARGET}/temp" objutil="${TARGET}/sharedutils" tools > "${TARGET}/sharedutils/make.log" 2>&1
+	${MAKE} -j "${cpus}" DOTCONFIG="${TMPCFG}" obj="${TARGET}/temp" objutil="${TARGET}/sharedutils" tools > "${TARGET}/sharedutils/make.log" 2>&1
 	local ret=$?
 	etime=$(add_timestamp)
 	duration=$(ts_delta_seconds "${stime}" "${etime}")
@@ -1039,10 +1067,6 @@ build_targets()
 		return
 	fi
 
-	if [[ "${scanbuild}" = "true" ]]; then
-		mv "${scanbuild_out}"tmp/* "${scanbuild_out}"
-		rmdir "${scanbuild_out}tmp"
-	fi
 	rm -rf "${TARGET}/temp" "${TMPCFG}"
 	num_targets=$(wc -w <<<"${targets}")
 	cpus_per_target=$(((${cpus:-1} + num_targets - 1) / num_targets))
@@ -1106,4 +1130,4 @@ if [[ "${recursive}" = "false" ]]; then
 	fi
 fi
 
-exit ${failed}
+exit ${failed}
\ No newline at end of file
diff --git a/util/cbfstool/lz4/Makefile b/util/cbfstool/lz4/Makefile
index 4506267ebf..d624e84703 100644
--- a/util/cbfstool/lz4/Makefile
+++ b/util/cbfstool/lz4/Makefile
@@ -81,7 +81,7 @@ sanitize: clean
 	CFLAGS="-O3 -g -fsanitize=undefined" $(MAKE) test CC=clang FUZZER_TIME="-T1mn" NB_LOOPS=-i1
 
 staticAnalyze: clean
-	CFLAGS=-g scan-build --status-bugs -v $(MAKE) all
+	CFLAGS=-g clang-tidy $(CLANG_TIDY_CHECKS) $(CLANG_TIDY_ARGS) $(SRCS)
 
 armtest: clean
 	CFLAGS="-O3 -Werror" $(MAKE) -C $(LZ4DIR) all CC=arm-linux-gnueabi-gcc
diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc
index a4a998536b..80b333569a 100755
--- a/util/crossgcc/buildgcc
+++ b/util/crossgcc/buildgcc
@@ -941,9 +941,6 @@ build_LLVM() {
 	$MAKE install || touch .failed
 
 	rm -f ../llvm ../clang ../clang-tools-extra ../compiler-rt ../cmake ../lld ../libunwind ../runtimes
-
-	cp -a ../$CLANG_DIR/tools/scan-build/* "$DESTDIR$TARGETDIR/bin"
-	cp -a ../$CLANG_DIR/tools/scan-view/* "$DESTDIR$TARGETDIR/bin"
 }
 
 build_CMAKE() {
diff --git a/util/testing/Makefile.mk b/util/testing/Makefile.mk
index c73502e9bc..58ceca6a00 100644
--- a/util/testing/Makefile.mk
+++ b/util/testing/Makefile.mk
@@ -116,8 +116,8 @@ test-lint:
 	util/lint/lint lint-extended $(JUNIT)
 
 test-abuild:
-ifneq ($(JENKINS_SKIP_SCANBUILD_TEST),y)
-	NAME=scanbuild; SCANBUILD_ARGS='-k -plist-html -maxloop 10' util/abuild/abuild -o $(COREBOOT_BUILD_DIR)/$${NAME} $(ABUILD_OPTIONS) --scan-build --target EMULATION_QEMU_X86_Q35 --exitcode --name $${NAME}
+ifneq ($(JENKINS_SKIP_STATIC_ANALYSIS_TEST),y)
+	NAME=clangtidy; util/abuild/abuild -o $(COREBOOT_BUILD_DIR)/$${NAME} $(ABUILD_OPTIONS) --static-analysis --target EMULATION_QEMU_X86_Q35
 endif
 ifneq ($(JENKINS_SKIP_GCC_TESTS),y)
 ifneq ($(JENKINS_SKIP_ALLTHREAD_TEST),y)
@@ -172,7 +172,7 @@ test-tools:
 test-cleanup:
 	rm -rf $(COREBOOT_BUILD_DIR)/chromeos $(COREBOOT_BUILD_DIR)/default
 	rm -rf $(COREBOOT_BUILD_DIR)/chromeos-clang $(COREBOOT_BUILD_DIR)/default-clang
-	rm -rf $(COREBOOT_BUILD_DIR)/scanbuild
+	rm -rf $(COREBOOT_BUILD_DIR)/clangtidy
 	$(MAKE) clean
 	$(foreach tool, $(TOOLLIST), $(MAKE) -C util/$(tool) clean ; )
 	$(MAKE) -C src/soc/nvidia/tegra124/lp0 clean

From f3bd8b7a077cedc1e1622a022d1f8183b5d6e2c5 Mon Sep 17 00:00:00 2001
From: Vince Liu <vince-wl.liu@mediatek.corp-partner.google.com>
Date: Fri, 27 Jun 2025 10:46:16 +0800
Subject: [PATCH 1452/3886] soc/mediatek/pmif_spmi: Move
 pmif_spmi_force_normal_mode() to common

Move pmif_spmi_force_normal_mode() to common code for better sharing:
- Extract code from common/pmif_spmi.c to common/pmif_spmi_v1.c
- Extract code from mt8196/pmif_spmi.c to common/pmif_spmi_v2.c

BUG=b:379008996
BRANCH=none
TEST=build pass

Signed-off-by: Vince Liu <vince-wl.liu@mediatek.corp-partner.google.com>
Change-Id: I47c6260872e0922feeab6e849b0ded8d2f7f4eb5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88243
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
---
 .../mediatek/common/include/soc/pmif_spmi.h   |  2 ++
 src/soc/mediatek/common/pmif_spmi.c           | 24 --------------
 src/soc/mediatek/common/pmif_spmi_v1.c        | 29 +++++++++++++++++
 src/soc/mediatek/common/pmif_spmi_v2.c        | 31 +++++++++++++++++++
 src/soc/mediatek/mt8186/Makefile.mk           |  2 +-
 src/soc/mediatek/mt8188/Makefile.mk           |  4 +--
 src/soc/mediatek/mt8189/Makefile.mk           |  4 +--
 src/soc/mediatek/mt8192/Makefile.mk           |  2 +-
 src/soc/mediatek/mt8195/Makefile.mk           |  2 +-
 src/soc/mediatek/mt8196/Makefile.mk           |  4 +--
 src/soc/mediatek/mt8196/pmif_spmi.c           | 25 ---------------
 11 files changed, 71 insertions(+), 58 deletions(-)
 create mode 100644 src/soc/mediatek/common/pmif_spmi_v1.c
 create mode 100644 src/soc/mediatek/common/pmif_spmi_v2.c

diff --git a/src/soc/mediatek/common/include/soc/pmif_spmi.h b/src/soc/mediatek/common/include/soc/pmif_spmi.h
index 2160e9edca..cdb84c6a7c 100644
--- a/src/soc/mediatek/common/include/soc/pmif_spmi.h
+++ b/src/soc/mediatek/common/include/soc/pmif_spmi.h
@@ -96,4 +96,6 @@ int spmi_config_master(void);
 size_t spmi_dev_cnt(void);
 void pmif_spmi_iocfg(void);
 void pmif_spmi_config(struct pmif *arb);
+void pmif_spmi_force_normal_mode(struct pmif *arb);
+
 #endif /* __SOC_MEDIATEK_PMIF_SPMI_H__ */
diff --git a/src/soc/mediatek/common/pmif_spmi.c b/src/soc/mediatek/common/pmif_spmi.c
index b39103aa4a..d6318eaa8c 100644
--- a/src/soc/mediatek/common/pmif_spmi.c
+++ b/src/soc/mediatek/common/pmif_spmi.c
@@ -12,16 +12,6 @@
 DEFINE_BIT(SAMPL_CK_POL, 0)
 DEFINE_BITFIELD(SAMPL_CK_DLY, 3, 1)
 
-/* PMIF, SPI_MODE_CTRL */
-DEFINE_BIT(SPI_MODE_CTRL, 7)
-DEFINE_BIT(SRVOL_EN, 11)
-DEFINE_BIT(SPI_MODE_EXT_CMD, 12)
-DEFINE_BIT(SPI_EINT_MODE_GATING_EN, 13)
-
-/* PMIF, SLEEP_PROTECTION_CTRL */
-DEFINE_BITFIELD(SPM_SLEEP_REQ_SEL, 1, 0)
-DEFINE_BITFIELD(SCP_SLEEP_REQ_SEL, 10, 9)
-
 __weak void pmif_spmi_config(struct pmif *arb)
 {
 	/* Do nothing. */
@@ -97,20 +87,6 @@ static int spmi_mst_init(struct pmif *pmif_arb)
 	return 0;
 }
 
-static void pmif_spmi_force_normal_mode(struct pmif *arb)
-{
-	/* listen srclken_0 only for entering normal or sleep mode */
-	SET32_BITFIELDS(&arb->mtk_pmif->spi_mode_ctrl,
-			SPI_MODE_CTRL, 0,
-			SRVOL_EN, 0,
-			SPI_MODE_EXT_CMD, 1,
-			SPI_EINT_MODE_GATING_EN, 1);
-
-	/* enable spm/scp sleep request */
-	SET32_BITFIELDS(&arb->mtk_pmif->sleep_protection_ctrl, SPM_SLEEP_REQ_SEL, 0,
-			SCP_SLEEP_REQ_SEL, 0);
-}
-
 static void pmif_spmi_enable_swinf(struct pmif *arb)
 {
 	write32(&arb->mtk_pmif->inf_en, PMIF_SPMI_SW_CHAN);
diff --git a/src/soc/mediatek/common/pmif_spmi_v1.c b/src/soc/mediatek/common/pmif_spmi_v1.c
new file mode 100644
index 0000000000..2069b604fe
--- /dev/null
+++ b/src/soc/mediatek/common/pmif_spmi_v1.c
@@ -0,0 +1,29 @@
+/* SPDX-License-Identifier: GPL-2.0-only OR MIT */
+
+#include <device/mmio.h>
+#include <soc/pmif.h>
+#include <soc/pmif_spmi.h>
+
+/* PMIF, SPI_MODE_CTRL */
+DEFINE_BIT(SPI_MODE_CTRL, 7)
+DEFINE_BIT(SRVOL_EN, 11)
+DEFINE_BIT(SPI_MODE_EXT_CMD, 12)
+DEFINE_BIT(SPI_EINT_MODE_GATING_EN, 13)
+
+/* PMIF, SLEEP_PROTECTION_CTRL */
+DEFINE_BITFIELD(SPM_SLEEP_REQ_SEL, 1, 0)
+DEFINE_BITFIELD(SCP_SLEEP_REQ_SEL, 10, 9)
+
+void pmif_spmi_force_normal_mode(struct pmif *arb)
+{
+	/* listen srclken_0 only for entering normal or sleep mode */
+	SET32_BITFIELDS(&arb->mtk_pmif->spi_mode_ctrl,
+			SPI_MODE_CTRL, 0,
+			SRVOL_EN, 0,
+			SPI_MODE_EXT_CMD, 1,
+			SPI_EINT_MODE_GATING_EN, 1);
+
+	/* enable spm/scp sleep request */
+	SET32_BITFIELDS(&arb->mtk_pmif->sleep_protection_ctrl, SPM_SLEEP_REQ_SEL, 0,
+			SCP_SLEEP_REQ_SEL, 0);
+}
diff --git a/src/soc/mediatek/common/pmif_spmi_v2.c b/src/soc/mediatek/common/pmif_spmi_v2.c
new file mode 100644
index 0000000000..54ef132d33
--- /dev/null
+++ b/src/soc/mediatek/common/pmif_spmi_v2.c
@@ -0,0 +1,31 @@
+/* SPDX-License-Identifier: GPL-2.0-only OR MIT */
+
+#include <console/console.h>
+#include <device/mmio.h>
+#include <soc/pmif.h>
+#include <soc/pmif_spmi.h>
+
+/* PMIF, SPI_MODE_CTRL */
+DEFINE_BIT(VLD_SRCLK_EN_CTRL, 5)
+DEFINE_BIT(SPI_MODE_CTRL_PMIF_RDY, 9)
+DEFINE_BIT(SPI_MODE_CTRL_SRCLK_EN, 10)
+DEFINE_BIT(SPI_MODE_CTRL_SRVOL_EN, 11)
+
+/* PMIF, SLEEP_PROTECTION_CTRL */
+DEFINE_BIT(SPM_SLEEP_REQ_SEL, 0)
+DEFINE_BIT(SCP_SLEEP_REQ_SEL, 9)
+
+void pmif_spmi_force_normal_mode(struct pmif *arb)
+{
+	/* listen srclken_0 only for entering normal or sleep mode */
+	SET32_BITFIELDS(&arb->mtk_pmif->spi_mode_ctrl,
+			VLD_SRCLK_EN_CTRL, 0,
+			SPI_MODE_CTRL_PMIF_RDY, 1,
+			SPI_MODE_CTRL_SRCLK_EN, 0,
+			SPI_MODE_CTRL_SRVOL_EN, 0);
+
+	/* disable spm/scp sleep request */
+	SET32_BITFIELDS(&arb->mtk_pmif->sleep_protection_ctrl, SPM_SLEEP_REQ_SEL, 1,
+			SCP_SLEEP_REQ_SEL, 1);
+	printk(BIOS_INFO, "%s done\n", __func__);
+}
diff --git a/src/soc/mediatek/mt8186/Makefile.mk b/src/soc/mediatek/mt8186/Makefile.mk
index 4e0526c0e5..4ed3db42fc 100644
--- a/src/soc/mediatek/mt8186/Makefile.mk
+++ b/src/soc/mediatek/mt8186/Makefile.mk
@@ -30,7 +30,7 @@ romstage-y += ../common/mmu_operations.c ../common/mmu_cmops.c
 romstage-y += ../common/mt6315.c mt6315.c
 romstage-y += ../common/pmic_wrap.c pmic_wrap.c pmif.c mt6366.c
 romstage-y += ../common/pmif.c ../common/pmif_clk.c ../common/pmif_init.c pmif_clk.c
-romstage-y += ../common/pmif_spmi.c pmif_spmi.c
+romstage-y += ../common/pmif_spmi.c ../common/pmif_spmi_v1.c pmif_spmi.c
 romstage-y += ../common/rtc.c ../common/rtc_pwrap_ops.c ../common/rtc_osc_init.c rtc.c
 
 ramstage-y += adsp.c
diff --git a/src/soc/mediatek/mt8188/Makefile.mk b/src/soc/mediatek/mt8188/Makefile.mk
index 0cd05b94ce..33b41835fb 100644
--- a/src/soc/mediatek/mt8188/Makefile.mk
+++ b/src/soc/mediatek/mt8188/Makefile.mk
@@ -29,7 +29,7 @@ romstage-y += ../common/mt6315.c mt6315.c
 romstage-y += ../common/mt6359p.c mt6359p.c
 romstage-y += ../common/pmif.c ../common/pmif_clk.c ../common/pmif_init.c pmif_clk.c
 romstage-y += ../common/pmif_spi.c pmif_spi.c
-romstage-y += ../common/pmif_spmi.c pmif_spmi.c
+romstage-y += ../common/pmif_spmi.c ../common/pmif_spmi_v1.c pmif_spmi.c
 romstage-y += ../common/rtc.c ../common/rtc_osc_init.c ../common/rtc_mt6359p.c
 
 ramstage-y += ../common/auxadc.c
@@ -56,7 +56,7 @@ ramstage-y += ../common/mt6359p.c mt6359p.c
 ramstage-y += ../common/mtcmos.c mtcmos.c
 ramstage-y += ../common/pmif.c ../common/pmif_clk.c ../common/pmif_init.c pmif_clk.c
 ramstage-y += ../common/pmif_spi.c pmif_spi.c
-ramstage-y += ../common/pmif_spmi.c pmif_spmi.c
+ramstage-y += ../common/pmif_spmi.c ../common/pmif_spmi_v1.c pmif_spmi.c
 ramstage-y += ../common/rtc.c ../common/rtc_osc_init.c ../common/rtc_mt6359p.c
 ramstage-y += soc.c
 ramstage-y += ../common/spm.c ../common/spm_v1.c spm.c
diff --git a/src/soc/mediatek/mt8189/Makefile.mk b/src/soc/mediatek/mt8189/Makefile.mk
index 50c576b4f1..077ee13533 100644
--- a/src/soc/mediatek/mt8189/Makefile.mk
+++ b/src/soc/mediatek/mt8189/Makefile.mk
@@ -28,7 +28,7 @@ romstage-y += ../common/mt6315.c mt6315.c
 romstage-y += ../common/mt6359p.c mt6359p.c
 romstage-y += ../common/pmif.c ../common/pmif_clk.c ../common/pmif_init.c pmif_clk.c
 romstage-y += ../common/pmif_spi.c pmif_spi.c
-romstage-y += ../common/pmif_spmi.c pmif_spmi.c
+romstage-y += ../common/pmif_spmi.c ../common/pmif_spmi_v1.c pmif_spmi.c
 romstage-y += ../common/rtc.c ../common/rtc_osc_init.c ../common/rtc_mt6359p.c
 
 ramstage-y += ../common/auxadc.c
@@ -51,7 +51,7 @@ ramstage-y += ../common/mtcmos.c mtcmos.c
 ramstage-y += ../common/mtk_fsp.c
 ramstage-y += ../common/pmif.c ../common/pmif_clk.c ../common/pmif_init.c pmif_clk.c
 ramstage-y += ../common/pmif_spi.c pmif_spi.c
-ramstage-y += ../common/pmif_spmi.c pmif_spmi.c
+ramstage-y += ../common/pmif_spmi.c ../common/pmif_spmi_v1.c pmif_spmi.c
 ramstage-y += ../common/rtc.c ../common/rtc_mt6359p.c ../common/rtc_osc_init.c
 ramstage-y += soc.c
 ramstage-y += ../common/spm.c ../common/spm_v2.c spm.c
diff --git a/src/soc/mediatek/mt8192/Makefile.mk b/src/soc/mediatek/mt8192/Makefile.mk
index a92584da0b..7b88100478 100644
--- a/src/soc/mediatek/mt8192/Makefile.mk
+++ b/src/soc/mediatek/mt8192/Makefile.mk
@@ -27,7 +27,7 @@ romstage-y += ../common/mmu_operations.c ../common/mmu_cmops.c
 romstage-y += ../common/pll.c pll.c
 romstage-y += ../common/pmif.c ../common/pmif_clk.c ../common/pmif_init.c pmif_clk.c
 romstage-y += ../common/pmif_spi.c pmif_spi.c
-romstage-y += ../common/pmif_spmi.c pmif_spmi.c
+romstage-y += ../common/pmif_spmi.c ../common/pmif_spmi_v1.c pmif_spmi.c
 romstage-y += ../common/mt6315.c mt6315.c
 romstage-y += ../common/mt6359p.c mt6359p.c
 romstage-y += ../common/rtc.c ../common/rtc_osc_init.c ../common/rtc_mt6359p.c
diff --git a/src/soc/mediatek/mt8195/Makefile.mk b/src/soc/mediatek/mt8195/Makefile.mk
index 1f26419f02..bcbeb128db 100644
--- a/src/soc/mediatek/mt8195/Makefile.mk
+++ b/src/soc/mediatek/mt8195/Makefile.mk
@@ -31,7 +31,7 @@ romstage-y += ../common/pll.c pll.c
 romstage-y += scp.c
 romstage-y += ../common/pmif.c ../common/pmif_clk.c ../common/pmif_init.c pmif_clk.c
 romstage-y += ../common/pmif_spi.c pmif_spi.c
-romstage-y += ../common/pmif_spmi.c pmif_spmi.c
+romstage-y += ../common/pmif_spmi.c ../common/pmif_spmi_v1.c pmif_spmi.c
 romstage-y += ../common/mt6315.c mt6315.c
 romstage-y += ../common/mt6359p.c mt6359p.c
 romstage-y += mt6360.c
diff --git a/src/soc/mediatek/mt8196/Makefile.mk b/src/soc/mediatek/mt8196/Makefile.mk
index 3d8e50baa7..ea691e391b 100644
--- a/src/soc/mediatek/mt8196/Makefile.mk
+++ b/src/soc/mediatek/mt8196/Makefile.mk
@@ -49,7 +49,7 @@ romstage-y += pwrsel.c
 romstage-y += ../common/pmif_clk.c pmif_clk.c
 romstage-y += ../common/pmif.c pmif_init.c
 romstage-y += ../common/rtc.c ../common/rtc_osc_init.c
-romstage-y += pmif_spmi.c
+romstage-y += ../common/pmif_spmi_v2.c pmif_spmi.c
 romstage-y += srclken_rc.c
 romstage-y += thermal.c
 romstage-y += thermal_sram.c
@@ -85,7 +85,7 @@ ramstage-y += ../common/spm.c ../common/spm_v2.c spm.c
 ramstage-y += ../common/sspm.c ../common/sspm_sram.c
 ramstage-y += ../common/pmif_clk.c pmif_clk.c
 ramstage-y += ../common/pmif.c pmif_init.c
-ramstage-y += pmif_spmi.c
+ramstage-y += ../common/pmif_spmi_v2.c pmif_spmi.c
 ramstage-y += ../common/rtc.c ../common/rtc_osc_init.c
 ramstage-y += ../common/usb.c usb.c
 
diff --git a/src/soc/mediatek/mt8196/pmif_spmi.c b/src/soc/mediatek/mt8196/pmif_spmi.c
index 8baff6ac99..5b395e3c23 100644
--- a/src/soc/mediatek/mt8196/pmif_spmi.c
+++ b/src/soc/mediatek/mt8196/pmif_spmi.c
@@ -24,16 +24,6 @@ DEFINE_BIT(SAMPL_CK_POL, 0)
 DEFINE_BITFIELD(SAMPL_CK_DLY, 3, 1)
 DEFINE_BITFIELD(SAMPL_CK_DLY_ARB, 6, 4)
 
-/* PMIF, SPI_MODE_CTRL */
-DEFINE_BIT(VLD_SRCLK_EN_CTRL, 5)
-DEFINE_BIT(SPI_MODE_CTRL_PMIF_RDY, 9)
-DEFINE_BIT(SPI_MODE_CTRL_SRCLK_EN, 10)
-DEFINE_BIT(SPI_MODE_CTRL_SRVOL_EN, 11)
-
-/* PMIF, SLEEP_PROTECTION_CTRL */
-DEFINE_BIT(SPM_SLEEP_REQ_SEL, 0)
-DEFINE_BIT(SCP_SLEEP_REQ_SEL, 9)
-
 const struct spmi_device spmi_dev[] = {
 	{
 		.slvid = SPMI_SLAVE_4,	/* MT6363 */
@@ -264,21 +254,6 @@ static int spmi_mst_init(struct pmif *arb)
 	return 0;
 }
 
-static void pmif_spmi_force_normal_mode(struct pmif *arb)
-{
-	/* listen srclken_0 only for entering normal or sleep mode */
-	SET32_BITFIELDS(&arb->mtk_pmif->spi_mode_ctrl,
-			VLD_SRCLK_EN_CTRL, 0,
-			SPI_MODE_CTRL_PMIF_RDY, 1,
-			SPI_MODE_CTRL_SRCLK_EN, 0,
-			SPI_MODE_CTRL_SRVOL_EN, 0);
-
-	/* disable spm/scp sleep request */
-	SET32_BITFIELDS(&arb->mtk_pmif->sleep_protection_ctrl, SPM_SLEEP_REQ_SEL, 1,
-			SCP_SLEEP_REQ_SEL, 1);
-	printk(BIOS_INFO, "%s done\n", __func__);
-}
-
 static void pmif_spmi_enable_swinf(struct pmif *arb)
 {
 	write32(&arb->mtk_pmif->inf_en, PMIF_SPMI_SW_CHAN);

From 316f76635f0f216ccbf13788f1cbe1990ac3d4b5 Mon Sep 17 00:00:00 2001
From: Zhigang Qin <zhigang.qin@mediatek.corp-partner.google.com>
Date: Fri, 30 May 2025 11:27:48 +0800
Subject: [PATCH 1453/3886] soc/mediatek/mt8189: Use pmif_spmi_v2 for MT8189

MT8189 is equipped with the Power Mode Resource Collector (PMRC)
feature, and the implementation to set PMIF to normal mode is the same
as in pmif_spmi_v2. Use pmif_spmi_v2 to correct the configuration to
allow PMIF to properly enter normal mode on MT8189.

BUG=b:379008996
BRANCH=none
TEST=check the following logs for PMIC communication
[DEBUG]  pmic_efuse_setting: Set efuses in 10 msecs
[INFO ]  [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
[INFO ]  [RTC]rtc_boot,330: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
[INFO ]  [RTC]rtc_enable_dcxo,66: con=0x486, osc32con=0xfe69, sec=0x0
[INFO ]  [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
[INFO ]  [RTC]rtc_osc_init,62: osc32con val = 0xfe69
[INFO ]  [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a

Signed-off-by: Zhigang Qin <zhigang.qin@mediatek.corp-partner.google.com>
Change-Id: Ib3eeba7ca9bd446b641a17fbe97bcda373cb4a24
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88244
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
---
 src/soc/mediatek/mt8189/Makefile.mk |  4 ++--
 src/soc/mediatek/mt8189/pmif_spi.c  | 10 ++++++++++
 2 files changed, 12 insertions(+), 2 deletions(-)

diff --git a/src/soc/mediatek/mt8189/Makefile.mk b/src/soc/mediatek/mt8189/Makefile.mk
index 077ee13533..9e5124b2a4 100644
--- a/src/soc/mediatek/mt8189/Makefile.mk
+++ b/src/soc/mediatek/mt8189/Makefile.mk
@@ -28,7 +28,7 @@ romstage-y += ../common/mt6315.c mt6315.c
 romstage-y += ../common/mt6359p.c mt6359p.c
 romstage-y += ../common/pmif.c ../common/pmif_clk.c ../common/pmif_init.c pmif_clk.c
 romstage-y += ../common/pmif_spi.c pmif_spi.c
-romstage-y += ../common/pmif_spmi.c ../common/pmif_spmi_v1.c pmif_spmi.c
+romstage-y += ../common/pmif_spmi.c ../common/pmif_spmi_v2.c pmif_spmi.c
 romstage-y += ../common/rtc.c ../common/rtc_osc_init.c ../common/rtc_mt6359p.c
 
 ramstage-y += ../common/auxadc.c
@@ -51,7 +51,7 @@ ramstage-y += ../common/mtcmos.c mtcmos.c
 ramstage-y += ../common/mtk_fsp.c
 ramstage-y += ../common/pmif.c ../common/pmif_clk.c ../common/pmif_init.c pmif_clk.c
 ramstage-y += ../common/pmif_spi.c pmif_spi.c
-ramstage-y += ../common/pmif_spmi.c ../common/pmif_spmi_v1.c pmif_spmi.c
+ramstage-y += ../common/pmif_spmi.c ../common/pmif_spmi_v2.c pmif_spmi.c
 ramstage-y += ../common/rtc.c ../common/rtc_mt6359p.c ../common/rtc_osc_init.c
 ramstage-y += soc.c
 ramstage-y += ../common/spm.c ../common/spm_v2.c spm.c
diff --git a/src/soc/mediatek/mt8189/pmif_spi.c b/src/soc/mediatek/mt8189/pmif_spi.c
index 91fb74b306..68e275c22f 100644
--- a/src/soc/mediatek/mt8189/pmif_spi.c
+++ b/src/soc/mediatek/mt8189/pmif_spi.c
@@ -4,6 +4,11 @@
 #include <gpio.h>
 #include <soc/pmif_spi.h>
 
+/* PMIF, SPI_MODE_CTRL */
+DEFINE_BIT(SPI_MODE_CTRL_PMIF_RDY, 9)
+DEFINE_BIT(SPI_MODE_CTRL_SRCLK_EN, 10)
+DEFINE_BIT(SPI_MODE_CTRL_SRVOL_EN, 11)
+
 /* PMIF, SLEEP_PROTECTION_CTRL */
 DEFINE_BITFIELD(SPM_SLEEP_REQ_SEL, 1, 0)
 DEFINE_BITFIELD(SCP_SLEEP_REQ_SEL, 10, 9)
@@ -19,6 +24,11 @@ void pmif_spi_iocfg(void)
 
 void pmif_spi_setting(struct pmif *arb)
 {
+	SET32_BITFIELDS(&arb->mtk_pmif->spi_mode_ctrl,
+			SPI_MODE_CTRL_SRCLK_EN, 0,
+			SPI_MODE_CTRL_SRVOL_EN, 0,
+			SPI_MODE_CTRL_PMIF_RDY, 1);
+
 	SET32_BITFIELDS(&arb->mtk_pmif->sleep_protection_ctrl,
 			SPM_SLEEP_REQ_SEL, 1,
 			SCP_SLEEP_REQ_SEL, 1);

From 0a94fcd2db870c1b0da86190c1c6ccbd45112294 Mon Sep 17 00:00:00 2001
From: Elyes Haouas <ehaouas@noos.fr>
Date: Mon, 30 Jun 2025 17:43:44 +0200
Subject: [PATCH 1454/3886] crossgcc: upgrade binutils from version 2.43 to
 2.44

Change-Id: Ic78053f55c59de7af16fca0265d0d23fadfb20f6
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86254
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
---
 util/crossgcc/buildgcc                        |   2 +-
 .../patches/binutils-2.43.1_no-makeinfo.patch | 241 ------------------
 ...ipxe.patch => binutils-2.44_as-ipxe.patch} |  14 +-
 .../patches/binutils-2.44_no-makeinfo.patch   | 217 ++++++++++++++++
 .../crossgcc/sum/binutils-2.43.1.tar.xz.cksum |   1 -
 util/crossgcc/sum/binutils-2.44.tar.xz.cksum  |   1 +
 6 files changed, 220 insertions(+), 256 deletions(-)
 delete mode 100644 util/crossgcc/patches/binutils-2.43.1_no-makeinfo.patch
 rename util/crossgcc/patches/{binutils-2.43.1_as-ipxe.patch => binutils-2.44_as-ipxe.patch} (78%)
 create mode 100644 util/crossgcc/patches/binutils-2.44_no-makeinfo.patch
 delete mode 100644 util/crossgcc/sum/binutils-2.43.1.tar.xz.cksum
 create mode 100644 util/crossgcc/sum/binutils-2.44.tar.xz.cksum

diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc
index 80b333569a..2f513d8333 100755
--- a/util/crossgcc/buildgcc
+++ b/util/crossgcc/buildgcc
@@ -41,7 +41,7 @@ MPFR_VERSION=4.2.2
 MPC_VERSION=1.3.1
 # Core GCC components
 GCC_VERSION=14.2.0
-BINUTILS_VERSION=2.43.1
+BINUTILS_VERSION=2.44
 LIBSTDCXX_VERSION="${GCC_VERSION}"	# GCC-specific C++ library
 
 # Low-level Tools (built after GCC)
diff --git a/util/crossgcc/patches/binutils-2.43.1_no-makeinfo.patch b/util/crossgcc/patches/binutils-2.43.1_no-makeinfo.patch
deleted file mode 100644
index c43ab0e700..0000000000
--- a/util/crossgcc/patches/binutils-2.43.1_no-makeinfo.patch
+++ /dev/null
@@ -1,241 +0,0 @@
-It fails to compile when using "MAKEINFO = @MAKEINFO@":
-binutils-gdb/missing: 81: makeinfo: not found
-WARNING: 'makeinfo' is missing on your system.
-         You should only need it if you modified a '.texi' file, or
-         any other file indirectly affecting the aspect of the manual.
-         You might want to install the Texinfo package:
-         <http://www.gnu.org/software/texinfo/>
-         The spurious makeinfo call might also be the consequence of
-         using a buggy 'make' (AIX, DU, IRIX), in which case you might
-         want to install GNU make:
-         <http://www.gnu.org/software/make/>
-make[4]: *** [Makefile:507: as.info] Error 127
-Current patch will change that to "MAKEINFO = true"
-diff -ur binutils-2.41.orig/bfd/Makefile.in binutils-2.40/bfd/Makefile.in
---- binutils-2.41.orig/bfd/Makefile.in	2022-08-05 11:53:59.000000000 +0200
-+++ binutils-2.40/bfd/Makefile.in	2022-08-20 05:46:39.960039957 +0200
-@@ -379,7 +379,7 @@
- LN_S = @LN_S@
- LTLIBOBJS = @LTLIBOBJS@
- MAINT = @MAINT@
--MAKEINFO = @MAKEINFO@
-+MAKEINFO = true
- MKDIR_P = @MKDIR_P@
- MKINSTALLDIRS = @MKINSTALLDIRS@
- MSGFMT = @MSGFMT@
-diff -ur binutils-2.41.orig/binutils/Makefile.in binutils-2.40/binutils/Makefile.in
---- binutils-2.41.orig/binutils/Makefile.in	2022-08-05 11:56:21.000000000 +0200
-+++ binutils-2.40/binutils/Makefile.in	2022-08-20 05:46:38.563035937 +0200
-@@ -532,7 +532,7 @@
- LTLIBICONV = @LTLIBICONV@
- LTLIBOBJS = @LTLIBOBJS@
- MAINT = @MAINT@
--MAKEINFO = @MAKEINFO@
-+MAKEINFO = true
- MKDIR_P = @MKDIR_P@
- MKINSTALLDIRS = @MKINSTALLDIRS@
- MSGFMT = @MSGFMT@
-diff -ur binutils-2.41.orig/etc/Makefile.in binutils-2.40/etc/Makefile.in
---- binutils-2.41.orig/etc/Makefile.in	2022-07-08 11:46:47.000000000 +0200
-+++ binutils-2.40/etc/Makefile.in	2022-08-20 05:46:38.525035827 +0200
-@@ -154,7 +154,7 @@
- LIBS = @LIBS@
- LTLIBOBJS = @LTLIBOBJS@
- MAINT = @MAINT@
--MAKEINFO = @MAKEINFO@
-+MAKEINFO = true
- MKDIR_P = @MKDIR_P@
- PACKAGE = @PACKAGE@
- PACKAGE_BUGREPORT = @PACKAGE_BUGREPORT@
-diff -ur binutils-2.41.orig/gas/Makefile.in binutils-2.40/gas/Makefile.in
---- binutils-2.41.orig/gas/Makefile.in	2022-08-05 11:55:17.000000000 +0200
-+++ binutils-2.40/gas/Makefile.in	2022-08-20 05:46:38.535035856 +0200
-@@ -408,7 +408,7 @@
- LN_S = @LN_S@
- LTLIBOBJS = @LTLIBOBJS@
- MAINT = @MAINT@
--MAKEINFO = @MAKEINFO@
-+MAKEINFO = true
- MKDIR_P = @MKDIR_P@
- MKINSTALLDIRS = @MKINSTALLDIRS@
- MSGFMT = @MSGFMT@
-diff -ur binutils-2.41.orig/gold/Makefile.in binutils-2.40/gold/Makefile.in
---- binutils-2.41.orig/gold/Makefile.in	2022-07-08 11:58:08.000000000 +0200
-+++ binutils-2.40/gold/Makefile.in	2022-08-20 05:46:38.522035819 +0200
-@@ -558,7 +558,7 @@
- LN_S = @LN_S@
- LTLIBOBJS = @LTLIBOBJS@
- MAINT = @MAINT@
--MAKEINFO = @MAKEINFO@
-+MAKEINFO = true
- MERGE_CONSTANTS_FLAG = @MERGE_CONSTANTS_FLAG@
- MKDIR_P = @MKDIR_P@
- MKINSTALLDIRS = @MKINSTALLDIRS@
-diff -ur binutils-2.41.orig/gold/testsuite/Makefile.in binutils-2.40/gold/testsuite/Makefile.in
---- binutils-2.41.orig/gold/testsuite/Makefile.in	2022-07-08 11:58:08.000000000 +0200
-+++ binutils-2.40/gold/testsuite/Makefile.in	2022-08-20 05:46:38.524035824 +0200
-@@ -2644,7 +2644,7 @@
- LN_S = @LN_S@
- LTLIBOBJS = @LTLIBOBJS@
- MAINT = @MAINT@
--MAKEINFO = @MAKEINFO@
-+MAKEINFO = true
- MERGE_CONSTANTS_FLAG = @MERGE_CONSTANTS_FLAG@
- MKDIR_P = @MKDIR_P@
- MKINSTALLDIRS = @MKINSTALLDIRS@
-diff -ur binutils-2.41.orig/gprof/Makefile.in binutils-2.40/gprof/Makefile.in
---- binutils-2.41.orig/gprof/Makefile.in	2022-08-05 11:59:11.000000000 +0200
-+++ binutils-2.40/gprof/Makefile.in	2022-08-20 05:46:39.964039969 +0200
-@@ -351,7 +351,7 @@
- LN_S = @LN_S@
- LTLIBOBJS = @LTLIBOBJS@
- MAINT = @MAINT@
--MAKEINFO = @MAKEINFO@
-+MAKEINFO = true
- MKDIR_P = @MKDIR_P@
- MKINSTALLDIRS = @MKINSTALLDIRS@
- MSGFMT = @MSGFMT@
-diff -ur binutils-2.41.orig/gprofng/doc/Makefile.in binutils-2.40/gprofng/doc/Makefile.in
---- binutils-2.41.orig/gprofng/doc/Makefile.in	2022-08-05 11:59:31.000000000 +0200
-+++ binutils-2.40/gprofng/doc/Makefile.in	2022-08-20 05:46:39.252037920 +0200
-@@ -271,7 +271,7 @@
- LN_S = @LN_S@
- LTLIBOBJS = @LTLIBOBJS@
- MAINT = @MAINT@
--MAKEINFO = @MAKEINFO@
-+MAKEINFO = true
- MKDIR_P = @MKDIR_P@
- NM = @NM@
- NMEDIT = @NMEDIT@
-diff -ur binutils-2.41.orig/gprofng/gp-display-html/Makefile.in binutils-2.40/gprofng/gp-display-html/Makefile.in
---- binutils-2.41.orig/gprofng/gp-display-html/Makefile.in	2022-08-05 11:59:33.000000000 +0200
-+++ binutils-2.40/gprofng/gp-display-html/Makefile.in	2022-08-20 05:46:39.479038573 +0200
-@@ -234,7 +234,7 @@
- LN_S = @LN_S@
- LTLIBOBJS = @LTLIBOBJS@
- MAINT = @MAINT@
--MAKEINFO = @MAKEINFO@
-+MAKEINFO = true
- MKDIR_P = @MKDIR_P@
- NM = @NM@
- NMEDIT = @NMEDIT@
-diff -ur binutils-2.41.orig/gprofng/libcollector/Makefile.in binutils-2.40/gprofng/libcollector/Makefile.in
---- binutils-2.41.orig/gprofng/libcollector/Makefile.in	2022-08-05 11:59:38.000000000 +0200
-+++ binutils-2.40/gprofng/libcollector/Makefile.in	2022-08-20 05:46:38.965037094 +0200
-@@ -341,7 +341,7 @@
- LN_S = @LN_S@
- LTLIBOBJS = @LTLIBOBJS@
- MAINT = @MAINT@
--MAKEINFO = @MAKEINFO@
-+MAKEINFO = true
- MKDIR_P = @MKDIR_P@
- NM = @NM@
- NMEDIT = @NMEDIT@
-diff -ur binutils-2.41.orig/gprofng/Makefile.in binutils-2.40/gprofng/Makefile.in
---- binutils-2.41.orig/gprofng/Makefile.in	2022-08-05 11:59:30.000000000 +0200
-+++ binutils-2.40/gprofng/Makefile.in	2022-08-20 05:46:38.574035968 +0200
-@@ -289,7 +289,7 @@
- LN_S = @LN_S@
- LTLIBOBJS = @LTLIBOBJS@
- MAINT = @MAINT@
--MAKEINFO = @MAKEINFO@
-+MAKEINFO = true
- MKDIR_P = @MKDIR_P@
- NM = @NM@
- NMEDIT = @NMEDIT@
-diff -ur binutils-2.41.orig/gprofng/src/Makefile.in binutils-2.40/gprofng/src/Makefile.in
---- binutils-2.41.orig/gprofng/src/Makefile.in	2022-08-05 11:59:34.000000000 +0200
-+++ binutils-2.40/gprofng/src/Makefile.in	2022-08-20 05:46:38.573035965 +0200
-@@ -358,7 +358,7 @@
- LN_S = @LN_S@
- LTLIBOBJS = @LTLIBOBJS@
- MAINT = @MAINT@
--MAKEINFO = @MAKEINFO@
-+MAKEINFO = true
- MKDIR_P = @MKDIR_P@
- NM = @NM@
- NMEDIT = @NMEDIT@
-diff -ur binutils-2.41.orig/ld/Makefile.in binutils-2.40/ld/Makefile.in
---- binutils-2.41.orig/ld/Makefile.in	2022-08-05 11:56:53.000000000 +0200
-+++ binutils-2.40/ld/Makefile.in	2022-08-20 05:46:38.536035859 +0200
-@@ -432,7 +432,7 @@
- LN_S = @LN_S@
- LTLIBOBJS = @LTLIBOBJS@
- MAINT = @MAINT@
--MAKEINFO = @MAKEINFO@
-+MAKEINFO = true
- MKDIR_P = @MKDIR_P@
- MKINSTALLDIRS = @MKINSTALLDIRS@
- MSGFMT = @MSGFMT@
-diff -ur binutils-2.41.orig/libctf/Makefile.in binutils-2.40/libctf/Makefile.in
---- binutils-2.41.orig/libctf/Makefile.in	2022-07-08 12:02:15.000000000 +0200
-+++ binutils-2.40/libctf/Makefile.in	2022-08-20 05:46:39.771039414 +0200
-@@ -425,7 +425,7 @@
- LN_S = @LN_S@
- LTLIBOBJS = @LTLIBOBJS@
- MAINT = @MAINT@
--MAKEINFO = @MAKEINFO@
-+MAKEINFO = true
- MKDIR_P = @MKDIR_P@
- NM = @NM@
- NMEDIT = @NMEDIT@
-diff -ur binutils-2.41.orig/libiberty/Makefile.in binutils-2.40/libiberty/Makefile.in
---- binutils-2.41.orig/libiberty/Makefile.in	2022-07-08 11:46:48.000000000 +0200
-+++ binutils-2.40/libiberty/Makefile.in	2022-08-20 05:46:39.961039960 +0200
-@@ -57,7 +57,7 @@
- CFLAGS = @CFLAGS@
- CPPFLAGS = @CPPFLAGS@
- RANLIB = @RANLIB@ @RANLIB_PLUGIN_OPTION@
--MAKEINFO = @MAKEINFO@
-+MAKEINFO = true
- PERL = @PERL@
- 
- PICFLAG = @PICFLAG@
-diff -ur binutils-2.41.orig/Makefile.in binutils-2.40/Makefile.in
---- binutils-2.41.orig/Makefile.in	2022-08-05 13:00:56.000000000 +0200
-+++ binutils-2.40/Makefile.in	2022-08-20 05:46:38.549035896 +0200
-@@ -399,7 +399,7 @@
- FLEX = @FLEX@
- LEX = @LEX@
- M4 = @M4@
--MAKEINFO = @MAKEINFO@
-+MAKEINFO = true
- EXPECT = @EXPECT@
- RUNTEST = @RUNTEST@
- 
-diff -ur binutils-2.41.orig/Makefile.tpl binutils-2.40/Makefile.tpl
---- binutils-2.41.orig/Makefile.tpl	2022-07-08 11:46:47.000000000 +0200
-+++ binutils-2.40/Makefile.tpl	2022-08-20 05:46:38.535035856 +0200
-@@ -402,7 +402,7 @@
- FLEX = @FLEX@
- LEX = @LEX@
- M4 = @M4@
--MAKEINFO = @MAKEINFO@
-+MAKEINFO = true
- EXPECT = @EXPECT@
- RUNTEST = @RUNTEST@
- 
-diff -ur binutils-2.41.orig/opcodes/Makefile.in binutils-2.40/opcodes/Makefile.in
---- binutils-2.41.orig/opcodes/Makefile.in	2022-08-05 11:54:59.000000000 +0200
-+++ binutils-2.40/opcodes/Makefile.in	2022-08-20 05:46:38.522035819 +0200
-@@ -324,7 +324,7 @@
- LN_S = @LN_S@
- LTLIBOBJS = @LTLIBOBJS@
- MAINT = @MAINT@
--MAKEINFO = @MAKEINFO@
-+MAKEINFO = true
- MKDIR_P = @MKDIR_P@
- MKINSTALLDIRS = @MKINSTALLDIRS@
- MSGFMT = @MSGFMT@
-diff -ur binutils-2.41.orig/zlib/Makefile.in binutils-2.40/zlib/Makefile.in
---- binutils-2.41.orig/zlib/Makefile.in	2022-07-08 11:56:28.000000000 +0200
-+++ binutils-2.40/zlib/Makefile.in	2022-08-20 05:46:38.571035960 +0200
-@@ -321,7 +321,7 @@
- LN_S = @LN_S@
- LTLIBOBJS = @LTLIBOBJS@
- MAINT = @MAINT@
--MAKEINFO = @MAKEINFO@
-+MAKEINFO = true
- MKDIR_P = @MKDIR_P@
- NM = @NM@
- NMEDIT = @NMEDIT@
diff --git a/util/crossgcc/patches/binutils-2.43.1_as-ipxe.patch b/util/crossgcc/patches/binutils-2.44_as-ipxe.patch
similarity index 78%
rename from util/crossgcc/patches/binutils-2.43.1_as-ipxe.patch
rename to util/crossgcc/patches/binutils-2.44_as-ipxe.patch
index fb15cce5ec..afd587c777 100644
--- a/util/crossgcc/patches/binutils-2.43.1_as-ipxe.patch
+++ b/util/crossgcc/patches/binutils-2.44_as-ipxe.patch
@@ -2,18 +2,10 @@ From 6984bd861cc595e56d26ea033851d9174e855129 Mon Sep 17 00:00:00 2001
 From: Himanshu Sahdev aka CunningLearner <sahdev.himan@gmail.com>
 Date: Mon, 26 Aug 2019 16:57:13 +0530
 Subject: [PATCH] as: facilitate tests based on /dev/null
-
 Signed-off-by: Himanshu Sahdev <himanshusah@hcl.com>
-
----
- gas/as.c | 4 ++--
- 1 file changed, 2 insertions(+), 2 deletions(-)
-
-diff --git a/gas/as.c b/gas/as.c
-index 728811bc..78b4802c 100644
 --- a/gas/as.c
 +++ b/gas/as.c
-@@ -1364,13 +1364,14 @@ main (int argc, char ** argv)
+@@ -1385,13 +1385,14 @@
    char ** argv_orig = argv;
    struct stat sob;
  
@@ -28,7 +20,3 @@ index 728811bc..78b4802c 100644
 +  if (argc > 1 && stat (out_file_name, &sob) == 0 && strcmp(out_file_name,dev_null_file)!=0)
      {
        int i;
- 
--- 
-2.17.1
-
diff --git a/util/crossgcc/patches/binutils-2.44_no-makeinfo.patch b/util/crossgcc/patches/binutils-2.44_no-makeinfo.patch
new file mode 100644
index 0000000000..2dac8b1b2c
--- /dev/null
+++ b/util/crossgcc/patches/binutils-2.44_no-makeinfo.patch
@@ -0,0 +1,217 @@
+It fails to compile when using "MAKEINFO = @MAKEINFO@":
+binutils-gdb/missing: 81: makeinfo: not found
+WARNING: 'makeinfo' is missing on your system.
+         You should only need it if you modified a '.texi' file, or
+         any other file indirectly affecting the aspect of the manual.
+         You might want to install the Texinfo package:
+         <http://www.gnu.org/software/texinfo/>
+         The spurious makeinfo call might also be the consequence of
+         using a buggy 'make' (AIX, DU, IRIX), in which case you might
+         want to install GNU make:
+         <http://www.gnu.org/software/make/>
+make[4]: *** [Makefile:507: as.info] Error 127
+Current patch will change that to "MAKEINFO = true"
+diff -ur binutils-2.44.orig/bfd/Makefile.in binutils-2.44/bfd/Makefile.in
+--- binutils-2.44.orig/bfd/Makefile.in	2022-08-05 11:53:59.000000000 +0200
++++ binutils-2.44/bfd/Makefile.in	2022-08-20 05:46:39.960039957 +0200
+@@ -379,7 +379,7 @@
+ LN_S = @LN_S@
+ LTLIBOBJS = @LTLIBOBJS@
+ MAINT = @MAINT@
+-MAKEINFO = @MAKEINFO@
++MAKEINFO = true
+ MKDIR_P = @MKDIR_P@
+ MKINSTALLDIRS = @MKINSTALLDIRS@
+ MSGFMT = @MSGFMT@
+diff -ur binutils-2.44.orig/binutils/Makefile.in binutils-2.44/binutils/Makefile.in
+--- binutils-2.44.orig/binutils/Makefile.in	2022-08-05 11:56:21.000000000 +0200
++++ binutils-2.44/binutils/Makefile.in	2022-08-20 05:46:38.563035937 +0200
+@@ -532,7 +532,7 @@
+ LTLIBICONV = @LTLIBICONV@
+ LTLIBOBJS = @LTLIBOBJS@
+ MAINT = @MAINT@
+-MAKEINFO = @MAKEINFO@
++MAKEINFO = true
+ MKDIR_P = @MKDIR_P@
+ MKINSTALLDIRS = @MKINSTALLDIRS@
+ MSGFMT = @MSGFMT@
+diff -ur binutils-2.44.orig/etc/Makefile.in binutils-2.44/etc/Makefile.in
+--- binutils-2.44.orig/etc/Makefile.in	2022-07-08 11:46:47.000000000 +0200
++++ binutils-2.44/etc/Makefile.in	2022-08-20 05:46:38.525035827 +0200
+@@ -154,7 +154,7 @@
+ LIBS = @LIBS@
+ LTLIBOBJS = @LTLIBOBJS@
+ MAINT = @MAINT@
+-MAKEINFO = @MAKEINFO@
++MAKEINFO = true
+ MKDIR_P = @MKDIR_P@
+ PACKAGE = @PACKAGE@
+ PACKAGE_BUGREPORT = @PACKAGE_BUGREPORT@
+diff -ur binutils-2.44.orig/gas/Makefile.in binutils-2.44/gas/Makefile.in
+--- binutils-2.44.orig/gas/Makefile.in	2022-08-05 11:55:17.000000000 +0200
++++ binutils-2.44/gas/Makefile.in	2022-08-20 05:46:38.535035856 +0200
+@@ -408,7 +408,7 @@
+ LN_S = @LN_S@
+ LTLIBOBJS = @LTLIBOBJS@
+ MAINT = @MAINT@
+-MAKEINFO = @MAKEINFO@
++MAKEINFO = true
+ MKDIR_P = @MKDIR_P@
+ MKINSTALLDIRS = @MKINSTALLDIRS@
+ MSGFMT = @MSGFMT@
+diff -ur binutils-2.44.orig/gprof/Makefile.in binutils-2.44/gprof/Makefile.in
+--- binutils-2.44.orig/gprof/Makefile.in	2022-08-05 11:59:11.000000000 +0200
++++ binutils-2.44/gprof/Makefile.in	2022-08-20 05:46:39.964039969 +0200
+@@ -351,7 +351,7 @@
+ LN_S = @LN_S@
+ LTLIBOBJS = @LTLIBOBJS@
+ MAINT = @MAINT@
+-MAKEINFO = @MAKEINFO@
++MAKEINFO = true
+ MKDIR_P = @MKDIR_P@
+ MKINSTALLDIRS = @MKINSTALLDIRS@
+ MSGFMT = @MSGFMT@
+diff -ur binutils-2.44.orig/gprofng/doc/Makefile.in binutils-2.44/gprofng/doc/Makefile.in
+--- binutils-2.44.orig/gprofng/doc/Makefile.in	2022-08-05 11:59:31.000000000 +0200
++++ binutils-2.44/gprofng/doc/Makefile.in	2022-08-20 05:46:39.252037920 +0200
+@@ -271,7 +271,7 @@
+ LN_S = @LN_S@
+ LTLIBOBJS = @LTLIBOBJS@
+ MAINT = @MAINT@
+-MAKEINFO = @MAKEINFO@
++MAKEINFO = true
+ MKDIR_P = @MKDIR_P@
+ NM = @NM@
+ NMEDIT = @NMEDIT@
+diff -ur binutils-2.44.orig/gprofng/gp-display-html/Makefile.in binutils-2.44/gprofng/gp-display-html/Makefile.in
+--- binutils-2.44.orig/gprofng/gp-display-html/Makefile.in	2022-08-05 11:59:33.000000000 +0200
++++ binutils-2.44/gprofng/gp-display-html/Makefile.in	2022-08-20 05:46:39.479038573 +0200
+@@ -234,7 +234,7 @@
+ LN_S = @LN_S@
+ LTLIBOBJS = @LTLIBOBJS@
+ MAINT = @MAINT@
+-MAKEINFO = @MAKEINFO@
++MAKEINFO = true
+ MKDIR_P = @MKDIR_P@
+ NM = @NM@
+ NMEDIT = @NMEDIT@
+diff -ur binutils-2.44.orig/gprofng/libcollector/Makefile.in binutils-2.44/gprofng/libcollector/Makefile.in
+--- binutils-2.44.orig/gprofng/libcollector/Makefile.in	2022-08-05 11:59:38.000000000 +0200
++++ binutils-2.44/gprofng/libcollector/Makefile.in	2022-08-20 05:46:38.965037094 +0200
+@@ -341,7 +341,7 @@
+ LN_S = @LN_S@
+ LTLIBOBJS = @LTLIBOBJS@
+ MAINT = @MAINT@
+-MAKEINFO = @MAKEINFO@
++MAKEINFO = true
+ MKDIR_P = @MKDIR_P@
+ NM = @NM@
+ NMEDIT = @NMEDIT@
+diff -ur binutils-2.44.orig/gprofng/Makefile.in binutils-2.44/gprofng/Makefile.in
+--- binutils-2.44.orig/gprofng/Makefile.in	2022-08-05 11:59:30.000000000 +0200
++++ binutils-2.44/gprofng/Makefile.in	2022-08-20 05:46:38.574035968 +0200
+@@ -289,7 +289,7 @@
+ LN_S = @LN_S@
+ LTLIBOBJS = @LTLIBOBJS@
+ MAINT = @MAINT@
+-MAKEINFO = @MAKEINFO@
++MAKEINFO = true
+ MKDIR_P = @MKDIR_P@
+ NM = @NM@
+ NMEDIT = @NMEDIT@
+diff -ur binutils-2.44.orig/gprofng/src/Makefile.in binutils-2.44/gprofng/src/Makefile.in
+--- binutils-2.44.orig/gprofng/src/Makefile.in	2022-08-05 11:59:34.000000000 +0200
++++ binutils-2.44/gprofng/src/Makefile.in	2022-08-20 05:46:38.573035965 +0200
+@@ -358,7 +358,7 @@
+ LN_S = @LN_S@
+ LTLIBOBJS = @LTLIBOBJS@
+ MAINT = @MAINT@
+-MAKEINFO = @MAKEINFO@
++MAKEINFO = true
+ MKDIR_P = @MKDIR_P@
+ NM = @NM@
+ NMEDIT = @NMEDIT@
+diff -ur binutils-2.44.orig/ld/Makefile.in binutils-2.44/ld/Makefile.in
+--- binutils-2.44.orig/ld/Makefile.in	2022-08-05 11:56:53.000000000 +0200
++++ binutils-2.44/ld/Makefile.in	2022-08-20 05:46:38.536035859 +0200
+@@ -432,7 +432,7 @@
+ LN_S = @LN_S@
+ LTLIBOBJS = @LTLIBOBJS@
+ MAINT = @MAINT@
+-MAKEINFO = @MAKEINFO@
++MAKEINFO = true
+ MKDIR_P = @MKDIR_P@
+ MKINSTALLDIRS = @MKINSTALLDIRS@
+ MSGFMT = @MSGFMT@
+diff -ur binutils-2.44.orig/libctf/Makefile.in binutils-2.44/libctf/Makefile.in
+--- binutils-2.44.orig/libctf/Makefile.in	2022-07-08 12:02:15.000000000 +0200
++++ binutils-2.44/libctf/Makefile.in	2022-08-20 05:46:39.771039414 +0200
+@@ -425,7 +425,7 @@
+ LN_S = @LN_S@
+ LTLIBOBJS = @LTLIBOBJS@
+ MAINT = @MAINT@
+-MAKEINFO = @MAKEINFO@
++MAKEINFO = true
+ MKDIR_P = @MKDIR_P@
+ NM = @NM@
+ NMEDIT = @NMEDIT@
+diff -ur binutils-2.44.orig/libiberty/Makefile.in binutils-2.44/libiberty/Makefile.in
+--- binutils-2.44.orig/libiberty/Makefile.in	2022-07-08 11:46:48.000000000 +0200
++++ binutils-2.44/libiberty/Makefile.in	2022-08-20 05:46:39.961039960 +0200
+@@ -57,7 +57,7 @@
+ CFLAGS = @CFLAGS@
+ CPPFLAGS = @CPPFLAGS@
+ RANLIB = @RANLIB@ @RANLIB_PLUGIN_OPTION@
+-MAKEINFO = @MAKEINFO@
++MAKEINFO = true
+ PERL = @PERL@
+ 
+ PICFLAG = @PICFLAG@
+diff -ur binutils-2.44.orig/Makefile.in binutils-2.44/Makefile.in
+--- binutils-2.44.orig/Makefile.in	2022-08-05 13:00:56.000000000 +0200
++++ binutils-2.44/Makefile.in	2022-08-20 05:46:38.549035896 +0200
+@@ -399,7 +399,7 @@
+ FLEX = @FLEX@
+ LEX = @LEX@
+ M4 = @M4@
+-MAKEINFO = @MAKEINFO@
++MAKEINFO = true
+ EXPECT = @EXPECT@
+ RUNTEST = @RUNTEST@
+ 
+diff -ur binutils-2.44.orig/Makefile.tpl binutils-2.44/Makefile.tpl
+--- binutils-2.44.orig/Makefile.tpl	2022-07-08 11:46:47.000000000 +0200
++++ binutils-2.44/Makefile.tpl	2022-08-20 05:46:38.535035856 +0200
+@@ -402,7 +402,7 @@
+ FLEX = @FLEX@
+ LEX = @LEX@
+ M4 = @M4@
+-MAKEINFO = @MAKEINFO@
++MAKEINFO = true
+ EXPECT = @EXPECT@
+ RUNTEST = @RUNTEST@
+ 
+diff -ur binutils-2.44.orig/opcodes/Makefile.in binutils-2.44/opcodes/Makefile.in
+--- binutils-2.44.orig/opcodes/Makefile.in	2022-08-05 11:54:59.000000000 +0200
++++ binutils-2.44/opcodes/Makefile.in	2022-08-20 05:46:38.522035819 +0200
+@@ -324,7 +324,7 @@
+ LN_S = @LN_S@
+ LTLIBOBJS = @LTLIBOBJS@
+ MAINT = @MAINT@
+-MAKEINFO = @MAKEINFO@
++MAKEINFO = true
+ MKDIR_P = @MKDIR_P@
+ MKINSTALLDIRS = @MKINSTALLDIRS@
+ MSGFMT = @MSGFMT@
+diff -ur binutils-2.44.orig/zlib/Makefile.in binutils-2.44/zlib/Makefile.in
+--- binutils-2.44.orig/zlib/Makefile.in	2022-07-08 11:56:28.000000000 +0200
++++ binutils-2.44/zlib/Makefile.in	2022-08-20 05:46:38.571035960 +0200
+@@ -321,7 +321,7 @@
+ LN_S = @LN_S@
+ LTLIBOBJS = @LTLIBOBJS@
+ MAINT = @MAINT@
+-MAKEINFO = @MAKEINFO@
++MAKEINFO = true
+ MKDIR_P = @MKDIR_P@
+ NM = @NM@
+ NMEDIT = @NMEDIT@
diff --git a/util/crossgcc/sum/binutils-2.43.1.tar.xz.cksum b/util/crossgcc/sum/binutils-2.43.1.tar.xz.cksum
deleted file mode 100644
index 80914b7ef8..0000000000
--- a/util/crossgcc/sum/binutils-2.43.1.tar.xz.cksum
+++ /dev/null
@@ -1 +0,0 @@
-86bfee61d18cb9ea84ca700ecb820d97bb4e92a7  tarballs/binutils-2.43.1.tar.xz
diff --git a/util/crossgcc/sum/binutils-2.44.tar.xz.cksum b/util/crossgcc/sum/binutils-2.44.tar.xz.cksum
new file mode 100644
index 0000000000..fd3669abff
--- /dev/null
+++ b/util/crossgcc/sum/binutils-2.44.tar.xz.cksum
@@ -0,0 +1 @@
+c8c9f5ae46ab9e3722c71821982d2c270e267748  tarballs/binutils-2.44.tar.xz

From ae282fe502c93f6b0d554e1565f7632ef872d45b Mon Sep 17 00:00:00 2001
From: Elyes Haouas <ehaouas@noos.fr>
Date: Wed, 26 Feb 2025 17:04:02 +0100
Subject: [PATCH 1455/3886] drivers/generic/bayhub: Use boolean for
 power_saving

Change-Id: I7cc89989296b48e20b41e6ff06570a9d30bfc114
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86607
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
---
 src/drivers/generic/bayhub/chip.h                            | 4 ++--
 src/mainboard/google/kahlee/variants/baseboard/devicetree.cb | 2 +-
 src/mainboard/google/kahlee/variants/nuwani/overridetree.cb  | 2 +-
 src/mainboard/google/kahlee/variants/treeya/overridetree.cb  | 2 +-
 src/mainboard/google/sarien/variants/arcada/devicetree.cb    | 2 +-
 src/mainboard/google/sarien/variants/sarien/devicetree.cb    | 4 ++--
 6 files changed, 8 insertions(+), 8 deletions(-)

diff --git a/src/drivers/generic/bayhub/chip.h b/src/drivers/generic/bayhub/chip.h
index 82fe67085b..e43bf5f02c 100644
--- a/src/drivers/generic/bayhub/chip.h
+++ b/src/drivers/generic/bayhub/chip.h
@@ -9,8 +9,8 @@
  * Bayhub BG720 PCI to eMMC bridge
  */
 struct drivers_generic_bayhub_config {
-	/* 1 to enable power-saving mode, 0 to disable */
-	int power_saving;
+	/* enable/disable power-saving mode */
+	bool power_saving;
 
 	/* When set, disables programming HS200 mode */
 	bool disable_hs200_mode;
diff --git a/src/mainboard/google/kahlee/variants/baseboard/devicetree.cb b/src/mainboard/google/kahlee/variants/baseboard/devicetree.cb
index 4deac2beed..6176b69f4c 100644
--- a/src/mainboard/google/kahlee/variants/baseboard/devicetree.cb
+++ b/src/mainboard/google/kahlee/variants/baseboard/devicetree.cb
@@ -20,7 +20,7 @@ chip soc/amd/stoneyridge
 		device ref gpp_bridge_1 on end # WLAN
 		device ref gpp_bridge_3 on
 			chip drivers/generic/bayhub
-				register "power_saving" = "1"
+				register "power_saving" = "true"
 				device pci 00.0 on end
 			end
 		end
diff --git a/src/mainboard/google/kahlee/variants/nuwani/overridetree.cb b/src/mainboard/google/kahlee/variants/nuwani/overridetree.cb
index f53a6720cc..c618542fb8 100644
--- a/src/mainboard/google/kahlee/variants/nuwani/overridetree.cb
+++ b/src/mainboard/google/kahlee/variants/nuwani/overridetree.cb
@@ -40,7 +40,7 @@ chip soc/amd/stoneyridge
 	device domain 0 on
 		device ref gpp_bridge_3 on
 			chip drivers/generic/bayhub
-				register "power_saving" = "1"
+				register "power_saving" = "true"
 				register "vih_tuning_value" = "0x35"
 				device pci 00.0 on end
 			end
diff --git a/src/mainboard/google/kahlee/variants/treeya/overridetree.cb b/src/mainboard/google/kahlee/variants/treeya/overridetree.cb
index 011b3a1295..fe9e6ac1fe 100644
--- a/src/mainboard/google/kahlee/variants/treeya/overridetree.cb
+++ b/src/mainboard/google/kahlee/variants/treeya/overridetree.cb
@@ -40,7 +40,7 @@ chip soc/amd/stoneyridge
 	device domain 0 on
 		device ref gpp_bridge_3 on
 			chip drivers/generic/bayhub
-				register "power_saving" = "1"
+				register "power_saving" = "true"
 				register "vih_tuning_value" = "0x35"
 				device pci 00.0 on end
 			end
diff --git a/src/mainboard/google/sarien/variants/arcada/devicetree.cb b/src/mainboard/google/sarien/variants/arcada/devicetree.cb
index aed9743573..624856ce45 100644
--- a/src/mainboard/google/sarien/variants/arcada/devicetree.cb
+++ b/src/mainboard/google/sarien/variants/arcada/devicetree.cb
@@ -346,7 +346,7 @@ chip soc/intel/cannonlake
 		device ref pcie_rp13 on
 			# x4 lanes
 			chip drivers/generic/bayhub
-				register "power_saving" = "1"
+				register "power_saving" = "true"
 				device pci 00.0 on end
 			end
 			smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "2280" "SlotDataBusWidth4X"
diff --git a/src/mainboard/google/sarien/variants/sarien/devicetree.cb b/src/mainboard/google/sarien/variants/sarien/devicetree.cb
index c88bf6fff0..a90c7b2b98 100644
--- a/src/mainboard/google/sarien/variants/sarien/devicetree.cb
+++ b/src/mainboard/google/sarien/variants/sarien/devicetree.cb
@@ -372,7 +372,7 @@ chip soc/intel/cannonlake
 		end
 		device ref pcie_rp9 on
 			chip drivers/generic/bayhub
-				register "power_saving" = "1"
+				register "power_saving" = "true"
 				device pci 00.0 on end
 			end
 			smbios_slot_desc "SlotTypeM2Socket1_SD" "SlotLengthOther" "2230" "SlotDataBusWidth1X"
@@ -384,7 +384,7 @@ chip soc/intel/cannonlake
 		device ref pcie_rp13 on
 			# x4 lanes
 			chip drivers/generic/bayhub
-				register "power_saving" = "1"
+				register "power_saving" = "true"
 				device pci 00.0 on end
 			end
 			smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "2280" "SlotDataBusWidth4X"

From f33507c1d80605a4cc691eee7ecd4eec8803bb0e Mon Sep 17 00:00:00 2001
From: Elyes Haouas <ehaouas@noos.fr>
Date: Wed, 26 Feb 2025 17:06:07 +0100
Subject: [PATCH 1456/3886] mb/{google/zork,novacustom/mtl-h}: Use true/false
 for boolean

enable_power_saving is a boolean so use "true" "false".

Change-Id: I0f62fc2b0db3abd3f204951f15081b89e02a0754
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86608
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/google/zork/variants/vilboz/overridetree.cb | 2 +-
 src/mainboard/novacustom/mtl-h/devicetree.cb              | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/mainboard/google/zork/variants/vilboz/overridetree.cb b/src/mainboard/google/zork/variants/vilboz/overridetree.cb
index b1d0c0f6a9..8740611c6a 100644
--- a/src/mainboard/google/zork/variants/vilboz/overridetree.cb
+++ b/src/mainboard/google/zork/variants/vilboz/overridetree.cb
@@ -154,7 +154,7 @@ chip soc/amd/picasso
 		subsystemid 0x1022 0x1510 inherit
 		device ref gpp_bridge_2 on
 			chip drivers/generic/bayhub_lv2
-				register "enable_power_saving" = "1"
+				register "enable_power_saving" = "true"
 				device pci 00.0 on end
 			end
 		end # SD
diff --git a/src/mainboard/novacustom/mtl-h/devicetree.cb b/src/mainboard/novacustom/mtl-h/devicetree.cb
index 76548bb292..e45fc99b7a 100644
--- a/src/mainboard/novacustom/mtl-h/devicetree.cb
+++ b/src/mainboard/novacustom/mtl-h/devicetree.cb
@@ -203,7 +203,7 @@ chip soc/intel/meteorlake
 				.flags = PCIE_RP_LTR | PCIE_RP_AER,
 			}"
 			chip drivers/generic/bayhub_lv2
-				register "enable_power_saving" = "1"
+				register "enable_power_saving" = "true"
 				device pci 00.0 on end
 			end
 		end

From 9be383b855b57aedf156fdad3ffb3a20f96acf61 Mon Sep 17 00:00:00 2001
From: Elyes Haouas <ehaouas@noos.fr>
Date: Wed, 26 Feb 2025 17:22:21 +0100
Subject: [PATCH 1457/3886] drivers/lenovo/hybrid_graphics/chip: Use boolean
 when appropriate

Change-Id: I1f456765eb60b8ad1e680255b50abad5dea8252c
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86610
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
---
 src/drivers/lenovo/hybrid_graphics/chip.h          | 14 +++++++-------
 .../lenovo/t400/variants/t400/overridetree.cb      | 12 ++++++------
 src/mainboard/lenovo/t410/devicetree.cb            | 14 +++++++-------
 src/mainboard/lenovo/t420/devicetree.cb            | 10 +++++-----
 src/mainboard/lenovo/t420s/devicetree.cb           | 10 +++++-----
 src/mainboard/lenovo/t430/devicetree.cb            | 10 +++++-----
 src/mainboard/lenovo/t520/devicetree.cb            | 10 +++++-----
 src/mainboard/lenovo/t530/devicetree.cb            | 10 +++++-----
 8 files changed, 45 insertions(+), 45 deletions(-)

diff --git a/src/drivers/lenovo/hybrid_graphics/chip.h b/src/drivers/lenovo/hybrid_graphics/chip.h
index b3ea2b6d2f..4a17138552 100644
--- a/src/drivers/lenovo/hybrid_graphics/chip.h
+++ b/src/drivers/lenovo/hybrid_graphics/chip.h
@@ -23,19 +23,19 @@ enum dgpu_detect_lvl {
 struct drivers_lenovo_hybrid_graphics_config {
 	unsigned int detect_gpio;
 
-	unsigned int has_panel_hybrid_gpio;
+	bool has_panel_hybrid_gpio;
 	unsigned int panel_hybrid_gpio;
-	unsigned int panel_integrated_lvl;
+	bool panel_integrated_lvl;
 
-	unsigned int has_backlight_gpio;
+	bool has_backlight_gpio;
 	unsigned int backlight_gpio;
-	unsigned int backlight_integrated_lvl;
+	bool backlight_integrated_lvl;
 
-	unsigned int has_dgpu_power_gpio;
+	bool has_dgpu_power_gpio;
 	unsigned int dgpu_power_gpio;
-	unsigned int dgpu_power_off_lvl;
+	bool dgpu_power_off_lvl;
 
-	unsigned int has_thinker1;
+	bool has_thinker1;
 };
 
 #endif /* _LENOVO_HYBRID_GRAPHICS_CHIP_H_ */
diff --git a/src/mainboard/lenovo/t400/variants/t400/overridetree.cb b/src/mainboard/lenovo/t400/variants/t400/overridetree.cb
index a1b4f9de3c..c3c3b082a5 100644
--- a/src/mainboard/lenovo/t400/variants/t400/overridetree.cb
+++ b/src/mainboard/lenovo/t400/variants/t400/overridetree.cb
@@ -8,17 +8,17 @@ chip northbridge/intel/gm45
 
 					register "detect_gpio" = "21"
 
-					register "has_panel_hybrid_gpio" = "1"
+					register "has_panel_hybrid_gpio" = "true"
 					register "panel_hybrid_gpio" = "22"
-					register "panel_integrated_lvl" = "0"
+					register "panel_integrated_lvl" = "false"
 
-					register "has_backlight_gpio" = "1"
+					register "has_backlight_gpio" = "true"
 					register "backlight_gpio" = "19"
-					register "backlight_integrated_lvl" = "0"
+					register "backlight_integrated_lvl" = "false"
 
-					register "has_dgpu_power_gpio" = "1"
+					register "has_dgpu_power_gpio" = "true"
 					register "dgpu_power_gpio" = "49"
-					register "dgpu_power_off_lvl" = "0"
+					register "dgpu_power_off_lvl" = "false"
 
 					register "has_thinker1" = "0"
 				end
diff --git a/src/mainboard/lenovo/t410/devicetree.cb b/src/mainboard/lenovo/t410/devicetree.cb
index 1ef7075ebf..9ba70d79e8 100644
--- a/src/mainboard/lenovo/t410/devicetree.cb
+++ b/src/mainboard/lenovo/t410/devicetree.cb
@@ -138,19 +138,19 @@ chip northbridge/intel/ironlake
 
 					register "detect_gpio" = "21"
 
-					register "has_panel_hybrid_gpio" = "1"
+					register "has_panel_hybrid_gpio" = "true"
 					register "panel_hybrid_gpio" = "52"
-					register "panel_integrated_lvl" = "1"
+					register "panel_integrated_lvl" = "true"
 
-					register "has_backlight_gpio" = "1"
+					register "has_backlight_gpio" = "true"
 					register "backlight_gpio" = "50"
-					register "backlight_integrated_lvl" = "0"
+					register "backlight_integrated_lvl" = "false"
 
-					register "has_dgpu_power_gpio" = "1"
+					register "has_dgpu_power_gpio" = "true"
 					register "dgpu_power_gpio" = "49"
-					register "dgpu_power_off_lvl" = "0"
+					register "dgpu_power_off_lvl" = "false"
 
-					register "has_thinker1" = "1"
+					register "has_thinker1" = "true"
 				end
 			end
 			device pci 1f.2 on # IDE/SATA
diff --git a/src/mainboard/lenovo/t420/devicetree.cb b/src/mainboard/lenovo/t420/devicetree.cb
index 65891f0c30..f5272fc701 100644
--- a/src/mainboard/lenovo/t420/devicetree.cb
+++ b/src/mainboard/lenovo/t420/devicetree.cb
@@ -158,14 +158,14 @@ chip northbridge/intel/sandybridge
 
 					register "detect_gpio" = "21"
 
-					register "has_panel_hybrid_gpio" = "1"
+					register "has_panel_hybrid_gpio" = "true"
 					register "panel_hybrid_gpio" = "52"
-					register "panel_integrated_lvl" = "1"
+					register "panel_integrated_lvl" = "true"
 
-					register "has_backlight_gpio" = "0"
-					register "has_dgpu_power_gpio" = "0"
+					register "has_backlight_gpio" = "false"
+					register "has_dgpu_power_gpio" = "false"
 
-					register "has_thinker1" = "1"
+					register "has_thinker1" = "true"
 				end
 			end # LPC Controller
 			device ref sata1 on end # 6 port SATA AHCI Controller
diff --git a/src/mainboard/lenovo/t420s/devicetree.cb b/src/mainboard/lenovo/t420s/devicetree.cb
index b358885069..840e520fbb 100644
--- a/src/mainboard/lenovo/t420s/devicetree.cb
+++ b/src/mainboard/lenovo/t420s/devicetree.cb
@@ -150,14 +150,14 @@ chip northbridge/intel/sandybridge
 
 					register "detect_gpio" = "21"
 
-					register "has_panel_hybrid_gpio" = "1"
+					register "has_panel_hybrid_gpio" = "true"
 					register "panel_hybrid_gpio" = "52"
-					register "panel_integrated_lvl" = "1"
+					register "panel_integrated_lvl" = "true"
 
-					register "has_backlight_gpio" = "0"
-					register "has_dgpu_power_gpio" = "0"
+					register "has_backlight_gpio" = "false"
+					register "has_dgpu_power_gpio" = "false"
 
-					register "has_thinker1" = "1"
+					register "has_thinker1" = "true"
 				end
 			end # LPC Controller
 			device ref sata1 on end # 6 port SATA AHCI Controller
diff --git a/src/mainboard/lenovo/t430/devicetree.cb b/src/mainboard/lenovo/t430/devicetree.cb
index 89dcf97fea..9a0db4dd85 100644
--- a/src/mainboard/lenovo/t430/devicetree.cb
+++ b/src/mainboard/lenovo/t430/devicetree.cb
@@ -131,14 +131,14 @@ chip northbridge/intel/sandybridge
 
 					register "detect_gpio" = "21"
 
-					register "has_panel_hybrid_gpio" = "1"
+					register "has_panel_hybrid_gpio" = "true"
 					register "panel_hybrid_gpio" = "52"
-					register "panel_integrated_lvl" = "1"
+					register "panel_integrated_lvl" = "true"
 
-					register "has_backlight_gpio" = "0"
-					register "has_dgpu_power_gpio" = "0"
+					register "has_backlight_gpio" = "false"
+					register "has_dgpu_power_gpio" = "false"
 
-					register "has_thinker1" = "1"
+					register "has_thinker1" = "true"
 				end
 				chip drivers/pc80/tpm
 					device pnp 0c31.0 on end
diff --git a/src/mainboard/lenovo/t520/devicetree.cb b/src/mainboard/lenovo/t520/devicetree.cb
index c404df2d2d..7102df0b9d 100644
--- a/src/mainboard/lenovo/t520/devicetree.cb
+++ b/src/mainboard/lenovo/t520/devicetree.cb
@@ -146,14 +146,14 @@ chip northbridge/intel/sandybridge
 
 					register "detect_gpio" = "21"
 
-					register "has_panel_hybrid_gpio" = "1"
+					register "has_panel_hybrid_gpio" = "true"
 					register "panel_hybrid_gpio" = "52"
-					register "panel_integrated_lvl" = "1"
+					register "panel_integrated_lvl" = "true"
 
-					register "has_backlight_gpio" = "0"
-					register "has_dgpu_power_gpio" = "0"
+					register "has_backlight_gpio" = "false"
+					register "has_dgpu_power_gpio" = "false"
 
-					register "has_thinker1" = "1"
+					register "has_thinker1" = "true"
 				end
 			end
 			device ref sata1 on end
diff --git a/src/mainboard/lenovo/t530/devicetree.cb b/src/mainboard/lenovo/t530/devicetree.cb
index 305a47efff..362e0a69e9 100644
--- a/src/mainboard/lenovo/t530/devicetree.cb
+++ b/src/mainboard/lenovo/t530/devicetree.cb
@@ -126,14 +126,14 @@ chip northbridge/intel/sandybridge
 
 					register "detect_gpio" = "21"
 
-					register "has_panel_hybrid_gpio" = "1"
+					register "has_panel_hybrid_gpio" = "true"
 					register "panel_hybrid_gpio" = "52"
-					register "panel_integrated_lvl" = "1"
+					register "panel_integrated_lvl" = "true"
 
-					register "has_backlight_gpio" = "0"
-					register "has_dgpu_power_gpio" = "0"
+					register "has_backlight_gpio" = "false"
+					register "has_dgpu_power_gpio" = "false"
 
-					register "has_thinker1" = "1"
+					register "has_thinker1" = "true"
 				end
 			end
 			device ref sata1 on end

From c0413336bc0550eafc58fedf0b87e2b8f4160eda Mon Sep 17 00:00:00 2001
From: Elyes Haouas <ehaouas@noos.fr>
Date: Thu, 24 Oct 2024 19:12:17 +0200
Subject: [PATCH 1458/3886] acpi/acpi.h: Use boolean

permanent_smi_handler and acpi_s3_resume_allowed returns boolean,
so use boolean instead of int.

Change-Id: I8f390bf3b472519dc41db7daa57b16458961139e
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84858
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
---
 src/include/acpi/acpi.h | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/include/acpi/acpi.h b/src/include/acpi/acpi.h
index 4d9599dac7..06dba65738 100644
--- a/src/include/acpi/acpi.h
+++ b/src/include/acpi/acpi.h
@@ -1967,12 +1967,12 @@ int acpi_get_gpe(int gpe);
 
 /* Once we enter payload, is SMI handler installed and capable of
    responding to APM_CNT Advanced Power Management Control commands. */
-static inline int permanent_smi_handler(void)
+static inline bool permanent_smi_handler(void)
 {
 	return CONFIG(HAVE_SMI_HANDLER);
 }
 
-static inline int acpi_s3_resume_allowed(void)
+static inline bool acpi_s3_resume_allowed(void)
 {
 	return CONFIG(HAVE_ACPI_RESUME);
 }

From 17abedaef6115493eb8dcf14ed246a74fe8a216b Mon Sep 17 00:00:00 2001
From: Elyes Haouas <ehaouas@noos.fr>
Date: Sat, 8 Feb 2025 09:37:59 +0100
Subject: [PATCH 1459/3886] include/smp/node: Drop unused is_smp_boot

Change-Id: I831d405c58817da64eb241f432a3eb8a096dbe1b
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86327
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
---
 src/include/smp/node.h | 5 -----
 1 file changed, 5 deletions(-)

diff --git a/src/include/smp/node.h b/src/include/smp/node.h
index 8f3d14fde1..78db124e8f 100644
--- a/src/include/smp/node.h
+++ b/src/include/smp/node.h
@@ -9,9 +9,4 @@ int boot_cpu(void);
 #define boot_cpu(x) 1
 #endif
 
-static inline int is_smp_boot(void)
-{
-	return CONFIG(SMP) && CONFIG_MAX_CPUS > 1;
-}
-
 #endif /* _SMP_NODE_H_ */

From d636b38577e7ab6b81c9b0e9e188767f2f7920a3 Mon Sep 17 00:00:00 2001
From: Subrata Banik <subratabanik@google.com>
Date: Mon, 30 Jun 2025 16:39:57 +0000
Subject: [PATCH 1460/3886] soc/qualcomm/x1p42100: Select
 ARM64_USE_ARM_TRUSTED_FIRMWARE

This commit enables `ARM64_USE_ARM_TRUSTED_FIRMWARE` for the
Qualcomm X1P42100 SoC.

Selecting this option ensures that coreboot is configured to
integrate with ARM Trusted Firmware (TF-A), which is essential
for proper boot and power management functionality on this platform.

BUG=b:424149462
TEST=Able to build google/bluey.

Change-Id: I30bc3eb9eedcaaef67cccf8c2f29c6ed76c71e9a
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88251
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Pranava Y N <pranavayn@google.com>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
---
 src/soc/qualcomm/x1p42100/Kconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/src/soc/qualcomm/x1p42100/Kconfig b/src/soc/qualcomm/x1p42100/Kconfig
index 7aa6481581..cb32c2f8b3 100644
--- a/src/soc/qualcomm/x1p42100/Kconfig
+++ b/src/soc/qualcomm/x1p42100/Kconfig
@@ -8,6 +8,7 @@ config SOC_QUALCOMM_X1P42100
 	select ARCH_ROMSTAGE_ARMV8_64
 	select ARCH_VERSTAGE_ARMV8_64
 	select ARM64_USE_ARCH_TIMER
+	select ARM64_USE_ARM_TRUSTED_FIRMWARE
 	select CACHE_MRC_SETTINGS
 	select COMMONLIB_STORAGE
 	select COMMONLIB_STORAGE_SD

From 0c9204046aa9310e6f52f62ba4b9c820cde65156 Mon Sep 17 00:00:00 2001
From: Subrata Banik <subratabanik@google.com>
Date: Tue, 1 Jul 2025 15:09:54 +0000
Subject: [PATCH 1461/3886] mb/google/bluey: Update SPI flash vendor selection

This commit refactors the SPI flash vendor selection for Google Bluey
boards to accurately reflect the components used by each variant.

Previously, `SPI_FLASH_WINBOND` was unconditionally selected for
`BOARD_GOOGLE_BLUEY_COMMON`. This is incorrect as different Bluey
variants may use different SPI flash chips.

This change now specifically selects:
- `SPI_FLASH_MACRONIX` for `BOARD_GOOGLE_BLUEY`
- `SPI_FLASH_WINBOND` for `BOARD_GOOGLE_QUENBI`

This ensures that the correct SPI flash driver is enabled for each
specific board variant, as per underlying hardware design.

TEST=Able to build google/bluey.

Change-Id: I7deaed90a7f6533ed4fe9fd815715dabdaa561a3
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88267
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Pranava Y N <pranavayn@google.com>
---
 src/mainboard/google/bluey/Kconfig | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/src/mainboard/google/bluey/Kconfig b/src/mainboard/google/bluey/Kconfig
index 812b792797..21a1c410a4 100644
--- a/src/mainboard/google/bluey/Kconfig
+++ b/src/mainboard/google/bluey/Kconfig
@@ -8,7 +8,6 @@ config BOARD_GOOGLE_BLUEY_COMMON
 	select SOC_QUALCOMM_X1P42100
 	select SPI_FLASH
 	select SPI_FLASH_FORCE_4_BYTE_ADDR_MODE
-	select SPI_FLASH_WINBOND
 
 config BOARD_GOOGLE_BASEBOARD_BLUEY
 	def_bool n
@@ -18,12 +17,14 @@ config BOARD_GOOGLE_BLUEY
 	select BOARD_GOOGLE_BASEBOARD_BLUEY
 	select MAINBOARD_HAS_FINGERPRINT_VIA_USB
 	select MISSING_BOARD_RESET
+	select SPI_FLASH_MACRONIX
 
 config BOARD_GOOGLE_QUENBI
 	select BOARD_GOOGLE_BASEBOARD_BLUEY
 	select MAINBOARD_HAS_CHROME_EC
 	select MAINBOARD_HAS_FINGERPRINT_VIA_SPI
 	select MAINBOARD_HAS_GOOGLE_TPM
+	select SPI_FLASH_WINBOND
 
 if BOARD_GOOGLE_BLUEY_COMMON
 

From a90a7e0aedd4d38c3e36a4089fda190dd9993b15 Mon Sep 17 00:00:00 2001
From: Subrata Banik <subratabanik@google.com>
Date: Tue, 1 Jul 2025 15:22:02 +0000
Subject: [PATCH 1462/3886] mb/google/bluey: Specify ROM size per board variant

This commit refines the ROM size configuration for Google Bluey
mainboards by moving the `BOARD_ROMSIZE_KB_*` selection from the
common Kconfig to the specific board variants.

Previously, `BOARD_ROMSIZE_KB_65536` was selected for
`BOARD_GOOGLE_BLUEY_COMMON`. This blanket setting is inaccurate as
different Bluey-based boards utilize different sized ROMs.

With this change:
- `BOARD_GOOGLE_BLUEY` now selects `BOARD_ROMSIZE_KB_65536`.
- `BOARD_GOOGLE_QUENBI` now selects `BOARD_ROMSIZE_KB_32768`.

This ensures that each board variant has the correct ROM size
configured, preventing potential issues related to image size or
flash programming.

TEST=Able to verify that google/bluey AP FW image os 64MB and
google/quenbi AP FW is 32MB in size.

Change-Id: Ifcf75b310f08cbc4bbbd27ad7947df06da4f5d5a
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88268
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Pranava Y N <pranavayn@google.com>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
---
 src/mainboard/google/bluey/Kconfig | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/src/mainboard/google/bluey/Kconfig b/src/mainboard/google/bluey/Kconfig
index 21a1c410a4..356ec0705d 100644
--- a/src/mainboard/google/bluey/Kconfig
+++ b/src/mainboard/google/bluey/Kconfig
@@ -2,7 +2,6 @@
 
 config BOARD_GOOGLE_BLUEY_COMMON
 	def_bool n
-	select BOARD_ROMSIZE_KB_65536
 	select COMMON_CBFS_SPI_WRAPPER
 	select MAINBOARD_HAS_CHROMEOS
 	select SOC_QUALCOMM_X1P42100
@@ -15,12 +14,14 @@ config BOARD_GOOGLE_BASEBOARD_BLUEY
 
 config BOARD_GOOGLE_BLUEY
 	select BOARD_GOOGLE_BASEBOARD_BLUEY
+	select BOARD_ROMSIZE_KB_65536
 	select MAINBOARD_HAS_FINGERPRINT_VIA_USB
 	select MISSING_BOARD_RESET
 	select SPI_FLASH_MACRONIX
 
 config BOARD_GOOGLE_QUENBI
 	select BOARD_GOOGLE_BASEBOARD_BLUEY
+	select BOARD_ROMSIZE_KB_32768
 	select MAINBOARD_HAS_CHROME_EC
 	select MAINBOARD_HAS_FINGERPRINT_VIA_SPI
 	select MAINBOARD_HAS_GOOGLE_TPM

From 626c5364b87f9457b1673a43a3475c11cd9838c2 Mon Sep 17 00:00:00 2001
From: Elyes Haouas <ehaouas@noos.fr>
Date: Tue, 1 Jul 2025 18:56:58 +0200
Subject: [PATCH 1463/3886] tree: Use boolean for PcieRpSlotImplemented[]

Change-Id: I15b062a7225700988d5db8a0840d555dc2a1c353
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88269
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/asrock/imb-1222/devicetree.cb      |  6 +++---
 .../clevo/cml-u/variants/l140cu/devicetree.cb    |  6 +++---
 src/mainboard/erying/tgl/devicetree.cb           |  6 +++---
 .../drallion/variants/drallion/devicetree.cb     |  4 ++--
 .../hatch/variants/baseboard/devicetree.cb       |  4 ++--
 .../puff/variants/ambassador/overridetree.cb     |  4 ++--
 .../google/puff/variants/baseboard/devicetree.cb |  4 ++--
 .../google/puff/variants/dooly/overridetree.cb   |  2 +-
 .../google/puff/variants/duffy/overridetree.cb   |  4 ++--
 .../google/puff/variants/faffy/overridetree.cb   |  4 ++--
 .../google/puff/variants/genesis/overridetree.cb | 10 +++++-----
 .../google/puff/variants/kaisa/overridetree.cb   |  4 ++--
 .../puff/variants/moonbuggy/overridetree.cb      | 10 +++++-----
 .../google/puff/variants/noibat/overridetree.cb  |  4 ++--
 .../google/puff/variants/puff/overridetree.cb    |  4 ++--
 .../google/puff/variants/scout/overridetree.cb   |  8 ++++----
 .../google/puff/variants/wyvern/overridetree.cb  |  4 ++--
 .../google/sarien/variants/arcada/devicetree.cb  |  6 +++---
 .../google/sarien/variants/sarien/devicetree.cb  | 10 +++++-----
 .../volteer/variants/baseboard/devicetree.cb     |  6 +++---
 .../volteer/variants/voema/overridetree.cb       |  2 +-
 .../variants/cfl_h/overridetree.cb               |  6 +++---
 .../variants/cfl_s/overridetree.cb               | 16 ++++++++--------
 .../variants/cfl_u/overridetree.cb               |  6 +++---
 .../variants/cml_u/overridetree.cb               |  6 +++---
 .../variants/whl_u/overridetree.cb               |  6 +++---
 .../tglrvp/variants/tglrvp_up3/devicetree.cb     |  8 ++++----
 .../tglrvp/variants/tglrvp_up4/devicetree.cb     |  8 ++++----
 src/mainboard/lenovo/m920q/devicetree.cb         |  8 ++++----
 src/mainboard/prodrive/hermes/devicetree.cb      | 10 +++++-----
 .../variants/librem_14/overridetree.cb           |  6 +++---
 .../variants/librem_mini/overridetree.cb         |  4 ++--
 .../purism/librem_l1um_v2/devicetree.cb          |  4 ++--
 .../siemens/chili/variants/base/devicetree.cb    |  8 ++++----
 .../siemens/chili/variants/chili/devicetree.cb   | 10 +++++-----
 .../starlabs/starbook/variants/cml/devicetree.cb |  2 +-
 .../starlabs/starbook/variants/tgl/devicetree.cb |  2 +-
 src/mainboard/system76/addw1/devicetree.cb       | 10 +++++-----
 .../cml-u/variants/lemp9/overridetree.cb         |  8 ++++----
 src/mainboard/system76/gaze15/devicetree.cb      |  8 ++++----
 src/mainboard/system76/oryp6/devicetree.cb       | 12 ++++++------
 .../tgl-h/variants/gaze16-3050/overridetree.cb   |  4 ++--
 .../tgl-h/variants/gaze16-3060/overridetree.cb   |  4 ++--
 .../tgl-h/variants/oryp8/overridetree.cb         |  4 ++--
 .../tgl-u/variants/darp7/overridetree.cb         |  4 ++--
 .../tgl-u/variants/galp5/overridetree.cb         |  2 +-
 .../tgl-u/variants/lemp10/overridetree.cb        |  4 ++--
 src/soc/intel/alderlake/fsp_params.c             |  2 +-
 src/soc/intel/tigerlake/chip.h                   |  2 +-
 49 files changed, 143 insertions(+), 143 deletions(-)

diff --git a/src/mainboard/asrock/imb-1222/devicetree.cb b/src/mainboard/asrock/imb-1222/devicetree.cb
index 0a84b106bb..c26baeaa0f 100644
--- a/src/mainboard/asrock/imb-1222/devicetree.cb
+++ b/src/mainboard/asrock/imb-1222/devicetree.cb
@@ -224,7 +224,7 @@ chip soc/intel/cannonlake
 		end
 		device ref pcie_rp17 on # M.2 Key-M 2242/2260/2280 slot for SSD (PCIEx4)
 			register "PcieRpLtrEnable[16]" = "true"
-			register "PcieRpSlotImplemented[16]" = "1"
+			register "PcieRpSlotImplemented[16]" = "true"
 			register "PcieClkSrcUsage[7]" = "16"
 			register "PcieClkSrcClkReq[7]" = "7"
 			smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M.2/M 2242/2260/2280 (M2_KEYM1)" "SlotDataBusWidth4X"
@@ -235,14 +235,14 @@ chip soc/intel/cannonlake
 			register "PcieClkSrcClkReq[3]" = "3"
 		end
 		device ref pcie_rp6 on # M.2 Key-E 2230 slot for Wireless M.2 Key-E (PCIe x1)
-			register "PcieRpSlotImplemented[5]" = "1"
+			register "PcieRpSlotImplemented[5]" = "true"
 			register "PcieRpLtrEnable[5]" = "true"
 			register "PcieClkSrcUsage[5]" = "5"
 			register "PcieClkSrcClkReq[5]" = "5"
 			smbios_slot_desc "SlotTypeM2Socket1_SD" "SlotLengthOther" "M.2/E 2230 (M2_KEYE1)" "SlotDataBusWidth1X"
 		end
 		device ref pcie_rp7 on # M.2 Key-B 3042/3052 slot for 4G/5G modem (PCIe x1)
-			register "PcieRpSlotImplemented[6]" = "1"
+			register "PcieRpSlotImplemented[6]" = "true"
 			register "PcieRpLtrEnable[6]" = "true"
 			register "PcieClkSrcUsage[6]" = "6"
 			register "PcieClkSrcClkReq[6]" = "6"
diff --git a/src/mainboard/clevo/cml-u/variants/l140cu/devicetree.cb b/src/mainboard/clevo/cml-u/variants/l140cu/devicetree.cb
index 1dc9f1b8d9..fa9344e1b6 100644
--- a/src/mainboard/clevo/cml-u/variants/l140cu/devicetree.cb
+++ b/src/mainboard/clevo/cml-u/variants/l140cu/devicetree.cb
@@ -121,21 +121,21 @@ chip soc/intel/cannonlake
 			register "PcieRpLtrEnable[7]" = "true"
 			register "PcieClkSrcUsage[2]" = "7"
 			register "PcieClkSrcClkReq[2]" = "2"
-			register "PcieRpSlotImplemented[7]" = "1"
+			register "PcieRpSlotImplemented[7]" = "true"
 			smbios_slot_desc "SlotTypeM2Socket1_SD" "SlotLengthOther" "M.2/E 2230 (J_WLAN1)" "SlotDataBusWidth1X"
 		end
 		device ref pcie_rp9 on
 			register "PcieRpLtrEnable[8]" = "true"
 			register "PcieClkSrcUsage[4]" = "8"
 			register "PcieClkSrcClkReq[4]" = "4"
-			register "PcieRpSlotImplemented[8]" = "1"
+			register "PcieRpSlotImplemented[8]" = "true"
 			smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M.2/M 2280 (J_SSD2)" "SlotDataBusWidth4X"
 		end
 		device ref pcie_rp13 on
 			register "PcieRpLtrEnable[12]" = "true"
 			register "PcieClkSrcUsage[5]" = "12"
 			register "PcieClkSrcClkReq[5]" = "5"
-			register "PcieRpSlotImplemented[12]" = "1"
+			register "PcieRpSlotImplemented[12]" = "true"
 			smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M.2/M 2280 (J_SSD1)" "SlotDataBusWidth4X"
 		end
 		device ref lpc_espi on
diff --git a/src/mainboard/erying/tgl/devicetree.cb b/src/mainboard/erying/tgl/devicetree.cb
index 0a0a01be5c..c6cd68d1ae 100644
--- a/src/mainboard/erying/tgl/devicetree.cb
+++ b/src/mainboard/erying/tgl/devicetree.cb
@@ -109,13 +109,13 @@ chip soc/intel/tigerlake
 		end
 
 		device ref pcie_rp5 on		# PCH M.2 (Gen3)
-			register "PcieRpSlotImplemented[4]" = "1"
+			register "PcieRpSlotImplemented[4]" = "true"
 			register "PcieClkSrcUsage[4]" = "4"
 			register "PcieClkSrcClkReq[4]" = "PCIE_CLK_NOTUSED"
 		end
 
 		device ref pcie_rp9 on		# PCH NGFF (WiFi)
-			register "PcieRpSlotImplemented[8]" = "1"
+			register "PcieRpSlotImplemented[8]" = "true"
 			register "PcieClkSrcUsage[5]" = "8"
 			register "PcieClkSrcClkReq[5]" = "PCIE_CLK_NOTUSED"
 
@@ -127,7 +127,7 @@ chip soc/intel/tigerlake
 		end
 
 		device ref pcie_rp12 on		# PCH x1 (Gen3)
-			register "PcieRpSlotImplemented[11]" = "1"
+			register "PcieRpSlotImplemented[11]" = "true"
 			register "PcieClkSrcUsage[1]" = "11"
 			register "PcieClkSrcClkReq[1]" = "PCIE_CLK_NOTUSED"
 		end
diff --git a/src/mainboard/google/drallion/variants/drallion/devicetree.cb b/src/mainboard/google/drallion/variants/drallion/devicetree.cb
index b79c1cd1d7..1830dd3220 100644
--- a/src/mainboard/google/drallion/variants/drallion/devicetree.cb
+++ b/src/mainboard/google/drallion/variants/drallion/devicetree.cb
@@ -408,11 +408,11 @@ chip soc/intel/cannonlake
 		end
 		device ref pcie_rp9 on
 			smbios_slot_desc "SlotTypeM2Socket1_SD" "SlotLengthOther" "2230" "SlotDataBusWidth1X"
-			register "PcieRpSlotImplemented[8]" = "1"
+			register "PcieRpSlotImplemented[8]" = "true"
 		end
 		device ref pcie_rp13 on
 			smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "2280" "SlotDataBusWidth4X"
-			register "PcieRpSlotImplemented[12]" = "1"
+			register "PcieRpSlotImplemented[12]" = "true"
 		end
 		device ref uart0 on end
 		device ref lpc_espi on
diff --git a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb
index 0c4ebd7b65..5a1b7e2ca9 100644
--- a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb
+++ b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb
@@ -282,14 +282,14 @@ chip soc/intel/cannonlake
 		device ref sata		on end
 		device ref i2c4		on end
 		device ref pcie_rp9	on
-			register "PcieRpSlotImplemented[8]" = "1"
+			register "PcieRpSlotImplemented[8]" = "true"
 		end # (x4 NVMe)
 		device ref pcie_rp14	on
 			chip drivers/wifi/generic
 				register "wake" = "GPE0_DW1_01"
 				device generic 0 on  end
 			end
-			register "PcieRpSlotImplemented[13]" = "1"
+			register "PcieRpSlotImplemented[13]" = "true"
 		end # (x1 WiFi)
 		device ref uart0	on end
 		device ref gspi0	on
diff --git a/src/mainboard/google/puff/variants/ambassador/overridetree.cb b/src/mainboard/google/puff/variants/ambassador/overridetree.cb
index e2fc98b2fa..3339033df6 100644
--- a/src/mainboard/google/puff/variants/ambassador/overridetree.cb
+++ b/src/mainboard/google/puff/variants/ambassador/overridetree.cb
@@ -388,11 +388,11 @@ chip soc/intel/cannonlake
 				register "enable_aspm_l1_2" = "1"
 				device pci 00.0 on end
 			end
-			register "PcieRpSlotImplemented[6]" = "1"
+			register "PcieRpSlotImplemented[6]" = "true"
 		end
 		device ref pcie_rp11	on
 			# X2 NVMe
-			register "PcieRpSlotImplemented[10]" = "1"
+			register "PcieRpSlotImplemented[10]" = "true"
 		end
 	end
 
diff --git a/src/mainboard/google/puff/variants/baseboard/devicetree.cb b/src/mainboard/google/puff/variants/baseboard/devicetree.cb
index 2e851c8e39..090dc87be0 100644
--- a/src/mainboard/google/puff/variants/baseboard/devicetree.cb
+++ b/src/mainboard/google/puff/variants/baseboard/devicetree.cb
@@ -284,7 +284,7 @@ chip soc/intel/cannonlake
 		device ref sata		on end
 		device ref pcie_rp9	on
 			# X4 NVME
-			register "PcieRpSlotImplemented[8]" = "1"
+			register "PcieRpSlotImplemented[8]" = "true"
 		end
 		device ref pcie_rp14	on
 			# x4
@@ -292,7 +292,7 @@ chip soc/intel/cannonlake
 				register "wake" = "GPE0_DW1_01"
 				device generic 0 on  end
 			end
-			register "PcieRpSlotImplemented[13]" = "1"
+			register "PcieRpSlotImplemented[13]" = "true"
 		end
 		device ref uart0	on end
 		device ref gspi0	on
diff --git a/src/mainboard/google/puff/variants/dooly/overridetree.cb b/src/mainboard/google/puff/variants/dooly/overridetree.cb
index 4dd2865c88..e8095c6267 100644
--- a/src/mainboard/google/puff/variants/dooly/overridetree.cb
+++ b/src/mainboard/google/puff/variants/dooly/overridetree.cb
@@ -385,7 +385,7 @@ chip soc/intel/cannonlake
 		device ref emmc		on end
 		device ref pcie_rp11	on
 			# X2 NVMe
-			register "PcieRpSlotImplemented[10]" = "1"
+			register "PcieRpSlotImplemented[10]" = "true"
 		end
 		device ref hda		on
 			chip drivers/sof
diff --git a/src/mainboard/google/puff/variants/duffy/overridetree.cb b/src/mainboard/google/puff/variants/duffy/overridetree.cb
index ba06ff855d..eee3d48021 100644
--- a/src/mainboard/google/puff/variants/duffy/overridetree.cb
+++ b/src/mainboard/google/puff/variants/duffy/overridetree.cb
@@ -447,11 +447,11 @@ chip soc/intel/cannonlake
 				register "enable_aspm_l1_2" = "1"
 				device pci 00.0 on end
 			end
-			register "PcieRpSlotImplemented[6]" = "1"
+			register "PcieRpSlotImplemented[6]" = "true"
 		end
 		device ref pcie_rp11	on
 			# X2 NVMe
-			register "PcieRpSlotImplemented[10]" = "1"
+			register "PcieRpSlotImplemented[10]" = "true"
 		end
 	end
 
diff --git a/src/mainboard/google/puff/variants/faffy/overridetree.cb b/src/mainboard/google/puff/variants/faffy/overridetree.cb
index 840a9fdab2..a2f53df0b1 100644
--- a/src/mainboard/google/puff/variants/faffy/overridetree.cb
+++ b/src/mainboard/google/puff/variants/faffy/overridetree.cb
@@ -421,11 +421,11 @@ chip soc/intel/cannonlake
 				register "enable_aspm_l1_2" = "1"
 				device pci 00.0 on end
 			end
-			register "PcieRpSlotImplemented[6]" = "1"
+			register "PcieRpSlotImplemented[6]" = "true"
 		end
 		device ref pcie_rp11	on
 			# X2 NVMe
-			register "PcieRpSlotImplemented[10]" = "1"
+			register "PcieRpSlotImplemented[10]" = "true"
 		end
 	end
 
diff --git a/src/mainboard/google/puff/variants/genesis/overridetree.cb b/src/mainboard/google/puff/variants/genesis/overridetree.cb
index d11d7efbb9..a635cd2cb3 100644
--- a/src/mainboard/google/puff/variants/genesis/overridetree.cb
+++ b/src/mainboard/google/puff/variants/genesis/overridetree.cb
@@ -412,23 +412,23 @@ chip soc/intel/cannonlake
 		end
 		device ref pcie_rp8	on
 			# WLAN
-			register "PcieRpSlotImplemented[7]" = "1" # M.2 Slot
+			register "PcieRpSlotImplemented[7]" = "true" # M.2 Slot
 		end
 		device ref pcie_rp9	on
 			# TPU
-			register "PcieRpSlotImplemented[8]" = "1" # M.2 Slot
+			register "PcieRpSlotImplemented[8]" = "true" # M.2 Slot
 		end
 		device ref pcie_rp11	on
 			# TPU1
-			register "PcieRpSlotImplemented[10]" = "1" # M.2 Slot
+			register "PcieRpSlotImplemented[10]" = "true" # M.2 Slot
 		end
 		device ref pcie_rp12	on
 			# TPU0
-			register "PcieRpSlotImplemented[11]" = "1" # M.2 Slot
+			register "PcieRpSlotImplemented[11]" = "true" # M.2 Slot
 		end
 		device ref pcie_rp13	on
 			# X4 i350 NIC
-			register "PcieRpSlotImplemented[12]" = "0" # Built-in
+			register "PcieRpSlotImplemented[12]" = "false" # Built-in
 		end
 	end
 
diff --git a/src/mainboard/google/puff/variants/kaisa/overridetree.cb b/src/mainboard/google/puff/variants/kaisa/overridetree.cb
index 1193d6bf68..0b539a1a0b 100644
--- a/src/mainboard/google/puff/variants/kaisa/overridetree.cb
+++ b/src/mainboard/google/puff/variants/kaisa/overridetree.cb
@@ -447,11 +447,11 @@ chip soc/intel/cannonlake
 				register "enable_aspm_l1_2" = "1"
 				device pci 00.0 on end
 			end
-			register "PcieRpSlotImplemented[6]" = "1"
+			register "PcieRpSlotImplemented[6]" = "true"
 		end
 		device ref pcie_rp11	on
 			# X2 NVMe
-			register "PcieRpSlotImplemented[10]" = "1"
+			register "PcieRpSlotImplemented[10]" = "true"
 		end
 	end
 
diff --git a/src/mainboard/google/puff/variants/moonbuggy/overridetree.cb b/src/mainboard/google/puff/variants/moonbuggy/overridetree.cb
index 85a3c7fb16..d0c8b8de94 100644
--- a/src/mainboard/google/puff/variants/moonbuggy/overridetree.cb
+++ b/src/mainboard/google/puff/variants/moonbuggy/overridetree.cb
@@ -414,23 +414,23 @@ chip soc/intel/cannonlake
 		end
 		device ref pcie_rp8	on
 			# WLAN
-			register "PcieRpSlotImplemented[7]" = "1" # M.2 Slot
+			register "PcieRpSlotImplemented[7]" = "true" # M.2 Slot
 		end
 		device ref pcie_rp9	on
 			# TPU
-			register "PcieRpSlotImplemented[8]" = "1" # M.2 Slot
+			register "PcieRpSlotImplemented[8]" = "true" # M.2 Slot
 		end
 		device ref pcie_rp11	on
 			# TPU1
-			register "PcieRpSlotImplemented[10]" = "1" # M.2 Slot
+			register "PcieRpSlotImplemented[10]" = "true" # M.2 Slot
 		end
 		device ref pcie_rp12	on
 			# TPU0
-			register "PcieRpSlotImplemented[11]" = "1" # M.2 Slot
+			register "PcieRpSlotImplemented[11]" = "true" # M.2 Slot
 		end
 		device ref pcie_rp13	on
 			# X4 i350 NIC
-			register "PcieRpSlotImplemented[12]" = "0" # Built-in
+			register "PcieRpSlotImplemented[12]" = "false" # Built-in
 		end
 		device ref uart1	on end
 	end
diff --git a/src/mainboard/google/puff/variants/noibat/overridetree.cb b/src/mainboard/google/puff/variants/noibat/overridetree.cb
index 006f954a49..c5407bd0f2 100644
--- a/src/mainboard/google/puff/variants/noibat/overridetree.cb
+++ b/src/mainboard/google/puff/variants/noibat/overridetree.cb
@@ -358,11 +358,11 @@ chip soc/intel/cannonlake
 				register "enable_aspm_l1_2" = "1"
 				device pci 00.0 on end
 			end
-			register "PcieRpSlotImplemented[6]" = "1"
+			register "PcieRpSlotImplemented[6]" = "true"
 		end
 		device ref pcie_rp11	on
 			# X2 NVMe
-			register "PcieRpSlotImplemented[10]" = "1"
+			register "PcieRpSlotImplemented[10]" = "true"
 		end
 	end
 
diff --git a/src/mainboard/google/puff/variants/puff/overridetree.cb b/src/mainboard/google/puff/variants/puff/overridetree.cb
index 43402ab192..beb53ef4db 100644
--- a/src/mainboard/google/puff/variants/puff/overridetree.cb
+++ b/src/mainboard/google/puff/variants/puff/overridetree.cb
@@ -382,11 +382,11 @@ chip soc/intel/cannonlake
 				register "enable_aspm_l1_2" = "1"
 				device pci 00.0 on end
 			end
-			register "PcieRpSlotImplemented[6]" = "1"
+			register "PcieRpSlotImplemented[6]" = "true"
 		end
 		device ref pcie_rp11	on
 			# X2 NVMe
-			register "PcieRpSlotImplemented[10]" = "1"
+			register "PcieRpSlotImplemented[10]" = "true"
 		end
 	end
 
diff --git a/src/mainboard/google/puff/variants/scout/overridetree.cb b/src/mainboard/google/puff/variants/scout/overridetree.cb
index 8c593d5b71..50dcdaf604 100644
--- a/src/mainboard/google/puff/variants/scout/overridetree.cb
+++ b/src/mainboard/google/puff/variants/scout/overridetree.cb
@@ -397,19 +397,19 @@ chip soc/intel/cannonlake
 		end
 		device ref pcie_rp8	on
 			# WLAN
-			register "PcieRpSlotImplemented[7]" = "1" # M.2 Slot
+			register "PcieRpSlotImplemented[7]" = "true" # M.2 Slot
 		end
 		device ref pcie_rp9	on
 			# SSD
-			register "PcieRpSlotImplemented[8]" = "1" # M.2 Slot
+			register "PcieRpSlotImplemented[8]" = "true" # M.2 Slot
 		end
 		device ref pcie_rp13	on
 			# TPU0
-			register "PcieRpSlotImplemented[12]" = "1" # M.2 Slot
+			register "PcieRpSlotImplemented[12]" = "true" # M.2 Slot
 		end
 		device ref pcie_rp14	on
 			# TPU1
-			register "PcieRpSlotImplemented[13]" = "1" # M.2 Slot
+			register "PcieRpSlotImplemented[13]" = "true" # M.2 Slot
 		end
 		device ref uart1	on end
 	end
diff --git a/src/mainboard/google/puff/variants/wyvern/overridetree.cb b/src/mainboard/google/puff/variants/wyvern/overridetree.cb
index e38a0c741e..1373928a92 100644
--- a/src/mainboard/google/puff/variants/wyvern/overridetree.cb
+++ b/src/mainboard/google/puff/variants/wyvern/overridetree.cb
@@ -383,11 +383,11 @@ chip soc/intel/cannonlake
 				register "enable_aspm_l1_2" = "1"
 				device ref system_agent on end
 			end
-			register "PcieRpSlotImplemented[6]" = "1"
+			register "PcieRpSlotImplemented[6]" = "true"
 		end
 		device ref pcie_rp11	on
 			# X2 NVMe
-			register "PcieRpSlotImplemented[10]" = "1"
+			register "PcieRpSlotImplemented[10]" = "true"
 		end
 	end
 
diff --git a/src/mainboard/google/sarien/variants/arcada/devicetree.cb b/src/mainboard/google/sarien/variants/arcada/devicetree.cb
index 624856ce45..1c8f8a40c2 100644
--- a/src/mainboard/google/sarien/variants/arcada/devicetree.cb
+++ b/src/mainboard/google/sarien/variants/arcada/devicetree.cb
@@ -338,10 +338,10 @@ chip soc/intel/cannonlake
 		device ref uart2 on  end
 		device ref pcie_rp10 on
 			smbios_slot_desc "SlotTypeM2Socket1_SD" "SlotLengthOther" "2230" "SlotDataBusWidth1X"
-			register "PcieRpSlotImplemented[9]" = "1"
+			register "PcieRpSlotImplemented[9]" = "true"
 		end
 		device ref pcie_rp11 on
-			register "PcieRpSlotImplemented[10]" = "1"
+			register "PcieRpSlotImplemented[10]" = "true"
 		end
 		device ref pcie_rp13 on
 			# x4 lanes
@@ -350,7 +350,7 @@ chip soc/intel/cannonlake
 				device pci 00.0 on end
 			end
 			smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "2280" "SlotDataBusWidth4X"
-			register "PcieRpSlotImplemented[12]" = "1"
+			register "PcieRpSlotImplemented[12]" = "true"
 		end
 		device ref lpc_espi on
 			chip ec/google/wilco
diff --git a/src/mainboard/google/sarien/variants/sarien/devicetree.cb b/src/mainboard/google/sarien/variants/sarien/devicetree.cb
index a90c7b2b98..7bc72d67a0 100644
--- a/src/mainboard/google/sarien/variants/sarien/devicetree.cb
+++ b/src/mainboard/google/sarien/variants/sarien/devicetree.cb
@@ -365,10 +365,10 @@ chip soc/intel/cannonlake
 		device ref uart2 on  end
 		device ref pcie_rp1 on
 			# USB
-			register "PcieRpSlotImplemented[0]" = "1"
+			register "PcieRpSlotImplemented[0]" = "true"
 		end
 		device ref pcie_rp8 on
-			register "PcieRpSlotImplemented[7]" = "1"
+			register "PcieRpSlotImplemented[7]" = "true"
 		end
 		device ref pcie_rp9 on
 			chip drivers/generic/bayhub
@@ -376,10 +376,10 @@ chip soc/intel/cannonlake
 				device pci 00.0 on end
 			end
 			smbios_slot_desc "SlotTypeM2Socket1_SD" "SlotLengthOther" "2230" "SlotDataBusWidth1X"
-			register "PcieRpSlotImplemented[8]" = "1"
+			register "PcieRpSlotImplemented[8]" = "true"
 		end
 		device ref pcie_rp10 on
-			register "PcieRpSlotImplemented[9]" = "1"
+			register "PcieRpSlotImplemented[9]" = "true"
 		end
 		device ref pcie_rp13 on
 			# x4 lanes
@@ -388,7 +388,7 @@ chip soc/intel/cannonlake
 				device pci 00.0 on end
 			end
 			smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "2280" "SlotDataBusWidth4X"
-			register "PcieRpSlotImplemented[12]" = "1"
+			register "PcieRpSlotImplemented[12]" = "true"
 		end
 		device ref lpc_espi on
 			chip ec/google/wilco
diff --git a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb
index 132d7cec6b..c200d88f2f 100644
--- a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb
+++ b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb
@@ -428,7 +428,7 @@ chip soc/intel/tigerlake
 			register "PcieRpLtrEnable[6]" = "true"
 			register "PcieClkSrcUsage[1]" = "6"
 			register "PcieClkSrcClkReq[1]" = "1"
-			register "PcieRpSlotImplemented[6]" = "1"
+			register "PcieRpSlotImplemented[6]" = "true"
 		end
 		device ref pcie_rp8 on
 			# SD Card PCIE 8 using clk 3
@@ -467,13 +467,13 @@ chip soc/intel/tigerlake
 			register "PcieRpLtrEnable[8]" = "true"
 			register "PcieClkSrcUsage[0]" = "8"
 			register "PcieClkSrcClkReq[0]" = "0"
-			register "PcieRpSlotImplemented[8]" = "1"
+			register "PcieRpSlotImplemented[8]" = "true"
 		end
 		device ref pcie_rp11 on
 			# Optane PCIE 11 using clk 0
 			register "PcieRpLtrEnable[10]" = "true"
 			register "HybridStorageMode" = "0"
-			register "PcieRpSlotImplemented[10]" = "1"
+			register "PcieRpSlotImplemented[10]" = "true"
 		end
 		device ref uart0 on end
 		device ref gspi0 on
diff --git a/src/mainboard/google/volteer/variants/voema/overridetree.cb b/src/mainboard/google/volteer/variants/voema/overridetree.cb
index abcc64afb1..bbf51356ac 100644
--- a/src/mainboard/google/volteer/variants/voema/overridetree.cb
+++ b/src/mainboard/google/volteer/variants/voema/overridetree.cb
@@ -92,7 +92,7 @@ chip soc/intel/tigerlake
 			# Disable WLAN PCIE 7
 			register "PcieRpLtrEnable[6]" = "false"
 			register "PcieClkSrcUsage[1]" = "PCIE_CLK_NOTUSED"
-			register "PcieRpSlotImplemented[6]" = "1"
+			register "PcieRpSlotImplemented[6]" = "true"
 		end
 		device ref pcie_rp8 off
 			# Disable SD Card PCIE 8
diff --git a/src/mainboard/intel/coffeelake_rvp/variants/cfl_h/overridetree.cb b/src/mainboard/intel/coffeelake_rvp/variants/cfl_h/overridetree.cb
index d36f9e22a4..5449cc599e 100644
--- a/src/mainboard/intel/coffeelake_rvp/variants/cfl_h/overridetree.cb
+++ b/src/mainboard/intel/coffeelake_rvp/variants/cfl_h/overridetree.cb
@@ -67,13 +67,13 @@ chip soc/intel/cannonlake
 		device ref uart2 on  end
 		device ref emmc on  end
 		device ref pcie_rp1 on	# x4 SLOT1
-			register "PcieRpSlotImplemented[0]" = "1"
+			register "PcieRpSlotImplemented[0]" = "true"
 		end
 		device ref pcie_rp5 on	# x1 SLOT2/LAN
-			register "PcieRpSlotImplemented[4]" = "1"
+			register "PcieRpSlotImplemented[4]" = "true"
 		end
 		device ref pcie_rp9 on
-			register "PcieRpSlotImplemented[8]" = "1"
+			register "PcieRpSlotImplemented[8]" = "true"
 		end
 		device ref gbe on  end
 	end
diff --git a/src/mainboard/intel/coffeelake_rvp/variants/cfl_s/overridetree.cb b/src/mainboard/intel/coffeelake_rvp/variants/cfl_s/overridetree.cb
index 607eb6a371..ec92fe76bb 100644
--- a/src/mainboard/intel/coffeelake_rvp/variants/cfl_s/overridetree.cb
+++ b/src/mainboard/intel/coffeelake_rvp/variants/cfl_s/overridetree.cb
@@ -77,28 +77,28 @@ chip soc/intel/cannonlake
 		device ref uart2 on  end
 		device ref emmc on  end
 		device ref pcie_rp1 on
-			register "PcieRpSlotImplemented[0]" = "1"
+			register "PcieRpSlotImplemented[0]" = "true"
 		end
 		device ref pcie_rp5 on
-			register "PcieRpSlotImplemented[4]" = "1"
+			register "PcieRpSlotImplemented[4]" = "true"
 		end
 		device ref pcie_rp9 on	# x4 SLOT 1
-			register "PcieRpSlotImplemented[8]" = "1"
+			register "PcieRpSlotImplemented[8]" = "true"
 		end
 		device ref pcie_rp17 on
-			register "PcieRpSlotImplemented[16]" = "1"
+			register "PcieRpSlotImplemented[16]" = "true"
 		end
 		device ref pcie_rp18 on
-			register "PcieRpSlotImplemented[17]" = "1"
+			register "PcieRpSlotImplemented[17]" = "true"
 		end
 		device ref pcie_rp19 on
-			register "PcieRpSlotImplemented[18]" = "1"
+			register "PcieRpSlotImplemented[18]" = "true"
 		end
 		device ref pcie_rp20 on
-			register "PcieRpSlotImplemented[19]" = "1"
+			register "PcieRpSlotImplemented[19]" = "true"
 		end
 		device ref pcie_rp21 on	# x4 SLOT 2
-			register "PcieRpSlotImplemented[20]" = "1"
+			register "PcieRpSlotImplemented[20]" = "true"
 		end
 		device ref gbe on  end
 	end
diff --git a/src/mainboard/intel/coffeelake_rvp/variants/cfl_u/overridetree.cb b/src/mainboard/intel/coffeelake_rvp/variants/cfl_u/overridetree.cb
index 908632093c..00407f3017 100644
--- a/src/mainboard/intel/coffeelake_rvp/variants/cfl_u/overridetree.cb
+++ b/src/mainboard/intel/coffeelake_rvp/variants/cfl_u/overridetree.cb
@@ -61,13 +61,13 @@ chip soc/intel/cannonlake
 		device ref uart2 on  end
 		device ref emmc on  end
 		device ref pcie_rp1 on	# x4 SLOT1
-			register "PcieRpSlotImplemented[0]" = "1"
+			register "PcieRpSlotImplemented[0]" = "true"
 		end
 		device ref pcie_rp5 on	# x1 SLOT2/LAN
-			register "PcieRpSlotImplemented[4]" = "1"
+			register "PcieRpSlotImplemented[4]" = "true"
 		end
 		device ref pcie_rp9 on
-			register "PcieRpSlotImplemented[8]" = "1"
+			register "PcieRpSlotImplemented[8]" = "true"
 		end
 	end
 end
diff --git a/src/mainboard/intel/coffeelake_rvp/variants/cml_u/overridetree.cb b/src/mainboard/intel/coffeelake_rvp/variants/cml_u/overridetree.cb
index a14e9910c1..fb2e8fd4d2 100644
--- a/src/mainboard/intel/coffeelake_rvp/variants/cml_u/overridetree.cb
+++ b/src/mainboard/intel/coffeelake_rvp/variants/cml_u/overridetree.cb
@@ -73,13 +73,13 @@ chip soc/intel/cannonlake
 		device ref uart2 on  end
 		device ref emmc on  end
 		device ref pcie_rp1 on	# x4 SLOT1
-			register "PcieRpSlotImplemented[0]" = "1"
+			register "PcieRpSlotImplemented[0]" = "true"
 		end
 		device ref pcie_rp5 on	# x1 SLOT2/LAN
-			register "PcieRpSlotImplemented[4]" = "1"
+			register "PcieRpSlotImplemented[4]" = "true"
 		end
 		device ref pcie_rp9 on
-			register "PcieRpSlotImplemented[8]" = "1"
+			register "PcieRpSlotImplemented[8]" = "true"
 		end
 		device ref gbe on  end
 	end
diff --git a/src/mainboard/intel/coffeelake_rvp/variants/whl_u/overridetree.cb b/src/mainboard/intel/coffeelake_rvp/variants/whl_u/overridetree.cb
index ded8e72c23..3885d89ff4 100644
--- a/src/mainboard/intel/coffeelake_rvp/variants/whl_u/overridetree.cb
+++ b/src/mainboard/intel/coffeelake_rvp/variants/whl_u/overridetree.cb
@@ -57,13 +57,13 @@ chip soc/intel/cannonlake
 		device ref uart2 on  end
 		device ref emmc on  end
 		device ref pcie_rp1 on	# x4 SLOT1
-			register "PcieRpSlotImplemented[0]" = "1"
+			register "PcieRpSlotImplemented[0]" = "true"
 		end
 		device ref pcie_rp5 on	# x1 SLOT2/LAN
-			register "PcieRpSlotImplemented[4]" = "1"
+			register "PcieRpSlotImplemented[4]" = "true"
 		end
 		device ref pcie_rp9 on
-			register "PcieRpSlotImplemented[8]" = "1"
+			register "PcieRpSlotImplemented[8]" = "true"
 		end
 		device ref gbe on  end
 	end
diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb
index 032e80efc6..00450dea11 100644
--- a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb
+++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb
@@ -242,13 +242,13 @@ chip soc/intel/tigerlake
 		device ref pcie_rp1 off end
 		device ref pcie_rp2 off end
 		device ref pcie_rp3 on
-			register "PcieRpSlotImplemented[2]" = "1"
+			register "PcieRpSlotImplemented[2]" = "true"
 			register "PcieRpLtrEnable[2]" = "true"
 			register "PcieClkSrcUsage[1]" = "0x2"
 			register "PcieClkSrcClkReq[1]" = "1"
 		end
 		device ref pcie_rp4 on
-			register "PcieRpSlotImplemented[3]" = "1"
+			register "PcieRpSlotImplemented[3]" = "true"
 			register "PcieRpLtrEnable[3]" = "true"
 			register "PcieClkSrcUsage[2]" = "0x3"
 			register "PcieClkSrcClkReq[2]" = "2"
@@ -263,14 +263,14 @@ chip soc/intel/tigerlake
 		device ref pcie_rp7 off end
 		device ref pcie_rp8 off end
 		device ref pcie_rp9 on
-			register "PcieRpSlotImplemented[8]" = "1"
+			register "PcieRpSlotImplemented[8]" = "true"
 			register "PcieRpLtrEnable[8]" = "true"
 			register "PcieClkSrcUsage[3]" = "0x8"
 			register "PcieClkSrcClkReq[3]" = "3"
 		end
 		device ref pcie_rp10 off end
 		device ref pcie_rp11 on
-			register "PcieRpSlotImplemented[10]" = "1"
+			register "PcieRpSlotImplemented[10]" = "true"
 			register "PcieRpLtrEnable[10]" = "true"
 		end
 		device ref pcie_rp12 off end
diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb
index 720e40f438..feaf9dc26c 100644
--- a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb
+++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb
@@ -244,14 +244,14 @@ chip soc/intel/tigerlake
 		device ref pcie_rp1 off end
 		device ref pcie_rp2 off end
 		device ref pcie_rp3 on
-			register "PcieRpSlotImplemented[2]" = "1"
+			register "PcieRpSlotImplemented[2]" = "true"
 			register "PcieRpLtrEnable[2]" = "true"
 			register "PcieClkSrcUsage[1]" = "0x2"
 			register "PcieClkSrcClkReq[1]" = "1"
 		end
 
 		device ref pcie_rp4 on
-			register "PcieRpSlotImplemented[3]" = "1"
+			register "PcieRpSlotImplemented[3]" = "true"
 			register "PcieRpLtrEnable[3]" = "true"
 			register "PcieClkSrcUsage[2]" = "0x3"
 			register "PcieClkSrcClkReq[2]" = "2"
@@ -266,14 +266,14 @@ chip soc/intel/tigerlake
 		device ref pcie_rp7 off end
 		device ref pcie_rp8 off end
 		device ref pcie_rp9 on
-			register "PcieRpSlotImplemented[8]" = "1"
+			register "PcieRpSlotImplemented[8]" = "true"
 			register "PcieRpLtrEnable[8]" = "true"
 			register "PcieClkSrcUsage[3]" = "0x8"
 			register "PcieClkSrcClkReq[3]" = "3"
 		end
 		device ref pcie_rp10 off end
 		device ref pcie_rp11 on
-			register "PcieRpSlotImplemented[10]" = "1"
+			register "PcieRpSlotImplemented[10]" = "true"
 			register "PcieRpLtrEnable[10]" = "true"
 		end
 		device ref pcie_rp12 off end
diff --git a/src/mainboard/lenovo/m920q/devicetree.cb b/src/mainboard/lenovo/m920q/devicetree.cb
index 87e11fff62..9e704b4471 100644
--- a/src/mainboard/lenovo/m920q/devicetree.cb
+++ b/src/mainboard/lenovo/m920q/devicetree.cb
@@ -67,25 +67,25 @@ chip soc/intel/cannonlake
 		end
 
 		device ref pcie_rp6	on # WLAN
-			register "PcieRpSlotImplemented[5]"	= "1"
+			register "PcieRpSlotImplemented[5]"	= "true"
 			register "PcieClkSrcUsage[3]"		= "5"
 			register "PcieClkSrcClkReq[3]"		= "3"
 		end
 
 		device ref pcie_rp9	on # PCIe x4
-			register "PcieRpSlotImplemented[8]"	= "1"
+			register "PcieRpSlotImplemented[8]"	= "true"
 			register "PcieClkSrcUsage[2]"		= "8"
 			register "PcieClkSrcClkReq[2]"		= "2"
 		end
 
 		device ref pcie_rp17 on # M.2 SSD #2
-			register "PcieRpSlotImplemented[16]"	= "1"
+			register "PcieRpSlotImplemented[16]"	= "true"
 			register "PcieClkSrcUsage[10]"		= "16"
 			register "PcieClkSrcClkReq[10]"		= "10"
 		end
 
 		device ref pcie_rp21 on # M.2 SSD #1
-			register "PcieRpSlotImplemented[20]"	= "1"
+			register "PcieRpSlotImplemented[20]"	= "true"
 			register "PcieClkSrcUsage[4]"		= "20"
 			register "PcieClkSrcClkReq[4]"		= "4"
 		end
diff --git a/src/mainboard/prodrive/hermes/devicetree.cb b/src/mainboard/prodrive/hermes/devicetree.cb
index aaa8e53d9c..9fb6780cb5 100644
--- a/src/mainboard/prodrive/hermes/devicetree.cb
+++ b/src/mainboard/prodrive/hermes/devicetree.cb
@@ -172,7 +172,7 @@ chip soc/intel/cannonlake
 		device ref pcie_rp21 on
 			smbios_slot_desc "SlotTypePciExpressGen3X16" "SlotLengthOther" "SLOT1" "SlotDataBusWidth4X"
 			register "PcieRpLtrEnable[20]" = "true"
-			register "PcieRpSlotImplemented[20]" = "1"
+			register "PcieRpSlotImplemented[20]" = "true"
 			register "PcieRpMaxPayload[20]" = "RpMaxPayload_256"
 			register "PcieRpAdvancedErrorReporting[20]" = "1"
 			register "PcieRpAspm[20]" = "AspmDisabled"
@@ -180,7 +180,7 @@ chip soc/intel/cannonlake
 		device ref pcie_rp1 on
 			smbios_slot_desc "SlotTypePciExpressGen3X16" "SlotLengthOther" "SLOT3" "SlotDataBusWidth4X"
 			register "PcieRpLtrEnable[0]" = "true"
-			register "PcieRpSlotImplemented[0]" = "1"
+			register "PcieRpSlotImplemented[0]" = "true"
 			register "PcieRpMaxPayload[0]" = "RpMaxPayload_256"
 			register "PcieRpAdvancedErrorReporting[0]" = "1"
 			register "PcieRpAspm[0]" = "AspmDisabled"
@@ -212,7 +212,7 @@ chip soc/intel/cannonlake
 		device ref pcie_rp9 on
 			smbios_slot_desc "SlotTypePciExpressGen3X16" "SlotLengthOther" "M2 M" "SlotDataBusWidth4X"
 			register "PcieRpLtrEnable[8]" = "true"
-			register "PcieRpSlotImplemented[8]" = "1"
+			register "PcieRpSlotImplemented[8]" = "true"
 		end
 		device ref pcie_rp14 on	# PHY 0
 			register "PcieRpLtrEnable[13]" = "true"
@@ -225,12 +225,12 @@ chip soc/intel/cannonlake
 				device pci 00.0 on end  # Aspeed 2500 VGA
 			end
 			register "PcieRpLtrEnable[14]" = "true"
-			register "PcieRpSlotImplemented[14]" = "1"
+			register "PcieRpSlotImplemented[14]" = "true"
 		end
 		device ref pcie_rp16 on	# M.2 E/CNVi
 			# Disabled when CNVi is present
 			register "PcieRpLtrEnable[15]" = "true"
-			register "PcieRpSlotImplemented[15]" = "1"
+			register "PcieRpSlotImplemented[15]" = "true"
 		end
 		device ref uart0 on  end
 		device ref uart1 on  end
diff --git a/src/mainboard/purism/librem_cnl/variants/librem_14/overridetree.cb b/src/mainboard/purism/librem_cnl/variants/librem_14/overridetree.cb
index 6bd2eb0f8f..af1dddd96a 100644
--- a/src/mainboard/purism/librem_cnl/variants/librem_14/overridetree.cb
+++ b/src/mainboard/purism/librem_cnl/variants/librem_14/overridetree.cb
@@ -125,7 +125,7 @@ chip soc/intel/cannonlake
 			register "SataPortsDevSlp[2]" = "1"
 		end
 		device ref pcie_rp7 on	# x1 M.2/E 2230 (WLAN)
-			register "PcieRpSlotImplemented[6]" = "1"
+			register "PcieRpSlotImplemented[6]" = "true"
 			register "PcieRpLtrEnable[6]" = "true"
 			register "PcieRpHotPlug[6]" = "1"
 			register "PcieClkSrcUsage[2]" = "6"
@@ -138,14 +138,14 @@ chip soc/intel/cannonlake
 			register "PcieClkSrcClkReq[3]" = "3"
 		end
 		device ref pcie_rp9 on	# x4 M.2/M 2280 (NVMe)
-			register "PcieRpSlotImplemented[8]" = "1"
+			register "PcieRpSlotImplemented[8]" = "true"
 			register "PcieRpLtrEnable[8]" = "true"
 			register "PcieClkSrcUsage[0]" = "8"
 			register "PcieClkSrcClkReq[0]" = "0"
 			smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M.2/M 2280" "SlotDataBusWidth4X"
 		end
 		device ref pcie_rp13 on	# x4 M.2/M 2280 (NVMe)
-			register "PcieRpSlotImplemented[12]" = "1"
+			register "PcieRpSlotImplemented[12]" = "true"
 			register "PcieRpLtrEnable[12]" = "true"
 			register "PcieClkSrcUsage[1]" = "12"
 			register "PcieClkSrcClkReq[1]" = "1"
diff --git a/src/mainboard/purism/librem_cnl/variants/librem_mini/overridetree.cb b/src/mainboard/purism/librem_cnl/variants/librem_mini/overridetree.cb
index 036a82e366..42105e12e0 100644
--- a/src/mainboard/purism/librem_cnl/variants/librem_mini/overridetree.cb
+++ b/src/mainboard/purism/librem_cnl/variants/librem_mini/overridetree.cb
@@ -117,7 +117,7 @@ chip soc/intel/cannonlake
 			register "satapwroptimize" = "1"
 		end
 		device ref pcie_rp8 on	# x1 M.2/E 2230 (WLAN)
-			register "PcieRpSlotImplemented[7]" = "1"
+			register "PcieRpSlotImplemented[7]" = "true"
 			register "PcieRpLtrEnable[7]" = "true"
 			# ClkSrcUsage must be set to free-run since SRCCLKREQ2 is NC
 			register "PcieClkSrcUsage[2]" = "0x80"
@@ -129,7 +129,7 @@ chip soc/intel/cannonlake
 			register "PcieClkSrcClkReq[3]" = "3"
 		end
 		device ref pcie_rp13 on	# x4 M.2/M 2280 (NVMe)
-			register "PcieRpSlotImplemented[12]" = "1"
+			register "PcieRpSlotImplemented[12]" = "true"
 			register "PcieRpLtrEnable[12]" = "true"
 			register "PcieClkSrcUsage[1]" = "12"
 			register "PcieClkSrcClkReq[1]" = "1"
diff --git a/src/mainboard/purism/librem_l1um_v2/devicetree.cb b/src/mainboard/purism/librem_l1um_v2/devicetree.cb
index e7c7fea41d..9c6fffae8b 100644
--- a/src/mainboard/purism/librem_l1um_v2/devicetree.cb
+++ b/src/mainboard/purism/librem_l1um_v2/devicetree.cb
@@ -209,13 +209,13 @@ chip soc/intel/cannonlake
 			register "SataPortsHotPlug[7]" = "1"
 		end
 		device ref pcie_rp21 on
-			register "PcieRpSlotImplemented[20]" = "1"
+			register "PcieRpSlotImplemented[20]" = "true"
 			register "PcieRpLtrEnable[20]" = "true"
 			register "PcieClkSrcUsage[10]" = "20"
 			smbios_slot_desc "SlotTypePciExpressGen3X4" "SlotLengthOther" "PCIE5" "SlotDataBusWidth4X"
 		end
 		device ref pcie_rp1 on
-			register "PcieRpSlotImplemented[0]" = "1"
+			register "PcieRpSlotImplemented[0]" = "true"
 			register "PcieRpLtrEnable[0]" = "true"
 			register "PcieClkSrcUsage[1]" = "0x80"
 			smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M2_1" "SlotDataBusWidth4X"
diff --git a/src/mainboard/siemens/chili/variants/base/devicetree.cb b/src/mainboard/siemens/chili/variants/base/devicetree.cb
index fb39040008..81c662ad0a 100644
--- a/src/mainboard/siemens/chili/variants/base/devicetree.cb
+++ b/src/mainboard/siemens/chili/variants/base/devicetree.cb
@@ -40,22 +40,22 @@ chip soc/intel/cannonlake
 			device pci 00.0 on end	# x1 i219
 			register "PcieClkSrcUsage[4]" = "0x70"
 			register "PcieClkSrcClkReq[4]" = "4"
-			register "PcieRpSlotImplemented[4]" = "0"
+			register "PcieRpSlotImplemented[4]" = "false"
 		end
 		device ref pcie_rp6		on
 			device pci 00.0 on end	# x1 i210
 			register "PcieClkSrcUsage[5]" = "5"
 			register "PcieClkSrcClkReq[5]" = "5"
-			register "PcieRpSlotImplemented[5]" = "0"
+			register "PcieRpSlotImplemented[5]" = "false"
 		end
 		device ref pcie_rp7		on
-			register "PcieRpSlotImplemented[6]" = "1"
+			register "PcieRpSlotImplemented[6]" = "true"
 			smbios_slot_desc "SlotTypeM2Socket1_SD" "SlotLengthOther" "M.2/E 2230" "SlotDataBusWidth1X"
 		end
 		device ref pcie_rp17		on
 			register "PcieClkSrcUsage[7]" = "16"
 			register "PcieClkSrcClkReq[7]" = "7"
-			register "PcieRpSlotImplemented[16]" = "1"
+			register "PcieRpSlotImplemented[16]" = "true"
 			smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M.2/M 2280" "SlotDataBusWidth4X"
 		end
 		device ref lpc_espi		on
diff --git a/src/mainboard/siemens/chili/variants/chili/devicetree.cb b/src/mainboard/siemens/chili/variants/chili/devicetree.cb
index 794db85bc0..160c531277 100644
--- a/src/mainboard/siemens/chili/variants/chili/devicetree.cb
+++ b/src/mainboard/siemens/chili/variants/chili/devicetree.cb
@@ -87,30 +87,30 @@ chip soc/intel/cannonlake
 		device ref pcie_rp5		on
 			register "PcieClkSrcUsage[4]" = "4"
 			register "PcieClkSrcClkReq[4]" = "4"
-			register "PcieRpSlotImplemented[4]" = "1"
+			register "PcieRpSlotImplemented[4]" = "true"
 		end
 		device ref pcie_rp6		on
 			device pci 00.0 on end	# i210 (x1)
 			register "PcieClkSrcUsage[5]" = "5"
 			register "PcieClkSrcClkReq[5]" = "5"
-			register "PcieRpSlotImplemented[5]" = "0"
+			register "PcieRpSlotImplemented[5]" = "false"
 		end
 		device ref pcie_rp7		on
 			device pci 00.0 on end	# VL805 Front Rack/UIB (x1)
 			register "PcieClkSrcUsage[1]" = "6"
 			register "PcieClkSrcClkReq[1]" = "1"
-			register "PcieRpSlotImplemented[6]" = "0"
+			register "PcieRpSlotImplemented[6]" = "false"
 		end
 		device ref pcie_rp8		on
 			device pci 00.0 on end	# VL805 Back MB (x1)
 			register "PcieClkSrcUsage[0]" = "7"
 			register "PcieClkSrcClkReq[0]" = "0"
-			register "PcieRpSlotImplemented[7]" = "0"
+			register "PcieRpSlotImplemented[7]" = "false"
 		end
 		device ref pcie_rp17		on
 			register "PcieClkSrcUsage[7]" = "16"
 			register "PcieClkSrcClkReq[7]" = "7"
-			register "PcieRpSlotImplemented[16]" = "1"
+			register "PcieRpSlotImplemented[16]" = "true"
 			smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "2280" "SlotDataBusWidth4X"
 		end
 		device ref uart0		on  end
diff --git a/src/mainboard/starlabs/starbook/variants/cml/devicetree.cb b/src/mainboard/starlabs/starbook/variants/cml/devicetree.cb
index 0fb641be36..900c504e3d 100644
--- a/src/mainboard/starlabs/starbook/variants/cml/devicetree.cb
+++ b/src/mainboard/starlabs/starbook/variants/cml/devicetree.cb
@@ -161,7 +161,7 @@ chip soc/intel/cannonlake
 		device ref i2c4 on  end
 		device ref uart2 on  end
 		device ref pcie_rp9 on						# SSD x4
-			register "PcieRpSlotImplemented[8]"	= "1"
+			register "PcieRpSlotImplemented[8]"	= "true"
 			register "PcieRpLtrEnable[8]"		= "true"
 			register "PcieClkSrcUsage[1]"		= "0x08"
 			register "PcieClkSrcClkReq[1]"		= "1"
diff --git a/src/mainboard/starlabs/starbook/variants/tgl/devicetree.cb b/src/mainboard/starlabs/starbook/variants/tgl/devicetree.cb
index 3808aca17b..16df1ef5c6 100644
--- a/src/mainboard/starlabs/starbook/variants/tgl/devicetree.cb
+++ b/src/mainboard/starlabs/starbook/variants/tgl/devicetree.cb
@@ -182,7 +182,7 @@ chip soc/intel/tigerlake
 			register "PcieRpLtrEnable[8]"			= "1"
 			register "PcieClkSrcUsage[3]"			= "0x08"
 			register "PcieClkSrcClkReq[3]"			= "3"
-			register "PcieRpSlotImplemented[8]"		= "1"
+			register "PcieRpSlotImplemented[8]"		= "true"
 
 			smbios_slot_desc				"SlotTypeM2Socket3"
 									"SlotLengthOther"
diff --git a/src/mainboard/system76/addw1/devicetree.cb b/src/mainboard/system76/addw1/devicetree.cb
index e498173b07..cd93ddcc14 100644
--- a/src/mainboard/system76/addw1/devicetree.cb
+++ b/src/mainboard/system76/addw1/devicetree.cb
@@ -106,7 +106,7 @@ chip soc/intel/cannonlake
 			register "PcieRpLtrEnable[20]" = "true"
 			register "PcieClkSrcUsage[10]" = "20"
 			register "PcieClkSrcClkReq[10]" = "10"
-			register "PcieRpSlotImplemented[20]" = "1"
+			register "PcieRpSlotImplemented[20]" = "true"
 			smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M.2/M 2280 (J_SSD2)" "SlotDataBusWidth4X"
 		end
 		device ref pcie_rp9	on
@@ -114,7 +114,7 @@ chip soc/intel/cannonlake
 			register "PcieRpLtrEnable[8]" = "true"
 			register "PcieClkSrcUsage[9]" = "8"
 			register "PcieClkSrcClkReq[9]" = "9"
-			register "PcieRpSlotImplemented[8]" = "1"
+			register "PcieRpSlotImplemented[8]" = "true"
 			smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M.2/M 2280 (J_SSD1)" "SlotDataBusWidth4X"
 		end
 		device ref pcie_rp14	on
@@ -122,21 +122,21 @@ chip soc/intel/cannonlake
 			register "PcieRpLtrEnable[13]" = "true"
 			register "PcieClkSrcUsage[5]" = "13"
 			register "PcieClkSrcClkReq[5]" = "5"
-			register "PcieRpSlotImplemented[13]" = "1"
+			register "PcieRpSlotImplemented[13]" = "true"
 		end
 		device ref pcie_rp15	on
 			# PCI Express root port #15 x1, Clock 7 (Card Reader)
 			register "PcieRpLtrEnable[14]" = "true"
 			register "PcieClkSrcUsage[7]" = "14"
 			register "PcieClkSrcClkReq[7]" = "7"
-			register "PcieRpSlotImplemented[14]" = "1"
+			register "PcieRpSlotImplemented[14]" = "true"
 		end
 		device ref pcie_rp16	on
 			# PCI Express root port #16 x1, Clock 6 (WLAN)
 			register "PcieRpLtrEnable[15]" = "true"
 			register "PcieClkSrcUsage[6]" = "15"
 			register "PcieClkSrcClkReq[6]" = "6"
-			register "PcieRpSlotImplemented[15]" = "1"
+			register "PcieRpSlotImplemented[15]" = "true"
 			smbios_slot_desc "SlotTypeM2Socket1_SD" "SlotLengthOther" "M.2/E 2230 (J_WLAN1)" "SlotDataBusWidth1X"
 		end
 		device ref lpc_espi	on
diff --git a/src/mainboard/system76/cml-u/variants/lemp9/overridetree.cb b/src/mainboard/system76/cml-u/variants/lemp9/overridetree.cb
index 4dfd3cc648..60e786012f 100644
--- a/src/mainboard/system76/cml-u/variants/lemp9/overridetree.cb
+++ b/src/mainboard/system76/cml-u/variants/lemp9/overridetree.cb
@@ -44,14 +44,14 @@ chip soc/intel/cannonlake
 			register "PcieRpLtrEnable[5]" = "true"
 			register "PcieClkSrcUsage[3]" = "5"
 			register "PcieClkSrcClkReq[3]" = "3"
-			register "PcieRpSlotImplemented[5]" = "1"
+			register "PcieRpSlotImplemented[5]" = "true"
 		end
 		device ref pcie_rp8	on
 			device pci 00.0 on end # x1 M.2/E 2230 (J_WLAN1)
 			register "PcieRpLtrEnable[7]" = "true"
 			register "PcieClkSrcUsage[2]" = "7"
 			register "PcieClkSrcClkReq[2]" = "2"
-			register "PcieRpSlotImplemented[7]" = "1"
+			register "PcieRpSlotImplemented[7]" = "true"
 			chip drivers/wifi/generic
 				device pci 00.0 on end
 			end
@@ -62,7 +62,7 @@ chip soc/intel/cannonlake
 			register "PcieRpLtrEnable[8]" = "true"
 			register "PcieClkSrcUsage[4]" = "8"
 			register "PcieClkSrcClkReq[4]" = "4"
-			register "PcieRpSlotImplemented[8]" = "1"
+			register "PcieRpSlotImplemented[8]" = "true"
 			smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M.2/M 2280 (J_SSD2)" "SlotDataBusWidth4X"
 		end
 		device ref pcie_rp13	on
@@ -70,7 +70,7 @@ chip soc/intel/cannonlake
 			register "PcieRpLtrEnable[12]" = "true"
 			register "PcieClkSrcUsage[5]" = "12"
 			register "PcieClkSrcClkReq[5]" = "5"
-			register "PcieRpSlotImplemented[12]" = "1"
+			register "PcieRpSlotImplemented[12]" = "true"
 			smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M.2/M 2280 (J_SSD1)" "SlotDataBusWidth4X"
 		end
 	end
diff --git a/src/mainboard/system76/gaze15/devicetree.cb b/src/mainboard/system76/gaze15/devicetree.cb
index 02f4d70f58..be36abf73f 100644
--- a/src/mainboard/system76/gaze15/devicetree.cb
+++ b/src/mainboard/system76/gaze15/devicetree.cb
@@ -97,7 +97,7 @@ chip soc/intel/cannonlake
 			register "PcieRpLtrEnable[20]" = "true"
 			register "PcieClkSrcUsage[11]" = "20"
 			register "PcieClkSrcClkReq[11]" = "11"
-			register "PcieRpSlotImplemented[20]" = "1"
+			register "PcieRpSlotImplemented[20]" = "true"
 			smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M.2/M 2280 (J_SSD2)" "SlotDataBusWidth4X"
 		end
 		device ref pcie_rp9	on
@@ -105,7 +105,7 @@ chip soc/intel/cannonlake
 			register "PcieRpLtrEnable[8]" = "true"
 			register "PcieClkSrcUsage[10]" = "8"
 			register "PcieClkSrcClkReq[10]" = "10"
-			register "PcieRpSlotImplemented[8]" = "1"
+			register "PcieRpSlotImplemented[8]" = "true"
 			smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M.2/M 2280 (J_SSD1)" "SlotDataBusWidth4X"
 		end
 		device ref pcie_rp14	on
@@ -113,7 +113,7 @@ chip soc/intel/cannonlake
 			register "PcieRpLtrEnable[13]" = "true"
 			register "PcieClkSrcUsage[6]" = "13"
 			register "PcieClkSrcClkReq[6]" = "6"
-			register "PcieRpSlotImplemented[13]" = "1"
+			register "PcieRpSlotImplemented[13]" = "true"
 			smbios_slot_desc "SlotTypeM2Socket1_SD" "SlotLengthOther" "M.2/E 2230 (J_WLAN1)" "SlotDataBusWidth1X"
 		end
 		device ref pcie_rp15	on
@@ -121,7 +121,7 @@ chip soc/intel/cannonlake
 			register "PcieRpLtrEnable[14]" = "true"
 			register "PcieClkSrcUsage[5]" = "14"
 			register "PcieClkSrcClkReq[5]" = "5"
-			register "PcieRpSlotImplemented[14]" = "1"
+			register "PcieRpSlotImplemented[14]" = "true"
 		end
 		device ref lpc_espi	on
 			register "gen1_dec" = "0x00040069"
diff --git a/src/mainboard/system76/oryp6/devicetree.cb b/src/mainboard/system76/oryp6/devicetree.cb
index 0737ceb714..bcb75d0b3c 100644
--- a/src/mainboard/system76/oryp6/devicetree.cb
+++ b/src/mainboard/system76/oryp6/devicetree.cb
@@ -108,14 +108,14 @@ chip soc/intel/cannonlake
 			register "PcieRpHotPlug[16]" = "1"
 			register "PcieClkSrcUsage[0]" = "16"
 			register "PcieClkSrcClkReq[0]" = "0"
-			register "PcieRpSlotImplemented[16]" = "1"
+			register "PcieRpSlotImplemented[16]" = "true"
 		end
 		device ref pcie_rp21	on
 			# PCI Express root port #21 x4, Clock 11 (SSD2)
 			register "PcieRpLtrEnable[20]" = "true"
 			register "PcieClkSrcUsage[11]" = "20"
 			register "PcieClkSrcClkReq[11]" = "11"
-			register "PcieRpSlotImplemented[20]" = "1"
+			register "PcieRpSlotImplemented[20]" = "true"
 			smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M.2/M 2280 (J_SSD2)" "SlotDataBusWidth4X"
 		end
 		device ref pcie_rp9	on
@@ -123,7 +123,7 @@ chip soc/intel/cannonlake
 			register "PcieRpLtrEnable[8]" = "true"
 			register "PcieClkSrcUsage[12]" = "8"
 			register "PcieClkSrcClkReq[12]" = "12"
-			register "PcieRpSlotImplemented[8]" = "1"
+			register "PcieRpSlotImplemented[8]" = "true"
 			smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M.2/M 2280 (J_SSD1)" "SlotDataBusWidth4X"
 		end
 		device ref pcie_rp14	on
@@ -131,21 +131,21 @@ chip soc/intel/cannonlake
 			register "PcieRpLtrEnable[13]" = "true"
 			register "PcieClkSrcUsage[7]" = "13"
 			register "PcieClkSrcClkReq[7]" = "7"
-			register "PcieRpSlotImplemented[13]" = "1"
+			register "PcieRpSlotImplemented[13]" = "true"
 		end
 		device ref pcie_rp15	on
 			# PCI Express root port #15 x1, Clock 9 (Card Reader)
 			register "PcieRpLtrEnable[14]" = "true"
 			register "PcieClkSrcUsage[9]" = "14"
 			register "PcieClkSrcClkReq[9]" = "9"
-			register "PcieRpSlotImplemented[14]" = "1"
+			register "PcieRpSlotImplemented[14]" = "true"
 		end
 		device ref pcie_rp16	on
 			# PCI Express root port #16 x1, Clock 6 (WLAN)
 			register "PcieRpLtrEnable[15]" = "true"
 			register "PcieClkSrcUsage[6]" = "15"
 			register "PcieClkSrcClkReq[6]" = "6"
-			register "PcieRpSlotImplemented[15]" = "1"
+			register "PcieRpSlotImplemented[15]" = "true"
 			smbios_slot_desc "SlotTypeM2Socket1_SD" "SlotLengthOther" "M.2/E 2230 (J_WLAN1)" "SlotDataBusWidth1X"
 		end
 		device ref lpc_espi	on
diff --git a/src/mainboard/system76/tgl-h/variants/gaze16-3050/overridetree.cb b/src/mainboard/system76/tgl-h/variants/gaze16-3050/overridetree.cb
index b65c45b955..8382c084a8 100644
--- a/src/mainboard/system76/tgl-h/variants/gaze16-3050/overridetree.cb
+++ b/src/mainboard/system76/tgl-h/variants/gaze16-3050/overridetree.cb
@@ -71,7 +71,7 @@ chip soc/intel/tigerlake
 			register "PcieRpLtrEnable[7]" = "true"
 			register "PcieClkSrcUsage[8]" = "7"
 			register "PcieClkSrcClkReq[8]" = "8"
-			register "PcieRpSlotImplemented[7]" = "1"
+			register "PcieRpSlotImplemented[7]" = "true"
 			smbios_slot_desc "SlotTypeM2Socket1_SD" "SlotLengthOther" "M.2/E 2230 (J_WLAN1)" "SlotDataBusWidth1X"
 		end
 		device ref pcie_rp9 on
@@ -79,7 +79,7 @@ chip soc/intel/tigerlake
 			register "PcieRpLtrEnable[8]" = "true"
 			register "PcieClkSrcUsage[9]" = "8"
 			register "PcieClkSrcClkReq[9]" = "9"
-			register "PcieRpSlotImplemented[8]" = "1"
+			register "PcieRpSlotImplemented[8]" = "true"
 			smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M.2/M 2280 (J_SSD1)" "SlotDataBusWidth4X"
 		end
 	end
diff --git a/src/mainboard/system76/tgl-h/variants/gaze16-3060/overridetree.cb b/src/mainboard/system76/tgl-h/variants/gaze16-3060/overridetree.cb
index 461736c367..2915989eef 100644
--- a/src/mainboard/system76/tgl-h/variants/gaze16-3060/overridetree.cb
+++ b/src/mainboard/system76/tgl-h/variants/gaze16-3060/overridetree.cb
@@ -71,7 +71,7 @@ chip soc/intel/tigerlake
 			register "PcieRpLtrEnable[7]" = "true"
 			register "PcieClkSrcUsage[2]" = "7"
 			register "PcieClkSrcClkReq[2]" = "2"
-			register "PcieRpSlotImplemented[7]" = "1"
+			register "PcieRpSlotImplemented[7]" = "true"
 			smbios_slot_desc "SlotTypeM2Socket1_SD" "SlotLengthOther" "M.2/E 2230 (J_WLAN1)" "SlotDataBusWidth1X"
 		end
 		device ref pcie_rp9 on
@@ -79,7 +79,7 @@ chip soc/intel/tigerlake
 			register "PcieRpLtrEnable[8]" = "true"
 			register "PcieClkSrcUsage[10]" = "8"
 			register "PcieClkSrcClkReq[10]" = "10"
-			register "PcieRpSlotImplemented[8]" = "1"
+			register "PcieRpSlotImplemented[8]" = "true"
 			smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M.2/M 2280 (J_SSD2)" "SlotDataBusWidth4X"
 		end
 		device ref gbe on end
diff --git a/src/mainboard/system76/tgl-h/variants/oryp8/overridetree.cb b/src/mainboard/system76/tgl-h/variants/oryp8/overridetree.cb
index 3c4578bf61..331fe179a7 100644
--- a/src/mainboard/system76/tgl-h/variants/oryp8/overridetree.cb
+++ b/src/mainboard/system76/tgl-h/variants/oryp8/overridetree.cb
@@ -80,7 +80,7 @@ chip soc/intel/tigerlake
 			register "PcieRpLtrEnable[7]" = "true"
 			register "PcieClkSrcUsage[2]" = "7"
 			register "PcieClkSrcClkReq[2]" = "2"
-			register "PcieRpSlotImplemented[7]" = "1"
+			register "PcieRpSlotImplemented[7]" = "true"
 			smbios_slot_desc "SlotTypeM2Socket1_SD" "SlotLengthOther" "M.2/E 2230 (J_WLAN1)" "SlotDataBusWidth1X"
 		end
 		device ref pcie_rp9 on
@@ -88,7 +88,7 @@ chip soc/intel/tigerlake
 			register "PcieRpLtrEnable[8]" = "true"
 			register "PcieClkSrcUsage[6]" = "8"
 			register "PcieClkSrcClkReq[6]" = "6"
-			register "PcieRpSlotImplemented[8]" = "1"
+			register "PcieRpSlotImplemented[8]" = "true"
 			smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M.2/M 2280 (J_SSD2)" "SlotDataBusWidth4X"
 		end
 		device ref smbus on
diff --git a/src/mainboard/system76/tgl-u/variants/darp7/overridetree.cb b/src/mainboard/system76/tgl-u/variants/darp7/overridetree.cb
index 9ede4dd1d7..32ba1bac89 100644
--- a/src/mainboard/system76/tgl-u/variants/darp7/overridetree.cb
+++ b/src/mainboard/system76/tgl-u/variants/darp7/overridetree.cb
@@ -165,7 +165,7 @@ chip soc/intel/tigerlake
 			register "PcieRpLtrEnable[7]" = "true"
 			register "PcieClkSrcUsage[1]" = "7"
 			register "PcieClkSrcClkReq[1]" = "1"
-			register "PcieRpSlotImplemented[7]" = "1"
+			register "PcieRpSlotImplemented[7]" = "true"
 			smbios_slot_desc "SlotTypeM2Socket1_SD" "SlotLengthOther" "M.2/E 2230 (J_WLAN1)" "SlotDataBusWidth1X"
 		end
 		device ref pcie_rp9 on
@@ -173,7 +173,7 @@ chip soc/intel/tigerlake
 			register "PcieRpLtrEnable[8]" = "true"
 			register "PcieClkSrcUsage[4]" = "8"
 			register "PcieClkSrcClkReq[4]" = "4"
-			register "PcieRpSlotImplemented[8]" = "1"
+			register "PcieRpSlotImplemented[8]" = "true"
 			chip soc/intel/common/block/pcie/rtd3
 				register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D14)" # SSD_PWR_EN
 				register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_H0)" # GPP_H0_RTD3
diff --git a/src/mainboard/system76/tgl-u/variants/galp5/overridetree.cb b/src/mainboard/system76/tgl-u/variants/galp5/overridetree.cb
index c272244222..2d5dc150d6 100644
--- a/src/mainboard/system76/tgl-u/variants/galp5/overridetree.cb
+++ b/src/mainboard/system76/tgl-u/variants/galp5/overridetree.cb
@@ -181,7 +181,7 @@ chip soc/intel/tigerlake
 			register "PcieRpLtrEnable[10]" = "true"
 			register "PcieClkSrcUsage[1]" = "10"
 			register "PcieClkSrcClkReq[1]" = "1"
-			register "PcieRpSlotImplemented[10]" = "1"
+			register "PcieRpSlotImplemented[10]" = "true"
 			smbios_slot_desc "SlotTypeM2Socket1_SD" "SlotLengthOther" "M.2/E 2230 (J_WLAN1)" "SlotDataBusWidth1X"
 		end
 		device ref pmc hidden
diff --git a/src/mainboard/system76/tgl-u/variants/lemp10/overridetree.cb b/src/mainboard/system76/tgl-u/variants/lemp10/overridetree.cb
index 8ecb00e88d..08344126c4 100644
--- a/src/mainboard/system76/tgl-u/variants/lemp10/overridetree.cb
+++ b/src/mainboard/system76/tgl-u/variants/lemp10/overridetree.cb
@@ -124,7 +124,7 @@ chip soc/intel/tigerlake
 			register "PcieRpLtrEnable[2]" = "true"
 			register "PcieClkSrcUsage[1]" = "2"
 			register "PcieClkSrcClkReq[1]" = "1"
-			register "PcieRpSlotImplemented[2]" = "1"
+			register "PcieRpSlotImplemented[2]" = "true"
 			smbios_slot_desc "SlotTypeM2Socket1_SD" "SlotLengthOther" "M.2/E 2230 (J_WLAN1)" "SlotDataBusWidth1X"
 		end
 		device ref pcie_rp6 on
@@ -139,7 +139,7 @@ chip soc/intel/tigerlake
 			register "PcieRpLtrEnable[8]" = "true"
 			register "PcieClkSrcUsage[0]" = "8"
 			register "PcieClkSrcClkReq[0]" = "0"
-			register "PcieRpSlotImplemented[8]" = "1"
+			register "PcieRpSlotImplemented[8]" = "true"
 			chip soc/intel/common/block/pcie/rtd3
 				register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D14)" # SSD2_PWR_DN#
 				register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D9)" # GPP_D13_RTD3 (labeled incorrectly)
diff --git a/src/soc/intel/alderlake/fsp_params.c b/src/soc/intel/alderlake/fsp_params.c
index 3368b3642b..a5ac6c886c 100644
--- a/src/soc/intel/alderlake/fsp_params.c
+++ b/src/soc/intel/alderlake/fsp_params.c
@@ -927,7 +927,7 @@ static void fill_fsps_pcie_params(FSP_S_CONFIG *s_cfg,
 		s_cfg->PcieRpClkReqDetect[i] = !!(rp_cfg->flags & PCIE_RP_CLK_REQ_DETECT);
 		/* PcieRpSlotImplemented default to 1 (slot implemented) in FSP; 0: built-in */
 		if (!!(rp_cfg->flags & PCIE_RP_BUILT_IN))
-			s_cfg->PcieRpSlotImplemented[i] = 0;
+			s_cfg->PcieRpSlotImplemented[i] = false;
 		s_cfg->PcieRpDetectTimeoutMs[i] = rp_cfg->pcie_rp_detect_timeout_ms;
 		configure_pch_rp_power_management(s_cfg, rp_cfg, i);
 	}
diff --git a/src/soc/intel/tigerlake/chip.h b/src/soc/intel/tigerlake/chip.h
index 6f9acb9a92..0fd00076aa 100644
--- a/src/soc/intel/tigerlake/chip.h
+++ b/src/soc/intel/tigerlake/chip.h
@@ -295,7 +295,7 @@ struct soc_intel_tigerlake_config {
 	/* PCIe Root Ports */
 	uint8_t PcieRpHotPlug[CONFIG_MAX_ROOT_PORTS];
 	/* Implemented as slot or built-in? */
-	uint8_t PcieRpSlotImplemented[CONFIG_MAX_ROOT_PORTS];
+	bool PcieRpSlotImplemented[CONFIG_MAX_ROOT_PORTS];
 	/* PCIe output clocks type to PCIe devices.
 	 * 0-23: PCH rootport, 0x70: LAN, 0x80: unspecified but in use,
 	 * 0xFF: not used */

From ae5810e358a2d1d5aa7df5993e87e108aecd6db2 Mon Sep 17 00:00:00 2001
From: smadhesu <smadhesu@qualcomm.corp-partner.google.com>
Date: Sun, 29 Jun 2025 22:26:04 +0530
Subject: [PATCH 1464/3886] util/qualcomm: Add MBN v7 format support

The QCOM X1P42100 SoC requires images loaded by PBL in MBN v7
format. This script is updated to support MBN v7 format which will
be used to generate the Bootblock binary.

Starting with the Qualcomm x1p42100 SoC, the bootblock ELF header
expects MBN version 7 instead of version 6 with the SC7280 SoC. This
patch adds the necessary adjustment to ensure compatibility with older
SoC platforms and also adds incremental support for newer SoC
generations. If Qualcomm SoCs in the future demands a more advanced
version of MBN (version > 7), additional logic will be added to the
newly added section as `self.flash_parti_ver == 8`.

BUG=b:420542130, b:404985109

TEST=Create image.serial.bin with bootblock in MBN v7 format and
ensure it boots on X1P42100. Please refer to the steps mentioned
below to create final AP FW image for QC SoC X1P42100.

Step 1: Create Bootblock MBN image using createxbl.py script where the
newly added MBN v7 support will be used.

Step 2: Call create_multielf.py to create the concatenated multi ELF
( TME SEQ + TME FW + QC_SEC + BOOTBLOCK from step 1)

Step 3: Call nqgpt.py to create final GPT image.

Change-Id: I484df537ac7d1e51ec86dcae74a74dc211710616
Signed-off-by: Sasirekaa Madhesu <smadhesu@qualcomm.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88240
Reviewed-by: Pranava Y N <pranavayn@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
---
 util/qualcomm/createxbl.py |   2 +-
 util/qualcomm/mbn_tools.py | 178 ++++++++++++++++++++++++++++++-------
 2 files changed, 146 insertions(+), 34 deletions(-)

diff --git a/util/qualcomm/createxbl.py b/util/qualcomm/createxbl.py
index 97fc9728b4..f604727f10 100755
--- a/util/qualcomm/createxbl.py
+++ b/util/qualcomm/createxbl.py
@@ -98,7 +98,7 @@ def main():
 
   parser.add_option("--mbn_version",
                     action="store", type="int", dest="mbn_version",
-                    help="Add mbn header in elf image. '3', '5' or '6'")
+                    help="Add mbn header in elf image. '3', '5', '6' or '7'")
 
 
   (options, args) = parser.parse_args()
diff --git a/util/qualcomm/mbn_tools.py b/util/qualcomm/mbn_tools.py
index 9abb96c72a..6e611026c6 100755
--- a/util/qualcomm/mbn_tools.py
+++ b/util/qualcomm/mbn_tools.py
@@ -528,50 +528,154 @@ class Boot_Hdr:
       self.reserved_1 = init_val
       self.reserved_2 = init_val
       self.reserved_3 = init_val
+      self.reserved = 0
+      self.common_metadata_size = init_val
+
+      # Common Metadata members. These are needed for an MBNv7.
+      # Common Metadata is placed just after the header, hence, clubbed with
+      # this header.
+      self.common_metadata_major_version = 0
+      self.common_metadata_minor_version = 0
+      self.software_id = init_val
+      self.secondary_software_id = 0
+      self.hash_table_algorithm = 3
+      self.measurement_register_target = 0
+
+      # OEM Metadata 2.0 Members added for MBNv7.
+      self.major_version = 2
+      self.minor_version = 0
+      self.anti_rollback_version = 0
+      self.mrc_index = 0
+      self.soc_hw_ver_0 = 0
+      self.soc_hw_ver_1 = 0
+      self.soc_hw_ver_2 = 0
+      self.soc_hw_ver_3 = 0
+      self.soc_hw_ver_4 = 0
+      self.soc_hw_ver_5 = 0
+      self.soc_hw_ver_6 = 0
+      self.soc_hw_ver_7 = 0
+      self.soc_hw_ver_8 = 0
+      self.soc_hw_ver_9 = 0
+      self.soc_hw_ver_10 = 0
+      self.soc_hw_ver_11 = 0
+      self.soc_feature_id = 0
+      self.jtag_id = 0
+      self.serial_number_0 = 0
+      self.serial_number_1 = 0
+      self.serial_number_2 = 0
+      self.serial_number_3 = 0
+      self.serial_number_4 = 0
+      self.serial_number_5 = 0
+      self.serial_number_6 = 0
+      self.serial_number_7 = 0
+      self.oem_id = 0
+      self.oem_product_id = 0
+      self.soc_lifecycle_state = 0
+      self.oem_lifecycle_state = 0
+      self.oem_root_certificate_hash_algorithm = 0
+      self.oem_root_certificate_hash = b'\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00'
+      self.flags = 1398101
 
    def getLength(self):
       return BOOT_HEADER_LENGTH
 
    def writePackedData(self, target, write_full_hdr):
-      values = [self.image_id,
-                self.flash_parti_ver,
-                self.image_src,
-                self.image_dest_ptr,
-                self.image_size,
-                self.code_size ,
-                self.sig_ptr,
-                self.sig_size,
-                self.cert_chain_ptr,
-                self.cert_chain_size,
-                self.magic_number1,
-                self.version,
-                self.OS_type,
-                self.boot_apps_parti_entry,
-                self.boot_apps_size_entry,
-                self.boot_apps_ram_loc,
-                self.reserved_ptr,
-                self.reserved_1,
-                self.reserved_2,
-                self.reserved_3 ]
+      if self.flash_parti_ver == 7:
+        values = [self.reserved,
+                  self.flash_parti_ver,
+                  self.common_metadata_size,
+                  self.metadata_size_qti,
+                  self.metadata_size,
+                  self.code_size,
+                  self.image_src, # QTI signature size per MBNv6/v5/v3 structure below.
+                  self.image_dest_ptr, # QTI certificate chain size per MBNv6/v5/v3 structure below.
+                  self.sig_size,
+                  self.cert_chain_size,
+                  # Common Metadata members.
+                  self.common_metadata_major_version,
+                  self.common_metadata_minor_version,
+                  self.software_id,
+                  self.secondary_software_id,
+                  self.hash_table_algorithm,
+                  self.measurement_register_target,
+                  # OEM Metadata 2.0 members.
+                  self.major_version,
+                  self.minor_version,
+                  self.anti_rollback_version,
+                  self.mrc_index,
+                  self.soc_hw_ver_0,
+                  self.soc_hw_ver_1,
+                  self.soc_hw_ver_2,
+                  self.soc_hw_ver_3,
+                  self.soc_hw_ver_4,
+                  self.soc_hw_ver_5,
+                  self.soc_hw_ver_6,
+                  self.soc_hw_ver_7,
+                  self.soc_hw_ver_8,
+                  self.soc_hw_ver_9,
+                  self.soc_hw_ver_10,
+                  self.soc_hw_ver_11,
+                  self.soc_feature_id,
+                  self.jtag_id,
+                  self.serial_number_0,
+                  self.serial_number_1,
+                  self.serial_number_2,
+                  self.serial_number_3,
+                  self.serial_number_4,
+                  self.serial_number_5,
+                  self.serial_number_6,
+                  self.serial_number_7,
+                  self.oem_id,
+                  self.oem_product_id,
+                  self.soc_lifecycle_state,
+                  self.oem_lifecycle_state,
+                  self.oem_root_certificate_hash_algorithm,
+                  self.oem_root_certificate_hash,
+                  self.flags]
+      else:
+        values = [self.image_id,
+                  self.flash_parti_ver,
+                  self.image_src,
+                  self.image_dest_ptr,
+                  self.image_size,
+                  self.code_size ,
+                  self.sig_ptr,
+                  self.sig_size,
+                  self.cert_chain_ptr,
+                  self.cert_chain_size,
+                  self.magic_number1,
+                  self.version,
+                  self.OS_type,
+                  self.boot_apps_parti_entry,
+                  self.boot_apps_size_entry,
+                  self.boot_apps_ram_loc,
+                  self.reserved_ptr,
+                  self.reserved_1,
+                  self.reserved_2,
+                  self.reserved_3 ]
 
-      if self.flash_parti_ver >= 6:
-        values.insert(10, self.metadata_size_qti)
-        values.insert(11, self.metadata_size)
+        if self.flash_parti_ver == 6:
+            values.insert(10, self.metadata_size_qti)
+            values.insert(11, self.metadata_size)
 
-      if self.image_dest_ptr >= 0x100000000:
-        values[3] = 0xFFFFFFFF
+        if self.image_dest_ptr >= 0x100000000:
+            values[3] = 0xFFFFFFFF
 
-      if self.cert_chain_ptr >= 0x100000000:
-        values[6] = 0xFFFFFFFF
+        if self.cert_chain_ptr >= 0x100000000:
+            values[6] = 0xFFFFFFFF
 
-      if self.sig_ptr >= 0x100000000:
-        values[8] = 0xFFFFFFFF
+        if self.sig_ptr >= 0x100000000:
+            values[8] = 0xFFFFFFFF
 
       # Write 10 entries(40B) or 20 entries(80B) of boot header
       if write_full_hdr is False:
-         if self.flash_parti_ver >= 6:
+         if self.flash_parti_ver == 6:
             s = struct.Struct('I'* 12)
             values = values[:12]
+         elif self.flash_parti_ver == 7:
+            # MBNv7 Header is 40 bytes. Common Metadata is 24 bytes,
+            # OEM Metadata is 224 bytes and of the format: "I*18 + Q*8 + I*5+ 64s + I".
+            s = struct.Struct('I'*34 + 'Q'*8 + 'I'*5 + '64sI')
          else:
             s = struct.Struct('I'* 10)
             values = values[:10]
@@ -935,7 +1039,7 @@ def image_header(env, gen_dict,
       image_size = code_size
 
    if header_version:
-      assert header_version in [3, 5, 6], 'Not a valid MBN header version'
+      assert header_version in [3, 5, 6, 7], 'Not a valid MBN header version'
 
    # For ELF or hashed images, image destination will be determined from an ELF input file
    if gen_dict['IMAGE_KEY_MBN_TYPE'] == 'elf':
@@ -993,6 +1097,12 @@ def image_header(env, gen_dict,
          boot_header.metadata_size_qti = 0                    # qti_metadata size
          boot_header.metadata_size = 0                        # oem_metadata size
 
+      if header_version == 7:
+         boot_header.software_id = 0x7B                       # Hardcoded to BOOTBLOCK SW ID
+         boot_header.common_metadata_size = 24
+         boot_header.metadata_size = 224
+
+
       # If preamble is required, output the preamble file and update the boot_header
       if requires_preamble is True:
          boot_header = image_preamble(gen_dict, preamble_file_name, boot_header, num_of_pages)
@@ -2113,11 +2223,13 @@ def file_copy_offset(in_fp, in_off, out_fp, out_off, num_bytes):
    return num_bytes
 
 #----------------------------------------------------------------------------
-# sha1/sha256 hash routine wrapper
+# Return header_size based on version
 #----------------------------------------------------------------------------
 def header_size(header_version):
-    if header_version >= 6:
+    if header_version == 6:
         return 48
+    elif header_version == 7:
+        return 288
     else:
         return 40
 

From e96bf7e094d7b74873c3359e288932c27d1d9e41 Mon Sep 17 00:00:00 2001
From: smadhesu <smadhesu@qualcomm.corp-partner.google.com>
Date: Sun, 29 Jun 2025 23:13:51 +0530
Subject: [PATCH 1465/3886] soc/qc/x1p42100: Support to generate Bootblock as
 multi ELF

This commit performs below to create Bootblock binary.
1. createxbl.py: Converts "bootblock.raw.elf" to MBN (v7 format).
2. create_multielf.py: Concatenates TME SEQ, TME FW, QC_SEC and
bootblock into multi ELF binary.

BUG=b:415949107

TEST=Generate image.serial.bin and verify bootup on X1P42100

Change-Id: Icc499221d8806b549f6c873a14382a28c3efb74f
Signed-off-by: Sasirekaa Madhesu <smadhesu@qualcomm.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88241
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Pranava Y N <pranavayn@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
---
 src/soc/qualcomm/x1p42100/Makefile.mk | 13 +++++++++----
 util/qualcomm/create_multielf.py      |  0
 2 files changed, 9 insertions(+), 4 deletions(-)
 mode change 100644 => 100755 util/qualcomm/create_multielf.py

diff --git a/src/soc/qualcomm/x1p42100/Makefile.mk b/src/soc/qualcomm/x1p42100/Makefile.mk
index 7a8b928930..3140ea2445 100644
--- a/src/soc/qualcomm/x1p42100/Makefile.mk
+++ b/src/soc/qualcomm/x1p42100/Makefile.mk
@@ -72,12 +72,17 @@ endif
 
 ################################################################################
 QC_SEC_FILE := $(X1P42100_BLOB)/qc_sec/qc_sec.mbn
+TME_SEQ_FILE := $(X1P42100_BLOB)/tme/sequencer_ram.elf
+TME_FW_FILE := $(X1P42100_BLOB)/tme/signed_firmware_soc_view.elf
+
 $(objcbfs)/bootblock.bin: $(objcbfs)/bootblock.raw.elf
-	@util/qualcomm/createxbl.py --mbn_version 6 -f $(objcbfs)/bootblock.raw.elf \
-		-x $(QC_SEC_FILE) -o $(objcbfs)/merged_bb_qcsec.mbn \
-		-a 64 -d 64 -c 64
+	@util/qualcomm/createxbl.py --mbn_version 7 -f $(objcbfs)/bootblock.raw.elf \
+		-o $(objcbfs)/bootblock.mbn \
+		-a 64 -c 64
+	@util/qualcomm/create_multielf.py -f $(TME_SEQ_FILE),$(TME_FW_FILE),$(QC_SEC_FILE),$(objcbfs)/bootblock.mbn \
+		-o $(objcbfs)/merged_bb.melf
 	@printf "\nqgpt.py 4K sector size\n"
-	@util/qualcomm/qgpt.py $(objcbfs)/merged_bb_qcsec.mbn \
+	@util/qualcomm/qgpt.py $(objcbfs)/merged_bb.melf \
 		$(objcbfs)/bootblock.bin
 
 ################################################################################
diff --git a/util/qualcomm/create_multielf.py b/util/qualcomm/create_multielf.py
old mode 100644
new mode 100755

From e3ffa3c14fed7a6ed000a71f0ceb841b123fef48 Mon Sep 17 00:00:00 2001
From: Vince Liu <vince-wl.liu@mediatek.corp-partner.google.com>
Date: Fri, 2 May 2025 23:16:42 +0800
Subject: [PATCH 1466/3886] soc/meidatek/mt8196: Move PI image related code to
 common

To promote code reuse and maintainability, move PI image related code to
common folder. The function add_pi_image_params is renamed to
pi_image_add_mtk_fsp_params for prefix consistency.

BUG=b:379008996
BRANCH=none
TEST=build passed.

Signed-off-by: Vince Liu <vince-wl.liu@mediatek.corp-partner.google.com>
Change-Id: If5e3d9e6d5f97ead763ef9adc2d23bce0ed68877
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88265
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 .../common/include/soc/pi_image_common.h      |  8 ++++++++
 .../mediatek/{mt8196 => common}/pi_image.c    | 19 +++++++++++++++----
 src/soc/mediatek/mt8196/Makefile.mk           |  2 +-
 .../mediatek/mt8196/include/soc/pi_image.h    |  5 +----
 src/soc/mediatek/mt8196/soc.c                 | 15 +--------------
 5 files changed, 26 insertions(+), 23 deletions(-)
 create mode 100644 src/soc/mediatek/common/include/soc/pi_image_common.h
 rename src/soc/mediatek/{mt8196 => common}/pi_image.c (53%)

diff --git a/src/soc/mediatek/common/include/soc/pi_image_common.h b/src/soc/mediatek/common/include/soc/pi_image_common.h
new file mode 100644
index 0000000000..b00ff67b56
--- /dev/null
+++ b/src/soc/mediatek/common/include/soc/pi_image_common.h
@@ -0,0 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0-only OR MIT */
+
+#ifndef __SOC_MEDIATEK_COMMON_PI_IMAGE_COMMON_H__
+#define __SOC_MEDIATEK_COMMON_PI_IMAGE_COMMON_H__
+
+void pi_image_add_mtk_fsp_params(void);
+
+#endif  /* __SOC_MEDIATEK_COMMON_PI_IMAGE_COMMON_H__ */
diff --git a/src/soc/mediatek/mt8196/pi_image.c b/src/soc/mediatek/common/pi_image.c
similarity index 53%
rename from src/soc/mediatek/mt8196/pi_image.c
rename to src/soc/mediatek/common/pi_image.c
index d1e60e084f..32ffa12029 100644
--- a/src/soc/mediatek/mt8196/pi_image.c
+++ b/src/soc/mediatek/common/pi_image.c
@@ -1,18 +1,16 @@
 /* SPDX-License-Identifier: GPL-2.0-only OR MIT */
 
-#include <arch/cache.h>
 #include <assert.h>
 #include <soc/mcu_common.h>
+#include <soc/mtk_fsp.h>
 #include <soc/pi_image.h>
 #include <soc/symbols.h>
-#include <string.h>
-#include <sys/types.h>
 
 static struct mtk_mcu pi_image = {
 	.firmware_name = CONFIG_PI_IMG_FIRMWARE
 };
 
-size_t pi_image_load(void **buffer)
+static size_t pi_image_load(void **buffer)
 {
 	*buffer = NULL;
 	pi_image.load_buffer = _dram_dma;
@@ -24,3 +22,16 @@ size_t pi_image_load(void **buffer)
 	*buffer = pi_image.load_buffer;
 	return pi_image.run_size;
 }
+
+void pi_image_add_mtk_fsp_params(void)
+{
+	void *pi_img;
+	size_t pi_image_size;
+	pi_image_size = pi_image_load(&pi_img);
+
+	void *csram = (void *)PI_IMAGE_CSRAM;
+	size_t csram_size = PI_IMAGE_CSRAM_SIZE;
+
+	mtk_fsp_add_param(FSP_PARAM_TYPE_PI_IMG, pi_image_size, pi_img);
+	mtk_fsp_add_param(FSP_PARAM_TYPE_PI_IMG_CSRAM, csram_size, csram);
+}
diff --git a/src/soc/mediatek/mt8196/Makefile.mk b/src/soc/mediatek/mt8196/Makefile.mk
index ea691e391b..c69f67c2b7 100644
--- a/src/soc/mediatek/mt8196/Makefile.mk
+++ b/src/soc/mediatek/mt8196/Makefile.mk
@@ -79,7 +79,7 @@ ramstage-y += ../common/mt6685.c mt6685.c
 ramstage-y += mt6685_rtc.c
 ramstage-y += mtcmos.c
 ramstage-y += ../common/mtk_fsp.c
-ramstage-y += pi_image.c
+ramstage-y += ../common/pi_image.c
 ramstage-y += soc.c
 ramstage-y += ../common/spm.c ../common/spm_v2.c spm.c
 ramstage-y += ../common/sspm.c ../common/sspm_sram.c
diff --git a/src/soc/mediatek/mt8196/include/soc/pi_image.h b/src/soc/mediatek/mt8196/include/soc/pi_image.h
index 74f8ebe893..d30d925985 100644
--- a/src/soc/mediatek/mt8196/include/soc/pi_image.h
+++ b/src/soc/mediatek/mt8196/include/soc/pi_image.h
@@ -3,12 +3,9 @@
 #ifndef __SOC_MEDIATEK_MT8196_PI_IMAGE_H__
 #define __SOC_MEDIATEK_MT8196_PI_IMAGE_H__
 
-#include <commonlib/bsd/helpers.h>
-#include <soc/mcu_common.h>
+#include <soc/pi_image_common.h>
 
 #define PI_IMAGE_CSRAM		0x00120000
 #define PI_IMAGE_CSRAM_SIZE	(16 * KiB)
 
-size_t pi_image_load(void **buffer);
-
 #endif  /* __SOC_MEDIATEK_MT8196_PI_IMAGE_H__ */
diff --git a/src/soc/mediatek/mt8196/soc.c b/src/soc/mediatek/mt8196/soc.c
index c5a83d0c73..16271643ea 100644
--- a/src/soc/mediatek/mt8196/soc.c
+++ b/src/soc/mediatek/mt8196/soc.c
@@ -36,19 +36,6 @@ static void soc_read_resources(struct device *dev)
 	ram_range(dev, 0, (uintptr_t)_dram, sdram_size());
 }
 
-static void add_pi_image_params(void)
-{
-	void *pi_image;
-	size_t pi_image_size;
-	pi_image_size = pi_image_load(&pi_image);
-
-	void *csram = (void *)PI_IMAGE_CSRAM;
-	size_t csram_size = PI_IMAGE_CSRAM_SIZE;
-
-	mtk_fsp_add_param(FSP_PARAM_TYPE_PI_IMG, pi_image_size, pi_image);
-	mtk_fsp_add_param(FSP_PARAM_TYPE_PI_IMG_CSRAM, csram_size, csram);
-}
-
 static void soc_init(struct device *dev)
 {
 	uint32_t storage_type = mainboard_get_storage_type();
@@ -56,7 +43,7 @@ static void soc_init(struct device *dev)
 	dcc_init();
 	mtk_fsp_init(RAMSTAGE_SOC_INIT);
 	mtk_fsp_add_param(FSP_PARAM_TYPE_STORAGE, sizeof(storage_type), &storage_type);
-	add_pi_image_params();
+	pi_image_add_mtk_fsp_params();
 	mtk_fsp_load_and_run();
 
 	mtk_mmu_disable_l2c_sram();

From 4f1f502fd555f324822b500c4f57d3f89731cbae Mon Sep 17 00:00:00 2001
From: Vince Liu <vince-wl.liu@mediatek.corp-partner.google.com>
Date: Wed, 2 Jul 2025 08:36:21 +0800
Subject: [PATCH 1467/3886] soc/mediatek/mt8189: Add PI image loader in
 ramstage

Load PI image through CBFS and pass parameters of PI image to mtk_fsp
for parsing.

BUG=b:379008996
BRANCH=none
TEST=check the boot log:
[INFO ]  CBFS: Found 'pi_img.img' @0x3d880 size 0x10b in mcache @0xfffdd314
[DEBUG]  mtk_init_mcu: Loaded (and reset) pi_img.img in 14 msecs (720 bytes)

Signed-off-by: Hope Wang <hope.wang@mediatek.corp-partner.google.com>
Change-Id: Iada90ad4298d0a91ad73798252db19b12f2f6ef7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88266
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
---
 src/soc/mediatek/common/include/soc/symbols.h  |  1 +
 src/soc/mediatek/mt8189/Kconfig                |  7 +++++++
 src/soc/mediatek/mt8189/Makefile.mk            |  2 ++
 src/soc/mediatek/mt8189/include/soc/pi_image.h | 11 +++++++++++
 src/soc/mediatek/mt8189/soc.c                  |  2 ++
 5 files changed, 23 insertions(+)
 create mode 100644 src/soc/mediatek/mt8189/include/soc/pi_image.h

diff --git a/src/soc/mediatek/common/include/soc/symbols.h b/src/soc/mediatek/common/include/soc/symbols.h
index ae0c7932a4..c0e46733ec 100644
--- a/src/soc/mediatek/common/include/soc/symbols.h
+++ b/src/soc/mediatek/common/include/soc/symbols.h
@@ -10,6 +10,7 @@ DECLARE_REGION(resv_mem_optee)
 DECLARE_REGION(resv_mem_gpu)
 DECLARE_REGION(resv_mem_gpueb)
 DECLARE_REGION(dvfs2_reserved)
+DECLARE_REGION(ptp1_reserved)
 DECLARE_OPTIONAL_REGION(mcufw_reserved)
 
 #endif /* _SOC_MEDIATEK_COMMON_SYMBOLS_H_ */
diff --git a/src/soc/mediatek/mt8189/Kconfig b/src/soc/mediatek/mt8189/Kconfig
index f8ba8e4d26..7cf5ebe64f 100644
--- a/src/soc/mediatek/mt8189/Kconfig
+++ b/src/soc/mediatek/mt8189/Kconfig
@@ -42,6 +42,13 @@ config MCUPM_FIRMWARE
 	help
 	  The file name of the MediaTek MCUPM firmware.
 
+config PI_IMG_FIRMWARE
+	string
+	default "pi_img.img"
+	help
+	  The file name of the MediaTek PI image firmware. The main purpose of the PI image is
+	  to pass various frequency and voltage scaling parameters and settings to MCUPM.
+
 config SPM_FIRMWARE
 	string
 	default "spm_firmware.bin"
diff --git a/src/soc/mediatek/mt8189/Makefile.mk b/src/soc/mediatek/mt8189/Makefile.mk
index 9e5124b2a4..1386ed063d 100644
--- a/src/soc/mediatek/mt8189/Makefile.mk
+++ b/src/soc/mediatek/mt8189/Makefile.mk
@@ -49,6 +49,7 @@ ramstage-y += ../common/mt6315.c mt6315.c
 ramstage-y += ../common/mt6359p.c mt6359p.c
 ramstage-y += ../common/mtcmos.c mtcmos.c
 ramstage-y += ../common/mtk_fsp.c
+ramstage-y += ../common/pi_image.c
 ramstage-y += ../common/pmif.c ../common/pmif_clk.c ../common/pmif_init.c pmif_clk.c
 ramstage-y += ../common/pmif_spi.c pmif_spi.c
 ramstage-y += ../common/pmif_spmi.c ../common/pmif_spmi_v2.c pmif_spmi.c
@@ -70,6 +71,7 @@ firmware-files := \
 	$(CONFIG_DPM_DM_FIRMWARE) \
 	$(CONFIG_DPM_PM_FIRMWARE) \
 	$(CONFIG_MCUPM_FIRMWARE) \
+	$(CONFIG_PI_IMG_FIRMWARE) \
 	$(CONFIG_SPM_FIRMWARE) \
 	$(CONFIG_SSPM_FIRMWARE)
 
diff --git a/src/soc/mediatek/mt8189/include/soc/pi_image.h b/src/soc/mediatek/mt8189/include/soc/pi_image.h
new file mode 100644
index 0000000000..2e11011843
--- /dev/null
+++ b/src/soc/mediatek/mt8189/include/soc/pi_image.h
@@ -0,0 +1,11 @@
+/* SPDX-License-Identifier: GPL-2.0-only OR MIT */
+
+#ifndef __SOC_MEDIATEK_MT8189_PI_IMAGE_H__
+#define __SOC_MEDIATEK_MT8189_PI_IMAGE_H__
+
+#include <soc/pi_image_common.h>
+
+#define PI_IMAGE_CSRAM		(_ptp1_reserved + 0xC00)
+#define PI_IMAGE_CSRAM_SIZE	(2 * KiB)
+
+#endif  /* __SOC_MEDIATEK_MT8189_PI_IMAGE_H__ */
diff --git a/src/soc/mediatek/mt8189/soc.c b/src/soc/mediatek/mt8189/soc.c
index 5ee602f1dc..af3dee8a05 100644
--- a/src/soc/mediatek/mt8189/soc.c
+++ b/src/soc/mediatek/mt8189/soc.c
@@ -6,6 +6,7 @@
 #include <soc/emi.h>
 #include <soc/mcupm.h>
 #include <soc/mtk_fsp.h>
+#include <soc/pi_image.h>
 #include <soc/sspm.h>
 #include <symbols.h>
 
@@ -22,6 +23,7 @@ static void soc_read_resources(struct device *dev)
 static void soc_init(struct device *dev)
 {
 	mtk_fsp_init(RAMSTAGE_SOC_INIT);
+	pi_image_add_mtk_fsp_params();
 	mtk_fsp_load_and_run();
 
 	mcupm_init();

From 5993dd6ef5765a49929257d1cc94b7f37e215f3f Mon Sep 17 00:00:00 2001
From: Martin Roth <gaumless@gmail.com>
Date: Sat, 5 Apr 2025 14:58:22 -0600
Subject: [PATCH 1468/3886] Documentation: Add Timers, Stopwatch, and Delays

Change-Id: I3b58817c1ed06e6d7d5d5668b0e38ec8cfedf122
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87187
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 Documentation/lib/index.md     |   1 +
 Documentation/lib/stopwatch.md | 910 +++++++++++++++++++++++++++++++++
 2 files changed, 911 insertions(+)
 create mode 100644 Documentation/lib/stopwatch.md

diff --git a/Documentation/lib/index.md b/Documentation/lib/index.md
index f75408dd5f..b0eaf437b1 100644
--- a/Documentation/lib/index.md
+++ b/Documentation/lib/index.md
@@ -11,4 +11,5 @@ ABI data consumption <abi-data-consumption.md>
 Timestamps <timestamp.md>
 Firmware Configuration Interface <fw_config.md>
 Relocatable Modules <rmodules.md>
+Timers, Stopwatch, and Delays <stopwatch.md>
 ```
diff --git a/Documentation/lib/stopwatch.md b/Documentation/lib/stopwatch.md
new file mode 100644
index 0000000000..94817e8f07
--- /dev/null
+++ b/Documentation/lib/stopwatch.md
@@ -0,0 +1,910 @@
+# coreboot Timers, Stopwatch, Delays, and Associated Callbacks
+
+## Introduction
+
+coreboot provides several mechanisms for handling time, including
+high-precision stopwatches for profiling, simple delay functions for
+hardware timing, and a monotonic timer system that forms the foundation
+for these features. It also supports scheduling timer callbacks for
+deferred execution. These tools are crucial for performance
+optimization, debugging, ensuring proper hardware timing, and managing
+asynchronous events during the boot process.
+
+This document describes the core monotonic timer, the delay functions
+(`udelay`, `mdelay`, `delay`), the stopwatch API (`struct stopwatch`),
+and the timer callback mechanism.
+
+
+## Architecture Overview
+
+The timing facilities are layered:
+
+- **Platform Timer:** Hardware-specific implementations provide a raw
+  time source (e.g., LAPIC timer, Time Base register). These are often
+  abstracted by `timer_monotonic_get()`.
+- **Monotonic Timer:** (`src/include/timer.h`, `src/lib/timer.c`)
+  Provides a consistent time source (`struct mono_time`) counting
+  microseconds since timer initialization. Requires
+  `CONFIG(HAVE_MONOTONIC_TIMER)`.
+- **Delay Functions:** (`src/include/delay.h`, `src/lib/delay.c`,
+  `src/lib/timer.c`) Simple blocking delays (`udelay`, `mdelay`,
+  `delay`). The generic `udelay` uses the stopwatch API if yielding via
+  `thread_yield_microseconds()` is not performed.
+- **Stopwatch API:** (`src/include/timer.h`) A lightweight wrapper
+  around the monotonic timer for measuring durations and handling
+  timeouts (`struct stopwatch`,`wait_us`,`wait_ms`).
+- **Timer Callbacks:** (`src/include/timer.h`) Allows scheduling
+  functions to be called after a specified delay
+  (`struct timeout_callback`, `timer_sched_callback()`, `timers_run()`).
+
+These APIs are generally designed to be thread-safe and usable across
+different boot stages.
+
+
+## Core Monotonic Timer
+
+The foundation is the monotonic timer, enabled by
+`CONFIG(HAVE_MONOTONIC_TIMER)`. It provides a time source that
+continuously increases from an arbitrary starting point (usually near
+timer initialization).
+
+### Data Structures
+
+#### struct mono_time
+
+```c
+struct mono_time {
+    uint64_t microseconds;     // Time in microseconds since timer init
+};
+```
+Represents a point in monotonic time. Direct field access outside core
+timer code is discouraged; use helper functions.
+
+### API Functions
+
+#### timer_monotonic_get
+
+```c
+void timer_monotonic_get(struct mono_time *mt);
+```
+Retrieves the current monotonic time.
+
+**Parameters:**
+- `mt`: Pointer to a `struct mono_time` to store the current time.
+
+**Preconditions:**
+- `CONFIG(HAVE_MONOTONIC_TIMER)` must be enabled.
+- The underlying platform timer must be functional. Platform
+  implementations may require an `init_timer()` call.
+
+**Postconditions:**
+- `mt` contains the current monotonic time in microseconds.
+
+**Note:** If `CONFIG(HAVE_MONOTONIC_TIMER)` is *not* enabled, functions
+relying on it (like stopwatch functions) will generally fall back to
+basic behavior (e.g., returning 0 durations, immediate expiration
+checks).
+
+#### init_timer
+
+```c
+void init_timer(void);
+```
+
+Platform-specific timer initialization. The generic version in
+`src/lib/timer.c` is a weak empty function
+`__weak void init_timer(void) { /* do nothing */ }`. Platforms needing
+explicit timer setup (e.g., configuring frequency, enabling the
+counter) must provide their own strong implementation. Check platform
+code (`src/cpu/`, `src/soc/`) for details.
+
+#### `mono_time` Helper Functions
+
+`src/include/timer.h` also provides several inline helper functions for
+manipulating `struct mono_time` values:
+- `mono_time_set_usecs()`, `mono_time_set_msecs()`: Set time.
+- `mono_time_add_usecs()`, `mono_time_add_msecs()`: Add duration.
+- `mono_time_cmp()`: Compare two times.
+- `mono_time_after()`, `mono_time_before()`: Check time ordering.
+- `mono_time_diff_microseconds()`: Calculate difference between two
+  times.
+
+Refer to `src/include/timer.h` for their exact definitions.
+
+
+## Delay Functions
+
+coreboot provides simple functions for introducing delays.
+
+### udelay
+
+```c
+void udelay(unsigned int usecs);
+```
+Delays execution for *at least* the specified number of microseconds.
+
+**Parameters:**
+- `usecs`: Number of microseconds to delay.
+
+**Implementation Notes:**
+- The generic implementation in `src/lib/timer.c` first attempts to
+  yield using `thread_yield_microseconds()` if `CONFIG(HAS_THREADS)` is
+  enabled. If yielding handles the required delay (function returns 0),
+  `udelay` returns immediately, allowing other threads to run.
+- If `thread_yield_microseconds()` does not handle the delay (returns
+  non-zero), or if threading is disabled, the generic `udelay` falls
+  back to a busy-wait using the stopwatch API
+  (`stopwatch_init_usecs_expire()` and
+  `stopwatch_wait_until_expired()`).
+- Architecture-specific implementations (e.g., in `src/arch/`) may
+  override the generic one for better precision or efficiency.
+- Adds 1 microsecond internally to ensure the delay is *at least* the
+  requested duration.
+
+**Preconditions:**
+- If relying on the stopwatch fallback,
+  `CONFIG(HAVE_MONOTONIC_TIMER)` is needed.
+- Underlying timer (if used) must be initialized (potentially via a
+  platform `init_timer()`).
+- The delay value should be reasonable (overly large values might cause
+  issues or unexpected behavior depending on the implementation).
+
+**Example:**
+```c
+#include <delay.h>
+
+// Wait for 100 microseconds
+udelay(100);
+```
+
+### mdelay
+
+```c
+void mdelay(unsigned int msecs);
+```
+Delays execution for *at least* the specified number of milliseconds.
+
+**Parameters:**
+- `msecs`: Number of milliseconds to delay.
+
+**Implementation Notes:**
+- The generic implementation in `src/lib/delay.c` simply calls
+  `udelay(1000)` in a loop `msecs` times.
+- Therefore, it inherits the behavior of `udelay`, including the attempt
+  to yield first if `udelay` supports it.
+
+**Preconditions:**
+- Same as `udelay`.
+
+**Example:**
+```c
+#include <delay.h>
+
+// Wait for 50 milliseconds
+mdelay(50);
+```
+
+### delay
+
+```c
+void delay(unsigned int secs);
+```
+Delays execution for *at least* the specified number of seconds.
+
+**Parameters:**
+- `secs`: Number of seconds to delay.
+
+**Implementation Notes:**
+- The generic implementation in `src/lib/delay.c` simply calls
+  `mdelay(1000)` in a loop `secs` times.
+- Inherits the behavior of `mdelay` and `udelay`.
+
+**Preconditions:**
+- Same as `udelay`.
+
+**Example:**
+```c
+#include <delay.h>
+
+// Wait for 2 seconds
+delay(2);
+```
+
+
+## Stopwatch API
+
+The stopwatch API provides a convenient way to measure time durations
+and implement timeouts based on the monotonic timer.
+
+### Data Structures
+
+#### struct stopwatch
+
+```c
+#include <timer.h> // For struct stopwatch and struct mono_time
+
+struct stopwatch {
+    struct mono_time start;    // Time when stopwatch was started or initialized
+    struct mono_time current;  // Time when stopwatch was last ticked
+    struct mono_time expires;  // Expiration time for timeout operations
+};
+```
+Holds the state for a stopwatch instance.
+
+### API Functions
+
+#### Initialization Functions
+
+##### stopwatch_init
+
+```c
+#include <timer.h>
+
+static inline void stopwatch_init(struct stopwatch *sw);
+```
+Initializes a stopwatch structure. `start`, `current`, and `expires` are
+all set to the current monotonic time. Use this when you only need to
+measure elapsed duration from initialization.
+
+**Parameters:**
+- `sw`: Pointer to the stopwatch structure to initialize.
+
+**Preconditions:**
+- `sw` must point to valid memory.
+- `CONFIG(HAVE_MONOTONIC_TIMER)` should be enabled for meaningful
+  timing.
+
+**Postconditions:**
+- The stopwatch is initialized.
+
+
+##### stopwatch_init_usecs_expire
+
+```c
+#include <timer.h>
+
+static inline void stopwatch_init_usecs_expire(struct stopwatch *sw, uint64_t us);
+```
+Initializes a stopwatch and sets an expiration time `us` microseconds
+from now.
+
+**Parameters:**
+- `sw`: Pointer to the stopwatch structure.
+- `us`: Timeout duration in microseconds.
+
+**Preconditions:**
+- `sw` must point to valid memory.
+- `CONFIG(HAVE_MONOTONIC_TIMER)` should be enabled.
+
+**Postconditions:**
+- The stopwatch is initialized, and `expires` is set `us` microseconds
+  after `start`.
+
+
+##### stopwatch_init_msecs_expire
+
+```c
+#include <timer.h>
+
+static inline void stopwatch_init_msecs_expire(struct stopwatch *sw, uint64_t ms);
+```
+Initializes a stopwatch and sets an expiration time `ms` milliseconds
+from now.
+
+**Parameters:**
+- `sw`: Pointer to the stopwatch structure.
+- `ms`: Timeout duration in milliseconds.
+
+**Preconditions:**
+- `sw` must point to valid memory.
+- `CONFIG(HAVE_MONOTONIC_TIMER)` should be enabled.
+
+**Postconditions:**
+- The stopwatch is initialized, and `expires` is set `ms` milliseconds
+  after `start`.
+
+
+#### Time Measurement Functions
+
+##### stopwatch_tick
+
+```c
+#include <timer.h>
+
+static inline void stopwatch_tick(struct stopwatch *sw);
+```
+Updates the `current` time field in the stopwatch structure to the
+current monotonic time. This is often called implicitly by other
+stopwatch functions like `stopwatch_expired()` and
+`stopwatch_duration_usecs()`.
+
+**Parameters:**
+- `sw`: Pointer to the stopwatch structure.
+
+**Preconditions:**
+- The stopwatch must be initialized.
+- `CONFIG(HAVE_MONOTONIC_TIMER)` should be enabled.
+
+
+##### stopwatch_expired
+
+```c
+#include <timer.h>
+
+static inline int stopwatch_expired(struct stopwatch *sw);
+```
+Checks if the stopwatch's expiration time (`expires`) has passed. It
+implicitly calls `stopwatch_tick()` to get the current time for
+comparison.
+
+**Parameters:**
+- `sw`: Pointer to the stopwatch structure.
+
+**Returns:**
+- Non-zero (true) if `current` time >= `expires` time.
+- Zero (false) otherwise.
+
+**Preconditions:**
+- The stopwatch must be initialized (preferably with an expiration
+  time).
+- `CONFIG(HAVE_MONOTONIC_TIMER)` should be enabled.
+
+
+##### stopwatch_wait_until_expired
+
+```c
+#include <timer.h>
+
+static inline void stopwatch_wait_until_expired(struct stopwatch *sw);
+```
+Blocks (busy-waits) until the stopwatch expires by repeatedly calling
+`stopwatch_expired()`.
+
+**Parameters:**
+- `sw`: Pointer to the stopwatch structure.
+
+**Preconditions:**
+- The stopwatch must be initialized with an expiration time.
+- `CONFIG(HAVE_MONOTONIC_TIMER)` should be enabled.
+
+**Postconditions:**
+- The function returns only after the stopwatch has expired.
+
+
+#### Duration Measurement Functions
+
+##### stopwatch_duration_usecs
+
+```c
+#include <timer.h>
+
+static inline int64_t stopwatch_duration_usecs(struct stopwatch *sw);
+```
+Returns the elapsed time in microseconds between `start` and `current`.
+If `current` hasn't been updated since `stopwatch_init`, it implicitly
+calls `stopwatch_tick()` first.
+
+**Parameters:**
+- `sw`: Pointer to the stopwatch structure.
+
+**Returns:**
+- Elapsed time in microseconds (`current` - `start`).
+
+**Preconditions:**
+- The stopwatch must be initialized.
+- `CONFIG(HAVE_MONOTONIC_TIMER)` should be enabled for a meaningful
+  duration.
+
+
+##### stopwatch_duration_msecs
+
+```c
+#include <timer.h>
+
+static inline int64_t stopwatch_duration_msecs(struct stopwatch *sw);
+```
+Returns the elapsed time in milliseconds since the stopwatch was
+started. It calls `stopwatch_duration_usecs()` and divides by 1000.
+
+**Parameters:**
+- `sw`: Pointer to the stopwatch structure.
+
+**Returns:**
+- Elapsed time in milliseconds.
+
+**Preconditions:**
+- The stopwatch must be initialized.
+- `CONFIG(HAVE_MONOTONIC_TIMER)` should be enabled.
+
+
+### Utility Macros
+
+These macros combine stopwatch initialization and expiration checking with
+a user-provided condition.
+
+#### wait_us
+
+```c
+#include <timer.h>
+
+#define wait_us(timeout_us, condition) ...
+```
+Waits until a condition becomes true or a timeout elapses, whichever
+comes first. Internally uses a `struct stopwatch`.
+
+**Parameters:**
+- `timeout_us`: Timeout duration in microseconds.
+- `condition`: A C expression that evaluates to true or false. The loop
+  continues as long as the condition is false and the timeout has not
+  expired.
+
+**Returns:**
+- 0: If the condition was still false when the timeout expired.
+- >0: If the condition became true before the timeout. The return value
+  is the approximate number of microseconds waited (at least 1).
+
+**Preconditions:**
+- `CONFIG(HAVE_MONOTONIC_TIMER)` should be enabled.
+
+
+#### wait_ms
+
+```c
+#include <timer.h>
+
+#define wait_ms(timeout_ms, condition) ...
+```
+Similar to `wait_us`, but the timeout is specified in milliseconds.
+
+**Parameters:**
+- `timeout_ms`: Timeout duration in milliseconds.
+- `condition`: C expression to wait for.
+
+**Returns:**
+- 0: If the condition was still false after the timeout.
+- >0: If the condition became true before the timeout. The return value
+  is the approximate number of milliseconds waited (rounded up, at
+  least 1).
+
+**Preconditions:**
+- `CONFIG(HAVE_MONOTONIC_TIMER)` should be enabled.
+
+
+## Key differences between `mdelay` and `wait_ms`
+
+While both can be used to wait, they serve different purposes:
+
+### Purpose and Use Case
+
+- `mdelay`: Provides an *unconditional* delay for a fixed duration. The
+  generic implementation attempts to yield to other threads first (if
+  `CONFIG(HAS_THREADS)` is enabled via `udelay`), but it always waits
+  for (at least) the specified time, potentially using a busy-wait if
+  yielding doesn't occur. Primarily used for hardware timing
+  requirements or pacing operations.
+
+- `wait_ms`: Provides a *conditional* wait. It waits for a specific C
+  expression (`condition`) to become true, but *only up to* a maximum
+  timeout duration. Used when polling for a status change or event, with
+  a safeguard against waiting indefinitely.
+
+### When to Use Which
+
+#### Use `mdelay` when:
+
+- You need a guaranteed minimum delay (e.g., waiting for hardware to
+  settle after a register write).
+- You are implementing a hardware initialization sequence with specific
+  timing requirements between steps.
+- You want a simple pause, potentially allowing other threads to run if
+  the underlying `udelay` yields.
+
+**Example:**
+```c
+#include <delay.h>
+#include <arch/io.h> // For write_reg hypothetical function
+
+// Initialize hardware with specific timing requirements
+write_reg(REG_A, value);
+mdelay(10);  // Must wait (at least) 10ms after writing REG_A
+write_reg(REG_B, another_value);
+```
+
+#### Use `wait_ms` when:
+
+- You are waiting for a hardware status bit to change or a condition to
+  become true.
+- You need to implement a timeout for an operation that might fail or
+  take too long.
+- You want to know approximately how long you waited for the condition
+  to become true (via the return value).
+
+**Example:**
+```c
+#include <timer.h>
+#include <console/console.h>
+#include <arch/io.h> // For read_reg hypothetical function
+
+// Wait for hardware to become ready, but not forever
+#define STATUS_REG 0x100
+#define READY_BIT  (1 << 0)
+int64_t waited_ms = wait_ms(100, (read_reg(STATUS_REG) & READY_BIT));
+
+if (waited_ms > 0) {
+    printk(BIOS_INFO, "Hardware ready after ~%lld ms\n", waited_ms);
+} else {
+    printk(BIOS_ERR, "Timeout: Hardware failed to become ready within 100 ms\n");
+}
+```
+
+### Performance Considerations
+
+- `mdelay`: Generally simpler if the underlying `udelay` performs a
+  busy-wait. If it yields (`thread_yield_microseconds`), overhead depends
+  on the scheduler. Always waits for the full duration (approximately).
+- `wait_ms`: Involves repeated condition checking and stopwatch
+  management (`stopwatch_expired`, which calls `timer_monotonic_get`),
+  adding overhead within the loop. However, it can return early if the
+  condition becomes true, potentially saving time compared to a fixed
+  `mdelay`.
+
+### Error Handling / Feedback
+
+- `mdelay`: Provides no feedback. It simply waits.
+- `wait_ms`: Returns whether the condition was met within the timeout
+  and provides the approximate wait time if successful. This allows for
+  explicit timeout handling.
+
+### Summary
+
+Use `mdelay` for fixed, unconditional delays, potentially allowing
+thread yielding. Use `wait_ms` for conditional waits with a timeout and
+feedback on success or failure. Choose based on whether you need to poll
+for a condition or simply need to pause execution.
+
+
+## Timer Callbacks
+
+coreboot provides a mechanism to schedule functions (callbacks) to be
+executed after a certain time has elapsed. This requires
+`CONFIG(TIMER_QUEUE)`.
+
+### Data Structures
+
+#### struct timeout_callback
+
+```c
+#include <timer.h>
+
+struct timeout_callback {
+    void *priv;                     // Private data for the callback
+    void (*callback)(struct timeout_callback *tocb); // Function to call
+    /* Internal use by timer library: */
+    struct mono_time expiration;    // Calculated expiration time
+};
+```
+
+Represents a scheduled callback. The user initializes `priv` and
+`callback`.
+
+### API Functions
+
+#### timer_sched_callback
+
+```c
+#include <timer.h>
+
+int timer_sched_callback(struct timeout_callback *tocb, uint64_t us);
+```
+Schedules a callback function to run after a specified delay.
+
+**Parameters:**
+- `tocb`: Pointer to a `struct timeout_callback`. The `priv` and
+  `callback` fields must be set by the caller. The structure must
+  persist until the callback runs or is canceled (cancellation not
+  directly supported by API).
+- `us`: Delay in microseconds from the time of this call until the
+  callback should run.
+
+**Returns:**
+- 0: Success.
+- <0: Error (e.g., timer queue full, invalid arguments).
+
+**Preconditions:**
+- `CONFIG(TIMER_QUEUE)` and `CONFIG(HAVE_MONOTONIC_TIMER)` must be
+  enabled.
+- `tocb` must point to a valid structure with `callback` assigned.
+
+**Postconditions:**
+- The callback is added to a queue, to be executed when `timers_run()`
+  is called after the expiration time.
+
+
+#### timers_run
+
+```c
+#include <timer.h>
+
+int timers_run(void);
+```
+
+Checks the timer callback queue and executes any callbacks whose
+expiration time has passed. This function needs to be called
+periodically from the main execution flow (e.g., in a boot state loop
+or idle task) for callbacks to be processed.
+
+**Returns:**
+- 1: If callbacks were run or are still pending in the queue.
+- 0: If the queue is empty and no callbacks were run.
+
+**Preconditions:**
+- `CONFIG(TIMER_QUEUE)` and `CONFIG(HAVE_MONOTONIC_TIMER)` must be
+  enabled.
+
+**Usage:**
+Typically called in loops where deferred work might need processing:
+```c
+#include <timer.h>
+
+// Example main loop structure
+while (some_condition) {
+    // ... do other work ...
+
+    // Process any expired timer callbacks
+    timers_run();
+
+    // ... potentially yield or sleep ...
+}
+```
+
+
+## Usage Examples
+
+### Basic Timing Measurement Example
+
+```c
+#include <timer.h>
+#include <console/console.h>
+
+struct stopwatch sw;
+stopwatch_init(&sw);
+
+// ---> Code section to measure start
+// ... perform some operations ...
+// ---> Code section to measure end
+
+// stopwatch_duration_usecs implicitly ticks the stopwatch if needed
+int64_t duration_us = stopwatch_duration_usecs(&sw);
+printk(BIOS_INFO, "Operation took %lld microseconds\n", duration_us);
+
+// Or in milliseconds
+int64_t duration_ms = stopwatch_duration_msecs(&sw);
+printk(BIOS_INFO, "Operation took %lld milliseconds\n", duration_ms);
+```
+
+
+### Timeout Operation (Polling) Example
+
+```c
+#include <timer.h>
+#include <console/console.h>
+#include <stdint.h> // For uint8_t example
+
+// Hypothetical hardware status check
+extern uint8_t check_hardware_status(void);
+#define HW_READY (1 << 0)
+
+struct stopwatch sw;
+// Initialize stopwatch with a 100 millisecond timeout
+stopwatch_init_msecs_expire(&sw, 100);
+
+uint8_t status = 0;
+while (!(status & HW_READY)) {
+    status = check_hardware_status();
+
+    if (stopwatch_expired(&sw)) {
+        printk(BIOS_ERR, "Operation timed out waiting for HW_READY\n");
+        // Handle timeout error...
+        status = 0; // Indicate failure perhaps
+        break;
+    }
+    // Optional: Add a small delay here to avoid busy-spinning the CPU excessively
+    // udelay(10); // e.g., wait 10us between checks
+}
+
+if (status & HW_READY) {
+    printk(BIOS_DEBUG, "Hardware became ready.\n");
+    // Continue with operation...
+}
+```
+
+
+### Waiting for a Condition (Using `wait_ms`) Example
+
+```c
+#include <timer.h>
+#include <console/console.h>
+#include <stdint.h> // For uint8_t example
+
+// Hypothetical hardware status check
+extern uint8_t check_hardware_status(void);
+#define HW_READY (1 << 0)
+
+// Wait up to 100ms for the HW_READY bit
+int64_t waited_ms = wait_ms(100, (check_hardware_status() & HW_READY));
+
+if (waited_ms > 0) {
+    printk(BIOS_INFO, "Condition met: HW_READY asserted after ~%lld ms\n", waited_ms);
+    // Continue...
+} else {
+    printk(BIOS_ERR, "Timeout: HW_READY not asserted within 100 ms\n");
+    // Handle timeout error...
+}
+```
+
+### Scheduling a Timer Callback Example
+
+```c
+#include <timer.h>
+#include <console/console.h>
+
+// Data structure for our callback context
+struct my_callback_data {
+    int counter;
+    const char *message;
+};
+
+// The callback function
+static void my_callback_handler(struct timeout_callback *tocb)
+{
+    struct my_callback_data *data = tocb->priv;
+    printk(BIOS_INFO, "Callback executed! Message: %s, Counter: %d\n",
+           data->message, data->counter);
+    // Note: 'tocb' can be reused here to reschedule if needed,
+    // or the memory it points to can be freed if dynamically allocated.
+}
+
+// Somewhere in initialization code:
+static struct timeout_callback my_timer;
+static struct my_callback_data my_data;
+
+void schedule_my_task(void)
+{
+    my_data.counter = 42;
+    my_data.message = "Hello from timer";
+
+    my_timer.priv = &my_data;
+    my_timer.callback = my_callback_handler;
+
+    // Schedule the callback to run after 500 milliseconds (500,000 us)
+    int rc = timer_sched_callback(&my_timer, 500 * 1000);
+    if (rc == 0) {
+        printk(BIOS_DEBUG, "Scheduled my_callback_handler successfully.\n");
+    } else {
+        printk(BIOS_ERR, "Failed to schedule callback!\n");
+    }
+}
+
+// Remember that timers_run() must be called periodically elsewhere
+// for the callback to actually execute after the delay.
+```
+
+## Best Practices
+
+1. **Enable Monotonic Timer:** For accurate timing and stopwatch
+   functionality, ensure `CONFIG(HAVE_MONOTONIC_TIMER)` is enabled and a
+   suitable platform timer is configured.
+2. **Minimize Stopwatch Overhead:** While lightweight, frequent calls,
+   especially `timer_monotonic_get()` implicitly called by stopwatch
+   functions, can add up. Measure larger, significant code blocks rather
+   than tiny ones in tight loops unless absolutely necessary.
+3. **Use Appropriate Time Units:** Choose `usecs` or `msecs` variants
+   based on the scale of time you are dealing with.
+4. **Handle Timeouts Gracefully:** When using expiration or
+   `wait_ms`/`wait_us`, always check the result and handle the timeout
+   case appropriately. Don't assume success.
+5. **Process Timer Callbacks:** If using `timer_sched_callback`, ensure
+   `timers_run()` is called regularly in your main processing loops or
+   idle states.
+6. **Avoid `mdelay` for Polling:** Prefer `wait_ms` or manual polling
+   with `stopwatch_expired` when waiting for conditions, as `mdelay`
+   offers no timeout handling or feedback.
+7. **Consider Platform Accuracy:** Timer resolution and accuracy vary
+   between platforms. Don't assume microsecond precision unless verified
+   for the target hardware.
+
+
+## Limitations
+
+1. **Monotonic Timer Dependence:** Stopwatch and timer callbacks rely
+    heavily on `CONFIG(HAVE_MONOTONIC_TIMER)`. Without it, their
+    behavior is limited.
+2. **Timer Resolution:** Accuracy is limited by the underlying platform
+    timer's resolution and the frequency of `timer_monotonic_get()`
+    updates internally.
+3. **64-bit Microsecond Counter:** While large, the
+    `uint64_t microseconds` counter will eventually wrap around
+    (after ~584,000 years), though this is not a practical concern for
+    boot times. More relevant is the potential rollover of the
+    *underlying hardware counter* between `timer_monotonic_get` calls,
+    which the implementation must handle correctly (typically ok for
+    intervals up to several seconds).
+4. **Busy Waiting:** `stopwatch_wait_until_expired` and the internal
+   loops of `wait_us`/`wait_ms` (and potentially the fallback in
+   `udelay`/`mdelay`) perform busy-waits, consuming CPU cycles. Consider
+   alternatives like interrupt-driven timers or yielding
+   (`thread_yield_microseconds`) if power consumption or concurrency is
+   critical.
+5. **Callback Queue Size:** The timer callback queue has a fixed size
+   defined by `CONFIG(TIMER_QUEUE_SIZE)`, limiting the number of pending
+   callbacks.
+
+
+## Troubleshooting
+
+Common issues and solutions:
+
+1. **Inaccurate Timing / Durations are Zero:**
+  - Verify `CONFIG(HAVE_MONOTONIC_TIMER)` is enabled.
+  - Check if a platform-specific `init_timer()` is required and being
+    called.
+  - Ensure the platform timer frequency is correctly configured.
+  - Check for potential timer hardware issues or conflicts.
+
+2. **Timeouts Not Working / `wait_ms` Never Returns > 0:**
+  - Verify the timeout value is appropriate (not too short).
+  - Double-check the `condition` logic in `wait_ms`/`wait_us`. Is it
+    actually capable of becoming true?
+  - Ensure the stopwatch (`sw` or the internal one in `wait_ms`) is
+    properly initialized before the check loop.
+  - Confirm `CONFIG(HAVE_MONOTONIC_TIMER)` is enabled.
+
+3. **Timer Callbacks Not Running:**
+  - Verify `CONFIG(TIMER_QUEUE)` is enabled.
+  - Ensure `timer_sched_callback()` returned success (0).
+  - **Crucially:** Check that `timers_run()` is being called
+    periodically in a suitable loop after the callback was scheduled.
+  - Make sure the `struct timeout_callback` structure persists in memory
+    until the callback runs.
+
+4. **Performance Impact:**
+  - Reduce frequency of stopwatch checks or `wait_ms`/`wait_us` calls if
+    possible.
+  - Measure larger code blocks.
+  - Investigate if the underlying `udelay` implementation is
+    busy-waiting excessively; yielding (`thread_yield_microseconds`)
+    might be preferable if available and appropriate.
+
+
+## Platform-Specific Considerations
+
+The core APIs are generic, but the underlying implementation relies on
+platform code:
+- **Timer Source:** Platforms implement `timer_monotonic_get` (often
+  weakly linked) or provide the necessary hooks for it, using hardware
+  like the APIC timer (x86), Time Base (PPC), architectural timers
+  (ARM), etc.
+- **`init_timer()`:** Platforms may need a custom `init_timer` to set up
+  clocks, dividers, or enable the timer hardware.
+- **`udelay`:** Platforms might provide optimized `udelay`
+  implementations.
+
+Refer to the documentation and code within specific `src/soc/`,
+`src/cpu/`, or `src/arch/` directories for platform details.
+
+
+## References
+
+- `src/include/timer.h`: Monotonic timer, stopwatch, and callback
+  declarations.
+- `src/include/delay.h`: `udelay`, `mdelay`, `delay` declarations.
+- `src/lib/timer.c`: Generic `udelay` (using stopwatch/yield), weak
+  `init_timer`.
+- `src/lib/delay.c`: Generic `mdelay` and `delay` implementations
+  (calling `udelay`).
+- `src/lib/hardwaremain.c`: Example usage of `timers_run()` in boot
+  state machine.
+- Platform timer implementations: Search for `timer_monotonic_get` or
+  `init_timer` in `src/cpu/`, `src/soc/`, `src/arch/` directories
+  (e.g., `src/cpu/x86/lapic/apic_timer.c`,
+  `src/arch/arm64/timer.c`).

From 1e8e5d902a8ff8b91c19fd6ca8e1c75c6e10c6ee Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Mon, 30 Jun 2025 14:34:05 -0500
Subject: [PATCH 1469/3886] mb/starlabs/starlite_adl: Add support for MXC6655
 accelerometer

Add support for the Memsic MXC6655 accelerometer on I2C0, as an
alternative to the existing Kionix KCXJ9. Use the "detect" function
of the I2C generic driver to determine which is present at runtime.

TEST=build/boot starlite_adl with MXC6655, verify screen roation works
properly when detached from keyboard under Linux and Windows.

Change-Id: I59d424903cceda9871855372e1d666eaa12443b0
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88253
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
---
 .../starlabs/starlite_adl/variants/mk_v/devicetree.cb  | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/src/mainboard/starlabs/starlite_adl/variants/mk_v/devicetree.cb b/src/mainboard/starlabs/starlite_adl/variants/mk_v/devicetree.cb
index 862f31fa5c..598e2724d0 100644
--- a/src/mainboard/starlabs/starlite_adl/variants/mk_v/devicetree.cb
+++ b/src/mainboard/starlabs/starlite_adl/variants/mk_v/devicetree.cb
@@ -157,8 +157,18 @@ chip soc/intel/alderlake
 				register "has_rotation_matrix"		= "1"
 				register "rotation_matrix"		= "{1, 0, 0, 0, -1, 0, 0, 0, 1}"
 				register "cdm_index"			= "6"
+				register "detect"			= "1"
 				device i2c 0f on end
 			end
+			chip drivers/i2c/generic
+				register "hid"				= ""MXC6655""
+				register "cid"				= ""MXC6655""
+				register "desc"				= ""Accelerometer""
+				register "has_rotation_matrix"		= "1"
+				register "rotation_matrix"		= "{1, 0, 0, 0, -1, 0, 0, 0, 1}"
+				register "detect"			= "1"
+				device i2c 15 on end
+			end
 		end
 		device ref i2c2		on				# Touchscreen
 			chip drivers/i2c/hid

From 984c64295b3b399e93a9c9765fbaab5398f0c7c6 Mon Sep 17 00:00:00 2001
From: Patrick Rudolph <patrick.rudolph@9elements.com>
Date: Mon, 30 Jun 2025 13:55:15 +0200
Subject: [PATCH 1470/3886] drivers/crb/tpm: Add new method to retrieve base
 address

In order to support runtime evaluation of the TPM base address
introduce and use a new method for CRB TPMs.

Change-Id: I29c81d82947eb2603472a515f9ada598e4f8e6ea
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88249
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <inforichland@gmail.com>
---
 src/acpi/acpi.c       |  2 +-
 src/drivers/crb/tpm.c | 10 ++++++++++
 src/drivers/crb/tpm.h |  2 ++
 3 files changed, 13 insertions(+), 1 deletion(-)

diff --git a/src/acpi/acpi.c b/src/acpi/acpi.c
index 84e314c8e9..07e84f6d39 100644
--- a/src/acpi/acpi.c
+++ b/src/acpi/acpi.c
@@ -281,7 +281,7 @@ static void acpi_create_tpm2(acpi_header_t *header, void *unused)
 	tpm2->platform_class = 0;
 	if (CONFIG(CRB_TPM)) {
 		/* Must be set to 7 for CRB Support */
-		tpm2->control_area = CONFIG_CRB_TPM_BASE_ADDRESS + 0x40;
+		tpm2->control_area = crb_tpm_base_address() + 0x40;
 		tpm2->start_method = 7;
 	} else {
 		/* Must be set to 0 for FIFO interface support */
diff --git a/src/drivers/crb/tpm.c b/src/drivers/crb/tpm.c
index ea5e7017fc..c33d63428e 100644
--- a/src/drivers/crb/tpm.c
+++ b/src/drivers/crb/tpm.c
@@ -346,3 +346,13 @@ bool crb_tpm_is_active(void)
 
 	return true;
 }
+
+/*
+ * crb_tpm_base_address
+ *
+ * Returns the CRB TPM base address.
+ */
+uintptr_t crb_tpm_base_address(void)
+{
+	return CONFIG_CRB_TPM_BASE_ADDRESS;
+}
diff --git a/src/drivers/crb/tpm.h b/src/drivers/crb/tpm.h
index aaf63a4a35..dd44a2e2cc 100644
--- a/src/drivers/crb/tpm.h
+++ b/src/drivers/crb/tpm.h
@@ -68,3 +68,5 @@ size_t crb_tpm_process_command(const void *tpm2_command, size_t command_size,
 bool crb_tpm_is_active(void);
 
 tis_sendrecv_fn crb_tis_probe(enum tpm_family *family);
+
+uintptr_t crb_tpm_base_address(void);

From ac4dfa5762b5b4b364e4661a70fe048b7b91559d Mon Sep 17 00:00:00 2001
From: Keith Hui <buurin@gmail.com>
Date: Sun, 16 Mar 2025 18:09:57 -0400
Subject: [PATCH 1471/3886] mb/hp/snb_ivb_desktops: Add Compaq Pro 6300 MT/SFF
 variant

A compaq_8300_elite_sff build can run on these models mostly unmodified.
Spawn a new variant from it, tie up some obvious loose ends and bring it
officially into the fold.

BUG=https://ticket.coreboot.org/issues/581

Change-Id: Ic0f04d586a8361968d7f6c3e3d048f945528cb84
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86869
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Walter Sonius <walterav1984@gmail.com>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
---
 .../mainboard/hp/compaq_pro_6300_series.md    | 109 +++++++++++
 Documentation/mainboard/index.md              |   1 +
 src/mainboard/hp/snb_ivb_desktops/Kconfig     |   7 +
 .../hp/snb_ivb_desktops/Kconfig.name          |   3 +
 .../variants/compaq_pro_6300/board_info.txt   |   7 +
 .../variants/compaq_pro_6300/data.vbt         | Bin 0 -> 3777 bytes
 .../variants/compaq_pro_6300/early_init.c     |  13 ++
 .../compaq_pro_6300/gma-mainboard.ads         |  17 ++
 .../variants/compaq_pro_6300/gpio.c           | 176 ++++++++++++++++++
 .../variants/compaq_pro_6300/hda_verb.c       |  32 ++++
 .../variants/compaq_pro_6300/overridetree.cb  |  36 ++++
 11 files changed, 401 insertions(+)
 create mode 100644 Documentation/mainboard/hp/compaq_pro_6300_series.md
 create mode 100644 src/mainboard/hp/snb_ivb_desktops/variants/compaq_pro_6300/board_info.txt
 create mode 100644 src/mainboard/hp/snb_ivb_desktops/variants/compaq_pro_6300/data.vbt
 create mode 100644 src/mainboard/hp/snb_ivb_desktops/variants/compaq_pro_6300/early_init.c
 create mode 100644 src/mainboard/hp/snb_ivb_desktops/variants/compaq_pro_6300/gma-mainboard.ads
 create mode 100644 src/mainboard/hp/snb_ivb_desktops/variants/compaq_pro_6300/gpio.c
 create mode 100644 src/mainboard/hp/snb_ivb_desktops/variants/compaq_pro_6300/hda_verb.c
 create mode 100644 src/mainboard/hp/snb_ivb_desktops/variants/compaq_pro_6300/overridetree.cb

diff --git a/Documentation/mainboard/hp/compaq_pro_6300_series.md b/Documentation/mainboard/hp/compaq_pro_6300_series.md
new file mode 100644
index 0000000000..24a30b8be7
--- /dev/null
+++ b/Documentation/mainboard/hp/compaq_pro_6300_series.md
@@ -0,0 +1,109 @@
+# HP Compaq Pro 6300 Series
+
+This page describes how to run coreboot on the HP [Compaq Pro 6300 Series] desktop.
+
+These come in two versions: Microtower or Small Form Factor (SFF). They share the same
+mainboard (657239-001) and Maintenance and Service Guide (690362-003/c04034127). This port has
+been tested on a SFF unit.
+
+## Working
+- i3-3220 / e3-1225v2 CPUs
+- SeaBIOS (version rel-1.16.3-0-ga6ed6b70)
+- EDK2 (MrChromebox/2502)
+- Fedora-mate with Linux kernels 6.11.4, 6.13.6; KDE neon with Linux kernel 6.8.0 / 6.11.0
+- Mixed memory configurations from single 4GB to 24GB total with 1.35v & 1.5v modules
+- Integrated Ethernet
+- Serial port
+- PS/2 keyboard and mouse
+- Integrated graphics over DisplayPort and VGA port
+- libgfxinit textmode (SeaBIOS) / framebuffer (EDK2)
+- discrete GPU's show boot screen using SeaBIOS / EDK2 (LOAD_OPTION_ROMS=TRUE)
+- All SATA ports
+- All USB2 & USB3 ports
+- PCI slot (Realtek RTL8169 GbE card)
+- PCIe 3.0 x16 using 2.0 8x 10Gb Intel X540-AT2 / 1.0 16x nVidia GeForce(6200 LE / GT640-2GD3)
+- PCIe 2.0 x1 using 2.0 1x 2.5Gb Realtek RTL8125
+- PCIe 2.0 x1 using 1.0 1x 1Gb Intel 82574L (SeaBIOS loads option rom)
+- Audio built-in speaker (plays music in OS compared to legacy bleep pc-speaker)
+- Front panel audio ports (front headphone port overrides built-in speaker; only microphone
+  works with combo mic/headphone with TRRS plug)
+- Back panel audio ports
+- Sensors CPU and 4 DIMM jc42-i2c sensors
+- Booting USB / SATA(HDD/DVD)
+- LEDs HDD, Power(blinks on suspend)
+- Shutdown, Reboot, Suspend & Wake (USB keyboard & LAN)
+- Strip down Intel ME/TXE firmware and hide MEI device
+
+## Untested
+- Parallel port
+
+## Not working
+- Simultaneous use of discrete and integrated graphics
+
+## TODO
+
+The following things are still missing from this coreboot port:
+
+- Extended HWM reporting
+- Advanced LED control
+- Advanced power configuration in S3
+
+## Flashing coreboot
+
+```{eval-rst}
++---------------------+------------+
+| Type                | Value      |
++=====================+============+
+| Socketed flash      | no         |
++---------------------+------------+
+| Model               | MT25Q128A  |
++---------------------+------------+
+| Size                | 16 MiB     |
++---------------------+------------+
+| In circuit flashing | yes        |
++---------------------+------------+
+| Package             | SOIC-16    |
++---------------------+------------+
+| Write protection    | Yes        |
++---------------------+------------+
+| Dual BIOS feature   | No         |
++---------------------+------------+
+| Internal flashing   | yes        |
++---------------------+------------+
+```
+
+### Internal programming
+
+Internal flashing is possible. The SPI flash can be accessed using [flashrom],
+but you have to short the FDO pins located near the rear USB3 ports on the
+motherboard using a jumper to temporarily disable write protections while on the
+stock firmware. Remove the jumper once coreboot is installed.
+
+### External programming
+
+External programming with an SPI adapter and [flashrom] does work, but it powers the
+whole southbridge complex. You need to supply enough current through the programming adapter.
+
+If you want to use a SOIC Pomona test clip, you have to cut the 2nd DRAM DIMM holder,
+as otherwise there's not enough space near the flash.
+
+## Technology
+
+```{eval-rst}
++------------------+--------------------------------------------------+
+| Northbridge      | :doc:`../../northbridge/intel/sandybridge/index` |
++------------------+--------------------------------------------------+
+| Southbridge      | bd82x6x (Q75)                                    |
++------------------+--------------------------------------------------+
+| CPU              | model_206ax                                      |
++------------------+--------------------------------------------------+
+| SuperIO          | Nuvoton NPCD379                                  |
++------------------+--------------------------------------------------+
+| EC               |                                                  |
++------------------+--------------------------------------------------+
+| Coprocessor      | Intel ME                                         |
++------------------+--------------------------------------------------+
+```
+
+[Compaq Pro 6300 Series]: https://support.hp.com/us-en/product/details/hp-compaq-pro-6300-small-form-factor-pc/model/5232884
+[flashrom]: https://flashrom.org/Flashrom
diff --git a/Documentation/mainboard/index.md b/Documentation/mainboard/index.md
index c66b119302..7ae0ef5644 100644
--- a/Documentation/mainboard/index.md
+++ b/Documentation/mainboard/index.md
@@ -140,6 +140,7 @@ GA-H61M-S2PV <gigabyte/ga-h61m-s2pv.md>
 Compaq 8200 Elite SFF <hp/compaq_8200_sff.md>
 Compaq 8300 Elite SFF <hp/compaq_8300_sff.md>
 Compaq Elite 8300 USDT <hp/compaq_8300_usdt.md>
+Compaq Pro 6300 Series Microtower/SFF <hp/compaq_pro_6300_series.md>
 Pro 3x00 Series <hp/pro_3x00_series.md>
 Z220 Workstation SFF <hp/z220_sff.md>
 ```
diff --git a/src/mainboard/hp/snb_ivb_desktops/Kconfig b/src/mainboard/hp/snb_ivb_desktops/Kconfig
index c23e85477f..c51813b6f9 100644
--- a/src/mainboard/hp/snb_ivb_desktops/Kconfig
+++ b/src/mainboard/hp/snb_ivb_desktops/Kconfig
@@ -17,6 +17,11 @@ config BOARD_HP_SNB_IVB_DESKTOPS_COMMON
 	select SUPERIO_NUVOTON_NPCD378
 	select USE_NATIVE_RAMINIT
 
+config BOARD_HP_COMPAQ_PRO_6300
+	select BOARD_HP_SNB_IVB_DESKTOPS_COMMON
+	select BOARD_ROMSIZE_KB_16384
+	select SOUTHBRIDGE_INTEL_C216
+
 config BOARD_HP_COMPAQ_8200_ELITE_SFF_PC
 	select BOARD_HP_SNB_IVB_DESKTOPS_COMMON
 	select SOUTHBRIDGE_INTEL_BD82X6X
@@ -68,6 +73,7 @@ config MAINBOARD_DIR
 	default "hp/snb_ivb_desktops"
 
 config VARIANT_DIR
+	default "compaq_pro_6300" if BOARD_HP_COMPAQ_PRO_6300
 	default "compaq_8200_elite_sff" if BOARD_HP_COMPAQ_8200_ELITE_SFF_PC
 	default "compaq_8200_elite_usdt" if BOARD_HP_COMPAQ_8200_ELITE_USDT
 	default "compaq_8300_elite_sff" if BOARD_HP_COMPAQ_8300_ELITE_SFF
@@ -76,6 +82,7 @@ config VARIANT_DIR
 	default "z220_sff_workstation" if BOARD_HP_Z220_SFF_WORKSTATION
 
 config MAINBOARD_PART_NUMBER
+	default "HP Compaq Pro 6300 SFF/MT" if BOARD_HP_COMPAQ_PRO_6300
 	default "HP Compaq 8200 Elite SFF PC" if BOARD_HP_COMPAQ_8200_ELITE_SFF_PC
 	default "HP Compaq 8200 Elite USDT" if BOARD_HP_COMPAQ_8200_ELITE_USDT
 	default "HP Compaq 8300 Elite SFF" if BOARD_HP_COMPAQ_8300_ELITE_SFF
diff --git a/src/mainboard/hp/snb_ivb_desktops/Kconfig.name b/src/mainboard/hp/snb_ivb_desktops/Kconfig.name
index 2d3cf43620..ff5293cddc 100644
--- a/src/mainboard/hp/snb_ivb_desktops/Kconfig.name
+++ b/src/mainboard/hp/snb_ivb_desktops/Kconfig.name
@@ -1,5 +1,8 @@
 ## SPDX-License-Identifier: GPL-2.0-only
 
+config BOARD_HP_COMPAQ_PRO_6300
+	bool "Compaq Pro 6300 SFF/MT"
+
 config BOARD_HP_COMPAQ_8200_ELITE_SFF_PC
 	bool "Compaq 8200 Elite SFF"
 
diff --git a/src/mainboard/hp/snb_ivb_desktops/variants/compaq_pro_6300/board_info.txt b/src/mainboard/hp/snb_ivb_desktops/variants/compaq_pro_6300/board_info.txt
new file mode 100644
index 0000000000..ff6be95d1c
--- /dev/null
+++ b/src/mainboard/hp/snb_ivb_desktops/variants/compaq_pro_6300/board_info.txt
@@ -0,0 +1,7 @@
+Category: desktop
+Board URL: https://support.hp.com/us-en/product/details/hp-compaq-pro-6300-small-form-factor-pc/model/5232884
+ROM IC: MT25Q128A
+ROM package: SOIC-16
+ROM socketed: no
+Flashrom support: yes
+Release year: 2012
diff --git a/src/mainboard/hp/snb_ivb_desktops/variants/compaq_pro_6300/data.vbt b/src/mainboard/hp/snb_ivb_desktops/variants/compaq_pro_6300/data.vbt
new file mode 100644
index 0000000000000000000000000000000000000000..c1fd6d1e13e1e85e95810b3b83d343375b7435bd
GIT binary patch
literal 3777
zcmdT{Yitx%6h5;v`<T14?RLszyOid%AZ|-rrrTO-t#S6z(xs){c1tZp(iV2D#6ruq
z7>ExBEeXUZYvKb8(HasTBqsG2KZReSCW<Cv3_ry9M=&NN@XH|Uxih<kP^B9q5%1)?
z=iamDesdq^oVmMtFg$>XP)~GAxIY%%&|VisOo9eyi-78dB^>Kb3`au)q2X|MZ=?%P
z!ZLWR=;jrGBnTy*U_(PgZ1;3(JkVdA7~P%RzdgM(IhMj`YU=6fiAjt{Vi?-7BQ>5%
zk4~qOm>Ap;LeA-7;k`S@li0I&*Y;Gp6*&=EV?$GYV-unlTo-Iy7t~0J4eMK*8e5wl
z_ONJsq<2$1)*Tv%_4Z(IKSpDTP$JR3DcrpU<Ndvzv2bjlJ?dfkbwnm6_osJ`JvEJi
zNHqpEO{=4-5zQ%MWFkFTkD>8#?B_O9*q@q8rJqS9>phHfoDp4;03g_*_#g<vA3=}>
zmm;}3byomgc0mdWdZmC-N%sg+yC5YcJtpYY0(MLKY6)v4^n%SJ*d%~T7gTw3vqCOO
zC*IyC#f1^@dL>p0rhyZ{ZW?$6q)7niIfL??fy*SJA5cIWH$eE-WT?*>5Wj=#X$6>n
zm)WHX^Nqig_sT#j2QApt+|t^nhoc>x8@uEE1A{|bpD+%-_|l9YZe)NKD+p8-2^zGB
z0Z559m=IfFPMn1)hYL<SRQQ~5k?<SA=47A{mJyIpM_5k?5xNN52xEjjgl7qd2uBIW
z2`3336HXJ(622sSNBEI&nQ)EZ*akPUHUsEDs2D;{mRJ(J61-Xs#)+K%L|$)NFJ5J{
zPAA;Ve&vH~*7YcVlYUj=djL_AymaPdw<$$2p6d^g<aR^3em2Wa0y)L~Ufl0Pr9qR-
zxg_%W3iipBT+SDRTDKe6?CHB3%#X}B?qta8=jEaXN-1oluoPWwGfT`-n*p*1i)0Y0
z>|5aldmR+N4Dx)gnJ50&8nTrD3gs)gb@-}cx<-EFl6S!2w>r+Yyz)-@U;eVJi+n&d
zBg(~n+AP`(eUrL7;=}RL-Kp`O(OszmJIgyESq6Ft)@Z)N%@&zYtAS&Epy}FVsimp-
zaNWL3ef~B2(6PLx^D$l9J{Q#WGkJ|K0L=$PYcrMR19mVoEwzM<>7LYb@LUd{lm(y+
zey67lG6I72oTIdDJ+;EEmY=h%_yW#TdO7dBE*vhsKU;iVg_ZJVxF8!DytLBm8mY3z
zR1~5K_-IR~{_-W&uY<T$#z$mzlgu8M@p)N2DzoD<ek!Zq$n2tw0#i#FTgfoO)Xj_y
zGd#r9w-|em;b%<!fw7+%%5HUqn?2yhF1NbP&BomLid%ix%|3GD*KYMEH~ZC%C5pOA
zVRZ^76g8!=2?gI!)DIN)iGtrN>ScvpQ?SgVuJy2oJf51Xl3}|f7$xML<O8m>LT5N+
zQ%reX@RGC_KS=3(;qu9Ca;}8pkZo~>*<yr-p>hluRsw>G<^wj`FDeSpOp7xtj05h@
zmg~~}LgEZ<cU{H8xZz=7x%@u6zaWNv*ys1^-ucMm;bZ1Dr7(ttk;)m&%Z;Kt<_eg@
z!pP=<YbG3J&|b(+K3O?<st+o(j!f<>e6*7pGv(4$3fYI}>NB$={t8{gTu!3Xlrpk;
znufEGRRr3M*~z(8#8AUW0rv-c#{2>)v-X(+{Ne5D+4FrfRa*S`@_7ak+`LUYSqOtx
zqn{g@Nou}6>w3cHAd)+BhJWajCWFUfuwwzMxZ;P|I4;)|Ey72c`ygg09%&ASv&Hm>
zyT_)j)$r|Usndt*Zk>e)#U=w?q8y9IMYRqi29%C?y(N5<H3#tWmQvt%>VIRlb`Ll<
jo};Vgse4yv?<loP;YbH<W(*i?hB*D*tQFpbU&KEFn>cY9

literal 0
HcmV?d00001

diff --git a/src/mainboard/hp/snb_ivb_desktops/variants/compaq_pro_6300/early_init.c b/src/mainboard/hp/snb_ivb_desktops/variants/compaq_pro_6300/early_init.c
new file mode 100644
index 0000000000..aace18dfa8
--- /dev/null
+++ b/src/mainboard/hp/snb_ivb_desktops/variants/compaq_pro_6300/early_init.c
@@ -0,0 +1,13 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <bootblock_common.h>
+#include <superio/nuvoton/npcd378/npcd378.h>
+#include <superio/nuvoton/common/nuvoton.h>
+
+#define SERIAL_DEV PNP_DEV(0x2e, NPCD378_SP2)
+
+void bootblock_mainboard_early_init(void)
+{
+	if (CONFIG(CONSOLE_SERIAL))
+		nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
+}
diff --git a/src/mainboard/hp/snb_ivb_desktops/variants/compaq_pro_6300/gma-mainboard.ads b/src/mainboard/hp/snb_ivb_desktops/variants/compaq_pro_6300/gma-mainboard.ads
new file mode 100644
index 0000000000..686f7d44db
--- /dev/null
+++ b/src/mainboard/hp/snb_ivb_desktops/variants/compaq_pro_6300/gma-mainboard.ads
@@ -0,0 +1,17 @@
+-- SPDX-License-Identifier: GPL-2.0-or-later
+
+with HW.GFX.GMA;
+with HW.GFX.GMA.Display_Probing;
+
+use HW.GFX.GMA;
+use HW.GFX.GMA.Display_Probing;
+
+private package GMA.Mainboard is
+
+   ports : constant Port_List :=
+     (DP2,
+      HDMI2,
+      Analog,
+      others => Disabled);
+
+end GMA.Mainboard;
diff --git a/src/mainboard/hp/snb_ivb_desktops/variants/compaq_pro_6300/gpio.c b/src/mainboard/hp/snb_ivb_desktops/variants/compaq_pro_6300/gpio.c
new file mode 100644
index 0000000000..e43a4e8e69
--- /dev/null
+++ b/src/mainboard/hp/snb_ivb_desktops/variants/compaq_pro_6300/gpio.c
@@ -0,0 +1,176 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <southbridge/intel/common/gpio.h>
+
+static const struct pch_gpio_set1 pch_gpio_set1_mode = {
+	.gpio0 = GPIO_MODE_GPIO,
+	.gpio1 = GPIO_MODE_GPIO,
+	.gpio2 = GPIO_MODE_NATIVE,
+	.gpio3 = GPIO_MODE_NATIVE,
+	.gpio4 = GPIO_MODE_NATIVE,
+	.gpio5 = GPIO_MODE_NATIVE,
+	.gpio6 = GPIO_MODE_GPIO,
+	.gpio7 = GPIO_MODE_GPIO,
+	.gpio8 = GPIO_MODE_GPIO,
+	.gpio9 = GPIO_MODE_NATIVE,
+	.gpio10 = GPIO_MODE_NATIVE,
+	.gpio11 = GPIO_MODE_GPIO,
+	.gpio12 = GPIO_MODE_NATIVE,
+	.gpio13 = GPIO_MODE_GPIO,
+	.gpio14 = GPIO_MODE_NATIVE,
+	.gpio15 = GPIO_MODE_GPIO,
+	.gpio16 = GPIO_MODE_GPIO,
+	.gpio17 = GPIO_MODE_GPIO,
+	.gpio18 = GPIO_MODE_NATIVE,
+	.gpio19 = GPIO_MODE_NATIVE,
+	.gpio20 = GPIO_MODE_NATIVE,
+	.gpio21 = GPIO_MODE_GPIO,
+	.gpio22 = GPIO_MODE_GPIO,
+	.gpio23 = GPIO_MODE_NATIVE,
+	.gpio24 = GPIO_MODE_GPIO,
+	.gpio25 = GPIO_MODE_NATIVE,
+	.gpio26 = GPIO_MODE_NATIVE,
+	.gpio27 = GPIO_MODE_GPIO,
+	.gpio28 = GPIO_MODE_GPIO,
+	.gpio29 = GPIO_MODE_GPIO,
+	.gpio30 = GPIO_MODE_NATIVE,
+	.gpio31 = GPIO_MODE_GPIO,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_direction = {
+	.gpio0 = GPIO_DIR_INPUT,
+	.gpio1 = GPIO_DIR_INPUT,
+	.gpio6 = GPIO_DIR_INPUT,
+	.gpio7 = GPIO_DIR_INPUT,
+	.gpio8 = GPIO_DIR_INPUT,
+	.gpio11 = GPIO_DIR_INPUT,
+	.gpio13 = GPIO_DIR_INPUT,
+	.gpio15 = GPIO_DIR_OUTPUT,
+	.gpio16 = GPIO_DIR_INPUT,
+	.gpio17 = GPIO_DIR_OUTPUT,
+	.gpio21 = GPIO_DIR_INPUT,
+	.gpio22 = GPIO_DIR_INPUT,
+	.gpio24 = GPIO_DIR_INPUT,
+	.gpio27 = GPIO_DIR_INPUT,
+	.gpio28 = GPIO_DIR_OUTPUT,
+	.gpio29 = GPIO_DIR_OUTPUT,
+	.gpio31 = GPIO_DIR_INPUT,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_level = {
+	.gpio15 = GPIO_LEVEL_LOW,
+	.gpio17 = GPIO_LEVEL_LOW,
+	.gpio28 = GPIO_LEVEL_LOW,
+	.gpio29 = GPIO_LEVEL_HIGH,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_invert = {
+	.gpio0 = GPIO_INVERT,
+	.gpio1 = GPIO_INVERT,
+	.gpio6 = GPIO_INVERT,
+	.gpio11 = GPIO_INVERT,
+	.gpio13 = GPIO_INVERT,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_zero = {
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_mode = {
+	.gpio32 = GPIO_MODE_GPIO,
+	.gpio33 = GPIO_MODE_GPIO,
+	.gpio34 = GPIO_MODE_GPIO,
+	.gpio35 = GPIO_MODE_GPIO,
+	.gpio36 = GPIO_MODE_GPIO,
+	.gpio37 = GPIO_MODE_GPIO,
+	.gpio38 = GPIO_MODE_GPIO,
+	.gpio39 = GPIO_MODE_GPIO,
+	.gpio40 = GPIO_MODE_NATIVE,
+	.gpio41 = GPIO_MODE_NATIVE,
+	.gpio42 = GPIO_MODE_NATIVE,
+	.gpio43 = GPIO_MODE_GPIO,
+	.gpio44 = GPIO_MODE_NATIVE,
+	.gpio45 = GPIO_MODE_NATIVE,
+	.gpio46 = GPIO_MODE_GPIO,
+	.gpio47 = GPIO_MODE_NATIVE,
+	.gpio48 = GPIO_MODE_GPIO,
+	.gpio49 = GPIO_MODE_GPIO,
+	.gpio50 = GPIO_MODE_NATIVE,
+	.gpio51 = GPIO_MODE_NATIVE,
+	.gpio52 = GPIO_MODE_NATIVE,
+	.gpio53 = GPIO_MODE_NATIVE,
+	.gpio54 = GPIO_MODE_GPIO,
+	.gpio55 = GPIO_MODE_NATIVE,
+	.gpio56 = GPIO_MODE_NATIVE,
+	.gpio57 = GPIO_MODE_GPIO,
+	.gpio58 = GPIO_MODE_NATIVE,
+	.gpio59 = GPIO_MODE_NATIVE,
+	.gpio60 = GPIO_MODE_NATIVE,
+	.gpio61 = GPIO_MODE_GPIO,
+	.gpio62 = GPIO_MODE_NATIVE,
+	.gpio63 = GPIO_MODE_NATIVE,
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_direction = {
+	.gpio32 = GPIO_DIR_INPUT,
+	.gpio33 = GPIO_DIR_INPUT,
+	.gpio34 = GPIO_DIR_INPUT,
+	.gpio35 = GPIO_DIR_INPUT,
+	.gpio36 = GPIO_DIR_INPUT,
+	.gpio37 = GPIO_DIR_INPUT,
+	.gpio38 = GPIO_DIR_INPUT,
+	.gpio39 = GPIO_DIR_INPUT,
+	.gpio43 = GPIO_DIR_INPUT,
+	.gpio46 = GPIO_DIR_INPUT,
+	.gpio48 = GPIO_DIR_INPUT,
+	.gpio49 = GPIO_DIR_INPUT,
+	.gpio54 = GPIO_DIR_INPUT,
+	.gpio57 = GPIO_DIR_INPUT,
+	.gpio61 = GPIO_DIR_INPUT,
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_mode = {
+	.gpio64 = GPIO_MODE_NATIVE,
+	.gpio65 = GPIO_MODE_NATIVE,
+	.gpio66 = GPIO_MODE_NATIVE,
+	.gpio67 = GPIO_MODE_NATIVE,
+	.gpio68 = GPIO_MODE_GPIO,
+	.gpio69 = GPIO_MODE_GPIO,
+	.gpio70 = GPIO_MODE_GPIO,
+	.gpio71 = GPIO_MODE_GPIO,
+	.gpio72 = GPIO_MODE_GPIO,
+	.gpio73 = GPIO_MODE_NATIVE,
+	.gpio74 = GPIO_MODE_NATIVE,
+	.gpio75 = GPIO_MODE_NATIVE,
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_direction = {
+	.gpio68 = GPIO_DIR_INPUT,
+	.gpio69 = GPIO_DIR_INPUT,
+	.gpio70 = GPIO_DIR_INPUT,
+	.gpio71 = GPIO_DIR_OUTPUT,
+	.gpio72 = GPIO_DIR_INPUT,
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_level = {
+	.gpio71 = GPIO_LEVEL_LOW,
+};
+
+const struct pch_gpio_map mainboard_gpio_map = {
+	.set1 = {
+		.mode		= &pch_gpio_set1_mode,
+		.direction	= &pch_gpio_set1_direction,
+		.level		= &pch_gpio_set1_level,
+		.blink		= &pch_gpio_set1_zero,
+		.invert		= &pch_gpio_set1_invert,
+		.reset		= &pch_gpio_set1_zero,
+	},
+	.set2 = {
+		.mode		= &pch_gpio_set2_mode,
+		.direction	= &pch_gpio_set2_direction,
+	},
+	.set3 = {
+		.mode		= &pch_gpio_set3_mode,
+		.direction	= &pch_gpio_set3_direction,
+		.level		= &pch_gpio_set3_level,
+	},
+};
diff --git a/src/mainboard/hp/snb_ivb_desktops/variants/compaq_pro_6300/hda_verb.c b/src/mainboard/hp/snb_ivb_desktops/variants/compaq_pro_6300/hda_verb.c
new file mode 100644
index 0000000000..2a7a9d9f3a
--- /dev/null
+++ b/src/mainboard/hp/snb_ivb_desktops/variants/compaq_pro_6300/hda_verb.c
@@ -0,0 +1,32 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <device/azalia_device.h>
+
+const u32 cim_verb_data[] = {
+	0x10ec0221,	/* Codec Vendor / Device ID: Realtek */
+	0x103c339a,	/* Subsystem ID */
+	11,		/* Number of 4 dword sets */
+	AZALIA_SUBVENDOR(0, 0x103c339a),
+	AZALIA_PIN_CFG(0, 0x12, AZALIA_PIN_CFG_NC(0)),
+	AZALIA_PIN_CFG(0, 0x14, 0x01014020),
+	AZALIA_PIN_CFG(0, 0x17, 0x90170110),
+	AZALIA_PIN_CFG(0, 0x18, AZALIA_PIN_CFG_NC(0)),
+	AZALIA_PIN_CFG(0, 0x19, AZALIA_PIN_CFG_NC(0)),
+	AZALIA_PIN_CFG(0, 0x1a, 0x02a11c3f),
+	AZALIA_PIN_CFG(0, 0x1b, 0x01813c30),
+	AZALIA_PIN_CFG(0, 0x1d, 0x598301f0),
+	AZALIA_PIN_CFG(0, 0x1e, AZALIA_PIN_CFG_NC(0)),
+	AZALIA_PIN_CFG(0, 0x21, 0x0221102f),
+
+	0x80862806,	/* Codec Vendor / Device ID: Intel */
+	0x80860101,	/* Subsystem ID */
+	4,		/* Number of 4 dword sets */
+	AZALIA_SUBVENDOR(3, 0x80860101),
+	AZALIA_PIN_CFG(3, 0x05, 0x58560010),
+	AZALIA_PIN_CFG(3, 0x06, 0x18560020),
+	AZALIA_PIN_CFG(3, 0x07, 0x58560030),
+};
+
+const u32 pc_beep_verbs[0] = {};
+
+AZALIA_ARRAY_SIZES;
diff --git a/src/mainboard/hp/snb_ivb_desktops/variants/compaq_pro_6300/overridetree.cb b/src/mainboard/hp/snb_ivb_desktops/variants/compaq_pro_6300/overridetree.cb
new file mode 100644
index 0000000000..243fa25a53
--- /dev/null
+++ b/src/mainboard/hp/snb_ivb_desktops/variants/compaq_pro_6300/overridetree.cb
@@ -0,0 +1,36 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
+chip northbridge/intel/sandybridge
+	device domain 0 on
+		subsystemid 0x103c 0x339a inherit
+
+		chip southbridge/intel/bd82x6x
+			register "sata_port_map" = "0x17"
+				# 0 = Blue
+				# 1 = White #1
+				# 2 = White #2
+				# 3,5 not implemented
+				# 4 = Black (eSATA)
+			register "superspeed_capable_ports" = "0xf"
+			register "xhci_switchable_ports"    = "0xf"
+			register "usb_port_config" = "{
+				{1, 0x84b, 0},
+				{1, 0x84b, 0},
+				{1, 0xa4b, 1},
+				{1, 0xa4b, 1},
+				{1, 0xb43, 2},
+				{1, 0x94b, 2},
+				{1, 0x94f, 3},
+				{1, 0xb53, 3},
+				{1, 1, 4},
+				{1, 5, 4},
+				{1, 0x65b, 6},
+				{1, 0x65f, 5},
+				{1, 0x84b, 5},
+				{1, 0x94b, 6},
+			}"
+
+			device ref xhci on end
+		end
+	end
+end

From faf0f29f8dcde9e6c6ed6358c1dbd9fa2da4a59d Mon Sep 17 00:00:00 2001
From: "P, Usha" <usha.p@intel.com>
Date: Tue, 24 Jun 2025 10:49:50 +0530
Subject: [PATCH 1472/3886] mb/google/ocelot: Update EC host command range for
 variants

This patch updates the EC host command range configuration for Ocelot
board variants, ensuring that each variant uses the correct range based
on its specific EC.

BOARD_GOOGLE_OCELOTMCHP and BOARD_GOOGLE_OCELOTMCHP4ES uses Microchip
EC.
BOARD_GOOGLE_OCELOT and BOARD_GOOGLE_OCELOT4ES uses Nuvoton EC.
BOARD_GOOGLE_OCELOTITE and BOARD_GOOGLE_OCELOTITE4ES uses ITE EC.

Key changes:
- Microchip EC: Configured to use host command ranges 0x800-0x807 and
0x200-0x20f. The register is set to 0x00040801 to accommodate these
constraints.

BUG=b:394208231
TEST=Build Ocelot and verify it compiles without any error.

Change-Id: If08f2362a7b3bafca69375ce3b346f75435a83df
Signed-off-by: P, Usha <usha.p@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88179
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 .../google/ocelot/variants/baseboard/ocelot/devicetree.cb      | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/src/mainboard/google/ocelot/variants/baseboard/ocelot/devicetree.cb b/src/mainboard/google/ocelot/variants/baseboard/ocelot/devicetree.cb
index 1ac4027eec..b79a3b3674 100644
--- a/src/mainboard/google/ocelot/variants/baseboard/ocelot/devicetree.cb
+++ b/src/mainboard/google/ocelot/variants/baseboard/ocelot/devicetree.cb
@@ -8,7 +8,8 @@ chip soc/intel/pantherlake
 	#	EC host command ranges are in 0x800-0x807 & 0x200-0x20f
 	# For Ocelot variants with ITE/Nuvoton EC:
 	# 	EC host command ranges are in 0x800-0x8ff & 0x200-0x20f
-	register "gen1_dec" = "CONFIG(BOARD_GOOGLE_OCELOT)? 0x00040801 : 0x00fc0801"
+	register "gen1_dec" = "CONFIG(BOARD_GOOGLE_OCELOTMCHP) ||
+			CONFIG(BOARD_GOOGLE_OCELOTMCHP4ES)? 0x00040801 : 0x00fc0801"
 	register "gen2_dec" = "0x000c0201"
 	# EC memory map range is 0x900-0x9ff
 	register "gen3_dec" = "0x00fc0901"

From 10d01fc2de8113e7bdf05c6a48e587cf829ac984 Mon Sep 17 00:00:00 2001
From: Martin Roth <gaumless@gmail.com>
Date: Sat, 5 Apr 2025 14:58:54 -0600
Subject: [PATCH 1473/3886] Documentation: Add Threads

Change-Id: I49a273118f19e4b332ac7f51b1f34247acf66b85
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87188
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
---
 Documentation/lib/index.md   |   1 +
 Documentation/lib/threads.md | 310 +++++++++++++++++++++++++++++++++++
 2 files changed, 311 insertions(+)
 create mode 100644 Documentation/lib/threads.md

diff --git a/Documentation/lib/index.md b/Documentation/lib/index.md
index b0eaf437b1..a877f3bce9 100644
--- a/Documentation/lib/index.md
+++ b/Documentation/lib/index.md
@@ -12,4 +12,5 @@ Timestamps <timestamp.md>
 Firmware Configuration Interface <fw_config.md>
 Relocatable Modules <rmodules.md>
 Timers, Stopwatch, and Delays <stopwatch.md>
+Threads <threads.md>
 ```
diff --git a/Documentation/lib/threads.md b/Documentation/lib/threads.md
new file mode 100644
index 0000000000..6b2d9977d0
--- /dev/null
+++ b/Documentation/lib/threads.md
@@ -0,0 +1,310 @@
+# coreboot Threads
+
+## Thread Management
+
+coreboot provides a cooperative threading system that allows for
+concurrent execution of tasks during the boot process. The thread API is
+particularly useful for implementing asynchronous operations and
+managing hardware initialization sequences.
+
+
+### Thread Creation and Management
+
+#### thread_run
+
+```c
+int thread_run(struct thread_handle *handle, enum cb_err (*func)(void *), void *arg)
+```
+Creates and starts a new thread to execute the specified function.
+
+**Parameters:**
+- `handle`: Pointer to a thread handle structure to track thread state
+  (Note: `struct thread_handle` is an opaque structure used by the API
+  to manage the thread's state.)
+- `func`: Function to execute in the new thread
+- `arg`: Argument to pass to the function
+
+**Returns:**
+- 0 on success
+- < 0 on failure
+
+**Example:**
+```c
+struct thread_handle th;
+enum cb_err thread_func(void *arg) {
+    // Thread work here
+    return CB_SUCCESS;
+}
+
+if (thread_run(&th, thread_func, NULL) < 0) {
+    printk(BIOS_ERR, "Failed to create thread\n");
+} else {
+    // Wait for the thread to complete and check its status
+    enum cb_err err = thread_join(&th);
+    if (err != CB_SUCCESS) {
+        printk(BIOS_ERR, "Thread failed with error %d\n", err);
+    }
+}
+```
+
+
+#### thread_run_until
+
+```c
+int thread_run_until(struct thread_handle *handle, enum cb_err (*func)(void *), void *arg,
+                    boot_state_t state, boot_state_sequence_t seq)
+```
+Creates a thread that blocks boot state transitions until completion.
+
+**Parameters:**
+- `handle`: Pointer to a thread handle structure
+- `func`: Function to execute
+- `arg`: Argument to pass to the function
+- `state`: Boot state to block
+- `seq`: Boot state sequence to block
+
+**Returns:**
+- 0 on success
+- < 0 on failure
+
+**Example:**
+```c
+struct thread_handle th;
+enum cb_err init_func(void *arg) {
+    // Hardware initialization
+    return CB_SUCCESS;
+}
+
+// Block BS_DEV_ENABLE until initialization completes
+thread_run_until(&th, init_func, NULL, BS_DEV_ENABLE, 0);
+```
+
+
+### Thread Synchronization
+
+#### thread_join
+
+```c
+enum cb_err thread_join(struct thread_handle *handle)
+```
+Waits for a thread to complete and returns its error code.
+
+**Parameters:**
+- `handle`: Thread handle to wait for
+
+**Returns:**
+- Thread's error code (e.g., `CB_SUCCESS`, `CB_ERR`). See
+  `src/include/cb_err.h` for details.
+
+**Example:**
+```c
+struct thread_handle th;
+// ... create thread ...
+
+enum cb_err err = thread_join(&th);
+if (err != CB_SUCCESS) {
+    printk(BIOS_ERR, "Thread failed with error %d\n", err);
+}
+```
+
+
+### Thread Yielding
+
+Yielding is crucial in a cooperative multitasking system like
+coreboot's. Threads must explicitly yield control using `thread_yield`
+or `thread_yield_microseconds` to allow other threads to run. Failure to
+yield can lead to a single thread monopolizing the CPU, preventing other
+tasks from executing.
+
+#### thread_yield
+
+```c
+int thread_yield(void)
+```
+Yields the current thread's execution to allow other threads to run.
+
+**Returns:**
+- 0 on success
+- < 0 if thread cannot yield
+
+**Example:**
+```c
+while (!condition) {
+    if (thread_yield() < 0) {
+        printk(BIOS_ERR, "Failed to yield thread\n");
+        break;
+    }
+}
+```
+
+
+#### thread_yield_microseconds
+
+```c
+int thread_yield_microseconds(unsigned int microsecs)
+```
+Yields the current thread for a specified number of microseconds.
+
+**Parameters:**
+- `microsecs`: Number of microseconds to yield
+
+**Returns:**
+- 0 on success
+- < 0 if thread cannot yield
+
+**Example:**
+```c
+// Wait for 100 microseconds
+if (thread_yield_microseconds(100) < 0) {
+    printk(BIOS_ERR, "Failed to yield thread\n");
+}
+```
+
+
+### Thread Cooperation Control
+
+#### thread_coop_enable
+
+```c
+void thread_coop_enable(void)
+```
+Enables cooperative behavior for the current thread.
+
+**Example:**
+```c
+thread_coop_enable();  // Allow thread to yield
+```
+
+#### thread_coop_disable
+
+```c
+void thread_coop_disable(void)
+```
+Disables cooperative behavior for the current thread.
+
+**Example:**
+```c
+thread_coop_disable();  // Prevent thread from yielding
+```
+
+
+### Thread Mutexes
+
+#### thread_mutex_lock
+
+```c
+void thread_mutex_lock(struct thread_mutex *mutex)
+```
+Acquires a mutex lock, waiting if necessary.
+
+**Parameters:**
+- `mutex`: Mutex to lock
+
+**Example:**
+```c
+struct thread_mutex mtx = THREAD_MUTEX_INITIALIZER; // Or = { .locked = false };
+thread_mutex_lock(&mtx);
+// Critical section
+thread_mutex_unlock(&mtx);
+```
+
+
+#### thread_mutex_unlock
+
+```c
+void thread_mutex_unlock(struct thread_mutex *mutex)
+```
+Releases a mutex lock.
+
+**Parameters:**
+- `mutex`: Mutex to unlock
+
+## Best Practices
+
+1. **Thread Safety**:
+   - Use mutexes to protect shared resources
+   - Be careful with global variables in threaded code
+   - Consider thread cooperation when implementing critical sections
+
+2. **Resource Management**:
+   - Always join threads that you create using `thread_run` to check
+     their completion status and clean up resources. Threads started
+     with `thread_run_until` are implicitly managed by the boot state
+     machine and typically do not require explicit joining.
+   - Consistently check return values from thread creation and operation
+     functions (like `thread_run`, `thread_yield`, `thread_join`) to
+     detect errors early.
+   - Clean up resources allocated or used within thread functions before
+     they exit.
+
+3. **Performance Considerations**:
+   - Use thread_yield_microseconds for precise timing
+   - Minimize time spent in critical sections
+   - Consider using thread_run_until for hardware initialization
+
+4. **Error Handling**:
+   - Check thread creation and operation return values (as noted in
+     Resource Management).
+   - Implement proper error handling within thread functions, returning
+     appropriate `cb_err` values.
+   - Use `thread_join` (for `thread_run` threads) to check the final
+     completion status.
+
+
+## Common Patterns
+
+### Hardware Initialization
+
+```c
+struct thread_handle init_th;
+enum cb_err init_hardware(void *arg) {
+    // Initialize hardware
+    if (hardware_init() != 0)
+        return CB_ERR;
+    return CB_SUCCESS;
+}
+
+// Run initialization in a thread
+thread_run_until(&init_th, init_hardware, NULL, BS_DEV_ENABLE, 0);
+```
+
+### Asynchronous Operation
+
+```c
+struct thread_handle async_th;
+enum cb_err async_operation(void *arg) {
+    // Perform async operation
+    while (!operation_complete()) {
+        if (thread_yield() < 0)
+            return CB_ERR;
+    }
+    return CB_SUCCESS;
+}
+
+// Start async operation
+thread_run(&async_th, async_operation, NULL);
+```
+
+
+### Critical Section Protection
+
+```c
+struct thread_mutex resource_mtx = { .locked = false };
+
+void access_shared_resource(void) {
+    thread_mutex_lock(&resource_mtx);
+    // Access shared resource
+    thread_mutex_unlock(&resource_mtx);
+}
+```
+
+## Limitations
+
+1. The thread system is cooperative, not preemptive.
+2. Threads must explicitly yield to allow other threads to run.
+3. Thread operations are typically only available after RAM
+   initialization (in ramstage and later). Check specific environment
+   constraints if unsure.
+4. Thread count is limited by the `CONFIG_NUM_THREADS` Kconfig option.
+5. Thread stack size is fixed by the `CONFIG_STACK_SIZE` Kconfig option.
+

From d24c4086e1af098566dc07bf7fe81a01e35b35f0 Mon Sep 17 00:00:00 2001
From: Martin Roth <gaumless@gmail.com>
Date: Sat, 5 Apr 2025 15:52:08 -0600
Subject: [PATCH 1474/3886] Documentation: Add Ramstage Bootstates

Change-Id: I18801967be50e2f318b4404d08c171ffa7e92bbc
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87189
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
---
 Documentation/lib/index.md               |   1 +
 Documentation/lib/ramstage_bootstates.md | 514 +++++++++++++++++++++++
 2 files changed, 515 insertions(+)
 create mode 100644 Documentation/lib/ramstage_bootstates.md

diff --git a/Documentation/lib/index.md b/Documentation/lib/index.md
index a877f3bce9..7edac1ebf6 100644
--- a/Documentation/lib/index.md
+++ b/Documentation/lib/index.md
@@ -13,4 +13,5 @@ Firmware Configuration Interface <fw_config.md>
 Relocatable Modules <rmodules.md>
 Timers, Stopwatch, and Delays <stopwatch.md>
 Threads <threads.md>
+Ramstage Bootstates & Bootstate Callbacks <ramstage_bootstates.md>
 ```
diff --git a/Documentation/lib/ramstage_bootstates.md b/Documentation/lib/ramstage_bootstates.md
new file mode 100644
index 0000000000..20205be5e1
--- /dev/null
+++ b/Documentation/lib/ramstage_bootstates.md
@@ -0,0 +1,514 @@
+# coreboot Ramstage Bootstates & Bootstate Callbacks
+
+## Introduction
+
+The coreboot boot process is divided into several discrete phases, one
+of which is **ramstage**. Ramstage is the phase where the main hardware
+initialization and device setup occurs after memory initialization.
+Within ramstage, a state machine called the **bootstate machine**
+manages the sequence of operations needed to initialize the system,
+configure devices, and prepare to load and execute the payload (such as
+a bootloader, operating system, or firmware utility).
+
+The bootstate machine provides a structured and extensible way to
+organize code execution during the boot process. It allows for clear
+separation of concerns between different initialization phases and
+provides hooks for component-specific code to run at well-defined
+points.
+
+**Important Note:** The exact execution order of multiple callbacks
+registered for the same state and sequence (entry/exit) is not
+guaranteed. This means that you cannot depend on one call for the
+state/sequence in any other calls to the same state/sequence. If this
+ordering is required, join the calls to the two functions into a single
+function which specifies the order and create a callback to call the
+top-level function instead of the two individual callbacks.
+
+
+## Bootstate Machine Architecture
+
+The bootstate machine's public API is defined in
+`src/include/bootstate.h`, and its core implementation resides in
+`src/lib/hardwaremain.c`. At its core, it consists of:
+
+1. A series of sequential states that represent phases of the boot process
+2. A mechanism for callback registration to execute code during state transitions
+3. A framework for blocking and unblocking state transitions
+4. Timing and debugging facilities to measure and report performance during boot
+
+
+### Key Data Structures
+
+The primary public data structure for interacting with the bootstate
+machine is `struct boot_state_callback`. The internal implementation
+also uses `struct boot_state` and `struct boot_phase`.
+
+
+#### Boot State Callback (Public API)
+
+Callbacks that run during state transitions are defined by this
+structure in `src/include/bootstate.h`:
+
+```c
+struct boot_state_callback {
+    void *arg;                  // Argument to pass to the callback
+    void (*callback)(void *arg); // Function pointer to the callback
+    struct boot_state_callback *next; // Next callback in linked list (internal use)
+#if CONFIG(DEBUG_BOOT_STATE)
+    const char *location;       // Source location for debugging
+#endif
+};
+```
+
+#### Boot State Sequence (Public API)
+
+The boot state sequence type, defined in `src/include/bootstate.h`,
+specifies when a callback should run relative to the state's main
+action:
+
+```c
+typedef enum {
+    BS_ON_ENTRY,                // Execute before state function
+    BS_ON_EXIT                  // Execute after state function
+} boot_state_sequence_t;
+```
+
+
+#### Boot State (Internal Implementation)
+
+The main internal data structure in `src/lib/hardwaremain.c` is
+`struct boot_state`, which defines a single state in the bootstate
+machine:
+
+```c
+struct boot_state {
+    const char *name;           // Human-readable name of the state
+    boot_state_t id;            // Enumerated identifier for the state
+    u8 post_code;               // POST code to output during state execution
+    struct boot_phase phases[2]; // Entry and exit phases (internal use)
+    boot_state_t (*run_state)(void *arg); // Function to execute during the state
+    void *arg;                  // Argument to pass to the run_state function
+    int num_samples;            // Counter for timing samples (internal use)
+    bool complete;              // Flag indicating if state has completed (internal use)
+};
+```
+
+
+#### Boot Phase (Internal Implementation)
+
+Each boot state has two internal phases ("entry" and "exit") represented
+by `struct boot_phase` in `src/lib/hardwaremain.c`:
+
+```c
+struct boot_phase {
+    struct boot_state_callback *callbacks; // Linked list of callbacks
+    int blockers;               // Counter for blocking state transition
+};
+```
+
+## Bootstate Sequence
+
+The bootstate machine defines the following sequence of states, executed
+in order by the `bs_walk_state_machine` function in
+`src/lib/hardwaremain.c`. The sequence is defined by the `boot_state_t`
+enum in `src/include/bootstate.h`:
+
+1. **BS_PRE_DEVICE**: Initial state before any device operations begin
+2. **BS_DEV_INIT_CHIPS**: Early chip initialization for critical components
+3. **BS_DEV_ENUMERATE**: Device enumeration (discovering devices on buses)
+4. **BS_DEV_RESOURCES**: Resource allocation for devices
+5. **BS_DEV_ENABLE**: Enabling devices that were discovered
+6. **BS_DEV_INIT**: Device initialization
+7. **BS_POST_DEVICE**: All device operations have been completed
+8. **BS_OS_RESUME_CHECK**: Check if we're resuming from a sleep state
+9. **BS_OS_RESUME**: Handle OS resume process (if needed)
+10. **BS_WRITE_TABLES**: Write system tables (e.g., ACPI, SMBIOS)
+11. **BS_PAYLOAD_LOAD**: Load the payload into memory
+12. **BS_PAYLOAD_BOOT**: Boot the payload
+
+This sequence forms the backbone of the ramstage execution flow. Each
+state performs a specific task, runs associated callbacks, and
+transitions to the next state upon completion, unless blocked.
+
+
+## Bootstate Details
+
+### BS_PRE_DEVICE
+
+**Purpose**: Serves as the initial state before any device tree
+operations begin.
+
+**Key Functions**:
+- `bs_pre_device()`: Sets up initial environment and transitions to next
+  state.
+
+**Usage**: This state is used for initializing core components that need
+to be set up before any device operations. Examples include:
+- Setting up global NVRAM variables
+- Initializing debugging facilities
+- Preparing ACPI tables or other critical system structures
+
+
+### BS_DEV_INIT_CHIPS
+
+**Purpose**: Initializes critical chips early in the boot process.
+
+**Key Functions**:
+- `bs_dev_init_chips()`: Calls `dev_initialize_chips()` to initialize
+  all chips in the device tree.
+
+**Notes**: Chip initialization can disable unused devices, which is why
+it happens before device enumeration.
+
+
+### BS_DEV_ENUMERATE
+
+**Purpose**: Discovers devices in the system.
+
+**Key Functions**:
+- `bs_dev_enumerate()`: Calls `dev_enumerate()` to probe and identify
+  devices.
+
+**Notes**: During this phase, the system scans buses and detects
+connected devices.
+
+
+### BS_DEV_RESOURCES
+
+**Purpose**: Allocates and assigns resources (I/O, memory, IRQs) to
+devices.
+
+**Key Functions**:
+- `bs_dev_resources()`: Calls `dev_configure()` to compute and assign
+  bus resources.
+
+**Notes**: Resource allocation resolves conflicts and ensures each
+device has the resources it needs.
+
+
+### BS_DEV_ENABLE
+
+**Purpose**: Enables devices in the system.
+
+**Key Functions**:
+- `bs_dev_enable()`: Calls `dev_enable()` to enable devices on the bus.
+
+**Notes**: Some devices may be selectively disabled based on hardware
+configuration or policy.
+
+
+### BS_DEV_INIT
+
+**Purpose**: Initializes enabled devices.
+
+**Key Functions**:
+- `bs_dev_init()`: Calls `dev_initialize()` to initialize devices on the
+  bus.
+
+**Notes**: This state performs device-specific initialization routines
+for all enabled devices.
+
+
+### BS_POST_DEVICE
+
+**Purpose**: Final state after all device operations have completed.
+
+**Key Functions**:
+- `bs_post_device()`: Calls `dev_finalize()` to complete any final
+  device operations.
+
+**Notes**: This state serves as a checkpoint that all device
+initialization is complete.
+
+
+### BS_OS_RESUME_CHECK
+
+**Purpose**: Checks if the system should resume from a sleep state.
+
+**Key Functions**:
+- `bs_os_resume_check()`: Looks for a wake vector to determine if resume
+  is needed.
+
+**Notes**: This state branches the boot flow based on whether the system
+is resuming from a sleep state.
+
+### BS_OS_RESUME
+
+**Purpose**: Handles the OS resume process.
+
+**Key Functions**:
+- `bs_os_resume()`: Calls `acpi_resume()` with the wake vector to resume
+  the OS.
+
+**Notes**: After successful resume, control is transferred to the OS and
+does not return to coreboot.
+
+
+### BS_WRITE_TABLES
+
+**Purpose**: Writes configuration tables for the payload or OS.
+
+**Key Functions**:
+- `bs_write_tables()`: Calls `write_tables()` to generate system tables.
+
+**Notes**: Tables include ACPI, SMBIOS, and other system configuration
+data.
+
+
+### BS_PAYLOAD_LOAD
+
+**Purpose**: Loads the payload into memory.
+
+**Key Functions**:
+- `bs_payload_load()`: Calls `payload_load()` to load the payload.
+
+**Notes**: The payload could be a bootloader, an operating system kernel,
+or a firmware utility.
+
+
+### BS_PAYLOAD_BOOT
+
+**Purpose**: Final state that boots the loaded payload.
+
+**Key Functions**:
+- `bs_payload_boot()`: Calls `payload_run()` to execute the payload.
+
+**Notes**: After successful execution, control is transferred to the
+payload and does not return to coreboot. If execution returns (which
+indicates an error), a boot failure message is printed.
+
+
+## Driving the State Machine
+
+The state machine is driven by the `main()` function in
+`src/lib/hardwaremain.c`. After initial setup (like initializing the
+console and CBMEM), it calls `bs_walk_state_machine()`.
+
+`bs_walk_state_machine()` loops through the defined boot states:
+1. It identifies the current state.
+2. Runs all `BS_ON_ENTRY` callbacks for that state.
+3. Executes the state's specific function (e.g., `bs_dev_enumerate()`).
+4. Runs all `BS_ON_EXIT` callbacks for that state.
+5. Transitions to the next state returned by the state function.
+
+This loop continues until the final state (`BS_PAYLOAD_BOOT` or
+`BS_OS_RESUME`) transfers control away from coreboot.
+
+
+## External Functions (Public API)
+
+The bootstate machine provides several functions in
+`src/include/bootstate.h` for interacting with states:
+
+
+### Callback Registration
+
+```c
+int boot_state_sched_on_entry(struct boot_state_callback *bscb, boot_state_t state_id);
+```
+Schedules a callback to run when entering a state (`BS_ON_ENTRY`).
+
+```c
+int boot_state_sched_on_exit(struct boot_state_callback *bscb, boot_state_t state_id);
+```
+Schedules a callback to run when exiting a state (`BS_ON_EXIT`).
+
+
+### State Transition Control
+
+```c
+int boot_state_block(boot_state_t state, boot_state_sequence_t seq);
+```
+Blocks a state transition from occurring after the specified sequence
+(entry or exit callbacks). The transition will pause until the block is
+removed.
+
+```c
+int boot_state_unblock(boot_state_t state, boot_state_sequence_t seq);
+```
+Removes a previously set block on a state transition.
+
+
+### Static Callback Registration
+
+For registering callbacks at compile time, use the `BOOT_STATE_INIT_ENTRY`
+macro defined in `src/include/bootstate.h`:
+
+```c
+BOOT_STATE_INIT_ENTRY(state, when, func, arg)
+```
+
+This macro creates a static entry in a special section (`.bs_init`) of
+the binary. These entries are processed early in `main()` by
+`boot_state_schedule_static_entries()` to register the callbacks before
+the state machine starts running.
+
+
+## Configuration Options
+
+The bootstate machine behavior can be modified through Kconfig options:
+
+
+### DEBUG_BOOT_STATE
+
+```
+config DEBUG_BOOT_STATE
+    bool "Debug boot state machine"
+    default n
+    help
+        Control debugging of the boot state machine. When selected displays
+        the state boundaries in ramstage.
+```
+
+When enabled, this option causes the bootstate machine to output
+debugging information via `printk`, including:
+- State transition notifications (`Entering/Exiting <state> state.`)
+- Callback execution details (address, source location, execution time)
+- Timing information for state execution phases (entry, run, exit)
+
+
+## Examples
+
+### Adding a New Bootstate Callback
+
+To register a function to be called when entering a specific state using
+the static registration method:
+
+```c
+// Function to be called
+static void my_init_function(void *arg)
+{
+    // Initialization code
+    printk(BIOS_DEBUG, "My initialization running...\n");
+}
+
+// Register the callback at compile time
+BOOT_STATE_INIT_ENTRY(BS_DEV_INIT, BS_ON_ENTRY, my_init_function, NULL);
+```
+
+
+### Runtime Callback Registration
+
+For dynamic callback registration during runtime (e.g., within another
+callback or state function):
+
+```c
+static void runtime_init(void *arg)
+{
+    // Do something
+}
+
+void register_my_callbacks(void)
+{
+    // Allocate or define a static callback structure
+    static struct boot_state_callback bscb = {
+        .callback = runtime_init,
+        .arg = NULL,
+        // .location is automatically handled if DEBUG_BOOT_STATE=y
+    };
+
+    // Schedule it
+    boot_state_sched_on_entry(&bscb, BS_DEV_ENABLE);
+}
+```
+
+
+### Blocking State Transition
+
+To temporarily block a state from progressing until a condition is met,
+often used with timers:
+
+```c
+#include <timer.h> // Required for timer functions
+
+static void wait_for_device(void *arg)
+{
+    if (!device_is_ready()) {
+        // Block the transition *after* BS_DEV_INIT exits
+        boot_state_block(BS_DEV_INIT, BS_ON_EXIT);
+
+        // Schedule a function to check again later (e.g., after 100us)
+        // Assume schedule_timer exists and works appropriately
+        schedule_timer(check_device_ready, NULL, 100);
+    }
+}
+
+static void check_device_ready(void *arg)
+{
+    if (device_is_ready()) {
+        // Device is ready, unblock the transition
+        boot_state_unblock(BS_DEV_INIT, BS_ON_EXIT);
+    } else {
+        // Still not ready, check again later
+        schedule_timer(check_device_ready, NULL, 100);
+    }
+}
+
+// Register the initial check to run when entering BS_DEV_INIT
+BOOT_STATE_INIT_ENTRY(BS_DEV_INIT, BS_ON_ENTRY, wait_for_device, NULL);
+```
+
+
+## Best Practices
+
+### When Working with Bootstates
+
+1. **Choose the appropriate state**: Register callbacks at the earliest
+    state where all dependencies are guaranteed to be initialized, but no
+    earlier. Check the state descriptions and the functions called by
+    each state function (`bs_*`) in `hardwaremain.c`.
+
+2. **Keep callbacks focused**: Each callback should perform a specific,
+    related task and avoid complex operations that might significantly
+    delay the boot process.
+
+3. **Consider dependencies carefully**: Ensure any hardware, data
+    structures, or other resources your callback needs are available and
+    initialized at the chosen state and sequence (`BS_ON_ENTRY` vs.
+    `BS_ON_EXIT`).
+
+4. **Do not rely on callback order**: Remember that the execution order
+    of callbacks within the same state and sequence is not guaranteed.
+    Callbacks should be self-contained and not depend on side effects from
+    other callbacks that might run before or after them in the same phase.
+
+5. **Use blocking sparingly**: The blocking mechanism is powerful for
+    synchronization but can complicate the boot flow and make debugging
+    harder if overused. Always ensure a corresponding `boot_state_unblock`
+    call will eventually run.
+
+6. **Leverage compile-time registration**: Prefer using
+    `BOOT_STATE_INIT_ENTRY` for callbacks whenever possible. It makes the
+    registration explicit and easier to find. Runtime registration is
+    necessary only when the need for the callback is determined dynamically.
+
+7. **Debug with timestamps and `DEBUG_BOOT_STATE`**: Use the timestamp API
+    (`timestamp_add_now()`) and enable `DEBUG_BOOT_STATE` to measure
+    callback execution time, identify bottlenecks, and understand the
+    flow during development.
+
+8. **Document state-specific behavior**: When adding callbacks, add
+    comments explaining why they are placed in a particular state and
+    sequence.
+
+9. **Be careful with late states**: Avoid registering non-essential
+    callbacks in `BS_PAYLOAD_BOOT` or `BS_OS_RESUME`. Callbacks on
+    `BS_ON_EXIT` for these states are disallowed by compile-time asserts,
+    as coreboot is about to transfer control.
+
+
+## Related Documentation
+
+- [Boot Stages in coreboot](https://doc.coreboot.org/getting_started/architecture.html):
+  Overview of all coreboot boot stages.
+
+
+## References
+
+- `src/include/bootstate.h`: Public API definitions (callbacks, enums,
+  scheduling/blocking functions, static registration macro).
+- `src/lib/hardwaremain.c`: Internal implementation (state machine driver,
+  state definitions, state functions).
+- `src/ec/google/wilco/chip.c`: Example of bootstate callback usage.
+- `src/mainboard/prodrive/hermes/mainboard.c`: Examples of mainboard-specific
+  bootstate callbacks.

From 20c281389184dc01906683259d230e9d8d5be9af Mon Sep 17 00:00:00 2001
From: Swathi Tamilselvan <tswathi@qualcomm.corp-partner.google.com>
Date: Wed, 25 Jun 2025 15:39:39 +0530
Subject: [PATCH 1475/3886] soc/qualcomm/common: Update QUP register structure
 for QUP v3.2

The register layout for QUP has been updated in QUP v3.2. Update the
structure definition accordingly. Allow SoCs to use the existing version
or the updated version based on QC_COMMON_QUPV3_2.

Change-Id: I304012d72a1af33510dcd620953367f0a9e98ac1
Signed-off-by: Swathi Tamilselvan <tswathi@qualcomm.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88190
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/soc/qualcomm/common/Kconfig                    |  6 ++++++
 src/soc/qualcomm/common/clock.c                    | 11 +++++++++--
 src/soc/qualcomm/common/include/soc/clock_common.h |  3 +++
 3 files changed, 18 insertions(+), 2 deletions(-)

diff --git a/src/soc/qualcomm/common/Kconfig b/src/soc/qualcomm/common/Kconfig
index e0efc9a987..8a3adf58d7 100644
--- a/src/soc/qualcomm/common/Kconfig
+++ b/src/soc/qualcomm/common/Kconfig
@@ -6,6 +6,12 @@ config SOC_QUALCOMM_COMMON
 	help
 	  Selected by platforms that use the common code.
 
+config QC_COMMON_QUPV3_2
+	bool
+	default n
+	help
+	  Selected by chipsets that has QUPv3 HW Version 2.
+
 if SOC_QUALCOMM_COMMON
 
 config QC_SDI_ENABLE
diff --git a/src/soc/qualcomm/common/clock.c b/src/soc/qualcomm/common/clock.c
index 09484b76f4..cd700a3224 100644
--- a/src/soc/qualcomm/common/clock.c
+++ b/src/soc/qualcomm/common/clock.c
@@ -128,8 +128,15 @@ void clock_configure_dfsr_table(int qup, struct clock_freq_config *clk_cfg,
 	unsigned int idx, s = qup % QUP_WRAP1_S0;
 	uint32_t reg_val;
 
-	qup_clk = qup < QUP_WRAP1_S0 ?
-				&gcc->qup_wrap0_s[s] : &gcc->qup_wrap1_s[s];
+#if QUP_WRAP2_BASE
+	if (qup >= QUP_WRAP2_S0)
+		qup_clk = &gcc->qup_wrap2_s[s];
+	else
+#endif
+	if (qup >= QUP_WRAP1_S0)
+		qup_clk = &gcc->qup_wrap1_s[s];
+	else
+		qup_clk = &gcc->qup_wrap0_s[s];
 
 	clrsetbits32(&qup_clk->dfsr_clk.cmd_dfsr,
 			BIT(CLK_CTL_CMD_RCG_SW_CTL_SHFT),
diff --git a/src/soc/qualcomm/common/include/soc/clock_common.h b/src/soc/qualcomm/common/include/soc/clock_common.h
index b08d39bdd8..2c127429e1 100644
--- a/src/soc/qualcomm/common/include/soc/clock_common.h
+++ b/src/soc/qualcomm/common/include/soc/clock_common.h
@@ -45,6 +45,9 @@ struct clock_freq_config {
 
 struct qupv3_clock {
 	u32 cbcr;
+#if CONFIG(QC_COMMON_QUPV3_2)
+	u8 _res0[0x08];
+#endif
 	struct clock_rcg_mnd clk;
 	struct clock_rcg_dfsr dfsr_clk;
 };

From 8d8d0f9746a9e309074945aea2cc51609c275471 Mon Sep 17 00:00:00 2001
From: Swathi Tamilselvan <tswathi@qualcomm.corp-partner.google.com>
Date: Fri, 27 Jun 2025 16:34:11 +0530
Subject: [PATCH 1476/3886] soc/qualcomm/x1p42100: Add Clock support for
 x1p42100

Add support to enable QUPV3, QSPI and GPLL0 clocks. Modify
XO Source clock frequency value to 19.2KHz. The register
details are part of HRD-X1P42100-S1 document.
https://docs.qualcomm.com/bundle/resource/topics/HRD-X1P42100-S1/

TEST=Create an image.serial.bin and ensure it boots on X1P42100

Change-Id: I6252bc1fda3c53a683c65d2ab4a3b9f27ea64618
Signed-off-by: Swathi Tamilselvan <tswathi@qualcomm.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88175
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
---
 src/soc/qualcomm/x1p42100/Kconfig             |   1 +
 src/soc/qualcomm/x1p42100/Makefile.mk         |   1 +
 src/soc/qualcomm/x1p42100/clock.c             | 170 +++++++++++++++++-
 .../x1p42100/include/soc/addressmap.h         |   1 +
 src/soc/qualcomm/x1p42100/include/soc/clock.h | 137 +++++++++++++-
 5 files changed, 305 insertions(+), 5 deletions(-)

diff --git a/src/soc/qualcomm/x1p42100/Kconfig b/src/soc/qualcomm/x1p42100/Kconfig
index cb32c2f8b3..8ae8beadde 100644
--- a/src/soc/qualcomm/x1p42100/Kconfig
+++ b/src/soc/qualcomm/x1p42100/Kconfig
@@ -22,6 +22,7 @@ config SOC_QUALCOMM_X1P42100
 	select MAINBOARD_FORCE_NATIVE_VGA_INIT
 	select MAINBOARD_HAS_NATIVE_VGA_INIT
 	select PCI
+	select QC_COMMON_QUPV3_2
 	select NO_ECAM_MMCONF_SUPPORT
 	select SDHCI_CONTROLLER
 	select SOC_QUALCOMM_COMMON
diff --git a/src/soc/qualcomm/x1p42100/Makefile.mk b/src/soc/qualcomm/x1p42100/Makefile.mk
index 3140ea2445..da3c25b005 100644
--- a/src/soc/qualcomm/x1p42100/Makefile.mk
+++ b/src/soc/qualcomm/x1p42100/Makefile.mk
@@ -6,6 +6,7 @@ decompressor-y += mmu.c
 decompressor-y += ../common/timer.c
 all-y += ../common/timer.c
 all-y += ../common/gpio.c
+all-y += ../common/clock.c
 all-y += clock.c
 all-y += ../common/spi.c
 all-y += ../common/qspi.c
diff --git a/src/soc/qualcomm/x1p42100/clock.c b/src/soc/qualcomm/x1p42100/clock.c
index 5e9706f698..283428642e 100644
--- a/src/soc/qualcomm/x1p42100/clock.c
+++ b/src/soc/qualcomm/x1p42100/clock.c
@@ -1,23 +1,185 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
+#include <assert.h>
+#include <commonlib/helpers.h>
+#include <device/mmio.h>
 #include <soc/clock.h>
+#include <types.h>
+
+static struct clock_freq_config qspi_core_cfg[] = {
+	{
+		.hz = SRC_XO_HZ,	/* 19.2MHz */
+		.src = SRC_XO_19_2MHZ,
+		.div = QCOM_CLOCK_DIV(1),
+	},
+	{
+		.hz = 100 * MHz,
+		.src = SRC_GPLL0_MAIN_600MHZ,
+		.div = QCOM_CLOCK_DIV(6),
+	},
+	{
+		.hz = 150 * MHz,
+		.src = SRC_GPLL0_MAIN_600MHZ,
+		.div = QCOM_CLOCK_DIV(4),
+	},
+	{
+		.hz = 200 * MHz,
+		.src = SRC_GPLL0_MAIN_600MHZ,
+		.div = QCOM_CLOCK_DIV(3),
+	},
+	{
+		.hz = 400 * MHz,
+		.src = SRC_GPLL0_MAIN_600MHZ,
+		.div = QCOM_CLOCK_DIV(1.5),
+	},
+};
+
+static struct clock_freq_config qupv3_wrap_cfg[] = {
+	{
+		.hz = SRC_XO_HZ,	/* 19.2MHz */
+		.src = SRC_XO_19_2MHZ,
+		.div = QCOM_CLOCK_DIV(1),
+	},
+	{
+		.hz =  32 * MHz,
+		.src = SRC_GPLL0_EVEN_300MHZ,
+		.div = QCOM_CLOCK_DIV(1),
+		.m = 8,
+		.n = 75,
+		.d_2 = 75,
+	},
+	{
+		.hz =  48 * MHz,
+		.src = SRC_GPLL0_EVEN_300MHZ,
+		.div = QCOM_CLOCK_DIV(1),
+		.m = 4,
+		.n = 25,
+		.d_2 = 25,
+	},
+	{
+		.hz =  64 * MHz,
+		.src = SRC_GPLL0_EVEN_300MHZ,
+		.div = QCOM_CLOCK_DIV(1),
+		.m = 16,
+		.n = 75,
+		.d_2 = 75,
+	},
+	{
+		.hz =  96 * MHz,
+		.src = SRC_GPLL0_EVEN_300MHZ,
+		.div = QCOM_CLOCK_DIV(1),
+		.m = 8,
+		.n = 25,
+		.d_2 = 25,
+	},
+	{
+		.hz =  100 * MHz,
+		.src = SRC_GPLL0_MAIN_600MHZ,
+		.div = QCOM_CLOCK_DIV(6),
+	},
+};
 
 void clock_configure_qspi(uint32_t hz)
 {
-	/* placeholder */
+	clock_configure(&gcc->qspi_core, qspi_core_cfg, hz, ARRAY_SIZE(qspi_core_cfg));
+	clock_enable(&gcc->qspi_cnoc_ahb_cbcr);
+	clock_enable(&gcc->qspi_core_cbcr);
 }
 
 void clock_enable_qup(int qup)
 {
-	/* placeholder */
+	struct qupv3_clock *qup_clk;
+	int s = qup % QUP_WRAP1_S0, clk_en_off;
+	void *clk_br_en_ptr = NULL;	// Pointer to the correct apcs_clk_br_enX
+	qup_clk = qup < QUP_WRAP1_S0 ? &gcc->qup_wrap0_s[s] : qup < QUP_WRAP2_S0 ?
+		&gcc->qup_wrap1_s[s] : &gcc->qup_wrap2_s[s];
+
+	if (qup <= QUP_WRAP0_S7) {
+		clk_en_off = QUPV3_WRAP0_CLK_ENA_S(s);
+		clk_br_en_ptr = &gcc->apcs_clk_br_en4;
+	} else if (qup >= QUP_WRAP1_S0 && qup <= QUP_WRAP1_S6) {
+		clk_en_off = QUPV3_WRAP1_CLK_ENA_S(s);
+		clk_br_en_ptr = &gcc->apcs_clk_br_en1;
+	} else if (qup >= QUP_WRAP2_S0 && qup <= QUP_WRAP2_S6) {
+		clk_en_off = QUPV3_WRAP2_CLK_ENA_S(s);
+		clk_br_en_ptr = &gcc->apcs_clk_br_en2;
+	} else if (qup == QUP_WRAP1_S7 || qup == QUP_WRAP2_S7) {
+		clk_en_off = qup == QUP_WRAP1_S7 ? QUPV3_WRAP1_SE7_CLK_ENA : QUPV3_WRAP2_SE7_CLK_ENA;
+		clk_br_en_ptr = &gcc->apcs_clk_br_en2;
+	}
+
+	/* Only call if a valid pointer was assigned */
+	if (clk_br_en_ptr)
+		clock_enable_vote(&qup_clk->cbcr, clk_br_en_ptr, clk_en_off);
 }
 
 void clock_configure_dfsr(int qup)
 {
-	/* placeholder */
+	clock_configure_dfsr_table(qup, qupv3_wrap_cfg,
+						ARRAY_SIZE(qupv3_wrap_cfg));
+}
+static enum cb_err clock_configure_gpll0(void)
+{
+	struct alpha_pll_reg_val_config gpll0_cfg = {0};
+
+	gpll0_cfg.reg_user_ctl = &gcc->gpll0.user_ctl;
+
+	gpll0_cfg.user_ctl_val = (read32(gpll0_cfg.reg_user_ctl) |
+				1 << PLL_POST_DIV_EVEN_SHFT_X1P42100 |
+				2 << PLL_POST_DIV_ODD_SHFT_X1P42100 |
+				1 << PLL_PLLOUT_EVEN_SHFT_X1P42100 |
+				1 << PLL_PLLOUT_MAIN_SHFT_X1P42100 |
+				1 << PLL_PLLOUT_ODD_SHFT_X1P42100);
+
+	return clock_configure_enable_gpll(&gpll0_cfg, false, 0);
+}
+
+static void speed_up_boot_cpu(void)
+{
+	/* Placeholder */
 }
 
 void clock_init(void)
 {
-	/* placeholder */
+	clock_configure_gpll0();
+	clock_enable_vote(&gcc->qup_wrap0_core_2x_cbcr,
+				&gcc->apcs_clk_br_en4,
+				QUPV3_WRAP0_CORE_2X_CLK_ENA);
+	clock_enable_vote(&gcc->qup_wrap0_core_cbcr,
+				&gcc->apcs_clk_br_en4,
+				QUPV3_WRAP0_CORE_CLK_ENA);
+	clock_enable_vote(&gcc->qup_wrap0_m_ahb_cbcr,
+				&gcc->apcs_clk_br_en4,
+				QUPV3_WRAP_0_M_AHB_CLK_ENA);
+	clock_enable_vote(&gcc->qup_wrap0_s_ahb_cbcr,
+				&gcc->apcs_clk_br_en4,
+				QUPV3_WRAP_0_S_AHB_CLK_ENA);
+
+	clock_enable_vote(&gcc->qup_wrap1_core_2x_cbcr,
+				&gcc->apcs_clk_br_en1,
+				QUPV3_WRAP1_CORE_2X_CLK_ENA);
+	clock_enable_vote(&gcc->qup_wrap1_core_cbcr,
+				&gcc->apcs_clk_br_en1,
+				QUPV3_WRAP1_CORE_CLK_ENA);
+	clock_enable_vote(&gcc->qup_wrap1_m_ahb_cbcr,
+				&gcc->apcs_clk_br_en1,
+				QUPV3_WRAP_1_M_AHB_CLK_ENA);
+	clock_enable_vote(&gcc->qup_wrap1_s_ahb_cbcr,
+				&gcc->apcs_clk_br_en1,
+				QUPV3_WRAP_1_S_AHB_CLK_ENA);
+
+	clock_enable_vote(&gcc->qup_wrap2_core_2x_cbcr,
+				&gcc->apcs_clk_br_en2,
+				QUPV3_WRAP2_CORE_2X_CLK_ENA);
+	clock_enable_vote(&gcc->qup_wrap2_core_cbcr,
+				&gcc->apcs_clk_br_en2,
+				QUPV3_WRAP2_CORE_CLK_ENA);
+	clock_enable_vote(&gcc->qup_wrap2_m_ahb_cbcr,
+				&gcc->apcs_clk_br_en2,
+				QUPV3_WRAP_2_M_AHB_CLK_ENA);
+	clock_enable_vote(&gcc->qup_wrap2_s_ahb_cbcr,
+				&gcc->apcs_clk_br_en2,
+				QUPV3_WRAP_2_S_AHB_CLK_ENA);
+	speed_up_boot_cpu();
+
 }
diff --git a/src/soc/qualcomm/x1p42100/include/soc/addressmap.h b/src/soc/qualcomm/x1p42100/include/soc/addressmap.h
index a119d17295..818b3463b4 100644
--- a/src/soc/qualcomm/x1p42100/include/soc/addressmap.h
+++ b/src/soc/qualcomm/x1p42100/include/soc/addressmap.h
@@ -8,6 +8,7 @@
 #define AOSS_CC_BASE			0x0C2A0000
 #define QSPI_BASE			0x088DC000
 #define TLMM_TILE_BASE			0x0F100000
+#define GCC_BASE			0x00100000
 
 /* X1P42100 QSPI GPIO PINS */
 #define QSPI_CS				GPIO(132)
diff --git a/src/soc/qualcomm/x1p42100/include/soc/clock.h b/src/soc/qualcomm/x1p42100/include/soc/clock.h
index bb327709af..f9848c697a 100644
--- a/src/soc/qualcomm/x1p42100/include/soc/clock.h
+++ b/src/soc/qualcomm/x1p42100/include/soc/clock.h
@@ -7,7 +7,141 @@
 #ifndef __SOC_QUALCOMM_X1P42100_CLOCK_H__
 #define __SOC_QUALCOMM_X1P42100_CLOCK_H__
 
-#define SRC_XO_HZ		(38400 * KHz)
+#define SRC_XO_HZ		(19200 * KHz)
+
+#define GPLL0_EVEN_HZ		(300 * MHz)
+#define GPLL0_MAIN_HZ		(600 * MHz)
+#define CLK_100MHZ		(100 * MHz)
+
+#define QUPV3_WRAP0_CLK_ENA_S(idx)		(10 + idx)
+#define QUPV3_WRAP1_CLK_ENA_S(idx)		(22 + idx)
+#define QUPV3_WRAP2_CLK_ENA_S(idx)		(4 + idx)
+
+#define QUPV3_WRAP1_SE7_CLK_ENA			16
+#define QUPV3_WRAP2_SE7_CLK_ENA			17
+
+enum clk_ctl_gpll_user_ctl_x1p42100 {
+	PLL_PLLOUT_MAIN_SHFT_X1P42100 = 0,
+	PLL_PLLOUT_EVEN_SHFT_X1P42100 = 1,
+	PLL_PLLOUT_ODD_SHFT_X1P42100 = 2,
+	PLL_POST_DIV_EVEN_SHFT_X1P42100 = 10,
+	PLL_POST_DIV_ODD_SHFT_X1P42100 = 14,
+};
+
+enum clk_pll_src {
+	SRC_XO_19_2MHZ = 0,
+	SRC_GPLL0_MAIN_600MHZ = 1,
+	SRC_GPLL9_MAIN_808MHZ = 2,
+	SRC_GCC_DISP_GPLL0_CLK = 4,
+	SRC_GPLL10_MAIN_384MHZ = 5,
+	SRC_GPLL0_EVEN_300MHZ = 6,
+};
+
+enum apcs_branch_en_vote {
+	QUPV3_WRAP_0_M_AHB_CLK_ENA = 6,
+	QUPV3_WRAP_0_S_AHB_CLK_ENA = 7,
+	QUPV3_WRAP0_CORE_CLK_ENA = 8,
+	QUPV3_WRAP0_CORE_2X_CLK_ENA = 9,
+	QUPV3_WRAP1_CORE_2X_CLK_ENA = 18,
+	QUPV3_WRAP1_CORE_CLK_ENA = 19,
+	QUPV3_WRAP_1_M_AHB_CLK_ENA = 20,
+	QUPV3_WRAP_1_S_AHB_CLK_ENA = 21,
+	QUPV3_WRAP2_CORE_2X_CLK_ENA = 3,
+	QUPV3_WRAP2_CORE_CLK_ENA = 0,
+	QUPV3_WRAP_2_M_AHB_CLK_ENA = 2,
+	QUPV3_WRAP_2_S_AHB_CLK_ENA = 1,
+};
+
+struct x1p42100_gpll {
+	u32 mode;
+	u32 opmode;
+	u32 state;
+	u32 status;
+	u32 l;
+	u32 alpha;
+	u32 user_ctl;
+	u32 user_ctl_u;
+	u32 config_ctl;
+	u32 config_ctl_u;
+	u32 config_ctl_u1;
+};
+
+struct x1p42100_gcc {
+	struct x1p42100_gpll gpll0;
+	u8 _res1[0x18004 - 0x0002c];
+	struct qupv3_clock qup_wrap1_s[8];
+	u8 _res2[0x1e004 - 0x189c4];
+	struct qupv3_clock qup_wrap2_s[8];
+	u8 _res3[0x23000 - 0x1e9c4];
+	u32 qup_wrap0_m_ahb_cbcr;
+	u32 qup_wrap0_s_ahb_cbcr;
+	u32 qup_wrap0_core_cbcr;
+	u8 _res4[0x23014 - 0x2300c];
+	u32 qup_wrap0_core_cdivr;
+	u32 qup_wrap0_core_2x_cbcr;
+	u8 _res5[0x23024 - 0x2301c];
+	struct clock_rcg qup_wrap0_core_2x;
+	u8 _res6[0x23150 - 0x2302c];
+	u32 qup_wrap1_m_ahb_cbcr;
+	u32 qup_wrap1_s_ahb_cbcr;
+	u32 qup_wrap1_core_cbcr;
+	u8 _res7[0x23164 - 0x2315c];
+	u32 qup_wrap1_core_cdivr;
+	u32 qup_wrap1_core_2x_cbcr;
+	u8 _res8[0x23174 - 0x2316c];
+	struct clock_rcg qup_wrap1_core_2x;
+	u8 _res9[0x232a0 - 0x2317c];
+	u32 qup_wrap2_m_ahb_cbcr;
+	u32 qup_wrap2_s_ahb_cbcr;
+	u32 qup_wrap2_core_cbcr;
+	u8 _res10[0x232b4 - 0x232ac];
+	u32 qup_wrap2_core_cdivr;
+	u32 qup_wrap2_core_2x_cbcr;
+	u8 _res11[0x232c4 - 0x232bc];
+	struct clock_rcg qup_wrap2_core_2x;
+	u8 _res12[0x42004 - 0x232cc];
+	struct qupv3_clock qup_wrap0_s[8];
+	u8 _res13[0x4b000 - 0x429c4];
+	u32 qspi_bcr;
+	u32 qspi_cnoc_ahb_cbcr;
+	u32 qspi_core_cbcr;
+	struct clock_rcg qspi_core;
+	u8 _res14[0x52000 - 0x4b014];
+	u32 apcs_clk_br_en;
+	u8 _res15[0x52008 - 0x52004];
+	u32 apcs_clk_br_en1;
+	u8 _res16[0x52010 - 0x5200C];
+	u32 apcs_clk_br_en2;
+	u8 _res17[0x52018 - 0x52014];
+	u32 apcs_clk_br_en3;
+	u8 _res18[0x52020 - 0x5201c];
+	u32 apcs_clk_br_en4;
+	u8 _res19[0x52028 - 0x52024];
+	u32 apcs_clk_br_en5;
+	u8 _res20[0x52030 - 0x5202c];
+	u32 apcs_pll_br_en;
+};
+
+check_member(x1p42100_gcc, qup_wrap1_s, 0x18004);
+check_member(x1p42100_gcc, qup_wrap2_s, 0x1e004);
+check_member(x1p42100_gcc, qup_wrap0_m_ahb_cbcr, 0x23000);
+check_member(x1p42100_gcc, qup_wrap0_core_cdivr, 0x23014);
+check_member(x1p42100_gcc, qup_wrap0_core_2x, 0x23024);
+check_member(x1p42100_gcc, qup_wrap1_m_ahb_cbcr, 0x23150);
+check_member(x1p42100_gcc, qup_wrap1_core_cdivr, 0x23164);
+check_member(x1p42100_gcc, qup_wrap1_core_2x, 0x23174);
+check_member(x1p42100_gcc, qup_wrap2_m_ahb_cbcr, 0x232a0);
+check_member(x1p42100_gcc, qup_wrap2_core_cdivr, 0x232b4);
+check_member(x1p42100_gcc, qup_wrap2_core_2x, 0x232c4);
+check_member(x1p42100_gcc, qup_wrap0_s, 0x42004);
+check_member(x1p42100_gcc, qspi_bcr, 0x4b000);
+check_member(x1p42100_gcc, apcs_clk_br_en, 0x52000);
+check_member(x1p42100_gcc, apcs_clk_br_en1, 0x52008);
+check_member(x1p42100_gcc, apcs_clk_br_en2, 0x52010);
+check_member(x1p42100_gcc, apcs_clk_br_en3, 0x52018);
+check_member(x1p42100_gcc, apcs_clk_br_en4, 0x52020);
+check_member(x1p42100_gcc, apcs_clk_br_en5, 0x52028);
+check_member(x1p42100_gcc, apcs_pll_br_en, 0x52030);
 
 enum clk_qup {
 	QUP_WRAP0_S0,
@@ -44,5 +178,6 @@ void clock_configure_dfsr(int qup);
 
 /* Subsystem Reset */
 static struct aoss *const aoss = (void *)AOSS_CC_BASE;
+static struct x1p42100_gcc *const gcc = (void *)GCC_BASE;
 
 #endif	// __SOC_QUALCOMM_X1P42100_CLOCK_H__

From 78a89d4d70c8b5f41f3cb8f284ed3268aa2a37e9 Mon Sep 17 00:00:00 2001
From: Vince Liu <vince-wl.liu@mediatek.corp-partner.google.com>
Date: Fri, 6 Jun 2025 16:42:46 +0800
Subject: [PATCH 1477/3886] soc/mediatek/mt8189: Extract code to disable secure
 mode from DDP driver

Extract code for disabling secure mode from mtk_ddp_init and implement
it as mtk_display_disable_secure_mode(). This allows disabling display
secure mode without using DDP, for example, when FW display is not
needed.

Unlike previous SoCs, MT8189 is designed so that access to display
registers defaults to secure mode, due to specific product requirements.
However, Chromebook products do not use this setting and instead require
the register permissions to be set for normal mode access, consistent
with previous SoC behavior.

Also reordered function declarations to group similar types (e.g.,
display, DDP) together for better readability.

BUG=b:422507985
BRANCH=none
TEST=utility gbb --set --flash --flags=0x0, and check the DUT screen.

Signed-off-by: Xiandong Wang <xiandong.wang@mediatek.corp-partner.google.com>
Signed-off-by: Vince Liu <vince-wl.liu@mediatek.corp-partner.google.com>
Change-Id: Ic378ef62540c408ccd59e482abfe9f9c8ca5a13d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88272
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
---
 src/soc/mediatek/common/include/soc/display.h |  3 +-
 src/soc/mediatek/mt8189/ddp.c                 | 36 +++++++++++--------
 2 files changed, 24 insertions(+), 15 deletions(-)

diff --git a/src/soc/mediatek/common/include/soc/display.h b/src/soc/mediatek/common/include/soc/display.h
index 2881505860..0d06a3cd2c 100644
--- a/src/soc/mediatek/common/include/soc/display.h
+++ b/src/soc/mediatek/common/include/soc/display.h
@@ -26,8 +26,9 @@ struct panel_description {
 	uint32_t quirks;
 };
 
-int mtk_display_init(void);
 struct panel_description *get_active_panel(void);
+void mtk_display_disable_secure_mode(void);
+int mtk_display_init(void);
 
 void mtk_ddp_init(void);
 void mtk_ddp_mode_set(const struct edid *edid, enum disp_path_sel path);
diff --git a/src/soc/mediatek/mt8189/ddp.c b/src/soc/mediatek/mt8189/ddp.c
index 32c3b5b12f..f7bdc7f835 100644
--- a/src/soc/mediatek/mt8189/ddp.c
+++ b/src/soc/mediatek/mt8189/ddp.c
@@ -86,26 +86,18 @@ static void disp_clock_on(void)
 	       __func__, read32(&mmsys_cfg->mmsys_cg_con0), read32(&mmsys_cfg->mmsys_cg_con1));
 }
 
-void mtk_ddp_init(void)
+void mtk_display_disable_secure_mode(void)
 {
-	int i;
-
 	disp_clock_on();
 
-	printk(BIOS_DEBUG, "%s: shadow: %#x %#x, secure before: [%#x %#x %#x] larb: %x\n",
+	printk(BIOS_DEBUG, "%s: shadow: %#x %#x, secure before: [%#x %#x %#x]\n",
 	       __func__,
 	       read32(&mmsys_cfg->disp_bypass_mux_shadow),
 	       read32(&mmsys_cfg->disp_crossbar_con),
 	       read32(&mmsys_cfg->mmsys_security_disable),
 	       read32(&mmsys_cfg->mmsys_security_disable1),
-	       read32(&mmsys_cfg->mmsys_security_disable2),
-	       read32(&smi_larb0->port_l0_ovl_rdma[0]));
+	       read32(&mmsys_cfg->mmsys_security_disable2));
 
-	/* Turn off M4U port */
-	for (i = 0; i < RDMA_PORT_NR; i++) {
-		write32(&smi_larb0->port_l0_ovl_rdma[i], 0);
-		write32(&smi_larb1->port_l0_ovl_rdma[i], 0);
-	}
 	/* disable shadow */
 	write32(&mmsys_cfg->disp_bypass_mux_shadow, 0x1);
 	write32(&mmsys_cfg->disp_crossbar_con, 0x00FF0000);
@@ -113,14 +105,30 @@ void mtk_ddp_init(void)
 	write32(&mmsys_cfg->mmsys_security_disable, 0xFFFFFFFF);
 	write32(&mmsys_cfg->mmsys_security_disable1, 0xFFFFFFFF);
 	write32(&mmsys_cfg->mmsys_security_disable2, 0xFFFFFFFF);
-	printk(BIOS_DEBUG, "%s: shadow: %#x %#x, secure: [%#x %#x %#x] larb: %#x\n",
+
+	printk(BIOS_DEBUG, "%s: shadow: %#x %#x, secure: [%#x %#x %#x]n",
 	       __func__,
 	       read32(&mmsys_cfg->disp_bypass_mux_shadow),
 	       read32(&mmsys_cfg->disp_crossbar_con),
 	       read32(&mmsys_cfg->mmsys_security_disable),
 	       read32(&mmsys_cfg->mmsys_security_disable1),
-	       read32(&mmsys_cfg->mmsys_security_disable2),
-	       read32(&smi_larb0->port_l0_ovl_rdma[0]));
+	       read32(&mmsys_cfg->mmsys_security_disable2));
+}
+
+void mtk_ddp_init(void)
+{
+	int i;
+
+	mtk_display_disable_secure_mode();
+
+	/* Turn off M4U port */
+	for (i = 0; i < RDMA_PORT_NR; i++) {
+		write32(&smi_larb0->port_l0_ovl_rdma[i], 0);
+		write32(&smi_larb1->port_l0_ovl_rdma[i], 0);
+	}
+
+	printk(BIOS_DEBUG, "%s: larb: %#x\n",
+	       __func__, read32(&smi_larb0->port_l0_ovl_rdma[0]));
 }
 
 void mtk_ddp_mode_set(const struct edid *edid, enum disp_path_sel path)

From 8cec500968ba4fe45bfef0c0f685e9733c166d10 Mon Sep 17 00:00:00 2001
From: Vince Liu <vince-wl.liu@mediatek.corp-partner.google.com>
Date: Wed, 2 Jul 2025 15:47:49 +0800
Subject: [PATCH 1478/3886] mb/google/skywalker: Configure firmware display for
 eDP panel

Add eDP panel power-on sequences and initialize the display in the
ramstage. Also Set display registers to normal mode if initialization
flow is skipped to prevent abnormal behavior.

BUG=b:400886838,b:422507985
BRANCH=none
TEST=utility gbb --set --flash --flags=0x39, and check the firmware
screen.
utility gbb --set --flash --flags=0x0, and check the DUT screen.

Signed-off-by: Bincai Liu <bincai.liu@mediatek.corp-partner.google.com>
Signed-off-by: Vince Liu <vince-wl.liu@mediatek.corp-partner.google.com>
Signed-off-by: Xiandong Wang <xiandong.wang@mediatek.corp-partner.google.com>
Change-Id: I09edceefee9c17ce18681b85da8ca75f65ed2876
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88273
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/google/skywalker/Kconfig     |  2 ++
 src/mainboard/google/skywalker/mainboard.c | 14 ++++++++++++++
 2 files changed, 16 insertions(+)

diff --git a/src/mainboard/google/skywalker/Kconfig b/src/mainboard/google/skywalker/Kconfig
index a868258643..9f8ca1bffa 100644
--- a/src/mainboard/google/skywalker/Kconfig
+++ b/src/mainboard/google/skywalker/Kconfig
@@ -26,6 +26,8 @@ config BOARD_SPECIFIC_OPTIONS
 	select COMMON_CBFS_SPI_WRAPPER
 	select SPI_FLASH
 	select SPI_FLASH_INCLUDE_ALL_DRIVERS
+	select MAINBOARD_HAS_NATIVE_VGA_INIT
+	select HAVE_LINEAR_FRAMEBUFFER
 	select EC_GOOGLE_CHROMEEC
 	select EC_GOOGLE_CHROMEEC_BOARDID
 	select EC_GOOGLE_CHROMEEC_SPI
diff --git a/src/mainboard/google/skywalker/mainboard.c b/src/mainboard/google/skywalker/mainboard.c
index 3327c038d1..fb5316201a 100644
--- a/src/mainboard/google/skywalker/mainboard.c
+++ b/src/mainboard/google/skywalker/mainboard.c
@@ -1,10 +1,12 @@
 /* SPDX-License-Identifier: GPL-2.0-only OR MIT */
 
+#include <bootmode.h>
 #include <device/device.h>
 #include <device/mmio.h>
 #include <fw_config.h>
 #include <gpio.h>
 #include <soc/bl31.h>
+#include <soc/display.h>
 #include <soc/dpm_v2.h>
 #include <soc/i2c.h>
 #include <soc/msdc.h>
@@ -101,6 +103,18 @@ static void mainboard_init(struct device *dev)
 
 	if (CONFIG(ARM64_USE_ARM_TRUSTED_FIRMWARE))
 		register_reset_to_bl31(GPIO_AP_EC_WARM_RST_REQ.id, true);
+
+	if (display_init_required()) {
+		if (mtk_display_init() < 0)
+			printk(BIOS_ERR, "%s: Failed to init display\n", __func__);
+	} else {
+		printk(BIOS_INFO, "%s: Skipping display init; disabling secure mode\n",
+		       __func__);
+		mtcmos_display_power_on();
+		mtcmos_protect_display_bus();
+		mtk_display_disable_secure_mode();
+	}
+
 }
 
 static void mainboard_enable(struct device *dev)

From da49da6c82e57514d60af50bd5b90fc4250b5e7a Mon Sep 17 00:00:00 2001
From: Jeremy Soller <jackpot51@gmail.com>
Date: Mon, 24 Mar 2025 13:23:56 -0600
Subject: [PATCH 1479/3886] soc/intel: Add Arrow Lake-S/HX IDs

Change-Id: I7a0a56cf80f053b4bb0c8acb9038c1e46dca5d2e
Ref: Intel Arrow Lake-S/HX EDS, Volume 1 (#729037, rev 2.01)
Ref: Intel 800 Series Chipset Family PCH EDS, Volume 1 (#728144, rev 1.52)
Signed-off-by: Jeremy Soller <jeremy@system76.com>
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87454
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/drivers/intel/ish/ish.c                   |   1 +
 src/include/device/pci_ids.h                  | 142 ++++++++++++++++++
 src/soc/intel/common/block/cnvi/cnvi.c        |   1 +
 src/soc/intel/common/block/cse/cse.c          |   7 +
 src/soc/intel/common/block/dsp/dsp.c          |   1 +
 src/soc/intel/common/block/dtt/dtt.c          |   1 +
 .../intel/common/block/fast_spi/fast_spi.c    |   2 +
 src/soc/intel/common/block/hda/hda.c          |   1 +
 src/soc/intel/common/block/i2c/i2c.c          |   6 +
 src/soc/intel/common/block/lpc/lpc.c          |  64 ++++++++
 src/soc/intel/common/block/p2sb/p2sb.c        |   2 +
 src/soc/intel/common/block/pcie/pcie.c        |  27 ++++
 src/soc/intel/common/block/pmc/pmc.c          |   2 +
 src/soc/intel/common/block/sata/sata.c        |   2 +
 src/soc/intel/common/block/smbus/smbus.c      |   2 +
 src/soc/intel/common/block/spi/spi.c          |   4 +
 src/soc/intel/common/block/sram/sram.c        |   3 +
 .../intel/common/block/tracehub/tracehub.c    |   2 +
 src/soc/intel/common/block/uart/uart.c        |   4 +
 src/soc/intel/common/block/xdci/xdci.c        |   1 +
 src/soc/intel/common/block/xhci/xhci.c        |   1 +
 src/soc/intel/meteorlake/Makefile.mk          |   1 +
 22 files changed, 277 insertions(+)

diff --git a/src/drivers/intel/ish/ish.c b/src/drivers/intel/ish/ish.c
index 8f2a187c4f..9cf6b7c0e5 100644
--- a/src/drivers/intel/ish/ish.c
+++ b/src/drivers/intel/ish/ish.c
@@ -91,6 +91,7 @@ static const unsigned short pci_device_ids[] = {
 	PCI_DID_INTEL_LNL_ISHB,
 	PCI_DID_INTEL_MTL_ISHB,
 	PCI_DID_INTEL_ARL_ISHB,
+	PCI_DID_INTEL_ARP_S_ISHB,
 	PCI_DID_INTEL_CNL_ISHB,
 	PCI_DID_INTEL_CML_ISHB,
 	PCI_DID_INTEL_TGL_ISHB,
diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h
index 93d2e81e61..908ac17d50 100644
--- a/src/include/device/pci_ids.h
+++ b/src/include/device/pci_ids.h
@@ -2183,6 +2183,7 @@
 #define PCI_DID_INTEL_TGL_H_ISHB	0x43fc
 #define PCI_DID_INTEL_MTL_ISHB		0x7e45
 #define PCI_DID_INTEL_ARL_ISHB		0x7745
+#define PCI_DID_INTEL_ARP_S_ISHB	0x7f78
 #define PCI_DID_INTEL_ADL_N_ISHB	0x54fc
 #define PCI_DID_INTEL_ADL_P_ISHB	0x51fc
 #define PCI_DID_INTEL_LNL_ISHB		0xa845
@@ -3146,6 +3147,70 @@
 #define PCI_DID_INTEL_ARL_H_ESPI_0			0x7202
 #define PCI_DID_INTEL_ARL_H_ESPI_1			0x7702
 #define PCI_DID_INTEL_ARL_U_ESPI_0			0x7203
+#define PCI_DID_INTEL_ARL_S_ESPI_0			0xae00
+#define PCI_DID_INTEL_ARL_S_ESPI_1			0xae01
+#define PCI_DID_INTEL_ARL_S_ESPI_2			0xae02
+#define PCI_DID_INTEL_ARL_S_ESPI_3			0xae03
+#define PCI_DID_INTEL_ARL_S_ESPI_4			0xae04
+#define PCI_DID_INTEL_ARL_S_ESPI_5			0xae05
+#define PCI_DID_INTEL_ARL_S_ESPI_6			0xae06
+#define PCI_DID_INTEL_ARL_S_ESPI_7			0xae07
+#define PCI_DID_INTEL_ARL_S_ESPI_8			0xae08
+#define PCI_DID_INTEL_ARL_S_ESPI_9			0xae09
+#define PCI_DID_INTEL_ARL_S_ESPI_10			0xae0a
+#define PCI_DID_INTEL_ARL_S_ESPI_11			0xae0b
+#define PCI_DID_INTEL_ARL_S_ESPI_12			0xae0c
+#define PCI_DID_INTEL_ARL_S_ESPI_13			0xae0d
+#define PCI_DID_INTEL_ARL_S_ESPI_14			0xae0e
+#define PCI_DID_INTEL_ARL_S_ESPI_15			0xae0f
+#define PCI_DID_INTEL_ARL_S_ESPI_16			0xae10
+#define PCI_DID_INTEL_ARL_S_ESPI_17			0xae11
+#define PCI_DID_INTEL_ARL_S_ESPI_18			0xae12
+#define PCI_DID_INTEL_ARL_S_ESPI_19			0xae13
+#define PCI_DID_INTEL_ARL_S_ESPI_20			0xae14
+#define PCI_DID_INTEL_ARL_S_ESPI_21			0xae15
+#define PCI_DID_INTEL_ARL_S_ESPI_22			0xae16
+#define PCI_DID_INTEL_ARL_S_ESPI_23			0xae17
+#define PCI_DID_INTEL_ARL_S_ESPI_24			0xae18
+#define PCI_DID_INTEL_ARL_S_ESPI_25			0xae19
+#define PCI_DID_INTEL_ARL_S_ESPI_26			0xae1a
+#define PCI_DID_INTEL_ARL_S_ESPI_27			0xae1b
+#define PCI_DID_INTEL_ARL_S_ESPI_28			0xae1c
+#define PCI_DID_INTEL_ARL_S_ESPI_29			0xae1d
+#define PCI_DID_INTEL_ARL_S_ESPI_30			0xae1e
+#define PCI_DID_INTEL_ARL_S_ESPI_31			0xae1f
+#define PCI_DID_INTEL_ARP_S_ESPI_0			0x7f00
+#define PCI_DID_INTEL_ARP_S_ESPI_1			0x7f01
+#define PCI_DID_INTEL_ARP_S_ESPI_2			0x7f02
+#define PCI_DID_INTEL_ARP_S_ESPI_3			0x7f03
+#define PCI_DID_INTEL_ARP_S_ESPI_4			0x7f04
+#define PCI_DID_INTEL_ARP_S_ESPI_5			0x7f05
+#define PCI_DID_INTEL_ARP_S_ESPI_6			0x7f06
+#define PCI_DID_INTEL_ARP_S_ESPI_7			0x7f07
+#define PCI_DID_INTEL_ARP_S_ESPI_8			0x7f08
+#define PCI_DID_INTEL_ARP_S_ESPI_9			0x7f09
+#define PCI_DID_INTEL_ARP_S_ESPI_10			0x7f0a
+#define PCI_DID_INTEL_ARP_S_ESPI_11			0x7f0b
+#define PCI_DID_INTEL_ARP_S_ESPI_12			0x7f0c
+#define PCI_DID_INTEL_ARP_S_ESPI_13			0x7f0d
+#define PCI_DID_INTEL_ARP_S_ESPI_14			0x7f0e
+#define PCI_DID_INTEL_ARP_S_ESPI_15			0x7f0f
+#define PCI_DID_INTEL_ARP_S_ESPI_16			0x7f10
+#define PCI_DID_INTEL_ARP_S_ESPI_17			0x7f11
+#define PCI_DID_INTEL_ARP_S_ESPI_18			0x7f12
+#define PCI_DID_INTEL_ARP_S_ESPI_19			0x7f13
+#define PCI_DID_INTEL_ARP_S_ESPI_20			0x7f14
+#define PCI_DID_INTEL_ARP_S_ESPI_21			0x7f15
+#define PCI_DID_INTEL_ARP_S_ESPI_22			0x7f16
+#define PCI_DID_INTEL_ARP_S_ESPI_23			0x7f17
+#define PCI_DID_INTEL_ARP_S_ESPI_24			0x7f18
+#define PCI_DID_INTEL_ARP_S_ESPI_25			0x7f19
+#define PCI_DID_INTEL_ARP_S_ESPI_26			0x7f1a
+#define PCI_DID_INTEL_ARP_S_ESPI_27			0x7f1b
+#define PCI_DID_INTEL_ARP_S_ESPI_28			0x7f1c
+#define PCI_DID_INTEL_ARP_S_ESPI_29			0x7f1d
+#define PCI_DID_INTEL_ARP_S_ESPI_30			0x7f1e
+#define PCI_DID_INTEL_ARP_S_ESPI_31			0x7f1f
 #define PCI_DID_INTEL_RPP_P_ESPI_0			0x5180
 #define PCI_DID_INTEL_RPP_P_ADP_P_ESPI_1		0x5181
 #define PCI_DID_INTEL_RPP_P_ADP_P_ESPI_2		0x5182
@@ -3650,6 +3715,34 @@
 #define PCI_DID_INTEL_ARL_SOC_PCIE_RP7			0x773e
 #define PCI_DID_INTEL_ARL_SOC_PCIE_RP8			0x773f
 #define PCI_DID_INTEL_ARL_SOC_PCIE_RP9			0x774d
+#define PCI_DID_INTEL_ARL_S_PCIE_RP13			0xae4d
+#define PCI_DID_INTEL_ARL_S_PCIE_RP14			0xae4e
+#define PCI_DID_INTEL_ARL_S_PCIE_RP15			0xae4f
+
+#define PCI_DID_INTEL_ARP_S_PCIE_RP1			0x7f38
+#define PCI_DID_INTEL_ARP_S_PCIE_RP2			0x7f39
+#define PCI_DID_INTEL_ARP_S_PCIE_RP3			0x7f3a
+#define PCI_DID_INTEL_ARP_S_PCIE_RP4			0x7f3b
+#define PCI_DID_INTEL_ARP_S_PCIE_RP5			0x7f3c
+#define PCI_DID_INTEL_ARP_S_PCIE_RP6			0x7f3d
+#define PCI_DID_INTEL_ARP_S_PCIE_RP7			0x7f3e
+#define PCI_DID_INTEL_ARP_S_PCIE_RP8			0x7f3f
+#define PCI_DID_INTEL_ARP_S_PCIE_RP9			0x7f30
+#define PCI_DID_INTEL_ARP_S_PCIE_RP10			0x7f31
+#define PCI_DID_INTEL_ARP_S_PCIE_RP11			0x7f32
+#define PCI_DID_INTEL_ARP_S_PCIE_RP12			0x7f33
+#define PCI_DID_INTEL_ARP_S_PCIE_RP13			0x7f34
+#define PCI_DID_INTEL_ARP_S_PCIE_RP14			0x7f35
+#define PCI_DID_INTEL_ARP_S_PCIE_RP15			0x7f36
+#define PCI_DID_INTEL_ARP_S_PCIE_RP16			0x7f37
+#define PCI_DID_INTEL_ARP_S_PCIE_RP17			0x7f40
+#define PCI_DID_INTEL_ARP_S_PCIE_RP18			0x7f41
+#define PCI_DID_INTEL_ARP_S_PCIE_RP19			0x7f42
+#define PCI_DID_INTEL_ARP_S_PCIE_RP20			0x7f43
+#define PCI_DID_INTEL_ARP_S_PCIE_RP21			0x7f44
+#define PCI_DID_INTEL_ARP_S_PCIE_RP22			0x7f45
+#define PCI_DID_INTEL_ARP_S_PCIE_RP23			0x7f46
+#define PCI_DID_INTEL_ARP_S_PCIE_RP24			0x7f47
 
 #define PCI_DID_INTEL_RPL_P_PCIE_RP1			0xa74d
 #define PCI_DID_INTEL_RPL_P_PCIE_RP2			0xa70d
@@ -3820,6 +3913,8 @@
 #define PCI_DID_INTEL_ADP_M_SATA_3		0x282a
 #define PCI_DID_INTEL_MTL_SATA			0x7e63
 #define PCI_DID_INTEL_ARL_SATA			0x7763
+#define PCI_DID_INTEL_ARP_S_SATA_1		0x7f62
+#define PCI_DID_INTEL_ARP_S_SATA_2		0x7f66
 #define PCI_DID_INTEL_RPP_P_SATA_1		0x51d3
 #define PCI_DID_INTEL_RPP_P_SATA_2		0x51d7
 #define PCI_DID_INTEL_RPP_S_SATA		0x7a62
@@ -3850,6 +3945,8 @@
 #define PCI_DID_INTEL_MTL_IOE_M_PMC		0x7ebe
 #define PCI_DID_INTEL_MTL_IOE_P_PMC		0x7ece
 #define PCI_DID_INTEL_ARL_SOC_PMC		0x7721
+#define PCI_DID_INTEL_ARL_IOE_S_PMC		0xae21
+#define PCI_DID_INTEL_ARP_S_PMC			0x7f21
 #define PCI_DID_INTEL_RPP_P_PMC			0x51a1
 #define PCI_DID_INTEL_RPP_S_PMC			0x7a21
 #define PCI_DID_INTEL_LNL_PMC			0xa821
@@ -3987,6 +4084,13 @@
 #define PCI_DID_INTEL_ARL_I2C4			0x7750
 #define PCI_DID_INTEL_ARL_I2C5			0x7751
 
+#define PCI_DID_INTEL_ARP_S_I2C0		0x7f4c
+#define PCI_DID_INTEL_ARP_S_I2C1		0x7f4d
+#define PCI_DID_INTEL_ARP_S_I2C2		0x7f4e
+#define PCI_DID_INTEL_ARP_S_I2C3		0x7f4f
+#define PCI_DID_INTEL_ARP_S_I2C4		0x7f7a
+#define PCI_DID_INTEL_ARP_S_I2C5		0x7f7b
+
 #define PCI_DID_INTEL_LNL_I2C0			0xa878
 #define PCI_DID_INTEL_LNL_I2C1			0xa879
 #define PCI_DID_INTEL_LNL_I2C2			0xa87a
@@ -4097,6 +4201,11 @@
 #define PCI_DID_INTEL_ARL_UART1			0x7726
 #define PCI_DID_INTEL_ARL_UART2			0x7752
 
+#define PCI_DID_INTEL_ARP_S_UART0		0x7f28
+#define PCI_DID_INTEL_ARP_S_UART1		0x7f29
+#define PCI_DID_INTEL_ARP_S_UART2		0x7f5c
+#define PCI_DID_INTEL_ARP_S_UART3		0x7f5d
+
 #define PCI_DID_INTEL_LNL_UART0			0xa825
 #define PCI_DID_INTEL_LNL_UART1			0xa826
 #define PCI_DID_INTEL_LNL_UART2			0xa852
@@ -4211,6 +4320,13 @@
 #define PCI_DID_INTEL_ARL_GSPI1			0x7730
 #define PCI_DID_INTEL_ARL_GSPI2			0x7746
 
+#define PCI_DID_INTEL_ARL_S_HWSEQ_SPI		0xae23
+#define PCI_DID_INTEL_ARP_S_HWSEQ_SPI		0x7f24
+#define PCI_DID_INTEL_ARP_S_GSPI0		0x7f2a
+#define PCI_DID_INTEL_ARP_S_GSPI1		0x7f2b
+#define PCI_DID_INTEL_ARP_S_GSPI2		0x7f5e
+#define PCI_DID_INTEL_ARP_S_GSPI3		0x7f5f
+
 #define PCI_DID_INTEL_LNL_HWSEQ_SPI		0xa823
 #define PCI_DID_INTEL_LNL_GSPI0			0xa827
 #define PCI_DID_INTEL_LNL_GSPI1			0xa830
@@ -4597,6 +4713,8 @@
 #define PCI_DID_INTEL_ADP_M_N_SMBUS			0x54a3
 #define PCI_DID_INTEL_MTL_SMBUS				0x7e22
 #define PCI_DID_INTEL_ARL_SMBUS				0x7722
+#define PCI_DID_INTEL_ARL_S_SMBUS			0xae22
+#define PCI_DID_INTEL_ARP_S_SMBUS			0x7f22
 #define PCI_DID_INTEL_RPP_P_SMBUS			0x51a3
 #define PCI_DID_INTEL_RPP_S_SMBUS			0x7a23
 #define PCI_DID_INTEL_LNL_SMBUS				0xa822
@@ -4642,6 +4760,7 @@
 #define PCI_DID_INTEL_MTL_M_TCSS_XHCI		0x7eb0
 #define PCI_DID_INTEL_MTL_P_TCSS_XHCI		0x7ec0
 #define PCI_DID_INTEL_ARL_XHCI			0x777d
+#define PCI_DID_INTEL_ARP_S_XHCI		0x7f6e
 #define PCI_DID_INTEL_RPP_P_TCSS_XHCI		0xa71e
 #define PCI_DID_INTEL_RPP_S_XHCI		0x7a60
 #define PCI_DID_INTEL_LNL_XHCI			0xa87d
@@ -4678,6 +4797,8 @@
 #define PCI_DID_INTEL_MTL_IOE_M_P2SB		0x7eb8
 #define PCI_DID_INTEL_MTL_IOE_P_P2SB		0x7ec8
 #define PCI_DID_INTEL_ARL_SOC_P2SB		0x7720
+#define PCI_DID_INTEL_ARL_IOE_S_P2SB		0xae20
+#define PCI_DID_INTEL_ARP_S_P2SB		0x7f20
 #define PCI_DID_INTEL_RPP_P_P2SB		0x51a0
 #define PCI_DID_INTEL_RPP_S_P2SB		0x7a20
 #define PCI_DID_INTEL_LNL_P2SB			0xa820
@@ -4704,6 +4825,8 @@
 #define PCI_DID_INTEL_MTL_IOE_M_SRAM		0x7ebf
 #define PCI_DID_INTEL_MTL_IOE_P_SRAM		0x7ecf
 #define PCI_DID_INTEL_ARL_SOC_SRAM		0x777f
+#define PCI_DID_INTEL_ARL_SOC_S_SRAM		0xae7f
+#define PCI_DID_INTEL_ARP_S_SRAM		0x7f27
 #define PCI_DID_INTEL_LNL_SRAM			0xa87f
 #define PCI_DID_INTEL_PTL_H_SRAM		0xe47f
 #define PCI_DID_INTEL_PTL_U_H_SRAM		0xe37f
@@ -4767,6 +4890,8 @@
 
 #define PCI_DID_INTEL_ARL_AUDIO		0x7728
 
+#define PCI_DID_INTEL_ARP_S_AUDIO		0x7f50
+
 #define PCI_DID_INTEL_LNL_AUDIO_1		0xa828
 #define PCI_DID_INTEL_LNL_AUDIO_2		0xa829
 #define PCI_DID_INTEL_LNL_AUDIO_3		0xa82a
@@ -4847,6 +4972,13 @@
 #define PCI_DID_INTEL_RPP_S_CSE3		0x7a6d
 #define PCI_DID_INTEL_MTL_CSE0			0x7e70
 #define PCI_DID_INTEL_ARL_CSE0			0x7770
+#define PCI_DID_INTEL_ARL_S_CSE0		0xae70
+#define PCI_DID_INTEL_ARL_S_CSE1		0xae71
+#define PCI_DID_INTEL_ARL_S_CSE2		0xae74
+#define PCI_DID_INTEL_ARP_S_CSE0		0x7f68
+#define PCI_DID_INTEL_ARP_S_CSE1		0x7f69
+#define PCI_DID_INTEL_ARP_S_CSE2		0x7f6c
+#define PCI_DID_INTEL_ARP_S_CSE3		0x7f6d
 #define PCI_DID_INTEL_LNL_CSE0			0xa870
 #define PCI_DID_INTEL_PTL_H_CSE0		0xe470
 #define PCI_DID_INTEL_PTL_U_H_CSE0		0xe370
@@ -4876,6 +5008,7 @@
 #define PCI_DID_INTEL_MTL_M_TCSS_XDCI		0x7eb1
 #define PCI_DID_INTEL_MTL_P_TCSS_XDCI		0x7ec1
 #define PCI_DID_INTEL_ARL_XDCI			0x777e
+#define PCI_DID_INTEL_ARP_S_XDCI			0x7f6f
 #define PCI_DID_INTEL_PTL_H_XDCI		0xe47e
 #define PCI_DID_INTEL_PTL_U_H_XDCI		0xe37e
 #define PCI_DID_INTEL_WCL_XDCI		0x4d7e
@@ -4989,6 +5122,7 @@
 #define PCI_DID_INTEL_JSL_DTT			0x4E03
 #define PCI_DID_INTEL_ADL_DTT			0x461d
 #define PCI_DID_INTEL_MTL_DTT			0x7d03
+#define PCI_DID_INTEL_ARL_S_DTT			0xad03
 #define PCI_DID_INTEL_RPL_DTT			0xa71d
 #define PCI_DID_INTEL_PTL_DTT			0xb01d
 #define PCI_DID_INTEL_WCL_DTT			0xfd1d
@@ -5035,6 +5169,7 @@
 #define PCI_DID_INTEL_MTL_CNVI_WIFI_2		0x7e42
 #define PCI_DID_INTEL_MTL_CNVI_WIFI_3		0x7e43
 #define PCI_DID_INTEL_ARL_CNVI_WIFI		0x7740
+#define PCI_DID_INTEL_ARP_S_CNVI_WIFI		0x7f70
 #define PCI_DID_INTEL_RPL_S_CNVI_WIFI_0		0x7a70
 #define PCI_DID_INTEL_RPL_S_CNVI_WIFI_1		0x7a71
 #define PCI_DID_INTEL_RPL_S_CNVI_WIFI_2		0x7a72
@@ -5079,6 +5214,7 @@
 #define PCI_DID_INTEL_ADP_N_PMC_CRASHLOG_SRAM		0x54ef
 #define PCI_DID_INTEL_TGP_PMC_CRASHLOG_SRAM		0xa0ef
 #define PCI_DID_INTEL_MTL_CRASHLOG_SRAM			0x7d0d
+#define PCI_DID_INTEL_ARL_S_CRASHLOG_SRAM		0xad0d
 #define PCI_DID_INTEL_RPL_CPU_CRASHLOG_SRAM		0xa77d
 #define PCI_DID_INTEL_RPP_S_PMC_CRASHLOG_SRAM		0x7a27
 #define PCI_DID_INTEL_PTL_PUNIT_CRASHLOG_SRAM		0xb07d
@@ -5087,6 +5223,8 @@
 /* Intel Trace Hub */
 #define PCI_DID_INTEL_MTL_TRACEHUB			0x7e24
 #define PCI_DID_INTEL_ARL_TRACEHUB			0x7724
+#define PCI_DID_INTEL_ARL_S_TRACEHUB			0xae24
+#define PCI_DID_INTEL_ARP_S_TRACEHUB			0x7f26
 #define PCI_DID_INTEL_RPL_TRACEHUB			0xa76f
 #define PCI_DID_INTEL_PTL_H_TRACEHUB			0xe424
 #define PCI_DID_INTEL_PTL_U_H_TRACEHUB			0xe324
@@ -5118,6 +5256,10 @@
 #define PCI_DID_INTEL_ARL_THC0_2	0x7749
 #define PCI_DID_INTEL_ARL_THC1_1	0x774a
 #define PCI_DID_INTEL_ARL_THC1_2	0x774b
+#define PCI_DID_INTEL_ARP_S_THC0_1	0x7f58
+#define PCI_DID_INTEL_ARP_S_THC0_2	0x7f59
+#define PCI_DID_INTEL_ARP_S_THC1_1	0x7f5a
+#define PCI_DID_INTEL_ARP_S_THC1_2	0x7f5b
 
 #define PCI_VID_COMPUTONE		0x8e0e
 #define PCI_DID_COMPUTONE_IP2EX		0x0291
diff --git a/src/soc/intel/common/block/cnvi/cnvi.c b/src/soc/intel/common/block/cnvi/cnvi.c
index cb19abc2e5..6ca91b1190 100644
--- a/src/soc/intel/common/block/cnvi/cnvi.c
+++ b/src/soc/intel/common/block/cnvi/cnvi.c
@@ -489,6 +489,7 @@ static const unsigned short wifi_pci_device_ids[] = {
 	PCI_DID_INTEL_MTL_CNVI_WIFI_2,
 	PCI_DID_INTEL_MTL_CNVI_WIFI_3,
 	PCI_DID_INTEL_ARL_CNVI_WIFI,
+	PCI_DID_INTEL_ARP_S_CNVI_WIFI,
 	PCI_DID_INTEL_CML_LP_CNVI_WIFI,
 	PCI_DID_INTEL_CML_H_CNVI_WIFI,
 	PCI_DID_INTEL_CNL_LP_CNVI_WIFI,
diff --git a/src/soc/intel/common/block/cse/cse.c b/src/soc/intel/common/block/cse/cse.c
index 58999c0b9f..1f519312ce 100644
--- a/src/soc/intel/common/block/cse/cse.c
+++ b/src/soc/intel/common/block/cse/cse.c
@@ -1533,6 +1533,13 @@ static const unsigned short pci_device_ids[] = {
 	PCI_DID_INTEL_LNL_CSE0,
 	PCI_DID_INTEL_MTL_CSE0,
 	PCI_DID_INTEL_ARL_CSE0,
+	PCI_DID_INTEL_ARL_S_CSE0,
+	PCI_DID_INTEL_ARL_S_CSE1,
+	PCI_DID_INTEL_ARL_S_CSE2,
+	PCI_DID_INTEL_ARP_S_CSE0,
+	PCI_DID_INTEL_ARP_S_CSE1,
+	PCI_DID_INTEL_ARP_S_CSE2,
+	PCI_DID_INTEL_ARP_S_CSE3,
 	PCI_DID_INTEL_APL_CSE0,
 	PCI_DID_INTEL_GLK_CSE0,
 	PCI_DID_INTEL_CNL_CSE0,
diff --git a/src/soc/intel/common/block/dsp/dsp.c b/src/soc/intel/common/block/dsp/dsp.c
index f36ab088aa..af43a99e77 100644
--- a/src/soc/intel/common/block/dsp/dsp.c
+++ b/src/soc/intel/common/block/dsp/dsp.c
@@ -54,6 +54,7 @@ static const unsigned short pci_device_ids[] = {
 	PCI_DID_INTEL_MTL_AUDIO_7,
 	PCI_DID_INTEL_MTL_AUDIO_8,
 	PCI_DID_INTEL_ARL_AUDIO,
+	PCI_DID_INTEL_ARP_S_AUDIO,
 	PCI_DID_INTEL_RPP_P_AUDIO,
 	PCI_DID_INTEL_RPP_S_AUDIO_1,
 	PCI_DID_INTEL_RPP_S_AUDIO_2,
diff --git a/src/soc/intel/common/block/dtt/dtt.c b/src/soc/intel/common/block/dtt/dtt.c
index 1d0451fc78..4274b8976d 100644
--- a/src/soc/intel/common/block/dtt/dtt.c
+++ b/src/soc/intel/common/block/dtt/dtt.c
@@ -12,6 +12,7 @@ static const unsigned short pci_device_ids[] = {
 	PCI_DID_INTEL_PTL_DTT,
 	PCI_DID_INTEL_RPL_DTT,
 	PCI_DID_INTEL_MTL_DTT,
+	PCI_DID_INTEL_ARL_S_DTT,
 	PCI_DID_INTEL_CML_DTT,
 	PCI_DID_INTEL_TGL_DTT,
 	PCI_DID_INTEL_JSL_DTT,
diff --git a/src/soc/intel/common/block/fast_spi/fast_spi.c b/src/soc/intel/common/block/fast_spi/fast_spi.c
index b5ee53a715..f7abaa2743 100644
--- a/src/soc/intel/common/block/fast_spi/fast_spi.c
+++ b/src/soc/intel/common/block/fast_spi/fast_spi.c
@@ -578,6 +578,8 @@ static const unsigned short pci_device_ids[] = {
 	PCI_DID_INTEL_MCC_SPI0,
 	PCI_DID_INTEL_MTL_HWSEQ_SPI,
 	PCI_DID_INTEL_ARL_HWSEQ_SPI,
+	PCI_DID_INTEL_ARL_S_HWSEQ_SPI,
+	PCI_DID_INTEL_ARP_S_HWSEQ_SPI,
 	PCI_DID_INTEL_RPP_S_HWSEQ_SPI,
 	PCI_DID_INTEL_SPR_HWSEQ_SPI,
 	PCI_DID_INTEL_TGP_SPI0,
diff --git a/src/soc/intel/common/block/hda/hda.c b/src/soc/intel/common/block/hda/hda.c
index f375e0c58d..37dc9ea91b 100644
--- a/src/soc/intel/common/block/hda/hda.c
+++ b/src/soc/intel/common/block/hda/hda.c
@@ -70,6 +70,7 @@ static const unsigned short pci_device_ids[] = {
 	PCI_DID_INTEL_MTL_AUDIO_7,
 	PCI_DID_INTEL_MTL_AUDIO_8,
 	PCI_DID_INTEL_ARL_AUDIO,
+	PCI_DID_INTEL_ARP_S_AUDIO,
 	PCI_DID_INTEL_RPP_P_AUDIO,
 	PCI_DID_INTEL_RPP_S_AUDIO_1,
 	PCI_DID_INTEL_RPP_S_AUDIO_2,
diff --git a/src/soc/intel/common/block/i2c/i2c.c b/src/soc/intel/common/block/i2c/i2c.c
index dfb14a0ea5..2c0e010ccb 100644
--- a/src/soc/intel/common/block/i2c/i2c.c
+++ b/src/soc/intel/common/block/i2c/i2c.c
@@ -210,6 +210,12 @@ static const unsigned short pci_device_ids[] = {
 	PCI_DID_INTEL_ARL_I2C3,
 	PCI_DID_INTEL_ARL_I2C4,
 	PCI_DID_INTEL_ARL_I2C5,
+	PCI_DID_INTEL_ARP_S_I2C0,
+	PCI_DID_INTEL_ARP_S_I2C1,
+	PCI_DID_INTEL_ARP_S_I2C2,
+	PCI_DID_INTEL_ARP_S_I2C3,
+	PCI_DID_INTEL_ARP_S_I2C4,
+	PCI_DID_INTEL_ARP_S_I2C5,
 	PCI_DID_INTEL_APL_I2C0,
 	PCI_DID_INTEL_APL_I2C1,
 	PCI_DID_INTEL_APL_I2C2,
diff --git a/src/soc/intel/common/block/lpc/lpc.c b/src/soc/intel/common/block/lpc/lpc.c
index 960a26f7d3..118adea1f0 100644
--- a/src/soc/intel/common/block/lpc/lpc.c
+++ b/src/soc/intel/common/block/lpc/lpc.c
@@ -266,6 +266,70 @@ static const unsigned short pci_device_ids[] = {
 	PCI_DID_INTEL_ARL_H_ESPI_0,
 	PCI_DID_INTEL_ARL_H_ESPI_1,
 	PCI_DID_INTEL_ARL_U_ESPI_0,
+	PCI_DID_INTEL_ARL_S_ESPI_0,
+	PCI_DID_INTEL_ARL_S_ESPI_1,
+	PCI_DID_INTEL_ARL_S_ESPI_2,
+	PCI_DID_INTEL_ARL_S_ESPI_3,
+	PCI_DID_INTEL_ARL_S_ESPI_4,
+	PCI_DID_INTEL_ARL_S_ESPI_5,
+	PCI_DID_INTEL_ARL_S_ESPI_6,
+	PCI_DID_INTEL_ARL_S_ESPI_7,
+	PCI_DID_INTEL_ARL_S_ESPI_8,
+	PCI_DID_INTEL_ARL_S_ESPI_9,
+	PCI_DID_INTEL_ARL_S_ESPI_10,
+	PCI_DID_INTEL_ARL_S_ESPI_11,
+	PCI_DID_INTEL_ARL_S_ESPI_12,
+	PCI_DID_INTEL_ARL_S_ESPI_13,
+	PCI_DID_INTEL_ARL_S_ESPI_14,
+	PCI_DID_INTEL_ARL_S_ESPI_15,
+	PCI_DID_INTEL_ARL_S_ESPI_16,
+	PCI_DID_INTEL_ARL_S_ESPI_17,
+	PCI_DID_INTEL_ARL_S_ESPI_18,
+	PCI_DID_INTEL_ARL_S_ESPI_19,
+	PCI_DID_INTEL_ARL_S_ESPI_20,
+	PCI_DID_INTEL_ARL_S_ESPI_21,
+	PCI_DID_INTEL_ARL_S_ESPI_22,
+	PCI_DID_INTEL_ARL_S_ESPI_23,
+	PCI_DID_INTEL_ARL_S_ESPI_24,
+	PCI_DID_INTEL_ARL_S_ESPI_25,
+	PCI_DID_INTEL_ARL_S_ESPI_26,
+	PCI_DID_INTEL_ARL_S_ESPI_27,
+	PCI_DID_INTEL_ARL_S_ESPI_28,
+	PCI_DID_INTEL_ARL_S_ESPI_29,
+	PCI_DID_INTEL_ARL_S_ESPI_30,
+	PCI_DID_INTEL_ARL_S_ESPI_31,
+	PCI_DID_INTEL_ARP_S_ESPI_0,
+	PCI_DID_INTEL_ARP_S_ESPI_1,
+	PCI_DID_INTEL_ARP_S_ESPI_2,
+	PCI_DID_INTEL_ARP_S_ESPI_3,
+	PCI_DID_INTEL_ARP_S_ESPI_4,
+	PCI_DID_INTEL_ARP_S_ESPI_5,
+	PCI_DID_INTEL_ARP_S_ESPI_6,
+	PCI_DID_INTEL_ARP_S_ESPI_7,
+	PCI_DID_INTEL_ARP_S_ESPI_8,
+	PCI_DID_INTEL_ARP_S_ESPI_9,
+	PCI_DID_INTEL_ARP_S_ESPI_10,
+	PCI_DID_INTEL_ARP_S_ESPI_11,
+	PCI_DID_INTEL_ARP_S_ESPI_12,
+	PCI_DID_INTEL_ARP_S_ESPI_13,
+	PCI_DID_INTEL_ARP_S_ESPI_14,
+	PCI_DID_INTEL_ARP_S_ESPI_15,
+	PCI_DID_INTEL_ARP_S_ESPI_16,
+	PCI_DID_INTEL_ARP_S_ESPI_17,
+	PCI_DID_INTEL_ARP_S_ESPI_18,
+	PCI_DID_INTEL_ARP_S_ESPI_19,
+	PCI_DID_INTEL_ARP_S_ESPI_20,
+	PCI_DID_INTEL_ARP_S_ESPI_21,
+	PCI_DID_INTEL_ARP_S_ESPI_22,
+	PCI_DID_INTEL_ARP_S_ESPI_23,
+	PCI_DID_INTEL_ARP_S_ESPI_24,
+	PCI_DID_INTEL_ARP_S_ESPI_25,
+	PCI_DID_INTEL_ARP_S_ESPI_26,
+	PCI_DID_INTEL_ARP_S_ESPI_27,
+	PCI_DID_INTEL_ARP_S_ESPI_28,
+	PCI_DID_INTEL_ARP_S_ESPI_29,
+	PCI_DID_INTEL_ARP_S_ESPI_30,
+	PCI_DID_INTEL_ARP_S_ESPI_31,
 	PCI_DID_INTEL_RPP_P_ESPI_0,
 	PCI_DID_INTEL_RPP_P_ADP_P_ESPI_1,
 	PCI_DID_INTEL_RPP_P_ADP_P_ESPI_2,
diff --git a/src/soc/intel/common/block/p2sb/p2sb.c b/src/soc/intel/common/block/p2sb/p2sb.c
index 1986e4ce4f..fea3103026 100644
--- a/src/soc/intel/common/block/p2sb/p2sb.c
+++ b/src/soc/intel/common/block/p2sb/p2sb.c
@@ -143,6 +143,8 @@ static const unsigned short pci_device_ids[] = {
 	PCI_DID_INTEL_LNL_P2SB,
 	PCI_DID_INTEL_MTL_SOC_P2SB,
 	PCI_DID_INTEL_ARL_SOC_P2SB,
+	PCI_DID_INTEL_ARL_IOE_S_P2SB,
+	PCI_DID_INTEL_ARP_S_P2SB,
 	PCI_DID_INTEL_RPP_P_P2SB,
 	PCI_DID_INTEL_APL_P2SB,
 	PCI_DID_INTEL_GLK_P2SB,
diff --git a/src/soc/intel/common/block/pcie/pcie.c b/src/soc/intel/common/block/pcie/pcie.c
index 1b3e148f15..18b938e280 100644
--- a/src/soc/intel/common/block/pcie/pcie.c
+++ b/src/soc/intel/common/block/pcie/pcie.c
@@ -128,6 +128,33 @@ static const unsigned short pcie_device_ids[] = {
 	PCI_DID_INTEL_ARL_SOC_PCIE_RP7,
 	PCI_DID_INTEL_ARL_SOC_PCIE_RP8,
 	PCI_DID_INTEL_ARL_SOC_PCIE_RP9,
+	PCI_DID_INTEL_ARL_S_PCIE_RP13,
+	PCI_DID_INTEL_ARL_S_PCIE_RP14,
+	PCI_DID_INTEL_ARL_S_PCIE_RP15,
+	PCI_DID_INTEL_ARP_S_PCIE_RP1,
+	PCI_DID_INTEL_ARP_S_PCIE_RP2,
+	PCI_DID_INTEL_ARP_S_PCIE_RP3,
+	PCI_DID_INTEL_ARP_S_PCIE_RP4,
+	PCI_DID_INTEL_ARP_S_PCIE_RP5,
+	PCI_DID_INTEL_ARP_S_PCIE_RP6,
+	PCI_DID_INTEL_ARP_S_PCIE_RP7,
+	PCI_DID_INTEL_ARP_S_PCIE_RP8,
+	PCI_DID_INTEL_ARP_S_PCIE_RP9,
+	PCI_DID_INTEL_ARP_S_PCIE_RP10,
+	PCI_DID_INTEL_ARP_S_PCIE_RP11,
+	PCI_DID_INTEL_ARP_S_PCIE_RP12,
+	PCI_DID_INTEL_ARP_S_PCIE_RP13,
+	PCI_DID_INTEL_ARP_S_PCIE_RP14,
+	PCI_DID_INTEL_ARP_S_PCIE_RP15,
+	PCI_DID_INTEL_ARP_S_PCIE_RP16,
+	PCI_DID_INTEL_ARP_S_PCIE_RP17,
+	PCI_DID_INTEL_ARP_S_PCIE_RP18,
+	PCI_DID_INTEL_ARP_S_PCIE_RP19,
+	PCI_DID_INTEL_ARP_S_PCIE_RP20,
+	PCI_DID_INTEL_ARP_S_PCIE_RP21,
+	PCI_DID_INTEL_ARP_S_PCIE_RP22,
+	PCI_DID_INTEL_ARP_S_PCIE_RP23,
+	PCI_DID_INTEL_ARP_S_PCIE_RP24,
 	PCI_DID_INTEL_LWB_PCIE_RP1,
 	PCI_DID_INTEL_LWB_PCIE_RP2,
 	PCI_DID_INTEL_LWB_PCIE_RP3,
diff --git a/src/soc/intel/common/block/pmc/pmc.c b/src/soc/intel/common/block/pmc/pmc.c
index dbdf2fe5fd..09c08cdbb5 100644
--- a/src/soc/intel/common/block/pmc/pmc.c
+++ b/src/soc/intel/common/block/pmc/pmc.c
@@ -119,6 +119,8 @@ static const unsigned short pci_device_ids[] = {
 	PCI_DID_INTEL_MTL_IOE_M_PMC,
 	PCI_DID_INTEL_MTL_IOE_P_PMC,
 	PCI_DID_INTEL_ARL_SOC_PMC,
+	PCI_DID_INTEL_ARL_IOE_S_PMC,
+	PCI_DID_INTEL_ARP_S_PMC,
 	PCI_DID_INTEL_RPP_P_PMC,
 	PCI_DID_INTEL_DNV_PMC,
 	PCI_DID_INTEL_LWB_PMC,
diff --git a/src/soc/intel/common/block/sata/sata.c b/src/soc/intel/common/block/sata/sata.c
index ae51efa95c..f406096c85 100644
--- a/src/soc/intel/common/block/sata/sata.c
+++ b/src/soc/intel/common/block/sata/sata.c
@@ -37,6 +37,8 @@ struct device_operations sata_ops = {
 static const unsigned short pci_device_ids[] = {
 	PCI_DID_INTEL_MTL_SATA,
 	PCI_DID_INTEL_ARL_SATA,
+	PCI_DID_INTEL_ARP_S_SATA_1,
+	PCI_DID_INTEL_ARP_S_SATA_2,
 	PCI_DID_INTEL_RPP_P_SATA_1,
 	PCI_DID_INTEL_RPP_P_SATA_2,
 	PCI_DID_INTEL_RPP_S_SATA,
diff --git a/src/soc/intel/common/block/smbus/smbus.c b/src/soc/intel/common/block/smbus/smbus.c
index fc8c0aff09..dba5ed29d8 100644
--- a/src/soc/intel/common/block/smbus/smbus.c
+++ b/src/soc/intel/common/block/smbus/smbus.c
@@ -55,6 +55,8 @@ static const unsigned short pci_device_ids[] = {
 	PCI_DID_INTEL_LNL_SMBUS,
 	PCI_DID_INTEL_MTL_SMBUS,
 	PCI_DID_INTEL_ARL_SMBUS,
+	PCI_DID_INTEL_ARL_S_SMBUS,
+	PCI_DID_INTEL_ARP_S_SMBUS,
 	PCI_DID_INTEL_RPP_P_SMBUS,
 	PCI_DID_INTEL_RPP_S_SMBUS,
 	PCI_DID_INTEL_APL_SMBUS,
diff --git a/src/soc/intel/common/block/spi/spi.c b/src/soc/intel/common/block/spi/spi.c
index 1dc12d0b45..1ac0de0d7c 100644
--- a/src/soc/intel/common/block/spi/spi.c
+++ b/src/soc/intel/common/block/spi/spi.c
@@ -144,6 +144,10 @@ static const unsigned short pci_device_ids[] = {
 	PCI_DID_INTEL_ARL_GSPI0,
 	PCI_DID_INTEL_ARL_GSPI1,
 	PCI_DID_INTEL_ARL_GSPI2,
+	PCI_DID_INTEL_ARP_S_GSPI0,
+	PCI_DID_INTEL_ARP_S_GSPI1,
+	PCI_DID_INTEL_ARP_S_GSPI2,
+	PCI_DID_INTEL_ARP_S_GSPI3,
 	PCI_DID_INTEL_APL_SPI0,
 	PCI_DID_INTEL_APL_SPI1,
 	PCI_DID_INTEL_APL_SPI2,
diff --git a/src/soc/intel/common/block/sram/sram.c b/src/soc/intel/common/block/sram/sram.c
index 35777d98ba..ba2ed8616f 100644
--- a/src/soc/intel/common/block/sram/sram.c
+++ b/src/soc/intel/common/block/sram/sram.c
@@ -43,7 +43,10 @@ static const unsigned short pci_device_ids[] = {
 	PCI_DID_INTEL_MTL_IOE_M_SRAM,
 	PCI_DID_INTEL_MTL_IOE_P_SRAM,
 	PCI_DID_INTEL_MTL_CRASHLOG_SRAM,
+	PCI_DID_INTEL_ARL_S_CRASHLOG_SRAM,
 	PCI_DID_INTEL_ARL_SOC_SRAM,
+	PCI_DID_INTEL_ARL_SOC_S_SRAM,
+	PCI_DID_INTEL_ARP_S_SRAM,
 	PCI_DID_INTEL_APL_SRAM,
 	PCI_DID_INTEL_GLK_SRAM,
 	PCI_DID_INTEL_CMP_SRAM,
diff --git a/src/soc/intel/common/block/tracehub/tracehub.c b/src/soc/intel/common/block/tracehub/tracehub.c
index 65eadf33b2..dc8c3fd2d6 100644
--- a/src/soc/intel/common/block/tracehub/tracehub.c
+++ b/src/soc/intel/common/block/tracehub/tracehub.c
@@ -47,6 +47,8 @@ static const unsigned short pci_device_ids[] = {
 	PCI_DID_INTEL_PTL_U_H_TRACEHUB,
 	PCI_DID_INTEL_MTL_TRACEHUB,
 	PCI_DID_INTEL_ARL_TRACEHUB,
+	PCI_DID_INTEL_ARL_S_TRACEHUB,
+	PCI_DID_INTEL_ARP_S_TRACEHUB,
 	PCI_DID_INTEL_RPL_TRACEHUB,
 	0
 };
diff --git a/src/soc/intel/common/block/uart/uart.c b/src/soc/intel/common/block/uart/uart.c
index 2c1075993a..8133551a27 100644
--- a/src/soc/intel/common/block/uart/uart.c
+++ b/src/soc/intel/common/block/uart/uart.c
@@ -378,6 +378,10 @@ static const unsigned short pci_device_ids[] = {
 	PCI_DID_INTEL_ARL_UART0,
 	PCI_DID_INTEL_ARL_UART1,
 	PCI_DID_INTEL_ARL_UART2,
+	PCI_DID_INTEL_ARP_S_UART0,
+	PCI_DID_INTEL_ARP_S_UART1,
+	PCI_DID_INTEL_ARP_S_UART2,
+	PCI_DID_INTEL_ARP_S_UART3,
 	PCI_DID_INTEL_APL_UART0,
 	PCI_DID_INTEL_APL_UART1,
 	PCI_DID_INTEL_APL_UART2,
diff --git a/src/soc/intel/common/block/xdci/xdci.c b/src/soc/intel/common/block/xdci/xdci.c
index a5a5158789..ed6a15b363 100644
--- a/src/soc/intel/common/block/xdci/xdci.c
+++ b/src/soc/intel/common/block/xdci/xdci.c
@@ -33,6 +33,7 @@ static const unsigned short pci_device_ids[] = {
 	PCI_DID_INTEL_PTL_U_H_XDCI,
 	PCI_DID_INTEL_MTL_XDCI,
 	PCI_DID_INTEL_ARL_XDCI,
+	PCI_DID_INTEL_ARP_S_XDCI,
 	PCI_DID_INTEL_APL_XDCI,
 	PCI_DID_INTEL_CNL_LP_XDCI,
 	PCI_DID_INTEL_GLK_XDCI,
diff --git a/src/soc/intel/common/block/xhci/xhci.c b/src/soc/intel/common/block/xhci/xhci.c
index 0197f46626..8350c3650b 100644
--- a/src/soc/intel/common/block/xhci/xhci.c
+++ b/src/soc/intel/common/block/xhci/xhci.c
@@ -137,6 +137,7 @@ static const unsigned short pci_device_ids[] = {
 	PCI_DID_INTEL_LNL_XHCI,
 	PCI_DID_INTEL_MTL_XHCI,
 	PCI_DID_INTEL_ARL_XHCI,
+	PCI_DID_INTEL_ARP_S_XHCI,
 	PCI_DID_INTEL_APL_XHCI,
 	PCI_DID_INTEL_CNL_LP_XHCI,
 	PCI_DID_INTEL_GLK_XHCI,
diff --git a/src/soc/intel/meteorlake/Makefile.mk b/src/soc/intel/meteorlake/Makefile.mk
index f3dce87131..ab4e8a7f56 100644
--- a/src/soc/intel/meteorlake/Makefile.mk
+++ b/src/soc/intel/meteorlake/Makefile.mk
@@ -57,6 +57,7 @@ smm-y += smihandler.c
 smm-y += soc_info.c
 smm-y += uart.c
 smm-y += xhci.c
+
 CPPFLAGS_common += -I$(src)/soc/intel/meteorlake
 CPPFLAGS_common += -I$(src)/soc/intel/meteorlake/include
 

From b5db9bcc9d21c9443a3557afc6e18e1870dc21c9 Mon Sep 17 00:00:00 2001
From: Doris Hsu <doris.hsu@intel.corp-partner.google.com>
Date: Mon, 16 Jun 2025 14:45:35 +0800
Subject: [PATCH 1480/3886] soc/intel/alderlake: Enable USB3 HSIO related
 parameters for USB3 GEN2 support

Add parameters and default setting of FSP

BUG=b:407645233
TEST= IOMT verification confirmed, that USB settings can be updated through FSP parameters.

Change-Id: Idbd9ee795b74f43921472ef42a95b2be23af6f5d
Signed-off-by: Doris Hsu <doris.hsu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88105
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
---
 src/soc/intel/alderlake/fsp_params.c      | 25 +++++++++++++++++++++++
 src/soc/intel/alderlake/include/soc/usb.h | 18 ++++++++++++++++
 2 files changed, 43 insertions(+)

diff --git a/src/soc/intel/alderlake/fsp_params.c b/src/soc/intel/alderlake/fsp_params.c
index a5ac6c886c..6382322786 100644
--- a/src/soc/intel/alderlake/fsp_params.c
+++ b/src/soc/intel/alderlake/fsp_params.c
@@ -716,6 +716,31 @@ static void fill_fsps_xhci_params(FSP_S_CONFIG *s_cfg,
 			s_cfg->Usb3HsioTxDownscaleAmp[i] =
 				config->usb3_ports[i].tx_downscale_amp;
 		}
+		if (config->usb3_ports[i].tx_rate2_uniq_tran) {
+			s_cfg->Usb3HsioTxRate2UniqTranEnable[i] = 1;
+			s_cfg->Usb3HsioTxRate2UniqTran[i] =
+				config->usb3_ports[i].tx_rate2_uniq_tran;
+		}
+		if (config->usb3_ports[i].ctrl_adapt_offset_cfg_enable) {
+			s_cfg->PchUsb3HsioCtrlAdaptOffsetCfgEnable[i] = 1;
+			s_cfg->PchUsb3HsioCtrlAdaptOffsetCfg[i] =
+				config->usb3_ports[i].ctrl_adapt_offset_cfg;
+		}
+		if (config->usb3_ports[i].olfps_cfg_pull_up_dwn_res) {
+			s_cfg->PchUsb3HsioOlfpsCfgPullUpDwnResEnable[i] = 1;
+			s_cfg->PchUsb3HsioOlfpsCfgPullUpDwnRes[i] =
+				config->usb3_ports[i].olfps_cfg_pull_up_dwn_res;
+		}
+		if (config->usb3_ports[i].filter_sel_n) {
+			s_cfg->PchUsb3HsioFilterSelNEnable[i] = 1;
+			s_cfg->PchUsb3HsioFilterSelN[i] =
+				config->usb3_ports[i].filter_sel_n;
+		}
+		if (config->usb3_ports[i].filter_sel_p) {
+			s_cfg->PchUsb3HsioFilterSelPEnable[i] = 1;
+			s_cfg->PchUsb3HsioFilterSelP[i] =
+				config->usb3_ports[i].filter_sel_p;
+		}
 	}
 
 	for (i = 0; i < ARRAY_SIZE(config->tcss_ports); i++) {
diff --git a/src/soc/intel/alderlake/include/soc/usb.h b/src/soc/intel/alderlake/include/soc/usb.h
index b84cce7a66..0bf18a788b 100644
--- a/src/soc/intel/alderlake/include/soc/usb.h
+++ b/src/soc/intel/alderlake/include/soc/usb.h
@@ -132,6 +132,12 @@ struct usb3_port_config {
 	uint8_t ocpin;
 	uint8_t tx_de_emp;
 	uint8_t tx_downscale_amp;
+	uint8_t tx_rate2_uniq_tran;
+	uint8_t ctrl_adapt_offset_cfg_enable;
+	uint8_t ctrl_adapt_offset_cfg;
+	uint8_t olfps_cfg_pull_up_dwn_res;
+	uint8_t filter_sel_n;
+	uint8_t filter_sel_p;
 };
 
 #define USB3_PORT_EMPTY { \
@@ -139,6 +145,12 @@ struct usb3_port_config {
 	.ocpin            = OC_SKIP, \
 	.tx_de_emp        = 0x00, \
 	.tx_downscale_amp = 0x00, \
+	.tx_rate2_uniq_tran = 0x00, \
+	.ctrl_adapt_offset_cfg_enable = 0, \
+	.ctrl_adapt_offset_cfg = 0x00, \
+	.olfps_cfg_pull_up_dwn_res = 0x00, \
+	.filter_sel_n = 0x00, \
+	.filter_sel_p = 0x00, \
 }
 
 #define USB3_PORT_DEFAULT(pin) { \
@@ -146,6 +158,12 @@ struct usb3_port_config {
 	.ocpin            = (pin), \
 	.tx_de_emp        = 0x0, \
 	.tx_downscale_amp = 0x00, \
+	.tx_rate2_uniq_tran = 0x00, \
+	.ctrl_adapt_offset_cfg_enable = 0, \
+	.ctrl_adapt_offset_cfg = 0x00, \
+	.olfps_cfg_pull_up_dwn_res = 0x00, \
+	.filter_sel_n = 0x00, \
+	.filter_sel_p = 0x00, \
 }
 
 struct tcss_port_config {

From c3dba4da2b5ea57f57fc0a8cd2699b42a799f7e2 Mon Sep 17 00:00:00 2001
From: Kun-Yi Chen <kunyi.chen@gmail.com>
Date: Wed, 25 Jun 2025 21:19:37 +0800
Subject: [PATCH 1481/3886] mb/lattepanda/mu: Add flashmap definition

Add `board.fmd` and update Kconfig to define FMDFILE for
LattePanda MU.

This file describes the flash layout including
- Flash Descriptor
- ME
- MRC_CACHE
- SMMSTORE
- CBFS

TEST=Built mb/lattepanda/mu with and without board.fmd.

Adjusting FMAP layout via board.fmd changes section sizes and offsets.
This affects the position and size of the COREBOOT (CBFS) region in
the final ROM image.

With board.fmd:
  - FMAP layout explicitly defines COREBOOT size and offset
  - build log shows detailed FMAP section breakdown, including
    CBFS region

Sample log excerpt:
  'COREBOOT' (CBFS, size 3865600, offset 12911616)

Without board.fmd:
  - default FMAP layout is applied
  - COREBOOT region is located differently

with board.fmd

```
Writing new image to build/coreboot.pre
    UPDATE-FIT set FIT pointer to table
    UPDATE-FIT Microcode
    CBFS       coreboot.rom

    FIT table:
    Index  Type                 Addr             Size
         0 Microcode            0xffc504b0      0x00000000

    CBFSLAYOUT  coreboot.rom

This image contains the following sections that can be manipulated
with this tool:

'SI_DESC' (size 4096, offset 0)
'SI_ME' (size 4272128, offset 4096)
'SI_PDR' (size 2015232, offset 4276224)
'RW_MRC_CACHE' (size 65536, offset 12582912)
'SMMSTORE' (size 262144, offset 12648448)
'COREBOOT' (CBFS, size 3865600, offset 12911616)

...

Built lattepanda/mu (MU_8G)
```

without 'board.fmd'

```
Writing new image to build/coreboot.pre
    UPDATE-FIT set FIT pointer to table
    UPDATE-FIT Microcode
    CBFS       coreboot.rom

    FIT table:
    Index  Type                 Addr             Size
         0 Microcode            0xffc502b0      0x00000000

    CBFSLAYOUT  coreboot.rom

This image contains the following sections that can be manipulated
with this tool:

'SI_DESC' (size 4096, offset 0)
'SI_ME' (size 4272128, offset 4096)
'SI_DEVICEEXT2' (size 2015232, offset 4276224)
'RW_MRC_CACHE' (size 65536, offset 12582912)
'SMMSTORE' (size 262144, offset 12648448)
'COREBOOT' (CBFS, size 3866112, offset 12911104)

...

Built lattepanda/mu (MU_8G)
```

Change-Id: If197679c8359f5f75ab125b0c8600926611ac57b
Signed-off-by: Kun-Yi Chen <kunyi.chen@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88192
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/lattepanda/mu/Kconfig   |  3 +++
 src/mainboard/lattepanda/mu/board.fmd | 22 ++++++++++++++++++++++
 2 files changed, 25 insertions(+)
 create mode 100644 src/mainboard/lattepanda/mu/board.fmd

diff --git a/src/mainboard/lattepanda/mu/Kconfig b/src/mainboard/lattepanda/mu/Kconfig
index 7908aade55..d3cf7f6d01 100644
--- a/src/mainboard/lattepanda/mu/Kconfig
+++ b/src/mainboard/lattepanda/mu/Kconfig
@@ -18,6 +18,9 @@ config BOARD_SPECIFIC_OPTIONS
 	select SOC_INTEL_ALDERLAKE_PCH_N
 	select SUPERIO_ITE_IT8613E
 
+config FMDFILE
+	default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/board.fmd"
+
 config MAINBOARD_DIR
 	default "lattepanda/mu"
 
diff --git a/src/mainboard/lattepanda/mu/board.fmd b/src/mainboard/lattepanda/mu/board.fmd
new file mode 100644
index 0000000000..6f2bfba8ba
--- /dev/null
+++ b/src/mainboard/lattepanda/mu/board.fmd
@@ -0,0 +1,22 @@
+# layout for firmware residing at top of 4GB address space
+# +-------------+ <-- 4GB - ROM_SIZE / start of flash
+# | unspecified |
+# +-------------+ <-- 4GB - BIOS_SIZE
+# | FMAP        |
+# +-------------+ <-- 4GB - BIOS_SIZE + FMAP_SIZE
+# | CBFS        |
+# +-------------+ <-- 4GB / end of flash
+
+FLASH 16M {
+	SI_ALL	6M {
+		SI_DESC		4K
+		SI_ME		4172K
+		SI_PDR		1968K
+	}
+	SI_BIOS@12M 4M {
+		RW_MRC_CACHE	64K
+		SMMSTORE 	256K
+		FMAP		1K
+		COREBOOT(CBFS)
+	}
+}

From 3cfa24c1bf103cce7196ac1707a3007738ee5622 Mon Sep 17 00:00:00 2001
From: Kun-Yi Chen <kunyi.chen@gmail.com>
Date: Wed, 25 Jun 2025 21:51:43 +0800
Subject: [PATCH 1482/3886] mb/lattepanda/mu: Enable PMC drivers

Enable Intel PMC and ACPI IPC interface in Kconfig to fix
power-off failure on shutdown.

Previously, the system failed to fully power off after shutdown,
leaving some power rails active and preventing restart via the
power button. A full power cycle was required to reboot.

This change ensures proper system power-off behavior.

TEST=Tested shutdown behavior with PMC and ACPI IPC interface
enabled in Kconfig. System now powers off cleanly and can restart
via power button without unplugging power

Verify OS: Ubuntu 24.04

Change-Id: I1f93410bcd717630319adabec40534b5b7467582
Signed-off-by: Kun-Yi Chen <kunyi.chen@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88193
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
---
 src/mainboard/lattepanda/mu/Kconfig | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/src/mainboard/lattepanda/mu/Kconfig b/src/mainboard/lattepanda/mu/Kconfig
index d3cf7f6d01..aa98fcf2cf 100644
--- a/src/mainboard/lattepanda/mu/Kconfig
+++ b/src/mainboard/lattepanda/mu/Kconfig
@@ -5,6 +5,7 @@ if BOARD_LATTEPANDA_MU
 config BOARD_SPECIFIC_OPTIONS
 	def_bool y
 	select BOARD_ROMSIZE_KB_16384
+	select DRIVERS_INTEL_PMC
 	select DRIVERS_SPI_ACPI
 	select DRIVERS_UART_8250IO
 	select DRIVERS_USB_ACPI
@@ -13,8 +14,10 @@ config BOARD_SPECIFIC_OPTIONS
 	select HAVE_ACPI_TABLES
 	select HAVE_SPD_IN_CBFS
 	select INTEL_GMA_HAVE_VBT
+	select PMC_IPC_ACPI_INTERFACE
 	select REALTEK_8168_RESET
 	select RT8168_GEN_ACPI_POWER_RESOURCE
+	select SOC_INTEL_ALDERLAKE
 	select SOC_INTEL_ALDERLAKE_PCH_N
 	select SUPERIO_ITE_IT8613E
 

From 2ec9a9f17de283f19ff26a62a51bf035d4518e20 Mon Sep 17 00:00:00 2001
From: Kun-Yi Chen <kunyi.chen@gmail.com>
Date: Wed, 25 Jun 2025 22:10:02 +0800
Subject: [PATCH 1483/3886] mb/lattepanda/mu: Update eDP/HDMI in devicetree

Updated DDI port configuration to properly enable eDP (Port A)
and HDMI (Port B) with HPD and DDC settings on LattePanda MU.

This change ensures both internal and external displays are
detected and initialized correctly during boot.

Change-Id: I84e5bc4b8a26f58b9cb26a4018eef640ac245e7f
Signed-off-by: Kun-Yi Chen <kunyi.chen@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88194
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/lattepanda/mu/devicetree.cb | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/src/mainboard/lattepanda/mu/devicetree.cb b/src/mainboard/lattepanda/mu/devicetree.cb
index ba55f1412a..563d8fbd2e 100644
--- a/src/mainboard/lattepanda/mu/devicetree.cb
+++ b/src/mainboard/lattepanda/mu/devicetree.cb
@@ -8,7 +8,9 @@ chip soc/intel/alderlake
 	# Enable EDP in PortA
 	register "ddi_portA_config" = "1"
 	# Enable HDMI in Port B
+	register "ddi_portB_config" = "1"
 	register "ddi_ports_config" = "{
+		[DDI_PORT_A] = DDI_ENABLE_HPD,
 		[DDI_PORT_B] = DDI_ENABLE_HPD | DDI_ENABLE_DDC,
 	}"
 

From 26d6da453394977c186060a6dd9ea4463279122a Mon Sep 17 00:00:00 2001
From: Kun-Yi Chen <kunyi.chen@gmail.com>
Date: Thu, 26 Jun 2025 00:09:37 +0800
Subject: [PATCH 1484/3886] mb/lattepanda/mu: Correct UART1 pinmux for native
 mode

Correct UART1 TX/RX pad configuration in early_gpio.c from NF2
to NF1. This enables proper UART1 signaling on GPP_D17 and GPP_D18
when operating in native mode.

This change is based on guidance from Intel Doc. No. 648094.

TEST=Patched and booted board. Confirmed UART1 communication
works via serial adapter. Loopback test passed.

Change-Id: Ib1f5ee17e6f3d8a845d024e6b8593606b0430b6f
Signed-off-by: Kun-Yi Chen <kunyi.chen@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88195
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/lattepanda/mu/early_gpio.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/mainboard/lattepanda/mu/early_gpio.c b/src/mainboard/lattepanda/mu/early_gpio.c
index f44e67dcfb..e08e7bbd55 100644
--- a/src/mainboard/lattepanda/mu/early_gpio.c
+++ b/src/mainboard/lattepanda/mu/early_gpio.c
@@ -10,9 +10,9 @@ static const struct pad_config early_uart_gpio_table[] = {
 	/* UART0 TX */
 	PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2),
 	/* UART1 RX */
-	PAD_CFG_NF(GPP_D17, NONE, DEEP, NF2),
+	PAD_CFG_NF(GPP_D17, NONE, DEEP, NF1),
 	/* UART1 TX */
-	PAD_CFG_NF(GPP_D18, NONE, DEEP, NF2),
+	PAD_CFG_NF(GPP_D18, NONE, DEEP, NF1),
 	/* UART2 RX */
 	PAD_CFG_NF(GPP_F1, NONE, DEEP, NF2),
 	/* UART2 TX */

From cb86b9a08901fe488f85a33f84f8aeabde857479 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Micha=C5=82=20Kope=C4=87?= <michal.kopec@3mdeb.com>
Date: Sun, 30 Mar 2025 10:38:04 +0200
Subject: [PATCH 1485/3886] mb/lenovo/m900_tiny: Put options in CFR cbtable
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Change-Id: I259f88a3ceb9aee54016bb88a7d4de2b58dffa83
Signed-off-by: Michał Kopeć <michal.kopec@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87048
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
---
 src/mainboard/lenovo/m900_tiny/Kconfig     |  2 +
 src/mainboard/lenovo/m900_tiny/Makefile.mk |  1 +
 src/mainboard/lenovo/m900_tiny/cfr.c       | 79 ++++++++++++++++++++++
 src/mainboard/lenovo/m900_tiny/ramstage.c  | 35 ++++++++--
 4 files changed, 113 insertions(+), 4 deletions(-)
 create mode 100644 src/mainboard/lenovo/m900_tiny/cfr.c

diff --git a/src/mainboard/lenovo/m900_tiny/Kconfig b/src/mainboard/lenovo/m900_tiny/Kconfig
index 8ad36e0014..a99afa1b8b 100644
--- a/src/mainboard/lenovo/m900_tiny/Kconfig
+++ b/src/mainboard/lenovo/m900_tiny/Kconfig
@@ -6,6 +6,8 @@ if BOARD_LENOVO_THINKCENTRE_M900_TINY
 config BOARD_SPECIFIC_OPTIONS
 	def_bool y
 	select BOARD_ROMSIZE_KB_16384
+	select DRIVERS_EFI_VARIABLE_STORE
+	select DRIVERS_OPTION_CFR
 	select DRIVERS_UART_8250IO
 	select HAVE_ACPI_RESUME
 	select HAVE_ACPI_TABLES
diff --git a/src/mainboard/lenovo/m900_tiny/Makefile.mk b/src/mainboard/lenovo/m900_tiny/Makefile.mk
index 44db0910ed..3b5a2a27a5 100644
--- a/src/mainboard/lenovo/m900_tiny/Makefile.mk
+++ b/src/mainboard/lenovo/m900_tiny/Makefile.mk
@@ -7,6 +7,7 @@ bootblock-y += gpio_early.c
 
 romstage-y += romstage.c
 
+ramstage-$(CONFIG_DRIVERS_OPTION_CFR) += cfr.c
 ramstage-y += gpio.c
 ramstage-y += hda_verb.c
 ramstage-y += ramstage.c
diff --git a/src/mainboard/lenovo/m900_tiny/cfr.c b/src/mainboard/lenovo/m900_tiny/cfr.c
new file mode 100644
index 0000000000..0bd2f8f56e
--- /dev/null
+++ b/src/mainboard/lenovo/m900_tiny/cfr.c
@@ -0,0 +1,79 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <boot/coreboot_tables.h>
+#include <drivers/option/cfr_frontend.h>
+
+struct sm_object wifi_slot_enable = SM_DECLARE_BOOL({
+	.flags		= CFR_OPTFLAG_RUNTIME,
+	.opt_name	= "wifi_slot_enable",
+	.ui_name	= "Enable Wi-Fi card slot",
+	.ui_helptext	= "Enable or disable detection of devices in the Wi-Fi card slot",
+	.default_value	= true,
+});
+
+struct sm_object ssd_slot_enable = SM_DECLARE_BOOL({
+	.flags		= CFR_OPTFLAG_RUNTIME,
+	.opt_name	= "ssd_slot_enable",
+	.ui_name	= "Enable SSD slot",
+	.ui_helptext	= "Enable or disable detection of devices in the SSD slot",
+	.default_value	= true,
+});
+
+struct sm_object hdd_slot_enable = SM_DECLARE_BOOL({
+	.flags		= CFR_OPTFLAG_RUNTIME,
+	.opt_name	= "hdd_slot_enable",
+	.ui_name	= "Enable 2.5 inch disk slot",
+	.ui_helptext	= "Enable or disable detection of devices in the 2.5 inch disk slot",
+	.default_value	= true,
+});
+
+static struct sm_obj_form devices = {
+	.ui_name	= "Devices",
+	.obj_list	= (const struct sm_object *[]) {
+		&wifi_slot_enable,
+		&ssd_slot_enable,
+		&hdd_slot_enable,
+		NULL
+	},
+};
+
+struct sm_object ps2_enable = SM_DECLARE_BOOL({
+	.flags		= CFR_OPTFLAG_RUNTIME,
+	.opt_name	= "ps2_enable",
+	.ui_name	= "PS/2 controller",
+	.ui_helptext	= "Enable or disable the PS/2 controller",
+	.default_value	= true,
+});
+
+struct sm_object power_on_after_fail = SM_DECLARE_ENUM({
+	.flags		= CFR_OPTFLAG_RUNTIME,
+	.opt_name	= "power_on_after_fail",
+	.ui_name	= "Power state after fail",
+	.ui_helptext	= "State of the platform after external power is restored",
+	.default_value	= CONFIG_MAINBOARD_POWER_FAILURE_STATE,
+	.values		= (const struct sm_enum_value[]) {
+				{ "Off",	0 },
+				{ "On",		1 },
+				{ "Previous",	2 },
+				SM_ENUM_VALUE_END },
+});
+
+static struct sm_obj_form superio = {
+	.ui_name	= "Super I/O",
+	.obj_list	= (const struct sm_object *[]) {
+		&ps2_enable,
+		&power_on_after_fail,
+		NULL
+	},
+};
+
+static struct sm_obj_form *sm_root[] = {
+	&devices,
+	&superio,
+	NULL
+};
+
+void mb_cfr_setup_menu(struct lb_cfr *cfr_root)
+{
+	cfr_write_setup_menu(cfr_root, sm_root);
+}
diff --git a/src/mainboard/lenovo/m900_tiny/ramstage.c b/src/mainboard/lenovo/m900_tiny/ramstage.c
index 6e66f3a7cc..7eadabe2a2 100644
--- a/src/mainboard/lenovo/m900_tiny/ramstage.c
+++ b/src/mainboard/lenovo/m900_tiny/ramstage.c
@@ -2,10 +2,14 @@
 
 #include <console/console.h>
 #include <device/device.h>
+#include <device/pci_def.h>
 #include <drivers/intel/gma/int15.h>
 #include <gpio.h>
 #include <mainboard/gpio.h>
+#include <option.h>
 #include <soc/ramstage.h>
+#include <static.h>
+#include <superio/nuvoton/nct6687d/nct6687d.h>
 
 static void print_board_id(void)
 {
@@ -32,19 +36,42 @@ static void print_board_id(void)
 	}
 
 	printk(BIOS_INFO, "Serial header %spopulated\n", !gpio_get(GPP_A22) ? "" : "un");
-
 	printk(BIOS_INFO, "PS/2 header %spopulated\n", !gpio_get(GPP_D14) ? "" : "un");
-
 	printk(BIOS_INFO, "USB header %spopulated\n", !gpio_get(GPP_C19) ? "" : "un");
-
 	printk(BIOS_INFO, "DisplayPort header %spopulated\n", !gpio_get(GPP_B15) ? "" : "un");
-
 	printk(BIOS_INFO, "PCIe / SATA header %spopulated\n", !gpio_get(GPP_B21) ? "" : "un");
 }
 
+static void devtree_update(void)
+{
+	config_t *cfg = config_of_soc();
+	struct device *wifi_dev = DEV_PTR(pcie_rp7);
+	struct device *ssd_dev = DEV_PTR(pcie_rp17);
+	struct device *ps2_dev = dev_find_slot_pnp(0x2e, NCT6687D_KBC);
+
+	if (get_uint_option("wifi_slot_enable", 1) == 0) {
+		cfg->usb2_ports[8].enable = 0;
+		wifi_dev->enabled = 0;
+	}
+
+	if (get_uint_option("ssd_slot_enable", 1) == 0) {
+		cfg->SataPortsEnable[4] = 0;
+		ssd_dev->enabled = 0;
+	}
+
+	if (get_uint_option("hdd_slot_enable", 1) == 0) {
+		cfg->SataPortsEnable[0] = 0;
+		cfg->SataPortsEnable[1] = 0;
+	}
+
+	if (get_uint_option("ps2_enable", 1) == 0)
+		ps2_dev->enabled = 0;
+}
+
 static void mainboard_enable(struct device *dev)
 {
 	mainboard_configure_gpios();
+	devtree_update();
 	print_board_id();
 }
 

From dabc200abb8293a3301603ce88e8e35b33f45685 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Micha=C5=82=20Kope=C4=87?= <michal.kopec@3mdeb.com>
Date: Thu, 24 Oct 2024 19:42:45 +0200
Subject: [PATCH 1486/3886] mb/lenovo/m900_tiny: enable power LED blink in S3
 and S4
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

The power LED may be disabled by GPP_D1. The pin is PWM capable, so
configure it in PWM mode with a frequency of 0.5Hz, duty cycle of 50%
when entering sleep.

The result is that the power LED toggles on/off every second.

TEST=Boot to Windows 10, enter S3, and wake. The power LED will blink
when system is asleep and glow continuously when awake.

Change-Id: I121e0ef3e47aec1cacdace3f2af47a3fdacf69cf
Signed-off-by: Michał Kopeć <michal.kopec@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84860
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
---
 src/mainboard/lenovo/m900_tiny/Makefile.mk  |  2 ++
 src/mainboard/lenovo/m900_tiny/gpio.c       |  2 +-
 src/mainboard/lenovo/m900_tiny/ramstage.c   |  8 ++++++++
 src/mainboard/lenovo/m900_tiny/smihandler.c | 22 +++++++++++++++++++++
 4 files changed, 33 insertions(+), 1 deletion(-)
 create mode 100644 src/mainboard/lenovo/m900_tiny/smihandler.c

diff --git a/src/mainboard/lenovo/m900_tiny/Makefile.mk b/src/mainboard/lenovo/m900_tiny/Makefile.mk
index 3b5a2a27a5..d016e93f49 100644
--- a/src/mainboard/lenovo/m900_tiny/Makefile.mk
+++ b/src/mainboard/lenovo/m900_tiny/Makefile.mk
@@ -12,3 +12,5 @@ ramstage-y += gpio.c
 ramstage-y += hda_verb.c
 ramstage-y += ramstage.c
 ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads
+
+smm-y += smihandler.c
diff --git a/src/mainboard/lenovo/m900_tiny/gpio.c b/src/mainboard/lenovo/m900_tiny/gpio.c
index 4c4bac4b8e..101f47b673 100644
--- a/src/mainboard/lenovo/m900_tiny/gpio.c
+++ b/src/mainboard/lenovo/m900_tiny/gpio.c
@@ -91,7 +91,7 @@ static const struct pad_config gpio_table[] = {
 	/* ------- GPIO Group GPP_D ------- */
 
 	PAD_NC(GPP_D0, NONE),
-	PAD_NC(GPP_D1, NONE),
+	PAD_CFG_NF(GPP_D1, NONE, DEEP, NF4), /* PW_LED# (blink mode)*/
 	PAD_NC(GPP_D2, NONE),
 	PAD_NC(GPP_D3, NONE),
 	PAD_NC(GPP_D4, NONE),
diff --git a/src/mainboard/lenovo/m900_tiny/ramstage.c b/src/mainboard/lenovo/m900_tiny/ramstage.c
index 7eadabe2a2..92ef6b8e67 100644
--- a/src/mainboard/lenovo/m900_tiny/ramstage.c
+++ b/src/mainboard/lenovo/m900_tiny/ramstage.c
@@ -5,8 +5,10 @@
 #include <device/pci_def.h>
 #include <drivers/intel/gma/int15.h>
 #include <gpio.h>
+#include <intelblocks/pcr.h>
 #include <mainboard/gpio.h>
 #include <option.h>
+#include <soc/pcr_ids.h>
 #include <soc/ramstage.h>
 #include <static.h>
 #include <superio/nuvoton/nct6687d/nct6687d.h>
@@ -73,6 +75,12 @@ static void mainboard_enable(struct device *dev)
 	mainboard_configure_gpios();
 	devtree_update();
 	print_board_id();
+	/* Configure GPIO community 1 PWM frequency to 0.5Hz, 0% duty cycle */
+	pcr_write32(PID_GPIOCOM1, 0x204, (1 << 14));
+	/* Set the software update flag */
+	pcr_or32(PID_GPIOCOM1, 0x204, (1 << 30));
+	/* Enable PWM */
+	pcr_or32(PID_GPIOCOM1, 0x204, (1 << 31));
 }
 
 struct chip_operations mainboard_ops = {
diff --git a/src/mainboard/lenovo/m900_tiny/smihandler.c b/src/mainboard/lenovo/m900_tiny/smihandler.c
new file mode 100644
index 0000000000..6ae0b36a25
--- /dev/null
+++ b/src/mainboard/lenovo/m900_tiny/smihandler.c
@@ -0,0 +1,22 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <acpi/acpi.h>
+#include <cpu/x86/smm.h>
+#include <intelblocks/pcr.h>
+#include <soc/pcr_ids.h>
+
+void mainboard_smi_sleep(u8 slp_typ)
+{
+	/* Enable blinking power LED when entering S3 or S4 */
+	switch (slp_typ) {
+	case ACPI_S3:
+	case ACPI_S4:
+		/* Configure GPIO community 1 PWM duty cycle to 50% */
+		pcr_rmw32(PID_GPIOCOM1, 0x204, 0xffffff00, 0x7f);
+		/* Set the software update flag */
+		pcr_or32(PID_GPIOCOM1, 0x204, (1 << 30));
+		break;
+	default:
+		break;
+	}
+}

From a9e97268fed2f29830159b984492351a05cef6b6 Mon Sep 17 00:00:00 2001
From: Zhixing Ma <zhixing.ma@intel.com>
Date: Wed, 2 Jul 2025 18:18:12 -0700
Subject: [PATCH 1487/3886] crossgcc: Fix acpica base url version
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Due to a recent acpica version upgrade, the acpica tool is now
failing to download due to an incorrect url. This commit aims to
fix the issue by updating the iasl base url to match the upgraded
version.

Change-Id: I7eddff2d17587f5d90295928800c10068c8cf281
Signed-off-by: Zhixing Ma <zhixing.ma@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88278
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
---
 util/crossgcc/buildgcc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc
index 2f513d8333..1984054fa9 100755
--- a/util/crossgcc/buildgcc
+++ b/util/crossgcc/buildgcc
@@ -86,7 +86,7 @@ MPC_BASE_URL="https://ftpmirror.gnu.org/mpc"
 GCC_BASE_URL="https://ftpmirror.gnu.org/gcc/gcc-${GCC_VERSION}"
 LIBSTDCXX_BASE_URL="${GCC_BASE_URL}"
 BINUTILS_BASE_URL="https://ftpmirror.gnu.org/binutils"
-IASL_BASE_URL="https://github.com/acpica/acpica/releases/download/R2024_12_12"
+IASL_BASE_URL="https://downloadmirror.intel.com/852044"
 # CLANG toolchain archive locations
 LLVM_BASE_URL="https://github.com/llvm/llvm-project/releases/download/llvmorg-${CLANG_VERSION}"
 CLANG_BASE_URL="https://github.com/llvm/llvm-project/releases/download/llvmorg-${CLANG_VERSION}"

From d8455dfbf60a0e387c244c71a892c6fadfa34ff0 Mon Sep 17 00:00:00 2001
From: Luca Lai <luca.lai@lcfc.corp-partner.google.com>
Date: Thu, 26 Jun 2025 10:36:56 +0800
Subject: [PATCH 1488/3886] mb/trulo/var/pujjolo: Change wifi SAR id fw config
 bits

Because of the internal misunderstanding, so now correct the right fw
config of wifi SAR id number from 18 to 21 to 17 to 20.

BUG=b:395763555
BRANCH=none
TEST=Build and boot to OS and check coreboot log to check the wifi SAR table could work fine.

Change-Id: Ib006996fb8887a36feb5dfe71baef58fa74c35f7
Signed-off-by: Luca Lai <luca.lai@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88200
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/google/brya/variants/pujjolo/overridetree.cb | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/mainboard/google/brya/variants/pujjolo/overridetree.cb b/src/mainboard/google/brya/variants/pujjolo/overridetree.cb
index 9fbff83aa2..de40681426 100644
--- a/src/mainboard/google/brya/variants/pujjolo/overridetree.cb
+++ b/src/mainboard/google/brya/variants/pujjolo/overridetree.cb
@@ -4,7 +4,7 @@ fw_config
 		option LTE_PRESENT		1
 		option 5G_PRESENT		2
 	end
-	field WIFI_SAR_ID 18 21
+	field WIFI_SAR_ID 17 20
 		option WIFI_SAR_TABLE_AX211	0
 		option WIFI_SAR_TABLE_AX203	1
 	end

From 167c771bc5fe8761a1991a0ec6a97eb15b7da4fa Mon Sep 17 00:00:00 2001
From: Ian Feng <ian_feng@compal.corp-partner.google.com>
Date: Tue, 10 Jun 2025 13:09:45 +0800
Subject: [PATCH 1489/3886] mb/google/fatcat/var/francka: Enable audio codec
 ALC722/ALC1320

Enable Realtek ALC722 and ALC1320 soundwire codec for francka.
Refer to the main board schematic(1224A) and
audio board schematic(1106A).

BUG=b:420516709
TEST=Build and boot and check the ssdt dump PCI0.HDAS.SNDW.
Scope (\_SB.PCI0.HDAS.SNDW)
    Device (SW00)
        Name (_ADR, 0x000030025D072201)  // _ADR: Address
        Name (_DDN, "Headset Codec")  // _DDN: DOS Device Name
Scope (\_SB.PCI0.HDAS.SNDW)
    Device (SW20)
        Name (_ADR, 0x000230025D132001)  // _ADR: Address
        Name (_DDN, "Speaker Amp")  // _DDN: DOS Device Name
Scope (\_SB.PCI0.HDAS.SNDW)
    Device (SW30)
        Name (_ADR, 0x000330025D132001)  // _ADR: Address
        Name (_DDN, "Speaker Amp")  // _DDN: DOS Device Name

Change-Id: I542d94fd792272d3b7d75538671ba2f59c331a1e
Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88022
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Pranava Y N <pranavayn@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mac Chiang <mac.chiang@intel.com>
---
 src/mainboard/google/fatcat/Kconfig           |  1 +
 .../fatcat/variants/francka/fw_config.c       | 22 ++++++++++++++
 .../fatcat/variants/francka/overridetree.cb   | 30 +++++++++++++++++++
 3 files changed, 53 insertions(+)

diff --git a/src/mainboard/google/fatcat/Kconfig b/src/mainboard/google/fatcat/Kconfig
index 7a7748dc03..1ba556523d 100644
--- a/src/mainboard/google/fatcat/Kconfig
+++ b/src/mainboard/google/fatcat/Kconfig
@@ -107,6 +107,7 @@ config BOARD_GOOGLE_FELINO4ES
 
 config BOARD_GOOGLE_FRANCKA
 	select BOARD_GOOGLE_BASEBOARD_FATCAT
+	select DRIVERS_SOUNDWIRE_ALC1320
 	select HAVE_SLP_S0_GATE
 
 config BOARD_GOOGLE_KINMEN
diff --git a/src/mainboard/google/fatcat/variants/francka/fw_config.c b/src/mainboard/google/fatcat/variants/francka/fw_config.c
index 2ec7c4481b..fe8ce59a10 100644
--- a/src/mainboard/google/fatcat/variants/francka/fw_config.c
+++ b/src/mainboard/google/fatcat/variants/francka/fw_config.c
@@ -37,6 +37,25 @@ static const struct pad_config sndw_alc721_enable_pads[] = {
 	PAD_CFG_NF(GPP_S07, NONE, DEEP, NF5),
 };
 
+static const struct pad_config sndw_alc722_alc1320_enable_pads[] = {
+	/* GPP_S00:     SNDW_3_SCL */
+	PAD_CFG_NF(GPP_S00, NONE, DEEP, NF1),
+	/* GPP_S01:     SNDW_3_SDA */
+	PAD_CFG_NF(GPP_S01, NONE, DEEP, NF1),
+	/* GPP_S02:     SNDW0_CLK */
+	PAD_CFG_NF(GPP_S02, NONE, DEEP, NF3),
+	/* GPP_S03:     SNDW0_DATA0 */
+	PAD_CFG_NF(GPP_S03, NONE, DEEP, NF3),
+	/* GPP_S04:     SNDW_2_SCL */
+	PAD_CFG_NF(GPP_S04, NONE, DEEP, NF2),
+	/* GPP_S05:     SNDW_2_SDA */
+	PAD_CFG_NF(GPP_S05, NONE, DEEP, NF2),
+	/* GPP_S06:     SOC_DMIC_CLK1 */
+	PAD_CFG_NF(GPP_S06, NONE, DEEP, NF5),
+	/* GPP_S07:     SOC_DMIC_DATA1 */
+	PAD_CFG_NF(GPP_S07, NONE, DEEP, NF5),
+};
+
 static const struct pad_config enable_dmic_0_pads[] = {
 	/* GPP_S02:     SOC_DMIC_CLK0 */
 	PAD_CFG_NF(GPP_S02, NONE, DEEP, NF5),
@@ -131,6 +150,9 @@ void fw_config_gpio_padbased_override(struct pad_config *padbased_table)
 	} else if (fw_config_probe(FW_CONFIG(AUDIO, AUDIO_ALC721_SNDW))) {
 		printk(BIOS_INFO, "Configure GPIOs for Soundwire ALC721 mode.\n");
 		GPIO_PADBASED_OVERRIDE(padbased_table, sndw_alc721_enable_pads);
+	} else if (fw_config_probe(FW_CONFIG(AUDIO, AUDIO_ALC722_ALC1320_SNDW))) {
+		printk(BIOS_INFO, "Configure GPIOs for Soundwire ALC722 & ALC1320 mode.\n");
+		GPIO_PADBASED_OVERRIDE(padbased_table, sndw_alc722_alc1320_enable_pads);
 	}
 
 	if (fw_config_probe(FW_CONFIG(WWAN, WWAN_PRESENT))) {
diff --git a/src/mainboard/google/fatcat/variants/francka/overridetree.cb b/src/mainboard/google/fatcat/variants/francka/overridetree.cb
index f61c8dddaf..d93d6a1738 100644
--- a/src/mainboard/google/fatcat/variants/francka/overridetree.cb
+++ b/src/mainboard/google/fatcat/variants/francka/overridetree.cb
@@ -296,6 +296,36 @@ chip soc/intel/pantherlake
 							probe AUDIO AUDIO_ALC721_SNDW
 						end
 					end
+					chip drivers/soundwire/alc711
+						register "desc" = ""Headset Codec""
+						register "alc711_address.version" = "SOUNDWIRE_VERSION_1_2"
+						register "alc711_address.class" = "MIPI_CLASS_SDCA"
+						register "alc711_address.part_id" = "MIPI_DEV_ID_REALTEK_ALC722"
+						# SoundWire Link 0 ID 0
+						device generic 0.0 on
+							probe AUDIO AUDIO_ALC722_ALC1320_SNDW
+						end
+					end
+					chip drivers/soundwire/alc1320
+						register "desc" = ""Speaker Amp""
+						register "alc1320_address.version" = "SOUNDWIRE_VERSION_1_2"
+						register "alc1320_address.class" = "MIPI_CLASS_SDCA"
+						register "alc1320_address.part_id" = "MIPI_DEV_ID_REALTEK_ALC1320"
+						 # SoundWire Link 2 ID 0
+						device generic 2.0 on
+							probe AUDIO AUDIO_ALC722_ALC1320_SNDW
+						end
+					end
+					chip drivers/soundwire/alc1320
+						register "desc" = ""Speaker Amp""
+						register "alc1320_address.version" = "SOUNDWIRE_VERSION_1_2"
+						register "alc1320_address.class" = "MIPI_CLASS_SDCA"
+						register "alc1320_address.part_id" = "MIPI_DEV_ID_REALTEK_ALC1320"
+						 # SoundWire Link 3 ID 0
+						device generic 3.0 on
+							probe AUDIO AUDIO_ALC722_ALC1320_SNDW
+						end
+					end
 				end
 			end
 		end

From 9f73b040748d003bd34eb212fdae0597459a8183 Mon Sep 17 00:00:00 2001
From: Appukuttan V K <appukuttan.vk@intel.com>
Date: Mon, 30 Jun 2025 16:47:40 +0530
Subject: [PATCH 1490/3886] soc/intel/pantherlake: Add new MCH ID for Wildcat
 Lake
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

This commit introduces a new MCH device ID to support the Wildcat
Lake SoC. It updates the PCI device ID list and platform reporting
logic to accommodate this new ID.

Key changes:
 - Add PCI_DID_INTEL_WCL_ID_3 (0xfd02) to the list of recognized
   device IDs.
 - Update system agent operations to include the new MCH ID.
 - Enhance platform reporting to recognize the new MCH ID.

References:
- Wildcat Lake Processor EDS Volume 1 (#842271)
- Wildcat Lake External Design Specification (EDS) Volume 2 (#829345)

BUG=b:394208231
TEST=Build Ocelot and verify it compiles without any error.

Change-Id: I464fb147f0d3df214ca64b1321eebab08505d7bc
Signed-off-by: Appukuttan V K <appukuttan.vk@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88248
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Pranava Y N <pranavayn@google.com>
---
 src/include/device/pci_ids.h                          | 1 +
 src/soc/intel/common/block/systemagent/systemagent.c  | 1 +
 src/soc/intel/pantherlake/bootblock/report_platform.c | 1 +
 3 files changed, 3 insertions(+)

diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h
index 908ac17d50..a63df081a8 100644
--- a/src/include/device/pci_ids.h
+++ b/src/include/device/pci_ids.h
@@ -4686,6 +4686,7 @@
 #define PCI_DID_INTEL_SNR_ID			0x09a2
 #define PCI_DID_INTEL_WCL_ID_1			0xfd00
 #define PCI_DID_INTEL_WCL_ID_2			0xfd01
+#define PCI_DID_INTEL_WCL_ID_3			0xfd02
 
 /* Intel SMBUS device Ids */
 #define PCI_DID_INTEL_LPT_H_SMBUS			0x8c22
diff --git a/src/soc/intel/common/block/systemagent/systemagent.c b/src/soc/intel/common/block/systemagent/systemagent.c
index f98606a18d..30acf30f49 100644
--- a/src/soc/intel/common/block/systemagent/systemagent.c
+++ b/src/soc/intel/common/block/systemagent/systemagent.c
@@ -427,6 +427,7 @@ struct device_operations systemagent_ops = {
 static const unsigned short systemagent_ids[] = {
 	PCI_DID_INTEL_WCL_ID_1,
 	PCI_DID_INTEL_WCL_ID_2,
+	PCI_DID_INTEL_WCL_ID_3,
 	PCI_DID_INTEL_PTL_U_ID_1,
 	PCI_DID_INTEL_PTL_U_ID_2,
 	PCI_DID_INTEL_PTL_U_ID_3,
diff --git a/src/soc/intel/pantherlake/bootblock/report_platform.c b/src/soc/intel/pantherlake/bootblock/report_platform.c
index 099075417e..516264de02 100644
--- a/src/soc/intel/pantherlake/bootblock/report_platform.c
+++ b/src/soc/intel/pantherlake/bootblock/report_platform.c
@@ -42,6 +42,7 @@ static struct {
 	{ PCI_DID_INTEL_PTL_H_ID_8, "Pantherlake H" },
 	{ PCI_DID_INTEL_WCL_ID_1, "Wildcatlake" },
 	{ PCI_DID_INTEL_WCL_ID_2, "Wildcatlake" },
+	{ PCI_DID_INTEL_WCL_ID_3, "Wildcatlake" },
 };
 
 static struct {

From a4156f99ffb886bbb9e5f8395182104e201fb072 Mon Sep 17 00:00:00 2001
From: Appukuttan V K <appukuttan.vk@intel.com>
Date: Tue, 1 Jul 2025 22:54:03 +0530
Subject: [PATCH 1491/3886] soc/intel/ptl: Add Wildcat Lake CPU ID to platform
 reporting
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

This commit updates the platform reporting logic to recognize the
Wildcat Lake SoC CPU ID.

Key changes:
 - Add CPUID_WILDCATLAKE_A0 to the list of recognized CPU IDs in
   the platform reporting module.

References:
- Wildcat Lake Processor EDS Volume 1 (#842271)
- Wildcat Lake External Design Specification (EDS) Volume 2 (#829345)

BUG=b:394208231
TEST=Build Ocelot and verify it compiles without any error.

Change-Id: I8c9e81446a12ee0a6e18f1ba3f36166652a05f5e
Signed-off-by: Appukuttan V K <appukuttan.vk@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88271
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Pranava Y N <pranavayn@google.com>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
---
 src/soc/intel/pantherlake/bootblock/report_platform.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/src/soc/intel/pantherlake/bootblock/report_platform.c b/src/soc/intel/pantherlake/bootblock/report_platform.c
index 516264de02..d6cae4afad 100644
--- a/src/soc/intel/pantherlake/bootblock/report_platform.c
+++ b/src/soc/intel/pantherlake/bootblock/report_platform.c
@@ -23,6 +23,7 @@ static struct {
 	{ CPUID_PANTHERLAKE_A0, "Pantherlake A0" },
 	{ CPUID_PANTHERLAKE_B0_1, "Pantherlake B0" },
 	{ CPUID_PANTHERLAKE_B0_2, "Pantherlake B0" },
+	{ CPUID_WILDCATLAKE_A0, "Wildcatlake A0" },
 };
 
 static struct {

From 2739c4b77396651282bcf6b4b101d013ec910a17 Mon Sep 17 00:00:00 2001
From: Martin Roth <gaumless@gmail.com>
Date: Sat, 28 Jun 2025 10:14:16 -0600
Subject: [PATCH 1492/3886] SBOM: Change makefile to get versions from build.h

Builds using SBOM were failing in the release because we don't have a
git tree to get information from. We can't assume that the coreboot
source will always be in a git tree, so it needs to be updated. This
updates build.h to contain all the data that the SBOM wants and changes
the SBOM makefile to get its information from build.h which can generate
the required data in a number of different ways.

Change-Id: I59fba349d95cb0dcff7a31d335f4acb4f11c89c7
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88236
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
---
 src/sbom/Makefile.mk          | 6 +++---
 util/genbuild_h/genbuild_h.sh | 4 ++++
 util/release/build-release    | 2 +-
 3 files changed, 8 insertions(+), 4 deletions(-)

diff --git a/src/sbom/Makefile.mk b/src/sbom/Makefile.mk
index 4e3adc27d1..26f48dc3e8 100644
--- a/src/sbom/Makefile.mk
+++ b/src/sbom/Makefile.mk
@@ -110,10 +110,10 @@ $(build-dir)/compiler-%.json: $(src-dir)/compiler-%.json | $(build-dir)/goswid
 		$(build-dir)/goswid add-payload-file -o $@ -i $@ --name $$(basename $$tool) --version $$version; \
 	done
 
-$(build-dir)/coreboot.json: $(src-dir)/coreboot.json .git/HEAD | $(build-dir)/goswid
+$(build-dir)/coreboot.json: $(src-dir)/coreboot.json $(obj)/build.h | $(build-dir)/goswid
 	cp $< $@
-	git_tree_hash=$$(git log -n 1 --format=%T);\
-	git_comm_hash=$$(git log -n 1 --format=%H);\
+	git_tree_hash=$$(grep 'COREBOOT_ORIGIN_TREE_REVISION' $(obj)/build.h | sed 's/.*"\(.*\)".*/\1/');\
+	git_comm_hash=$$(grep 'COREBOOT_ORIGIN_GIT_REVISION' $(obj)/build.h | sed 's/.*"\(.*\)".*/\1/');\
 	sed -i -e "s/<colloquial_version>/$$git_tree_hash/" -e "s/<software_version>/$$git_comm_hash/" $@;\
 	$(build-dir)/goswid add-license -o $@ -i $@ $(coreboot-licenses)
 
diff --git a/util/genbuild_h/genbuild_h.sh b/util/genbuild_h/genbuild_h.sh
index b381ab2776..e83d4e177f 100755
--- a/util/genbuild_h/genbuild_h.sh
+++ b/util/genbuild_h/genbuild_h.sh
@@ -33,6 +33,7 @@ if [ "${BUILD_TIMELESS}" = "1" ]; then
 	DATE=0
 elif [ "$(git rev-parse --is-inside-work-tree 2>/dev/null)" = "true" ]; then
 	GITREV="$(get_git_head_data %h)"
+	TREE_REV="$(get_git_head_data %t)"
 	TIMESOURCE=git
 	DATE="$(get_git_head_data %ct)"
 	VERSION="$(git describe)"
@@ -45,6 +46,8 @@ else
 	if [ -f "${COREBOOT_VERSION_FILE}" ]; then
 		MAJOR_VER="$(sed -n 's/^0*\([0-9]*\)\.0*\([0-9]*\).*/\1/p' "${COREBOOT_VERSION_FILE}")"
 		MINOR_VER="$(sed -n 's/^0*\([0-9]*\)\.0*\([0-9]*\).*/\2/p' "${COREBOOT_VERSION_FILE}")"
+		GITREV="Based_on_$(sed -n 's/^[^-]*-\([^-]*\)-.*/\1/p' "${COREBOOT_VERSION_FILE}")"
+		TREE_REV="Based_on_$(sed -n 's/^[^-]*-[^-]*-\(.*\)/\1/p' "${COREBOOT_VERSION_FILE}")"
 	fi
 fi
 
@@ -78,6 +81,7 @@ printf "#define COREBOOT_VERSION %s\n" "\"${KERNELVERSION}\""
 printf "/* timesource: %s */\n" "${TIMESOURCE}"
 printf "#define COREBOOT_VERSION_TIMESTAMP %s\n" "${DATE}"
 printf "#define COREBOOT_ORIGIN_GIT_REVISION \"%s\"\n" "${GITREV}"
+printf "#define COREBOOT_ORIGIN_TREE_REVISION \"%s\"\n" "${TREE_REV:-0}"
 
 printf "#define COREBOOT_EXTRA_VERSION \"%s\"\n" "${COREBOOT_EXTRA_VERSION}"
 printf "#define COREBOOT_MAJOR_VERSION %s\n" "${MAJOR_VER:-0}"
diff --git a/util/release/build-release b/util/release/build-release
index c8e939b4bb..7c4aeb597f 100755
--- a/util/release/build-release
+++ b/util/release/build-release
@@ -89,7 +89,7 @@ fi
 
 	git submodule update --init --checkout
 
-	printf "%s-%s\n" "$VERSION_NAME"  "$(git log --pretty=%h -1)" > .coreboot-version
+	printf "%s-%s-%s\n" "$VERSION_NAME"  "$(git log --pretty=%h -1)" "$(git log --pretty=%t -1)" > .coreboot-version
 	printf "%s\n" "$(git log --pretty=format:%ci -1)" > "${TIME_FILE}"
 )
 tstamp=$(cat "${TIME_FILE}" | sed 's/ +0000//')

From d5854e4139950575a23355a04f8523ca4787fbf0 Mon Sep 17 00:00:00 2001
From: Angel Pons <th3fanbus@gmail.com>
Date: Sun, 25 May 2025 16:51:16 +0200
Subject: [PATCH 1493/3886] Haswell NRI: Implement COMP offset optimisation

This algorithm minimises the per-channel, per-lane digital COMP offsets
by adjusting the global COMP offset accordingly. The purpose of this is
not fully known, but it is likely to prevent saturation of per-channel,
per-lane registers during subsequent training steps, which NRI does not
implement yet. Some of the COMP offset functions are generic since they
are also used in said training steps.

Tested on Asrock B85M Pro4, still boots to Arch Linux.

Change-Id: Idb03c6c5ed85a522ff1b55905f522211d1472bd9
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87833
Reviewed-by: Benjamin Doron <benjamin.doron00@gmail.com>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 .../haswell/native_raminit/change_margin.c    | 310 ++++++++++++++++++
 .../haswell/native_raminit/configure_mc.c     |  17 +-
 .../haswell/native_raminit/io_comp_control.c  | 166 ++++++++++
 .../haswell/native_raminit/raminit_main.c     |   1 +
 .../haswell/native_raminit/raminit_native.h   |  51 ++-
 .../haswell/native_raminit/reg_structs.h      |  63 +++-
 .../intel/haswell/registers/mchbar.h          |   4 +-
 7 files changed, 597 insertions(+), 15 deletions(-)

diff --git a/src/northbridge/intel/haswell/native_raminit/change_margin.c b/src/northbridge/intel/haswell/native_raminit/change_margin.c
index 299c44a6b0..517ddc23a6 100644
--- a/src/northbridge/intel/haswell/native_raminit/change_margin.c
+++ b/src/northbridge/intel/haswell/native_raminit/change_margin.c
@@ -288,3 +288,313 @@ void change_1d_margin_multicast(
 {
 	change_margin(ctrl, param, value0, true, 0, rank, 0, update_ctrl, regfile);
 }
+
+uint32_t update_comp_global_offset(
+	struct sysinfo *ctrl,
+	const enum global_comp_offset param,
+	const int32_t offset,
+	const uint8_t update_ctrl)
+{
+	union ddr_comp_ctl_0_reg ddr_comp_ctl_0 = ctrl->comp_ctl_0;
+	union ddr_comp_ctl_1_reg ddr_comp_ctl_1 = ctrl->comp_ctl_1;
+	switch (param) {
+	case RdOdt:
+		/* Disable fixed ODT offset before changing this param */
+		ddr_comp_ctl_0.fixed_odt_offset = 0;
+		ddr_comp_ctl_0.dq_odt_vref = offset;
+		break;
+	case WrDS:
+		ddr_comp_ctl_0.dq_drv_vref = offset;
+		break;
+	case WrDSCmd:
+		ddr_comp_ctl_0.cmd_drv_vref = offset;
+		break;
+	case WrDSCtl:
+		ddr_comp_ctl_0.ctl_drv_vref = offset;
+		break;
+	case WrDSClk:
+		ddr_comp_ctl_0.clk_drv_vref = offset;
+		break;
+	case SCompDq:
+		ddr_comp_ctl_1.dq_scomp = offset;
+		break;
+	case SCompCmd:
+		ddr_comp_ctl_1.cmd_scomp = offset;
+		break;
+	case SCompCtl:
+		ddr_comp_ctl_1.ctl_scomp = offset;
+		break;
+	case SCompClk:
+		ddr_comp_ctl_1.clk_scomp = offset;
+		break;
+	case DisOdtStatic:
+		ctrl->comp_ctl_0.disable_odt_static = !!offset;
+		for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
+			union ddr_data_control_0_reg data_control_0 = {
+				.raw = ctrl->dq_control_0[channel],
+			};
+			data_control_0.disable_odt_static = !!offset;
+			mchbar_write32(DDR_DATA_ch_CONTROL_0(channel), data_control_0.raw);
+			if (update_ctrl) {
+				ctrl->dq_control_0[channel] = data_control_0.raw;
+			}
+		}
+		break;
+	default:
+		die("%s: Invalid global comp offset %d\n", __func__, param);
+	}
+	mchbar_write32(DDR_COMP_CTL_0, ddr_comp_ctl_0.raw);
+	mchbar_write32(DDR_COMP_CTL_1, ddr_comp_ctl_1.raw);
+	if (update_ctrl) {
+		ctrl->comp_ctl_0 = ddr_comp_ctl_0;
+		ctrl->comp_ctl_1 = ddr_comp_ctl_1;
+	}
+	force_rcomp_and_wait_us(8);
+	const union ddr_data_comp_1_reg ddr_data_comp_1 = {
+		.raw = mchbar_read32(DDR_DATA_COMP_1),
+	};
+	const uint8_t rcomp_odt_up = ddr_data_comp_1.rcomp_odt_up;
+	/* Check if we are close to saturation and try changing the static legs */
+	if (param == RdOdt && (rcomp_odt_up < 16 || rcomp_odt_up > 48)) {
+		const bool dis_odt_static = rcomp_odt_up < 16;
+
+		/* Host always needs to be up-to-date with the static leg state */
+		ddr_comp_ctl_0.disable_odt_static = dis_odt_static;
+		for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
+			if (!does_ch_exist(ctrl, channel))
+				continue;
+
+			union ddr_data_control_0_reg data_control_0 = {
+				.raw = ctrl->dq_control_0[channel],
+			};
+			data_control_0.disable_odt_static = dis_odt_static;
+			mchbar_write32(DDR_DATA_ch_CONTROL_0(channel),
+					data_control_0.raw);
+			ctrl->dq_control_0[channel] = data_control_0.raw;
+		}
+		mchbar_write32(DDR_COMP_CTL_0, ddr_comp_ctl_0.raw);
+		ctrl->comp_ctl_0.disable_odt_static = dis_odt_static;
+		force_rcomp_and_wait_us(8);
+	}
+	switch (param) {
+	case RdOdt:
+	case DisOdtStatic: {
+		/* Re-enable fixed ODT offset after changing this param */
+		const uint32_t delta = ddr_data_comp_1.rcomp_odt_down - ddr_data_comp_1.rcomp_odt_up;
+		ddr_comp_ctl_0.odt_up_down_off  = delta;
+		ddr_comp_ctl_0.fixed_odt_offset = 1;
+		mchbar_write32(DDR_COMP_CTL_0, ddr_comp_ctl_0.raw);
+		if (update_ctrl)
+			ctrl->comp_ctl_0 = ddr_comp_ctl_0;
+
+		return ddr_data_comp_1.rcomp_odt_up;
+	}
+	case WrDS:
+	case SCompDq: {
+		const union ddr_data_comp_0_reg data_comp_0 = {
+			.raw = mchbar_read32(DDR_DATA_COMP_0),
+		};
+		return param == WrDS ? data_comp_0.rcomp_drv_up : data_comp_0.slew_rate_comp;
+	}
+	case WrDSCmd:
+	case SCompCmd: {
+		const union ddr_comp_cmd_comp_reg cmd_comp = {
+			.raw = mchbar_read32(DDR_COMP_CMD_COMP),
+		};
+		return param == WrDSCmd ? cmd_comp.rcomp_drv_up : cmd_comp.slew_rate_comp;
+	}
+	case WrDSCtl:
+	case SCompCtl: {
+		const union ddr_comp_ctl_comp_reg ctl_comp = {
+			.raw = mchbar_read32(DDR_COMP_CTL_COMP),
+		};
+		return param == WrDSCtl ? ctl_comp.rcomp_drv_up : ctl_comp.slew_rate_comp;
+	}
+	case WrDSClk:
+	case SCompClk: {
+		const union ddr_comp_clk_comp_reg clk_comp = {
+			.raw = mchbar_read32(DDR_COMP_CLK_COMP),
+		};
+		return param == WrDSClk ? clk_comp.rcomp_drv_up : clk_comp.slew_rate_comp;
+	}
+	default:
+		die("%s: Invalid global comp offset %d\n", __func__, param);
+		return 0;
+	}
+}
+
+static bool is_cpu_comp(const enum opt_param optparam)
+{
+	switch (optparam) {
+	case OptWrDS:
+	case OptRdOdt:
+	case OptSComp:
+	case OptTComp:
+		return true;
+	default:
+		return false;
+	}
+}
+
+static const uint8_t odt_map[6] = {0, 120, 60, 40, 30, 20};
+
+void update_opt_param_offset(
+	struct sysinfo *ctrl,
+	const uint8_t channel,
+	const uint8_t ranks_in,
+	const uint8_t byte,
+	const enum opt_param optparam,
+	const int16_t off_in,
+	const bool update_ctrl)
+{
+	const uint8_t rankmask = ranks_in & ctrl->rankmap[channel];
+	union ddr_data_offset_comp_reg data_offset_comp = ctrl->data_offset_comp[channel][byte];
+	if (optparam == OptDefault) {
+		mchbar_write32(DDR_DATA_OFFSET_COMP_ch_b(channel, byte), data_offset_comp.raw);
+		for (uint8_t rank = 0; rank < NUM_SLOTRANKS; rank++) {
+			if (!rank_in_mask(rank, rankmask)) {
+				continue;
+			}
+			update_rxt(ctrl, channel, rank, byte, RXT_RESTORE, 0);
+			update_txt(ctrl, channel, rank, byte, TXT_RESTORE, 0);
+		}
+		mchbar_write32(DQ_CONTROL_1(channel, byte), ctrl->dq_control_1[channel][byte]);
+		return;
+	}
+	if (is_cpu_comp(optparam)) {
+		int16_t off;
+		if (optparam == OptWrDS) {
+			off = clamp_s16(-32, off_in, 31);
+		} else {
+			off = clamp_s16(-16, off_in, 15);
+		}
+		if (optparam == OptWrDS) {
+			data_offset_comp.drv_up   = off;
+			data_offset_comp.drv_down = off;
+		} else if (optparam == OptRdOdt) {
+			data_offset_comp.odt_up   = off;
+			data_offset_comp.odt_down = off;
+		} else if (optparam == OptTComp) {
+			data_offset_comp.t_clk_out = off;
+		} else if (optparam == OptSComp) {
+			data_offset_comp.slew_rate = off;
+		}
+		mchbar_write32(DDR_DATA_OFFSET_COMP_ch_b(channel, byte), data_offset_comp.raw);
+		if (update_ctrl) {
+			ctrl->data_offset_comp[channel][byte] = data_offset_comp;
+		}
+		union ddr_scram_misc_control_reg misc_control = ctrl->misc_control_0;
+		misc_control.force_comp_update = 1;
+		mchbar_write32(DDR_SCRAM_MISC_CONTROL, misc_control.raw);
+	}
+	if (optparam == OptTxEq) {
+		for (uint8_t rank = 0; rank < NUM_SLOTRANKS; rank++) {
+			if (!rank_in_mask(rank, rankmask)) {
+				continue;
+			}
+			/*
+			 * TxEq[5:4] = Emphasize   = [3, 6, 9, 12] legs
+			 * TxEq[3:0] = Deemphasize = [0 .. 11, 4 * Rsvd] legs
+			 */
+			/* Use 12 emphasis legs (not trained) */
+			const uint8_t off_code = clamp_s16(0, off_in, 11) | TXEQFULLDRV;
+			update_txt(ctrl, channel, rank, byte, TXT_TX_EQ, off_code);
+			if (update_ctrl) {
+				ctrl->tx_eq[channel][rank][byte] = off_code;
+			}
+		}
+	}
+	if (optparam == OptRxEq) {
+		for (uint8_t rank = 0; rank < NUM_SLOTRANKS; rank++) {
+			if (!rank_in_mask(rank, rankmask)) {
+				continue;
+			}
+			/*
+			 * RxEQ[4:0] CR Decoding (pF/kOhm)
+			 *            [2:0]
+			 *  [4:3]     0        1        2        3        4        5-7
+			 *     0      0.5/.02  0.5/1.0  0.5/.50  0.5/.25  0.5/.12  rsvd
+			 *     1      1.0/.02  1.0/1.0  1.0/.50  1.0/.25  1.0/.12  rsvd
+			 *     2      1.5/.02  1.5/1.0  1.5/.50  1.5/.25  1.5/.12  rsvd
+			 *     3      2.0/.02  2.0/1.0  2.0/.50  2.0/.25  2.0/.12  rsvd
+			 * Sweep = 0-19        [4:3] = (Sweep / 5)  [2:0] = (Sweep % 5)
+			 */
+			const int16_t off = clamp_s16(0, off_in, 19);
+			const uint8_t value = ((off / 5) << 3) + (off % 5);
+			update_rxt(ctrl, channel, rank, byte, RXT_RX_EQ, value);
+			if (update_ctrl) {
+				ctrl->rx_eq[channel][rank][byte] = value;
+			}
+		}
+	}
+	if (optparam == OptRxBias) {
+		/*
+		 * Mapping: 0: 0.44   1: 0.66   2: 0.88   3: 1.00
+		 *          4: 1.33   5: 1.66   6: 2.00   7: 2.33
+		 */
+		union ddr_data_control_1_reg data_control_1 = {
+			.raw = ctrl->dq_control_1[channel][byte],
+		};
+		data_control_1.rx_bias_ctl = clamp_s16(0, off_in, 7);
+		mchbar_write32(DQ_CONTROL_1(channel, byte), data_control_1.raw);
+		if (update_ctrl) {
+			ctrl->dq_control_1[channel][byte] = data_control_1.raw;
+		}
+	}
+	if (optparam == OptDimmRon) {
+		if (ctrl->lpddr) {
+			die("%s: LPDDR3 support missing\n", __func__);
+		}
+		/* DIMM Ron: 240/6, 240/7 Ohms */
+		const uint16_t ron = !!off_in << 1;
+		for (uint8_t rank = 0; rank < NUM_SLOTRANKS; rank++) {
+			if (!rank_in_mask(rank, rankmask)) {
+				continue;
+			}
+			const uint16_t mr1reg = (ctrl->mr1[channel][rank] & ~BIT(1)) | ron;
+			reut_issue_mrs(ctrl, channel, BIT(rank), 1, mr1reg);
+			if (update_ctrl) {
+				ctrl->mr1[channel][rank] = mr1reg;
+			}
+		}
+	}
+	if (optparam == OptDimmOdt || optparam == OptDimmOdtWr) {
+		if (ctrl->lpddr) {
+			die("%s: LPDDR3 support missing\n", __func__);
+		}
+		const uint16_t rtt_wr_mrs_encoding[] = { 0, 2, 1 };
+		const uint16_t rtt_wr_mask = BIT(10) | BIT(9);
+		for (uint8_t rank = 0; rank < NUM_SLOTRANKS; rank++) {
+			if (!rank_in_mask(rank, rankmask)) {
+				continue;
+			}
+			uint8_t index = off_in;
+			if (optparam == OptDimmOdt) {
+				index >>= 4;
+			}
+			index = MIN(index, 2);
+			const uint16_t rtt_wr = rtt_wr_mrs_encoding[index] << 9;
+			uint16_t mr2reg = (ctrl->mr2[channel][rank] & ~rtt_wr_mask) | rtt_wr;
+			reut_issue_mrs(ctrl, channel, BIT(rank), 2, mr2reg);
+			if (update_ctrl) {
+				ctrl->mr2[channel][rank] = mr2reg;
+			}
+			if (optparam == OptDimmOdtWr) {
+				continue;
+			}
+			index = off_in;
+			index &= 0xf;
+			if (index >= ARRAY_SIZE(odt_map)) {
+				printk(BIOS_ERR, "C%uR%u RTT NOM idx %u is too large\n",
+					channel, rank, index);
+				index = ARRAY_SIZE(odt_map) - 1;
+			}
+			const uint16_t rtt_nom = encode_ddr3_rttnom(odt_map[index]);
+			uint16_t mr1reg = (ctrl->mr1[channel][rank] & ~RTTNOM_MASK) | rtt_nom;
+			reut_issue_mrs(ctrl, channel, BIT(rank), 1, mr1reg);
+			if (update_ctrl) {
+				ctrl->mr1[channel][rank] = mr1reg;
+			}
+		}
+	}
+}
diff --git a/src/northbridge/intel/haswell/native_raminit/configure_mc.c b/src/northbridge/intel/haswell/native_raminit/configure_mc.c
index 8ff81727ec..a86a11ca4e 100644
--- a/src/northbridge/intel/haswell/native_raminit/configure_mc.c
+++ b/src/northbridge/intel/haswell/native_raminit/configure_mc.c
@@ -205,7 +205,7 @@ static void program_ddr_data(struct sysinfo *ctrl, const bool dis_odt_static, co
 			const uint8_t stg = latency * byte_stagger[byte] / ctrl->lanes;
 			data_control_2.rx_stagger_ctl = stg & 0x1f;
 			mchbar_write32(DQ_CONTROL_2(channel, byte), data_control_2.raw);
-			ctrl->data_offset_comp[channel][byte] = 0;
+			ctrl->data_offset_comp[channel][byte].raw = 0;
 			ctrl->dq_control_1[channel][byte] = data_control_1.raw;
 			ctrl->dq_control_2[channel][byte] = data_control_2.raw;
 		}
@@ -548,14 +548,7 @@ static void override_comp(uint32_t value, uint32_t width, uint32_t shift, uint32
 
 static void program_ls_comp(struct sysinfo *ctrl)
 {
-	/* Disable periodic COMP */
-	const union pcu_comp_reg m_comp = {
-		.comp_disable  = 1,
-		.comp_interval = COMP_INT,
-		.comp_force    = 1,
-	};
-	mchbar_write32(M_COMP, m_comp.raw);
-	udelay(10);
+	force_rcomp_and_wait_us(10);
 
 	/* Override level shifter compensation */
 	const uint32_t ls_comp = 2;
@@ -563,7 +556,7 @@ static void program_ls_comp(struct sysinfo *ctrl)
 	override_comp(ls_comp, 3, 24, DDR_CMD_COMP);
 	override_comp(ls_comp, 3, 24, DDR_CKE_CTL_COMP);
 	override_comp(ls_comp, 3, 23, DDR_CLK_COMP);
-	override_comp(ls_comp, 3, 28, DDR_COMP_DATA_COMP_1);
+	override_comp(ls_comp, 3, 28, DDR_DATA_COMP_1);
 	override_comp(ls_comp, 3, 24, DDR_COMP_CMD_COMP);
 	override_comp(ls_comp, 4, 24, DDR_COMP_CTL_COMP);
 	override_comp(ls_comp, 4, 23, DDR_COMP_CLK_COMP);
@@ -575,8 +568,8 @@ static void program_ls_comp(struct sysinfo *ctrl)
 	mchbar_write32(DDR_SCRAM_MISC_CONTROL, ddr_scram_misc_ctrl.raw);
 
 	/* Use a fixed offset between ODT Up/Dn */
-	const union ddr_comp_data_comp_1_reg data_comp_1 = {
-		.raw = mchbar_read32(DDR_COMP_DATA_COMP_1),
+	const union ddr_data_comp_1_reg data_comp_1 = {
+		.raw = mchbar_read32(DDR_DATA_COMP_1),
 	};
 	const uint32_t odt_offset = data_comp_1.rcomp_odt_down - data_comp_1.rcomp_odt_up;
 	ctrl->comp_ctl_0.odt_up_down_off  = odt_offset;
diff --git a/src/northbridge/intel/haswell/native_raminit/io_comp_control.c b/src/northbridge/intel/haswell/native_raminit/io_comp_control.c
index 8a55fd81b2..77d2c73f66 100644
--- a/src/northbridge/intel/haswell/native_raminit/io_comp_control.c
+++ b/src/northbridge/intel/haswell/native_raminit/io_comp_control.c
@@ -2,6 +2,7 @@
 
 #include <commonlib/bsd/clamp.h>
 #include <console/console.h>
+#include <delay.h>
 #include <northbridge/intel/haswell/haswell.h>
 #include <timer.h>
 #include <types.h>
@@ -39,3 +40,168 @@ enum raminit_status wait_for_first_rcomp(void)
 	printk(BIOS_ERR, "Timed out waiting for RCOMP to complete\n");
 	return RAMINIT_STATUS_POLL_TIMEOUT;
 }
+
+void force_rcomp_and_wait_us(unsigned int usecs)
+{
+	/* Disable periodic COMP */
+	const union pcu_comp_reg m_comp = {
+		.comp_disable  = 1,
+		.comp_interval = COMP_INT,
+		.comp_force    = 1,
+	};
+	mchbar_write32(M_COMP, m_comp.raw);
+	if (usecs) {
+		udelay(usecs);
+	}
+}
+
+static int8_t get_comp(union ddr_data_offset_comp_reg data_offset_comp, enum opt_param optparam)
+{
+	switch (optparam) {
+		case OptWrDS:	return data_offset_comp.drv_up;
+		case OptRdOdt:	return data_offset_comp.odt_up;
+		case OptSComp:	return data_offset_comp.slew_rate;
+		default:	return 0;
+	}
+}
+
+static void optimise_comp_offset(struct sysinfo *ctrl, const enum opt_param optparam)
+{
+	const uint8_t reserved_codes = 3;
+	const bool update_ctrl = true;
+
+	uint8_t param;
+	uint8_t current_comp;
+	int32_t min_comp_vref;
+	int32_t max_comp_vref;
+	int32_t curr_comp_vref;
+	switch (optparam) {
+	case OptWrDS: {
+		const union ddr_data_comp_0_reg data_comp_0 = {
+			.raw = mchbar_read32(DDR_DATA_COMP_0),
+		};
+		current_comp = data_comp_0.rcomp_drv_up;
+		curr_comp_vref = ctrl->comp_ctl_0.dq_drv_vref;
+		min_comp_vref = -8;
+		max_comp_vref = 7;
+		param = WrDS;
+		break;
+	}
+	case OptRdOdt: {
+		const union ddr_data_comp_1_reg data_comp_1 = {
+			.raw = mchbar_read32(DDR_DATA_COMP_1),
+		};
+		current_comp = data_comp_1.rcomp_odt_up;
+		curr_comp_vref = ctrl->comp_ctl_0.dq_odt_vref;
+		min_comp_vref = -16;
+		max_comp_vref = 15;
+		param = RdOdt;
+		break;
+	}
+	case OptSComp: {
+		const union ddr_data_comp_0_reg data_comp_0 = {
+			.raw = mchbar_read32(DDR_DATA_COMP_0),
+		};
+		current_comp = data_comp_0.slew_rate_comp;
+		/* Mask out the phase/cycle bit */
+		curr_comp_vref = ctrl->comp_ctl_1.dq_scomp & ~BIT(4);
+		min_comp_vref = 4;
+		max_comp_vref = 15;
+		param = SCompDq;
+		break;
+	}
+	default:
+		die("%s: Invalid optparam: %d\n", __func__, optparam);
+	}
+
+	uint8_t comp_codes[NUM_CHANNELS][NUM_LANES] = {0};
+	int16_t avg_offset = 0;
+	uint8_t num_ch = 0;
+	for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
+		if (!does_ch_exist(ctrl, channel)) {
+			continue;
+		}
+
+		num_ch++;
+		for (uint8_t byte = 0; byte < ctrl->lanes; byte++) {
+			int8_t off = get_comp(ctrl->data_offset_comp[channel][byte], optparam);
+			avg_offset += off;
+			comp_codes[channel][byte] = current_comp + off;
+		}
+	}
+	if (!num_ch) {
+		return;
+	}
+
+	avg_offset = DIV_ROUND_CLOSEST(avg_offset, num_ch * ctrl->lanes);
+	if (!avg_offset) {
+		return;
+	}
+
+	const uint8_t start_delta = ABS(avg_offset);
+	uint8_t best_vref_off = curr_comp_vref;
+	uint8_t min_delta = start_delta;
+	uint8_t new_comp = current_comp;
+	uint8_t dq_scomp_pc = ctrl->comp_ctl_1.dq_scomp & BIT(4); /* phase/cycle bit */
+	int8_t sign = sign_of(avg_offset);
+	if (optparam == OptSComp) {
+		sign = -sign;
+	}
+	bool done = false;
+	for (uint8_t offset = 1; !done; offset++) {
+		int8_t new_comp_vref = curr_comp_vref + sign * offset;
+		if (new_comp_vref < min_comp_vref || new_comp_vref > max_comp_vref) {
+			done = true;
+		}
+		if (reserved_codes > new_comp || new_comp > 63 - reserved_codes) {
+			done = true;
+		}
+		if (optparam == OptSComp) {
+			if (new_comp_vref >= 16) {
+				dq_scomp_pc = 0;
+			}
+			new_comp_vref = dq_scomp_pc | new_comp_vref;
+		}
+		if (!done) {
+			new_comp = update_comp_global_offset(ctrl, param, new_comp_vref, 0);
+			const uint8_t curr_delta = ABS(current_comp + avg_offset - new_comp);
+			if (curr_delta >= start_delta) {
+				done = true;
+			} else if (curr_delta < min_delta) {
+				best_vref_off = new_comp_vref;
+				min_delta = curr_delta;
+				if (min_delta == 0) {
+					done = true;
+				}
+			}
+		}
+	}
+	new_comp = update_comp_global_offset(ctrl, param, best_vref_off, update_ctrl);
+	if (best_vref_off == curr_comp_vref) {
+		return;
+	}
+
+	for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
+		if (!does_ch_exist(ctrl, channel)) {
+			continue;
+		}
+		for (uint8_t byte = 0; byte < ctrl->lanes; byte++) {
+			update_opt_param_offset(
+				ctrl,
+				channel,
+				0,
+				byte,
+				optparam,
+				comp_codes[channel][byte] - new_comp,
+				update_ctrl);
+		}
+	}
+}
+
+enum raminit_status optimise_comp(struct sysinfo *ctrl)
+{
+	optimise_comp_offset(ctrl, OptWrDS);
+	optimise_comp_offset(ctrl, OptRdOdt);
+	optimise_comp_offset(ctrl, OptSComp);
+	return RAMINIT_STATUS_SUCCESS;
+}
diff --git a/src/northbridge/intel/haswell/native_raminit/raminit_main.c b/src/northbridge/intel/haswell/native_raminit/raminit_main.c
index 0e72ae66aa..84db33ebdf 100644
--- a/src/northbridge/intel/haswell/native_raminit/raminit_main.c
+++ b/src/northbridge/intel/haswell/native_raminit/raminit_main.c
@@ -129,6 +129,7 @@ static const struct task_entry cold_boot[] = {
 	{ train_receive_enable,                                   true, "RCVET",      },
 	{ train_read_mpr,                                         true, "RDMPRT",     },
 	{ train_jedec_write_leveling,                             true, "JWRL",       },
+	{ optimise_comp,                                          true, "OPTCOMP",    },
 	{ post_training,                                          true, "POSTTRAIN",  },
 	{ activate_mc,                                            true, "ACTIVATE",   },
 	{ save_training_values,                                   true, "SAVE_TRAIN", },
diff --git a/src/northbridge/intel/haswell/native_raminit/raminit_native.h b/src/northbridge/intel/haswell/native_raminit/raminit_native.h
index 097b6411b3..b9e84a11df 100644
--- a/src/northbridge/intel/haswell/native_raminit/raminit_native.h
+++ b/src/northbridge/intel/haswell/native_raminit/raminit_native.h
@@ -70,6 +70,33 @@ enum margin_parameter {
 	RdV,
 };
 
+enum opt_param {
+	OptWrDS = 0,
+	OptRdOdt,
+	OptSComp,
+	OptTComp,
+	OptTxEq,
+	OptRxEq,
+	OptRxBias,
+	OptDimmOdt,
+	OptDimmOdtWr,
+	OptDimmRon,
+	OptDefault,
+};
+
+enum global_comp_offset {
+	RdOdt,
+	WrDS,
+	WrDSCmd,
+	WrDSCtl,
+	WrDSClk,
+	SCompDq,
+	SCompCmd,
+	SCompCtl,
+	SCompClk,
+	DisOdtStatic,
+};
+
 /* ZQ calibration types */
 enum {
 	ZQ_INIT,	/* DDR3: ZQCL with tZQinit, LPDDR3: ZQ Init  with tZQinit  */
@@ -312,7 +339,7 @@ struct sysinfo {
 	uint32_t rt_io_comp[NUM_CHANNELS];
 
 	uint32_t data_offset_train[NUM_CHANNELS][NUM_LANES];
-	uint32_t data_offset_comp[NUM_CHANNELS][NUM_LANES];
+	union ddr_data_offset_comp_reg data_offset_comp[NUM_CHANNELS][NUM_LANES];
 
 	uint32_t dq_control_0[NUM_CHANNELS];
 	uint32_t dq_control_1[NUM_CHANNELS][NUM_LANES];
@@ -354,6 +381,11 @@ struct sysinfo {
 	uint8_t dq_pat_lc;
 };
 
+static inline int8_t sign_of(const int32_t val)
+{
+	return val < 0 ? -1 : 1;
+}
+
 static inline bool is_hsw_ult(void)
 {
 	return CONFIG(INTEL_LYNXPOINT_LP);
@@ -456,6 +488,7 @@ enum raminit_status train_sense_amp_offset(struct sysinfo *ctrl);
 enum raminit_status train_receive_enable(struct sysinfo *ctrl);
 enum raminit_status train_read_mpr(struct sysinfo *ctrl);
 enum raminit_status train_jedec_write_leveling(struct sysinfo *ctrl);
+enum raminit_status optimise_comp(struct sysinfo *ctrl);
 enum raminit_status save_training_values(struct sysinfo *ctrl);
 enum raminit_status restore_training_values(struct sysinfo *ctrl);
 enum raminit_status save_non_training(struct sysinfo *ctrl);
@@ -482,6 +515,7 @@ uint32_t get_tZQCS(uint32_t mem_clock_mhz, bool lpddr);
 
 enum raminit_status io_reset(void);
 enum raminit_status wait_for_first_rcomp(void);
+void force_rcomp_and_wait_us(unsigned int usecs);
 
 uint16_t encode_ddr3_rttnom(uint32_t rttnom);
 void ddr3_program_mr1(struct sysinfo *ctrl, uint8_t wl_mode, uint8_t q_off);
@@ -588,6 +622,21 @@ void change_1d_margin_multicast(
 	const bool update_ctrl,
 	const enum regfile_mode regfile);
 
+uint32_t update_comp_global_offset(
+	struct sysinfo *ctrl,
+	const enum global_comp_offset param,
+	const int32_t offset,
+	const uint8_t update_ctrl);
+
+void update_opt_param_offset(
+	struct sysinfo *ctrl,
+	const uint8_t channel,
+	const uint8_t ranks,
+	const uint8_t byte,
+	const enum opt_param optparam,
+	const int16_t off_in,
+	const bool update_ctrl);
+
 uint8_t get_rx_bias(const struct sysinfo *ctrl);
 
 uint8_t get_tCWL(uint32_t mem_clock_mhz);
diff --git a/src/northbridge/intel/haswell/native_raminit/reg_structs.h b/src/northbridge/intel/haswell/native_raminit/reg_structs.h
index b9043e8883..b0a121fa1a 100644
--- a/src/northbridge/intel/haswell/native_raminit/reg_structs.h
+++ b/src/northbridge/intel/haswell/native_raminit/reg_structs.h
@@ -25,6 +25,18 @@ union ddr_data_tx_train_rank_reg {
 	uint32_t raw;
 };
 
+union ddr_data_offset_comp_reg {
+	struct __packed {
+		int32_t drv_up    : 6; // Bits  5:0
+		int32_t drv_down  : 6; // Bits 11:6
+		int32_t odt_up    : 5; // Bits 16:12
+		int32_t odt_down  : 5; // Bits 21:17
+		int32_t t_clk_out : 5; // Bits 26:22
+		int32_t slew_rate : 5; // Bits 31:27
+	};
+	uint32_t raw;
+};
+
 union ddr_data_offset_train_reg {
 	struct __packed {
 		int32_t rcven  : 6; // Bits  5:0
@@ -114,7 +126,20 @@ union ddr_data_control_2_reg {
 	uint32_t raw;
 };
 
-union ddr_comp_data_comp_1_reg {
+union ddr_data_comp_0_reg {
+	struct __packed {
+		uint32_t rcomp_drv_up   : 6; // Bits  5:0
+		uint32_t                : 3; // Bits  8:6
+		uint32_t rcomp_drv_down : 6; // Bits 14:9
+		uint32_t vt_comp        : 5; // Bits 19:15
+		uint32_t tco_comp       : 6; // Bits 25:20
+		uint32_t slew_rate_comp : 5; // Bits 30:26
+		uint32_t                : 1; // Bits 31:31
+	};
+	uint32_t raw;
+};
+
+union ddr_data_comp_1_reg {
 	struct __packed {
 		uint32_t rcomp_odt_up   : 6; // Bits  5:0
 		uint32_t                : 3; // Bits  8:6
@@ -128,6 +153,42 @@ union ddr_comp_data_comp_1_reg {
 	uint32_t raw;
 };
 
+union ddr_comp_cmd_comp_reg {
+	struct __packed {
+		uint32_t slew_rate_comp : 6; // Bits  5:0
+		uint32_t tco_comp       : 6; // Bits 11:6
+		uint32_t rcomp_drv_up   : 6; // Bits 17:12
+		uint32_t rcomp_drv_down : 6; // Bits 23:18
+		uint32_t ls_comp        : 3; // Bits 26:24
+		uint32_t                : 5; // Bits 31:27
+	};
+	uint32_t raw;
+};
+
+union ddr_comp_ctl_comp_reg {
+	struct __packed {
+		uint32_t slew_rate_comp : 6; // Bits  5:0
+		uint32_t tco_comp       : 6; // Bits 11:6
+		uint32_t rcomp_drv_up   : 6; // Bits 17:12
+		uint32_t rcomp_drv_down : 6; // Bits 23:18
+		uint32_t ls_comp        : 4; // Bits 27:24
+		uint32_t                : 4; // Bits 31:28
+	};
+	uint32_t raw;
+};
+
+union ddr_comp_clk_comp_reg {
+	struct __packed {
+		uint32_t slew_rate_comp : 5; // Bits  4:0
+		uint32_t tco_comp       : 6; // Bits 10:5
+		uint32_t rcomp_drv_up   : 6; // Bits 16:11
+		uint32_t rcomp_drv_down : 6; // Bits 22:17
+		uint32_t ls_comp        : 4; // Bits 26:23
+		uint32_t                : 5; // Bits 31:27
+	};
+	uint32_t raw;
+};
+
 union ddr_comp_ctl_0_reg {
 	struct __packed {
 		uint32_t                    : 3; // Bits  2:0
diff --git a/src/northbridge/intel/haswell/registers/mchbar.h b/src/northbridge/intel/haswell/registers/mchbar.h
index 1a168a3fc8..a944e12625 100644
--- a/src/northbridge/intel/haswell/registers/mchbar.h
+++ b/src/northbridge/intel/haswell/registers/mchbar.h
@@ -22,6 +22,7 @@
 
 #define DDR_DATA_TRAIN_FEEDBACK(ch, byte)	_DDRIO_C_R_B(0x0054, ch, 0, byte)
 
+#define DDR_DATA_OFFSET_COMP_ch_b(ch, byte)	_DDRIO_C_R_B(0x005c, ch, 0, byte)
 #define DQ_CONTROL_1(ch, byte)			_DDRIO_C_R_B(0x0060, ch, 0, byte)
 #define DQ_CONTROL_2(ch, byte)			_DDRIO_C_R_B(0x0064, ch, 0, byte)
 #define DDR_DATA_OFFSET_TRAIN_ch_b(ch, byte)	_DDRIO_C_R_B(0x0070, ch, 0, byte)
@@ -88,7 +89,8 @@
 #define DDR_CLK_CB_STATUS			0x3918
 
 /* DDR COMP (global) */
-#define DDR_COMP_DATA_COMP_1			0x3a04
+#define DDR_DATA_COMP_0				0x3a00
+#define DDR_DATA_COMP_1				0x3a04
 #define DDR_COMP_CMD_COMP			0x3a08
 #define DDR_COMP_CTL_COMP			0x3a0c
 #define DDR_COMP_CLK_COMP			0x3a10

From eaf76d2dd13245dc14778341816133547f198c2c Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Wed, 2 Jul 2025 11:30:37 -0500
Subject: [PATCH 1494/3886] vc/intel/fsp2_0/twinlake: Update FSP headers

Replace the existing TWL FSP headers, which were copied from ADL-N,
with the actual TWL headers.

TEST=starlabs byte_twl passes abuild w/o using IOT FSP.

Change-Id: I5c2836e81dee47dee73b14ce02f7bb8d0e846135
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88274
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
---
 .../intel/fsp/fsp2_0/twinlake/FspUpd.h        |   2 +-
 .../intel/fsp/fsp2_0/twinlake/FspmUpd.h       | 994 ++++++++++++++++--
 .../intel/fsp/fsp2_0/twinlake/FspsUpd.h       | 699 +++++++++---
 3 files changed, 1478 insertions(+), 217 deletions(-)

diff --git a/src/vendorcode/intel/fsp/fsp2_0/twinlake/FspUpd.h b/src/vendorcode/intel/fsp/fsp2_0/twinlake/FspUpd.h
index 54c7c64a5f..ab4bfca85c 100644
--- a/src/vendorcode/intel/fsp/fsp2_0/twinlake/FspUpd.h
+++ b/src/vendorcode/intel/fsp/fsp2_0/twinlake/FspUpd.h
@@ -1,6 +1,6 @@
 /** @file
 
-Copyright (c) 2022 - 2024, Intel Corporation. All rights reserved.<BR>
+Copyright (c) 2025, Intel Corporation. All rights reserved.<BR>
 
 Redistribution and use in source and binary forms, with or without modification,
 are permitted provided that the following conditions are met:
diff --git a/src/vendorcode/intel/fsp/fsp2_0/twinlake/FspmUpd.h b/src/vendorcode/intel/fsp/fsp2_0/twinlake/FspmUpd.h
index a85327d3c6..a4184fc592 100644
--- a/src/vendorcode/intel/fsp/fsp2_0/twinlake/FspmUpd.h
+++ b/src/vendorcode/intel/fsp/fsp2_0/twinlake/FspmUpd.h
@@ -1,6 +1,6 @@
 /** @file
 
-Copyright (c) 2022 - 2024, Intel Corporation. All rights reserved.<BR>
+Copyright (c) 2025, Intel Corporation. All rights reserved.<BR>
 
 Redistribution and use in source and binary forms, with or without modification,
 are permitted provided that the following conditions are met:
@@ -308,9 +308,9 @@ typedef struct {
 **/
   UINT8                       TrainTrace;
 
-/** Offset 0x0177 - Reserved
+/** Offset 0x0177
 **/
-  UINT8                       Reserved0;
+  UINT8                       UnusedUpdSpace0;
 
 /** Offset 0x0178 - Tseg Size
   Size of SMRAM memory reserved. 0x400000 for Release build and 0x1000000 for Debug build
@@ -407,9 +407,11 @@ typedef struct {
 **/
   UINT8                       PchHdaAudioLinkDmicClockSelect[2];
 
-/** Offset 0x019A - Reserved
+/** Offset 0x019A - PchPreMemRsvd
+  Reserved for PCH Pre-Mem Reserved
+  $EN_DIS
 **/
-  UINT8                       Reserved1[5];
+  UINT8                       PchPreMemRsvd[5];
 
 /** Offset 0x019F - State of X2APIC_OPT_OUT bit in the DMAR table
   0=Disable/Clear, 1=Enable/Set
@@ -423,9 +425,9 @@ typedef struct {
 **/
   UINT8                       DmaControlGuarantee;
 
-/** Offset 0x01A1 - Reserved
+/** Offset 0x01A1
 **/
-  UINT8                       Reserved2[3];
+  UINT8                       UnusedUpdSpace1[3];
 
 /** Offset 0x01A4 - Base addresses for VT-d function MMIO access
   Base addresses for VT-d MMIO access per VT-d engine
@@ -493,9 +495,14 @@ typedef struct {
 **/
   UINT8                       UserBd;
 
-/** Offset 0x01D1 - Reserved
+/** Offset 0x01D1 - MRC Retraining on RTC Power Loss
+  Specifies whether MRC memory training will occur when RTC power loss is detected.
+  Options are 0=Memory will be re-trained if RTC power loss is detected. 1=Memory
+  will not be re-trained when RTC power loss is detected. (Typically used on board
+  designs without a dedicated RTC battery)
+  0:Disabled, 1:Enabled
 **/
-  UINT8                       Reserved3;
+  UINT8                       DisableMrcRetrainingOnRtcPowerLoss;
 
 /** Offset 0x01D2 - DDR Frequency Limit
   Maximum Memory Frequency Selections in Mhz. Options are 1067, 1333, 1600, 1867,
@@ -598,9 +605,9 @@ typedef struct {
 **/
   UINT8                       RefClk;
 
-/** Offset 0x01E3 - Reserved
+/** Offset 0x01E3
 **/
-  UINT8                       Reserved4;
+  UINT8                       UnusedUpdSpace2;
 
 /** Offset 0x01E4 - Memory Voltage
   DRAM voltage (Vdd) (supply voltage for input buffers and core logic of the DRAM
@@ -627,9 +634,9 @@ typedef struct {
 **/
   UINT8                       tCWL;
 
-/** Offset 0x01E9 - Reserved
+/** Offset 0x01E9
 **/
-  UINT8                       Reserved5;
+  UINT8                       UnusedUpdSpace3;
 
 /** Offset 0x01EA - tFAW
   Min Four Activate Window Delay Time, 0: AUTO, max: 63. Only used if FspmUpd->FspmConfig.SpdProfileSelected
@@ -649,9 +656,9 @@ typedef struct {
 **/
   UINT8                       tRCDtRP;
 
-/** Offset 0x01EF - Reserved
+/** Offset 0x01EF
 **/
-  UINT8                       Reserved6;
+  UINT8                       UnusedUpdSpace4;
 
 /** Offset 0x01F0 - tREFI
   Refresh Interval, 0: AUTO, max: 65535. Only used if FspmUpd->FspmConfig.SpdProfileSelected
@@ -804,9 +811,9 @@ typedef struct {
 **/
   UINT8                       PsmiRegionSize;
 
-/** Offset 0x0221 - Reserved
+/** Offset 0x0221
 **/
-  UINT8                       Reserved7[3];
+  UINT8                       UnusedUpdSpace5[3];
 
 /** Offset 0x0224 - Temporary MMIO address for GMADR
   Obsolete field now and it has been extended to 64 bit address, used GmAdr64
@@ -1046,9 +1053,9 @@ typedef struct {
 **/
   UINT8                       DdiPort4Ddc;
 
-/** Offset 0x0289 - Reserved
+/** Offset 0x0289
 **/
-  UINT8                       Reserved8[7];
+  UINT8                       UnusedUpdSpace6[7];
 
 /** Offset 0x0290 - Temporary MMIO address for GMADR
   The reference code will use this as Temporary MMIO address space to access GMADR
@@ -1072,9 +1079,9 @@ typedef struct {
 **/
   UINT8                       SaVoltageMode;
 
-/** Offset 0x029B - Reserved
+/** Offset 0x029B
 **/
-  UINT8                       Reserved9;
+  UINT8                       UnusedUpdSpace7;
 
 /** Offset 0x029C - SA/Uncore Voltage Override
   The SA/Uncore voltage override applicable when SA/Uncore voltage mode is in Override
@@ -1103,9 +1110,73 @@ typedef struct {
 **/
   UINT8                       TvbVoltageOptimization;
 
-/** Offset 0x02A2 - Reserved
+/** Offset 0x02A2 - Enable/Disable Display Audio Link in Pre-OS
+  0(Default)= Disable, 1 = Enable
+  0: Disabled, 1: Enabled
 **/
-  UINT8                       Reserved10[111];
+  UINT8                       DisplayAudioLink;
+
+/** Offset 0x02A3
+**/
+  UINT8                       UnusedUpdSpace8;
+
+/** Offset 0x02A4 - Memory VDDQ Voltage
+  DRAM voltage (Vddq) (supply voltage for DQ/DQS of the DRAM chips) in millivolts
+  from 0 - default to 1435mv.
+**/
+  UINT16                      VddqVoltage;
+
+/** Offset 0x02A6 - Memory VPP Voltage
+  DRAM voltage (Vpp) (supply voltage for VPP of the DRAM chips) in millivolts from
+  0 - default to 2135mv.
+**/
+  UINT16                      VppVoltage;
+
+/** Offset 0x02A8 - CPU PCIe New FOM
+  Enable/Disable NewFom for DEKEL Programming. 0: Disable(Default); 1: Enable
+  $EN_DIS
+**/
+  UINT8                       CpuPcieNewFom[4];
+
+/** Offset 0x02AC - DMI DEKEL New FOM
+  Enable/Disable NewFom for DEKEL Programming. 0: Disable(Default); 1: Enable
+  $EN_DIS
+**/
+  UINT8                       DmiNewFom;
+
+/** Offset 0x02AD - Dynamic Memory Boost
+  0(Default): Disable, 1: Enable. When enabled, MRC will train the Default SPD Profile,
+  and also the profile selected by SpdProfileSelected, to allow automatic switching
+  during runtime. Only valid if SpdProfileSelected is an XMP Profile, otherwise ignored.
+  $EN_DIS
+**/
+  UINT8                       DynamicMemoryBoost;
+
+/** Offset 0x02AE - Hybrid Graphics Support
+  0(Default): PEG10, 1: PEG60, 2:PEG62. Help to select Hybrid Graphics Support on Peg Port
+**/
+  UINT8                       HgSupport;
+
+/** Offset 0x02AF - Realtime Memory Frequency
+  0(Default): Disabled, 1: Enabled. Ignored unless SpdProfileSelected is an XMP Profile.
+  If enabled, MRC will train the Default SPD Profile, and also the selected XMP Profile,
+  to allow manually triggered switching between frequencies at runtime.
+  $EN_DIS
+**/
+  UINT8                       RealtimeMemoryFrequency;
+
+/** Offset 0x02B0 - OC Safe Mode
+  0: Disabled, 1(Default): Enabled. Ignored unless SpdProfileSelected is an XMP Profile.
+  If enabled, MRC will use less aggressive controls when training memory.
+  $EN_DIS
+**/
+  UINT8                       OCSafeMode;
+
+/** Offset 0x02B1 - SaPreMemProductionRsvd
+  Reserved for SA Pre-Mem Production
+  $EN_DIS
+**/
+  UINT8                       SaPreMemProductionRsvd[96];
 
 /** Offset 0x0311 - Enable Gt CLOS
   0(Default)=Disable, 1=Enable
@@ -1273,9 +1344,83 @@ typedef struct {
 **/
   UINT8                       DmiGen3UsPortTxPreset[8];
 
-/** Offset 0x037B - Reserved
+/** Offset 0x037B - DMI Hw Eq Gen4 CoeffList Cm
+  CPU_PCIE_EQ_PARAM. Coefficient C-1.
 **/
-  UINT8                       Reserved11[54];
+  UINT8                       CpuDmiHwEqGen4CoeffListCm[8];
+
+/** Offset 0x0383 - DMI Hw Eq Gen4 CoeffList Cp
+  CPU_PCIE_EQ_PARAM. Coefficient C+1.
+**/
+  UINT8                       CpuDmiHwEqGen4CoeffListCp[8];
+
+/** Offset 0x038B - Enable/Disable CPU DMI GEN4 Phase 23 Bypass
+  CPU DMI GEN4 Phase 23 Bypass. Disabled(0x0)(Default): Disable Phase 23 Bypass, Enabled(0x1):
+  Enable  Phase 23 Bypass
+  $EN_DIS
+**/
+  UINT8                       Gen4EqPhase23Bypass;
+
+/** Offset 0x038C - Enable/Disable CPU DMI GEN4 Phase 3 Bypass
+  CPU DMI GEN3 Phase 4 Bypass. Disabled(0x0)(Default): Disable Phase 3 Bypass, Enabled(0x1):
+  Enable  Phase 3 Bypass
+  $EN_DIS
+**/
+  UINT8                       Gen4EqPhase3Bypass;
+
+/** Offset 0x038D - Enable/Disable DMI GEN4 DmiGen4DsPresetEnable
+  Enable/Disable DMI GEN4 DmiGen4DsPreset. Auto(0x0)(Default): DmiGen4DsPresetEnable,
+  Manual(0x1): Enable DmiGen4DsPresetEnable
+  $EN_DIS
+**/
+  UINT8                       DmiGen4DsPresetEnable;
+
+/** Offset 0x038E - DMI Gen4 Root port preset Tx values per lane
+  Used for programming DMI Gen4 preset values per lane. Range: 0-10, 7 is default
+  for each lane
+**/
+  UINT8                       DmiGen4DsPortTxPreset[8];
+
+/** Offset 0x0396 - Enable/Disable CPU DMI Gen4 EQ Remote Transmitter Coefficient/Preset Override Enable
+  Program Remote Transmitter Coefficient/Preset Override. Disabled(0x0)(Default):
+  Disable Remote Transmitter Coefficient/Preset Override, Enabled(0x1): Enable  Remote
+  Transmitter Coefficient/Preset Override
+  $EN_DIS
+**/
+  UINT8                       Gen4RtcoRtpoEnable;
+
+/** Offset 0x0397 - Enable/Disable CPU DMI Gen4 EQ Local Transmitter Coefficient Override Enable
+  Program Gen3 EQ Local Transmitter Coefficient Override. Disabled(0x0)(Default):
+  Disable Local Transmitter Coefficient Override, Enabled(0x1): Enable  Local Transmitter
+  Coefficient Override
+  $EN_DIS
+**/
+  UINT8                       Gen4LtcoEnable;
+
+/** Offset 0x0398 - DMI Gen4 Transmitter Pre-Cursor Coefficient
+  Used for programming DMI Gen4 Transmitter Pre-Cursor Coefficient . Range: 0-10,
+  7 is default for each lane
+**/
+  UINT8                       DmiGen4Ltcpre[8];
+
+/** Offset 0x03A0 - DMI Gen4 Transmitter Post-Cursor Coefficient
+  Used for programming DMI Gen4 Transmitter Post-Cursor Coefficient. Range: 0-9, 7
+  is default for each lane
+**/
+  UINT8                       DmiGen4Ltcpo[8];
+
+/** Offset 0x03A8 - Enable/Disable DMI GEN4 DmiGen4UsPresetEnable
+  Enable/Disable DMI GEN4 DmiGen4UsPreset. Auto(0x0)(Default): DmiGen4UsPresetEnable,
+  Manual(0x1): Enable DmiGen4UsPresetEnable
+  $EN_DIS
+**/
+  UINT8                       DmiGen4UsPresetEnable;
+
+/** Offset 0x03A9 - DMI Gen4 Root port preset Tx values per lane
+  Used for programming DMI Gen4 preset values per lane. Range: 0-10, 1 is default
+  for each lane
+**/
+  UINT8                       DmiGen4UsPortTxPreset[8];
 
 /** Offset 0x03B1 - DMI ASPM Control Configuration:{Combo
   Set ASPM Control configuration
@@ -1430,9 +1575,10 @@ typedef struct {
 **/
   UINT8                       CorePllVoltageOffset;
 
-/** Offset 0x03CD - Reserved
+/** Offset 0x03CD - Atom Core PLL voltage offset
+  Atom Core PLL voltage offset. <b>0: No offset</b>. Range 0-15
 **/
-  UINT8                       Reserved12;
+  UINT8                       AtomPllVoltageOffset;
 
 /** Offset 0x03CE - Ring Downbin
   Ring Downbin enable/disable. When enabled, CPU will ensure the ring ratio is always
@@ -1453,9 +1599,9 @@ typedef struct {
 **/
   UINT8                       TjMaxOffset;
 
-/** Offset 0x03D1 - Reserved
+/** Offset 0x03D1
 **/
-  UINT8                       Reserved13;
+  UINT8                       UnusedUpdSpace9;
 
 /** Offset 0x03D2 - Ring voltage override
   The ring voltage override which is applied to the entire range of cpu ring frequencies.
@@ -1499,9 +1645,72 @@ typedef struct {
 **/
   UINT8                       DebugInterfaceLockEnable;
 
-/** Offset 0x03DC - Reserved
+/** Offset 0x03DC - Atom L2 voltage mode
+  Atom L2 voltage mode; <b>0: Adaptive</b>; 1: Override.
+  $EN_DIS
 **/
-  UINT8                       Reserved14[24];
+  UINT8                       AtomL2VoltageMode;
+
+/** Offset 0x03DD
+**/
+  UINT8                       UnusedUpdSpace10;
+
+/** Offset 0x03DE - Atom L2 Voltage Override
+  The atom L2 voltage override which is applied to the entire range of atom L2 frequencies.
+  Valid Range 0 to 2000
+**/
+  UINT16                      AtomL2VoltageOverride;
+
+/** Offset 0x03E0 - Atom L2 Turbo voltage Adaptive
+  Extra Turbo voltage applied to the atom L2 when the atom L2 is operating in turbo
+  mode. Valid Range 0 to 2000
+**/
+  UINT16                      AtomL2VoltageAdaptive;
+
+/** Offset 0x03E2 - Atom L2 Turbo voltage Offset
+  The voltage offset applied to the atom while operating in turbo mode.Valid Range 0 to 1000
+**/
+  UINT16                      AtomL2VoltageOffset;
+
+/** Offset 0x03E4 - Per-Atom-Cluster VF Offset
+  Array used to specifies the selected Atom Core Cluster Offset Voltage. This voltage
+  is specified in millivolts.
+**/
+  UINT16                      PerAtomClusterVoltageOffset[4];
+
+/** Offset 0x03EC - Per-Atom-Cluster VF Offset Prefix
+  Sets the PerAtomClusterVoltageOffset value as positive or negative for the selected
+  Core; <b>0: Positive </b>; 1: Negative.
+**/
+  UINT8                       PerAtomClusterVoltageOffsetPrefix[4];
+
+/** Offset 0x03F0 - Enable IA CEP
+  Control for enabling/disabling IA CEP (Current Excursion Protection)). <b>1: Enable</b>;
+  0: Disable
+  $EN_DIS
+**/
+  UINT8                       IaCepEnable;
+
+/** Offset 0x03F1 - Enable GT CEP
+  Control for enabling/disabling GT CEP (Current Excursion Protection)). <b>1: Enable</b>;
+  0: Disable
+  $EN_DIS
+**/
+  UINT8                       GtCepEnable;
+
+/** Offset 0x03F2 - Enable CPU DLVR bypass mode support
+  DEPRECATED
+  $EN_DIS
+**/
+  UINT8                       DlvrBypassModeEnable;
+
+/** Offset 0x03F3 - Number of active small cores
+  Number of active small cores(Depends on Number of small cores). Default 0xFF means
+  to active all system supported small cores. <b>0xFF: Active all small cores</b>;
+  0: Disable all small cores; 1: 1; 2: 2; 3: 3;
+  0:Disable all small cores, 1:1, 2:2, 3:3, 0xFF:Active all small cores
+**/
+  UINT8                       ActiveSmallCoreCount;
 
 /** Offset 0x03F4 - Core VF Point Offset Mode
   Selects Core Voltage & Frequency Offset mode between Legacy and Selection modes.
@@ -1511,9 +1720,9 @@ typedef struct {
 **/
   UINT8                       CoreVfPointOffsetMode;
 
-/** Offset 0x03F5 - Reserved
+/** Offset 0x03F5
 **/
-  UINT8                       Reserved15;
+  UINT8                       UnusedUpdSpace11[1];
 
 /** Offset 0x03F6 - Core VF Point Offset
   Array used to specifies the Core Voltage Offset applied to the each selected VF
@@ -1538,9 +1747,24 @@ typedef struct {
 **/
   UINT8                       CoreVfPointCount;
 
-/** Offset 0x0433 - Reserved
+/** Offset 0x0433 - Core VF Configuration Scope
+  Alows both all-core VF curve or per-core VF curve configuration; <b>0: All-core</b>;
+  1: Per-core.
+  0:All-core, 1:Per-core
 **/
-  UINT8                       Reserved16[25];
+  UINT8                       CoreVfConfigScope;
+
+/** Offset 0x0434 - Per-core VF Offset
+  Array used to specifies the selected Core Offset Voltage. This voltage is specified
+  in millivolts.
+**/
+  UINT16                      PerCoreVoltageOffset[8];
+
+/** Offset 0x0444 - Per-core VF Offset Prefix
+  Sets the PerCoreVoltageOffset value as positive or negative for the selected Core;
+  <b>0: Positive </b>; 1: Negative.
+**/
+  UINT8                       PerCoreVoltageOffsetPrefix[8];
 
 /** Offset 0x044C - Per Core Max Ratio override
   Enable or disable Per Core PState OC supported by writing OCMB 0x1D to program new
@@ -1554,9 +1778,18 @@ typedef struct {
 **/
   UINT8                       PerCoreRatio[8];
 
-/** Offset 0x0455 - Reserved
+/** Offset 0x0455 - Atom Cluster Max Ratio
+  Array for Atom Cluster Max Ratio, 4 ATOM cores are in the same Cluster and their
+  max core ratio will be aligned.
 **/
-  UINT8                       Reserved17[5];
+  UINT8                       AtomClusterRatio[4];
+
+/** Offset 0x0459 - Core Ratio Extension Mode
+  Enable or disable Core Ratio above 85 Extension Mode by writing BIOS MB 0x37 to
+  enable FULL_RANGE_MULTIPLIER_UNLOCK_EN. <b>0: Disable</b>, 1: enable
+  $EN_DIS
+**/
+  UINT8                       CoreRatioExtensionMode;
 
 /** Offset 0x045A - Pvd Ratio Threshold
   Select PVD Ratio Threshold Value from Range 1 to 40. 0 - Auto/Default.
@@ -1576,9 +1809,35 @@ typedef struct {
 **/
   UINT8                       CrashLogGprs;
 
-/** Offset 0x045D - Reserved
+/** Offset 0x045D - Ring VF Point Offset Mode
+  Selects Ring Voltage & Frequency Offset mode between Legacy and Selection modes.
+  In Legacy Mode, setting a global offset for the entire VF curve. In Selection Mode,
+  setting a selected VF point; <b>0: Legacy</b>; 1: Selection.
+  0:Legacy, 1:Selection
 **/
-  UINT8                       Reserved18[62];
+  UINT8                       RingVfPointOffsetMode;
+
+/** Offset 0x045E - Ring VF Point Offset
+  Array used to specifies the Ring Voltage Offset applied to the each selected VF
+  Point. This voltage is specified in millivolts.
+**/
+  UINT16                      RingVfPointOffset[15];
+
+/** Offset 0x047C - Ring VF Point Offset Prefix
+  Sets the RingVfPointOffset value as positive or negative for corresponding core
+  VF Point; <b>0: Positive </b>; 1: Negative.
+**/
+  UINT8                       RingVfPointOffsetPrefix[15];
+
+/** Offset 0x048B - Ring VF Point Ratio
+  Array for the each selected Ring VF Point to display the ration.
+**/
+  UINT8                       RingVfPointRatio[15];
+
+/** Offset 0x049A - Ring VF Point Count
+  Number of supported Ring Voltage & Frequency Point Offset
+**/
+  UINT8                       RingVfPointCount;
 
 /** Offset 0x049B - BCLK Frequency Source
   Clock source of BCLK OC frequency, <b>1:CPU BCLK</b>, 2:PCH BCLK, 3:External CLK
@@ -1593,9 +1852,9 @@ typedef struct {
 **/
   UINT8                       GpioOverride;
 
-/** Offset 0x049D - Reserved
+/** Offset 0x049D
 **/
-  UINT8                       Reserved19[3];
+  UINT8                       UnusedUpdSpace12[3];
 
 /** Offset 0x04A0 - CPU BCLK OC Frequency
   CPU BCLK OC Frequency in 10KHz units increasing. Value 9800 (10KHz) = 98MHz <b>0
@@ -1603,9 +1862,144 @@ typedef struct {
 **/
   UINT32                      CpuBclkOcFrequency;
 
-/** Offset 0x04A4 - Reserved
+/** Offset 0x04A4 - Bitmask of disable cores
+  Core mask is a bitwise indication of which core should be disabled. <b>0x00=Default</b>;
+  Bit 0 - core 0, bit 7 - core 7.
 **/
-  UINT8                      Reserved20[40];
+  UINT32                      DisablePerCoreMask;
+
+/** Offset 0x04A8 - Bitmask of disable atoms
+  DEPRECATED
+**/
+  UINT32                      DisablePerAtomMask;
+
+/** Offset 0x04AC - Sa PLL Frequency
+  Configure Sa PLL Frequency. <b>0: 3200MHz </b>, 1: 1600MHz
+  0: 3200MHz, 1: 1600MHz
+**/
+  UINT8                       SaPllFreqOverride;
+
+/** Offset 0x04AD - Skip override boot mode When Fw Update.
+  When set to TRUE and boot mode is BOOT_ON_FLASH_UPDATE, skip setting boot mode to
+  BOOT_WITH_FULL_CONFIGURATION in PEI memory init.
+  $EN_DIS
+**/
+  UINT8                       SiSkipOverrideBootModeWhenFwUpdate;
+
+/** Offset 0x04AE - TSC HW Fixup disable
+  TSC HW Fixup disable during TSC copy from PMA to APIC. <b>0: Enable</b>; 1: Disable
+  0:Enable, 1:Disable
+**/
+  UINT8                       TscDisableHwFixup;
+
+/** Offset 0x04AF - Support IA Unlimited ICCMAX
+  Support IA Unlimited ICCMAX up to maximum value 512A; <b>0: Disabled</b>; 1: Enabled.
+  $EN_DIS
+**/
+  UINT8                       IaIccUnlimitedMode;
+
+/** Offset 0x04B0 - IA ICCMAX
+  IA ICCMAX value is represented in 1/4 A increments. A value of 400 = 100A. <b>4
+  </b>. Range is 4-2047.
+**/
+  UINT16                      IaIccMax;
+
+/** Offset 0x04B2 - Support GT Unlimited ICCMAX
+  Support GT Unlimited ICCMAX up to maximum value 512A; <b>0: Disabled</b>; 1: Enabled.
+  $EN_DIS
+**/
+  UINT8                       GtIccUnlimitedMode;
+
+/** Offset 0x04B3
+**/
+  UINT8                       UnusedUpdSpace13;
+
+/** Offset 0x04B4 - GT ICCMAX
+  GT ICCMAX value is represented in 1/4 A increments. A value of 400 = 100A. <b>4
+  </b>. Range is 4-2047.
+**/
+  UINT16                      GtIccMax;
+
+/** Offset 0x04B6 - TVB Down Bins for Temp Threshold 0
+  Down Bins (delta) for Temperature Threshold 0. When running above Temperature Threshold
+  0, the ratio will be clipped by MAX_RATIO[n]-This value, when TVB ratio clipping
+  is enabled. Default is 1.
+**/
+  UINT8                       TvbDownBinsTempThreshold0;
+
+/** Offset 0x04B7 - TVB Temperature Threshold 0
+  TVB Temp (degrees C) - Temperature Threshold 0. Running ABOVE this temperature will
+  clip delta Down Bins for Threshold 0 from the resolved OC Ratio, when TVB ratio
+  clipping is enabled. Default is 70.
+**/
+  UINT8                       TvbTempThreshold0;
+
+/** Offset 0x04B8 - TVB Temperature Threshold 1
+  TVB Temp (degrees C) - Temperature Threshold 1. Running ABOVE this temperature will
+  clip delta Down Bins for Threshold 1 from the resolved OC Ratio, when TVB ratio
+  clipping is enabled. Default is 100.
+**/
+  UINT8                       TvbTempThreshold1;
+
+/** Offset 0x04B9 - TVB Down Bins for Temp Threshold 1
+  Down Bins (delta) for Temperature Threshold 1. When running above Temperature Threshold
+  1, the ratio will be clipped by MAX_RATIO[n]-Down Bin Threshold 1-This value, when
+  TVB ratio clipping is enabled. Default is 2.
+**/
+  UINT8                       TvbDownBinsTempThreshold1;
+
+/** Offset 0x04BA - FLL Overclock Mode Enable
+  Select FLL Mode Value from 0 to 3. 0x0 = no overclocking, 0x1 = ratio overclocking
+  with nominal (0.5-1x) reference clock frequency, 0x2 = BCLK overclocking with elevated
+  (1-3x) reference clock frequency, 0x3 = BCLK overclocking with extreme elevated
+  (3-5x) reference clock frequency and ratio limited to 63.
+  $EN_DIS
+**/
+  UINT8                       FllOcModeEn;
+
+/** Offset 0x04BB - FLL Overclock Mode
+  Select FLL Mode Value from 0 to 3. 0x0 = no overclocking, 0x1 = ratio overclocking
+  with nominal (0.5-1x) reference clock frequency, 0x2 = BCLK overclocking with elevated
+  (1-3x) reference clock frequency, 0x3 = BCLK overclocking with extreme elevated
+  (3-5x) reference clock frequency and ratio limited to 63.
+**/
+  UINT8                       FllOverclockMode;
+
+/** Offset 0x04BC - Configuration for boot TDP selection
+  Configuration for boot TDP selection; <b>0: TDP Nominal</b>; 1: TDP Down; 2: TDP
+  Up;0xFF : Deactivate
+**/
+  UINT8                       ConfigTdpLevel;
+
+/** Offset 0x04BD
+**/
+  UINT8                       UnusedUpdSpace14[3];
+
+/** Offset 0x04C0 - Short term Power Limit value for custom cTDP level 1
+  Short term Power Limit value for custom cTDP level 1. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid
+  Range 0 to 4095875 in Step size of 125
+**/
+  UINT32                      CustomPowerLimit1;
+
+/** Offset 0x04C4 - Enhanced Thermal Turbo Mode
+  When eTVB mode is enabled user will be clipped when temperatures reach 70C <b>0:
+  Disabled</b>; 1: Enabled.
+  $EN_DIS
+**/
+  UINT8                       Etvb;
+
+/** Offset 0x04C5 - UnderVolt Protection
+  When UnderVolt Protection is enabled, user will be not be able to program under
+  voltage in OS runtime. 0: Disabled; <b>1: Enabled</b>
+  $EN_DIS
+**/
+  UINT8                       UnderVoltProtection;
+
+/** Offset 0x04C6 - ReservedCpuPreMem
+  Reserved for Cpu Pre-Mem
+  $EN_DIS
+**/
+  UINT8                       ReservedCpuPreMem[6];
 
 /** Offset 0x04CC - BiosGuard
   Enable/Disable. 0: Disable, Enable/Disable BIOS Guard feature, 1: enable
@@ -1623,9 +2017,9 @@ typedef struct {
 **/
   UINT8                       Txt;
 
-/** Offset 0x04CF - Reserved
+/** Offset 0x04CF
 **/
-  UINT8                       Reserved21;
+  UINT8                       UnusedUpdSpace15;
 
 /** Offset 0x04D0 - PrmrrSize
   Enable/Disable. 0: Disable, define default value of PrmrrSize , 1: enable
@@ -1687,9 +2081,11 @@ typedef struct {
 **/
   UINT8                       IsTPMPresence;
 
-/** Offset 0x0509 - Reserved
+/** Offset 0x0509 - ReservedSecurityPreMem
+  Reserved for Security Pre-Mem
+  $EN_DIS
 **/
-  UINT8                       Reserved22[32];
+  UINT8                       ReservedSecurityPreMem[32];
 
 /** Offset 0x0529 - Enable PCH HSIO PCIE Rx Set Ctle
   Enable PCH PCIe Gen 3 Set CTLE Value.
@@ -1874,9 +2270,9 @@ typedef struct {
 **/
   UINT8                       PchNumRsvdSmbusAddresses;
 
-/** Offset 0x0745 - Reserved
+/** Offset 0x0745
 **/
-  UINT8                       Reserved23;
+  UINT8                       UnusedUpdSpace16;
 
 /** Offset 0x0746 - SMBUS Base Address
   SMBUS Base Address (IO space).
@@ -1895,18 +2291,32 @@ typedef struct {
 **/
   UINT8                       PcieClkSrcUsage[18];
 
-/** Offset 0x075B - Reserved
+/** Offset 0x075B
 **/
-  UINT8                       Reserved24[14];
+  UINT8                       PcieClkSrcUsageRsvd[14];
 
 /** Offset 0x0769 - ClkReq-to-ClkSrc mapping
   Number of ClkReq signal assigned to ClkSrc
 **/
   UINT8                       PcieClkSrcClkReq[18];
 
-/** Offset 0x077B - Reserved
+/** Offset 0x077B
 **/
-  UINT8                       Reserved25[93];
+  UINT8                       PcieClkSrcClkReqRsvd[14];
+
+/** Offset 0x0789
+**/
+  UINT8                       UnusedUpdSpace17[3];
+
+/** Offset 0x078C - Clk Req GPIO Pin
+  Select Clk Req Pin. Refer to GPIO_*_MUXING_SRC_CLKREQ_x* for possible values.
+**/
+  UINT32                      PcieClkReqGpioMux[18];
+
+/** Offset 0x07D4 - Point of RsvdSmbusAddressTable
+  Array of addresses reserved for non-ARP-capable SMBus devices.
+**/
+  UINT32                      RsvdSmbusAddressTablePtr;
 
 /** Offset 0x07D8 - Enable PCIE RP Mask
   Enable/disable PCIE Root Ports. 0: disable, 1: enable. One bit for each port, bit0
@@ -1966,9 +2376,9 @@ typedef struct {
 **/
   UINT8                       PchHdaDspEnable;
 
-/** Offset 0x07F5 - Reserved
+/** Offset 0x07F5
 **/
-  UINT8                       Reserved26[3];
+  UINT8                       UnusedUpdSpace18[3];
 
 /** Offset 0x07F8 - DMIC<N> Data Pin Muxing
   Determines DMIC<N> Data Pin muxing. See GPIO_*_MUXING_DMIC<N>_DATA_*
@@ -2028,9 +2438,9 @@ typedef struct {
 **/
   UINT8                       SerialIoUartDebugAutoFlow;
 
-/** Offset 0x0811 - Reserved
+/** Offset 0x0811
 **/
-  UINT8                       Reserved27[3];
+  UINT8                       UnusedUpdSpace19[3];
 
 /** Offset 0x0814 - Serial Io Uart Debug BaudRate
   Set default BaudRate Supported from 0 - default to 6000000. Recommended values 9600,
@@ -2056,9 +2466,9 @@ typedef struct {
 **/
   UINT8                       SerialIoUartDebugDataBits;
 
-/** Offset 0x081B - Reserved
+/** Offset 0x081B
 **/
-  UINT8                       Reserved28;
+  UINT8                       UnusedUpdSpace20;
 
 /** Offset 0x081C - Serial Io Uart Debug Mmio Base
   Select SerialIo Uart default MMIO resource in SEC/PEI phase when PcdSerialIoUartMode
@@ -2376,9 +2786,11 @@ typedef struct {
 **/
   UINT8                       ChHashEnable;
 
-/** Offset 0x0854 - Reserved
+/** Offset 0x0854 - Ch Hash Settings Override
+  Channel Hash Settings Override
+  $EN_DIS
 **/
-  UINT8                       Reserved29;
+  UINT8                       ChHashOverride;
 
 /** Offset 0x0855 - Extern Therm Status
   Enables/Disable Extern Therm Status
@@ -2416,9 +2828,11 @@ typedef struct {
 **/
   UINT8                       ThrtCkeMinDefeat;
 
-/** Offset 0x085B - Reserved
+/** Offset 0x085B - Row Hammer Select
+  Row Hammer Select
+  0:Disable, 1:RFM, 2:pTRR
 **/
-  UINT8                       Reserved30;
+  UINT8                       RhSelect;
 
 /** Offset 0x085C - Exit On Failure (MRC)
   Enables/Disable Exit On Failure (MRC)
@@ -2522,9 +2936,17 @@ typedef struct {
 **/
   UINT8                       RMTBIT;
 
-/** Offset 0x086D - Reserved
+/** Offset 0x086D - ECC DFT feature
+  Enables/Disable ECC DFT feature
+  $EN_DIS
 **/
-  UINT8                       Reserved31[2];
+  UINT8                       EccDftEn;
+
+/** Offset 0x086E - Write0 feature
+  Enables/Disable Write0 feature
+  $EN_DIS
+**/
+  UINT8                       Write0;
 
 /** Offset 0x086F - Select if CLK0 is shared between Rank0 and Rank1 in DDR4 DDP
   Select if CLK0 is shared between Rank0 and Rank1 in DDR4 DDP
@@ -2581,9 +3003,11 @@ typedef struct {
 **/
   UINT8                       EWRDSEQ;
 
-/** Offset 0x087E - Reserved
+/** Offset 0x087E - MC_REFRESH_2X_MODE
+  DEPRECATED
+  $EN_DIS
 **/
-  UINT8                       Reserved32;
+  UINT8                       McRefresh2X;
 
 /** Offset 0x087F - Idle Energy Mc0Ch0Dimm0
   Idle Energy Consumed for 1 clk w/dimm idle/cke on, range[63;0],(10= Def)
@@ -2791,9 +3215,16 @@ typedef struct {
 **/
   UINT8                       ThrtCkeMinTmr;
 
-/** Offset 0x08A8 - Reserved
+/** Offset 0x08A8 - Allow Opp Ref Below Write Threhold
+  Allow opportunistic refreshes while we don't exit power down.
+  $EN_DIS
 **/
-  UINT8                       Reserved33[2];
+  UINT8                       AllowOppRefBelowWriteThrehold;
+
+/** Offset 0x08A9 - Write Threshold
+  Number of writes that can be accumulated while CKE is low before CKE is asserted.
+**/
+  UINT8                       WriteThreshold;
 
 /** Offset 0x08AA - Rapl Power Floor Ch0
   Power budget ,range[255;0],(0= 5.3W Def)
@@ -2823,9 +3254,10 @@ typedef struct {
 **/
   UINT8                       EpgEnable;
 
-/** Offset 0x08AF - Reserved
+/** Offset 0x08AF - RH pTRR LFSR0 Mask
+  Row Hammer pTRR LFSR0 Mask, 1/2^(value)
 **/
-  UINT8                       Reserved34;
+  UINT8                       Lfsr0Mask;
 
 /** Offset 0x08B0 - User Manual Threshold
   Disabled: Predefined threshold will be used.\n
@@ -2897,9 +3329,9 @@ typedef struct {
 **/
   UINT8                       UsbTcPortEnPreMem;
 
-/** Offset 0x08BB - Reserved
+/** Offset 0x08BB
 **/
-  UINT8                       Reserved35;
+  UINT8                       UnusedUpdSpace21;
 
 /** Offset 0x08BC - Post Code Output Port
   This option configures Post Code Output Port
@@ -2924,9 +3356,9 @@ typedef struct {
 **/
   UINT8                       WrcFeatureEnable;
 
-/** Offset 0x08C1 - Reserved
+/** Offset 0x08C1
 **/
-  UINT8                       Reserved36[3];
+  UINT8                       UnusedUpdSpace22[3];
 
 /** Offset 0x08C4 - BCLK RFI Frequency
   Bclk RFI Frequency for each SAGV point in Hz units. 98000000Hz = 98MHz <b>0 - No
@@ -2974,9 +3406,20 @@ typedef struct {
 **/
   UINT8                       Ddr4OneDpc;
 
-/** Offset 0x08DB - Reserved
+/** Offset 0x08DB - RH pTRR LFSR1 Mask
+  Row Hammer pTRR LFSR1 Mask, 1/2^(value)
 **/
-  UINT8                       Reserved37[3];
+  UINT8                       Lfsr1Mask;
+
+/** Offset 0x08DC - LPDDR ODT RttWr
+  Initial RttWr for LP4/5 in Ohms. 0x0 - Auto
+**/
+  UINT8                       LpddrRttWr;
+
+/** Offset 0x08DD - LPDDR ODT RttCa
+  Initial RttCa for LP4/5 in Ohms. 0x0 - Auto
+**/
+  UINT8                       LpddrRttCa;
 
 /** Offset 0x08DE - REFRESH_PANIC_WM
   DEPRECATED
@@ -3000,9 +3443,59 @@ typedef struct {
 **/
   UINT8                       CmdMirror;
 
-/** Offset 0x08E2 - Reserved
+/** Offset 0x08E2 - DIMM DFE Training
+  Enable/Disable DIMM DFE Training
+  $EN_DIS
 **/
-  UINT8                       Reserved38[9];
+  UINT8                       DIMMDFE;
+
+/** Offset 0x08E3 - Extended Bank Hashing
+  Enable/Disable Extended Bank Hashing
+  $EN_DIS
+**/
+  UINT8                       ExtendedBankHashing;
+
+/** Offset 0x08E4 - Refresh Watermarks
+  Refresh Watermarks: 0-Low, 1-High (default)
+  0:Set Refresh Watermarks to Low, 1:Set Refresh Watermarks to High (Default)
+**/
+  UINT8                       RefreshWm;
+
+/** Offset 0x08E5 - MC_REFRESH_RATE
+  Type of Refresh Rate used to prevent Row Hammer. Default is NORMAL Refresh
+  0:NORMAL Refresh, 1:1x Refresh, 2:2x Refresh, 3:4x Refresh
+**/
+  UINT8                       McRefreshRate;
+
+/** Offset 0x08E6 - Periodic DCC
+  Enable/Disable Periodic DCC; default: Disabled
+  $EN_DIS
+**/
+  UINT8                       PeriodicDcc;
+
+/** Offset 0x08E7 - LpMode
+  LpMode feature
+  0: Auto (default), 1: Enabled, 2: Disabled, 3: Reserved
+**/
+  UINT8                       LpMode;
+
+/** Offset 0x08E8 - TX DQS DCC Training
+  Enable/Disable TX DQS DCC Training
+  $EN_DIS
+**/
+  UINT8                       TXDQSDCC;
+
+/** Offset 0x08E9 - DRAM DCA Training
+  Enable/Disable DRAM DCA Training
+  $EN_DIS
+**/
+  UINT8                       DRAMDCA;
+
+/** Offset 0x08EA - EARLY DIMM DFE Training
+  Enable/Disable EARLY DIMM DFE Training
+  $EN_DIS
+**/
+  UINT8                       EARLYDIMMDFE;
 
 /** Offset 0x08EB - Skip external display device scanning
   Enable: Do not scan for external display device, Disable (Default): Scan external
@@ -3023,9 +3516,13 @@ typedef struct {
 **/
   UINT8                       LockPTMregs;
 
-/** Offset 0x08EE - Reserved
+/** Offset 0x08EE - Rsvd
+  Disable(0x0)(Default): Normal Operation - RxCTLE adaptive behavior enabled, Enable(0x1):
+  Override RxCTLE - Disable RxCTLE adaptive behavior to keep the configured RxCTLE
+  peak values unmodified
+  $EN_DIS
 **/
-  UINT8                       Reserved39;
+  UINT8                       PegGen3Rsvd;
 
 /** Offset 0x08EF - Panel Power Enable
   Control for enabling/disabling VDD force bit (Required only for early enabling of
@@ -3040,9 +3537,9 @@ typedef struct {
 **/
   UINT8                       BdatTestType;
 
-/** Offset 0x08F1 - Reserved
+/** Offset 0x08F1
 **/
-  UINT8                       Reserved40[3];
+  UINT8                       UnusedUpdSpace23[3];
 
 /** Offset 0x08F4 - PMR Size
   Size of PMR memory buffer. 0x400000 for normal boot and 0x200000 for S3 boot
@@ -3054,9 +3551,44 @@ typedef struct {
 **/
   UINT8                       PreBootDmaMask;
 
-/** Offset 0x08F9 - Reserved
+/** Offset 0x08F9
 **/
-  UINT8                       Reserved41[95];
+  UINT8                       UnusedUpdSpace24;
+
+/** Offset 0x08FA - Delta T12 Power Cycle Delay required in ms
+  Select the value for delay required. 0= No delay, 0xFFFF(Default) = Auto calculate
+  T12 Delay to max 500ms
+  0 : No Delay, 0xFFFF : Auto Calulate T12 Delay
+**/
+  UINT16                      DeltaT12PowerCycleDelay;
+
+/** Offset 0x08FC - Reuse Adl DDR5 Board or not
+  Indicate whether adl ddr5 board is reused.
+  0 : no, 1 : yes
+**/
+  UINT8                       ReuseAdlSDdr5Board;
+
+/** Offset 0x08FD - Oem T12 Delay Override
+  Oem T12 Delay Override. 0(Default)=Disable  1=Enable
+  $EN_DIS
+**/
+  UINT8                       OemT12DelayOverride;
+
+/** Offset 0x08FE - DQS Offset Adjust Training
+  Enable/Disable DQS Offset Adjust Training
+  $EN_DIS
+**/
+  UINT8                       DQSOFFSETADJUST;
+
+/** Offset 0x08FF - SaPreMemTestRsvd
+  Reserved for SA Pre-Mem Test
+  $EN_DIS
+**/
+  UINT8                       SaPreMemTestRsvd[88];
+
+/** Offset 0x0957
+**/
+  UINT8                       UnusedUpdSpace25;
 
 /** Offset 0x0958 - TotalFlashSize
   Enable/Disable. 0: Disable, define default value of TotalFlashSize , 1: enable
@@ -3070,9 +3602,11 @@ typedef struct {
 **/
   UINT16                      BiosSize;
 
-/** Offset 0x095C - Reserved
+/** Offset 0x095C - SecurityTestRsvd
+  Reserved for SA Pre-Mem Test
+  $EN_DIS
 **/
-  UINT8                       Reserved42[12];
+  UINT8                       SecurityTestRsvd[12];
 
 /** Offset 0x0968 - Smbus dynamic power gating
   Disable or Enable Smbus dynamic power gating.
@@ -3136,9 +3670,9 @@ typedef struct {
 **/
   UINT8                       SkipCpuReplacementCheck;
 
-/** Offset 0x0972 - Reserved
+/** Offset 0x0972
 **/
-  UINT8                       Reserved43[2];
+  UINT8                       UnusedUpdSpace26[2];
 
 /** Offset 0x0974 - Hybrid Graphics GPIO information for PEG 1
   Hybrid Graphics GPIO information for PEG 1, for Reset, power and wake GPIOs
@@ -3173,9 +3707,9 @@ typedef struct {
 **/
   UINT8                       SerialIoUartDebugMode;
 
-/** Offset 0x0A97 - Reserved
+/** Offset 0x0A97
 **/
-  UINT8                       Reserved44;
+  UINT8                       UnusedUpdSpace27;
 
 /** Offset 0x0A98 - SerialIoUartDebugRxPinMux - FSPT
   Select RX pin muxing for SerialIo UART used for debug
@@ -3199,9 +3733,257 @@ typedef struct {
 **/
   UINT32                      SerialIoUartDebugCtsPinMux;
 
-/** Offset 0x0AA8 - Reserved
+/** Offset 0x0AA8 - Ppr Enable Type
+  Enable Soft or Hard PPR <b>0:Disable</b>, 2:Hard PPR
+  0:Disable, 2:Hard PPR
 **/
-  UINT8                       Reserved45[130];
+  UINT8                       PprEnable;
+
+/** Offset 0x0AA9 - Margin Limit Check
+  Margin Limit Check. Choose level of margin check
+  0:Disable, 1:L1, 2:L2, 3:Both
+**/
+  UINT8                       MarginLimitCheck;
+
+/** Offset 0x0AAA - Margin Limit L2
+  % of L1 check for margin limit check
+**/
+  UINT16                      MarginLimitL2;
+
+/** Offset 0x0AAC - DEKEL CDR Relock
+  Enable/Disable CDR Relock. 0: Disable(Default); 1: Enable
+**/
+  UINT8                       CpuPcieRpCdrRelock[4];
+
+/** Offset 0x0AB0 - DMI DEKEL CDR Relock
+  Enable/Disable CPU DMI CDR Relock. 0: Disable(Default); 1: Enable
+  $EN_DIS
+**/
+  UINT8                       DmiCdrRelock;
+
+/** Offset 0x0AB1 - IbeccErrInjControl
+  IBECC Error Injection Control
+  0: No Error Injection, 1:Inject Correctable Error Address match, 3:Inject Correctable
+  Error on insertion counter, 5: Inject Uncorrectable Error Address match, 7:Inject
+  Uncorrectable Error on insertion counter
+**/
+  UINT8                       IbeccErrInjControl;
+
+/** Offset 0x0AB2
+**/
+  UINT8                       UnusedUpdSpace28[6];
+
+/** Offset 0x0AB8 - IbeccErrInjAddress
+  Address to match against for ECC error injection
+**/
+  UINT64                      IbeccErrInjAddress;
+
+/** Offset 0x0AC0 - IbeccErrInjMask
+  Mask to match against for ECC error injection
+**/
+  UINT64                      IbeccErrInjMask;
+
+/** Offset 0x0AC8 - IbeccErrInjCount
+  Number of transactions between ECC error injection
+**/
+  UINT32                      IbeccErrInjCount;
+
+/** Offset 0x0ACC - Pointer EnableDmaBuffer
+  Pointer of EnableDmaBuffer Callback Function.
+**/
+  UINT8                       EnableDmaBuffer[8];
+
+/** Offset 0x0AD4 - PLL Max Banding Ratio
+  DEPRECATED
+**/
+  UINT8                       PllMaxBandingRatio;
+
+/** Offset 0x0AD5
+**/
+  UINT8                       UnusedUpdSpace29[3];
+
+/** Offset 0x0AD8 - Debug Value
+  Debug Value
+**/
+  UINT32                      DebugValue;
+
+/** Offset 0x0ADC - Pre-Mem GPIO table address
+  AlderLake S needs to assert PCIe SLOT RTD3 and PEG reset pins in early PreMem phase.
+  0: Skip FSP PCIe pins programming. Refer to mAdlSPcieRstPinGpioTable[] in GpioSampleDef.h.
+**/
+  UINT32                      BoardGpioTablePreMemAddress;
+
+/** Offset 0x0AE0 - tRFCpb
+  Min Internal per bank refresh recovery delay time, 0: AUTO, max: 0xFFFF. Only used
+  if FspmUpd->FspmConfig.SpdProfileSelected == 1 (Custom Profile).
+**/
+  UINT16                      tRFCpb;
+
+/** Offset 0x0AE2 - tRFC2
+  Min Internal refresh recovery delay time, 0: AUTO, max: 0xFFFF. Only used if FspmUpd->FspmConfig.SpdProfileSelected
+  == 1 (Custom Profile).
+**/
+  UINT16                      tRFC2;
+
+/** Offset 0x0AE4 - tRFC4
+  Min Internal refresh recovery delay time, 0: AUTO, max: 0xFFFF. Only used if FspmUpd->FspmConfig.SpdProfileSelected
+  == 1 (Custom Profile).
+**/
+  UINT16                      tRFC4;
+
+/** Offset 0x0AE6 - tRRD_L
+  Min Internal row active to row active delay time for same bank groups, 0: AUTO,
+  max: 80. Only used if FspmUpd->FspmConfig.SpdProfileSelected == 1 (Custom Profile).
+**/
+  UINT8                       tRRD_L;
+
+/** Offset 0x0AE7 - tRRD_S
+  Min Internal row active to row active delay time for different bank groups, 0: AUTO,
+  max: 80. Only used if FspmUpd->FspmConfig.SpdProfileSelected == 1 (Custom Profile).
+**/
+  UINT8                       tRRD_S;
+
+/** Offset 0x0AE8 - tWTR_L
+  Min Internal write to read command delay time for same bank groups, 0: AUTO, max:
+  127. Only used if FspmUpd->FspmConfig.SpdProfileSelected == 1 (Custom Profile).
+**/
+  UINT8                       tWTR_L;
+
+/** Offset 0x0AE9 - tCCD_L
+  Min Internal CAS-to-CAS delay for same bank group, 0: AUTO, max: 80. Only used if
+  FspmUpd->FspmConfig.SpdProfileSelected == 1 (Custom Profile).
+**/
+  UINT8                       tCCD_L;
+
+/** Offset 0x0AEA - tWTR_S
+  Min Internal write to read command delay time for different bank groups, 0: AUTO,
+  max: 50. Only used if FspmUpd->FspmConfig.SpdProfileSelected == 1 (Custom Profile).
+**/
+  UINT8                       tWTR_S;
+
+/** Offset 0x0AEB
+**/
+  UINT8                       UnusedUpdSpace30[5];
+
+/** Offset 0x0AF0 - EccErrInjAddress
+  Address to match against for ECC error injection
+**/
+  UINT64                      EccErrInjAddress;
+
+/** Offset 0x0AF8 - EccErrInjMask
+  Mask to match against for ECC error injection
+**/
+  UINT64                      EccErrInjMask;
+
+/** Offset 0x0B00 - EccErrInjCount
+  Number of transactions between ECC error injection
+**/
+  UINT32                      EccErrInjCount;
+
+/** Offset 0x0B04 - Frequency Limit for 2DPC Mixed or non-POR Config
+  Frequency Limit for 2DPC Mixed or non-POR Config. 0: Auto (default), otherwise a
+  frequency in MT/s
+**/
+  UINT16                      FreqLimitMixedConfig;
+
+/** Offset 0x0B06 - First Dimm BitMask
+  Defines which DIMM should be populated first on a 2DPC board. Bit0: MC0 DIMM0, Bit1:
+  MC0 DIMM1, Bit2: MC1 DIMM0, Bit3: MC1 DIMM1. For each MC, the first DIMM to be
+  populated should be set to '1'
+**/
+  UINT8                       FirstDimmBitMask;
+
+/** Offset 0x0B07 - SAGV Switch Factor IA DDR BW
+  SAGV Switch Factor IA DDR BW: IA DDR load percentage when system switch to high
+  SAGV point from 1 to 50%.
+**/
+  UINT8                       SagvSwitchFactorIA;
+
+/** Offset 0x0B08 - SAGV Switch Factor GT DDR BW
+  SAGV Switch Factor GT DDR BW: GT DDR load percentage when system switch to high
+  SAGV point from 1 to 50%.
+**/
+  UINT8                       SagvSwitchFactorGT;
+
+/** Offset 0x0B09 - SAGV Switch Factor IO DDR BW
+  SAGV Switch Factor IO DDR BW: IO DDR load percentage when system switch to high
+  SAGV point from 1 to 50%.
+**/
+  UINT8                       SagvSwitchFactorIO;
+
+/** Offset 0x0B0A - SAGV Switch Factor IA and GT Stall
+  SAGV Switch Factor IA and GT Stall: IA and GT percentage when system switch to high
+  SAGV point from 1 to 50%.
+**/
+  UINT8                       SagvSwitchFactorStall;
+
+/** Offset 0x0B0B - Threshold For Switch Down
+  SAGV heuristics down control: Duration in ms of low activity after which SAGV will
+  switch down, from 1 to 50ms.
+**/
+  UINT8                       SagvHeuristicsDownControl;
+
+/** Offset 0x0B0C - Threshold For Switch Up
+  SAGV heuristics up control: Duration in ms of low activity after which SAGV will
+  switch up, from 1 to 50ms.
+**/
+  UINT8                       SagvHeuristicsUpControl;
+
+/** Offset 0x0B0D
+**/
+  UINT8                       UnusedUpdSpace31;
+
+/** Offset 0x0B0E - Frequency Limit for Mixed 2DPC DDR5 1 Rank 8GB and 8GB
+  Frequency Limit for 2DPC Mixed or non-POR Config. 0: Auto, otherwise a frequency
+  in MT/s, default is 2000
+**/
+  UINT16                      FreqLimitMixedConfig_1R1R_8GB;
+
+/** Offset 0x0B10 - Frequency Limit for Mixed 2DPC DDR5 1 Rank 16GB and 16GB
+  Frequency Limit for 2DPC Mixed or non-POR Config. 0: Auto, otherwise a frequency
+  in MT/s, default is 2000
+**/
+  UINT16                      FreqLimitMixedConfig_1R1R_16GB;
+
+/** Offset 0x0B12 - Frequency Limit for Mixed 2DPC DDR5 1 Rank 8GB and 16GB
+  Frequency Limit for 2DPC Mixed or non-POR Config. 0: Auto, otherwise a frequency
+  in MT/s, default is 2000
+**/
+  UINT16                      FreqLimitMixedConfig_1R1R_8GB_16GB;
+
+/** Offset 0x0B14 - Frequency Limit for Mixed 2DPC DDR5 2 Rank
+  Frequency Limit for 2DPC Mixed or non-POR Config. 0: Auto, otherwise a frequency
+  in MT/s, default is 2000
+**/
+  UINT16                      FreqLimitMixedConfig_2R2R;
+
+/** Offset 0x0B16 - DMI Hw Eq Gen3 CoeffList Cm
+  PCH_DMI_EQ_PARAM. Coefficient C-1.
+**/
+  UINT8                       PchDmiHwEqGen3CoeffListCm[8];
+
+/** Offset 0x0B1E - DMI Hw Eq Gen3 CoeffList Cp
+  PCH_DMI_EQ_PARAM. Coefficient C+1.
+**/
+  UINT8                       PchDmiHwEqGen3CoeffListCp[8];
+
+/** Offset 0x0B26 -  LCT Command eyewidth
+   LCT Command eyewidth. 0: Auto, otherwise eyewidth , default is 96
+**/
+  UINT16                      LctCmdEyeWidth;
+
+/** Offset 0x0B28 - For LPDDR Only: Throttler CKEMin Timer
+  For LPDDR Only: Timer value for CKEMin, range[255;0]. Reqd min of SC_ROUND_T + BYTE_LENGTH
+  (4). Dfault is 0x00
+**/
+  UINT8                       ThrtCkeMinTmrLpddr;
+
+/** Offset 0x0B29 - First ECC Dimm BitMask
+  Defines which ECC DIMM should be populated first on a 2DPC board. Bit0: MC0 DIMM0,
+  Bit1: MC0 DIMM1, Bit2: MC1 DIMM0, Bit3: MC1 DIMM1. For each MC, the first DIMM
+  to be populated should be set to '1'
+**/
+  UINT8                       FirstDimmBitMaskEcc;
 
 /** Offset 0x0B2A -  LP5 Bank Mode
   LP5 Bank Mode. 0: Auto, 1: 8 Bank Mode, 2: 16 Bank Mode, 3: BG Mode, default is 0
@@ -3209,9 +3991,31 @@ typedef struct {
 **/
   UINT8                       Lp5BankMode;
 
-/** Offset 0x0B2B - Reserved
+/** Offset 0x0B2B - Write DS Training
+  Enable/Disable Write DS Training
+  $EN_DIS
 **/
-  UINT8                       Reserved46[13];
+  UINT8                       WRDS;
+
+/** Offset 0x0B2C - SAM Overlaoding
+  Enable: copy the sagv frequency point. Disable: not copy.
+  $EN_DIS
+**/
+  UINT8                       OverloadSAM;
+
+/** Offset 0x0B2D - Time Measure
+  Time Measure: 0(Default)=Disable, 1=Enable
+  $EN_DIS
+**/
+  UINT8                       MrcTimeMeasure;
+
+/** Offset 0x0B2E
+**/
+  UINT8                       UnusedUpdSpace32[5];
+
+/** Offset 0x0B33
+**/
+  UINT8                       ReservedFspmUpd2[5];
 } FSP_M_CONFIG;
 
 /** Fsp M UPD Configuration
diff --git a/src/vendorcode/intel/fsp/fsp2_0/twinlake/FspsUpd.h b/src/vendorcode/intel/fsp/fsp2_0/twinlake/FspsUpd.h
index b5e96c1846..96e4686009 100644
--- a/src/vendorcode/intel/fsp/fsp2_0/twinlake/FspsUpd.h
+++ b/src/vendorcode/intel/fsp/fsp2_0/twinlake/FspsUpd.h
@@ -1,6 +1,6 @@
 /** @file
 
-Copyright (c) 2022 - 2024, Intel Corporation. All rights reserved.<BR>
+Copyright (c) 2025, Intel Corporation. All rights reserved.<BR>
 
 Redistribution and use in source and binary forms, with or without modification,
 are permitted provided that the following conditions are met:
@@ -123,9 +123,9 @@ typedef struct {
 **/
   UINT8                       ShowSpiController;
 
-/** Offset 0x0056 - Reserved
+/** Offset 0x0056
 **/
-  UINT8                       Reserved0[2];
+  UINT8                       UnusedUpdSpace0[2];
 
 /** Offset 0x0058 - MicrocodeRegionBase
   Memory Base of Microcode Updates
@@ -161,9 +161,14 @@ typedef struct {
 **/
   UINT8                       SataPortsDevSlp[8];
 
-/** Offset 0x0072 - Reserved
+/** Offset 0x0072
 **/
-  UINT8                       Reserved1[34];
+  UINT8                       UnusedUpdSpace1[2];
+
+/** Offset 0x0074 - SATA DEVSLP GPIO Pin
+  Select SATA DEVSLP Pin. Refer to GPIO_*_MUXING_SATA_DEVSLP_x* for possible values.
+**/
+  UINT32                      SataPortDevSlpPinMux[8];
 
 /** Offset 0x0094 - Enable USB2 ports
   Enable/disable per USB2 ports. One byte for each port, byte0 for port0, byte1 for
@@ -183,9 +188,9 @@ typedef struct {
 **/
   UINT8                       XdciEnable;
 
-/** Offset 0x00AF - Reserved
+/** Offset 0x00AF
 **/
-  UINT8                       Reserved2;
+  UINT8                       UnusedUpdSpace2;
 
 /** Offset 0x00B0 - Address of PCH_DEVICE_INTERRUPT_CONFIG table.
   The address of the table of PCH_DEVICE_INTERRUPT_CONFIG.
@@ -231,9 +236,9 @@ typedef struct {
 **/
   UINT8                       PchHdaVerbTableEntryNum;
 
-/** Offset 0x00C2 - Reserved
+/** Offset 0x00C2
 **/
-  UINT8                       Reserved3[2];
+  UINT8                       UnusedUpdSpace3[2];
 
 /** Offset 0x00C4 - PCH HDA Verb Table Pointer
   Pointer to Array of pointers to Verb Table.
@@ -299,9 +304,9 @@ typedef struct {
 **/
   UINT8                       SerialIoUartMode[7];
 
-/** Offset 0x010A - Reserved
+/** Offset 0x010A
 **/
-  UINT8                       Reserved4[2];
+  UINT8                       UnusedUpdSpace4[2];
 
 /** Offset 0x010C - Default BaudRate for each Serial IO UART
   Set default BaudRate Supported from 0 - default to 6000000
@@ -339,9 +344,9 @@ typedef struct {
 **/
   UINT8                       SerialIoUartAutoFlow[7];
 
-/** Offset 0x0152 - Reserved
+/** Offset 0x0152
 **/
-  UINT8                       Reserved5[2];
+  UINT8                       UnusedUpdSpace5[2];
 
 /** Offset 0x0154 - SerialIoUartRtsPinMuxPolicy
   Select SerialIo Uart Rts pin muxing. Refer to GPIO_*_MUXING_SERIALIO_UARTx_RTS*
@@ -654,9 +659,19 @@ typedef struct {
 **/
   UINT8                       PchTsnLinkSpeed;
 
-/** Offset 0x038F - Reserved
+/** Offset 0x038F
 **/
-  UINT8                       Reserved6[9];
+  UINT8                       UnusedUpdSpace6;
+
+/** Offset 0x0390 - PCH TSN MAC Address High Bits
+  Set TSN MAC Address High.
+**/
+  UINT32                      PchTsnMacAddressHigh;
+
+/** Offset 0x0394 - PCH TSN MAC Address Low Bits
+  Set TSN MAC Address Low.
+**/
+  UINT32                      PchTsnMacAddressLow;
 
 /** Offset 0x0398 - PCIe PTM enable/disable
   Enable/disable Precision Time Measurement for PCIE Root Ports.
@@ -680,9 +695,9 @@ typedef struct {
 **/
   UINT8                       UsbPdoProgramming;
 
-/** Offset 0x03ED - Reserved
+/** Offset 0x03ED
 **/
-  UINT8                       Reserved7[3];
+  UINT8                       UnusedUpdSpace7[3];
 
 /** Offset 0x03F0 - Power button debounce configuration
   Debounce time for PWRBTN in microseconds. For values not supported by HW, they will
@@ -733,9 +748,9 @@ typedef struct {
 **/
   UINT8                       PchFivrExtVnnRailSupportedVoltageStates;
 
-/** Offset 0x03FD - Reserved
+/** Offset 0x03FD
 **/
-  UINT8                       Reserved8;
+  UINT8                       UnusedUpdSpace8;
 
 /** Offset 0x03FE - External Vnn Voltage Value that will be used in S0ix/Sx states
   Value is given in 2.5mV increments (0=0mV, 1=2.5mV, 2=5mV...), Default is set to 420
@@ -795,9 +810,9 @@ typedef struct {
 **/
   UINT8                       PmcDbgMsgEn;
 
-/** Offset 0x040B - Reserved
+/** Offset 0x040B
 **/
-  UINT8                       Reserved9;
+  UINT8                       UnusedUpdSpace9;
 
 /** Offset 0x040C - Pointer of ChipsetInit Binary
   ChipsetInit Binary Pointer.
@@ -844,9 +859,9 @@ typedef struct {
 **/
   UINT8                       PchSpiExtendedBiosDecodeRangeEnable;
 
-/** Offset 0x041D - Reserved
+/** Offset 0x041D
 **/
-  UINT8                       Reserved10[3];
+  UINT8                       UnusedUpdSpace10[3];
 
 /** Offset 0x0420 - Extended BIOS Direct Read Decode Range base
   Bits of 31:16 of a memory address that'll be a base for Extended BIOS Direct Read Decode.
@@ -858,9 +873,25 @@ typedef struct {
 **/
   UINT32                      PchSpiExtendedBiosDecodeRangeLimit;
 
-/** Offset 0x0428 - Reserved
+/** Offset 0x0428 - USB Audio Offload enable
+  Enable/Disable USB Audio Offload capabilites. 0: disabled, 1: enabled (default)
+  $EN_DIS
 **/
-  UINT8                       Reserved11[12];
+  UINT8                       PchXhciUaolEnable;
+
+/** Offset 0x0429
+**/
+  UINT8                       UnusedUpdSpace11[3];
+
+/** Offset 0x042C - Pointer of SYNPS PHY Binary
+  ChipsetInit Binary Pointer.
+**/
+  UINT32                      SynpsPhyBinPtr;
+
+/** Offset 0x0430 - Length of SYNPS PHY Binary
+  ChipsetInit Binary Length.
+**/
+  UINT32                      SynpsPhyBinLen;
 
 /** Offset 0x0434 - CNVi Configuration
   This option allows for automatic detection of Connectivity Solution. [Auto Detection]
@@ -989,9 +1020,9 @@ typedef struct {
 **/
   UINT8                       AmtSolEnabled;
 
-/** Offset 0x0455 - Reserved
+/** Offset 0x0455
 **/
-  UINT8                       Reserved12;
+  UINT8                       UnusedUpdSpace12;
 
 /** Offset 0x0456 - OS Timer
   16 bits Value, Set OS watchdog timer. Setting is invalid if AmtEnabled is 0.
@@ -1025,9 +1056,9 @@ typedef struct {
 **/
   UINT8                       PcieRpEnableCpm[28];
 
-/** Offset 0x04AF - Reserved
+/** Offset 0x04AF
 **/
-  UINT8                       Reserved13;
+  UINT8                       UnusedUpdSpace13[1];
 
 /** Offset 0x04B0 - PCIE RP Detect Timeout Ms
   The number of milliseconds within 0~65535 in reference code will wait for link to
@@ -1136,9 +1167,27 @@ typedef struct {
 **/
   UINT8                       LidStatus;
 
-/** Offset 0x0521 - Reserved
+/** Offset 0x0521 - Set Iom stay in TC cold seconds in TCSS
+  Set Iom stay in TC cold seconds in IOM
 **/
-  UINT8                       Reserved14[8];
+  UINT8                       IomStayInTCColdSeconds;
+
+/** Offset 0x0522 - Set Iom before entering TC cold seconds in TCSS
+  Set Iom before entering TC cold seconds in IOM
+**/
+  UINT8                       IomBeforeEnteringTCColdSeconds;
+
+/** Offset 0x0523 - SaPostMemRsvd
+  Reserved for PCH Post-Mem
+  $EN_DIS
+**/
+  UINT8                       SaPostMemRsvd[5];
+
+/** Offset 0x0528 - PCH xHCI enable HS Interrupt IN Alarm
+  PCH xHCI enable HS Interrupt IN Alarm. 0: disabled (default), 1: enabled
+  $EN_DIS
+**/
+  UINT8                       PchXhciHsiiEnable;
 
 /** Offset 0x0529 - Enable VMD controller
   Enable/disable to VMD controller.0: Disable; 1: Enable(Default)
@@ -1195,9 +1244,9 @@ typedef struct {
 **/
   UINT8                       VmdMemBar2Attr;
 
-/** Offset 0x058D - Reserved
+/** Offset 0x058D
 **/
-  UINT8                       Reserved15[3];
+  UINT8                       UnusedUpdSpace14[3];
 
 /** Offset 0x0590 - VMD Variable
   VMD Variable Pointer.
@@ -1219,9 +1268,12 @@ typedef struct {
 **/
   UINT32                      VmdMemBar2Base;
 
-/** Offset 0x05A0 - Reserved
+/** Offset 0x05A0 - TCSS CPU USB PDO Programming
+  Enable/disable PDO programming for TCSS CPU USB in PEI phase. Disabling will allow
+  for programming during later phase. 1: enable, 0: disable
+  $EN_DIS
 **/
-  UINT8                       Reserved16;
+  UINT8                       TcssCpuUsbPdoProgramming;
 
 /** Offset 0x05A1 - Enable/Disable PMC-PD Solution
   This policy will enable/disable PMC-PD Solution vs EC-TCPC Solution
@@ -1274,18 +1326,20 @@ typedef struct {
 **/
   UINT8                       VccSt;
 
-/** Offset 0x05B1 - Reserved
+/** Offset 0x05B1
 **/
-  UINT8                       Reserved17;
+  UINT8                       UnusedUpdSpace15[1];
 
 /** Offset 0x05B2 - ITBT DMA LTR
   TCSS DMA1, DMA2 LTR value
 **/
   UINT16                      ITbtDmaLtr[2];
 
-/** Offset 0x05B6 - Reserved
+/** Offset 0x05B6 - Enable/Disable CrashLog
+  Enable(Default): Enable CPU CrashLog, Disable: Disable CPU CrashLog
+  $EN_DIS
 **/
-  UINT8                       Reserved18;
+  UINT8                       CpuCrashLogEnable;
 
 /** Offset 0x05B7 - Enable/Disable PTM
   This policy will enable/disable Precision Time Measurement for TCSS PCIe Root Ports
@@ -1308,9 +1362,9 @@ typedef struct {
 **/
   UINT8                       SaPcieItbtRpSnoopLatencyOverrideMultiplier[4];
 
-/** Offset 0x05C7 - Reserved
+/** Offset 0x05C7
 **/
-  UINT8                       Reserved19;
+  UINT8                       UnusedUpdSpace16[1];
 
 /** Offset 0x05C8 - PCIE RP Snoop Latency Override Value
   Latency Tolerance Reporting, Snoop Latency Override Value.
@@ -1360,9 +1414,9 @@ typedef struct {
 **/
   UINT8                       Psi4Enable[5];
 
-/** Offset 0x05F3 - Reserved
+/** Offset 0x05F3
 **/
-  UINT8                       Reserved20;
+  UINT8                       UnusedUpdSpace17[1];
 
 /** Offset 0x05F4 - Imon slope correction
   PCODE MMIO Mailbox: Imon slope correction. Specified in 1/100 increment values.
@@ -1387,9 +1441,9 @@ typedef struct {
 **/
   UINT8                       TdcEnable[5];
 
-/** Offset 0x0612 - Reserved
+/** Offset 0x0612
 **/
-  UINT8                       Reserved21[2];
+  UINT8                       UnusedUpdSpace18[2];
 
 /** Offset 0x0614 - Thermal Design Current time window
   PCODE MMIO Mailbox: Thermal Design Current time window. Defined in milli seconds.
@@ -1436,9 +1490,9 @@ typedef struct {
 **/
   UINT8                       SlowSlewRate[5];
 
-/** Offset 0x063B - Reserved
+/** Offset 0x063B
 **/
-  UINT8                       Reserved22;
+  UINT8                       UnusedUpdSpace19[1];
 
 /** Offset 0x063C - Thermal Design Current current limit
   PCODE MMIO Mailbox: Thermal Design Current current limit. Specified in 1/8A units.
@@ -1505,9 +1559,9 @@ typedef struct {
 **/
   UINT8                       FivrSpreadSpectrum;
 
-/** Offset 0x0687 - Reserved
+/** Offset 0x0687
 **/
-  UINT8                       Reserved23;
+  UINT8                       UnusedUpdSpace20;
 
 /** Offset 0x0688 - CpuBistData
   Pointer CPU BIST Data
@@ -1542,9 +1596,9 @@ typedef struct {
 **/
   UINT8                       RampDown;
 
-/** Offset 0x0693 - Reserved
+/** Offset 0x0693
 **/
-  UINT8                       Reserved24;
+  UINT8                       UnusedUpdSpace21[1];
 
 /** Offset 0x0694 - VR Voltage Limit
   PCODE MMIO Mailbox: Voltage Limit. Range is 0 - 7999mV
@@ -1557,9 +1611,40 @@ typedef struct {
 **/
   UINT16                      VccInAuxImonIccImax;
 
-/** Offset 0x06A0 - Reserved
+/** Offset 0x06A0 - Vsys Critical
+  PCODE MMIO Mailbox: Vsys Critical. <b>0: Disable</b>; 1: Enable Range is 0-255.
 **/
-  UINT8                       Reserved25[7];
+  UINT8                       EnableVsysCritical;
+
+/** Offset 0x06A1 - Vsys Full Scale
+  DEPRECATED
+**/
+  UINT8                       VsysFullScale;
+
+/** Offset 0x06A2 - Vsys Critical Threshold
+  DEPRECATED
+**/
+  UINT8                       VsysCriticalThreshold;
+
+/** Offset 0x06A3 - Assertion Deglitch Mantissa
+  Assertion Deglitch Mantissa, Range is 0-255
+**/
+  UINT8                       VsysAssertionDeglitchMantissa;
+
+/** Offset 0x06A4 - Assertion Deglitch Exponent
+  Assertion Deglitch Exponent, Range is 0-255
+**/
+  UINT8                       VsysAssertionDeglitchExponent;
+
+/** Offset 0x06A5 - De assertion Deglitch Mantissa
+  De assertion Deglitch Mantissa, Range is 0-255
+**/
+  UINT8                       VsysDeassertionDeglitchMantissa;
+
+/** Offset 0x06A6 - De assertion Deglitch Exponent
+  De assertion Deglitch Exponent, Range is 0-255
+**/
+  UINT8                       VsysDeassertionDeglitchExponent;
 
 /** Offset 0x06A7 - VccIn Aux Imon slope correction
   PCODE MMIO Mailbox: VccIn Aux Imon slope correction. <b>0 - Auto</b> Specified in
@@ -1567,18 +1652,30 @@ typedef struct {
 **/
   UINT8                       VccInAuxImonSlope;
 
-/** Offset 0x06A8 - Reserved
+/** Offset 0x06A8 - VccIn Aux Imon offset correction
+  PCODE MMIO Mailbox: VccIn Aux Imon offset correction. <b>0 - Auto</b> Units 1/1000,
+  Range 0-63999. For an offset of 25.348, enter 25348.
 **/
-  UINT8                      Reserved26[2];
+  UINT16                      VccInAuxImonOffset;
 
 /** Offset 0x06AA - FIVR RFI Spread Spectrum Enable or disable
   Enable or Disable FIVR RFI Spread Spectrum. 0: Disable ; <b> 1: Enable </b>
 **/
   UINT8                       FivrSpectrumEnable;
 
-/** Offset 0x06AB - Reserved
+/** Offset 0x06AB
 **/
-  UINT8                       Reserved27[13];
+  UINT8                       UnusedUpdSpace22[1];
+
+/** Offset 0x06AC - VR Fast Vmode ICC Limit support
+  PCODE MMIO Mailbox: The non-zero value will only be effective by setting the corresponding
+  EnableFastVmode to 1. 0-510A in 1/4 A units. 400 = 100A
+**/
+  UINT16                      IccLimit[5];
+
+/** Offset 0x06B6
+**/
+  UINT8                       CpuPostMemRsvd[2];
 
 /** Offset 0x06B8 - PpinSupport to view Protected Processor Inventory Number
   Enable or Disable or Auto (Based on End of Manufacturing flag. Disabled if this
@@ -1599,9 +1696,17 @@ typedef struct {
 **/
   UINT16                      MinVoltageRuntime;
 
-/** Offset 0x06BC - Reserved
+/** Offset 0x06BC - Memory size per thread allocated for Processor Trace
+  Memory size per thread for Processor Trace. Processor Trace requires 2^N alignment
+  and size in bytes per thread, from 4KB to 128MB.\n
+  <b> 0xff:none </b>, 0:4k, 0x1:8k, 0x2:16k, 0x3:32k, 0x4:64k, 0x5:128k, 0x6:256k,
+  0x7:512k, 0x8:1M, 0x9:2M, 0xa:4M. 0xb:8M, 0xc:16M, 0xd:32M, 0xe:64M, 0xf:128M
 **/
-  UINT8                       Reserved28[2];
+  UINT8                       ProcessorTraceMemSize;
+
+/** Offset 0x06BD
+**/
+  UINT8                       UnusedUpdSpace23;
 
 /** Offset 0x06BE - Min Voltage for C8
   PCODE MMIO Mailbox: Minimum voltage for C8. Valid if EnableMinVoltageOverride =
@@ -1633,9 +1738,11 @@ typedef struct {
 **/
   UINT8                       Avx3Disable;
 
-/** Offset 0x06C9 - Reserved
+/** Offset 0x06C9 - X2ApicSupport
+  Enable or Disable X2APIC Support
+  $EN_DIS
 **/
-  UINT8                       Reserved29;
+  UINT8                       X2ApicSupport;
 
 /** Offset 0x06CA - CPU VR Power Delivery Design
   Used to communicate the power delivery design capability of the board. This value
@@ -1644,9 +1751,38 @@ typedef struct {
 **/
   UINT8                       VrPowerDeliveryDesign;
 
-/** Offset 0x06CB - Reserved
+/** Offset 0x06CB - Enable/Disable VR FastVmode. The VR will initiate reactive protection if Fast Vmode is enabled.
+  Enable/Disable VR FastVmode; The value will only be effective by enabling the corresponding
+  CEP.<b>0: Disable</b>; 1: Enable.For all VR by domain
+  0: Disable, 1: Enable
 **/
-  UINT8                       Reserved30[32];
+  UINT8                       EnableFastVmode[5];
+
+/** Offset 0x06D0 - Vsys Full Scale
+  Vsys Full Scale, Range is 0-255000mV
+**/
+  UINT32                      VsysFullScale1;
+
+/** Offset 0x06D4 - Vsys Critical Threshold
+  Vsys Critical Threshold, Range is 0-255000mV
+**/
+  UINT32                      VsysCriticalThreshold1;
+
+/** Offset 0x06D8 - Psys Full Scale
+  Vsys Full Scale, Range is 0-255000mV
+**/
+  UINT32                      PsysFullScale;
+
+/** Offset 0x06DC - Psys Critical Threshold
+  Vsys Critical Threshold, Range is 0-255000mV
+**/
+  UINT32                      PsysCriticalThreshold;
+
+/** Offset 0x06E0 - ReservedCpuPostMemProduction
+  Reserved for CPU Post-Mem Production
+  $EN_DIS
+**/
+  UINT8                       ReservedCpuPostMemProduction[11];
 
 /** Offset 0x06EB - Enable Power Optimizer
   Enable DMI Power Optimizer on PCH side.
@@ -1838,9 +1974,12 @@ typedef struct {
 **/
   UINT32                      ThcPort0InterruptPinMuxing;
 
-/** Offset 0x0894 - Reserved
+/** Offset 0x0894 - Touch Host Controller Port 0 Wake On Touch
+  Based on this setting vGPIO for given THC will be in native mode, and additional
+  _CRS for wake will be exposed in ACPI
+  $EN_DIS
 **/
-  UINT8                       Reserved31;
+  UINT8                       ThcPort0WakeOnTouch;
 
 /** Offset 0x0895 - Touch Host Controller Port 1 Assignment
   Assign THC Port 1
@@ -1848,9 +1987,10 @@ typedef struct {
 **/
   UINT8                       ThcPort1Assignment;
 
-/** Offset 0x0896 - Reserved
+/** Offset 0x0896 - Touch Host Controller Port 1 Hid Over Spi Reset Sequencing Delay [ms]
+  Policy control for reset sequencing delay (ACPI _INI, _RST) default 300ms
 **/
-  UINT8                      Reserved32[2];
+  UINT16                      ThcPort1HidResetSequencingDelay;
 
 /** Offset 0x0898 - Touch Host Controller Port 1 Interrupt Pin Mux
   Set THC Port 1 Pin Muxing Value if signal can be enabled on multiple pads. Refer
@@ -1858,9 +1998,12 @@ typedef struct {
 **/
   UINT32                      ThcPort1InterruptPinMuxing;
 
-/** Offset 0x089C - Reserved
+/** Offset 0x089C - Touch Host Controller Port 1 Wake On Touch
+  Based on this setting vGPIO for given THC will be in native mode, and additional
+  _CRS for wake will be exposed in ACPI
+  $EN_DIS
 **/
-  UINT8                       Reserved33;
+  UINT8                       ThcPort1WakeOnTouch;
 
 /** Offset 0x089D - PCIE RP Pcie Speed
   Determines each PCIE Port speed capability. 0: Auto; 1: Gen1; 2: Gen2; 3: Gen3;
@@ -1890,9 +2033,10 @@ typedef struct {
 **/
   UINT8                       PcieRpL1Substates[28];
 
-/** Offset 0x0929 - Reserved
+/** Offset 0x0929 - PCIE RP L1 Low Substate
+  The L1 Low Substate configuration of the root port. 0: Disable; 1: Enable.
 **/
-  UINT8                       Reserved34[28];
+  UINT8                       PcieRpL1Low[28];
 
 /** Offset 0x0945 - PCIE RP Ltr Enable
   Latency Tolerance Reporting Mechanism.
@@ -1948,9 +2092,14 @@ typedef struct {
 **/
   UINT8                       PcieEqPh3PresetList[11];
 
-/** Offset 0x09A1 - Reserved
+/** Offset 0x09A1
 **/
-  UINT8                       Reserved35[3];
+  UINT8                       UnusedUpdSpace24;
+
+/** Offset 0x09A2 - Touch Host Controller Port 0 Hid Over Spi Reset Sequencing Delay [ms]
+  Policy control for reset sequencing delay (ACPI _INI, _RST) default 300ms
+**/
+  UINT16                      ThcPort0HidResetSequencingDelay;
 
 /** Offset 0x09A4 - PCIe EQ phase 1 downstream transmitter port preset
   Allows to select the downstream port preset value that will be used during phase
@@ -2226,8 +2375,7 @@ typedef struct {
   UINT8                       SataRstPcieDeviceResetDelay[3];
 
 /** Offset 0x0A42 - UFS enable/disable
-  Enable/Disable UFS controller, One byte for each Controller - (1,0) to enable controller
-  0 and (0,1) to enable controller 1
+  PCIe Storage Device Reset Delay in milliseconds. Default value is 100ms
   $EN_DIS
 **/
   UINT8                       UfsEnable[2];
@@ -2238,9 +2386,9 @@ typedef struct {
 **/
   UINT8                       IehMode;
 
-/** Offset 0x0A45 - Reserved
+/** Offset 0x0A45
 **/
-  UINT8                       Reserved36;
+  UINT8                       UnusedUpdSpace25;
 
 /** Offset 0x0A46 - Thermal Throttling Custimized T0Level Value
   Custimized T0Level value.
@@ -2413,9 +2561,9 @@ typedef struct {
 **/
   UINT8                       PchMemoryPinSelection[2];
 
-/** Offset 0x0A6B - Reserved
+/** Offset 0x0A6B
 **/
-  UINT8                       Reserved37;
+  UINT8                       UnusedUpdSpace26;
 
 /** Offset 0x0A6C - Thermal Device Temperature
   Decides the temperature.
@@ -2438,9 +2586,14 @@ typedef struct {
 **/
   UINT8                       PchUsbLtrOverrideEnable;
 
-/** Offset 0x0A89 - Reserved
+/** Offset 0x0A89 - Touch Host Controller Mode
+  Switch between Intel THC protocol and Industry standard HID Over SPI protocol. 0x0:Thc, 0x1:Hid
 **/
-  UINT8                       Reserved38[3];
+  UINT8                       ThcMode[2];
+
+/** Offset 0x0A8B
+**/
+  UINT8                       UnusedUpdSpace27;
 
 /** Offset 0x0A8C - xHCI High Idle Time LTR override
   Value used for overriding LTR recommendation for xHCI High Idle Time LTR setting
@@ -2488,9 +2641,26 @@ typedef struct {
 **/
   UINT8                       HybridStorageMode;
 
-/** Offset 0x0A9C - Reserved
+/** Offset 0x0A9C - CPU Root Port used for Hybrid Storage
+  Specifies the CPU root port used for Hybrid storage.
 **/
-  UINT8                       Reserved39[4];
+  UINT8                       CpuRootportUsedForHybridStorage;
+
+/** Offset 0x0A9D - PCH Root Port used for Hybrid Storage when two lanes are connected to CPU
+  Specifies PCH Root Port used for Hybrid Storage when two lanes are connected to CPU.
+**/
+  UINT8                       PchRootportUsedForCpuAttach;
+
+/** Offset 0x0A9E - PCH GPE event handler
+  Enabled _L6D ACPI handler. PME GPE is shared by multiple devices So BIOS must verify
+  the same in the ASL handler by reading offset for PMEENABLE and PMESTATUS bit
+  $EN_DIS
+**/
+  UINT8                       PchAcpiL6dPmeHandling;
+
+/** Offset 0x0A9F
+**/
+  UINT8                       UnusedUpdSpace28[1];
 
 /** Offset 0x0AA0 - BgpdtHash[4]
   BgpdtHash values
@@ -2502,9 +2672,9 @@ typedef struct {
 **/
   UINT32                      BiosGuardAttr;
 
-/** Offset 0x0AC4 - Reserved
+/** Offset 0x0AC4
 **/
-  UINT8                       Reserved40[4];
+  UINT8                       UnusedUpdSpace29[4];
 
 /** Offset 0x0AC8 - BiosGuardModulePtr
   BiosGuardModulePtr default values
@@ -2535,9 +2705,9 @@ typedef struct {
 **/
   UINT8                       SiSkipSsidProgramming;
 
-/** Offset 0x0ADB - Reserved
+/** Offset 0x0ADB
 **/
-  UINT8                       Reserved41;
+  UINT8                       UnusedUpdSpace30;
 
 /** Offset 0x0ADC - Change Default SVID
   Change the default SVID used in FSP to programming internal devices. This is only
@@ -2635,9 +2805,48 @@ typedef struct {
 **/
   UINT8                       PchPmLatchEventsC10Exit;
 
-/** Offset 0x0B00 - Reserved
+/** Offset 0x0B00 - PMC ADR enable
+  Enable/disable asynchronous DRAM refresh
+  $EN_DIS
 **/
-  UINT8                       Reserved42[12];
+  UINT8                       PmcAdrEn;
+
+/** Offset 0x0B01 - PMC ADR timer configuration enable
+  Enable/disable ADR timer configuration
+  $EN_DIS
+**/
+  UINT8                       PmcAdrTimerEn;
+
+/** Offset 0x0B02 - PMC ADR phase 1 timer value
+  Enable/disable ADR timer configuration
+**/
+  UINT8                       PmcAdrTimer1Val;
+
+/** Offset 0x0B03 - PMC ADR phase 1 timer multiplier value
+  Specify the multiplier value for phase 1 ADR timer
+**/
+  UINT8                       PmcAdrMultiplier1Val;
+
+/** Offset 0x0B04 - PMC ADR host reset partition enable
+  Specify whether PMC should set ADR_RST_STS bit after receiving Reset_Warn_Ack DMI message
+  $EN_DIS
+**/
+  UINT8                       PmcAdrHostPartitionReset;
+
+/** Offset 0x0B05 - PMC ADR source select override enable
+  Tells the FSP to update the source select with platform value
+  $EN_DIS
+**/
+  UINT8                       PmcAdrSrcOverride;
+
+/** Offset 0x0B06
+**/
+  UINT8                       UnusedUpdSpace31[2];
+
+/** Offset 0x0B08 - PMC ADR source selection
+  Specify which sources should cause ADR flow
+**/
+  UINT32                      PmcAdrSrcSel;
 
 /** Offset 0x0B0C - PCIE Eq Ph3 Lane Param Cm
   CPU_PCIE_EQ_LANE_PARAM. Coefficient C-1.
@@ -2728,9 +2937,9 @@ typedef struct {
 **/
   UINT8                       CpuPcieSlotSelection;
 
-/** Offset 0x0BD1 - Reserved
+/** Offset 0x0BD1
 **/
-  UINT8                       Reserved43[3];
+  UINT8                       UnusedUpdSpace32[3];
 
 /** Offset 0x0BD4 - CPU PCIE device override table pointer
   The PCIe device table is being used to override PCIe device ASPM settings. This
@@ -3005,9 +3214,9 @@ typedef struct {
 **/
   UINT8                       PchTsnMultiVcEnable;
 
-/** Offset 0x0CA2 - Reserved
+/** Offset 0x0CA2
 **/
-  UINT8                       Reserved44[2];
+  UINT8                       UnusedUpdSpace33[2];
 
 /** Offset 0x0CA4 - LogoPixelHeight Address
   Address of LogoPixelHeight
@@ -3024,9 +3233,17 @@ typedef struct {
 **/
   UINT8                       Usb4CmMode;
 
-/** Offset 0x0CAD - Reserved
+/** Offset 0x0CAD - PCIE Resizable BAR Support
+  Enable/Disable PCIE Resizable BAR Support.0: Disable; 1: Enable; 2: Auto(Default).
+  $EN_DIS
 **/
-  UINT8                       Reserved45[4];
+  UINT8                       CpuPcieResizableBarSupport;
+
+/** Offset 0x0CAE - SaPostMemTestRsvd
+  Reserved for SA Post-Mem Test
+  $EN_DIS
+**/
+  UINT8                       SaPostMemTestRsvd[3];
 
 /** Offset 0x0CB1 - RSR feature
   Enable or Disable RSR feature; 0: Disable; <b>1: Enable </b>
@@ -3034,9 +3251,11 @@ typedef struct {
 **/
   UINT8                       EnableRsr;
 
-/** Offset 0x0CB2 - Reserved
+/** Offset 0x0CB2 - ReservedCpuPostMem1
+  Reserved for CPU Post-Mem 1
+  $EN_DIS
 **/
-  UINT8                       Reserved46[4];
+  UINT8                       ReservedCpuPostMem1[4];
 
 /** Offset 0x0CB6 - Enable or Disable HWP
   Enable or Disable HWP(Hardware P states) Support. 0: Disable; <b>1: Enable;</b>
@@ -3427,9 +3646,9 @@ typedef struct {
 **/
   UINT8                       StateRatioMax16[16];
 
-/** Offset 0x0D2D - Reserved
+/** Offset 0x0D2D
 **/
-  UINT8                       Reserved47;
+  UINT8                       UnusedUpdSpace34;
 
 /** Offset 0x0D2E - Platform Power Pmax
   PCODE MMIO Mailbox: Platform Power Pmax. <b>0 - Auto</b> Specified in 1/8 Watt increments.
@@ -3467,9 +3686,9 @@ typedef struct {
 **/
   UINT16                      CstateLatencyControl5Irtl;
 
-/** Offset 0x0D3A - Reserved
+/** Offset 0x0D3A
 **/
-  UINT8                       Reserved48[2];
+  UINT8                       UnusedUpdSpace35[2];
 
 /** Offset 0x0D3C - Package Long duration turbo mode power limit
   Package Long duration turbo mode power limit. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.
@@ -3570,9 +3789,11 @@ typedef struct {
 **/
   UINT8                       HwpInterruptControl;
 
-/** Offset 0x0D73 - Reserved
+/** Offset 0x0D73 - ReservedCpuPostMem2
+  Reserved for CPU Post-Mem 2
+  $EN_DIS
 **/
-  UINT8                       Reserved49[4];
+  UINT8                       ReservedCpuPostMem2[4];
 
 /** Offset 0x0D77 - Intel Turbo Boost Max Technology 3.0
   Intel Turbo Boost Max Technology 3.0. 0: Disabled; <b>1: Enabled</b>
@@ -3642,9 +3863,11 @@ typedef struct {
 **/
   UINT8                       ApplyConfigTdp;
 
-/** Offset 0x0D82 - Reserved
+/** Offset 0x0D82 - Misc Power Management MSR Lock
+  Lock Misc Power Management MSR. Enable/Disable; 0: Disable , <b> 1: Enable </b>
+  $EN_DIS
 **/
-  UINT8                       Reserved50;
+  UINT8                       HwpLock;
 
 /** Offset 0x0D83 - Dual Tau Boost
   Enable, Disable Dual Tau Boost feature. This is only applicable for Desktop; <b>0:
@@ -3653,9 +3876,33 @@ typedef struct {
 **/
   UINT8                       DualTauBoost;
 
-/** Offset 0x0D84 - Reserved
+/** Offset 0x0D84 - Is Battery Present
+  BatteryPresent Enable/Disable; <b>0: Disable</b> ; 1:Enable
+  $EN_DIS
 **/
-  UINT8                       Reserved51[32];
+  UINT8                       StepDownMode;
+
+/** Offset 0x0D85 - Platform ATX Telemetry Unit
+  Set ATX Telemetry Unit in Watts or Percentage; <b>0: Watts</b>; 1: Percent
+**/
+  UINT8                       PlatformAtxTelemetryUnit;
+
+/** Offset 0x0D86 - ProcHot Demotion Algorithm configuration
+  ProcHot Demotion Algorithm configuration. Hardware Default/Disable; 0: Disable;<b>
+  1: Hardware Default</b>
+  $EN_DIS
+**/
+  UINT8                       ProcHotDemotion;
+
+/** Offset 0x0D87 - ReservedCpuPostMemTest
+  Reserved for CPU Post-Mem Test
+  $EN_DIS
+**/
+  UINT8                       ReservedCpuPostMemTest[13];
+
+/** Offset 0x0D94
+**/
+  UINT8                       SecurityPostMemRsvd[16];
 
 /** Offset 0x0DA4 - End of Post message
   Test, Send End of Post message. Disable(0x0): Disable EOP message, Send in PEI(0x1):
@@ -3702,9 +3949,9 @@ typedef struct {
 **/
   UINT8                       PchSbAccessUnlock;
 
-/** Offset 0x0DAB - Reserved
+/** Offset 0x0DAB
 **/
-  UINT8                       Reserved52;
+  UINT8                       UnusedUpdSpace36[1];
 
 /** Offset 0x0DAC - PCIE RP Ltr Max Snoop Latency
   Latency Tolerance Reporting, Max Snoop Latency.
@@ -3854,12 +4101,18 @@ typedef struct {
 **/
   UINT8                       CpuPcieRpGen4Dptp[4];
 
-/** Offset 0x0F96 - Reserved
+/** Offset 0x0F96 - PCIE RP Upstream Port Transmiter Preset
+  Used during Gen5 Link Equalization. Used for all lanes.  Default is 7.
 **/
-  UINT8                       Reserved53[8];
+  UINT8                       CpuPcieRpGen5Uptp[4];
 
-/** Offset 0x0F9E - Type C Port x Convert to Type A
-  Enable / Disable (default) Type C Port x Convert to Type A
+/** Offset 0x0F9A - PCIE RP Downstream Port Transmiter Preset
+  Used during Gen5 Link Equalization. Used for all lanes.  Default is 7.
+**/
+  UINT8                       CpuPcieRpGen5Dptp[4];
+
+/** Offset 0x0F9E - Type C Port x Convert to TypeA
+  Enable / Disable(default) Type C Port x Convert to TypeA
   $EN_DIS
 **/
   UINT8                       EnableTcssCovTypeA[4];
@@ -3887,9 +4140,33 @@ typedef struct {
 **/
   UINT8                       CpuPcieRpPeerToPeerMode[4];
 
-/** Offset 0x0FAF - Reserved
+/** Offset 0x0FAF - Turbo Ratio Limit Ratio array
+  TurboRatioLimitRatio[7-0] will pair with TurboRatioLimitNumCore[7-0] to determine
+  the active core ranges for each frequency point.
 **/
-  UINT8                       Reserved54[33];
+  UINT8                       TurboRatioLimitRatio[8];
+
+/** Offset 0x0FB7 - Turbo Ratio Limit Num Core array
+  TurboRatioLimitNumCore[7-0] will pair with TurboRatioLimitRatio[7-0] to determine
+  the active core ranges for each frequency point.
+**/
+  UINT8                       TurboRatioLimitNumCore[8];
+
+/** Offset 0x0FBF - ATOM Turbo Ratio Limit Ratio array
+  AtomTurboRatioLimitRatio[7-0] will pair with AtomTurboRatioLimitNumCore[7-0] to
+  determine the active core ranges for each frequency point.
+**/
+  UINT8                       AtomTurboRatioLimitRatio[8];
+
+/** Offset 0x0FC7 - ATOM Turbo Ratio Limit Num Core array
+  AtomTurboRatioLimitNumCore[7-0] will pair with AtomTurboRatioLimitRatio[7-0] to
+  determine the active core ranges for each frequency point.
+**/
+  UINT8                       AtomTurboRatioLimitNumCore[8];
+
+/** Offset 0x0FCF
+**/
+  UINT8                       UnusedUpdSpace37;
 
 /** Offset 0x0FD0 - FspEventHandler
   <b>Optional</b> pointer to the boot loader's implementation of FSP_EVENT_HANDLER.
@@ -3914,9 +4191,9 @@ typedef struct {
 **/
   UINT8                       EmmcUseCustomDlls;
 
-/** Offset 0x0FD7 - Reserved
+/** Offset 0x0FD7
 **/
-  UINT8                       Reserved55;
+  UINT8                       UnusedUpdSpace38;
 
 /** Offset 0x0FD8 - Emmc Tx CMD Delay control register value
   Please see Tx CMD Delay Control register definition for help
@@ -3948,9 +4225,73 @@ typedef struct {
 **/
   UINT32                      EmmcRxStrobeDelayRegValue;
 
-/** Offset 0x0FF0 - Reserved
+/** Offset 0x0FF0 - Emmc Command Pin Mux
+  Select  pin muxing. Refer to GPIO_*_MUXING_EMMC_CMD* for possible values.
 **/
-  UINT8                      Reserved56[69];
+  UINT32                      EmmcGpioCmdPinMux;
+
+/** Offset 0x0FF4 - Emmc Command Pad Termination
+  0x0: Hardware default, 0x1: None, 0x13: 1kOhm weak pull-up, 0x15: 5kOhm weak pull-up,
+  0x19: 20kOhm weak pull-up
+**/
+  UINT8                       EmmcGpioCmdPadTermination;
+
+/** Offset 0x0FF5 - Emmc Data Pin Mux
+  Select  pin muxing. Refer to GPIO_*_MUXING_EMMC_DATA_x* for possible values. One
+  UINT32 for each data pin [0-8]
+**/
+  UINT8                       EmmcGpioDataPinMux[32];
+
+/** Offset 0x1015 - Emmc Data Pad Termination
+  0x0: Hardware default, 0x1: None, 0x13: 1kOhm weak pull-up, 0x15: 5kOhm weak pull-up,
+  0x19: 20kOhm weak pull-up. One byte for each data pin [0-8]
+**/
+  UINT8                       EmmcGpioDataPadTermination[8];
+
+/** Offset 0x101D
+**/
+  UINT8                       UnusedUpdSpace39[3];
+
+/** Offset 0x1020 - Emmc Rclk PinMux
+  Select Rclk pin muxing. Refer to GPIO_*_MUXING_EMMC_RCLK* for possible values.
+**/
+  UINT32                      EmmcGpioRclkPinMux;
+
+/** Offset 0x1024 - Emmc Rclk Pad Termination
+  0x0: Hardware default, 0x1: None, 0x13: 1kOhm weak pull-up, 0x15: 5kOhm weak pull-up,
+  0x19: 20kOhm weak pull-up
+**/
+  UINT8                       EmmcGpioRclkPadTermination;
+
+/** Offset 0x1025
+**/
+  UINT8                       UnusedUpdSpace40[3];
+
+/** Offset 0x1028 - Emmc Clock Pin Mux
+  Select Clock pin muxing. Refer to GPIO_*_MUXING_EMMC_CLK* for possible values.
+**/
+  UINT32                      EmmcGpioClkPinMux;
+
+/** Offset 0x102C - Emmc Clock Pad Termination
+  0x0: Hardware default, 0x1: None, 0x13: 1kOhm weak pull-up, 0x15: 5kOhm weak pull-up,
+  0x19: 20kOhm weak pull-up
+**/
+  UINT8                       EmmcGpioClkPadTermination;
+
+/** Offset 0x102D
+**/
+  UINT8                       UnusedUpdSpace41[3];
+
+/** Offset 0x1030 - Emmc Resetb PinMux
+  Select Resetb pin muxing. Refer to GPIO_*_MUXING_EMMC_RESETB* for possible values.
+**/
+  UINT32                      EmmcGpioResetbPinMux;
+
+/** Offset 0x1034 - Emmc Resetb Pad Termination
+  0x0: Hardware default, 0x1: None, 0x13: 1kOhm weak pull-up, 0x15: 5kOhm weak pull-up,
+  0x19: 20kOhm weak pull-up
+**/
+  UINT8                       EmmcGpioResetbPadTermination;
 
 /** Offset 0x1035 - Enable VMD Global Mapping
   Enable/disable to VMD controller.0: Disable; 1: Enable(Default)
@@ -3958,9 +4299,125 @@ typedef struct {
 **/
   UINT8                       VmdGlobalMapping;
 
-/** Offset 0x1036 - Reserved
+/** Offset 0x1036 - CPU PCIE Port0 Link Disable
+  CPU PCIE Port0 Link Disable while Device attached into Port0 and Port1.0: Disable(Default);
+  1: Enable.
+  $EN_DIS
 **/
-  UINT8                       Reserved57[138];
+  UINT8                       CpuPcieFunc0LinkDisable[4];
+
+/** Offset 0x103A - Skip VccIn Configuration
+  Skips VccIn configuration when enabled
+  $EN_DIS
+**/
+  UINT8                       PmcSkipVccInConfig;
+
+/** Offset 0x103B - CSE Data Resilience Support
+  0: Disable CSE Data Resilience Support. <b>; 1: Enable CSE Data Resilience Support.</b>
+  $EN_DIS
+**/
+  UINT8                       CseDataResilience;
+
+/** Offset 0x103C - HorizontalResolution for PEI Logo
+  HorizontalResolution from PEIm Gfx for PEI Logo
+**/
+  UINT32                      HorizontalResolution;
+
+/** Offset 0x1040 - VerticalResolution for PEI Logo
+  VerticalResolution from PEIm Gfx for PEI Logo
+**/
+  UINT32                      VerticalResolution;
+
+/** Offset 0x1044 - Touch Host Controller Active Ltr
+  Expose Active Ltr for OS driver to set
+**/
+  UINT32                      ThcActiveLtr[2];
+
+/** Offset 0x104C - Touch Host Controller Idle Ltr
+  Expose Idle Ltr for OS driver to set
+**/
+  UINT32                      ThcIdleLtr[2];
+
+/** Offset 0x1054 - Touch Host Controller Hid Over Spi ResetPad
+  Hid Over Spi ResetPad 0x0 - Use THC HW default Pad, For other pad setting refer
+  to GpioPins
+**/
+  UINT32                      ThcHidResetPad[2];
+
+/** Offset 0x105C - Touch Host Controller Hid Over Spi ResetPad Trigger
+  Hid Over Spi Reset Pad Trigger 0x0:Low, 0x1:High
+**/
+  UINT32                      ThcHidResetPadTrigger[2];
+
+/** Offset 0x1064 - Touch Host Controller Hid Over Spi Connection Speed
+  Hid Over Spi Connection Speed - SPI Frequency
+**/
+  UINT32                      ThcHidConnectionSpeed[2];
+
+/** Offset 0x106C - Touch Host Controller Hid Over Spi Limit PacketSize
+  When set, limits SPI read & write packet size to 64B. Otherwise, THC uses Max Soc
+  packet size for SPI Read and Write 0x0- Max Soc Packet Size,  0x11 - 64 Bytes
+**/
+  UINT32                      ThcLimitPacketSize[2];
+
+/** Offset 0x1074 - Touch Host Controller Hid Over Spi Limit PacketSize
+  Minimum amount of delay the THC/QUICKSPI driver must wait between end of write operation
+  and begin of read operation. This value shall be in 10us multiples 0x0: Disabled,
+  1-65535 (0xFFFF) - up to 655350 us
+**/
+  UINT32                      ThcPerformanceLimitation[2];
+
+/** Offset 0x107C - Touch Host Controller Hid Over Spi Input Report Header Address
+  Hid Over Spi Input Report Header Address
+**/
+  UINT32                      ThcHidInputReportHeaderAddress[2];
+
+/** Offset 0x1084 - Touch Host Controller Hid Over Spi Input Report Body Address
+  Hid Over Spi Input Report Body Address
+**/
+  UINT32                      ThcHidInputReportBodyAddress[2];
+
+/** Offset 0x108C - Touch Host Controller Hid Over Spi Output Report Address
+  Hid Over Spi Output Report Address
+**/
+  UINT32                      ThcHidOutputReportAddress[2];
+
+/** Offset 0x1094 - Touch Host Controller Hid Over Spi Read Opcode
+  Hid Over Spi Read Opcode
+**/
+  UINT32                      ThcHidReadOpcode[2];
+
+/** Offset 0x109C - Touch Host Controller Hid Over Spi Write Opcode
+  Hid Over Spi Write Opcode
+**/
+  UINT32                      ThcHidWriteOpcode[2];
+
+/** Offset 0x10A4 - Touch Host Controller Hid Over Spi Flags
+  Hid Over Spi Flags 0x0:Single SPI Mode, 0x4000:Dual SPI Mode, 0x8000:Quad SPI Mode
+**/
+  UINT32                      ThcHidFlags[2];
+
+/** Offset 0x10AC
+**/
+  UINT8                       UnusedUpdSpace42[4];
+
+/** Offset 0x10B0 - MemoryBuffer
+  MemoryBuffer address
+**/
+  UINT64                      MemoryBuffer;
+
+/** Offset 0x10B8 - MemorySize
+  MemorySize value
+**/
+  UINT32                      MemorySize;
+
+/** Offset 0x10BC
+**/
+  UINT8                       UnusedUpdSpace43[2];
+
+/** Offset 0x10BE
+**/
+  UINT8                       ReservedFspsUpd[2];
 } FSP_S_CONFIG;
 
 /** Fsp S UPD Configuration

From 29440057b0fa7ba130c157211356d85d92d21d1a Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Wed, 11 Jun 2025 15:33:56 +0100
Subject: [PATCH 1495/3886] mb/starlabs/{adl_n,twl}: Don't use the IOT FSP

The IOT version of FSP is inconsistent at resuming from S3,
so switch to the client version.

Change-Id: Ifadfebf53e20bc82e6272ea28e5bc443b9829545
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88055
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
---
 src/mainboard/starlabs/byte_adl/Kconfig     | 1 -
 src/mainboard/starlabs/starbook/Kconfig     | 1 -
 src/mainboard/starlabs/starlite_adl/Kconfig | 1 -
 3 files changed, 3 deletions(-)

diff --git a/src/mainboard/starlabs/byte_adl/Kconfig b/src/mainboard/starlabs/byte_adl/Kconfig
index 6c7250e39f..cb1b21953d 100644
--- a/src/mainboard/starlabs/byte_adl/Kconfig
+++ b/src/mainboard/starlabs/byte_adl/Kconfig
@@ -9,7 +9,6 @@ config BOARD_STARLABS_BYTE_SERIES
 	select EC_STARLABS_ITE
 	select EC_STARLABS_MERLIN
 	select EC_STARLABS_NEED_ITE_BIN
-	select FSP_TYPE_IOT
 	select HAVE_ACPI_RESUME
 	select HAVE_ACPI_TABLES
 	select HAVE_INTEL_PTT
diff --git a/src/mainboard/starlabs/starbook/Kconfig b/src/mainboard/starlabs/starbook/Kconfig
index c9ce050e49..bfb986fc6f 100644
--- a/src/mainboard/starlabs/starbook/Kconfig
+++ b/src/mainboard/starlabs/starbook/Kconfig
@@ -92,7 +92,6 @@ config BOARD_STARLABS_STARBOOK_ADL
 config BOARD_STARLABS_STARBOOK_ADL_N
 	select BOARD_ROMSIZE_KB_16384
 	select BOARD_STARLABS_STARBOOK_ADL_COMMON
-	select FSP_TYPE_IOT
 	select SOC_INTEL_ALDERLAKE_PCH_N
 
 config BOARD_STARLABS_STARBOOK_RPL
diff --git a/src/mainboard/starlabs/starlite_adl/Kconfig b/src/mainboard/starlabs/starlite_adl/Kconfig
index c228a22d5d..0a4d948fc2 100644
--- a/src/mainboard/starlabs/starlite_adl/Kconfig
+++ b/src/mainboard/starlabs/starlite_adl/Kconfig
@@ -15,7 +15,6 @@ config BOARD_STARLABS_STARLITE_SERIES
 	select EC_STARLABS_MERLIN
 	select EC_STARLABS_NEED_ITE_BIN
 	select EC_STARLABS_POWER_LED
-	select FSP_TYPE_IOT
 	select HAVE_ACPI_RESUME
 	select HAVE_ACPI_TABLES
 	select HAVE_INTEL_PTT

From f3ca3aa16b15d63f74ea60ca5a4a83da65d9b215 Mon Sep 17 00:00:00 2001
From: Bill XIE <persmule@hardenedlinux.org>
Date: Wed, 4 Jun 2025 10:04:54 +0800
Subject: [PATCH 1496/3886] util/cbfstool/cbfs-payload-linux: Copy segments
 when compression fails

When compression fails (usually due to larger result), we could retry
with memcpy() as in cbfs-mkpayload.c, instead of stopping immediately.

Signed-off-by: Bill XIE <persmule@hardenedlinux.org>
Change-Id: Id8b2cffef3832c4bad49bd722c9a5133735f61b0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87934
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 util/cbfstool/cbfs-payload-linux.c | 10 ++++++----
 1 file changed, 6 insertions(+), 4 deletions(-)

diff --git a/util/cbfstool/cbfs-payload-linux.c b/util/cbfstool/cbfs-payload-linux.c
index d0f24fec6c..0eb841df82 100644
--- a/util/cbfstool/cbfs-payload-linux.c
+++ b/util/cbfstool/cbfs-payload-linux.c
@@ -163,10 +163,12 @@ static int bzp_output_segment(struct bzpayload *bzp, struct buffer *b,
 	seg->offset = bzp->offset;
 
 	comp_func_ptr compress_func = compression_function(algo);
-	int ret = compress_func(buffer_get(b), buffer_size(b), buffer_get(&out), &len);
-	if (ret) {
-		ERROR("%s(): Compression failed\n", __func__);
-		return ret;
+	if (compress_func(buffer_get(b), buffer_size(b), buffer_get(&out), &len)) {
+		WARN("Compression failed or would make the data bigger "
+		     "- disabled.\n");
+		algo = CBFS_COMPRESS_NONE;
+		len = buffer_size(b);
+		memcpy(buffer_get(&out), buffer_get(b), len);
 	}
 
 	seg->compression = algo;

From d4616276689a2878eece75ae0f7c9c86b3fd8907 Mon Sep 17 00:00:00 2001
From: Bill XIE <persmule@hardenedlinux.org>
Date: Wed, 4 Jun 2025 08:38:52 +0800
Subject: [PATCH 1497/3886] payloads/Kconfig: Allow compression for Linux
 payloads

Linux (bzImage) payloads used to be totally not compressed with
cbfstool. However, only bzImage is already compressed and initrd is
usually compressed, but the trampoline, parameter, and kernel command
line should be compressible.

Now cbfstool can copy segments instead when compression fails, so
compression for Linux payloads (including LinuxBoot) could be enabled
for compressible components.

TEST=With LZMA, parameter is compressed from 0x1000 to 0x4c,
     trampoline is compressed from 0x171 to 0x14b, kernel command line
     is not compressed for being too short (0x22), initrd is not
     compressed for being already compressed.

Signed-off-by: Bill XIE <persmule@hardenedlinux.org>
Change-Id: I8af3c904de55910a1298673d8ec2925a317bcff5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87935
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
---
 payloads/Kconfig | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/payloads/Kconfig b/payloads/Kconfig
index 49486246c6..586e54a4dd 100644
--- a/payloads/Kconfig
+++ b/payloads/Kconfig
@@ -68,8 +68,8 @@ config PAYLOAD_FILE
 choice
 	prompt "Payload compression algorithm"
 	default COMPRESSED_PAYLOAD_LZMA
-	default COMPRESSED_PAYLOAD_NONE if PAYLOAD_LINUX || PAYLOAD_LINUXBOOT || PAYLOAD_FIT
-	depends on !PAYLOAD_LINUX && !PAYLOAD_LINUXBOOT && !PAYLOAD_FIT
+	default COMPRESSED_PAYLOAD_NONE if PAYLOAD_FIT
+	depends on !PAYLOAD_FIT
 	help
 	  Choose the compression algorithm for the chosen payloads.
 	  You can choose between None, LZMA, or LZ4.

From 812d0e2f626dfea7e7deb960a8dc08ff0e026bc1 Mon Sep 17 00:00:00 2001
From: Martin Roth <gaumless@gmail.com>
Date: Sat, 5 Apr 2025 14:57:28 -0600
Subject: [PATCH 1498/3886] Documentation/lib: Update Timestamp documentation

- Rephrase some items
- Add additional code examples
- Add additional sections
- Update documentation to the current state of the codebase.

Change-Id: I6e4cc244edf6cc860cc66165173f134a30a81589
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87186
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
---
 Documentation/lib/timestamp.md | 471 ++++++++++++++++++++++++---------
 1 file changed, 349 insertions(+), 122 deletions(-)

diff --git a/Documentation/lib/timestamp.md b/Documentation/lib/timestamp.md
index d08d4420dd..0e63b5dcaf 100644
--- a/Documentation/lib/timestamp.md
+++ b/Documentation/lib/timestamp.md
@@ -4,179 +4,406 @@
 
 The aim of the timestamp library is to make it easier for different
 boards to save timestamps in cbmem / stash (until cbmem is brought up)
-by providing a simple API to initialize, add and sync timestamps. In
+by providing a simple API to initialize, add, and sync timestamps. In
 order to make the timestamps persistent and accessible from the kernel,
 we need to ensure that all the saved timestamps end up in cbmem under
 the CBMEM_ID_TIMESTAMP tag. However, until the cbmem area is available,
-the timestamps can be saved to a SoC-defined \_timestamp region or in a
-local stage-specific stash. The work of identifying the right location
-for storing timestamps is done by the library and is not exposed to the
-user.
+the timestamps can be saved to a SoC-defined `_timestamp` region if one
+is defined in the board's `memlayout.ld`. The work of identifying the
+right location for storing timestamps is done by the library and is not
+exposed to the user.
+
+Timestamps in coreboot are a critical feature for performance analysis,
+debugging, and optimization of the boot process. They provide precise
+timing information about various stages and operations during system
+initialization, allowing developers to identify bottlenecks and optimize
+boot performance. The timestamp system is designed to be lightweight,
+accurate, and persistent across different boot stages.
 
 Working of timestamp library from a user perspective can be outlined in
 the following steps:
-1. Initialize the base time and reset cbmem timestamp area
-2. Start adding timestamps
+1. Initialize the base time and reset cbmem timestamp area using
+   `timestamp_init()`.
+2. Start adding timestamps using `timestamp_add()` or
+   `timestamp_add_now()`.
 
 Behind the scenes, the timestamp library takes care of:
-1. Identifying the correct location for storing timestamps (cbmem or
-   timestamp region or local stash).
-2. Once cbmem is up, ensure that all timestamps are synced from
-   timestamp region or local stash into the cbmem area.
-3. Add a new cbmem timestamp area based on whether a reset of the cbmem
+1. Identifying the correct location for storing timestamps (`_timestamp`
+   region before cbmem is ready, then cbmem region).
+2. Add a new cbmem timestamp area based on whether a reset of the cbmem
    timestamp region is required or not.
+3. Once cbmem is ready, ensuring that all timestamps are synced from the
+   `_timestamp` region into the cbmem area.
 
-### Transition from cache to cbmem
-
-To move timestamps from the cache to cbmem (and initialize the cbmem
-area in the first place), we use the CBMEM_INIT_HOOK infrastructure of
-coreboot.
-
-When cbmem is initialized, the hook is called, which creates the area,
-copies all timestamps to cbmem and disables the cache.
-
-After such a transition, timestamp_init() must not be run again.
+Note that if `CONFIG_COLLECT_TIMESTAMPS` is disabled, all timestamp
+functions are implemented as no-ops, and no timestamps will be
+collected.
 
 
-## Data structures used
+## Background
 
-The main structure that maintains information about the timestamp cache
-is:
+The timestamp implementation in coreboot has evolved over time to meet
+the needs of the firmware development and performance analysis.
+Initially designed as a simple timing mechanism, it has grown into a
+sophisticated system that:
 
-```c
-struct __packed timestamp_cache {
-        uint16_t cache_state;
-        struct timestamp_table table;
-        struct timestamp_entry entries[MAX_TIMESTAMP_CACHE];
-};
-```
-
-### cache_state
-
-The state of the cache is maintained by `cache_state` attribute which
-can be any one of the following:
-
-```c
-enum {
-        TIMESTAMP_CACHE_UNINITIALIZED = 0,
-        TIMESTAMP_CACHE_INITIALIZED,
-        TIMESTAMP_CACHE_NOT_NEEDED,
-};
-```
-
-By default, if the cache is stored in local stash (bss area), then it
-will be reset to uninitialized state. However, if the cache is stored in
-timestamp region, then it might have garbage in any of the attributes.
-Thus, if the timestamp region is being used by any board, it is
-initialized to default values by the library.
-
-Once the cache is initialized, its state is set to
-`CACHE_INITIALIZED`. Henceforth, the calls to cache i.e. `timestamp_add`
-know that the state reflected is valid and timestamps can be directly
-saved in the cache.
-
-Once the cbmem area is up (i.e. call to
-`timestamp_sync_cache_to_cbmem`), we do not need to store the timestamps
-in local stash / timestamp area anymore. Thus, the cache state is set to
-`CACHE_NOT_NEEDED`, which allows `timestamp_add` to store all timestamps
-directly into the cbmem area.
+- Tracks boot stages and critical operations
+- Supports multiple hardware platforms (x86, ARM, RISC-V)
+- Provides persistent storage across boot stages
+- Enables post-boot analysis of boot performance
+- Integrates with vendor-specific firmware components
 
 
-### table
+## Timestamp Architecture
 
-This field is represented by a structure which provides overall
-information about the entries in the timestamp area:
+### Transition from cache (`_timestamp` region) to cbmem
 
-```c
-struct timestamp_table {
-        uint64_t        base_time;
-        uint32_t        max_entries;
-        uint32_t        num_entries;
-        struct timestamp_entry entries[0]; /* Variable number of entries */
-} __packed;
-```
+To move timestamps from the early `_timestamp` region to cbmem (and
+initialize the cbmem area in the first place), we use the
+`CBMEM_READY_HOOK` infrastructure of coreboot.
 
-It indicates the base time for all timestamp entries, maximum number of
-entries that can be stored, total number of entries that currently exist
-and an entry structure to hold variable number of entries.
+When cbmem is initialized (`cbmem_initialize` or `cbmem_recovery`), the
+hook calls the `timestamp_reinit` function. This function allocates or
+finds the `CBMEM_ID_TIMESTAMP` area in cbmem, copies all timestamps from
+the `_timestamp` region (if used) using `timestamp_sync_cache_to_cbmem`,
+and updates an internal global pointer (`glob_ts_table`) to point to the
+cbmem table. Subsequent calls to `timestamp_add` will then write
+directly to cbmem.
+
+After such a transition, `timestamp_init()` must not be run again (it is
+asserted to only run in `ENV_ROMSTAGE_OR_BEFORE`).
 
 
-### entries
+### Data structures used
+
+Timestamps are stored using instances of `struct timestamp_table`. A
+global pointer, `glob_ts_table`, points to the currently active table,
+which is either the `_timestamp` memory region (during early boot) or
+the CBMEM area.
+
+The `_timestamp` region acts as an early cache before cbmem is ready.
+Its size is determined by `REGION_SIZE(timestamp)` defined in the linker
+script (`memlayout.ld`) and dictates the maximum number of entries that
+can be stored early on.
+
+For timestamps stored in the cbmem area, a `timestamp_table` is
+allocated with space for a fixed number of entries (currently 192)
+defined by `MAX_TIMESTAMPS` in `src/lib/timestamp.c`.
 
-This field holds the details of each timestamp entry, up to a maximum of
-`MAX_TIMESTAMP_CACHE` which is defined as 16 entries. Each entry is
-defined by:
 
 ```c
 struct timestamp_entry {
-        uint32_t        entry_id;
-        uint64_t        entry_stamp;
+	uint32_t        entry_id;
+	int64_t         entry_stamp;
 } __packed;
 ```
-
-`entry_id` holds the timestamp id corresponding to this entry and
-`entry_stamp` holds the actual timestamp.
+>>> _Source: `/src/commonlib/include/commonlib/timestamp_serialized.h`_
 
 
-For timestamps stored in the cbmem area, a `timestamp_table` is
-allocated with space for `MAX_TIMESTAMPS` equal to 30. Thus, the cbmem
-area holds `base_time`, `max_entries` (which is 30), current number of
-entries and the actual entries represented by `timestamp_entry`.
+```c
+struct timestamp_table {
+	uint64_t        base_time;
+	uint16_t        max_entries;
+	uint16_t        tick_freq_mhz;
+	uint32_t        num_entries;
+	struct timestamp_entry entries[]; /* Variable number of entries */
+} __packed;
+```
+>>> _Source: `/src/commonlib/include/commonlib/timestamp_serialized.h`_
+
+
+- `base_time`: Indicates the base time (offset) for all timestamp
+  entries in this table.
+- `max_entries`: Maximum number of entries that can be stored in this
+  table instance.
+- `tick_freq_mhz`: Timestamp tick frequency in MHz. Populated later in
+  boot.
+- `num_entries`: Total number of entries that currently exist in this
+  table instance.
+- `entries`: Array holding the actual timestamp entries.
+
+
+### Memory Layout
+
+Timestamps are stored in two locations during the boot process:
+
+1.  **`_timestamp` Region**: Used during early boot stages (before CBMEM
+    is available), *if* defined in `memlayout.ld`.
+    - Located at the `_timestamp` symbol.
+    - Persists across stage transitions within `ENV_ROMSTAGE_OR_BEFORE`.
+    - Size determined by `REGION_SIZE(timestamp)` in the linker script,
+      which limits the number of entries.
+
+2.  **CBMEM**: Used after CBMEM is initialized.
+    - Identified by `CBMEM_ID_TIMESTAMP`.
+    - Provides persistent storage across warm reboots.
+    - Supports a fixed maximum number of entries.
+    - Automatically synchronized from the `_timestamp` region when CBMEM
+      becomes available via `timestamp_reinit`.
 
 
 ## Function APIs
 
-### timestamp_init
+### Core Functions
 
-This function initializes the timestamp cache and should be run as early
-as possible. On platforms with SRAM, this might mean in bootblock, on
-x86 with its CAR backed memory in romstage, this means romstage before
-memory init.
+#### timestamp_init
 
-### timestamp_add
+```c
+void timestamp_init(uint64_t base);
+```
+>>> _Source: `/src/include/timestamp.h`_
 
-This function accepts from user a timestamp id and time to record in the
-timestamp table. It stores the entry in the appropriate table in cbmem
-or `_timestamp` region or local stash.
+Initializes the timestamp system with a base time. This function sets up
+the timestamp cache (`_timestamp` region) and should be run in
+bootblock. It must be called once in *one* of the
+`ENV_ROMSTAGE_OR_BEFORE` stages. It will fail if no `timestamp` region
+is defined in `memlayout.ld`.
+
+Note that platform setup code on x86 or the decompressor on Arm can
+measure some timestamps earlier and pass them in to
+bootblock_main_with_timestamp().
 
 
-### timestamp_add_now
+#### timestamp_add
 
-This function calls `timestamp_add` with user-provided id and current
-time.
+```c
+void timestamp_add(enum timestamp_id id, int64_t ts_time);
+```
+>>> _Source: `/src/include/timestamp.h`_
+
+Adds a new timestamp with the specified ID and time value. It stores the
+timestamp in the currently active table (either `_timestamp` region or
+cbmem). The time value must be an absolute time value (typically
+obtained from `timestamp_get()`), as it will be adjusted by subtracting
+the table's `base_time` before being stored as an entry.
+
+
+#### timestamp_add_now
+
+```c
+void timestamp_add_now(enum timestamp_id id);
+```
+>>> _Source: `/src/include/timestamp.h`_
+
+Adds a new timestamp with the current time. This function calls
+`timestamp_add` with user-provided id and current time obtained from
+`timestamp_get()`.
+
+
+#### timestamp_rescale_table
+
+```c
+void timestamp_rescale_table(uint16_t N, uint16_t M);
+```
+>>> _Source: `/src/include/timestamp.h`_
+
+Applies a scaling factor N/M to all recorded timestamps (including the
+`base_time`).
+
+
+#### get_us_since_boot
+
+```c
+uint32_t get_us_since_boot(void);
+```
+>>> _Source: `/src/include/timestamp.h`_
+
+Returns the time since boot (relative to `base_time`) in microseconds.
+Requires `tick_freq_mhz` to be populated.
+
+
+#### timestamp_get
+
+```c
+uint64_t timestamp_get(void);
+```
+>>> _Source: `/src/include/timestamp.h`_
+
+Returns the current raw timestamp value from the underlying hardware
+timer (platform-specific weak implementation).
+
+
+#### timestamp_tick_freq_mhz
+
+```c
+int timestamp_tick_freq_mhz(void);
+```
+>>> _Source: `/src/include/timestamp.h`_
+
+Returns the timestamp tick frequency in MHz (platform-specific weak
+implementation).
+
+
+### Timestamp IDs
+
+The system uses predefined timestamp IDs to mark various boot stages and
+operations. These are organized in ranges:
+
+- 1-500: Miscellaneous coreboot operations (e.g., `TS_POSTCAR_START`,
+  `TS_DELAY_START`, `TS_READ_UCODE_START`)
+- 500-600: Google/ChromeOS specific (e.g., `TS_VBOOT_START`,
+  `TS_EC_SYNC_START`).
+
+  Note many of the existing timestamps here are no longer
+  Google-specific since many features originally added for Google
+  vendorcode have since been migrated into general coreboot code.
+
+- 900-940: AMD specific (e.g., `TS_AGESA_INIT_EARLY_START`)
+- 940-950: Intel ME specific (e.g., `TS_ME_INFORM_DRAM_START`)
+- 950-989: Intel FSP specific (e.g., `TS_FSP_MEMORY_INIT_START`)
+- 990-999: Intel ME specific (continued) (e.g., `TS_ME_ROM_START`)
+- 1000+: Payload specific
+  - Depthcharge: 1000-1199
+  - ChromeOS Hypervisor: 1200-1299
+
+Refer to `src/commonlib/include/commonlib/timestamp_serialized.h` for
+the complete list and descriptions.
 
 
 ## Use / Test Cases
 
-The following cases have been considered while designing the timestamp
-library. It is important to ensure that any changes made to this library
-satisfy each of the following use cases:
+The following cases describe the behavior based on the presence of the
+`timestamp` region and when cbmem is initialized.
 
-### Case 1: Timestamp Region Exists (Fresh Boot / Resume)
 
-In this case, the library needs to call `timestamp_init` as early as
-possible to enable the timestamp cache. Once cbmem is available, the
-values will be transferred automatically.
+### Case 1: Timestamp Region Exists
 
-All regions are automatically reset on initialization.
+This is the standard configuration for collecting early timestamps.
+`timestamp_init` must be called in an `ENV_ROMSTAGE_OR_BEFORE` stage to
+initialize the `_timestamp` region. When the `CBMEM_READY_HOOK` runs
+`timestamp_reinit`, the contents of the `_timestamp` region are copied
+to the cbmem table, and subsequent timestamps go directly to cbmem. The
+cbmem table is reset on fresh boot or resume.
 
-### Case 2: No timestamp region, fresh boot, cbmem_initialize called after timestamp_init
 
-`timestamp_init` will set up a local cache. cbmem must be initialized
-before that cache vanishes - as happens when jumping to the next stage.
+### Case 2: No Timestamp Region Defined
 
-### Case 3: No timestamp region, fresh boot, cbmem_initialize called before timestamp_init
+If no `timestamp` region is defined in `memlayout.ld`, attempts to call
+`timestamp_init` will fail (specifically, `timestamp_cache_get()` will
+return NULL). No timestamps can be collected before cbmem is ready.
+Timestamps added after `timestamp_reinit` has run (via the
+`CBMEM_READY_HOOK`) will be added directly to the cbmem table, but there
+will be no `base_time` established from early boot.
 
-This case is not supported right now, just don't call `timestamp_init`
-after `cbmem_initialize`. (Patches to make this more robust are
-welcome.)
 
-### Case 4: No timestamp region, resume, cbmem_initialize called after timestamp_init
+### Case 3: Resume
 
-We always reset the cbmem region before using it, so pre-suspend
-timestamps will be gone.
+On resume (e.g., x86 S3), `timestamp_reinit` is typically called again.
+If `ENV_CREATES_CBMEM` is true for the resume path (as it is for x86
+S3), a new cbmem table is allocated by `timestamp_alloc_cbmem_table`,
+effectively clearing any pre-suspend timestamps. The `_timestamp` region
+content (if any) is copied over, but this usually contains stale data
+from the previous boot's early stages.
 
-### Case 5: No timestamp region, resume, cbmem_initialize called before timestamp_init
 
-We always reset the cbmem region before using it, so pre-suspend
-timestamps will be gone.
+## Configuration
+
+### Kconfig Options
+
+- `CONFIG_COLLECT_TIMESTAMPS`: Enable/disable timestamp collection
+  globally. If disabled, timestamp functions become no-ops.
+- `CONFIG_TIMESTAMPS_ON_CONSOLE`: Print timestamps to console during
+  boot as they are added.
+
+
+### Memory Layout
+
+Collecting timestamps before cbmem is ready requires an `_timestamp`
+region in the memory layout, defined in the `memlayout.ld` linker
+script. Depending on the platform, the memory layout can be for the
+board, the SOC, or the Architecture. Any of them will typically follow
+the following pattern:
+
+```text
+#include <memlayout.h>
+
+...
+TIMESTAMP(., 0x200)
+...
+
+```
+
+The size allocated to this region determines the maximum number of
+timestamps that can be stored before cbmem is available.
+
+The cbmem timestamp table (`CBMEM_ID_TIMESTAMP`) has a fixed size,
+currently allowing up to 192 entries. This limit is defined by
+`MAX_TIMESTAMPS` in `src/lib/timestamp.c`.
+
+
+### Hardware Considerations
+
+- x86: `timestamp_init` must be called before CAR (Cache-as-RAM) is torn
+  down if called from bootblock or separate romstage. The library
+  includes checks (`timestamp_should_run`) to ensure timestamps are only
+  added by the primary processor during early boot on AP systems.
+- ARM: No special considerations noted in the code.
+- RISC-V: No special considerations noted in the code.
+
+
+## Examples
+
+### Initializing Timestamps (in bootblock)
+
+```c
+/* In src/mainboard/$(MAINBOARDDIR)/bootblock.c */
+#include <timestamp.h>
+#include <timer.h> /* For timestamp_get() default implementation */
+
+void bootblock_mainboard_init(void)
+{
+	/* Initialize timestamp region with current time as base. */
+	timestamp_init(timestamp_get());
+
+	/* Add first timestamp */
+	timestamp_add_now(TS_BOOTBLOCK_START);
+
+	/* ... other bootblock code ... */
+}
+```
+
+Note: `timestamp_get()` here provides the initial base time. Requires
+`CONFIG_COLLECT_TIMESTAMPS=y` and a `timestamp` region.
+
+
+### Adding Custom Timestamps
+
+```c
+#include <timestamp.h>
+
+void my_custom_function(void)
+{
+	timestamp_add_now(TS_DEVICE_INITIALIZE); /* Use a relevant ID */
+	// ... perform initialization ...
+	timestamp_add_now(TS_DEVICE_DONE);       /* Use a relevant ID */
+}
+```
+
+
+## Best Practices
+
+1.  **Initialization**:
+    - Enable `CONFIG_COLLECT_TIMESTAMPS` if needed.
+    - Define a `timestamp` region in `memlayout.ld` if early
+      timestamps (before cbmem) are required. Ensure it's large enough
+      for the expected number of early entries.
+    - Call `timestamp_init()` exactly once in the earliest possible
+      `ENV_ROMSTAGE_OR_BEFORE` stage (e.g., `bootblock`).
+    - Use a consistent base time, typically `timestamp_get()`.
+
+2.  **Adding Timestamps**:
+    - Use appropriate predefined timestamp IDs from
+      `timestamp_serialized.h` whenever possible. Add custom IDs if
+      necessary, avoiding conflicts.
+    - Add timestamps for significant operations or stage transitions
+      using `timestamp_add_now()`.
+    - Be mindful of the entry limits: the size of the `_timestamp`
+      region for early timestamps, and the fixed limit for the cbmem
+      table. Check for "Timestamp table full" errors in the log.
+
+3.  **Analysis**:
+    - Use the `cbmem -t` utility in the OS (if using LinuxBoot/NERF)
+      to read and display timestamps stored in CBMEM.
+    - Consider the `tick_freq_mhz` (also available in the `cbmem -t`
+      output) when converting raw timestamp differences (`entry_stamp`)
+      to time units. The raw values are offsets from `base_time`.

From 267f08dafd85caf733329bfb2792b27bd71df0ec Mon Sep 17 00:00:00 2001
From: Alicja Michalska <alicja.michalska@9elements.com>
Date: Wed, 2 Jul 2025 20:25:21 +0200
Subject: [PATCH 1499/3886] MAINTAINERS: Add KunYi Chen as maintainer for
 LattePanda Mu

It makes it easier to request reviews on patches or report bugs.

Change-Id: Icaefa00c866ec6600637f67e7906f523b36348cb
Signed-off-by: Alicja Michalska <alicja.michalska@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88276
Reviewed-by: KunYi Chen <kunyi.chen@gmail.com>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 MAINTAINERS | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/MAINTAINERS b/MAINTAINERS
index f87502a74d..ddca248f82 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -465,7 +465,10 @@ M:	Felix Singer <felixsinger@posteo.net>
 S:	Supported
 F:	src/mainboard/kontron/mal10/
 
-
+LATTEPANDA MU MAINBOARD
+M:	KunYi Chen <kunyi.chen@gmail.com>
+S:	Maintained
+F:	src/mainboard/lattepanda/mu/
 
 LENOVO MAINBOARDS
 M:	Alexander Couzens <lynxis@fe80.eu>

From 2eaec1b53a72a56f1132fecf17eb1574fa5633b4 Mon Sep 17 00:00:00 2001
From: Benjamin Doron <benjamin.doron@9elements.com>
Date: Fri, 4 Jul 2025 23:13:27 -0400
Subject: [PATCH 1500/3886] sbom: Fix build with merged bootblock and romstage

Do not attempt to use the VBOOT pkgconfig file when it doesn't exist.

Change-Id: I9633fc7fb060b1d00fddfd938ff2956c03b24274
Signed-off-by: Benjamin Doron <benjamin.doron@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88319
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/sbom/Makefile.mk | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/src/sbom/Makefile.mk b/src/sbom/Makefile.mk
index 26f48dc3e8..5009c3186f 100644
--- a/src/sbom/Makefile.mk
+++ b/src/sbom/Makefile.mk
@@ -63,7 +63,10 @@ swid-files-$(CONFIG_SBOM_EC) += $(CONFIG_SBOM_EC_PATH)
 swid-files-$(CONFIG_SBOM_BIOS_ACM) += $(CONFIG_BIOS_ACM_PATH)
 swid-files-$(CONFIG_SBOM_SINIT_ACM) += $(CONFIG_SINIT_ACM_PATH)
 
-vboot-pkgconfig-files = $(obj)/external/vboot_reference-bootblock/vboot_host.pc $(obj)/external/vboot_reference-romstage/vboot_host.pc $(obj)/external/vboot_reference-ramstage/vboot_host.pc $(obj)/external/vboot_reference-postcar/vboot_host.pc
+vboot-pkgconfig-files = $(obj)/external/vboot_reference-bootblock/vboot_host.pc $(obj)/external/vboot_reference-ramstage/vboot_host.pc $(obj)/external/vboot_reference-postcar/vboot_host.pc
+ifeq ($(CONFIG_SEPARATE_ROMSTAGE),y)
+vboot-pkgconfig-files += $(obj)/external/vboot_reference-romstage/vboot_host.pc
+endif
 swid-files-$(CONFIG_SBOM_VBOOT) += $(vboot-pkgconfig-files)
 $(vboot-pkgconfig-files): $(VBOOT_LIB_bootblock) $(VBOOT_LIB_romstage) $(VBOOT_LIB_ramstage) $(VBOOT_LIB_postcar) # src/security/vboot/Makefile.mk
 

From e94ac6e65512eb70bd11f5e863c328fd58aed134 Mon Sep 17 00:00:00 2001
From: Baozhen Yang <yangbaozhen5@huaqin.corp-partner.google.com>
Date: Thu, 3 Jul 2025 13:56:42 +0800
Subject: [PATCH 1501/3886] mb/google/nissa/var/pujjocento: Reduce PL4 to 38 W
 with no battery
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

When battery is not present, reduce power limits to below 45W,
avoid inability to enter the system.

To avoid poor efficiency of the adapter, leave a margin and set the powerlimit to 38w.

This will check the current battery status and configure cpu power
limits using current PD power value.

BUG=b:418695656
BRANCH=None
TEST=
1、built(emerge-nissa coreboot chromeos-bootimage) and push ap firmware to dut.
2、Connect 15W machine without battery to 45W adapter and check if it starts up properly.
3、Use ec command “cbmem -c | grep PL“ to check if the PL4 value is 38 watts.

Change-Id: I72429052f5b3d25e56076176728498357a298cdd
Signed-off-by: Baozhen Yang <yangbaozhen5@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88282
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
---
 .../brya/variants/baseboard/trulo/Makefile.mk |  1 +
 .../brya/variants/baseboard/trulo/ramstage.c  | 39 +++++++++++++++++++
 2 files changed, 40 insertions(+)
 create mode 100644 src/mainboard/google/brya/variants/baseboard/trulo/ramstage.c

diff --git a/src/mainboard/google/brya/variants/baseboard/trulo/Makefile.mk b/src/mainboard/google/brya/variants/baseboard/trulo/Makefile.mk
index cc62f1ddb7..754843f8cf 100644
--- a/src/mainboard/google/brya/variants/baseboard/trulo/Makefile.mk
+++ b/src/mainboard/google/brya/variants/baseboard/trulo/Makefile.mk
@@ -2,3 +2,4 @@
 
 romstage-$(CONFIG_MAINBOARD_USE_EARLY_LIBGFXINIT) += gma-mainboard.ads
 romstage-y += memory.c
+ramstage-y += ramstage.c
diff --git a/src/mainboard/google/brya/variants/baseboard/trulo/ramstage.c b/src/mainboard/google/brya/variants/baseboard/trulo/ramstage.c
new file mode 100644
index 0000000000..66001bd4be
--- /dev/null
+++ b/src/mainboard/google/brya/variants/baseboard/trulo/ramstage.c
@@ -0,0 +1,39 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <baseboard/gpio.h>
+#include <baseboard/variants.h>
+#include <device/pci_ops.h>
+#include <gpio.h>
+#include <soc/gpio.h>
+#include <soc/ramstage.h>
+#include <soc/pci_devs.h>
+#include <static.h>
+#include <intelblocks/power_limit.h>
+
+struct soc_power_limits_config *variant_get_soc_power_limit_config(void)
+{
+	config_t *config = config_of_soc();
+	size_t i;
+	struct device *sa = pcidev_path_on_root(SA_DEVFN_ROOT);
+	uint16_t sa_pci_id;
+	u8 tdp;
+
+	if (!sa)
+		return NULL;
+
+	sa_pci_id = pci_read_config16(sa, PCI_DEVICE_ID);
+
+	if (sa_pci_id == 0xffff)
+		return NULL;
+
+	tdp = get_cpu_tdp();
+
+	for (i = 0; i < ARRAY_SIZE(cpuid_to_adl); i++) {
+		if (sa_pci_id == cpuid_to_adl[i].cpu_id &&
+				tdp == cpuid_to_adl[i].cpu_tdp) {
+			return &config->power_limits_config[cpuid_to_adl[i].limits];
+		}
+	}
+
+	return NULL;
+}

From 07267d19ce4501343fae7abf92a0e048ff29ceae Mon Sep 17 00:00:00 2001
From: melongmelong <knw0507@naver.com>
Date: Sun, 16 Mar 2025 20:57:59 +0900
Subject: [PATCH 1502/3886] arch/x86/postcar_loader: Add comment line for
 reloc_params assignment

During finalize_load(), cpu/x86/mtrr/earlymtrr.c:postcar_mtrr is signaled

to be loaded as reloc_params, e.g. with its cache flushed.

Add a comment line to specify the relationship to improve the readability.

I didn't see code to set up parameter at first time.
So, I just guess that adding a comment would be helpful. :)

Change-Id: Ic7d3f9cf514ce5a8efc2af9e78992cb39a91e537
Signed-off-by: NyeonWoo Kim <knw0507@naver.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86866
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
---
 src/arch/x86/postcar_loader.c | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/src/arch/x86/postcar_loader.c b/src/arch/x86/postcar_loader.c
index aac4af8568..d3d3dac4c4 100644
--- a/src/arch/x86/postcar_loader.c
+++ b/src/arch/x86/postcar_loader.c
@@ -83,7 +83,12 @@ void __noreturn prepare_and_run_postcar(void)
 
 static void finalize_load(uintptr_t *reloc_params, uintptr_t mtrr_frame_ptr)
 {
+	/*
+	 * set postcar(rmodule)'s parameter.
+	 * the parameter is defined as post_car_mtrrs in cpu/x86/mtrr/earlymtrr.c
+	 */
 	*reloc_params = mtrr_frame_ptr;
+
 	/*
 	 * Signal to rest of system that another update was made to the
 	 * postcar program prior to running it.

From 13f1c6118e25090333fa345ea3ac948cfb392c7a Mon Sep 17 00:00:00 2001
From: Martin Roth <gaumless@gmail.com>
Date: Sun, 6 Apr 2025 14:36:29 -0600
Subject: [PATCH 1503/3886] Documentation: Update cbmem.md with more
 information

Change-Id: I2b3eecdf994d4d5b48eacb3ae695efbb5640eb8b
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87193
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
---
 Documentation/getting_started/cbmem.md | 368 +++++++++++++++++++++++--
 1 file changed, 344 insertions(+), 24 deletions(-)

diff --git a/Documentation/getting_started/cbmem.md b/Documentation/getting_started/cbmem.md
index 13e6cf807e..f752a453ff 100644
--- a/Documentation/getting_started/cbmem.md
+++ b/Documentation/getting_started/cbmem.md
@@ -1,41 +1,361 @@
 # CBMEM high table memory manager
 
 ## Introduction
+
 CBMEM (coreboot memory) is a dynamic memory infrastructure used in
 coreboot to store runtime data structures, logs, and other information
-that needs to persist across different boot stages. CBMEM is crucial
-for maintaining state and logging information across different stages
-of the coreboot boot process.
+that needs to persist across different boot stages, and even across warm
+boots. CBMEM is crucial for maintaining state and information through
+the coreboot boot process.
+
+Its key responsibilities include:
+- Providing a stable storage area for critical boot data
+- Managing console logging
+- Storing configuration tables for hand off to payloads
+- Maintaining timestamps for performance analysis
+- Preserving boot state during S3 suspend/resume cycles
+- Storing data such as ACPI tables, SMBIOS tables and coreboot tables
+  which are used at runtime
+
 
 ## Creation and Placement
-CBMEM is initialized by coreboot during romstage, but is used mainly in
-ramstage for storing data such as coreboot and ACPI tables, SMBIOS,
-timestamps, stage information, vendor-specific data structures, etc.
 
-For 32-bit builds, CBMEM is typically located at the highest usable
-DRAM address below the 4GiB boundary. For 64-bit builds, while there
-is no strict upper limit, it is advisable to follow the same guidelines
-to prevent access or addressing issues. Regardless of the build type,
-the CBMEM address must remain consistent between romstage and ramstage.
+CBMEM is initialized by coreboot during romstage, but is used mainly in
+ramstage for storing any data that needs to be saved for more than a
+short period of time.
+
+For 32-bit builds, CBMEM is typically located at the highest usable DRAM
+address below the 4GiB boundary. For 64-bit builds, while there is no
+strict upper limit, it is advisable to follow the same guidelines to
+prevent access or addressing issues. Regardless of the build type, the
+CBMEM address must remain consistent between romstage and ramstage.
 
 Each platform may need to implement its own method for determining the
 `cbmem_top` address, as this can depend on specific hardware
 configurations and memory layouts.
 
-## Usage
+
+## Architecture Overview
+
 Each CBMEM region is identified by a unique ID, allowing different
-components to store and retrieve their data during runtime. The ID is a
-32-bit value that optionally encodes characters to indicate the type or
-source of the data.
+components to store and retrieve their data during runtime.
 
-Upon creating an entry, a block of memory is allocated of the requested
-size from the reserved CBMEM region. This region persists across warm
-reboots, making it useful for debugging and passing information to
-payloads.
+Upon creating an entry, a block of memory of the requested size is
+allocated from the reserved CBMEM region. This region typically persists
+across warm reboots, making it useful for debugging and passing
+information to payloads.
 
-Note that CBMEM is implemented as imd (in-memory database), meaning
-it grows downwards in memory from the provided upper limit, and only
-the latest added entry may be removed.
+CBMEM is implemented as a specialized in-memory database (IMD) system
+that grows downward from a defined upper memory limit. This means that
+only the latest added entry may be removed.
 
-The `cbmem` tool in `/util` can be used to list and access entries
-using their ID.
+```text
+High Memory
++----------------------+ <- cbmem_top
+|  Root Pointer        |
+|----------------------|
+|  Root Structure      |
+|----------------------|
+|  Entry 1             |
+|----------------------|
+|  Entry 2             |
+|----------------------|
+|  ...                 |
+|  (grows downward)    |
++----------------------+
+```
+
+
+### Core Components
+
+The CBMEM system consists of several key components:
+
+1. **Root Pointer**: Located at the very top of CBMEM memory space,
+   contains a magic number and offset to the Root Structure
+
+2. **Root Structure**: Contains metadata about the CBMEM region,
+   including:
+   - Entry alignment requirements
+   - Maximum number of entries
+   - Current number of entries
+   - Address of the lowest allocated memory
+
+3. **Entries**: Individual allocations within CBMEM, identified by:
+   - 32-bit ID (often encoding ASCII characters for readability)
+   - Size information
+   - Magic validation value
+
+4. **IMD Implementation**: The underlying memory management system
+   that handles allocation, deallocation, and entry management
+
+
+## Memory Layout and Initialization
+
+CBMEM is positioned at the top of available system RAM, typically
+just below the 4GiB boundary for 32-bit builds. This placement
+ensures compatibility with legacy code while allowing CBMEM to
+retain its contents across warm resets.
+
+
+### CBMEM Location Determination
+
+Each platform must implement a `cbmem_top_chipset()` function
+that returns the physical address where CBMEM should be located.
+This address must be consistent across coreboot stages and is
+determined based on:
+
+- Available physical memory
+- Architecture-specific constraints
+- BIOS/chipset requirements
+
+
+### Initialization Process
+
+CBMEM is initialized in a multi-step process:
+
+1. **Early Initialization**: A small console buffer is created in during
+   bootblock and romstage
+
+2. **RAM Initialization**: The full CBMEM area is established in
+   ramstage
+
+3. **Normal Operation**:
+   - In a normal boot, CBMEM is created fresh
+   - Size and alignment values are specified
+   - Initial entries are allocated
+
+4. **Recovery Operation**:
+   - During S3 resume, CBMEM structure is recovered from memory
+   - Content is validated using magic numbers and checksums
+   - All existing entries remain accessible
+
+
+## Entry Management
+
+CBMEM entries are identified by a 32-bit ID, often encoding ASCII
+characters to indicate their purpose (for example, "CNSL" for console).
+
+### Entry Creation
+
+```c
+void *cbmem_add(u32 id, u64 size);
+```
+
+This function:
+- Searches for an existing entry with the given ID
+- If found, returns the existing entry (size is ignored)
+- If not found, allocates a new entry of the requested size
+- Returns a pointer to the entry's data area
+
+
+### Entry Access
+
+```c
+void *cbmem_find(u32 id);
+```
+
+This function:
+- Searches for an entry with the specified ID
+- Returns a pointer to the entry's data area if found
+- Returns NULL if the entry does not exist
+
+
+### Entry Removal
+
+```c
+int cbmem_entry_remove(const struct cbmem_entry *entry);
+```
+
+This function:
+- Removes the specified entry if it was the last one added
+- Returns 0 on success, negative value on failure
+- Note: Due to the downward-growing design, only the most recently
+  added entry can be removed
+
+
+## CBMEM Console Implementation
+
+The CBMEM console is a circular buffer used for capturing log messages
+across all boot stages. It is one of the most widely used CBMEM
+features. The size of this buffer is determined by the
+`CONFIG_CBMEM_CONSOLE_SIZE` Kconfig option.
+
+
+### Console Structure
+
+```c
+struct cbmem_console {
+    u32 size;            // Size of the buffer
+    u32 cursor;          // Current write position and flags
+    u8  body[];          // Actual data buffer
+};
+```
+
+Key features:
+- The high bit of `cursor` indicates overflow condition
+- Only the lower 28 bits of `cursor` are used as position
+- Supports ring-buffer operation when full
+
+
+### Console Operation
+
+1. **Initialization**: A console entry is created in CBMEM with ID
+   `CBMEM_ID_CONSOLE` (0x434f4e53 - 'CONS')
+
+2. **Writing**: Log messages are written byte-by-byte using
+   `cbmemc_tx_byte()` which:
+   - Adds data to the current cursor position
+   - Advances the cursor
+   - Sets the overflow flag when wrapping around
+
+3. **Stage Transition**: When transitioning between boot stages:
+   - Pre-RAM console contents are copied to the main CBMEM console
+   - Any overflow condition is preserved and noted
+   - The process ensures no log messages are lost
+
+
+## Common CBMEM Entry Types
+
+CBMEM contains various data structures used by different coreboot
+components:
+
+- **Console**: Log messages from all boot stages (`CBMEM_ID_CONSOLE`)
+- **Timestamps**: Performance metrics (`CBMEM_ID_TIMESTAMP`)
+- **ACPI Tables**: ACPI data for OS handoff (`CBMEM_ID_ACPI`)
+- **coreboot Tables**: System information (`CBMEM_ID_CBTABLE`)
+- **Memory Information**: RAM configuration (`CBMEM_ID_MEMINFO`)
+- **Stage Cache**: Code/data for faster S3 resume
+- **ROM/CBFS Cache**: Cached ROM content
+- **Vendor-specific**: Platform-dependent structures
+
+A complete list of IDs is defined in
+`src/commonlib/bsd/include/commonlib/bsd/cbmem_id.h`.
+
+
+## Integration with Boot Stages
+
+CBMEM interacts differently with each coreboot boot stage.
+
+
+### Bootblock/Romstage
+
+- Uses cache-as-RAM for temporary console storage
+- Limited CBMEM functionality before RAM initialization
+- Sets up initial timestamp entries
+
+
+### Ramstage
+
+- Full CBMEM initialization or recovery
+- All entries become accessible
+- Most coreboot subsystems interact with CBMEM
+- Console logging is fully operational
+
+
+### Payload Handoff
+
+- CBMEM contents are preserved when transferring to the payload
+- Entries are made available via coreboot tables
+- Common payloads (SeaBIOS, GRUB, etc.) can access CBMEM data
+
+
+## Platform-Specific Considerations
+
+Different platforms have unique requirements for CBMEM implementation.
+
+
+### x86 Platforms
+
+- CBMEM typically located just below 4GiB
+- Often integrates with ACPI resume and SMM operations
+- May need to accommodate memory reserved by legacy components
+
+
+### ARM/RISC-V Platforms
+
+- More flexibility in CBMEM placement
+- Must coordinate with platform-specific memory controllers
+- Memory topology can vary significantly between implementations
+
+
+## CBMEM Hooks
+
+CBMEM provides a hook mechanism to allow subsystems to perform
+initialization or recovery operations when CBMEM becomes available:
+
+```c
+CBMEM_CREATION_HOOK(hook_function);    // First-time creation only
+CBMEM_READY_HOOK(hook_function);       // Any CBMEM initialization
+CBMEM_READY_HOOK_EARLY(hook_function); // Early CBMEM initialization
+```
+
+These macros register functions to be called when CBMEM is initialized,
+allowing components to set up their CBMEM entries at the appropriate time.
+
+
+## Debugging and Utilities
+
+### CBMEM Utility
+
+The `cbmem` utility provides direct access to CBMEM contents on a
+running system. It needs to be built from the coreboot source tree using
+`make -C util/cbmem`. Common uses include:
+
+- Listing all CBMEM entries (`cbmem -l`)
+- Viewing console logs (`cbmem -c`)
+- Analyzing timestamps (`cbmem -t`)
+- Extracting specific entries by ID (`cbmem -e <ID>`)
+
+
+### Debugging Techniques
+
+- CBMEM console contents can be dumped to UART for debugging if serial
+  output is enabled.
+- The console overflow flag (`cbmem -c` output) helps identify if logs
+  were truncated.
+- Size validation within CBMEM helps detect potential memory corruption.
+- Magic numbers provide integrity validation for CBMEM structures.
+- Enabling `CONFIG_CBMEM_CHECKS` in Kconfig adds extra sanity checks
+  that can help catch issues during development.
+
+
+## Limitations
+
+While CBMEM is a powerful tool, it has some inherent limitations:
+
+- **Downward Growth**: The stack-like allocation (growing downwards)
+  means that only the most recently added entry can be removed. This
+  prevents fragmentation but limits flexibility in freeing memory.
+- **Fixed Size**: Once CBMEM is initialized in ramstage, its total size
+  and top address (`cbmem_top`) are fixed. Entries cannot be resized
+  after allocation.
+- **Platform Complexity**: Determining the correct `cbmem_top` can be
+  complex on some platforms due to varying memory maps and reserved
+  regions.
+
+
+## Best Practices for Developers
+
+When working with the CBMEM subsystem:
+
+1. **Alignment**: Always respect the alignment requirements of the
+   CBMEM tier (`IMD_ROOT` vs `IMD_SMALL`) you are using.
+
+2. **ID Selection**: Use unique, meaningful IDs for new entries,
+   preferably encoding ASCII characters for readability (see
+   `cbmem_id.h`).
+
+3. **Size Estimation**: Allocate sufficient space initially, as
+   entries cannot be resized.
+
+4. **Memory Conservation**: Be mindful of limited memory resources,
+   especially on constrained platforms. Avoid storing excessively large
+   data structures in CBMEM unless necessary.
+
+5. **Persistence**: Remember that CBMEM contents persist across
+   warm reboots (like S3 resume) but not across full system resets
+   (cold boots).
+
+6. **Entry Ordering**: Consider that only the most recently added
+   entry can be removed, which might influence your allocation strategy
+   if you anticipate needing to free space.

From 11b1dc0a9707fdd417bae4873ed4e76638ca60b2 Mon Sep 17 00:00:00 2001
From: Jakub Czapiga <czapiga@google.com>
Date: Fri, 13 Jun 2025 15:12:05 +0000
Subject: [PATCH 1504/3886] Reapply "util/cbmem: Consolidate CBMEM and coreboot
 table access"

This reverts commit 712dfb376136a9d69451624c59c0dd6b880a3597.

printf formats fixed to use PRI* macros instead of raw values.

BUG=b:391874512
TEST=cbmem -l; cbmem -x; cbmem -r 434f4e53; cbmem -t; cbmem -c \
On both x86 (Brya) and ARM64 (Corsola)

Change-Id: Iba6e3af080fe10c4a55adfcaee9c373a2cce1378
Signed-off-by: Jakub Czapiga <czapiga@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88292
Reviewed-by: Jon Murphy <jpmurphy@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 util/cbmem/cbmem.c | 683 +++++++++++++++++++++++----------------------
 1 file changed, 353 insertions(+), 330 deletions(-)

diff --git a/util/cbmem/cbmem.c b/util/cbmem/cbmem.c
index bdb6794dbf..f80d334962 100644
--- a/util/cbmem/cbmem.c
+++ b/util/cbmem/cbmem.c
@@ -35,9 +35,6 @@
 #include <x86intrin.h>
 #endif
 
-/* Return < 0 on error, 0 on success. */
-static int parse_cbtable(uint64_t address, size_t table_size);
-
 struct mapping {
 	void *virt;
 	size_t offset;
@@ -56,9 +53,6 @@ static int verbose = 0;
 static int mem_fd;
 static struct mapping lbtable_mapping;
 
-/* TSC frequency from the LB_TAG_TSC_INFO record. 0 if not present. */
-static uint32_t tsc_freq_khz = 0;
-
 static void die(const char *msg)
 {
 	if (msg)
@@ -195,57 +189,6 @@ static void *aligned_memcpy(void *dest, const void *src, size_t n)
 	return dest;
 }
 
-/* Find the first cbmem entry filling in the details. */
-static int find_cbmem_entry(uint32_t id, uint64_t *addr, size_t *size)
-{
-	const uint8_t *table;
-	size_t offset;
-	int ret = -1;
-
-	table = mapping_virt(&lbtable_mapping);
-
-	if (table == NULL)
-		return -1;
-
-	offset = 0;
-
-	while (offset < mapping_size(&lbtable_mapping)) {
-		const struct lb_record *lbr;
-		struct lb_cbmem_entry lbe;
-
-		lbr = (const void *)(table + offset);
-		offset += lbr->size;
-
-		if (lbr->tag != LB_TAG_CBMEM_ENTRY)
-			continue;
-
-		aligned_memcpy(&lbe, lbr, sizeof(lbe));
-		if (lbe.id != id)
-			continue;
-
-		*addr = lbe.address;
-		*size = lbe.entry_size;
-		ret = 0;
-		break;
-	}
-
-	return ret;
-}
-
-/*
- * Try finding the timestamp table and coreboot cbmem console starting from the
- * passed in memory offset.  Could be called recursively in case a forwarding
- * entry is found.
- *
- * Returns pointer to a memory buffer containing the timestamp table or zero if
- * none found.
- */
-
-static struct lb_cbmem_ref timestamps;
-static struct lb_cbmem_ref console;
-static struct lb_cbmem_ref tpm_cb_log;
-static struct lb_memory_range cbmem;
-
 /* This is a work-around for a nasty problem introduced by initially having
  * pointer sized entries in the lb_cbmem_ref structures. This caused problems
  * on 64bit x86 systems because coreboot is 32bit on those systems.
@@ -267,90 +210,168 @@ static struct lb_cbmem_ref parse_cbmem_ref(const struct lb_cbmem_ref *cbmem_ref)
 	return ret;
 }
 
-static void parse_memory_tags(const struct lb_memory *mem)
+static uint32_t cbmem_id_to_lb_tag(uint32_t tag)
 {
-	int num_entries;
-	int i;
-
-	/* Peel off the header size and calculate the number of entries. */
-	num_entries = (mem->size - sizeof(*mem)) / sizeof(mem->map[0]);
-
-	for (i = 0; i < num_entries; i++) {
-		if (mem->map[i].type != LB_MEM_TABLE)
-			continue;
-		debug("      LB_MEM_TABLE found.\n");
-		/* The last one found is CBMEM */
-		aligned_memcpy(&cbmem, &mem->map[i], sizeof(cbmem));
+	/* Minimal subset. Expand based on the CBMEM to coreboot table
+	   records mapping in lib/coreboot_table.c */
+	switch (tag) {
+	case CBMEM_ID_TIMESTAMP:
+		return LB_TAG_TIMESTAMPS;
+	case CBMEM_ID_CONSOLE:
+		return LB_TAG_CBMEM_CONSOLE;
+	case CBMEM_ID_TPM_CB_LOG:
+		return LB_TAG_TPM_CB_LOG;
 	}
+	return LB_TAG_UNUSED;
 }
 
-/* Return < 0 on error, 0 on success, 1 if forwarding table entry found. */
-static int parse_cbtable_entries(const struct mapping *table_mapping)
+struct cbmem_console {
+	uint32_t size;
+	uint32_t cursor;
+	uint8_t body[];
+} __packed;
+
+#define CBMC_CURSOR_MASK ((1 << 28) - 1)
+#define CBMC_OVERFLOW    (1 << 31)
+
+
+/* Find the first cbmem entry filling in the details. */
+static int find_cbmem_entry(uint32_t id, uint64_t *addr, size_t *size)
 {
-	size_t i;
-	const struct lb_record *lbr_p;
-	size_t table_size = mapping_size(table_mapping);
-	const void *lbtable = mapping_virt(table_mapping);
-	int forwarding_table_found = 0;
+	const uint8_t *table;
+	size_t offset = 0;
+	const uint32_t legacy_tag = cbmem_id_to_lb_tag(id);
+	struct lb_cbmem_ref *ref = NULL;
 
-	for (i = 0; i < table_size; i += lbr_p->size) {
-		lbr_p = lbtable + i;
-		debug("  coreboot table entry 0x%02x\n", lbr_p->tag);
-		switch (lbr_p->tag) {
-		case LB_TAG_MEMORY:
-			debug("    Found memory map.\n");
-			parse_memory_tags(lbtable + i);
-			continue;
-		case LB_TAG_TIMESTAMPS: {
-			debug("    Found timestamp table.\n");
-			timestamps =
-			    parse_cbmem_ref((struct lb_cbmem_ref *)lbr_p);
-			continue;
-		}
-		case LB_TAG_CBMEM_CONSOLE: {
-			debug("    Found cbmem console.\n");
-			console = parse_cbmem_ref((struct lb_cbmem_ref *)lbr_p);
-			continue;
-		}
-		case LB_TAG_TPM_CB_LOG: {
-			debug("    Found TPM CB log table.\n");
-			tpm_cb_log =
-			    parse_cbmem_ref((struct lb_cbmem_ref *)lbr_p);
-			continue;
-		}
-		case LB_TAG_TSC_INFO:
-			debug("    Found TSC info.\n");
-			tsc_freq_khz = ((struct lb_tsc_info *)lbr_p)->freq_khz;
-			continue;
-		case LB_TAG_FORWARD: {
-			int ret;
-			/*
-			 * This is a forwarding entry - repeat the
-			 * search at the new address.
-			 */
-			struct lb_forward lbf_p =
-			    *(const struct lb_forward *)lbr_p;
-			debug("    Found forwarding entry.\n");
-			ret = parse_cbtable(lbf_p.forward, 0);
+	table = mapping_virt(&lbtable_mapping);
 
-			/* Assume the forwarding entry is valid. If this fails
-			 * then there's a total failure. */
-			if (ret < 0)
-				return -1;
-			forwarding_table_found = 1;
-		}
-		default:
-			break;
-		}
+	if (table == NULL)
+		return -1;
+
+	const struct lb_record *lbr = NULL;
+	while (offset < mapping_size(&lbtable_mapping)) {
+		lbr = (const void *)(table + offset);
+		offset += lbr->size;
+
+		/* Store coreboot table entry for later if CBMEM entry does not exist.
+		   CBMEM entry stores size including the reserved area, so prefer it,
+		   so more potential data and/or space is available. */
+		if (legacy_tag != LB_TAG_UNUSED && lbr->tag == legacy_tag)
+			ref = (struct lb_cbmem_ref *)lbr;
+
+		if (lbr->tag != LB_TAG_CBMEM_ENTRY)
+			continue;
+
+		struct lb_cbmem_entry lbe;
+		aligned_memcpy(&lbe, lbr, sizeof(lbe));
+		if (lbe.id != id)
+			continue;
+
+		*addr = lbe.address;
+		*size = lbe.entry_size;
+		return 0;
 	}
 
-	return forwarding_table_found;
+	/* No mapping and/or no potential reference means that
+	   the requested entry does not exit. */
+	if (legacy_tag == LB_TAG_UNUSED || ref == NULL)
+		return -1;
+
+	debug("Found coreboot table record equivalent of CBMEM entry id: %#x, tag: %#x\n", id,
+	      legacy_tag);
+
+	const struct lb_cbmem_ref lbc = parse_cbmem_ref(ref);
+	size_t header_map_size = 0;
+
+	/* Process legacy coreboot table entries */
+	switch (lbc.tag) {
+	case LB_TAG_TIMESTAMPS:
+		header_map_size = sizeof(struct timestamp_table);
+		break;
+	case LB_TAG_CBMEM_CONSOLE:
+		header_map_size = sizeof(struct cbmem_console);
+		break;
+	case LB_TAG_TPM_CB_LOG:
+		header_map_size = sizeof(struct tpm_cb_log_table);
+		break;
+	}
+
+	struct mapping entry_mapping;
+	const void *entry_header = NULL;
+
+	entry_header = map_memory(&entry_mapping, lbc.cbmem_addr, header_map_size);
+	if (!entry_header) {
+		fprintf(stderr, "Unable to map header for coreboot table entry id: %#x\n",
+			legacy_tag);
+		abort();
+	}
+
+	*addr = lbc.cbmem_addr;
+
+	switch (legacy_tag) {
+	case LB_TAG_TIMESTAMPS: {
+		const struct timestamp_table *tst_p = entry_header;
+		*size = sizeof(*tst_p) + tst_p->num_entries * sizeof(tst_p->entries[0]);
+		break;
+	}
+	case LB_TAG_CBMEM_CONSOLE: {
+		const struct cbmem_console *console_p = entry_header;
+		*size = sizeof(*console_p) + console_p->size;
+		break;
+	}
+	case LB_TAG_TPM_CB_LOG: {
+		const struct tpm_cb_log_table *tclt_p = entry_header;
+		*size = sizeof(*tclt_p) + tclt_p->num_entries * sizeof(tclt_p->entries[0]);
+		break;
+	}
+	}
+
+	unmap_memory(&entry_mapping);
+
+	return 0;
+}
+
+/**
+ * Returns pointer to allocated buffer and size of the buffer in parameters.
+ * Returns zero on success.
+ * free() buffer after use.
+ */
+static int get_cbmem_entry(uint32_t id, uint8_t **buf_out, size_t *size_out)
+{
+	uint64_t addr;
+	size_t size;
+	struct mapping cbmem_mapping;
+
+	if (find_cbmem_entry(id, &addr, &size)) {
+		debug("CBMEM entry not found. CBMEM id: %#x\n", id);
+		return -1;
+	}
+
+	const uint8_t *buf = map_memory(&cbmem_mapping, addr, size);
+	if (!buf) {
+		fprintf(stderr, "Unable to map CBMEM entry id: %#x, size: %zu\n", id, size);
+		abort();
+	}
+
+	*buf_out = malloc(size);
+	if (!*buf_out) {
+		unmap_memory(&cbmem_mapping);
+		fprintf(stderr,
+			"Unable to allocate memory for CBMEM entry id: %#x, size: %zu\n", id,
+			size);
+		abort();
+	}
+
+	aligned_memcpy(*buf_out, buf, size);
+	unmap_memory(&cbmem_mapping);
+	*size_out = size;
+	return 0;
 }
 
 /* Return < 0 on error, 0 on success. */
 static int parse_cbtable(uint64_t address, size_t table_size)
 {
-	const void *buf;
+	const uint8_t *buf;
 	struct mapping header_mapping;
 	size_t req_size;
 	size_t i;
@@ -360,8 +381,7 @@ static int parse_cbtable(uint64_t address, size_t table_size)
 	if (req_size == 0)
 		req_size = 4 * 1024;
 
-	debug("Looking for coreboot table at %" PRIx64 " %zd bytes.\n",
-		address, req_size);
+	debug("Looking for coreboot table at %" PRIx64 " %zd bytes.\n", address, req_size);
 
 	buf = map_memory(&header_mapping, address, req_size);
 
@@ -370,11 +390,10 @@ static int parse_cbtable(uint64_t address, size_t table_size)
 
 	/* look at every 16 bytes */
 	for (i = 0; i <= req_size - sizeof(struct lb_header); i += 16) {
-		int ret;
 		const struct lb_header *lbh;
 		struct mapping table_mapping;
 
-		lbh = buf + i;
+		lbh = (const struct lb_header *)&buf[i];
 		if (memcmp(lbh->signature, "LBIO", sizeof(lbh->signature)) ||
 		    !lbh->header_bytes ||
 		    ipchksum(lbh, sizeof(*lbh))) {
@@ -395,27 +414,32 @@ static int parse_cbtable(uint64_t address, size_t table_size)
 			continue;
 		}
 
-		debug("Found!\n");
+		debug("Found at %#" PRIx64 "\n", address + i);
 
-		ret = parse_cbtable_entries(&table_mapping);
+		const struct lb_record *lbr_p;
+		const uint8_t *lbtable = mapping_virt(&table_mapping);
 
-		/* Table parsing failed. */
-		if (ret < 0) {
+		for (size_t offset = 0; offset < lbh->table_bytes; offset += lbr_p->size) {
+			lbr_p = (const struct lb_record *)&lbtable[offset];
+			debug("  coreboot table entry 0x%02x\n", lbr_p->tag);
+
+			if (lbr_p->tag != LB_TAG_FORWARD)
+				continue;
+
+			/* This is a forwarding entry. Repeat the search at the new address. */
+			struct lb_forward lbf_p = *(const struct lb_forward *)lbr_p;
+			debug("    Found forwarding entry.\n");
+
+			const uint64_t next_addr = lbf_p.forward;
+			unmap_memory(&header_mapping);
 			unmap_memory(&table_mapping);
-			continue;
+
+			return parse_cbtable(next_addr, 0);
 		}
 
-		/* Succeeded in parsing the table. Header not needed anymore. */
+		debug("correct coreboot table found.\n");
 		unmap_memory(&header_mapping);
-
-		/*
-		 * Table parsing succeeded. If forwarding table not found update
-		 * coreboot table mapping for future use.
-		 */
-		if (ret == 0)
-			lbtable_mapping = table_mapping;
-		else
-			unmap_memory(&table_mapping);
+		lbtable_mapping = table_mapping;
 
 		return 0;
 	}
@@ -425,6 +449,78 @@ static int parse_cbtable(uint64_t address, size_t table_size)
 	return -1;
 }
 
+static void lb_table_get_entry(uint32_t tag, uint8_t **buf_out, size_t *size_out)
+{
+	const struct lb_record *lbr_p;
+	const uint8_t *lbtable_raw;
+	size_t table_size;
+	bool tag_found = false;
+
+	if (get_cbmem_entry(CBMEM_ID_CBTABLE, (uint8_t **)&lbtable_raw, &table_size)) {
+		fprintf(stderr, "coreboot table not found.\n");
+		abort();
+	}
+
+	const struct lb_header *lbh = (const struct lb_header *)lbtable_raw;
+
+	for (size_t i = 0; i < lbh->table_bytes; i += lbr_p->size) {
+		lbr_p = (const struct lb_record *)(&lbtable_raw[lbh->header_bytes + i]);
+		if (lbr_p->tag == tag) {
+			tag_found = true;
+			break;
+		}
+	}
+
+	if (!tag_found) {
+		fprintf(stderr, "coreboot table entry %#x not found.\n", tag);
+		free((void *)lbtable_raw);
+		abort();
+	}
+
+	debug("coreboot table entry %#x found.\n", tag);
+
+	*buf_out = malloc(lbr_p->size);
+	if (!*buf_out) {
+		fprintf(stderr,
+			"Unable to allocate memory for coreboot table entry %#x, size: %d\n",
+			tag, lbr_p->size);
+		free((void *)lbtable_raw);
+		abort();
+	}
+	memcpy(*buf_out, lbr_p, lbr_p->size);
+	*size_out = lbr_p->size;
+	free((void *)lbtable_raw);
+}
+
+
+/**
+ * Returns mapping, mapped buffer pointer and its size by parameters.
+ * Returns zero on success.
+ * unmap_mempry() after use.
+ */
+static int map_cbmem_entry_rw(uint32_t id, struct mapping *mapping, uint8_t **buf_out,
+			       size_t *size_out)
+{
+	uint64_t addr;
+	size_t size;
+
+	if (find_cbmem_entry(id, &addr, &size)) {
+		debug("CBMEM entry not found. CBMEM id: %#x\n", id);
+		return -1;
+	}
+
+	*buf_out = map_memory_with_prot(mapping, addr, size, PROT_READ | PROT_WRITE);
+	if (!*buf_out) {
+		fprintf(stderr,
+			"Unable to map CBMEM entry id: %#x, size: %zu for read-write access.\n",
+			id, size);
+		abort();
+	}
+
+	*size_out = size;
+	return 0;
+}
+
 #if defined(linux) && (defined(__i386__) || defined(__x86_64__))
 /*
  * read CPU frequency from a sysfs file, return an frequency in Megahertz as
@@ -528,11 +624,19 @@ static uint64_t timestamp_get(uint64_t table_tick_freq_mhz)
 {
 #if defined(__i386__) || defined(__x86_64__)
 	uint64_t tsc = __rdtsc();
+	struct lb_tsc_info *tsc_info;
+	size_t size;
 
 	/* No tick frequency specified means raw TSC values. */
 	if (!table_tick_freq_mhz)
 		return tsc;
 
+	lb_table_get_entry(LB_TAG_TSC_INFO, (uint8_t **)&tsc_info, &size);
+
+	const uint32_t tsc_freq_khz = tsc_info->freq_khz;
+
+	free(tsc_info);
+
 	if (tsc_freq_khz)
 		return tsc * table_tick_freq_mhz * 1000 / tsc_freq_khz;
 #else
@@ -679,34 +783,23 @@ static void dump_timestamps(enum timestamps_print_type output_type)
 	size_t size;
 	uint64_t prev_stamp = 0;
 	uint64_t total_time = 0;
-	struct mapping timestamp_mapping;
 
-	if (timestamps.tag != LB_TAG_TIMESTAMPS) {
-		fprintf(stderr, "No timestamps found in coreboot table.\n");
-		return;
+	if (get_cbmem_entry(CBMEM_ID_TIMESTAMP, (uint8_t **)&tst_p, &size)) {
+		fprintf(stderr, "Timestamps not found.\n");
+		abort();
 	}
 
-	size = sizeof(*tst_p);
-	tst_p = map_memory(&timestamp_mapping, timestamps.cbmem_addr, size);
-	if (!tst_p)
-		die("Unable to map timestamp header\n");
-
 	timestamp_set_tick_freq(tst_p->tick_freq_mhz);
 
 	if (output_type == TIMESTAMPS_PRINT_NORMAL)
 		printf("%d entries total:\n\n", tst_p->num_entries);
-	size += tst_p->num_entries * sizeof(tst_p->entries[0]);
-
-	unmap_memory(&timestamp_mapping);
-
-	tst_p = map_memory(&timestamp_mapping, timestamps.cbmem_addr, size);
-	if (!tst_p)
-		die("Unable to map full timestamp table\n");
 
 	sorted_tst_p = malloc(size + sizeof(struct timestamp_entry));
-	if (!sorted_tst_p)
+	if (!sorted_tst_p) {
+		free((void *)tst_p);
 		die("Failed to allocate memory");
-	aligned_memcpy(sorted_tst_p, tst_p, size);
+	}
+	memcpy(sorted_tst_p, tst_p, size);
 
 	/*
 	 * Insert a timestamp to represent the base time (start of coreboot),
@@ -783,8 +876,8 @@ static void dump_timestamps(enum timestamps_print_type output_type)
 		printf("\n");
 	}
 
-	unmap_memory(&timestamp_mapping);
 	free(sorted_tst_p);
+	free((void *)tst_p);
 }
 
 /* add a timestamp entry */
@@ -792,16 +885,14 @@ static void timestamp_add_now(uint32_t timestamp_id)
 {
 	struct timestamp_table *tst_p;
 	struct mapping timestamp_mapping;
+	size_t tst_size;
 
-	if (timestamps.tag != LB_TAG_TIMESTAMPS) {
-		die("No timestamps found in coreboot table.\n");
+	if (map_cbmem_entry_rw(CBMEM_ID_TIMESTAMP, &timestamp_mapping, (uint8_t **)&tst_p,
+			       &tst_size)) {
+		fprintf(stderr, "Unable to find timestamps.\n");
+		abort();
 	}
 
-	tst_p = map_memory_with_prot(&timestamp_mapping, timestamps.cbmem_addr,
-				     timestamps.size, PROT_READ | PROT_WRITE);
-	if (!tst_p)
-		die("Unable to map timestamp table\n");
-
 	/*
 	 * Note that coreboot sizes the cbmem entry in the table according to
 	 * max_entries, so it's OK to just add more entries if there's room.
@@ -995,32 +1086,24 @@ static void parse_tpm2_log(const struct tcg_efi_spec_id_event *tpm2_log)
 }
 
 /* Dump the TPM log table in format defined by specifications */
-static void dump_tpm_std_log(uint64_t addr, size_t size)
+static void dump_tpm_std_log(void *buf)
 {
-	const void *event_log;
 	const struct tcpa_spec_entry *tspec_entry;
 	const struct tcg_efi_spec_id_event *tcg_spec_entry;
-	struct mapping log_mapping;
 
-	event_log = map_memory(&log_mapping, addr, size);
-	if (!event_log)
-		die("Unable to map TPM eventlog\n");
-
-	tspec_entry = event_log;
+	tspec_entry = buf;
 	if (!strcmp((const char *)tspec_entry->signature, TCPA_SPEC_ID_EVENT_SIGNATURE)) {
 		if (tspec_entry->spec_version_major == 1 &&
-		    tspec_entry->spec_version_minor == 2 &&
-		    tspec_entry->spec_errata >= 1 &&
+		    tspec_entry->spec_version_minor == 2 && tspec_entry->spec_errata >= 1 &&
 		    le32toh(tspec_entry->entry.event_type) == EV_NO_ACTION) {
 			parse_tpm12_log(tspec_entry);
 		} else {
 			fprintf(stderr, "Unknown TPM1.2 log specification\n");
 		}
-		unmap_memory(&log_mapping);
 		return;
 	}
 
-	tcg_spec_entry = event_log;
+	tcg_spec_entry = buf;
 	if (!strcmp((const char *)tcg_spec_entry->signature, TCG_EFI_SPEC_ID_EVENT_SIGNATURE)) {
 		if (tcg_spec_entry->spec_version_major == 2 &&
 		    tcg_spec_entry->spec_version_minor == 0 &&
@@ -1029,42 +1112,25 @@ static void dump_tpm_std_log(uint64_t addr, size_t size)
 		} else {
 			fprintf(stderr, "Unknown TPM2 log specification.\n");
 		}
-		unmap_memory(&log_mapping);
 		return;
 	}
 
 	fprintf(stderr, "Unknown TPM log specification: %.*s\n",
 		(int)sizeof(tcg_spec_entry->signature),
 		(const char *)tcg_spec_entry->signature);
-
-	unmap_memory(&log_mapping);
 }
 
 /* dump the TPM CB log table */
 static void dump_tpm_cb_log(void)
 {
 	const struct tpm_cb_log_table *tclt_p;
-	size_t size;
-	struct mapping log_mapping;
+	size_t tclt_size;
 
-	if (tpm_cb_log.tag != LB_TAG_TPM_CB_LOG) {
-		fprintf(stderr, "No TPM log found in coreboot table.\n");
-		return;
+	if (get_cbmem_entry(CBMEM_ID_TPM_CB_LOG, (uint8_t **)&tclt_p, &tclt_size)) {
+		fprintf(stderr, "coreboot TPM log not found.\n");
+		abort();
 	}
 
-	size = sizeof(*tclt_p);
-	tclt_p = map_memory(&log_mapping, tpm_cb_log.cbmem_addr, size);
-	if (!tclt_p)
-		die("Unable to map TPM log header\n");
-
-	size += tclt_p->num_entries * sizeof(tclt_p->entries[0]);
-
-	unmap_memory(&log_mapping);
-
-	tclt_p = map_memory(&log_mapping, tpm_cb_log.cbmem_addr, size);
-	if (!tclt_p)
-		die("Unable to map full TPM log table\n");
-
 	printf("coreboot TPM log:\n\n");
 
 	for (uint16_t i = 0; i < tclt_p->num_entries; i++) {
@@ -1075,30 +1141,22 @@ static void dump_tpm_cb_log(void)
 		printf(" %s [%s]\n", tce->digest_type, tce->name);
 	}
 
-	unmap_memory(&log_mapping);
+	free((void *)tclt_p);
 }
 
 static void dump_tpm_log(void)
 {
-	uint64_t start;
+	uint8_t *buf;
 	size_t size;
 
-	if (!find_cbmem_entry(CBMEM_ID_TCPA_TCG_LOG, &start, &size) ||
-	    !find_cbmem_entry(CBMEM_ID_TPM2_TCG_LOG, &start, &size))
-		dump_tpm_std_log(start, size);
-	else
+	if (!get_cbmem_entry(CBMEM_ID_TCPA_TCG_LOG, &buf, &size) ||
+	    !get_cbmem_entry(CBMEM_ID_TPM2_TCG_LOG, &buf, &size)) {
+		dump_tpm_std_log(buf);
+		free(buf);
+	} else
 		dump_tpm_cb_log();
 }
 
-struct cbmem_console {
-	uint32_t size;
-	uint32_t cursor;
-	uint8_t  body[];
-}  __attribute__ ((__packed__));
-
-#define CBMC_CURSOR_MASK ((1 << 28) - 1)
-#define CBMC_OVERFLOW (1 << 31)
-
 enum console_print_type {
 	CONSOLE_PRINT_FULL = 0,
 	CONSOLE_PRINT_LAST,
@@ -1134,50 +1192,37 @@ static void dump_console(enum console_print_type type, int max_loglevel, int pri
 	const struct cbmem_console *console_p;
 	char *console_c;
 	size_t size, cursor, previous;
-	struct mapping console_mapping;
+	size_t console_buf_size;
 
-	if (console.tag != LB_TAG_CBMEM_CONSOLE) {
-		fprintf(stderr, "No console found in coreboot table.\n");
-		return;
+	if (get_cbmem_entry(CBMEM_ID_CONSOLE, (uint8_t **)&console_p, &console_buf_size)) {
+		fprintf(stderr, "CBMEM console not found.\n");
+		abort();
 	}
 
-	size = sizeof(*console_p);
-	console_p = map_memory(&console_mapping, console.cbmem_addr, size);
-	if (!console_p)
-		die("Unable to map console object.\n");
-
 	cursor = console_p->cursor & CBMC_CURSOR_MASK;
 	if (!(console_p->cursor & CBMC_OVERFLOW) && cursor < console_p->size)
 		size = cursor;
 	else
 		size = console_p->size;
-	unmap_memory(&console_mapping);
 
 	console_c = malloc(size + 1);
 	if (!console_c) {
 		fprintf(stderr, "Not enough memory for console.\n");
-		exit(1);
+		free((void *)console_p);
+		abort();
 	}
 	console_c[size] = '\0';
 
-	console_p = map_memory(&console_mapping, console.cbmem_addr,
-		size + sizeof(*console_p));
-
-	if (!console_p)
-		die("Unable to map full console object.\n");
-
 	if (console_p->cursor & CBMC_OVERFLOW) {
 		if (cursor >= size) {
 			printf("cbmem: ERROR: CBMEM console struct is illegal, "
 			       "output may be corrupt or out of order!\n\n");
 			cursor = 0;
 		}
-		aligned_memcpy(console_c, console_p->body + cursor,
-			       size - cursor);
-		aligned_memcpy(console_c + size - cursor,
-			       console_p->body, cursor);
+		memcpy(console_c, console_p->body + cursor, size - cursor);
+		memcpy(console_c + size - cursor, console_p->body, cursor);
 	} else {
-		aligned_memcpy(console_c, console_p->body, size);
+		memcpy(console_c, console_p->body, size);
 	}
 
 	/* Slight memory corruption may occur between reboots and give us a few
@@ -1252,109 +1297,88 @@ static void dump_console(enum console_print_type type, int max_loglevel, int pri
 		printf(BIOS_LOG_ESCAPE_RESET);
 
 	free(console_c);
-	unmap_memory(&console_mapping);
+	free((void *)console_p);
 }
 
-static void hexdump(unsigned long memory, int length)
+/* Hexdump provided buffer using start_address as an offset in the output. */
+static void hexdump(const uintptr_t start_address, const uint8_t *buf, const int length)
 {
 	int i;
-	const uint8_t *m;
 	int all_zero = 0;
-	struct mapping hexdump_mapping;
-
-	m = map_memory(&hexdump_mapping, memory, length);
-	if (!m)
-		die("Unable to map hexdump memory.\n");
 
 	for (i = 0; i < length; i += 16) {
 		int j;
 
 		all_zero++;
 		for (j = 0; j < 16; j++) {
-			if(m[i+j] != 0) {
+			if (buf[i + j] != 0) {
 				all_zero = 0;
 				break;
 			}
 		}
 
 		if (all_zero < 2) {
-			printf("%08lx:", memory + i);
+			printf("%08" PRIxPTR ":", start_address + i);
 			for (j = 0; j < 16; j++)
-				printf(" %02x", m[i+j]);
+				printf(" %02x", buf[i + j]);
 			printf("  ");
 			for (j = 0; j < 16; j++)
-				printf("%c", isprint(m[i+j]) ? m[i+j] : '.');
+				printf("%c", isprint(buf[i + j]) ? buf[i + j] : '.');
 			printf("\n");
 		} else if (all_zero == 2) {
 			printf("...\n");
 		}
 	}
-
-	unmap_memory(&hexdump_mapping);
 }
 
 static void dump_cbmem_hex(void)
 {
-	if (cbmem.type != LB_MEM_TABLE) {
-		fprintf(stderr, "No coreboot CBMEM area found!\n");
-		return;
+	struct mapping cbmem_mapping;
+	struct lb_memory *memory;
+	const uint8_t *buf = NULL;
+	size_t size = 0;
+
+	lb_table_get_entry(LB_TAG_MEMORY, (uint8_t **)&memory, &size);
+
+	if (!memory)
+		die("No memory entries available.\n");
+
+	const int entries = (memory->size - sizeof(*memory)) / sizeof(memory->map[0]);
+	/* First from the end is CBMEM */
+	for (int i = entries - 1; i >= 0; --i) {
+		if (memory->map[i].type != LB_MEM_TABLE)
+			continue;
+
+		buf = map_memory(&cbmem_mapping, memory->map[i].start, memory->map[i].size);
+		if (!buf)
+			die("Unable to map CBMEM area memory.\n");
+
+		size = memory->map[i].size;
+		break;
 	}
 
-	hexdump(cbmem.start, cbmem.size);
-}
+	if (!buf)
+		die("Unable to find CBMEM area memory entry.\n");
 
-static void rawdump(uint64_t base, uint64_t size)
-{
-	const uint8_t *m;
-	struct mapping dump_mapping;
+	hexdump(cbmem_mapping.phys, buf, size);
 
-	m = map_memory(&dump_mapping, base, size);
-	if (!m)
-		die("Unable to map rawdump memory\n");
-
-	for (uint64_t i = 0 ; i < size; i++)
-		printf("%c", m[i]);
-
-	unmap_memory(&dump_mapping);
+	unmap_memory(&cbmem_mapping);
+	free(memory);
 }
 
 static void dump_cbmem_raw(unsigned int id)
 {
-	const uint8_t *table;
-	size_t offset;
-	uint64_t base = 0;
-	uint64_t size = 0;
+	uint8_t *buf;
+	size_t size;
 
-	table = mapping_virt(&lbtable_mapping);
-
-	if (table == NULL)
-		return;
-
-	offset = 0;
-
-	while (offset < mapping_size(&lbtable_mapping)) {
-		const struct lb_record *lbr;
-		struct lb_cbmem_entry lbe;
-
-		lbr = (const void *)(table + offset);
-		offset += lbr->size;
-
-		if (lbr->tag != LB_TAG_CBMEM_ENTRY)
-			continue;
-
-		aligned_memcpy(&lbe, lbr, sizeof(lbe));
-		if (lbe.id == id) {
-			debug("found id for raw dump %0x", lbe.id);
-			base = lbe.address;
-			size = lbe.entry_size;
-			break;
-		}
+	if (get_cbmem_entry(id, &buf, &size)) {
+		fprintf(stderr, "cbmem entry id: %#x not found.\n", id);
+		abort();
 	}
 
-	if (!base)
-		fprintf(stderr, "id %0x not found in cbtable\n", id);
-	else
-		rawdump(base, size);
+	fwrite(buf, 1, size, stdout);
+
+	free(buf);
 }
 
 struct cbmem_id_to_name {
@@ -1399,34 +1423,31 @@ static void cbmem_print_entry(int n, uint32_t id, uint64_t base, uint64_t size)
 
 static void dump_cbmem_toc(void)
 {
-	int i;
-	const uint8_t *table;
-	size_t offset;
+	int i = 0;
+	const uint8_t *table = NULL;
+	size_t table_size = 0;
 
-	table = mapping_virt(&lbtable_mapping);
+	if (get_cbmem_entry(CBMEM_ID_CBTABLE, (uint8_t **)&table, &table_size)) {
+		fprintf(stderr, "coreboot table not found.\n");
+		abort();
+	}
 
-	if (table == NULL)
-		return;
+	const struct lb_header *lbh = (const struct lb_header *)table;
 
 	printf("CBMEM table of contents:\n");
-	printf("    %-20s  %-8s  %-8s  %-8s\n", "NAME", "ID", "START",
-			"LENGTH");
+	printf("    %-20s  %-8s  %-8s  %-8s\n", "NAME", "ID", "START", "LENGTH");
 
-	i = 0;
-	offset = 0;
-
-	while (offset < mapping_size(&lbtable_mapping)) {
-		const struct lb_record *lbr;
-		struct lb_cbmem_entry lbe;
-
-		lbr = (const void *)(table + offset);
-		offset += lbr->size;
+	const struct lb_record *lbr = NULL;
+	for (size_t offset = lbh->header_bytes;
+	     offset < lbh->table_bytes + lbh->header_bytes - sizeof(struct lb_cbmem_entry);
+	     offset += lbr->size) {
+		lbr = (const struct lb_record *)&table[offset];
 
 		if (lbr->tag != LB_TAG_CBMEM_ENTRY)
 			continue;
 
-		aligned_memcpy(&lbe, lbr, sizeof(lbe));
-		cbmem_print_entry(i, lbe.id, lbe.address, lbe.entry_size);
+		const struct lb_cbmem_entry *lbe = (const struct lb_cbmem_entry *)lbr;
+		cbmem_print_entry(i, lbe->id, lbe->address, lbe->entry_size);
 		i++;
 	}
 }
@@ -1461,21 +1482,23 @@ static int mkpath(char *path, mode_t mode)
 static void dump_coverage(void)
 {
 	uint64_t start;
+	uint8_t *coverage;
 	size_t size;
-	const void *coverage;
-	struct mapping coverage_mapping;
 	unsigned long phys_offset;
 #define phys_to_virt(x) ((void *)(unsigned long)(x) + phys_offset)
 
+	if (get_cbmem_entry(CBMEM_ID_COVERAGE, &coverage, &size)) {
+		fprintf(stderr, "No coverage information found\n");
+		return;
+	}
+
+	// Physical address is needed for pointer translation
 	if (find_cbmem_entry(CBMEM_ID_COVERAGE, &start, &size)) {
 		fprintf(stderr, "No coverage information found\n");
 		return;
 	}
 
 	/* Map coverage area */
-	coverage = map_memory(&coverage_mapping, start, size);
-	if (!coverage)
-		die("Unable to map coverage area.\n");
 	phys_offset = (unsigned long)coverage - (unsigned long)start;
 
 	printf("Dumping coverage data...\n");
@@ -1512,7 +1535,7 @@ static void dump_coverage(void)
 		else
 			file = NULL;
 	}
-	unmap_memory(&coverage_mapping);
+	free(coverage);
 }
 
 static void print_version(void)

From f1d06a5ad49e2a8138981661cf5c5c7611e96b05 Mon Sep 17 00:00:00 2001
From: Werner Zeh <werner.zeh@siemens.com>
Date: Tue, 1 Jul 2025 08:11:55 +0200
Subject: [PATCH 1505/3886] soc/intel/common/block/memory: Provide a way to use
 SPD data from memory

There can be cases where it is needed to provide the SPD data in a
different way than an EEPROM or CBFS file. This patch adds a third
method where the SPD data can be provided in a memory buffer for
memory-down configurations. Where this memory buffer comes from
and how SPD data is filled in is up to the mainboard code.

To use this new method set 'spd_data.in_mem' to 'true' and provide a
pointer to the SPD data in memory via 'spd_data.ptr' where
'spd_data.len' holds the length of the SPD data in that buffer.

This feature is useful for Siemens mainboards where the SPD data is part
of a larger configuration block called 'HWInfo block'. Though this block
itself do reside in CBFS, the SPD data cannot simply be indexed into
(like with the cbfs_index). Instead, the hwinfo-lib is used to get
dedicated fields from that block, this includes the SPD data, too. With
this patch the SPD data can be retrieved from HWInfo block and passed as
a buffer to the memory initialization code.

Change-Id: I2bd4970967cfe81bba96d8e2b2fd3a0bb85430c4
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88258
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 .../block/include/intelblocks/meminit.h       | 11 +++++++++
 src/soc/intel/common/block/memory/meminit.c   | 23 ++++++++++++-------
 2 files changed, 26 insertions(+), 8 deletions(-)

diff --git a/src/soc/intel/common/block/include/intelblocks/meminit.h b/src/soc/intel/common/block/include/intelblocks/meminit.h
index a4fb9fa1f3..566efa03d9 100644
--- a/src/soc/intel/common/block/include/intelblocks/meminit.h
+++ b/src/soc/intel/common/block/include/intelblocks/meminit.h
@@ -57,6 +57,17 @@ struct mem_spd {
 	struct {
 		uint8_t addr_dimm[CONFIG_DIMMS_PER_CHANNEL];
 	} smbus[MRC_CHANNELS];
+
+	/* If the SPD data is provided in a memory buffer, spd_data.in_mem needs to be
+	 * set to 'true'. In this case spd_data.ptr points to the memory buffer where the
+	 * SPD data is stored in and spd_data.len stores the length of the SPD data
+	 * in that buffer. In this case cbfs_index is ignored.
+	 */
+	struct {
+		bool in_mem;
+		size_t len;
+		uintptr_t ptr;
+	} spd_data;
 };
 
 /* Information about memory technology supported by SoC */
diff --git a/src/soc/intel/common/block/memory/meminit.c b/src/soc/intel/common/block/memory/meminit.c
index 3c310798d0..fa80017c50 100644
--- a/src/soc/intel/common/block/memory/meminit.c
+++ b/src/soc/intel/common/block/memory/meminit.c
@@ -60,17 +60,24 @@ static void read_spd_md(const struct soc_mem_cfg *soc_mem_cfg, const struct mem_
 
 	if (pop_mask == 0)
 		die("Memory technology does not support the selected configuration!\n");
+	if (!(info->spd_data.in_mem)) {
 
-	printk(BIOS_DEBUG, "SPD index = %zu\n", info->cbfs_index);
+		printk(BIOS_DEBUG, "SPD index = %zu\n", info->cbfs_index);
 
-	/* Memory leak is ok as long as we have memory mapped boot media */
-	_Static_assert(CONFIG(BOOT_DEVICE_MEMORY_MAPPED),
-		"Function assumes memory-mapped boot media");
+		/* Memory leak is ok as long as we have memory mapped boot media */
+		_Static_assert(CONFIG(BOOT_DEVICE_MEMORY_MAPPED),
+				"Function assumes memory-mapped boot media");
 
-	*spd_len = CONFIG_DIMM_SPD_SIZE;
-	spd_data = spd_cbfs_map(info->cbfs_index);
-	if (!spd_data)
-		die("SPD not found in CBFS or incorrect index!\n");
+		*spd_len = CONFIG_DIMM_SPD_SIZE;
+		spd_data = spd_cbfs_map(info->cbfs_index);
+		if (!spd_data)
+			die("SPD not found in CBFS or incorrect index!\n");
+	} else {
+		*spd_len = info->spd_data.len;
+		spd_data = info->spd_data.ptr;
+		if (!spd_data)
+			die("SPD data in memory expected but no buffer provided!\n");
+	}
 
 	print_spd_info((uint8_t *)spd_data);
 

From 689af47b52585ca49f5681e378bbfce6314a76cf Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Bart=C5=82omiej=20Grzesik?= <bgrzesik@google.com>
Date: Thu, 3 Jul 2025 10:07:23 +0200
Subject: [PATCH 1506/3886] commonlib: Add pvmfw related timestamps
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Add 3 new timestamps for measuring the time to setup pvmfw in
depthcharge. First indicate when the setup has started. Second when the
comm with GSC has finished and third when the setup is complete.

BUG=b:429115233
BUG=b:359340876
TEST=build rauru

Change-Id: I0e0d069ae85997d3e4c02f257cd801e7b6787762
Signed-off-by: Bartłomiej Grzesik <bgrzesik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88289
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
---
 src/commonlib/include/commonlib/timestamp_serialized.h | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/src/commonlib/include/commonlib/timestamp_serialized.h b/src/commonlib/include/commonlib/timestamp_serialized.h
index 2af574c088..022725af3e 100644
--- a/src/commonlib/include/commonlib/timestamp_serialized.h
+++ b/src/commonlib/include/commonlib/timestamp_serialized.h
@@ -174,6 +174,10 @@ enum timestamp_id {
 	TS_KERNEL_START = 1101,
 	TS_KERNEL_DECOMPRESSION = 1102,
 
+	TS_PVMFW_SETUP_START = 1110,
+	TS_PVMFW_GSC_NVRAM_DONE = 1111,
+	TS_PVMFW_SETUP_DONE = 1112,
+
 	/* 1200-1300: ChromeOS Hypervisor */
 	TS_CRHV_BOOT = 1200,
 	TS_CRHV_PLATFORM_INIT = 1201,
@@ -371,6 +375,10 @@ static const struct timestamp_id_to_name {
 	TS_NAME_DEF(TS_KERNEL_START, 0, "jumping to kernel"),
 	TS_NAME_DEF(TS_KERNEL_DECOMPRESSION, 0, "starting kernel decompression/relocation"),
 
+	TS_NAME_DEF(TS_PVMFW_SETUP_START, 0, "started pvmfw setup"),
+	TS_NAME_DEF(TS_PVMFW_GSC_NVRAM_DONE, 0, "finished fetching boot params from GSC"),
+	TS_NAME_DEF(TS_PVMFW_SETUP_DONE, 0, "finished pvmfw setup"),
+
 	/* ChromeOS hypervisor */
 	TS_NAME_DEF(TS_CRHV_BOOT, 0, "hypervisor boot finished"),
 	TS_NAME_DEF(TS_CRHV_PLATFORM_INIT, 0, "hypervisor platform initialized"),

From f323adb19fc43589c8df1c029f64621f90da7084 Mon Sep 17 00:00:00 2001
From: Vince Liu <vince-wl.liu@mediatek.corp-partner.google.com>
Date: Wed, 25 Jun 2025 08:48:12 +0800
Subject: [PATCH 1507/3886] soc/mediatek/mt8189: Increase SPI NOR clock rate
 from 26MHz to 52MHz

Set SPI NOR clock from 26MHz to 52MHz to improve boot time.

BUG=b:379008996
BRANCH=none
TEST=Verified clock rate via oscilloscope, and measure boot time with
cbmem
(previous) Total Time: 800,539
(now) Total Time: 739,292

Signed-off-by: Vince Liu <vince-wl.liu@mediatek.corp-partner.google.com>
Change-Id: Ibe3df8200417fa9a8292bfd3c29339b7d125e3c4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88339
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
---
 src/soc/mediatek/mt8189/pll.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/soc/mediatek/mt8189/pll.c b/src/soc/mediatek/mt8189/pll.c
index ffd48987e4..c05c39227c 100644
--- a/src/soc/mediatek/mt8189/pll.c
+++ b/src/soc/mediatek/mt8189/pll.c
@@ -261,7 +261,7 @@ static const struct mux_sel mux_sels[] = {
 	{ .id = CLK_TOP_DP_SEL, .sel = 4 },
 	{ .id = CLK_TOP_EDP_SEL, .sel = 4 },
 	{ .id = CLK_TOP_EDP_FAVT_SEL, .sel = 4 },
-	{ .id = CLK_TOP_SFLASH_SEL, .sel = 0 },
+	{ .id = CLK_TOP_SFLASH_SEL, .sel = 2 },
 	{ .id = CLK_TOP_ECC_SEL, .sel = 5 },
 };
 

From 95784dbafb2d5b0980a7613c058a9a1ce1d9bc3c Mon Sep 17 00:00:00 2001
From: Sowmya Aralguppe <sowmya.aralguppe@intel.com>
Date: Mon, 23 Jun 2025 13:56:39 +0530
Subject: [PATCH 1508/3886] mb/google/ocelot/var/ocelot: Add FW_CONFIG for
 Audio

Add FW_CONFIG probe based on Ocelot for Audio device:
	1.HDA Interface
	2.SNDW Interface
	3.DMIC - 2

Schematic version: schematic_1433518
Platform Mapping Document : Rev0p86

BUG=b:394208231
TEST= Build Ocelot and verify it compiles without any error.

Change-Id: Ideea34defdb6f4da63374ae09e2088c3de745657
Signed-off-by: Sowmya Aralguppe <sowmya.aralguppe@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88173
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Avi Uday <aviuday@google.com>
---
 .../google/ocelot/variants/ocelot/fw_config.c | 125 ++++++++----------
 1 file changed, 52 insertions(+), 73 deletions(-)

diff --git a/src/mainboard/google/ocelot/variants/ocelot/fw_config.c b/src/mainboard/google/ocelot/variants/ocelot/fw_config.c
index 49de442e7d..0b2620716f 100644
--- a/src/mainboard/google/ocelot/variants/ocelot/fw_config.c
+++ b/src/mainboard/google/ocelot/variants/ocelot/fw_config.c
@@ -12,92 +12,77 @@
 #define GPIO_CONFIGURE_PADS(t) gpio_configure_pads(t, ARRAY_SIZE(t))
 
 static const struct pad_config hda_enable_pads[] = {
-	/* HDA_BCLK */
+	/* GPP_D10:     HDA_BCLK (HDR) */
 	PAD_CFG_NF(GPP_D10, NONE, DEEP, NF1),
-	/* HDA_SYNC */
-	PAD_CFG_NF(GPP_D11, NATIVE, DEEP, NF1),
-	/* HDA_SDO */
-	PAD_CFG_NF(GPP_D12, NATIVE, DEEP, NF1),
-	/* HDA_SDI_0 */
-	PAD_CFG_NF(GPP_D13, NATIVE, DEEP, NF1),
-
-	/* DMIC_CLK */
+	/* GPP_D11:     HDA_SYNC (HDR) */
+	PAD_CFG_NF(GPP_D11, NONE, DEEP, NF1),
+	/* GPP_D12:     HDA_SDO (HDR) */
+	PAD_CFG_NF(GPP_D12, NONE, DEEP, NF1),
+	/* GPP_D13:     HDA_SDI0 (HDR) */
+	PAD_CFG_NF(GPP_D13, NONE, DEEP, NF1),
+	/* GPP_D16:     HDA_RST_N (HDR) */
+	PAD_CFG_NF(GPP_D16, NONE, DEEP, NF1),
+	/* GPP_D17:     HDA_SDI1 (HDR) */
+	PAD_CFG_NF(GPP_D17, NONE, DEEP, NF1),
+	/* GPP_S04:     DMIC0_CLK (HDR) */
 	PAD_CFG_NF(GPP_S04, NONE, DEEP, NF5),
-	/* DMIC_DATA */
+	/* GPP_S05:     DMIC0_DATA (HDR) */
 	PAD_CFG_NF(GPP_S05, NONE, DEEP, NF5),
-};
-
-static const struct pad_config bt_i2s_enable_pads[] = {
-	/* GPP_V30 : [] ==> BT_I2S_BCLK - SSP2 */
-	PAD_CFG_NF(GPP_VGPIO30, NONE, DEEP, NF3),
-	/* GPP_V31 : [] ==> BT_I2S_SYNC - SSP2 */
-	PAD_CFG_NF(GPP_VGPIO31, NONE, DEEP, NF3),
-	/* GPP_V32 : [] ==> BT_I2S_SDO - SSP2 */
-	PAD_CFG_NF(GPP_VGPIO32, NONE, DEEP, NF3),
-	/* GPP_V33 : [] ==> BT_I2S_SDI - SSP2 */
-	PAD_CFG_NF(GPP_VGPIO33, NONE, DEEP, NF3),
-	/* GPP_V34 : [] ==> SSP_SCLK */
-	PAD_CFG_NF(GPP_VGPIO34, NONE, DEEP, NF1),
-	/* GPP_V35 : [] ==> SSP_SFRM */
-	PAD_CFG_NF(GPP_VGPIO35, NONE, DEEP, NF1),
-	/* GPP_V36 : [] ==> SSP_TXD */
-	PAD_CFG_NF(GPP_VGPIO36, NONE, DEEP, NF1),
-	/* GPP_V37 : [] ==> SSP_RXD */
-	PAD_CFG_NF(GPP_VGPIO37, NONE, DEEP, NF1),
-};
-
-static const struct pad_config bt_i2s_disable_pads[] = {
-	/* GPP_V30 : [] ==> BT_I2S_BCLK */
-	PAD_NC(GPP_VGPIO30, NONE),
-	/* GPP_V31 : [] ==> BT_I2S_SYNC */
-	PAD_NC(GPP_VGPIO31, NONE),
-	/* GPP_V32 : [] ==> BT_I2S_SDO */
-	PAD_NC(GPP_VGPIO32, NONE),
-	/* GPP_V33 : [] ==> BT_I2S_SDI */
-	PAD_NC(GPP_VGPIO33, NONE),
-	/* GPP_V34 : [] ==> SSP2_SCLK */
-	PAD_NC(GPP_VGPIO34, NONE),
-	/* GPP_V35 : [] ==> SSP2_SFRM */
-	PAD_NC(GPP_VGPIO35, NONE),
-	/* GPP_V36 : [] ==> SSP_TXD */
-	PAD_NC(GPP_VGPIO36, NONE),
-	/* GPP_V37 : [] ==> SSP_RXD */
-	PAD_NC(GPP_VGPIO37, NONE),
+	/* GPP_S06:     DMIC1_CLK (HDR) */
+	PAD_CFG_NF(GPP_S06, NONE, DEEP, NF5),
+	/* GPP_S07:     DMIC1_DATA (HDR) */
+	PAD_CFG_NF(GPP_S07, NONE, DEEP, NF5),
 };
 
 static const struct pad_config sndw_alc721_enable_pads[] = {
-	/* SNDW3_CLK   */
+	/* Soundwire GPIO Config */
+	/* GPP_S00:     SNDW3_CLK_CODEC (HDR) */
 	PAD_CFG_NF(GPP_S00, NONE, DEEP, NF1),
-	/* SNDW3_DATA0 */
+	/* GPP_S01:     SNDW3_DATA0_CODEC (HDR) */
 	PAD_CFG_NF(GPP_S01, NONE, DEEP, NF1),
-	/* SNDW3_DATA1 */
+	/* GPP_S02:     SNDW3_DATA1_CODEC (HDR) */
 	PAD_CFG_NF(GPP_S02, NONE, DEEP, NF1),
-	/* SNDW3_DATA2 */
+	/* GPP_S03:     SNDW3_DATA2_CODEC (HDR) */
 	PAD_CFG_NF(GPP_S03, NONE, DEEP, NF1),
-	/* DMIC_CLK_A0 */
+	/* GPP_S04:     DMIC0_CLK (HDR) */
 	PAD_CFG_NF(GPP_S04, NONE, DEEP, NF5),
-	/* DMIC_DATA_0 */
+	/* GPP_S05:     DMIC0_DATA (HDR) */
 	PAD_CFG_NF(GPP_S05, NONE, DEEP, NF5),
-	/* SNDW1_CLK   */
-	PAD_CFG_NF(GPP_S06, NONE, DEEP, NF3),
-	/* SNDW1_DATA  */
-	PAD_CFG_NF(GPP_S07, NONE, DEEP, NF3),
+	/* GPP_S06:     DMIC1_CLK (HDR) */
+	PAD_CFG_NF(GPP_S06, NONE, DEEP, NF5),
+	/* GPP_S07:     DMIC1_DATA (HDR) */
+	PAD_CFG_NF(GPP_S07, NONE, DEEP, NF5),
 };
 
 static const struct pad_config audio_disable_pads[] = {
-	PAD_NC(GPP_S00, NONE),
-	PAD_NC(GPP_S01, NONE),
-	PAD_NC(GPP_S02, NONE),
-	PAD_NC(GPP_S03, NONE),
-	PAD_NC(GPP_S04, NONE),
-	PAD_NC(GPP_S05, NONE),
-	PAD_NC(GPP_S06, NONE),
-	PAD_NC(GPP_S07, NONE),
-	PAD_NC(GPP_D09, NONE),
+	/* GPP_D10:     HDA_BCLK (HDR) */
 	PAD_NC(GPP_D10, NONE),
+	/* GPP_D11:     HDA_SYNC (HDR) */
 	PAD_NC(GPP_D11, NONE),
+	/* GPP_D12:     HDA_SDO (HDR) */
 	PAD_NC(GPP_D12, NONE),
+	/* GPP_D13:     HDA_SDI0 (HDR) */
 	PAD_NC(GPP_D13, NONE),
+	/* GPP_D16:     HDA_RST_N (HDR) */
+	PAD_NC(GPP_D16, NONE),
+	/* GPP_D17:     HDA_SDI1 (HDR) */
+	PAD_NC(GPP_D17, NONE),
+	/* GPP_S00:     SNDW3_CLK_CODEC (HDR) */
+	PAD_NC(GPP_S00, NONE),
+	/* GPP_S01:     SNDW3_DATA0_CODEC (HDR) */
+	PAD_NC(GPP_S01, NONE),
+	/* GPP_S02:     SNDW3_DATA1_CODEC (HDR) */
+	PAD_NC(GPP_S02, NONE),
+	/* GPP_S03:     SNDW3_DATA2_CODEC (HDR) */
+	PAD_NC(GPP_S03, NONE),
+	/* GPP_S04:     DMIC0_CLK (HDR) */
+	PAD_NC(GPP_S04, NONE),
+	/* GPP_S05:     DMIC0_DATA (HDR) */
+	PAD_NC(GPP_S05, NONE),
+	/* GPP_S06:     DMIC1_CLK (HDR) */
+	PAD_NC(GPP_S06, NONE),
+	/* GPP_S07:     DMIC1_DATA (HDR) */
+	PAD_NC(GPP_S07, NONE),
 };
 
 static const struct pad_config x1slot_pads[] = {
@@ -473,16 +458,10 @@ void fw_config_gpio_padbased_override(struct pad_config *padbased_table)
 
 	if (fw_config_probe(FW_CONFIG(AUDIO, AUDIO_NONE))) {
 		GPIO_PADBASED_OVERRIDE(padbased_table, audio_disable_pads);
-		GPIO_PADBASED_OVERRIDE(padbased_table, bt_i2s_disable_pads);
 	} else if (fw_config_probe(FW_CONFIG(AUDIO, AUDIO_ALC721_SNDW))) {
-		printk(BIOS_INFO, "Configure GPIOs for Soundwire audio.\n");
 		GPIO_PADBASED_OVERRIDE(padbased_table, sndw_alc721_enable_pads);
-		printk(BIOS_INFO, "Configure GPIOs for BT offload mode.\n");
-		GPIO_PADBASED_OVERRIDE(padbased_table, bt_i2s_enable_pads);
 	} else if (fw_config_probe(FW_CONFIG(AUDIO, AUDIO_ALC256_HDA))) {
-		printk(BIOS_INFO, "Configure GPIOs for HDA ALC 256 mode.\n");
 		GPIO_PADBASED_OVERRIDE(padbased_table, hda_enable_pads);
-		GPIO_PADBASED_OVERRIDE(padbased_table, bt_i2s_disable_pads);
 	}
 
 	if (fw_config_probe(FW_CONFIG(WIFI, WIFI_PCIE_6)) ||

From d99769bbdeda4ea2f59f5f6ef9f5b117e967f6c1 Mon Sep 17 00:00:00 2001
From: Walter Sonius <walterav1984@gmail.com>
Date: Fri, 4 Jul 2025 13:15:26 +0000
Subject: [PATCH 1509/3886] mb/hp/snb_ivb_desktops/variants: enable 4th sata
 port on tested models
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Recent development of the "pro_6300" variant fixed the 4th sata port,
using "register sata_port_map" = "0x17" in "overridetree.cb" the same
is valid for the following 2 variants:
 - compaq_8300_elite_sff
 - compaq_8200_elite_sff

BUG=581#note-22
TEST=grub2 output & dmesg output

p4
�����������������������������������������
�                                  Boot Menu                                   �
�����������������������������������������

                                                Device Path :
   Select a Boot Device                         PciRoot(0x0)/Pci(0x1F,
                                                0x2)/Sata(0x4,0xFFFF,0
   UEFI Shell                                   x0)
   USB Device
   SATA: hp DVD A DH16ABSH

dmesg | grep SATA | grep link
[    4.994271] ata1: SATA link down (SStatus 0 SControl 300)
[    5.304068] ata2: SATA link down (SStatus 0 SControl 300)
[    5.616102] ata3: SATA link down (SStatus 0 SControl 300)
[    5.920122] ata5: SATA link up 1.5 Gbps (SStatus 113 SControl 300)

Change-Id: Idcef5854e1e97380bec12374411ddfdb50395c29
Signed-off-by: Walter Sonius <walterav1984@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88304
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 .../variants/compaq_8200_elite_sff/overridetree.cb              | 2 +-
 .../variants/compaq_8300_elite_sff/overridetree.cb              | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/mainboard/hp/snb_ivb_desktops/variants/compaq_8200_elite_sff/overridetree.cb b/src/mainboard/hp/snb_ivb_desktops/variants/compaq_8200_elite_sff/overridetree.cb
index fb749ba078..e5798c772b 100644
--- a/src/mainboard/hp/snb_ivb_desktops/variants/compaq_8200_elite_sff/overridetree.cb
+++ b/src/mainboard/hp/snb_ivb_desktops/variants/compaq_8200_elite_sff/overridetree.cb
@@ -5,7 +5,7 @@ chip northbridge/intel/sandybridge
 		subsystemid 0x103c 0x1495 inherit
 
 		chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH
-			register "sata_port_map" = "0xf"
+			register "sata_port_map" = "0x17"
 			register "spi_uvscc" = "0x0"
 			register "usb_port_config" = "{
 				{ 1, 0, -1 },
diff --git a/src/mainboard/hp/snb_ivb_desktops/variants/compaq_8300_elite_sff/overridetree.cb b/src/mainboard/hp/snb_ivb_desktops/variants/compaq_8300_elite_sff/overridetree.cb
index 9a4e9eb3af..e27cb199f8 100644
--- a/src/mainboard/hp/snb_ivb_desktops/variants/compaq_8300_elite_sff/overridetree.cb
+++ b/src/mainboard/hp/snb_ivb_desktops/variants/compaq_8300_elite_sff/overridetree.cb
@@ -5,7 +5,7 @@ chip northbridge/intel/sandybridge
 		subsystemid 0x103c 0x3397 inherit
 
 		chip southbridge/intel/bd82x6x
-			register "sata_port_map" = "0xf"
+			register "sata_port_map" = "0x17"
 			register "superspeed_capable_ports" = "0x0000000f"
 			register "xhci_switchable_ports"    = "0x0000000f"
 			register "usb_port_config" = "{

From 2b7115b13991d88081b74b9aec38007ecdcaad57 Mon Sep 17 00:00:00 2001
From: Keith Hui <buurin@gmail.com>
Date: Sat, 5 Apr 2025 21:09:38 -0400
Subject: [PATCH 1510/3886] mb/hp/snb_ivb_desktops: Add gfx_uma_size options up
 to 512MB

This board is missing option values for 256MB and up.
Make complete by referencing asus/p8x7x-series and Intel IVB
datasheet vol.2, document #326765.

Intel datasheet lists an additional 1GB option for Ivy Bridge
CPUs, but since nb/intel/sandybridge/northbridge.c has been
found to not handle this setting properly when doing memory
calculations, a fix is needed there before it can be included.
It was not an option for Sandy Bridge anyway.

BUG=https://ticket.coreboot.org/issues/581

Change-Id: Id89290a673b0e5dbc72c11c097aeb70d410adeab
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87192
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
---
 src/mainboard/hp/snb_ivb_desktops/cmos.layout | 11 ++++++++++-
 1 file changed, 10 insertions(+), 1 deletion(-)

diff --git a/src/mainboard/hp/snb_ivb_desktops/cmos.layout b/src/mainboard/hp/snb_ivb_desktops/cmos.layout
index 1fc83b1a55..ac486e553c 100644
--- a/src/mainboard/hp/snb_ivb_desktops/cmos.layout
+++ b/src/mainboard/hp/snb_ivb_desktops/cmos.layout
@@ -23,7 +23,7 @@ entries
 421	1	e	9	sata_mode
 
 # coreboot config options: northbridge
-432	3	e	11	gfx_uma_size
+432	4	e	11	gfx_uma_size
 
 448	128	r	0	vbnv
 
@@ -67,6 +67,15 @@ enumerations
 11	4	160M
 11	5	192M
 11	6	224M
+11	7	256M
+11	8	288M
+11	9	320M
+11	10	352M
+11	11	384M
+11	12	416M
+11	13	448M
+11	14	480M
+11	15	512M
 
 # -----------------------------------------------------------------
 checksums

From 3b61dbaa06c0702f758da588de9dc03e2b427ca4 Mon Sep 17 00:00:00 2001
From: Keith Hui <buurin@gmail.com>
Date: Thu, 3 Jul 2025 14:46:39 -0400
Subject: [PATCH 1511/3886] mb/asus/p8z77-m_pro: Remove incorrect gfx_uma_size
 options

Values here above 512M are:
1. Inconsistent with Intel IVB datasheet vol.2, document #326765;
2. Apparently not properly supported by nb/intel/sandybridge.

Take them out until a fix can be implemented.

Change-Id: I6183f447af2816d00c9f6d78329113cd9c584191
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88293
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 .../p8x7x-series/variants/p8z77-m_pro/cmos.layout | 15 ---------------
 1 file changed, 15 deletions(-)

diff --git a/src/mainboard/asus/p8x7x-series/variants/p8z77-m_pro/cmos.layout b/src/mainboard/asus/p8x7x-series/variants/p8z77-m_pro/cmos.layout
index 3d717b444d..a256ed9ddb 100644
--- a/src/mainboard/asus/p8x7x-series/variants/p8z77-m_pro/cmos.layout
+++ b/src/mainboard/asus/p8x7x-series/variants/p8z77-m_pro/cmos.layout
@@ -113,21 +113,6 @@ enumerations
 7	13	448M
 7	14	480M
 7	15	512M
-7	16	544M
-7	17	576M
-7	18	608M
-7	19	640M
-7	20	672M
-7	21	704M
-7	22	736M
-7	23	768M
-7	24	800M
-7	25	832M
-7	26	864M
-7	27	896M
-7	28	928M
-7	29	960M
-7	30	992M
 
 # usb3_mode
 # Disable = Use the port always as USB 2.0 for compatibility

From 6c059f8af3ffd66da21a8c94a7f158e2dfc770bf Mon Sep 17 00:00:00 2001
From: Keith Hui <buurin@gmail.com>
Date: Thu, 3 Jul 2025 14:55:36 -0400
Subject: [PATCH 1512/3886] IVB mainboards: Drop 1024M option for gfx_uma_size

While reviewing CB:87192 that deals with this option on another
mainboard, it was found that northbridge/intel/sandybridge
actually could not handle this option (present on Ivy Bridge
only anyway) properly. It would only factor 544MB into memory
calculations while telling IGD it can use 1024MB.

Until a fix can be implemented there, remove this option from
Ivy Bridge mainboards.

Change-Id: I0c87c52ef050cca54e050de3d41603c4ab29740b
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88294
Reviewed-by: Kevin Keijzer <kevin@quietlife.nl>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/asrock/b75m-itx/cmos.layout                        | 1 -
 src/mainboard/asrock/b75pro3-m/cmos.layout                       | 1 -
 src/mainboard/asrock/h77pro4-m/cmos.layout                       | 1 -
 src/mainboard/asus/p8x7x-series/variants/p8c_ws/cmos.layout      | 1 -
 src/mainboard/asus/p8x7x-series/variants/p8h77-v/cmos.layout     | 1 -
 src/mainboard/asus/p8x7x-series/variants/p8z77-m/cmos.layout     | 1 -
 src/mainboard/asus/p8x7x-series/variants/p8z77-v/cmos.layout     | 1 -
 .../asus/p8x7x-series/variants/p8z77-v_le_plus/cmos.layout       | 1 -
 src/mainboard/asus/p8x7x-series/variants/p8z77-v_lx2/cmos.layout | 1 -
 src/mainboard/intel/dq67sw/cmos.layout                           | 1 -
 src/mainboard/supermicro/x9sae/cmos.layout                       | 1 -
 11 files changed, 11 deletions(-)

diff --git a/src/mainboard/asrock/b75m-itx/cmos.layout b/src/mainboard/asrock/b75m-itx/cmos.layout
index 998806ade4..350cdb8041 100644
--- a/src/mainboard/asrock/b75m-itx/cmos.layout
+++ b/src/mainboard/asrock/b75m-itx/cmos.layout
@@ -78,7 +78,6 @@ enumerations
 6	13	448M
 6	14	480M
 6	15	512M
-6	16	1024M
 
 # -----------------------------------------------------------------
 checksums
diff --git a/src/mainboard/asrock/b75pro3-m/cmos.layout b/src/mainboard/asrock/b75pro3-m/cmos.layout
index 0f9de5ed18..58e2f1f6a6 100644
--- a/src/mainboard/asrock/b75pro3-m/cmos.layout
+++ b/src/mainboard/asrock/b75pro3-m/cmos.layout
@@ -78,7 +78,6 @@ enumerations
 6	13	448M
 6	14	480M
 6	15	512M
-6	16	1024M
 
 # -----------------------------------------------------------------
 checksums
diff --git a/src/mainboard/asrock/h77pro4-m/cmos.layout b/src/mainboard/asrock/h77pro4-m/cmos.layout
index ac88ee9621..b4654dcdf8 100644
--- a/src/mainboard/asrock/h77pro4-m/cmos.layout
+++ b/src/mainboard/asrock/h77pro4-m/cmos.layout
@@ -81,7 +81,6 @@ enumerations
 6	13	448M
 6	14	480M
 6	15	512M
-6	16	1024M
 
 # cpu_fan_header (select which header provides the tachometer
 # signal to the Super I/O on its CPUFANIN input)
diff --git a/src/mainboard/asus/p8x7x-series/variants/p8c_ws/cmos.layout b/src/mainboard/asus/p8x7x-series/variants/p8c_ws/cmos.layout
index 0f9de5ed18..58e2f1f6a6 100644
--- a/src/mainboard/asus/p8x7x-series/variants/p8c_ws/cmos.layout
+++ b/src/mainboard/asus/p8x7x-series/variants/p8c_ws/cmos.layout
@@ -78,7 +78,6 @@ enumerations
 6	13	448M
 6	14	480M
 6	15	512M
-6	16	1024M
 
 # -----------------------------------------------------------------
 checksums
diff --git a/src/mainboard/asus/p8x7x-series/variants/p8h77-v/cmos.layout b/src/mainboard/asus/p8x7x-series/variants/p8h77-v/cmos.layout
index 0f9de5ed18..58e2f1f6a6 100644
--- a/src/mainboard/asus/p8x7x-series/variants/p8h77-v/cmos.layout
+++ b/src/mainboard/asus/p8x7x-series/variants/p8h77-v/cmos.layout
@@ -78,7 +78,6 @@ enumerations
 6	13	448M
 6	14	480M
 6	15	512M
-6	16	1024M
 
 # -----------------------------------------------------------------
 checksums
diff --git a/src/mainboard/asus/p8x7x-series/variants/p8z77-m/cmos.layout b/src/mainboard/asus/p8x7x-series/variants/p8z77-m/cmos.layout
index 86bd35a907..ca77a82cec 100644
--- a/src/mainboard/asus/p8x7x-series/variants/p8z77-m/cmos.layout
+++ b/src/mainboard/asus/p8x7x-series/variants/p8z77-m/cmos.layout
@@ -118,7 +118,6 @@ enumerations
 7     13    448M
 7     14    480M
 7     15    512M
-7     16    1024M
 
 # usb3_mode
 # Disable = Use the port always as USB 2.0 for compatibility
diff --git a/src/mainboard/asus/p8x7x-series/variants/p8z77-v/cmos.layout b/src/mainboard/asus/p8x7x-series/variants/p8z77-v/cmos.layout
index 0f9de5ed18..58e2f1f6a6 100644
--- a/src/mainboard/asus/p8x7x-series/variants/p8z77-v/cmos.layout
+++ b/src/mainboard/asus/p8x7x-series/variants/p8z77-v/cmos.layout
@@ -78,7 +78,6 @@ enumerations
 6	13	448M
 6	14	480M
 6	15	512M
-6	16	1024M
 
 # -----------------------------------------------------------------
 checksums
diff --git a/src/mainboard/asus/p8x7x-series/variants/p8z77-v_le_plus/cmos.layout b/src/mainboard/asus/p8x7x-series/variants/p8z77-v_le_plus/cmos.layout
index 07b2a8c0bb..86cbffd918 100644
--- a/src/mainboard/asus/p8x7x-series/variants/p8z77-v_le_plus/cmos.layout
+++ b/src/mainboard/asus/p8x7x-series/variants/p8z77-v_le_plus/cmos.layout
@@ -82,7 +82,6 @@ enumerations
 6	13	448M
 6	14	480M
 6	15	512M
-6	16	1024M
 
 # audio_panel_type
 9     0     HDA
diff --git a/src/mainboard/asus/p8x7x-series/variants/p8z77-v_lx2/cmos.layout b/src/mainboard/asus/p8x7x-series/variants/p8z77-v_lx2/cmos.layout
index 0f9de5ed18..58e2f1f6a6 100644
--- a/src/mainboard/asus/p8x7x-series/variants/p8z77-v_lx2/cmos.layout
+++ b/src/mainboard/asus/p8x7x-series/variants/p8z77-v_lx2/cmos.layout
@@ -78,7 +78,6 @@ enumerations
 6	13	448M
 6	14	480M
 6	15	512M
-6	16	1024M
 
 # -----------------------------------------------------------------
 checksums
diff --git a/src/mainboard/intel/dq67sw/cmos.layout b/src/mainboard/intel/dq67sw/cmos.layout
index d3676ae250..785a9be734 100644
--- a/src/mainboard/intel/dq67sw/cmos.layout
+++ b/src/mainboard/intel/dq67sw/cmos.layout
@@ -80,7 +80,6 @@ enumerations
 6	13	448M
 6	14	480M
 6	15	512M
-6	16	1024M
 
 # -----------------------------------------------------------------
 checksums
diff --git a/src/mainboard/supermicro/x9sae/cmos.layout b/src/mainboard/supermicro/x9sae/cmos.layout
index 0f9de5ed18..58e2f1f6a6 100644
--- a/src/mainboard/supermicro/x9sae/cmos.layout
+++ b/src/mainboard/supermicro/x9sae/cmos.layout
@@ -78,7 +78,6 @@ enumerations
 6	13	448M
 6	14	480M
 6	15	512M
-6	16	1024M
 
 # -----------------------------------------------------------------
 checksums

From dcbe591201ad92ab3a7c2e3173a4dc19b4247528 Mon Sep 17 00:00:00 2001
From: Werner Zeh <werner.zeh@siemens.com>
Date: Tue, 1 Jul 2025 08:38:32 +0200
Subject: [PATCH 1513/3886] mb/siemens/mc_rpl: Use SPD data from HWInfo instead
 of from CBFS

Siemens boards store their memory configuration data (SPD) in a field
inside the HWInfo block (which itself is located in CBFS). This patch
removes all *spd.hex-files and uses HWInfo instead for the SPD data
source. In addition, the memory data swizzling is updated to reflect
the board wiring so that DRAM can work properly.

Change-Id: I63d6e7c4543b7d99a4b1815c8ee81efcb6a87b94
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88259
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
---
 src/mainboard/siemens/mc_rpl/Kconfig          |   6 +-
 src/mainboard/siemens/mc_rpl/Makefile.mk      |   5 -
 src/mainboard/siemens/mc_rpl/memory.c         | 349 +-----------------
 src/mainboard/siemens/mc_rpl/memory_rpl.c     |  28 --
 .../siemens/mc_rpl/romstage_fsp_params.c      |  84 +----
 src/mainboard/siemens/mc_rpl/spd/Makefile.mk  |  10 -
 .../siemens/mc_rpl/spd/adlrvp_ddr5_mr.spd.hex |  32 --
 .../siemens/mc_rpl/spd/adlrvp_lp4.spd.hex     |  32 --
 .../siemens/mc_rpl/spd/adlrvp_lp5.spd.hex     |  32 --
 .../siemens/mc_rpl/spd/adlrvp_n_lp5.spd.hex   |  32 --
 .../siemens/mc_rpl/spd/empty.spd.hex          |  32 --
 11 files changed, 42 insertions(+), 600 deletions(-)
 delete mode 100644 src/mainboard/siemens/mc_rpl/memory_rpl.c
 delete mode 100644 src/mainboard/siemens/mc_rpl/spd/Makefile.mk
 delete mode 100644 src/mainboard/siemens/mc_rpl/spd/adlrvp_ddr5_mr.spd.hex
 delete mode 100644 src/mainboard/siemens/mc_rpl/spd/adlrvp_lp4.spd.hex
 delete mode 100644 src/mainboard/siemens/mc_rpl/spd/adlrvp_lp5.spd.hex
 delete mode 100644 src/mainboard/siemens/mc_rpl/spd/adlrvp_n_lp5.spd.hex
 delete mode 100644 src/mainboard/siemens/mc_rpl/spd/empty.spd.hex

diff --git a/src/mainboard/siemens/mc_rpl/Kconfig b/src/mainboard/siemens/mc_rpl/Kconfig
index 4c04775b09..c08139e619 100644
--- a/src/mainboard/siemens/mc_rpl/Kconfig
+++ b/src/mainboard/siemens/mc_rpl/Kconfig
@@ -15,10 +15,10 @@ config BOARD_SIEMENS_BASEBOARD_MC_RPL
 	select DRIVERS_USB_ACPI
 	select HAVE_ACPI_RESUME
 	select HAVE_ACPI_TABLES
-	select HAVE_SPD_IN_CBFS
 	select SOC_INTEL_COMMON_BLOCK_IPU
 	select SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES
 	select SOC_INTEL_CSE_LITE_SKU
+	select USE_SIEMENS_HWILIB
 
 
 config BOARD_SIEMENS_MC_RPL1
@@ -60,6 +60,10 @@ config UART_FOR_CONSOLE
 	int
 	default 0
 
+config DIMM_SPD_SIZE
+	int
+	default 256
+
 config DRIVER_TPM_SPI_BUS
 	default 0x2 if BOARD_SIEMENS_MC_RPL1
 
diff --git a/src/mainboard/siemens/mc_rpl/Makefile.mk b/src/mainboard/siemens/mc_rpl/Makefile.mk
index e6c0dd62d1..872ab9e94d 100644
--- a/src/mainboard/siemens/mc_rpl/Makefile.mk
+++ b/src/mainboard/siemens/mc_rpl/Makefile.mk
@@ -1,15 +1,10 @@
 ## SPDX-License-Identifier: GPL-2.0-only
 
-subdirs-y += spd
-
 bootblock-y += bootblock.c
 
 romstage-y += romstage_fsp_params.c
 romstage-y += board_id.c
 romstage-y += memory.c
-ifeq ($(CONFIG_BOARD_INTEL_ADLRVP_RPL_EXT_EC),y)
-romstage-y += memory_rpl.c
-endif
 
 ramstage-y += mainboard.c
 ramstage-y += board_id.c
diff --git a/src/mainboard/siemens/mc_rpl/memory.c b/src/mainboard/siemens/mc_rpl/memory.c
index 160059921b..40b4c971d2 100644
--- a/src/mainboard/siemens/mc_rpl/memory.c
+++ b/src/mainboard/siemens/mc_rpl/memory.c
@@ -4,124 +4,42 @@
 #include <console/console.h>
 #include <soc/romstage.h>
 
-#include "board_id.h"
-
-static const struct mb_cfg ddr4_mem_config = {
-	.type = MEM_TYPE_DDR4,
-
-	.rcomp = {
-		/* Baseboard uses only 100ohm Rcomp resistor */
-		.resistor = 100,
-
-		/* Baseboard Rcomp target values */
-		.targets = { 50, 20, 25, 25, 25 },
-	},
-
-	.ect = true, /* Early Command Training */
-
-	.UserBd = BOARD_TYPE_MOBILE,
-
-	.LpDdrDqDqsReTraining = 1,
-
-	.ddr_config = {
-		.dq_pins_interleaved = false,
-	},
-};
-
-static const struct mb_cfg lpddr4_mem_config = {
-	.type = MEM_TYPE_LP4X,
-
-	/* DQ byte map */
-	.lpx_dq_map = {
-		.ddr0 = {
-			.dq0 = {  0,  2,  3,  1,  6,  7,  5,  4, },
-			.dq1 = { 10,  8, 11,  9, 14, 12, 13, 15, },
-		},
-		.ddr1 = {
-			.dq0 = { 12,  8, 14, 10, 11, 13, 15,  9, },
-			.dq1 = {  5,  0,  7,  3,  6,  2,  1,  4, },
-		},
-		.ddr2 = {
-			.dq0 = {  3,  0,  2,  1,  6,  5,  4,  7, },
-			.dq1 = { 12, 13, 14, 15, 10,  9,  8, 11, },
-		},
-		.ddr3 = {
-			.dq0 = {  2,  6,  7,  1,  3,  4,  0,  5, },
-			.dq1 = {  9, 13,  8, 15, 14, 11, 12, 10, },
-		},
-		.ddr4 = {
-			.dq0 = {  3,  0,  1,  2,  7,  4,  6,  5, },
-			.dq1 = { 10,  8, 11,  9, 14, 13, 12, 15, },
-		},
-		.ddr5 = {
-			.dq0 = { 10, 12, 14,  8,  9, 13, 15, 11, },
-			.dq1 = {  3,  7,  6,  2,  0,  4,  5,  1, },
-		},
-		.ddr6 = {
-			.dq0 = { 12, 15, 14, 13,  9, 10, 11,  8, },
-			.dq1 = {  7,  4,  6,  5,  0,  1,  3,  2, },
-		},
-		.ddr7 = {
-			.dq0 = {  0,  2,  4,  3,  1,  6,  7,  5, },
-			.dq1 = { 13,  9, 10, 11,  8, 12, 14, 15, },
-		},
-	},
-
-	/* DQS CPU<>DRAM map */
-	.lpx_dqs_map = {
-		.ddr0 = { .dqs0 = 0, .dqs1 = 1 },
-		.ddr1 = { .dqs0 = 1, .dqs1 = 0 },
-		.ddr2 = { .dqs0 = 0, .dqs1 = 1 },
-		.ddr3 = { .dqs0 = 0, .dqs1 = 1 },
-		.ddr4 = { .dqs0 = 0, .dqs1 = 1 },
-		.ddr5 = { .dqs0 = 1, .dqs1 = 0 },
-		.ddr6 = { .dqs0 = 1, .dqs1 = 0 },
-		.ddr7 = { .dqs0 = 0, .dqs1 = 1 },
-	},
-
-	.LpDdrDqDqsReTraining = 1,
-
-	.ect = true, /* Early Command Training */
-
-	.UserBd = BOARD_TYPE_MOBILE,
-};
-
-static const struct mb_cfg lp5_mem_config = {
+static const struct mb_cfg mc_rpl1_lp5_mem_config = {
 	.type = MEM_TYPE_LP5X,
 
 	/* DQ byte map */
 	.lpx_dq_map = {
 		.ddr0 = {
-			.dq0 = {  3,  2,  1,  0,  5,  4,  6,  7, },
-			.dq1 = { 15, 14, 12, 13,  8,  9, 10, 11, },
+			.dq0 = {  0,  3,  2,  1,  4,  5,  7,  6, },
+			.dq1 = { 14, 12, 13, 15,  8, 10,  9, 11, },
 		},
 		.ddr1 = {
-			.dq0 = {  0,  2,  3,  1,  5,  7,  4,  6, },
-			.dq1 = { 14, 13, 15, 12,  8,  9, 11, 10, },
+			.dq0 = {  1,  0,  2,  3,  6,  4,  7,  5, },
+			.dq1 = { 15, 13, 12, 14,  8, 11,  10,  9, },
 		},
 		.ddr2 = {
-			.dq0 = {  1,  2,  0,  3,  4,  6,  5,  7, },
-			.dq1 = { 15, 13, 12, 14,  9, 10,  8, 11, },
+			.dq0 = {  2,  1,  3,  0,  7,  6,  4,  5, },
+			.dq1 = { 14, 12, 13, 15,  9, 10, 11,  8, },
 		},
 		.ddr3 = {
-			.dq0 = {  2,  1,  3,  0,  7,  4,  5,  6, },
-			.dq1 = { 13, 12, 15, 14,  9, 11,  8, 10, },
+			.dq0 = {  1,  2,  3,  0,  6,  4,  7,  5, },
+			.dq1 = { 13, 15, 12, 14,  8, 11, 10,  9, },
 		},
 		.ddr4 = {
-			.dq0 = {  1,  2,  3,  0,  6,  4,  5,  7, },
-			.dq1 = { 15, 13, 14, 12, 10,  9,  8, 11, },
+			.dq0 = {  2,  3,  0,  1,  5,  7,  4,  6, },
+			.dq1 = { 14, 12, 13, 15, 10,  9, 11,  8, },
 		},
 		.ddr5 = {
-			.dq0 = {  1,  0,  3,  2,  6,  7,  4,  5, },
-			.dq1 = { 14, 12, 15, 13,  8,  9, 10, 11, },
+			.dq0 = {  1,  2,  3,  0,  6,  4,  7,  5, },
+			.dq1 = { 15, 13, 12, 14, 11,  9, 10,  8, },
 		},
 		.ddr6 = {
-			.dq0 = {  0,  2,  1,  3,  4,  7,  5,  6, },
-			.dq1 = { 12, 13, 15, 14,  9, 11, 10,  8, },
+			.dq0 = {  3,  1,  2,  0,  5,  4,  7,  6, },
+			.dq1 = {  15, 13, 14, 12, 9, 10,  8, 11, },
 		},
 		.ddr7 = {
-			.dq0 = {  3,  2,  1,  0,  5,  4,  6,  7, },
-			.dq1 = { 13, 15, 11, 12, 10,  9, 14,  8, },
+			.dq0 = {  2,  3,  1,  0,  5,  4,  7,  6, },
+			.dq1 = { 14, 15, 10, 11, 13,  8,  9, 12, },
 		},
 	},
 
@@ -137,215 +55,9 @@ static const struct mb_cfg lp5_mem_config = {
 		.ddr7 = { .dqs0 = 0, .dqs1 = 1 }
 	},
 
-	.ect = true, /* Early Command Training */
-
-	.LpDdrDqDqsReTraining = 1,
-
-	.UserBd = BOARD_TYPE_MOBILE,
-
-	.lp5x_config = {
-		.ccc_config = 0xff,
-	},
-};
-
-static const struct mb_cfg ddr5_mem_config = {
-	.type = MEM_TYPE_DDR5,
-
-	.rcomp = {
-		/* Baseboard uses only 100ohm Rcomp resistor */
-		.resistor = 100,
-
-		/* Baseboard Rcomp target values */
-		.targets = { 50, 30, 30, 30, 27 },
-	},
-
-	.ect = true, /* Early Command Training */
-
-	.UserBd = BOARD_TYPE_MOBILE,
-
-	.LpDdrDqDqsReTraining = 1,
-
-	.ddr_config = {
-		.dq_pins_interleaved = false,
-	}
-};
-
-static const struct mb_cfg adlm_lp4_mem_config = {
-	.type = MEM_TYPE_LP4X,
-
-	/* DQ byte map */
-	.lpx_dq_map = {
-		.ddr0 = {
-			.dq0 = { 13, 12, 14, 8, 11, 10, 9, 15, }, /* DDR0_DQ0[7:0] */
-			.dq1 = {  3,  2,  7, 6,  0,  1, 5,  4, }, /* DDR0_DQ1[7:0] */
-		},
-		.ddr1 = {
-			.dq0 = { 11, 15, 10, 9, 12, 8, 14, 13, },  /* DDR1_DQ0[7:0] */
-			.dq1 = {  0,  1,  7, 6,  2, 5,  4,  3, },  /* DDR1_DQ1[7:0] */
-		},
-		.ddr2 = {
-			.dq0 = {  6, 7,  3,  2,  0, 4,  1,  5, }, /* DDR2_DQ0[7:0] */
-			.dq1 = { 14, 8, 13, 12, 11, 9, 10, 15, }, /* DDR2_DQ1[7:0] */
-		},
-		.ddr3 = {
-			.dq0 = { 2,  6,  7,  3,  1,  5, 0,  4, }, /* DDR3_DQ0[7:0] */
-			.dq1 = { 8, 14, 13, 12, 10, 11, 9, 15, }, /* DDR3_DQ1[7:0] */
-		},
-		.ddr4 = {
-			.dq0 = { 8, 14, 13, 12, 10, 11, 9, 15, }, /* DDR3_DQ1[7:0] */
-			.dq1 = { 1,  0,  5,  4,  6,  2, 3,  7, }, /* DDR4_DQ1[7:0] */
-		},
-		.ddr5 = {
-			.dq0 = { 8, 10, 9, 12, 14, 11, 13, 15, }, /* DDR5_DQ0[7:0] */
-			.dq1 = { 0,  7, 2,  6,  3,  1,  4,  5, }, /* DDR5_DQ1[7:0] */
-		},
-		.ddr6 = {
-			.dq0 = { 14, 12, 9, 8, 15, 10, 13, 11, }, /* DDR6_DQ0[7:0] */
-			.dq1 = {  4,  0, 5, 6,  3,  2,  1,  7, }, /* DDR6_DQ1[7:0] */
-		},
-		.ddr7 = {
-			.dq0 = { 10, 15, 12, 11, 9, 14, 13, 8, }, /* DDR7_DQ0[7:0] */
-			.dq1 = {  7,  1,  2,  3, 6,  0,  5, 4, }, /* DDR7_DQ1[7:0] */
-		},
-	},
-
-	/* DQS CPU<>DRAM map */
-	.lpx_dqs_map = {
-		.ddr0 = { .dqs0 = 1, .dqs1 = 0 },
-		.ddr1 = { .dqs0 = 1, .dqs1 = 0 },
-		.ddr2 = { .dqs0 = 0, .dqs1 = 1 },
-		.ddr3 = { .dqs0 = 0, .dqs1 = 1 },
-		.ddr4 = { .dqs0 = 1, .dqs1 = 0 },
-		.ddr5 = { .dqs0 = 1, .dqs1 = 0 },
-		.ddr6 = { .dqs0 = 1, .dqs1 = 0 },
-		.ddr7 = { .dqs0 = 1, .dqs1 = 0 }
-	},
-
-	.ect = true, /* Early Command Training */
-
-	.CmdMirror = 0xCC,
-
-	.LpDdrDqDqsReTraining = 1,
-
-	.UserBd = BOARD_TYPE_ULT_ULX_T4,
-};
-
-static const struct mb_cfg adlm_lp5_mem_config = {
-	.type = MEM_TYPE_LP5X,
-
-	/* DQ byte map */
-	.lpx_dq_map = {
-		.ddr0 = {
-			.dq0 = {  4,  5,  7,  6,  3,  2,  1,  0, },
-			.dq1 = { 12, 10,  8, 15, 11,  9, 14, 13, },
-		},
-		.ddr1 = {
-			.dq0 = {  1,  0,  2,  3,  7,  4,  5,  6, },
-			.dq1 = { 14, 15, 10, 11, 13, 12,  8,  9, },
-		},
-		.ddr2 = {
-			.dq0 = {  7,  4,  2,  0,  3,  1,  6,  5, },
-			.dq1 = { 14, 13, 15, 12,  8,  9, 10, 11, },
-		},
-		.ddr3 = {
-			.dq0 = {  3,  2,  0,  1,  7,  5,  6,  4, },
-			.dq1 = { 12, 14, 15, 13, 11,  8, 10,  9, },
-		},
-		.ddr4 = {
-			.dq0 = {  2,  3,  0,  1,  6,  4,  7,  5, },
-			.dq1 = { 14,  9, 11, 13, 12,  8, 15, 10, },
-		},
-		.ddr5 = {
-			.dq0 = {  4,  7,  3,  1,  5,  2,  6,  0, },
-			.dq1 = { 14,  8, 11,  9, 12, 15, 10, 13, },
-		},
-		.ddr6 = {
-			.dq0 = { 10, 11, 13,  9, 15, 12,  8, 14, },
-			.dq1 = {  2,  4,  7,  0,  6,  3,  5,  1, },
-		},
-		.ddr7 = {
-			.dq0 = { 13, 15, 11, 14, 10, 12,  8,  9, },
-			.dq1 = {  6,  5,  4,  7,  3,  1,  2,  0, },
-		},
-	},
-
-	/* DQS CPU<>DRAM map */
-	.lpx_dqs_map = {
-		.ddr0 = { .dqs0 = 0, .dqs1 = 1 },
-		.ddr1 = { .dqs0 = 0, .dqs1 = 1 },
-		.ddr2 = { .dqs0 = 0, .dqs1 = 1 },
-		.ddr3 = { .dqs0 = 0, .dqs1 = 1 },
-		.ddr4 = { .dqs0 = 0, .dqs1 = 1 },
-		.ddr5 = { .dqs0 = 0, .dqs1 = 1 },
-		.ddr6 = { .dqs0 = 1, .dqs1 = 0 },
-		.ddr7 = { .dqs0 = 1, .dqs1 = 0 }
-	},
-
 	.ect = false, /* Early Command Training */
 
-	.UserBd = BOARD_TYPE_ULT_ULX_T4,
-
-	.lp5x_config = {
-		.ccc_config = 0xff,
-	},
-};
-
-static const struct mb_cfg adln_lp5_mem_config = {
-	.type = MEM_TYPE_LP5X,
-
-	/* DQ byte map */
-	.lpx_dq_map = {
-		.ddr0 = {
-			.dq0 = { 12,  9, 10, 11, 14, 13,  8, 15 },
-			.dq1 = {  3,  1,  2,  0,  4,  7,  5,  6 },
-		},
-		.ddr1 = {
-			.dq0 = {  3,  1,  2,  0,  4,  7,  5,  6 },
-			.dq1 = { 13,  9,  8, 11, 10, 14, 15, 12 },
-		},
-		.ddr2 = {
-			.dq0 = {  2,  1,  3,  0,  4,  6,  5,  7 },
-			.dq1 = {  8,  9, 10, 11, 13, 14, 12, 15 },
-		},
-		.ddr3 = {
-			.dq0 = {  3,  0,  1,  2,  5,  6,  4,  7 },
-			.dq1 = { 13,  9, 11,  8, 14, 15, 10, 12 },
-		},
-		.ddr4 = {
-			.dq0 = { 12,  9, 10, 11, 14, 13,  8, 15 },
-			.dq1 = {  3,  1,  2,  0,  4,  7,  5,  6 },
-		},
-		.ddr5 = {
-			.dq0 = {  3,  1,  2,  0,  4,  7,  5,  6 },
-			.dq1 = { 13,  9,  8, 11, 10, 14, 15, 12 },
-		},
-		.ddr6 = {
-			.dq0 = {  2,  1,  3,  0,  4,  6,  5,  7 },
-			.dq1 = {  8,  9, 10, 11, 13, 14, 12, 15 },
-		},
-		.ddr7 = {
-			.dq0 = {  3,  0,  1,  2,  5,  6,  4,  7 },
-			.dq1 = { 13,  9, 11,  8, 14, 15, 10, 12 },
-		},
-	},
-
-	/* DQS CPU<>DRAM map */
-	.lpx_dqs_map = {
-		.ddr0 = { .dqs0 = 1, .dqs1 = 0 },
-		.ddr1 = { .dqs0 = 0, .dqs1 = 1 },
-		.ddr2 = { .dqs0 = 0, .dqs1 = 1 },
-		.ddr3 = { .dqs0 = 0, .dqs1 = 1 },
-		.ddr4 = { .dqs0 = 1, .dqs1 = 0 },
-		.ddr5 = { .dqs0 = 0, .dqs1 = 1 },
-		.ddr6 = { .dqs0 = 0, .dqs1 = 1 },
-		.ddr7 = { .dqs0 = 0, .dqs1 = 1 }
-	},
-
-	.ect = true, /* Early Command Training */
-
-	.UserBd = BOARD_TYPE_ULT_ULX,
-
-	.LpDdrDqDqsReTraining = 1,
+	.UserBd = BOARD_TYPE_MOBILE,
 
 	.lp5x_config = {
 		.ccc_config = 0xff,
@@ -354,28 +66,5 @@ static const struct mb_cfg adln_lp5_mem_config = {
 
 const struct mb_cfg *variant_memory_params(void)
 {
-	int board_id = get_board_id();
-
-	switch (board_id) {
-	case ADL_P_LP4_1:
-	case ADL_P_LP4_2:
-		return &lpddr4_mem_config;
-	case ADL_P_DDR4_1:
-	case ADL_P_DDR4_2:
-		return &ddr4_mem_config;
-	case ADL_P_DDR5_1:
-	case ADL_P_DDR5_2:
-		return &ddr5_mem_config;
-	case ADL_P_LP5_1:
-	case ADL_P_LP5_2:
-		return &lp5_mem_config;
-	case ADL_M_LP4:
-		return &adlm_lp4_mem_config;
-	case ADL_M_LP5:
-		return &adlm_lp5_mem_config;
-	case ADL_N_LP5:
-		return &adln_lp5_mem_config;
-	default:
-		die("unsupported board id : 0x%x\n", board_id);
-	}
+	return &mc_rpl1_lp5_mem_config;
 }
diff --git a/src/mainboard/siemens/mc_rpl/memory_rpl.c b/src/mainboard/siemens/mc_rpl/memory_rpl.c
deleted file mode 100644
index 8302a06d1f..0000000000
--- a/src/mainboard/siemens/mc_rpl/memory_rpl.c
+++ /dev/null
@@ -1,28 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <baseboard/variants.h>
-#include <soc/romstage.h>
-
-#include "board_id.h"
-
-void rpl_memory_params(FSPM_UPD *memupd)
-{
-	FSP_M_CONFIG *mem_cfg = &memupd->FspmConfig;
-
-	int board_id = get_board_id();
-
-	switch (board_id) {
-	case ADL_P_LP4_1:
-	case ADL_P_LP4_2:
-	case ADL_P_DDR4_1:
-	case ADL_P_DDR4_2:
-	case ADL_P_DDR5_1:
-	case ADL_P_DDR5_2:
-	default:
-		return;
-	case ADL_P_LP5_1:
-	case ADL_P_LP5_2:
-		mem_cfg->Lp5BankMode = 1;
-		return;
-	}
-}
diff --git a/src/mainboard/siemens/mc_rpl/romstage_fsp_params.c b/src/mainboard/siemens/mc_rpl/romstage_fsp_params.c
index 46640b6aad..962b514d2f 100644
--- a/src/mainboard/siemens/mc_rpl/romstage_fsp_params.c
+++ b/src/mainboard/siemens/mc_rpl/romstage_fsp_params.c
@@ -2,26 +2,11 @@
 
 #include <console/console.h>
 #include <fsp/api.h>
+#include <hwilib.h>
 #include <soc/romstage.h>
 #include <spd_bin.h>
 #include <soc/meminit.h>
 #include <baseboard/variants.h>
-#include "board_id.h"
-
-#define SPD_ID_MASK 0x7
-
-static size_t get_spd_index(void)
-{
-	uint8_t board_id = get_board_id();
-	size_t spd_index;
-
-	printk(BIOS_INFO, "board id is 0x%x\n", board_id);
-
-	spd_index = board_id & SPD_ID_MASK;
-
-	printk(BIOS_INFO, "SPD index is 0x%x\n", (unsigned int)spd_index);
-	return spd_index;
-}
 
 /*
  * ADL-P silicon can support 7 SRC CLK's and 10 CLKREQ signals. Out of 7 SRCCLK's
@@ -49,7 +34,22 @@ void mainboard_memory_init_params(FSPM_UPD *memupd)
 {
 	FSP_M_CONFIG *m_cfg = &memupd->FspmConfig;
 	const struct mb_cfg *mem_config = variant_memory_params();
-	int board_id = get_board_id();
+
+	static struct mem_spd spd_info;
+	static uint8_t spd_data[CONFIG_DIMM_SPD_SIZE];
+	const char *cbfs_hwi_name = "hwinfo.hex";
+
+	/* Initialize SPD information for LPDDR5 from HW-Info. */
+	memset(spd_data, 0, sizeof(spd_data));
+	if ((hwilib_find_blocks(cbfs_hwi_name) == CB_SUCCESS) &&
+	    (hwilib_get_field(SPD, spd_data, 0x80) == 0x80)) {
+		spd_info.topo = MEM_TOPO_MEMORY_DOWN;
+		spd_info.spd_data.in_mem = true;
+		spd_info.spd_data.ptr = (uintptr_t)spd_data;
+		spd_info.spd_data.len = CONFIG_DIMM_SPD_SIZE;
+	} else {
+		die("No SPD in HW-Info found!\n");
+	}
 
 	/*
 	 * Set Raptor Lake specific new upds that Alder Lake doesn't have.
@@ -57,55 +57,7 @@ void mainboard_memory_init_params(FSPM_UPD *memupd)
 	 */
 	rpl_memory_params(memupd);
 
-	/*
-	 * Alder Lake common meminit block driver considers bus width to be 128-bit and
-	 * populates the meminit data accordingly. Alder Lake-N has single memory controller
-	 * with 64-bit bus width. By setting half_populated to true, only the bottom half is
-	 * populated.
-	 * TODO: Implement __weak variant_is_half_populated(void) function.
-	 */
-	const bool half_populated = (CONFIG(BOARD_INTEL_ADLRVP_N_EXT_EC)
-			 || CONFIG(BOARD_INTEL_ADLRVP_N));
-
-	const struct mem_spd memory_down_spd_info = {
-		.topo = MEM_TOPO_MEMORY_DOWN,
-		.cbfs_index = get_spd_index(),
-	};
-
-	const struct mem_spd dimm_module_spd_info = {
-		.topo = MEM_TOPO_DIMM_MODULE,
-		.smbus = {
-			[0] = {
-				.addr_dimm[0] = 0x50,
-				.addr_dimm[1] = 0x51,
-			},
-			[1] = {
-				.addr_dimm[0] = 0x52,
-				.addr_dimm[1] = 0x53,
-			},
-		},
-	};
-
-	switch (board_id) {
-	case ADL_P_DDR4_1:
-	case ADL_P_DDR4_2:
-	case ADL_P_DDR5_1:
-		memcfg_init(memupd, mem_config, &dimm_module_spd_info, half_populated);
-		break;
-	case ADL_P_DDR5_2:
-	case ADL_P_LP4_1:
-	case ADL_P_LP4_2:
-	case ADL_P_LP5_1:
-	case ADL_P_LP5_2:
-	case ADL_M_LP4:
-	case ADL_M_LP5:
-	case ADL_N_LP5:
-		memcfg_init(memupd, mem_config, &memory_down_spd_info, half_populated);
-		break;
-	default:
-		die("Unknown board id = 0x%x\n", board_id);
-		break;
-	}
+	memcfg_init(memupd, mem_config, &spd_info, 0);
 
 	if (CONFIG(GEN3_EXTERNAL_CLOCK_BUFFER))
 		configure_external_clksrc(m_cfg);
diff --git a/src/mainboard/siemens/mc_rpl/spd/Makefile.mk b/src/mainboard/siemens/mc_rpl/spd/Makefile.mk
deleted file mode 100644
index f503b6d959..0000000000
--- a/src/mainboard/siemens/mc_rpl/spd/Makefile.mk
+++ /dev/null
@@ -1,10 +0,0 @@
-## SPDX-License-Identifier: GPL-2.0-only
-
-SPD_SOURCES =  adlrvp_lp4	# 0b000
-SPD_SOURCES += empty		# 0b001
-SPD_SOURCES += empty		# 0b002
-SPD_SOURCES += adlrvp_lp5	# 0b003
-SPD_SOURCES += empty		# 0b004
-SPD_SOURCES += empty		# 0b005
-SPD_SOURCES += adlrvp_ddr5_mr	# 0b006
-SPD_SOURCES += adlrvp_n_lp5	# 0b007
diff --git a/src/mainboard/siemens/mc_rpl/spd/adlrvp_ddr5_mr.spd.hex b/src/mainboard/siemens/mc_rpl/spd/adlrvp_ddr5_mr.spd.hex
deleted file mode 100644
index 80ef521cfa..0000000000
--- a/src/mainboard/siemens/mc_rpl/spd/adlrvp_ddr5_mr.spd.hex
+++ /dev/null
@@ -1,32 +0,0 @@
-30 08 12 03 04 00 20 62 00 00 00 00 60 00 00 00
-00 00 00 00 A1 01 E8 03 72 15 00 00 00 00 1E 41
-1E 41 1E 41 00 7D 1E BE 30 75 27 01 A0 00 82 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 47 AE
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-08 00 C2 C4 80 00 80 B3 80 11 00 00 00 00 00 00
-00 00 80 B3 80 11 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 0F 10 00 01 01 22 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 9C AD
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
diff --git a/src/mainboard/siemens/mc_rpl/spd/adlrvp_lp4.spd.hex b/src/mainboard/siemens/mc_rpl/spd/adlrvp_lp4.spd.hex
deleted file mode 100644
index e1d338edbc..0000000000
--- a/src/mainboard/siemens/mc_rpl/spd/adlrvp_lp4.spd.hex
+++ /dev/null
@@ -1,32 +0,0 @@
-23 11 11 0E 15 21 B5 08 00 40 00 00 0A 01 00 00
-48 00 04 FF 92 55 00 00 8C 00 90 A8 90 C0 08 60
-04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 7F E1 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 55 00 00 00 20 20 20 20 20 20 20
-20 20 20 20 20 20 20 20 20 20 20 20 20 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
diff --git a/src/mainboard/siemens/mc_rpl/spd/adlrvp_lp5.spd.hex b/src/mainboard/siemens/mc_rpl/spd/adlrvp_lp5.spd.hex
deleted file mode 100644
index 2f2a31a33d..0000000000
--- a/src/mainboard/siemens/mc_rpl/spd/adlrvp_lp5.spd.hex
+++ /dev/null
@@ -1,32 +0,0 @@
-23 10 13 0E 15 1A 95 08 00 40 00 00 02 01 00 00
-48 00 0A FF 92 55 05 00 AA 00 98 A8 90 90 06 C0
-03 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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-00 00 00 00 00 00 00 00 00 00 00 00 7F 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 20 00 00 00 20 20 20 20 20 20 20
-20 20 20 20 20 20 20 20 20 20 20 20 20 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
diff --git a/src/mainboard/siemens/mc_rpl/spd/adlrvp_n_lp5.spd.hex b/src/mainboard/siemens/mc_rpl/spd/adlrvp_n_lp5.spd.hex
deleted file mode 100644
index 88a1f1f473..0000000000
--- a/src/mainboard/siemens/mc_rpl/spd/adlrvp_n_lp5.spd.hex
+++ /dev/null
@@ -1,32 +0,0 @@
-23 10 13 0E 15 1A B5 08 00 40 00 00 0A 01 00 00
-48 00 0A FF 92 55 05 00 AA 00 90 A8 90 90 06 C0
-03 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 20 00 00 00 20 20 20 20 20 20 20
-20 20 20 20 20 20 20 20 20 20 20 20 20 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
diff --git a/src/mainboard/siemens/mc_rpl/spd/empty.spd.hex b/src/mainboard/siemens/mc_rpl/spd/empty.spd.hex
deleted file mode 100644
index 67b46cd239..0000000000
--- a/src/mainboard/siemens/mc_rpl/spd/empty.spd.hex
+++ /dev/null
@@ -1,32 +0,0 @@
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 80 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00

From 463cda84d245084ac39757c42749cc89c15f3fac Mon Sep 17 00:00:00 2001
From: Werner Zeh <werner.zeh@siemens.com>
Date: Tue, 1 Jul 2025 09:00:58 +0200
Subject: [PATCH 1514/3886] mb/siemens/mc_rpl: Remove unused Type-C data
 definition

This mainboard is not going to use Type-C subsystem. Therefore, disable
and remove the config data for it.

Change-Id: I2d9e53bf63b41811040f84cfe9dedf275f1059e4
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88260
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-by: Kilian Krause <kilian.krause@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/siemens/mc_rpl/Kconfig       |  1 -
 src/mainboard/siemens/mc_rpl/devicetree.cb | 10 -------
 src/mainboard/siemens/mc_rpl/dsdt.asl      |  1 -
 src/mainboard/siemens/mc_rpl/ramstage.c    | 35 ----------------------
 4 files changed, 47 deletions(-)

diff --git a/src/mainboard/siemens/mc_rpl/Kconfig b/src/mainboard/siemens/mc_rpl/Kconfig
index c08139e619..d775a470f0 100644
--- a/src/mainboard/siemens/mc_rpl/Kconfig
+++ b/src/mainboard/siemens/mc_rpl/Kconfig
@@ -16,7 +16,6 @@ config BOARD_SIEMENS_BASEBOARD_MC_RPL
 	select HAVE_ACPI_RESUME
 	select HAVE_ACPI_TABLES
 	select SOC_INTEL_COMMON_BLOCK_IPU
-	select SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES
 	select SOC_INTEL_CSE_LITE_SKU
 	select USE_SIEMENS_HWILIB
 
diff --git a/src/mainboard/siemens/mc_rpl/devicetree.cb b/src/mainboard/siemens/mc_rpl/devicetree.cb
index 9bd0d15cbd..98e2b4d31e 100644
--- a/src/mainboard/siemens/mc_rpl/devicetree.cb
+++ b/src/mainboard/siemens/mc_rpl/devicetree.cb
@@ -123,9 +123,6 @@ chip soc/intel/alderlake
 		[DDI_PORT_B] = DDI_ENABLE_HPD | DDI_ENABLE_DDC,
 	}"
 
-	# TCSS USB3
-	register "tcss_aux_ori" = "0"
-
 	register "s0ix_enable" = "true"
 	register "dptf_enable" = "true"
 
@@ -311,14 +308,7 @@ chip soc/intel/alderlake
 		end
 		device ref pcie4_0 on end
 		device ref pcie4_1 on end
-		device ref tbt_pcie_rp0 on end
-		device ref tbt_pcie_rp1 on end
-		device ref tbt_pcie_rp2 on end
-		device ref tbt_pcie_rp3 on end
 		device ref crashlog off end
-		device ref tcss_xhci on end
-		device ref tcss_dma0 on end
-		device ref tcss_dma1 on end
 		device ref xhci on
 			chip drivers/usb/acpi
 				register "desc" = ""Root Hub""
diff --git a/src/mainboard/siemens/mc_rpl/dsdt.asl b/src/mainboard/siemens/mc_rpl/dsdt.asl
index f379610866..161069c862 100644
--- a/src/mainboard/siemens/mc_rpl/dsdt.asl
+++ b/src/mainboard/siemens/mc_rpl/dsdt.asl
@@ -21,7 +21,6 @@ DefinitionBlock(
 	Device (\_SB.PCI0) {
 		#include <soc/intel/common/block/acpi/acpi/northbridge.asl>
 		#include <soc/intel/alderlake/acpi/southbridge.asl>
-		#include <soc/intel/alderlake/acpi/tcss.asl>
 	}
 
 #if CONFIG(EC_GOOGLE_CHROMEEC)
diff --git a/src/mainboard/siemens/mc_rpl/ramstage.c b/src/mainboard/siemens/mc_rpl/ramstage.c
index fd8e20332b..c1d50f0a00 100644
--- a/src/mainboard/siemens/mc_rpl/ramstage.c
+++ b/src/mainboard/siemens/mc_rpl/ramstage.c
@@ -11,7 +11,6 @@
 #include <static.h>
 #include <string.h>
 #include <drivers/intel/dptf/chip.h>
-#include "board_id.h"
 #include <intelblocks/power_limit.h>
 
 const struct cpu_power_limits limits[] = {
@@ -63,41 +62,7 @@ void variant_update_power_limits(void)
 	}
 }
 
-static const struct typec_aux_bias_pads pad_config = { GPP_E23, GPP_E22 };
-
-static const struct board_id_iom_port_config {
-	int board_id;
-	enum typec_port_index port;
-} port_config[] = {
-	{ ADL_P_LP4_1,	TYPE_C_PORT_2 },
-	{ ADL_P_LP4_2,	TYPE_C_PORT_2 },
-	{ ADL_P_DDR4_1,	TYPE_C_PORT_2 },
-	{ ADL_P_DDR4_2,	TYPE_C_PORT_2 },
-	{ ADL_P_LP5_1,	TYPE_C_PORT_2 },
-	{ ADL_P_LP5_2,	TYPE_C_PORT_2 },
-	{ ADL_M_LP4,	TYPE_C_PORT_1 },
-	{ ADL_M_LP5,	TYPE_C_PORT_0 },
-};
-
-static void variant_update_typec_init_config(void)
-{
-	/* Skip filling aux bias gpio pads for Windows SKUs */
-	if (!(CONFIG(BOARD_INTEL_ADLRVP_P_EXT_EC) || CONFIG(BOARD_INTEL_ADLRVP_RPL_EXT_EC)))
-		return;
-
-	config_t *config = config_of_soc();
-	int board_id = get_board_id();
-	for (int i = 0; i < ARRAY_SIZE(port_config); i++) {
-		if (board_id != port_config[i].board_id)
-			continue;
-
-		memcpy(&config->typec_aux_bias_pads[port_config[i].port], &pad_config,
-			sizeof(pad_config));
-	}
-}
-
 void variant_devtree_update(void)
 {
 	variant_update_power_limits();
-	variant_update_typec_init_config();
 }

From a1067ec6de5070cc14f8b336c83395d93c50bc07 Mon Sep 17 00:00:00 2001
From: Werner Zeh <werner.zeh@siemens.com>
Date: Tue, 1 Jul 2025 10:54:44 +0200
Subject: [PATCH 1515/3886] mb/siemens/mc_rpl: Remove unneeded code to select a
 VBT name in CBFS

This mainboard will just have a single VBT in cbfs which will be named
as the default name is (vbt.bin). There is no need to chose between
different configurations for the VBT selection. Therefore, remove the
corresponding code.

Change-Id: Ia72e8bae23c15476c362e456dc8358bec3b102a5
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88261
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
---
 src/mainboard/siemens/mc_rpl/mainboard.c | 22 ----------------------
 1 file changed, 22 deletions(-)

diff --git a/src/mainboard/siemens/mc_rpl/mainboard.c b/src/mainboard/siemens/mc_rpl/mainboard.c
index c02cbf9a58..a95e1efae6 100644
--- a/src/mainboard/siemens/mc_rpl/mainboard.c
+++ b/src/mainboard/siemens/mc_rpl/mainboard.c
@@ -5,7 +5,6 @@
 #include <cpu/cpu.h>
 #include <cpu/intel/cpu_ids.h>
 #include <device/device.h>
-#include <drivers/intel/gma/opregion.h>
 #include <ec/ec.h>
 #include <fw_config.h>
 #include <smbios.h>
@@ -68,24 +67,3 @@ struct chip_operations mainboard_ops = {
 	.init = mainboard_init,
 	.enable_dev = mainboard_enable,
 };
-
-const char *mainboard_vbt_filename(void)
-{
-	if (!CONFIG(CHROMEOS))
-		return "vbt.bin";
-
-	uint32_t cpu_id = cpu_get_cpuid();
-	uint8_t sku_id = get_board_id();
-	switch (sku_id) {
-	case ADL_P_LP5_1:
-	case ADL_P_LP5_2:
-		if (cpu_id == CPUID_RAPTORLAKE_J0)
-			return "vbt_adlrvp_rpl_lp5.bin";
-		return "vbt_adlrvp_lp5.bin";
-	case ADL_P_DDR5_1:
-	case ADL_P_DDR5_2:
-		return "vbt_adlrvp_ddr5.bin";
-	default:
-		return "vbt.bin";
-	}
-}

From 5de16ed1b8a12fd25b649ed6e1b8acb3ed49ebd7 Mon Sep 17 00:00:00 2001
From: Werner Zeh <werner.zeh@siemens.com>
Date: Tue, 1 Jul 2025 11:04:37 +0200
Subject: [PATCH 1516/3886] mb/siemens/mc_rpl: Remove unused embedded
 controller code

This mainboard does not have an embedded controller (EC), therefore
remove the code for it.

Change-Id: Ib37b3cc257f7ac4af6a6505a3e43c9e5275fcd3f
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88262
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-by: Kilian Krause <kilian.krause@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/siemens/mc_rpl/devicetree.cb    |  9 ---
 src/mainboard/siemens/mc_rpl/dsdt.asl         | 12 ----
 .../siemens/mc_rpl/include/baseboard/ec.h     | 72 -------------------
 .../siemens/mc_rpl/include/baseboard/gpio.h   |  8 ---
 src/mainboard/siemens/mc_rpl/mainboard.c      | 45 ------------
 src/mainboard/siemens/mc_rpl/smihandler.c     | 30 --------
 6 files changed, 176 deletions(-)
 delete mode 100644 src/mainboard/siemens/mc_rpl/include/baseboard/ec.h
 delete mode 100644 src/mainboard/siemens/mc_rpl/smihandler.c

diff --git a/src/mainboard/siemens/mc_rpl/devicetree.cb b/src/mainboard/siemens/mc_rpl/devicetree.cb
index 98e2b4d31e..fd582dfbb1 100644
--- a/src/mainboard/siemens/mc_rpl/devicetree.cb
+++ b/src/mainboard/siemens/mc_rpl/devicetree.cb
@@ -1,14 +1,5 @@
 chip soc/intel/alderlake
 
-	# This disables autonomous GPIO power management, otherwise
-	# old cr50 FW only supports short pulses.
-	register "gpio_override_pm" = "1"
-	register "gpio_pm[COMM_0]" = "0"
-	register "gpio_pm[COMM_1]" = "0"
-	register "gpio_pm[COMM_2]" = "0"
-	register "gpio_pm[COMM_4]" = "0"
-	register "gpio_pm[COMM_5]" = "0"
-
 	# GPE configuration
 	# Note that GPE events called out in ASL code rely on this
 	# route. i.e. If this route changes then the affected GPE
diff --git a/src/mainboard/siemens/mc_rpl/dsdt.asl b/src/mainboard/siemens/mc_rpl/dsdt.asl
index 161069c862..64ada0bd66 100644
--- a/src/mainboard/siemens/mc_rpl/dsdt.asl
+++ b/src/mainboard/siemens/mc_rpl/dsdt.asl
@@ -1,7 +1,6 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
 #include <acpi/acpi.h>
-#include <baseboard/ec.h>
 #include <baseboard/gpio.h>
 
 DefinitionBlock(
@@ -23,16 +22,5 @@ DefinitionBlock(
 		#include <soc/intel/alderlake/acpi/southbridge.asl>
 	}
 
-#if CONFIG(EC_GOOGLE_CHROMEEC)
-	/* ChromeOS Embedded Controller */
-	Scope (\_SB.PCI0.LPCB)
-	{
-		/* ACPI code for EC SuperIO functions */
-		#include <ec/google/chromeec/acpi/superio.asl>
-		/* ACPI code for EC functions */
-		#include <ec/google/chromeec/acpi/ec.asl>
-	}
-#endif
-
 	#include <southbridge/intel/common/acpi/sleepstates.asl>
 }
diff --git a/src/mainboard/siemens/mc_rpl/include/baseboard/ec.h b/src/mainboard/siemens/mc_rpl/include/baseboard/ec.h
deleted file mode 100644
index 6a5c72ceeb..0000000000
--- a/src/mainboard/siemens/mc_rpl/include/baseboard/ec.h
+++ /dev/null
@@ -1,72 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#ifndef __BASEBOARD_EC_H__
-#define __BASEBOARD_EC_H__
-
-#include <ec/ec.h>
-#include <ec/google/chromeec/ec_commands.h>
-#include <baseboard/gpio.h>
-
-#define MAINBOARD_EC_SCI_EVENTS \
-	(EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED)        |\
-	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN)          |\
-	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_CONNECTED)      |\
-	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_DISCONNECTED)   |\
-	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_LOW)       |\
-	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_CRITICAL)  |\
-	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY)           |\
-	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_STATUS)    |\
-	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_THRESHOLD) |\
-	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_START)    |\
-	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_STOP)     |\
-	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_PD_MCU)            |\
-	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_MODE_CHANGE)       |\
-	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_MKBP)              |\
-	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_USB_MUX))
-
-#define MAINBOARD_EC_SMI_EVENTS \
-	(EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED))
-
-/* EC can wake from S5 with lid or power button */
-#define MAINBOARD_EC_S5_WAKE_EVENTS \
-	(EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) |\
-	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_POWER_BUTTON))
-
-/*
- * EC can wake from S3 with lid or power button or key press or AC connect/disconnect or
- * mode change event.
- */
-#define MAINBOARD_EC_S3_WAKE_EVENTS \
-	(MAINBOARD_EC_S5_WAKE_EVENTS |\
-	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_CONNECTED)    |\
-	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_DISCONNECTED) |\
-	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEY_PRESSED) |\
-	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_MODE_CHANGE))
-
-#define MAINBOARD_EC_S0IX_WAKE_EVENTS	(MAINBOARD_EC_S3_WAKE_EVENTS)
-
-/* Log EC wake events plus EC shutdown events */
-#define MAINBOARD_EC_LOG_EVENTS \
-	(EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_SHUTDOWN) |\
-	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_SHUTDOWN) |\
-	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_PANIC))
-
-/*
- * ACPI related definitions for ASL code.
- */
-
-/* Enable EC backed ALS device in ACPI */
-#define EC_ENABLE_ALS_DEVICE
-
-/* Enable EC backed PD MCU device in ACPI */
-#define EC_ENABLE_PD_MCU_DEVICE
-
-/* Enable LID switch and provide wake pin for EC */
-#define EC_ENABLE_LID_SWITCH
-#define EC_ENABLE_WAKE_PIN	GPE_EC_WAKE
-
-#define SIO_EC_MEMMAP_ENABLE	/* EC Memory Map Resources */
-#define SIO_EC_HOST_ENABLE	/* EC Host Interface Resources */
-#define SIO_EC_ENABLE_PS2K      /* Enable PS/2 Keyboard */
-
-#endif /* __BASEBOARD_EC_H__ */
diff --git a/src/mainboard/siemens/mc_rpl/include/baseboard/gpio.h b/src/mainboard/siemens/mc_rpl/include/baseboard/gpio.h
index 9a1c5851c0..a27221c728 100644
--- a/src/mainboard/siemens/mc_rpl/include/baseboard/gpio.h
+++ b/src/mainboard/siemens/mc_rpl/include/baseboard/gpio.h
@@ -6,12 +6,4 @@
 #include <soc/gpe.h>
 #include <soc/gpio.h>
 
-/* eSPI virtual wire reporting */
-#define EC_SCI_GPI	GPE0_ESPI
-
-/* EC wake is LAN_WAKE# which is a special DeepSX wake pin */
-#define GPE_EC_WAKE	GPE0_LAN_WAK
-
-#define GPIO_EC_IN_RW	GPP_E7
-
 #endif /* __BASEBOARD_GPIO_H__ */
diff --git a/src/mainboard/siemens/mc_rpl/mainboard.c b/src/mainboard/siemens/mc_rpl/mainboard.c
index a95e1efae6..46741323c8 100644
--- a/src/mainboard/siemens/mc_rpl/mainboard.c
+++ b/src/mainboard/siemens/mc_rpl/mainboard.c
@@ -2,34 +2,15 @@
 
 #include <baseboard/gpio.h>
 #include <baseboard/variants.h>
-#include <cpu/cpu.h>
-#include <cpu/intel/cpu_ids.h>
 #include <device/device.h>
-#include <ec/ec.h>
-#include <fw_config.h>
-#include <smbios.h>
 #include <soc/gpio.h>
 #include <stdint.h>
 #include <stdio.h>
 
-#include "board_id.h"
-
-const char *smbios_system_sku(void)
-{
-	static char sku_str[7] = "";
-	uint8_t sku_id = get_board_id();
-
-	snprintf(sku_str, sizeof(sku_str), "sku%u", sku_id);
-	return sku_str;
-}
-
 static void mainboard_init(void *chip_info)
 {
 	variant_configure_gpio_pads();
 
-	if (CONFIG(EC_GOOGLE_CHROMEEC))
-		mainboard_ec_init();
-
 	variant_devtree_update();
 }
 
@@ -38,32 +19,6 @@ void __weak variant_devtree_update(void)
 	/* Override dev tree settings per board */
 }
 
-#if CONFIG(BOARD_INTEL_ADLRVP_N_EXT_EC)
-static void add_fw_config_oem_string(const struct fw_config *config, void *arg)
-{
-	struct smbios_type11 *t;
-	char buffer[64];
-
-	t = (struct smbios_type11 *)arg;
-
-	snprintf(buffer, sizeof(buffer), "%s-%s", config->field_name, config->option_name);
-	t->count = smbios_add_string(t->eos, buffer);
-}
-
-static void mainboard_smbios_strings(struct device *dev, struct smbios_type11 *t)
-{
-	fw_config_for_each_found(add_fw_config_oem_string, t);
-}
-#endif
-
-static void mainboard_enable(struct device *dev)
-{
-#if CONFIG(BOARD_INTEL_ADLRVP_N_EXT_EC)
-	dev->ops->get_smbios_strings = mainboard_smbios_strings;
-#endif
-}
-
 struct chip_operations mainboard_ops = {
 	.init = mainboard_init,
-	.enable_dev = mainboard_enable,
 };
diff --git a/src/mainboard/siemens/mc_rpl/smihandler.c b/src/mainboard/siemens/mc_rpl/smihandler.c
deleted file mode 100644
index a3b43231ec..0000000000
--- a/src/mainboard/siemens/mc_rpl/smihandler.c
+++ /dev/null
@@ -1,30 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-or-later */
-
-#include <cpu/x86/smm.h>
-#include <ec/google/chromeec/smm.h>
-#include <intelblocks/smihandler.h>
-#include <baseboard/ec.h>
-
-void mainboard_smi_espi_handler(void)
-{
-	if (!CONFIG(EC_GOOGLE_CHROMEEC))
-		return;
-
-	chromeec_smi_process_events();
-}
-
-void mainboard_smi_sleep(u8 slp_typ)
-{
-	if (!CONFIG(EC_GOOGLE_CHROMEEC))
-		return;
-
-	chromeec_smi_sleep(slp_typ, MAINBOARD_EC_S3_WAKE_EVENTS, MAINBOARD_EC_S5_WAKE_EVENTS);
-}
-
-int mainboard_smi_apmc(u8 apmc)
-{
-	if (CONFIG(EC_GOOGLE_CHROMEEC))
-		chromeec_smi_apmc(apmc, MAINBOARD_EC_SCI_EVENTS, MAINBOARD_EC_SMI_EVENTS);
-
-	return 0;
-}

From b3d7c40fb50222ac2c5d4b349d3fd76fbfd54dd2 Mon Sep 17 00:00:00 2001
From: Werner Zeh <werner.zeh@siemens.com>
Date: Tue, 1 Jul 2025 12:02:57 +0200
Subject: [PATCH 1517/3886] mb/siemens/mc_rpl: Remove code for board_id

This board does not use the board_id-feature hence the code can be
removed.

Change-Id: I18c67580d4611b4c53248315937277bed53bd1ea
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88263
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
---
 src/mainboard/siemens/mc_rpl/Makefile.mk |  2 --
 src/mainboard/siemens/mc_rpl/board_id.c  | 11 -----------
 src/mainboard/siemens/mc_rpl/board_id.h  | 12 ------------
 3 files changed, 25 deletions(-)
 delete mode 100644 src/mainboard/siemens/mc_rpl/board_id.c
 delete mode 100644 src/mainboard/siemens/mc_rpl/board_id.h

diff --git a/src/mainboard/siemens/mc_rpl/Makefile.mk b/src/mainboard/siemens/mc_rpl/Makefile.mk
index 872ab9e94d..b52fe96f2e 100644
--- a/src/mainboard/siemens/mc_rpl/Makefile.mk
+++ b/src/mainboard/siemens/mc_rpl/Makefile.mk
@@ -3,11 +3,9 @@
 bootblock-y += bootblock.c
 
 romstage-y += romstage_fsp_params.c
-romstage-y += board_id.c
 romstage-y += memory.c
 
 ramstage-y += mainboard.c
-ramstage-y += board_id.c
 ramstage-y += ramstage.c
 
 CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/include
diff --git a/src/mainboard/siemens/mc_rpl/board_id.c b/src/mainboard/siemens/mc_rpl/board_id.c
deleted file mode 100644
index ba154243a9..0000000000
--- a/src/mainboard/siemens/mc_rpl/board_id.c
+++ /dev/null
@@ -1,11 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <boardid.h>
-#include <types.h>
-#include "board_id.h"
-
-/* Get Board ID */
-int get_board_id(void)
-{
-	return 1;
-}
diff --git a/src/mainboard/siemens/mc_rpl/board_id.h b/src/mainboard/siemens/mc_rpl/board_id.h
deleted file mode 100644
index 1408573b1b..0000000000
--- a/src/mainboard/siemens/mc_rpl/board_id.h
+++ /dev/null
@@ -1,12 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#ifndef _MAINBOARD_COMMON_BOARD_ID_H_
-#define _MAINBOARD_COMMON_BOARD_ID_H_
-
-/*
- * Returns board information (board id[15:8] and
- * Fab info[7:0]) on success and < 0 on error
- */
-int get_board_id(void);
-
-#endif /* _MAINBOARD_COMMON_BOARD_ID_H_ */

From 03c331399c317760e499f728328bd58eeccf3cb2 Mon Sep 17 00:00:00 2001
From: David Wu <david_wu@quanta.corp-partner.google.com>
Date: Thu, 3 Jul 2025 16:20:41 +0800
Subject: [PATCH 1518/3886] mb/google/nissa/var/craask: Add focaltech
 touchscreen support

This change adds the necessary configuration for the focaltech
touchscreen (FTSC1000) device, connected to I2C bus 38.

It includes settings for:
* HID descriptor
* Device description
* IRQ configuration
* Detection
* Reset and enable GPIOs with their respective delays
* Power resource handling
* HID descriptor register offset

Datasheet: FT8112_Data_Sheet_V0.2_HKC20240415.pdf

BUG=b:429335394
TEST=emerge-nissa coreboot and focaltech touchscreen can work well.

Change-Id: Ic1c4bea599db23d5bc760bb7a54a2581cb293ce3
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88284
Reviewed-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 .../google/brya/variants/craask/overridetree.cb | 17 +++++++++++++++++
 1 file changed, 17 insertions(+)

diff --git a/src/mainboard/google/brya/variants/craask/overridetree.cb b/src/mainboard/google/brya/variants/craask/overridetree.cb
index 576d9f1f4d..f95d0ae2c2 100644
--- a/src/mainboard/google/brya/variants/craask/overridetree.cb
+++ b/src/mainboard/google/brya/variants/craask/overridetree.cb
@@ -38,6 +38,7 @@ fw_config
 		option TS_UNPROVISIONED 	0
 		option TS_GTCH7503		1
 		option TS_ILTK0001		2
+		option TS_FTSC1000		3
 	end
 end
 
@@ -412,6 +413,22 @@ chip soc/intel/alderlake
 					probe TS_SOURCE TS_ILTK0001
 				end
 			end
+			chip drivers/i2c/hid
+				register "generic.hid" = ""FTSC1000""
+				register "generic.desc" = ""Focal Touchscreen""
+				register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_C7_IRQ)"
+				register "generic.detect" = "1"
+				register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C1)"
+				register "generic.reset_delay_ms" = "20"
+				register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C0)"
+				register "generic.enable_delay_ms" = "6"
+				register "generic.has_power_resource" = "1"
+				register "generic.use_gpio_for_status" = "true"
+				register "hid_desc_reg_offset" = "0x01"
+				device i2c 38 on
+					probe TS_SOURCE TS_FTSC1000
+				end
+			end
 		end
 		device ref i2c2 on
 			chip drivers/intel/mipi_camera

From 4367daae204ed04f4d1e759dd94a23fefd6e8752 Mon Sep 17 00:00:00 2001
From: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Date: Mon, 7 Jul 2025 09:53:30 +0800
Subject: [PATCH 1519/3886] drivers/spi: Add option to generate proper
 PowerResource _STA

The _STA method of drivers/spi PowerResource currently always
returns true. To allow generating _STA that returns the device's actual
power state, this CL adds a new boolean option `use_gpio_for_status` to
the `drivers_spi_acpi_config` struct, and propagates the value to
`acpi_power_res_params` to reuse the feature implemented for acpi/device
in [1].

[1] https://review.coreboot.org/c/coreboot/+/55027

BUG=b:428793056
TEST=Dump SSDT on kinmen with use_gpio_for_status=true

    Scope (\_SB.PCI0.SPI0)
    {
        Device (CRFP)
        {
        ...
        ...
            PowerResource (PR00, 0x00, 0x0000)
            {
                Method (_STA, 0, Serialized)  // _STA: Status
                {
                    0x5D = \_SB.PCI0.GTXS /* External reference */
                    Local0
                    If (!Local0)
                    {
                        Return (Zero)
                    }

                    0x27 = \_SB.PCI0.GTXS /* External reference */
                    Local0
                    Local0 ^= One
                    If (Local0)
                    {
                        Return (Zero)
                    }

                    Return (One)
                }

                Method (_ON, 0, Serialized)  // _ON_: Power On
                {
                    Local0 = _STA ()
                    If ((Local0 == One))
                    {
                        Return (Zero)
                    }

                    \_SB.PCI0.CTXS (0x27)
                    \_SB.PCI0.STXS (0x5D)
                    Sleep (0x03)
                    \_SB.PCI0.STXS (0x27)
                }

                Method (_OFF, 0, Serialized)  // _OFF: Power Off
                {
                    \_SB.PCI0.CTXS (0x27)
                    \_SB.PCI0.CTXS (0x5D)
                }
            }
        }
    }

Change-Id: I9591957f2db66081ffe447f91afd6655835d8feb
Signed-off-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88337
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
---
 src/drivers/spi/acpi/acpi.c | 3 ++-
 src/drivers/spi/acpi/chip.h | 6 ++++++
 2 files changed, 8 insertions(+), 1 deletion(-)

diff --git a/src/drivers/spi/acpi/acpi.c b/src/drivers/spi/acpi/acpi.c
index bd3f89a857..be049173b6 100644
--- a/src/drivers/spi/acpi/acpi.c
+++ b/src/drivers/spi/acpi/acpi.c
@@ -166,7 +166,8 @@ static void spi_acpi_fill_ssdt_generator(const struct device *dev)
 			config->enable_off_delay_ms,
 			&config->stop_gpio,
 			config->stop_delay_ms,
-			config->stop_off_delay_ms
+			config->stop_off_delay_ms,
+			config->use_gpio_for_status
 		};
 		acpi_device_add_power_res(&power_res_params);
 	}
diff --git a/src/drivers/spi/acpi/chip.h b/src/drivers/spi/acpi/chip.h
index b7b39f7c3a..54c5cadd52 100644
--- a/src/drivers/spi/acpi/chip.h
+++ b/src/drivers/spi/acpi/chip.h
@@ -47,6 +47,12 @@ struct drivers_spi_acpi_config {
 	/* Generic properties for exporting device-specific data to the OS */
 	struct acpi_dp property_list[MAX_GENERIC_PROPERTY_LIST];
 	unsigned int property_count;
+
+	/* Write a _STA method that uses the state of the GPIOs to determine if
+	 * the PowerResource is ON or OFF. If this is false, the _STA method
+	 * will always return ON.
+	 */
+	bool use_gpio_for_status;
 };
 
 #endif /* __SPI_ACPI_CHIP_H__ */

From d866e72b3a17be70efbb7778a977550a7a857a12 Mon Sep 17 00:00:00 2001
From: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Date: Mon, 7 Jul 2025 09:55:45 +0800
Subject: [PATCH 1520/3886] mb/google/fatcat/var/kinmen: Set CRFP to use GPIO
 for status

Set the CRFP device to use GPIO for the power status. This causes an
ACPI `_STA()` function to be generated that returns the power status of
the CRFP device, rather than always returning `0x1`. This `_STA()`
function can be used during boot to skip enabling the device (and
performing the associated sleep) if the device is already powered on.

BUG=b:428793056
TEST=Boot the board and make sure the FPMCU was booted once
     (e.g. examine FPMCU console logs)
TEST=Dump SSDT on kinmen

    Scope (\_SB.PCI0.SPI0)
    {
        Device (CRFP)
        {
        ...
        ...
            PowerResource (PR00, 0x00, 0x0000)
            {
                Method (_STA, 0, Serialized)  // _STA: Status
                {
                    0x5D = \_SB.PCI0.GTXS /* External reference */
                    Local0
                    If (!Local0)
                    {
                        Return (Zero)
                    }

                    0x27 = \_SB.PCI0.GTXS /* External reference */
                    Local0
                    Local0 ^= One
                    If (Local0)
                    {
                        Return (Zero)
                    }

                    Return (One)
                }

                Method (_ON, 0, Serialized)  // _ON_: Power On
                {
                    Local0 = _STA ()
                    If ((Local0 == One))
                    {
                        Return (Zero)
                    }

                    \_SB.PCI0.CTXS (0x27)
                    \_SB.PCI0.STXS (0x5D)
                    Sleep (0x03)
                    \_SB.PCI0.STXS (0x27)
                }

                Method (_OFF, 0, Serialized)  // _OFF: Power Off
                {
                    \_SB.PCI0.CTXS (0x27)
                    \_SB.PCI0.CTXS (0x5D)
                }
            }
        }
    }

Change-Id: Ia3054c61dfab185d124b3aae8df9e80aa6afc71a
Signed-off-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88338
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/google/fatcat/variants/kinmen/overridetree.cb | 1 +
 1 file changed, 1 insertion(+)

diff --git a/src/mainboard/google/fatcat/variants/kinmen/overridetree.cb b/src/mainboard/google/fatcat/variants/kinmen/overridetree.cb
index 1944d148a5..ac48600b97 100644
--- a/src/mainboard/google/fatcat/variants/kinmen/overridetree.cb
+++ b/src/mainboard/google/fatcat/variants/kinmen/overridetree.cb
@@ -269,6 +269,7 @@ chip soc/intel/pantherlake
 				register "irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_E22_IRQ)"
 				register "wake" = "GPE0_DW2_22"
 				register "has_power_resource" = "true"
+				register "use_gpio_for_status" = "true"
 				register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C15)"
 				register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E19)"
 				register "enable_delay_ms" = "3"

From 12199811776efb1ce9db100c1a7f4652491ca634 Mon Sep 17 00:00:00 2001
From: Martin Roth <gaumless@gmail.com>
Date: Sun, 6 Jul 2025 11:46:22 -0600
Subject: [PATCH 1521/3886] drivers/emu/qemu: Add a comment about fw_cfg
 assumptions

This documents that if the fw_cfg table was improperly configured by
QEMU, the fw_cfg_smbios_init() function would leak memory. We could
add a check to verify that this doesn't happen, but honestly that seems
like overkill. This just documents the issue in case this code is
copied for use elsewhere.

BUG=CIDs 1405799, 1405791, 1405792, 1405796, 1405797
Signed-off-by: Martin Roth <gaumless@gmail.com>

Change-Id: I4f253194dae52897633ab5d96bb8c2964b8365d0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88332
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
---
 src/drivers/emulation/qemu/fw_cfg.c | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/src/drivers/emulation/qemu/fw_cfg.c b/src/drivers/emulation/qemu/fw_cfg.c
index 3725419e7b..98f2a7b94d 100644
--- a/src/drivers/emulation/qemu/fw_cfg.c
+++ b/src/drivers/emulation/qemu/fw_cfg.c
@@ -351,6 +351,12 @@ static const char *type1_serial_number;
 static const char *type1_family;
 static u8 type1_uuid[16];
 
+/*
+ * We're making an assumption that the table we get from fw_cfg_get() &
+ * fw_cfg_read() only has one entry for each of the above fields. If
+ * there's more than one, we would leak the memory created by strdup()
+ * for the previous iterations through the loop.
+ */
 static void fw_cfg_smbios_init(void)
 {
 	static int done = 0;

From 05396238dad21be4154c216d58b83fcec4264d05 Mon Sep 17 00:00:00 2001
From: Martin Roth <gaumless@gmail.com>
Date: Sun, 6 Jul 2025 11:56:03 -0600
Subject: [PATCH 1522/3886] libpayload/drivers: Fix mem-leak in cbmem_console
 error condition

When returning from cbmem_console_snapshot() because of a corrupted
console structure, the memory that was just allocated was not being
freed as it "should be".

BUG=CID 1419477

Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I85370fb49c9ef9a00cd2ea516fa80c9e152c9b48
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88334
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
---
 payloads/libpayload/drivers/cbmem_console.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/payloads/libpayload/drivers/cbmem_console.c b/payloads/libpayload/drivers/cbmem_console.c
index c243d5e88d..65fd52da59 100644
--- a/payloads/libpayload/drivers/cbmem_console.c
+++ b/payloads/libpayload/drivers/cbmem_console.c
@@ -126,6 +126,7 @@ char *cbmem_console_snapshot(void)
 	if (overflow) {
 		if (cursor >= size) {
 			printf("ERROR: CBMEM console struct is corrupted\n");
+			free(console_c);
 			return NULL;
 		}
 		for (oldc = cursor; oldc < size; oldc++)

From c68645cd88a2c72c14b71ad1a590b9e1edf13a6e Mon Sep 17 00:00:00 2001
From: Martin Roth <gaumless@gmail.com>
Date: Sun, 6 Jul 2025 12:01:55 -0600
Subject: [PATCH 1523/3886] util/supermicro: Fix mem leak in get_line_as_int
 error conditions

When parsing the string, if it doesn't end with 0 or \n, get_line_as_int
returns -1, but wasn't freeing the buffer. Also if we got an empty
string with just null termination, that byte would also cause a leak, so
move the second free() to the bottom. It's always fine to free a null
pointer if the allocation failed.

BUG=CID 1419489

Change-Id: Ibb3a7544ec8c46820b6e47b6fd4bbe5cabafe1a8
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88335
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 util/supermicro/smcbiosinfo/smcbiosinfo.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/util/supermicro/smcbiosinfo/smcbiosinfo.c b/util/supermicro/smcbiosinfo/smcbiosinfo.c
index 6a27ba7a77..c55cb46013 100644
--- a/util/supermicro/smcbiosinfo/smcbiosinfo.c
+++ b/util/supermicro/smcbiosinfo/smcbiosinfo.c
@@ -101,15 +101,16 @@ static int get_line_as_int(char *fn, char *match, int bcd)
 		ret = strtol(s, &endptr, 0);
 		if (*endptr != '\0' && *endptr != '\n') {
 			fprintf(stderr, "E: Couldn't parse number for key '%s'\n", match);
+			free(s);
 			return -1;
 		}
 		if (bcd)
 			ret = bcd2int(ret);
-		free(s);
 	} else {
 		fprintf(stderr, "E: Got invalid line for key '%s'\n", match);
 	}
 
+	free(s);
 	return ret;
 }
 

From 24ea6937f254d09b06e5ffd0813af2181b6e6910 Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Sat, 23 Jul 2022 10:46:38 +0100
Subject: [PATCH 1524/3886] soc/intel/apollolake: Add the Kconfig options for
 IFWI Boot Profile

The Boot Profile for use with the IFWI Boot Flow. The selected profile
should be equal to or higher than the one configured in IFWI.

No Profile
  Since its inception, coreboot has ignored the Boot Flow designed by
  Intel; this only uses an IBB and OBB. Neither are measured or verified
  and mapped without assistance.

Legacy
  Profile 0 is for platforms that do not wish to enable Boot Guard boot
  block verification or measurement enforcement.

Verified
  Profile 1 is strict Verification enforcement. It prevents unverified
  BIOS components from running.

Verified and Measured
  Boot Guard Profile 2 is strict Verification and Measurement
  enforcement; this prevents unverified BIOS components from running.
  Upon manufacturing completion, this value is burned into an FPF
  and is permanent. This setting is only configurable when OEM signing
  is enabled.

Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I83d2fd134e1a893766f625fe2e2ddd81d48f9f8a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66103
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/soc/intel/apollolake/Kconfig | 88 +++++++++++++++++++++++++++++++-
 1 file changed, 87 insertions(+), 1 deletion(-)

diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig
index 4b770da889..47a90830e1 100644
--- a/src/soc/intel/apollolake/Kconfig
+++ b/src/soc/intel/apollolake/Kconfig
@@ -109,7 +109,7 @@ config USE_LEGACY_8254_TIMER
 
 config SKIP_CSE_RBP
 	bool
-	default y if BOOT_DEVICE_MEMORY_MAPPED
+	default y if BOOT_DEVICE_MEMORY_MAPPED && !IFWI_IBBM_LOAD
 	help
 	  Tell CSE we do not need to use Ring Buffer Protocol (RBP) to fetch
 	  firmware for us if we are using memory-mapped SPI. This lets CSE
@@ -399,4 +399,90 @@ config HAVE_PAM0_REGISTER
 config DOMAIN_RESOURCE_32BIT_LIMIT
 	default PCR_BASE_ADDRESS
 
+choice
+	prompt "Boot Profile"
+	default NO_BOOT_PROFILE
+	help
+	  The Boot Profile that is used for the IFWI Boot Flow. This should
+	  be equal to, or higher than the one configured in IFWI.
+
+config NO_BOOT_PROFILE
+	bool "No Profile"
+	help
+	  Since its inception, coreboot has ignored the Boot Flow designed
+	  by Intel; this only uses an IBB and OBB. Neither are measured or
+	  verified and mapped without assistance.
+
+config BOOT_PROFILE_0
+	bool "Legacy"
+	help
+	  Profile 0 is for platforms that do not wish to enable Boot Guard
+	  boot block verification or measurement enforcement.
+
+config BOOT_PROFILE_1
+	bool "Verified"
+	depends on !VBOOT
+	help
+	  Profile 1 is strict Verification enforcement. It prevents unverified
+	  BIOS components from running.
+
+config BOOT_PROFILE_2
+	bool "Verified and Measured"
+	depends on !VBOOT
+	help
+	  Boot Guard Profile 2 is strict Verification and Measurement enforcement;
+	  this prevents unverified BIOS components from running. Upon manufacturing
+	  completion, this value is burned into an FPF and is permanent. This
+	  setting is only configurable when OEM signing is enabled.
+
+endchoice
+
+config IFWI_IBBM_LOAD
+	bool
+	default y if BOOT_PROFILE_0 || BOOT_PROFILE_1 || BOOT_PROFILE_2
+	help
+	  Create IBBL, IBBM and OBB that are required for Apollo Lake's secure boot flow. The IBBM
+	  will be loaded and measured with the assistance of the CSEs Ring Buffer Protocol.
+
+config IBBM_ROM_SIZE
+	hex
+	default 0x16000
+	depends on IFWI_IBBM_LOAD
+	help
+	  The size of the IBBM ($(objcbfs/ibbm.rom). This is the size of the
+	  ELF, with the ELF header removed, rounded down to the nearest 0x100.
+
+config IBBM_ROM_COMPONENT
+	string
+	depends on IFWI_IBBM_LOAD
+	default "verstage.elf" if VBOOT
+	default "romstage.elf"
+	help
+	  The component to use as the IBB. This must be the component that runs
+	  straight after the bootblock.
+
+config IBBM_ROM_ADDR
+	hex
+	depends on IFWI_IBBM_LOAD
+	default VERSTAGE_ADDR if VBOOT
+	default ROMSTAGE_ADDR
+	help
+	  The base address (in CAR) where the IBBM should be copied to.
+
+config IFWI_VERIFIED_BOOT
+	bool
+	default y if BOOT_PROFILE_1 || BOOT_PROFILE_2
+	depends on TPM && IFWI_IBBM_LOAD
+	help
+	  Verify the individual states of coreboot against SHA256 hashes that are created
+	  at build time.
+
+config IFWI_MEASURED_BOOT
+	bool
+	default y if BOOT_PROFILE_2
+	depends on TPM && IFWI_IBBM_LOAD
+	help
+	  Measuring the IBBL, IBB and TXE using either PTT or a TPM. The IBB is measured
+	  only after it has been loaded into the CSE.
+
 endif

From 584fdd6572a128f0711109a8a5b0abef29a16df4 Mon Sep 17 00:00:00 2001
From: Yidi Lin <yidilin@google.com>
Date: Wed, 9 Jul 2025 05:21:46 +0800
Subject: [PATCH 1525/3886] soc/mediatek/mt8196: Remove redundant bootblock.c
 from Makefile.mk

Change-Id: I7974dbde907e1697073080c0260c5968c40d9ed2
Signed-off-by: Yidi Lin <yidilin@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88359
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/soc/mediatek/mt8196/Makefile.mk | 1 -
 1 file changed, 1 deletion(-)

diff --git a/src/soc/mediatek/mt8196/Makefile.mk b/src/soc/mediatek/mt8196/Makefile.mk
index c69f67c2b7..729f73f638 100644
--- a/src/soc/mediatek/mt8196/Makefile.mk
+++ b/src/soc/mediatek/mt8196/Makefile.mk
@@ -12,7 +12,6 @@ all-y += timer.c timer_prepare.c
 all-y += ../common/uart.c
 
 bootblock-y += booker.c
-bootblock-y += bootblock.c
 bootblock-y += ../common/bootblock.c bootblock.c
 bootblock-y += cksys.c
 bootblock-y += ../common/early_init.c

From f6de6f8933105ed25a26db0688125d38822cb63c Mon Sep 17 00:00:00 2001
From: Subrata Banik <subratabanik@google.com>
Date: Tue, 8 Jul 2025 04:15:39 +0000
Subject: [PATCH 1526/3886] mb/google/fatcat: Drop redundant SNDW GPIO mapping

This patch removes redundant SNDW GPIO mapping that was already present
in fw_config.c and applied as per FW_CONFIG.

BUG=b:427091370
TEST=Boot beep verification is possible using google/fatcat.

Change-Id: Ibeca991b9e855792df48073d2138b9c7ec130c41
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88350
Reviewed-by: Pranava Y N <pranavayn@google.com>
Reviewed-by: Jayvik Desai <jayvik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 .../google/fatcat/variants/fatcat/gpio.c        | 17 -----------------
 1 file changed, 17 deletions(-)

diff --git a/src/mainboard/google/fatcat/variants/fatcat/gpio.c b/src/mainboard/google/fatcat/variants/fatcat/gpio.c
index 6f551f2f18..b31ba05437 100644
--- a/src/mainboard/google/fatcat/variants/fatcat/gpio.c
+++ b/src/mainboard/google/fatcat/variants/fatcat/gpio.c
@@ -324,23 +324,6 @@ static const struct pad_config gpio_table[] = {
 	/* GPP_H22:     I2C1_SCL_I3C1_SCL_CAM_FLSH_CVS */
 	PAD_CFG_NF(GPP_H22, NONE, DEEP, NF1),
 
-	/* GPP_S00:     SNDW3_CLK_CODEC */
-	PAD_CFG_NF(GPP_S00, NONE, DEEP, NF1),
-	/* GPP_S01:     SNDW3_DATA0_CODEC */
-	PAD_CFG_NF(GPP_S01, NONE, DEEP, NF1),
-	/* GPP_S02:     SNDW3_DATA1_CODEC */
-	PAD_CFG_NF(GPP_S02, NONE, DEEP, NF1),
-	/* GPP_S03:     SNDW3_DATA2_CODEC */
-	PAD_CFG_NF(GPP_S03, NONE, DEEP, NF1),
-	/* GPP_S04:     SNDW2_CLK */
-	PAD_CFG_NF(GPP_S04, NONE, DEEP, NF2),
-	/* GPP_S05:     SNDW2_DATA0 */
-	PAD_CFG_NF(GPP_S05, NONE, DEEP, NF2),
-	/* GPP_S06:     SNDW1_CLK */
-	PAD_CFG_NF(GPP_S06, NONE, DEEP, NF3),
-	/* GPP_S07:     SNDW1_DATA0 */
-	PAD_CFG_NF(GPP_S07, NONE, DEEP, NF3),
-
 	/* GPP_V00:     PM_BATLOW_N */
 	PAD_CFG_NF(GPP_V00, NONE, DEEP, NF1),
 	/* GPP_V01:     BC_ACOK_MCP */

From afaf4c3d7b3c07bc155f30363acbd37e36d0cd89 Mon Sep 17 00:00:00 2001
From: Kyle Lin <kylelinck@google.com>
Date: Thu, 29 May 2025 15:55:10 +0800
Subject: [PATCH 1527/3886] mb/google/brya/variants/pujjolo: Update ISH GPIOs
 and add ISH firmware name

GPIO config for ISH:
 - GPP_B3 -> IMU_INT_L
 - GPP_B4 -> ACC_INT_L
 - GPP_B5 -> ISH_I2C0_SCL
 - GPP_B6 -> ISH_I2C0_SDA
 - GPP_D1 -> SEN_MODE2_EC_ISH_INT_ODL

ISH FW Name: pujjolo_ish.bin

TEST='ectool --name=cros_ish motionsense' command should print the
following messages:
Motion sensing active
Sensor 0: 420   704     8068
Sensor 1: 452   -16844  908
Sensor 2: 0     0       0

Change-Id: I6798c47c84d6948a861ac641d4e4b6830ba53b23
Signed-off-by: Kyle Lin <kylelinck@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87897
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Derek Huang <derekhuang@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 .../google/brya/variants/pujjolo/gpio.c          | 16 ++++++++--------
 .../google/brya/variants/pujjolo/overridetree.cb |  1 +
 2 files changed, 9 insertions(+), 8 deletions(-)

diff --git a/src/mainboard/google/brya/variants/pujjolo/gpio.c b/src/mainboard/google/brya/variants/pujjolo/gpio.c
index ac14f0d22f..802dad18f9 100644
--- a/src/mainboard/google/brya/variants/pujjolo/gpio.c
+++ b/src/mainboard/google/brya/variants/pujjolo/gpio.c
@@ -56,14 +56,14 @@ static const struct pad_config override_gpio_table[] = {
 	PAD_CFG_NF(GPP_B1, NONE, DEEP, NF1),
 	/* B2  : NC */
 	PAD_NC(GPP_B2, NONE),
-	/* B3  : CPU_GP2 ==> GYRO_SENSOR_INT */
-	PAD_CFG_GPI_APIC(GPP_B3, NONE, PWROK, LEVEL, INVERT),
-	/* B4  : PROC_GP3 ==> ACC_SENSOR_INT */
-	PAD_CFG_GPI_APIC(GPP_B4, NONE, PWROK, LEVEL, INVERT),
-	/* B5  : GPP_B5 ==> ISH_I2C0_SENSOR_SCL */
-	PAD_CFG_NF(GPP_B5, NONE, DEEP, NF1),
-	/* B6  : GPP_B6 ==> ISH_I2C0_SENSOR_SDA */
-	PAD_CFG_NF(GPP_B6, NONE, DEEP, NF1),
+	/* B3  : ISH_IMU_INT_L */
+	PAD_CFG_NF(GPP_B3, NONE, DEEP, NF4),
+	/* B4  : ISH_ACC_INT_L */
+	PAD_CFG_NF(GPP_B4, NONE, DEEP, NF4),
+	/* B5  : EC_I2C_SENSOR_SDA_SOC */
+	PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_B5, NONE, DEEP, NF1),
+	/* B6  : EC_I2C_SENSOR_SCL_SOC */
+	PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_B6, NONE, DEEP, NF1),
 	/* B7  : GPP_B7 ==> NC */
 	PAD_CFG_NF(GPP_B7, NONE, DEEP, NF2),
 	/* B8  : WWAN_SAR_DETECT_2_ODL */
diff --git a/src/mainboard/google/brya/variants/pujjolo/overridetree.cb b/src/mainboard/google/brya/variants/pujjolo/overridetree.cb
index de40681426..9347f7912e 100644
--- a/src/mainboard/google/brya/variants/pujjolo/overridetree.cb
+++ b/src/mainboard/google/brya/variants/pujjolo/overridetree.cb
@@ -448,6 +448,7 @@ chip soc/intel/alderlake
 		device ref ish on
 			chip drivers/intel/ish
 				register "add_acpi_dma_property" = "true"
+				register "firmware_name" = ""pujjolo_ish.bin""
 				device generic 0 on end
 			end
 		end

From 410b3c697f928c8cd25fef415b18cc3b93828916 Mon Sep 17 00:00:00 2001
From: Sowmya Aralguppe <sowmya.aralguppe@intel.com>
Date: Sun, 6 Jul 2025 18:08:26 +0530
Subject: [PATCH 1528/3886] mb/google/ocelot/var/ocelot: Add FW_CONIG for ISH

This patch provides option to enable/disable ISH.Removed the
copies and redundant ISH pins from GPIO.c

Schematic version: schematic_1433518
Platform Mapping Document : Rev0p86

BUG=b:394208231
TEST= Build Ocelot and verify it compiles without any error.

Change-Id: I02bfa6b90b1c37a1d69d094804b4153e191a29af
Signed-off-by: Sowmya Aralguppe <sowmya.aralguppe@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88329
Reviewed-by: Avi Uday <aviuday@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 .../google/ocelot/variants/ocelot/fw_config.c | 47 ++++++++++++++-----
 .../google/ocelot/variants/ocelot/gpio.c      | 32 ++++---------
 2 files changed, 44 insertions(+), 35 deletions(-)

diff --git a/src/mainboard/google/ocelot/variants/ocelot/fw_config.c b/src/mainboard/google/ocelot/variants/ocelot/fw_config.c
index 0b2620716f..fdbbe7a003 100644
--- a/src/mainboard/google/ocelot/variants/ocelot/fw_config.c
+++ b/src/mainboard/google/ocelot/variants/ocelot/fw_config.c
@@ -346,20 +346,44 @@ static const struct pad_config thc1_enable_wake[] = {
 };
 
 static const struct pad_config ish_disable_pads[] = {
-	/* GPP_D06:     NC */
+	/* GPP_B05:     C_EC_ISH_ALRT */
+	PAD_NC(GPP_B05, NONE),
+	/* GPP_B07:     SLATEMODE_HALLOUT_SNSR_R */
+	PAD_NC(GPP_B07, NONE),
+	/* GPP_B18:     ISH_I2C2_SDA_SNSR_HDR */
+	PAD_NC(GPP_B18, NONE),
+	/* GPP_B19:     ISH_I2C2_SCL_SNSR_HDR */
+	PAD_NC(GPP_B19, NONE),
+	/* GPP_B22:     ISH_GP_5_SNSR_HDR */
+	PAD_NC(GPP_B22, NONE),
+	/* GPP_B23:     ISH_GP_6_SNSR_HDR */
+	PAD_NC(GPP_B23, NONE),
+	/* GPP_D05:     ISH_UART0_ECAIC_RXD */
+	PAD_NC(GPP_D05, NONE),
+	/* GPP_D06:     ISH_UART0_ECAIC_TXD */
 	PAD_NC(GPP_D06, NONE),
-	/* GPP_E05:     NC */
-	PAD_NC(GPP_E05, NONE),
-	/* GPP_F23:     NC */
+	/* GPP_F23:     SMC_LID / ISH_GP9A*/
 	PAD_NC(GPP_F23, NONE),
 };
 
 static const struct pad_config ish_enable_pads[] = {
-	/* GPP_D06:     ISH_UART0_TXD */
+	/* GPP_B05:     C_EC_ISH_ALRT */
+	PAD_CFG_NF(GPP_B05, NONE, DEEP, NF4),
+	/* GPP_B07:     SLATEMODE_HALLOUT_SNSR_R */
+	PAD_CFG_NF(GPP_B07, NONE, DEEP, NF4),
+	/* GPP_B18:     ISH_I2C2_SDA_SNSR_HDR */
+	PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_B18, NONE, DEEP, NF1),
+	/* GPP_B19:     ISH_I2C2_SCL_SNSR_HDR */
+	PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_B19, NONE, DEEP, NF1),
+	/* GPP_B22:     ISH_GP_5_SNSR_HDR */
+	PAD_CFG_NF(GPP_B22, NONE, DEEP, NF4),
+	/* GPP_B23:     ISH_GP_6_SNSR_HDR */
+	PAD_CFG_NF(GPP_B23, NONE, DEEP, NF4),
+	/* GPP_D05:     ISH_UART0_ECAIC_RXD */
+	PAD_CFG_NF(GPP_D05, NONE, DEEP, NF2),
+	/* GPP_D06:     ISH_UART0_ECAIC_TXD */
 	PAD_CFG_NF(GPP_D06, NONE, DEEP, NF2),
-	/* GPP_E05:     ISH_GP_7_SNSR_HDR */
-	PAD_CFG_NF(GPP_E05, NONE, DEEP, NF4),
-	/* GPP_F23:     ISH_GP_9A */
+	/* GPP_F23:     SMC_LID / ISH_GP9A*/
 	PAD_CFG_NF(GPP_F23, NONE, DEEP, NF8),
 };
 
@@ -506,10 +530,11 @@ void fw_config_gpio_padbased_override(struct pad_config *padbased_table)
 		GPIO_PADBASED_OVERRIDE(padbased_table, touchscreen_disable_pads);
 	}
 
-	if (fw_config_probe(FW_CONFIG(ISH, ISH_DISABLE)))
-		GPIO_PADBASED_OVERRIDE(padbased_table, ish_disable_pads);
-	else
+	if (fw_config_probe(FW_CONFIG(ISH, ISH_ENABLE))) {
 		GPIO_PADBASED_OVERRIDE(padbased_table, ish_enable_pads);
+	} else {
+		GPIO_PADBASED_OVERRIDE(padbased_table, ish_disable_pads);
+	}
 
 	/* NOTE: disable PEG (x8 slot) and x4 slot wake for now */
 	GPIO_PADBASED_OVERRIDE(padbased_table, peg_x4slot_wake_disable_pads);
diff --git a/src/mainboard/google/ocelot/variants/ocelot/gpio.c b/src/mainboard/google/ocelot/variants/ocelot/gpio.c
index 6b11af063e..dcef9f7579 100644
--- a/src/mainboard/google/ocelot/variants/ocelot/gpio.c
+++ b/src/mainboard/google/ocelot/variants/ocelot/gpio.c
@@ -50,17 +50,15 @@ static const struct pad_config gpio_table[] = {
 	/* GPP_B01:     USBC_SML_DATA_PD */
 	PAD_CFG_NF(GPP_B01, NONE, DEEP, NF1),
 	/* GPP_B02:     ISH_I2C0_SDA_SNSR_HDR */
-	PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_B02, NONE, DEEP, NF3),
+	PAD_NC(GPP_B02, NONE),
 	/* GPP_B03:     ISH_I2C0_SCL_SNSR_HDR */
-	PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_B03, NONE, DEEP, NF3),
+	PAD_NC(GPP_B03, NONE),
 	/* GPP_B04:     ISH_GP_0_SNSR_HDR */
-	PAD_CFG_NF(GPP_B04, NONE, DEEP, NF4),
+	PAD_NC(GPP_B04, NONE),
 	/* GPP_B06:     SOC_PDB_CTRL */
 	PAD_CFG_GPO(GPP_B06, 0, DEEP),
-	/* GPP_B07:     SLATEMODE_HALLOUT_SNSR_R */
-	PAD_CFG_NF(GPP_B07, NONE, DEEP, NF4),
 	/* GPP_B08:     ISH_GP_4_SNSR_HDR */
-	PAD_CFG_NF(GPP_B08, NONE, DEEP, NF4),
+	PAD_NC(GPP_B08, NONE),
 	/* GPP_B09:     BT_RF_KILL_N */
 	PAD_CFG_GPO(GPP_B09, 1, DEEP),
 	/* GPP_B10:     NC */
@@ -75,18 +73,10 @@ static const struct pad_config gpio_table[] = {
 	PAD_CFG_GPI(GPP_B16, NONE, DEEP),
 	/* GPP_B17:     SPI_TPM_INT_N */
 	PAD_CFG_GPI_APIC_LOCK(GPP_B17, NONE, LEVEL, INVERT, LOCK_CONFIG),
-	/* GPP_B18:     ISH_I2C2_SDA_SNSR_HDR */
-	PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_B18, NONE, DEEP, NF1),
-	/* GPP_B19:     ISH_I2C2_SCL_SNSR_HDR */
-	PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_B19, NONE, DEEP, NF1),
 	/* GPP_B20:     WWAN_RST_N */
 	PAD_CFG_GPO(GPP_B20, 1, PLTRST),
 	/* GPP_B21:     TCP_RETIMER_FORCE_PWR */
 	PAD_CFG_GPO(GPP_B21, 0, DEEP),
-	/* GPP_B22:     ISH_GP_5_SNSR_HDR */
-	PAD_CFG_NF(GPP_B22, NONE, DEEP, NF4),
-	/* GPP_B23:     ISH_GP_6_SNSR_HDR */
-	PAD_CFG_NF(GPP_B23, NONE, DEEP, NF4),
 	/* GPP_B24:     ESPI_ALERT0_EC_R_N */
 	PAD_NC(GPP_B24, NONE),
 	/* GPP_B25:     None */
@@ -145,14 +135,10 @@ static const struct pad_config gpio_table[] = {
 	PAD_CFG_GPO(GPP_D02, 0, DEEP),
 	/* GPP_D03:     X4_SLOT_WAKE_N */
 	PAD_CFG_GPI_SCI_LOW(GPP_D03, NONE, DEEP, LEVEL),
-	/* GPP_D05:     ISH_UART0_ECAIC_RXD */
-	PAD_CFG_NF(GPP_D05, NONE, DEEP, NF2),
-	/* GPP_D06:     ISH_UART0_ECAIC_TXD */
-	PAD_CFG_NF(GPP_D06, NONE, DEEP, NF2),
 	/* GPP_D07:     ISH_UART0_RTS_N_SNSR_HDR */
-	PAD_CFG_NF(GPP_D07, NONE, DEEP, NF3),
+	PAD_NC(GPP_D07, NONE),
 	/* GPP_D08:     ISH_UART0_CTS_N_SNSR_HDR */
-	PAD_CFG_NF(GPP_D08, NONE, DEEP, NF3),
+	PAD_NC(GPP_D08, NONE),
 	/* GPP_D09:     I2S_MCLK_HDR */
 	PAD_CFG_NF(GPP_D09, NONE, DEEP, NF1),
 	/* GPP_D10:     HDA_BCLK (HDR) */
@@ -261,8 +247,6 @@ static const struct pad_config gpio_table[] = {
 	PAD_CFG_GPI(GPP_F20, NONE, DEEP),
 	/* GPP_F22:     THC1_SPI2_DSYNC */
 	PAD_CFG_NF(GPP_F22, NONE, DEEP, NF3),
-	/* GPP_F23:     SMC_LID */
-	PAD_CFG_GPI_SCI_LOW(GPP_F23, NONE, DEEP, LEVEL),
 
 	/* GPP_H */
 	/* GPP_H00:     NC */
@@ -292,9 +276,9 @@ static const struct pad_config gpio_table[] = {
 	/* GPP_H13:     CPU_C10_GATE_N_R */
 	PAD_CFG_NF(GPP_H13, NONE, DEEP, NF1),
 	/* GPP_H14:     ISH_I3C1_SDA_SNSR_HDR */
-	PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_H14, NONE, DEEP, NF4),
+	PAD_NC(GPP_H14, NONE),
 	/* GPP_H15:     ISH_I3C1_SCL_SNSR_HDR */
-	PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_H15, NONE, DEEP, NF4),
+	PAD_NC(GPP_H15, NONE),
 	/* GPP_H17:     MIC MUTE LED */
 	PAD_CFG_NF(GPP_H17, NONE, DEEP, NF1),
 	/* GPP_H18:     GEN4_SSD_PWREN */

From bb95a26cda317f9fffea5eed680525244734a067 Mon Sep 17 00:00:00 2001
From: Sowmya Aralguppe <sowmya.aralguppe@intel.com>
Date: Sun, 6 Jul 2025 18:49:26 +0530
Subject: [PATCH 1529/3886] mb/google/ocelot/var/ocelot: Add FW_CONFIG for WiFi

This patch provides option to enable WiFi through
1) PCIe Interface - Enable PCIe and Disable CNVi
2) CNVi - Enable CNVi Module and Disable PCIe

Schematic version: schematic_1433518
Platform Mapping Document : Rev0p86

BUG=b:394208231
TEST= Build Ocelot and verify it compiles without any error.

Change-Id: I82360f87b3afc83b6494e59060d3213806aefc8a
Signed-off-by: Sowmya Aralguppe <sowmya.aralguppe@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88330
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Pranava Y N <pranavayn@google.com>
---
 .../google/ocelot/variants/ocelot/fw_config.c | 19 +++++++++----------
 1 file changed, 9 insertions(+), 10 deletions(-)

diff --git a/src/mainboard/google/ocelot/variants/ocelot/fw_config.c b/src/mainboard/google/ocelot/variants/ocelot/fw_config.c
index fdbbe7a003..082fa3a5c3 100644
--- a/src/mainboard/google/ocelot/variants/ocelot/fw_config.c
+++ b/src/mainboard/google/ocelot/variants/ocelot/fw_config.c
@@ -187,7 +187,11 @@ static const struct pad_config pcie_wlan_disable_pads[] = {
 };
 
 static const struct pad_config cnvi_enable_pads[] = {
-	/* NOTE: IOSSTAGE: 'Ignore' for S0ix */
+	/* GPP_B09:     BT_RF_KILL_N */
+	PAD_CFG_GPO(GPP_B09, 1, DEEP),
+	/* GPP_C10:     WIFI_RF_KILL_N */
+	PAD_CFG_GPO(GPP_C10, 1, DEEP),
+	/* GPP_F00:     M.2_CNV_BRI_DT_BT_UART2_RTS_N */
 	PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_F00, NONE, DEEP, NF1),
 	/* GPP_F01:     M.2_CNV_BRI_RSP_BT_UART2_RXD */
 	/* NOTE: IOSSTAGE: 'Ignore' for S0ix */
@@ -204,13 +208,13 @@ static const struct pad_config cnvi_enable_pads[] = {
 	/* GPP_F05:     CRF_CLKREQ_R */
 	/* NOTE: IOSSTAGE: 'Ignore' for S0ix */
 	PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_F05, NONE, DEEP, NF3),
-	/* GPP_A16:     BT_RF_KILL_N */
-	PAD_CFG_GPO(GPP_A16, 1, DEEP),
-	/* GPP_A17:     WIFI_RF_KILL_N */
-	PAD_CFG_GPO(GPP_A17, 1, DEEP),
 };
 
 static const struct pad_config cnvi_disable_pads[] = {
+	/* GPP_B09:     BT_RF_KILL_N */
+	PAD_NC(GPP_B09, NONE),
+	/* GPP_C10:     WIFI_RF_KILL_N */
+	PAD_NC(GPP_C10, NONE),
 	/* GPP_F00:     M.2_CNV_BRI_DT_BT_UART2_RTS_N */
 	PAD_NC(GPP_F00, NONE),
 	/* GPP_F01:     M.2_CNV_BRI_RSP_BT_UART2_RXD */
@@ -223,11 +227,6 @@ static const struct pad_config cnvi_disable_pads[] = {
 	PAD_NC(GPP_F04, NONE),
 	/* GPP_F05:     CRF_CLKREQ_R */
 	PAD_NC(GPP_F05, NONE),
-
-	/* GPP_A16:     BT_RF_KILL_N */
-	PAD_NC(GPP_A16, NONE),
-	/* GPP_A17:     WIFI_RF_KILL_N */
-	PAD_NC(GPP_A17, NONE),
 };
 
 static const struct pad_config touchscreen_disable_pads[] = {

From 3f61df24d5e4bb3ce4384f723d1299e3b149ae88 Mon Sep 17 00:00:00 2001
From: Sowmya Aralguppe <sowmya.aralguppe@intel.com>
Date: Sun, 6 Jul 2025 19:52:34 +0530
Subject: [PATCH 1530/3886] mb/google/ocelot/var/ocelot: Add FW_CONFIG for
 Storage

Add FW_CONFIG probe based on Ocelot for Storage devices:
    1.SD
    2.UFS
    3.NVMe

Schematic version: schematic_1433518
Platform Mapping Document : Rev0p86

BUG=b:394208231
TEST= Build Ocelot and verify it compiles without any error.

Change-Id: I4aff3e3815d5fd09daa550d1a353bd828b7f382c
Signed-off-by: Sowmya Aralguppe <sowmya.aralguppe@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88331
Reviewed-by: Pranava Y N <pranavayn@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 .../google/ocelot/variants/ocelot/fw_config.c | 44 ++++++++-----------
 1 file changed, 19 insertions(+), 25 deletions(-)

diff --git a/src/mainboard/google/ocelot/variants/ocelot/fw_config.c b/src/mainboard/google/ocelot/variants/ocelot/fw_config.c
index 082fa3a5c3..6735e6f73e 100644
--- a/src/mainboard/google/ocelot/variants/ocelot/fw_config.c
+++ b/src/mainboard/google/ocelot/variants/ocelot/fw_config.c
@@ -85,18 +85,22 @@ static const struct pad_config audio_disable_pads[] = {
 	PAD_NC(GPP_S07, NONE),
 };
 
-static const struct pad_config x1slot_pads[] = {
-	/* GPP_A08:     X1_PCIE_SLOT_PWR_EN */
-	PAD_CFG_GPO(GPP_A08, 1, PLTRST),
-	/* GPP_D19:     X1_DT_PCIE_RST_N */
-	PAD_CFG_GPO(GPP_D19, 1, PLTRST),
+static const struct pad_config x4slot_pads[] = {
+	/* GPP_F10:     X4_PCIE_SLOT1_PWR_EN */
+	PAD_CFG_GPO(GPP_F10, 1, PLTRST),
+	/* GPP_E03:     X4_DT_PCIE_RST_N */
+	PAD_CFG_GPO(GPP_E03, 1, PLTRST),
+	/* GPP_D03:     X4_SLOT_WAKE_N */
+	PAD_CFG_GPI_SCI_LOW(GPP_D03, NONE, DEEP, LEVEL),
 };
 
-static const struct pad_config x1slot_disable_pads[] = {
-	/* GPP_A08:     X1_PCIE_SLOT_PWR_EN */
-	PAD_CFG_GPO(GPP_A08, 0, PLTRST),
-	/* GPP_D19:     X1_DT_PCIE_RST_N */
-	PAD_NC(GPP_D19, NONE),
+static const struct pad_config x4slot_disable_pads[] = {
+	/* GPP_F10:     X4_PCIE_SLOT1_PWR_EN */
+	PAD_CFG_GPO(GPP_F10, 0, PLTRST),
+	/* GPP_E03:     X4_DT_PCIE_RST_N */
+	PAD_NC(GPP_E03, NONE),
+	/* GPP_D03:     X4_SLOT_WAKE_N */
+	PAD_NC(GPP_D03, NONE),
 };
 
 /*
@@ -149,14 +153,14 @@ static const struct pad_config wwan_disable_pads[] = {
 
 /* Gen4 NVME: at the top M.2 slot */
 static const struct pad_config pre_mem_gen4_ssd_pwr_pads[] = {
-	/* GPP_H18:     EN_PP3300_SSD */
+	/* GPP_H18:     GEN4_SSD_PWREN */
 	PAD_CFG_GPO(GPP_H18, 0, PLTRST),
 };
 
 static const struct pad_config gen4_ssd_pads[] = {
-	/* GPP_B10:     EN_PP3300_SSD */
+	/* GPP_H18:     GEN4_SSD_PWREN */
 	PAD_CFG_GPO(GPP_H18, 1, PLTRST),
-	/* GPP_B09:     SSD_PERST_L */
+	/* GPP_A08:     M2_GEN4_SSD_RESET_N */
 	PAD_CFG_GPO(GPP_A08, 1, PLTRST),
 };
 
@@ -165,13 +169,6 @@ static const struct pad_config ufs_enable_pads[] = {
 	PAD_CFG_NF(GPP_D21, NONE, DEEP, NF1),
 };
 
-static const struct pad_config peg_x4slot_wake_disable_pads[] = {
-	/* GPP_D24:     PEG_SLOT_WAKE_N */
-	PAD_NC(GPP_D24, NONE),
-	/* GPP_D25:     X4_SLOT_WAKE_N */
-	PAD_NC(GPP_D25, NONE),
-};
-
 static const struct pad_config pcie_wlan_enable_pads[] = {
 	/* GPP_A11:     WLAN_RST_N */
 	PAD_CFG_GPO(GPP_A11, 1, PLTRST),
@@ -505,9 +502,9 @@ void fw_config_gpio_padbased_override(struct pad_config *padbased_table)
 	}
 
 	if (fw_config_probe(FW_CONFIG(SD, SD_NONE)))
-		GPIO_PADBASED_OVERRIDE(padbased_table, x1slot_disable_pads);
+		GPIO_PADBASED_OVERRIDE(padbased_table, x4slot_disable_pads);
 	else
-		GPIO_PADBASED_OVERRIDE(padbased_table, x1slot_pads);
+		GPIO_PADBASED_OVERRIDE(padbased_table, x4slot_pads);
 
 	if (fw_config_probe(FW_CONFIG(TOUCHPAD, TOUCHPAD_LPSS_I2C))) {
 		GPIO_PADBASED_OVERRIDE(padbased_table, touchpad_lpss_i2c_enable_pads);
@@ -535,9 +532,6 @@ void fw_config_gpio_padbased_override(struct pad_config *padbased_table)
 		GPIO_PADBASED_OVERRIDE(padbased_table, ish_disable_pads);
 	}
 
-	/* NOTE: disable PEG (x8 slot) and x4 slot wake for now */
-	GPIO_PADBASED_OVERRIDE(padbased_table, peg_x4slot_wake_disable_pads);
-
 	if (fw_config_probe(FW_CONFIG(FP, FP_PRESENT))) {
 		GPIO_PADBASED_OVERRIDE(padbased_table, fp_enable_pads);
 	} else {

From 6ab37f0e0e20a513838090050ff3f8d816cd96f6 Mon Sep 17 00:00:00 2001
From: Sowmya Aralguppe <sowmya.aralguppe@intel.com>
Date: Sun, 6 Jul 2025 23:44:21 +0530
Subject: [PATCH 1531/3886] mb/google/ocelot/var/ocelot: Add FW_CONFIG for
 Finger Print

This patch adds FW_CONFIG probe for Finger Print(FP).

Schematic version: schematic_1433518
Platform Mapping Document : Rev0p86

BUG=b:394208231
TEST= Build Ocelot and verify it compiles without any error.

Change-Id: Ie817774d962898e2770206db52fc00ad241fb580
Signed-off-by: Sowmya Aralguppe <sowmya.aralguppe@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88336
Reviewed-by: Pranava Y N <pranavayn@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 .../google/ocelot/variants/ocelot/fw_config.c | 38 ++++++++++---------
 1 file changed, 20 insertions(+), 18 deletions(-)

diff --git a/src/mainboard/google/ocelot/variants/ocelot/fw_config.c b/src/mainboard/google/ocelot/variants/ocelot/fw_config.c
index 6735e6f73e..1e7756769c 100644
--- a/src/mainboard/google/ocelot/variants/ocelot/fw_config.c
+++ b/src/mainboard/google/ocelot/variants/ocelot/fw_config.c
@@ -384,38 +384,40 @@ static const struct pad_config ish_enable_pads[] = {
 };
 
 static const struct pad_config fp_disable_pads[] = {
+	/* GPP_E05:     GPP_E05_FPS_PWREN */
+	PAD_NC(GPP_E05, NONE),
+	/* GPP_C15:     FPS_RST_N */
 	PAD_NC(GPP_C15, NONE),
-	/* GPP_D01:     MOD_TCSS1_TYP_A_VBUS_EN */
-	PAD_CFG_GPO(GPP_D01, 1, DEEP),
-	PAD_NC(GPP_E17, NONE),
-	/* FIXME: b/390031369
-	 * use dedicated GPIO PIN for codec enable
-	 * when FPS is enabled.
-	 */
-	/* GPP_E19:     CODEC_EN */
-	PAD_CFG_GPO(GPP_E19, 1, PLTRST),
+	/* GPP_E19:     FPS_INT_N */
+	PAD_NC(GPP_E19, NONE),
+	/* GPP_E20:     FPS_FW_UPDATE */
 	PAD_NC(GPP_E20, NONE),
+	/* GPP_E17:     GPP_E17_GSPI0A_CS0 */
+	PAD_NC(GPP_E17, NONE),
+	/* GPP_F14:     GPP_F14_GPSI0A_MOSI */
 	PAD_NC(GPP_F14, NONE),
+	/* GPP_F15:     GPP_F15_GSPI0A_MISO */
 	PAD_NC(GPP_F15, NONE),
+	/* GPP_F16:     GPP_F16_GSPI0A_CLK */
 	PAD_NC(GPP_F16, NONE),
 };
 
 static const struct pad_config fp_enable_pads[] = {
+	/* GPP_E05:     GPP_E5_FPS_PWREN */
+	PAD_CFG_GPO(GPP_E05, 1, DEEP),
 	/* GPP_C15:     FPS_RST_N */
 	PAD_CFG_GPO_LOCK(GPP_C15, 1, LOCK_CONFIG),
-	/* GPP_D01:     FPS_SOC_INT_L */
-	PAD_CFG_GPI_IRQ_WAKE(GPP_D01, NONE, PWROK, LEVEL, INVERT),
-	/* GPP_E17:     GSPI0A_CS0 */
+	/* GPP_E17:     GPP_E17_GSPI0A_CS0 */
 	PAD_CFG_NF(GPP_E17, NONE, DEEP, NF5),
-	/* GPP_E19:     FPMCU_PWREN */
-	PAD_CFG_GPO(GPP_E19, 1, DEEP),
-	/* GPP_E20:     FPMCU_FW_UPDATE */
+	/* GPP_E19:     FPS_INT_N */
+	PAD_CFG_GPI_IRQ_WAKE(GPP_E19, NONE, PWROK, LEVEL, INVERT),
+	/* GPP_E20:     FPS_FW_UPDATE */
 	PAD_CFG_GPO_LOCK(GPP_E20, 0, LOCK_CONFIG),
-	/* GPP_F14:     GPSI0A_MOSI */
+	/* GPP_F14:     GPP_F14_GPSI0A_MOSI */
 	PAD_CFG_NF(GPP_F14, NONE, DEEP, NF8),
-	/* GPP_F15:     GSPI0A_MISO */
+	/* GPP_F15:     GPP_F15_GSPI0A_MISO */
 	PAD_CFG_NF(GPP_F15, NONE, DEEP, NF8),
-	/* GPP_F16:     GPSI0A_CLK */
+	/* GPP_F16:     GPP_F16_GSPI0A_CLK */
 	PAD_CFG_NF(GPP_F16, NONE, DEEP, NF8),
 };
 

From 0ef670a66a28212e29e543bc86d714f0ef8851ee Mon Sep 17 00:00:00 2001
From: Sowmya Aralguppe <sowmya.aralguppe@intel.com>
Date: Tue, 8 Jul 2025 10:47:41 +0530
Subject: [PATCH 1532/3886] mb/google/ocelot/var/ocelot: Configure FPS related
 changes

This patch configures Interrupt, Enable and Reset pins for FPS.

BUG=b:394208231
TEST=Build Ocelot and verify it compiles without any error.

Change-Id: Ida4fab8da007403898e6843d5161249a5093fd54
Signed-off-by: Sowmya Aralguppe <sowmya.aralguppe@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88351
Reviewed-by: Pranava Y N <pranavayn@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/google/ocelot/variants/ocelot/overridetree.cb | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/src/mainboard/google/ocelot/variants/ocelot/overridetree.cb b/src/mainboard/google/ocelot/variants/ocelot/overridetree.cb
index 31959f5a27..56aa468b6e 100644
--- a/src/mainboard/google/ocelot/variants/ocelot/overridetree.cb
+++ b/src/mainboard/google/ocelot/variants/ocelot/overridetree.cb
@@ -558,11 +558,11 @@ chip soc/intel/pantherlake
 				register "hid" = "ACPI_DT_NAMESPACE_HID"
 				register "uid" = "1"
 				register "compat_string" = ""google,cros-ec-spi""
-				register "irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_D01_IRQ)"
-				register "wake" = "GPE0_DW1_01"
+				register "irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_E19_IRQ)"
+				register "wake" = "GPE0_DW1_19"
 				register "has_power_resource" = "true"
 				register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C15)"
-				register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E19)"
+				register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E05)"
 				register "enable_delay_ms" = "3"
 				device spi 0 on
 					probe FP FP_PRESENT

From 454079c3bccd7d3bf389f9f692fab75dca3f11b9 Mon Sep 17 00:00:00 2001
From: Jeremy Compostella <jeremy.compostella@intel.com>
Date: Thu, 3 Jul 2025 17:13:08 -0700
Subject: [PATCH 1533/3886] lib/cbfs: Ensure cache buffer alignment in ramstage

The cache buffer is expected to be aligned to CONFIG_CBFS_CACHE_ALIGN by
the mem_pool_alloc function.

Change-Id: I153a4de5ae2b8549288946d0773009d586d5c65c
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88299
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/lib/cbfs.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/lib/cbfs.c b/src/lib/cbfs.c
index 03624bf2d7..f25030491e 100644
--- a/src/lib/cbfs.c
+++ b/src/lib/cbfs.c
@@ -23,7 +23,7 @@
 #if ENV_X86 && (ENV_POSTCAR || ENV_SMM)
 struct mem_pool cbfs_cache = MEM_POOL_INIT(NULL, 0, 0);
 #elif CONFIG(POSTRAM_CBFS_CACHE_IN_BSS) && ENV_RAMSTAGE
-static u8 cache_buffer[CONFIG_RAMSTAGE_CBFS_CACHE_SIZE];
+static u8 cache_buffer[CONFIG_RAMSTAGE_CBFS_CACHE_SIZE] __aligned(CONFIG_CBFS_CACHE_ALIGN);
 struct mem_pool cbfs_cache =
 	MEM_POOL_INIT(cache_buffer, sizeof(cache_buffer), CONFIG_CBFS_CACHE_ALIGN);
 #else

From edf47d44cd615fd27268bdf3215e9ea9d8e4aef0 Mon Sep 17 00:00:00 2001
From: Subrata Banik <subratabanik@google.com>
Date: Wed, 9 Jul 2025 07:21:50 +0000
Subject: [PATCH 1534/3886] mb/google/fatcat/var/fatcat: Disable Audio for
 invalid Audio FW_CONFIG

This commit modifies the Fatcat mainboard configuration to ensure the
Audio controller is only enabled when a valid `FW_CONFIG` is selected.

This change introduces audio probe statements that allow the
system to boot successfully even if `FW_CONFIG` is set to
`AUDIO_UNKNOWN`, effectively disabling the audio controller in such
cases.

This prevents boot failures when an unsupported or unknown audio codec
is selected, improving system robustness.

BUG=b:430205874
TEST=Able to boot google/fatcat to UI without valid Audio configuration.

Change-Id: I7d1fa07978725129c2651f258894f3590e0a69eb
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88365
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: YH Lin <yueherngl@google.com>
---
 src/mainboard/google/fatcat/variants/fatcat/overridetree.cb | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/src/mainboard/google/fatcat/variants/fatcat/overridetree.cb b/src/mainboard/google/fatcat/variants/fatcat/overridetree.cb
index 69c00ee8de..12c293b4a4 100644
--- a/src/mainboard/google/fatcat/variants/fatcat/overridetree.cb
+++ b/src/mainboard/google/fatcat/variants/fatcat/overridetree.cb
@@ -924,6 +924,11 @@ chip soc/intel/pantherlake
 
 		device ref smbus on end
 		device ref hda on
+			probe AUDIO AUDIO_MAX98373_ALC5682_SNDW
+			probe AUDIO AUDIO_ALC722_SNDW
+			probe AUDIO AUDIO_ALC256_HDA
+			probe AUDIO AUDIO_MAX98360_ALC5682I_I2S
+			probe AUDIO AUDIO_ALC721_SNDW
 			chip drivers/intel/soundwire
 				device generic 0 on
 					chip drivers/soundwire/alc711

From 306544b4276feb52df7be67b3767930f22ba872f Mon Sep 17 00:00:00 2001
From: Subrata Banik <subratabanik@google.com>
Date: Wed, 9 Jul 2025 07:25:28 +0000
Subject: [PATCH 1535/3886] mb/google/fatcat/var/francka: Add AUDIO_UNKNOWN and
 audio probes

This commit introduces an `AUDIO_UNKNOWN` option to the `fw_config` for
the Francka variant of the Fatcat mainboard. This allows for a default
or fallback state when a specific audio configuration isn't known or
desired.

Additionally, this change introduces audio probe statements that allow
the system to boot successfully even if `FW_CONFIG` is set to
`AUDIO_UNKNOWN`, effectively disabling the audio controller in such
cases.

This prevents boot failures when an unsupported or unknown audio codec
is selected, improving system robustness.

BUG=b:430205874
TEST=Able to boot google/francka to UI without valid Audio
configuration.

Change-Id: I34f7fe5f0509cbddfd3648afb087786373fcf8df
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88366
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: YH Lin <yueherngl@google.com>
---
 src/mainboard/google/fatcat/variants/francka/overridetree.cb | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/src/mainboard/google/fatcat/variants/francka/overridetree.cb b/src/mainboard/google/fatcat/variants/francka/overridetree.cb
index d93d6a1738..a0a6ec680d 100644
--- a/src/mainboard/google/fatcat/variants/francka/overridetree.cb
+++ b/src/mainboard/google/fatcat/variants/francka/overridetree.cb
@@ -8,6 +8,7 @@ fw_config
 		option AUDIO_ALC721_SNDW		1
 		option AUDIO_CS42L43_CS35L56_SNDW	2
 		option AUDIO_ALC722_ALC1320_SNDW	3
+		option AUDIO_UNKNOWN		7
 	end
 	field BRIDGE 6 7
 		option BRIDGE_HAYDEN		0
@@ -276,6 +277,10 @@ chip soc/intel/pantherlake
 
 		device ref smbus on end
 		device ref hda on
+			probe AUDIO AUDIO_ALC256M_CG_HDA
+			probe AUDIO AUDIO_ALC721_SNDW
+			probe AUDIO AUDIO_CS42L43_CS35L56_SNDW
+			probe AUDIO AUDIO_ALC722_ALC1320_SNDW
 			chip drivers/sof
 				register "spkr_tplg" = "max98360a"
 				register "jack_tplg" = "rt5682"

From a1dfd39e040d0985b09819e32d264b9a342e8051 Mon Sep 17 00:00:00 2001
From: Subrata Banik <subratabanik@google.com>
Date: Wed, 9 Jul 2025 07:28:20 +0000
Subject: [PATCH 1536/3886] mb/google/fatcat/var/kinmen: Add AUDIO_UNKNOWN and
 probe for ALC721

This commit enhances the Kinmen variant of the Fatcat mainboard by
introducing an `fw_config` field for AUDIO. This field includes an
`AUDIO_UNKNOWN` option, providing a clear state when no specific audio
configuration is selected or known.

Furthermore, a probe statement for `AUDIO_ALC721_SNDW` has been added
to the `hda` device. This ensures that the system can correctly identify
and initialize the Realtek ALC721 audio codec when present.

These changes improve the flexibility and accuracy of audio
configuration and detection for the Kinmen board.

BUG=b:430205874
TEST=Able to boot google/kinmen to UI without valid Audio configuration.

Change-Id: I86634a4a49c4006584fc808719b2891186953a51
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88367
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: YH Lin <yueherngl@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 .../google/fatcat/variants/kinmen/overridetree.cb    | 12 +++++++++++-
 1 file changed, 11 insertions(+), 1 deletion(-)

diff --git a/src/mainboard/google/fatcat/variants/kinmen/overridetree.cb b/src/mainboard/google/fatcat/variants/kinmen/overridetree.cb
index ac48600b97..edf70986e9 100644
--- a/src/mainboard/google/fatcat/variants/kinmen/overridetree.cb
+++ b/src/mainboard/google/fatcat/variants/kinmen/overridetree.cb
@@ -1,3 +1,10 @@
+fw_config
+	field AUDIO 3 5
+		option AUDIO_UNKNOWN		0
+		option AUDIO_ALC721_SNDW	1
+	end
+end
+
 chip soc/intel/pantherlake
 
 	# The initial version temporarily uses the PTL-H,
@@ -279,6 +286,7 @@ chip soc/intel/pantherlake
 
 		device ref smbus on end
 		device ref hda on
+			probe AUDIO AUDIO_ALC721_SNDW
 			chip drivers/intel/soundwire
 				device generic 0 on
 					chip drivers/soundwire/alc711
@@ -287,7 +295,9 @@ chip soc/intel/pantherlake
 						register "alc711_address.class" = "MIPI_CLASS_SDCA"
 						register "alc711_address.part_id" = "MIPI_DEV_ID_REALTEK_ALC721"
 						# SoundWire Link 3 ID 1
-						device generic 3.1 on end
+						device generic 3.1 on
+							probe AUDIO AUDIO_ALC721_SNDW
+						end
 					end
 				end
 			end

From 4f5f75da34a1432a1b258e1ecdbc4ec07a6f0fbc Mon Sep 17 00:00:00 2001
From: Ben Kao <ben.kao@intel.com>
Date: Thu, 3 Jul 2025 19:26:20 +0800
Subject: [PATCH 1537/3886] mb/trulo/var/pujjolo: Correct USB3 Type-A OC pins

Align USB3 Type-A and the related GPIO settings with Pujjolo schematic
(Pujjolo_Pujjoquince_MB_EVT_20250523.pdf).

BUG=b:427962702
TEST= Connect USB 3.0 devices to the Type-A interface and use "lsusb -t"
 command to verify the connection

Change-Id: I559dc8105258b91ca89b2f10644e4f95d6a4a085
Signed-off-by: Ben Kao <ben.kao@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88290
Reviewed-by: Derek Huang <derekhuang@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
---
 src/mainboard/google/brya/variants/pujjolo/gpio.c         | 8 ++++----
 .../google/brya/variants/pujjolo/overridetree.cb          | 4 ++--
 2 files changed, 6 insertions(+), 6 deletions(-)

diff --git a/src/mainboard/google/brya/variants/pujjolo/gpio.c b/src/mainboard/google/brya/variants/pujjolo/gpio.c
index 802dad18f9..ef612a6ee2 100644
--- a/src/mainboard/google/brya/variants/pujjolo/gpio.c
+++ b/src/mainboard/google/brya/variants/pujjolo/gpio.c
@@ -30,10 +30,10 @@ static const struct pad_config override_gpio_table[] = {
 	PAD_CFG_GPI_SCI_HIGH(GPP_A12, NONE, PLTRST, EDGE_BOTH),
 	/* A13 : GPP_A13 ==> GSC_SOC_INT_ODL */
 	PAD_CFG_GPI_APIC(GPP_A13, NONE, PLTRST, LEVEL, INVERT),
-	/* A14 : USB_OC1# */
-	PAD_CFG_NF(GPP_A14, NONE, DEEP, NF1),
-	/* A15 : USB_OC2# */
-	PAD_CFG_NF(GPP_A15, NONE, DEEP, NF1),
+	/* A14 : USB_OC1# ==> NC */
+	PAD_NC(GPP_A14, NONE),
+	/* A15 : USB_OC2# ==> NC */
+	PAD_NC(GPP_A15, NONE),
 	/* A16 : USB_OC3# ==> NC */
 	PAD_NC_LOCK(GPP_A16, NONE, LOCK_CONFIG),
 	/* A17 : NC */
diff --git a/src/mainboard/google/brya/variants/pujjolo/overridetree.cb b/src/mainboard/google/brya/variants/pujjolo/overridetree.cb
index 9347f7912e..ee9b93d2e1 100644
--- a/src/mainboard/google/brya/variants/pujjolo/overridetree.cb
+++ b/src/mainboard/google/brya/variants/pujjolo/overridetree.cb
@@ -66,8 +66,8 @@ chip soc/intel/alderlake
 	register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)"	# Bluetooth port for PCIe WLAN
 	register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)"	# Bluetooth port for CNVi WLAN
 
-	register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC1)"	# USB3 Type-A port A0(MLB))
-	register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC2)"	# USB3 Type-A port A1(DB)
+	register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)"	# USB3 Type-A port A0(MLB))
+	register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)"	# USB3 Type-A port A1(DB)
 
 	#register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)"	# USB3 port for WWAN
 

From 6e92554ab6a5421955894419b0aa3c61c4b3f9a1 Mon Sep 17 00:00:00 2001
From: Luca Lai <luca.lai@lcfc.corp-partner.google.com>
Date: Tue, 8 Jul 2025 15:33:37 +0800
Subject: [PATCH 1538/3886] mb/trulo/var/pujjolo: Modify FW_CONFIG for mipi
 camera

Because of internal misunderstanding, modify mipi camera FW_CONFIG

Schematic version: 500E_S3A0_TWL_MB_FVT_20250527

BUG=b:395763555
BRANCH=none
TEST=Boot to OS and verify the mipi camera device are set based on
     fw_config.

Change-Id: Id2d62d14bdfd6ad925c5a0c1a9799350a93e57e2
Signed-off-by: Luca Lai <luca.lai@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88352
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
---
 src/mainboard/google/brya/variants/pujjolo/overridetree.cb | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/mainboard/google/brya/variants/pujjolo/overridetree.cb b/src/mainboard/google/brya/variants/pujjolo/overridetree.cb
index ee9b93d2e1..32ca93d51b 100644
--- a/src/mainboard/google/brya/variants/pujjolo/overridetree.cb
+++ b/src/mainboard/google/brya/variants/pujjolo/overridetree.cb
@@ -18,7 +18,7 @@ fw_config
 	end
 	field WFC 26 27
 		option WFC_ABSENT               0
-		option WFC_MIPI_OVTI8856        2
+		option WFC_MIPI_OVTI8856        1
 	end
 end
 chip soc/intel/alderlake

From 6c4e502fddbd939d127b91e5c86b5bbac1c5d2af Mon Sep 17 00:00:00 2001
From: Baozhen Yang <yangbaozhen5@huaqin.corp-partner.google.com>
Date: Wed, 25 Jun 2025 10:12:32 +0800
Subject: [PATCH 1539/3886] mb/google/nissa/var/pujjocento: Reduce PL4 to 38W
 with no battery
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

When battery is not present, reduce power limits to below 45W,avoid
inability to enter the system.

To avoid poor efficiency of the adapter, leave a margin and set the
powerlimit to 38W.

This will check the current battery status and configure cpu power
limits using current PD power value.

BUG=b:418695656
BRANCH=None
TEST=
1、built (emerge-nissa coreboot chromeos-bootimage) and push ap firmware
   to dut.
2、Connect 15W machine without battery to 45W adapter and check if it
   starts up properly.
3、Use ec command “cbmem -c | grep PL“ to check if the PL4 value is 38
   watts.
   Log result:[INFO] CPU PL4 = 38 Watts

Change-Id: Iadd43c75ea9235b7ba0e3b97ef460280c13ef1e3
Signed-off-by: Baozhen Yang <yangbaozhen5@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88210
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
---
 .../brya/variants/pujjocento/Makefile.mk      |  1 +
 .../brya/variants/pujjocento/ramstage.c       | 35 +++++++++++++++++++
 2 files changed, 36 insertions(+)
 create mode 100644 src/mainboard/google/brya/variants/pujjocento/ramstage.c

diff --git a/src/mainboard/google/brya/variants/pujjocento/Makefile.mk b/src/mainboard/google/brya/variants/pujjocento/Makefile.mk
index f265e04132..f076cc9af9 100644
--- a/src/mainboard/google/brya/variants/pujjocento/Makefile.mk
+++ b/src/mainboard/google/brya/variants/pujjocento/Makefile.mk
@@ -4,5 +4,6 @@ bootblock-y += gpio.c
 romstage-y += gpio.c
 romstage-y += memory.c
 ramstage-y += gpio.c
+ramstage-y += ramstage.c
 ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_HDA_VERB) += hda_verb.c
 ramstage-y += variant.c
diff --git a/src/mainboard/google/brya/variants/pujjocento/ramstage.c b/src/mainboard/google/brya/variants/pujjocento/ramstage.c
new file mode 100644
index 0000000000..49441a20d8
--- /dev/null
+++ b/src/mainboard/google/brya/variants/pujjocento/ramstage.c
@@ -0,0 +1,35 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <baseboard/variants.h>
+#include <chip.h>
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci_ids.h>
+#include <device/pci_ops.h>
+#include <ec/google/chromeec/ec.h>
+#include <intelblocks/power_limit.h>
+
+#define NO_BATTERY_PL4_WATTS_LIMIT	38
+
+void variant_devtree_update(void)
+{
+	struct soc_power_limits_config *soc_config;
+	u32 pl4_watts = NO_BATTERY_PL4_WATTS_LIMIT;
+
+	soc_config = variant_get_soc_power_limit_config();
+	if (soc_config == NULL)
+		return;
+
+	/*
+	 * If battery is not present, reduce power limits to below 45W,
+	 * avoid inability to enter the system.
+	 * To avoid poor efficiency of the adapter, leave a margin and
+	 * set the powerlimit to 38W.
+	 */
+	if (!google_chromeec_is_battery_present()) {
+		/* Adjust PL4 values */
+		printk(BIOS_INFO, "previous PL4 value is %d, override PL4 settings to %d watts\n",
+		       soc_config->tdp_pl4, pl4_watts);
+		soc_config->tdp_pl4 = pl4_watts;
+	}
+}

From 5b3063802eeff8ff0dfbe40051b7a158448b489d Mon Sep 17 00:00:00 2001
From: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Date: Wed, 9 Jul 2025 10:42:34 +0800
Subject: [PATCH 1540/3886] mb/google/fatcat/var/kinmen: Fix touchscreen IRQ
 setting

Previously, the touchscreen IRQ pin was not correctly configured to
GPP_F18_IRQ, which caused an unexpected interrupt storm and led to
the touchscreen becoming unresponsive. This change sets it to the
correct configuration. (schematics version 20250611_v31)

BUG=b:430200649
TEST= Ensure the touchscreen is working properly.
Ensure the interrupt count increases only when the screen is touched
via 'cat /proc/interrupts | grep ELAN'

Change-Id: I20cc9632df76acdfafd2968ece0dde8ee95cc791
Signed-off-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88360
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
---
 src/mainboard/google/fatcat/variants/kinmen/overridetree.cb | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/mainboard/google/fatcat/variants/kinmen/overridetree.cb b/src/mainboard/google/fatcat/variants/kinmen/overridetree.cb
index edf70986e9..aeda394cbf 100644
--- a/src/mainboard/google/fatcat/variants/kinmen/overridetree.cb
+++ b/src/mainboard/google/fatcat/variants/kinmen/overridetree.cb
@@ -251,7 +251,7 @@ chip soc/intel/pantherlake
 			chip drivers/i2c/hid
 				register "generic.hid" = ""ELAN9004""
 				register "generic.desc" = ""ELAN Touchscreen""
-				register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_F18)"
+				register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_F18_IRQ)"
 				register "generic.detect" = "1"
 				register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_F16)"
 				register "generic.reset_delay_ms" = "150"

From 0660fe50de161591259ba9c1ffffe7da8e7c20f8 Mon Sep 17 00:00:00 2001
From: "P, Usha" <usha.p@intel.com>
Date: Mon, 16 Jun 2025 11:58:30 +0530
Subject: [PATCH 1541/3886] mb/google/ocelot: Update GPE configuration

This patch updates the GPE configuration for Ocelot in baseboard
devicetree based on schematic_1433518.

BUG=b:394208231, b:430001789
TEST=Build Ocelot and verify it compiles without any error.

Change-Id: I60bcf586ab8653732925bfd9393baef226519c3a
Signed-off-by: P, Usha <usha.p@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88106
Reviewed-by: Krishna P Bhat D <krishna.p.bhat.d@intel.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Sowmya Aralguppe <sowmya.aralguppe@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 .../google/ocelot/variants/baseboard/ocelot/devicetree.cb     | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/mainboard/google/ocelot/variants/baseboard/ocelot/devicetree.cb b/src/mainboard/google/ocelot/variants/baseboard/ocelot/devicetree.cb
index b79a3b3674..3c8ab4f7b1 100644
--- a/src/mainboard/google/ocelot/variants/baseboard/ocelot/devicetree.cb
+++ b/src/mainboard/google/ocelot/variants/baseboard/ocelot/devicetree.cb
@@ -1,7 +1,7 @@
 chip soc/intel/pantherlake
 	# GPE configuration
-	register "pmc_gpe0_dw0" = "GPP_A"
-	register "pmc_gpe0_dw1" = "GPP_D"
+	register "pmc_gpe0_dw0" = "GPP_VGPIO"
+	register "pmc_gpe0_dw1" = "GPP_B"
 	register "pmc_gpe0_dw2" = "GPP_E"
 
 	# For Ocelot variants with microchip EC:

From 48c6f66fa42b1c2730df54e13886eee18ed9c0e2 Mon Sep 17 00:00:00 2001
From: "P, Usha" <usha.p@intel.com>
Date: Tue, 8 Jul 2025 23:32:38 +0530
Subject: [PATCH 1542/3886] mb/google/ocelot: Update TPM_TIS_ACPI_INTERRUPT
 value in Kconfig

Update TPM related default value for TPM_TIS_ACPI_INTERRUPT based on
schematic_1433518 after mapping GPP_B to GPE0_DW1.

BUG=b:394208231, b:430001789
TEST=Build Ocelot and verify it compiles without any error.

Change-Id: I890c6779a24eaa7804594003466e8660af4becc2
Signed-off-by: P, Usha <usha.p@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88358
Reviewed-by: Krishna P Bhat D <krishna.p.bhat.d@intel.com>
Reviewed-by: Sowmya Aralguppe <sowmya.aralguppe@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
---
 src/mainboard/google/ocelot/Kconfig | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/mainboard/google/ocelot/Kconfig b/src/mainboard/google/ocelot/Kconfig
index 5e8a60b96f..304033b26c 100644
--- a/src/mainboard/google/ocelot/Kconfig
+++ b/src/mainboard/google/ocelot/Kconfig
@@ -142,7 +142,7 @@ config MEMORY_SOLDERDOWN
 
 config TPM_TIS_ACPI_INTERRUPT
 	int
-	default 17 if BOARD_GOOGLE_OCELOT # GPE0_DW0_17 (GPP_B17)
+	default 49 if BOARD_GOOGLE_OCELOT # GPE0_DW1_17 (GPP_B17)
 
 config UART_FOR_CONSOLE
 	int

From d5bce8c420e287c1000b59775dc81f2be0b42786 Mon Sep 17 00:00:00 2001
From: Walter Sonius <walterav1984@gmail.com>
Date: Sun, 6 Jul 2025 09:55:15 +0200
Subject: [PATCH 1543/3886] mb/hp: Add HP 260 G1 DM Business PC (Haswell)

This HP desktop comes in 4 different CPU variants. This port was made
using the Pentium 3558U @ 1.70GHz variant with 2*4GB DDR3L SODIMM RAM
modules with a single SATA adapter cable. Other variants may come with
an M2.SSD slot which may need other devicetree.cb PCIe / SATA edits!

Model: HP 260 G1 DM Business PC
Regulatory Model: TPC-1011-DM
Product No.: N9F00EA#ABH, 260G1eD/G3558U/500h/4X/50f NL
Mainboard: E131920, 791401-002

Pure autoport (initial commit) doesn't boot, further patches bring up
general Haswell fixes, vendor/product naming corrected, RAM SPD MAP
slot detection, (m)PCIe fixes enabling onboard LAN and mini PCIe slot
and some NPCD379 code from other HP desktops make most superio related
functions work for this PC.

Flash instructions:
After setting the FDO jumper on the motherboard the whole ROM can be
dumped, however writing is locked for some part of the BIOS region.
An external flasher ch341a_spi (3.3v mod) was used with a SOIC 8 pomona
probe to flash the MX25L6406E in situ without any issues. Only the
power of the USB programmer was used, and the board's main PSU was
disconnected during flash!

Tested:
 - coreboot 25.06-77-g812d0e2f626d as base
 - EDK2 (MrChromebox/2502)
 - SeaBIOS 1.16.3
 - SystemAgent mrc.bin (haswell/peppy)
 - libgfxinit textmode (SeaBIOS) / framebuffer (EDK2)
 - DP / DP++ (HDMI) & VGA all available during POST, BOOT and OS
 - Pentium 3558U
 - RAM single 4GB and dual slot 8GB total with 1.35V DDR3L SODIMMS
	4GB DDR3-1600 - SK Hynix HMT451S6BFR8A-PB (2016-W01)
	    HMT451S6BFR8A-PB NO AA 1601
	    1Rx8 PC3L-12800S-11-13-B4
	4GB DDR3 1600 - Kingston 9905469-143.A00LF (2016-W05)
	    KTH-X3CL/4G
	    1.35V
	    BPMK0831621
	    9905469-143.A00LF
	    0000007258426-PW005291
 - Fedora MATE 42 (Kernel 6.14)
 - KDE NEON 6.4 (Kernel 6.11)
 - Audio Outputs HDMI, Headphone, Lineout & Speaker (left&right chan.)
 - USB2/3 all ports
 - Realtek onboard Gb LAN
 - miniPCIe slot + its embedded USB (Intel Wireless AC3160HMW+BT)
 - SATA port using the original flatcable adapter
 - PowerButton (Poweron/Poweroff/Wake)
 - LEDs HDD & POWER (both off during suspend)
 - Shutdown/Reboot/Suspend
 - Strip down the Intel ME/TXE firmware (make menuconfig)
 - Disabling ME HECI (manually disable in devicetree.cb)
 - flashrom -p internal -c "MX25L6406E/MX25L6408E" (read & write)

Not tested:
 - Broadwell mrc.bin
 - Front Microphone Port
 - USBDEBUG
 - VBIOS

Not working:
 - FAN control its either full OFF or full ON see instruction!
 - Wake on LAN
 - Ethernet is detected as PCIe slot connected instead of onboard
 - Disable Intel ME PCI interface (make menuconfig)
 - Windows 10/11 USB detection/hotplug issues (all USB ports)
 - Haswell NRI (posts & boots but will shutdown in less than a minute)

FAN instructions:
If the superio HWM (devicetree.cb node pnp 2e.8) is set to on, the FAN
will turn OFF during post and stays OFF. If the superio HWM pnp 2e.8 is
set to off the FAN will stay ON and will rampup after post in roughly a
minute to its maximum RPM and will stay that way (current default)!

The data.vbt blob was extracted using debugfs from the OEM firmware
v2.19 which enables all video outputs Displayport / DP++ (HDMI) and VGA.

Theoretically like the "compaq_8200_elite_sff" it should be possible
to flash internally using a 2 step flash procedure using a minimized ME
a small SeaBIOS based coreboot and a temporary flash layout inside the
writeable BIOS region.

Change-Id: Ifedd9f700e5f3875d3577fa56225d9d49d622b47
Signed-off-by: Walter Sonius <walterav1984@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88326
Reviewed-by: Nicholas Chin <nic.c3.14@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/hp/260_g1_dm/Kconfig           |  29 ++++
 src/mainboard/hp/260_g1_dm/Kconfig.name      |   4 +
 src/mainboard/hp/260_g1_dm/Makefile.mk       |   5 +
 src/mainboard/hp/260_g1_dm/acpi/ec.asl       |   3 +
 src/mainboard/hp/260_g1_dm/acpi/platform.asl |  10 ++
 src/mainboard/hp/260_g1_dm/acpi/superio.asl  |   3 +
 src/mainboard/hp/260_g1_dm/board_info.txt    |   8 +
 src/mainboard/hp/260_g1_dm/data.vbt          | Bin 0 -> 6144 bytes
 src/mainboard/hp/260_g1_dm/devicetree.cb     | 160 +++++++++++++++++++
 src/mainboard/hp/260_g1_dm/dsdt.asl          |  27 ++++
 src/mainboard/hp/260_g1_dm/gma-mainboard.ads |  17 ++
 src/mainboard/hp/260_g1_dm/gpio.c            | 128 +++++++++++++++
 src/mainboard/hp/260_g1_dm/hda_verb.c        |  24 +++
 src/mainboard/hp/260_g1_dm/romstage.c        |  27 ++++
 14 files changed, 445 insertions(+)
 create mode 100644 src/mainboard/hp/260_g1_dm/Kconfig
 create mode 100644 src/mainboard/hp/260_g1_dm/Kconfig.name
 create mode 100644 src/mainboard/hp/260_g1_dm/Makefile.mk
 create mode 100644 src/mainboard/hp/260_g1_dm/acpi/ec.asl
 create mode 100644 src/mainboard/hp/260_g1_dm/acpi/platform.asl
 create mode 100644 src/mainboard/hp/260_g1_dm/acpi/superio.asl
 create mode 100644 src/mainboard/hp/260_g1_dm/board_info.txt
 create mode 100644 src/mainboard/hp/260_g1_dm/data.vbt
 create mode 100644 src/mainboard/hp/260_g1_dm/devicetree.cb
 create mode 100644 src/mainboard/hp/260_g1_dm/dsdt.asl
 create mode 100644 src/mainboard/hp/260_g1_dm/gma-mainboard.ads
 create mode 100644 src/mainboard/hp/260_g1_dm/gpio.c
 create mode 100644 src/mainboard/hp/260_g1_dm/hda_verb.c
 create mode 100644 src/mainboard/hp/260_g1_dm/romstage.c

diff --git a/src/mainboard/hp/260_g1_dm/Kconfig b/src/mainboard/hp/260_g1_dm/Kconfig
new file mode 100644
index 0000000000..deae64a5a4
--- /dev/null
+++ b/src/mainboard/hp/260_g1_dm/Kconfig
@@ -0,0 +1,29 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
+if BOARD_HP_260_G1_DM
+
+config BOARD_SPECIFIC_OPTIONS
+	def_bool y
+	select BOARD_ROMSIZE_KB_8192
+	select CPU_INTEL_HASWELL
+	select HAVE_ACPI_RESUME
+	select HAVE_ACPI_TABLES
+	select INTEL_GMA_HAVE_VBT
+	select INTEL_LYNXPOINT_LP
+	select MAINBOARD_HAS_LIBGFXINIT
+	select MAINBOARD_HAS_TPM1
+	select MEMORY_MAPPED_TPM
+	select NORTHBRIDGE_INTEL_HASWELL
+	select SERIRQ_CONTINUOUS_MODE
+	select SOUTHBRIDGE_INTEL_LYNXPOINT
+	select SUPERIO_NUVOTON_NPCD378
+
+config MAINBOARD_DIR
+	default "hp/260_g1_dm"
+
+config MAINBOARD_PART_NUMBER
+	default "260 G1 DM"
+
+config USBDEBUG_HCD_INDEX
+	default 1
+endif
diff --git a/src/mainboard/hp/260_g1_dm/Kconfig.name b/src/mainboard/hp/260_g1_dm/Kconfig.name
new file mode 100644
index 0000000000..2eccbf75c8
--- /dev/null
+++ b/src/mainboard/hp/260_g1_dm/Kconfig.name
@@ -0,0 +1,4 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
+config BOARD_HP_260_G1_DM
+	bool "260 G1 DM"
diff --git a/src/mainboard/hp/260_g1_dm/Makefile.mk b/src/mainboard/hp/260_g1_dm/Makefile.mk
new file mode 100644
index 0000000000..c9500cfe9b
--- /dev/null
+++ b/src/mainboard/hp/260_g1_dm/Makefile.mk
@@ -0,0 +1,5 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
+bootblock-y += gpio.c
+romstage-y += gpio.c
+ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads
diff --git a/src/mainboard/hp/260_g1_dm/acpi/ec.asl b/src/mainboard/hp/260_g1_dm/acpi/ec.asl
new file mode 100644
index 0000000000..16990d45f4
--- /dev/null
+++ b/src/mainboard/hp/260_g1_dm/acpi/ec.asl
@@ -0,0 +1,3 @@
+/* SPDX-License-Identifier: CC-PDDC */
+
+/* Please update the license if adding licensable material. */
diff --git a/src/mainboard/hp/260_g1_dm/acpi/platform.asl b/src/mainboard/hp/260_g1_dm/acpi/platform.asl
new file mode 100644
index 0000000000..aff432b6f4
--- /dev/null
+++ b/src/mainboard/hp/260_g1_dm/acpi/platform.asl
@@ -0,0 +1,10 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+Method(_WAK, 1)
+{
+	Return(Package() {0, 0})
+}
+
+Method(_PTS, 1)
+{
+}
diff --git a/src/mainboard/hp/260_g1_dm/acpi/superio.asl b/src/mainboard/hp/260_g1_dm/acpi/superio.asl
new file mode 100644
index 0000000000..16990d45f4
--- /dev/null
+++ b/src/mainboard/hp/260_g1_dm/acpi/superio.asl
@@ -0,0 +1,3 @@
+/* SPDX-License-Identifier: CC-PDDC */
+
+/* Please update the license if adding licensable material. */
diff --git a/src/mainboard/hp/260_g1_dm/board_info.txt b/src/mainboard/hp/260_g1_dm/board_info.txt
new file mode 100644
index 0000000000..1c9a30d23a
--- /dev/null
+++ b/src/mainboard/hp/260_g1_dm/board_info.txt
@@ -0,0 +1,8 @@
+Category: desktop
+Board URL: https://support.hp.com/us-en/product/setup-user-guides/hp-260-g1-desktop-mini-pc/7375834
+ROM IC: MX25L6406E
+ROM protocol: SPI
+Flashrom support: y
+ROM package: SOIC8
+ROM socketed: no
+Release year: 2015
diff --git a/src/mainboard/hp/260_g1_dm/data.vbt b/src/mainboard/hp/260_g1_dm/data.vbt
new file mode 100644
index 0000000000000000000000000000000000000000..d89e108323795186463bd0ef214f74b6d27d01f7
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literal 0
HcmV?d00001

diff --git a/src/mainboard/hp/260_g1_dm/devicetree.cb b/src/mainboard/hp/260_g1_dm/devicetree.cb
new file mode 100644
index 0000000000..cf6c95bc35
--- /dev/null
+++ b/src/mainboard/hp/260_g1_dm/devicetree.cb
@@ -0,0 +1,160 @@
+chip northbridge/intel/haswell
+	register "dq_pins_interleaved" = "1"
+	register "ec_present" = "false"
+
+	register "gpu_ddi_e_connected" = "1"
+
+	register "spd_addresses" = "{0x50, 0, 0x51, 0}"
+
+	chip cpu/intel/haswell
+		device cpu_cluster 0x0 on ops haswell_cpu_bus_ops end
+	end
+	device domain 0x0 on
+		ops haswell_pci_domain_ops
+		subsystemid 0x103c 0x8000 inherit
+
+		device pci 00.0 on end # ULT Host bridge
+		device pci 02.0 on end # Internal graphics VGA controller
+		device pci 03.0 on end # Mini-HD audio
+		chip southbridge/intel/lynxpoint # Intel Series 8 Lynx Point PCH
+			register "docking_supported" = "1"
+			register "gen1_dec" = "0x00fc0a01"
+			register "gen2_dec" = "0x00fc0b01"
+			register "gpe0_en_4" = "0x2046"
+			register "sata_port0_gen3_dtle" = "0x7"
+			register "sata_port1_gen3_dtle" = "0x9"
+			register "sata_port_map" = "0x1"
+			device pci 13.0 off end # Smart Sound Audio DSP
+			device pci 14.0 on end # xHCI Controller
+			device pci 15.0 off end # Serial I/O DMA
+			device pci 15.1 off end # I2C0
+			device pci 15.2 off end # I2C1
+			device pci 15.3 off end # GSPI0
+			device pci 15.4 off end # GSPI1
+			device pci 15.5 off end # UART0
+			device pci 15.6 off end # UART1
+			device pci 16.0 on end # Management Engine Interface 1
+			device pci 16.1 off end # Management Engine Interface 2
+			device pci 16.2 off end # Management Engine IDE-R
+			device pci 16.3 off end # Management Engine KT
+			device pci 17.0 off end # SDIO
+			device pci 19.0 off end # Intel Gigabit Ethernet
+			device pci 1b.0 on end # High Definition Audio
+			device pci 1c.0 off end # PCIe Port #1
+			device pci 1c.1 off end # PCIe Port #2
+			device pci 1c.2 on end # Onboard Realtek LAN
+			device pci 1c.3 on end # X1PCIEXP11
+			device pci 1c.4 off end # PCIe Port #5
+			device pci 1c.5 off end # PCIe Port #6
+			device pci 1d.0 on end # USB2 EHCI #1
+			device pci 1f.0 on # LPC bridge
+				chip superio/common
+					device pnp 2e.ff on # passes SIO base addr to SSDT gen
+						chip superio/nuvoton/npcd378
+							device pnp 2e.0 off end		# Floppy
+							device pnp 2e.1 off		# Parallel port
+								# global
+
+								# serialice: Vendor writes:
+								irq 0x14 = 0xd0
+								irq 0x1c = 0xa8
+								irq 0x1d = 0x01
+								irq 0x22 = 0x3f
+								irq 0x1a = 0xa0
+								# dumped from superiotool:
+								irq 0x1b = 0x1e
+								irq 0x27 = 0x08
+								irq 0x2a = 0x00
+								irq 0x2d = 0x21
+								# parallel port
+								io 0x60 = 0x278
+								irq 0x70 = 0x07
+								drq 0x74 = 0x04
+							end
+							device pnp 2e.2 off		# COM1
+								io 0x60 = 0x2f8
+								irq 0x70 = 3
+							end
+							device pnp 2e.3 off		# COM2, IR
+								io 0x60 = 0x3f8
+								irq 0x70 = 4
+							end
+							device pnp 2e.4 on		# LED control
+								io 0x60 = 0x0a20
+								# IOBASE[0h] = bit0 LED red / green
+								# IOBASE[0h] = bit1-4 LED PWM duty cycle
+								# IOBASE[1h] = bit6 SWCC
+
+								io 0x62 = 0x0aa0
+								# IOBASE [0h] = GPES
+								# IOBASE [1h] = GPEE
+								# IOBASE [4h:7h] = 32bit upcounter at 1Mhz
+								# IOBASE [8h:bh] = GPS
+								# IOBASE [ch:fh] = GPE
+							end
+							device pnp 2e.5 off		# Mouse
+								irq 0x70 = 0xc
+							end
+							device pnp 2e.6 off		# Keyboard
+								io 0x60 = 0x0060
+								io 0x62 = 0x0064
+								irq 0x70 = 0x01
+								# serialice: Vendor writes:
+								drq 0xf0 = 0x40
+							end
+							device pnp 2e.7 on		#  WDT ?
+								io 0x60 = 0x0a00
+							end
+							device pnp 2e.8 off		# HWM
+								io 0x60 = 0x0b00
+								# IOBASE[0h:feh] HWM page
+								# IOBASE[ffh] bit0-bit3 page selector
+
+								drq 0xf0 = 0x20
+								drq 0xf1 = 0x01
+								drq 0xf2 = 0x40
+								drq 0xf3 = 0x01
+
+								drq 0xf4 = 0x66
+								drq 0xf5 = 0x66
+								drq 0xf6 = 0x66
+								drq 0xf7 = 0x01
+							end
+							device pnp 2e.f on		# GPIO OD ?
+								drq 0xf1 = 0x97
+								drq 0xf2 = 0x01
+								drq 0xf5 = 0x0b
+								drq 0xfe = 0x80
+							end
+							device pnp 2e.15 off		# BUS ?
+								io 0x60 = 0x0000
+								io 0x62 = 0x0000
+							end
+							device pnp 2e.1c on		# Suspend Control ?
+								io 0x60 = 0x0a60
+								# writing to IOBASE[5h]
+								#  0x0: Power off
+								#  0x9: Power off and bricked until CMOS battery removed
+							end
+							device pnp 2e.1e off	# GPIO ?
+								io 0x60 = 0x0000
+								drq 0xf4 = 0x00
+								# skip the following, as it
+								# looks like remapped registers
+								#drq 0xf5 = 0x06
+								#drq 0xf6 = 0x60
+								#drq 0xfe = 0x03
+							end
+						end
+					end
+				end
+				chip drivers/pc80/tpm
+					device pnp 4e.0 on end          # TPM module
+				end
+			end
+			device pci 1f.2 on end # SATA Controller (AHCI)
+			device pci 1f.3 on end # SMBus
+			device pci 1f.6 off end # Thermal
+		end
+	end
+end
diff --git a/src/mainboard/hp/260_g1_dm/dsdt.asl b/src/mainboard/hp/260_g1_dm/dsdt.asl
new file mode 100644
index 0000000000..2eb0805cf2
--- /dev/null
+++ b/src/mainboard/hp/260_g1_dm/dsdt.asl
@@ -0,0 +1,27 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <acpi/acpi.h>
+
+DefinitionBlock(
+	"dsdt.aml",
+	"DSDT",
+	ACPI_DSDT_REV_2,
+	OEM_ID,
+	ACPI_TABLE_CREATOR,
+	0x20141018
+)
+{
+	#include <acpi/dsdt_top.asl>
+	#include "acpi/platform.asl"
+	#include <cpu/intel/common/acpi/cpu.asl>
+	#include <southbridge/intel/common/acpi/platform.asl>
+	/* global NVS and variables. */
+	#include <southbridge/intel/lynxpoint/acpi/globalnvs.asl>
+	#include <southbridge/intel/common/acpi/sleepstates.asl>
+
+	Device (\_SB.PCI0)
+	{
+		#include <northbridge/intel/haswell/acpi/hostbridge.asl>
+		#include <southbridge/intel/lynxpoint/acpi/pch.asl>
+	}
+}
diff --git a/src/mainboard/hp/260_g1_dm/gma-mainboard.ads b/src/mainboard/hp/260_g1_dm/gma-mainboard.ads
new file mode 100644
index 0000000000..439aff80c1
--- /dev/null
+++ b/src/mainboard/hp/260_g1_dm/gma-mainboard.ads
@@ -0,0 +1,17 @@
+-- SPDX-License-Identifier: GPL-2.0-or-later
+
+with HW.GFX.GMA;
+with HW.GFX.GMA.Display_Probing;
+
+use HW.GFX.GMA;
+use HW.GFX.GMA.Display_Probing;
+
+private package GMA.Mainboard is
+
+   ports : constant Port_List :=
+     (DP1,
+      HDMI1,
+      DP2,
+      others => Disabled);
+
+end GMA.Mainboard;
diff --git a/src/mainboard/hp/260_g1_dm/gpio.c b/src/mainboard/hp/260_g1_dm/gpio.c
new file mode 100644
index 0000000000..4f48be2737
--- /dev/null
+++ b/src/mainboard/hp/260_g1_dm/gpio.c
@@ -0,0 +1,128 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <southbridge/intel/lynxpoint/lp_gpio.h>
+
+const struct pch_lp_gpio_map mainboard_lp_gpio_map[] = {
+	[0]  = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT, .owner = GPIO_OWNER_GPIO },
+	[1]  = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT, .owner = GPIO_OWNER_GPIO },
+	[2]  = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT, .owner = GPIO_OWNER_GPIO },
+	[3]  = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT, .owner = GPIO_OWNER_GPIO },
+	[4]  = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT, .owner = GPIO_OWNER_GPIO },
+	[5]  = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT, .owner = GPIO_OWNER_GPIO },
+	[6]  = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT, .owner = GPIO_OWNER_GPIO },
+	[7]  = LP_GPIO_INPUT,
+	[8]  = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT, .owner = GPIO_OWNER_GPIO,
+		.pirq = GPIO_PIRQ_APIC_ROUTE
+		},
+	[9]  = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT, .owner = GPIO_OWNER_GPIO,
+		.pirq = GPIO_PIRQ_APIC_ROUTE
+		},
+	[10] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT, .owner = GPIO_OWNER_GPIO,
+		.pirq = GPIO_PIRQ_APIC_ROUTE
+		},
+	[11] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT, .owner = GPIO_OWNER_GPIO },
+	[12] = LP_GPIO_OUT_LOW,
+	[13] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT, .owner = GPIO_OWNER_GPIO,
+		.pirq = GPIO_PIRQ_APIC_ROUTE
+		},
+	[14] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT, .owner = GPIO_OWNER_GPIO,
+		.pirq = GPIO_PIRQ_APIC_ROUTE
+		},
+	[15] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT, .owner = GPIO_OWNER_GPIO },
+	[16] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT, .owner = GPIO_OWNER_GPIO },
+	[17] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT, .owner = GPIO_OWNER_GPIO },
+	[18] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT, .owner = GPIO_OWNER_GPIO },
+	[19] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT, .owner = GPIO_OWNER_GPIO },
+	[20] = LP_GPIO_NATIVE,
+	[21] = LP_GPIO_NATIVE,
+	[22] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT, .owner = GPIO_OWNER_GPIO },
+	[23] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT, .owner = GPIO_OWNER_GPIO },
+	[24] = LP_GPIO_OUT_LOW,
+	[25] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT, .owner = GPIO_OWNER_GPIO },
+	[26] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT, .owner = GPIO_OWNER_GPIO },
+	[27] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT, .owner = GPIO_OWNER_GPIO },
+	[28] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT, .owner = GPIO_OWNER_GPIO },
+	[29] = LP_GPIO_NATIVE,
+	[30] = LP_GPIO_NATIVE,
+	[31] = LP_GPIO_NATIVE,
+	[32] = LP_GPIO_NATIVE,
+	[33] = LP_GPIO_NATIVE,
+	[34] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT, .owner = GPIO_OWNER_GPIO },
+	[35] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT, .owner = GPIO_OWNER_GPIO },
+	[36] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT, .owner = GPIO_OWNER_GPIO },
+	[37] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT, .owner = GPIO_OWNER_GPIO },
+	[38] = LP_GPIO_NATIVE,
+	[39] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT, .owner = GPIO_OWNER_GPIO },
+	[40] = LP_GPIO_NATIVE,
+	[41] = LP_GPIO_NATIVE,
+	[42] = LP_GPIO_NATIVE,
+	[43] = LP_GPIO_NATIVE,
+	[44] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT, .owner = GPIO_OWNER_GPIO },
+	[45] = LP_GPIO_OUT_LOW,
+	[46] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT, .owner = GPIO_OWNER_GPIO,
+		.pirq = GPIO_PIRQ_APIC_ROUTE
+		},
+	[47] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT, .owner = GPIO_OWNER_GPIO,
+		.pirq = GPIO_PIRQ_APIC_ROUTE
+		},
+	[48] = LP_GPIO_PIRQ,
+	[49] = LP_GPIO_PIRQ,
+	[50] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT, .owner = GPIO_OWNER_GPIO,
+		.pirq = GPIO_PIRQ_APIC_ROUTE
+		},
+	[51] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT, .owner = GPIO_OWNER_GPIO,
+		.pirq = GPIO_PIRQ_APIC_ROUTE
+		},
+	[52] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT, .owner = GPIO_OWNER_GPIO,
+		.pirq = GPIO_PIRQ_APIC_ROUTE
+		},
+	[53] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT, .owner = GPIO_OWNER_GPIO,
+		.pirq = GPIO_PIRQ_APIC_ROUTE
+		},
+	[54] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT, .owner = GPIO_OWNER_GPIO,
+		.pirq = GPIO_PIRQ_APIC_ROUTE
+		},
+	[55] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT, .owner = GPIO_OWNER_GPIO,
+		.pirq = GPIO_PIRQ_APIC_ROUTE
+		},
+	[56] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT, .owner = GPIO_OWNER_GPIO },
+	[57] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT, .owner = GPIO_OWNER_GPIO },
+	[58] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT, .owner = GPIO_OWNER_GPIO },
+	[59] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT, .owner = GPIO_OWNER_GPIO },
+	[60] = LP_GPIO_NATIVE,
+	[61] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT, .owner = GPIO_OWNER_GPIO },
+	[62] = LP_GPIO_NATIVE,
+	[63] = LP_GPIO_NATIVE,
+	[64] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT, .owner = GPIO_OWNER_GPIO },
+	[65] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT, .owner = GPIO_OWNER_GPIO },
+	[66] = LP_GPIO_NATIVE,
+	[67] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT, .owner = GPIO_OWNER_GPIO },
+	[68] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT, .owner = GPIO_OWNER_GPIO },
+	[69] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT, .owner = GPIO_OWNER_GPIO },
+	[70] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT, .owner = GPIO_OWNER_GPIO },
+	[71] = LP_GPIO_NATIVE,
+	[72] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT, .owner = GPIO_OWNER_GPIO },
+	[73] = LP_GPIO_NATIVE,
+	[74] = LP_GPIO_NATIVE,
+	[75] = LP_GPIO_NATIVE,
+	[76] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT, .owner = GPIO_OWNER_GPIO },
+	[77] = LP_GPIO_INPUT,
+	[78] = LP_GPIO_INPUT,
+	[79] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT, .owner = GPIO_OWNER_GPIO },
+	[80] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT, .owner = GPIO_OWNER_GPIO },
+	[81] = LP_GPIO_NATIVE,
+	[82] = LP_GPIO_NATIVE,
+	[83] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT, .owner = GPIO_OWNER_GPIO },
+	[84] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT, .owner = GPIO_OWNER_GPIO },
+	[85] = LP_GPIO_INPUT,
+	[86] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT, .owner = GPIO_OWNER_GPIO },
+	[87] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT, .owner = GPIO_OWNER_GPIO },
+	[88] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT, .owner = GPIO_OWNER_GPIO },
+	[89] = LP_GPIO_INPUT,
+	[90] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT, .owner = GPIO_OWNER_GPIO },
+	[91] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT, .owner = GPIO_OWNER_GPIO },
+	[92] = LP_GPIO_INPUT,
+	[93] = LP_GPIO_INPUT,
+	[94] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT, .owner = GPIO_OWNER_GPIO },
+	LP_GPIO_END
+};
diff --git a/src/mainboard/hp/260_g1_dm/hda_verb.c b/src/mainboard/hp/260_g1_dm/hda_verb.c
new file mode 100644
index 0000000000..f3614d8910
--- /dev/null
+++ b/src/mainboard/hp/260_g1_dm/hda_verb.c
@@ -0,0 +1,24 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <device/azalia_device.h>
+
+const u32 cim_verb_data[] = {
+	0x10ec0221,	/* Codec Vendor / Device ID: Realtek */
+	0x103c8000,	/* Subsystem ID */
+	11,		/* Number of 4 dword sets */
+	AZALIA_SUBVENDOR(0, 0x103c8000),
+	AZALIA_PIN_CFG(0, 0x12, 0x400c0000),
+	AZALIA_PIN_CFG(0, 0x14, 0x01014020),
+	AZALIA_PIN_CFG(0, 0x17, 0x90170110),
+	AZALIA_PIN_CFG(0, 0x18, AZALIA_PIN_CFG_NC(0)),
+	AZALIA_PIN_CFG(0, 0x19, AZALIA_PIN_CFG_NC(0)),
+	AZALIA_PIN_CFG(0, 0x1a, 0x02a11030),
+	AZALIA_PIN_CFG(0, 0x1b, AZALIA_PIN_CFG_NC(0)),
+	AZALIA_PIN_CFG(0, 0x1d, 0x40500001),
+	AZALIA_PIN_CFG(0, 0x1e, AZALIA_PIN_CFG_NC(0)),
+	AZALIA_PIN_CFG(0, 0x21, 0x0221102f),
+};
+
+const u32 pc_beep_verbs[0] = {};
+
+AZALIA_ARRAY_SIZES;
diff --git a/src/mainboard/hp/260_g1_dm/romstage.c b/src/mainboard/hp/260_g1_dm/romstage.c
new file mode 100644
index 0000000000..e5c559a2da
--- /dev/null
+++ b/src/mainboard/hp/260_g1_dm/romstage.c
@@ -0,0 +1,27 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <southbridge/intel/lynxpoint/pch.h>
+
+void mainboard_config_rcba(void)
+{
+}
+
+const struct usb2_port_config mainboard_usb2_ports[MAX_USB2_PORTS] = {
+	/* FIXME: Length and Location are computed from IOBP values, may be inaccurate */
+	/* Length, Enable, OCn#, Location */
+	{ 0x0080, 1, 1, USB_PORT_MINI_PCIE },
+	{ 0x0080, 1, 0, USB_PORT_MINI_PCIE },
+	{ 0x0040, 1, 3, USB_PORT_BACK_PANEL },
+	{ 0x0080, 1, 3, USB_PORT_DOCK },
+	{ 0x0080, 1, 2, USB_PORT_MINI_PCIE },
+	{ 0x0080, 1, 2, USB_PORT_MINI_PCIE },
+	{ 0x0040, 1, 1, USB_PORT_BACK_PANEL },
+	{ 0x0040, 1, 1, USB_PORT_BACK_PANEL },
+};
+
+const struct usb3_port_config mainboard_usb3_ports[MAX_USB3_PORTS] = {
+	{ 1, 1 },
+	{ 1, 0 },
+	{ 1, 3 },
+	{ 1, 3 },
+};

From 2f5b384ba5bc9ef05a7c2e33cd7cc688e1fcc370 Mon Sep 17 00:00:00 2001
From: Vince Liu <vince-wl.liu@mediatek.corp-partner.google.com>
Date: Wed, 9 Jul 2025 09:56:25 +0800
Subject: [PATCH 1544/3886] soc/mediatek/mt8189: Enable EARLY_MMU_INIT to
 improve boot time

The boot time is improved by 50ms in bootblock.

BUG=b:379008996
BRANCH=none
TEST=check the boot time by `cbmem`.
(previous)
11:start of bootblock                                247,551 (60)
12:end of bootblock                                  312,495 (64,944)

(now)
11:start of bootblock                                255,424 (60)
12:end of bootblock                                  270,911 (15,487)

Signed-off-by: Vince Liu <vince-wl.liu@mediatek.corp-partner.google.com>
Change-Id: I0c3a5cff7eecb67e34d8ff1d3084f6a34d9cdbe0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88368
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
---
 src/soc/mediatek/mt8189/Kconfig     | 1 +
 src/soc/mediatek/mt8189/Makefile.mk | 2 +-
 2 files changed, 2 insertions(+), 1 deletion(-)

diff --git a/src/soc/mediatek/mt8189/Kconfig b/src/soc/mediatek/mt8189/Kconfig
index 7cf5ebe64f..ea3c7d2ece 100644
--- a/src/soc/mediatek/mt8189/Kconfig
+++ b/src/soc/mediatek/mt8189/Kconfig
@@ -8,6 +8,7 @@ config SOC_MEDIATEK_MT8189
 	select ARCH_ROMSTAGE_ARMV8_64
 	select ARCH_RAMSTAGE_ARMV8_64
 	select ARM64_USE_ARM_TRUSTED_FIRMWARE
+	select EARLY_MMU_INIT
 	select HAVE_UART_SPECIAL
 	select CACHE_MRC_SETTINGS
 	select MEDIATEK_DRAM_BLOB_FAST_INIT
diff --git a/src/soc/mediatek/mt8189/Makefile.mk b/src/soc/mediatek/mt8189/Makefile.mk
index 1386ed063d..2f73bcc1f0 100644
--- a/src/soc/mediatek/mt8189/Makefile.mk
+++ b/src/soc/mediatek/mt8189/Makefile.mk
@@ -10,7 +10,7 @@ all-$(CONFIG_SPI_FLASH) += ../common/spi.c spi.c
 all-y += ../common/timer_prepare.c timer.c
 all-y += ../common/uart.c
 
-bootblock-y += bootblock.c
+bootblock-y += ../common/bootblock.c bootblock.c
 bootblock-y += efuse.c
 bootblock-y += ../common/mmu_operations.c
 bootblock-y += ../common/mtcmos.c mtcmos.c

From 18c067d3920e353aa712922e23c10fa285f14220 Mon Sep 17 00:00:00 2001
From: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Date: Tue, 8 Jul 2025 12:03:01 +0800
Subject: [PATCH 1545/3886] mb/google/fatcat/var/kinmen: Add Synaptics touchpad

Add support for Synaptics HID-over-I2C touchpad
(addr and offset per spec: Product Spec_03510_Rev1.pdf)

BUG=None
TEST=1. emerge-fatcat coreboot
     2. check touchpad function is working properly.

Change-Id: Ib4e96e9b7df7d9adba2534b12eaf5d6cb7bb4317
Signed-off-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88349
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
---
 .../google/fatcat/variants/kinmen/overridetree.cb        | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/src/mainboard/google/fatcat/variants/kinmen/overridetree.cb b/src/mainboard/google/fatcat/variants/kinmen/overridetree.cb
index aeda394cbf..3fc3d28ff5 100644
--- a/src/mainboard/google/fatcat/variants/kinmen/overridetree.cb
+++ b/src/mainboard/google/fatcat/variants/kinmen/overridetree.cb
@@ -246,6 +246,15 @@ chip soc/intel/pantherlake
 				register "hid_desc_reg_offset" = "0x20"
 				device i2c 68 on end
 			end
+			chip drivers/i2c/hid
+				register "generic.hid" = ""PNP0C50""
+				register "generic.desc" = ""Synaptics Touchpad""
+				register "generic.irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_E18_IRQ)"
+				register "generic.wake" = "GPE0_DW2_18"
+				register "generic.detect" = "1"
+				register "hid_desc_reg_offset" = "0x20"
+				device i2c 2c on end
+			end
 		end # I2C4
 		device ref i2c5 on
 			chip drivers/i2c/hid

From 396a883a0cc0bbc07dd16e062a8a5ff084c0acf1 Mon Sep 17 00:00:00 2001
From: Walter Sonius <walterav1984@gmail.com>
Date: Sat, 5 Jul 2025 19:58:59 +0000
Subject: [PATCH 1546/3886] mb/hp/snb_ivb_desktops: Include PS/2 controller ASL
 code for MS Windows

The PS/2 Keyboard and Mouse won't work in Microsoft Windows 10 or 11 on
these tested HP variants:
 - compaq_pro_6300
 - compaq_8200_elite_sff
 - compaq_8300_elite_sff

Unless the following line to acpi/superio.asl was added:
#include <drivers/pc80/pc/ps2_controller.asl>

Without this patch PS/2 ports only work in EDK2, SeaBIOS, GRUB 2 and
Linux.

Dmesg output for comparison without and with patch (trimmed):
[    0.232601] pnp: PnP ACPI: found 16 devices
...
[    0.231146] pnp: PnP ACPI: found 18 devices
...

TEST=Boot Windows 10 / 11 verify that PS/2 Keyboard & Mouse works!

Although only 3 models were tested and this common option affects all
snb_ivb_desktops variants I'm pretty confident it will work on all the
others since it also works on boards from other Manufacturers from Dell
and GIGABYTE even single port with splitter cable.

Change-Id: I21c10cc24c25887ab822a5889de5eec3b3537ac9
Signed-off-by: Walter Sonius <walterav1984@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88322
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
---
 src/mainboard/hp/snb_ivb_desktops/acpi/superio.asl | 1 +
 1 file changed, 1 insertion(+)

diff --git a/src/mainboard/hp/snb_ivb_desktops/acpi/superio.asl b/src/mainboard/hp/snb_ivb_desktops/acpi/superio.asl
index 506c6d4c2d..1488e3a83e 100644
--- a/src/mainboard/hp/snb_ivb_desktops/acpi/superio.asl
+++ b/src/mainboard/hp/snb_ivb_desktops/acpi/superio.asl
@@ -1,5 +1,6 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
+#include <drivers/pc80/pc/ps2_controller.asl>
 #include <superio/nuvoton/npcd378/acpi/superio.asl>
 
 Scope (\_GPE)

From f74027d5aef2b99f12a1ef05642030976d5594fe Mon Sep 17 00:00:00 2001
From: David Wu <david_wu@quanta.corp-partner.google.com>
Date: Wed, 9 Jul 2025 17:26:52 +0800
Subject: [PATCH 1547/3886] mb/google/nissa/var/craask: Add elan touchscreen
 support

This change adds the necessary configuration for the elan
touchscreen (ELAN9004) device, connected to I2C bus 16.

It includes settings for:
* HID descriptor
* Device description
* IRQ configuration
* Detection
* Reset, stop and enable GPIOs with their respective delays
* Power resource handling
* HID descriptor register offset

BUG=b:430467732
TEST=emerge-nissa coreboot and elan touchscreen can work well.

Change-Id: I08a32eae272d5ef93f1c89bcb96b9ba50c037624
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88370
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
---
 .../brya/variants/craask/overridetree.cb      | 20 +++++++++++++++++++
 1 file changed, 20 insertions(+)

diff --git a/src/mainboard/google/brya/variants/craask/overridetree.cb b/src/mainboard/google/brya/variants/craask/overridetree.cb
index f95d0ae2c2..677abedb47 100644
--- a/src/mainboard/google/brya/variants/craask/overridetree.cb
+++ b/src/mainboard/google/brya/variants/craask/overridetree.cb
@@ -395,6 +395,26 @@ chip soc/intel/alderlake
 					probe TS_SOURCE TS_UNPROVISIONED
 				end
 			end
+			chip drivers/i2c/hid
+				register "generic.hid" = ""ELAN9004""
+				register "generic.desc" = ""ELAN Touchscreen""
+				register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_C7_IRQ)"
+				register "generic.detect" = "1"
+				register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C1)"
+				register "generic.reset_delay_ms" = "20"
+				register "generic.reset_off_delay_ms" = "2"
+				register "generic.stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C6)"
+				register "generic.stop_delay_ms" = "280"
+				register "generic.stop_off_delay_ms" = "2"
+				register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C0)"
+				register "generic.enable_delay_ms" = "1"
+				register "generic.has_power_resource" = "1"
+				register "generic.use_gpio_for_status" = "true"
+				register "hid_desc_reg_offset" = "0x01"
+				device i2c 16 on
+					probe TS_SOURCE TS_UNPROVISIONED
+				end
+			end
 			chip drivers/i2c/hid
 				register "generic.hid" = ""ILTK0001""
 				register "generic.desc" = ""ILITEK Touchscreen""

From 7b8520ab690e4c145903f767dc120d534be54f90 Mon Sep 17 00:00:00 2001
From: erin liang <erin.liang@lcfc.corp-partner.google.com>
Date: Thu, 3 Jul 2025 17:34:58 +0800
Subject: [PATCH 1548/3886] mb/trulo/var/pujjolo: Update fingerprint enable pin
 status

Update fingerprint enable pin status to keep the module disabled
and in reset in firmware. This allows the module to be enabled
and released from reset during kernel boot via ACPI.

BUG=b:411558536
BRANCH=none
TEST= Boot to OS and into VT2, use ectool --name=cros_fp version
will return fingerprint version information and check the
functionality works.

Change-Id: I98707e0e6ba550f6b7d75a84e72843c3873fa56c
Signed-off-by: erin liang <erin.liang@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88287
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
---
 src/mainboard/google/brya/variants/pujjolo/gpio.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/mainboard/google/brya/variants/pujjolo/gpio.c b/src/mainboard/google/brya/variants/pujjolo/gpio.c
index ef612a6ee2..505333437d 100644
--- a/src/mainboard/google/brya/variants/pujjolo/gpio.c
+++ b/src/mainboard/google/brya/variants/pujjolo/gpio.c
@@ -119,7 +119,7 @@ static const struct pad_config override_gpio_table[] = {
 	/* D1  : ISH_GP1 ==> SOC_GSEN2_INT# */
 	PAD_CFG_NF(GPP_D1, NONE, DEEP, NF1),
 	/* D2  : NC => EN_FP_PWR */
-	PAD_CFG_GPO_LOCK(GPP_D2, 1, LOCK_CONFIG),
+	PAD_CFG_GPO_LOCK(GPP_D2, 0, LOCK_CONFIG),
 	/* D3  : ISH_GP3 ==> WCAM_RST_L */
 	PAD_CFG_GPO_LOCK(GPP_D3, 0, LOCK_CONFIG),
 	/* D4  : IMGCLKOUT0 ==> BT_DISABLE_L */

From e013c9586c3132eae3274793f3f1cd21cc59f550 Mon Sep 17 00:00:00 2001
From: Luca Lai <luca.lai@lcfc.corp-partner.google.com>
Date: Thu, 3 Jul 2025 17:05:57 +0800
Subject: [PATCH 1549/3886] mb/trulo/var/pujjolo: Modify mipi camera parameters

Because of intel suggestion, the change will fix the sensor driver
could be "probe fail" issue. So update mipi camera parameters' value.

Change:
1. CSI Camera lanes from 2 to 4.
2. Value of index 0 of frequency link array from 720000000 to 360000000
3. Value of index 1 of frequency link array from 360000000 to 180000000

BUG=b:395763555
BRANCH=none
TEST=Build and boot to OS and check mipi camera function.

Change-Id: Ieea6d99182df9c5aa9ca7a7f72f031921c24199e
Signed-off-by: Luca Lai <luca.lai@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88288
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
---
 .../google/brya/variants/pujjolo/overridetree.cb          | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/src/mainboard/google/brya/variants/pujjolo/overridetree.cb b/src/mainboard/google/brya/variants/pujjolo/overridetree.cb
index 32ca93d51b..9c273d23d8 100644
--- a/src/mainboard/google/brya/variants/pujjolo/overridetree.cb
+++ b/src/mainboard/google/brya/variants/pujjolo/overridetree.cb
@@ -170,7 +170,7 @@ chip soc/intel/alderlake
 				register "device_type" = "INTEL_ACPI_CAMERA_CIO2"
 
 				register "cio2_num_ports" = "1"
-				register "cio2_lanes_used" = "{2}" # 2 CSI Camera lanes are used
+				register "cio2_lanes_used" = "{4}" # 4 CSI Camera lanes are used
 				register "cio2_lane_endpoint[0]" = ""^I2C4.CAM0""
 				register "cio2_prt[0]" = "1"
 				device generic 0 on end
@@ -320,13 +320,13 @@ chip soc/intel/alderlake
 				register "has_power_resource" = "1"
 				register "max_dstate_for_probe" = "ACPI_DEVICE_SLEEP_D3_COLD"
 
-				register "ssdb.lanes_used" = "2"
+				register "ssdb.lanes_used" = "4"
 				register "ssdb.link_used" = "1"
 				register "ssdb.vcm_type" = "0x0C"
 				register "vcm_name" = ""VCM0""
 				register "num_freq_entries" = "2"
-				register "link_freq[0]" = "720000000"
-				register "link_freq[1]" = "360000000"
+				register "link_freq[0]" = "360000000"
+				register "link_freq[1]" = "180000000"
 				register "remote_name" = ""IPU0""
 
 				#Controls

From 5db8bf0cfa7be8c964ad53cb544a460f24709661 Mon Sep 17 00:00:00 2001
From: Luca Lai <luca.lai@lcfc.corp-partner.google.com>
Date: Mon, 7 Jul 2025 14:32:15 +0800
Subject: [PATCH 1550/3886] mb/trulo/var/pujjolo: Enable USB3 WWAN device

Enable USB3 WWAN since the issue is fixed with the latest schematics.

Schematic version: 500E_S3A0_TWL_MB_FVT_20250527

BUG=b:424945817
BRANCH=none
TEST=Remove Verify USB3 WWAN with the latest schematics.check the WWAN USB3 interface is now working properly..

Change-Id: I30eb74a8456bc63c964269822e0b10135d24aa1f
Signed-off-by: Luca Lai <luca.lai@lcfc.corp-partner.google.com>

Schematic version: 500E_S3A0_TWL_MB_FVT_20250527

BUG=b:424945817
BRANCH=none
TEST=Verify USB3 WWAN with the latest schematics.

Change-Id: I30eb74a8456bc63c964269822e0b10135d24aa1f
Signed-off-by: Luca Lai <luca.lai@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88340
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/google/brya/variants/pujjolo/overridetree.cb | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/mainboard/google/brya/variants/pujjolo/overridetree.cb b/src/mainboard/google/brya/variants/pujjolo/overridetree.cb
index 9c273d23d8..c6cce61c73 100644
--- a/src/mainboard/google/brya/variants/pujjolo/overridetree.cb
+++ b/src/mainboard/google/brya/variants/pujjolo/overridetree.cb
@@ -69,7 +69,7 @@ chip soc/intel/alderlake
 	register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)"	# USB3 Type-A port A0(MLB))
 	register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)"	# USB3 Type-A port A1(DB)
 
-	#register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)"	# USB3 port for WWAN
+	register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)"	# USB3 port for WWAN
 
 	# HD Audio
 	register "pch_hda_dsp_enable" = "1"

From 569b7a8861837f736dda50a152f7bc302f5d0341 Mon Sep 17 00:00:00 2001
From: Martin Roth <gaumless@gmail.com>
Date: Fri, 4 Jul 2025 12:03:34 -0600
Subject: [PATCH 1551/3886] Docs/releases: Finalize 25.06 release notes

This change incorporates the final statistics for the 26.06 release and
changes it from upcoming to the final version of the notes.
- Add a section for Project Updates
- Update the introduction, removing the comment about GCC 15, which was
a bit confusing. We can now build the toolchain with GCC 15, but it is
not yet part of the toolchain.

Change-Id: I27defefacdf8b3a826c801da051e3218394f81e2
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88312
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 .../releases/coreboot-25.06-relnotes.md       | 49 +++++++++++++------
 1 file changed, 35 insertions(+), 14 deletions(-)

diff --git a/Documentation/releases/coreboot-25.06-relnotes.md b/Documentation/releases/coreboot-25.06-relnotes.md
index 50ac305cc7..05cf066275 100644
--- a/Documentation/releases/coreboot-25.06-relnotes.md
+++ b/Documentation/releases/coreboot-25.06-relnotes.md
@@ -1,14 +1,15 @@
-Upcoming release - coreboot 25.06
+coreboot 25.06
 ========================================================================
 
 The coreboot project is pleased to announce the release of coreboot
 25.06, another milestone in our work promoting the use of open-source
 firmware. This release incorporates almost 900 commits from more than
-120 contributors, bringing enhanced boot splash screen capabilities,
-improved build tooling with GCC 15 support, and expanded wireless power
-management features. Along with these headline improvements, we've
-delivered numerous stability enhancements and infrastructure updates
-that strengthen coreboot's foundation across all supported platforms.
+120 contributors, including 28 first time contributors. It brings
+enhanced boot splash screen capabilities, improved build tooling
+support, and expanded wireless power management features. Along with
+these headline improvements, we've delivered numerous stability
+enhancements and infrastructure updates that strengthen coreboot's
+foundation across all supported platforms.
 
 As always, the coreboot project extends our appreciation to everyone who
 contributed to this release. From seasoned developers submitting complex
@@ -20,6 +21,26 @@ vitality of the open firmware community.
 The next coreboot release, 25.09, is scheduled for the end of September
 2025.
 
+Project Updates
+---------------
+
+* In the past several months, the coreboot project has worked to help
+  groups who can't always push their code directly to the main
+  development branch, offering to host separate branches and separate
+  repositories for this work. A document with more details will be
+  uploaded shortly.
+* The coreboot project has had bi-weekly leadership meetings where
+  project issues are discussed for a number of years, but they've always
+  been at a time which makes it difficult for people in Asia to attend.
+  We are going to start a second meeting on the same day as the existing
+  meeting, but at a better time for Asia. Check the coreboot calendar
+  for details: https://www.coreboot.org/calendar.html
+* After many years, the coreboot mascot finally has a name: Blitz, the
+  corebunny. This is a reference to the boot speed which can be achieved
+  through using the coreboot project, and reflects the design intent of
+  the logo, a European Brown Hare, which is very adaptable and runs at
+  speeds of up to 72 km/h (45 mph).
+
 
 Significant or interesting changes
 ----------------------------------
@@ -248,15 +269,15 @@ Platform Updates
 
 Statistics from the 25.03 to the 25.06 release
 --------------------------------------------
-* Total Commits: 879
-* Average Commits per day: 9.95
-* Total lines added: 73596
-* Average lines added per commit: 83.73
-* Number of patches adding more than 100 lines: 84
-* Average lines added per small commit: 40.40
-* Total lines removed: 15717
+* Total Commits: 882
+* Average Commits per day: 9.85
+* Total lines added: 73906
+* Average lines added per commit: 83.79
+* Number of patches adding more than 100 lines: 85
+* Average lines added per small commit: 40.39
+* Total lines removed: 15766
 * Average lines removed per commit: 17.88
-* Total difference between added and removed: 57879
+* Total difference between added and removed: 58140
 * Total authors: 128
 * New authors: 34
 

From 8b52167a9f7d31a009b123e152c5c62dcf0a5202 Mon Sep 17 00:00:00 2001
From: Jeremy Compostella <jeremy.compostella@intel.com>
Date: Fri, 27 Jun 2025 14:48:43 -0700
Subject: [PATCH 1552/3886] arch/x86: Add support for cooperative multitasking
 on x86_64

This commit extends the cooperative multitasking functionality to
support the x86_64 architecture. Previously, cooperative multitasking
was only available for x86_32, as indicated by the error directive in
thread.c.

A new thread_switch_64.S file has been added to implement 64-bit
register handling for thread switching, and thread_switch.S has been
renamed to thread_switch_32.S accordingly.

Change-Id: I14ed625160a62e42d800757d30397c6c85f943b4
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88216
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/arch/x86/Makefile.mk                      | 10 ++-
 src/arch/x86/thread.c                         | 26 ++++--
 .../{thread_switch.S => thread_switch_32.S}   |  0
 src/arch/x86/thread_switch_64.S               | 86 +++++++++++++++++++
 4 files changed, 115 insertions(+), 7 deletions(-)
 rename src/arch/x86/{thread_switch.S => thread_switch_32.S} (100%)
 create mode 100644 src/arch/x86/thread_switch_64.S

diff --git a/src/arch/x86/Makefile.mk b/src/arch/x86/Makefile.mk
index a455a09100..0aaa962cfa 100644
--- a/src/arch/x86/Makefile.mk
+++ b/src/arch/x86/Makefile.mk
@@ -159,7 +159,10 @@ romstage-y += postcar_loader.c
 romstage-$(CONFIG_COLLECT_TIMESTAMPS_TSC) += timestamp.c
 romstage-$(CONFIG_HAVE_CF9_RESET) += cf9_reset.c
 romstage-$(CONFIG_COOP_MULTITASKING) += thread.c
-romstage-$(CONFIG_COOP_MULTITASKING) += thread_switch.S
+ifeq ($(CONFIG_COOP_MULTITASKING),y)
+romstage-$(CONFIG_ARCH_ROMSTAGE_X86_32) += thread_switch_32.S
+romstage-$(CONFIG_ARCH_ROMSTAGE_X86_64) += thread_switch_64.S
+endif # CONFIG_COOP_MULTITASKING
 romstage-y += car.ld
 
 romstage-srcs += $(wildcard $(src)/mainboard/$(MAINBOARDDIR)/romstage.c)
@@ -248,7 +251,10 @@ ramstage-y += rdrand.c
 ramstage-$(CONFIG_GENERATE_SMBIOS_TABLES) += smbios.c
 ramstage-y += tables.c
 ramstage-$(CONFIG_COOP_MULTITASKING) += thread.c
-ramstage-$(CONFIG_COOP_MULTITASKING) += thread_switch.S
+ifeq ($(CONFIG_COOP_MULTITASKING),y)
+ramstage-$(CONFIG_ARCH_RAMSTAGE_X86_32) += thread_switch_32.S
+ramstage-$(CONFIG_ARCH_RAMSTAGE_X86_64) += thread_switch_64.S
+endif # CONFIG_COOP_MULTITASKING
 ramstage-$(CONFIG_COLLECT_TIMESTAMPS_TSC) += timestamp.c
 ramstage-$(CONFIG_HAVE_ACPI_RESUME) += wakeup.S
 ramstage-$(CONFIG_HAVE_CF9_RESET) += cf9_reset.c
diff --git a/src/arch/x86/thread.c b/src/arch/x86/thread.c
index fa6096161b..bdc02fbfa2 100644
--- a/src/arch/x86/thread.c
+++ b/src/arch/x86/thread.c
@@ -3,11 +3,26 @@
 #include <thread.h>
 
 #if ENV_X86_64
-#error COOP_MULTITASKING does not currently support x86_64
-#endif
-
+struct saved_regs {
+	uint64_t r15; /* Offset 0x00 */
+	uint64_t r14; /* Offset 0x08 */
+	uint64_t r13; /* Offset 0x10 */
+	uint64_t r12; /* Offset 0x18 */
+	uint64_t r11; /* Offset 0x20 */
+	uint64_t r10; /* Offset 0x28 */
+	uint64_t r9;  /* Offset 0x30 */
+	uint64_t r8;  /* Offset 0x38 */
+	uint64_t rdi; /* Offset 0x40 */
+	uint64_t rsi; /* Offset 0x48 */
+	uint64_t rbp; /* Offset 0x50 */
+	uint64_t rbx; /* Offset 0x58 */
+	uint64_t rdx; /* Offset 0x60 */
+	uint64_t rcx; /* Offset 0x68 */
+	uint64_t rax; /* Offset 0x70 */
+};
+#else
 /* The stack frame looks like the following after a pushad instruction. */
-struct pushad_regs {
+struct saved_regs {
 	uint32_t edi; /* Offset 0x00 */
 	uint32_t esi; /* Offset 0x04 */
 	uint32_t ebp; /* Offset 0x08 */
@@ -17,6 +32,7 @@ struct pushad_regs {
 	uint32_t ecx; /* Offset 0x18 */
 	uint32_t eax; /* Offset 0x1c */
 };
+#endif	/* ENV_X86_64 */
 
 static inline uintptr_t push_stack(uintptr_t cur_stack, uintptr_t value)
 {
@@ -39,7 +55,7 @@ void arch_prepare_thread(struct thread *t,
 	stack = push_stack(stack, (uintptr_t)0);
 	stack = push_stack(stack, (uintptr_t)thread_entry);
 	/* Make room for the registers. Ignore initial values. */
-	stack -= sizeof(struct pushad_regs);
+	stack -= sizeof(struct saved_regs);
 
 	t->stack_current = stack;
 }
diff --git a/src/arch/x86/thread_switch.S b/src/arch/x86/thread_switch_32.S
similarity index 100%
rename from src/arch/x86/thread_switch.S
rename to src/arch/x86/thread_switch_32.S
diff --git a/src/arch/x86/thread_switch_64.S b/src/arch/x86/thread_switch_64.S
new file mode 100644
index 0000000000..b4397f10dc
--- /dev/null
+++ b/src/arch/x86/thread_switch_64.S
@@ -0,0 +1,86 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+/*
+ * Stack layout after pushing all the registers.
+ * +------------+
+ * |  ret addr  | <-- esp + 0x78
+ * +------------+
+ * |    rax     | <-- esp + 0x70
+ * +------------+
+ * |    rcx     | <-- esp + 0x68
+ * +------------+
+ * |    rdx     | <-- esp + 0x60
+ * +------------+
+ * |    rbx     | <-- esp + 0x58
+ * +------------+
+ * |    rbp     | <-- esp + 0x50
+ * +------------+
+ * |    rsi     | <-- esp + 0x48
+ * +------------+
+ * |    rdi     | <-- esp + 0x40
+ * +------------+
+ * |    r8      | <-- esp + 0x38
+ * +------------+
+ * |    r9      | <-- esp + 0x30
+ * +------------+
+ * |    r10     | <-- esp + 0x28
+ * +------------+
+ * |    r11     | <-- esp + 0x20
+ * +------------+
+ * |    r12     | <-- esp + 0x18
+ * +------------+
+ * |    r13     | <-- esp + 0x10
+ * +------------+
+ * |    r14     | <-- esp + 0x08
+ * +------------+
+ * |    r15     | <-- esp + 0x00
+ * +------------+
+ */
+.global switch_to_thread
+switch_to_thread:
+	/* Backup registers. */
+	push	%rax
+	push	%rcx
+	push	%rdx
+	push	%rbx
+
+	push	%rbp
+	push	%rsi
+	push	%rdi
+
+	push	%r8
+	push	%r9
+	push	%r10
+	push	%r11
+	push	%r12
+	push	%r13
+	push	%r14
+	push	%r15
+
+	/* Save the current stack */
+	mov	%rsp, (%rsi)
+
+	/* Switch to the new stack. */
+	mov	%rdi, %rsp
+
+	/* Restore registers. */
+	pop	%r15
+	pop	%r14
+	pop	%r13
+	pop	%r12
+	pop	%r11
+	pop	%r10
+	pop	%r9
+	pop	%r8
+
+	pop	%rdi
+	pop	%rsi
+	pop	%rbp
+
+	pop	%rbx
+	pop	%rdx
+	pop	%rcx
+	pop	%rax
+
+	/* Done. */
+	ret

From 0e682859e7b4524468792d2882a3b91b47232724 Mon Sep 17 00:00:00 2001
From: Elyes Haouas <ehaouas@noos.fr>
Date: Mon, 30 Dec 2024 10:32:13 +0100
Subject: [PATCH 1553/3886] payloads/external/U-Boot: Upgrade from 2024.07 to
 v2025.07

Change-Id: Id31a726e475ea1d1dd1b8c08a150849d1045e95e
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85804
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
---
 payloads/external/U-Boot/Kconfig | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/payloads/external/U-Boot/Kconfig b/payloads/external/U-Boot/Kconfig
index e2bdddfd70..28bc72765d 100644
--- a/payloads/external/U-Boot/Kconfig
+++ b/payloads/external/U-Boot/Kconfig
@@ -9,14 +9,14 @@ config PAYLOAD_SPECIFIC_OPTIONS
 
 config UBOOT_STABLE_COMMIT_ID
 	string
-	default "v2024.07"
+	default "v2025.07"
 
 choice
 	prompt "U-Boot version"
 	default UBOOT_STABLE
 
 config UBOOT_STABLE
-	bool "v2024.07"
+	bool "v2025.07"
 	help
 	  Stable U-Boot version
 

From e35c784847087b65745674e9183ee1a51863c5e0 Mon Sep 17 00:00:00 2001
From: Nir Lichtman <nir@lichtman.org>
Date: Fri, 11 Jul 2025 21:04:38 +0300
Subject: [PATCH 1554/3886] Doc/gfx/libgfxinit.md: Fix file names in source
 code references

The files were renamed in commit 7458629de369 (drivers/intel/gma: Move gfxinit into sub package).

Change-Id: I41de759809122cdef8d4449fb6f564bbcd48bf9e
Signed-off-by: Nir Lichtman <nir@lichtman.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88392
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nicholas Chin <nic.c3.14@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
---
 Documentation/gfx/libgfxinit.md | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/Documentation/gfx/libgfxinit.md b/Documentation/gfx/libgfxinit.md
index 40f194a4eb..a9163b001f 100644
--- a/Documentation/gfx/libgfxinit.md
+++ b/Documentation/gfx/libgfxinit.md
@@ -22,14 +22,14 @@ GMA: Framebuffer Configuration
 *coreboot* supports two different framebuffer setups. The default
 enables the legacy VGA plane in textmode. Due to legacy hardware
 constraints, only the first found display is enabled in this mode.
-(cf. `src/drivers/intel/gma/text_fb/gma.adb`).
+(cf. `src/drivers/intel/gma/text_fb/gma-gfx_init.adb`).
 
 The second option sets up a high-resolution framebuffer with the
 native resolution of the display if only one is detected, or the
 smallest of all resolutions (per dimension) if multiple displays
 are detected. This option is selected by
 `CONFIG_FRAMEBUFFER_KEEP_VESA_MODE`.
-(cf. `src/drivers/intel/gma/hires_fb/gma.adb`).
+(cf. `src/drivers/intel/gma/hires_fb/gma-gfx_init.adb`).
 
 In any case, a smaller framebuffer is up-scaled to each display's
 native resolution while keeping aspect ratio.

From 8e666c367df66d1fe8b84f92eb811e03f5a1c9c5 Mon Sep 17 00:00:00 2001
From: Sasirekaa Madhesu <smadhesu@qualcomm.corp-partner.google.com>
Date: Mon, 14 Jul 2025 10:38:08 +0530
Subject: [PATCH 1555/3886] soc/qualcomm/x1p42100: Update boot critical
 firmware memory layout

This patch updates the memory layout for AP Firmware boot on the
Qualcomm x1p42100 SoC. This update is crucial to ensure that all
processors and co-processors can successfully load their
respective blobs during the process of booting to the OS.

TEST=Successfully booted google/blueu.

Change-Id: Ibce385e9d201f0a3c5daf19e8dfe235fa9f695af
Signed-off-by: Sasirekaa Madhesu <smadhesu@qualcomm.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88420
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
---
 src/soc/qualcomm/x1p42100/memlayout.ld | 25 +++++++++++++++----------
 1 file changed, 15 insertions(+), 10 deletions(-)

diff --git a/src/soc/qualcomm/x1p42100/memlayout.ld b/src/soc/qualcomm/x1p42100/memlayout.ld
index c2e2f90766..016b2aef9c 100644
--- a/src/soc/qualcomm/x1p42100/memlayout.ld
+++ b/src/soc/qualcomm/x1p42100/memlayout.ld
@@ -19,16 +19,14 @@
 
 SECTIONS
 {
-	REGION(shrm, 0x09060000, 64K , 4K)
-
 	AOPSRAM_START(0x0B000000)
 	REGION(aop_code_ram, 0x0B000000, 0x80000, 4096)
 	REGION(aop_data_ram, 0x0B0E0000, 0x20000, 4096)
 	AOPSRAM_END(0x0B100000)
 
 	SSRAM_START(0x14680000)
-	OVERLAP_DECOMPRESSOR_VERSTAGE_ROMSTAGE(0x14680000, 132K)
-	REGION(qcsdi, 0x146A1000, 40K, 4K)
+	REGION(qcsdi, 0x14699000, 48K, 4K)
+	REGION(shared_imem, 0x146A8000, 12K, 4K)
 	SSRAM_END(0x146AB000)
 
 	BSRAM_START(0x14800000)
@@ -45,12 +43,19 @@ SECTIONS
 	CBFS_MCACHE(0x1485C000,16K)
 	REGION(ddr_information, 0x14860000, 1K, 1K)
 	FMAP_CACHE(0x14860400, 2K)
-	REGION(dcb, 0x14862000, 32K, 4K)
-	REGION(pmic, 0x1486A000, 96K, 4K)
-	REGION(ddr_training, 0x14882000, 32K, 4K)
-	REGION(qclib, 0x1488A000, 800K, 4K)
-	PRERAM_CBMEM_CONSOLE(0x14954000, 32K)
-	BSRAM_END(0x1495C000)
+	REGION(dcb, 0x14862000, 56K, 4K)
+	REGION(dtb, 0x14870000, 32K, 4K)
+	REGION(ddr_training, 0x14878000, 64K, 4K)
+	REGION(shrm_meta, 0x14888000, 16K, 4K)
+	REGION(debug_policy_meta,0x1488C000 , 12K, 4K)
+	REGION(qclib, 0x14897000, 1536K, 4K)
+	PRERAM_CBMEM_CONSOLE(0x14A17000, 32K)
+	OVERLAP_DECOMPRESSOR_VERSTAGE_ROMSTAGE(0x14A38000, 132K)
+	REGION(auth_metadata,0x14A7D000 , 8K, 4K)
+	REGION(debug_policy, 0x14A7F000, 4K, 4K)
+	BSRAM_END(0x14A80000)
+
+	REGION(shrm, 0x24040000, 128K , 4K)
 
 	DRAM_START(0x80000000)
 	POSTRAM_CBFS_CACHE(0x9F800000, 16M)

From d745d383939a21a149852157b6fad849ae5ee234 Mon Sep 17 00:00:00 2001
From: Jeremy Compostella <jeremy.compostella@intel.com>
Date: Wed, 2 Jul 2025 13:12:48 -0700
Subject: [PATCH 1556/3886] soc/intel/cmn/block/fast_spi: Add DMA support

This commit introduces Direct Memory Access (DMA) support for the Intel
Fast SPI block, enhancing data transfer capabilities from SPI flash
memory. The primary motivation for this addition is to improve
performance in multitasking environments by offloading read operations
to DMA, thus freeing up CPU resources for other tasks. The traditional
memory-mapped SPI flash read operations can be CPU-intensive and slow in
scenarios where large data volumes are transferred.

This feature is gated by a FAST_SPI_DMA configuration option. The DMA
operations are integrated with existing SPI flash read functionalities,
ensuring fallback to memory-mapped operations if DMA is unsupported or
fails. The DMA code implementation uses mutex-based synchronization to
ensure thread-safe DMA transactions.

The boot_device_ro() function has been modified to check for DMA support
and installs custom DMA operations when available.

We conducted measurements on a 200 KB data transfer and noticed a 1.8%
improvement with DMA compared to memcpy on memory-mapped SPINOR, with
DMA taking 10.8 ms and memcpy taking 11 ms.

Change-Id: I4b4ca9ff08e436ca627afa6b0d9bb00f3c450a5e
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88277
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/soc/intel/common/block/fast_spi/Kconfig   |  10 +
 .../intel/common/block/fast_spi/Makefile.mk   |   1 +
 .../common/block/fast_spi/fast_spi_dma.c      | 405 ++++++++++++++++++
 .../common/block/fast_spi/fast_spi_dma.h      |  42 ++
 .../intel/common/block/fast_spi/mmap_boot.c   |   4 +
 5 files changed, 462 insertions(+)
 create mode 100644 src/soc/intel/common/block/fast_spi/fast_spi_dma.c
 create mode 100644 src/soc/intel/common/block/fast_spi/fast_spi_dma.h

diff --git a/src/soc/intel/common/block/fast_spi/Kconfig b/src/soc/intel/common/block/fast_spi/Kconfig
index 3a541f861c..a983797989 100644
--- a/src/soc/intel/common/block/fast_spi/Kconfig
+++ b/src/soc/intel/common/block/fast_spi/Kconfig
@@ -60,3 +60,13 @@ config FAST_SPI_GENERATE_SSDT
 	  If this switch is selected, an entry in the SSDT will be generated
 	  for the controller to report the occupied resource which is not
 	  discoverable at OS runtime.
+
+config FAST_SPI_DMA
+	bool
+	help
+	  Choose this option to allow the use of the SPI DMA controller, if
+	  it's available. When enabled, the boot read-only region device
+	  functions are enhanced with a DMA version of the readat()
+	  callback. Although DMA transfers may not be significantly faster,
+	  they can free up CPU resources for other meaningful tasks in a
+	  multitasking environment (see COOP_MULTITASKING).
diff --git a/src/soc/intel/common/block/fast_spi/Makefile.mk b/src/soc/intel/common/block/fast_spi/Makefile.mk
index 6e274df69f..e2325d9f3e 100644
--- a/src/soc/intel/common/block/fast_spi/Makefile.mk
+++ b/src/soc/intel/common/block/fast_spi/Makefile.mk
@@ -10,6 +10,7 @@ romstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_FAST_SPI) += fast_spi_flash.c
 
 ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_FAST_SPI) += fast_spi.c
 ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_FAST_SPI) += fast_spi_flash.c
+ramstage-$(CONFIG_FAST_SPI_DMA) += fast_spi_dma.c
 
 postcar-$(CONFIG_SOC_INTEL_COMMON_BLOCK_FAST_SPI) += fast_spi.c
 postcar-$(CONFIG_SOC_INTEL_COMMON_BLOCK_FAST_SPI) += fast_spi_flash.c
diff --git a/src/soc/intel/common/block/fast_spi/fast_spi_dma.c b/src/soc/intel/common/block/fast_spi/fast_spi_dma.c
new file mode 100644
index 0000000000..c21056aa18
--- /dev/null
+++ b/src/soc/intel/common/block/fast_spi/fast_spi_dma.c
@@ -0,0 +1,405 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <console/console.h>
+#include <delay.h>
+#include <device/pci.h>
+#include <fast_spi_dma.h>
+#include <static.h>
+#include <thread.h>
+#include <timer.h>
+
+#define REGION_BIOS	1
+
+/* BIOS DMA Fast SPI registers */
+enum fast_spi_dma_register {
+	FAST_SPI_DMA_DEST_ADDRESS_HIGH = 0xb0,
+	FAST_SPI_DMA_DEST_ADDRESS_LOW = 0xb4,
+	FAST_SPI_DMA_REGION = 0xb8,
+	FAST_SPI_DMA_CONTROL = 0xbc,
+	FAST_SPI_DMA_STATUS = 0xc0
+};
+
+/* FAST_SPI_DMA_REGION */
+union fast_spi_dma_region {
+	uint32_t data;
+	struct {
+		uint32_t reserved: 16;
+		uint32_t offset_kb: 16;
+	} fields;
+};
+
+/* FAST_SPI_DMA_CONTROL */
+union fast_spi_dma_control {
+	uint32_t data;
+	struct {
+		uint32_t start: 1;
+		uint32_t reserved0: 5;
+		uint32_t reset_write_pointer: 1;
+		uint32_t reserved1: 1;
+		uint32_t flash_region: 4;
+		uint32_t reserved2: 3;
+		uint32_t lock: 1;
+		uint32_t size: 16;
+	} fields;
+};
+
+/* FAST_SPI_DMA_STATUS */
+union fast_spi_dma_status {
+	uint32_t data;
+	struct {
+		uint32_t reserved0: 2;
+		uint32_t complete: 1;
+		uint32_t error: 5;
+		uint32_t reserved1: 8;
+		uint32_t write_pointer: 16;
+	} fields;
+};
+
+#define FAST_SPI_DMA_BLOCK_ALIGN	KiB
+#define FAST_SPI_DMA_TIMEOUT_MSEC	1000
+#define FAST_SPI_DMA_DELAY_STEP_USEC	200
+#define FAST_SPI_DEV			DEV_PTR(fast_spi)
+
+/*
+ * The bios_top variable stores the offset indicating the end of the BIOS region within
+ * the SPI flash memory map. It is calculated based on the size and arrangement of memory
+ * regions within the flash device. This value is used in DMA operations to determine the
+ * correct addressing and transfer boundaries.
+ */
+static uint32_t bios_top;
+
+/*
+ * Pointer to the operations structure for memory-mapped region devices. This pointer is
+ * used to store and access the original operations associated with the memory-mapped
+ * device, allowing for custom operations such as DMA transfers to be installed and
+ * utilized while preserving the original functionalities.
+ */
+static const struct region_device_ops *mmap_ops;
+
+/*
+ * The fast_spi_dma_mutex is used to ensure thread-safe access to DMA operations. This
+ * synchronization mechanism guarantees that only one thread can perform DMA operations
+ * at a time.
+ */
+static struct thread_mutex fast_spi_dma_mutex;
+
+static inline uint32_t fast_spi_read(enum fast_spi_dma_register reg)
+{
+	return pci_read_config32(FAST_SPI_DEV, reg);
+}
+
+static inline void fast_spi_write(enum fast_spi_dma_register reg, uint32_t value)
+{
+	pci_write_config32(FAST_SPI_DEV, reg, value);
+}
+
+/*
+ * Perform a DMA transfer using the Fast SPI interface.
+ *
+ * This function initiates a DMA transfer from the SPI flash to a specified buffer. It
+ * configures the necessary registers, handles potential errors, and ensures proper
+ * completion of the DMA operation. If the operation succeeds, it returns CB_SUCCESS;
+ * otherwise, it returns CB_ERR.
+ *
+ * @param buffer Pointer to the destination buffer where the data will be transferred.
+ * @param size Number of blocks to transfer, specified in 1KB units.
+ * @param offset Offset within the flash region from where the transfer begins.
+ *
+ * @return CB_SUCCESS if the DMA transfer completes successfully,
+ *         CB_ERR if the operation encounters an error or times out.
+ */
+static enum cb_err fast_spi_do_dma_transfer(void *buffer, uint32_t size, uint32_t offset)
+{
+	enum cb_err ret = CB_ERR;
+
+	union fast_spi_dma_control control = {fast_spi_read(FAST_SPI_DMA_CONTROL)};
+	union fast_spi_dma_status status = {fast_spi_read(FAST_SPI_DMA_STATUS)};
+
+	/* Verify if the DMA is locked; if so, exit. FSP-S should lock the SPI DMA prior
+	   to exiting.  */
+	if (control.fields.lock) {
+		printk(BIOS_WARNING, "Fast-SPI: DMA is locked\n");
+		goto out;
+	}
+
+	if (control.fields.start && !status.fields.complete) {
+		printk(BIOS_ERR, "Fast-SPI: DMA operation is still ongoing...\n");
+		goto out;
+	}
+
+	/* Clear any error bits in the status register. */
+	if (status.fields.error)
+		fast_spi_write(FAST_SPI_DMA_STATUS, status.data);
+
+	/* Configure the destination address for the DMA transfer. */
+	fast_spi_write(FAST_SPI_DMA_DEST_ADDRESS_HIGH, (uint32_t)((uintptr_t)buffer >> 32));
+	fast_spi_write(FAST_SPI_DMA_DEST_ADDRESS_LOW, (uint32_t)((uintptr_t)buffer));
+
+	/* Ensure the PCI command master bit is set. */
+	uint16_t pci_command = pci_read_config16(FAST_SPI_DEV, PCI_COMMAND);
+	if (!(pci_command & PCI_COMMAND_MASTER))
+		pci_write_config16(FAST_SPI_DEV, PCI_COMMAND,
+				   pci_command | PCI_COMMAND_MASTER);
+
+	/* Configure the region offset for the transfer. */
+	union fast_spi_dma_region region = {fast_spi_read(FAST_SPI_DMA_REGION)};
+	region.fields.offset_kb = offset - 1;
+	fast_spi_write(FAST_SPI_DMA_REGION, region.data);
+
+	/* Set the buffer size and start the DMA transaction. */
+	control.fields.size = size - 1;
+	control.fields.start = 1;
+	fast_spi_write(FAST_SPI_DMA_CONTROL, control.data);
+
+	printk(BIOS_DEBUG, "Fast-SPI: Reading %d blocks via DMA\n", size);
+
+	/* Initialize a stopwatch to track the timeout period. */
+	struct stopwatch timer;
+	stopwatch_init_msecs_expire(&timer, FAST_SPI_DMA_TIMEOUT_MSEC);
+
+	/* Poll for completion of the DMA operation. */
+	do {
+		udelay(FAST_SPI_DMA_DELAY_STEP_USEC);
+
+		control.data = fast_spi_read(FAST_SPI_DMA_CONTROL);
+		status.data = fast_spi_read(FAST_SPI_DMA_STATUS);
+
+		if (status.fields.complete || status.fields.error || control.fields.lock) {
+			break;
+		}
+	} while (!stopwatch_expired(&timer));
+
+	if (status.fields.error) {
+		printk(BIOS_ERR, "Fast-SPI: error(s) detected, 0x%08x\n", status.data);
+		goto out;
+	}
+
+	/* Check if the DMA has been locked since we started the DMA transaction; if it
+	   is locked, exit with an error as we cannot guarantee that the data has been
+	   loaded prior to locking. */
+	if (control.fields.lock) {
+		printk(BIOS_ERR, "Fast-SPI: DMA has been locked\n");
+		goto out;
+	}
+
+	/* Check if the operation has timed out. */
+	if (!status.fields.complete && stopwatch_expired(&timer)) {
+		printk(BIOS_ERR, "Fast-SPI: DMA operation timed out\n");
+		goto out;
+	}
+
+	printk(BIOS_DEBUG, "Fast-SPI: transfer completed in %" PRId64 " us\n",
+	       stopwatch_duration_usecs(&timer));
+
+	/* Clear the complete status. */
+	status.data = 0;
+	status.fields.complete = 1;
+	fast_spi_write(FAST_SPI_DMA_STATUS, status.data);
+
+	/* Restore PCI command if it was changed. */
+	if (!(pci_command & PCI_COMMAND_MASTER))
+		pci_write_config16(FAST_SPI_DEV, PCI_COMMAND, pci_command);
+
+	ret = CB_SUCCESS;
+
+out:
+	return ret;
+}
+
+static enum cb_err fast_spi_dma_mmap_readat(const struct region_device *rd, void *b,
+					    size_t offset, size_t size, ssize_t *transferred)
+{
+	ssize_t count = mmap_ops->readat(rd, b, offset, size);
+	if (count < 0) {
+		printk(BIOS_ERR, "Fast-SPI: Failed to read %zu bytes", size);
+		return CB_ERR;
+	}
+	*transferred += count;
+	if (count != size) {
+		printk(BIOS_ERR, "Fast-SPI: Partial read detected %zu/%zu bytes",
+		       count, size);
+		return CB_ERR;
+	}
+
+	return CB_SUCCESS;
+}
+
+/*
+ * Perform DMA transfer from SPI flash to a buffer.
+ *
+ * This function is responsible for transferring data blocks from SPI flash memory to a
+ * specified buffer using DMA. It handles alignment of memory addresses, calculates the
+ * correct offset and block count, performs the DMA transfer, and falls back to
+ * memory-mapped operations if DMA transfer fails. Additionally, it ensures that leading
+ * and trailing bytes around the DMA blocks are correctly read and transferred.
+ *
+ * Address transformation:
+ *
+ * The address needs to be transformed from a memory map address into a DMA
+ * address. Consider the following diagram illustrating SPINOR addressing with a 32 MB
+ * SPI flash as an example:
+ *
+ * - On the left is memory addressing
+ * - On the right is DMA addressing
+ *
+ *      BIOS end (32M) --->   +--------------+  |  <- DMA start (0)
+ *                         ^  |              |  |
+ *                         |  |              |  |
+ *      offset ----------> |  |  <address>   |  |  <- bios end - offset
+ *                         |  |              |  |
+ *                         |  |              |  |
+ *                         |  |              |  |
+ *                         |  |              |  |
+ *                         |  |              |  |
+ *      BIOS start (9M) -> |  +--------------+  v  <- DMA end (32 - 9 = 23M)
+ *                         |  | DESC + other |
+ *      bottom (0M) -----> |  +--------------+
+ *
+ * @param rd Pointer to the region device structure, representing the memory region.
+ * @param b Pointer to the destination buffer where data will be transferred.
+ * @param offset Address offset from where the transfer begins.
+ * @param size Total number of bytes to transfer.
+ *
+ * @return The total number of bytes transferred if successful, or -1 if the DMA
+ *         transfer fails and fallback to memory map operation is required.
+ */
+static ssize_t fast_spi_dma_transfer(const struct region_device *rd, void *b,
+				     size_t offset, size_t size)
+{
+	/* Calculate aligned offset and flash offset for DMA transfer. */
+	uint32_t aligned_offset = ALIGN_UP(offset, FAST_SPI_DMA_BLOCK_ALIGN);
+	uint32_t flash_offset = (bios_top - aligned_offset) / FAST_SPI_DMA_BLOCK_ALIGN;
+	ssize_t early_bytes = aligned_offset - offset;
+	uint32_t block_count = (size - early_bytes) / FAST_SPI_DMA_BLOCK_ALIGN;
+
+	/* Perform DMA transfer. */
+	thread_mutex_lock(&fast_spi_dma_mutex);
+	enum cb_err ret = fast_spi_do_dma_transfer(b, block_count, flash_offset);
+	thread_mutex_unlock(&fast_spi_dma_mutex);
+	if (ret != CB_SUCCESS) {
+		printk(BIOS_ERR, "Fast-SPI: DMA transfer failed, falling back to memory map operation\n");
+		return -1;
+	}
+
+	/* Handle bytes preceding DMA blocks. */
+	ssize_t transferred = block_count * FAST_SPI_DMA_BLOCK_ALIGN;
+	if (early_bytes) {
+		memmove((char *)b + early_bytes, b, transferred);
+		ret = fast_spi_dma_mmap_readat(rd, b, offset, early_bytes, &transferred);
+		if (ret != CB_SUCCESS) {
+			printk(BIOS_ERR, "Fast-SPI: Failed to read leading DMA block bytes");
+			return -1;
+		}
+	}
+
+	/* Handle bytes following DMA blocks. */
+	size_t remaining = size - transferred;
+	if (remaining) {
+		ret = fast_spi_dma_mmap_readat(rd, (char *)b + transferred,
+					       offset + transferred, remaining, &transferred);
+		if (ret != CB_SUCCESS) {
+			printk(BIOS_ERR, "Fast-SPI: Failed to read the remaining bytes");
+			return transferred;
+		}
+	}
+	return transferred;
+}
+
+/*
+ * Perform a read operation using DMA if applicable.
+ *
+ * This function attempts to perform a read operation using DMA for the specified region
+ * device if the size and alignment conditions are met. If the conditions are not met or
+ * if the DMA operation fails, it falls back to using the memory-mapped read operation.
+ *
+ * @param rd Pointer to the region device structure, representing the memory region.
+ * @param b Pointer to the destination buffer where data will be read.
+ * @param offset Memory map address offset from where the read begins.
+ * @param size Total number of bytes to read.
+ *
+ * @return The total number of bytes read if successful, or the result of the
+ *         fallback memory-mapped read operation.
+ */
+static ssize_t fast_spi_dma_readat(const struct region_device *rd, void *b,
+				   size_t offset, size_t size)
+{
+	/* Check if the size is greater than or equal to the DMA block alignment and if
+	   the destination buffer is aligned accordingly. */
+	if (size >= FAST_SPI_DMA_BLOCK_ALIGN &&
+	    IS_ALIGNED((uintptr_t)b, FAST_SPI_DMA_BLOCK_ALIGN)) {
+		ssize_t ret = fast_spi_dma_transfer(rd, b, offset, size);
+		if (ret != -1)
+			return ret;
+	}
+
+	return mmap_ops->readat(rd, b, offset, size);
+}
+
+/*
+ * Check if Fast SPI DMA is supported by the current device.
+ *
+ * This function determines whether Fast SPI DMA operations are supported by the current
+ * hardware configuration. It performs a one-time initialization to check the PCI vendor
+ * ID and the Fast SPI DMA control register. If the vendor ID is invalid or the control
+ * register does not indicate support for the BIOS region, the function returns false.
+ * Otherwise, it returns true.
+ *
+ * @return True if Fast SPI DMA is supported; false otherwise.
+ */
+bool fast_spi_dma_is_supported(void)
+{
+	static bool initialized, supported;
+
+	if (initialized)
+		return supported;
+	initialized = true;
+
+	if (pci_read_config32(FAST_SPI_DEV, PCI_VENDOR_ID) == 0xffffffff) {
+		printk(BIOS_ERR, "Fast-SPI: DMA is not supported\n");
+		return false;
+	}
+
+	union fast_spi_dma_control control = {fast_spi_read(FAST_SPI_DMA_CONTROL)};
+	supported = control.data != 0xffffffff &&
+		control.fields.flash_region == REGION_BIOS;
+	return supported;
+}
+
+/*
+ * Install custom DMA operations for SPI flash memory access.
+ *
+ * This function sets up a specialized set of operations to access SPI flash memory
+ * regions using DMA transfers. The new operation set is derived from the original
+ * one. Only the original readat() callback is replaced by a DMA-specific version. The
+ * original operations are kept available for fallback use. The function is meant to run
+ * only once, ensuring the proper installation of the custom operations.
+ *
+ * @param mmap_xlate_rdev Pointer to the xlate_region_device structure, which contains
+ *                        information about the memory-mapped regions and operations.
+ */
+void spi_flash_dma_install_ops(struct xlate_region_device *mmap_xlate_rdev)
+{
+	static struct region_device_ops fast_spi_dma_rdev_ro_ops;
+
+	/* Check if the operations have already been installed. */
+	if (mmap_xlate_rdev->rdev.ops == &fast_spi_dma_rdev_ro_ops)
+		return;
+
+	/* Calculate the top boundary of the BIOS region within the SPI flash. */
+	for (size_t i = 0; i < mmap_xlate_rdev->window_count; i++) {
+		uint32_t begin = mmap_xlate_rdev->window_arr[i].sub_region.offset;
+		uint32_t end = begin + mmap_xlate_rdev->window_arr[i].sub_region.size;
+		if (bios_top < end)
+			bios_top = end;
+	}
+
+	/* Store the original region device operations for fallback purposes. */
+	mmap_ops = mmap_xlate_rdev->rdev.ops;
+
+	/* Copy the original operations and replace the readat() callback with DMA-based
+	   readat(). */
+	memcpy(&fast_spi_dma_rdev_ro_ops, mmap_xlate_rdev->rdev.ops,
+	       sizeof(fast_spi_dma_rdev_ro_ops));
+	fast_spi_dma_rdev_ro_ops.readat = fast_spi_dma_readat;
+	mmap_xlate_rdev->rdev.ops = &fast_spi_dma_rdev_ro_ops;
+}
diff --git a/src/soc/intel/common/block/fast_spi/fast_spi_dma.h b/src/soc/intel/common/block/fast_spi/fast_spi_dma.h
new file mode 100644
index 0000000000..3bb71ccbdc
--- /dev/null
+++ b/src/soc/intel/common/block/fast_spi/fast_spi_dma.h
@@ -0,0 +1,42 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef SOC_INTEL_COMMON_BLOCK_FAST_SPI_DMA_H
+#define SOC_INTEL_COMMON_BLOCK_FAST_SPI_DMA_H
+
+#include <commonlib/region.h>
+
+#if CONFIG(FAST_SPI_DMA) && ENV_RAMSTAGE
+/*
+ * Check if Fast SPI DMA is supported by the current device.
+ *
+ * This function determines whether Fast SPI DMA operations are supported by the current
+ * hardware configuration. It performs a one-time initialization to check the PCI vendor
+ * ID and the Fast SPI DMA control register. If the vendor ID is invalid or the control
+ * register does not indicate support for the BIOS region, the function returns false.
+ * Otherwise, it returns true.
+ *
+ * @return True if Fast SPI DMA is supported; false otherwise.
+ */
+bool fast_spi_dma_is_supported(void);
+#else
+static inline bool fast_spi_dma_is_supported(void)
+{
+	return false;
+}
+#endif
+
+/*
+ * Install custom DMA operations for SPI flash memory access.
+ *
+ * This function sets up a specialized set of operations to access SPI flash memory
+ * regions using DMA transfers. The new operation set is derived from the original
+ * one. Only the original readat() callback is replaced by a DMA-specific version. The
+ * original operations are kept available for fallback use. The function is meant to run
+ * only once, ensuring the proper installation of the custom operations.
+ *
+ * @param mmap_xlate_rdev Pointer to the xlate_region_device structure, which contains
+ *                        information about the memory-mapped regions and operations.
+ */
+void spi_flash_dma_install_ops(struct xlate_region_device *mmap_xlate_rdev);
+
+#endif /* SOC_INTEL_COMMON_BLOCK_FAST_SPI_DMA_H */
diff --git a/src/soc/intel/common/block/fast_spi/mmap_boot.c b/src/soc/intel/common/block/fast_spi/mmap_boot.c
index 2315c44bbd..af0a026b01 100644
--- a/src/soc/intel/common/block/fast_spi/mmap_boot.c
+++ b/src/soc/intel/common/block/fast_spi/mmap_boot.c
@@ -9,6 +9,7 @@
 #include <boot_device.h>
 #include <commonlib/region.h>
 #include <console/console.h>
+#include <fast_spi_dma.h>
 #include <fmap.h>
 #include <intelblocks/fast_spi.h>
 #include <spi_flash.h>
@@ -143,6 +144,9 @@ const struct region_device *boot_device_ro(void)
 {
 	bios_mmap_init();
 
+	if (fast_spi_dma_is_supported())
+		spi_flash_dma_install_ops(&real_dev);
+
 	return &real_dev.rdev;
 }
 

From ce5a1e8a5113277493d2d9b770784e3bc96d426e Mon Sep 17 00:00:00 2001
From: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Date: Wed, 9 Jul 2025 16:12:08 +0800
Subject: [PATCH 1557/3886] mb/google/brox: Create caboc variant

Create the caboc variant of the brox reference board by copying
the template files to a new directory named for the variant.

BUG=b:420796212
TEST=util/abuild/abuild -p none -t google/brox -x -a
make sure the build includes GOOGLE_CABOC.

Change-Id: I424933574873defe5289fbe7309270583cb8a49e
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88379
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/google/brox/Kconfig             |  15 +
 src/mainboard/google/brox/Kconfig.name        |   3 +
 .../google/brox/variants/caboc/Makefile.mk    |  11 +
 .../google/brox/variants/caboc/data.vbt       | Bin 0 -> 8704 bytes
 .../google/brox/variants/caboc/fw_config.c    |  78 ++++
 .../google/brox/variants/caboc/gpio.c         | 188 ++++++++
 .../brox/variants/caboc/include/variant/ec.h  |   8 +
 .../variants/caboc/include/variant/gpio.h     |  14 +
 .../variants/caboc/include/variant/hda_verb.h | 123 ++++++
 .../google/brox/variants/caboc/memory.c       | 106 +++++
 .../brox/variants/caboc/memory/Makefile.mk    |  10 +
 .../caboc/memory/dram_id.generated.txt        |  14 +
 .../variants/caboc/memory/mem_parts_used.txt  |   8 +
 .../brox/variants/caboc/overridetree.cb       | 403 ++++++++++++++++++
 .../google/brox/variants/caboc/ramstage.c     |  43 ++
 .../google/brox/variants/caboc/variant.c      |  25 ++
 16 files changed, 1049 insertions(+)
 create mode 100644 src/mainboard/google/brox/variants/caboc/Makefile.mk
 create mode 100644 src/mainboard/google/brox/variants/caboc/data.vbt
 create mode 100644 src/mainboard/google/brox/variants/caboc/fw_config.c
 create mode 100644 src/mainboard/google/brox/variants/caboc/gpio.c
 create mode 100644 src/mainboard/google/brox/variants/caboc/include/variant/ec.h
 create mode 100644 src/mainboard/google/brox/variants/caboc/include/variant/gpio.h
 create mode 100644 src/mainboard/google/brox/variants/caboc/include/variant/hda_verb.h
 create mode 100644 src/mainboard/google/brox/variants/caboc/memory.c
 create mode 100644 src/mainboard/google/brox/variants/caboc/memory/Makefile.mk
 create mode 100644 src/mainboard/google/brox/variants/caboc/memory/dram_id.generated.txt
 create mode 100644 src/mainboard/google/brox/variants/caboc/memory/mem_parts_used.txt
 create mode 100644 src/mainboard/google/brox/variants/caboc/overridetree.cb
 create mode 100644 src/mainboard/google/brox/variants/caboc/ramstage.c
 create mode 100644 src/mainboard/google/brox/variants/caboc/variant.c

diff --git a/src/mainboard/google/brox/Kconfig b/src/mainboard/google/brox/Kconfig
index 9a22731a94..c37ccacb21 100644
--- a/src/mainboard/google/brox/Kconfig
+++ b/src/mainboard/google/brox/Kconfig
@@ -95,6 +95,18 @@ config BOARD_GOOGLE_JUBILANT
 	select MAINBOARD_HAS_GOOGLE_STRAUSS_KEYBOARD
 	select USE_UNIFIED_AP_FIRMWARE_FOR_UFS_AND_NON_UFS
 
+config BOARD_GOOGLE_CABOC
+	select BOARD_GOOGLE_BASEBOARD_BROX
+	select CHROMEOS_WIFI_SAR if CHROMEOS
+	select DRIVERS_WWAN_FM350GL
+	select HAVE_PCIE_WWAN
+	select HAVE_WWAN_POWER_SEQUENCE
+	select MAINBOARD_HAS_GOOGLE_STRAUSS_KEYBOARD
+	select RT8168_GEN_ACPI_POWER_RESOURCE
+	select RT8168_GET_MAC_FROM_VPD
+	select RT8168_SET_LED_MODE
+	select USE_UNIFIED_AP_FIRMWARE_FOR_UFS_AND_NON_UFS
+
 if BOARD_GOOGLE_BROX_COMMON
 
 config BASEBOARD_DIR
@@ -125,6 +137,7 @@ config PL4_LIMIT_FOR_CRITICAL_BAT_BOOT
 	int
 	default 9 if BOARD_GOOGLE_BROX
 	default 9 if BOARD_GOOGLE_BROX_RTK_EC
+	default 14 if BOARD_GOOGLE_CABOC
 	default 14 if BOARD_GOOGLE_JUBILANT
 	default 40 if BOARD_GOOGLE_LOTSO
 	help
@@ -163,6 +176,7 @@ config MAINBOARD_PART_NUMBER
 	default "Brox_Ec_Ish" if BOARD_GOOGLE_BROX_EC_ISH
 	default "Brox_Ti_Pdc" if BOARD_GOOGLE_BROX_TI_PDC
 	default "Brox_Rtk_Ec" if BOARD_GOOGLE_BROX_RTK_EC
+	default "Caboc" if BOARD_GOOGLE_CABOC
 	default "Greenbayupoc" if BOARD_GOOGLE_GREENBAYUPOC
 	default "Jubilant" if BOARD_GOOGLE_JUBILANT
 	default "Lotso" if BOARD_GOOGLE_LOTSO
@@ -173,6 +187,7 @@ config VARIANT_DIR
 		BOARD_GOOGLE_BROX_EC_ISH || \
 		BOARD_GOOGLE_BROX_TI_PDC || \
 		BOARD_GOOGLE_BROX_RTK_EC
+	default "caboc" if BOARD_GOOGLE_CABOC
 	default "lotso" if BOARD_GOOGLE_LOTSO
 	default "greenbayupoc" if BOARD_GOOGLE_GREENBAYUPOC
 	default "jubilant" if BOARD_GOOGLE_JUBILANT
diff --git a/src/mainboard/google/brox/Kconfig.name b/src/mainboard/google/brox/Kconfig.name
index 7820878bd2..2d67ec094d 100644
--- a/src/mainboard/google/brox/Kconfig.name
+++ b/src/mainboard/google/brox/Kconfig.name
@@ -14,6 +14,9 @@ config BOARD_GOOGLE_BROX_EC_ISH
 config BOARD_GOOGLE_BROX_TI_PDC
 	bool "->  Brox TI PDC"
 
+config BOARD_GOOGLE_CABOC
+	bool "->  Caboc"
+
 config BOARD_GOOGLE_GREENBAYUPOC
 	bool "->  Greenbayupoc"
 
diff --git a/src/mainboard/google/brox/variants/caboc/Makefile.mk b/src/mainboard/google/brox/variants/caboc/Makefile.mk
new file mode 100644
index 0000000000..06ae480be1
--- /dev/null
+++ b/src/mainboard/google/brox/variants/caboc/Makefile.mk
@@ -0,0 +1,11 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
+bootblock-y += gpio.c
+
+romstage-y += gpio.c
+romstage-y += memory.c
+romstage-$(CONFIG_FW_CONFIG) += variant.c
+ramstage-$(CONFIG_FW_CONFIG) += fw_config.c
+ramstage-$(CONFIG_FW_CONFIG) += variant.c
+ramstage-y += gpio.c
+ramstage-y += ramstage.c
diff --git a/src/mainboard/google/brox/variants/caboc/data.vbt b/src/mainboard/google/brox/variants/caboc/data.vbt
new file mode 100644
index 0000000000000000000000000000000000000000..716d09f557dab5fec2978a41ed2c332c3d7db3fe
GIT binary patch
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literal 0
HcmV?d00001

diff --git a/src/mainboard/google/brox/variants/caboc/fw_config.c b/src/mainboard/google/brox/variants/caboc/fw_config.c
new file mode 100644
index 0000000000..0f77546624
--- /dev/null
+++ b/src/mainboard/google/brox/variants/caboc/fw_config.c
@@ -0,0 +1,78 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <bootstate.h>
+#include <baseboard/gpio.h>
+#include <baseboard/variants.h>
+#include <console/console.h>
+#include <fw_config.h>
+
+static const struct pad_config fp_disable_pads[] = {
+	/* GPP_D8 : PCH_FP_BOOT0 */
+	PAD_NC(GPP_D8, NONE),
+	/* GPP_D9 : FP_RST_ODL */
+	PAD_NC(GPP_D9, NONE),
+	/* GPP_D11 : [] ==> EN_FP_PWR */
+	PAD_NC(GPP_D11, NONE),
+	/* GPP_E4 : FP GSPI INT */
+	PAD_NC(GPP_E4, NONE),
+	/* GPP_F11 : FP GSPI CLK */
+	PAD_NC(GPP_F11, NONE),
+	/* GPP_F12 : FP GSPI DO */
+	PAD_NC(GPP_F12, NONE),
+	/* GPP_F13 : FP GSPI DI */
+	PAD_NC(GPP_F13, NONE),
+	/* GPP_F16 : FP GSPI CS */
+	PAD_NC(GPP_F16, NONE),
+};
+
+static const struct pad_config lte_disable_pads[] = {
+	/* GPP_A17 :WWAN_TRANSMIT_OFF */
+	PAD_NC(GPP_A17, NONE),
+	/* GPP_A21 : WWAN_ASPM_EXIT */
+	PAD_NC(GPP_A21, NONE),
+	/* GPP_D4 : WWAN_GPS_XMIT_L */
+	PAD_NC(GPP_D4, NONE),
+	/* GPP_D15 : WWAN_CONFIG_3 */
+	PAD_NC(GPP_D15, NONE),
+	/* GPP_D16 : WWAN_CONFIG_2 */
+	PAD_NC(GPP_D16, NONE),
+	/* GPP_D19 : WWAN_FWUPD# */
+	PAD_NC(GPP_D19, NONE),
+	/* GPP_E5 : WWAN_WAKE# */
+	PAD_NC(GPP_E5, NONE),
+	/* GPP_F19 : PCIE_CLKREQ_WWAN */
+	PAD_NC(GPP_F19, NONE),
+	/* GPP_F21 : WWAN_OFF# */
+	PAD_NC(GPP_F21, NONE),
+};
+
+static const struct pad_config nvme_disable_pads[] = {
+	/* GPP_F9 : SSD_PERST_L */
+	PAD_NC(GPP_F9, NONE),
+	/* GPP_D5 : SSD_CLKREQ_ODL */
+	PAD_NC(GPP_D5, NONE),
+};
+
+static void fw_config_handle(void *unused)
+{
+	if (!fw_config_is_provisioned()) {
+		printk(BIOS_WARNING, "FW_CONFIG is unprovisioned. Skip disable device's pads.\n");
+		return;
+	}
+
+	if (fw_config_probe(FW_CONFIG(FP, FP_ABSENT))) {
+		printk(BIOS_INFO, "Disable Fingerprint GPIOs by fw_config.\n");
+		gpio_configure_pads(fp_disable_pads, ARRAY_SIZE(fp_disable_pads));
+	}
+
+	if (fw_config_probe(FW_CONFIG(DB_USB, DB_1A))) {
+		printk(BIOS_INFO, "Disable LTE-related GPIO pins by fw_config.\n");
+		gpio_configure_pads(lte_disable_pads, ARRAY_SIZE(lte_disable_pads));
+	}
+
+	if (!fw_config_probe(FW_CONFIG(STORAGE, STORAGE_NVME))) {
+		printk(BIOS_INFO, "Disable NVMe GPIO pins by fw_config.\n");
+		gpio_configure_pads(nvme_disable_pads, ARRAY_SIZE(nvme_disable_pads));
+	}
+}
+BOOT_STATE_INIT_ENTRY(BS_DEV_ENABLE, BS_ON_ENTRY, fw_config_handle, NULL);
diff --git a/src/mainboard/google/brox/variants/caboc/gpio.c b/src/mainboard/google/brox/variants/caboc/gpio.c
new file mode 100644
index 0000000000..e2127d0ceb
--- /dev/null
+++ b/src/mainboard/google/brox/variants/caboc/gpio.c
@@ -0,0 +1,188 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <baseboard/gpio.h>
+#include <baseboard/variants.h>
+#include <commonlib/helpers.h>
+#include <soc/gpio.h>
+#include <vendorcode/google/chromeos/chromeos.h>
+
+/* Pad configuration in ramstage */
+static const struct pad_config override_gpio_table[] = {
+	/* GPP_A12 : [NF1: SATAXPCIE1 NF2: SATAGP1 NF4: SRCCLKREQ9B# NF6: USB_C_GPP_A12] ==> KBL_DET(reserve) */
+	PAD_NC(GPP_A12, NONE),
+	/* GPP_A14 : [NF1: USB_OC1# NF2: DDSP_HPD3 NF4: DISP_MISC3 NF6: USB_C_GPP_A14] ==> NC */
+	PAD_NC(GPP_A14, NONE),
+	/* GPP_A15 : [NF1: USB_OC2# NF2: DDSP_HPD4 NF4: DISP_MISC4 NF6: USB_C_GPP_A15] ==> NC */
+	PAD_NC(GPP_A15, NONE),
+	/* GPP_A17 : [NF4: DISP_MISCC NF6: USB_C_GPP_A17] ==> WWAN_TRANSMIT_OFF(WAN_RF_DISABLE_ODL) */
+	PAD_CFG_GPO(GPP_A17, 1, DEEP),
+	/* GPP_A21 : [NF1: DDPC_CTRLCLK NF6: USB_C_GPP_A21] ==> WWAN_ASPM_EXIT(WWAN_PERST_L) */
+	PAD_CFG_GPO(GPP_A21, 1, DEEP),
+
+	/* GPP_D4 : [NF1: IMGCLKOUT0 NF2: BK4 NF5: SBK4 NF6: USB_C_GPP_D4] ==> WWAN_GPS_XMIT_OFF */
+	PAD_CFG_GPO(GPP_D4, 0, DEEP),
+	/* GPP_D5 : SRCCLKREQ0_L ==> SSD_CLKREQ_ODL */
+	PAD_CFG_NF(GPP_D5, NONE, DEEP, NF1),
+	/* GPP_D7 : SRCCLKREQ2_L ==> PCIE_CLKREQ_LAN */
+	PAD_CFG_NF(GPP_D7, NONE, DEEP, NF1),
+	/* GPP_D8 : [NF1: SRCCLKREQ3# NF6: USB_C_GPP_D8] ==> PCH_FP_BOOT0 */
+	PAD_CFG_GPO_LOCK(GPP_D8, 0, LOCK_CONFIG),
+	/* GPP_D9 : [NF1: ISH_SPI_CS# NF2: DDP3_CTRLCLK NF4: TBT_LSX2_TXD NF5: BSSB_LS2_RX NF6: USB_C_GPP_D9 NF7: GSPI2_CS0#] ==> FP_RST_ODL */
+	PAD_CFG_GPO_LOCK(GPP_D9, 0, LOCK_CONFIG),
+	/* GPP_D10 : [NF1: ISH_SPI_CLK NF2: DDP3_CTRLDATA NF4: TBT_LSX2_RXD NF5: BSSB_LS2_TX NF6: USB_C_GPP_D10 NF7: GSPI2_CLK] ==> USB_C2_LSX_RX_STRAP(NC) */
+	PAD_NC(GPP_D10, NONE),
+	/* GPP_D11 : [] ==> EN_FP_POWER*/
+	PAD_CFG_GPO_LOCK(GPP_D11, 0, LOCK_CONFIG),
+	/* GPP_D15 : ISH_UART0_RTS_L/I2C7B_SDA ==> WWAN_CONFIG_3 */
+	PAD_CFG_GPI_LOCK(GPP_D15, NONE, LOCK_CONFIG),
+	/* GPP_D16 : ISH_UART0_CTS_L/I2C7B_SCL ==> WWAN_CONFIG_2 */
+	PAD_CFG_GPI_LOCK(GPP_D16, NONE, LOCK_CONFIG),
+	/* GPP_D18 : UART1_TXD/ISH_UART1_RXD ==> LANLINK_STATUS */
+	PAD_CFG_GPI(GPP_D18, NONE, DEEP),
+	/* GPP_D19 : [NF1: I2S_MCLK1_OUT NF6: USB_C_GPP_D19] ==> WWAN_FWUPD#(WWAN_RST_L) */
+	PAD_CFG_GPO(GPP_D19, 1, DEEP),
+
+	/* GPP_E4 : [NF1: DEVSLP0 NF6: USB_C_GPP_E4 NF7: SRCCLK_OE9#] ==> GSPI_FPMCU_INT_L */
+	PAD_CFG_GPI_IRQ_WAKE(GPP_E4, NONE, PWROK, LEVEL, INVERT),
+	/* GPP_E5 : [NF1: DEVSLP1 NF6: USB_C_GPP_E5 NF7: SRCCLK_OE6#] ==> WWAN_WAKE# */
+	PAD_CFG_GPI_INT(GPP_E5, NONE, PLTRST, EDGE_SINGLE),
+	/* GPP_E7 : [NF1: PROC_GP1 NF6: USB_C_GPP_E7] ==> EN_UCAM_PWR*/
+	PAD_CFG_GPO(GPP_E7, 1, DEEP),
+	/* GPP_E18 : [NF1: DDP1_CTRLCLK NF4: TBT_LSX0_TXD NF5: BSSB_LS0_RX NF6: USB_C_GPP_E18] ==> NC */
+	PAD_NC(GPP_E18, NONE),
+	/* GPP_E19 : [NF1: DDP1_CTRLDATA NF4: TBT_LSX0_RXD NF5: BSSB_LS0_TX NF6: USB_C_GPP_E19] ==> USB_C0_LSX_RX_STRAP(NC) */
+	PAD_NC(GPP_E19, NONE),
+
+	/* GPP_F11 : [NF3: THC1_SPI2_CLK NF4: GSPI1_CLK NF6: USB_C_GPP_F11] ==> GSPI_PCH_CLK_FPMCU_R */
+	PAD_CFG_NF_LOCK(GPP_F11, NONE, NF4, LOCK_CONFIG),
+	/* GPP_F12 : [NF1: GSXDOUT NF3: THC1_SPI2_IO0 NF4: GSPI1_MOSI NF5: I2C1A_SCL NF6: USB_C_GPP_F12] ==> GSPI_PCH_DO_FPMCU_DI_R */
+	PAD_CFG_NF_LOCK(GPP_F12, NONE, NF4, LOCK_CONFIG),
+	/* GPP_F13 : [NF1: GSXSLOAD NF3: THC1_SPI2_IO1 NF4: GSPI1_MISIO NF5: I2C1A_SDA NF6: USB_C_GPP_F13] ==> GSPI_PCH_DI_FPMCU_DO */
+	PAD_CFG_NF_LOCK(GPP_F13, NONE, NF4, LOCK_CONFIG),
+	/* GPP_F15 : [NF1: GSXSRESET# NF3: THC1_SPI2_IO3 NF6: USB_C_GPP_F15] ==> NC */
+	PAD_NC(GPP_F15, NONE),
+	/* GPP_F16 : [NF1: GSXCLK NF3: THC1_SPI2_CS# NF4: GSPI1_CS0# NF6: USB_C_GPP_F16] ==> GSPI_PCH_CS_FPMCU_R_L */
+	PAD_CFG_NF_LOCK(GPP_F16, NONE, NF4, LOCK_CONFIG),
+	/* GPP_F19 : SRCCLKREQ6 ==> PCIE_CLKREQ_WWAN */
+	PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1),
+	/* F21 : [NF1: Reserved NF6: USB_C_GPP_F21] ==> WWAN_OFF#(WWAN_FCPO_L)*/
+	PAD_CFG_GPO(GPP_F21, 1, DEEP),
+};
+
+/* Early pad configuration in bootblock */
+static const struct pad_config early_gpio_table[] = {
+
+	/* F21 : [NF1: Reserved NF6: USB_C_GPP_F21] ==> WWAN_OFF#(WWAN_FCPO_L) */
+	PAD_CFG_GPO(GPP_F21, 0, DEEP),
+	/* GPP_A21 : [NF1: DDPC_CTRLCLK NF6: USB_C_GPP_A21] ==> WWAN_ASPM_EXIT(WWAN_PERST_L) */
+	PAD_CFG_GPO(GPP_A21, 0, DEEP),
+	/* GPP_D19 : [NF1: I2S_MCLK1_OUT NF6: USB_C_GPP_D19] ==> WWAM_FWUPD#(WWAN_RST_L) */
+	PAD_CFG_GPO(GPP_D19, 0, DEEP),
+
+	/*
+	 * FP_RST_ODL comes out of reset as hi-z and does not have an external pull-down.
+	 * To ensure proper power sequencing for the FPMCU device, reset signal is driven low
+	 * early on in bootblock, followed by enabling of power. Reset signal is deasserted
+	 * later on in ramstage. Since reset signal is asserted in bootblock, it results in
+	 * FPMCU not working after a S3 resume. This is a known issue.
+	 */
+	/* GPP_D9 : [NF1: ISH_SPI_CS# NF2: DDP3_CTRLCLK NF4: TBT_LSX2_TXD NF5: BSSB_LS2_RX NF6: USB_C_GPP_D9 NF7: GSPI2_CS0#] ==> FP_RST_ODL */
+	PAD_CFG_GPO(GPP_D9, 0, DEEP),
+	/* GPP_D11  : [] ==> EN_FP_PWR */
+	PAD_CFG_GPO(GPP_D11, 1, DEEP),
+
+	/* GPP_E2  : THC0_SPI1_IO3 ==> GSC_PCH_INT_ODL */
+	PAD_CFG_GPI_APIC(GPP_E2, NONE, PLTRST, LEVEL, INVERT),
+	/* GPP_E8 : GPP_E8 ==> PCH_WP_OD */
+	PAD_CFG_GPI_LOCK(GPP_E8, NONE, LOCK_CONFIG),
+	/* GPP_F9 : [NF1: BOOTMPC NF6: USB_C_GPP_F9] ==> SSD_PERST_L */
+	PAD_CFG_GPO(GPP_F9, 0, DEEP),
+	/* GPP_H8 : [NF1: I2C4_SDA NF2: CNV_MFUART2_RXD NF6: USB_C_GPP_H8] ==> PCH_I2C_GSC_SDA */
+	PAD_CFG_NF(GPP_H8, NONE, DEEP, NF1),
+	/* GPP_H9 : [NF1: I2C4_SCL NF2: CNV_MFUART2_TXD] ==> PCH_I2C_GSC_SCL */
+	PAD_CFG_NF(GPP_H9, NONE, DEEP, NF1),
+	/* H10 : UART0_RXD ==> UART_PCH_RX_DBG_TX */
+	PAD_CFG_NF(GPP_H10, NONE, PLTRST, NF2),
+	/* H11 : UART0_TXD ==> UART_PCH_TX_DBG_RX */
+	PAD_CFG_NF(GPP_H11, NONE, PLTRST, NF2),
+	/* GPP_S0 : SNDW0_CLL/I2S1_SCLK ==> MEM_CH_SEL */
+	PAD_CFG_GPI(GPP_S0, NONE, DEEP),
+
+	/* CPU PCIe vGPIO for RP2 */
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_32, NONE, PLTRST, NF1),
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_33, NONE, PLTRST, NF1),
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_34, NONE, PLTRST, NF1),
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_35, NONE, PLTRST, NF1),
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_36, NONE, PLTRST, NF1),
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_37, NONE, PLTRST, NF1),
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_38, NONE, PLTRST, NF1),
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_39, NONE, PLTRST, NF1),
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_40, NONE, PLTRST, NF1),
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_41, NONE, PLTRST, NF1),
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_42, NONE, PLTRST, NF1),
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_43, NONE, PLTRST, NF1),
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_44, NONE, PLTRST, NF1),
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_45, NONE, PLTRST, NF1),
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_46, NONE, PLTRST, NF1),
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_47, NONE, PLTRST, NF1),
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_72, NONE, PLTRST, NF1),
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_73, NONE, PLTRST, NF1),
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_74, NONE, PLTRST, NF1),
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_75, NONE, PLTRST, NF1),
+};
+
+static const struct pad_config romstage_gpio_table[] = {
+	/* GPP_D9 : [NF1: ISH_SPI_CS# NF2: DDP3_CTRLCLK NF4: TBT_LSX2_TXD NF5: BSSB_LS2_RX NF6: USB_C_GPP_D9 NF7: GSPI2_CS0#] ==> FP_RST_ODL */
+	PAD_CFG_GPO(GPP_D9, 0, DEEP),
+	/* GPP_D11 : [] ==> EN_FP_PWR */
+	PAD_CFG_GPO(GPP_D11, 0, DEEP),
+
+	/* F21 : [NF1: Reserved NF6: USB_C_GPP_F21] ==> WWAN_OFF#(WWAN_FCPO_L) */
+	PAD_CFG_GPO(GPP_F21, 1, DEEP),
+	/* GPP_A21 : [NF1: DDPC_CTRLCLK NF6: USB_C_GPP_A21] ==> WWAN_ASPM_EXIT(WWAN_PERST_L) */
+	PAD_CFG_GPO(GPP_A21, 0, DEEP),
+	/* GPP_D19 : [NF1: I2S_MCLK1_OUT NF6: USB_C_GPP_D19] ==> WWAM_FWUPD#(WWAN_RST_L) */
+	PAD_CFG_GPO(GPP_D19, 0, DEEP),
+
+	/* GPP_E10 : THC0_SPI1_CS_L/GSPI0_CS0_L ==> MEM_STRAP_3 */
+	PAD_CFG_GPI(GPP_E10, NONE, PLTRST),
+	/* GPP_E12 : THC0_SPI1_IO1/I2C0A_SDA/GSPI0_MISO ==> MEM_STRAP_1 */
+	PAD_CFG_GPI(GPP_E12, NONE, PLTRST),
+	/* GPP_E13 : THC0_SPI1_IO0/I2C0A_SCL/GSPI0_MOSI ==> MEM_STRAP_2 */
+	PAD_CFG_GPI(GPP_E13, NONE, PLTRST),
+	/* GPP_E15 : SRCCLK_OE8_L ==> MEM_STRAP_0 */
+	PAD_CFG_GPI(GPP_E15, NONE, PLTRST),
+	/* GPP_F7 : [NF6: USB_C_GPP_F7] ==> EN_PP3300_TCHSCR */
+	PAD_CFG_GPO(GPP_F7, 1, PLTRST),
+	/* GPP_F9 : [NF1: BOOTMPC NF6: USB_C_GPP_F9] ==> SSD_PERST_L */
+	PAD_CFG_GPO(GPP_F9, 1, DEEP),
+	/* GPP_F17 : [NF3: THC1_SPI2_RST# NF6: USB_C_GPP_F17] ==> TCHSCR_RST_L */
+	PAD_CFG_GPO(GPP_F17, 0, DEEP),
+	/* GPP_S0 : SNDW0_CLL/I2S1_SCLK ==> MEM_CH_SEL */
+	PAD_CFG_GPI(GPP_S0, NONE, DEEP),
+};
+
+const struct pad_config *variant_gpio_override_table(size_t *num)
+{
+	*num = ARRAY_SIZE(override_gpio_table);
+	return override_gpio_table;
+}
+
+const struct pad_config *variant_early_gpio_table(size_t *num)
+{
+	*num = ARRAY_SIZE(early_gpio_table);
+	return early_gpio_table;
+}
+
+const struct pad_config *variant_romstage_gpio_table(size_t *num)
+{
+	*num = ARRAY_SIZE(romstage_gpio_table);
+	return romstage_gpio_table;
+}
+
+static const struct cros_gpio cros_gpios[] = {
+	CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME),
+	CROS_GPIO_WP_AH(GPIO_PCH_WP, CROS_GPIO_DEVICE_NAME),
+};
+
+DECLARE_CROS_GPIOS(cros_gpios);
diff --git a/src/mainboard/google/brox/variants/caboc/include/variant/ec.h b/src/mainboard/google/brox/variants/caboc/include/variant/ec.h
new file mode 100644
index 0000000000..4fc0622f15
--- /dev/null
+++ b/src/mainboard/google/brox/variants/caboc/include/variant/ec.h
@@ -0,0 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#ifndef MAINBOARD_EC_H
+#define MAINBOARD_EC_H
+
+#include <baseboard/ec.h>
+
+#endif /* MAINBOARD_GPIO_H */
diff --git a/src/mainboard/google/brox/variants/caboc/include/variant/gpio.h b/src/mainboard/google/brox/variants/caboc/include/variant/gpio.h
new file mode 100644
index 0000000000..8fbc069648
--- /dev/null
+++ b/src/mainboard/google/brox/variants/caboc/include/variant/gpio.h
@@ -0,0 +1,14 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#ifndef __MAINBOARD_GPIO_H__
+#define __MAINBOARD_GPIO_H__
+
+#include <baseboard/gpio.h>
+
+#define T1_OFF_MS	16
+#define T2_OFF_MS	2
+#define WWAN_FCPO	GPP_F21
+#define WWAN_RST	GPP_D19
+#define WWAN_PERST	GPP_A21
+
+#endif /* __MAINBOARD_GPIO_H__ */
diff --git a/src/mainboard/google/brox/variants/caboc/include/variant/hda_verb.h b/src/mainboard/google/brox/variants/caboc/include/variant/hda_verb.h
new file mode 100644
index 0000000000..9435ad7d46
--- /dev/null
+++ b/src/mainboard/google/brox/variants/caboc/include/variant/hda_verb.h
@@ -0,0 +1,123 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef MAINBOARD_HDA_VERB_H
+#define MAINBOARD_HDA_VERB_H
+
+#include <device/azalia_device.h>
+
+const u32 cim_verb_data[] = {
+	/* coreboot specific header */
+	0x10ec0236,	// Codec Vendor / Device ID: Realtek ALC236
+	0x103C8C60,	// Subsystem ID
+	0x00000017,	// Number of jacks (NID entries)
+
+	AZALIA_RESET(0x1),
+	/* NID 0x01, HDA Codec Subsystem ID Verb table */
+	AZALIA_SUBVENDOR(0, 0x103C8C60),
+
+	/* Pin Widget Verb Table */
+
+	/*
+	 * DMIC
+	 * Requirement is to use PCH DMIC. Hence,
+	 * commented out codec's Internal DMIC.
+	 * AZALIA_PIN_CFG(0, 0x12, 0x90A60130),
+	 * AZALIA_PIN_CFG(0, 0x13, 0x40000000),
+	 */
+
+	/* Pin widget 0x14 - Front (Port-D) */
+	AZALIA_PIN_CFG(0, 0x14, 0x90170110),
+	/* Pin widget 0x18 - NPC */
+	AZALIA_PIN_CFG(0, 0x18, 0x411111F0),
+	/* Pin widget 0x19 - MIC2 (Port-F) */
+	AZALIA_PIN_CFG(0, 0x19, 0x03A11020),
+	/* Pin widget 0x1A - LINE1 (Port-C) */
+	AZALIA_PIN_CFG(0, 0x1a, 0x411111F0),
+	/* Pin widget 0x1B - NPC */
+	AZALIA_PIN_CFG(0, 0x1b, 0x411111F0),
+	/* Pin widget 0x1D - BEEP-IN */
+	AZALIA_PIN_CFG(0, 0x1d, 0x40600001),
+	/* Pin widget 0x1E - NPC */
+	AZALIA_PIN_CFG(0, 0x1e, 0x411111F0),
+	/* Pin widget 0x21 - HP1-OUT (Port-I) */
+	AZALIA_PIN_CFG(0, 0x21, 0x03211040),
+
+	/*
+	 * Widget node 0x20 - 1
+	 */
+	0x0205003C,
+	0x02040354,
+	0x0205003C,
+	0x02040314,
+	/*
+	 * Widget node 0x20 - 2
+	 * Set JD2 pull high
+	 */
+	0x0205001B,
+	0x02040A4B,
+	0x0205000B,
+	0x02047778,
+	/*
+	 * Widget node 0x20 - 3
+	 */
+	0x02050046,
+	0x02040004,
+	0x05750003,
+	0x057409A3,
+	/* disable EQ first */
+	0x05350000,
+	0x0534201A,
+	/* Left Channel */
+	0x0535001d,
+	0x05340800,
+	0x0535001e,
+	0x05340800,
+	0x05350003,
+	0x05341F7B,
+	0x05350004,
+	0x05340000,
+	/* Right Channel */
+	0x05450000,
+	0x05442000,
+	0x0545001d,
+	0x05440800,
+	0x0545001e,
+	0x05440800,
+	0x05450003,
+	0x05441F7B,
+	0x05450004,
+	0x05440000,
+	/* enable EQ */
+	0x05350000,
+	0x0534E01A,
+	/* 1.8W/4ohm */
+	0x02050038,
+	0x02047901,
+	/* AGC Enable */
+	0x0205004C,
+	0x0204465C,
+	0x02050016,
+	0x02044E50,
+	0x02050020,
+	0x020451FF,
+	/* Headphone Pop */
+	0x05750007,
+	0x057412B2,
+};
+
+const u32 pc_beep_verbs[] = {
+	/* Dos beep path - 1 */
+	0x02050036,
+	0x02047151,
+	0x02050010,
+	0x02040020,
+	/* Dos beep path - 2 */
+	0x0143B000,
+	0x01470740,
+	0x01470C02,
+	0x01470C02,
+};
+
+AZALIA_ARRAY_SIZES;
+
+#endif
diff --git a/src/mainboard/google/brox/variants/caboc/memory.c b/src/mainboard/google/brox/variants/caboc/memory.c
new file mode 100644
index 0000000000..24d625b157
--- /dev/null
+++ b/src/mainboard/google/brox/variants/caboc/memory.c
@@ -0,0 +1,106 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <baseboard/gpio.h>
+#include <baseboard/variants.h>
+#include <gpio.h>
+#include <soc/romstage.h>
+
+static const struct mb_cfg baseboard_memcfg = {
+	.type = MEM_TYPE_LP5X,
+
+	/* Leave Rcomp unspecified to use the FSP optimized defaults */
+
+	/* DQ byte map */
+	.lpx_dq_map = {
+		.ddr0 = {
+			.dq0 = { 4,  7, 5,  6,  0,  1,  2,  3, },
+			.dq1 = { 8, 11, 9, 10, 13, 14, 15, 12, },
+		},
+		.ddr1 = {
+			.dq0 = {  1,  2,  3,  0, 6,  4, 7,  5, },
+			.dq1 = { 13, 15, 12, 14, 8, 11, 9, 10, },
+		},
+		.ddr2 = {
+			.dq0 = {  0,  3,  2,  1, 6,  5, 7,  4, },
+			.dq1 = { 14, 12, 15, 13, 8, 10, 9, 11, },
+		},
+		.ddr3 = {
+			.dq0 = {  5, 7,  4, 6,  2,  0,  1,  3, },
+			.dq1 = { 10, 9, 11, 8, 12, 15, 13, 14, },
+		},
+		.ddr4 = {
+			.dq0 = { 4,  6, 5,  7,  3,  2,  1,  0, },
+			.dq1 = { 8, 11, 9, 10, 14, 13, 15, 12, },
+		},
+		.ddr5 = {
+			.dq0 = {  2,  1,  3,  0, 6,  4, 7,  5, },
+			.dq1 = { 13, 15, 12, 14, 8, 11, 9, 10, },
+		},
+		.ddr6 = {
+			.dq0 = { 14, 12, 15, 13, 8, 11, 10, 9, },
+			.dq1 = {  1,  2,  3,  0, 5,  6,  7, 4, },
+		},
+		.ddr7 = {
+			.dq0 = { 3, 6,  2,  7,  5,  0,  1,  4, },
+			.dq1 = { 9, 8, 14, 15, 10, 12, 13, 11, },
+		},
+	},
+
+	/* DQS CPU<>DRAM map */
+	.lpx_dqs_map = {
+		.ddr0 = { .dqs0 = 0, .dqs1 = 1 },
+		.ddr1 = { .dqs0 = 0, .dqs1 = 1 },
+		.ddr2 = { .dqs0 = 0, .dqs1 = 1 },
+		.ddr3 = { .dqs0 = 0, .dqs1 = 1 },
+		.ddr4 = { .dqs0 = 0, .dqs1 = 1 },
+		.ddr5 = { .dqs0 = 0, .dqs1 = 1 },
+		.ddr6 = { .dqs0 = 1, .dqs1 = 0 },
+		.ddr7 = { .dqs0 = 0, .dqs1 = 1 }
+	},
+
+	.lp5x_config = {
+		.ccc_config = 0x99,
+	},
+
+	.LpDdrDqDqsReTraining = 1,
+
+	.ect = 1, /* Early Command Training */
+
+	.UserBd = BOARD_TYPE_ULT_ULX,
+};
+
+const struct mb_cfg *variant_memory_params(void)
+{
+	return &baseboard_memcfg;
+}
+
+int variant_memory_sku(void)
+{
+	/*
+	 * Memory configuration board straps
+	 * MEM_STRAP_0	GPP_E15
+	 * MEM_STRAP_1	GPP_E12
+	 * MEM_STRAP_2	GPP_E13
+	 * MEM_STRAP_3	GPP_E10
+	 */
+	gpio_t spd_gpios[] = {
+		GPP_E15,
+		GPP_E12,
+		GPP_E13,
+		GPP_E10,
+	};
+
+	return gpio_base2_value(spd_gpios, ARRAY_SIZE(spd_gpios));
+}
+
+bool variant_is_half_populated(void)
+{
+	/* MEM_CH_SEL GPP_S0 */
+	return gpio_get(GPP_S0);
+}
+
+void variant_get_spd_info(struct mem_spd *spd_info)
+{
+	spd_info->topo = MEM_TOPO_MEMORY_DOWN;
+	spd_info->cbfs_index = variant_memory_sku();
+}
diff --git a/src/mainboard/google/brox/variants/caboc/memory/Makefile.mk b/src/mainboard/google/brox/variants/caboc/memory/Makefile.mk
new file mode 100644
index 0000000000..5d896055e9
--- /dev/null
+++ b/src/mainboard/google/brox/variants/caboc/memory/Makefile.mk
@@ -0,0 +1,10 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+# This is an auto-generated file. Do not edit!!
+# Generated by:
+# ./util/spd_tools/bin/part_id_gen adl lp5 src/mainboard/google/brox/variants/caboc/memory src/mainboard/google/brox/variants/caboc/memory/mem_parts_used.txt
+
+SPD_SOURCES =
+SPD_SOURCES += spd/lp5/set-0/spd-1.hex      # ID = 0(0b0000)  Parts = H9JCNNNBK3MLYR-N6E
+SPD_SOURCES += spd/lp5/set-0/spd-9.hex      # ID = 1(0b0001)  Parts = K3KL6L60GM-MGCT
+SPD_SOURCES += spd/lp5/set-0/spd-11.hex      # ID = 2(0b0010)  Parts = MT62F1G32D2DS-023 WT:C, K3KL8L80EM-MGCU, H58G56CK8BX146
+SPD_SOURCES += spd/lp5/set-0/spd-10.hex      # ID = 3(0b0011)  Parts = MT62F2G32D4DS-023 WT:C, K3KL9L90EM-MGCU, H58G66CK8BX147
diff --git a/src/mainboard/google/brox/variants/caboc/memory/dram_id.generated.txt b/src/mainboard/google/brox/variants/caboc/memory/dram_id.generated.txt
new file mode 100644
index 0000000000..fdd88ea78d
--- /dev/null
+++ b/src/mainboard/google/brox/variants/caboc/memory/dram_id.generated.txt
@@ -0,0 +1,14 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+# This is an auto-generated file. Do not edit!!
+# Generated by:
+# ./util/spd_tools/bin/part_id_gen adl lp5 src/mainboard/google/brox/variants/caboc/memory src/mainboard/google/brox/variants/caboc/memory/mem_parts_used.txt
+
+DRAM Part Name                 ID to assign
+H9JCNNNBK3MLYR-N6E             0 (0000)
+K3KL6L60GM-MGCT                1 (0001)
+MT62F1G32D2DS-023 WT:C         2 (0010)
+K3KL8L80EM-MGCU                2 (0010)
+H58G56CK8BX146                 2 (0010)
+MT62F2G32D4DS-023 WT:C         3 (0011)
+K3KL9L90EM-MGCU                3 (0011)
+H58G66CK8BX147                 3 (0011)
diff --git a/src/mainboard/google/brox/variants/caboc/memory/mem_parts_used.txt b/src/mainboard/google/brox/variants/caboc/memory/mem_parts_used.txt
new file mode 100644
index 0000000000..91bbc50cbc
--- /dev/null
+++ b/src/mainboard/google/brox/variants/caboc/memory/mem_parts_used.txt
@@ -0,0 +1,8 @@
+H9JCNNNBK3MLYR-N6E
+K3KL6L60GM-MGCT
+MT62F1G32D2DS-023 WT:C
+K3KL8L80EM-MGCU
+H58G56CK8BX146
+MT62F2G32D4DS-023 WT:C
+K3KL9L90EM-MGCU
+H58G66CK8BX147
diff --git a/src/mainboard/google/brox/variants/caboc/overridetree.cb b/src/mainboard/google/brox/variants/caboc/overridetree.cb
new file mode 100644
index 0000000000..1270765c9a
--- /dev/null
+++ b/src/mainboard/google/brox/variants/caboc/overridetree.cb
@@ -0,0 +1,403 @@
+fw_config
+	field DB_USB 0 1
+		option DB_1A			0
+		option DB_1A_LTE		1
+	end
+	field WIFI_BT 2 2
+		option WIFI_BT_CNVI		0
+		option WIFI_BT_PCIE		1
+	end
+	field STORAGE 3 4
+		option STORAGE_UFS		1
+		option STORAGE_NVME		2
+	end
+	field KB_BL 5 5
+		option KB_BL_ABSENT		0
+		option KB_BL_PRESENT		1
+	end
+	field FP 7 7
+		option FP_ABSENT		0
+		option FP_PRESENT		1
+	end
+	field PANEL 8 10
+		option TOUCH_UNKNOWN		0
+		option TOUCH_ELAN_HID_I2C	1
+		option TOUCH_G2TOUCH_HID_I2C	2
+	end
+end
+
+chip soc/intel/alderlake
+	register "usb2_ports[0]" = "USB2_PORT_MID(OC_SKIP)"	# Camera
+	register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC_SKIP)"	# USB2_C0
+	register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)"	# Type-A Port A2(DB)
+	register "usb2_ports[3]" = "USB2_PORT_TYPE_C(OC_SKIP)"	# USB2_C2
+	register "usb2_ports[4]" = "USB2_PORT_EMPTY"		# Disable USB2 Port
+	register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)"	# Type-A Port A0(MLB)
+	register "usb2_ports[6]" = "USB2_PORT_EMPTY"		# Disable USB2 Port
+	register "usb2_ports[7]" = "USB2_PORT_EMPTY"		# Disable USB2 Port
+	register "usb2_ports[8]" = "USB2_PORT_MID(OC_SKIP)"	# WWAN
+	register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)"	# M.2 Bluetooth
+
+	register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)"	# Type-A port A2(DB)
+	register "usb3_ports[1]" = "USB3_PORT_EMPTY"		# Disable USB3 Port
+	register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)"	# Type A port A0(MLB)
+	register "usb3_ports[3]" = "USB3_PORT_EMPTY"		# Disable USB3 Port
+
+	register "platform_pmax" = "208"
+
+	device domain 0 on
+		device ref dtt on
+			chip drivers/intel/dptf
+				## sensor information
+				register "options.tsr[0].desc" = ""DRAM_SOC""
+				register "options.tsr[1].desc" = ""CPU-Inlet""
+				register "options.tsr[2].desc" = ""Charger""
+				register "options.tsr[3].desc" = ""5V regulator""
+
+				## Passive Policy
+				register "policies.passive" = "{
+						[0] = DPTF_PASSIVE(CPU,		CPU,		97, 5000),
+						[1] = DPTF_PASSIVE(CPU,		TEMP_SENSOR_0,	85, 5000),
+						[2] = DPTF_PASSIVE(CPU,		TEMP_SENSOR_1,	85, 5000),
+						[3] = DPTF_PASSIVE(CHARGER,	TEMP_SENSOR_2,	85, 5000),
+						[4] = DPTF_PASSIVE(CPU,		TEMP_SENSOR_3,	85, 5000),
+				}"
+
+				## Critical Policy
+				register "policies.critical" = "{
+						[0] = DPTF_CRITICAL(CPU,               105, SHUTDOWN),
+						[1] = DPTF_CRITICAL(TEMP_SENSOR_0,      95, SHUTDOWN),
+						[2] = DPTF_CRITICAL(TEMP_SENSOR_1,      95, SHUTDOWN),
+						[3] = DPTF_CRITICAL(TEMP_SENSOR_2,      95, SHUTDOWN),
+						[4] = DPTF_CRITICAL(TEMP_SENSOR_3,      95, SHUTDOWN),
+				}"
+
+				register "controls.power_limits" = "{
+						.pl1 = {
+							.min_power = 15000,
+							.max_power = 15000,
+							.time_window_min = 28 * MSECS_PER_SEC,
+							.time_window_max = 32 * MSECS_PER_SEC,
+							.granularity = 200,
+							},
+						.pl2 = {
+							.min_power = 55000,
+							.max_power = 55000,
+							.time_window_min = 28 * MSECS_PER_SEC,
+							.time_window_max = 32 * MSECS_PER_SEC,
+							.granularity = 1000,
+							}
+				}"
+
+				## Charger Performance Control (Control, mA)
+				register "controls.charger_perf" = "{
+						[0] = { 255, 1700 },
+						[1] = {  24, 1500 },
+						[2] = {  16, 1000 },
+						[3] = {   8,  500 }
+				}"
+
+				device generic 0 alias dptf_policy on end
+			end
+		end # DTT
+		device ref igpu on
+			chip drivers/gfx/generic
+				register "device_count" = "6"
+				# DDIA for eDP
+				register "device[0].name" = ""LCD0""
+				register "device[0].type" = "panel"
+				# DDIB for HDMI
+				# If HDMI is not enumerated in the kernel, then no GFX device should be added for DDIB
+				register "device[1].name" = ""DD01""
+				# TCP0 (DP-1) for port C0
+				register "device[2].name" = ""DD02""
+				register "device[2].use_pld" = "true"
+				register "device[2].pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(1, 1))"
+				# TCP1 (DP-2) is unused for any ports but still enumerated in the kernel, so GFX device is added for TCP1
+				register "device[3].name" = ""DD03""
+				# TCP2 (DP-3) for port C2
+				register "device[4].name" = ""DD04""
+				register "device[4].use_pld" = "true"
+				register "device[4].pld" = "ACPI_PLD_TYPE_C(LEFT, RIGHT, ACPI_PLD_GROUP(2, 1))"
+				# TCP3 (DP-4) is unused for any ports but still enumerated in the kernel, so GFX device is added for TCP3
+				register "device[5].name" = ""DD05""
+				device generic 0 on end
+			end
+		end # Integrated Graphics Device
+		device ref pch_espi on
+			chip ec/google/chromeec
+				device pnp 0c09.0 on end
+			end
+		end
+		device ref pmc hidden
+			chip drivers/intel/pmc_mux
+				device generic 0 on
+					chip drivers/intel/pmc_mux/conn
+						use usb2_port2 as usb2_port
+						use tcss_usb3_port1 as usb3_port
+						device generic 0 on end
+					end
+					chip drivers/intel/pmc_mux/conn
+						use usb2_port4 as usb2_port
+						use tcss_usb3_port3 as usb3_port
+						device generic 1 on end
+					end
+				end
+			end
+		end
+		device ref tcss_xhci on
+			chip drivers/usb/acpi
+				device ref tcss_root_hub on
+					chip drivers/usb/acpi
+						register "desc" = ""USB3 Type-C Port C0 (MLB)""
+						register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
+						register "use_custom_pld" = "true"
+						register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(1, 1))"
+						device ref tcss_usb3_port1 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB3 Type-C Port C2 (MLB)""
+						register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
+						register "use_custom_pld" = "true"
+						register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, RIGHT, ACPI_PLD_GROUP(2, 1))"
+						device ref tcss_usb3_port3 on end
+					end
+				end
+			end
+		end
+		device ref xhci on
+			chip drivers/usb/acpi
+				device ref xhci_root_hub on
+					chip drivers/usb/acpi
+						register "desc" = ""USB2 Camera""
+						register "type" = "UPC_TYPE_INTERNAL"
+						register "has_power_resource" = "true"
+						register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E7)"
+						device ref usb2_port1 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB2 Type-C Port C0 (MLB)""
+						register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
+						register "use_custom_pld" = "true"
+						register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(1, 1))"
+						device ref usb2_port2 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB2 Type-A Port A2 (DB)""
+						register "type" = "UPC_TYPE_A"
+						register "use_custom_pld" = "true"
+						register "custom_pld" = "ACPI_PLD_TYPE_A(RIGHT, LEFT, ACPI_PLD_GROUP(4, 1))"
+						device ref usb2_port3 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB2 Type-C Port C2 (MLB)""
+						register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
+						register "use_custom_pld" = "true"
+						register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, RIGHT, ACPI_PLD_GROUP(2, 1))"
+						device ref usb2_port4 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB2 Type-A Port A0 (MLB)""
+						register "type" = "UPC_TYPE_A"
+						register "use_custom_pld" = "true"
+						register "custom_pld" = "ACPI_PLD_TYPE_A(LEFT, LEFT, ACPI_PLD_GROUP(3, 1))"
+						device ref usb2_port6 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB2 WWAN""
+						register "type" = "UPC_TYPE_INTERNAL"
+						device ref usb2_port9 on
+							probe DB_USB DB_1A_LTE
+						end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB2 Bluetooth""
+						register "type" = "UPC_TYPE_INTERNAL"
+						register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A13)"
+						device ref usb2_port10 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB3 Type-A Port A2 (DB)""
+						register "type" = "UPC_TYPE_USB3_A"
+						register "use_custom_pld" = "true"
+						register "custom_pld" = "ACPI_PLD_TYPE_A(RIGHT, LEFT, ACPI_PLD_GROUP(4, 1))"
+						device ref usb3_port1 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB3 Type-A Port A0 (MLB)""
+						register "type" = "UPC_TYPE_USB3_A"
+						register "use_custom_pld" = "true"
+						register "custom_pld" = "ACPI_PLD_TYPE_A(LEFT, LEFT, ACPI_PLD_GROUP(3, 1))"
+						device ref usb3_port3 on end
+					end
+				end
+			end
+		end
+		device ref pcie4_1 on
+			# Enable CPU PCIE RP 3 using CLK 0
+			register "cpu_pcie_rp[CPU_RP(3)]" = "{
+				.clk_req = 0,
+				.clk_src = 0,
+				.flags = PCIE_RP_LTR | PCIE_RP_AER,
+				.pcie_rp_aspm = ASPM_L1,
+			}"
+			probe STORAGE STORAGE_NVME
+			probe unprovisioned
+		end
+		device ref pcie_rp4 on
+			# Enable WWAN PCIE 4 using clk 6
+			register "pch_pcie_rp[PCH_RP(4)]" = "{
+				.clk_src = 6,
+				.clk_req = 6,
+				.flags = PCIE_RP_LTR | PCIE_RP_AER,
+			}"
+			chip soc/intel/common/block/pcie/rtd3
+				register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A21)"
+				register "reset_off_delay_ms" = "20"
+				register "srcclk_pin" = "6"
+				register "ext_pm_support" = "ACPI_PCIE_RP_EMIT_ALL"
+				register "skip_on_off_support" = "true"
+				register "use_rp_mutex" = "true"
+				device generic 0 alias rp4_rtd3 on
+					probe DB_USB DB_1A_LTE
+				end
+			end
+			chip drivers/wwan/fm
+				register "fcpo_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_F21)"
+				register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D19)"
+				register "perst_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A21)"
+				register "wake_gpio" = "ACPI_GPIO_IRQ_EDGE_LOW(GPP_E5)"
+				register "add_acpi_dma_property" = "true"
+				use rp4_rtd3 as rtd3dev
+				device generic 0 alias rp4_wwan on
+					probe DB_USB DB_1A_LTE
+				end
+			end
+			probe DB_USB DB_1A_LTE
+		end
+		device ref pcie_rp7 on
+			register "pch_pcie_rp[PCH_RP(7)]" = "{
+				.clk_src = 1,
+				.clk_req = 1,
+				.flags = PCIE_RP_LTR | PCIE_RP_AER,
+			}"
+			chip drivers/wifi/generic
+				register "wake" = "GPE0_DW0_03" #GPP_B3
+				register "add_acpi_dma_property" = "true"
+				use usb2_port10 as bluetooth_companion
+				device pci 00.0 on
+					probe WIFI_BT WIFI_BT_PCIE
+					probe unprovisioned
+				end
+			end
+			chip soc/intel/common/block/pcie/rtd3
+				# enable_gpio is controlled by the EC with EC_EN_PP3300_WLAN
+				register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_H2)"
+				register "srcclk_pin" = "1"
+				device generic 0 on end
+			end
+			probe WIFI_BT WIFI_BT_PCIE
+			probe unprovisioned
+		end
+		device ref pcie_rp8 on
+			# Enable PCIE 8 using clk 2
+			register "pch_pcie_rp[PCH_RP(8)]" = "{
+				.clk_src = 2,
+				.clk_req = 2,
+				.flags = PCIE_RP_LTR | PCIE_RP_AER,
+			}"
+			chip drivers/net
+				register "customized_leds" = "0x05af"
+				register "device_index" = "0"
+				register "enable_aspm_l1_2" = "1"
+				register "add_acpi_dma_property" = "true"
+				device pci 00.0 on end
+			end
+		end     #RTL8111H Ethernet NIC
+		device ref cnvi_wifi on
+			chip drivers/wifi/generic
+				register "wake" = "GPE0_PME_B0"
+				register "add_acpi_dma_property" = "true"
+				register "enable_cnvi_ddr_rfim" = "true"
+				device generic 0 on end
+			end
+			probe WIFI_BT WIFI_BT_CNVI
+			probe unprovisioned
+		end
+		device ref ish on
+			chip drivers/intel/ish
+				register "add_acpi_dma_property" = "true"
+				device generic 0 alias ish_conf on end
+			end
+			probe STORAGE STORAGE_UFS
+			probe unprovisioned
+		end
+		device ref ufs on
+			probe STORAGE STORAGE_UFS
+			probe unprovisioned
+		end
+		device ref i2c0 on
+			chip drivers/i2c/generic
+				register "hid" = ""ELAN0000""
+				register "desc" = ""ELAN Touchpad""
+				register "irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_E3_IRQ)"
+				register "wake" = "GPE0_DW2_03" #GPP_E3
+				register "detect" = "1"
+				device i2c 15 on end
+			end
+		end #I2C0
+		device ref i2c1 on
+			chip drivers/i2c/hid
+				register "generic.hid" = ""ELAN2513""
+				register "generic.desc" = ""ELAN Touchscreen""
+				register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_F18_IRQ)"
+				register "generic.detect" = "1"
+				register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_F17)"
+				register "generic.reset_delay_ms" = "150"
+				register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_F7)"
+				register "generic.enable_delay_ms" = "6"
+				register "generic.has_power_resource" = "1"
+				register "generic.use_gpio_for_status" = "true"
+				register "hid_desc_reg_offset" = "0x01"
+				device i2c 10 on
+					probe PANEL TOUCH_ELAN_HID_I2C
+					probe unprovisioned
+				end
+			end
+			chip drivers/i2c/hid
+				register "generic.hid" = ""GTCH7503""
+				register "generic.desc" = ""G2TOUCH Touchscreen""
+				register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_F18_IRQ)"
+				register "generic.detect" = "1"
+				register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_F17)"
+				register "generic.reset_delay_ms" = "150"
+				register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_F7)"
+				register "generic.enable_delay_ms" = "6"
+				register "generic.has_power_resource" = "1"
+				register "generic.use_gpio_for_status" = "true"
+				register "hid_desc_reg_offset" = "0x01"
+				device i2c 10 on
+					probe PANEL TOUCH_G2TOUCH_HID_I2C
+				end
+			end
+		end
+		device ref gspi1 on
+			chip drivers/spi/acpi
+				register "name" = ""CRFP""
+				register "hid" = "ACPI_DT_NAMESPACE_HID"
+				register "uid" = "1"
+				register "compat_string" = ""google,cros-ec-spi""
+				register "irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_E4_IRQ)"
+				register "wake" = "GPE0_DW2_04" #GPP_E4
+				register "has_power_resource" = "true"
+				register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D9)"
+				register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D11)"
+				register "enable_delay_ms" = "3"
+				device spi 0 on
+					probe FP FP_PRESENT
+					probe unprovisioned
+				end
+			end # FPMCU
+		end
+	end
+end
diff --git a/src/mainboard/google/brox/variants/caboc/ramstage.c b/src/mainboard/google/brox/variants/caboc/ramstage.c
new file mode 100644
index 0000000000..5af6d57247
--- /dev/null
+++ b/src/mainboard/google/brox/variants/caboc/ramstage.c
@@ -0,0 +1,43 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <baseboard/variants.h>
+#include <device/pci_ids.h>
+#include <ec/google/chromeec/ec.h>
+#include <intelblocks/power_limit.h>
+
+/*
+ * SKU_ID, TDP (Watts), pl1_min (milliWatts), pl1_max (milliWatts),
+ * pl2_min (milliWatts), pl2_max (milliWatts), pl4 (milliWatts)
+ * Following values are for performance config as per document #640982
+ */
+
+const struct cpu_power_limits performance_efficient_limits[] = {
+	{
+		.mchid = PCI_DID_INTEL_RPL_P_ID_3,
+		.cpu_tdp = 15,
+		.pl1_min_power = 15000,
+		.pl1_max_power = 15000,
+		.pl2_min_power = 55000,
+		.pl2_max_power = 55000,
+		.pl4_power = 114000
+	},
+	{
+		.mchid = PCI_DID_INTEL_RPL_P_ID_4,
+		.cpu_tdp = 15,
+		.pl1_min_power = 15000,
+		.pl1_max_power = 15000,
+		.pl2_min_power = 55000,
+		.pl2_max_power = 55000,
+		.pl4_power = 114000
+	},
+};
+
+void __weak variant_devtree_update(void)
+{
+	printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__);
+
+	const struct cpu_power_limits *limits = performance_efficient_limits;
+	size_t limits_size = ARRAY_SIZE(performance_efficient_limits);
+
+	variant_update_power_limits(limits, limits_size);
+}
diff --git a/src/mainboard/google/brox/variants/caboc/variant.c b/src/mainboard/google/brox/variants/caboc/variant.c
new file mode 100644
index 0000000000..666e370008
--- /dev/null
+++ b/src/mainboard/google/brox/variants/caboc/variant.c
@@ -0,0 +1,25 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <baseboard/variants.h>
+#include <chip.h>
+#include <device/device.h>
+#include <fw_config.h>
+#include <sar.h>
+
+void variant_update_soc_chip_config(struct soc_intel_alderlake_config *config)
+{
+	if (fw_config_probe(FW_CONFIG(WIFI_BT, WIFI_BT_CNVI)) || (!fw_config_is_provisioned())) {
+		printk(BIOS_INFO, "CNVi bluetooth enabled by fw_config\n");
+		config->cnvi_bt_core = true;
+	}
+}
+
+const char *get_wifi_sar_cbfs_filename(void)
+{
+	return get_wifi_sar_fw_config_filename(FW_CONFIG_FIELD(WIFI_BT));
+}
+
+const char *variant_get_auxfw_version_file(void)
+{
+	return NULL;
+}

From 45d9973a6dfef9548cbec3c9806ef0ce4e6daa96 Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Fri, 11 Jul 2025 16:07:29 -0500
Subject: [PATCH 1558/3886] ec/lenovo/h8: Add CFR objects for existing options

Add a header with CFR objects for existing configuration options,
so that supported boards can make use of them without duplication.

TEST=build/boot lenovo/t480 w/edk2 payload

Change-Id: I198f569e69abd42071df4d5354cd2bb258749257
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88393
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/ec/lenovo/h8/cfr.h | 158 +++++++++++++++++++++++++++++++++++++++++
 1 file changed, 158 insertions(+)
 create mode 100644 src/ec/lenovo/h8/cfr.h

diff --git a/src/ec/lenovo/h8/cfr.h b/src/ec/lenovo/h8/cfr.h
new file mode 100644
index 0000000000..b410f2d449
--- /dev/null
+++ b/src/ec/lenovo/h8/cfr.h
@@ -0,0 +1,158 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+/*
+ * CFR enums and structs for Lenovo H8 EC
+ */
+
+#ifndef _LENOVO_H8_CFR_H_
+#define _LENOVO_H8_CFR_H_
+
+#include <drivers/option/cfr_frontend.h>
+#include "h8.h"
+
+/* Bluetooth */
+static const struct sm_object bluetooth = SM_DECLARE_ENUM({
+	.opt_name	= "bluetooth",
+	.ui_name	= "Bluetooth",
+	.ui_helptext	= "Enable or disable the bluetooth module",
+	.default_value	= 1,
+	.values		= (const struct sm_enum_value[]) {
+				{ "Disabled",	0	},
+				{ "Enabled",	1	},
+				SM_ENUM_VALUE_END	},
+});
+
+/* Keyboard Backlight */
+static const struct sm_object backlight = SM_DECLARE_ENUM({
+	.opt_name	= "backlight",
+	.ui_name	= "Keyboard Backlight",
+	.ui_helptext	= "Enable or disable the keyboard backlight",
+	.default_value	= 0,
+	.values		= (const struct sm_enum_value[]) {
+				{ "Disabled",	0	},
+				{ "Enabled",	1	},
+				SM_ENUM_VALUE_END	},
+});
+
+/* USB Always-On */
+static const struct sm_object usb_always_on = SM_DECLARE_ENUM({
+	.opt_name	= "usb_always_on",
+	.ui_name	= "USB Always-on",
+	.ui_helptext	= "Always keep USB ports powered",
+	.default_value	= UAO_OFF,
+	.values		= (const struct sm_enum_value[]) {
+				{ "Disabled",		UAO_OFF			},
+				{ "AC only",		UAO_AC_ONLY		},
+				{ "AC and Battery",	UAO_AC_AND_BATTERY	},
+				SM_ENUM_VALUE_END				},
+});
+
+/* Ultrawideband */
+static const struct sm_object uwb = SM_DECLARE_ENUM({
+	.opt_name	= "uwb",
+	.ui_name	= "Ultrawideband",
+	.ui_helptext	= "TBD",
+	.default_value	= 1,
+	.values		= (const struct sm_enum_value[]) {
+				{ "Disabled",	0	},
+				{ "Enabled",	1	},
+				SM_ENUM_VALUE_END	},
+});
+
+/* Volume control */
+static const struct sm_object volume = SM_DECLARE_ENUM({
+	.opt_name	= "volume",
+	.ui_name	= "Volume",
+	.ui_helptext	= "TBD",
+	.default_value	= 0,
+	.values		= (const struct sm_enum_value[]) {
+				{ "Disabled",	0	},
+				{ "Enabled",	1	},
+				SM_ENUM_VALUE_END	},
+});
+
+/* WLAN */
+static const struct sm_object wlan = SM_DECLARE_ENUM({
+	.opt_name	= "wlan",
+	.ui_name	= "WLAN",
+	.ui_helptext	= "Enable or disable the WLAN module",
+	.default_value	= 1,
+	.values		= (const struct sm_enum_value[]) {
+				{ "Disabled",	0	},
+				{ "Enabled",	1	},
+				SM_ENUM_VALUE_END	},
+});
+
+/* WWAN */
+static const struct sm_object wwan = SM_DECLARE_ENUM({
+	.opt_name	= "wwan",
+	.ui_name	= "WWAN",
+	.ui_helptext	= "Enable or disable the WWAN module",
+	.default_value	= 1,
+	.values		= (const struct sm_enum_value[]) {
+				{ "Disabled",	0	},
+				{ "Enabled",	1	},
+				SM_ENUM_VALUE_END	},
+});
+
+/* Power Management Beeps */
+static const struct sm_object pm_beeps = SM_DECLARE_ENUM({
+	.opt_name	= "power_management_beeps",
+	.ui_name	= "Power Management Beeps",
+	.ui_helptext	= "Enable or disable power management beeps",
+	.default_value	= 1,
+	.values		= (const struct sm_enum_value[]) {
+				{ "Disabled",	0	},
+				{ "Enabled",	1	},
+				SM_ENUM_VALUE_END	},
+});
+
+/* Low Battery Beep */
+static const struct sm_object battery_beep = SM_DECLARE_ENUM({
+	.opt_name	= "low_battery_beep",
+	.ui_name	= "Low Battery Beep",
+	.ui_helptext	= "Enable or disable low battery beep",
+	.default_value	= 1,
+	.values		= (const struct sm_enum_value[]) {
+				{ "Disabled",	0	},
+				{ "Enabled",	1	},
+				SM_ENUM_VALUE_END	},
+});
+
+/* Fn-CTRL Swap */
+static const struct sm_object fn_ctrl_swap = SM_DECLARE_ENUM({
+	.opt_name	= "fn_ctrl_swap",
+	.ui_name	= "Swap Fn and CTRL",
+	.ui_helptext	= "Swap the left Fn and CTRL keys",
+	.default_value	= CONFIG(H8_FN_CTRL_SWAP),
+	.values		= (const struct sm_enum_value[]) {
+				{ "Disabled",	0	},
+				{ "Enabled",	1	},
+				SM_ENUM_VALUE_END	},
+});
+
+/* Fn Lock */
+static const struct sm_object sticky_fn = SM_DECLARE_ENUM({
+	.opt_name	= "sticky_fn",
+	.ui_name	= "Sticky Fn key",
+	.ui_helptext	= "Function key acts as a toggle",
+	.default_value	= 0,
+	.values		= (const struct sm_enum_value[]) {
+				{ "Disabled",	0	},
+				{ "Enabled",	1	},
+				SM_ENUM_VALUE_END	},
+});
+
+/* Function keys primary */
+static const struct sm_object f1_to_f12_as_primary = SM_DECLARE_ENUM({
+	.opt_name	= "f1_to_f12_as_primary",
+	.ui_name	= "Primary Function keys",
+	.ui_helptext	= "F1-F12 default act as function keys",
+	.default_value	= 1,
+	.values		= (const struct sm_enum_value[]) {
+				{ "Disabled",	0	},
+				{ "Enabled",	1	},
+				SM_ENUM_VALUE_END	},
+});
+
+#endif /* _LENOVO_H8_CFR_H_ */

From d9169ef6171ba7ddd8ccc5fc275cee77801bcef0 Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Fri, 11 Jul 2025 16:09:08 -0500
Subject: [PATCH 1559/3886] ec/lenovo/pmh7: Add CFR objects for existing
 options

Add a header with CFR objects for existing configuration options,
so that supported boards can make use of them without duplication.

TEST=build/boot lenovo/t480 w/edk2 payload

Change-Id: I8f5c335a8b9d1697b77b3c3542bd96f98583dbf6
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88394
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
---
 src/ec/lenovo/pmh7/cfr.h | 36 ++++++++++++++++++++++++++++++++++++
 1 file changed, 36 insertions(+)
 create mode 100644 src/ec/lenovo/pmh7/cfr.h

diff --git a/src/ec/lenovo/pmh7/cfr.h b/src/ec/lenovo/pmh7/cfr.h
new file mode 100644
index 0000000000..329fb56a3e
--- /dev/null
+++ b/src/ec/lenovo/pmh7/cfr.h
@@ -0,0 +1,36 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+/*
+ * CFR enums and structs for Lenovo PMH7 EC
+ */
+
+#ifndef _LENOVO_PMH7_CFR_H_
+#define _LENOVO_PMH7_CFR_H_
+
+#include <drivers/option/cfr_frontend.h>
+
+/* Touchpad */
+static const struct sm_object touchpad = SM_DECLARE_ENUM({
+	.opt_name	= "touchpad",
+	.ui_name	= "Touchpad",
+	.ui_helptext	= "Enable or disable the touchpad",
+	.default_value	= 1,
+	.values		= (const struct sm_enum_value[]) {
+				{ "Disabled",	0	},
+				{ "Enabled",	1	},
+				SM_ENUM_VALUE_END	},
+});
+
+/* Trackpoint */
+static const struct sm_object trackpoint = SM_DECLARE_ENUM({
+	.opt_name	= "trackpoint",
+	.ui_name	= "Trackpoint",
+	.ui_helptext	= "Enable or disable the trackpoint",
+	.default_value	= 1,
+	.values		= (const struct sm_enum_value[]) {
+				{ "Disabled",	0	},
+				{ "Enabled",	1	},
+				SM_ENUM_VALUE_END	},
+});
+
+#endif /* _LENOVO_PMH7_CFR_H_ */

From bc116b8797d081a61c5a76db0a6e045171cfbafe Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Sat, 12 Jul 2025 14:48:33 -0500
Subject: [PATCH 1560/3886] ec/lenovo/h8: Replace chip regs for BT/WWAN detect
 with Kconfig options

Using Kconfig options instead of chip registers allows for newer boards
which do not implement BT/WWAN detection to not compile in the GPIO-
related parts, which are only valid for older (pre-FSP) platforms.

Change-Id: Ibfe738adfc75abfaf078c6b7ff5472a1424909f5
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88414
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/ec/lenovo/h8/Kconfig                                  | 8 ++++++++
 src/ec/lenovo/h8/bluetooth.c                              | 2 +-
 src/ec/lenovo/h8/chip.h                                   | 2 --
 src/ec/lenovo/h8/wwan.c                                   | 2 +-
 src/mainboard/lenovo/t400/Kconfig                         | 1 +
 src/mainboard/lenovo/t400/devicetree.cb                   | 1 -
 src/mainboard/lenovo/t420/Kconfig                         | 1 +
 src/mainboard/lenovo/t420/devicetree.cb                   | 1 -
 src/mainboard/lenovo/t420s/Kconfig                        | 1 +
 src/mainboard/lenovo/t420s/devicetree.cb                  | 1 -
 src/mainboard/lenovo/t430/Kconfig                         | 2 ++
 src/mainboard/lenovo/t430/devicetree.cb                   | 2 --
 src/mainboard/lenovo/t430s/Kconfig                        | 1 +
 src/mainboard/lenovo/t430s/variants/t430s/overridetree.cb | 1 -
 src/mainboard/lenovo/t430s/variants/t431s/overridetree.cb | 2 --
 src/mainboard/lenovo/t520/Kconfig                         | 2 ++
 src/mainboard/lenovo/t520/devicetree.cb                   | 1 -
 src/mainboard/lenovo/t520/variants/t520/overridetree.cb   | 1 -
 src/mainboard/lenovo/t530/Kconfig                         | 2 ++
 src/mainboard/lenovo/t530/devicetree.cb                   | 1 -
 src/mainboard/lenovo/t530/variants/t530/overridetree.cb   | 1 -
 src/mainboard/lenovo/t60/Kconfig                          | 1 +
 src/mainboard/lenovo/t60/variants/t60/overridetree.cb     | 1 -
 src/mainboard/lenovo/x1_carbon_gen1/Kconfig               | 2 ++
 src/mainboard/lenovo/x1_carbon_gen1/devicetree.cb         | 2 --
 src/mainboard/lenovo/x200/Kconfig                         | 1 +
 src/mainboard/lenovo/x200/devicetree.cb                   | 1 -
 src/mainboard/lenovo/x201/Kconfig                         | 1 +
 src/mainboard/lenovo/x201/devicetree.cb                   | 1 -
 src/mainboard/lenovo/x220/Kconfig                         | 1 +
 src/mainboard/lenovo/x220/devicetree.cb                   | 2 --
 src/mainboard/lenovo/x230/Kconfig                         | 1 +
 src/mainboard/lenovo/x230/devicetree.cb                   | 2 --
 src/mainboard/lenovo/x230/variants/x230s/overridetree.cb  | 2 --
 src/mainboard/lenovo/x60/Kconfig                          | 1 +
 src/mainboard/lenovo/x60/devicetree.cb                    | 1 -
 36 files changed, 28 insertions(+), 28 deletions(-)

diff --git a/src/ec/lenovo/h8/Kconfig b/src/ec/lenovo/h8/Kconfig
index b15657d21a..fbdca5f94a 100644
--- a/src/ec/lenovo/h8/Kconfig
+++ b/src/ec/lenovo/h8/Kconfig
@@ -65,4 +65,12 @@ config THINKPADEC_HKEY_EISAID
 	  Motherboards of newer thinkpad models can override the default to match
 	  vendor drivers and quirks.
 
+config H8_HAS_BDC_GPIO_DETECTION
+	bool
+	default n
+
+config H8_HAS_WWAN_GPIO_DETECTION
+	bool
+	default n
+
 endif # EC_LENOVO_H8
diff --git a/src/ec/lenovo/h8/bluetooth.c b/src/ec/lenovo/h8/bluetooth.c
index 16fc8dce39..aa5fc5814f 100644
--- a/src/ec/lenovo/h8/bluetooth.c
+++ b/src/ec/lenovo/h8/bluetooth.c
@@ -28,7 +28,7 @@ bool h8_has_bdc(const struct device *dev)
 {
 	struct ec_lenovo_h8_config *conf = dev->chip_info;
 
-	if (!conf->has_bdc_detection) {
+	if (!CONFIG(H8_HAS_BDC_GPIO_DETECTION)) {
 		printk(BIOS_INFO, "H8: BDC detection not implemented. "
 				  "Assuming BDC installed\n");
 		return true;
diff --git a/src/ec/lenovo/h8/chip.h b/src/ec/lenovo/h8/chip.h
index 440c2fc4dd..0e4b11e753 100644
--- a/src/ec/lenovo/h8/chip.h
+++ b/src/ec/lenovo/h8/chip.h
@@ -32,8 +32,6 @@ struct ec_lenovo_h8_config {
 	u8 has_keyboard_backlight;
 	u8 has_power_management_beeps;
 	u8 has_uwb;
-	u8 has_bdc_detection;
-	u8 has_wwan_detection;
 
 	u8 bdc_gpio_num;
 	u8 bdc_gpio_lvl;
diff --git a/src/ec/lenovo/h8/wwan.c b/src/ec/lenovo/h8/wwan.c
index 685886fcce..3eea9541ec 100644
--- a/src/ec/lenovo/h8/wwan.c
+++ b/src/ec/lenovo/h8/wwan.c
@@ -26,7 +26,7 @@ bool h8_has_wwan(const struct device *dev)
 {
 	struct ec_lenovo_h8_config *conf = dev->chip_info;
 
-	if (!conf->has_wwan_detection) {
+	if (!CONFIG(H8_HAS_WWAN_GPIO_DETECTION)) {
 		printk(BIOS_INFO, "H8: WWAN detection not implemented. "
 				  "Assuming WWAN installed\n");
 		return true;
diff --git a/src/mainboard/lenovo/t400/Kconfig b/src/mainboard/lenovo/t400/Kconfig
index 5afcde8b81..85e580e30e 100644
--- a/src/mainboard/lenovo/t400/Kconfig
+++ b/src/mainboard/lenovo/t400/Kconfig
@@ -12,6 +12,7 @@ config BOARD_SPECIFIC_OPTIONS
 	select EC_LENOVO_PMH7
 	select EC_LENOVO_H8
 	select H8_HAS_BAT_THRESHOLDS_IMPL
+	select H8_HAS_BDC_GPIO_DETECTION if !BOARD_LENOVO_R500
 	select BOARD_ROMSIZE_KB_8192 if !BOARD_LENOVO_R500
 	select BOARD_ROMSIZE_KB_4096 if BOARD_LENOVO_R500
 	select HAVE_ACPI_TABLES
diff --git a/src/mainboard/lenovo/t400/devicetree.cb b/src/mainboard/lenovo/t400/devicetree.cb
index 259c3e1b21..9e056772e9 100644
--- a/src/mainboard/lenovo/t400/devicetree.cb
+++ b/src/mainboard/lenovo/t400/devicetree.cb
@@ -155,7 +155,6 @@ chip northbridge/intel/gm45
 					register "eventc_enable" = "0xff"
 					register "eventd_enable" = "0xff"
 
-					register "has_bdc_detection" = "1"
 					register "bdc_gpio_num" = "48"
 					register "bdc_gpio_lvl" = "0"
 				end
diff --git a/src/mainboard/lenovo/t420/Kconfig b/src/mainboard/lenovo/t420/Kconfig
index e2137a3379..cbf07efab7 100644
--- a/src/mainboard/lenovo/t420/Kconfig
+++ b/src/mainboard/lenovo/t420/Kconfig
@@ -11,6 +11,7 @@ config BOARD_SPECIFIC_OPTIONS
 	select EC_LENOVO_PMH7
 	select EC_LENOVO_H8
 	select H8_HAS_BAT_THRESHOLDS_IMPL
+	select H8_HAS_BDC_GPIO_DETECTION
 	select NO_UART_ON_SUPERIO
 	select BOARD_ROMSIZE_KB_8192
 	select HAVE_ACPI_TABLES
diff --git a/src/mainboard/lenovo/t420/devicetree.cb b/src/mainboard/lenovo/t420/devicetree.cb
index f5272fc701..37ac884eb3 100644
--- a/src/mainboard/lenovo/t420/devicetree.cb
+++ b/src/mainboard/lenovo/t420/devicetree.cb
@@ -149,7 +149,6 @@ chip northbridge/intel/sandybridge
 					register "eventd_enable" = "0xff"
 					register "evente_enable" = "0x0d"
 
-					register "has_bdc_detection" = "1"
 					register "bdc_gpio_num" = "54"
 					register "bdc_gpio_lvl" = "0"
 				end
diff --git a/src/mainboard/lenovo/t420s/Kconfig b/src/mainboard/lenovo/t420s/Kconfig
index 5ed1fdefe9..37b3993a1a 100644
--- a/src/mainboard/lenovo/t420s/Kconfig
+++ b/src/mainboard/lenovo/t420s/Kconfig
@@ -11,6 +11,7 @@ config BOARD_SPECIFIC_OPTIONS
 	select EC_LENOVO_PMH7
 	select GFX_GMA_PANEL_1_ON_LVDS
 	select H8_HAS_BAT_THRESHOLDS_IMPL
+	select H8_HAS_BDC_GPIO_DETECTION
 	select HAVE_ACPI_RESUME
 	select HAVE_ACPI_TABLES
 	select HAVE_CMOS_DEFAULT
diff --git a/src/mainboard/lenovo/t420s/devicetree.cb b/src/mainboard/lenovo/t420s/devicetree.cb
index 840e520fbb..335e025c72 100644
--- a/src/mainboard/lenovo/t420s/devicetree.cb
+++ b/src/mainboard/lenovo/t420s/devicetree.cb
@@ -141,7 +141,6 @@ chip northbridge/intel/sandybridge
 					register "eventd_enable" = "0xff"
 					register "evente_enable" = "0x0d"
 
-					register "has_bdc_detection" = "1"
 					register "bdc_gpio_num" = "54"
 					register "bdc_gpio_lvl" = "0"
 				end
diff --git a/src/mainboard/lenovo/t430/Kconfig b/src/mainboard/lenovo/t430/Kconfig
index e136871503..1baa94a4c8 100644
--- a/src/mainboard/lenovo/t430/Kconfig
+++ b/src/mainboard/lenovo/t430/Kconfig
@@ -12,6 +12,8 @@ config BOARD_SPECIFIC_OPTIONS
 	select EC_LENOVO_PMH7
 	select GFX_GMA_PANEL_1_ON_LVDS
 	select H8_HAS_BAT_THRESHOLDS_IMPL
+	select H8_HAS_BDC_GPIO_DETECTION
+	select H8_HAS_WWAN_GPIO_DETECTION
 	select HAVE_ACPI_RESUME
 	select HAVE_ACPI_TABLES
 	select HAVE_CMOS_DEFAULT
diff --git a/src/mainboard/lenovo/t430/devicetree.cb b/src/mainboard/lenovo/t430/devicetree.cb
index 9a0db4dd85..02a4c85344 100644
--- a/src/mainboard/lenovo/t430/devicetree.cb
+++ b/src/mainboard/lenovo/t430/devicetree.cb
@@ -118,11 +118,9 @@ chip northbridge/intel/sandybridge
 					register "eventd_enable" = "0xff"
 					register "evente_enable" = "0x0d"
 
-					register "has_bdc_detection" = "1"
 					register "bdc_gpio_num" = "54"
 					register "bdc_gpio_lvl" = "0"
 
-					register "has_wwan_detection" = "1"
 					register "wwan_gpio_num" = "70"
 					register "wwan_gpio_lvl" = "0"
 				end
diff --git a/src/mainboard/lenovo/t430s/Kconfig b/src/mainboard/lenovo/t430s/Kconfig
index 9a7a91b512..3ab5d340bb 100644
--- a/src/mainboard/lenovo/t430s/Kconfig
+++ b/src/mainboard/lenovo/t430s/Kconfig
@@ -11,6 +11,7 @@ config BOARD_SPECIFIC_OPTIONS
 	select EC_LENOVO_PMH7
 	select EC_LENOVO_H8
 	select H8_HAS_BAT_THRESHOLDS_IMPL
+	select H8_HAS_BDC_GPIO_DETECTION if BOARD_LENOVO_T430S
 	select H8_HAS_PRIMARY_FN_KEYS if BOARD_LENOVO_T431S
 	select NO_UART_ON_SUPERIO
 	select BOARD_ROMSIZE_KB_16384
diff --git a/src/mainboard/lenovo/t430s/variants/t430s/overridetree.cb b/src/mainboard/lenovo/t430s/variants/t430s/overridetree.cb
index a9da730815..bc947af287 100644
--- a/src/mainboard/lenovo/t430s/variants/t430s/overridetree.cb
+++ b/src/mainboard/lenovo/t430s/variants/t430s/overridetree.cb
@@ -24,7 +24,6 @@ chip northbridge/intel/sandybridge
 			device ref lpc on
 				chip ec/lenovo/h8
 					device pnp ff.2 on end # dummy
-					register "has_bdc_detection" = "1"
 					register "bdc_gpio_num" = "54"
 					register "bdc_gpio_lvl" = "0"
 				end
diff --git a/src/mainboard/lenovo/t430s/variants/t431s/overridetree.cb b/src/mainboard/lenovo/t430s/variants/t431s/overridetree.cb
index 15712f941d..dae8bc7a2d 100644
--- a/src/mainboard/lenovo/t430s/variants/t431s/overridetree.cb
+++ b/src/mainboard/lenovo/t430s/variants/t431s/overridetree.cb
@@ -55,8 +55,6 @@ chip northbridge/intel/sandybridge
 					register "config1" = "0x09"
 					register "config3" = "0xc0"
 					register "evente_enable" = "0x1d"
-					# T431s only has BT on wlan card
-					register "has_bdc_detection" = "0"
 				end
 			end
 			device ref thermal off end
diff --git a/src/mainboard/lenovo/t520/Kconfig b/src/mainboard/lenovo/t520/Kconfig
index 663113b98f..384927989f 100644
--- a/src/mainboard/lenovo/t520/Kconfig
+++ b/src/mainboard/lenovo/t520/Kconfig
@@ -9,6 +9,8 @@ config BOARD_LENOVO_BASEBOARD_T520
 	select EC_LENOVO_PMH7
 	select EC_LENOVO_H8
 	select H8_HAS_BAT_THRESHOLDS_IMPL
+	select H8_HAS_BDC_GPIO_DETECTION
+	select H8_HAS_WWAN_GPIO_DETECTION
 	select NO_UART_ON_SUPERIO
 	select BOARD_ROMSIZE_KB_8192
 	select HAVE_ACPI_TABLES
diff --git a/src/mainboard/lenovo/t520/devicetree.cb b/src/mainboard/lenovo/t520/devicetree.cb
index 7102df0b9d..74605ca081 100644
--- a/src/mainboard/lenovo/t520/devicetree.cb
+++ b/src/mainboard/lenovo/t520/devicetree.cb
@@ -137,7 +137,6 @@ chip northbridge/intel/sandybridge
 					register "eventd_enable" = "0xff"
 					register "evente_enable" = "0x0d"
 
-					register "has_bdc_detection" = "1"
 					register "bdc_gpio_num" = "54"
 					register "bdc_gpio_lvl" = "0"
 				end
diff --git a/src/mainboard/lenovo/t520/variants/t520/overridetree.cb b/src/mainboard/lenovo/t520/variants/t520/overridetree.cb
index 52946d1b6e..48d8f34e8d 100644
--- a/src/mainboard/lenovo/t520/variants/t520/overridetree.cb
+++ b/src/mainboard/lenovo/t520/variants/t520/overridetree.cb
@@ -5,7 +5,6 @@ chip northbridge/intel/sandybridge
 			device ref lpc on
 				chip ec/lenovo/h8
 					device pnp ff.2 on end # dummy
-					register "has_wwan_detection" = "1"
 					register "wwan_gpio_num" = "70"
 					register "wwan_gpio_lvl" = "0"
 				end
diff --git a/src/mainboard/lenovo/t530/Kconfig b/src/mainboard/lenovo/t530/Kconfig
index a797656d71..9450fdddd7 100644
--- a/src/mainboard/lenovo/t530/Kconfig
+++ b/src/mainboard/lenovo/t530/Kconfig
@@ -9,6 +9,8 @@ config BOARD_LENOVO_BASEBOARD_T530
 	select EC_LENOVO_PMH7
 	select GFX_GMA_PANEL_1_ON_LVDS
 	select H8_HAS_BAT_THRESHOLDS_IMPL
+	select H8_HAS_BDC_GPIO_DETECTION
+	select H8_HAS_WWAN_GPIO_DETECTION
 	select HAVE_ACPI_RESUME
 	select HAVE_ACPI_TABLES
 	select HAVE_CMOS_DEFAULT
diff --git a/src/mainboard/lenovo/t530/devicetree.cb b/src/mainboard/lenovo/t530/devicetree.cb
index 362e0a69e9..13c40d91d4 100644
--- a/src/mainboard/lenovo/t530/devicetree.cb
+++ b/src/mainboard/lenovo/t530/devicetree.cb
@@ -117,7 +117,6 @@ chip northbridge/intel/sandybridge
 					register "eventd_enable" = "0xff"
 					register "evente_enable" = "0x0d"
 
-					register "has_bdc_detection" = "1"
 					register "bdc_gpio_num" = "54"
 					register "bdc_gpio_lvl" = "0"
 				end
diff --git a/src/mainboard/lenovo/t530/variants/t530/overridetree.cb b/src/mainboard/lenovo/t530/variants/t530/overridetree.cb
index 3f058e3854..9bd36488f6 100644
--- a/src/mainboard/lenovo/t530/variants/t530/overridetree.cb
+++ b/src/mainboard/lenovo/t530/variants/t530/overridetree.cb
@@ -21,7 +21,6 @@ chip northbridge/intel/sandybridge
 			device ref lpc on
 				chip ec/lenovo/h8
 					device pnp ff.2 on end # dummy
-					register "has_wwan_detection" = "1"
 					register "wwan_gpio_num" = "70"
 					register "wwan_gpio_lvl" = "0"
 				end
diff --git a/src/mainboard/lenovo/t60/Kconfig b/src/mainboard/lenovo/t60/Kconfig
index ec3a6e01bb..6d095943bd 100644
--- a/src/mainboard/lenovo/t60/Kconfig
+++ b/src/mainboard/lenovo/t60/Kconfig
@@ -25,6 +25,7 @@ config BOARD_SPECIFIC_OPTIONS
 	select HAVE_CMOS_DEFAULT
 	select I945_LVDS
 	select INTEL_GMA_HAVE_VBT
+	select H8_HAS_BDC_GPIO_DETECTION if BOARD_LENOVO_T60 || BOARD_LENOVO_R60
 
 config MAINBOARD_DIR
 	default "lenovo/t60"
diff --git a/src/mainboard/lenovo/t60/variants/t60/overridetree.cb b/src/mainboard/lenovo/t60/variants/t60/overridetree.cb
index c58884a4b5..42e07a648c 100644
--- a/src/mainboard/lenovo/t60/variants/t60/overridetree.cb
+++ b/src/mainboard/lenovo/t60/variants/t60/overridetree.cb
@@ -26,7 +26,6 @@ chip northbridge/intel/i945
 			end
 			device pci 1f.0 on # PCI-LPC bridge
 				chip ec/lenovo/h8
-					register "has_bdc_detection" = "1"
 					register "bdc_gpio_num" = "7"
 					register "bdc_gpio_lvl" = "0"
 					device pnp ff.2 on end
diff --git a/src/mainboard/lenovo/x1_carbon_gen1/Kconfig b/src/mainboard/lenovo/x1_carbon_gen1/Kconfig
index 4e4c58b246..f0dcb38ab4 100644
--- a/src/mainboard/lenovo/x1_carbon_gen1/Kconfig
+++ b/src/mainboard/lenovo/x1_carbon_gen1/Kconfig
@@ -11,6 +11,8 @@ config BOARD_SPECIFIC_OPTIONS
 	select EC_LENOVO_PMH7
 	select GFX_GMA_PANEL_1_ON_LVDS
 	select H8_HAS_BAT_THRESHOLDS_IMPL
+	select H8_HAS_BDC_GPIO_DETECTION
+	select H8_HAS_WWAN_GPIO_DETECTION
 	select HAVE_ACPI_RESUME
 	select HAVE_ACPI_TABLES
 	select HAVE_CMOS_DEFAULT
diff --git a/src/mainboard/lenovo/x1_carbon_gen1/devicetree.cb b/src/mainboard/lenovo/x1_carbon_gen1/devicetree.cb
index 84611d0656..6f601e9521 100644
--- a/src/mainboard/lenovo/x1_carbon_gen1/devicetree.cb
+++ b/src/mainboard/lenovo/x1_carbon_gen1/devicetree.cb
@@ -127,11 +127,9 @@ chip northbridge/intel/sandybridge
 					register "eventd_enable" = "0xff"
 					register "evente_enable" = "0x0d"
 
-					register "has_bdc_detection" = "1"
 					register "bdc_gpio_num" = "54"
 					register "bdc_gpio_lvl" = "0"
 
-					register "has_wwan_detection" = "1"
 					register "wwan_gpio_num" = "70"
 					register "wwan_gpio_lvl" = "0"
 				end
diff --git a/src/mainboard/lenovo/x200/Kconfig b/src/mainboard/lenovo/x200/Kconfig
index 29e2f6ca91..4aa1e2ce1e 100644
--- a/src/mainboard/lenovo/x200/Kconfig
+++ b/src/mainboard/lenovo/x200/Kconfig
@@ -11,6 +11,7 @@ config BOARD_SPECIFIC_OPTIONS
 	select EC_LENOVO_PMH7
 	select EC_LENOVO_H8
 	select H8_HAS_BAT_THRESHOLDS_IMPL
+	select H8_HAS_BDC_GPIO_DETECTION if BOARD_LENOVO_X200
 	select NO_UART_ON_SUPERIO
 	select BOARD_ROMSIZE_KB_8192
 	select HAVE_ACPI_TABLES
diff --git a/src/mainboard/lenovo/x200/devicetree.cb b/src/mainboard/lenovo/x200/devicetree.cb
index 7871cfd00d..2d6ea77214 100644
--- a/src/mainboard/lenovo/x200/devicetree.cb
+++ b/src/mainboard/lenovo/x200/devicetree.cb
@@ -144,7 +144,6 @@ chip northbridge/intel/gm45
 					register "eventc_enable" = "0xff"
 					register "eventd_enable" = "0xff"
 
-					register "has_bdc_detection" = "1"
 					register "bdc_gpio_num" = "7"
 					register "bdc_gpio_lvl" = "0"
 				end
diff --git a/src/mainboard/lenovo/x201/Kconfig b/src/mainboard/lenovo/x201/Kconfig
index 8517232d20..319f127ab6 100644
--- a/src/mainboard/lenovo/x201/Kconfig
+++ b/src/mainboard/lenovo/x201/Kconfig
@@ -25,6 +25,7 @@ config BOARD_SPECIFIC_OPTIONS
 	select INTEL_GMA_HAVE_VBT
 	select MAINBOARD_USES_IFD_GBE_REGION
 	select H8_HAS_BAT_THRESHOLDS_IMPL
+	select H8_HAS_BDC_GPIO_DETECTION
 
 config VBOOT
 	select VBOOT_VBNV_FLASH
diff --git a/src/mainboard/lenovo/x201/devicetree.cb b/src/mainboard/lenovo/x201/devicetree.cb
index 0be8a3ba07..5b6746b718 100644
--- a/src/mainboard/lenovo/x201/devicetree.cb
+++ b/src/mainboard/lenovo/x201/devicetree.cb
@@ -140,7 +140,6 @@ chip northbridge/intel/ironlake
 					register "eventc_enable" = "0xff"
 					register "eventd_enable" = "0xff"
 
-					register "has_bdc_detection" = "1"
 					register "bdc_gpio_num" = "48"
 					register "bdc_gpio_lvl" = "0"
 				end
diff --git a/src/mainboard/lenovo/x220/Kconfig b/src/mainboard/lenovo/x220/Kconfig
index e6a2e66209..a877546bb7 100644
--- a/src/mainboard/lenovo/x220/Kconfig
+++ b/src/mainboard/lenovo/x220/Kconfig
@@ -11,6 +11,7 @@ config BOARD_SPECIFIC_OPTIONS
 	select EC_LENOVO_PMH7
 	select GFX_GMA_PANEL_1_ON_LVDS
 	select H8_HAS_BAT_THRESHOLDS_IMPL
+	select H8_HAS_WWAN_GPIO_DETECTION
 	select HAVE_ACPI_RESUME
 	select HAVE_ACPI_TABLES
 	select HAVE_CMOS_DEFAULT
diff --git a/src/mainboard/lenovo/x220/devicetree.cb b/src/mainboard/lenovo/x220/devicetree.cb
index aaeecc8246..0ca9bcc6a3 100644
--- a/src/mainboard/lenovo/x220/devicetree.cb
+++ b/src/mainboard/lenovo/x220/devicetree.cb
@@ -141,9 +141,7 @@ chip northbridge/intel/sandybridge
 					#  BDC shorts pin14 and pin1
 					#  BDC's connector pin14 is left floating
 					#  BDC's connector pin1 is routed to SB GPIO 54
-					register "has_bdc_detection" = "0"
 
-					register "has_wwan_detection" = "1"
 					register "wwan_gpio_num" = "70"
 					register "wwan_gpio_lvl" = "0"
 				end
diff --git a/src/mainboard/lenovo/x230/Kconfig b/src/mainboard/lenovo/x230/Kconfig
index 1d04af9bff..cb6395beb9 100644
--- a/src/mainboard/lenovo/x230/Kconfig
+++ b/src/mainboard/lenovo/x230/Kconfig
@@ -12,6 +12,7 @@ config BOARD_SPECIFIC_OPTIONS
 	select EC_LENOVO_H8
 	select H8_HAS_BAT_THRESHOLDS_IMPL
 	select H8_HAS_PRIMARY_FN_KEYS if BOARD_LENOVO_X230S
+	select H8_HAS_WWAN_GPIO_DETECTION if !BOARD_LENOVO_X230S
 	select NO_UART_ON_SUPERIO
 	select BOARD_ROMSIZE_KB_12288 if BOARD_LENOVO_X230 || BOARD_LENOVO_X230T || BOARD_LENOVO_X230_EDP
 	select BOARD_ROMSIZE_KB_16384 if BOARD_LENOVO_X230S
diff --git a/src/mainboard/lenovo/x230/devicetree.cb b/src/mainboard/lenovo/x230/devicetree.cb
index 3067096f0d..735ce4d9d9 100644
--- a/src/mainboard/lenovo/x230/devicetree.cb
+++ b/src/mainboard/lenovo/x230/devicetree.cb
@@ -123,9 +123,7 @@ chip northbridge/intel/sandybridge
 					#  BDC shorts pin14 and pin1
 					#  BDC's connector pin14 is left floating
 					#  BDC's connector pin1 is routed to SB GPIO 54
-					register "has_bdc_detection" = "0"
 
-					register "has_wwan_detection" = "1"
 					register "wwan_gpio_num" = "70"
 					register "wwan_gpio_lvl" = "0"
 				end
diff --git a/src/mainboard/lenovo/x230/variants/x230s/overridetree.cb b/src/mainboard/lenovo/x230/variants/x230s/overridetree.cb
index a84b5f3bdd..86c2e16e7d 100644
--- a/src/mainboard/lenovo/x230/variants/x230s/overridetree.cb
+++ b/src/mainboard/lenovo/x230/variants/x230s/overridetree.cb
@@ -40,8 +40,6 @@ chip northbridge/intel/sandybridge
 					register "config3" = "0xc4"
 					register "event5_enable" = "0x3c"
 					register "evente_enable" = "0x1d"
-					# X230s only has BT on wlan card
-					register "has_bdc_detection" = "0"
 					device pnp ff.2 on end
 				end
 			end
diff --git a/src/mainboard/lenovo/x60/Kconfig b/src/mainboard/lenovo/x60/Kconfig
index 0f12a9272e..33238ccbd8 100644
--- a/src/mainboard/lenovo/x60/Kconfig
+++ b/src/mainboard/lenovo/x60/Kconfig
@@ -16,6 +16,7 @@ config BOARD_SPECIFIC_OPTIONS
 	select EC_LENOVO_H8
 	select DRIVERS_I2C_CK505
 	select DRIVER_LENOVO_SERIALS
+	select H8_HAS_BDC_GPIO_DETECTION
 	select HAVE_OPTION_TABLE
 	select INTEL_INT15
 	select HAVE_CMOS_DEFAULT
diff --git a/src/mainboard/lenovo/x60/devicetree.cb b/src/mainboard/lenovo/x60/devicetree.cb
index 0e1e5fced5..7f28bbae49 100644
--- a/src/mainboard/lenovo/x60/devicetree.cb
+++ b/src/mainboard/lenovo/x60/devicetree.cb
@@ -130,7 +130,6 @@ chip northbridge/intel/i945
 					register "eventc_enable" = "0xff"
 					register "eventd_enable" = "0xff"
 
-					register "has_bdc_detection" = "1"
 					register "bdc_gpio_num" = "7"
 					register "bdc_gpio_lvl" = "0"
 				end

From 621b1061d063c44ed77ac7aa3ad5ea72bedf6164 Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Sat, 12 Jul 2025 17:17:42 -0500
Subject: [PATCH 1561/3886] ec/lenovo/h8: Add Kconfig to select use of Thermal
 Zone 1

Looking at the ACPI dumps of many older Thinkpads, most do not have a
second thermal zone (zone 1), they only use zone 0. This doesn't seem
to be a problem for most boards in the tree currently, but newer boards
(such as the T480) are reporting critical temperature errors on zone 1,
due to differences in the EC RAM layout (ie, TMP1 is not valid).

To mitigate this issue with the T480 (and likely other newer boards),
only include the ACPI code for thermal zone 1 for boards which need it.
Explicitly select it for those boards based on ACPI dump analysis and
model similarity.

Change-Id: Ic022f2e14b2cae74656c0ac85ba8410d50cdc9de
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88415
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
---
 src/ec/lenovo/h8/Kconfig          | 4 ++++
 src/ec/lenovo/h8/acpi/thermal.asl | 3 ++-
 src/mainboard/lenovo/t400/Kconfig | 1 +
 src/mainboard/lenovo/t410/Kconfig | 1 +
 src/mainboard/lenovo/t60/Kconfig  | 1 +
 src/mainboard/lenovo/x200/Kconfig | 1 +
 src/mainboard/lenovo/x201/Kconfig | 1 +
 src/mainboard/lenovo/x60/Kconfig  | 1 +
 8 files changed, 12 insertions(+), 1 deletion(-)

diff --git a/src/ec/lenovo/h8/Kconfig b/src/ec/lenovo/h8/Kconfig
index fbdca5f94a..c8626cc75b 100644
--- a/src/ec/lenovo/h8/Kconfig
+++ b/src/ec/lenovo/h8/Kconfig
@@ -73,4 +73,8 @@ config H8_HAS_WWAN_GPIO_DETECTION
 	bool
 	default n
 
+config H8_HAS_2ND_THERMAL_ZONE
+	bool
+	default n
+
 endif # EC_LENOVO_H8
diff --git a/src/ec/lenovo/h8/acpi/thermal.asl b/src/ec/lenovo/h8/acpi/thermal.asl
index fa5a282f54..bf9b653e12 100644
--- a/src/ec/lenovo/h8/acpi/thermal.asl
+++ b/src/ec/lenovo/h8/acpi/thermal.asl
@@ -130,7 +130,7 @@ External (\PPKG, MethodObj)
 			Name (_PR0, Package () { FPWR })
 		}
 	}
-
+#if CONFIG(H8_HAS_2ND_THERMAL_ZONE)
 	ThermalZone(THM1)
 	{
 		/* Thermal zone polling frequency: 10 seconds */
@@ -168,4 +168,5 @@ External (\PPKG, MethodObj)
 			Return (C2K(\_SB.PCI0.LPCB.EC.TMP1))
 		}
 	}
+#endif
 }
diff --git a/src/mainboard/lenovo/t400/Kconfig b/src/mainboard/lenovo/t400/Kconfig
index 85e580e30e..12fbcbdee6 100644
--- a/src/mainboard/lenovo/t400/Kconfig
+++ b/src/mainboard/lenovo/t400/Kconfig
@@ -11,6 +11,7 @@ config BOARD_SPECIFIC_OPTIONS
 	select SOUTHBRIDGE_INTEL_I82801IX
 	select EC_LENOVO_PMH7
 	select EC_LENOVO_H8
+	select H8_HAS_2ND_THERMAL_ZONE
 	select H8_HAS_BAT_THRESHOLDS_IMPL
 	select H8_HAS_BDC_GPIO_DETECTION if !BOARD_LENOVO_R500
 	select BOARD_ROMSIZE_KB_8192 if !BOARD_LENOVO_R500
diff --git a/src/mainboard/lenovo/t410/Kconfig b/src/mainboard/lenovo/t410/Kconfig
index 9c78cb1741..6f18528824 100644
--- a/src/mainboard/lenovo/t410/Kconfig
+++ b/src/mainboard/lenovo/t410/Kconfig
@@ -22,6 +22,7 @@ config BOARD_SPECIFIC_OPTIONS
 	select DRIVERS_LENOVO_HYBRID_GRAPHICS
 	select INTEL_GMA_HAVE_VBT
 	select MAINBOARD_USES_IFD_GBE_REGION
+	select H8_HAS_2ND_THERMAL_ZONE
 	select H8_HAS_BAT_THRESHOLDS_IMPL
 	select MAINBOARD_HAS_LIBGFXINIT
 	select DRIVERS_RICOH_RCE822
diff --git a/src/mainboard/lenovo/t60/Kconfig b/src/mainboard/lenovo/t60/Kconfig
index 6d095943bd..f1221191da 100644
--- a/src/mainboard/lenovo/t60/Kconfig
+++ b/src/mainboard/lenovo/t60/Kconfig
@@ -25,6 +25,7 @@ config BOARD_SPECIFIC_OPTIONS
 	select HAVE_CMOS_DEFAULT
 	select I945_LVDS
 	select INTEL_GMA_HAVE_VBT
+	select H8_HAS_2ND_THERMAL_ZONE
 	select H8_HAS_BDC_GPIO_DETECTION if BOARD_LENOVO_T60 || BOARD_LENOVO_R60
 
 config MAINBOARD_DIR
diff --git a/src/mainboard/lenovo/x200/Kconfig b/src/mainboard/lenovo/x200/Kconfig
index 4aa1e2ce1e..148584ed5c 100644
--- a/src/mainboard/lenovo/x200/Kconfig
+++ b/src/mainboard/lenovo/x200/Kconfig
@@ -10,6 +10,7 @@ config BOARD_SPECIFIC_OPTIONS
 	select SOUTHBRIDGE_INTEL_I82801IX
 	select EC_LENOVO_PMH7
 	select EC_LENOVO_H8
+	select H8_HAS_2ND_THERMAL_ZONE if BOARD_LENOVO_X200
 	select H8_HAS_BAT_THRESHOLDS_IMPL
 	select H8_HAS_BDC_GPIO_DETECTION if BOARD_LENOVO_X200
 	select NO_UART_ON_SUPERIO
diff --git a/src/mainboard/lenovo/x201/Kconfig b/src/mainboard/lenovo/x201/Kconfig
index 319f127ab6..e91ec3e642 100644
--- a/src/mainboard/lenovo/x201/Kconfig
+++ b/src/mainboard/lenovo/x201/Kconfig
@@ -24,6 +24,7 @@ config BOARD_SPECIFIC_OPTIONS
 	select MAINBOARD_HAS_TPM1
 	select INTEL_GMA_HAVE_VBT
 	select MAINBOARD_USES_IFD_GBE_REGION
+	select H8_HAS_2ND_THERMAL_ZONE
 	select H8_HAS_BAT_THRESHOLDS_IMPL
 	select H8_HAS_BDC_GPIO_DETECTION
 
diff --git a/src/mainboard/lenovo/x60/Kconfig b/src/mainboard/lenovo/x60/Kconfig
index 33238ccbd8..edacdcf234 100644
--- a/src/mainboard/lenovo/x60/Kconfig
+++ b/src/mainboard/lenovo/x60/Kconfig
@@ -16,6 +16,7 @@ config BOARD_SPECIFIC_OPTIONS
 	select EC_LENOVO_H8
 	select DRIVERS_I2C_CK505
 	select DRIVER_LENOVO_SERIALS
+	select H8_HAS_2ND_THERMAL_ZONE
 	select H8_HAS_BDC_GPIO_DETECTION
 	select HAVE_OPTION_TABLE
 	select INTEL_INT15

From 6082bd771190e5938d71d1ec58f09c02439f7f94 Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Sat, 12 Jul 2025 17:28:13 -0500
Subject: [PATCH 1562/3886] ec/lenovo/h8: Rework invalid temperature reporting

As far back as the x201, Lenovo's EC ACPI has treated 128 as an invalid
value, and returned a corrected value when it is reported/read from EC
RAM. Drop the ME workaround, which most H8-equipped boards select, in
favor of Lenovo's logic, since both accomplish the same result.

Change-Id: Icdc91e439ec30c8263de5810a13e75f7595472a5
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88416
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/ec/lenovo/h8/acpi/thermal.asl             | 25 ++++++-------------
 .../lenovo/haswell/acpi/platform.asl          |  3 ---
 src/mainboard/lenovo/haswell/dsdt.asl         |  1 -
 src/mainboard/lenovo/l520/acpi/platform.asl   |  4 ---
 src/mainboard/lenovo/l520/dsdt.asl            |  1 -
 src/mainboard/lenovo/s230u/dsdt.asl           |  1 -
 src/mainboard/lenovo/t400/dsdt.asl            |  1 -
 src/mainboard/lenovo/t410/dsdt.asl            |  1 -
 src/mainboard/lenovo/t420/acpi/platform.asl   |  4 ---
 src/mainboard/lenovo/t420/dsdt.asl            |  1 -
 src/mainboard/lenovo/t420s/acpi/platform.asl  |  4 ---
 src/mainboard/lenovo/t420s/dsdt.asl           |  1 -
 src/mainboard/lenovo/t430/acpi/platform.asl   |  4 ---
 src/mainboard/lenovo/t430/dsdt.asl            |  1 -
 src/mainboard/lenovo/t430s/acpi/platform.asl  |  4 ---
 src/mainboard/lenovo/t430s/dsdt.asl           |  1 -
 src/mainboard/lenovo/t520/acpi/platform.asl   |  4 ---
 src/mainboard/lenovo/t520/dsdt.asl            |  1 -
 src/mainboard/lenovo/t530/acpi/platform.asl   |  4 ---
 src/mainboard/lenovo/t530/dsdt.asl            |  1 -
 src/mainboard/lenovo/x131e/acpi/platform.asl  |  4 ---
 src/mainboard/lenovo/x131e/dsdt.asl           |  1 -
 .../lenovo/x1_carbon_gen1/acpi/platform.asl   |  4 ---
 src/mainboard/lenovo/x1_carbon_gen1/dsdt.asl  |  1 -
 src/mainboard/lenovo/x201/acpi/platform.asl   |  4 ---
 src/mainboard/lenovo/x201/dsdt.asl            |  1 -
 src/mainboard/lenovo/x220/acpi/platform.asl   |  4 ---
 src/mainboard/lenovo/x220/dsdt.asl            |  1 -
 src/mainboard/lenovo/x230/acpi/platform.asl   |  4 ---
 src/mainboard/lenovo/x230/dsdt.asl            |  1 -
 30 files changed, 8 insertions(+), 84 deletions(-)

diff --git a/src/ec/lenovo/h8/acpi/thermal.asl b/src/ec/lenovo/h8/acpi/thermal.asl
index bf9b653e12..54f4f922bd 100644
--- a/src/ec/lenovo/h8/acpi/thermal.asl
+++ b/src/ec/lenovo/h8/acpi/thermal.asl
@@ -4,11 +4,6 @@
 
 Scope(\_TZ)
 {
-#if defined(EC_LENOVO_H8_ME_WORKAROUND)
-	Name (MEB1, 0)
-	Name (MEB2, 0)
-#endif
-
 	Method(C2K, 1, NotSerialized)
 	{
 		Local0 = Arg0 * 10
@@ -71,14 +66,12 @@ External (\PPKG, MethodObj)
 		}
 
 		Method(_TMP) {
-#if defined(EC_LENOVO_H8_ME_WORKAROUND)
-			/* Avoid tripping alarm if ME isn't booted at all yet */
-			If (!MEB1 && \_SB.PCI0.LPCB.EC.TMP0 == 128) {
+			Local0 = \_SB.PCI0.LPCB.EC.TMP0
+			/* Avoid tripping alarm if invalid value reported */
+			If (Local0 == 128) {
 				Return (C2K(40))
 			}
-			MEB1 = 1
-#endif
-			Return (C2K(\_SB.PCI0.LPCB.EC.TMP0))
+			Return (C2K(Local0))
 		}
 
 		Method (_AC0) {
@@ -158,14 +151,12 @@ External (\PPKG, MethodObj)
 		}
 
 		Method(_TMP) {
-#if defined(EC_LENOVO_H8_ME_WORKAROUND)
-			/* Avoid tripping alarm if ME isn't booted at all yet */
-			If (!MEB2 && \_SB.PCI0.LPCB.EC.TMP1 == 128) {
+			Local0 = \_SB.PCI0.LPCB.EC.TMP1
+			/* Avoid tripping alarm if invalid value reported */
+			If (Local0 == 128) {
 				Return (C2K(40))
 			}
-			MEB2 = 1
-#endif
-			Return (C2K(\_SB.PCI0.LPCB.EC.TMP1))
+			Return (C2K(Local0))
 		}
 	}
 #endif
diff --git a/src/mainboard/lenovo/haswell/acpi/platform.asl b/src/mainboard/lenovo/haswell/acpi/platform.asl
index f5a4df75f4..42587fd78a 100644
--- a/src/mainboard/lenovo/haswell/acpi/platform.asl
+++ b/src/mainboard/lenovo/haswell/acpi/platform.asl
@@ -2,9 +2,6 @@
 
 Method(_WAK,1)
 {
-	/* ME may not be up yet. */
-	\_TZ.MEB1 = 0
-	\_TZ.MEB2 = 0
 	Return(Package(){0,0})
 }
 
diff --git a/src/mainboard/lenovo/haswell/dsdt.asl b/src/mainboard/lenovo/haswell/dsdt.asl
index a7afeee766..708f524b08 100644
--- a/src/mainboard/lenovo/haswell/dsdt.asl
+++ b/src/mainboard/lenovo/haswell/dsdt.asl
@@ -2,7 +2,6 @@
 
 #define BRIGHTNESS_UP \_SB.PCI0.GFX0.INCB
 #define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.DECB
-#define EC_LENOVO_H8_ME_WORKAROUND 1
 #define THINKPAD_EC_GPE 17
 
 #include <acpi/acpi.h>
diff --git a/src/mainboard/lenovo/l520/acpi/platform.asl b/src/mainboard/lenovo/l520/acpi/platform.asl
index c4becafc2a..9dee90edc3 100644
--- a/src/mainboard/lenovo/l520/acpi/platform.asl
+++ b/src/mainboard/lenovo/l520/acpi/platform.asl
@@ -15,10 +15,6 @@ Method(_PTS,1)
 
 Method(_WAK,1)
 {
-	/* ME may not be up yet. */
-	\_TZ.MEB1 = 0
-	\_TZ.MEB2 = 0
-
 	/* Wake the HKEY to init BT/WWAN */
 	\_SB.PCI0.LPCB.EC.HKEY.WAKE (Arg0)
 
diff --git a/src/mainboard/lenovo/l520/dsdt.asl b/src/mainboard/lenovo/l520/dsdt.asl
index 06cffcf8a2..18e9f25a9a 100644
--- a/src/mainboard/lenovo/l520/dsdt.asl
+++ b/src/mainboard/lenovo/l520/dsdt.asl
@@ -3,7 +3,6 @@
 #define THINKPAD_EC_GPE 22
 #define BRIGHTNESS_UP \_SB.PCI0.GFX0.INCB
 #define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.DECB
-#define EC_LENOVO_H8_ME_WORKAROUND 1
 
 #include <acpi/acpi.h>
 DefinitionBlock(
diff --git a/src/mainboard/lenovo/s230u/dsdt.asl b/src/mainboard/lenovo/s230u/dsdt.asl
index 861309b8e9..47e91fdb30 100644
--- a/src/mainboard/lenovo/s230u/dsdt.asl
+++ b/src/mainboard/lenovo/s230u/dsdt.asl
@@ -3,7 +3,6 @@
 #define THINKPAD_EC_GPE 23
 #define BRIGHTNESS_UP \_SB.PCI0.GFX0.INCB
 #define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.DECB
-#define EC_LENOVO_H8_ME_WORKAROUND 1
 
 #include <acpi/acpi.h>
 DefinitionBlock(
diff --git a/src/mainboard/lenovo/t400/dsdt.asl b/src/mainboard/lenovo/t400/dsdt.asl
index f9c682f9dc..cb824e42da 100644
--- a/src/mainboard/lenovo/t400/dsdt.asl
+++ b/src/mainboard/lenovo/t400/dsdt.asl
@@ -3,7 +3,6 @@
 #define THINKPAD_EC_GPE 17
 #define BRIGHTNESS_UP \_SB.PCI0.GFX0.INCB
 #define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.DECB
-#define EC_LENOVO_H8_ME_WORKAROUND 1
 
 #include <acpi/acpi.h>
 DefinitionBlock(
diff --git a/src/mainboard/lenovo/t410/dsdt.asl b/src/mainboard/lenovo/t410/dsdt.asl
index 42a10e605c..e2571f60c7 100644
--- a/src/mainboard/lenovo/t410/dsdt.asl
+++ b/src/mainboard/lenovo/t410/dsdt.asl
@@ -3,7 +3,6 @@
 #define THINKPAD_EC_GPE 17
 #define BRIGHTNESS_UP \_SB.PCI0.GFX0.INCB
 #define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.DECB
-#define EC_LENOVO_H8_ME_WORKAROUND 1
 
 #include <acpi/acpi.h>
 DefinitionBlock(
diff --git a/src/mainboard/lenovo/t420/acpi/platform.asl b/src/mainboard/lenovo/t420/acpi/platform.asl
index c4becafc2a..9dee90edc3 100644
--- a/src/mainboard/lenovo/t420/acpi/platform.asl
+++ b/src/mainboard/lenovo/t420/acpi/platform.asl
@@ -15,10 +15,6 @@ Method(_PTS,1)
 
 Method(_WAK,1)
 {
-	/* ME may not be up yet. */
-	\_TZ.MEB1 = 0
-	\_TZ.MEB2 = 0
-
 	/* Wake the HKEY to init BT/WWAN */
 	\_SB.PCI0.LPCB.EC.HKEY.WAKE (Arg0)
 
diff --git a/src/mainboard/lenovo/t420/dsdt.asl b/src/mainboard/lenovo/t420/dsdt.asl
index 33b6f80b17..1134782675 100644
--- a/src/mainboard/lenovo/t420/dsdt.asl
+++ b/src/mainboard/lenovo/t420/dsdt.asl
@@ -3,7 +3,6 @@
 #define THINKPAD_EC_GPE 17
 #define BRIGHTNESS_UP \_SB.PCI0.GFX0.INCB
 #define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.DECB
-#define EC_LENOVO_H8_ME_WORKAROUND 1
 
 #include <acpi/acpi.h>
 DefinitionBlock(
diff --git a/src/mainboard/lenovo/t420s/acpi/platform.asl b/src/mainboard/lenovo/t420s/acpi/platform.asl
index c4becafc2a..9dee90edc3 100644
--- a/src/mainboard/lenovo/t420s/acpi/platform.asl
+++ b/src/mainboard/lenovo/t420s/acpi/platform.asl
@@ -15,10 +15,6 @@ Method(_PTS,1)
 
 Method(_WAK,1)
 {
-	/* ME may not be up yet. */
-	\_TZ.MEB1 = 0
-	\_TZ.MEB2 = 0
-
 	/* Wake the HKEY to init BT/WWAN */
 	\_SB.PCI0.LPCB.EC.HKEY.WAKE (Arg0)
 
diff --git a/src/mainboard/lenovo/t420s/dsdt.asl b/src/mainboard/lenovo/t420s/dsdt.asl
index 33b6f80b17..1134782675 100644
--- a/src/mainboard/lenovo/t420s/dsdt.asl
+++ b/src/mainboard/lenovo/t420s/dsdt.asl
@@ -3,7 +3,6 @@
 #define THINKPAD_EC_GPE 17
 #define BRIGHTNESS_UP \_SB.PCI0.GFX0.INCB
 #define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.DECB
-#define EC_LENOVO_H8_ME_WORKAROUND 1
 
 #include <acpi/acpi.h>
 DefinitionBlock(
diff --git a/src/mainboard/lenovo/t430/acpi/platform.asl b/src/mainboard/lenovo/t430/acpi/platform.asl
index c4becafc2a..9dee90edc3 100644
--- a/src/mainboard/lenovo/t430/acpi/platform.asl
+++ b/src/mainboard/lenovo/t430/acpi/platform.asl
@@ -15,10 +15,6 @@ Method(_PTS,1)
 
 Method(_WAK,1)
 {
-	/* ME may not be up yet. */
-	\_TZ.MEB1 = 0
-	\_TZ.MEB2 = 0
-
 	/* Wake the HKEY to init BT/WWAN */
 	\_SB.PCI0.LPCB.EC.HKEY.WAKE (Arg0)
 
diff --git a/src/mainboard/lenovo/t430/dsdt.asl b/src/mainboard/lenovo/t430/dsdt.asl
index c19e75ee82..795f9a1ee9 100644
--- a/src/mainboard/lenovo/t430/dsdt.asl
+++ b/src/mainboard/lenovo/t430/dsdt.asl
@@ -3,7 +3,6 @@
 #define THINKPAD_EC_GPE 17
 #define BRIGHTNESS_UP \_SB.PCI0.GFX0.INCB
 #define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.DECB
-#define EC_LENOVO_H8_ME_WORKAROUND 1
 
 #include <acpi/acpi.h>
 DefinitionBlock(
diff --git a/src/mainboard/lenovo/t430s/acpi/platform.asl b/src/mainboard/lenovo/t430s/acpi/platform.asl
index c4becafc2a..9dee90edc3 100644
--- a/src/mainboard/lenovo/t430s/acpi/platform.asl
+++ b/src/mainboard/lenovo/t430s/acpi/platform.asl
@@ -15,10 +15,6 @@ Method(_PTS,1)
 
 Method(_WAK,1)
 {
-	/* ME may not be up yet. */
-	\_TZ.MEB1 = 0
-	\_TZ.MEB2 = 0
-
 	/* Wake the HKEY to init BT/WWAN */
 	\_SB.PCI0.LPCB.EC.HKEY.WAKE (Arg0)
 
diff --git a/src/mainboard/lenovo/t430s/dsdt.asl b/src/mainboard/lenovo/t430s/dsdt.asl
index 33b6f80b17..1134782675 100644
--- a/src/mainboard/lenovo/t430s/dsdt.asl
+++ b/src/mainboard/lenovo/t430s/dsdt.asl
@@ -3,7 +3,6 @@
 #define THINKPAD_EC_GPE 17
 #define BRIGHTNESS_UP \_SB.PCI0.GFX0.INCB
 #define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.DECB
-#define EC_LENOVO_H8_ME_WORKAROUND 1
 
 #include <acpi/acpi.h>
 DefinitionBlock(
diff --git a/src/mainboard/lenovo/t520/acpi/platform.asl b/src/mainboard/lenovo/t520/acpi/platform.asl
index c4becafc2a..9dee90edc3 100644
--- a/src/mainboard/lenovo/t520/acpi/platform.asl
+++ b/src/mainboard/lenovo/t520/acpi/platform.asl
@@ -15,10 +15,6 @@ Method(_PTS,1)
 
 Method(_WAK,1)
 {
-	/* ME may not be up yet. */
-	\_TZ.MEB1 = 0
-	\_TZ.MEB2 = 0
-
 	/* Wake the HKEY to init BT/WWAN */
 	\_SB.PCI0.LPCB.EC.HKEY.WAKE (Arg0)
 
diff --git a/src/mainboard/lenovo/t520/dsdt.asl b/src/mainboard/lenovo/t520/dsdt.asl
index 33b6f80b17..1134782675 100644
--- a/src/mainboard/lenovo/t520/dsdt.asl
+++ b/src/mainboard/lenovo/t520/dsdt.asl
@@ -3,7 +3,6 @@
 #define THINKPAD_EC_GPE 17
 #define BRIGHTNESS_UP \_SB.PCI0.GFX0.INCB
 #define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.DECB
-#define EC_LENOVO_H8_ME_WORKAROUND 1
 
 #include <acpi/acpi.h>
 DefinitionBlock(
diff --git a/src/mainboard/lenovo/t530/acpi/platform.asl b/src/mainboard/lenovo/t530/acpi/platform.asl
index c4becafc2a..9dee90edc3 100644
--- a/src/mainboard/lenovo/t530/acpi/platform.asl
+++ b/src/mainboard/lenovo/t530/acpi/platform.asl
@@ -15,10 +15,6 @@ Method(_PTS,1)
 
 Method(_WAK,1)
 {
-	/* ME may not be up yet. */
-	\_TZ.MEB1 = 0
-	\_TZ.MEB2 = 0
-
 	/* Wake the HKEY to init BT/WWAN */
 	\_SB.PCI0.LPCB.EC.HKEY.WAKE (Arg0)
 
diff --git a/src/mainboard/lenovo/t530/dsdt.asl b/src/mainboard/lenovo/t530/dsdt.asl
index 33b6f80b17..1134782675 100644
--- a/src/mainboard/lenovo/t530/dsdt.asl
+++ b/src/mainboard/lenovo/t530/dsdt.asl
@@ -3,7 +3,6 @@
 #define THINKPAD_EC_GPE 17
 #define BRIGHTNESS_UP \_SB.PCI0.GFX0.INCB
 #define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.DECB
-#define EC_LENOVO_H8_ME_WORKAROUND 1
 
 #include <acpi/acpi.h>
 DefinitionBlock(
diff --git a/src/mainboard/lenovo/x131e/acpi/platform.asl b/src/mainboard/lenovo/x131e/acpi/platform.asl
index c4becafc2a..9dee90edc3 100644
--- a/src/mainboard/lenovo/x131e/acpi/platform.asl
+++ b/src/mainboard/lenovo/x131e/acpi/platform.asl
@@ -15,10 +15,6 @@ Method(_PTS,1)
 
 Method(_WAK,1)
 {
-	/* ME may not be up yet. */
-	\_TZ.MEB1 = 0
-	\_TZ.MEB2 = 0
-
 	/* Wake the HKEY to init BT/WWAN */
 	\_SB.PCI0.LPCB.EC.HKEY.WAKE (Arg0)
 
diff --git a/src/mainboard/lenovo/x131e/dsdt.asl b/src/mainboard/lenovo/x131e/dsdt.asl
index 34391416f3..dc9878030e 100644
--- a/src/mainboard/lenovo/x131e/dsdt.asl
+++ b/src/mainboard/lenovo/x131e/dsdt.asl
@@ -3,7 +3,6 @@
 #define THINKPAD_EC_GPE 22
 #define BRIGHTNESS_UP \_SB.PCI0.GFX0.INCB
 #define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.DECB
-#define EC_LENOVO_H8_ME_WORKAROUND 1
 
 #include <acpi/acpi.h>
 DefinitionBlock(
diff --git a/src/mainboard/lenovo/x1_carbon_gen1/acpi/platform.asl b/src/mainboard/lenovo/x1_carbon_gen1/acpi/platform.asl
index c4becafc2a..9dee90edc3 100644
--- a/src/mainboard/lenovo/x1_carbon_gen1/acpi/platform.asl
+++ b/src/mainboard/lenovo/x1_carbon_gen1/acpi/platform.asl
@@ -15,10 +15,6 @@ Method(_PTS,1)
 
 Method(_WAK,1)
 {
-	/* ME may not be up yet. */
-	\_TZ.MEB1 = 0
-	\_TZ.MEB2 = 0
-
 	/* Wake the HKEY to init BT/WWAN */
 	\_SB.PCI0.LPCB.EC.HKEY.WAKE (Arg0)
 
diff --git a/src/mainboard/lenovo/x1_carbon_gen1/dsdt.asl b/src/mainboard/lenovo/x1_carbon_gen1/dsdt.asl
index 6838b5e9a6..18a47960f4 100644
--- a/src/mainboard/lenovo/x1_carbon_gen1/dsdt.asl
+++ b/src/mainboard/lenovo/x1_carbon_gen1/dsdt.asl
@@ -3,7 +3,6 @@
 #define THINKPAD_EC_GPE 17
 #define BRIGHTNESS_UP \_SB.PCI0.GFX0.INCB
 #define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.DECB
-#define EC_LENOVO_H8_ME_WORKAROUND 1
 #define EC_LENOVO_H8_ALT_FN_F2F3_LAYOUT 1
 
 #include <acpi/acpi.h>
diff --git a/src/mainboard/lenovo/x201/acpi/platform.asl b/src/mainboard/lenovo/x201/acpi/platform.asl
index f17adafc88..a238248886 100644
--- a/src/mainboard/lenovo/x201/acpi/platform.asl
+++ b/src/mainboard/lenovo/x201/acpi/platform.asl
@@ -15,10 +15,6 @@ Method(_PTS,1)
 
 Method(_WAK,1)
 {
-	/* ME may not be up yet. */
-	\_TZ.MEB1 = 0
-	\_TZ.MEB2 = 0
-
 	/* Wake the HKEY to init BT/WWAN */
 	\_SB.PCI0.LPCB.EC.HKEY.WAKE (Arg0)
 
diff --git a/src/mainboard/lenovo/x201/dsdt.asl b/src/mainboard/lenovo/x201/dsdt.asl
index 42a10e605c..e2571f60c7 100644
--- a/src/mainboard/lenovo/x201/dsdt.asl
+++ b/src/mainboard/lenovo/x201/dsdt.asl
@@ -3,7 +3,6 @@
 #define THINKPAD_EC_GPE 17
 #define BRIGHTNESS_UP \_SB.PCI0.GFX0.INCB
 #define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.DECB
-#define EC_LENOVO_H8_ME_WORKAROUND 1
 
 #include <acpi/acpi.h>
 DefinitionBlock(
diff --git a/src/mainboard/lenovo/x220/acpi/platform.asl b/src/mainboard/lenovo/x220/acpi/platform.asl
index c4becafc2a..9dee90edc3 100644
--- a/src/mainboard/lenovo/x220/acpi/platform.asl
+++ b/src/mainboard/lenovo/x220/acpi/platform.asl
@@ -15,10 +15,6 @@ Method(_PTS,1)
 
 Method(_WAK,1)
 {
-	/* ME may not be up yet. */
-	\_TZ.MEB1 = 0
-	\_TZ.MEB2 = 0
-
 	/* Wake the HKEY to init BT/WWAN */
 	\_SB.PCI0.LPCB.EC.HKEY.WAKE (Arg0)
 
diff --git a/src/mainboard/lenovo/x220/dsdt.asl b/src/mainboard/lenovo/x220/dsdt.asl
index 33b6f80b17..1134782675 100644
--- a/src/mainboard/lenovo/x220/dsdt.asl
+++ b/src/mainboard/lenovo/x220/dsdt.asl
@@ -3,7 +3,6 @@
 #define THINKPAD_EC_GPE 17
 #define BRIGHTNESS_UP \_SB.PCI0.GFX0.INCB
 #define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.DECB
-#define EC_LENOVO_H8_ME_WORKAROUND 1
 
 #include <acpi/acpi.h>
 DefinitionBlock(
diff --git a/src/mainboard/lenovo/x230/acpi/platform.asl b/src/mainboard/lenovo/x230/acpi/platform.asl
index c4becafc2a..9dee90edc3 100644
--- a/src/mainboard/lenovo/x230/acpi/platform.asl
+++ b/src/mainboard/lenovo/x230/acpi/platform.asl
@@ -15,10 +15,6 @@ Method(_PTS,1)
 
 Method(_WAK,1)
 {
-	/* ME may not be up yet. */
-	\_TZ.MEB1 = 0
-	\_TZ.MEB2 = 0
-
 	/* Wake the HKEY to init BT/WWAN */
 	\_SB.PCI0.LPCB.EC.HKEY.WAKE (Arg0)
 
diff --git a/src/mainboard/lenovo/x230/dsdt.asl b/src/mainboard/lenovo/x230/dsdt.asl
index 33b6f80b17..1134782675 100644
--- a/src/mainboard/lenovo/x230/dsdt.asl
+++ b/src/mainboard/lenovo/x230/dsdt.asl
@@ -3,7 +3,6 @@
 #define THINKPAD_EC_GPE 17
 #define BRIGHTNESS_UP \_SB.PCI0.GFX0.INCB
 #define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.DECB
-#define EC_LENOVO_H8_ME_WORKAROUND 1
 
 #include <acpi/acpi.h>
 DefinitionBlock(

From 722c9314c7e1f66ff15b852b293a3fc5a84de25e Mon Sep 17 00:00:00 2001
From: Hualin Wei <weihualin@huaqin.corp-partner.google.com>
Date: Mon, 14 Jul 2025 11:54:13 +0800
Subject: [PATCH 1563/3886] mb/google/dedede/var/awasuki: Add 2 HYNIX modules
 to RAM id table

Add HYNIX H54G46CYRBX267 as id 0, and add HYNIX H54G56CYRBX247
as id 1, resulting in the list below:

DRAM Part Name                 ID to assign
K4U6E3S4AB-MGCL                0 (0000)
K4UBE3D4AB-MGCL                1 (0001)
MT53E1G32D2NP-046 WT:B         1 (0001)
NT6AP512T32BL-J1               2 (0010)
NT6AP1024F32BL-J1              3 (0011)
CXDB4CBAM-ML-A                 2 (0010)
H54G56CYRBX247                 1 (0001)
H54G46CYRBX267                 0 (0000)

BUG=430792154
TEST=Use part_id_gen to generate related settings

Change-Id: I6ea840862b4b7b728a351425da9fc4052c201e3c
Signed-off-by: Hualin Wei <weihualin@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88419
Reviewed-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 .../google/dedede/variants/awasuki/memory/Makefile.mk         | 4 ++--
 .../dedede/variants/awasuki/memory/dram_id.generated.txt      | 2 ++
 .../google/dedede/variants/awasuki/memory/mem_parts_used.txt  | 2 ++
 3 files changed, 6 insertions(+), 2 deletions(-)

diff --git a/src/mainboard/google/dedede/variants/awasuki/memory/Makefile.mk b/src/mainboard/google/dedede/variants/awasuki/memory/Makefile.mk
index 5fc455609e..f9e8983b53 100644
--- a/src/mainboard/google/dedede/variants/awasuki/memory/Makefile.mk
+++ b/src/mainboard/google/dedede/variants/awasuki/memory/Makefile.mk
@@ -4,7 +4,7 @@
 # util/spd_tools/bin/part_id_gen JSL lp4x src/mainboard/google/dedede/variants/awasuki/memory src/mainboard/google/dedede/variants/awasuki/memory/mem_parts_used.txt
 
 SPD_SOURCES =
-SPD_SOURCES += spd/lp4x/set-1/spd-1.hex      # ID = 0(0b0000)  Parts = K4U6E3S4AB-MGCL
-SPD_SOURCES += spd/lp4x/set-1/spd-3.hex      # ID = 1(0b0001)  Parts = K4UBE3D4AB-MGCL, MT53E1G32D2NP-046 WT:B
+SPD_SOURCES += spd/lp4x/set-1/spd-1.hex      # ID = 0(0b0000)  Parts = K4U6E3S4AB-MGCL, H54G46CYRBX267
+SPD_SOURCES += spd/lp4x/set-1/spd-3.hex      # ID = 1(0b0001)  Parts = K4UBE3D4AB-MGCL, MT53E1G32D2NP-046 WT:B, H54G56CYRBX247
 SPD_SOURCES += spd/lp4x/set-1/spd-11.hex      # ID = 2(0b0010)  Parts = NT6AP512T32BL-J1, CXDB4CBAM-ML-A
 SPD_SOURCES += spd/lp4x/set-1/spd-12.hex      # ID = 3(0b0011)  Parts = NT6AP1024F32BL-J1
diff --git a/src/mainboard/google/dedede/variants/awasuki/memory/dram_id.generated.txt b/src/mainboard/google/dedede/variants/awasuki/memory/dram_id.generated.txt
index 81011e157a..5d886b66dc 100644
--- a/src/mainboard/google/dedede/variants/awasuki/memory/dram_id.generated.txt
+++ b/src/mainboard/google/dedede/variants/awasuki/memory/dram_id.generated.txt
@@ -10,3 +10,5 @@ MT53E1G32D2NP-046 WT:B         1 (0001)
 NT6AP512T32BL-J1               2 (0010)
 NT6AP1024F32BL-J1              3 (0011)
 CXDB4CBAM-ML-A                 2 (0010)
+H54G56CYRBX247                 1 (0001)
+H54G46CYRBX267                 0 (0000)
diff --git a/src/mainboard/google/dedede/variants/awasuki/memory/mem_parts_used.txt b/src/mainboard/google/dedede/variants/awasuki/memory/mem_parts_used.txt
index 21c1901980..4ef82bcdbe 100644
--- a/src/mainboard/google/dedede/variants/awasuki/memory/mem_parts_used.txt
+++ b/src/mainboard/google/dedede/variants/awasuki/memory/mem_parts_used.txt
@@ -16,3 +16,5 @@ MT53E1G32D2NP-046 WT:B
 NT6AP512T32BL-J1
 NT6AP1024F32BL-J1
 CXDB4CBAM-ML-A
+H54G56CYRBX247
+H54G46CYRBX267

From 8687b3d108180aaa6dacc0a8f20d4a8ab19a2d34 Mon Sep 17 00:00:00 2001
From: erin liang <erin.liang@lcfc.corp-partner.google.com>
Date: Tue, 8 Jul 2025 13:38:48 +0800
Subject: [PATCH 1564/3886] mb/google/trulo/var/pujjolo: Add ISH firmware
 config

Due to Pujjoquince does not have ISH, thus define bit 29 in
firmware_config to indicate ISH presence per platform.

BUG=b:417599885
BRANCH=none
TEST= Use the command ls /dev/cros_ and no cros_ish option
will appear

Change-Id: I286300eadf7991d3a30936f5904ff3eef4480039
Signed-off-by: erin liang <erin.liang@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88364
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 .../google/brya/variants/pujjolo/overridetree.cb          | 8 +++++++-
 1 file changed, 7 insertions(+), 1 deletion(-)

diff --git a/src/mainboard/google/brya/variants/pujjolo/overridetree.cb b/src/mainboard/google/brya/variants/pujjolo/overridetree.cb
index c6cce61c73..c9c551025a 100644
--- a/src/mainboard/google/brya/variants/pujjolo/overridetree.cb
+++ b/src/mainboard/google/brya/variants/pujjolo/overridetree.cb
@@ -20,6 +20,10 @@ fw_config
 		option WFC_ABSENT               0
 		option WFC_MIPI_OVTI8856        1
 	end
+	field ISH 29
+		option ISH_ABSENT	0
+		option ISH_PRESENT	1
+	end
 end
 chip soc/intel/alderlake
 
@@ -449,7 +453,9 @@ chip soc/intel/alderlake
 			chip drivers/intel/ish
 				register "add_acpi_dma_property" = "true"
 				register "firmware_name" = ""pujjolo_ish.bin""
-				device generic 0 on end
+				device generic 0 on
+					probe ISH ISH_PRESENT
+				end
 			end
 		end
 		device ref ufs on end

From e9731f89256dd98866ba0065509f67a64a49b87e Mon Sep 17 00:00:00 2001
From: Jamie Ryu <jamie.m.ryu@intel.com>
Date: Fri, 27 Jun 2025 15:34:49 -0700
Subject: [PATCH 1565/3886] soc/intel/pantherlake: Add configs for
 pre-production silicon

This patch introduces a new configuration option
`SOC_INTEL_PANTHERLAKE_PRE_PRODUCTION_SILICON` that allows users to
specify if their mainboard is using Panther Lake pre-production silicon
aka Engineering Silicon (ES) with pre-production signed ME Firmwares.
The default value is set to 'n', ensuring it is disabled unless
explicitly chosen.

BUG=b:424355826
TEST=No change in the functionality, just added new configs.

Change-Id: I8ad83b07f057a227b62e33b6c6c0f46c3952be6b
Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88218
Reviewed-by: Pranava Y N <pranavayn@google.com>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/soc/intel/pantherlake/Kconfig | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/src/soc/intel/pantherlake/Kconfig b/src/soc/intel/pantherlake/Kconfig
index 87d78b85a2..585400759c 100644
--- a/src/soc/intel/pantherlake/Kconfig
+++ b/src/soc/intel/pantherlake/Kconfig
@@ -134,6 +134,13 @@ config SOC_INTEL_PANTHERLAKE_H
 	help
 	  Choose this option if the mainboard is built using PTL-H 4Xe system-on-a-chip (SoC).
 
+config SOC_INTEL_PANTHERLAKE_PRE_PRODUCTION_SILICON
+	bool
+	default n
+	help
+	  Choose this option if your mainboard has a Panther Lake pre-production
+	  silicon and pre-production signed ME Firmwares are integrated.
+
 config SOC_INTEL_WILDCATLAKE
 	bool
 	select SOC_INTEL_PANTHERLAKE_BASE

From e7cefe4f41111fa78a43885fd18a70127ee9f24f Mon Sep 17 00:00:00 2001
From: LiLiang Chen <liliang.chen@mediatek.corp-partner.google.com>
Date: Sun, 29 Jun 2025 21:26:48 +0800
Subject: [PATCH 1566/3886] soc/mediatek/mt8196: Move srclken_rc related code
 to common

To promote code reuse and maintainability, move srclken_rc related code
to common folder.

BUG=b:379008996
BRANCH=none
TEST=build passed.

Signed-off-by: LiLiang Chen <liliang.chen@mediatek.corp-partner.google.com>
Signed-off-by: Vince Liu <vince-wl.liu@mediatek.corp-partner.google.com>
Change-Id: Ic8401f910bf37c3f413147e293d1d9274c62d8ee
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88378
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
---
 .../common/include/soc/srclken_rc_common.h    | 185 ++++++++++++++++
 src/soc/mediatek/common/srclken_rc.c          |  58 +++++
 src/soc/mediatek/mt8196/Makefile.mk           |   2 +-
 .../mediatek/mt8196/include/soc/srclken_rc.h  |  57 +----
 src/soc/mediatek/mt8196/srclken_rc.c          | 198 ++----------------
 5 files changed, 260 insertions(+), 240 deletions(-)
 create mode 100644 src/soc/mediatek/common/include/soc/srclken_rc_common.h
 create mode 100644 src/soc/mediatek/common/srclken_rc.c

diff --git a/src/soc/mediatek/common/include/soc/srclken_rc_common.h b/src/soc/mediatek/common/include/soc/srclken_rc_common.h
new file mode 100644
index 0000000000..7fbadc7eca
--- /dev/null
+++ b/src/soc/mediatek/common/include/soc/srclken_rc_common.h
@@ -0,0 +1,185 @@
+/* SPDX-License-Identifier: GPL-2.0-only OR MIT */
+
+#ifndef SOC_MEDIATEK_COMMON_SRCLKEN_RC_H
+#define SOC_MEDIATEK_COMMON_SRCLKEN_RC_H
+
+#include <stdbool.h>
+#include <stddef.h>
+#include <stdint.h>
+
+#define ACK_DELAY_US			10
+#define ACK_DELAY_TIMES			200
+/* RC_CENTRAL_CFG1 setting */
+#define RC_CENTRAL_ENABLE_VAL		1
+#define RC_CENTRAL_DISABLE_VAL		0
+
+/* register direct write */
+#define IS_SPI2PMIC_SET_CLR_VAL		0
+#define KEEP_RC_SPI_ACTIVE_VAL		1
+#define SRCLKEN_RC_EN_SEL_VAL		0
+
+/* RC_CENTRAL_CFG1 settle time setting */
+#define VCORE_SETTLE_TIME_VAL		0x7	/* ~= 200us */
+#define ULPOSC_SETTLE_TIME_VAL		0x4	/* ~= ? 150us */
+#define NON_DCXO_SETTLE_TIME_VAL	0x1	/* 2^(step+5)*0x33*30.77ns~=400us */
+#define DCXO_SETTLE_TIME_VAL		0x41	/* 2^(step+5)*0x87*30.77ns~= 1063us */
+
+/* RC_CENTRAL_CFG2[8] */
+#define SRCLKENAO_MODE			0
+#define VREQ_MODE			1
+
+/* RC_CENTRAL_CFG2[25] */
+#define RC_32K				0
+#define RC_ULPOSC1			1
+
+/* Signal Control Mode */
+#define MERGE_OR_MODE			0x0
+#define BYPASS_MODE			0x1
+#define MERGE_AND_MODE			BIT(1)
+#define BYPASS_RC_MODE			(0x2 << 1)
+#define BYPASS_OR_MODE			0x3
+#define BYPASS_OTHER_MODE		(0x3 << 1)
+#define ASYNC_MODE			BIT(3)
+#define NO_REQ				0
+#define SW_SRCLKEN_BBLPM_MSK		0x1
+#define FPM_REQ				BIT(4)
+#define BBLPM_REQ			BIT(5)
+#define SW_SRCLKEN_FPM_MSK		0x1
+
+/* use srlckenao to set vcore */
+#define SPI_TRIG_MODE			SRCLKENAO_MODE
+/* release vcore when spi request done */
+#define IS_SPI_DONE_RELEASE		0
+/* pmic spec under 200us */
+#define SPI_CLK_SRC			RC_32K
+/* RC_CENTRAL_CFG2 control mode */
+/* merge with vreq */
+#define VREQ_CTRL_M			BYPASS_MODE
+/* merge with ulposc */
+#define ULPOSC_CTRL_M_VAL		BYPASS_MODE
+/* merge with pwrap_scp */
+#define PWRAP_CTRL_M			MERGE_OR_MODE
+
+/* RC_DCXO_FPM_CFG*/
+#define MD0_SRCLKENO_0_MASK_B		0
+#define FULL_SET_HW_MODE		0
+/* RC_DCXO_FPM_CFG control mode*/
+/* merge with spm */
+#define DCXO_FPM_CTRL_MODE		(MERGE_OR_MODE | ASYNC_MODE)
+
+/* RC_CENTRAL_CFG5 */
+#define RC_SPMI_BYTE_LEN		0x1
+#define PMIC_GROUP_ID			0xB
+
+/* MXX_SRCLKEN_CFG settle time setting */
+#define CENTROL_CNT_STEP		0x3	/* Fix in 3 */
+#define DCXO_STABLE_TIME		0x70	/* ~= 700us */
+#define XO_DEFAULT_STABLE_TIME		0x29	/* ~= 400us */
+#define XO_MD0_STABLE_TIME		0x15	/* ~= 200us */
+#define XO_MD1_STABLE_TIME		0x15	/* ~= 200us */
+#define XO_MDRF_STABLE_TIME		0x3D	/* ~= 600us */
+
+enum {
+	SW_BBLPM_LOW,
+	SW_BBLPM_HIGH,
+};
+
+enum {
+	SW_FPM_LOW,
+	SW_FPM_HIGH,
+};
+
+enum {
+	DXCO_SETTLE_BLK_DIS,
+	DXCO_SETTLE_BLK_EN,
+};
+
+enum {
+	REQ_ACK_IMD_DIS,
+	REQ_ACK_IMD_EN,
+};
+
+struct rc_config {
+	bool disabled;
+	bool lpm;
+	bool hw_mode;
+};
+
+enum rc_ctrl_m {
+	HW_MODE = 0,
+	SW_MODE = 1,
+	INIT_MODE = 0xff,
+};
+
+enum {
+	SRLCKEN_RC_BRINGUP = 0,
+	SRCLKEN_RC_DISABLE,
+	SRCLKEN_RC_ENABLE,
+	SRCLKEN_RC_SKIP,
+};
+
+struct subsys_rc_con {
+	u32 dcxo_prd;
+	u32 xo_prd;
+	u32 cnt_step;
+	u32 track_en;
+	u32 req_ack_imd_en;
+	u32 xo_soc_link_en;
+	u32 sw_bblpm;
+	u32 sw_fpm;
+	u32 sw_rc;
+	u32 bypass_cmd;
+	u32 dcxo_settle_blk_en;
+};
+
+#define SUB_CTRL_CON(_id, _dcxo_prd, _xo_prd, \
+		_sw_bblpm, _sw_fpm, _sw_rc, \
+		_req_ack_imd_en, _bypass_cmd, \
+		_dcxo_settle_blk_en) \
+	[_id] = { \
+		.dcxo_prd = _dcxo_prd, \
+		.xo_prd = _xo_prd, \
+		.cnt_step = CENTROL_CNT_STEP, \
+		.track_en = 0x0, \
+		.req_ack_imd_en = _req_ack_imd_en, \
+		.xo_soc_link_en = 0x0, \
+		.sw_bblpm = _sw_bblpm, \
+		.sw_fpm = _sw_fpm, \
+		.sw_rc = _sw_rc, \
+		.bypass_cmd = _bypass_cmd, \
+		.dcxo_settle_blk_en = _dcxo_settle_blk_en, \
+	}
+
+/* Init as SW FPM mode */
+#define SUB_CTRL_CON_INIT(_id, _dcxo_prd, _xo_prd, \
+			  _req_ack_imd_en, _bypass_cmd, \
+			  _dcxo_settle_blk_en) \
+	SUB_CTRL_CON(_id, _dcxo_prd, _xo_prd, \
+		     SW_BBLPM_LOW, SW_FPM_HIGH, SW_MODE, \
+		     _req_ack_imd_en, _bypass_cmd, \
+		     _dcxo_settle_blk_en)
+
+/* Init as SW LPM mode */
+#define SUB_CTRL_CON_NO_INIT(_id, _dcxo_prd, _xo_prd, \
+			     _req_ack_imd_en, _bypass_cmd, \
+			     _dcxo_settle_blk_en) \
+	SUB_CTRL_CON(_id, _dcxo_prd, _xo_prd, \
+		     SW_BBLPM_LOW, SW_FPM_LOW, SW_MODE, \
+		     _req_ack_imd_en, _bypass_cmd, \
+		     _dcxo_settle_blk_en)
+
+/* Normal init, SW FPM mode */
+#define SUB_CTRL_CON_EN(_id, _xo_prd, _req_ack_imd_en) \
+	SUB_CTRL_CON_INIT(_id, \
+			  DCXO_STABLE_TIME, _xo_prd, \
+			  _req_ack_imd_en, 0, DXCO_SETTLE_BLK_EN)
+
+extern const struct rc_config rc_config[];
+extern const size_t rc_config_num;
+
+void rc_init_subsys_hw_mode(void);
+void rc_init_subsys_lpm(void);
+
+int srclken_rc_init(void);
+
+#endif /* SOC_MEDIATEK_COMMON_SRCLKEN_RC_H */
diff --git a/src/soc/mediatek/common/srclken_rc.c b/src/soc/mediatek/common/srclken_rc.c
new file mode 100644
index 0000000000..d0a0dab36b
--- /dev/null
+++ b/src/soc/mediatek/common/srclken_rc.c
@@ -0,0 +1,58 @@
+/* SPDX-License-Identifier: GPL-2.0-only OR MIT */
+
+#include <assert.h>
+#include <console/console.h>
+#include <delay.h>
+#include <device/mmio.h>
+#include <soc/addressmap.h>
+#include <soc/clkbuf_ctl.h>
+#include <soc/pmif.h>
+#include <soc/pmif_common.h>
+#include <soc/spmi.h>
+#include <soc/srclken_rc.h>
+#include <soc/srclken_rc_common.h>
+#include <timer.h>
+
+/* RC initial flow and relative setting */
+static void rc_ctrl_mode_switch(enum chn_id id, enum rc_ctrl_m mode)
+{
+	assert(id < ARRAY_SIZE(rc_regs->rc_mxx_srclken_cfg));
+	int cfg = (mode == SW_MODE);
+
+	SET32_BITFIELDS(&rc_regs->rc_mxx_srclken_cfg[id], SW_SRCLKEN_RC, cfg);
+
+	printk(BIOS_INFO, "M0%d: 0x%x\n", id, read32(&rc_regs->rc_mxx_srclken_cfg[id]));
+}
+
+/* RC subsys FPM control */
+static void rc_ctrl_fpm_switch(enum chn_id id, u32 mode)
+{
+	assert(id < ARRAY_SIZE(rc_regs->rc_mxx_srclken_cfg));
+	assert(mode == SW_FPM_HIGH || mode == SW_FPM_LOW);
+
+	int fpm = (mode == SW_FPM_HIGH) ? 1 : 0;
+	SET32_BITFIELDS(&rc_regs->rc_mxx_srclken_cfg[id], SW_SRCLKEN_FPM, fpm);
+
+	printk(BIOS_INFO, "M0%d FPM SWITCH: %#x\n", id,
+	       read32(&rc_regs->rc_mxx_srclken_cfg[id]));
+}
+
+void rc_init_subsys_hw_mode(void)
+{
+	int chn_n;
+
+	for (chn_n = 0; chn_n < MAX_CHN_NUM; chn_n++) {
+		if (rc_config[chn_n].hw_mode)
+			rc_ctrl_mode_switch(chn_n, HW_MODE);
+	}
+}
+
+void rc_init_subsys_lpm(void)
+{
+	int chn_n;
+
+	for (chn_n = 0; chn_n < MAX_CHN_NUM; chn_n++) {
+		if (rc_config[chn_n].lpm)
+			rc_ctrl_fpm_switch(chn_n, SW_FPM_LOW);
+	}
+}
diff --git a/src/soc/mediatek/mt8196/Makefile.mk b/src/soc/mediatek/mt8196/Makefile.mk
index 729f73f638..9426d157db 100644
--- a/src/soc/mediatek/mt8196/Makefile.mk
+++ b/src/soc/mediatek/mt8196/Makefile.mk
@@ -49,7 +49,7 @@ romstage-y += ../common/pmif_clk.c pmif_clk.c
 romstage-y += ../common/pmif.c pmif_init.c
 romstage-y += ../common/rtc.c ../common/rtc_osc_init.c
 romstage-y += ../common/pmif_spmi_v2.c pmif_spmi.c
-romstage-y += srclken_rc.c
+romstage-y += ../common/srclken_rc.c srclken_rc.c
 romstage-y += thermal.c
 romstage-y += thermal_sram.c
 
diff --git a/src/soc/mediatek/mt8196/include/soc/srclken_rc.h b/src/soc/mediatek/mt8196/include/soc/srclken_rc.h
index af880d7faa..387526013c 100644
--- a/src/soc/mediatek/mt8196/include/soc/srclken_rc.h
+++ b/src/soc/mediatek/mt8196/include/soc/srclken_rc.h
@@ -3,6 +3,9 @@
 #ifndef __SOC_MEDIATEK_MT8196_INCLUDE_SOC_SRCLKEN_RC_H__
 #define __SOC_MEDIATEK_MT8196_INCLUDE_SOC_SRCLKEN_RC_H__
 
+#include <soc/addressmap.h>
+#include <soc/srclken_rc_common.h>
+
 /* Channel id: Update this enum for porting */
 enum chn_id {
 	CHN_SUSPEND = 0,
@@ -187,58 +190,6 @@ DEFINE_BIT(BBLPM_ACK, 3)
 DEFINE_BITFIELD(BYPASS_DCXO_VOTE_H, 31, 16)
 DEFINE_BITFIELD(BYPASS_DCXO_VOTE_L, 15, 0)
 
-enum {
-	SW_SRCLKEN_FPM_MSK = 0x1,
-	SW_SRCLKEN_BBLPM_MSK = 0x1,
-};
-
-/* RC_CENTRAL_CFG2[8] */
-#define SRCLKENAO_MODE			0
-#define VREQ_MODE			1
-
-/* RC_CENTRAL_CFG2[25] */
-#define RC_32K				0
-#define RC_ULPOSC1			1
-
-/* Signal Control Mode */
-#define MERGE_OR_MODE			0x0
-#define BYPASS_MODE			0x1
-#define MERGE_AND_MODE			BIT(1)
-#define BYPASS_RC_MODE			(0x2 << 1)
-#define BYPASS_OR_MODE			0x3
-#define BYPASS_OTHER_MODE		(0x3 << 1)
-#define ASYNC_MODE			BIT(3)
-
-#define NO_REQ				0
-#define FPM_REQ				BIT(4)
-#define BBLPM_REQ			BIT(5)
-
-enum rc_ctrl_m {
-	HW_MODE = 0,
-	SW_MODE = 1,
-};
-
-enum {
-	SRLCKEN_RC_BRINGUP = 0,
-	SRCLKEN_RC_DISABLE,
-	SRCLKEN_RC_ENABLE,
-	SRCLKEN_RC_SKIP,
-};
-
-struct subsys_rc_con {
-	u32 dcxo_prd;
-	u32 xo_prd;
-	u32 cnt_step;
-	u32 track_en;
-	u32 req_ack_imd_en;
-	u32 xo_soc_link_en;
-	u32 sw_bblpm;
-	u32 sw_fpm;
-	u32 sw_rc;
-	u32 bypass_cmd;
-	u32 dcxo_settle_blk_en;
-};
-
-int srclken_rc_init(void);
+static struct mtk_rc_regs *const rc_regs = (void *)RC_BASE;
 
 #endif
diff --git a/src/soc/mediatek/mt8196/srclken_rc.c b/src/soc/mediatek/mt8196/srclken_rc.c
index 412858c959..678c3d7250 100644
--- a/src/soc/mediatek/mt8196/srclken_rc.c
+++ b/src/soc/mediatek/mt8196/srclken_rc.c
@@ -12,53 +12,8 @@
 #include <soc/srclken_rc.h>
 #include <timer.h>
 
-static struct mtk_rc_regs *rc_regs = (struct mtk_rc_regs *)RC_BASE;
-
-#define ACK_DELAY_US			10
-#define ACK_DELAY_TIMES			200
-
-/* RC_CENTRAL_CFG1 setting */
-#define RC_CENTRAL_ENABLE_VAL		1
-#define RC_CENTRAL_DISABLE_VAL		0
-
-/* register direct write */
-#define IS_SPI2PMIC_SET_CLR_VAL		0
-#define KEEP_RC_SPI_ACTIVE_VAL		1
-#define SRCLKEN_RC_EN_SEL_VAL		0
-
-/* RC_CENTRAL_CFG1 settle time setting */
-#define VCORE_SETTLE_TIME_VAL		0x7	/* ~= 200us */
-#define ULPOSC_SETTLE_TIME_VAL		0x4	/* ~= ? 150us */
-#define NON_DCXO_SETTLE_TIME_VAL	0x1	/* 2^(step+5)*0x33*30.77ns ~= 400us */
-#define DCXO_SETTLE_TIME_VAL		0x41	/* 2^(step+5)*0x87*30.77ns ~= 1063us */
-
-/* RC_CENTRAL_CFG2 setting */
-/* use srlckenao to set vcore */
-#define SPI_TRIG_MODE			SRCLKENAO_MODE
-/* release vcore when spi request done */
-#define IS_SPI_DONE_RELEASE		0
-/* pmic spec under 200us */
-#define SPI_CLK_SRC			RC_32K
-/* RC_CENTRAL_CFG2 control mode */
 /* merge with spm */
 #define SRCLKENO_0_CTRL_M		BYPASS_MODE
-/* merge with vreq */
-#define VREQ_CTRL_M			BYPASS_MODE
-/* merge with ulposc */
-#define ULPOSC_CTRL_M_VAL		BYPASS_MODE
-/* merge with pwrap_scp */
-#define PWRAP_CTRL_M			MERGE_OR_MODE
-
-/* RC_DCXO_FPM_CFG*/
-#define MD0_SRCLKENO_0_MASK_B		0	/* md0 control by pmrc */
-#define FULL_SET_HW_MODE		0	/* dcxo mode use pmrc_en */
-/* RC_DCXO_FPM_CFG control mode*/
-/* merge with spm */
-#define DCXO_FPM_CTRL_MODE		(MERGE_OR_MODE | ASYNC_MODE)
-
-/* RC_CENTRAL_CFG5 */
-#define RC_SPMI_BYTE_LEN		0x1	/* 0: 2bytes, 1: 2 * 2bytes */
-#define PMIC_GROUP_ID			0xB
 
 /* pmrc_en address */
 /* default use this reg direct write */
@@ -66,68 +21,6 @@ static struct mtk_rc_regs *rc_regs = (struct mtk_rc_regs *)RC_BASE;
 #define PMRC_CON0_SET			0x198
 #define PMRC_CON0_CLR			0x19A
 
-enum {
-	SW_BBLPM_LOW,
-	SW_BBLPM_HIGH,
-};
-
-enum {
-	SW_FPM_LOW,
-	SW_FPM_HIGH,
-};
-
-enum {
-	DXCO_SETTLE_BLK_DIS,
-	DXCO_SETTLE_BLK_EN,
-};
-
-enum {
-	REQ_ACK_IMD_DIS,
-	REQ_ACK_IMD_EN,
-};
-
-#define SUB_CTRL_CON(_id, _dcxo_prd, _xo_prd, \
-		     _sw_bblpm, _sw_fpm, _sw_rc, \
-		     _req_ack_imd_en, _bypass_cmd, \
-		     _dcxo_settle_blk_en) \
-	[_id] = { \
-		.dcxo_prd = _dcxo_prd, \
-		.xo_prd = _xo_prd, \
-		.cnt_step = CENTROL_CNT_STEP, \
-		.track_en = 0, \
-		.req_ack_imd_en = _req_ack_imd_en, \
-		.xo_soc_link_en = 0, \
-		.sw_bblpm = _sw_bblpm, \
-		.sw_fpm = _sw_fpm, \
-		.sw_rc = _sw_rc, \
-		.bypass_cmd = _bypass_cmd, \
-		.dcxo_settle_blk_en = _dcxo_settle_blk_en, \
-	}
-
-/* Init as SW FPM mode */
-#define SUB_CTRL_CON_INIT(_id, _dcxo_prd, _xo_prd, \
-			  _req_ack_imd_en, _bypass_cmd, \
-			  _dcxo_settle_blk_en) \
-	SUB_CTRL_CON(_id, _dcxo_prd, _xo_prd, \
-		     SW_BBLPM_LOW, SW_FPM_HIGH, SW_MODE, \
-		     _req_ack_imd_en, _bypass_cmd, \
-		     _dcxo_settle_blk_en)
-
-/* Init as SW LPM mode */
-#define SUB_CTRL_CON_NO_INIT(_id, _dcxo_prd, _xo_prd, \
-			     _req_ack_imd_en, _bypass_cmd, \
-			     _dcxo_settle_blk_en) \
-	SUB_CTRL_CON(_id, _dcxo_prd, _xo_prd, \
-		     SW_BBLPM_LOW, SW_FPM_LOW, SW_MODE, \
-		     _req_ack_imd_en, _bypass_cmd, \
-		     _dcxo_settle_blk_en)
-
-/* Normal init, SW FPM mode */
-#define SUB_CTRL_CON_EN(_id, _xo_prd, _req_ack_imd_en) \
-	SUB_CTRL_CON_INIT(_id, \
-			  DCXO_STABLE_TIME, _xo_prd, \
-			  _req_ack_imd_en, 0, DXCO_SETTLE_BLK_EN)
-
 /* XO/DCXO settle time=0, bypass cmd */
 #define SUB_CTRL_CON_DIS(_id) \
 	SUB_CTRL_CON_INIT(_id, \
@@ -141,14 +34,7 @@ enum {
 			     REQ_ACK_IMD_EN, 0, DXCO_SETTLE_BLK_EN)
 
 /* Porting starting from here */
-/* MXX_SRCLKEN_CFG settle time setting */
-#define CENTROL_CNT_STEP		0x3	/* Fix in 3 */
-#define DCXO_STABLE_TIME		0x70	/* ~= 700us */
-#define XO_DEFAULT_STABLE_TIME		0x29	/* ~= 400us */
-#define XO_MD0_STABLE_TIME		0x15	/* ~= 200us */
-#define XO_MD1_STABLE_TIME		0x15	/* ~= 200us */
 #define XO_MD2_STABLE_TIME		0x33	/* ~= 500us */
-#define XO_MDRF_STABLE_TIME		0x3D	/* ~= 600us */
 #define VCORE_STABLE_TIME		0x15	/* ~= 200us */
 
 /* SUBSYS_INTF_CFG_FPM */
@@ -167,25 +53,21 @@ enum {
 #define SUBSYS_EN_H			0x0000
 
 /* First try to switch fpm. After polling ack done, switch to HW mode */
-static const struct {
-	bool disabled;
-	bool lpm;
-	bool hw_mode;
-} rc_config[MAX_CHN_NUM] = {
-	[CHN_SUSPEND] = { .lpm = false, .hw_mode = true },
-	[CHN_MD1] = { .lpm = false, .hw_mode = true },
-	[CHN_MD2] = { .lpm = false, .hw_mode = true },
-	[CHN_MD3] = { .lpm = false, .hw_mode = true },
-	[CHN_MDRF] = { .lpm = false, .hw_mode = true },
-	[CHN_MMWAVE] = { .lpm = false, .hw_mode = true },
+const struct rc_config rc_config[MAX_CHN_NUM] = {
+	[CHN_SUSPEND] = { .hw_mode = true },
+	[CHN_MD1] = { .hw_mode = true },
+	[CHN_MD2] = { .hw_mode = true },
+	[CHN_MD3] = { .hw_mode = true },
+	[CHN_MDRF] = { .hw_mode = true },
+	[CHN_MMWAVE] = { .hw_mode = true },
 	[CHN_GPS] = { .lpm = true, .hw_mode = true },
-	[CHN_PCIE_CONN1] = { .lpm = false, .hw_mode = true },
-	[CHN_VCORE] = { .lpm = true, .hw_mode = false },
+	[CHN_PCIE_CONN1] = { .hw_mode = true },
+	[CHN_VCORE] = { .lpm = true },
 	[CHN_CONN_MCU] = { .lpm = true, .hw_mode = true },
 	[CHN_COANT] = { .lpm = true, .hw_mode = true },
 	[CHN_NFC_CONN2] = { .lpm = true, .hw_mode = true },
-	[CHN_SUSPEND2] = { .lpm = false, .hw_mode = true },
-	[CHN_UFS_VREQ] = { .lpm = false, .hw_mode = true },
+	[CHN_SUSPEND2] = { .hw_mode = true },
+	[CHN_UFS_VREQ] = { .hw_mode = true },
 	[CHN_DCXO_L] = { .disabled = true },
 	[CHN_DCXO_H] = { .disabled = true },
 	[CHN_UFS_2] = {},
@@ -206,7 +88,7 @@ static const struct {
 	[CHN_RSV9] = {},
 };
 
-static const struct subsys_rc_con rc_ctrl[MAX_CHN_NUM] = {
+const struct subsys_rc_con rc_ctrl[MAX_CHN_NUM] = {
 	SUB_CTRL_CON_EN(CHN_SUSPEND, XO_DEFAULT_STABLE_TIME, REQ_ACK_IMD_EN),
 	/* CFG[2] = 0x1 for bypass waiting DCXO settle time */
 	/* Usually also need to set CFG6_2 not involve FPM vote */
@@ -296,38 +178,6 @@ static void rc_dump_reg_info(void)
 	printk(BIOS_INFO, "RC_PI_PO_STA:%#x\n", read32(&rc_regs->rc_pi_po_sta));
 }
 
-/* RC initial flow and relative setting */
-static void rc_ctrl_mode_switch(enum chn_id id, enum rc_ctrl_m mode)
-{
-	assert(id < MAX_CHN_NUM);
-
-	switch (mode) {
-	case SW_MODE:
-		SET32_BITFIELDS(&rc_regs->rc_mxx_srclken_cfg[id], SW_SRCLKEN_RC, 1);
-		break;
-	case HW_MODE:
-		SET32_BITFIELDS(&rc_regs->rc_mxx_srclken_cfg[id], SW_SRCLKEN_RC, 0);
-		break;
-	default:
-		return;
-	}
-
-	printk(BIOS_INFO, "M0%d: %#x\n", id, read32(&rc_regs->rc_mxx_srclken_cfg[id]));
-}
-
-/* RC subsys FPM control*/
-static void rc_ctrl_fpm_switch(enum chn_id id, u32 mode)
-{
-	assert(id < MAX_CHN_NUM);
-	assert(mode == SW_FPM_HIGH || mode == SW_FPM_LOW);
-
-	int fpm = (mode == SW_FPM_HIGH) ? 1 : 0;
-	SET32_BITFIELDS(&rc_regs->rc_mxx_srclken_cfg[id], SW_SRCLKEN_FPM, fpm);
-
-	printk(BIOS_INFO, "M0%d FPM SWITCH: %#x\n", id,
-	       read32(&rc_regs->rc_mxx_srclken_cfg[id]));
-}
-
 static void rc_ctrl_mode_init(void)
 {
 	u32 ch;
@@ -352,30 +202,6 @@ static void rc_ctrl_mode_init(void)
 	}
 }
 
-static void rc_init_subsys_lpm(void)
-{
-	u32 ch;
-
-	for (ch = 0; ch < MAX_CHN_NUM; ch++) {
-		if (rc_config[ch].disabled)
-			continue;
-		if (rc_config[ch].lpm)
-			rc_ctrl_fpm_switch(ch, SW_FPM_LOW);
-	}
-}
-
-static void rc_init_subsys_hw_mode(void)
-{
-	u32 ch;
-
-	for (ch = 0; ch < MAX_CHN_NUM; ch++) {
-		if (rc_config[ch].disabled)
-			continue;
-		if (rc_config[ch].hw_mode)
-			rc_ctrl_mode_switch(ch, HW_MODE);
-	}
-}
-
 static int polling_rc_chn_ack(enum chn_id id, u32 mask, u32 value)
 {
 	if (!retry(ACK_DELAY_TIMES,

From 626fd50a94453004c969f0590436456e3d5f7557 Mon Sep 17 00:00:00 2001
From: Bob Moragues <moragues@google.com>
Date: Wed, 9 Jul 2025 14:29:57 +0000
Subject: [PATCH 1567/3886] mb/google/fatcat/var/kinmen: Enable ISH

BUG=b:415605634
TEST=test build
BRANCH=none

Change-Id: I6110b2f2b0af20740f4ada61bbc1691a8bcc8bc9
Signed-off-by: Bob Moragues <moragues@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88371
Reviewed-by: YH Lin <yueherngl@google.com>
Reviewed-by: Yuval Peress <peress@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
---
 .../google/fatcat/variants/kinmen/overridetree.cb          | 7 ++++++-
 1 file changed, 6 insertions(+), 1 deletion(-)

diff --git a/src/mainboard/google/fatcat/variants/kinmen/overridetree.cb b/src/mainboard/google/fatcat/variants/kinmen/overridetree.cb
index 3fc3d28ff5..d3025dd8c6 100644
--- a/src/mainboard/google/fatcat/variants/kinmen/overridetree.cb
+++ b/src/mainboard/google/fatcat/variants/kinmen/overridetree.cb
@@ -147,7 +147,12 @@ chip soc/intel/pantherlake
 			end
 		end
 
-		# ToDo: enable ISH b/415605634
+		device ref ish on
+			chip drivers/intel/ish
+				register "add_acpi_dma_property" = "true"
+				device generic 0 on end
+			end
+		end
 
 		device ref xhci on
 			chip drivers/usb/acpi

From 8d9e18a122e10193cc7ab50255c3507748601fc6 Mon Sep 17 00:00:00 2001
From: Benjamin Doron <benjamin.doron@9elements.com>
Date: Sat, 12 Jul 2025 16:06:58 -0400
Subject: [PATCH 1568/3886] payloads/edk2: Indicate whether edk2-platforms is
 available

This allows EDK2 build files to decide whether these modules should be
built.

Change-Id: I12dc346d17ab0f963dedd5560b66b96210a4ec48
Signed-off-by: Benjamin Doron <benjamin.doron@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88428
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
---
 payloads/external/edk2/Makefile | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/payloads/external/edk2/Makefile b/payloads/external/edk2/Makefile
index d329b95b2a..bebd92b0f9 100644
--- a/payloads/external/edk2/Makefile
+++ b/payloads/external/edk2/Makefile
@@ -8,6 +8,7 @@ export WORKSPACE := $(CURDIR)/workspace
 export EDK2_PATH := $(WORKSPACE)/$(word 3,$(subst /, ,$(CONFIG_EDK2_REPOSITORY)))
 
 ifeq ($(CONFIG_EDK2_USE_EDK2_PLATFORMS),y)
+BUILD_STR += -D USE_EDK2_PLATFORMS=TRUE
 export EDK2_PLATFORMS_PATH := $(WORKSPACE)/edk2-platforms
 export PACKAGES_PATH := $(EDK2_PATH):\
 			$(EDK2_PLATFORMS_PATH)/Platform/Intel:\
@@ -26,7 +27,7 @@ endif
 OBJCOPY = $(GCC_PREFIX)objcopy
 
 ifeq ($(CONFIG_EDK2_UEFIPAYLOAD),y)
-BUILD_STR = -p UefiPayloadPkg/UefiPayloadPkg.dsc
+BUILD_STR += -p UefiPayloadPkg/UefiPayloadPkg.dsc
 endif
 BUILD_STR += -t COREBOOT
 BUILD_STR += -D BOOTLOADER=COREBOOT

From 9e5234feeed8760ee01d088f9cfc8cfda8cff8ab Mon Sep 17 00:00:00 2001
From: Benjamin Doron <benjamin.doron@9elements.com>
Date: Mon, 14 Jul 2025 13:51:23 -0400
Subject: [PATCH 1569/3886] payloads/external/edk2: Drop our toolchain override

It's no longer maintained here other than to address specific issues,
and it prevents us from benefiting from upstream changes. Already,
switching to the GCC toolchain saves 5-10 KiB.

Use the GCC toolchain over the backwards-compatible GCC5 one, since the
latter is being deprecated, and the former landed a few years ago,
in edk2-stable202305.

Change-Id: I47e47592ea29f5a09790b284378f28385faf29f9
Signed-off-by: Benjamin Doron <benjamin.doron@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88429
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 payloads/external/edk2/Makefile      |  18 +--
 payloads/external/edk2/tools_def.txt | 183 ---------------------------
 2 files changed, 7 insertions(+), 194 deletions(-)
 delete mode 100644 payloads/external/edk2/tools_def.txt

diff --git a/payloads/external/edk2/Makefile b/payloads/external/edk2/Makefile
index bebd92b0f9..f16aefd053 100644
--- a/payloads/external/edk2/Makefile
+++ b/payloads/external/edk2/Makefile
@@ -29,7 +29,7 @@ OBJCOPY = $(GCC_PREFIX)objcopy
 ifeq ($(CONFIG_EDK2_UEFIPAYLOAD),y)
 BUILD_STR += -p UefiPayloadPkg/UefiPayloadPkg.dsc
 endif
-BUILD_STR += -t COREBOOT
+BUILD_STR += -t GCC
 BUILD_STR += -D BOOTLOADER=COREBOOT
 ifneq ($(V),1)
 BUILD_STR += -q
@@ -285,12 +285,8 @@ prep: $(EDK2_PATH) $(EDK2_PLATFORMS_PATH) clean checktools logo gop_driver
 	cd $(WORKSPACE); \
 		source $(EDK2_PATH)/edksetup.sh; \
 		unset CC; $(MAKE) -C $(EDK2_PATH)/BaseTools 2>&1; \
-		grep -q "COREBOOT" $(EDK2_PATH)/Conf/tools_def.txt; \
-		if [ $$? -ne 0 ]; then \
-			cat ../tools_def.txt >> $(EDK2_PATH)/Conf/tools_def.txt; \
-		fi; \
 
-$(WORKSPACE)/Build/UefiPayloadPkgX64/$(RELEASE_STR)_COREBOOT/FV/UEFIPAYLOAD.fd: \
+$(WORKSPACE)/Build/UefiPayloadPkgX64/$(RELEASE_STR)_GCC/FV/UEFIPAYLOAD.fd: \
 	prep print
 	cd $(WORKSPACE); \
 		source $(EDK2_PATH)/edksetup.sh; \
@@ -315,7 +311,7 @@ $(WORKSPACE)/Build/UefiPayloadPkgX64/UniversalPayload.elf: \
 		fi
 		echo "Success!"; \
 
-$(WORKSPACE)/Build/UefiPayloadPkgX64/$(RELEASE_STR)_COREBOOT/IA32/UefiPayloadPkg/ShimLayer/ShimLayer/DEBUG/ShimLayer.dll: \
+$(WORKSPACE)/Build/UefiPayloadPkgX64/$(RELEASE_STR)_GCC/IA32/UefiPayloadPkg/ShimLayer/ShimLayer/DEBUG/ShimLayer.dll: \
 		$(WORKSPACE)/Build/UefiPayloadPkgX64/UniversalPayload.elf prep
 	cd $(WORKSPACE)/Build/UefiPayloadPkgX64 && \
 		$(OBJCOPY) -I binary UniversalPayload.elf -O elf32-i386 -B i386 \
@@ -327,12 +323,12 @@ $(WORKSPACE)/Build/UefiPayloadPkgX64/$(RELEASE_STR)_COREBOOT/IA32/UefiPayloadPkg
 			-t COREBOOT -D BOOTLOADER=COREBOOT -D SHIMLAYER=TRUE \
 			-y $(WORKSPACE)/Build/UefiPayloadPkgX64/ShimLayer.txt
 
-UefiPayloadPkg: $(WORKSPACE)/Build/UefiPayloadPkgX64/$(RELEASE_STR)_COREBOOT/FV/UEFIPAYLOAD.fd
-	mv $(WORKSPACE)/Build/UefiPayloadPkgX64/$(RELEASE_STR)_COREBOOT/FV/UEFIPAYLOAD.fd \
+UefiPayloadPkg: $(WORKSPACE)/Build/UefiPayloadPkgX64/$(RELEASE_STR)_GCC/FV/UEFIPAYLOAD.fd
+	mv $(WORKSPACE)/Build/UefiPayloadPkgX64/$(RELEASE_STR)_GCC/FV/UEFIPAYLOAD.fd \
 		../../../build/UEFIPAYLOAD.fd
 
-UniversalPayload: $(WORKSPACE)/Build/UefiPayloadPkgX64/$(RELEASE_STR)_COREBOOT/IA32/UefiPayloadPkg/ShimLayer/ShimLayer/DEBUG/ShimLayer.dll
-	mv $(WORKSPACE)/Build/UefiPayloadPkgX64/$(RELEASE_STR)_COREBOOT/IA32/UefiPayloadPkg/ShimLayer/ShimLayer/DEBUG/ShimLayer.dll \
+UniversalPayload: $(WORKSPACE)/Build/UefiPayloadPkgX64/$(RELEASE_STR)_GCC/IA32/UefiPayloadPkg/ShimLayer/ShimLayer/DEBUG/ShimLayer.dll
+	mv $(WORKSPACE)/Build/UefiPayloadPkgX64/$(RELEASE_STR)_GCC/IA32/UefiPayloadPkg/ShimLayer/ShimLayer/DEBUG/ShimLayer.dll \
 		../../../build/ShimmedUniversalPayload.elf
 
 clean:
diff --git a/payloads/external/edk2/tools_def.txt b/payloads/external/edk2/tools_def.txt
deleted file mode 100644
index 69b7933a66..0000000000
--- a/payloads/external/edk2/tools_def.txt
+++ /dev/null
@@ -1,183 +0,0 @@
-#
-#  Copyright (c) 2006 - 2016, Intel Corporation. All rights reserved.<BR>
-#  Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
-#  Portions copyright (c) 2011 - 2014, ARM Ltd. All rights reserved.<BR>
-#  Copyright (c) 2015, Hewlett-Packard Development Company, L.P.<BR>
-#  (C) Copyright 2016 Hewlett Packard Enterprise Development LP<BR>
-#
-#  This program and the accompanying materials
-#  are licensed and made available under the terms and conditions of the BSD License
-#  which accompanies this distribution.  The full text of the license may be found at
-#  http://opensource.org/licenses/bsd-license.php
-#
-#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-#
-
-#The following has been adapted from the BaseTools/Conf/tools_def.template file
-#and is used to direct the edk2 build to use coreboot's crossgcc toolchain
-#rather than the host machine's toolchain
-
-DEFINE COREBOOT_IA32_PREFIX    = ENV(GCC_CC_x86_32)
-DEFINE COREBOOT_X64_PREFIX     = ENV(GCC_CC_x86_64)
-DEFINE COREBOOT_ARM_PREFIX     = ENV(GCC_CC_arm)
-DEFINE COREBOOT_ARM64_PREFIX   = ENV(GCC_CC_arm64)
-
-DEFINE COREBOOT_IA32_OBJCOPY   = ENV(OBJCOPY_x86_32)
-DEFINE COREBOOT_X64_OBJCOPY    = ENV(OBJCOPY_x86_64)
-DEFINE COREBOOT_ARM_OBJCOPY    = ENV(OBJCOPY_arm)
-DEFINE COREBOOT_ARM64_OBJCOPY  = ENV(OBJCOPY_arm64)
-
-####################################################################################
-#
-# COREBOOT - This configuration is used to compile under Linux to produce
-#           PE/COFF binaries using coreboot's toolchain.
-#
-##################################################################################
-
-*_COREBOOT_*_*_FAMILY		 = GCC
-
-*_COREBOOT_*_MAKE_PATH               = make
-*_COREBOOT_*_*_DLL                   = ENV(GCC5_DLL)
-*_COREBOOT_*_ASL_PATH                = DEF(UNIX_IASL_BIN)
-
-*_COREBOOT_*_PP_FLAGS                = DEF(GCC_PP_FLAGS)
-*_COREBOOT_*_ASLPP_FLAGS             = DEF(GCC_ASLPP_FLAGS)
-*_COREBOOT_*_ASLCC_FLAGS             = DEF(GCC_ASLCC_FLAGS)
-*_COREBOOT_*_VFRPP_FLAGS             = DEF(GCC_VFRPP_FLAGS)
-*_COREBOOT_*_APP_FLAGS               =
-*_COREBOOT_*_ASL_FLAGS               = DEF(IASL_FLAGS)
-*_COREBOOT_*_ASL_OUTFLAGS            = DEF(IASL_OUTFLAGS)
-
-##################
-# COREBOOT IA32 definitions
-##################
-*_COREBOOT_IA32_OBJCOPY_PATH         = DEF(COREBOOT_IA32_OBJCOPY)
-*_COREBOOT_IA32_CC_PATH              = DEF(COREBOOT_IA32_PREFIX)
-*_COREBOOT_IA32_SLINK_PATH           = DEF(COREBOOT_IA32_PREFIX)-ar
-*_COREBOOT_IA32_DLINK_PATH           = DEF(COREBOOT_IA32_PREFIX)
-*_COREBOOT_IA32_ASLDLINK_PATH        = DEF(COREBOOT_IA32_PREFIX)
-*_COREBOOT_IA32_ASM_PATH             = DEF(COREBOOT_IA32_PREFIX)
-*_COREBOOT_IA32_PP_PATH              = DEF(COREBOOT_IA32_PREFIX)
-*_COREBOOT_IA32_VFRPP_PATH           = DEF(COREBOOT_IA32_PREFIX)
-*_COREBOOT_IA32_ASLCC_PATH           = DEF(COREBOOT_IA32_PREFIX)
-*_COREBOOT_IA32_ASLPP_PATH           = DEF(COREBOOT_IA32_PREFIX)
-*_COREBOOT_IA32_RC_PATH              = DEF(COREBOOT_IA32_OBJCOPY)
-
-*_COREBOOT_IA32_ASLCC_FLAGS          = DEF(GCC_ASLCC_FLAGS) -m32 -fno-lto
-*_COREBOOT_IA32_ASLDLINK_FLAGS       = DEF(GCC5_IA32_X64_ASLDLINK_FLAGS) -Wl,-m,elf_i386
-*_COREBOOT_IA32_ASM_FLAGS            = DEF(GCC5_ASM_FLAGS) -m32 -march=i386
-*_COREBOOT_IA32_DLINK2_FLAGS         = DEF(GCC5_IA32_DLINK2_FLAGS)
-*_COREBOOT_IA32_RC_FLAGS             = DEF(GCC_IA32_RC_FLAGS)
-*_COREBOOT_IA32_OBJCOPY_FLAGS        =
-*_COREBOOT_IA32_NASM_FLAGS           = -f elf32
-
-  DEBUG_COREBOOT_IA32_CC_FLAGS       = DEF(GCC5_IA32_CC_FLAGS) -flto -Os
-  DEBUG_COREBOOT_IA32_DLINK_FLAGS    = DEF(GCC5_IA32_X64_DLINK_FLAGS) -flto -Os -Wl,-m,elf_i386,--oformat=elf32-i386 -z common-page-size=0x1000
-
-RELEASE_COREBOOT_IA32_CC_FLAGS       = DEF(GCC5_IA32_CC_FLAGS) -flto -Os -Wno-unused-but-set-variable
-RELEASE_COREBOOT_IA32_DLINK_FLAGS    = DEF(GCC5_IA32_X64_DLINK_FLAGS) -flto -Os -Wl,-m,elf_i386,--oformat=elf32-i386 -z common-page-size=0x1000
-
-  NOOPT_COREBOOT_IA32_CC_FLAGS       = DEF(GCC5_IA32_CC_FLAGS) -O0
-  NOOPT_COREBOOT_IA32_DLINK_FLAGS    = DEF(GCC5_IA32_X64_DLINK_FLAGS) -Wl,-m,elf_i386,--oformat=elf32-i386 -O0 -z common-page-size=0x1000
-
-##################
-# COREBOOT X64 definitions
-##################
-*_COREBOOT_X64_OBJCOPY_PATH          = DEF(COREBOOT_X64_OBJCOPY)
-*_COREBOOT_X64_CC_PATH               = DEF(COREBOOT_X64_PREFIX)
-*_COREBOOT_X64_SLINK_PATH            = DEF(COREBOOT_X64_PREFIX)-ar
-*_COREBOOT_X64_DLINK_PATH            = DEF(COREBOOT_X64_PREFIX)
-*_COREBOOT_X64_ASLDLINK_PATH         = DEF(COREBOOT_X64_PREFIX)
-*_COREBOOT_X64_ASM_PATH              = DEF(COREBOOT_X64_PREFIX)
-*_COREBOOT_X64_PP_PATH               = DEF(COREBOOT_X64_PREFIX)
-*_COREBOOT_X64_VFRPP_PATH            = DEF(COREBOOT_X64_PREFIX)
-*_COREBOOT_X64_ASLCC_PATH            = DEF(COREBOOT_X64_PREFIX)
-*_COREBOOT_X64_ASLPP_PATH            = DEF(COREBOOT_X64_PREFIX)
-*_COREBOOT_X64_RC_PATH               = DEF(COREBOOT_X64_OBJCOPY)
-
-*_COREBOOT_X64_ASLCC_FLAGS           = DEF(GCC_ASLCC_FLAGS) -m64 -fno-lto
-*_COREBOOT_X64_ASLDLINK_FLAGS        = DEF(GCC5_IA32_X64_ASLDLINK_FLAGS) -Wl,-m,elf_x86_64
-*_COREBOOT_X64_ASM_FLAGS             = DEF(GCC5_ASM_FLAGS) -m64
-*_COREBOOT_X64_DLINK2_FLAGS          = DEF(GCC5_X64_DLINK2_FLAGS)
-*_COREBOOT_X64_RC_FLAGS              = DEF(GCC_X64_RC_FLAGS)
-*_COREBOOT_X64_OBJCOPY_FLAGS         =
-*_COREBOOT_X64_NASM_FLAGS            = -f elf64
-
-  DEBUG_COREBOOT_X64_CC_FLAGS        = DEF(GCC5_X64_CC_FLAGS) -flto -DUSING_LTO -Os
-  DEBUG_COREBOOT_X64_DLINK_FLAGS     = DEF(GCC5_X64_DLINK_FLAGS) -flto -Os -z common-page-size=0x1000
-
-RELEASE_COREBOOT_X64_CC_FLAGS        = DEF(GCC5_X64_CC_FLAGS) -flto -DUSING_LTO -Os -Wno-unused-but-set-variable
-RELEASE_COREBOOT_X64_DLINK_FLAGS     = DEF(GCC5_X64_DLINK_FLAGS) -flto -Os -z common-page-size=0x1000
-
-  NOOPT_COREBOOT_X64_CC_FLAGS        = DEF(GCC5_X64_CC_FLAGS) -O0
-  NOOPT_COREBOOT_X64_DLINK_FLAGS     = DEF(GCC5_X64_DLINK_FLAGS) -O0 -z common-page-size=0x1000
-
-##################
-# COREBOOT ARM definitions
-##################
-*_COREBOOT_ARM_CC_PATH               = ENV(COREBOOT_ARM_PREFIX)
-*_COREBOOT_ARM_SLINK_PATH            = ENV(COREBOOT_ARM_PREFIX)-ar
-*_COREBOOT_ARM_DLINK_PATH            = ENV(COREBOOT_ARM_PREFIX)
-*_COREBOOT_ARM_ASLDLINK_PATH         = ENV(COREBOOT_ARM_PREFIX)
-*_COREBOOT_ARM_ASM_PATH              = ENV(COREBOOT_ARM_PREFIX)
-*_COREBOOT_ARM_PP_PATH               = ENV(COREBOOT_ARM_PREFIX)
-*_COREBOOT_ARM_VFRPP_PATH            = ENV(COREBOOT_ARM_PREFIX)
-*_COREBOOT_ARM_ASLCC_PATH            = ENV(COREBOOT_ARM_PREFIX)
-*_COREBOOT_ARM_ASLPP_PATH            = ENV(COREBOOT_ARM_PREFIX)
-*_COREBOOT_ARM_RC_PATH               = ENV(COREBOOT_ARM_OBJCOPY)
-
-*_COREBOOT_ARM_ARCHCC_FLAGS          = -mthumb
-*_COREBOOT_ARM_ASLCC_FLAGS           = DEF(GCC_ASLCC_FLAGS)
-*_COREBOOT_ARM_ASLDLINK_FLAGS        = DEF(GCC5_ARM_ASLDLINK_FLAGS)
-*_COREBOOT_ARM_ASM_FLAGS             = DEF(GCC5_ARM_ASM_FLAGS)
-*_COREBOOT_ARM_DLINK2_FLAGS          = DEF(GCC5_ARM_DLINK2_FLAGS)
-*_COREBOOT_ARM_PLATFORM_FLAGS        = -march=armv7-a
-*_COREBOOT_ARM_PP_FLAGS              = $(ARCHCC_FLAGS) $(PLATFORM_FLAGS) DEF(GCC_PP_FLAGS)
-*_COREBOOT_ARM_RC_FLAGS              = DEF(GCC_ARM_RC_FLAGS)
-*_COREBOOT_ARM_VFRPP_FLAGS           = $(ARCHCC_FLAGS) $(PLATFORM_FLAGS) DEF(GCC_VFRPP_FLAGS)
-*_COREBOOT_ARM_CC_XIPFLAGS           = DEF(GCC5_ARM_CC_XIPFLAGS)
-
-  DEBUG_COREBOOT_ARM_CC_FLAGS        = DEF(GCC5_ARM_CC_FLAGS) -O0
-  DEBUG_COREBOOT_ARM_DLINK_FLAGS     = DEF(GCC5_ARM_DLINK_FLAGS) -z common-page-size=0x1000
-
-RELEASE_COREBOOT_ARM_CC_FLAGS        = DEF(GCC5_ARM_CC_FLAGS) -flto -Wno-unused-but-set-variable
-RELEASE_COREBOOT_ARM_DLINK_FLAGS     = DEF(GCC5_ARM_DLINK_FLAGS) -flto -Os -L$(WORKSPACE)/ArmPkg/Library/GccLto -llto-arm -Wl,-plugin-opt=-pass-through=-llto-arm -z common-page-size=0x1000
-
-  NOOPT_COREBOOT_ARM_CC_FLAGS        = DEF(GCC5_ARM_CC_FLAGS) -O0
-  NOOPT_COREBOOT_ARM_DLINK_FLAGS     = DEF(GCC5_ARM_DLINK_FLAGS) -O0 -z common-page-size=0x1000
-
-##################
-# COREBOOT AARCH64 definitions
-##################
-*_COREBOOT_AARCH64_CC_PATH           = ENV(COREBOOT_ARM64_PREFIX)
-*_COREBOOT_AARCH64_SLINK_PATH        = ENV(COREBOOT_ARM64_PREFIX)-ar
-*_COREBOOT_AARCH64_DLINK_PATH        = ENV(COREBOOT_ARM64_PREFIX)
-*_COREBOOT_AARCH64_ASLDLINK_PATH     = ENV(COREBOOT_ARM64_PREFIX)
-*_COREBOOT_AARCH64_ASM_PATH          = ENV(COREBOOT_ARM64_PREFIX)
-*_COREBOOT_AARCH64_PP_PATH           = ENV(COREBOOT_ARM64_PREFIX)
-*_COREBOOT_AARCH64_VFRPP_PATH        = ENV(COREBOOT_ARM64_PREFIX)
-*_COREBOOT_AARCH64_ASLCC_PATH        = ENV(COREBOOT_ARM64_PREFIX)
-*_COREBOOT_AARCH64_ASLPP_PATH        = ENV(COREBOOT_ARM64_PREFIX)
-*_COREBOOT_AARCH64_RC_PATH           = ENV(COREBOOT_ARM64_OBJCOPY)
-
-*_COREBOOT_AARCH64_ASLCC_FLAGS       = DEF(GCC_ASLCC_FLAGS)
-*_COREBOOT_AARCH64_ASLDLINK_FLAGS    = DEF(GCC5_AARCH64_ASLDLINK_FLAGS)
-*_COREBOOT_AARCH64_ASM_FLAGS         = DEF(GCC5_AARCH64_ASM_FLAGS)
-*_COREBOOT_AARCH64_DLINK2_FLAGS      = DEF(GCC5_AARCH64_DLINK2_FLAGS)
-*_COREBOOT_AARCH64_PLATFORM_FLAGS    =
-*_COREBOOT_AARCH64_PP_FLAGS          = $(ARCHCC_FLAGS) $(PLATFORM_FLAGS) DEF(GCC_PP_FLAGS)
-*_COREBOOT_AARCH64_RC_FLAGS          = DEF(GCC_AARCH64_RC_FLAGS)
-*_COREBOOT_AARCH64_VFRPP_FLAGS       = $(ARCHCC_FLAGS) $(PLATFORM_FLAGS) DEF(GCC_VFRPP_FLAGS)
-*_COREBOOT_AARCH64_CC_XIPFLAGS       = DEF(GCC5_AARCH64_CC_XIPFLAGS)
-
-  DEBUG_COREBOOT_AARCH64_CC_FLAGS    = DEF(GCC5_AARCH64_CC_FLAGS) -O0 -mcmodel=small
-  DEBUG_COREBOOT_AARCH64_DLINK_FLAGS = DEF(GCC5_AARCH64_DLINK_FLAGS) -z common-page-size=0x1000
-  DEBUG_COREBOOT_AARCH64_DLINK_XIPFLAGS = -z common-page-size=0x20
-
-RELEASE_COREBOOT_AARCH64_CC_FLAGS    = DEF(GCC5_AARCH64_CC_FLAGS) -flto -Wno-unused-but-set-variable -mcmodel=tiny -fomit-frame-pointer
-RELEASE_COREBOOT_AARCH64_DLINK_FLAGS = DEF(GCC5_AARCH64_DLINK_FLAGS) -flto -Os -L$(WORKSPACE)/ArmPkg/Library/GccLto -llto-aarch64 -Wl,-plugin-opt=-pass-through=-llto-aarch64 -z common-page-size=0x1000
-
-  NOOPT_COREBOOT_AARCH64_CC_FLAGS    = DEF(GCC5_AARCH64_CC_FLAGS) -O0 -mcmodel=small
-  NOOPT_COREBOOT_AARCH64_DLINK_FLAGS = DEF(GCC5_AARCH64_DLINK_FLAGS) -z common-page-size=0x1000 -O0
-  NOOPT_COREBOOT_AARCH64_DLINK_XIPFLAGS = -z common-page-size=0x20 -O0

From 9c5557f98275654d06dc0a64b68e22f0101be4fc Mon Sep 17 00:00:00 2001
From: Martin Roth <gaumless@gmail.com>
Date: Sat, 28 Jun 2025 16:03:07 -0600
Subject: [PATCH 1570/3886] util/abuild: Add --sequential-boards option

By default, when building all boards, we use a single thread for each
board and build a number of boards in parallel. The --sequential-boards
flag will change that to use all specified cores to build each board
in sequence.

This can give better performance in some cases where multiple builds
are conflicting for a given resource.

Change-Id: I35ae7a5df5de48b8ce3373b6659be0df5104ed39
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88239
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 util/abuild/abuild | 21 ++++++++++++++++-----
 1 file changed, 16 insertions(+), 5 deletions(-)

diff --git a/util/abuild/abuild b/util/abuild/abuild
index 8483942aed..b471e7d089 100755
--- a/util/abuild/abuild
+++ b/util/abuild/abuild
@@ -755,6 +755,7 @@ Options:\n
     [-R|--root <path>]            Absolute path to coreboot sources
                                   (defaults to ${ROOT})
     [--static-analysis]            Run clang-tidy for static code analysis
+    [-S|--sequential-boards]      Build boards sequentially using all cores
     [--skip_set <value>]          Skip building boards with this Kconfig set
     [--skip_unset <value>]        Skip building boards with this Kconfig not set
     [--timeless]                  Generate timeless builds
@@ -796,6 +797,7 @@ EOF
 # default options
 target=""
 buildall=false
+sequential=false
 
 test -f util/sconfig/sconfig.l && ROOT=$( pwd )
 test -f ../util/sconfig/sconfig.l && ROOT=$( cd .. && pwd )
@@ -814,12 +816,12 @@ getoptbrand="$(getopt -V)"
 # shellcheck disable=SC2086
 if [[ "${getoptbrand:0:6}" == "getopt" ]]; then
 	# Detected GNU getopt that supports long options.
-	args=$(getopt -l version,verbose,quiet,help,all,target:,board-variant:,payloads:,cpus:,silent,junit,config,loglevel:,remove,prefix:,update,static-analysis,ccache,blobs,clang,any-toolchain,clean,clean-somewhat,outdir:,chromeos,xmlfile:,kconfig:,dir:,root:,recursive,checksum:,timeless,exitcode,asserts,name:,skip_set:,skip_unset: -o Vvqhat:b:p:c:sJCl:rP:uyBLAzZo:xX:K:d:R:Ien: -- "$@") || exit 1
+	args=$(getopt -l version,verbose,quiet,help,all,target:,board-variant:,payloads:,cpus:,silent,junit,config,loglevel:,remove,prefix:,update,static-analysis,ccache,blobs,clang,any-toolchain,clean,clean-somewhat,outdir:,chromeos,xmlfile:,kconfig:,dir:,root:,recursive,checksum:,timeless,exitcode,asserts,name:,skip_set:,skip_unset:,sequential-boards -o Vvqhat:b:p:c:sJCl:rP:uyBLAzZo:xX:K:d:R:Ien:S -- "$@") || exit 1
 	eval set -- ${args}
 	retval=$?
 else
 	# Detected non-GNU getopt
-	args=$(getopt Vvqhat:b:p:c:sJCl:rP:uyBLAZzo:xX:K:d:R:Ien: "$@")
+	args=$(getopt Vvqhat:b:p:c:sJCl:rP:uyBLAZzo:xX:K:d:R:Ien:S "$@")
 	set -- ${args}
 	retval=$?
 fi
@@ -943,6 +945,7 @@ while true ; do
 			shift;;
 		--checksum)	shift; checksum_file="$1"; shift;;
 		--timeless)	shift; TIMELESS=1;;
+		-S|--sequential-boards) shift; sequential=true;;
 		--)		shift; break;;
 		-*)		printf "Invalid option '%s'\n\n" "$1"; myhelp; exit 1;;
 		*)		break;;
@@ -1002,7 +1005,10 @@ if [[ "${recursive}" = "false" ]]; then
 fi
 
 USE_XARGS=0
-if [[ "${cpus}" != "1" ]]; then
+if [[ "${sequential}" = "true" ]]; then
+	# Force sequential building when --sequential-boards is used
+	USE_XARGS=0
+elif [[ "${cpus}" != "1" ]]; then
 	# Limit to 32 parallel builds for now.
 	# Thrashing all caches because we run
 	# 160 abuilds in parallel is no fun.
@@ -1014,7 +1020,12 @@ if [[ "${cpus}" != "1" ]]; then
 fi
 
 if [[ "${USE_XARGS}" = "0" ]]; then
-test "${MAKEFLAGS}" == "" && test "${cpus}" != "" && export MAKEFLAGS="-j ${cpus}"
+if [[ "${sequential}" = "true" ]]; then
+	# Use all available cores for building boards sequentially
+	export MAKEFLAGS="-j ${cpus}"
+else
+	test "${MAKEFLAGS}" == "" && test "${cpus}" != "" && export MAKEFLAGS="-j ${cpus}"
+fi
 export MAKEFLAGS="${MAKEFLAGS} UPDATED_SUBMODULES=1" # no need to re-download
 build_targets()
 {
@@ -1130,4 +1141,4 @@ if [[ "${recursive}" = "false" ]]; then
 	fi
 fi
 
-exit ${failed}
\ No newline at end of file
+exit ${failed}

From eb1483ba1766fc1c931a3c96d1422e1d8c33c88e Mon Sep 17 00:00:00 2001
From: irving-ch-lin <irving-ch.lin@mediatek.com>
Date: Mon, 14 Jul 2025 10:32:27 +0800
Subject: [PATCH 1571/3886] soc/mediatek/mt8189: Increase SCP clock frequency
 from 26MHz to 416MHz

Increase the default SCP clock from 26MHz (value 0) to 416MHz (value 4).
With this change, decoder performance improves from 4K@39FPS to 4K@87FPS
during testing.

BUG=b:413506208
BRANCH=none
TEST=tast run root@${dut_ip_addr} video.Seek.stress_h264

Signed-off-by: Irving-CH.lin <irving-ch.lin@mediatek.corp-partner.google.com>
Change-Id: I30b3162b50c44ed23acc9e77eb5528b59e6ff569
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88445
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
---
 src/soc/mediatek/mt8189/pll.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/soc/mediatek/mt8189/pll.c b/src/soc/mediatek/mt8189/pll.c
index c05c39227c..35239a1cdf 100644
--- a/src/soc/mediatek/mt8189/pll.c
+++ b/src/soc/mediatek/mt8189/pll.c
@@ -287,7 +287,7 @@ static const struct mux vlp_muxes[] = {
 };
 
 static const struct vlp_mux_sel vlp_mux_sels[] = {
-	{ .id = CLK_VLP_CK_SCP_SEL, .sel = 0 },
+	{ .id = CLK_VLP_CK_SCP_SEL, .sel = 4 },
 	{ .id = CLK_VLP_CK_PWRAP_ULPOSC_SEL, .sel = 0 },
 	{ .id = CLK_VLP_CK_SPMI_P_MST_SEL, .sel = 0 },
 	{ .id = CLK_VLP_CK_DVFSRC_SEL, .sel = 0 },

From 2f978ecab37aec813715dd40aaadfb2e73d529fc Mon Sep 17 00:00:00 2001
From: Jamie Ryu <jamie.m.ryu@intel.com>
Date: Fri, 27 Jun 2025 15:43:15 -0700
Subject: [PATCH 1572/3886] mb/google/fatcat: Choose platforms with pre-prod
 Panther Lake SoC

This updates the Kconfig for Google Fatcat mainboards to include
`SOC_INTEL_PANTHERLAKE_PRE_PRODUCTION_SILICON` option to ensure
compatibility with Panther Lake pre-production silicon. This selection
aligns these boards with the necessary pre-production silicon settings

BUG=b:424355826
TEST=Ensure mainboards like fatcat4es and fatcatnuvo4es have
`SOC_INTEL_PANTHERLAKE_PRE_PRODUCTION_SILICON` config enabled.

Change-Id: Icde96976e0e3ccfc543bc948d2923e0f84e7da68
Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88219
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/google/fatcat/Kconfig | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/src/mainboard/google/fatcat/Kconfig b/src/mainboard/google/fatcat/Kconfig
index 1ba556523d..b2c3b46768 100644
--- a/src/mainboard/google/fatcat/Kconfig
+++ b/src/mainboard/google/fatcat/Kconfig
@@ -81,6 +81,7 @@ config BOARD_GOOGLE_FATCAT4ES
 	select BOARD_GOOGLE_MODEL_FATCAT
 	select EC_GOOGLE_CHROMEEC_MEC
 	select MAINBOARD_USES_IFD_EC_REGION
+	select SOC_INTEL_PANTHERLAKE_PRE_PRODUCTION_SILICON
 
 config BOARD_GOOGLE_FATCATISH
 	select BOARD_GOOGLE_MODEL_FATCAT
@@ -92,23 +93,28 @@ config BOARD_GOOGLE_FATCATNUVO
 
 config BOARD_GOOGLE_FATCATNUVO4ES
 	select BOARD_GOOGLE_MODEL_FATCAT
+	select SOC_INTEL_PANTHERLAKE_PRE_PRODUCTION_SILICON
 
 config BOARD_GOOGLE_FATCATITE
 	select BOARD_GOOGLE_MODEL_FATCAT
 
 config BOARD_GOOGLE_FATCATITE4ES
 	select BOARD_GOOGLE_MODEL_FATCAT
+	select SOC_INTEL_PANTHERLAKE_PRE_PRODUCTION_SILICON
 
 config BOARD_GOOGLE_FELINO
 	select BOARD_GOOGLE_MODEL_FELINO
+	select SOC_INTEL_PANTHERLAKE_PRE_PRODUCTION_SILICON
 
 config BOARD_GOOGLE_FELINO4ES
 	select BOARD_GOOGLE_MODEL_FELINO
+	select SOC_INTEL_PANTHERLAKE_PRE_PRODUCTION_SILICON
 
 config BOARD_GOOGLE_FRANCKA
 	select BOARD_GOOGLE_BASEBOARD_FATCAT
 	select DRIVERS_SOUNDWIRE_ALC1320
 	select HAVE_SLP_S0_GATE
+	select SOC_INTEL_PANTHERLAKE_PRE_PRODUCTION_SILICON
 
 config BOARD_GOOGLE_KINMEN
 	select BOARD_GOOGLE_BASEBOARD_FATCAT

From 8d60bf9975849438960a470bcb839ff49c382259 Mon Sep 17 00:00:00 2001
From: Jamie Ryu <jamie.m.ryu@intel.com>
Date: Fri, 27 Jun 2025 16:06:49 -0700
Subject: [PATCH 1573/3886] mb/google/fatcat: select MIPI pre-prod if PTL
 pre-prod SoC is set

This adds changes to conditionally enable the config
`DRIVERS_INTEL_MIPI_SUPPORTS_PRE_PRODUCTION_SOC` when
`SOC_INTEL_PANTHERLAKE_PRE_PRODUCTION_SILICON` is enabled.
This ensures that MIPI firmware and drivers are compatible with
Panther Lake pre-production silicon.

BUG=b:424355826
TEST=Ensures `DRIVERS_INTEL_MIPI_SUPPORTS_PRE_PRODUCTION_SOC` is
enabled for google/fatcat4es and all variants with ES silicon.

Change-Id: I9687618cfceac32425fa19b4f1f30040b88a2d15
Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88220
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Pranava Y N <pranavayn@google.com>
---
 src/mainboard/google/fatcat/Kconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/src/mainboard/google/fatcat/Kconfig b/src/mainboard/google/fatcat/Kconfig
index b2c3b46768..620368371c 100644
--- a/src/mainboard/google/fatcat/Kconfig
+++ b/src/mainboard/google/fatcat/Kconfig
@@ -9,6 +9,7 @@ config BOARD_GOOGLE_FATCAT_COMMON
 	select DRIVERS_I2C_HID
 	select DRIVERS_INTEL_DPTF
 	select DRIVERS_INTEL_MIPI_CAMERA
+	select DRIVERS_INTEL_MIPI_SUPPORTS_PRE_PRODUCTION_SOC if SOC_INTEL_PANTHERLAKE_PRE_PRODUCTION_SILICON
 	select DRIVERS_INTEL_PMC
 	select DRIVERS_INTEL_SOUNDWIRE
 	select DRIVERS_WWAN_FM350GL

From f62734976ce8045d11df597dec3a2ca10604cbce Mon Sep 17 00:00:00 2001
From: Nicholas Chin <nic.c3.14@gmail.com>
Date: Thu, 26 Sep 2024 19:48:26 -0600
Subject: [PATCH 1574/3886] mb/dell: Convert E6400 into a variant

In preparation for adding additional GM45/ICH9 based Dell Latitude
laptops, rework the E6400 port to use a variant scheme so that code can
be shared.

Change-Id: I8094fce56eaaadb20aef173644cd3b2c0b008e95
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84565
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
---
 src/mainboard/dell/e6400/Makefile.mk          |  10 ---------
 .../dell/{e6400 => gm45_latitude}/Kconfig     |  21 +++++++++++++-----
 .../{e6400 => gm45_latitude}/Kconfig.name     |   0
 src/mainboard/dell/gm45_latitude/Makefile.mk  |  11 +++++++++
 .../dell/{e6400 => gm45_latitude}/acpi/ec.asl |   0
 .../acpi/ich9_pci_irqs.asl                    |   0
 .../{e6400 => gm45_latitude}/acpi/superio.asl |   0
 .../dell/{e6400 => gm45_latitude}/blc.c       |   0
 .../{e6400 => gm45_latitude}/board_info.txt   |   0
 .../dell/{e6400 => gm45_latitude}/bootblock.c |   0
 .../{e6400 => gm45_latitude}/cmos.default     |   0
 .../dell/{e6400 => gm45_latitude}/cmos.layout |   0
 .../dell/{e6400 => gm45_latitude}/cstates.c   |   0
 .../{e6400 => gm45_latitude}/devicetree.cb    |   1 -
 .../dell/{e6400 => gm45_latitude}/dsdt.asl    |   0
 .../dell/{e6400 => gm45_latitude}/mainboard.c |   0
 .../dell/{e6400 => gm45_latitude}/romstage.c  |   0
 .../variants}/e6400/data.vbt                  | Bin
 .../variants}/e6400/gma-mainboard.ads         |   0
 .../{ => gm45_latitude/variants}/e6400/gpio.c |   0
 .../variants}/e6400/hda_verb.c                |   0
 .../variants/e6400/overridetree.cb            |   7 ++++++
 22 files changed, 33 insertions(+), 17 deletions(-)
 delete mode 100644 src/mainboard/dell/e6400/Makefile.mk
 rename src/mainboard/dell/{e6400 => gm45_latitude}/Kconfig (62%)
 rename src/mainboard/dell/{e6400 => gm45_latitude}/Kconfig.name (100%)
 create mode 100644 src/mainboard/dell/gm45_latitude/Makefile.mk
 rename src/mainboard/dell/{e6400 => gm45_latitude}/acpi/ec.asl (100%)
 rename src/mainboard/dell/{e6400 => gm45_latitude}/acpi/ich9_pci_irqs.asl (100%)
 rename src/mainboard/dell/{e6400 => gm45_latitude}/acpi/superio.asl (100%)
 rename src/mainboard/dell/{e6400 => gm45_latitude}/blc.c (100%)
 rename src/mainboard/dell/{e6400 => gm45_latitude}/board_info.txt (100%)
 rename src/mainboard/dell/{e6400 => gm45_latitude}/bootblock.c (100%)
 rename src/mainboard/dell/{e6400 => gm45_latitude}/cmos.default (100%)
 rename src/mainboard/dell/{e6400 => gm45_latitude}/cmos.layout (100%)
 rename src/mainboard/dell/{e6400 => gm45_latitude}/cstates.c (100%)
 rename src/mainboard/dell/{e6400 => gm45_latitude}/devicetree.cb (98%)
 rename src/mainboard/dell/{e6400 => gm45_latitude}/dsdt.asl (100%)
 rename src/mainboard/dell/{e6400 => gm45_latitude}/mainboard.c (100%)
 rename src/mainboard/dell/{e6400 => gm45_latitude}/romstage.c (100%)
 rename src/mainboard/dell/{ => gm45_latitude/variants}/e6400/data.vbt (100%)
 rename src/mainboard/dell/{ => gm45_latitude/variants}/e6400/gma-mainboard.ads (100%)
 rename src/mainboard/dell/{ => gm45_latitude/variants}/e6400/gpio.c (100%)
 rename src/mainboard/dell/{ => gm45_latitude/variants}/e6400/hda_verb.c (100%)
 create mode 100644 src/mainboard/dell/gm45_latitude/variants/e6400/overridetree.cb

diff --git a/src/mainboard/dell/e6400/Makefile.mk b/src/mainboard/dell/e6400/Makefile.mk
deleted file mode 100644
index ca3a82db48..0000000000
--- a/src/mainboard/dell/e6400/Makefile.mk
+++ /dev/null
@@ -1,10 +0,0 @@
-## SPDX-License-Identifier: GPL-2.0-only
-
-bootblock-y += bootblock.c
-
-romstage-y += gpio.c
-
-ramstage-y += cstates.c
-ramstage-y += blc.c
-
-ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads
diff --git a/src/mainboard/dell/e6400/Kconfig b/src/mainboard/dell/gm45_latitude/Kconfig
similarity index 62%
rename from src/mainboard/dell/e6400/Kconfig
rename to src/mainboard/dell/gm45_latitude/Kconfig
index 417d95fd5d..98ad18849c 100644
--- a/src/mainboard/dell/e6400/Kconfig
+++ b/src/mainboard/dell/gm45_latitude/Kconfig
@@ -1,9 +1,7 @@
 ## SPDX-License-Identifier: GPL-2.0-only
 
-if BOARD_DELL_E6400
-
-config BOARD_SPECIFIC_OPTIONS
-	def_bool y
+config BOARD_DELL_GM45_LATITUDE_COMMON
+	def_bool n
 	select SYSTEM_TYPE_LAPTOP
 	select CPU_INTEL_SOCKET_P
 	select NORTHBRIDGE_INTEL_GM45
@@ -19,16 +17,27 @@ config BOARD_SPECIFIC_OPTIONS
 	select INTEL_GMA_HAVE_VBT
 	select EC_DELL_MEC5035
 
+config BOARD_DELL_E6400
+	select BOARD_DELL_GM45_LATITUDE_COMMON
+
+if BOARD_DELL_GM45_LATITUDE_COMMON
+
 config MAINBOARD_DIR
-	default "dell/e6400"
+	default "dell/gm45_latitude"
 
 config MAINBOARD_PART_NUMBER
 	default "Latitude E6400" if BOARD_DELL_E6400
 
+config OVERRIDE_DEVICETREE
+	default "variants/\$(CONFIG_VARIANT_DIR)/overridetree.cb"
+
+config VARIANT_DIR
+	default "e6400" if BOARD_DELL_E6400
+
 config USBDEBUG_HCD_INDEX
 	default 1
 
 config CBFS_SIZE
 	default 0x1A0000
 
-endif # BOARD_DELL_E6400
+endif # BOARD_DELL_GM45_LATITUDE_COMMON
diff --git a/src/mainboard/dell/e6400/Kconfig.name b/src/mainboard/dell/gm45_latitude/Kconfig.name
similarity index 100%
rename from src/mainboard/dell/e6400/Kconfig.name
rename to src/mainboard/dell/gm45_latitude/Kconfig.name
diff --git a/src/mainboard/dell/gm45_latitude/Makefile.mk b/src/mainboard/dell/gm45_latitude/Makefile.mk
new file mode 100644
index 0000000000..5295d5be22
--- /dev/null
+++ b/src/mainboard/dell/gm45_latitude/Makefile.mk
@@ -0,0 +1,11 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
+bootblock-y += bootblock.c
+
+romstage-y += variants/$(VARIANT_DIR)/gpio.c
+
+ramstage-y += cstates.c
+ramstage-y += blc.c
+ramstage-y += variants/$(VARIANT_DIR)/hda_verb.c
+
+ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += variants/$(VARIANT_DIR)/gma-mainboard.ads
diff --git a/src/mainboard/dell/e6400/acpi/ec.asl b/src/mainboard/dell/gm45_latitude/acpi/ec.asl
similarity index 100%
rename from src/mainboard/dell/e6400/acpi/ec.asl
rename to src/mainboard/dell/gm45_latitude/acpi/ec.asl
diff --git a/src/mainboard/dell/e6400/acpi/ich9_pci_irqs.asl b/src/mainboard/dell/gm45_latitude/acpi/ich9_pci_irqs.asl
similarity index 100%
rename from src/mainboard/dell/e6400/acpi/ich9_pci_irqs.asl
rename to src/mainboard/dell/gm45_latitude/acpi/ich9_pci_irqs.asl
diff --git a/src/mainboard/dell/e6400/acpi/superio.asl b/src/mainboard/dell/gm45_latitude/acpi/superio.asl
similarity index 100%
rename from src/mainboard/dell/e6400/acpi/superio.asl
rename to src/mainboard/dell/gm45_latitude/acpi/superio.asl
diff --git a/src/mainboard/dell/e6400/blc.c b/src/mainboard/dell/gm45_latitude/blc.c
similarity index 100%
rename from src/mainboard/dell/e6400/blc.c
rename to src/mainboard/dell/gm45_latitude/blc.c
diff --git a/src/mainboard/dell/e6400/board_info.txt b/src/mainboard/dell/gm45_latitude/board_info.txt
similarity index 100%
rename from src/mainboard/dell/e6400/board_info.txt
rename to src/mainboard/dell/gm45_latitude/board_info.txt
diff --git a/src/mainboard/dell/e6400/bootblock.c b/src/mainboard/dell/gm45_latitude/bootblock.c
similarity index 100%
rename from src/mainboard/dell/e6400/bootblock.c
rename to src/mainboard/dell/gm45_latitude/bootblock.c
diff --git a/src/mainboard/dell/e6400/cmos.default b/src/mainboard/dell/gm45_latitude/cmos.default
similarity index 100%
rename from src/mainboard/dell/e6400/cmos.default
rename to src/mainboard/dell/gm45_latitude/cmos.default
diff --git a/src/mainboard/dell/e6400/cmos.layout b/src/mainboard/dell/gm45_latitude/cmos.layout
similarity index 100%
rename from src/mainboard/dell/e6400/cmos.layout
rename to src/mainboard/dell/gm45_latitude/cmos.layout
diff --git a/src/mainboard/dell/e6400/cstates.c b/src/mainboard/dell/gm45_latitude/cstates.c
similarity index 100%
rename from src/mainboard/dell/e6400/cstates.c
rename to src/mainboard/dell/gm45_latitude/cstates.c
diff --git a/src/mainboard/dell/e6400/devicetree.cb b/src/mainboard/dell/gm45_latitude/devicetree.cb
similarity index 98%
rename from src/mainboard/dell/e6400/devicetree.cb
rename to src/mainboard/dell/gm45_latitude/devicetree.cb
index bb954cbd7b..5919803be2 100644
--- a/src/mainboard/dell/e6400/devicetree.cb
+++ b/src/mainboard/dell/gm45_latitude/devicetree.cb
@@ -15,7 +15,6 @@ chip northbridge/intel/gm45
 	register "pci_mmio_size" = "2048"
 
 	device domain 0 on
-		subsystemid 0x1028 0x0233 inherit
 		ops gm45_pci_domain_ops
 
 		device pci 00.0 on end # host bridge
diff --git a/src/mainboard/dell/e6400/dsdt.asl b/src/mainboard/dell/gm45_latitude/dsdt.asl
similarity index 100%
rename from src/mainboard/dell/e6400/dsdt.asl
rename to src/mainboard/dell/gm45_latitude/dsdt.asl
diff --git a/src/mainboard/dell/e6400/mainboard.c b/src/mainboard/dell/gm45_latitude/mainboard.c
similarity index 100%
rename from src/mainboard/dell/e6400/mainboard.c
rename to src/mainboard/dell/gm45_latitude/mainboard.c
diff --git a/src/mainboard/dell/e6400/romstage.c b/src/mainboard/dell/gm45_latitude/romstage.c
similarity index 100%
rename from src/mainboard/dell/e6400/romstage.c
rename to src/mainboard/dell/gm45_latitude/romstage.c
diff --git a/src/mainboard/dell/e6400/data.vbt b/src/mainboard/dell/gm45_latitude/variants/e6400/data.vbt
similarity index 100%
rename from src/mainboard/dell/e6400/data.vbt
rename to src/mainboard/dell/gm45_latitude/variants/e6400/data.vbt
diff --git a/src/mainboard/dell/e6400/gma-mainboard.ads b/src/mainboard/dell/gm45_latitude/variants/e6400/gma-mainboard.ads
similarity index 100%
rename from src/mainboard/dell/e6400/gma-mainboard.ads
rename to src/mainboard/dell/gm45_latitude/variants/e6400/gma-mainboard.ads
diff --git a/src/mainboard/dell/e6400/gpio.c b/src/mainboard/dell/gm45_latitude/variants/e6400/gpio.c
similarity index 100%
rename from src/mainboard/dell/e6400/gpio.c
rename to src/mainboard/dell/gm45_latitude/variants/e6400/gpio.c
diff --git a/src/mainboard/dell/e6400/hda_verb.c b/src/mainboard/dell/gm45_latitude/variants/e6400/hda_verb.c
similarity index 100%
rename from src/mainboard/dell/e6400/hda_verb.c
rename to src/mainboard/dell/gm45_latitude/variants/e6400/hda_verb.c
diff --git a/src/mainboard/dell/gm45_latitude/variants/e6400/overridetree.cb b/src/mainboard/dell/gm45_latitude/variants/e6400/overridetree.cb
new file mode 100644
index 0000000000..acc34a2252
--- /dev/null
+++ b/src/mainboard/dell/gm45_latitude/variants/e6400/overridetree.cb
@@ -0,0 +1,7 @@
+## SPDX-License-Identifier: GPL-2.0-or-later
+
+chip northbridge/intel/gm45
+	device domain 0 on
+		subsystemid 0x1028 0x0233 inherit
+	end
+end

From e583b2ffb7d3625eb922c1b19bd6c91d212d6370 Mon Sep 17 00:00:00 2001
From: "kai-chun.huang" <kai-chun.huang@mediatek.com>
Date: Sat, 14 Jun 2025 14:34:50 +0800
Subject: [PATCH 1575/3886] soc/meidatek/mt8196: Extract common thermal code
 for reuse

To promote code reuse and maintainability, move partial thermal driver
to common.

BUG=b:379008996
BRANCH=none
TEST=build passed.

Signed-off-by: Kai-chun Huang <kai-chun.huang@mediatek.corp-partner.google.com>
Change-Id: I6a52d1cb02d04308f1e833df0f318f93a8231fe1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88440
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 .../common/include/soc/thermal_common.h       |  59 +++
 src/soc/mediatek/common/thermal.c             | 332 ++++++++++++++++
 src/soc/mediatek/common/thermal_sram.c        |  36 ++
 src/soc/mediatek/mt8196/Makefile.mk           |   4 +-
 src/soc/mediatek/mt8196/include/soc/thermal.h |   5 +-
 .../mt8196/include/soc/thermal_internal.h     |  38 +-
 src/soc/mediatek/mt8196/thermal.c             | 353 ++----------------
 src/soc/mediatek/mt8196/thermal_sram.c        |  34 +-
 8 files changed, 464 insertions(+), 397 deletions(-)
 create mode 100644 src/soc/mediatek/common/include/soc/thermal_common.h
 create mode 100644 src/soc/mediatek/common/thermal.c
 create mode 100644 src/soc/mediatek/common/thermal_sram.c

diff --git a/src/soc/mediatek/common/include/soc/thermal_common.h b/src/soc/mediatek/common/include/soc/thermal_common.h
new file mode 100644
index 0000000000..7875aec7ea
--- /dev/null
+++ b/src/soc/mediatek/common/include/soc/thermal_common.h
@@ -0,0 +1,59 @@
+/* SPDX-License-Identifier: GPL-2.0-only OR MIT */
+
+#ifndef __SOC_MEDIATEK_COMMON_INCLUDE_SOC_THERMAL_COMMON_H__
+#define __SOC_MEDIATEK_COMMON_INCLUDE_SOC_THERMAL_COMMON_H__
+
+#include <soc/thermal_internal.h>
+
+#define CHECK_DEVICE_ACCESS_RETRY_CNT	100
+#define LVTS_DEVICE_ACCESS_DELAY_US	3
+#define LVTS_READ_ID_RETRY_CNT		5
+#define LVTS_READ_ID_DELAY_US		3
+
+enum sensor_switch_status {
+	SEN_OFF,
+	SEN_ON,
+};
+
+struct lvts_thermal_controller_speed {
+	u32 group_interval_delay;
+	u32 period_unit;
+	u32 filter_interval_delay;
+	u32 sensor_interval_delay;
+};
+
+struct lvts_thermal_controller {
+	enum lvts_sensor ts[MAX_TS_NUMBER]; /* sensor point */
+	enum sensor_switch_status sensor_on_off[MAX_TS_NUMBER];
+	size_t ts_number;
+	int reboot_temperature;
+	int dominator_ts_idx;
+	unsigned int reboot_msr_sram_idx;
+	bool has_reboot_temp_sram;
+	bool has_reboot_msr_sram;
+	struct lvts_thermal_controller_speed speed;
+	struct mtk_thermal_controller_regs *regs;
+};
+
+int lvts_write_device(uint16_t config, uint8_t dev_reg_idx, uint8_t data, int tc_num);
+const struct lvts_thermal_controller *lvts_get_controller(int tc_num);
+void lvts_configure_polling_speed_and_filter(const struct lvts_thermal_controller *tc);
+int lvts_read_tc_raw_and_temp(void *msr_reg, enum lvts_sensor ts_name, uint32_t golden_temp);
+void lvts_thermal_init(void);
+void lvts_tscpu_reset_thermal(void);
+void lvts_thermal_cal_prepare(void);
+void lvts_device_identification(void);
+void lvts_device_enable_init_all_devices(void);
+void lvts_efuse_setting(void);
+void lvts_config_all_tc_hw_protect(void);
+uint16_t lvts_temp_to_raw(int temp_mc, enum lvts_sensor ts_name);
+void lvts_tscpu_thermal_read_tc_temp(const struct lvts_thermal_controller *tc, int order);
+
+void thermal_cls_sram(void);
+void thermal_stat_cls_sram(void);
+void thermal_sram_init(void);
+void thermal_init(void);
+void thermal_write_reboot_temp_sram(uint32_t value);
+void thermal_write_reboot_msr_sram(unsigned int idx, uint32_t value);
+
+#endif /* __SOC_MEDIATEK_COMMON_INCLUDE_SOC_THERMAL_COMMON_H__ */
diff --git a/src/soc/mediatek/common/thermal.c b/src/soc/mediatek/common/thermal.c
new file mode 100644
index 0000000000..47babf5ee4
--- /dev/null
+++ b/src/soc/mediatek/common/thermal.c
@@ -0,0 +1,332 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <assert.h>
+#include <delay.h>
+#include <device/mmio.h>
+#include <soc/thermal.h>
+#include <timer.h>
+
+#define LVTS_SINGLE_SENSE_MODE_EN		BIT(9)
+#define LVTS_SENSOR_POINT_SELECTION_SETTING	0x13121110
+#define LVTS_CALCULATION_SCALING_RULE		0x300
+
+static int lvts_raw_to_temp(uint16_t msr_raw, enum lvts_sensor ts_name, uint32_t golden_temp)
+{
+	int temp_mc;
+	int64_t temp1, coeff_a;
+
+	coeff_a = LVTS_COEFF_A;
+
+	temp1 = (coeff_a * msr_raw) / (1 << 14);
+	temp_mc = temp1 + golden_temp * 500 - coeff_a;
+
+	return temp_mc;
+}
+
+int lvts_read_tc_raw_and_temp(void *msr_reg, enum lvts_sensor ts_name, uint32_t golden_temp)
+{
+	int temp;
+	uint32_t msr_data;
+	uint16_t msr_raw;
+
+	msr_data = read32(msr_reg);
+	msr_raw = msr_data & 0xFFFF;
+
+	if (msr_raw > 0) {
+		temp = lvts_raw_to_temp(msr_raw, ts_name, golden_temp);
+	} else {
+		/*
+		 * 26111 is magic num.
+		 * This is to keep system alive for a while to wait until
+		 * HW init is done, because 0 msr raw will translate to 28x'C
+		 * and then 28x'C will trigger a SW reset.
+		 *
+		 * If HW init finishes, this msr raw will not be 0,
+		 * system can report normal temperature.
+		 * If wait over 60 times zero, this means something wrong with HW.
+		 */
+		temp = 26111;
+	}
+
+	printk(BIOS_INFO, "[LVTS_MSR] ts%d msr_all=%x, msr_temp=%d, temp=%d\n", ts_name,
+	       msr_data, msr_raw, temp);
+
+	return temp;
+}
+
+static void lvts_tscpu_thermal_initial_all_tc(void)
+{
+	u32 i = 0;
+
+	printk(BIOS_INFO, "===== %s begin ======\n", __func__);
+
+	for (i = 0; i < LVTS_CONTROLLER_NUM; i++) {
+		const struct lvts_thermal_controller *tc = lvts_get_controller(i);
+		/* Set sensor index of LVTS */
+		write32(&tc->regs->lvtstssel_0, LVTS_SENSOR_POINT_SELECTION_SETTING);
+		/* Set calculation scale rules */
+		write32(&tc->regs->lvtscalscale_0, LVTS_CALCULATION_SCALING_RULE);
+
+		lvts_configure_polling_speed_and_filter(tc);
+	}
+
+}
+
+void lvts_configure_polling_speed_and_filter(const struct lvts_thermal_controller *tc)
+{
+	u32 lvtsMonCtl1, lvtsMonCtl2;
+
+	printk(BIOS_INFO, "===== %s begin ======\n", __func__);
+
+	lvtsMonCtl1 = ((tc->speed.group_interval_delay << 20) &
+		LVTS_GROUP_INTERVAL_DELAY_MASK) | (tc->speed.period_unit & GENMASK(9, 0));
+
+	lvtsMonCtl2 = ((tc->speed.filter_interval_delay << 16) & GENMASK(25, 16)) |
+		      (tc->speed.sensor_interval_delay & GENMASK(9, 0));
+
+	/*
+	 * Calculating period unit in Module clock x 256, and the Module clock
+	 * will be changed to 26M when Infrasys enters Sleep mode.
+	 */
+
+	/*
+	 * Bus clock 66M counting unit is
+	 *           12 * 1/66M * 256 = 12 * 3.879us = 46.545 us
+	 */
+	write32(&tc->regs->lvtsmonctl1_0, lvtsMonCtl1);
+	/*
+	 * Filt interval is 1 * 46.545us = 46.545us,
+	 * sen interval is 429 * 46.545us = 19.968ms
+	 */
+	write32(&tc->regs->lvtsmonctl2_0, lvtsMonCtl2);
+
+	/* Temperature sampling control, 1 sample */
+	write32(&tc->regs->lvtsmsrctl0_0, 0);
+
+	udelay(1);
+	printk(BIOS_INFO,
+	       "%s,LVTSMONCTL1_0= %#x,LVTSMONCTL2_0= %#x,LVTSMSRCTL0_0= %#x\n",
+	       __func__,
+	       read32(&tc->regs->lvtsmonctl1_0),
+	       read32(&tc->regs->lvtsmonctl2_0),
+	       read32(&tc->regs->lvtsmsrctl0_0));
+}
+
+static int lvts_check_all_sensing_points_idle(void)
+{
+	uint32_t mask, temp;
+	int i;
+
+	mask = BIT(10) | BIT(7) | BIT(0);
+	for (i = 0; i < LVTS_CONTROLLER_NUM; i++) {
+		const struct lvts_thermal_controller *tc = lvts_get_controller(i);
+		temp = read32(&tc->regs->lvtsmsrctl1_0);
+		if ((temp & mask) != 0)
+			return -1;
+	}
+
+	return 0;
+}
+
+static void lvts_wait_all_sensing_points_idle(void)
+{
+	if (!retry(CHECK_DEVICE_ACCESS_RETRY_CNT,
+		   lvts_check_all_sensing_points_idle() == 0,
+		   udelay(2)))
+		printk(BIOS_ERR, "%s timeout\n", __func__);
+}
+
+static bool lvts_lk_init_check(void)
+{
+	int i;
+
+	for (i = 0; i < LVTS_CONTROLLER_NUM; i++) {
+		const struct lvts_thermal_controller *tc = lvts_get_controller(i);
+		/* Check LVTS device ID */
+		if ((read32(&tc->regs->lvtsspare[0]) & GENMASK(11, 0)) != LVTS_MAGIC)
+			return false;
+	}
+
+	return true;
+}
+
+int lvts_write_device(uint16_t config, uint8_t dev_reg_idx, uint8_t data, int tc_num)
+{
+	const struct lvts_thermal_controller *tc = lvts_get_controller(tc_num);
+	uint32_t config_data = (config << 16) | (dev_reg_idx << 8) | data;
+
+	write32(&tc->regs->lvts_config_0, config_data);
+	/*
+	 * LVTS Device Register Setting takes 1us (by 26MHz clock source)
+	 * interface latency to access.
+	 * So we set 2~3 us delay could guarantee access complete.
+	 */
+	udelay(LVTS_DEVICE_ACCESS_DELAY_US);
+
+	/*
+	 * Check ASIF bus status for transaction finished
+	 * Wait until DEVICE_ACCESS_START_BIT = 0
+	 */
+	if (!retry(CHECK_DEVICE_ACCESS_RETRY_CNT,
+		   !(read32(&tc->regs->lvts_config_0) & DEVICE_ACCESS_START_BIT), udelay(2))) {
+		printk(BIOS_ERR, "DEVICE_ACCESS_START_BIT didn't ready, reg0x%x\n",
+		       dev_reg_idx);
+	}
+	return 1;
+}
+
+static void lvts_enable_sensing_points(const struct lvts_thermal_controller *tc)
+{
+	int i;
+
+	printk(BIOS_INFO, "===== %s begin ======\n", __func__);
+	uint32_t value = LVTS_SINGLE_SENSE_MODE_EN;
+
+	for (i = 0; i < tc->ts_number; i++) {
+		if (tc->sensor_on_off[i] == SEN_ON)
+			value |= BIT(i);
+	}
+
+	write32(&tc->regs->lvtsmonctl0_0, value);
+
+	printk(BIOS_INFO, "%s,value in LVTSMONCTL0_0 = %#x\n", __func__, value);
+}
+
+/*
+ * disable ALL periodoc temperature sensing point
+ */
+static void lvts_disable_all_sensing_points(void)
+{
+	int i;
+
+	printk(BIOS_INFO, "===== %s begin ======\n", __func__);
+
+	for (i = 0; i < LVTS_CONTROLLER_NUM; i++) {
+		const struct lvts_thermal_controller *tc = lvts_get_controller(i);
+		write32(&tc->regs->lvtsmonctl0_0, LVTS_SINGLE_SENSE_MODE_EN);
+	}
+}
+
+static void lvts_enable_all_sensing_points(void)
+{
+	int i = 0;
+
+	printk(BIOS_INFO, "===== %s begin ======\n", __func__);
+
+	for (i = 0; i < LVTS_CONTROLLER_NUM; i++) {
+		const struct lvts_thermal_controller *tc = lvts_get_controller(i);
+		lvts_enable_sensing_points(tc);
+	}
+}
+
+static void lvts_set_init_flag(void)
+{
+	u32 i;
+
+	printk(BIOS_INFO, "===== %s begin ======\n", __func__);
+
+	/*write init done flag to inform kernel */
+
+	for (i = 0; i < LVTS_CONTROLLER_NUM; i++) {
+		const struct lvts_thermal_controller *tc = lvts_get_controller(i);
+		printk(BIOS_INFO, "%s %d:%zu, tc_base_addr:%p\n", __func__, i,
+		       tc->ts_number, tc->regs);
+
+		write32(&tc->regs->lvtsspare[0], LVTS_MAGIC);
+	}
+}
+
+static void lvts_set_tc_trigger_hw_protect(const struct lvts_thermal_controller *tc)
+{
+	int d_index, i;
+	uint32_t raw_high;
+	uint16_t raw;
+	enum lvts_sensor ts_name;
+
+	if (tc->dominator_ts_idx < tc->ts_number) {
+		d_index = tc->dominator_ts_idx;
+	} else {
+		printk(BIOS_ERR, "LVTS, dominator_ts_idx %d >= ts_number %zu; use idx 0\n",
+		       tc->dominator_ts_idx, tc->ts_number);
+		d_index = 0;
+	}
+
+	ts_name = tc->ts[d_index];
+
+	printk(BIOS_INFO, "%s, the dominator ts_name is %d\n", __func__, ts_name);
+
+	/* Maximum of 4 sensing points */
+	raw_high = 0;
+	for (i = 0; i < tc->ts_number; i++) {
+		ts_name = tc->ts[i];
+		raw = lvts_temp_to_raw(tc->reboot_temperature, ts_name);
+		raw_high = MAX(raw_high, raw);
+	}
+	if (tc->has_reboot_msr_sram)
+		thermal_write_reboot_msr_sram(tc->reboot_msr_sram_idx, raw_high);
+	if (tc->has_reboot_temp_sram)
+		thermal_write_reboot_temp_sram(tc->reboot_temperature);
+
+	setbits32(&tc->regs->lvtsprotctl_0, 0x3FFF);
+	/* disable trigger SPM interrupt */
+	write32(&tc->regs->lvtsmonint_0, 0);
+
+	clrsetbits32(&tc->regs->lvtsprotctl_0, 0xF << 16, BIT(16));
+
+	write32(&tc->regs->lvtsprottc_0, raw_high);
+
+	/* enable trigger Hot SPM interrupt */
+	write32(&tc->regs->lvtsmonint_0, STAGE3_INT_EN);
+
+	clrbits32(&tc->regs->lvtsprotctl_0, 0xFFFF);
+}
+
+void lvts_config_all_tc_hw_protect(void)
+{
+	int i;
+
+	printk(BIOS_INFO, "===== %s begin ======\n", __func__);
+
+	for (i = 0; i < LVTS_CONTROLLER_NUM; i++) {
+		const struct lvts_thermal_controller *tc = lvts_get_controller(i);
+		lvts_set_tc_trigger_hw_protect(tc);
+	}
+}
+
+static void read_all_tc_lvts_temperature(void)
+{
+	int i, j;
+
+	for (i = 0; i < LVTS_CONTROLLER_NUM; i++) {
+		const struct lvts_thermal_controller *tc = lvts_get_controller(i);
+		for (j = 0; j < tc->ts_number; j++)
+			lvts_tscpu_thermal_read_tc_temp(tc, j);
+	}
+}
+
+void lvts_thermal_init(void)
+{
+	printk(BIOS_INFO, "===== %s begin ======\n", __func__);
+
+	if (lvts_lk_init_check())
+		return;
+
+	lvts_tscpu_reset_thermal();
+
+	lvts_thermal_cal_prepare();
+	lvts_device_identification();
+	lvts_device_enable_init_all_devices();
+	lvts_efuse_setting();
+
+	lvts_disable_all_sensing_points();
+	lvts_wait_all_sensing_points_idle();
+	lvts_tscpu_thermal_initial_all_tc();
+	lvts_config_all_tc_hw_protect();
+	lvts_enable_all_sensing_points();
+
+	lvts_set_init_flag();
+
+	printk(BIOS_INFO, "%s: thermal initialized\n", __func__);
+
+	read_all_tc_lvts_temperature();
+}
diff --git a/src/soc/mediatek/common/thermal_sram.c b/src/soc/mediatek/common/thermal_sram.c
new file mode 100644
index 0000000000..3282c84599
--- /dev/null
+++ b/src/soc/mediatek/common/thermal_sram.c
@@ -0,0 +1,36 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <arch/cache.h>
+#include <soc/thermal.h>
+
+void thermal_cls_sram(void)
+{
+	int i = 0;
+	const uint32_t pattern = 0x27BC86AA;
+	uint32_t *buff = (uint32_t *)THERMAL_SRAM_BASE;
+	for (i = 0; i < THERMAL_SRAM_LEN / sizeof(*buff); i++) {
+		*buff = pattern;
+		buff++;
+	}
+	dcache_clean_invalidate_by_mva((void *)THERMAL_SRAM_BASE, THERMAL_SRAM_LEN);
+}
+
+void thermal_stat_cls_sram(void)
+{
+	int i = 0;
+	const uint32_t pattern = 0xFFFFFFFF;
+	uint32_t *buff = (uint32_t *)THERMAL_STAT_SRAM_BASE;
+	for (i = 0; i < THERMAL_STAT_SRAM_LEN / sizeof(*buff); i++) {
+		*buff = pattern;
+		buff++;
+	}
+	dcache_clean_invalidate_by_mva((void *)THERMAL_STAT_SRAM_BASE, THERMAL_STAT_SRAM_LEN);
+}
+
+__weak void thermal_write_reboot_temp_sram(uint32_t value)
+{
+}
+
+__weak void thermal_write_reboot_msr_sram(unsigned int idx, uint32_t value)
+{
+}
diff --git a/src/soc/mediatek/mt8196/Makefile.mk b/src/soc/mediatek/mt8196/Makefile.mk
index 9426d157db..762dcb17cb 100644
--- a/src/soc/mediatek/mt8196/Makefile.mk
+++ b/src/soc/mediatek/mt8196/Makefile.mk
@@ -50,8 +50,8 @@ romstage-y += ../common/pmif.c pmif_init.c
 romstage-y += ../common/rtc.c ../common/rtc_osc_init.c
 romstage-y += ../common/pmif_spmi_v2.c pmif_spmi.c
 romstage-y += ../common/srclken_rc.c srclken_rc.c
-romstage-y += thermal.c
-romstage-y += thermal_sram.c
+romstage-y += ../common/thermal.c thermal.c
+romstage-y += ../common/thermal_sram.c thermal_sram.c
 
 ramstage-$(CONFIG_ARM64_USE_ARM_TRUSTED_FIRMWARE) += ../common/bl31.c
 ramstage-y += dcc.c
diff --git a/src/soc/mediatek/mt8196/include/soc/thermal.h b/src/soc/mediatek/mt8196/include/soc/thermal.h
index 2494853f99..b1bab82099 100644
--- a/src/soc/mediatek/mt8196/include/soc/thermal.h
+++ b/src/soc/mediatek/mt8196/include/soc/thermal.h
@@ -3,9 +3,6 @@
 #ifndef SOC_MEDIATEK_MT8196_THERMAL_H
 #define SOC_MEDIATEK_MT8196_THERMAL_H
 
-void thermal_sram_init(void);
-void thermal_init(void);
-void thermal_write_reboot_temp_sram(uint32_t value);
-void thermal_write_reboot_msr_sram(unsigned int idx, uint32_t value);
+#include <soc/thermal_common.h>
 
 #endif /* SOC_MEDIATEK_MT8196_THERMAL_H */
diff --git a/src/soc/mediatek/mt8196/include/soc/thermal_internal.h b/src/soc/mediatek/mt8196/include/soc/thermal_internal.h
index 65c053d21e..180c349b9c 100644
--- a/src/soc/mediatek/mt8196/include/soc/thermal_internal.h
+++ b/src/soc/mediatek/mt8196/include/soc/thermal_internal.h
@@ -3,16 +3,20 @@
 #ifndef SOC_MEDIATEK_MT8196_THERMAL_INTERNAL_H
 #define SOC_MEDIATEK_MT8196_THERMAL_INTERNAL_H
 
-#include <console/console.h>
-#include <device/mmio.h>
 #include <soc/addressmap.h>
 #include <soc/symbols.h>
-#include <soc/thermal.h>
-#include <stddef.h>
 
 #define LVTS_MAGIC                      0x0000555
 #define MAX_TS_NUMBER			4
 
+/* SRAM for Thermal */
+#define THERMAL_SRAM_BASE		(_mcufw_reserved + 0x1000)
+#define THERMAL_SRAM_LEN		0x400
+
+/* SRAM for Thermal state */
+#define THERMAL_STAT_SRAM_BASE		((uintptr_t)_sram + 0x0001A800)
+#define THERMAL_STAT_SRAM_LEN		0x400
+
 /* private thermal sensor enum */
 enum lvts_sensor {
 	L_TS_LVTS11_0 = 0,	/* LVTS11-0 SOC-TOP */
@@ -37,30 +41,6 @@ enum lvts_tc_offset {
 	TS_OFFSET_AP_CONTROLLER1 = 0x100,
 };
 
-enum sensor_switch_status {
-	SEN_OFF,
-	SEN_ON,
-};
-
-struct lvts_thermal_controller_speed {
-	uint32_t group_interval_delay;
-	uint32_t period_unit;
-	uint32_t filter_interval_delay;
-	uint32_t sensor_interval_delay;
-};
-
-struct lvts_thermal_controller {
-	enum lvts_sensor ts[MAX_TS_NUMBER];
-	enum sensor_switch_status sensor_on_off[MAX_TS_NUMBER];
-	size_t ts_number;
-	int reboot_temperature;
-	int dominator_ts_idx;
-	unsigned int reboot_msr_sram_idx;
-	bool has_reboot_temp_sram;
-	struct lvts_thermal_controller_speed speed;
-	struct mtk_thermal_controller_regs *regs;
-};
-
 /* LVTS Thermal Controller Register Definition */
 static struct mtk_thermal_controller_regs *const
 	mtk_lvts_ap_controller0 = (void *)(THERM_CTRL_BASE + TS_OFFSET_AP_CONTROLLER0);
@@ -154,8 +134,10 @@ check_member(mtk_thermal_controller_regs, lvtsspare, 0x0f0);
 #define AP_RST_CLR			(INFRACFG_AO_SEC_BASE + 0xf34)
 
 #define LVTS_COF_T_SLP_GLD		391460
+#define LVTS_COEFF_A			LVTS_COF_T_SLP_GLD
 #define LVTS_COF_COUNT_R_GLD		34412
 #define LVTS_COF_T_CONST_OFS		0
+#define LVTS_GROUP_INTERVAL_DELAY_MASK	GENMASK(31, 17)
 
 #define DEFAULT_EFUSE_GOLDEN_TEMP	60
 #define DEFAULT_EFUSE_COUNT		34389
diff --git a/src/soc/mediatek/mt8196/thermal.c b/src/soc/mediatek/mt8196/thermal.c
index 7ea2725283..ef4f73eaca 100644
--- a/src/soc/mediatek/mt8196/thermal.c
+++ b/src/soc/mediatek/mt8196/thermal.c
@@ -3,11 +3,10 @@
 #include <assert.h>
 #include <console/console.h>
 #include <delay.h>
+#include <device/mmio.h>
 #include <soc/thermal.h>
-#include <soc/thermal_internal.h>
 
 #define LVTS_DEVICE_ACCESS_DELAY_US		3
-#define CHECK_DEVICE_ACCESS_RETRY_CNT		100
 #define THERMAL_LVTS_MSR_OFT			64552
 #define LVTS_READ_ID_DELAY_US			3
 #define LVTS_READ_ID_RETRY_CNT			5
@@ -44,6 +43,7 @@ static const struct lvts_thermal_controller lvts_tscpu_g_tc[LVTS_CONTROLLER_NUM]
 		.reboot_temperature = 118800,
 		.dominator_ts_idx = 0,
 		.reboot_msr_sram_idx = 0,
+		.has_reboot_msr_sram = true,
 		.has_reboot_temp_sram = true,
 		.speed = {
 			.group_interval_delay = 0x7fff,
@@ -60,6 +60,7 @@ static const struct lvts_thermal_controller lvts_tscpu_g_tc[LVTS_CONTROLLER_NUM]
 		.reboot_temperature = 118800,
 		.dominator_ts_idx = 0,
 		.reboot_msr_sram_idx = 1,
+		.has_reboot_msr_sram = true,
 		.has_reboot_temp_sram = false,
 		.speed = {
 			.group_interval_delay = 0x7fff,
@@ -75,58 +76,24 @@ static uint32_t golden_temp;
 static uint32_t ts_edata[L_TS_LVTS_NUM];
 static uint8_t op_cali[LVTS_CONTROLLER_NUM];
 
-static int lvts_write_device(uint16_t config, uint8_t dev_reg_idx, uint8_t data, int tc_num)
+const struct lvts_thermal_controller *lvts_get_controller(int tc_num)
 {
-	const struct lvts_thermal_controller *tc = &lvts_tscpu_g_tc[tc_num];
-	uint32_t config_data = (config << 16) | (dev_reg_idx << 8) | data;
+	assert(tc_num < LVTS_CONTROLLER_NUM);
 
-	write32(&tc->regs->lvts_config_0, config_data);
-
-	/*
-	 * LVTS Device Register Setting takes 1us (by 26MHz clock source)
-	 * interface latency to access.
-	 * So we set 2~3 us delay could guarantee access complete.
-	 */
-	udelay(LVTS_DEVICE_ACCESS_DELAY_US);
-
-	/*
-	 * Check ASIF bus status for transaction finished
-	 * Wait until DEVICE_ACCESS_START = 0
-	 */
-	if (!retry(CHECK_DEVICE_ACCESS_RETRY_CNT,
-		   !(read32(&tc->regs->lvts_config_0) & DEVICE_ACCESS_START_BIT), udelay(2))) {
-		printk(BIOS_ERR, "DEVICE_ACCESS_START didn't ready, reg0x%x\n",
-		       dev_reg_idx);
-	}
-
-	return 1;
-}
-
-static int lvts_raw_to_temp(uint16_t msr_raw, enum lvts_sensor ts_name)
-{
-	/* In millidegree Celsius */
-	int temp_mc;
-	int64_t temp1, coff_a;
-
-	coff_a = LVTS_COF_T_SLP_GLD;
-
-	temp1 = (coff_a * msr_raw) / (1 << 14);
-	temp_mc = temp1 + golden_temp * 500 - coff_a;
-
-	return temp_mc;
+	return &lvts_tscpu_g_tc[tc_num];
 }
 
 /*
  * The return value is NOT the same as the argument `msr_raw` of lvts_raw_to_temp.
  * Instead, it is equal to "(1 << 28) / msr_raw".
  */
-static uint16_t lvts_temp_to_raw(int temp_mc, enum lvts_sensor ts_name)
+uint16_t lvts_temp_to_raw(int temp_mc, enum lvts_sensor ts_name)
 {
 	uint32_t msr_raw = 0;
 	int64_t coff_a = 0;
 	int64_t temp1;
 
-	coff_a = LVTS_COF_T_SLP_GLD;
+	coff_a = LVTS_COEFF_A;
 
 	temp1 = (int64_t)temp_mc - (golden_temp * 500) + coff_a;
 	assert(temp1 > 0);
@@ -137,7 +104,7 @@ static uint16_t lvts_temp_to_raw(int temp_mc, enum lvts_sensor ts_name)
 	return msr_raw;
 }
 
-static void lvts_efuse_setting(void)
+void lvts_efuse_setting(void)
 {
 	int i, j, s_index;
 	uint32_t efuse_data;
@@ -145,8 +112,8 @@ static void lvts_efuse_setting(void)
 
 	printk(BIOS_INFO, "%s\n", __func__);
 
-	for (i = 0; i < ARRAY_SIZE(lvts_tscpu_g_tc); i++) {
-		const struct lvts_thermal_controller *tc = &lvts_tscpu_g_tc[i];
+	for (i = 0; i < LVTS_CONTROLLER_NUM; i++) {
+		const struct lvts_thermal_controller *tc = lvts_get_controller(i);
 		val_0 = 0;
 		val_1 = 0;
 		for (j = 0; j < tc->ts_number; j++) {
@@ -196,14 +163,14 @@ static void lvts_efuse_setting(void)
 	}
 }
 
-static void lvts_device_identification(void)
+void lvts_device_identification(void)
 {
 	uint32_t dev_id, data;
 	int i;
 
 	printk(BIOS_INFO, "===== %s begin ======\n", __func__);
-	for (i = 0; i < ARRAY_SIZE(lvts_tscpu_g_tc); i++) {
-		const struct lvts_thermal_controller *tc = &lvts_tscpu_g_tc[i];
+	for (i = 0; i < LVTS_CONTROLLER_NUM; i++) {
+		const struct lvts_thermal_controller *tc = lvts_get_controller(i);
 		/* Enable LVTS_CTRL Clock */
 		write32(&tc->regs->lvtsclken_0, 0x00000001);
 
@@ -228,12 +195,12 @@ static void lvts_device_identification(void)
 	}
 }
 
-static void lvts_device_enable_init_all_devices(void)
+void lvts_device_enable_init_all_devices(void)
 {
 	int i;
 	uint8_t cali_0, cali_1;
 
-	for (i = 0; i < ARRAY_SIZE(lvts_tscpu_g_tc); i++) {
+	for (i = 0; i < LVTS_CONTROLLER_NUM; i++) {
 		/* Stop Counting (RG_TSFM_ST=0) */
 		lvts_write_device(LVTS_DEVICE_WRITE_CONFIG, 0x03, 0x00, i);
 
@@ -252,7 +219,7 @@ static void lvts_device_enable_init_all_devices(void)
 	}
 }
 
-static void lvts_thermal_cal_prepare(void)
+void lvts_thermal_cal_prepare(void)
 {
 	uint32_t temp[7];
 	int i, j;
@@ -316,38 +283,7 @@ static void lvts_thermal_cal_prepare(void)
 	write32(&lvts_tscpu_g_tc[LVTS_AP_CONTROLLER0].regs->lvtsspare[1], golden_temp);
 }
 
-static int lvts_read_tc_raw_and_temp(void *msr_reg, enum lvts_sensor ts_name)
-{
-	int temp;
-	uint32_t msr_data;
-	uint16_t msr_raw;
-
-	msr_data = read32(msr_reg);
-	msr_raw = msr_data & 0xFFFF;
-
-	if (msr_raw > 0) {
-		temp = lvts_raw_to_temp(msr_raw, ts_name);
-	} else {
-		/*
-		 * 26111 is magic num.
-		 * This is to keep system alive for a while to wait until
-		 * HW init is done, because 0 msr raw will translate to 28x'C
-		 * and then 28x'C will trigger a SW reset.
-		 *
-		 * If HW init finishes, this msr raw will not be 0,
-		 * system can report normal temperature.
-		 * If wait over 60 times zero, this means something wrong with HW.
-		 */
-		temp = 26111;
-	}
-
-	printk(BIOS_INFO, "[LVTS_MSR] ts%d msr_all=%x, msr_temp=%d, temp=%d\n", ts_name,
-	       msr_data, msr_raw, temp);
-
-	return temp;
-}
-
-static void lvts_tscpu_thermal_read_tc_temp(const struct lvts_thermal_controller *tc, int order)
+void lvts_tscpu_thermal_read_tc_temp(const struct lvts_thermal_controller *tc, int order)
 {
 	uint32_t rg_temp;
 	enum lvts_sensor ts_name = tc->ts[order];
@@ -355,163 +291,16 @@ static void lvts_tscpu_thermal_read_tc_temp(const struct lvts_thermal_controller
 
 	ASSERT(order < ARRAY_SIZE(tc->regs->lvtsatp));
 
-	temperature = lvts_read_tc_raw_and_temp(&tc->regs->lvtsatp[order], ts_name);
+	temperature = lvts_read_tc_raw_and_temp(&tc->regs->lvtsatp[order],
+						ts_name,
+						golden_temp);
 	rg_temp = read32(&tc->regs->lvtstemp[order]) & 0x7FFFFF;
 
 	printk(BIOS_INFO, "%s order %d ts_name %d temp %d rg_temp %d(%d)\n", __func__, order,
 	       ts_name, temperature, (rg_temp * 1000 / 1024), rg_temp);
 }
 
-static void read_all_tc_lvts_temperature(void)
-{
-	int i, j;
-
-	for (i = 0; i < ARRAY_SIZE(lvts_tscpu_g_tc); i++) {
-		const struct lvts_thermal_controller *tc = &lvts_tscpu_g_tc[i];
-		for (j = 0; j < tc->ts_number; j++)
-			lvts_tscpu_thermal_read_tc_temp(tc, j);
-	}
-}
-
-static void lvts_enable_sensing_points(const struct lvts_thermal_controller *tc)
-{
-	int i;
-
-	printk(BIOS_INFO, "===== %s begin ======\n", __func__);
-	uint32_t value = LVTS_SINGLE_SENSE_MODE_EN;
-
-	for (i = 0; i < tc->ts_number; i++) {
-		if (tc->sensor_on_off[i] == SEN_ON)
-			value |= BIT(i);
-	}
-
-	write32(&tc->regs->lvtsmonctl0_0, value);
-
-	printk(BIOS_INFO, "%s, value in LVTSMONCTL0_0 = %#x\n", __func__, value);
-}
-
-/*
- * disable ALL periodoc temperature sensing point
- */
-static void lvts_disable_all_sensing_points(void)
-{
-	int i = 0;
-
-	printk(BIOS_INFO, "%s\n", __func__);
-
-	for (i = 0; i < ARRAY_SIZE(lvts_tscpu_g_tc); i++) {
-		const struct lvts_thermal_controller *tc = &lvts_tscpu_g_tc[i];
-		write32(&tc->regs->lvtsmonctl0_0, LVTS_SINGLE_SENSE_MODE_EN);
-	}
-}
-
-static int lvts_check_all_sensing_points_idle(void)
-{
-	uint32_t mask, temp;
-	int i;
-
-	mask = BIT(10) | BIT(7) | BIT(0);
-	for (i = 0; i < ARRAY_SIZE(lvts_tscpu_g_tc); i++) {
-		const struct lvts_thermal_controller *tc = &lvts_tscpu_g_tc[i];
-		temp = read32(&tc->regs->lvtsmsrctl1_0);
-		if ((temp & mask) != 0)
-			return -1;
-	}
-
-	return 0;
-}
-
-static void lvts_wait_all_sensing_points_idle(void)
-{
-	if (!retry(CHECK_SENSING_POINTS_IDLE_RETRY_CNT,
-		   lvts_check_all_sensing_points_idle() == 0,
-		   udelay(2)))
-		printk(BIOS_ERR, "%s timeout\n", __func__);
-}
-
-static void lvts_enable_all_sensing_points(void)
-{
-	int i = 0;
-
-	printk(BIOS_INFO, "%s\n", __func__);
-
-	for (i = 0; i < ARRAY_SIZE(lvts_tscpu_g_tc); i++) {
-		const struct lvts_thermal_controller *tc = &lvts_tscpu_g_tc[i];
-		lvts_enable_sensing_points(tc);
-	}
-}
-
-static void lvts_set_init_flag(void)
-{
-	int i;
-
-	printk(BIOS_INFO, "%s\n", __func__);
-
-	/* write init done flag to inform kernel */
-
-	for (i = 0; i < ARRAY_SIZE(lvts_tscpu_g_tc); i++) {
-		const struct lvts_thermal_controller *tc = &lvts_tscpu_g_tc[i];
-		printk(BIOS_INFO, "%s %d:%zu, tc_base_addr:%p\n", __func__, i,
-		       tc->ts_number, tc->regs);
-
-		write32(&tc->regs->lvtsspare[0], LVTS_MAGIC);
-	}
-}
-
-static void lvts_configure_polling_speed_and_filter(const struct lvts_thermal_controller *tc)
-{
-	uint32_t lvts_mon_ctl1, lvts_mon_ctl2;
-
-	lvts_mon_ctl1 = (((tc->speed.group_interval_delay << 17) & GENMASK(31, 17)) |
-		(tc->speed.period_unit & GENMASK(9, 0)));
-
-	lvts_mon_ctl2 = (((tc->speed.filter_interval_delay << 16) & GENMASK(25, 16)) |
-		(tc->speed.sensor_interval_delay & GENMASK(9, 0)));
-
-	/*
-	 * Calculate period unit in Module clock x 256, and the Module clock
-	 * will be changed to 26M when Infrasys enters Sleep mode.
-	 */
-
-	/*
-	 * bus clock 66M counting unit is
-	 * 12 * 1/66M * 256 = 12 * 3.879us = 46.545 us
-	 */
-	write32(&tc->regs->lvtsmonctl1_0, lvts_mon_ctl1);
-	/*
-	 * filt interval is 1 * 46.545us = 46.545us,
-	 * sen interval is 429 * 46.545us = 19.968ms
-	 */
-	write32(&tc->regs->lvtsmonctl2_0, lvts_mon_ctl2);
-
-	/* temperature sampling control, 1 sample */
-	write32(&tc->regs->lvtsmsrctl0_0, 0);
-
-	udelay(1);
-	printk(BIOS_INFO, "%s, LVTSMONCTL1_0= 0x%x,LVTSMONCTL2_0= 0x%x,LVTSMSRCTL0_0= 0x%x\n",
-	       __func__, read32(&tc->regs->lvtsmonctl1_0), read32(&tc->regs->lvtsmonctl2_0),
-	       read32(&tc->regs->lvtsmsrctl0_0));
-}
-
-static void lvts_tscpu_thermal_initial_all_tc(void)
-{
-	uint32_t i = 0;
-
-	printk(BIOS_INFO, "%s\n", __func__);
-
-	for (i = 0; i < ARRAY_SIZE(lvts_tscpu_g_tc); i++) {
-		const struct lvts_thermal_controller *tc = &lvts_tscpu_g_tc[i];
-		/*  set sensor index of LVTS */
-		write32(&tc->regs->lvtstssel_0, LVTS_SENSOR_POINT_SELECTION_SETTING);
-		/*  set calculation scale rules */
-		write32(&tc->regs->lvtscalscale_0, LVTS_CALCULATION_SCALING_RULE);
-
-		lvts_configure_polling_speed_and_filter(tc);
-	}
-
-}
-
-static void lvts_tscpu_reset_thermal(void)
+void lvts_tscpu_reset_thermal(void)
 {
 	/* Enable thermal control software reset */
 	write32p(AP_RST_SET, BIT(11));
@@ -520,104 +309,6 @@ static void lvts_tscpu_reset_thermal(void)
 	write32p(AP_RST_CLR, BIT(11));
 }
 
-static void lvts_set_tc_trigger_hw_protect(const struct lvts_thermal_controller *tc)
-{
-	int d_index, i;
-	uint32_t raw_high;
-	uint16_t raw;
-	enum lvts_sensor ts_name;
-
-	if (tc->dominator_ts_idx < tc->ts_number) {
-		d_index = tc->dominator_ts_idx;
-	} else {
-		printk(BIOS_ERR, "LVTS, dominator_ts_idx %d >= ts_number %zu; use idx 0\n",
-		       tc->dominator_ts_idx, tc->ts_number);
-		d_index = 0;
-	}
-
-	ts_name = tc->ts[d_index];
-
-	printk(BIOS_INFO, "%s, the dominator ts_name is %d\n", __func__, ts_name);
-
-	/* Maximum of 4 sensing points */
-	raw_high = 0;
-	for (i = 0; i < tc->ts_number; i++) {
-		ts_name = tc->ts[i];
-		raw = lvts_temp_to_raw(tc->reboot_temperature, ts_name);
-		raw_high = MAX(raw_high, raw);
-	}
-
-	thermal_write_reboot_msr_sram(tc->reboot_msr_sram_idx, raw_high);
-	if (tc->has_reboot_temp_sram)
-		thermal_write_reboot_temp_sram(tc->reboot_temperature);
-
-	setbits32(&tc->regs->lvtsprotctl_0, 0x3FFF);
-	/* disable trigger SPM interrupt */
-	write32(&tc->regs->lvtsmonint_0, 0);
-
-	clrsetbits32(&tc->regs->lvtsprotctl_0, 0xF << 16, BIT(16));
-
-	write32(&tc->regs->lvtsprottc_0, raw_high);
-
-	/* enable trigger Hot SPM interrupt */
-	write32(&tc->regs->lvtsmonint_0, STAGE3_INT_EN);
-
-	clrbits32(&tc->regs->lvtsprotctl_0, 0xFFFF);
-}
-
-static void lvts_config_all_tc_hw_protect(void)
-{
-	int i = 0;
-
-	printk(BIOS_INFO, "===== %s begin ======\n", __func__);
-
-	for (i = 0; i < ARRAY_SIZE(lvts_tscpu_g_tc); i++) {
-		const struct lvts_thermal_controller *tc = &lvts_tscpu_g_tc[i];
-		lvts_set_tc_trigger_hw_protect(tc);
-	}
-}
-
-static bool lvts_lk_init_check(void)
-{
-	int i;
-
-	for (i = 0; i < ARRAY_SIZE(lvts_tscpu_g_tc); i++) {
-		const struct lvts_thermal_controller *tc = &lvts_tscpu_g_tc[i];
-		/* Check LVTS device ID */
-		if ((read32(&tc->regs->lvtsspare[0]) & GENMASK(11, 0)) != LVTS_MAGIC)
-			return false;
-	}
-
-	return true;
-}
-
-static void lvts_thermal_init(void)
-{
-	printk(BIOS_INFO, "===== %s begin ======\n", __func__);
-
-	if (lvts_lk_init_check())
-		return;
-
-	lvts_tscpu_reset_thermal();
-
-	lvts_thermal_cal_prepare();
-	lvts_device_identification();
-	lvts_device_enable_init_all_devices();
-	lvts_efuse_setting();
-
-	lvts_disable_all_sensing_points();
-	lvts_wait_all_sensing_points_idle();
-	lvts_tscpu_thermal_initial_all_tc();
-	lvts_config_all_tc_hw_protect();
-	lvts_enable_all_sensing_points();
-
-	lvts_set_init_flag();
-
-	printk(BIOS_INFO, "%s: thermal initialized\n", __func__);
-
-	read_all_tc_lvts_temperature();
-}
-
 static void reset_cpu_lvts(void)
 {
 	write32p(CPU_LVTS_RESET_ADDR, 1);
diff --git a/src/soc/mediatek/mt8196/thermal_sram.c b/src/soc/mediatek/mt8196/thermal_sram.c
index eb36bf478e..789f240024 100644
--- a/src/soc/mediatek/mt8196/thermal_sram.c
+++ b/src/soc/mediatek/mt8196/thermal_sram.c
@@ -2,44 +2,14 @@
 
 #include <arch/cache.h>
 #include <assert.h>
-#include <soc/thermal_internal.h>
-#include <string.h>
+#include <device/mmio.h>
+#include <soc/thermal.h>
 
 /* SRAM for Thermal */
-#define THERMAL_SRAM_BASE		(_mcufw_reserved + 0x1000)
-#define THERMAL_SRAM_LEN		0x400
 #define THERMAL_REBOOT_TEMP_SRAM_OFFSET	0x39C
 #define THERMAL_REBOOT_MSR_SRAM_OFFSET	0x340
 #define THERMAL_REBOOT_MSR_SRAM_LEN	(6 * 4)
 
-static void thermal_cls_sram(void)
-{
-	int i = 0;
-	const uint32_t pattern = 0x27BC86AA;
-	uint32_t *buff = (uint32_t *)THERMAL_SRAM_BASE;
-	for (i = 0; i < THERMAL_SRAM_LEN / sizeof(*buff); i++) {
-		*buff = pattern;
-		buff++;
-	}
-	dcache_clean_invalidate_by_mva((void *)THERMAL_SRAM_BASE, THERMAL_SRAM_LEN);
-}
-
-/* SRAM for Thermal state */
-#define THERMAL_STAT_SRAM_BASE		((uintptr_t)_sram + 0x0001A800)
-#define THERMAL_STAT_SRAM_LEN		0x400
-
-static void thermal_stat_cls_sram(void)
-{
-	int i = 0;
-	const uint32_t pattern = 0xFFFFFFFF;
-	uint32_t *buff = (uint32_t *)THERMAL_STAT_SRAM_BASE;
-	for (i = 0; i < THERMAL_STAT_SRAM_LEN / sizeof(*buff); i++) {
-		*buff = pattern;
-		buff++;
-	}
-	dcache_clean_invalidate_by_mva((void *)THERMAL_STAT_SRAM_BASE, THERMAL_STAT_SRAM_LEN);
-}
-
 /* SRAM for GPU Thermal state */
 #define GPU_THERMAL_STAT_SRAM_BASE	((uintptr_t)_sram + 0x00017C00)
 #define GPU_THERMAL_STAT_SRAM_LEN	0x400

From a775bfc2b2320fe062cf9a561806fe4af8b04073 Mon Sep 17 00:00:00 2001
From: Gavin Liu <gavin.liu@mediatek.corp-partner.google.com>
Date: Fri, 25 Apr 2025 16:24:41 +0800
Subject: [PATCH 1576/3886] soc/mediatek/mt8189: Specify MTKLIB_PATH for
 building BL31

Add BL31 static library path to BL31 build argument.

BUG=b:379008996
BRANCH=none
TEST=build passed

Signed-off-by: Gavin Liu <gavin.liu@mediatek.corp-partner.google.com>
Change-Id: I718be15e1a9b6942558ce929baedec18bdcd3309
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88448
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
---
 src/soc/mediatek/mt8189/Makefile.mk | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/src/soc/mediatek/mt8189/Makefile.mk b/src/soc/mediatek/mt8189/Makefile.mk
index 2f73bcc1f0..f7294c0e74 100644
--- a/src/soc/mediatek/mt8189/Makefile.mk
+++ b/src/soc/mediatek/mt8189/Makefile.mk
@@ -67,6 +67,12 @@ CPPFLAGS_common += -Isrc/soc/mediatek/common/dp/include
 
 MT8189_BLOB_DIR := 3rdparty/blobs/soc/mediatek/mt8189
 
+BL31_LIB := $(top)/$(MT8189_BLOB_DIR)/libbl31.a
+
+ifneq ($(wildcard $(BL31_LIB)),)
+BL31_MAKEARGS += MTKLIB_PATH=$(BL31_LIB)
+endif
+
 firmware-files := \
 	$(CONFIG_DPM_DM_FIRMWARE) \
 	$(CONFIG_DPM_PM_FIRMWARE) \

From 79bd154b49bed8ca951fec44312ffaf5c75a4cd3 Mon Sep 17 00:00:00 2001
From: Victor Shih <victorshihgli@gmail.com>
Date: Thu, 3 Jul 2025 12:27:46 +0000
Subject: [PATCH 1577/3886] drivers/genesyslogic/gl9763e: Mask replay timer
 timeout of AER

Due to a flaw in the hardware design, the GL9763e replay timer
frequently times out when ASPM is enabled. As a result, the warning
messages will often appear in the system log when the system accesses
the GL9763e PCI config. Therefore, the replay timer timeout must be
masked.

BUG=b:428025481

Sample output on screen:
PCIe Bus Error: severity=Corrected, type=Data Link Layer
device [17a0:e763] error status/mask=00001000/00002000
 [12] Timeout

Change-Id: I6f921f40f169d7811b7bd51145023b549e8aee1c
Signed-off-by: Victor Shih <victorshihgli@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88291
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/drivers/genesyslogic/gl9763e/gl9763e.c | 11 ++++++++++-
 1 file changed, 10 insertions(+), 1 deletion(-)

diff --git a/src/drivers/genesyslogic/gl9763e/gl9763e.c b/src/drivers/genesyslogic/gl9763e/gl9763e.c
index 136c585d95..98e69bb3f8 100644
--- a/src/drivers/genesyslogic/gl9763e/gl9763e.c
+++ b/src/drivers/genesyslogic/gl9763e/gl9763e.c
@@ -5,13 +5,15 @@
 #include <console/console.h>
 #include <device/device.h>
 #include <device/pci.h>
+#include <device/pciexp.h>
 #include <device/pci_ops.h>
 #include <device/pci_ids.h>
 #include "gl9763e.h"
 
 static void gl9763e_init(struct device *dev)
 {
-	uint32_t ver;
+	uint32_t ver, value;
+	int aer;
 
 	printk(BIOS_INFO, "GL9763E: init\n");
 	pci_dev_init(dev);
@@ -41,6 +43,13 @@ static void gl9763e_init(struct device *dev)
 	pci_update_config32(dev, SD_CLKRX_DLY, ~HS400_RX_DELAY_MASK, HS400_RX_DELAY);
 	/* Disable Slow mode */
 	pci_and_config32(dev, EMMC_CTL, ~SLOW_MODE);
+	/* mask the replay timer timeout of AER */
+	aer = pciexp_find_extended_cap(dev, PCI_EXT_CAP_ID_ERR, 0);
+	if (aer) {
+		value = pci_read_config32(dev, aer + PCI_ERR_COR_MASK);
+		value |= PCI_ERR_COR_REP_TIMER;
+		pci_write_config32(dev, aer + PCI_ERR_COR_MASK, value);
+	}
 	/* Set VHS to read-only */
 	pci_update_config32(dev, VHS, ~VHS_REV_MASK, VHS_REV_R);
 }

From e9af95d5ab8b088c966b12d5750b8118fa217a5a Mon Sep 17 00:00:00 2001
From: Jamie Ryu <jamie.m.ryu@intel.com>
Date: Mon, 28 Apr 2025 00:25:12 -0700
Subject: [PATCH 1578/3886] soc/intel/pantherlake: Configure FSP UPDs for
 minimum assertion widths

This configures FSP UPDs for PCH PM minimum assertion widths and
reset power cycle duration per mainboard variants configuration.
This also checks the reset power cycle duration is not be smaller
than SLP_S3, SLP_S4 and SLP_A Minimum Assertion Width.

 PchPmSlpS3MinAssert: SLP_S3 Minimum Assertion Width Policy
 PchPmSlpS4MinAssert: SLP_S4 Minimum Assertion Width Policy
 PchPmSlpSusMinAssert: SLP_SUS Minimum Assertion Width Policy
 PchPmSlpAMinAssert: SLP_A Minimum Assertion Width Policy
 PchPmPwrCycDur: PCH PM Reset Power Cycle Duration
  The Reset Power Cycle Duration starts at 20ms and increases by 20ms
  for each step, beginning from 0x0 to 0xFF. Each subsequent increment
  corresponds to an additional 20 milliseconds in duration.

Reference:
 Panther Lake External Design Specification (EDS) Volume 2 (#813032)

BUG=None
TEST=Build a fatcat coreboot and boot to OS without an issue.

Change-Id: I7234c7539c1e7eb5e2b8c04ccff6c62c853d6807
Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88443
Reviewed-by: Pranava Y N <pranavayn@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
---
 src/soc/intel/pantherlake/chip.h       | 56 ++++++++++++++++++++++++++
 src/soc/intel/pantherlake/fsp_params.c | 45 +++++++++++++++++++++
 2 files changed, 101 insertions(+)

diff --git a/src/soc/intel/pantherlake/chip.h b/src/soc/intel/pantherlake/chip.h
index 53168ff662..e060a28bb3 100644
--- a/src/soc/intel/pantherlake/chip.h
+++ b/src/soc/intel/pantherlake/chip.h
@@ -521,6 +521,62 @@ struct soc_intel_pantherlake_config {
 		ISA_SERIAL_BASE_ADDR_2F8,
 	} isa_serial_uart_base;
 
+	/* PCH PM SLP_S3 Minimum Assertion Width */
+	enum {
+		SLP_S3_ASSERTION_DEFAULT,
+		SLP_S3_ASSERTION_60_US,
+		SLP_S3_ASSERTION_1_MS,
+		SLP_S3_ASSERTION_50_MS,
+		SLP_S3_ASSERTION_2_S,
+	} pch_slp_s3_min_assertion_width;
+
+	/* PCH PM SLP_S4 Minimum Assertion Width */
+	enum {
+		SLP_S4_ASSERTION_DEFAULT,
+		SLP_S4_ASSERTION_1S,
+		SLP_S4_ASSERTION_2S,
+		SLP_S4_ASSERTION_3S,
+		SLP_S4_ASSERTION_4S,
+	} pch_slp_s4_min_assertion_width;
+
+	/* PCH PM SLP_SUS Minimum Assertion Width */
+	enum {
+		SLP_SUS_ASSERTION_DEFAULT,
+		SLP_SUS_ASSERTION_0_MS,
+		SLP_SUS_ASSERTION_500_MS,
+		SLP_SUS_ASSERTION_1_S,
+		SLP_SUS_ASSERTION_4_S,
+	} pch_slp_sus_min_assertion_width;
+
+	/* PCH PM SLP_A Minimum Assertion Width */
+	enum {
+		SLP_A_ASSERTION_DEFAULT,
+		SLP_A_ASSERTION_0_MS,
+		SLP_A_ASSERTION_4_S,
+		SLP_A_ASSERTION_98_MS,
+		SLP_A_ASSERTION_2_S,
+	} pch_slp_a_min_assertion_width;
+
+	/*
+	 * PCH PM Reset Power Cycle Duration
+	 * The Reset Power Cycle Duration starts at 20ms and increases by 20ms for each step,
+	 * beginning from 0x0 in hexadecimal. Each subsequent hexadecimal increment corresponds
+	 * to an additional 20 milliseconds in duration.
+	 * NOTE: Duration programmed in the PchPmPwrCycDur should never be smaller than the
+	 * stretch duration programmed in the following registers:
+	 *  - GEN_PMCON_A.SLP_S3_MIN_ASST_WDTH (PchPmSlpS3MinAssert)
+	 *  - GEN_PMCON_A.S4MAW (PchPmSlpS4MinAssert)
+	 *  - PM_CFG.SLP_A_MIN_ASST_WDTH (PchPmSlpAMinAssert)
+	 *  - PM_CFG.SLP_LAN_MIN_ASST_WDTH
+	 */
+	enum {
+		POWER_CYCLE_DURATION_DEFAULT,
+		POWER_CYCLE_DURATION_1S,
+		POWER_CYCLE_DURATION_2S,
+		POWER_CYCLE_DURATION_3S,
+		POWER_CYCLE_DURATION_4S,
+	} pch_reset_power_cycle_duration;
+
 	/*
 	 * Enable or Disable C1 C-state Auto Demotion & un-demotion
 	 * The algorithm looks at the behavior of the wake up tracker, how
diff --git a/src/soc/intel/pantherlake/fsp_params.c b/src/soc/intel/pantherlake/fsp_params.c
index 01ec0860a6..df4f350c48 100644
--- a/src/soc/intel/pantherlake/fsp_params.c
+++ b/src/soc/intel/pantherlake/fsp_params.c
@@ -10,6 +10,7 @@
 #include <fsp/ppi/mp_service_ppi.h>
 #include <intelblocks/irq.h>
 #include <intelblocks/mp_init.h>
+#include <intelblocks/pmclib.h>
 #include <intelblocks/systemagent.h>
 #include <intelblocks/xdci.h>
 #include <intelpch/lockdown.h>
@@ -663,6 +664,50 @@ static void fill_fsps_misc_power_params(FSP_S_CONFIG *s_cfg,
 
 	/* Enable/Disable PCH to CPU energy report feature. */
 	s_cfg->PchPmDisableEnergyReport = !config->pch_pm_energy_report_enable;
+
+	/* Apply PCH PM minimum assertion width settings */
+	if (config->pch_slp_s3_min_assertion_width == SLP_S3_ASSERTION_DEFAULT)
+		s_cfg->PchPmSlpS3MinAssert = SLP_S3_ASSERTION_50_MS;
+	else
+		s_cfg->PchPmSlpS3MinAssert = config->pch_slp_s3_min_assertion_width;
+
+	if (config->pch_slp_s4_min_assertion_width == SLP_S4_ASSERTION_DEFAULT)
+		s_cfg->PchPmSlpS4MinAssert = SLP_S4_ASSERTION_1S;
+	else
+		s_cfg->PchPmSlpS4MinAssert = config->pch_slp_s4_min_assertion_width;
+
+	if (config->pch_slp_sus_min_assertion_width == SLP_SUS_ASSERTION_DEFAULT)
+		s_cfg->PchPmSlpSusMinAssert = SLP_SUS_ASSERTION_4_S;
+	else
+		s_cfg->PchPmSlpSusMinAssert = config->pch_slp_sus_min_assertion_width;
+
+	if (config->pch_slp_a_min_assertion_width == SLP_A_ASSERTION_DEFAULT)
+		s_cfg->PchPmSlpAMinAssert = SLP_A_ASSERTION_2_S;
+	else
+		s_cfg->PchPmSlpAMinAssert = config->pch_slp_a_min_assertion_width;
+
+	/*
+	 * The Reset Power Cycle Duration starts at 20ms and increases by 20ms for each step,
+	 * beginning from 0x0 to 0xFF. Each subsequent increment corresponds to an additional
+	 * 20 milliseconds in duration.
+	 * PCH PM Reset Power Cycle Duration = (PchPmPwrCycDur + 1) * 20ms
+	 */
+	const uint8_t fsp_pm_pwr_cyc_dur_list[] = {
+		0xc7,	/* POWER_CYCLE_DURATION_DEFAULT */
+		0x31,	/* POWER_CYCLE_DURATION_1S */
+		0x63,	/* POWER_CYCLE_DURATION_2S */
+		0x95,	/* POWER_CYCLE_DURATION_3S */
+		0xc7	/* POWER_CYCLE_DURATION_4S */
+	};
+	if (config->pch_reset_power_cycle_duration) {
+		uint8_t pwr_cyc_dur = get_pm_pwr_cyc_dur(s_cfg->PchPmSlpS4MinAssert,
+							   s_cfg->PchPmSlpS3MinAssert,
+							   s_cfg->PchPmSlpAMinAssert,
+							   config->pch_reset_power_cycle_duration);
+		s_cfg->PchPmPwrCycDur =  fsp_pm_pwr_cyc_dur_list[pwr_cyc_dur];
+	} else {
+		s_cfg->PchPmPwrCycDur =  fsp_pm_pwr_cyc_dur_list[POWER_CYCLE_DURATION_DEFAULT];
+	}
 }
 
 static void fill_fsps_npu_params(FSP_S_CONFIG *s_cfg,

From 61b4e1983c26144172260ca3a1325b0d6bbfc736 Mon Sep 17 00:00:00 2001
From: Jamie Ryu <jamie.m.ryu@intel.com>
Date: Tue, 15 Jul 2025 17:55:44 -0700
Subject: [PATCH 1579/3886] mb/google/fatcat: Update PCH reset power cycle
 duration to 1 second

This updates FSP UPDs for PCH PM SLP minimum assertion width and reset
power cycle duration to reduce the delays during a global reset and S5
suspend and resume flow.

Reference:
 Panther Lake External Design Specification (EDS) Volume 2 (#813032)

BUG=None
TEST=Build a fatcat coreboot and issue a global reset to check the reset
delay is reduced to 1 second. Issue a lid close to suspend to S5 and
wake up by lid open to check the delay is reduced to 1 second.

Change-Id: If94917879125b1a523de131936047b497cce8ba7
Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88444
Reviewed-by: Pranava Y N <pranavayn@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
---
 .../google/fatcat/variants/baseboard/fatcat/devicetree.cb  | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/src/mainboard/google/fatcat/variants/baseboard/fatcat/devicetree.cb b/src/mainboard/google/fatcat/variants/baseboard/fatcat/devicetree.cb
index 00b4ea4506..5c73dee1e0 100644
--- a/src/mainboard/google/fatcat/variants/baseboard/fatcat/devicetree.cb
+++ b/src/mainboard/google/fatcat/variants/baseboard/fatcat/devicetree.cb
@@ -62,6 +62,13 @@ chip soc/intel/pantherlake
 	# Enable Energy Reporting
 	register "pch_pm_energy_report_enable" = "true"
 
+	# PCH PM SLP miminum assertion width and Reset Power Cycle Duration
+	register "pch_slp_s3_min_assertion_width" = "SLP_S3_ASSERTION_50_MS"
+	register "pch_slp_s4_min_assertion_width" = "SLP_S4_ASSERTION_1S"
+	register "pch_slp_sus_min_assertion_width" = "SLP_SUS_ASSERTION_1_S"
+	register "pch_slp_a_min_assertion_width" = "SLP_A_ASSERTION_98_MS"
+	register "pch_reset_power_cycle_duration" = "POWER_CYCLE_DURATION_1S"
+
 	# As per document 813278, the following PTL SoC supports Fast
 	# V-Mode (FVM) on cores (IA), Graphics (GT), and System Agent
 	# (SA). The ICC Limit is represented in 1/4 A increments,

From 138402e7ff1cff8c33cc8b2adef15664276731a6 Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Wed, 6 Jul 2022 19:51:51 +0100
Subject: [PATCH 1580/3886] soc/intel/apollolake: Create IBB, IBBL and OBB

coreboot's method of creating IFWI is to modify an existing IFWI
images by deleting the IBB, replacing the IBBL with the bootblock
and everything else is put in the OBB.

This poses a problem when using Intel's FIT or technologies such
as Boot Guard. The main problem is that the IBB is never verified by
the CSE or copied from SRAM to CAR, so the CSE cannot complete BUP
and stays in recovery mode. The vast majority of the stages in
Apollolake's Secure Boot flow is not met using this method (Intel
document number 597827 summarizes these steps).

This patch series is based on the principles of a patch from Brenton
Dong (CB:17064) creates an IBBL, IBB and OBB binaries with the
correct functions to complete the Secure Boot flow. This is to copy
the IBB from SRAM using the CSE's Ring Buffer Protocol.

These binaries can then be used by FIT or coreboot's existing
method of hacking IFWI together (IFWI_STITCH) via IFWITOOL. If it is
the latter and Boot Guard is enabled, the hashes for IFWI and "ibb+obb"
must be recreated.

Whilst this option doesn't form a complete image, the components it
builds will work as Intel intended them to once stitched correctly into
an IFWI image.

Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I0deebf04f22f3017ee0c13bf1ca7f6dcc0d458b5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65680
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
---
 src/soc/intel/apollolake/Makefile.mk          | 26 +++++++++++++++++++
 .../intel/common/firmware/Makefile.mk         |  2 ++
 2 files changed, 28 insertions(+)

diff --git a/src/soc/intel/apollolake/Makefile.mk b/src/soc/intel/apollolake/Makefile.mk
index 82937bc9a6..3f2aa3bc2f 100644
--- a/src/soc/intel/apollolake/Makefile.mk
+++ b/src/soc/intel/apollolake/Makefile.mk
@@ -205,4 +205,30 @@ else
 cpu_microcode_bins += $(wildcard 3rdparty/intel-microcode/intel-ucode/06-5c-*)
 endif
 
+$(objcbfs)/ibbl.rom: $(objcbfs)/bootblock.bin
+	cp $(objcbfs)/bootblock.bin $@
+
+$(objcbfs)/ibbm.rom: $(objcbfs)/$(call strip_quotes,$(CONFIG_IBBM_ROM_COMPONENT))
+	dd if=$(objcbfs)/$(call strip_quotes,$(CONFIG_IBBM_ROM_COMPONENT)) \
+		of=$@ skip=96 bs=1 count=$(call _toint,$(CONFIG_IBBM_ROM_SIZE))
+
+obb-deps-$(CONFIG_VBOOT) := $(obj)/gbb.region $(obj)/fwid.region
+$(objcbfs)/obb.rom: $(CBFSTOOL) $(obj)/coreboot.rom $(obb-deps-y)
+ifeq ($(CONFIG_VBOOT),y)
+	@printf "    WRITE GBB\n"
+	$(CBFSTOOL) $(obj)/coreboot.rom write -u -r GBB -i 0 -f $(obj)/gbb.region
+	$(CBFSTOOL) $(obj)/coreboot.rom write -u -r RO_FRID -i 0 -f $(obj)/fwid.region
+ifeq ($(CONFIG_VBOOT_SLOTS_RW_A),y)
+	$(CBFSTOOL) $(obj)/coreboot.rom write -u -r RW_FWID_A -i 0 -f $(obj)/fwid.region
+endif
+ifeq ($(CONFIG_VBOOT_SLOTS_RW_AB),y)
+	$(CBFSTOOL) $(obj)/coreboot.rom write -u -r RW_FWID_B -i 0 -f $(obj)/fwid.region
+endif
+endif # CONFIG_VBOOT
+	$(CBFSTOOL) $(obj)/coreboot.rom read -r OBB -f $@
+
+ifeq ($(CONFIG_IFWI_IBBM_LOAD),y)
+coreboot: $(objcbfs)/ibbl.rom $(objcbfs)/ibbm.rom $(objcbfs)/obb.rom
+endif
+
 endif # if CONFIG_SOC_INTEL_APOLLOLAKE
diff --git a/src/southbridge/intel/common/firmware/Makefile.mk b/src/southbridge/intel/common/firmware/Makefile.mk
index 1425d5a352..a4f0e2e1a9 100644
--- a/src/southbridge/intel/common/firmware/Makefile.mk
+++ b/src/southbridge/intel/common/firmware/Makefile.mk
@@ -9,7 +9,9 @@ ifeq ($(CONFIG_HAVE_INTEL_FIRMWARE),y)
 ifeq ($(CONFIG_HAVE_IFD_BIN),y)
 $(call add_intermediate, add_intel_firmware)
 else ifeq ($(CONFIG_INTEL_DESCRIPTOR_MODE_REQUIRED),y)
+ifneq ($(CONFIG_IFWI_IBBM_LOAD),y)
 show_notices:: warn_intel_firmware
+endif # CONFIG_IFWI_IBBM_LOAD
 endif
 
 IFD_BIN_PATH := $(CONFIG_IFD_BIN_PATH)

From 61b66e9a81658d8f178dec1ad003649b2e3139bc Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Wed, 6 Jul 2022 19:53:22 +0100
Subject: [PATCH 1581/3886] soc/intel/apollolake: Add function to clear MCA in
 Bank 4

Change-Id: Ic3b88e336a1cb3be5a9281ce266c7d9fb2465799
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65576
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/soc/intel/apollolake/include/soc/cpu.h | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/src/soc/intel/apollolake/include/soc/cpu.h b/src/soc/intel/apollolake/include/soc/cpu.h
index 621fe4cbb5..bbdf4ab75d 100644
--- a/src/soc/intel/apollolake/include/soc/cpu.h
+++ b/src/soc/intel/apollolake/include/soc/cpu.h
@@ -17,4 +17,14 @@ static inline void flush_l1d_to_l2(void)
 	msr.lo |= FLUSH_DL1_L2;
 	wrmsr(MSR_POWER_MISC, msr);
 }
+
+/* Clear MCA in Bank 4 */
+static inline void clear_mca_bank4(void)
+{
+	msr_t msr;
+	msr.hi = 0;
+	msr.lo = 0;
+	wrmsr(IA32_MC_STATUS(4), msr);
+}
+
 #endif /* _SOC_APOLLOLAKE_CPU_H_ */

From 2408695dd35a0c27dc16e7e173e335aefbb00878 Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Wed, 6 Jul 2022 19:55:07 +0100
Subject: [PATCH 1582/3886] soc/intel/apollolake: Add a loader for the IBB

Add a loader that will load the IBB into the CSE via the Ring Protocol
Buffer.

All registers were taken from Intel document number #336561.

Change-Id: Ia41e3909f8099d2ea864166e9ea03e10e40a1b68
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65270
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/soc/intel/apollolake/Makefile.mk          |   1 +
 src/soc/intel/apollolake/bootflow.md          |  52 +++++++
 src/soc/intel/apollolake/include/soc/loader.h |  15 ++
 src/soc/intel/apollolake/loader.c             | 138 ++++++++++++++++++
 4 files changed, 206 insertions(+)
 create mode 100644 src/soc/intel/apollolake/bootflow.md
 create mode 100644 src/soc/intel/apollolake/include/soc/loader.h
 create mode 100644 src/soc/intel/apollolake/loader.c

diff --git a/src/soc/intel/apollolake/Makefile.mk b/src/soc/intel/apollolake/Makefile.mk
index 3f2aa3bc2f..ea3e05aebf 100644
--- a/src/soc/intel/apollolake/Makefile.mk
+++ b/src/soc/intel/apollolake/Makefile.mk
@@ -12,6 +12,7 @@ bootblock-y += car.c
 bootblock-y += heci.c
 bootblock-y += gspi.c
 bootblock-y += i2c.c
+bootblock-$(CONFIG_IFWI_IBBM_LOAD) += loader.c
 bootblock-y += lpc.c
 bootblock-y += mmap_boot.c
 bootblock-y += pmutil.c
diff --git a/src/soc/intel/apollolake/bootflow.md b/src/soc/intel/apollolake/bootflow.md
new file mode 100644
index 0000000000..932cc5ed00
--- /dev/null
+++ b/src/soc/intel/apollolake/bootflow.md
@@ -0,0 +1,52 @@
+IFWI Boot Flow
+==============
+
+ ╔═══════════════════════════════════════════════════════════╗
+ ║                 BIOS Region (512 KiB maximum)             ║
+ ║ ╔════════════════════════════════════════════╗ ╔════════╗ ║
+ ║ ║                  IBBM                      ║ ║  IBBL  ║ ║
+ ║ ╚════════════════════════════════════════════╝ ╚════════╝ ║
+ ╚═══════════════════════════════════════════════════════════╝
+
+ When we enter the bootblock, the first 128k will be copied
+ into the SRAM. This will contain the IBBL partition (bootblock)
+ and whatever will fit in the IBB partition.
+
+ We can't touch the bootblock as we are running from it. The RBP
+ can handle a maximum of 0x9be2 per copy, so the contents
+ of the SRAM is typically copied in 4 equally sized chunks of
+ 0x8000.
+
+ ╔════════════════════╗    ╔════════════════════╗
+ ║   SRAM (128 KiB)   ║    ║        CAR         ║
+ ║ ╔═════╗ ╔════════╗ ║    ║ ╔════╗             ║
+ ║ ║>IBBM║ ║  IBBL  ║ ║    ║ ║IBBM║             ║
+ ║ ╚═════╝ ╚════════╝ ║    ║ ╚════╝             ║
+ ╚════════════════════╝    ╚════════════════════╝
+     🠗                                                🠕
+      🠖🠖🠖🠖🠖🠖🠖🠖🠖🠖🠖🠖🠖🠖🠖🠖🠖🠖
+
+ This means that from the bootblock, we copy the IBB in chunks of
+ 0x8000 (or less if the IBB is smaller than a chunk) into CAR.
+
+                                        ╔════════════════════╗
+                                        ║        CAR         ║
+                                        ║ ╔════════════════╗ ║
+                                        ║ ║      IBBM      ║ ║
+                                        ║ ╚════════════════╝ ║
+                                        ╚════════════════════╝
+
+ We mark it as executable by flushing the L1 cache and then jump
+ to the verstage in CAR. The first thing we do is set the IBBL to
+ be uncachable, as we no longer have a use for it.
+
+ ╔════════════════════╗
+ ║   SRAM (128 KiB)   ║
+ ║ ╔════════════════╗ ║
+ ║ ║                ║ ║
+ ║ ╚════════════════╝ ║
+ ╚════════════════════╝
+
+ We keep copying the chunks until there is none left, then send
+ one final acknowledgement to the CSE - so it can know that the
+ bootflow is complete.
diff --git a/src/soc/intel/apollolake/include/soc/loader.h b/src/soc/intel/apollolake/include/soc/loader.h
new file mode 100644
index 0000000000..cfa4792a0e
--- /dev/null
+++ b/src/soc/intel/apollolake/include/soc/loader.h
@@ -0,0 +1,15 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef _SOC_LOADER_H_
+#define _SOC_LOADER_H_
+
+/* HECI 1 offsets MMIO */
+#define HOST2CSE		0x70
+#define CSE2HOST		0x60
+
+#define CSE_RBP_LIMIT		0x9be2
+#define FIRST_CHUNK		0x8000
+
+bool load_ibb(uint32_t ibb_dst, uint32_t ibb_size);
+
+#endif
diff --git a/src/soc/intel/apollolake/loader.c b/src/soc/intel/apollolake/loader.c
new file mode 100644
index 0000000000..5e15f2e2d6
--- /dev/null
+++ b/src/soc/intel/apollolake/loader.c
@@ -0,0 +1,138 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <assert.h>
+#include <console/console.h>
+#include <cpu/x86/cache.h>
+#include <device/pci_ids.h>
+#include <device/pci_ops.h>
+#include <soc/cpu.h>
+#include <soc/iomap.h>
+#include <soc/loader.h>
+#include <soc/pci_devs.h>
+#include <string.h>
+#include <symbols.h>
+
+static void flush_cache(uintptr_t start, uintptr_t size)
+{
+	uintptr_t	end;
+	uintptr_t	addr;
+
+	end = start + (ALIGN_UP(size, 4096));
+	for (addr = start; addr < end; addr += 64)
+		clflush((void *)addr);
+}
+
+/*
+ * This function is intentionally comment heavy, as the documentation for
+ * APL and GLK is almost non-existant.
+ */
+
+bool load_ibb(uint32_t ibb_dest, uint32_t ibb_size)
+{
+	uint32_t	host_to_cse		= (ibb_size << 4) | 0xc0000000;
+	uint32_t	cse_to_host;
+	uint32_t	state;
+	uint8_t		ring_index;
+
+	uint32_t	chunk_num;
+	uint32_t	chunk_index		= 0;
+	uint32_t	chunk_size;
+	uint32_t	number_of_chunks;
+	uint32_t	ibb_size_left;
+
+	uint8_t		*dst;
+	uint8_t		*src;
+	uint32_t	size;
+
+	/* Check if the CSE exists */
+	if ((pci_read_config32(PCH_DEV_CSE, 0) !=
+		((PCI_DID_INTEL_APL_CSE0 << 16) | PCI_VID_INTEL)) &&
+	    (pci_read_config32(PCH_DEV_CSE, 0) !=
+		((PCI_DID_INTEL_GLK_CSE0 << 16) | PCI_VID_INTEL)))
+		return -1;
+
+	/* Request data from CSE */
+	pci_write_config32(PCH_DEV_CSE, HOST2CSE, host_to_cse);
+
+	/* Wait for response */
+	do {
+		cse_to_host	= pci_read_config32(PCH_DEV_CSE, CSE2HOST);
+		chunk_num	= (cse_to_host >> 28) & 3;
+	} while (chunk_num == 0);
+
+	/*
+	 * As the size of the SRAM isn't divisible by 3, we split
+	 * the data into 4 equally sized chunks of 0x8000.
+	 */
+	if (chunk_num == 3)
+		chunk_num = 4;
+
+	/* Retrieve related information */
+	number_of_chunks	= chunk_num;
+	/* Get the size of the IBB remaining bytes */
+	ibb_size_left		= (cse_to_host & 0x0fffc000) >> 4;
+	ibb_size		= ibb_size_left;
+	chunk_size		= SHARED_SRAM_SIZE / number_of_chunks;
+
+	/* Loading IBBM */
+	while (ibb_size_left > 0) {
+
+		/* Check whether there is ring buffer ready to copy */
+		state = (cse_to_host ^ host_to_cse) & 0x0f;
+		while (state == 0) {
+			cse_to_host	= pci_read_config32(PCH_DEV_CSE, CSE2HOST);
+			state		= (cse_to_host ^ host_to_cse) & 0x0f;
+		}
+
+		/* Calculate ring index */
+		ring_index	= (uint8_t)(chunk_index % number_of_chunks);
+		if ((state & (1 << ring_index)) != 0) {
+			/* Calculate the source and destination address in ring buffer */
+			src	= (uint8_t *)(uintptr_t)
+					(SHARED_SRAM_BASE + chunk_size * ring_index);
+			dst	= (uint8_t *)(uintptr_t)
+					(ibb_dest + chunk_size * chunk_index);
+
+			if (ibb_size_left < chunk_size)
+				size	= ibb_size_left;
+			else
+				size	= chunk_size;
+
+			/*
+			 * The RBP can handle a maximum of 0x9be2 for each copy.
+			 * Whilst the above code should account for this, copying
+			 * more will break serial output so we die here so the
+			 * issue is known.
+			 */
+			if (size > CSE_RBP_LIMIT)
+				die("CSE RBP capabilities exceeded!\n");
+
+			/* Move data from SRAM into temporary memory */
+			if ((uint32_t)src >= SHARED_SRAM_BASE)
+				flush_cache((uint32_t)(uint32_t)src, size);
+
+			memcpy(dst, src, size);
+			assert(!memcmp(dst, src, size));
+			ibb_size_left -= size;
+
+			/* Send ACK to CSE */
+			host_to_cse ^= 1 << ring_index;
+			pci_write_config32(PCH_DEV_CSE, HOST2CSE, host_to_cse);
+
+			chunk_index++;
+		}
+	}
+
+	/* Check that there are no remaining chunks */
+	do {
+		cse_to_host = pci_read_config32(PCH_DEV_CSE, CSE2HOST);
+	} while ((cse_to_host & (BIT(10))) == 0);
+
+	if ((cse_to_host & ((BIT(9)))) != 0)
+		printk(BIOS_DEBUG, "CSE RBP: IBBM loaded to CAR!\n");
+
+	/* Clear MCA in BANK4 caused by the Clflush */
+	clear_mca_bank4();
+
+	return 0;
+}

From 289cff34235e367b42dfad21182f672849574aea Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Thu, 30 Jun 2022 21:22:59 +0100
Subject: [PATCH 1583/3886] soc/intel/apollolake: Load the IBB into CAR

Copy the IBB into CAR via the CSEs RBP to ensure it has not been
modified.

Test on the StarLite Mk III and Mk IV:
Without VBOOT:
    [DEBUG]  CSE: IBB Verification Result: PASS
    [DEBUG]  CSE: IBB Verification Done  : YES
    [DEBUG]  CSE: IBB Size               : 88

With VBOOT:
    [DEBUG]  CSE: IBB Verification Result: PASS
    [DEBUG]  CSE: IBB Verification Done  : YES
    [DEBUG]  CSE: IBB Size               : 102

Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I0d4e26834cef4c876e37e414b424a031c11111ff
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65577
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/soc/intel/apollolake/bootblock/bootblock.c | 8 +++++++-
 1 file changed, 7 insertions(+), 1 deletion(-)

diff --git a/src/soc/intel/apollolake/bootblock/bootblock.c b/src/soc/intel/apollolake/bootblock/bootblock.c
index 090bd5071d..cb1dd20a2c 100644
--- a/src/soc/intel/apollolake/bootblock/bootblock.c
+++ b/src/soc/intel/apollolake/bootblock/bootblock.c
@@ -15,8 +15,9 @@
 #include <intelblocks/pmclib.h>
 #include <intelblocks/tco.h>
 #include <intelblocks/uart.h>
-#include <soc/iomap.h>
 #include <soc/cpu.h>
+#include <soc/loader.h>
+#include <soc/gpio.h>
 #include <soc/soc_chip.h>
 #include <soc/systemagent.h>
 #include <soc/pci_devs.h>
@@ -55,6 +56,11 @@ asmlinkage void bootblock_c_entry(uint64_t base_timestamp)
 
 	enable_rtc_upper_bank();
 
+	if (CONFIG(IFWI_IBBM_LOAD)) {
+		load_ibb(CONFIG_IBBM_ROM_ADDR, CONFIG_IBBM_ROM_SIZE);
+		flush_l1d_to_l2();
+	}
+
 	/* Call lib/bootblock.c main */
 	bootblock_main_with_basetime(base_timestamp);
 }

From 0b5ce9d9f003cc1f3c4aee3dc59ea69eec770bb3 Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Mon, 20 Jun 2022 21:30:23 +0100
Subject: [PATCH 1584/3886] soc/intel/apollolake: Add support for IFWI Measured
 Boot

Add Measured Boot that is specific to Apollolake, and is used
for measuring the IBBL, IBB and TXE. The IBB is measured only if it
exists, and only after it has been loaded into the CSE.

Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I61ce4a34875d6d3357d4088167cdd887bafdff23
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65272
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
---
 src/soc/intel/apollolake/Makefile.mk          |   1 +
 src/soc/intel/apollolake/include/soc/fit.h    |  27 +++++
 .../apollolake/include/soc/measured_boot.h    |  31 +++++
 src/soc/intel/apollolake/measured_boot.c      | 114 ++++++++++++++++++
 4 files changed, 173 insertions(+)
 create mode 100644 src/soc/intel/apollolake/include/soc/fit.h
 create mode 100644 src/soc/intel/apollolake/include/soc/measured_boot.h
 create mode 100644 src/soc/intel/apollolake/measured_boot.c

diff --git a/src/soc/intel/apollolake/Makefile.mk b/src/soc/intel/apollolake/Makefile.mk
index ea3e05aebf..8dc4b5fd46 100644
--- a/src/soc/intel/apollolake/Makefile.mk
+++ b/src/soc/intel/apollolake/Makefile.mk
@@ -7,6 +7,7 @@ subdirs-y += ../../../cpu/intel/turbo
 
 bootblock-$(CONFIG_TPM_MEASURED_BOOT) += bootblock/bootblock_measure.c
 bootblock-y += bootblock/bootblock.c
+bootblock-$(CONFIG_IFWI_MEASURED_BOOT) += measured_boot.c
 bootblock-y += ../common/block/cpu/pm_timer_emulation.c
 bootblock-y += car.c
 bootblock-y += heci.c
diff --git a/src/soc/intel/apollolake/include/soc/fit.h b/src/soc/intel/apollolake/include/soc/fit.h
new file mode 100644
index 0000000000..fa81e6e42e
--- /dev/null
+++ b/src/soc/intel/apollolake/include/soc/fit.h
@@ -0,0 +1,27 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef _FIT_H_
+#define _FIT_H_
+
+#include <vendorcode/intel/edk2/uefi_2.4/uefi_types.h>
+
+#define FIT_TABLE_SIGNATURE		SIGNATURE_64('_', 'F', 'I', 'T', '_', ' ', ' ', ' ')
+
+#define	FIT_TABLE_TYPE_HEADER		0x0
+#define	FIT_TABLE_TYPE_TXE_SECURE_BOOT	0x10
+#define	FIT_ENTRY_SUB_TYPE_TXE_HASH	0x2
+#define	FIT_ENTRY_SUB_TYPE_BOOT_POLICY	0x3
+#define	FIT_ENTRY_SUB_TYPE_IBBL_HASH	0x7
+#define	FIT_ENTRY_SUB_TYPE_IBB_HASH	0x8
+
+struct firmware_interface_table_entry {
+	uint64_t	address;
+	uint8_t		size[3];
+	uint8_t		sub_type;
+	uint16_t	version;
+	uint8_t		type:		7;
+	uint8_t		cv:		1;
+	uint8_t		chk_sum;
+};
+
+#endif /* _FIT_H_ */
diff --git a/src/soc/intel/apollolake/include/soc/measured_boot.h b/src/soc/intel/apollolake/include/soc/measured_boot.h
new file mode 100644
index 0000000000..e6e06f3f08
--- /dev/null
+++ b/src/soc/intel/apollolake/include/soc/measured_boot.h
@@ -0,0 +1,31 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef _BOOT_GUARD_LIB_H_
+#define _BOOT_GUARD_LIB_H_
+
+#include <types.h>
+
+/* Boot Policy configuration for Boot Guard */
+struct boot_policy {
+	uint16_t pbe:		1;
+	uint16_t bbi:		1;
+	uint16_t vb:		1;
+	uint16_t mb:		1;
+	uint16_t kmid:		4;
+	uint16_t dcd:		1;
+	uint16_t sb_s3_opt:	1;
+	uint16_t res:		6;
+};
+
+/* Boot Policy info populated by TXE */
+struct boot_policy_manifest {
+	struct boot_policy bpm;
+	uint8_t	txe_hash[SHA256_DIGEST_SIZE];
+	uint8_t	ibbl_hash[32];
+	uint8_t ibb_hash[32];
+};
+
+bool fetch_pre_rbp_data(struct boot_policy_manifest *bpm_info);
+void fetch_post_rbp_data(struct boot_policy_manifest *bpm_info);
+
+#endif /* _BOOT_GUARD_LIB_H_ */
diff --git a/src/soc/intel/apollolake/measured_boot.c b/src/soc/intel/apollolake/measured_boot.c
new file mode 100644
index 0000000000..8f1d1ee321
--- /dev/null
+++ b/src/soc/intel/apollolake/measured_boot.c
@@ -0,0 +1,114 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <console/console.h>
+#include <device/mmio.h>
+#include <lib.h>
+#include <security/tpm/tspi.h>
+#include <security/tpm/tss/tcg-2.0/tss_structures.h>
+#include <soc/measured_boot.h>
+#include <soc/fit.h>
+#include <string.h>
+
+extern const uint64_t fit_ptr;
+
+static void *find_fit_entry_data(uint8_t type, uint8_t sub_type)
+{
+	struct firmware_interface_table_entry	*fit_entry;
+	uint32_t entry_num;
+	uint32_t fit_table_offset;
+	uint32_t index;
+
+	fit_table_offset = fit_ptr;
+	fit_entry = (struct firmware_interface_table_entry *)(uint32_t)fit_table_offset;
+	if (fit_entry[0].address != FIT_TABLE_SIGNATURE)
+		return NULL;
+
+	if (fit_entry[0].type != FIT_TABLE_TYPE_HEADER)
+		return NULL;
+
+	entry_num = *(uint32_t *)(&fit_entry[0].size[0]) & 0xffffff;
+	for (index = 0; index < entry_num; index++) {
+		if ((fit_entry[index].type == type) && (fit_entry[index].sub_type == sub_type))
+			return (void *)(uint32_t)fit_entry[index].address;
+	}
+
+	return NULL;
+}
+
+bool fetch_pre_rbp_data(struct boot_policy_manifest *bpm_info)
+{
+	uint8_t *fit_data;
+	fit_data = find_fit_entry_data(FIT_TABLE_TYPE_TXE_SECURE_BOOT,
+				       FIT_ENTRY_SUB_TYPE_BOOT_POLICY);
+
+	if (fit_data != NULL) {
+		memcpy((void *)&(bpm_info->bpm), fit_data, sizeof(bpm_info->bpm));
+
+		printk(BIOS_DEBUG, "Boot Guard 2.0: Verified Boot: %s\n",
+			bpm_info->bpm.vb ? "Enforced" : "Not enforced");
+		if (bpm_info->bpm.vb && !CONFIG(IFWI_VERIFIED_BOOT))
+			printk(BIOS_CRIT, "Boot Guard 2.0: Verified boot is enforced but not enabled.\n");
+
+		printk(BIOS_DEBUG, "Boot Guard 2.0: Measured Boot: %s\n",
+			bpm_info->bpm.mb ? "Enforced" : "Not enforced");
+		if (bpm_info->bpm.mb && !CONFIG(IFWI_MEASURED_BOOT))
+			printk(BIOS_CRIT, "Boot Guard 2.0: Measured boot is enforced but not enabled.\n");
+	}
+
+	if (CONFIG(IFWI_MEASURED_BOOT)) {
+		/* TXE */
+		fit_data = find_fit_entry_data(FIT_TABLE_TYPE_TXE_SECURE_BOOT,
+					       FIT_ENTRY_SUB_TYPE_TXE_HASH);
+		if (fit_data) {
+			memcpy((void *)(bpm_info->txe_hash), fit_data,
+				sizeof(bpm_info->txe_hash));
+			printk(BIOS_DEBUG, "TXE Hash: %hhn\n", bpm_info->txe_hash);
+			hexdump((void *)bpm_info->txe_hash, SHA256_DIGEST_SIZE);
+
+			tpm_extend_pcr(0, TPM_ALG_SHA256, bpm_info->txe_hash,
+				SHA256_DIGEST_SIZE, "TXE");
+		}
+
+		/* IBBL */
+		fit_data = find_fit_entry_data(FIT_TABLE_TYPE_TXE_SECURE_BOOT,
+					       FIT_ENTRY_SUB_TYPE_IBBL_HASH);
+		if (fit_data) {
+			memcpy((void *)(bpm_info->ibbl_hash), fit_data,
+				sizeof(bpm_info->ibbl_hash));
+			printk(BIOS_DEBUG, "IBBL Hash: %hhn\n", bpm_info->ibbl_hash);
+			hexdump((void *)bpm_info->ibbl_hash, SHA256_DIGEST_SIZE);
+
+			tpm_extend_pcr(0, TPM_ALG_SHA256, bpm_info->ibbl_hash,
+			SHA256_DIGEST_SIZE, "IBBL");
+
+		}
+		/* Return if IBB exists */
+		fit_data = find_fit_entry_data(FIT_TABLE_TYPE_TXE_SECURE_BOOT,
+					       FIT_ENTRY_SUB_TYPE_IBB_HASH);
+
+		printk(BIOS_DEBUG, "IBB: %s\n", fit_data ? "Present" : "Not present");
+		return fit_data;
+	}
+
+	return 0;
+}
+
+void fetch_post_rbp_data(struct boot_policy_manifest *bpm_info)
+{
+	if (CONFIG(IFWI_MEASURED_BOOT)) {
+		/* IBB */
+		uint8_t *fit_data;
+		fit_data = find_fit_entry_data(FIT_TABLE_TYPE_TXE_SECURE_BOOT,
+					       FIT_ENTRY_SUB_TYPE_IBB_HASH);
+
+		if (fit_data) {
+			memcpy((void *)bpm_info->ibb_hash, fit_data,
+				sizeof(bpm_info->ibb_hash));
+			printk(BIOS_DEBUG, "IBB Hash: %hhn\n", bpm_info->ibb_hash);
+			hexdump((void *)bpm_info->ibb_hash, SHA256_DIGEST_SIZE);
+
+			tpm_extend_pcr(0, TPM_ALG_SHA256, bpm_info->ibb_hash,
+				SHA256_DIGEST_SIZE, "IBBM");
+		}
+	}
+}

From e63620012cb64baa0de3c45e906ffcc74fe5d656 Mon Sep 17 00:00:00 2001
From: Patrick Rudolph <patrick.rudolph@9elements.com>
Date: Wed, 23 Apr 2025 11:54:00 +0200
Subject: [PATCH 1585/3886] util: Add Microchip EC FW tool

The Microchip EC can share the SPI flash with the x86 host. Since
it boots first and does power sequencing, there's no problem with
concurrent access happening. Due to various vendor specific flash
layouts used on x86, the EC needs a pointer to it's own firmware.

The pointer resides at flash offset 0 and is read by MEC152x and
MEC1701 and MEC172x ECs, probably others as well.

The introduced tool generates the EC FW PTR at flash offset 0.

Allows to get rid of hand-crafted binary files (EC_SIG) being used
on AMD mainboards that hardcode the offset and must manually being
checked if those match the FMAP.

When there'll be additional firmware regions added it becomes
unconvienient to maintain those by hand.

Usage output:

Usage: ./util/mec152x/mec152xtool <rom-file> <command>
        -h|--help
        -f|--fmap_region_name

Command:
 GEN_ECFW_PTR - Writes the ECFW PTR

Based on https://chromium.googlesource.com/chromiumos/platform/ec/+/08f5a1e6fc2c9467230444ac9b582dcf4d9f0068/chip/mchp/util/pack_ec_mec172x.py

Change-Id: I3b74c9f65643ad4437de29d4aed307b1a2b33286
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87428
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
---
 util/mec152x/Makefile       | 54 ++++++++++++++++++++
 util/mec152x/Makefile.mk    | 23 +++++++++
 util/mec152x/description.md |  8 +++
 util/mec152x/main.c         | 99 +++++++++++++++++++++++++++++++++++++
 util/mec152x/rom.c          | 77 +++++++++++++++++++++++++++++
 util/mec152x/rom.h          | 10 ++++
 util/mec152x/utils.c        | 79 +++++++++++++++++++++++++++++
 util/mec152x/utils.h        | 20 ++++++++
 8 files changed, 370 insertions(+)
 create mode 100644 util/mec152x/Makefile
 create mode 100644 util/mec152x/Makefile.mk
 create mode 100644 util/mec152x/description.md
 create mode 100644 util/mec152x/main.c
 create mode 100644 util/mec152x/rom.c
 create mode 100644 util/mec152x/rom.h
 create mode 100644 util/mec152x/utils.c
 create mode 100644 util/mec152x/utils.h

diff --git a/util/mec152x/Makefile b/util/mec152x/Makefile
new file mode 100644
index 0000000000..43b350145c
--- /dev/null
+++ b/util/mec152x/Makefile
@@ -0,0 +1,54 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+PRG  := mec152xtool
+TOP  ?= $(abspath ../..)
+ROOT := $(TOP)/src
+
+CC      ?= $(CROSS_COMPILE)gcc
+HOSTCC  ?= $(CC)
+INSTALL ?= /usr/bin/env install
+PREFIX  ?= /usr/local
+
+HOSTCFLAGS ?= $(CFLAGS)
+HOSTCFLAGS += -Wall -Wextra -MMD -MP -O3
+HOSTCFLAGS += -I $(TOP)/util/cbfstool/flashmap/
+HOSTCFLAGS += -I $(ROOT)/commonlib/bsd/include
+
+HOSTLDFLAGS ?= $(LDFLAGS)
+
+# there files are in this directory
+SRC := main.c utils.c rom.c
+# and these are in $(TOP)/util/cbfstool/flashmap/
+SRC += fmap.c kv_pair.c valstr.c
+
+OBJ := $(SRC:.c=.o)
+DEP := $(SRC:.c=.o.d)
+
+.PHONY: all debug clean install
+
+all: $(PRG)
+
+debug: HOSTCFLAGS += -O0 -g
+debug: HOSTLDFLAGS += -g
+debug: all
+
+install: $(PRG)
+	$(INSTALL) -d $(DESTDIR)$(PREFIX)/bin/
+	$(INSTALL) $^ $(DESTDIR)$(PREFIX)/bin/
+
+uninstall:
+	$(RM) $(DESTDIR)$(PREFIX)/bin/$(PRG)
+
+clean:
+	$(RM) -f $(PRG) $(OBJ) $(DEP)
+
+$(PRG): $(OBJ)
+	$(HOSTCC) -o $@ $^ $(HOSTLDFLAGS)
+
+%.o: %.c
+	$(HOSTCC) $(HOSTCFLAGS) -c -o $@ -MF $@.d $<
+
+%.o: $(TOP)/util/cbfstool/flashmap/%.c
+	$(HOSTCC) $(HOSTCFLAGS) -c -o $@ -MF $@.d $<
+
+-include $(DEP)
diff --git a/util/mec152x/Makefile.mk b/util/mec152x/Makefile.mk
new file mode 100644
index 0000000000..067fdb097f
--- /dev/null
+++ b/util/mec152x/Makefile.mk
@@ -0,0 +1,23 @@
+# SPDX-License-Identifier: BSD-3-Clause
+
+mec152xtoolobj = main.o utils.o rom.o fmap.o kv_pair.o valstr.o
+mec152xheader = $(addprefix $(dir)/,utils.h rom.h)
+
+WERROR ?= -Wno-error
+MEC152XCFLAGS := -Wno-array-bounds -Wextra -O3 -Wshadow $(WERROR)
+MEC152XCFLAGS += -I $(top)/util/cbfstool/flashmap/
+MEC152XCFLAGS += -I $(top)/util/mec152x
+MEC152XCFLAGS += -I $(top)/src/commonlib/bsd/include
+
+additional-dirs += $(objutil)/mec152x
+
+$(objutil)/mec152x/%.o: $(top)/util/mec152x/%.c $(mec152xheader) | $(objutil)
+	printf "    MEC152X   $@\n"
+	$(HOSTCC) $(MEC152XCFLAGS) $(HOSTCFLAGS) -c -o $@ $<
+
+$(objutil)/mec152x/%.o: $(top)/util/cbfstool/flashmap/%.c $(mec152xheader) | $(objutil)
+	$(HOSTCC) $(MEC152XCFLAGS) $(HOSTCFLAGS) -c -o $@ $<
+
+$(objutil)/mec152x/mec152xtool: $(addprefix $(objutil)/mec152x/,$(mec152xtoolobj)) $(mec152xheader) | $(objutil)
+	printf "    MEC152X    $@\n"
+	$(HOSTCC) $(addprefix $(objutil)/mec152x/,$(mec152xtoolobj)) $(LDFLAGS) -o $@
diff --git a/util/mec152x/description.md b/util/mec152x/description.md
new file mode 100644
index 0000000000..c2ef805441
--- /dev/null
+++ b/util/mec152x/description.md
@@ -0,0 +1,8 @@
+Offline Microchip EC FW modification tool `C`
+
+Generates the EC firmware pointer at flash offset 0 based on
+the FMAP and the specified FMAP region name. The EC will read
+this pointer to find the EC firmware in the host SPI flash.
+
+This will overwrite the first 4 bytes of flash. The user must
+be aware of potential conflicts such as with the Intel IFD.
diff --git a/util/mec152x/main.c b/util/mec152x/main.c
new file mode 100644
index 0000000000..569cc43300
--- /dev/null
+++ b/util/mec152x/main.c
@@ -0,0 +1,99 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <errno.h>
+#include <getopt.h>
+#include <unistd.h>
+#include <stdbool.h>
+#include <stdint.h>
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+
+#include "rom.h"
+
+static const char *USAGE_FMT = "Usage: %s <rom-file> <command>\n"
+			       "        -h|--help\n"
+			       "        -f|--fmap_region_name\n\n"
+			       "Command:\n"
+			       " GEN_ECFW_PTR - Writes the ECFW PTR\n";
+
+static const char *program_name;
+
+static void print_program_usage(void)
+{
+	fprintf(stderr, USAGE_FMT, program_name);
+	exit(EXIT_FAILURE);
+}
+
+#define ERROR(...) do { fprintf(stderr, "ERROR: " __VA_ARGS__); \
+			print_program_usage(); } \
+			while (0)
+
+static void print_help(void)
+{
+	printf(USAGE_FMT, program_name);
+}
+
+static const struct option longopts[] = {
+	{"help", 0, 0, 'h'},
+	{"fmap_region_name", 1, 0, 'f'},
+	{NULL, 0, 0, 0}
+};
+
+int main(int argc, char *argv[])
+{
+	char *fmap_region_name = NULL;
+	const char *rom_file = NULL;
+	const char *command = NULL;
+
+	int opt, idx, ret = 0;
+	program_name = argv[0];
+
+	if (argc < 3)
+		ERROR("Not enough argument given\n\n");
+
+	while (!ret &&
+		(opt = getopt_long(argc, argv, "?hf:",
+				   longopts, &idx)) != -1) {
+		switch (opt) {
+		case 'h':
+		case '?':
+			print_help();
+			exit(EXIT_SUCCESS);
+			break;
+		case 'f':
+			fmap_region_name = strdup(optarg);
+			break;
+		}
+	}
+	if (optind < argc) {
+		rom_file = argv[optind];
+		optind++;
+	}
+	if (optind < argc) {
+		command = argv[optind];
+		optind++;
+	}
+
+	if (optind < argc)
+		ERROR("Unknown argument: %s\n\n", argv[optind]);
+
+	if (!rom_file)
+		ERROR("No ROM specified\n\n");
+
+	if (!command) {
+		ERROR("No command specified\n\n");
+	} else if (!strcmp(command, "GEN_ECFW_PTR")) {
+		if (!fmap_region_name)
+			ERROR("No fmap region specified\n\n");
+		if (!rom_set_ec_fw_ptr(rom_file, fmap_region_name))
+			ERROR("Failed to write EC FW PTR\n\n");
+	} else {
+		ERROR("Unknown command specified: '%s'\n\n", command);
+	}
+
+	if (fmap_region_name)
+		free(fmap_region_name);
+
+	return ret;
+}
diff --git a/util/mec152x/rom.c b/util/mec152x/rom.c
new file mode 100644
index 0000000000..2c61c6ce2b
--- /dev/null
+++ b/util/mec152x/rom.c
@@ -0,0 +1,77 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <assert.h>
+#include <commonlib/bsd/compiler.h>
+#include <endian.h>
+#include <fmap.h>
+#include <stdio.h>
+#include "rom.h"
+#include "utils.h"
+
+/* Generate EC FW PTR. EC FW must be 256 byte aligned and has a CRC-8 checksum */
+static uint32_t gen_signature(uint32_t rom_offset)
+{
+	uint32_t signature = rom_offset >> 8;
+	uint8_t crc = crc8_itu((uint8_t *)&signature, 3);
+
+	signature |= ((uint32_t)crc) << 24;
+
+	return signature;
+}
+
+/**
+ *  @brief  Write the EC FW pointer to the ROM
+ *  @param  rom_file          The filename of the ROM to update
+ *                            The ROM must contain a valid FMAP
+ *  @param  fmap_region_name  FMAP region name containing the EC firmware
+ *  @return  True on success
+ *
+ *  On MEC15x1 the firmware resides in the shared x86 SPI flash. As the EC
+ *  boots first and does the power sequencing there's no concurrent access.
+ *  The EC expects to find a pointer to the FW at offset 0.
+ */
+bool rom_set_ec_fw_ptr(const char rom_file[], const char *fmap_region_name)
+{
+	struct mem_range file = {0};
+	bool ret = false;
+
+	file = map_file(rom_file, true);
+	if (file.start == NULL) {
+		fprintf(stderr, "ERROR: Failed to load \"%s\"\n", rom_file);
+		return false;
+	}
+
+	long fmap_offset = fmap_find(file.start, file.length);
+	if (fmap_offset >= 0) {
+		struct fmap *fmap = (void *)(file.start + fmap_offset);
+		const struct fmap_area *area = fmap_find_area(fmap, fmap_region_name);
+		if (area == NULL) {
+			fprintf(stderr,
+				"ERROR: Found FMAP without '%s' in \"%s\"\n\n",
+				fmap_region_name, rom_file);
+			printf("FMAP is:\n");
+			fmap_print(fmap);
+			goto error;
+		}
+
+		/* EC FW must be aligned */
+		if (area->offset % 256) {
+			fprintf(stderr,
+				"ERROR: Region '%s' not aligned to 256 in \"%s\"\n",
+				fmap_region_name, rom_file);
+			goto error;
+		}
+
+		/* EC FW pointer resides at offset 0 */
+		uint32_t *ec_fw_ptr = (uint32_t *)file.start;
+		*ec_fw_ptr = htole32(gen_signature(area->offset));
+	} else {
+		fprintf(stderr, "ERROR: FMAP not found \"%s\"\n", rom_file);
+		goto error;
+	}
+
+	ret = true;
+error:
+	unmap_file(file);
+	return ret;
+}
diff --git a/util/mec152x/rom.h b/util/mec152x/rom.h
new file mode 100644
index 0000000000..0d7a3cb4a5
--- /dev/null
+++ b/util/mec152x/rom.h
@@ -0,0 +1,10 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#ifndef MEC15X1__ROM_H__
+#define MEC15X1__ROM_H__
+
+#include <stdbool.h>
+
+bool rom_set_ec_fw_ptr(const char rom_file[], const char *fmap_region_name);
+
+#endif // MEC15X1__ROM_H__
diff --git a/util/mec152x/utils.c b/util/mec152x/utils.c
new file mode 100644
index 0000000000..b4b0afd02d
--- /dev/null
+++ b/util/mec152x/utils.c
@@ -0,0 +1,79 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include "utils.h"
+
+#include <sys/mman.h>
+#include <sys/stat.h>
+#include <fcntl.h>
+#include <unistd.h>
+
+#include <errno.h>
+#include <limits.h>
+#include <stdbool.h>
+#include <stddef.h>
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+
+/* Return CRC-8 of the data, using x^8 x^2 x 1 polynomial. */
+uint8_t crc8_itu(const uint8_t *data, int len)
+{
+	unsigned int crc = 0;
+	int i, j;
+
+	for (j = 0; j < len; j++, data++) {
+		crc ^= (*data << 8);
+		for (i = 8; i; i--) {
+			if (crc & 0x8000)
+				crc ^= (0x1070 << 3);
+			crc <<= 1;
+		}
+	}
+
+	return (uint8_t)(crc >> 8) ^ 0x55;
+}
+
+struct mem_range map_file(const char path[], bool rw)
+{
+	struct mem_range range = {0};
+
+	int open_flags = rw ? O_RDWR : O_RDONLY;
+	int mmap_flags = rw ? PROT_READ | PROT_WRITE : PROT_READ;
+
+	int fd = open(path, open_flags);
+	if (fd == -1) {
+		fprintf(stderr, "Failed to open(): %s\n", strerror(errno));
+		return range;
+	}
+
+	struct stat stat_buf;
+	if (fstat(fd, &stat_buf) != 0) {
+		(void)close(fd);
+		fprintf(stderr, "Failed to fstat(): %s\n", strerror(errno));
+		return range;
+	}
+
+	if (stat_buf.st_size == 0) {
+		(void)close(fd);
+		fprintf(stderr, "Can't map an empty \"%s\" file\n", path);
+		return range;
+	}
+
+	uint8_t *mem = mmap(/*addr=*/NULL, stat_buf.st_size, mmap_flags,
+			    MAP_SHARED | MAP_POPULATE, fd, /*offset=*/0);
+	(void)close(fd);
+	if (mem == MAP_FAILED) {
+		fprintf(stderr, "Failed to mmap(): %s\n", strerror(errno));
+		return range;
+	}
+
+	range.start = mem;
+	range.length = stat_buf.st_size;
+	return range;
+}
+
+void unmap_file(struct mem_range store)
+{
+	if (munmap(store.start, store.length) != 0)
+		fprintf(stderr, "Failed to munmap(): %s\n", strerror(errno));
+}
diff --git a/util/mec152x/utils.h b/util/mec152x/utils.h
new file mode 100644
index 0000000000..f586565e3b
--- /dev/null
+++ b/util/mec152x/utils.h
@@ -0,0 +1,20 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#ifndef MEC152X__UTILS_H__
+#define MEC152X__UTILS_H__
+
+#include <stddef.h>
+#include <stdbool.h>
+#include <stdint.h>
+
+struct mem_range {
+	uint8_t *start;
+	size_t length;
+};
+uint8_t crc8_itu(const uint8_t *data, int len);
+
+struct mem_range map_file(const char path[], bool rw);
+
+void unmap_file(struct mem_range store);
+
+#endif // MEC152X__UTILS_H__

From 5a0953614be9551ee15d5ba9a655087bcd915278 Mon Sep 17 00:00:00 2001
From: Patrick Rudolph <patrick.rudolph@9elements.com>
Date: Wed, 23 Apr 2025 15:17:14 +0200
Subject: [PATCH 1586/3886] util/amdtools: Add ec_usb_pd_fw

ec_usb_pd_fw is a board specific utility to generate pointers to
firmware images found in the SPI flash. On some AMD boards the
x86 SPI flash is shared with the EC. The EC can also update the
USB Power Delivery controllers firmware, but it needs to know where
to load the firmware from. It uses pointers stored in the first
128 bytes of the x86 SPI flash.

Add a small utility to generate pointers to the USB PD firmware,
located somewhere in the ROM identified by the FMAP region.

There can be up to 12 USB PD firmwares, depending on the used
vendor or model.

Change-Id: I98717e849592f83eb7bacbfed33a8d4b811a5e18
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87430
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 util/amdtools/ec_usb_pd_fw/Makefile       |  55 +++++++++++
 util/amdtools/ec_usb_pd_fw/Makefile.mk    |  24 +++++
 util/amdtools/ec_usb_pd_fw/description.md |   8 ++
 util/amdtools/ec_usb_pd_fw/main.c         | 114 ++++++++++++++++++++++
 util/amdtools/ec_usb_pd_fw/rom.c          | 108 ++++++++++++++++++++
 util/amdtools/ec_usb_pd_fw/rom.h          |  10 ++
 util/amdtools/ec_usb_pd_fw/utils.c        |  61 ++++++++++++
 util/amdtools/ec_usb_pd_fw/utils.h        |  20 ++++
 8 files changed, 400 insertions(+)
 create mode 100644 util/amdtools/ec_usb_pd_fw/Makefile
 create mode 100644 util/amdtools/ec_usb_pd_fw/Makefile.mk
 create mode 100644 util/amdtools/ec_usb_pd_fw/description.md
 create mode 100644 util/amdtools/ec_usb_pd_fw/main.c
 create mode 100644 util/amdtools/ec_usb_pd_fw/rom.c
 create mode 100644 util/amdtools/ec_usb_pd_fw/rom.h
 create mode 100644 util/amdtools/ec_usb_pd_fw/utils.c
 create mode 100644 util/amdtools/ec_usb_pd_fw/utils.h

diff --git a/util/amdtools/ec_usb_pd_fw/Makefile b/util/amdtools/ec_usb_pd_fw/Makefile
new file mode 100644
index 0000000000..6049884a2f
--- /dev/null
+++ b/util/amdtools/ec_usb_pd_fw/Makefile
@@ -0,0 +1,55 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+PRG  := ec_usb_pd_fw
+TOP  ?= $(abspath ../../..)
+ROOT := $(TOP)/src
+
+CC      ?= $(CROSS_COMPILE)gcc
+HOSTCC  ?= $(CC)
+INSTALL ?= /usr/bin/env install
+PREFIX  ?= /usr/local
+
+HOSTCFLAGS ?= $(CFLAGS)
+HOSTCFLAGS += -Wall -Wextra -MMD -MP -O3
+HOSTCFLAGS += -I $(TOP)/util/cbfstool/flashmap/
+HOSTCFLAGS += -I $(ROOT)/commonlib/bsd/include
+
+HOSTLDFLAGS ?= $(LDFLAGS)
+
+# there files are in this directory
+SRC := main.c utils.c rom.c
+# and these are in $(TOP)/util/cbfstool/flashmap/
+SRC += fmap.c kv_pair.c valstr.c
+
+OBJ := $(SRC:.c=.o)
+DEP := $(SRC:.c=.o.d)
+
+.PHONY: all debug clean install
+
+all: $(PRG)
+
+debug: HOSTCFLAGS += -O0 -g
+debug: HOSTLDFLAGS += -g
+debug: all
+
+install: $(PRG)
+	$(INSTALL) -d $(DESTDIR)$(PREFIX)/bin/
+	$(INSTALL) $^ $(DESTDIR)$(PREFIX)/bin/
+
+uninstall:
+	$(RM) $(PRG) $(DESTDIR)$(PREFIX)/bin/
+	$(RMDIR) $(DESTDIR)$(PREFIX)/bin/
+
+clean:
+	-$(RM) $(PRG) $(OBJ) $(DEP)
+
+$(PRG): $(OBJ)
+	$(HOSTCC) -o $@ $^ $(HOSTLDFLAGS)
+
+%.o: %.c
+	$(HOSTCC) $(HOSTCFLAGS) -c -o $@ -MF $@.d $<
+
+%.o: $(TOP)/util/cbfstool/flashmap/%.c
+	$(HOSTCC) $(HOSTCFLAGS) -c -o $@ -MF $@.d $<
+
+-include $(DEP)
diff --git a/util/amdtools/ec_usb_pd_fw/Makefile.mk b/util/amdtools/ec_usb_pd_fw/Makefile.mk
new file mode 100644
index 0000000000..0905f8524d
--- /dev/null
+++ b/util/amdtools/ec_usb_pd_fw/Makefile.mk
@@ -0,0 +1,24 @@
+# SPDX-License-Identifier: BSD-3-Clause
+
+ec_usb_pd_fwtoolobj = main.o utils.o rom.o fmap.o kv_pair.o valstr.o
+ec_usb_pd_fwheader = $(addprefix $(dir)/,utils.h rom.h)
+
+WERROR ?= -Wno-error
+EC_USB_PD_FWCFLAGS ?= $(CFLAGS)
+EC_USB_PD_FWCFLAGS += -Wno-array-bounds -Wextra -MMD -MP -O3 -Wshadow $(WERROR)
+EC_USB_PD_FWCFLAGS += -I $(top)/util/cbfstool/flashmap/
+EC_USB_PD_FWCFLAGS += -I $(top)/util/amdtools/ec_usb_pd_fw
+EC_USB_PD_FWCFLAGS += -I $(top)/src/commonlib/bsd/include
+
+additional-dirs += $(objutil)/ec_usb_pd_fw
+
+$(objutil)/ec_usb_pd_fw/%.o: $(top)/util/amdtools/ec_usb_pd_fw/%.c $(ec_usb_pd_fwheader) | $(objutil)/ec_usb_pd_fw
+	printf "    PD_FWTOOL  $@\n"
+	$(HOSTCC) $(EC_USB_PD_FWCFLAGS) $(HOSTCFLAGS) -c -o $@ $<
+
+$(objutil)/ec_usb_pd_fw/%.o: $(top)/util/cbfstool/flashmap/%.c $(ec_usb_pd_fwheader) | $(objutil)/ec_usb_pd_fw
+	$(HOSTCC) $(EC_USB_PD_FWCFLAGS) $(HOSTCFLAGS) -c -o $@ $<
+
+$(objutil)/ec_usb_pd_fw/ec_usb_pd_fw: $(addprefix $(objutil)/ec_usb_pd_fw/,$(ec_usb_pd_fwtoolobj)) $(ec_usb_pd_fwheader) | $(objutil)/ec_usb_pd_fw
+	printf "    PD_FWTOOL  $@\n"
+	$(HOSTCC) $(addprefix $(objutil)/ec_usb_pd_fw/,$(ec_usb_pd_fwtoolobj)) $(LDFLAGS) -o $@
diff --git a/util/amdtools/ec_usb_pd_fw/description.md b/util/amdtools/ec_usb_pd_fw/description.md
new file mode 100644
index 0000000000..15e60e595e
--- /dev/null
+++ b/util/amdtools/ec_usb_pd_fw/description.md
@@ -0,0 +1,8 @@
+Offline AMD Board specific USB Type-C PD FW modification tool `C`
+
+Generates pointers at flash offset 16 for the EC firmware to consume
+by reading the FMAP and the provided FMAP region name. The EC will
+load the USB PD firmware into the corresponding chip where necessary.
+
+This will overwrite parts of the flash without warning. The user must
+be aware of potential conflicts such as with the Intel IFD.
diff --git a/util/amdtools/ec_usb_pd_fw/main.c b/util/amdtools/ec_usb_pd_fw/main.c
new file mode 100644
index 0000000000..9f239f46e2
--- /dev/null
+++ b/util/amdtools/ec_usb_pd_fw/main.c
@@ -0,0 +1,114 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <errno.h>
+#include <getopt.h>
+#include <unistd.h>
+#include <stdbool.h>
+#include <stdint.h>
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+
+#include "rom.h"
+
+static const char *USAGE_FMT = "Usage: %s <rom-file> <command> [arguments]\n"
+			       "        -h|--help\n"
+			       "        -f|--fmap_region_name  FMAP region\n"
+			       "        -s|--slot [0-11]  Specify slot to use\n"
+			       "        -n|--next_free  Use next free slot\n\n"
+			       "Command:\n"
+			       " GEN_PDFW_PTR - Writes the USB Type-C PD firmware PTR\n";
+
+static const char *program_name;
+
+static void print_program_usage(void)
+{
+	fprintf(stderr, USAGE_FMT, program_name);
+	exit(EXIT_FAILURE);
+}
+
+#define ERROR(...) do { fprintf(stderr, "ERROR: " __VA_ARGS__); print_program_usage(); } while(0)
+
+static void print_help(void)
+{
+	printf(USAGE_FMT, program_name);
+}
+
+static const struct option longopts[] = {
+	{"help", 0, 0, 'h'},
+	{"fmap_region_name", 1, 0, 'f'},
+	{"next_free", 0, 0, 'n'},
+	{"slot", 1, 0, 's'},
+	{NULL, 0, 0, 0}
+};
+
+int main(int argc, char *argv[])
+{
+	char *fmap_region_name = NULL;
+	const char *rom_file = NULL;
+	const char *command = NULL;
+	int slot = -1;
+	bool next_free = false;
+
+	int opt, idx, ret = 0;
+	program_name = argv[0];
+
+	if (argc < 3)
+		ERROR("Not enough argument given\n\n");
+
+	while (!ret &&
+		(opt = getopt_long(argc, argv, "?hf:s:n",
+				   longopts, &idx)) != -1) {
+		switch (opt) {
+		case 'h':
+		case '?':
+			print_help();
+			exit(EXIT_SUCCESS);
+			break;
+		case 'n':
+			next_free = true;
+			break;
+		case 'f':
+			fmap_region_name = strdup(optarg);
+			break;
+		case 's':
+			slot = strtol(optarg, NULL, 0);
+			break;
+		}
+	}
+	if (optind < argc) {
+		rom_file = argv[optind];
+		optind++;
+	}
+	if (optind < argc) {
+		command = argv[optind];
+		optind++;
+	}
+
+	if (optind < argc)
+		ERROR("Unknown argument: %s\n\n", argv[optind]);
+
+	if (!rom_file)
+		ERROR("No ROM specified\n\n");
+
+	if (!command) {
+		ERROR("No command specified\n\n");
+	} else if (!strcmp(command, "GEN_PDFW_PTR")) {
+		if (!fmap_region_name)
+			ERROR("No fmap region specified\n\n");
+		if (next_free && slot >= 0)
+			ERROR("Specified slot and auto allocation\n\n");
+		if (!next_free && slot < 0)
+			ERROR("Didn't specify a slot and not auto allocating\n\n");
+		if (slot > 11)
+			ERROR("Invalid slot specified\n\n");
+		if (!rom_set_pd_fw_ptr(rom_file, fmap_region_name, slot, next_free))
+			ERROR("Failed to write EC PD PTR\n\n");
+	} else
+		ERROR("Unknown command specified: '%s'\n\n", command);
+
+	if (fmap_region_name)
+		free(fmap_region_name);
+
+	return ret;
+}
diff --git a/util/amdtools/ec_usb_pd_fw/rom.c b/util/amdtools/ec_usb_pd_fw/rom.c
new file mode 100644
index 0000000000..183eb6ac1d
--- /dev/null
+++ b/util/amdtools/ec_usb_pd_fw/rom.c
@@ -0,0 +1,108 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <assert.h>
+#include <commonlib/bsd/compiler.h>
+#include <endian.h>
+#include <fmap.h>
+#include <stdio.h>
+#include "rom.h"
+#include "utils.h"
+
+/**
+ *  @brief Generate pointer to PD firmware.
+ *  @param  rom_offset  Offset of the PD firmware
+ *  @param  size        Size of the PD firmware
+ *
+ *  Each pointer is 8 byte wide consists of:
+ *   - 4 byte offset
+ *   - 3 byte size
+ *   - 1 byte checksum (all 8 bytes sum up to 0xff)
+ */
+static uint64_t gen_signature(uint32_t rom_offset, uint32_t size)
+{
+	uint64_t signature = rom_offset;
+	signature |= ((uint64_t)size & 0xffffffULL) << 32;
+	uint8_t crc = 0;
+
+	for (int i = 0; i < 7; i++)
+		crc += (signature >> (i * 8)) & 0xff;
+
+	signature |= (0xffULL - (uint64_t)crc) << 56;
+
+	return signature;
+}
+
+static bool check_signature(uint64_t signature)
+{
+	uint8_t crc = 0;
+
+	for (int i = 0; i < 8; i++)
+		crc += (signature >> (i * 8)) & 0xff;
+
+	return crc == 0xff;
+}
+
+/**
+ *  @brief  Write the EC PD pointer to the ROM
+ *  @param  rom_file          The filename of the ROM to update
+ *                            The ROM must contain a valid FMAP
+ *  @param  fmap_region_name  FMAP region name containing the PD firmware
+ *  @return  True on success
+ *
+ *  The EC firmware copies the USB Type-C PD firmware from the x86 SPI flash
+ *  to the corresponding controller when necessary. It expects to find a list
+ *  of pointers at offset 10h. The ROM can contain multiple PD firmwares depending
+ *  on the used IC vendor/familiy.
+ *
+ */
+bool rom_set_pd_fw_ptr(const char rom_file[], const char *fmap_region_name, int slot, bool automatic)
+{
+	uint64_t *ec_pd_fw_ptr;
+	struct mem_range file = {0};
+	bool ret = false;
+
+	file = map_file(rom_file, true);
+	if (file.start == NULL) {
+		fprintf(stderr, "ERROR: Failed to load \"%s\"\n", rom_file);
+		return false;
+	}
+
+	if (automatic)
+		slot = 0;
+
+	long fmap_offset = fmap_find(file.start, file.length);
+	if (fmap_offset >= 0) {
+		struct fmap *fmap = (void *)(file.start + fmap_offset);
+		const struct fmap_area *area = fmap_find_area(fmap, fmap_region_name);
+		if (area == NULL) {
+			fprintf(stderr,
+				"ERROR: Found FMAP without '%s' in \"%s\"\n\n",
+				fmap_region_name, rom_file);
+			printf("FMAP is:\n");
+			fmap_print(fmap);
+			goto error;
+		}
+
+		/* EC PD pointer resides at offset 0x10 */
+		ec_pd_fw_ptr = (uint64_t *)(file.start + 0x10 + slot * 8);
+
+		/* Find free slot if in auto mode */
+		for (; automatic && check_signature(le64toh(*ec_pd_fw_ptr)) && slot < 12; slot++)
+			ec_pd_fw_ptr++;
+
+		if (slot == 12) {
+			fprintf(stderr, "ERROR: No free slots left\n\n");
+			goto error;
+		}
+
+		*ec_pd_fw_ptr = htole64(gen_signature(area->offset, area->size));
+	} else {
+		fprintf(stderr, "ERROR: FMAP not found \"%s\"\n", rom_file);
+		goto error;
+	}
+
+	ret = true;
+error:
+	unmap_file(file);
+	return ret;
+}
diff --git a/util/amdtools/ec_usb_pd_fw/rom.h b/util/amdtools/ec_usb_pd_fw/rom.h
new file mode 100644
index 0000000000..452f2ecb1a
--- /dev/null
+++ b/util/amdtools/ec_usb_pd_fw/rom.h
@@ -0,0 +1,10 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#ifndef EC_USB_PD_FW__ROM_H__
+#define EC_USB_PD_FW__ROM_H__
+
+#include <stdbool.h>
+
+bool rom_set_pd_fw_ptr(const char rom_file[], const char *fmap_region_name, int slot, bool automatic);
+
+#endif // EC_USB_PD_FW__ROM_H__
diff --git a/util/amdtools/ec_usb_pd_fw/utils.c b/util/amdtools/ec_usb_pd_fw/utils.c
new file mode 100644
index 0000000000..e196ff35a7
--- /dev/null
+++ b/util/amdtools/ec_usb_pd_fw/utils.c
@@ -0,0 +1,61 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include "utils.h"
+
+#include <sys/mman.h>
+#include <sys/stat.h>
+#include <fcntl.h>
+#include <unistd.h>
+
+#include <errno.h>
+#include <limits.h>
+#include <stdbool.h>
+#include <stddef.h>
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+
+struct mem_range map_file(const char path[], bool rw)
+{
+	struct mem_range range = {0};
+
+	int open_flags = rw ? O_RDWR : O_RDONLY;
+	int mmap_flags = rw ? PROT_READ | PROT_WRITE : PROT_READ;
+
+	int fd = open(path, open_flags);
+	if (fd == -1) {
+		fprintf(stderr, "Failed to open(): %s\n", strerror(errno));
+		return range;
+	}
+
+	struct stat stat_buf;
+	if (fstat(fd, &stat_buf) != 0) {
+		(void)close(fd);
+		fprintf(stderr, "Failed to fstat(): %s\n", strerror(errno));
+		return range;
+	}
+
+	if (stat_buf.st_size == 0) {
+		(void)close(fd);
+		fprintf(stderr, "Can't map an empty \"%s\" file\n", path);
+		return range;
+	}
+
+	uint8_t *mem = mmap(/*addr=*/NULL, stat_buf.st_size, mmap_flags,
+			    MAP_SHARED | MAP_POPULATE, fd, /*offset=*/0);
+	(void)close(fd);
+	if (mem == MAP_FAILED) {
+		fprintf(stderr, "Failed to mmap(): %s\n", strerror(errno));
+		return range;
+	}
+
+	range.start = mem;
+	range.length = stat_buf.st_size;
+	return range;
+}
+
+void unmap_file(struct mem_range store)
+{
+	if (munmap(store.start, store.length) != 0)
+		fprintf(stderr, "Failed to munmap(): %s\n", strerror(errno));
+}
diff --git a/util/amdtools/ec_usb_pd_fw/utils.h b/util/amdtools/ec_usb_pd_fw/utils.h
new file mode 100644
index 0000000000..f914e2ceb4
--- /dev/null
+++ b/util/amdtools/ec_usb_pd_fw/utils.h
@@ -0,0 +1,20 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#ifndef EC_USB_PD_FW__UTILS_H__
+#define EC_USB_PD_FW__UTILS_H__
+
+#include <stddef.h>
+#include <stdbool.h>
+#include <stdint.h>
+
+struct mem_range {
+	uint8_t *start;
+	size_t length;
+};
+uint8_t crc8_itu(const uint8_t *data, int len);
+
+struct mem_range map_file(const char path[], bool rw);
+
+void unmap_file(struct mem_range store);
+
+#endif // EC_USB_PD_FW__UTILS_H__

From 3698517d82df048c2a2b2c901b3aa1b790f8bdc0 Mon Sep 17 00:00:00 2001
From: Patrick Rudolph <patrick.rudolph@9elements.com>
Date: Wed, 23 Apr 2025 12:06:07 +0200
Subject: [PATCH 1587/3886] mb/amd: Use mec152x tool

Instead of providing an EC_SIG binary blob, generate it at build time
using the mec152x tool. Allows to move the EC_BODY in the fmap without
the need to generate a new EC_SIG.

TEST=Booted on amd/birman_plus without EC_SIG blob.
Change-Id: I2d7a791820d905b088194b290853509f10689fc6
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87429
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/amd/birman/Kconfig          | 9 ---------
 src/mainboard/amd/birman/Makefile.mk      | 7 ++++---
 src/mainboard/amd/birman_plus/Kconfig     | 9 ---------
 src/mainboard/amd/birman_plus/Makefile.mk | 7 ++++---
 src/mainboard/amd/crater/Kconfig          | 8 --------
 src/mainboard/amd/crater/Makefile.mk      | 7 ++++---
 6 files changed, 12 insertions(+), 35 deletions(-)

diff --git a/src/mainboard/amd/birman/Kconfig b/src/mainboard/amd/birman/Kconfig
index 3a9ffc77f1..f690e5e67a 100644
--- a/src/mainboard/amd/birman/Kconfig
+++ b/src/mainboard/amd/birman/Kconfig
@@ -52,15 +52,6 @@ config BIRMAN_HAVE_MCHP_FW
 	bool "Have Microchip EC firmware?"
 	default n
 
-config BIRMAN_MCHP_SIG_FILE
-	string "Microchip EC signature file"
-	depends on BIRMAN_HAVE_MCHP_FW
-	default "3rdparty/blobs/mainboard/amd/birman/EC_birman_sig.bin"
-	help
-	  The EC sig blob is the first 4kBytes of the firmware image.
-	  The first 4 bytes form a pointer (with CRC) to where the EC firmware
-	  is located
-
 config AMD_SOC_CONSOLE_UART
 	default y if !SOC_AMD_COMMON_BLOCK_SIMNOW_BUILD
 
diff --git a/src/mainboard/amd/birman/Makefile.mk b/src/mainboard/amd/birman/Makefile.mk
index a784d1a7fa..aa26adb4fe 100644
--- a/src/mainboard/amd/birman/Makefile.mk
+++ b/src/mainboard/amd/birman/Makefile.mk
@@ -23,10 +23,11 @@ show_notices:: warn_no_apcb
 endif
 
 ifeq ($(CONFIG_BIRMAN_HAVE_MCHP_FW),y)
-$(call add_intermediate, add_mchp_fw)
-	$(CBFSTOOL) $(obj)/coreboot.pre write -r EC_SIG -f $(CONFIG_BIRMAN_MCHP_SIG_FILE) --fill-upward
-	$(CBFSTOOL) $(obj)/coreboot.pre write -r EC_BODY -f $(CONFIG_BIRMAN_MCHP_FW_FILE) --fill-upward
+subdirs-y += ../../../../util/mec152x
 
+$(call add_intermediate, add_mchp_fw, $(objutil)/mec152x/mec152xtool)
+	$(CBFSTOOL) $(obj)/coreboot.pre write -r EC_BODY -f $(CONFIG_BIRMAN_MCHP_FW_FILE) --fill-upward
+	$(objutil)/mec152x/mec152xtool $(obj)/coreboot.pre GEN_ECFW_PTR -f EC_BODY
 else
 show_notices:: warn_no_mchp
 endif # CONFIG_BIRMAN_HAVE_MCHP_FW
diff --git a/src/mainboard/amd/birman_plus/Kconfig b/src/mainboard/amd/birman_plus/Kconfig
index 62d5c29141..a5291a495c 100644
--- a/src/mainboard/amd/birman_plus/Kconfig
+++ b/src/mainboard/amd/birman_plus/Kconfig
@@ -48,15 +48,6 @@ config BIRMANPLUS_HAVE_MCHP_FW
 	bool "Have Microchip EC firmware?"
 	default n
 
-config BIRMANPLUS_MCHP_SIG_FILE
-	string "Microchip EC signature file"
-	depends on BIRMANPLUS_HAVE_MCHP_FW
-	default "3rdparty/blobs/mainboard/amd/birman_plus/EC_birmanplus_sig.bin"
-	help
-	  The EC sig blob is the first 4kBytes of the firmware image.
-	  The first 4 bytes form a pointer (with CRC) to where the EC firmware
-	  is located
-
 config AMD_SOC_CONSOLE_UART
 	default y if !SOC_AMD_COMMON_BLOCK_SIMNOW_BUILD
 
diff --git a/src/mainboard/amd/birman_plus/Makefile.mk b/src/mainboard/amd/birman_plus/Makefile.mk
index 5ef9ed92e3..c025591115 100644
--- a/src/mainboard/amd/birman_plus/Makefile.mk
+++ b/src/mainboard/amd/birman_plus/Makefile.mk
@@ -20,10 +20,11 @@ show_notices:: warn_no_apcb
 endif
 
 ifeq ($(CONFIG_BIRMANPLUS_HAVE_MCHP_FW),y)
-$(call add_intermediate, add_mchp_fw)
-	$(CBFSTOOL) $(obj)/coreboot.pre write -r EC_SIG -f $(CONFIG_BIRMANPLUS_MCHP_SIG_FILE) --fill-upward
-	$(CBFSTOOL) $(obj)/coreboot.pre write -r EC_BODY -f $(CONFIG_BIRMANPLUS_MCHP_FW_FILE) --fill-upward
+subdirs-y += ../../../../util/mec152x
 
+$(call add_intermediate, add_mchp_fw, $(objutil)/mec152x/mec152xtool)
+	$(CBFSTOOL) $(obj)/coreboot.pre write -r EC_BODY -f $(CONFIG_BIRMANPLUS_MCHP_FW_FILE) --fill-upward
+	$(objutil)/mec152x/mec152xtool $(obj)/coreboot.pre GEN_ECFW_PTR -f EC_BODY
 else
 show_notices:: warn_no_mchp
 endif # CONFIG_BIRMAN_HAVE_MCHP_FW
diff --git a/src/mainboard/amd/crater/Kconfig b/src/mainboard/amd/crater/Kconfig
index 11bd6b9cf7..136d1b834c 100644
--- a/src/mainboard/amd/crater/Kconfig
+++ b/src/mainboard/amd/crater/Kconfig
@@ -42,14 +42,6 @@ config CRATER_HAVE_MCHP_FW
 	bool "Have Microchip EC firmware?"
 	default n
 
-config CRATER_MCHP_SIG_FILE
-	string "Microchip EC signature file"
-	depends on CRATER_HAVE_MCHP_FW
-	help
-	  The EC sig blob is the first 4kBytes of the firmware image.
-	  The first 4 bytes form a pointer (with CRC) to where the EC firmware
-	  is located
-
 config AMD_SOC_CONSOLE_UART
 	default y if !SOC_AMD_COMMON_BLOCK_SIMNOW_BUILD
 
diff --git a/src/mainboard/amd/crater/Makefile.mk b/src/mainboard/amd/crater/Makefile.mk
index dc169f1969..3207c59c5c 100644
--- a/src/mainboard/amd/crater/Makefile.mk
+++ b/src/mainboard/amd/crater/Makefile.mk
@@ -18,10 +18,11 @@ show_notices:: warn_no_apcb
 endif
 
 ifeq ($(CONFIG_CRATER_HAVE_MCHP_FW),y)
-$(call add_intermediate, add_mchp_fw)
-	$(CBFSTOOL) $(obj)/coreboot.pre write -r EC_SIG -f $(CONFIG_CRATER_MCHP_SIG_FILE) --fill-upward
-	$(CBFSTOOL) $(obj)/coreboot.pre write -r EC_BODY -f $(CONFIG_CRATER_MCHP_FW_FILE) --fill-upward
+subdirs-y += ../../../../util/mec152x
 
+$(call add_intermediate, add_mchp_fw, $(objutil)/mec152x/mec152xtool)
+	$(CBFSTOOL) $(obj)/coreboot.pre write -r EC_BODY -f $(CONFIG_CRATER_MCHP_FW_FILE) --fill-upward
+	$(objutil)/mec152x/mec152xtool $(obj)/coreboot.pre GEN_ECFW_PTR -f EC_BODY
 else
 show_notices:: warn_no_mchp
 endif

From a6fbaa47ea9859319f1dbe55b804d0cd7e549adf Mon Sep 17 00:00:00 2001
From: Benjamin Doron <benjamin.doron@9elements.com>
Date: Fri, 11 Jul 2025 16:56:54 -0400
Subject: [PATCH 1588/3886] util/smmstoretool: Clarify the `auth_vars` field

We want to distinguish between a variable store that's marked as capable
of storing authenticated variables (basically, checking their signatures
and promising that there's no TOCTOU possible), and a variable with the
authentication-checking enabled.

Change-Id: Ibf6ffbe279961ff54b0988d98a912a8421598e3b
Signed-off-by: Benjamin Doron <benjamin.doron@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88423
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
---
 util/smmstoretool/fv.c      | 10 +++++-----
 util/smmstoretool/fv.h      |  2 +-
 util/smmstoretool/storage.c |  8 ++++----
 util/smmstoretool/vs.c      | 20 ++++++++++----------
 util/smmstoretool/vs.h      |  4 ++--
 5 files changed, 22 insertions(+), 22 deletions(-)

diff --git a/util/smmstoretool/fv.c b/util/smmstoretool/fv.c
index c6ee913d3c..89212bad43 100644
--- a/util/smmstoretool/fv.c
+++ b/util/smmstoretool/fv.c
@@ -124,10 +124,10 @@ static bool check_fw_vol_hdr(const EFI_FIRMWARE_VOLUME_HEADER *hdr,
 
 static bool check_var_store_hdr(const VARIABLE_STORE_HEADER *hdr,
 				size_t max_size,
-				bool *auth_vars)
+				bool *is_auth_var_store)
 {
-	*auth_vars = guid_eq(&hdr->Signature, &EfiAuthenticatedVariableGuid);
-	if (!*auth_vars && !guid_eq(&hdr->Signature, &EfiVariableGuid)) {
+	*is_auth_var_store = guid_eq(&hdr->Signature, &EfiAuthenticatedVariableGuid);
+	if (!*is_auth_var_store && !guid_eq(&hdr->Signature, &EfiVariableGuid)) {
 		fprintf(stderr, "Variable store has unexpected GUID\n");
 		return false;
 	}
@@ -152,7 +152,7 @@ static bool check_var_store_hdr(const VARIABLE_STORE_HEADER *hdr,
 }
 
 bool fv_parse(struct mem_range_t fv, struct mem_range_t *var_store,
-	      bool *auth_vars)
+	      bool *is_auth_var_store)
 {
 	const EFI_FIRMWARE_VOLUME_HEADER *vol_hdr = (void *)fv.start;
 	if (!check_fw_vol_hdr(vol_hdr, fv.length)) {
@@ -163,7 +163,7 @@ bool fv_parse(struct mem_range_t fv, struct mem_range_t *var_store,
 	uint8_t *fw_vol_data = fv.start + vol_hdr->HeaderLength;
 	size_t volume_size = fv.length - vol_hdr->HeaderLength;
 	const VARIABLE_STORE_HEADER *var_store_hdr = (void *)fw_vol_data;
-	if (!check_var_store_hdr(var_store_hdr, volume_size, auth_vars)) {
+	if (!check_var_store_hdr(var_store_hdr, volume_size, is_auth_var_store)) {
 		fprintf(stderr, "No valid variable store was found");
 		return false;
 	}
diff --git a/util/smmstoretool/fv.h b/util/smmstoretool/fv.h
index b28db4cbf2..23d54dc40a 100644
--- a/util/smmstoretool/fv.h
+++ b/util/smmstoretool/fv.h
@@ -14,6 +14,6 @@ bool fv_init(struct mem_range_t fv);
 
 bool fv_parse(struct mem_range_t fv,
 	      struct mem_range_t *var_store,
-	      bool *auth_vars);
+	      bool *is_auth_var_store);
 
 #endif // SMMSTORETOOL__FV_H__
diff --git a/util/smmstoretool/storage.c b/util/smmstoretool/storage.c
index 87284f7bf3..45ea955c02 100644
--- a/util/smmstoretool/storage.c
+++ b/util/smmstoretool/storage.c
@@ -41,8 +41,8 @@ bool storage_open(const char store_file[], struct storage_t *storage, bool rw)
 		storage->region.length = area->size;
 	}
 
-	bool auth_vars;
-	if (!fv_parse(storage->region, &storage->store_area, &auth_vars)) {
+	bool is_auth_var_store;
+	if (!fv_parse(storage->region, &storage->store_area, &is_auth_var_store)) {
 		if (!rw) {
 			fprintf(stderr,
 				"Failed to find variable store in \"%s\"\n",
@@ -63,7 +63,7 @@ bool storage_open(const char store_file[], struct storage_t *storage, bool rw)
 			goto error;
 		}
 
-		if (!fv_parse(storage->region, &storage->store_area, &auth_vars)) {
+		if (!fv_parse(storage->region, &storage->store_area, &is_auth_var_store)) {
 			fprintf(stderr,
 				"Failed to parse newly formatted store in \"%s\"\n",
 				store_file);
@@ -75,7 +75,7 @@ bool storage_open(const char store_file[], struct storage_t *storage, bool rw)
 			store_file);
 	}
 
-	storage->vs = vs_load(storage->store_area, auth_vars);
+	storage->vs = vs_load(storage->store_area, is_auth_var_store);
 	return true;
 
 error:
diff --git a/util/smmstoretool/vs.c b/util/smmstoretool/vs.c
index a1167ca2de..0060e69b02 100644
--- a/util/smmstoretool/vs.c
+++ b/util/smmstoretool/vs.c
@@ -10,32 +10,32 @@
 #include "udk2017.h"
 #include "utils.h"
 
-static size_t get_var_hdr_size(bool auth_vars)
+static size_t get_var_hdr_size(bool is_auth_var_store)
 {
-	if (auth_vars)
+	if (is_auth_var_store)
 		return sizeof(AUTHENTICATED_VARIABLE_HEADER);
 	return sizeof(VARIABLE_HEADER);
 }
 
-struct var_store_t vs_load(struct mem_range_t vs_data, bool auth_vars)
+struct var_store_t vs_load(struct mem_range_t vs_data, bool is_auth_var_store)
 {
 	uint8_t *var_hdr = vs_data.start;
 
 	struct var_store_t vs = {
-		.auth_vars = auth_vars,
+		.is_auth_var_store = is_auth_var_store,
 		.vars = NULL,
 	};
 
 	struct var_t *last_var = NULL;
 
-	const size_t var_hdr_size = get_var_hdr_size(auth_vars);
+	const size_t var_hdr_size = get_var_hdr_size(is_auth_var_store);
 	while (var_hdr + var_hdr_size < vs_data.start + vs_data.length) {
 		uint16_t start_id;
 		uint8_t state;
 		struct var_t var = {0};
 		uint8_t *var_data = var_hdr;
 
-		if (auth_vars) {
+		if (is_auth_var_store) {
 			const AUTHENTICATED_VARIABLE_HEADER *auth_hdr =
 				(void *)var_data;
 
@@ -96,9 +96,9 @@ struct var_store_t vs_load(struct mem_range_t vs_data, bool auth_vars)
 	return vs;
 }
 
-static void store_var(const struct var_t *var, bool auth_vars, uint8_t *data)
+static void store_var(const struct var_t *var, bool is_auth_var_store, uint8_t *data)
 {
-	if (auth_vars) {
+	if (is_auth_var_store) {
 		AUTHENTICATED_VARIABLE_HEADER hdr;
 		memset(&hdr, 0xff, sizeof(hdr));
 
@@ -136,7 +136,7 @@ bool vs_store(struct var_store_t *vs, struct mem_range_t vs_data)
 {
 	uint8_t *out_data = vs_data.start;
 
-	const size_t var_hdr_size = get_var_hdr_size(vs->auth_vars);
+	const size_t var_hdr_size = get_var_hdr_size(vs->is_auth_var_store);
 	for (struct var_t *var = vs->vars; var != NULL; var = var->next) {
 		const size_t var_size =
 			var_hdr_size + var->name_size + var->data_size;
@@ -146,7 +146,7 @@ bool vs_store(struct var_store_t *vs, struct mem_range_t vs_data)
 			return false;
 		}
 
-		store_var(var, vs->auth_vars, out_data);
+		store_var(var, vs->is_auth_var_store, out_data);
 		out_data += HEADER_ALIGN(var_size);
 	}
 
diff --git a/util/smmstoretool/vs.h b/util/smmstoretool/vs.h
index 2ac9e6c8b2..d3dfeeaf33 100644
--- a/util/smmstoretool/vs.h
+++ b/util/smmstoretool/vs.h
@@ -24,10 +24,10 @@ struct var_t {
 
 struct var_store_t {
 	struct var_t *vars;
-	bool auth_vars;
+	bool is_auth_var_store;
 };
 
-struct var_store_t vs_load(struct mem_range_t vs_data, bool auth_vars);
+struct var_store_t vs_load(struct mem_range_t vs_data, bool is_auth_var_store);
 
 bool vs_store(struct var_store_t *vs, struct mem_range_t vs_data);
 

From b49f567e45d231c70b2e5c4f5055e4cac0a893dc Mon Sep 17 00:00:00 2001
From: Benjamin Doron <benjamin.doron@9elements.com>
Date: Wed, 16 Jul 2025 12:44:20 -0400
Subject: [PATCH 1589/3886] util/smmstoretool: Ensure that the FVB header isn't
 too large

If the header size is equal to fv.length, then `fv_parse()` will go
out-of-bounds when obtaining the variable store data, and obviously,
there is no data if the header takes up all available space.

Change-Id: I0ac46e098a14b51f936cb99f5e6bf83411570bc5
Signed-off-by: Benjamin Doron <benjamin.doron@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88452
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
---
 util/smmstoretool/fv.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/util/smmstoretool/fv.c b/util/smmstoretool/fv.c
index 89212bad43..8ac8646d92 100644
--- a/util/smmstoretool/fv.c
+++ b/util/smmstoretool/fv.c
@@ -100,7 +100,7 @@ static bool check_fw_vol_hdr(const EFI_FIRMWARE_VOLUME_HEADER *hdr,
 	if (hdr->Revision != EFI_FVH_REVISION ||
 		hdr->Signature != EFI_FVH_SIGNATURE ||
 		hdr->FvLength > max_size ||
-		hdr->HeaderLength > max_size ||
+		hdr->HeaderLength >= max_size ||
 		hdr->HeaderLength % 2 != 0) {
 		fprintf(stderr, "No firmware volume header present\n");
 		return false;

From 30584642632d5691c24e9c697b288aff9ac7120d Mon Sep 17 00:00:00 2001
From: Benjamin Doron <benjamin.doron@9elements.com>
Date: Thu, 10 Jul 2025 11:57:41 -0400
Subject: [PATCH 1590/3886] util/smmstoretool: Add support for creating
 variable from file contents

This helps with initialising UEFI secure boot variables for the first
boot, for example, by setting PKDefault, KEKDefault, dbDefault and
dbxDefault to the desired certificates.

Tested, and the get subcommand returns the same data that the set
command added. However, EDK2's variable driver (from approximately
edk2-stable202505) asserts that the variable store isn't the expected
size, and UEFITool can't decode it correctly. This is also the case for
other types supported before this patch, suggesting that the bug is in
general variable-handling code in this utility. Will be debugged and
addressed in a follow-up.

Change-Id: If36394bb56388a35882702c93e26e63124fe0a63
Signed-off-by: Benjamin Doron <benjamin.doron@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88377
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 util/smmstoretool/data.c | 16 ++++++++++++++++
 util/smmstoretool/data.h |  1 +
 util/smmstoretool/main.c |  1 +
 3 files changed, 18 insertions(+)

diff --git a/util/smmstoretool/data.c b/util/smmstoretool/data.c
index 41d3b75aba..5eca5f6a81 100644
--- a/util/smmstoretool/data.c
+++ b/util/smmstoretool/data.c
@@ -80,6 +80,9 @@ void print_data(const uint8_t data[], size_t data_size, enum data_type type)
 		printf("%s\n", chars);
 		free(chars);
 		break;
+	case DATA_TYPE_FILE:
+		fprintf(stderr, "File data type is input only\n");
+		break;
 	case DATA_TYPE_RAW:
 		fwrite(data, 1, data_size, stdout);
 		break;
@@ -115,6 +118,7 @@ void *make_data(const char source[], size_t *data_size, enum data_type type)
 	void *data;
 	bool boolean;
 	uint64_t uint;
+	struct mem_range_t file;
 	bool failed;
 
 	case DATA_TYPE_BOOL:
@@ -173,6 +177,16 @@ void *make_data(const char source[], size_t *data_size, enum data_type type)
 		return strdup(source);
 	case DATA_TYPE_UNICODE:
 		return to_uchars(source, data_size);
+	case DATA_TYPE_FILE:
+		file = map_file(source, /*rw=*/false);
+		if (file.start == NULL || file.length == 0)
+			return NULL;
+
+		*data_size = file.length;
+		data = xmalloc(*data_size);
+		memcpy(data, file.start, *data_size);
+		unmap_file(file);
+		return data;
 	case DATA_TYPE_RAW:
 		fprintf(stderr, "Raw data type is output only\n");
 		return NULL;
@@ -197,6 +211,8 @@ bool parse_data_type(const char str[], enum data_type *type)
 		*type = DATA_TYPE_ASCII;
 	else if (str_eq(str, "unicode"))
 		*type = DATA_TYPE_UNICODE;
+	else if (str_eq(str, "file"))
+		*type = DATA_TYPE_FILE;
 	else if (str_eq(str, "raw"))
 		*type = DATA_TYPE_RAW;
 	else
diff --git a/util/smmstoretool/data.h b/util/smmstoretool/data.h
index 58e6c7d7a6..9bd4506856 100644
--- a/util/smmstoretool/data.h
+++ b/util/smmstoretool/data.h
@@ -15,6 +15,7 @@ enum data_type {
 	DATA_TYPE_UINT64,
 	DATA_TYPE_ASCII,
 	DATA_TYPE_UNICODE,
+	DATA_TYPE_FILE,
 	DATA_TYPE_RAW,
 };
 
diff --git a/util/smmstoretool/main.c b/util/smmstoretool/main.c
index 89d58d619a..4092fc59dc 100644
--- a/util/smmstoretool/main.c
+++ b/util/smmstoretool/main.c
@@ -128,6 +128,7 @@ static void print_types(FILE *f)
 	fprintf(f, " * uint64 (0..2^64-1)\n");
 	fprintf(f, " * ascii (NUL-terminated)\n");
 	fprintf(f, " * unicode (widened and NUL-terminated)\n");
+	fprintf(f, " * file (input only; file contents as variable)\n");
 	fprintf(f, " * raw (output only; raw bytes on output)\n");
 }
 

From 2181b027650e169e1b25a67b2bca038cfb4db50b Mon Sep 17 00:00:00 2001
From: Benjamin Doron <benjamin.doron@9elements.com>
Date: Fri, 11 Jul 2025 17:11:40 -0400
Subject: [PATCH 1591/3886] util/smmstoretool: Properly initialise the
 authenticated variable header

MonotonicCount is required, or UEFITool fails to parse the store.
TimeStamp is required for variables with authenticated attributes.

Change-Id: Iea933c9943ec18ea773700cdf1e3bede0e8ef292
Signed-off-by: Benjamin Doron <benjamin.doron00@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88424
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 util/smmstoretool/fv.c | 1 -
 util/smmstoretool/vs.c | 4 ++++
 2 files changed, 4 insertions(+), 1 deletion(-)

diff --git a/util/smmstoretool/fv.c b/util/smmstoretool/fv.c
index 8ac8646d92..2744292761 100644
--- a/util/smmstoretool/fv.c
+++ b/util/smmstoretool/fv.c
@@ -73,7 +73,6 @@ bool fv_init(struct mem_range_t fv)
 	++vol_hdr_dst->Checksum;
 
 	const VARIABLE_STORE_HEADER var_store_hdr = {
-		// Authentication-related fields will be filled with 0xff.
 		.Signature = EfiAuthenticatedVariableGuid,
 		// Actual size of the storage is block size, the rest is
 		// Fault Tolerant Write (FTW) space and the FTW spare space.
diff --git a/util/smmstoretool/vs.c b/util/smmstoretool/vs.c
index 0060e69b02..f78ed0aad2 100644
--- a/util/smmstoretool/vs.c
+++ b/util/smmstoretool/vs.c
@@ -110,6 +110,10 @@ static void store_var(const struct var_t *var, bool is_auth_var_store, uint8_t *
 		hdr.NameSize = var->name_size;
 		hdr.DataSize = var->data_size;
 
+		hdr.MonotonicCount = 0;
+		memset(&hdr.TimeStamp, 0, sizeof(hdr.TimeStamp));
+		//hdr.PubKeyIndex = 0;
+
 		memcpy(data, &hdr, sizeof(hdr));
 		data += sizeof(hdr);
 	} else {

From 96e381766e8dfd79e3c859e2de0e7c787df8b50a Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Fri, 11 Jul 2025 16:11:47 -0500
Subject: [PATCH 1592/3886] ec/lenovo: Add support for MEC1653 EC
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Add support for the MEC1653 EC as used by the Thinkpad T480/480s.

Change-Id: If82a7d27eb3163f51565c0c6e60cab60753611a7
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88395
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Reviewed-by: Filip Lewiński <filip.lewinski@3mdeb.com>
Reviewed-by: Máté Kukri <km@mkukri.xyz>
---
 src/ec/lenovo/mec1653/Kconfig     | 24 +++++++++
 src/ec/lenovo/mec1653/Makefile.mk |  9 ++++
 src/ec/lenovo/mec1653/debug.c     | 81 +++++++++++++++++++++++++++++++
 src/ec/lenovo/mec1653/debug.h     | 36 ++++++++++++++
 src/ec/lenovo/mec1653/mec1653.c   | 30 ++++++++++++
 src/ec/lenovo/mec1653/mec1653.h   |  8 +++
 src/ec/lenovo/mec1653/uart.c      | 47 ++++++++++++++++++
 src/ec/lenovo/mec1653/uart.h      | 35 +++++++++++++
 8 files changed, 270 insertions(+)
 create mode 100644 src/ec/lenovo/mec1653/Kconfig
 create mode 100644 src/ec/lenovo/mec1653/Makefile.mk
 create mode 100644 src/ec/lenovo/mec1653/debug.c
 create mode 100644 src/ec/lenovo/mec1653/debug.h
 create mode 100644 src/ec/lenovo/mec1653/mec1653.c
 create mode 100644 src/ec/lenovo/mec1653/mec1653.h
 create mode 100644 src/ec/lenovo/mec1653/uart.c
 create mode 100644 src/ec/lenovo/mec1653/uart.h

diff --git a/src/ec/lenovo/mec1653/Kconfig b/src/ec/lenovo/mec1653/Kconfig
new file mode 100644
index 0000000000..463b00559a
--- /dev/null
+++ b/src/ec/lenovo/mec1653/Kconfig
@@ -0,0 +1,24 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
+config EC_LENOVO_MEC1653
+	bool
+
+if EC_LENOVO_MEC1653
+
+config MEC1653_HAS_DEBUG_UNLOCK
+	bool
+
+config MEC1653_DEBUG_UNLOCK_KEY
+	string
+	depends on MEC1653_HAS_DEBUG_UNLOCK
+	help
+	  Debug unlock key necessary to enable the UART.
+
+config MEC1653_ENABLE_UART
+	bool "Enable EC UART"
+	depends on MEC1653_HAS_DEBUG_UNLOCK
+	help
+	  The EC UART physical interface is board-specific and requires
+	  a board-specific debug unlock key.
+
+endif
diff --git a/src/ec/lenovo/mec1653/Makefile.mk b/src/ec/lenovo/mec1653/Makefile.mk
new file mode 100644
index 0000000000..2188069c7c
--- /dev/null
+++ b/src/ec/lenovo/mec1653/Makefile.mk
@@ -0,0 +1,9 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
+ifeq ($(CONFIG_EC_LENOVO_MEC1653),y)
+
+bootblock-y += mec1653.c
+bootblock-$(CONFIG_MEC1653_ENABLE_UART) += debug.c
+bootblock-$(CONFIG_MEC1653_ENABLE_UART) += uart.c
+
+endif
diff --git a/src/ec/lenovo/mec1653/debug.c b/src/ec/lenovo/mec1653/debug.c
new file mode 100644
index 0000000000..5f7000b320
--- /dev/null
+++ b/src/ec/lenovo/mec1653/debug.c
@@ -0,0 +1,81 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <arch/io.h>
+#include <ec/acpi/ec.h>
+#include "debug.h"
+#include "mec1653.h"
+
+
+static void debug_cmd(uint8_t cmd)
+{
+	ec_set_ports(EC_SC, EC_DATA);
+	ec_write(EC_DEBUG_CMD, cmd);
+	while (ec_read(EC_DEBUG_CMD) & 0x80)
+		;
+}
+
+uint32_t debug_read_dword(uint32_t addr)
+{
+	ec_set_ports(EC3_CMD, EC3_DATA);
+	ec_clear_out_queue();
+	ec_ready_send(EC_SEND_TIMEOUT_US);
+	outl(addr << 8 | 0xE2, EC3_DATA);
+	ec_ready_recv(EC_SEND_TIMEOUT_US);
+	return inl(EC3_DATA);
+}
+
+void debug_write_dword(uint32_t addr, uint32_t val)
+{
+	ec_set_ports(EC3_CMD, EC3_DATA);
+	ec_clear_out_queue();
+	ec_ready_send(EC_SEND_TIMEOUT_US);
+	outl(addr << 8 | 0xEA, EC3_DATA);
+	ec_ready_send(EC_SEND_TIMEOUT_US);
+	outl(val, EC3_DATA);
+}
+
+// Helper function to convert hex character to byte
+static uint8_t hex_char_to_byte(char c)
+{
+	if (c >= '0' && c <= '9')
+		return c - '0';
+	if (c >= 'a' && c <= 'f')
+		return c - 'a' + 10;
+	if (c >= 'A' && c <= 'F')
+		return c - 'A' + 10;
+	return 0; // Invalid character
+}
+
+// Helper function to convert 16-char hex string to 8 bytes
+static void hex_string_to_bytes(const char *hex_str, uint8_t *bytes)
+{
+	for (int i = 0; i < 8; ++i) {
+		bytes[i] = (hex_char_to_byte(hex_str[i * 2]) << 4) |
+			   hex_char_to_byte(hex_str[i * 2 + 1]);
+	}
+}
+
+void debug_write_key(uint8_t i, const char *hex_key)
+{
+	uint8_t key_bytes[8];
+
+	ec_set_ports(EC_SC, EC_DATA);
+	hex_string_to_bytes(hex_key, key_bytes);
+
+	for (int j = 0; j < 8; ++j)
+		ec_write(0x3e + j, key_bytes[j]);
+	debug_cmd(0xc0 |  (i & 0xf));
+}
+
+void debug_read_key(uint8_t i, uint8_t *key)
+{
+	debug_cmd(0x80 | (i & 0xf));
+	for (int j = 0; j < 8; ++j)
+		key[j] = ec_read(0x3e + j);
+}
+
+uint16_t debug_loaded_keys(void)
+{
+	ec_set_ports(EC_SC, EC_DATA);
+	return (uint16_t) ec_read(0x87) << 8 | (uint16_t) ec_read(0x86);
+}
diff --git a/src/ec/lenovo/mec1653/debug.h b/src/ec/lenovo/mec1653/debug.h
new file mode 100644
index 0000000000..063b4b58e7
--- /dev/null
+++ b/src/ec/lenovo/mec1653/debug.h
@@ -0,0 +1,36 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef EC_LENOVO_MEC1653_DEBUG_H
+#define EC_LENOVO_MEC1653_DEBUG_H
+
+// The following location (via either EC0 or EC1) can be used to interact with the debug interface
+#define EC_DEBUG_CMD		0x3d
+
+// RW unlock key index
+#define DEBUG_RW_KEY_IDX	1
+
+#define EC_SEND_TIMEOUT_US	20000	// 20ms
+#define EC_RECV_TIMEOUT_US	320000	// 320ms
+
+#define EC0_CMD		0x0066
+#define EC0_DATA	0x0062
+#define EC1_CMD		0x1604
+#define EC1_DATA	0x1600
+#define EC2_CMD		0x1634
+#define EC2_DATA	0x1630
+#define EC3_CMD		0x161c
+#define EC3_DATA	0x1618
+
+
+// Read loaded debug key mask
+uint16_t debug_loaded_keys(void);
+
+void debug_read_key(uint8_t i, uint8_t *key);
+
+void debug_write_key(uint8_t i, const char *hex_key);
+
+uint32_t debug_read_dword(uint32_t addr);
+
+void debug_write_dword(uint32_t addr, uint32_t val);
+
+#endif /* EC_LENOVO_MEC1653_DEBUG_H */
diff --git a/src/ec/lenovo/mec1653/mec1653.c b/src/ec/lenovo/mec1653/mec1653.c
new file mode 100644
index 0000000000..08682c0e38
--- /dev/null
+++ b/src/ec/lenovo/mec1653/mec1653.c
@@ -0,0 +1,30 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <ec/acpi/ec.h>
+#include <arch/io.h>
+#include "mec1653.h"
+#include "uart.h"
+
+void bootblock_ec_init(void)
+{
+	// Tell EC via BIOS Debug Port 1 that the world isn't on fire
+
+	// Let the EC know that BIOS code is running
+	outb(0x11, 0x86);
+	outb(0x6e, 0x86);
+
+	// Enable accesses to EC1 interface
+	ec_set_ports(EC_SC, EC_DATA);
+	ec_clear_out_queue();
+	ec_write(ec_read(0), 0x20);
+
+	// Reset LEDs to power on state
+	// (Without this warm reboot leaves LEDs off)
+	ec_write(0x0c, 0x80);
+	ec_write(0x0c, 0x07);
+	ec_write(0x0c, 0x8a);
+
+	// Setup debug UART
+	if (CONFIG(MEC1653_ENABLE_UART))
+		mec1653_configure_uart();
+}
diff --git a/src/ec/lenovo/mec1653/mec1653.h b/src/ec/lenovo/mec1653/mec1653.h
new file mode 100644
index 0000000000..c3d6074465
--- /dev/null
+++ b/src/ec/lenovo/mec1653/mec1653.h
@@ -0,0 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef EC_LENOVO_MEC1653_H
+#define EC_LENOVO_MEC1653_H
+
+void bootblock_ec_init(void);
+
+#endif /* EC_LENOVO_MEC1653_H */
diff --git a/src/ec/lenovo/mec1653/uart.c b/src/ec/lenovo/mec1653/uart.c
new file mode 100644
index 0000000000..c6a6186406
--- /dev/null
+++ b/src/ec/lenovo/mec1653/uart.c
@@ -0,0 +1,47 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <device/pnp_ops.h>
+#include <ec/lenovo/mec1653/mec1653.h>
+#include "debug.h"
+#include "uart.h"
+
+static void pnp_write_config32(pnp_devfn_t dev, uint8_t offset, uint32_t value)
+{
+	pnp_write_config(dev, offset, value & 0xff);
+	pnp_write_config(dev, offset + 1, (value >> 8) & 0xff);
+	pnp_write_config(dev, offset + 2, (value >> 16) & 0xff);
+	pnp_write_config(dev, offset + 3, (value >> 24) & 0xff);
+}
+
+void mec1653_configure_uart(void)
+{
+	pnp_devfn_t lpc_dev = PNP_DEV(EC_CFG_PORT, LDN_LPCIF);
+	pnp_devfn_t uart_dev = PNP_DEV(EC_CFG_PORT, LDN_UART);
+
+	// Enter PNP conf state
+	outb(MEC_CFG_ENTRY_KEY, EC_CFG_PORT);
+
+	// Select LPC I/F LDN
+	pnp_set_logical_device(lpc_dev);
+
+	// Write UART BAR
+	pnp_write_config32(lpc_dev, LPCIF_BAR_UART, (uint32_t) UART_PORT << 16 | 0x8707);
+
+	// Set SIRQ4 to UART
+	pnp_write_config(lpc_dev, LPCIF_SIRQ(UART_IRQ), LDN_UART);
+
+	// Enable and configure UART LDN
+	pnp_set_logical_device(uart_dev);
+	pnp_set_enable(uart_dev, 1);
+	pnp_write_config(uart_dev, UART_CONFIG_SELECT, 0);
+
+	// Exit PNP conf state
+	outb(MEC_CFG_EXIT_KEY, EC_CFG_PORT);
+
+	// Supply debug unlock key
+	debug_write_key(DEBUG_RW_KEY_IDX, CONFIG_MEC1653_DEBUG_UNLOCK_KEY);
+
+	// Use debug writes to set UART_TX and UART_RX GPIOs
+	debug_write_dword(MEC1653_CFG_REG + MEC1653_CFG_TX_GPIO_OFFSET, 0x1000);
+	debug_write_dword(MEC1653_CFG_REG + MEC1653_CFG_RX_GPIO_OFFSET, 0x1000);
+}
diff --git a/src/ec/lenovo/mec1653/uart.h b/src/ec/lenovo/mec1653/uart.h
new file mode 100644
index 0000000000..46fe4d10ff
--- /dev/null
+++ b/src/ec/lenovo/mec1653/uart.h
@@ -0,0 +1,35 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef EC_LENOVO_MEC1653_UART_H
+#define EC_LENOVO_MEC1653_UART_H
+
+#define MEC_CFG_ENTRY_KEY		0x55
+#define MEC_CFG_EXIT_KEY		0xaa
+
+#define UART_PORT			0x3f8
+#define UART_IRQ			4
+
+#define MEC1653_CFG_REG			0xf0c400
+#define  MEC1653_CFG_TX_GPIO_OFFSET	0x110
+#define  MEC1653_CFG_RX_GPIO_OFFSET	0x114
+
+// EC configuration base address
+#define EC_CFG_PORT			0x4e
+
+// Chip global registers
+#define PNP_LDN_SELECT			0x07
+# define LDN_UART			0x07
+# define LDN_LPCIF			0x0c
+
+// LPC I/F registers
+#define LPCIF_SIRQ(i)			(0x40 + (i))
+
+#define LPCIF_BAR_UART			0x80
+
+// UART registers
+#define UART_ACTIVATE			0x30
+#define UART_CONFIG_SELECT		0xf0
+
+void mec1653_configure_uart(void);
+
+#endif /* EC_LENOVO_MEC1653_UART_H */

From ad8b738af009de63cb7474e425e5d0d095643022 Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Wed, 9 Jul 2025 12:28:48 -0500
Subject: [PATCH 1593/3886] mb/lenovo: Add ThinkPad T480 and ThinkPad T480s
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

These machine have BootGuard fused and requires deguard to
boot coreboot.

Known issues:
- Alpine Ridge Thunderbolt 3 controller does not work
- Some Fn+F{1-12} keys aren't handled correctly
- Nvidia dGPU is finicky
  - Needs option ROM
  - Power enable code is buggy
  - Nouveau only works on linux 6.8-6.9
- Headphone jack isn't detected as plugged in despite correct verbs

Thanks to Leah Rowe for helping with the T480s.

Change-Id: I19d421412c771c1f242f6ff39453f824fa866163
Signed-off-by: Mate Kukri <km@mkukri.xyz>
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83274
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Reviewed-by: Filip Lewiński <filip.lewinski@3mdeb.com>
---
 src/mainboard/lenovo/sklkbl_thinkpad/Kconfig  |  92 ++++++++
 .../lenovo/sklkbl_thinkpad/Kconfig.name       |   7 +
 .../lenovo/sklkbl_thinkpad/Makefile.mk        |  16 ++
 .../lenovo/sklkbl_thinkpad/acpi/ec.asl        |  12 ++
 .../lenovo/sklkbl_thinkpad/acpi/superio.asl   |   3 +
 .../lenovo/sklkbl_thinkpad/board_info.txt     |   6 +
 .../lenovo/sklkbl_thinkpad/bootblock.c        |   9 +
 src/mainboard/lenovo/sklkbl_thinkpad/cfr.c    |  82 +++++++
 .../lenovo/sklkbl_thinkpad/devicetree.cb      |  78 +++++++
 src/mainboard/lenovo/sklkbl_thinkpad/dgpu.c   |  66 ++++++
 src/mainboard/lenovo/sklkbl_thinkpad/dsdt.asl |  33 +++
 .../lenovo/sklkbl_thinkpad/ramstage.c         |  23 ++
 .../lenovo/sklkbl_thinkpad/variant.h          |  12 ++
 .../sklkbl_thinkpad/variants/t480/data.vbt    | Bin 0 -> 4106 bytes
 .../variants/t480/gma-mainboard.ads           |  19 ++
 .../sklkbl_thinkpad/variants/t480/gpio.c      | 203 ++++++++++++++++++
 .../sklkbl_thinkpad/variants/t480/hda_verb.c  |  90 ++++++++
 .../variants/t480/include/variant/dgpu.h      |  15 ++
 .../variants/t480/memory_init_params.c        |  20 ++
 .../variants/t480/overridetree.cb             |  93 ++++++++
 .../variants/t480s/Makefile.mk                |  10 +
 .../sklkbl_thinkpad/variants/t480s/data.vbt   | Bin 0 -> 4106 bytes
 .../variants/t480s/gma-mainboard.ads          |  19 ++
 .../sklkbl_thinkpad/variants/t480s/gpio.c     | 199 +++++++++++++++++
 .../sklkbl_thinkpad/variants/t480s/hda_verb.c |  90 ++++++++
 .../variants/t480s/include/variant/dgpu.h     |  15 ++
 .../variants/t480s/memory_init_params.c       |  44 ++++
 .../variants/t480s/overridetree.cb            |  93 ++++++++
 .../variants/t480s/spd/spd_0.bin              | Bin 0 -> 512 bytes
 .../variants/t480s/spd/spd_1.bin              | Bin 0 -> 512 bytes
 .../variants/t480s/spd/spd_10.bin             | Bin 0 -> 512 bytes
 .../variants/t480s/spd/spd_11.bin             | Bin 0 -> 512 bytes
 .../variants/t480s/spd/spd_12.bin             | Bin 0 -> 512 bytes
 .../variants/t480s/spd/spd_13.bin             | Bin 0 -> 512 bytes
 .../variants/t480s/spd/spd_14.bin             | Bin 0 -> 512 bytes
 .../variants/t480s/spd/spd_15.bin             | Bin 0 -> 512 bytes
 .../variants/t480s/spd/spd_16.bin             | Bin 0 -> 512 bytes
 .../variants/t480s/spd/spd_17.bin             | Bin 0 -> 512 bytes
 .../variants/t480s/spd/spd_18.bin             | Bin 0 -> 512 bytes
 .../variants/t480s/spd/spd_19.bin             | Bin 0 -> 512 bytes
 .../variants/t480s/spd/spd_2.bin              | Bin 0 -> 512 bytes
 .../variants/t480s/spd/spd_20.bin             | Bin 0 -> 512 bytes
 .../variants/t480s/spd/spd_3.bin              | Bin 0 -> 512 bytes
 .../variants/t480s/spd/spd_4.bin              | Bin 0 -> 512 bytes
 .../variants/t480s/spd/spd_5.bin              | Bin 0 -> 512 bytes
 .../variants/t480s/spd/spd_6.bin              | Bin 0 -> 512 bytes
 .../variants/t480s/spd/spd_7.bin              | Bin 0 -> 512 bytes
 .../variants/t480s/spd/spd_8.bin              | Bin 0 -> 512 bytes
 .../variants/t480s/spd/spd_9.bin              | Bin 0 -> 512 bytes
 49 files changed, 1349 insertions(+)
 create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/Kconfig
 create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/Kconfig.name
 create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/Makefile.mk
 create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/acpi/ec.asl
 create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/acpi/superio.asl
 create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/board_info.txt
 create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/bootblock.c
 create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/cfr.c
 create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/devicetree.cb
 create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/dgpu.c
 create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/dsdt.asl
 create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/ramstage.c
 create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variant.h
 create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t480/data.vbt
 create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t480/gma-mainboard.ads
 create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t480/gpio.c
 create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t480/hda_verb.c
 create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t480/include/variant/dgpu.h
 create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t480/memory_init_params.c
 create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t480/overridetree.cb
 create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/Makefile.mk
 create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/data.vbt
 create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/gma-mainboard.ads
 create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/gpio.c
 create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/hda_verb.c
 create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/include/variant/dgpu.h
 create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/memory_init_params.c
 create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/overridetree.cb
 create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd/spd_0.bin
 create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd/spd_1.bin
 create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd/spd_10.bin
 create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd/spd_11.bin
 create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd/spd_12.bin
 create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd/spd_13.bin
 create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd/spd_14.bin
 create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd/spd_15.bin
 create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd/spd_16.bin
 create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd/spd_17.bin
 create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd/spd_18.bin
 create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd/spd_19.bin
 create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd/spd_2.bin
 create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd/spd_20.bin
 create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd/spd_3.bin
 create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd/spd_4.bin
 create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd/spd_5.bin
 create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd/spd_6.bin
 create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd/spd_7.bin
 create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd/spd_8.bin
 create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd/spd_9.bin

diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/Kconfig b/src/mainboard/lenovo/sklkbl_thinkpad/Kconfig
new file mode 100644
index 0000000000..6036ceb06d
--- /dev/null
+++ b/src/mainboard/lenovo/sklkbl_thinkpad/Kconfig
@@ -0,0 +1,92 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
+config BOARD_LENOVO_SKLKBL_THINKPAD_COMMON
+	bool
+	select BOARD_ROMSIZE_KB_16384
+	select DRIVERS_OPTION_CFR_ENABLED if PAYLOAD_EDK2 && SMMSTORE
+	select EC_LENOVO_H8
+	select EC_LENOVO_MEC1653
+	select EC_LENOVO_PMH7
+	select H8_HAS_BAT_THRESHOLDS_IMPL
+	select H8_HAS_LEDLOGO
+	select H8_HAS_PRIMARY_FN_KEYS
+	select H8_SUPPORT_BT_ON_WIFI
+	select HAVE_ACPI_RESUME
+	select HAVE_ACPI_TABLES
+	select INTEL_GMA_HAVE_VBT
+	select MAINBOARD_HAS_LIBGFXINIT
+	select MAINBOARD_HAS_TPM2
+	select MAINBOARD_USES_IFD_GBE_REGION
+	select MEMORY_MAPPED_TPM
+	select SOC_INTEL_COMMON_BLOCK_HDA_VERB
+	select SOC_INTEL_KABYLAKE
+	select SPD_READ_BY_WORD
+	select SYSTEM_TYPE_LAPTOP
+
+config BOARD_LENOVO_T480
+	bool
+	select BOARD_LENOVO_SKLKBL_THINKPAD_COMMON
+	select MEC1653_HAS_DEBUG_UNLOCK
+	select VARIANT_HAS_DGPU
+
+config BOARD_LENOVO_T480S
+	bool
+	select BOARD_LENOVO_SKLKBL_THINKPAD_COMMON
+	select VARIANT_HAS_DGPU
+
+if BOARD_LENOVO_SKLKBL_THINKPAD_COMMON
+
+config MAINBOARD_DIR
+	default "lenovo/sklkbl_thinkpad"
+
+config VARIANT_DIR
+	default "t480" if BOARD_LENOVO_T480
+	default "t480s" if BOARD_LENOVO_T480S
+
+config OVERRIDE_DEVICETREE
+	default "variants/\$(CONFIG_VARIANT_DIR)/overridetree.cb"
+
+config MAINBOARD_PART_NUMBER
+	default "T480" if BOARD_LENOVO_T480
+	default "T480s" if BOARD_LENOVO_T480S
+
+config CBFS_SIZE
+	default 0x900000
+
+config DIMM_MAX
+	default 2
+
+config DIMM_SPD_SIZE
+	default 512	# DDR4
+
+config CONSOLE_SERIAL
+	default n
+
+config NO_POST
+	default y
+
+config EDK2_BOOT_MANAGER_ESCAPE
+	default y
+
+config EDK2_FOLLOW_BGRT_SPEC
+	default y
+
+config EDK2_FULL_SCREEN_SETUP
+	default n
+
+config PS2K_EISAID
+	default "LEN0071"
+
+config PS2M_EISAID
+	default "LEN0094"
+
+config THINKPADEC_HKEY_EISAID
+	default "LEN0268"
+
+config MEC1653_DEBUG_UNLOCK_KEY
+	default "7a41b149fe2101cf" if BOARD_LENOVO_T480
+
+config VARIANT_HAS_DGPU
+	bool
+
+endif
diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/Kconfig.name b/src/mainboard/lenovo/sklkbl_thinkpad/Kconfig.name
new file mode 100644
index 0000000000..abc273f387
--- /dev/null
+++ b/src/mainboard/lenovo/sklkbl_thinkpad/Kconfig.name
@@ -0,0 +1,7 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
+config BOARD_LENOVO_T480
+	bool "ThinkPad T480"
+
+config BOARD_LENOVO_T480S
+	bool "ThinkPad T480s"
diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/Makefile.mk b/src/mainboard/lenovo/sklkbl_thinkpad/Makefile.mk
new file mode 100644
index 0000000000..bf88dd3cd7
--- /dev/null
+++ b/src/mainboard/lenovo/sklkbl_thinkpad/Makefile.mk
@@ -0,0 +1,16 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
+bootblock-y += bootblock.c
+
+romstage-y += variants/$(VARIANT_DIR)/memory_init_params.c
+
+ramstage-$(CONFIG_DRIVERS_OPTION_CFR) += cfr.c
+ramstage-$(CONFIG_VARIANT_HAS_DGPU) += dgpu.c
+ramstage-y += variants/$(VARIANT_DIR)/gpio.c
+ramstage-y += variants/$(VARIANT_DIR)/hda_verb.c
+ramstage-y += ramstage.c
+ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += variants/$(VARIANT_DIR)/gma-mainboard.ads
+
+subdirs-y += variants/$(VARIANT_DIR)
+
+CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/include
diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/acpi/ec.asl b/src/mainboard/lenovo/sklkbl_thinkpad/acpi/ec.asl
new file mode 100644
index 0000000000..3a949a2fca
--- /dev/null
+++ b/src/mainboard/lenovo/sklkbl_thinkpad/acpi/ec.asl
@@ -0,0 +1,12 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#define BRIGHTNESS_UP \_SB.PCI0.GFX0.INCB
+#define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.DECB
+#define THINKPAD_EC_GPE 22
+
+Name(\TCRT, 100)
+Name(\TPSV, 90)
+Name(\FLVL, 0)
+
+#include <ec/lenovo/h8/acpi/ec.asl>
+#include <ec/lenovo/h8/acpi/thinkpad_bat_thresholds_b0.asl>
diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/acpi/superio.asl b/src/mainboard/lenovo/sklkbl_thinkpad/acpi/superio.asl
new file mode 100644
index 0000000000..55b1db5b11
--- /dev/null
+++ b/src/mainboard/lenovo/sklkbl_thinkpad/acpi/superio.asl
@@ -0,0 +1,3 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <drivers/pc80/pc/ps2_controller.asl>
diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/board_info.txt b/src/mainboard/lenovo/sklkbl_thinkpad/board_info.txt
new file mode 100644
index 0000000000..07ab6a3cd0
--- /dev/null
+++ b/src/mainboard/lenovo/sklkbl_thinkpad/board_info.txt
@@ -0,0 +1,6 @@
+Category: laptop
+ROM package: SOIC-8
+ROM protocol: SPI
+ROM socketed: n
+Flashrom support: y
+Release year: 2016
diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/bootblock.c b/src/mainboard/lenovo/sklkbl_thinkpad/bootblock.c
new file mode 100644
index 0000000000..e1fdf18add
--- /dev/null
+++ b/src/mainboard/lenovo/sklkbl_thinkpad/bootblock.c
@@ -0,0 +1,9 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <bootblock_common.h>
+#include <ec/lenovo/mec1653/mec1653.h>
+
+void bootblock_mainboard_early_init(void)
+{
+	bootblock_ec_init();
+}
diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/cfr.c b/src/mainboard/lenovo/sklkbl_thinkpad/cfr.c
new file mode 100644
index 0000000000..45f344b939
--- /dev/null
+++ b/src/mainboard/lenovo/sklkbl_thinkpad/cfr.c
@@ -0,0 +1,82 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <boot/coreboot_tables.h>
+#include <drivers/option/cfr_frontend.h>
+#include <ec/lenovo/h8/cfr.h>
+#include <ec/lenovo/pmh7/cfr.h>
+#include <intelblocks/cfr.h>
+#include <soc/cfr.h>
+#include <static.h>
+
+/* Hide the dGPU CFR entry if dGPU not present */
+static void update_dgpu(const struct sm_object *obj, struct sm_object *new)
+{
+	struct device *dgpu = DEV_PTR(dgpu);
+	if (!dgpu || !dgpu->enabled) {
+		new->sm_bool.flags = CFR_OPTFLAG_SUPPRESS;
+	}
+}
+
+/* dGPU */
+static const struct sm_object dgpu = SM_DECLARE_ENUM({
+	.opt_name	= "dgpu_enable",
+	.ui_name	= "dGPU",
+	.ui_helptext	= "Enable or disable the dGPU",
+	.default_value	= 0,
+	.values		= (const struct sm_enum_value[]) {
+				{ "Disabled",	0	},
+				{ "Enabled",	1	},
+				SM_ENUM_VALUE_END	},
+}, WITH_CALLBACK(update_dgpu));
+
+static struct sm_obj_form system = {
+	.ui_name = "System",
+	.obj_list = (const struct sm_object *[]) {
+		&dgpu,
+		&hyper_threading,
+		&igd_dvmt,
+		&igd_aperture,
+		&legacy_8254_timer,
+		&me_state,
+		&me_state_counter,
+		&pciexp_aspm,
+		&pciexp_clk_pm,
+		&pciexp_l1ss,
+		&pciexp_speed,
+		&s0ix_enable,
+		&vtd,
+		NULL
+	},
+};
+
+static struct sm_obj_form ec = {
+	.ui_name = "Embedded Controller",
+	.obj_list = (const struct sm_object *[]) {
+		&bluetooth,
+		&backlight,
+		&uwb,
+		&usb_always_on,
+		&volume,
+		&wlan,
+		&wwan,
+		&pm_beeps,
+		&battery_beep,
+		&fn_ctrl_swap,
+		&sticky_fn,
+		&f1_to_f12_as_primary,
+		&touchpad,
+		&trackpoint,
+		NULL
+	},
+};
+
+static struct sm_obj_form *sm_root[] = {
+	&ec,
+	&system,
+	NULL
+};
+
+void mb_cfr_setup_menu(struct lb_cfr *cfr_root)
+{
+	cfr_write_setup_menu(cfr_root, sm_root);
+}
diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/devicetree.cb b/src/mainboard/lenovo/sklkbl_thinkpad/devicetree.cb
new file mode 100644
index 0000000000..5ec7750025
--- /dev/null
+++ b/src/mainboard/lenovo/sklkbl_thinkpad/devicetree.cb
@@ -0,0 +1,78 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
+chip soc/intel/skylake
+
+        # Power
+        register "PmConfigSlpS3MinAssert" = "2"         # 50ms
+        register "PmConfigSlpS4MinAssert" = "1"         # 1s
+        register "PmConfigSlpSusMinAssert" = "3"        # 500ms
+        register "PmConfigSlpAMinAssert" = "3"          # 2s
+
+	device domain 0 on
+		subsystemid 0x17aa 0x225d inherit
+		device ref igpu on
+			register "gfx" = "GMA_STATIC_DISPLAYS(0)"
+			register "panel_cfg" = "{
+				.up_delay_ms		= 200,
+				.down_delay_ms		=  50,
+				.cycle_delay_ms		= 600,
+				.backlight_on_delay_ms	=   1,
+				.backlight_off_delay_ms	= 200,
+				.backlight_pwm_hz	= 200,
+			}"
+		end
+		device ref sa_thermal on end
+		device ref thermal on end
+		device ref south_xhci on end
+		device ref sata on
+			register "SataPortsEnable[2]" = "1"
+			register "SataPortsDevSlp[2]" = "1"
+		end
+		device ref lpc_espi on
+			register "serirq_mode" = "SERIRQ_CONTINUOUS"
+
+			register "gen1_dec" = "0x007c1601"
+			register "gen2_dec" = "0x000c15e1"
+			register "lpc_ioe"  = "LPC_IOE_EC_4E_4F |
+					       LPC_IOE_EC_62_66 |
+					       LPC_IOE_KBC_60_64"
+
+			chip ec/lenovo/pmh7
+				register "backlight_enable" = "true"
+				register "dock_event_enable" = "true"
+				device pnp ff.1 on end # dummy
+			end
+
+			chip ec/lenovo/h8
+				register "beepmask0" = "0x00"
+				register "beepmask1" = "0x86"
+				register "config0" = "0xa6"
+				register "config1" = "0x0d"
+				register "config2" = "0xa8"
+				register "config3" = "0xc4"
+				register "has_keyboard_backlight" = "1"
+				register "event2_enable" = "0xff"
+				register "event3_enable" = "0xff"
+				register "event4_enable" = "0xd0"
+				register "event5_enable" = "0x3c"
+				register "event7_enable" = "0x01"
+				register "event8_enable" = "0x7b"
+				register "event9_enable" = "0xff"
+				register "eventc_enable" = "0xff"
+				register "eventd_enable" = "0xff"
+				register "evente_enable" = "0x9d"
+				device pnp ff.2 on # dummy
+					io 0x60 = 0x62
+					io 0x62 = 0x66
+					io 0x64 = 0x1600
+					io 0x66 = 0x1604
+				end
+			end
+
+			chip drivers/pc80/tpm
+				device pnp 0c31.0 on end
+			end
+		end
+		device ref hda on end
+	end
+end
diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/dgpu.c b/src/mainboard/lenovo/sklkbl_thinkpad/dgpu.c
new file mode 100644
index 0000000000..eda21a45d7
--- /dev/null
+++ b/src/mainboard/lenovo/sklkbl_thinkpad/dgpu.c
@@ -0,0 +1,66 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <acpi/acpigen.h>
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci_rom.h>
+#include <option.h>
+#include <mainboard/lenovo/sklkbl_thinkpad/variant.h>
+#include <soc/ramstage.h>
+#include <static.h>
+#include <variant/dgpu.h>
+
+void ssdt_add_dgpu(const struct device *dev)
+{
+	struct rom_header *rom;
+	struct device *dgpu = DEV_PTR(dgpu);
+
+	/* Add entry for dGPU if present/enabled */
+	if (!dgpu || !dgpu->enabled)
+		return;
+
+	/* ROM should be already loaded? */
+	rom = dgpu->pci_vga_option_rom;
+	if (!rom) {
+		printk(BIOS_DEBUG, "dGPU oprom not loaded - probing\n");
+		rom = pci_rom_probe(dgpu);
+		if (!rom || !pci_rom_load(dgpu, rom))
+			return;
+	}
+
+	acpigen_write_scope("\\_SB.PCI0.RP01.PEGP");
+	acpigen_write_rom((void *)rom, rom->size * 512);
+	acpigen_pop_len();
+}
+
+void dgpu_detect(void)
+{
+	static const char * const dgfx_vram_id_str[] = { "1GB", "2GB", "4GB", "N/A" };
+	struct device *dgpu = DEV_PTR(dgpu);
+
+	int dgfx_vram_id;
+
+	// Detect and enable dGPU
+	if (gpio_get(GPIO_DISCRETE_PRESENCE) == 0) { // active low
+		dgfx_vram_id = gpio_get(GPIO_DGFX_VRAM_ID0) | gpio_get(GPIO_DGFX_VRAM_ID1) << 1;
+		printk(BIOS_DEBUG, "Discrete GPU present with %s VRAM\n", dgfx_vram_id_str[dgfx_vram_id]);
+
+		// NOTE: i pulled this GPU enable sequence from thin air
+		// it sometimes works but is buggy and the GPU disappears in some cases so disabling it by default.
+		// also unrelated to this enable sequence the nouveau driver only works on 6.8-6.9 kernels
+		if (get_uint_option("dgpu_enable", 0)) {
+			printk(BIOS_DEBUG, "Enabling discrete GPU\n");
+			gpio_set(GPIO_1R8VIDEO_AON_ON, 1);	// Enable GPU power rail
+			while (!gpio_get(GPIO_DGFX_PWRGD))	// Wait for power good signal from GPU
+				;
+			gpio_set(GPIO_GPU_RST, 1);		// Release GPU from reset
+		} else {
+			printk(BIOS_DEBUG, "Discrete GPU will remain disabled\n");
+			dgpu->enabled = 0;
+		}
+
+	} else {
+		printk(BIOS_DEBUG, "Discrete GPU not present\n");
+		dgpu->enabled = 0;
+	}
+}
diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/dsdt.asl b/src/mainboard/lenovo/sklkbl_thinkpad/dsdt.asl
new file mode 100644
index 0000000000..aa4d4de2a6
--- /dev/null
+++ b/src/mainboard/lenovo/sklkbl_thinkpad/dsdt.asl
@@ -0,0 +1,33 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <acpi/acpi.h>
+DefinitionBlock(
+	"dsdt.aml",
+	"DSDT",
+	ACPI_DSDT_REV_2,
+	OEM_ID,
+	ACPI_TABLE_CREATOR,
+	0x20110725
+)
+{
+	#include <acpi/dsdt_top.asl>
+	#include <soc/intel/common/block/acpi/acpi/globalnvs.asl>
+	#include <cpu/intel/common/acpi/cpu.asl>
+
+	Device (\_SB.PCI0)
+	{
+		#include <soc/intel/skylake/acpi/systemagent.asl>
+		#include <soc/intel/skylake/acpi/pch.asl>
+		#include <drivers/intel/gma/acpi/default_brightness_levels.asl>
+	}
+
+	Scope (\_SB.PCI0.RP01)
+	{
+		Device (PEGP)
+		{
+			Name (_ADR, Zero)
+		}
+	}
+
+	#include <southbridge/intel/common/acpi/sleepstates.asl>
+}
diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/ramstage.c b/src/mainboard/lenovo/sklkbl_thinkpad/ramstage.c
new file mode 100644
index 0000000000..db1b18ac17
--- /dev/null
+++ b/src/mainboard/lenovo/sklkbl_thinkpad/ramstage.c
@@ -0,0 +1,23 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <soc/ramstage.h>
+#include "variant.h"
+
+void mainboard_silicon_init_params(FSP_SIL_UPD *params)
+{
+	// Setup GPIOs
+	variant_config_gpios();
+}
+
+
+static void mainboard_enable(struct device *dev)
+{
+	if (CONFIG(VARIANT_HAS_DGPU)) {
+		dgpu_detect();
+		dev->ops->acpi_fill_ssdt = ssdt_add_dgpu;
+	}
+}
+
+struct chip_operations mainboard_ops = {
+	.enable_dev = mainboard_enable,
+};
diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variant.h b/src/mainboard/lenovo/sklkbl_thinkpad/variant.h
new file mode 100644
index 0000000000..66fdc0fa82
--- /dev/null
+++ b/src/mainboard/lenovo/sklkbl_thinkpad/variant.h
@@ -0,0 +1,12 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef _SKLKBL_THINKPAD_VARIANT_H_
+#define _SKLKBL_THINKPAD_VARIANT_H_
+
+void variant_config_gpios(void);
+
+void ssdt_add_dgpu(const struct device *dev);
+
+void dgpu_detect(void);
+
+#endif
diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480/data.vbt b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480/data.vbt
new file mode 100644
index 0000000000000000000000000000000000000000..4db4202961d0be67b75f52b28f2111d5655595c3
GIT binary patch
literal 4106
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zDF)LeX(GlTYoZ2xkUp4bc(Fbi;|s>bV0gipVB&+pHzmFpc`=IXxii}qiqH*)7}PU+
z?woV)x!<09?wNbfhQa6n_IK}3M!Gw&OgS)sY2Q$LJ4F+z{-JneATkt9refXr6+8sr
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zTqQzcH(berra`9K(R~0OJ_eeA<Ovbd&vdN3&y}qtJ`q3y6wpP2V}*{Dbi8b357>=>
z&R-)LYP^U3@%6h}+0)7m-mEOhOM92<j^WbYrTU_kNXz~GCDNT`I|IC3AsFzURKM6k
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zp|Em=T_#B53Y|R}mtw!K3mUyWRhytxx_wi^(}HurDkx@L%OlKIA%rq@7%bE{p{Wl~
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z3yTO|pc0N&G3cozl21Q6c)l0vjm~0uFL)%2_T5RYR1$~dO~u)4px!jFycZNnchPVA
z!0+Vc_afL{m>rv2PY8{Cma`W{yG~JNJu?;L!#fSLmwRW{8R@gD7Z5~{xvZGpN)U`j
z^I~=;XVmtVzgSv@Na@HC?lC8A1l2+CU<IqV7J%6_t~L}S#%I}a5R3FZk`D#n4m*-O
z$?u%iuC_w$3p=)&nXQX^AwrdnK*hRu`Mqc`AzOgztfsBxvm77j5G7KQo#~<Ufx}jQ
z?|~8PU!d?s-JLd{0Ph}c6J*Zsxd^=dPINEGPS4+NOQoUG&E#4_TUNoTPI5CrmHR%r
VymGKbcpH8Yo8|ycF3<xZ{s}94r0@U$

literal 0
HcmV?d00001

diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480/gma-mainboard.ads b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480/gma-mainboard.ads
new file mode 100644
index 0000000000..fcfbd75a92
--- /dev/null
+++ b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480/gma-mainboard.ads
@@ -0,0 +1,19 @@
+-- SPDX-License-Identifier: GPL-2.0-or-later
+
+with HW.GFX.GMA;
+with HW.GFX.GMA.Display_Probing;
+
+use HW.GFX.GMA;
+use HW.GFX.GMA.Display_Probing;
+
+private package GMA.Mainboard is
+
+   ports : constant Port_List :=
+     (eDP,
+      DP1,
+      DP2,
+      HDMI1,
+      HDMI2,
+      others => Disabled);
+
+end GMA.Mainboard;
diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480/gpio.c b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480/gpio.c
new file mode 100644
index 0000000000..f337843fd9
--- /dev/null
+++ b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480/gpio.c
@@ -0,0 +1,203 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <soc/gpio.h>
+#include "../../variant.h"
+
+/* FIXME: There are multiple GPIOs here that should be locked to prevent "TPM GPIO fail" style
+ * attacks. Unfortunately SKL/KBL GPIO locking *does not* work currently. */
+
+static const struct pad_config gpio_table[] = {
+
+	/* ------- GPIO Community 0 ------- */
+
+	/* ------- GPIO Group GPP_A ------- */
+	PAD_CFG_NF(GPP_A0, NONE, DEEP, NF1),				/* -KBRC */
+	PAD_CFG_NF(GPP_A1, NATIVE, DEEP, NF1),				/* LPC_AD0 */
+	PAD_CFG_NF(GPP_A2, NATIVE, DEEP, NF1),				/* LPC_AD1 */
+	PAD_CFG_NF(GPP_A3, NATIVE, DEEP, NF1),				/* LPC_AD2 */
+	PAD_CFG_NF(GPP_A4, NATIVE, DEEP, NF1),				/* LPC_AD3 */
+	PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1),				/* -LPC_FRAME */
+	PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1),				/* IRQSER */
+	PAD_CFG_NF(GPP_A7, NONE, DEEP, NF1),				/* -TPM_IRQ */
+	PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1),				/* -CLKRUN */
+	PAD_CFG_NF(GPP_A9, NATIVE, DEEP, NF1),				/* LPCCLK_EC_24M */
+	PAD_CFG_NF(GPP_A10, NATIVE, DEEP, NF1),				/* LPCCLK_DEBUG_24M */
+	PAD_NC(GPP_A11, NONE),
+	PAD_NC(GPP_A12, NONE),
+	PAD_CFG_NF(GPP_A13, NATIVE, DEEP, NF1),				/* -SUSWARN */
+	PAD_CFG_NF(GPP_A14, NATIVE, DEEP, NF1),				/* -SUS_STAT */
+	PAD_CFG_NF(GPP_A15, NATIVE, DEEP, NF1),				/* -SUSWARN */
+	PAD_NC(GPP_A16, NONE),
+	PAD_NC(GPP_A17, NONE),
+	PAD_NC(GPP_A18, NONE),
+	PAD_NC(GPP_A19, NONE),
+	PAD_NC(GPP_A20, NONE),
+	PAD_NC(GPP_A21, NONE),
+	PAD_NC(GPP_A22, NONE),
+	PAD_NC(GPP_A23, NONE),
+
+	/* ------- GPIO Group GPP_B ------- */
+	PAD_NC(GPP_B0, NONE),
+	PAD_NC(GPP_B1, NONE),
+	PAD_NC(GPP_B2, NONE),
+	PAD_NC(GPP_B3, NONE),
+	PAD_CFG_GPI_SCI(GPP_B4, NONE, DEEP, EDGE_SINGLE, INVERT),	/* -TBT_PLUG_EVENT */
+	PAD_CFG_NF(GPP_B5, NONE, DEEP, NF1),				/* -CLKREQ_PCIE0 */
+	PAD_CFG_NF(GPP_B6, NONE, DEEP, NF1),				/* -CLKREQ_PCIE4 */
+	PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1),				/* -CLKREQ_PCIE5 */
+	PAD_CFG_NF(GPP_B8, NONE, DEEP, NF1),				/* -CLKREQ_PCIE6 */
+	PAD_CFG_NF(GPP_B9, NONE, DEEP, NF1),				/* -CLKREQ_PCIE8 */
+	PAD_CFG_NF(GPP_B10, NONE, DEEP, NF1),				/* -CLKREQ_PCIE10 */
+	PAD_NC(GPP_B11, NONE),
+	PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1),				/* -PCH_SLP_S0 */
+	PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1),				/* -PLTRST */
+	PAD_CFG_NF(GPP_B14, NATIVE, DEEP, NF1),				/* PCH_SPKR */
+	PAD_CFG_GPO(GPP_B15, 1, DEEP),					/* NFC_DLREQ */
+	PAD_NC(GPP_B16, NONE),
+	PAD_NC(GPP_B17, NONE),
+	PAD_NC(GPP_B18, NONE),
+	PAD_NC(GPP_B19, NONE),
+	PAD_NC(GPP_B20, NONE),
+	PAD_NC(GPP_B21, NONE),
+	PAD_NC(GPP_B22, NONE),
+	PAD_NC(GPP_B23, NONE),
+
+	/* ------- GPIO Community 1 ------- */
+
+	/* ------- GPIO Group GPP_C ------- */
+	PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1),				/* SMB_CLK */
+	PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1),				/* SMB_DATA */
+	PAD_NC(GPP_C2, NONE),
+	PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1),				/* SML0_CLK */
+	PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1),				/* SML0_DATA */
+	PAD_NC(GPP_C5, NONE),
+	PAD_CFG_NF(GPP_C6, NONE, DEEP, NF1),				/* EC_SCL2 */
+	PAD_CFG_NF(GPP_C7, NONE, DEEP, NF1),				/* EC_SDA2 */
+	PAD_NC(GPP_C8, NONE),
+	PAD_NC(GPP_C9, NONE),
+	PAD_NC(GPP_C10, NONE),
+	PAD_NC(GPP_C11, NONE),
+	PAD_NC(GPP_C12, NONE),
+	PAD_NC(GPP_C13, NONE),
+	PAD_NC(GPP_C14, NONE),
+	PAD_NC(GPP_C15, NONE),
+	PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1),				/* I2C0_DATA */
+	PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1),				/* I2C0_CLK */
+	PAD_NC(GPP_C18, NONE),
+	PAD_NC(GPP_C19, NONE),
+	PAD_CFG_GPO(GPP_C20, 0, DEEP),					/* EPRIVACY_ON */
+	PAD_CFG_GPO(GPP_C21, 0, DEEP),					/* TBT_FORCE_PWR */
+	PAD_CFG_GPI_SCI(GPP_C22, NONE, DEEP, EDGE_SINGLE, INVERT),	/* -EC_SCI */
+	PAD_CFG_GPI_SCI(GPP_C23, NONE, DEEP, EDGE_SINGLE, INVERT),	/* -EC_WAKE */
+
+	/* ------- GPIO Group GPP_D ------- */
+	PAD_NC(GPP_D0, NONE),
+	PAD_NC(GPP_D1, NONE),
+	PAD_NC(GPP_D2, NONE),
+	PAD_NC(GPP_D3, NONE),
+	PAD_NC(GPP_D4, NONE),
+	PAD_NC(GPP_D5, NONE),
+	PAD_NC(GPP_D6, NONE),
+	PAD_NC(GPP_D7, NONE),
+	PAD_NC(GPP_D8, NONE),
+	PAD_CFG_GPI_TRIG_OWN(GPP_D9, UP_20K, DEEP, OFF, ACPI),		/* -DISCRETE_PRESENCE */
+	PAD_NC(GPP_D10, NONE),
+	PAD_CFG_GPI_TRIG_OWN(GPP_D11, UP_20K, DEEP, OFF, ACPI),		/* DGFX_VRAM_ID0 */
+	PAD_CFG_GPI_TRIG_OWN(GPP_D12, UP_20K, DEEP, OFF, ACPI),		/* DGFX_VRAM_ID1 */
+	PAD_NC(GPP_D13, NONE),
+	PAD_NC(GPP_D14, NONE),
+	PAD_NC(GPP_D15, NONE),
+	PAD_NC(GPP_D16, NONE),
+	PAD_CFG_GPO(GPP_D17, 0, DEEP),					/* DDI_PRIORITY1 */
+	PAD_NC(GPP_D18, NONE),
+	PAD_NC(GPP_D19, NONE),
+	PAD_NC(GPP_D20, NONE),
+	PAD_NC(GPP_D21, NONE),
+	PAD_CFG_GPI_TRIG_OWN(GPP_D22, UP_20K, DEEP, OFF, ACPI),		/* -NFC_DTCT */
+	PAD_NC(GPP_D23, NONE),
+
+	/* ------- GPIO Group GPP_E ------- */
+	PAD_NC(GPP_E0, NONE),
+	PAD_CFG_NF(GPP_E1, NONE, DEEP, NF1),				/* -WWAN_SATA_DTCT (always HIGH) */
+	PAD_CFG_NF(GPP_E2, NONE, DEEP, NF1),				/* -PE_DTCT */
+	PAD_CFG_GPI_TRIG_OWN(GPP_E3, NONE, DEEP, EDGE_SINGLE, ACPI),	/* -TBT_PLUG_EVENT */
+	PAD_CFG_GPO(GPP_E4, 1, DEEP),					/* NFC_ON */
+	PAD_NC(GPP_E5, NONE),
+	PAD_CFG_NF(GPP_E6, NONE, RSMRST, NF1),				/* SATA2_DEVSLP */
+	PAD_NC(GPP_E7, NONE),
+	PAD_NC(GPP_E8, NONE),
+	PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1),				/* -USB_PORT0_OC0 (AON port) */
+	PAD_CFG_NF(GPP_E10, NONE, DEEP, NF1),				/* -USB_PORT1_OC1 (regular port) */
+	PAD_NC(GPP_E11, NONE),
+	PAD_CFG_GPI_APIC_HIGH(GPP_E12, NONE, DEEP),			/* NFC_INT */
+	PAD_CFG_NF(GPP_E13, NONE, DEEP, NF1),				/* DDIP1_HPD */
+	PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1),				/* DDIP2_HPD */
+	PAD_NC(GPP_E15, NONE),
+	PAD_NC(GPP_E16, NONE),
+	PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1),				/* EDP_HPD */
+	PAD_NC(GPP_E18, NONE),
+	PAD_NC(GPP_E19, NONE),
+	PAD_CFG_NF(GPP_E20, NONE, DEEP, NF1),				/* DDIP2_CTRLCLK */
+	PAD_CFG_NF(GPP_E21, NONE, DEEP, NF1),				/* DDIP2_CTRLDATA */
+	PAD_CFG_TERM_GPO(GPP_E22, 0, UP_20K, RSMRST),			/* -GPU_RST */
+	PAD_CFG_TERM_GPO(GPP_E23, 0, UP_20K, RSMRST),			/* 1R8VIDEO_AON_ON */
+
+	/* ------- GPIO Community 2 ------- */
+
+	/* -------- GPIO Group GPD -------- */
+	PAD_CFG_NF(GPD0, NONE, PWROK, NF1),				/* -BATLOW */
+	PAD_CFG_NF(GPD1, NATIVE, PWROK, NF1),				/* AC_PRESENT */
+	PAD_CFG_NF(GPD2, NATIVE, PWROK, NF1),				/* -LANWAKE */
+	PAD_CFG_NF(GPD3, UP_20K, PWROK, NF1),				/* -PWRSW_EC */
+	PAD_CFG_NF(GPD4, NONE, PWROK, NF1),				/* -PCH_SLP_S3 */
+	PAD_CFG_NF(GPD5, NONE, PWROK, NF1),				/* -PCH_SLP_S4 */
+	PAD_CFG_NF(GPD6, NONE, PWROK, NF1),				/* -PCH_SLP_M */
+	PAD_NC(GPD7, NONE),
+	PAD_CFG_NF(GPD8, NONE, PWROK, NF1),				/* SUSCLK_32K */
+	PAD_CFG_NF(GPD9, NONE, PWROK, NF1),				/* -PCH_SLP_WLAN */
+	PAD_CFG_NF(GPD10, NONE, PWROK, NF1),				/* -PCH_SLP_S5 */
+	PAD_CFG_NF(GPD11, NONE, PWROK, NF1),				/* LANPHYPC */
+
+	/* ------- GPIO Community 3 ------- */
+
+	/* ------- GPIO Group GPP_F ------- */
+	PAD_NC(GPP_F0, NONE),
+	PAD_CFG_GPI_TRIG_OWN(GPP_F1, NONE, DEEP, OFF, ACPI),		/* GC6_FB_EN */
+	PAD_CFG_GPO(GPP_F2, 1, DEEP),					/* -GPU_EVENT */
+	PAD_CFG_GPI_TRIG_OWN(GPP_F3, NONE, DEEP, OFF, ACPI),		/* DGFX_PWRGD */
+	PAD_CFG_GPO(GPP_F4, 1, DEEP),					/* -WWAN_RESET */
+	PAD_NC(GPP_F5, NONE),
+	PAD_CFG_GPI_TRIG_OWN(GPP_F6, UP_20K, DEEP, OFF, ACPI),		/* -MIC_HW_EN (R961 to GND) */
+	PAD_CFG_GPI_TRIG_OWN(GPP_F7, UP_20K, DEEP, OFF, ACPI),		/* -INT_MIC_DTCT */
+	PAD_CFG_GPI_TRIG_OWN(GPP_F8, UP_20K, DEEP, OFF, ACPI),		/* WWAN_CFG0 */
+	PAD_CFG_GPI_TRIG_OWN(GPP_F9, UP_20K, DEEP, OFF, ACPI),		/* WWAN_CFG1 */
+	PAD_CFG_GPI_TRIG_OWN(GPP_F10, UP_20K, DEEP, OFF, ACPI),		/* WWAN_CFG2 */
+	PAD_CFG_GPI_TRIG_OWN(GPP_F11, UP_20K, DEEP, OFF, ACPI),		/* WWAN_CFG3 */
+	PAD_CFG_GPI_TRIG_OWN(GPP_F12, UP_20K, DEEP, OFF, ACPI),		/* PLANARID0 */
+	PAD_CFG_GPI_TRIG_OWN(GPP_F13, UP_20K, DEEP, OFF, ACPI),		/* PLANARID1 */
+	PAD_CFG_GPI_TRIG_OWN(GPP_F14, UP_20K, DEEP, OFF, ACPI),		/* PLANARID2 */
+	PAD_CFG_GPI_TRIG_OWN(GPP_F15, UP_20K, DEEP, OFF, ACPI),		/* PLANARID3 */
+	PAD_NC(GPP_F16, NONE),
+	PAD_NC(GPP_F17, NONE),
+	PAD_NC(GPP_F18, NONE),
+	PAD_NC(GPP_F19, NONE),
+	PAD_NC(GPP_F20, NONE),
+	PAD_NC(GPP_F21, NONE),
+	PAD_CFG_GPI_TRIG_OWN(GPP_F22, UP_20K, DEEP, OFF, ACPI),		/* -INTRUDER_PCH */
+	PAD_CFG_GPI_TRIG_OWN(GPP_F23, UP_20K, DEEP, OFF, ACPI),		/* -SC_DTCT */
+
+	/* ------- GPIO Group GPP_G ------- */
+	PAD_NC(GPP_G0, NONE),
+	PAD_NC(GPP_G1, NONE),
+	PAD_NC(GPP_G2, NONE),
+	PAD_NC(GPP_G3, NONE),
+	PAD_CFG_GPO(GPP_G4, 0, DEEP),					/* TBT_RTD3_PWR_EN */
+	PAD_CFG_GPO(GPP_G5, 0, DEEP),					/* TBT_FORCE_USB_PWR */
+	PAD_CFG_GPO(GPP_G6, 0, DEEP),					/* -TBT_PERST */
+	PAD_CFG_GPI_SCI(GPP_G7, NONE, DEEP, LEVEL, INVERT),		/* -TBT_PCIE_WAKE */
+};
+
+void variant_config_gpios(void)
+{
+	gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table));
+}
diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480/hda_verb.c b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480/hda_verb.c
new file mode 100644
index 0000000000..3a951ce0da
--- /dev/null
+++ b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480/hda_verb.c
@@ -0,0 +1,90 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <device/azalia_device.h>
+
+const u32 cim_verb_data[] = {
+	0x10ec0257, // Vendor/Device ID: Realtek ALC257
+	0x17aa225d, // Subsystem ID
+	11,
+	AZALIA_SUBVENDOR(0, 0x17aa225d),
+
+	AZALIA_PIN_CFG(0, 0x12, AZALIA_PIN_DESC(
+		AZALIA_INTEGRATED,
+		AZALIA_INTERNAL,
+		AZALIA_MIC_IN,
+		AZALIA_OTHER_DIGITAL,
+		AZALIA_COLOR_UNKNOWN,
+		AZALIA_NO_JACK_PRESENCE_DETECT,
+		2, 0
+	)),
+	AZALIA_PIN_CFG(0, 0x13, 0x40000000), // does not describe a jack or internal device
+	AZALIA_PIN_CFG(0, 0x14, AZALIA_PIN_DESC(
+		AZALIA_INTEGRATED,
+		AZALIA_INTERNAL,
+		AZALIA_SPEAKER,
+		AZALIA_OTHER_ANALOG,
+		AZALIA_COLOR_UNKNOWN,
+		AZALIA_NO_JACK_PRESENCE_DETECT,
+		1, 0
+	)),
+	AZALIA_PIN_CFG(0, 0x18, AZALIA_PIN_CFG_NC(0)),
+	AZALIA_PIN_CFG(0, 0x19, AZALIA_PIN_DESC(
+		AZALIA_JACK,
+		AZALIA_EXTERNAL_PRIMARY_CHASSIS | AZALIA_RIGHT,
+		AZALIA_MIC_IN,
+		AZALIA_STEREO_MONO_1_8,
+		AZALIA_BLACK,
+		AZALIA_JACK_PRESENCE_DETECT,
+		3, 0
+	)),
+	AZALIA_PIN_CFG(0, 0x1a, AZALIA_PIN_CFG_NC(0)),
+	AZALIA_PIN_CFG(0, 0x1b, AZALIA_PIN_CFG_NC(0)),
+	AZALIA_PIN_CFG(0, 0x1d, 0x40661b45), // does not describe a jack or internal device
+	AZALIA_PIN_CFG(0, 0x1e, AZALIA_PIN_CFG_NC(0)),
+	AZALIA_PIN_CFG(0, 0x21, AZALIA_PIN_DESC(
+		AZALIA_JACK,
+		AZALIA_EXTERNAL_PRIMARY_CHASSIS | AZALIA_RIGHT,
+		AZALIA_HP_OUT,
+		AZALIA_STEREO_MONO_1_8,
+		AZALIA_BLACK,
+		AZALIA_JACK_PRESENCE_DETECT,
+		1, 15
+	)),
+
+	0x8086280b, // Vendor/Device ID: Intel Kabylake HDMI
+	0x80860101, // Subsystem ID
+	4,
+	AZALIA_SUBVENDOR(2, 0x80860101),
+
+	AZALIA_PIN_CFG(2, 0x05, AZALIA_PIN_DESC(
+		AZALIA_JACK,
+		AZALIA_DIGITAL_DISPLAY,
+		AZALIA_DIGITAL_OTHER_OUT,
+		AZALIA_OTHER_DIGITAL,
+		AZALIA_COLOR_UNKNOWN,
+		AZALIA_JACK_PRESENCE_DETECT,
+		1, 0
+	)),
+	AZALIA_PIN_CFG(2, 0x06, AZALIA_PIN_DESC(
+		AZALIA_JACK,
+		AZALIA_DIGITAL_DISPLAY,
+		AZALIA_DIGITAL_OTHER_OUT,
+		AZALIA_OTHER_DIGITAL,
+		AZALIA_COLOR_UNKNOWN,
+		AZALIA_JACK_PRESENCE_DETECT,
+		2, 0
+	)),
+	AZALIA_PIN_CFG(2, 0x07, AZALIA_PIN_DESC(
+		AZALIA_JACK,
+		AZALIA_DIGITAL_DISPLAY,
+		AZALIA_DIGITAL_OTHER_OUT,
+		AZALIA_OTHER_DIGITAL,
+		AZALIA_COLOR_UNKNOWN,
+		AZALIA_JACK_PRESENCE_DETECT,
+		3, 0
+	)),
+};
+
+const u32 pc_beep_verbs[] = {};
+
+AZALIA_ARRAY_SIZES;
diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480/include/variant/dgpu.h b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480/include/variant/dgpu.h
new file mode 100644
index 0000000000..deb0cf4c1e
--- /dev/null
+++ b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480/include/variant/dgpu.h
@@ -0,0 +1,15 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef _VARIANT_DGPU_H_
+#define _VARIANT_DGPU_H_
+
+#define GPIO_GPU_RST			GPP_E22 // active low
+#define GPIO_1R8VIDEO_AON_ON		GPP_E23
+
+#define GPIO_DGFX_PWRGD			GPP_F3
+
+#define GPIO_DISCRETE_PRESENCE		GPP_D9	// active low
+#define GPIO_DGFX_VRAM_ID0		GPP_D11
+#define GPIO_DGFX_VRAM_ID1		GPP_D12
+
+#endif
diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480/memory_init_params.c b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480/memory_init_params.c
new file mode 100644
index 0000000000..5252a402f9
--- /dev/null
+++ b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480/memory_init_params.c
@@ -0,0 +1,20 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <soc/romstage.h>
+#include <spd_bin.h>
+
+void mainboard_memory_init_params(FSPM_UPD *mupd)
+{
+	FSP_M_CONFIG *mem_cfg = &mupd->FspmConfig;
+	mem_cfg->DqPinsInterleaved = true;			/* DDR_DQ in interleave mode */
+	mem_cfg->CaVrefConfig      = 2;				/* VREF_CA to CH_A and VREF_DQ_B to CH_B */
+	mem_cfg->MemorySpdDataLen  = CONFIG_DIMM_SPD_SIZE;
+
+	/* Get SPD for memory slots */
+	struct spd_block blk = { .addr_map = { 0x50, 0x51, } };
+	get_spd_smbus(&blk);
+	dump_spd_info(&blk);
+
+	mem_cfg->MemorySpdPtr00    = (uintptr_t)blk.spd_array[0];
+	mem_cfg->MemorySpdPtr10    = (uintptr_t)blk.spd_array[1];
+}
diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480/overridetree.cb b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480/overridetree.cb
new file mode 100644
index 0000000000..9acb823c10
--- /dev/null
+++ b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480/overridetree.cb
@@ -0,0 +1,93 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
+chip soc/intel/skylake
+	device domain 0 on
+		device ref south_xhci on
+			register "usb2_ports" = "{
+				[0] = USB2_PORT_MID(OC1),		// USB-A
+				[1] = USB2_PORT_MID(OC0),		// USB-A (always on)
+				[2] = USB2_PORT_MID(OC_SKIP),		// JSC-1 (smartcard slot)
+				[3] = USB2_PORT_MID(OC_SKIP),		// USB-C (charging port)
+				[4] = USB2_PORT_MID(OC_SKIP),		// JCAM1 (IR camera)
+				[5] = USB2_PORT_MID(OC_SKIP),		// JWWAN1 (M.2 WWAN USB)
+				[6] = USB2_PORT_MID(OC_SKIP),		// JWLAN1 (M.2 WLAN USB)
+				[7] = USB2_PORT_MID(OC_SKIP),		// JCAM1 (webcam)
+				[8] = USB2_PORT_MID(OC_SKIP),		// JFPR1 (fingerprint reader)
+				[9] = USB2_PORT_MID(OC_SKIP),		// JLCD1 (touch panel)
+			}"
+			register "usb3_ports" = "{
+				[0] = USB3_PORT_DEFAULT(OC1),		// USB-A
+				[1] = USB3_PORT_DEFAULT(OC0),		// USB-A (always on)
+				[2] = USB3_PORT_DEFAULT(OC_SKIP),	// RTS5344S (SD card reader)
+				[3] = USB3_PORT_DEFAULT(OC_SKIP),	// USB-C (charging port)
+			}"
+		end
+
+		# PCIe controller 1 - 1x4
+		#   PCIE 1-4   - RP1  - dGPU - CLKOUT0 - CLKREQ0
+		#
+		# PCIe controller 2 - 2x1+1x2 (lane reversal)
+		#   PCIE 5     - GBE  - GBE  - CLKOUT1 - CLKREQ1 (clobbers RP8)
+		#   PCIE 6     - RP7  - WLAN - CLKOUT2 - CLKREQ2
+		#   PCIE 7-8   - RP5  - WWAN - CLKOUT3 - CLKREQ3
+		#
+		# PCIe controller 3 - 2x2
+		#   PCIE 9-10  - RP9  - TB3  - CLKOUT4 - CLKREQ4
+		#   PCIE 11-12 - RP11 - SSD  - CLKOUT5 - CLKREQ5
+
+		# dGPU - x4
+		device ref pcie_rp1 on
+			register "PcieRpClkReqSupport[0]"		= "1"
+			register "PcieRpClkReqNumber[0]"		= "0"
+			register "PcieRpClkSrcNumber[0]"		= "0"
+			register "PcieRpAdvancedErrorReporting[0]"	= "1"
+			register "PcieRpLtrEnable[0]"			= "1"
+			device generic 0 alias dgpu on end
+		end
+
+		# Ethernet (clobbers RP8)
+		device ref gbe on
+			register "LanClkReqSupported"			= "1"
+			register "LanClkReqNumber"			= "1"
+			register "EnableLanLtr"				= "1"
+			register "EnableLanK1Off"			= "1"
+		end
+
+		# M.2 WLAN - x1
+		device ref pcie_rp7 on
+			register "PcieRpClkReqSupport[6]"		= "1"
+			register "PcieRpClkReqNumber[6]"		= "2"
+			register "PcieRpClkSrcNumber[6]"		= "2"
+			register "PcieRpAdvancedErrorReporting[6]"	= "1"
+			register "PcieRpLtrEnable[6]"			= "1"
+		end
+
+		# M.2 WWAN - x2
+		device ref pcie_rp5 on
+			register "PcieRpClkReqSupport[4]"		= "1"
+			register "PcieRpClkReqNumber[4]"		= "3"
+			register "PcieRpClkSrcNumber[4]"		= "3"
+			register "PcieRpAdvancedErrorReporting[4]"	= "1"
+			register "PcieRpLtrEnable[4]"			= "1"
+		end
+
+		# TB3 (Alpine Ridge LP) - x2
+		device ref pcie_rp9 on
+			register "PcieRpClkReqSupport[8]"		= "1"
+			register "PcieRpClkReqNumber[8]"		= "4"
+			register "PcieRpClkSrcNumber[8]"		= "4"
+			register "PcieRpAdvancedErrorReporting[8]"	= "1"
+			register "PcieRpLtrEnable[8]"			= "1"
+			register "PcieRpHotPlug[8]"			= "1"
+		end
+
+		# M.2 2280 caddy - x2
+		device ref pcie_rp11 on
+			register "PcieRpClkReqSupport[10]"		= "1"
+			register "PcieRpClkReqNumber[10]"		= "5"
+			register "PcieRpClkSrcNumber[10]"		= "5"
+			register "PcieRpAdvancedErrorReporting[10]"	= "1"
+			register "PcieRpLtrEnable[10]"			= "1"
+		end
+	end
+end
diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/Makefile.mk b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/Makefile.mk
new file mode 100644
index 0000000000..a6b399f161
--- /dev/null
+++ b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/Makefile.mk
@@ -0,0 +1,10 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
+# Add files spd_0.bin to spd_20.bin to the cbfs image
+SPD_BINS := $(shell seq 0 20)
+define SPD_template
+cbfs-files-y += spd_$(1).bin
+spd_$(1).bin-file := spd/spd_$(1).bin
+spd_$(1).bin-type := raw
+endef
+$(foreach n,$(SPD_BINS),$(eval $(call SPD_template,$(n))))
diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/data.vbt b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/data.vbt
new file mode 100644
index 0000000000000000000000000000000000000000..47732e37d5b2bad4e674fd10eafa605d26f97840
GIT binary patch
literal 4106
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zMT)`nNScT-%9*GEA8a2?G`v`!jPV6yVlcd5OnC6Y;F}U&jJz1db9VRID@E)DLk#NN
z&9^i2&Hiq_`R2ZF8ipf7IM{nI5$^585@kULrrx0OPKv~ngNI__q41$dA{p()ui+v1
zw(9rm09lUPAP4nOTm0CRnF|aw5^SQSH<G}<u_Gfnvn6IuK0h@!j;UxI!$*&rIdkIh
zl$piB;eBDWa1|CgK9bAg{^O%Z%!ziiz{neeJDb~fBI?1GV5p^44?a$ETl=n1d+;%Z
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zmP&-g0$k02szSQj(Y*j}YYtQnDH0;2ui<!ko-28Y){6ilAcrmz951v4RTWQ_ye!or
z4xOJya#Sr7{o)%XFUfJCndM%KM(c^ol_hzlb*1h&uC%Vy%U(P!_qUfwcb4r;SmPQ_
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z#z{?mXvVqrXs_rvUmYR40gNzg(QD6y9E94?4DWO|6eb83LI-smcVC6x1n2reH}rAp
zLM);f=tWDCr``UF5T>!;PYu^H1g>EBP8A}2*fM>s-@nC3pDV|}6+CtfhG(II7`pcw
z`jLfJ!?;*R@Bp=Nw2EPOC7FEs(cugIP_K6tN_$~tvS8nx6iOv|IMrO3&-m*N9ZP#b
znG^~>I|l1cUVSeD9r^k3h0TP}WWD9=MZxY<<azgO1@-W5<NTHW*-d)t{Q4yX9_+?a
zHawLe=uO6@%xqS#?JxafX%#$`BhkIqq>Z3B2yU!k71#YRpThOJtVheMDA50rV#s@U
z+nKbA{O(olYR}icuzQD*-cjBQ9;%!eMDVP>7mWsF@=%>o)wSgq=n%DHNOYwRr4Ao6
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literal 0
HcmV?d00001

diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/gma-mainboard.ads b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/gma-mainboard.ads
new file mode 100644
index 0000000000..fcfbd75a92
--- /dev/null
+++ b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/gma-mainboard.ads
@@ -0,0 +1,19 @@
+-- SPDX-License-Identifier: GPL-2.0-or-later
+
+with HW.GFX.GMA;
+with HW.GFX.GMA.Display_Probing;
+
+use HW.GFX.GMA;
+use HW.GFX.GMA.Display_Probing;
+
+private package GMA.Mainboard is
+
+   ports : constant Port_List :=
+     (eDP,
+      DP1,
+      DP2,
+      HDMI1,
+      HDMI2,
+      others => Disabled);
+
+end GMA.Mainboard;
diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/gpio.c b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/gpio.c
new file mode 100644
index 0000000000..4f1c57390d
--- /dev/null
+++ b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/gpio.c
@@ -0,0 +1,199 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <soc/gpio.h>
+#include "../../variant.h"
+
+static const struct pad_config gpio_table[] = {
+	/* ------- GPIO Community 0 ------- */
+
+	/* ------- GPIO Group GPP_A ------- */
+	PAD_CFG_NF(GPP_A0, NONE, DEEP, NF1),				/* -KBRC */
+	PAD_CFG_NF(GPP_A1, NATIVE, DEEP, NF1),				/* LPC_AD0 */
+	PAD_CFG_NF(GPP_A2, NATIVE, DEEP, NF1),				/* LPC_AD1 */
+	PAD_CFG_NF(GPP_A3, NATIVE, DEEP, NF1),				/* LPC_AD2 */
+	PAD_CFG_NF(GPP_A4, NATIVE, DEEP, NF1),				/* LPC_AD3 */
+	PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1),				/* -LPC_FRAME */
+	PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1),				/* IRQSER */
+	PAD_CFG_NF(GPP_A7, NONE, DEEP, NF1),				/* -TPM_IRQ */
+	PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1),				/* -CLKRUN */
+	PAD_CFG_NF(GPP_A9, DN_20K, DEEP, NF1),				/* LPCCLK_EC_24M */
+	PAD_CFG_NF(GPP_A10, DN_20K, DEEP, NF1),				/* LPCCLK_DEBUG_24M */
+	PAD_NC(GPP_A11, NONE),
+	PAD_NC(GPP_A12, NONE),
+	PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1),				/* -SUSWARN */
+	PAD_CFG_NF(GPP_A14, NONE, DEEP, NF1),				/* -SUS_STAT */
+	PAD_CFG_NF(GPP_A15, UP_20K, DEEP, NF1),				/* -SUSWARN */
+	PAD_NC(GPP_A16, NONE),
+	PAD_NC(GPP_A17, NONE),
+	PAD_NC(GPP_A18, NONE),
+	PAD_NC(GPP_A19, NONE),
+	PAD_NC(GPP_A20, NONE),
+	PAD_NC(GPP_A21, NONE),
+	PAD_NC(GPP_A22, NONE),
+	PAD_NC(GPP_A23, NONE),
+
+	/* ------- GPIO Group GPP_B ------- */
+	PAD_CFG_NF(GPP_B0, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_B1, NONE, DEEP, NF1),
+	PAD_NC(GPP_B2, NONE),
+	PAD_NC(GPP_B3, NONE),
+	PAD_CFG_GPI_SCI(GPP_B4, NONE, DEEP, EDGE_SINGLE, INVERT),	/* -TBT_PLUG_EVENT */
+	PAD_CFG_NF(GPP_B5, NONE, DEEP, NF1),				/* -CLKREQ_PCIE0 (dGPU) */
+	PAD_CFG_NF(GPP_B6, NONE, DEEP, NF1),				/* -CLKREQ_PCIE3 (WWAN) */
+	PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1),				/* -CLKREQ_PCIE4 (GBE) */
+	PAD_CFG_NF(GPP_B8, NONE, DEEP, NF1),				/* -CLKREQ_PCIE5 (WLAN) */
+	PAD_CFG_NF(GPP_B9, NONE, DEEP, NF1),				/* -CLKREQ_PCIE6 (TB3) */
+	PAD_CFG_NF(GPP_B10, NONE, DEEP, NF1),				/* -CLKREQ_PCIE8 (SSD) */
+	PAD_NC(GPP_B11, NONE),
+	PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1),				/* -PCH_SLP_S0 */
+	PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1),				/* -PLTRST */
+	PAD_CFG_NF(GPP_B14, NONE, DEEP, NF1),				/* PCH_SPKR */
+	PAD_CFG_GPO(GPP_B15, 0, DEEP),					/* NFC_DLREQ */
+	PAD_NC(GPP_B16, NONE),
+	PAD_NC(GPP_B17, NONE),
+	PAD_NC(GPP_B18, NONE),
+	PAD_NC(GPP_B19, NONE),
+	PAD_NC(GPP_B20, NONE),
+	PAD_NC(GPP_B21, NONE),
+	PAD_NC(GPP_B22, NONE),
+	PAD_NC(GPP_B23, NONE),
+
+	/* ------- GPIO Community 1 ------- */
+
+	/* ------- GPIO Group GPP_C ------- */
+	PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1),				/* SMB_CLK */
+	PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1),				/* SMB_DATA */
+	PAD_CFG_GPO(GPP_C2, 1, DEEP),
+	PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1),				/* SML0_CLK */
+	PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1),				/* SML0_DATA */
+	PAD_NC(GPP_C5, NONE),
+	PAD_CFG_NF(GPP_C6, NONE, DEEP, NF1),				/* EC_SCL2 */
+	PAD_CFG_NF(GPP_C7, NONE, DEEP, NF1),				/* EC_SDA2 */
+	PAD_NC(GPP_C8, NONE),
+	PAD_NC(GPP_C9, NONE),
+	PAD_NC(GPP_C10, NONE),
+	PAD_NC(GPP_C11, NONE),
+	PAD_NC(GPP_C12, NONE),
+	PAD_NC(GPP_C13, NONE),
+	PAD_NC(GPP_C14, NONE),
+	PAD_NC(GPP_C15, NONE),
+	PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1),				/* I2C0_DATA */
+	PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1),				/* I2C0_CLK */
+	PAD_NC(GPP_C18, NONE),
+	PAD_NC(GPP_C19, NONE),
+	PAD_CFG_GPO(GPP_C20, 0, DEEP),					/* EPRIVACY_ON */
+	PAD_CFG_GPO(GPP_C21, 0, DEEP),					/* TBT_FORCE_PWR */
+	PAD_CFG_GPI_SCI(GPP_C22, NONE, DEEP, EDGE_SINGLE, INVERT),	/* -EC_SCI */
+	PAD_CFG_GPI_SCI(GPP_C23, NONE, DEEP, EDGE_SINGLE, INVERT),	/* -EC_WAKE */
+
+	/* ------- GPIO Group GPP_D ------- */
+	PAD_NC(GPP_D0, NONE),
+	PAD_NC(GPP_D1, NONE),
+	PAD_NC(GPP_D2, NONE),
+	PAD_NC(GPP_D3, NONE),
+	PAD_NC(GPP_D4, NONE),
+	PAD_NC(GPP_D5, NONE),
+	PAD_NC(GPP_D6, NONE),
+	PAD_NC(GPP_D7, NONE),
+	PAD_NC(GPP_D8, NONE),
+	PAD_CFG_GPI_TRIG_OWN(GPP_D9, UP_20K, DEEP, OFF, ACPI),		/* -DISCRETE_PRESENCE */
+	PAD_NC(GPP_D10, NONE),
+	PAD_CFG_GPI_TRIG_OWN(GPP_D11, UP_20K, DEEP, OFF, ACPI),		/* DGFX_VRAM_ID0 */
+	PAD_CFG_GPI_TRIG_OWN(GPP_D12, UP_20K, DEEP, OFF, ACPI),		/* DGFX_VRAM_ID1 */
+	PAD_NC(GPP_D13, NONE),
+	PAD_NC(GPP_D14, NONE),
+	PAD_NC(GPP_D15, NONE),
+	PAD_NC(GPP_D16, NONE),
+	PAD_CFG_GPO(GPP_D17, 0, DEEP),					/* DDI_PRIORITY */
+	PAD_NC(GPP_D18, NONE),
+	PAD_NC(GPP_D19, NONE),
+	PAD_NC(GPP_D20, NONE),
+	PAD_NC(GPP_D21, NONE),
+	PAD_CFG_GPI_TRIG_OWN(GPP_D22, UP_20K, DEEP, OFF, ACPI),		/* -NFC_DTCT */
+	PAD_NC(GPP_D23, NONE),
+
+	/* ------- GPIO Group GPP_E ------- */
+	PAD_CFG_GPO(GPP_E0, 1, DEEP),					/* BDC_ON */
+	PAD_NC(GPP_E1, NONE),
+	PAD_CFG_NF(GPP_E2, NONE, DEEP, NF1),				/* -SATA2_DTCT */
+	PAD_CFG_GPI_TRIG_OWN(GPP_E3, NONE, DEEP, EDGE_SINGLE, ACPI),	/* -TBT_PLUG_EVENT */
+	PAD_CFG_GPO(GPP_E4, 1, DEEP),					/* NFC_ON */
+	PAD_NC(GPP_E5, NONE),
+	PAD_CFG_NF(GPP_E6, NONE, RSMRST, NF1),				/* SATA2_DEVSLP */
+	PAD_NC(GPP_E7, NONE),
+	PAD_NC(GPP_E8, NONE),
+	PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1),				/* -USB_PORT0_OC0 */
+	PAD_CFG_NF(GPP_E10, NONE, DEEP, NF1),				/* -USB_PORT1_OC1 */
+	PAD_NC(GPP_E11, NONE),
+	PAD_CFG_GPI_APIC_HIGH(GPP_E12, NONE, DEEP),			/* NFC_INT */
+	PAD_CFG_NF(GPP_E13, NONE, DEEP, NF1),				/* DDIP1_HPD */
+	PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1),				/* DDIP2_HPD */
+	PAD_NC(GPP_E15, NONE),
+	PAD_NC(GPP_E16, NONE),
+	PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1),				/* EDP_HPD */
+	PAD_NC(GPP_E18, NONE),
+	PAD_CFG_GPO(GPP_E19, 0, DEEP),
+	PAD_CFG_NF(GPP_E20, NONE, DEEP, NF1),				/* DDIP2_CTRLCLK */
+	PAD_CFG_NF(GPP_E21, NONE, DEEP, NF1),				/* DDIP2_CTRLDATA */
+	PAD_CFG_TERM_GPO(GPP_E22, 0, UP_20K, RSMRST),			/* -GPU_RST */
+	PAD_CFG_TERM_GPO(GPP_E23, 0, UP_20K, RSMRST),			/* 1R8VIDEO_AON_ON */
+
+	/* ------- GPIO Community 2 ------- */
+
+	/* -------- GPIO Group GPD -------- */
+	PAD_CFG_NF(GPD0, NONE, PWROK, NF1),				/* -BATLOW */
+	PAD_CFG_NF(GPD1, NATIVE, PWROK, NF1),				/* AC_PRESENT */
+	PAD_CFG_NF(GPD2, NATIVE, PWROK, NF1),				/* -LANWAKE */
+	PAD_CFG_NF(GPD3, UP_20K, PWROK, NF1),				/* -PWRSW_EC */
+	PAD_CFG_NF(GPD4, NONE, PWROK, NF1),				/* -PCH_SLP_S3 */
+	PAD_CFG_NF(GPD5, NONE, PWROK, NF1),				/* -PCH_SLP_S4 */
+	PAD_CFG_NF(GPD6, NONE, PWROK, NF1),				/* -PCH_SLP_M */
+	PAD_NC(GPD7, NONE),
+	PAD_CFG_NF(GPD8, NONE, PWROK, NF1),				/* SUSCLK_32K */
+	PAD_CFG_NF(GPD9, NONE, PWROK, NF1),				/* -PCH_SLP_WLAN */
+	PAD_CFG_NF(GPD10, NONE, PWROK, NF1),				/* -PCH_SLP_S5 */
+	PAD_CFG_NF(GPD11, NONE, PWROK, NF1),				/* LANPHYPC */
+
+	/* ------- GPIO Community 3 ------- */
+
+	/* ------- GPIO Group GPP_F ------- */
+	PAD_CFG_GPO(GPP_F0, 0, DEEP),
+	PAD_CFG_GPI_TRIG_OWN(GPP_F1, NONE, DEEP, OFF, ACPI),		/* GC6_FB_EN */
+	PAD_CFG_GPO(GPP_F2, 1, DEEP),					/* -GPU_EVENT */
+	PAD_CFG_GPI_TRIG_OWN(GPP_F3, NONE, PLTRST, OFF, ACPI),		/* DGFX_PWRGD */
+	PAD_NC(GPP_F4, NONE),						/* -WWAN_RESET */
+	PAD_NC(GPP_F5, NONE),
+	PAD_CFG_GPI_TRIG_OWN(GPP_F6, UP_20K, DEEP, OFF, ACPI),		/* -MIC_HW_EN (R37 to GND) */
+	PAD_CFG_GPI_TRIG_OWN(GPP_F7, UP_20K, DEEP, OFF, ACPI),		/* -INT_MIC_DTCT */
+	PAD_CFG_GPI_TRIG_OWN(GPP_F8, UP_20K, DEEP, OFF, ACPI),		/* WWAN_CFG0 */
+	PAD_CFG_GPI_TRIG_OWN(GPP_F9, UP_20K, DEEP, OFF, ACPI),		/* WWAN_CFG1 */
+	PAD_CFG_GPI_TRIG_OWN(GPP_F10, UP_20K, DEEP, OFF, ACPI),		/* WWAN_CFG2 */
+	PAD_CFG_GPI_TRIG_OWN(GPP_F11, UP_20K, DEEP, OFF, ACPI),		/* WWAN_CFG3 */
+	PAD_CFG_GPI_TRIG_OWN(GPP_F12, UP_20K, DEEP, OFF, ACPI),		/* PLANARID0 */
+	PAD_CFG_GPI_TRIG_OWN(GPP_F13, UP_20K, DEEP, OFF, ACPI),		/* PLANARID1 */
+	PAD_CFG_GPI_TRIG_OWN(GPP_F14, UP_20K, DEEP, OFF, ACPI),		/* PLANARID2 */
+	PAD_CFG_GPI_TRIG_OWN(GPP_F15, UP_20K, DEEP, OFF, ACPI),		/* PLANARID3 */
+	PAD_CFG_GPI_TRIG_OWN(GPP_F16, UP_20K, DEEP, OFF, ACPI),		/* MEMORYID0 */
+	PAD_CFG_GPI_TRIG_OWN(GPP_F17, UP_20K, DEEP, OFF, ACPI),		/* MEMORYID1 */
+	PAD_CFG_GPI_TRIG_OWN(GPP_F18, UP_20K, DEEP, OFF, ACPI),		/* MEMORYID2 */
+	PAD_CFG_GPI_TRIG_OWN(GPP_F19, UP_20K, DEEP, OFF, ACPI),		/* MEMORYID3 */
+	PAD_CFG_GPI_TRIG_OWN(GPP_F20, UP_20K, DEEP, OFF, ACPI),		/* MEMORYID4 */
+	PAD_NC(GPP_F21, NONE),
+	PAD_CFG_GPI_TRIG_OWN(GPP_F22, UP_20K, DEEP, OFF, ACPI),		/* -TAMPER_SW_DTCT */
+	PAD_CFG_GPI_TRIG_OWN(GPP_F23, UP_20K, DEEP, OFF, ACPI),		/* -SC_DTCT */
+
+	/* ------- GPIO Group GPP_G ------- */
+	PAD_NC(GPP_G0, NONE),
+	PAD_NC(GPP_G1, NONE),
+	PAD_NC(GPP_G2, NONE),
+	PAD_NC(GPP_G3, NONE),
+	PAD_CFG_GPO(GPP_G4, 0, DEEP),					/* TBT_RTD3_PWR_EN */
+	PAD_CFG_GPO(GPP_G5, 0, DEEP),					/* TBT_FORCE_USB_PWR */
+	PAD_CFG_GPO(GPP_G6, 0, DEEP),					/* -TBT_PERST */
+	PAD_CFG_GPI_SCI(GPP_G7, NONE, DEEP, LEVEL, INVERT),		/* -TBT_PCIE_WAKE */
+};
+
+void variant_config_gpios(void)
+{
+	gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table));
+}
diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/hda_verb.c b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/hda_verb.c
new file mode 100644
index 0000000000..b1d96c5a76
--- /dev/null
+++ b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/hda_verb.c
@@ -0,0 +1,90 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <device/azalia_device.h>
+
+const u32 cim_verb_data[] = {
+	0x10ec0257, // Vendor/Device ID: Realtek ALC257
+	0x17aa2258, // Subsystem ID
+	11,
+	AZALIA_SUBVENDOR(0, 0x17aa2258),
+
+	AZALIA_PIN_CFG(0, 0x12, AZALIA_PIN_DESC(
+		AZALIA_INTEGRATED,
+		AZALIA_INTERNAL,
+		AZALIA_MIC_IN,
+		AZALIA_OTHER_DIGITAL,
+		AZALIA_COLOR_UNKNOWN,
+		AZALIA_NO_JACK_PRESENCE_DETECT,
+		2, 0
+	)),
+	AZALIA_PIN_CFG(0, 0x13, 0x40000000), // does not describe a jack or internal device
+	AZALIA_PIN_CFG(0, 0x14, AZALIA_PIN_DESC(
+		AZALIA_INTEGRATED,
+		AZALIA_INTERNAL,
+		AZALIA_SPEAKER,
+		AZALIA_OTHER_ANALOG,
+		AZALIA_COLOR_UNKNOWN,
+		AZALIA_NO_JACK_PRESENCE_DETECT,
+		1, 0
+	)),
+	AZALIA_PIN_CFG(0, 0x18, AZALIA_PIN_CFG_NC(0)),
+	AZALIA_PIN_CFG(0, 0x19, AZALIA_PIN_DESC(
+		AZALIA_JACK,
+		AZALIA_EXTERNAL_PRIMARY_CHASSIS | AZALIA_RIGHT,
+		AZALIA_MIC_IN,
+		AZALIA_STEREO_MONO_1_8,
+		AZALIA_BLACK,
+		AZALIA_JACK_PRESENCE_DETECT,
+		3, 0
+	)),
+	AZALIA_PIN_CFG(0, 0x1a, AZALIA_PIN_CFG_NC(0)),
+	AZALIA_PIN_CFG(0, 0x1b, AZALIA_PIN_CFG_NC(0)),
+	AZALIA_PIN_CFG(0, 0x1d, 0x40661b45), // does not describe a jack or internal device
+	AZALIA_PIN_CFG(0, 0x1e, AZALIA_PIN_CFG_NC(0)),
+	AZALIA_PIN_CFG(0, 0x21, AZALIA_PIN_DESC(
+		AZALIA_JACK,
+		AZALIA_EXTERNAL_PRIMARY_CHASSIS | AZALIA_RIGHT,
+		AZALIA_HP_OUT,
+		AZALIA_STEREO_MONO_1_8,
+		AZALIA_BLACK,
+		AZALIA_JACK_PRESENCE_DETECT,
+		1, 15
+	)),
+
+	0x8086280b, // Vendor/Device ID: Intel Kabylake HDMI
+	0x80860101, // Subsystem ID
+	4,
+	AZALIA_SUBVENDOR(2, 0x80860101),
+
+	AZALIA_PIN_CFG(2, 0x05, AZALIA_PIN_DESC(
+		AZALIA_JACK,
+		AZALIA_DIGITAL_DISPLAY,
+		AZALIA_DIGITAL_OTHER_OUT,
+		AZALIA_OTHER_DIGITAL,
+		AZALIA_COLOR_UNKNOWN,
+		AZALIA_JACK_PRESENCE_DETECT,
+		1, 0
+	)),
+	AZALIA_PIN_CFG(2, 0x06, AZALIA_PIN_DESC(
+		AZALIA_JACK,
+		AZALIA_DIGITAL_DISPLAY,
+		AZALIA_DIGITAL_OTHER_OUT,
+		AZALIA_OTHER_DIGITAL,
+		AZALIA_COLOR_UNKNOWN,
+		AZALIA_JACK_PRESENCE_DETECT,
+		1, 0
+	)),
+	AZALIA_PIN_CFG(2, 0x07, AZALIA_PIN_DESC(
+		AZALIA_JACK,
+		AZALIA_DIGITAL_DISPLAY,
+		AZALIA_DIGITAL_OTHER_OUT,
+		AZALIA_OTHER_DIGITAL,
+		AZALIA_COLOR_UNKNOWN,
+		AZALIA_JACK_PRESENCE_DETECT,
+		1, 0
+	)),
+};
+
+const u32 pc_beep_verbs[] = {};
+
+AZALIA_ARRAY_SIZES;
diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/include/variant/dgpu.h b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/include/variant/dgpu.h
new file mode 100644
index 0000000000..deb0cf4c1e
--- /dev/null
+++ b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/include/variant/dgpu.h
@@ -0,0 +1,15 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef _VARIANT_DGPU_H_
+#define _VARIANT_DGPU_H_
+
+#define GPIO_GPU_RST			GPP_E22 // active low
+#define GPIO_1R8VIDEO_AON_ON		GPP_E23
+
+#define GPIO_DGFX_PWRGD			GPP_F3
+
+#define GPIO_DISCRETE_PRESENCE		GPP_D9	// active low
+#define GPIO_DGFX_VRAM_ID0		GPP_D11
+#define GPIO_DGFX_VRAM_ID1		GPP_D12
+
+#endif
diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/memory_init_params.c b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/memory_init_params.c
new file mode 100644
index 0000000000..001e934b3a
--- /dev/null
+++ b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/memory_init_params.c
@@ -0,0 +1,44 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <cbfs.h>
+#include <gpio.h>
+#include <soc/gpio.h>
+#include <soc/romstage.h>
+#include <spd_bin.h>
+#include <stdio.h>
+
+static const struct pad_config memory_id_gpio_table[] = {
+	PAD_CFG_GPI_TRIG_OWN(GPP_F16, UP_20K, DEEP, OFF, ACPI),		/* MEMORYID0 */
+	PAD_CFG_GPI_TRIG_OWN(GPP_F17, UP_20K, DEEP, OFF, ACPI),		/* MEMORYID1 */
+	PAD_CFG_GPI_TRIG_OWN(GPP_F18, UP_20K, DEEP, OFF, ACPI),		/* MEMORYID2 */
+	PAD_CFG_GPI_TRIG_OWN(GPP_F19, UP_20K, DEEP, OFF, ACPI),		/* MEMORYID3 */
+	PAD_CFG_GPI_TRIG_OWN(GPP_F20, UP_20K, DEEP, OFF, ACPI),		/* MEMORYID4 */
+};
+
+void mainboard_memory_init_params(FSPM_UPD *mupd)
+{
+	int spd_idx;
+	char spd_name[20];
+	size_t spd_size;
+
+	FSP_M_CONFIG *mem_cfg = &mupd->FspmConfig;
+	mem_cfg->DqPinsInterleaved = true;			/* DDR_DQ in interleave mode */
+	mem_cfg->CaVrefConfig      = 2;				/* VREF_CA to CH_A and VREF_DQ_B to CH_B */
+	mem_cfg->MemorySpdDataLen  = CONFIG_DIMM_SPD_SIZE;
+
+	/* Get SPD for soldered RAM SPD (CH A) */
+	gpio_configure_pads(memory_id_gpio_table, ARRAY_SIZE(memory_id_gpio_table));
+
+	spd_idx = gpio_get(GPP_F16) | gpio_get(GPP_F17) << 1 | gpio_get(GPP_F18) << 2 |
+		  gpio_get(GPP_F19) << 3 | gpio_get(GPP_F20) << 4;
+	printk(BIOS_DEBUG, "Detected MEMORY_ID = %d\n", spd_idx);
+	snprintf(spd_name, sizeof(spd_name), "spd_%d.bin", spd_idx);
+	mem_cfg->MemorySpdPtr00    = (uintptr_t)cbfs_map(spd_name, &spd_size);
+
+	/* Get SPD for memory slot (CH B) */
+	struct spd_block blk = { .addr_map = { [1] = 0x51, } };
+	get_spd_smbus(&blk);
+	dump_spd_info(&blk);
+
+	mem_cfg->MemorySpdPtr10    = (uintptr_t)blk.spd_array[1];
+}
diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/overridetree.cb b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/overridetree.cb
new file mode 100644
index 0000000000..14fcf371c7
--- /dev/null
+++ b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/overridetree.cb
@@ -0,0 +1,93 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
+chip soc/intel/skylake
+	device domain 0 on
+		device ref south_xhci on
+			register "usb2_ports" = "{
+				[0] = USB2_PORT_MID(OC0),		// JUSB1 (USB-A always on)
+				[1] = USB2_PORT_MID(OC1),		// JUSB2 (USB-A)
+				[2] = USB2_PORT_MID(OC_SKIP),		// JFPR (smartcard slot)
+				[3] = USB2_PORT_MID(OC_SKIP),		// JUSBC (USB-C)
+				[4] = USB2_PORT_MID(OC_SKIP),		// JCAM (IR camera)
+				[5] = USB2_PORT_MID(OC_SKIP),		// JWWAN (M.2 WWAN USB)
+				[6] = USB2_PORT_MID(OC_SKIP),		// JWLAN (M.2 WLAN USB)
+				[7] = USB2_PORT_MID(OC_SKIP),		// JCAM (webcam)
+				[8] = USB2_PORT_MID(OC_SKIP),		// JFPR (fingerprint reader)
+				[9] = USB2_PORT_MID(OC_SKIP),		// JLCD (touch panel)
+			}"
+			register "usb3_ports" = "{
+				[0] = USB3_PORT_DEFAULT(OC0),		// JUSB1 (USB-A always on)
+				[1] = USB3_PORT_DEFAULT(OC1),		// JUSB2 (USB-A)
+				[2] = USB3_PORT_DEFAULT(OC_SKIP),	// JSD (SD card reader)
+				[3] = USB3_PORT_DEFAULT(OC_SKIP),	// JUSBC (USB-C)
+			}"
+		end
+
+		# PCIe controller 1 - 1x2+2x1
+		#   PCIE 1-2   - RP1  - dGPU - CLKOUT0 - CLKREQ0
+		#   PCIE 4     - RP4  - WWAN - CLKOUT1 - CLKREQ1
+		#
+		# PCIe controller 2 - 2x1+1x2 (lane reversal)
+		#   PCIE 5     - GBE  - GBE  - CLKOUT2 - CLKREQ2 (clobbers RP8)
+		#   PCIE 6     - RP7  - WLAN - CLKOUT3 - CLKREQ3
+		#   PCIE 7-8   - RP5  - TB3  - CLKOUT4 - CLKREQ4
+		#
+		# PCIe controller 3 - 1x4 (lane reversal)
+		#   PCIE 9-12  - RP9  - SSD  - CLKOUT5 - CLKREQ5
+
+		# dGPU - x2
+		device ref pcie_rp1 on
+			register "PcieRpClkReqSupport[0]"		= "1"
+			register "PcieRpClkReqNumber[0]"		= "0"
+			register "PcieRpClkSrcNumber[0]"		= "0"
+			register "PcieRpAdvancedErrorReporting[0]"	= "1"
+			register "PcieRpLtrEnable[0]"			= "1"
+			device generic 0 alias dgpu on end
+		end
+
+		# M.2 WWAN - x1
+		device ref pcie_rp4 on
+			register "PcieRpClkReqSupport[3]"		= "1"
+			register "PcieRpClkReqNumber[3]"		= "1"
+			register "PcieRpClkSrcNumber[3]"		= "1"
+			register "PcieRpAdvancedErrorReporting[3]"	= "1"
+			register "PcieRpLtrEnable[3]"			= "1"
+		end
+
+		# Ethernet (clobbers RP8)
+		device ref gbe on
+			register "LanClkReqSupported"			= "1"
+			register "LanClkReqNumber"			= "2"
+			register "EnableLanLtr"				= "1"
+			register "EnableLanK1Off"			= "1"
+		end
+
+		# M.2 WLAN - x1
+		device ref pcie_rp7 on
+			register "PcieRpClkReqSupport[6]"		= "1"
+			register "PcieRpClkReqNumber[6]"		= "3"
+			register "PcieRpClkSrcNumber[6]"		= "3"
+			register "PcieRpAdvancedErrorReporting[6]"	= "1"
+			register "PcieRpLtrEnable[6]"			= "1"
+		end
+
+		# TB3 (Alpine Ridge LP) - x2
+		device ref pcie_rp5 on
+			register "PcieRpClkReqSupport[4]"		= "1"
+			register "PcieRpClkReqNumber[4]"		= "4"
+			register "PcieRpClkSrcNumber[4]"		= "4"
+			register "PcieRpAdvancedErrorReporting[4]"	= "1"
+			register "PcieRpLtrEnable[4]"			= "1"
+			register "PcieRpHotPlug[4]"			= "1"
+		end
+
+		# M.2 2280 SSD - x2
+		device ref pcie_rp9 on
+			register "PcieRpClkReqSupport[8]"		= "1"
+			register "PcieRpClkReqNumber[8]"		= "5"
+			register "PcieRpClkSrcNumber[8]"		= "5"
+			register "PcieRpAdvancedErrorReporting[8]"	= "1"
+			register "PcieRpLtrEnable[8]"			= "1"
+		end
+	end
+end
diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd/spd_0.bin b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd/spd_0.bin
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new file mode 100644
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diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd/spd_11.bin b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd/spd_11.bin
new file mode 100644
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diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd/spd_12.bin b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd/spd_12.bin
new file mode 100644
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diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd/spd_13.bin b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd/spd_13.bin
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diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd/spd_16.bin b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd/spd_16.bin
new file mode 100644
index 0000000000000000000000000000000000000000..a64a5a93fb4aef4d5f63d79cb2582731b9ac5063
GIT binary patch
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literal 0
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diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd/spd_17.bin b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd/spd_17.bin
new file mode 100644
index 0000000000000000000000000000000000000000..5f23e86606094d3e5d2011db902ebd4a500bbffa
GIT binary patch
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HcmV?d00001

diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd/spd_18.bin b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd/spd_18.bin
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diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd/spd_19.bin b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd/spd_19.bin
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HcmV?d00001

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HcmV?d00001

diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd/spd_3.bin b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd/spd_3.bin
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diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd/spd_4.bin b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd/spd_4.bin
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diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd/spd_5.bin b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd/spd_5.bin
new file mode 100644
index 0000000000000000000000000000000000000000..a64a5a93fb4aef4d5f63d79cb2582731b9ac5063
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literal 512
NcmZQz7zHCa1ONg600961

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HcmV?d00001

diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd/spd_6.bin b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd/spd_6.bin
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GIT binary patch
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NcmZQz7zHCa1ONg600961

literal 0
HcmV?d00001

diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd/spd_7.bin b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd/spd_7.bin
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diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd/spd_8.bin b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd/spd_8.bin
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From 6768586353488beedadad33fe478251ac578c896 Mon Sep 17 00:00:00 2001
From: Mate Kukri <km@mkukri.xyz>
Date: Mon, 28 Oct 2024 17:57:49 +0100
Subject: [PATCH 1594/3886] Documentation: Add information about the deguard
 utility
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Change-Id: Idba0f461d31db31cbc9c35ee3da70c116d5493ce
Signed-off-by: Mate Kukri <km@mkukri.xyz>
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84825
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Nicholas Chin <nic.c3.14@gmail.com>
Reviewed-by: Filip Lewiński <filip.lewinski@3mdeb.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 Documentation/soc/intel/deguard.md | 100 +++++++++++++++++++++++++++++
 Documentation/soc/intel/index.md   |   1 +
 2 files changed, 101 insertions(+)
 create mode 100644 Documentation/soc/intel/deguard.md

diff --git a/Documentation/soc/intel/deguard.md b/Documentation/soc/intel/deguard.md
new file mode 100644
index 0000000000..9b90594242
--- /dev/null
+++ b/Documentation/soc/intel/deguard.md
@@ -0,0 +1,100 @@
+# Intel BootGuard bypass on Skylake/Kabylake
+
+Run `git clone "https://review.coreboot.org/deguard"` to get the deguard source code.
+
+## How deguard works
+
+Deguard makes use of [CVE-2017-5705].
+
+This vulnerability has been fixed by Intel in newer ME v11.x.x.x firmware releases, however ME
+11 hardware has no protection against downgrading the ME version by overwriting the SPI flash
+physically, thus we can downgrade to a vulnerable version.
+
+After downgrade, we exploit the bring-up (BUP) module of the vulnerable firmware, overwriting
+the copy of field programmable fuses (FPF) stored in SRAM, resulting in the fused BootGuard
+configuration being replaced with our desired one (which has Bootguard disabled).
+
+## Supported boards
+
+The list of supported boards can be seen by examining the degaurd repo:
+
+    ls -l data/delta
+
+If your board is already supported, you can skip to `Generating a deguarded ME image` below.
+
+If not, then you need to generate the delta data for your board first.
+
+## Adding a new board/target
+
+If your board is not yet supported, you will need to generate the delta data between the default
+ME configuration and vendor-provided board-specific ME configuration.
+
+This data is located in the `data/delta/<target>` directory for each target.
+
+To generate the delta data, dump the vendor firmware from your board, and execute:
+
+    ./generatedelta.py --input <dump> --output data/delta/<target>
+
+NOTE:
+The delta generation process only takes your factory dump ME firmware as an input. This is
+because an ME firmware image contains both the default and system specific configuration, which
+are then compared by deguard.
+
+You *must discard* the `/home/secureboot` directory from the delta for the zero FPF config to work.
+
+You can optionally also discard `home/{amt,fwupdate,pavp,ptt}` from the delta.
+
+Please submit delta data for new boards to the deguard repo using the regular Gerrit review
+process.
+
+## Generating a deguarded ME image
+
+Once you have the delta data for your board, you will need to obtain a donor image for your
+platform variant with a supported/vulnerable ME version (see URLs below).
+
+This can either be a full image with a flash descriptor or just a bare ME region.
+
+Afterwards, execute the following command and enjoy:
+
+    ./finalimage.py --delta data/delta/<target> --version <donor version> --pch <H or LP PCH type> --sku <2M or 5M SKU> --fake-fpfs data/fpfs/zero --input <donor> --output <output>
+
+Example: `./finalimage.py --delta data/delta/thinkpad_t480 --version 11.6.0.1126 --pch LP --sku 2M --fake-fpfs data/fpfs/zero --input me_donor.bin --output me_deguarded.bin`
+
+NOTE:
+The output will be a bare deguard-patched ME region which requires **the HAP bit to be enabled**
+in your flash descriptor to work.
+
+If you do not enable the HAP bit, the deguard-patched ME will not load, and the system will not
+boot.
+
+## Note on field programmable fuses
+
+This document recommends faking a set of FPFs that are all zero as a BootGuard bypass strategy.
+
+This causes the platform to work in legacy mode, and does not require dumping the fuses from the
+PCH.
+
+It is also possible to enable measured mode instead (there is some example FPF data for this).
+
+Theoretically it is possible to even re-enable BootGuard with a custom private key (with the
+caveat that it is obviously insecure against physical access).
+
+## Donor images
+
+This section lists some URLs to recommended and tested donor images. Any image with a supported
+firmware version and variant ought to work, but the path of least resistance is for everyone to
+use the same images.
+
+|Version|Variant|SKU|URL|Notes|
+|-|-|-|-|-|
+|11.6.0.1126|H (Desktop)|2M|[link](https://web.archive.org/web/20230822134231/https://download.asrock.com/BIOS/1151/H110M-DGS(7.30)ROM.zip)|Zipped flash image|
+|11.6.0.1126|LP (Laptop)|2M|[link](https://dl.dell.com/FOLDER04573471M/1/Inspiron_5468_1.3.0.exe)|Dell BIOS update (use [Dell_PFS_Extract.py](https://github.com/vuquangtrong/Dell-PFS-BIOS-Assembler/blob/master/Dell_PFS_Extract.py))|
+
+## Thanks
+
+Thanks goes to PT Research and Youness El Alaoui for previous work on exploiting Intel SA 00086.
+
+- [IntelTXE-PoC](https://github.com/kakaroto/IntelTXE-PoC)
+- [MFSUtil](https://github.com/kakaroto/MFSUtil)
+
+[CVE-2017-5705]: https://www.intel.com/content/www/us/en/security-center/advisory/intel-sa-00086.html
\ No newline at end of file
diff --git a/Documentation/soc/intel/index.md b/Documentation/soc/intel/index.md
index 5eac084206..ef032f5ece 100644
--- a/Documentation/soc/intel/index.md
+++ b/Documentation/soc/intel/index.md
@@ -16,4 +16,5 @@ Firmware Interface Table <fit.md>
 Apollolake <apollolake/index.md>
 CSE FW Update <cse_fw_update/cse_fw_update.md>
 Xeon Scalable processor <xeon_sp/index.md>
+Skylake/Kaby Lake BootGuard bypass <deguard.md>
 ```

From 397c5fe420217362110c0f17e2f03bc997eee5da Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Tue, 15 Jul 2025 14:31:53 -0500
Subject: [PATCH 1595/3886] Documentation: Add a mainboard entry for the Lenovo
 T480/T480s

Add a heading for Skylake/Kabylake Lenovo mainboards in anticipation
of additional boards being added in the future. Add a new page for the
T480/T480s, loosely based on the page for the T440p.

Thanks to Askareth on Matrix for the initial draft and copious testing.

Change-Id: I3c7a9ca28be5524b42177b92387f35c6d25b48da
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88439
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 Documentation/mainboard/index.md       |   7 +
 Documentation/mainboard/lenovo/t480.md | 199 +++++++++++++++++++++++++
 2 files changed, 206 insertions(+)
 create mode 100644 Documentation/mainboard/lenovo/t480.md

diff --git a/Documentation/mainboard/index.md b/Documentation/mainboard/index.md
index 7ae0ef5644..7412bc0f1d 100644
--- a/Documentation/mainboard/index.md
+++ b/Documentation/mainboard/index.md
@@ -242,6 +242,13 @@ Internal flashing <lenovo/ivb_internal_flashing.md>
 T440p <lenovo/t440p.md>
 ```
 
+### Skylake/Kabylake series
+
+```{toctree}
+:maxdepth: 1
+
+T480/T480s <lenovo/t480.md>
+```
 ## Libretrend
 
 ```{toctree}
diff --git a/Documentation/mainboard/lenovo/t480.md b/Documentation/mainboard/lenovo/t480.md
new file mode 100644
index 0000000000..9ebce8ff7d
--- /dev/null
+++ b/Documentation/mainboard/lenovo/t480.md
@@ -0,0 +1,199 @@
+# Lenovo ThinkPad T480/T480s
+
+This page describes how to run coreboot on the [Lenovo ThinkPad T480/T480s].
+
+## Important Notes
+
+### EC UART
+The T480 (but not T480s) supports the use of the EC UART for debugging. If you want to use this
+feature, you need to downgrade the vendor firmware to a version with a compatible EC firmware
+*before flashing* for the EC UART to work properly. The EC firmware version needs to be 1.22
+(N24HT37W), which means any BIOS from 1.39 (N24ET64W) to 1.54 (N24ET79W) is acceptable.
+
+The mapping can be seen here [on Lenovo's site].
+
+### Bootguard
+The T480/T480s both have Intel Bootguard enabled, which prevents the device from running
+firmware which is not cryptographically signed using the manufacturer's key.
+
+The [deguard utility](../../soc/intel/deguard) will need to be used in order to bypass Bootguard
+on these devices.
+
+### Thunderbolt
+
+Older versions of Thunderbolt 3 controller firmware are buggy on these laptops.
+
+The issue is that the TB3 firmware writes its logging data to the TB3's own 4M flash chip, and
+when the flash chip fills up, the device fails to boot.
+
+Lenovo has addressed this in a TB3 firmware update, which is recommended be be applied before
+installing coreboot to ensure long-term reliability of the device. That said, most laptops that
+still work likely have this fix already applied, and you can always externally flash the TB3
+firmware update at the same time as flashing coreboot.
+
+If your device becomes bricked due to this issue, the only resolution is to externally flash the
+updated/fixed TB3 firmware flash (which is located on a separate flash IC from the main firmware).
+
+The Lenovo TB3 FW update can be obtained [from Lenovo's site].
+
+The Libreboot project has some more information about the issue and [how to externally flash the
+TB3 firmware].
+
+## Initial Setup
+
+Follow the coreboot [tutorial](../../tutorial/part1) to:
+* install dependencies/prerequisites
+* clone the coreboot repo
+* build the coreboot toolchain
+
+You will also need to clone the [deguard](https://review.coreboot.org/deguard) repository, in
+order to bypass BootGuard.
+
+## Required proprietary blobs
+
+When flashing the T480/T480s for the first time, the following blobs are required for a full
+flash image:
+ * Flash Descriptor (IFD)
+ * Management Engine (ME)
+ * Gigabit Ethernet (GBE)
+
+These will either be extracted from the vendor firmware on the device or downloaded as needed.
+
+Additionally, the T480/T480s make use of Intel's Firmware Support Package (FSP) for memory and
+silicon init. FSP is provided by default as part of the coreboot build, no user intervention is
+required.
+
+## Reading the vendor firmware
+
+The T480/T480s have a single flash chip, a 16 MiB W25Q128 in a SOIC-8 package. The flash chip
+uses the following layout:
+
+    00000000:00000fff flash descriptor (fd)
+    00fff000:00000fff platform data (unused)
+    00001000:00002fff gbe
+    00003000:006fffff me
+    00700000:00ffffff bios
+
+
+To read the vendor firmware, disconnect external power and remove the back of the laptop
+according to the T480 [Hardware Maintenance Manual].
+Disconnect/remove the battery (and CMOS battery if equipped). Attach a chip clip to the flash.
+Use an external programmer (ch341a, raspberry Pi, etc) and flashrom to read the chip.
+
+## Preparing the binaries
+
+The IFD and GBE need to be extracted from the vendor firmware backup read from the flash chip.
+See [Extract IFD binaries](../../util/ifdtool/binary_extraction).
+Rename the extracted files to `ifd.bin` and `gbe.bin` and move them to the `binaries` folder
+you created per the instructions.
+
+### Preparing the ME with deguard
+
+Please review the documentation on the use of the [deguard utility](../../soc/intel/deguard).
+
+Since the T480/T480s is already a supported target, we simply need to download/extract the donor
+image, then generate the "deguarded" ME firmware image
+
+The donor ME binary required for use with the deguard utility can be downloaded as part of the
+[Dell firmware updater]. After downloading, use [Dell_PFS_Extract.py] to extract the required ME
+firmware image from the updater:
+
+    python Dell_PFS_Extract.py Inspiron_5468_1.3.0.exe
+
+The resulting binary should be renamed `me_donor.bin` and moved to the `binaries` folder with
+the IFD and GBE.
+
+Then, generate the deguarded ME firmware image:
+
+    ./finalimage.py --delta data/delta/thinkpad_t480 --version 11.6.0.1126 --pch LP --sku 2M --fake-fpfs data/fpfs/zero --input ../coreboot/binaries/me_donor.bin --output ../coreboot/binaries/me_deguarded.bin
+
+The command above assumes you are running deguard from the root of the deguard repo, that the
+deguard and coreboot repos are checked out under the same parent directory, and that your ME
+donor firmware is in the `binaries` subdirectory of coreboot (along with the IFD/GBE binaries).
+Adjust the paths as necessary if that is not the case.
+
+### Preparing the IFD
+
+In order to use the modified ME firmware binary generated by deguard above, we need to set the
+HAP bit in the IFD using `ifdtool`:
+
+    util/ifdtool/ifdtool -p sklkbl -M 1 binaries/ifd.bin
+
+The modified IFD will be saved as `ifd.bin.new`. Rename the original file to `ifd.bin.orig` and
+the HAP-enabled one to `ifd.bin`
+
+## Building coreboot
+
+You can use `make menuconfig` or `make nconfig` to select the mainboard (Lenovo T480 or T480s),
+enable the inclusion of the IFD/ME/GBE binaries, and select your payload and options.
+You can also just use the following defconfig:
+
+    CONFIG_VENDOR_LENOVO=y
+    CONFIG_IFD_BIN_PATH="binaries/ifd.bin"
+    CONFIG_ME_BIN_PATH="binaries/me_deguarded.bin"
+    CONFIG_GBE_BIN_PATH="binaries/gbe.bin"
+    CONFIG_HAVE_IFD_BIN=y
+    CONFIG_BOARD_LENOVO_T480=y
+    CONFIG_HAVE_ME_BIN=y
+    CONFIG_HAVE_GBE_BIN=y
+    CONFIG_PAYLOAD_EDK2=y
+
+Save the above to a file called `defconfig` in your coreboot directory, then run:
+
+    make defconfig
+    make -j"$(nproc)"
+
+Upon successful compilation, you will have a file `coreboot.rom` in the `build` directory ready
+to flash.
+
+## Flashing instructions
+
+The initial flash of coreboot with the modified IFD and deguarded ME must be done using an
+external programmer:
+
+    sudo flashrom -p <programmer> -w coreboot.rom
+
+Subsequent flashes can be done internally and need only modify the `bios` region of the flash:
+
+    sudo flashrom -p internal -w coreboot.rom --ifd -i bios -N
+
+The `coreboot.rom` flashed on subsequent flashes does not need to contain the IFD/ME/GBE
+binaries if only flashing the `bios` region.
+
+## Known Issues
+
+- Alpine Ridge Thunderbolt 3 controller does not work
+  - Lower (right) USB-C port only works for charging/DP alt mode, not USB/PCIe data
+- Some Fn+F{1-12} keys aren't handled correctly
+- Nvidia dGPU is finicky
+  - Needs option ROM
+  - Power enable code is buggy
+  - Proprietary driver does not work at all
+  - Nouveau only works on linux 6.8-6.9
+- Headphone jack detection
+  - Both headphone jack and speakers work when manually selected via pulseaudio
+
+## Verified Working
+
+- Integrated graphics init with libgfxinit
+- video output: internal (eDP), miniDP
+- ACPI support
+- keyboard and trackpoint
+- SATA
+- M.2 SATA SSD
+- NVMe
+- USB
+- Ethernet
+- WLAN
+- WWAN
+- Bluetooth
+- Virtualization: VT-x and VT-d
+- Internal flashing (after initial flash with unlocked IFD)
+
+[Lenovo ThinkPad T480/T480s]: https://pcsupport.lenovo.com/us/en/products/laptops-and-netbooks/thinkpad-t-series-laptops/thinkpad-t480-type-20l5-20l6/
+[Hardware Maintenance Manual]: https://download.lenovo.com/pccbbs/mobiles_pdf/t480_hmm_en.pdf
+[on Lenovo's site]: https://support.lenovo.com/us/en/downloads/ds502355-bios-update-utility-bootable-cd-for-windows-10-64-bit-linux-thinkpad-t480
+[from Lenovo's site]: https://pcsupport.lenovo.com/gb/en/products/laptops-and-netbooks/thinkpad-t-series-laptops/thinkpad-t480s-type-20l7-20l8/solutions/ht508988-critical-intel-thunderbolt-software-and-firmware-updates-thinkpad
+[how to externally flash the TB3 firmware]: https://libreboot.org/docs/install/t480.html#thunderbolt-issue-read-this-before-flashing
+[Dell firmware updater]: https://web.archive.org/web/20241110222323/https://dl.dell.com/FOLDER04573471M/1/Inspiron_5468_1.3.0.exe
+[Dell_PFS_Extract.py]: https://github.com/vuquangtrong/Dell-PFS-BIOS-Assembler/blob/master/Dell_PFS_Extract.py
\ No newline at end of file

From 85da3954d02df53deb5d46444882c2004b2926b5 Mon Sep 17 00:00:00 2001
From: Martin Roth <gaumless@gmail.com>
Date: Sun, 20 Apr 2025 16:06:56 -0600
Subject: [PATCH 1596/3886] .gitmodules: Ignore changes make by
 what-jenkins-does

When running `make what-jenkins-does`, the intel-sec-tools and gowsid
submodules are left with some new files, marking them as dirty.
This changes fixes that.

Change-Id: Ice98c1a61201cbf63580835966b78f053d7853a2
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87380
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 .gitmodules | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/.gitmodules b/.gitmodules
index c1d7849a9e..4fa82999dc 100644
--- a/.gitmodules
+++ b/.gitmodules
@@ -54,6 +54,7 @@
 [submodule "3rdparty/intel-sec-tools"]
 	path = 3rdparty/intel-sec-tools
 	url = https://review.coreboot.org/9esec-security-tooling.git
+	ignore = dirty
 [submodule "3rdparty/stm"]
 	path = 3rdparty/stm
 	url = https://review.coreboot.org/STM
@@ -62,6 +63,7 @@
 	path = util/goswid
 	url = https://review.coreboot.org/goswid
 	branch = trunk
+	ignore = dirty
 [submodule "src/vendorcode/amd/opensil/genoa_poc/opensil"]
 	path = src/vendorcode/amd/opensil/genoa_poc/opensil
 	url = https://review.coreboot.org/opensil_genoa_poc.git

From 43a54e3b1b87a2b2101682deb6d9b60e291cbfdc Mon Sep 17 00:00:00 2001
From: Maximilian Brune <maximilian.brune@9elements.com>
Date: Sun, 15 Sep 2024 08:27:00 -0700
Subject: [PATCH 1597/3886] util/amdfwtool: Add binary parsing

This adds parsing for some more possible firmware blobs on AMD.
These binaries are used on a mainboard based on glinda SOC.

Tested: Boot birman_plus mainboard

Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: I78d7a9dba71de557e0a9a885d8561eea1f4191ef
Original-signed-off-by: Anand Vaikar <a.vaikar2021@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84373
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 util/amdfwtool/amdfwtool.c  | 29 ++++++++++++---
 util/amdfwtool/amdfwtool.h  | 10 ++++++
 util/amdfwtool/data_parse.c | 70 +++++++++++++++++++++++++++++++++++++
 3 files changed, 105 insertions(+), 4 deletions(-)

diff --git a/util/amdfwtool/amdfwtool.c b/util/amdfwtool/amdfwtool.c
index 36b205c355..2b70a0527b 100644
--- a/util/amdfwtool/amdfwtool.c
+++ b/util/amdfwtool/amdfwtool.c
@@ -172,12 +172,14 @@ amd_fw_entry amd_psp_fw_table[] = {
 	{ .type = AMD_FW_PSP_SMU_FIRMWARE, .subprog = 1, .level = PSP_BOTH | PSP_LVL2_AB },
 	{ .type = AMD_FW_PSP_SMU_FIRMWARE, .subprog = 2, .level = PSP_BOTH | PSP_LVL2_AB },
 	{ .type = AMD_FW_PSP_SECURED_DEBUG, .level = PSP_LVL2 | PSP_LVL2_AB,
-									.skip_hashing = true },
+	  .skip_hashing = true },
+	{ .type = AMD_FW_PSP_TEEIPKEY, .subprog = 0, .level = PSP_LVL2 | PSP_LVL2_AB,
+	  .skip_hashing = true },
 	{ .type = AMD_FW_ABL_PUBKEY, .level = PSP_BOTH | PSP_BOTH_AB },
 	{ .type = AMD_PSP_FUSE_CHAIN, .level = PSP_LVL2 | PSP_LVL2_AB },
 	{ .type = AMD_FW_PSP_TRUSTLETS, .level = PSP_LVL2 | PSP_LVL2_AB },
 	{ .type = AMD_FW_PSP_TRUSTLETKEY, .level = PSP_LVL2 | PSP_LVL2_AB },
-	{ .type = AMD_FW_PSP_SMU_FIRMWARE2, .level = PSP_BOTH | PSP_LVL2_AB },
+	{ .type = AMD_FW_PSP_SMU_FIRMWARE2, .subprog = 0, .level = PSP_BOTH | PSP_LVL2_AB },
 	{ .type = AMD_FW_PSP_SMU_FIRMWARE2, .subprog = 1, .level = PSP_BOTH | PSP_LVL2_AB },
 	{ .type = AMD_FW_PSP_SMU_FIRMWARE2, .subprog = 2, .level = PSP_BOTH | PSP_LVL2_AB },
 	{ .type = AMD_BOOT_DRIVER, .level = PSP_BOTH | PSP_LVL2_AB },
@@ -187,6 +189,7 @@ amd_fw_entry amd_psp_fw_table[] = {
 	{ .type = AMD_DEBUG_UNLOCK, .level = PSP_LVL2 | PSP_LVL2_AB },
 	{ .type = AMD_HW_IPCFG, .subprog = 0, .level = PSP_LVL2 | PSP_LVL2_AB },
 	{ .type = AMD_HW_IPCFG, .subprog = 1, .level = PSP_LVL2 | PSP_LVL2_AB },
+	{ .type = AMD_HW_IPCFG, .subprog = 2, .level = PSP_LVL2 | PSP_LVL2_AB },
 	{ .type = AMD_WRAPPED_IKEK, .level = PSP_BOTH | PSP_LVL2_AB, .skip_hashing = true },
 	{ .type = AMD_TOKEN_UNLOCK, .level = PSP_BOTH | PSP_LVL2_AB },
 	{ .type = AMD_SEC_GASKET, .subprog = 0, .level = PSP_BOTH | PSP_LVL2_AB },
@@ -226,7 +229,8 @@ amd_fw_entry amd_psp_fw_table[] = {
 	{ .type = AMD_FW_SPL, .level = PSP_LVL2 | PSP_LVL2_AB },
 	{ .type = AMD_FW_DMCU_ERAM, .level = PSP_LVL2 | PSP_LVL2_AB },
 	{ .type = AMD_FW_DMCU_ISR, .level = PSP_LVL2 | PSP_LVL2_AB },
-	{ .type = AMD_FW_MSMU, .level = PSP_LVL2 | PSP_LVL2_AB },
+	{ .type = AMD_FW_MSMU, .subprog = 0, .level = PSP_LVL2 | PSP_LVL2_AB },
+	{ .type = AMD_FW_MSMU, .subprog = 1, .level = PSP_LVL2 | PSP_LVL2_AB },
 	{ .type = AMD_FW_SPIROM_CFG, .level = PSP_LVL2 | PSP_LVL2_AB },
 	{ .type = AMD_FW_MPIO, .level = PSP_LVL2 | PSP_LVL2_AB },
 	{ .type = AMD_FW_PSP_SMUSCS, .level = PSP_BOTH | PSP_LVL2_AB },
@@ -235,6 +239,7 @@ amd_fw_entry amd_psp_fw_table[] = {
 		.generate_manifest = true },
 	{ .type = AMD_RIB, .subprog = 0, .level = PSP_LVL2 | PSP_LVL2_AB },
 	{ .type = AMD_RIB, .subprog = 1, .level = PSP_LVL2 | PSP_LVL2_AB },
+	{ .type = AMD_RIB, .subprog = 2, .level = PSP_LVL2 | PSP_LVL2_AB },
 	{ .type = AMD_FW_MPDMA_TF, .level = PSP_BOTH | PSP_BOTH_AB },
 	{ .type = AMD_TA_IKEK, .level = PSP_BOTH | PSP_LVL2_AB, .skip_hashing = true },
 	{ .type = AMD_FW_GMI3_PHY, .level = PSP_BOTH | PSP_BOTH_AB },
@@ -242,18 +247,33 @@ amd_fw_entry amd_psp_fw_table[] = {
 	{ .type = AMD_FW_AMF_SRAM, .level = PSP_LVL2 | PSP_LVL2_AB },
 	{ .type = AMD_FW_AMF_DRAM, .inst = 0, .level = PSP_LVL2 | PSP_LVL2_AB },
 	{ .type = AMD_FW_AMF_DRAM, .inst = 1, .level = PSP_LVL2 | PSP_LVL2_AB },
+	{ .type = AMD_FW_MFD_MPM, .inst = 0, .level = PSP_LVL2 | PSP_LVL2_AB },
+	{ .type = AMD_FW_MFD_MPM, .inst = 1, .level = PSP_LVL2 | PSP_LVL2_AB },
 	{ .type = AMD_FW_FCFG_TABLE, .level = PSP_LVL2 | PSP_LVL2_AB },
 	{ .type = AMD_FW_AMF_WLAN, .inst = 0, .level = PSP_LVL2 | PSP_LVL2_AB },
 	{ .type = AMD_FW_AMF_WLAN, .inst = 1, .level = PSP_LVL2 | PSP_LVL2_AB },
+	{ .type = AMD_FW_AMF_WLAN, .inst = 2, .level = PSP_LVL2 | PSP_LVL2_AB },
+	{ .type = AMD_FW_AMF_WLAN, .inst = 3, .level = PSP_LVL2 | PSP_LVL2_AB },
 	{ .type = AMD_FW_AMF_MFD, .level = PSP_LVL2 | PSP_LVL2_AB },
 	{ .type = AMD_TA_IKEK, .level = PSP_BOTH | PSP_LVL2_AB, .skip_hashing = true },
-	{ .type = AMD_FW_MPCCX, .level = PSP_LVL2 | PSP_LVL2_AB },
+	{ .type = AMD_FW_MPCCX, .subprog = 0, .level = PSP_LVL2 | PSP_LVL2_AB },
+	{ .type = AMD_FW_MPCCX, .subprog = 1, .level = PSP_LVL2 | PSP_LVL2_AB },
 	{ .type = AMD_FW_LSDMA, .level = PSP_LVL2 | PSP_LVL2_AB },
 	{ .type = AMD_FW_C20_MP, .level = PSP_BOTH | PSP_LVL2_AB },
 	{ .type = AMD_FW_MINIMSMU, .inst = 0, .level = PSP_BOTH | PSP_LVL2_AB },
 	{ .type = AMD_FW_MINIMSMU, .inst = 1, .level = PSP_BOTH | PSP_LVL2_AB },
+	{ .type = AMD_FW_MINIMSMU, .subprog = 1, .level = PSP_BOTH | PSP_LVL2_AB },
+	{ .type = AMD_FW_GFXIMU_0, .subprog = 0, .level = PSP_BOTH | PSP_LVL2_AB },
+	{ .type = AMD_FW_GFXIMU_0, .subprog = 1, .level = PSP_BOTH | PSP_LVL2_AB },
+	{ .type = AMD_FW_GFXIMU_1, .subprog = 0, .level = PSP_BOTH | PSP_LVL2_AB },
+	{ .type = AMD_FW_GFXIMU_1, .subprog = 1, .level = PSP_BOTH | PSP_LVL2_AB },
+	{ .type = AMD_FW_GFXIMU_2, .level = PSP_BOTH | PSP_LVL2_AB },
 	{ .type = AMD_FW_SRAM_FW_EXT, .level = PSP_LVL2 | PSP_LVL2_AB },
 	{ .type = AMD_FW_UMSMU, .level = PSP_LVL2 | PSP_LVL2_AB },
+	{ .type = AMD_FW_S3IMG, .level = PSP_LVL2 | PSP_LVL2_AB },
+	{ .type = AMD_FW_USBDP, .level = PSP_LVL2 | PSP_LVL2_AB },
+	{ .type = AMD_FW_USBSS, .level = PSP_LVL2 | PSP_LVL2_AB },
+	{ .type = AMD_FW_USB4, .level = PSP_LVL2 | PSP_LVL2_AB },
 	{ .type = AMD_FW_INVALID },
 };
 
@@ -303,6 +323,7 @@ amd_bios_entry amd_bios_table[] = {
 	{ .type = AMD_BIOS_BIN,
 			.reset = 1, .copy = 1, .zlib = 1, .inst = 0, .level = BDT_BOTH },
 	{ .type = AMD_BIOS_APOB_NV, .level = BDT_LVL2 },
+	{ .type = AMD_BIOS_NV_ST, .level = BDT_LVL2 },
 	{ .type = AMD_BIOS_PMUI, .inst = 1, .subpr = 0, .level = BDT_BOTH },
 	{ .type = AMD_BIOS_PMUD, .inst = 1, .subpr = 0, .level = BDT_BOTH },
 	{ .type = AMD_BIOS_PMUI, .inst = 2, .subpr = 0, .level = BDT_BOTH },
diff --git a/util/amdfwtool/amdfwtool.h b/util/amdfwtool/amdfwtool.h
index 70b2600f5c..9897721607 100644
--- a/util/amdfwtool/amdfwtool.h
+++ b/util/amdfwtool/amdfwtool.h
@@ -52,6 +52,7 @@ typedef enum _amd_fw_type {
 	AMD_FW_PSP_TRUSTLETKEY = 0x0d,
 	AMD_FW_PSP_SMU_FIRMWARE2 = 0x12,
 	AMD_DEBUG_UNLOCK = 0x13,
+	AMD_FW_PSP_TEEIPKEY = 0x15,
 	AMD_BOOT_DRIVER = 0x1b,
 	AMD_SOC_DRIVER = 0x1c,
 	AMD_DEBUG_DRIVER = 0x1d,
@@ -103,6 +104,7 @@ typedef enum _amd_fw_type {
 	AMD_RIB = 0x76,
 	AMD_FW_AMF_SRAM = 0x85,
 	AMD_FW_AMF_DRAM = 0x86,
+	AMD_FW_MFD_MPM = 0x87,
 	AMD_FW_AMF_WLAN = 0x88,
 	AMD_FW_AMF_MFD = 0x89,
 	AMD_FW_MPDMA_TF = 0x8c,
@@ -114,8 +116,15 @@ typedef enum _amd_fw_type {
 	AMD_FW_C20_MP = 0x95,
 	AMD_FW_FCFG_TABLE = 0x98,
 	AMD_FW_MINIMSMU = 0x9a,
+	AMD_FW_GFXIMU_0 = 0x9b,
+	AMD_FW_GFXIMU_1 = 0x9c,
+	AMD_FW_GFXIMU_2 = 0x9d,
 	AMD_FW_SRAM_FW_EXT = 0x9d,
 	AMD_FW_UMSMU = 0xa2,
+	AMD_FW_S3IMG = 0xa0,
+	AMD_FW_USBDP = 0xa4,
+	AMD_FW_USBSS = 0xa5,
+	AMD_FW_USB4 = 0xa6,
 	AMD_FW_IMC = 0x200,	/* Large enough to be larger than the top BHD entry type. */
 	AMD_FW_GEC,
 	AMD_FW_XHCI,
@@ -137,6 +146,7 @@ typedef enum _amd_bios_type {
 	AMD_BIOS_EARLY_VGA = 0x69,
 	AMD_BIOS_MP2_CFG = 0x6a,
 	AMD_BIOS_PSP_SHARED_MEM = 0x6b,
+	AMD_BIOS_NV_ST = 0x6d,
 	AMD_BIOS_L2_PTR =  0x70,
 	AMD_BIOS_INVALID,
 	AMD_BIOS_SKIP
diff --git a/util/amdfwtool/data_parse.c b/util/amdfwtool/data_parse.c
index 154d34dc6a..e508e9147b 100644
--- a/util/amdfwtool/data_parse.c
+++ b/util/amdfwtool/data_parse.c
@@ -208,6 +208,9 @@ static uint8_t find_register_fw_filename_psp_dir(char *fw_name, char *filename,
 	} else if (strcmp(fw_name, "PSP_HW_IPCFG_FILE_SUB1") == 0) {
 		fw_type = AMD_HW_IPCFG;
 		subprog = 1;
+	} else if (strcmp(fw_name, "PSP_HW_IPCFG_FILE_SUB2") == 0) {
+		fw_type = AMD_HW_IPCFG;
+		subprog = 2;
 	} else if (strcmp(fw_name, "PSP_SMUFW1_SUB1_FILE") == 0) {
 		fw_type = AMD_FW_PSP_SMU_FIRMWARE;
 		subprog = 1;
@@ -220,6 +223,9 @@ static uint8_t find_register_fw_filename_psp_dir(char *fw_name, char *filename,
 	} else if (strcmp(fw_name, "PSP_SMUFW2_SUB1_FILE") == 0) {
 		fw_type = AMD_FW_PSP_SMU_FIRMWARE2;
 		subprog = 1;
+	} else if (strcmp(fw_name, "PSP_TEEIPKEY_FILE") == 0) {
+		fw_type = AMD_FW_PSP_TEEIPKEY;
+		subprog = 0;
 	} else if (strcmp(fw_name, "PSP_SMUFW2_SUB2_FILE") == 0) {
 		fw_type = AMD_FW_PSP_SMU_FIRMWARE2;
 		subprog = 2;
@@ -341,6 +347,14 @@ static uint8_t find_register_fw_filename_psp_dir(char *fw_name, char *filename,
 		fw_type = AMD_FW_AMF_DRAM;
 		subprog = 0;
 		instance = 1;
+	} else if (strcmp(fw_name, "MFD_MPM_TEE_INS0") == 0) {
+		fw_type = AMD_FW_MFD_MPM;
+		subprog = 0;
+		instance = 0;
+	} else if (strcmp(fw_name, "MFD_MPM_TEE_INS1") == 0) {
+		fw_type = AMD_FW_MFD_MPM;
+		subprog = 0;
+		instance = 1;
 	} else if (strcmp(fw_name, "AMF_WLAN_FILE_INS0") == 0) {
 		fw_type = AMD_FW_AMF_WLAN;
 		subprog = 0;
@@ -349,12 +363,23 @@ static uint8_t find_register_fw_filename_psp_dir(char *fw_name, char *filename,
 		fw_type = AMD_FW_AMF_WLAN;
 		subprog = 0;
 		instance = 1;
+	} else if (strcmp(fw_name, "AMF_WLAN_FILE_INS2") == 0) {
+		fw_type = AMD_FW_AMF_WLAN;
+		subprog = 0;
+		instance = 2;
+	} else if (strcmp(fw_name, "AMF_WLAN_FILE_INS3") == 0) {
+		fw_type = AMD_FW_AMF_WLAN;
+		subprog = 0;
+		instance = 3;
 	} else if (strcmp(fw_name, "AMF_MFD_FILE") == 0) {
 		fw_type = AMD_FW_AMF_MFD;
 		subprog = 0;
 	} else if (strcmp(fw_name, "MPCCX_FILE") == 0) {
 		fw_type = AMD_FW_MPCCX;
 		subprog = 0;
+	} else if (strcmp(fw_name, "MPCCX_FILE_SUB1_FILE") == 0) {
+		fw_type = AMD_FW_MPCCX;
+		subprog = 1;
 	} else if (strcmp(fw_name, "LSDMA_FILE") == 0) {
 		fw_type = AMD_FW_LSDMA;
 		subprog = 0;
@@ -362,6 +387,30 @@ static uint8_t find_register_fw_filename_psp_dir(char *fw_name, char *filename,
 		fw_type = AMD_FW_MINIMSMU;
 		instance = 0;
 		subprog = 0;
+	} else if (strcmp(fw_name, "MINIMSMU_FILE_SUB1_FILE") == 0) {
+		fw_type = AMD_FW_MINIMSMU;
+		instance = 0;
+		subprog = 1;
+	} else if (strcmp(fw_name, "PSP_GFX_IMMU_FILE_0") == 0) {
+		fw_type = AMD_FW_GFXIMU_0;
+		instance = 0;
+		subprog = 0;
+	} else if (strcmp(fw_name, "PSP_GFX_IMMU_FILE_01") == 0) {
+		fw_type = AMD_FW_GFXIMU_0;
+		instance = 0;
+		subprog = 1;
+	} else if (strcmp(fw_name, "PSP_GFX_IMMU_FILE_1") == 0) {
+		fw_type = AMD_FW_GFXIMU_1;
+		instance = 0;
+		subprog = 0;
+	} else if (strcmp(fw_name, "PSP_GFX_IMMU_FILE_11") == 0) {
+		fw_type = AMD_FW_GFXIMU_1;
+		instance = 0;
+		subprog = 1;
+	} else if (strcmp(fw_name, "PSP_GFX_IMMU_FILE_2") == 0) {
+		fw_type = AMD_FW_GFXIMU_2;
+		instance = 0;
+		subprog = 0;
 	} else if (strcmp(fw_name, "MINIMSMU_FILE_INS1") == 0) {
 		fw_type = AMD_FW_MINIMSMU;
 		instance = 1;
@@ -416,6 +465,9 @@ static uint8_t find_register_fw_filename_psp_dir(char *fw_name, char *filename,
 	} else if (strcmp(fw_name, "MSMU_FILE") == 0) {
 		fw_type = AMD_FW_MSMU;
 		subprog = 0;
+	} else if (strcmp(fw_name, "MSMU_FILE_SUB1_FILE") == 0) {
+		fw_type = AMD_FW_MSMU;
+		subprog = 1;
 	} else if (strcmp(fw_name, "DMCUB_FILE") == 0) {
 		fw_type = AMD_FW_DMCUB;
 		subprog = 0;
@@ -447,6 +499,18 @@ static uint8_t find_register_fw_filename_psp_dir(char *fw_name, char *filename,
 	} else if (strcmp(fw_name, "UMSMU_FILE") == 0) {
 		fw_type = AMD_FW_UMSMU;
 		subprog = 0;
+	} else if (strcmp(fw_name, "PSP_S3_IMG") == 0) {
+		fw_type = AMD_FW_S3IMG;
+		subprog = 0;
+	} else if (strcmp(fw_name, "PSP_USB_DP") == 0) {
+		fw_type = AMD_FW_USBDP;
+		subprog = 0;
+	} else if (strcmp(fw_name, "PSP_USB_SS") == 0) {
+		fw_type = AMD_FW_USBSS;
+		subprog = 0;
+	} else if (strcmp(fw_name, "PSP_USB_4") == 0) {
+		fw_type = AMD_FW_USB4;
+		subprog = 0;
 	} else if (strcmp(fw_name, "PSP_OEM_ABL_KEY_FILE") == 0) {
 		fw_type = AMD_FW_ABL_PUBKEY;
 		subprog = 0;
@@ -471,6 +535,9 @@ static uint8_t find_register_fw_filename_psp_dir(char *fw_name, char *filename,
 	} else if (strcmp(fw_name, "PSP_RIB_FILE_SUB1") == 0) {
 		fw_type = AMD_RIB;
 		subprog = 1;
+	} else if (strcmp(fw_name, "PSP_RIB_FILE_SUB2") == 0) {
+		fw_type = AMD_RIB;
+		subprog = 2;
 	} else if (strcmp(fw_name, "FEATURE_TABLE_FILE") == 0) {
 		fw_type = AMD_FW_FCFG_TABLE;
 		subprog = 0;
@@ -559,6 +626,9 @@ static uint8_t find_register_fw_filename_bios_dir(char *fw_name, char *filename,
 		} else {
 			fw_type = AMD_BIOS_SKIP;
 		}
+	} else if (strcmp(fw_name, "PSP_MP2CFG_FILE") == 0) {
+		fw_type = AMD_BIOS_MP2_CFG;
+		subprog = 0;
 	} else {
 		fw_type = AMD_BIOS_INVALID;
 	}

From cba0f0b8b925db48e8a8ff13dccde26b0756c395 Mon Sep 17 00:00:00 2001
From: Maximilian Brune <maximilian.brune@9elements.com>
Date: Sun, 25 May 2025 11:03:07 +0200
Subject: [PATCH 1598/3886] payloads/external/LinuxBoot: Rename build target

To avoid confusion and make it more obvious that the 'build' target
creates the build directory, append a slash at the end.

Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: I49b4fef859f642cc03c0223cb1773597718e56cb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87819
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 payloads/external/LinuxBoot/Makefile         | 12 ++++++------
 payloads/external/LinuxBoot/targets/linux.mk |  4 ++--
 2 files changed, 8 insertions(+), 8 deletions(-)

diff --git a/payloads/external/LinuxBoot/Makefile b/payloads/external/LinuxBoot/Makefile
index 83b8d6e0ea..c56e9fc635 100644
--- a/payloads/external/LinuxBoot/Makefile
+++ b/payloads/external/LinuxBoot/Makefile
@@ -19,32 +19,32 @@ endif
 
 ifeq ($(CONFIG_LINUXBOOT_KERNEL_BZIMAGE),y)
 
-build/Image: $(kernel_dir)/arch/x86/boot/bzImage | build
+build/Image: $(kernel_dir)/arch/x86/boot/bzImage | build/
 	cp $< $@
 
 else ifeq ($(CONFIG_LINUXBOOT_KERNEL_UIMAGE),y)
 
-build/target.dtb: $(CONFIG_LINUXBOOT_DTS_FILE) | build
+build/target.dtb: $(CONFIG_LINUXBOOT_DTS_FILE) | build/
 	$(DTC) -o $@ $<
 
-build/Image: build/vmlinux.bin.lzma build/initramfs build/target.dtb $(LINUX_ARCH-y)/kernel_fdt_lzma.its | build
+build/Image: build/vmlinux.bin.lzma build/initramfs build/target.dtb $(LINUX_ARCH-y)/kernel_fdt_lzma.its | build/
 	mkimage -f $(LINUX_ARCH-y)/kernel_fdt_lzma.its $@
 
 else ifneq ($(CONFIG_LINUXBOOT_COMPILE_KERNEL),y)
 
-build/Image: $(CONFIG_LINUXBOOT_KERNEL_PATH) | build
+build/Image: $(CONFIG_LINUXBOOT_KERNEL_PATH) | build/
 	cp $< $@
 
 endif
 
-build/initramfs: build/initramfs_u-root.cpio | build
+build/initramfs: build/initramfs_u-root.cpio | build/
 ifeq ($(CONFIG_LINUXBOOT_INITRAMFS_COMPRESSION_XZ),y)
 	xz --stdout --keep --force --check=crc32 --lzma2=dict=1MiB $< > $@
 else
 	cp $< $@
 endif
 
-build:
+build/:
 	mkdir build
 
 clean:
diff --git a/payloads/external/LinuxBoot/targets/linux.mk b/payloads/external/LinuxBoot/targets/linux.mk
index 5cd3c540e0..17ed9dd198 100644
--- a/payloads/external/LinuxBoot/targets/linux.mk
+++ b/payloads/external/LinuxBoot/targets/linux.mk
@@ -28,7 +28,7 @@ else ifeq ($(findstring x6.,x$(kernel_version)),x6.)
 kernel_mirror_path := $(kernel_mirror)/v6.x
 endif
 
-build/$(kernel_tarball).xz: | build
+build/$(kernel_tarball).xz: | build/
 	echo "    Test $(kernel_version)"
 	echo "    WWW        $(kernel_mirror_path)/$(kernel_tarball).xz";
 	curl -OLSs --output-dir build "$(kernel_mirror_path)/$(kernel_tarball).xz";
@@ -48,7 +48,7 @@ $(kernel_dir)/vmlinux : $(kernel_dir)/.config | $(kernel_dir)
 	echo "$(MAKE) -j $(CPUS) -C $(kernel_dir) $(KERNEL_MAKE_FLAGS) vmlinux"
 	$(MAKE) -j $(CPUS) -C $(kernel_dir) $(KERNEL_MAKE_FLAGS) vmlinux
 
-build/vmlinux.bin: $(kernel_dir)/vmlinux | build
+build/vmlinux.bin: $(kernel_dir)/vmlinux | build/
 	$(OBJCOPY) -O binary $< $@
 
 build/vmlinux.bin.lzma: build/vmlinux.bin

From 502d19be8990de31eba76dec2aae2a95a59557db Mon Sep 17 00:00:00 2001
From: Maximilian Brune <maximilian.brune@9elements.com>
Date: Sun, 25 May 2025 11:06:12 +0200
Subject: [PATCH 1599/3886] payloads/external/LinuxBoot/targets/u-root.mk: Add
 missing prerequisite

the build directory prerequisite was missing. As far as I know, it
didn't cause any issues, but it should still be there for correctness.

Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: Ieba578871af2fe886def059ab1568b85cd641e6e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87820
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
---
 payloads/external/LinuxBoot/targets/u-root.mk | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/payloads/external/LinuxBoot/targets/u-root.mk b/payloads/external/LinuxBoot/targets/u-root.mk
index 158a605f29..ddc09e15ba 100644
--- a/payloads/external/LinuxBoot/targets/u-root.mk
+++ b/payloads/external/LinuxBoot/targets/u-root.mk
@@ -35,7 +35,7 @@ ifeq ($(shell if [ $(go_version_minor) -lt 9 ]; then echo y; fi),y)
 endif
 endif
 
-$(uroot_build):
+$(uroot_build): | build/
 	git clone https://$(uroot_package) $(uroot_build)
 	git -C $(uroot_build) checkout --quiet $(CONFIG_LINUXBOOT_UROOT_VERSION)
 

From d233b6c9036f6b9105e31072a30df137c162479e Mon Sep 17 00:00:00 2001
From: Maximilian Brune <maximilian.brune@9elements.com>
Date: Sun, 25 May 2025 11:09:33 +0200
Subject: [PATCH 1600/3886] payloads/external/LinuxBoot/Makefile: Fix build
 prerequisite

Sometimes during build you could get this error:
mkdir: cannot create directory 'build': File exists
make[1]: *** [Makefile:48: build] Error 1
make: *** [payloads/external/Makefile.mk:408: payloads/external/LinuxBoot/build/initramfs] Erro
make: *** Waiting for unfinished jobs....
    Test 6.3
    WWW        https://mirrors.edge.kernel.org/pub/linux/kernel/v6.x/linux-6.3.tar.xz

Usually this should not happen, because the 'build' target is an
order-only prerequisite, but I assume its still happening, because the
makefile is called twice during a Linuxboot build. Once for the Linux
kernel and once again for the initramfs.

A quick and dirty fix is to add a '-p' to the mkdir command.

Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: I5663d1cb592bec6a8576347dd22223b382cd617f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87821
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 payloads/external/LinuxBoot/Makefile | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/payloads/external/LinuxBoot/Makefile b/payloads/external/LinuxBoot/Makefile
index c56e9fc635..64a8e1c331 100644
--- a/payloads/external/LinuxBoot/Makefile
+++ b/payloads/external/LinuxBoot/Makefile
@@ -45,7 +45,7 @@ else
 endif
 
 build/:
-	mkdir build
+	mkdir -p build
 
 clean:
 	rm -rf build/kernel*

From 5171098814e0f19c27cf2ae998116cab2af4cc53 Mon Sep 17 00:00:00 2001
From: Alper Nebi Yasak <alpernebiyasak@gmail.com>
Date: Tue, 5 Dec 2023 12:55:31 +0300
Subject: [PATCH 1601/3886] drivers/qemu/bochs: Allow building for non-x86
 architectures

The Bochs display driver uses port I/O functions to initialize the VGA
device, so it could only have been built on x86 architectures so far,
but its supported devices can be used just fine on others on the QEMU
side as long as the emulated platform supports PCI. A previous commit
adds port I/O functions for more including ARM* and RISC-V, which should
enable this driver to be successfully built and used on these as well.

Allow the Bochs display driver to be built for non-x86 QEMU boards by
changing the Kconfig dependencies. Make VGA text framebuffer support
depend on x86, because it isn't usable at the standard 0xB8000 address
on other architectures. Add a dependency on PCI since this is a PCI
device and vexpress-a9 (qemu-armv7) doesn't have the (emulated) hardware
for PCI.

Change-Id: I7f72d7ea13e54ecf89d067394c02b572c5f92d24
Signed-off-by: Alper Nebi Yasak <alpernebiyasak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80376
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
---
 src/drivers/emulation/qemu/Kconfig | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/src/drivers/emulation/qemu/Kconfig b/src/drivers/emulation/qemu/Kconfig
index cab06948f2..f319768bb6 100644
--- a/src/drivers/emulation/qemu/Kconfig
+++ b/src/drivers/emulation/qemu/Kconfig
@@ -3,9 +3,10 @@
 config DRIVERS_EMULATION_QEMU_BOCHS
 	bool "bochs dispi interface vga driver"
 	default y
-	depends on CPU_QEMU_X86
+	depends on PCI
+	depends on VENDOR_EMULATION
 	depends on MAINBOARD_DO_NATIVE_VGA_INIT
-	select HAVE_VGA_TEXT_FRAMEBUFFER
+	select HAVE_VGA_TEXT_FRAMEBUFFER if CPU_QEMU_X86
 	select HAVE_LINEAR_FRAMEBUFFER
 	select VGA
 	help

From 7100f226ca7d8b462680a89a74a40bc60128b924 Mon Sep 17 00:00:00 2001
From: alokagar <alok.agarwal@intel.com>
Date: Tue, 15 Jul 2025 13:00:59 +0530
Subject: [PATCH 1602/3886] vc/intel/fsp/fsp2_0/wcl: Add FSP headers for WCL
 FSP

Details:
- First set files to compile google/ocelot mainboard w.r.t. WCL FSP
  3266_02.
- Change file path for the FSP_HEADER_PATH for WildacatLake.

BUG=b:431683053
TEST=Build Ocelot without any errors.

Change-Id: Iec31b0055bc145d795adef6723511ac07f83406b
Signed-off-by: alokagar <alok.agarwal@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88433
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/soc/intel/pantherlake/Kconfig             |    1 +
 .../fsp2_0/wildcatlake/FirmwareVersionInfo.h  |   53 +
 .../wildcatlake/FspProducerDataHeader.h       |   81 +
 .../intel/fsp/fsp2_0/wildcatlake/FspUpd.h     |   48 +
 .../intel/fsp/fsp2_0/wildcatlake/FspmUpd.h    | 3075 +++++++++++++++++
 .../intel/fsp/fsp2_0/wildcatlake/FspsUpd.h    | 2426 +++++++++++++
 .../intel/fsp/fsp2_0/wildcatlake/MemInfoHob.h |  409 +++
 7 files changed, 6093 insertions(+)
 create mode 100644 src/vendorcode/intel/fsp/fsp2_0/wildcatlake/FirmwareVersionInfo.h
 create mode 100644 src/vendorcode/intel/fsp/fsp2_0/wildcatlake/FspProducerDataHeader.h
 create mode 100644 src/vendorcode/intel/fsp/fsp2_0/wildcatlake/FspUpd.h
 create mode 100644 src/vendorcode/intel/fsp/fsp2_0/wildcatlake/FspmUpd.h
 create mode 100644 src/vendorcode/intel/fsp/fsp2_0/wildcatlake/FspsUpd.h
 create mode 100644 src/vendorcode/intel/fsp/fsp2_0/wildcatlake/MemInfoHob.h

diff --git a/src/soc/intel/pantherlake/Kconfig b/src/soc/intel/pantherlake/Kconfig
index 585400759c..439cdc75f9 100644
--- a/src/soc/intel/pantherlake/Kconfig
+++ b/src/soc/intel/pantherlake/Kconfig
@@ -362,6 +362,7 @@ config CONSOLE_CBMEM_BUFFER_SIZE
 
 config FSP_HEADER_PATH
 	string "Location of FSP headers"
+	default "src/vendorcode/intel/fsp/fsp2_0/wildcatlake" if SOC_INTEL_WILDCATLAKE
 	default "src/vendorcode/intel/fsp/fsp2_0/pantherlake/"
 
 # Override platform debug consent value:
diff --git a/src/vendorcode/intel/fsp/fsp2_0/wildcatlake/FirmwareVersionInfo.h b/src/vendorcode/intel/fsp/fsp2_0/wildcatlake/FirmwareVersionInfo.h
new file mode 100644
index 0000000000..085b246b92
--- /dev/null
+++ b/src/vendorcode/intel/fsp/fsp2_0/wildcatlake/FirmwareVersionInfo.h
@@ -0,0 +1,53 @@
+/** @file
+  Intel Firmware Version Info (FVI) related definitions.
+
+  Copyright (c) 2024, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+  @par Specification Reference:
+  System Management BIOS (SMBIOS) Reference Specification v3.0.0 dated 2015-Feb-12
+  http://www.dmtf.org/sites/default/files/standards/documents/DSP0134_3.0.0.pdf
+
+**/
+
+#ifndef __FIRMWARE_VERSION_INFO_H__
+#define __FIRMWARE_VERSION_INFO_H__
+
+#include <IndustryStandard/SmBios.h>
+
+#define INTEL_FIRMWARE_VERSION_INFO_GROUP_NAME    "Firmware Version Info"
+#define INTEL_FVI_SMBIOS_TYPE                     0xDD
+
+#pragma pack(1)
+
+///
+/// Firmware Version Structure
+///
+typedef struct {
+  UINT8                       MajorVersion;
+  UINT8                       MinorVersion;
+  UINT8                       Revision;
+  UINT16                      BuildNumber;
+} INTEL_FIRMWARE_VERSION;
+
+///
+/// Firmware Version Info (FVI) Structure
+///
+typedef struct {
+  SMBIOS_TABLE_STRING         ComponentName;  ///< String Index of Component Name
+  SMBIOS_TABLE_STRING         VersionString;  ///< String Index of Version String
+  INTEL_FIRMWARE_VERSION      Version;        ///< Firmware version
+} INTEL_FIRMWARE_VERSION_INFO;
+
+///
+/// SMBIOS OEM Type Intel Firmware Version Info (FVI) Structure
+///
+typedef struct {
+  SMBIOS_STRUCTURE            Header;         ///< SMBIOS structure header
+  UINT8                       Count;          ///< Number of FVI entries in this structure
+  INTEL_FIRMWARE_VERSION_INFO Fvi[1];         ///< FVI structure(s)
+} SMBIOS_TABLE_TYPE_OEM_INTEL_FVI;
+
+#pragma pack()
+
+#endif
diff --git a/src/vendorcode/intel/fsp/fsp2_0/wildcatlake/FspProducerDataHeader.h b/src/vendorcode/intel/fsp/fsp2_0/wildcatlake/FspProducerDataHeader.h
new file mode 100644
index 0000000000..e939d23532
--- /dev/null
+++ b/src/vendorcode/intel/fsp/fsp2_0/wildcatlake/FspProducerDataHeader.h
@@ -0,0 +1,81 @@
+/** @file
+
+  Copyright (c) 2024, Intel Corporation. All rights reserved.<BR>
+  This program and the accompanying materials
+  are licensed and made available under the terms and conditions of the BSD License
+  which accompanies this distribution. The full text of the license may be found at
+  http://opensource.org/licenses/bsd-license.php
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+**/
+#ifndef _FSP_PRODUCER_DATA_HEADER_H_
+#define _FSP_PRODUCER_DATA_HEADER_H_
+
+#include <Guid/FspHeaderFile.h>
+
+#define BUILD_TIME_STAMP_SIZE 12
+
+//
+// FSP Header Data structure from FspHeader driver.
+//
+#pragma pack(1)
+///
+/// FSP Producer Data Subtype - 1
+///
+typedef struct {
+  ///
+  /// Byte 0x00: Length of this FSP producer data type record.
+  ///
+  UINT16  Length;
+  ///
+  /// Byte 0x02: FSP producer data type.
+  ///
+  UINT8   Type;
+  ///
+  /// Byte 0x03: Revision of this FSP producer data type.
+  ///
+  UINT8   Revision;
+  ///
+  /// Byte 0x04: 4 byte field of RC version which is used to build this FSP image.
+  ///
+  UINT32  RcVersion;
+  ///
+  /// Byte 0x08: Represents the build time stamp "YYYYMMDDHHMM".
+  ///
+  UINT8  BuildTimeStamp[BUILD_TIME_STAMP_SIZE];
+} FSP_PRODUCER_DATA_TYPE1;
+
+///
+/// FSP Producer Data Subtype - 2
+///
+typedef struct {
+  ///
+  /// Byte 0x00: Length of this FSP producer data type record.
+  ///
+  UINT16  Length;
+  ///
+  /// Byte 0x02: FSP producer data type.
+  ///
+  UINT8   Type;
+  ///
+  /// Byte 0x03: Revision of this FSP producer data type.
+  ///
+  UINT8   Revision;
+  ///
+  /// Byte 0x04: 4 byte field of Mrc version which is used to build this FSP image.
+  ///
+  UINT8  MrcVersion [4];
+} FSP_PRODUCER_DATA_TYPE2;
+
+
+typedef struct {
+  FSP_INFO_HEADER          FspInfoHeader;
+  FSP_INFO_EXTENDED_HEADER FspInfoExtendedHeader;
+  FSP_PRODUCER_DATA_TYPE1  FspProduceDataType1;
+  FSP_PRODUCER_DATA_TYPE2  FspProduceDataType2;
+  FSP_PATCH_TABLE          FspPatchTable;
+} FSP_PRODUCER_DATA_TABLES;
+#pragma pack()
+
+#endif // _FSP_PRODUCER_DATA_HEADER_H
diff --git a/src/vendorcode/intel/fsp/fsp2_0/wildcatlake/FspUpd.h b/src/vendorcode/intel/fsp/fsp2_0/wildcatlake/FspUpd.h
new file mode 100644
index 0000000000..9661285ef3
--- /dev/null
+++ b/src/vendorcode/intel/fsp/fsp2_0/wildcatlake/FspUpd.h
@@ -0,0 +1,48 @@
+/** @file
+
+Copyright (c) 2024, Intel Corporation. All rights reserved.<BR>
+
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+
+* Redistributions of source code must retain the above copyright notice, this
+  list of conditions and the following disclaimer.
+* Redistributions in binary form must reproduce the above copyright notice, this
+  list of conditions and the following disclaimer in the documentation and/or
+  other materials provided with the distribution.
+* Neither the name of Intel Corporation nor the names of its contributors may
+  be used to endorse or promote products derived from this software without
+  specific prior written permission.
+
+  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
+  THE POSSIBILITY OF SUCH DAMAGE.
+
+  This file is automatically generated. Please do NOT modify !!!
+
+**/
+
+#ifndef __FSPUPD_H__
+#define __FSPUPD_H__
+
+#include <FspEas.h>
+
+#pragma pack(1)
+
+#define FSPT_UPD_SIGNATURE               0x545F4450554C5450        /* 'PTLUPD_T' */
+
+#define FSPM_UPD_SIGNATURE               0x4D5F4450554C5450        /* 'PTLUPD_M' */
+
+#define FSPS_UPD_SIGNATURE               0x535F4450554C5450        /* 'PTLUPD_S' */
+
+#pragma pack()
+
+#endif
diff --git a/src/vendorcode/intel/fsp/fsp2_0/wildcatlake/FspmUpd.h b/src/vendorcode/intel/fsp/fsp2_0/wildcatlake/FspmUpd.h
new file mode 100644
index 0000000000..1d9868ca13
--- /dev/null
+++ b/src/vendorcode/intel/fsp/fsp2_0/wildcatlake/FspmUpd.h
@@ -0,0 +1,3075 @@
+/** @file
+
+Copyright (c) 2025, Intel Corporation. All rights reserved.<BR>
+
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+
+* Redistributions of source code must retain the above copyright notice, this
+  list of conditions and the following disclaimer.
+* Redistributions in binary form must reproduce the above copyright notice, this
+  list of conditions and the following disclaimer in the documentation and/or
+  other materials provided with the distribution.
+* Neither the name of Intel Corporation nor the names of its contributors may
+  be used to endorse or promote products derived from this software without
+  specific prior written permission.
+
+  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
+  THE POSSIBILITY OF SUCH DAMAGE.
+
+  This file is automatically generated. Please do NOT modify !!!
+
+**/
+
+#ifndef __FSPMUPD_H__
+#define __FSPMUPD_H__
+
+#include <FspUpd.h>
+
+#pragma pack(1)
+
+
+#include <MemInfoHob.h>
+
+///
+/// The ChipsetInit Info structure provides the information of ME ChipsetInit CRC and BIOS ChipsetInit CRC.
+///
+typedef struct {
+  UINT8             Revision;         ///< Chipset Init Info Revision
+  UINT8             Rsvd[3];          ///< Reserved
+  UINT16            MeChipInitCrc;    ///< 16 bit CRC value of MeChipInit Table
+  UINT16            BiosChipInitCrc;  ///< 16 bit CRC value of PchChipInit Table
+} CHIPSET_INIT_INFO;
+
+
+/** Fsp M Configuration
+**/
+typedef struct {
+
+/** Offset 0x0060 - Serial Io Uart Debug Mode
+  Select SerialIo Uart Controller mode
+  0:SerialIoUartDisabled, 1:SerialIoUartPci, 2:SerialIoUartHidden, 3:SerialIoUartCom,
+  4:SerialIoUartSkipInit
+**/
+  UINT8                       SerialIoUartDebugMode;
+
+/** Offset 0x0061 - Serial Io Uart Debug Auto Flow
+  Enables UART hardware flow control, CTS and RTS lines.
+  $EN_DIS
+**/
+  UINT8                       SerialIoUartDebugAutoFlow;
+
+/** Offset 0x0062 - Reserved
+**/
+  UINT8                       Reserved0[2];
+
+/** Offset 0x0064 - SerialIoUartDebugRxPinMux - FSPT
+  Select RX pin muxing for SerialIo UART used for debug
+**/
+  UINT32                      SerialIoUartDebugRxPinMux;
+
+/** Offset 0x0068 - SerialIoUartDebugTxPinMux - FSPM
+  Select TX pin muxing for SerialIo UART used for debug
+**/
+  UINT32                      SerialIoUartDebugTxPinMux;
+
+/** Offset 0x006C - SerialIoUartDebugRtsPinMux - FSPM
+  Select SerialIo Uart used for debug Rts pin muxing. Refer to GPIO_*_MUXING_SERIALIO_UARTx_RTS*
+  for possible values.
+**/
+  UINT32                      SerialIoUartDebugRtsPinMux;
+
+/** Offset 0x0070 - SerialIoUartDebugCtsPinMux - FSPM
+  Select SerialIo Uart used for debug Cts pin muxing. Refer to GPIO_*_MUXING_SERIALIO_UARTx_CTS*
+  for possible values.
+**/
+  UINT32                      SerialIoUartDebugCtsPinMux;
+
+/** Offset 0x0074 - Reserved
+**/
+  UINT8                       Reserved1;
+
+/** Offset 0x0075 - DCI Enable
+  Determine if to enable DCI debug from host
+  $EN_DIS
+**/
+  UINT8                       DciEn;
+
+/** Offset 0x0076 - DCI DbC Mode
+  Disabled: Clear both USB2/3DBCEN; USB2: set USB2DBCEN; USB3: set USB3DBCEN; Both:
+  Set both USB2/3DBCEN; No Change: Comply with HW value
+  0:Disabled, 1:USB2 DbC, 2:USB3 DbC, 3:Both, 4:No Change
+**/
+  UINT8                       DciDbcMode;
+
+/** Offset 0x0077 - Reserved
+**/
+  UINT8                       Reserved2[3];
+
+/** Offset 0x007A - Memory Test on Warm Boot
+  Run Base Memory Test on Warm Boot
+  0:Disable, 1:Enable
+**/
+  UINT8                       MemTestOnWarmBoot;
+
+/** Offset 0x007B - Reserved
+**/
+  UINT8                       Reserved3[5];
+
+/** Offset 0x0080 - Platform Reserved Memory Size
+  The minimum platform memory size required to pass control into DXE
+**/
+  UINT64                      PlatformMemorySize;
+
+/** Offset 0x0088 - SPD Data Length
+  Length of SPD Data
+  0x100:256 Bytes, 0x200:512 Bytes, 0x400:1024 Bytes
+**/
+  UINT16                      MemorySpdDataLen;
+
+/** Offset 0x008A - Reserved
+**/
+  UINT8                       Reserved4[6];
+
+/** Offset 0x0090 - Memory SPD Pointer Controller 0 Channel 0 Dimm 0
+  Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00
+**/
+  UINT64                      MemorySpdPtr000;
+
+/** Offset 0x0098 - Memory SPD Pointer Controller 0 Channel 0 Dimm 1
+  Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00
+**/
+  UINT64                      MemorySpdPtr001;
+
+/** Offset 0x00A0 - Memory SPD Pointer Controller 0 Channel 1 Dimm 0
+  Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00
+**/
+  UINT64                      MemorySpdPtr010;
+
+/** Offset 0x00A8 - Memory SPD Pointer Controller 0 Channel 1 Dimm 1
+  Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00
+**/
+  UINT64                      MemorySpdPtr011;
+
+/** Offset 0x00B0 - Memory SPD Pointer Controller 0 Channel 2 Dimm 0
+  Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00
+**/
+  UINT64                      MemorySpdPtr020;
+
+/** Offset 0x00B8 - Memory SPD Pointer Controller 0 Channel 2 Dimm 1
+  Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00
+**/
+  UINT64                      MemorySpdPtr021;
+
+/** Offset 0x00C0 - Memory SPD Pointer Controller 0 Channel 3 Dimm 0
+  Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00
+**/
+  UINT64                      MemorySpdPtr030;
+
+/** Offset 0x00C8 - Memory SPD Pointer Controller 0 Channel 3 Dimm 1
+  Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00
+**/
+  UINT64                      MemorySpdPtr031;
+
+/** Offset 0x00D0 - Memory SPD Pointer Controller 1 Channel 0 Dimm 0
+  Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00
+**/
+  UINT64                      MemorySpdPtr100;
+
+/** Offset 0x00D8 - Memory SPD Pointer Controller 1 Channel 0 Dimm 1
+  Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00
+**/
+  UINT64                      MemorySpdPtr101;
+
+/** Offset 0x00E0 - Memory SPD Pointer Controller 1 Channel 1 Dimm 0
+  Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00
+**/
+  UINT64                      MemorySpdPtr110;
+
+/** Offset 0x00E8 - Memory SPD Pointer Controller 1 Channel 1 Dimm 1
+  Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00
+**/
+  UINT64                      MemorySpdPtr111;
+
+/** Offset 0x00F0 - Memory SPD Pointer Controller 1 Channel 2 Dimm 0
+  Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00
+**/
+  UINT64                      MemorySpdPtr120;
+
+/** Offset 0x00F8 - Memory SPD Pointer Controller 1 Channel 2 Dimm 1
+  Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00
+**/
+  UINT64                      MemorySpdPtr121;
+
+/** Offset 0x0100 - Memory SPD Pointer Controller 1 Channel 3 Dimm 0
+  Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00
+**/
+  UINT64                      MemorySpdPtr130;
+
+/** Offset 0x0108 - Memory SPD Pointer Controller 1 Channel 3 Dimm 1
+  Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00
+**/
+  UINT64                      MemorySpdPtr131;
+
+/** Offset 0x0110 - RcompResistor settings
+  Indicates  RcompResistor settings: Board-dependent
+**/
+  UINT16                      RcompResistor;
+
+/** Offset 0x0112 - RcompTarget settings
+  RcompTarget settings: board-dependent
+**/
+  UINT16                      RcompTarget[5];
+
+/** Offset 0x011C - Dqs Map CPU to DRAM MC 0 CH 0
+  Set Dqs mapping relationship between CPU and DRAM, Channel 0: board-dependent
+**/
+  UINT8                       DqsMapCpu2DramMc0Ch0[2];
+
+/** Offset 0x011E - Dqs Map CPU to DRAM MC 0 CH 1
+  Set Dqs mapping relationship between CPU and DRAM, Channel 1: board-dependent
+**/
+  UINT8                       DqsMapCpu2DramMc0Ch1[2];
+
+/** Offset 0x0120 - Dqs Map CPU to DRAM MC 0 CH 2
+  Set Dqs mapping relationship between CPU and DRAM, Channel 2: board-dependent
+**/
+  UINT8                       DqsMapCpu2DramMc0Ch2[2];
+
+/** Offset 0x0122 - Dqs Map CPU to DRAM MC 0 CH 3
+  Set Dqs mapping relationship between CPU and DRAM, Channel 3: board-dependent
+**/
+  UINT8                       DqsMapCpu2DramMc0Ch3[2];
+
+/** Offset 0x0124 - Dqs Map CPU to DRAM MC 1 CH 0
+  Set Dqs mapping relationship between CPU and DRAM, Channel 0: board-dependent
+**/
+  UINT8                       DqsMapCpu2DramMc1Ch0[2];
+
+/** Offset 0x0126 - Dqs Map CPU to DRAM MC 1 CH 1
+  Set Dqs mapping relationship between CPU and DRAM, Channel 1: board-dependent
+**/
+  UINT8                       DqsMapCpu2DramMc1Ch1[2];
+
+/** Offset 0x0128 - Dqs Map CPU to DRAM MC 1 CH 2
+  Set Dqs mapping relationship between CPU and DRAM, Channel 2: board-dependent
+**/
+  UINT8                       DqsMapCpu2DramMc1Ch2[2];
+
+/** Offset 0x012A - Dqs Map CPU to DRAM MC 1 CH 3
+  Set Dqs mapping relationship between CPU and DRAM, Channel 3: board-dependent
+**/
+  UINT8                       DqsMapCpu2DramMc1Ch3[2];
+
+/** Offset 0x012C - Dq Map CPU to DRAM MC 0 CH 0
+  Set Dq mapping relationship between CPU and DRAM, Channel 0: board-dependent
+**/
+  UINT8                       DqMapCpu2DramMc0Ch0[16];
+
+/** Offset 0x013C - Dq Map CPU to DRAM MC 0 CH 1
+  Set Dq mapping relationship between CPU and DRAM, Channel 1: board-dependent
+**/
+  UINT8                       DqMapCpu2DramMc0Ch1[16];
+
+/** Offset 0x014C - Dq Map CPU to DRAM MC 0 CH 2
+  Set Dq mapping relationship between CPU and DRAM, Channel 2: board-dependent
+**/
+  UINT8                       DqMapCpu2DramMc0Ch2[16];
+
+/** Offset 0x015C - Dq Map CPU to DRAM MC 0 CH 3
+  Set Dq mapping relationship between CPU and DRAM, Channel 3: board-dependent
+**/
+  UINT8                       DqMapCpu2DramMc0Ch3[16];
+
+/** Offset 0x016C - Dq Map CPU to DRAM MC 1 CH 0
+  Set Dq mapping relationship between CPU and DRAM, Channel 0: board-dependent
+**/
+  UINT8                       DqMapCpu2DramMc1Ch0[16];
+
+/** Offset 0x017C - Dq Map CPU to DRAM MC 1 CH 1
+  Set Dq mapping relationship between CPU and DRAM, Channel 1: board-dependent
+**/
+  UINT8                       DqMapCpu2DramMc1Ch1[16];
+
+/** Offset 0x018C - Dq Map CPU to DRAM MC 1 CH 2
+  Set Dq mapping relationship between CPU and DRAM, Channel 2: board-dependent
+**/
+  UINT8                       DqMapCpu2DramMc1Ch2[16];
+
+/** Offset 0x019C - Dq Map CPU to DRAM MC 1 CH 3
+  Set Dq mapping relationship between CPU and DRAM, Channel 3: board-dependent
+**/
+  UINT8                       DqMapCpu2DramMc1Ch3[16];
+
+/** Offset 0x01AC - LowerBasicMemTestSize
+  Reduce BasicMemTest size. 0: Disabled (default), regular BasicMemTest. 1: Enabled,
+  shorter BasicMemTest (faster boot)
+  $EN_DIS
+**/
+  UINT8                       LowerBasicMemTestSize;
+
+/** Offset 0x01AD - Reserved
+**/
+  UINT8                       Reserved5[2];
+
+/** Offset 0x01AF - CaVrefHigh
+  DDR5 CA Sweep High Vref Value for DDR5 OC
+**/
+  UINT8                       CaVrefHigh;
+
+/** Offset 0x01B0 - CaVrefLow
+  DDR5 CA Sweep Low Vref Value for DDR5 OC
+**/
+  UINT8                       CaVrefLow;
+
+/** Offset 0x01B1 - CsVrefHigh
+  DDR5 CS Sweep High Vref Value for DDR5 OC
+**/
+  UINT8                       CsVrefHigh;
+
+/** Offset 0x01B2 - CsVrefLow
+  DDR5 CS Sweep Low Vref Value for DDR5 OC
+**/
+  UINT8                       CsVrefLow;
+
+/** Offset 0x01B3 - DIMM DFE Tap1 Step Size
+  DIMM DFE Tap1 Step Size for DDR5 OC
+**/
+  UINT8                       DFETap1StepSize;
+
+/** Offset 0x01B4 - DIMM DFE Tap2 Step Size
+  DIMM DFE Tap2 Step Size for DDR5 OC
+**/
+  UINT8                       DFETap2StepSize;
+
+/** Offset 0x01B5 - Reserved
+**/
+  UINT8                       Reserved6;
+
+/** Offset 0x01B6 - VDD2 override
+  VDD2 override for DDR5 OC; 0 - Auto
+**/
+  UINT16                      Vdd2Mv;
+
+/** Offset 0x01B8 - tRAS
+  RAS Active Time, 0: AUTO, max: 65535. Only used if FspmUpd->FspmConfig.SpdProfileSelected
+  == 1 (Custom Profile).
+**/
+  UINT16                      tRAS;
+
+/** Offset 0x01BA - tRCD/tRP
+  RAS to CAS delay time and Row Precharge delay time, 0: AUTO, max: 255. Only used
+  if FspmUpd->FspmConfig.SpdProfileSelected == 1 (Custom Profile).
+**/
+  UINT16                      tRCDtRP;
+
+/** Offset 0x01BC - tREFI
+  Refresh Interval, 0: AUTO, max: 65535. Only used if FspmUpd->FspmConfig.SpdProfileSelected
+  == 1 (Custom Profile).
+**/
+  UINT32                      tREFI;
+
+/** Offset 0x01C0 - tCL
+  CAS Latency, 0: AUTO, max: 255. Only used if FspmUpd->FspmConfig.SpdProfileSelected
+  == 1 (Custom Profile).
+**/
+  UINT16                      tCL;
+
+/** Offset 0x01C2 - tCWL
+  Min CAS Write Latency Delay Time, 0: AUTO, max: 255. Only used if FspmUpd->FspmConfig.SpdProfileSelected
+  == 1 (Custom Profile).
+**/
+  UINT16                      tCWL;
+
+/** Offset 0x01C4 - tFAW
+  Min Four Activate Window Delay Time, 0: AUTO, max: 65535. Only used if FspmUpd->FspmConfig.SpdProfileSelected
+  == 1 (Custom Profile).
+**/
+  UINT16                      tFAW;
+
+/** Offset 0x01C6 - tRFC
+  Min Refresh Recovery Delay Time, 0: AUTO, max: 65535. Only used if FspmUpd->FspmConfig.SpdProfileSelected
+  == 1 (Custom Profile).
+**/
+  UINT16                      tRFC;
+
+/** Offset 0x01C8 - tRRD
+  Min Row Active to Row Active Delay Time, 0: AUTO, max: 255. Only used if FspmUpd->FspmConfig.SpdProfileSelected
+  == 1 (Custom Profile).
+**/
+  UINT16                      tRRD;
+
+/** Offset 0x01CA - tRTP
+  Min Internal Read to Precharge Command Delay Time, 0: AUTO, max: 255. Only used
+  if FspmUpd->FspmConfig.SpdProfileSelected == 1 (Custom Profile).
+**/
+  UINT16                      tRTP;
+
+/** Offset 0x01CC - tWR
+  Min Write Recovery Time, 0: AUTO, legal values: 5, 6, 7, 8, 10, 12, 14, 16, 18,
+  20, 24, 30, 34, 40. Only used if FspmUpd->FspmConfig.SpdProfileSelected == 1 (Custom Profile).
+  0:Auto, 5:5, 6:6, 7:7, 8:8, 10:10, 12:12, 14:14, 16:16, 18:18, 20:20, 24:24, 30:30,
+  34:34, 40:40
+**/
+  UINT16                      tWR;
+
+/** Offset 0x01CE - tWTR
+  Min Internal Write to Read Command Delay Time, 0: AUTO, max: 255. Only used if FspmUpd->FspmConfig.SpdProfileSelected
+  == 1 (Custom Profile).
+**/
+  UINT16                      tWTR;
+
+/** Offset 0x01D0 - tWTR_S
+  tWTR_S value for OC Custom Profile, 0 - Auto
+**/
+  UINT16                      tWTR_S;
+
+/** Offset 0x01D2 - tWTR_L
+  tWTR_L value for OC Custom Profile, 0 - Auto
+**/
+  UINT16                      tWTR_L;
+
+/** Offset 0x01D4 - tCCD_L
+  tCCD_L value for OC Custom Profile, 0 - Auto
+**/
+  UINT16                      tCCD_L;
+
+/** Offset 0x01D6 - tRRD_S
+  tRRD_S value for OC Custom Profile, 0 - Auto
+**/
+  UINT16                      tRRD_S;
+
+/** Offset 0x01D8 - tRRD_L
+  tRRD_L value for OC Custom Profile, 0 - Auto
+**/
+  UINT16                      tRRD_L;
+
+/** Offset 0x01DA - tRFC4
+  tRFC4 value for OC Custom Profile, 0 - Auto
+**/
+  UINT16                      tRFC4;
+
+/** Offset 0x01DC - tRFC2
+  tRFC2 value for OC Custom Profile, 0 - Auto
+**/
+  UINT16                      tRFC2;
+
+/** Offset 0x01DE - tRFCpb
+  tRFCpb value for OC Custom Profile, 0 - Auto
+**/
+  UINT16                      tRFCpb;
+
+/** Offset 0x01E0 - tCCD_L_WR
+  Number of tCK cycles for the channel DIMM's minimum Write-to-Write delay for same
+  bank groups, for OC Custom Profile, 0 - Auto
+**/
+  UINT16                      tCCD_L_WR;
+
+/** Offset 0x01E2 - Reserved
+**/
+  UINT8                       Reserved7[2];
+
+/** Offset 0x01E4 - LPMode Support
+  Bit[0]: Enable Lpmode0p5 (Idle_enable), Bit[1]: Enable Lpmode2 (Powerdown_enable),
+  Bit[2]: Enable Lpmode3 (Selfrefresh_enable)
+**/
+  UINT8                       LpMode;
+
+/** Offset 0x01E5 - Reserved
+**/
+  UINT8                       Reserved8[2];
+
+/** Offset 0x01E7 - MRC OCSafeMode
+  OverClocking Safe Mode for tCL
+  $EN_DIS
+**/
+  UINT8                       OCSafeMode;
+
+/** Offset 0x01E8 - Reserved
+**/
+  UINT8                       Reserved9;
+
+/** Offset 0x01E9 - Dqs Pins Interleaved Setting
+  Indicates DqPinsInterleaved setting: board-dependent
+  $EN_DIS
+**/
+  UINT8                       DqPinsInterleaved;
+
+/** Offset 0x01EA - Smram Mask
+  The SMM Regions AB-SEG and/or H-SEG reserved
+  0: Neither, 1:AB-SEG, 2:H-SEG, 3: Both
+**/
+  UINT8                       SmramMask;
+
+/** Offset 0x01EB - MRC Fast Boot
+  Enables/Disable the MRC fast path thru the MRC
+  $EN_DIS
+**/
+  UINT8                       MrcFastBoot;
+
+/** Offset 0x01EC - Rank Margin Tool per Task
+  This option enables the user to execute Rank Margin Tool per major training step
+  in the MRC.
+  $EN_DIS
+**/
+  UINT8                       RmtPerTask;
+
+/** Offset 0x01ED - Training Trace
+  This option enables the trained state tracing feature in MRC.  This feature will
+  print out the key training parameters state across major training steps.
+  $EN_DIS
+**/
+  UINT8                       TrainTrace;
+
+/** Offset 0x01EE - Probeless Trace
+  Probeless Trace: 0=Disabled, 1=Enable. Enabling Probeless Trace will reserve 128MB.
+  This also requires IED to be enabled.
+  $EN_DIS
+**/
+  UINT8                       ProbelessTrace;
+
+/** Offset 0x01EF - Reserved
+**/
+  UINT8                       Reserved10;
+
+/** Offset 0x01F0 - DDR Frequency Limit
+  Maximum Memory Frequency Selections in Mhz. Options are 1067, 1333, 1600, 1867,
+  2133, 2400, 2667, 2933 and 0 for Auto.
+  1067:1067, 1333:1333, 1600:1600, 1867:1867, 2133:2133, 2400:2400, 2667:2667, 2933:2933, 0:Auto
+**/
+  UINT16                      DdrFreqLimit;
+
+/** Offset 0x01F2 - SAGV
+  System Agent dynamic frequency support.
+  0:Disabled, 1:Enabled
+**/
+  UINT8                       SaGv;
+
+/** Offset 0x01F3 - SAGV WP Mask
+  System Agent dynamic frequency workpoints that memory will be training at the enabled
+  frequencies.
+  0x3:Points0_1, 0x7:Points0_1_2, 0xF:AllPoints0_1_2_3
+**/
+  UINT8                       SaGvWpMask;
+
+/** Offset 0x01F4 - SAGV Gear Ratio
+  Gear Selection for SAGV points. 0 - Auto, 1-1 Gear 1, 2-Gear 2
+**/
+  UINT8                       SaGvGear[4];
+
+/** Offset 0x01F8 - SAGV Frequency
+  SAGV Frequency per point in Mhz. 0 for Auto and a ratio of 133/100MHz: 1333/1300.
+**/
+  UINT16                      SaGvFreq[4];
+
+/** Offset 0x0200 - SAGV Disabled Gear Ratio
+  Gear Selection for SAGV Disabled. 0 - Auto, 1-1 Gear 1, 2-Gear 2
+**/
+  UINT8                       GearRatio;
+
+/** Offset 0x0201 - Rank Margin Tool
+  Enable/disable Rank Margin Tool.
+  $EN_DIS
+**/
+  UINT8                       RMT;
+
+/** Offset 0x0202 - Controller 0 Channel 0 DIMM Control
+  Enable / Disable DIMMs on Controller 0 Channel 0
+  $EN_DIS
+**/
+  UINT8                       DisableMc0Ch0;
+
+/** Offset 0x0203 - Controller 0 Channel 1 DIMM Control
+  Enable / Disable DIMMs on Controller 0 Channel 1
+  $EN_DIS
+**/
+  UINT8                       DisableMc0Ch1;
+
+/** Offset 0x0204 - Controller 0 Channel 2 DIMM Control
+  Enable / Disable DIMMs on Controller 0 Channel 2
+  $EN_DIS
+**/
+  UINT8                       DisableMc0Ch2;
+
+/** Offset 0x0205 - Controller 0 Channel 3 DIMM Control
+  Enable / Disable DIMMs on Controller 0 Channel 3
+  $EN_DIS
+**/
+  UINT8                       DisableMc0Ch3;
+
+/** Offset 0x0206 - Controller 1 Channel 0 DIMM Control
+  Enable / Disable DIMMs on Controller 1 Channel 0
+  $EN_DIS
+**/
+  UINT8                       DisableMc1Ch0;
+
+/** Offset 0x0207 - Controller 1 Channel 1 DIMM Control
+  Enable / Disable DIMMs on Controller 1 Channel 1
+  $EN_DIS
+**/
+  UINT8                       DisableMc1Ch1;
+
+/** Offset 0x0208 - Controller 1 Channel 2 DIMM Control
+  Enable / Disable DIMMs on Controller 1 Channel 2
+  $EN_DIS
+**/
+  UINT8                       DisableMc1Ch2;
+
+/** Offset 0x0209 - Controller 1 Channel 3 DIMM Control
+  Enable / Disable DIMMs on Controller 1 Channel 3
+  $EN_DIS
+**/
+  UINT8                       DisableMc1Ch3;
+
+/** Offset 0x020A - Scrambler Support
+  This option enables data scrambling in memory.
+  $EN_DIS
+**/
+  UINT8                       ScramblerSupport;
+
+/** Offset 0x020B - Memory Slice Hash Override
+  Memory Slice (Controller) Hash Mask and LSB Override. 0 = Use default memory slice
+  hash mask / lsb, 1 = Use values from MsHashMask and MsHashInterleaveBit
+  $EN_DIS
+**/
+  UINT8                       MsHashOverride;
+
+/** Offset 0x020C - Memory Voltage
+  DRAM voltage (Vdd) (supply voltage for input buffers and core logic of the DRAM
+  chips) in millivolts. <b>0=Platform Default (no override)</b>, 1200=1.2V, 1350=1.35V etc.
+  0:Default, 1200:1.20 Volts, 1250:1.25 Volts, 1300:1.30 Volts, 1350:1.35 Volts, 1400:1.40
+  Volts, 1450:1.45 Volts, 1500:1.50 Volts, 1550:1.55 Volts, 1600:1.60 Volts, 1650:1.65 Volts
+**/
+  UINT16                      VddVoltage;
+
+/** Offset 0x020E - Memory Ratio
+  Automatic or the frequency will equal ratio times reference clock. Set to Auto to
+  recalculate memory timings listed below.
+  0:Auto, 4:4, 5:5, 6:6, 7:7, 8:8, 9:9, 10:10, 11:11, 12:12, 13:13, 14:14, 15:15
+**/
+  UINT16                      Ratio;
+
+/** Offset 0x0210 - SPD Profile Selected
+  Select DIMM timing profile. Options are 0=Default Profile, 1=Custom Profile, 2=XMP
+  Profile 1, 3=XMP Profile 2
+  0:Default Profile, 1:Custom Profile, 2:XMP Profile 1, 3:XMP Profile 2
+**/
+  UINT8                       SpdProfileSelected;
+
+/** Offset 0x0211 - RxVref Per-Bit Training
+  Enable/Disable RxVref Per-Bit Training
+  $EN_DIS
+**/
+  UINT8                       RXVREFPERBIT;
+
+/** Offset 0x0212 - TXDQS DCC Training
+  Enables/Disable TXDQS DCC Training
+  $EN_DIS
+**/
+  UINT8                       TXDQSDCC;
+
+/** Offset 0x0213 - Reserved
+**/
+  UINT8                       Reserved11;
+
+/** Offset 0x0214 - Ch Hash Override
+  Select if Channel Hash setting values will be taken from input parameters or automatically
+  taken from POR values depending on DRAM type detected. NOTE: ONLY if Memory interleaved Mode
+  $EN_DIS
+**/
+  UINT8                       ChHashOverride;
+
+/** Offset 0x0215 - Reserved
+**/
+  UINT8                       Reserved12[2];
+
+/** Offset 0x0217 - DQS Rise/Fall
+  Enables/Disable DQS Rise/Fall
+  $EN_DIS
+**/
+  UINT8                       RDDQSODTT;
+
+/** Offset 0x0218 - Reserved
+**/
+  UINT8                       Reserved13[2];
+
+/** Offset 0x021A - Functional Duty Cycle Correction for DDR5 CLK
+  Enable/Disable Functional Duty Cycle Correction for DDR5 CLK
+  0:Disable, 1:Enable
+**/
+  UINT8                       FUNCDCCCLK;
+
+/** Offset 0x021B - Functional Duty Cycle Correction for DDR5 DQS
+  Enable/Disable Functional Duty Cycle Correction for DDR5 DQS
+  0:Disable, 1:Enable
+**/
+  UINT8                       FUNCDCCDQS;
+
+/** Offset 0x021C
+**/
+  UINT8                       FUNCDCCWCK;
+
+/** Offset 0x021D - Duty Cycle Correction for LP5 DCA
+  Enable/Disable Duty Cycle Correction for LP5 DCA
+  $EN_DIS
+**/
+  UINT8                       DCCLP5WCKDCA;
+
+/** Offset 0x021E - DQ/DQS Swizzle Training
+  Enable/Disable DQ/DQS Swizzle Training
+  $EN_DIS
+**/
+  UINT8                       DQDQSSWZ;
+
+/** Offset 0x021F - Reserved
+**/
+  UINT8                       Reserved14;
+
+/** Offset 0x0220 - Functional Duty Cycle Correction for Data DQ
+  Enable/Disable Functional Duty Cycle Correction for Data DQ
+  0:Disable, 1:Enable
+**/
+  UINT8                       FUNCDCCDQ;
+
+/** Offset 0x0221 - Reserved
+**/
+  UINT8                       Reserved15[5];
+
+/** Offset 0x0226 - Unmatched Rx Calibration
+  Enable/Disable Rx Unmatched Calibration
+  $EN_DIS
+**/
+  UINT8                       RXUNMATCHEDCAL;
+
+/** Offset 0x0227 - Reserved
+**/
+  UINT8                       Reserved16[10];
+
+/** Offset 0x0231 - Memory Slice Hash LSB Bit
+  Memory Slice (Controller) Hash LSB bit. Valid values are 0..7 for BITS 6..13; used
+  when MsHashOverride is set
+  0:BIT6, 1:BIT7, 2:BIT8, 3:BIT9, 4:BIT10, 5:BIT11, 6:BIT12, 7:BIT13
+**/
+  UINT8                       MsHashInterleaveBit;
+
+/** Offset 0x0232 - Memory Slice Hash Mask
+  Memory Slice (Controller) Hash Mask: 0x0001=BIT6 set(Minimal), 0x3FFF=BIT[19:6]
+  set(Maximum); used when MsHashOverride is set
+**/
+  UINT16                      MsHashMask;
+
+/** Offset 0x0234 - Reserved
+**/
+  UINT8                      Reserved17[13];
+
+/** Offset 0x0241 - LVR Auto Trim
+  Enable/disable LVR Auto Trim
+  $EN_DIS
+**/
+  UINT8                       LVRAUTOTRIM;
+
+/** Offset 0x0242 - Compensation Optimization
+  Enable/Disable Compensation Optimization
+  $EN_DIS
+**/
+  UINT8                       OPTIMIZECOMP;
+
+/** Offset 0x0243 - Write DQ/DQS Retraining
+  Enable/Disable Write DQ/DQS Retraining
+  $EN_DIS
+**/
+  UINT8                       WRTRETRAIN;
+
+/** Offset 0x0244 - Reserved
+**/
+  UINT8                       Reserved18[3];
+
+/** Offset 0x0247 - RDDQODTT
+  Enable/disable Read DQ ODT Training
+  $EN_DIS
+**/
+  UINT8                       RDDQODTT;
+
+/** Offset 0x0248 - RDCTLET
+  Enable/disable Read CTLE Training
+  $EN_DIS
+**/
+  UINT8                       RDCTLET;
+
+/** Offset 0x0249 - RxVref Pre EMPHASIS Training
+  Enable/Disable Pre EMPHASIS Training
+  $EN_DIS
+**/
+  UINT8                       EMPHASIS;
+
+/** Offset 0x024A - RX DQS VOC Centring Training
+  Enable/Disable RX DQS VOC Centring Training
+  $EN_DIS
+**/
+  UINT8                       RXDQSVOCC;
+
+/** Offset 0x024B - NMode
+  System command rate, range 0-2, 0 means auto, 1 = 1N, 2 = 2N
+**/
+  UINT8                       NModeSupport;
+
+/** Offset 0x024C - LPDDR ODT RttWr
+  Initial RttWr for LP4/5 in Ohms. 0x0 - Auto
+**/
+  UINT8                       LpddrRttWr;
+
+/** Offset 0x024D - Retrain on Fast flow Failure
+  Restart MRC in Cold mode if SW MemTest fails during Fast flow.
+  $EN_DIS
+**/
+  UINT8                       RetrainOnFastFail;
+
+/** Offset 0x024E - LPDDR ODT RttCa
+  Initial RttCa for LP4/5 in Ohms. 0x0 - Auto
+**/
+  UINT8                       LpddrRttCa;
+
+/** Offset 0x024F - DIMM DFE Training
+  Enable/Disable DIMM DFE Training
+  $EN_DIS
+**/
+  UINT8                       WRTDIMMDFE;
+
+/** Offset 0x0250 - DDR5 ODT Timing Config
+  Enable/Disable DDR5 ODT TIMING CONFIG
+  $EN_DIS
+**/
+  UINT8                       DDR5ODTTIMING;
+
+/** Offset 0x0251 - HobBufferSize
+  Size to set HOB Buffer. 0:Default, 1: 1 Byte, 2: 1 KB, 3: Max value(assuming 63KB
+  total HOB size).
+  0:Default, 1: 1 Byte, 2: 1 KB, 3: Max value
+**/
+  UINT8                       HobBufferSize;
+
+/** Offset 0x0252 - Early Command Training
+  Enables/Disable Early Command Training
+  $EN_DIS
+**/
+  UINT8                       ECT;
+
+/** Offset 0x0253 - SenseAmp Offset Training
+  Enables/Disable SenseAmp Offset Training
+  $EN_DIS
+**/
+  UINT8                       SOT;
+
+/** Offset 0x0254 - Early ReadMPR Timing Centering 2D
+  Enables/Disable Early ReadMPR Timing Centering 2D
+  $EN_DIS
+**/
+  UINT8                       ERDMPRTC2D;
+
+/** Offset 0x0255 - Read MPR Training
+  Enables/Disable Read MPR Training
+  $EN_DIS
+**/
+  UINT8                       RDMPRT;
+
+/** Offset 0x0256 - Receive Enable Training
+  Enables/Disable Receive Enable Training
+  $EN_DIS
+**/
+  UINT8                       RCVET;
+
+/** Offset 0x0257 - Jedec Write Leveling
+  Enables/Disable Jedec Write Leveling
+  $EN_DIS
+**/
+  UINT8                       JWRL;
+
+/** Offset 0x0258 - Early Write Time Centering 2D
+  Enables/Disable Early Write Time Centering 2D
+  $EN_DIS
+**/
+  UINT8                       EWRTC2D;
+
+/** Offset 0x0259 - Early Read Time Centering 2D
+  Enables/Disable Early Read Time Centering 2D
+  $EN_DIS
+**/
+  UINT8                       ERDTC2D;
+
+/** Offset 0x025A - Unmatched Write Time Centering 1D
+  Enable/Disable Unmatched Write Time Centering 1D
+  $EN_DIS
+**/
+  UINT8                       UNMATCHEDWRTC1D;
+
+/** Offset 0x025B - Write Timing Centering 1D
+  Enables/Disable Write Timing Centering 1D
+  $EN_DIS
+**/
+  UINT8                       WRTC1D;
+
+/** Offset 0x025C - Write Voltage Centering 1D
+  Enables/Disable Write Voltage Centering 1D
+  $EN_DIS
+**/
+  UINT8                       WRVC1D;
+
+/** Offset 0x025D - Read Timing Centering 1D
+  Enables/Disable Read Timing Centering 1D
+  $EN_DIS
+**/
+  UINT8                       RDTC1D;
+
+/** Offset 0x025E - Dimm ODT Training
+  Enables/Disable Dimm ODT Training
+  $EN_DIS
+**/
+  UINT8                       DIMMODTT;
+
+/** Offset 0x025F - DIMM RON Training
+  Enables/Disable DIMM RON Training
+  $EN_DIS
+**/
+  UINT8                       DIMMRONT;
+
+/** Offset 0x0260 - Write Drive Strength/Equalization 2D
+  Enables/Disable Write Drive Strength/Equalization 2D
+  $EN_DIS
+**/
+  UINT8                       WRDSEQT;
+
+/** Offset 0x0261 - Read Equalization Training
+  Enables/Disable Read Equalization Training
+  $EN_DIS
+**/
+  UINT8                       RDEQT;
+
+/** Offset 0x0262 - Write Timing Centering 2D
+  Enables/Disable Write Timing Centering 2D
+  $EN_DIS
+**/
+  UINT8                       WRTC2D;
+
+/** Offset 0x0263 - Read Timing Centering 2D
+  Enables/Disable Read Timing Centering 2D
+  $EN_DIS
+**/
+  UINT8                       RDTC2D;
+
+/** Offset 0x0264 - Write Voltage Centering 2D
+  Enables/Disable Write Voltage Centering 2D
+  $EN_DIS
+**/
+  UINT8                       WRVC2D;
+
+/** Offset 0x0265 - Read Voltage Centering 2D
+  Enables/Disable Read Voltage Centering 2D
+  $EN_DIS
+**/
+  UINT8                       RDVC2D;
+
+/** Offset 0x0266 - Command Voltage Centering
+  Enables/Disable Command Voltage Centering
+  $EN_DIS
+**/
+  UINT8                       CMDVC;
+
+/** Offset 0x0267 - Late Command Training
+  Enables/Disable Late Command Training
+  $EN_DIS
+**/
+  UINT8                       LCT;
+
+/** Offset 0x0268 - Round Trip Latency Training
+  Enables/Disable Round Trip Latency Training
+  $EN_DIS
+**/
+  UINT8                       RTL;
+
+/** Offset 0x0269 - Turn Around Timing Training
+  Enables/Disable Turn Around Timing Training
+  $EN_DIS
+**/
+  UINT8                       TAT;
+
+/** Offset 0x026A - Reserved
+**/
+  UINT8                       Reserved19;
+
+/** Offset 0x026B - DIMM SPD Alias Test
+  Enables/Disable DIMM SPD Alias Test
+  $EN_DIS
+**/
+  UINT8                       ALIASCHK;
+
+/** Offset 0x026C - Receive Enable Centering 1D
+  Enables/Disable Receive Enable Centering 1D
+  $EN_DIS
+**/
+  UINT8                       RCVENC1D;
+
+/** Offset 0x026D - Retrain Margin Check
+  Enables/Disable Retrain Margin Check
+  $EN_DIS
+**/
+  UINT8                       RMC;
+
+/** Offset 0x026E - ECC Support
+  Enables/Disable ECC Support
+  $EN_DIS
+**/
+  UINT8                       EccSupport;
+
+/** Offset 0x026F - Reserved
+**/
+  UINT8                       Reserved20[2];
+
+/** Offset 0x0271 - Ibecc
+  In-Band ECC Support
+  $EN_DIS
+**/
+  UINT8                       Ibecc;
+
+/** Offset 0x0272 - IbeccParity
+  In-Band ECC Parity Control
+  $EN_DIS
+**/
+  UINT8                       IbeccParity;
+
+/** Offset 0x0273 - Reserved
+**/
+  UINT8                       Reserved21;
+
+/** Offset 0x0274 - IbeccOperationMode
+  In-Band ECC Operation Mode
+  0:Protect base on address range, 1: Non-protected, 2: All protected
+**/
+  UINT8                       IbeccOperationMode;
+
+/** Offset 0x0275 - IbeccProtectedRegionEnable
+  In-Band ECC Protected Region Enable
+  $EN_DIS
+**/
+  UINT8                       IbeccProtectedRegionEnable[8];
+
+/** Offset 0x027D - Reserved
+**/
+  UINT8                       Reserved22;
+
+/** Offset 0x027E - IbeccProtectedRegionBases
+  IBECC Protected Region Bases per IBECC instance
+**/
+  UINT16                      IbeccProtectedRegionBase[8];
+
+/** Offset 0x028E - IbeccProtectedRegionMasks
+  IBECC Protected Region Masks
+**/
+  UINT16                      IbeccProtectedRegionMask[8];
+
+/** Offset 0x029E - Memory Remap
+  Enables/Disable Memory Remap
+  $EN_DIS
+**/
+  UINT8                       RemapEnable;
+
+/** Offset 0x029F - Rank Interleave support
+  Enables/Disable Rank Interleave support. NOTE: RI and HORI can not be enabled at
+  the same time.
+  $EN_DIS
+**/
+  UINT8                       RankInterleave;
+
+/** Offset 0x02A0 - Enhanced Interleave support
+  Enables/Disable Enhanced Interleave support
+  $EN_DIS
+**/
+  UINT8                       EnhancedInterleave;
+
+/** Offset 0x02A1 - Ch Hash Support
+  Enable/Disable Channel Hash Support. NOTE: ONLY if Memory interleaved Mode
+  $EN_DIS
+**/
+  UINT8                       ChHashEnable;
+
+/** Offset 0x02A2 - DDR PowerDown and idle counter
+  Enables/Disable DDR PowerDown and idle counter(For LPDDR Only)
+  $EN_DIS
+**/
+  UINT8                       EnablePwrDn;
+
+/** Offset 0x02A3 - DDR PowerDown and idle counter
+  Enables/Disable DDR PowerDown and idle counter(For LPDDR Only)
+  $EN_DIS
+**/
+  UINT8                       EnablePwrDnLpddr;
+
+/** Offset 0x02A4 - SelfRefresh Enable
+  Enables/Disable SelfRefresh Enable
+  $EN_DIS
+**/
+  UINT8                       SrefCfgEna;
+
+/** Offset 0x02A5 - Throttler CKEMin Defeature
+  Enables/Disable Throttler CKEMin Defeature(For LPDDR Only)
+  $EN_DIS
+**/
+  UINT8                       ThrtCkeMinDefeatLpddr;
+
+/** Offset 0x02A6 - Throttler CKEMin Defeature
+  Enables/Disable Throttler CKEMin Defeature
+  $EN_DIS
+**/
+  UINT8                       ThrtCkeMinDefeat;
+
+/** Offset 0x02A7 - Exit On Failure (MRC)
+  Enables/Disable Exit On Failure (MRC)
+  $EN_DIS
+**/
+  UINT8                       ExitOnFailure;
+
+/** Offset 0x02A8 - Reserved
+**/
+  UINT8                       Reserved23[2];
+
+/** Offset 0x02AA - Read Voltage Centering 1D
+  Enable/Disable Read Voltage Centering 1D
+  $EN_DIS
+**/
+  UINT8                       RDVC1D;
+
+/** Offset 0x02AB - TxDqTCO Comp Training
+  Enable/Disable TxDqTCO Comp Training
+  $EN_DIS
+**/
+  UINT8                       TXTCO;
+
+/** Offset 0x02AC - ClkTCO Comp Training
+  Enable/Disable ClkTCO Comp Training
+  $EN_DIS
+**/
+  UINT8                       CLKTCO;
+
+/** Offset 0x02AD - CMD Slew Rate Training
+  Enable/Disable CMD Slew Rate Training
+  $EN_DIS
+**/
+  UINT8                       CMDSR;
+
+/** Offset 0x02AE - CMD Drive Strength and Tx Equalization
+  Enable/Disable CMD Drive Strength and Tx Equalization
+  $EN_DIS
+**/
+  UINT8                       CMDDSEQ;
+
+/** Offset 0x02AF - DIMM CA ODT Training
+  Enable/Disable DIMM CA ODT Training
+  $EN_DIS
+**/
+  UINT8                       DIMMODTCA;
+
+/** Offset 0x02B0 - Read Vref Decap Training*
+  Enable/Disable Read Vref Decap Training*
+  $EN_DIS
+**/
+  UINT8                       RDVREFDC;
+
+/** Offset 0x02B1 - Rank Margin Tool Per Bit
+  Enable/Disable Rank Margin Tool Per Bit
+  $EN_DIS
+**/
+  UINT8                       RMTBIT;
+
+/** Offset 0x02B2 - Ref PI Calibration
+  Enable/Disable Ref PI Calibration
+  $EN_DIS
+**/
+  UINT8                       REFPI;
+
+/** Offset 0x02B3 - VccClk FF Offset Correction
+  Enable/Disable VccClk FF Offset Correction
+  0:Disable, 1:Enable
+**/
+  UINT8                       VCCCLKFF;
+
+/** Offset 0x02B4 - Data PI Linearity Calibration
+  Enable/Disable {Data PI Linearity Calibration
+  $EN_DIS
+**/
+  UINT8                       DATAPILIN;
+
+/** Offset 0x02B5 - Ddr5 Rx Cross-Talk Cancellation
+  Enable/Disable {Ddr5 Rx Cross-Talk Cancellation
+  $EN_DIS
+**/
+  UINT8                       DDR5XTALK;
+
+/** Offset 0x02B6 - Retrain On Working Channel
+  Enables/Disable Retrain On Working Channel feature
+  $EN_DIS
+**/
+  UINT8                       RetrainToWorkingChannel;
+
+/** Offset 0x02B7 - Row Press
+  Enables/Disable Row Press feature
+  $EN_DIS
+**/
+  UINT8                       RowPressEn;
+
+/** Offset 0x02B8 - Reserved
+**/
+  UINT8                       Reserved24;
+
+/** Offset 0x02B9 - DDR5 MR7 WICA support
+  Enable if DDR5 DRAM Device supports MR7 WICA 0.5 tCK offset alignment
+  $EN_DIS
+**/
+  UINT8                       IsDdr5MR7WicaSupported;
+
+/** Offset 0x02BA - Ch Hash Interleaved Bit
+  Select the BIT to be used for Channel Interleaved mode. NOTE: BIT7 will interlave
+  the channels at a 2 cacheline granularity, BIT8 at 4 and BIT9 at 8. Default is BIT8
+  0:BIT6, 1:BIT7, 2:BIT8, 3:BIT9, 4:BIT10, 5:BIT11, 6:BIT12, 7:BIT13
+**/
+  UINT8                       ChHashInterleaveBit;
+
+/** Offset 0x02BB - Reserved
+**/
+  UINT8                       Reserved25;
+
+/** Offset 0x02BC - Ch Hash Mask
+  Set the BIT(s) to be included in the XOR function. NOTE BIT mask corresponds to
+  BITS [19:6] Default is 0x30CC
+**/
+  UINT16                      ChHashMask;
+
+/** Offset 0x02BE - Reserved
+**/
+  UINT8                       Reserved26;
+
+/** Offset 0x02BF - Throttler CKEMin Timer
+  Timer value for CKEMin, range[255;0]. Req'd min of SC_ROUND_T + BYTE_LENGTH (4).
+  Dfault is 0x00
+**/
+  UINT8                       ThrtCkeMinTmr;
+
+/** Offset 0x02C0 - Allow Opp Ref Below Write Threhold
+  Allow opportunistic refreshes while we don't exit power down.
+  $EN_DIS
+**/
+  UINT8                       AllowOppRefBelowWriteThrehold;
+
+/** Offset 0x02C1 - Write Threshold
+  Number of writes that can be accumulated while CKE is low before CKE is asserted.
+**/
+  UINT8                       WriteThreshold;
+
+/** Offset 0x02C2 - MC_REFRESH_RATE
+  Type of Refresh Rate used to prevent Row Hammer. Default is NORMAL Refresh
+  0:NORMAL Refresh, 1:1x Refresh, 2:2x Refresh, 3:4x Refresh
+**/
+  UINT8                       McRefreshRate;
+
+/** Offset 0x02C3 - Refresh Watermarks
+  Refresh Watermarks: 0-Low, 1-High (default)
+  0:Set Refresh Watermarks to Low, 1:Set Refresh Watermarks to High (Default)
+**/
+  UINT8                       RefreshWm;
+
+/** Offset 0x02C4 - User Manual Threshold
+  Disabled: Predefined threshold will be used.\n
+  Enabled: User Input will be used.
+  $EN_DIS
+**/
+  UINT8                       UserThresholdEnable;
+
+/** Offset 0x02C5 - User Manual Budget
+  Disabled: Configuration of memories will defined the Budget value.\n
+  Enabled: User Input will be used.
+  $EN_DIS
+**/
+  UINT8                       UserBudgetEnable;
+
+/** Offset 0x02C6 - Power Down Mode
+  This option controls command bus tristating during idle periods
+  0x0:No Power Down, 0x1:APD, 0x6:PPD DLL OFF, 0xFF:Auto
+**/
+  UINT8                       PowerDownMode;
+
+/** Offset 0x02C7 - Pwr Down Idle Timer
+  The minimum value should = to the worst case Roundtrip delay + Burst_Length. 0 means
+  AUTO: 64 for ULX/ULT, 128 for DT/Halo
+**/
+  UINT8                       PwdwnIdleCounter;
+
+/** Offset 0x02C8 - Page Close Idle Timeout
+  This option controls Page Close Idle Timeout
+  0:Enabled, 1:Disabled
+**/
+  UINT8                       DisPgCloseIdleTimeout;
+
+/** Offset 0x02C9 - Bitmask of ranks that have CA bus terminated
+  LPDDR5: Bitmask of ranks that have CA bus terminated. <b>0x01=Default, Rank0 is
+  terminating and Rank1 is non-terminating</b>
+**/
+  UINT8                       CmdRanksTerminated;
+
+/** Offset 0x02CA - MRC Safe Mode Override
+  SafeModeOverride[0] Enable DdrSafeMode override, SafeModeOverride[1] Enable McSafeMode
+  override, SafeModeOverride[2] Enable MrcSafeMode override, SafeModeOverride[3]
+  Enable Training Algorithm (TrainingEnables) safe mode override, SafeModeOverride[4]
+  Enable SaGv safe mode override
+**/
+  UINT8                       SafeModeOverride;
+
+/** Offset 0x02CB - Reserved
+**/
+  UINT8                       Reserved27[5];
+
+/** Offset 0x02D0 - DDR Phy Safe Mode Support
+  DdrSafeMode[0]: Basic PM Features, DdrSafeMode[1]: Spine Gating, DdrSafeMode[2]:
+  Advanced DCC, DdrSafeMode[3]: R2R Training, DdrSafeMode[4]: Transformer Mode, DdrSafeMode[5]:
+  PLL Operation, DdrSafeMode[6]: Safe ODT
+**/
+  UINT32                      DdrSafeMode;
+
+/** Offset 0x02D4 - Mc Safe Mode Support
+  McSafeMode[0]: Reserved, McSafeMode[1]: OppSR
+**/
+  UINT8                       McSafeMode;
+
+/** Offset 0x02D5 - Ask MRC to clear memory content
+  Ask MRC to clear memory content <b>0: Do not Clear Memory;</b> 1: Clear Memory.
+  $EN_DIS
+**/
+  UINT8                       CleanMemory;
+
+/** Offset 0x02D6 - Reserved
+**/
+  UINT8                       Reserved28[8];
+
+/** Offset 0x02DE - RMTLoopCount
+  Specifies the Loop Count to be used during Rank Margin Tool Testing. 0 - AUTO
+**/
+  UINT8                       RMTLoopCount;
+
+/** Offset 0x02DF - DdrOneDpc
+  DDR 1DPC performance feature for 2R DIMMs. Can be enabled on DIMM0 or DIMM1 only,
+  or on both (default)
+  0: Disabled, 1: Enabled on DIMM0 only, 2: Enabled on DIMM1 only, 3: Enabled
+**/
+  UINT8                       DdrOneDpc;
+
+/** Offset 0x02E0 - Vddq Voltage Override
+  # is multiple of 1mV where 0 means Auto.
+**/
+  UINT16                      VddqVoltageOverride;
+
+/** Offset 0x02E2 - VccIog Voltage Override
+  # is multiple of 1mV where 0 means Auto.
+**/
+  UINT16                      VccIogVoltageOverride;
+
+/** Offset 0x02E4 - VccClk Voltage Override
+  # is multiple of 1mV where 0 means Auto.
+**/
+  UINT16                      VccClkVoltageOverride;
+
+/** Offset 0x02E6 - ThrtCkeMinTmrLpddr
+  Throttler CKE min timer for LPDDR: 0=Minimal, 0xFF=Maximum, <b>0x00=Default</b>
+**/
+  UINT8                       ThrtCkeMinTmrLpddr;
+
+/** Offset 0x02E7 - Reserved
+**/
+  UINT8                       Reserved29;
+
+/** Offset 0x02E8 - Margin limit check L2
+  Margin limit check L2 threshold: <b>100=Default</b>
+**/
+  UINT16                      MarginLimitL2;
+
+/** Offset 0x02EA - Extended Bank Hashing
+  Eanble/Disable ExtendedBankHashing
+  $EN_DIS
+**/
+  UINT8                       ExtendedBankHashing;
+
+/** Offset 0x02EB - Reserved
+**/
+  UINT8                       Reserved30;
+
+/** Offset 0x02EC - LP5 Command Pins Mapping
+  BitMask where bits [3:0] are Controller 0 Channel [3:0] and bits [7:4] are Controller
+  1 Channel [3:0]. 0 = CCC pin mapping is Ascending, 1 = CCC pin mapping is Descending.
+**/
+  UINT8                       Lp5CccConfig;
+
+/** Offset 0x02ED - Command Pins Mirrored
+  BitMask where bits [3:0] are Controller 0 Channel [3:0] and bits [7:4] are Controller
+  1 Channel [3:0]. 0 = No Command Mirror and 1 = Command Mirror.
+**/
+  UINT8                       CmdMirror;
+
+/** Offset 0x02EE - Time Measure
+  Time Measure: 0(Default)=Disable, 1=Enable
+  $EN_DIS
+**/
+  UINT8                       MrcTimeMeasure;
+
+/** Offset 0x02EF - Reserved
+**/
+  UINT8                       Reserved31[43];
+
+/** Offset 0x031A - Read Vref Decap Training*
+  Enable/Disable Read Timing Centering Training with SR stress*
+  $EN_DIS
+**/
+  UINT8                       RDTCIDLE;
+
+/** Offset 0x031B - PPR Retry Limit
+  Sets a limit on the number of times Memory Testing will be retried after attempting
+  to repair using PPR.
+**/
+  UINT8                       PprRetryLimit;
+
+/** Offset 0x031C - Use 1p5 Read Postamble
+  Enables/Disable using 1p5 tCK Read Postamble for higher freqencies
+  $EN_DIS
+**/
+  UINT8                       Use1p5ReadPostamble;
+
+/** Offset 0x031D - Reserved
+**/
+  UINT8                       Reserved32[18];
+
+/** Offset 0x032F - Board Type
+  MrcBoardType, Options are 0=Mobile/Mobile Halo, 1=Desktop/DT Halo, 5=ULT/ULX/Mobile
+  Halo, 7=UP Server
+  0:Mobile/Mobile Halo, 1:Desktop/DT Halo, 5:ULT/ULX/Mobile Halo, 7:UP Server
+**/
+  UINT8                       UserBd;
+
+/** Offset 0x0330 - Spd Address Table
+  Specify SPD Address table for CH0D0/CH0D1/CH1D0&CH1D1. MemorySpdPtr will be used
+  if SPD Address is 00
+**/
+  UINT8                       SpdAddressTable[16];
+
+/** Offset 0x0340 - Enable/Disable MRC TXT dependency
+  When enabled MRC execution will wait for TXT initialization to be done first. Disabled(0x0)(Default):
+  MRC will not wait for TXT initialization, Enabled(0x1): MRC will wait for TXT initialization
+  $EN_DIS
+**/
+  UINT8                       TxtImplemented;
+
+/** Offset 0x0341 - Reserved
+**/
+  UINT8                       Reserved33;
+
+/** Offset 0x0342 - Skip external display device scanning
+  Enable: Do not scan for external display device, Disable (Default): Scan external
+  display devices
+  $EN_DIS
+**/
+  UINT8                       SkipExtGfxScan;
+
+/** Offset 0x0343 - Generate BIOS Data ACPI Table
+  Enable: Generate BDAT for MRC RMT or SA PCIe data. Disable (Default): Do not generate it
+  $EN_DIS
+**/
+  UINT8                       BdatEnable;
+
+/** Offset 0x0344 - BdatTestType
+  Indicates the type of Memory Training data to populate into the BDAT ACPI table.
+  0:RMT per Rank, 1:RMT per Bit, 2:Margin2D
+**/
+  UINT8                       BdatTestType;
+
+/** Offset 0x0345 - Enable PCH HSIO PCIE Rx Set Ctle
+  Enable PCH PCIe Gen 3 Set CTLE Value.
+**/
+  UINT8                       PchPcieHsioRxSetCtleEnable[28];
+
+/** Offset 0x0361 - PCH HSIO PCIE Rx Set Ctle Value
+  PCH PCIe Gen 3 Set CTLE Value.
+**/
+  UINT8                       PchPcieHsioRxSetCtle[28];
+
+/** Offset 0x037D - Enble PCH HSIO PCIE TX Gen 1 Downscale Amplitude Adjustment value override
+  0: Disable; 1: Enable.
+**/
+  UINT8                       PchPcieHsioTxGen1DownscaleAmpEnable[28];
+
+/** Offset 0x0399 - PCH HSIO PCIE Gen 2 TX Output Downscale Amplitude Adjustment value
+  PCH PCIe Gen 2 TX Output Downscale Amplitude Adjustment value.
+**/
+  UINT8                       PchPcieHsioTxGen1DownscaleAmp[28];
+
+/** Offset 0x03B5 - Enable PCH HSIO PCIE TX Gen 2 Downscale Amplitude Adjustment value override
+  0: Disable; 1: Enable.
+**/
+  UINT8                       PchPcieHsioTxGen2DownscaleAmpEnable[28];
+
+/** Offset 0x03D1 - PCH HSIO PCIE Gen 2 TX Output Downscale Amplitude Adjustment value
+  PCH PCIe Gen 2 TX Output Downscale Amplitude Adjustment value.
+**/
+  UINT8                       PchPcieHsioTxGen2DownscaleAmp[28];
+
+/** Offset 0x03ED - Enable PCH HSIO PCIE TX Gen 3 Downscale Amplitude Adjustment value override
+  0: Disable; 1: Enable.
+**/
+  UINT8                       PchPcieHsioTxGen3DownscaleAmpEnable[28];
+
+/** Offset 0x0409 - PCH HSIO PCIE Gen 3 TX Output Downscale Amplitude Adjustment value
+  PCH PCIe Gen 3 TX Output Downscale Amplitude Adjustment value.
+**/
+  UINT8                       PchPcieHsioTxGen3DownscaleAmp[28];
+
+/** Offset 0x0425 - Enable PCH HSIO PCIE Gen 1 TX Output De-Emphasis Adjustment Setting value override
+  0: Disable; 1: Enable.
+**/
+  UINT8                       PchPcieHsioTxGen1DeEmphEnable[28];
+
+/** Offset 0x0441 - PCH HSIO PCIE Gen 1 TX Output De-Emphasis Adjustment value
+  PCH PCIe Gen 1 TX Output De-Emphasis Adjustment Setting.
+**/
+  UINT8                       PchPcieHsioTxGen1DeEmph[28];
+
+/** Offset 0x045D - Enable PCH HSIO PCIE Gen 2 TX Output -3.5dB De-Emphasis Adjustment Setting value override
+  0: Disable; 1: Enable.
+**/
+  UINT8                       PchPcieHsioTxGen2DeEmph3p5Enable[28];
+
+/** Offset 0x0479 - PCH HSIO PCIE Gen 2 TX Output -3.5dB De-Emphasis Adjustment value
+  PCH PCIe Gen 2 TX Output -3.5dB De-Emphasis Adjustment Setting.
+**/
+  UINT8                       PchPcieHsioTxGen2DeEmph3p5[28];
+
+/** Offset 0x0495 - Enable PCH HSIO PCIE Gen 2 TX Output -6.0dB De-Emphasis Adjustment Setting value override
+  0: Disable; 1: Enable.
+**/
+  UINT8                       PchPcieHsioTxGen2DeEmph6p0Enable[28];
+
+/** Offset 0x04B1 - PCH HSIO PCIE Gen 2 TX Output -6.0dB De-Emphasis Adjustment value
+  PCH PCIe Gen 2 TX Output -6.0dB De-Emphasis Adjustment Setting.
+**/
+  UINT8                       PchPcieHsioTxGen2DeEmph6p0[28];
+
+/** Offset 0x04CD - HD Audio DMIC Link Clock Select
+  Determines DMIC<N> Clock Source. 0: Both, 1: ClkA, 2: ClkB
+  0: Both, 1: ClkA, 2: ClkB
+**/
+  UINT8                       PchHdaAudioLinkDmicClockSelect[2];
+
+/** Offset 0x04CF - Enable Intel HD Audio (Azalia)
+  0: Disable, 1: Enable (Default) Azalia controller
+  $EN_DIS
+**/
+  UINT8                       PchHdaEnable;
+
+/** Offset 0x04D0 - Universal Audio Architecture compliance for DSP enabled system
+  0: Not-UAA Compliant (Intel SST driver supported only), 1: UAA Compliant (HDA Inbox
+  driver or SST driver supported).
+  $EN_DIS
+**/
+  UINT8                       PchHdaDspUaaCompliance;
+
+/** Offset 0x04D1 - Enable HD Audio Link
+  Enable/disable HD Audio Link. Muxed with SSP0/SSP1/SNDW1.
+  $EN_DIS
+**/
+  UINT8                       PchHdaAudioLinkHdaEnable;
+
+/** Offset 0x04D2 - Enable HDA SDI lanes
+  Enable/disable HDA SDI lanes.
+**/
+  UINT8                       PchHdaSdiEnable[2];
+
+/** Offset 0x04D4 - Enable HD Audio DMIC_N Link
+  Enable/disable HD Audio DMIC1 link. Muxed with SNDW3.
+**/
+  UINT8                       PchHdaAudioLinkDmicEnable[2];
+
+/** Offset 0x04D6 - Reserved
+**/
+  UINT8                       Reserved34[2];
+
+/** Offset 0x04D8 - DMIC<N> ClkA Pin Muxing (N - DMIC number)
+  Determines DMIC<N> ClkA Pin muxing. See  GPIO_*_MUXING_DMIC<N>_CLKA_*
+**/
+  UINT32                      PchHdaAudioLinkDmicClkAPinMux[2];
+
+/** Offset 0x04E0 - Enable HD Audio DSP
+  Enable/disable HD Audio DSP feature.
+  $EN_DIS
+**/
+  UINT8                       PchHdaDspEnable;
+
+/** Offset 0x04E1 - Reserved
+**/
+  UINT8                       Reserved35[3];
+
+/** Offset 0x04E4 - DMIC<N> Data Pin Muxing
+  Determines DMIC<N> Data Pin muxing. See GPIO_*_MUXING_DMIC<N>_DATA_*
+**/
+  UINT32                      PchHdaAudioLinkDmicDataPinMux[2];
+
+/** Offset 0x04EC - Enable HD Audio SSP0 Link
+  Enable/disable HD Audio SSP_N/I2S link. Muxed with HDA. N-number 0-5
+**/
+  UINT8                       PchHdaAudioLinkSspEnable[7];
+
+/** Offset 0x04F3 - Reserved
+**/
+  UINT8                       Reserved36[117];
+
+/** Offset 0x0568 - Enable HD Audio SoundWire#N Link
+  Enable/disable HD Audio SNDW#N link. Muxed with HDA.
+**/
+  UINT8                       PchHdaAudioLinkSndwEnable[5];
+
+/** Offset 0x056D - iDisp-Link Frequency
+  iDisp-Link Freq (PCH_HDAUDIO_LINK_FREQUENCY enum): 4: 96MHz, 3: 48MHz.
+  4: 96MHz, 3: 48MHz
+**/
+  UINT8                       PchHdaIDispLinkFrequency;
+
+/** Offset 0x056E - iDisp-Link T-mode
+  iDisp-Link T-Mode (PCH_HDAUDIO_IDISP_TMODE enum): 0: 2T, 2: 4T, 3: 8T, 4: 16T
+  0: 2T, 2: 4T, 3: 8T, 4: 16T
+**/
+  UINT8                       PchHdaIDispLinkTmode;
+
+/** Offset 0x056F - Reserved
+**/
+  UINT8                       Reserved37[45];
+
+/** Offset 0x059C - iDisplay Audio Codec disconnection
+  0: Not disconnected, enumerable, 1: Disconnected SDI, not enumerable.
+  $EN_DIS
+**/
+  UINT8                       PchHdaIDispCodecDisconnect;
+
+/** Offset 0x059D - Reserved
+**/
+  UINT8                       Reserved38[5];
+
+/** Offset 0x05A2 - HDA Power/Clock Gating (PGD/CGD)
+  Enable/Disable HD Audio Power and Clock Gating(POR: Enable). 0: PLATFORM_POR, 1:
+  FORCE_ENABLE, 2: FORCE_DISABLE.
+  0: POR, 1: Force Enable, 2: Force Disable
+**/
+  UINT8                       PchHdaTestPowerClockGating;
+
+/** Offset 0x05A3 - Reserved
+**/
+  UINT8                       Reserved39;
+
+/** Offset 0x05A4 - Audio Sub System IDs
+  Set default Audio Sub System IDs. If its set to 0 then value from Strap is used.
+**/
+  UINT32                      PchHdaSubSystemIds;
+
+/** Offset 0x05A8 - Reserved
+**/
+  UINT8                       Reserved40;
+
+/** Offset 0x05A9 - PCH LPC Enhance the port 8xh decoding
+  Original LPC only decodes one byte of port 80h.
+  $EN_DIS
+**/
+  UINT8                       PchLpcEnhancePort8xhDecoding;
+
+/** Offset 0x05AA - Usage type for ClkSrc
+  0-23: PCH rootport, 0x70:LAN, 0x80: unspecified but in use (free running), 0xFF: not used
+**/
+  UINT8                       PcieClkSrcUsage[18];
+
+/** Offset 0x05BC - ClkReq-to-ClkSrc mapping
+  Number of ClkReq signal assigned to ClkSrc
+**/
+  UINT8                       PcieClkSrcClkReq[18];
+
+/** Offset 0x05CE - Reserved
+**/
+  UINT8                       Reserved41[46];
+
+/** Offset 0x05FC - Enable PCIE RP Mask
+  Enable/disable PCIE Root Ports. 0: disable, 1: enable. One bit for each port, bit0
+  for port1, bit1 for port2, and so on.
+**/
+  UINT32                      PcieRpEnableMask;
+
+/** Offset 0x0600 - Debug Interfaces
+  Debug Interfaces. BIT0-RAM, BIT1-UART, BIT3-USB3, BIT4-Serial IO, BIT5-TraceHub,
+  BIT2 - Not used.
+**/
+  UINT8                       PcdDebugInterfaceFlags;
+
+/** Offset 0x0601 - Reserved
+**/
+  UINT8                       Reserved42[3];
+
+/** Offset 0x0604 - Serial Io Uart Debug Mmio Base
+  Select SerialIo Uart default MMIO resource in SEC/PEI phase when PcdLpssUartMode
+  = SerialIoUartPci.
+**/
+  UINT32                      SerialIoUartDebugMmioBase;
+
+/** Offset 0x0608 - PcdSerialDebugLevel
+  Serial Debug Message Level. 0:Disable, 1:Error Only, 2:Error & Warnings, 3:Load,
+  Error, Warnings & Info, 4:Load, Error, Warnings, Info & Event, 5:Load, Error, Warnings,
+  Info & Verbose.
+  0:Disable, 1:Error Only, 2:Error and Warnings, 3:Load Error Warnings and Info, 4:Load
+  Error Warnings and Info & Event, 5:Load Error Warnings Info and Verbose
+**/
+  UINT8                       PcdSerialDebugLevel;
+
+/** Offset 0x0609 - SerialDebugMrcLevel
+  MRC Serial Debug Message Level. 0:Disable, 1:Error Only, 2:Error & Warnings, 3:Load,
+  Error, Warnings & Info, 4:Load, Error, Warnings, Info & Event, 5:Load, Error, Warnings,
+  Info & Verbose.
+  0:Disable, 1:Error Only, 2:Error and Warnings, 3:Load Error Warnings and Info, 4:Load
+  Error Warnings and Info & Event, 5:Load Error Warnings Info and Verbose
+**/
+  UINT8                       SerialDebugMrcLevel;
+
+/** Offset 0x060A - Serial Io Uart Debug Controller Number
+  Select SerialIo Uart Controller for debug. Note: If UART0 is selected as CNVi BT
+  Core interface, it cannot be used for debug purpose.
+  0:SerialIoUart0, 1:SerialIoUart1, 2:SerialIoUart2
+**/
+  UINT8                       SerialIoUartDebugControllerNumber;
+
+/** Offset 0x060B - Serial Io Uart Debug Parity
+  Set default Parity.
+  0: DefaultParity, 1: NoParity, 2: EvenParity, 3: OddParity
+**/
+  UINT8                       SerialIoUartDebugParity;
+
+/** Offset 0x060C - Serial Io Uart Debug BaudRate
+  Set default BaudRate Supported from 0 - default to 6000000. Recommended values 9600,
+  19200, 57600, 115200, 460800, 921600, 1500000, 1843200, 3000000, 3686400, 6000000
+**/
+  UINT32                      SerialIoUartDebugBaudRate;
+
+/** Offset 0x0610 - Serial Io Uart Debug Stop Bits
+  Set default stop bits.
+  0: DefaultStopBits, 1: OneStopBit, 2: OneFiveStopBits, 3: TwoStopBits
+**/
+  UINT8                       SerialIoUartDebugStopBits;
+
+/** Offset 0x0611 - Serial Io Uart Debug Data Bits
+  Set default word length. 0: Default, 5,6,7,8
+  5:5BITS, 6:6BITS, 7:7BITS, 8:8BITS
+**/
+  UINT8                       SerialIoUartDebugDataBits;
+
+/** Offset 0x0612 - IMGU CLKOUT Configuration
+  The configuration of IMGU CLKOUT, 0: Disable;<b>1: Enable</b>.
+  $EN_DIS
+**/
+  UINT8                       ImguClkOutEn[6];
+
+/** Offset 0x0618 - Enable/Disable SA IPU
+  Enable(Default): Enable SA IPU, Disable: Disable SA IPU
+  $EN_DIS
+**/
+  UINT8                       SaIpuEnable;
+
+/** Offset 0x0619 - Disable and Lock Watch Dog Register
+  Set 1 to clear WDT status, then disable and lock WDT registers.
+  $EN_DIS
+**/
+  UINT8                       WdtDisableAndLock;
+
+/** Offset 0x061A - Reserved
+**/
+  UINT8                       Reserved43[2];
+
+/** Offset 0x061C - HECI Timeouts
+  0: Disable, 1: Enable (Default) timeout check for HECI
+  $EN_DIS
+**/
+  UINT8                       HeciTimeouts;
+
+/** Offset 0x061D - HECI2 Interface Communication
+  Test, 0: disable, 1: enable, Adds or Removes HECI2 Device from PCI space.
+  $EN_DIS
+**/
+  UINT8                       HeciCommunication2;
+
+/** Offset 0x061E - Check HECI message before send
+  Test, 0: disable, 1: enable, Enable/Disable message check.
+  $EN_DIS
+**/
+  UINT8                       DisableMessageCheck;
+
+/** Offset 0x061F - Force ME DID Init Status
+  Test, 0: disable, 1: Success, 2: No Memory in Channels, 3: Memory Init Error, Set
+  ME DID init stat value
+  $EN_DIS
+**/
+  UINT8                       DidInitStat;
+
+/** Offset 0x0620 - Enable KT device
+  Test, 0: POR, 1: enable, 2: disable, Enable or Disable KT device.
+  $EN_DIS
+**/
+  UINT8                       KtDeviceEnable;
+
+/** Offset 0x0621 - CPU Replaced Polling Disable
+  Test, 0: disable, 1: enable, Setting this option disables CPU replacement polling loop
+  $EN_DIS
+**/
+  UINT8                       DisableCpuReplacedPolling;
+
+/** Offset 0x0622 - Skip CPU replacement check
+  Test, 0: disable, 1: enable, Setting this option to skip CPU replacement check
+  $EN_DIS
+**/
+  UINT8                       SkipCpuReplacementCheck;
+
+/** Offset 0x0623 - Skip MBP HOB
+  Test, 0: disable, 1: enable, Enable/Disable sending MBP message and creating MBP Hob.
+  $EN_DIS
+**/
+  UINT8                       SkipMbpHob;
+
+/** Offset 0x0624 - Reserved
+**/
+  UINT8                       Reserved44[2];
+
+/** Offset 0x0626 - ISA Serial Base selection
+  Select ISA Serial Base address. Default is 0x3F8.
+  0:0x3F8, 1:0x2F8
+**/
+  UINT8                       PcdIsaSerialUartBase;
+
+/** Offset 0x0627 - PcdSerialDebugBaudRate
+  Baud Rate for Serial Debug Messages. 3:9600, 4:19200, 6:56700, 7:115200.
+  3:9600, 4:19200, 6:56700, 7:115200
+**/
+  UINT8                       PcdSerialDebugBaudRate;
+
+/** Offset 0x0628 - Post Code Output Port
+  This option configures Post Code Output Port
+**/
+  UINT16                      PostCodeOutputPort;
+
+/** Offset 0x062A - Reserved
+**/
+  UINT8                       Reserved45[26];
+
+/** Offset 0x0644 - Enable SMBus
+  Enable/disable SMBus controller.
+  $EN_DIS
+**/
+  UINT8                       SmbusEnable;
+
+/** Offset 0x0645 - Enable SMBus ARP support
+  Enable SMBus ARP support.
+  $EN_DIS
+**/
+  UINT8                       SmbusArpEnable;
+
+/** Offset 0x0646 - Number of RsvdSmbusAddressTable.
+  The number of elements in the RsvdSmbusAddressTable.
+**/
+  UINT8                       PchNumRsvdSmbusAddresses;
+
+/** Offset 0x0647 - Reserved
+**/
+  UINT8                       Reserved46;
+
+/** Offset 0x0648 - SMBUS Base Address
+  SMBUS Base Address (IO space).
+**/
+  UINT16                      PchSmbusIoBase;
+
+/** Offset 0x064A - Enable SMBus Alert Pin
+  Enable SMBus Alert Pin.
+  $EN_DIS
+**/
+  UINT8                       PchSmbAlertEnable;
+
+/** Offset 0x064B - Reserved
+**/
+  UINT8                       Reserved47[13];
+
+/** Offset 0x0658 - Smbus dynamic power gating
+  Disable or Enable Smbus dynamic power gating.
+  $EN_DIS
+**/
+  UINT8                       SmbusDynamicPowerGating;
+
+/** Offset 0x0659 - SMBUS SPD Write Disable
+  Set/Clear Smbus SPD Write Disable. 0: leave SPD Write Disable bit; 1: set SPD Write
+  Disable bit. For security recommendations, SPD write disable bit must be set.
+  $EN_DIS
+**/
+  UINT8                       SmbusSpdWriteDisable;
+
+/** Offset 0x065A - Enable/Disable SA OcSupport
+  Enable: Enable SA OcSupport, Disable(Default): Disable SA OcSupport
+  $EN_DIS
+**/
+  UINT8                       SaOcSupport;
+
+/** Offset 0x065B - Reserved
+**/
+  UINT8                       Reserved48[18];
+
+/** Offset 0x066D - Over clocking support
+  Over clocking support; <b>0: Disable</b>; 1: Enable
+  $EN_DIS
+**/
+  UINT8                       OcSupport;
+
+/** Offset 0x066E - Reserved
+**/
+  UINT8                       Reserved49;
+
+/** Offset 0x066F - Realtime Memory Timing
+  0(Default): Disabled, 1: Enabled. When enabled, it will allow the system to perform
+  realtime memory timing changes after MRC_DONE.
+  0: Disabled, 1: Enabled
+**/
+  UINT8                       RealtimeMemoryTiming;
+
+/** Offset 0x0670 - core voltage override
+  The core voltage override which is applied to the entire range of cpu core frequencies.
+  Valid Range 0 to 2000
+**/
+  UINT16                      CoreVoltageOverride;
+
+/** Offset 0x0672 - Core Turbo voltage Offset
+  The voltage offset applied to the core while operating in turbo mode.Valid Range 0 to 1000
+**/
+  UINT16                      CoreVoltageOffset;
+
+/** Offset 0x0674 - Core PLL voltage offset
+  Core PLL voltage offset. <b>0: No offset</b>. Range 0-15
+**/
+  UINT8                       CorePllVoltageOffset;
+
+/** Offset 0x0675 - AVX2 Ratio Offset
+  0(Default)= No Offset. Range 0 - 31. Specifies number of bins to decrease AVX ratio
+  vs. Core Ratio. Uses Mailbox MSR 0x150, cmd 0x1B.
+**/
+  UINT8                       Avx2RatioOffset;
+
+/** Offset 0x0676 - BCLK Adaptive Voltage Enable
+  When enabled, the CPU V/F curves are aware of BCLK frequency when calculated. </b>0:
+  Disable;<b> 1: Enable
+  $EN_DIS
+**/
+  UINT8                       BclkAdaptiveVoltage;
+
+/** Offset 0x0677 - Ring Downbin
+  Ring Downbin enable/disable. When enabled, CPU will ensure the ring ratio is always
+  lower than the core ratio.0: Disable; <b>1: Enable.</b>
+  $EN_DIS
+**/
+  UINT8                       RingDownBin;
+
+/** Offset 0x0678 - Row Hammer pTRR LFSR0 Mask
+  Row Hammer pTRR LFSR0 Mask, 1/2^(value)
+**/
+  UINT8                       Lfsr0Mask;
+
+/** Offset 0x0679 - Margin Limit Check
+  Margin Limit Check. Choose level of margin check
+  0:Disable, 1:L1, 2:L2, 3:Both
+**/
+  UINT8                       MarginLimitCheck;
+
+/** Offset 0x067A - Row Hammer pTRR LFSR1 Mask
+  Row Hammer pTRR LFSR1 Mask, 1/2^(value)
+**/
+  UINT8                       Lfsr1Mask;
+
+/** Offset 0x067B - Reserved
+**/
+  UINT8                       Reserved50[2];
+
+/** Offset 0x067D - TjMax Offset
+  TjMax offset.Specified value here is clipped by pCode (125 - TjMax Offset) to support
+  TjMax in the range of 62 to 115 deg Celsius. Valid Range 10 - 63
+**/
+  UINT8                       TjMaxOffset;
+
+/** Offset 0x067E - Reserved
+**/
+  UINT8                      Reserved51[48];
+
+/** Offset 0x06AE - Core VF Point Offset
+  Array used to specifies the Core Voltage Offset applied to the each selected VF
+  Point. This voltage is specified in millivolts.
+**/
+  UINT16                      CoreVfPointOffset[15];
+
+/** Offset 0x06CC - Core VF Point Offset Prefix
+  Sets the CoreVfPointOffset value as positive or negative for corresponding core
+  VF Point; <b>0: Positive </b>; 1: Negative.
+  0:Positive, 1:Negative
+**/
+  UINT8                       CoreVfPointOffsetPrefix[15];
+
+/** Offset 0x06DB - Core VF Point Ratio
+  Array for the each selected Core VF Point to display the ration.
+**/
+  UINT8                       CoreVfPointRatio[15];
+
+/** Offset 0x06EA - Reserved
+**/
+  UINT8                       Reserved52[26];
+
+/** Offset 0x0704 - Per Core Max Ratio override
+  Enable or disable Per Core PState OC supported by writing OCMB 0x1D to program new
+  favored core ratio to each Core. <b>0: Disable</b>, 1: enable
+  $EN_DIS
+**/
+  UINT8                       PerCoreRatioOverride;
+
+/** Offset 0x0705 - Reserved
+**/
+  UINT8                       Reserved53[25];
+
+/** Offset 0x071E - Per Core Current Max Ratio
+  Array for the Per Core Max Ratio
+**/
+  UINT8                       PerCoreRatio[8];
+
+/** Offset 0x0726 - Reserved
+**/
+  UINT8                       Reserved54[8];
+
+/** Offset 0x072E - Pvd Ratio Threshold for SOC/CPU die
+  Array of Pvd Ratio Threshold for SOC/CPU die is the threshold value for input ratio
+  (P0 to Pn) to select the multiplier so that the output is within the DCO frequency
+  range. As per the die selected, this threshold is applied to SA and MC/CMI PLL
+  for SOC die and SA, Ring and Atom PLL for CPU die. Range 0-63. When the threshold
+  is 0, static PVD ratio is selected based on the PVD Mode for SOC. <b>0: Default</b>.
+**/
+  UINT8                       PvdRatioThreshold;
+
+/** Offset 0x072F - Reserved
+**/
+  UINT8                       Reserved55[65];
+
+/** Offset 0x0770 - CPU BCLK OC Frequency
+  CPU BCLK OC Frequency in KHz units. 98000000Hz = 98MHz <b>0 - Auto</b>. Range is
+  40Mhz-1000Mhz.
+**/
+  UINT32                      CpuBclkOcFrequency;
+
+/** Offset 0x0774 - Reserved
+**/
+  UINT8                      Reserved56[13];
+
+/** Offset 0x0781 - Avx2 Voltage Guardband Scaling Factor
+  AVX2 Voltage Guardband Scale factor applied to AVX2 workloads. Range is 0-200 in
+  1/100 units, where a value of 125 would apply a 1.25 scale factor.
+**/
+  UINT8                       Avx2VoltageScaleFactor;
+
+/** Offset 0x0782 - Ring PLL voltage offset
+  Core PLL voltage offset. <b>0: No offset</b>. Range 0-15
+**/
+  UINT8                       RingPllVoltageOffset;
+
+/** Offset 0x0783 - Reserved
+**/
+  UINT8                       Reserved57[5];
+
+/** Offset 0x0788 - Enable PCH ISH Controller
+  0: Disable, 1: Enable (Default) ISH Controller
+  $EN_DIS
+**/
+  UINT8                       PchIshEnable;
+
+/** Offset 0x0789 - Reserved
+**/
+  UINT8                       Reserved58;
+
+/** Offset 0x078A - BiosSize
+  The size of the BIOS region of the IFWI. Used if FspmUpd->FspmConfig.BiosGuard !=
+  0. If BiosGuard is enabled, MRC will increase the size of the DPR (DMA Protected
+  Range) so that a BIOS Update Script can be stored in the DPR.
+**/
+  UINT16                      BiosSize;
+
+/** Offset 0x078C - BiosGuard
+  Enable/Disable. 0: Disable, Enable/Disable BIOS Guard feature, 1: enable
+  $EN_DIS
+**/
+  UINT8                       BiosGuard;
+
+/** Offset 0x078D
+**/
+  UINT8                       BiosGuardToolsInterface;
+
+/** Offset 0x078E - Txt
+  Enables utilization of additional hardware capabilities provided by Intel (R) Trusted
+  Execution Technology. Changes require a full power cycle to take effect. <b>0:
+  Disable</b>, 1: Enable
+  $EN_DIS
+**/
+  UINT8                       Txt;
+
+/** Offset 0x078F - Skip Stop PBET Timer Enable/Disable
+  Skip Stop PBET Timer; <b>0: Disable</b>; 1: Enable
+  $EN_DIS
+**/
+  UINT8                       SkipStopPbet;
+
+/** Offset 0x0790 - Reserved
+**/
+  UINT8                       Reserved59[3];
+
+/** Offset 0x0793 - MKTME Key-Id Bits Override Enable
+  Configure Trust Domain Extension (TDX) to isolate VMs from Virtual-Machine Manager
+  (VMM)/hypervisor <b>0: Disable</b>; 1: Enable.
+  $EN_DIS
+**/
+  UINT8                       GenerateNewTmeKey;
+
+/** Offset 0x0794 - Reserved
+**/
+  UINT8                       Reserved60[4];
+
+/** Offset 0x0798 - TME Exclude Base Address
+  TME Exclude Base Address.
+**/
+  UINT64                      TmeExcludeBase;
+
+/** Offset 0x07A0 - TME Exclude Size Value
+  TME Exclude Size Value.
+**/
+  UINT64                      TmeExcludeSize;
+
+/** Offset 0x07A8 - Reserved
+**/
+  UINT8                      Reserved61[14];
+
+/** Offset 0x07B6 - BIST on Reset
+  Enable/Disable BIST (Built-In Self Test) on reset. <b>0: Disable</b>; 1: Enable.
+  $EN_DIS
+**/
+  UINT8                       BistOnReset;
+
+/** Offset 0x07B7 - Reserved
+**/
+  UINT8                       Reserved62;
+
+/** Offset 0x07B8 - Enable or Disable VMX
+  Enable or Disable VMX, When enabled, a VMM can utilize the additional hardware capabilities
+  provided by Vanderpool Technology. 0: Disable; <b>1: Enable</b>.
+  $EN_DIS
+**/
+  UINT8                       VmxEnable;
+
+/** Offset 0x07B9 - Processor Early Power On Configuration FCLK setting
+  FCLK frequency can take values of 400MHz, 800MHz and 1GHz. <b>0: 800 MHz (ULT/ULX)</b>.
+  <b>1: 1 GHz (DT/Halo)</b>. Not supported on ULT/ULX.- 2: 400 MHz. - 3: Reserved
+  0:800 MHz, 1: 1 GHz, 2: 400 MHz, 3: Reserved
+**/
+  UINT8                       FClkFrequency;
+
+/** Offset 0x07BA - Enable CPU CrashLog
+  Enable or Disable CPU CrashLog; 0: Disable; <b>1: Enable</b>.
+  $EN_DIS
+**/
+  UINT8                       CpuCrashLogEnable;
+
+/** Offset 0x07BB - Enable or Disable TME
+  Configure Total Memory Encryption (TME) to protect DRAM data from physical attacks.
+  <b>0: Disable</b>; 1: Enable.
+  $EN_DIS
+**/
+  UINT8                       TmeEnable;
+
+/** Offset 0x07BC - CPU Run Control
+  Enable, Disable or Do not configure CPU Run Control; 0: Disable; 1: Enable ; <b>2:
+  No Change</b>
+  0:Disabled, 1:Enabled, 2:No Change
+**/
+  UINT8                       DebugInterfaceEnable;
+
+/** Offset 0x07BD - CPU Run Control Lock
+  Lock or Unlock CPU Run Control; 0: Disable; <b>1: Enable</b>.
+  $EN_DIS
+**/
+  UINT8                       DebugInterfaceLockEnable;
+
+/** Offset 0x07BE - Enable CPU CrashLog GPRs dump
+  Enable or Disable CPU CrashLog GPRs dump; <b>0: Disable</b>; 1: Enable; 2: Only
+  disable Smm GPRs dump
+  0:Disabled, 1:Enabled, 2:Only Smm GPRs Disabled
+**/
+  UINT8                       CrashLogGprs;
+
+/** Offset 0x07BF - Over clocking Lock
+  Lock Overclocking. 0: Disable; <b>1: Enable</b>
+  $EN_DIS
+**/
+  UINT8                       OcLock;
+
+/** Offset 0x07C0 - CPU ratio value
+  This value must be between Max Efficiency Ratio (LFM) and Maximum non-turbo ratio
+  set by Hardware (HFM). Valid Range 0 to 63.
+**/
+  UINT8                       CpuRatio;
+
+/** Offset 0x07C1 - Number of active big cores
+  Number of P-cores to enable in each processor package. Note: Number of P-Cores and
+  E-Cores are looked at together. When both are {0,0
+  0:Disable all big cores, 1:1, 2:2, 3:3, 0xFF:Active all big cores
+**/
+  UINT8                       ActiveCoreCount;
+
+/** Offset 0x07C2 - Reserved
+**/
+  UINT8                       Reserved63[6];
+
+/** Offset 0x07C8 - PrmrrSize
+  Enable/Disable. 0: Disable, define default value of PrmrrSize , 1: enable
+**/
+  UINT32                      PrmrrSize;
+
+/** Offset 0x07CC - Tseg Size
+  Size of SMRAM memory reserved. 0x400000 for Release build and 0x1000000 for Debug build
+  0x0400000:4MB, 0x01000000:16MB
+**/
+  UINT32                      TsegSize;
+
+/** Offset 0x07D0 - SmmRelocationEnable Enable
+  Enable or Disable SmmRelocationEnable. <b>0: Disable</b>, 1:Enable
+  $EN_DIS
+**/
+  UINT8                       SmmRelocationEnable;
+
+/** Offset 0x07D1 - TCC Activation Offset
+  TCC Activation Offset. Offset from factory set TCC activation temperature at which
+  the Thermal Control Circuit must be activated. TCC will be activated at TCC Activation
+  Temperature, in volts. <b>Default = 0h</b>.
+**/
+  UINT8                       TccActivationOffset;
+
+/** Offset 0x07D2 - Reserved
+**/
+  UINT8                       Reserved64[98];
+
+/** Offset 0x0834 - SinitMemorySize
+  Enable/Disable. 0: Disable, define default value of SinitMemorySize , 1: enable
+**/
+  UINT32                      SinitMemorySize;
+
+/** Offset 0x0838 - TxtDprMemoryBase
+  Enable/Disable. 0: Disable, define default value of TxtDprMemoryBase , 1: enable
+**/
+  UINT64                      TxtDprMemoryBase;
+
+/** Offset 0x0840 - TxtHeapMemorySize
+  Enable/Disable. 0: Disable, define default value of TxtHeapMemorySize , 1: enable
+**/
+  UINT32                      TxtHeapMemorySize;
+
+/** Offset 0x0844 - TxtDprMemorySize
+  Reserve DPR memory size (0-255) MB. 0: Disable, define default value of TxtDprMemorySize
+  , 1: enable
+**/
+  UINT32                      TxtDprMemorySize;
+
+/** Offset 0x0848 - TxtLcpPdBase
+  Enable/Disable. 0: Disable, define default value of TxtLcpPdBase , 1: enable
+**/
+  UINT64                      TxtLcpPdBase;
+
+/** Offset 0x0850 - TxtLcpPdSize
+  Enable/Disable. 0: Disable, define default value of TxtLcpPdSize , 1: enable
+**/
+  UINT64                      TxtLcpPdSize;
+
+/** Offset 0x0858 - BiosAcmBase
+  Enable/Disable. 0: Disable, define default value of BiosAcmBase , 1: enable
+**/
+  UINT64                      BiosAcmBase;
+
+/** Offset 0x0860 - BiosAcmSize
+  Enable/Disable. 0: Disable, define default value of BiosAcmSize , 1: enable
+**/
+  UINT32                      BiosAcmSize;
+
+/** Offset 0x0864 - ApStartupBase
+  Enable/Disable. 0: Disable, define default value of BiosAcmBase , 1: enable
+**/
+  UINT32                      ApStartupBase;
+
+/** Offset 0x0868 - TgaSize
+  Enable/Disable. 0: Disable, define default value of TgaSize , 1: enable
+**/
+  UINT32                      TgaSize;
+
+/** Offset 0x086C - IsTPMPresence
+  IsTPMPresence default values
+**/
+  UINT8                       IsTPMPresence;
+
+/** Offset 0x086D - Acoustic Noise Mitigation feature
+  Enabling this option will help mitigate acoustic noise on certain SKUs when the
+  CPU is in deeper C state. <b>0: Disabled</b>; 1: Enabled
+  $EN_DIS
+**/
+  UINT8                       AcousticNoiseMitigation;
+
+/** Offset 0x086E - Reserved
+**/
+  UINT8                       Reserved65[2];
+
+/** Offset 0x0870 - Platform Power Pmax
+  PSYS PMax power, defined in 1/8 Watt increments. <b>0 - Auto</b> Specified in 1/8
+  Watt increments. Range 0-1024 Watts(0-8191). Value of 800 = 100W
+**/
+  UINT16                      PsysPmax;
+
+/** Offset 0x0872 - Thermal Design Current current limit
+  TDC Current Limit, defined in 1/8A increments. Range 0-32767. For a TDC Current
+  Limit of 125A, enter 1000. 0 = 0 Amps. <b>0: Auto</b>. [0] for IA, [1] for GT,
+  [2] for SA, [3] for atom, [4]-[5] are Reserved.
+**/
+  UINT16                      TdcCurrentLimit[6];
+
+/** Offset 0x087E - AcLoadline
+  AC Loadline defined in 1/100 mOhms. A value of 100 = 1.00 mOhm, and 1255 = 12.55
+  mOhm. Range is 0-6249 (0-62.49 mOhms). 0 = AUTO/HW default. [0] for IA, [1] for
+  GT, [2] for SA, [3] through [5] are Reserved.
+**/
+  UINT16                      AcLoadline[6];
+
+/** Offset 0x088A - DcLoadline
+  DC Loadline defined in 1/100 mOhms. A value of 100 = 1.00 mOhm, and 1255 = 12.55
+  mOhm. Range is 0-6249 (0-62.49 mOhms). 0 = AUTO/HW default. [0] for IA, [1] for
+  GT, [2] for SA, [3] through [5] are Reserved.
+**/
+  UINT16                      DcLoadline[6];
+
+/** Offset 0x0896 - Reserved
+**/
+  UINT8                      Reserved66[116];
+
+/** Offset 0x090A - Thermal Design Current enable/disable
+  Thermal Design Current enable/disable; <b>0: Disable</b>; 1: Enable. [0] for IA,
+  [1] for GT, [2] for SA, [3] for atom, [4]-[5] are Reserved.
+**/
+  UINT8                       TdcEnable[6];
+
+/** Offset 0x0910 - Reserved
+**/
+  UINT8                       Reserved67[6];
+
+/** Offset 0x0916 - Disable Fast Slew Rate for Deep Package C States for VR domains
+  This option needs to be configured to reduce acoustic noise during deeper C states.
+  False: Don't disable Fast ramp during deeper C states; True: Disable Fast ramp
+  during deeper C state. [0] for IA, [1] for GT, [2] for SA, [3] through [5] are
+  Reserved. <b>0: False</b>; 1: True
+  $EN_DIS
+**/
+  UINT8                       FastPkgCRampDisable[6];
+
+/** Offset 0x091C - Slew Rate configuration for Deep Package C States for VR domains
+  Set VR IA/GT/SA Slow Slew Rate for Deep Package C State ramp time; Slow slew rate
+  equals to Fast divided by number, the number is 2, 4, 8, 16 to slow down the slew
+  rate to help minimize acoustic noise; divide by 16 is disabled for GT/SA. <b>0:
+  Fast/2</b>; 1: Fast/4; 2: Fast/8; 3: Fast/16; 0xFF: Ignore the configuration
+  0: Fast/2, 1: Fast/4, 2: Fast/8, 3: Fast/16, 0xFF: Ignore the configuration
+**/
+  UINT8                       SlowSlewRate[6];
+
+/** Offset 0x0922 - Reserved
+**/
+  UINT8                       Reserved68[6];
+
+/** Offset 0x0928 - Thermal Design Current time window
+  Auto = 0 is default. Range is from 1ms to 448s. <b>0: Auto</b>. [0] for IA, [1]
+  for GT, [2] for SA, [3] for atom, [4]-[5] are Reserved.
+**/
+  UINT32                      TdcTimeWindow[6];
+
+/** Offset 0x0940 - Reserved
+**/
+  UINT8                       Reserved69[8];
+
+/** Offset 0x0948 - DLVR RFI Enable
+  Enable/Disable DLVR RFI frequency hopping. 0: Disable; <b>1: Enable</b>.
+  $EN_DIS
+**/
+  UINT8                       DlvrRfiEnable;
+
+/** Offset 0x0949 - Reserved
+**/
+  UINT8                       Reserved70[13];
+
+/** Offset 0x0956 - VR Fast Vmode ICC Limit support
+  Voltage Regulator Fast Vmode ICC Limit. A value of 400 = 100A. A value of 0 corresponds
+  to feature disabled (no reactive protection). This value represents the current
+  threshold where the VR would initiate reactive protection if Fast Vmode is enabled.
+  The value is represented in 1/4 A increments. Range 0-2040. [0] for IA, [1] for
+  GT, [2] for SA, [3] through [5] are Reserved.
+**/
+  UINT16                      IccLimit[6];
+
+/** Offset 0x0962 - Enable/Disable VR FastVmode. The VR will initiate reactive protection if Fast Vmode is enabled.
+  Enable/Disable VR FastVmode; <b>0: Disable</b>; 1: Enable.For all VR by domain
+  0: Disable, 1: Enable
+**/
+  UINT8                       EnableFastVmode[6];
+
+/** Offset 0x0968 - Enable/Disable CEP
+  Control for enabling/disabling CEP (Current Excursion Protection). <b>0: Disable</b>; 1: Enable
+  0: Disable, 1: Enable
+**/
+  UINT8                       CepEnable[6];
+
+/** Offset 0x096E - Reserved
+**/
+  UINT8                       Reserved71[28];
+
+/** Offset 0x098A - PCH Port80 Route
+  Control where the Port 80h cycles are sent, 0: LPC; 1: PCI.
+  $EN_DIS
+**/
+  UINT8                       PchPort80Route;
+
+/** Offset 0x098B - GPIO Override
+  Gpio Override Level - FSP will not configure any GPIOs and rely on GPIO setings
+  before moved to FSP. Available configurations 0: Disable; 1: Level 1 - Skips GPIO
+  configuration in PEI/FSPM/FSPT phase;2: Level 2 - Reserved for future use
+**/
+  UINT8                       GpioOverride;
+
+/** Offset 0x098C - Reserved
+**/
+  UINT8                       Reserved72[4];
+
+/** Offset 0x0990 - PMR Size
+  Size of PMR memory buffer. 0x400000 for normal boot and 0x200000 for S3 boot
+**/
+  UINT32                      DmaBufferSize;
+
+/** Offset 0x0994 - The policy for VTd driver behavior
+  BIT0: Enable IOMMU during boot, BIT1: Enable IOMMU when transfer control to OS
+**/
+  UINT8                       PreBootDmaMask;
+
+/** Offset 0x0995 - State of DMA_CONTROL_GUARANTEE bit in the DMAR table
+  0=Disable/Clear, 1=Enable/Set
+  $EN_DIS
+**/
+  UINT8                       DmaControlGuarantee;
+
+/** Offset 0x0996 - Disable VT-d
+  0=Enable/FALSE(VT-d enabled), 1=Disable/TRUE (VT-d disabled)
+  $EN_DIS
+**/
+  UINT8                       VtdDisable;
+
+/** Offset 0x0997 - Reserved
+**/
+  UINT8                       Reserved73;
+
+/** Offset 0x0998 - Base addresses for VT-d function MMIO access
+  Base addresses for VT-d MMIO access per VT-d engine
+**/
+  UINT32                      VtdBaseAddress[9];
+
+/** Offset 0x09BC - Reserved
+**/
+  UINT8                       Reserved74[20];
+
+/** Offset 0x09D0 - MMIO Size
+  Size of MMIO space reserved for devices. 0(Default)=Auto, non-Zero=size in MB
+**/
+  UINT16                      MmioSize;
+
+/** Offset 0x09D2 - MMIO size adjustment for AUTO mode
+  Positive number means increasing MMIO size, Negative value means decreasing MMIO
+  size: 0 (Default)=no change to AUTO mode MMIO size
+**/
+  UINT16                      MmioSizeAdjustment;
+
+/** Offset 0x09D4 - Reserved
+**/
+  UINT8                      Reserved75[36];
+
+/** Offset 0x09F8 - Enable above 4GB MMIO resource support
+  Enable/disable above 4GB MMIO resource support
+  $EN_DIS
+**/
+  UINT8                       EnableAbove4GBMmio;
+
+/** Offset 0x09F9 - Enable/Disable SA CRID
+  Enable: SA CRID, Disable (Default): SA CRID
+  $EN_DIS
+**/
+  UINT8                       CridEnable;
+
+/** Offset 0x09FA - Reserved
+**/
+  UINT8                       Reserved76[10];
+
+/** Offset 0x0A04 - Enable/Disable CrashLog Device
+  Enable or Disable CrashLog/Telemetry Device  0- Disable, <b>1- Enable</b>
+  $EN_DIS
+**/
+  UINT32                      CpuCrashLogDevice;
+
+/** Offset 0x0A08 - Reserved
+**/
+  UINT8                      Reserved77[20];
+
+/** Offset 0x0A1C - Platform Debug Option
+  Enabled Trace active: TraceHub is enabled and trace is active, blocks s0ix.\n
+  \n
+  Enabled Trace ready: TraceHub is enabled and allowed S0ix.\n
+  \n
+  Enabled Trace power off: TraceHub is powergated, provide setting close to functional
+  low power state\n
+  \n
+  Manual: user needs to configure Advanced Debug Settings manually, aimed at advanced users
+  0:Disabled, 2:Enabled Trace Active, 4:Enabled Trace Ready, 6:Enable Trace Power-Off, 7:Manual
+**/
+  UINT8                       PlatformDebugOption;
+
+/** Offset 0x0A1D - Reserved
+**/
+  UINT8                       Reserved78[14];
+
+/** Offset 0x0A2B - Program GPIOs for LFP on DDI port-A device
+  0=Disabled,1(Default)=eDP, 2=MIPI DSI
+  0:Disabled, 1:eDP, 2:MIPI DSI
+**/
+  UINT8                       DdiPortAConfig;
+
+/** Offset 0x0A2C - Reserved
+**/
+  UINT8                      Reserved79[2];
+
+/** Offset 0x0A2E - Program GPIOs for LFP on DDI port-B device
+  0(Default)=Disabled,1=eDP, 2=MIPI DSI
+  0:Disabled, 1:eDP, 2:MIPI DSI
+**/
+  UINT8                       DdiPortBConfig;
+
+/** Offset 0x0A2F - Enable or disable HPD of DDI port A
+  0(Default)=Disable, 1=Enable
+  $EN_DIS
+**/
+  UINT8                       DdiPortAHpd;
+
+/** Offset 0x0A30 - Enable or disable HPD of DDI port B
+  0=Disable, 1(Default)=Enable
+  $EN_DIS
+**/
+  UINT8                       DdiPortBHpd;
+
+/** Offset 0x0A31 - Enable or disable HPD of DDI port C
+  0(Default)=Disable, 1=Enable
+  $EN_DIS
+**/
+  UINT8                       DdiPortCHpd;
+
+/** Offset 0x0A32 - Enable or disable HPD of DDI port 1
+  0=Disable, 1(Default)=Enable
+  $EN_DIS
+**/
+  UINT8                       DdiPort1Hpd;
+
+/** Offset 0x0A33 - Enable or disable HPD of DDI port 2
+  0(Default)=Disable, 1=Enable
+  $EN_DIS
+**/
+  UINT8                       DdiPort2Hpd;
+
+/** Offset 0x0A34 - Enable or disable HPD of DDI port 3
+  0(Default)=Disable, 1=Enable
+  $EN_DIS
+**/
+  UINT8                       DdiPort3Hpd;
+
+/** Offset 0x0A35 - Enable or disable HPD of DDI port 4
+  0(Default)=Disable, 1=Enable
+  $EN_DIS
+**/
+  UINT8                       DdiPort4Hpd;
+
+/** Offset 0x0A36 - Enable or disable DDC of DDI port A
+  0(Default)=Disable, 1=Enable
+  $EN_DIS
+**/
+  UINT8                       DdiPortADdc;
+
+/** Offset 0x0A37 - Enable or disable DDC of DDI port B
+  0=Disable, 1(Default)=Enable
+  $EN_DIS
+**/
+  UINT8                       DdiPortBDdc;
+
+/** Offset 0x0A38 - Enable or disable DDC of DDI port C
+  0(Default)=Disable, 1=Enable
+  $EN_DIS
+**/
+  UINT8                       DdiPortCDdc;
+
+/** Offset 0x0A39 - Enable DDC setting of DDI Port 1
+  0(Default)=Disable, 1=Enable
+  $EN_DIS
+**/
+  UINT8                       DdiPort1Ddc;
+
+/** Offset 0x0A3A - Enable DDC setting of DDI Port 2
+  0(Default)=Disable, 1=Enable
+  $EN_DIS
+**/
+  UINT8                       DdiPort2Ddc;
+
+/** Offset 0x0A3B - Enable DDC setting of DDI Port 3
+  0(Default)=Disable, 1=Enable
+  $EN_DIS
+**/
+  UINT8                       DdiPort3Ddc;
+
+/** Offset 0x0A3C - Enable DDC setting of DDI Port 4
+  0(Default)=Disable, 1=Enable
+  $EN_DIS
+**/
+  UINT8                       DdiPort4Ddc;
+
+/** Offset 0x0A3D - Reserved
+**/
+  UINT8                       Reserved80[3];
+
+/** Offset 0x0A40 - Temporary MMIO address for GMADR
+  The reference code will use this as Temporary MMIO address space to access GMADR
+  Registers.Platform should provide conflict free Temporary MMIO Range: GmAdr to
+  (GmAdr + 256MB). Default is (PciExpressBaseAddress - 256MB) to (PciExpressBaseAddress - 0x1)
+**/
+  UINT64                      LMemBar;
+
+/** Offset 0x0A48 - Temporary MMIO address for GTTMMADR
+  The reference code will use this as Temporary MMIO address space to access GTTMMADR
+  Registers.Platform should provide conflict free Temporary MMIO Range: GttMmAdr
+  to (GttMmAdr + 2MB MMIO + 6MB Reserved + GttSize). Default is (GmAdr - (2MB MMIO
+  + 6MB Reserved + GttSize)) to (GmAdr - 0x1) (Where GttSize = 8MB)
+**/
+  UINT64                      GttMmAdr;
+
+/** Offset 0x0A50 - Reserved
+**/
+  UINT8                      Reserved81[2];
+
+/** Offset 0x0A52 - Enable/Disable Memory Bandwidth Compression
+  0=Disable, 1(Default)=Enable
+  $EN_DIS
+**/
+  UINT8                       MemoryBandwidthCompression;
+
+/** Offset 0x0A53 - Panel Power Enable
+  Control for enabling/disabling VDD force bit (Required only for early enabling of
+  eDP panel). 0=Disable, 1(Default)=Enable
+  $EN_DIS
+**/
+  UINT8                       PanelPowerEnable;
+
+/** Offset 0x0A54 - Selection of the primary display device
+  3(Default)=AUTO, 0=IGFX, 4=Hybrid Graphics
+  3:AUTO, 0:IGFX, 4:HG
+**/
+  UINT8                       PrimaryDisplay;
+
+/** Offset 0x0A55 - Internal Graphics Data Stolen Memory GSM2
+  Size of memory preallocated for internal graphics GSM2.
+  0:2GB, 1:4GB, 2:6GB, 3:8GB, 4:10GB, 5:12GB, 6:14GB, 7:16GB, 8:18GB, 9:20GB, 10:22GB,
+  11:24GB, 12:26GB, 13:28GB, 14:30GB, 15:32GB, 0xFF:No Allocation
+**/
+  UINT8                       IGpuGsm2Size;
+
+/** Offset 0x0A56 - Reserved
+**/
+  UINT8                       Reserved82[2];
+
+/** Offset 0x0A58 - Intel Graphics VBT (Video BIOS Table) Size
+  Size of Internal Graphics VBT Image
+**/
+  UINT32                      VbtSize;
+
+/** Offset 0x0A5C - Reserved
+**/
+  UINT8                       Reserved83[4];
+
+/** Offset 0x0A60 - Graphics Configuration Ptr
+  Points to VBT
+**/
+  UINT64                      VbtPtr;
+
+/** Offset 0x0A68 - SOL Training Message Pointer
+  Points to SOL Message String
+**/
+  UINT64                      VgaMessage;
+
+/** Offset 0x0A70 - Platform LID Status for LFP Displays.
+  LFP Display Lid Status (LID_STATUS enum): 0 (Default): LidClosed, 1: LidOpen.
+  0: LidClosed, 1: LidOpen
+**/
+  UINT8                       LidStatus;
+
+/** Offset 0x0A71 - Control SOL VGA Initialition sequence
+  Initialise SOL Init, BIT0 - (0 : Disable VGA Support, 1 : Enable VGA Support),,
+  BIT1 - (0 : VGA Text Mode 3, 1 : VGA Graphics Mode 12), BIT2 - (0 : VGA Exit Supported,
+  1: NO VGA Exit)
+  0:VGA Disable, 1:Mode 3 VGA, 2:Mode 12 VGA
+**/
+  UINT8                       VgaInitControl;
+
+/** Offset 0x0A72 - Reserved
+**/
+  UINT8                      Reserved84[16];
+
+/** Offset 0x0A82 - TCSS USB HOST (xHCI) Enable
+  Set TCSS XHCI. 0:Disabled  1:Enabled - Must be enabled if xDCI is enabled below
+  $EN_DIS
+**/
+  UINT8                       TcssXhciEn;
+
+/** Offset 0x0A83 - Reserved
+**/
+  UINT8                       Reserved85[4];
+
+/** Offset 0x0A87 - TCSS Type C Port 0
+  Set TCSS Type C Port 0 Type, Options are 0=DISABLE, 1=DP_ONLY, 2=NO_TBT, 3=NO_PCIE,
+  7=FULL_FUN
+  0:DISABLE, 1:DP_ONLY, 2:NO_TBT, 3: NO_PCIE, 7:FULL_FUN
+**/
+  UINT8                       TcssPort0;
+
+/** Offset 0x0A88 - TCSS Type C Port 1
+  Set TCSS Type C Port 1 Type, Options are 0=DISABLE, 1=DP_ONLY, 2=NO_TBT, 3=NO_PCIE,
+  7=FULL_FUN
+  0:DISABLE, 1:DP_ONLY, 2:NO_TBT, 3: NO_PCIE, 7:FULL_FUN
+**/
+  UINT8                       TcssPort1;
+
+/** Offset 0x0A89 - TCSS Type C Port 2
+  Set TCSS Type C Port 2 Type, Options are 0=DISABLE, 1=DP_ONLY, 2=NO_TBT, 3=NO_PCIE,
+  7=FULL_FUN
+  0:DISABLE, 1:DP_ONLY, 2:NO_TBT, 3: NO_PCIE, 7:FULL_FUN
+**/
+  UINT8                       TcssPort2;
+
+/** Offset 0x0A8A - TCSS Type C Port 3
+  Set TCSS Type C Port 3 Type, Options are 0=DISABLE, 1=DP_ONLY, 2=NO_TBT, 3=NO_PCIE,
+  7=FULL_FUN
+  0:DISABLE, 1:DP_ONLY, 2:NO_TBT, 3: NO_PCIE, 7:FULL_FUN
+**/
+  UINT8                       TcssPort3;
+
+/** Offset 0x0A8B - Reserved
+**/
+  UINT8                       Reserved86;
+
+/** Offset 0x0A8C - TypeC port GPIO setting
+  GPIO Pin number for Type C Aux orientation setting, use the GpioPad that is defined
+  in GpioPinsXXX.h as argument.(XXX is platform name, Ex: Ptl = PantherLake)
+**/
+  UINT32                      IomTypeCPortPadCfg[12];
+
+/** Offset 0x0ABC - TCSS Aux Orientation Override Enable
+  Bits 0, 2, ... 10 control override enables, bits 1, 3, ... 11 control overrides
+**/
+  UINT16                      TcssAuxOri;
+
+/** Offset 0x0ABE - TCSS HSL Orientation Override Enable
+  Bits 0, 2, ... 10 control override enables, bits 1, 3, ... 11 control overrides
+**/
+  UINT16                      TcssHslOri;
+
+/** Offset 0x0AC0 - CNVi DDR RFI Mitigation
+  Enable/Disable DDR RFI Mitigation. Default is ENABLE. 0: DISABLE, 1: ENABLE
+  $EN_DIS
+**/
+  UINT8                       CnviDdrRfim;
+
+/** Offset 0x0AC1 - SOC Trace Hub Mode
+  Enable/Disable SOC TraceHub
+  $EN_DIS
+**/
+  UINT8                       SocTraceHubMode;
+
+/** Offset 0x0AC2 - SOC Trace Hub Memory Region 0 buffer Size
+  Select size of memory region 0 buffer. Memory allocated by BIOS only applies to
+  ITH tool running on the host. For ITH tool running on the target, choose None/OS,
+  memory shall be allocated by tool. User should be cautious to choose the amount
+  of memory. If chosen size is larger than half of system memory, setup will automatically
+  rollback to default value.
+  0x00:1MB, 0x03:8MB, 0x06:64MB, 0x07:128MB, 0x08:256MB, 0x09:512MB, 0x0A:1GB, 0x0B:2GB,
+  0x0C:4GB, 0x0D:8GB, 0x0E:0MB
+**/
+  UINT16                      SocTraceHubMemReg0Size;
+
+/** Offset 0x0AC4 - SOC Trace Hub Memory Region 0 buffer Size
+  Select size of memory region 1 buffer. Memory allocated by BIOS only applies to
+  ITH tool running on the host. For ITH tool running on the target, choose None/OS,
+  memory shall be allocated by tool. User should be cautious to choose the amount
+  of memory. If chosen size is larger than half of system memory, setup will automatically
+  rollback to default value.
+  0x00:1MB, 0x03:8MB, 0x06:64MB, 0x07:128MB, 0x08:256MB, 0x09:512MB, 0x0A:1GB, 0x0B:2GB,
+  0x0C:4GB, 0x0D:8GB, 0x0E:0MB
+**/
+  UINT16                      SocTraceHubMemReg1Size;
+
+/** Offset 0x0AC6 - Internal Graphics Pre-allocated Memory
+  Size of memory preallocated for internal graphics.
+  0x00:0MB, 0x01:32MB, 0x02:64MB, 0x03:96MB, 0x04:128MB, 0xF0:4MB, 0xF1:8MB, 0xF2:12MB,
+  0xF3:16MB, 0xF4:20MB, 0xF5:24MB, 0xF6:28MB, 0xF7:32MB, 0xF8:36MB, 0xF9:40MB, 0xFA:44MB,
+  0xFB:48MB, 0xFC:52MB, 0xFD:56MB, 0xFE:60MB
+**/
+  UINT16                      IgdDvmt50PreAlloc;
+
+/** Offset 0x0AC8 - Internal Graphics
+  Expect 3 values from 0 to 2
+  2:AUTO, 1:Enable, 0:Disable
+**/
+  UINT8                       InternalGraphics;
+
+/** Offset 0x0AC9 - Reserved
+**/
+  UINT8                       Reserved87;
+
+/** Offset 0x0ACA - DLL Weak Lock Support
+  Enables/Disable DLL Weak Lock Support
+  $EN_DIS
+**/
+  UINT8                       WeaklockEn;
+
+/** Offset 0x0ACB - Reserved
+**/
+  UINT8                       Reserved88;
+
+/** Offset 0x0ACC - Rx DQS Delay Comp Support
+  Enables/Disable Rx DQS Delay Comp Support
+  $EN_DIS
+**/
+  UINT8                       RxDqsDelayCompEn;
+
+/** Offset 0x0ACD - Reserved
+**/
+  UINT8                       Reserved89[2];
+
+/** Offset 0x0ACF - Mrc Failure On Unsupported Dimm
+  Enables/Disable Mrc Failure On Unsupported Dimm
+  $EN_DIS
+**/
+  UINT8                       MrcFailureOnUnsupportedDimm;
+
+/** Offset 0x0AD0 - Reserved
+**/
+  UINT8                      Reserved90[4];
+
+/** Offset 0x0AD4 - DynamicMemoryBoost
+  Enable/Disable Dynamic Memory Boost Feature. Only valid if SpdProfileSelected is
+  an XMP Profile; otherwise ignored. <b>0=Disabled</b>, 1=Enabled.
+  $EN_DIS
+**/
+  UINT32                      DynamicMemoryBoost;
+
+/** Offset 0x0AD8 - RealtimeMemoryFrequency
+  Enable/Disable Realtime Memory Frequency feature. Only valid if SpdProfileSelected
+  is an XMP Profile; otherwise ignored. <b>0=Disabled</b>, 1=Enabled.
+  $EN_DIS
+**/
+  UINT32                      RealtimeMemoryFrequency;
+
+/** Offset 0x0ADC - Reserved
+**/
+  UINT8                      Reserved91[9];
+
+/** Offset 0x0AE5 - Vref Offset
+  Offset to be applied to DDRDATACH0_CR_DDRCRDATAOFFSETTRAIN.VrefOffset
+  0xFA:-6, 0xFB:-5, 0xFC:-4, 0xFD:-3, 0xFE:-2, 0xFF:-1, 0:0, 1:+1, 2:+2, 3:+3, 4:+4,
+  5:+5, 6:+6
+**/
+  UINT8                       VrefOffset;
+
+/** Offset 0x0AE6 - Reserved
+**/
+  UINT8                       Reserved92[2];
+
+/** Offset 0x0AE8 - tRRSG Delta
+  Delay between Read-to-Read commands in the same Bank Group. 0 - Auto. Signed TAT
+  delta is (Value - 128). Input value range of [1..255] will give a TAT delta range
+  of [-127..127]
+**/
+  UINT8                       tRRSG;
+
+/** Offset 0x0AE9 - tRRDG Delta
+  Delay between Read-to-Read commands in different Bank Group. 0 - Auto. Signed TAT
+  delta is (Value - 128). Input value range of [1..255] will give a TAT delta range
+  of [-127..127]
+**/
+  UINT8                       tRRDG;
+
+/** Offset 0x0AEA - tRRDR Delta
+  Delay between Read-to-Read commands in different Ranks. 0 - Auto. Signed TAT delta
+  is (Value - 128). Input value range of [1..255] will give a TAT delta range of
+  [-127..127]
+**/
+  UINT8                       tRRDR;
+
+/** Offset 0x0AEB - tRRDD Delta
+  Delay between Read-to-Read commands in different DIMMs. 0 - Auto. Signed TAT delta
+  is (Value - 128). Input value range of [1..255] will give a TAT delta range of
+  [-127..127]
+**/
+  UINT8                       tRRDD;
+
+/** Offset 0x0AEC - tWRSG Delta
+  Delay between Write-to-Read commands in the same Bank Group. 0 - Auto. Signed TAT
+  delta is (Value - 128). Input value range of [1..255] will give a TAT delta range
+  of [-127..127]
+**/
+  UINT8                       tWRSG;
+
+/** Offset 0x0AED - tWRDG Delta
+  Delay between Write-to-Read commands in different Bank Group. 0 - Auto. Signed TAT
+  delta is (Value - 128). Input value range of [1..255] will give a TAT delta range
+  of [-127..127]
+**/
+  UINT8                       tWRDG;
+
+/** Offset 0x0AEE - tWRDR Delta
+  Delay between Write-to-Read commands in different Ranks. 0 - Auto. Signed TAT delta
+  is (Value - 128). Input value range of [1..255] will give a TAT delta range of
+  [-127..127]
+**/
+  UINT8                       tWRDR;
+
+/** Offset 0x0AEF - tWRDD Delta
+  Delay between Write-to-Read commands in different DIMMs. 0 - Auto. Signed TAT delta
+  is (Value - 128). Input value range of [1..255] will give a TAT delta range of
+  [-127..127]
+**/
+  UINT8                       tWRDD;
+
+/** Offset 0x0AF0 - tWWSG Delta
+  Delay between Write-to-Write commands in the same Bank Group. 0 - Auto. Signed TAT
+  delta is (Value - 128). Input value range of [1..255] will give a TAT delta range
+  of [-127..127]
+**/
+  UINT8                       tWWSG;
+
+/** Offset 0x0AF1 - tWWDG Delta
+  Delay between Write-to-Write commands in different Bank Group. 0 - Auto. Signed
+  TAT delta is (Value - 128). Input value range of [1..255] will give a TAT delta
+  range of [-127..127]
+**/
+  UINT8                       tWWDG;
+
+/** Offset 0x0AF2 - tWWDR Delta
+  Delay between Write-to-Write commands in different Ranks. 0 - Auto. Signed TAT delta
+  is (Value - 128). Input value range of [1..255] will give a TAT delta range of
+  [-127..127]
+**/
+  UINT8                       tWWDR;
+
+/** Offset 0x0AF3 - tWWDD Delta
+  Delay between Write-to-Write commands in different DIMMs. 0 - Auto. Signed TAT delta
+  is (Value - 128). Input value range of [1..255] will give a TAT delta range of
+  [-127..127]
+**/
+  UINT8                       tWWDD;
+
+/** Offset 0x0AF4 - tRWSG Delta
+  Delay between Read-to-Write commands in the same Bank Group. 0 - Auto. Signed TAT
+  delta is (Value - 128). Input value range of [1..255] will give a TAT delta range
+  of [-127..127]
+**/
+  UINT8                       tRWSG;
+
+/** Offset 0x0AF5 - tRWDG Delta
+  Delay between Read-to-Write commands in different Bank Group. 0 - Auto. Signed TAT
+  delta is (Value - 128). Input value range of [1..255] will give a TAT delta range
+  of [-127..127]
+**/
+  UINT8                       tRWDG;
+
+/** Offset 0x0AF6 - tRWDR Delta
+  Delay between Read-to-Write commands in different Ranks. 0 - Auto. Signed TAT delta
+  is (Value - 128). Input value range of [1..255] will give a TAT delta range of
+  [-127..127]
+**/
+  UINT8                       tRWDR;
+
+/** Offset 0x0AF7 - tRWDD Delta
+  Delay between Read-to-Write commands in different DIMMs. 0 - Auto. Signed TAT delta
+  is (Value - 128). Input value range of [1..255] will give a TAT delta range of
+  [-127..127]
+**/
+  UINT8                       tRWDD;
+
+/** Offset 0x0AF8 - Reserved
+**/
+  UINT8                       Reserved93[41];
+
+/** Offset 0x0B21 - Channel to CKD QCK Mapping
+  Specify Channel to CKD QCK Mapping for CH0D0/CH0D1/CH1D0&CH1D1
+**/
+  UINT8                       ChannelToCkdQckMapping[8];
+
+/** Offset 0x0B29 - DDRIO Clock to CKD DIMM
+  Specify DDRIO Clock to CKD DIMM for CH0D0/CH0D1/CH1D0&CH1D1
+**/
+  UINT8                       PhyClockToCkdDimm[8];
+
+/** Offset 0x0B31 - Reserved
+**/
+  UINT8                       Reserved94[55];
+} FSP_M_CONFIG;
+
+/** Fsp M UPD Configuration
+**/
+typedef struct {
+
+/** Offset 0x0000
+**/
+  FSP_UPD_HEADER              FspUpdHeader;
+
+/** Offset 0x0020
+**/
+  FSPM_ARCH2_UPD              FspmArchUpd;
+
+/** Offset 0x0060
+**/
+  FSP_M_CONFIG                FspmConfig;
+
+/** Offset 0x0B68
+**/
+  UINT8                       FspmRsvd3834[6];
+
+/** Offset 0x0B6E
+**/
+  UINT16                      UpdTerminator;
+} FSPM_UPD;
+
+#pragma pack()
+
+#endif
diff --git a/src/vendorcode/intel/fsp/fsp2_0/wildcatlake/FspsUpd.h b/src/vendorcode/intel/fsp/fsp2_0/wildcatlake/FspsUpd.h
new file mode 100644
index 0000000000..0b540c7e14
--- /dev/null
+++ b/src/vendorcode/intel/fsp/fsp2_0/wildcatlake/FspsUpd.h
@@ -0,0 +1,2426 @@
+/** @file
+
+Copyright (c) 2025, Intel Corporation. All rights reserved.<BR>
+
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+
+* Redistributions of source code must retain the above copyright notice, this
+  list of conditions and the following disclaimer.
+* Redistributions in binary form must reproduce the above copyright notice, this
+  list of conditions and the following disclaimer in the documentation and/or
+  other materials provided with the distribution.
+* Neither the name of Intel Corporation nor the names of its contributors may
+  be used to endorse or promote products derived from this software without
+  specific prior written permission.
+
+  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
+  THE POSSIBILITY OF SUCH DAMAGE.
+
+  This file is automatically generated. Please do NOT modify !!!
+
+**/
+
+#ifndef __FSPSUPD_H__
+#define __FSPSUPD_H__
+
+#include <FspUpd.h>
+
+#pragma pack(1)
+
+
+///
+/// Azalia Header structure
+///
+typedef struct {
+  UINT16 VendorId;           ///< Codec Vendor ID
+  UINT16 DeviceId;           ///< Codec Device ID
+  UINT8  RevisionId;         ///< Revision ID of the codec. 0xFF matches any revision.
+  UINT8  SdiNum;             ///< SDI number, 0xFF matches any SDI.
+  UINT16 DataDwords;         ///< Number of data DWORDs pointed by the codec data buffer.
+  UINT32 Reserved;           ///< Reserved for future use. Must be set to 0.
+} AZALIA_HEADER;
+
+///
+/// Audio Azalia Verb Table structure
+///
+typedef struct {
+  AZALIA_HEADER Header;      ///< AZALIA PCH header
+  UINT32        *Data;       ///< Pointer to the data buffer. Its length is specified in the header
+} AUDIO_AZALIA_VERB_TABLE;
+
+///
+/// Refer to the definition of PCH_INT_PIN
+///
+typedef enum {
+  SiPchNoInt,        ///< No Interrupt Pin
+  SiPchIntA,
+  SiPchIntB,
+  SiPchIntC,
+  SiPchIntD
+} SI_PCH_INT_PIN;
+///
+/// The PCH_DEVICE_INTERRUPT_CONFIG block describes interrupt pin, IRQ and interrupt mode for PCH device.
+///
+typedef struct {
+  UINT8        Device;                  ///< Device number
+  UINT8        Function;                ///< Device function
+  UINT8        IntX;                    ///< Interrupt pin: INTA-INTD (see SI_PCH_INT_PIN)
+  UINT8        Irq;                     ///< IRQ to be set for device.
+} SI_PCH_DEVICE_INTERRUPT_CONFIG;
+
+#define SI_PCH_MAX_DEVICE_INTERRUPT_CONFIG  64       ///< Number of all PCH devices
+
+
+/** Fsp S Configuration
+**/
+typedef struct {
+
+/** Offset 0x0040 - BgpdtHash[6]
+  BgpdtHash values
+**/
+  UINT64                      BgpdtHash[6];
+
+/** Offset 0x0070 - BiosGuardAttr
+  BiosGuardAttr default values
+**/
+  UINT32                      BiosGuardAttr;
+
+/** Offset 0x0074 - Reserved
+**/
+  UINT8                       Reserved0[4];
+
+/** Offset 0x0078 - BiosGuardModulePtr
+  BiosGuardModulePtr default values
+**/
+  UINT64                      BiosGuardModulePtr;
+
+/** Offset 0x0080 - Reserved
+**/
+  UINT8                      Reserved1[17];
+
+/** Offset 0x0091 - PCH eSPI Link Configuration Lock (SBLCL)
+  Enable/Disable lock of communication through SET_CONFIG/GET_CONFIG to eSPI target
+  addresseses from range 0x0 - 0x7FF
+  $EN_DIS
+**/
+  UINT8                       PchEspiLockLinkConfiguration;
+
+/** Offset 0x0092 - Enable Host C10 reporting through eSPI
+  Enable/disable Host C10 reporting to Device via eSPI Virtual Wire.
+  $EN_DIS
+**/
+  UINT8                       PchEspiHostC10ReportEnable;
+
+/** Offset 0x0093 - Espi Lgmr Memory Range decode
+  This option enables or disables espi lgmr
+  $EN_DIS
+**/
+  UINT8                       PchEspiLgmrEnable;
+
+/** Offset 0x0094 - Reserved
+**/
+  UINT8                       Reserved2[4];
+
+/** Offset 0x0098 - CpuBistData
+  Pointer CPU BIST Data
+**/
+  UINT64                      CpuBistData;
+
+/** Offset 0x00A0 - CpuMpPpi
+  <b>Optional</b> pointer to the boot loader's implementation of EFI_PEI_MP_SERVICES_PPI.
+  If not NULL, FSP will use the boot loader's implementation of multiprocessing.
+  See section 5.1.4 of the FSP Integration Guide for more details.
+**/
+  UINT64                      CpuMpPpi;
+
+/** Offset 0x00A8 - Enable/Disable CrashLog
+  Enable(Default): Enable CPU CrashLog, Disable: Disable CPU CrashLog
+  $EN_DIS
+**/
+  UINT8                       CpuCrashLogEnable;
+
+/** Offset 0x00A9 - Reserved
+**/
+  UINT8                       Reserved3[7];
+
+/** Offset 0x00B0 - MicrocodeRegionBase
+  Memory Base of Microcode Updates
+**/
+  UINT64                      MicrocodeRegionBase;
+
+/** Offset 0x00B8 - MicrocodeRegionSize
+  Size of Microcode Updates
+**/
+  UINT64                      MicrocodeRegionSize;
+
+/** Offset 0x00C0 - Enable or Disable TXT
+  Enables utilization of additional hardware capabilities provided by Intel (R) Trusted
+  Execution Technology. Changes require a full power cycle to take effect. <b>0:
+  Disable</b>, 1: Enable.
+  $EN_DIS
+**/
+  UINT8                       TxtEnable;
+
+/** Offset 0x00C1 - PpinSupport to view Protected Processor Inventory Number
+  PPIN Feature Support to view Protected Processor Inventory Number. Disable to turn
+  off this feature. When 'PPIN Enable Mode' is selected, this shows second option
+  where feature can be enabled based on EOM (End of Manufacturing) flag or it is
+  always enabled
+  0: Disable, 1: Enable, 2: Auto
+**/
+  UINT8                       PpinSupport;
+
+/** Offset 0x00C2 - Advanced Encryption Standard (AES) feature
+  Enable or Disable Advanced Encryption Standard (AES) feature; </b>0: Disable; <b>1: Enable
+  $EN_DIS
+**/
+  UINT8                       AesEnable;
+
+/** Offset 0x00C3 - AvxDisable
+  Enable/Disable the AVX and AVX2 Instructions
+  0: Enable, 1: Disable
+**/
+  UINT8                       AvxDisable;
+
+/** Offset 0x00C4 - Reserved
+**/
+  UINT8                       Reserved4;
+
+/** Offset 0x00C5 - P-state ratios for max 16 version of custom P-state table
+  P-state ratios for max 16 version of custom P-state table. This table is used for
+  OS versions limited to a max of 16 P-States. If the first entry of this table is
+  0, or if Number of Entries is 16 or less, then this table will be ignored, and
+  up to the top 16 values of the StateRatio table will be used instead. Valid Range
+  of each entry is 0 to 0x7F
+**/
+  UINT8                       StateRatioMax16[16];
+
+/** Offset 0x00D5 - Enable or Disable Intel SpeedStep Technology
+  Allows more than two frequency ranges to be supported. 0: Disable; <b>1: Enable</b>
+  $EN_DIS
+**/
+  UINT8                       Eist;
+
+/** Offset 0x00D6 - Enable or Disable Energy Efficient P-state
+  Enable/Disable Energy Efficient P-state feature. When set to 0, will disable access
+  to ENERGY_PERFORMANCE_BIAS MSR and CPUID Function will read 0 indicating no support
+  for Energy Efficient policy setting. When set to 1 will enable access to ENERGY_PERFORMANCE_BIAS
+  MSR and CPUID Function will read 1 indicating Energy Efficient policy setting is
+  supported. 0: Disable; <b>1: Enable</b>
+  $EN_DIS
+**/
+  UINT8                       EnergyEfficientPState;
+
+/** Offset 0x00D7 - Enable or Disable Energy Efficient Turbo
+  Enable/Disable Energy Efficient Turbo Feature. This feature will opportunistically
+  lower the turbo frequency to increase efficiency. Recommended only to disable in
+  overclocking situations where turbo frequency must remain constant. Otherwise,
+  leave enabled. <b>0: Disable</b>; 1: Enable
+  $EN_DIS
+**/
+  UINT8                       EnergyEfficientTurbo;
+
+/** Offset 0x00D8 - Enable or Disable T states
+  Enable or Disable T states; <b>0: Disable</b>; 1: Enable.
+  $EN_DIS
+**/
+  UINT8                       TStates;
+
+/** Offset 0x00D9 - Enable or Disable Thermal Reporting
+  Enable or Disable Thermal Reporting through ACPI tables; 0: Disable; <b>1: Enable</b>.
+  $EN_DIS
+**/
+  UINT8                       EnableAllThermalFunctions;
+
+/** Offset 0x00DA - Enable or Disable CPU power states (C-states)
+  Enable/Disable CPU Power Management. Allows CPU to go to C states when it's not
+  100% utilized. 0: Disable; <b>1: Enable</b>
+  $EN_DIS
+**/
+  UINT8                       Cx;
+
+/** Offset 0x00DB - Configure C-State Configuration Lock
+  Configure MSR to CFG Lock bit. 0: Disable; <b>1: Enable</b>.
+  $EN_DIS
+**/
+  UINT8                       PmgCstCfgCtrlLock;
+
+/** Offset 0x00DC - Enable or Disable Package Cstate Demotion
+  Enable or Disable Package C-State Demotion. 0: Disable; <b>1: Enable</b>
+  $EN_DIS
+**/
+  UINT8                       PkgCStateDemotion;
+
+/** Offset 0x00DD - Enable or Disable Package Cstate UnDemotion
+  Enable or Disable Package C-State Un-Demotion. 0: Disable; <b>1: Enable</b>
+  $EN_DIS
+**/
+  UINT8                       PkgCStateUnDemotion;
+
+/** Offset 0x00DE - Enable or Disable CState-Pre wake
+  Disable - to disable the Cstate Pre-Wake. 0: Disable; <b>1: Enable</b>
+  $EN_DIS
+**/
+  UINT8                       CStatePreWake;
+
+/** Offset 0x00DF - Enable or Disable TimedMwait Support.
+  Enable or Disable TimedMwait Support. <b>0: Disable</b>; 1: Enable
+  $EN_DIS
+**/
+  UINT8                       TimedMwait;
+
+/** Offset 0x00E0 - Set the Max Pkg Cstate
+  Maximum Package C State Limit Setting. Cpu Default: Leaves to Factory default value.
+  Auto: Initializes to deepest available Package C State Limit. Valid values 0 -
+  C0/C1, 1 - C2, 2 - C3, 3 - C6, 4 - C7, 5 - C7S, 6 - C8, 7 - C9, 8 - C10, 254 -
+  CPU Default, <b>255 - Auto</b>
+**/
+  UINT8                       PkgCStateLimit;
+
+/** Offset 0x00E1 - Reserved
+**/
+  UINT8                       Reserved5[2];
+
+/** Offset 0x00E3 - Interrupt Redirection Mode Select
+  Interrupt Redirection Mode Select for Logical Interrupts. 0: Fixed priority; 1:
+  Round robin; 2: Hash vector; 7: No change.
+**/
+  UINT8                       PpmIrmSetting;
+
+/** Offset 0x00E4 - Turbo Mode
+  Enable/Disable processor Turbo Mode. 0:disable, <b>1: Enable</b>
+  $EN_DIS
+**/
+  UINT8                       TurboMode;
+
+/** Offset 0x00E5 - Reserved
+**/
+  UINT8                       Reserved6;
+
+/** Offset 0x00E6 - P-state ratios for custom P-state table
+  P-state ratios for custom P-state table. NumberOfEntries has valid range between
+  0 to 40. For no. of P-States supported(NumberOfEntries) , StateRatio[NumberOfEntries]
+  are configurable. Valid Range of each entry is 0 to 0x7F
+**/
+  UINT8                       StateRatio[40];
+
+/** Offset 0x010E - Custom Ratio State Entries
+  The number of custom ratio state entries, ranges from 0 to 40 for a valid custom
+  ratio table. Sets the number of custom P-states. At least 2 states must be present
+**/
+  UINT8                       NumberOfEntries;
+
+/** Offset 0x010F - Max P-State Ratio
+  Maximum P-state ratio to use in the custom P-state table. Valid Range 0 to 0x7F
+**/
+  UINT8                       MaxRatio;
+
+/** Offset 0x0110 - Reserved
+**/
+  UINT8                       Reserved7;
+
+/** Offset 0x0111 - Turbo settings Lock
+  Enable/Disable locking of Package Power Limit settings. When enabled, PACKAGE_POWER_LIMIT
+  MSR will be locked and a reset will be required to unlock the register. <b>0: Disable;
+  </b> 1: Enable
+  $EN_DIS
+**/
+  UINT8                       TurboPowerLimitLock;
+
+/** Offset 0x0112 - Reserved
+**/
+  UINT8                       Reserved8[33];
+
+/** Offset 0x0133 - Race To Halt
+  Enable/Disable Race To Halt feature. RTH will dynamically increase CPU frequency
+  in order to enter pkg C-State faster to reduce overall power. 0: Disable; <b>1:
+  Enable</b>
+  $EN_DIS
+**/
+  UINT8                       RaceToHalt;
+
+/** Offset 0x0134 - Enable or Disable C1 Cstate Demotion
+  Enable or Disable C1 Cstate Auto Demotion. Disable; <b>1: Enable</b>
+  $EN_DIS
+**/
+  UINT8                       C1StateAutoDemotion;
+
+/** Offset 0x0135 - Enable or Disable C1 Cstate UnDemotion
+  Enable or Disable C1 Cstate Un-Demotion. Disable; <b>1: Enable</b>
+  $EN_DIS
+**/
+  UINT8                       C1StateUnDemotion;
+
+/** Offset 0x0136 - Minimum Ring ratio limit override
+  Minimum Ring ratio limit override. <b>0: Hardware defaults.</b> Range: 0 - Max turbo
+  ratio limit
+**/
+  UINT8                       MinRingRatioLimit;
+
+/** Offset 0x0137 - Maximum Ring ratio limit override
+  Maximum Ring ratio limit override. <b>0: Hardware defaults.</b> Range: 0 - Max turbo
+  ratio limit
+**/
+  UINT8                       MaxRingRatioLimit;
+
+/** Offset 0x0138 - Reserved
+**/
+  UINT8                       Reserved9;
+
+/** Offset 0x0139 - Enable or Disable HWP
+  Enable/Disable Intel(R) Speed Shift Technology support. Enabling will expose the
+  CPPC v2 interface to allow for hardware controlled P-states. 0: Disable; <b>1:
+  Enable;</b>
+  $EN_DIS
+**/
+  UINT8                       Hwp;
+
+/** Offset 0x013A - Set HW P-State Interrupts Enabled for for MISC_PWR_MGMT
+  Set HW P-State Interrupts Enabled for for MISC_PWR_MGMT; <b>0: Disable</b>; 1: Enable.
+  $EN_DIS
+**/
+  UINT8                       HwpInterruptControl;
+
+/** Offset 0x013B - Enable or Disable HwP Autonomous Per Core P State OS control
+  Disable Autonomous PCPS Autonomous will request the same value for all cores all
+  the time. 0: Disable; <b>1: Enable</b>
+  $EN_DIS
+**/
+  UINT8                       EnableHwpAutoPerCorePstate;
+
+/** Offset 0x013C - Enable or Disable HwP Autonomous EPP Grouping
+  Enable EPP grouping Autonomous will request the same values for all cores with same
+  EPP. Disable EPP grouping autonomous will not necessarily request same values for
+  all cores with same EPP. 0: Disable; <b>1: Enable</b>
+  $EN_DIS
+**/
+  UINT8                       EnableHwpAutoEppGrouping;
+
+/** Offset 0x013D - Reserved
+**/
+  UINT8                       Reserved10[5];
+
+/** Offset 0x0142 - Enable or Disable MLC Streamer Prefetcher
+  Enable or Disable MLC Streamer Prefetcher; 0: Disable; <b>1: Enable</b>.
+  $EN_DIS
+**/
+  UINT8                       MlcStreamerPrefetcher;
+
+/** Offset 0x0143 - Enable or Disable MLC Spatial Prefetcher
+  Enable or Disable MLC Spatial Prefetcher; 0: Disable; <b>1: Enable</b>
+  $EN_DIS
+**/
+  UINT8                       MlcSpatialPrefetcher;
+
+/** Offset 0x0144 - Enable or Disable Monitor /MWAIT instructions
+  Enable/Disable MonitorMWait, if Disable MonitorMwait, the AP threads Idle Manner
+  should not set in MWAIT Loop. 0: Disable; <b>1: Enable</b>.
+  $EN_DIS
+**/
+  UINT8                       MonitorMwaitEnable;
+
+/** Offset 0x0145 - Enable or Disable initialization of machine check registers
+  Enable or Disable initialization of machine check registers; 0: Disable; <b>1: Enable</b>.
+  $EN_DIS
+**/
+  UINT8                       MachineCheckEnable;
+
+/** Offset 0x0146 - Control on Processor Trace output scheme
+  Control on Processor Trace output scheme; <b>0: Single Range Output</b>; 1: ToPA Output.
+  0: Single Range Output, 1: ToPA Output
+**/
+  UINT8                       ProcessorTraceOutputScheme;
+
+/** Offset 0x0147 - Enable or Disable Processor Trace feature
+  Enable or Disable Processor Trace feature; <b>0: Disable</b>; 1: Enable.
+  $EN_DIS
+**/
+  UINT8                       ProcessorTraceEnable;
+
+/** Offset 0x0148 - Reserved
+**/
+  UINT8                       Reserved11[3];
+
+/** Offset 0x014B - UFS enable/disable
+  Enable/Disable UFS controller, One byte for each Controller - (1,0) to enable controller
+  0 and (0,1) to enable controller 1
+  $EN_DIS
+**/
+  UINT8                       UfsEnable[2];
+
+/** Offset 0x014D - Reserved
+**/
+  UINT8                       Reserved12[4];
+
+/** Offset 0x0151 - Enable/Disable PCIe tunneling for USB4
+  Enable/Disable PCIe tunneling for USB4, default is enable
+  $EN_DIS
+**/
+  UINT8                       ITbtPcieTunnelingForUsb4;
+
+/** Offset 0x0152 - Reserved
+**/
+  UINT8                       Reserved13[2];
+
+/** Offset 0x0154 - ITBTForcePowerOn Timeout value
+  ITBTForcePowerOn value. Specified increment values in miliseconds. Range is 0-1000.
+  100 = 100 ms.
+**/
+  UINT16                      ITbtForcePowerOnTimeoutInMs;
+
+/** Offset 0x0156 - ITbtConnectTopology Timeout value
+  ITbtConnectTopologyTimeout value. Specified increment values in miliseconds. Range
+  is 0-10000. 100 = 100 ms.
+**/
+  UINT16                      ITbtConnectTopologyTimeoutInMs;
+
+/** Offset 0x0158 - ITBT DMA LTR
+  TCSS DMA1, DMA2 LTR value
+**/
+  UINT16                      ITbtDmaLtr[2];
+
+/** Offset 0x015C - ITbt Usb4CmMode value
+  ITbt Usb4CmMode value. 0:Firmware CM, 1:Software CM
+**/
+  UINT8                       Usb4CmMode;
+
+/** Offset 0x015D - Reserved
+**/
+  UINT8                       Reserved14[19];
+
+/** Offset 0x0170 - IEH Mode
+  Integrated Error Handler Mode, 0: Bypass, 1: Enable
+  0: Bypass, 1:Enable
+**/
+  UINT8                       IehMode;
+
+/** Offset 0x0171 - RTC BIOS Interface Lock
+  Enable RTC BIOS interface lock. When set, prevents RTC TS (BUC.TS) from being changed.
+  $EN_DIS
+**/
+  UINT8                       RtcBiosInterfaceLock;
+
+/** Offset 0x0172 - RTC Cmos Memory Lock
+  Enable RTC lower and upper 128 byte Lock bits to lock Bytes 38h-3Fh in the upper
+  and and lower 128-byte bank of RTC RAM.
+  $EN_DIS
+**/
+  UINT8                       RtcMemoryLock;
+
+/** Offset 0x0173 - AMT Switch
+  Enable/Disable. 0: Disable, 1: enable, Enable or disable AMT functionality.
+  $EN_DIS
+**/
+  UINT8                       AmtEnabled;
+
+/** Offset 0x0174 - SOL Switch
+  Enable/Disable. 0: Disable, 1: enable, Serial Over Lan enable/disable state by Mebx.
+  Setting is invalid if AmtEnabled is 0.
+  $EN_DIS
+**/
+  UINT8                       AmtSolEnabled;
+
+/** Offset 0x0175 - WatchDog Timer Switch
+  Enable/Disable. 0: Disable, 1: enable, Enable or disable WatchDog timer. Setting
+  is invalid if AmtEnabled is 0.
+  $EN_DIS
+**/
+  UINT8                       WatchDogEnabled;
+
+/** Offset 0x0176 - OS Timer
+  16 bits Value, Set OS watchdog timer. Setting is invalid if AmtEnabled is 0.
+**/
+  UINT16                      WatchDogTimerOs;
+
+/** Offset 0x0178 - BIOS Timer
+  16 bits Value, Set BIOS watchdog timer. Setting is invalid if AmtEnabled is 0.
+**/
+  UINT16                      WatchDogTimerBios;
+
+/** Offset 0x017A - Iax Switch
+  Enable/Disable. 0: Disable, 1: enable, Enable or disable Iax functionality.
+  $EN_DIS
+**/
+  UINT8                       IaxEnable;
+
+/** Offset 0x017B - Reserved
+**/
+  UINT8                       Reserved15;
+
+/** Offset 0x017C - ISH GP GPIO Pin Muxing
+  Determines ISH GP GPIO Pin muxing. See GPIO_*_MUXING_ISH_GP_x_GPIO_*. 'x' are GP_NUMBER
+**/
+  UINT32                      IshGpGpioPinMuxing[12];
+
+/** Offset 0x01AC - ISH UART Rx Pin Muxing
+  Determines ISH UART Rx Pin muxing. See GPIO_*_MUXING_ISH_UARTx_TXD_*
+**/
+  UINT32                      IshUartRxPinMuxing[3];
+
+/** Offset 0x01B8 - ISH UART Tx Pin Muxing
+  Determines ISH UART Tx Pin muxing. See GPIO_*_MUXING_ISH_UARTx_RXD_*
+**/
+  UINT32                      IshUartTxPinMuxing[3];
+
+/** Offset 0x01C4 - ISH UART Rts Pin Muxing
+  Select ISH UART Rts Pin muxing. Refer to GPIO_*_MUXING_ISH_UARTx_RTS_* for possible values.
+**/
+  UINT32                      IshUartRtsPinMuxing[3];
+
+/** Offset 0x01D0 - ISH UART Rts Pin Muxing
+  Select ISH UART Cts Pin muxing. Refer to GPIO_*_MUXING_ISH_UARTx_CTS_* for possible values.
+**/
+  UINT32                      IshUartCtsPinMuxing[3];
+
+/** Offset 0x01DC - ISH I2C SDA Pin Muxing
+  Select ISH I2C SDA Pin muxing. Refer to GPIO_*_MUXING_ISH_I2Cx_SDA_* for possible values.
+**/
+  UINT32                      IshI2cSdaPinMuxing[3];
+
+/** Offset 0x01E8 - ISH I2C SCL Pin Muxing
+  Select ISH I2C SCL Pin muxing. Refer to GPIO_*_MUXING_ISH_I2Cx_SCL_* for possible values.
+**/
+  UINT32                      IshI2cSclPinMuxing[3];
+
+/** Offset 0x01F4 - ISH SPI MOSI Pin Muxing
+  Select ISH SPI MOSI Pin muxing. Refer to GPIO_*_MUXING_ISH_SPIx_MOSI_* for possible values.
+**/
+  UINT32                      IshSpiMosiPinMuxing[2];
+
+/** Offset 0x01FC - ISH SPI MISO Pin Muxing
+  Select ISH SPI MISO Pin muxing. Refer to GPIO_*_MUXING_ISH_SPIx_MISO_* for possible values.
+**/
+  UINT32                      IshSpiMisoPinMuxing[2];
+
+/** Offset 0x0204 - ISH SPI CLK Pin Muxing
+  Select ISH SPI CLK Pin muxing. Refer to GPIO_*_MUXING_ISH_SPIx_CLK_* for possible values.
+**/
+  UINT32                      IshSpiClkPinMuxing[2];
+
+/** Offset 0x020C - ISH SPI CS#N Pin Muxing
+  Select ISH SPI CS#N Pin muxing. Refer to GPIO_*_MUXING_ISH_SPIx_CS<N>_* for possible
+  values. N-SPI number, 0-1.
+**/
+  UINT32                      IshSpiCsPinMuxing[4];
+
+/** Offset 0x021C - ISH GP GPIO Pad termination
+  0x0: Hardware default, 0x1: None, 0x13: 1kOhm weak pull-up, 0x15: 5kOhm weak pull-up,
+  0x19: 20kOhm weak pull-up - Enable/disable SerialIo GP#N GPIO pads termination
+  respectively. #N are GP_NUMBER, not strictly relate to indexes of this table. Index
+  0-23 -> ISH_GP_0-23, Index 24-25 -> ISH_GP_30-31
+**/
+  UINT8                       IshGpGpioPadTermination[12];
+
+/** Offset 0x0228 - ISH UART Rx Pad termination
+  0x0: Hardware default, 0x1: None, 0x13: 1kOhm weak pull-up, 0x15: 5kOhm weak pull-up,
+  0x19: 20kOhm weak pull-up - Enable/disable SerialIo UART#N Rx pads termination
+  respectively. #N-byte for each controller, byte0 for UART0 Rx, byte1 for UART1
+  Rx, and so on.
+**/
+  UINT8                       IshUartRxPadTermination[3];
+
+/** Offset 0x022B - ISH UART Tx Pad termination
+  0x0: Hardware default, 0x1: None, 0x13: 1kOhm weak pull-up, 0x15: 5kOhm weak pull-up,
+  0x19: 20kOhm weak pull-up - Enable/disable SerialIo UART#N Tx pads termination
+  respectively. #N-byte for each controller, byte0 for UART0 Tx, byte1 for UART1
+  Tx, and so on.
+**/
+  UINT8                       IshUartTxPadTermination[3];
+
+/** Offset 0x022E - ISH UART Rts Pad termination
+  0x0: Hardware default, 0x1: None, 0x13: 1kOhm weak pull-up, 0x15: 5kOhm weak pull-up,
+  0x19: 20kOhm weak pull-up - Enable/disable SerialIo UART#N Rts pads termination
+  respectively. #N-byte for each controller, byte0 for UART0 Rts, byte1 for UART1
+  Rts, and so on.
+**/
+  UINT8                       IshUartRtsPadTermination[3];
+
+/** Offset 0x0231 - ISH UART Rts Pad termination
+  0x0: Hardware default, 0x1: None, 0x13: 1kOhm weak pull-up, 0x15: 5kOhm weak pull-up,
+  0x19: 20kOhm weak pull-up - Enable/disable SerialIo UART#N Cts pads termination
+  respectively. #N-byte for each controller, byte0 for UART0 Cts, byte1 for UART1
+  Cts, and so on.
+**/
+  UINT8                       IshUartCtsPadTermination[3];
+
+/** Offset 0x0234 - ISH I2C SDA Pad termination
+  0x0: Hardware default, 0x1: None, 0x13: 1kOhm weak pull-up, 0x15: 5kOhm weak pull-up,
+  0x19: 20kOhm weak pull-up - Enable/disable SerialIo I2C#N Sda pads termination
+  respectively. #N-byte for each controller, byte0 for I2C0 Sda, byte1 for I2C1 Sda,
+  and so on.
+**/
+  UINT8                       IshI2cSdaPadTermination[3];
+
+/** Offset 0x0237 - ISH I2C SCL Pad termination
+  0x0: Hardware default, 0x1: None, 0x13: 1kOhm weak pull-up, 0x15: 5kOhm weak pull-up,
+  0x19: 20kOhm weak pull-up - Enable/disable SerialIo I2C#N Scl pads termination
+  respectively. #N-byte for each controller, byte0 for I2C0 Scl, byte1 for I2C1 Scl,
+  and so on.
+**/
+  UINT8                       IshI2cSclPadTermination[3];
+
+/** Offset 0x023A - ISH SPI MOSI Pad termination
+  0x0: Hardware default, 0x1: None, 0x13: 1kOhm weak pull-up, 0x15: 5kOhm weak pull-up,
+  0x19: 20kOhm weak pull-up - Enable/disable SerialIo SPI#N Mosi pads termination
+  respectively. #N-byte for each controller, byte0 for SPI0 Mosi, byte1 for SPI1
+  Mosi, and so on.
+**/
+  UINT8                       IshSpiMosiPadTermination[2];
+
+/** Offset 0x023C - ISH SPI MISO Pad termination
+  0x0: Hardware default, 0x1: None, 0x13: 1kOhm weak pull-up, 0x15: 5kOhm weak pull-up,
+  0x19: 20kOhm weak pull-up - Enable/disable SerialIo SPI#N Miso pads termination
+  respectively. #N-byte for each controller, byte0 for SPI0 Miso, byte1 for SPI1
+  Miso, and so on.
+**/
+  UINT8                       IshSpiMisoPadTermination[2];
+
+/** Offset 0x023E - ISH SPI CLK Pad termination
+  0x0: Hardware default, 0x1: None, 0x13: 1kOhm weak pull-up, 0x15: 5kOhm weak pull-up,
+  0x19: 20kOhm weak pull-up - Enable/disable SerialIo SPI#N Clk pads termination
+  respectively. #N-byte for each controller, byte0 for SPI0 Clk, byte1 for SPI1 Clk,
+  and so on.
+**/
+  UINT8                       IshSpiClkPadTermination[2];
+
+/** Offset 0x0240 - ISH SPI CS#N Pad termination
+  0x0: Hardware default, 0x1: None, 0x13: 1kOhm weak pull-up, 0x15: 5kOhm weak pull-up,
+  0x19: 20kOhm weak pull-up - Enable/disable SerialIo SPI#N Cs#M pads termination
+  respectively. N*M-byte for each controller, byte0 for SPI0 Cs0, byte1 for SPI1
+  Cs1, SPI1 Cs0, byte2, SPI1 Cs1, byte3
+**/
+  UINT8                       IshSpiCsPadTermination[4];
+
+/** Offset 0x0244 - Enable PCH ISH SPI Cs#N pins assigned
+  Set if ISH SPI Cs#N pins are to be enabled by BIOS. 0: Disable; 1: Enable. N-Cs
+  number: 0-1
+**/
+  UINT8                       PchIshSpiCsEnable[4];
+
+/** Offset 0x0248 - Enable PCH ISH SPI Cs0 pins assigned
+  Set if ISH SPI Cs0 pins are to be enabled by BIOS. 0: Disable; 1: Enable.
+**/
+  UINT8                       PchIshSpiCs0Enable[1];
+
+/** Offset 0x0249 - Enable PCH ISH SPI pins assigned
+  Set if ISH SPI native pins are to be enabled by BIOS. 0: Disable; 1: Enable.
+**/
+  UINT8                       PchIshSpiEnable[1];
+
+/** Offset 0x024A - Enable PCH ISH UART pins assigned
+  Set if ISH UART native pins are to be enabled by BIOS. 0: Disable; 1: Enable.
+**/
+  UINT8                       PchIshUartEnable[2];
+
+/** Offset 0x024C - Enable PCH ISH I2C pins assigned
+  Set if ISH I2C native pins are to be enabled by BIOS. 0: Disable; 1: Enable.
+**/
+  UINT8                       PchIshI2cEnable[3];
+
+/** Offset 0x024F - Enable PCH ISH GP pins assigned
+  Set if ISH GP native pins are to be enabled by BIOS. 0: Disable; 1: Enable.
+**/
+  UINT8                       PchIshGpEnable[12];
+
+/** Offset 0x025B - PCH ISH PDT Unlock Msg
+  0: False; 1: True.
+  $EN_DIS
+**/
+  UINT8                       PchIshPdtUnlock;
+
+/** Offset 0x025C - Reserved
+**/
+  UINT8                       Reserved16;
+
+/** Offset 0x025D - End of Post message
+  Test, Send End of Post message. Disable(0x0): Disable EOP message, Send in PEI(0x1):
+  EOP send in PEI, Send in DXE(0x2)(Default): EOP send in DXE
+  0:Disable, 1:Send in PEI, 2:Send in DXE, 3:Reserved
+**/
+  UINT8                       EndOfPostMessage;
+
+/** Offset 0x025E - D0I3 Setting for HECI Disable
+  Test, 0: disable, 1: enable, Setting this option disables setting D0I3 bit for all
+  HECI devices
+  $EN_DIS
+**/
+  UINT8                       DisableD0I3SettingForHeci;
+
+/** Offset 0x025F - Mctp Broadcast Cycle
+  Test, Determine if MCTP Broadcast is enabled <b>0: Disable</b>; 1: Enable.
+  $EN_DIS
+**/
+  UINT8                       MctpBroadcastCycle;
+
+/** Offset 0x0260 - ME Unconfig on RTC clear
+  0: Disable ME Unconfig On Rtc Clear. <b>1: Enable ME Unconfig On Rtc Clear</b>.
+  2: Cmos is clear, status unkonwn. 3: Reserved
+  0: Disable ME Unconfig On Rtc Clear, 1: Enable ME Unconfig On Rtc Clear, 2: Cmos
+  is clear, 3: Reserved
+**/
+  UINT8                       MeUnconfigOnRtcClear;
+
+/** Offset 0x0261 - Reserved
+**/
+  UINT8                       Reserved17[22];
+
+/** Offset 0x0277 - Enable PCH ISH I3C pins assigned
+  Set if ISH I3C native pins are to be enabled by BIOS. 0: Disable; 1: Enable.
+**/
+  UINT8                       PchIshI3cEnable[2];
+
+/** Offset 0x0279 - Reserved
+**/
+  UINT8                       Reserved18[3];
+
+/** Offset 0x027C - Power button debounce configuration
+  Debounce time for PWRBTN in microseconds. For values not supported by HW, they will
+  be rounded down to closest supported on. 0: disable, 250-1024000us: supported range
+**/
+  UINT32                      PmcPowerButtonDebounce;
+
+/** Offset 0x0280 - PCH USB2 PHY Power Gating enable
+  1: Will enable USB2 PHY SUS Well Power Gating, 0: Will not enable PG of USB2 PHY
+  Sus Well PG
+  $EN_DIS
+**/
+  UINT8                       PmcUsb2PhySusPgEnable;
+
+/** Offset 0x0281 - VRAlert# Pin
+  When VRAlert# feature pin is enabled and its state is '0', the PMC requests throttling
+  to a T3 Tstate to the PCH throttling unit.. 0: disable, 1: enable
+  $EN_DIS
+**/
+  UINT8                       PchPmVrAlert;
+
+/** Offset 0x0282 - ModPHY SUS Power Domain Dynamic Gating
+  Enable/Disable ModPHY SUS Power Domain Dynamic Gating. Setting not supported on
+  PCH-H. 0: disable, 1: enable
+  $EN_DIS
+**/
+  UINT8                       PmcModPhySusPgEnable;
+
+/** Offset 0x0283 - V1p05-PHY supply external FET control
+  Enable/Disable control using EXT_PWR_GATE# pin of external FET to power gate v1p05-PHY
+  supply. 0: disable, 1: enable
+  $EN_DIS
+**/
+  UINT8                       PmcV1p05PhyExtFetControlEn;
+
+/** Offset 0x0284 - V1p05-IS supply external FET control
+  Enable/Disable control using EXT_PWR_GATE2# pin of external FET to power gate v1p05-IS
+  supply. 0: disable, 1: enable
+  $EN_DIS
+**/
+  UINT8                       PmcV1p05IsExtFetControlEn;
+
+/** Offset 0x0285 - PCH Pm PME_B0_S5_DIS
+  When cleared (default), wake events from PME_B0_STS are allowed in S5 if PME_B0_EN = 1.
+  $EN_DIS
+**/
+  UINT8                       PchPmPmeB0S5Dis;
+
+/** Offset 0x0286 - PCH Pm Wol Enable Override
+  Corresponds to the WOL Enable Override bit in the General PM Configuration B (GEN_PMCON_B) register.
+  $EN_DIS
+**/
+  UINT8                       PchPmWolEnableOverride;
+
+/** Offset 0x0287 - PCH Pm WoW lan Enable
+  Determine if WLAN wake from Sx, corresponds to the HOST_WLAN_PP_EN bit in the PWRM_CFG3 register.
+  $EN_DIS
+**/
+  UINT8                       PchPmWoWlanEnable;
+
+/** Offset 0x0288 - PCH Pm Slp S3 Min Assert
+  SLP_S3 Minimum Assertion Width Policy. Default is PchSlpS350ms.
+**/
+  UINT8                       PchPmSlpS3MinAssert;
+
+/** Offset 0x0289 - PCH Pm Slp S4 Min Assert
+  SLP_S4 Minimum Assertion Width Policy. Default is PchSlpS44s.
+**/
+  UINT8                       PchPmSlpS4MinAssert;
+
+/** Offset 0x028A - PCH Pm Slp Sus Min Assert
+  SLP_SUS Minimum Assertion Width Policy. Default is PchSlpSus4s.
+**/
+  UINT8                       PchPmSlpSusMinAssert;
+
+/** Offset 0x028B - PCH Pm Slp A Min Assert
+  SLP_A Minimum Assertion Width Policy. Default is PchSlpA2s.
+**/
+  UINT8                       PchPmSlpAMinAssert;
+
+/** Offset 0x028C - PCH Pm Slp Strch Sus Up
+  Enable SLP_X Stretching After SUS Well Power Up.
+  $EN_DIS
+**/
+  UINT8                       PchPmSlpStrchSusUp;
+
+/** Offset 0x028D - PCH Pm Slp Lan Low Dc
+  Enable/Disable SLP_LAN# Low on DC Power.
+  $EN_DIS
+**/
+  UINT8                       PchPmSlpLanLowDc;
+
+/** Offset 0x028E - PCH Pm Pwr Btn Override Period
+  PCH power button override period. 000b-4s, 001b-6s, 010b-8s, 011b-10s, 100b-12s, 101b-14s.
+**/
+  UINT8                       PchPmPwrBtnOverridePeriod;
+
+/** Offset 0x028F - PCH Pm Disable Native Power Button
+  Power button native mode disable.
+  $EN_DIS
+**/
+  UINT8                       PchPmDisableNativePowerButton;
+
+/** Offset 0x0290 - PCH Pm ME_WAKE_STS
+  Clear the ME_WAKE_STS bit in the Power and Reset Status (PRSTS) register.
+  $EN_DIS
+**/
+  UINT8                       PchPmMeWakeSts;
+
+/** Offset 0x0291 - PCH Pm WOL_OVR_WK_STS
+  Clear the WOL_OVR_WK_STS bit in the Power and Reset Status (PRSTS) register.
+  $EN_DIS
+**/
+  UINT8                       PchPmWolOvrWkSts;
+
+/** Offset 0x0292 - PCH Pm Reset Power Cycle Duration
+  Could be customized in the unit of second. Please refer to EDS for all support settings.
+  0 is default, 1 is 1 second, 2 is 2 seconds, ...
+**/
+  UINT8                       PchPmPwrCycDur;
+
+/** Offset 0x0293 - PCH Pm Pcie Pll Ssc
+  Specifies the Pcie Pll Spread Spectrum Percentage. The default is 0xFF: AUTO - No
+  BIOS override.
+**/
+  UINT8                       PchPmPciePllSsc;
+
+/** Offset 0x0294 - Enable TCO timer.
+  When FALSE, it disables PCH ACPI timer, and stops TCO timer. NOTE: This will have
+  huge power impact when it's enabled. If TCO timer is disabled, uCode ACPI timer
+  emulation must be enabled, and WDAT table must not be exposed to the OS.
+  $EN_DIS
+**/
+  UINT8                       EnableTcoTimer;
+
+/** Offset 0x0295 - Enable PS_ON.
+  PS_ON is a new C10 state from the CPU on desktop SKUs that enables a lower power
+  target that will be required by the California Energy Commission (CEC). When FALSE,
+  PS_ON is to be disabled.
+  $EN_DIS
+**/
+  UINT8                       PsOnEnable;
+
+/** Offset 0x0296 - Pmc Cpu C10 Gate Pin Enable
+  Enable/Disable platform support for CPU_C10_GATE# pin to control gating of CPU VccIO
+  and VccSTG rails instead of SLP_S0# pin.
+  $EN_DIS
+**/
+  UINT8                       PmcCpuC10GatePinEnable;
+
+/** Offset 0x0297 - OS IDLE Mode Enable
+  Enable/Disable OS Idle Mode
+  $EN_DIS
+**/
+  UINT8                       PmcOsIdleEnable;
+
+/** Offset 0x0298 - S0ix Auto-Demotion
+  Enable/Disable the Low Power Mode Auto-Demotion Host Control feature.
+  $EN_DIS
+**/
+  UINT8                       PchS0ixAutoDemotion;
+
+/** Offset 0x0299 - Latch Events C10 Exit
+  When this bit is set to 1, SLP_S0# entry events in SLP_S0_DEBUG_REGx registers are
+  captured on C10 exit (instead of C10 entry which is default)
+  $EN_DIS
+**/
+  UINT8                       PchPmLatchEventsC10Exit;
+
+/** Offset 0x029A - PCH Energy Reporting
+  Disable/Enable PCH to CPU energy report feature.
+  $EN_DIS
+**/
+  UINT8                       PchPmDisableEnergyReport;
+
+/** Offset 0x029B - Low Power Mode Enable/Disable config mask
+  Configure if respective S0i2/3 sub-states are to be supported. Each bit corresponds
+  to one sub-state (LPMx - BITx): LPM0-s0i2.0, LPM1-s0i2.1, LPM2-s0i2.2, LPM3-s0i3.0,
+  LPM4-s0i3.1, LPM5-s0i3.2, LPM6-s0i3.3, LPM7-s0i3.4.
+**/
+  UINT8                       PmcLpmS0ixSubStateEnableMask;
+
+/** Offset 0x029C - Reserved
+**/
+  UINT8                       Reserved19;
+
+/** Offset 0x029D - PMC C10 dynamic threshold dajustment enable
+  Set if you want to enable PMC C10 dynamic threshold adjustment. Only works on supported SKUs
+  $EN_DIS
+**/
+  UINT8                       PmcC10DynamicThresholdAdjustment;
+
+/** Offset 0x029E - Enable LOCKDOWN BIOS LOCK
+  Enable the BIOS Lock feature and set EISS bit (D31:F5:RegDCh[5]) for the BIOS region
+  protection.
+  $EN_DIS
+**/
+  UINT8                       PchLockDownBiosLock;
+
+/** Offset 0x029F - Enable LOCKDOWN SMI
+  Enable SMI_LOCK bit to prevent writes to the Global SMI Enable bit.
+  $EN_DIS
+**/
+  UINT8                       PchLockDownGlobalSmi;
+
+/** Offset 0x02A0 - Enable LOCKDOWN BIOS Interface
+  Enable BIOS Interface Lock Down bit to prevent writes to the Backup Control Register.
+  $EN_DIS
+**/
+  UINT8                       PchLockDownBiosInterface;
+
+/** Offset 0x02A1 - Unlock all GPIO pads
+  Force all GPIO pads to be unlocked for debug purpose.
+  $EN_DIS
+**/
+  UINT8                       PchUnlockGpioPads;
+
+/** Offset 0x02A2 - PCH Flash Protection Ranges Write Enble
+  Write or erase is blocked by hardware.
+**/
+  UINT8                       PchWriteProtectionEnable[5];
+
+/** Offset 0x02A7 - PCH Flash Protection Ranges Read Enble
+  Read is blocked by hardware.
+**/
+  UINT8                       PchReadProtectionEnable[5];
+
+/** Offset 0x02AC - PCH Protect Range Limit
+  Left shifted address by 12 bits with address bits 11:0 are assumed to be FFFh for
+  limit comparison.
+**/
+  UINT16                      PchProtectedRangeLimit[5];
+
+/** Offset 0x02B6 - PCH Protect Range Base
+  Left shifted address by 12 bits with address bits 11:0 are assumed to be 0.
+**/
+  UINT16                      PchProtectedRangeBase[5];
+
+/** Offset 0x02C0 - PCIe PTM enable/disable
+  Enable/disable Precision Time Measurement for PCIE Root Ports.
+**/
+  UINT8                       PciePtm[28];
+
+/** Offset 0x02DC - PCH PCIe root port connection type
+  0: built-in device, 1:slot
+**/
+  UINT8                       PcieRpSlotImplemented[28];
+
+/** Offset 0x02F8 - PCIE RP Access Control Services Extended Capability
+  Enable/Disable PCIE RP Access Control Services Extended Capability
+**/
+  UINT8                       PcieRpAcsEnabled[28];
+
+/** Offset 0x0314 - PCIE RP Clock Power Management
+  Enable/Disable PCIE RP Clock Power Management, even if disabled, CLKREQ# signal
+  can still be controlled by L1 PM substates mechanism
+**/
+  UINT8                       PcieRpEnableCpm[28];
+
+/** Offset 0x0330 - PCIE RP Detect Timeout Ms
+  The number of milliseconds within 0~65535 in reference code will wait for link to
+  exit Detect state for enabled ports before assuming there is no device and potentially
+  disabling the port.
+**/
+  UINT16                      PcieRpDetectTimeoutMs[24];
+
+/** Offset 0x0360 - Enable PCIE RP HotPlug
+  Indicate whether the root port is hot plug available.
+**/
+  UINT8                       PcieRpHotPlug[28];
+
+/** Offset 0x037C - Enable PCIE RP Pm Sci
+  Indicate whether the root port power manager SCI is enabled.
+**/
+  UINT8                       PcieRpPmSci[28];
+
+/** Offset 0x0398 - Enable PCIE RP Transmitter Half Swing
+  Indicate whether the Transmitter Half Swing is enabled.
+**/
+  UINT8                       PcieRpTransmitterHalfSwing[28];
+
+/** Offset 0x03B4 - Enable PCIE RP Clk Req Detect
+  Probe CLKREQ# signal before enabling CLKREQ# based power management.
+**/
+  UINT8                       PcieRpClkReqDetect[28];
+
+/** Offset 0x03D0 - PCIE RP Advanced Error Report
+  Indicate whether the Advanced Error Reporting is enabled.
+**/
+  UINT8                       PcieRpAdvancedErrorReporting[28];
+
+/** Offset 0x03EC - PCIE RP Unsupported Request Report
+  Indicate whether the Unsupported Request Report is enabled.
+**/
+  UINT8                       PcieRpUnsupportedRequestReport[28];
+
+/** Offset 0x0408 - PCIE RP Fatal Error Report
+  Indicate whether the Fatal Error Report is enabled.
+**/
+  UINT8                       PcieRpFatalErrorReport[28];
+
+/** Offset 0x0424 - PCIE RP No Fatal Error Report
+  Indicate whether the No Fatal Error Report is enabled.
+**/
+  UINT8                       PcieRpNoFatalErrorReport[28];
+
+/** Offset 0x0440 - PCIE RP Correctable Error Report
+  Indicate whether the Correctable Error Report is enabled.
+**/
+  UINT8                       PcieRpCorrectableErrorReport[28];
+
+/** Offset 0x045C - PCIE RP System Error On Fatal Error
+  Indicate whether the System Error on Fatal Error is enabled.
+**/
+  UINT8                       PcieRpSystemErrorOnFatalError[28];
+
+/** Offset 0x0478 - PCIE RP System Error On Non Fatal Error
+  Indicate whether the System Error on Non Fatal Error is enabled.
+**/
+  UINT8                       PcieRpSystemErrorOnNonFatalError[28];
+
+/** Offset 0x0494 - PCIE RP System Error On Correctable Error
+  Indicate whether the System Error on Correctable Error is enabled.
+**/
+  UINT8                       PcieRpSystemErrorOnCorrectableError[28];
+
+/** Offset 0x04B0 - PCIE RP Max Payload
+  Max Payload Size supported, Default 256B, see enum PCH_PCIE_MAX_PAYLOAD.
+**/
+  UINT8                       PcieRpMaxPayload[28];
+
+/** Offset 0x04CC - PCIE RP Pcie Speed
+  Determines each PCIE Port speed capability. 0: Auto; 1: Gen1; 2: Gen2; 3: Gen3 (see:
+  PCIE_SPEED).
+**/
+  UINT8                       PcieRpPcieSpeed[28];
+
+/** Offset 0x04E8 - PCIE RP Physical Slot Number
+  Indicates the slot number for the root port. Default is the value as root port index.
+**/
+  UINT8                       PcieRpPhysicalSlotNumber[28];
+
+/** Offset 0x0504 - PCIE RP Completion Timeout
+  The root port completion timeout(see: PCIE_COMPLETION_TIMEOUT). Default is PchPcieCompletionTO_Default.
+**/
+  UINT8                       PcieRpCompletionTimeout[28];
+
+/** Offset 0x0520 - PCIE RP Aspm
+  The ASPM configuration of the root port (see: PCH_PCIE_ASPM_CONTROL). Default is
+  PchPcieAspmAutoConfig.
+**/
+  UINT8                       PcieRpAspm[28];
+
+/** Offset 0x053C - Reserved
+**/
+  UINT8                       Reserved20[28];
+
+/** Offset 0x0558 - PCIE RP L1 Substates
+  The L1 Substates configuration of the root port (see: PCH_PCIE_L1SUBSTATES_CONTROL).
+  Default is PchPcieL1SubstatesL1_1_2.
+**/
+  UINT8                       PcieRpL1Substates[28];
+
+/** Offset 0x0574 - PCIE RP Ltr Enable
+  Latency Tolerance Reporting Mechanism.
+**/
+  UINT8                       PcieRpLtrEnable[28];
+
+/** Offset 0x0590 - PCIE RP Ltr Config Lock
+  0: Disable; 1: Enable.
+**/
+  UINT8                       PcieRpLtrConfigLock[28];
+
+/** Offset 0x05AC - PCIE RP override default settings for EQ
+  Choose PCIe EQ method
+  $EN_DIS
+**/
+  UINT8                       PcieEqOverrideDefault[12];
+
+/** Offset 0x05B8 - Reserved
+**/
+  UINT8                       Reserved21[1525];
+
+/** Offset 0x0BAD - PCIE RP Enable Peer Memory Write
+  This member describes whether Peer Memory Writes are enabled on the platform.
+  $EN_DIS
+**/
+  UINT8                       PcieEnablePeerMemoryWrite[12];
+
+/** Offset 0x0BB9 - Assertion on Link Down GPIOs
+  GPIO Assertion on Link Down. Disabled(0x0)(Default): Disable assertion on Link Down
+  GPIOs, Enabled(0x1): Enable assertion on Link Down GPIOs
+  0:Disable, 1:Enable
+**/
+  UINT8                       PcieRpLinkDownGpios[12];
+
+/** Offset 0x0BC5 - PCIE Compliance Test Mode
+  Compliance Test Mode shall be enabled when using Compliance Load Board.
+  $EN_DIS
+**/
+  UINT8                       PcieComplianceTestMode;
+
+/** Offset 0x0BC6 - PCIE Rp Function Swap
+  Allows BIOS to use root port function number swapping when root port of function
+  0 is disabled.
+  $EN_DIS
+**/
+  UINT8                       PcieRpFunctionSwap;
+
+/** Offset 0x0BC7 - Reserved
+**/
+  UINT8                       Reserved22[12];
+
+/** Offset 0x0BD3 - PCIe RootPort Power Gating
+  Describes whether the PCI Express Power Gating for each root port is enabled by
+  platform modules. 0: Disable; 1: Enable(Default).
+  $EN_DIS
+**/
+  UINT8                       PciePowerGating[12];
+
+/** Offset 0x0BDF - Reserved
+**/
+  UINT8                       Reserved23[49];
+
+/** Offset 0x0C10 - PCIE RP Ltr Max Snoop Latency
+  Latency Tolerance Reporting, Max Snoop Latency.
+**/
+  UINT16                      PcieRpLtrMaxSnoopLatency[24];
+
+/** Offset 0x0C40 - PCIE RP Ltr Max No Snoop Latency
+  Latency Tolerance Reporting, Max Non-Snoop Latency.
+**/
+  UINT16                      PcieRpLtrMaxNoSnoopLatency[24];
+
+/** Offset 0x0C70 - PCIE RP Snoop Latency Override Mode
+  Latency Tolerance Reporting, Snoop Latency Override Mode.
+**/
+  UINT8                       PcieRpSnoopLatencyOverrideMode[28];
+
+/** Offset 0x0C8C - PCIE RP Snoop Latency Override Multiplier
+  Latency Tolerance Reporting, Snoop Latency Override Multiplier.
+**/
+  UINT8                       PcieRpSnoopLatencyOverrideMultiplier[28];
+
+/** Offset 0x0CA8 - PCIE RP Snoop Latency Override Value
+  Latency Tolerance Reporting, Snoop Latency Override Value.
+**/
+  UINT16                      PcieRpSnoopLatencyOverrideValue[24];
+
+/** Offset 0x0CD8 - PCIE RP Non Snoop Latency Override Mode
+  Latency Tolerance Reporting, Non-Snoop Latency Override Mode.
+**/
+  UINT8                       PcieRpNonSnoopLatencyOverrideMode[28];
+
+/** Offset 0x0CF4 - PCIE RP Non Snoop Latency Override Multiplier
+  Latency Tolerance Reporting, Non-Snoop Latency Override Multiplier.
+**/
+  UINT8                       PcieRpNonSnoopLatencyOverrideMultiplier[28];
+
+/** Offset 0x0D10 - PCIE RP Non Snoop Latency Override Value
+  Latency Tolerance Reporting, Non-Snoop Latency Override Value.
+**/
+  UINT16                      PcieRpNonSnoopLatencyOverrideValue[24];
+
+/** Offset 0x0D40 - PCIE RP Slot Power Limit Scale
+  Specifies scale used for slot power limit value. Leave as 0 to set to default.
+**/
+  UINT8                       PcieRpSlotPowerLimitScale[28];
+
+/** Offset 0x0D5C - PCIE RP Slot Power Limit Value
+  Specifies upper limit on power supplie by slot. Leave as 0 to set to default.
+**/
+  UINT16                      PcieRpSlotPowerLimitValue[24];
+
+/** Offset 0x0D8C - PCIE RP Enable Port8xh Decode
+  This member describes whether PCIE root port Port 8xh Decode is enabled. 0: Disable;
+  1: Enable.
+  $EN_DIS
+**/
+  UINT8                       PcieEnablePort8xhDecode;
+
+/** Offset 0x0D8D - PCIE Port8xh Decode Port Index
+  The Index of PCIe Port that is selected for Port8xh Decode (1 Based).
+**/
+  UINT8                       PchPciePort8xhDecodePortIndex;
+
+/** Offset 0x0D8E - Reserved
+**/
+  UINT8                       Reserved24[114];
+
+/** Offset 0x0E00 - SPIn Device Mode
+  Selects SPI operation mode. N represents controller index: SPI0, SPI1, ... Available
+  modes: 0:LpssSpiDisabled, 1:LpssSpiPci, 2:LpssSpiHidden
+**/
+  UINT8                       SerialIoLpssSpiMode[7];
+
+/** Offset 0x0E07 - Reserved
+**/
+  UINT8                       Reserved25[85];
+
+/** Offset 0x0E5C - SPIn Default Chip Select Mode HW/SW
+  Sets Default CS Mode Hardware or Software. N represents controller index: SPI0,
+  SPI1, ... Available options: 0:HW, 1:SW
+**/
+  UINT8                       SerialIoLpssSpiCsMode[7];
+
+/** Offset 0x0E63 - SPIn Default Chip Select State Low/High
+  Sets Default CS State Low or High. N represents controller index: SPI0, SPI1, ...
+  Available options: 0:Low, 1:High
+**/
+  UINT8                       SerialIoLpssSpiCsState[7];
+
+/** Offset 0x0E6A - UARTn Device Mode
+  Selects Uart operation mode. N represents controller index: Uart0, Uart1, ... Available
+  modes: 0:SerialIoUartDisabled, 1:SerialIoUartPci, 2:SerialIoUartHidden, 3:SerialIoUartCom,
+  4:SerialIoUartSkipInit
+**/
+  UINT8                       SerialIoUartMode[7];
+
+/** Offset 0x0E71 - Reserved
+**/
+  UINT8                       Reserved26[3];
+
+/** Offset 0x0E74 - Default BaudRate for each Serial IO UART
+  Set default BaudRate Supported from 0 - default to 6000000
+**/
+  UINT32                      SerialIoUartBaudRate[7];
+
+/** Offset 0x0E90 - Default ParityType for each Serial IO UART
+  Set default Parity. 0: DefaultParity, 1: NoParity, 2: EvenParity, 3: OddParity
+**/
+  UINT8                       SerialIoUartParity[7];
+
+/** Offset 0x0E97 - Default DataBits for each Serial IO UART
+  Set default word length. 0: Default, 5,6,7,8
+**/
+  UINT8                       SerialIoUartDataBits[7];
+
+/** Offset 0x0E9E - Default StopBits for each Serial IO UART
+  Set default stop bits. 0: DefaultStopBits, 1: OneStopBit, 2: OneFiveStopBits, 3:
+  TwoStopBits
+**/
+  UINT8                       SerialIoUartStopBits[7];
+
+/** Offset 0x0EA5 - Power Gating mode for each Serial IO UART that works in COM mode
+  Set Power Gating. 0: Disabled, 1: Enabled, 2: Auto
+**/
+  UINT8                       SerialIoUartPowerGating[7];
+
+/** Offset 0x0EAC - Enable Dma for each Serial IO UART that supports it
+  Set DMA/PIO mode. 0: Disabled, 1: Enabled
+**/
+  UINT8                       SerialIoUartDmaEnable[7];
+
+/** Offset 0x0EB3 - Enables UART hardware flow control, CTS and RTS lines
+  Enables UART hardware flow control, CTS and RTS lines.
+**/
+  UINT8                       SerialIoUartAutoFlow[7];
+
+/** Offset 0x0EBA - Reserved
+**/
+  UINT8                       Reserved27[2];
+
+/** Offset 0x0EBC - SerialIoUartRtsPinMuxPolicy
+  Select SerialIo Uart Rts pin muxing. Refer to GPIO_*_MUXING_SERIALIO_UARTx_RTS*
+  for possible values.
+**/
+  UINT32                      SerialIoUartRtsPinMuxPolicy[7];
+
+/** Offset 0x0ED8 - SerialIoUartRxPinMuxPolicy
+  Select SerialIo Uart Rx pin muxing. Refer to GPIO_*_MUXING_SERIALIO_UARTx_RX* for
+  possible values.
+**/
+  UINT32                      SerialIoUartRxPinMuxPolicy[7];
+
+/** Offset 0x0EF4 - SerialIoUartTxPinMuxPolicy
+  Select SerialIo Uart Tx pin muxing. Refer to GPIO_*_MUXING_SERIALIO_UARTx_TX* for
+  possible values.
+**/
+  UINT32                      SerialIoUartTxPinMuxPolicy[7];
+
+/** Offset 0x0F10 - Serial IO UART DBG2 table
+  Enable or disable Serial Io UART DBG2 table, default is Disable; <b>0: Disable;</b>
+  1: Enable.
+**/
+  UINT8                       SerialIoUartDbg2[7];
+
+/** Offset 0x0F17 - Reserved
+**/
+  UINT8                       Reserved28[7];
+
+/** Offset 0x0F1E - I2Cn Device Mode
+  Selects I2c operation mode. N represents controller index: I2c0, I2c1, ... Available
+  modes: 0:SerialIoI2cDisabled, 1:SerialIoI2cPci, 2:SerialIoI2cHidden
+**/
+  UINT8                       SerialIoI2cMode[8];
+
+/** Offset 0x0F26 - Reserved
+**/
+  UINT8                       Reserved29[2];
+
+/** Offset 0x0F28 - Serial IO I2C SDA Pin Muxing
+  Select SerialIo I2c Sda pin muxing. Refer to GPIO_*_MUXING_SERIALIO_I2Cx_SDA* for
+  possible values.
+**/
+  UINT32                      PchSerialIoI2cSdaPinMux[8];
+
+/** Offset 0x0F48 - Serial IO I2C SCL Pin Muxing
+  Select SerialIo I2c Scl pin muxing. Refer to GPIO_*_MUXING_SERIALIO_I2Cx_SCL* for
+  possible values.
+**/
+  UINT32                      PchSerialIoI2cSclPinMux[8];
+
+/** Offset 0x0F68 - PCH SerialIo I2C Pads Termination
+  0x0: Hardware default, 0x1: None, 0x13: 1kOhm weak pull-up, 0x15: 5kOhm weak pull-up,
+  0x19: 20kOhm weak pull-up - Enable/disable SerialIo I2C0,I2C1,... pads termination
+  respectively. One byte for each controller, byte0 for I2C0, byte1 for I2C1, and so on.
+**/
+  UINT8                       PchSerialIoI2cPadsTermination[8];
+
+/** Offset 0x0F70 - I3C Device Mode
+  Selects I3c operation mode. Available modes: 0:SerialIoI3cDisabled, 1:SerialIoI3cPci,
+  2:SerialIoI3cPhantom (only applicable to I3C1, controlls GPIO enabling)
+**/
+  UINT8                       SerialIoI3cMode[3];
+
+/** Offset 0x0F73 - Reserved
+**/
+  UINT8                       Reserved30[48];
+
+/** Offset 0x0FA3 - Enable VMD controller
+  Enable/disable to VMD controller.0: Disable; 1: Enable(Default)
+  $EN_DIS
+**/
+  UINT8                       VmdEnable;
+
+/** Offset 0x0FA4 - Enable VMD Global Mapping
+  Enable/disable to VMD controller.0: Disable(Default); 1: Enable
+  $EN_DIS
+**/
+  UINT8                       VmdGlobalMapping;
+
+/** Offset 0x0FA5 - Map port under VMD
+  Map/UnMap port under VMD
+  $EN_DIS
+**/
+  UINT8                       VmdPort[31];
+
+/** Offset 0x0FC4 - Reserved
+**/
+  UINT8                       Reserved31[31];
+
+/** Offset 0x0FE3 - VMD Port Device
+  VMD Root port device number.
+**/
+  UINT8                       VmdPortDev[31];
+
+/** Offset 0x1002 - VMD Port Func
+  VMD Root port function number.
+**/
+  UINT8                       VmdPortFunc[31];
+
+/** Offset 0x1021 - Reserved
+**/
+  UINT8                       Reserved32[7];
+
+/** Offset 0x1028 - VMD Variable
+  VMD Variable Pointer.
+**/
+  UINT64                      VmdVariablePtr;
+
+/** Offset 0x1030 - Reserved
+**/
+  UINT8                      Reserved33[4];
+
+/** Offset 0x1034 - Temporary MemBar1 address for VMD
+  VMD Variable Pointer.
+**/
+  UINT32                      VmdMemBar1Base;
+
+/** Offset 0x1038 - Temporary MemBar2 address for VMD
+  VMD Variable Pointer.
+**/
+  UINT32                      VmdMemBar2Base;
+
+/** Offset 0x103C - Enable D3 Hot in TCSS
+  This policy will enable/disable D3 hot support in IOM
+  $EN_DIS
+**/
+  UINT8                       D3HotEnable;
+
+/** Offset 0x103D - Reserved
+**/
+  UINT8                       Reserved34[3];
+
+/** Offset 0x1040 - TypeC port GPIO setting
+  GPIO Ping number for Type C Aux orientation setting, use the GpioPad that is defined
+  in GpioPinsXXXH.h and GpioPinsXXXLp.h as argument.(XXX is platform name, Ex: Lnl
+  = LunarLake)
+**/
+  UINT32                      IomTypeCPortPadCfg[12];
+
+/** Offset 0x1070 - CPU USB3 Port Over Current Pin
+  Describe the specific over current pin number of USBC Port N.
+**/
+  UINT8                       CpuUsb3OverCurrentPin[10];
+
+/** Offset 0x107A - Enable D3 Cold in TCSS
+  This policy will enable/disable D3 cold support in IOM
+  $EN_DIS
+**/
+  UINT8                       D3ColdEnable;
+
+/** Offset 0x107B - TC State in TCSS
+  This TC C-State Limit in IOM
+**/
+  UINT8                       TcCstateLimit;
+
+/** Offset 0x107C - Reserved
+**/
+  UINT8                       Reserved35[2];
+
+/** Offset 0x107E - Enable/Disable PMC-PD Solution
+  This policy will enable/disable PMC-PD Solution vs EC-TCPC Solution
+  $EN_DIS
+**/
+  UINT8                       PmcPdEnable;
+
+/** Offset 0x107F - Reserved
+**/
+  UINT8                       Reserved36;
+
+/** Offset 0x1080 - TCSS Aux Orientation Override Enable
+  Bits 0, 2, ... 10 control override enables, bits 1, 3, ... 11 control overrides
+**/
+  UINT16                      TcssAuxOri;
+
+/** Offset 0x1082 - TCSS HSL Orientation Override Enable
+  Bits 0, 2, ... 10 control override enables, bits 1, 3, ... 11 control overrides
+**/
+  UINT16                      TcssHslOri;
+
+/** Offset 0x1084 - TCSS USB Port Enable
+  Bits 0, 1, ... max Type C port control enables
+**/
+  UINT8                       UsbTcPortEn;
+
+/** Offset 0x1085 - VCCST request for IOM
+  This policy will enable/disable VCCST and also decides if message would be replayed in S4/S5
+  $EN_DIS
+**/
+  UINT8                       VccSt;
+
+/** Offset 0x1086 - Enable/Disable PTM
+  This policy will enable/disable Precision Time Measurement for TCSS PCIe Root Ports
+  $EN_DIS
+**/
+  UINT8                       PtmEnabled[4];
+
+/** Offset 0x108A - PCIE RP Ltr Enable
+  Latency Tolerance Reporting Mechanism.
+**/
+  UINT8                       SaPcieItbtRpLtrEnable[4];
+
+/** Offset 0x108E - PCIE RP Snoop Latency Override Mode
+  Latency Tolerance Reporting, Snoop Latency Override Mode.
+**/
+  UINT8                       SaPcieItbtRpSnoopLatencyOverrideMode[4];
+
+/** Offset 0x1092 - PCIE RP Snoop Latency Override Multiplier
+  Latency Tolerance Reporting, Snoop Latency Override Multiplier.
+**/
+  UINT8                       SaPcieItbtRpSnoopLatencyOverrideMultiplier[4];
+
+/** Offset 0x1096 - PCIE RP Snoop Latency Override Value
+  Latency Tolerance Reporting, Snoop Latency Override Value.
+**/
+  UINT16                      SaPcieItbtRpSnoopLatencyOverrideValue[4];
+
+/** Offset 0x109E - PCIE RP Non Snoop Latency Override Mode
+  Latency Tolerance Reporting, Non-Snoop Latency Override Mode.
+**/
+  UINT8                       SaPcieItbtRpNonSnoopLatencyOverrideMode[4];
+
+/** Offset 0x10A2 - PCIE RP Non Snoop Latency Override Multiplier
+  Latency Tolerance Reporting, Non-Snoop Latency Override Multiplier.
+**/
+  UINT8                       SaPcieItbtRpNonSnoopLatencyOverrideMultiplier[4];
+
+/** Offset 0x10A6 - PCIE RP Non Snoop Latency Override Value
+  Latency Tolerance Reporting, Non-Snoop Latency Override Value.
+**/
+  UINT16                      SaPcieItbtRpNonSnoopLatencyOverrideValue[4];
+
+/** Offset 0x10AE - Force LTR Override
+  Force LTR Override.
+**/
+  UINT8                       SaPcieItbtRpForceLtrOverride[4];
+
+/** Offset 0x10B2 - PCIE RP Ltr Config Lock
+  0: Disable; 1: Enable.
+**/
+  UINT8                       SaPcieItbtRpLtrConfigLock[4];
+
+/** Offset 0x10B6 - Reserved
+**/
+  UINT8                       Reserved37[4];
+
+/** Offset 0x10BA - Touch Host Controller Assignment
+  Assign THC 0x0:ThcAssignmentNone, 0x1:ThcAssignmentThc0, 0x2:ThcAssignmentThc1
+**/
+  UINT8                       ThcAssignment[2];
+
+/** Offset 0x10BC - Touch Host Controller Interrupt Pin Mux
+  Set THC Pin Muxing Value if signal can be enabled on multiple pads. Refer to GPIO_*_MUXING_THC_SPIx_INTB_*
+  for possible values.
+**/
+  UINT8                       ThcInterruptPinMuxing[8];
+
+/** Offset 0x10C4 - Touch Host Controller Mode
+  Switch between Intel THC protocol and Industry standard HID Over SPI protocol. 0x0:Thc, 0x1:Hid
+**/
+  UINT8                       ThcMode[2];
+
+/** Offset 0x10C6 - Touch Host Controller Wake On Touch
+  Based on this setting vGPIO for given THC will be in native mode, and additional
+  _CRS for wake will be exposed in ACPI
+**/
+  UINT8                       ThcWakeOnTouch[2];
+
+/** Offset 0x10C8 - Reserved
+**/
+  UINT8                      Reserved38[337];
+
+/** Offset 0x1219 - PCHHOT# pin
+  Enable PCHHOT# pin assertion when temperature is higher than PchHotLevel. 0: disable, 1: enable
+  $EN_DIS
+**/
+  UINT8                       PchHotEnable;
+
+/** Offset 0x121A - Thermal Throttling Custimized T0Level Value
+  Custimized T0Level value.
+**/
+  UINT16                      PchT0Level;
+
+/** Offset 0x121C - Thermal Throttling Custimized T1Level Value
+  Custimized T1Level value.
+**/
+  UINT16                      PchT1Level;
+
+/** Offset 0x121E - Thermal Throttling Custimized T2Level Value
+  Custimized T2Level value.
+**/
+  UINT16                      PchT2Level;
+
+/** Offset 0x1220 - Enable The Thermal Throttle
+  Enable the thermal throttle function.
+  $EN_DIS
+**/
+  UINT8                       PchTTEnable;
+
+/** Offset 0x1221 - PMSync State 13
+  When set to 1 and the programmed GPIO pin is a 1, then PMSync state 13 will force
+  at least T2 state.
+  $EN_DIS
+**/
+  UINT8                       PchTTState13Enable;
+
+/** Offset 0x1222 - Thermal Throttle Lock
+  Thermal Throttle Lock.
+  $EN_DIS
+**/
+  UINT8                       PchTTLock;
+
+/** Offset 0x1223 - Thermal Throttling Suggested Setting
+  Thermal Throttling Suggested Setting.
+  $EN_DIS
+**/
+  UINT8                       TTSuggestedSetting;
+
+/** Offset 0x1224 - Thermal Device Temperature
+  Decides the temperature.
+**/
+  UINT16                      PchTemperatureHotLevel;
+
+/** Offset 0x1226 - Enable PCH TSN
+  Enable/disable TSN on the PCH.
+  $EN_DIS
+**/
+  UINT8                       PchTsnEnable[4];
+
+/** Offset 0x122A - Reserved
+**/
+  UINT8                      Reserved39[34];
+
+/** Offset 0x124C - Enable USB2 ports
+  Enable/disable per USB2 ports. One byte for each port, byte0 for port0, byte1 for
+  port1, and so on.
+**/
+  UINT8                       PortUsb20Enable[16];
+
+/** Offset 0x125C - Enable USB3 ports
+  Enable/disable per USB3 ports. One byte for each port, byte0 for port0, byte1 for
+  port1, and so on.
+**/
+  UINT8                       PortUsb30Enable[10];
+
+/** Offset 0x1266 - Enable xDCI controller
+  Enable/disable to xDCI controller.
+  $EN_DIS
+**/
+  UINT8                       XdciEnable;
+
+/** Offset 0x1267 - USB PDO Programming
+  Enable/disable PDO programming for USB in PEI phase. Disabling will allow for programming
+  during later phase. 1: enable, 0: disable
+  $EN_DIS
+**/
+  UINT8                       UsbPdoProgramming;
+
+/** Offset 0x1268 - Reserved
+**/
+  UINT8                       Reserved40;
+
+/** Offset 0x1269 - PCH USB OverCurrent mapping enable
+  1: Will program USB OC pin mapping in xHCI controller memory, 0: Will clear OC pin
+  mapping allow for NOA usage of OC pins
+  $EN_DIS
+**/
+  UINT8                       PchUsbOverCurrentEnable;
+
+/** Offset 0x126A - USB2 Port Over Current Pin
+  Describe the specific over current pin number of USB 2.0 Port N.
+**/
+  UINT8                       Usb2OverCurrentPin[16];
+
+/** Offset 0x127A - USB3 Port Over Current Pin
+  Describe the specific over current pin number of USB 3.0 Port N.
+**/
+  UINT8                       Usb3OverCurrentPin[10];
+
+/** Offset 0x1284 - Enable xHCI LTR override
+  Enables override of recommended LTR values for xHCI
+  $EN_DIS
+**/
+  UINT8                       PchUsbLtrOverrideEnable;
+
+/** Offset 0x1285 - Reserved
+**/
+  UINT8                       Reserved41[3];
+
+/** Offset 0x1288 - xHCI High Idle Time LTR override
+  Value used for overriding LTR recommendation for xHCI High Idle Time LTR setting
+**/
+  UINT32                      PchUsbLtrHighIdleTimeOverride;
+
+/** Offset 0x128C - xHCI Medium Idle Time LTR override
+  Value used for overriding LTR recommendation for xHCI Medium Idle Time LTR setting
+**/
+  UINT32                      PchUsbLtrMediumIdleTimeOverride;
+
+/** Offset 0x1290 - xHCI Low Idle Time LTR override
+  Value used for overriding LTR recommendation for xHCI Low Idle Time LTR setting
+**/
+  UINT32                      PchUsbLtrLowIdleTimeOverride;
+
+/** Offset 0x1294 - USB2 Port Reset Message Enable
+  0: Disable USB2 Port Reset Message; 1: Enable USB2 Port Reset Message; This must
+  be enable for USB2 Port those are paired with CPU XHCI Port
+**/
+  UINT8                       PortResetMessageEnable[16];
+
+/** Offset 0x12A4 - PCH USB OverCurrent mapping lock enable
+  If this policy option is enabled then BIOS will program OCCFDONE bit in xHCI meaning
+  that OC mapping data will be consumed by xHCI and OC mapping registers will be locked.
+  $EN_DIS
+**/
+  UINT8                       PchXhciOcLock;
+
+/** Offset 0x12A5 - USB Per Port HS Preemphasis Bias
+  USB Per Port HS Preemphasis Bias. 000b-0mV, 001b-11.25mV, 010b-16.9mV, 011b-28.15mV,
+  100b-28.15mV, 101b-39.35mV, 110b-45mV, 111b-56.3mV. One byte for each port.
+**/
+  UINT8                       Usb2PhyPetxiset[16];
+
+/** Offset 0x12B5 - USB Per Port HS Transmitter Bias
+  USB Per Port HS Transmitter Bias. 000b-0mV, 001b-11.25mV, 010b-16.9mV, 011b-28.15mV,
+  100b-28.15mV, 101b-39.35mV, 110b-45mV, 111b-56.3mV, One byte for each port.
+**/
+  UINT8                       Usb2PhyTxiset[16];
+
+/** Offset 0x12C5 - USB Per Port HS Transmitter Emphasis
+  USB Per Port HS Transmitter Emphasis. 00b - Emphasis OFF, 01b - De-emphasis ON,
+  10b - Pre-emphasis ON, 11b - Pre-emphasis & De-emphasis ON. One byte for each port.
+**/
+  UINT8                       Usb2PhyPredeemp[16];
+
+/** Offset 0x12D5 - USB Per Port Half Bit Pre-emphasis
+  USB Per Port Half Bit Pre-emphasis. 1b - half-bit pre-emphasis, 0b - full-bit pre-emphasis.
+  One byte for each port.
+**/
+  UINT8                       Usb2PhyPehalfbit[16];
+
+/** Offset 0x12E5 - Enable the write to USB 3.0 TX Output -3.5dB De-Emphasis Adjustment
+  Enable the write to USB 3.0 TX Output -3.5dB De-Emphasis Adjustment. Each value
+  in arrary can be between 0-1. One byte for each port.
+**/
+  UINT8                       Usb3HsioTxDeEmphEnable[10];
+
+/** Offset 0x12EF - USB 3.0 TX Output -3.5dB De-Emphasis Adjustment Setting
+  USB 3.0 TX Output -3.5dB De-Emphasis Adjustment Setting, HSIO_TX_DWORD5[21:16],
+  <b>Default = 29h</b> (approximately -3.5dB De-Emphasis). One byte for each port.
+**/
+  UINT8                       Usb3HsioTxDeEmph[10];
+
+/** Offset 0x12F9 - Enable the write to USB 3.0 TX Output Downscale Amplitude Adjustment
+  Enable the write to USB 3.0 TX Output Downscale Amplitude Adjustment, Each value
+  in arrary can be between 0-1. One byte for each port.
+**/
+  UINT8                       Usb3HsioTxDownscaleAmpEnable[10];
+
+/** Offset 0x1303 - USB 3.0 TX Output Downscale Amplitude Adjustment
+  USB 3.0 TX Output Downscale Amplitude Adjustment, HSIO_TX_DWORD8[21:16], <b>Default
+  = 00h</b>. One byte for each port.
+**/
+  UINT8                       Usb3HsioTxDownscaleAmp[10];
+
+/** Offset 0x130D
+**/
+  UINT8                       PchUsb3HsioCtrlAdaptOffsetCfgEnable[10];
+
+/** Offset 0x1317
+**/
+  UINT8                       PchUsb3HsioFilterSelNEnable[10];
+
+/** Offset 0x1321
+**/
+  UINT8                       PchUsb3HsioFilterSelPEnable[10];
+
+/** Offset 0x132B
+**/
+  UINT8                       PchUsb3HsioOlfpsCfgPullUpDwnResEnable[10];
+
+/** Offset 0x1335
+**/
+  UINT8                       PchUsb3HsioCtrlAdaptOffsetCfg[10];
+
+/** Offset 0x133F
+**/
+  UINT8                       PchUsb3HsioOlfpsCfgPullUpDwnRes[10];
+
+/** Offset 0x1349
+**/
+  UINT8                       PchUsb3HsioFilterSelN[10];
+
+/** Offset 0x1353
+**/
+  UINT8                       PchUsb3HsioFilterSelP[10];
+
+/** Offset 0x135D - Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 3
+  Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 3, Each
+  value in array can be between 0-1. One byte for each port.
+**/
+  UINT8                       Usb3HsioTxRate3UniqTranEnable[10];
+
+/** Offset 0x1367 - USB 3.0 TX Output Unique Transition Bit Scale for rate 3
+  USB 3.0 TX Output Unique Transition Bit Scale for rate 3, HSIO_TX_DWORD9[6:0], <b>Default
+  = 4Ch</b>. One byte for each port.
+**/
+  UINT8                       Usb3HsioTxRate3UniqTran[10];
+
+/** Offset 0x1371 - Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 2
+  Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 2, Each
+  value in array can be between 0-1. One byte for each port.
+**/
+  UINT8                       Usb3HsioTxRate2UniqTranEnable[10];
+
+/** Offset 0x137B - USB 3.0 TX Output Unique Transition Bit Scale for rate 2
+  USB 3.0 TX Output Unique Transition Bit Scale for rate 2, HSIO_TX_DWORD9[14:8],
+  <b>Default = 4Ch</b>. One byte for each port.
+**/
+  UINT8                       Usb3HsioTxRate2UniqTran[10];
+
+/** Offset 0x1385 - Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 1
+  Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 1, Each
+  value in array can be between 0-1. One byte for each port.
+**/
+  UINT8                       Usb3HsioTxRate1UniqTranEnable[10];
+
+/** Offset 0x138F - USB 3.0 TX Output Unique Transition Bit Scale for rate 1
+  USB 3.0 TX Output Unique Transition Bit Scale for rate 1, HSIO_TX_DWORD9[22:16],
+  <b>Default = 4Ch</b>. One byte for each port.
+**/
+  UINT8                       Usb3HsioTxRate1UniqTran[10];
+
+/** Offset 0x1399 - Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 0
+  Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 0, Each
+  value in array can be between 0-1. One byte for each port.
+**/
+  UINT8                       Usb3HsioTxRate0UniqTranEnable[10];
+
+/** Offset 0x13A3 - USB 3.0 TX Output Unique Transition Bit Scale for rate 0
+  USB 3.0 TX Output Unique Transition Bit Scale for rate 0, HSIO_TX_DWORD9[30:24],
+  <b>Default = 4Ch</b>. One byte for each port.
+**/
+  UINT8                       Usb3HsioTxRate0UniqTran[10];
+
+/** Offset 0x13AD - Reserved
+**/
+  UINT8                       Reserved42[4];
+
+/** Offset 0x13B1 - Enable/Disable NPU Device
+  Enable(Default): Enable NPU Device, Disable: Disable NPU Device
+  $EN_DIS
+**/
+  UINT8                       NpuEnable;
+
+/** Offset 0x13B2 - Enable LAN
+  Enable/disable LAN controller.
+  $EN_DIS
+**/
+  UINT8                       PchLanEnable;
+
+/** Offset 0x13B3 - Enable PCH Lan LTR capabilty of PCH internal LAN
+  0: Disable; 1: Enable.
+  $EN_DIS
+**/
+  UINT8                       PchLanLtrEnable;
+
+/** Offset 0x13B4 - Reserved
+**/
+  UINT8                       Reserved43;
+
+/** Offset 0x13B5 - Skip Ssid Programming.
+  When set to TRUE, silicon code will not do any SSID programming and platform code
+  needs to handle that by itself properly.
+  $EN_DIS
+**/
+  UINT8                       SiSkipSsidProgramming;
+
+/** Offset 0x13B6 - Change Default SVID
+  Change the default SVID used in FSP to programming internal devices. This is only
+  valid when SkipSsidProgramming is FALSE.
+**/
+  UINT16                      SiCustomizedSvid;
+
+/** Offset 0x13B8 - Change Default SSID
+  Change the default SSID used in FSP to programming internal devices. This is only
+  valid when SkipSsidProgramming is FALSE.
+**/
+  UINT16                      SiCustomizedSsid;
+
+/** Offset 0x13BA - Reserved
+**/
+  UINT8                       Reserved44[6];
+
+/** Offset 0x13C0 - SVID SDID table Poniter.
+  The address of the table of SVID SDID to customize each SVID SDID entry. This is
+  only valid when SkipSsidProgramming is FALSE.
+**/
+  UINT64                      SiSsidTablePtr;
+
+/** Offset 0x13C8 - Number of ssid table.
+  SiNumberOfSsidTableEntry should match the table entries created in SiSsidTablePtr.
+  This is only valid when SkipSsidProgramming is FALSE.
+**/
+  UINT16                      SiNumberOfSsidTableEntry;
+
+/** Offset 0x13CA - Reserved
+**/
+  UINT8                       Reserved45[10];
+
+/** Offset 0x13D4 - LogoPixelHeight Address
+  Address of LogoPixelHeight
+**/
+  UINT32                      LogoPixelHeight;
+
+/** Offset 0x13D8 - LogoPixelWidth Address
+  Address of LogoPixelWidth
+**/
+  UINT32                      LogoPixelWidth;
+
+/** Offset 0x13DC - Reserved
+**/
+  UINT8                       Reserved46[4];
+
+/** Offset 0x13E0 - Blt Buffer Address
+  Address of Blt buffer
+**/
+  UINT64                      BltBufferAddress;
+
+/** Offset 0x13E8 - Graphics Configuration Ptr
+  Points to VBT
+**/
+  UINT64                      GraphicsConfigPtr;
+
+/** Offset 0x13F0 - Enable/Disable SkipFspGop
+  Enable: Skip FSP provided GOP driver, Disable(Default): Use FSP provided GOP driver
+  $EN_DIS
+**/
+  UINT8                       SkipFspGop;
+
+/** Offset 0x13F1 - Reserved
+**/
+  UINT8                       Reserved47;
+
+/** Offset 0x13F2 - Enable/Disable IGFX RenderStandby
+  Enable(Default): Enable IGFX RenderStandby, Disable: Disable IGFX RenderStandby
+  $EN_DIS
+**/
+  UINT8                       RenderStandby;
+
+/** Offset 0x13F3 - Reserved
+**/
+  UINT8                       Reserved48[3];
+
+/** Offset 0x13F6 - Enable/Disable PavpEnable
+  Enable(Default): Enable PavpEnable, Disable: Disable PavpEnable
+  $EN_DIS
+**/
+  UINT8                       PavpEnable;
+
+/** Offset 0x13F7 - Enable/Disable PeiGraphicsPeimInit
+  <b>Enable(Default):</b> FSP will initialize the framebuffer and provide it via EFI_PEI_GRAPHICS_INFO_HOB.
+  Disable: FSP will NOT initialize the framebuffer.
+  $EN_DIS
+**/
+  UINT8                       PeiGraphicsPeimInit;
+
+/** Offset 0x13F8 - Reserved
+**/
+  UINT8                       Reserved49[4];
+
+/** Offset 0x13FC - Intel Graphics VBT (Video BIOS Table) Size
+  Size of Internal Graphics VBT Image
+**/
+  UINT32                      VbtSize;
+
+/** Offset 0x1400 - Platform LID Status for LFP Displays.
+  LFP Display Lid Status (LID_STATUS enum): 0 (Default): LidClosed, 1: LidOpen.
+  0: LidClosed, 1: LidOpen
+**/
+  UINT8                       LidStatus;
+
+/** Offset 0x1401 - Reserved
+**/
+  UINT8                       Reserved50[67];
+
+/** Offset 0x1444 - Address of PCH_DEVICE_INTERRUPT_CONFIG table.
+  The address of the table of PCH_DEVICE_INTERRUPT_CONFIG.
+**/
+  UINT32                      DevIntConfigPtr;
+
+/** Offset 0x1448 - Number of DevIntConfig Entry
+  Number of Device Interrupt Configuration Entry. If this is not zero, the DevIntConfigPtr
+  must not be NULL.
+**/
+  UINT8                       NumOfDevIntConfig;
+
+/** Offset 0x1449 - Select GPIO IRQ Route
+  GPIO IRQ Select. The valid value is 14 or 15.
+**/
+  UINT8                       GpioIrqRoute;
+
+/** Offset 0x144A - Select SciIrqSelect
+  SCI IRQ Select. The valid value is 9, 10, 11, and 20, 21, 22, 23 for APIC only.
+**/
+  UINT8                       SciIrqSelect;
+
+/** Offset 0x144B - Select TcoIrqSelect
+  TCO IRQ Select. The valid value is 9, 10, 11, 20, 21, 22, 23.
+**/
+  UINT8                       TcoIrqSelect;
+
+/** Offset 0x144C - Enable/Disable Tco IRQ
+  Enable/disable TCO IRQ
+  $EN_DIS
+**/
+  UINT8                       TcoIrqEnable;
+
+/** Offset 0x144D - Reserved
+**/
+  UINT8                       Reserved51[5];
+
+/** Offset 0x1452 - Mask to enable the usage of external V1p05 VR rail in specific S0ix or Sx states
+  Enable External V1P05 Rail in: BIT0:S0i1/S0i2, BIT1:S0i3, BIT2:S3, BIT3:S4, BIT5:S5
+**/
+  UINT8                       PchFivrExtV1p05RailEnabledStates;
+
+/** Offset 0x1453 - Mask to enable the platform configuration of external V1p05 VR rail
+  External V1P05 Rail Supported Configuration
+**/
+  UINT8                       PchFivrExtV1p05RailSupportedVoltageStates;
+
+/** Offset 0x1454 - External V1P05 Voltage Value that will be used in S0i2/S0i3 states
+  Value is given in 2.5mV increments (0=0mV, 1=2.5mV, 2=5mV...)
+**/
+  UINT16                      PchFivrExtV1p05RailVoltage;
+
+/** Offset 0x1456 - External V1P05 Icc Max Value
+  Granularity of this setting is 1mA and maximal possible value is 200mA
+**/
+  UINT8                       PchFivrExtV1p05RailIccMax;
+
+/** Offset 0x1457 - Mask to enable the usage of external Vnn VR rail in specific S0ix or Sx states
+  Enable External Vnn Rail in: BIT0:S0i1/S0i2, BIT1:S0i3, BIT2:S3, BIT3:S4, BIT5:S5
+**/
+  UINT8                       PchFivrExtVnnRailEnabledStates;
+
+/** Offset 0x1458 - Mask to enable the platform configuration of external Vnn VR rail
+  External Vnn Rail Supported Configuration
+**/
+  UINT8                       PchFivrExtVnnRailSupportedVoltageStates;
+
+/** Offset 0x1459 - Reserved
+**/
+  UINT8                       Reserved52;
+
+/** Offset 0x145A - External Vnn Voltage Value that will be used in S0ix/Sx states
+  Value is given in 2.5mV increments (0=0mV, 1=2.5mV, 2=5mV...), Default is set to 420
+**/
+  UINT16                      PchFivrExtVnnRailVoltage;
+
+/** Offset 0x145C - External Vnn Icc Max Value that will be used in S0ix/Sx states
+  Granularity of this setting is 1mA and maximal possible value is 200mA
+**/
+  UINT8                       PchFivrExtVnnRailIccMax;
+
+/** Offset 0x145D - Mask to enable the usage of external Vnn VR rail in Sx states
+  Use only if Ext Vnn Rail config is different in Sx. Enable External Vnn Rail in
+  Sx: BIT0-1:Reserved, BIT2:S3, BIT3:S4, BIT5:S5
+**/
+  UINT8                       PchFivrExtVnnRailSxEnabledStates;
+
+/** Offset 0x145E - External Vnn Voltage Value that will be used in Sx states
+  Use only if Ext Vnn Rail config is different in Sx. Value is given in 2.5mV increments
+  (0=0mV, 1=2.5mV, 2=5mV...)
+**/
+  UINT16                      PchFivrExtVnnRailSxVoltage;
+
+/** Offset 0x1460 - External Vnn Icc Max Value that will be used in Sx states
+  Use only if Ext Vnn Rail config is different in Sx. Granularity of this setting
+  is 1mA and maximal possible value is 200mA
+**/
+  UINT8                       PchFivrExtVnnRailSxIccMax;
+
+/** Offset 0x1461 - Transition time in microseconds from Low Current Mode Voltage to High Current Mode Voltage
+  This field has 1us resolution. When value is 0 PCH will not transition VCCIN_AUX
+  to low current mode voltage.
+**/
+  UINT8                       PchFivrVccinAuxLowToHighCurModeVolTranTime;
+
+/** Offset 0x1462 - Transition time in microseconds from Retention Mode Voltage to High Current Mode Voltage
+  This field has 1us resolution. When value is 0 PCH will not transition VCCIN_AUX
+  to retention mode voltage.
+**/
+  UINT8                       PchFivrVccinAuxRetToHighCurModeVolTranTime;
+
+/** Offset 0x1463 - Transition time in microseconds from Retention Mode Voltage to Low Current Mode Voltage
+  This field has 1us resolution. When value is 0 PCH will not transition VCCIN_AUX
+  to retention mode voltage.
+**/
+  UINT8                       PchFivrVccinAuxRetToLowCurModeVolTranTime;
+
+/** Offset 0x1464 - Transition time in microseconds from Off (0V) to High Current Mode Voltage
+  This field has 1us resolution. When value is 0 Transition to 0V is disabled.
+**/
+  UINT16                      PchFivrVccinAuxOffToHighCurModeVolTranTime;
+
+/** Offset 0x1466 - FIVR Dynamic Power Management
+  Enable/Disable FIVR Dynamic Power Management.
+  $EN_DIS
+**/
+  UINT8                       PchFivrDynPm;
+
+/** Offset 0x1467 - Reserved
+**/
+  UINT8                       Reserved53;
+
+/** Offset 0x1468 - External V1P05 Icc Max Value
+  Granularity of this setting is 1mA and maximal possible value is 500mA
+**/
+  UINT16                      PchFivrExtV1p05RailIccMaximum;
+
+/** Offset 0x146A - External Vnn Icc Max Value that will be used in S0ix/Sx states
+  Granularity of this setting is 1mA and maximal possible value is 500mA
+**/
+  UINT16                      PchFivrExtVnnRailIccMaximum;
+
+/** Offset 0x146C - External Vnn Icc Max Value that will be used in Sx states
+  Use only if Ext Vnn Rail config is different in Sx. Granularity of this setting
+  is 1mA and maximal possible value is 500mA
+**/
+  UINT16                      PchFivrExtVnnRailSxIccMaximum;
+
+/** Offset 0x146E - External V1P05 Control Ramp Timer value
+  Hold off time to be used when changing the v1p05_ctrl for external bypass value in us
+**/
+  UINT8                       PchFivrExtV1p05RailCtrlRampTmr;
+
+/** Offset 0x146F - External VNN Control Ramp Timer value
+  Hold off time to be used when changing the vnn_ctrl for external bypass value in us
+**/
+  UINT8                       PchFivrExtVnnRailCtrlRampTmr;
+
+/** Offset 0x1470 - PCH Compatibility Revision ID
+  This member describes whether or not the CRID feature of PCH should be enabled.
+  $EN_DIS
+**/
+  UINT8                       PchCrid;
+
+/** Offset 0x1471 - PCH Legacy IO Low Latency Enable
+  Set to enable low latency of legacy IO. <b>0: Disable</b>, 1: Enable
+  $EN_DIS
+**/
+  UINT8                       PchLegacyIoLowLatency;
+
+/** Offset 0x1472 - Reserved
+**/
+  UINT8                       Reserved54;
+
+/** Offset 0x1473 - PCH Unlock SideBand access
+  The SideBand PortID mask for certain end point (e.g. PSFx) will be locked before
+  3rd party code execution. 0: Lock SideBand access; 1: Unlock SideBand access.
+  $EN_DIS
+**/
+  UINT8                       PchSbAccessUnlock;
+
+/** Offset 0x1474 - Enable 8254 Static Clock Gating
+  Set 8254CGE=1 is required for SLP_S0 support. However, set 8254CGE=1 in POST time
+  might fail to boot legacy OS using 8254 timer. Make sure it is disabled to support
+  legacy OS using 8254 timer. Also enable this while S0ix is enabled.
+  $EN_DIS
+**/
+  UINT8                       Enable8254ClockGating;
+
+/** Offset 0x1475 - Enable 8254 Static Clock Gating On S3
+  This is only applicable when Enable8254ClockGating is disabled. FSP will do the
+  8254 CGE programming on S3 resume when Enable8254ClockGatingOnS3 is enabled. This
+  avoids the SMI requirement for the programming.
+  $EN_DIS
+**/
+  UINT8                       Enable8254ClockGatingOnS3;
+
+/** Offset 0x1476 - Enable PCH Io Apic Entry 24-119
+  0: Disable; 1: Enable.
+  $EN_DIS
+**/
+  UINT8                       PchIoApicEntry24_119;
+
+/** Offset 0x1477 - PCH Io Apic ID
+  This member determines IOAPIC ID. Default is 0x02.
+**/
+  UINT8                       PchIoApicId;
+
+/** Offset 0x1478 - CNVi Configuration
+  This option allows for automatic detection of Connectivity Solution. [Auto Detection]
+  assumes that CNVi will be enabled when available, [Disable] allows for disabling CNVi.
+  0:Disable, 1:Auto
+**/
+  UINT8                       CnviMode;
+
+/** Offset 0x1479 - CNVi Wi-Fi Core
+  Enable/Disable CNVi Wi-Fi Core, Default is ENABLE. 0: DISABLE, 1: ENABLE
+  $EN_DIS
+**/
+  UINT8                       CnviWifiCore;
+
+/** Offset 0x147A - CNVi BT Core
+  Enable/Disable CNVi BT Core, Default is ENABLE. 0: DISABLE, 1: ENABLE
+  $EN_DIS
+**/
+  UINT8                       CnviBtCore;
+
+/** Offset 0x147B - CNVi BT Interface
+  This option configures BT device interface to either USB/PCI
+  1:USB, 2:PCI
+**/
+  UINT8                       CnviBtInterface;
+
+/** Offset 0x147C - CNVi BT Audio Offload
+  Enable/Disable BT Audio Offload, Default is ENABLE. 0: DISABLE, 1: ENABLE
+  $EN_DIS
+**/
+  UINT8                       CnviBtAudioOffload;
+
+/** Offset 0x147D - Reserved
+**/
+  UINT8                       Reserved55[3];
+
+/** Offset 0x1480 - CNVi RF_RESET pin muxing
+  Select CNVi RF_RESET# pin depending on board routing. LP/P/M: GPP_A8 = 0x2942E408(default)
+  or GPP_F4 = 0x194CE404. H/S: 0. Refer to GPIO_*_MUXING_CNVI_RF_RESET_* in GpioPins*.h.
+**/
+  UINT32                      CnviRfResetPinMux;
+
+/** Offset 0x1484 - CNVi CLKREQ pin muxing
+  Select CNVi CLKREQ pin depending on board routing. LP/P/M: GPP_A9 = 0x3942E609(default)
+  or GPP_F5 = 0x394CE605. H/S: 0. Refer to GPIO_*_MUXING_CNVI_CRF_XTAL_CLKREQ_* in
+  GpioPins*.h.
+**/
+  UINT32                      CnviClkreqPinMux;
+
+/** Offset 0x1488 - Reserved
+**/
+  UINT8                       Reserved56;
+
+/** Offset 0x1489 - Enable Device 4
+  Enable/disable Device 4
+  $EN_DIS
+**/
+  UINT8                       Device4Enable;
+
+/** Offset 0x148A - Skip PAM regsiter lock
+  Enable: PAM register will not be locked by RC, platform code should lock it, Disable(Default):
+  PAM registers will be locked by RC
+  $EN_DIS
+**/
+  UINT8                       SkipPamLock;
+
+/** Offset 0x148B - Reserved
+**/
+  UINT8                       Reserved57;
+
+/** Offset 0x148C - PCH HDA Verb Table Entry Number
+  Number of Entries in Verb Table.
+**/
+  UINT8                       PchHdaVerbTableEntryNum;
+
+/** Offset 0x148D - Reserved
+**/
+  UINT8                       Reserved58[3];
+
+/** Offset 0x1490 - PCH HDA Verb Table Pointer
+  Pointer to Array of pointers to Verb Table.
+**/
+  UINT64                      PchHdaVerbTablePtr;
+
+/** Offset 0x1498 - PCH HDA Codec Sx Wake Capability
+  Capability to detect wake initiated by a codec in Sx
+**/
+  UINT8                       PchHdaCodecSxWakeCapability;
+
+/** Offset 0x1499 - Enable Pme
+  Enable Azalia wake-on-ring.
+  $EN_DIS
+**/
+  UINT8                       PchHdaPme;
+
+/** Offset 0x149A - HD Audio Link Frequency
+  HDA Link Freq (PCH_HDAUDIO_LINK_FREQUENCY enum): 0: 6MHz, 1: 12MHz, 2: 24MHz.
+  0: 6MHz, 1: 12MHz, 2: 24MHz
+**/
+  UINT8                       PchHdaLinkFrequency;
+
+/** Offset 0x149B - Reserved
+**/
+  UINT8                       Reserved59[2];
+
+/** Offset 0x149D - HD Audio Microphone Privacy applied for SoundWire Link number 0 in HW Mode
+  HD Audio Microphone Privacy applied for SoundWire Link number 0 in HW Mode: 0: Disable, 1: Enable
+  $EN_DIS
+**/
+  UINT8                       PchHdaMicPrivacyHwModeSoundWire0;
+
+/** Offset 0x149E - HD Audio Microphone Privacy applied for SoundWire Link number 1 in HW Mode
+  HD Audio Microphone Privacy applied for SoundWire Link number 1 in HW Mode: 0: Disable, 1: Enable
+  $EN_DIS
+**/
+  UINT8                       PchHdaMicPrivacyHwModeSoundWire1;
+
+/** Offset 0x149F - HD Audio Microphone Privacy applied for SoundWire Link number 2 in HW Mode
+  HD Audio Microphone Privacy applied for SoundWire Link number 2 in HW Mode: 0: Disable, 1: Enable
+  $EN_DIS
+**/
+  UINT8                       PchHdaMicPrivacyHwModeSoundWire2;
+
+/** Offset 0x14A0 - HD Audio Microphone Privacy applied for SoundWire Link number 3 in HW Mode
+  HD Audio Microphone Privacy applied for SoundWire Link number 3 in HW Mode: 0: Disable, 1: Enable
+  $EN_DIS
+**/
+  UINT8                       PchHdaMicPrivacyHwModeSoundWire3;
+
+/** Offset 0x14A1 - HD Audio Microphone Privacy applied for SoundWire Link number 4 in HW Mode
+  HD Audio Microphone Privacy applied for SoundWire Link number 4 in HW Mode: 0: Disable, 1: Enable
+  $EN_DIS
+**/
+  UINT8                       PchHdaMicPrivacyHwModeSoundWire4;
+
+/** Offset 0x14A2 - HD Audio Microphone Privacy applied for Dmic in HW Mode
+  HD Audio Microphone Privacy applied for Dmic in HW Mode: 0: Disable, 1: Enable
+  $EN_DIS
+**/
+  UINT8                       PchHdaMicPrivacyHwModeDmic;
+
+/** Offset 0x14A3 - Reserved
+**/
+  UINT8                       Reserved60[13];
+
+/** Offset 0x14B0 - Pointer to ChipsetInit Binary
+  ChipsetInit Binary Pointer.
+**/
+  UINT64                      ChipsetInitBinPtr;
+
+/** Offset 0x14B8 - Length of ChipsetInit Binary
+  ChipsetInit Binary Length.
+**/
+  UINT32                      ChipsetInitBinLen;
+
+/** Offset 0x14BC - Reserved
+**/
+  UINT8                       Reserved61[36];
+} FSP_S_CONFIG;
+
+/** Fsp S UPD Configuration
+**/
+typedef struct {
+
+/** Offset 0x0000
+**/
+  FSP_UPD_HEADER              FspUpdHeader;
+
+/** Offset 0x0020
+**/
+  FSPS_ARCH2_UPD              FspsArchUpd;
+
+/** Offset 0x0040
+**/
+  FSP_S_CONFIG                FspsConfig;
+
+/** Offset 0x14E0
+**/
+  UINT8                       FspsUpdRsvd36[6];
+
+/** Offset 0x14E6
+**/
+  UINT16                      UpdTerminator;
+} FSPS_UPD;
+
+#pragma pack()
+
+#endif
diff --git a/src/vendorcode/intel/fsp/fsp2_0/wildcatlake/MemInfoHob.h b/src/vendorcode/intel/fsp/fsp2_0/wildcatlake/MemInfoHob.h
new file mode 100644
index 0000000000..83e346ca5c
--- /dev/null
+++ b/src/vendorcode/intel/fsp/fsp2_0/wildcatlake/MemInfoHob.h
@@ -0,0 +1,409 @@
+/** @file
+  This file contains definitions required for creation of
+  Memory S3 Save data, Memory Info data and Memory Platform
+  data hobs.
+
+  @copyright
+  Copyright (c) 1999 - 2024, Intel Corporation. All rights reserved.<BR>
+  This program and the accompanying materials are licensed and made available under
+  the terms and conditions of the BSD License that accompanies this distribution.
+  The full text of the license may be found at
+  http://opensource.org/licenses/bsd-license.php.
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+@par Specification Reference:
+**/
+#ifndef _MEM_INFO_HOB_H_
+#define _MEM_INFO_HOB_H_
+
+
+#pragma pack (push, 1)
+
+extern EFI_GUID gSiMemoryS3DataGuid;
+extern EFI_GUID gSiMemoryS3Data2Guid;
+extern EFI_GUID gSiMemoryInfoDataGuid;
+extern EFI_GUID gSiMemoryPlatformDataGuid;
+
+#define MAX_NODE        2
+#define MAX_CH          4
+#define MAX_DDR5_CH     2
+#define MAX_DIMM        2
+
+// Must be same or higher than the corresponding definitions in MrcGlobalDefinitions.h
+#define _MAX_RANK_IN_CHANNEL       (4)       ///< The maximum number of ranks per channel.
+#define _MAX_SDRAM_IN_DIMM         (5)       ///< The maximum number of SDRAMs per DIMM.
+
+// Must match definitions in
+// Intel\OneSiliconPkg\IpBlock\MemoryInit\Mtl\Include\MrcInterface.h
+#define HOB_MAX_SAGV_POINTS 4
+
+///
+/// Host reset states from MRC.
+///
+#define  WARM_BOOT        2
+
+#define R_MC_CHNL_RANK_PRESENT  0x7C
+#define   B_RANK0_PRS           BIT0
+#define   B_RANK1_PRS           BIT1
+#define   B_RANK2_PRS           BIT4
+#define   B_RANK3_PRS           BIT5
+
+// @todo remove and use the MdePkg\Include\Pi\PiHob.h
+#if !defined(_PEI_HOB_H_) && !defined(__PI_HOB_H__)
+#ifndef __HOB__H__
+typedef struct _EFI_HOB_GENERIC_HEADER {
+  UINT16  HobType;
+  UINT16  HobLength;
+  UINT32  Reserved;
+} EFI_HOB_GENERIC_HEADER;
+
+typedef struct _EFI_HOB_GUID_TYPE {
+  EFI_HOB_GENERIC_HEADER  Header;
+  EFI_GUID                Name;
+  ///
+  /// Guid specific data goes here
+  ///
+} EFI_HOB_GUID_TYPE;
+#endif
+#endif
+
+///
+/// Defines taken from MRC so avoid having to include MrcInterface.h
+///
+
+//
+// Matches MAX_SPD_SAVE define in MRC
+//
+#ifndef MAX_SPD_SAVE
+#define MAX_SPD_SAVE 39
+#endif
+
+//
+// MRC version description.
+//
+typedef struct {
+  UINT8  Major;     ///< Major version number
+  UINT8  Minor;     ///< Minor version number
+  UINT8  Rev;       ///< Revision number
+  UINT8  Build;     ///< Build number
+} SiMrcVersion;
+
+//
+// Matches MrcChannelSts enum in MRC
+//
+#ifndef CHANNEL_NOT_PRESENT
+#define CHANNEL_NOT_PRESENT     0  // There is no channel present on the controller.
+#endif
+#ifndef CHANNEL_DISABLED
+#define CHANNEL_DISABLED        1  // There is a channel present but it is disabled.
+#endif
+#ifndef CHANNEL_PRESENT
+#define CHANNEL_PRESENT         2  // There is a channel present and it is enabled.
+#endif
+
+//
+// Matches MrcDimmSts enum in MRC
+//
+#ifndef DIMM_ENABLED
+#define DIMM_ENABLED     0  // DIMM/rank Pair is enabled, presence will be detected.
+#endif
+#ifndef DIMM_DISABLED
+#define DIMM_DISABLED    1  // DIMM/rank Pair is disabled, regardless of presence.
+#endif
+#ifndef DIMM_PRESENT
+#define DIMM_PRESENT     2  // There is a DIMM present in the slot/rank pair and it will be used.
+#endif
+#ifndef DIMM_NOT_PRESENT
+#define DIMM_NOT_PRESENT 3  // There is no DIMM present in the slot/rank pair.
+#endif
+
+//
+// Matches MrcBootMode enum in MRC
+//
+#ifndef __MRC_BOOT_MODE__
+#define __MRC_BOOT_MODE__                 //The below values are originated from MrcCommonTypes.h
+  #ifndef INT32_MAX
+  #define INT32_MAX                       (0x7FFFFFFF)
+  #endif  //INT32_MAX
+typedef enum {
+  bmCold,                                 ///< Cold boot
+  bmWarm,                                 ///< Warm boot
+  bmS3,                                   ///< S3 resume
+  bmFast,                                 ///< Fast boot
+  MrcBootModeMax,                         ///< MRC_BOOT_MODE enumeration maximum value.
+  MrcBootModeDelim = INT32_MAX            ///< This value ensures the enum size is consistent on both sides of the PPI.
+} MRC_BOOT_MODE;
+#endif  //__MRC_BOOT_MODE__
+
+//
+// Matches MrcDdrType enum in MRC
+//
+#ifndef MRC_DDR_TYPE_LPDDR5
+#define MRC_DDR_TYPE_LPDDR5   0
+#endif
+#ifndef MRC_DDR_TYPE_DDR5
+#define MRC_DDR_TYPE_DDR5     1
+#endif
+#ifndef MRC_DDR_TYPE_UNKNOWN
+#define MRC_DDR_TYPE_UNKNOWN  2
+#endif
+
+#define MAX_PROFILE_NUM       7 // number of memory profiles supported
+#define MAX_XMP_PROFILE_NUM   5 // number of XMP profiles supported
+
+#ifndef MAX_RCOMP_TARGETS
+#define MAX_RCOMP_TARGETS     5
+#endif
+
+#ifndef MAX_ODT_ENTRIES
+#define MAX_ODT_ENTRIES       11
+#endif
+
+#ifndef MAX_COPY_DIMM_DFE_TAPS
+#define MAX_COPY_DIMM_DFE_TAPS      2
+#endif
+
+#define MAX_TRACE_REGION              5
+#define MAX_TRACE_CACHE_TYPE          2
+
+//
+// DIMM timings
+//
+typedef struct {
+  UINT32 tCK;       ///< Memory cycle time, in femtoseconds.
+  UINT16 NMode;     ///< Number of tCK cycles for the channel DIMM's command rate mode.
+  UINT16 tCL;       ///< Number of tCK cycles for the channel DIMM's CAS latency.
+  UINT16 tCWL;      ///< Number of tCK cycles for the channel DIMM's minimum CAS write latency time.
+  UINT16 tFAW;      ///< Number of tCK cycles for the channel DIMM's minimum four activate window delay time.
+  UINT16 tRAS;      ///< Number of tCK cycles for the channel DIMM's minimum active to precharge delay time.
+  UINT16 tRCDtRP;   ///< Number of tCK cycles for the channel DIMM's minimum RAS# to CAS# delay time and Row Precharge delay time.
+  UINT32 tREFI;     ///< Number of tCK cycles for the channel DIMM's minimum Average Periodic Refresh Interval.
+  UINT16 tRFC;      ///< Number of tCK cycles for the channel DIMM's minimum refresh recovery delay time.
+  UINT16 tRFCpb;    ///< Number of tCK cycles for the channel DIMM's minimum per bank refresh recovery delay time.
+  UINT16 tRFC2;     ///< Number of tCK cycles for the channel DIMM's minimum refresh recovery delay time.
+  UINT16 tRFC4;     ///< Number of tCK cycles for the channel DIMM's minimum refresh recovery delay time.
+  UINT16 tRPab;     ///< Number of tCK cycles for the channel DIMM's minimum row precharge delay time for all banks.
+  UINT16 tRRD;      ///< Number of tCK cycles for the channel DIMM's minimum row active to row active delay time.
+  UINT16 tRRD_L;    ///< Number of tCK cycles for the channel DIMM's minimum row active to row active delay time for same bank groups.
+  UINT16 tRRD_S;    ///< Number of tCK cycles for the channel DIMM's minimum row active to row active delay time for different bank groups.
+  UINT16 tRTP;      ///< Number of tCK cycles for the channel DIMM's minimum internal read to precharge command delay time.
+  UINT16 tWR;       ///< Number of tCK cycles for the channel DIMM's minimum write recovery time.
+  UINT16 tWTR;      ///< Number of tCK cycles for the channel DIMM's minimum internal write to read command delay time.
+  UINT16 tWTR_L;    ///< Number of tCK cycles for the channel DIMM's minimum internal write to read command delay time for same bank groups.
+  UINT16 tWTR_S;    ///< Number of tCK cycles for the channel DIMM's minimum internal write to read command delay time for different bank groups.
+  UINT16 tCCD_L;    ///< Number of tCK cycles for the channel DIMM's minimum CAS-to-CAS delay for same bank group.
+  UINT16 tCCD_L_WR; ///< Number of tCK cycles for the channel DIMM's minimum Write-to-Write delay for same bank group.
+  UINT8  Resv[2];   ///< Reserved.
+} MRC_CH_TIMING;
+
+typedef struct {
+  UINT16 tRDPRE;     ///< Read CAS to Precharge cmd delay
+} MRC_IP_TIMING;
+
+typedef union {
+  struct {
+    UINT16 ContinuationCount                   :  7; ///< Bits 6:0
+    UINT16 ContinuationParity                  :  1; ///< Bits 7:7
+    UINT16 LastNonZeroByte                     :  8; ///< Bits 15:8
+  } Bits;
+  UINT16 Data;
+  UINT8  Data8[2];
+} HOB_MANUFACTURER_ID_CODE;
+
+///
+/// Memory SMBIOS & OC Memory Data Hob
+///
+typedef struct {
+  UINT8                     Status;                  ///< See MrcDimmStatus for the definition of this field.
+  UINT8                     DimmId;
+  UINT32                    DimmCapacity;            ///< DIMM size in MBytes.
+  HOB_MANUFACTURER_ID_CODE  MfgId;                   ///< Dram module manufacturer ID
+  HOB_MANUFACTURER_ID_CODE  CkdMfgID;                ///< Clock Driver (CKD) Manufacturer ID
+  UINT8                     CkdDeviceRev;            ///< Clock Driver (CKD) device revision
+  HOB_MANUFACTURER_ID_CODE  DramMfgID;               ///< Manufacturer ID code for DRAM chip on the module
+  UINT8                     ModulePartNum[30];       ///< Module part number in ASCII
+  UINT8                     RankInDimm;              ///< The number of ranks in this DIMM.
+  UINT8                     SpdDramDeviceType;       ///< Save SPD DramDeviceType information needed for SMBIOS structure creation.
+  UINT8                     SpdModuleType;           ///< Save SPD ModuleType information needed for SMBIOS structure creation.
+  UINT8                     SpdSave[MAX_SPD_SAVE];   ///< Save SPD Manufacturing information needed for SMBIOS structure creation.
+  UINT16                    Speed;                   ///< The maximum capable speed of the device, in MHz
+  UINT8                     MdSocket;                ///< MdSocket: 0 = Memory Down, 1 = Socketed. Needed for SMBIOS structure creation.
+  UINT8                     Banks;                   ///< Number of banks the DIMM contains.
+  UINT8                     BankGroups;              ///< Number of bank groups the DIMM contains.
+  UINT8                     DeviceDensity;           ///< Device Density in Gb
+  UINT32                    SerialNumber;            ///< DIMM Serial Number
+  UINT8                     TotalWidth;              ///< Total Data width in bits
+  UINT8                     DataWidth;               ///< Primary bus width in bits
+} DIMM_INFO;
+
+typedef struct {
+  UINT8            Status;                  ///< Indicates whether this channel should be used.
+  UINT8            ChannelId;
+  UINT8            DimmCount;               ///< Number of valid DIMMs that exist in the channel.
+  MRC_CH_TIMING    Timing[MAX_PROFILE_NUM]; ///< The channel timing values.
+  DIMM_INFO        DimmInfo[MAX_DIMM];      ///< Save the DIMM output characteristics.
+} CHANNEL_INFO;
+
+typedef struct {
+  UINT8            Status;                  ///< Indicates whether this controller should be used.
+  UINT16           DeviceId;                ///< The PCI device id of this memory controller.
+  UINT8            RevisionId;              ///< The PCI revision id of this memory controller.
+  UINT8            ChannelCount;            ///< Number of valid channels that exist on the controller.
+  CHANNEL_INFO     ChannelInfo[MAX_CH];     ///< The following are channel level definitions.
+} CONTROLLER_INFO;
+
+//
+// Each DIMM Slot Mechanical present bit map
+//
+typedef struct {
+  UINT8 MrcSlotMap[MAX_NODE][MAX_CH];
+} MRC_SLOTMAP;
+
+typedef struct {
+  UINT64   BaseAddress;   ///< Trace Base Address
+  UINT64   TotalSize;     ///< Total Trace Region of Same Cache type
+  UINT8    CacheType;     ///< Trace Cache Type
+  UINT8    ErrorCode;     ///< Trace Region Allocation Fail Error code
+  UINT8    Rsvd[2];
+} PSMI_MEM_INFO;
+
+/// This data structure contains per-SaGv timing values that are considered output by the MRC.
+typedef struct {
+  UINT32        DataRate;    ///< The memory rate for the current SaGv Point in units of MT/s
+  MRC_CH_TIMING JedecTiming; ///< Timings used for this entry's corresponding SaGv Point - derived from JEDEC SPD spec
+  MRC_IP_TIMING IpTiming;    ///< Timings used for this entry's corresponding SaGv Point - IP specific
+  UINT16        MaxMemoryBandwidth; ///< Maximum theoretical bandwidth in GB/s supported by GV
+} HOB_SAGV_TIMING_OUT;
+
+/// This data structure contains SAGV config values that are considered output by the MRC.
+typedef struct {
+  UINT32              NumSaGvPointsEnabled; ///< Count of the total number of SAGV Points enabled.
+  UINT32              SaGvPointMask;        ///< Bit mask where each bit indicates an enabled SAGV point.
+  HOB_SAGV_TIMING_OUT SaGvTiming[HOB_MAX_SAGV_POINTS];
+} HOB_SAGV_INFO;
+
+typedef struct _PPR_RESULT_COLUMNS_HOB {
+  UINT8  PprRowRepairsSuccessful;
+  UINT8  Controller;
+  UINT8  Channel;
+  UINT8  Rank;
+  UINT8  BankGroup;
+  UINT8  Bank;
+  UINT32 Row;
+  UINT8  Device;
+} PPR_RESULT_COLUMNS_HOB;
+
+/**
+  Memory Info Data Hob
+
+  <b>Revision 1:</b>
+  - Initial version. (from MTL)
+  <b>Revision 2:</b>
+  - Added MopPackages, MopDensity, MopRanks, MopVendor fields
+  <b>Revision 3:</b>
+  - Added MaxRankCapacity
+  - Removed DataWidth
+  - DIMM_INFO: increased ModulePartNum from 20 to 30 chars
+  - DIMM_INFO: Added SerialNumber, TotalWidth and DataWidth
+  - DIMM_INFO: Removed SpdModuleMemoryBusWidth
+  - MFG ID fields: use HOB_MANUFACTURER_ID_CODE instead of UINT16 for easier parsing
+
+**/
+typedef struct {
+  UINT8             Revision;
+  /** As defined in SMBIOS 3.0 spec
+    Section 7.18.2 and Table 75
+  **/
+  UINT8             MemoryType;                 ///< DDR type: DDR5 or LPDDR5, uses SMBIOS MEMORY_DEVICE_TYPE encoding
+  UINT16            MaximumMemoryClockSpeed;    ///< The maximum capable speed of the device, in megahertz (MHz)
+  UINT16            ConfiguredMemoryClockSpeed; ///< The configured clock speed to the memory device, in megahertz (MHz)
+  /** As defined in SMBIOS 3.0 spec
+    Section 7.17.3 and Table 72
+  **/
+  UINT8             ErrorCorrectionType;
+
+  SiMrcVersion      Version;
+  BOOLEAN           EccSupport;
+  UINT8             MemoryProfile;
+  UINT32            TotalPhysicalMemorySize;
+  UINT32            DefaultXmptCK[MAX_XMP_PROFILE_NUM];///< Stores the tCK value read from SPD XMP profiles if they exist.
+  UINT8             XmpProfileEnable;                  ///< If XMP capable DIMMs are detected, this will indicate which XMP Profiles are common among all DIMMs.
+  UINT8             XmpConfigWarning;                  ///< If XMP capable DIMMs config support only 1DPC, but 2DPC is installed
+  BOOLEAN           DynamicMemoryBoostTrainingFailed;  ///< TRUE if Dynamic Memory Boost failed to train and was force disabled on the last full training boot. FALSE otherwise.
+  UINT16            Ratio;                             ///< DDR Frequency Ratio, used for programs that require ratios higher then 255
+  UINT8             RefClk;
+  UINT32            VddVoltage[MAX_PROFILE_NUM];
+  UINT32            VddqVoltage[MAX_PROFILE_NUM];
+  UINT32            VppVoltage[MAX_PROFILE_NUM];
+  UINT16            RcompTarget[MAX_PROFILE_NUM][MAX_RCOMP_TARGETS];
+  UINT16            DimmOdt[MAX_PROFILE_NUM][MAX_DIMM][MAX_ODT_ENTRIES];
+  INT8              DimmDFE[MAX_PROFILE_NUM][MAX_DDR5_CH][MAX_DIMM][MAX_COPY_DIMM_DFE_TAPS];
+  CONTROLLER_INFO   Controller[MAX_NODE];
+  UINT32            NumPopulatedChannels;              ///< Total number of memory channels populated
+  HOB_SAGV_INFO     SagvConfigInfo;                    ///< This data structure contains SAGV config values that are considered output by the MRC.
+  BOOLEAN           IsIbeccEnabled;
+  UINT16            TotalMemWidth;                     ///< Total Memory Width in bits from all populated channels
+  UINT8             MopPackages;                       ///< Mop DRAM package population
+  UINT8             MopDensity;                        ///< Mop DRAM die density
+  UINT8             MopRanks;                          ///< Mop Number of ranks
+  UINT8             MopVendor;                         ///< Mop DRAM vendor ID
+  UINT8             PprRanInLastBoot;                  ///< Whether PPR ran in the prior boot
+  UINT16            PprDetectedErrors;                 ///< PPR: Counts of detected bad rows
+  UINT16            PprRepairFails;                    ///< PPR: Counts of repair failure
+  UINT16            PprForceRepairStatus;              ///< PPR: Force Repair Status
+  UINT16            PprRepairsSuccessful;              ///< PPR: Counts of repair successes
+  PPR_RESULT_COLUMNS_HOB PprErrorInfo;                 ///< PPR: Error location
+  UINT8             PprAvailableResources[MAX_NODE][MAX_CH][_MAX_RANK_IN_CHANNEL][_MAX_SDRAM_IN_DIMM]; ///< PPR available resources per device
+  BOOLEAN           MixedEccDimms;                     ///< TRUE if both ECC and nonECC Dimms were detected in the system
+  UINT8             MaxRankCapacity;                   ///< Maximum possible rank capacity in [GB]
+  UINT16            PprFailingChannelBitMask;          ///< PPR failing channel mask
+} MEMORY_INFO_DATA_HOB;
+
+/**
+  Memory Platform Data Hob
+
+  <b>Revision 1:</b>
+  - Initial version.
+  <b>Revision 2:</b>
+  - Added TsegBase, PrmrrSize, PrmrrBase, Gttbase, MmioSize, PciEBaseAddress fields
+**/
+typedef struct {
+  UINT8             Revision;
+  UINT8             Reserved[3];
+  UINT32            BootMode;
+  UINT32            TsegSize;
+  UINT32            TsegBase;
+  UINT32            PrmrrSize;
+  UINT64            PrmrrBase;
+  UINT32            GttBase;
+  UINT32            MmioSize;
+  UINT32            PciEBaseAddress;
+  PSMI_MEM_INFO     PsmiInfo[MAX_TRACE_CACHE_TYPE];
+  PSMI_MEM_INFO     PsmiRegionInfo[MAX_TRACE_REGION];
+  BOOLEAN           MrcBasicMemoryTestPass;
+} MEMORY_PLATFORM_DATA;
+
+typedef struct {
+  EFI_HOB_GUID_TYPE    EfiHobGuidType;
+  MEMORY_PLATFORM_DATA Data;
+  UINT8                *Buffer;
+} MEMORY_PLATFORM_DATA_HOB;
+
+#define EFI_RMT_OS_VARIABLE_NAME        L"Rmt"
+#define RMT_ENABLE  1
+#define RMT_DISABLE 0
+
+extern EFI_GUID gRmtVariableGuid;
+
+//Structure of RMT UEFI variable which should be R/W by OS
+//EnDsRmt - To enable Memory margining support
+
+typedef struct {
+  UINT8                EnDsRmt;
+} RMT_VAR;
+
+#pragma pack (pop)
+
+#endif // _MEM_INFO_HOB_H_

From ced4c0935945e17421eef246f106482df553b58a Mon Sep 17 00:00:00 2001
From: Jincheng Li <jincheng.li@intel.com>
Date: Mon, 23 Jun 2025 11:10:14 +0800
Subject: [PATCH 1603/3886] soc/intel/xeon_sp/gnr: Implement
 get_mmio_high_base_size

Report above 4G MMIO base and size to coreboot so that coreboot
could correctly set MTRR coverage for the whole region instead
of only covering PCI driver used parts, where much fragmentation
was introduced.

TESTED=Build and boot on intel/avenuecity CRB, check MTRR usage:
[DEBUG]  0x0000000080000000: PHYBASE0: Address = 0x0000000080000000, UC
[DEBUG]  0x000fffff80000800: PHYMASK0: Length  = 0x0000000080000000, Valid
[DEBUG]  0x00001e0000000000: PHYBASE1: Address = 0x00001e0000000000, UC
[DEBUG]  0x000fff0000000800: PHYMASK1: Length  = 0x0000010000000000, Valid
[DEBUG]  0x00001f0000000000: PHYBASE2: Address = 0x00001f0000000000, UC
[DEBUG]  0x000fffc000000800: PHYMASK2: Length  = 0x0000004000000000, Valid
[DEBUG]  0x0000000000000000: PHYBASE3
[DEBUG]  0x0000000000000000: PHYMASK3: Disabled

Change-Id: I61a7e96b3e7566d6a2c14951e7eb4f0be98c13e5
Signed-off-by: Jincheng Li <jincheng.li@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88279
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/soc/intel/xeon_sp/gnr/soc_util.c | 6 +++++-
 1 file changed, 5 insertions(+), 1 deletion(-)

diff --git a/src/soc/intel/xeon_sp/gnr/soc_util.c b/src/soc/intel/xeon_sp/gnr/soc_util.c
index 6912809d2d..0a74a0214b 100644
--- a/src/soc/intel/xeon_sp/gnr/soc_util.c
+++ b/src/soc/intel/xeon_sp/gnr/soc_util.c
@@ -165,5 +165,9 @@ bool is_memtype_processor_attached(uint16_t mem_type)
 
 bool get_mmio_high_base_size(resource_t *base, resource_t *size)
 {
-	return false;
+	const IIO_UDS *hob = get_iio_uds();
+	*base = hob->PlatformData.SystemMmio64Base;
+	*size = hob->PlatformData.SystemMmio64Limit - (*base) + 1;
+
+	return true;
 }

From c5613469aeaf63c63380505de37cc6f742c83c11 Mon Sep 17 00:00:00 2001
From: Benjamin Doron <benjamin.doron@9elements.com>
Date: Wed, 16 Jul 2025 14:11:59 -0400
Subject: [PATCH 1604/3886] device: Make a note that SeaBIOS doesn't support
 above 4G MMIO

This is fairly intuitive upon thinking about it, SeaBIOS has neither
long mode nor PAE page tables, but make it obvious to developers,
and let users know this.

Change-Id: I769c1bdb9d7ea78d56455d125adf3d9bf07a1211
Signed-off-by: Benjamin Doron <benjamin.doron@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88453
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/device/Kconfig | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/device/Kconfig b/src/device/Kconfig
index e1a8d38ea3..1e869521b5 100644
--- a/src/device/Kconfig
+++ b/src/device/Kconfig
@@ -1015,7 +1015,7 @@ config ALWAYS_ALLOW_ABOVE_4G_ALLOCATION
 	  Required for modern graphics cards that support resizable BAR, such as
 	  Intel Arc or AMD RX series.
 	  Please keep in mind that not all payloads support it
-	  (i.e: LinuxBoot and EDK2 do, GRUB doesn't).
+	  (i.e: LinuxBoot and EDK2 do, SeaBIOS and GRUB don't).
 
 config XHCI_UTILS
 	def_bool n

From 64056416479774d9e87f0cd2f1219331f57f9e21 Mon Sep 17 00:00:00 2001
From: Pranava Y N <pranavayn@google.com>
Date: Tue, 8 Jul 2025 14:03:56 +0530
Subject: [PATCH 1605/3886] mb/google/fatcat: Use same mainboard part number
 for all fatcat variants

This patch unifies all the fatcat variants based on
`BOARD_GOOGLE_MODEL_FATCAT` to use the same mainboard part number
`Fatcat`.

BUG=b:430205874
TEST=Able to build/boot fatcat

Change-Id: I13a45e4763abaa9dfe26c53b4e5051d50640291d
Signed-off-by: Pranava Y N <pranavayn@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88353
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
---
 src/mainboard/google/fatcat/Kconfig | 8 +-------
 1 file changed, 1 insertion(+), 7 deletions(-)

diff --git a/src/mainboard/google/fatcat/Kconfig b/src/mainboard/google/fatcat/Kconfig
index 620368371c..fa592c96c3 100644
--- a/src/mainboard/google/fatcat/Kconfig
+++ b/src/mainboard/google/fatcat/Kconfig
@@ -171,13 +171,7 @@ config MAINBOARD_FAMILY
 	default "Google_Fatcat"
 
 config MAINBOARD_PART_NUMBER
-	default "Fatcat" if BOARD_GOOGLE_FATCAT
-	default "Fatcat4ES" if BOARD_GOOGLE_FATCAT4ES
-	default "Fatcat_ish" if BOARD_GOOGLE_FATCATISH
-	default "Fatcatite" if BOARD_GOOGLE_FATCATITE
-	default "Fatcatite4ES" if BOARD_GOOGLE_FATCATITE4ES
-	default "Fatcatnuvo" if BOARD_GOOGLE_FATCATNUVO
-	default "Fatcatnuvo4ES" if BOARD_GOOGLE_FATCATNUVO4ES
+	default "Fatcat" if BOARD_GOOGLE_MODEL_FATCAT
 	default "Francka" if BOARD_GOOGLE_FRANCKA
 	default "Felino" if BOARD_GOOGLE_FELINO
 	default "Felino4ES" if BOARD_GOOGLE_FELINO4ES

From 82163aedc6f5787a7e9445ffc4602d1e07546f93 Mon Sep 17 00:00:00 2001
From: Patrick Rudolph <patrick.rudolph@9elements.com>
Date: Sat, 12 Apr 2025 08:56:50 +0200
Subject: [PATCH 1606/3886] soc/amd/common/block/cpu/noncar: Move BSS and DATA
 out of PT_LOAD

Currently .bss and .data are within the PT_LOAD area of the
bootblock.elf and thus are placed and initialized at the correct spot
when PSP loads the BIOS Reset Image into DRAM.

On S3 resume PSP verifies that the "BIOS Reset Image" is unmodified
before it hands over control to such. Due to the use of BSS and DATA
within the BIOS Reset Image and the modifications of such at previous
boot the verification always fails.

This change moves '.bss' and '.data' out of the *first* PT_LOAD area
and moves it into a separate data_segment also marked PT_LOAD. Since
the second PT_LOAD is ignored by AMDCOMPRESS it doesn't end in the area
being verified at S3 resume. Since '.data' is now part of a separate
PT_LOAD a new region is inserted called '.datacopy' which is filled
by using objcopy. In turn the assembly code in bootblock will memcpy
'.datacopy' to '.data'.

TEST: Can still boot on amd/birman+ and on up/squared.

Change-Id: Id159ade3029060ce2ca6abcb723d5bdfe8841c3a
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87305
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
---
 src/cpu/x86/copy_data_section.inc             |  7 ++-
 src/include/rules.h                           | 37 +++++++++++--
 src/soc/amd/cezanne/Makefile.mk               |  4 +-
 .../amd/common/block/cpu/noncar/Makefile.mk   | 14 +++++
 .../common/block/cpu/noncar/memlayout_x86.ld  | 55 ++++++++++++++++++-
 src/soc/amd/common/block/cpu/noncar/pre_c.S   |  3 +
 src/soc/amd/genoa_poc/Makefile.mk             |  4 +-
 src/soc/amd/glinda/Makefile.mk                |  4 +-
 src/soc/amd/mendocino/Makefile.mk             |  4 +-
 src/soc/amd/phoenix/Makefile.mk               |  4 +-
 src/soc/amd/picasso/Makefile.mk               |  4 +-
 11 files changed, 117 insertions(+), 23 deletions(-)

diff --git a/src/cpu/x86/copy_data_section.inc b/src/cpu/x86/copy_data_section.inc
index dccb8d3975..10e6f6c5d6 100644
--- a/src/cpu/x86/copy_data_section.inc
+++ b/src/cpu/x86/copy_data_section.inc
@@ -3,9 +3,10 @@
 #if ENV_SEPARATE_DATA_AND_BSS
 
 /*
- * Copy .data section content to Cache-As-Ram.
- * This code can be included from 32 bits or 64 bits code. It also preserves
- * registers.
+ * Copy .data section content from _data_load to it's linked
+ * address. Usually that's inside Cache-As-Ram.
+ * This code can be included from 32 bits or 64 bits code.
+ * It also preserves registers by using stack.
  */
 copy_data_section:
 #if ENV_X86_64
diff --git a/src/include/rules.h b/src/include/rules.h
index 1005058b48..673138bfe6 100644
--- a/src/include/rules.h
+++ b/src/include/rules.h
@@ -274,13 +274,38 @@
 #if ENV_X86
 /* Indicates memory layout is determined with arch/x86/car.ld. */
 #define ENV_CACHE_AS_RAM		(ENV_ROMSTAGE_OR_BEFORE && !CONFIG(RESET_VECTOR_IN_RAM))
-#else
-#define ENV_CACHE_AS_RAM		0
-#endif
 
-/* Indicates if the stage uses the _data and _bss regions defined in
- * arch/x86/car.ld */
-#define ENV_SEPARATE_DATA_AND_BSS	(ENV_CACHE_AS_RAM && (ENV_BOOTBLOCK || !CONFIG(NO_XIP_EARLY_STAGES)))
+/*
+ * ENV_SEPARATE_DATA_AND_BSS:
+ * When not set .data and .bss are in the same PT_LOAD segment defined
+ * in program.ld. When set .data and .bss are in a different PT_LOAD segment,
+ * defined outside of program.ld.
+ *
+ *
+ * On Intel APL the bootblock is loaded into a 4KiB SRAM.
+ * There's no space for .data and .bss.
+ * Once the bootblock code has set up CAR it will use it for .data and .bss.
+ * The other stages are load into CAR and doesn't need separation.
+ *
+ *
+ * On Non CAR AMD platforms the bootblock is loaded into DRAM on cold boot.
+ * On S3 the loader verifies that the bootblock has the same hash as on cold boot.
+ * As it must not change .data and .bss are not part of the PT_LOAD segment and
+ * the assembly code must set up .bss and load .data.
+ *
+ *
+ * On other platforms that use Cache As RAM:
+ * By default CAR implies separate .data and .bss.
+ * The stages execute from memory mapped SPI flash and use CAR as heap.
+ */
+#define ENV_SEPARATE_DATA_AND_BSS      (ENV_BOOTBLOCK || (ENV_CACHE_AS_RAM && !CONFIG(NO_XIP_EARLY_STAGES)))
+
+#else /* !ENV_X86 */
+
+#define ENV_CACHE_AS_RAM		0
+#define ENV_SEPARATE_DATA_AND_BSS	0
+
+#endif
 
 /* Currently ramstage has heap. */
 #define ENV_HAS_HEAP_SECTION	ENV_RAMSTAGE
diff --git a/src/soc/amd/cezanne/Makefile.mk b/src/soc/amd/cezanne/Makefile.mk
index 2747622a47..ee193e1bf2 100644
--- a/src/soc/amd/cezanne/Makefile.mk
+++ b/src/soc/amd/cezanne/Makefile.mk
@@ -115,7 +115,7 @@ PSP_APOB_BASE=$(CONFIG_PSP_APOB_DRAM_ADDRESS)
 
 # type = 0x62
 PSP_BIOSBIN_FILE=$(obj)/amd_biospsp.img
-PSP_ELF_FILE=$(objcbfs)/bootblock.elf
+PSP_ELF_FILE=$(objcbfs)/bootblock_fixed_data.elf
 PSP_BIOSBIN_SIZE=$(shell $(READELF_bootblock) -Wl $(PSP_ELF_FILE) | grep LOAD | awk '{print $$5}')
 PSP_BIOSBIN_DEST=$(shell $(READELF_bootblock) -Wl $(PSP_ELF_FILE) | grep LOAD | awk '{print $$3}')
 
@@ -217,7 +217,7 @@ $(obj)/amdfw.rom:	$(call strip_quotes, $(PSP_BIOSBIN_FILE)) \
 			$(DEP_FILES) \
 			$(AMDFWTOOL) \
 			$(obj)/fmap_config.h \
-			$(objcbfs)/bootblock.elf # this target also creates the .map file
+			$(objcbfs)/bootblock_fixed_data.elf # this target also creates the .map file
 	$(if $(PSP_APCB_FILES), ,$(error APCB_SOURCES is not set))
 	rm -f $@
 	@printf "    AMDFWTOOL  $(subst $(obj)/,,$(@))\n"
diff --git a/src/soc/amd/common/block/cpu/noncar/Makefile.mk b/src/soc/amd/common/block/cpu/noncar/Makefile.mk
index f3ada6250f..80072b529d 100644
--- a/src/soc/amd/common/block/cpu/noncar/Makefile.mk
+++ b/src/soc/amd/common/block/cpu/noncar/Makefile.mk
@@ -14,4 +14,18 @@ romstage-y += cpu.c
 ramstage-y += memmap.c
 ramstage-y += mpinit.c
 
+# See memlayout_x86.ld for details:
+# AMDCOMPRESS only supports one PT_LOAD segment.
+# 1. Copy .data section to .datacopy section
+#    Assembly will copy .datacopy to .data at runtime
+# 2. Mark .data and .bss as NOLOAD
+#    Drops the second PT_LOAD segment from ELF
+$(objcbfs)/bootblock_fixed_data.elf: $(objcbfs)/bootblock.elf
+	@printf "    OBJCOPY    $(notdir $(@))\n"
+	$(OBJCOPY_bootblock) --dump-section .data=$(objcbfs)/data.section $<
+	cp $< $@
+	$(OBJCOPY_bootblock) --set-section-flags .datacopy=load \
+		--set-section-flags .bss=noload --set-section-flags .data=noload $@
+	$(OBJCOPY_bootblock) --update-section .datacopy=$(objcbfs)/data.section $@
+
 endif # CONFIG_SOC_AMD_COMMON_BLOCK_NONCAR
diff --git a/src/soc/amd/common/block/cpu/noncar/memlayout_x86.ld b/src/soc/amd/common/block/cpu/noncar/memlayout_x86.ld
index 3c596f4c20..1161e38448 100644
--- a/src/soc/amd/common/block/cpu/noncar/memlayout_x86.ld
+++ b/src/soc/amd/common/block/cpu/noncar/memlayout_x86.ld
@@ -130,14 +130,64 @@ MEMORY
 }
 
 SECTIONS {
-	/* Page tables need to be at a 4K boundary so align the bootblock downwards */
+	/*
+	 * AMD's PSP will verify the integrity of the BIOS Reset Image at S3 resume,
+	 * thus it must not change during execution. Having .data and .bss between
+	 * .text and .reset breaks the integrity, as .bss or .data might get modified.
+	 *
+	 * Enable ENV_SEPARATE_DATA_AND_BSS for AMD's bootblock and mark as
+	 * data_segment to place it in the second PT_LOAD area. AMDCOMPRESS will ignore
+	 * the second PT_LOAD area and discard it.
+	 */
+	. = BOOTBLOCK_ADDR & ~(16 - 1);
+	.data . : {
+		_data = .;
+		*(.data);
+		*(.data.*);
+		*(.ldata);
+		*(.ldata.*);
+		*(.sdata);
+		*(.sdata.*);
+		. = ALIGN(ARCH_POINTER_ALIGN_SIZE);
+		_edata = .;
+		RECORD_SIZE(data)
+	} : data_segment
+
+	. = ALIGN(ARCH_POINTER_ALIGN_SIZE);
+
+	.bss . (NOLOAD) : {
+		_bss = .;
+		*(.bss)
+		*(.bss.*)
+		*(.lbss)
+		*(.lbss.*)
+		*(.sbss)
+		*(.sbss.*)
+		. = ALIGN(ARCH_POINTER_ALIGN_SIZE);
+		_ebss = .;
+		RECORD_SIZE(bss)
+	} : data_segment
+
 	. = (BOOTBLOCK_TOP - PROGRAM_SZ) & ~(4096 - 1);
 	_bootblock = .;
 
 	INCLUDE "bootblock/lib/program.ld"
 
-	PROGRAM_SZ = SIZEOF(.text) + SIZEOF(.bss) + SIZEOF(.data);
+	/*
+	 * Add free space for a copy of the data section. The assembly code will copy
+	 * the section to .data at runtime when ENV_SEPARATE_DATA_AND_BSS is set.
+	 *
+	 * objcopy will be used during build to copy the .data to the .datacopy section.
+	 * This ensures that only *one* loadable segment is being used as bootblock.
+	 */
+	.datacopy . : {
+		_datacopy = .;
+		. += SIZEOF(.data);
+		_edatacopy = .;
+	} : to_load = 0xff
+	_data_load = LOADADDR(.datacopy);
 
+	PROGRAM_SZ = SIZEOF(.text) + SIZEOF(.data);
 	. = _X86_RESET_VECTOR - EARLYASM_SZ;
 	. = ALIGN(16);
 	BOOTBLOCK_TOP = .;
@@ -159,6 +209,7 @@ SECTIONS {
 	.reset (_X86_RESET_VECTOR) : {
 		*(.reset);
 	} >resetsection
+
 	.last_byte (BOOTBLOCK_END - 1) : {
 		BYTE(0xff);
 	} >resetsection
diff --git a/src/soc/amd/common/block/cpu/noncar/pre_c.S b/src/soc/amd/common/block/cpu/noncar/pre_c.S
index b75458815e..3dc3dd30f0 100644
--- a/src/soc/amd/common/block/cpu/noncar/pre_c.S
+++ b/src/soc/amd/common/block/cpu/noncar/pre_c.S
@@ -42,6 +42,9 @@ bootblock_pre_c_entry:
 
 	movl	$_eearlyram_stack, %esp
 
+	/* Copy .data section content */
+#include <cpu/x86/copy_data_section.inc>
+
 	/* Align the stack and keep aligned for call to bootblock_c_entry() */
 	and	$0xfffffff0, %esp
 	sub	$8, %esp
diff --git a/src/soc/amd/genoa_poc/Makefile.mk b/src/soc/amd/genoa_poc/Makefile.mk
index 8a62852157..6e98378542 100644
--- a/src/soc/amd/genoa_poc/Makefile.mk
+++ b/src/soc/amd/genoa_poc/Makefile.mk
@@ -75,7 +75,7 @@ PSP_APOB_BASE=$(CONFIG_PSP_APOB_DRAM_ADDRESS)
 
 # type = 0x62
 PSP_BIOSBIN_FILE=$(obj)/amd_biospsp.img
-PSP_ELF_FILE=$(objcbfs)/bootblock.elf
+PSP_ELF_FILE=$(objcbfs)/bootblock_fixed_data.elf
 PSP_BIOSBIN_SIZE=$(shell $(READELF_bootblock) -Wl $(PSP_ELF_FILE) | grep LOAD | awk '{print $$5}')
 PSP_BIOSBIN_DEST=$(shell $(READELF_bootblock) -Wl $(PSP_ELF_FILE) | grep LOAD | awk '{print $$3}')
 
@@ -134,7 +134,7 @@ $(obj)/amdfw.rom:	$(call strip_quotes, $(PSP_BIOSBIN_FILE)) \
 			$(DEP_FILES) \
 			$(AMDFWTOOL) \
 			$(obj)/fmap_config.h \
-			$(objcbfs)/bootblock.elf # this target also creates the .map file
+			$(objcbfs)/bootblock_fixed_data.elf # this target also creates the .map file
 	$(if $(PSP_APCB_FILES), ,$(error APCB_SOURCES is not set))
 	rm -f $@
 	@printf "    AMDFWTOOL  $(subst $(obj)/,,$(@))\n"
diff --git a/src/soc/amd/glinda/Makefile.mk b/src/soc/amd/glinda/Makefile.mk
index eb488d6a0f..f4c55c6e33 100644
--- a/src/soc/amd/glinda/Makefile.mk
+++ b/src/soc/amd/glinda/Makefile.mk
@@ -122,7 +122,7 @@ PSP_APOB_BASE=$(CONFIG_PSP_APOB_DRAM_ADDRESS)
 
 # type = 0x62
 PSP_BIOSBIN_FILE=$(obj)/amd_biospsp.img
-PSP_ELF_FILE=$(objcbfs)/bootblock.elf
+PSP_ELF_FILE=$(objcbfs)/bootblock_fixed_data.elf
 PSP_BIOSBIN_SIZE=$(shell $(READELF_bootblock) -Wl $(PSP_ELF_FILE) | grep LOAD | awk '{print $$5}')
 PSP_BIOSBIN_DEST=$(shell $(READELF_bootblock) -Wl $(PSP_ELF_FILE) | grep LOAD | awk '{print $$3}')
 
@@ -237,7 +237,7 @@ $(obj)/amdfw.rom:	$(call strip_quotes, $(PSP_BIOSBIN_FILE)) \
 			$(DEP_FILES) \
 			$(AMDFWTOOL) \
 			$(obj)/fmap_config.h \
-			$(objcbfs)/bootblock.elf # this target also creates the .map file
+			$(objcbfs)/bootblock_fixed_data.elf # this target also creates the .map file
 	rm -f $@
 	@printf "    AMDFWTOOL  $(subst $(obj)/,,$(@))\n"
 	$(AMDFWTOOL) \
diff --git a/src/soc/amd/mendocino/Makefile.mk b/src/soc/amd/mendocino/Makefile.mk
index 06ac55bda4..b8fec5701c 100644
--- a/src/soc/amd/mendocino/Makefile.mk
+++ b/src/soc/amd/mendocino/Makefile.mk
@@ -124,7 +124,7 @@ PSP_APOB_BASE=$(CONFIG_PSP_APOB_DRAM_ADDRESS)
 
 # type = 0x62
 PSP_BIOSBIN_FILE=$(obj)/amd_biospsp.img
-PSP_ELF_FILE=$(objcbfs)/bootblock.elf
+PSP_ELF_FILE=$(objcbfs)/bootblock_fixed_data.elf
 PSP_BIOSBIN_SIZE=$(shell $(READELF_bootblock) -Wl $(PSP_ELF_FILE) | grep LOAD | awk '{print $$5}')
 PSP_BIOSBIN_DEST=$(shell $(READELF_bootblock) -Wl $(PSP_ELF_FILE) | grep LOAD | awk '{print $$3}')
 
@@ -264,7 +264,7 @@ $(obj)/amdfw.rom:	$(call strip_quotes, $(PSP_BIOSBIN_FILE)) \
 			$(DEP_FILES) \
 			$(AMDFWTOOL) \
 			$(obj)/fmap_config.h \
-			$(objcbfs)/bootblock.elf # this target also creates the .map file
+			$(objcbfs)/bootblock_fixed_data.elf # this target also creates the .map file
 	rm -f $@
 	@printf "    AMDFWTOOL  $(subst $(obj)/,,$(@))\n"
 	$(AMDFWTOOL) \
diff --git a/src/soc/amd/phoenix/Makefile.mk b/src/soc/amd/phoenix/Makefile.mk
index 68cc935f75..21f10c56b9 100644
--- a/src/soc/amd/phoenix/Makefile.mk
+++ b/src/soc/amd/phoenix/Makefile.mk
@@ -128,7 +128,7 @@ PSP_APOB_BASE=$(CONFIG_PSP_APOB_DRAM_ADDRESS)
 
 # type = 0x62
 PSP_BIOSBIN_FILE=$(obj)/amd_biospsp.img
-PSP_ELF_FILE=$(objcbfs)/bootblock.elf
+PSP_ELF_FILE=$(objcbfs)/bootblock_fixed_data.elf
 PSP_BIOSBIN_SIZE=$(shell $(READELF_bootblock) -Wl $(PSP_ELF_FILE) | grep LOAD | awk '{print $$5}')
 PSP_BIOSBIN_DEST=$(shell $(READELF_bootblock) -Wl $(PSP_ELF_FILE) | grep LOAD | awk '{print $$3}')
 
@@ -265,7 +265,7 @@ $(obj)/amdfw.rom:	$(call strip_quotes, $(PSP_BIOSBIN_FILE)) \
 			$(DEP_FILES) \
 			$(AMDFWTOOL) \
 			$(obj)/fmap_config.h \
-			$(objcbfs)/bootblock.elf # this target also creates the .map file
+			$(objcbfs)/bootblock_fixed_data.elf # this target also creates the .map file
 	rm -f $@
 	@printf "    AMDFWTOOL  $(subst $(obj)/,,$(@))\n"
 	$(AMDFWTOOL) \
diff --git a/src/soc/amd/picasso/Makefile.mk b/src/soc/amd/picasso/Makefile.mk
index 7ba975f0e4..0b574db845 100644
--- a/src/soc/amd/picasso/Makefile.mk
+++ b/src/soc/amd/picasso/Makefile.mk
@@ -116,7 +116,7 @@ PSP_APOB_BASE=$(CONFIG_PSP_APOB_DRAM_ADDRESS)
 
 # type = 0x62
 PSP_BIOSBIN_FILE=$(obj)/amd_biospsp.img
-PSP_ELF_FILE=$(objcbfs)/bootblock.elf
+PSP_ELF_FILE=$(objcbfs)/bootblock_fixed_data.elf
 PSP_BIOSBIN_SIZE=$(shell $(READELF_bootblock) -Wl $(PSP_ELF_FILE) | grep LOAD | awk '{print $$5}')
 PSP_BIOSBIN_DEST=$(shell $(READELF_bootblock) -Wl $(PSP_ELF_FILE) | grep LOAD | awk '{print $$3}')
 
@@ -225,7 +225,7 @@ $(obj)/amdfw.rom:	$(call strip_quotes, $(PSP_BIOSBIN_FILE)) \
 			$(DEP_FILES) \
 			$(AMDFWTOOL) \
 			$(obj)/fmap_config.h \
-			$(objcbfs)/bootblock.elf # this target also creates the .map file
+			$(objcbfs)/bootblock_fixed_data.elf # this target also creates the .map file
 	$(if $(PSP_APCB_FILES), ,$(error APCB_SOURCES is not set))
 	rm -f $@
 	@printf "    AMDFWTOOL  $(subst $(obj)/,,$(@))\n"

From 55ae0d8a371746d3b36993ab5b7318e23213fcb3 Mon Sep 17 00:00:00 2001
From: David Wu <david_wu@quanta.corp-partner.google.com>
Date: Fri, 27 Jun 2025 10:25:46 +0800
Subject: [PATCH 1607/3886] mb/google/nissa/var/baseboard/nissa: Add power
 limits functions

Support variant specific power limits

BUG=b:399236160
TEST=emerge-nissa coreboot and check correct value on dirks.

Change-Id: If09a8f4d157c6fd01aabae1e455e289d3908b39b
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88245
Reviewed-by: Derek Huang <derekhuang@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 .../brya/variants/baseboard/nissa/ramstage.c  | 85 +++++++++++++++++++
 1 file changed, 85 insertions(+)

diff --git a/src/mainboard/google/brya/variants/baseboard/nissa/ramstage.c b/src/mainboard/google/brya/variants/baseboard/nissa/ramstage.c
index a45b1eb4a9..e2c8f90107 100644
--- a/src/mainboard/google/brya/variants/baseboard/nissa/ramstage.c
+++ b/src/mainboard/google/brya/variants/baseboard/nissa/ramstage.c
@@ -3,6 +3,7 @@
 #include <baseboard/gpio.h>
 #include <baseboard/variants.h>
 #include <device/pci_ops.h>
+#include <ec/google/chromeec/ec.h>
 #include <gpio.h>
 #include <soc/gpio.h>
 #include <soc/ramstage.h>
@@ -10,6 +11,8 @@
 #include <static.h>
 #include <intelblocks/power_limit.h>
 
+#define SET_PSYSPL2(e, w) ((e) * (w) / 100)
+
 struct soc_power_limits_config *variant_get_soc_power_limit_config(void)
 {
 	config_t *config = config_of_soc();
@@ -38,6 +41,88 @@ struct soc_power_limits_config *variant_get_soc_power_limit_config(void)
 	return NULL;
 }
 
+static bool get_sku_index(const struct cpu_power_limits *limits, size_t num_entries,
+					size_t *intel_idx, size_t *nissa_idx)
+{
+	uint16_t mch_id = pci_s_read_config16(PCI_DEV(0, 0, 0), PCI_DEVICE_ID);
+	u8 tdp = get_cpu_tdp();
+	size_t i = 0;
+
+	for (i = 0; i < ARRAY_SIZE(cpuid_to_adl); i++) {
+		if (mch_id == cpuid_to_adl[i].cpu_id && tdp == cpuid_to_adl[i].cpu_tdp) {
+			*intel_idx = cpuid_to_adl[i].limits;
+			break;
+		}
+	}
+
+	if (i == ARRAY_SIZE(cpuid_to_adl)) {
+		printk(BIOS_ERR, "Cannot find correct intel sku index.\n");
+		return false;
+	}
+
+	for (i = 0; i < num_entries; i++) {
+		if (mch_id == limits[i].mchid && tdp == limits[i].cpu_tdp) {
+			*nissa_idx = i;
+			break;
+		}
+	}
+
+	if (i == num_entries) {
+		printk(BIOS_ERR, "Cannot find correct nissa sku index.\n");
+		return false;
+	}
+
+	return true;
+}
+
+void variant_update_psys_power_limits(const struct cpu_power_limits *limits,
+					const struct system_power_limits *sys_limits,
+					size_t num_entries,
+					const struct psys_config *config_psys)
+{
+	struct soc_power_limits_config *soc_config;
+	size_t intel_idx, nissa_idx;
+	u16 volts_mv, current_ma;
+	enum usb_chg_type type;
+	u32 psyspl2;
+	config_t *conf;
+	u32 watts;
+	int rv;
+
+	if (!num_entries)
+		return;
+
+	if (!get_sku_index(limits, num_entries, &intel_idx, &nissa_idx))
+		return;
+
+	conf = config_of_soc();
+	soc_config = &conf->power_limits_config[intel_idx];
+
+	rv = google_chromeec_get_usb_pd_power_info(&type, &current_ma, &volts_mv);
+
+	if (rv == 0 && type == USB_CHG_TYPE_PD) {
+		/* Detected USB-PD. Base on max value of adapter */
+		watts = ((u32)current_ma * volts_mv) / 1000000;
+
+		/* set psyspl2 to 97% of adapter rating */
+		psyspl2 = SET_PSYSPL2(config_psys->efficiency, watts);
+	} else {
+		/* Input type is barrel jack */
+		volts_mv = config_psys->bj_volts_mv;
+		psyspl2 = sys_limits[nissa_idx].psys_pl2_power;
+	}
+
+	/* voltage unit is milliVolts and current is in milliAmps */
+	soc_config->psys_pmax = (u16)(((u32)config_psys->psys_imax_ma * volts_mv) / 1000000);
+	conf->platform_pmax = soc_config->psys_pmax;
+
+	soc_config->tdp_psyspl2 = psyspl2;
+
+	printk(BIOS_INFO, "Overriding PsysPL2 (%u) Psys_Pmax (%u)\n",
+			soc_config->tdp_psyspl2,
+			soc_config->psys_pmax);
+}
+
 void variant_configure_pads(void)
 {
 	const struct pad_config *base_pads;

From a4284815741bce1ccf36e643670c1820a9659ea1 Mon Sep 17 00:00:00 2001
From: David Wu <david_wu@quanta.corp-partner.google.com>
Date: Mon, 30 Jun 2025 14:22:29 +0800
Subject: [PATCH 1608/3886] mb/google/nissa/var/dirks: Update power limits

Update PsysPL2 and PsysPmax values on dirks.

BUG=b:399236160
TEST=emerge-nissa coreboot and
     check PsysPL2 and PsysPmax values on dirks

Change-Id: I45f11cccc0c77fcdb73629065f71e1284c36857b
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88246
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Derek Huang <derekhuang@google.com>
---
 .../google/brya/variants/dirks/ramstage.c     | 53 +++++++++++++++++++
 1 file changed, 53 insertions(+)

diff --git a/src/mainboard/google/brya/variants/dirks/ramstage.c b/src/mainboard/google/brya/variants/dirks/ramstage.c
index d66241f413..04f9c6df83 100644
--- a/src/mainboard/google/brya/variants/dirks/ramstage.c
+++ b/src/mainboard/google/brya/variants/dirks/ramstage.c
@@ -1,5 +1,12 @@
 /* SPDX-License-Identifier: GPL-2.0-or-later */
 
+#include <baseboard/variants.h>
+#include <chip.h>
+#include <device/device.h>
+#include <device/pci_ids.h>
+#include <device/pci_ops.h>
+#include <ec/google/chromeec/ec.h>
+#include <intelblocks/power_limit.h>
 #include <soc/ramstage.h>
 
 void mainboard_silicon_init_params(FSP_S_CONFIG *params)
@@ -10,3 +17,49 @@ void mainboard_silicon_init_params(FSP_S_CONFIG *params)
 	params->MappingPchXhciUsbA[1] = 2;
 
 }
+
+const struct cpu_power_limits limits[] = {
+	/* SKU_ID, TDP (Watts), pl1_min, pl1_max, pl2_min, pl2_max, pl4 */
+	{ PCI_DID_INTEL_ADL_N_ID_1, 7, 3000, 6000,  25000,  25000, 78000 },
+	{ PCI_DID_INTEL_ADL_N_ID_2, 6, 3000, 6000,  25000,  25000, 78000 },
+	{ PCI_DID_INTEL_ADL_N_ID_3, 6, 3000, 6000,  25000,  25000, 78000 },
+};
+
+const struct system_power_limits sys_limits[] = {
+	/* SKU_ID, TDP (Watts), psys_pl2 (Watts) */
+	{ PCI_DID_INTEL_ADL_N_ID_1, 7, 63 },
+	{ PCI_DID_INTEL_ADL_N_ID_2, 6, 63 },
+	{ PCI_DID_INTEL_ADL_N_ID_3, 6, 63 },
+};
+
+/*
+ * Psys_pmax considerations.
+ *
+ * Given the hardware design in dirks, the serial shunt resistor is 0.01ohm.
+ * The full scale of hardware PSYS signal 1.6v maps to system current 6.009A
+ * instead of real system power. The equation is shown below:
+ * PSYS = 1.6v ~= (0.01ohm x 6.009A) x 50 (INA213, gain 50V/V) x PR222/(PR222 + R3193)
+ * PR222/(PR222 + R3193) = 0.5325 = 36K / (36K + 31.6K)
+ *
+ * The Psys_pmax is a SW setting which tells IMVP9.1 the mapping between system input
+ * current and the actual system power. Since there is no voltage information
+ * from PSYS, different voltage input would map to different Psys_pmax settings:
+ * For Type-C 15V, the Psys_pmax should be 15v x 6.009A = 90.135W
+ * For Type-C 20V, the Psys_pmax should be 20v x 6.009A = 120.18W
+ * For a barrel jack, the Psys_pmax should be 19v x 6.009A = 114.171W
+ *
+ * Imagine that there is a type-c 100W (20V/5A) connected to DUT w/ full loading,
+ * and the Psys_pmax setting is 120W. Then IMVP9.1 can calculate the current system
+ * power = 120W * 5A / 6.009A = 100W, which is the actual system power.
+ */
+const struct psys_config psys_config = {
+	.efficiency = 97,
+	.psys_imax_ma = 6009,
+	.bj_volts_mv = 19000,
+};
+
+void variant_devtree_update(void)
+{
+	size_t total_entries = ARRAY_SIZE(limits);
+	variant_update_psys_power_limits(limits, sys_limits, total_entries, &psys_config);
+}

From 67cd138df9397d93af987801eb19f57eaeb311cf Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Thu, 17 Jul 2025 12:51:30 -0500
Subject: [PATCH 1609/3886] soc/intel/apollolake: Add missing header in
 measured_boot.h

tss_structures.h is needed for SHA256_DIGEST_SIZE.

Change-Id: I0f19b09b770d1e7de6483beb55e901e5f7d3a456
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88473
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
---
 src/soc/intel/apollolake/include/soc/measured_boot.h | 1 +
 1 file changed, 1 insertion(+)

diff --git a/src/soc/intel/apollolake/include/soc/measured_boot.h b/src/soc/intel/apollolake/include/soc/measured_boot.h
index e6e06f3f08..492c1e63aa 100644
--- a/src/soc/intel/apollolake/include/soc/measured_boot.h
+++ b/src/soc/intel/apollolake/include/soc/measured_boot.h
@@ -3,6 +3,7 @@
 #ifndef _BOOT_GUARD_LIB_H_
 #define _BOOT_GUARD_LIB_H_
 
+#include <security/tpm/tss/tcg-2.0/tss_structures.h>
 #include <types.h>
 
 /* Boot Policy configuration for Boot Guard */

From 5cc4b9e6ce812d5d024e616c2a2c548ec1cf41d8 Mon Sep 17 00:00:00 2001
From: Maximilian Brune <maximilian.brune@9elements.com>
Date: Sat, 15 Mar 2025 14:48:35 +0100
Subject: [PATCH 1610/3886] soc/amd/common/cpu/noncar: Add bootblock overlap
 detection

Currently overlaps with bootblock are not detected by our linker script.
So increasing the PSP_SHAREDMEM_BASE + size to an extent that would
overlap with bootblock would be just ignored.

Add another region for the sole purpose of detecting these overlaps.
This may not be the ideal solution, but should sufficient for now.

Also check that the actual loadable segment of bootblock does not use up
more space then that.

Tested: Check that GCC and Clang can still compile it and that the
loadable segment (and therefore what PSP loads into memory) does not
change.

Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: I0f82f9b8655908676dc2d6545e72cb40fe9110e1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86862
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/soc/amd/common/block/cpu/noncar/memlayout_x86.ld | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/src/soc/amd/common/block/cpu/noncar/memlayout_x86.ld b/src/soc/amd/common/block/cpu/noncar/memlayout_x86.ld
index 1161e38448..4372de8760 100644
--- a/src/soc/amd/common/block/cpu/noncar/memlayout_x86.ld
+++ b/src/soc/amd/common/block/cpu/noncar/memlayout_x86.ld
@@ -95,6 +95,7 @@ SECTIONS
 	PSP_SHAREDMEM_DRAM_END(CONFIG_PSP_SHAREDMEM_BASE + CONFIG_PSP_SHAREDMEM_SIZE)
 #endif
 	_ = ASSERT(BOOTBLOCK_END == ((BOOTBLOCK_END + 0xFFFF) & 0xFFFF0000), "Bootblock end must be 16 bit aligned");
+	REGION(bootblock_overlap_detection, BOOTBLOCK_ADDR, CONFIG_C_ENV_BOOTBLOCK_SIZE, 1)
 	ROMSTAGE(CONFIG_ROMSTAGE_ADDR, CONFIG_ROMSTAGE_SIZE)
 
 #if CONFIG(PLATFORM_USES_FSP2_0)
@@ -214,5 +215,7 @@ SECTIONS {
 		BYTE(0xff);
 	} >resetsection
 	_ebootblock = BOOTBLOCK_END;
+
+	ASSERT(_ebootblock - _bootblock <= CONFIG_C_ENV_BOOTBLOCK_SIZE, "CONFIG_C_ENV_BOOTBLOCK_SIZE is not big enough")
 }
 #endif  /* ENV_BOOTBLOCK */

From 6aec09875be943a9975f1f7093046c93eab0c6b2 Mon Sep 17 00:00:00 2001
From: Vince Liu <vince-wl.liu@mediatek.corp-partner.google.com>
Date: Fri, 18 Jul 2025 21:38:14 +0800
Subject: [PATCH 1611/3886] soc/mediatek/mt8189: Add thermal driver

Add MT8189 thermal driver for LVTS (low voltage thermal sensor)
initialization.

BUG=b:379008996
BRANCH=none
TEST=temperature log should between 30~50 degrees:
[INFO ]  thermal_init: thermal initialized
[INFO ]  [LVTS_MSR] ts0 msr_all=13c50, valid=1, msr_temp=15440, temp=44430
[INFO ]  [LVTS_MSR] ts1 msr_all=13c41, valid=1, msr_temp=15425, temp=44660
[INFO ]  [LVTS_MSR] ts2 msr_all=13c3f, valid=1, msr_temp=15423, temp=44690
[INFO ]  [LVTS_MSR] ts3 msr_all=13c4e, valid=1, msr_temp=15438, temp=44461
[INFO ]  [LVTS_MSR] ts4 msr_all=13bc6, valid=1, msr_temp=15302, temp=46540
[INFO ]  [LVTS_MSR] ts5 msr_all=13bd2, valid=1, msr_temp=15314, temp=46356
[INFO ]  [LVTS_MSR] ts6 msr_all=13bd1, valid=1, msr_temp=15313, temp=46372
[INFO ]  [LVTS_MSR] ts7 msr_all=13bc9, valid=1, msr_temp=15305, temp=46494
[INFO ]  [LVTS_MSR] ts8 msr_all=13bed, valid=1, msr_temp=15341, temp=45944
[INFO ]  [LVTS_MSR] ts9 msr_all=13be3, valid=1, msr_temp=15331, temp=46097
[INFO ]  [LVTS_MSR] ts10 msr_all=13c01, valid=1, msr_temp=15361, temp=45638
[INFO ]  [LVTS_MSR] ts11 msr_all=13bc6, valid=1, msr_temp=15302, temp=46540
[INFO ]  [LVTS_MSR] ts12 msr_all=13c06, valid=1, msr_temp=15366, temp=45562
[INFO ]  [LVTS_MSR] ts13 msr_all=13c03, valid=1, msr_temp=15363, temp=45607
[INFO ]  [LVTS_MSR] ts14 msr_all=13bf3, valid=1, msr_temp=15347, temp=45852
[INFO ]  [LVTS_MSR] ts15 msr_all=13c1a, valid=1, msr_temp=15386, temp=45256
[INFO ]  [LVTS_MSR] ts16 msr_all=13c8b, valid=1, msr_temp=15499, temp=43528
[INFO ]  [LVTS_MSR] ts17 msr_all=13c8b, valid=1, msr_temp=15499, temp=43528

Signed-off-by: Raymond Sun <raymond.sun@mediatek.corp-partner.google.com>
Signed-off-by: Kai-chun Huang <kai-chun.huang@mediatek.corp-partner.google..com>
Change-Id: I37dd9da6592146ade556660fa07d2fa374646da5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88441
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/soc/mediatek/common/include/soc/symbols.h |   2 +
 .../common/include/soc/thermal_common.h       |   2 +
 src/soc/mediatek/common/thermal.c             |  12 +
 src/soc/mediatek/mt8189/Makefile.mk           |   2 +
 .../mediatek/mt8189/include/soc/addressmap.h  |   1 +
 src/soc/mediatek/mt8189/include/soc/efuse.h   |  10 +-
 .../mediatek/mt8189/include/soc/spm_mtcmos.h  |   1 +
 src/soc/mediatek/mt8189/include/soc/thermal.h |   8 +
 .../mt8189/include/soc/thermal_internal.h     | 170 +++++++
 src/soc/mediatek/mt8189/thermal.c             | 448 ++++++++++++++++++
 src/soc/mediatek/mt8189/thermal_sram.c        |   9 +
 11 files changed, 662 insertions(+), 3 deletions(-)
 create mode 100644 src/soc/mediatek/mt8189/include/soc/thermal.h
 create mode 100644 src/soc/mediatek/mt8189/include/soc/thermal_internal.h
 create mode 100644 src/soc/mediatek/mt8189/thermal.c
 create mode 100644 src/soc/mediatek/mt8189/thermal_sram.c

diff --git a/src/soc/mediatek/common/include/soc/symbols.h b/src/soc/mediatek/common/include/soc/symbols.h
index c0e46733ec..b709e5c71c 100644
--- a/src/soc/mediatek/common/include/soc/symbols.h
+++ b/src/soc/mediatek/common/include/soc/symbols.h
@@ -9,8 +9,10 @@ DECLARE_REGION(dram_dma)
 DECLARE_REGION(resv_mem_optee)
 DECLARE_REGION(resv_mem_gpu)
 DECLARE_REGION(resv_mem_gpueb)
+DECLARE_REGION(cpucooler_reserved)
 DECLARE_REGION(dvfs2_reserved)
 DECLARE_REGION(ptp1_reserved)
+DECLARE_REGION(thermal_reserved)
 DECLARE_OPTIONAL_REGION(mcufw_reserved)
 
 #endif /* _SOC_MEDIATEK_COMMON_SYMBOLS_H_ */
diff --git a/src/soc/mediatek/common/include/soc/thermal_common.h b/src/soc/mediatek/common/include/soc/thermal_common.h
index 7875aec7ea..9faca59b09 100644
--- a/src/soc/mediatek/common/include/soc/thermal_common.h
+++ b/src/soc/mediatek/common/include/soc/thermal_common.h
@@ -38,8 +38,10 @@ struct lvts_thermal_controller {
 int lvts_write_device(uint16_t config, uint8_t dev_reg_idx, uint8_t data, int tc_num);
 const struct lvts_thermal_controller *lvts_get_controller(int tc_num);
 void lvts_configure_polling_speed_and_filter(const struct lvts_thermal_controller *tc);
+void lvts_set_device_single_mode(int tc_num);
 int lvts_read_tc_raw_and_temp(void *msr_reg, enum lvts_sensor ts_name, uint32_t golden_temp);
 void lvts_thermal_init(void);
+void lvts_clock_gate_disable(void);
 void lvts_tscpu_reset_thermal(void);
 void lvts_thermal_cal_prepare(void);
 void lvts_device_identification(void);
diff --git a/src/soc/mediatek/common/thermal.c b/src/soc/mediatek/common/thermal.c
index 47babf5ee4..4fedf73821 100644
--- a/src/soc/mediatek/common/thermal.c
+++ b/src/soc/mediatek/common/thermal.c
@@ -10,6 +10,14 @@
 #define LVTS_SENSOR_POINT_SELECTION_SETTING	0x13121110
 #define LVTS_CALCULATION_SCALING_RULE		0x300
 
+__weak void lvts_set_device_single_mode(int tc_num)
+{
+}
+
+__weak void lvts_clock_gate_disable(void)
+{
+}
+
 static int lvts_raw_to_temp(uint16_t msr_raw, enum lvts_sensor ts_name, uint32_t golden_temp)
 {
 	int temp_mc;
@@ -66,6 +74,8 @@ static void lvts_tscpu_thermal_initial_all_tc(void)
 		write32(&tc->regs->lvtstssel_0, LVTS_SENSOR_POINT_SELECTION_SETTING);
 		/* Set calculation scale rules */
 		write32(&tc->regs->lvtscalscale_0, LVTS_CALCULATION_SCALING_RULE);
+		/* Set Device Single mode */
+		lvts_set_device_single_mode(i);
 
 		lvts_configure_polling_speed_and_filter(tc);
 	}
@@ -311,6 +321,8 @@ void lvts_thermal_init(void)
 	if (lvts_lk_init_check())
 		return;
 
+	lvts_clock_gate_disable();
+
 	lvts_tscpu_reset_thermal();
 
 	lvts_thermal_cal_prepare();
diff --git a/src/soc/mediatek/mt8189/Makefile.mk b/src/soc/mediatek/mt8189/Makefile.mk
index f7294c0e74..cf44747310 100644
--- a/src/soc/mediatek/mt8189/Makefile.mk
+++ b/src/soc/mediatek/mt8189/Makefile.mk
@@ -24,6 +24,8 @@ romstage-y += dvfs.c
 romstage-y += ../common/emi.c
 romstage-y += ../common/memory.c ../common/memory_test.c ../common/memory_type.c
 romstage-y += ../common/mmu_operations.c ../common/mmu_cmops.c
+romstage-y += ../common/thermal.c thermal.c
+romstage-y += ../common/thermal_sram.c thermal_sram.c
 romstage-y += ../common/mt6315.c mt6315.c
 romstage-y += ../common/mt6359p.c mt6359p.c
 romstage-y += ../common/pmif.c ../common/pmif_clk.c ../common/pmif_init.c pmif_clk.c
diff --git a/src/soc/mediatek/mt8189/include/soc/addressmap.h b/src/soc/mediatek/mt8189/include/soc/addressmap.h
index b591d1c294..fed77162e8 100644
--- a/src/soc/mediatek/mt8189/include/soc/addressmap.h
+++ b/src/soc/mediatek/mt8189/include/soc/addressmap.h
@@ -35,6 +35,7 @@ enum {
 	INFRA_AO_BCRM_BASE		= IO_PHYS + 0x00022000,
 	DEVAPC_INFRA_AO_BASE		= IO_PHYS + 0x00030000,
 	DEVAPC_INFRA_AO1_BASE		= IO_PHYS + 0x00034000,
+	INFRACFG_BASE			= IO_PHYS + 0x0020E000,
 	EMI0_BASE			= IO_PHYS + 0x00219000,
 	EMI0_MPU_BASE			= IO_PHYS + 0x00226000,
 	DRAMC_CHA_AO_BASE		= IO_PHYS + 0x00230000,
diff --git a/src/soc/mediatek/mt8189/include/soc/efuse.h b/src/soc/mediatek/mt8189/include/soc/efuse.h
index 47cc54af4f..5ef62267d6 100644
--- a/src/soc/mediatek/mt8189/include/soc/efuse.h
+++ b/src/soc/mediatek/mt8189/include/soc/efuse.h
@@ -4,19 +4,23 @@
 #define __SOC_MEDIATEK_MT8189_INCLUDE_SOC_EFUSE_H__
 
 #include <soc/addressmap.h>
+#include <soc/thermal_internal.h>
 #include <stdint.h>
 
 struct efuse_regs {
 	u32 reserved1[96];
 	u32 adc_cali_reg;
-	u32 reserved2[391];
+	u32 reserved2[8];
+	u32 lvts_reg[LVTS_ADDRESS_INDEX_NUM];
+	u32 reserved3[360];
 	u32 cpu_id_reg;
-	u32 reserved3[15];
+	u32 reserved4[15];
 	u32 cpu_seg_id_reg;
-	u32 reserved4[14908];
+	u32 reserved5[14908];
 	u32 ecc_status_reg;
 };
 check_member(efuse_regs, adc_cali_reg, 0x180);
+check_member(efuse_regs, lvts_reg, 0x1A4);
 check_member(efuse_regs, cpu_id_reg, 0x7A0);
 check_member(efuse_regs, cpu_seg_id_reg, 0x7E0);
 check_member(efuse_regs, ecc_status_reg, 0xF0D4);
diff --git a/src/soc/mediatek/mt8189/include/soc/spm_mtcmos.h b/src/soc/mediatek/mt8189/include/soc/spm_mtcmos.h
index 707b96371b..e68b531bb9 100644
--- a/src/soc/mediatek/mt8189/include/soc/spm_mtcmos.h
+++ b/src/soc/mediatek/mt8189/include/soc/spm_mtcmos.h
@@ -60,6 +60,7 @@ struct mtk_infracfg_ao_regs {
 };
 check_member(mtk_infracfg_ao_regs, infra_bus_dcm_ctrl, 0x0070);
 check_member(mtk_infracfg_ao_regs, infracfg_ao_module_cg_0_set, 0x0080);
+check_member(mtk_infracfg_ao_regs, infracfg_ao_module_cg_0_clr, 0x0084);
 check_member(mtk_infracfg_ao_regs, infracfg_ao_module_cg_1, 0x0094);
 check_member(mtk_infracfg_ao_regs, infracfg_ao_module_cg_2_set, 0x00A4);
 check_member(mtk_infracfg_ao_regs, infracfg_ao_module_cg_3_set, 0x00C0);
diff --git a/src/soc/mediatek/mt8189/include/soc/thermal.h b/src/soc/mediatek/mt8189/include/soc/thermal.h
new file mode 100644
index 0000000000..4291857ebb
--- /dev/null
+++ b/src/soc/mediatek/mt8189/include/soc/thermal.h
@@ -0,0 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0-only OR MIT */
+
+#ifndef __SOC_MEDIATEK_MT8189_INCLUDE_SOC_THERMAL_H__
+#define __SOC_MEDIATEK_MT8189_INCLUDE_SOC_THERMAL_H__
+
+#include <soc/thermal_common.h>
+
+#endif /* __SOC_MEDIATEK_MT8189_INCLUDE_SOC_THERMAL_H__ */
diff --git a/src/soc/mediatek/mt8189/include/soc/thermal_internal.h b/src/soc/mediatek/mt8189/include/soc/thermal_internal.h
new file mode 100644
index 0000000000..562cb9fa27
--- /dev/null
+++ b/src/soc/mediatek/mt8189/include/soc/thermal_internal.h
@@ -0,0 +1,170 @@
+/* SPDX-License-Identifier: GPL-2.0-only OR MIT */
+
+#ifndef __SOC_MEDIATEK_MT8189_INCLUDE_SOC_THERMAL_INTERNAL_H__
+#define __SOC_MEDIATEK_MT8189_INCLUDE_SOC_THERMAL_INTERNAL_H__
+
+#include <soc/addressmap.h>
+#include <soc/spm_mtcmos.h>
+#include <soc/symbols.h>
+
+#define LVTS_MAGIC			0x0000555
+#define MAX_TS_NUMBER			4
+
+#define LVTS_COF_T_SLP_GLD		219960
+#define LVTS_COF_COUNT_R_GLD		14437
+#define LVTS_COF_T_CONST_OFS		280000
+#define LVTS_ADDRESS_INDEX_NUM		(L_TS_LVTS_NUM + LVTS_CONTROLLER_NUM)
+#define LVTS_GROUP_INTERVAL_DELAY_MASK	GENMASK(29, 20)
+#define LVTS_COEFF_A			(-250460)
+
+#define DEFAULT_EFUSE_GOLDEN_TEMP	50
+#define DEFAULT_EFUSE_GOLDEN_TEMP_HT	170
+#define DEFAULT_EFUSE_COUNT		35000
+#define DEFAULT_EFUSE_COUNT_RC		2750
+
+/* INFRACFG_AO_BASE + 0x0084 */
+#define THERM_CG			BIT(10)
+
+/* THERM_CTRL_BASE + lvts_tc_offset_enum + 0x0050 */
+#define DEVICE_SENSING_STATUS		BIT(25)
+#define DEVICE_ACCESS_START_BIT		BIT(24)
+#define WRITE_ACCESS			BIT(16)
+
+/* THERM_CTRL_BASE + lvts_tc_offset_enum + 0x000C */
+#define STAGE3_INT_EN			BIT(31)
+
+/* SRAM for Thermal */
+#define THERMAL_ATC_SRAM_OFFSET		0x280
+#define THERMAL_SRAM_BASE		(_thermal_reserved + THERMAL_ATC_SRAM_OFFSET)
+#define THERMAL_SRAM_LEN		(24 * 4)
+#define THERMAL_STAT_SRAM_BASE		_cpucooler_reserved
+#define THERMAL_STAT_SRAM_LEN		REGION_SIZE(cpucooler_reserved)
+
+/*
+ * module		LVTS Plan
+ *=====================================================
+ * MCU_BIG core0/1	LVTS1-0, LVTS1-1, LVTS1-2, LVTS1-3
+ * MCU_BIG core2/3	LVTS2-0, LVTS2-1, LVTS2-2, LVTS2-3
+ * MCU_LITTLE		LVTS3-0, LVTS3-1, LVTS3-2, LVTS3-3
+ * SOC-TOP,APU		LVTS4-0, LVTS4-1, LVTS4-2, LVTS4-3
+ * GPU			LVTS5-0, LVTS5-1
+ * ptp_therm_ctrl_AP  Base address: (+0x1031_5000), 0x1031_5100, 0x1031_5200
+ * ptp_therm_ctrl_MCU Base address: (+0x1031_6000), 0x1031_6100, 0x1031_6200, 0x1031_6300
+ */
+
+/* private thermal sensor */
+enum lvts_sensor {
+	L_TS_LVTS1_0 = 0,	/* LVTS1-0 Big-core0 */
+	L_TS_LVTS1_1,		/* LVTS1-1 Big-core0 */
+	L_TS_LVTS1_2,		/* LVTS1-2 Big-core1 */
+	L_TS_LVTS1_3,		/* LVTS1-3 Big-core1 */
+	L_TS_LVTS2_0,		/* LVTS2-0 Big-core2 */
+	L_TS_LVTS2_1,		/* LVTS2-1 Big-core2 */
+	L_TS_LVTS2_2,		/* LVTS2-2 Big-core3 */
+	L_TS_LVTS2_3,		/* LVTS2-3 Big-core3 */
+	L_TS_LVTS3_0,		/* LVTS3-0 Little-core0 */
+	L_TS_LVTS3_1,		/* LVTS3-1 Little-core1 */
+	L_TS_LVTS3_2,		/* LVTS3-2 Little-core2 */
+	L_TS_LVTS3_3,		/* LVTS3-3 Little-core3 */
+	L_TS_LVTS4_0,		/* LVTS4-0 SCO-TOP */
+	L_TS_LVTS4_1,		/* LVTS4-1 SCO-TOP */
+	L_TS_LVTS4_2,		/* LVTS4-0 SCO-TOP */
+	L_TS_LVTS4_3,		/* LVTS4-1 APU */
+	L_TS_LVTS5_0,		/* LVTS5-0 GPU */
+	L_TS_LVTS5_1,		/* LVTS5-1 GPU */
+	L_TS_LVTS_NUM,
+};
+
+enum lvts_tc_enum {
+	LVTS_MCU_CONTROLLER0 = 0,
+	LVTS_MCU_CONTROLLER1,
+	LVTS_MCU_CONTROLLER2,
+	LVTS_AP_CONTROLLER0,
+	LVTS_MFG_CONTROLLER0,
+	LVTS_CONTROLLER_NUM,
+};
+
+enum lvts_tc_offset_enum {
+	TC_OFFSET_AP_CONTROLLER0 = 0,
+	TC_OFFSET_MFG_CONTROLLER0 = 0x100,
+	TC_OFFSET_MCU_CONTROLLER0 = 0x1000,
+	TC_OFFSET_MCU_CONTROLLER1 = 0x1100,
+	TC_OFFSET_MCU_CONTROLLER2 = 0x1200,
+};
+
+struct mtk_thermal_controller_regs {
+	u32 lvtsmonctl0_0;
+	u32 lvtsmonctl1_0;
+	u32 lvtsmonctl2_0;
+	u32 lvtsmonint_0;
+	u32 reserved1[5];
+	u32 lvtsh2nthre_0;
+	u32 lvtshthre_0;
+	u32 lvtscthre_0;
+	u32 lvtsoffseth_0;
+	u32 lvtsoffsetl_0;
+	u32 lvtsmsrctl0_0;
+	u32 lvtsmsrctl1_0;
+	u32 lvtstssel_0;
+	u32 reserved2[1];
+	u32 lvtscalscale_0;
+	u32 lvts_id_0;
+	u32 lvts_config_0;
+	u32 lvtsedata[4];
+	u32 reserved3[11];
+	u32 lvtsmsr[4];
+	u32 reserved4[4];
+	u32 lvtsrdata0_0;
+	u32 reserved5[3];
+	u32 lvtsprotctl_0;
+	u32 reserved6[2];
+	u32 lvtsprottc_0;
+	u32 reserved7[5];
+	u32 lvtsclken_0;
+	u32 reserved8[2];
+	u32 lvtsspare[2];
+	u32 reserved9[2];
+};
+check_member(mtk_thermal_controller_regs, lvtsmonint_0, 0x000C);
+check_member(mtk_thermal_controller_regs, lvtsh2nthre_0, 0x0024);
+check_member(mtk_thermal_controller_regs, lvtstssel_0, 0x0040);
+check_member(mtk_thermal_controller_regs, lvtscalscale_0, 0x0048);
+check_member(mtk_thermal_controller_regs, lvtsedata[3], 0x0060);
+check_member(mtk_thermal_controller_regs, lvtsmsr[0], 0x0090);
+check_member(mtk_thermal_controller_regs, lvtsmsr[3], 0x009C);
+check_member(mtk_thermal_controller_regs, lvtsrdata0_0, 0x00B0);
+check_member(mtk_thermal_controller_regs, lvtsprotctl_0, 0x00C0);
+check_member(mtk_thermal_controller_regs, lvtsprottc_0, 0x00CC);
+check_member(mtk_thermal_controller_regs, lvtsclken_0, 0x00E4);
+check_member(mtk_thermal_controller_regs, lvtsspare[0], 0x00F0);
+check_member(mtk_thermal_controller_regs, lvtsspare[1], 0x00F4);
+
+struct mtk_infracfg_regs {
+	u32 reserved1[968];
+	u32 mcu_rst_set;
+	u32 mcu_rst_clr;
+	u32 reserved2[10];
+	u32 ap_rst_set;
+	u32 ap_rst_clr;
+};
+check_member(mtk_infracfg_regs, mcu_rst_set, 0x0F20);
+check_member(mtk_infracfg_regs, mcu_rst_clr, 0x0F24);
+check_member(mtk_infracfg_regs, ap_rst_set, 0x0F50);
+check_member(mtk_infracfg_regs, ap_rst_clr, 0x0F54);
+
+ /* LVTS Thermal Controller Register Definition */
+
+static struct mtk_thermal_controller_regs *const
+	mtk_lvts_mcu_controller0 = (void *)(THERM_CTRL_BASE + TC_OFFSET_MCU_CONTROLLER0);
+static struct mtk_thermal_controller_regs *const
+	mtk_lvts_mcu_controller1 = (void *)(THERM_CTRL_BASE + TC_OFFSET_MCU_CONTROLLER1);
+static struct mtk_thermal_controller_regs *const
+	mtk_lvts_mcu_controller2 = (void *)(THERM_CTRL_BASE + TC_OFFSET_MCU_CONTROLLER2);
+static struct mtk_thermal_controller_regs *const
+	mtk_lvts_ap_controller0 = (void *)(THERM_CTRL_BASE + TC_OFFSET_AP_CONTROLLER0);
+static struct mtk_thermal_controller_regs *const
+	mtk_lvts_mfg_controller0 = (void *)(THERM_CTRL_BASE + TC_OFFSET_MFG_CONTROLLER0);
+
+static struct mtk_infracfg_regs *const mtk_infracfg = (void *)INFRACFG_BASE;
+
+#endif /* __SOC_MEDIATEK_MT8189_INCLUDE_SOC_THERMAL_INTERNAL_H__ */
diff --git a/src/soc/mediatek/mt8189/thermal.c b/src/soc/mediatek/mt8189/thermal.c
new file mode 100644
index 0000000000..0735cbf86c
--- /dev/null
+++ b/src/soc/mediatek/mt8189/thermal.c
@@ -0,0 +1,448 @@
+/* SPDX-License-Identifier: GPL-2.0-only OR MIT */
+
+/*
+ * This file is created based on MT8189 Functional Specification
+ * Chapter number: 9.13
+ */
+
+#include <assert.h>
+#include <delay.h>
+#include <soc/efuse.h>
+#include <soc/thermal.h>
+
+#define LVTS_DEVICE_WRITE_CONFIG	0xC103
+
+static uint32_t golden_temp;
+
+static u32 ts_edata[L_TS_LVTS_NUM];
+static u32 op_cali[LVTS_CONTROLLER_NUM];
+static u32 count_rc_now[L_TS_LVTS_NUM];
+
+/*
+ * module            LVTS Plan
+ *=====================================================
+ * MCU_BIG core0/1 LVTS1-0, LVTS1-1, LVTS1-2, LVTS1-3
+ * MCU_BIG core2/3 LVTS2-0, LVTS2-1, LVTS2-2, LVTS2-3
+ * MCU_LITTLE      LVTS3-0, LVTS3-1, LVTS3-2, LVTS3-3
+ * SOC-TOP,APU     LVTS4-0, LVTS4-1, LVTS4-2, LVTS4-3
+ * GPU             LVTS5-0, LVTS5-1
+ *
+ * ptp_therm_ctrl_AP  Base address: (+0x1031_5000), 0x1031_5100, 0x1031_5200
+ * ptp_therm_ctrl_MCU Base address: (+0x1031_6000), 0x1031_6100, 0x1031_6200, 0x1031_6300
+ */
+static const struct lvts_thermal_controller lvts_tscpu_g_tc[LVTS_CONTROLLER_NUM] = {
+	[LVTS_MCU_CONTROLLER0] = { /* MCU_BIG core0/1 */
+		.ts = {L_TS_LVTS1_0, L_TS_LVTS1_1, L_TS_LVTS1_2, L_TS_LVTS1_3},
+		.sensor_on_off = {SEN_ON, SEN_ON, SEN_ON, SEN_ON},
+		.ts_number = 4,
+		.reboot_temperature = 119000,
+		.dominator_ts_idx = 0,
+		.reboot_msr_sram_idx = 0,
+		.has_reboot_msr_sram = false,
+		.has_reboot_temp_sram = false,
+		.speed = {
+			.group_interval_delay = 0x0F6,
+			.period_unit = 0x001,
+			.filter_interval_delay = 0x001,
+			.sensor_interval_delay = 0x001
+		},
+		.regs = mtk_lvts_mcu_controller0,
+	},
+	[LVTS_MCU_CONTROLLER1] = { /* MCU_BIG core2/3 */
+		.ts = {L_TS_LVTS2_0, L_TS_LVTS2_1, L_TS_LVTS2_2, L_TS_LVTS2_3},
+		.sensor_on_off = {SEN_ON, SEN_ON, SEN_ON, SEN_ON},
+		.ts_number = 4,
+		.reboot_temperature = 119000,
+		.dominator_ts_idx = 0,
+		.reboot_msr_sram_idx = 0,
+		.has_reboot_msr_sram = false,
+		.has_reboot_temp_sram = false,
+		.speed = {
+			.group_interval_delay = 0x0F6,
+			.period_unit = 0x001,
+			.filter_interval_delay = 0x001,
+			.sensor_interval_delay = 0x001
+		},
+		.regs = mtk_lvts_mcu_controller1,
+	},
+	[LVTS_MCU_CONTROLLER2] = { /* MCU_LITTLE */
+		.ts = {L_TS_LVTS3_0, L_TS_LVTS3_1, L_TS_LVTS3_2, L_TS_LVTS3_3},
+		.sensor_on_off = {SEN_ON, SEN_ON, SEN_ON, SEN_ON},
+		.ts_number = 4,
+		.reboot_temperature = 119000,
+		.dominator_ts_idx = 0,
+		.reboot_msr_sram_idx = 0,
+		.has_reboot_msr_sram = false,
+		.has_reboot_temp_sram = false,
+		.speed = {
+			.group_interval_delay = 0x1C1,
+			.period_unit = 0x001,
+			.filter_interval_delay = 0x001,
+			.sensor_interval_delay = 0x001
+		},
+		.regs = mtk_lvts_mcu_controller2,
+	},
+	[LVTS_AP_CONTROLLER0] = { /* SOC-TOP, APU */
+		.ts = {L_TS_LVTS4_0, L_TS_LVTS4_1, L_TS_LVTS4_2, L_TS_LVTS4_3},
+		.sensor_on_off = {SEN_ON, SEN_ON, SEN_ON, SEN_ON},
+		.ts_number = 4,
+		.reboot_temperature = 119000,
+		.dominator_ts_idx = 0,
+		.reboot_msr_sram_idx = 0,
+		.has_reboot_msr_sram = false,
+		.has_reboot_temp_sram = false,
+		.speed = {
+			.group_interval_delay = 0x0D2,
+			.period_unit = 0x001,
+			.filter_interval_delay = 0x001,
+			.sensor_interval_delay = 0x001
+		},
+		.regs = mtk_lvts_ap_controller0,
+	},
+	[LVTS_MFG_CONTROLLER0] = { /* MFG */
+		.ts = {L_TS_LVTS5_0, L_TS_LVTS5_1},
+		.sensor_on_off = {SEN_ON, SEN_ON},
+		.ts_number = 2,
+		.reboot_temperature = 119000,
+		.dominator_ts_idx = 0,
+		.reboot_msr_sram_idx = 0,
+		.has_reboot_msr_sram = false,
+		.has_reboot_temp_sram = false,
+		.speed = {
+			.group_interval_delay = 0x08A,
+			.period_unit = 0x001,
+			.filter_interval_delay = 0x001,
+			.sensor_interval_delay = 0x001
+		},
+		.regs = mtk_lvts_mfg_controller0,
+	},
+};
+
+const struct lvts_thermal_controller *lvts_get_controller(int tc_num)
+{
+	assert(tc_num < LVTS_CONTROLLER_NUM);
+
+	return &lvts_tscpu_g_tc[tc_num];
+}
+
+void lvts_clock_gate_disable(void)
+{
+	write32(&mtk_infracfg_ao->infracfg_ao_module_cg_0_clr, THERM_CG);
+}
+
+void lvts_tscpu_reset_thermal(void)
+{
+	/* Reset AP thermal control */
+	write32(&mtk_infracfg->ap_rst_set, BIT(23));
+	write32(&mtk_infracfg->ap_rst_clr, BIT(23));
+
+	/* Reset MCU thermal control */
+	write32(&mtk_infracfg->mcu_rst_set, BIT(12));
+	write32(&mtk_infracfg->mcu_rst_clr, BIT(12));
+}
+
+void lvts_thermal_cal_prepare(void)
+{
+	u32 temp[LVTS_ADDRESS_INDEX_NUM];
+	int i;
+	bool efuse_calibrated = false;
+	enum lvts_sensor sensor_groups[] = {L_TS_LVTS1_0, L_TS_LVTS2_0,
+					    L_TS_LVTS3_0, L_TS_LVTS4_0,
+					    L_TS_LVTS5_0};
+	const size_t sensor_group_size = 4;
+	int idx;
+
+	for (i = 0; i < ARRAY_SIZE(temp); i++) {
+		temp[i] = read32(&mtk_efuse->lvts_reg[i]);
+		printk(BIOS_INFO, "[lvts_cali] %d: 0x%x\n", i, temp[i]);
+
+		if (temp[i] != 0)
+			efuse_calibrated = true;
+	}
+
+	/* 0x11F1_01A4,LVTS1 */
+	golden_temp = (temp[0] & GENMASK(7, 0));
+	idx = 0;
+
+	for (i = 0; i < ARRAY_SIZE(sensor_groups); i++) {
+		idx++;
+		for (int j = 0; j < sensor_group_size; j++) {
+			enum lvts_sensor sensor = sensor_groups[i] + j;
+			if (sensor >= L_TS_LVTS_NUM)
+				break;
+			ts_edata[sensor] = temp[idx++] & GENMASK(23, 0);
+		}
+	}
+
+	/* 0x11F1_01A4,LVTS1 */
+	op_cali[LVTS_MCU_CONTROLLER0] = ((temp[0] & GENMASK(31, 8)) >> 8);
+	/* 0x11F1_01B8,LVTS2 */
+	op_cali[LVTS_MCU_CONTROLLER1] = (temp[5] & GENMASK(23, 0));
+	/* 0x11F1_01CC,LVTS3 */
+	op_cali[LVTS_MCU_CONTROLLER2] = (temp[10] & GENMASK(23, 0));
+
+	/* 0x11F1_01E0,LVTS4 */
+	op_cali[LVTS_AP_CONTROLLER0] = (temp[15] & GENMASK(23, 0));
+
+	/* 0x11F1_01F4,LVTS5 */
+	op_cali[LVTS_MFG_CONTROLLER0] = (temp[20] & GENMASK(23, 0));
+
+	if (!efuse_calibrated) {
+		/* It means all efuse data are equal to 0 */
+		printk(BIOS_ERR,
+		       "[lvts_cal] The efuses of this sample are all zero, "
+		       "meaning it is not calibrated, fake!!!\n");
+		golden_temp = DEFAULT_EFUSE_GOLDEN_TEMP;
+		for (i = 0; i < L_TS_LVTS_NUM; i++)
+			ts_edata[i] = DEFAULT_EFUSE_COUNT;
+
+		for (i = 0; i < LVTS_CONTROLLER_NUM; i++)
+			op_cali[i] = DEFAULT_EFUSE_COUNT_RC;
+	}
+
+	printk(BIOS_INFO, "[lvts_cal] golden_temp = %d mdegC\n", golden_temp);
+
+	printk(BIOS_INFO, "[lvts_cal] num:ts_edata:op_cali ");
+	for (i = 0; i < ARRAY_SIZE(ts_edata); i++) {
+		if (i < ARRAY_SIZE(op_cali))
+			printk(BIOS_INFO, "%d:%d:%d ", i, ts_edata[i], op_cali[i]);
+		else
+			printk(BIOS_INFO, "%d:%d ", i, ts_edata[i]);
+	}
+	printk(BIOS_INFO, "\n");
+
+	write32(&lvts_tscpu_g_tc[0].regs->lvtsspare[1], golden_temp);
+}
+
+void lvts_device_identification(void)
+{
+	u32 dev_id, data;
+	int i;
+
+	printk(BIOS_INFO, "===== %s begin ======\n", __func__);
+	for (i = 0; i < LVTS_CONTROLLER_NUM; i++) {
+		const struct lvts_thermal_controller *tc = lvts_get_controller(i);
+		/* Enable LVTS_CTRL Clock */
+		write32(&tc->regs->lvtsclken_0, 0x00000001);
+
+		/* Reset All Devices */
+		lvts_write_device(LVTS_DEVICE_WRITE_CONFIG, 0xFF, 0xFF, i);
+
+		/*  Read back Dev_ID with Update */
+		lvts_write_device(0xC502, 0xFC, 0x55, i);
+
+		dev_id = 0x81 + i;
+
+		if (!retry(LVTS_READ_ID_RETRY_CNT,
+			   (data = read32(&tc->regs->lvts_id_0) & GENMASK(7, 0)) == dev_id,
+			   udelay(LVTS_READ_ID_DELAY_US)))
+			printk(BIOS_ERR,
+			       "LVTS_TC_%d read timeout, addr:0x%lx, Device ID should be 0x%x,"
+			       " but 0x%x\n",
+			       i, (uintptr_t)(&tc->regs->lvts_id_0), dev_id, data);
+	}
+}
+
+void lvts_device_enable_init_all_devices(void)
+{
+	int i;
+
+	printk(BIOS_INFO, "===== %s begin ======\n", __func__);
+
+	for (i = 0; i < LVTS_CONTROLLER_NUM; i++) {
+		/*  Stop Counting (RG_TSFM_ST=0) */
+		lvts_write_device(LVTS_DEVICE_WRITE_CONFIG, 0x03, 0x00, i);
+		/* RG_TSFM_LPDLY[1:0]=2' 10 */
+		lvts_write_device(LVTS_DEVICE_WRITE_CONFIG, 0x07, 0xA6, i);
+		/* Set LVTS device counting window 20us */
+		/* Counting Window */
+		lvts_write_device(LVTS_DEVICE_WRITE_CONFIG, 0x05, 0x00, i);
+		lvts_write_device(LVTS_DEVICE_WRITE_CONFIG, 0x04, 0x20, i);
+		/* TSV2F_CHOP_CKSEL & TSV2F_EN */
+		lvts_write_device(LVTS_DEVICE_WRITE_CONFIG, 0x0A, 0x8C, i);
+		/* TSBG_DEM_CKSEL * TSBG_CHOP_EN */
+		lvts_write_device(LVTS_DEVICE_WRITE_CONFIG, 0x0C, 0xFC, i);
+		/* Set TS_RSV */
+		lvts_write_device(LVTS_DEVICE_WRITE_CONFIG, 0x09, 0x8D, i);
+		/* Set TS_CHOP control */
+		lvts_write_device(LVTS_DEVICE_WRITE_CONFIG, 0x08, 0xF1, i);
+	}
+}
+
+static u32 lvts_read_device(u32 config, u32 dev_reg_idx, int tc_num)
+{
+	u32 data;
+	u32 *lvts_config_reg = &lvts_tscpu_g_tc[tc_num].regs->lvts_config_0;
+
+	config |= (dev_reg_idx & 0xFF) << 8;
+
+	write32(lvts_config_reg, config);
+
+	/* Wait 2us + 3us buffer */
+	udelay(5);
+
+	if (!retry(CHECK_DEVICE_ACCESS_RETRY_CNT,
+		   !(read32(lvts_config_reg) & DEVICE_ACCESS_START_BIT),
+		   udelay(2)))
+		printk(BIOS_ERR,
+		       "read err: DEVICE_ACCESS_START_BIT is not ready, "
+		       "ASIF transaction not finished, reg0x%x\n",
+		       dev_reg_idx);
+
+	data = read32(&lvts_tscpu_g_tc[tc_num].regs->lvtsrdata0_0);
+
+	return data;
+}
+
+static void lvts_device_check_counting_status(const struct lvts_thermal_controller *tc)
+{
+	/*
+	 * Check this when LVTS device is counting for a temperature or
+	 * a RC (Resistor-Capacitor Calibration) now
+	 */
+
+	if (!retry(CHECK_DEVICE_ACCESS_RETRY_CNT,
+		   !(read32(&tc->regs->lvts_config_0) & DEVICE_SENSING_STATUS),
+		   udelay(2)))
+		printk(BIOS_ERR, "Error: DEVICE_SENSING_STATUS is not ready\n");
+}
+
+static void lvts_device_read_count_rc_n(void)
+{
+	/* Perform RC (Resistor-Capacitor Calibration) and read current count (count_rc_n) */
+	int i, j, s_index;
+	u32 data;
+
+	/* Set LVTS MANUAL-RCK operation */
+	for (i = 0; i < LVTS_CONTROLLER_NUM; i++)
+		lvts_write_device(LVTS_DEVICE_WRITE_CONFIG, 0x0E, 0x00, i);
+
+	for (i = 0; i < LVTS_CONTROLLER_NUM; i++) {
+		const struct lvts_thermal_controller *tc = lvts_get_controller(i);
+
+		/* Set LVTS Manual-RCK operation */
+		lvts_write_device(LVTS_DEVICE_WRITE_CONFIG, 0x0E, 0x00, i);
+
+		for (j = 0; j < tc->ts_number; j++) {
+			if (tc->sensor_on_off[j] == SEN_OFF)
+				continue;
+
+			s_index = tc->ts[j];
+
+			/* Select sensor-N with RCK */
+			lvts_write_device(LVTS_DEVICE_WRITE_CONFIG, 0x0D, j, i);
+			/* Set Device Low-Power Single mode */
+			lvts_write_device(LVTS_DEVICE_WRITE_CONFIG, 0x06, 0x78, i);
+			/* Set TS_EN and DEV_EN */
+			lvts_write_device(LVTS_DEVICE_WRITE_CONFIG, 0x08, 0xF5, i);
+			/* Toggle VCO_RST */
+			lvts_write_device(LVTS_DEVICE_WRITE_CONFIG, 0x08, 0xFD, i);
+			/* Set TS_EN and DEV_EN */
+			lvts_write_device(LVTS_DEVICE_WRITE_CONFIG, 0x08, 0xF5, i);
+			/* wait 10us */
+			udelay(10);
+			lvts_write_device(LVTS_DEVICE_WRITE_CONFIG, 0x03, 0x02, i);
+			/* polling counting status */
+			lvts_device_check_counting_status(tc);
+			/* disable TS_EN */
+			lvts_write_device(LVTS_DEVICE_WRITE_CONFIG, 0x08, 0xF1, i);
+			/* wait 40us at sensor0 */
+			/* 2us is margin for different IC */
+			if (j == 0)
+				udelay(42);
+
+			/* Get RCK count data (sensor-N) */
+			data = lvts_read_device(0xC1020000, 0x00, i);
+			/* wait 2us + 3us buffer */
+			udelay(5);
+
+			/* Get RCK value from LSB[23:0] */
+			count_rc_now[s_index] = data & GENMASK(23, 0);
+
+			/*
+			 * Recover Setting for Normal Access on
+			 * temperature fetch
+			 */
+			/* Select Sensor-N without RCK */
+			lvts_write_device(LVTS_DEVICE_WRITE_CONFIG, 0x0D, (0x10 | j), i);
+		}
+	}
+
+	printk(BIOS_INFO, "[COUNT_RC_NOW] ");
+	for (i = 0; i < L_TS_LVTS_NUM; i++)
+		printk(BIOS_INFO, "%d:%d ", i, count_rc_now[i]);
+
+	printk(BIOS_INFO, "\n");
+}
+
+void lvts_efuse_setting(void)
+{
+	int i, j, s_index;
+	uint32_t efuse_data;
+
+	printk(BIOS_INFO, "===== %s begin ======\n", __func__);
+
+	lvts_device_read_count_rc_n();
+
+	for (i = 0; i < LVTS_CONTROLLER_NUM; i++) {
+		const struct lvts_thermal_controller *tc = lvts_get_controller(i);
+
+		assert(tc->ts_number <= ARRAY_SIZE(tc->regs->lvtsedata));
+		for (j = 0; j < tc->ts_number; j++) {
+			if (tc->sensor_on_off[j] == SEN_OFF)
+				continue;
+
+			s_index = tc->ts[j];
+
+			efuse_data = ((u64)count_rc_now[s_index] * ts_edata[s_index]) >> 14;
+
+			write32(&tc->regs->lvtsedata[j], efuse_data);
+			printk(BIOS_INFO,
+			       "efuse LVTSEDATA[%d]_%d %#x\n", j, i,
+			       read32(&tc->regs->lvtsedata[j]));
+		}
+	}
+}
+
+void lvts_tscpu_thermal_read_tc_temp(const struct lvts_thermal_controller *tc, int order)
+{
+	enum lvts_sensor ts_name = tc->ts[order];
+	int temperature;
+	assert(order < ARRAY_SIZE(tc->regs->lvtsmsr));
+	temperature = lvts_read_tc_raw_and_temp(&tc->regs->lvtsmsr[order],
+						ts_name,
+						golden_temp);
+
+	printk(BIOS_INFO,
+	       "%s order %d ts_name %d temp %d mdegC\n",
+	       __func__, order, ts_name, temperature);
+}
+
+void lvts_set_device_single_mode(int tc_num)
+{
+	lvts_write_device(LVTS_DEVICE_WRITE_CONFIG, 0x06, 0xF8, tc_num);
+}
+
+uint16_t lvts_temp_to_raw(int temp_mc, enum lvts_sensor ts_name)
+{
+	/*
+	 * MSR_RAW = ((temp_mc - GOLDEN_TEMP/2 - b) * 16384) / a
+	 * a = -250.46
+	 * b =  250.46
+	 */
+	uint32_t msr_raw;
+	int64_t temp1;
+
+	temp1 = (int64_t)golden_temp * 500 - LVTS_COEFF_A - temp_mc;
+	assert(temp1 >= 0);
+	msr_raw = ((temp1 << 14) / (-1 * LVTS_COEFF_A)) & 0xFFFF;
+
+	printk(BIOS_INFO, "%s msr_raw = %u, temp_mc = %d\n", __func__, msr_raw, temp_mc);
+	return msr_raw;
+}
+
+void thermal_init(void)
+{
+	lvts_thermal_init();
+	thermal_sram_init();
+}
diff --git a/src/soc/mediatek/mt8189/thermal_sram.c b/src/soc/mediatek/mt8189/thermal_sram.c
new file mode 100644
index 0000000000..cdf13192b2
--- /dev/null
+++ b/src/soc/mediatek/mt8189/thermal_sram.c
@@ -0,0 +1,9 @@
+/* SPDX-License-Identifier: GPL-2.0-only OR MIT */
+
+#include <soc/thermal.h>
+
+void thermal_sram_init(void)
+{
+	thermal_cls_sram();
+	thermal_stat_cls_sram();
+}

From edaa67d0c9f25bfd7518397d5ad31b11c090ab6d Mon Sep 17 00:00:00 2001
From: Raymond Sun <raymond.sun@mediatek.corp-partner.google.com>
Date: Wed, 4 Dec 2024 20:13:47 +0800
Subject: [PATCH 1612/3886] mb/google/skywalker: Add thermal init flow in
 romstage

BUG=b:379008996
BRANCH=none
TEST=build pass, thermal init log:
[INFO ]  ===== lvts_thermal_init begin ======
[INFO ]  thermal_init: thermal initialized

Signed-off-by: Raymond Sun <raymond.sun@mediatek.corp-partner.google.com>
Change-Id: Id57f73206135f814f44b34290c5f2624ea56e1df
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88442
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/google/skywalker/romstage.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/src/mainboard/google/skywalker/romstage.c b/src/mainboard/google/skywalker/romstage.c
index f8643061bf..9aa89a2730 100644
--- a/src/mainboard/google/skywalker/romstage.c
+++ b/src/mainboard/google/skywalker/romstage.c
@@ -10,6 +10,7 @@
 #include <soc/pmif.h>
 #include <soc/regulator.h>
 #include <soc/rtc.h>
+#include <soc/thermal.h>
 
 static void raise_little_cpu_freq(void)
 {
@@ -29,4 +30,5 @@ void platform_romstage_main(void)
 	rtc_boot();
 	dvfs_init();
 	mtk_dram_init();
+	thermal_init();
 }

From d1c096a5b91855243b455e0eae5fa106930ed3db Mon Sep 17 00:00:00 2001
From: Vince Liu <vince-wl.liu@mediatek.corp-partner.google.com>
Date: Fri, 18 Jul 2025 14:14:18 +0800
Subject: [PATCH 1613/3886] src/soc/mt8196: Correct systimer register offset

A recent datasheet review finds that the previously used offset for
the `cnttval` register is incorrect. Since the relevant bits used by
`clear_timer()` have default values of 0, the functionality is not
affected before this fix.

BUG=b:430211678
BRANCH=rauru
TEST=check the timestamp order of depthcharge is correct in `cbmem`
  16:finished LZMA decompress (ignore for x86)         895,082 (526)
1000:depthcharge start                                 941,621 (46,539)
1002:RO vboot init                                     942,644 (1,023)
1020:vboot select&load kernel                          942,645 (1)
1030:finished EC verification                          980,005 (37,360)
1060:finished AuxFW Sync                               997,302 (17,297)
1040:finished storage device initialization            1,025,910 (28,608)
1050:finished reading kernel from disk                 2,174,931 (1,149,021)
1100:finished vboot kernel verification                2,229,874 (54,943)
1102:starting kernel decompression/relocation          2,249,121 (19,247)
1101:jumping to kernel                                 2,284,317 (35,196)

Total Time: 2,020,762

Change-Id: I018d81de79d6896a31972f925d5a26f41cf942a0
Signed-off-by: Vince Liu <vince-wl.liu@mediatek.corp-partner.google.com>
Signed-off-by: Zhanzhan Ge <zhanzhan.ge@mediatek.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88480
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/soc/mediatek/mt8196/include/soc/timer.h | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/src/soc/mediatek/mt8196/include/soc/timer.h b/src/soc/mediatek/mt8196/include/soc/timer.h
index f6841fc250..fbc18a9b69 100644
--- a/src/soc/mediatek/mt8196/include/soc/timer.h
+++ b/src/soc/mediatek/mt8196/include/soc/timer.h
@@ -31,7 +31,7 @@ struct systimer {
 	u32 reserved;
 	u32 cntcv_l;
 	u32 cntcv_h;
-	u32 reserved1[0x30];
+	u32 reserved1[12];
 	struct {
 		u32 con;
 		u32 val;
@@ -40,6 +40,8 @@ struct systimer {
 
 check_member(systimer, cntcr, 0x0);
 check_member(systimer, cntcv_l, 0x0008);
-check_member(systimer, cntcv_h, 0x000c);
+check_member(systimer, cntcv_h, 0x000C);
+check_member(systimer, cnttval[0].con, 0x0040);
+check_member(systimer, cnttval[0].val, 0x0044);
 
 #endif

From d898653b0e0cd1c285dada910176606aa06fea0e Mon Sep 17 00:00:00 2001
From: Vince Liu <vince-wl.liu@mediatek.corp-partner.google.com>
Date: Fri, 11 Jul 2025 15:53:18 +0800
Subject: [PATCH 1614/3886] soc/meidatek/mt8196: Extract common timer code for
 reuse

To promote code reuse and maintainability, move mt8196/timer_prepare.c
to timer_prepare_v2.c. The original timer_prepare.c is renamed to
timer_prepare_v1.c. Also use `mtk_systimer->cntcr` instead of
`SYSTIMER_BASE` for consistency.

BUG=b:379008996
BRANCH=none
TEST=build passed.

Signed-off-by: Vince Liu <vince-wl.liu@mediatek.corp-partner.google.com>
Change-Id: Iab617e7a8bfedb81bcf673edd94d24870df7f751
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88467
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
---
 .../mediatek/common/include/soc/timer_reg.h   | 39 +++++++++++++++++++
 .../mediatek/common/include/soc/timer_v2.h    |  2 +
 src/soc/mediatek/common/timer_prepare.c       | 11 ------
 src/soc/mediatek/common/timer_prepare_v1.c    | 11 ++++++
 src/soc/mediatek/common/timer_prepare_v2.c    | 24 ++++++++++++
 src/soc/mediatek/mt8186/Makefile.mk           |  2 +-
 src/soc/mediatek/mt8188/Makefile.mk           |  2 +-
 src/soc/mediatek/mt8189/Makefile.mk           |  2 +-
 src/soc/mediatek/mt8195/Makefile.mk           |  2 +-
 src/soc/mediatek/mt8196/Makefile.mk           |  2 +-
 src/soc/mediatek/mt8196/include/soc/timer.h   | 29 +-------------
 src/soc/mediatek/mt8196/timer.c               |  8 ++++
 src/soc/mediatek/mt8196/timer_prepare.c       | 34 ----------------
 13 files changed, 90 insertions(+), 78 deletions(-)
 create mode 100644 src/soc/mediatek/common/include/soc/timer_reg.h
 delete mode 100644 src/soc/mediatek/common/timer_prepare.c
 create mode 100644 src/soc/mediatek/common/timer_prepare_v1.c
 create mode 100644 src/soc/mediatek/common/timer_prepare_v2.c
 delete mode 100644 src/soc/mediatek/mt8196/timer_prepare.c

diff --git a/src/soc/mediatek/common/include/soc/timer_reg.h b/src/soc/mediatek/common/include/soc/timer_reg.h
new file mode 100644
index 0000000000..df5d83272d
--- /dev/null
+++ b/src/soc/mediatek/common/include/soc/timer_reg.h
@@ -0,0 +1,39 @@
+/* SPDX-License-Identifier: GPL-2.0-only OR MIT */
+
+#ifndef SOC_MEDIATEK_COMMON_TIMER_REG_H
+#define SOC_MEDIATEK_COMMON_TIMER_REG_H
+
+#include <device/mmio.h>
+#include <soc/addressmap.h>
+
+#define SYST_CON_EN			BIT(0)
+#define SYST_CON_IRQ_CLR		BIT(4)
+#define REV_CLR_EN			0x3
+#define COMP_FEATURE_CLR		0
+#define SYSTIMER_CNT			8
+#define SYST_CON_CLR			0
+
+struct systimer {
+	u32 cntcr;
+	u32 reserved;
+	u32 cntcv_l;
+	u32 cntcv_h;
+	u32 reserved1[12];
+	struct {
+		u32 con;
+		u32 val;
+	} cnttval[SYSTIMER_CNT];
+};
+check_member(systimer, cntcr, 0x0);
+check_member(systimer, cntcv_l, 0x0008);
+check_member(systimer, cntcv_h, 0x000C);
+check_member(systimer, cnttval[0].con, 0x0040);
+check_member(systimer, cnttval[0].val, 0x0044);
+
+static struct systimer *mtk_systimer = (void *)SYSTIMER_BASE;
+
+DEFINE_BITFIELD(COMP_FEATURE, 12, 10)
+DEFINE_BITFIELD(REV_SET, 18, 17)
+DEFINE_BITFIELD(SYST_CON, 4, 0)
+
+#endif
diff --git a/src/soc/mediatek/common/include/soc/timer_v2.h b/src/soc/mediatek/common/include/soc/timer_v2.h
index d4f854c605..c13fa7c325 100644
--- a/src/soc/mediatek/common/include/soc/timer_v2.h
+++ b/src/soc/mediatek/common/include/soc/timer_v2.h
@@ -43,4 +43,6 @@ DEFINE_BITFIELD(GPT6_CON_MODE6, 6, 5)
 DEFINE_BITFIELD(GPT6_CLK_CLKDIV6, 3, 0)
 DEFINE_BITFIELD(GPT6_CLK_CLK6, 13, 10)
 
+void timer_set_compensation(void);
+
 #endif
diff --git a/src/soc/mediatek/common/timer_prepare.c b/src/soc/mediatek/common/timer_prepare.c
deleted file mode 100644
index 3fb4be7f2d..0000000000
--- a/src/soc/mediatek/common/timer_prepare.c
+++ /dev/null
@@ -1,11 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <device/mmio.h>
-#include <soc/addressmap.h>
-#include <soc/timer.h>
-
-void timer_prepare(void)
-{
-	clrbits32((void *)SYSTIMER_BASE, COMP_FEATURE_MASK);
-	setbits32((void *)SYSTIMER_BASE, COMP_25_MASK);
-}
diff --git a/src/soc/mediatek/common/timer_prepare_v1.c b/src/soc/mediatek/common/timer_prepare_v1.c
new file mode 100644
index 0000000000..5a49b1b4cf
--- /dev/null
+++ b/src/soc/mediatek/common/timer_prepare_v1.c
@@ -0,0 +1,11 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <device/mmio.h>
+#include <soc/timer.h>
+#include <soc/timer_reg.h>
+
+void timer_prepare(void)
+{
+	clrbits32(&mtk_systimer->cntcr, COMP_FEATURE_MASK);
+	setbits32(&mtk_systimer->cntcr, COMP_25_MASK);
+}
diff --git a/src/soc/mediatek/common/timer_prepare_v2.c b/src/soc/mediatek/common/timer_prepare_v2.c
new file mode 100644
index 0000000000..8f62888983
--- /dev/null
+++ b/src/soc/mediatek/common/timer_prepare_v2.c
@@ -0,0 +1,24 @@
+/* SPDX-License-Identifier: GPL-2.0-only OR MIT */
+
+#include <device/mmio.h>
+#include <soc/timer.h>
+
+static void clear_systimer(void)
+{
+	int id;
+
+	for (id = 0; id < SYSTIMER_CNT; id++) {
+		u32 *cnttval_con = &mtk_systimer->cnttval[id].con;
+		WRITE32_BITFIELDS(cnttval_con, SYST_CON, SYST_CON_EN);
+		SET32_BITFIELDS(cnttval_con, SYST_CON, SYST_CON_IRQ_CLR);
+		WRITE32_BITFIELDS(cnttval_con, SYST_CON, SYST_CON_CLR);
+	}
+
+	SET32_BITFIELDS(&mtk_systimer->cntcr, REV_SET, REV_CLR_EN);
+}
+
+void timer_prepare(void)
+{
+	timer_set_compensation();
+	clear_systimer();
+}
diff --git a/src/soc/mediatek/mt8186/Makefile.mk b/src/soc/mediatek/mt8186/Makefile.mk
index 4ed3db42fc..e3592fc418 100644
--- a/src/soc/mediatek/mt8186/Makefile.mk
+++ b/src/soc/mediatek/mt8186/Makefile.mk
@@ -8,7 +8,7 @@ all-y += ../common/gpio_eint_v1.c ../common/gpio.c ../common/gpio_op.c  gpio.c
 all-y += ../common/i2c.c ../common/i2c_common.c i2c.c
 all-y += ../common/pll.c pll.c
 all-$(CONFIG_SPI_FLASH) += ../common/spi.c spi.c
-all-y += ../common/timer.c ../common/timer_prepare.c
+all-y += ../common/timer.c ../common/timer_prepare_v1.c
 all-y += ../common/uart.c
 
 bootblock-y += bootblock.c
diff --git a/src/soc/mediatek/mt8188/Makefile.mk b/src/soc/mediatek/mt8188/Makefile.mk
index 33b41835fb..0469738ff4 100644
--- a/src/soc/mediatek/mt8188/Makefile.mk
+++ b/src/soc/mediatek/mt8188/Makefile.mk
@@ -6,7 +6,7 @@ all-y += ../common/gpio_eint_v1.c ../common/gpio.c ../common/gpio_op.c gpio.c
 all-y += ../common/i2c.c ../common/i2c_common.c i2c.c
 all-y += ../common/pll.c pll.c
 all-$(CONFIG_SPI_FLASH) += ../common/spi.c spi.c
-all-y += timer.c ../common/timer_prepare.c
+all-y += timer.c ../common/timer_prepare_v1.c
 all-y += ../common/uart.c
 
 bootblock-y += ../common/bootblock.c bootblock.c
diff --git a/src/soc/mediatek/mt8189/Makefile.mk b/src/soc/mediatek/mt8189/Makefile.mk
index cf44747310..7c114e8a6d 100644
--- a/src/soc/mediatek/mt8189/Makefile.mk
+++ b/src/soc/mediatek/mt8189/Makefile.mk
@@ -7,7 +7,7 @@ all-y += ../common/gpio.c ../common/gpio_op.c ../common/gpio_eint_v2.c gpio.c gp
 all-y += ../common/i2c.c ../common/i2c_common.c i2c.c
 all-y += ../common/pll.c pll.c
 all-$(CONFIG_SPI_FLASH) += ../common/spi.c spi.c
-all-y += ../common/timer_prepare.c timer.c
+all-y += ../common/timer_prepare_v1.c timer.c
 all-y += ../common/uart.c
 
 bootblock-y += ../common/bootblock.c bootblock.c
diff --git a/src/soc/mediatek/mt8195/Makefile.mk b/src/soc/mediatek/mt8195/Makefile.mk
index bcbeb128db..35c6c63385 100644
--- a/src/soc/mediatek/mt8195/Makefile.mk
+++ b/src/soc/mediatek/mt8195/Makefile.mk
@@ -6,7 +6,7 @@ all-y += ../common/flash_controller.c
 all-y += ../common/gpio_eint_v1.c ../common/gpio.c ../common/gpio_op.c gpio.c
 all-y += ../common/i2c.c ../common/i2c_common.c i2c.c
 all-$(CONFIG_SPI_FLASH) += ../common/spi.c spi.c
-all-y += ../common/timer.c ../common/timer_prepare.c
+all-y += ../common/timer.c ../common/timer_prepare_v1.c
 all-y += ../common/uart.c
 
 bootblock-y += bootblock.c
diff --git a/src/soc/mediatek/mt8196/Makefile.mk b/src/soc/mediatek/mt8196/Makefile.mk
index 762dcb17cb..b6cefb37f1 100644
--- a/src/soc/mediatek/mt8196/Makefile.mk
+++ b/src/soc/mediatek/mt8196/Makefile.mk
@@ -8,7 +8,7 @@ all-y += ../common/gpio_eint_v2.c gpio_eint.c
 all-y += ../common/i2c.c ../common/i2c_common.c i2c.c
 all-y += ../common/pll.c pll.c
 all-$(CONFIG_SPI_FLASH) += ../common/spi.c spi.c
-all-y += timer.c timer_prepare.c
+all-y += ../common/timer_prepare_v2.c timer.c
 all-y += ../common/uart.c
 
 bootblock-y += booker.c
diff --git a/src/soc/mediatek/mt8196/include/soc/timer.h b/src/soc/mediatek/mt8196/include/soc/timer.h
index fbc18a9b69..6fffdc8725 100644
--- a/src/soc/mediatek/mt8196/include/soc/timer.h
+++ b/src/soc/mediatek/mt8196/include/soc/timer.h
@@ -8,40 +8,13 @@
 #ifndef SOC_MEDIATEK_MT8196_TIMER_H
 #define SOC_MEDIATEK_MT8196_TIMER_H
 
+#include <soc/timer_reg.h>
 #include <soc/timer_v2.h>
-#include <stdint.h>
 
-DEFINE_BITFIELD(COMP_FEATURE, 12, 10)
 DEFINE_BITFIELD(COMP_FEATURE_TIE, 4, 3)
-DEFINE_BITFIELD(REV_SET, 18, 17)
-DEFINE_BITFIELD(SYST_CON, 4, 0)
 
-#define SYST_CON_EN			BIT(0)
-#define SYST_CON_IRQ_CLR		BIT(4)
-#define REV_CLR_EN			0x3
 #define COMP_FEATURE_20_EN		0x2
 #define COMP_FEATURE_TIE_EN		0x1
-#define COMP_FEATURE_CLR                0
 #define COMP_FEATURE_TIE_CLR		0
-#define SYSTIMER_CNT			8
-#define SYST_CON_CLR			0
-
-struct systimer {
-	u32 cntcr;
-	u32 reserved;
-	u32 cntcv_l;
-	u32 cntcv_h;
-	u32 reserved1[12];
-	struct {
-		u32 con;
-		u32 val;
-	} cnttval[SYSTIMER_CNT];
-};
-
-check_member(systimer, cntcr, 0x0);
-check_member(systimer, cntcv_l, 0x0008);
-check_member(systimer, cntcv_h, 0x000C);
-check_member(systimer, cnttval[0].con, 0x0040);
-check_member(systimer, cnttval[0].val, 0x0044);
 
 #endif
diff --git a/src/soc/mediatek/mt8196/timer.c b/src/soc/mediatek/mt8196/timer.c
index 5db5c4ac2f..a7f085997e 100644
--- a/src/soc/mediatek/mt8196/timer.c
+++ b/src/soc/mediatek/mt8196/timer.c
@@ -3,8 +3,16 @@
 #include <arch/lib_helpers.h>
 #include <commonlib/helpers.h>
 #include <delay.h>
+#include <device/mmio.h>
 #include <soc/timer.h>
 
+void timer_set_compensation(void)
+{
+	SET32_BITFIELDS(&mtk_systimer->cntcr,
+			COMP_FEATURE, COMP_FEATURE_CLR | COMP_FEATURE_20_EN,
+			COMP_FEATURE_TIE, COMP_FEATURE_TIE_CLR | COMP_FEATURE_TIE_EN);
+}
+
 void init_timer(void)
 {
 	timer_prepare();
diff --git a/src/soc/mediatek/mt8196/timer_prepare.c b/src/soc/mediatek/mt8196/timer_prepare.c
deleted file mode 100644
index 08496e83d8..0000000000
--- a/src/soc/mediatek/mt8196/timer_prepare.c
+++ /dev/null
@@ -1,34 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-/*
- * This file is created based on MT8196 Functional Specification
- * Chapter number: 1.2 2.2
- */
-
-#include <device/mmio.h>
-#include <soc/addressmap.h>
-#include <soc/timer.h>
-
-static void clear_systimer(struct systimer *const mtk_systimer)
-{
-	unsigned int id = 0;
-
-	for (id = 0; id < SYSTIMER_CNT; id++) {
-		u32 *cnttval_con = &mtk_systimer->cnttval[id].con;
-		WRITE32_BITFIELDS(cnttval_con, SYST_CON, SYST_CON_EN);
-		SET32_BITFIELDS(cnttval_con, SYST_CON, SYST_CON_IRQ_CLR);
-		WRITE32_BITFIELDS(cnttval_con, SYST_CON, SYST_CON_CLR);
-	}
-
-	SET32_BITFIELDS(&mtk_systimer->cntcr, REV_SET, REV_CLR_EN);
-}
-
-void timer_prepare(void)
-{
-	struct systimer *mtk_systimer = (void *)SYSTIMER_BASE;
-
-	SET32_BITFIELDS(&mtk_systimer->cntcr,
-			COMP_FEATURE, COMP_FEATURE_CLR | COMP_FEATURE_20_EN,
-			COMP_FEATURE_TIE, COMP_FEATURE_TIE_CLR | COMP_FEATURE_TIE_EN);
-	clear_systimer(mtk_systimer);
-}

From 4d3def7514e0c95532fc38b95447d7c8899934ca Mon Sep 17 00:00:00 2001
From: Vince Liu <vince-wl.liu@mediatek.corp-partner.google.com>
Date: Thu, 17 Jul 2025 17:36:06 +0800
Subject: [PATCH 1615/3886] soc/mediatek/mt8189: Fix timer reset in BL31 by
 using time_prepare_v2

After reboot, the system does not need to serve pending IRQ from
systimer. Therefore, clear systimer IRQ pending bits in init_timer().
For that to work, the systimer compensation version 2.5 needs to be
enabled. Otherwise, inaccurate timestamps may occur after BL31, for
example in depthcharge. As the solution has already been implemented
in time_prepare_v2, mt8189 can adopt this version to fix the issue.

Also remove unnecessary headers in timer.c.

BUG=b:430211678
BRANCH=none
TEST=check the depthcharge timstamp in `cbmem` is correct.
 554:finished TPM enable update                        399,533 (12,059)
  90:starting to load payload                          399,541 (8)
  15:starting LZMA decompress (ignore for x86)         410,775 (11,234)
  16:finished LZMA decompress (ignore for x86)         465,472 (54,697)
  99:selfboot jump                                     487,643 (22,171)
  15:starting LZMA decompress (ignore for x86)         490,591 (2,948)
  16:finished LZMA decompress (ignore for x86)         502,153 (11,562)
  15:starting LZMA decompress (ignore for x86)         502,210 (57)
  16:finished LZMA decompress (ignore for x86)         504,510 (2,300)
1000:depthcharge start                                 534,769 (30,259)
1002:RO vboot init                                     534,813 (44)
1020:vboot select&load kernel                          534,815 (2)
1030:finished EC verification                          554,600 (19,785)
1060:finished AuxFW Sync                               560,740 (6,140)
1040:finished storage device initialization            612,960 (52,220)
1050:finished reading kernel from disk                 639,711 (26,751)
1100:finished vboot kernel verification                710,596 (70,885)
1102:starting kernel decompression/relocation          731,729 (21,133)
1101:jumping to kernel                                 945,034 (213,305)

Signed-off-by: Vince Liu <vince-wl.liu@mediatek.corp-partner.google.com>
Signed-off-by: Zhanzhan Ge <zhanzhan.ge@mediatek.corp-partner.google.com>
Change-Id: Ic79003b5a5b747a3761fd4612cad6a96ada216b6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88468
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
---
 src/soc/mediatek/mt8189/Makefile.mk         | 2 +-
 src/soc/mediatek/mt8189/include/soc/timer.h | 3 +++
 src/soc/mediatek/mt8189/timer.c             | 8 ++++++--
 3 files changed, 10 insertions(+), 3 deletions(-)

diff --git a/src/soc/mediatek/mt8189/Makefile.mk b/src/soc/mediatek/mt8189/Makefile.mk
index 7c114e8a6d..b0adf83fa7 100644
--- a/src/soc/mediatek/mt8189/Makefile.mk
+++ b/src/soc/mediatek/mt8189/Makefile.mk
@@ -7,7 +7,7 @@ all-y += ../common/gpio.c ../common/gpio_op.c ../common/gpio_eint_v2.c gpio.c gp
 all-y += ../common/i2c.c ../common/i2c_common.c i2c.c
 all-y += ../common/pll.c pll.c
 all-$(CONFIG_SPI_FLASH) += ../common/spi.c spi.c
-all-y += ../common/timer_prepare_v1.c timer.c
+all-y += ../common/timer_prepare_v2.c timer.c
 all-y += ../common/uart.c
 
 bootblock-y += ../common/bootblock.c bootblock.c
diff --git a/src/soc/mediatek/mt8189/include/soc/timer.h b/src/soc/mediatek/mt8189/include/soc/timer.h
index 60af8aac87..331b400002 100644
--- a/src/soc/mediatek/mt8189/include/soc/timer.h
+++ b/src/soc/mediatek/mt8189/include/soc/timer.h
@@ -8,6 +8,9 @@
 #ifndef __SOC_MEDIATEK_MT8189_INCLUDE_SOC_TIMER_H__
 #define __SOC_MEDIATEK_MT8189_INCLUDE_SOC_TIMER_H__
 
+#include <soc/timer_reg.h>
 #include <soc/timer_v2.h>
 
+#define COMP_FEATURE_25_EN		0x6
+
 #endif /* __SOC_MEDIATEK_MT8189_INCLUDE_SOC_TIMER_H__ */
diff --git a/src/soc/mediatek/mt8189/timer.c b/src/soc/mediatek/mt8189/timer.c
index 0d9776b0c2..ee49b4d57e 100644
--- a/src/soc/mediatek/mt8189/timer.c
+++ b/src/soc/mediatek/mt8189/timer.c
@@ -5,11 +5,15 @@
  * Chapter number: 9.16
  */
 
-#include <arch/lib_helpers.h>
-#include <commonlib/helpers.h>
 #include <delay.h>
 #include <soc/timer.h>
 
+void timer_set_compensation(void)
+{
+	SET32_BITFIELDS(&mtk_systimer->cntcr,
+			COMP_FEATURE, COMP_FEATURE_CLR | COMP_FEATURE_25_EN);
+}
+
 void init_timer(void)
 {
 	timer_prepare();

From 1b8dd662a9e1ea3b05699ae8c8d3f7a2989cccf3 Mon Sep 17 00:00:00 2001
From: haril <haril@qualcomm.corp-partner.google.com>
Date: Wed, 16 Jul 2025 16:55:00 +0530
Subject: [PATCH 1616/3886] soc/qualcomm/x1p42100: Add PCIE Clock support for
 x1p42100

Add support to enable PCIE NOC, Controller and PHY clocks.
The register details are part of HRD-X1P42100-S1 document.
https://docs.qualcomm.com/bundle/resource/topics/HRD-X1P42100-S1/

TEST=Create an image.serial.bin, ensure it boots on X1P42100 and
check clock status

Change-Id: I6007a8315343a2d56d51c8472ace831a10146768
Signed-off-by: Hari L <haril@qualcomm.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88481
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
---
 src/soc/qualcomm/x1p42100/Makefile.mk         |   1 +
 src/soc/qualcomm/x1p42100/clock.c             | 205 ++++++++++++++++++
 .../x1p42100/include/soc/addressmap.h         |  42 ++++
 src/soc/qualcomm/x1p42100/include/soc/clock.h | 177 ++++++++++++++-
 src/soc/qualcomm/x1p42100/pcie.c              |  42 +++-
 5 files changed, 454 insertions(+), 13 deletions(-)

diff --git a/src/soc/qualcomm/x1p42100/Makefile.mk b/src/soc/qualcomm/x1p42100/Makefile.mk
index da3c25b005..719f53988d 100644
--- a/src/soc/qualcomm/x1p42100/Makefile.mk
+++ b/src/soc/qualcomm/x1p42100/Makefile.mk
@@ -40,6 +40,7 @@ ramstage-y += soc.c
 ramstage-y += cbmem.c
 ramstage-$(CONFIG_DRIVERS_UART) += ../common/qupv3_uart.c
 ramstage-$(CONFIG_PCI) += ../common/pcie_common.c
+ramstage-$(CONFIG_PCI) += pcie.c
 ramstage-y += cpucp_load_reset.c
 
 ################################################################################
diff --git a/src/soc/qualcomm/x1p42100/clock.c b/src/soc/qualcomm/x1p42100/clock.c
index 283428642e..510c2ca559 100644
--- a/src/soc/qualcomm/x1p42100/clock.c
+++ b/src/soc/qualcomm/x1p42100/clock.c
@@ -79,6 +79,169 @@ static struct clock_freq_config qupv3_wrap_cfg[] = {
 	},
 };
 
+static u32 *gdsc[MAX_GDSC] = {
+	[PCIE_6A_GDSC] = &gcc->pcie_6a.gdscr,
+	[PCIE_6_PHY_GDSC] = &gcc->pcie_6_phy_gdscr,
+};
+
+struct pcie pcie_cfg[] = {
+	[PCIE_6A_GDSC] = {
+		.gdscr = &gcc->pcie_6a.gdscr,
+	},
+	[ANOC_PCIE_AT_CBCR] = {
+		.clk = &gcc->pcie_noc.anoc_pcie_at_cbcr,
+		.clk_br_en = &gcc->apcs_clk_br_en2,
+		.vote_bit = ANOC_PCIE_AT_CLK_ENA,
+	},
+	[ANOC_PCIE_QOSGEN_EXTREF_CBCR] = {
+		.clk = &gcc->pcie_noc.anoc_pcie_qosgen_extref_cbcr,
+		.clk_br_en = &gcc->apcs_clk_br_en2,
+		.vote_bit = ANOC_PCIE_QOSGEN_EXTREF_CLK_ENA,
+	},
+	[DDRSS_PCIE_SF_QTB_CBCR] = {
+		.clk = &gcc->pcie_noc.ddrss_pcie_sf_qtb_cbcr,
+		.clk_br_en = &gcc->apcs_clk_br_en,
+		.vote_bit = DDRSS_PCIE_SF_QTB_CLK_ENA,
+	},
+	[CNOC_PCIE_NORTH_SF_AXI_CBCR] = {
+		.clk = &gcc->pcie_noc.cnoc_pcie_north_sf_axi_cbcr,
+		.clk_br_en = &gcc->apcs_clk_br_en1,
+		.vote_bit = CNOC_PCIE_NORTH_SF_AXI_CLK_ENA,
+	},
+	[CNOC_PCIE_SOUTH_SF_AXI_CBCR] = {
+		.clk = &gcc->pcie_noc.cnoc_pcie_south_sf_axi_cbcr,
+		.clk_br_en = &gcc->apcs_clk_br_en5,
+		.vote_bit = CNOC_PCIE_SOUTH_SF_AXI_CLK_ENA,
+	},
+	[NOC_PCIE_DCD_XO_CBCR] = {
+		.clk = &gcc->pcie_noc.noc_pcie_dcd_xo_cbcr,
+		.clk_br_en = &gcc->apcs_clk_br_en5,
+		.vote_bit = NOC_PCIE_DCD_XO_CLK_ENA,
+	},
+	[NOC_PCIE_SOUTH_DCD_XO_CBCR] = {
+		.clk = &gcc->pcie_noc.noc_pcie_south_dcd_xo_cbcr,
+		.clk_br_en = &gcc->apcs_clk_br_en5,
+		.vote_bit = NOC_PCIE_SOUTH_DCD_XO_CLK_ENA,
+	},
+	[NOC_PCIE_NORTH_DCD_XO_CBCR] = {
+		.clk = &gcc->pcie_noc.noc_pcie_north_dcd_xo_cbcr,
+		.clk_br_en = &gcc->apcs_clk_br_en1,
+		.vote_bit = NOC_PCIE_NORTH_DCD_XO_CLK_ENA,
+	},
+	[CFG_NOC_PCIE_ANOC_AHB_CBCR] = {
+		.clk = &gcc->pcie_noc.cfg_noc_pcie_anoc_ahb_cbcr,
+		.clk_br_en = &gcc->apcs_clk_br_en5,
+		.vote_bit = CFG_NOC_PCIE_ANOC_AHB_CLK_ENA,
+	},
+	[CFG_NOC_PCIE_ANOC_NORTH_AHB_CBCR] = {
+		.clk = &gcc->pcie_noc.cfg_noc_pcie_anoc_north_ahb_cbcr,
+		.clk_br_en = &gcc->apcs_clk_br_en5,
+		.vote_bit = CFG_NOC_PCIE_ANOC_NORTH_AHB_CLK_ENA,
+	},
+	[CFG_NOC_PCIE_ANOC_SOUTH_AHB_CBCR] = {
+		.clk = &gcc->pcie_noc.cfg_noc_pcie_anoc_south_ahb_cbcr,
+		.clk_br_en = &gcc->apcs_clk_br_en,
+		.vote_bit = CFG_NOC_PCIE_ANOC_SOUTH_AHB_CLK_ENA,
+	},
+	[AGGRE_NOC_PCIE_NORTH_AXI_CBCR] = {
+		.clk = &gcc->pcie_noc.aggre_noc_pcie_north_axi_cbcr,
+		.clk_br_en = &gcc->apcs_clk_br_en5,
+		.vote_bit = AGGRE_NOC_PCIE_NORTH_AXI_CLK_ENA,
+	},
+	[ANOC_PCIE_PWRCTL_CBCR] = {
+		.clk = &gcc->pcie_noc.anoc_pcie_pwrctl_cbcr,
+		.clk_br_en = &gcc->apcs_clk_br_en1,
+		.vote_bit = ANOC_PCIE_PWRCTL_CLK_ENA,
+	},
+	[AGGRE_NOC_PCIE_SOUTH_AXI_CBCR] = {
+		.clk = &gcc->pcie_noc.aggre_noc_pcie_south_axi_cbcr,
+		.clk_br_en = &gcc->apcs_clk_br_en5,
+		.vote_bit = AGGRE_NOC_PCIE_SOUTH_AXI_CLK_ENA,
+	},
+	[AGGRE_NOC_PCIE_HS_AXI_CBCR] = {
+		.clk = &gcc->pcie_noc.aggre_noc_pcie_hs_axi_cbcr,
+		.clk_br_en = &gcc->apcs_clk_br_en5,
+		.vote_bit = AGGRE_NOC_PCIE_HS_AXI_CLK_ENA,
+	},
+	[AGGRE_NOC_PCIE_HS_NORTH_AXI_CBCR] = {
+		.clk = &gcc->pcie_noc.aggre_noc_pcie_hs_north_axi_cbcr,
+		.clk_br_en = &gcc->apcs_clk_br_en5,
+		.vote_bit = AGGRE_NOC_PCIE_HS_NORTH_AXI_CLK_ENA,
+	},
+	[AGGRE_NOC_PCIE_HS_SOUTH_AXI_CBCR] = {
+		.clk = &gcc->pcie_noc.aggre_noc_pcie_hs_south_axi_cbcr,
+		.clk_br_en = &gcc->apcs_clk_br_en5,
+		.vote_bit = AGGRE_NOC_PCIE_HS_SOUTH_AXI_CLK_ENA,
+	},
+	[CNOC_PCIE_NORTH_SF_TUNNEL_AXI_CBCR] = {
+		.clk = &gcc->pcie_noc.cnoc_pcie_north_sf_tunnel_axi_cbcr,
+		.clk_br_en = &gcc->apcs_clk_br_en2,
+		.vote_bit = CNOC_PCIE_NORTH_SF_TUNNEL_AXI_CLK_ENA,
+	},
+	[CNOC_PCIE_SOUTH_SF_TUNNEL_AXI_CBCR] = {
+		.clk = &gcc->pcie_noc.cnoc_pcie_south_sf_tunnel_axi_cbcr,
+		.clk_br_en = &gcc->apcs_clk_br_en2,
+		.vote_bit = CNOC_PCIE_SOUTH_SF_TUNNEL_AXI_CLK_ENA,
+	},
+	[PCIE_6A_SLV_Q2A_AXI_CLK] = {
+		.clk = &gcc->pcie_6a.slv_q2a_axi_cbcr,
+		.clk_br_en = &gcc->apcs_clk_br_en3,
+		.vote_bit = PCIE_6A_SLV_Q2A_AXI_CLK_ENA,
+	},
+	[PCIE_6A_SLV_AXI_CLK] = {
+		.clk = &gcc->pcie_6a.slv_axi_cbcr,
+		.clk_br_en = &gcc->apcs_clk_br_en3,
+		.vote_bit = PCIE_6A_SLV_AXI_CLK_ENA,
+	},
+	[PCIE_6A_MSTR_AXI_CLK] = {
+		.clk = &gcc->pcie_6a.mstr_axi_cbcr,
+		.clk_br_en = &gcc->apcs_clk_br_en3,
+		.vote_bit = PCIE_6A_MSTR_AXI_CLK_ENA,
+	},
+	[PCIE_6A_CFG_AHB_CLK] = {
+		.clk = &gcc->pcie_6a.cfg_ahb_cbcr,
+		.clk_br_en = &gcc->apcs_clk_br_en3,
+		.vote_bit = PCIE_6A_CFG_AHB_CLK_ENA,
+	},
+	[PCIE_6A_AUX_CLK] = {
+		.clk = &gcc->pcie_6a.aux_cbcr,
+		.clk_br_en = &gcc->apcs_clk_br_en3,
+		.vote_bit = PCIE_6A_AUX_CLK_ENA,
+	},
+	[PCIE_6A_PHY_AUX_CLK] = {
+		.clk = &gcc->pcie_6a.phy_aux_cbcr,
+		.clk_br_en = &gcc->apcs_clk_br_en3,
+		.vote_bit = PCIE_6A_PHY_AUX_CLK_ENA,
+	},
+	[PCIE_6A_PHY_RCHNG_CLK] = {
+		.clk = &gcc->pcie_6a.phy_rchng_cbcr,
+		.clk_br_en = &gcc->apcs_clk_br_en3,
+		.vote_bit = PCIE_6A_PHY_RCHNG_CLK_ENA,
+	},
+	[PCIE_6A_PIPE_CLK] = {
+		.clk = &gcc->pcie_6a.pipe_cbcr,
+		.clk_br_en = &gcc->apcs_clk_br_en3,
+		.vote_bit = PCIE_6A_PIPE_CLK_ENA,
+	},
+	[PCIE_6A_PIPEDIV2_CLK] = {
+		.clk = &gcc->pcie_6a.pipediv2_cbcr,
+		.clk_br_en = &gcc->apcs_clk_br_en3,
+		.vote_bit = PCIE_6A_PIPEDIV2_CLK_ENA,
+	},
+	[PCIE_6A_PIPE_MUXR] = {
+		.clk = &gcc->pcie_6a.pipe_muxr,
+		.vote_bit = NO_VOTE_BIT,
+	},
+};
+
+static struct clock_freq_config pcie_core_cfg[] = {
+	{
+		.hz = 100 * MHz,
+		.src = SRC_GPLL0_MAIN_600MHZ,
+		.div = QCOM_CLOCK_DIV(6),
+	},
+};
+
 void clock_configure_qspi(uint32_t hz)
 {
 	clock_configure(&gcc->qspi_core, qspi_core_cfg, hz, ARRAY_SIZE(qspi_core_cfg));
@@ -134,6 +297,48 @@ static enum cb_err clock_configure_gpll0(void)
 	return clock_configure_enable_gpll(&gpll0_cfg, false, 0);
 }
 
+
+enum cb_err clock_enable_gdsc(enum clk_gdsc gdsc_type)
+{
+	if (gdsc_type > MAX_GDSC)
+		return CB_ERR;
+
+	return enable_and_poll_gdsc_status(gdsc[gdsc_type]);
+}
+
+enum cb_err clock_enable_pcie(enum clk_pcie clk_type)
+{
+	int clk_vote_bit;
+
+	if (clk_type >= PCIE_CLK_COUNT)
+		return CB_ERR;
+
+	clk_vote_bit = pcie_cfg[clk_type].vote_bit;
+	if (clk_vote_bit < 0)
+		return clock_enable(pcie_cfg[clk_type].clk);
+
+	return clock_enable_vote(pcie_cfg[clk_type].clk,
+			pcie_cfg[clk_type].clk_br_en, pcie_cfg[clk_type].vote_bit);
+
+}
+
+enum cb_err clock_configure_mux(enum clk_pcie clk_type, u32 src_type)
+{
+	if (clk_type >= PCIE_CLK_COUNT)
+		return CB_ERR;
+
+	/* Set clock src */
+	write32(pcie_cfg[clk_type].clk, src_type);
+
+	return CB_SUCCESS;
+}
+
+void clock_configure_pcie(void)
+{
+	 clock_configure(&gcc->pcie_6a.phy_rchng_rcg,
+			pcie_core_cfg, PCIE_PHY_RCHNG_FREQ, ARRAY_SIZE(pcie_core_cfg));
+}
+
 static void speed_up_boot_cpu(void)
 {
 	/* Placeholder */
diff --git a/src/soc/qualcomm/x1p42100/include/soc/addressmap.h b/src/soc/qualcomm/x1p42100/include/soc/addressmap.h
index 818b3463b4..c79f300bd2 100644
--- a/src/soc/qualcomm/x1p42100/include/soc/addressmap.h
+++ b/src/soc/qualcomm/x1p42100/include/soc/addressmap.h
@@ -59,4 +59,46 @@
 #define QUP_WRAP2_BASE			0x008C0000
 #define QUP_2_GSI_BASE			0x00804000
 
+/* PCIE 6A */
+#define PCIE6A_PCIE_PARF		0x01BF8000
+#define PCIE6A_GEN1X4_PCIE_DBI		0x70000000
+#define PCIE6A_GEN1X4_PCIE_ELBI		0x70000F40
+#define PCIE6A_GEN1X4_DWC_PCIE_DM_IATU	0x70001000
+#define PCIE6A_SPACE_END_ADDR		0x74000000
+#define PCIE6A_BCR			0x131000
+#define GCC_PCIE_6A_PHY_BCR		0x1AC01C
+
+/* QMP PHY, Serdes,Tx, Rx and PCS register definitions */
+#define PCIE_6A_AQMP_PHY		0x01BFC000
+#define PCIE_6A_BQMP_PHY		0x01BFE000
+
+#define PCIE6A_AQPHY_TX0		0x01BFC000
+#define PCIE6A_AQPHY_RX0		0x01BFC200
+#define PCIE6A_AQPHY_TX1		0x01BFC800
+#define PCIE6A_AQPHY_RX1		0x01BFCA00
+#define PCIE6A_AQPHY_LN_SHRD		0x01BFCE00
+#define PCIE6A_AQPHY_SERDES		0x01BFD000
+#define PCIE6A_AQPHY_PCS_COM		0x01BFD200
+#define PCIE6A_AQPHY_PCS_PCIE		0x01BFD400
+#define PCIE6A_AQPHY_PCS_LANE0		0x01BFD800
+#define PCIE6A_AQPHY_PCS_PCIE_LANE0	0x01BFDA00
+#define PCIE6A_AQPHY_PCS_LANE1		0x01BFDC00
+#define PCIE6A_AQPHY_PCS_PCIE_LANE1	0x01BFDE00
+
+#define PCIE6A_BQPHY_TX0		0x01BFE000
+#define PCIE6A_BQPHY_RX0		0x01BFE200
+#define PCIE6A_BQPHY_TX1		0x01BFE800
+#define PCIE6A_BQPHY_RX1		0x01BFEA00
+#define PCIE6A_BQPHY_LN_SHRD		0x01BFEE00
+#define PCIE6A_BQPHY_SERDES		0x01BFF000
+#define PCIE6A_BQPHY_PCS_COM		0x01BFF200
+#define PCIE6A_BQPHY_PCS_PCIE		0x01BFF400
+#define PCIE6A_BQPHY_PCS_LANE0		0x01BFF800
+#define PCIE6A_BQPHY_PCS_PCIE_LANE0	0x01BFFA00
+#define PCIE6A_BQPHY_PCS_LANE1		0x01BFFC00
+#define PCIE6A_BQPHY_PCS_PCIE_LANE1	0x01BFFE00
+
+/* TCSR */
+#define TCSR_GCC_PCIE_4L_CLKREF_EN_PCIE_ENABLE           ((void *)0x1FD512C)
+
 #endif /*  __SOC_QUALCOMM_X1P42100_ADDRESS_MAP_H__ */
diff --git a/src/soc/qualcomm/x1p42100/include/soc/clock.h b/src/soc/qualcomm/x1p42100/include/soc/clock.h
index f9848c697a..82556341ca 100644
--- a/src/soc/qualcomm/x1p42100/include/soc/clock.h
+++ b/src/soc/qualcomm/x1p42100/include/soc/clock.h
@@ -13,6 +13,8 @@
 #define GPLL0_MAIN_HZ		(600 * MHz)
 #define CLK_100MHZ		(100 * MHz)
 
+#define PCIE_PHY_RCHNG_FREQ CLK_100MHZ
+
 #define QUPV3_WRAP0_CLK_ENA_S(idx)		(10 + idx)
 #define QUPV3_WRAP1_CLK_ENA_S(idx)		(22 + idx)
 #define QUPV3_WRAP2_CLK_ENA_S(idx)		(4 + idx)
@@ -50,6 +52,35 @@ enum apcs_branch_en_vote {
 	QUPV3_WRAP2_CORE_CLK_ENA = 0,
 	QUPV3_WRAP_2_M_AHB_CLK_ENA = 2,
 	QUPV3_WRAP_2_S_AHB_CLK_ENA = 1,
+	ANOC_PCIE_AT_CLK_ENA = 11,
+	ANOC_PCIE_QOSGEN_EXTREF_CLK_ENA = 13,
+	DDRSS_PCIE_SF_QTB_CLK_ENA = 19,
+	CNOC_PCIE_NORTH_SF_AXI_CLK_ENA = 6,
+	CNOC_PCIE_SOUTH_SF_AXI_CLK_ENA = 12,
+	NOC_PCIE_DCD_XO_CLK_ENA = 24,
+	NOC_PCIE_SOUTH_DCD_XO_CLK_ENA = 25,
+	NOC_PCIE_NORTH_DCD_XO_CLK_ENA = 29,
+	CFG_NOC_PCIE_ANOC_AHB_CLK_ENA = 20,
+	CFG_NOC_PCIE_ANOC_NORTH_AHB_CLK_ENA = 22,
+	CFG_NOC_PCIE_ANOC_SOUTH_AHB_CLK_ENA = 20,
+	AGGRE_NOC_PCIE_NORTH_AXI_CLK_ENA = 19,
+	ANOC_PCIE_PWRCTL_CLK_ENA = 31,
+	AGGRE_NOC_PCIE_SOUTH_AXI_CLK_ENA = 13,
+	AGGRE_NOC_PCIE_HS_AXI_CLK_ENA = 14,
+	AGGRE_NOC_PCIE_HS_NORTH_AXI_CLK_ENA = 15,
+	AGGRE_NOC_PCIE_HS_SOUTH_AXI_CLK_ENA = 16,
+	CNOC_PCIE_NORTH_SF_TUNNEL_AXI_CLK_ENA = 14,
+	CNOC_PCIE_SOUTH_SF_TUNNEL_AXI_CLK_ENA = 15,
+	PCIE_6A_SLV_Q2A_AXI_CLK_ENA = 20,
+	PCIE_6A_SLV_AXI_CLK_ENA = 21,
+	PCIE_6A_MSTR_AXI_CLK_ENA = 22,
+	PCIE_6A_CFG_AHB_CLK_ENA = 23,
+	PCIE_6A_AUX_CLK_ENA = 24,
+	PCIE_6A_PHY_AUX_CLK_ENA = 25,
+	PCIE_6A_PIPE_CLK_ENA = 26,
+	PCIE_6A_PHY_RCHNG_CLK_ENA = 27,
+	PCIE_6A_PIPEDIV2_CLK_ENA = 28,
+	NO_VOTE_BIT = -1,
 };
 
 struct x1p42100_gpll {
@@ -66,9 +97,68 @@ struct x1p42100_gpll {
 	u32 config_ctl_u1;
 };
 
+struct x1p42100_pcie_noc {
+	u32 anoc_pcie_at_cbcr;
+	u32 anoc_pcie_tsctr_cbcr;
+	u32 anoc_pcie_qosgen_extref_cbcr;
+	u32 ddrss_pcie_sf_qtb_cbcr;
+	u32 cnoc_pcie_north_sf_axi_cbcr;
+	u32 cnoc_pcie_south_sf_axi_cbcr;
+	u32 noc_pcie_north_dcd_xo_cbcr;
+	u32 noc_pcie_dcd_xo_cbcr;
+	u32 noc_pcie_south_dcd_xo_cbcr;
+	u32 cfg_noc_pcie_anoc_ahb_cbcr;
+	u32 cfg_noc_pcie_anoc_north_ahb_cbcr;
+	u32 cfg_noc_pcie_anoc_south_ahb_cbcr;
+	u32 aggre_noc_pcie_north_axi_cbcr;
+	u32 anoc_pcie_pwrctl_cbcr;
+	u32 aggre_noc_pcie_south_axi_cbcr;
+	u32 aggre_noc_pcie_hs_axi_cbcr;
+	u32 aggre_noc_pcie_hs_north_axi_cbcr;
+	u32 aggre_noc_pcie_hs_south_axi_cbcr;
+	u32 cnoc_pcie_north_sf_tunnel_axi_cbcr;
+	u32 cnoc_pcie_south_sf_tunnel_axi_cbcr;
+};
+
+struct x1p42100_pcie {
+	u32 bcr;
+	u32 gdscr;
+	u8 _res0[0x131018 - 0x131008];
+	u32 slv_q2a_axi_cbcr;
+	u32 slv_axi_cbcr;
+	u8 _res1[0x131028 - 0x131020];
+	u32 mstr_axi_cbcr;
+	u8 _res2[0x131034 - 0x13102c];
+	u32 cfg_ahb_cbcr;
+	u32 aux_cbcr;
+	u8 _res3[0x131044 - 0x13103c];
+	u32 phy_aux_cbcr;
+	u8 _res4[0x131050 - 0x131048];
+	u32 pipe_cbcr;
+	u8 _res5[0x13105c - 0x131054];
+	u32 phy_rchng_cbcr;
+	u32 pipediv2_cbcr;
+	u8 _res6[0x131070 - 0x131064];
+	struct clock_rcg phy_rchng_rcg;
+	u8 _res7[0x131088 - 0x131078];
+	u32 pipe_muxr;
+};
+
+check_member(x1p42100_pcie, slv_q2a_axi_cbcr, 0x18);
+check_member(x1p42100_pcie, mstr_axi_cbcr, 0x28);
+check_member(x1p42100_pcie, cfg_ahb_cbcr, 0x34);
+check_member(x1p42100_pcie, phy_aux_cbcr, 0x44);
+check_member(x1p42100_pcie, pipe_cbcr, 0x50);
+check_member(x1p42100_pcie, phy_rchng_cbcr, 0x5c);
+check_member(x1p42100_pcie, phy_rchng_rcg, 0x70);
+check_member(x1p42100_pcie, pipe_muxr, 0x88);
+
 struct x1p42100_gcc {
 	struct x1p42100_gpll gpll0;
-	u8 _res1[0x18004 - 0x0002c];
+	u8 _res0[0x10004 - 0x0002c];
+	struct x1p42100_pcie_noc pcie_noc;
+	u8 _res1[0x18004 - 0x10054];
+
 	struct qupv3_clock qup_wrap1_s[8];
 	u8 _res2[0x1e004 - 0x189c4];
 	struct qupv3_clock qup_wrap2_s[8];
@@ -99,27 +189,33 @@ struct x1p42100_gcc {
 	u32 qup_wrap2_core_2x_cbcr;
 	u8 _res11[0x232c4 - 0x232bc];
 	struct clock_rcg qup_wrap2_core_2x;
-	u8 _res12[0x42004 - 0x232cc];
+	u8 _res12[0x31000 - 0x232cc];
+	struct x1p42100_pcie pcie_6a;
+	u8  res13[0x42004-0x3108c];
 	struct qupv3_clock qup_wrap0_s[8];
-	u8 _res13[0x4b000 - 0x429c4];
+	u8 _res14[0x4b000 - 0x429c4];
 	u32 qspi_bcr;
 	u32 qspi_cnoc_ahb_cbcr;
 	u32 qspi_core_cbcr;
 	struct clock_rcg qspi_core;
-	u8 _res14[0x52000 - 0x4b014];
+	u8 _res15[0x52000 - 0x4b014];
 	u32 apcs_clk_br_en;
-	u8 _res15[0x52008 - 0x52004];
+	u8 _res16[0x52008 - 0x52004];
 	u32 apcs_clk_br_en1;
-	u8 _res16[0x52010 - 0x5200C];
+	u8 _res17[0x52010 - 0x5200c];
 	u32 apcs_clk_br_en2;
-	u8 _res17[0x52018 - 0x52014];
+	u8 _res18[0x52018 - 0x52014];
 	u32 apcs_clk_br_en3;
-	u8 _res18[0x52020 - 0x5201c];
+	u8 _res19[0x52020 - 0x5201c];
 	u32 apcs_clk_br_en4;
-	u8 _res19[0x52028 - 0x52024];
+	u8 _res20[0x52028 - 0x52024];
 	u32 apcs_clk_br_en5;
-	u8 _res20[0x52030 - 0x5202c];
+	u8 _res21[0x52030 - 0x5202c];
 	u32 apcs_pll_br_en;
+	u8 _res22[0x8e000 - 0x52034];
+	u32 pcie_6_phy_gdscr;
+	u8 _res23[0xac01c - 0x8e004];
+	u32 pcie_6a_phy_bcr;
 };
 
 check_member(x1p42100_gcc, qup_wrap1_s, 0x18004);
@@ -142,6 +238,8 @@ check_member(x1p42100_gcc, apcs_clk_br_en3, 0x52018);
 check_member(x1p42100_gcc, apcs_clk_br_en4, 0x52020);
 check_member(x1p42100_gcc, apcs_clk_br_en5, 0x52028);
 check_member(x1p42100_gcc, apcs_pll_br_en, 0x52030);
+check_member(x1p42100_gcc, pcie_6_phy_gdscr, 0x8e000);
+check_member(x1p42100_gcc, pcie_6a_phy_bcr, 0xac01c);
 
 enum clk_qup {
 	QUP_WRAP0_S0,
@@ -170,11 +268,70 @@ enum clk_qup {
 	QUP_WRAP2_S7,
 };
 
+struct pcie {
+	uint32_t *gdscr;
+	uint32_t *clk;
+	uint32_t *clk_br_en;
+	int vote_bit;
+};
+
+enum clk_gdsc {
+	PCIE_6A_GDSC,
+	PCIE_6_PHY_GDSC,
+	MAX_GDSC
+};
+
+enum clk_pcie_src_sel {
+	PCIE_6A_PIPE_SRC_SEL = 0,
+	PCIE_6A_XO_SRC_SEL = 2,
+};
+
+enum clk_pcie {
+	ANOC_PCIE_AT_CBCR = 1,
+	ANOC_PCIE_QOSGEN_EXTREF_CBCR,
+	DDRSS_PCIE_SF_QTB_CBCR,
+	CNOC_PCIE_NORTH_SF_AXI_CBCR,
+	CNOC_PCIE_SOUTH_SF_AXI_CBCR,
+	NOC_PCIE_DCD_XO_CBCR,
+	NOC_PCIE_SOUTH_DCD_XO_CBCR,
+	NOC_PCIE_NORTH_DCD_XO_CBCR,
+	CFG_NOC_PCIE_ANOC_AHB_CBCR,
+	CFG_NOC_PCIE_ANOC_NORTH_AHB_CBCR,
+	CFG_NOC_PCIE_ANOC_SOUTH_AHB_CBCR,
+	AGGRE_NOC_PCIE_NORTH_AXI_CBCR,
+	ANOC_PCIE_PWRCTL_CBCR,
+	AGGRE_NOC_PCIE_SOUTH_AXI_CBCR,
+	AGGRE_NOC_PCIE_HS_AXI_CBCR,
+	AGGRE_NOC_PCIE_HS_NORTH_AXI_CBCR,
+	AGGRE_NOC_PCIE_HS_SOUTH_AXI_CBCR,
+	CNOC_PCIE_NORTH_SF_TUNNEL_AXI_CBCR,
+	CNOC_PCIE_SOUTH_SF_TUNNEL_AXI_CBCR,
+	PCIE_6A_SLV_Q2A_AXI_CLK,
+	PCIE_6A_SLV_AXI_CLK,
+	PCIE_6A_MSTR_AXI_CLK,
+	PCIE_6A_CFG_AHB_CLK,
+	PCIE_6A_AUX_CLK,
+	PCIE_6A_PHY_AUX_CLK,
+	PCIE_6A_PHY_RCHNG_CLK,
+	PCIE_6A_PIPE_CLK,
+	PCIE_6A_PIPEDIV2_CLK,
+	PCIE_6A_PIPE_MUXR,
+	PCIE_CLK_COUNT,
+};
+enum subsystem_reset {
+	AOP_RESET_SHFT,
+	CORE_SW_RESET,
+};
+
 /* TODO: update as per datasheet */
 void clock_init(void);
 void clock_configure_qspi(uint32_t hz);
 void clock_enable_qup(int qup);
 void clock_configure_dfsr(int qup);
+void clock_configure_pcie(void);
+enum cb_err clock_enable_gdsc(enum clk_gdsc gdsc_type);
+enum cb_err clock_enable_pcie(enum clk_pcie clk_type);
+enum cb_err clock_configure_mux(enum clk_pcie clk_type, u32 src_type);
 
 /* Subsystem Reset */
 static struct aoss *const aoss = (void *)AOSS_CC_BASE;
diff --git a/src/soc/qualcomm/x1p42100/pcie.c b/src/soc/qualcomm/x1p42100/pcie.c
index 3e38450c4b..031e15d8c8 100644
--- a/src/soc/qualcomm/x1p42100/pcie.c
+++ b/src/soc/qualcomm/x1p42100/pcie.c
@@ -1,11 +1,22 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
+#include <console/console.h>
+#include <device/device.h>
+#include <device/mmio.h>
+#include <device/pci.h>
+#include <soc/addressmap.h>
+#include <soc/clock.h>
+#include <soc/qcom_qmp_phy.h>
 #include <soc/pcie.h>
 
 /* Enable PIPE clock */
 int qcom_dw_pcie_enable_pipe_clock(void)
 {
-	/* placeholder */
+	/* Set pipe clock source */
+	if (clock_configure_mux(PCIE_6A_PIPE_MUXR, PCIE_6A_PIPE_SRC_SEL)) {
+		printk(BIOS_ERR, " %s(): Pipe clock enable failed\n", __func__);
+		return -1;
+	}
 
 	return 0;
 }
@@ -13,9 +24,34 @@ int qcom_dw_pcie_enable_pipe_clock(void)
 /* Enable controller specific clocks */
 int32_t qcom_dw_pcie_enable_clock(void)
 {
-	/* placeholder */
+	int32_t ret, clk, gdsc;
 
-	return 0;
+	/* Enable gdsc before enable pcie clocks */
+	for (gdsc = PCIE_6A_GDSC; gdsc < MAX_GDSC; gdsc++) {
+		ret = clock_enable_gdsc(gdsc);
+		if (ret) {
+			printk(BIOS_ERR, "Failed to enable gdsc\n");
+			return ret;
+		}
+	}
+
+	/* Configure gcc_pcie*_phy_rchng_clk to 100mhz */
+	clock_configure_pcie();
+
+	/* Enable pcie and PHY clocks */
+	for (clk = ANOC_PCIE_AT_CBCR; clk < PCIE_CLK_COUNT; clk++) {
+		if (clk == PCIE_6A_PIPE_MUXR) {
+			printk(BIOS_DEBUG, "Skipping pipe\n");
+			continue;
+		}
+		ret = clock_enable_pcie(clk);
+		if (ret) {
+			printk(BIOS_ERR, "Failed to enable %d clock\n", clk);
+			return ret;
+		}
+	}
+	write32(TCSR_GCC_PCIE_4L_CLKREF_EN_PCIE_ENABLE, 0x1);
+	return ret;
 }
 
 /* Turn on NVMe */

From 6e4f4538bbdb7dcddd2195df22a3f9ee2f64a6a8 Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Fri, 18 Jul 2025 13:43:58 +0100
Subject: [PATCH 1617/3886] soc/intel/{tgl,adl,mtl,ptl}: Default to Software
 Connection Manager

Commit 060df17f1d17 ("soc/intel/alderlake/acpi: Add Kconfig options for SCM and FCM")
set the default to Firmware Connection Manager, as linux commit
c6da62a219d028de10f2e22e93a34c7ee2b88d03 did not work correctly with
Software Connection Manager.

This issue was fixed with linux commit
719e1f561afbe020ed175825a9bd25ed62ed1697, so now that Software
Connection Manager works, default to it for normal builds as well as
ChromeOS ones.

Change-Id: I4393fc4992d602b7214929592f542270002d84ec
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88484
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
---
 src/soc/intel/alderlake/Kconfig   | 2 +-
 src/soc/intel/meteorlake/Kconfig  | 2 +-
 src/soc/intel/pantherlake/Kconfig | 2 +-
 src/soc/intel/tigerlake/Kconfig   | 2 +-
 4 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig
index fc94695f18..51bdf98b9d 100644
--- a/src/soc/intel/alderlake/Kconfig
+++ b/src/soc/intel/alderlake/Kconfig
@@ -10,7 +10,7 @@ config SOC_INTEL_ALDERLAKE
 	select CPU_INTEL_FIRMWARE_INTERFACE_TABLE
 	select CPU_SUPPORTS_INTEL_TME
 	select CPU_SUPPORTS_PM_TIMER_EMULATION
-	select DEFAULT_SOFTWARE_CONNECTION_MANAGER if MAINBOARD_HAS_CHROMEOS
+	select DEFAULT_SOFTWARE_CONNECTION_MANAGER
 	select DISPLAY_FSP_VERSION_INFO
 	select DRIVERS_USB_ACPI
 	select EDK2_CPU_TIMER_LIB if PAYLOAD_EDK2
diff --git a/src/soc/intel/meteorlake/Kconfig b/src/soc/intel/meteorlake/Kconfig
index 050ddfcd3f..b9dc579c44 100644
--- a/src/soc/intel/meteorlake/Kconfig
+++ b/src/soc/intel/meteorlake/Kconfig
@@ -11,7 +11,7 @@ config SOC_INTEL_METEORLAKE
 	select CPU_INTEL_FIRMWARE_INTERFACE_TABLE
 	select CPU_SUPPORTS_INTEL_TME
 	select CPU_SUPPORTS_PM_TIMER_EMULATION
-	select DEFAULT_SOFTWARE_CONNECTION_MANAGER if MAINBOARD_HAS_CHROMEOS
+	select DEFAULT_SOFTWARE_CONNECTION_MANAGER
 	select DEFAULT_X2APIC_LATE_WORKAROUND
 	select DISPLAY_FSP_VERSION_INFO_2 if !FSP_USE_REPO
 	select DRIVERS_USB_ACPI
diff --git a/src/soc/intel/pantherlake/Kconfig b/src/soc/intel/pantherlake/Kconfig
index 439cdc75f9..9f4e748f74 100644
--- a/src/soc/intel/pantherlake/Kconfig
+++ b/src/soc/intel/pantherlake/Kconfig
@@ -11,7 +11,7 @@ config SOC_INTEL_PANTHERLAKE_BASE
 	select CPU_INTEL_FIRMWARE_INTERFACE_TABLE
 	select CPU_SUPPORTS_INTEL_TME
 	select CPU_SUPPORTS_PM_TIMER_EMULATION
-	select DEFAULT_SOFTWARE_CONNECTION_MANAGER if MAINBOARD_HAS_CHROMEOS
+	select DEFAULT_SOFTWARE_CONNECTION_MANAGER
 	select DEFAULT_X2APIC_LATE_WORKAROUND
 	select POSTPONE_SPI_ACCESS
 	select DISPLAY_FSP_VERSION_INFO_2
diff --git a/src/soc/intel/tigerlake/Kconfig b/src/soc/intel/tigerlake/Kconfig
index 1b04fbc0c8..833684f0a6 100644
--- a/src/soc/intel/tigerlake/Kconfig
+++ b/src/soc/intel/tigerlake/Kconfig
@@ -10,7 +10,7 @@ config SOC_INTEL_TIGERLAKE
 	select CPU_INTEL_FIRMWARE_INTERFACE_TABLE
 	select CPU_SUPPORTS_INTEL_TME
 	select CPU_SUPPORTS_PM_TIMER_EMULATION
-	select DEFAULT_SOFTWARE_CONNECTION_MANAGER if MAINBOARD_HAS_CHROMEOS
+	select DEFAULT_SOFTWARE_CONNECTION_MANAGER
 	select DISPLAY_FSP_VERSION_INFO if !FSP_TYPE_IOT
 	select DRIVERS_USB_ACPI
 	select EDK2_CPU_TIMER_LIB if PAYLOAD_EDK2

From 2e47bd50f2c48db4732a5c864272d066cdd77de0 Mon Sep 17 00:00:00 2001
From: lizheng <lizheng@huaqin.corp-partner.google.com>
Date: Thu, 17 Jul 2025 11:19:44 +0800
Subject: [PATCH 1618/3886] mb/google/trulo/var/pujjocento: Add 6W and 15W DPTF
 parameters

The DPTF parameters were defined by the thermal team.
Based on thermal table in 432114256 comment#1

BUG=b:432114256
TEST=emerge-nissa coreboot chromeos-bootimage
Signed-off-by: lizheng <lizheng@huaqin.corp-partner.google.com>

Change-Id: I969f93f384bb2a59f1300478794f48e30997736d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88463
Reviewed-by: Kun Liu <liukun11@huaqin.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
---
 .../google/brya/variants/pujjocento/overridetree.cb  | 12 ++++++++++++
 1 file changed, 12 insertions(+)

diff --git a/src/mainboard/google/brya/variants/pujjocento/overridetree.cb b/src/mainboard/google/brya/variants/pujjocento/overridetree.cb
index 517d210598..d84f1000ea 100644
--- a/src/mainboard/google/brya/variants/pujjocento/overridetree.cb
+++ b/src/mainboard/google/brya/variants/pujjocento/overridetree.cb
@@ -156,6 +156,18 @@ chip soc/intel/alderlake
 		},
 	}"
 
+	# Power limit config
+	register "power_limits_config[ADL_N_041_6W_CORE]" = "{
+		.tdp_pl1_override = 13,
+		.tdp_pl2_override = 25,
+		.tdp_pl4 = 78,
+	}"
+	register "power_limits_config[ADL_N_081_15W_CORE]" = "{
+		.tdp_pl1_override = 22,
+		.tdp_pl2_override = 35,
+		.tdp_pl4 = 83,
+	}"
+
 	device domain 0 on
 		device ref dtt on
 			chip drivers/intel/dptf

From 542e52c126902e25b013a71f19f9c037d2d9e3bf Mon Sep 17 00:00:00 2001
From: Sasirekaa Madhesu <smadhesu@qualcomm.corp-partner.google.com>
Date: Fri, 18 Jul 2025 14:46:22 +0530
Subject: [PATCH 1619/3886] soc/qualcomm/x1p42100: Optimize memory layout for
 X1P42100

Refactor memory layout on x1p42100 to reuse a single reserved region
for all QC image metadata passed from coreboot to QcLib for TME
authentication. Also, reposition the PRERAM_CBMEM_CONSOLE reservation
after the QcLib region to allow for future expansion.

TEST=Successfully booted google/bluey.

Change-Id: I6eea99241c233935c5d99d48093c42bb1424143f
Signed-off-by: Sasirekaa Madhesu <smadhesu@qualcomm.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88485
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/soc/qualcomm/x1p42100/memlayout.ld | 5 ++---
 1 file changed, 2 insertions(+), 3 deletions(-)

diff --git a/src/soc/qualcomm/x1p42100/memlayout.ld b/src/soc/qualcomm/x1p42100/memlayout.ld
index 016b2aef9c..664ef3570c 100644
--- a/src/soc/qualcomm/x1p42100/memlayout.ld
+++ b/src/soc/qualcomm/x1p42100/memlayout.ld
@@ -46,10 +46,9 @@ SECTIONS
 	REGION(dcb, 0x14862000, 56K, 4K)
 	REGION(dtb, 0x14870000, 32K, 4K)
 	REGION(ddr_training, 0x14878000, 64K, 4K)
-	REGION(shrm_meta, 0x14888000, 16K, 4K)
-	REGION(debug_policy_meta,0x1488C000 , 12K, 4K)
+	REGION(qc_blob_meta, 0x14888000, 16K, 4K)
 	REGION(qclib, 0x14897000, 1536K, 4K)
-	PRERAM_CBMEM_CONSOLE(0x14A17000, 32K)
+	PRERAM_CBMEM_CONSOLE(0x14A30000, 32K)
 	OVERLAP_DECOMPRESSOR_VERSTAGE_ROMSTAGE(0x14A38000, 132K)
 	REGION(auth_metadata,0x14A7D000 , 8K, 4K)
 	REGION(debug_policy, 0x14A7F000, 4K, 4K)

From 451988d01568d65b79223a02e7dd669dcaab1960 Mon Sep 17 00:00:00 2001
From: Luca Lai <luca.lai@lcfc.corp-partner.google.com>
Date: Tue, 15 Jul 2025 11:05:45 +0800
Subject: [PATCH 1620/3886] mb/google/trulo/var/pujjolo: Fix Goodix touchscreen
 function

Change level from low to high to fix goodix touchscreen issue.

BUG=b:430156965
BRANCH=none
TEST= Build and boot to OS to test touch function work fine.

Change-Id: I9bd16b2a9ebb5699ad4bf04b018aefc6b86b4199
Signed-off-by: Luca Lai <luca.lai@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88432
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
---
 src/mainboard/google/brya/variants/pujjolo/overridetree.cb | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/mainboard/google/brya/variants/pujjolo/overridetree.cb b/src/mainboard/google/brya/variants/pujjolo/overridetree.cb
index c9c551025a..3c6d1102e5 100644
--- a/src/mainboard/google/brya/variants/pujjolo/overridetree.cb
+++ b/src/mainboard/google/brya/variants/pujjolo/overridetree.cb
@@ -208,7 +208,7 @@ chip soc/intel/alderlake
 			chip drivers/i2c/hid
 				register "generic.hid" = ""GDIX0000""
 				register "generic.desc" = ""Goodix Touchscreen""
-				register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_E11_IRQ)"
+				register "generic.irq" = "ACPI_IRQ_LEVEL_HIGH(GPP_E11_IRQ)"
 				register "generic.detect" = "1"
 				register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C0)"
 				register "generic.enable_delay_ms" = "20"

From 19d7104d8545c2b5065e82a801b5c4f9887503b2 Mon Sep 17 00:00:00 2001
From: Paul Menzel <pmenzel@molgen.mpg.de>
Date: Fri, 18 Jul 2025 18:30:43 +0200
Subject: [PATCH 1621/3886] drivers/intel/touch: Use recommended short
 multi-line comment style
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

The current style is not part of the coding style [1]. The comment has
five lines, so it’s unclear if the short or long multi-line comment
style should be used. Use the short one, to keep it concise.

[1]: Documentation/contributing/coding_style.md

Change-Id: I500340fd02a54c69db4ca5d753fcb690fae1c520
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88491
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/drivers/intel/touch/touch.c | 9 ++++-----
 1 file changed, 4 insertions(+), 5 deletions(-)

diff --git a/src/drivers/intel/touch/touch.c b/src/drivers/intel/touch/touch.c
index 5ad4518a2a..d0723d5dce 100644
--- a/src/drivers/intel/touch/touch.c
+++ b/src/drivers/intel/touch/touch.c
@@ -510,11 +510,10 @@ static void touch_dev_fill_ssdt_generator(const struct device *dev)
 			touch_generate_acpi_ini(dev);
 			touch_generate_acpi_dsm(config, dev);
 			/* When only THC1 is used, both THC0/1 need to be enabled since THC0's
-			 * device function is '0'. In this case, THC0 should set
-			 * connected_device to TH_SENSOR_NONE so that when the driver detects
-			 * THC0, the _DSM will be available for it to check and exit without
-			 * error.
-			 */
+			   device function is '0'. In this case, THC0 should set
+			   connected_device to TH_SENSOR_NONE so that when the driver detects
+			   THC0, the _DSM will be available for it to check and exit without
+			   error. */
 			if (config->connected_device == TH_SENSOR_NONE)
 				return;
 

From a7710ed8fddca66baf697f74e3ac33a69199b19f Mon Sep 17 00:00:00 2001
From: Paul Menzel <pmenzel@molgen.mpg.de>
Date: Fri, 18 Jul 2025 18:36:20 +0200
Subject: [PATCH 1622/3886] Documentation: coding_style: Add *long* to long
 multi-line comment example

Update the example, after the short multi-line comment alternative was
added several years ago, when the Wiki was still used.

Change-Id: I401180a9ac7c7cdc45fb8e9ba364823092cea6da
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88492
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
---
 Documentation/contributing/coding_style.md | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/Documentation/contributing/coding_style.md b/Documentation/contributing/coding_style.md
index 8828da48fa..50761ae65c 100644
--- a/Documentation/contributing/coding_style.md
+++ b/Documentation/contributing/coding_style.md
@@ -522,7 +522,7 @@ The preferred style for *long* (multi-line) comments is:
 
 ```c
 /*
- * This is the preferred style for multi-line
+ * This is the preferred style for long multi-line
  * comments in the coreboot source code.
  * Please use it consistently.
  *

From 3b069d320cccb93e01f090f435e1ddd5c67d57ff Mon Sep 17 00:00:00 2001
From: Jeremy Compostella <jeremy.compostella@intel.com>
Date: Wed, 16 Jul 2025 14:58:09 -0700
Subject: [PATCH 1623/3886] cbfs: Add a function to wait for all CBFS preload
 operations to complete

Introduce cbfs_preload_wait_for_all() to guarantee that all CBFS preload
contexts complete their tasks before moving forward. This function goes
through each preload context and waits for the corresponding thread to
finish by using thread_join(). If any preload thread runs into an issue,
it records an error message along with the context name.

This addition provides a synchronization point during the boot process
which platform code can leverage, typically when the storage backend
supporting asynchronous file transfer is about to be deactivated.

Change-Id: I3ee27ef2fbfdc19bd75532713966f333ad975861
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88457
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/include/cbfs.h | 2 ++
 src/lib/cbfs.c     | 8 ++++++++
 2 files changed, 10 insertions(+)

diff --git a/src/include/cbfs.h b/src/include/cbfs.h
index f0ae7a80ef..27a285e51d 100644
--- a/src/include/cbfs.h
+++ b/src/include/cbfs.h
@@ -126,6 +126,8 @@ static inline void *cbfs_unverified_area_cbmem_alloc(const char *area, const cha
  * method succeeds or fails.
  */
 void cbfs_preload(const char *name);
+/* Wait for all preloaded CBFS contexts to complete their operations. */
+void cbfs_preload_wait_for_all(void);
 
 /* Removes a previously allocated CBFS mapping. Should try to unmap mappings in strict LIFO
    order where possible, since mapping backends often don't support more complicated cases. */
diff --git a/src/lib/cbfs.c b/src/lib/cbfs.c
index f25030491e..fab64d3b7b 100644
--- a/src/lib/cbfs.c
+++ b/src/lib/cbfs.c
@@ -376,6 +376,14 @@ out:
 	free_cbfs_preload_context(context);
 }
 
+void cbfs_preload_wait_for_all(void)
+{
+	struct cbfs_preload_context *context;
+
+	list_for_each(context, cbfs_preload_context_list, list_node)
+		thread_join(&context->handle);
+}
+
 static struct cbfs_preload_context *find_cbfs_preload_context(const char *name)
 {
 	struct cbfs_preload_context *context;

From d5d633f6071d8c9eb082882866bc456177240078 Mon Sep 17 00:00:00 2001
From: Sowmya Aralguppe <sowmya.aralguppe@intel.com>
Date: Mon, 14 Jul 2025 00:05:21 +0530
Subject: [PATCH 1624/3886] mb/google/ocelot/var/ocelot: Update variant.c

Modify variant configuration to support THC-based touchscreen and
touchpad configurations.

Platform Mapping Document : Rev0p86

BUG=b:394208231
TEST=Build Ocelot and verify it compiles without any error.

Change-Id: I7af8195f76312aa362a6be504b3fec7a81acec06
Signed-off-by: Sowmya Aralguppe <sowmya.aralguppe@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88418
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Pranava Y N <pranavayn@google.com>
---
 src/mainboard/google/ocelot/variants/ocelot/variant.c | 8 ++------
 1 file changed, 2 insertions(+), 6 deletions(-)

diff --git a/src/mainboard/google/ocelot/variants/ocelot/variant.c b/src/mainboard/google/ocelot/variants/ocelot/variant.c
index 2f40fadad1..41ae40b759 100644
--- a/src/mainboard/google/ocelot/variants/ocelot/variant.c
+++ b/src/mainboard/google/ocelot/variants/ocelot/variant.c
@@ -48,19 +48,15 @@ void variant_update_soc_chip_config(struct soc_intel_pantherlake_config *config)
      * | with WOT disabled | with WOT disabled|                 |                            |
      * +===================+==================+=================+============================+
      */
+
 	if (fw_config_probe(FW_CONFIG(TOUCHSCREEN, TOUCHSCREEN_THC_I2C))) {
 		config->thc_mode[0] = THC_HID_I2C_MODE;
 	} else if (fw_config_probe(FW_CONFIG(TOUCHSCREEN, TOUCHSCREEN_THC_SPI))) {
 		config->thc_mode[0] = THC_HID_SPI_MODE;
 	}
 
-	if (fw_config_probe(FW_CONFIG(TOUCHPAD, TOUCHPAD_LPSS_I2C))) {
-		/* touchpad: GPP_F18: GPE0_DW0_18 */
-		if (config->thc_wake_on_touch[1])
-			config->pmc_gpe0_dw0 = GPP_F;
-	} else if (fw_config_probe(FW_CONFIG(TOUCHPAD, TOUCHPAD_THC_I2C))) {
+	if (fw_config_probe(FW_CONFIG(TOUCHPAD, TOUCHPAD_THC_I2C))) {
 		config->thc_mode[1] = THC_HID_I2C_MODE;
-
 		if (fw_config_probe(FW_CONFIG(TOUCHSCREEN, TOUCHSCREEN_NONE)))
 			/* When THC0 is only enabled due to THC1 is enabled, we force THC0
 			 * to I2C mode so that kernel THC I2C driver will find it and put

From b66c8ea3d38872e0e2c9eb416239550da862ebb5 Mon Sep 17 00:00:00 2001
From: Sowmya Aralguppe <sowmya.aralguppe@intel.com>
Date: Thu, 17 Jul 2025 06:52:41 +0530
Subject: [PATCH 1625/3886] mb/google/ocelot/var/ocelot: Remove Bluetooth Audio
 offload

Remove Bluetooth Audio offload to align to fw_config.c

Platform Mapping Document : Rev0p86

BUG=b:394208231
TEST=Build Ocelot and verify it compiles without any error.

Change-Id: I30edbc0a5622e8893469384b853cad323c6ac544
Signed-off-by: Sowmya Aralguppe <sowmya.aralguppe@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88460
Reviewed-by: Pranava Y N <pranavayn@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/google/ocelot/variants/ocelot/variant.c | 5 -----
 1 file changed, 5 deletions(-)

diff --git a/src/mainboard/google/ocelot/variants/ocelot/variant.c b/src/mainboard/google/ocelot/variants/ocelot/variant.c
index 41ae40b759..f4f1fb33f3 100644
--- a/src/mainboard/google/ocelot/variants/ocelot/variant.c
+++ b/src/mainboard/google/ocelot/variants/ocelot/variant.c
@@ -20,11 +20,6 @@ void variant_update_soc_chip_config(struct soc_intel_pantherlake_config *config)
 			fw_config_probe(FW_CONFIG(WIFI, WIFI_CNVI_7))) {
 		config->cnvi_wifi_core = true;
 		config->cnvi_bt_core = true;
-
-		if (fw_config_probe(FW_CONFIG(AUDIO, AUDIO_ALC721_SNDW))) {
-			printk(BIOS_INFO, "BT audio offload configured.\n");
-			config->cnvi_bt_audio_offload = true;
-		}
 	}
 
     /* Touchscreen and touchpad WOT support:

From e050e2fbfca9f47c4da313f38f97efefde1b8051 Mon Sep 17 00:00:00 2001
From: Sowmya Aralguppe <sowmya.aralguppe@intel.com>
Date: Thu, 17 Jul 2025 07:59:43 +0530
Subject: [PATCH 1626/3886] mb/google/ocelot/var/ocelot: Remove irrelevant
 comment

This patch removes comments that are not applicable when aligned to
fw_config.c

Platform Mapping Document : Rev0p86

BUG=b:394208231
TEST=Build Ocelot and verify it compiles without any error.

Change-Id: Id258b4e89c522ec438a74a9a149388bcfde125d1
Signed-off-by: Sowmya Aralguppe <sowmya.aralguppe@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88462
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Pranava Y N <pranavayn@google.com>
---
 .../google/ocelot/variants/ocelot/variant.c   | 20 +++----------------
 1 file changed, 3 insertions(+), 17 deletions(-)

diff --git a/src/mainboard/google/ocelot/variants/ocelot/variant.c b/src/mainboard/google/ocelot/variants/ocelot/variant.c
index f4f1fb33f3..c2d2bdded5 100644
--- a/src/mainboard/google/ocelot/variants/ocelot/variant.c
+++ b/src/mainboard/google/ocelot/variants/ocelot/variant.c
@@ -22,25 +22,11 @@ void variant_update_soc_chip_config(struct soc_intel_pantherlake_config *config)
 		config->cnvi_bt_core = true;
 	}
 
-    /* Touchscreen and touchpad WOT support:
+	/* Touchscreen and Touchpad WOT support:
      * +===================+==================+=================+============================+
-     * | touchsreen        | touchpad         | PMC_GPE0_DW0    | WOT                        |
+     * | Touchscreen       | Touchpad         | PMC_GPE0_DW0    | WOT                        |
      * +===================+==================+==============================================+
-     * | THC-SPI/THC-I2C   | LPSS-I2C         | GPP_F           | TS, TP                     |
-     * +-------------------+------------------+----------------------------------------------+
-     * | THC-SPI/THC-I2C   | not used or      | GPP_A (default) | TS                         |
-     * |                   | with WOT disabled|                 |                            |
-     * +-------------------+------------------+----------------------------------------------+
-     * | THC-SPI/THC-I2C   | THC-I2C          | GPP_A (default) | TS, TP                     |
-     * +-------------------+------------------+----------------------------------------------+
-     * | LPSS-SPI/LPSS-I2C | LPSS-I2C         | GPP_F           | TS via PMC_GPE0_DW2: GPP_E,|
-     * |                   |                  |                 | TP                         |
-     * +-------------------+------------------+----------------------------------------------+
-     * | LPSS-SPI/LPSS-I2C | not used or      | GPP_A (default) | TS via PMC_GPE0_DW2: GPP_E |
-     * |                   | with WOT disabled|                 |                            |
-     * +-------------------+------------------+----------------------------------------------+
-     * | not used          | not used or      | GPP_A (default) | NA                         |
-     * | with WOT disabled | with WOT disabled|                 |                            |
+     * | THC-SPI/THC-I2C   | THC-I2C          | VGPIO           | TS, TP                     |
      * +===================+==================+=================+============================+
      */
 

From ce88b12420d8f3d0ca8300b0c8a6a67128c09967 Mon Sep 17 00:00:00 2001
From: Pranava Y N <pranavayn@google.com>
Date: Mon, 21 Jul 2025 17:01:41 +0530
Subject: [PATCH 1627/3886] mb/google/ocelot: Set correct TPM I2C bus for all
 ocelot model variants

Set `DRIVER_TPM_I2C_BUS` to 0x01 for all ocelot variants selecting
`BOARD_GOOGLE_MODEL_OCELOT` instead of `BOARD_GOOGLE_OCELOT`. This
ensures that the right I2C Bus is selected for all the variants.

BUG=b:433177132
TEST=Ensure that TPM I2C probing is successful.

```
[INFO ]  Probing TPM I2C: I2C bus 1 version 0x3230322a
[INFO ]  DW I2C bus 1 at 0xfe022000 (400 KHz)
[INFO ]  done! DID_VID 0x504a6666
[INFO ]  TPM ready after 0 ms
```

Change-Id: Ib728eb410fcf2000e5d421d186a321a79b3894b0
Signed-off-by: Pranava Y N <pranavayn@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88513
Reviewed-by: Avi Uday <aviuday@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
---
 src/mainboard/google/ocelot/Kconfig | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/mainboard/google/ocelot/Kconfig b/src/mainboard/google/ocelot/Kconfig
index 304033b26c..53c810345e 100644
--- a/src/mainboard/google/ocelot/Kconfig
+++ b/src/mainboard/google/ocelot/Kconfig
@@ -115,7 +115,7 @@ config DRIVER_TPM_I2C_ADDR
 
 config DRIVER_TPM_I2C_BUS
 	hex
-	default 0x01 if BOARD_GOOGLE_OCELOT
+	default 0x01 if BOARD_GOOGLE_MODEL_OCELOT
 
 config HAVE_SLP_S0_GATE
 	def_bool n

From fbb0738272cc1bad122ce473f71b57c459e5443b Mon Sep 17 00:00:00 2001
From: Jian Tong <tongjian@huaqin.corp-partner.google.com>
Date: Sun, 20 Jul 2025 14:54:31 +0800
Subject: [PATCH 1628/3886] mb/google/brox/var/lotso: Decrease cpu power limits

Based on RPL 15W baseline, PL4 should set to 87W.
Ref: 686872_RPL_UPH_RPL_UH_R_Power_Map_Rev2p4p1.xlsm

BUG=b:404416910
TEST=emerge-brox coreboot chromeos-bootimage
     cbmem -c | grep PL shows PL4=87

Change-Id: Ief8c4e5b119dc334f3b469a046946f95a070b866
Signed-off-by: Jian Tong <tongjian@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88498
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
---
 src/mainboard/google/brox/variants/lotso/overridetree.cb | 2 +-
 src/mainboard/google/brox/variants/lotso/ramstage.c      | 4 ++--
 2 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/src/mainboard/google/brox/variants/lotso/overridetree.cb b/src/mainboard/google/brox/variants/lotso/overridetree.cb
index c6007b1269..f3c8107169 100644
--- a/src/mainboard/google/brox/variants/lotso/overridetree.cb
+++ b/src/mainboard/google/brox/variants/lotso/overridetree.cb
@@ -75,7 +75,7 @@ chip soc/intel/alderlake
 	register "power_limits_config[RPL_P_282_242_142_15W_CORE]" = "{
 		.tdp_pl1_override = 15,
 		.tdp_pl2_override = 25,
-		.tdp_pl4 = 114,
+		.tdp_pl4 = 87,
 	}"
 
 	device domain 0 on
diff --git a/src/mainboard/google/brox/variants/lotso/ramstage.c b/src/mainboard/google/brox/variants/lotso/ramstage.c
index 80276607be..d8de83fb08 100644
--- a/src/mainboard/google/brox/variants/lotso/ramstage.c
+++ b/src/mainboard/google/brox/variants/lotso/ramstage.c
@@ -19,7 +19,7 @@ const struct cpu_power_limits performance_efficient_limits[] = {
 		.pl1_max_power = 15000,
 		.pl2_min_power = 25000,
 		.pl2_max_power = 25000,
-		.pl4_power = 114000
+		.pl4_power = 87000
 	},
 	{
 		.mchid = PCI_DID_INTEL_RPL_P_ID_4,
@@ -28,7 +28,7 @@ const struct cpu_power_limits performance_efficient_limits[] = {
 		.pl1_max_power = 15000,
 		.pl2_min_power = 25000,
 		.pl2_max_power = 25000,
-		.pl4_power = 114000
+		.pl4_power = 87000
 	},
 };
 

From def945f3ba5ff9893f636a92af40fd7595f106c6 Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Sun, 26 Jun 2022 22:26:00 +0100
Subject: [PATCH 1629/3886] soc/intel/apollolake: Measure the IBBL, IBB and OBB
 from the bootblock

Get information about the current Boot Guard implementation, such as
whether it's enabled, the profile and if Measured Boot or Verified
Boot are required.

Then, measure the three individual components of the BIOS.

Tested on the StarLite Mk III where all three components were measured
successfully:
    [DEBUG]  Boot Guard 2.0: Verified Boot: Enforced
    [DEBUG]  Boot Guard 2.0: Measured Boot: Enforced
    [DEBUG]  TXE Hash:
    [DEBUG]  0xfef08f5e: ...
    [DEBUG]  0xfef08f6e: ...
    [DEBUG]  IBBL Hash:
    [DEBUG]  0xfef08f7e: ...
    [DEBUG]  0xfef08f8e: ...
    [DEBUG]  IBB Pointer: Present
    ...
    [DEBUG]  IBB Hash:
    [DEBUG]  0xfef08f9e: ...
    [DEBUG]  0xfef08fae: ...

Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: Ia962ae40b411671e82540b19f3b8680529783711
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65444
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
---
 src/soc/intel/apollolake/bootblock/bootblock.c | 18 ++++++++++++++++++
 1 file changed, 18 insertions(+)

diff --git a/src/soc/intel/apollolake/bootblock/bootblock.c b/src/soc/intel/apollolake/bootblock/bootblock.c
index cb1dd20a2c..6502ec4e51 100644
--- a/src/soc/intel/apollolake/bootblock/bootblock.c
+++ b/src/soc/intel/apollolake/bootblock/bootblock.c
@@ -15,9 +15,11 @@
 #include <intelblocks/pmclib.h>
 #include <intelblocks/tco.h>
 #include <intelblocks/uart.h>
+#include <soc/iomap.h>
 #include <soc/cpu.h>
 #include <soc/loader.h>
 #include <soc/gpio.h>
+#include <soc/measured_boot.h>
 #include <soc/soc_chip.h>
 #include <soc/systemagent.h>
 #include <soc/pci_devs.h>
@@ -42,6 +44,8 @@ static void tpm_enable(void)
 asmlinkage void bootblock_c_entry(uint64_t base_timestamp)
 {
 	pci_devfn_t dev;
+	bool ibb_exists;
+	struct boot_policy_manifest bpm_info;
 
 	bootblock_systemagent_early_init();
 
@@ -54,6 +58,13 @@ asmlinkage void bootblock_c_entry(uint64_t base_timestamp)
 	pci_write_config16(dev, PCI_COMMAND,
 				PCI_COMMAND_IO | PCI_COMMAND_MASTER);
 
+	/*
+	 * Check the status of the BPM, and measured the IBB and OBB
+	 * if required. Returns 1 if IBB exists.
+	 */
+	if (CONFIG(IFWI_MEASURED_BOOT))
+		ibb_exists = fetch_pre_rbp_data(&bpm_info);
+
 	enable_rtc_upper_bank();
 
 	if (CONFIG(IFWI_IBBM_LOAD)) {
@@ -61,6 +72,13 @@ asmlinkage void bootblock_c_entry(uint64_t base_timestamp)
 		flush_l1d_to_l2();
 	}
 
+	/*
+	 * If the IBB exists, measure it after it has been loaded via
+	 * the CSEs RBP.
+	 */
+	if (CONFIG(IFWI_MEASURED_BOOT) && ibb_exists)
+		fetch_post_rbp_data(&bpm_info);
+
 	/* Call lib/bootblock.c main */
 	bootblock_main_with_basetime(base_timestamp);
 }

From dd19f6bc5a2b161902c7e358d65906ea8da95c93 Mon Sep 17 00:00:00 2001
From: Jakub Czapiga <czapiga@google.com>
Date: Thu, 24 Apr 2025 18:15:06 +0000
Subject: [PATCH 1630/3886] util/cbmem: Extract devmem and common code to
 separate files

Extract devmem-specific code to a separate file providing unified API.
Move hexdump() and cbmem_print_entry() to common.c.
Create common function for getting coreboot table entries. This can be
adjusted later to use higher-level API that selects appropriate backend.

BUG=b:391874512
TEST=cbmem -l; cbmem -x; cbmem -r 434f4e53; cbmem -t

Change-Id: Ic11f0659833e03324f6909fa3c1d62c36988b7b7
Signed-off-by: Jakub Czapiga <czapiga@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86557
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
---
 util/cbmem/Makefile     |   2 +-
 util/cbmem/cbmem.c      | 873 +++++-----------------------------------
 util/cbmem/cbmem_util.h |  96 +++++
 util/cbmem/devmem_drv.c | 675 +++++++++++++++++++++++++++++++
 4 files changed, 866 insertions(+), 780 deletions(-)
 create mode 100644 util/cbmem/cbmem_util.h
 create mode 100644 util/cbmem/devmem_drv.c

diff --git a/util/cbmem/Makefile b/util/cbmem/Makefile
index 0c88aebbbe..1376b04d52 100644
--- a/util/cbmem/Makefile
+++ b/util/cbmem/Makefile
@@ -14,7 +14,7 @@ CFLAGS   += -Wall -Wextra -Wmissing-prototypes -Wshadow $(WERROR)
 CPPFLAGS += -I . -I $(ROOT)/commonlib/include -I $(ROOT)/commonlib/bsd/include
 CPPFLAGS += -include $(ROOT)/commonlib/bsd/include/commonlib/bsd/compiler.h
 
-OBJS = $(PROGRAM).o $(COMMONLIB)/bsd/ipchksum.o
+OBJS = $(PROGRAM).o devmem_drv.o $(COMMONLIB)/bsd/ipchksum.o
 
 all: $(PROGRAM)
 
diff --git a/util/cbmem/cbmem.c b/util/cbmem/cbmem.c
index f80d334962..93a58d5999 100644
--- a/util/cbmem/cbmem.c
+++ b/util/cbmem/cbmem.c
@@ -7,519 +7,32 @@
 #include <string.h>
 #include <unistd.h>
 #include <getopt.h>
-#include <dirent.h>
 #include <errno.h>
 #include <fcntl.h>
 #include <ctype.h>
 #include <arpa/inet.h>
-#include <sys/types.h>
 #include <sys/stat.h>
-#include <sys/mman.h>
 #include <libgen.h>
 #include <assert.h>
 #include <regex.h>
 #include <commonlib/bsd/cbmem_id.h>
-#include <commonlib/bsd/ipchksum.h>
+#include <commonlib/bsd/helpers.h>
 #include <commonlib/bsd/tpm_log_defs.h>
 #include <commonlib/loglevel.h>
 #include <commonlib/timestamp_serialized.h>
 #include <commonlib/tpm_log_serialized.h>
 #include <commonlib/coreboot_tables.h>
 
-#ifdef __OpenBSD__
-#include <sys/param.h>
-#include <sys/sysctl.h>
-#endif
-
 #if defined(__i386__) || defined(__x86_64__)
 #include <x86intrin.h>
 #endif
 
-struct mapping {
-	void *virt;
-	size_t offset;
-	size_t virt_size;
-	unsigned long long phys;
-	size_t size;
-};
+#include "cbmem_util.h"
 
 #define CBMEM_VERSION "1.1"
 
-/* verbose output? */
-static int verbose = 0;
-#define debug(x...) if(verbose) printf(x)
-
-/* File handle used to access /dev/mem */
-static int mem_fd;
-static struct mapping lbtable_mapping;
-
-static void die(const char *msg)
-{
-	if (msg)
-		fputs(msg, stderr);
-	exit(1);
-}
-
-static unsigned long long system_page_size(void)
-{
-	static unsigned long long page_size;
-
-	if (!page_size)
-		page_size = getpagesize();
-
-	return page_size;
-}
-
-static inline size_t size_to_mib(size_t sz)
-{
-	return sz >> 20;
-}
-
-/* Return mapping of physical address requested. */
-static void *mapping_virt(const struct mapping *mapping)
-{
-	char *v = mapping->virt;
-
-	if (v == NULL)
-		return NULL;
-
-	return v + mapping->offset;
-}
-
-/* Returns virtual address on success, NULL on error. mapping is filled in. */
-static void *map_memory_with_prot(struct mapping *mapping,
-				  unsigned long long phys, size_t sz, int prot)
-{
-	void *v;
-	unsigned long long page_size;
-
-	page_size = system_page_size();
-
-	mapping->virt = NULL;
-	mapping->offset = phys % page_size;
-	mapping->virt_size = sz + mapping->offset;
-	mapping->size = sz;
-	mapping->phys = phys;
-
-	if (size_to_mib(mapping->virt_size) == 0) {
-		debug("Mapping %zuB of physical memory at 0x%llx (requested 0x%llx).\n",
-			mapping->virt_size, phys - mapping->offset, phys);
-	} else {
-		debug("Mapping %zuMB of physical memory at 0x%llx (requested 0x%llx).\n",
-			size_to_mib(mapping->virt_size), phys - mapping->offset,
-			phys);
-	}
-
-	v = mmap(NULL, mapping->virt_size, prot, MAP_SHARED, mem_fd,
-			phys - mapping->offset);
-
-	if (v == MAP_FAILED) {
-		debug("Mapping failed %zuB of physical memory at 0x%llx.\n",
-			mapping->virt_size, phys - mapping->offset);
-		return NULL;
-	}
-
-	mapping->virt = v;
-
-	if (mapping->offset != 0)
-		debug("  ... padding virtual address with 0x%zx bytes.\n",
-			mapping->offset);
-
-	return mapping_virt(mapping);
-}
-
-/* Convenience helper for the common case of read-only mappings. */
-static const void *map_memory(struct mapping *mapping, unsigned long long phys,
-			      size_t sz)
-{
-	return map_memory_with_prot(mapping, phys, sz, PROT_READ);
-}
-
-
-/* Returns 0 on success, < 0 on error. mapping is cleared if successful. */
-static int unmap_memory(struct mapping *mapping)
-{
-	if (mapping->virt == NULL)
-		return -1;
-
-	munmap(mapping->virt, mapping->virt_size);
-	mapping->virt = NULL;
-	mapping->offset = 0;
-	mapping->virt_size = 0;
-
-	return 0;
-}
-
-/* Return size of physical address mapping requested. */
-static size_t mapping_size(const struct mapping *mapping)
-{
-	if (mapping->virt == NULL)
-		return 0;
-
-	return mapping->size;
-}
-
-/*
- * Some architectures map /dev/mem memory in a way that doesn't support
- * unaligned accesses. Most normal libc memcpy()s aren't safe to use in this
- * case, so build our own which makes sure to never do unaligned accesses on
- * *src (*dest is fine since we never map /dev/mem for writing).
- */
-static void *aligned_memcpy(void *dest, const void *src, size_t n)
-{
-	uint8_t *d = dest;
-	const volatile uint8_t *s = src;	/* volatile to prevent optimization */
-
-	while ((uintptr_t)s & (sizeof(size_t) - 1)) {
-		if (n-- == 0)
-			return dest;
-		*d++ = *s++;
-	}
-
-	while (n >= sizeof(size_t)) {
-		*(size_t *)d = *(const volatile size_t *)s;
-		d += sizeof(size_t);
-		s += sizeof(size_t);
-		n -= sizeof(size_t);
-	}
-
-	while (n-- > 0)
-		*d++ = *s++;
-
-	return dest;
-}
-
-/* This is a work-around for a nasty problem introduced by initially having
- * pointer sized entries in the lb_cbmem_ref structures. This caused problems
- * on 64bit x86 systems because coreboot is 32bit on those systems.
- * When the problem was found, it was corrected, but there are a lot of
- * systems out there with a firmware that does not produce the right
- * lb_cbmem_ref structure. Hence we try to autocorrect this issue here.
- */
-static struct lb_cbmem_ref parse_cbmem_ref(const struct lb_cbmem_ref *cbmem_ref)
-{
-	struct lb_cbmem_ref ret;
-
-	aligned_memcpy(&ret, cbmem_ref, sizeof(ret));
-
-	if (cbmem_ref->size < sizeof(*cbmem_ref))
-		ret.cbmem_addr = (uint32_t)ret.cbmem_addr;
-
-	debug("      cbmem_addr = %" PRIx64 "\n", ret.cbmem_addr);
-
-	return ret;
-}
-
-static uint32_t cbmem_id_to_lb_tag(uint32_t tag)
-{
-	/* Minimal subset. Expand based on the CBMEM to coreboot table
-	   records mapping in lib/coreboot_table.c */
-	switch (tag) {
-	case CBMEM_ID_TIMESTAMP:
-		return LB_TAG_TIMESTAMPS;
-	case CBMEM_ID_CONSOLE:
-		return LB_TAG_CBMEM_CONSOLE;
-	case CBMEM_ID_TPM_CB_LOG:
-		return LB_TAG_TPM_CB_LOG;
-	}
-	return LB_TAG_UNUSED;
-}
-
-struct cbmem_console {
-	uint32_t size;
-	uint32_t cursor;
-	uint8_t body[];
-} __packed;
-
-#define CBMC_CURSOR_MASK ((1 << 28) - 1)
-#define CBMC_OVERFLOW    (1 << 31)
-
-
-/* Find the first cbmem entry filling in the details. */
-static int find_cbmem_entry(uint32_t id, uint64_t *addr, size_t *size)
-{
-	const uint8_t *table;
-	size_t offset = 0;
-	const uint32_t legacy_tag = cbmem_id_to_lb_tag(id);
-	struct lb_cbmem_ref *ref = NULL;
-
-	table = mapping_virt(&lbtable_mapping);
-
-	if (table == NULL)
-		return -1;
-
-	const struct lb_record *lbr = NULL;
-	while (offset < mapping_size(&lbtable_mapping)) {
-		lbr = (const void *)(table + offset);
-		offset += lbr->size;
-
-		/* Store coreboot table entry for later if CBMEM entry does not exist.
-		   CBMEM entry stores size including the reserved area, so prefer it,
-		   so more potential data and/or space is available. */
-		if (legacy_tag != LB_TAG_UNUSED && lbr->tag == legacy_tag)
-			ref = (struct lb_cbmem_ref *)lbr;
-
-		if (lbr->tag != LB_TAG_CBMEM_ENTRY)
-			continue;
-
-		struct lb_cbmem_entry lbe;
-		aligned_memcpy(&lbe, lbr, sizeof(lbe));
-		if (lbe.id != id)
-			continue;
-
-		*addr = lbe.address;
-		*size = lbe.entry_size;
-		return 0;
-	}
-
-	/* No mapping and/or no potential reference means that
-	   the requested entry does not exit. */
-	if (legacy_tag == LB_TAG_UNUSED || ref == NULL)
-		return -1;
-
-	debug("Found coreboot table record equivalent of CBMEM entry id: %#x, tag: %#x\n", id,
-	      legacy_tag);
-
-	const struct lb_cbmem_ref lbc = parse_cbmem_ref(ref);
-	size_t header_map_size = 0;
-
-	/* Process legacy coreboot table entries */
-	switch (lbc.tag) {
-	case LB_TAG_TIMESTAMPS:
-		header_map_size = sizeof(struct timestamp_table);
-		break;
-	case LB_TAG_CBMEM_CONSOLE:
-		header_map_size = sizeof(struct cbmem_console);
-		break;
-	case LB_TAG_TPM_CB_LOG:
-		header_map_size = sizeof(struct tpm_cb_log_table);
-		break;
-	}
-
-	struct mapping entry_mapping;
-	const void *entry_header = NULL;
-
-	entry_header = map_memory(&entry_mapping, lbc.cbmem_addr, header_map_size);
-	if (!entry_header) {
-		fprintf(stderr, "Unable to map header for coreboot table entry id: %#x\n",
-			legacy_tag);
-		abort();
-	}
-
-	*addr = lbc.cbmem_addr;
-
-	switch (legacy_tag) {
-	case LB_TAG_TIMESTAMPS: {
-		const struct timestamp_table *tst_p = entry_header;
-		*size = sizeof(*tst_p) + tst_p->num_entries * sizeof(tst_p->entries[0]);
-		break;
-	}
-	case LB_TAG_CBMEM_CONSOLE: {
-		const struct cbmem_console *console_p = entry_header;
-		*size = sizeof(*console_p) + console_p->size;
-		break;
-	}
-	case LB_TAG_TPM_CB_LOG: {
-		const struct tpm_cb_log_table *tclt_p = entry_header;
-		*size = sizeof(*tclt_p) + tclt_p->num_entries * sizeof(tclt_p->entries[0]);
-		break;
-	}
-	}
-
-	unmap_memory(&entry_mapping);
-
-	return 0;
-}
-
-/**
- * Returns pointer to allocated buffer and size of the buffer in parameters.
- * Returns zero on success.
- * free() buffer after use.
- */
-static int get_cbmem_entry(uint32_t id, uint8_t **buf_out, size_t *size_out)
-{
-	uint64_t addr;
-	size_t size;
-	struct mapping cbmem_mapping;
-
-	if (find_cbmem_entry(id, &addr, &size)) {
-		debug("CBMEM entry not found. CBMEM id: %#x\n", id);
-		return -1;
-	}
-
-	const uint8_t *buf = map_memory(&cbmem_mapping, addr, size);
-	if (!buf) {
-		fprintf(stderr, "Unable to map CBMEM entry id: %#x, size: %zu\n", id, size);
-		abort();
-	}
-
-	*buf_out = malloc(size);
-	if (!*buf_out) {
-		unmap_memory(&cbmem_mapping);
-		fprintf(stderr,
-			"Unable to allocate memory for CBMEM entry id: %#x, size: %zu\n", id,
-			size);
-		abort();
-	}
-
-	aligned_memcpy(*buf_out, buf, size);
-	unmap_memory(&cbmem_mapping);
-	*size_out = size;
-	return 0;
-}
-
-/* Return < 0 on error, 0 on success. */
-static int parse_cbtable(uint64_t address, size_t table_size)
-{
-	const uint8_t *buf;
-	struct mapping header_mapping;
-	size_t req_size;
-	size_t i;
-
-	req_size = table_size;
-	/* Default to 4 KiB search space. */
-	if (req_size == 0)
-		req_size = 4 * 1024;
-
-	debug("Looking for coreboot table at %" PRIx64 " %zd bytes.\n", address, req_size);
-
-	buf = map_memory(&header_mapping, address, req_size);
-
-	if (!buf)
-		return -1;
-
-	/* look at every 16 bytes */
-	for (i = 0; i <= req_size - sizeof(struct lb_header); i += 16) {
-		const struct lb_header *lbh;
-		struct mapping table_mapping;
-
-		lbh = (const struct lb_header *)&buf[i];
-		if (memcmp(lbh->signature, "LBIO", sizeof(lbh->signature)) ||
-		    !lbh->header_bytes ||
-		    ipchksum(lbh, sizeof(*lbh))) {
-			continue;
-		}
-
-		/* Map in the whole table to parse. */
-		if (!map_memory(&table_mapping, address + i + lbh->header_bytes,
-				 lbh->table_bytes)) {
-			debug("Couldn't map in table\n");
-			continue;
-		}
-
-		if (ipchksum(mapping_virt(&table_mapping), lbh->table_bytes) !=
-		    lbh->table_checksum) {
-			debug("Signature found, but wrong checksum.\n");
-			unmap_memory(&table_mapping);
-			continue;
-		}
-
-		debug("Found at %#" PRIx64 "\n", address + i);
-
-		const struct lb_record *lbr_p;
-		const uint8_t *lbtable = mapping_virt(&table_mapping);
-
-		for (size_t offset = 0; offset < lbh->table_bytes; offset += lbr_p->size) {
-			lbr_p = (const struct lb_record *)&lbtable[offset];
-			debug("  coreboot table entry 0x%02x\n", lbr_p->tag);
-
-			if (lbr_p->tag != LB_TAG_FORWARD)
-				continue;
-
-			/* This is a forwarding entry. Repeat the search at the new address. */
-			struct lb_forward lbf_p = *(const struct lb_forward *)lbr_p;
-			debug("    Found forwarding entry.\n");
-
-			const uint64_t next_addr = lbf_p.forward;
-			unmap_memory(&header_mapping);
-			unmap_memory(&table_mapping);
-
-			return parse_cbtable(next_addr, 0);
-		}
-
-		debug("correct coreboot table found.\n");
-		unmap_memory(&header_mapping);
-		lbtable_mapping = table_mapping;
-
-		return 0;
-	}
-
-	unmap_memory(&header_mapping);
-
-	return -1;
-}
-
-static void lb_table_get_entry(uint32_t tag, uint8_t **buf_out, size_t *size_out)
-{
-	const struct lb_record *lbr_p;
-	const uint8_t *lbtable_raw;
-	size_t table_size;
-	bool tag_found = false;
-
-	if (get_cbmem_entry(CBMEM_ID_CBTABLE, (uint8_t **)&lbtable_raw, &table_size)) {
-		fprintf(stderr, "coreboot table not found.\n");
-		abort();
-	}
-
-	const struct lb_header *lbh = (const struct lb_header *)lbtable_raw;
-
-	for (size_t i = 0; i < lbh->table_bytes; i += lbr_p->size) {
-		lbr_p = (const struct lb_record *)(&lbtable_raw[lbh->header_bytes + i]);
-		if (lbr_p->tag == tag) {
-			tag_found = true;
-			break;
-		}
-	}
-
-	if (!tag_found) {
-		fprintf(stderr, "coreboot table entry %#x not found.\n", tag);
-		free((void *)lbtable_raw);
-		abort();
-	}
-
-	debug("coreboot table entry %#x found.\n", tag);
-
-	*buf_out = malloc(lbr_p->size);
-	if (!*buf_out) {
-		fprintf(stderr,
-			"Unable to allocate memory for coreboot table entry %#x, size: %d\n",
-			tag, lbr_p->size);
-		free((void *)lbtable_raw);
-		abort();
-	}
-	memcpy(*buf_out, lbr_p, lbr_p->size);
-	*size_out = lbr_p->size;
-	free((void *)lbtable_raw);
-}
-
-
-/**
- * Returns mapping, mapped buffer pointer and its size by parameters.
- * Returns zero on success.
- * unmap_mempry() after use.
- */
-static int map_cbmem_entry_rw(uint32_t id, struct mapping *mapping, uint8_t **buf_out,
-			       size_t *size_out)
-{
-	uint64_t addr;
-	size_t size;
-
-	if (find_cbmem_entry(id, &addr, &size)) {
-		debug("CBMEM entry not found. CBMEM id: %#x\n", id);
-		return -1;
-	}
-
-	*buf_out = map_memory_with_prot(mapping, addr, size, PROT_READ | PROT_WRITE);
-	if (!*buf_out) {
-		fprintf(stderr,
-			"Unable to map CBMEM entry id: %#x, size: %zu for read-write access.\n",
-			id, size);
-		abort();
-	}
-
-	*size_out = size;
-	return 0;
-}
+/* Global verbosity level for debug() macro. */
+int cbmem_util_verbose;
 
 #if defined(linux) && (defined(__i386__) || defined(__x86_64__))
 /*
@@ -620,6 +133,46 @@ static void print_norm(uint64_t v)
 	}
 }
 
+#if defined(__i386__) || defined(__x86_64__)
+static void cbmem_get_lb_table_entry(uint32_t tag, uint8_t **buf_out, size_t *size_out)
+{
+	const struct lb_record *lbr_p;
+	const uint8_t *lbtable_raw;
+	bool tag_found = false;
+
+	if (!cbmem_devmem_get_cbmem_entry(CBMEM_ID_CBTABLE, (uint8_t **)&lbtable_raw, NULL,
+					  NULL))
+		die("coreboot table not found.\n");
+
+	const struct lb_header *lbh = (const struct lb_header *)lbtable_raw;
+
+	for (size_t i = 0; i < lbh->table_bytes - sizeof(struct lb_record); i += lbr_p->size) {
+		lbr_p = (const struct lb_record *)(&lbtable_raw[lbh->header_bytes + i]);
+		if (lbr_p->tag == tag) {
+			tag_found = true;
+			break;
+		}
+	}
+
+	if (!tag_found) {
+		free((void *)lbtable_raw);
+		die("coreboot table entry %#x not found.\n", tag);
+	}
+
+	debug("coreboot table entry %#x found.\n", tag);
+
+	*buf_out = malloc(lbr_p->size);
+	if (!*buf_out) {
+		free((void *)lbtable_raw);
+		die("Unable to allocate memory for coreboot table entry %#x, size: %d\n", tag,
+		    lbr_p->size);
+	}
+	memcpy(*buf_out, lbr_p, lbr_p->size);
+	*size_out = lbr_p->size;
+	free((void *)lbtable_raw);
+}
+#endif /* defined(__i386__) || defined(__x86_64__) */
+
 static uint64_t timestamp_get(uint64_t table_tick_freq_mhz)
 {
 #if defined(__i386__) || defined(__x86_64__)
@@ -631,7 +184,7 @@ static uint64_t timestamp_get(uint64_t table_tick_freq_mhz)
 	if (!table_tick_freq_mhz)
 		return tsc;
 
-	lb_table_get_entry(LB_TAG_TSC_INFO, (uint8_t **)&tsc_info, &size);
+	cbmem_get_lb_table_entry(LB_TAG_TSC_INFO, (uint8_t **)&tsc_info, &size);
 
 	const uint32_t tsc_freq_khz = tsc_info->freq_khz;
 
@@ -784,10 +337,8 @@ static void dump_timestamps(enum timestamps_print_type output_type)
 	uint64_t prev_stamp = 0;
 	uint64_t total_time = 0;
 
-	if (get_cbmem_entry(CBMEM_ID_TIMESTAMP, (uint8_t **)&tst_p, &size)) {
-		fprintf(stderr, "Timestamps not found.\n");
-		abort();
-	}
+	if (!cbmem_devmem_get_cbmem_entry(CBMEM_ID_TIMESTAMP, (uint8_t **)&tst_p, &size, NULL))
+		die("Timestamps not found.\n");
 
 	timestamp_set_tick_freq(tst_p->tick_freq_mhz);
 
@@ -884,14 +435,10 @@ static void dump_timestamps(enum timestamps_print_type output_type)
 static void timestamp_add_now(uint32_t timestamp_id)
 {
 	struct timestamp_table *tst_p;
-	struct mapping timestamp_mapping;
 	size_t tst_size;
 
-	if (map_cbmem_entry_rw(CBMEM_ID_TIMESTAMP, &timestamp_mapping, (uint8_t **)&tst_p,
-			       &tst_size)) {
-		fprintf(stderr, "Unable to find timestamps.\n");
-		abort();
-	}
+	if (!cbmem_devmem_get_cbmem_entry(CBMEM_ID_TIMESTAMP, (uint8_t **)&tst_p, &tst_size, NULL))
+		die("Unable to find timestamps.\n");
 
 	/*
 	 * Note that coreboot sizes the cbmem entry in the table according to
@@ -907,7 +454,9 @@ static void timestamp_add_now(uint32_t timestamp_id)
 		tst_p->num_entries += 1;
 	}
 
-	unmap_memory(&timestamp_mapping);
+	if (!cbmem_devmem_write_cbmem_entry(CBMEM_ID_TIMESTAMP, (uint8_t *)tst_p, tst_size))
+		die("Unable to write timestamps.\n");
+	free((uint8_t *)tst_p);
 }
 
 static bool can_print(const uint8_t *data, size_t len)
@@ -1124,12 +673,9 @@ static void dump_tpm_std_log(void *buf)
 static void dump_tpm_cb_log(void)
 {
 	const struct tpm_cb_log_table *tclt_p;
-	size_t tclt_size;
 
-	if (get_cbmem_entry(CBMEM_ID_TPM_CB_LOG, (uint8_t **)&tclt_p, &tclt_size)) {
-		fprintf(stderr, "coreboot TPM log not found.\n");
-		abort();
-	}
+	if (!cbmem_devmem_get_cbmem_entry(CBMEM_ID_TPM_CB_LOG, (uint8_t **)&tclt_p, NULL, NULL))
+		die("coreboot TPM log not found.\n");
 
 	printf("coreboot TPM log:\n\n");
 
@@ -1141,16 +687,15 @@ static void dump_tpm_cb_log(void)
 		printf(" %s [%s]\n", tce->digest_type, tce->name);
 	}
 
-	free((void *)tclt_p);
+	free((uint8_t *)tclt_p);
 }
 
 static void dump_tpm_log(void)
 {
 	uint8_t *buf;
-	size_t size;
 
-	if (!get_cbmem_entry(CBMEM_ID_TCPA_TCG_LOG, &buf, &size) ||
-	    !get_cbmem_entry(CBMEM_ID_TPM2_TCG_LOG, &buf, &size)) {
+	if (cbmem_devmem_get_cbmem_entry(CBMEM_ID_TCPA_TCG_LOG, &buf, NULL, NULL) ||
+	    cbmem_devmem_get_cbmem_entry(CBMEM_ID_TPM2_TCG_LOG, &buf, NULL, NULL)) {
 		dump_tpm_std_log(buf);
 		free(buf);
 	} else
@@ -1192,12 +737,9 @@ static void dump_console(enum console_print_type type, int max_loglevel, int pri
 	const struct cbmem_console *console_p;
 	char *console_c;
 	size_t size, cursor, previous;
-	size_t console_buf_size;
 
-	if (get_cbmem_entry(CBMEM_ID_CONSOLE, (uint8_t **)&console_p, &console_buf_size)) {
-		fprintf(stderr, "CBMEM console not found.\n");
-		abort();
-	}
+	if (!cbmem_devmem_get_cbmem_entry(CBMEM_ID_CONSOLE, (uint8_t **)&console_p, NULL, NULL))
+		die("CBMEM console not found.\n");
 
 	cursor = console_p->cursor & CBMC_CURSOR_MASK;
 	if (!(console_p->cursor & CBMC_OVERFLOW) && cursor < console_p->size)
@@ -1207,9 +749,8 @@ static void dump_console(enum console_print_type type, int max_loglevel, int pri
 
 	console_c = malloc(size + 1);
 	if (!console_c) {
-		fprintf(stderr, "Not enough memory for console.\n");
-		free((void *)console_p);
-		abort();
+		free((uint8_t *)console_p);
+		die("Not enough memory for console.\n");
 	}
 	console_c[size] = '\0';
 
@@ -1297,10 +838,9 @@ static void dump_console(enum console_print_type type, int max_loglevel, int pri
 		printf(BIOS_LOG_ESCAPE_RESET);
 
 	free(console_c);
-	free((void *)console_p);
+	free((uint8_t *)console_p);
 }
 
-/* Hexdump provided buffer using start_address as an offset in the output. */
 static void hexdump(const uintptr_t start_address, const uint8_t *buf, const int length)
 {
 	int i;
@@ -1331,39 +871,18 @@ static void hexdump(const uintptr_t start_address, const uint8_t *buf, const int
 	}
 }
 
+static bool hexdump_handler(const uint32_t id, const uint64_t physical_address, const uint8_t *buf,
+		 const size_t size, void *data)
+{
+	(void)id;
+	(void)data;
+	hexdump(physical_address, buf, size);
+	return false;
+}
+
 static void dump_cbmem_hex(void)
 {
-	struct mapping cbmem_mapping;
-	struct lb_memory *memory;
-	const uint8_t *buf = NULL;
-	size_t size = 0;
-
-	lb_table_get_entry(LB_TAG_MEMORY, (uint8_t **)&memory, &size);
-
-	if (!memory)
-		die("No memory entries available.\n");
-
-	const int entries = (memory->size - sizeof(*memory)) / sizeof(memory->map[0]);
-	/* First from the end is CBMEM */
-	for (int i = entries - 1; i >= 0; --i) {
-		if (memory->map[i].type != LB_MEM_TABLE)
-			continue;
-
-		buf = map_memory(&cbmem_mapping, memory->map[i].start, memory->map[i].size);
-		if (!buf)
-			die("Unable to map CBMEM area memory.\n");
-
-		size = memory->map[i].size;
-		break;
-	}
-
-	if (!buf)
-		die("Unable to find CBMEM area memory entry.\n");
-
-	hexdump(cbmem_mapping.phys, buf, size);
-
-	unmap_memory(&cbmem_mapping);
-	free(memory);
+	cbmem_devmem_foreach_cbmem_entry(hexdump_handler, NULL, true);
 }
 
 static void dump_cbmem_raw(unsigned int id)
@@ -1371,10 +890,8 @@ static void dump_cbmem_raw(unsigned int id)
 	uint8_t *buf;
 	size_t size;
 
-	if (get_cbmem_entry(id, &buf, &size)) {
-		fprintf(stderr, "cbmem entry id: %#x not found.\n", id);
-		abort();
-	}
+	if (!cbmem_devmem_get_cbmem_entry(id, &buf, &size, NULL))
+		die("cbmem entry id: %#x not found.\n", id);
 
 	fwrite(buf, 1, size, stdout);
 
@@ -1421,35 +938,27 @@ static void cbmem_print_entry(int n, uint32_t id, uint64_t base, uint64_t size)
 	printf(" %08" PRIx64 "\n", size);
 }
 
+static bool toc_handler(const uint32_t id, const uint64_t physical_address, const uint8_t *buf,
+		 const size_t size, void *data)
+{
+	(void)buf;
+	int *i = data;
+
+	cbmem_print_entry(*i, id, physical_address, size);
+
+	(*i)++;
+
+	return false;
+}
+
 static void dump_cbmem_toc(void)
 {
 	int i = 0;
-	const uint8_t *table = NULL;
-	size_t table_size = 0;
-
-	if (get_cbmem_entry(CBMEM_ID_CBTABLE, (uint8_t **)&table, &table_size)) {
-		fprintf(stderr, "coreboot table not found.\n");
-		abort();
-	}
-
-	const struct lb_header *lbh = (const struct lb_header *)table;
 
 	printf("CBMEM table of contents:\n");
 	printf("    %-20s  %-8s  %-8s  %-8s\n", "NAME", "ID", "START", "LENGTH");
 
-	const struct lb_record *lbr = NULL;
-	for (size_t offset = lbh->header_bytes;
-	     offset < lbh->table_bytes + lbh->header_bytes - sizeof(struct lb_cbmem_entry);
-	     offset += lbr->size) {
-		lbr = (const struct lb_record *)&table[offset];
-
-		if (lbr->tag != LB_TAG_CBMEM_ENTRY)
-			continue;
-
-		const struct lb_cbmem_entry *lbe = (const struct lb_cbmem_entry *)lbr;
-		cbmem_print_entry(i, lbe->id, lbe->address, lbe->entry_size);
-		i++;
-	}
+	cbmem_devmem_foreach_cbmem_entry(toc_handler, &i, false);
 }
 
 #define COVERAGE_MAGIC 0x584d4153
@@ -1483,20 +992,11 @@ static void dump_coverage(void)
 {
 	uint64_t start;
 	uint8_t *coverage;
-	size_t size;
 	unsigned long phys_offset;
 #define phys_to_virt(x) ((void *)(unsigned long)(x) + phys_offset)
 
-	if (get_cbmem_entry(CBMEM_ID_COVERAGE, &coverage, &size)) {
-		fprintf(stderr, "No coverage information found\n");
-		return;
-	}
-
-	// Physical address is needed for pointer translation
-	if (find_cbmem_entry(CBMEM_ID_COVERAGE, &start, &size)) {
-		fprintf(stderr, "No coverage information found\n");
-		return;
-	}
+	if (!cbmem_devmem_get_cbmem_entry(CBMEM_ID_COVERAGE, &coverage, NULL, &start))
+		die("No coverage information found\n");
 
 	/* Map coverage area */
 	phys_offset = (unsigned long)coverage - (unsigned long)start;
@@ -1576,121 +1076,6 @@ static void print_usage(const char *name, int exit_code)
 	exit(exit_code);
 }
 
-#if defined(__arm__) || defined(__aarch64__)
-static void dt_update_cells(const char *name, int *addr_cells_ptr,
-			    int *size_cells_ptr)
-{
-	if (*addr_cells_ptr >= 0 && *size_cells_ptr >= 0)
-		return;
-
-	int buffer;
-	size_t nlen = strlen(name);
-	char *prop = alloca(nlen + sizeof("/#address-cells"));
-	strcpy(prop, name);
-
-	if (*addr_cells_ptr < 0) {
-		strcpy(prop + nlen, "/#address-cells");
-		int fd = open(prop, O_RDONLY);
-		if (fd < 0 && errno != ENOENT) {
-			perror(prop);
-		} else if (fd >= 0) {
-			if (read(fd, &buffer, sizeof(int)) < 0)
-				perror(prop);
-			else
-				*addr_cells_ptr = ntohl(buffer);
-			close(fd);
-		}
-	}
-
-	if (*size_cells_ptr < 0) {
-		strcpy(prop + nlen, "/#size-cells");
-		int fd = open(prop, O_RDONLY);
-		if (fd < 0 && errno != ENOENT) {
-			perror(prop);
-		} else if (fd >= 0) {
-			if (read(fd, &buffer, sizeof(int)) < 0)
-				perror(prop);
-			else
-				*size_cells_ptr = ntohl(buffer);
-			close(fd);
-		}
-	}
-}
-
-static char *dt_find_compat(const char *parent, const char *compat,
-			    int *addr_cells_ptr, int *size_cells_ptr)
-{
-	char *ret = NULL;
-	struct dirent *entry;
-	DIR *dir;
-
-	if (!(dir = opendir(parent))) {
-		perror(parent);
-		return NULL;
-	}
-
-	/* Loop through all files in the directory (DT node). */
-	while ((entry = readdir(dir))) {
-		/* We only care about compatible props or subnodes. */
-		if (entry->d_name[0] == '.' || !((entry->d_type & DT_DIR) ||
-		    !strcmp(entry->d_name, "compatible")))
-			continue;
-
-		/* Assemble the file name (on the stack, for speed). */
-		size_t plen = strlen(parent);
-		char *name = alloca(plen + strlen(entry->d_name) + 2);
-
-		strcpy(name, parent);
-		name[plen] = '/';
-		strcpy(name + plen + 1, entry->d_name);
-
-		/* If it's a subnode, recurse. */
-		if (entry->d_type & DT_DIR) {
-			ret = dt_find_compat(name, compat, addr_cells_ptr,
-					     size_cells_ptr);
-
-			/* There is only one matching node to find, abort. */
-			if (ret) {
-				/* Gather cells values on the way up. */
-				dt_update_cells(parent, addr_cells_ptr,
-						size_cells_ptr);
-				break;
-			}
-			continue;
-		}
-
-		/* If it's a compatible string, see if it's the right one. */
-		int fd = open(name, O_RDONLY);
-		int clen = strlen(compat);
-		char *buffer = alloca(clen + 1);
-
-		if (fd < 0) {
-			perror(name);
-			continue;
-		}
-
-		if (read(fd, buffer, clen + 1) < 0) {
-			perror(name);
-			close(fd);
-			continue;
-		}
-		close(fd);
-
-		if (!strcmp(compat, buffer)) {
-			/* Initialize these to "unset" for the way up. */
-			*addr_cells_ptr = *size_cells_ptr = -1;
-
-			/* Can't leave string on the stack or we'll lose it! */
-			ret = strdup(parent);
-			break;
-		}
-	}
-
-	closedir(dir);
-	return ret;
-}
-#endif /* defined(__arm__) || defined(__aarch64__) */
-
 int main(int argc, char** argv)
 {
 	int print_defaults = 1;
@@ -1788,7 +1173,7 @@ int main(int argc, char** argv)
 				timestamp_id = strtoul(optarg, NULL, 0);
 			break;
 		case 'V':
-			verbose = 1;
+			cbmem_util_verbose++;
 			break;
 		case 'v':
 			print_version();
@@ -1809,77 +1194,8 @@ int main(int argc, char** argv)
 		print_usage(argv[0], 1);
 	}
 
-	mem_fd = open("/dev/mem", timestamp_id ? O_RDWR : O_RDONLY, 0);
-	if (mem_fd < 0) {
-		fprintf(stderr, "Failed to gain memory access: %s\n",
-			strerror(errno));
-		return 1;
-	}
-
-#if defined(__arm__) || defined(__aarch64__)
-	int addr_cells, size_cells;
-	char *coreboot_node = dt_find_compat("/proc/device-tree", "coreboot",
-					     &addr_cells, &size_cells);
-
-	if (!coreboot_node) {
-		fprintf(stderr, "Could not find 'coreboot' compatible node!\n");
-		return 1;
-	}
-
-	if (addr_cells < 0) {
-		fprintf(stderr, "Warning: no #address-cells node in tree!\n");
-		addr_cells = 1;
-	}
-
-	int nlen = strlen(coreboot_node);
-	char *reg = alloca(nlen + sizeof("/reg"));
-
-	strcpy(reg, coreboot_node);
-	strcpy(reg + nlen, "/reg");
-	free(coreboot_node);
-
-	int fd = open(reg, O_RDONLY);
-	if (fd < 0) {
-		perror(reg);
-		return 1;
-	}
-
-	int i;
-	size_t size_to_read = addr_cells * 4 + size_cells * 4;
-	uint8_t *dtbuffer = alloca(size_to_read);
-	if (read(fd, dtbuffer, size_to_read) < 0) {
-		perror(reg);
-		return 1;
-	}
-	close(fd);
-
-	/* No variable-length byte swap function anywhere in C... how sad. */
-	uint64_t baseaddr = 0;
-	for (i = 0; i < addr_cells * 4; i++) {
-		baseaddr <<= 8;
-		baseaddr |= *dtbuffer;
-		dtbuffer++;
-	}
-	uint64_t cb_table_size = 0;
-	for (i = 0; i < size_cells * 4; i++) {
-		cb_table_size <<= 8;
-		cb_table_size |= *dtbuffer;
-		dtbuffer++;
-	}
-
-	parse_cbtable(baseaddr, cb_table_size);
-#else
-	unsigned long long possible_base_addresses[] = { 0, 0xf0000 };
-
-	/* Find and parse coreboot table */
-	for (size_t j = 0; j < ARRAY_SIZE(possible_base_addresses); j++) {
-		if (!parse_cbtable(possible_base_addresses[j], 0))
-			break;
-	}
-#endif
-
-	if (mapping_virt(&lbtable_mapping) == NULL)
-		die("Table not found.\n");
+	if (!cbmem_devmem_init(timestamp_id != 0))
+		die("Unable to initialize /dev/mem access to coreboot tables and CBMEM.\n");
 
 	if (print_console)
 		dump_console(console_type, max_loglevel, print_unknown_logs);
@@ -1908,8 +1224,7 @@ int main(int argc, char** argv)
 	if (print_tcpa_log)
 		dump_tpm_log();
 
-	unmap_memory(&lbtable_mapping);
+	cbmem_devmem_terminate();
 
-	close(mem_fd);
 	return 0;
 }
diff --git a/util/cbmem/cbmem_util.h b/util/cbmem/cbmem_util.h
new file mode 100644
index 0000000000..8e513c1f32
--- /dev/null
+++ b/util/cbmem/cbmem_util.h
@@ -0,0 +1,96 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <inttypes.h>
+#include <stdbool.h>
+#include <stdio.h>
+
+#include <commonlib/bsd/cbmem_id.h>
+#include <commonlib/bsd/helpers.h>
+
+extern int cbmem_util_verbose;
+
+#define debug(x...)                                                            \
+	do {                                                                   \
+		if (cbmem_util_verbose > 1)                                    \
+			printf("[%s:%d %s()] ", __FILE__, __LINE__, __func__); \
+		if (cbmem_util_verbose)                                        \
+			printf(x);                                             \
+	} while (0)
+
+#define die(x...)                   \
+	do {                        \
+		fprintf(stderr, x); \
+		abort();            \
+	} while (0)
+
+struct cbmem_console {
+	uint32_t size;
+	uint32_t cursor;
+	uint8_t body[];
+} __packed;
+
+#define CBMC_CURSOR_MASK ((1 << 28) - 1)
+#define CBMC_OVERFLOW    (1 << 31)
+
+/**
+ * Function pointer type used by CBMEM foreach iteration calls.
+ *
+ * @param id CBMEM_ID_* value.
+ * @param physical_address CBMEM entry address in physical memory.
+ * @param buf heap-allocated buffer with CBMEM entry contents.
+ * @param size is the size of CBMEM entry in bytes.
+ * @param data callback-specific context data.
+ *
+ * @returns true if iteration should finish, false if it should continue.
+ */
+typedef bool (*cbmem_iterator_callback)(const uint32_t id, const uint64_t physical_address,
+					const uint8_t *buf, const size_t size, void *data);
+
+/* API for accessing CBMEM via /dev/mem */
+
+/**
+ * Initialize the driver.
+ *
+ * @param writeable tries to map CBMEM in R/W mode.
+ *
+ * @returns true on success, false otherwise.
+ */
+bool cbmem_devmem_init(bool writeable);
+
+/**
+ * Cleanup and terminate the driver. **MUST** be called if cbmem_devmem_init succeeded before.
+ */
+void cbmem_devmem_terminate(void);
+
+/**
+ * Get CBMEM entry as an allocated buffer.
+ *
+ * @param id CBMEM_ID_* value.
+ * @param buf_out return pointer for the allocated buffer containing entry contents.
+ * @param size_out size of returned buffer. Optional.
+ * @param addr_out pointer to the output buffer for entry address in physical memory. Optional.
+ *
+ * @returns true on success, false otherwise.
+ */
+bool cbmem_devmem_get_cbmem_entry(uint32_t id, uint8_t **buf_out, size_t *size_out, uint64_t *addr_out);
+
+/**
+ * Write provided buffer contents to the CBMEM entry.
+ *
+ * @param id CBMEM_ID_* value.
+ * @param buf pointer to the source buffer.
+ * @param buf_size size of the source buffer.
+ *
+ * @returns true on success, false otherwise.
+ */
+bool cbmem_devmem_write_cbmem_entry(uint32_t id, uint8_t *buf, size_t buf_size);
+
+/**
+ * Backend-specific function iterating over CBMEM entries.
+ *
+ * @param cb user callback function to call during iteration.
+ * @param data pointer to the context data for the callback.
+ * @param with_contents tells whether the callback should get NULL (false) or copy of the entry (true).
+ */
+void cbmem_devmem_foreach_cbmem_entry(cbmem_iterator_callback cb, void *data,
+				      bool with_contents);
diff --git a/util/cbmem/devmem_drv.c b/util/cbmem/devmem_drv.c
new file mode 100644
index 0000000000..249f44a4cd
--- /dev/null
+++ b/util/cbmem/devmem_drv.c
@@ -0,0 +1,675 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <alloca.h>
+#include <errno.h>
+#include <inttypes.h>
+#include <stdbool.h>
+#include <stdint.h>
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+
+#include <arpa/inet.h>
+#include <dirent.h>
+#include <endian.h>
+#include <fcntl.h>
+#include <unistd.h>
+#include <sys/mman.h>
+#include <sys/types.h>
+
+#include <commonlib/bsd/cbmem_id.h>
+#include <commonlib/bsd/ipchksum.h>
+#include <commonlib/coreboot_tables.h>
+#include <commonlib/helpers.h>
+#include <commonlib/timestamp_serialized.h>
+#include <commonlib/tpm_log_serialized.h>
+
+#ifdef __OpenBSD__
+#include <sys/param.h>
+#include <sys/sysctl.h>
+#endif
+
+#include "cbmem_util.h"
+
+struct mapping {
+	void *virt;
+	size_t offset;
+	size_t virt_size;
+	unsigned long long phys;
+	size_t size;
+};
+
+/* File handle used to access /dev/mem */
+static int mem_fd;
+static struct mapping lbtable_mapping;
+
+static unsigned long long system_page_size(void)
+{
+	static unsigned long long page_size;
+
+	if (!page_size)
+		page_size = getpagesize();
+
+	return page_size;
+}
+
+static inline size_t size_to_mib(size_t sz)
+{
+	return sz >> 20;
+}
+
+/* Return mapping of physical address requested. */
+static void *mapping_virt(const struct mapping *mapping)
+{
+	char *v = mapping->virt;
+
+	if (v == NULL)
+		return NULL;
+
+	return v + mapping->offset;
+}
+
+/* Returns virtual address on success, NULL on error. mapping is filled in. */
+static void *map_memory_with_prot(struct mapping *mapping, unsigned long long phys, size_t sz,
+				  int prot)
+{
+	void *v;
+	unsigned long long page_size;
+
+	page_size = system_page_size();
+
+	mapping->virt = NULL;
+	mapping->offset = phys % page_size;
+	mapping->virt_size = sz + mapping->offset;
+	mapping->size = sz;
+	mapping->phys = phys;
+
+	if (size_to_mib(mapping->virt_size) == 0) {
+		debug("Mapping %zuB of physical memory at 0x%llx (requested 0x%llx).\n",
+		      mapping->virt_size, phys - mapping->offset, phys);
+	} else {
+		debug("Mapping %zuMB of physical memory at 0x%llx (requested 0x%llx).\n",
+		      size_to_mib(mapping->virt_size), phys - mapping->offset, phys);
+	}
+
+	v = mmap(NULL, mapping->virt_size, prot, MAP_SHARED, mem_fd, phys - mapping->offset);
+
+	if (v == MAP_FAILED) {
+		debug("Mapping failed %zuB of physical memory at 0x%llx.\n", mapping->virt_size,
+		      phys - mapping->offset);
+		return NULL;
+	}
+
+	mapping->virt = v;
+
+	if (mapping->offset != 0)
+		debug("  ... padding virtual address with 0x%zx bytes.\n", mapping->offset);
+
+	return mapping_virt(mapping);
+}
+
+/* Convenience helper for the common case of read-only mappings. */
+static const void *map_memory(struct mapping *mapping, unsigned long long phys, size_t sz)
+{
+	return map_memory_with_prot(mapping, phys, sz, PROT_READ);
+}
+
+/* Returns 0 on success, < 0 on error. mapping is cleared if successful. */
+static int unmap_memory(struct mapping *mapping)
+{
+	if (mapping->virt == NULL)
+		return -1;
+
+	munmap(mapping->virt, mapping->virt_size);
+	mapping->virt = NULL;
+	mapping->offset = 0;
+	mapping->virt_size = 0;
+
+	return 0;
+}
+
+/*
+ * Some architectures map /dev/mem memory in a way that doesn't support
+ * unaligned accesses. Most normal libc memcpy()s aren't safe to use in this
+ * case, so build our own which makes sure to never do unaligned accesses on
+ * *src (*dest is fine since we never map /dev/mem for writing).
+ */
+static void *aligned_memcpy(void *dest, const void *src, size_t n)
+{
+	uint8_t *d = dest;
+	const volatile uint8_t *s = src; /* volatile to prevent optimization */
+
+	while ((uintptr_t)s & (sizeof(size_t) - 1)) {
+		if (n-- == 0)
+			return dest;
+		*d++ = *s++;
+	}
+
+	while (n >= sizeof(size_t)) {
+		*(size_t *)d = *(const volatile size_t *)s;
+		d += sizeof(size_t);
+		s += sizeof(size_t);
+		n -= sizeof(size_t);
+	}
+
+	while (n-- > 0)
+		*d++ = *s++;
+
+	return dest;
+}
+
+/* Return < 0 on error, 0 on success. */
+static int parse_cbtable(uint64_t address, size_t table_size)
+{
+	const uint8_t *buf;
+	struct mapping header_mapping;
+	size_t req_size;
+	size_t i;
+
+	req_size = table_size;
+	/* Default to 4 KiB search space. */
+	if (req_size == 0)
+		req_size = 4 * 1024;
+
+	debug("Looking for coreboot table at %" PRIx64 " %zd bytes.\n", address, req_size);
+
+	buf = map_memory(&header_mapping, address, req_size);
+
+	if (!buf)
+		return -1;
+
+	/* look at every 16 bytes */
+	for (i = 0; i <= req_size - sizeof(struct lb_header); i += 16) {
+		const struct lb_header *lbh;
+		struct mapping table_mapping;
+
+		lbh = (const struct lb_header *)&buf[i];
+		if (memcmp(lbh->signature, "LBIO", sizeof(lbh->signature)) ||
+		    !lbh->header_bytes || ipchksum(lbh, sizeof(*lbh))) {
+			continue;
+		}
+
+		/* Map in the whole table to parse. */
+		if (!map_memory(&table_mapping, address + i,
+				lbh->header_bytes + lbh->table_bytes)) {
+			debug("Couldn't map in table\n");
+			continue;
+		}
+
+		const uint8_t *table_contents =
+			&((uint8_t *)mapping_virt(&table_mapping))[lbh->header_bytes];
+		if (ipchksum(table_contents, lbh->table_bytes) !=
+		    lbh->table_checksum) {
+			debug("Signature found, but wrong checksum.\n");
+			unmap_memory(&table_mapping);
+			continue;
+		}
+
+		debug("Found at %#" PRIx64 "\n", address + i);
+
+		const struct lb_record *lbr_p;
+
+		for (size_t offset = 0; offset < lbh->table_bytes; offset += lbr_p->size) {
+			lbr_p = (const struct lb_record *)&table_contents[offset];
+			debug("  coreboot table entry 0x%02x\n", lbr_p->tag);
+
+			if (lbr_p->tag != LB_TAG_FORWARD)
+				continue;
+
+			/* This is a forwarding entry. Repeat the search at the new address. */
+			struct lb_forward lbf_p = *(const struct lb_forward *)lbr_p;
+			debug("    Found forwarding entry.\n");
+
+			const uint64_t next_addr = lbf_p.forward;
+			unmap_memory(&header_mapping);
+			unmap_memory(&table_mapping);
+
+			return parse_cbtable(next_addr, 0);
+		}
+
+		debug("correct coreboot table found.\n");
+		unmap_memory(&header_mapping);
+		lbtable_mapping = table_mapping;
+
+		return 0;
+	}
+
+	unmap_memory(&header_mapping);
+
+	return -1;
+}
+
+#if defined(__arm__) || defined(__aarch64__)
+static void dt_update_cells(const char *name, int *addr_cells_ptr, int *size_cells_ptr)
+{
+	if (*addr_cells_ptr >= 0 && *size_cells_ptr >= 0)
+		return;
+
+	int buffer;
+	size_t nlen = strlen(name);
+	char *prop = alloca(nlen + sizeof("/#address-cells"));
+	strcpy(prop, name);
+
+	if (*addr_cells_ptr < 0) {
+		strcpy(prop + nlen, "/#address-cells");
+		int fd = open(prop, O_RDONLY);
+		if (fd < 0 && errno != ENOENT) {
+			perror(prop);
+		} else if (fd >= 0) {
+			if (read(fd, &buffer, sizeof(int)) < 0)
+				perror(prop);
+			else
+				*addr_cells_ptr = ntohl(buffer);
+			close(fd);
+		}
+	}
+
+	if (*size_cells_ptr < 0) {
+		strcpy(prop + nlen, "/#size-cells");
+		int fd = open(prop, O_RDONLY);
+		if (fd < 0 && errno != ENOENT) {
+			perror(prop);
+		} else if (fd >= 0) {
+			if (read(fd, &buffer, sizeof(int)) < 0)
+				perror(prop);
+			else
+				*size_cells_ptr = ntohl(buffer);
+			close(fd);
+		}
+	}
+}
+
+static char *dt_find_compat(const char *parent, const char *compat, int *addr_cells_ptr,
+			    int *size_cells_ptr)
+{
+	char *ret = NULL;
+	struct dirent *entry;
+	DIR *dir;
+
+	if (!(dir = opendir(parent))) {
+		perror(parent);
+		return NULL;
+	}
+
+	/* Loop through all files in the directory (DT node). */
+	while ((entry = readdir(dir))) {
+		/* We only care about compatible props or subnodes. */
+		if (entry->d_name[0] == '.' ||
+		    !((entry->d_type & DT_DIR) || !strcmp(entry->d_name, "compatible")))
+			continue;
+
+		/* Assemble the file name (on the stack, for speed). */
+		size_t plen = strlen(parent);
+		char *name = alloca(plen + strlen(entry->d_name) + 2);
+
+		strcpy(name, parent);
+		name[plen] = '/';
+		strcpy(name + plen + 1, entry->d_name);
+
+		/* If it's a subnode, recurse. */
+		if (entry->d_type & DT_DIR) {
+			ret = dt_find_compat(name, compat, addr_cells_ptr, size_cells_ptr);
+
+			/* There is only one matching node to find, abort. */
+			if (ret) {
+				/* Gather cells values on the way up. */
+				dt_update_cells(parent, addr_cells_ptr, size_cells_ptr);
+				break;
+			}
+			continue;
+		}
+
+		/* If it's a compatible string, see if it's the right one. */
+		int fd = open(name, O_RDONLY);
+		int clen = strlen(compat);
+		char *buffer = alloca(clen + 1);
+
+		if (fd < 0) {
+			perror(name);
+			continue;
+		}
+
+		if (read(fd, buffer, clen + 1) < 0) {
+			perror(name);
+			close(fd);
+			continue;
+		}
+		close(fd);
+
+		if (!strcmp(compat, buffer)) {
+			/* Initialize these to "unset" for the way up. */
+			*addr_cells_ptr = *size_cells_ptr = -1;
+
+			/* Can't leave string on the stack or we'll lose it! */
+			ret = strdup(parent);
+			break;
+		}
+	}
+
+	closedir(dir);
+	return ret;
+}
+#endif /* defined(__arm__) || defined(__aarch64__) */
+
+bool cbmem_devmem_init(bool writeable)
+{
+	mem_fd = open("/dev/mem", writeable ? O_RDWR : O_RDONLY, 0);
+	if (mem_fd < 0) {
+		fprintf(stderr, "Failed to gain memory access: %s\n", strerror(errno));
+		return false;
+	}
+
+#if defined(__arm__) || defined(__aarch64__)
+	int addr_cells, size_cells;
+	char *coreboot_node =
+		dt_find_compat("/proc/device-tree", "coreboot", &addr_cells, &size_cells);
+
+	if (!coreboot_node) {
+		fprintf(stderr, "Could not find 'coreboot' compatible node!\n");
+		return false;
+	}
+
+	if (addr_cells < 0) {
+		fprintf(stderr, "Warning: no #address-cells node in tree!\n");
+		addr_cells = 1;
+	}
+
+	int nlen = strlen(coreboot_node);
+	char *reg = alloca(nlen + sizeof("/reg"));
+
+	strcpy(reg, coreboot_node);
+	strcpy(reg + nlen, "/reg");
+	free(coreboot_node);
+
+	int fd = open(reg, O_RDONLY);
+	if (fd < 0) {
+		perror(reg);
+		return false;
+	}
+
+	int i;
+	size_t size_to_read = addr_cells * 4 + size_cells * 4;
+	uint8_t *dtbuffer = alloca(size_to_read);
+	if (read(fd, dtbuffer, size_to_read) < 0) {
+		perror(reg);
+		return false;
+	}
+	close(fd);
+
+	/* No variable-length byte swap function anywhere in C... how sad. */
+	uint64_t baseaddr = 0;
+	for (i = 0; i < addr_cells * 4; i++) {
+		baseaddr <<= 8;
+		baseaddr |= *dtbuffer;
+		dtbuffer++;
+	}
+	uint64_t cb_table_size = 0;
+	for (i = 0; i < size_cells * 4; i++) {
+		cb_table_size <<= 8;
+		cb_table_size |= *dtbuffer;
+		dtbuffer++;
+	}
+
+	parse_cbtable(baseaddr, cb_table_size);
+#else
+	unsigned long long possible_base_addresses[] = {0, 0xf0000};
+
+	/* Find and parse coreboot table */
+	for (size_t j = 0; j < ARRAY_SIZE(possible_base_addresses); j++) {
+		if (!parse_cbtable(possible_base_addresses[j], 0))
+			break;
+	}
+#endif
+
+	if (mapping_virt(&lbtable_mapping) == NULL) {
+		debug("Table not found.\n");
+		return false;
+	}
+
+	return true;
+}
+
+void cbmem_devmem_terminate(void)
+{
+	unmap_memory(&lbtable_mapping);
+	close(mem_fd);
+	mem_fd = -1;
+}
+
+/* This is a work-around for a nasty problem introduced by initially having
+ * pointer sized entries in the lb_cbmem_ref structures. This caused problems
+ * on 64bit x86 systems because coreboot is 32bit on those systems.
+ * When the problem was found, it was corrected, but there are a lot of
+ * systems out there with a firmware that does not produce the right
+ * lb_cbmem_ref structure. Hence we try to autocorrect this issue here.
+ */
+static struct lb_cbmem_ref parse_cbmem_ref(const struct lb_cbmem_ref *cbmem_ref)
+{
+	struct lb_cbmem_ref ret;
+
+	aligned_memcpy(&ret, cbmem_ref, sizeof(ret));
+
+	if (cbmem_ref->size < sizeof(*cbmem_ref))
+		ret.cbmem_addr = (uint32_t)ret.cbmem_addr;
+
+	debug("      cbmem_addr = %" PRIx64 "\n", ret.cbmem_addr);
+
+	return ret;
+}
+
+static uint32_t cbmem_id_to_lb_tag(uint32_t tag)
+{
+	/* Minimal subset. Expand based on the CBMEM to coreboot table
+	   records mapping in lib/coreboot_table.c */
+	switch (tag) {
+	case CBMEM_ID_TIMESTAMP:
+		return LB_TAG_TIMESTAMPS;
+	case CBMEM_ID_CONSOLE:
+		return LB_TAG_CBMEM_CONSOLE;
+	case CBMEM_ID_TPM_CB_LOG:
+		return LB_TAG_TPM_CB_LOG;
+	}
+	return LB_TAG_UNUSED;
+}
+
+static bool cbmem_devmem_probe_cbmem_entry(uint32_t id, uint64_t *addr_out, size_t *size_out)
+{
+	const uint8_t *table;
+	const struct lb_header *lbh;
+	const uint32_t legacy_tag = cbmem_id_to_lb_tag(id);
+	struct lb_cbmem_ref *ref = NULL;
+	const struct lb_record *lbr = NULL;
+
+	table = mapping_virt(&lbtable_mapping);
+	if (table == NULL)
+		die("No correct coreboot table found\n");
+
+	lbh = (const struct lb_header *)table;
+	table = &table[lbh->header_bytes];
+
+	/* Fast track for the coreboot table. */
+	if (id == CBMEM_ID_CBTABLE) {
+		*addr_out = lbtable_mapping.phys;
+		*size_out = lbtable_mapping.size;
+		return true;
+	}
+
+	for (size_t offset = 0; offset < lbh->table_bytes - sizeof(struct lb_cbmem_entry);) {
+		lbr = (const void *)(table + offset);
+		offset += lbr->size;
+
+		/* Store coreboot table entry for later if CBMEM entry does not exist.
+		   CBMEM entry stores size including the reserved area, so prefer it,
+		   so more potential data and/or space is available. */
+		if (legacy_tag != LB_TAG_UNUSED && lbr->tag == legacy_tag)
+			ref = (struct lb_cbmem_ref *)lbr;
+
+		if (lbr->tag != LB_TAG_CBMEM_ENTRY)
+			continue;
+
+		struct lb_cbmem_entry lbe;
+		aligned_memcpy(&lbe, lbr, sizeof(lbe));
+		if (lbe.id != id)
+			continue;
+
+		*addr_out = lbe.address;
+		*size_out = lbe.entry_size;
+		return true;
+	}
+
+	/* No mapping and/or no potential reference means that
+	   the requested entry does not exit. */
+	if (legacy_tag == LB_TAG_UNUSED || ref == NULL)
+		return false;
+
+	debug("Found coreboot table record equivalent of CBMEM entry id: %#x, tag: %#x\n", id,
+	      legacy_tag);
+
+	const struct lb_cbmem_ref lbc = parse_cbmem_ref(ref);
+	size_t header_map_size = 0;
+
+	/* Process legacy coreboot table entries */
+	switch (lbc.tag) {
+	case LB_TAG_TIMESTAMPS:
+		header_map_size = sizeof(struct timestamp_table);
+		break;
+	case LB_TAG_CBMEM_CONSOLE:
+		header_map_size = sizeof(struct cbmem_console);
+		break;
+	case LB_TAG_TPM_CB_LOG:
+		header_map_size = sizeof(struct tpm_cb_log_table);
+		break;
+	}
+
+	struct mapping entry_mapping;
+	const void *entry_header = NULL;
+
+	entry_header = map_memory(&entry_mapping, lbc.cbmem_addr, header_map_size);
+	if (!entry_header)
+		die("Unable to map header for coreboot table entry id: %#x\n", legacy_tag);
+
+	*addr_out = lbc.cbmem_addr;
+
+	switch (legacy_tag) {
+	case LB_TAG_TIMESTAMPS: {
+		const struct timestamp_table *tst_p = entry_header;
+		*size_out = sizeof(*tst_p) + tst_p->num_entries * sizeof(tst_p->entries[0]);
+		break;
+	}
+	case LB_TAG_CBMEM_CONSOLE: {
+		const struct cbmem_console *console_p = entry_header;
+		*size_out = sizeof(*console_p) + console_p->size;
+		break;
+	}
+	case LB_TAG_TPM_CB_LOG: {
+		const struct tpm_cb_log_table *tclt_p = entry_header;
+		*size_out = sizeof(*tclt_p) + tclt_p->num_entries * sizeof(tclt_p->entries[0]);
+		break;
+	}
+	}
+
+	unmap_memory(&entry_mapping);
+
+	return true;
+}
+
+static void fetch_cbmem_entry(const uint32_t id, const uint64_t addr, const size_t size,
+			      uint8_t **buf_out)
+{
+	struct mapping cbmem_mapping;
+	const uint8_t *buf = map_memory(&cbmem_mapping, addr, size);
+	if (!buf)
+		die("Unable to map CBMEM entry id: %#x, size: %zu\n", id, size);
+
+	*buf_out = malloc(size);
+	if (!*buf_out) {
+		unmap_memory(&cbmem_mapping);
+		die("Unable to allocate memory for CBMEM entry id: %#x, size: %zu\n", id, size);
+	}
+
+	aligned_memcpy(*buf_out, buf, size);
+	unmap_memory(&cbmem_mapping);
+}
+
+bool cbmem_devmem_get_cbmem_entry(uint32_t id, uint8_t **buf_out, size_t *size_out,
+				  uint64_t *addr_out)
+{
+	uint64_t addr;
+	size_t size;
+
+	if (!cbmem_devmem_probe_cbmem_entry(id, &addr, &size)) {
+		debug("CBMEM entry not found. CBMEM id: %#x\n", id);
+		return false;
+	}
+
+	fetch_cbmem_entry(id, addr, size, buf_out);
+
+	if (size_out)
+		*size_out = size;
+	if (addr_out)
+		*addr_out = addr;
+
+	return true;
+}
+
+bool cbmem_devmem_write_cbmem_entry(uint32_t id, uint8_t *buf, size_t buf_size)
+{
+	uint64_t addr = 0;
+	size_t size = 0;
+	uint8_t *origin_buf = NULL;
+	struct mapping mapping;
+
+	if (!cbmem_devmem_probe_cbmem_entry(id, &addr, &size)) {
+		debug("CBMEM entry not found. CBMEM id: %#x\n", id);
+		return false;
+	}
+
+	if (buf_size > size)
+		die("Attempting to write %zu bytes to CBMEM entry id: %#x of %zu bytes. Operation not possible.\n",
+		    buf_size, id, size);
+
+	origin_buf = map_memory_with_prot(&mapping, addr, size, PROT_READ | PROT_WRITE);
+	if (!origin_buf)
+		die("Unable to map CBMEM entry id: %#x, size: %zu for read-write access.\n", id,
+		    size);
+
+	aligned_memcpy(origin_buf, buf, buf_size);
+	unmap_memory(&mapping);
+
+	return true;
+}
+
+void cbmem_devmem_foreach_cbmem_entry(cbmem_iterator_callback cb, void *data,
+				      bool with_contents)
+{
+	uint8_t *table = NULL;
+	size_t table_size = 0;
+
+	if (!cbmem_devmem_get_cbmem_entry(CBMEM_ID_CBTABLE, &table, &table_size, NULL))
+		die("coreboot table not found.\n");
+
+	const struct lb_header *lbh = (const struct lb_header *)table;
+	const struct lb_record *lbr = NULL;
+	bool should_iteration_end = false;
+	size_t offset = 0;
+	while (offset < lbh->table_bytes - sizeof(struct lb_cbmem_entry) &&
+	       should_iteration_end == false) {
+		lbr = (const struct lb_record *)&table[lbh->header_bytes + offset];
+		offset += lbr->size;
+
+		if (lbr->tag != LB_TAG_CBMEM_ENTRY)
+			continue;
+
+		const struct lb_cbmem_entry *lbe = (const struct lb_cbmem_entry *)lbr;
+		uint8_t *buf = NULL;
+		if (with_contents)
+			fetch_cbmem_entry(lbe->id, lbe->address, lbe->entry_size, &buf);
+
+		should_iteration_end = cb(lbe->id, lbe->address, buf, lbe->entry_size, data);
+
+		if (with_contents)
+			free(buf);
+	}
+
+	free(table);
+}

From bf4f08f3b6504c876c9974ccd052f2776da9ea82 Mon Sep 17 00:00:00 2001
From: Walter Sonius <walterav1984@gmail.com>
Date: Fri, 4 Jul 2025 13:43:07 +0000
Subject: [PATCH 1631/3886] 
 mb/hp/snb_ivb_desktops/variants/compaq_8300_elite_sff: early VGA output

Recent development of the "pro_6300" variant fixed VGA output in EDK2
(MrChromebox/2502) and SeaBIOS 1.16.3 using libgfxinit by removing the
following line from Kconfig "select GFX_GMA_ANALOG_I2C_HDMI_B" hinted by
Keith Hui. This fix also applies to the "compaq_8300_elite_sff" variant.

The VGA output without this change only works after loading the OS!

Change-Id: Ifaf3df12fdde996d2842650be411a6d844f949a4
Signed-off-by: Walter Sonius <walterav1984@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88305
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
---
 src/mainboard/hp/snb_ivb_desktops/Kconfig | 1 -
 1 file changed, 1 deletion(-)

diff --git a/src/mainboard/hp/snb_ivb_desktops/Kconfig b/src/mainboard/hp/snb_ivb_desktops/Kconfig
index c51813b6f9..7973d7b3e8 100644
--- a/src/mainboard/hp/snb_ivb_desktops/Kconfig
+++ b/src/mainboard/hp/snb_ivb_desktops/Kconfig
@@ -35,7 +35,6 @@ config BOARD_HP_COMPAQ_8200_ELITE_USDT
 config BOARD_HP_COMPAQ_8300_ELITE_SFF
 	select BOARD_HP_SNB_IVB_DESKTOPS_COMMON
 	select BOARD_ROMSIZE_KB_16384
-	select GFX_GMA_ANALOG_I2C_HDMI_B
 	select SOUTHBRIDGE_INTEL_BD82X6X
 
 config BOARD_HP_COMPAQ_ELITE_8300_USDT

From 480ac1504407ff132e75b6c64085316b07c6b1ab Mon Sep 17 00:00:00 2001
From: Martin Roth <gaumless@gmail.com>
Date: Sat, 5 Jul 2025 16:19:09 -0600
Subject: [PATCH 1632/3886] util/cbfstool: Prevent overflow when sorting fit
 table entries

If fit_table_entries() fails, it returns zero, but the sort loop
subtracts 1 from that value before comparing for the loop termination.
Since the value is unsigned, this results in wraparound overflow,
effectively causing an infinite loop. To mitigate this, store the
number of FIT entries as an int, and use that for the loop exit
condition check. Use int type for the loop counters as well to
avoid the compiler complaining about an signed/unsigned comparison.

BUG=CID 1612099

Change-Id: Id0a16bdb86d075ec6c322b44fd782f81d15ca6a7
Signed-off-by: Martin Roth <gaumless@gmail.com>
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88324
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 util/cbfstool/fit.c | 9 +++++----
 1 file changed, 5 insertions(+), 4 deletions(-)

diff --git a/util/cbfstool/fit.c b/util/cbfstool/fit.c
index ca60720b2c..0d5d4c7847 100644
--- a/util/cbfstool/fit.c
+++ b/util/cbfstool/fit.c
@@ -165,13 +165,14 @@ static inline size_t fit_free_space(struct fit_table *fit,
 static void sort_fit_table(struct fit_table *fit)
 {
 	struct fit_entry tmp;
-	size_t i, j;
-	int swapped;
+	int i, j, num_entries, swapped;
+
+	num_entries = fit_table_entries(fit);
 
 	/* Bubble sort entries */
-	for (j = 0; j < fit_table_entries(fit) - 1; j++) {
+	for (j = 0; j < num_entries - 1; j++) {
 		swapped = 0;
-		for (i = 0; i < fit_table_entries(fit) - j - 1; i++) {
+		for (i = 0; i < num_entries - j - 1; i++) {
 			if (fit->entries[i].type_checksum_valid <=
 			    fit->entries[i + 1].type_checksum_valid)
 				continue;

From a87cbcd3c913227515c279c044db23d3a7c23c9b Mon Sep 17 00:00:00 2001
From: Jincheng Li <jincheng.li@intel.com>
Date: Wed, 18 Jun 2025 09:47:02 +0800
Subject: [PATCH 1633/3886] soc/intel/xeon_sp/ibl: Config ACPI base using PMC
 device

IBL shall use PMC device to program ABASE instead of PCR.

TESTED=Build and boot on intel/avenuecity CRB with below log:
[INFO ]  soc_config_acpibase : pmbase = 501

Change-Id: I3497c287a5370deed02b269405bc45d5d41e7f33
Signed-off-by: Jincheng Li <jincheng.li@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88144
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/soc/intel/xeon_sp/ibl/soc_pch.c | 32 +++++++++--------------------
 1 file changed, 10 insertions(+), 22 deletions(-)

diff --git a/src/soc/intel/xeon_sp/ibl/soc_pch.c b/src/soc/intel/xeon_sp/ibl/soc_pch.c
index 7487441242..ee66c0d0cb 100644
--- a/src/soc/intel/xeon_sp/ibl/soc_pch.c
+++ b/src/soc/intel/xeon_sp/ibl/soc_pch.c
@@ -1,40 +1,28 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
+#include <assert.h>
 #include <console/console.h>
 #include <device/pci_ops.h>
-#include <intelblocks/pcr.h>
 #include <soc/bootblock.h>
 #include <soc/pci_devs.h>
-#include <soc/pcr_ids.h>
+#include <soc/pmc.h>
 #include <soc/soc_pch.h>
 
-#define PCR_PSF3_TO_SHDW_PMC_REG_BASE	0x600
-#define PCR_PSFX_TO_SHDW_BAR4		0x10
-#define PCR_PSFX_TO_SHDW_PCIEN_IOEN	0x01
-#define PCR_PSFX_T0_SHDW_PCIEN		0x1C
-
 static void soc_config_acpibase(void)
 {
-	uint32_t pmc_reg_value;
-	uint32_t pmc_base_reg = PCR_PSF3_TO_SHDW_PMC_REG_BASE;
+	/* Disable IO command in PMC Device first before changing Base Address */
+	uint16_t reg16 = pci_read_config16(PCH_DEV_PMC, PCI_COMMAND);
+	pci_write_config16(PCH_DEV_PMC, PCI_COMMAND,
+			reg16 & ~(PCI_COMMAND_IO | PCI_COMMAND_MASTER));
 
-	pmc_reg_value = pcr_read32(PID_PSF3, pmc_base_reg + PCR_PSFX_TO_SHDW_BAR4);
+	/* Program ACPI Base */
+	pci_write_config32(PCH_DEV_PMC, ABASE, ACPI_BASE_ADDRESS);
 
-	if (pmc_reg_value != 0xffffffff) {
-		/* Disable Io Space before changing the address */
-		pcr_rmw32(PID_PSF3, pmc_base_reg + PCR_PSFX_T0_SHDW_PCIEN,
-				~PCR_PSFX_TO_SHDW_PCIEN_IOEN, 0);
-		/* Program ABASE in PSF3 PMC space BAR4*/
-		pcr_write32(PID_PSF3, pmc_base_reg + PCR_PSFX_TO_SHDW_BAR4,
-				ACPI_BASE_ADDRESS);
-		/* Enable IO Space */
-		pcr_rmw32(PID_PSF3, pmc_base_reg + PCR_PSFX_T0_SHDW_PCIEN,
-				~0, PCR_PSFX_TO_SHDW_PCIEN_IOEN);
-	}
 	/* Enable Bus Master and IO Space */
 	pci_or_config16(PCH_DEV_PMC, PCI_COMMAND, (PCI_COMMAND_IO | PCI_COMMAND_MASTER));
 
-	uint16_t data = pcr_read16(PID_PSF3, pmc_base_reg + PCR_PSFX_TO_SHDW_BAR4);
+	uint32_t data = pci_read_config32(PCH_DEV_PMC, ABASE);
+	assert(ACPI_BASE_ADDRESS == (data & ~PCI_BASE_ADDRESS_IO_ATTR_MASK));
 	printk(BIOS_INFO, "%s : pmbase = %x\n", __func__, (int)data);
 }
 

From 3828153ea5c3871b7ba3b2aa392df63d815a6978 Mon Sep 17 00:00:00 2001
From: Jincheng Li <jincheng.li@intel.com>
Date: Thu, 3 Jul 2025 14:31:39 +0800
Subject: [PATCH 1634/3886] soc/intel/xeon_sp/gnr: Use official microcodes

Use microcode updates from intel-microcode submodule by default.
Downstream users can still decide to use their own files.

TEST=Build and boot on intel/avenuecity CRB
TEST=Build and boot on intel/beechnutcity CRB

Change-Id: I5a37423426b19dc9ec76984df5ad9c6d2a28f83b
Signed-off-by: Jincheng Li <jincheng.li@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88283
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
---
 configs/builder/config.intel.crb.avc  | 2 --
 configs/builder/config.intel.crb.bnc  | 2 --
 src/soc/intel/xeon_sp/gnr/Kconfig     | 1 -
 src/soc/intel/xeon_sp/gnr/Makefile.mk | 3 +++
 4 files changed, 3 insertions(+), 5 deletions(-)

diff --git a/configs/builder/config.intel.crb.avc b/configs/builder/config.intel.crb.avc
index e547c4148f..433f06dac7 100644
--- a/configs/builder/config.intel.crb.avc
+++ b/configs/builder/config.intel.crb.avc
@@ -15,7 +15,6 @@ CONFIG_NO_GFX_INIT=y
 CONFIG_HAVE_IFD_BIN=y
 CONFIG_HAVE_PBP_BIN=y
 CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION=y
-CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y
 CONFIG_ADD_FSP_BINARIES=y
 CONFIG_PAYLOAD_LINUX=y
 
@@ -27,7 +26,6 @@ CONFIG_CONSOLE_SERIAL_115200=y
 #
 CONFIG_IFD_BIN_PATH="site-local/avenuecity/descriptor.bin"
 CONFIG_PBP_BIN_PATH="site-local/avenuecity/pbp.bin"
-CONFIG_CPU_UCODE_BINARIES="site-local/avenuecity/ucode.mcb"
 CONFIG_FSP_T_FILE="site-local/avenuecity/Server_T.fd"
 CONFIG_FSP_M_FILE="site-local/avenuecity/Server_M.fd"
 CONFIG_FSP_S_FILE="site-local/avenuecity/Server_S.fd"
diff --git a/configs/builder/config.intel.crb.bnc b/configs/builder/config.intel.crb.bnc
index a4ffaf7f29..80ec39133e 100644
--- a/configs/builder/config.intel.crb.bnc
+++ b/configs/builder/config.intel.crb.bnc
@@ -15,7 +15,6 @@ CONFIG_NO_GFX_INIT=y
 CONFIG_HAVE_IFD_BIN=y
 CONFIG_HAVE_PBP_BIN=y
 CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION=y
-CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y
 CONFIG_ADD_FSP_BINARIES=y
 CONFIG_PAYLOAD_LINUX=y
 
@@ -27,7 +26,6 @@ CONFIG_CONSOLE_SERIAL_115200=y
 #
 CONFIG_IFD_BIN_PATH="site-local/beechnutcity/descriptor.bin"
 CONFIG_PBP_BIN_PATH="site-local/beechnutcity/pbp.bin"
-CONFIG_CPU_UCODE_BINARIES="site-local/beechnutcity/ucode.mcb"
 CONFIG_FSP_T_FILE="site-local/beechnutcity/Server_T.fd"
 CONFIG_FSP_M_FILE="site-local/beechnutcity/Server_M.fd"
 CONFIG_FSP_S_FILE="site-local/beechnutcity/Server_S.fd"
diff --git a/src/soc/intel/xeon_sp/gnr/Kconfig b/src/soc/intel/xeon_sp/gnr/Kconfig
index 4dee9616fe..a259320342 100644
--- a/src/soc/intel/xeon_sp/gnr/Kconfig
+++ b/src/soc/intel/xeon_sp/gnr/Kconfig
@@ -2,7 +2,6 @@
 
 config SOC_INTEL_GRANITERAPIDS
 	bool
-	select MICROCODE_BLOB_NOT_HOOKED_UP
 	select FSP_NVS_DATA_POST_SILICON_INIT
 	select SOC_INTEL_MEM_MAPPED_PM_CONFIGURATION
 	select XEON_SP_COMMON_BASE
diff --git a/src/soc/intel/xeon_sp/gnr/Makefile.mk b/src/soc/intel/xeon_sp/gnr/Makefile.mk
index 054d5132c1..7af7416973 100644
--- a/src/soc/intel/xeon_sp/gnr/Makefile.mk
+++ b/src/soc/intel/xeon_sp/gnr/Makefile.mk
@@ -26,4 +26,7 @@ CPPFLAGS_common += -I$(src)/soc/intel/xeon_sp/gnr
 
 CFLAGS_common += -fshort-wchar
 
+cpu_microcode_bins += 3rdparty/intel-microcode/intel-ucode/06-ad-01
+cpu_microcode_bins += 3rdparty/intel-microcode/intel-ucode/06-af-03
+
 endif ## CONFIG_SOC_INTEL_GRANITERAPIDS

From f0d50aa404d10adeb7215478df9b13a697ef2888 Mon Sep 17 00:00:00 2001
From: Patrick Rudolph <patrick.rudolph@9elements.com>
Date: Sun, 5 Jan 2025 15:16:33 +0100
Subject: [PATCH 1635/3886] commonlib/include/commonlib: Add volatile qualifier

With the introduction of the stack canary breakpoint QEMU uncovered
a different bug within coreboot. Currently the compiler optimizes
over aggressively inline functions and memory stores.

That also affects write_at_ble8(), which is supposed to store a
single byte at time. The compiler however optimizes multiple byte
stores into a single wider (and possibly unaligned) store operation.

This can be seen in the emited assembly code of write_le16(), as used
to install the EBDA:
 401348a:       66 c7 04 25 13 04 00    movw   $0x400,0x413
 4013491:       00 00 04

Make sure that the compiler does not optimize multiple calls to
write_at_ble8() by adding the volatile qualifier.

The emitted assembly code of the same function changes to:
 401394c:       c6 04 25 13 04 00 00    movb   $0x0,0x413
 4013953:       00
 4013954:       c6 04 25 14 04 00 00    movb   $0x4,0x414
 401395b:       04

Fixes a strange bug in QEMU where it triggers the DEBUG breakpoint
handler on unaligned 16-bit stores in the first 4KiB of memory.
Aligned stores and store outside of the first 4KiB do not dispatch
the DEBUG breakpoint handler.

Change-Id: Ibbc661235a38c7f7540b656a67f067c3e51105d1
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85855
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
---
 src/commonlib/include/commonlib/endian.h | 12 ++++++------
 1 file changed, 6 insertions(+), 6 deletions(-)

diff --git a/src/commonlib/include/commonlib/endian.h b/src/commonlib/include/commonlib/endian.h
index 84c90b4297..971854c2b3 100644
--- a/src/commonlib/include/commonlib/endian.h
+++ b/src/commonlib/include/commonlib/endian.h
@@ -11,7 +11,7 @@
 
 static inline uint8_t read_ble8(const void *src)
 {
-	const uint8_t *s = src;
+	const volatile uint8_t *s = src;
 	return *s;
 }
 
@@ -24,7 +24,7 @@ static inline uint8_t read_at_ble8(const void *src, size_t offset)
 
 static inline void write_ble8(void *dest, uint8_t val)
 {
-	*(uint8_t *)dest = val;
+	*(volatile uint8_t *)dest = val;
 }
 
 static inline void write_at_ble8(void *dest, uint8_t val, size_t offset)
@@ -58,7 +58,7 @@ static inline void write_at_be8(void *dest, uint8_t val, size_t offset)
 
 static inline uint16_t read_be16(const void *src)
 {
-	const uint8_t *s = src;
+	const volatile uint8_t *s = src;
 	return (((uint16_t)s[0]) << 8) | (((uint16_t)s[1]) << 0);
 }
 
@@ -84,7 +84,7 @@ static inline void write_at_be16(void *dest, uint16_t val, size_t offset)
 
 static inline uint32_t read_be32(const void *src)
 {
-	const uint8_t *s = src;
+	const volatile uint8_t *s = src;
 	return (((uint32_t)s[0]) << 24) | (((uint32_t)s[1]) << 16) |
 		(((uint32_t)s[2]) << 8) | (((uint32_t)s[3]) << 0);
 }
@@ -162,7 +162,7 @@ static inline void write_at_le8(void *dest, uint8_t val, size_t offset)
 
 static inline uint16_t read_le16(const void *src)
 {
-	const uint8_t *s = src;
+	const volatile uint8_t *s = src;
 	return (((uint16_t)s[1]) << 8) | (((uint16_t)s[0]) << 0);
 }
 
@@ -188,7 +188,7 @@ static inline void write_at_le16(void *dest, uint16_t val, size_t offset)
 
 static inline uint32_t read_le32(const void *src)
 {
-	const uint8_t *s = src;
+	const volatile uint8_t *s = src;
 	return (((uint32_t)s[3]) << 24) | (((uint32_t)s[2]) << 16) |
 		(((uint32_t)s[1]) << 8) | (((uint32_t)s[0]) << 0);
 }

From 50c39b3a22a3ae0bf61eb296d16a1b2524ae2188 Mon Sep 17 00:00:00 2001
From: "peng.eren" <peng.eren@inventec.corp-partner.google.com>
Date: Thu, 10 Jul 2025 13:27:59 +0800
Subject: [PATCH 1636/3886] mb/google/trulo/var/kaladin: Fix Type C function

Fix Type C USB and display function

BUG=b:429267772
TEST=Build and flash to DUT, verify Type C USB and display function works

Change-Id: I37af5f4608b2756f0918a6b544b53818d1e45d63
Signed-off-by: Eren Peng <peng.eren@inventec.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88374
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 .../google/brya/variants/kaladin/Makefile.mk  |  1 +
 .../google/brya/variants/kaladin/fw_config.c  |  9 +++
 .../google/brya/variants/kaladin/gpio.c       | 16 ++---
 .../brya/variants/kaladin/overridetree.cb     | 69 ++++++++++++-------
 4 files changed, 62 insertions(+), 33 deletions(-)
 create mode 100644 src/mainboard/google/brya/variants/kaladin/fw_config.c

diff --git a/src/mainboard/google/brya/variants/kaladin/Makefile.mk b/src/mainboard/google/brya/variants/kaladin/Makefile.mk
index cc61780e02..936c557f19 100644
--- a/src/mainboard/google/brya/variants/kaladin/Makefile.mk
+++ b/src/mainboard/google/brya/variants/kaladin/Makefile.mk
@@ -5,3 +5,4 @@ romstage-y += gpio.c
 romstage-y += memory.c
 ramstage-y += gpio.c
 ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_HDA_VERB) += hda_verb.c
+ramstage-$(CONFIG_FW_CONFIG) += fw_config.c
diff --git a/src/mainboard/google/brya/variants/kaladin/fw_config.c b/src/mainboard/google/brya/variants/kaladin/fw_config.c
new file mode 100644
index 0000000000..6db352e3e9
--- /dev/null
+++ b/src/mainboard/google/brya/variants/kaladin/fw_config.c
@@ -0,0 +1,9 @@
+#include <fw_config.h>
+#include <baseboard/variants.h>
+
+void variant_update_soc_chip_config(struct soc_intel_alderlake_config *config)
+{
+	if (fw_config_probe(FW_CONFIG(MB_USB, MB_USB_2C_1A))) {
+		config->tcss_ports[1] = (struct tcss_port_config) TCSS_PORT_DEFAULT(OC_SKIP);
+	}
+}
diff --git a/src/mainboard/google/brya/variants/kaladin/gpio.c b/src/mainboard/google/brya/variants/kaladin/gpio.c
index c43caf380c..0e0518dff5 100644
--- a/src/mainboard/google/brya/variants/kaladin/gpio.c
+++ b/src/mainboard/google/brya/variants/kaladin/gpio.c
@@ -44,10 +44,10 @@ static const struct pad_config gpio_table[] = {
 	PAD_NC(GPP_A19, NONE),
 	/* A20 : NC */
 	PAD_NC(GPP_A20, NONE),
-	/* A21 : USB_C1_AUX_DC_P */
-	PAD_CFG_NF(GPP_A21, NONE, DEEP, NF6),
-	/* A22 : USB_C1_AUX_DC_N */
-	PAD_CFG_NF(GPP_A22, NONE, DEEP, NF6),
+	/* A21 : NC */
+	PAD_NC(GPP_A21, NONE),
+	/* A22 : NC */
+	PAD_NC(GPP_A22, NONE),
 	/* A23 : GPP_A23 ==> NC */
 	PAD_NC(GPP_A23, NONE),
 
@@ -202,10 +202,10 @@ static const struct pad_config gpio_table[] = {
 	PAD_NC(GPP_E20, NONE),
 	/* E21 : DDP2_CTRLDATA ==> NC */
 	PAD_NC(GPP_E21, NONE),
-	/* E22 : DDPA_CTRLCLK ==> USB_C0_AUX_DC_P */
-	PAD_CFG_NF(GPP_E22, NONE, DEEP, NF6),
-	/* E23 : DDPA_CTRLDATA ==> USB_C0_AUX_DC_N */
-	PAD_CFG_NF(GPP_E23, NONE, DEEP, NF6),
+	/* E22 : DDPA_CTRLCLK ==> NC */
+	PAD_NC(GPP_E22, NONE),
+	/* E23 : DDPA_CTRLDATA ==> NC */
+	PAD_NC(GPP_E23, NONE),
 
 	/* F0  : CNV_BRI_DT ==> CNV_BRI_DT_STRAP */
 	PAD_CFG_NF(GPP_F0, NONE, DEEP, NF1),
diff --git a/src/mainboard/google/brya/variants/kaladin/overridetree.cb b/src/mainboard/google/brya/variants/kaladin/overridetree.cb
index 4e97a62f6a..5b720a24e9 100644
--- a/src/mainboard/google/brya/variants/kaladin/overridetree.cb
+++ b/src/mainboard/google/brya/variants/kaladin/overridetree.cb
@@ -3,6 +3,10 @@ fw_config
 		option THERMAL_SOLUTION_6W	0
 		option THERMAL_SOLUTION_15W	1
 	end
+	field MB_USB 2 2
+		option MB_USB_1C_1A 0
+		option MB_USB_2C_1A 1
+	end
 	field STORAGE 30 31
 		option STORAGE_EMMC		0
 		option STORAGE_NVME		1
@@ -40,10 +44,9 @@ chip soc/intel/alderlake
 	register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)"	# Bluetooth port for PCIe WLAN (2.5 inch)
 	register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)"	# Bluetooth port for CNVi WLAN
 
-	register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC1)"	# USB3 Type-A port A0(MLB))
+	register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC1)"	# USB3 Type-A port A0(MLB)
 
 	register "tcss_ports[0]" = "TCSS_PORT_DEFAULT(OC_SKIP)"
-	register "tcss_ports[1]" = "TCSS_PORT_DEFAULT(OC_SKIP)"
 
 	# SOC Aux orientation override:
 	# This is a bitfield that corresponds to up to 4 TCSS ports.
@@ -54,7 +57,6 @@ chip soc/intel/alderlake
 	# motherboard to USBC connector
 	register "tcss_aux_ori" = "0"
 
-
 	# HD Audio
 	register "pch_hda_dsp_enable" = "1"
 	register "pch_hda_audio_link_hda_enable" = "1"
@@ -248,37 +250,42 @@ chip soc/intel/alderlake
 		end
 		device ref igpu on
 			chip drivers/gfx/generic
-				register "device_count" = "4"
+				register "device_count" = "3"
 				# DDIA for eDP
 				register "device[0].name" = ""LCD0""
 				# Internal panel on the first port of the graphics chip
 				register "device[0].type" = "panel"
-				# DDIB for HDMI
-				# If HDMI is not enumerated in the kernel, then no GFX device should be added for DDIB
-				register "device[1].name" = ""DD01""
+				# DDIB is unused and HDMI is not enumerated in the kernel, so no GFX device is added for DDIB
 				# TCP0 (DP-1) for port C0
+				register "device[1].name" = ""DD01""
+				register "device[1].use_pld" = "true"
+				register "device[1].pld" = "ACPI_PLD_TYPE_C(LEFT, RIGHT, ACPI_PLD_GROUP(1, 1))"
+				# TCP1 is unused and not enumerated in the kernel, so no GFX device is added for TCP1
+				# TCP2 (DP-2) for port C1
 				register "device[2].name" = ""DD02""
 				register "device[2].use_pld" = "true"
-				register "device[2].pld" = "ACPI_PLD_TYPE_C(RIGHT, LEFT, ACPI_PLD_GROUP(1, 1))"
-				# TCP1 (DP-2) for port C1
-				register "device[3].name" = ""DD03""
-				register "device[3].use_pld" = "true"
-				register "device[3].pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(2, 1))"
+				register "device[2].pld" = "ACPI_PLD_TYPE_C(RIGHT, LEFT, ACPI_PLD_GROUP(2, 1))"
+				# TCP3 is unused and not enumerated in the kernel, so no GFX device is added for TCP3
 				device generic 0 on end
 			end
-		end
+		end # Integrated Graphics Device
 		device ref pmc hidden
 			chip drivers/intel/pmc_mux
 				device generic 0 on
 					chip drivers/intel/pmc_mux/conn
 						use usb2_port1 as usb2_port
 						use tcss_usb3_port1 as usb3_port
-						device generic 0 alias conn0 on end
+						device generic 0 alias conn0 on
+							probe MB_USB MB_USB_2C_1A
+							probe MB_USB MB_USB_1C_1A
+						end
 					end
 					chip drivers/intel/pmc_mux/conn
 						use usb2_port2 as usb2_port
 						use tcss_usb3_port2 as usb3_port
-						device generic 1 alias conn1 on end
+						device generic 1 alias conn1 on
+							probe MB_USB MB_USB_2C_1A
+						end
 					end
 				end
 			end
@@ -290,15 +297,20 @@ chip soc/intel/alderlake
 						register "desc" = ""USB3 Type-C Port C0 (MLB)""
 						register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
 						register "use_custom_pld" = "true"
-						register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, LEFT, ACPI_PLD_GROUP(1, 1))"
-						device ref tcss_usb3_port1 on end
+						register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, RIGHT, ACPI_PLD_GROUP(1, 1))"
+						device ref tcss_usb3_port1 on
+							probe MB_USB MB_USB_2C_1A
+							probe MB_USB MB_USB_1C_1A
+						end
 					end
 					chip drivers/usb/acpi
 						register "desc" = ""USB3 Type-C Port C1 (DB)""
 						register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
 						register "use_custom_pld" = "true"
-						register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(2, 1))"
-						device ref tcss_usb3_port2 on end
+						register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, LEFT, ACPI_PLD_GROUP(2, 1))"
+						device ref tcss_usb3_port2 on
+							probe MB_USB MB_USB_2C_1A
+						end
 					end
 				end
 			end
@@ -310,21 +322,26 @@ chip soc/intel/alderlake
 						register "desc" = ""USB2 Type-C Port C0 (MLB)""
 						register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
 						register "use_custom_pld" = "true"
-						register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, LEFT, ACPI_PLD_GROUP(1, 1))"
-						device ref usb2_port1 on end
+						register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, RIGHT, ACPI_PLD_GROUP(1, 1))"
+						device ref usb2_port1 on
+							probe MB_USB MB_USB_2C_1A
+							probe MB_USB MB_USB_1C_1A
+						end
 					end
 					chip drivers/usb/acpi
 						register "desc" = ""USB2 Type-C Port C1 (DB)""
 						register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
 						register "use_custom_pld" = "true"
-						register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(2, 1))"
-						device ref usb2_port2 on end
+						register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, LEFT, ACPI_PLD_GROUP(2, 1))"
+						device ref usb2_port2 on
+							probe MB_USB MB_USB_2C_1A
+						end
 					end
 					chip drivers/usb/acpi
 						register "desc" = ""USB2 Type-A Port A0 (MLB)""
 						register "type" = "UPC_TYPE_A"
 						register "use_custom_pld" = "true"
-						register "custom_pld" = "ACPI_PLD_TYPE_A(RIGHT, RIGHT, ACPI_PLD_GROUP(3, 1))"
+						register "custom_pld" = "ACPI_PLD_TYPE_A(LEFT, LEFT, ACPI_PLD_GROUP(3, 1))"
 						device ref usb2_port3 on end
 					end
 					chip drivers/usb/acpi
@@ -350,7 +367,7 @@ chip soc/intel/alderlake
 						register "desc" = ""USB3 Type-A Port A0 (MLB)""
 						register "type" = "UPC_TYPE_USB3_A"
 						register "use_custom_pld" = "true"
-						register "custom_pld" = "ACPI_PLD_TYPE_A(RIGHT, RIGHT, ACPI_PLD_GROUP(3, 1))"
+						register "custom_pld" = "ACPI_PLD_TYPE_A(LEFT, LEFT, ACPI_PLD_GROUP(3, 1))"
 						device ref usb3_port1 on end
 					end
 					chip drivers/usb/acpi
@@ -458,6 +475,8 @@ chip soc/intel/alderlake
 		device ref uart0 on end
 		device ref pch_espi on
 			chip ec/google/chromeec
+				use conn0 as mux_conn[0]
+				use conn1 as mux_conn[1]
 				device pnp 0c09.0 on end
 			end
 		end

From f13f980e0380ee6ae0442d6a7727c65f378f6061 Mon Sep 17 00:00:00 2001
From: "peng.eren" <peng.eren@inventec.corp-partner.google.com>
Date: Tue, 15 Jul 2025 10:17:05 +0800
Subject: [PATCH 1637/3886] mb/google/trulo/var/kaladin: Add fw_config probe
 for storage

Add FW Config probe for storage

BUG=b:430725546
TEST=Flash and boot on NVMe,eMMC,UFS

Change-Id: I7a200124930d0191f9c6f488444c052d803dfa70
Signed-off-by: peng.eren <peng.eren@inventec.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88430
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
---
 .../google/brya/variants/kaladin/overridetree.cb     | 12 ++++++++++--
 1 file changed, 10 insertions(+), 2 deletions(-)

diff --git a/src/mainboard/google/brya/variants/kaladin/overridetree.cb b/src/mainboard/google/brya/variants/kaladin/overridetree.cb
index 5b720a24e9..960705d539 100644
--- a/src/mainboard/google/brya/variants/kaladin/overridetree.cb
+++ b/src/mainboard/google/brya/variants/kaladin/overridetree.cb
@@ -387,7 +387,10 @@ chip soc/intel/alderlake
 				device generic 0 on end
 			end
 		end
-		device ref emmc on end
+		device ref emmc on
+			probe STORAGE STORAGE_EMMC
+			probe STORAGE STORAGE_UNKNOWN
+		end
 		device ref pcie_rp4 on
 			# PCIe 4 WLAN
 			register "pch_pcie_rp[PCH_RP(4)]" = "{
@@ -415,6 +418,8 @@ chip soc/intel/alderlake
 				.clk_req = 0,
 				.flags = PCIE_RP_LTR | PCIE_RP_AER,
 			}"
+			probe STORAGE STORAGE_NVME
+			probe STORAGE STORAGE_UNKNOWN
 		end
 
 		device ref i2c0 on
@@ -471,7 +476,10 @@ chip soc/intel/alderlake
 				device generic 0 on end
 			end
 		end
-		device ref ufs on end
+		device ref ufs on
+			probe STORAGE STORAGE_UFS
+			probe STORAGE STORAGE_UNKNOWN
+		end
 		device ref uart0 on end
 		device ref pch_espi on
 			chip ec/google/chromeec

From c1d45ef93b8db649390b0c3c71308150ef96d446 Mon Sep 17 00:00:00 2001
From: "peng.eren" <peng.eren@inventec.corp-partner.google.com>
Date: Tue, 15 Jul 2025 10:42:58 +0800
Subject: [PATCH 1638/3886] mb/google/trulo/var/kaladin: Update touchpad
 settings

Update touchpad settings

BUG=b:431870030
TEST=Flash and boot on DUT, touchpad works normally

Change-Id: If3eefd5041e06b25dd1945a40fd2aa95186efc4a
Signed-off-by: peng.eren <peng.eren@inventec.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88431
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
---
 .../google/brya/variants/kaladin/overridetree.cb    | 13 ++++++-------
 1 file changed, 6 insertions(+), 7 deletions(-)

diff --git a/src/mainboard/google/brya/variants/kaladin/overridetree.cb b/src/mainboard/google/brya/variants/kaladin/overridetree.cb
index 960705d539..cd264f6de5 100644
--- a/src/mainboard/google/brya/variants/kaladin/overridetree.cb
+++ b/src/mainboard/google/brya/variants/kaladin/overridetree.cb
@@ -449,13 +449,12 @@ chip soc/intel/alderlake
 			end
 		end #I2C1
 		device ref i2c5 on
-			chip drivers/i2c/hid
-				register "generic.hid" = ""ELAN0000""
-				register "generic.desc" = ""ELAN Touchpad""
-				register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_F14_IRQ)"
-				register "generic.wake" = "GPE0_DW2_14"
-				register "generic.detect" = "1"
-				register "hid_desc_reg_offset" = "0x01"
+			chip drivers/i2c/generic
+				register "hid" = ""ELAN0000""
+				register "desc" = ""ELAN Touchpad""
+				register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_F14_IRQ)"
+				register "wake" = "GPE0_DW2_14"
+				register "detect" = "1"
 				device i2c 15 on end
 			end
 			chip drivers/i2c/hid

From 9e41c7cec791d84b079251065add7dba66662913 Mon Sep 17 00:00:00 2001
From: Jeremy Compostella <jeremy.compostella@intel.com>
Date: Fri, 18 Jul 2025 13:12:56 -0700
Subject: [PATCH 1639/3886] soc/intel/cmn/block/fast_spi: Lock DMA before
 exiting coreboot

Introduce a DMA lock mechanism to secure the Fast SPI DMA operations
during the payload boot phase. A new `fast_spi_dma_lock` function is
added to lock the DMA control register when the system enters the
payload boot state. This ensures that DMA operations are appropriately
secured, preventing any unintended data transfers post-boot.

TEST=On a Fatcat device with an FSP not locking down Fast SPI DMA,
     coreboot logs show "Fast-SPI: DMA has been locked." and
     /sys/devices/pci0000:00/0000:00:1f.5/config shows that bit 15 of
     register FAST_SPI_DMA_CONTROL (0xbc) has been is set.

Change-Id: Ie4abbcfc798480319a32b0049e3559d623ef78ef
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88488
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/soc/intel/common/block/fast_spi/fast_spi_dma.c | 14 ++++++++++++++
 1 file changed, 14 insertions(+)

diff --git a/src/soc/intel/common/block/fast_spi/fast_spi_dma.c b/src/soc/intel/common/block/fast_spi/fast_spi_dma.c
index c21056aa18..c6bf38c7d4 100644
--- a/src/soc/intel/common/block/fast_spi/fast_spi_dma.c
+++ b/src/soc/intel/common/block/fast_spi/fast_spi_dma.c
@@ -403,3 +403,17 @@ void spi_flash_dma_install_ops(struct xlate_region_device *mmap_xlate_rdev)
 	fast_spi_dma_rdev_ro_ops.readat = fast_spi_dma_readat;
 	mmap_xlate_rdev->rdev.ops = &fast_spi_dma_rdev_ro_ops;
 }
+
+static void fast_spi_dma_lock(void *unused)
+{
+	union fast_spi_dma_control control = {fast_spi_read(FAST_SPI_DMA_CONTROL)};
+	if (control.fields.lock)
+		return;
+
+	control.fields.lock = 1;
+	fast_spi_write(FAST_SPI_DMA_CONTROL, control.data);
+
+	printk(BIOS_DEBUG, "Fast-SPI: driver locked DMA\n");
+}
+
+BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_BOOT, BS_ON_ENTRY, fast_spi_dma_lock, NULL);

From da33feeb510410c4885f22ebafc7375479babc45 Mon Sep 17 00:00:00 2001
From: Raymond Sun <raymond.sun@mediatek.corp-partner.google.com>
Date: Tue, 22 Jul 2025 14:38:05 +0800
Subject: [PATCH 1640/3886] soc/mediatek/mt8189: Correct thermal SRAM base
 address and length

A recent code review reveals incorrect SRAM base address and length
settings from the thermal driver refactor. This causes incorrect initial
values in SRAM and leads to CPU DVFS not working properly. After
correction, the CPU DVFS voltage and clock operate normally.

BUG=b:428613901
BRANCH=none
TEST=Clocks fm_armpll_ll_ck (LITTLE) and fm_armpll_bl_ck (big) are
correct. Voltages: vbuck1 (big) <1100mV, vmodem (LITTLE) <1050mV.
echo 2000000 > /sys/devices/system/cpu/cpufreq/policy0/scaling_max_freq
echo 2000000 > /sys/devices/system/cpu/cpufreq/policy0/scaling_min_freq
echo 2600000 > /sys/devices/system/cpu/cpufreq/policy6/scaling_min_freq
echo 2600000 > /sys/devices/system/cpu/cpufreq/policy6/scaling_max_freq
clkdbg() { echo $@ > /proc/clkdbg ; cat /proc/clkdbg ; }
clkdbg fmeter | grep armpll
cat /sys/kernel/debug/regulator/regulator_summary | grep buck1
cat /sys/kernel/debug/regulator/regulator_summary | grep modem
 6: fm_armpll_bl_ck              : 2600000
 8: fm_armpll_ll_ck              : 1999968
 vbuck1                           1    0      0  normal  1037mV     0mA     0mV     0mV
 vmodem                           1    0      0  normal  1043mV     0mA   400mV  1100mV

Signed-off-by: Raymond Sun <raymond.sun@mediatek.corp-partner.google.com>
Change-Id: I5caebb27a47d7b19330ec8ac23e20a6efe23e940
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88530
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
---
 src/soc/mediatek/mt8189/include/soc/thermal_internal.h | 5 ++---
 1 file changed, 2 insertions(+), 3 deletions(-)

diff --git a/src/soc/mediatek/mt8189/include/soc/thermal_internal.h b/src/soc/mediatek/mt8189/include/soc/thermal_internal.h
index 562cb9fa27..617a706627 100644
--- a/src/soc/mediatek/mt8189/include/soc/thermal_internal.h
+++ b/src/soc/mediatek/mt8189/include/soc/thermal_internal.h
@@ -34,9 +34,8 @@
 #define STAGE3_INT_EN			BIT(31)
 
 /* SRAM for Thermal */
-#define THERMAL_ATC_SRAM_OFFSET		0x280
-#define THERMAL_SRAM_BASE		(_thermal_reserved + THERMAL_ATC_SRAM_OFFSET)
-#define THERMAL_SRAM_LEN		(24 * 4)
+#define THERMAL_SRAM_BASE		_thermal_reserved
+#define THERMAL_SRAM_LEN		REGION_SIZE(thermal_reserved)
 #define THERMAL_STAT_SRAM_BASE		_cpucooler_reserved
 #define THERMAL_STAT_SRAM_LEN		REGION_SIZE(cpucooler_reserved)
 

From 3b008bde8c8a00089d4e8ada724b34aa02845876 Mon Sep 17 00:00:00 2001
From: Bincai Liu <bincai.liu@mediatek.corp-partner.google.com>
Date: Fri, 4 Jul 2025 17:12:20 +0800
Subject: [PATCH 1641/3886] soc/mediatek/mt8196: Fix intermittent black screen
 issue

Currently we set DP_PHY_DIG_TX_CTL_0 during the PHYD reset flow.
However, that would cause the training to fail and result in
intermittent black screen issues.

As suggested by the eDP PHYD designer, the reset procedure should be
refined by setting bit 0 of DP_PHY_DIG_SW_RST from 0 to 1 to reset the
eDP PHYD status before training. DP_PHY_DIG_TX_CTL_0 controls the eDP
PHYD lane count: setting BIT0 enables lane0, and setting BIT1 enables
lane1. The eDP PHYD designer also recommends that when resetting PHYD,
it is sufficient to set DP_GLB_SW_RST_PHYD and leave DP_PHY_DIG_TX_CTL_0
unchanged.

After this change, this function is identical to the mt8189
implementation. Move dptx_hal_phyd_reset code to common for reuse.

BUG=b:427119942
BRANCH:rauru
TEST=Check the display function on Navi

Change-Id: I07bd6203a2b957eea79d1431953b043820c00338
Signed-off-by: Jarried Lin <jarried.lin@mediatek.corp-partner.google.com>
Signed-off-by: Bincai Liu <bincai.liu@mediatek.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88450
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/soc/mediatek/common/dp/dptx_hal_v2.c |  9 +++++++++
 src/soc/mediatek/mt8189/dptx_hal.c       |  9 ---------
 src/soc/mediatek/mt8196/dptx_hal.c       | 21 ---------------------
 3 files changed, 9 insertions(+), 30 deletions(-)

diff --git a/src/soc/mediatek/common/dp/dptx_hal_v2.c b/src/soc/mediatek/common/dp/dptx_hal_v2.c
index 0833f2de62..628af99112 100644
--- a/src/soc/mediatek/common/dp/dptx_hal_v2.c
+++ b/src/soc/mediatek/common/dp/dptx_hal_v2.c
@@ -339,3 +339,12 @@ void dptx_hal_phy_set_idle_pattern(struct mtk_dp *mtk_dp, u8 lane_count, bool en
 	mtk_dp_mask(mtk_dp, REG_3580_DP_TRANS_P0, (enable ? val : 0x0) << 8,
 		    POST_MISC_DATA_LANE_OV_DP_TRANS_4P_MASK);
 }
+
+void dptx_hal_phyd_reset(struct mtk_dp *mtk_dp)
+{
+	mtk_dp_phy_mask(mtk_dp, DP_PHY_DIG_SW_RST, 0, BIT(0));
+	udelay(10);
+	mtk_dp_phy_mask(mtk_dp, DP_PHY_DIG_SW_RST, BIT(0), BIT(0));
+
+	dptx_hal_reset_swing_preemphasis(mtk_dp);
+}
diff --git a/src/soc/mediatek/mt8189/dptx_hal.c b/src/soc/mediatek/mt8189/dptx_hal.c
index 552f79b7cd..3fa3955f55 100644
--- a/src/soc/mediatek/mt8189/dptx_hal.c
+++ b/src/soc/mediatek/mt8189/dptx_hal.c
@@ -26,12 +26,3 @@ void dptx_hal_phy_set_lanes(struct mtk_dp *mtk_dp, u8 lane_count)
 	mtk_dp_phy_mask(mtk_dp, PHYD_DIG_GLB_OFFSET + 0x44,
 			GENMASK(4 + lane_count - 1, 4), GENMASK(7, 4));
 }
-
-void dptx_hal_phyd_reset(struct mtk_dp *mtk_dp)
-{
-	mtk_dp_phy_mask(mtk_dp, DP_PHY_DIG_SW_RST, 0, BIT(0));
-	udelay(10);
-	mtk_dp_phy_mask(mtk_dp, DP_PHY_DIG_SW_RST, BIT(0), BIT(0));
-
-	dptx_hal_reset_swing_preemphasis(mtk_dp);
-}
diff --git a/src/soc/mediatek/mt8196/dptx_hal.c b/src/soc/mediatek/mt8196/dptx_hal.c
index 110f5f1ada..9fe8571231 100644
--- a/src/soc/mediatek/mt8196/dptx_hal.c
+++ b/src/soc/mediatek/mt8196/dptx_hal.c
@@ -18,24 +18,3 @@ void dptx_hal_phy_set_lanes(struct mtk_dp *mtk_dp, u8 lane_count)
 	for (int i = 0; i < lane_count; i++)
 		mtk_dp_phy_mask(mtk_dp, PHYD_DIG_GLB_OFFSET + 0x74, BIT(i), BIT(i));
 }
-
-void dptx_hal_phyd_reset(struct mtk_dp *mtk_dp)
-{
-	u32 val;
-
-	mtk_dp_phy_mask(mtk_dp, DP_PHY_DIG_SW_RST, 0, BIT(0));
-	udelay(10);
-	mtk_dp_phy_mask(mtk_dp, DP_PHY_DIG_SW_RST, BIT(0), BIT(0));
-	val = mtk_dp_phy_read(mtk_dp, DP_PHY_DIG_TX_CTL_0) & 0xF;
-	printk(BIOS_DEBUG, "[eDPTX] DP_PHY_DIG_TX_CTL_0:%#x\n", val);
-
-	while (val > 0) {
-		val >>= 1;
-		mtk_dp_phy_mask(mtk_dp, DP_PHY_DIG_TX_CTL_0, val, 0xF);
-		printk(BIOS_DEBUG, "[eDPTX] DP_PHY_DIG_TX_CTL_0:%#x\n", val);
-	}
-	printk(BIOS_DEBUG, "[eDPTX] DP_PHY_DIG_TX_CTL_0:%#x\n",
-	       mtk_dp_phy_read(mtk_dp, DP_PHY_DIG_TX_CTL_0));
-
-	dptx_hal_reset_swing_preemphasis(mtk_dp);
-}

From 69888bc7fca5a55dca5282b02eef165e2c61b3ef Mon Sep 17 00:00:00 2001
From: Patrick Rudolph <patrick.rudolph@9elements.com>
Date: Tue, 15 Apr 2025 09:37:28 +0200
Subject: [PATCH 1642/3886] util/cbfstool/amdcompress: Bail out on invalid ELF

Ensure that only one PT_LOAD segment is inside the input ELF as
the tool only expects and support one PT_LOAD segment. Instead of silently
discarding all other PT_LOAD segments than the first throw an error.

Change-Id: I90cfc8b9dd0b5e8060880790e5ff0ce73843943b
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87315
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 .../common/block/cpu/noncar/memlayout_x86.ld   |  5 +++--
 util/cbfstool/amdcompress.c                    | 18 +++++++++++++++++-
 2 files changed, 20 insertions(+), 3 deletions(-)

diff --git a/src/soc/amd/common/block/cpu/noncar/memlayout_x86.ld b/src/soc/amd/common/block/cpu/noncar/memlayout_x86.ld
index 4372de8760..024afbe7e5 100644
--- a/src/soc/amd/common/block/cpu/noncar/memlayout_x86.ld
+++ b/src/soc/amd/common/block/cpu/noncar/memlayout_x86.ld
@@ -137,8 +137,9 @@ SECTIONS {
 	 * .text and .reset breaks the integrity, as .bss or .data might get modified.
 	 *
 	 * Enable ENV_SEPARATE_DATA_AND_BSS for AMD's bootblock and mark as
-	 * data_segment to place it in the second PT_LOAD area. AMDCOMPRESS will ignore
-	 * the second PT_LOAD area and discard it.
+	 * data_segment to place it in the second PT_LOAD area. The second PT_LOAD area
+	 * must be removed using objcopy since AMDCOMPRESS doesn't support multiple
+	 * PT_LOAD segments.
 	 */
 	. = BOOTBLOCK_ADDR & ~(16 - 1);
 	.data . : {
diff --git a/util/cbfstool/amdcompress.c b/util/cbfstool/amdcompress.c
index 76089ea340..9b778cbc07 100644
--- a/util/cbfstool/amdcompress.c
+++ b/util/cbfstool/amdcompress.c
@@ -75,12 +75,28 @@ static int do_file(char *name, size_t *size, int oflag)
 }
 
 static int parse_elf_to_xip_ram(const struct buffer *input,
-					struct buffer *output)
+				struct buffer *output)
 {
 	struct parsed_elf pelf;
+	const Elf64_Phdr *phdr;
 
 	if (parse_elf(input, &pelf, ELF_PARSE_ALL))
 		return 1;
+
+	/* Validate ELF. Expect only on PT_LOAD program header at index 0. */
+	for (int i = 0; i < pelf.ehdr.e_phnum; i++) {
+		phdr = &pelf.phdr[i];
+		/* Expect PT_LOAD on first entry */
+		if (i == 0 && (phdr->p_type != PT_LOAD || !phdr->p_memsz)) {
+			printf("\tProgram header #0 is invalid.\n");
+		}
+		/* Expect not to find more PT_LOAD program headers */
+		if (i > 0 && phdr->p_type == PT_LOAD && phdr->p_memsz) {
+			printf("\tMultiple program headers found, but only one is supported!\n");
+			return 1;
+		}
+	}
+
 	if (buffer_create(output, pelf.phdr->p_filesz, "") != 0)
 		return 1;
 

From b6425a9a787997133520f92206fb8bd8e3376958 Mon Sep 17 00:00:00 2001
From: Patrick Rudolph <patrick.rudolph@9elements.com>
Date: Mon, 14 Apr 2025 08:09:53 +0200
Subject: [PATCH 1643/3886] soc/amd/common: Add comments about bootblock

Since the boot flow is different on AMD compared to other x86
platforms document what is done and where.

Explain that AMDCOMPRESS does more than compressing the input.
It also parses the input as an ELF and extracts the first PT_LOAD marked
area from it and discards all other information from the ELF.

Explain bootblock.bin generation and that it has not much to do
with bootblock.elf, unlike on other platforms.
While on it also fix a whitespace in the following line.

Change-Id: Ida763f879c133be54ea1ca2abd3059db0d2c1ef7
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87316
Reviewed-by: Alexander Goncharov <chat@joursoir.net>
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
---
 Documentation/soc/amd/psp_integration.md | 14 ++++++++++++--
 src/soc/amd/cezanne/Makefile.mk          |  7 +++++++
 src/soc/amd/common/Makefile.mk           |  6 +++++-
 src/soc/amd/genoa_poc/Makefile.mk        |  7 +++++++
 src/soc/amd/glinda/Makefile.mk           |  7 +++++++
 src/soc/amd/mendocino/Makefile.mk        |  7 +++++++
 src/soc/amd/phoenix/Makefile.mk          |  7 +++++++
 src/soc/amd/picasso/Makefile.mk          |  7 +++++++
 8 files changed, 59 insertions(+), 3 deletions(-)

diff --git a/Documentation/soc/amd/psp_integration.md b/Documentation/soc/amd/psp_integration.md
index 74f35b9e2e..3606753838 100644
--- a/Documentation/soc/amd/psp_integration.md
+++ b/Documentation/soc/amd/psp_integration.md
@@ -382,8 +382,18 @@ The BIOS Directory table structure is slightly different from the PSP Directory:
 `cbfstool/amdcompress` is a helper for creating the BIOS Reset Image (BIOS
 Directory Table type 0x62).  This is the code the PSP uncompresses into DRAM
 at the location where the x86 begins execution when released from reset.
-Typical usage is for amdcompress to convert an ELF file’s program section
-into a zlib compressed image.
+To tool expects an ELF as input (the bootblock.elf) and extracts the **first**
+`PT_LOAD` area out of it. Since only `PT_LOAD` contains what's needed, everything
+else can be discarded from the input ELF when the following points are valid:
+* The binary is loaded at the address it is linked for
+  This is done by the PSP at boot time.
+* The BSS segment is cleared
+  This is not done by PSP, but by bootblock assembly code.
+* The data segment is initialized
+  Done automatically when it's part of `PT_LOAD` area or done by bootblock assembly code
+  when `ENV_SEPARATE_DATA_AND_BSS` is set
+
+Amdcompress finally compresses the ELF file’s `PT_LOAD` section into a zlib compressed image.
 
 ### amdfwtool
 
diff --git a/src/soc/amd/cezanne/Makefile.mk b/src/soc/amd/cezanne/Makefile.mk
index ee193e1bf2..80a877a978 100644
--- a/src/soc/amd/cezanne/Makefile.mk
+++ b/src/soc/amd/cezanne/Makefile.mk
@@ -231,6 +231,13 @@ $(obj)/amdfw.rom:	$(call strip_quotes, $(PSP_BIOSBIN_FILE)) \
 		--multilevel \
 		--output $@
 
+#
+# Extracts everything from the ELF's first PT_LOAD area and compresses it.
+# This discards everything before PT_LOAD, every symbol, debug information
+# and relocations. The generated binary is expected to run at PSP_BIOSBIN_DEST
+# with a maximum size of PSP_BIOSBIN_SIZE. The entrypoint is fixed at
+# PSP_BIOSBIN_DEST + PSP_BIOSBIN_SIZE - 0x10.
+#
 $(PSP_BIOSBIN_FILE): $(PSP_ELF_FILE) $(AMDCOMPRESS)
 	rm -f $@
 	@printf "    AMDCOMPRS  $(subst $(obj)/,,$(@))\n"
diff --git a/src/soc/amd/common/Makefile.mk b/src/soc/amd/common/Makefile.mk
index db60c01b87..5d41968493 100644
--- a/src/soc/amd/common/Makefile.mk
+++ b/src/soc/amd/common/Makefile.mk
@@ -39,6 +39,10 @@ DEP_FILES = $(patsubst %,$(FIRMWARE_LOCATION)/%, $(AMDFW_CFG_IN_FW_LOC)) \
 	$(AMDFW_CFG_WITH_PATH)
 
 ifeq ($(CONFIG_RESET_VECTOR_IN_RAM),y)
+# Even though the target is called bootblock.bin it's way more than that,
+# but the name is mandatory for the 'add_bootblock' directive below.
+# On AMD the bootblock resides within the AMD FW as part of the
+# Bios Directory Tables (BDT), thus about 1% of this file is actually the bootblock.
 $(objcbfs)/bootblock.bin: $(obj)/amdfw.rom $(obj)/fmap_config.h
 	cp $< $@
 
@@ -49,7 +53,7 @@ amdfw_offset=$(call int-subtract, \
 
 add_bootblock = \
 	$(CBFSTOOL) $(1) add -f $(2) -n apu/amdfw -t amdfw \
-        -b $(amdfw_offset) -r $(call regions-for-file,apu/amdfw) \
+	-b $(amdfw_offset) -r $(call regions-for-file,apu/amdfw) \
 	$(CBFSTOOL_ADD_CMD_OPTIONS)
 
 endif # ifeq ($(CONFIG_RESET_VECTOR_IN_RAM),y)
diff --git a/src/soc/amd/genoa_poc/Makefile.mk b/src/soc/amd/genoa_poc/Makefile.mk
index 6e98378542..162180dec4 100644
--- a/src/soc/amd/genoa_poc/Makefile.mk
+++ b/src/soc/amd/genoa_poc/Makefile.mk
@@ -144,6 +144,13 @@ $(obj)/amdfw.rom:	$(call strip_quotes, $(PSP_BIOSBIN_FILE)) \
 		--multilevel \
 		--output $@
 
+#
+# Extracts everything from the ELF's first PT_LOAD area and compresses it.
+# This discards everything before PT_LOAD, every symbol, debug information
+# and relocations. The generated binary is expected to run at PSP_BIOSBIN_DEST
+# with a maximum size of PSP_BIOSBIN_SIZE. The entrypoint is fixed at
+# PSP_BIOSBIN_DEST + PSP_BIOSBIN_SIZE - 0x10.
+#
 $(PSP_BIOSBIN_FILE): $(PSP_ELF_FILE) $(AMDCOMPRESS)
 	rm -f $@
 	@printf "    AMDCOMPRS  $(subst $(obj)/,,$(@))\n"
diff --git a/src/soc/amd/glinda/Makefile.mk b/src/soc/amd/glinda/Makefile.mk
index f4c55c6e33..e0ce02c666 100644
--- a/src/soc/amd/glinda/Makefile.mk
+++ b/src/soc/amd/glinda/Makefile.mk
@@ -250,6 +250,13 @@ $(obj)/amdfw.rom:	$(call strip_quotes, $(PSP_BIOSBIN_FILE)) \
 		--location $(CONFIG_AMD_FWM_POSITION) \
 		--output $@
 
+#
+# Extracts everything from the ELF's first PT_LOAD area and compresses it.
+# This discards everything before PT_LOAD, every symbol, debug information
+# and relocations. The generated binary is expected to run at PSP_BIOSBIN_DEST
+# with a maximum size of PSP_BIOSBIN_SIZE. The entrypoint is fixed at
+# PSP_BIOSBIN_DEST + PSP_BIOSBIN_SIZE - 0x10.
+#
 $(PSP_BIOSBIN_FILE): $(PSP_ELF_FILE) $(AMDCOMPRESS)
 	rm -f $@
 	@printf "    AMDCOMPRS  $(subst $(obj)/,,$(@))\n"
diff --git a/src/soc/amd/mendocino/Makefile.mk b/src/soc/amd/mendocino/Makefile.mk
index b8fec5701c..4f93e490a4 100644
--- a/src/soc/amd/mendocino/Makefile.mk
+++ b/src/soc/amd/mendocino/Makefile.mk
@@ -284,6 +284,13 @@ $(PSP_BIOSBIN_FILE): $(PSP_ELF_FILE)
 	rm -f $@
 	$(OBJCOPY_bootblock) -O binary $< $@
 else
+#
+# Extracts everything from the ELF's first PT_LOAD area and compresses it.
+# This discards everything before PT_LOAD, every symbol, debug information
+# and relocations. The generated binary is expected to run at PSP_BIOSBIN_DEST
+# with a maximum size of PSP_BIOSBIN_SIZE. The entrypoint is fixed at
+# PSP_BIOSBIN_DEST + PSP_BIOSBIN_SIZE - 0x10.
+#
 $(PSP_BIOSBIN_FILE): $(PSP_ELF_FILE) $(AMDCOMPRESS)
 	rm -f $@
 	@printf "    AMDCOMPRS  $(subst $(obj)/,,$(@))\n"
diff --git a/src/soc/amd/phoenix/Makefile.mk b/src/soc/amd/phoenix/Makefile.mk
index 21f10c56b9..672e10fb8d 100644
--- a/src/soc/amd/phoenix/Makefile.mk
+++ b/src/soc/amd/phoenix/Makefile.mk
@@ -285,6 +285,13 @@ $(call add_intermediate, add_amdfwbody, $(obj)/amdfw.rom.body)
 	$(CBFSTOOL) $(obj)/coreboot.pre write -r AMDFWBODY -f $(obj)/amdfw.rom.body --fill-upward
 endif
 
+#
+# Extracts everything from the ELF's first PT_LOAD area and compresses it.
+# This discards everything before PT_LOAD, every symbol, debug information
+# and relocations. The generated binary is expected to run at PSP_BIOSBIN_DEST
+# with a maximum size of PSP_BIOSBIN_SIZE. The entrypoint is fixed at
+# PSP_BIOSBIN_DEST + PSP_BIOSBIN_SIZE - 0x10.
+#
 $(PSP_BIOSBIN_FILE): $(PSP_ELF_FILE) $(AMDCOMPRESS)
 	rm -f $@
 	@printf "    AMDCOMPRS  $(subst $(obj)/,,$(@))\n"
diff --git a/src/soc/amd/picasso/Makefile.mk b/src/soc/amd/picasso/Makefile.mk
index 0b574db845..3f4395478b 100644
--- a/src/soc/amd/picasso/Makefile.mk
+++ b/src/soc/amd/picasso/Makefile.mk
@@ -238,6 +238,13 @@ $(obj)/amdfw.rom:	$(call strip_quotes, $(PSP_BIOSBIN_FILE)) \
 		--location $(CONFIG_AMD_FWM_POSITION) \
 		--output $@
 
+#
+# Extracts everything from the ELF's first PT_LOAD area and compresses it.
+# This discards everything before PT_LOAD, every symbol, debug information
+# and relocations. The generated binary is expected to run at PSP_BIOSBIN_DEST
+# with a maximum size of PSP_BIOSBIN_SIZE. The entrypoint is fixed at
+# PSP_BIOSBIN_DEST + PSP_BIOSBIN_SIZE - 0x10.
+#
 $(PSP_BIOSBIN_FILE): $(PSP_ELF_FILE) $(AMDCOMPRESS)
 	rm -f $@
 	@printf "    AMDCOMPRS  $(subst $(obj)/,,$(@))\n"

From debfac6352081e50d6aed3647f87f79364a9060a Mon Sep 17 00:00:00 2001
From: Sowmya Aralguppe <sowmya.aralguppe@intel.com>
Date: Tue, 22 Jul 2025 18:19:06 +0530
Subject: [PATCH 1644/3886] mb/google/ocelot/var/ocelot: Add wake support for
 touchpad

This patch supports wake on touch for touchpad when LPSS I2C interface
is used by overriding GPE DW0 with group GPP_F.

Schematic version: schematic_1433518
Platform Mapping Document : Rev0p86

BUG=b:394208231
TEST= Build Ocelot and verify it compiles without any error.

Change-Id: Id2cc248aacebc0e85d06ad5c63c0605dd72cd05c
Signed-off-by: Sowmya Aralguppe <sowmya.aralguppe@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88534
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Pranava Y N <pranavayn@google.com>
Reviewed-by: Avi Uday <aviuday@google.com>
---
 .../google/ocelot/variants/ocelot/variant.c   | 19 ++++++++++++-------
 1 file changed, 12 insertions(+), 7 deletions(-)

diff --git a/src/mainboard/google/ocelot/variants/ocelot/variant.c b/src/mainboard/google/ocelot/variants/ocelot/variant.c
index c2d2bdded5..cb3908277e 100644
--- a/src/mainboard/google/ocelot/variants/ocelot/variant.c
+++ b/src/mainboard/google/ocelot/variants/ocelot/variant.c
@@ -23,12 +23,14 @@ void variant_update_soc_chip_config(struct soc_intel_pantherlake_config *config)
 	}
 
 	/* Touchscreen and Touchpad WOT support:
-     * +===================+==================+=================+============================+
-     * | Touchscreen       | Touchpad         | PMC_GPE0_DW0    | WOT                        |
-     * +===================+==================+==============================================+
-     * | THC-SPI/THC-I2C   | THC-I2C          | VGPIO           | TS, TP                     |
-     * +===================+==================+=================+============================+
-     */
+	* +===================+==================+=================+========================+
+	* | Touchscreen       | Touchpad         | PMC_GPE0_DW0    | WOT                    |
+	* +===================+==================+=================+========================+
+	* | THC-SPI/THC-I2C   | THC-I2C          | VGPIO           | TS, TP                 |
+	* +===================+==================+=================+========================+
+	* | THC-SPI/THC-I2C   | LPSS-I2C         | GPP_F18         | TP                     |
+	* +===================+==================+=================+========================+
+	*/
 
 	if (fw_config_probe(FW_CONFIG(TOUCHSCREEN, TOUCHSCREEN_THC_I2C))) {
 		config->thc_mode[0] = THC_HID_I2C_MODE;
@@ -36,7 +38,10 @@ void variant_update_soc_chip_config(struct soc_intel_pantherlake_config *config)
 		config->thc_mode[0] = THC_HID_SPI_MODE;
 	}
 
-	if (fw_config_probe(FW_CONFIG(TOUCHPAD, TOUCHPAD_THC_I2C))) {
+	if (fw_config_probe(FW_CONFIG(TOUCHPAD, TOUCHPAD_LPSS_I2C))) {
+		/* touchpad: GPP_F18: GPE0_DW0_18 */
+		config->pmc_gpe0_dw0 = GPP_F;
+	} else if (fw_config_probe(FW_CONFIG(TOUCHPAD, TOUCHPAD_THC_I2C))) {
 		config->thc_mode[1] = THC_HID_I2C_MODE;
 		if (fw_config_probe(FW_CONFIG(TOUCHSCREEN, TOUCHSCREEN_NONE)))
 			/* When THC0 is only enabled due to THC1 is enabled, we force THC0

From 15bf25de78ab5c12c7716f5891125941632c0c1d Mon Sep 17 00:00:00 2001
From: Jincheng Li <jincheng.li@intel.com>
Date: Mon, 21 Jul 2025 13:54:39 +0800
Subject: [PATCH 1645/3886] Documentation/soc/intel: Update the referenced
 linuxboot_defconfig

Changes mainly include:
- Switch kernel compression from LZ4 to LZMA for better compression
  efficiency.
- Support loopback block device.
- Enable SCSI and ATA support.

Change-Id: I1a46a239eead27efa709ee07bf1b85a10cd631b4
Signed-off-by: Jincheng Li <jincheng.li@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88501
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
---
 .../soc/intel/xeon_sp/linuxboot_defconfig         | 15 +++++++++++++--
 1 file changed, 13 insertions(+), 2 deletions(-)

diff --git a/Documentation/soc/intel/xeon_sp/linuxboot_defconfig b/Documentation/soc/intel/xeon_sp/linuxboot_defconfig
index c707372229..938994b08e 100644
--- a/Documentation/soc/intel/xeon_sp/linuxboot_defconfig
+++ b/Documentation/soc/intel/xeon_sp/linuxboot_defconfig
@@ -1,6 +1,7 @@
 # CONFIG_LOCALVERSION_AUTO is not set
-CONFIG_KERNEL_LZ4=y
+CONFIG_KERNEL_LZMA=y
 # CONFIG_CROSS_MEMORY_ATTACH is not set
+CONFIG_IKCONFIG=y
 CONFIG_BLK_DEV_INITRD=y
 CONFIG_INITRAMFS_SOURCE="/tmp/initramfs.linux_amd64.cpio"
 # CONFIG_RD_GZIP is not set
@@ -37,8 +38,8 @@ CONFIG_X86_X2APIC=y
 # CONFIG_X86_EXTENDED_PLATFORM is not set
 # CONFIG_SCHED_OMIT_FRAME_POINTER is not set
 CONFIG_HYPERVISOR_GUEST=y
-# CONFIG_DMI is not set
 CONFIG_MAXSMP=y
+# CONFIG_SCHED_MC is not set
 # CONFIG_X86_MCE is not set
 # CONFIG_PERF_EVENTS_INTEL_UNCORE is not set
 # CONFIG_PERF_EVENTS_INTEL_RAPL is not set
@@ -88,10 +89,18 @@ CONFIG_DEVTMPFS_MOUNT=y
 # CONFIG_PREVENT_FIRMWARE_BUILD is not set
 # CONFIG_ALLOW_DEV_COREDUMP is not set
 # CONFIG_FIRMWARE_MEMMAP is not set
+CONFIG_BLK_DEV_LOOP=y
 CONFIG_BLK_DEV_NVME=y
 CONFIG_NVME_MULTIPATH=y
 CONFIG_NVME_FC=y
 # CONFIG_INTEL_MEI is not set
+CONFIG_BLK_DEV_SD=y
+CONFIG_CHR_DEV_SG=y
+CONFIG_SCSI_DH=y
+CONFIG_ATA=y
+CONFIG_SATA_AHCI=y
+CONFIG_SATA_AHCI_PLATFORM=y
+CONFIG_ATA_GENERIC=y
 CONFIG_NETDEVICES=y
 # CONFIG_NET_VENDOR_3COM is not set
 # CONFIG_NET_VENDOR_ADAPTEC is not set
@@ -174,6 +183,8 @@ CONFIG_SERIAL_8250_RUNTIME_UARTS=1
 # CONFIG_VIRTIO_MENU is not set
 # CONFIG_X86_PLATFORM_DEVICES is not set
 CONFIG_COMMON_CLK=y
+CONFIG_MAILBOX=y
+CONFIG_PCC=y
 CONFIG_INTEL_IOMMU=y
 # CONFIG_INTEL_IOMMU_DEFAULT_ON is not set
 CONFIG_IRQ_REMAP=y

From 4b58ec5ac25a1704e154f99eee2428ad2e4d5017 Mon Sep 17 00:00:00 2001
From: Patrick Rudolph <patrick.rudolph@amd.com>
Date: Tue, 1 Jul 2025 13:51:28 +0200
Subject: [PATCH 1646/3886] soc/amd/common/block/psp: Add fTPM specific bits

Add helper functions for PSP fTPM support.

Signed-off-by: Patrick Rudolph <patrick.rudolph@amd.com>
Change-Id: I5c111bbdda52859381693cb0a15d49f3284a2291
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88355
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
---
 .../amd/common/block/include/amdblocks/psp.h  | 12 +++
 src/soc/amd/common/block/psp/Makefile.mk      |  2 +
 src/soc/amd/common/block/psp/ftpm.c           | 88 +++++++++++++++++++
 src/soc/amd/common/block/psp/psp_def.h        |  3 +
 4 files changed, 105 insertions(+)
 create mode 100644 src/soc/amd/common/block/psp/ftpm.c

diff --git a/src/soc/amd/common/block/include/amdblocks/psp.h b/src/soc/amd/common/block/include/amdblocks/psp.h
index 1ab3385314..40197396fe 100644
--- a/src/soc/amd/common/block/include/amdblocks/psp.h
+++ b/src/soc/amd/common/block/include/amdblocks/psp.h
@@ -4,6 +4,7 @@
 #define AMD_BLOCK_PSP_H
 
 #include <stdint.h>
+#include <stdbool.h>
 
 #define SMM_TRIGGER_IO		0
 #define SMM_TRIGGER_MEM		1
@@ -84,4 +85,15 @@ int psp_load_named_blob(enum psp_blob_type type, const char *name);
 /* Sets the GPIO used for the TPM IRQ */
 void psp_set_tpm_irq_gpio(unsigned int gpio);
 
+/* Returns the fTPM base address, 0 on error. */
+uintptr_t psp_ftpm_base_address(void);
+
+/* Returns true when the fTPM CRB interface is enabled */
+bool psp_ftpm_is_active(void);
+
+/* Returns required recovery actions to be taken */
+void psp_ftpm_needs_recovery(bool *psp_rpmc_nvram,
+			     bool *psp_nvram,
+			     bool *psp_dir);
+
 #endif /* AMD_BLOCK_PSP_H */
diff --git a/src/soc/amd/common/block/psp/Makefile.mk b/src/soc/amd/common/block/psp/Makefile.mk
index dc811f9098..9929d72998 100644
--- a/src/soc/amd/common/block/psp/Makefile.mk
+++ b/src/soc/amd/common/block/psp/Makefile.mk
@@ -11,6 +11,8 @@ smm-y += psp_smm.c
 bootblock-y += psp_efs.c
 verstage-y += psp_efs.c
 
+all-y += ftpm.c
+
 endif # CONFIG_SOC_AMD_COMMON_BLOCK_PSP
 
 ifeq ($(CONFIG_SOC_AMD_COMMON_BLOCK_PSP_GEN1),y)
diff --git a/src/soc/amd/common/block/psp/ftpm.c b/src/soc/amd/common/block/psp/ftpm.c
new file mode 100644
index 0000000000..7e50365f6d
--- /dev/null
+++ b/src/soc/amd/common/block/psp/ftpm.c
@@ -0,0 +1,88 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <amdblocks/psp.h>
+#include <console/console.h>
+#include <device/mmio.h>
+
+#include "psp_def.h"
+
+uintptr_t psp_ftpm_base_address(void)
+{
+	const uintptr_t psp_base = get_psp_mmio_base();
+	if (!psp_base)
+		return 0;
+
+	/* TPM MMIO space starts 0xA0 bytes before MBOX */
+	return psp_base + CONFIG_PSPV2_MBOX_CMD_OFFSET - 0xA0;
+}
+
+/*
+ * psp_ftpm_is_active
+ *
+ * Checks that fTPM CRB interface is available and active.
+ */
+bool psp_ftpm_is_active(void)
+{
+	uint32_t caps = 0;
+
+	/* PSP must report fTPM capability support */
+	if (psp_get_ftpm_capabilties(&caps) != CB_SUCCESS)
+		return false;
+
+	if (!(caps & MBOX_FTPM_CAP_TPM_SUPPORTED))
+		return false;
+
+	/* Must have valid MMIO base address */
+	if (!psp_ftpm_base_address())
+		return false;
+
+	return true;
+}
+
+/*
+ * psp_ftpm_needs_recovery
+ *
+ * Checks the PSP and returns the necessary recovery actions
+ * to be taken. Recovery actions involve erasing parts of the SPI flash
+ * and might possibly erase TPM secrets, preventing unsealing of
+ * the OS.
+ *
+ * @psp_rpmc_nvram The PSP_RPMC_NVRAM FMAP regions must be cleared
+ * @psp_nvram The PSP_NVRAM FMAP regions must be cleared
+ * @psp_dir The fTPM driver in the PSP directory is missing or corrupted
+ */
+void psp_ftpm_needs_recovery(bool *psp_rpmc_nvram,
+			     bool *psp_nvram,
+			     bool *psp_dir)
+{
+	uint32_t psp_caps;
+	uint32_t caps;
+
+	*psp_rpmc_nvram = false;
+	*psp_nvram = false;
+	*psp_dir = false;
+
+	if (psp_get_psp_capabilities(&psp_caps) != CB_SUCCESS) {
+		printk(BIOS_ERR, "FTPM: Failed to get PSP capabilities\n");
+		return;
+	}
+
+	if (psp_get_ftpm_capabilties(&caps) != CB_SUCCESS) {
+		printk(BIOS_ERR, "FTPM: Failed to get fTPM capabilities\n");
+		return;
+	}
+
+	if ((psp_caps & 0x5) == 0x4) {
+		printk(BIOS_WARNING, "FTPM: PSP_RPMC_NVRAM region corrupted.\n");
+		*psp_rpmc_nvram = true;
+		*psp_nvram = true;
+	}
+
+	if (caps & MBOX_FTPM_CAP_TPM_REQ_FACTORY_RESET) {
+		printk(BIOS_WARNING, "FTPM: PSP_NVRAM region corrupted.\n");
+		*psp_nvram = true;
+	}
+
+	if (caps & MBOX_FTPM_CAP_FTPM_NEED_RECOVER)
+		*psp_dir = true;
+}
diff --git a/src/soc/amd/common/block/psp/psp_def.h b/src/soc/amd/common/block/psp/psp_def.h
index 369ef08e02..56c963dd7c 100644
--- a/src/soc/amd/common/block/psp/psp_def.h
+++ b/src/soc/amd/common/block/psp/psp_def.h
@@ -19,6 +19,9 @@
 #define   MBOX_BIOS_CMD_SX_INFO_SLEEP_TYPE_MAX	0x07
 #define MBOX_BIOS_CMD_RSM_INFO			0x04
 #define MBOX_BIOS_CMD_PSP_FTPM_QUERY		0x05
+#define   MBOX_FTPM_CAP_TPM_SUPPORTED		(1 << 0)
+#define   MBOX_FTPM_CAP_TPM_REQ_FACTORY_RESET	(1 << 1)
+#define   MBOX_FTPM_CAP_FTPM_NEED_RECOVER	(1 << 2)
 #define MBOX_BIOS_CMD_BOOT_DONE			0x06
 #define MBOX_BIOS_CMD_CLEAR_S3_STS		0x07
 #define MBOX_BIOS_CMD_S3_DATA_INFO		0x08

From 5b1a8b53b6333ae0048c304f06c848979b24d33e Mon Sep 17 00:00:00 2001
From: Felix Held <felix-coreboot@felixheld.de>
Date: Wed, 23 Apr 2025 17:42:42 +0200
Subject: [PATCH 1647/3886] soc/amd/common/i23c_pad_ctrl: add I3C pad config
 options

Before, the I2C/I3C pads could only be configured to I2C mode. To be
able to use the I3C controller, add the corresponding options and
implementation for the I3C pad mode with all possible voltages.

Change-Id: I1cc2e830019101cfef96b9474477717a8a75111c
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87435
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
---
 src/soc/amd/common/block/i2c/i23c_pad_ctrl.c  | 31 +++++++++++++++++--
 .../amd/common/block/include/amdblocks/i2c.h  |  3 ++
 2 files changed, 31 insertions(+), 3 deletions(-)

diff --git a/src/soc/amd/common/block/i2c/i23c_pad_ctrl.c b/src/soc/amd/common/block/i2c/i23c_pad_ctrl.c
index bff6223b78..be5ebc4fd2 100644
--- a/src/soc/amd/common/block/i2c/i23c_pad_ctrl.c
+++ b/src/soc/amd/common/block/i2c/i23c_pad_ctrl.c
@@ -14,26 +14,51 @@ void fch_i23c_pad_init(unsigned int bus,
 
 	pad_ctrl = misc_read32(MISC_I23C_PAD_CTRL(bus));
 
-	pad_ctrl &= ~I23C_PAD_CTRL_MODE_I3C_I2C_MASK;
-	pad_ctrl |= I23C_PAD_CTRL_MODE_I2C;
-
 	switch (ctrl->rx_level) {
 	case I2C_PAD_RX_NO_CHANGE:
+		pad_ctrl &= ~I23C_PAD_CTRL_MODE_I3C_I2C_MASK;
+		pad_ctrl |= I23C_PAD_CTRL_MODE_I2C;
 		/* Default is enabled and thresholds for 1.8V operation */
 		break;
 	case I2C_PAD_RX_OFF:
+		pad_ctrl &= ~I23C_PAD_CTRL_MODE_I3C_I2C_MASK;
+		pad_ctrl |= I23C_PAD_CTRL_MODE_I2C;
 		pad_ctrl &= ~I23C_PAD_CTRL_RX_SEL_MASK;
 		pad_ctrl |= I23C_PAD_CTRL_RX_SEL_OFF;
 		pad_ctrl &= ~I23C_PAD_CTRL_MODE_1_8V_1_1V_MASK;
 		pad_ctrl |= I23C_PAD_CTRL_MODE_1_8V;
 		break;
 	case I2C_PAD_RX_1_8V:
+		pad_ctrl &= ~I23C_PAD_CTRL_MODE_I3C_I2C_MASK;
+		pad_ctrl |= I23C_PAD_CTRL_MODE_I2C;
 		pad_ctrl &= ~I23C_PAD_CTRL_RX_SEL_MASK;
 		pad_ctrl |= I23C_PAD_CTRL_RX_SEL_ON;
 		pad_ctrl &= ~I23C_PAD_CTRL_MODE_1_8V_1_1V_MASK;
 		pad_ctrl |= I23C_PAD_CTRL_MODE_1_8V;
 		break;
 	case I2C_PAD_RX_1_1V:
+		pad_ctrl &= ~I23C_PAD_CTRL_MODE_I3C_I2C_MASK;
+		pad_ctrl |= I23C_PAD_CTRL_MODE_I2C;
+		pad_ctrl &= ~I23C_PAD_CTRL_RX_SEL_MASK;
+		pad_ctrl |= I23C_PAD_CTRL_RX_SEL_ON;
+		pad_ctrl &= ~I23C_PAD_CTRL_MODE_1_8V_1_1V_MASK;
+		pad_ctrl |= I23C_PAD_CTRL_MODE_1_1V;
+		break;
+	case I3C_PAD_RX_NO_CHANGE:
+		pad_ctrl &= ~I23C_PAD_CTRL_MODE_I3C_I2C_MASK;
+		pad_ctrl |= I23C_PAD_CTRL_MODE_I3C;
+		break;
+	case I3C_PAD_RX_1_8V:
+		pad_ctrl &= ~I23C_PAD_CTRL_MODE_I3C_I2C_MASK;
+		pad_ctrl |= I23C_PAD_CTRL_MODE_I3C;
+		pad_ctrl &= ~I23C_PAD_CTRL_RX_SEL_MASK;
+		pad_ctrl |= I23C_PAD_CTRL_RX_SEL_ON;
+		pad_ctrl &= ~I23C_PAD_CTRL_MODE_1_8V_1_1V_MASK;
+		pad_ctrl |= I23C_PAD_CTRL_MODE_1_8V;
+		break;
+	case I3C_PAD_RX_1_1V:
+		pad_ctrl &= ~I23C_PAD_CTRL_MODE_I3C_I2C_MASK;
+		pad_ctrl |= I23C_PAD_CTRL_MODE_I3C;
 		pad_ctrl &= ~I23C_PAD_CTRL_RX_SEL_MASK;
 		pad_ctrl |= I23C_PAD_CTRL_RX_SEL_ON;
 		pad_ctrl &= ~I23C_PAD_CTRL_MODE_1_8V_1_1V_MASK;
diff --git a/src/soc/amd/common/block/include/amdblocks/i2c.h b/src/soc/amd/common/block/include/amdblocks/i2c.h
index 94ac173d9b..fc1a03217a 100644
--- a/src/soc/amd/common/block/include/amdblocks/i2c.h
+++ b/src/soc/amd/common/block/include/amdblocks/i2c.h
@@ -62,6 +62,9 @@ enum i2c_pad_rx_level {
 	I2C_PAD_RX_3_3V,
 	I2C_PAD_RX_1_8V,
 	I2C_PAD_RX_1_1V,
+	I3C_PAD_RX_NO_CHANGE,
+	I3C_PAD_RX_1_8V,
+	I3C_PAD_RX_1_1V,
 };
 
 struct i2c_pad_control {

From 5f0177ac5d9f6a3c0ca69e585f9361911dac9357 Mon Sep 17 00:00:00 2001
From: Luca Lai <luca.lai@lcfc.corp-partner.google.com>
Date: Fri, 18 Jul 2025 14:48:03 +0800
Subject: [PATCH 1648/3886] mb/google/trulo/var/pujjolo: Update Stylus IRQ
 wakeup group

Because when stylus bringing into the garage will resume
from suspend using powerd_dbus_suspend command, so
update the stylus setting which wake_gpe from DW0 to DW2
to fix the funtion.

BUG=b:430712526
BRANCH=none
TEST= Build and boot to OS and check when stylus bringing into
garage and the system will not resume from suspend.

Change-Id: I526b608b03631f365bb33fc44904c87b00a47436
Signed-off-by: Luca Lai <luca.lai@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88479
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
---
 src/mainboard/google/brya/variants/pujjolo/overridetree.cb | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/mainboard/google/brya/variants/pujjolo/overridetree.cb b/src/mainboard/google/brya/variants/pujjolo/overridetree.cb
index 3c6d1102e5..a68adf5425 100644
--- a/src/mainboard/google/brya/variants/pujjolo/overridetree.cb
+++ b/src/mainboard/google/brya/variants/pujjolo/overridetree.cb
@@ -241,7 +241,7 @@ chip soc/intel/alderlake
 			chip drivers/generic/gpio_keys
 				register "name" = ""PENH""
 				register "gpio" = "ACPI_GPIO_INPUT_ACTIVE_LOW(GPP_E0)"
-				register "key.wake_gpe" = "GPE0_DW0_12"
+				register "key.wake_gpe" = "GPE0_DW2_15"
 				register "key.wakeup_route" = "WAKEUP_ROUTE_SCI"
 				register "key.wakeup_event_action" = "EV_ACT_DEASSERTED"
 				register "key.dev_name" = ""EJCT""

From b98f78637599be92d74ef9ae10442a9a83cce58d Mon Sep 17 00:00:00 2001
From: Ian Feng <ian_feng@compal.corp-partner.google.com>
Date: Tue, 22 Jul 2025 10:42:12 +0800
Subject: [PATCH 1649/3886] mb/google/fatcat/var/francka: Increase reset delay
 to 100ms for ILTK0001

Fix resume failure on i2c-ILTK0001:00 where acpi_subsys_resume
returns -121. Increase reset_delay_ms from 10ms to 100ms to
ensure the device is ready after reset.

BUG=b:411164455
TEST=Build and boot and verified resume time across 5 cycles.
All within 500 ms limit.
Suspend-resume time w/ and w/o:

w/o: Average=433.6 ms
1. Resume time 430 ms within limit of 500 ms
2. Resume time 435 ms within limit of 500 ms
3. Resume time 440 ms within limit of 500 ms
4. Resume time 430 ms within limit of 500 ms
5. Resume time 433 ms within limit of 500 ms

w/: Average=449.4 ms
1. Resume time 440 ms within limit of 500 ms
2. Resume time 439 ms within limit of 500 ms
3. Resume time 451 ms within limit of 500 ms
4. Resume time 482 ms within limit of 500 ms
5. Resume time 435 ms within limit of 500 ms

Change-Id: I67ea9aa5ca8ba6f30f772c2decd464d889865347
Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88527
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
---
 src/mainboard/google/fatcat/variants/francka/overridetree.cb | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/mainboard/google/fatcat/variants/francka/overridetree.cb b/src/mainboard/google/fatcat/variants/francka/overridetree.cb
index a0a6ec680d..323918aafe 100644
--- a/src/mainboard/google/fatcat/variants/francka/overridetree.cb
+++ b/src/mainboard/google/fatcat/variants/francka/overridetree.cb
@@ -209,7 +209,7 @@ chip soc/intel/pantherlake
 				register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_E01_IRQ)"
 				register "generic.detect" = "1"
 				register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B08)"
-				register "generic.reset_delay_ms" = "10"
+				register "generic.reset_delay_ms" = "100"
 				register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B18)"
 				register "generic.enable_delay_ms" = "12"
 				register "generic.has_power_resource" = "1"

From 92dd8cea594226b118d2d1aa0bae1acd27f974e4 Mon Sep 17 00:00:00 2001
From: David Wu <david_wu@quanta.corp-partner.google.com>
Date: Fri, 18 Jul 2025 19:17:07 +0800
Subject: [PATCH 1650/3886] mb/google/nissa/var/riven: Add parade touchscreen
 support

This change adds the necessary configuration for the parade
touchscreen (PRT3406) device, connected to I2C bus 24.

It includes settings for:
* HID descriptor
* Device description
* IRQ configuration
* Detection
* Reset, stop and enable GPIOs with their respective delays
* Power resource handling
* HID descriptor register offset

BUG=b:431658711
TEST=emerge-nissa coreboot and parade touchscreen can work well

Change-Id: I5ca4853c4105d422b907c29fd0b3a4f2a1ce6d9f
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88483
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
---
 .../google/brya/variants/riven/overridetree.cb | 18 ++++++++++++++++++
 1 file changed, 18 insertions(+)

diff --git a/src/mainboard/google/brya/variants/riven/overridetree.cb b/src/mainboard/google/brya/variants/riven/overridetree.cb
index ee3afa616b..7f92627145 100644
--- a/src/mainboard/google/brya/variants/riven/overridetree.cb
+++ b/src/mainboard/google/brya/variants/riven/overridetree.cb
@@ -303,6 +303,24 @@ chip soc/intel/alderlake
 				register "hid_desc_reg_offset" = "0x01"
 				device i2c 38 on end
 			end
+			chip drivers/i2c/hid
+				register "generic.hid" = ""PRT3406""
+				register "generic.desc" = ""Parade Touchscreen""
+				register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_C7_IRQ)"
+				register "generic.detect" = "1"
+				register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C1)"
+				register "generic.reset_delay_ms" = "20"
+				register "generic.reset_off_delay_ms" = "2"
+				register "generic.stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C6)"
+				register "generic.stop_delay_ms" = "280"
+				register "generic.stop_off_delay_ms" = "2"
+				register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C0)"
+				register "generic.enable_delay_ms" = "1"
+				register "generic.has_power_resource" = "1"
+				register "generic.use_gpio_for_status" = "true"
+				register "hid_desc_reg_offset" = "0x01"
+				device i2c 24 on end
+			end
 			chip drivers/generic/gpio_keys
 				register "name" = ""PENH""
 				register "gpio" = "ACPI_GPIO_INPUT_ACTIVE_LOW(GPP_F13)"

From a6173177757e42e638efac54e4eb6d781dc00899 Mon Sep 17 00:00:00 2001
From: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Date: Wed, 16 Jul 2025 17:17:52 +0800
Subject: [PATCH 1651/3886] mb/google/fatcat/var/kinmen: Support SAR table
 selection via FW_CONFIG

Add wifi SAR table support for kinmen. Bit 2 in the CBI/FW_CONFIG
field is used to determine which SAR table file to load at runtime.

BUG=b:424628935
TEST= check coreboot log:
before:

[WARN ] CBFS: 'wifi_sar_defaults.hex' not found.
[ERROR] Failed to get the wifi_sar_defaults.hex file size!
[ERROR] failed getting SAR limits!

after:

[INFO ] Use wifi_sar_0.hex.
[INFO ] CBFS: Found 'wifi_sar_0.hex' @0x7072c0 size 0x116 in mcache @0x73abdd28

Change-Id: I63e44ba0a4094264165cc9bd7e41c4bd2094c242
Signed-off-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88458
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
---
 src/mainboard/google/fatcat/variants/kinmen/Makefile.mk  | 1 +
 .../google/fatcat/variants/kinmen/overridetree.cb        | 3 +++
 src/mainboard/google/fatcat/variants/kinmen/variant.c    | 9 +++++++++
 3 files changed, 13 insertions(+)
 create mode 100644 src/mainboard/google/fatcat/variants/kinmen/variant.c

diff --git a/src/mainboard/google/fatcat/variants/kinmen/Makefile.mk b/src/mainboard/google/fatcat/variants/kinmen/Makefile.mk
index 4c33dad4db..cbe8155bd4 100644
--- a/src/mainboard/google/fatcat/variants/kinmen/Makefile.mk
+++ b/src/mainboard/google/fatcat/variants/kinmen/Makefile.mk
@@ -4,3 +4,4 @@ bootblock-y += gpio.c
 romstage-y += gpio.c
 romstage-y += memory.c
 ramstage-y += gpio.c
+ramstage-$(CONFIG_FW_CONFIG) += variant.c
diff --git a/src/mainboard/google/fatcat/variants/kinmen/overridetree.cb b/src/mainboard/google/fatcat/variants/kinmen/overridetree.cb
index d3025dd8c6..624fa76f3b 100644
--- a/src/mainboard/google/fatcat/variants/kinmen/overridetree.cb
+++ b/src/mainboard/google/fatcat/variants/kinmen/overridetree.cb
@@ -1,4 +1,7 @@
 fw_config
+	field WIFI 2 2
+		option WIFI_CNVI_7		0
+	end
 	field AUDIO 3 5
 		option AUDIO_UNKNOWN		0
 		option AUDIO_ALC721_SNDW	1
diff --git a/src/mainboard/google/fatcat/variants/kinmen/variant.c b/src/mainboard/google/fatcat/variants/kinmen/variant.c
new file mode 100644
index 0000000000..4221a5bf8e
--- /dev/null
+++ b/src/mainboard/google/fatcat/variants/kinmen/variant.c
@@ -0,0 +1,9 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <fw_config.h>
+#include <sar.h>
+
+const char *get_wifi_sar_cbfs_filename(void)
+{
+	return get_wifi_sar_fw_config_filename(FW_CONFIG_FIELD(WIFI));
+}

From 9a8ba5b39ac0eaa3370f9be46ee022aa5497890e Mon Sep 17 00:00:00 2001
From: Kapil Porwal <kapilporwal@google.com>
Date: Wed, 9 Jul 2025 10:42:12 +0530
Subject: [PATCH 1652/3886] {lib, drivers/intel}: Move BMP rendering logic out
 of SoC code

This patch refactors the BMP rendering logic, moving it from
drivers/intel/fsp2_0 to src/lib. This centralizes the code
responsible for rendering BMP images to the framebuffer.

Key changes:
- Move BMP rendering functions (e.g., calculate_logo_coordinates,
  copy_logo_to_framebuffer) and their dependencies to
  src/lib/render_bmp.c and src/lib/render_bmp.h.
- Decouple BMP definitions from UEFI headers by introducing new
  coreboot-specific structures for BMP images and BLT pixels.
- Consolidate bootsplash-related declarations into bootsplash.h,
  including new `fw_splash_vertical_alignment`,
  `fw_splash_horizontal_alignment`, and `struct logo_config`.
- Update `soc_load_logo_by_coreboot` to use the new common
  `load_and_render_logo_to_framebuffer` function and `struct
  logo_config` for rendering.
- Relocate `release_logo` to `src/lib/render_bmp.c` for better
  module structure.
- Update `src/lib/Makefile.mk` to include the new render_bmp.c.

This refactoring improves code organization and reusability, making
BMP rendering accessible without tight coupling to Intel-specific
driver code.

BUG=b:427387842
TEST=Verify firmware splash screen on google/fatcat.

Change-Id: I0e20ea7e44b4b3ccdb2d4aa9b6aa10ed3447ccfc
Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88361
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/drivers/intel/fsp2_0/cb_logo.c            | 207 +----
 src/drivers/intel/fsp2_0/fsp_gop_blt.c        | 448 +----------
 src/drivers/intel/fsp2_0/silicon_init.c       |   9 -
 src/include/bootsplash.h                      | 120 +++
 src/lib/Makefile.mk                           |   1 +
 src/lib/render_bmp.c                          | 721 ++++++++++++++++++
 src/lib/render_bmp.h                          |  58 ++
 .../common/block/include/intelblocks/cfg.h    | 101 +--
 8 files changed, 918 insertions(+), 747 deletions(-)
 create mode 100644 src/lib/render_bmp.c
 create mode 100644 src/lib/render_bmp.h

diff --git a/src/drivers/intel/fsp2_0/cb_logo.c b/src/drivers/intel/fsp2_0/cb_logo.c
index d533806656..c77e55eeed 100644
--- a/src/drivers/intel/fsp2_0/cb_logo.c
+++ b/src/drivers/intel/fsp2_0/cb_logo.c
@@ -17,11 +17,6 @@
 #include <stdlib.h>
 #include <string.h>
 
-struct logo_coordinates {
-	uint32_t x;
-	uint32_t y;
-};
-
 /*
  * Programs the Local Memory BAR (LMEMBAR) for the IGD.
  *
@@ -44,169 +39,12 @@ static void program_igd_lmembar(uint32_t base)
 	pci_or_config16(SA_DEV_IGD, PCI_COMMAND, enable_mask);
 }
 
-/*
- * Calculates the destination coordinates for the logo based on both horizontal and
- * vertical alignment settings.
- *
- * horizontal_resolution: The horizontal resolution of the display panel.
- * vertical_resolution: The vertical resolution of the display panel.
- * logo_width: The width of the logo bitmap.
- * logo_height: The height of the logo bitmap.
- * halignment: The horizontal alignment setting. Use FW_SPLASH_HALIGNMENT_NONE
- *             if only vertical alignment is specified.
- * valignment: The vertical alignment setting. Use FW_SPLASH_VALIGNMENT_NONE
- *             if only horizontal alignment is specified.
- *
- * Returning `struct logo_coordinates` that contains the calculated x and y coordinates
- * for rendering the logo.
- */
-static struct logo_coordinates calculate_logo_coordinates(
-	uint32_t horizontal_resolution, uint32_t vertical_resolution,
-	uint32_t logo_width, uint32_t logo_height,
-	enum fw_splash_vertical_alignment valignment,
-	enum fw_splash_horizontal_alignment halignment)
-{
-	struct logo_coordinates coords;
-
-	/* Calculate X coordinate */
-	switch (halignment) {
-	case FW_SPLASH_HALIGNMENT_LEFT:
-		coords.x = 0;
-		break;
-	case FW_SPLASH_HALIGNMENT_RIGHT:
-		coords.x = horizontal_resolution - logo_width;
-		break;
-	default: /* FW_SPLASH_HALIGNMENT_CENTER (default) */
-		coords.x = (horizontal_resolution - logo_width) / 2;
-		break;
-	}
-
-	/* Calculate Y coordinate */
-	switch (valignment) {
-	case FW_SPLASH_VALIGNMENT_MIDDLE:
-		coords.y = vertical_resolution / 2;
-		break;
-	case FW_SPLASH_VALIGNMENT_TOP:
-		coords.y = 0;
-		break;
-	case FW_SPLASH_VALIGNMENT_BOTTOM:
-		coords.y = vertical_resolution - logo_height;
-		break;
-	default: /* FW_SPLASH_VALIGNMENT_CENTER (default) */
-		coords.y = (vertical_resolution - logo_height) / 2;
-		break;
-	}
-
-	return coords;
-}
-
-/*
- * Copies the logo to the framebuffer.
- *
- * framebuffer_base: The base address of the framebuffer.
- * bytes_per_scanline: The number of bytes per scanline in the framebuffer.
- * logo_buffer_addr: The address of the logo data in BLT format.
- * logo_width: The width of the logo bitmap.
- * logo_height: The height of the logo bitmap.
- * dest_x: The destination x-coordinate in the framebuffer for rendering the logo.
- * dest_y: The destination y-coordinate in the framebuffer for rendering the logo.
- */
-static void copy_logo_to_framebuffer(
-	uintptr_t framebuffer_base, uint32_t bytes_per_scanline,
-	efi_uintn_t logo_buffer_addr, uint32_t logo_width, uint32_t logo_height,
-	efi_uintn_t dest_x, efi_uintn_t dest_y)
-{
-	size_t pixel_size = sizeof(efi_graphics_output_blt_pixel);
-	size_t logo_line_bytes = logo_width * pixel_size;
-	efi_uintn_t framebuffer_offset = framebuffer_base + dest_y * bytes_per_scanline
-					 + dest_x * pixel_size;
-	uint8_t *dst_row_address = (uint8_t *)framebuffer_offset;
-	uint8_t *src_row_address = (uint8_t *)(uintptr_t)logo_buffer_addr;
-	for (uint32_t i = 0; i < logo_height; i++) {
-		memcpy(dst_row_address, src_row_address, logo_line_bytes);
-		dst_row_address += bytes_per_scanline;
-		src_row_address += logo_line_bytes;
-	}
-}
-
-/*
- * Loads, converts, and renders a BMP logo to the framebuffer.
- *
- * Returns 0 on success, -1 on failure.
- */
-static int render_logo_to_framebuffer(uintptr_t framebuffer_base, uint32_t bytes_per_scanline,
-	uint32_t horizontal_resolution, uint32_t vertical_resolution,
-	struct soc_intel_common_config *config, enum bootsplash_type logo_type)
-{
-	uintptr_t logo_ptr;
-	size_t logo_ptr_size;
-	efi_uintn_t blt_size, blt_buffer_addr;
-	uint32_t logo_height, logo_width;
-	struct logo_coordinates logo_coords;
-
-	logo_ptr = (uintptr_t)bmp_load_logo_by_type(logo_type, &logo_ptr_size);
-
-	if (!logo_ptr || logo_ptr_size < sizeof(efi_bmp_image_header)) {
-		printk(BIOS_ERR, "%s: BMP image (%zu) is less than expected minimum size (%zu).\n",
-				 __func__, logo_ptr_size, sizeof(efi_bmp_image_header));
-		return -1;
-	}
-
-	fsp_convert_bmp_to_gop_blt(logo_ptr, logo_ptr_size, &blt_buffer_addr, &blt_size,
-				   &logo_height, &logo_width, config->panel_orientation);
-
-	enum fw_splash_horizontal_alignment halignment = FW_SPLASH_HALIGNMENT_CENTER;
-	enum fw_splash_vertical_alignment valignment = FW_SPLASH_VALIGNMENT_CENTER;
-	/* Determine logo coordinates based on context (main logo vs. footer) */
-	if (logo_type == BOOTSPLASH_LOW_BATTERY || logo_type == BOOTSPLASH_CENTER) {
-		/* Override logo alignment if the default screen orientation is not normal */
-		if (config->panel_orientation != LB_FB_ORIENTATION_NORMAL)
-			config->logo_valignment = FW_SPLASH_VALIGNMENT_CENTER;
-
-		valignment = config->logo_valignment;
-	} else {
-		/* Calculate logo destination coordinates */
-		switch (config->panel_orientation) {
-		case LB_FB_ORIENTATION_RIGHT_UP:
-			halignment = FW_SPLASH_HALIGNMENT_LEFT;
-			break;
-		case LB_FB_ORIENTATION_LEFT_UP:
-			halignment = FW_SPLASH_HALIGNMENT_RIGHT;
-			break;
-		case LB_FB_ORIENTATION_BOTTOM_UP:
-			valignment = FW_SPLASH_VALIGNMENT_TOP;
-			break;
-		default: /* LB_FB_ORIENTATION_NORMAL (default) */
-			valignment = FW_SPLASH_VALIGNMENT_BOTTOM;
-			break;
-		}
-	}
-
-	logo_coords = calculate_logo_coordinates(horizontal_resolution,
-		 vertical_resolution, logo_width, logo_height, valignment, halignment);
-
-	/* Adjust the logo axis for rendering footer bootsplash if any override is available */
-	if (logo_type == BOOTSPLASH_FOOTER && config->logo_bottom_margin) {
-		if (config->panel_orientation == LB_FB_ORIENTATION_BOTTOM_UP ||
-				 config->panel_orientation == LB_FB_ORIENTATION_NORMAL)
-			logo_coords.y -= config->logo_bottom_margin;
-		else
-			logo_coords.x -= config->logo_bottom_margin;
-	}
-
-	copy_logo_to_framebuffer(framebuffer_base, bytes_per_scanline, blt_buffer_addr,
-				 logo_width, logo_height, logo_coords.x, logo_coords.y);
-
-	bmp_release_logo();
-
-	return 0;
-}
-
 void soc_load_logo_by_coreboot(void)
 {
 	const struct hob_graphics_info *ginfo;
 	struct soc_intel_common_config *config = chip_get_common_soc_structure();
 	int temp_mtrr_index = -1;
+	struct logo_config logo_cfg;
 	size_t size;
 
 	/* Find the graphics information HOB */
@@ -226,12 +64,6 @@ void soc_load_logo_by_coreboot(void)
 		return;
 	}
 
-	uintptr_t framebuffer_bar = ginfo->framebuffer_base;
-	uint32_t horizontal_resolution = ginfo->horizontal_resolution;
-	uint32_t vertical_resolution = ginfo->vertical_resolution;
-	uint32_t bytes_per_scanline = ginfo->pixels_per_scanline *
-				 sizeof(efi_graphics_output_blt_pixel);
-
 	/*
 	 * Adjusts panel orientation for external display when the lid is closed.
 	 *
@@ -243,33 +75,20 @@ void soc_load_logo_by_coreboot(void)
 	if (CONFIG(VBOOT_LID_SWITCH) ? !get_lid_switch() : !CONFIG(RUN_FSP_GOP))
 		config->panel_orientation = LB_FB_ORIENTATION_NORMAL;
 
-	/*
-	 * If the device is in low-battery mode and the low-battery splash screen is being
-	 * displayed, prevent further operation and bail out early.
-	 */
-	if (platform_is_low_battery_shutdown_needed()) {
-		if (render_logo_to_framebuffer(framebuffer_bar, bytes_per_scanline,
-				 horizontal_resolution, vertical_resolution, config,
-				 BOOTSPLASH_LOW_BATTERY) != 0) {
-			printk(BIOS_ERR, "%s: Failed to render low-battery logo.\n", __func__);
-		}
-		goto cleanup;
-	}
 
-	/* Render the main logo */
-	if (render_logo_to_framebuffer(framebuffer_bar, bytes_per_scanline,
-				 horizontal_resolution, vertical_resolution, config,
-				 BOOTSPLASH_CENTER) != 0) {
-		printk(BIOS_ERR, "%s: Failed to render main splash screen logo.\n", __func__);
-	} else if (CONFIG(SPLASH_SCREEN_FOOTER)) {
-		/* Render the footer logo */
-		if (render_logo_to_framebuffer(framebuffer_bar, bytes_per_scanline,
-				 horizontal_resolution, vertical_resolution, config,
-				 BOOTSPLASH_FOOTER) != 0)
-			printk(BIOS_ERR, "%s: Failed to render footer logo.\n", __func__);
-	}
+	memset((void *)&logo_cfg, 0, sizeof(logo_cfg));
+	logo_cfg.framebuffer_base = ginfo->framebuffer_base;
+	logo_cfg.horizontal_resolution = ginfo->horizontal_resolution;
+	logo_cfg.vertical_resolution = ginfo->vertical_resolution;
+	logo_cfg.bytes_per_scanline = ginfo->pixels_per_scanline *
+				 sizeof(efi_graphics_output_blt_pixel);
+	logo_cfg.panel_orientation = config->panel_orientation;
+	logo_cfg.halignment = FW_SPLASH_HALIGNMENT_CENTER;
+	logo_cfg.valignment = config->logo_valignment;
+	logo_cfg.logo_bottom_margin = config->logo_bottom_margin;
+
+	render_logo_to_framebuffer(&logo_cfg);
 
-cleanup:
 	/* Clear temporary Write Combine (WC) MTRR */
 	clear_var_mtrr(temp_mtrr_index);
 }
diff --git a/src/drivers/intel/fsp2_0/fsp_gop_blt.c b/src/drivers/intel/fsp2_0/fsp_gop_blt.c
index bc37ca6baa..52bc3c1989 100644
--- a/src/drivers/intel/fsp2_0/fsp_gop_blt.c
+++ b/src/drivers/intel/fsp2_0/fsp_gop_blt.c
@@ -7,450 +7,13 @@
 #include <fsp/fsp_gop_blt.h>
 #include <stdlib.h>
 
-static bool is_bmp_image_valid(efi_bmp_image_header *header)
-{
-	/* Check if the BMP Header Signature is valid */
-	if (header->CharB != 'B' || header->CharM != 'M')
-		return false;
-
-	/* Check if the BMP Image Header Length is valid */
-	if (!header->PixelHeight || !header->PixelWidth)
-		return false;
-
-	if (header->Size < header->ImageOffset)
-		return false;
-
-	if (header->ImageOffset < sizeof(efi_bmp_image_header))
-		return false;
-
-	return true;
-}
-
-static bool is_bmp_image_compressed(efi_bmp_image_header *header)
-{
-	return header->CompressionType != 0;
-}
-
-static bool is_bitmap_format_supported(efi_bmp_image_header *header)
-{
-	/*
-	 * Check BITMAP format is supported
-	 * BMP_IMAGE_HEADER = BITMAP_FILE_HEADER + BITMAP_INFO_HEADER
-	 */
-	if (header->HeaderSize != sizeof(efi_bmp_image_header) -
-			 OFFSET_OF(efi_bmp_image_header, HeaderSize))
-		return false;
-
-	return true;
-}
-
-static bool do_bmp_image_authentication(efi_bmp_image_header *header)
-{
-	if (!is_bmp_image_valid(header)) {
-		printk(BIOS_ERR, "%s: BMP Image Header is invalid.\n", __func__);
-		return false;
-	}
-
-	/*
-	 * BMP image compression is unsupported by FSP implementation,
-	 * hence, exit if the BMP image is compressed.
-	 */
-	if (is_bmp_image_compressed(header)) {
-		printk(BIOS_ERR, "%s: BMP Image Compression is unsupported.\n", __func__);
-		return false;
-	}
-
-	if (!is_bitmap_format_supported(header)) {
-		printk(BIOS_ERR, "%s: BmpHeader Header Size (0x%x) is not as expected.\n",
-			 __func__, header->HeaderSize);
-		return false;
-	}
-
-	return true;
-}
-
-static uint32_t calculate_blt_buffer_size(efi_bmp_image_header *header)
-{
-	uint32_t blt_buffer_size;
-
-	/* Calculate the size required for BLT buffer */
-	blt_buffer_size = header->PixelWidth * header->PixelHeight *
-			 sizeof(efi_graphics_output_blt_pixel);
-	if (!blt_buffer_size)
-		return 0;
-
-	return blt_buffer_size;
-}
-
-static int get_color_map_num(efi_bmp_image_header *header)
-{
-	int col_map_number;
-
-	switch (header->BitPerPixel) {
-	case 1:
-		col_map_number = 2;
-		break;
-	case 4:
-		col_map_number = 16;
-		break;
-	case 8:
-		col_map_number = 256;
-		break;
-	default:
-		/*
-		 * For other bit depths (e.g., 24-bit and 32-bit) that doesn't have
-		 * a standard palette, col_map_number remains 0.
-		 */
-		col_map_number = 0;
-		break;
-	}
-
-	/*
-	 * At times BMP file may have padding data between its header section and the
-	 * data section.
-	 */
-	if (header->ImageOffset - sizeof(efi_bmp_image_header) <
-			 sizeof(efi_bmp_color_map) * col_map_number)
-		return -1;
-
-	return col_map_number;
-}
-
-/*
- * Visual Representation of the Flipping:
- *
- * Original BMP Image:
- *
- *      0 -----------------------------------------PixelWidth-1
- *      |                                          |
- *      |                                          |
- *      |                                          |
- *      PixelHeight-1------------------------------|
- *
- * Blitting Region:
- *
- *      (x, y) ----------------------------------- (x + blt_width, y)
- *      |                                          |
- *      |                                          |
- *      (x, y + blt_height) -------------------- --(x + blt_width, y + blt_height)
- *
- * Flipped Coordinates:
- *
- * flipped_x:  Represents the horizontal coordinate from the `right` edge of the BMP,
- *             accounting for the blit width.
- *
- * flipped_y:  Represents the vertical coordinate from the `bottom` edge of the BMP,
- *             accounting for the blit height.
- *
- * Example (Orientation: LB_FB_ORIENTATION_BOTTOM_UP):
- *
- * If blt_width is small, flipped_x will be near PixelWidth.
- * If blt_height is small, flipped_y will be near PixelHeight.
- *
- * The blit then starts at (flipped_x, blt_height), effectively flipping the
- * horizontal position and using the original blit height.
- *
- * This allows for blitting from the bottom-left corner of the display panel.
- */
-static bool calculate_adj_height_width(const efi_bmp_image_header *header, size_t *adjusted_x,
-	 size_t *adjusted_y, enum lb_fb_orientation orientation, int blt_width, int blt_height)
-{
-	size_t flipped_x = header->PixelWidth - blt_width - 1;
-	size_t flipped_y = header->PixelHeight - blt_height - 1;
-
-	switch (orientation) {
-	case LB_FB_ORIENTATION_LEFT_UP:
-		*adjusted_x = flipped_y;
-		*adjusted_y = flipped_x;
-		break;
-
-	case LB_FB_ORIENTATION_BOTTOM_UP:
-		*adjusted_x = flipped_x;
-		*adjusted_y = blt_height;
-		break;
-
-	case LB_FB_ORIENTATION_RIGHT_UP:
-		*adjusted_x = blt_height;
-		*adjusted_y = blt_width;
-		break;
-
-	case LB_FB_ORIENTATION_NORMAL:
-	default:
-		*adjusted_x = blt_width;
-		*adjusted_y = flipped_y;
-		break;
-	}
-
-	return true;
-}
-
-/*
- * Visual Representation of gop_width and calculate linear offset into the GOP buffer:
- *
- * GOP Display Buffer:
- *
- *      +------------------------------------------------+
- *      | 0                                              |
- *      | |--> gop_width pixels in this row              |
- *      +------------------------------------------------+
- *      | gop_width                                      |
- *      |                                                |
- *      | gop_width                                      |
- *      | ...                                            |
- *      +------------------------------------------------+
- *      | gop_width                                      |
- *      +------------------------------------------------+
- *
- * gop_width: Represents the width of a row in the GOP buffer.
- * - It is determined by the `orientation` of the image.
- * - For `LEFT_UP` and `RIGHT_UP`, the GOP width is the BMP image's `PixelHeight`.
- * - For `BOTTOM_UP` and `NORMAL`, the GOP width is the BMP image's `PixelWidth`.
- *
- * gop_x, gop_y: Coordinates within the GOP buffer where the blit will start.
- * - These are calculated by `calculate_adj_height_width` based on the `orientation`,
- * `blt_width`, and `blt_height`.
- *
- * Pointer to the calculated pixel in the GOP blit buffer, or NULL on error.
- * - Calculate `gop_blt_offset`as `gop_y * gop_width + gop_x` to determine the offset
- *   to access the correct pixel within `gop_blt_buffer`.
- * - `gop_y * gop_width` calculates the offset of the row.
- * - `gop_x` calculates the offset within that row.
- */
-static efi_graphics_output_blt_pixel *get_gop_blt_pixel(
-	efi_graphics_output_blt_pixel *gop_blt_buffer, const efi_bmp_image_header *header,
-	 int blt_width, int blt_height, enum lb_fb_orientation orientation)
-{
-	size_t gop_x;
-	size_t gop_y;
-	size_t gop_width;
-
-	switch (orientation) {
-	case LB_FB_ORIENTATION_LEFT_UP:
-	case LB_FB_ORIENTATION_RIGHT_UP:
-		gop_width = header->PixelHeight;
-		break;
-
-	case LB_FB_ORIENTATION_BOTTOM_UP:
-	case LB_FB_ORIENTATION_NORMAL:
-	default:
-		gop_width = header->PixelWidth;
-		break;
-	}
-
-	if (!calculate_adj_height_width(header, &gop_x, &gop_y, orientation,
-			 blt_width, blt_height))
-		return NULL;
-
-	/*
-	 * Calculated pixel in the Graphics Output Protocol (GOP) blit buffer.
-	 * This offset represents the starting position where the blitted region will be placed
-	 * in the framebuffer.
-	 */
-	return &gop_blt_buffer[gop_y * gop_width + gop_x];
-}
-
-/*
- * Fill BMP image into BLT buffer format with optional orientation
- *
- * +------------------------------------------------------------------+
- * |  BMP Image (header: efi_bmp_image_header)                        |
- * |  (PixelWidth, PixelHeight)                                       |
- * +------------------------------------------------------------------+
- *        |
- *        | (blt_width, blt_height) : Region to blit
- *        V
- * +------------------------------------------------------------------+
- * |  calculate_adj_height_width(header, adjusted_x, adjusted_y,      |
- * |                               orientation, blt_width, blt_height)|
- * +------------------------------------------------------------------+
- *        |
- *        | Calculates adjusted coordinates based on orientation:
- *        |   - flipped_x = header->PixelWidth - blt_width - 1
- *        |   - flipped_y = header->PixelHeight - blt_height - 1
- *        |   - Depending on 'orientation', adjusted_x and adjusted_y are set.
- *        V
- * +-------------------------------------------------------------------+
- * |  get_gop_blt_pixel(gop_blt_buffer, header, blt_width, blt_height, |
- * |                                                  orientation)     |
- * +-------------------------------------------------------------------+
- *        |
- *        | 1. Determines gop_width based on orientation:
- *        |    - LEFT_UP/RIGHT_UP: gop_width = header->PixelHeight,
- *        |    - BOTTOM_UP/NORMAL: gop_width = header->PixelWidth,
- *        | 2. Calls calculate_adj_height_width to get gop_x and gop_y.
- *        | 3. GOP BLT offset: calculates linear offset into the GOP buffer
- *        |    - gop_blt_offset = gop_y * gop_width + gop_x
- *        | 4. GOP BLT offset is used to access the correct regions in:
- *        V
- * +------------------------------------------------------------------+
- * |  GOP Blit Buffer (Framebuffer)                                   |
- * +------------------------------------------------------------------+
- */
-static void *fill_blt_buffer(efi_bmp_image_header *header,
-	uintptr_t logo_ptr, size_t blt_buffer_size, enum lb_fb_orientation orientation)
-{
-	efi_graphics_output_blt_pixel *gop_blt_buffer;
-	efi_graphics_output_blt_pixel *gop_blt_ptr;
-	efi_graphics_output_blt_pixel *gop_blt;
-	uint8_t *bmp_image;
-	uint8_t *bmp_image_header;
-	efi_bmp_color_map *bmp_color_map;
-	size_t image_index;
-
-	gop_blt_ptr = malloc(sizeof(blt_buffer_size));
-	if (!gop_blt_ptr)
-		die("%s: out of memory. Consider increasing the `CONFIG_HEAP_SIZE`\n",
-			 __func__);
-
-	bmp_image = ((uint8_t *)logo_ptr) + header->ImageOffset;
-	bmp_image_header = bmp_image;
-	gop_blt_buffer = gop_blt_ptr;
-	bmp_color_map = (efi_bmp_color_map *)(logo_ptr + sizeof(efi_bmp_image_header));
-
-	for (size_t height = 0; height < header->PixelHeight; height++) {
-		for (size_t width = 0; width < header->PixelWidth; width++, bmp_image++) {
-			size_t index = 0;
-
-			gop_blt = get_gop_blt_pixel(gop_blt_buffer, header, width, height,
-							 orientation);
-			if (!gop_blt) {
-				free(gop_blt_ptr);
-				return NULL;
-			}
-
-			switch (header->BitPerPixel) {
-			/* Translate 1-bit (2 colors) BMP to 24-bit color */
-			case 1:
-				for (index = 0; index < 8 && width < header->PixelWidth; index++) {
-					uint8_t bit = ((*bmp_image) >> (7 - index)) & 0x1;
-					gop_blt->Red = bmp_color_map[bit].Red;
-					gop_blt->Green = bmp_color_map[bit].Green;
-					gop_blt->Blue = bmp_color_map[bit].Blue;
-					width++;
-					gop_blt = get_gop_blt_pixel(gop_blt_buffer, header, width, height,
-								 orientation);
-					if (!gop_blt) {
-						free(gop_blt_ptr);
-						return NULL;
-					}
-				}
-				width--;
-				break;
-
-			/* Translate 4-bit (16 colors) BMP Palette to 24-bit color */
-			case 4:
-				index = (*bmp_image) >> 4;
-				gop_blt->Red = bmp_color_map[index].Red;
-				gop_blt->Green = bmp_color_map[index].Green;
-				gop_blt->Blue = bmp_color_map[index].Blue;
-				if (width < (header->PixelWidth - 1)) {
-					width++;
-					gop_blt = get_gop_blt_pixel(gop_blt_buffer, header, width, height,
-								 orientation);
-					if (!gop_blt) {
-						free(gop_blt_ptr);
-						return NULL;
-					}
-					index = (*bmp_image) & 0x0f;
-					gop_blt->Red = bmp_color_map[index].Red;
-					gop_blt->Green = bmp_color_map[index].Green;
-					gop_blt->Blue = bmp_color_map[index].Blue;
-				}
-				break;
-
-			/* Translate 8-bit (256 colors) BMP Palette to 24-bit color */
-			case 8:
-				gop_blt->Red = bmp_color_map[*bmp_image].Red;
-				gop_blt->Green = bmp_color_map[*bmp_image].Green;
-				gop_blt->Blue = bmp_color_map[*bmp_image].Blue;
-				break;
-
-			/* For 24-bit BMP */
-			case 24:
-				gop_blt->Blue = *bmp_image++;
-				gop_blt->Green = *bmp_image++;
-				gop_blt->Red = *bmp_image;
-				break;
-
-			/* Convert 32 bit to 24bit bmp - just ignore the final byte of each pixel */
-			case 32:
-				gop_blt->Blue = *bmp_image++;
-				gop_blt->Green = *bmp_image++;
-				gop_blt->Red = *bmp_image++;
-				break;
-
-			/* Other bit format of BMP is not supported. */
-			default:
-				free(gop_blt_ptr);
-				gop_blt_ptr = NULL;
-
-				printk(BIOS_ERR, "%s, BMP Bit format not supported. 0x%X\n", __func__,
-					 header->BitPerPixel);
-				return NULL;
-			}
-		}
-		image_index = (uintptr_t)bmp_image - (uintptr_t)bmp_image_header;
-		/* Each row in BMP Image should be 4-byte align */
-		if ((image_index % 4) != 0)
-			bmp_image = bmp_image + (4 - (image_index % 4));
-	}
-
-	return gop_blt_ptr;
-}
-
-/* Helper function to perform the common BMP to GOP BLT conversion logic */
-static bool convert_bmp_to_gop_blt_common(uintptr_t logo_ptr, size_t logo_ptr_size,
-	efi_uintn_t *blt_ptr, efi_uintn_t *blt_size, uint32_t *pixel_height,
-	uint32_t *pixel_width, enum lb_fb_orientation orientation)
-{
-	size_t blt_buffer_size;
-	efi_bmp_image_header *bmp_header;
-
-	bmp_header = (efi_bmp_image_header *)logo_ptr;
-
-	/* Authenticate BMP header and validate size against provided logo_ptr_size */
-	if (!do_bmp_image_authentication(bmp_header) || (bmp_header->Size != logo_ptr_size))
-		return false;
-
-	blt_buffer_size = calculate_blt_buffer_size(bmp_header);
-	if (!blt_buffer_size)
-		return false;
-
-	if (get_color_map_num(bmp_header) < 0)
-		return false;
-
-	bool is_standard_orientation = (orientation == LB_FB_ORIENTATION_NORMAL ||
-					orientation == LB_FB_ORIENTATION_BOTTOM_UP);
-
-	*blt_size = blt_buffer_size;
-	*pixel_height = is_standard_orientation ? bmp_header->PixelHeight : bmp_header->PixelWidth;
-	*pixel_width = is_standard_orientation ? bmp_header->PixelWidth : bmp_header->PixelHeight;
-	*blt_ptr = (uintptr_t)fill_blt_buffer(bmp_header, logo_ptr, blt_buffer_size, orientation);
-
-	return true;
-}
-
 /* Convert a *.BMP graphics image to a GOP blt buffer */
 void fsp_load_and_convert_bmp_to_gop_blt(efi_uintn_t *logo, uint32_t *logo_size,
 	efi_uintn_t *blt_ptr, efi_uintn_t *blt_size, uint32_t *pixel_height, uint32_t *pixel_width,
 	enum lb_fb_orientation orientation)
 {
-	uintptr_t logo_ptr;
-	size_t logo_ptr_size;
-
-	if (!logo || !logo_size || !blt_ptr || !blt_size || !pixel_height || !pixel_width)
-		return;
-
-	logo_ptr = (uintptr_t)bmp_load_logo(&logo_ptr_size);
-
-	if (!logo_ptr || logo_ptr_size < sizeof(efi_bmp_image_header))
-		return;
-
-	*logo = logo_ptr;
-	*logo_size = logo_ptr_size;
-
-	convert_bmp_to_gop_blt_common(logo_ptr, logo_ptr_size, blt_ptr, blt_size,
-				      pixel_height, pixel_width, orientation);
+	load_and_convert_bmp_to_blt((uintptr_t *)logo, (size_t *)logo_size, (uintptr_t *)blt_ptr,
+				(size_t *)blt_size, pixel_height, pixel_width, orientation);
 }
 
 /* Convert a *.BMP graphics image (as per input `logo_ptr`) to a GOP blt buffer */
@@ -458,9 +21,6 @@ void fsp_convert_bmp_to_gop_blt(uintptr_t logo_ptr, size_t logo_ptr_size,
 	efi_uintn_t *blt_ptr, efi_uintn_t *blt_size, uint32_t *pixel_height, uint32_t *pixel_width,
 	enum lb_fb_orientation orientation)
 {
-	if (!blt_ptr || !blt_size || !pixel_height || !pixel_width)
-		return;
-
-	convert_bmp_to_gop_blt_common(logo_ptr, logo_ptr_size, blt_ptr, blt_size,
-				      pixel_height, pixel_width, orientation);
+	convert_bmp_to_blt(logo_ptr, logo_ptr_size, (uintptr_t *)blt_ptr, (size_t *)blt_size,
+				pixel_height, pixel_width, orientation);
 }
diff --git a/src/drivers/intel/fsp2_0/silicon_init.c b/src/drivers/intel/fsp2_0/silicon_init.c
index f6ed00be4d..6de71c9202 100644
--- a/src/drivers/intel/fsp2_0/silicon_init.c
+++ b/src/drivers/intel/fsp2_0/silicon_init.c
@@ -3,7 +3,6 @@
 #include <arch/null_breakpoint.h>
 #include <arch/stack_canary_breakpoint.h>
 #include <bootsplash.h>
-#include <bootstate.h>
 #include <cbfs.h>
 #include <cbmem.h>
 #include <commonlib/fsp.h>
@@ -300,11 +299,3 @@ void fsp_silicon_init(void)
 }
 
 __weak void soc_load_logo_by_fsp(FSPS_UPD *supd) { }
-
-static void release_logo(void *arg_unused)
-{
-	if (CONFIG(BMP_LOGO))
-		bmp_release_logo();
-}
-
-BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_LOAD, BS_ON_EXIT, release_logo, NULL);
diff --git a/src/include/bootsplash.h b/src/include/bootsplash.h
index a8e51cf1ba..841dd50b7b 100644
--- a/src/include/bootsplash.h
+++ b/src/include/bootsplash.h
@@ -3,6 +3,7 @@
 #ifndef __BOOTSPLASH_H__
 #define __BOOTSPLASH_H__
 
+#include <boot/coreboot_tables.h>
 #include <types.h>
 
 enum bootsplash_type {
@@ -27,6 +28,125 @@ void set_bootsplash(unsigned char *framebuffer, unsigned int x_resolution,
 		    unsigned int y_resolution, unsigned int bytes_per_line,
 		    unsigned int fb_resolution);
 
+/*
+ * Specifies the vertical alignment for the splash screen image.
+ *
+ * Visual Guide (representing the display area and the [LOGO]):
+ *
+ * Each option dictates the vertical placement of the splash image
+ * within the display's height.
+ */
+enum fw_splash_vertical_alignment {
+	/*
+	 * The splash image is centered vertically `(Y-axis - logo_height)/2` on the screen.
+	 * The center of the [LOGO] aligns with the vertical center of the screen.
+	 *
+	 * +---------------+
+	 * |               |
+	 * |               |
+	 * |    [LOGO]     |  <-- Vertically Centered
+	 * |               |
+	 * |               |
+	 * +---------------+
+	 */
+	FW_SPLASH_VALIGNMENT_CENTER = 0,
+
+	/*
+	 * The splash image is aligned to the top edge of the screen.
+	 *
+	 * +---------------+
+	 * |    [LOGO]     |  <-- Top Aligned
+	 * |               |
+	 * |               |
+	 * |               |
+	 * |               |
+	 * +---------------+
+	 */
+	FW_SPLASH_VALIGNMENT_TOP = 1,
+
+	/*
+	 * The splash image is aligned to the bottom edge of the screen.
+	 *
+	 * +---------------+
+	 * |               |
+	 * |               |
+	 * |               |
+	 * |               |
+	 * |    [LOGO]     |  <-- Bottom Aligned
+	 * +---------------+
+	 */
+	FW_SPLASH_VALIGNMENT_BOTTOM = 2,
+
+	/*
+	 * The splash image is placed in the vertical middle `(Y-axis/2)` of the screen
+	 * (without considering the `logo height`). This means the TOP EDGE of the
+	 * [LOGO] aligns with the screen's vertical midpoint line.
+	 *
+	 * +---------------+
+	 * | (Upper Half)  |
+	 * |               |
+	 * |    [LOGO]     | <-- [LOGO] aligns at Middle of the Y-axis
+	 * |               |
+	 * | (Lower Half)  |
+	 * +---------------+
+	 *
+	 * Note: The distinction between CENTER and MIDDLE is relevant as in for MIDDLE
+	 * alignment, it ignores the logo height (i.e., the logo's top edge is placed
+	 * at the screen's Y-midpoint). CENTER alignment, by contrast, would place
+	 * the geometrical center of the logo at the screen's Y-midpoint.
+	 */
+	FW_SPLASH_VALIGNMENT_MIDDLE = 3,
+};
+
+enum fw_splash_horizontal_alignment {
+	/*
+	 * The splash image is centered horizontally `(X-axis - logo_width)/2` on the screen.
+	 * The center of the [LOGO] aligns with the horizontal center of the screen.
+	 *
+	 * +-----------------+
+	 * |      [LOGO]     |
+	 * +-----------------+
+	 */
+	FW_SPLASH_HALIGNMENT_CENTER = 0,
+
+	/*
+	 * The splash image is aligned to the left edge of the screen.
+	 *
+	 * +-----------------+
+	 * |[LOGO]           |
+	 * +-----------------+
+	 */
+	FW_SPLASH_HALIGNMENT_LEFT = 1,
+
+	/*
+	 * The splash image is aligned to the right edge of the screen.
+	 *
+	 * +-----------------+
+	 * |           [LOGO]|
+	 * +-----------------+
+	 */
+	FW_SPLASH_HALIGNMENT_RIGHT = 2,
+};
+
+struct logo_config {
+	uintptr_t framebuffer_base;
+	uint32_t horizontal_resolution;
+	uint32_t vertical_resolution;
+	uint32_t bytes_per_scanline;
+	enum lb_fb_orientation panel_orientation;
+	enum fw_splash_horizontal_alignment halignment;
+	enum fw_splash_vertical_alignment valignment;
+	uint8_t logo_bottom_margin;
+};
+
+void render_logo_to_framebuffer(struct logo_config *config);
+void load_and_convert_bmp_to_blt(uintptr_t *logo, size_t *logo_size,
+	uintptr_t *blt, size_t *blt_size, uint32_t *pixel_height, uint32_t *pixel_width,
+	enum lb_fb_orientation orientation);
+void convert_bmp_to_blt(uintptr_t logo, size_t logo_size,
+	uintptr_t *blt, size_t *blt_size, uint32_t *pixel_height, uint32_t *pixel_width,
+	enum lb_fb_orientation orientation);
+
 /*
  * Allow platform-specific BMP logo overrides via HAVE_CUSTOM_BMP_LOGO config.
  * For example: Introduce configurable BMP logo for customization on platforms like ChromeOS
diff --git a/src/lib/Makefile.mk b/src/lib/Makefile.mk
index f13bb66f79..ecb06c4765 100644
--- a/src/lib/Makefile.mk
+++ b/src/lib/Makefile.mk
@@ -148,6 +148,7 @@ ramstage-y += hexstrtobin.c
 ramstage-y += wrdd.c
 ramstage-$(CONFIG_CONSOLE_CBMEM) += cbmem_console.c
 ramstage-$(CONFIG_BMP_LOGO) += bmp_logo.c
+ramstage-$(CONFIG_BMP_LOGO) += render_bmp.c
 ramstage-$(CONFIG_BOOTSPLASH) += bootsplash.c
 ramstage-$(CONFIG_BOOTSPLASH) += jpeg.c
 ramstage-$(CONFIG_COLLECT_TIMESTAMPS) += timestamp.c
diff --git a/src/lib/render_bmp.c b/src/lib/render_bmp.c
new file mode 100644
index 0000000000..7dc808b13c
--- /dev/null
+++ b/src/lib/render_bmp.c
@@ -0,0 +1,721 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <boot/coreboot_tables.h>
+#include <bootmode.h>
+#include <bootsplash.h>
+#include <bootstate.h>
+#include <console/console.h>
+#include <stdlib.h>
+#include <string.h>
+
+#include "render_bmp.h"
+
+static bool is_bmp_image_valid(struct bmp_image_header *header)
+{
+	/* Check if the BMP Header Signature is valid */
+	if (header->CharB != 'B' || header->CharM != 'M')
+		return false;
+
+	/* Check if the BMP Image Header Length is valid */
+	if (!header->PixelHeight || !header->PixelWidth)
+		return false;
+
+	if (header->Size < header->ImageOffset)
+		return false;
+
+	if (header->ImageOffset < sizeof(struct bmp_image_header))
+		return false;
+
+	return true;
+}
+
+static bool is_bmp_image_compressed(struct bmp_image_header *header)
+{
+	return header->CompressionType != 0;
+}
+
+static bool is_bitmap_format_supported(struct bmp_image_header *header)
+{
+	/*
+	 * Check BITMAP format is supported
+	 * BMP_IMAGE_HEADER = BITMAP_FILE_HEADER + BITMAP_INFO_HEADER
+	 */
+	if (header->HeaderSize != sizeof(struct bmp_image_header) -
+			 OFFSET_OF(struct bmp_image_header, HeaderSize))
+		return false;
+
+	return true;
+}
+
+static bool do_bmp_image_authentication(struct bmp_image_header *header)
+{
+	if (!is_bmp_image_valid(header)) {
+		printk(BIOS_ERR, "%s: BMP Image Header is invalid.\n", __func__);
+		return false;
+	}
+
+	/*
+	 * BMP image compression is unsupported by FSP implementation,
+	 * hence, exit if the BMP image is compressed.
+	 */
+	if (is_bmp_image_compressed(header)) {
+		printk(BIOS_ERR, "%s: BMP Image Compression is unsupported.\n", __func__);
+		return false;
+	}
+
+	if (!is_bitmap_format_supported(header)) {
+		printk(BIOS_ERR, "%s: BmpHeader Header Size (0x%x) is not as expected.\n",
+			 __func__, header->HeaderSize);
+		return false;
+	}
+
+	return true;
+}
+
+static uint32_t calculate_blt_buffer_size(struct bmp_image_header *header)
+{
+	uint32_t blt_buffer_size;
+
+	/* Calculate the size required for BLT buffer */
+	blt_buffer_size = header->PixelWidth * header->PixelHeight *
+			 sizeof(struct blt_pixel);
+	if (!blt_buffer_size)
+		return 0;
+
+	return blt_buffer_size;
+}
+
+static int get_color_map_num(struct bmp_image_header *header)
+{
+	int col_map_number;
+
+	switch (header->BitPerPixel) {
+	case 1:
+		col_map_number = 2;
+		break;
+	case 4:
+		col_map_number = 16;
+		break;
+	case 8:
+		col_map_number = 256;
+		break;
+	default:
+		/*
+		 * For other bit depths (e.g., 24-bit and 32-bit) that doesn't have
+		 * a standard palette, col_map_number remains 0.
+		 */
+		col_map_number = 0;
+		break;
+	}
+
+	/*
+	 * At times BMP file may have padding data between its header section and the
+	 * data section.
+	 */
+	if (header->ImageOffset - sizeof(struct bmp_image_header) <
+			 sizeof(struct bmp_color_map) * col_map_number)
+		return -1;
+
+	return col_map_number;
+}
+
+/*
+ * Visual Representation of the Flipping:
+ *
+ * Original BMP Image:
+ *
+ *      0 -----------------------------------------PixelWidth-1
+ *      |                                          |
+ *      |                                          |
+ *      |                                          |
+ *      PixelHeight-1------------------------------|
+ *
+ * Blitting Region:
+ *
+ *      (x, y) ----------------------------------- (x + blt_width, y)
+ *      |                                          |
+ *      |                                          |
+ *      (x, y + blt_height) -------------------- --(x + blt_width, y + blt_height)
+ *
+ * Flipped Coordinates:
+ *
+ * flipped_x:  Represents the horizontal coordinate from the `right` edge of the BMP,
+ *             accounting for the blit width.
+ *
+ * flipped_y:  Represents the vertical coordinate from the `bottom` edge of the BMP,
+ *             accounting for the blit height.
+ *
+ * Example (Orientation: LB_FB_ORIENTATION_BOTTOM_UP):
+ *
+ * If blt_width is small, flipped_x will be near PixelWidth.
+ * If blt_height is small, flipped_y will be near PixelHeight.
+ *
+ * The blit then starts at (flipped_x, blt_height), effectively flipping the
+ * horizontal position and using the original blit height.
+ *
+ * This allows for blitting from the bottom-left corner of the display panel.
+ */
+static bool calculate_adj_height_width(const struct bmp_image_header *header, size_t *adjusted_x,
+	 size_t *adjusted_y, enum lb_fb_orientation orientation, int blt_width, int blt_height)
+{
+	size_t flipped_x = header->PixelWidth - blt_width - 1;
+	size_t flipped_y = header->PixelHeight - blt_height - 1;
+
+	switch (orientation) {
+	case LB_FB_ORIENTATION_LEFT_UP:
+		*adjusted_x = flipped_y;
+		*adjusted_y = flipped_x;
+		break;
+
+	case LB_FB_ORIENTATION_BOTTOM_UP:
+		*adjusted_x = flipped_x;
+		*adjusted_y = blt_height;
+		break;
+
+	case LB_FB_ORIENTATION_RIGHT_UP:
+		*adjusted_x = blt_height;
+		*adjusted_y = blt_width;
+		break;
+
+	case LB_FB_ORIENTATION_NORMAL:
+	default:
+		*adjusted_x = blt_width;
+		*adjusted_y = flipped_y;
+		break;
+	}
+
+	return true;
+}
+
+/*
+ * Visual Representation of gop_width and calculate linear offset into the GOP buffer:
+ *
+ * GOP Display Buffer:
+ *
+ *      +------------------------------------------------+
+ *      | 0                                              |
+ *      | |--> gop_width pixels in this row              |
+ *      +------------------------------------------------+
+ *      | gop_width                                      |
+ *      |                                                |
+ *      | gop_width                                      |
+ *      | ...                                            |
+ *      +------------------------------------------------+
+ *      | gop_width                                      |
+ *      +------------------------------------------------+
+ *
+ * gop_width: Represents the width of a row in the GOP buffer.
+ * - It is determined by the `orientation` of the image.
+ * - For `LEFT_UP` and `RIGHT_UP`, the GOP width is the BMP image's `PixelHeight`.
+ * - For `BOTTOM_UP` and `NORMAL`, the GOP width is the BMP image's `PixelWidth`.
+ *
+ * gop_x, gop_y: Coordinates within the GOP buffer where the blit will start.
+ * - These are calculated by `calculate_adj_height_width` based on the `orientation`,
+ * `blt_width`, and `blt_height`.
+ *
+ * Pointer to the calculated pixel in the GOP blit buffer, or NULL on error.
+ * - Calculate `gop_blt_offset`as `gop_y * gop_width + gop_x` to determine the offset
+ *   to access the correct pixel within `gop_blt_buffer`.
+ * - `gop_y * gop_width` calculates the offset of the row.
+ * - `gop_x` calculates the offset within that row.
+ */
+static struct blt_pixel *get_gop_blt_pixel(
+	struct blt_pixel *gop_blt_buffer, const struct bmp_image_header *header,
+	 int blt_width, int blt_height, enum lb_fb_orientation orientation)
+{
+	size_t gop_x;
+	size_t gop_y;
+	size_t gop_width;
+
+	switch (orientation) {
+	case LB_FB_ORIENTATION_LEFT_UP:
+	case LB_FB_ORIENTATION_RIGHT_UP:
+		gop_width = header->PixelHeight;
+		break;
+
+	case LB_FB_ORIENTATION_BOTTOM_UP:
+	case LB_FB_ORIENTATION_NORMAL:
+	default:
+		gop_width = header->PixelWidth;
+		break;
+	}
+
+	if (!calculate_adj_height_width(header, &gop_x, &gop_y, orientation,
+			 blt_width, blt_height))
+		return NULL;
+
+	/*
+	 * Calculated pixel in the Graphics Output Protocol (GOP) blit buffer.
+	 * This offset represents the starting position where the blitted region will be placed
+	 * in the framebuffer.
+	 */
+	return &gop_blt_buffer[gop_y * gop_width + gop_x];
+}
+
+/*
+ * Fill BMP image into BLT buffer format with optional orientation
+ *
+ * +------------------------------------------------------------------+
+ * |  BMP Image (header: bmp_image_header)                        |
+ * |  (PixelWidth, PixelHeight)                                       |
+ * +------------------------------------------------------------------+
+ *        |
+ *        | (blt_width, blt_height) : Region to blit
+ *        V
+ * +------------------------------------------------------------------+
+ * |  calculate_adj_height_width(header, adjusted_x, adjusted_y,      |
+ * |                               orientation, blt_width, blt_height)|
+ * +------------------------------------------------------------------+
+ *        |
+ *        | Calculates adjusted coordinates based on orientation:
+ *        |   - flipped_x = header->PixelWidth - blt_width - 1
+ *        |   - flipped_y = header->PixelHeight - blt_height - 1
+ *        |   - Depending on 'orientation', adjusted_x and adjusted_y are set.
+ *        V
+ * +-------------------------------------------------------------------+
+ * |  get_gop_blt_pixel(gop_blt_buffer, header, blt_width, blt_height, |
+ * |                                                  orientation)     |
+ * +-------------------------------------------------------------------+
+ *        |
+ *        | 1. Determines gop_width based on orientation:
+ *        |    - LEFT_UP/RIGHT_UP: gop_width = header->PixelHeight,
+ *        |    - BOTTOM_UP/NORMAL: gop_width = header->PixelWidth,
+ *        | 2. Calls calculate_adj_height_width to get gop_x and gop_y.
+ *        | 3. GOP BLT offset: calculates linear offset into the GOP buffer
+ *        |    - gop_blt_offset = gop_y * gop_width + gop_x
+ *        | 4. GOP BLT offset is used to access the correct regions in:
+ *        V
+ * +------------------------------------------------------------------+
+ * |  GOP Blit Buffer (Framebuffer)                                   |
+ * +------------------------------------------------------------------+
+ */
+static void *fill_blt_buffer(struct bmp_image_header *header,
+	uintptr_t logo, size_t blt_buffer_size, enum lb_fb_orientation orientation)
+{
+	struct blt_pixel *gop_blt_buffer;
+	struct blt_pixel *gop_blt_ptr;
+	struct blt_pixel *gop_blt;
+	uint8_t *bmp_image;
+	uint8_t *bmp_header;
+	struct bmp_color_map *color_map;
+	size_t image_index;
+
+	gop_blt_ptr = malloc(sizeof(blt_buffer_size));
+	if (!gop_blt_ptr)
+		die("%s: out of memory. Consider increasing the `CONFIG_HEAP_SIZE`\n",
+			 __func__);
+
+	bmp_image = ((uint8_t *)logo) + header->ImageOffset;
+	bmp_header = bmp_image;
+	gop_blt_buffer = gop_blt_ptr;
+	color_map = (struct bmp_color_map *)(logo + sizeof(struct bmp_image_header));
+
+	for (size_t height = 0; height < header->PixelHeight; height++) {
+		for (size_t width = 0; width < header->PixelWidth; width++, bmp_image++) {
+			size_t index = 0;
+
+			gop_blt = get_gop_blt_pixel(gop_blt_buffer, header, width, height,
+							 orientation);
+			if (!gop_blt) {
+				free(gop_blt_ptr);
+				return NULL;
+			}
+
+			switch (header->BitPerPixel) {
+			/* Translate 1-bit (2 colors) BMP to 24-bit color */
+			case 1:
+				for (index = 0; index < 8 && width < header->PixelWidth; index++) {
+					uint8_t bit = ((*bmp_image) >> (7 - index)) & 0x1;
+					gop_blt->Red = color_map[bit].Red;
+					gop_blt->Green = color_map[bit].Green;
+					gop_blt->Blue = color_map[bit].Blue;
+					width++;
+					gop_blt = get_gop_blt_pixel(gop_blt_buffer, header, width, height,
+								 orientation);
+					if (!gop_blt) {
+						free(gop_blt_ptr);
+						return NULL;
+					}
+				}
+				width--;
+				break;
+
+			/* Translate 4-bit (16 colors) BMP Palette to 24-bit color */
+			case 4:
+				index = (*bmp_image) >> 4;
+				gop_blt->Red = color_map[index].Red;
+				gop_blt->Green = color_map[index].Green;
+				gop_blt->Blue = color_map[index].Blue;
+				if (width < (header->PixelWidth - 1)) {
+					width++;
+					gop_blt = get_gop_blt_pixel(gop_blt_buffer, header, width, height,
+								 orientation);
+					if (!gop_blt) {
+						free(gop_blt_ptr);
+						return NULL;
+					}
+					index = (*bmp_image) & 0x0f;
+					gop_blt->Red = color_map[index].Red;
+					gop_blt->Green = color_map[index].Green;
+					gop_blt->Blue = color_map[index].Blue;
+				}
+				break;
+
+			/* Translate 8-bit (256 colors) BMP Palette to 24-bit color */
+			case 8:
+				gop_blt->Red = color_map[*bmp_image].Red;
+				gop_blt->Green = color_map[*bmp_image].Green;
+				gop_blt->Blue = color_map[*bmp_image].Blue;
+				break;
+
+			/* For 24-bit BMP */
+			case 24:
+				gop_blt->Blue = *bmp_image++;
+				gop_blt->Green = *bmp_image++;
+				gop_blt->Red = *bmp_image;
+				break;
+
+			/* Convert 32 bit to 24bit bmp - just ignore the final byte of each pixel */
+			case 32:
+				gop_blt->Blue = *bmp_image++;
+				gop_blt->Green = *bmp_image++;
+				gop_blt->Red = *bmp_image++;
+				break;
+
+			/* Other bit format of BMP is not supported. */
+			default:
+				free(gop_blt_ptr);
+				gop_blt_ptr = NULL;
+
+				printk(BIOS_ERR, "%s, BMP Bit format not supported. 0x%X\n", __func__,
+					 header->BitPerPixel);
+				return NULL;
+			}
+		}
+		image_index = (uintptr_t)bmp_image - (uintptr_t)bmp_header;
+		/* Each row in BMP Image should be 4-byte align */
+		if ((image_index % 4) != 0)
+			bmp_image = bmp_image + (4 - (image_index % 4));
+	}
+
+	return gop_blt_ptr;
+}
+
+/* Helper function to perform the common BMP to GOP BLT conversion logic */
+static bool convert_bmp_to_gop_blt_common(uintptr_t logo, size_t logo_size,
+	uintptr_t *blt, size_t *blt_size, uint32_t *pixel_height,
+	uint32_t *pixel_width, enum lb_fb_orientation orientation)
+{
+	size_t blt_buffer_size;
+	struct bmp_image_header *bmp_header;
+
+	bmp_header = (struct bmp_image_header *)logo;
+
+	/* Authenticate BMP header and validate size against provided logo_size */
+	if (!do_bmp_image_authentication(bmp_header) || (bmp_header->Size != logo_size))
+		return false;
+
+	blt_buffer_size = calculate_blt_buffer_size(bmp_header);
+	if (!blt_buffer_size)
+		return false;
+
+	if (get_color_map_num(bmp_header) < 0)
+		return false;
+
+	bool is_standard_orientation = (orientation == LB_FB_ORIENTATION_NORMAL ||
+					orientation == LB_FB_ORIENTATION_BOTTOM_UP);
+
+	*blt_size = blt_buffer_size;
+	*pixel_height = is_standard_orientation ? bmp_header->PixelHeight : bmp_header->PixelWidth;
+	*pixel_width = is_standard_orientation ? bmp_header->PixelWidth : bmp_header->PixelHeight;
+	*blt = (uintptr_t)fill_blt_buffer(bmp_header, logo, blt_buffer_size, orientation);
+
+	return true;
+}
+
+/* Convert a *.BMP graphics image to a blt buffer */
+void load_and_convert_bmp_to_blt(uintptr_t *logo, size_t *logo_size,
+	uintptr_t *blt, size_t *blt_size, uint32_t *pixel_height, uint32_t *pixel_width,
+	enum lb_fb_orientation orientation)
+{
+	uintptr_t bmp;
+	size_t bmp_size;
+
+	if (!logo || !logo_size || !blt || !blt_size || !pixel_height || !pixel_width)
+		return;
+
+	bmp = (uintptr_t)bmp_load_logo(&bmp_size);
+
+	if (!bmp || bmp_size < sizeof(struct bmp_image_header))
+		return;
+
+	*logo = bmp;
+	*logo_size = bmp_size;
+
+	convert_bmp_to_gop_blt_common(*logo, *logo_size, blt, blt_size,
+				      pixel_height, pixel_width, orientation);
+}
+
+/* Convert a *.BMP graphics image (as per input `logo`) to a GOP blt buffer */
+void convert_bmp_to_blt(uintptr_t logo, size_t logo_size,
+	uintptr_t *blt, size_t *blt_size, uint32_t *pixel_height, uint32_t *pixel_width,
+	enum lb_fb_orientation orientation)
+{
+	if (!blt || !blt_size || !pixel_height || !pixel_width)
+		return;
+
+	if (!logo || logo_size < sizeof(struct bmp_image_header))
+		return;
+
+	convert_bmp_to_gop_blt_common(logo, logo_size, blt, blt_size,
+				      pixel_height, pixel_width, orientation);
+}
+
+/*
+ * Calculates the destination coordinates for the logo based on both horizontal and
+ * vertical alignment settings.
+ *
+ * horizontal_resolution: The horizontal resolution of the display panel.
+ * vertical_resolution: The vertical resolution of the display panel.
+ * logo_width: The width of the logo bitmap.
+ * logo_height: The height of the logo bitmap.
+ * halignment: The horizontal alignment setting. Use FW_SPLASH_HALIGNMENT_NONE
+ *             if only vertical alignment is specified.
+ * valignment: The vertical alignment setting. Use FW_SPLASH_VALIGNMENT_NONE
+ *             if only horizontal alignment is specified.
+ *
+ * Returning `struct logo_coordinates` that contains the calculated x and y coordinates
+ * for rendering the logo.
+ */
+static struct logo_coordinates calculate_logo_coordinates(
+	uint32_t horizontal_resolution, uint32_t vertical_resolution,
+	uint32_t logo_width, uint32_t logo_height,
+	enum fw_splash_horizontal_alignment halignment,
+	enum fw_splash_vertical_alignment valignment)
+{
+	struct logo_coordinates coords;
+
+	/* Calculate X coordinate */
+	switch (halignment) {
+	case FW_SPLASH_HALIGNMENT_LEFT:
+		coords.x = 0;
+		break;
+	case FW_SPLASH_HALIGNMENT_RIGHT:
+		coords.x = horizontal_resolution - logo_width;
+		break;
+	default: /* FW_SPLASH_HALIGNMENT_CENTER (default) */
+		coords.x = (horizontal_resolution - logo_width) / 2;
+		break;
+	}
+
+	/* Calculate Y coordinate */
+	switch (valignment) {
+	case FW_SPLASH_VALIGNMENT_MIDDLE:
+		coords.y = vertical_resolution / 2;
+		break;
+	case FW_SPLASH_VALIGNMENT_TOP:
+		coords.y = 0;
+		break;
+	case FW_SPLASH_VALIGNMENT_BOTTOM:
+		coords.y = vertical_resolution - logo_height;
+		break;
+	default: /* FW_SPLASH_VALIGNMENT_CENTER (default) */
+		coords.y = (vertical_resolution - logo_height) / 2;
+		break;
+	}
+
+	return coords;
+}
+
+/*
+ * Copies the logo to the framebuffer.
+ *
+ * framebuffer_base: The base address of the framebuffer.
+ * bytes_per_scanline: The number of bytes per scanline in the framebuffer.
+ * logo_buffer: The address of the logo data in BLT format.
+ * logo_width: The width of the logo bitmap.
+ * logo_height: The height of the logo bitmap.
+ * dest_x: The destination x-coordinate in the framebuffer for rendering the logo.
+ * dest_y: The destination y-coordinate in the framebuffer for rendering the logo.
+ */
+static void copy_logo_to_framebuffer(
+	uintptr_t framebuffer_base, uint32_t bytes_per_scanline,
+	uintptr_t logo_buffer, uint32_t logo_width, uint32_t logo_height,
+	uint32_t dest_x, uint32_t dest_y)
+{
+	size_t pixel_size = sizeof(struct blt_pixel);
+	size_t bytes_per_logo_line = logo_width * pixel_size;
+	uint8_t *framebuffer_offset = (uint8_t *)framebuffer_base + dest_y * bytes_per_scanline
+					 + dest_x * pixel_size;
+	uint8_t *dst_row_address = framebuffer_offset;
+	uint8_t *src_row_address = (uint8_t *)logo_buffer;
+	for (uint32_t i = 0; i < logo_height; i++) {
+		memcpy(dst_row_address, src_row_address, bytes_per_logo_line);
+		dst_row_address += bytes_per_scanline;
+		src_row_address += bytes_per_logo_line;
+	}
+}
+
+/*
+ * Adjust logo layout based on the panel orientation.
+ *
+ * logo_type: Logo type.
+ * config: Logo configuration information.
+ * logo_halignment: Resultant horizontal alignment setting.
+ * logo_valignment: Resultant vertical alignment setting.
+ * logo_bottom_margin: Resultant bottom margin.
+ */
+static void get_logo_layout(
+	enum bootsplash_type logo_type,
+	struct logo_config *config,
+	enum fw_splash_horizontal_alignment *logo_halignment,
+	enum fw_splash_vertical_alignment *logo_valignment,
+	uint8_t *logo_bottom_margin
+)
+{
+	if (!config || !logo_halignment || !logo_valignment || !logo_bottom_margin)
+		return;
+
+	if (logo_type == BOOTSPLASH_LOW_BATTERY || logo_type == BOOTSPLASH_CENTER) {
+		*logo_halignment = config->halignment;
+		*logo_valignment = config->valignment;
+		/* Override logo alignment if the default screen orientation is not normal */
+		if (config->panel_orientation != LB_FB_ORIENTATION_NORMAL)
+			*logo_valignment = FW_SPLASH_VALIGNMENT_CENTER;
+		*logo_bottom_margin = 0;
+	} else if (logo_type == BOOTSPLASH_FOOTER) {
+		*logo_halignment = FW_SPLASH_HALIGNMENT_CENTER;
+		*logo_valignment = FW_SPLASH_VALIGNMENT_CENTER;
+		switch (config->panel_orientation) {
+		case LB_FB_ORIENTATION_RIGHT_UP:
+			*logo_halignment = FW_SPLASH_HALIGNMENT_LEFT;
+			break;
+		case LB_FB_ORIENTATION_LEFT_UP:
+			*logo_halignment = FW_SPLASH_HALIGNMENT_RIGHT;
+			break;
+		case LB_FB_ORIENTATION_BOTTOM_UP:
+			*logo_valignment = FW_SPLASH_VALIGNMENT_TOP;
+			break;
+		default: /* LB_FB_ORIENTATION_NORMAL (default) */
+			*logo_valignment = FW_SPLASH_VALIGNMENT_BOTTOM;
+			break;
+		}
+		*logo_bottom_margin = config->logo_bottom_margin;
+	} else { // Default values
+		*logo_halignment = FW_SPLASH_HALIGNMENT_CENTER;
+		*logo_valignment = FW_SPLASH_VALIGNMENT_CENTER;
+		*logo_bottom_margin = 0;
+	}
+}
+
+/*
+ * Loads, converts, and renders a BMP logo to the framebuffer.
+ *
+ * logo_type: Logo type.
+ * config: Logo configuration information.
+ *
+ * Returns 0 on success, -1 on failure.
+ */
+static int load_and_render_logo_to_framebuffer(
+	enum bootsplash_type logo_type,
+	struct logo_config *config
+)
+{
+	uintptr_t logo;
+	size_t logo_size;
+	size_t blt_size;
+	uintptr_t blt_buffer;
+	uint32_t logo_height, logo_width;
+	struct logo_coordinates logo_coords;
+	enum fw_splash_horizontal_alignment halignment;
+	enum fw_splash_vertical_alignment valignment;
+	uint8_t logo_bottom_margin;
+
+	if (!config)
+		return -1;
+
+	logo = (uintptr_t)bmp_load_logo_by_type(logo_type, &logo_size);
+
+	if (!logo || logo_size < sizeof(struct bmp_image_header)) {
+		printk(BIOS_ERR, "%s: BMP image (%zu) is less than expected minimum size (%zu).\n",
+				 __func__, logo_size, sizeof(struct bmp_image_header));
+		return -1;
+	}
+
+	convert_bmp_to_blt(logo, logo_size, &blt_buffer, &blt_size,
+				   &logo_height, &logo_width, config->panel_orientation);
+
+	get_logo_layout(logo_type, config, &halignment, &valignment, &logo_bottom_margin);
+
+	logo_coords = calculate_logo_coordinates(config->horizontal_resolution,
+		 config->vertical_resolution, logo_width, logo_height, halignment, valignment);
+
+	if (logo_bottom_margin) {
+		if (config->panel_orientation == LB_FB_ORIENTATION_BOTTOM_UP ||
+				 config->panel_orientation == LB_FB_ORIENTATION_NORMAL)
+			logo_coords.y -= logo_bottom_margin;
+		else
+			logo_coords.x -= logo_bottom_margin;
+	}
+
+	copy_logo_to_framebuffer(config->framebuffer_base, config->bytes_per_scanline, blt_buffer,
+				 logo_width, logo_height, logo_coords.x, logo_coords.y);
+
+	bmp_release_logo();
+
+	return 0;
+}
+
+/*
+ * Loads, converts, and renders a BMP logo to the framebuffer.
+ * The logo type (primary or low battery etc.) is seletcted dynamically.
+ *
+ * config: Logo configuration information.
+ *
+ */
+void render_logo_to_framebuffer(struct logo_config *config)
+{
+	if (!config)
+		return;
+
+	if (config->framebuffer_base == 0) {
+		/* Try to load from already populated framebuffer information */
+		struct lb_framebuffer framebuffer;
+		memset(&framebuffer, 0, sizeof(struct lb_framebuffer));
+		fill_lb_framebuffer(&framebuffer);
+		/* Exit if framebuffer is still not available */
+		if (framebuffer.physical_address == 0)
+			return;
+		config->framebuffer_base = framebuffer.physical_address;
+		config->horizontal_resolution = framebuffer.x_resolution;
+		config->vertical_resolution = framebuffer.y_resolution;
+		config->bytes_per_scanline = framebuffer.bytes_per_line;
+	}
+
+	/*
+	 * If the device is in low-battery mode and the low-battery splash screen is being
+	 * displayed, prevent further operation and bail out early.
+	 */
+	if (platform_is_low_battery_shutdown_needed()) {
+		if (load_and_render_logo_to_framebuffer(BOOTSPLASH_LOW_BATTERY, config) != 0) {
+			printk(BIOS_ERR, "%s: Failed to render low-battery logo.\n", __func__);
+		}
+		return;
+	}
+
+	/* Render the main logo */
+	if (load_and_render_logo_to_framebuffer(BOOTSPLASH_CENTER, config) != 0) {
+		printk(BIOS_ERR, "%s: Failed to render main splash screen logo.\n", __func__);
+	} else if (CONFIG(SPLASH_SCREEN_FOOTER)) {
+		/* Render the footer logo */
+		if (load_and_render_logo_to_framebuffer(BOOTSPLASH_FOOTER, config) != 0)
+			printk(BIOS_ERR, "%s: Failed to render footer logo.\n", __func__);
+	}
+}
+
+static void release_logo(void *arg_unused)
+{
+	bmp_release_logo();
+}
+
+BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_LOAD, BS_ON_EXIT, release_logo, NULL);
diff --git a/src/lib/render_bmp.h b/src/lib/render_bmp.h
new file mode 100644
index 0000000000..41ef273b86
--- /dev/null
+++ b/src/lib/render_bmp.h
@@ -0,0 +1,58 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#ifndef __RENDER_BMP_H__
+#define __RENDER_BMP_H__
+
+#ifndef OFFSET_OF
+#if (defined (__GNUC__) && __GNUC__ >= 4) || defined (__clang__)
+#define OFFSET_OF(TYPE, Field)  ((size_t) __builtin_offsetof(TYPE, Field))
+#endif
+#endif
+
+#ifndef OFFSET_OF
+#define OFFSET_OF(TYPE, Field)  ((size_t) &(((TYPE *)0)->Field))
+#endif
+
+#pragma pack(1)
+
+struct bmp_color_map {
+	uint8_t Blue;
+	uint8_t Green;
+	uint8_t Red;
+	uint8_t Reserved;
+};
+
+struct bmp_image_header {
+	char     CharB;				// 'B'
+	char     CharM;				// 'M'
+	uint32_t Size;
+	uint16_t Reserved[2];
+	uint32_t ImageOffset;
+	uint32_t HeaderSize;
+	uint32_t PixelWidth;
+	uint32_t PixelHeight;
+	uint16_t Planes;
+	uint16_t BitPerPixel;			// 1, 4, 8, 24 or 32
+	uint32_t CompressionType;
+	uint32_t ImageSize;			// Compressed image size in bytes
+	uint32_t XPixelsPerMeter;
+	uint32_t YPixelsPerMeter;
+	uint32_t NumberOfColors;
+	uint32_t ImportantColors;
+};
+
+struct blt_pixel {
+	uint8_t Blue;
+	uint8_t Green;
+	uint8_t Red;
+	uint8_t Reserved;
+};
+
+struct logo_coordinates {
+	uint32_t x;
+	uint32_t y;
+};
+
+#pragma pack()
+
+#endif // __RENDER_BMP_H__
diff --git a/src/soc/intel/common/block/include/intelblocks/cfg.h b/src/soc/intel/common/block/include/intelblocks/cfg.h
index 8aac699525..26252ac867 100644
--- a/src/soc/intel/common/block/include/intelblocks/cfg.h
+++ b/src/soc/intel/common/block/include/intelblocks/cfg.h
@@ -4,6 +4,7 @@
 #define SOC_INTEL_COMMON_BLOCK_CFG_H
 
 #include <boot/coreboot_tables.h>
+#include <bootsplash.h>
 #include <intelblocks/gspi.h>
 #include <drivers/i2c/designware/dw_i2c.h>
 #include <intelblocks/mmc.h>
@@ -13,106 +14,6 @@ enum {
 	CHIPSET_LOCKDOWN_FSP,		/* FSP handles locking per UPDs */
 };
 
-/*
- * Specifies the vertical alignment for the splash screen image.
- *
- * Visual Guide (representing the display area and the [LOGO]):
- *
- * Each option dictates the vertical placement of the splash image
- * within the display's height.
- */
-enum fw_splash_vertical_alignment {
-	/*
-	 * The splash image is centered vertically `(Y-axis - logo_height)/2` on the screen.
-	 * The center of the [LOGO] aligns with the vertical center of the screen.
-	 *
-	 * +---------------+
-	 * |               |
-	 * |               |
-	 * |    [LOGO]     |  <-- Vertically Centered
-	 * |               |
-	 * |               |
-	 * +---------------+
-	 */
-	FW_SPLASH_VALIGNMENT_CENTER = 0,
-
-	/*
-	 * The splash image is aligned to the top edge of the screen.
-	 *
-	 * +---------------+
-	 * |    [LOGO]     |  <-- Top Aligned
-	 * |               |
-	 * |               |
-	 * |               |
-	 * |               |
-	 * +---------------+
-	 */
-	FW_SPLASH_VALIGNMENT_TOP = 1,
-
-	/*
-	 * The splash image is aligned to the bottom edge of the screen.
-	 *
-	 * +---------------+
-	 * |               |
-	 * |               |
-	 * |               |
-	 * |               |
-	 * |    [LOGO]     |  <-- Bottom Aligned
-	 * +---------------+
-	 */
-	FW_SPLASH_VALIGNMENT_BOTTOM = 2,
-
-	/*
-	 * The splash image is placed in the vertical middle `(Y-axis/2)` of the screen
-	 * (without considering the `logo height`). This means the TOP EDGE of the
-	 * [LOGO] aligns with the screen's vertical midpoint line.
-	 *
-	 * +---------------+
-	 * | (Upper Half)  |
-	 * |               |
-	 * |    [LOGO]     | <-- [LOGO] aligns at Middle of the Y-axis
-	 * |               |
-	 * | (Lower Half)  |
-	 * +---------------+
-	 *
-	 * Note: The distinction between CENTER and MIDDLE is relevant as in for MIDDLE
-	 * alignment, it ignores the logo height (i.e., the logo's top edge is placed
-	 * at the screen's Y-midpoint). CENTER alignment, by contrast, would place
-	 * the geometrical center of the logo at the screen's Y-midpoint.
-	 */
-	FW_SPLASH_VALIGNMENT_MIDDLE = 3,
-};
-
-enum fw_splash_horizontal_alignment {
-	/*
-	 * The splash image is centered horizontally `(X-axis - logo_width)/2` on the screen.
-	 * The center of the [LOGO] aligns with the horizontal center of the screen.
-	 *
-	 * +-----------------+
-	 * |      [LOGO]     |
-	 * +-----------------+
-	 */
-	FW_SPLASH_HALIGNMENT_CENTER = 0,
-
-	/*
-	 * The splash image is aligned to the left edge of the screen.
-	 *
-	 * +-----------------+
-	 * |[LOGO]           |
-	 * +-----------------+
-	 */
-	FW_SPLASH_HALIGNMENT_LEFT = 1,
-
-	/*
-	 * The splash image is aligned to the right edge of the screen.
-	 *
-	 * +-----------------+
-	 * |           [LOGO]|
-	 * +-----------------+
-	 */
-	FW_SPLASH_HALIGNMENT_RIGHT = 2,
-};
-
 /*
  * This structure will hold data required by common blocks.
  * These are soc specific configurations which will be filled by soc.

From 2ee78458bec6816821d6fcdc14ece97d02b5a9c9 Mon Sep 17 00:00:00 2001
From: Sowmya Aralguppe <sowmya.aralguppe@intel.com>
Date: Mon, 21 Jul 2025 11:01:26 +0530
Subject: [PATCH 1653/3886] soc/intel/pantherlake: Use CONSUMED_BIOS bit
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

After the BIOS reads and processes the crashLog record, it sets the
CONSUMED_BIOS bit to indicate that the reading and storing of crashlog
record is complete. This is read only bit. When this bit is set ,
crashlog discovery and data collection are skipped. This bit helps in
preventing the same crashLog from being extracted multiple times after
a reset.

BUG= b:None
TEST= The header value during warm boot after crash
      cpu_cl_disc_tab.header.data dw0=88420003, dw1=0x0

Change-Id: I4b9e6900218f28b6beb71b7667bc1c57f0134a84
Signed-off-by: Sowmya Aralguppe <sowmya.aralguppe@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88499
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Reviewed-by: <srinivas.kulkarni@intel.com>
---
 src/soc/intel/pantherlake/crashlog.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/soc/intel/pantherlake/crashlog.c b/src/soc/intel/pantherlake/crashlog.c
index 0f288efe14..d9a80f46c1 100644
--- a/src/soc/intel/pantherlake/crashlog.c
+++ b/src/soc/intel/pantherlake/crashlog.c
@@ -17,7 +17,7 @@
 #define CRASHLOG_NODES_COUNT		0x1
 #define CRASHLOG_PUNIT_STORAGE_OFF_MASK	BIT(24)
 #define CRASHLOG_RE_ARM_STATUS_MASK	BIT(25)
-#define CRASHLOG_CONSUMED_MASK		BIT(31)
+#define CRASHLOG_CONSUMED_BIOS_MASK	BIT(27)
 
 /* Global crashLog info */
 static bool m_pmc_crash_log_support;
@@ -327,7 +327,7 @@ static bool cpu_cl_gen_discovery_table(void)
 			continue;
 
 		u32 dw0 = read32p(disc_tab_addr + cur_offset);
-		if (dw0 & CRASHLOG_CONSUMED_MASK) {
+		if (dw0 & CRASHLOG_CONSUMED_BIOS_MASK) {
 			printk(BIOS_DEBUG, "cpu crashlog records already consumed."
 						"id: 0x%x dw0: 0x%x\n", i, dw0);
 			break;

From 182ba5279279e63f101b12e34c2d42f771a0c2e7 Mon Sep 17 00:00:00 2001
From: Sowmya Aralguppe <sowmya.aralguppe@intel.com>
Date: Mon, 21 Jul 2025 11:55:59 +0530
Subject: [PATCH 1654/3886] soc/intel/pantherlake: Remove mailbox interface
 offset
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

In PTL Crashlog Watcher interface is used instead of Mailbox since it
is based on the Intel Platform Monitoring Technology (PMT) standard.
The Watcher interface provides a more flexible and efficient way to
control and monitor crashlog collection. Hence the functionalities like
rearm and clear are implemented using watcher interface instead of BIOS
mailbox to PUNIT.

Change-Id: I24c5c9753a577b255a7129d20ab83f93001a0485
Signed-off-by: Sowmya Aralguppe <sowmya.aralguppe@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88500
Reviewed-by: <srinivas.kulkarni@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
---
 src/soc/intel/pantherlake/include/soc/crashlog.h | 3 ---
 1 file changed, 3 deletions(-)

diff --git a/src/soc/intel/pantherlake/include/soc/crashlog.h b/src/soc/intel/pantherlake/include/soc/crashlog.h
index 5b988e9729..eed653ba7d 100644
--- a/src/soc/intel/pantherlake/include/soc/crashlog.h
+++ b/src/soc/intel/pantherlake/include/soc/crashlog.h
@@ -15,9 +15,6 @@
 #define TEL_DVSEC_TBIR_BAR0			0
 #define TEL_DVSEC_TBIR_BAR1			1
 
-/* CPU CrashLog MMIO Registers */
-#define CRASHLOG_MAILBOX_INTF_ADDRESS		0x6038
-
 typedef union {
 	struct {
 		u32 reserved1		:27;

From eb1b5ee11608c68f370c75750c389cd0b7f01ba9 Mon Sep 17 00:00:00 2001
From: Jeremy Compostella <jeremy.compostella@intel.com>
Date: Thu, 17 Jul 2025 12:27:07 -0700
Subject: [PATCH 1655/3886] soc/intel/cmn/block/fast_spi: Introduce a DMA
 transfer queue

This commit implements a token-based queuing system to reduce delays
between consecutive DMA operations. The queuing mechanism aims to
improve overall throughput.

A Kconfig option FAST_SPI_DMA_QUEUE_SIZE defines the maximum number of
concurrent DMA transfers that can be queued and processed.

When DMA transfers are queued, a new thread is initiated to run
fast_spi_dma_main_thread(). This function consistently monitors for
available transfer tokens and performs DMA operations when tokens are in
the DMA_REQUESTED state. If there are no tokens in the desired state,
the thread_running flag is set to false, and the thread terminates
smoothly.

While it provides a barely perceptible boot time improvement with the
Panther Lake configuration, it makes the boot flow more consistent and
predictable.

TEST=On a Fatcat device with CBFS_PRELOAD enabled and set up, we observe
     consecutive logs as follows, proving a new DMA transfer is issued
     as soon as the previous one's completion is detected.
     [DEBUG]  Fast-SPI: transfer completed in 2574 us
     [DEBUG]  Fast-SPI: Reading 240 blocks via DMA

Change-Id: Ic5249362041cfa028885874b43893e1d7942ed94
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88474
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
---
 src/soc/intel/common/block/fast_spi/Kconfig   |   8 ++
 .../common/block/fast_spi/fast_spi_dma.c      | 122 ++++++++++++++++--
 2 files changed, 122 insertions(+), 8 deletions(-)

diff --git a/src/soc/intel/common/block/fast_spi/Kconfig b/src/soc/intel/common/block/fast_spi/Kconfig
index a983797989..f49b7d9b51 100644
--- a/src/soc/intel/common/block/fast_spi/Kconfig
+++ b/src/soc/intel/common/block/fast_spi/Kconfig
@@ -70,3 +70,11 @@ config FAST_SPI_DMA
 	  callback. Although DMA transfers may not be significantly faster,
 	  they can free up CPU resources for other meaningful tasks in a
 	  multitasking environment (see COOP_MULTITASKING).
+
+config FAST_SPI_DMA_QUEUE_SIZE
+	int
+	depends on FAST_SPI_DMA
+	default 4
+	help
+	  Defines the maximum number of concurrent DMA transfers that can
+	  be queued and processed.
diff --git a/src/soc/intel/common/block/fast_spi/fast_spi_dma.c b/src/soc/intel/common/block/fast_spi/fast_spi_dma.c
index c6bf38c7d4..e4eea9d704 100644
--- a/src/soc/intel/common/block/fast_spi/fast_spi_dma.c
+++ b/src/soc/intel/common/block/fast_spi/fast_spi_dma.c
@@ -55,11 +55,37 @@ union fast_spi_dma_status {
 	} fields;
 };
 
+enum transfer_state {
+	DMA_TOKEN_FREE,
+	DMA_REQUESTED,
+	DMA_IN_PROGRESS,
+	DMA_COMPLETE,
+	DMA_FAILED
+};
+
+struct fast_spi_dma_transfer {
+	enum transfer_state state;
+	uint32_t flash_offset;
+	uint32_t block_count;
+	void *buffer;
+};
+
 #define FAST_SPI_DMA_BLOCK_ALIGN	KiB
 #define FAST_SPI_DMA_TIMEOUT_MSEC	1000
 #define FAST_SPI_DMA_DELAY_STEP_USEC	200
 #define FAST_SPI_DEV			DEV_PTR(fast_spi)
 
+/*
+ * This array holds the transfer tokens used for managing DMA operations with the Fast
+ * SPI interface. Each token represents a transfer request.  The number of tokens is
+ * determined by the FAST_SPI_DMA_QUEUE_SIZE kconfig, which defines the maximum number of
+ * concurrent DMA transfers that can be queued and processed.
+ *
+ * The tokens are utilized by the DMA transfer management functions to execute transfers
+ * in a sequential manner.
+ */
+static struct fast_spi_dma_transfer tokens[CONFIG_FAST_SPI_DMA_QUEUE_SIZE];
+
 /*
  * The bios_top variable stores the offset indicating the end of the BIOS region within
  * the SPI flash memory map. It is calculated based on the size and arrangement of memory
@@ -77,11 +103,12 @@ static uint32_t bios_top;
 static const struct region_device_ops *mmap_ops;
 
 /*
- * The fast_spi_dma_mutex is used to ensure thread-safe access to DMA operations. This
- * synchronization mechanism guarantees that only one thread can perform DMA operations
- * at a time.
+ * This boolean variable is used to track whether the Fast SPI DMA thread is actively
+ * running. It is set to true when the thread is executing and handling DMA transfer
+ * requests. When no transfer tokens are in the requested state, the thread sets this
+ * variable to false and exits gracefully.
  */
-static struct thread_mutex fast_spi_dma_mutex;
+static bool thread_running;
 
 static inline uint32_t fast_spi_read(enum fast_spi_dma_register reg)
 {
@@ -224,6 +251,75 @@ static enum cb_err fast_spi_dma_mmap_readat(const struct region_device *rd, void
 	return CB_SUCCESS;
 }
 
+static struct fast_spi_dma_transfer *fast_spi_dma_find_token(enum transfer_state state)
+{
+	struct fast_spi_dma_transfer *cur;
+	size_t i;
+
+	for (i = 0, cur = tokens; i < ARRAY_SIZE(tokens); i++, cur++)
+		if (cur->state == state)
+			return cur;
+
+	return NULL;
+}
+
+/*
+ * This function operates as the core logic for handling Fast SPI DMA transfers. It
+ * continuously checks for transfer tokens in the DMA_REQUESTED state and executes the
+ * associated DMA transfer operations. If no tokens are found in the requested state, it
+ * sets the thread_running flag to false and exits the thread gracefully.
+ */
+static enum cb_err fast_spi_dma_main_thread(void *arg)
+{
+	struct fast_spi_dma_transfer *token;
+
+	thread_running = true;
+	for (;;) {
+		token = fast_spi_dma_find_token(DMA_REQUESTED);
+		if (!token)
+			break;
+
+		token->state = DMA_IN_PROGRESS;
+		enum cb_err ret = fast_spi_do_dma_transfer(token->buffer,
+							   token->block_count,
+							   token->flash_offset);
+		token->state = ret == CB_SUCCESS ? DMA_COMPLETE : DMA_FAILED;
+	}
+	thread_running = false;
+
+	return CB_SUCCESS;
+}
+
+/*
+ * This function is responsible for allocating and preparing a new DMA transfer token to
+ * perform a data transfer from the SPI flash to a buffer. It also ensures that the DMA
+ * management thread is running. If the thread is not running, it attempts to start it.
+ */
+static struct fast_spi_dma_transfer *fast_spi_dma_queue_transfer(void *buffer,
+								 uint32_t block_count,
+								 uint32_t flash_offset)
+{
+	struct fast_spi_dma_transfer *token = fast_spi_dma_find_token(DMA_TOKEN_FREE);
+	if (!token) {
+		printk(BIOS_ERR, "Fast-SPI: Could not find a new transfer token\n");
+		return NULL;
+	}
+
+	token->buffer = buffer;
+	token->flash_offset = flash_offset;
+	token->block_count = block_count;
+	token->state = DMA_REQUESTED;
+
+	printk(BIOS_DEBUG, "Fast-SPI: %d blocks transfer token queued\n", block_count);
+
+	/* Ensure the DMA transfer thread is running. */
+	static struct thread_handle handle;
+	if (!thread_running && thread_run(&handle, fast_spi_dma_main_thread, NULL) != 0)
+		return NULL;
+
+	return token;
+}
+
 /*
  * Perform DMA transfer from SPI flash to a buffer.
  *
@@ -266,6 +362,8 @@ static enum cb_err fast_spi_dma_mmap_readat(const struct region_device *rd, void
 static ssize_t fast_spi_dma_transfer(const struct region_device *rd, void *b,
 				     size_t offset, size_t size)
 {
+	enum cb_err ret;
+
 	/* Calculate aligned offset and flash offset for DMA transfer. */
 	uint32_t aligned_offset = ALIGN_UP(offset, FAST_SPI_DMA_BLOCK_ALIGN);
 	uint32_t flash_offset = (bios_top - aligned_offset) / FAST_SPI_DMA_BLOCK_ALIGN;
@@ -273,10 +371,14 @@ static ssize_t fast_spi_dma_transfer(const struct region_device *rd, void *b,
 	uint32_t block_count = (size - early_bytes) / FAST_SPI_DMA_BLOCK_ALIGN;
 
 	/* Perform DMA transfer. */
-	thread_mutex_lock(&fast_spi_dma_mutex);
-	enum cb_err ret = fast_spi_do_dma_transfer(b, block_count, flash_offset);
-	thread_mutex_unlock(&fast_spi_dma_mutex);
-	if (ret != CB_SUCCESS) {
+	struct fast_spi_dma_transfer *token = fast_spi_dma_queue_transfer(b, block_count,
+									  flash_offset);
+	if (!token)
+		return -1;
+	/* Wait for completion */
+	while (token->state == DMA_REQUESTED || token->state == DMA_IN_PROGRESS)
+		udelay(FAST_SPI_DMA_DELAY_STEP_USEC);
+	if (token->state != DMA_COMPLETE) {
 		printk(BIOS_ERR, "Fast-SPI: DMA transfer failed, falling back to memory map operation\n");
 		return -1;
 	}
@@ -302,6 +404,10 @@ static ssize_t fast_spi_dma_transfer(const struct region_device *rd, void *b,
 			return transferred;
 		}
 	}
+
+	/* We are done with the transfer token. */
+	token->state = DMA_TOKEN_FREE;
+
 	return transferred;
 }
 

From 2de0158eecd8dd75f42515d0b57eef731e68b15c Mon Sep 17 00:00:00 2001
From: Jeremy Compostella <jeremy.compostella@intel.com>
Date: Thu, 3 Jul 2025 17:18:36 -0700
Subject: [PATCH 1656/3886] soc/intel/pantherlake: Add asynchronous CBFS file
 loading support

This commit introduces support for asynchronous coreboot File
System (CBFS) file loading from SPINOR, specifically targeting the
fsps.bin file, in the Intel Panther Lake (PTL) System on a Chip (SoC)
platform. The primary motivation for this change is to improve boot time
performance by utilizing SPI Direct Memory Access (DMA) to preload files
while the Central Processing Unit (CPU) continues executing other tasks.

This feature uses cooperative multithreading. Because the scheduling is
cooperative, the boot process stays mostly predictable, which minimizes
debugging difficulties while still enhancing boot performance.

The preload operations are strategically modified according to the
chipset lockdown settings. This guarantees that payload preloading is
finalized prior to SPI DMA locking when the chipset lockdown is managed
by FSP or otherwise maximizes the pre-loading feature.

Note: As there is no UPD to control the Fast DMI DMA interface lockdown,
a special FSP binary, built without the Fast SPI DMA driver
(PcdSpiDmaEnable), is required when chipset lockdown setting is set to
CHIPSET_LOCKDOWN_COREBOOT.

TEST=On a Fatcat device, with CHIPSET_LOCKDOWN_COREBOOT, the boot time
     has improved by around 17-18 ms.

Change-Id: I4106058d382b99eac5f988c134cc02f024f7d473
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88300
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/soc/intel/pantherlake/Kconfig        | 12 ++++++++
 src/soc/intel/pantherlake/Makefile.mk    |  1 +
 src/soc/intel/pantherlake/cbfs_preload.c | 35 ++++++++++++++++++++++++
 src/soc/intel/pantherlake/fsp_params.c   |  6 ++++
 4 files changed, 54 insertions(+)
 create mode 100644 src/soc/intel/pantherlake/cbfs_preload.c

diff --git a/src/soc/intel/pantherlake/Kconfig b/src/soc/intel/pantherlake/Kconfig
index 9f4e748f74..2ebc92a78d 100644
--- a/src/soc/intel/pantherlake/Kconfig
+++ b/src/soc/intel/pantherlake/Kconfig
@@ -6,6 +6,8 @@ config SOC_INTEL_PANTHERLAKE_BASE
 	select ARCH_X86
 	select BOOT_DEVICE_SUPPORTS_WRITES
 	select CACHE_MRC_SETTINGS
+	select CBFS_PRELOAD
+	select COOP_MULTITASKING
 	select CPU_INTEL_COMMON
 	select CPU_INTEL_COMMON_VOLTAGE
 	select CPU_INTEL_FIRMWARE_INTERFACE_TABLE
@@ -16,6 +18,7 @@ config SOC_INTEL_PANTHERLAKE_BASE
 	select POSTPONE_SPI_ACCESS
 	select DISPLAY_FSP_VERSION_INFO_2
 	select DRIVERS_USB_ACPI
+	select FAST_SPI_DMA
 	select FAST_SPI_SUPPORTS_EXT_BIOS_WINDOW
 	select FSP_COMPRESS_FSP_S_LZ4
 	select FSP_M_XIP
@@ -460,4 +463,13 @@ config DEBUG_STACK_OVERFLOW_BREAKPOINTS_IN_ALL_STAGES
 	bool
 	default n
 
+# Increase the CBFS cache size to accommodate FSP-S binary pre-loading
+# process.
+config RAMSTAGE_CBFS_CACHE_SIZE
+	default 0xd0000
+
+# Fast SPI DMA operations require 1 KiB-aligned memory buffers.
+config CBFS_CACHE_ALIGN
+	default 1024
+
 endif
diff --git a/src/soc/intel/pantherlake/Makefile.mk b/src/soc/intel/pantherlake/Makefile.mk
index e2f8dd7c6c..6476bf6e36 100644
--- a/src/soc/intel/pantherlake/Makefile.mk
+++ b/src/soc/intel/pantherlake/Makefile.mk
@@ -26,6 +26,7 @@ romstage-y += pcie_rp.c
 romstage-y += reset.c
 
 ramstage-y += acpi.c
+ramstage-y += cbfs_preload.c
 ramstage-y += chip.c
 ramstage-y += cpu.c
 ramstage-$(CONFIG_SOC_INTEL_CRASHLOG) += crashlog.c
diff --git a/src/soc/intel/pantherlake/cbfs_preload.c b/src/soc/intel/pantherlake/cbfs_preload.c
new file mode 100644
index 0000000000..7e2cd56f93
--- /dev/null
+++ b/src/soc/intel/pantherlake/cbfs_preload.c
@@ -0,0 +1,35 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <bootstate.h>
+#include <cbfs.h>
+#include <fsp/api.h>
+#include <intelblocks/cfg.h>
+#include <program_loading.h>
+
+static void preload_pre_fsps(void *unused)
+{
+	preload_fsps();
+
+	struct soc_intel_common_config *config = chip_get_common_soc_structure();
+	/* If chipset lockdown is handled by FSP, CBFS pre-loading must be completed
+	   before FSP-S finishes. In this case, it yields better results to preload the
+	   payload before lockdown.*/
+	if (config->chipset_lockdown == CHIPSET_LOCKDOWN_FSP)
+		payload_preload();
+}
+
+BOOT_STATE_INIT_ENTRY(BS_PRE_DEVICE, BS_ON_ENTRY, preload_pre_fsps, NULL);
+
+static void preload_post_fsps(void *unused)
+{
+	struct soc_intel_common_config *config = chip_get_common_soc_structure();
+	/* If the chipset lockdown is handled by FSP, SPI DMA is locked, and we cannot
+	   preload any other CBFS files. */
+	if (config->chipset_lockdown == CHIPSET_LOCKDOWN_FSP)
+		return;
+
+	cbfs_preload(CONFIG_CBFS_PREFIX "/dsdt.aml");
+	payload_preload();
+}
+
+BOOT_STATE_INIT_ENTRY(BS_DEV_ENUMERATE, BS_ON_ENTRY, preload_post_fsps, NULL);
diff --git a/src/soc/intel/pantherlake/fsp_params.c b/src/soc/intel/pantherlake/fsp_params.c
index df4f350c48..b5dfd4d4df 100644
--- a/src/soc/intel/pantherlake/fsp_params.c
+++ b/src/soc/intel/pantherlake/fsp_params.c
@@ -2,6 +2,7 @@
 
 #include <boot/coreboot_tables.h>
 #include <bootmode.h>
+#include <cbfs.h>
 #include <cpu/intel/microcode.h>
 #include <fsp/api.h>
 #include <fsp/debug.h>
@@ -832,6 +833,11 @@ void platform_fsp_silicon_multi_phase_init_cb(uint32_t phase_index)
 			const struct soc_intel_pantherlake_config *config = config_of_soc();
 			tcss_configure(config->typec_aux_bias_pads);
 		}
+
+		/* Allow CBFS preload transfers to complete before FSP-S locks SPI DMA. */
+		struct soc_intel_common_config *config = chip_get_common_soc_structure();
+		if (config->chipset_lockdown == CHIPSET_LOCKDOWN_FSP)
+			cbfs_preload_wait_for_all();
 		break;
 	default:
 		break;

From f131f0e336748d91c1c5bc5b24d72307b467c08b Mon Sep 17 00:00:00 2001
From: LiLiang Chen <liliang.chen@mediatek.corp-partner.google.com>
Date: Tue, 10 Jun 2025 15:08:17 +0800
Subject: [PATCH 1657/3886] soc/mediatek/mt8189: Add clk_buf and srclken_rc
 drivers

MT8189 uses MT6359 clk_buf, and will use new RC mode with srclken_rc.
The clk_buf will provide several 26M clocks, and these clocks can be
independently turned on.

BUG=b:379008996,b:422503190,b:403478729
BRANCH=none
TEST=show driver init log:
RG_CENTRAL_CFG1: 0x104014e5
RG_CENTRAL_CFG2: 0x1010
RG_CENTRAL_CFG3: 0x400f

Signed-off-by: LiLiang Chen <liliang.chen@mediatek.corp-partner.google.com>
Signed-off-by: Vince Liu <vince-wl.liu@mediatek.corp-partner.google.com>
Change-Id: Ia04526d55191c695caf3ef40002e1ec99f299966
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88525
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/soc/mediatek/mt8189/Makefile.mk           |   2 +
 src/soc/mediatek/mt8189/clkbuf_ctl.c          | 218 ++++++++++++++
 .../mediatek/mt8189/include/soc/addressmap.h  |   1 +
 .../mediatek/mt8189/include/soc/clkbuf_ctl.h  | 207 +++++++++++++
 .../mediatek/mt8189/include/soc/srclken_rc.h  | 156 ++++++++++
 src/soc/mediatek/mt8189/srclken_rc.c          | 281 ++++++++++++++++++
 6 files changed, 865 insertions(+)
 create mode 100644 src/soc/mediatek/mt8189/clkbuf_ctl.c
 create mode 100644 src/soc/mediatek/mt8189/include/soc/clkbuf_ctl.h
 create mode 100644 src/soc/mediatek/mt8189/include/soc/srclken_rc.h
 create mode 100644 src/soc/mediatek/mt8189/srclken_rc.c

diff --git a/src/soc/mediatek/mt8189/Makefile.mk b/src/soc/mediatek/mt8189/Makefile.mk
index b0adf83fa7..57666fc1d2 100644
--- a/src/soc/mediatek/mt8189/Makefile.mk
+++ b/src/soc/mediatek/mt8189/Makefile.mk
@@ -17,6 +17,7 @@ bootblock-y += ../common/mtcmos.c mtcmos.c
 bootblock-y += ../common/wdt.c ../common/wdt_req.c wdt.c
 
 romstage-y += ../common/cbmem.c
+romstage-y += clkbuf_ctl.c
 romstage-y += ../common/cpu_id.c ../common/cpu_segment_id.c
 romstage-y += ../common/dram_init.c
 romstage-y += ../common/dramc_param.c
@@ -32,6 +33,7 @@ romstage-y += ../common/pmif.c ../common/pmif_clk.c ../common/pmif_init.c pmif_c
 romstage-y += ../common/pmif_spi.c pmif_spi.c
 romstage-y += ../common/pmif_spmi.c ../common/pmif_spmi_v2.c pmif_spmi.c
 romstage-y += ../common/rtc.c ../common/rtc_osc_init.c ../common/rtc_mt6359p.c
+romstage-y += ../common/srclken_rc.c srclken_rc.c
 
 ramstage-y += ../common/auxadc.c
 ramstage-$(CONFIG_ARM64_USE_ARM_TRUSTED_FIRMWARE) += ../common/bl31.c
diff --git a/src/soc/mediatek/mt8189/clkbuf_ctl.c b/src/soc/mediatek/mt8189/clkbuf_ctl.c
new file mode 100644
index 0000000000..c979e1a8fc
--- /dev/null
+++ b/src/soc/mediatek/mt8189/clkbuf_ctl.c
@@ -0,0 +1,218 @@
+/* SPDX-License-Identifier: GPL-2.0-only OR MIT */
+
+#include <console/console.h>
+#include <delay.h>
+#include <soc/clkbuf_ctl.h>
+#include <soc/mt6359p.h>
+#include <soc/srclken_rc.h>
+
+#define PMIC_REG_MASK			0xFFFF
+#define PMIC_REG_SHIFT			0
+
+#define DCXO_DBG_AUXOUT_1		54
+#define DCXO_DBG_AUXOUT_2		55
+#define DCXO_DBG_AUXOUT_3		56
+
+#define PMIC_CW00_INIT_VAL		0x4F1D
+#define PMIC_CW09_INIT_VAL		0x31F0
+#define XO_SOC_VOTER_MASK		0x001
+#define XO_CONN_VOTER_MASK		0x7C0
+#define XO_NFC_VOTER_MASK		0x001
+#define XO_EXT_VOTER_MASK		0x001
+#define XO_CDAC_FPM_VAL			0xA8
+#define XO_CDAC_LPM_VAL			0xFF
+
+static void clk_buf_dump_clkbuf_log(void)
+{
+	u32 pmic_cw00, pmic_cw09, pmic_cw12, pmic_cw13,
+	    pmic_cw15, pmic_cw19, top_spi_con1,
+	    ldo_vrfck_op_en, ldo_vbbck_op_en, ldo_vrfck_en,
+	    ldo_vbbck_en, vrfck_hv_en;
+
+	pmic_cw00 = mt6359p_read_field(PMIC_XO_EXTBUF1_MODE_ADDR,
+				       PMIC_REG_MASK, PMIC_REG_SHIFT);
+	pmic_cw09 = mt6359p_read_field(PMIC_XO_EXTBUF7_MODE_ADDR,
+				       PMIC_REG_MASK, PMIC_REG_SHIFT);
+	pmic_cw12 = mt6359p_read_field(PMIC_XO_EXTBUF2_CLKSEL_MAN_ADDR,
+				       PMIC_REG_MASK, PMIC_REG_SHIFT);
+	pmic_cw13 = mt6359p_read_field(PMIC_RG_XO_EXTBUF2_SRSEL_ADDR,
+				       PMIC_REG_MASK, PMIC_REG_SHIFT);
+	pmic_cw15 = mt6359p_read_field(PMIC_RG_XO_RESERVED1_ADDR,
+				       PMIC_REG_MASK, PMIC_REG_SHIFT);
+	pmic_cw19 = mt6359p_read_field(PMIC_RG_XO_EXTBUF2_RSEL_ADDR,
+				       PMIC_REG_MASK, PMIC_REG_SHIFT);
+	top_spi_con1 = mt6359p_read_field(PMIC_RG_SRCLKEN_IN3_EN_ADDR,
+					  PMIC_RG_SRCLKEN_IN3_EN_MASK,
+					  PMIC_RG_SRCLKEN_IN3_EN_SHIFT);
+	ldo_vrfck_op_en = mt6359p_read_field(PMIC_RG_LDO_VRFCK_HW14_OP_EN_ADDR,
+					     PMIC_RG_LDO_VRFCK_HW14_OP_EN_MASK,
+					     PMIC_RG_LDO_VRFCK_HW14_OP_EN_SHIFT);
+	ldo_vbbck_op_en = mt6359p_read_field(PMIC_RG_LDO_VBBCK_HW14_OP_EN_ADDR,
+					     PMIC_RG_LDO_VBBCK_HW14_OP_EN_MASK,
+					     PMIC_RG_LDO_VBBCK_HW14_OP_EN_SHIFT);
+	ldo_vrfck_en = mt6359p_read_field(PMIC_RG_LDO_VRFCK_EN_ADDR,
+					  PMIC_RG_LDO_VRFCK_EN_MASK,
+					  PMIC_RG_LDO_VRFCK_EN_SHIFT);
+	ldo_vbbck_en = mt6359p_read_field(PMIC_RG_LDO_VBBCK_EN_ADDR,
+					  PMIC_RG_LDO_VBBCK_EN_MASK,
+					  PMIC_RG_LDO_VBBCK_EN_SHIFT);
+	printk(BIOS_INFO, "%s DCXO_CW00/09/12/13/15/19=0x%x %x %x %x %x %x\n",
+	       __func__, pmic_cw00, pmic_cw09, pmic_cw12, pmic_cw13, pmic_cw15, pmic_cw19);
+	printk(BIOS_INFO, "%s spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/"
+	       "ldo_bb_en=0x%x %x %x %x %x\n", __func__, top_spi_con1,
+	       ldo_vrfck_op_en, ldo_vbbck_op_en, ldo_vrfck_en, ldo_vbbck_en);
+	vrfck_hv_en = mt6359p_read_field(PMIC_RG_VRFCK_HV_EN_ADDR,
+					 PMIC_RG_VRFCK_HV_EN_MASK,
+					 PMIC_RG_VRFCK_HV_EN_SHIFT);
+	printk(BIOS_INFO, "%s clk buf vrfck_hv_en=0x%x\n", __func__, vrfck_hv_en);
+}
+
+u32 clk_buf_get_pmrc_en(void)
+{
+	return mt6359p_read_field(PMIC_PMRC_EN_ADDR, PMIC_PMRC_EN_MASK, PMIC_PMRC_EN_SHIFT);
+}
+
+static void clk_buf_init_pmic_clkbuf(void)
+{
+	int pmic_cw04_l, pmic_cw04_h;
+
+	/* Dump registers before setting */
+	clk_buf_dump_clkbuf_log();
+
+	/* unlock pmic key */
+	mt6359p_write_field(PMIC_TMA_KEY_ADDR, 0x9CA6,
+			    PMIC_TMA_KEY_MASK, PMIC_TMA_KEY_SHIFT);
+
+	/* 1.1 set VRFCK input supply */
+	mt6359p_write_field(PMIC_RG_VRFCK_HV_EN_ADDR, 0x0,
+			    PMIC_RG_VRFCK_HV_EN_MASK, PMIC_RG_VRFCK_HV_EN_SHIFT);
+	/* 1.2.1 set VRFCK En = 0 */
+	mt6359p_write_field(PMIC_RG_LDO_VRFCK_EN_ADDR, 0x0,
+			    PMIC_RG_LDO_VRFCK_EN_MASK, PMIC_RG_LDO_VRFCK_EN_SHIFT);
+	/* 1.2.1 set VRFCK1 as power src */
+	mt6359p_write_field(PMIC_RG_LDO_VRFCK_ANA_SEL_ADDR, 0x1,
+			    PMIC_RG_LDO_VRFCK_ANA_SEL_MASK, PMIC_RG_LDO_VRFCK_ANA_SEL_SHIFT);
+	/* 1.2.2 switch LDO-RFCK to LDO-RFCK1 */
+	mt6359p_write_field(PMIC_RG_VRFCK_NDIS_EN_ADDR, 0x0,
+			    PMIC_RG_VRFCK_NDIS_EN_MASK, PMIC_RG_VRFCK_NDIS_EN_SHIFT);
+	mt6359p_write_field(PMIC_RG_VRFCK_1_NDIS_EN_ADDR, 0x1,
+			    PMIC_RG_VRFCK_1_NDIS_EN_MASK, PMIC_RG_VRFCK_1_NDIS_EN_SHIFT);
+	/* 1.2.3 Set VRFCK En = 1 */
+	mt6359p_write_field(PMIC_RG_LDO_VRFCK_EN_ADDR, 0x1,
+			    PMIC_RG_LDO_VRFCK_EN_MASK, PMIC_RG_LDO_VRFCK_EN_SHIFT);
+
+	/* 1.3 turn on LDO HW control from EXTBUFs */
+	mt6359p_write_field(PMIC_RG_LDO_VRFCK_OP_EN_SET_ADDR, 0x1,
+			    PMIC_RG_LDO_VRFCK_HW14_OP_EN_MASK,
+			    PMIC_RG_LDO_VRFCK_HW14_OP_EN_SHIFT);
+	mt6359p_write_field(PMIC_RG_LDO_VBBCK_OP_EN_SET_ADDR, 0x1,
+			    PMIC_RG_LDO_VBBCK_HW14_OP_EN_MASK,
+			    PMIC_RG_LDO_VBBCK_HW14_OP_EN_SHIFT);
+
+	/* 1.4 turn on LDO SW control */
+	mt6359p_write_field(PMIC_RG_LDO_VRFCK_EN_ADDR, 0x0,
+			    PMIC_RG_LDO_VRFCK_EN_MASK, PMIC_RG_LDO_VRFCK_EN_SHIFT);
+	mt6359p_write_field(PMIC_RG_LDO_VBBCK_EN_ADDR, 0x0,
+			    PMIC_RG_LDO_VBBCK_EN_MASK, PMIC_RG_LDO_VBBCK_EN_SHIFT);
+
+	/* lock pmic key */
+	mt6359p_write_field(PMIC_TMA_KEY_ADDR, 0,
+			    PMIC_TMA_KEY_MASK, PMIC_TMA_KEY_SHIFT);
+
+	/* Setup initial PMIC clock buffer setting */
+	/* 1.5 Buffer de-sense setting */
+	mt6359p_write_field(PMIC_RG_XO_EXTBUF2_SRSEL_ADDR, PMIC_CLK_BUF2_CONTROLS_FOR_DESENSE,
+			    PMIC_RG_XO_EXTBUF2_SRSEL_MASK, PMIC_RG_XO_EXTBUF2_SRSEL_SHIFT);
+	mt6359p_write_field(PMIC_RG_XO_EXTBUF3_HD_ADDR, PMIC_CLK_BUF3_CONTROLS_FOR_DESENSE,
+			    PMIC_RG_XO_EXTBUF3_HD_MASK, PMIC_RG_XO_EXTBUF3_HD_SHIFT);
+	mt6359p_write_field(PMIC_RG_XO_EXTBUF4_SRSEL_ADDR, PMIC_CLK_BUF4_CONTROLS_FOR_DESENSE,
+			    PMIC_RG_XO_EXTBUF4_SRSEL_MASK, PMIC_RG_XO_EXTBUF4_SRSEL_SHIFT);
+
+	/* 1.6 Buffer setting for trace impedance */
+	mt6359p_write_field(PMIC_RG_XO_EXTBUF1_RSEL_ADDR, PMIC_CLK_BUF1_OUTPUT_IMPEDANCE,
+			    PMIC_RG_XO_EXTBUF1_RSEL_MASK, PMIC_RG_XO_EXTBUF1_RSEL_SHIFT);
+	mt6359p_write_field(PMIC_RG_XO_EXTBUF2_RSEL_ADDR, PMIC_CLK_BUF2_OUTPUT_IMPEDANCE,
+			    PMIC_RG_XO_EXTBUF2_RSEL_MASK, PMIC_RG_XO_EXTBUF2_RSEL_SHIFT);
+	mt6359p_write_field(PMIC_RG_XO_EXTBUF3_RSEL_ADDR, PMIC_CLK_BUF3_OUTPUT_IMPEDANCE,
+			    PMIC_RG_XO_EXTBUF3_RSEL_MASK, PMIC_RG_XO_EXTBUF3_RSEL_SHIFT);
+	mt6359p_write_field(PMIC_RG_XO_EXTBUF4_RSEL_ADDR, PMIC_CLK_BUF4_OUTPUT_IMPEDANCE,
+			    PMIC_RG_XO_EXTBUF4_RSEL_MASK, PMIC_RG_XO_EXTBUF4_RSEL_SHIFT);
+	mt6359p_write_field(PMIC_RG_XO_EXTBUF7_RSEL_ADDR, PMIC_CLK_BUF7_OUTPUT_IMPEDANCE,
+			    PMIC_RG_XO_EXTBUF7_RSEL_MASK, PMIC_RG_XO_EXTBUF7_RSEL_SHIFT);
+
+	/* 1.7 26M enable control */
+	/* fully new co-clock mode */
+	/* All XO mode should set to 2'b01 */
+	mt6359p_write_field(PMIC_XO_EXTBUF1_MODE_ADDR, PMIC_CW00_INIT_VAL,
+			    PMIC_REG_MASK, PMIC_REG_SHIFT);
+	mt6359p_write_field(PMIC_XO_EXTBUF7_MODE_ADDR, PMIC_CW09_INIT_VAL,
+			    PMIC_REG_MASK, PMIC_REG_SHIFT);
+	/* update control mapping table */
+	mt6359p_write_field(PMIC_XO_SOC_VOTE_ADDR, XO_SOC_VOTER_MASK,
+			    PMIC_XO_SOC_VOTE_MASK, PMIC_XO_SOC_VOTE_SHIFT);
+	mt6359p_write_field(PMIC_XO_WCN_VOTE_ADDR, XO_CONN_VOTER_MASK,
+			    PMIC_XO_WCN_VOTE_MASK, PMIC_XO_WCN_VOTE_SHIFT);
+	mt6359p_write_field(PMIC_XO_NFC_VOTE_ADDR, XO_NFC_VOTER_MASK,
+			    PMIC_XO_NFC_VOTE_MASK, PMIC_XO_NFC_VOTE_SHIFT);
+	mt6359p_write_field(PMIC_XO_CEL_VOTE_ADDR, XO_CONN_VOTER_MASK,
+			    PMIC_XO_CEL_VOTE_MASK, PMIC_XO_CEL_VOTE_SHIFT);
+	mt6359p_write_field(PMIC_XO_EXT_VOTE_ADDR, XO_EXT_VOTER_MASK,
+			    PMIC_XO_EXT_VOTE_MASK, PMIC_XO_EXT_VOTE_SHIFT);
+	mdelay(1);
+
+	/* switch to new control mode */
+	/*
+	 * XO_PMIC_TOP_DIG_SW is set to 0
+	 * XO_MODE_CONN_BT_MASK is set to 0 (BT only : 1)
+	 * XO_BUF_CONN_BT_MASK is set to 0 (BT only : 1 )
+	 */
+	mt6359p_write_field(PMIC_XO_PMIC_TOP_DIG_SW_ADDR, 0x0,
+			    PMIC_XO_PMIC_TOP_DIG_SW_MASK, PMIC_XO_PMIC_TOP_DIG_SW_SHIFT);
+	mt6359p_write_field(PMIC_XO_MODE_CONN_BT_MASK_ADDR, 0x0,
+			    PMIC_XO_MODE_CONN_BT_MASK_MASK, PMIC_XO_MODE_CONN_BT_MASK_SHIFT);
+	mt6359p_write_field(PMIC_XO_BUF_CONN_BT_MASK_ADDR, 0x0,
+			    PMIC_XO_BUF_CONN_BT_MASK_MASK, PMIC_XO_BUF_CONN_BT_MASK_SHIFT);
+
+	/* set capid */
+	mt6359p_write_field(PMIC_XO_CDAC_FPM_ADDR, XO_CDAC_FPM_VAL,
+			    PMIC_XO_CDAC_FPM_MASK, PMIC_XO_CDAC_FPM_SHIFT);
+	mt6359p_write_field(PMIC_XO_CDAC_LPM_ADDR, XO_CDAC_LPM_VAL,
+			    PMIC_XO_CDAC_LPM_MASK, PMIC_XO_CDAC_LPM_SHIFT);
+
+	pmic_cw04_l = mt6359p_read_field(PMIC_XO_CDAC_FPM_ADDR,
+				       PMIC_XO_CDAC_FPM_MASK, PMIC_XO_CDAC_FPM_SHIFT);
+	pmic_cw04_h = mt6359p_read_field(PMIC_XO_CDAC_LPM_ADDR,
+				       PMIC_XO_CDAC_LPM_MASK, PMIC_XO_CDAC_LPM_SHIFT);
+	printk(BIOS_INFO,
+	       "%s clk buf pmic_cw04_l=0x%x, pmic_cw04_h=0x%x\n",
+	       __func__, pmic_cw04_l, pmic_cw04_h);
+
+	/* Check if the setting is ok */
+	clk_buf_dump_clkbuf_log();
+}
+
+/* For CONN DBG */
+static void dcxo_dump_auxout(u16 sel)
+{
+	u32 rg_auxout;
+
+	mt6359p_write_field(PMIC_XO_STATIC_AUXOUT_SEL_ADDR, sel,
+			    PMIC_XO_STATIC_AUXOUT_SEL_MASK,
+			    PMIC_XO_STATIC_AUXOUT_SEL_SHIFT);
+	rg_auxout = mt6359p_read_field(PMIC_XO_STATIC_AUXOUT_ADDR,
+				       PMIC_XO_STATIC_AUXOUT_MASK,
+				       PMIC_XO_STATIC_AUXOUT_SHIFT);
+	printk(BIOS_INFO, "%s: sel=%d, rg_auxout=0x%x\n", __func__, sel, rg_auxout);
+}
+
+int clk_buf_init(void)
+{
+	/* dump lpsd dbg1-3 for debug */
+	dcxo_dump_auxout(DCXO_DBG_AUXOUT_1);
+	dcxo_dump_auxout(DCXO_DBG_AUXOUT_2);
+	dcxo_dump_auxout(DCXO_DBG_AUXOUT_3);
+
+	clk_buf_init_pmic_clkbuf();
+
+	return 0;
+}
diff --git a/src/soc/mediatek/mt8189/include/soc/addressmap.h b/src/soc/mediatek/mt8189/include/soc/addressmap.h
index fed77162e8..8c633c5f17 100644
--- a/src/soc/mediatek/mt8189/include/soc/addressmap.h
+++ b/src/soc/mediatek/mt8189/include/soc/addressmap.h
@@ -132,6 +132,7 @@ enum {
 	SPM_BASE			= IO_PHYS + 0x0C001000,
 	RGU_BASE			= IO_PHYS + 0x0C00A000,
 	VLPCFG_REG_BASE			= IO_PHYS + 0x0C00C000,
+	RC_BASE				= IO_PHYS + 0x0C00D000,
 	DVFSRC_TOP_BASE			= IO_PHYS + 0x0C00F000,
 	VLP_CK_BASE			= IO_PHYS + 0x0C012000,
 	PMICSPI_MST_BASE		= IO_PHYS + 0x0C013000,
diff --git a/src/soc/mediatek/mt8189/include/soc/clkbuf_ctl.h b/src/soc/mediatek/mt8189/include/soc/clkbuf_ctl.h
new file mode 100644
index 0000000000..decc94c5e0
--- /dev/null
+++ b/src/soc/mediatek/mt8189/include/soc/clkbuf_ctl.h
@@ -0,0 +1,207 @@
+/* SPDX-License-Identifier: GPL-2.0-only OR MIT */
+
+#ifndef __SOC_MEDIATEK_MT8189_INCLUDE_SOC_CLK_BUF_CTL_H__
+#define __SOC_MEDIATEK_MT8189_INCLUDE_SOC_CLK_BUF_CTL_H__
+
+#define MT6359_PMRC_CON0				0x1A6
+#define MT6359_TOP_TMA_KEY				0x3A8
+#define MT6359_TOP_SPI_CON1				0x458
+#define MT6359_XO_BUF_CTL0				0x54C
+#define MT6359_XO_BUF_CTL1				0x54E
+#define MT6359_XO_BUF_CTL2				0x550
+#define MT6359_XO_BUF_CTL3				0x552
+#define MT6359_XO_BUF_CTL4				0x554
+#define MT6359_XO_CONN_BT0				0x556
+#define MT6359_DCXO_CW00				0x788
+#define MT6359_DCXO_CW00_SET				0x78A
+#define MT6359_DCXO_CW00_CLR				0x78C
+#define MT6359_DCXO_CW01				0x78E
+#define MT6359_DCXO_CW02				0x790
+#define MT6359_DCXO_CW03				0x792
+#define MT6359_DCXO_CW04				0x794
+#define MT6359_DCXO_CW05				0x796
+#define MT6359_DCXO_CW06				0x798
+#define MT6359_DCXO_CW07				0x79A
+#define MT6359_DCXO_CW08				0x79C
+#define MT6359_DCXO_CW09				0x79E
+#define MT6359_DCXO_CW09_SET				0x7A0
+#define MT6359_DCXO_CW09_CLR				0x7A2
+#define MT6359_DCXO_CW10				0x7A4
+#define MT6359_DCXO_CW11				0x7A6
+#define MT6359_DCXO_CW12				0x7A8
+#define MT6359_DCXO_CW13				0x7AA
+#define MT6359_DCXO_CW14				0x7AC
+#define MT6359_DCXO_CW15				0x7AE
+#define MT6359_DCXO_CW16				0x7B0
+#define MT6359_DCXO_CW17				0x7B2
+#define MT6359_DCXO_CW18				0x7B4
+#define MT6359_DCXO_CW19				0x7B6
+#define MT6359_LDO_VRFCK_ELR				0x1B40
+#define MT6359_LDO_VRFCK_CON0				0x1D1C
+#define MT6359_LDO_VRFCK_OP_EN				0x1D22
+#define MT6359_LDO_VRFCK_OP_EN_SET			0x1D24
+#define MT6359_LDO_VBBCK_CON0				0x1D2E
+#define MT6359_LDO_VBBCK_OP_EN				0x1D34
+#define MT6359_LDO_VBBCK_OP_EN_SET			0x1D36
+#define MT6359_DCXO_ADLDO_BIAS_ELR_0			0x209C
+#define MT6359_DCXO_ADLDO_BIAS_ELR_1			0x209E
+#define PMIC_RG_SRCLKEN_IN3_EN_ADDR			MT6359_TOP_SPI_CON1
+#define PMIC_RG_SRCLKEN_IN3_EN_MASK			0x1
+#define PMIC_RG_SRCLKEN_IN3_EN_SHIFT			0
+#define PMIC_RG_LDO_VBBCK_HW14_OP_EN_ADDR		MT6359_LDO_VBBCK_OP_EN
+#define PMIC_RG_LDO_VBBCK_HW14_OP_EN_MASK		0x1
+#define PMIC_RG_LDO_VBBCK_HW14_OP_EN_SHIFT		14
+#define PMIC_RG_LDO_VRFCK_HW14_OP_EN_ADDR		MT6359_LDO_VRFCK_OP_EN
+#define PMIC_RG_LDO_VRFCK_HW14_OP_EN_MASK		0x1
+#define PMIC_RG_LDO_VRFCK_HW14_OP_EN_SHIFT		14
+#define PMIC_RG_LDO_VRFCK_EN_ADDR			MT6359_LDO_VRFCK_CON0
+#define PMIC_RG_LDO_VRFCK_EN_MASK			0x1
+#define PMIC_RG_LDO_VRFCK_EN_SHIFT			0
+#define PMIC_RG_LDO_VBBCK_EN_ADDR			MT6359_LDO_VBBCK_CON0
+#define PMIC_RG_LDO_VBBCK_EN_MASK			0x1
+#define PMIC_RG_LDO_VBBCK_EN_SHIFT			0
+#define PMIC_RG_VRFCK_HV_EN_ADDR			MT6359_DCXO_ADLDO_BIAS_ELR_0
+#define PMIC_RG_VRFCK_HV_EN_MASK			0x1
+#define PMIC_RG_VRFCK_HV_EN_SHIFT			9
+#define PMIC_PMRC_EN_ADDR				MT6359_PMRC_CON0
+#define PMIC_PMRC_EN_MASK				0xFFFF
+#define PMIC_PMRC_EN_SHIFT				0
+#define PMIC_TMA_KEY_ADDR				MT6359_TOP_TMA_KEY
+#define PMIC_TMA_KEY_MASK				0xFFFF
+#define PMIC_TMA_KEY_SHIFT				0
+#define PMIC_RG_LDO_VRFCK_ANA_SEL_ADDR			MT6359_LDO_VRFCK_ELR
+#define PMIC_RG_LDO_VRFCK_ANA_SEL_MASK			0x1
+#define PMIC_RG_LDO_VRFCK_ANA_SEL_SHIFT			0
+#define PMIC_RG_VRFCK_NDIS_EN_ADDR			MT6359_DCXO_ADLDO_BIAS_ELR_0
+#define PMIC_RG_VRFCK_NDIS_EN_MASK			0x1
+#define PMIC_RG_VRFCK_NDIS_EN_SHIFT			11
+#define PMIC_RG_LDO_VRFCK_OP_EN_SET_ADDR		MT6359_LDO_VRFCK_OP_EN_SET
+#define PMIC_RG_LDO_VBBCK_OP_EN_SET_ADDR		MT6359_LDO_VBBCK_OP_EN_SET
+#define PMIC_XO_EXTBUF1_MODE_ADDR			MT6359_DCXO_CW00
+#define PMIC_XO_EXTBUF2_MODE_MASK			0x3
+#define PMIC_XO_EXTBUF2_MODE_SHIFT			3
+#define PMIC_XO_EXTBUF2_EN_M_MASK			0x1
+#define PMIC_XO_EXTBUF2_EN_M_SHIFT			5
+#define PMIC_XO_EXTBUF4_MODE_MASK			0x3
+#define PMIC_XO_EXTBUF4_MODE_SHIFT			9
+#define PMIC_XO_EXTBUF4_EN_M_MASK			0x1
+#define PMIC_XO_EXTBUF4_EN_M_SHIFT			11
+#define PMIC_DCXO_CW00_CLR_ADDR				MT6359_DCXO_CW00_CLR
+#define PMIC_XO_CLKSEL_EN_M_ADDR			MT6359_DCXO_CW01
+
+#define PMIC_XO_CDAC_FPM_ADDR                           MT6359_DCXO_CW04
+#define PMIC_XO_CDAC_FPM_MASK                           0xFF
+#define PMIC_XO_CDAC_FPM_SHIFT                          0
+#define PMIC_XO_CDAC_LPM_ADDR                           MT6359_DCXO_CW04
+#define PMIC_XO_CDAC_LPM_MASK                           0xFF
+#define PMIC_XO_CDAC_LPM_SHIFT                          8
+
+#define PMIC_XO_PMIC_TOP_DIG_SW_ADDR			MT6359_DCXO_CW08
+#define PMIC_XO_PMIC_TOP_DIG_SW_MASK			0x1
+#define PMIC_XO_PMIC_TOP_DIG_SW_SHIFT			2
+#define PMIC_XO_EXTBUF7_MODE_ADDR			MT6359_DCXO_CW09
+#define PMIC_XO_EXTBUF2_CLKSEL_MAN_ADDR			MT6359_DCXO_CW12
+#define PMIC_XO_EXTBUF2_CLKSEL_MAN_MASK			0x1
+#define PMIC_XO_EXTBUF2_CLKSEL_MAN_SHIFT		12
+#define PMIC_RG_XO_EXTBUF2_SRSEL_ADDR			MT6359_DCXO_CW13
+#define PMIC_RG_XO_EXTBUF2_SRSEL_MASK			0x7
+#define PMIC_RG_XO_EXTBUF2_SRSEL_SHIFT			0
+#define PMIC_RG_XO_EXTBUF4_SRSEL_ADDR			MT6359_DCXO_CW13
+#define PMIC_RG_XO_EXTBUF4_SRSEL_MASK			0x7
+#define PMIC_RG_XO_EXTBUF4_SRSEL_SHIFT			4
+#define PMIC_RG_XO_EXTBUF3_HD_ADDR			MT6359_DCXO_CW13
+#define PMIC_RG_XO_EXTBUF3_HD_MASK			0x3
+#define PMIC_RG_XO_EXTBUF3_HD_SHIFT			10
+#define PMIC_RG_XO_RESERVED1_ADDR			MT6359_DCXO_CW15
+#define PMIC_XO_STATIC_AUXOUT_SEL_ADDR			MT6359_DCXO_CW16
+#define PMIC_XO_STATIC_AUXOUT_SEL_MASK			0x3F
+#define PMIC_XO_STATIC_AUXOUT_SEL_SHIFT			0
+#define PMIC_XO_STATIC_AUXOUT_ADDR			MT6359_DCXO_CW17
+#define PMIC_XO_STATIC_AUXOUT_MASK			0xFFFF
+#define PMIC_XO_STATIC_AUXOUT_SHIFT			0
+#define PMIC_RG_XO_EXTBUF1_RSEL_ADDR			MT6359_DCXO_CW19
+#define PMIC_RG_XO_EXTBUF1_RSEL_MASK			0x7
+#define PMIC_RG_XO_EXTBUF1_RSEL_SHIFT			1
+#define PMIC_RG_XO_EXTBUF2_RSEL_ADDR			MT6359_DCXO_CW19
+#define PMIC_RG_XO_EXTBUF2_RSEL_MASK			0x7
+#define PMIC_RG_XO_EXTBUF2_RSEL_SHIFT			4
+#define PMIC_RG_XO_EXTBUF3_RSEL_ADDR			MT6359_DCXO_CW19
+#define PMIC_RG_XO_EXTBUF3_RSEL_MASK			0x7
+#define PMIC_RG_XO_EXTBUF3_RSEL_SHIFT			7
+#define PMIC_RG_XO_EXTBUF4_RSEL_ADDR			MT6359_DCXO_CW19
+#define PMIC_RG_XO_EXTBUF4_RSEL_MASK			0x7
+#define PMIC_RG_XO_EXTBUF4_RSEL_SHIFT			10
+#define PMIC_RG_XO_EXTBUF7_RSEL_ADDR			MT6359_DCXO_CW19
+#define PMIC_RG_XO_EXTBUF7_RSEL_MASK			0x7
+#define PMIC_RG_XO_EXTBUF7_RSEL_SHIFT			13
+#define PMIC_RG_VRFCK_1_NDIS_EN_ADDR			MT6359_DCXO_ADLDO_BIAS_ELR_1
+#define PMIC_RG_VRFCK_1_NDIS_EN_MASK			0x1
+#define PMIC_RG_VRFCK_1_NDIS_EN_SHIFT			0
+#define PMIC_XO_SOC_VOTE_ADDR				MT6359_XO_BUF_CTL0
+#define PMIC_XO_SOC_VOTE_MASK				0x7FF
+#define PMIC_XO_SOC_VOTE_SHIFT				0
+#define PMIC_XO_WCN_VOTE_ADDR				MT6359_XO_BUF_CTL1
+#define PMIC_XO_WCN_VOTE_MASK				0x7FF
+#define PMIC_XO_WCN_VOTE_SHIFT				0
+#define PMIC_XO_NFC_VOTE_ADDR				MT6359_XO_BUF_CTL2
+#define PMIC_XO_NFC_VOTE_MASK				0x7FF
+#define PMIC_XO_NFC_VOTE_SHIFT				0
+#define PMIC_XO_CEL_VOTE_ADDR				MT6359_XO_BUF_CTL3
+#define PMIC_XO_CEL_VOTE_MASK				0x7FF
+#define PMIC_XO_CEL_VOTE_SHIFT				0
+#define PMIC_XO_EXT_VOTE_ADDR				MT6359_XO_BUF_CTL4
+#define PMIC_XO_EXT_VOTE_MASK				0x7FF
+#define PMIC_XO_EXT_VOTE_SHIFT				0
+#define PMIC_XO_MODE_CONN_BT_MASK_ADDR			MT6359_XO_CONN_BT0
+#define PMIC_XO_MODE_CONN_BT_MASK_MASK			0x1
+#define PMIC_XO_MODE_CONN_BT_MASK_SHIFT			0
+#define PMIC_XO_BUF_CONN_BT_MASK_ADDR			MT6359_XO_CONN_BT0
+#define PMIC_XO_BUF_CONN_BT_MASK_MASK			0x1
+#define PMIC_XO_BUF_CONN_BT_MASK_SHIFT			1
+
+enum {
+	CLOCK_BUFFER_DISABLE,
+	CLOCK_BUFFER_SW_CONTROL,
+	CLOCK_BUFFER_HW_CONTROL
+};
+
+enum {
+	CLK_BUF_OUTPUT_IMPEDANCE_0,
+	CLK_BUF_OUTPUT_IMPEDANCE_1,
+	CLK_BUF_OUTPUT_IMPEDANCE_2,
+	CLK_BUF_OUTPUT_IMPEDANCE_3,
+	CLK_BUF_OUTPUT_IMPEDANCE_4,
+	CLK_BUF_OUTPUT_IMPEDANCE_5,
+	CLK_BUF_OUTPUT_IMPEDANCE_6,
+	CLK_BUF_OUTPUT_IMPEDANCE_7,
+};
+
+enum {
+	CLK_BUF_CONTROLS_FOR_DESENSE_0,
+	CLK_BUF_CONTROLS_FOR_DESENSE_1,
+	CLK_BUF_CONTROLS_FOR_DESENSE_2,
+	CLK_BUF_CONTROLS_FOR_DESENSE_3,
+	CLK_BUF_CONTROLS_FOR_DESENSE_4,
+	CLK_BUF_CONTROLS_FOR_DESENSE_5,
+	CLK_BUF_CONTROLS_FOR_DESENSE_6,
+	CLK_BUF_CONTROLS_FOR_DESENSE_7,
+};
+
+#define CLK_BUF1_STATUS_PMIC			CLOCK_BUFFER_HW_CONTROL
+#define CLK_BUF2_STATUS_PMIC			CLOCK_BUFFER_HW_CONTROL
+#define CLK_BUF3_STATUS_PMIC			CLOCK_BUFFER_HW_CONTROL
+#define CLK_BUF4_STATUS_PMIC			CLOCK_BUFFER_HW_CONTROL
+#define CLK_BUF7_STATUS_PMIC			CLOCK_BUFFER_HW_CONTROL
+#define PMIC_CLK_BUF1_OUTPUT_IMPEDANCE		CLK_BUF_OUTPUT_IMPEDANCE_6
+#define PMIC_CLK_BUF2_OUTPUT_IMPEDANCE		CLK_BUF_OUTPUT_IMPEDANCE_4
+#define PMIC_CLK_BUF3_OUTPUT_IMPEDANCE		CLK_BUF_OUTPUT_IMPEDANCE_4
+#define PMIC_CLK_BUF4_OUTPUT_IMPEDANCE		CLK_BUF_OUTPUT_IMPEDANCE_4
+#define PMIC_CLK_BUF7_OUTPUT_IMPEDANCE		CLK_BUF_OUTPUT_IMPEDANCE_4
+#define PMIC_CLK_BUF2_CONTROLS_FOR_DESENSE	CLK_BUF_CONTROLS_FOR_DESENSE_4
+#define PMIC_CLK_BUF3_CONTROLS_FOR_DESENSE	CLK_BUF_CONTROLS_FOR_DESENSE_0
+#define PMIC_CLK_BUF4_CONTROLS_FOR_DESENSE	CLK_BUF_CONTROLS_FOR_DESENSE_4
+
+int clk_buf_init(void);
+u32 clk_buf_get_pmrc_en(void);
+
+#endif
diff --git a/src/soc/mediatek/mt8189/include/soc/srclken_rc.h b/src/soc/mediatek/mt8189/include/soc/srclken_rc.h
new file mode 100644
index 0000000000..4fe262aa7a
--- /dev/null
+++ b/src/soc/mediatek/mt8189/include/soc/srclken_rc.h
@@ -0,0 +1,156 @@
+/* SPDX-License-Identifier: GPL-2.0-only OR MIT */
+
+#ifndef __SOC_MEDIATEK_MT8189_INCLUDE_SOC_SRCLKEN_RC_H__
+#define __SOC_MEDIATEK_MT8189_INCLUDE_SOC_SRCLKEN_RC_H__
+
+#include <device/mmio.h>
+#include <soc/addressmap.h>
+#include <soc/srclken_rc_common.h>
+
+enum chn_id {
+	CHN_SUSPEND = 0,
+	CHN_MD0,
+	CHN_MD1,
+	CHN_MD2,
+	CHN_MDRF,
+	CHN_MMWAVE = 5,
+	CHN_GPS,
+	CHN_BT,
+	CHN_WF,
+	CHN_CONN_MCU,
+	CHN_COANT = 10,
+	CHN_NFC,
+	CHN_SUSPEND2,
+	CHN_UFS,
+	MAX_CHN_NUM,
+};
+
+struct mtk_rc_regs {
+	u32 srclken_rc_cfg;
+	u32 rc_central_cfg1;
+	u32 rc_central_cfg2;
+	u32 rc_cmd_arb_cfg;
+	u32 rc_pmic_rcen_addr;
+	u32 rc_pmic_rcen_set_clr_addr;
+	u32 rc_dcxo_fpm_cfg;
+	u32 rc_central_cfg3;
+	u32 rc_mxx_srclken_cfg[MAX_CHN_NUM];
+	u32 srclken_sw_con_cfg;
+	u32 rc_central_cfg4;
+	u32 reserved1;
+	u32 rc_debug_cfg;
+	u32 reserved2;
+	u32 reserved3;
+	u32 rc_central_cfg5;
+	u32 rc_central_cfg6;
+	u32 rcen_mt_m_cfg_0;
+	u32 rcen_mt_m_cfg_1;
+	u32 rcen_mt_p_cfg_0;
+	u32 rcen_mt_p_cfg_1;
+	u32 rcen_mt_cfg_0;
+	u32 reserved4[12];
+	u32 subsys_intf_cfg;
+	u32 reserved5[19];
+	u32 rc_spi_sta_0;
+	u32 rc_pi_po_sta;
+	u32 rc_mxx_req_sta[MAX_CHN_NUM];
+};
+check_member(mtk_rc_regs, rc_spi_sta_0, 0x10C);
+
+DEFINE_BIT(SW_RESET, 0)
+DEFINE_BITFIELD(CG_32K_EN, 3, 1)
+DEFINE_BIT(CG_FCLK_EN, 2)
+DEFINE_BIT(CG_FCLK_FR_EN, 3)
+DEFINE_BIT(MUX_FCLK_FR, 4)
+DEFINE_BIT(RC_32K_DCM, 8)
+DEFINE_BIT(SRCLKEN_RC_EN, 0)
+DEFINE_BIT(RCEN_ISSUE_M, 1)
+DEFINE_BIT(RC_SPI_ACTIVE, 2)
+DEFINE_BIT(SRCLKEN_RC_EN_SEL, 3)
+DEFINE_BITFIELD(VCORE_SETTLE_T, 7, 5)
+DEFINE_BITFIELD(ULPOSC_SETTLE_T, 11, 8)
+DEFINE_BITFIELD(NON_DCXO_SETTLE_T, 21, 12)
+DEFINE_BITFIELD(DCXO_SETTLE_T, 31, 22)
+DEFINE_BITFIELD(SRCVOLTEN_CTRL, 3, 0)
+DEFINE_BITFIELD(VREQ_CTRL, 7, 4)
+DEFINE_BIT(SRCVOLTEN_VREQ_SEL, 8)
+DEFINE_BIT(SRCVOLTEN_VREQ_M, 9)
+DEFINE_BIT(FORCE_SRCVOLTEN_OFF, 10)
+DEFINE_BIT(FORCE_SRCVOLTEN_ON, 11)
+DEFINE_BITFIELD(ULPOSC_CTRL_M, 15, 12)
+DEFINE_BIT(FORCE_VCORE_RDY, 16)
+DEFINE_BIT(FORCE_ULPOSC2ON, 17)
+DEFINE_BIT(FORCE_ULPOSC_CLK_EN, 18)
+DEFINE_BIT(FORCE_ULPOSC_ON, 19)
+DEFINE_BIT(DIS_ULPOSC_RDY_CHK, 20)
+DEFINE_BIT(PWRAP_SLP_CTRL_M, 21)
+DEFINE_BIT(PWRAP_SLP_MUX_SEL, 25)
+DEFINE_BIT(FORCE_PWRAP_ON, 26)
+DEFINE_BIT(FORCE_PWRAP_AWK, 27)
+DEFINE_BIT(NON_DCXO_REQ_FORCEON, 28)
+DEFINE_BIT(NON_DCXO_REQ_FORCEOFF, 29)
+DEFINE_BIT(DCXO_REQ_FORCEON, 30)
+DEFINE_BIT(DCXO_REQ_FORCEOFF, 31)
+DEFINE_BITFIELD(SW_RC_EN, 12, 0)
+DEFINE_BITFIELD(SW_RCEN_EN, 25, 13)
+DEFINE_BIT(SW_DCXO_M_EN, 28)
+DEFINE_BITFIELD(SW_DCXO_M, 31, 29)
+DEFINE_BITFIELD(DCXO_FPM_CTRL_M, 3, 0)
+DEFINE_BIT(SRCVOLTEN_FPM_MSK_B, 4)
+DEFINE_BITFIELD(SUB_SRCLKEN_FPM_MSK_B, 28, 16)
+DEFINE_BIT(TO_LPM_SETTLE_EN, 0)
+DEFINE_BIT(BLK_SCP_DXCO_MD_TARGET, 1)
+DEFINE_BIT(BLK_COANT_DXCO_MD_TARGET, 2)
+DEFINE_BIT(TO_BBLPM_SETTLE_EN, 3)
+DEFINE_BIT(TO_BBLPM_SETTLE_ND_EN, 4)
+DEFINE_BITFIELD(TO_LPM_SETTLE_T, 21, 12)
+DEFINE_BIT(DCXO_SETTLE_BLK_EN, 1)
+DEFINE_BIT(BYPASS_CMD_EN, 2)
+DEFINE_BIT(SW_SRCLKEN_RC, 3)
+DEFINE_BIT(SW_SRCLKEN_FPM, 4)
+DEFINE_BIT(SW_SRCLKEN_BBLPM, 5)
+DEFINE_BIT(XO_SOC_LINKAGE_EN, 6)
+DEFINE_BIT(REQ_ACK_LOW_IMD_EN, 7)
+DEFINE_BIT(SRCLKEN_TRACK_M_EN, 8)
+DEFINE_BITFIELD(CNT_PRD_STEP, 11, 10)
+DEFINE_BITFIELD(XO_STABLE_PRD, 21, 12)
+DEFINE_BITFIELD(DCXO_STABLE_PRD, 31, 22)
+DEFINE_BIT(TACE_EN, 0)
+DEFINE_BITFIELD(TIE_SYS_RDY, 4, 1)
+DEFINE_BITFIELD(KEEP_RC_SPI_ACTIVE, 12, 0)
+DEFINE_BIT(PWRAP_VLD_FORCE, 16)
+DEFINE_BIT(SLEEP_VLD_MODE, 17)
+DEFINE_BIT(SCP_SLEEP_REQ_MODE, 18)
+DEFINE_BIT(SLEEP_REQ_MODE, 20)
+DEFINE_BIT(BYPASS_PMIF_M, 24)
+DEFINE_BIT(BYPASS_PMIF_P, 25)
+DEFINE_BIT(TRACE_MODE_EN, 24)
+DEFINE_BIT(DBG_STOP_PROT_EN, 28)
+DEFINE_BIT(SPMI_CMD_BYTE_CNT, 0)
+DEFINE_BITFIELD(SPMI_M_SLV_ID, 8, 5)
+DEFINE_BITFIELD(SPMI_P_SLV_ID, 12, 9)
+DEFINE_BIT(SPMI_M_PMIF_ID, 17)
+DEFINE_BIT(SPMI_P_PMIF_ID, 18)
+DEFINE_BITFIELD(SPMI_M_CMD_TYPE, 21, 19)
+DEFINE_BITFIELD(SPMI_P_CMD_TYPE, 22, 21)
+DEFINE_BIT(SPMI_M_WRITE_EN, 23)
+DEFINE_BIT(SPMI_P_WRITE_EN, 24)
+DEFINE_BIT(BROADCAST_MODE_EN, 25)
+DEFINE_BIT(MULTI_CMD_MODE_EN, 26)
+DEFINE_BIT(DCXO_ENCODE, 27)
+DEFINE_BIT(SPMI_M_FIRST, 28)
+DEFINE_BIT(SPMI_BYTE_NUM, 29)
+DEFINE_BITFIELD(REQ_TO_DCXO_MASK, 15, 0)
+DEFINE_BITFIELD(REQ_TO_SPMI_P_MASK_B, 31, 16)
+DEFINE_BITFIELD(PMIC_M_COUNTER_VAL, 3, 0)
+DEFINE_BITFIELD(PMIC_P_COUNTER_VAL, 7, 4)
+DEFINE_BITFIELD(SRCLKEN_FPM_MASK_B, 13, 0)
+DEFINE_BITFIELD(SRCLKEN_BBLPM_MASK_B, 29, 16)
+DEFINE_BIT(FPM_ACK, 1)
+DEFINE_BIT(BBLPM_ACK, 3)
+DEFINE_BITFIELD(BYPASS_DCXO_VOTE_H, 31, 16)
+DEFINE_BITFIELD(BYPASS_DCXO_VOTE_L, 15, 0)
+
+static struct mtk_rc_regs *const rc_regs = (void *)RC_BASE;
+
+#endif
diff --git a/src/soc/mediatek/mt8189/srclken_rc.c b/src/soc/mediatek/mt8189/srclken_rc.c
new file mode 100644
index 0000000000..c77b6d6d59
--- /dev/null
+++ b/src/soc/mediatek/mt8189/srclken_rc.c
@@ -0,0 +1,281 @@
+/* SPDX-License-Identifier: GPL-2.0-only OR MIT */
+
+#include <console/console.h>
+#include <delay.h>
+#include <device/mmio.h>
+#include <soc/clkbuf_ctl.h>
+#include <soc/srclken_rc.h>
+
+#define XO_MD2_STABLE_TIME		0x80	/* ~= 1260us */
+
+/* merge with spm */
+#define SRCLKENO_0_CTRL_M		MERGE_OR_MODE
+
+/* pmrc_en address */
+/* default use this reg direct write */
+#define PMRC_CON0			0x1A6
+#define PMRC_CON0_SET			0x1A8
+#define PMRC_CON0_CLR			0x1AA
+
+/* SUBSYS_INTF_CFG */
+#define SUB_BBLPM_SET		(1 << CHN_COANT)
+#define SUB_FPM_SET		(1 << CHN_SUSPEND | 1 << CHN_MD0 | \
+				 1 << CHN_MD1 | 1 << CHN_MD2 | \
+				 1 << CHN_MDRF | 1 << CHN_MMWAVE | \
+				 1 << CHN_GPS | 1 << CHN_BT | \
+				 1 << CHN_WF | 1 << CHN_CONN_MCU | \
+				 1 << CHN_NFC | 1 << CHN_SUSPEND2 | \
+				 1 << CHN_UFS)
+
+/* CFG6, mask subsys XO/DCXO request */
+#define DCXO_MASK_SUBSYS	0
+#define REQ_TO_SPMI_P_SUBSYS	0
+
+/* First try to switch fpm. After polling ack done, switch to HW mode */
+const struct rc_config rc_config[MAX_CHN_NUM] = {
+	[CHN_SUSPEND] = { .hw_mode = true },
+	[CHN_MD0] = { .hw_mode = true },
+	[CHN_MD1] = { .hw_mode = true },
+	[CHN_MD2] = { .hw_mode = true },
+	[CHN_MDRF] = { .hw_mode = true },
+	[CHN_MMWAVE] = { .hw_mode = true },
+	[CHN_GPS] = { .lpm = true, .hw_mode = true },
+	[CHN_BT] = { .lpm = true, .hw_mode = true },
+	[CHN_WF] = { .lpm = true, .hw_mode = true },
+	[CHN_CONN_MCU] = { .lpm = true, .hw_mode = true },
+	[CHN_COANT] = { .lpm = true, .hw_mode = true },
+	[CHN_NFC] = { .lpm = true, .hw_mode = true },
+	[CHN_SUSPEND2] = { .hw_mode = true },
+	[CHN_UFS] = { .lpm = true, .hw_mode = true },
+};
+
+const size_t rc_config_num = ARRAY_SIZE(rc_config);
+
+static const struct subsys_rc_con rc_ctrl[MAX_CHN_NUM] = {
+	SUB_CTRL_CON_EN(CHN_SUSPEND, XO_DEFAULT_STABLE_TIME, REQ_ACK_IMD_EN),
+	SUB_CTRL_CON_EN(CHN_MD0, XO_MD0_STABLE_TIME, REQ_ACK_IMD_EN),
+	SUB_CTRL_CON_EN(CHN_MD1, XO_MD1_STABLE_TIME, REQ_ACK_IMD_EN),
+	SUB_CTRL_CON_EN(CHN_MD2, XO_MD2_STABLE_TIME, REQ_ACK_IMD_EN),
+	SUB_CTRL_CON_EN(CHN_MDRF, XO_MDRF_STABLE_TIME, REQ_ACK_IMD_EN),
+	SUB_CTRL_CON_EN(CHN_MMWAVE, XO_DEFAULT_STABLE_TIME, REQ_ACK_IMD_EN),
+	SUB_CTRL_CON_EN(CHN_GPS, XO_DEFAULT_STABLE_TIME, REQ_ACK_IMD_EN),
+	SUB_CTRL_CON_EN(CHN_BT, XO_DEFAULT_STABLE_TIME, REQ_ACK_IMD_EN),
+	SUB_CTRL_CON_EN(CHN_WF, XO_DEFAULT_STABLE_TIME, REQ_ACK_IMD_EN),
+	SUB_CTRL_CON_EN(CHN_CONN_MCU, XO_DEFAULT_STABLE_TIME, REQ_ACK_IMD_EN),
+	SUB_CTRL_CON_EN(CHN_COANT, XO_DEFAULT_STABLE_TIME, REQ_ACK_IMD_EN),
+	SUB_CTRL_CON_EN(CHN_NFC, XO_DEFAULT_STABLE_TIME, REQ_ACK_IMD_EN),
+	SUB_CTRL_CON_EN(CHN_SUSPEND2, XO_DEFAULT_STABLE_TIME, REQ_ACK_IMD_EN),
+	SUB_CTRL_CON_EN(CHN_UFS, XO_DEFAULT_STABLE_TIME, REQ_ACK_IMD_EN),
+};
+
+static void rc_dump_reg_info(void)
+{
+	int chn_n;
+
+	printk(BIOS_INFO, "RG_DEBUG_CFG[24]: %#lx\n",
+	       (read32(&rc_regs->rc_debug_cfg) & BIT(24)) >> 24);
+	printk(BIOS_INFO, "SRCLKEN_RC_CFG: 0x%x\n", read32(&rc_regs->srclken_rc_cfg));
+	printk(BIOS_INFO, "RG_SRCLKEN_SW_CON_CFG: 0x%x\n",
+	       read32(&rc_regs->srclken_sw_con_cfg));
+	printk(BIOS_INFO, "RG_PMIC_RCEN_ADDR: 0x%x\n", read32(&rc_regs->rc_pmic_rcen_addr));
+	printk(BIOS_INFO, "RG_PMIC_RCEN_SET_CLR_ADDR: 0x%x\n",
+	       read32(&rc_regs->rc_pmic_rcen_set_clr_addr));
+	printk(BIOS_INFO, "RG_CMD_ARB_CFG: 0x%x\n", read32(&rc_regs->rc_cmd_arb_cfg));
+	printk(BIOS_INFO, "RG_CENTRAL_CFG1: 0x%x\n", read32(&rc_regs->rc_central_cfg1));
+	printk(BIOS_INFO, "RG_CENTRAL_CFG2: 0x%x\n", read32(&rc_regs->rc_central_cfg2));
+	printk(BIOS_INFO, "RG_CENTRAL_CFG3: 0x%x\n", read32(&rc_regs->rc_central_cfg3));
+	printk(BIOS_INFO, "RG_CENTRAL_CFG4: 0x%x\n", read32(&rc_regs->rc_central_cfg4));
+	printk(BIOS_INFO, "RG_CENTRAL_CFG5: 0x%x\n", read32(&rc_regs->rc_central_cfg5));
+	printk(BIOS_INFO, "RG_CENTRAL_CFG6: 0x%x\n", read32(&rc_regs->rc_central_cfg6));
+	printk(BIOS_INFO, "RG_DCXO_FPM_CFG: 0x%x\n", read32(&rc_regs->rc_dcxo_fpm_cfg));
+	printk(BIOS_INFO, "SUBSYS_INTF_CFG: 0x%x\n", read32(&rc_regs->subsys_intf_cfg));
+	printk(BIOS_INFO, "RC_SPI_STA_0: 0x%x\n", read32(&rc_regs->rc_spi_sta_0));
+	printk(BIOS_INFO, "RC_PI_PO_STA: 0x%x\n", read32(&rc_regs->rc_pi_po_sta));
+	for (chn_n = 0; chn_n < MAX_CHN_NUM; chn_n++)
+		printk(BIOS_INFO, "M%d: 0x%x\n", chn_n,
+		       read32(&rc_regs->rc_mxx_srclken_cfg[chn_n]));
+}
+
+static void rc_ctrl_mode_switch_init(void)
+{
+	int ch;
+	const struct subsys_rc_con *rc_ctrl_ch;
+	for (ch = 0; ch < MAX_CHN_NUM; ch++) {
+		rc_ctrl_ch = &rc_ctrl[ch];
+		SET32_BITFIELDS(&rc_regs->rc_mxx_srclken_cfg[ch],
+				DCXO_SETTLE_BLK_EN, rc_ctrl_ch->dcxo_settle_blk_en,
+				BYPASS_CMD_EN, rc_ctrl_ch->bypass_cmd,
+				SW_SRCLKEN_RC, rc_ctrl_ch->sw_rc,
+				SW_SRCLKEN_FPM, rc_ctrl_ch->sw_fpm,
+				SW_SRCLKEN_BBLPM, rc_ctrl_ch->sw_bblpm,
+				XO_SOC_LINKAGE_EN, rc_ctrl_ch->xo_soc_link_en,
+				REQ_ACK_LOW_IMD_EN, rc_ctrl_ch->req_ack_imd_en,
+				SRCLKEN_TRACK_M_EN, rc_ctrl_ch->track_en,
+				CNT_PRD_STEP, rc_ctrl_ch->cnt_step,
+				XO_STABLE_PRD, rc_ctrl_ch->xo_prd,
+				DCXO_STABLE_PRD, rc_ctrl_ch->dcxo_prd);
+	}
+}
+
+static int polling_rc_chn_ack(int chn, u32 chk_sta)
+{
+	u32 pmrc_en;
+
+	if (!retry(ACK_DELAY_TIMES,
+		   (read32(&rc_regs->rc_mxx_req_sta[chn]) & 0xA) == chk_sta,
+		   udelay(ACK_DELAY_US))) {
+		pmrc_en = clk_buf_get_pmrc_en();
+		printk(BIOS_ERR, "%s: polling M%u"
+		       "status fail(R:0x%x)(C:0x%x)(PMRC:0x%x)\n",
+		       __func__, chn,
+		       read32(&rc_regs->rc_mxx_req_sta[chn]),
+		       read32(&rc_regs->rc_mxx_srclken_cfg[chn]),
+		       pmrc_en);
+		return -1;
+	}
+
+	return 0;
+}
+
+int srclken_rc_init(void)
+{
+	int chn_n, fpm;
+	u32 chk_sta;
+
+	/* Todo: Init in pll init flow */
+	/* enable srclken_rc debug trace */
+	SET32_BITFIELDS(&rc_regs->rc_debug_cfg, TRACE_MODE_EN, 0x1);
+
+	/* Set SW RESET 1 */
+	SET32_BITFIELDS(&rc_regs->srclken_rc_cfg, SW_RESET, 0x1);
+
+	/* Wait 100us */
+	udelay(100);
+
+	/* Set SW CG 1 */
+	SET32_BITFIELDS(&rc_regs->srclken_rc_cfg, CG_32K_EN, 0x7);
+
+	/* Wait 100us */
+	udelay(100);
+
+	/* Set Clock Mux*/
+	SET32_BITFIELDS(&rc_regs->srclken_rc_cfg, MUX_FCLK_FR, 0x1);
+
+	/* Set req_filter m00~m13 as default SW_FPM */
+	rc_ctrl_mode_switch_init();
+
+	/* enable sw trace & pmrc_o0 sel */
+	SET32_BITFIELDS(&rc_regs->srclken_sw_con_cfg, TACE_EN, 0x1);
+	SET32_BITFIELDS(&rc_regs->srclken_sw_con_cfg, TIE_SYS_RDY, 0x1);
+
+	/* Set PMIC addr for SPI CMD */
+	write32(&rc_regs->rc_pmic_rcen_addr, PMRC_CON0);
+	write32(&rc_regs->rc_cmd_arb_cfg, 0);
+
+	/* CFG1 setting for spi cmd config */
+	WRITE32_BITFIELDS(&rc_regs->rc_central_cfg1,
+			  DCXO_SETTLE_T, DCXO_SETTLE_TIME_VAL,
+			  NON_DCXO_SETTLE_T, NON_DCXO_SETTLE_TIME_VAL,
+			  ULPOSC_SETTLE_T, ULPOSC_SETTLE_TIME_VAL,
+			  VCORE_SETTLE_T, VCORE_SETTLE_TIME_VAL,
+			  SRCLKEN_RC_EN_SEL, SRCLKEN_RC_EN_SEL_VAL,
+			  RC_SPI_ACTIVE, KEEP_RC_SPI_ACTIVE_VAL,
+			  RCEN_ISSUE_M, IS_SPI2PMIC_SET_CLR_VAL,
+			  SRCLKEN_RC_EN, RC_CENTRAL_DISABLE_VAL);
+
+	/* CFG2 setting for signal mode of each control mux */
+	WRITE32_BITFIELDS(&rc_regs->rc_central_cfg2,
+			  PWRAP_SLP_MUX_SEL, SPI_CLK_SRC,
+			  PWRAP_SLP_CTRL_M, PWRAP_CTRL_M,
+			  ULPOSC_CTRL_M, ULPOSC_CTRL_M_VAL,
+			  SRCVOLTEN_VREQ_M, IS_SPI_DONE_RELEASE,
+			  SRCVOLTEN_VREQ_SEL, SPI_TRIG_MODE,
+			  VREQ_CTRL, VREQ_CTRL_M,
+			  SRCVOLTEN_CTRL, SRCLKENO_0_CTRL_M);
+	WRITE32_BITFIELDS(&rc_regs->rc_central_cfg3,
+			  TO_LPM_SETTLE_T, 0x4,
+			  TO_BBLPM_SETTLE_EN, 0x1,
+			  BLK_COANT_DXCO_MD_TARGET, 0x1,
+			  BLK_SCP_DXCO_MD_TARGET, 0x1,
+			  TO_LPM_SETTLE_EN, 0x1);
+
+	/* broadcast/multi-cmd setting */
+	WRITE32_BITFIELDS(&rc_regs->rc_central_cfg5,
+			  SPMI_CMD_BYTE_CNT, RC_SPMI_BYTE_LEN,
+			  SPMI_M_SLV_ID, PMIC_GROUP_ID,
+			  SPMI_P_SLV_ID, PMIC_GROUP_ID,
+			  SPMI_P_PMIF_ID, 0x1,
+			  SPMI_M_CMD_TYPE, 0x3,
+			  SPMI_P_CMD_TYPE, 0x3,
+			  SPMI_M_WRITE_EN, 0x1,
+			  SPMI_P_WRITE_EN, 0x1,
+			  BROADCAST_MODE_EN, 0x1,
+			  DCXO_ENCODE, 0x1,
+			  SPMI_M_FIRST, 0x1);
+
+	/* CFG6 = 0x0 */
+	WRITE32_BITFIELDS(&rc_regs->rc_central_cfg6,
+			  REQ_TO_DCXO_MASK, DCXO_MASK_SUBSYS,
+			  REQ_TO_SPMI_P_MASK_B, REQ_TO_SPMI_P_SUBSYS);
+
+	/* Set srclkeno_0/conn_bt as factor to allow dcxo change to FPM */
+	WRITE32_BITFIELDS(&rc_regs->rc_dcxo_fpm_cfg,
+			  SUB_SRCLKEN_FPM_MSK_B, FULL_SET_HW_MODE,
+			  SRCVOLTEN_FPM_MSK_B, MD0_SRCLKENO_0_MASK_B,
+			  DCXO_FPM_CTRL_M, DCXO_FPM_CTRL_MODE);
+
+	/* Set bblpm/fpm channel */
+	WRITE32_BITFIELDS(&rc_regs->subsys_intf_cfg,
+			  SRCLKEN_BBLPM_MASK_B, SUB_BBLPM_SET,
+			  SRCLKEN_FPM_MASK_B, SUB_FPM_SET);
+
+	/* Trigger srclken_rc enable */
+	SET32_BITFIELDS(&rc_regs->rc_central_cfg1, SRCLKEN_RC_EN, 0x1);
+
+	/* MT8189 uses PMIF_M only */
+	WRITE32_BITFIELDS(&rc_regs->rc_central_cfg4,
+			  SLEEP_VLD_MODE, 0x1,
+			  PWRAP_VLD_FORCE, 0x1,
+			  KEEP_RC_SPI_ACTIVE, 0x800,
+			  BYPASS_PMIF_P, 0x1);
+
+	/* Wait 100us */
+	udelay(100);
+
+	/* Set SW RESET 0 */
+	SET32_BITFIELDS(&rc_regs->srclken_rc_cfg, SW_RESET, 0x0);
+
+	/* Wait 100us */
+	udelay(100);
+
+	/* Set SW CG 0 */
+	SET32_BITFIELDS(&rc_regs->srclken_rc_cfg, CG_32K_EN, 0x0);
+
+	/* Wait 500us */
+	udelay(500);
+
+	/* Set req_filter m00~m12 FPM to LPM*/
+	rc_init_subsys_lpm();
+
+	/* Polling ACK of Initial Subsys Input */
+	for (chn_n = 0; chn_n < MAX_CHN_NUM; chn_n++) {
+		fpm = rc_ctrl[chn_n].sw_fpm;
+		if (rc_config[chn_n].lpm)
+			fpm = SW_FPM_LOW;
+
+		chk_sta = (fpm & SW_SRCLKEN_FPM_MSK) << 1 |
+			  (rc_ctrl[chn_n].sw_bblpm & SW_SRCLKEN_BBLPM_MSK) << 3;
+		if (polling_rc_chn_ack(chn_n, chk_sta))
+			die("%s() failed to polling rc_chn %d\n", __func__, chn_n);
+	}
+
+	/* Set req_filter m00~m13 */
+	rc_init_subsys_hw_mode();
+
+	/* release force pmic req signal*/
+	SET32_BITFIELDS(&rc_regs->rc_central_cfg4, PWRAP_VLD_FORCE, 0x0);
+
+	rc_dump_reg_info();
+
+	return 0;
+}

From 4b6ebbdd9482f0bf93aa017f381584bf41b7a360 Mon Sep 17 00:00:00 2001
From: LiLiang Chen <liliang.chen@mediatek.corp-partner.google.com>
Date: Sun, 8 Jun 2025 22:55:40 +0800
Subject: [PATCH 1658/3886] mb/google/skywalker: Initialize clkbuf and srclken
 in romstage

Initialize clkbuf and srclken drivers.

BUG=b:379008996,b:422503190,b:403478729
BRANCH=none
TEST=1. Check register is configured  correctly:
clkbuf:
[clk_buf_init_pmic_clkbuf] XO_WCN_VOTER(0x7c0)
[clk_buf_init_pmic_clkbuf] XO_NFC_VOTER(0x1)
[clk_buf_init_pmic_clkbuf] XO_CEL_VOTER(0x7c0)
[clk_buf_init_pmic_clkbuf] XO_EXT_VOTER(0x1)
srclken:
RG_CENTRAL_CFG1: 0x104014e5
RG_CENTRAL_CFG2: 0x1010
RG_CENTRAL_CFG3: 0x400f
RG_CENTRAL_CFG4: 0x2020800
RG_CENTRAL_CFG5: 0x1bfc1761
RG_CENTRAL_CFG6: 0x0
2. Pass Y1_PMIC MT6365-26MHz cystal test.

Signed-off-by: LiLiang Chen <liliang.chen@mediatek.corp-partner.google.com>
Signed-off-by: Vince Liu <vince-wl.liu@mediatek.corp-partner.google.com>
Change-Id: I9fe79a9f457f3e2efd2e810b87ea91c92ddd69b5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88526
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
---
 src/mainboard/google/skywalker/romstage.c | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/src/mainboard/google/skywalker/romstage.c b/src/mainboard/google/skywalker/romstage.c
index 9aa89a2730..822134b30b 100644
--- a/src/mainboard/google/skywalker/romstage.c
+++ b/src/mainboard/google/skywalker/romstage.c
@@ -2,6 +2,7 @@
 
 #include <arch/stages.h>
 #include <delay.h>
+#include <soc/clkbuf_ctl.h>
 #include <soc/dvfs.h>
 #include <soc/emi.h>
 #include <soc/mt6315.h>
@@ -10,6 +11,7 @@
 #include <soc/pmif.h>
 #include <soc/regulator.h>
 #include <soc/rtc.h>
+#include <soc/srclken_rc.h>
 #include <soc/thermal.h>
 
 static void raise_little_cpu_freq(void)
@@ -30,5 +32,7 @@ void platform_romstage_main(void)
 	rtc_boot();
 	dvfs_init();
 	mtk_dram_init();
+	srclken_rc_init();
+	clk_buf_init();
 	thermal_init();
 }

From 00d99a6e9bcb8004a072d130753746b9ab6d23a1 Mon Sep 17 00:00:00 2001
From: Jian Tong <tongjian@huaqin.corp-partner.google.com>
Date: Wed, 23 Jul 2025 13:52:06 +0800
Subject: [PATCH 1659/3886] mb/google/brox/var/lotso: Configure Acoustic noise
 mitigation

- Enable Acoustic noise mitigation
- Set slow slew rate VCCIA and VCCGT to SLEW_FAST_4
- Set FastPkgCRampDisable VCCIA and VCCGT to 1

BUG=b:404416910
TEST=emerge-brox coreboot chromeos-bootimage
	USE=fw_debug confirm SlowSlewRate set to 1 at FSP

Change-Id: I0b8622472e4e851bb5d1d64367a402f7ad6dfabc
Signed-off-by: Jian Tong <tongjian@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88537
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Dengwu Yu <yudengwu@huaqin.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kun Liu <liukun11@huaqin.corp-partner.google.com>
---
 src/mainboard/google/brox/variants/lotso/overridetree.cb | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/src/mainboard/google/brox/variants/lotso/overridetree.cb b/src/mainboard/google/brox/variants/lotso/overridetree.cb
index f3c8107169..c1b919269e 100644
--- a/src/mainboard/google/brox/variants/lotso/overridetree.cb
+++ b/src/mainboard/google/brox/variants/lotso/overridetree.cb
@@ -72,6 +72,13 @@ chip soc/intel/alderlake
 		[PchSerialIoIndexGSPI1] = PchSerialIoPci,
 	}"
 
+	# Acoustic settings
+	register "acoustic_noise_mitigation" = "1"
+	register "slow_slew_rate[VR_DOMAIN_IA]" = "SLEW_FAST_4"
+	register "slow_slew_rate[VR_DOMAIN_GT]" = "SLEW_FAST_4"
+	register "fast_pkg_c_ramp_disable[VR_DOMAIN_IA]" = "1"
+	register "fast_pkg_c_ramp_disable[VR_DOMAIN_GT]" = "1"
+
 	register "power_limits_config[RPL_P_282_242_142_15W_CORE]" = "{
 		.tdp_pl1_override = 15,
 		.tdp_pl2_override = 25,

From 26e6d0be00004143f63fd5fa2966c7326a433e08 Mon Sep 17 00:00:00 2001
From: Subrata Banik <subratabanik@google.com>
Date: Tue, 22 Jul 2025 04:31:31 +0000
Subject: [PATCH 1660/3886] mb/google/rex/var/karis: Use ACPI for touchscreen
 power sequencing

This commit transitions the touchscreen power sequencing for the Karis
variant from static coreboot GPIO configuration to ACPI-driven
management. This allows the kernel's touch driver to handle the power
sequencing, providing more flexible and dynamic control.

Redundant touchscreen GPIO configurations in bootblock and romstage are
removed from early_gpio_table, and romstage_gpio_table. These GPIOs are
no longer required to be explicitly set in coreboot given the shift to
ACPI power sequencing.

The generic.use_gpio_for_status register is set to true in the
device's override tree to enable ACPI power sequencing for touchscreen
signaling.

When the generic.use_gpio_for_status flag is enabled, the touchscreen
driver's power resource method will perform a probe to determine the
device's operational status. This probe specifically verifies two
critical conditions:

- The Enable GPIO pin is enabled (HIGH).
- The Reset GPIO pin is not in reset (LOW).

If both of these conditions are met, the touchscreen is considered ready
and functional.

Conversely, if either of these conditions is not met, the _ON method
within the power resource will be invoked. The _ON method is then
responsible for executing the full touchscreen initialization sequence
to bring the device into an operational state.

BUG=b:430444353
TEST=Able to build and boot google/karis. Verified touchscreen is
working as expected with this patch.

Change-Id: I967650290dda9ca3ca66a2f161fff0ae84b14f04
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88516
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/google/rex/variants/karis/gpio.c          | 9 ---------
 src/mainboard/google/rex/variants/karis/overridetree.cb | 1 +
 2 files changed, 1 insertion(+), 9 deletions(-)

diff --git a/src/mainboard/google/rex/variants/karis/gpio.c b/src/mainboard/google/rex/variants/karis/gpio.c
index 0bc8f3d7f9..9c130348b0 100644
--- a/src/mainboard/google/rex/variants/karis/gpio.c
+++ b/src/mainboard/google/rex/variants/karis/gpio.c
@@ -399,11 +399,6 @@ static const struct pad_config early_gpio_table[] = {
 	/* GPP_H10 : [] ==> SOC_WP_OD */
 	PAD_CFG_GPI_GPIO_DRIVER_LOCK(GPP_H10, NONE, LOCK_CONFIG),
 
-	/* GPP_C00 : [] ==> EN_TCHSCR_PWR */
-	PAD_CFG_GPO(GPP_C00, 1, DEEP),
-	/* GPP_C01 : [] ==> SOC_TCHSCR_RST_R_L */
-	PAD_CFG_GPO(GPP_C01, 0, DEEP),
-
 	/* GPP_A19 : [] ==> EN_PP3300_SSD */
 	PAD_CFG_GPO(GPP_A19, 1, DEEP),
 };
@@ -413,10 +408,6 @@ static const struct pad_config romstage_gpio_table[] = {
 	PAD_CFG_GPO(GPP_B11, 0, DEEP),
 	/* GPP_C23 : [] ==> FP_RST_ODL */
 	PAD_CFG_GPO(GPP_C23, 0, DEEP),
-	/* GPP_C00 : [] ==> EN_TCHSCR_PWR */
-	PAD_CFG_GPO(GPP_C00, 1, DEEP),
-	/* GPP_C01 : [] ==> SOC_TCHSCR_RST_R_L */
-	PAD_CFG_GPO(GPP_C01, 0, DEEP),
 	/* GPP_D02 : Not Connected */
 	PAD_NC(GPP_D02, NONE),
 	/* GPP_A20 : [] ==> SSD_PERST_L */
diff --git a/src/mainboard/google/rex/variants/karis/overridetree.cb b/src/mainboard/google/rex/variants/karis/overridetree.cb
index ea45d61981..2607ad776f 100644
--- a/src/mainboard/google/rex/variants/karis/overridetree.cb
+++ b/src/mainboard/google/rex/variants/karis/overridetree.cb
@@ -404,6 +404,7 @@ chip soc/intel/meteorlake
 				register "generic.stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C06)"
 				register "generic.stop_off_delay_ms" = "1"
 				register "generic.has_power_resource" = "1"
+				register "generic.use_gpio_for_status" = "true"
 				register "hid_desc_reg_offset" = "0x01"
 				device i2c 0x10 on end
 			end

From 712aac780fba8880c0a741b5a82180b8ecd7e21e Mon Sep 17 00:00:00 2001
From: Subrata Banik <subratabanik@google.com>
Date: Mon, 21 Jul 2025 13:31:04 +0000
Subject: [PATCH 1661/3886] mb/google/rex/kanix: Use ACPI for touchscreen power
 sequencing

This commit transitions the touchscreen power sequencing for the Karis
variant from static coreboot GPIO configuration to ACPI-driven
management. This allows the kernel's touch driver to handle the power
sequencing, providing more flexible and dynamic control.

Redundant touchscreen GPIO configurations are removed from
early_gpio_table, and romstage_gpio_table. These GPIOs are no
longer required to be explicitly set in coreboot given the shift to ACPI
power sequencing.

The generic.use_gpio_for_status register is set to true in the
device's override tree to enable ACPI power sequencing for touchscreen
signaling.

When the generic.use_gpio_for_status flag is enabled, the touchscreen
driver's power resource method will perform a probe to determine the
device's operational status. This probe specifically verifies two
critical conditions:

- The Enable GPIO pin is enabled (HIGH).
- The Reset GPIO pin is not in reset (LOW).

If both of these conditions are met, the touchscreen is considered ready
and functional.

Conversely, if either of these conditions is not met, the _ON method
within the power resource will be invoked. The _ON method is then
responsible for executing the full touchscreen initialization sequence
to bring the device into an operational state.

BUG=b:430444353
TEST=Able to build and boot google/kanix. Verified touchscreen is
working as expected with this patch.

Change-Id: I5c049c76fed185a40c31a6e779119c953926e6c9
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88517
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
---
 src/mainboard/google/rex/variants/kanix/gpio.c         | 10 +---------
 .../google/rex/variants/kanix/overridetree.cb          |  1 +
 2 files changed, 2 insertions(+), 9 deletions(-)

diff --git a/src/mainboard/google/rex/variants/kanix/gpio.c b/src/mainboard/google/rex/variants/kanix/gpio.c
index 4b757a1ae5..3b44043354 100644
--- a/src/mainboard/google/rex/variants/kanix/gpio.c
+++ b/src/mainboard/google/rex/variants/kanix/gpio.c
@@ -399,11 +399,6 @@ static const struct pad_config early_gpio_table[] = {
 	/* GPP_H10 : [] ==> SOC_WP_OD */
 	PAD_CFG_GPI_GPIO_DRIVER_LOCK(GPP_H10, NONE, LOCK_CONFIG),
 
-	/* GPP_C00 : [] ==> EN_TCHSCR_PWR */
-	PAD_CFG_GPO(GPP_C00, 1, DEEP),
-	/* GPP_C01 : [] ==> SOC_TCHSCR_RST_R_L */
-	PAD_CFG_GPO(GPP_C01, 0, DEEP),
-
 	/* GPP_A19 : [] ==> EN_PP3300_SSD */
 	PAD_CFG_GPO(GPP_A19, 1, DEEP),
 };
@@ -413,10 +408,7 @@ static const struct pad_config romstage_gpio_table[] = {
 	PAD_CFG_GPO(GPP_B11, 0, DEEP),
 	/* GPP_C23 : [] ==> FP_RST_ODL */
 	PAD_CFG_GPO(GPP_C23, 0, DEEP),
-	/* GPP_C00 : [] ==> EN_TCHSCR_PWR */
-	PAD_CFG_GPO(GPP_C00, 1, DEEP),
-	/* GPP_C01 : [] ==> SOC_TCHSCR_RST_R_L */
-	PAD_CFG_GPO(GPP_C01, 0, DEEP),
+
 	/* GPP_D02 : Not Connected */
 	PAD_NC(GPP_D02, NONE),
 	/* GPP_A20 : [] ==> SSD_PERST_L */
diff --git a/src/mainboard/google/rex/variants/kanix/overridetree.cb b/src/mainboard/google/rex/variants/kanix/overridetree.cb
index f0d57b3046..31fbf555a6 100644
--- a/src/mainboard/google/rex/variants/kanix/overridetree.cb
+++ b/src/mainboard/google/rex/variants/kanix/overridetree.cb
@@ -459,6 +459,7 @@ chip soc/intel/meteorlake
 				register "generic.stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C06)"
 				register "generic.stop_off_delay_ms" = "1"
 				register "generic.has_power_resource" = "1"
+				register "generic.use_gpio_for_status" = "true"
 				register "hid_desc_reg_offset" = "0x01"
 				device i2c 0x10 on end
 			end

From a6842184abfdfdf10d2b38223bb03ff09102b021 Mon Sep 17 00:00:00 2001
From: Subrata Banik <subratabanik@google.com>
Date: Mon, 21 Jul 2025 14:35:14 +0000
Subject: [PATCH 1662/3886] mb/google/fatcat/var/kinmen: Use ACPI for
 touchscreen power sequencing

This commit removes redundant touchscreen GPIO configurations from
romstage_gpio_table. These GPIOs are no longer required to be explicitly
set for the touchscreen while using ACPI for touchscreen power
sequencing.

When the generic.use_gpio_for_status flag is enabled, the touchscreen
driver's power resource method will perform a probe to determine the
device's operational status. This probe specifically verifies two
critical conditions:

- The Enable GPIO pin is enabled (HIGH).
- The Reset GPIO pin is not in reset (LOW).

If both of these conditions are met, the touchscreen is considered ready
and functional.

Conversely, if either of these conditions is not met, the _ON method
within the power resource will be invoked. The _ON method is then
responsible for executing the full touchscreen initialization sequence
to bring the device into an operational state.

BUG=b:430444353
TEST=Able to build and boot google/kinmen. Verified touchscreen is
working as expected with this patch.

Change-Id: I0bb2e1ddd4168ef1831b30817dbb3bc3f6e6a5d2
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88518
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
---
 src/mainboard/google/fatcat/variants/kinmen/gpio.c | 4 ----
 1 file changed, 4 deletions(-)

diff --git a/src/mainboard/google/fatcat/variants/kinmen/gpio.c b/src/mainboard/google/fatcat/variants/kinmen/gpio.c
index ae339809e8..9a28421783 100644
--- a/src/mainboard/google/fatcat/variants/kinmen/gpio.c
+++ b/src/mainboard/google/fatcat/variants/kinmen/gpio.c
@@ -424,10 +424,6 @@ static const struct pad_config romstage_gpio_table[] = {
 	PAD_CFG_GPO(GPP_E19, 0, DEEP),
 	/* GPP_C15:     FPS_RST_N */
 	PAD_CFG_GPO(GPP_C15, 0, DEEP),
-	/* GPP_F08:     EN_TCHSCR_PWR */
-	PAD_CFG_GPO(GPP_F08, 1, DEEP),
-	/* GPP_F16:     TCHSCR_RST_L */
-	PAD_CFG_GPO(GPP_F16, 0, DEEP),
 };
 
 const struct pad_config *variant_gpio_table(size_t *num)

From 8bdc170901d013e1facad3dea31bba8346caa401 Mon Sep 17 00:00:00 2001
From: Jian Tong <tongjian@huaqin.corp-partner.google.com>
Date: Wed, 23 Jul 2025 14:02:19 +0800
Subject: [PATCH 1663/3886] mb/google/brox/var/lotso: Update VR domain config

Based on RPL 15W baseline and 686872_RPL_UPH_RPL_UH_R_Power_Map_Rev2p4p1.xlsm
Get VR domain configs from internal power teams.

BUG=b:404416910
TEST=emerge-brox coreboot chromeos-bootimage
	USE=fw_debug confirm VR configs

Change-Id: I5c7124477eeaa7b864e58c083e9c546f955bee29
Signed-off-by: Jian Tong <tongjian@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88539
Reviewed-by: Kun Liu <liukun11@huaqin.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Dengwu Yu <yudengwu@huaqin.corp-partner.google.com>
Reviewed-by: YH Lin <yueherngl@google.com>
---
 .../brox/variants/lotso/overridetree.cb       | 19 +++++++++++++++++++
 1 file changed, 19 insertions(+)

diff --git a/src/mainboard/google/brox/variants/lotso/overridetree.cb b/src/mainboard/google/brox/variants/lotso/overridetree.cb
index c1b919269e..6338e828f6 100644
--- a/src/mainboard/google/brox/variants/lotso/overridetree.cb
+++ b/src/mainboard/google/brox/variants/lotso/overridetree.cb
@@ -79,6 +79,25 @@ chip soc/intel/alderlake
 	register "fast_pkg_c_ramp_disable[VR_DOMAIN_IA]" = "1"
 	register "fast_pkg_c_ramp_disable[VR_DOMAIN_GT]" = "1"
 
+	# VR Settings
+	register "domain_vr_config[VR_DOMAIN_IA]" = "{
+		.vr_config_enable = 1,
+		.icc_max = 248,
+		.tdc_timewindow = 28000,
+		.tdc_currentlimit = 176,
+		.ac_loadline = 280,
+		.dc_loadline = 280,
+	}"
+
+	register "domain_vr_config[VR_DOMAIN_GT]" = "{
+		.vr_config_enable = 1,
+		.icc_max = 160,
+		.tdc_timewindow = 28000,
+		.tdc_currentlimit = 176,
+		.ac_loadline = 320,
+		.dc_loadline = 320,
+	}"
+
 	register "power_limits_config[RPL_P_282_242_142_15W_CORE]" = "{
 		.tdp_pl1_override = 15,
 		.tdp_pl2_override = 25,

From 69e6d96aad68b20ca35ff2bdcdcc62c777706d85 Mon Sep 17 00:00:00 2001
From: Megha Verma <megha.verma@intel.com>
Date: Thu, 24 Jul 2025 12:12:49 +0530
Subject: [PATCH 1664/3886] mb/google/fatcat: Configure host command ranges for
 FATCAT4ES variant

The commit introduces changes to support the FATCAT4ES board variant
by updating the EC command range configuration. The changes updates the
gen1_dec register to configure correctly to accomdate the FATCAT4ES
variant which ensures the ec-host communication should not fail. Also it
ensures other conditional checks in the EC header file for enabling this
new variant.

BUG=b:432676108
TEST=Build with the FATCAT4ES configuration and verify ec host
    communication is not failing.

Change-Id: I5c84dc2161847f9fe4316c0e63aa876696947423
Signed-off-by: Megha Verma <megha.verma@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88552
Reviewed-by: <srinivas.kulkarni@intel.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 .../google/fatcat/variants/baseboard/fatcat/devicetree.cb     | 2 +-
 .../fatcat/variants/baseboard/fatcat/include/baseboard/ec.h   | 4 +++-
 src/mainboard/google/fatcat/variants/fatcat/gpio.c            | 2 +-
 3 files changed, 5 insertions(+), 3 deletions(-)

diff --git a/src/mainboard/google/fatcat/variants/baseboard/fatcat/devicetree.cb b/src/mainboard/google/fatcat/variants/baseboard/fatcat/devicetree.cb
index 5c73dee1e0..6eded7c12f 100644
--- a/src/mainboard/google/fatcat/variants/baseboard/fatcat/devicetree.cb
+++ b/src/mainboard/google/fatcat/variants/baseboard/fatcat/devicetree.cb
@@ -8,7 +8,7 @@ chip soc/intel/pantherlake
 	#	EC host command ranges are in 0x800-0x807 & 0x200-0x20f
 	# For Fatcat variants with ITE/Nuvoton EC:
 	# 	EC host command ranges are in 0x800-0x8ff & 0x200-0x20f
-	register "gen1_dec" = "CONFIG(BOARD_GOOGLE_FATCAT) || CONFIG(BOARD_GOOGLE_FATCATISH) ? 0x00040801 : 0x00fc0801"
+	register "gen1_dec" = "CONFIG(BOARD_GOOGLE_FATCAT) || CONFIG(BOARD_GOOGLE_FATCAT4ES) || CONFIG(BOARD_GOOGLE_FATCATISH) ? 0x00040801 : 0x00fc0801"
 	register "gen2_dec" = "0x000c0201"
 	# EC memory map range is 0x900-0x9ff
 	register "gen3_dec" = "0x00fc0901"
diff --git a/src/mainboard/google/fatcat/variants/baseboard/fatcat/include/baseboard/ec.h b/src/mainboard/google/fatcat/variants/baseboard/fatcat/include/baseboard/ec.h
index 7fff4dae75..8f583e9308 100644
--- a/src/mainboard/google/fatcat/variants/baseboard/fatcat/include/baseboard/ec.h
+++ b/src/mainboard/google/fatcat/variants/baseboard/fatcat/include/baseboard/ec.h
@@ -75,7 +75,9 @@
 /* Enable EC backed PD MCU device in ACPI */
 #define EC_ENABLE_PD_MCU_DEVICE
 
-#if !CONFIG(BOARD_GOOGLE_FATCAT) && !CONFIG(BOARD_GOOGLE_FATCATISH)
+#if !CONFIG(BOARD_GOOGLE_FATCAT) \
+	&& !CONFIG(BOARD_GOOGLE_FATCAT4ES) \
+	&& !CONFIG(BOARD_GOOGLE_FATCATISH)
  #define EC_ENABLE_SYNC_IRQ      /* Enable tight timestamp / wake support */
  #define EC_SYNC_IRQ_WAKE_CAPABLE /* Let the OS know ec_sync is wake capable */
 #endif
diff --git a/src/mainboard/google/fatcat/variants/fatcat/gpio.c b/src/mainboard/google/fatcat/variants/fatcat/gpio.c
index b31ba05437..4b6462a60e 100644
--- a/src/mainboard/google/fatcat/variants/fatcat/gpio.c
+++ b/src/mainboard/google/fatcat/variants/fatcat/gpio.c
@@ -196,7 +196,7 @@ static const struct pad_config gpio_table[] = {
 	PAD_CFG_GPO(GPP_E03, 1, PLTRST),
 	/* GPP_E06:     SECURE_CAM_SW */
 	PAD_CFG_GPI_TRIG_OWN(GPP_E06, NONE, PLTRST, LEVEL, ACPI),
-#if CONFIG(BOARD_GOOGLE_FATCAT) || CONFIG(BOARD_GOOGLE_FATCATISH)
+#if CONFIG(BOARD_GOOGLE_FATCAT) || CONFIG(BOARD_GOOGLE_FATCAT4ES) || CONFIG(BOARD_GOOGLE_FATCATISH)
 	/* GPP_E07:     Not used */
 	PAD_NC(GPP_E07, NONE),
 #else

From c2dfe61016f3414627f3c7ec9064487ea89d55d0 Mon Sep 17 00:00:00 2001
From: Pranava Y N <pranavayn@google.com>
Date: Thu, 24 Jul 2025 11:39:58 +0530
Subject: [PATCH 1665/3886] mb/google/ocelot: Disable CNVi bluetooth core in
 the baseboard code

Disable CNVi bluetooth in the baseboard by default. This will be
enabled per variant basis based on the WIFI fw_config in variant.c
file.

BUG=b:433215861
TEST=Able to connect to boot Ocelot and connect to bluetooth.
Below error is not seen when WIFI_PCI_6/7 selected.

```
[ERROR]  CNVi BT is enabled without CNVi being enabled
```

Change-Id: Ibe5d22c013852f868a2a3296c79dfdf1de7c1455
Signed-off-by: Pranava Y N <pranavayn@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88551
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Avi Uday <aviuday@google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 .../google/ocelot/variants/baseboard/ocelot/devicetree.cb      | 3 ---
 1 file changed, 3 deletions(-)

diff --git a/src/mainboard/google/ocelot/variants/baseboard/ocelot/devicetree.cb b/src/mainboard/google/ocelot/variants/baseboard/ocelot/devicetree.cb
index 3c8ab4f7b1..2939a065fa 100644
--- a/src/mainboard/google/ocelot/variants/baseboard/ocelot/devicetree.cb
+++ b/src/mainboard/google/ocelot/variants/baseboard/ocelot/devicetree.cb
@@ -63,9 +63,6 @@ chip soc/intel/pantherlake
 	# Enable Energy Reporting
 	register "pch_pm_energy_report_enable" = "true"
 
-	# Enable CNVi BT
-	register "cnvi_bt_core" = "true"
-
 	register "serial_io_uart_mode" = "{
 		[PchSerialIoIndexUART0] = PchSerialIoSkipInit,
 		[PchSerialIoIndexUART1] = PchSerialIoDisabled,

From 88b10e09b6d752acd78a80014743230b6a1f24ca Mon Sep 17 00:00:00 2001
From: Pranava Y N <pranavayn@google.com>
Date: Wed, 23 Jul 2025 15:56:38 +0530
Subject: [PATCH 1666/3886] mb/google/ocelot: Set TPM_TIS_ACPI_INTERRUPT for
 all ocelot variants

Set `TPM_TIS_ACPI_INTERRUPT` to 49 (GPE0_DW1_17) for all ocelot
variants using `BOARD_GOOGLE_MODEL_OCELOT` instead of
`BOARD_GOOGLE_OCELOT`.

BUG=b:433177132
TEST=Able to boot Ocelot

Change-Id: I662e1b38530861da008cf54da4a31dd0ac6212c8
Signed-off-by: Pranava Y N <pranavayn@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88541
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Avi Uday <aviuday@google.com>
---
 src/mainboard/google/ocelot/Kconfig | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/mainboard/google/ocelot/Kconfig b/src/mainboard/google/ocelot/Kconfig
index 53c810345e..12d9e9ce67 100644
--- a/src/mainboard/google/ocelot/Kconfig
+++ b/src/mainboard/google/ocelot/Kconfig
@@ -142,7 +142,7 @@ config MEMORY_SOLDERDOWN
 
 config TPM_TIS_ACPI_INTERRUPT
 	int
-	default 49 if BOARD_GOOGLE_OCELOT # GPE0_DW1_17 (GPP_B17)
+	default 49 if BOARD_GOOGLE_MODEL_OCELOT # GPE0_DW1_17 (GPP_B17)
 
 config UART_FOR_CONSOLE
 	int

From dd76bcc4c3274a73d34c1aa3238ba2c79ca9c759 Mon Sep 17 00:00:00 2001
From: Sasirekaa Madhesu <smadhesu@qualcomm.corp-partner.google.com>
Date: Wed, 23 Jul 2025 19:04:14 +0530
Subject: [PATCH 1667/3886] soc/qc/sc7280: Relocate SHRM firmware load to
 common Qualcomm path

This patch moves the shrm_fw_load_reset() API from the SC7280 specific
implementation to the Qualcomm common directory. This change enables
reuse of the API across multiple Qualcomm chipsets.

Change-Id: Ifab870b9aea7396e29fa93c999c29cf11ab0d199
Signed-off-by: Sasirekaa Madhesu <smadhesu@qualcomm.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88545
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/soc/qualcomm/common/aop_load_reset.c              |  2 --
 src/soc/qualcomm/{sc7280 => common}/shrm_load_reset.c |  2 --
 src/soc/qualcomm/sc7280/Makefile.mk                   |  2 +-
 src/soc/qualcomm/sc7280/include/soc/clock.h           | 11 +++++++++--
 4 files changed, 10 insertions(+), 7 deletions(-)
 rename src/soc/qualcomm/{sc7280 => common}/shrm_load_reset.c (93%)

diff --git a/src/soc/qualcomm/common/aop_load_reset.c b/src/soc/qualcomm/common/aop_load_reset.c
index 9064120215..f746530891 100644
--- a/src/soc/qualcomm/common/aop_load_reset.c
+++ b/src/soc/qualcomm/common/aop_load_reset.c
@@ -15,6 +15,4 @@ void aop_fw_load_reset(void)
 		die("SOC image: AOP load failed");
 
 	clock_reset_aop();
-
-	printk(BIOS_DEBUG, "SOC:AOP brought out of reset.\n");
 }
diff --git a/src/soc/qualcomm/sc7280/shrm_load_reset.c b/src/soc/qualcomm/common/shrm_load_reset.c
similarity index 93%
rename from src/soc/qualcomm/sc7280/shrm_load_reset.c
rename to src/soc/qualcomm/common/shrm_load_reset.c
index 4da5a55dd6..f86dc10271 100644
--- a/src/soc/qualcomm/sc7280/shrm_load_reset.c
+++ b/src/soc/qualcomm/common/shrm_load_reset.c
@@ -27,6 +27,4 @@ void shrm_fw_load_reset(void)
 	mmu_config_range((void *)_shrm, REGION_SIZE(shrm), DEV_MEM);
 
 	clock_reset_shrm();
-
-	printk(BIOS_DEBUG, "SOC:SHRM brought out of reset.\n");
 }
diff --git a/src/soc/qualcomm/sc7280/Makefile.mk b/src/soc/qualcomm/sc7280/Makefile.mk
index ae23f45ede..7e010c731a 100644
--- a/src/soc/qualcomm/sc7280/Makefile.mk
+++ b/src/soc/qualcomm/sc7280/Makefile.mk
@@ -28,7 +28,7 @@ verstage-$(CONFIG_DRIVERS_UART) += ../common/qupv3_uart.c
 
 ################################################################################
 romstage-y += cbmem.c
-romstage-y += shrm_load_reset.c
+romstage-y += ../common/shrm_load_reset.c
 romstage-y += cpucp_load_reset.c
 romstage-y += ../common/qclib.c
 romstage-y += ../common/mmu.c
diff --git a/src/soc/qualcomm/sc7280/include/soc/clock.h b/src/soc/qualcomm/sc7280/include/soc/clock.h
index 402c898c4b..d6eb7a77c8 100644
--- a/src/soc/qualcomm/sc7280/include/soc/clock.h
+++ b/src/soc/qualcomm/sc7280/include/soc/clock.h
@@ -397,8 +397,15 @@ static struct aoss *const aoss = (void *)AOSS_CC_BASE;
 static struct shrm *const shrm = (void *)SHRM_SPROC_BASE;
 
 #define clock_reset_aop()  \
-	clock_reset_subsystem(&aoss->aoss_cc_apcs_misc, AOP_RESET_SHFT)
+	do {  \
+		clock_reset_subsystem(&aoss->aoss_cc_apcs_misc, AOP_RESET_SHFT);  \
+		printk(BIOS_DEBUG, "SOC:AOP brought out of reset.\n");  \
+	} while (0)
+
 #define clock_reset_shrm()  \
-	clock_reset_subsystem(&shrm->shrm_sproc_ctrl, SHRM_RUN_STALL)
+	do {  \
+		clock_reset_subsystem(&shrm->shrm_sproc_ctrl, SHRM_RUN_STALL);  \
+		printk(BIOS_DEBUG, "SOC:SHRM brought out of reset.\n");  \
+	} while (0)
 
 #endif	// __SOC_QUALCOMM_SC7280_CLOCK_H__

From f84934a203685d2085ee230b7888016b381c223e Mon Sep 17 00:00:00 2001
From: Eren Peng <peng.eren@inventec.corp-partner.google.com>
Date: Thu, 17 Jul 2025 17:42:49 +0800
Subject: [PATCH 1668/3886] mb/google/trulo/var/kaladin: Add DRAM part
 H58G56CK8BX146

Add DRAM part H58G56CK8BX146

BUG=b:432397864
TEST=Flash and boot to OS successfully on kaladin

Change-Id: Id880940d608c76b88e384ee2cbea03eec8e35b53
Signed-off-by: Eren Peng <peng.eren@inventec.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88469
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/google/brya/variants/kaladin/memory/Makefile.mk  | 3 ++-
 .../google/brya/variants/kaladin/memory/dram_id.generated.txt  | 3 ++-
 .../google/brya/variants/kaladin/memory/mem_parts_used.txt     | 1 +
 3 files changed, 5 insertions(+), 2 deletions(-)

diff --git a/src/mainboard/google/brya/variants/kaladin/memory/Makefile.mk b/src/mainboard/google/brya/variants/kaladin/memory/Makefile.mk
index 1b7204365d..39725c41d2 100644
--- a/src/mainboard/google/brya/variants/kaladin/memory/Makefile.mk
+++ b/src/mainboard/google/brya/variants/kaladin/memory/Makefile.mk
@@ -1,9 +1,10 @@
 # SPDX-License-Identifier: GPL-2.0-or-later
 # This is an auto-generated file. Do not edit!!
 # Generated by:
-# /tmp/go-build1397538409/b001/exe/part_id_gen ADL lp5 src/mainboard/google/brya/variants/kaladin/memory/ src/mainboard/google/brya/variants/kaladin/memory/mem_parts_used.txt
+# util/spd_tools/bin/part_id_gen ADL lp5 src/mainboard/google/brya/variants/kaladin/memory src/mainboard/google/brya/variants/kaladin/memory/mem_parts_used.txt
 
 SPD_SOURCES =
 SPD_SOURCES += spd/lp5/set-0/spd-1.hex      # ID = 0(0b0000)  Parts = H9JCNNNBK3MLYR-N6E
 SPD_SOURCES += spd/lp5/set-0/spd-9.hex      # ID = 1(0b0001)  Parts = K3KL6L60GM-MGCT
 SPD_SOURCES += spd/lp5/set-0/spd-7.hex      # ID = 2(0b0010)  Parts = K3KL8L80CM-MGCT
+SPD_SOURCES += spd/lp5/set-0/spd-11.hex      # ID = 3(0b0011)  Parts = H58G56CK8BX146
diff --git a/src/mainboard/google/brya/variants/kaladin/memory/dram_id.generated.txt b/src/mainboard/google/brya/variants/kaladin/memory/dram_id.generated.txt
index aade5a77ef..3a81c28ba4 100644
--- a/src/mainboard/google/brya/variants/kaladin/memory/dram_id.generated.txt
+++ b/src/mainboard/google/brya/variants/kaladin/memory/dram_id.generated.txt
@@ -1,9 +1,10 @@
 # SPDX-License-Identifier: GPL-2.0-or-later
 # This is an auto-generated file. Do not edit!!
 # Generated by:
-# /tmp/go-build1397538409/b001/exe/part_id_gen ADL lp5 src/mainboard/google/brya/variants/kaladin/memory/ src/mainboard/google/brya/variants/kaladin/memory/mem_parts_used.txt
+# util/spd_tools/bin/part_id_gen ADL lp5 src/mainboard/google/brya/variants/kaladin/memory src/mainboard/google/brya/variants/kaladin/memory/mem_parts_used.txt
 
 DRAM Part Name                 ID to assign
 H9JCNNNBK3MLYR-N6E             0 (0000)
 K3KL6L60GM-MGCT                1 (0001)
 K3KL8L80CM-MGCT                2 (0010)
+H58G56CK8BX146                 3 (0011)
diff --git a/src/mainboard/google/brya/variants/kaladin/memory/mem_parts_used.txt b/src/mainboard/google/brya/variants/kaladin/memory/mem_parts_used.txt
index e6fb0b2562..0cefe2ecaf 100644
--- a/src/mainboard/google/brya/variants/kaladin/memory/mem_parts_used.txt
+++ b/src/mainboard/google/brya/variants/kaladin/memory/mem_parts_used.txt
@@ -12,3 +12,4 @@
 H9JCNNNBK3MLYR-N6E
 K3KL6L60GM-MGCT
 K3KL8L80CM-MGCT
+H58G56CK8BX146

From 9a89e3b4c6a4c2cd6439718f9a99f86bfa1ed8d8 Mon Sep 17 00:00:00 2001
From: Eren Peng <peng.eren@inventec.corp-partner.google.com>
Date: Fri, 18 Jul 2025 11:18:40 +0800
Subject: [PATCH 1669/3886] mb/google/trulo/var/kaladin: Select
 USE_UNIFIED_AP_FIRMWARE_FOR_UFS_AND_NON_UFS

Kaladin need to set this config since we use unified firmware for UFS and non UFS skus

BUG=b:432579255
TEST=Flash and boot on every sku on kaladin

Change-Id: I5fa8f51776e6ba13e9003ea7913c2b4784b76217
Signed-off-by: Eren Peng <peng.eren@inventec.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88475
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
---
 src/mainboard/google/brya/Kconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/src/mainboard/google/brya/Kconfig b/src/mainboard/google/brya/Kconfig
index 399f1de409..a635ed0cb8 100644
--- a/src/mainboard/google/brya/Kconfig
+++ b/src/mainboard/google/brya/Kconfig
@@ -328,6 +328,7 @@ config BOARD_GOOGLE_KALADIN
 	select SOC_INTEL_COMMON_BLOCK_HDA_VERB
 	select SOC_INTEL_TCSS_USE_PDC_PMC_USBC_MUX_CONFIGURATION
 	select SOC_INTEL_TWINLAKE
+	select USE_UNIFIED_AP_FIRMWARE_FOR_UFS_AND_NON_UFS
 
 config BOARD_GOOGLE_KANO
 	select BOARD_GOOGLE_BASEBOARD_BRYA

From 28848dc4fb30571bbf62322becf9b8dbd06b1388 Mon Sep 17 00:00:00 2001
From: "wu.garen" <wu.garen@inventec.corp-partner.google.com>
Date: Thu, 17 Jul 2025 17:41:55 +0800
Subject: [PATCH 1670/3886] mb/google/trulo/var/kaladin: Add elan touchscreen
 support

New Touchscreen support for kaladin.
Touchscreen controller: ELAN_EKTH3918NBY

BUG=b:432399420

Change-Id: Ia6edc78e11c6dbd5835017f443f272ff3c12b66e
Signed-off-by: wu.garen <wu.garen@inventec.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88471
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
---
 .../brya/variants/kaladin/overridetree.cb       | 17 +++++++++++++++++
 1 file changed, 17 insertions(+)

diff --git a/src/mainboard/google/brya/variants/kaladin/overridetree.cb b/src/mainboard/google/brya/variants/kaladin/overridetree.cb
index cd264f6de5..c58dc8659d 100644
--- a/src/mainboard/google/brya/variants/kaladin/overridetree.cb
+++ b/src/mainboard/google/brya/variants/kaladin/overridetree.cb
@@ -447,6 +447,23 @@ chip soc/intel/alderlake
 				register "hid_desc_reg_offset" = "0x01"
 				device i2c 10 on end
 			end
+			chip drivers/i2c/hid
+				register "generic.hid" = ""ELAN2513""
+				register "generic.desc" = ""ELAN Touchscreen""
+				register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_E11_IRQ)"
+				register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C1)"
+				register "generic.reset_delay_ms" = "20"
+				register "generic.reset_off_delay_ms" = "2"
+				register "generic.stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C4)"
+				register "generic.stop_delay_ms" = "280"
+				register "generic.stop_off_delay_ms" = "2"
+				register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C0)"
+				register "generic.enable_delay_ms" = "1"
+				register "generic.has_power_resource" = "1"
+				register "generic.use_gpio_for_status" = "true"
+				register "hid_desc_reg_offset" = "0x01"
+				device i2c 15 on end
+			end
 		end #I2C1
 		device ref i2c5 on
 			chip drivers/i2c/generic

From 1ade8247ce7a4fba0aae8fcc1155c28ab5cbef56 Mon Sep 17 00:00:00 2001
From: lizheng <lizheng@huaqin.corp-partner.google.com>
Date: Thu, 24 Jul 2025 10:36:56 +0800
Subject: [PATCH 1671/3886] mb/google/trulo/var/pujjocento: update hda_verb
 table for ALC257

Update hda_verb table for pujjocento to optimize noise floor.

BUG=b:433647377
TEST=emerge-nissa sys-boot/coreboot sys-boot/chromeos-bootimage

Verify that the noise floor on AP is less than -90 dB when
DUT plays mute.wav.

Change-Id: Ib8642a88bb707e99c3d459eb70a6fdf5562f4c75
Signed-off-by: lizheng <lizheng@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88549
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/google/brya/variants/pujjocento/hda_verb.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/mainboard/google/brya/variants/pujjocento/hda_verb.c b/src/mainboard/google/brya/variants/pujjocento/hda_verb.c
index c995caf0f6..b857e82576 100644
--- a/src/mainboard/google/brya/variants/pujjocento/hda_verb.c
+++ b/src/mainboard/google/brya/variants/pujjocento/hda_verb.c
@@ -67,7 +67,7 @@ const u32 cim_verb_data[] = {
 	0x02050037,
 	0x0204FE15,
 	0x02050030,
-	0x02041000,
+	0x02049000,
 };
 
 const u32 pc_beep_verbs[] = {

From b20f6d27e21b3b4b94ef655fb4761047a37d2c7e Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Mon, 21 Jul 2025 14:17:50 -0500
Subject: [PATCH 1672/3886] device/dram: Rename 'USE_DDRx' config options

Rename config options 'USE_DDRx' to 'DRAM_SUPPORT_DDRx' to make them
less clunky, and in preparation to expand their use inside SoC code.

Change-Id: Ie6edd730c5cbad679a90fcf7989a942d9b2dd3d8
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88520
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: <yuchi.chen@intel.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
---
 src/device/dram/Kconfig                     | 20 +++++++++----------
 src/device/dram/Makefile.mk                 | 22 ++++++++++-----------
 src/mainboard/hardkernel/odroid-h4/Kconfig  |  2 +-
 src/mainboard/protectli/vault_adl_p/Kconfig |  2 +-
 src/northbridge/amd/pi/00730F01/Kconfig     |  2 +-
 src/northbridge/intel/gm45/Kconfig          |  4 ++--
 src/northbridge/intel/haswell/Kconfig       |  2 +-
 src/northbridge/intel/i945/Kconfig          |  2 +-
 src/northbridge/intel/ironlake/Kconfig      |  2 +-
 src/northbridge/intel/pineview/Kconfig      |  4 ++--
 src/northbridge/intel/sandybridge/Kconfig   |  2 +-
 src/northbridge/intel/x4x/Kconfig           |  4 ++--
 src/soc/amd/cezanne/Kconfig                 |  4 ++--
 src/soc/amd/common/fsp/dmi.c                |  6 +++---
 src/soc/amd/glinda/Kconfig                  |  2 +-
 src/soc/amd/mendocino/Kconfig               |  2 +-
 src/soc/amd/phoenix/Kconfig                 |  2 +-
 src/soc/amd/picasso/Kconfig                 |  2 +-
 src/soc/amd/stoneyridge/Kconfig             |  2 +-
 src/soc/intel/baytrail/Kconfig              |  2 +-
 src/soc/intel/snowridge/Kconfig             |  2 +-
 21 files changed, 46 insertions(+), 46 deletions(-)

diff --git a/src/device/dram/Kconfig b/src/device/dram/Kconfig
index b9b5de4f6d..ceb5be4caf 100644
--- a/src/device/dram/Kconfig
+++ b/src/device/dram/Kconfig
@@ -1,31 +1,31 @@
 ## SPDX-License-Identifier: GPL-2.0-only
 
-config USE_DDR5
+config DRAM_SUPPORT_DDR5
 	bool
 	default n
 	help
-	  system supports DDR5 memory
+	  System supports DDR5 memory
 
-config USE_LPDDR4
+config DRAM_SUPPORT_LPDDR4
 	bool
 	default n
 	help
-	  system supports LPDDR4 memory
+	  System supports LPDDR4 memory
 
-config USE_DDR4
+config DRAM_SUPPORT_DDR4
 	bool
 	default n
 	help
-	  system supports DDR4 memory
+	  System supports DDR4 memory
 
-config USE_DDR3
+config DRAM_SUPPORT_DDR3
 	bool
 	default n
 	help
-	  system supports DDR3 memory
+	  System supports DDR3 memory
 
-config USE_DDR2
+config DRAM_SUPPORT_DDR2
 	bool
 	default n
 	help
-	  system supports DDR2 memory
+	  System supports DDR2 memory
diff --git a/src/device/dram/Makefile.mk b/src/device/dram/Makefile.mk
index 7772db2de5..74ef7a054c 100644
--- a/src/device/dram/Makefile.mk
+++ b/src/device/dram/Makefile.mk
@@ -4,18 +4,18 @@ romstage-y += ddr_common.c
 ramstage-y += ddr_common.c
 ramstage-y += spd.c
 
-romstage-$(CONFIG_USE_DDR5) += ddr5.c
-ramstage-$(CONFIG_USE_DDR5) += ddr5.c
+romstage-$(CONFIG_DRAM_SUPPORT_DDR5) += ddr5.c
+ramstage-$(CONFIG_DRAM_SUPPORT_DDR5) += ddr5.c
 
-romstage-$(CONFIG_USE_LPDDR4) += lpddr4.c
-ramstage-$(CONFIG_USE_LPDDR4) += lpddr4.c
+romstage-$(CONFIG_DRAM_SUPPORT_LPDDR4) += lpddr4.c
+ramstage-$(CONFIG_DRAM_SUPPORT_LPDDR4) += lpddr4.c
 
-romstage-$(CONFIG_USE_DDR4) += ddr4.c
-romstage-$(CONFIG_USE_DDR4) += rcd.c
-ramstage-$(CONFIG_USE_DDR4) += ddr4.c
+romstage-$(CONFIG_DRAM_SUPPORT_DDR4) += ddr4.c
+romstage-$(CONFIG_DRAM_SUPPORT_DDR4) += rcd.c
+ramstage-$(CONFIG_DRAM_SUPPORT_DDR4) += ddr4.c
 
-romstage-$(CONFIG_USE_DDR3) += ddr3.c
-ramstage-$(CONFIG_USE_DDR3) += ddr3.c
+romstage-$(CONFIG_DRAM_SUPPORT_DDR3) += ddr3.c
+ramstage-$(CONFIG_DRAM_SUPPORT_DDR3) += ddr3.c
 
-romstage-$(CONFIG_USE_DDR2) += ddr2.c
-ramstage-$(CONFIG_USE_DDR2) += ddr2.c
+romstage-$(CONFIG_DRAM_SUPPORT_DDR2) += ddr2.c
+ramstage-$(CONFIG_DRAM_SUPPORT_DDR2) += ddr2.c
diff --git a/src/mainboard/hardkernel/odroid-h4/Kconfig b/src/mainboard/hardkernel/odroid-h4/Kconfig
index 3e03116db7..146d245dc7 100644
--- a/src/mainboard/hardkernel/odroid-h4/Kconfig
+++ b/src/mainboard/hardkernel/odroid-h4/Kconfig
@@ -15,7 +15,7 @@ config BOARD_SPECIFIC_OPTIONS
 	select SUPERIO_ITE_IT8613E
 	select SOC_INTEL_ALDERLAKE_PCH_N
 	select SOC_INTEL_COMMON_BLOCK_HDA_VERB
-	select USE_DDR5
+	select DRAM_SUPPORT_DDR5
 
 config MAINBOARD_DIR
 	default "hardkernel/odroid-h4"
diff --git a/src/mainboard/protectli/vault_adl_p/Kconfig b/src/mainboard/protectli/vault_adl_p/Kconfig
index b7578ab91b..4cfea63cf2 100644
--- a/src/mainboard/protectli/vault_adl_p/Kconfig
+++ b/src/mainboard/protectli/vault_adl_p/Kconfig
@@ -15,7 +15,7 @@ config BOARD_SPECIFIC_OPTIONS
 	select HAVE_ACPI_TABLES
 	select INTEL_GMA_HAVE_VBT
 	select MEMORY_MAPPED_TPM
-	select USE_DDR5
+	select DRAM_SUPPORT_DDR5
 
 config MAINBOARD_DIR
 	default "protectli/vault_adl_p"
diff --git a/src/northbridge/amd/pi/00730F01/Kconfig b/src/northbridge/amd/pi/00730F01/Kconfig
index 46acb2d59d..3c2829efe7 100644
--- a/src/northbridge/amd/pi/00730F01/Kconfig
+++ b/src/northbridge/amd/pi/00730F01/Kconfig
@@ -2,7 +2,7 @@
 
 config NORTHBRIDGE_AMD_PI_00730F01
 	bool
-	select USE_DDR3
+	select DRAM_SUPPORT_DDR3
 
 if NORTHBRIDGE_AMD_PI_00730F01
 
diff --git a/src/northbridge/intel/gm45/Kconfig b/src/northbridge/intel/gm45/Kconfig
index fef0d735b3..a776217475 100644
--- a/src/northbridge/intel/gm45/Kconfig
+++ b/src/northbridge/intel/gm45/Kconfig
@@ -8,8 +8,8 @@ config NORTHBRIDGE_INTEL_GM45
 	select INTEL_GMA_ACPI
 	select INTEL_GMA_SSC_ALTERNATE_REF
 	select HAVE_X86_64_SUPPORT
-	select USE_DDR3
-	select USE_DDR2
+	select DRAM_SUPPORT_DDR3
+	select DRAM_SUPPORT_DDR2
 	select NEED_SMALL_2MB_PAGE_TABLES
 
 if NORTHBRIDGE_INTEL_GM45
diff --git a/src/northbridge/intel/haswell/Kconfig b/src/northbridge/intel/haswell/Kconfig
index 6191cb6ccf..c57f1ec380 100644
--- a/src/northbridge/intel/haswell/Kconfig
+++ b/src/northbridge/intel/haswell/Kconfig
@@ -6,7 +6,7 @@ config NORTHBRIDGE_INTEL_HASWELL
 	select CACHE_MRC_SETTINGS
 	select INTEL_DDI
 	select INTEL_GMA_ACPI
-	select USE_DDR3
+	select DRAM_SUPPORT_DDR3
 
 if NORTHBRIDGE_INTEL_HASWELL
 
diff --git a/src/northbridge/intel/i945/Kconfig b/src/northbridge/intel/i945/Kconfig
index 32eff1a611..c4e17f90bf 100644
--- a/src/northbridge/intel/i945/Kconfig
+++ b/src/northbridge/intel/i945/Kconfig
@@ -8,7 +8,7 @@ config NORTHBRIDGE_INTEL_I945
 	select INTEL_GMA_SSC_ALTERNATE_REF
 	select INTEL_EDID
 	select HAVE_VGA_TEXT_FRAMEBUFFER if MAINBOARD_DO_NATIVE_VGA_INIT
-	select USE_DDR2
+	select DRAM_SUPPORT_DDR2
 	select NEED_SMALL_2MB_PAGE_TABLES
 
 if NORTHBRIDGE_INTEL_I945
diff --git a/src/northbridge/intel/ironlake/Kconfig b/src/northbridge/intel/ironlake/Kconfig
index 2bafebf92e..39566a6e5f 100644
--- a/src/northbridge/intel/ironlake/Kconfig
+++ b/src/northbridge/intel/ironlake/Kconfig
@@ -8,7 +8,7 @@ config NORTHBRIDGE_INTEL_IRONLAKE
 	select INTEL_GMA_ACPI
 	select CACHE_MRC_SETTINGS
 	select HAVE_DEBUG_RAM_SETUP
-	select USE_DDR3
+	select DRAM_SUPPORT_DDR3
 	select NEED_SMALL_2MB_PAGE_TABLES
 
 if NORTHBRIDGE_INTEL_IRONLAKE
diff --git a/src/northbridge/intel/pineview/Kconfig b/src/northbridge/intel/pineview/Kconfig
index 59cfcd5e0a..a05b866dad 100644
--- a/src/northbridge/intel/pineview/Kconfig
+++ b/src/northbridge/intel/pineview/Kconfig
@@ -8,8 +8,8 @@ config NORTHBRIDGE_INTEL_PINEVIEW
 	select HAVE_VGA_TEXT_FRAMEBUFFER if MAINBOARD_DO_NATIVE_VGA_INIT
 	select INTEL_EDID if MAINBOARD_DO_NATIVE_VGA_INIT
 	select INTEL_GMA_ACPI
-	select USE_DDR3
-	select USE_DDR2
+	select DRAM_SUPPORT_DDR3
+	select DRAM_SUPPORT_DDR2
 	select NEED_SMALL_2MB_PAGE_TABLES
 
 if NORTHBRIDGE_INTEL_PINEVIEW
diff --git a/src/northbridge/intel/sandybridge/Kconfig b/src/northbridge/intel/sandybridge/Kconfig
index 973eed8bbd..9972a43da0 100644
--- a/src/northbridge/intel/sandybridge/Kconfig
+++ b/src/northbridge/intel/sandybridge/Kconfig
@@ -7,7 +7,7 @@ config NORTHBRIDGE_INTEL_SANDYBRIDGE
 	select HAVE_DEBUG_RAM_SETUP
 	select INTEL_GMA_ACPI
 	select NEED_SMALL_2MB_PAGE_TABLES
-	select USE_DDR3
+	select DRAM_SUPPORT_DDR3
 
 if NORTHBRIDGE_INTEL_SANDYBRIDGE
 
diff --git a/src/northbridge/intel/x4x/Kconfig b/src/northbridge/intel/x4x/Kconfig
index 097e11126c..6fa4551957 100644
--- a/src/northbridge/intel/x4x/Kconfig
+++ b/src/northbridge/intel/x4x/Kconfig
@@ -8,8 +8,8 @@ config NORTHBRIDGE_INTEL_X4X
 	select CACHE_MRC_SETTINGS
 	select BOOT_DEVICE_SPI_FLASH_NO_EARLY_WRITES
 	select HAVE_X86_64_SUPPORT
-	select USE_DDR3
-	select USE_DDR2
+	select DRAM_SUPPORT_DDR3
+	select DRAM_SUPPORT_DDR2
 	select NEED_SMALL_2MB_PAGE_TABLES
 
 if NORTHBRIDGE_INTEL_X4X
diff --git a/src/soc/amd/cezanne/Kconfig b/src/soc/amd/cezanne/Kconfig
index 96e4f31e50..ebe96e40d9 100644
--- a/src/soc/amd/cezanne/Kconfig
+++ b/src/soc/amd/cezanne/Kconfig
@@ -80,8 +80,8 @@ config SOC_AMD_CEZANNE
 	select SOC_AMD_COMMON_ROMSTAGE_LEGACY_DMA_FIXUP
 	select SSE2
 	select UDK_2017_BINDING
-	select USE_DDR4
-	select USE_LPDDR4
+	select DRAM_SUPPORT_DDR4
+	select DRAM_SUPPORT_LPDDR4
 	select USE_FSP_NOTIFY_PHASE_POST_PCI_ENUM
 	select USE_FSP_NOTIFY_PHASE_READY_TO_BOOT
 	select USE_FSP_NOTIFY_PHASE_END_OF_FIRMWARE
diff --git a/src/soc/amd/common/fsp/dmi.c b/src/soc/amd/common/fsp/dmi.c
index d132590483..f820e73139 100644
--- a/src/soc/amd/common/fsp/dmi.c
+++ b/src/soc/amd/common/fsp/dmi.c
@@ -23,11 +23,11 @@
  */
 static uint16_t ddr_speed_mhz_to_reported_mts(uint16_t ddr_type, uint16_t speed)
 {
-	if (CONFIG(USE_DDR4) && ddr_type == MEMORY_TYPE_DDR4)
+	if (CONFIG(DRAM_SUPPORT_DDR4) && ddr_type == MEMORY_TYPE_DDR4)
 		return ddr4_speed_mhz_to_reported_mts(speed);
-	else if (CONFIG(USE_LPDDR4) && ddr_type == MEMORY_TYPE_LPDDR4)
+	else if (CONFIG(DRAM_SUPPORT_LPDDR4) && ddr_type == MEMORY_TYPE_LPDDR4)
 		return lpddr4_speed_mhz_to_reported_mts(speed);
-	else if (CONFIG(USE_DDR5) && (ddr_type == MEMORY_TYPE_DDR5 ||
+	else if (CONFIG(DRAM_SUPPORT_DDR5) && (ddr_type == MEMORY_TYPE_DDR5 ||
 			ddr_type == MEMORY_TYPE_LPDDR5))
 		return ddr5_speed_mhz_to_reported_mts(speed);
 
diff --git a/src/soc/amd/glinda/Kconfig b/src/soc/amd/glinda/Kconfig
index 868a984bcc..5cd7e7d1dc 100644
--- a/src/soc/amd/glinda/Kconfig
+++ b/src/soc/amd/glinda/Kconfig
@@ -84,7 +84,7 @@ config SOC_AMD_GLINDA
 	select SOC_FILL_CPU_CACHE_INFO
 	select SSE2
 	select UDK_2017_BINDING
-	select USE_DDR5
+	select DRAM_SUPPORT_DDR5
 	select USE_FSP_NOTIFY_PHASE_POST_PCI_ENUM
 	select USE_FSP_NOTIFY_PHASE_READY_TO_BOOT
 	select USE_FSP_NOTIFY_PHASE_END_OF_FIRMWARE
diff --git a/src/soc/amd/mendocino/Kconfig b/src/soc/amd/mendocino/Kconfig
index 2adb012264..fcbc53b10c 100644
--- a/src/soc/amd/mendocino/Kconfig
+++ b/src/soc/amd/mendocino/Kconfig
@@ -86,7 +86,7 @@ config SOC_AMD_REMBRANDT_BASE
 	select SOC_AMD_COMMON_ROMSTAGE_LEGACY_DMA_FIXUP
 	select SSE2
 	select UDK_2017_BINDING
-	select USE_DDR5
+	select DRAM_SUPPORT_DDR5
 	select USE_FSP_NOTIFY_PHASE_POST_PCI_ENUM
 	select USE_FSP_NOTIFY_PHASE_READY_TO_BOOT
 	select USE_FSP_NOTIFY_PHASE_END_OF_FIRMWARE
diff --git a/src/soc/amd/phoenix/Kconfig b/src/soc/amd/phoenix/Kconfig
index ac227b9f6f..5379baf7dd 100644
--- a/src/soc/amd/phoenix/Kconfig
+++ b/src/soc/amd/phoenix/Kconfig
@@ -73,7 +73,7 @@ config SOC_AMD_PHOENIX_BASE
 	select SOC_AMD_COMMON_BLOCK_XHCI
 	select SOC_AMD_COMMON_ROMSTAGE_LEGACY_DMA_FIXUP
 	select SSE2
-	select USE_DDR5
+	select DRAM_SUPPORT_DDR5
 	select VBOOT_DEFINE_WIDEVINE_COUNTERS if VBOOT_STARTS_BEFORE_BOOTBLOCK
 	select VBOOT_X86_SHA256_ACCELERATION if VBOOT
 	select X86_AMD_FIXED_MTRRS
diff --git a/src/soc/amd/picasso/Kconfig b/src/soc/amd/picasso/Kconfig
index 5678aaf1fb..f85d420697 100644
--- a/src/soc/amd/picasso/Kconfig
+++ b/src/soc/amd/picasso/Kconfig
@@ -70,7 +70,7 @@ config SOC_AMD_PICASSO
 	select SOC_AMD_SUPPORTS_WARM_RESET
 	select SSE2
 	select UDK_2017_BINDING
-	select USE_DDR4
+	select DRAM_SUPPORT_DDR4
 	select USE_FSP_NOTIFY_PHASE_POST_PCI_ENUM
 	select USE_FSP_NOTIFY_PHASE_READY_TO_BOOT
 	select USE_FSP_NOTIFY_PHASE_END_OF_FIRMWARE
diff --git a/src/soc/amd/stoneyridge/Kconfig b/src/soc/amd/stoneyridge/Kconfig
index 47de10290c..2abd9d7985 100644
--- a/src/soc/amd/stoneyridge/Kconfig
+++ b/src/soc/amd/stoneyridge/Kconfig
@@ -46,7 +46,7 @@ config SOC_AMD_STONEYRIDGE
 	select SOC_AMD_COMMON_LATE_SMM_LOCKING
 	select SSE2
 	select TSC_SYNC_LFENCE
-	select USE_DDR4
+	select DRAM_SUPPORT_DDR4
 	select X86_AMD_FIXED_MTRRS
 	help
 	  AMD support for SOCs in Family 15h Models 60h-6Fh and Models 70h-7Fh.
diff --git a/src/soc/intel/baytrail/Kconfig b/src/soc/intel/baytrail/Kconfig
index 09fdbbaae4..1b7770241c 100644
--- a/src/soc/intel/baytrail/Kconfig
+++ b/src/soc/intel/baytrail/Kconfig
@@ -32,7 +32,7 @@ config SOC_INTEL_BAYTRAIL
 	select CPU_INTEL_COMMON
 	select CPU_HAS_L2_ENABLE_MSR
 	select TCO_SPACE_NOT_YET_SPLIT
-	select USE_DDR3
+	select DRAM_SUPPORT_DDR3
 	select NEED_SMALL_2MB_PAGE_TABLES
 	help
 	  Bay Trail M/D part support.
diff --git a/src/soc/intel/snowridge/Kconfig b/src/soc/intel/snowridge/Kconfig
index ad77f9a1ea..afc2f40747 100644
--- a/src/soc/intel/snowridge/Kconfig
+++ b/src/soc/intel/snowridge/Kconfig
@@ -27,7 +27,7 @@ config SOC_INTEL_SNOWRIDGE
 	select ACPI_INTEL_HARDWARE_SLEEP_VALUES
 
 	## Device
-	select USE_DDR4
+	select DRAM_SUPPORT_DDR4
 
 	## Drivers
 	select CACHE_MRC_SETTINGS

From b44c0ab25b256edea6b376abe79ae22878adc416 Mon Sep 17 00:00:00 2001
From: Patrick Rudolph <patrick.rudolph@9elements.com>
Date: Wed, 23 Jul 2025 10:27:13 +0200
Subject: [PATCH 1673/3886] ec/lenovo/pmh7: Include stdbool.h

When moving headers compilation can fail as pmh7.h is missing
the include for type bool. Add the missing include to make sure
future code refactoring works.

Fixed the error:
src/ec/lenovo/pmh7/pmh7.h:27:1: error: unknown type name 'bool'

Change-Id: Ib0a2489a0c461bf021168e98737ecb6062caa696
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88542
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
---
 src/ec/lenovo/pmh7/pmh7.h | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/src/ec/lenovo/pmh7/pmh7.h b/src/ec/lenovo/pmh7/pmh7.h
index 637942641b..61dc1137d3 100644
--- a/src/ec/lenovo/pmh7/pmh7.h
+++ b/src/ec/lenovo/pmh7/pmh7.h
@@ -3,6 +3,8 @@
 #ifndef EC_LENOVO_PMH7_H
 #define EC_LENOVO_PMH7_H
 
+#include <stdbool.h>
+
 #define EC_LENOVO_PMH7_INDEX 0x77
 
 #define EC_LENOVO_PMH7_BASE 0x15e0

From 04cc15feb4106869881f72255eaca2d1f334a66a Mon Sep 17 00:00:00 2001
From: Patrick Rudolph <patrick.rudolph@9elements.com>
Date: Wed, 23 Jul 2025 15:58:03 +0200
Subject: [PATCH 1674/3886] sb/intel/common/pmutil: Drop unused header

Change-Id: Ic63668eb741d96f0d28e3657c0b1c9a683ade272
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88544
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
---
 src/southbridge/intel/common/pmutil.c | 1 -
 1 file changed, 1 deletion(-)

diff --git a/src/southbridge/intel/common/pmutil.c b/src/southbridge/intel/common/pmutil.c
index 8ecb74c371..9dbbc100ca 100644
--- a/src/southbridge/intel/common/pmutil.c
+++ b/src/southbridge/intel/common/pmutil.c
@@ -4,7 +4,6 @@
 #include <console/console.h>
 #include <device/pci_def.h>
 #include <southbridge/intel/common/pmbase.h>
-#include <southbridge/intel/common/gpio.h>
 
 #include "pmutil.h"
 

From 6a20caea01c5c72a4e57217990ac6aacdc6b7724 Mon Sep 17 00:00:00 2001
From: Patrick Rudolph <patrick.rudolph@9elements.com>
Date: Wed, 23 Jul 2025 18:07:52 +0200
Subject: [PATCH 1675/3886] drivers/lenovo/hybrid_graphics: Add missing header

Include the missing header stdbool.h

Fixes compilation error
hybrid_graphics.h:6:28: error: unknown type name 'bool'
while refactoring some code.

Change-Id: I96f7255049cd9e24d74838a173e920a00636b09e
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88546
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/drivers/lenovo/hybrid_graphics/hybrid_graphics.h | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/src/drivers/lenovo/hybrid_graphics/hybrid_graphics.h b/src/drivers/lenovo/hybrid_graphics/hybrid_graphics.h
index b5de8a8566..d69486575d 100644
--- a/src/drivers/lenovo/hybrid_graphics/hybrid_graphics.h
+++ b/src/drivers/lenovo/hybrid_graphics/hybrid_graphics.h
@@ -3,6 +3,8 @@
 #ifndef _DRIVERS_LENOVO_HYBRID_GRAPHICS_H_
 #define _DRIVERS_LENOVO_HYBRID_GRAPHICS_H_
 
+#include <stdbool.h>
+
 void early_hybrid_graphics(bool *enable_igd, bool *enable_peg);
 
 #endif /* _DRIVERS_LENOVO_HYBRID_GRAPHICS_CHIP_H_ */

From 2d7891abe2b01a82bc19c17d4e98f849db25e46d Mon Sep 17 00:00:00 2001
From: Patrick Rudolph <patrick.rudolph@9elements.com>
Date: Sun, 13 Jul 2025 12:03:05 +0200
Subject: [PATCH 1676/3886] sb/intel: Add soc/gpio.h

In order to use the common gpio.h header file typedef gpio_t in
soc/gpio.h for Intel common code, Intel lynxpoint and Intel broadwell.

Change-Id: I2049a2cfd75c60d00bdd564b294808760b6aff7f
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88502
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
---
 src/soc/intel/broadwell/include/soc/gpio.h         | 10 ++++++++++
 src/southbridge/intel/common/Makefile.mk           |  6 ++++++
 src/southbridge/intel/common/gpio.h                |  4 +---
 src/southbridge/intel/common/include/soc/gpio.h    | 13 +++++++++++++
 src/southbridge/intel/lynxpoint/include/soc/gpio.h | 10 ++++++++++
 5 files changed, 40 insertions(+), 3 deletions(-)
 create mode 100644 src/soc/intel/broadwell/include/soc/gpio.h
 create mode 100644 src/southbridge/intel/common/include/soc/gpio.h
 create mode 100644 src/southbridge/intel/lynxpoint/include/soc/gpio.h

diff --git a/src/soc/intel/broadwell/include/soc/gpio.h b/src/soc/intel/broadwell/include/soc/gpio.h
new file mode 100644
index 0000000000..8cd1e1fa79
--- /dev/null
+++ b/src/soc/intel/broadwell/include/soc/gpio.h
@@ -0,0 +1,10 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef _BROADWELL_GPIO_H_
+#define _BROADWELL_GPIO_H_
+
+#include <stdint.h>
+
+typedef uint32_t gpio_t;
+
+#endif /* _BROADWELL_GPIO_H_ */
diff --git a/src/southbridge/intel/common/Makefile.mk b/src/southbridge/intel/common/Makefile.mk
index 2f4c777561..39cb1b985e 100644
--- a/src/southbridge/intel/common/Makefile.mk
+++ b/src/southbridge/intel/common/Makefile.mk
@@ -53,3 +53,9 @@ smm-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMM) += pmutil.c smihandler.c
 smm-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_FINALIZE) += finalize.c
 
 all-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_RTC) += rtc.c
+
+ifeq ($(CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO),y)
+
+CPPFLAGS_common += -I$(src)/southbridge/intel/common/include
+
+endif
diff --git a/src/southbridge/intel/common/gpio.h b/src/southbridge/intel/common/gpio.h
index 687886525f..6dd2acbacc 100644
--- a/src/southbridge/intel/common/gpio.h
+++ b/src/southbridge/intel/common/gpio.h
@@ -4,6 +4,7 @@
 #define INTEL_COMMON_GPIO_H
 
 #include <stdint.h>
+#include <soc/gpio.h>
 
 /* ICH7 GPIOBASE */
 #define GPIO_USE_SEL	0x00
@@ -31,9 +32,6 @@
 #define GPIO_NO_INVERT		0
 #define GPIO_INVERT		1
 
-#define GPIO_LEVEL_LOW		0
-#define GPIO_LEVEL_HIGH		1
-
 #define GPIO_NO_BLINK		0
 #define GPIO_BLINK		1
 
diff --git a/src/southbridge/intel/common/include/soc/gpio.h b/src/southbridge/intel/common/include/soc/gpio.h
new file mode 100644
index 0000000000..1e9d4a63b8
--- /dev/null
+++ b/src/southbridge/intel/common/include/soc/gpio.h
@@ -0,0 +1,13 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef SB_INTEL_COMMON_GPIO_BANKS_H
+#define SB_INTEL_COMMON_GPIO_BANKS_H
+
+#include <stdint.h>
+
+typedef uint32_t gpio_t;
+
+#define GPIO_LEVEL_LOW		0
+#define GPIO_LEVEL_HIGH		1
+
+#endif /* SB_INTEL_COMMON_GPIO_BANKS_H */
diff --git a/src/southbridge/intel/lynxpoint/include/soc/gpio.h b/src/southbridge/intel/lynxpoint/include/soc/gpio.h
new file mode 100644
index 0000000000..9f869ff077
--- /dev/null
+++ b/src/southbridge/intel/lynxpoint/include/soc/gpio.h
@@ -0,0 +1,10 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef SB_INTEL_LYNXPOINT_GPIO_BANKS_H
+#define SB_INTEL_LYNXPOINT_GPIO_BANKS_H
+
+#include <stdint.h>
+
+typedef uint32_t gpio_t;
+
+#endif /* SB_INTEL_LYNXPOINT_GPIO_BANKS_H */

From 69364fc9e0f57b9feb17b30e8d94ecb151d2b585 Mon Sep 17 00:00:00 2001
From: Patrick Rudolph <patrick.rudolph@9elements.com>
Date: Mon, 21 Jul 2025 08:19:39 +0200
Subject: [PATCH 1677/3886] sb/intel: Convert get_gpio() to gpio_get()

Drop the custom function to set the value of a single GPIO and
use the generic function prototype defined in include/gpio.h instead.

Migrate all users of the old function to the new function.

Allows to share more code between older x86 Intel boards and newer
x86 Intel boards since they now use a common header.

Change-Id: I714eaf2115a455d327e6b2313dafd0e293bee8a7
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88506
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
---
 .../lenovo/hybrid_graphics/hybrid_graphics.c  | 10 +++---
 src/drivers/lenovo/hybrid_graphics/romstage.c | 14 ++++----
 src/ec/lenovo/h8/bluetooth.c                  |  4 +--
 src/ec/lenovo/h8/wwan.c                       |  4 +--
 src/mainboard/dell/optiplex_9020/mainboard.c  |  6 ++--
 .../dell/snb_ivb_workstations/mainboard.c     | 34 +++++++++----------
 .../dell/snb_ivb_workstations/sch5545_ec.c    | 10 +++---
 src/mainboard/google/auron/chromeos.c         |  6 ++--
 src/mainboard/google/beltino/chromeos.c       |  6 ++--
 src/mainboard/google/butterfly/chromeos.c     |  5 ++-
 src/mainboard/google/jecht/chromeos.c         |  6 ++--
 src/mainboard/google/link/chromeos.c          |  6 ++--
 src/mainboard/google/parrot/chromeos.c        |  9 +++--
 src/mainboard/google/slippy/chromeos.c        |  6 ++--
 src/mainboard/google/stout/chromeos.c         |  5 ++-
 src/mainboard/intel/baskingridge/chromeos.c   |  6 ++--
 src/mainboard/intel/dcp847ske/mainboard.c     |  8 ++---
 src/mainboard/intel/emeraldlake2/chromeos.c   |  6 ++--
 src/mainboard/lenovo/t400/romstage.c          |  7 ++--
 .../lenovo/x1_carbon_gen1/early_init.c        |  2 +-
 src/mainboard/samsung/lumpy/chromeos.c        |  6 ++--
 src/mainboard/samsung/stumpy/chromeos.c       |  6 ++--
 src/southbridge/intel/common/gpio.c           |  7 ++--
 src/southbridge/intel/common/gpio.h           |  2 --
 src/southbridge/intel/lynxpoint/lp_gpio.c     |  5 +--
 src/southbridge/intel/lynxpoint/lp_gpio.h     |  3 --
 26 files changed, 92 insertions(+), 97 deletions(-)

diff --git a/src/drivers/lenovo/hybrid_graphics/hybrid_graphics.c b/src/drivers/lenovo/hybrid_graphics/hybrid_graphics.c
index 1fda1fd7ea..ebd7efccac 100644
--- a/src/drivers/lenovo/hybrid_graphics/hybrid_graphics.c
+++ b/src/drivers/lenovo/hybrid_graphics/hybrid_graphics.c
@@ -1,10 +1,10 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
-#include <option.h>
-#include <device/device.h>
-
-#include <southbridge/intel/common/gpio.h>
 #include <console/console.h>
+#include <device/device.h>
+#include <gpio.h>
+#include <option.h>
+#include <southbridge/intel/common/gpio.h>
 #include "chip.h"
 
 /*
@@ -20,7 +20,7 @@ static void lenovo_hybrid_graphics_enable(struct device *dev)
 	dev->enabled = 0;
 
 	config = dev->chip_info;
-	if (!config || (get_gpio(config->detect_gpio) == DGPU_NOT_INSTALLED)) {
+	if (!config || (gpio_get(config->detect_gpio) == DGPU_NOT_INSTALLED)) {
 		printk(BIOS_DEBUG, "Hybrid graphics: Not installed\n");
 		return;
 	}
diff --git a/src/drivers/lenovo/hybrid_graphics/romstage.c b/src/drivers/lenovo/hybrid_graphics/romstage.c
index 7cc1610e1d..b28237c8c3 100644
--- a/src/drivers/lenovo/hybrid_graphics/romstage.c
+++ b/src/drivers/lenovo/hybrid_graphics/romstage.c
@@ -1,12 +1,12 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
-#include <types.h>
-#include <option.h>
-#include <device/device.h>
-
-#include <southbridge/intel/common/gpio.h>
-#include <ec/lenovo/pmh7/pmh7.h>
 #include <console/console.h>
+#include <device/device.h>
+#include <ec/lenovo/pmh7/pmh7.h>
+#include <option.h>
+#include <gpio.h>
+#include <types.h>
+#include <southbridge/intel/common/gpio.h>
 
 #include "hybrid_graphics.h"
 #include "chip.h"
@@ -31,7 +31,7 @@ void early_hybrid_graphics(bool *enable_igd, bool *enable_peg)
 	}
 
 	config = dev->chip_info;
-	if (get_gpio(config->detect_gpio) == DGPU_NOT_INSTALLED) {
+	if (gpio_get(config->detect_gpio) == DGPU_NOT_INSTALLED) {
 		printk(BIOS_DEBUG, "Hybrid graphics:"
 		       " No discrete GPU present.\n");
 		*enable_igd = true;
diff --git a/src/ec/lenovo/h8/bluetooth.c b/src/ec/lenovo/h8/bluetooth.c
index aa5fc5814f..166b3fb01e 100644
--- a/src/ec/lenovo/h8/bluetooth.c
+++ b/src/ec/lenovo/h8/bluetooth.c
@@ -1,9 +1,9 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
-#include <southbridge/intel/common/gpio.h>
 #include <console/console.h>
 #include <device/device.h>
 #include <ec/acpi/ec.h>
+#include <gpio.h>
 #include <option.h>
 #include <types.h>
 
@@ -34,7 +34,7 @@ bool h8_has_bdc(const struct device *dev)
 		return true;
 	}
 
-	if (get_gpio(conf->bdc_gpio_num) == conf->bdc_gpio_lvl) {
+	if (gpio_get(conf->bdc_gpio_num) == conf->bdc_gpio_lvl) {
 		printk(BIOS_INFO, "H8: BDC installed\n");
 		return true;
 	}
diff --git a/src/ec/lenovo/h8/wwan.c b/src/ec/lenovo/h8/wwan.c
index 3eea9541ec..edb76659f0 100644
--- a/src/ec/lenovo/h8/wwan.c
+++ b/src/ec/lenovo/h8/wwan.c
@@ -1,9 +1,9 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
-#include <southbridge/intel/common/gpio.h>
 #include <console/console.h>
 #include <device/device.h>
 #include <ec/acpi/ec.h>
+#include <gpio.h>
 #include <option.h>
 #include <types.h>
 
@@ -32,7 +32,7 @@ bool h8_has_wwan(const struct device *dev)
 		return true;
 	}
 
-	if (get_gpio(conf->wwan_gpio_num) == conf->wwan_gpio_lvl) {
+	if (gpio_get(conf->wwan_gpio_num) == conf->wwan_gpio_lvl) {
 		printk(BIOS_INFO, "H8: WWAN installed\n");
 		return true;
 	}
diff --git a/src/mainboard/dell/optiplex_9020/mainboard.c b/src/mainboard/dell/optiplex_9020/mainboard.c
index 1cb850c46c..733efbb729 100644
--- a/src/mainboard/dell/optiplex_9020/mainboard.c
+++ b/src/mainboard/dell/optiplex_9020/mainboard.c
@@ -4,8 +4,8 @@
 #include <cpu/x86/msr.h>
 #include <device/device.h>
 #include <drivers/intel/gma/int15.h>
+#include <gpio.h>
 #include <option.h>
-#include <southbridge/intel/common/gpio.h>
 #include "sch5555_ec.h"
 
 static void mainboard_enable(struct device *dev)
@@ -269,8 +269,8 @@ static uint8_t get_chassis_type(void)
 	uint8_t gpio_chassis_type;
 
 	// Read chassis type from GPIO
-	gpio_chassis_type = get_gpio(70) << 3 | get_gpio(38) << 2 |
-			    get_gpio(17) << 1 | get_gpio(1);
+	gpio_chassis_type = gpio_get(70) << 3 | gpio_get(38) << 2 |
+	gpio_get(17) << 1 | gpio_get(1);
 
 	printk(BIOS_DEBUG, "GPIO chassis type = %#x\n", gpio_chassis_type);
 
diff --git a/src/mainboard/dell/snb_ivb_workstations/mainboard.c b/src/mainboard/dell/snb_ivb_workstations/mainboard.c
index c32121112a..2c09e683dd 100644
--- a/src/mainboard/dell/snb_ivb_workstations/mainboard.c
+++ b/src/mainboard/dell/snb_ivb_workstations/mainboard.c
@@ -5,8 +5,8 @@
 #include <device/device.h>
 #include <device/pci_ops.h>
 #include <drivers/intel/gma/int15.h>
+#include <gpio.h>
 #include <southbridge/intel/bd82x6x/pch.h>
-#include <southbridge/intel/common/gpio.h>
 #include <superio/smsc/sch5545/sch5545.h>
 
 #include <baseboard/sch5545_ec.h>
@@ -56,10 +56,10 @@ static void mainboard_enable(struct device *dev)
 					GMA_INT15_PANEL_FIT_DEFAULT,
 					GMA_INT15_BOOT_DISPLAY_DEFAULT, 0);
 
-	pin_sts = get_gpio(GPIO_CHASSIS_ID0);
-	pin_sts |= get_gpio(GPIO_CHASSIS_ID1) << 1;
-	pin_sts |= get_gpio(GPIO_CHASSIS_ID2) << 2;
-	pin_sts |= get_gpio(GPIO_FRONT_PANEL_CHASSIS_DET_L) << 3;
+	pin_sts = gpio_get(GPIO_CHASSIS_ID0);
+	pin_sts |= gpio_get(GPIO_CHASSIS_ID1) << 1;
+	pin_sts |= gpio_get(GPIO_CHASSIS_ID2) << 2;
+	pin_sts |= gpio_get(GPIO_FRONT_PANEL_CHASSIS_DET_L) << 3;
 
 	printk(BIOS_DEBUG, "Chassis type: ");
 	switch (pin_sts) {
@@ -88,15 +88,15 @@ static void mainboard_enable(struct device *dev)
 		break;
 	}
 
-	pin_sts = get_gpio(GPIO_BOARD_REV0);
-	pin_sts |= get_gpio(GPIO_BOARD_REV1) << 1;
-	pin_sts |= get_gpio(GPIO_BOARD_REV2) << 2;
+	pin_sts = gpio_get(GPIO_BOARD_REV0);
+	pin_sts |= gpio_get(GPIO_BOARD_REV1) << 1;
+	pin_sts |= gpio_get(GPIO_BOARD_REV2) << 2;
 
 	printk(BIOS_DEBUG, "Board revision: %d\n", pin_sts);
 
-	pin_sts = get_gpio(GPIO_SKU0);
-	pin_sts |= get_gpio(GPIO_SKU1) << 1;
-	pin_sts |= get_gpio(GPIO_SKU2) << 2;
+	pin_sts = gpio_get(GPIO_SKU0);
+	pin_sts |= gpio_get(GPIO_SKU1) << 1;
+	pin_sts |= gpio_get(GPIO_SKU2) << 2;
 
 	printk(BIOS_DEBUG, "SKU ID is %d:", pin_sts);
 	switch (pin_sts) {
@@ -115,15 +115,15 @@ static void mainboard_enable(struct device *dev)
 	}
 
 	printk(BIOS_DEBUG, "VGA cable %sconnected\n",
-	       get_gpio(GPIO_VGA_CABLE_DET_L) ? "dis" : "");
+	       gpio_get(GPIO_VGA_CABLE_DET_L) ? "dis" : "");
 
 	printk(BIOS_DEBUG, "Flexbay %sattached to internal USB 2.0 header\n",
-	       get_gpio(FLEXBAY_HEADER_CABLE_DET_L) ? "not " : "");
+	       gpio_get(FLEXBAY_HEADER_CABLE_DET_L) ? "not " : "");
 
 	printk(BIOS_DEBUG, "Password clear jumper %sactive\n",
-	       get_gpio(GPIO_PSWD_CLR) ? "in" : "");
+	       gpio_get(GPIO_PSWD_CLR) ? "in" : "");
 
-	if (!get_gpio(GPIO_FRONT_PANEL_PRESENT_L)) {
+	if (!gpio_get(GPIO_FRONT_PANEL_PRESENT_L)) {
 		printk(BIOS_DEBUG, "Front panel cable connected\n");
 	} else {
 		printk(BIOS_WARNING, "Front panel cable not connected!\n");
@@ -132,7 +132,7 @@ static void mainboard_enable(struct device *dev)
 		printk(BIOS_WARNING, "Check the front panel cable!\n");
 	}
 
-	if (!get_gpio(GPIO_INTRUDER_CABLE_DET_L)) {
+	if (!gpio_get(GPIO_INTRUDER_CABLE_DET_L)) {
 		printk(BIOS_DEBUG, "Intruder cable connected\n");
 	} else {
 		printk(BIOS_WARNING, "Intruder cable not connected!\n");
@@ -140,7 +140,7 @@ static void mainboard_enable(struct device *dev)
 		printk(BIOS_WARNING, "Check the intruder cable!\n");
 	}
 
-	if (!get_gpio(GPIO_USB_HEADER_DET_L)) {
+	if (!gpio_get(GPIO_USB_HEADER_DET_L)) {
 		printk(BIOS_DEBUG, "Front USB 3.0 cable connected\n");
 	} else {
 		printk(BIOS_WARNING, "Front USB 3.0 cable not connected!\n");
diff --git a/src/mainboard/dell/snb_ivb_workstations/sch5545_ec.c b/src/mainboard/dell/snb_ivb_workstations/sch5545_ec.c
index a68f285a98..a32c0fc937 100644
--- a/src/mainboard/dell/snb_ivb_workstations/sch5545_ec.c
+++ b/src/mainboard/dell/snb_ivb_workstations/sch5545_ec.c
@@ -6,7 +6,7 @@
 #include <cpu/x86/msr.h>
 #include <console/console.h>
 #include <cpu/intel/model_206ax/model_206ax.h>
-#include <southbridge/intel/common/gpio.h>
+#include <gpio.h>
 #include <superio/smsc/sch5545/sch5545.h>
 #include <superio/smsc/sch5545/sch5545_emi.h>
 
@@ -300,10 +300,10 @@ static uint8_t get_chassis_type(void)
 {
 	uint8_t chassis_id;
 
-	chassis_id  = get_gpio(GPIO_CHASSIS_ID0);
-	chassis_id |= get_gpio(GPIO_CHASSIS_ID1) << 1;
-	chassis_id |= get_gpio(GPIO_CHASSIS_ID2) << 2;
-	chassis_id |= get_gpio(GPIO_FRONT_PANEL_CHASSIS_DET_L) << 3;
+	chassis_id  = gpio_get(GPIO_CHASSIS_ID0);
+	chassis_id |= gpio_get(GPIO_CHASSIS_ID1) << 1;
+	chassis_id |= gpio_get(GPIO_CHASSIS_ID2) << 2;
+	chassis_id |= gpio_get(GPIO_FRONT_PANEL_CHASSIS_DET_L) << 3;
 
 	/* This mapping will determine which EC init sequence to use */
 	switch (chassis_id) {
diff --git a/src/mainboard/google/auron/chromeos.c b/src/mainboard/google/auron/chromeos.c
index 84940e2f5c..f958098107 100644
--- a/src/mainboard/google/auron/chromeos.c
+++ b/src/mainboard/google/auron/chromeos.c
@@ -2,10 +2,10 @@
 
 #include <bootmode.h>
 #include <boot/coreboot_tables.h>
+#include <gpio.h>
 #include <types.h>
 #include <vendorcode/google/chromeos/chromeos.h>
 #include <soc/chromeos.h>
-#include <southbridge/intel/lynxpoint/lp_gpio.h>
 
 #include "onboard.h"
 
@@ -28,7 +28,7 @@ void fill_lb_gpios(struct lb_gpios *gpios)
 
 int get_write_protect_state(void)
 {
-	return get_gpio(CROS_WP_GPIO);
+	return gpio_get(CROS_WP_GPIO);
 }
 
 static const struct cros_gpio cros_gpios[] = {
@@ -40,5 +40,5 @@ DECLARE_CROS_GPIOS(cros_gpios);
 int get_ec_is_trusted(void)
 {
 	/* EC is trusted if not in RW. */
-	return !get_gpio(EC_IN_RW_GPIO);
+	return !gpio_get(EC_IN_RW_GPIO);
 }
diff --git a/src/mainboard/google/beltino/chromeos.c b/src/mainboard/google/beltino/chromeos.c
index 0e0189549e..30cba96c39 100644
--- a/src/mainboard/google/beltino/chromeos.c
+++ b/src/mainboard/google/beltino/chromeos.c
@@ -3,8 +3,8 @@
 #include <bootmode.h>
 #include <boot/coreboot_tables.h>
 #include <device/device.h>
+#include <gpio.h>
 #include <southbridge/intel/lynxpoint/pch.h>
-#include <southbridge/intel/common/gpio.h>
 #include <types.h>
 #include <vendorcode/google/chromeos/chromeos.h>
 #include "onboard.h"
@@ -23,12 +23,12 @@ void fill_lb_gpios(struct lb_gpios *gpios)
 
 int get_write_protect_state(void)
 {
-	return get_gpio(GPIO_SPI_WP);
+	return gpio_get(GPIO_SPI_WP);
 }
 
 int get_recovery_mode_switch(void)
 {
-	return !get_gpio(GPIO_REC_MODE);
+	return !gpio_get(GPIO_REC_MODE);
 }
 
 static const struct cros_gpio cros_gpios[] = {
diff --git a/src/mainboard/google/butterfly/chromeos.c b/src/mainboard/google/butterfly/chromeos.c
index 595b2ca22e..cbb54ecf10 100644
--- a/src/mainboard/google/butterfly/chromeos.c
+++ b/src/mainboard/google/butterfly/chromeos.c
@@ -3,9 +3,8 @@
 #include <bootmode.h>
 #include <boot/coreboot_tables.h>
 #include <device/device.h>
-
+#include <gpio.h>
 #include <southbridge/intel/bd82x6x/pch.h>
-#include <southbridge/intel/common/gpio.h>
 #include <ec/quanta/ene_kb3940q/ec.h>
 #include <types.h>
 #include <vendorcode/google/chromeos/chromeos.h>
@@ -31,7 +30,7 @@ void fill_lb_gpios(struct lb_gpios *gpios)
 
 int get_write_protect_state(void)
 {
-	return !get_gpio(WP_GPIO);
+	return !gpio_get(WP_GPIO);
 }
 
 int get_lid_switch(void)
diff --git a/src/mainboard/google/jecht/chromeos.c b/src/mainboard/google/jecht/chromeos.c
index 563e32b79c..7c1b953b0c 100644
--- a/src/mainboard/google/jecht/chromeos.c
+++ b/src/mainboard/google/jecht/chromeos.c
@@ -4,10 +4,10 @@
 #include <boot/coreboot_tables.h>
 #include <device/pci_ops.h>
 #include <device/device.h>
+#include <gpio.h>
 #include <types.h>
 #include <vendorcode/google/chromeos/chromeos.h>
 #include <soc/chromeos.h>
-#include <southbridge/intel/lynxpoint/lp_gpio.h>
 #include "onboard.h"
 
 void fill_lb_gpios(struct lb_gpios *gpios)
@@ -24,12 +24,12 @@ void fill_lb_gpios(struct lb_gpios *gpios)
 
 int get_write_protect_state(void)
 {
-	return get_gpio(GPIO_SPI_WP);
+	return gpio_get(GPIO_SPI_WP);
 }
 
 int get_recovery_mode_switch(void)
 {
-	return !get_gpio(GPIO_REC_MODE);
+	return !gpio_get(GPIO_REC_MODE);
 }
 
 static const struct cros_gpio cros_gpios[] = {
diff --git a/src/mainboard/google/link/chromeos.c b/src/mainboard/google/link/chromeos.c
index 8c6749b4d4..da25d9b23e 100644
--- a/src/mainboard/google/link/chromeos.c
+++ b/src/mainboard/google/link/chromeos.c
@@ -2,8 +2,8 @@
 
 #include <bootmode.h>
 #include <boot/coreboot_tables.h>
+#include <gpio.h>
 #include <southbridge/intel/bd82x6x/pch.h>
-#include <southbridge/intel/common/gpio.h>
 #include <types.h>
 #include <vendorcode/google/chromeos/chromeos.h>
 #include "onboard.h"
@@ -29,7 +29,7 @@ void fill_lb_gpios(struct lb_gpios *gpios)
 
 int get_write_protect_state(void)
 {
-	return get_gpio(GPIO_SPI_WP);
+	return gpio_get(GPIO_SPI_WP);
 }
 
 static const struct cros_gpio cros_gpios[] = {
@@ -41,5 +41,5 @@ DECLARE_CROS_GPIOS(cros_gpios);
 int get_ec_is_trusted(void)
 {
 	/* EC is trusted if not in RW. */
-	return !get_gpio(GPIO_EC_IN_RW);
+	return !gpio_get(GPIO_EC_IN_RW);
 }
diff --git a/src/mainboard/google/parrot/chromeos.c b/src/mainboard/google/parrot/chromeos.c
index 10314f517f..a0ad19313f 100644
--- a/src/mainboard/google/parrot/chromeos.c
+++ b/src/mainboard/google/parrot/chromeos.c
@@ -4,9 +4,8 @@
 #include <boot/coreboot_tables.h>
 #include <device/pci_ops.h>
 #include <device/device.h>
-
+#include <gpio.h>
 #include <southbridge/intel/bd82x6x/pch.h>
-#include <southbridge/intel/common/gpio.h>
 #include <types.h>
 #include <vendorcode/google/chromeos/chromeos.h>
 
@@ -33,17 +32,17 @@ void fill_lb_gpios(struct lb_gpios *gpios)
 
 int get_lid_switch(void)
 {
-	return get_gpio(GPIO_LID);
+	return gpio_get(GPIO_LID);
 }
 
 int get_write_protect_state(void)
 {
-	return !get_gpio(GPIO_SPI_WP);
+	return !gpio_get(GPIO_SPI_WP);
 }
 
 int get_recovery_mode_switch(void)
 {
-	return !get_gpio(GPIO_REC_MODE);
+	return !gpio_get(GPIO_REC_MODE);
 }
 
 static const struct cros_gpio cros_gpios[] = {
diff --git a/src/mainboard/google/slippy/chromeos.c b/src/mainboard/google/slippy/chromeos.c
index ddc6e3a876..60f5fd62ad 100644
--- a/src/mainboard/google/slippy/chromeos.c
+++ b/src/mainboard/google/slippy/chromeos.c
@@ -2,8 +2,8 @@
 
 #include <bootmode.h>
 #include <boot/coreboot_tables.h>
+#include <gpio.h>
 #include <southbridge/intel/lynxpoint/pch.h>
-#include <southbridge/intel/common/gpio.h>
 #include <types.h>
 #include <vendorcode/google/chromeos/chromeos.h>
 #include "onboard.h"
@@ -20,7 +20,7 @@ void fill_lb_gpios(struct lb_gpios *gpios)
 
 int get_write_protect_state(void)
 {
-	return get_gpio(GPIO_SPI_WP);
+	return gpio_get(GPIO_SPI_WP);
 }
 
 static const struct cros_gpio cros_gpios[] = {
@@ -32,5 +32,5 @@ DECLARE_CROS_GPIOS(cros_gpios);
 int get_ec_is_trusted(void)
 {
 	/* EC is trusted if not in RW. */
-	return !get_gpio(14);
+	return !gpio_get(14);
 }
diff --git a/src/mainboard/google/stout/chromeos.c b/src/mainboard/google/stout/chromeos.c
index 8abdb67cbf..39dbb6fe17 100644
--- a/src/mainboard/google/stout/chromeos.c
+++ b/src/mainboard/google/stout/chromeos.c
@@ -5,9 +5,8 @@
 #include <device/pci_ops.h>
 #include <console/console.h>
 #include <device/device.h>
-
+#include <gpio.h>
 #include <southbridge/intel/bd82x6x/pch.h>
-#include <southbridge/intel/common/gpio.h>
 #include <types.h>
 #include <vendorcode/google/chromeos/chromeos.h>
 #include "ec.h"
@@ -36,7 +35,7 @@ void fill_lb_gpios(struct lb_gpios *gpios)
 
 int get_write_protect_state(void)
 {
-	return !get_gpio(GPIO_SPI_WP);
+	return !gpio_get(GPIO_SPI_WP);
 }
 
 int get_lid_switch(void)
diff --git a/src/mainboard/intel/baskingridge/chromeos.c b/src/mainboard/intel/baskingridge/chromeos.c
index e82edeba04..73dfc7ae2d 100644
--- a/src/mainboard/intel/baskingridge/chromeos.c
+++ b/src/mainboard/intel/baskingridge/chromeos.c
@@ -3,8 +3,8 @@
 #include <bootmode.h>
 #include <boot/coreboot_tables.h>
 #include <device/device.h>
+#include <gpio.h>
 #include <southbridge/intel/lynxpoint/pch.h>
-#include <southbridge/intel/common/gpio.h>
 #include <types.h>
 #include <vendorcode/google/chromeos/chromeos.h>
 #include "onboard.h"
@@ -33,13 +33,13 @@ int get_recovery_mode_switch(void)
 	 * Recovery: GPIO69, Connected to J8E3, however the silkscreen says
 	 * J8E2. The jump is active high.
 	 */
-	return get_gpio(GPIO_REC_MODE);
+	return gpio_get(GPIO_REC_MODE);
 }
 
 int get_write_protect_state(void)
 {
 	/* Write protect is active low, so invert it here */
-	return !get_gpio(GPIO_SPI_WP);
+	return !gpio_get(GPIO_SPI_WP);
 }
 
 static const struct cros_gpio cros_gpios[] = {
diff --git a/src/mainboard/intel/dcp847ske/mainboard.c b/src/mainboard/intel/dcp847ske/mainboard.c
index d279ac6ade..4df5b33944 100644
--- a/src/mainboard/intel/dcp847ske/mainboard.c
+++ b/src/mainboard/intel/dcp847ske/mainboard.c
@@ -3,16 +3,16 @@
 #include <console/console.h>
 #include <device/device.h>
 #include <drivers/intel/gma/int15.h>
-#include <southbridge/intel/common/gpio.h>
+#include <gpio.h>
 
 static void mainboard_enable(struct device *dev)
 {
 	printk(BIOS_DEBUG, "Memory voltage: %s\n",
-		get_gpio(8) ? "1.35V" : "1.5V");
+		gpio_get(8) ? "1.35V" : "1.5V");
 	printk(BIOS_DEBUG, "BIOS_CFG jumper: %s\n",
-		get_gpio(22) ? "normal (1-2)" : "setup (2-3)");
+		gpio_get(22) ? "normal (1-2)" : "setup (2-3)");
 	printk(BIOS_DEBUG, "mSATA: %s\n",
-		get_gpio(35) ? "present" : "absent");
+		gpio_get(35) ? "present" : "absent");
 
 	install_intel_vga_int15_handler(
 		GMA_INT15_ACTIVE_LFP_NONE, GMA_INT15_PANEL_FIT_DEFAULT,
diff --git a/src/mainboard/intel/emeraldlake2/chromeos.c b/src/mainboard/intel/emeraldlake2/chromeos.c
index 727258ebbc..370fd21456 100644
--- a/src/mainboard/intel/emeraldlake2/chromeos.c
+++ b/src/mainboard/intel/emeraldlake2/chromeos.c
@@ -3,8 +3,8 @@
 #include <bootmode.h>
 #include <boot/coreboot_tables.h>
 #include <device/device.h>
+#include <gpio.h>
 #include <southbridge/intel/bd82x6x/pch.h>
-#include <southbridge/intel/common/gpio.h>
 #include <types.h>
 #include <vendorcode/google/chromeos/chromeos.h>
 #include "onboard.h"
@@ -30,13 +30,13 @@ void fill_lb_gpios(struct lb_gpios *gpios)
 int get_recovery_mode_switch(void)
 {
 	/* Recovery: GPIO22, active low */
-	return !get_gpio(GPIO_REC_MODE);
+	return !gpio_get(GPIO_REC_MODE);
 }
 
 int get_write_protect_state(void)
 {
 	/* Write protect is active low, so invert it here */
-	return !get_gpio(GPIO_SPI_WP);
+	return !gpio_get(GPIO_SPI_WP);
 }
 
 static const struct cros_gpio cros_gpios[] = {
diff --git a/src/mainboard/lenovo/t400/romstage.c b/src/mainboard/lenovo/t400/romstage.c
index 89afaeed20..850116aad2 100644
--- a/src/mainboard/lenovo/t400/romstage.c
+++ b/src/mainboard/lenovo/t400/romstage.c
@@ -1,9 +1,10 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
 #include <console/console.h>
-#include <southbridge/intel/common/gpio.h>
-#include <northbridge/intel/gm45/gm45.h>
 #include <drivers/lenovo/hybrid_graphics/hybrid_graphics.h>
+#include <gpio.h>
+#include <northbridge/intel/gm45/gm45.h>
+#include <southbridge/intel/common/gpio.h>
 
 static void hybrid_graphics_init(sysinfo_t *sysinfo)
 {
@@ -24,7 +25,7 @@ void get_mb_spd_addrmap(u8 spd_addrmap[4])
 void mb_pre_raminit_setup(sysinfo_t *sysinfo)
 {
 	if (CONFIG(BOARD_LENOVO_R500)) {
-		int use_integrated = get_gpio(21);
+		int use_integrated = gpio_get(21);
 		printk(BIOS_DEBUG, "R500 variant found with an %s GPU\n",
 		       use_integrated ? "integrated" : "discrete");
 		if (use_integrated) {
diff --git a/src/mainboard/lenovo/x1_carbon_gen1/early_init.c b/src/mainboard/lenovo/x1_carbon_gen1/early_init.c
index bb24a26cd2..508ae8a915 100644
--- a/src/mainboard/lenovo/x1_carbon_gen1/early_init.c
+++ b/src/mainboard/lenovo/x1_carbon_gen1/early_init.c
@@ -10,7 +10,7 @@ static unsigned int get_spd_index(void)
 	unsigned int spd_index = get_gpios(spd_gpio_vector);
 
 	/* 4gb model = 0, 8gb model = 1 */
-	/* int extended_memory_version = get_gpio(44); */
+	/* int extended_memory_version = gpio_get(44); */
 
 	/*
 	 * So far there is no need to parse gpio 44, as the 4GiB use
diff --git a/src/mainboard/samsung/lumpy/chromeos.c b/src/mainboard/samsung/lumpy/chromeos.c
index 7761c69769..e0b588dd03 100644
--- a/src/mainboard/samsung/lumpy/chromeos.c
+++ b/src/mainboard/samsung/lumpy/chromeos.c
@@ -4,8 +4,8 @@
 #include <boot/coreboot_tables.h>
 #include <device/pci_ops.h>
 #include <device/device.h>
+#include <gpio.h>
 #include <southbridge/intel/bd82x6x/pch.h>
-#include <southbridge/intel/common/gpio.h>
 #include <types.h>
 #include <vendorcode/google/chromeos/chromeos.h>
 #include "onboard.h"
@@ -34,12 +34,12 @@ void fill_lb_gpios(struct lb_gpios *gpios)
 
 int get_write_protect_state(void)
 {
-	return get_gpio(GPIO_SPI_WP);
+	return gpio_get(GPIO_SPI_WP);
 }
 
 int get_recovery_mode_switch(void)
 {
-	return !get_gpio(GPIO_REC_MODE);
+	return !gpio_get(GPIO_REC_MODE);
 }
 
 int get_lid_switch(void)
diff --git a/src/mainboard/samsung/stumpy/chromeos.c b/src/mainboard/samsung/stumpy/chromeos.c
index 739b5775df..f103da293a 100644
--- a/src/mainboard/samsung/stumpy/chromeos.c
+++ b/src/mainboard/samsung/stumpy/chromeos.c
@@ -4,8 +4,8 @@
 #include <boot/coreboot_tables.h>
 #include <device/pci_ops.h>
 #include <device/device.h>
+#include <gpio.h>
 #include <southbridge/intel/bd82x6x/pch.h>
-#include <southbridge/intel/common/gpio.h>
 #include <types.h>
 #include <vendorcode/google/chromeos/chromeos.h>
 #include "onboard.h"
@@ -32,12 +32,12 @@ void fill_lb_gpios(struct lb_gpios *gpios)
 
 int get_write_protect_state(void)
 {
-	return get_gpio(GPIO_SPI_WP);
+	return gpio_get(GPIO_SPI_WP);
 }
 
 int get_recovery_mode_switch(void)
 {
-	return !get_gpio(GPIO_REC_MODE);
+	return !gpio_get(GPIO_REC_MODE);
 }
 
 int get_power_switch(void)
diff --git a/src/southbridge/intel/common/gpio.c b/src/southbridge/intel/common/gpio.c
index f32532c1cf..9f8f27d579 100644
--- a/src/southbridge/intel/common/gpio.c
+++ b/src/southbridge/intel/common/gpio.c
@@ -3,9 +3,10 @@
 #include <arch/io.h>
 #include <device/pci_ops.h>
 #include <device/pci_type.h>
+#include <gpio.h>
 #include <stdint.h>
 
-#include "gpio.h"
+#include "southbridge/intel/common/gpio.h"
 
 #define MAX_GPIO_NUMBER 75 /* zero based */
 
@@ -84,7 +85,7 @@ void setup_pch_gpios(const struct pch_gpio_map *gpio)
 /*
  * return current gpio level.
  */
-int get_gpio(int gpio_num)
+int gpio_get(gpio_t gpio_num)
 {
 	static const int gpio_reg_offsets[] = {GP_LVL, GP_LVL2, GP_LVL3};
 	u16 gpio_base = get_gpio_base();
@@ -111,7 +112,7 @@ unsigned int get_gpios(const int *gpio_num_array)
 
 	while (bitmask &&
 	       ((gpio = *gpio_num_array++) != -1)) {
-		if (get_gpio(gpio))
+		if (gpio_get(gpio))
 			vector |= bitmask;
 		bitmask <<= 1;
 	}
diff --git a/src/southbridge/intel/common/gpio.h b/src/southbridge/intel/common/gpio.h
index 6dd2acbacc..791c9f2e8b 100644
--- a/src/southbridge/intel/common/gpio.h
+++ b/src/southbridge/intel/common/gpio.h
@@ -151,8 +151,6 @@ extern const struct pch_gpio_map mainboard_gpio_map;
 /* Configure GPIOs with mainboard provided settings */
 void setup_pch_gpios(const struct pch_gpio_map *gpio);
 
-/* get GPIO pin value */
-int get_gpio(int gpio_num);
 /*
  * get a number comprised of multiple GPIO values. gpio_num_array points to
  * the array of gpio pin numbers to scan, terminated by -1.
diff --git a/src/southbridge/intel/lynxpoint/lp_gpio.c b/src/southbridge/intel/lynxpoint/lp_gpio.c
index 448ee8bd68..df860a5e15 100644
--- a/src/southbridge/intel/lynxpoint/lp_gpio.c
+++ b/src/southbridge/intel/lynxpoint/lp_gpio.c
@@ -5,6 +5,7 @@
 #include <device/pci_ops.h>
 #include <device/device.h>
 #include <device/pci.h>
+#include <gpio.h>
 
 #include "pch.h"
 #include "lp_gpio.h"
@@ -99,7 +100,7 @@ void setup_pch_lp_gpios(const struct pch_lp_gpio_map map[])
 	outl(pirq2apic, gpio_base + GPIO_PIRQ_APIC_EN);
 }
 
-int get_gpio(int gpio_num)
+int gpio_get(gpio_t gpio_num)
 {
 	u16 gpio_base = get_gpio_base();
 
@@ -121,7 +122,7 @@ unsigned int get_gpios(const int *gpio_num_array)
 
 	while (bitmask &&
 	       ((gpio = *gpio_num_array++) != -1)) {
-		if (get_gpio(gpio))
+		if (gpio_get(gpio))
 			vector |= bitmask;
 		bitmask <<= 1;
 	}
diff --git a/src/southbridge/intel/lynxpoint/lp_gpio.h b/src/southbridge/intel/lynxpoint/lp_gpio.h
index fc40c3ddcc..1e06a195a9 100644
--- a/src/southbridge/intel/lynxpoint/lp_gpio.h
+++ b/src/southbridge/intel/lynxpoint/lp_gpio.h
@@ -157,9 +157,6 @@ struct pch_lp_gpio_map {
 /* Configure GPIOs with mainboard provided settings */
 void setup_pch_lp_gpios(const struct pch_lp_gpio_map map[]);
 
-/* Get GPIO pin value */
-int get_gpio(int gpio_num);
-
 /* Set GPIO pin value */
 void set_gpio(int gpio_num, int value);
 

From 0c79443ca986af0cc1f0cd139dc3faf7614e6ea6 Mon Sep 17 00:00:00 2001
From: Patrick Rudolph <patrick.rudolph@9elements.com>
Date: Sun, 13 Jul 2025 08:57:06 +0200
Subject: [PATCH 1678/3886] sb/intel/*/gpio: Convert get_gpios to
 gpio_base2_value

Drop the custom function to retrieve the value of multiple GPIOs
at once as integer value and use the generic function prototype
defined in include/gpio.h instead.

Therefore:
* select GENERIC_GPIO_LIB
* Stub gpio_input(). Existing code assumes the pin is input.
* Drop get_gpios() implementation
* Include new header file gpio.h
* Migrate pins from type int to gpio_t

Migrate all users of the old function to the new function.

Allows to share more code between older x86 Intel boards and newer
x86 Intel boards since they now use a common header.

Change-Id: I2296ff72231b569c618295b36b95a89ffebb3a6e
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88503
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 .../auron/variants/auron_paine/spd/spd.c      |  9 +++----
 .../auron/variants/auron_yuna/spd/spd.c       |  9 +++----
 .../google/auron/variants/gandof/spd/spd.c    |  9 +++----
 .../google/auron/variants/lulu/spd/spd.c      |  9 +++----
 .../google/auron/variants/samus/spd/spd.c     |  9 +++----
 src/mainboard/google/link/early_init.c        |  6 ++---
 .../google/slippy/variants/falco/romstage.c   |  6 ++---
 .../google/slippy/variants/leon/romstage.c    |  6 ++---
 .../google/slippy/variants/peppy/romstage.c   |  6 ++---
 .../google/slippy/variants/wolf/romstage.c    |  6 ++---
 src/mainboard/lenovo/s230u/early_init.c       |  6 ++---
 src/mainboard/lenovo/t410/dock.c              |  6 ++---
 .../lenovo/x1_carbon_gen1/early_init.c        |  7 ++---
 .../lenovo/x200/variants/x200/dock.c          |  5 ++--
 src/mainboard/lenovo/x201/dock.c              |  5 ++--
 src/soc/intel/broadwell/Kconfig               |  1 +
 src/southbridge/intel/common/Kconfig.common   |  1 +
 src/southbridge/intel/common/gpio.c           | 26 +++++--------------
 src/southbridge/intel/common/gpio.h           |  6 -----
 src/southbridge/intel/lynxpoint/Kconfig       |  1 +
 src/southbridge/intel/lynxpoint/lp_gpio.c     | 24 ++++-------------
 src/southbridge/intel/lynxpoint/lp_gpio.h     |  6 -----
 22 files changed, 66 insertions(+), 103 deletions(-)

diff --git a/src/mainboard/google/auron/variants/auron_paine/spd/spd.c b/src/mainboard/google/auron/variants/auron_paine/spd/spd.c
index f2401d4be7..05df95e389 100644
--- a/src/mainboard/google/auron/variants/auron_paine/spd/spd.c
+++ b/src/mainboard/google/auron/variants/auron_paine/spd/spd.c
@@ -1,7 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
 #include <mainboard/google/auron/variant.h>
-#include <southbridge/intel/lynxpoint/lp_gpio.h>
+#include <gpio.h>
 
 /* Auron board memory configuration GPIOs */
 #define SPD_GPIO_BIT0		13
@@ -10,13 +10,12 @@
 
 unsigned int variant_get_spd_index(void)
 {
-	const int gpio_vector[] = {
+	const gpio_t gpio_vector[] = {
 		SPD_GPIO_BIT0,
 		SPD_GPIO_BIT1,
-		SPD_GPIO_BIT2,
-		-1,
+		SPD_GPIO_BIT2
 	};
-	return get_gpios(gpio_vector);
+	return gpio_base2_value(gpio_vector, ARRAY_SIZE(gpio_vector));
 }
 
 bool variant_is_dual_channel(const unsigned int spd_index)
diff --git a/src/mainboard/google/auron/variants/auron_yuna/spd/spd.c b/src/mainboard/google/auron/variants/auron_yuna/spd/spd.c
index f2401d4be7..05df95e389 100644
--- a/src/mainboard/google/auron/variants/auron_yuna/spd/spd.c
+++ b/src/mainboard/google/auron/variants/auron_yuna/spd/spd.c
@@ -1,7 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
 #include <mainboard/google/auron/variant.h>
-#include <southbridge/intel/lynxpoint/lp_gpio.h>
+#include <gpio.h>
 
 /* Auron board memory configuration GPIOs */
 #define SPD_GPIO_BIT0		13
@@ -10,13 +10,12 @@
 
 unsigned int variant_get_spd_index(void)
 {
-	const int gpio_vector[] = {
+	const gpio_t gpio_vector[] = {
 		SPD_GPIO_BIT0,
 		SPD_GPIO_BIT1,
-		SPD_GPIO_BIT2,
-		-1,
+		SPD_GPIO_BIT2
 	};
-	return get_gpios(gpio_vector);
+	return gpio_base2_value(gpio_vector, ARRAY_SIZE(gpio_vector));
 }
 
 bool variant_is_dual_channel(const unsigned int spd_index)
diff --git a/src/mainboard/google/auron/variants/gandof/spd/spd.c b/src/mainboard/google/auron/variants/gandof/spd/spd.c
index d144e20ec3..53aad4891d 100644
--- a/src/mainboard/google/auron/variants/gandof/spd/spd.c
+++ b/src/mainboard/google/auron/variants/gandof/spd/spd.c
@@ -1,7 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
 #include <mainboard/google/auron/variant.h>
-#include <southbridge/intel/lynxpoint/lp_gpio.h>
+#include <gpio.h>
 
 /* Gandof board memory configuration GPIOs */
 #define SPD_GPIO_BIT0		13
@@ -10,13 +10,12 @@
 
 unsigned int variant_get_spd_index(void)
 {
-	const int gpio_vector[] = {
+	const gpio_t gpio_vector[] = {
 		SPD_GPIO_BIT0,
 		SPD_GPIO_BIT1,
-		SPD_GPIO_BIT2,
-		-1,
+		SPD_GPIO_BIT2
 	};
-	return get_gpios(gpio_vector);
+	return gpio_base2_value(gpio_vector, ARRAY_SIZE(gpio_vector));
 }
 
 bool variant_is_dual_channel(const unsigned int spd_index)
diff --git a/src/mainboard/google/auron/variants/lulu/spd/spd.c b/src/mainboard/google/auron/variants/lulu/spd/spd.c
index 33e8c9b55d..87e0c0a2e9 100644
--- a/src/mainboard/google/auron/variants/lulu/spd/spd.c
+++ b/src/mainboard/google/auron/variants/lulu/spd/spd.c
@@ -1,7 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
 #include <mainboard/google/auron/variant.h>
-#include <southbridge/intel/lynxpoint/lp_gpio.h>
+#include <gpio.h>
 
 /* Lulu board memory configuration GPIOs */
 #define SPD_GPIO_BIT0		13
@@ -11,14 +11,13 @@
 
 unsigned int variant_get_spd_index(void)
 {
-	const int gpio_vector[] = {
+	const gpio_t gpio_vector[] = {
 		SPD_GPIO_BIT0,
 		SPD_GPIO_BIT1,
 		SPD_GPIO_BIT2,
-		SPD_GPIO_BIT3,
-		-1,
+		SPD_GPIO_BIT3
 	};
-	return get_gpios(gpio_vector);
+	return gpio_base2_value(gpio_vector, ARRAY_SIZE(gpio_vector));
 }
 
 bool variant_is_dual_channel(const unsigned int spd_index)
diff --git a/src/mainboard/google/auron/variants/samus/spd/spd.c b/src/mainboard/google/auron/variants/samus/spd/spd.c
index 65afe238ed..9795881e1b 100644
--- a/src/mainboard/google/auron/variants/samus/spd/spd.c
+++ b/src/mainboard/google/auron/variants/samus/spd/spd.c
@@ -2,7 +2,7 @@
 
 #include <mainboard/google/auron/variant.h>
 #include <soc/pei_wrapper.h>
-#include <southbridge/intel/lynxpoint/lp_gpio.h>
+#include <gpio.h>
 
 /* Samus board memory configuration GPIOs */
 #define SPD_GPIO_BIT0		69
@@ -12,14 +12,13 @@
 
 unsigned int variant_get_spd_index(void)
 {
-	const int gpio_vector[] = {
+	const gpio_t gpio_vector[] = {
 		SPD_GPIO_BIT0,
 		SPD_GPIO_BIT1,
 		SPD_GPIO_BIT2,
-		SPD_GPIO_BIT3,
-		-1,
+		SPD_GPIO_BIT3
 	};
-	return get_gpios(gpio_vector);
+	return gpio_base2_value(gpio_vector, ARRAY_SIZE(gpio_vector));
 }
 
 bool variant_is_dual_channel(const unsigned int spd_index)
diff --git a/src/mainboard/google/link/early_init.c b/src/mainboard/google/link/early_init.c
index 2d20ac03a9..9d43da5a62 100644
--- a/src/mainboard/google/link/early_init.c
+++ b/src/mainboard/google/link/early_init.c
@@ -1,10 +1,10 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
 #include <device/pci_ops.h>
+#include <gpio.h>
 #include <northbridge/intel/sandybridge/sandybridge.h>
 #include <northbridge/intel/sandybridge/raminit.h>
 #include <southbridge/intel/bd82x6x/pch.h>
-#include <southbridge/intel/common/gpio.h>
 #include "ec/google/chromeec/ec.h"
 
 #include <southbridge/intel/bd82x6x/chip.h>
@@ -54,8 +54,8 @@ void mainboard_late_rcba_config(void)
 
 static unsigned int get_spd_index(void)
 {
-	const int gpio_vector[] = {41, 42, 43, 10, -1};
-	return get_gpios(gpio_vector);
+	const gpio_t gpio_vector[] = {41, 42, 43, 10};
+	return gpio_base2_value(gpio_vector, ARRAY_SIZE(gpio_vector));
 }
 
 void mainboard_fill_pei_data(struct pei_data *pei_data)
diff --git a/src/mainboard/google/slippy/variants/falco/romstage.c b/src/mainboard/google/slippy/variants/falco/romstage.c
index b391d81b31..404d5bb276 100644
--- a/src/mainboard/google/slippy/variants/falco/romstage.c
+++ b/src/mainboard/google/slippy/variants/falco/romstage.c
@@ -1,14 +1,14 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
+#include <gpio.h>
 #include <northbridge/intel/haswell/raminit.h>
 #include <southbridge/intel/lynxpoint/pch.h>
-#include <southbridge/intel/lynxpoint/lp_gpio.h>
 #include "../../variant.h"
 
 unsigned int variant_get_spd_index(void)
 {
-	const int gpio_vector[] = {13, 9, 47, -1};
-	return get_gpios(gpio_vector);
+	const gpio_t gpio_vector[] = {13, 9, 47};
+	return gpio_base2_value(gpio_vector, ARRAY_SIZE(gpio_vector));
 }
 
 bool variant_is_dual_channel(const unsigned int spd_index)
diff --git a/src/mainboard/google/slippy/variants/leon/romstage.c b/src/mainboard/google/slippy/variants/leon/romstage.c
index 50a1b7305c..0b4bd6773f 100644
--- a/src/mainboard/google/slippy/variants/leon/romstage.c
+++ b/src/mainboard/google/slippy/variants/leon/romstage.c
@@ -1,14 +1,14 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
+#include <gpio.h>
 #include <northbridge/intel/haswell/raminit.h>
 #include <southbridge/intel/lynxpoint/pch.h>
-#include <southbridge/intel/lynxpoint/lp_gpio.h>
 #include "../../variant.h"
 
 unsigned int variant_get_spd_index(void)
 {
-	const int gpio_vector[] = {13, 9, 47, -1};
-	return get_gpios(gpio_vector);
+	const gpio_t gpio_vector[] = {13, 9, 47};
+	return gpio_base2_value(gpio_vector, ARRAY_SIZE(gpio_vector));
 }
 
 bool variant_is_dual_channel(const unsigned int spd_index)
diff --git a/src/mainboard/google/slippy/variants/peppy/romstage.c b/src/mainboard/google/slippy/variants/peppy/romstage.c
index 32fdd97e94..130d7f6a7d 100644
--- a/src/mainboard/google/slippy/variants/peppy/romstage.c
+++ b/src/mainboard/google/slippy/variants/peppy/romstage.c
@@ -2,16 +2,16 @@
 
 #include <stdint.h>
 #include <ec/google/chromeec/ec.h>
+#include <gpio.h>
 #include <northbridge/intel/haswell/raminit.h>
 #include <southbridge/intel/lynxpoint/pch.h>
-#include <southbridge/intel/lynxpoint/lp_gpio.h>
 #include "../../onboard.h"
 #include "../../variant.h"
 
 unsigned int variant_get_spd_index(void)
 {
-	const int gpio_vector[] = {13, 9, 47, -1};
-	return get_gpios(gpio_vector);
+	const gpio_t gpio_vector[] = {13, 9, 47};
+	return gpio_base2_value(gpio_vector, ARRAY_SIZE(gpio_vector));
 }
 
 bool variant_is_dual_channel(const unsigned int spd_index)
diff --git a/src/mainboard/google/slippy/variants/wolf/romstage.c b/src/mainboard/google/slippy/variants/wolf/romstage.c
index 7c1bff007b..b5f1def1ea 100644
--- a/src/mainboard/google/slippy/variants/wolf/romstage.c
+++ b/src/mainboard/google/slippy/variants/wolf/romstage.c
@@ -1,14 +1,14 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
+#include <gpio.h>
 #include <northbridge/intel/haswell/raminit.h>
 #include <southbridge/intel/lynxpoint/pch.h>
-#include <southbridge/intel/lynxpoint/lp_gpio.h>
 #include "../../variant.h"
 
 unsigned int variant_get_spd_index(void)
 {
-	const int gpio_vector[] = {13, 9, 47, -1};
-	return get_gpios(gpio_vector);
+	const gpio_t gpio_vector[] = {13, 9, 47};
+	return gpio_base2_value(gpio_vector, ARRAY_SIZE(gpio_vector));
 }
 
 bool variant_is_dual_channel(const unsigned int spd_index)
diff --git a/src/mainboard/lenovo/s230u/early_init.c b/src/mainboard/lenovo/s230u/early_init.c
index f4396cb617..ba52b7e7c9 100644
--- a/src/mainboard/lenovo/s230u/early_init.c
+++ b/src/mainboard/lenovo/s230u/early_init.c
@@ -2,9 +2,9 @@
 
 #include <device/pci_ops.h>
 #include <console/console.h>
+#include <gpio.h>
 #include <northbridge/intel/sandybridge/raminit.h>
 #include <southbridge/intel/bd82x6x/pch.h>
-#include <southbridge/intel/common/gpio.h>
 #include "ec.h"
 
 void mainboard_pch_lpc_setup(void)
@@ -34,9 +34,9 @@ static const char *mainboard_spd_names[9] = {
 
 static unsigned int get_spd_index(void)
 {
-	const int spd_gpios[] = {71, 70, 16, 48, -1};
+	const gpio_t spd_gpios[] = {71, 70, 16, 48};
 
-	unsigned int spd_index = get_gpios(spd_gpios);
+	unsigned int spd_index = gpio_base2_value(spd_gpios, ARRAY_SIZE(spd_gpios));
 	if (spd_index >= ARRAY_SIZE(mainboard_spd_names)) {
 		/* Fallback to pessimistic 2GB image (ELPIDA 2GB) */
 		spd_index = 6;
diff --git a/src/mainboard/lenovo/t410/dock.c b/src/mainboard/lenovo/t410/dock.c
index 37a2908c1d..759afe98c5 100644
--- a/src/mainboard/lenovo/t410/dock.c
+++ b/src/mainboard/lenovo/t410/dock.c
@@ -2,6 +2,7 @@
 
 #include <console/console.h>
 #include <device/device.h>
+#include <gpio.h>
 #include "dock.h"
 #include <southbridge/intel/common/gpio.h>
 #include <ec/lenovo/h8/h8.h>
@@ -35,7 +36,6 @@ void dock_disconnect(void)
 
 int dock_present(void)
 {
-	const int gpio_num_array[] = {3, 4, 5, -1};
-
-	return get_gpios(gpio_num_array) != 7;
+	const gpio_t gpio_num_array[] = {3, 4, 5};
+	return gpio_base2_value(gpio_num_array, ARRAY_SIZE(gpio_num_array)) != 7;
 }
diff --git a/src/mainboard/lenovo/x1_carbon_gen1/early_init.c b/src/mainboard/lenovo/x1_carbon_gen1/early_init.c
index 508ae8a915..7cfc5d9a0e 100644
--- a/src/mainboard/lenovo/x1_carbon_gen1/early_init.c
+++ b/src/mainboard/lenovo/x1_carbon_gen1/early_init.c
@@ -1,13 +1,14 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
 #include <console/console.h>
+#include <gpio.h>
 #include <northbridge/intel/sandybridge/raminit.h>
-#include <southbridge/intel/common/gpio.h>
 
 static unsigned int get_spd_index(void)
 {
-	const int spd_gpio_vector[] = {25, 45, -1};
-	unsigned int spd_index = get_gpios(spd_gpio_vector);
+	const gpio_t spd_gpio_vector[] = {25, 45};
+	unsigned int spd_index = gpio_base2_value(spd_gpio_vector,
+						  ARRAY_SIZE(spd_gpio_vector));
 
 	/* 4gb model = 0, 8gb model = 1 */
 	/* int extended_memory_version = gpio_get(44); */
diff --git a/src/mainboard/lenovo/x200/variants/x200/dock.c b/src/mainboard/lenovo/x200/variants/x200/dock.c
index ff787ec2a8..a10772ede2 100644
--- a/src/mainboard/lenovo/x200/variants/x200/dock.c
+++ b/src/mainboard/lenovo/x200/variants/x200/dock.c
@@ -2,6 +2,7 @@
 
 #include <console/console.h>
 #include <device/device.h>
+#include <gpio.h>
 #include <southbridge/intel/common/gpio.h>
 #include <ec/lenovo/h8/h8.h>
 #include <ec/acpi/ec.h>
@@ -32,7 +33,7 @@ void dock_disconnect(void)
 
 int dock_present(void)
 {
-	const int dock_id_gpio[] = { 2, 3, 4, -1};
+	const gpio_t dock_id_gpio[] = {2, 3, 4};
 
-	return get_gpios(dock_id_gpio) != 7;
+	return gpio_base2_value(dock_id_gpio, ARRAY_SIZE(dock_id_gpio)) != 7;
 }
diff --git a/src/mainboard/lenovo/x201/dock.c b/src/mainboard/lenovo/x201/dock.c
index 7354eeeb41..a1bd1e81d7 100644
--- a/src/mainboard/lenovo/x201/dock.c
+++ b/src/mainboard/lenovo/x201/dock.c
@@ -2,6 +2,7 @@
 
 #include <console/console.h>
 #include <device/device.h>
+#include <gpio.h>
 #include "dock.h"
 #include <southbridge/intel/common/gpio.h>
 #include <ec/lenovo/h8/h8.h>
@@ -37,7 +38,7 @@ void dock_disconnect(void)
 
 int dock_present(void)
 {
-	const int dock_id_gpio[] = { 3, 4, 5, -1};
+	const gpio_t dock_id_gpio[] = {3, 4, 5};
 
-	return get_gpios(dock_id_gpio) != 7;
+	return gpio_base2_value(dock_id_gpio, ARRAY_SIZE(dock_id_gpio)) != 7;
 }
diff --git a/src/soc/intel/broadwell/Kconfig b/src/soc/intel/broadwell/Kconfig
index 4859a7e41a..e92aee0cef 100644
--- a/src/soc/intel/broadwell/Kconfig
+++ b/src/soc/intel/broadwell/Kconfig
@@ -4,6 +4,7 @@ config SOC_INTEL_BROADWELL
 	bool
 	select CACHE_MRC_SETTINGS
 	select CPU_INTEL_HASWELL
+	select GENERIC_GPIO_LIB
 	select INTEL_GMA_ACPI
 	select MRC_SETTINGS_PROTECT
 	select REG_SCRIPT
diff --git a/src/southbridge/intel/common/Kconfig.common b/src/southbridge/intel/common/Kconfig.common
index c621399785..0da0d70742 100644
--- a/src/southbridge/intel/common/Kconfig.common
+++ b/src/southbridge/intel/common/Kconfig.common
@@ -15,6 +15,7 @@ config SOUTHBRIDGE_INTEL_COMMON_PMBASE
 	def_bool n
 
 config SOUTHBRIDGE_INTEL_COMMON_GPIO
+	select GENERIC_GPIO_LIB
 	def_bool n
 
 config SOUTHBRIDGE_INTEL_COMMON_ME
diff --git a/src/southbridge/intel/common/gpio.c b/src/southbridge/intel/common/gpio.c
index 9f8f27d579..a033ead057 100644
--- a/src/southbridge/intel/common/gpio.c
+++ b/src/southbridge/intel/common/gpio.c
@@ -1,10 +1,12 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
+#include <assert.h>
 #include <arch/io.h>
 #include <device/pci_ops.h>
 #include <device/pci_type.h>
 #include <gpio.h>
 #include <stdint.h>
+#include <gpio.h>
 
 #include "southbridge/intel/common/gpio.h"
 
@@ -100,25 +102,6 @@ int gpio_get(gpio_t gpio_num)
 	return (inl(gpio_base + gpio_reg_offsets[index]) >> bit) & 1;
 }
 
-/*
- * get a number comprised of multiple GPIO values. gpio_num_array points to
- * the array of gpio pin numbers to scan, terminated by -1.
- */
-unsigned int get_gpios(const int *gpio_num_array)
-{
-	int gpio;
-	unsigned int bitmask = 1;
-	unsigned int vector = 0;
-
-	while (bitmask &&
-	       ((gpio = *gpio_num_array++) != -1)) {
-		if (gpio_get(gpio))
-			vector |= bitmask;
-		bitmask <<= 1;
-	}
-	return vector;
-}
-
 /*
  * set gpio output to level.
  */
@@ -162,3 +145,8 @@ int gpio_is_native(int gpio_num)
 	config = inl(gpio_base + gpio_reg_offsets[index]);
 	return !(config & (1 << bit));
 }
+
+void gpio_input(gpio_t gpio)
+{
+	// FIXME: Implement
+}
diff --git a/src/southbridge/intel/common/gpio.h b/src/southbridge/intel/common/gpio.h
index 791c9f2e8b..4e47f18ae2 100644
--- a/src/southbridge/intel/common/gpio.h
+++ b/src/southbridge/intel/common/gpio.h
@@ -151,12 +151,6 @@ extern const struct pch_gpio_map mainboard_gpio_map;
 /* Configure GPIOs with mainboard provided settings */
 void setup_pch_gpios(const struct pch_gpio_map *gpio);
 
-/*
- * get a number comprised of multiple GPIO values. gpio_num_array points to
- * the array of gpio pin numbers to scan, terminated by -1.
- */
-unsigned int get_gpios(const int *gpio_num_array);
-
 void set_gpio(int gpio_num, int value);
 
 void clear_gpio(int gpio_num);
diff --git a/src/southbridge/intel/lynxpoint/Kconfig b/src/southbridge/intel/lynxpoint/Kconfig
index 48492e6692..d126eb4fde 100644
--- a/src/southbridge/intel/lynxpoint/Kconfig
+++ b/src/southbridge/intel/lynxpoint/Kconfig
@@ -24,6 +24,7 @@ config SOUTHBRIDGE_INTEL_LYNXPOINT
 	select HAVE_EM100PRO_SPI_CONSOLE_SUPPORT
 	select RTC
 	select SOUTHBRIDGE_INTEL_COMMON_GPIO if !INTEL_LYNXPOINT_LP
+	select GENERIC_GPIO_LIB
 	select SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ
 	select HAVE_INTEL_CHIPSET_LOCKDOWN
 	select HAVE_POWER_STATE_AFTER_FAILURE
diff --git a/src/southbridge/intel/lynxpoint/lp_gpio.c b/src/southbridge/intel/lynxpoint/lp_gpio.c
index df860a5e15..123e4a43f9 100644
--- a/src/southbridge/intel/lynxpoint/lp_gpio.c
+++ b/src/southbridge/intel/lynxpoint/lp_gpio.c
@@ -110,25 +110,6 @@ int gpio_get(gpio_t gpio_num)
 	return !!(inl(gpio_base + GPIO_CONFIG0(gpio_num)) & GPI_LEVEL);
 }
 
-/*
- * get a number comprised of multiple GPIO values. gpio_num_array points to
- * the array of gpio pin numbers to scan, terminated by -1.
- */
-unsigned int get_gpios(const int *gpio_num_array)
-{
-	int gpio;
-	unsigned int bitmask = 1;
-	unsigned int vector = 0;
-
-	while (bitmask &&
-	       ((gpio = *gpio_num_array++) != -1)) {
-		if (gpio_get(gpio))
-			vector |= bitmask;
-		bitmask <<= 1;
-	}
-	return vector;
-}
-
 void set_gpio(int gpio_num, int value)
 {
 	u16 gpio_base = get_gpio_base();
@@ -149,3 +130,8 @@ int gpio_is_native(int gpio_num)
 
 	return !(inl(gpio_base + GPIO_CONFIG0(gpio_num)) & 1);
 }
+
+void gpio_input(gpio_t gpio)
+{
+	// FIXME: Implement
+}
diff --git a/src/southbridge/intel/lynxpoint/lp_gpio.h b/src/southbridge/intel/lynxpoint/lp_gpio.h
index 1e06a195a9..dd2a89a373 100644
--- a/src/southbridge/intel/lynxpoint/lp_gpio.h
+++ b/src/southbridge/intel/lynxpoint/lp_gpio.h
@@ -163,12 +163,6 @@ void set_gpio(int gpio_num, int value);
 /* Return non-zero if gpio is set to native function. 0 otherwise. */
 int gpio_is_native(int gpio_num);
 
-/*
- * Get a number comprised of multiple GPIO values. gpio_num_array points to
- * the array of gpio pin numbers to scan, terminated by -1.
- */
-unsigned int get_gpios(const int *gpio_num_array);
-
 extern const struct pch_lp_gpio_map mainboard_lp_gpio_map[];
 
 #endif

From 84899e6fb76f087f3dc5c50bfda6d70c42b40e6f Mon Sep 17 00:00:00 2001
From: Patrick Rudolph <patrick.rudolph@9elements.com>
Date: Sun, 13 Jul 2025 19:03:47 +0200
Subject: [PATCH 1679/3886] sb/intel: Convert set_gpio to gpio_set

Drop the custom function to set the value of a single GPIO and
use the generic function prototype defined in include/gpio.h instead.

Migrate all users of the old function to the new function.

Allows to share more code between older x86 Intel boards and newer
x86 Intel boards since they now use a common header.

Change-Id: I8c83b3436818275958cd8eb8b1c0d7b235e0344c
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88504
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 .../lenovo/hybrid_graphics/hybrid_graphics.c     |  9 ++++-----
 src/drivers/lenovo/hybrid_graphics/romstage.c    |  5 ++---
 .../variants/p8z77-v_le_plus/early_init.c        |  4 ++--
 src/mainboard/google/auron/smihandler.c          | 11 ++++++-----
 .../google/auron/variants/samus/variant.c        |  8 ++++----
 src/mainboard/google/jecht/smihandler.c          |  3 ++-
 src/mainboard/google/slippy/smihandler.c         | 16 ++++++++--------
 src/mainboard/lenovo/t400/romstage.c             |  3 +--
 src/mainboard/lenovo/x200/romstage.c             |  4 ++--
 src/mainboard/lenovo/x200/variants/x200/dock.c   |  5 ++---
 src/mainboard/lenovo/x201/dock.c                 |  7 +++----
 src/southbridge/intel/common/gpio.c              |  2 +-
 src/southbridge/intel/common/gpio.h              |  2 --
 src/southbridge/intel/lynxpoint/lp_gpio.c        |  2 +-
 src/southbridge/intel/lynxpoint/lp_gpio.h        |  3 ---
 15 files changed, 38 insertions(+), 46 deletions(-)

diff --git a/src/drivers/lenovo/hybrid_graphics/hybrid_graphics.c b/src/drivers/lenovo/hybrid_graphics/hybrid_graphics.c
index ebd7efccac..1d960f7f06 100644
--- a/src/drivers/lenovo/hybrid_graphics/hybrid_graphics.c
+++ b/src/drivers/lenovo/hybrid_graphics/hybrid_graphics.c
@@ -4,7 +4,6 @@
 #include <device/device.h>
 #include <gpio.h>
 #include <option.h>
-#include <southbridge/intel/common/gpio.h>
 #include "chip.h"
 
 /*
@@ -32,22 +31,22 @@ static void lenovo_hybrid_graphics_enable(struct device *dev)
 		       " Switching panel to discrete GPU.\n");
 
 		if (config->has_panel_hybrid_gpio)
-			set_gpio(config->panel_hybrid_gpio,
+			gpio_set(config->panel_hybrid_gpio,
 				 !config->panel_integrated_lvl);
 
 		if (config->has_backlight_gpio)
-			set_gpio(config->backlight_gpio,
+			gpio_set(config->backlight_gpio,
 				 !config->backlight_integrated_lvl);
 	} else {
 		printk(BIOS_DEBUG, "Hybrid graphics:"
 		       " Switching panel to integrated GPU.\n");
 
 		if (config->has_panel_hybrid_gpio)
-			set_gpio(config->panel_hybrid_gpio,
+			gpio_set(config->panel_hybrid_gpio,
 				 config->panel_integrated_lvl);
 
 		if (config->has_backlight_gpio)
-			set_gpio(config->backlight_gpio,
+			gpio_set(config->backlight_gpio,
 				 config->backlight_integrated_lvl);
 	}
 }
diff --git a/src/drivers/lenovo/hybrid_graphics/romstage.c b/src/drivers/lenovo/hybrid_graphics/romstage.c
index b28237c8c3..10f94439f8 100644
--- a/src/drivers/lenovo/hybrid_graphics/romstage.c
+++ b/src/drivers/lenovo/hybrid_graphics/romstage.c
@@ -6,7 +6,6 @@
 #include <option.h>
 #include <gpio.h>
 #include <types.h>
-#include <southbridge/intel/common/gpio.h>
 
 #include "hybrid_graphics.h"
 #include "chip.h"
@@ -67,10 +66,10 @@ void early_hybrid_graphics(bool *enable_igd, bool *enable_peg)
 	 */
 	if (config->has_dgpu_power_gpio) {
 		if (*enable_peg)
-			set_gpio(config->dgpu_power_gpio,
+			gpio_set(config->dgpu_power_gpio,
 				 !config->dgpu_power_off_lvl);
 		else
-			set_gpio(config->dgpu_power_gpio,
+			gpio_set(config->dgpu_power_gpio,
 				 config->dgpu_power_off_lvl);
 	} else if (config->has_thinker1) {
 		bool power_en = pmh7_dgpu_power_state();
diff --git a/src/mainboard/asus/p8x7x-series/variants/p8z77-v_le_plus/early_init.c b/src/mainboard/asus/p8x7x-series/variants/p8z77-v_le_plus/early_init.c
index 024f8e9d81..343c9a889b 100644
--- a/src/mainboard/asus/p8x7x-series/variants/p8z77-v_le_plus/early_init.c
+++ b/src/mainboard/asus/p8x7x-series/variants/p8z77-v_le_plus/early_init.c
@@ -5,10 +5,10 @@
 #include <device/pnp_ops.h>
 #include <device/pci_ops.h>
 #include <device/pci.h>
+#include <gpio.h>
 #include <superio/nuvoton/common/nuvoton.h>
 #include <superio/nuvoton/nct6779d/nct6779d.h>
 #include <southbridge/intel/common/rcba.h>
-#include <southbridge/intel/common/gpio.h>
 #include <southbridge/intel/bd82x6x/pch.h>
 #include <console/console.h>
 #include <option.h>
@@ -85,7 +85,7 @@ void bootblock_mainboard_init(void)
 	}
 
 	/* Match GPIO to soft strap. */
-	set_gpio(46, gp46);
+	gpio_set(46, gp46);
 }
 
 void bootblock_mainboard_early_init(void)
diff --git a/src/mainboard/google/auron/smihandler.c b/src/mainboard/google/auron/smihandler.c
index e20976c5f1..9485b8d13a 100644
--- a/src/mainboard/google/auron/smihandler.c
+++ b/src/mainboard/google/auron/smihandler.c
@@ -2,11 +2,12 @@
 
 #include <acpi/acpi.h>
 #include <cpu/x86/smm.h>
-#include <soc/pm.h>
 #include <ec/google/chromeec/ec.h>
 #include <ec/google/chromeec/smm.h>
+#include <gpio.h>
 #include <southbridge/intel/lynxpoint/lp_gpio.h>
 #include <soc/iomap.h>
+#include <soc/pm.h>
 #include "ec.h"
 #include <variant/onboard.h>
 
@@ -21,14 +22,14 @@ static void mainboard_disable_gpios(void)
 {
 #if CONFIG(BOARD_GOOGLE_SAMUS)
 	/* Put SSD in reset to prevent leak */
-	set_gpio(BOARD_SSD_RESET_GPIO, 0);
+	gpio_set(BOARD_SSD_RESET_GPIO, 0);
 	/* Disable LTE */
-	set_gpio(BOARD_LTE_DISABLE_GPIO, 0);
+	gpio_set(BOARD_LTE_DISABLE_GPIO, 0);
 #else
-	set_gpio(BOARD_PP3300_CODEC_GPIO, 0);
+	gpio_set(BOARD_PP3300_CODEC_GPIO, 0);
 #endif
 	/* Prevent leak from standby rail to WLAN rail */
-	set_gpio(BOARD_WLAN_DISABLE_GPIO, 0);
+	gpio_set(BOARD_WLAN_DISABLE_GPIO, 0);
 }
 
 void mainboard_smi_sleep(u8 slp_typ)
diff --git a/src/mainboard/google/auron/variants/samus/variant.c b/src/mainboard/google/auron/variants/samus/variant.c
index 441cefe6e8..23468aba1e 100644
--- a/src/mainboard/google/auron/variants/samus/variant.c
+++ b/src/mainboard/google/auron/variants/samus/variant.c
@@ -2,13 +2,13 @@
 
 #include <console/console.h>
 #include <ec/google/chromeec/ec.h>
-#include <southbridge/intel/lynxpoint/lp_gpio.h>
+#include <gpio.h>
+#include <mainboard/google/auron/variant.h>
 #include <soc/pm.h>
 #include <soc/romstage.h>
 #include <smbios.h>
 #include <variant/board_version.h>
 #include <variant/onboard.h>
-#include <mainboard/google/auron/variant.h>
 
 const char *smbios_mainboard_version(void)
 {
@@ -29,11 +29,11 @@ void mainboard_post_raminit(const int s3resume)
 	printk(BIOS_INFO, "MLB: board version %s\n", samus_board_version());
 
 	/* Bring SSD out of reset */
-	set_gpio(BOARD_SSD_RESET_GPIO, 1);
+	gpio_set(BOARD_SSD_RESET_GPIO, 1);
 
 	/*
 	 * Enable PP3300_AUTOBAHN_EN after initial GPIO setup
 	 * to prevent possible brownout.
 	 */
-	set_gpio(BOARD_PP3300_AUTOBAHN_GPIO, 1);
+	gpio_set(BOARD_PP3300_AUTOBAHN_GPIO, 1);
 }
diff --git a/src/mainboard/google/jecht/smihandler.c b/src/mainboard/google/jecht/smihandler.c
index 076d3fe08c..7743ce546e 100644
--- a/src/mainboard/google/jecht/smihandler.c
+++ b/src/mainboard/google/jecht/smihandler.c
@@ -2,6 +2,7 @@
 
 #include <acpi/acpi.h>
 #include <cpu/x86/smm.h>
+#include <gpio.h>
 #include <soc/pm.h>
 #include <southbridge/intel/lynxpoint/lp_gpio.h>
 #include <soc/iomap.h>
@@ -21,7 +22,7 @@ void mainboard_smi_sleep(u8 slp_typ)
 
 		/* Enable DCP mode */
 		if (CONFIG(BOARD_GOOGLE_TIDUS)) {
-			set_gpio(GPIO_USB_CTL_1, 0);
+			gpio_set(GPIO_USB_CTL_1, 0);
 		}
 		break;
 	case ACPI_S5:
diff --git a/src/mainboard/google/slippy/smihandler.c b/src/mainboard/google/slippy/smihandler.c
index cefaf7a099..42e79220e1 100644
--- a/src/mainboard/google/slippy/smihandler.c
+++ b/src/mainboard/google/slippy/smihandler.c
@@ -1,12 +1,12 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
 #include <acpi/acpi.h>
-#include <cpu/x86/smm.h>
-#include <southbridge/intel/lynxpoint/pch.h>
-#include <southbridge/intel/common/gpio.h>
-#include <southbridge/intel/lynxpoint/me.h>
-#include <northbridge/intel/haswell/haswell.h>
 #include <cpu/intel/haswell/haswell.h>
+#include <cpu/x86/smm.h>
+#include <gpio.h>
+#include <northbridge/intel/haswell/haswell.h>
+#include <southbridge/intel/lynxpoint/pch.h>
+#include <southbridge/intel/lynxpoint/me.h>
 
 /* Include EC functions */
 #include <ec/google/chromeec/smm.h>
@@ -35,10 +35,10 @@ void mainboard_smi_sleep(u8 slp_typ)
 	case ACPI_S4:
 	case ACPI_S5:
 		/* Prevent leak from standby rail to WLAN rail in S3/S4/S5. */
-		set_gpio(GPIO_WLAN_DISABLE_L, 0);
-		set_gpio(GPIO_PP3300_CODEC_EN, 0);
+		gpio_set(GPIO_WLAN_DISABLE_L, 0);
+		gpio_set(GPIO_PP3300_CODEC_EN, 0);
 		/* Disable LTE */
-		set_gpio(GPIO_LTE_DISABLE_L, 0);
+		gpio_set(GPIO_LTE_DISABLE_L, 0);
 		break;
 	}
 
diff --git a/src/mainboard/lenovo/t400/romstage.c b/src/mainboard/lenovo/t400/romstage.c
index 850116aad2..20add1e112 100644
--- a/src/mainboard/lenovo/t400/romstage.c
+++ b/src/mainboard/lenovo/t400/romstage.c
@@ -4,7 +4,6 @@
 #include <drivers/lenovo/hybrid_graphics/hybrid_graphics.h>
 #include <gpio.h>
 #include <northbridge/intel/gm45/gm45.h>
-#include <southbridge/intel/common/gpio.h>
 
 static void hybrid_graphics_init(sysinfo_t *sysinfo)
 {
@@ -44,5 +43,5 @@ void mb_post_raminit_setup(void)
 {
 	/* FIXME: make a proper SMBUS mux support. */
 	/* Set the SMBUS mux to the eeprom */
-	set_gpio(42, GPIO_LEVEL_LOW);
+	gpio_set(42, GPIO_LEVEL_LOW);
 }
diff --git a/src/mainboard/lenovo/x200/romstage.c b/src/mainboard/lenovo/x200/romstage.c
index 6764644274..224c46b865 100644
--- a/src/mainboard/lenovo/x200/romstage.c
+++ b/src/mainboard/lenovo/x200/romstage.c
@@ -1,6 +1,6 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
-#include <southbridge/intel/common/gpio.h>
+#include <gpio.h>
 #include <northbridge/intel/gm45/gm45.h>
 
 void get_mb_spd_addrmap(u8 spd_addrmap[4])
@@ -13,5 +13,5 @@ void mb_post_raminit_setup(void)
 {
 	/* FIXME: make a proper SMBUS mux support. */
 	/* Set the SMBUS mux to the eeprom */
-	set_gpio(42, GPIO_LEVEL_LOW);
+	gpio_set(42, GPIO_LEVEL_LOW);
 }
diff --git a/src/mainboard/lenovo/x200/variants/x200/dock.c b/src/mainboard/lenovo/x200/variants/x200/dock.c
index a10772ede2..da085dc7aa 100644
--- a/src/mainboard/lenovo/x200/variants/x200/dock.c
+++ b/src/mainboard/lenovo/x200/variants/x200/dock.c
@@ -3,7 +3,6 @@
 #include <console/console.h>
 #include <device/device.h>
 #include <gpio.h>
-#include <southbridge/intel/common/gpio.h>
 #include <ec/lenovo/h8/h8.h>
 #include <ec/acpi/ec.h>
 
@@ -22,13 +21,13 @@ void h8_mb_init(void)
 void dock_connect(void)
 {
 	ec_set_bit(0x02, 0);
-	set_gpio(28, GPIO_LEVEL_HIGH);
+	gpio_set(28, GPIO_LEVEL_HIGH);
 }
 
 void dock_disconnect(void)
 {
 	ec_clr_bit(0x02, 0);
-	set_gpio(28, GPIO_LEVEL_LOW);
+	gpio_set(28, GPIO_LEVEL_LOW);
 }
 
 int dock_present(void)
diff --git a/src/mainboard/lenovo/x201/dock.c b/src/mainboard/lenovo/x201/dock.c
index a1bd1e81d7..202fc26f07 100644
--- a/src/mainboard/lenovo/x201/dock.c
+++ b/src/mainboard/lenovo/x201/dock.c
@@ -3,10 +3,9 @@
 #include <console/console.h>
 #include <device/device.h>
 #include <gpio.h>
-#include "dock.h"
-#include <southbridge/intel/common/gpio.h>
 #include <ec/lenovo/h8/h8.h>
 #include <ec/acpi/ec.h>
+#include "dock.h"
 
 void h8_mb_init(void)
 {
@@ -24,7 +23,7 @@ void dock_connect(void)
 	ec_set_bit(0x1a, 0);
 	ec_set_bit(0xfe, 4);
 
-	set_gpio(28, GPIO_LEVEL_HIGH);
+	gpio_set(28, GPIO_LEVEL_HIGH);
 }
 
 void dock_disconnect(void)
@@ -33,7 +32,7 @@ void dock_disconnect(void)
 	ec_clr_bit(0x1a, 0);
 	ec_clr_bit(0xfe, 4);
 
-	set_gpio(28, GPIO_LEVEL_LOW);
+	gpio_set(28, GPIO_LEVEL_LOW);
 }
 
 int dock_present(void)
diff --git a/src/southbridge/intel/common/gpio.c b/src/southbridge/intel/common/gpio.c
index a033ead057..8ce77fbcb6 100644
--- a/src/southbridge/intel/common/gpio.c
+++ b/src/southbridge/intel/common/gpio.c
@@ -105,7 +105,7 @@ int gpio_get(gpio_t gpio_num)
 /*
  * set gpio output to level.
  */
-void set_gpio(int gpio_num, int value)
+void gpio_set(gpio_t gpio_num, int value)
 {
 	static const int gpio_reg_offsets[] = {
 		GP_LVL, GP_LVL2, GP_LVL3
diff --git a/src/southbridge/intel/common/gpio.h b/src/southbridge/intel/common/gpio.h
index 4e47f18ae2..8c7b2301ac 100644
--- a/src/southbridge/intel/common/gpio.h
+++ b/src/southbridge/intel/common/gpio.h
@@ -151,8 +151,6 @@ extern const struct pch_gpio_map mainboard_gpio_map;
 /* Configure GPIOs with mainboard provided settings */
 void setup_pch_gpios(const struct pch_gpio_map *gpio);
 
-void set_gpio(int gpio_num, int value);
-
 void clear_gpio(int gpio_num);
 
 int gpio_is_native(int gpio_num);
diff --git a/src/southbridge/intel/lynxpoint/lp_gpio.c b/src/southbridge/intel/lynxpoint/lp_gpio.c
index 123e4a43f9..e5884e8d8d 100644
--- a/src/southbridge/intel/lynxpoint/lp_gpio.c
+++ b/src/southbridge/intel/lynxpoint/lp_gpio.c
@@ -110,7 +110,7 @@ int gpio_get(gpio_t gpio_num)
 	return !!(inl(gpio_base + GPIO_CONFIG0(gpio_num)) & GPI_LEVEL);
 }
 
-void set_gpio(int gpio_num, int value)
+void gpio_set(gpio_t gpio_num, int value)
 {
 	u16 gpio_base = get_gpio_base();
 	u32 conf0;
diff --git a/src/southbridge/intel/lynxpoint/lp_gpio.h b/src/southbridge/intel/lynxpoint/lp_gpio.h
index dd2a89a373..7c051b138b 100644
--- a/src/southbridge/intel/lynxpoint/lp_gpio.h
+++ b/src/southbridge/intel/lynxpoint/lp_gpio.h
@@ -157,9 +157,6 @@ struct pch_lp_gpio_map {
 /* Configure GPIOs with mainboard provided settings */
 void setup_pch_lp_gpios(const struct pch_lp_gpio_map map[]);
 
-/* Set GPIO pin value */
-void set_gpio(int gpio_num, int value);
-
 /* Return non-zero if gpio is set to native function. 0 otherwise. */
 int gpio_is_native(int gpio_num);
 

From 55bed620a4487fbc5db3dfe8175dff9960b96e9f Mon Sep 17 00:00:00 2001
From: Patrick Rudolph <patrick.rudolph@9elements.com>
Date: Mon, 21 Jul 2025 08:11:03 +0200
Subject: [PATCH 1680/3886] mb/dell: Use gpio_base2_value

Instead of open coding what gpio_base2_value() does use the
function to get the GPIO states of the ID pins.

Change-Id: Ib09993998f7e8ee2a7e5295f49ed14058a095eb0
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88505
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
---
 src/mainboard/dell/optiplex_9020/mainboard.c    |  4 ++--
 .../dell/snb_ivb_workstations/mainboard.c       | 17 +++++++----------
 .../dell/snb_ivb_workstations/sch5545_ec.c      |  7 +++----
 3 files changed, 12 insertions(+), 16 deletions(-)

diff --git a/src/mainboard/dell/optiplex_9020/mainboard.c b/src/mainboard/dell/optiplex_9020/mainboard.c
index 733efbb729..f4451aafd9 100644
--- a/src/mainboard/dell/optiplex_9020/mainboard.c
+++ b/src/mainboard/dell/optiplex_9020/mainboard.c
@@ -269,8 +269,8 @@ static uint8_t get_chassis_type(void)
 	uint8_t gpio_chassis_type;
 
 	// Read chassis type from GPIO
-	gpio_chassis_type = gpio_get(70) << 3 | gpio_get(38) << 2 |
-	gpio_get(17) << 1 | gpio_get(1);
+	const gpio_t chassis_id_pins[] = {1, 17, 38, 70};
+	gpio_chassis_type = gpio_base2_value(chassis_id_pins, ARRAY_SIZE(chassis_id_pins));
 
 	printk(BIOS_DEBUG, "GPIO chassis type = %#x\n", gpio_chassis_type);
 
diff --git a/src/mainboard/dell/snb_ivb_workstations/mainboard.c b/src/mainboard/dell/snb_ivb_workstations/mainboard.c
index 2c09e683dd..9a46d152a4 100644
--- a/src/mainboard/dell/snb_ivb_workstations/mainboard.c
+++ b/src/mainboard/dell/snb_ivb_workstations/mainboard.c
@@ -56,10 +56,9 @@ static void mainboard_enable(struct device *dev)
 					GMA_INT15_PANEL_FIT_DEFAULT,
 					GMA_INT15_BOOT_DISPLAY_DEFAULT, 0);
 
-	pin_sts = gpio_get(GPIO_CHASSIS_ID0);
-	pin_sts |= gpio_get(GPIO_CHASSIS_ID1) << 1;
-	pin_sts |= gpio_get(GPIO_CHASSIS_ID2) << 2;
-	pin_sts |= gpio_get(GPIO_FRONT_PANEL_CHASSIS_DET_L) << 3;
+	const gpio_t chassis_id_pins[] = {GPIO_CHASSIS_ID0, GPIO_CHASSIS_ID1,
+					  GPIO_CHASSIS_ID2, GPIO_FRONT_PANEL_CHASSIS_DET_L};
+	pin_sts = gpio_base2_value(chassis_id_pins, ARRAY_SIZE(chassis_id_pins));
 
 	printk(BIOS_DEBUG, "Chassis type: ");
 	switch (pin_sts) {
@@ -88,15 +87,13 @@ static void mainboard_enable(struct device *dev)
 		break;
 	}
 
-	pin_sts = gpio_get(GPIO_BOARD_REV0);
-	pin_sts |= gpio_get(GPIO_BOARD_REV1) << 1;
-	pin_sts |= gpio_get(GPIO_BOARD_REV2) << 2;
+	const gpio_t board_id_pins[] = {GPIO_BOARD_REV0, GPIO_BOARD_REV1, GPIO_BOARD_REV2};
+	pin_sts = gpio_base2_value(board_id_pins, ARRAY_SIZE(board_id_pins));
 
 	printk(BIOS_DEBUG, "Board revision: %d\n", pin_sts);
 
-	pin_sts = gpio_get(GPIO_SKU0);
-	pin_sts |= gpio_get(GPIO_SKU1) << 1;
-	pin_sts |= gpio_get(GPIO_SKU2) << 2;
+	const gpio_t sku_id_pins[] = {GPIO_SKU0, GPIO_SKU1, GPIO_SKU2};
+	pin_sts = gpio_base2_value(sku_id_pins, ARRAY_SIZE(sku_id_pins));
 
 	printk(BIOS_DEBUG, "SKU ID is %d:", pin_sts);
 	switch (pin_sts) {
diff --git a/src/mainboard/dell/snb_ivb_workstations/sch5545_ec.c b/src/mainboard/dell/snb_ivb_workstations/sch5545_ec.c
index a32c0fc937..2e9476d435 100644
--- a/src/mainboard/dell/snb_ivb_workstations/sch5545_ec.c
+++ b/src/mainboard/dell/snb_ivb_workstations/sch5545_ec.c
@@ -300,10 +300,9 @@ static uint8_t get_chassis_type(void)
 {
 	uint8_t chassis_id;
 
-	chassis_id  = gpio_get(GPIO_CHASSIS_ID0);
-	chassis_id |= gpio_get(GPIO_CHASSIS_ID1) << 1;
-	chassis_id |= gpio_get(GPIO_CHASSIS_ID2) << 2;
-	chassis_id |= gpio_get(GPIO_FRONT_PANEL_CHASSIS_DET_L) << 3;
+	const gpio_t chassis_id_pins[] = {GPIO_CHASSIS_ID0, GPIO_CHASSIS_ID1,
+					  GPIO_CHASSIS_ID2, GPIO_FRONT_PANEL_CHASSIS_DET_L};
+	chassis_id = gpio_base2_value(chassis_id_pins, ARRAY_SIZE(chassis_id_pins));
 
 	/* This mapping will determine which EC init sequence to use */
 	switch (chassis_id) {

From c54fde50402fb8ee1891866d0d44f568161ff7bc Mon Sep 17 00:00:00 2001
From: Patrick Rudolph <patrick.rudolph@9elements.com>
Date: Mon, 21 Jul 2025 09:15:39 +0200
Subject: [PATCH 1681/3886] sb/inte/common/gpio: Implement gpio_input() and
 gpio_output()

Implement the two functions defined as prototypes in gpio.h.
Allows to drop custom SMI handler code and use the generic function
from gpio.c instead.

Change-Id: I795af83374118d3fc2b46837b1822205c966fda6
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88508
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/southbridge/intel/bd82x6x/smihandler.c  | 45 +-----------
 src/southbridge/intel/common/gpio.c         | 76 ++++++++++++++++++++-
 src/southbridge/intel/ibexpeak/smihandler.c | 45 +-----------
 3 files changed, 80 insertions(+), 86 deletions(-)

diff --git a/src/southbridge/intel/bd82x6x/smihandler.c b/src/southbridge/intel/bd82x6x/smihandler.c
index d4833a2673..fa166a4244 100644
--- a/src/southbridge/intel/bd82x6x/smihandler.c
+++ b/src/southbridge/intel/bd82x6x/smihandler.c
@@ -10,64 +10,25 @@
 #include <device/pci_def.h>
 #include <device/pci_ops.h>
 #include <northbridge/intel/sandybridge/sandybridge.h>
+#include <gpio.h>
 #include <soc/nvs.h>
 #include <southbridge/intel/bd82x6x/me.h>
 #include <southbridge/intel/common/finalize.h>
-#include <southbridge/intel/common/gpio.h>
 #include <southbridge/intel/common/pmutil.h>
 #include <types.h>
 
 #include "pch.h"
 
-static void southbridge_gate_memory_reset_real(int offset,
-					       u16 use, u16 io, u16 lvl)
-{
-	u32 reg32;
-
-	/* Make sure it is set as GPIO */
-	reg32 = inl(use);
-	if (!(reg32 & (1 << offset))) {
-		reg32 |= (1 << offset);
-		outl(reg32, use);
-	}
-
-	/* Make sure it is set as output */
-	reg32 = inl(io);
-	if (reg32 & (1 << offset)) {
-		reg32 &= ~(1 << offset);
-		outl(reg32, io);
-	}
-
-	/* Drive the output low */
-	reg32 = inl(lvl);
-	reg32 &= ~(1 << offset);
-	outl(reg32, lvl);
-}
-
 /*
- * Drive GPIO 60 low to gate memory reset in S3.
+ * Drive reset gate GPIO low to gate memory reset in S3.
  *
  * Intel reference designs all use GPIO 60 but it is
  * not a requirement and boards could use a different pin.
  */
 void southbridge_gate_memory_reset(void)
 {
-	u16 gpiobase;
 
-	gpiobase = pci_read_config16(PCH_LPC_DEV, GPIOBASE) & 0xfffc;
-	if (!gpiobase)
-		return;
-
-	if (CONFIG_DRAM_RESET_GATE_GPIO >= 32)
-		southbridge_gate_memory_reset_real(CONFIG_DRAM_RESET_GATE_GPIO - 32,
-						   gpiobase + GPIO_USE_SEL2,
-						   gpiobase + GP_IO_SEL2,
-						   gpiobase + GP_LVL2);
-	else
-		southbridge_gate_memory_reset_real(CONFIG_DRAM_RESET_GATE_GPIO,
-						   gpiobase + GPIO_USE_SEL,
-						   gpiobase + GP_IO_SEL,
-						   gpiobase + GP_LVL);
+	gpio_output(CONFIG_DRAM_RESET_GATE_GPIO, 0);
 }
 
 void southbridge_smi_monitor(void)
diff --git a/src/southbridge/intel/common/gpio.c b/src/southbridge/intel/common/gpio.c
index 8ce77fbcb6..a1b2b5426b 100644
--- a/src/southbridge/intel/common/gpio.c
+++ b/src/southbridge/intel/common/gpio.c
@@ -146,7 +146,79 @@ int gpio_is_native(int gpio_num)
 	return !(config & (1 << bit));
 }
 
-void gpio_input(gpio_t gpio)
+static void gpio_set_gpio(gpio_t gpio_num)
 {
-	// FIXME: Implement
+	static const int gpio_use_reg_offsets[] = {
+		GPIO_USE_SEL, GPIO_USE_SEL2, GPIO_USE_SEL3
+	};
+	u16 gpio_base = get_gpio_base();
+	int index, bit;
+	u32 config;
+
+	if (gpio_num > MAX_GPIO_NUMBER)
+		return; /* Just ignore wrong gpio numbers. */
+
+	index = gpio_num / 32;
+	bit = gpio_num % 32;
+
+	config = inl(gpio_base + gpio_use_reg_offsets[index]);
+	if (config & (GPIO_MODE_GPIO << bit))
+		return;
+
+	config |= GPIO_MODE_GPIO << bit;
+	outl(gpio_base + gpio_use_reg_offsets[index], config);
+}
+
+void gpio_input(gpio_t gpio_num)
+{
+	static const int gpio_io_reg_offsets[] = {
+		GP_IO_SEL, GP_IO_SEL2, GP_IO_SEL3
+	};
+	u16 gpio_base = get_gpio_base();
+	int index, bit;
+	u32 config;
+
+	if (gpio_num > MAX_GPIO_NUMBER)
+		return; /* Just ignore wrong gpio numbers. */
+
+	gpio_set_gpio(gpio_num);
+
+	index = gpio_num / 32;
+	bit = gpio_num % 32;
+
+	config = inl(gpio_base + gpio_io_reg_offsets[index]);
+	if (((config >> bit) & 1) == GPIO_DIR_INPUT)
+		return;
+
+	config |= 1 << bit;
+	outl(gpio_base + gpio_io_reg_offsets[index], config);
+}
+
+void gpio_output(gpio_t gpio_num, int value)
+{
+	static const int gpio_io_reg_offsets[] = {
+		GP_IO_SEL, GP_IO_SEL2, GP_IO_SEL3
+	};
+	u16 gpio_base = get_gpio_base();
+	int index, bit;
+	u32 config;
+
+	if (gpio_num > MAX_GPIO_NUMBER)
+		return; /* Just ignore wrong gpio numbers. */
+
+	gpio_set_gpio(gpio_num);
+	gpio_set(gpio_num, value);
+
+	index = gpio_num / 32;
+	bit = gpio_num % 32;
+
+	config = inl(gpio_base + gpio_io_reg_offsets[index]);
+	if (((config >> bit) & 1) == GPIO_DIR_OUTPUT)
+		return;
+
+	config &= ~(1 << bit);
+	outl(gpio_base + gpio_io_reg_offsets[index], config);
+
+	/* Set value again in case output register was gated */
+	gpio_set(gpio_num, value);
 }
diff --git a/src/southbridge/intel/ibexpeak/smihandler.c b/src/southbridge/intel/ibexpeak/smihandler.c
index cb4f65ea95..5ced6a7c04 100644
--- a/src/southbridge/intel/ibexpeak/smihandler.c
+++ b/src/southbridge/intel/ibexpeak/smihandler.c
@@ -7,6 +7,7 @@
 #include <device/pci_def.h>
 #include <cpu/intel/em64t101_save_state.h>
 #include <cpu/intel/model_2065x/model_2065x.h>
+#include <gpio.h>
 #include <southbridge/intel/common/finalize.h>
 #include <southbridge/intel/common/pmbase.h>
 #include <southbridge/intel/ibexpeak/me.h>
@@ -17,58 +18,18 @@
  *  2. we don't need to worry about how we leave 0xcf8/0xcfc behind
  */
 #include <northbridge/intel/ironlake/ironlake.h>
-#include <southbridge/intel/common/gpio.h>
 #include <southbridge/intel/common/pmutil.h>
 
-static void southbridge_gate_memory_reset_real(int offset,
-					       u16 use, u16 io, u16 lvl)
-{
-	u32 reg32;
-
-	/* Make sure it is set as GPIO */
-	reg32 = inl(use);
-	if (!(reg32 & (1 << offset))) {
-		reg32 |= (1 << offset);
-		outl(reg32, use);
-	}
-
-	/* Make sure it is set as output */
-	reg32 = inl(io);
-	if (reg32 & (1 << offset)) {
-		reg32 &= ~(1 << offset);
-		outl(reg32, io);
-	}
-
-	/* Drive the output low */
-	reg32 = inl(lvl);
-	reg32 &= ~(1 << offset);
-	outl(reg32, lvl);
-}
-
 /*
- * Drive GPIO 60 low to gate memory reset in S3.
+ * Drive reset gate GPIO low to gate memory reset in S3.
  *
  * Intel reference designs all use GPIO 60 but it is
  * not a requirement and boards could use a different pin.
  */
 void southbridge_gate_memory_reset(void)
 {
-	u16 gpiobase;
 
-	gpiobase = pci_read_config16(PCI_DEV(0, 0x1f, 0), GPIOBASE) & 0xfffc;
-	if (!gpiobase)
-		return;
-
-	if (CONFIG_DRAM_RESET_GATE_GPIO >= 32)
-		southbridge_gate_memory_reset_real(CONFIG_DRAM_RESET_GATE_GPIO - 32,
-						   gpiobase + GPIO_USE_SEL2,
-						   gpiobase + GP_IO_SEL2,
-						   gpiobase + GP_LVL2);
-	else
-		southbridge_gate_memory_reset_real(CONFIG_DRAM_RESET_GATE_GPIO,
-						   gpiobase + GPIO_USE_SEL,
-						   gpiobase + GP_IO_SEL,
-						   gpiobase + GP_LVL);
+	gpio_output(CONFIG_DRAM_RESET_GATE_GPIO, 0);
 }
 
 void southbridge_smi_monitor(void)

From e272b20c8526b0a42b7c7957dfbc5edc013c1c93 Mon Sep 17 00:00:00 2001
From: Patrick Rudolph <patrick.rudolph@9elements.com>
Date: Mon, 21 Jul 2025 08:44:28 +0200
Subject: [PATCH 1682/3886] sb/intel/common: Remove unused function prototype

Drop clear_gpio() since it's unused.

Change-Id: Ic5359f7689d7f633c34605cab107ba3623d0b806
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88507
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/southbridge/intel/common/gpio.h | 2 --
 1 file changed, 2 deletions(-)

diff --git a/src/southbridge/intel/common/gpio.h b/src/southbridge/intel/common/gpio.h
index 8c7b2301ac..71154a6066 100644
--- a/src/southbridge/intel/common/gpio.h
+++ b/src/southbridge/intel/common/gpio.h
@@ -151,8 +151,6 @@ extern const struct pch_gpio_map mainboard_gpio_map;
 /* Configure GPIOs with mainboard provided settings */
 void setup_pch_gpios(const struct pch_gpio_map *gpio);
 
-void clear_gpio(int gpio_num);
-
 int gpio_is_native(int gpio_num);
 
 #endif

From 1a9fb29a53ca31a08677fa461c775f009a5f14d9 Mon Sep 17 00:00:00 2001
From: Swathi Tamilselvan <tswathi@qualcomm.corp-partner.google.com>
Date: Wed, 16 Jul 2025 10:23:54 +0530
Subject: [PATCH 1683/3886] soc/qualcomm/common: Add API to enable Zondaole PLL
 for X1P42100

Add API to enable Zondaole PLL.

TEST=Create an image.serial.bin and ensure it boots on X1P42100.

Change-Id: I80e0b97eeda1bdd10059cc571c1258909df446f1
Signed-off-by: Swathi Tamilselvan <tswathi@qualcomm.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88531
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/soc/qualcomm/common/clock.c               | 22 +++++++++++++++++++
 .../common/include/soc/clock_common.h         |  7 ++++++
 2 files changed, 29 insertions(+)

diff --git a/src/soc/qualcomm/common/clock.c b/src/soc/qualcomm/common/clock.c
index cd700a3224..1768566f7c 100644
--- a/src/soc/qualcomm/common/clock.c
+++ b/src/soc/qualcomm/common/clock.c
@@ -271,6 +271,28 @@ enum cb_err zonda_pll_enable(struct alpha_pll_reg_val_config *cfg)
 	return CB_SUCCESS;
 }
 
+enum cb_err zondaole_pll_enable(struct alpha_pll_reg_val_config *cfg)
+{
+	setbits32(cfg->reg_mode, BIT(PLL_BYPASSNL_SHFT));
+
+	/*
+	 * H/W requires a 1us delay between disabling the bypass and
+	 * de-asserting the reset.
+	 */
+	udelay(1);
+	setbits32(cfg->reg_mode, BIT(PLL_RESET_SHFT));
+	setbits32(cfg->reg_opmode, PLL_RUN_MODE);
+
+	if (!wait_us(100, read32(cfg->reg_mode) & PLL_LOCK_DET_BMSK)) {
+		printk(BIOS_ERR, "CPU PLL did not lock!\n");
+		return CB_ERR;
+	}
+
+	setbits32(cfg->reg_mode, BIT(PLL_OUTCTRL_SHFT));
+
+	return CB_SUCCESS;
+}
+
 /* Bring subsystem out of RESET */
 void clock_reset_subsystem(u32 *misc, u32 shft)
 {
diff --git a/src/soc/qualcomm/common/include/soc/clock_common.h b/src/soc/qualcomm/common/include/soc/clock_common.h
index 2c127429e1..6dd9bfecc8 100644
--- a/src/soc/qualcomm/common/include/soc/clock_common.h
+++ b/src/soc/qualcomm/common/include/soc/clock_common.h
@@ -169,6 +169,13 @@ enum cb_err agera_pll_enable(struct alpha_pll_reg_val_config *cfg);
 
 enum cb_err zonda_pll_enable(struct alpha_pll_reg_val_config *cfg);
 
+/*
+ * zondaole_pll_enable(): Enable Zondaole PLL at the given configuration (cfg).
+ *
+ * @param cfg		struct alpha_pll_reg_val_config
+ */
+enum cb_err zondaole_pll_enable(struct alpha_pll_reg_val_config *cfg);
+
 struct aoss {
 	u8 _res0[0x50020];
 	u32 aoss_cc_reset_status;

From fc4911ec35a3635b9ed1f33432ce24365bb58a15 Mon Sep 17 00:00:00 2001
From: Swathi Tamilselvan <tswathi@qualcomm.corp-partner.google.com>
Date: Tue, 22 Jul 2025 11:16:03 +0530
Subject: [PATCH 1684/3886] soc/qualcomm/x1p42100: Add CPU Clock boost support
 for X1P42100

Add support to increase the CPU clock frequency to 1.36(GHz).
The register details are part of HRD-X1P42100-S1 document.
https://docs.qualcomm.com/bundle/resource/topics/HRD-X1P42100-S1/

TEST=Create an image.serial.bin and ensure it boots on X1P42100 and
CPU runs in 1.36GHz Frequency.

Change-Id: Ie51e032141bdfabf4c96b6891ec9f084561d97ff
Signed-off-by: Swathi Tamilselvan <tswathi@qualcomm.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88532
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
---
 src/soc/qualcomm/x1p42100/clock.c             | 48 ++++++++++++++-
 .../x1p42100/include/soc/addressmap.h         |  5 ++
 src/soc/qualcomm/x1p42100/include/soc/clock.h | 60 ++++++++++++++++++-
 3 files changed, 111 insertions(+), 2 deletions(-)

diff --git a/src/soc/qualcomm/x1p42100/clock.c b/src/soc/qualcomm/x1p42100/clock.c
index 510c2ca559..0e6fa8e0a7 100644
--- a/src/soc/qualcomm/x1p42100/clock.c
+++ b/src/soc/qualcomm/x1p42100/clock.c
@@ -339,9 +339,55 @@ void clock_configure_pcie(void)
 			pcie_core_cfg, PCIE_PHY_RCHNG_FREQ, ARRAY_SIZE(pcie_core_cfg));
 }
 
+static enum cb_err pll_init_and_set(struct x1p42100_ncc0_clock *ncc0, u32 l_val)
+{
+	int ret;
+	struct alpha_pll_reg_val_config ncc0_pll_cfg = {0};
+
+	setbits64p(NCC0_NCC_CMU_NCC_CLK_CFG, (BIT(PLLSWCTL) | BIT(OVRCKMUXPLLFASTCLK)));
+
+	setbits64p(NCC0_NCC_CMU_NCC_PLL_CFG,
+		(((LOCKTMOUTCNT_VAL & LOCKTMOUTCNT_BMSK) << LOCKTMOUTCNT) |
+		((LOCKDEASSERTTMOUTCNT_VAL & LOCKDEASSERTTMOUTCNT_BMSK) << LOCKDEASSERTTMOUTCNT)));
+
+	ncc0_pll_cfg.reg_config_ctl = &ncc0->pll0_config_ctl;
+
+	ncc0_pll_cfg.config_ctl_val = (read32(ncc0_pll_cfg.reg_config_ctl) |
+					PFA_MSB_VAL << PFA_MSB |
+					RON_DEGEN_MULTIPLY_VAL << RON_DEGEN_MULTIPLY |
+					FBC_ALPHA_CAL_VAL << FBC_ALPHA_CAL |
+					PLL_COUNTER_ENABLE_VAL << PLL_COUNTER_ENABLE);
+
+	ncc0_pll_cfg.reg_config_ctl_hi = &ncc0->pll0_config_ctl_u;
+	ncc0_pll_cfg.config_ctl_hi_val = (read32(ncc0_pll_cfg.reg_config_ctl_hi) |
+					CHP_REF_CUR_TRIM_VAL << CHP_REF_CUR_TRIM |
+					ADC_KLSB_VALUE_VAL << ADC_KLSB_VALUE |
+					ADC_KMSB_VALUE_VAL << ADC_KMSB_VALUE);
+
+	ncc0_pll_cfg.reg_l = &ncc0->pll0_l;
+	ncc0_pll_cfg.l_val = l_val;
+
+	ncc0_pll_cfg.reg_alpha = &ncc0->pll0_alpha;
+	ncc0_pll_cfg.alpha_val = 0x00;
+
+	clock_configure_enable_gpll(&ncc0_pll_cfg, false, 0);
+
+	ncc0_pll_cfg.reg_mode = &ncc0->pll0_mode;
+	ncc0_pll_cfg.reg_opmode = &ncc0->pll0_opmode;
+	ret =  zondaole_pll_enable(&ncc0_pll_cfg);
+	if (ret != CB_SUCCESS)
+		return CB_ERR;
+
+	setbits64p(NCC0_NCC_CMU_NCC_CLK_CFG, BIT(SELCKMUXPLLFASTCLK));
+
+	return CB_SUCCESS;
+}
+
 static void speed_up_boot_cpu(void)
 {
-	/* Placeholder */
+	/* 1363.2 MHz */
+	if (!pll_init_and_set(apss_ncc0, L_VAL_1363P2MHz))
+		printk(BIOS_DEBUG, "NCC Frequency bumped to 1.363(GHz)\n");
 }
 
 void clock_init(void)
diff --git a/src/soc/qualcomm/x1p42100/include/soc/addressmap.h b/src/soc/qualcomm/x1p42100/include/soc/addressmap.h
index c79f300bd2..3f66326a12 100644
--- a/src/soc/qualcomm/x1p42100/include/soc/addressmap.h
+++ b/src/soc/qualcomm/x1p42100/include/soc/addressmap.h
@@ -9,6 +9,11 @@
 #define QSPI_BASE			0x088DC000
 #define TLMM_TILE_BASE			0x0F100000
 #define GCC_BASE			0x00100000
+#define NCC0_BASE			0x19A30000
+
+/* X1P42100 NCC0 PLL CONFIG ADDRESSES */
+#define NCC0_NCC_CMU_NCC_PLL_CFG	0x199A2010
+#define NCC0_NCC_CMU_NCC_CLK_CFG	0x199A2030
 
 /* X1P42100 QSPI GPIO PINS */
 #define QSPI_CS				GPIO(132)
diff --git a/src/soc/qualcomm/x1p42100/include/soc/clock.h b/src/soc/qualcomm/x1p42100/include/soc/clock.h
index 82556341ca..06b573650d 100644
--- a/src/soc/qualcomm/x1p42100/include/soc/clock.h
+++ b/src/soc/qualcomm/x1p42100/include/soc/clock.h
@@ -13,6 +13,9 @@
 #define GPLL0_MAIN_HZ		(600 * MHz)
 #define CLK_100MHZ		(100 * MHz)
 
+/* CPU PLL*/
+#define L_VAL_1363P2MHz		0x47
+
 #define PCIE_PHY_RCHNG_FREQ CLK_100MHZ
 
 #define QUPV3_WRAP0_CLK_ENA_S(idx)		(10 + idx)
@@ -22,6 +25,21 @@
 #define QUPV3_WRAP1_SE7_CLK_ENA			16
 #define QUPV3_WRAP2_SE7_CLK_ENA			17
 
+#define LOCKDEASSERTTMOUTCNT_BMSK		0xFFF
+#define LOCKTMOUTCNT_BMSK			0xFFFF
+
+#define LOCKDEASSERTTMOUTCNT_VAL		960LL
+#define LOCKTMOUTCNT_VAL			960LL
+
+#define PFA_MSB_VAL				2
+#define RON_DEGEN_MULTIPLY_VAL			1
+#define FBC_ALPHA_CAL_VAL			2
+#define PLL_COUNTER_ENABLE_VAL			1
+
+#define CHP_REF_CUR_TRIM_VAL			1
+#define ADC_KLSB_VALUE_VAL			4
+#define ADC_KMSB_VALUE_VAL			10
+
 enum clk_ctl_gpll_user_ctl_x1p42100 {
 	PLL_PLLOUT_MAIN_SHFT_X1P42100 = 0,
 	PLL_PLLOUT_EVEN_SHFT_X1P42100 = 1,
@@ -83,6 +101,30 @@ enum apcs_branch_en_vote {
 	NO_VOTE_BIT = -1,
 };
 
+enum ncc0_cmu_clk_cfg_x1p42100 {
+	OVRCKMUXPLLFASTCLK = 2,
+	SELCKMUXPLLFASTCLK = 3,
+	PLLSWCTL = 25,
+};
+
+enum ncc0_cmu_pll_cfg_x1p42100 {
+	LOCKTMOUTCNT = 0,
+	LOCKDEASSERTTMOUTCNT = 32,
+};
+
+enum ncc0_pll0_config_ctl {
+	PFA_MSB = 10,
+	RON_DEGEN_MULTIPLY = 18,
+	FBC_ALPHA_CAL = 20,
+	PLL_COUNTER_ENABLE = 27,
+};
+
+enum ncc0_pll0_config_ctl_u {
+	CHP_REF_CUR_TRIM = 0,
+	ADC_KLSB_VALUE = 13,
+	ADC_KMSB_VALUE = 23,
+};
+
 struct x1p42100_gpll {
 	u32 mode;
 	u32 opmode;
@@ -97,6 +139,22 @@ struct x1p42100_gpll {
 	u32 config_ctl_u1;
 };
 
+struct x1p42100_ncc0_clock {
+	u32 pll0_mode;
+	u32 pll0_l;
+	u32 pll0_alpha;
+	u32 pll0_user_ctl;
+	u32 pll0_user_ctl_u;
+	u32 pll0_config_ctl;
+	u32 pll0_config_ctl_u;
+	u32 pll0_config_ctl_u1;
+	u32 pll0_config_ctl_u2;
+	u32 pll0_test_ctl;
+	u32 pll0_test_ctl_u;
+	u32 pll0_test_ctl_u1;
+	u32 pll0_opmode;
+};
+
 struct x1p42100_pcie_noc {
 	u32 anoc_pcie_at_cbcr;
 	u32 anoc_pcie_tsctr_cbcr;
@@ -336,5 +394,5 @@ enum cb_err clock_configure_mux(enum clk_pcie clk_type, u32 src_type);
 /* Subsystem Reset */
 static struct aoss *const aoss = (void *)AOSS_CC_BASE;
 static struct x1p42100_gcc *const gcc = (void *)GCC_BASE;
-
+static struct x1p42100_ncc0_clock *const apss_ncc0 = (void *)NCC0_BASE;
 #endif	// __SOC_QUALCOMM_X1P42100_CLOCK_H__

From 85b26f75d2174afd648fc8a6df17679e770f6f5d Mon Sep 17 00:00:00 2001
From: Jincheng Li <jincheng.li@intel.com>
Date: Mon, 21 Jul 2025 18:16:12 +0800
Subject: [PATCH 1685/3886] soc/intel/xeon_sp: Remove
 fast_spi_cache_bios_region

FSP-T will help to cache bios region along with MTRR programming
by setting CodeRegionBase/CodeRegionLength, thus there is no need
for xeon_sp platforms to do it.

TEST=Build and boot on intel/avenuecity CRB
TEST=Build and boot on intel/archercity CRB

Check MTRR usage and below duplicated MTRR item get removed:
[DEBUG]  0x00000000ff000005: PHYBASE1: Address = 0x00000000ff000000, WP
[DEBUG]  0x000fffffff000800: PHYMASK1: Length  = 0x0000000001000000, Valid

Change-Id: Ia414a35c663f3aa1b02d944475a96e11d07a4f00
Signed-off-by: Jincheng Li <jincheng.li@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88533
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
---
 src/soc/intel/xeon_sp/bootblock.c | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/src/soc/intel/xeon_sp/bootblock.c b/src/soc/intel/xeon_sp/bootblock.c
index 49548ed9ef..1e9c3bbc62 100644
--- a/src/soc/intel/xeon_sp/bootblock.c
+++ b/src/soc/intel/xeon_sp/bootblock.c
@@ -73,14 +73,13 @@ asmlinkage void bootblock_c_entry(uint64_t base_timestamp)
 	 */
 	assembly_timestamp = base_timestamp;
 	bootblock_timestamp = timestamp_get();
-	fast_spi_early_init(SPI_BASE_ADDRESS);
-	fast_spi_cache_bios_region();
 
 	bootblock_main_with_basetime(MIN(assembly_timestamp, bootblock_timestamp));
 }
 
 void bootblock_soc_early_init(void)
 {
+	fast_spi_early_init(SPI_BASE_ADDRESS);
 	pch_enable_lpc();
 
 	/* Set up P2SB BAR. This is needed for PCR to work */

From eb005f5f5c7ab1c59720475a24903f6d5c94dee1 Mon Sep 17 00:00:00 2001
From: Curtis Chen <curtis.chen@intel.com>
Date: Fri, 18 Jul 2025 16:12:27 +0800
Subject: [PATCH 1686/3886] mb/google/brya/var: Clarify comment for
 'tcss_aux_ori'

For the latest trulo projects: kaladin,pujjolo,pujjocent,
the original comment was too brief and led to some misunderstanding.
In the past years, only retimer has the SBU muxing function. Or said,
only retimer has Aux Orientation feature. So, 'no retimer' implies
Aux Orientation feature inside the processor is needed.

And now, the modern future PDC also has the Aux Orientation feature.
Not all "no retimer" cases require setting the override bit anymore.
The even numbered bits should be set only when there is no retimer and
the processor's Aux Orientation is still required.
(If set, the SoC inverts the orientation value coming from EC/PDC when
operating in flipped orientation.)

In the referenced issue tracker, the system has 'no retimer' and uses
a 'future PDC'. (The PDC has the Aux Orientation feature.)
Test results (DP + TCSS):
  - 'tcss_aux_ori' = 0 + PDC sends orientation detected value -> PASS
  - 'tcss_aux_ori' = 5 + PDC sends 'original' value           -> PASS
  - 'tcss_aux_ori' = 5 + PDC sends orientation detected value -> FAIL
     (Fail means only display one side.)

This patch updates the comment to more accurately describe the expected
usage and avoid future confusion.

Refer doc#:
646929 TWL PDG
734752 TCSS Cookbook (MTL Backward/MTL/PTL/WCL)
627270 TWL Bios Spec
758766 MTL Bios Spec
766031 MTL PDG

BUG=b:4292672
BRANCH=none
TEST=Update coreboot device tree with different tcss_aux_ori value and
     test the DP connection via TCSS on 2 orientations.

Change-Id: I3281110e522c53a35abf30fd1c372bb5ca18c10d
Signed-off-by: Curtis Chen <curtis.chen@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88482
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/google/brya/variants/kaladin/overridetree.cb   | 5 ++++-
 .../google/brya/variants/pujjocento/overridetree.cb          | 5 ++++-
 src/mainboard/google/brya/variants/pujjolo/overridetree.cb   | 5 ++++-
 3 files changed, 12 insertions(+), 3 deletions(-)

diff --git a/src/mainboard/google/brya/variants/kaladin/overridetree.cb b/src/mainboard/google/brya/variants/kaladin/overridetree.cb
index c58dc8659d..b46584a491 100644
--- a/src/mainboard/google/brya/variants/kaladin/overridetree.cb
+++ b/src/mainboard/google/brya/variants/kaladin/overridetree.cb
@@ -52,7 +52,10 @@ chip soc/intel/alderlake
 	# This is a bitfield that corresponds to up to 4 TCSS ports.
 	# Bits (0,1) allocated for TCSS Port1 configuration and Bits (2,3)for TCSS Port2.
 	# TcssAuxOri = 0101b
-	# Bit0,Bit2 set to "1" indicates no retimer on USBC Ports
+	# Set Bit0 and Bit2 to "1" to enable the Aux Orientation feature inside the processor.
+        # This only should be set when no retimer is present and processor-level Aux Orientation
+        # is still needed. (E.g. The PDC does not have Aux Orientation feature.)
+        # Bits 0 and 2 must be enabled first before configuring Bits 1 and 3 to be "1".
 	# Bit1,Bit3 set to "0" indicates Aux lines are not swapped on the
 	# motherboard to USBC connector
 	register "tcss_aux_ori" = "0"
diff --git a/src/mainboard/google/brya/variants/pujjocento/overridetree.cb b/src/mainboard/google/brya/variants/pujjocento/overridetree.cb
index d84f1000ea..cdf996e53a 100644
--- a/src/mainboard/google/brya/variants/pujjocento/overridetree.cb
+++ b/src/mainboard/google/brya/variants/pujjocento/overridetree.cb
@@ -60,7 +60,10 @@ chip soc/intel/alderlake
 	# This is a bitfield that corresponds to up to 4 TCSS ports.
 	# Bits (0,1) allocated for TCSS Port1 configuration and Bits (2,3)for TCSS Port2.
 	# TcssAuxOri = 0101b
-	# Bit0,Bit2 set to "1" indicates no retimer on USBC Ports
+	# Set Bit0 and Bit2 to "1" to enable the Aux Orientation feature inside the processor.
+        # This only should be set when no retimer is present and processor-level Aux Orientation
+        # is still needed. (E.g. The PDC does not have Aux Orientation feature.)
+        # Bits 0 and 2 must be enabled first before configuring Bits 1 and 3 to be "1".
 	# Bit1,Bit3 set to "0" indicates Aux lines are not swapped on the
 	# motherboard to USBC connector
 	register "tcss_aux_ori" = "0"
diff --git a/src/mainboard/google/brya/variants/pujjolo/overridetree.cb b/src/mainboard/google/brya/variants/pujjolo/overridetree.cb
index a68adf5425..e79d5988e7 100644
--- a/src/mainboard/google/brya/variants/pujjolo/overridetree.cb
+++ b/src/mainboard/google/brya/variants/pujjolo/overridetree.cb
@@ -52,7 +52,10 @@ chip soc/intel/alderlake
 	# This is a bitfield that corresponds to up to 4 TCSS ports.
 	# Bits (0,1) allocated for TCSS Port1 configuration and Bits (2,3)for TCSS Port2.
 	# TcssAuxOri = 0101b
-	# Bit0,Bit2 set to "1" indicates no retimer on USBC Ports
+	# Set Bit0 and Bit2 to "1" to enable the Aux Orientation feature inside the processor.
+        # This only should be set when no retimer is present and processor-level Aux Orientation
+        # is still needed. (E.g. The PDC does not have Aux Orientation feature.)
+        # Bits 0 and 2 must be enabled first before configuring Bits 1 and 3 to be "1".
 	# Bit1,Bit3 set to "0" indicates Aux lines are not swapped on the
 	# motherboard to USBC connector
 	register "tcss_aux_ori" = "0"

From 87d5c7224bf91e308c9c9f82f7ea94c538d6450d Mon Sep 17 00:00:00 2001
From: Luca Lai <luca.lai@lcfc.corp-partner.google.com>
Date: Wed, 16 Jul 2025 15:31:38 +0800
Subject: [PATCH 1687/3886] mb/google/trulo/var/pujjolo: Select Strauss
 keyboard to show G icon

Because the machine shows circle icon instead of G icon in 'Setting'
->'Device'->'View keyboard shortcuts'.
So add MAINBOARD_HAS_GOOGLE_STRAUSS_KEYBOARD to enable G icon.

BUG=b:429495479
BRANCH=none
TEST= Build and boot to OS and enter 'Setting'->'Device'
->'View keyboard shortcuts' to see G icon.

Change-Id: I0a195c65fe2835f9be66c56fb7129851b3251b90
Signed-off-by: Luca Lai <luca.lai@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88446
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
---
 src/mainboard/google/brya/Kconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/src/mainboard/google/brya/Kconfig b/src/mainboard/google/brya/Kconfig
index a635ed0cb8..9d2d40c397 100644
--- a/src/mainboard/google/brya/Kconfig
+++ b/src/mainboard/google/brya/Kconfig
@@ -512,6 +512,7 @@ config BOARD_GOOGLE_PUJJOLO
 	select DRIVERS_I2C_SX9324_SUPPORT_LEGACY_LINUX_DRIVER
 	select ENFORCE_MEM_CHANNEL_DISABLE
 	select HAVE_WWAN_POWER_SEQUENCE
+	select MAINBOARD_HAS_GOOGLE_STRAUSS_KEYBOARD
 	select SOC_INTEL_COMMON_BLOCK_HDA_VERB
 	select SOC_INTEL_TCSS_USE_PDC_PMC_USBC_MUX_CONFIGURATION
 	select SOC_INTEL_TWINLAKE

From 953957e9613b8eddf3a983cb6e205de6ea8ae1a4 Mon Sep 17 00:00:00 2001
From: Luca Lai <luca.lai@lcfc.corp-partner.google.com>
Date: Fri, 25 Jul 2025 09:34:34 +0800
Subject: [PATCH 1688/3886] mb/google/trulo/var/pujjolo: Change ICCmax at
 VCCIN_AUX from 25A to 27A

Becasue of requirement for VCCANA power from MBVR mode to FIVR mode,
so change ICCmax at VCCIN_AUX will be from 25A to 27A due to
internal VR.

BUG=b:417662158
TEST=Build and boot to OS at the rework motherboard and verfied by
power team.

Change-Id: Ie036412c0e435cfce39940de6bab363f9e875f42
Signed-off-by: Luca Lai <luca.lai@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88558
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 .../google/brya/variants/pujjolo/Makefile.mk          |  1 +
 src/mainboard/google/brya/variants/pujjolo/ramstage.c | 11 +++++++++++
 2 files changed, 12 insertions(+)
 create mode 100644 src/mainboard/google/brya/variants/pujjolo/ramstage.c

diff --git a/src/mainboard/google/brya/variants/pujjolo/Makefile.mk b/src/mainboard/google/brya/variants/pujjolo/Makefile.mk
index 98cf9a8419..4a6700c6ec 100644
--- a/src/mainboard/google/brya/variants/pujjolo/Makefile.mk
+++ b/src/mainboard/google/brya/variants/pujjolo/Makefile.mk
@@ -6,4 +6,5 @@ romstage-y += memory.c
 
 ramstage-y += gpio.c
 ramstage-y += variant.c
+ramstage-y += ramstage.c
 ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_HDA_VERB) += hda_verb.c
diff --git a/src/mainboard/google/brya/variants/pujjolo/ramstage.c b/src/mainboard/google/brya/variants/pujjolo/ramstage.c
new file mode 100644
index 0000000000..5cb79a81b9
--- /dev/null
+++ b/src/mainboard/google/brya/variants/pujjolo/ramstage.c
@@ -0,0 +1,11 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <soc/ramstage.h>
+
+void mainboard_silicon_init_params(FSP_S_CONFIG *params)
+{
+	/* Refer to FSP Silicon (soc/intel/alderlake/fsp_params.c)
+	   VccIn Aux Imon IccMax. Values are in 1/4 Amp increments */
+	params->VccInAuxImonIccImax = 108; /* 30000(30A) * 4 / 1000 */
+	printk(BIOS_INFO, "Override VccInAuxImonIccImax = %d\n", params->VccInAuxImonIccImax);
+}

From 5537ce7c2f85584652b396840988364dd0f22439 Mon Sep 17 00:00:00 2001
From: Zhixing Ma <zhixing.ma@intel.com>
Date: Fri, 25 Jul 2025 12:46:32 -0700
Subject: [PATCH 1689/3886] mb/google/fatcat: Fix GPIO config for headphone
 jack detection

This commit updates GPP_F17 (CODEC_INIT_N) configuration to fix an issue
with the 3.5mm headphone jack on the I2S codec AIC not detecting
headphone plug/unplug events. Specifically, we need to configure GPP_F17 to have interrupt capability, edge detection to detect plug and unplug events, and power state persistence.

BUG=b:434208278
TEST=After booting to OS, plug and unplug a headphone to the I2S codec
add-in card, headphone is getting detected.

Change-Id: I1c662ec680d8175be5854c753ea1481d09afb561
Signed-off-by: Zhixing Ma <zhixing.ma@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88564
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/google/fatcat/variants/fatcat/gpio.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/mainboard/google/fatcat/variants/fatcat/gpio.c b/src/mainboard/google/fatcat/variants/fatcat/gpio.c
index 4b6462a60e..d8dd67c034 100644
--- a/src/mainboard/google/fatcat/variants/fatcat/gpio.c
+++ b/src/mainboard/google/fatcat/variants/fatcat/gpio.c
@@ -270,7 +270,7 @@ static const struct pad_config gpio_table[] = {
 	/* GPP_F13:     THC_I2C1_SDA_TCH_PAD */
 	PAD_CFG_NF(GPP_F13, NONE, DEEP, NF8),
 	/* GPP_F17:     CODEC_INT_N */
-	PAD_CFG_GPI(GPP_F17, NONE, DEEP),
+	PAD_CFG_GPI_INT(GPP_F17, NONE, PLTRST, EDGE_BOTH),
 	/* GPP_F18:     TCH_PAD_INT_N */
 	/* NOTE: require rework to switch from GPP_A13 to GPP_F18 */
 	PAD_CFG_GPI_APIC(GPP_F18, NONE, PLTRST, LEVEL, INVERT),

From eeb15e83cbef6a1b402e91cd1305dd352fb0cc06 Mon Sep 17 00:00:00 2001
From: Walter Sonius <walterav1984@gmail.com>
Date: Sat, 12 Jul 2025 16:11:23 +0200
Subject: [PATCH 1690/3886] mb/gigabyte: Add ga-h81m-d2w (ITE8620E superio)

This board came virtually rebranded from a specific German OEM called
Wortmann AG and was identified as "TERRA_PC/H81M-D2W" model: 1009381.
It however ships a GIGABYTE GA-H81M-D2W rev 1.0 branded motherboard
which is extremely similar to a Retail GIGABYTE GA-H81M-D2V rev 1.0.
The only obvious differences are the onboard video outputs, its serial
connectivity and total abscence of it on the GIGABYTE support website.

- GA-H81M-D2W
    DVI-D + DVI-I + serial port header on motherboard
- GA-H81M-D2V
    DVI-D + VGA + DB9 serial port connector on backplate

Mainboard: GIGABYTE GA-H81M-D2W rev 1.0

Pure autoport (initial commit) doesn't boot, second patch brings up
general Haswell fixes, vendor/product naming corrected, RAM SPD MAP
slot detection, PCIe fixes enabling onboard LAN and other PCIe slots
and some IT8625E superio code from a other coreboot port made most
ITE8620E superio related functions work, especially WDT otherwise this
board resets every couple of seconds! Autoport did log hda codec / pins
but it didn't include them in the hda_verb.c, so I added them manually
which also fixes pcspkr (beep codes, not soundcard connected).

Flash instructions:
Internal flashing using flashrom works on OEM and when running coreboot
using the following command: flashrom -p internal -c "MX25L6473F" -w ROM
An external flasher ch341a_spi (3.3v mod) used with a SOIC 8 pomona
probe to recover the MX25L6473F in situ also works without issues. Only
the power of the USB programmer was used, and the board's main PSU was
disconnected during external flash!

Tested:
 - coreboot 25.06-77-g812d0e2f626d as base
 - EDK2 (MrChromebox/2502)
 - SeaBIOS 1.16.3
 - Broadwell mrc.bin (tidus)
 - Haswell mrc.bin (peppy used for all mrc.bin noted testing)
 - Haswell NRI
 - libgfxinit textmode (SeaBIOS) / framebuffer (EDK2)
 - DVI-D & DVI-I (VGA) all work during POST, BOOT and OS
 - Pentium G3220 / Xeon E3-1225 v3 / Xeon E3-1231 v3
 - RAM single and dual slot 2GB/4GB/8GB mixed DDR3 DIMMS max 6, 8, 16GB
	(NRI & mrc.bin)
	0/2: 2GB DDR3-1333 - Kingston 99U5458-001.A00LF (2010-W29)
	0&2: 4GB DDR3-1600 - Kingston 9905402-174.A00G (2015-W33)
	0/2: 2GB DDR3-1600 - Micron 8JTF25664AZ-1G6M1 (2013-W37)
	0/2: 4GB DDR3-1600 - Samsung M378B5173BH0-CK0 (2013-W30)
	(NRI single DIMM won't mix with others)
	0/2: 8GB DDR3-1600 - SK Hynix HMT41GU6MFR8C-PB (2023-W20)
	(ECC UDIMM, mrc.bin only, see NRI note below)
	0&2: 4GB DDR3-1600 ECC - Kingston 9965432-051.A00LF (2013-W19)
	0&2: 8GB DDR3-1866 ECC - Micron 18JSF1G72AZ-1G9E1 (2013-W29)
 - Fedora MATE 42 (Kernel 6.14)
 - KDE NEON 6.4 (Kernel 6.11)
 - MS Windows 10 / 11
 - Audio Outputs both DVI > HDMI, Headphone, Line Out (left&right chan.)
 - Audio Input Line In (back)
 - pcspkr
 - USB2/3 all Intel ports
 - SATA 4 ports
 - PCIe slots (16x 5GT/s & both 1x 5GT/s)
 - iGPU (plus dGPU as in dual GPU work both with mrc.bin / Haswell NRI)
 - dGPU (nVidia GeForce GT640-2GD3 2.5GT/s / Radeon HD7770-1GB 5GT/s)
 - Realtek RTL8111F onboard Gb LAN
 - Wake on LAN
 - HWM shows both fan speeds and voltages
 - PS/2 port (both Keyboard and Mouse with Y splitter cable)
 - Serial port header (coreboot console & OS)
 - PowerButton (Poweron/Poweroff/Wake)
 - ResetButton
 - LEDs HDD & POWER (off during suspend)
 - Shutdown/Reboot/Suspend
 - Strip down the Intel ME/TXE firmware (make menuconfig) see ME note!
 - Disabling ME HECI (manually remove from devicetree.cb) see ME note!
 - flashrom -p internal -c "MX25L6473F" #read & write

Not tested:
 - Audio Inputs Front & Back Microphone Ports
 - parallel port header
 - USBDEBUG
 - VBIOS

Not working:
 - Disable Intel ME PCI interface (make menuconfig)
 - USB2/3 all VIA VL805 backpanel ports

FD layout note:
The original OEM firmware ships a BIOS region that seem to use the
whole firmware:

00000000:00000fff fd
00000000:007fffff bios
00001000:001fffff me

Although coreboot works fine with this flash descriptor layout it is
mandatory to flash a complete image! Replacing only a specific region
like the BIOS region when relying on --ifd will confuse flashrom and
trash the flash chip's contents! As a temporary measure one can use
--layout to flash a specific region using the following layout:

00000000:00000fff fd
00001000:001fffff me
00200000:007fffff bios

Permanently changing the flash descriptor layout to look like this will
solve flashing specific regions and remains a valid option since it
cannot break GIGABYTE its DualBIOS feature since its absent.

NRI note:
EDK2 shows 0GB instead of the actual RAM amount installed. While using
Haswell mrc.bin EDK2 shows the correct amount of RAM. The earlier noted
RAM modules have also been tested using NRI in Memtest86+ v7.20 which
still correctly displays and test the total amount of RAM.
ECC UDIMMs currently do not work on this board because NRI does
not check whether the board / chipset support ECC. This results
in RCVET failures for the ECC bytelane (byte 8). Eventually this
will be fixed in NRI. Haswell mrc.bin works as expected.

ME note:
Neutering the ME will let the system still function correctly, unless
you include EFFS and FCRS partitions addressed by ME_CLEANER_ARGS:

"-S --whitelist EFFS,FCRS"

Failing to supply these ME partitions will cripple superio functions as
in serial output (breaks coreboot serial console) and HWM fan and
voltage info goes random nuts while the fan stays at normal speed.

VIA VL805 note:
Without firmware loading (which is still unknown) and enabling it in the
devicetree.cb will give DMAR IOMMU errors therefore disabled by default!

The data.vbt blob was extracted using debugfs from the OEM F5 firmware
which enables both video outputs DVI-D and DVI-I (VGA).

Since this board is not listed on the GIGABYTE website, but it works
with the Retail GA-H81M-D2V F6 firmware I listed that one instead in the
board_info.txt. However I cannot confirm that this coreboot port also
works for the GA-H81M-D2V, it is good practice to at least check its
gpio values matching this port!

Change-Id: I80dc414a92d115099ec8966841af0cf22d5b1d09
Signed-off-by: Walter Sonius <walterav1984@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88412
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/gigabyte/ga-h81m-d2w/Kconfig    |  32 +++
 .../gigabyte/ga-h81m-d2w/Kconfig.name         |   4 +
 .../gigabyte/ga-h81m-d2w/Makefile.mk          |   6 +
 .../gigabyte/ga-h81m-d2w/acpi/ec.asl          |   3 +
 .../gigabyte/ga-h81m-d2w/acpi/platform.asl    |  10 +
 .../gigabyte/ga-h81m-d2w/acpi/superio.asl     |   3 +
 .../gigabyte/ga-h81m-d2w/board_info.txt       |   8 +
 .../gigabyte/ga-h81m-d2w/bootblock.c          |  16 ++
 src/mainboard/gigabyte/ga-h81m-d2w/data.vbt   | Bin 0 -> 6144 bytes
 .../gigabyte/ga-h81m-d2w/devicetree.cb        |  97 +++++++++
 src/mainboard/gigabyte/ga-h81m-d2w/dsdt.asl   |  27 +++
 .../gigabyte/ga-h81m-d2w/gma-mainboard.ads    |  17 ++
 src/mainboard/gigabyte/ga-h81m-d2w/gpio.c     | 201 ++++++++++++++++++
 src/mainboard/gigabyte/ga-h81m-d2w/hda_verb.c |  28 +++
 src/mainboard/gigabyte/ga-h81m-d2w/romstage.c |  35 +++
 15 files changed, 487 insertions(+)
 create mode 100644 src/mainboard/gigabyte/ga-h81m-d2w/Kconfig
 create mode 100644 src/mainboard/gigabyte/ga-h81m-d2w/Kconfig.name
 create mode 100644 src/mainboard/gigabyte/ga-h81m-d2w/Makefile.mk
 create mode 100644 src/mainboard/gigabyte/ga-h81m-d2w/acpi/ec.asl
 create mode 100644 src/mainboard/gigabyte/ga-h81m-d2w/acpi/platform.asl
 create mode 100644 src/mainboard/gigabyte/ga-h81m-d2w/acpi/superio.asl
 create mode 100644 src/mainboard/gigabyte/ga-h81m-d2w/board_info.txt
 create mode 100644 src/mainboard/gigabyte/ga-h81m-d2w/bootblock.c
 create mode 100644 src/mainboard/gigabyte/ga-h81m-d2w/data.vbt
 create mode 100644 src/mainboard/gigabyte/ga-h81m-d2w/devicetree.cb
 create mode 100644 src/mainboard/gigabyte/ga-h81m-d2w/dsdt.asl
 create mode 100644 src/mainboard/gigabyte/ga-h81m-d2w/gma-mainboard.ads
 create mode 100644 src/mainboard/gigabyte/ga-h81m-d2w/gpio.c
 create mode 100644 src/mainboard/gigabyte/ga-h81m-d2w/hda_verb.c
 create mode 100644 src/mainboard/gigabyte/ga-h81m-d2w/romstage.c

diff --git a/src/mainboard/gigabyte/ga-h81m-d2w/Kconfig b/src/mainboard/gigabyte/ga-h81m-d2w/Kconfig
new file mode 100644
index 0000000000..9b0d7e72d8
--- /dev/null
+++ b/src/mainboard/gigabyte/ga-h81m-d2w/Kconfig
@@ -0,0 +1,32 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
+if BOARD_GIGABYTE_GA_H81M_D2W
+
+config BOARD_SPECIFIC_OPTIONS
+	def_bool y
+	select BOARD_ROMSIZE_KB_8192
+	select CPU_INTEL_HASWELL
+	select GFX_GMA_ANALOG_I2C_HDMI_B
+	select HAVE_ACPI_RESUME
+	select HAVE_ACPI_TABLES
+	select INTEL_GMA_HAVE_VBT
+	select MAINBOARD_HAS_LIBGFXINIT
+	select NORTHBRIDGE_INTEL_HASWELL
+	select SERIRQ_CONTINUOUS_MODE
+	select SOUTHBRIDGE_INTEL_LYNXPOINT
+	select SUPERIO_ITE_IT8625E
+
+config MAINBOARD_DIR
+	default "gigabyte/ga-h81m-d2w"
+
+config MAINBOARD_PART_NUMBER
+	default "GA_H81M_D2W"
+
+config ME_CLEANER_ARGS
+	depends on USE_ME_CLEANER
+	default "-S --whitelist EFFS,FCRS"
+
+config USBDEBUG_HCD_INDEX
+	default 2
+
+endif
diff --git a/src/mainboard/gigabyte/ga-h81m-d2w/Kconfig.name b/src/mainboard/gigabyte/ga-h81m-d2w/Kconfig.name
new file mode 100644
index 0000000000..3e164e67c8
--- /dev/null
+++ b/src/mainboard/gigabyte/ga-h81m-d2w/Kconfig.name
@@ -0,0 +1,4 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
+config BOARD_GIGABYTE_GA_H81M_D2W
+	bool "GA_H81M_D2W"
diff --git a/src/mainboard/gigabyte/ga-h81m-d2w/Makefile.mk b/src/mainboard/gigabyte/ga-h81m-d2w/Makefile.mk
new file mode 100644
index 0000000000..c3cf55d397
--- /dev/null
+++ b/src/mainboard/gigabyte/ga-h81m-d2w/Makefile.mk
@@ -0,0 +1,6 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
+bootblock-y += bootblock.c
+bootblock-y += gpio.c
+romstage-y += gpio.c
+ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads
diff --git a/src/mainboard/gigabyte/ga-h81m-d2w/acpi/ec.asl b/src/mainboard/gigabyte/ga-h81m-d2w/acpi/ec.asl
new file mode 100644
index 0000000000..16990d45f4
--- /dev/null
+++ b/src/mainboard/gigabyte/ga-h81m-d2w/acpi/ec.asl
@@ -0,0 +1,3 @@
+/* SPDX-License-Identifier: CC-PDDC */
+
+/* Please update the license if adding licensable material. */
diff --git a/src/mainboard/gigabyte/ga-h81m-d2w/acpi/platform.asl b/src/mainboard/gigabyte/ga-h81m-d2w/acpi/platform.asl
new file mode 100644
index 0000000000..aff432b6f4
--- /dev/null
+++ b/src/mainboard/gigabyte/ga-h81m-d2w/acpi/platform.asl
@@ -0,0 +1,10 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+Method(_WAK, 1)
+{
+	Return(Package() {0, 0})
+}
+
+Method(_PTS, 1)
+{
+}
diff --git a/src/mainboard/gigabyte/ga-h81m-d2w/acpi/superio.asl b/src/mainboard/gigabyte/ga-h81m-d2w/acpi/superio.asl
new file mode 100644
index 0000000000..55b1db5b11
--- /dev/null
+++ b/src/mainboard/gigabyte/ga-h81m-d2w/acpi/superio.asl
@@ -0,0 +1,3 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <drivers/pc80/pc/ps2_controller.asl>
diff --git a/src/mainboard/gigabyte/ga-h81m-d2w/board_info.txt b/src/mainboard/gigabyte/ga-h81m-d2w/board_info.txt
new file mode 100644
index 0000000000..1b0fb4c6de
--- /dev/null
+++ b/src/mainboard/gigabyte/ga-h81m-d2w/board_info.txt
@@ -0,0 +1,8 @@
+Category: desktop
+Board URL: https://www.gigabyte.com/Motherboard/GA-H81M-D2V-rev-10
+ROM IC: MX25L6473F
+ROM protocol: SPI
+Flashrom support: y
+ROM package: SOIC8
+ROM socketed: no
+Release year: 2014
diff --git a/src/mainboard/gigabyte/ga-h81m-d2w/bootblock.c b/src/mainboard/gigabyte/ga-h81m-d2w/bootblock.c
new file mode 100644
index 0000000000..057f155b86
--- /dev/null
+++ b/src/mainboard/gigabyte/ga-h81m-d2w/bootblock.c
@@ -0,0 +1,16 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <southbridge/intel/lynxpoint/pch.h>
+
+#include <device/pnp_ops.h>
+#include <superio/ite/common/ite.h>
+#include <superio/ite/it8625e/it8625e.h>
+
+#define UART_DEV PNP_DEV(0x2e, 0x1)
+#define SIO_GPIO PNP_DEV(0x2e, IT8625E_GPIO)
+
+void mainboard_config_superio(void)
+{
+	ite_enable_serial(UART_DEV, CONFIG_TTYS0_BASE);
+	ite_reg_write(SIO_GPIO, 0xEF, 0x7E); // magic SIO disable reboot
+}
diff --git a/src/mainboard/gigabyte/ga-h81m-d2w/data.vbt b/src/mainboard/gigabyte/ga-h81m-d2w/data.vbt
new file mode 100644
index 0000000000000000000000000000000000000000..39df2c4f66d1757bd34147bcf5e4d70a41f343b0
GIT binary patch
literal 6144
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diff --git a/src/mainboard/gigabyte/ga-h81m-d2w/devicetree.cb b/src/mainboard/gigabyte/ga-h81m-d2w/devicetree.cb
new file mode 100644
index 0000000000..c86e8bae00
--- /dev/null
+++ b/src/mainboard/gigabyte/ga-h81m-d2w/devicetree.cb
@@ -0,0 +1,97 @@
+chip northbridge/intel/haswell
+	register "gpu_ddi_e_connected" = "1"
+	register "gpu_dp_b_hotplug" = "4"
+	register "gpu_dp_c_hotplug" = "4"
+	register "spd_addresses" = "{0x50, 0, 0x52, 0}"
+	chip cpu/intel/haswell
+		device cpu_cluster 0 on ops haswell_cpu_bus_ops end
+	end
+	device domain 0 on
+		ops haswell_pci_domain_ops
+		device pci 00.0 on # Host bridge
+			subsystemid 0x1458 0x5000
+		end
+		device pci 01.0 on # PCIEX16
+			subsystemid 0x1458 0x5000
+		end
+		device pci 02.0 on # Internal graphics VGA controller
+			subsystemid 0x1458 0xd000
+		end
+		device pci 03.0 on end # Mini-HD audio
+		chip southbridge/intel/lynxpoint # Intel Series 8 Lynx Point PCH
+			register "gen1_dec" = "0x003c0a01"
+			register "gpe0_en_1" = "0x20000246"
+			register "sata_port0_gen3_dtle" = "0x2"
+			register "sata_port1_gen3_dtle" = "0x2"
+			register "sata_port_map" = "0x33"
+			device pci 14.0 on # xHCI Controller
+				subsystemid 0x1458 0x5007
+			end
+			device pci 16.0 on # Management Engine Interface 1
+				subsystemid 0x1458 0x1c3a
+			end
+			device pci 16.1 off end # Management Engine Interface 2
+			device pci 16.2 off end # Management Engine IDE-R
+			device pci 16.3 off end # Management Engine KT
+			device pci 19.0 off end # Intel Gigabit Ethernet
+			device pci 1a.0 on # USB2 EHCI #2
+				subsystemid 0x1458 0x5006
+			end
+			device pci 1b.0 on # High Definition Audio
+				subsystemid 0x1458 0xa002
+			end
+			device pci 1c.0 on # PCIe Port #1
+				subsystemid 0x1458 0x5001
+			end
+			device pci 1c.1 off end # PCIe Port #2
+			device pci 1c.2 on # PCIe Port #3: Realtek RTL8111F GbE NIC
+				subsystemid 0x1458 0x5001
+				device pci 00.0 on end
+			end
+			device pci 1c.3 off # PCIe Port #4: VIA VL805 USB
+				subsystemid 0x1458 0x5001
+			end
+			device pci 1c.4 on # PCIEX1_1
+				subsystemid 0x1458 0x5001
+			end
+			device pci 1c.5 on # PCIEX1_2
+				subsystemid 0x1458 0x5001
+			end
+			device pci 1d.0 on # USB2 EHCI #1
+				subsystemid 0x1458 0x5006
+			end
+			device pci 1f.0 on # LPC bridge
+				subsystemid 0x1458 0x5001
+				chip superio/ite/it8625e
+					device pnp 2e.1 on	# COM
+					io  0x60 = 0x03f8
+					irq 0x70 = 0x04
+					irq 0xf1 = 0x50
+					end
+					device pnp 2e.4 on	# EC
+						io 0x60 = 0x0a30
+						irq 0x70 = 9
+						io 0x62 = 0x0230
+					end
+					device pnp 2e.5 on	# Keyboard
+						io 0x60 = 0x0060
+						irq 0x70 = 1
+						io 0x62 = 0x0064
+					end
+					device pnp 2e.6 on	# Mouse
+						irq 0x70 = 12
+					end
+					device pnp 2e.7 off end	# GPIO
+				end
+			end
+			device pci 1f.2 on # SATA Controller (AHCI)
+				subsystemid 0x1458 0xb005
+			end
+			device pci 1f.3 on # SMBus
+				subsystemid 0x1458 0x5001
+			end
+			device pci 1f.5 off end # SATA Controller (Legacy)
+			device pci 1f.6 off end # Thermal
+		end
+	end
+end
diff --git a/src/mainboard/gigabyte/ga-h81m-d2w/dsdt.asl b/src/mainboard/gigabyte/ga-h81m-d2w/dsdt.asl
new file mode 100644
index 0000000000..2eb0805cf2
--- /dev/null
+++ b/src/mainboard/gigabyte/ga-h81m-d2w/dsdt.asl
@@ -0,0 +1,27 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <acpi/acpi.h>
+
+DefinitionBlock(
+	"dsdt.aml",
+	"DSDT",
+	ACPI_DSDT_REV_2,
+	OEM_ID,
+	ACPI_TABLE_CREATOR,
+	0x20141018
+)
+{
+	#include <acpi/dsdt_top.asl>
+	#include "acpi/platform.asl"
+	#include <cpu/intel/common/acpi/cpu.asl>
+	#include <southbridge/intel/common/acpi/platform.asl>
+	/* global NVS and variables. */
+	#include <southbridge/intel/lynxpoint/acpi/globalnvs.asl>
+	#include <southbridge/intel/common/acpi/sleepstates.asl>
+
+	Device (\_SB.PCI0)
+	{
+		#include <northbridge/intel/haswell/acpi/hostbridge.asl>
+		#include <southbridge/intel/lynxpoint/acpi/pch.asl>
+	}
+}
diff --git a/src/mainboard/gigabyte/ga-h81m-d2w/gma-mainboard.ads b/src/mainboard/gigabyte/ga-h81m-d2w/gma-mainboard.ads
new file mode 100644
index 0000000000..8b07c07695
--- /dev/null
+++ b/src/mainboard/gigabyte/ga-h81m-d2w/gma-mainboard.ads
@@ -0,0 +1,17 @@
+-- SPDX-License-Identifier: GPL-2.0-or-later
+
+with HW.GFX.GMA;
+with HW.GFX.GMA.Display_Probing;
+
+use HW.GFX.GMA;
+use HW.GFX.GMA.Display_Probing;
+
+private package GMA.Mainboard is
+
+   ports : constant Port_List :=
+     (HDMI1,
+      HDMI2,
+      Analog,
+      others => Disabled);
+
+end GMA.Mainboard;
diff --git a/src/mainboard/gigabyte/ga-h81m-d2w/gpio.c b/src/mainboard/gigabyte/ga-h81m-d2w/gpio.c
new file mode 100644
index 0000000000..f21e62b5bd
--- /dev/null
+++ b/src/mainboard/gigabyte/ga-h81m-d2w/gpio.c
@@ -0,0 +1,201 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <southbridge/intel/common/gpio.h>
+
+static const struct pch_gpio_set1 pch_gpio_set1_mode = {
+	.gpio0 = GPIO_MODE_GPIO,
+	.gpio1 = GPIO_MODE_GPIO,
+	.gpio2 = GPIO_MODE_GPIO,
+	.gpio3 = GPIO_MODE_GPIO,
+	.gpio4 = GPIO_MODE_GPIO,
+	.gpio5 = GPIO_MODE_GPIO,
+	.gpio6 = GPIO_MODE_GPIO,
+	.gpio7 = GPIO_MODE_GPIO,
+	.gpio8 = GPIO_MODE_GPIO,
+	.gpio9 = GPIO_MODE_NATIVE,
+	.gpio10 = GPIO_MODE_NATIVE,
+	.gpio11 = GPIO_MODE_GPIO,
+	.gpio12 = GPIO_MODE_GPIO,
+	.gpio13 = GPIO_MODE_GPIO,
+	.gpio14 = GPIO_MODE_NATIVE,
+	.gpio15 = GPIO_MODE_GPIO,
+	.gpio16 = GPIO_MODE_GPIO,
+	.gpio17 = GPIO_MODE_GPIO,
+	.gpio18 = GPIO_MODE_NATIVE,
+	.gpio19 = GPIO_MODE_GPIO,
+	.gpio20 = GPIO_MODE_NATIVE,
+	.gpio21 = GPIO_MODE_GPIO,
+	.gpio22 = GPIO_MODE_GPIO,
+	.gpio23 = GPIO_MODE_NATIVE,
+	.gpio24 = GPIO_MODE_GPIO,
+	.gpio25 = GPIO_MODE_NATIVE,
+	.gpio26 = GPIO_MODE_NATIVE,
+	.gpio27 = GPIO_MODE_GPIO,
+	.gpio28 = GPIO_MODE_GPIO,
+	.gpio29 = GPIO_MODE_NATIVE,
+	.gpio30 = GPIO_MODE_NATIVE,
+	.gpio31 = GPIO_MODE_GPIO,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_direction = {
+	.gpio0 = GPIO_DIR_INPUT,
+	.gpio1 = GPIO_DIR_INPUT,
+	.gpio2 = GPIO_DIR_INPUT,
+	.gpio3 = GPIO_DIR_INPUT,
+	.gpio4 = GPIO_DIR_INPUT,
+	.gpio5 = GPIO_DIR_INPUT,
+	.gpio6 = GPIO_DIR_INPUT,
+	.gpio7 = GPIO_DIR_INPUT,
+	.gpio8 = GPIO_DIR_OUTPUT,
+	.gpio11 = GPIO_DIR_INPUT,
+	.gpio12 = GPIO_DIR_OUTPUT,
+	.gpio13 = GPIO_DIR_OUTPUT,
+	.gpio15 = GPIO_DIR_OUTPUT,
+	.gpio16 = GPIO_DIR_INPUT,
+	.gpio17 = GPIO_DIR_INPUT,
+	.gpio19 = GPIO_DIR_INPUT,
+	.gpio21 = GPIO_DIR_OUTPUT,
+	.gpio22 = GPIO_DIR_INPUT,
+	.gpio24 = GPIO_DIR_OUTPUT,
+	.gpio27 = GPIO_DIR_INPUT,
+	.gpio28 = GPIO_DIR_OUTPUT,
+	.gpio31 = GPIO_DIR_INPUT,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_level = {
+	.gpio8 = GPIO_LEVEL_HIGH,
+	.gpio12 = GPIO_LEVEL_HIGH,
+	.gpio13 = GPIO_LEVEL_HIGH,
+	.gpio15 = GPIO_LEVEL_LOW,
+	.gpio21 = GPIO_LEVEL_LOW,
+	.gpio24 = GPIO_LEVEL_LOW,
+	.gpio28 = GPIO_LEVEL_LOW,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_reset = {
+	.gpio24 = GPIO_RESET_RSMRST,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_invert = {
+	.gpio11 = GPIO_INVERT,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_blink = {
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_mode = {
+	.gpio32 = GPIO_MODE_GPIO,
+	.gpio33 = GPIO_MODE_GPIO,
+	.gpio34 = GPIO_MODE_GPIO,
+	.gpio35 = GPIO_MODE_GPIO,
+	.gpio36 = GPIO_MODE_GPIO,
+	.gpio37 = GPIO_MODE_GPIO,
+	.gpio38 = GPIO_MODE_GPIO,
+	.gpio39 = GPIO_MODE_GPIO,
+	.gpio40 = GPIO_MODE_NATIVE,
+	.gpio41 = GPIO_MODE_NATIVE,
+	.gpio42 = GPIO_MODE_NATIVE,
+	.gpio43 = GPIO_MODE_NATIVE,
+	.gpio44 = GPIO_MODE_NATIVE,
+	.gpio45 = GPIO_MODE_NATIVE,
+	.gpio46 = GPIO_MODE_NATIVE,
+	.gpio47 = GPIO_MODE_NATIVE,
+	.gpio48 = GPIO_MODE_GPIO,
+	.gpio49 = GPIO_MODE_GPIO,
+	.gpio50 = GPIO_MODE_GPIO,
+	.gpio51 = GPIO_MODE_GPIO,
+	.gpio52 = GPIO_MODE_GPIO,
+	.gpio53 = GPIO_MODE_GPIO,
+	.gpio54 = GPIO_MODE_GPIO,
+	.gpio55 = GPIO_MODE_GPIO,
+	.gpio56 = GPIO_MODE_NATIVE,
+	.gpio57 = GPIO_MODE_GPIO,
+	.gpio58 = GPIO_MODE_NATIVE,
+	.gpio59 = GPIO_MODE_NATIVE,
+	.gpio60 = GPIO_MODE_NATIVE,
+	.gpio61 = GPIO_MODE_NATIVE,
+	.gpio62 = GPIO_MODE_NATIVE,
+	.gpio63 = GPIO_MODE_NATIVE,
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_direction = {
+	.gpio32 = GPIO_DIR_OUTPUT,
+	.gpio33 = GPIO_DIR_OUTPUT,
+	.gpio34 = GPIO_DIR_INPUT,
+	.gpio35 = GPIO_DIR_OUTPUT,
+	.gpio36 = GPIO_DIR_INPUT,
+	.gpio37 = GPIO_DIR_INPUT,
+	.gpio38 = GPIO_DIR_INPUT,
+	.gpio39 = GPIO_DIR_INPUT,
+	.gpio48 = GPIO_DIR_INPUT,
+	.gpio49 = GPIO_DIR_INPUT,
+	.gpio50 = GPIO_DIR_INPUT,
+	.gpio51 = GPIO_DIR_OUTPUT,
+	.gpio52 = GPIO_DIR_INPUT,
+	.gpio53 = GPIO_DIR_OUTPUT,
+	.gpio54 = GPIO_DIR_INPUT,
+	.gpio55 = GPIO_DIR_OUTPUT,
+	.gpio57 = GPIO_DIR_INPUT,
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_level = {
+	.gpio32 = GPIO_LEVEL_HIGH,
+	.gpio33 = GPIO_LEVEL_HIGH,
+	.gpio35 = GPIO_LEVEL_LOW,
+	.gpio51 = GPIO_LEVEL_HIGH,
+	.gpio53 = GPIO_LEVEL_HIGH,
+	.gpio55 = GPIO_LEVEL_HIGH,
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_reset = {
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_mode = {
+	.gpio64 = GPIO_MODE_NATIVE,
+	.gpio65 = GPIO_MODE_NATIVE,
+	.gpio66 = GPIO_MODE_NATIVE,
+	.gpio67 = GPIO_MODE_NATIVE,
+	.gpio68 = GPIO_MODE_GPIO,
+	.gpio69 = GPIO_MODE_GPIO,
+	.gpio70 = GPIO_MODE_NATIVE,
+	.gpio71 = GPIO_MODE_NATIVE,
+	.gpio72 = GPIO_MODE_GPIO,
+	.gpio73 = GPIO_MODE_NATIVE,
+	.gpio74 = GPIO_MODE_NATIVE,
+	.gpio75 = GPIO_MODE_NATIVE,
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_direction = {
+	.gpio68 = GPIO_DIR_INPUT,
+	.gpio69 = GPIO_DIR_INPUT,
+	.gpio72 = GPIO_DIR_INPUT,
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_level = {
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_reset = {
+};
+
+const struct pch_gpio_map mainboard_gpio_map = {
+	.set1 = {
+		.mode		= &pch_gpio_set1_mode,
+		.direction	= &pch_gpio_set1_direction,
+		.level		= &pch_gpio_set1_level,
+		.blink		= &pch_gpio_set1_blink,
+		.invert		= &pch_gpio_set1_invert,
+		.reset		= &pch_gpio_set1_reset,
+	},
+	.set2 = {
+		.mode		= &pch_gpio_set2_mode,
+		.direction	= &pch_gpio_set2_direction,
+		.level		= &pch_gpio_set2_level,
+		.reset		= &pch_gpio_set2_reset,
+	},
+	.set3 = {
+		.mode		= &pch_gpio_set3_mode,
+		.direction	= &pch_gpio_set3_direction,
+		.level		= &pch_gpio_set3_level,
+		.reset		= &pch_gpio_set3_reset,
+	},
+};
diff --git a/src/mainboard/gigabyte/ga-h81m-d2w/hda_verb.c b/src/mainboard/gigabyte/ga-h81m-d2w/hda_verb.c
new file mode 100644
index 0000000000..5d6633955c
--- /dev/null
+++ b/src/mainboard/gigabyte/ga-h81m-d2w/hda_verb.c
@@ -0,0 +1,28 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <device/azalia_device.h>
+
+const u32 cim_verb_data[] = {
+	0x10ec0887,	/* Codec Vendor / Device ID: Realtek */
+	0x1458a002,	/* Subsystem ID */
+	15,		/* Number of 4 dword sets */
+	AZALIA_SUBVENDOR(0, 0x1458a002),
+	AZALIA_PIN_CFG(0, 0x11, 0x4037c040),
+	AZALIA_PIN_CFG(0, 0x12, AZALIA_PIN_CFG_NC(0)),
+	AZALIA_PIN_CFG(0, 0x14, 0x01014010),
+	AZALIA_PIN_CFG(0, 0x15, AZALIA_PIN_CFG_NC(0)),
+	AZALIA_PIN_CFG(0, 0x16, AZALIA_PIN_CFG_NC(0)),
+	AZALIA_PIN_CFG(0, 0x17, AZALIA_PIN_CFG_NC(0)),
+	AZALIA_PIN_CFG(0, 0x18, 0x01a19030),
+	AZALIA_PIN_CFG(0, 0x19, 0x02a19040),
+	AZALIA_PIN_CFG(0, 0x1a, 0x0181303f),
+	AZALIA_PIN_CFG(0, 0x1b, 0x02214020),
+	AZALIA_PIN_CFG(0, 0x1c, AZALIA_PIN_CFG_NC(0)),
+	AZALIA_PIN_CFG(0, 0x1d, 0x4024c601),
+	AZALIA_PIN_CFG(0, 0x1e, AZALIA_PIN_CFG_NC(0)),
+	AZALIA_PIN_CFG(0, 0x1f, AZALIA_PIN_CFG_NC(0)),
+};
+
+const u32 pc_beep_verbs[0] = {};
+
+AZALIA_ARRAY_SIZES;
diff --git a/src/mainboard/gigabyte/ga-h81m-d2w/romstage.c b/src/mainboard/gigabyte/ga-h81m-d2w/romstage.c
new file mode 100644
index 0000000000..ff8d17a725
--- /dev/null
+++ b/src/mainboard/gigabyte/ga-h81m-d2w/romstage.c
@@ -0,0 +1,35 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <southbridge/intel/lynxpoint/pch.h>
+
+void mainboard_config_rcba(void)
+{
+}
+
+const struct usb2_port_config mainboard_usb2_ports[MAX_USB2_PORTS] = {
+	/* FIXME: Length and Location are computed from IOBP values, may be inaccurate */
+	/* Length, Enable, OCn#, Location */
+	{ 0x0040, 1, 0, USB_PORT_FLEX },
+	{ 0x0040, 1, 0, USB_PORT_FLEX },
+	{ 0x0110, 1, 1, USB_PORT_BACK_PANEL },
+	{ 0x0110, 1, USB_OC_PIN_SKIP, USB_PORT_BACK_PANEL },
+	{ 0x0040, 1, USB_OC_PIN_SKIP, USB_PORT_FLEX },
+	{ 0x0040, 1, 2, USB_PORT_FLEX },
+	{ 0x0040, 1, 3, USB_PORT_FLEX },
+	{ 0x0040, 1, 3, USB_PORT_FLEX },
+	{ 0x0110, 1, 4, USB_PORT_BACK_PANEL },
+	{ 0x0110, 1, 4, USB_PORT_BACK_PANEL },
+	{ 0x0140, 1, 5, USB_PORT_BACK_PANEL },
+	{ 0x0140, 1, 5, USB_PORT_BACK_PANEL },
+	{ 0x0040, 1, 6, USB_PORT_FLEX },
+	{ 0x0040, 1, 6, USB_PORT_FLEX },
+};
+
+const struct usb3_port_config mainboard_usb3_ports[MAX_USB3_PORTS] = {
+	{ 1, 0 },
+	{ 1, 0 },
+	{ 1, 1 },
+	{ 1, 1 },
+	{ 1, 2 },
+	{ 1, 2 },
+};

From 7095c99a8743805a6bce437547389c0d1e9265c6 Mon Sep 17 00:00:00 2001
From: Jakub Czapiga <czapiga@google.com>
Date: Fri, 25 Apr 2025 13:58:49 +0000
Subject: [PATCH 1691/3886] util/cbmem: Add support for CBMEM in sysfs

This commit adds support for CBMEM in sysfs. Useful for systems without
access to /dev/mem e.g. Android.
Linux kernel driver: drivers/firmware/google/cbmem.c
Linux driver Kconfig: CONFIG_GOOGLE_CBMEM

BUG=b:391874512
TEST=(devmem) cbmem -l; cbmem -x; cbmem -r 434f4e53; cbmem -t;
cbmem -a 1200
TEST=modprobe cbmem; cbmem -l; cbmem -x; cbmem -r 434f4e53; cbmem -t;
cbmem -a 1200

Change-Id: I527889509ffc84203be42d0160e5363c60eafd02
Signed-off-by: Jakub Czapiga <czapiga@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86606
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
---
 util/cbmem/Makefile     |   2 +-
 util/cbmem/cbmem.c      |  58 ++++++---
 util/cbmem/cbmem_drv.c  |  95 ++++++++++++++
 util/cbmem/cbmem_util.h |  98 +++++++++++++++
 util/cbmem/sysfs_drv.c  | 266 ++++++++++++++++++++++++++++++++++++++++
 5 files changed, 500 insertions(+), 19 deletions(-)
 create mode 100644 util/cbmem/cbmem_drv.c
 create mode 100644 util/cbmem/sysfs_drv.c

diff --git a/util/cbmem/Makefile b/util/cbmem/Makefile
index 1376b04d52..e265ea6693 100644
--- a/util/cbmem/Makefile
+++ b/util/cbmem/Makefile
@@ -14,7 +14,7 @@ CFLAGS   += -Wall -Wextra -Wmissing-prototypes -Wshadow $(WERROR)
 CPPFLAGS += -I . -I $(ROOT)/commonlib/include -I $(ROOT)/commonlib/bsd/include
 CPPFLAGS += -include $(ROOT)/commonlib/bsd/include/commonlib/bsd/compiler.h
 
-OBJS = $(PROGRAM).o devmem_drv.o $(COMMONLIB)/bsd/ipchksum.o
+OBJS = $(PROGRAM).o cbmem_drv.o devmem_drv.o sysfs_drv.o $(COMMONLIB)/bsd/ipchksum.o
 
 all: $(PROGRAM)
 
diff --git a/util/cbmem/cbmem.c b/util/cbmem/cbmem.c
index 93a58d5999..018ea871f9 100644
--- a/util/cbmem/cbmem.c
+++ b/util/cbmem/cbmem.c
@@ -5,6 +5,7 @@
 #include <stdio.h>
 #include <stdlib.h>
 #include <string.h>
+#include <strings.h>
 #include <unistd.h>
 #include <getopt.h>
 #include <errno.h>
@@ -29,7 +30,7 @@
 
 #include "cbmem_util.h"
 
-#define CBMEM_VERSION "1.1"
+#define CBMEM_VERSION "1.2"
 
 /* Global verbosity level for debug() macro. */
 int cbmem_util_verbose;
@@ -140,8 +141,7 @@ static void cbmem_get_lb_table_entry(uint32_t tag, uint8_t **buf_out, size_t *si
 	const uint8_t *lbtable_raw;
 	bool tag_found = false;
 
-	if (!cbmem_devmem_get_cbmem_entry(CBMEM_ID_CBTABLE, (uint8_t **)&lbtable_raw, NULL,
-					  NULL))
+	if (!cbmem_drv_get_cbmem_entry(CBMEM_ID_CBTABLE, (uint8_t **)&lbtable_raw, NULL, NULL))
 		die("coreboot table not found.\n");
 
 	const struct lb_header *lbh = (const struct lb_header *)lbtable_raw;
@@ -337,7 +337,7 @@ static void dump_timestamps(enum timestamps_print_type output_type)
 	uint64_t prev_stamp = 0;
 	uint64_t total_time = 0;
 
-	if (!cbmem_devmem_get_cbmem_entry(CBMEM_ID_TIMESTAMP, (uint8_t **)&tst_p, &size, NULL))
+	if (!cbmem_drv_get_cbmem_entry(CBMEM_ID_TIMESTAMP, (uint8_t **)&tst_p, &size, NULL))
 		die("Timestamps not found.\n");
 
 	timestamp_set_tick_freq(tst_p->tick_freq_mhz);
@@ -437,7 +437,7 @@ static void timestamp_add_now(uint32_t timestamp_id)
 	struct timestamp_table *tst_p;
 	size_t tst_size;
 
-	if (!cbmem_devmem_get_cbmem_entry(CBMEM_ID_TIMESTAMP, (uint8_t **)&tst_p, &tst_size, NULL))
+	if (!cbmem_drv_get_cbmem_entry(CBMEM_ID_TIMESTAMP, (uint8_t **)&tst_p, &tst_size, NULL))
 		die("Unable to find timestamps.\n");
 
 	/*
@@ -454,7 +454,7 @@ static void timestamp_add_now(uint32_t timestamp_id)
 		tst_p->num_entries += 1;
 	}
 
-	if (!cbmem_devmem_write_cbmem_entry(CBMEM_ID_TIMESTAMP, (uint8_t *)tst_p, tst_size))
+	if (!cbmem_drv_write_cbmem_entry(CBMEM_ID_TIMESTAMP, (uint8_t *)tst_p, tst_size))
 		die("Unable to write timestamps.\n");
 	free((uint8_t *)tst_p);
 }
@@ -674,7 +674,7 @@ static void dump_tpm_cb_log(void)
 {
 	const struct tpm_cb_log_table *tclt_p;
 
-	if (!cbmem_devmem_get_cbmem_entry(CBMEM_ID_TPM_CB_LOG, (uint8_t **)&tclt_p, NULL, NULL))
+	if (!cbmem_drv_get_cbmem_entry(CBMEM_ID_TPM_CB_LOG, (uint8_t **)&tclt_p, NULL, NULL))
 		die("coreboot TPM log not found.\n");
 
 	printf("coreboot TPM log:\n\n");
@@ -694,8 +694,8 @@ static void dump_tpm_log(void)
 {
 	uint8_t *buf;
 
-	if (cbmem_devmem_get_cbmem_entry(CBMEM_ID_TCPA_TCG_LOG, &buf, NULL, NULL) ||
-	    cbmem_devmem_get_cbmem_entry(CBMEM_ID_TPM2_TCG_LOG, &buf, NULL, NULL)) {
+	if (cbmem_drv_get_cbmem_entry(CBMEM_ID_TCPA_TCG_LOG, &buf, NULL, NULL) ||
+	    cbmem_drv_get_cbmem_entry(CBMEM_ID_TPM2_TCG_LOG, &buf, NULL, NULL)) {
 		dump_tpm_std_log(buf);
 		free(buf);
 	} else
@@ -738,7 +738,7 @@ static void dump_console(enum console_print_type type, int max_loglevel, int pri
 	char *console_c;
 	size_t size, cursor, previous;
 
-	if (!cbmem_devmem_get_cbmem_entry(CBMEM_ID_CONSOLE, (uint8_t **)&console_p, NULL, NULL))
+	if (!cbmem_drv_get_cbmem_entry(CBMEM_ID_CONSOLE, (uint8_t **)&console_p, NULL, NULL))
 		die("CBMEM console not found.\n");
 
 	cursor = console_p->cursor & CBMC_CURSOR_MASK;
@@ -882,7 +882,7 @@ static bool hexdump_handler(const uint32_t id, const uint64_t physical_address,
 
 static void dump_cbmem_hex(void)
 {
-	cbmem_devmem_foreach_cbmem_entry(hexdump_handler, NULL, true);
+	cbmem_drv_foreach_cbmem_entry(hexdump_handler, NULL, true);
 }
 
 static void dump_cbmem_raw(unsigned int id)
@@ -890,7 +890,7 @@ static void dump_cbmem_raw(unsigned int id)
 	uint8_t *buf;
 	size_t size;
 
-	if (!cbmem_devmem_get_cbmem_entry(id, &buf, &size, NULL))
+	if (!cbmem_drv_get_cbmem_entry(id, &buf, &size, NULL))
 		die("cbmem entry id: %#x not found.\n", id);
 
 	fwrite(buf, 1, size, stdout);
@@ -958,7 +958,7 @@ static void dump_cbmem_toc(void)
 	printf("CBMEM table of contents:\n");
 	printf("    %-20s  %-8s  %-8s  %-8s\n", "NAME", "ID", "START", "LENGTH");
 
-	cbmem_devmem_foreach_cbmem_entry(toc_handler, &i, false);
+	cbmem_drv_foreach_cbmem_entry(toc_handler, &i, false);
 }
 
 #define COVERAGE_MAGIC 0x584d4153
@@ -995,7 +995,7 @@ static void dump_coverage(void)
 	unsigned long phys_offset;
 #define phys_to_virt(x) ((void *)(unsigned long)(x) + phys_offset)
 
-	if (!cbmem_devmem_get_cbmem_entry(CBMEM_ID_COVERAGE, &coverage, NULL, &start))
+	if (!cbmem_drv_get_cbmem_entry(CBMEM_ID_COVERAGE, &coverage, NULL, &start))
 		die("No coverage information found\n");
 
 	/* Map coverage area */
@@ -1059,6 +1059,7 @@ static void print_usage(const char *name, int exit_code)
 	     "   -c | --console:                   print cbmem console\n"
 	     "   -1 | --oneboot:                   print cbmem console for last boot only\n"
 	     "   -2 | --2ndtolast:                 print cbmem console for the boot that came before the last one only\n"
+	     "   -b | --backend [devmem|sysfs]:    select specific CBMEM backend\n"
 	     "   -B | --loglevel:                  maximum loglevel to print; prefix `+` (e.g. -B +INFO) to also print lines that have no level\n"
 	     "   -C | --coverage:                  dump coverage information\n"
 	     "   -l | --list:                      print cbmem table of contents\n"
@@ -1091,10 +1092,12 @@ int main(int argc, char** argv)
 	int max_loglevel = BIOS_NEVER;
 	int print_unknown_logs = 1;
 	uint32_t timestamp_id = 0;
+	enum cbmem_drv_backend_type backend_type = CBMEM_DRV_BACKEND_ANY;
 
 	int opt, option_index = 0;
 	static struct option long_options[] = {
 		{"console", 0, 0, 'c'},
+		{"backend", required_argument, 0, 'b'},
 		{"oneboot", 0, 0, '1'},
 		{"2ndtolast", 0, 0, '2'},
 		{"loglevel", required_argument, 0, 'B'},
@@ -1112,13 +1115,24 @@ int main(int argc, char** argv)
 		{"help", 0, 0, 'h'},
 		{0, 0, 0, 0}
 	};
-	while ((opt = getopt_long(argc, argv, "c12B:CltTSa:LxVvh?r:",
+	while ((opt = getopt_long(argc, argv, "cb:12B:CltTSa:LxVvh?r:",
 				  long_options, &option_index)) != EOF) {
 		switch (opt) {
 		case 'c':
 			print_console = 1;
 			print_defaults = 0;
 			break;
+		case 'b':
+			if (!strcasecmp(optarg, "devmem"))
+				backend_type = CBMEM_DRV_BACKEND_DEVMEM;
+			else if (!strcasecmp(optarg, "sysfs"))
+				backend_type = CBMEM_DRV_BACKEND_SYSFS;
+			else if (!strcasecmp(optarg, "any"))
+				backend_type = CBMEM_DRV_BACKEND_ANY;
+			else
+				die("Unrecognized backend type: '%s'\n", optarg);
+			break;
+
 		case '1':
 			print_console = 1;
 			console_type = CONSOLE_PRINT_LAST;
@@ -1194,8 +1208,16 @@ int main(int argc, char** argv)
 		print_usage(argv[0], 1);
 	}
 
-	if (!cbmem_devmem_init(timestamp_id != 0))
-		die("Unable to initialize /dev/mem access to coreboot tables and CBMEM.\n");
+	if (print_hexdump) {
+		debug("Hexdump requested. CBMEM backend force-set to DEVMEM.\n");
+		backend_type = CBMEM_DRV_BACKEND_DEVMEM;
+	}
+
+	if (!cbmem_drv_init(backend_type, timestamp_id != 0)) {
+		if (print_hexdump)
+			fprintf(stderr, "Hexdump is only available on systems with /dev/mem.\n");
+		die("Unable to initialize CBMEM access. Check if you have either /dev/mem access or sysfs CBMEM entries.\n");
+	}
 
 	if (print_console)
 		dump_console(console_type, max_loglevel, print_unknown_logs);
@@ -1224,7 +1246,7 @@ int main(int argc, char** argv)
 	if (print_tcpa_log)
 		dump_tpm_log();
 
-	cbmem_devmem_terminate();
+	cbmem_drv_terminate();
 
 	return 0;
 }
diff --git a/util/cbmem/cbmem_drv.c b/util/cbmem/cbmem_drv.c
new file mode 100644
index 0000000000..bc9234b5a1
--- /dev/null
+++ b/util/cbmem/cbmem_drv.c
@@ -0,0 +1,95 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <stdbool.h>
+#include <stdlib.h>
+#include <stdio.h>
+
+#include "cbmem_util.h"
+
+/* "ANY" (0) means no backend is active. */
+static enum cbmem_drv_backend_type active_backend = CBMEM_DRV_BACKEND_ANY;
+
+static const char no_backend_error_message[] =
+	"No active/initialized CBMEM backend detected. Terminating.\n";
+
+static bool init_specific_backend(enum cbmem_drv_backend_type backend, bool writeable)
+{
+	switch (backend) {
+	case CBMEM_DRV_BACKEND_DEVMEM:
+		if (!cbmem_devmem_init(writeable))
+			return false;
+		debug("Initialized CBMEM backend: devmem\n");
+		break;
+	case CBMEM_DRV_BACKEND_SYSFS:
+		if (!cbmem_sysfs_init())
+			return false;
+		debug("Initialized CBMEM backend: sysfs\n");
+		break;
+	default:
+		die("Unsupported backend selected. Terminating.\n");
+	}
+
+	active_backend = backend;
+	return true;
+}
+
+bool cbmem_drv_init(enum cbmem_drv_backend_type backend, bool writeable)
+{
+	if (backend != CBMEM_DRV_BACKEND_ANY)
+		return init_specific_backend(backend, writeable);
+
+	/* First try SYSFS backend as it's more secure. */
+	if (!init_specific_backend(CBMEM_DRV_BACKEND_SYSFS, writeable))
+		return init_specific_backend(CBMEM_DRV_BACKEND_DEVMEM, writeable);
+
+	return true;
+}
+
+void cbmem_drv_terminate(void)
+{
+	/* Only /dev/mem driver requires termination. */
+	if (active_backend == CBMEM_DRV_BACKEND_DEVMEM)
+		cbmem_devmem_terminate();
+
+	active_backend = CBMEM_DRV_BACKEND_ANY;
+}
+
+bool cbmem_drv_get_cbmem_entry(uint32_t id, uint8_t **buf_out, size_t *size_out, uint64_t *addr_out)
+{
+	switch (active_backend) {
+	case CBMEM_DRV_BACKEND_DEVMEM:
+		return cbmem_devmem_get_cbmem_entry(id, buf_out, size_out, addr_out);
+	case CBMEM_DRV_BACKEND_SYSFS:
+		return cbmem_sysfs_get_cbmem_entry(id, buf_out, size_out, addr_out);
+	default:
+		die(no_backend_error_message);
+	}
+	return false;
+}
+
+bool cbmem_drv_write_cbmem_entry(uint32_t id, uint8_t *buf, size_t buf_size)
+{
+	switch (active_backend) {
+	case CBMEM_DRV_BACKEND_DEVMEM:
+		return cbmem_devmem_write_cbmem_entry(id, buf, buf_size);
+	case CBMEM_DRV_BACKEND_SYSFS:
+		return cbmem_sysfs_write_cbmem_entry(id, buf, buf_size);
+	default:
+		die(no_backend_error_message);
+	}
+	return false;
+}
+
+void cbmem_drv_foreach_cbmem_entry(cbmem_iterator_callback cb, void *data, bool with_contents)
+{
+	switch (active_backend) {
+	case CBMEM_DRV_BACKEND_DEVMEM:
+		cbmem_devmem_foreach_cbmem_entry(cb, data, with_contents);
+		break;
+	case CBMEM_DRV_BACKEND_SYSFS:
+		cbmem_sysfs_foreach_cbmem_entry(cb, data, with_contents);
+		break;
+	default:
+		die(no_backend_error_message);
+	}
+}
diff --git a/util/cbmem/cbmem_util.h b/util/cbmem/cbmem_util.h
index 8e513c1f32..738e7d35b9 100644
--- a/util/cbmem/cbmem_util.h
+++ b/util/cbmem/cbmem_util.h
@@ -46,6 +46,62 @@ struct cbmem_console {
 typedef bool (*cbmem_iterator_callback)(const uint32_t id, const uint64_t physical_address,
 					const uint8_t *buf, const size_t size, void *data);
 
+/* Common CBMEM access API */
+
+enum cbmem_drv_backend_type {
+	CBMEM_DRV_BACKEND_ANY,
+	CBMEM_DRV_BACKEND_DEVMEM,
+	CBMEM_DRV_BACKEND_SYSFS,
+};
+
+/**
+ * Pick and initialize CBMEM driver. Function can either probe for available drivers or initialize only the selected one.
+ *
+ * @param backend preferred CBMEM backend to initialize.
+ * @param writeable initialize CBMEM driver in writeable mode. Required by devmem driver to modify CBMEM.
+ *
+ * @returns true on success, false otherwise.
+ */
+bool cbmem_drv_init(enum cbmem_drv_backend_type backend, bool writeable);
+
+/**
+ * Cleanup and terminate previously initialized CBMEM driver.
+ * **MUST** be called if cbmem_drv_init() succeeded.
+ */
+void cbmem_drv_terminate(void);
+
+/**
+ * Get CBMEM entry as an allocated buffer.
+ *
+ * @param id CBMEM_ID_* value.
+ * @param buf_out return pointer for the allocated buffer containing entry contents.
+ * @param size_out size of returned buffer.
+ * @param addr_out pointer to the output buffer for entry address in physical memory. Optional.
+ *
+ * @returns true on success, false otherwise.
+ */
+bool cbmem_drv_get_cbmem_entry(uint32_t id, uint8_t **buf_out, size_t *size_out, uint64_t *addr_out);
+
+/**
+ * Write provided buffer contents to the CBMEM entry.
+ *
+ * @param id CBMEM_ID_* value.
+ * @param buf pointer to the source buffer.
+ * @param buf_size size of the source buffer.
+ *
+ * @returns true on success, false otherwise.
+ */
+bool cbmem_drv_write_cbmem_entry(uint32_t id, uint8_t *buf, size_t buf_size);
+
+/**
+ * Backend-specific function iterating over CBMEM entries.
+ *
+ * @param cb user callback function to call during iteration.
+ * @param data pointer to the context data for the callback.
+ * @param with_contents tells whether the callback should get NULL (false) or copy of the entry (true).
+ */
+void cbmem_drv_foreach_cbmem_entry(cbmem_iterator_callback cb, void *data, bool with_contents);
+
 /* API for accessing CBMEM via /dev/mem */
 
 /**
@@ -94,3 +150,45 @@ bool cbmem_devmem_write_cbmem_entry(uint32_t id, uint8_t *buf, size_t buf_size);
  */
 void cbmem_devmem_foreach_cbmem_entry(cbmem_iterator_callback cb, void *data,
 				      bool with_contents);
+
+/* API for accessing CBMEM via sysfs entries */
+
+/**
+ * Initialize the sysfs driver.
+ *
+ * @returns true on success, false otherwise.
+ */
+bool cbmem_sysfs_init(void);
+
+/**
+ * Get CBMEM entry as an allocated buffer.
+ *
+ * @param id CBMEM_ID_* value.
+ * @param buf_out return pointer for the allocated buffer containing entry contents.
+ * @param size_out size of returned buffer.
+ * @param addr_out pointer to the output buffer for entry address in physical memory. Optional.
+ *
+ * @returns true on success, false otherwise.
+ */
+bool cbmem_sysfs_get_cbmem_entry(uint32_t id, uint8_t **buf_out, size_t *size_out, uint64_t *addr_out);
+
+/**
+ * Write provided buffer contents to the CBMEM entry.
+ *
+ * @param id CBMEM_ID_* value.
+ * @param buf pointer to the source buffer.
+ * @param buf_size size of the source buffer.
+ *
+ * @returns true on success, false otherwise.
+ */
+bool cbmem_sysfs_write_cbmem_entry(uint32_t id, uint8_t *buf, size_t buf_size);
+
+/**
+ * Backend-specific function iterating over CBMEM entries.
+ *
+ * @param cb user callback function to call during iteration.
+ * @param data pointer to the context data for the callback.
+ * @param with_contents tells whether the callback should get NULL (false) or copy of the entry (true).
+ */
+void cbmem_sysfs_foreach_cbmem_entry(cbmem_iterator_callback cb, void *data,
+				     bool with_contents);
diff --git a/util/cbmem/sysfs_drv.c b/util/cbmem/sysfs_drv.c
new file mode 100644
index 0000000000..2820bbd4ee
--- /dev/null
+++ b/util/cbmem/sysfs_drv.c
@@ -0,0 +1,266 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <errno.h>
+#include <inttypes.h>
+#include <stdbool.h>
+#include <stdint.h>
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+
+#include <dirent.h>
+#include <fcntl.h>
+#include <unistd.h>
+#include <sys/mman.h>
+#include <sys/stat.h>
+#include <sys/types.h>
+
+#if defined(__linux__) || defined(__ANDROID__)
+#include <linux/fs.h>
+#include <sys/ioctl.h>
+#endif
+
+#include <commonlib/bsd/cbmem_id.h>
+#include <commonlib/bsd/ipchksum.h>
+#include <commonlib/coreboot_tables.h>
+#include <commonlib/helpers.h>
+#include <commonlib/timestamp_serialized.h>
+#include <commonlib/tpm_log_serialized.h>
+
+#include "cbmem_util.h"
+
+#define CBMEM_SYSFS_BASE_DIR               "/sys/bus/coreboot/devices/"
+#define CBMEM_SYSFS_ENTRY_DIR_NAME_PREFIX  "cbmem-"
+#define CBMEM_SYSFS_ENTRY_DIR_NAME_SCN_FMT CBMEM_SYSFS_ENTRY_DIR_NAME_PREFIX "%8" SCNx32
+#define CBMEM_SYSFS_ENTRY_DIR_NAME_PRI_FMT CBMEM_SYSFS_ENTRY_DIR_NAME_PREFIX "%08" PRIx32
+#define CBMEM_SYSFS_ENTRY_DIR_PATH_PRI_FMT \
+	CBMEM_SYSFS_BASE_DIR CBMEM_SYSFS_ENTRY_DIR_NAME_PRI_FMT
+
+enum cbmem_sysfs_path_type {
+	CBMEM_SYSFS_PATH_BASE,
+	CBMEM_SYSFS_PATH_ADDRESS,
+	CBMEM_SYSFS_PATH_MEM,
+	CBMEM_SYSFS_PATH_SIZE,
+};
+
+/* Maximum filesystem path length. */
+#define PATH_MAX_LEN 1024
+
+/**
+ * Create new path for CBMEM entry of a requested type. free() path_out after use.
+ *
+ * @param id CBMEM_ID_* value.
+ * @param t path type.
+ * @param path_out output pointer to created path.
+ */
+static void new_sysfs_path(uint32_t id, enum cbmem_sysfs_path_type t, char *path_out, size_t path_out_max_size)
+{
+	const char *const type2str[] = {
+		[CBMEM_SYSFS_PATH_BASE] = "",
+		[CBMEM_SYSFS_PATH_ADDRESS] = "/address",
+		[CBMEM_SYSFS_PATH_MEM] = "/mem",
+		[CBMEM_SYSFS_PATH_SIZE] = "/size"
+	};
+
+	if (t >= ARRAY_SIZE(type2str))
+		die("Incorrect path type requested: %d\n", t);
+
+	if (snprintf(path_out, path_out_max_size, CBMEM_SYSFS_ENTRY_DIR_PATH_PRI_FMT "%s", id,
+		     type2str[t]) <= 0)
+		die("Unable to create sysfs path string for coreboot table: %#" PRIx32
+		    ". Path type: %d. Error: %s\n",
+		    id, t, strerror(errno));
+}
+
+bool cbmem_sysfs_init(void)
+{
+	char path[PATH_MAX_LEN];
+
+	for (enum cbmem_sysfs_path_type t = CBMEM_SYSFS_PATH_ADDRESS; t <= CBMEM_SYSFS_PATH_SIZE; ++t) {
+		new_sysfs_path(CBMEM_ID_CBTABLE, t, path, sizeof(path));
+
+		FILE *f = fopen(path, "rb");
+		if (!f) {
+			debug("Unable to open path %s for reading. Error: %s\n", path, strerror(errno));
+			return false;
+		}
+
+		uint8_t test_byte = 0;
+		if (fread(&test_byte, 1, 1, f) != 1) {
+			debug("Unable to read data from %s. Error: %s\n", path, strerror(errno));
+			return false;
+		}
+
+		fclose(f);
+	}
+	return true;
+}
+
+static bool cbmem_sysfs_probe_cbmem_entry(uint32_t id, uint64_t *addr_out, size_t *size_out)
+{
+	char path[PATH_MAX_LEN];
+
+	new_sysfs_path(id, CBMEM_SYSFS_PATH_ADDRESS, path, sizeof(path));
+
+	FILE *address_file = fopen(path, "rb");
+	if (!address_file) {
+		debug("Unable to access CBMEM entry id: %#" PRIx32
+		      " address file at %s. Error: %s\n",
+		      id, path, strerror(errno));
+		return false;
+	}
+
+	if (fscanf(address_file, "%" SCNx64, addr_out) != 1) {
+		debug("Read from %s failed.\n", path);
+		fclose(address_file);
+		return false;
+	}
+	fclose(address_file);
+
+	new_sysfs_path(id,  CBMEM_SYSFS_PATH_SIZE, path, sizeof(path));
+
+	FILE *size_file = fopen(path, "rb");
+	if (!size_file) {
+		debug("Unable to access CBMEM entry id: %#" PRIx32
+		      " size file at %s. Error: %s\n",
+		      id, path, strerror(errno));
+		return false;
+	}
+
+	if (fscanf(size_file, "%zx", size_out) != 1) {
+		debug("Read from %s failed.\n", path);
+		fclose(size_file);
+		*addr_out = 0;
+		return false;
+	}
+	fclose(size_file);
+
+	return true;
+}
+
+static void fetch_cbmem_entry(const uint32_t id, const size_t size, uint8_t **buf_out)
+{
+	char path[PATH_MAX_LEN];
+
+	new_sysfs_path(id, CBMEM_SYSFS_PATH_MEM, path, sizeof(path));
+
+	FILE *mem_file = fopen(path, "rb");
+	if (!mem_file)
+		die("Unable to open mem file for CBMEM entry id: %#" PRIx32
+		    " at %s. Error: %s\n",
+		    id, path, strerror(errno));
+
+	*buf_out = malloc(size);
+	if (!buf_out)
+		die("Unable to allocate memory for CBMEM entry id: %#" PRIx32
+		    " of size: %zuB.\n",
+		    id, size);
+
+	if (fread(*buf_out, 1, size, mem_file) != size)
+		die("Unable to correctly read memory of CBMEM entry id: %#" PRIx32
+		    " at %s. Error: %s\n",
+		    id, path, strerror(errno));
+
+	fclose(mem_file);
+}
+
+bool cbmem_sysfs_get_cbmem_entry(uint32_t id, uint8_t **buf_out, size_t *size_out, uint64_t *addr_out)
+{
+	uint64_t addr;
+	size_t size;
+
+	if (!cbmem_sysfs_probe_cbmem_entry(id, &addr, &size)) {
+		debug("CBMEM entry id: %#" PRIx32 " not found.\n", id);
+		return false;
+	}
+
+	fetch_cbmem_entry(id, size, buf_out);
+	if (size_out)
+		*size_out = size;
+	if (addr_out)
+		*addr_out = addr;
+	return true;
+}
+
+bool cbmem_sysfs_write_cbmem_entry(uint32_t id, uint8_t *buf, size_t buf_size)
+{
+	char path[PATH_MAX_LEN];
+	uint64_t addr;
+	size_t size;
+
+	if (!cbmem_sysfs_probe_cbmem_entry(id, &addr, &size)) {
+		debug("Unable to find CBMEM entry id: %#" PRIx32 "\n", id);
+		return false;
+	}
+
+	if (buf_size > size)
+		die("Attempting to write %zu bytes to CBMEM entry id: %#" PRIx32
+		    " of %zu bytes. Operation not possible.\n",
+		    buf_size, id, size);
+
+	new_sysfs_path(id, CBMEM_SYSFS_PATH_MEM, path, sizeof(path));
+
+	FILE *mem_file = fopen(path, "rb+");
+	if (!mem_file)
+		die("Unable to open mem file for CBMEM entry id: %#" PRIx32
+		    " at %s. Error: %s\n",
+		    id, path, strerror(errno));
+
+	if (fwrite(buf, 1, buf_size, mem_file) != buf_size)
+		die("Unable to correctly write memory of CBMEM entry id: %#" PRIx32
+		    " at %s. Error: %s\n",
+		    id, path, strerror(errno));
+
+	fclose(mem_file);
+
+	return true;
+}
+
+void cbmem_sysfs_foreach_cbmem_entry(cbmem_iterator_callback cb, void *data, bool with_contents)
+{
+	DIR *dir;
+	struct dirent *entry;
+
+	if ((dir = opendir(CBMEM_SYSFS_BASE_DIR)) == NULL)
+		die("Unable to open directory containing CBMEM entries. Path: %s. Error: %s\n",
+		    CBMEM_SYSFS_BASE_DIR, strerror(errno));
+
+	while ((entry = readdir(dir)) != NULL) {
+		debug("Checking path: %s%s\n", CBMEM_SYSFS_BASE_DIR, entry->d_name);
+		/* Check directory name prefix */
+		if (strncmp(entry->d_name, CBMEM_SYSFS_ENTRY_DIR_NAME_PREFIX,
+			    strlen(CBMEM_SYSFS_ENTRY_DIR_NAME_PREFIX)) != 0)
+			continue;
+
+		uint32_t id = 0;
+		/* Extract CBMEM entry id from the directory name.
+		   If it fails, then directory is not a correct entry. */
+		if (sscanf(entry->d_name, CBMEM_SYSFS_ENTRY_DIR_NAME_SCN_FMT, &id) != 1)
+			continue;
+
+		uint64_t addr = 0;
+		uint64_t size = 0;
+		uint8_t *buf;
+
+		/* If entry was not found or previously matched directory
+		   does not contain necessary files, then omit the entry. */
+		if (!cbmem_sysfs_probe_cbmem_entry(id, &addr, &size))
+			continue;
+
+		if (with_contents)
+			fetch_cbmem_entry(id, size, &buf);
+
+		debug("Invoking callback on %s%s\n", CBMEM_SYSFS_BASE_DIR, entry->d_name);
+
+		const bool res = cb(id, addr, buf, size, data);
+
+		if (with_contents)
+			free(buf);
+
+		/* Finish iteration if callback requested it. */
+		if (res)
+			break;
+	}
+
+	closedir(dir);
+}

From 479b39c3e91eec926d577fcd93dbfac42cc4efbc Mon Sep 17 00:00:00 2001
From: Avi Uday <aviuday@google.com>
Date: Wed, 23 Jul 2025 15:19:41 +0530
Subject: [PATCH 1692/3886] mb/google/ocelot: Update wake on touch GPIO

GPP_F18 is the correct wake on touch GPIO, which overrides GPP_DW0_18.

Platform Mapping Document : Rev0p86

BUG=b:394208231
TEST=Touchpad works on ocelot RVP

Change-Id: I4ea9c36a371d69f829ba64bfeb35ab9afccf1e06
Signed-off-by: Avi Uday <aviuday@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88540
Reviewed-by: Sowmya Aralguppe <sowmya.aralguppe@intel.com>
Reviewed-by: Pranava Y N <pranavayn@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/google/ocelot/variants/ocelot/overridetree.cb | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/mainboard/google/ocelot/variants/ocelot/overridetree.cb b/src/mainboard/google/ocelot/variants/ocelot/overridetree.cb
index 56aa468b6e..24e697e972 100644
--- a/src/mainboard/google/ocelot/variants/ocelot/overridetree.cb
+++ b/src/mainboard/google/ocelot/variants/ocelot/overridetree.cb
@@ -542,7 +542,7 @@ chip soc/intel/pantherlake
 				register "generic.desc" = ""Hynitron TOUCHPAD""
 				register "generic.irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_F18_IRQ)"
 				# NOTE: pmc_gpe0_dw0 will be overridden to GPP_F in variant.c.
-				register "generic.wake" = "GPE0_DW0_13"
+				register "generic.wake" = "GPE0_DW0_18"
 				register "generic.uid" = "5"
 				register "generic.detect" = "1"
 				register "hid_desc_reg_offset" = "0x20"

From d7415f5d9a2e3ed09d18e9766cd6ec04db7470ac Mon Sep 17 00:00:00 2001
From: Eren Peng <peng.eren@inventec.corp-partner.google.com>
Date: Thu, 24 Jul 2025 15:48:18 +0800
Subject: [PATCH 1693/3886] mb/google/trulo/var/kaladin: Remove external bypass
 settings

We use internal bypass for kaladin, so remove the external bypass settings

BUG=b:432378989
TEST=Flash and boot up kaladin, test that DUT can enter S0ix

Change-Id: I84207a21f15de2df813387e16065688f409b2523
Signed-off-by: Eren Peng <peng.eren@inventec.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88553
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
---
 .../google/brya/variants/kaladin/overridetree.cb  | 15 ---------------
 1 file changed, 15 deletions(-)

diff --git a/src/mainboard/google/brya/variants/kaladin/overridetree.cb b/src/mainboard/google/brya/variants/kaladin/overridetree.cb
index b46584a491..bb70312c95 100644
--- a/src/mainboard/google/brya/variants/kaladin/overridetree.cb
+++ b/src/mainboard/google/brya/variants/kaladin/overridetree.cb
@@ -67,21 +67,6 @@ chip soc/intel/alderlake
 	register "pch_hda_idisp_link_frequency" = "HDA_LINKFREQ_96MHZ"
 	register "pch_hda_idisp_codec_enable" = "1"
 
-	# Configure external V1P05/Vnn/VnnSx Rails
-	register "ext_fivr_settings" = "{
-		.configure_ext_fivr = 1,
-		.v1p05_enable_bitmap = FIVR_ENABLE_ALL_SX & ~FIVR_ENABLE_S0,
-		.vnn_enable_bitmap = FIVR_ENABLE_ALL_SX,
-		.vnn_sx_enable_bitmap = FIVR_ENABLE_ALL_SX,
-		.v1p05_supported_voltage_bitmap = FIVR_VOLTAGE_NORMAL,
-		.vnn_supported_voltage_bitmap = FIVR_VOLTAGE_MIN_ACTIVE,
-		.v1p05_voltage_mv = 1050,
-		.vnn_voltage_mv = 780,
-		.vnn_sx_voltage_mv = 1050,
-		.v1p05_icc_max_ma = 500,
-		.vnn_icc_max_ma = 500,
-	}"
-
 	# Enable CNVi BT Audio offload
 	register "cnvi_bt_audio_offload" = "1"
 

From a5212f15cef1a478e98015a6d855b3176b21a787 Mon Sep 17 00:00:00 2001
From: Subrata Banik <subratabanik@google.com>
Date: Sat, 26 Jul 2025 20:43:53 +0530
Subject: [PATCH 1694/3886] mb/google/fatcat/var/fatcat: Remove unused GPP_B06
 GPIO configuration

The GPP_B06 pin configuration for ISH_GP_2_SNSR_HDR is never required
for the Panther Lake SoC/ISH. This commit removes the obsolete entry
from the GPIO table, streamlining the configuration.

BUG=b:396557201
TEST=Able to build and boot google/fatcat.

Change-Id: I3f38c52a305d14e21c7fcf2dfb943133ae4a7e45
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88569
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Pranava Y N <pranavayn@google.com>
---
 src/mainboard/google/fatcat/variants/fatcat/gpio.c | 2 --
 1 file changed, 2 deletions(-)

diff --git a/src/mainboard/google/fatcat/variants/fatcat/gpio.c b/src/mainboard/google/fatcat/variants/fatcat/gpio.c
index d8dd67c034..f9a1ba2c74 100644
--- a/src/mainboard/google/fatcat/variants/fatcat/gpio.c
+++ b/src/mainboard/google/fatcat/variants/fatcat/gpio.c
@@ -57,8 +57,6 @@ static const struct pad_config gpio_table[] = {
 	PAD_CFG_NF(GPP_B04, NONE, DEEP, NF4),
 	/* GPP_B05:     ISH_GP_1_SNSR_HDR */
 	PAD_CFG_NF(GPP_B05, NONE, DEEP, NF4),
-	/* GPP_B06:     ISH_GP_2_SNSR_HDR */
-	PAD_CFG_NF(GPP_B06, NONE, DEEP, NF4),
 	/* GPP_B07:     ISH_GP_3_SNSR_HDR */
 	PAD_CFG_NF(GPP_B07, NONE, DEEP, NF4),
 	/* GPP_B08:     ISH_GP_4_SNSR_HDR */

From 6bb199d258401c13ee56b850c94700bbfa639c3a Mon Sep 17 00:00:00 2001
From: Subrata Banik <subratabanik@google.com>
Date: Sat, 26 Jul 2025 20:51:07 +0530
Subject: [PATCH 1695/3886] mb/google/fatcat/var/fatcat: Move `ISH_GP_x` pads
 to fw_config.c

The ISH GPIO pads for `ISH_GP_x` (GPP_B04, GPP_B05, GPP_B07, GPP_B08,
GPP_B22, GPP_B23) were previously configured in the generic gpio_table.
This commit moves their configuration to the `ish_enable_pads` and
`ish_disable_pads` structures within `fw_config.c`.

This change ensures that these ISH-specific pads are only configured
when the ISH is enabled, aligning with best practices for power
management and reducing potential conflicts when ISH is not in use.

BUG=b:396557201
TEST=Able to build and boot google/fatcat w/ ISH enable and/or disable.

Change-Id: I4ef896d220fbe5f9c042c4d9df97d32ac238cbc5
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88570
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Pranava Y N <pranavayn@google.com>
---
 .../google/fatcat/variants/fatcat/fw_config.c | 24 +++++++++++++++++++
 .../google/fatcat/variants/fatcat/gpio.c      | 12 ----------
 2 files changed, 24 insertions(+), 12 deletions(-)

diff --git a/src/mainboard/google/fatcat/variants/fatcat/fw_config.c b/src/mainboard/google/fatcat/variants/fatcat/fw_config.c
index 75a7a06007..e10dfbb389 100644
--- a/src/mainboard/google/fatcat/variants/fatcat/fw_config.c
+++ b/src/mainboard/google/fatcat/variants/fatcat/fw_config.c
@@ -488,6 +488,18 @@ static const struct pad_config thc1_enable_wake[] = {
 };
 
 static const struct pad_config ish_disable_pads[] = {
+	/* GPP_B04:     NC */
+	PAD_NC(GPP_B04, NONE),
+	/* GPP_B05:     NC */
+	PAD_NC(GPP_B05, NONE),
+	/* GPP_B07:     NC */
+	PAD_NC(GPP_B07, NONE),
+	/* GPP_B08:     NC */
+	PAD_NC(GPP_B08, NONE),
+	/* GPP_B22:     NC */
+	PAD_NC(GPP_B22, NONE),
+	/* GPP_B23:     NC */
+	PAD_NC(GPP_B23, NONE),
 	/* GPP_D06:     NC */
 	PAD_NC(GPP_D06, NONE),
 	/* GPP_E05:     NC */
@@ -497,6 +509,18 @@ static const struct pad_config ish_disable_pads[] = {
 };
 
 static const struct pad_config ish_enable_pads[] = {
+	/* GPP_B04:     ISH_GP_0_SNSR_HDR */
+	PAD_CFG_NF(GPP_B04, NONE, DEEP, NF4),
+	/* GPP_B05:     ISH_GP_1_SNSR_HDR */
+	PAD_CFG_NF(GPP_B05, NONE, DEEP, NF4),
+	/* GPP_B07:     ISH_GP_3_SNSR_HDR */
+	PAD_CFG_NF(GPP_B07, NONE, DEEP, NF4),
+	/* GPP_B08:     ISH_GP_4_SNSR_HDR */
+	PAD_CFG_NF(GPP_B08, NONE, DEEP, NF4),
+	/* GPP_B22:     ISH_GP_5_SNSR_HDR */
+	PAD_CFG_NF(GPP_B22, NONE, DEEP, NF4),
+	/* GPP_B23:     ISH_GP_6_SNSR_HDR */
+	PAD_CFG_NF(GPP_B23, NONE, DEEP, NF4),
 	/* GPP_D06:     ISH_UART0_TXD */
 	PAD_CFG_NF(GPP_D06, NONE, DEEP, NF2),
 	/* GPP_E05:     ISH_GP_7_SNSR_HDR */
diff --git a/src/mainboard/google/fatcat/variants/fatcat/gpio.c b/src/mainboard/google/fatcat/variants/fatcat/gpio.c
index f9a1ba2c74..62fc5aed49 100644
--- a/src/mainboard/google/fatcat/variants/fatcat/gpio.c
+++ b/src/mainboard/google/fatcat/variants/fatcat/gpio.c
@@ -53,14 +53,6 @@ static const struct pad_config gpio_table[] = {
 	/* GPP_B03:     ISH_I2C0_SCL_SNSR_HDR */
 	/* NOTE: IOSSTAGE: 'Ignore' for S0ix */
 	PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_B03, NONE, DEEP, NF3),
-	/* GPP_B04:     ISH_GP_0_SNSR_HDR */
-	PAD_CFG_NF(GPP_B04, NONE, DEEP, NF4),
-	/* GPP_B05:     ISH_GP_1_SNSR_HDR */
-	PAD_CFG_NF(GPP_B05, NONE, DEEP, NF4),
-	/* GPP_B07:     ISH_GP_3_SNSR_HDR */
-	PAD_CFG_NF(GPP_B07, NONE, DEEP, NF4),
-	/* GPP_B08:     ISH_GP_4_SNSR_HDR */
-	PAD_CFG_NF(GPP_B08, NONE, DEEP, NF4),
 	/* GPP_B09:     M2_GEN4_SSD_RESET_N */
 	PAD_CFG_GPO(GPP_B09, 1, PLTRST),
 	/* GPP_B10:     GEN4_SSD_PWREN */
@@ -89,10 +81,6 @@ static const struct pad_config gpio_table[] = {
 	PAD_CFG_GPO(GPP_B20, 1, PLTRST),
 	/* GPP_B21:     TCP_RETIMER_FORCE_PWR */
 	PAD_CFG_GPO(GPP_B21, 0, DEEP),
-	/* GPP_B22:     ISH_GP_5_SNSR_HDR */
-	PAD_CFG_NF(GPP_B22, NONE, DEEP, NF4),
-	/* GPP_B23:     ISH_GP_6_SNSR_HDR */
-	PAD_CFG_NF(GPP_B23, NONE, DEEP, NF4),
 	/* GPP_B24:     ESPI_ALERT0_EC_R_N */
 	PAD_NC(GPP_B24, NONE),
 

From 823fa6b8f6976dff0552cc58549f7744190fc1fd Mon Sep 17 00:00:00 2001
From: Hari L <haril@qualcomm.corp-partner.google.com>
Date: Mon, 28 Jul 2025 12:20:49 +0530
Subject: [PATCH 1696/3886] soc/qualcomm/common: Integrate QMP PCIe 4.0 PHY
 2x2/1x4

Enable QMP PCIe 4.0 PHY 2x2/1x4 lanes.
The register details are part of HRD-X1P42100-S1 document.
https://docs.qualcomm.com/bundle/resource/topics/HRD-X1P42100-S1/

TEST= Verified that link is enumerated and NVMe is accessible via PCIE.

Change-Id: I8a3cb1b21e712e588f641f70c040a2334faf0031
Signed-off-by: Hari L <haril@qualcomm.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88543
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
---
 src/soc/qualcomm/common/Kconfig               |   6 +
 src/soc/qualcomm/common/include/soc/pcie.h    |  62 +++++++
 .../common/include/soc/qcom_qmp_phy.h         | 151 +++++++++++++++++-
 src/soc/qualcomm/common/pcie_common.c         | 118 +++++++++++++-
 4 files changed, 332 insertions(+), 5 deletions(-)

diff --git a/src/soc/qualcomm/common/Kconfig b/src/soc/qualcomm/common/Kconfig
index 8a3adf58d7..eca772ce59 100644
--- a/src/soc/qualcomm/common/Kconfig
+++ b/src/soc/qualcomm/common/Kconfig
@@ -12,6 +12,12 @@ config QC_COMMON_QUPV3_2
 	help
 	  Selected by chipsets that has QUPv3 HW Version 2.
 
+config QMP_PHY_2X2_1X4
+	bool
+	default n
+	help
+	  Selected by chipsets that have PCIE QMP PHY 2X2/1X4
+
 if SOC_QUALCOMM_COMMON
 
 config QC_SDI_ENABLE
diff --git a/src/soc/qualcomm/common/include/soc/pcie.h b/src/soc/qualcomm/common/include/soc/pcie.h
index b2f9e45a3d..fa1e603f08 100644
--- a/src/soc/qualcomm/common/include/soc/pcie.h
+++ b/src/soc/qualcomm/common/include/soc/pcie.h
@@ -36,6 +36,15 @@
 #define DEVICE_TYPE_RC			0x4
 #define PCIE_PARF_BDF_TO_SID_CFG	0x2C00
 #define BDF_TO_SID_BYPASS		BIT(0)
+#define PCIE_PARF_PM_CTRL		0x10
+#define REQ_NOT_ENTR_L1			BIT(5)
+#define PCIE_PARF_SLAVE_AXI_ERR_REPORT	0x3C4
+#define AXI_SLAVE_ERR_CRS_BRESP_EN	BIT(14)
+#define PCIE_PARF_AXI_MSTR_WR_ADDR_HALT	0x1A8
+#define PCIE_SRIS_MODE			0x644
+#define PCIE_APP_MARGINING_CTRL		0x2C38
+#define APP_MARGINING_READY		BIT(0)
+#define APP_MARGINING_SW_READY		BIT(1)
 
 /* ELBI */
 #define PCIE3X2_ELBI_SYS_STTS		0x08
@@ -48,8 +57,24 @@
 #define LINK_SPEED_GEN_1		0x1
 #define LINK_SPEED_GEN_2		0x2
 #define LINK_SPEED_GEN_3		0x3
+#define LINK_SPEED_GEN_4		0x4
 #define PCIE_LINK_UP_MS			100
+#define PCIE_PHY_POLL_US		1000
 #define LINK_WAIT_MAX_RETRIES		10
+#define PCIE_AMBA_ERR_RESP_DEFLT_OFF	0x8D0
+#define AMBA_ERR_RESP_CRS_MASK		0x18
+#define PCIE_SPCIE_CAP_OFF_0CH_REG	0x154
+#define PCIE_SPCIE_CAP_OFF_10H_REG	0x158
+#define PCIE_PL16G_CAP_OFF_20H_REG	0x188
+#define PCIE_GEN3_EQ_CONTROL_OFF	0x8A8
+#define GEN3_EQ_PSET_REQ_VEC		0x00FFFF00
+#define PCIE_GEN3_EQ_FB_MODE_DIR_CHANGE_OFF	0x8AC
+#define GEN3_EQ_FMDC_T_MIN_PHASE23	0xF
+#define PCIE_GEN3_RELATED_OFF		0x890
+#define RATE_SHADOW_SEL_MASK		(BIT(25)|BIT(24))
+#define RATE_SHADOW_SEL_VAL		(BIT(24))
+#define PCIE_CAP_HOT_PLUG_CAPABLE	BIT(6)
+#define PCIE_SLOT_CAPABILITIES_REG	0x84
 
 #define COMMAND_MASK			0xffff
 
@@ -66,6 +91,7 @@
 #define PCIE_DBI_RO_WR_EN		BIT(0)
 
 #define PCIE_3x2_NUM_LANES		2
+#define PCIE_1x4_NUM_LANES		4
 #define PCIE_LINK_WIDTH_SPEED_CONTROL	0x80C
 #define PORT_LOGIC_LINK_WIDTH_MASK	(0x1f << 8)
 #define PORT_LOGIC_LINK_WIDTH_1_LANES	(0x1 << 8)
@@ -177,6 +203,7 @@ typedef struct {
 	struct	pcie_region mem;
 } pcie_cntlr_cfg_t;
 
+#if CONFIG(QMP_PHY_2X2_1X4)
 typedef struct {
 	void *qmp_phy_base;
 	void *serdes;
@@ -186,7 +213,32 @@ typedef struct {
 	void *tx1;
 	void *rx1;
 	void *pcs_misc;
+	void *lane0_pcs;
+	void *lane1_pcs;
+	void *lane0_pcie_pcs;
+	void *lane1_pcie_pcs;
+	void *ln_shrd;
+} pcie_qmp_phy_base_t;
+#endif
 
+typedef struct {
+#if !CONFIG(QMP_PHY_2X2_1X4)
+	void *qmp_phy_base;
+	void *serdes;
+	void *tx0;
+	void *rx0;
+	void *pcs;
+	void *tx1;
+	void *rx1;
+	void *pcs_misc;
+	void *lane0_pcs;
+	void *lane1_pcs;
+	void *lane0_pcie_pcs;
+	void *lane1_pcie_pcs;
+#else
+	pcie_qmp_phy_base_t porta;
+	pcie_qmp_phy_base_t portb;
+#endif
 	/* Init sequence for PHY blocks - serdes, tx, rx, pcs */
 	const struct qcom_qmp_phy_init_tbl *serdes_tbl;
 	unsigned int serdes_tbl_num;
@@ -208,6 +260,16 @@ typedef struct {
 	unsigned int pcs_misc_tbl_num;
 	const struct qcom_qmp_phy_init_tbl *pcs_misc_tbl_sec;
 	unsigned int pcs_misc_tbl_num_sec;
+	const struct qcom_qmp_phy_init_tbl *pcs_misc_tbl_thrd;
+	unsigned int pcs_misc_tbl_num_thrd;
+	const struct qcom_qmp_phy_init_tbl *lane0_pcie_pcs_tbl;
+	unsigned int lane0_pcie_pcs_tbl_num;
+	const struct qcom_qmp_phy_init_tbl *lane1_pcie_pcs_tbl;
+	unsigned int lane1_pcie_pcs_tbl_num;
+#if CONFIG(QMP_PHY_2X2_1X4)
+	const struct qcom_qmp_phy_init_tbl *ln_shrd_tbl;
+	unsigned int ln_shrd_tbl_num;
+#endif
 } pcie_qmp_phy_cfg_t;
 
 struct qcom_pcie_cntlr_t {
diff --git a/src/soc/qualcomm/common/include/soc/qcom_qmp_phy.h b/src/soc/qualcomm/common/include/soc/qcom_qmp_phy.h
index ec4ac3465b..046ba82ea2 100644
--- a/src/soc/qualcomm/common/include/soc/qcom_qmp_phy.h
+++ b/src/soc/qualcomm/common/include/soc/qcom_qmp_phy.h
@@ -3,6 +3,7 @@
 #ifndef QCOM_PHY_QMP_H_
 #define QCOM_PHY_QMP_H_
 
+#if !CONFIG(QMP_PHY_2X2_1X4)
 /* Only for QMP V4 PHY - QSERDES COM registers */
 #define QSERDES_V4_COM_SSC_EN_CENTER			0x010
 #define QSERDES_V4_COM_SSC_PER1				0x01c
@@ -269,4 +270,152 @@
 #define QPHY_V4_PCS_PCIE_PRESET_P10_PRE			0xbc
 #define QPHY_V4_PCS_PCIE_PRESET_P10_POST		0xe0
 
-#endif
+#else
+/* Only for QMP V4 2X2_1X4 PHY - QSERDES PLL registers */
+#define QSERDES_V4_PLL_SSC_STEP_SIZE1_MODE1		0x00
+#define QSERDES_V4_PLL_SSC_STEP_SIZE2_MODE1		0x04
+#define QSERDES_V4_PLL_CP_CTRL_MODE1			0x10
+#define QSERDES_V4_PLL_PLL_RCTRL_MODE1			0x14
+#define QSERDES_V4_PLL_PLL_CCTRL_MODE1			0x18
+#define QSERDES_V4_PLL_CORECLK_DIV_MODE1		0x1c
+#define QSERDES_V4_PLL_LOCK_CMP1_MODE1			0x20
+#define QSERDES_V4_PLL_LOCK_CMP2_MODE1			0x24
+#define QSERDES_V4_PLL_DEC_START_MODE1			0x28
+#define QSERDES_V4_PLL_DIV_FRAC_START1_MODE1		0x30
+#define QSERDES_V4_PLL_DIV_FRAC_START2_MODE1		0x34
+#define QSERDES_V4_PLL_DIV_FRAC_START3_MODE1		0x38
+#define QSERDES_V4_PLL_HSCLK_SEL_1			0x3C
+#define QSERDES_V4_PLL_SSC_STEP_SIZE1_MODE0		0x60
+#define QSERDES_V4_PLL_SSC_STEP_SIZE2_MODE0		0x64
+#define QSERDES_V4_PLL_CP_CTRL_MODE0			0x70
+#define QSERDES_V4_PLL_PLL_RCTRL_MODE0			0x74
+#define QSERDES_V4_PLL_PLL_CCTRL_MODE0			0x78
+#define QSERDES_V4_PLL_CORECLK_DIV_MODE0		0x7c
+#define QSERDES_V4_PLL_LOCK_CMP1_MODE0			0x80
+#define QSERDES_V4_PLL_LOCK_CMP2_MODE0			0x84
+#define QSERDES_V4_PLL_DEC_START_MODE0			0x88
+#define QSERDES_V4_PLL_DIV_FRAC_START1_MODE0		0x90
+#define QSERDES_V4_PLL_DIV_FRAC_START2_MODE0		0x94
+#define QSERDES_V4_PLL_DIV_FRAC_START3_MODE0		0x98
+#define QSERDES_V4_PLL_HSCLK_HS_SWITCH_SEL_1		0x9c
+#define QSERDES_V4_PLL_BG_TIMER				0xbc
+#define QSERDES_V4_PLL_SSC_EN_CENTER			0xc0
+#define QSERDES_V4_PLL_SSC_PER1				0xcc
+#define QSERDES_V4_PLL_SSC_PER2				0xd0
+#define QSERDES_V4_PLL_POST_DIV_MUX			0xd8
+#define QSERDES_V4_PLL_BIAS_EN_CLKBUFLR_EN		0xdc
+#define QSERDES_V4_PLL_CLK_ENABLE1			0xe0
+#define QSERDES_V4_PLL_SYS_CLK_CTRL			0xe4
+#define QSERDES_V4_PLL_PLL_IVCO				0xf4
+#define QSERDES_V4_PLL_SYSCLK_EN_SEL			0x110
+#define QSERDES_V4_PLL_LOCK_CMP_EN			0x120
+#define QSERDES_V4_PLL_LOCK_CMP_CFG			0x124
+#define QSERDES_V4_PLL_VCO_TUNE_MAP			0x140
+#define QSERDES_V4_PLL_CLK_SELECT			0x164
+#define QSERDES_V4_PLL_CORE_CLK_EN			0x170
+#define QSERDES_V4_PLL_CMN_CONFIG_1			0x174
+#define QSERDES_V4_PLL_CMN_MISC1			0x184
+#define QSERDES_V4_PLL_CMN_MODE				0x188
+#define QSERDES_V4_PLL_VCO_DC_LEVEL_CTRL		0x198
+
+/* Only for QMP V4 2X2_1X4 PHY - TX registers */
+#define QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX		0x30
+#define QSERDES_V4_TX_RES_CODE_LANE_OFFSET_RX		0x34
+#define QSERDES_V4_TX_LANE_MODE_1			0x78
+#define QSERDES_V4_TX_LANE_MODE_2			0x7c
+#define QSERDES_V4_TX_LANE_MODE_3			0x80
+#define QSERDES_V4_TX_TRAN_DRVR_EMP_EN			0xAC
+
+/* Only for QMP V4 2X2_1X4 PHY - RX registers */
+#define QSERDES_V4_RX_UCDR_FO_GAIN_RATE2		0x08
+#define QSERDES_V4_RX_UCDR_SO_GAIN_RATE2		0x18
+#define QSERDES_V4_RX_UCDR_FO_GAIN_RATE3		0x0c
+#define QSERDES_V4_RX_UCDR_SO_GAIN_RATE3		0x1c
+#define QSERDES_V4_RX_UCDR_PI_CONTROLS			0x20
+#define QSERDES_V4_RX_UCDR_SO_ACC_DEFAULT_VAL_RATE3	0x34
+#define QSERDES_V4_RX_RX_IVCM_CAL_CTRL2			0x9c
+#define QSERDES_V4_RX_RX_IVCM_POSTCAL_OFFSET		0xa0
+#define QSERDES_V4_RX_RX_BKUP_CTRL1			0x22c
+#define QSERDES_V4_RX_DFE_1				0xac
+#define QSERDES_V4_RX_DFE_2				0xb0
+#define QSERDES_V4_RX_DFE_3				0xb4
+#define QSERDES_V4_RX_VGA_CAL_MAN_VAL			0xe8
+#define QSERDES_V4_RX_VGA_CAL_CNTRL1			0xe0
+#define QSERDES_V4_RX_GM_CAL				0x10c
+#define QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4		0x120
+#define QSERDES_V4_RX_SIGDET_ENABLES			0x148
+#define QSERDES_V4_RX_PHPRE_CTRL			0x188
+#define QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET		0x194
+#define QSERDES_V4_RX_Q_PI_INTRINSIC_BIAS_RATE32	0x1dc
+#define QSERDES_V4_RX_RX_MODE_RATE2_B0			0x1f4
+#define QSERDES_V4_RX_RX_MODE_RATE2_B1			0x1f8
+#define QSERDES_V4_RX_RX_MODE_RATE2_B2			0x1fc
+#define QSERDES_V4_RX_RX_MODE_RATE2_B3			0x200
+#define QSERDES_V4_RX_RX_MODE_RATE2_B4			0x204
+#define QSERDES_V4_RX_RX_MODE_RATE2_B5			0x208
+#define QSERDES_V4_RX_RX_MODE_RATE2_B6			0x20c
+#define QSERDES_V4_RX_RX_MODE_RATE3_B0			0x210
+#define QSERDES_V4_RX_RX_MODE_RATE3_B1			0x214
+#define QSERDES_V4_RX_RX_MODE_RATE3_B2			0x218
+#define QSERDES_V4_RX_RX_MODE_RATE3_B3			0x21c
+#define QSERDES_V4_RX_RX_MODE_RATE3_B4			0x220
+#define QSERDES_V4_RX_RX_MODE_RATE3_B5			0x224
+#define QSERDES_V4_RX_RX_MODE_RATE3_B6			0x228
+#define QSERDES_V4_RX_TX_ADPT_CTRL			0xd4
+
+/* Only for QMP V4 2X2_1X4 PHY - Lane Shared registers */
+#define QSERDES_V4_LN_SHRD_RXCLK_DIV2_CTRL		0xA0
+#define QSERDES_V4_LN_SHRD_DFE_DAC_ENABLE1		0xB4
+#define QSERDES_V4_LN_SHRD_TX_ADAPT_POST_THRESH1	0xC4
+#define QSERDES_V4_LN_SHRD_TX_ADAPT_POST_THRESH2	0xC8
+#define QSERDES_V4_LN_SHRD_RX_MODE_RATE_0_1_B0		0xD4
+#define QSERDES_V4_LN_SHRD_RX_MODE_RATE_0_1_B1		0xD8
+#define QSERDES_V4_LN_SHRD_RX_MODE_RATE_0_1_B2		0xDC
+#define QSERDES_V4_LN_SHRD_RX_MODE_RATE_0_1_B3		0xE0
+#define QSERDES_V4_LN_SHRD_RX_MODE_RATE_0_1_B4		0xE4
+#define QSERDES_V4_LN_SHRD_RX_MODE_RATE_0_1_B5		0xE8
+#define QSERDES_V4_LN_SHRD_RX_MODE_RATE_0_1_B6		0xEC
+#define QSERDES_V4_LN_SHRD_RX_MARG_COARSE_THRESH1_RATE210	0xF0
+#define QSERDES_V4_LN_SHRD_RX_MARG_COARSE_THRESH1_RATE3		0xF4
+#define QSERDES_V4_LN_SHRD_RX_MARG_COARSE_THRESH2_RATE210	0xF8
+#define QSERDES_V4_LN_SHRD_RX_MARG_COARSE_THRESH2_RATE3		0xFC
+#define QSERDES_V4_LN_SHRD_RX_MARG_COARSE_THRESH3_RATE210	0x100
+#define QSERDES_V4_LN_SHRD_RX_MARG_COARSE_THRESH3_RATE3		0x104
+#define QSERDES_V4_LN_SHRD_RX_MARG_COARSE_THRESH4_RATE3		0x10C
+#define QSERDES_V4_LN_SHRD_RX_MARG_COARSE_THRESH5_RATE3		0x114
+#define QSERDES_V4_LN_SHRD_RX_MARG_COARSE_THRESH6_RATE3		0x11C
+#define QSERDES_V4_LN_SHRD_RX_SUMMER_CAL_SPD_MODE		0x128
+
+/* Only for QMP V4 2X2_1X4 PHY - PCS COM registers */
+#define QPHY_PCIE4_PCS_COM_G3S2_PRE_GAIN			0x178
+#define QPHY_PCIE4_PCS_COM_RX_SIGDET_LVL			0x190
+#define QPHY_PCIE4_PCS_COM_EQ_CONFIG4				0x1F8
+#define QPHY_PCIE4_PCS_COM_EQ_CONFIG5				0x1FC
+#define QPHY_PCIE4_PCS_COM_PCS_TX_RX_CONFIG			0x1DC
+#define QPHY_PCIE4_PCS_COM_PCS_TX_RX_CONFIG2			0x1E0
+
+/* Only for QMP V4 2X2_1X4 PHY - PCS PCIE registers */
+#define QPHY_PCIE4_PCS_PCIE_ENDPOINT_REFCLK_DRIVE		0x1C
+#define QPHY_PCIE4_PCS_PCIE_OSC_DTCT_ACTIONS			0x90
+#define QPHY_PCIE4_PCS_PCIE_EQ_CONFIG1				0xA0
+#define QPHY_PCIE4_PCS_PCIE_G4_EQ_CONFIG5			0x108
+#define QPHY_PCIE4_PCS_PCIE_G4_PRE_GAIN				0x15C
+#define QPHY_PCIE4_PCS_PCIE_G3_FOM_EQ_CONFIG5			0x1AC
+#define QPHY_PCIE4_PCS_PCIE_G4_FOM_EQ_CONFIG5			0x1C0
+#define QPHY_PCIE4_PCS_PCIE_G3_RXEQEVAL_TIME			0xF0
+#define QPHY_PCIE4_PCS_PCIE_G4_RXEQEVAL_TIME			0xF4
+#define QPHY_PCIE4_PCS_PCIE_RX_MARGINING_CONFIG1		0x17C
+#define QPHY_PCIE4_PCS_PCIE_RX_MARGINING_CONFIG3		0x184
+#define QPHY_PCIE4_PCS_PCIE_RX_MARGINING_CONFIG5		0x18C
+#define QPHY_PCIE4_PCS_PCIE_PCS_TX_RX_CONFIG			0x18
+
+/* Only for QMP V4 2X2_1X4 PHY - Lane 0/1 PCS registers */
+#define QPHY_PCIE4_PCS_LANE0_OUTSIG_MX_CTRL2			0x38
+#define QPHY_PCIE4_PCS_LANE1_OUTSIG_MX_CTRL2			0x38
+#define QPHY_PCIE4_PCS_LANE1_INSIG_SW_CTRL2			0x24
+#define QPHY_PCIE4_PCS_LANE1_INSIG_MX_CTRL2			0x28
+
+/* Only for QMP V4 2X2_1X4 PHY - PCS PCIE MISC registers */
+#define QPHY_PCIE4_PCS_PCIE_POWER_STATE_CONFIG2			0x0C
+#endif  /* QMP_PHY_2X2_1X4 */
+#endif	/* QCOM_PHY_QMP_H_ */
diff --git a/src/soc/qualcomm/common/pcie_common.c b/src/soc/qualcomm/common/pcie_common.c
index b877563a49..2ad32b02b2 100644
--- a/src/soc/qualcomm/common/pcie_common.c
+++ b/src/soc/qualcomm/common/pcie_common.c
@@ -16,6 +16,12 @@
 #define ROOT_PORT_BDF		0x0
 #define ATU_CTRL2		PCIE_ATU_UNR_REGION_CTRL2
 
+#if CONFIG(QMP_PHY_2X2_1X4)
+#define LINK_SPEED_DEFAULT LINK_SPEED_GEN_4
+#else
+#define LINK_SPEED_DEFAULT LINK_SPEED_GEN_2
+#endif
+
 static struct qcom_pcie_cntlr_t qcom_pcie_cfg;
 
 static inline void dw_pcie_dbi_rd_wr(bool enable)
@@ -96,6 +102,43 @@ static void qcom_dw_pcie_configure(uint32_t cap_speed)
 	printk(BIOS_INFO, "PCIe Link speed configured in Gen %d\n", cap_speed);
 }
 
+#if CONFIG(QMP_PHY_2X2_1X4)
+static void post_phy_pwr_up_init(struct qcom_pcie_cntlr_t *pcie)
+{
+	pcie_cntlr_cfg_t *pcierc = pcie->cntlr_cfg;
+	/* configure PCIe to RC mode */
+	write32(pcierc->parf + PCIE_PARF_DEVICE_TYPE, DEVICE_TYPE_RC);
+	dsb();
+	clrbits32(pcierc->parf + PCIE_PARF_SLAVE_AXI_ERR_REPORT, AXI_SLAVE_ERR_CRS_BRESP_EN);
+	clrsetbits32(pcierc->dbi_base + PCIE_AMBA_ERR_RESP_DEFLT_OFF, AMBA_ERR_RESP_CRS_MASK, 0x2);
+	dsb();
+	write32(pcierc->parf + PCIE_PARF_AXI_MSTR_WR_ADDR_HALT, 0x0);
+	write32(pcierc->parf + PCIE_SRIS_MODE, 0x0);
+	write32(pcierc->parf + PCIE_APP_MARGINING_CTRL, (APP_MARGINING_SW_READY | APP_MARGINING_READY));
+	dsb();
+}
+
+static void post_phy_pwr_up_dbi_init(struct qcom_pcie_cntlr_t *pcie)
+{
+	pcie_cntlr_cfg_t *pcierc = pcie->cntlr_cfg;
+	dw_pcie_dbi_rd_wr(true);
+	write32(pcierc->dbi_base + PCIE_SPCIE_CAP_OFF_0CH_REG, 0x55555555);
+	write32(pcierc->dbi_base + PCIE_SPCIE_CAP_OFF_10H_REG, 0x55555555);
+	write32(pcierc->dbi_base + PCIE_PL16G_CAP_OFF_20H_REG, 0x55555555);
+	clrbits32(pcierc->dbi_base + PCIE_SLOT_CAPABILITIES_REG, PCIE_CAP_HOT_PLUG_CAPABLE);
+	dsb();
+	clrsetbits32(pcierc->dbi_base + PCIE_GEN3_RELATED_OFF, RATE_SHADOW_SEL_MASK, 0x0);
+	clrsetbits32(pcierc->dbi_base + PCIE_GEN3_EQ_FB_MODE_DIR_CHANGE_OFF, GEN3_EQ_FMDC_T_MIN_PHASE23, 0x1);
+	clrbits32(pcierc->dbi_base + PCIE_GEN3_EQ_CONTROL_OFF, GEN3_EQ_PSET_REQ_VEC);
+	dsb();
+	clrsetbits32(pcierc->dbi_base + PCIE_GEN3_RELATED_OFF, RATE_SHADOW_SEL_MASK, RATE_SHADOW_SEL_VAL);
+	clrsetbits32(pcierc->dbi_base + PCIE_GEN3_EQ_FB_MODE_DIR_CHANGE_OFF, GEN3_EQ_FMDC_T_MIN_PHASE23, 0x1);
+	clrbits32(pcierc->dbi_base + PCIE_GEN3_EQ_CONTROL_OFF, GEN3_EQ_PSET_REQ_VEC);
+	dsb();
+	dw_pcie_dbi_rd_wr(false);
+}
+#endif
+
 /**
  * is_pcie_link_up() - Return the link state
  *
@@ -130,7 +173,7 @@ static enum cb_err qcom_pcie_dw_link_up(struct qcom_pcie_cntlr_t *pcie)
 	}
 
 	/* DW pre link configurations */
-	qcom_dw_pcie_configure(LINK_SPEED_GEN_2);
+	qcom_dw_pcie_configure(LINK_SPEED_DEFAULT);
 
 	/* enable link training */
 	setbits32(pcie->cntlr_cfg->parf + PCIE_PARF_LTSSM, LTSSM_EN);
@@ -282,7 +325,7 @@ static void qcom_qmp_phy_configure(void *base, const struct qcom_qmp_phy_init_tb
 {
 	qcom_qmp_phy_config_lane(base, tbl, num, 0xff);
 }
-
+#if !CONFIG(QMP_PHY_2X2_1X4)
 static enum cb_err qcom_qmp_phy_power_on(pcie_qmp_phy_cfg_t *qphy)
 {
 	uint64_t lock_us;
@@ -317,7 +360,7 @@ static enum cb_err qcom_qmp_phy_power_on(pcie_qmp_phy_cfg_t *qphy)
 	 * Wait for PHY initialization to be done
 	 * PCS_STATUS: wait for 1ms for PHY STATUS bit to be set
 	 */
-	lock_us = wait_us(1000, !(read32(qphy->qmp_phy_base + QPHY_PCS_STATUS) & PHY_STATUS));
+	lock_us = wait_us(PCIE_PHY_POLL_US, !(read32(qphy->qmp_phy_base + QPHY_PCS_STATUS) & PHY_STATUS));
 	if (!lock_us) {
 		printk(BIOS_ERR, "PCIe QMP PHY PLL failed to lock in 1ms\n");
 		return CB_ERR;
@@ -329,6 +372,70 @@ static enum cb_err qcom_qmp_phy_power_on(pcie_qmp_phy_cfg_t *qphy)
 
 	return CB_SUCCESS;
 }
+#else
+static void configure_phy_port(pcie_qmp_phy_base_t *port, pcie_qmp_phy_cfg_t *qphy, int lane_base)
+{
+	qcom_qmp_phy_config_lane(port->tx0, qphy->tx_tbl, qphy->tx_tbl_num, lane_base);
+	qcom_qmp_phy_config_lane(port->rx0, qphy->rx_tbl, qphy->rx_tbl_num, lane_base);
+	qcom_qmp_phy_config_lane(port->tx1, qphy->tx_tbl, qphy->tx_tbl_num, lane_base + 1);
+	qcom_qmp_phy_config_lane(port->rx1, qphy->rx_tbl, qphy->rx_tbl_num, lane_base + 1);
+	qcom_qmp_phy_configure(port->ln_shrd, qphy->ln_shrd_tbl, qphy->ln_shrd_tbl_num);
+	qcom_qmp_phy_configure(port->serdes, qphy->serdes_tbl, qphy->serdes_tbl_num);
+	qcom_qmp_phy_configure(port->pcs, qphy->pcs_tbl, qphy->pcs_tbl_num);
+	qcom_qmp_phy_configure(port->pcs_misc, qphy->pcs_misc_tbl, qphy->pcs_misc_tbl_num);
+	qcom_qmp_phy_configure(port->pcs, qphy->pcs_tbl_sec, qphy->pcs_tbl_num_sec);
+	qcom_qmp_phy_configure(port->pcs_misc, qphy->pcs_misc_tbl_sec, qphy->pcs_misc_tbl_num_sec);
+	qcom_qmp_phy_configure(port->pcs_misc, qphy->pcs_misc_tbl_thrd, qphy->pcs_misc_tbl_num_thrd);
+	qcom_qmp_phy_configure(port->lane0_pcie_pcs, qphy->lane0_pcie_pcs_tbl, qphy->lane0_pcie_pcs_tbl_num);
+	qcom_qmp_phy_configure(port->lane1_pcie_pcs, qphy->lane1_pcie_pcs_tbl, qphy->lane1_pcie_pcs_tbl_num);
+}
+
+static enum cb_err qcom_qmp_phy_power_on(pcie_qmp_phy_cfg_t *qphy)
+{
+	uint64_t lock_us;
+
+	qcom_dw_pcie_enable_pipe_clock();
+
+	/*
+	 * The PHY has two independent CSR interfaces that control lanes 0/1 and
+	 * lanes 2/3. These are called PortA and PortB.
+	 *
+	 * In 1x4 mode, the PCS is only used in PortA and PortB
+	 * writes are ignored, except for lane-specific registers
+	 */
+	/* Select Lane config 0x1 - 1x4 mode 0x0 - 2x2mode */
+	write32(TCSR_PCIE_CTRL_4LN_CONFIG_SEL, 0x1);
+	write32(qphy->porta.serdes + QSERDES_V4_PLL_BIAS_EN_CLKBUFLR_EN, 0x1c);
+	write32(qphy->portb.serdes + QSERDES_V4_PLL_BIAS_EN_CLKBUFLR_EN, 0x1c);
+
+	/* Release powerdown mode and allow endpoint refclk drive */
+	write32(qphy->porta.pcs + QPHY_PCS_PWR_DWN_CNTRL, SW_PWRDN | REFCLK_DRV_DSBL);
+
+	/* Write all PLL/TX/RX/PCS config registers on Port A */
+	configure_phy_port(&qphy->porta, qphy, 1);
+	/* Write all PLL/TX/RX/PCS config registers on Port B */
+	configure_phy_port(&qphy->portb, qphy, 3);
+
+	/* Release software reset of PCS/Serdes */
+	clrbits32(qphy->porta.pcs + QPHY_SW_RESET, SW_RESET);
+
+	/* start PCS/Serdes to operation mode */
+	write32(qphy->porta.pcs  + QPHY_START_CTRL, PCS_START | SERDES_START);
+
+	/*
+	 * Wait for PHY initialization to be done
+	 * PCS_STATUS: wait for 1ms for PHY STATUS bit to be set
+	 */
+	lock_us = wait_us(PCIE_PHY_POLL_US, !(read32(qphy->porta.qmp_phy_base + QPHY_PCS_STATUS) & PHY_STATUS));
+	if (!lock_us) {
+		printk(BIOS_ERR, "PCIe QMP PHY PLL failed to lock in 1ms\n");
+		return CB_ERR;
+	}
+
+	printk(BIOS_DEBUG, "PCIe QPHY Initialized took %lldus\n", lock_us);
+	return CB_SUCCESS;
+}
+#endif
 
 /*
  * Reset the PCIe PHY core.
@@ -394,7 +501,10 @@ static enum cb_err qcom_dw_pcie_enable(struct qcom_pcie_cntlr_t *pcie)
 	}
 
 	qcom_dw_pcie_setup_rc(pcie);
-
+#if CONFIG(QMP_PHY_2X2_1X4)
+	post_phy_pwr_up_init(pcie);
+	post_phy_pwr_up_dbi_init(pcie);
+#endif
 	/* de-assert PCIe reset link to bring EP out of reset */
 	gpio_set(pcierc->perst, 1);
 

From 6f115f7bf00706f93a2950b13a39230f756d641b Mon Sep 17 00:00:00 2001
From: Hari L <haril@qualcomm.corp-partner.google.com>
Date: Mon, 28 Jul 2025 12:41:55 +0530
Subject: [PATCH 1697/3886] soc/qualcomm/x1p42100: Configure Gen4 PHY link for
 x1p42100

Add support to enable QMP PCIe 4.0 PHY 2x2/1x4 lanes.
The register details are part of HRD-X1P42100-S1 document.
https://docs.qualcomm.com/bundle/resource/topics/HRD-X1P42100-S1/

TEST= Verified that link is enumerated and NVMe is accessible via PCIE.

Change-Id: I9dd9a5340f28326ebabf12489c11e7f73f2c8d2f
Signed-off-by: Hari L <haril@qualcomm.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88583
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
---
 src/soc/qualcomm/x1p42100/Kconfig             |   1 +
 .../x1p42100/include/soc/addressmap.h         |   1 +
 src/soc/qualcomm/x1p42100/pcie.c              | 245 +++++++++++++++++-
 src/soc/qualcomm/x1p42100/soc.c               |  10 +-
 4 files changed, 249 insertions(+), 8 deletions(-)

diff --git a/src/soc/qualcomm/x1p42100/Kconfig b/src/soc/qualcomm/x1p42100/Kconfig
index 8ae8beadde..826df95372 100644
--- a/src/soc/qualcomm/x1p42100/Kconfig
+++ b/src/soc/qualcomm/x1p42100/Kconfig
@@ -23,6 +23,7 @@ config SOC_QUALCOMM_X1P42100
 	select MAINBOARD_HAS_NATIVE_VGA_INIT
 	select PCI
 	select QC_COMMON_QUPV3_2
+	select QMP_PHY_2X2_1X4
 	select NO_ECAM_MMCONF_SUPPORT
 	select SDHCI_CONTROLLER
 	select SOC_QUALCOMM_COMMON
diff --git a/src/soc/qualcomm/x1p42100/include/soc/addressmap.h b/src/soc/qualcomm/x1p42100/include/soc/addressmap.h
index 3f66326a12..e0cc910d44 100644
--- a/src/soc/qualcomm/x1p42100/include/soc/addressmap.h
+++ b/src/soc/qualcomm/x1p42100/include/soc/addressmap.h
@@ -105,5 +105,6 @@
 
 /* TCSR */
 #define TCSR_GCC_PCIE_4L_CLKREF_EN_PCIE_ENABLE           ((void *)0x1FD512C)
+#define TCSR_PCIE_CTRL_4LN_CONFIG_SEL            ((void *)0x1FDA000)
 
 #endif /*  __SOC_QUALCOMM_X1P42100_ADDRESS_MAP_H__ */
diff --git a/src/soc/qualcomm/x1p42100/pcie.c b/src/soc/qualcomm/x1p42100/pcie.c
index 031e15d8c8..a456e2805d 100644
--- a/src/soc/qualcomm/x1p42100/pcie.c
+++ b/src/soc/qualcomm/x1p42100/pcie.c
@@ -4,11 +4,251 @@
 #include <device/device.h>
 #include <device/mmio.h>
 #include <device/pci.h>
+#include <gpio.h>
 #include <soc/addressmap.h>
 #include <soc/clock.h>
 #include <soc/qcom_qmp_phy.h>
 #include <soc/pcie.h>
 
+#define NVME_REG_EN GPIO(18)
+
+static const struct qcom_qmp_phy_init_tbl x1p42100_qmp_pcie_serdes_pll_tbl[] = {
+	QMP_PHY_INIT_CFG(QSERDES_V4_PLL_SSC_STEP_SIZE1_MODE1, 0x26),
+	QMP_PHY_INIT_CFG(QSERDES_V4_PLL_SSC_STEP_SIZE2_MODE1, 0x03),
+	QMP_PHY_INIT_CFG(QSERDES_V4_PLL_CP_CTRL_MODE1, 0x06),
+	QMP_PHY_INIT_CFG(QSERDES_V4_PLL_PLL_RCTRL_MODE1, 0x16),
+	QMP_PHY_INIT_CFG(QSERDES_V4_PLL_PLL_CCTRL_MODE1, 0x36),
+	QMP_PHY_INIT_CFG(QSERDES_V4_PLL_CORECLK_DIV_MODE1, 0x04),
+	QMP_PHY_INIT_CFG(QSERDES_V4_PLL_LOCK_CMP1_MODE1, 0x0A),
+	QMP_PHY_INIT_CFG(QSERDES_V4_PLL_LOCK_CMP2_MODE1, 0x1A),
+	QMP_PHY_INIT_CFG(QSERDES_V4_PLL_DEC_START_MODE1, 0x68),
+	QMP_PHY_INIT_CFG(QSERDES_V4_PLL_DIV_FRAC_START1_MODE1, 0xAB),
+	QMP_PHY_INIT_CFG(QSERDES_V4_PLL_DIV_FRAC_START2_MODE1, 0xAA),
+	QMP_PHY_INIT_CFG(QSERDES_V4_PLL_DIV_FRAC_START3_MODE1, 0x02),
+	QMP_PHY_INIT_CFG(QSERDES_V4_PLL_HSCLK_SEL_1, 0x12),
+	QMP_PHY_INIT_CFG(QSERDES_V4_PLL_SSC_STEP_SIZE1_MODE0, 0xF8),
+	QMP_PHY_INIT_CFG(QSERDES_V4_PLL_SSC_STEP_SIZE2_MODE0, 0x01),
+	QMP_PHY_INIT_CFG(QSERDES_V4_PLL_CP_CTRL_MODE0, 0x06),
+	QMP_PHY_INIT_CFG(QSERDES_V4_PLL_PLL_RCTRL_MODE0, 0x16),
+	QMP_PHY_INIT_CFG(QSERDES_V4_PLL_PLL_CCTRL_MODE0, 0x36),
+	QMP_PHY_INIT_CFG(QSERDES_V4_PLL_CORECLK_DIV_MODE0, 0x0A),
+	QMP_PHY_INIT_CFG(QSERDES_V4_PLL_LOCK_CMP1_MODE0, 0x04),
+	QMP_PHY_INIT_CFG(QSERDES_V4_PLL_LOCK_CMP2_MODE0, 0x0D),
+	QMP_PHY_INIT_CFG(QSERDES_V4_PLL_DEC_START_MODE0, 0x41),
+	QMP_PHY_INIT_CFG(QSERDES_V4_PLL_DIV_FRAC_START1_MODE0, 0xAB),
+	QMP_PHY_INIT_CFG(QSERDES_V4_PLL_DIV_FRAC_START2_MODE0, 0xAA),
+	QMP_PHY_INIT_CFG(QSERDES_V4_PLL_DIV_FRAC_START3_MODE0, 0x01),
+	QMP_PHY_INIT_CFG(QSERDES_V4_PLL_HSCLK_HS_SWITCH_SEL_1, 0x00),
+	QMP_PHY_INIT_CFG(QSERDES_V4_PLL_BG_TIMER, 0x0A),
+	QMP_PHY_INIT_CFG(QSERDES_V4_PLL_SSC_EN_CENTER, 0x01),
+	QMP_PHY_INIT_CFG(QSERDES_V4_PLL_SSC_PER1, 0x62),
+	QMP_PHY_INIT_CFG(QSERDES_V4_PLL_SSC_PER2, 0x02),
+	QMP_PHY_INIT_CFG(QSERDES_V4_PLL_POST_DIV_MUX, 0x40),
+	QMP_PHY_INIT_CFG(QSERDES_V4_PLL_CLK_ENABLE1, 0x90),
+	QMP_PHY_INIT_CFG(QSERDES_V4_PLL_SYS_CLK_CTRL, 0x82),
+	QMP_PHY_INIT_CFG(QSERDES_V4_PLL_PLL_IVCO, 0x0f),
+	QMP_PHY_INIT_CFG(QSERDES_V4_PLL_SYSCLK_EN_SEL, 0x08),
+	QMP_PHY_INIT_CFG(QSERDES_V4_PLL_LOCK_CMP_EN, 0x46),
+	QMP_PHY_INIT_CFG(QSERDES_V4_PLL_LOCK_CMP_CFG, 0x04),
+	QMP_PHY_INIT_CFG(QSERDES_V4_PLL_VCO_TUNE_MAP, 0x14),
+	QMP_PHY_INIT_CFG(QSERDES_V4_PLL_CLK_SELECT, 0x34),
+	QMP_PHY_INIT_CFG(QSERDES_V4_PLL_CORE_CLK_EN, 0xA0),
+	QMP_PHY_INIT_CFG(QSERDES_V4_PLL_CMN_CONFIG_1, 0x06),
+	QMP_PHY_INIT_CFG(QSERDES_V4_PLL_CMN_MISC1, 0x88),
+	QMP_PHY_INIT_CFG(QSERDES_V4_PLL_CMN_MODE, 0x14),
+	QMP_PHY_INIT_CFG(QSERDES_V4_PLL_VCO_DC_LEVEL_CTRL, 0x0F),
+};
+
+static const struct qcom_qmp_phy_init_tbl x1p42100_qmp_pcie_tx_tbl[] = {
+	QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x1D),
+	QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_RX, 0x03),
+	QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x01),
+	QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_2, 0x10),
+	QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_3, 0x90),
+	QMP_PHY_INIT_CFG(QSERDES_V4_TX_TRAN_DRVR_EMP_EN, 0x34),
+};
+
+static const struct qcom_qmp_phy_init_tbl x1p42100_qmp_pcie_rx_tbl[] = {
+	QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN_RATE2, 0x0C),
+	QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN_RATE2, 0x04),
+	QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN_RATE3, 0x0A),
+	QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN_RATE3, 0x05),
+	QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x16),
+	QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_ACC_DEFAULT_VAL_RATE3, 0x00),
+	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IVCM_CAL_CTRL2, 0x82),
+	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IVCM_POSTCAL_OFFSET, 0x00),
+	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_BKUP_CTRL1, 0x12),
+	QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_1, 0x01),
+	QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_2, 0x01),
+	QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_3, 0x45),
+	QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_MAN_VAL, 0x0A),
+	QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x00),
+	QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x0D),
+	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0B),
+	QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_ENABLES, 0x1C),
+	QMP_PHY_INIT_CFG(QSERDES_V4_RX_PHPRE_CTRL, 0x20),
+	QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
+	QMP_PHY_INIT_CFG(QSERDES_V4_RX_Q_PI_INTRINSIC_BIAS_RATE32, 0x01),
+	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_RATE2_B0, 0x14),
+	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_RATE2_B1, 0xB3),
+	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_RATE2_B2, 0x58),
+	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_RATE2_B3, 0x9A),
+	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_RATE2_B4, 0x28),
+	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_RATE2_B5, 0xB6),
+	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_RATE2_B6, 0xEE),
+	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_RATE3_B0, 0xE4),
+	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_RATE3_B1, 0xA4),
+	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_RATE3_B2, 0x60),
+	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_RATE3_B3, 0xDF),
+	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_RATE3_B4, 0x4B),
+	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_RATE3_B5, 0x76),
+	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_RATE3_B6, 0xFF),
+	QMP_PHY_INIT_CFG(QSERDES_V4_RX_TX_ADPT_CTRL, 0x10),
+};
+
+static const struct qcom_qmp_phy_init_tbl x1p42100_qmp_pcie_ln_shrd_tbl[] = {
+	QMP_PHY_INIT_CFG(QSERDES_V4_LN_SHRD_RXCLK_DIV2_CTRL, 0x01),
+	QMP_PHY_INIT_CFG(QSERDES_V4_LN_SHRD_DFE_DAC_ENABLE1, 0x88),
+	QMP_PHY_INIT_CFG(QSERDES_V4_LN_SHRD_TX_ADAPT_POST_THRESH1, 0x02),
+	QMP_PHY_INIT_CFG(QSERDES_V4_LN_SHRD_TX_ADAPT_POST_THRESH2, 0x0D),
+	QMP_PHY_INIT_CFG(QSERDES_V4_LN_SHRD_RX_MODE_RATE_0_1_B0, 0xD4),
+	QMP_PHY_INIT_CFG(QSERDES_V4_LN_SHRD_RX_MODE_RATE_0_1_B1, 0x12),
+	QMP_PHY_INIT_CFG(QSERDES_V4_LN_SHRD_RX_MODE_RATE_0_1_B2, 0xDB),
+	QMP_PHY_INIT_CFG(QSERDES_V4_LN_SHRD_RX_MODE_RATE_0_1_B3, 0x9A),
+	QMP_PHY_INIT_CFG(QSERDES_V4_LN_SHRD_RX_MODE_RATE_0_1_B4, 0x32),
+	QMP_PHY_INIT_CFG(QSERDES_V4_LN_SHRD_RX_MODE_RATE_0_1_B5, 0xB6),
+	QMP_PHY_INIT_CFG(QSERDES_V4_LN_SHRD_RX_MODE_RATE_0_1_B6, 0x64),
+	QMP_PHY_INIT_CFG(QSERDES_V4_LN_SHRD_RX_MARG_COARSE_THRESH1_RATE210, 0x1F),
+	QMP_PHY_INIT_CFG(QSERDES_V4_LN_SHRD_RX_MARG_COARSE_THRESH1_RATE3, 0x1F),
+	QMP_PHY_INIT_CFG(QSERDES_V4_LN_SHRD_RX_MARG_COARSE_THRESH2_RATE210, 0x1F),
+	QMP_PHY_INIT_CFG(QSERDES_V4_LN_SHRD_RX_MARG_COARSE_THRESH2_RATE3, 0x1F),
+	QMP_PHY_INIT_CFG(QSERDES_V4_LN_SHRD_RX_MARG_COARSE_THRESH3_RATE210, 0x1F),
+	QMP_PHY_INIT_CFG(QSERDES_V4_LN_SHRD_RX_MARG_COARSE_THRESH3_RATE3, 0x1F),
+	QMP_PHY_INIT_CFG(QSERDES_V4_LN_SHRD_RX_MARG_COARSE_THRESH4_RATE3, 0x1F),
+	QMP_PHY_INIT_CFG(QSERDES_V4_LN_SHRD_RX_MARG_COARSE_THRESH5_RATE3, 0x1F),
+	QMP_PHY_INIT_CFG(QSERDES_V4_LN_SHRD_RX_MARG_COARSE_THRESH6_RATE3, 0x1F),
+	QMP_PHY_INIT_CFG(QSERDES_V4_LN_SHRD_RX_SUMMER_CAL_SPD_MODE, 0x5B),
+};
+
+static const struct qcom_qmp_phy_init_tbl x1p42100_qmp_pcie_pcs_com_tbl[] = {
+	QMP_PHY_INIT_CFG(QPHY_PCIE4_PCS_COM_G3S2_PRE_GAIN, 0x2E),
+	QMP_PHY_INIT_CFG(QPHY_PCIE4_PCS_COM_RX_SIGDET_LVL, 0xAA),
+	QMP_PHY_INIT_CFG(QPHY_PCIE4_PCS_COM_EQ_CONFIG4, 0x00),
+	QMP_PHY_INIT_CFG(QPHY_PCIE4_PCS_COM_EQ_CONFIG5, 0x22),
+};
+
+static const struct qcom_qmp_phy_init_tbl x1p42100_qmp_pcie_pcs_pcie_tbl[] = {
+	QMP_PHY_INIT_CFG(QPHY_PCIE4_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1),
+	QMP_PHY_INIT_CFG(QPHY_PCIE4_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00),
+	QMP_PHY_INIT_CFG(QPHY_PCIE4_PCS_PCIE_EQ_CONFIG1, 0x16),
+	QMP_PHY_INIT_CFG(QPHY_PCIE4_PCS_PCIE_G4_EQ_CONFIG5, 0x02),
+	QMP_PHY_INIT_CFG(QPHY_PCIE4_PCS_PCIE_G4_PRE_GAIN, 0x2E),
+	QMP_PHY_INIT_CFG(QPHY_PCIE4_PCS_PCIE_RX_MARGINING_CONFIG1, 0x03),
+	QMP_PHY_INIT_CFG(QPHY_PCIE4_PCS_PCIE_RX_MARGINING_CONFIG3, 0x28),
+	QMP_PHY_INIT_CFG(QPHY_PCIE4_PCS_PCIE_RX_MARGINING_CONFIG5, 0x18),
+	QMP_PHY_INIT_CFG(QPHY_PCIE4_PCS_PCIE_G3_FOM_EQ_CONFIG5, 0x7A),
+	QMP_PHY_INIT_CFG(QPHY_PCIE4_PCS_PCIE_G4_FOM_EQ_CONFIG5, 0x8A),
+	QMP_PHY_INIT_CFG(QPHY_PCIE4_PCS_PCIE_G3_RXEQEVAL_TIME, 0x27),
+	QMP_PHY_INIT_CFG(QPHY_PCIE4_PCS_PCIE_G4_RXEQEVAL_TIME, 0x27),
+};
+
+static const struct qcom_qmp_phy_init_tbl x1p42100_qmp_gen4x4_pcie_com_tx_rx_tbl[] = {
+	QMP_PHY_INIT_CFG(QPHY_PCIE4_PCS_COM_PCS_TX_RX_CONFIG, 0x04),
+	QMP_PHY_INIT_CFG(QPHY_PCIE4_PCS_COM_PCS_TX_RX_CONFIG2, 0x02),
+};
+
+static const struct qcom_qmp_phy_init_tbl x1p42100_qmp_gen4x4_pcie_pcs_tx_rx_tbl[] = {
+	QMP_PHY_INIT_CFG(QPHY_PCIE4_PCS_PCIE_PCS_TX_RX_CONFIG, 0xC0),
+};
+
+static const struct qcom_qmp_phy_init_tbl x1p42100_qmp_gen4x4_pcie_power_misc_tbl[] = {
+	QMP_PHY_INIT_CFG(QPHY_PCIE4_PCS_PCIE_POWER_STATE_CONFIG2, 0x1D),
+};
+
+static const struct qcom_qmp_phy_init_tbl x1p42100_qmp_gen4x4_lane0_pcie_pcs_tbl[] = {
+	QMP_PHY_INIT_CFG(QPHY_PCIE4_PCS_LANE0_OUTSIG_MX_CTRL2, 0x00),
+};
+
+static const struct qcom_qmp_phy_init_tbl x1p42100_qmp_gen4x4_lane1_pcie_pcs_tbl[] = {
+	QMP_PHY_INIT_CFG(QPHY_PCIE4_PCS_LANE1_OUTSIG_MX_CTRL2, 0x00),
+	QMP_PHY_INIT_CFG(QPHY_PCIE4_PCS_LANE1_INSIG_SW_CTRL2, 0x00),
+	QMP_PHY_INIT_CFG(QPHY_PCIE4_PCS_LANE1_INSIG_MX_CTRL2, 0x00),
+};
+
+static pcie_cntlr_cfg_t pcie_host = {
+	.parf           = (void *)PCIE6A_PCIE_PARF,
+	.dbi_base       = (void *)PCIE6A_GEN1X4_PCIE_DBI,
+	.elbi           = (void *)PCIE6A_GEN1X4_PCIE_ELBI,
+	.atu_base       = (void *)PCIE6A_GEN1X4_DWC_PCIE_DM_IATU,
+	.cfg_base       = (void *)PCIE6A_GEN1X4_PCIE_DBI + PCIE_EP_CONF_OFFSET,
+	.pcie_bcr       = (void *)PCIE6A_BCR,
+	.qmp_phy_bcr    = (void *)GCC_PCIE_6A_PHY_BCR,
+	.lanes          = PCIE_1x4_NUM_LANES,
+	.cfg_size       = PCIE_EP_CONF_SIZE,
+	.perst          = GPIO(152),
+
+	/* Store the IO and MEM space settings for future use by the ATU */
+	.io.phys_start  = PCIE6A_GEN1X4_PCIE_DBI + PCIE_IO_SPACE_OFFSET,
+	.io.size        = PCIE_IO_SPACE_SIZE,
+	.mem.phys_start = PCIE6A_GEN1X4_PCIE_DBI + PCIE_MMIO_SPACE_OFFSET,
+	.mem.size       = PCIE6A_SPACE_END_ADDR,
+};
+
+static pcie_qmp_phy_cfg_t pcie6a_qmp_phy_1x4 = {
+	.porta = {
+		.qmp_phy_base      = (void *)PCIE_6A_AQMP_PHY,
+		.serdes            = (void *)PCIE6A_AQPHY_SERDES,
+		.tx0               = (void *)PCIE6A_AQPHY_TX0,
+		.rx0               = (void *)PCIE6A_AQPHY_RX0,
+		.pcs               = (void *)PCIE6A_AQPHY_PCS_COM,
+		.tx1               = (void *)PCIE6A_AQPHY_TX1,
+		.rx1               = (void *)PCIE6A_AQPHY_RX1,
+		.pcs_misc          = (void *)PCIE6A_AQPHY_PCS_PCIE,
+		.lane0_pcs         = (void *)PCIE6A_AQPHY_PCS_LANE0,
+		.lane1_pcs         = (void *)PCIE6A_AQPHY_PCS_LANE1,
+		.lane0_pcie_pcs    = (void *)PCIE6A_AQPHY_PCS_PCIE_LANE0,
+		.lane1_pcie_pcs    = (void *)PCIE6A_AQPHY_PCS_PCIE_LANE1,
+		.ln_shrd           = (void *)PCIE6A_AQPHY_LN_SHRD,
+	},
+	.portb = {
+		.qmp_phy_base      = (void *)PCIE_6A_BQMP_PHY,
+		.serdes            = (void *)PCIE6A_BQPHY_SERDES,
+		.tx0               = (void *)PCIE6A_BQPHY_TX0,
+		.rx0               = (void *)PCIE6A_BQPHY_RX0,
+		.pcs               = (void *)PCIE6A_BQPHY_PCS_COM,
+		.tx1               = (void *)PCIE6A_BQPHY_TX1,
+		.rx1               = (void *)PCIE6A_BQPHY_RX1,
+		.pcs_misc          = (void *)PCIE6A_BQPHY_PCS_PCIE,
+		.lane0_pcs         = (void *)PCIE6A_BQPHY_PCS_LANE0,
+		.lane1_pcs         = (void *)PCIE6A_BQPHY_PCS_LANE1,
+		.lane0_pcie_pcs    = (void *)PCIE6A_BQPHY_PCS_PCIE_LANE0,
+		.lane1_pcie_pcs    = (void *)PCIE6A_BQPHY_PCS_PCIE_LANE1,
+		.ln_shrd           = (void *)PCIE6A_BQPHY_LN_SHRD,
+	},
+	.serdes_tbl             = x1p42100_qmp_pcie_serdes_pll_tbl,
+	.serdes_tbl_num         = ARRAY_SIZE(x1p42100_qmp_pcie_serdes_pll_tbl),
+	.tx_tbl                 = x1p42100_qmp_pcie_tx_tbl,
+	.tx_tbl_num             = ARRAY_SIZE(x1p42100_qmp_pcie_tx_tbl),
+	.rx_tbl                 = x1p42100_qmp_pcie_rx_tbl,
+	.rx_tbl_num             = ARRAY_SIZE(x1p42100_qmp_pcie_rx_tbl),
+	.pcs_tbl                = x1p42100_qmp_pcie_pcs_com_tbl,
+	.pcs_tbl_num            = ARRAY_SIZE(x1p42100_qmp_pcie_pcs_com_tbl),
+	.pcs_misc_tbl           = x1p42100_qmp_pcie_pcs_pcie_tbl,
+	.pcs_misc_tbl_num       = ARRAY_SIZE(x1p42100_qmp_pcie_pcs_pcie_tbl),
+	.pcs_tbl_sec            = x1p42100_qmp_gen4x4_pcie_com_tx_rx_tbl,
+	.pcs_tbl_num_sec        = ARRAY_SIZE(x1p42100_qmp_gen4x4_pcie_com_tx_rx_tbl),
+	.pcs_misc_tbl_sec       = x1p42100_qmp_gen4x4_pcie_pcs_tx_rx_tbl,
+	.pcs_misc_tbl_num_sec   = ARRAY_SIZE(x1p42100_qmp_gen4x4_pcie_pcs_tx_rx_tbl),
+	.lane0_pcie_pcs_tbl     = x1p42100_qmp_gen4x4_lane0_pcie_pcs_tbl,
+	.lane0_pcie_pcs_tbl_num = ARRAY_SIZE(x1p42100_qmp_gen4x4_lane0_pcie_pcs_tbl),
+	.lane1_pcie_pcs_tbl     = x1p42100_qmp_gen4x4_lane1_pcie_pcs_tbl,
+	.lane1_pcie_pcs_tbl_num = ARRAY_SIZE(x1p42100_qmp_gen4x4_lane1_pcie_pcs_tbl),
+	.pcs_misc_tbl_thrd      = x1p42100_qmp_gen4x4_pcie_power_misc_tbl,
+	.pcs_misc_tbl_num_thrd  = ARRAY_SIZE(x1p42100_qmp_gen4x4_pcie_power_misc_tbl),
+	.ln_shrd_tbl            = x1p42100_qmp_pcie_ln_shrd_tbl,
+	.ln_shrd_tbl_num        = ARRAY_SIZE(x1p42100_qmp_pcie_ln_shrd_tbl),
+};
+
 /* Enable PIPE clock */
 int qcom_dw_pcie_enable_pipe_clock(void)
 {
@@ -57,10 +297,11 @@ int32_t qcom_dw_pcie_enable_clock(void)
 /* Turn on NVMe */
 void gcom_pcie_power_on_ep(void)
 {
-	/* placeholder */
+	gpio_output(NVME_REG_EN, 1);
 }
 
 void gcom_pcie_get_config(struct qcom_pcie_cntlr_t *host_cfg)
 {
-	/* placeholder */
+	host_cfg->cntlr_cfg = &pcie_host;
+	host_cfg->qmp_phy_cfg = &pcie6a_qmp_phy_1x4;
 }
diff --git a/src/soc/qualcomm/x1p42100/soc.c b/src/soc/qualcomm/x1p42100/soc.c
index c23aa89c69..f43d348684 100644
--- a/src/soc/qualcomm/x1p42100/soc.c
+++ b/src/soc/qualcomm/x1p42100/soc.c
@@ -1,17 +1,15 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
 #include <device/device.h>
-#include <soc/mmu.h>
-#include <soc/mmu_common.h>
 #include <soc/symbols_common.h>
-#include <soc/cpucp.h>
 #include <soc/pcie.h>
 
 static struct device_operations pci_domain_ops = {
-	.read_resources = noop_read_resources,
-	.set_resources = noop_set_resources,
+	.read_resources = &qcom_pci_domain_read_resources,
+	.set_resources = &pci_domain_set_resources,
+	.scan_bus = &pci_host_bridge_scan_bus,
+	.enable = &qcom_setup_pcie_host,
 };
-
 static void soc_read_resources(struct device *dev)
 {
 	/* placeholder */

From eee3ea0346bdf711ea776fc1c502c6620c87b5eb Mon Sep 17 00:00:00 2001
From: Hari L <haril@qualcomm.corp-partner.google.com>
Date: Sun, 20 Jul 2025 20:16:48 +0530
Subject: [PATCH 1698/3886] mb/google/bluey: Enable PCIE Feature for bluey

Enable PCIE init for bluey board and update device pci node.
Remove unused pci 4.0 node(WLAN).

TEST= Verified that link is enumerated and NVMe is accessible via PCIE.

Change-Id: I7ad4a9409ff0465b45b8bb1f3e005bf9f83f2c42
Signed-off-by: Hari L <haril@qualcomm.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88535
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/google/bluey/devicetree.cb | 3 +--
 src/mainboard/google/bluey/mainboard.c   | 3 +--
 2 files changed, 2 insertions(+), 4 deletions(-)

diff --git a/src/mainboard/google/bluey/devicetree.cb b/src/mainboard/google/bluey/devicetree.cb
index 69d0533e0e..a0e753792f 100644
--- a/src/mainboard/google/bluey/devicetree.cb
+++ b/src/mainboard/google/bluey/devicetree.cb
@@ -3,7 +3,6 @@
 chip soc/qualcomm/x1p42100
 	device cpu_cluster 0 on end
 	device domain 0 on
-		device pci 04.0 on end # WLAN
-		device pci 06.0 on end # SSD
+		device pci 00.0 on end # Root Bridge
 	end
 end
diff --git a/src/mainboard/google/bluey/mainboard.c b/src/mainboard/google/bluey/mainboard.c
index db44fe7972..9950f88545 100644
--- a/src/mainboard/google/bluey/mainboard.c
+++ b/src/mainboard/google/bluey/mainboard.c
@@ -11,8 +11,7 @@
 
 bool mainboard_needs_pcie_init(void)
 {
-	/* Placeholder */
-	return false;
+	return true;
 }
 
 static void display_startup(void)

From db10b681b4f78882f5b8c724078f5669ed950e74 Mon Sep 17 00:00:00 2001
From: Sasirekaa Madhesu <smadhesu@qualcomm.corp-partner.google.com>
Date: Wed, 23 Jul 2025 19:13:21 +0530
Subject: [PATCH 1699/3886] soc/qc/x1p42100: Load and populate QcLib interface
 table entries

This patch adds support to pack aop_meta into CBFS and load QcLib DTB,
SHRM metadata, and AOP metadata. It also populates the QcLib interface
table with these information for firmware authentication and execution.

TEST=Verify presence of AOP metadata file in the CBFS and QcLib
interface table content.

Change-Id: I1a74d9ffbfc10023b0e5610d54218909b18efa01
Signed-off-by: Sasirekaa Madhesu <smadhesu@qualcomm.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88486
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 .../common/include/soc/qclib_common.h         |   7 +
 .../common/include/soc/symbols_common.h       |   4 +-
 src/soc/qualcomm/common/qclib.c               | 129 ++++++++++++------
 src/soc/qualcomm/x1p42100/Makefile.mk         |  18 ++-
 src/soc/qualcomm/x1p42100/include/soc/clock.h |   6 +
 src/soc/qualcomm/x1p42100/qclib.c             |  33 +++++
 src/soc/qualcomm/x1p42100/shrm_load_reset.c   |   8 --
 7 files changed, 157 insertions(+), 48 deletions(-)
 create mode 100644 src/soc/qualcomm/x1p42100/qclib.c
 delete mode 100644 src/soc/qualcomm/x1p42100/shrm_load_reset.c

diff --git a/src/soc/qualcomm/common/include/soc/qclib_common.h b/src/soc/qualcomm/common/include/soc/qclib_common.h
index 850202a490..fc2ed93399 100644
--- a/src/soc/qualcomm/common/include/soc/qclib_common.h
+++ b/src/soc/qualcomm/common/include/soc/qclib_common.h
@@ -23,6 +23,9 @@
 #define QCLIB_TE_LIMITS_CFG_DATA   "limits_cfg_data"
 #define QCLIB_TE_QCSDI             "qcsdi"
 #define QCLIB_TE_MEM_CHIP_INFO     "mem_chip_info"
+#define QCLIB_TE_DTB_SETTINGS      "dtb"
+#define QCLIB_TE_SHRM_META_SETTINGS	"shrm_metadata"
+#define QCLIB_TE_AOP_META_SETTINGS      "aop_metadata"
 
 /* BA_BMASK_VALUES (blob_attributes bit mask values) */
 #define QCLIB_BA_SAVE_TO_STORAGE 0x00000001
@@ -32,6 +35,9 @@ enum qclib_cbfs_file {
 	QCLIB_CBFS_QCSDI,
 	QCLIB_CBFS_QCLIB,
 	QCLIB_CBFS_DCB,
+	QCLIB_CBFS_DTB,
+	QCLIB_CBFS_SHRM_META,
+	QCLIB_CBFS_AOP_META,
 	QCLIB_CBFS_MAX
 };
 
@@ -68,6 +74,7 @@ extern struct qclib_cb_if_table qclib_cb_if_table;
 void qclib_add_if_table_entry(const char *name, void *base,
 			      uint32_t size, uint32_t attrs);
 void qclib_load_and_run(void);
+void qclib_rerun(void);
 int  qclib_soc_override(struct qclib_cb_if_table *table);
 
 const char *qclib_file_default(enum qclib_cbfs_file file);
diff --git a/src/soc/qualcomm/common/include/soc/symbols_common.h b/src/soc/qualcomm/common/include/soc/symbols_common.h
index 75602665ce..461ffb7d0e 100644
--- a/src/soc/qualcomm/common/include/soc/symbols_common.h
+++ b/src/soc/qualcomm/common/include/soc/symbols_common.h
@@ -13,7 +13,9 @@ DECLARE_REGION(bsram)
 DECLARE_REGION(dram_aop)
 DECLARE_REGION(dram_soc)
 DECLARE_REGION(dcb)
-DECLARE_REGION(pmic)
+DECLARE_REGION(dtb)
+DECLARE_REGION(qc_blob_meta)
+DECLARE_OPTIONAL_REGION(pmic)
 DECLARE_REGION(limits_cfg)
 DECLARE_REGION(aop)
 DECLARE_REGION(modem_id)
diff --git a/src/soc/qualcomm/common/qclib.c b/src/soc/qualcomm/common/qclib.c
index deb047d45a..ef6f90eefc 100644
--- a/src/soc/qualcomm/common/qclib.c
+++ b/src/soc/qualcomm/common/qclib.c
@@ -56,14 +56,20 @@ static void add_mem_chip_info(int unused)
 
 CBMEM_CREATION_HOOK(add_mem_chip_info);
 
-struct qclib_cb_if_table qclib_cb_if_table = {
-	.magic = QCLIB_MAGIC_NUMBER,
-	.version = QCLIB_INTERFACE_VERSION,
-	.num_entries = 0,
-	.max_entries = QCLIB_MAX_NUMBER_OF_ENTRIES,
-	.global_attributes = 0,
-	.reserved = 0,
-};
+struct qclib_cb_if_table qclib_cb_if_table;
+
+static inline void init_qclib_cb_if_table(struct qclib_cb_if_table *tbl)
+{
+	if (!tbl)
+		return;
+
+	memcpy(tbl->magic, QCLIB_MAGIC_NUMBER, sizeof(tbl->magic));
+	tbl->version = QCLIB_INTERFACE_VERSION;
+	tbl->num_entries = 0;
+	tbl->max_entries = QCLIB_MAX_NUMBER_OF_ENTRIES;
+	tbl->global_attributes = 0;
+	tbl->reserved = 0;
+}
 
 const char *qclib_file_default(enum qclib_cbfs_file file)
 {
@@ -76,6 +82,12 @@ const char *qclib_file_default(enum qclib_cbfs_file file)
 		return CONFIG_CBFS_PREFIX "/qclib";
 	case QCLIB_CBFS_DCB:
 		return CONFIG_CBFS_PREFIX "/dcb";
+	case QCLIB_CBFS_DTB:
+		return CONFIG_CBFS_PREFIX "/dtb";
+	case QCLIB_CBFS_SHRM_META:
+		return CONFIG_CBFS_PREFIX "/shrm_meta";
+	case QCLIB_CBFS_AOP_META:
+		return CONFIG_CBFS_PREFIX "/aop_meta";
 	default:
 		die("unknown QcLib file %d", file);
 	}
@@ -167,15 +179,44 @@ static void dump_te_table(void)
 
 __weak int qclib_soc_override(struct qclib_cb_if_table *table) { return 0; }
 
+struct prog qclib; /* This will be re-used by qclib_rerun() */
+
+static void qclib_prepare_and_run(void)
+{
+	struct mmu_context pre_qclib_mmu_context;
+
+	printk(BIOS_DEBUG, "Global Attributes[%#x]..Table Entries Count[%d]\n",
+		qclib_cb_if_table.global_attributes,
+		qclib_cb_if_table.num_entries);
+	printk(BIOS_DEBUG, "Jumping to QCLib code at %p(%p)\n",
+		prog_entry(&qclib), prog_entry_arg(&qclib));
+
+	/* back-up mmu context before disabling mmu and executing qclib */
+	mmu_save_context(&pre_qclib_mmu_context);
+	/* disable mmu before jumping to qclib. mmu_disable also
+	   flushes and invalidates caches before disabling mmu. */
+	mmu_disable();
+
+	prog_run(&qclib);
+
+	/* Before returning, QCLib flushes cache and disables mmu.
+	   Explicitly disable mmu (flush, invalidate and disable mmu)
+	   before re-enabling mmu with backed-up mmu context */
+	mmu_disable();
+	mmu_restore_context(&pre_qclib_mmu_context);
+	mmu_enable();
+}
+
 void qclib_load_and_run(void)
 {
 	int i;
 	ssize_t data_size;
-	struct mmu_context pre_qclib_mmu_context;
 
 	/* zero ddr_information SRAM region, needs new data each boot */
 	memset(ddr_region, 0, sizeof(struct region));
 
+	init_qclib_cb_if_table(&qclib_cb_if_table);
+
 	/* output area, QCLib copies console log buffer out */
 	if (CONFIG(CONSOLE_CBMEM))
 		qclib_add_if_table_entry(QCLIB_TE_QCLIB_LOG_BUFFER,
@@ -198,14 +239,16 @@ void qclib_load_and_run(void)
 	/* Address and size of this entry will be filled in by QcLib. */
 	qclib_add_if_table_entry(QCLIB_TE_MEM_CHIP_INFO, NULL, 0, 0);
 
-	/* Attempt to load PMICCFG Blob */
-	data_size = cbfs_load(qclib_file(QCLIB_CBFS_PMICCFG),
-			_pmic, REGION_SIZE(pmic));
-	if (!data_size) {
-		printk(BIOS_ERR, "[%s] /pmiccfg failed\n", __func__);
-		goto fail;
+	if (_pmic) {
+		/* Attempt to load PMICCFG Blob */
+		data_size = cbfs_load(qclib_file(QCLIB_CBFS_PMICCFG),
+				_pmic, REGION_SIZE(pmic));
+		if (!data_size) {
+			printk(BIOS_ERR, "[%s] /pmiccfg failed\n", __func__);
+			goto fail;
+		}
+		qclib_add_if_table_entry(QCLIB_TE_PMIC_SETTINGS, _pmic, data_size, 0);
 	}
-	qclib_add_if_table_entry(QCLIB_TE_PMIC_SETTINGS, _pmic, data_size, 0);
 
 	/* Attempt to load DCB Blob */
 	data_size = cbfs_load(qclib_file(QCLIB_CBFS_DCB),
@@ -245,7 +288,7 @@ void qclib_load_and_run(void)
 	dump_te_table();
 
 	/* Attempt to load QCLib elf */
-	struct prog qclib =
+	qclib = (struct prog)
 		PROG_INIT(PROG_REFCODE, qclib_file(QCLIB_CBFS_QCLIB));
 
 	if (cbfs_prog_stage_load(&qclib))
@@ -253,27 +296,9 @@ void qclib_load_and_run(void)
 
 	prog_set_entry(&qclib, prog_entry(&qclib), &qclib_cb_if_table);
 
-	printk(BIOS_DEBUG, "\n\n\nQCLib is about to Initialize DDR\n");
-	printk(BIOS_DEBUG, "Global Attributes[%#x]..Table Entries Count[%d]\n",
-		qclib_cb_if_table.global_attributes,
-		qclib_cb_if_table.num_entries);
-	printk(BIOS_DEBUG, "Jumping to QCLib code at %p(%p)\n",
-		prog_entry(&qclib), prog_entry_arg(&qclib));
-
-	/* back-up mmu context before disabling mmu and executing qclib */
-	mmu_save_context(&pre_qclib_mmu_context);
-	/* disable mmu before jumping to qclib. mmu_disable also
-	   flushes and invalidates caches before disabling mmu. */
-	mmu_disable();
-
-	prog_run(&qclib);
-
-	/* Before returning, QCLib flushes cache and disables mmu.
-	   Explicitly disable mmu (flush, invalidate and disable mmu)
-	   before re-enabling mmu with backed-up mmu context */
-	mmu_disable();
-	mmu_restore_context(&pre_qclib_mmu_context);
-	mmu_enable();
+	/* Set up the system and jump into QcLib */
+	printk(BIOS_DEBUG, "\n\n\nEnter QcLib to Initialize DDR and bring up SHRM\n");
+	qclib_prepare_and_run();
 
 	if (qclib_cb_if_table.global_attributes & QCLIB_GA_FORCE_COLD_REBOOT) {
 		printk(BIOS_NOTICE, "QcLib requested cold reboot\n");
@@ -297,3 +322,31 @@ void qclib_load_and_run(void)
 fail:
 	die("Couldn't run QCLib.\n");
 }
+
+void qclib_rerun(void)
+{
+	ssize_t data_size;
+
+	assert(prog_type(&qclib) == PROG_REFCODE)
+
+	init_qclib_cb_if_table(&qclib_cb_if_table);
+
+	/* Attempt to load aop_meta Blob (reuse the qc_blob_meta region). */
+	data_size = cbfs_load(qclib_file(QCLIB_CBFS_AOP_META),
+			_qc_blob_meta, REGION_SIZE(qc_blob_meta));
+	if (!data_size) {
+		printk(BIOS_ERR, "[%s] /aop_meta failed\n", __func__);
+		goto fail;
+	}
+
+	qclib_add_if_table_entry(QCLIB_TE_AOP_META_SETTINGS, _qc_blob_meta, data_size, 0);
+
+	/* Set up the system and jump into QcLib */
+	printk(BIOS_DEBUG, "\n\n\nRe-enter QCLib to bring up AOP\n");
+	qclib_prepare_and_run();
+
+	return;
+
+fail:
+	die("Couldn't reload QCLib.\n");
+}
diff --git a/src/soc/qualcomm/x1p42100/Makefile.mk b/src/soc/qualcomm/x1p42100/Makefile.mk
index 719f53988d..cb249f494d 100644
--- a/src/soc/qualcomm/x1p42100/Makefile.mk
+++ b/src/soc/qualcomm/x1p42100/Makefile.mk
@@ -27,12 +27,14 @@ verstage-$(CONFIG_DRIVERS_UART) += ../common/qupv3_uart.c
 
 ################################################################################
 romstage-y += cbmem.c
-romstage-y += shrm_load_reset.c
+romstage-y += ../common/shrm_load_reset.c
 romstage-y += cpucp_load_reset.c
 romstage-y += ../common/qclib.c
 romstage-y += ../common/mmu.c
 romstage-y += ../common/watchdog.c
+romstage-y += qclib.c
 romstage-y += mmu.c
+romstage-y += ../common/aop_load_reset.c
 romstage-$(CONFIG_DRIVERS_UART) += ../common/qupv3_uart.c
 
 ################################################################################
@@ -143,6 +145,20 @@ $(AOP_CBFS)-type := payload
 $(AOP_CBFS)-compression := $(CBFS_COMPRESS_FLAG)
 cbfs-files-y += $(AOP_CBFS)
 
+################################################################################
+# Rule to create aop_meta from aop.mbn
+# This rule depends on aop.mbn built and the extractor script existing.
+$(obj)/mainboard/$(MAINBOARDDIR)/aop_meta: $(X1P42100_BLOB)/aop/aop.mbn util/qualcomm/elf_segment_extractor.py
+	@echo "Extracting ELF headers and hash table segment from $< to $@"
+	@util/qualcomm/elf_segment_extractor.py --eh --pht --hashtable $< $@
+
+AOP_META_FILE := $(obj)/mainboard/$(MAINBOARDDIR)/aop_meta
+AOP_META_CBFS := $(CONFIG_CBFS_PREFIX)/aop_meta
+$(AOP_META_CBFS)-file := $(AOP_META_FILE)
+$(AOP_META_CBFS)-type := raw
+$(AOP_META_CBFS)-compression := $(CBFS_COMPRESS_FLAG)
+cbfs-files-y += $(AOP_META_CBFS)
+
 ################################################################################
 CPUCP_FILE := $(X1P42100_BLOB)/cpucp/cpucp.elf
 CPUCP_CBFS := $(CONFIG_CBFS_PREFIX)/cpucp
diff --git a/src/soc/qualcomm/x1p42100/include/soc/clock.h b/src/soc/qualcomm/x1p42100/include/soc/clock.h
index 06b573650d..e9b827b0fe 100644
--- a/src/soc/qualcomm/x1p42100/include/soc/clock.h
+++ b/src/soc/qualcomm/x1p42100/include/soc/clock.h
@@ -395,4 +395,10 @@ enum cb_err clock_configure_mux(enum clk_pcie clk_type, u32 src_type);
 static struct aoss *const aoss = (void *)AOSS_CC_BASE;
 static struct x1p42100_gcc *const gcc = (void *)GCC_BASE;
 static struct x1p42100_ncc0_clock *const apss_ncc0 = (void *)NCC0_BASE;
+
+/* Does nothing */
+#define clock_reset_aop() do {} while (0)
+/* Does nothing */
+#define clock_reset_shrm() do {} while (0)
+
 #endif	// __SOC_QUALCOMM_X1P42100_CLOCK_H__
diff --git a/src/soc/qualcomm/x1p42100/qclib.c b/src/soc/qualcomm/x1p42100/qclib.c
new file mode 100644
index 0000000000..961f822a4f
--- /dev/null
+++ b/src/soc/qualcomm/x1p42100/qclib.c
@@ -0,0 +1,33 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <assert.h>
+#include <arch/mmu.h>
+#include <cbfs.h>
+#include <soc/qclib_common.h>
+#include <device/mmio.h>
+#include <soc/symbols_common.h>
+
+int qclib_soc_override(struct qclib_cb_if_table *table)
+{
+	ssize_t data_size;
+
+	/* Attempt to load DTB Blob */
+	data_size = cbfs_load(qclib_file(QCLIB_CBFS_DTB), _dtb, REGION_SIZE(dtb));
+	if (!data_size) {
+		printk(BIOS_ERR, "[%s] /dtb failed\n", __func__);
+		return -1;
+	}
+	qclib_add_if_table_entry(QCLIB_TE_DTB_SETTINGS, _dtb, data_size, 0);
+
+	/* Attempt to load shrm_meta Blob */
+	data_size = cbfs_load(qclib_file(QCLIB_CBFS_SHRM_META),
+			_qc_blob_meta, REGION_SIZE(qc_blob_meta));
+	if (!data_size) {
+		printk(BIOS_ERR, "[%s] /shrm_meta failed\n", __func__);
+		return -1;
+	}
+
+	qclib_add_if_table_entry(QCLIB_TE_SHRM_META_SETTINGS, _qc_blob_meta, data_size, 0);
+
+	return 0;
+}
diff --git a/src/soc/qualcomm/x1p42100/shrm_load_reset.c b/src/soc/qualcomm/x1p42100/shrm_load_reset.c
deleted file mode 100644
index 6bd1b1d530..0000000000
--- a/src/soc/qualcomm/x1p42100/shrm_load_reset.c
+++ /dev/null
@@ -1,8 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <soc/shrm.h>
-
-void shrm_fw_load_reset(void)
-{
-	/* Placeholder */
-}

From d79febf356725eff94c850f04eb055cf9d1656d9 Mon Sep 17 00:00:00 2001
From: Sasirekaa Madhesu <smadhesu@qualcomm.corp-partner.google.com>
Date: Fri, 18 Jul 2025 15:54:21 +0530
Subject: [PATCH 1700/3886] soc/qc/x1p42100: Enable QcLib, SHRM and AOP
 firmware load

This patch enables QcLib execution for DDR and PMIC initialization.
SHRM and AOP firmware metadata are passed from coreboot to QcLib via
the interface table. On first entry, QcLib authenticates SHRM metadata
through TME and brings SHRM out of reset. Upon re-entry, QcLib forwards
AOP metadata to TME for authentication and brings AOP out of reset.

TEST=Verified QcLib boot (DDR Init, SHRM/AOP authentication & out of
reset flow) on google/bluey.

Change-Id: I4b726d5066ca807bf9d4df70f275e5dd991520cc
Signed-off-by: Sasirekaa Madhesu <smadhesu@qualcomm.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88487
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
---
 src/mainboard/google/bluey/romstage.c | 16 ++++++++++++++--
 1 file changed, 14 insertions(+), 2 deletions(-)

diff --git a/src/mainboard/google/bluey/romstage.c b/src/mainboard/google/bluey/romstage.c
index f6932fefdc..b15f6e694f 100644
--- a/src/mainboard/google/bluey/romstage.c
+++ b/src/mainboard/google/bluey/romstage.c
@@ -1,12 +1,24 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
 #include <arch/stages.h>
-#include <gpio.h>
 #include "board.h"
+#include <gpio.h>
+#include <soc/aop_common.h>
+#include <soc/qclib_common.h>
+#include <soc/shrm.h>
 
 void platform_romstage_main(void)
 {
-	/* Placeholder */
+	void (*const fw_init_sequence[])(void) = {
+		shrm_fw_load_reset,
+		qclib_load_and_run,
+		aop_fw_load_reset,
+		qclib_rerun,
+	};
+
+	/* Executing essential firmware loading */
+	for (size_t i = 0; i < ARRAY_SIZE(fw_init_sequence); i++)
+		fw_init_sequence[i]();
 
 	/*
 	 * Enable this power rail now for FPMCU stability prior to

From 190c27d08b252883bc2476bcb1588e04446d6e8a Mon Sep 17 00:00:00 2001
From: Daniel Peng <Daniel_Peng@pegatron.corp-partner.google.com>
Date: Wed, 16 Jul 2025 18:11:14 +0800
Subject: [PATCH 1701/3886] mb/google/brya/var/marasov: Add SPD ID for
 K3KL6L60GM-MGCT and K3KL8L80EM-MGCU

Add the 2 new Samsung memory support.

DRAM Part Name   Vendor   Model    ID to assign
K3KL6L60GM-MGCT  Samsung  LPDDR5X  4 (0100)
K3KL8L80EM-MGCU  Samsung  LPDDR5X  5 (0101)

BUG=b:426427376, b:432169883
BRANCH=firmware-brya-14505.B
TEST=emerge-brya coreboot chromeos-bootimage

Change-Id: Ib707e2e482dc90bc02d73bd0fcda62630bacf1b5
Signed-off-by: Daniel Peng <Daniel_Peng@pegatron.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88449
Reviewed-by: Daniel Peng <daniel_peng@pegatron.corp-partner.google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
---
 src/mainboard/google/brya/variants/marasov/memory/Makefile.mk   | 2 ++
 .../google/brya/variants/marasov/memory/dram_id.generated.txt   | 2 ++
 .../google/brya/variants/marasov/memory/mem_parts_used.txt      | 2 ++
 3 files changed, 6 insertions(+)

diff --git a/src/mainboard/google/brya/variants/marasov/memory/Makefile.mk b/src/mainboard/google/brya/variants/marasov/memory/Makefile.mk
index ecf9d34e52..659b165949 100644
--- a/src/mainboard/google/brya/variants/marasov/memory/Makefile.mk
+++ b/src/mainboard/google/brya/variants/marasov/memory/Makefile.mk
@@ -8,3 +8,5 @@ SPD_SOURCES += spd/lp5/set-0/spd-1.hex      # ID = 0(0b0000)  Parts = MT62F512M3
 SPD_SOURCES += spd/lp5/set-0/spd-1.hex      # ID = 1(0b0001)  Parts = H9JCNNNBK3MLYR-N6E
 SPD_SOURCES += spd/lp5/set-0/spd-2.hex      # ID = 2(0b0010)  Parts = MT62F1G32D4DR-031 WT:B
 SPD_SOURCES += spd/lp5/set-0/spd-2.hex      # ID = 3(0b0011)  Parts = H9JCNNNCP3MLYR-N6E
+SPD_SOURCES += spd/lp5/set-0/spd-9.hex      # ID = 4(0b0100)  Parts = K3KL6L60GM-MGCT
+SPD_SOURCES += spd/lp5/set-0/spd-11.hex      # ID = 5(0b0101)  Parts = K3KL8L80EM-MGCU
diff --git a/src/mainboard/google/brya/variants/marasov/memory/dram_id.generated.txt b/src/mainboard/google/brya/variants/marasov/memory/dram_id.generated.txt
index 82e3b33a4e..27c87ea35c 100644
--- a/src/mainboard/google/brya/variants/marasov/memory/dram_id.generated.txt
+++ b/src/mainboard/google/brya/variants/marasov/memory/dram_id.generated.txt
@@ -8,3 +8,5 @@ MT62F512M32D2DR-031 WT:B	0 (0000)
 H9JCNNNBK3MLYR-N6E		1 (0001)
 MT62F1G32D4DR-031 WT:B		2 (0010)
 H9JCNNNCP3MLYR-N6E		3 (0011)
+K3KL6L60GM-MGCT			4 (0100)
+K3KL8L80EM-MGCU			5 (0101)
diff --git a/src/mainboard/google/brya/variants/marasov/memory/mem_parts_used.txt b/src/mainboard/google/brya/variants/marasov/memory/mem_parts_used.txt
index b00f3f49e7..9a3eead884 100644
--- a/src/mainboard/google/brya/variants/marasov/memory/mem_parts_used.txt
+++ b/src/mainboard/google/brya/variants/marasov/memory/mem_parts_used.txt
@@ -13,3 +13,5 @@ MT62F512M32D2DR-031 WT:B
 H9JCNNNBK3MLYR-N6E
 MT62F1G32D4DR-031 WT:B
 H9JCNNNCP3MLYR-N6E
+K3KL6L60GM-MGCT
+K3KL8L80EM-MGCU

From d4b735f9f18c77f74da2e2a601c36569c1a0e302 Mon Sep 17 00:00:00 2001
From: Avi Uday <aviuday@google.com>
Date: Fri, 25 Jul 2025 14:23:49 +0530
Subject: [PATCH 1702/3886] mb/google/ocelot: Turn off unused I2C ports

The I2C2 and I2C3 ports are unused. This patch removes them from overridetree.cb as they are already turned off in chipset_wcl.cb.

BUG=b:434127691

Change-Id: I8c00f7c96915a1a11b848af5ea128900fb5a16db
Signed-off-by: Avi Uday <aviuday@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88562
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/google/ocelot/variants/ocelot/overridetree.cb | 5 -----
 1 file changed, 5 deletions(-)

diff --git a/src/mainboard/google/ocelot/variants/ocelot/overridetree.cb b/src/mainboard/google/ocelot/variants/ocelot/overridetree.cb
index 24e697e972..d20e0297ea 100644
--- a/src/mainboard/google/ocelot/variants/ocelot/overridetree.cb
+++ b/src/mainboard/google/ocelot/variants/ocelot/overridetree.cb
@@ -531,11 +531,6 @@ chip soc/intel/pantherlake
 				device i2c 50 on end
 			end
 		end
-		device ref i2c2 on end
-		device ref i2c3 on
-		end # I2C3
-		device ref i2c4 off
-		end # I2C4
 		device ref i2c5 on
 			chip drivers/i2c/hid
 				register "generic.hid" = ""HFW68H""

From f34bc61ca73ced73b72b1f99f3553a9d20df5732 Mon Sep 17 00:00:00 2001
From: Luca Lai <luca.lai@lcfc.corp-partner.google.com>
Date: Thu, 17 Jul 2025 09:51:44 +0800
Subject: [PATCH 1703/3886] mb/google/trulo/var/pujjolo: Correct the Goodix
 touchpad description

Fix the ACPI HID and description for Goodix touchpad.

BUG=b:395763555
BRANCH=none
TEST=Build and boot to OS and check the touchpad name in evtest.

Change-Id: I44b75841034a2004c62a577e60c630cc0e430fc8
Signed-off-by: Luca Lai <luca.lai@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88461
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/google/brya/variants/pujjolo/overridetree.cb | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/mainboard/google/brya/variants/pujjolo/overridetree.cb b/src/mainboard/google/brya/variants/pujjolo/overridetree.cb
index e79d5988e7..30a8af33be 100644
--- a/src/mainboard/google/brya/variants/pujjolo/overridetree.cb
+++ b/src/mainboard/google/brya/variants/pujjolo/overridetree.cb
@@ -432,9 +432,9 @@ chip soc/intel/alderlake
 				device i2c 15 on end
 			end
 			chip drivers/i2c/hid
-				register "generic.hid" = ""SYNA0000""
+				register "generic.hid" = ""GXTP5100""
 				register "generic.cid" = ""ACPI0C50""
-				register "generic.desc" = ""Synaptics Touchpad""
+				register "generic.desc" = ""Goodix Touchpad""
 				register "generic.irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_F14_IRQ)"
 				register "generic.wake" = "GPE0_DW2_14"
 				register "generic.detect" = "1"

From 0a4bc796859aab789658d8e59e0fcf20709756ca Mon Sep 17 00:00:00 2001
From: Eren Peng <peng.eren@inventec.corp-partner.google.com>
Date: Fri, 25 Jul 2025 09:17:54 +0800
Subject: [PATCH 1704/3886] mb/google/trulo/var/kaladin: Update USB2 driving
 settings

Update USB2 driving for all USB2 ports

BUG=b:419548309
TEST=Pass USB2 eye diagram test on kaladin

Change-Id: I947ec78de29e20f72122c1b84df4ee99e2655208
Signed-off-by: Eren Peng <peng.eren@inventec.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88556
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
---
 .../brya/variants/kaladin/overridetree.cb     | 57 +++++++++++++++++--
 1 file changed, 51 insertions(+), 6 deletions(-)

diff --git a/src/mainboard/google/brya/variants/kaladin/overridetree.cb b/src/mainboard/google/brya/variants/kaladin/overridetree.cb
index bb70312c95..6d36246028 100644
--- a/src/mainboard/google/brya/variants/kaladin/overridetree.cb
+++ b/src/mainboard/google/brya/variants/kaladin/overridetree.cb
@@ -37,12 +37,57 @@ chip soc/intel/alderlake
 	# eMMC HS400
 	register "emmc_enable_hs400_mode" = "true"
 
-	register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC_SKIP)"	# Type-C MB (7.5 inch)
-	register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC_SKIP)"	# Type-C DB (7.1 inch)
-	register "usb2_ports[2]" = "USB2_PORT_MID(OC1)"		# Type-A MB (6.4 inch)
-	register "usb2_ports[5]" = "USB2_PORT_SHORT(OC_SKIP)"	# UFC (3.7 inch)
-	register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)"	# Bluetooth port for PCIe WLAN (2.5 inch)
-	register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)"	# Bluetooth port for CNVi WLAN
+	register "usb2_ports[0]" = "{
+		.enable = 1,
+		.ocpin = OC_SKIP,
+		.tx_bias = USB2_BIAS_0MV,
+		.tx_emp_enable = USB2_PRE_EMP_ON,
+		.pre_emp_bias = USB2_BIAS_39P35MV,
+		.pre_emp_bit = USB2_HALF_BIT_PRE_EMP,
+		.type_c = 1,
+	}"# Type-C0
+	register "usb2_ports[1]" = "{
+		.enable = 1,
+		.ocpin = OC_SKIP,
+		.tx_bias = USB2_BIAS_0MV,
+		.tx_emp_enable = USB2_PRE_EMP_ON,
+		.pre_emp_bias = USB2_BIAS_39P35MV,
+		.pre_emp_bit = USB2_HALF_BIT_PRE_EMP,
+		.type_c = 1,
+	}"# Type-C1
+	register "usb2_ports[2]" = "{
+		.enable = 1,
+		.ocpin = OC_SKIP,
+		.tx_bias = USB2_BIAS_0MV,
+		.tx_emp_enable = USB2_DE_EMP_ON_PRE_EMP_ON,
+		.pre_emp_bias = USB2_BIAS_39P35MV,
+		.pre_emp_bit = USB2_FULL_BIT_PRE_EMP,
+	}"# Type-A
+	register "usb2_ports[5]" = "{
+		.enable = 1,
+		.ocpin = OC_SKIP,
+		.tx_bias = USB2_BIAS_0MV,
+		.tx_emp_enable = USB2_DE_EMP_ON_PRE_EMP_ON,
+		.pre_emp_bias = USB2_BIAS_39P35MV,
+		.pre_emp_bit = USB2_FULL_BIT_PRE_EMP,
+	}"#UFC
+	register "usb2_ports[7]" = "{
+		.enable = 1,
+		.ocpin = OC_SKIP,
+		.tx_bias = USB2_BIAS_0MV,
+		.tx_emp_enable = USB2_DE_EMP_ON_PRE_EMP_ON,
+		.pre_emp_bias = USB2_BIAS_28P15MV,
+		.pre_emp_bit = USB2_FULL_BIT_PRE_EMP,
+	}"# Bluetooth port for PCIe WLAN
+	register "usb2_ports[9]" = "{
+		.enable = 1,
+		.ocpin = OC_SKIP,
+		.tx_bias = USB2_BIAS_0MV,
+		.tx_emp_enable = USB2_DE_EMP_ON_PRE_EMP_ON,
+		.pre_emp_bias = USB2_BIAS_28P15MV,
+		.pre_emp_bit = USB2_FULL_BIT_PRE_EMP,
+	}"# Bluetooth port for CNVi WLAN
+
 
 	register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC1)"	# USB3 Type-A port A0(MLB)
 

From ae942a70b89a5523816c4b0f73fcd31ca301dbd8 Mon Sep 17 00:00:00 2001
From: Eren Peng <peng.eren@inventec.corp-partner.google.com>
Date: Fri, 25 Jul 2025 09:45:52 +0800
Subject: [PATCH 1705/3886] mb/google/trulo/var/kaladin: Update GPIOs table

Update GPIO config:
 - GPP_A16 -> NC
 - GPP_D0 -> NC
 - GPP_E9 -> NC
 - GPP_E13 -> MEM_STRAP_3
 - GPP_E17 -> NC
 - GPP_H17 -> NC

BUG=b:434005755
TEST=Flash and boot to OS on kaladin

Change-Id: I201e2bfa9a9da048b09552c3e3bfd976185a56a7
Signed-off-by: Eren Peng <peng.eren@inventec.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88559
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
---
 .../google/brya/variants/kaladin/gpio.c       | 22 +++++++++----------
 1 file changed, 11 insertions(+), 11 deletions(-)

diff --git a/src/mainboard/google/brya/variants/kaladin/gpio.c b/src/mainboard/google/brya/variants/kaladin/gpio.c
index 0e0518dff5..6f433bcd73 100644
--- a/src/mainboard/google/brya/variants/kaladin/gpio.c
+++ b/src/mainboard/google/brya/variants/kaladin/gpio.c
@@ -34,8 +34,8 @@ static const struct pad_config gpio_table[] = {
 	PAD_CFG_NF(GPP_A14, NONE, DEEP, NF1),
 	/* A15 : NC */
 	PAD_NC(GPP_A15, NONE),
-	/* A16 : USB_OC3# */
-	PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1),
+	/* A16 : USB_OC3# ==> NC */
+	PAD_NC(GPP_A16, NONE),
 	/* A17 : NC */
 	PAD_NC(GPP_A17, NONE),
 	/* A18 : NC */
@@ -118,7 +118,7 @@ static const struct pad_config gpio_table[] = {
 	PAD_CFG_NF(GPP_C7, NONE, DEEP, NF1),
 
 	/* D0  : SEN_MODE2_EC_PCH_INT_ODL */
-	PAD_CFG_NF(GPP_D0, NONE, DEEP, NF1),
+	PAD_NC_LOCK(GPP_D0, NONE, LOCK_CONFIG),
 	/* D1  : ISH_GP1 ==> SEN_MODE2_EC_ISH_INT_ODL */
 	PAD_CFG_NF(GPP_D1, NONE, DEEP, NF1),
 	/* D2  : NC */
@@ -176,24 +176,24 @@ static const struct pad_config gpio_table[] = {
 	PAD_NC(GPP_E7, NONE),
 	/* E8  : GPP_E8 ==> WLAN_DISABLE_L */
 	PAD_CFG_GPO(GPP_E8, 1, DEEP),
-	/* E9  : SOC_USB_OC0 */
-	PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1),
+	/* E9  : SOC_USB_OC0 ==> NC */
+	PAD_NC(GPP_E9, NONE),
 	/* E10 : EN_PP3300_WLAN_X */
 	PAD_CFG_GPO(GPP_E10, 1, DEEP),
 	/* E11 : TCHSCR_INT_ODL */
 	PAD_CFG_GPI_APIC(GPP_E11, NONE, PLTRST, LEVEL, INVERT),
 	/* E12 : THC0_SPI1_IO1 ==> SOC_WP_OD */
 	PAD_CFG_GPI_GPIO_DRIVER_LOCK(GPP_E12, NONE, LOCK_CONFIG),
-	/* E13 : THC0_SPI1_IO0 ==> NC*/
-	PAD_NC_LOCK(GPP_E13, NONE, LOCK_CONFIG),
+	/* E13 : THC0_SPI1_IO0 ==> MEM_STRAP_3 */
+	PAD_CFG_GPI_LOCK(GPP_E13, NONE, LOCK_CONFIG),
 	/* E14 : DDSP_HPDA ==> EDP_HPD */
 	PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1),
 	/* E15 : NC */
 	PAD_NC(GPP_E15, NONE),
 	/* E16 : NC */
 	PAD_NC(GPP_E16, NONE),
-	/* E17  : MEM_STRAP_3 */
-	PAD_CFG_GPI_LOCK(GPP_E17, NONE, LOCK_CONFIG),
+	/* E17  : MEM_STRAP_3 => NC */
+	PAD_NC_LOCK(GPP_E17, NONE, LOCK_CONFIG),
 	/* E18 : NC */
 	PAD_NC(GPP_E18, NONE),
 	/* E19 : DDP1_CTRLDATA ==> GPP_E19_STRAP */
@@ -290,8 +290,8 @@ static const struct pad_config gpio_table[] = {
 	PAD_NC_LOCK(GPP_H15, NONE, LOCK_CONFIG),
 	/* H16 : Not available */
 	PAD_NC(GPP_H16, NONE),
-	/* H17  : DDPB_CTRLDATA ==> PD_SOC_DBG_L */
-	PAD_CFG_NF(GPP_H17, NONE, DEEP, NF1),
+	/* H17  : DDPB_CTRLDATA ==> NC */
+	PAD_NC(GPP_H17, NONE),
 	/* H18 : PROC_C10_GATE# ==> CPU_C10_GATE# */
 	PAD_CFG_NF(GPP_H18, NONE, DEEP, NF1),
 	/* H19 : SOC_I2C_SUB_INT_ODL */

From 350c977fefdb85f15ce1530158ecdc2e0eb62816 Mon Sep 17 00:00:00 2001
From: Sowmya Aralguppe <sowmya.aralguppe@intel.com>
Date: Mon, 21 Jul 2025 18:56:53 +0530
Subject: [PATCH 1706/3886] soc/intel/pantherlake: Clear crashlog record using
 watcher

After crash data extraction, the records are cleared and reinitialized
to their default values. This is done using watcher interface instead
of BIOS mailbox commands because of low latency and efficiency.

Ref: LNL FAS 733648
BUG= b:None
TEST= iotools mmio_dump 0x9c199d40 0x10 - PMC
0x000000009c199d40: 0xdeadbeef 0xdeadbeef 0xdeadbeef 0xdeadbeef
iotools mmio_dump 0x9c1d0058 0x10 - CPU
0x000000009c1d0058: 0xcafecafe 0xcafecafe 0xcafecafe 0xcafecafe
Initial 8 bytes of header are zeroes - indicating that both header
and crashlog data buffer are cleared

Change-Id: I8a36e091f61833067caf9e9f94ba79149e699d68
Signed-off-by: Sowmya Aralguppe <sowmya.aralguppe@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88514
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
---
 src/soc/intel/pantherlake/crashlog.c             | 6 ++++++
 src/soc/intel/pantherlake/include/soc/crashlog.h | 1 +
 2 files changed, 7 insertions(+)

diff --git a/src/soc/intel/pantherlake/crashlog.c b/src/soc/intel/pantherlake/crashlog.c
index d9a80f46c1..a57a16863f 100644
--- a/src/soc/intel/pantherlake/crashlog.c
+++ b/src/soc/intel/pantherlake/crashlog.c
@@ -18,6 +18,8 @@
 #define CRASHLOG_PUNIT_STORAGE_OFF_MASK	BIT(24)
 #define CRASHLOG_RE_ARM_STATUS_MASK	BIT(25)
 #define CRASHLOG_CONSUMED_BIOS_MASK	BIT(27)
+#define CRASHLOG_SET_CLEAR_TRIGGER_MASK	BIT(30)
+#define CRASHLOG_SET_CONSUMED_MASK	BIT(18)
 
 /* Global crashLog info */
 static bool m_pmc_crash_log_support;
@@ -392,6 +394,10 @@ static uintptr_t get_control_status_interface(void)
 
 int cpu_cl_clear_data(void)
 {
+	/* Clear all crashlog data and CRASHLOG_SET_CONSUMED = 1 -> sets CONSUMED_BIOS bit */
+	setbits64p(cl_get_cpu_bar_addr() + CRASHLOG_WATCHER_CONTROL_OFFSET,
+			CRASHLOG_SET_CLEAR_TRIGGER_MASK | CRASHLOG_SET_CONSUMED_MASK);
+
 	return 0;
 }
 
diff --git a/src/soc/intel/pantherlake/include/soc/crashlog.h b/src/soc/intel/pantherlake/include/soc/crashlog.h
index eed653ba7d..32a37bd89b 100644
--- a/src/soc/intel/pantherlake/include/soc/crashlog.h
+++ b/src/soc/intel/pantherlake/include/soc/crashlog.h
@@ -14,6 +14,7 @@
 #define CRASHLOG_DVSEC_ID			0x04
 #define TEL_DVSEC_TBIR_BAR0			0
 #define TEL_DVSEC_TBIR_BAR1			1
+#define CRASHLOG_WATCHER_CONTROL_OFFSET		0x10
 
 typedef union {
 	struct {

From 8a45e505b9b1126cbaafcb3c4509f5253fb9c514 Mon Sep 17 00:00:00 2001
From: Yidi Lin <yidilin@google.com>
Date: Mon, 28 Jul 2025 11:53:34 +0800
Subject: [PATCH 1707/3886] soc/mediatek/common/dp: Change
 dptx_hal_phy_wait_aux_ldo_ready to static

TEST=emerge-rauru coreboot

Change-Id: Ia72960c14426b8412bfb5238fa882d1adcb1d6b3
Signed-off-by: Yidi Lin <yidilin@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88581
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
---
 src/soc/mediatek/common/dp/dptx_hal_v2.c             | 2 +-
 src/soc/mediatek/common/dp/include/soc/dptx_hal_v2.h | 1 -
 2 files changed, 1 insertion(+), 2 deletions(-)

diff --git a/src/soc/mediatek/common/dp/dptx_hal_v2.c b/src/soc/mediatek/common/dp/dptx_hal_v2.c
index 628af99112..4de941fa61 100644
--- a/src/soc/mediatek/common/dp/dptx_hal_v2.c
+++ b/src/soc/mediatek/common/dp/dptx_hal_v2.c
@@ -282,7 +282,7 @@ void dptx_hal_swing_emp_reset(struct mtk_dp *mtk_dp)
 		    DP_TX2_PRE_EMPH_MASK | DP_TX3_PRE_EMPH_MASK);
 }
 
-void dptx_hal_phy_wait_aux_ldo_ready(struct mtk_dp *mtk_dp)
+static void dptx_hal_phy_wait_aux_ldo_ready(struct mtk_dp *mtk_dp)
 {
 	u32 mask = RGS_BG_CORE_EN_READY_MASK | RGS_AUX_LDO_EN_READY_MASK;
 
diff --git a/src/soc/mediatek/common/dp/include/soc/dptx_hal_v2.h b/src/soc/mediatek/common/dp/include/soc/dptx_hal_v2.h
index 7f49e5608b..1727b84eb6 100644
--- a/src/soc/mediatek/common/dp/include/soc/dptx_hal_v2.h
+++ b/src/soc/mediatek/common/dp/include/soc/dptx_hal_v2.h
@@ -21,7 +21,6 @@ extern const int dptx_hal_driving_offset_size;
 
 void dptx_hal_swing_emp_reset(struct mtk_dp *mtk_dp);
 void dptx_hal_phy_init(struct mtk_dp *mtk_dp);
-void dptx_hal_phy_wait_aux_ldo_ready(struct mtk_dp *mtk_dp);
 void dptx_hal_phy_set_idle_pattern(struct mtk_dp *mtk_dp, u8 lane_count, bool enable);
 void dptx_hal_phy_set_lanes(struct mtk_dp *mtk_dp, u8 lane_count);
 

From 7b91339e5536101d25110bcf45462a01c87f5e9d Mon Sep 17 00:00:00 2001
From: Nick Vaccaro <nvaccaro@google.com>
Date: Mon, 28 Jul 2025 16:43:07 -0700
Subject: [PATCH 1708/3886] Revert "mb/google/brya: Fix pmc_mux port mapping
 for mithrax and felwinter"

BUG=b:368661724, b:434033860, b:407590653, b:398060672
TEST: `emerge-brya coreboot chromeos-bootimage`, flash and boot mithrax
to recovery screen and verify it can detect USB recovery stick in USB-C
ports

This reverts commit e638a113fafe981c224c9d7f7a7701dda5e1fd0b.

Change-Id: I6a6349515f6662d792cf2f069bc847effa33a400
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88595
Reviewed-by: Eran Mitrani <mitrani@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 .../brya/variants/felwinter/overridetree.cb   | 24 ++++++++--------
 .../brya/variants/mithrax/overridetree.cb     | 28 +++++++++----------
 2 files changed, 26 insertions(+), 26 deletions(-)

diff --git a/src/mainboard/google/brya/variants/felwinter/overridetree.cb b/src/mainboard/google/brya/variants/felwinter/overridetree.cb
index 1865ac6966..97909b2cec 100644
--- a/src/mainboard/google/brya/variants/felwinter/overridetree.cb
+++ b/src/mainboard/google/brya/variants/felwinter/overridetree.cb
@@ -359,13 +359,13 @@ chip soc/intel/alderlake
 			chip drivers/intel/pmc_mux
 				device generic 0 on
 					chip drivers/intel/pmc_mux/conn
-						use usb2_port2 as usb2_port
-						use tcss_usb3_port2 as usb3_port
+						use usb2_port3 as usb2_port
+						use tcss_usb3_port3 as usb3_port
 						device generic 2 alias conn2 on end
 					end
 					chip drivers/intel/pmc_mux/conn
-						use usb2_port3 as usb2_port
-						use tcss_usb3_port3 as usb3_port
+						use usb2_port2 as usb2_port
+						use tcss_usb3_port2 as usb3_port
 						device generic 1 alias conn1 on end
 					end
 				end
@@ -378,16 +378,16 @@ chip soc/intel/alderlake
 						register "desc" = ""USB3 Type-C Port C1 (DB)""
 						register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
 						register "use_custom_pld" = "true"
-						register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, RIGHT, ACPI_PLD_GROUP(1, 1))"
+						register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(1, 1))"
 						register "usb_lpm_incapable" = "true"
-						device ref tcss_usb3_port3 on end
+						device ref tcss_usb3_port2 on end
 					end
 					chip drivers/usb/acpi
 						register "desc" = ""USB3 Type-C Port C2 (MLB)""
 						register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
 						register "use_custom_pld" = "true"
-						register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(2, 1))"
-						device ref tcss_usb3_port2 on end
+						register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, RIGHT, ACPI_PLD_GROUP(2, 1))"
+						device ref tcss_usb3_port3 on end
 					end
 				end
 			end
@@ -399,15 +399,15 @@ chip soc/intel/alderlake
 						register "desc" = ""USB2 Type-C Port C1 (DB)""
 						register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
 						register "use_custom_pld" = "true"
-						register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, RIGHT, ACPI_PLD_GROUP(1, 1))"
-						device ref usb2_port3 on end
+						register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(1, 1))"
+						device ref usb2_port2 on end
 					end
 					chip drivers/usb/acpi
 						register "desc" = ""USB2 Type-C Port C2 (MLB)""
 						register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
 						register "use_custom_pld" = "true"
-						register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(2, 1))"
-						device ref usb2_port2 on end
+						register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, RIGHT, ACPI_PLD_GROUP(2, 1))"
+						device ref usb2_port3 on end
 					end
 					chip drivers/usb/acpi
 						register "desc" = ""USB2 Camera""
diff --git a/src/mainboard/google/brya/variants/mithrax/overridetree.cb b/src/mainboard/google/brya/variants/mithrax/overridetree.cb
index 6a85edf658..3695e6b669 100644
--- a/src/mainboard/google/brya/variants/mithrax/overridetree.cb
+++ b/src/mainboard/google/brya/variants/mithrax/overridetree.cb
@@ -316,13 +316,13 @@ chip soc/intel/alderlake
 			chip drivers/intel/pmc_mux
 				device generic 0 on
 					chip drivers/intel/pmc_mux/conn
-						use usb2_port2 as usb2_port
-						use tcss_usb3_port2 as usb3_port
+						use usb2_port3 as usb2_port
+						use tcss_usb3_port3 as usb3_port
 						device generic 2 alias conn2 on end
 					end
 					chip drivers/intel/pmc_mux/conn
-						use usb2_port3 as usb2_port
-						use tcss_usb3_port3 as usb3_port
+						use usb2_port2 as usb2_port
+						use tcss_usb3_port2 as usb3_port
 						device generic 1 alias conn1 on end
 					end
 				end
@@ -335,16 +335,16 @@ chip soc/intel/alderlake
 						register "desc" = ""USB3 Type-C Port C1 (DB)""
 						register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
 						register "use_custom_pld" = "true"
-						register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, LEFT, ACPI_PLD_GROUP(1, 1))"
+						register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(1, 1))"
 						register "usb_lpm_incapable" = "true"
-						device ref tcss_usb3_port3 on end
+						device ref tcss_usb3_port2 on end
 					end
 					chip drivers/usb/acpi
 						register "desc" = ""USB3 Type-C Port C2 (MLB)""
 						register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
 						register "use_custom_pld" = "true"
-						register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(2, 1))"
-						device ref tcss_usb3_port2 on end
+						register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, RIGHT, ACPI_PLD_GROUP(2, 1))"
+						device ref tcss_usb3_port3 on end
 					end
 				end
 			end
@@ -356,15 +356,15 @@ chip soc/intel/alderlake
 						register "desc" = ""USB2 Type-C Port C1 (DB)""
 						register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
 						register "use_custom_pld" = "true"
-						register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, LEFT, ACPI_PLD_GROUP(1, 1))"
-						device ref usb2_port3 on end
+						register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(1, 1))"
+						device ref usb2_port2 on end
 					end
 					chip drivers/usb/acpi
 						register "desc" = ""USB2 Type-C Port C2 (MLB)""
 						register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
 						register "use_custom_pld" = "true"
-						register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(2, 1))"
-						device ref usb2_port2 on end
+						register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, RIGHT, ACPI_PLD_GROUP(2, 1))"
+						device ref usb2_port3 on end
 					end
 					chip drivers/usb/acpi
 						register "desc" = ""USB2 Camera""
@@ -375,7 +375,7 @@ chip soc/intel/alderlake
 						register "desc" = ""USB2 Type-A Port A0 (DB)""
 						register "type" = "UPC_TYPE_A"
 						register "use_custom_pld" = "true"
-						register "custom_pld" = "ACPI_PLD_TYPE_A(RIGHT, RIGHT, ACPI_PLD_GROUP(1, 2))"
+						register "custom_pld" = "ACPI_PLD_TYPE_A(RIGHT, LEFT, ACPI_PLD_GROUP(1, 2))"
 						device ref usb2_port9 on end
 					end
 					chip drivers/usb/acpi
@@ -389,7 +389,7 @@ chip soc/intel/alderlake
 						register "desc" = ""USB3 Type-A Port A0 (DB)""
 						register "type" = "UPC_TYPE_USB3_A"
 						register "use_custom_pld" = "true"
-						register "custom_pld" = "ACPI_PLD_TYPE_A(RIGHT, RIGHT, ACPI_PLD_GROUP(1, 2))"
+						register "custom_pld" = "ACPI_PLD_TYPE_A(RIGHT, LEFT, ACPI_PLD_GROUP(1, 2))"
 						device ref usb3_port1 on end
 					end
 				end

From 211526ff38c6149b85cd112f87427cbe1189c3a9 Mon Sep 17 00:00:00 2001
From: Nick Vaccaro <nvaccaro@google.com>
Date: Mon, 28 Jul 2025 16:52:18 -0700
Subject: [PATCH 1709/3886] Revert "mb/google/brya: Fix mux_conn index used by
 ec/google/chromeec"

BUG=b:368661724, b:434033860, b:407590653, b:398060672
TEST: `emerge-brya coreboot chromeos-bootimage`, flash and boot mithrax
to recovery screen and verify it can detect USB recovery stick in USB-C
ports.

This reverts commit 9207621d23aefe7213ab1a764bd78402237e4e8f.

Change-Id: I453562ab5802c7b9e38b7555415747dd9205aacb
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88596
Reviewed-by: Eran Mitrani <mitrani@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/google/brya/variants/felwinter/overridetree.cb | 4 ++--
 src/mainboard/google/brya/variants/mithrax/overridetree.cb   | 4 ++--
 2 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/src/mainboard/google/brya/variants/felwinter/overridetree.cb b/src/mainboard/google/brya/variants/felwinter/overridetree.cb
index 97909b2cec..23d6d17f08 100644
--- a/src/mainboard/google/brya/variants/felwinter/overridetree.cb
+++ b/src/mainboard/google/brya/variants/felwinter/overridetree.cb
@@ -350,8 +350,8 @@ chip soc/intel/alderlake
 		end
 		device ref pch_espi on
 			chip ec/google/chromeec
-				use conn1 as mux_conn[0]
-				use conn2 as mux_conn[1]
+				use conn1 as mux_conn[1]
+				use conn2 as mux_conn[0]
 				device pnp 0c09.0 on end
 			end
 		end
diff --git a/src/mainboard/google/brya/variants/mithrax/overridetree.cb b/src/mainboard/google/brya/variants/mithrax/overridetree.cb
index 3695e6b669..4c1a359161 100644
--- a/src/mainboard/google/brya/variants/mithrax/overridetree.cb
+++ b/src/mainboard/google/brya/variants/mithrax/overridetree.cb
@@ -307,8 +307,8 @@ chip soc/intel/alderlake
 		end
 		device ref pch_espi on
 			chip ec/google/chromeec
-				use conn1 as mux_conn[0]
-				use conn2 as mux_conn[1]
+				use conn1 as mux_conn[1]
+				use conn2 as mux_conn[0]
 				device pnp 0c09.0 on end
 			end
 		end

From fea789ed63c5fdca918e7ca77f88acb19e3b349d Mon Sep 17 00:00:00 2001
From: Subrata Banik <subratabanik@google.com>
Date: Mon, 28 Jul 2025 11:59:58 +0530
Subject: [PATCH 1710/3886] mb/google/fatcat/var/francka: Use ACPI for
 touchscreen power sequencing

This commit transitions the touchscreen power sequencing from static
coreboot GPIO configuration to ACPI-driven management for the Francka
variant.

BUG=b:430444353
TEST=Able to build and boot google/francka. Verified touchscreen is
working as expected with this patch.

Change-Id: I2b6c0cacdc159eaf98279bd57efb81c8454ee580
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88510
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
---
 src/mainboard/google/fatcat/variants/francka/overridetree.cb | 1 +
 1 file changed, 1 insertion(+)

diff --git a/src/mainboard/google/fatcat/variants/francka/overridetree.cb b/src/mainboard/google/fatcat/variants/francka/overridetree.cb
index 323918aafe..342a23da17 100644
--- a/src/mainboard/google/fatcat/variants/francka/overridetree.cb
+++ b/src/mainboard/google/fatcat/variants/francka/overridetree.cb
@@ -213,6 +213,7 @@ chip soc/intel/pantherlake
 				register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B18)"
 				register "generic.enable_delay_ms" = "12"
 				register "generic.has_power_resource" = "1"
+				register "generic.use_gpio_for_status" = "true"
 				register "hid_desc_reg_offset" = "0x01"
 				device i2c 41 on end
 			end

From a9997f2d7f05adcb157f85d140de723a5254d8ff Mon Sep 17 00:00:00 2001
From: Subrata Banik <subratabanik@google.com>
Date: Sun, 27 Jul 2025 18:18:14 +0530
Subject: [PATCH 1711/3886] soc/intel/cmn/block: Request bus master in final op
 for DSP and HDA

This commit assigns pci_dev_request_bus_master to the .final operation
for both the DSP and HDA device operations to ensure that the bus
master is enabled.

This change ensures correct PCI configuration for DSP and HDA devices,
preventing potential issues with direct memory access operations.

BUG=b:427091370
TEST=Able to build and boot google/fatcat.

w/o this patch

```
firmware-shell: pcir.b 0 0x1f 3 0x4
0x02
```

w/ this patch:

```
firmware-shell: pcir.b 0 0x1f 3 0x4
0x06
```

Change-Id: Id2480dba08ea8ee7a9219327b8a31f8f9f65410c
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88575
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
---
 src/soc/intel/common/block/dsp/dsp.c | 1 +
 src/soc/intel/common/block/hda/hda.c | 1 +
 2 files changed, 2 insertions(+)

diff --git a/src/soc/intel/common/block/dsp/dsp.c b/src/soc/intel/common/block/dsp/dsp.c
index af43a99e77..9155a2a7b7 100644
--- a/src/soc/intel/common/block/dsp/dsp.c
+++ b/src/soc/intel/common/block/dsp/dsp.c
@@ -10,6 +10,7 @@ static struct device_operations dsp_dev_ops = {
 	.enable_resources       = pci_dev_enable_resources,
 	.ops_pci                = &pci_dev_ops_pci,
 	.scan_bus               = scan_static_bus,
+	.final                  = pci_dev_request_bus_master,
 };
 
 static const unsigned short pci_device_ids[] = {
diff --git a/src/soc/intel/common/block/hda/hda.c b/src/soc/intel/common/block/hda/hda.c
index 37dc9ea91b..f5e22bc6d9 100644
--- a/src/soc/intel/common/block/hda/hda.c
+++ b/src/soc/intel/common/block/hda/hda.c
@@ -24,6 +24,7 @@ struct device_operations hda_ops = {
 	.set_resources		= pci_dev_set_resources,
 	.enable_resources	= pci_dev_enable_resources,
 	.init			= hda_init,
+	.final			= pci_dev_request_bus_master,
 	.ops_pci		= &pci_dev_ops_pci,
 	.scan_bus		= scan_static_bus
 };

From 54016e273e2edeb186490a403b7be5d443e6bd3b Mon Sep 17 00:00:00 2001
From: Yu-Ping Wu <yupingso@chromium.org>
Date: Wed, 30 Jul 2025 03:32:20 +0800
Subject: [PATCH 1712/3886] util/cbmem/sysfs_drv: Fix incompatible pointer type
 for 'size'

Fix the following error for armv7a-cros-linux-gnueabihf-clang.

sysfs_drv.c:247:49: error: incompatible pointer types passing 'uint64_t *' (aka
      'unsigned long long *') to parameter of type 'size_t *'
      (aka 'unsigned int *') [-Werror,-Wincompatible-pointer-types]
  247 |                 if (!cbmem_sysfs_probe_cbmem_entry(id, &addr, &size))
      |                                                               ^~~~~
sysfs_drv.c:99:84: note: passing argument to parameter 'size_out' here
   99 |   ...id, uint64_t *addr_out, size_t *size_out)
      |                                      ^
1 error generated.

BUG=b:434971585
TEST=none
BRANCH=none

Change-Id: I5e2be25d57c5e69501564b6e8b6d880ec046bc3b
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88605
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 util/cbmem/sysfs_drv.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/util/cbmem/sysfs_drv.c b/util/cbmem/sysfs_drv.c
index 2820bbd4ee..cb4a4ab540 100644
--- a/util/cbmem/sysfs_drv.c
+++ b/util/cbmem/sysfs_drv.c
@@ -239,7 +239,7 @@ void cbmem_sysfs_foreach_cbmem_entry(cbmem_iterator_callback cb, void *data, boo
 			continue;
 
 		uint64_t addr = 0;
-		uint64_t size = 0;
+		size_t size = 0;
 		uint8_t *buf;
 
 		/* If entry was not found or previously matched directory

From 53dd93ff14d1237e694a28c406cb031348e8feb2 Mon Sep 17 00:00:00 2001
From: Kapil Porwal <kapilporwal@google.com>
Date: Mon, 28 Jul 2025 17:28:22 +0530
Subject: [PATCH 1713/3886] libpayload/drivers/pci_qcom: Fix address during ATU
 config

BUG=none
TEST=CQ

Change-Id: Id9825cca5dc6cb26cc72970ee496efa564c0b95d
Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88588
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
---
 payloads/libpayload/drivers/pci_qcom.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/payloads/libpayload/drivers/pci_qcom.c b/payloads/libpayload/drivers/pci_qcom.c
index ee159b952c..26db30f5ac 100644
--- a/payloads/libpayload/drivers/pci_qcom.c
+++ b/payloads/libpayload/drivers/pci_qcom.c
@@ -120,7 +120,8 @@ uintptr_t pci_map_bus(pcidev_t dev)
 	atu_type = current_bus == 1 ? PCIE_ATU_TYPE_CFG0 : PCIE_ATU_TYPE_CFG1;
 
 	dw_pcie_prog_outbound_atu(atu_base, PCIE_ATU_REGION_INDEX0, atu_type,
-				  (uint64_t)config_base, busdev, config_size);
+				  (uint64_t)config_base + (QCOM_EP_CFG_SIZE * devfn),
+				  busdev, config_size);
 out:
 	return (uintptr_t)config_base + (QCOM_EP_CFG_SIZE * devfn);
 }

From 2ae0f6cdb94b5fa391f90f038e867e02f76963fd Mon Sep 17 00:00:00 2001
From: "wu.garen" <wu.garen@inventec.corp-partner.google.com>
Date: Mon, 28 Jul 2025 14:38:02 +0800
Subject: [PATCH 1714/3886] mb/google/trulo/var/kaladin: Add fw config for ELAN
 touchscreen

Kaladin support 2 kinds of ELAN touchscreen with different
slave address:

TOP(Touch_IC on Panel): slave address 0x10
DBTS(Touch IC on Daughter BOARD):slave address 0x15

Add FW config to separate ELAN touch screen.

BUG=b:434591789
TEST=build and verified touchscreen work

Change-Id: I3e1c748baf1d392c626ce17f4fcb601ec02ce428
Signed-off-by: wu.garen <wu.garen@inventec.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88585
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 .../google/brya/variants/kaladin/overridetree.cb   | 14 +++++++++++---
 1 file changed, 11 insertions(+), 3 deletions(-)

diff --git a/src/mainboard/google/brya/variants/kaladin/overridetree.cb b/src/mainboard/google/brya/variants/kaladin/overridetree.cb
index 6d36246028..d6396afe55 100644
--- a/src/mainboard/google/brya/variants/kaladin/overridetree.cb
+++ b/src/mainboard/google/brya/variants/kaladin/overridetree.cb
@@ -7,6 +7,10 @@ fw_config
 		option MB_USB_1C_1A 0
 		option MB_USB_2C_1A 1
 	end
+	field TOUCH_PANEL 4 5
+		option TOUCH_ELAN_TOP   0
+		option TOUCH_ELAN_DBTS  1
+	end
 	field STORAGE 30 31
 		option STORAGE_EMMC		0
 		option STORAGE_NVME		1
@@ -464,7 +468,7 @@ chip soc/intel/alderlake
 		end #I2C0
 		device ref i2c1 on
 			chip drivers/i2c/hid
-				register "generic.hid" = ""ELAN901C""
+				register "generic.hid" = ""ELAN2513""
 				register "generic.desc" = ""ELAN Touchscreen""
 				register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_E11_IRQ)"
 				register "generic.detect" = "1"
@@ -478,7 +482,9 @@ chip soc/intel/alderlake
 				register "generic.enable_delay_ms" = "1"
 				register "generic.has_power_resource" = "1"
 				register "hid_desc_reg_offset" = "0x01"
-				device i2c 10 on end
+				device i2c 10 on
+					probe TOUCH_PANEL TOUCH_ELAN_TOP
+				end
 			end
 			chip drivers/i2c/hid
 				register "generic.hid" = ""ELAN2513""
@@ -495,7 +501,9 @@ chip soc/intel/alderlake
 				register "generic.has_power_resource" = "1"
 				register "generic.use_gpio_for_status" = "true"
 				register "hid_desc_reg_offset" = "0x01"
-				device i2c 15 on end
+				device i2c 15 on
+					probe TOUCH_PANEL TOUCH_ELAN_DBTS
+				end
 			end
 		end #I2C1
 		device ref i2c5 on

From 3c4fb7b729ca409bdb6acf1f63d17258664e5390 Mon Sep 17 00:00:00 2001
From: Luca Lai <luca.lai@lcfc.corp-partner.google.com>
Date: Mon, 28 Jul 2025 21:30:20 +0800
Subject: [PATCH 1715/3886] mb/google/trulo/var/pujjolo: Update verb table

Update the verb table to decrease the speaker output level.

BUG=b:404480459
TEST=Build and boot to OS, check test result is pass with
hardware engineer and Realtek.

Change-Id: I4f0544ab220ffdbcb2e61ca2f1d2e0d9ae36b1ce
Signed-off-by: Luca Lai <luca.lai@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88592
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
---
 src/mainboard/google/brya/variants/pujjolo/hda_verb.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/mainboard/google/brya/variants/pujjolo/hda_verb.c b/src/mainboard/google/brya/variants/pujjolo/hda_verb.c
index a34adef9f8..d7f73667f6 100644
--- a/src/mainboard/google/brya/variants/pujjolo/hda_verb.c
+++ b/src/mainboard/google/brya/variants/pujjolo/hda_verb.c
@@ -37,7 +37,7 @@ const u32 cim_verb_data[] = {
 	0x0204C003,
 	//==========Widget node 0x20 - 1 : ClassD 2W
 	0x02050038,
-	0x02047981,
+	0x02048981,
 	0x0205001B,
 	0x02040A4B,
 	//==========Widget node 0x20 - 2

From 749fd1a8d8246566a9b38338743576073ac62d16 Mon Sep 17 00:00:00 2001
From: Subrata Banik <subratabanik@google.com>
Date: Wed, 30 Jul 2025 12:10:46 +0530
Subject: [PATCH 1716/3886] soc/intel/pantherlake: Use macro for VGA Init
 Control

The magic number '1' for VgaInitControl is replaced with the
VGA_INIT_CONTROL_ENABLE macro for improved readability and
maintainability.

This makes the code's intent clearer and aligns with best practices
for using named constants.

The VGA_INIT_CONTROL_ENABLE macro is defined in ux.h along with a
comment to describe its purpose.

TEST=Able to see eSOL while booting google/fatcat.

Change-Id: I27a91030c0aaa52e099869c5870da670d3e28628
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88608
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Pranava Y N <pranavayn@google.com>
---
 src/soc/intel/pantherlake/romstage/ux.c | 2 +-
 src/soc/intel/pantherlake/romstage/ux.h | 5 +++++
 2 files changed, 6 insertions(+), 1 deletion(-)

diff --git a/src/soc/intel/pantherlake/romstage/ux.c b/src/soc/intel/pantherlake/romstage/ux.c
index 9fcb418157..e9d94fd315 100644
--- a/src/soc/intel/pantherlake/romstage/ux.c
+++ b/src/soc/intel/pantherlake/romstage/ux.c
@@ -44,7 +44,7 @@ static bool ux_inform_user_of_operation(const char *name, enum ux_locale_msg id,
 		return false;
 	}
 
-	m_cfg->VgaInitControl = 1;
+	m_cfg->VgaInitControl = VGA_INIT_CONTROL_ENABLE;
 	m_cfg->VbtPtr = (efi_uintn_t)vbt;
 	m_cfg->VbtSize = vbt_size;
 	m_cfg->LidStatus = CONFIG(VBOOT_LID_SWITCH) ? get_lid_switch() : CONFIG(RUN_FSP_GOP);
diff --git a/src/soc/intel/pantherlake/romstage/ux.h b/src/soc/intel/pantherlake/romstage/ux.h
index bcee87f24d..28858d5843 100644
--- a/src/soc/intel/pantherlake/romstage/ux.h
+++ b/src/soc/intel/pantherlake/romstage/ux.h
@@ -3,7 +3,12 @@
 #ifndef _SOC_INTEL_PANTHERLAKE_ROMSTAGE_UX_H_
 #define _SOC_INTEL_PANTHERLAKE_ROMSTAGE_UX_H_
 
+#include <types.h>
+
 bool ux_inform_user_of_update_operation(const char *name, FSPM_UPD *mupd);
 bool ux_inform_user_of_poweroff_operation(const char *name, FSPM_UPD *mupd);
 
+/* VGA initialization configuration */
+#define VGA_INIT_CONTROL_ENABLE		BIT(0)
+
 #endif /* _SOC_INTEL_PANTHERLAKE_ROMSTAGE_UX_H_ */

From 0f84878c89d249dfa902d201d83cd6dc228defd7 Mon Sep 17 00:00:00 2001
From: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Date: Wed, 30 Jul 2025 08:36:16 +0800
Subject: [PATCH 1717/3886] mb/google/brox: Handle NULL return value in
 variant_get_auxfw_version_file

When bundled fw is NULL the system boot hangs.
Add a judgement to return mismatch when bundled fw is NULL.

BUG=b:434844512
BRANCH=firmware-brox-16080.B
TEST=emerge-brox coreboot
     set FW_CONFIG=STORAGE_NVME and DUT can boot into OS

Change-Id: Ibe81e944725b8c387c61451c2e422d57f7aeb8c1
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88606
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jon Murphy <jpmurphy@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
---
 src/mainboard/google/brox/variants/baseboard/brox/romstage.c | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/src/mainboard/google/brox/variants/baseboard/brox/romstage.c b/src/mainboard/google/brox/variants/baseboard/brox/romstage.c
index 6a03a9ae46..ce402af933 100644
--- a/src/mainboard/google/brox/variants/baseboard/brox/romstage.c
+++ b/src/mainboard/google/brox/variants/baseboard/brox/romstage.c
@@ -30,6 +30,10 @@ static bool check_auxfw_ver_mismatch(void)
 	cur_major_ver = (pd_chip_r.fw_version_number >> 16) & 0xFF;
 	is_productionfw = !!(cur_major_ver & 0xF0);
 
+	/* check whether bundled fw is NULL */
+	if (!fwver_fname)
+		return mismatch;
+
 	/* find bundled fw hash */
 	new_ver = cbfs_map(fwver_fname, &new_ver_size);
 	if (new_ver == NULL || new_ver_size != FWVER_SIZE)

From ac7487d766ce97333f3e4f3661de95759a45f139 Mon Sep 17 00:00:00 2001
From: Pranava Y N <pranavayn@google.com>
Date: Wed, 30 Jul 2025 09:14:16 +0530
Subject: [PATCH 1718/3886] mb/google/fatcat: Use same MAINBOARD_PART_NUMBER
 for felino variants

This patch unifies all the felino variants based on
`BOARD_GOOGLE_MODEL_FELINO` to use the same mainboard part number
`Felino`.

BUG=b:430205874
TEST=Able to build/boot felino

Change-Id: I15a9372e18a910916e9f695d920fc502bf6afa06
Signed-off-by: Pranava Y N <pranavayn@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88611
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/google/fatcat/Kconfig | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/src/mainboard/google/fatcat/Kconfig b/src/mainboard/google/fatcat/Kconfig
index fa592c96c3..e0377cabaa 100644
--- a/src/mainboard/google/fatcat/Kconfig
+++ b/src/mainboard/google/fatcat/Kconfig
@@ -173,8 +173,7 @@ config MAINBOARD_FAMILY
 config MAINBOARD_PART_NUMBER
 	default "Fatcat" if BOARD_GOOGLE_MODEL_FATCAT
 	default "Francka" if BOARD_GOOGLE_FRANCKA
-	default "Felino" if BOARD_GOOGLE_FELINO
-	default "Felino4ES" if BOARD_GOOGLE_FELINO4ES
+	default "Felino" if BOARD_GOOGLE_MODEL_FELINO
 	default "Kinmen" if BOARD_GOOGLE_KINMEN
 
 config MEMORY_SOLDERDOWN

From e977560e725c2a8ff0e990bbf7d4d552a7e57ea8 Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Mon, 28 Jul 2025 14:57:32 -0500
Subject: [PATCH 1719/3886] payloads/edk2: Increase non-full-screen menu size

When the edk2 full-screen setup option is not used, the default console
size is 80x25, which is far to small to effectively navigate the menus,
especially now with many boards implementing CFR for setup options.
Increase the default size from 80x25 to 128x40, which is a good middle
ground for both low-res laptop displays and large external monitors.

TEST=build/boot edk2 with full-screen setup option disabled on Starlabs
starlite_adl and byte_twl with displays of varying resolution.

Change-Id: I5ddcd06a66989b45f8f6e39a102298dc73b06c6d
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88594
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Benjamin Doron <benjamin.doron00@gmail.com>
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
---
 payloads/external/edk2/Makefile | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/payloads/external/edk2/Makefile b/payloads/external/edk2/Makefile
index f16aefd053..7c87c3469e 100644
--- a/payloads/external/edk2/Makefile
+++ b/payloads/external/edk2/Makefile
@@ -172,6 +172,11 @@ BUILD_STR += --pcd gEfiMdeModulePkgTokenSpaceGuid.PcdConOutRow=0
 BUILD_STR += --pcd gEfiMdeModulePkgTokenSpaceGuid.PcdConOutColumn=0
 BUILD_STR += --pcd gEfiMdeModulePkgTokenSpaceGuid.PcdSetupConOutRow=0
 BUILD_STR += --pcd gEfiMdeModulePkgTokenSpaceGuid.PcdSetupConOutColumn=0
+else
+BUILD_STR += --pcd gEfiMdeModulePkgTokenSpaceGuid.PcdConOutRow=40
+BUILD_STR += --pcd gEfiMdeModulePkgTokenSpaceGuid.PcdConOutColumn=128
+BUILD_STR += --pcd gEfiMdeModulePkgTokenSpaceGuid.PcdSetupConOutRow=40
+BUILD_STR += --pcd gEfiMdeModulePkgTokenSpaceGuid.PcdSetupConOutColumn=128
 endif
 
 BUILD_STR += --pcd gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultOemId="COREv4"

From 88aeb8b7cde43998d4bf1188c90977b7d1706e43 Mon Sep 17 00:00:00 2001
From: Benjamin Doron <benjamin.doron@9elements.com>
Date: Fri, 11 Jul 2025 17:23:51 -0400
Subject: [PATCH 1720/3886] util/smmstoretool: Allow setting authenticated
 variable

Change-Id: I82ee1b84dfa7fafb17ddb0d4adf1891e1c5f149b
Signed-off-by: Benjamin Doron <benjamin.doron@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88425
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
---
 util/smmstoretool/main.c | 8 +++++++-
 1 file changed, 7 insertions(+), 1 deletion(-)

diff --git a/util/smmstoretool/main.c b/util/smmstoretool/main.c
index 4092fc59dc..7a5de9b9ce 100644
--- a/util/smmstoretool/main.c
+++ b/util/smmstoretool/main.c
@@ -140,6 +140,7 @@ static void help_set(FILE *f, const struct subcommand_t *info)
 	fprintf(f, "      -n variable-name \\\n");
 	fprintf(f, "      -t variable-type \\\n");
 	fprintf(f, "      -v value\n");
+	fprintf(f, "      -a\n");
 	fprintf(f, "\n");
 	print_types(f);
 }
@@ -150,8 +151,9 @@ static int process_set(int argc, char *argv[], const char store_file[])
 	const char *value = NULL;
 	const char *type_str = NULL;
 	const char *guid_str = NULL;
+	bool authenticated_var = false;
 	int opt;
-	while ((opt = getopt(argc, argv, "n:t:v:g:")) != -1) {
+	while ((opt = getopt(argc, argv, "n:t:v:g:a::")) != -1) {
 		switch (opt) {
 		case 'n':
 			name = optarg;
@@ -165,6 +167,9 @@ static int process_set(int argc, char *argv[], const char store_file[])
 		case 'g':
 			guid_str = optarg;
 			break;
+		case 'a':
+			authenticated_var = true;
+			break;
 
 		case '?': /* parsing error */
 			print_sub_command_usage(argv[0]);
@@ -217,6 +222,7 @@ static int process_set(int argc, char *argv[], const char store_file[])
 	struct var_t *var = vs_find(&storage.vs, name, &guid);
 	if (var == NULL) {
 		var = vs_new_var(&storage.vs);
+		var->attrs |= authenticated_var ? EFI_VARIABLE_TIME_BASED_AUTHENTICATED_WRITE_ACCESS : 0;
 		var->name = to_uchars(name, &var->name_size);
 		var->data = data;
 		var->data_size = data_size;

From 008f0ec078fe24ab707aadafddfafc19b37d9bcf Mon Sep 17 00:00:00 2001
From: Benjamin Doron <benjamin.doron@9elements.com>
Date: Mon, 14 Jul 2025 13:40:19 -0400
Subject: [PATCH 1721/3886] util/smmstoretool: Alias
 EfiImageSecurityDatabaseGuid to "secureboot"

Finalise the new support for adding secure boot variables by adding this
alias. db and dbx have this GUID, all others (PKDefault, KEKDefault,
dbDefault, dbxDefault, PK, and KEK) have the "global" GUID.

Change-Id: I58a825498d57c0bc04516fe41fe94924bdff2181
Signed-off-by: Benjamin Doron <benjamin.doron@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88426
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
---
 util/smmstoretool/guids.c | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/util/smmstoretool/guids.c b/util/smmstoretool/guids.c
index 4ba92b9798..ee93988b25 100644
--- a/util/smmstoretool/guids.c
+++ b/util/smmstoretool/guids.c
@@ -32,6 +32,13 @@ const struct guid_alias_t known_guids[] = {
 			{ 0xaa, 0x0d, 0x00, 0xe0, 0x98, 0x03, 0x2b, 0x8c }
 		},
 	},
+	{
+		"secureboot",
+		{
+			0xd719b2cb, 0x3d3a, 0x4596,
+			{ 0xa3, 0xbc, 0xda, 0xd0, 0x0e, 0x67, 0x65, 0x6f }
+		},
+	},
 	{
 		"microsoft",
 		{

From fbc2d76ab3beb0a59e97b82c5b1dbb793a1c4a4e Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Mon, 21 Jul 2025 14:32:20 -0500
Subject: [PATCH 1722/3886] soc/intel/*: Select 'DRAM_SUPPORT_DDRx' as
 appropriate

These will be used in subsequent patches which optimize the reading of
SPDs based on the supported memory type(s).

Change-Id: I8b0d4f37b4b992c42bede25d678cb9afc9db3dd6
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88521
Reviewed-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
---
 src/soc/intel/alderlake/Kconfig    | 2 ++
 src/soc/intel/apollolake/Kconfig   | 2 ++
 src/soc/intel/braswell/Kconfig     | 1 +
 src/soc/intel/broadwell/Kconfig    | 1 +
 src/soc/intel/cannonlake/Kconfig   | 1 +
 src/soc/intel/denverton_ns/Kconfig | 1 +
 src/soc/intel/elkhartlake/Kconfig  | 2 ++
 src/soc/intel/jasperlake/Kconfig   | 1 +
 src/soc/intel/meteorlake/Kconfig   | 1 +
 src/soc/intel/pantherlake/Kconfig  | 1 +
 src/soc/intel/skylake/Kconfig      | 2 ++
 src/soc/intel/tigerlake/Kconfig    | 2 ++
 src/soc/intel/xeon_sp/cpx/Kconfig  | 1 +
 src/soc/intel/xeon_sp/gnr/Kconfig  | 1 +
 src/soc/intel/xeon_sp/skx/Kconfig  | 1 +
 src/soc/intel/xeon_sp/spr/Kconfig  | 1 +
 16 files changed, 21 insertions(+)

diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig
index 51bdf98b9d..97c2ecca70 100644
--- a/src/soc/intel/alderlake/Kconfig
+++ b/src/soc/intel/alderlake/Kconfig
@@ -12,6 +12,8 @@ config SOC_INTEL_ALDERLAKE
 	select CPU_SUPPORTS_PM_TIMER_EMULATION
 	select DEFAULT_SOFTWARE_CONNECTION_MANAGER
 	select DISPLAY_FSP_VERSION_INFO
+	select DRAM_SUPPORT_DDR4
+	select DRAM_SUPPORT_DDR5
 	select DRIVERS_USB_ACPI
 	select EDK2_CPU_TIMER_LIB if PAYLOAD_EDK2
 	select FSP_COMPRESS_FSP_S_LZ4
diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig
index 47a90830e1..ef5d4f6b8a 100644
--- a/src/soc/intel/apollolake/Kconfig
+++ b/src/soc/intel/apollolake/Kconfig
@@ -10,6 +10,8 @@ config SOC_INTEL_APOLLOLAKE
 	# CPU specific options
 	select CPU_INTEL_COMMON
 	select CPU_SUPPORTS_PM_TIMER_EMULATION
+	select DRAM_SUPPORT_DDR3
+	select DRAM_SUPPORT_LPDDR4
 	select PCR_COMMON_IOSF_1_0
 	select SSE2
 	select SUPPORT_CPU_UCODE_IN_CBFS
diff --git a/src/soc/intel/braswell/Kconfig b/src/soc/intel/braswell/Kconfig
index 9b96d112fc..7189078f2c 100644
--- a/src/soc/intel/braswell/Kconfig
+++ b/src/soc/intel/braswell/Kconfig
@@ -40,6 +40,7 @@ config SOC_INTEL_BRASWELL
 	select NO_CBFS_MCACHE
 	select TCO_SPACE_NOT_YET_SPLIT
 	select NEED_SMALL_2MB_PAGE_TABLES
+	select DRAM_SUPPORT_DDR3
 	help
 	  Braswell M/D part support.
 
diff --git a/src/soc/intel/broadwell/Kconfig b/src/soc/intel/broadwell/Kconfig
index e92aee0cef..74650ff212 100644
--- a/src/soc/intel/broadwell/Kconfig
+++ b/src/soc/intel/broadwell/Kconfig
@@ -4,6 +4,7 @@ config SOC_INTEL_BROADWELL
 	bool
 	select CACHE_MRC_SETTINGS
 	select CPU_INTEL_HASWELL
+	select DRAM_SUPPORT_DDR3
 	select GENERIC_GPIO_LIB
 	select INTEL_GMA_ACPI
 	select MRC_SETTINGS_PROTECT
diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig
index 67ab428a49..738371bc1b 100644
--- a/src/soc/intel/cannonlake/Kconfig
+++ b/src/soc/intel/cannonlake/Kconfig
@@ -11,6 +11,7 @@ config SOC_INTEL_CANNONLAKE_BASE
 	select CPU_INTEL_FIRMWARE_INTERFACE_TABLE
 	select CPU_SUPPORTS_PM_TIMER_EMULATION
 	select DISPLAY_FSP_VERSION_INFO
+	select DRAM_SUPPORT_DDR4
 	select DRIVERS_USB_ACPI
 	select EDK2_CPU_TIMER_LIB if PAYLOAD_EDK2
 	select FSP_COMPRESS_FSP_S_LZMA
diff --git a/src/soc/intel/denverton_ns/Kconfig b/src/soc/intel/denverton_ns/Kconfig
index 55ba2cdae9..c462cf77c0 100644
--- a/src/soc/intel/denverton_ns/Kconfig
+++ b/src/soc/intel/denverton_ns/Kconfig
@@ -9,6 +9,7 @@ config SOC_INTEL_DENVERTON_NS
 	select CPU_INTEL_FIRMWARE_INTERFACE_TABLE
 	select CPU_SUPPORTS_PM_TIMER_EMULATION
 	select DEBUG_GPIO
+	select DRAM_SUPPORT_DDR4
 	select EDK2_CPU_TIMER_LIB if PAYLOAD_EDK2
 	select FSP_M_XIP
 	select FSP_T_XIP if FSP_CAR
diff --git a/src/soc/intel/elkhartlake/Kconfig b/src/soc/intel/elkhartlake/Kconfig
index ff3c82f6ff..6fb4f52d61 100644
--- a/src/soc/intel/elkhartlake/Kconfig
+++ b/src/soc/intel/elkhartlake/Kconfig
@@ -10,6 +10,8 @@ config SOC_INTEL_ELKHARTLAKE
 	select CPU_INTEL_FIRMWARE_INTERFACE_TABLE
 	select CPU_SUPPORTS_PM_TIMER_EMULATION
 	select DISPLAY_FSP_VERSION_INFO
+	select DRAM_SUPPORT_DDR4
+	select DRAM_SUPPORT_LPDDR4
 	select EDK2_CPU_TIMER_LIB if PAYLOAD_EDK2
 	select FSP_COMPRESS_FSP_S_LZ4
 	select FSP_M_XIP
diff --git a/src/soc/intel/jasperlake/Kconfig b/src/soc/intel/jasperlake/Kconfig
index 3fd6826e12..727e9609ce 100644
--- a/src/soc/intel/jasperlake/Kconfig
+++ b/src/soc/intel/jasperlake/Kconfig
@@ -11,6 +11,7 @@ config SOC_INTEL_JASPERLAKE
 	select CPU_SUPPORTS_PM_TIMER_EMULATION
 	select COS_MAPPED_TO_MSB
 	select DISPLAY_FSP_VERSION_INFO_2
+	select DRAM_SUPPORT_DDR4
 	select EDK2_CPU_TIMER_LIB if PAYLOAD_EDK2
 	select FSP_COMPRESS_FSP_S_LZ4
 	select FSP_M_XIP
diff --git a/src/soc/intel/meteorlake/Kconfig b/src/soc/intel/meteorlake/Kconfig
index b9dc579c44..c1c2266973 100644
--- a/src/soc/intel/meteorlake/Kconfig
+++ b/src/soc/intel/meteorlake/Kconfig
@@ -14,6 +14,7 @@ config SOC_INTEL_METEORLAKE
 	select DEFAULT_SOFTWARE_CONNECTION_MANAGER
 	select DEFAULT_X2APIC_LATE_WORKAROUND
 	select DISPLAY_FSP_VERSION_INFO_2 if !FSP_USE_REPO
+	select DRAM_SUPPORT_DDR5
 	select DRIVERS_USB_ACPI
 	select EDK2_CPU_TIMER_LIB if PAYLOAD_EDK2
 	select FSP_COMPRESS_FSP_S_LZ4
diff --git a/src/soc/intel/pantherlake/Kconfig b/src/soc/intel/pantherlake/Kconfig
index 2ebc92a78d..d604edb555 100644
--- a/src/soc/intel/pantherlake/Kconfig
+++ b/src/soc/intel/pantherlake/Kconfig
@@ -17,6 +17,7 @@ config SOC_INTEL_PANTHERLAKE_BASE
 	select DEFAULT_X2APIC_LATE_WORKAROUND
 	select POSTPONE_SPI_ACCESS
 	select DISPLAY_FSP_VERSION_INFO_2
+	select DRAM_SUPPORT_DDR5
 	select DRIVERS_USB_ACPI
 	select FAST_SPI_DMA
 	select FAST_SPI_SUPPORTS_EXT_BIOS_WINDOW
diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig
index 4ad33496b2..4977e8d25d 100644
--- a/src/soc/intel/skylake/Kconfig
+++ b/src/soc/intel/skylake/Kconfig
@@ -10,6 +10,8 @@ config SOC_INTEL_COMMON_SKYLAKE_BASE
 	select CPU_INTEL_COMMON
 	select CPU_INTEL_FIRMWARE_INTERFACE_TABLE
 	select CPU_SUPPORTS_PM_TIMER_EMULATION
+	select DRAM_SUPPORT_DDR3
+	select DRAM_SUPPORT_DDR4
 	select EDK2_CPU_TIMER_LIB if PAYLOAD_EDK2
 	select FSP_COMPRESS_FSP_S_LZ4
 	select FSP_M_XIP
diff --git a/src/soc/intel/tigerlake/Kconfig b/src/soc/intel/tigerlake/Kconfig
index 833684f0a6..d76ddec335 100644
--- a/src/soc/intel/tigerlake/Kconfig
+++ b/src/soc/intel/tigerlake/Kconfig
@@ -12,6 +12,8 @@ config SOC_INTEL_TIGERLAKE
 	select CPU_SUPPORTS_PM_TIMER_EMULATION
 	select DEFAULT_SOFTWARE_CONNECTION_MANAGER
 	select DISPLAY_FSP_VERSION_INFO if !FSP_TYPE_IOT
+	select DRAM_SUPPORT_DDR4
+	select DRAM_SUPPORT_LPDDR4
 	select DRIVERS_USB_ACPI
 	select EDK2_CPU_TIMER_LIB if PAYLOAD_EDK2
 	select FAST_SPI_SUPPORTS_EXT_BIOS_WINDOW
diff --git a/src/soc/intel/xeon_sp/cpx/Kconfig b/src/soc/intel/xeon_sp/cpx/Kconfig
index 51e545f148..6e3ee60b1c 100644
--- a/src/soc/intel/xeon_sp/cpx/Kconfig
+++ b/src/soc/intel/xeon_sp/cpx/Kconfig
@@ -9,6 +9,7 @@ config SOC_INTEL_COOPERLAKE_SP
 	select HAVE_INTEL_FSP_REPO
 	select FSP_SPEC_VIOLATION_XEON_SP_HEAP_WORKAROUND
 	select UDK_202005_BINDING
+	select DRAM_SUPPORT_DDR4
 	help
 	  Intel Cooper Lake-SP support
 
diff --git a/src/soc/intel/xeon_sp/gnr/Kconfig b/src/soc/intel/xeon_sp/gnr/Kconfig
index a259320342..e55f458164 100644
--- a/src/soc/intel/xeon_sp/gnr/Kconfig
+++ b/src/soc/intel/xeon_sp/gnr/Kconfig
@@ -14,6 +14,7 @@ config SOC_INTEL_GRANITERAPIDS
 	select PLATFORM_USES_FSP2_X86_32
 	select HAVE_IOAT_DOMAINS
 	select FSP_SPEC_VIOLATION_XEON_SP_HEAP_WORKAROUND
+	select DRAM_SUPPORT_DDR5
 	help
 	  Intel Granite Rapids support
 
diff --git a/src/soc/intel/xeon_sp/skx/Kconfig b/src/soc/intel/xeon_sp/skx/Kconfig
index acbc31fcad..54bcfc09be 100644
--- a/src/soc/intel/xeon_sp/skx/Kconfig
+++ b/src/soc/intel/xeon_sp/skx/Kconfig
@@ -8,6 +8,7 @@ config SOC_INTEL_SKYLAKE_SP
 	select UDK_202005_BINDING
 	select HAVE_X86_64_SUPPORT
 	select USE_X86_64_SUPPORT
+	select DRAM_SUPPORT_DDR4
 	help
 	  Intel Skylake-SP support
 
diff --git a/src/soc/intel/xeon_sp/spr/Kconfig b/src/soc/intel/xeon_sp/spr/Kconfig
index e36f684cc6..75cf107ce3 100644
--- a/src/soc/intel/xeon_sp/spr/Kconfig
+++ b/src/soc/intel/xeon_sp/spr/Kconfig
@@ -17,6 +17,7 @@ config SOC_INTEL_SAPPHIRERAPIDS_SP
 	select SOC_INTEL_HAS_CXL
 	select HAVE_X86_64_SUPPORT
 	select HAVE_INTEL_FSP_REPO
+	select DRAM_SUPPORT_DDR5
 	help
 	  Intel Sapphire Rapids-SP support
 

From 280d3a25e8e84e1bfed84ef957c65c491badfd86 Mon Sep 17 00:00:00 2001
From: Nicholas Chin <nic.c3.14@gmail.com>
Date: Wed, 30 Jul 2025 21:13:16 -0600
Subject: [PATCH 1723/3886] util/lint/kconfig_lint: Fix operator precedence
 issue

Perl 5.42.0 added a new warning for possible precedence problems between
the `!` logical negation operator and various other operators [1]. In
particular, the kconfig_lint script uses `!` and `=~` (binding operator)
to check that a filename does not match a regex, but was written in a
way that would be parsed as negating the filename and then comparing it
to the regex. The resulting warning from the newer version of Perl
caused lint-stable to fail on the lint-stable-008-kconfig test due to
the non empty output, causing the pre-commit hook to fail.

Fix this by using the negated binding operator `!~` instead as
recommended by the Perl documentation [2].

[1] https://perldoc.perl.org/perl5420delta#New-Warnings
[2] https://perldoc.perl.org/perldiag#Possible-precedence-problem-between-!-and-%25s

Change-Id: I3631b8b0be92bf85a1510be1f1d4221a010be1ba
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88619
Reviewed-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 util/lint/kconfig_lint | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/util/lint/kconfig_lint b/util/lint/kconfig_lint
index 551faabdbb..e8a498b19a 100755
--- a/util/lint/kconfig_lint
+++ b/util/lint/kconfig_lint
@@ -1347,8 +1347,8 @@ sub print_wholeconfig {
 sub check_if_file_referenced {
     my $filename = $File::Find::name;
     if (   ( $filename =~ /Kconfig/ )
-        && ( !$filename =~ /\.orig$/ )
-        && ( !$filename =~ /~$/ )
+        && ( $filename !~ /\.orig$/ )
+        && ( $filename !~ /~$/ )
         && ( !exists $loaded_files{$filename} ) )
     {
         show_warning("'$filename' is never referenced");

From 9411c6e7c769db09f10eacf2b0ac4eba5423ddbc Mon Sep 17 00:00:00 2001
From: Martin Roth <gaumless@gmail.com>
Date: Wed, 30 Jul 2025 13:16:08 -0600
Subject: [PATCH 1724/3886] util/amdfwtool: Fix NULL pointer dereference in
 fill_dir_header

Move the NULL pointer check to the beginning of the fill_dir_header function
before any dereference of the directory pointer. This prevents the potential
segmentation fault that could occur if directory is NULL.

This fixes CID 1540835 - Dereference before null check (REVERSE_NULL).

Change-Id: I12bb146d59839381478034f974b7d408f92ae677
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88617
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 util/amdfwtool/amdfwtool.c | 10 +++++-----
 1 file changed, 5 insertions(+), 5 deletions(-)

diff --git a/util/amdfwtool/amdfwtool.c b/util/amdfwtool/amdfwtool.c
index 2b70a0527b..d071a5be7c 100644
--- a/util/amdfwtool/amdfwtool.c
+++ b/util/amdfwtool/amdfwtool.c
@@ -586,6 +586,11 @@ static void copy_psp_header(void *bak, void *orig)
 
 static void fill_dir_header(void *directory, uint32_t count, context *ctx)
 {
+	if (ctx == NULL || directory == NULL) {
+		fprintf(stderr, "Calling %s with NULL pointers\n", __func__);
+		return;
+	}
+
 	psp_combo_directory *cdir = directory;
 	psp_directory_table *dir = directory;
 	bios_directory_table *bdir = directory;
@@ -593,11 +598,6 @@ static void fill_dir_header(void *directory, uint32_t count, context *ctx)
 	uint32_t cookie = ((psp_directory_table *)directory)->header.cookie;
 	uint32_t table_size = 0;
 
-	if (ctx == NULL || directory == NULL) {
-		fprintf(stderr, "Calling %s with NULL pointers\n", __func__);
-		return;
-	}
-
 	/* The table size needs to be 0x1000 aligned. So align the end of table. */
 	adjust_current_pointer(ctx, 0, TABLE_ALIGNMENT);
 

From a79f341d29edd15074773626f4699b457665433e Mon Sep 17 00:00:00 2001
From: Luca Lai <luca.lai@lcfc.corp-partner.google.com>
Date: Tue, 29 Jul 2025 22:02:18 +0800
Subject: [PATCH 1725/3886] mb/google/trulo/var/pujjolo: Disable mipi camera
 dmic LED

Because we do not want to enable the mipi camera dmic LED
at booting, so pull down the EN_PP2800_WCAM_X.
(Pujjolo_Pujjoquince_MB_EVT_20250523.pdf).

BUG=b:427962702
TEST= Build and boot to OS, check the LED is off. And
check the mipi camera function works fine.

Change-Id: Ia9ccf3e335ad65c9a8f68fe33226803cc8555228
Signed-off-by: Luca Lai <luca.lai@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88604
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Eric Lai <ericllai@google.com>
---
 src/mainboard/google/brya/variants/pujjolo/gpio.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/mainboard/google/brya/variants/pujjolo/gpio.c b/src/mainboard/google/brya/variants/pujjolo/gpio.c
index 505333437d..efab7a15b6 100644
--- a/src/mainboard/google/brya/variants/pujjolo/gpio.c
+++ b/src/mainboard/google/brya/variants/pujjolo/gpio.c
@@ -145,7 +145,7 @@ static const struct pad_config override_gpio_table[] = {
 	/* D14 : UART0_ISH_TX_DBG_RX */
 	PAD_CFG_NF(GPP_D14, NONE, DEEP, NF1),
 	/* D15 : ISH_UART0_RTS# ==> EN_PP2800_WCAM_X */
-	PAD_CFG_GPO_LOCK(GPP_D15, 1, LOCK_CONFIG),
+	PAD_CFG_GPO_LOCK(GPP_D15, 0, LOCK_CONFIG),
 	/* D16 : ISH_UART0_CTS# ==> EN_PP1800_PP1200_WCAM_X */
 	PAD_CFG_GPO_LOCK(GPP_D16, 1, LOCK_CONFIG),
 	/* D17  : NC ==> UART_AP_RX_FP_TX */

From cba46a41b7078358b9a0545ef0c385ba8fd9d905 Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Mon, 21 Jul 2025 16:43:21 -0500
Subject: [PATCH 1726/3886] mainboard/{hardkernel,protectli}: Drop use of
 DRAM_SUPPORT_DDR5

This is now selected at the SoC level and therefore redundant.

Change-Id: Ib6ae94c359d3dac34886147e9078043e4f132f84
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88522
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/hardkernel/odroid-h4/Kconfig  | 1 -
 src/mainboard/protectli/vault_adl_p/Kconfig | 1 -
 2 files changed, 2 deletions(-)

diff --git a/src/mainboard/hardkernel/odroid-h4/Kconfig b/src/mainboard/hardkernel/odroid-h4/Kconfig
index 146d245dc7..9307ca4e29 100644
--- a/src/mainboard/hardkernel/odroid-h4/Kconfig
+++ b/src/mainboard/hardkernel/odroid-h4/Kconfig
@@ -15,7 +15,6 @@ config BOARD_SPECIFIC_OPTIONS
 	select SUPERIO_ITE_IT8613E
 	select SOC_INTEL_ALDERLAKE_PCH_N
 	select SOC_INTEL_COMMON_BLOCK_HDA_VERB
-	select DRAM_SUPPORT_DDR5
 
 config MAINBOARD_DIR
 	default "hardkernel/odroid-h4"
diff --git a/src/mainboard/protectli/vault_adl_p/Kconfig b/src/mainboard/protectli/vault_adl_p/Kconfig
index 4cfea63cf2..5b7d52d19f 100644
--- a/src/mainboard/protectli/vault_adl_p/Kconfig
+++ b/src/mainboard/protectli/vault_adl_p/Kconfig
@@ -15,7 +15,6 @@ config BOARD_SPECIFIC_OPTIONS
 	select HAVE_ACPI_TABLES
 	select INTEL_GMA_HAVE_VBT
 	select MEMORY_MAPPED_TPM
-	select DRAM_SUPPORT_DDR5
 
 config MAINBOARD_DIR
 	default "protectli/vault_adl_p"

From e9cb352706c17a53148c3f682debdb12ae774d4a Mon Sep 17 00:00:00 2001
From: Jeremy Soller <jeremy@system76.com>
Date: Fri, 31 May 2024 18:35:37 -0600
Subject: [PATCH 1727/3886] soc/common/smbus: Support reading SPD5 hubs for
 DDR5

DDR5 uses a Serial Presence Detect (SPD) with hub function
(SPD5 hub device) to store the SPD data. The SPD5 hub has 1024 bytes of
EEPROM (`CONFIG_DIMM_SPD_SIZE=1024`).

Ref: DDR5 SDRAM spec, JESD79-5C.01

Change-Id: Ic5e6c58f255bef86b68ce90a4f853bf4e7c7ccfe
Co-authored-by: Meera Ravindranath <meera.ravindranath@intel.com>
Signed-off-by: Jeremy Soller <jeremy@system76.com>
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52731
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/include/spd_bin.h                       | 12 +++
 src/lib/spd_cache.c                         |  4 +-
 src/soc/intel/common/block/smbus/smbuslib.c | 97 +++++++++++++++++----
 3 files changed, 96 insertions(+), 17 deletions(-)

diff --git a/src/include/spd_bin.h b/src/include/spd_bin.h
index bf72b2d122..c380ec89f0 100644
--- a/src/include/spd_bin.h
+++ b/src/include/spd_bin.h
@@ -16,6 +16,18 @@
 #define DDR4_ORGANIZATION	12
 #define DDR4_BUS_DEV_WIDTH	13
 #define DDR4_SPD_SN_OFF		325
+#define MAX_SPD_PAGE_SIZE_SPD5	128
+#define MAX_SPD_SIZE		(256 * 4)
+#define SPD_HUB_MEMREG(addr)	((u8)(0x80 | (addr)))
+#define SPD5_MR11		0x0B
+#define SPD5_MR0		0x00
+#define SPD5_MEMREG_REG(addr)	((u8)((~0x80) & (addr)))
+#define SPD5_MR0_SPD5_HUB_DEV	0x51
+
+struct spd_offset_table {
+	u16 start;		/* Offset 0 */
+	u16 end;		/* Offset 2 */
+};
 
 struct spd_block {
 	u8 addr_map[CONFIG_DIMM_MAX]; /* 7 bit I2C addresses */
diff --git a/src/lib/spd_cache.c b/src/lib/spd_cache.c
index 9a84906bc3..1582270a17 100644
--- a/src/lib/spd_cache.c
+++ b/src/lib/spd_cache.c
@@ -212,7 +212,9 @@ enum cb_err spd_fill_from_cache(uint8_t *spd_cache, struct spd_block *blk)
 
 	dram_type = *(spd_cache + SC_SPD_OFFSET(i) + SPD_MEMORY_TYPE);
 
-	if (dram_type == SPD_MEMORY_TYPE_DDR4_SDRAM)
+	if (dram_type == SPD_MEMORY_TYPE_DDR5_SDRAM)
+		blk->len = CONFIG_DIMM_SPD_SIZE;
+	else if (dram_type == SPD_MEMORY_TYPE_DDR4_SDRAM)
 		blk->len = SPD_SIZE_MAX_DDR4;
 	else
 		blk->len = SPD_SIZE_MAX_DDR3;
diff --git a/src/soc/intel/common/block/smbus/smbuslib.c b/src/soc/intel/common/block/smbus/smbuslib.c
index 2bf33f4370..f7ec63772f 100644
--- a/src/soc/intel/common/block/smbus/smbuslib.c
+++ b/src/soc/intel/common/block/smbus/smbuslib.c
@@ -16,8 +16,11 @@ static void update_spd_len(struct spd_block *blk)
 		if (blk->spd_array[i] != NULL)
 			j |= blk->spd_array[i][SPD_MEMORY_TYPE];
 
+	/* If spd used is DDR5, then its length is 1024 byte. */
+	if (j == SPD_MEMORY_TYPE_DDR5_SDRAM)
+		blk->len = CONFIG_DIMM_SPD_SIZE;
 	/* If spd used is DDR4, then its length is 512 byte. */
-	if (j == SPD_MEMORY_TYPE_DDR4_SDRAM)
+	else if (j == SPD_MEMORY_TYPE_DDR4_SDRAM)
 		blk->len = SPD_SIZE_MAX_DDR4;
 	else
 		blk->len = SPD_SIZE_MAX_DDR3;
@@ -40,6 +43,59 @@ static void spd_read(u8 *spd, u8 addr)
 	}
 }
 
+static void switch_page(u8 spd_addr, u8 new_page)
+{
+	/*
+	 *  By default,an SPD5 hub accepts 1 byte addressing pointing
+	 *  to the first 128 bytes of memory. MR11[2:0] selects the page
+	 *  pointer to address the entire 1024 bytes of non-volatile memory.
+	 */
+	smbus_write_byte(spd_addr, SPD5_MEMREG_REG(SPD5_MR11), new_page);
+}
+
+/*
+ * Read the SPD data over the SMBus, at the specified SPD address,
+ * starting at the specified starting offset and read the given amount of data.
+ */
+static void smbus_read_spd5(u8 *spd, u8 spd_addr, u16 size)
+{
+	u8 page = ~0;
+	u32 max_page_size = MAX_SPD_PAGE_SIZE_SPD5;
+
+	if (size > MAX_SPD_SIZE) {
+		printk(BIOS_ERR, "Maximum SPD size reached\n");
+		return;
+	}
+	for (int i = 0; i < size; i++) {
+		u8 next_page = (u8) (i / max_page_size);
+		if (next_page != page) {
+			switch_page(spd_addr, next_page);
+			page = next_page;
+		}
+		unsigned int byte_addr = SPD_HUB_MEMREG(i % max_page_size);
+		spd[i] = smbus_read_byte(spd_addr, byte_addr);
+	}
+}
+
+/* Read SPD5 MR0 and check if SPD Byte 0 matches the SPD5 HUB MR0 identifier.*/
+static int is_spd5_hub(u8 spd_addr)
+{
+	u8 spd_hub_byte;
+
+	spd_hub_byte = smbus_read_byte(spd_addr, SPD5_MEMREG_REG(SPD5_MR0));
+	return spd_hub_byte == SPD5_MR0_SPD5_HUB_DEV;
+}
+
+/*
+ * Reset the SPD page back to page 0 on an SPD5 Hub device at the
+ * input SPD SMbus address.
+ */
+static void reset_page_spd5(u8 spd_addr)
+{
+	/* Set SPD5 MR11[2:0] = 0 (Page 0) */
+	switch_page(spd_addr, 0);
+}
+
 /* return -1 if SMBus errors otherwise return 0 */
 static int get_spd(u8 *spd, u8 addr)
 {
@@ -55,27 +111,36 @@ static int get_spd(u8 *spd, u8 addr)
 		return -1;
 	}
 
-	/* IMC doesn't support i2c eeprom read. */
-	if (CONFIG(SOC_INTEL_COMMON_BLOCK_IMC) ||
-	    i2c_eeprom_read(addr, 0, SPD_SIZE_MAX_DDR3, spd) < 0) {
-		printk(BIOS_INFO, "do_i2c_eeprom_read failed, using fallback\n");
-		spd_read(spd, addr);
-	}
-
-	/* Check if module is DDR4, DDR4 spd is 512 byte. */
-	if (spd[SPD_MEMORY_TYPE] == SPD_MEMORY_TYPE_DDR4_SDRAM && CONFIG_DIMM_SPD_SIZE > SPD_SIZE_MAX_DDR3) {
-		/* Switch to page 1 */
-		spd_write_byte(SPD_PAGE_1, 0, 0);
+	if (CONFIG(DRAM_SUPPORT_DDR5) && is_spd5_hub(addr)) {
+		smbus_read_spd5(spd, addr, CONFIG_DIMM_SPD_SIZE);
 
+		/* Reset the page for the next loop iteration */
+		reset_page_spd5(addr);
+	} else {
 		/* IMC doesn't support i2c eeprom read. */
 		if (CONFIG(SOC_INTEL_COMMON_BLOCK_IMC) ||
-		    i2c_eeprom_read(addr, 0, SPD_SIZE_MAX_DDR3, spd + SPD_SIZE_MAX_DDR3) < 0) {
+		    i2c_eeprom_read(addr, 0, SPD_SIZE_MAX_DDR3, spd) < 0) {
 			printk(BIOS_INFO, "do_i2c_eeprom_read failed, using fallback\n");
-			spd_read(spd + SPD_SIZE_MAX_DDR3, addr);
+			spd_read(spd, addr);
+		}
+
+		/* Check if module is DDR4, DDR4 spd is 512 byte. */
+		if (spd[SPD_MEMORY_TYPE] == SPD_MEMORY_TYPE_DDR4_SDRAM &&
+		    CONFIG_DIMM_SPD_SIZE > SPD_SIZE_MAX_DDR3) {
+			/* Switch to page 1 */
+			spd_write_byte(SPD_PAGE_1, 0, 0);
+
+			/* IMC doesn't support i2c eeprom read. */
+			if (CONFIG(SOC_INTEL_COMMON_BLOCK_IMC) ||
+			    i2c_eeprom_read(addr, 0, SPD_SIZE_MAX_DDR3, spd + SPD_SIZE_MAX_DDR3) < 0) {
+				printk(BIOS_INFO, "do_i2c_eeprom_read failed, using fallback\n");
+				spd_read(spd + SPD_SIZE_MAX_DDR3, addr);
+			}
+			/* Restore to page 0 */
+			spd_write_byte(SPD_PAGE_0, 0, 0);
 		}
-		/* Restore to page 0 */
-		spd_write_byte(SPD_PAGE_0, 0, 0);
 	}
+
 	return 0;
 }
 

From 6a42eb9134ceb667d45e3d23118d08eabed41d5f Mon Sep 17 00:00:00 2001
From: alokagar <alok.agarwal@intel.com>
Date: Tue, 22 Jul 2025 10:37:58 +0530
Subject: [PATCH 1728/3886] soc/intel/pantherlake: Disable memory training
 progress bar

Introduce the disable_progress_bar setting in configuration to allow
disabling the memory training progress bar during firmware
initialization.

BUG=b:418675387
TEST=After setting disable_progress_bar, memory training progress bar
is disabled.

Change-Id: I35e8191df27c0eda634724580514e980bd620136
Signed-off-by: Alok Agarwal <alok.agarwal@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88529
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
---
 src/soc/intel/pantherlake/chip.h        | 3 +++
 src/soc/intel/pantherlake/romstage/ux.c | 5 +++++
 src/soc/intel/pantherlake/romstage/ux.h | 1 +
 3 files changed, 9 insertions(+)

diff --git a/src/soc/intel/pantherlake/chip.h b/src/soc/intel/pantherlake/chip.h
index e060a28bb3..b424cb1ebc 100644
--- a/src/soc/intel/pantherlake/chip.h
+++ b/src/soc/intel/pantherlake/chip.h
@@ -653,6 +653,9 @@ struct soc_intel_pantherlake_config {
 	 * for wake will be exposed in ACPI
 	 */
 	bool thc_wake_on_touch[NUM_THC];
+
+	/* Disable the progress bar during MRC training operations. */
+	bool disable_progress_bar;
 };
 
 typedef struct soc_intel_pantherlake_config config_t;
diff --git a/src/soc/intel/pantherlake/romstage/ux.c b/src/soc/intel/pantherlake/romstage/ux.c
index e9d94fd315..5f511a2827 100644
--- a/src/soc/intel/pantherlake/romstage/ux.c
+++ b/src/soc/intel/pantherlake/romstage/ux.c
@@ -5,12 +5,15 @@
 #include <fsp/util.h>
 #include <timestamp.h>
 #include <ux_locales.h>
+#include <static.h>
+#include <soc/soc_chip.h>
 
 #include "ux.h"
 
 static bool ux_inform_user_of_operation(const char *name, enum ux_locale_msg id,
 		 FSPM_UPD *mupd)
 {
+	const struct soc_intel_pantherlake_config *config = config_of_soc();
 	timestamp_add_now(TS_ESOL_START);
 
 	if (!CONFIG(CHROMEOS_ENABLE_ESOL)) {
@@ -45,6 +48,8 @@ static bool ux_inform_user_of_operation(const char *name, enum ux_locale_msg id,
 	}
 
 	m_cfg->VgaInitControl = VGA_INIT_CONTROL_ENABLE;
+	if (config->disable_progress_bar)
+		m_cfg->VgaInitControl |= VGA_INIT_DISABLE_ANIMATION;
 	m_cfg->VbtPtr = (efi_uintn_t)vbt;
 	m_cfg->VbtSize = vbt_size;
 	m_cfg->LidStatus = CONFIG(VBOOT_LID_SWITCH) ? get_lid_switch() : CONFIG(RUN_FSP_GOP);
diff --git a/src/soc/intel/pantherlake/romstage/ux.h b/src/soc/intel/pantherlake/romstage/ux.h
index 28858d5843..85a641dec8 100644
--- a/src/soc/intel/pantherlake/romstage/ux.h
+++ b/src/soc/intel/pantherlake/romstage/ux.h
@@ -10,5 +10,6 @@ bool ux_inform_user_of_poweroff_operation(const char *name, FSPM_UPD *mupd);
 
 /* VGA initialization configuration */
 #define VGA_INIT_CONTROL_ENABLE		BIT(0)
+#define VGA_INIT_DISABLE_ANIMATION  BIT(4)
 
 #endif /* _SOC_INTEL_PANTHERLAKE_ROMSTAGE_UX_H_ */

From ba228d160f766e507f0c542cd97362a8b0a23ce2 Mon Sep 17 00:00:00 2001
From: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Date: Thu, 31 Jul 2025 15:46:04 +0800
Subject: [PATCH 1729/3886] mb/google/fatcat: Create new kinmen4es variant

This new variant will support PTL pre-production silicon. The existing
`kinmen` variant will support production silicon.

BUG=b:434847748
TEST=Able to build google/kinmen4es.

Change-Id: If0597c1b63179e46a83286f2d46f958189f627cc
Signed-off-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88622
Reviewed-by: YH Lin <yueherngl@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Pranava Y N <pranavayn@google.com>
---
 src/mainboard/google/fatcat/Kconfig           | 23 +++++++++++++------
 src/mainboard/google/fatcat/Kconfig.name      |  3 +++
 .../baseboard/fatcat/include/baseboard/gpio.h |  2 +-
 3 files changed, 20 insertions(+), 8 deletions(-)

diff --git a/src/mainboard/google/fatcat/Kconfig b/src/mainboard/google/fatcat/Kconfig
index e0377cabaa..372b27ccd1 100644
--- a/src/mainboard/google/fatcat/Kconfig
+++ b/src/mainboard/google/fatcat/Kconfig
@@ -73,6 +73,13 @@ config BOARD_GOOGLE_MODEL_FELINO
 	select DRIVERS_SOUNDWIRE_ALC1320
 	select MAINBOARD_HAS_GOOGLE_STRAUSS_KEYBOARD
 
+config BOARD_GOOGLE_MODEL_KINMEN
+	def_bool n
+	select BOARD_GOOGLE_BASEBOARD_FATCAT
+	select FSP_UGOP_EARLY_SIGN_OF_LIFE
+	select HAVE_SLP_S0_GATE
+	select MAINBOARD_HAS_GOOGLE_STRAUSS_KEYBOARD
+
 config BOARD_GOOGLE_FATCAT
 	select BOARD_GOOGLE_MODEL_FATCAT
 	select EC_GOOGLE_CHROMEEC_MEC
@@ -117,10 +124,12 @@ config BOARD_GOOGLE_FRANCKA
 	select HAVE_SLP_S0_GATE
 	select SOC_INTEL_PANTHERLAKE_PRE_PRODUCTION_SILICON
 
+config BOARD_GOOGLE_KINMEN4ES
+	select BOARD_GOOGLE_MODEL_KINMEN
+	select SOC_INTEL_PANTHERLAKE_PRE_PRODUCTION_SILICON
+
 config BOARD_GOOGLE_KINMEN
-	select BOARD_GOOGLE_BASEBOARD_FATCAT
-	select HAVE_SLP_S0_GATE
-	select MAINBOARD_HAS_GOOGLE_STRAUSS_KEYBOARD
+	select BOARD_GOOGLE_MODEL_KINMEN
 
 if BOARD_GOOGLE_FATCAT_COMMON
 
@@ -158,7 +167,7 @@ config DRIVER_TPM_I2C_BUS
 	default 0x03 if BOARD_GOOGLE_MODEL_FATCAT
 	default 0x01 if BOARD_GOOGLE_FRANCKA
 	default 0x01 if BOARD_GOOGLE_MODEL_FELINO
-	default 0x03 if BOARD_GOOGLE_KINMEN
+	default 0x03 if BOARD_GOOGLE_MODEL_KINMEN
 
 config HAVE_SLP_S0_GATE
 	def_bool n
@@ -174,7 +183,7 @@ config MAINBOARD_PART_NUMBER
 	default "Fatcat" if BOARD_GOOGLE_MODEL_FATCAT
 	default "Francka" if BOARD_GOOGLE_FRANCKA
 	default "Felino" if BOARD_GOOGLE_MODEL_FELINO
-	default "Kinmen" if BOARD_GOOGLE_KINMEN
+	default "Kinmen" if BOARD_GOOGLE_MODEL_KINMEN
 
 config MEMORY_SOLDERDOWN
 	def_bool n
@@ -186,7 +195,7 @@ config TPM_TIS_ACPI_INTERRUPT
 	default 47 if BOARD_GOOGLE_MODEL_FATCAT # GPE0_DW1_15 (GPP_D15)
 	default 79 if BOARD_GOOGLE_MODEL_FELINO # GPE0_DW2_15 (GPP_F15)
 	default 11 if BOARD_GOOGLE_FRANCKA # GPE0_DW0_11 (GPP_H11)
-	default 66 if BOARD_GOOGLE_KINMEN # GPE0_DW2_02 (GPP_E02)
+	default 66 if BOARD_GOOGLE_MODEL_KINMEN # GPE0_DW2_02 (GPP_E02)
 
 # FIXME: update as per board schematics
 config UART_FOR_CONSOLE
@@ -201,7 +210,7 @@ config VARIANT_DIR
 	default "fatcat" if BOARD_GOOGLE_MODEL_FATCAT
 	default "francka" if BOARD_GOOGLE_FRANCKA
 	default "felino" if BOARD_GOOGLE_MODEL_FELINO
-	default "kinmen" if BOARD_GOOGLE_KINMEN
+	default "kinmen" if BOARD_GOOGLE_MODEL_KINMEN
 
 config OVERRIDE_DEVICETREE
 	default "variants/\$(CONFIG_VARIANT_DIR)/overridetree.cb"
diff --git a/src/mainboard/google/fatcat/Kconfig.name b/src/mainboard/google/fatcat/Kconfig.name
index 14ad4c1f6a..b7090069d4 100644
--- a/src/mainboard/google/fatcat/Kconfig.name
+++ b/src/mainboard/google/fatcat/Kconfig.name
@@ -32,5 +32,8 @@ config BOARD_GOOGLE_FELINO4ES
 config BOARD_GOOGLE_FRANCKA
 	bool "-> Francka"
 
+config BOARD_GOOGLE_KINMEN4ES
+	bool "-> Kinmen4ES"
+
 config BOARD_GOOGLE_KINMEN
 	bool "-> Kinmen"
diff --git a/src/mainboard/google/fatcat/variants/baseboard/fatcat/include/baseboard/gpio.h b/src/mainboard/google/fatcat/variants/baseboard/fatcat/include/baseboard/gpio.h
index 8c7121c1d8..f0a91b0ff7 100644
--- a/src/mainboard/google/fatcat/variants/baseboard/fatcat/include/baseboard/gpio.h
+++ b/src/mainboard/google/fatcat/variants/baseboard/fatcat/include/baseboard/gpio.h
@@ -32,7 +32,7 @@
  #define GPIO_PCH_WP	GPP_C08
 /* Used to gate SoC's SLP_S0# signal */
 #define GPIO_SLP_S0_GATE	GPP_D03
-#elif CONFIG(BOARD_GOOGLE_KINMEN)
+#elif CONFIG(BOARD_GOOGLE_MODEL_KINMEN)
  #define EC_SYNC_IRQ	GPP_E07_IRQ
  #define GPIO_PCH_WP	GPP_D02
 /* Used to gate SoC's SLP_S0# signal */

From 32b944b77a3b8da254a7e7b63d1482f8526335d9 Mon Sep 17 00:00:00 2001
From: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Date: Thu, 31 Jul 2025 17:13:18 +0800
Subject: [PATCH 1730/3886] mb/google/brox/var/caboc: Update hda_verb table

Update hda_verb table from vendor.

BUG=b:435345756
TEST=emerge-brox coreboot
     check system audio output is fine

Change-Id: Id46d1798b605e7d1fbdfacf2e1899bfc40a113a6
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88627
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
---
 .../variants/caboc/include/variant/hda_verb.h | 73 ++++++++++++++++---
 1 file changed, 62 insertions(+), 11 deletions(-)

diff --git a/src/mainboard/google/brox/variants/caboc/include/variant/hda_verb.h b/src/mainboard/google/brox/variants/caboc/include/variant/hda_verb.h
index 9435ad7d46..495d3b7dab 100644
--- a/src/mainboard/google/brox/variants/caboc/include/variant/hda_verb.h
+++ b/src/mainboard/google/brox/variants/caboc/include/variant/hda_verb.h
@@ -17,14 +17,25 @@ const u32 cim_verb_data[] = {
 
 	/* Pin Widget Verb Table */
 
+	/* 1 bit reset */
+	0x0205001A,
+	0x0204C003,
+	0x0205001A,
+	0x02048003,
+	0x0205007F,
+	0x02046001,
+	0x0205007F,
+	0x02040001,
+
 	/*
 	 * DMIC
-	 * Requirement is to use PCH DMIC. Hence,
-	 * commented out codec's Internal DMIC.
-	 * AZALIA_PIN_CFG(0, 0x12, 0x90A60130),
-	 * AZALIA_PIN_CFG(0, 0x13, 0x40000000),
+	 * Requirement is to use PCH DMIC.
+	 * Vendor suggested to follow verb table to config NID 0x12, NID 0x13.
 	 */
-
+	/* Pin widget 0x12 - DMIC */
+	AZALIA_PIN_CFG(0, 0x12, 0x411111F0),
+	/* Pin widget 0x13 - DMIC */
+	AZALIA_PIN_CFG(0, 0x13, 0x40000000),
 	/* Pin widget 0x14 - Front (Port-D) */
 	AZALIA_PIN_CFG(0, 0x14, 0x90170110),
 	/* Pin widget 0x18 - NPC */
@@ -66,16 +77,36 @@ const u32 cim_verb_data[] = {
 	0x057409A3,
 	/* disable EQ first */
 	0x05350000,
-	0x0534201A,
+	0x0534203A,
 	/* Left Channel */
 	0x0535001d,
 	0x05340800,
 	0x0535001e,
 	0x05340800,
 	0x05350003,
-	0x05341F7B,
+	0x05341F95,
 	0x05350004,
 	0x05340000,
+	0x05350005,
+	0x053403F6,
+	0x05350006,
+	0x0534854C,
+	0x05350007,
+	0x05341E09,
+	0x05350008,
+	0x05346472,
+	0x05350009,
+	0x053401FB,
+	0x0535000A,
+	0x05344836,
+	0x0535000B,
+	0x05341C00,
+	0x0535000C,
+	0x05340000,
+	0x0535000D,
+	0x05340200,
+	0x0535000E,
+	0x05340000,
 	/* Right Channel */
 	0x05450000,
 	0x05442000,
@@ -84,15 +115,35 @@ const u32 cim_verb_data[] = {
 	0x0545001e,
 	0x05440800,
 	0x05450003,
-	0x05441F7B,
+	0x05441F95,
 	0x05450004,
 	0x05440000,
+	0x05450005,
+	0x054403F6,
+	0x05450006,
+	0x0544854C,
+	0x05450007,
+	0x05441E09,
+	0x05450008,
+	0x05446472,
+	0x05450009,
+	0x054401FB,
+	0x0545000A,
+	0x05444836,
+	0x0545000B,
+	0x05441C00,
+	0x0545000C,
+	0x05440000,
+	0x0545000D,
+	0x05440200,
+	0x0545000E,
+	0x05440000,
 	/* enable EQ */
 	0x05350000,
-	0x0534E01A,
-	/* 1.8W/4ohm */
+	0x0534E03A,
+	/* 2.2W/4ohm */
 	0x02050038,
-	0x02047901,
+	0x02046901,
 	/* AGC Enable */
 	0x0205004C,
 	0x0204465C,

From e49743755de23a2fd81658184d39a3d6f01f6f79 Mon Sep 17 00:00:00 2001
From: Appukuttan V K <appukuttan.vk@intel.com>
Date: Fri, 1 Aug 2025 14:47:09 +0530
Subject: [PATCH 1731/3886] mb/google/ocelot: Select EC_GOOGLE_CHROMEEC_MEC for
 MCHP variants

This commit updates the Kconfig for the Google Ocelot mainboard to
select EC_GOOGLE_CHROMEEC_MEC for the OcelotMCHP and OcelotMCHP4ES
variants.

BUG=b:394208231
TEST=Build Ocelot and verify all variants compiles without any error.

Change-Id: Ie5f776d40029b52a57d82aa9b02b95fbf3905cfd
Signed-off-by: Appukuttan V K <appukuttan.vk@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88629
Reviewed-by: Pranava Y N <pranavayn@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Varun Upadhyay <varun.upadhyay@intel.com>
---
 src/mainboard/google/ocelot/Kconfig | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/src/mainboard/google/ocelot/Kconfig b/src/mainboard/google/ocelot/Kconfig
index 12d9e9ce67..8a61867757 100644
--- a/src/mainboard/google/ocelot/Kconfig
+++ b/src/mainboard/google/ocelot/Kconfig
@@ -72,6 +72,7 @@ config BOARD_GOOGLE_OCELOTITE
 
 config BOARD_GOOGLE_OCELOTMCHP
 	select BOARD_GOOGLE_MODEL_OCELOT
+	select EC_GOOGLE_CHROMEEC_MEC
 
 config BOARD_GOOGLE_OCELOT4ES
 	select BOARD_GOOGLE_MODEL_OCELOT
@@ -81,6 +82,7 @@ config BOARD_GOOGLE_OCELOTITE4ES
 
 config BOARD_GOOGLE_OCELOTMCHP4ES
 	select BOARD_GOOGLE_MODEL_OCELOT
+	select EC_GOOGLE_CHROMEEC_MEC
 
 if BOARD_GOOGLE_OCELOT_COMMON
 

From 965131e40fd108b78fea1d46296f5e63356a6a88 Mon Sep 17 00:00:00 2001
From: Vince Liu <vince-wl.liu@mediatek.corp-partner.google.com>
Date: Fri, 1 Aug 2025 17:33:44 +0800
Subject: [PATCH 1732/3886] soc/mediatek/common: Fix build error by including
 stdint.h in cpu_id.h

Include `stdint.h` in `cpu_id.h` to ensure `u32` is properly defined.
This resolves build errors when files including `cpu_id.h` cannot find
the definition for `u32`.

BUG=b:379008996
BRANCH=none
TEST=build passed
Signed-off-by: Vince Liu <vince-wl.liu@mediatek.corp-partner.google.com>
Change-Id: If4b41a6eae38470d4d30baeeef50c8b1ebb82033
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88630
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/soc/mediatek/common/include/soc/cpu_id.h | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/src/soc/mediatek/common/include/soc/cpu_id.h b/src/soc/mediatek/common/include/soc/cpu_id.h
index 173518fc42..0b81382989 100644
--- a/src/soc/mediatek/common/include/soc/cpu_id.h
+++ b/src/soc/mediatek/common/include/soc/cpu_id.h
@@ -3,6 +3,8 @@
 #ifndef SOC_MEDIATEK_COMMON_CPU_ID_H
 #define SOC_MEDIATEK_COMMON_CPU_ID_H
 
+#include <stdint.h>
+
 #define MTK_CPU_ID_MT8186G	0x81861001
 #define MTK_CPU_ID_MT8186T	0x81862001
 #define MTK_CPU_ID_MT8189	0x81890000

From 6afc1ff9acda977a776399e0cf6fb9d392a136e6 Mon Sep 17 00:00:00 2001
From: Zhigang Qin <zhigang.qin@mediatek.corp-partner.google.com>
Date: Wed, 30 Jul 2025 16:10:07 +0800
Subject: [PATCH 1733/3886] soc/mediatek/mt8189: Disable 8189G APU power to
 reduce power consumption

Since MT8189G does not support APU, the LDO_VSRAM_OTHERS and BUCK_VCORE
regulators for the APU power domain can be turned off. Disabling these
power supplies reduces overall system power consumption by about 1mW.

BUG=b:420874944,b:421989583,b:423081787
BRANCH=none
TEST=Verified by measuring system current in S3 state before and after
     disabling APU power.

Signed-off-by: Niklaus Liu <niklausi.liu@mediatek.corp-partner.google.com>
Signed-off-by: Vince Liu <vince-wl.liu@mediatek.corp-partner.google.com>
Signed-off-by: Zhigang Qin <zhigang.qin@mediatek.corp-partner.google.com>
Change-Id: I4e4eeb575327b554f5837bfc0f6a464ff7a1e228
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88631
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
---
 src/soc/mediatek/mt8189/mt6359p.c | 14 ++++++++++++++
 1 file changed, 14 insertions(+)

diff --git a/src/soc/mediatek/mt8189/mt6359p.c b/src/soc/mediatek/mt8189/mt6359p.c
index 7b399abf0f..9c21985fc5 100644
--- a/src/soc/mediatek/mt8189/mt6359p.c
+++ b/src/soc/mediatek/mt8189/mt6359p.c
@@ -1,5 +1,6 @@
 /* SPDX-License-Identifier: GPL-2.0-only OR MIT */
 
+#include <soc/cpu_id.h>
 #include <soc/mt6359p.h>
 
 /*
@@ -187,11 +188,24 @@ static const struct pmic_setting init_setting[] = {
 	{0x18b4, 0x34, 0x7F, 0},
 };
 
+static const struct pmic_setting disable_apu_power_setting[] = {
+	{0x1508, 0x0, 0x3, 0},
+	{0x1f08, 0x0, 0x3, 0},
+};
+
 void mt6359p_init_setting(void)
 {
 	for (size_t i = 0; i < ARRAY_SIZE(init_setting); i++)
 		mt6359p_write_field(init_setting[i].addr, init_setting[i].val,
 			init_setting[i].mask, init_setting[i].shift);
+
+	if (get_cpu_id() == MTK_CPU_ID_MT8189 &&
+	    get_cpu_segment_id() == MTK_CPU_SEG_ID_MT8189G)
+		for (int i = 0; i < ARRAY_SIZE(disable_apu_power_setting); i++)
+			mt6359p_write_field(disable_apu_power_setting[i].addr,
+					    disable_apu_power_setting[i].val,
+					    disable_apu_power_setting[i].mask,
+					    disable_apu_power_setting[i].shift);
 }
 
 void mt6359p_lp_setting(void)

From 49219f1ce16cce14284212c24c55076e305d9f99 Mon Sep 17 00:00:00 2001
From: Nicholas Chin <nic.c3.14@gmail.com>
Date: Wed, 30 Jul 2025 20:32:23 -0600
Subject: [PATCH 1734/3886] Docs: Use markdown autolinks instead of Sphinx doc
 directive

Several files use embedded reStructuredText blocks in order to use the
:doc: directive to reference other markdown files using a relative path.
MyST Parser supports a similar feature using the standard Markdown
autolink (angled bracket) syntax, so use this instead as it is cleaner.
Both methods use the first heading of the linked file as the text shown
in the reference, though MyST Parser also supports the standard [link
text](../path/to/file.md) syntax to explicitly set the link text.

Note that when using the autolink syntax, `project:` must be prepended
to the relative path as it expects a URI scheme for all autolinks. This
is not required when using the separate text and URI syntax.

Before:
    ```{eval-rst}
    Example text :doc:`../relative/path`.
    ```

After:
    Example text <project:../relative/path.md>

Using the Markdown syntax also avoids formatting issues if any plain
text in the eval-rst block uses Markdown formatting syntax where they
would unintentionally be parsed differently due to text being parsed as
reStructuredText.

Some :doc: instances still remain as they are used within reST style
tables in an eval-rst block, so these were left as is since the Markdown
syntax would be invalid in that context.

[1]: https://myst-parser.readthedocs.io/en/latest/syntax/cross-referencing.html#autolinks

Change-Id: I8828bf7efe13de6d6f628f6b64151fbd25289fa5
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88618
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
---
 Documentation/getting_started/build_system.md |  4 +---
 Documentation/mainboard/acer/g43t-am3.md      |  4 +---
 Documentation/mainboard/asrock/h77pro4-m.md   |  4 +---
 Documentation/mainboard/asrock/h81m-hds.md    |  9 +++-----
 .../mainboard/gigabyte/ga-g41m-es2l.md        |  8 ++-----
 .../mainboard/hp/compaq_8300_usdt.md          |  3 ++-
 Documentation/mainboard/intel/dq67sw.md       |  8 ++-----
 .../mainboard/lenovo/Ivy_Bridge_series.md     |  4 +---
 .../mainboard/supermicro/x10slm-f.md          | 22 +++++--------------
 .../northbridge/intel/haswell/known-issues.md |  4 +---
 10 files changed, 20 insertions(+), 50 deletions(-)

diff --git a/Documentation/getting_started/build_system.md b/Documentation/getting_started/build_system.md
index 4c91f436ec..1816787949 100644
--- a/Documentation/getting_started/build_system.md
+++ b/Documentation/getting_started/build_system.md
@@ -75,9 +75,7 @@ $(call add_intermediate, add_mrc_data)
 
 Note that the second line must start with a tab, not spaces.
 
-```{eval-rst}
-See also :doc:`../tutorial/managing_local_additions`.
-```
+See also <project:../tutorial/managing_local_additions.md>.
 
 #### FMAP region support
 With the addition of FMAP flash partitioning support to coreboot, there was a
diff --git a/Documentation/mainboard/acer/g43t-am3.md b/Documentation/mainboard/acer/g43t-am3.md
index 79aa8ffd5f..b290871283 100644
--- a/Documentation/mainboard/acer/g43t-am3.md
+++ b/Documentation/mainboard/acer/g43t-am3.md
@@ -122,10 +122,8 @@ $ sudo flashrom \
   -w coreboot.rom
 ```
 
-```{eval-rst}
 In addition to the information here, please see the
-:doc:`../../tutorial/flashing_firmware/index`.
-```
+<project:../../tutorial/flashing_firmware/index.md>.
 
 ### External flashing
 
diff --git a/Documentation/mainboard/asrock/h77pro4-m.md b/Documentation/mainboard/asrock/h77pro4-m.md
index 5ad4479fdb..1f285acaea 100644
--- a/Documentation/mainboard/asrock/h77pro4-m.md
+++ b/Documentation/mainboard/asrock/h77pro4-m.md
@@ -115,10 +115,8 @@ $ sudo flashrom --noverify-all --ifd -i bios -p internal -w coreboot.rom
 The use of `--noverify-all` is required since the Management Engine
 region is not readable even by the host.
 
-```{eval-rst}
 In addition to the information here, please see the
-:doc:`../../tutorial/flashing_firmware/index`.
-```
+<project:../../tutorial/flashing_firmware/index.md>.
 
 ## Hardware monitoring and fan control
 
diff --git a/Documentation/mainboard/asrock/h81m-hds.md b/Documentation/mainboard/asrock/h81m-hds.md
index 0ba17b2735..632c1562f9 100644
--- a/Documentation/mainboard/asrock/h81m-hds.md
+++ b/Documentation/mainboard/asrock/h81m-hds.md
@@ -4,9 +4,7 @@ This page describes how to run coreboot on the [ASRock H81M-HDS].
 
 ## Required proprietary blobs
 
-```{eval-rst}
-Please see :doc:`../../northbridge/intel/haswell/mrc.bin`.
-```
+Please see <project:../../northbridge/intel/haswell/mrc.bin.md>.
 
 ## Building coreboot
 
@@ -75,9 +73,8 @@ facing towards the bottom of the board.
   in coreboot. The `coretemp` driver can still be used for accurate CPU
   temperature readings from an OS.
 
-```{eval-rst}
-Please also see :doc:`../../northbridge/intel/haswell/known-issues`.
-```
+Please also see
+<project:../../northbridge/intel/haswell/known-issues.md>.
 
 ## Untested
 
diff --git a/Documentation/mainboard/gigabyte/ga-g41m-es2l.md b/Documentation/mainboard/gigabyte/ga-g41m-es2l.md
index b42cd81fd4..07c39271a6 100644
--- a/Documentation/mainboard/gigabyte/ga-g41m-es2l.md
+++ b/Documentation/mainboard/gigabyte/ga-g41m-es2l.md
@@ -30,9 +30,7 @@ This motherboard [also works with Libreboot](https://libreboot.org/docs/install/
 
 ## Preparation
 
-```{eval-rst}
-For more datails how to get sources and build the toolchain, see :doc:`../../tutorial/part1`.
-```
+For more datails how to get sources and build the toolchain, see <project:../../tutorial/part1.md>.
 
 ### Devuan 4 Chimaera
 
@@ -140,10 +138,8 @@ Built gigabyte/ga-g41m-es2l (GA-G41M-ES2L)
 
 ## Flashing coreboot
 
-```{eval-rst}
 In addition to the information here, please see the
-:doc:`../../tutorial/flashing_firmware/index`.
-```
+<project:../../tutorial/flashing_firmware/index.md>.
 
 ### Do backup
 
diff --git a/Documentation/mainboard/hp/compaq_8300_usdt.md b/Documentation/mainboard/hp/compaq_8300_usdt.md
index 4c2989a3a5..eaa8f4c2e8 100644
--- a/Documentation/mainboard/hp/compaq_8300_usdt.md
+++ b/Documentation/mainboard/hp/compaq_8300_usdt.md
@@ -59,7 +59,8 @@ Wake on LAN is active works great.
 ### SuperIO
 
 This board has a Nuvoton NPCD379 SuperIO chip. Fan speed and PS/2 keyboard work
-fine using coreboot's existing code for :doc:`../../superio/nuvoton/npcd378`.
+fine using coreboot's existing code for
+<project:../../superio/nuvoton/npcd378.md>.
 
 [Compaq Elite 8300 USDT]: https://support.hp.com/gb-en/product/hp-compaq-elite-8300-ultra-slim-pc/5232866
 [HP]: https://www.hp.com/
diff --git a/Documentation/mainboard/intel/dq67sw.md b/Documentation/mainboard/intel/dq67sw.md
index d641fc633b..dc79e04ede 100644
--- a/Documentation/mainboard/intel/dq67sw.md
+++ b/Documentation/mainboard/intel/dq67sw.md
@@ -104,11 +104,9 @@ the PCI configuration space of the LPC Interface Bridge, is set.
 It is possible to program the chip is to attach an external programmer
 with an SOIC-8 clip.
 
-```{eval-rst}
 Another way is to boot the vendor firmware in UEFI mode and exploit the
 unpatched S3 Boot Script vulnerability. See this page for a similar procedure:
-:doc:`../lenovo/ivb_internal_flashing`.
-```
+<project:../lenovo/ivb_internal_flashing.md>.
 
 On this specific board it is possible to prevent the BLE bit from being set
 when it resumes from S3. One entry in the S3 Boot Script must be modified,
@@ -126,12 +124,10 @@ The boot script contains an entry that writes 0x02 to memory at address
 Interface Bridge [0][1]. The value 0x02 sets the BLE bit, and the modification
 prevents this by making it write a 0 instead.
 
-```{eval-rst}
 After suspending and resuming the board, the BIOS region can be flashed with
 a coreboot image, e.g. using flashrom. Note that the ME region is not readable,
 so the `--noverify-all` flag is necessary. Please refer to the
-:doc:`../../tutorial/flashing_firmware/index`.
-```
+<project:../../tutorial/flashing_firmware/index.md>.
 
 ## Hardware monitoring and fan control
 
diff --git a/Documentation/mainboard/lenovo/Ivy_Bridge_series.md b/Documentation/mainboard/lenovo/Ivy_Bridge_series.md
index a7893e7ad3..001a1ccfc3 100644
--- a/Documentation/mainboard/lenovo/Ivy_Bridge_series.md
+++ b/Documentation/mainboard/lenovo/Ivy_Bridge_series.md
@@ -37,9 +37,7 @@ This information is valid for all supported models, except T430s, [T431s](t431s.
   exceed 4MiB in size, which means CONFIG_CBFS_SIZE must be smaller than 4MiB.
 * ROM chip size should be set to 12MiB.
 
-```{eval-rst}
-Please also have a look at :doc:`../../tutorial/flashing_firmware/index`.
-```
+Please also have a look at <project:../../tutorial/flashing_firmware/index.md>.
 
 ## Splitting the coreboot.rom
 
diff --git a/Documentation/mainboard/supermicro/x10slm-f.md b/Documentation/mainboard/supermicro/x10slm-f.md
index 27bf6b4340..c389217b34 100644
--- a/Documentation/mainboard/supermicro/x10slm-f.md
+++ b/Documentation/mainboard/supermicro/x10slm-f.md
@@ -4,16 +4,12 @@ This section details how to run coreboot on the [Supermicro X10SLM+-F].
 
 ## Required proprietary blobs
 
-```{eval-rst}
-Please see :doc:`../../northbridge/intel/haswell/mrc.bin`.
-```
+Please see <project:../../northbridge/intel/haswell/mrc.bin.md>.
 
 ## Building coreboot
 
-```{eval-rst}
 If you haven't already, build the coreboot toolchain as described in
-:doc:`../../tutorial/part1`.
-```
+<project:../../tutorial/part1.md>.
 
 A fully working image should be possible so long as you have the
 Haswell `mrc.bin` file. You can set the basic config with the following
@@ -40,10 +36,8 @@ Now, run `make` to build the coreboot image.
 
 ## Flashing coreboot
 
-```{eval-rst}
 In addition to the information here, please see the
-:doc:`../../tutorial/flashing_firmware/index`.
-```
+<project:../../tutorial/flashing_firmware/index.md>.
 
 ### Internal programming
 
@@ -119,11 +113,8 @@ eventually start. There is no such delay when running coreboot.
 
 ## ECC DRAM
 
-```{eval-rst}
 ECC DRAM seems to work, but please see
-:doc:`../../northbridge/intel/haswell/mrc.bin`
-for caveats.
-```
+<project:../../northbridge/intel/haswell/mrc.bin.md> for caveats.
 
 ## Known issues
 
@@ -139,9 +130,8 @@ for caveats.
   in coreboot. The `coretemp` driver can still be used for accurate CPU
   temperature readings from an OS, and hence the OS can do fan control.
 
-```{eval-rst}
-Please also see :doc:`../../northbridge/intel/haswell/known-issues`.
-```
+Please also see
+<project:../../northbridge/intel/haswell/known-issues.md>.
 
 ## Untested
 
diff --git a/Documentation/northbridge/intel/haswell/known-issues.md b/Documentation/northbridge/intel/haswell/known-issues.md
index e049a948e1..3c299d6620 100644
--- a/Documentation/northbridge/intel/haswell/known-issues.md
+++ b/Documentation/northbridge/intel/haswell/known-issues.md
@@ -5,11 +5,9 @@ mainboard, there might be additional issues to those listed here.
 
 ## PCIe graphics
 
-```{eval-rst}
 Using a PCIe graphics card for display output is not currently
-supported. This is because :doc:`./mrc.bin` requires workarounds to
+supported. This is because <project:mrc.bin.md> requires workarounds to
 have such a feature working correctly.
-```
 
 However, there is a [patch on Gerrit][hsw-gfx-gerrit] that allows PCIe
 graphics to be used for display output. This patch is not guaranteed to

From 227d434e2dcd49047994f7d131e5af63aa301aed Mon Sep 17 00:00:00 2001
From: Ian Feng <ian_feng@compal.corp-partner.google.com>
Date: Mon, 28 Jul 2025 16:26:02 +0800
Subject: [PATCH 1735/3886] drivers/soundwire/alc711: Support clock stop flag
 from devicetree

Allow overriding the default value (true) via devicetree configuration.
If disable_clkstop_sm_support is set in the devicetree,
the corresponding field in alc711_slave is set to false.

BUG=b:417133565, b:420516709
TEST=Verified build and boot with ALC721 and ALC722.
Headphone path switches successfully via audio jack event.
Confirmed SSDT dump at PCI0.HDAS.SNDW.
Package (0x02)
{
    "mipi-sdw-simplified-clockstopprepare-sm-supported",
    Zero
},

Change-Id: If958cd0c2136e4dd3f60cb9203d9394913d3f66e
Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88586
Reviewed-by: Mac Chiang <mac.chiang@intel.com>
Reviewed-by: Simon Yang <simon1.yang@intel.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/drivers/soundwire/alc711/alc711.c | 4 ++++
 src/drivers/soundwire/alc711/chip.h   | 1 +
 2 files changed, 5 insertions(+)

diff --git a/src/drivers/soundwire/alc711/alc711.c b/src/drivers/soundwire/alc711/alc711.c
index c698000266..dc738405ad 100644
--- a/src/drivers/soundwire/alc711/alc711.c
+++ b/src/drivers/soundwire/alc711/alc711.c
@@ -131,6 +131,10 @@ static void soundwire_alc711_fill_ssdt(const struct device *dev)
 		/* Currently only 1 audio mode is supported. */
 		memcpy(&alc711_audio_mode, &config->audio_mode, sizeof(struct soundwire_audio_mode));
 
+	/* Override the default (true) if disable_clkstop_sm_support is set in the devicetree. */
+	if (config->disable_clkstop_sm_support)
+		alc711_slave.simplified_clockstopprepare_sm_supported = false;
+
 	dsd = acpi_dp_new_table("_DSD");
 	soundwire_gen_codec(dsd, &alc711_codec, NULL);
 	acpi_dp_write(dsd);
diff --git a/src/drivers/soundwire/alc711/chip.h b/src/drivers/soundwire/alc711/chip.h
index 8b0230e6d1..26aaffafa4 100644
--- a/src/drivers/soundwire/alc711/chip.h
+++ b/src/drivers/soundwire/alc711/chip.h
@@ -7,6 +7,7 @@
 #include <mipi/ids.h>
 
 struct drivers_soundwire_alc711_config {
+	bool disable_clkstop_sm_support;
 	const char *name;
 	const char *desc;
 	struct soundwire_address alc711_address;

From a23be7a6fe128dc186c22ec9b295c8e62ec435e5 Mon Sep 17 00:00:00 2001
From: Ian Feng <ian_feng@compal.corp-partner.google.com>
Date: Mon, 28 Jul 2025 16:46:38 +0800
Subject: [PATCH 1736/3886] mb/google/fatcat/var/francka: Disable ALC721 &
 ALC722 clock stop support

This change allows flag to be override via devicetree,
instead of relying on the default value in alc711_slave.
It helps fix the missing event issue when plugging or
unplugging the 3.5mm headphone jack.

BUG=b:417133565, b:420516709
TEST=Verified build and boot with ALC721 and ALC722.
Headphone path switches successfully via audio jack event.
Confirmed SSDT dump at PCI0.HDAS.SNDW.
Package (0x02)
{
    "mipi-sdw-simplified-clockstopprepare-sm-supported",
    Zero
},

Change-Id: I975ed83e8614bd88861f115ffeea7c2450e6a432
Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88587
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Mac Chiang <mac.chiang@intel.com>
---
 src/mainboard/google/fatcat/variants/francka/overridetree.cb | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/src/mainboard/google/fatcat/variants/francka/overridetree.cb b/src/mainboard/google/fatcat/variants/francka/overridetree.cb
index 342a23da17..68e3b6635a 100644
--- a/src/mainboard/google/fatcat/variants/francka/overridetree.cb
+++ b/src/mainboard/google/fatcat/variants/francka/overridetree.cb
@@ -297,6 +297,7 @@ chip soc/intel/pantherlake
 						register "alc711_address.version" = "SOUNDWIRE_VERSION_1_2"
 						register "alc711_address.class" = "MIPI_CLASS_SDCA"
 						register "alc711_address.part_id" = "MIPI_DEV_ID_REALTEK_ALC721"
+						register "disable_clkstop_sm_support" = "true"
 						# SoundWire Link 0 ID 0
 						device generic 0.0 on
 							probe AUDIO AUDIO_ALC721_SNDW
@@ -307,6 +308,7 @@ chip soc/intel/pantherlake
 						register "alc711_address.version" = "SOUNDWIRE_VERSION_1_2"
 						register "alc711_address.class" = "MIPI_CLASS_SDCA"
 						register "alc711_address.part_id" = "MIPI_DEV_ID_REALTEK_ALC722"
+						register "disable_clkstop_sm_support" = "true"
 						# SoundWire Link 0 ID 0
 						device generic 0.0 on
 							probe AUDIO AUDIO_ALC722_ALC1320_SNDW

From 87c9bb39945bba0e52cc8c2abaeead361837a705 Mon Sep 17 00:00:00 2001
From: Jeremy Soller <jeremy@system76.com>
Date: Wed, 10 May 2023 14:14:07 -0600
Subject: [PATCH 1737/3886] soc/intel/adl: Fill in SPD data on both channels of
 DDR5 memory

Commit 91a1276d532b ("soc/intel/alderlake: Implement WA for DDR5 DIMM
modules") was added to allow FSP to perform the SPD read for DDR5
modules since coreboot did not properly support reading SPD from
EEPROM for DDR5.

Now that DDR5 SPD EEPROM reading has been fixed in commit e9cb352706c1
("soc/common/smbus: Support reading SPD5 hubs for DDR5"), remove the
now unneeded workaround for DDR5 and use coreboot's SPD read as we
do for all other module types.

Change-Id: I5a92199a7cd2718e9396f0dac8257df40e4f834c
Signed-off-by: Jeremy Soller <jeremy@system76.com>
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75284
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
---
 src/soc/intel/alderlake/meminit.c | 79 +++++++------------------------
 1 file changed, 18 insertions(+), 61 deletions(-)

diff --git a/src/soc/intel/alderlake/meminit.c b/src/soc/intel/alderlake/meminit.c
index 6b3143eadd..f7f8ef7d9e 100644
--- a/src/soc/intel/alderlake/meminit.c
+++ b/src/soc/intel/alderlake/meminit.c
@@ -118,7 +118,8 @@ static const struct soc_mem_cfg soc_mem_cfg[] = {
 	},
 };
 
-static void mem_init_spd_upds(FSP_M_CONFIG *mem_cfg, const struct mem_channel_data *data)
+static void mem_init_spd_upds(FSP_M_CONFIG *mem_cfg, const struct mem_channel_data *data,
+				bool expand_channels)
 {
 	uint32_t *spd_upds[MRC_CHANNELS][CONFIG_DIMMS_PER_CHANNEL] = {
 		[0] = { &mem_cfg->MemorySpdPtr000, &mem_cfg->MemorySpdPtr001, },
@@ -151,7 +152,19 @@ static void mem_init_spd_upds(FSP_M_CONFIG *mem_cfg, const struct mem_channel_da
 		for (dimm = 0; dimm < CONFIG_DIMMS_PER_CHANNEL; dimm++) {
 			uint32_t *spd_ptr = spd_upds[ch][dimm];
 
-			*spd_ptr = data->spd[ch][dimm];
+			/*
+			 * In DDR5 systems, since each DIMM has 2 channels,
+			 * we need to copy the SPD data such that:
+			 * Channel 0 data is used by channel 0 and 1
+			 * Channel 2 data is used by channel 2 and 3
+			 * Channel 4 data is used by channel 4 and 5
+			 * Channel 6 data is used by channel 6 and 7
+			 */
+			if (expand_channels)
+				*spd_ptr = data->spd[ch & ~1][dimm];
+			else
+				*spd_ptr = data->spd[ch][dimm];
+
 			if (*spd_ptr)
 				enable_channel = 1;
 		}
@@ -217,60 +230,12 @@ static void mem_init_dqs_upds(FSP_M_CONFIG *mem_cfg, const struct mem_channel_da
 	mem_init_dq_dqs_upds(dqs_upds, mb_cfg->dqs_map, upd_size, data, auto_detect);
 }
 
-#define DDR5_CH_DIMM_OFFSET(ch, dimm)        ((ch) * CONFIG_DIMMS_PER_CHANNEL + (dimm))
-
-static void ddr5_fill_dimm_module_info(FSP_M_CONFIG *mem_cfg, const struct mb_cfg *mb_cfg,
-						 const struct mem_spd *spd_info)
-{
-	for (size_t ch = 0; ch < soc_mem_cfg[MEM_TYPE_DDR5].num_phys_channels; ch++) {
-		for (size_t dimm = 0; dimm < CONFIG_DIMMS_PER_CHANNEL; dimm++) {
-			size_t mrc_ch = soc_mem_cfg[MEM_TYPE_DDR5].phys_to_mrc_map[ch];
-			mem_cfg->SpdAddressTable[DDR5_CH_DIMM_OFFSET(mrc_ch, dimm)] =
-				spd_info->smbus[ch].addr_dimm[dimm] << 1;
-		}
-	}
-	mem_init_dq_upds(mem_cfg, NULL, mb_cfg, true);
-	mem_init_dqs_upds(mem_cfg, NULL, mb_cfg, true);
-}
-
-/*
- * A memory channel will be disabled if corresponding bit in
- * ch_disable_mask is set.
- */
-static void mem_init_override_channel_mask(FSP_M_CONFIG *mem_cfg)
-{
-	uint8_t *disable_channel_upds[MRC_CHANNELS] = {
-		&mem_cfg->DisableMc0Ch0,
-		&mem_cfg->DisableMc0Ch1,
-		&mem_cfg->DisableMc0Ch2,
-		&mem_cfg->DisableMc0Ch3,
-		&mem_cfg->DisableMc1Ch0,
-		&mem_cfg->DisableMc1Ch1,
-		&mem_cfg->DisableMc1Ch2,
-		&mem_cfg->DisableMc1Ch3,
-	};
-
-	uint8_t ch_disable_mask = mb_get_channel_disable_mask();
-	if (ch_disable_mask == 0)
-		return;
-
-	/* Mc0Ch0 cannot be disabled */
-	if (ch_disable_mask & BIT(0)) {
-		printk(BIOS_ERR, "Cannot disable the first memory channel (Mc0Ch0).\n");
-		return;
-	}
-
-	for (size_t ch = 0; ch < MRC_CHANNELS; ch++) {
-		if (ch_disable_mask & BIT(ch))
-			*disable_channel_upds[ch] = 1;
-	}
-}
-
 void memcfg_init(FSPM_UPD *memupd, const struct mb_cfg *mb_cfg,
 		 const struct mem_spd *spd_info, bool half_populated)
 {
 	struct mem_channel_data data;
 	bool dq_dqs_auto_detect = false;
+	bool expand_channels = false;
 	FSP_M_CONFIG *mem_cfg = &memupd->FspmConfig;
 
 #if CONFIG(SOC_INTEL_RAPTORLAKE) && !CONFIG(FSP_USE_REPO)
@@ -294,14 +259,7 @@ void memcfg_init(FSPM_UPD *memupd, const struct mb_cfg *mb_cfg,
 	case MEM_TYPE_DDR5:
 		meminit_ddr(mem_cfg, &mb_cfg->ddr_config);
 		dq_dqs_auto_detect = true;
-		/*
-		* TODO: Drop this workaround once SMBus driver in coreboot is updated to
-		* support DDR5 EEPROM reading.
-		*/
-		if (spd_info->topo == MEM_TOPO_DIMM_MODULE) {
-			ddr5_fill_dimm_module_info(mem_cfg, mb_cfg, spd_info);
-			return;
-		}
+		expand_channels = true;
 		break;
 	case MEM_TYPE_LP4X:
 		meminit_lp4x(mem_cfg);
@@ -315,8 +273,7 @@ void memcfg_init(FSPM_UPD *memupd, const struct mb_cfg *mb_cfg,
 
 	mem_populate_channel_data(memupd, &soc_mem_cfg[mb_cfg->type], spd_info, half_populated,
 			&data);
-	mem_init_spd_upds(mem_cfg, &data);
-	mem_init_override_channel_mask(mem_cfg);
+	mem_init_spd_upds(mem_cfg, &data, expand_channels);
 	mem_init_dq_upds(mem_cfg, &data, mb_cfg, dq_dqs_auto_detect);
 	mem_init_dqs_upds(mem_cfg, &data, mb_cfg, dq_dqs_auto_detect);
 }

From 0da943ed99399f820352bc4c5ccb7f925bbb5d68 Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Fri, 1 Aug 2025 09:21:51 -0400
Subject: [PATCH 1738/3886] soc/intel/meteorlake: Fix DDR5 channel mapping

This patch applies commit 0e7cf3d81d12 ("soc/intel/alderlake: Fix DDR5
channel mapping") to Meteor Lake.

DDR5 memory modules have two separate 32-bit channels (40-bit on ECC
memory modules), and the SPD info refers to one channel: the primary
bus width is 32 (or 40) bits and the "DIMM size" is halved. On Meteor
Lake, there are 2 memory controllers with 4 32-bit channels each for
DDR5. FSP has 16 positions to store SPD data, some of which are only
used with LPDDR4/LPDDR5.

To try to make things less confusing, FSP abstracts the DDR5 channels
so that the configuration works like on DDR4. This is done by copying
each DIMM's SPD data to the other half-channel. Thus, fix the wrapper
parameters for DDR5 accordingly.

Change-Id: I00cd1fba855a50422a68fa662df4ca8ed2c6458d
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88636
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/soc/intel/meteorlake/meminit.c | 14 ++++++--------
 1 file changed, 6 insertions(+), 8 deletions(-)

diff --git a/src/soc/intel/meteorlake/meminit.c b/src/soc/intel/meteorlake/meminit.c
index dae175fd1a..7eea82b4f0 100644
--- a/src/soc/intel/meteorlake/meminit.c
+++ b/src/soc/intel/meteorlake/meminit.c
@@ -38,18 +38,16 @@ static const struct soc_mem_cfg soc_mem_cfg[] = {
 		.num_phys_channels = DDR5_CHANNELS,
 		.phys_to_mrc_map = {
 			[0] = 0,
-			[1] = 1,
-			[2] = 4,
-			[3] = 5,
+			[1] = 4,
 		},
 		.md_phy_masks = {
 			/*
-			 * Physical channels 0 and 1 are populated in case of
-			 * half-populated configurations.
+			 * Only channel 0 is populated in case of half-populated
+			 * configuration.
 			 */
-			.half_channel = BIT(0) | BIT(1),
-			/* In mixed topologies, channels 2 and 3 are always memory-down. */
-			.mixed_topo = BIT(2) | BIT(3),
+			.half_channel = BIT(0),
+			/* In mixed topologies, either channel 0 or 1 can be memory-down. */
+			.mixed_topo = BIT(0) | BIT(1),
 		},
 	},
 	[MEM_TYPE_LP5X] = {

From 910f1118913393828754da9f6a7415a9030cc2a5 Mon Sep 17 00:00:00 2001
From: Jeremy Soller <jackpot51@gmail.com>
Date: Thu, 7 Mar 2024 09:48:42 -0700
Subject: [PATCH 1739/3886] soc/intel/mtl: Fill in SPD data on both channels of
 DDR5 memory

Commit 91a1276d532b ("soc/intel/alderlake: Implement WA for DDR5 DIMM
modules") was added to allow FSP to perform the SPD read for DDR5
modules since coreboot did not properly support reading SPD from
EEPROM for DDR5. The same code was copied for Meteorlake.

Now that DDR5 SPD EEPROM reading has been fixed in commit e9cb352706c1
("soc/common/smbus: Support reading SPD5 hubs for DDR5"), remove the
now unneeded workaround for DDR5 and use coreboot's SPD read as we
do for all other module types.

Change-Id: I600d8fd480cb84d5dcb679e4f0bdeeaaebfab386
Signed-off-by: Jeremy Soller <jeremy@system76.com>
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82733
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/soc/intel/meteorlake/meminit.c | 49 ++++++++++++------------------
 1 file changed, 20 insertions(+), 29 deletions(-)

diff --git a/src/soc/intel/meteorlake/meminit.c b/src/soc/intel/meteorlake/meminit.c
index 7eea82b4f0..f4cde7e168 100644
--- a/src/soc/intel/meteorlake/meminit.c
+++ b/src/soc/intel/meteorlake/meminit.c
@@ -73,7 +73,8 @@ static const struct soc_mem_cfg soc_mem_cfg[] = {
 	},
 };
 
-static void mem_init_spd_upds(FSP_M_CONFIG *mem_cfg, const struct mem_channel_data *data)
+static void mem_init_spd_upds(FSP_M_CONFIG *mem_cfg, const struct mem_channel_data *data,
+				bool expand_channels)
 {
 	efi_uintn_t *spd_upds[MRC_CHANNELS][CONFIG_DIMMS_PER_CHANNEL] = {
 		[0] = { &mem_cfg->MemorySpdPtr000, &mem_cfg->MemorySpdPtr001, },
@@ -106,7 +107,19 @@ static void mem_init_spd_upds(FSP_M_CONFIG *mem_cfg, const struct mem_channel_da
 		for (dimm = 0; dimm < CONFIG_DIMMS_PER_CHANNEL; dimm++) {
 			efi_uintn_t *spd_ptr = spd_upds[ch][dimm];
 
-			*spd_ptr = data->spd[ch][dimm];
+			/*
+			 * In DDR5 systems, since each DIMM has 2 channels,
+			 * we need to copy the SPD data such that:
+			 * Channel 0 data is used by channel 0 and 1
+			 * Channel 2 data is used by channel 2 and 3
+			 * Channel 4 data is used by channel 4 and 5
+			 * Channel 6 data is used by channel 6 and 7
+			 */
+			if (expand_channels)
+				*spd_ptr = data->spd[ch & ~1][dimm];
+			else
+				*spd_ptr = data->spd[ch][dimm];
+
 			if (*spd_ptr)
 				enable_channel = 1;
 		}
@@ -172,27 +185,12 @@ static void mem_init_dqs_upds(FSP_M_CONFIG *mem_cfg, const struct mem_channel_da
 	mem_init_dq_dqs_upds(dqs_upds, mb_cfg->dqs_map, upd_size, data, auto_detect);
 }
 
-#define DDR5_CH_DIMM_OFFSET(ch, dimm)        ((ch) * CONFIG_DIMMS_PER_CHANNEL + (dimm))
-
-static void ddr5_fill_dimm_module_info(FSP_M_CONFIG *mem_cfg, const struct mb_cfg *mb_cfg,
-					const struct mem_spd *spd_info)
-{
-	for (size_t ch = 0; ch < soc_mem_cfg[MEM_TYPE_DDR5].num_phys_channels; ch++) {
-		for (size_t dimm = 0; dimm < CONFIG_DIMMS_PER_CHANNEL; dimm++) {
-			size_t mrc_ch = soc_mem_cfg[MEM_TYPE_DDR5].phys_to_mrc_map[ch];
-			mem_cfg->SpdAddressTable[DDR5_CH_DIMM_OFFSET(mrc_ch, dimm)] =
-				spd_info->smbus[ch].addr_dimm[dimm] << 1;
-		}
-	}
-	mem_init_dq_upds(mem_cfg, NULL, mb_cfg, true);
-	mem_init_dqs_upds(mem_cfg, NULL, mb_cfg, true);
-}
-
 void memcfg_init(FSPM_UPD *memupd, const struct mb_cfg *mb_cfg,
 		 const struct mem_spd *spd_info, bool half_populated)
 {
 	struct mem_channel_data data;
 	bool dq_dqs_auto_detect = false;
+	bool expand_channels = false;
 	FSP_M_CONFIG *mem_cfg = &memupd->FspmConfig;
 
 	mem_cfg->ECT = mb_cfg->ect;
@@ -203,14 +201,7 @@ void memcfg_init(FSPM_UPD *memupd, const struct mb_cfg *mb_cfg,
 	case MEM_TYPE_DDR5:
 		meminit_ddr(mem_cfg, &mb_cfg->ddr_config);
 		dq_dqs_auto_detect = true;
-		/*
-		* TODO: Drop this workaround once SMBus driver in coreboot is updated to
-		* support DDR5 EEPROM reading.
-		*/
-		if (spd_info->topo == MEM_TOPO_DIMM_MODULE) {
-			ddr5_fill_dimm_module_info(mem_cfg, mb_cfg, spd_info);
-			return;
-		}
+		expand_channels = true;
 		break;
 	case MEM_TYPE_LP5X:
 		meminit_lp5x(mem_cfg, &mb_cfg->lp5x_config);
@@ -219,9 +210,9 @@ void memcfg_init(FSPM_UPD *memupd, const struct mb_cfg *mb_cfg,
 		die("Unsupported memory type(%d)\n", mb_cfg->type);
 	}
 
-	mem_populate_channel_data(memupd, &soc_mem_cfg[mb_cfg->type], spd_info,
-					 half_populated, &data);
-	mem_init_spd_upds(mem_cfg, &data);
+	mem_populate_channel_data(memupd, &soc_mem_cfg[mb_cfg->type], spd_info, half_populated,
+			&data);
+	mem_init_spd_upds(mem_cfg, &data, expand_channels);
 	mem_init_dq_upds(mem_cfg, &data, mb_cfg, dq_dqs_auto_detect);
 	mem_init_dqs_upds(mem_cfg, &data, mb_cfg, dq_dqs_auto_detect);
 }

From 1e11bda5d0c9165a7ea593ba1d1700333afd5ae0 Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Mon, 21 Jul 2025 16:54:54 -0500
Subject: [PATCH 1740/3886] soc/intel/cmn/smbus: Drop use of update_spd_len()

It doesn't make sense to use CONFIG_DIMM_SPD_SIZE to determine the
amount of data to read from the SPD, then override that value.

Clean up the mess and simply set the SPD length fror the spd_block
struct to CONFIG_DIMM_SPD_SIZE.

Change-Id: Ifec6cf1f6d7c931131460ea72440aa236590d0b6
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88523
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/soc/intel/common/block/smbus/smbuslib.c | 19 +------------------
 1 file changed, 1 insertion(+), 18 deletions(-)

diff --git a/src/soc/intel/common/block/smbus/smbuslib.c b/src/soc/intel/common/block/smbus/smbuslib.c
index f7ec63772f..e2955f9c0b 100644
--- a/src/soc/intel/common/block/smbus/smbuslib.c
+++ b/src/soc/intel/common/block/smbus/smbuslib.c
@@ -9,23 +9,6 @@
 #include <device/smbus_host.h>
 #include "smbuslib.h"
 
-static void update_spd_len(struct spd_block *blk)
-{
-	u8 i, j = 0;
-	for (i = 0 ; i < CONFIG_DIMM_MAX; i++)
-		if (blk->spd_array[i] != NULL)
-			j |= blk->spd_array[i][SPD_MEMORY_TYPE];
-
-	/* If spd used is DDR5, then its length is 1024 byte. */
-	if (j == SPD_MEMORY_TYPE_DDR5_SDRAM)
-		blk->len = CONFIG_DIMM_SPD_SIZE;
-	/* If spd used is DDR4, then its length is 512 byte. */
-	else if (j == SPD_MEMORY_TYPE_DDR4_SDRAM)
-		blk->len = SPD_SIZE_MAX_DDR4;
-	else
-		blk->len = SPD_SIZE_MAX_DDR3;
-}
-
 static void spd_read(u8 *spd, u8 addr)
 {
 	u16 i;
@@ -164,7 +147,7 @@ void get_spd_smbus(struct spd_block *blk)
 			blk->spd_array[i] = NULL;
 	}
 
-	update_spd_len(blk);
+	blk->len = CONFIG_DIMM_SPD_SIZE;
 }
 
 /*

From b0d2d522eae5455f7491e30a60a7b1d74454bdb6 Mon Sep 17 00:00:00 2001
From: Subrata Banik <subratabanik@google.com>
Date: Thu, 31 Jul 2025 23:47:45 +0530
Subject: [PATCH 1741/3886] soc/qualcomm/x1p42100: Enable bootblock compression

Enable bootblock compression on the X1p42100 SoC to decrease boot
time by 10-20 ms.

This change helps to reduce the size of the bootblock, allowing it
to be loaded and decompressed faster, which improves overall boot
performance.

TEST=Able to build and boot google/quenbi.

Change-Id: I81cdbec4a05c8abacae39ff208cc0f7469206161
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88626
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/soc/qualcomm/x1p42100/Kconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/src/soc/qualcomm/x1p42100/Kconfig b/src/soc/qualcomm/x1p42100/Kconfig
index 826df95372..e65047e82b 100644
--- a/src/soc/qualcomm/x1p42100/Kconfig
+++ b/src/soc/qualcomm/x1p42100/Kconfig
@@ -12,6 +12,7 @@ config SOC_QUALCOMM_X1P42100
 	select CACHE_MRC_SETTINGS
 	select COMMONLIB_STORAGE
 	select COMMONLIB_STORAGE_SD
+	select COMPRESS_BOOTBLOCK
 	select FIXED_UART_FOR_CONSOLE
 	select GENERIC_GPIO_LIB
 	select GENERIC_UDELAY

From 2c8d157ea4e07cce93e72b707e5659be701e75f3 Mon Sep 17 00:00:00 2001
From: Subrata Banik <subratabanik@google.com>
Date: Fri, 1 Aug 2025 15:38:58 +0530
Subject: [PATCH 1742/3886] {drivers, soc/qualcomm/common}: Add configurable
 delay for UART bitbang
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

This commit introduces a new Kconfig option, UART_BITBANG_TX_DELAY_MS,
to make the UART TX pin stabilization delay configurable.

A default 5ms (CONFIG_UART_BITBANG_TX_DELAY_MS) delay is added in
uart_init() after the TX pin is set high. This addresses an issue
where the initial character sent by the UART could be corrupted due
to the pin not being stable. The delay ensures the line state is
properly established before data transmission begins.

This was found to resolve early boot console corruption on some boards.
The issue is likely a race condition where the first character starts
transmitting before the GPIO output is fully stabilized.

TEST=Able to build and boot google/zombie w/o any junk characters in
AP firmware log.

w/o this patch:

```
�ɍ���щ�����х�ѥ��b����ٕ��Jrrrjjm              UuI5�ፕ�ѥ���������ͥ��х�����jm             UuI5���ѥ���ፕ�ѥ��m��jm           UuI5����ѕ�ѕፕ�ѥ��m��[DEBUG]  NCC Frequency bumped to 1.363(GHz)
```

w/ this patch:

```
[NOTE ]  coreboot-25.06-78-gfe786406960e-dirty Fri Aug 01 17:12:22 UTC 2025 aarch64 bootblock starting (log level: 8)...
[DEBUG]  ARM64: Exception handlers installed.
[DEBUG]  ARM64: Testing exception
[DEBUG]  ARM64: Done test exception
[DEBUG]  Silver Frequency bumped to 1.5168(GHz)
[DEBUG]  L3 Frequency bumped to 1.1904(GHz)
```

Change-Id: I33c9ea65aa42d23acf3b89f977d4985569c144e8
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88633
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/drivers/uart/Kconfig               | 8 ++++++++
 src/soc/qualcomm/common/uart_bitbang.c | 3 +++
 2 files changed, 11 insertions(+)

diff --git a/src/drivers/uart/Kconfig b/src/drivers/uart/Kconfig
index dcdd5bc170..f323d14be4 100644
--- a/src/drivers/uart/Kconfig
+++ b/src/drivers/uart/Kconfig
@@ -35,6 +35,14 @@ config UART_OVERRIDE_REFCLK
 	  Set to "y" when the platform overrides the uart_platform_refclk
 	  routine.
 
+config UART_BITBANG_TX_DELAY_MS
+	int
+	default 5
+	help
+	  This option sets a delay in milliseconds after configuring the
+	  UART TX pin. This can help stabilize the line and prevent
+	  corruption of the first character transmitted.
+
 config DRIVERS_UART_8250MEM
 	bool
 	default n
diff --git a/src/soc/qualcomm/common/uart_bitbang.c b/src/soc/qualcomm/common/uart_bitbang.c
index d6447f1f18..448b00c055 100644
--- a/src/soc/qualcomm/common/uart_bitbang.c
+++ b/src/soc/qualcomm/common/uart_bitbang.c
@@ -1,6 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
 #include <console/uart.h>
+#include <delay.h>
 #include <gpio.h>
 #include <boot/coreboot_tables.h>
 #include <soc/uart.h>
@@ -18,6 +19,8 @@ static void set_tx(int line_state)
 void uart_init(unsigned int idx)
 {
 	gpio_output(UART_TX_PIN, 1);
+
+	mdelay(CONFIG_UART_BITBANG_TX_DELAY_MS);
 }
 
 void uart_tx_byte(unsigned int idx, unsigned char data)

From ef11f951257f7baf865039a23f9c8aaae68454c5 Mon Sep 17 00:00:00 2001
From: Subrata Banik <subratabanik@google.com>
Date: Sat, 2 Aug 2025 12:31:10 +0530
Subject: [PATCH 1743/3886] soc/qualcomm/x1p42100: Set 1ms TX delay

This commit overrides the `UART_BITBANG_TX_DELAY_MS` Kconfig option to
1ms for the `x1p42100` SoC configuration.

TEST=Able to build google/quenbi with proper AP console log.

```
[NOTE ]  coreboot-coreboot-unknown.9999.2712497 ....
[DEBUG]  ARM64: Exception handlers installed.
[DEBUG]  ARM64: Testing exception
[DEBUG]  ARM64: Done test exception
[DEBUG]  NCC Frequency bumped to 1.363(GHz)
```

Change-Id: Ic99ce17ea5e74fca483ef0cc8dd326d3459288b4
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88637
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/soc/qualcomm/x1p42100/Kconfig | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/src/soc/qualcomm/x1p42100/Kconfig b/src/soc/qualcomm/x1p42100/Kconfig
index e65047e82b..636f6032e2 100644
--- a/src/soc/qualcomm/x1p42100/Kconfig
+++ b/src/soc/qualcomm/x1p42100/Kconfig
@@ -58,4 +58,8 @@ config UART_FOR_CONSOLE
 	help
 	 Select the QUP instance to be used for UART console output.
 
+config UART_BITBANG_TX_DELAY_MS
+	int
+	default 1
+
 endif

From f01cc9258be9b0ebffaf9e265f4778d1aea048ff Mon Sep 17 00:00:00 2001
From: Subrata Banik <subratabanik@google.com>
Date: Sun, 3 Aug 2025 18:23:20 +0530
Subject: [PATCH 1744/3886] mb/google/rex/var/screebo: Use ACPI for touchscreen
 power sequencing

This commit transitions the touchscreen power sequencing from static
coreboot GPIO configuration to ACPI-driven management using the
devicetree infrastructure for the Screebo variant.

BUG=b:430444353
TEST=Able to build and boot google/screebo. Verified touchscreen is
working as expected with this patch.

Change-Id: Ie3456032c232ac92ed7501c08b1c89b0ac274c8c
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88638
Reviewed-by: Jakub "Kuba" Czapiga <czapiga@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Pranava Y N <pranavayn@google.com>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
Reviewed-by: Jayvik Desai <jayvik@google.com>
---
 src/mainboard/google/rex/variants/screebo/gpio.c          | 4 ++--
 src/mainboard/google/rex/variants/screebo/overridetree.cb | 6 ++++--
 2 files changed, 6 insertions(+), 4 deletions(-)

diff --git a/src/mainboard/google/rex/variants/screebo/gpio.c b/src/mainboard/google/rex/variants/screebo/gpio.c
index c4fd97e99b..d404062bf0 100644
--- a/src/mainboard/google/rex/variants/screebo/gpio.c
+++ b/src/mainboard/google/rex/variants/screebo/gpio.c
@@ -82,7 +82,7 @@ static const struct pad_config gpio_table[] = {
 	/* GPP_B16 : [] ==> SOC_HDMI_HPD_L */
 	PAD_CFG_NF(GPP_B16, NONE, DEEP, NF2),
 	/* GPP_B17 :[] ==> EN_TCHSCR_PWR */
-	PAD_CFG_GPO(GPP_B17, 0, DEEP),
+	PAD_CFG_GPO(GPP_B17, 1, DEEP),
 	/* GPP_B18 : [] ==> SOC_I2C_TPM_SDA */
 	PAD_CFG_NF_LOCK(GPP_B18, NONE, NF2, LOCK_CONFIG),
 	/* GPP_B19 : [] ==> SOC_I2C_TPM_SCL */
@@ -159,7 +159,7 @@ static const struct pad_config gpio_table[] = {
 	/* GPP_D06 : [] ==> UART0_TXD. */
 	PAD_CFG_NF_LOCK(GPP_D06, NONE, NF1, LOCK_CONFIG),
 	/* GPP_D07 : [] ==>  SOC_TCHSCR_RST_L */
-	PAD_CFG_GPO(GPP_D07, 0, DEEP),
+	PAD_CFG_GPO(GPP_D07, 1, DEEP),
 	/* GPP_D08 : net NC.  Test pad. */
 	PAD_NC(GPP_D08, NONE),
 	/* GPP_D09 : [] ==> I2S_MCLK_R */
diff --git a/src/mainboard/google/rex/variants/screebo/overridetree.cb b/src/mainboard/google/rex/variants/screebo/overridetree.cb
index d46d7c91ef..cbfa652273 100644
--- a/src/mainboard/google/rex/variants/screebo/overridetree.cb
+++ b/src/mainboard/google/rex/variants/screebo/overridetree.cb
@@ -445,12 +445,13 @@ chip soc/intel/meteorlake
 				register "generic.hid" = ""ILTK0001""
 				register "generic.desc" = ""ILITEK Touchscreen""
 				register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_C07_IRQ)"
-				register "generic.probed" = "1"
+				register "generic.detect" = "1"
 				register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D07)"
 				register "generic.reset_delay_ms" = "200"
 				register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B17)"
 				register "generic.enable_delay_ms" = "12"
 				register "generic.has_power_resource" = "1"
+				register "generic.use_gpio_for_status" = "true"
 				register "hid_desc_reg_offset" = "0x01"
 				device i2c 41 on
 					probe TOUCHSCREEN TOUCHSCREEN_ILITEK
@@ -460,13 +461,14 @@ chip soc/intel/meteorlake
 				register "generic.hid" = ""EKTH7B18U""
 				register "generic.desc" = ""ELAN Touchscreen""
 				register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_C07_IRQ)"
-				register "generic.probed" = "1"
+				register "generic.detect" = "1"
 				register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D07)"
 				register "generic.reset_delay_ms" = "20"
 				register "generic.reset_off_delay_ms" = "2"
 				register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B17)"
 				register "generic.enable_delay_ms" = "1"
 				register "generic.has_power_resource" = "1"
+				register "generic.use_gpio_for_status" = "true"
 				register "hid_desc_reg_offset" = "0x01"
 				device i2c 10 on
 					probe TOUCHSCREEN TOUCHSCREEN_ELAN

From 0b3fc8ce2d4ff5b29c675c583a6e622d353d4983 Mon Sep 17 00:00:00 2001
From: zengqinghong <zengqinghong@huaqin.corp-partner.google.com​>
Date: Tue, 5 Aug 2025 12:14:12 +0800
Subject: [PATCH 1745/3886] mb/google/nissa/var/pujjoniru: Decrease cpu power
 limits
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Based on TWL 15W baseline, PL4 should set to 83W.
Ref: 646929_ADL_N_TWL_PowerMap_Rev2p6.xlsm

BUG=b:434861879
TEST=emerge-nissa coreboot chromeos-bootimage
     cbmem -c | grep PL shows PL4=83

Change-Id: I6fa929ad6f3444d323364f71687b27eb0c9c468c
Signed-off-by: Qinghong Zeng <zengqinghong@huaqin.corp-partner.google.com​>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88646
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Jian Tong <tongjian@huaqin.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
---
 src/mainboard/google/brya/variants/pujjoniru/overridetree.cb | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/mainboard/google/brya/variants/pujjoniru/overridetree.cb b/src/mainboard/google/brya/variants/pujjoniru/overridetree.cb
index 418ac6db60..65ced15f45 100644
--- a/src/mainboard/google/brya/variants/pujjoniru/overridetree.cb
+++ b/src/mainboard/google/brya/variants/pujjoniru/overridetree.cb
@@ -104,7 +104,7 @@ chip soc/intel/alderlake
 	register "power_limits_config[ADL_N_081_15W_CORE]" = "{
 			.tdp_pl1_override = 22,
 			.tdp_pl2_override = 35,
-			.tdp_pl4 = 114,
+			.tdp_pl4 = 83,
 	}"
 
 	device domain 0 on

From f0d5b25e0233d28c9ac7c213a3d4487c62ce2dac Mon Sep 17 00:00:00 2001
From: Eren Peng <peng.eren@inventec.corp-partner.google.com>
Date: Tue, 29 Jul 2025 09:41:07 +0800
Subject: [PATCH 1746/3886] mb/google/trulo/var/kaladin: Add firmware name and
 gpio for ISH

Add firmware name and update gpio pins GPP_B3 GPP_B4 for ISH

bug=b:434789824,b:434858349
TEST=Flash and boot to OS on kaladin, tested sensors work fine and unit can enter s0ix

Change-Id: Ia8dbf17a589a580116430cc4978b8d4ebbcf785e
Signed-off-by: Eren Peng <peng.eren@inventec.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88597
Reviewed-by: Kyle Lin <kylelinck@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
---
 src/mainboard/google/brya/variants/kaladin/gpio.c         | 8 ++++----
 .../google/brya/variants/kaladin/overridetree.cb          | 1 +
 2 files changed, 5 insertions(+), 4 deletions(-)

diff --git a/src/mainboard/google/brya/variants/kaladin/gpio.c b/src/mainboard/google/brya/variants/kaladin/gpio.c
index 6f433bcd73..5dcac0a363 100644
--- a/src/mainboard/google/brya/variants/kaladin/gpio.c
+++ b/src/mainboard/google/brya/variants/kaladin/gpio.c
@@ -57,10 +57,10 @@ static const struct pad_config gpio_table[] = {
 	PAD_CFG_NF(GPP_B1, NONE, DEEP, NF1),
 	/* B2  : NC */
 	PAD_NC(GPP_B2, NONE),
-	/* B3  : IMU_INT_L */
-	PAD_CFG_GPI_APIC(GPP_B3, NONE, PWROK, LEVEL, INVERT),
-	/* B4  : ACC_INT_L */
-	PAD_CFG_GPI_APIC(GPP_B4, NONE, PWROK, LEVEL, INVERT),
+	/* B3  : ISH_IMU_INT_L */
+	PAD_CFG_NF(GPP_B3, NONE, DEEP, NF4),
+	/* B4  : ISH_ACC_INT_L */
+	PAD_CFG_NF(GPP_B4, NONE, DEEP, NF4),
 	/* B5  : GPP_B5 ==> ISH_I2C0_SENSOR_SDA */
 	PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_B5, NONE, DEEP, NF1),
 	/* B6  : GPP_B6 ==> ISH_I2C0_SENSOR_SCL */
diff --git a/src/mainboard/google/brya/variants/kaladin/overridetree.cb b/src/mainboard/google/brya/variants/kaladin/overridetree.cb
index d6396afe55..4a8ad625c0 100644
--- a/src/mainboard/google/brya/variants/kaladin/overridetree.cb
+++ b/src/mainboard/google/brya/variants/kaladin/overridetree.cb
@@ -529,6 +529,7 @@ chip soc/intel/alderlake
 		device ref heci1 on end
 		device ref ish on
 			chip drivers/intel/ish
+				register "firmware_name" = ""kaladin_ish.bin""
 				register "add_acpi_dma_property" = "true"
 				device generic 0 on end
 			end

From 1da2f46db8695d7da5ec958a9f3899e173ccefa4 Mon Sep 17 00:00:00 2001
From: Kapil Porwal <kapilporwal@google.com>
Date: Wed, 6 Aug 2025 09:31:53 +0530
Subject: [PATCH 1747/3886] soc/intel/alderlake: Restore
 mem_init_override_channel_mask()

Commit 87c9bb39945b ("soc/intel/adl: Fill in SPD data on both channels
of DDR5 memory") accidentally deleted the function
mem_init_override_channel_mask().

Additionally, skip checking for channel 0 while consuming the channel
disable mask.

BUG=none
TEST=CQ

Change-Id: I6217b2801e88b8ab98b2a3acaa0cb9580b05bb64
Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88697
Reviewed-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
---
 src/soc/intel/alderlake/meminit.c | 35 +++++++++++++++++++++++++++++++
 1 file changed, 35 insertions(+)

diff --git a/src/soc/intel/alderlake/meminit.c b/src/soc/intel/alderlake/meminit.c
index f7f8ef7d9e..efeac5cecd 100644
--- a/src/soc/intel/alderlake/meminit.c
+++ b/src/soc/intel/alderlake/meminit.c
@@ -230,6 +230,40 @@ static void mem_init_dqs_upds(FSP_M_CONFIG *mem_cfg, const struct mem_channel_da
 	mem_init_dq_dqs_upds(dqs_upds, mb_cfg->dqs_map, upd_size, data, auto_detect);
 }
 
+
+/*
+ * A memory channel will be disabled if corresponding bit in
+ * ch_disable_mask is set.
+ */
+static void mem_init_override_channel_mask(FSP_M_CONFIG *mem_cfg)
+{
+	uint8_t *disable_channel_upds[MRC_CHANNELS] = {
+		&mem_cfg->DisableMc0Ch0,
+		&mem_cfg->DisableMc0Ch1,
+		&mem_cfg->DisableMc0Ch2,
+		&mem_cfg->DisableMc0Ch3,
+		&mem_cfg->DisableMc1Ch0,
+		&mem_cfg->DisableMc1Ch1,
+		&mem_cfg->DisableMc1Ch2,
+		&mem_cfg->DisableMc1Ch3,
+	};
+
+	uint8_t ch_disable_mask = mb_get_channel_disable_mask();
+	if (ch_disable_mask == 0)
+		return;
+
+	/* Mc0Ch0 cannot be disabled */
+	if (ch_disable_mask & BIT(0)) {
+		printk(BIOS_ERR, "Cannot disable the first memory channel (Mc0Ch0).\n");
+		return;
+	}
+
+	for (size_t ch = 1; ch < MRC_CHANNELS; ch++) {
+		if (ch_disable_mask & BIT(ch))
+			*disable_channel_upds[ch] = 1;
+	}
+}
+
 void memcfg_init(FSPM_UPD *memupd, const struct mb_cfg *mb_cfg,
 		 const struct mem_spd *spd_info, bool half_populated)
 {
@@ -274,6 +308,7 @@ void memcfg_init(FSPM_UPD *memupd, const struct mb_cfg *mb_cfg,
 	mem_populate_channel_data(memupd, &soc_mem_cfg[mb_cfg->type], spd_info, half_populated,
 			&data);
 	mem_init_spd_upds(mem_cfg, &data, expand_channels);
+	mem_init_override_channel_mask(mem_cfg);
 	mem_init_dq_upds(mem_cfg, &data, mb_cfg, dq_dqs_auto_detect);
 	mem_init_dqs_upds(mem_cfg, &data, mb_cfg, dq_dqs_auto_detect);
 }

From 85306062d817d5ee56cbc9682259454faf8c55aa Mon Sep 17 00:00:00 2001
From: Cindy Lu <luyi8@huaqin.corp-partner.google.com>
Date: Tue, 5 Aug 2025 22:25:10 +0800
Subject: [PATCH 1748/3886] mb/google/skywalker: Create variant Tarkin

Create the variant Tarkin.

BUG=b:436492315
TEST=emerge-skywalker coreboot
BRANCH=None

Change-Id: Iad24d09b9d505fd95264c9179d8e202262b1d3dd
Signed-off-by: Cindy Lu <luyi8@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88653
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yang Wu <wuyang5@huaqin.corp-partner.google.com>
---
 src/mainboard/google/skywalker/Kconfig      | 2 ++
 src/mainboard/google/skywalker/Kconfig.name | 3 +++
 2 files changed, 5 insertions(+)

diff --git a/src/mainboard/google/skywalker/Kconfig b/src/mainboard/google/skywalker/Kconfig
index 9f8ca1bffa..34e3b5355c 100644
--- a/src/mainboard/google/skywalker/Kconfig
+++ b/src/mainboard/google/skywalker/Kconfig
@@ -6,6 +6,7 @@ config BOARD_GOOGLE_SKYWALKER_COMMON
 		 BOARD_GOOGLE_BAZE || \
 		 BOARD_GOOGLE_OBIWAN || \
 		 BOARD_GOOGLE_SKYWALKER || \
+		 BOARD_GOOGLE_TARKIN || \
 		 BOARD_GOOGLE_YODA
 
 if BOARD_GOOGLE_SKYWALKER_COMMON
@@ -50,6 +51,7 @@ config MAINBOARD_PART_NUMBER
 	default "Baze" if BOARD_GOOGLE_BAZE
 	default "Obiwan" if BOARD_GOOGLE_OBIWAN
 	default "Skywalker" if BOARD_GOOGLE_SKYWALKER
+	default "Tarkin" if BOARD_GOOGLE_TARKIN
 	default "Yoda" if BOARD_GOOGLE_YODA
 
 config BOOT_DEVICE_SPI_FLASH_BUS
diff --git a/src/mainboard/google/skywalker/Kconfig.name b/src/mainboard/google/skywalker/Kconfig.name
index d79033d744..d77b880023 100644
--- a/src/mainboard/google/skywalker/Kconfig.name
+++ b/src/mainboard/google/skywalker/Kconfig.name
@@ -14,5 +14,8 @@ config BOARD_GOOGLE_OBIWAN
 config BOARD_GOOGLE_SKYWALKER
 	bool "->  Skywalker"
 
+config BOARD_GOOGLE_TARKIN
+	bool "->  Tarkin"
+
 config BOARD_GOOGLE_YODA
 	bool "-> Yoda"

From 8d4bb94663eb89b6cc14d16f6cc3f06439752217 Mon Sep 17 00:00:00 2001
From: Patrick Rudolph <patrick.rudolph@9elements.com>
Date: Sat, 26 Jul 2025 09:20:06 +0200
Subject: [PATCH 1749/3886] sb/intel/common/gpio: Add and use gpio_invert()

Introduce a new helper function to set the INVERT bits on
the first GPIO bank. Use it on google link instead of using
a custom implementation.

Change-Id: Icfdbc3dcae5678695b6fcc9dab7ff97d291963cd
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88565
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/google/link/mainboard.c |  8 +-------
 src/southbridge/intel/common/gpio.c   | 16 ++++++++++++++++
 src/southbridge/intel/common/gpio.h   |  4 ++++
 3 files changed, 21 insertions(+), 7 deletions(-)

diff --git a/src/mainboard/google/link/mainboard.c b/src/mainboard/google/link/mainboard.c
index c31ab110a2..c6f357bcdf 100644
--- a/src/mainboard/google/link/mainboard.c
+++ b/src/mainboard/google/link/mainboard.c
@@ -114,13 +114,7 @@ static void mainboard_init(struct device *dev)
 	google_chromeec_get_board_version(&board_version);
 	if (board_version == 0) {
 		/* If running on proto1 - enable reversion of gpio11. */
-		u32 gpio_inv;
-		u16 gpio_base = pci_read_config16
-			(pcidev_on_root(0x1f, 0), GPIO_BASE) &
-			0xfffc;
-		u16 gpio_inv_addr = gpio_base + GPI_INV;
-		gpio_inv = inl(gpio_inv_addr);
-		outl(gpio_inv | (1 << 11), gpio_inv_addr);
+		gpio_invert(11, true);
 	}
 }
 
diff --git a/src/southbridge/intel/common/gpio.c b/src/southbridge/intel/common/gpio.c
index a1b2b5426b..681457d51c 100644
--- a/src/southbridge/intel/common/gpio.c
+++ b/src/southbridge/intel/common/gpio.c
@@ -222,3 +222,19 @@ void gpio_output(gpio_t gpio_num, int value)
 	/* Set value again in case output register was gated */
 	gpio_set(gpio_num, value);
 }
+
+void gpio_invert(gpio_t gpio_num, bool invert)
+{
+	u16 gpio_blink_reg = get_gpio_base() + GPI_INV;
+	u32 config;
+
+	if (gpio_num >= 32)
+		return; /* Just ignore wrong gpio numbers. */
+
+	config = inl(gpio_blink_reg);
+	if (invert)
+		config |= BIT(gpio_num);
+	else
+		config &= ~BIT(gpio_num);
+	outl(gpio_blink_reg, config);
+}
diff --git a/src/southbridge/intel/common/gpio.h b/src/southbridge/intel/common/gpio.h
index 71154a6066..4502d8f157 100644
--- a/src/southbridge/intel/common/gpio.h
+++ b/src/southbridge/intel/common/gpio.h
@@ -4,6 +4,7 @@
 #define INTEL_COMMON_GPIO_H
 
 #include <stdint.h>
+#include <stdbool.h>
 #include <soc/gpio.h>
 
 /* ICH7 GPIOBASE */
@@ -153,4 +154,7 @@ void setup_pch_gpios(const struct pch_gpio_map *gpio);
 
 int gpio_is_native(int gpio_num);
 
+/* Enable/disable GPI_INV for the specified GPIO */
+void gpio_invert(gpio_t gpio_num, bool invert);
+
 #endif

From 21639c377120e97a61532cc60cfa694e3202267f Mon Sep 17 00:00:00 2001
From: Patrick Rudolph <patrick.rudolph@9elements.com>
Date: Sat, 26 Jul 2025 09:21:48 +0200
Subject: [PATCH 1750/3886] mb/getac/p470: Use common gpio functions

Use existing common code instead of directly accessing GPIO
I/O registers. Makes code more readable.

Change-Id: Ieebf37372f1c44a877ef6e77eecaa9049bf3aec4
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88566
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
---
 src/mainboard/getac/p470/early_init.c | 26 +++++++++-----------------
 src/mainboard/getac/p470/smihandler.c |  8 +++-----
 2 files changed, 12 insertions(+), 22 deletions(-)

diff --git a/src/mainboard/getac/p470/early_init.c b/src/mainboard/getac/p470/early_init.c
index 1f206acd3a..b2e8a25240 100644
--- a/src/mainboard/getac/p470/early_init.c
+++ b/src/mainboard/getac/p470/early_init.c
@@ -1,33 +1,25 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
-#include <bootblock_common.h>
-#include <stdint.h>
 #include <arch/io.h>
+#include <bootblock_common.h>
+#include <console/console.h>
 #include <device/pnp_ops.h>
 #include <device/pci_ops.h>
-#include <option.h>
-#include <console/console.h>
+#include <gpio.h>
 #include <northbridge/intel/i945/i945.h>
+#include <option.h>
+#include <stdint.h>
 #include <southbridge/intel/i82801gx/i82801gx.h>
 
 void mainboard_pre_raminit_config(int s3_resume)
 {
-	u32 gpios;
-
 	printk(BIOS_SPEW, "\n  Initializing drive bay...\n");
-	gpios = inl(DEFAULT_GPIOBASE + 0x38); // GPIO Level 2
-	gpios |= (1 << 0); // GPIO33 = ODD
-	gpios |= (1 << 1); // GPIO34 = IDE_RST#
-	outl(gpios, DEFAULT_GPIOBASE + 0x38);	/* GP_LVL2 */
-
-	gpios = inl(DEFAULT_GPIOBASE + 0x0c); // GPIO Level
-	gpios &= ~(1 << 13);	// ??
-	outl(gpios, DEFAULT_GPIOBASE + 0x0c);	/* GP_LVL */
+	gpio_set(33, 1); // GPIO33 = ODD
+	gpio_set(34, 1); // GPIO34 = IDE_RST#
+	gpio_set(13, 0); // ??
 
 	printk(BIOS_SPEW, "\n  Initializing Ethernet NIC...\n");
-	gpios = inl(DEFAULT_GPIOBASE + 0x0c); // GPIO Level
-	gpios &= ~(1 << 24);	// Enable LAN Power
-	outl(gpios, DEFAULT_GPIOBASE + 0x0c);	/* GP_LVL */
+	gpio_set(24, 0); // Enable LAN Power
 }
 
 /* Override the default lpc decode ranges */
diff --git a/src/mainboard/getac/p470/smihandler.c b/src/mainboard/getac/p470/smihandler.c
index e69627af5d..6fd1484332 100644
--- a/src/mainboard/getac/p470/smihandler.c
+++ b/src/mainboard/getac/p470/smihandler.c
@@ -3,10 +3,11 @@
 #include <arch/io.h>
 #include <console/console.h>
 #include <cpu/x86/smm.h>
+#include <ec/acpi/ec.h>
+#include <gpio.h>
 #include <southbridge/intel/i82801gx/i82801gx.h>
 #include <soc/nvs.h>
 #include <southbridge/intel/common/gpio.h>
-#include <ec/acpi/ec.h>
 #include "ec_oem.c"
 
 #define MAX_LCD_BRIGHTNESS 0xd8
@@ -14,7 +15,6 @@
 int mainboard_io_trap_handler(int smif)
 {
 	u8 reg8;
-	u32 reg32;
 
 	switch (smif) {
 	case 0x2b:
@@ -95,9 +95,7 @@ int mainboard_io_trap_handler(int smif)
 		break;
 	case 0xde:
 		printk(BIOS_DEBUG, "LAN power off\n");
-		reg32 = inl(DEFAULT_GPIOBASE + GP_LVL);
-		reg32 |= (1 << 24);			// Disable LAN Power
-		outl(reg32, DEFAULT_GPIOBASE + GP_LVL);
+		gpio_set(24, 0); // Disable LAN Power
 		break;
 	case 0xdf:
 		printk(BIOS_DEBUG, "RF enable\n");

From d6ceaf72da444c8dafc54b327083b43319011199 Mon Sep 17 00:00:00 2001
From: Patrick Rudolph <patrick.rudolph@9elements.com>
Date: Sat, 26 Jul 2025 09:26:17 +0200
Subject: [PATCH 1751/3886] mb/samsung/lumpy: Use gpio_base2_value

Instead of directly accessing GPIO I/O registers use existing
common code to read the SPD pin straps.

Change-Id: Ie758a4bfb35d1f81c16537cda0e26e43ac860b1e
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88567
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
---
 src/mainboard/samsung/lumpy/early_init.c | 17 ++++++++---------
 1 file changed, 8 insertions(+), 9 deletions(-)

diff --git a/src/mainboard/samsung/lumpy/early_init.c b/src/mainboard/samsung/lumpy/early_init.c
index b82d4d3411..79382f3201 100644
--- a/src/mainboard/samsung/lumpy/early_init.c
+++ b/src/mainboard/samsung/lumpy/early_init.c
@@ -6,6 +6,7 @@
 #include <bootblock_common.h>
 #include <console/console.h>
 #include <bootmode.h>
+#include <gpio.h>
 #include <northbridge/intel/sandybridge/sandybridge.h>
 #include <northbridge/intel/sandybridge/raminit.h>
 #include <southbridge/intel/bd82x6x/pch.h>
@@ -59,22 +60,20 @@ void mainboard_late_rcba_config(void)
 
 static unsigned int get_spd_index(void)
 {
-	u32 gp_lvl2 = inl(DEFAULT_GPIOBASE + 0x38);
-	u8 gpio33, gpio41, gpio49;
-	gpio33 = (gp_lvl2 >> (33-32)) & 1;
-	gpio41 = (gp_lvl2 >> (41-32)) & 1;
-	gpio49 = (gp_lvl2 >> (49-32)) & 1;
+	const gpio_t spd_id_pins[] = {33, 41, 49};
+	u32 pin_sts = gpio_base2_value(spd_id_pins, ARRAY_SIZE(spd_id_pins));
+
 	printk(BIOS_DEBUG, "Memory Straps:\n");
 	printk(BIOS_DEBUG, " - memory capacity %dGB\n",
-		gpio33 ? 2 : 1);
+		(pin_sts & 1) ? 2 : 1);
 	printk(BIOS_DEBUG, " - die revision %d\n",
-		gpio41 ? 2 : 1);
+		(pin_sts & 2) ? 2 : 1);
 	printk(BIOS_DEBUG, " - vendor %s\n",
-		gpio49 ? "Samsung" : "Other");
+		(pin_sts & 4) ? "Samsung" : "Other");
 
 	unsigned int spd_index = 0;
 
-	switch ((gpio49 << 2) | (gpio41 << 1) | gpio33) {
+	switch (pin_sts) {
 	case 0: // Other 1G Rev 1
 		spd_index = 0;
 		break;

From f789899dac82dc13a50504f71efd1790b63baf8d Mon Sep 17 00:00:00 2001
From: Patrick Rudolph <patrick.rudolph@9elements.com>
Date: Sat, 26 Jul 2025 09:35:08 +0200
Subject: [PATCH 1752/3886] sb/intel/common/gpio: Move register defines

Move ICH7 GPIO register defines into private scope. This enforces
the use of GPIO common code and mainboard can no longer directly
access GPIO I/O registers.

Change-Id: Iedf3e55f8aecf7b1ac6f47b29d9f88d58d1b6867
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88568
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
---
 src/southbridge/intel/common/gpio.c | 22 ++++++++++++++++++++++
 src/southbridge/intel/common/gpio.h | 16 ----------------
 2 files changed, 22 insertions(+), 16 deletions(-)

diff --git a/src/southbridge/intel/common/gpio.c b/src/southbridge/intel/common/gpio.c
index 681457d51c..ae13cb95bf 100644
--- a/src/southbridge/intel/common/gpio.c
+++ b/src/southbridge/intel/common/gpio.c
@@ -12,9 +12,31 @@
 
 #define MAX_GPIO_NUMBER 75 /* zero based */
 
+/*
+ * If you want to use these macros outside this file, consider making
+ * more helper functions to expose the functionality you want instead.
+ */
+
 /* LPC GPIO Base Address Register */
 #define GPIO_BASE	0x48
 
+/* ICH7 GPIOBASE */
+#define GPIO_USE_SEL	0x00
+#define GP_IO_SEL	0x04
+#define GP_LVL		0x0c
+#define GPO_BLINK	0x18
+#define GPI_INV		0x2c
+#define GPIO_USE_SEL2	0x30
+#define GP_IO_SEL2	0x34
+#define GP_LVL2		0x38
+#define GPIO_USE_SEL3	0x40
+#define GP_IO_SEL3	0x44
+#define GP_LVL3		0x48
+#define GP_RST_SEL1	0x60
+#define GP_RST_SEL2	0x64
+#define GP_RST_SEL3	0x68
+
+
 static u16 get_gpio_base(void)
 {
 #ifdef __SIMPLE_DEVICE__
diff --git a/src/southbridge/intel/common/gpio.h b/src/southbridge/intel/common/gpio.h
index 4502d8f157..3d7bebf3c1 100644
--- a/src/southbridge/intel/common/gpio.h
+++ b/src/southbridge/intel/common/gpio.h
@@ -7,22 +7,6 @@
 #include <stdbool.h>
 #include <soc/gpio.h>
 
-/* ICH7 GPIOBASE */
-#define GPIO_USE_SEL	0x00
-#define GP_IO_SEL	0x04
-#define GP_LVL		0x0c
-#define GPO_BLINK	0x18
-#define GPI_INV		0x2c
-#define GPIO_USE_SEL2	0x30
-#define GP_IO_SEL2	0x34
-#define GP_LVL2		0x38
-#define GPIO_USE_SEL3	0x40
-#define GP_IO_SEL3	0x44
-#define GP_LVL3		0x48
-#define GP_RST_SEL1	0x60
-#define GP_RST_SEL2	0x64
-#define GP_RST_SEL3	0x68
-
 #define GPIO_MODE_NATIVE	0
 #define GPIO_MODE_GPIO		1
 #define GPIO_MODE_NONE		1

From 05a38e2af3f014e40b4ebefe9b2c7112fdb3699e Mon Sep 17 00:00:00 2001
From: alokagar <alok.agarwal@intel.com>
Date: Tue, 29 Jul 2025 10:07:37 +0530
Subject: [PATCH 1753/3886] mb/google/fatcat: Disable memory training progress
 bar

Set disable_progress_bar to disable the memory progress bar for fatcat
board. Removed the memory progress bar feature to enhance performance.

BUG=b:418675387
TEST=After setting disable_progress_bar, memory training progress bar is
disabled.

Change-Id: I25302f6ed095603150d8e7e0bbe04ff96944f07c
Signed-off-by: Alok Agarwal <alok.agarwal@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88598
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: <srinivas.kulkarni@intel.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
---
 .../google/fatcat/variants/baseboard/fatcat/devicetree.cb       | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/src/mainboard/google/fatcat/variants/baseboard/fatcat/devicetree.cb b/src/mainboard/google/fatcat/variants/baseboard/fatcat/devicetree.cb
index 6eded7c12f..fd9a6b4513 100644
--- a/src/mainboard/google/fatcat/variants/baseboard/fatcat/devicetree.cb
+++ b/src/mainboard/google/fatcat/variants/baseboard/fatcat/devicetree.cb
@@ -115,6 +115,8 @@ chip soc/intel/pantherlake
 	register "pch_hda_idisp_link_frequency" = "HDA_LINKFREQ_96MHZ"
 	register "pch_hda_idisp_codec_enable" = "true"
 
+	register "disable_progress_bar" = "true"
+
 	device domain 0 on
 		device ref dtt on end
 		device ref npu on end

From e290bb6750682b8261d54f37d58af8b8c466fbd2 Mon Sep 17 00:00:00 2001
From: Alok Agarwal <alok.agarwal@intel.com>
Date: Wed, 30 Jul 2025 17:58:27 +0530
Subject: [PATCH 1754/3886] mb/baseboard/ptlrvp: Disable memory training
 progress bar

Set disable_progress_bar to disable the memory progress bar for fatcat
board. Removed the memory progress bar feature to enhance performance.

BUG=b:418675387
TEST=After setting disable_progress_bar, memory training progress bar is
disable.

Change-Id: Ic303aa57843039f49130c09da0345f7e7573b0e5
Signed-off-by: Alok Agarwal <alok.agarwal@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88613
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: <srinivas.kulkarni@intel.com>
---
 .../intel/ptlrvp/variants/baseboard/ptlrvp/devicetree.cb        | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/src/mainboard/intel/ptlrvp/variants/baseboard/ptlrvp/devicetree.cb b/src/mainboard/intel/ptlrvp/variants/baseboard/ptlrvp/devicetree.cb
index c599a00139..83e99fb682 100644
--- a/src/mainboard/intel/ptlrvp/variants/baseboard/ptlrvp/devicetree.cb
+++ b/src/mainboard/intel/ptlrvp/variants/baseboard/ptlrvp/devicetree.cb
@@ -82,6 +82,8 @@ chip soc/intel/pantherlake
 	register "pch_hda_idisp_link_frequency" = "HDA_LINKFREQ_96MHZ"
 	register "pch_hda_idisp_codec_enable" = "true"
 
+	register "disable_progress_bar" = "true"
+
 	device domain 0 on
 		device ref dtt on end
 		device ref npu on end

From dc64b9659dc2ca4fdb4e76e0066a107018f18e7d Mon Sep 17 00:00:00 2001
From: Kapil Porwal <kapilporwal@google.com>
Date: Wed, 6 Aug 2025 00:37:38 +0530
Subject: [PATCH 1755/3886] soc/qc/cmn: Refactor qclib_load_and_run function

Move below code to `qclib_prepare_and_run()` -
1. Serial debug interface entry.
2. Enable serial output.
3. Dump interface table entries.
4. Handle reset requested by qclib.
5. Copy qclib log to cbmem.

BUG=none
TEST=Build Google/Quenbi.

Change-Id: I2f724d4da21a07fbc726dc5600cc706379b91138
Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88654
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
---
 src/soc/qualcomm/common/qclib.c | 54 ++++++++++++++++-----------------
 1 file changed, 27 insertions(+), 27 deletions(-)

diff --git a/src/soc/qualcomm/common/qclib.c b/src/soc/qualcomm/common/qclib.c
index ef6f90eefc..6a1df18d8a 100644
--- a/src/soc/qualcomm/common/qclib.c
+++ b/src/soc/qualcomm/common/qclib.c
@@ -184,6 +184,20 @@ struct prog qclib; /* This will be re-used by qclib_rerun() */
 static void qclib_prepare_and_run(void)
 {
 	struct mmu_context pre_qclib_mmu_context;
+	int i;
+
+	/* output area, QCLib copies console log buffer out */
+	if (CONFIG(CONSOLE_CBMEM))
+		qclib_add_if_table_entry(QCLIB_TE_QCLIB_LOG_BUFFER,
+				_qclib_serial_log,
+				REGION_SIZE(qclib_serial_log), 0);
+
+	/* Enable QCLib serial output, based on Kconfig */
+	if (CONFIG(CONSOLE_SERIAL))
+		qclib_cb_if_table.global_attributes =
+			QCLIB_GA_ENABLE_UART_LOGGING;
+
+	dump_te_table();
 
 	printk(BIOS_DEBUG, "Global Attributes[%#x]..Table Entries Count[%d]\n",
 		qclib_cb_if_table.global_attributes,
@@ -205,11 +219,23 @@ static void qclib_prepare_and_run(void)
 	mmu_disable();
 	mmu_restore_context(&pre_qclib_mmu_context);
 	mmu_enable();
+
+	if (qclib_cb_if_table.global_attributes & QCLIB_GA_FORCE_COLD_REBOOT) {
+		printk(BIOS_NOTICE, "QcLib requested cold reboot\n");
+		board_reset();
+	}
+
+	/* step through I/F table, handling return values */
+	for (i = 0; i < qclib_cb_if_table.num_entries; i++)
+		if (qclib_cb_if_table.te[i].blob_attributes &
+				QCLIB_BA_SAVE_TO_STORAGE)
+			write_table_entry(&qclib_cb_if_table.te[i]);
+
+	printk(BIOS_DEBUG, "QCLib completed\n\n\n");
 }
 
 void qclib_load_and_run(void)
 {
-	int i;
 	ssize_t data_size;
 
 	/* zero ddr_information SRAM region, needs new data each boot */
@@ -217,12 +243,6 @@ void qclib_load_and_run(void)
 
 	init_qclib_cb_if_table(&qclib_cb_if_table);
 
-	/* output area, QCLib copies console log buffer out */
-	if (CONFIG(CONSOLE_CBMEM))
-		qclib_add_if_table_entry(QCLIB_TE_QCLIB_LOG_BUFFER,
-				_qclib_serial_log,
-				REGION_SIZE(qclib_serial_log), 0);
-
 	/* output area, QCLib fills in DDR details */
 	qclib_add_if_table_entry(QCLIB_TE_DDR_INFORMATION, NULL, 0, 0);
 
@@ -259,11 +279,6 @@ void qclib_load_and_run(void)
 	}
 	qclib_add_if_table_entry(QCLIB_TE_DCB_SETTINGS, _dcb, data_size, 0);
 
-	/* Enable QCLib serial output, based on Kconfig */
-	if (CONFIG(CONSOLE_SERIAL))
-		qclib_cb_if_table.global_attributes =
-			QCLIB_GA_ENABLE_UART_LOGGING;
-
 	if (CONFIG(QC_SDI_ENABLE) && (!CONFIG(VBOOT) ||
 		!vboot_is_gbb_flag_set(VB2_GBB_FLAG_RUNNING_FAFT))) {
 		struct prog qcsdi =
@@ -285,8 +300,6 @@ void qclib_load_and_run(void)
 		goto fail;
 	}
 
-	dump_te_table();
-
 	/* Attempt to load QCLib elf */
 	qclib = (struct prog)
 		PROG_INIT(PROG_REFCODE, qclib_file(QCLIB_CBFS_QCLIB));
@@ -300,23 +313,10 @@ void qclib_load_and_run(void)
 	printk(BIOS_DEBUG, "\n\n\nEnter QcLib to Initialize DDR and bring up SHRM\n");
 	qclib_prepare_and_run();
 
-	if (qclib_cb_if_table.global_attributes & QCLIB_GA_FORCE_COLD_REBOOT) {
-		printk(BIOS_NOTICE, "QcLib requested cold reboot\n");
-		board_reset();
-	}
-
-	/* step through I/F table, handling return values */
-	for (i = 0; i < qclib_cb_if_table.num_entries; i++)
-		if (qclib_cb_if_table.te[i].blob_attributes &
-				QCLIB_BA_SAVE_TO_STORAGE)
-			write_table_entry(&qclib_cb_if_table.te[i]);
-
 	/* confirm that we received valid ddr information from QCLib */
 	assert((uintptr_t)_dram == region_offset(ddr_region) &&
 		region_sz(ddr_region) >= (u8 *)cbmem_top() - _dram);
 
-	printk(BIOS_DEBUG, "QCLib completed\n\n\n");
-
 	return;
 
 fail:

From b603f230886d319041337925276fbe9cd72f7c52 Mon Sep 17 00:00:00 2001
From: Kapil Porwal <kapilporwal@google.com>
Date: Wed, 6 Aug 2025 00:48:45 +0530
Subject: [PATCH 1756/3886] mb/google/bluey: Avoid using function call table

BUG=none
TEST=Build Google/Quenbi.

Change-Id: Ie2df9402c3a2cf95e150a4a4321477ddee7e9678
Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88655
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/google/bluey/romstage.c | 16 +++++++---------
 1 file changed, 7 insertions(+), 9 deletions(-)

diff --git a/src/mainboard/google/bluey/romstage.c b/src/mainboard/google/bluey/romstage.c
index b15f6e694f..4487b76cf9 100644
--- a/src/mainboard/google/bluey/romstage.c
+++ b/src/mainboard/google/bluey/romstage.c
@@ -9,16 +9,14 @@
 
 void platform_romstage_main(void)
 {
-	void (*const fw_init_sequence[])(void) = {
-		shrm_fw_load_reset,
-		qclib_load_and_run,
-		aop_fw_load_reset,
-		qclib_rerun,
-	};
+	shrm_fw_load_reset();
 
-	/* Executing essential firmware loading */
-	for (size_t i = 0; i < ARRAY_SIZE(fw_init_sequence); i++)
-		fw_init_sequence[i]();
+	/* QCLib: DDR init & train */
+	qclib_load_and_run();
+
+	aop_fw_load_reset();
+
+	qclib_rerun();
 
 	/*
 	 * Enable this power rail now for FPMCU stability prior to

From c11490623973b71e79b296b667236b9e5cc98232 Mon Sep 17 00:00:00 2001
From: Zheng Li <lizheng@huaqin.corp-partner.google.com>
Date: Wed, 6 Aug 2025 17:25:57 +0800
Subject: [PATCH 1757/3886] mb/google/trulo/var/pujjocento: Update DTT settings
 for thermal control

Update DTT settings according to b:436759545#comment1 in
order to increase the limit of the charging current to 3A/1.5A.

BUG=b:436759545
TEST=emerge-nissa coreboot, and thermal engineer verifies OK.

Change-Id: I3f07884b2817904925050ef24957b5070a8cab65
Signed-off-by: Zheng Li <lizheng@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88699
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kun Liu <liukun11@huaqin.corp-partner.google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
---
 src/mainboard/google/brya/variants/pujjocento/overridetree.cb | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/mainboard/google/brya/variants/pujjocento/overridetree.cb b/src/mainboard/google/brya/variants/pujjocento/overridetree.cb
index cdf996e53a..5a9621c7e1 100644
--- a/src/mainboard/google/brya/variants/pujjocento/overridetree.cb
+++ b/src/mainboard/google/brya/variants/pujjocento/overridetree.cb
@@ -309,8 +309,8 @@ chip soc/intel/alderlake
 				## Charger Performance Control (Control, mA)
 				register "controls.charger_perf" = "{
 					[0] = { 255, 4700 },
-					[1] = {  40, 2500 },
-					[2] = {  16, 1000 },
+					[1] = {  48, 3000 },
+					[2] = {  24, 1500 },
 					[3] = {   8,  500 }
 				}"
 

From 543fb60ec46b855b16223ee75d7e5ac3cb9003bf Mon Sep 17 00:00:00 2001
From: Jian Tong <tongjian@huaqin.corp-partner.google.com>
Date: Wed, 6 Aug 2025 09:11:42 +0800
Subject: [PATCH 1758/3886] mb/google/brox/var/lotso: Set slew rate to 1/8

Set slow slew rate VCCIA and VCCGT to SLEW_FAST_8.
The slope of the voltage measured by the oscilloscope 4 mV/us is close to the theoretical value of 3.75 mV/us.

BUG=b:404416910
TEST=emerge-brox coreboot chromeos-bootimage
	USE=fw_debug confirm SlowSlewRate set to 2 at FSP

Change-Id: I7ec05c6a20997fcc094b20fa763eb3bc030fefa1
Signed-off-by: Jian Tong <tongjian@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88696
Reviewed-by: Dengwu Yu <yudengwu@huaqin.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
---
 src/mainboard/google/brox/variants/lotso/overridetree.cb | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/mainboard/google/brox/variants/lotso/overridetree.cb b/src/mainboard/google/brox/variants/lotso/overridetree.cb
index 6338e828f6..fa26f03eb9 100644
--- a/src/mainboard/google/brox/variants/lotso/overridetree.cb
+++ b/src/mainboard/google/brox/variants/lotso/overridetree.cb
@@ -74,8 +74,8 @@ chip soc/intel/alderlake
 
 	# Acoustic settings
 	register "acoustic_noise_mitigation" = "1"
-	register "slow_slew_rate[VR_DOMAIN_IA]" = "SLEW_FAST_4"
-	register "slow_slew_rate[VR_DOMAIN_GT]" = "SLEW_FAST_4"
+	register "slow_slew_rate[VR_DOMAIN_IA]" = "SLEW_FAST_8"
+	register "slow_slew_rate[VR_DOMAIN_GT]" = "SLEW_FAST_8"
 	register "fast_pkg_c_ramp_disable[VR_DOMAIN_IA]" = "1"
 	register "fast_pkg_c_ramp_disable[VR_DOMAIN_GT]" = "1"
 

From 0bedce05d898c5f100523408c91cb0875e124520 Mon Sep 17 00:00:00 2001
From: Zhongtian Wu <wuzhongtian@huaqin.corp-partner.google.com>
Date: Thu, 7 Aug 2025 15:04:05 +0800
Subject: [PATCH 1759/3886] mb/google/nissa/var/pujjocento: Change touchpanel
 sequence to meet spec
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Setup GPP_C0 and GPP_C1 in early and romstage to meet spec requirements
Spec require TP_Reset ON after VTSP ON 0-10ms.
Before modification，TP_Reset ON before VTSP ON.
After modification，TP_Reset ON after VTSP ON 1ms.

BUG=b:421455835
BRANCH=none
TEST=Build and boot to pujjocento. Verify touchpanel sequence

Change-Id: I7d3d79c9f67edf42b64316757c448fe385207a86
Signed-off-by: Zhongtian Wu <wuzhongtian@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88704
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
---
 src/mainboard/google/brya/variants/pujjocento/gpio.c | 8 ++------
 1 file changed, 2 insertions(+), 6 deletions(-)

diff --git a/src/mainboard/google/brya/variants/pujjocento/gpio.c b/src/mainboard/google/brya/variants/pujjocento/gpio.c
index 517eb495b4..aab27a7550 100644
--- a/src/mainboard/google/brya/variants/pujjocento/gpio.c
+++ b/src/mainboard/google/brya/variants/pujjocento/gpio.c
@@ -102,8 +102,6 @@ static const struct pad_config gpio_table[] = {
 
 	/* C0  : SMBCLK ==> EN_PP3300_TCHSCR_X */
 	PAD_CFG_GPO(GPP_C0, 1, DEEP),
-	/* C1  : SMBDATA ==> TCHSCR_RST_L */
-	PAD_CFG_GPO(GPP_C1, 1, DEEP),
 	/* C2  : SMBALERT# ==> GPP_C2_STRAP */
 	PAD_NC(GPP_C2, NONE),
 	/* C3  : EN_PP3300_UCAM_X */
@@ -180,6 +178,8 @@ static const struct pad_config gpio_table[] = {
 	PAD_NC_LOCK(GPP_E9, NONE, LOCK_CONFIG),
 	/* E10 : EN_PP3300_WLAN_X */
 	PAD_CFG_GPO(GPP_E10, 0, DEEP),
+	/* C1  : SMBDATA ==> TCHSCR_RST_L */
+	PAD_CFG_GPO(GPP_C1, 1, DEEP),
 	/* E11 : TCHSCR_INT_ODL */
 	PAD_CFG_GPI_APIC(GPP_E11, NONE, PLTRST, LEVEL, INVERT),
 	/* E12 : THC0_SPI1_IO1 ==> SOC_WP_OD */
@@ -432,10 +432,6 @@ static const struct pad_config gpio_table[] = {
 
 /* Early pad configuration in bootblock */
 static const struct pad_config early_gpio_table[] = {
-	/* C0  : SMBCLK ==> EN_PP3300_TCHSCR_X */
-	PAD_CFG_GPO(GPP_C0, 1, DEEP),
-	/* C1  : SMBDATA ==> TCHSCR_RST_L */
-	PAD_CFG_GPO(GPP_C1, 1, DEEP),
 	/* A13 : GPP_A13 ==> GSC_SOC_INT_ODL */
 	PAD_CFG_GPI_APIC(GPP_A13, NONE, PLTRST, LEVEL, INVERT),
 	/* E3 : PROC_GP0 ==> SOC_WP_OD */

From ab2ef8878c0b3c3afe44c223c36afa772a974e92 Mon Sep 17 00:00:00 2001
From: Zhongtian Wu <wuzhongtian@huaqin.corp-partner.google.com>
Date: Thu, 7 Aug 2025 15:23:06 +0800
Subject: [PATCH 1760/3886] mb/google/trulo/var/pujjocento: Update touchscreen
 information

The properties of PARA3406 and PARA3408 are the same
Update PARA3406&PARA3408 to PARA340X

BUG=b:417106542
BRANCH=none
TEST=Build and boot to pujjocento. Verify touchscreen works.

Change-Id: Ifed5dd9c2b0512c700f5262d7105578bc604a945
Signed-off-by: Zhongtian Wu <wuzhongtian@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88705
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 .../brya/variants/pujjocento/overridetree.cb  | 19 +------------------
 1 file changed, 1 insertion(+), 18 deletions(-)

diff --git a/src/mainboard/google/brya/variants/pujjocento/overridetree.cb b/src/mainboard/google/brya/variants/pujjocento/overridetree.cb
index 5a9621c7e1..961ffa86bd 100644
--- a/src/mainboard/google/brya/variants/pujjocento/overridetree.cb
+++ b/src/mainboard/google/brya/variants/pujjocento/overridetree.cb
@@ -540,24 +540,7 @@ chip soc/intel/alderlake
 				device i2c 10 on end
 			end
 			chip drivers/i2c/hid
-				register "generic.hid" = ""PARA3406""
-				register "generic.desc" = ""Parade Touchscreen""
-				register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_E11_IRQ)"
-				register "generic.detect" = "1"
-				register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C1)"
-				register "generic.reset_delay_ms" = "20"
-				register "generic.reset_off_delay_ms" = "2"
-				register "generic.stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C4)"
-				register "generic.stop_delay_ms" = "280"
-				register "generic.stop_off_delay_ms" = "2"
-				register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C0)"
-				register "generic.enable_delay_ms" = "1"
-				register "generic.has_power_resource" = "1"
-				register "hid_desc_reg_offset" = "0x01"
-				device i2c 24 on end
-			end
-			chip drivers/i2c/hid
-				register "generic.hid" = ""PARA3408""
+				register "generic.hid" = ""PARA340X""
 				register "generic.desc" = ""Parade Touchscreen""
 				register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_E11_IRQ)"
 				register "generic.detect" = "1"

From 8f09629fb11c81e0d9b38e51d8d1769018ea82d9 Mon Sep 17 00:00:00 2001
From: Julius Werner <jwerner@chromium.org>
Date: Wed, 6 Aug 2025 14:06:14 -0700
Subject: [PATCH 1761/3886] spi_flash: Fix initialization of `flags` field in
 lb_spi_flash

Commit 8dec5fcaf8d4 ("drivers/spi: Add 4-byte address mode flag to
lb_spi_flash") split the existing 32-bit `erase_cmd` field into multiple
fields. The new `flags` field thus created is used to pass information
about whether the flash is in 4-byte address mode.

Unfortunately, we forgot to initialize the new fields in the case that
the flash is not in 4-byte address mode. This means it can have any
arbitrary value, including values where the new flag bit is accidentally
set (causing flash access errors in the payload).

This patch fixes the problem and tries to prevent further issues with
field changes in the future by explicitly zeroing the entire coreboot
table structure before starting to fill in the values.

Change-Id: I3ad9812fc76ae2989dcf4a294034c4e31456c74e
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88700
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
---
 src/drivers/spi/spi_flash.c | 7 +++----
 1 file changed, 3 insertions(+), 4 deletions(-)

diff --git a/src/drivers/spi/spi_flash.c b/src/drivers/spi/spi_flash.c
index dda089e917..daf8a219db 100644
--- a/src/drivers/spi/spi_flash.c
+++ b/src/drivers/spi/spi_flash.c
@@ -743,6 +743,7 @@ void lb_spi_flash(struct lb_header *header)
 		return;
 
 	flash = (struct lb_spi_flash *)lb_new_record(header);
+	memset(flash, 0, sizeof(*flash));
 
 	flash->tag = LB_TAG_SPI_FLASH;
 	flash->size = sizeof(*flash);
@@ -761,9 +762,7 @@ void lb_spi_flash(struct lb_header *header)
 		flash->erase_cmd = CMD_BLOCK_ERASE;
 	}
 
-	if (!CONFIG(BOOT_DEVICE_MEMORY_MAPPED)) {
-		flash->mmap_count = 0;
-	} else {
+	if (CONFIG(BOOT_DEVICE_MEMORY_MAPPED)) {
 		struct flash_mmap_window *table = (struct flash_mmap_window *)(flash + 1);
 		flash->mmap_count = spi_flash_get_mmap_windows(table);
 		flash->size += flash->mmap_count * sizeof(*table);
@@ -771,7 +770,7 @@ void lb_spi_flash(struct lb_header *header)
 
 	/* Pass 4-byte address mode information to payload */
 	if (CONFIG(SPI_FLASH_FORCE_4_BYTE_ADDR_MODE))
-		flash->flags = LB_SPI_FLASH_FLAG_IN_4BYTE_ADDR_MODE;
+		flash->flags |= LB_SPI_FLASH_FLAG_IN_4BYTE_ADDR_MODE;
 }
 
 int spi_flash_ctrlr_protect_region(const struct spi_flash *flash,

From 34d9305dcce40171a29b4e8fe769c5983320e20e Mon Sep 17 00:00:00 2001
From: smadhesu <smadhesu@qualcomm.corp-partner.google.com>
Date: Fri, 8 Aug 2025 13:54:07 +0530
Subject: [PATCH 1762/3886] soc/qc/x1p42100: Pack QcLib DTB into CBFS

This patch enables packaging of the QcLib DTB into CBFS.

TEST=Verify QcLib execution on Bluey platform.

Change-Id: I3e70a6615336cae783456f4d2f72b811fd9b6edc
Signed-off-by: smadhesu <smadhesu@qualcomm.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88723
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
---
 src/soc/qualcomm/x1p42100/Makefile.mk | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/src/soc/qualcomm/x1p42100/Makefile.mk b/src/soc/qualcomm/x1p42100/Makefile.mk
index cb249f494d..51770fd8f7 100644
--- a/src/soc/qualcomm/x1p42100/Makefile.mk
+++ b/src/soc/qualcomm/x1p42100/Makefile.mk
@@ -113,6 +113,14 @@ $(DCB_CBFS)-type := raw
 $(DCB_CBFS)-compression := $(CBFS_COMPRESS_FLAG)
 cbfs-files-y += $(DCB_CBFS)
 
+################################################################################
+DTB_FILE := $(X1P42100_BLOB)/boot/pre-ddr.dtb
+DTB_CBFS := $(CONFIG_CBFS_PREFIX)/dtb
+$(DTB_CBFS)-file := $(DTB_FILE)
+$(DTB_CBFS)-type := raw
+$(DTB_CBFS)-compression := $(CBFS_COMPRESS_FLAG)
+cbfs-files-y += $(DTB_CBFS)
+
 ################################################################################
 UART_FW_FILE := $(X1P42100_BLOB)/qup_fw/uart_fw.bin
 UART_FW_CBFS := $(CONFIG_CBFS_PREFIX)/uart_fw

From 795157a606375106cc2b4aed274d1f3c58c1da3b Mon Sep 17 00:00:00 2001
From: Subrata Banik <subratabanik@google.com>
Date: Sat, 9 Aug 2025 02:15:35 +0530
Subject: [PATCH 1763/3886] mb/google/bluey: Increase MRC cache size

Increase the size of the Memory Reference Code (MRC) cache to prevent
boot failures.

Previously, the MRC cache was 64K (32K for recovery and 32K for
read/write), which was insufficient for the firmware. This change
expands the UNIFIED_MRC_CACHE to 128K, with RECOVERY_MRC_CACHE and
RW_MRC_CACHE each receiving 64K.

BUG=b:437402936
TEST=Able to build and boot google/quenbi till depthcharge.

w/o this patch:

```
[ERROR]  REGF metadata allocation failed: 3880 data blocks 2048 total blocks
[ERROR]  MRC: failed to update 'RW_MRC_CACHE'.
```

w/ this patch:

```
[DEBUG]  FMAP: area RW_MRC_CACHE found @ c10000 (65536 bytes)
...
[DEBUG]  FMAP: area RW_MRC_CACHE found @ c10000 (65536 bytes)
[DEBUG]  MRC: Checking cached data update for 'RW_MRC_CACHE'.
[DEBUG]  read SPI 0xc10010 0xf27c: 5011 us, 12387 KB/s, 99.096 Mbps
[DEBUG]  MRC: cache data 'RW_MRC_CACHE' needs update.
[INFO ]  REGF update can't fit. Will empty.
[DEBUG]  SF: Successfully erased 65536 bytes @ 0xc10000
[DEBUG]  MRC: updated 'RW_MRC_CACHE'.

```

Change-Id: Ie456f9ab870eab06c2d23cb5d2734faf644a2176
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88727
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
---
 src/mainboard/google/bluey/chromeos.fmd | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/src/mainboard/google/bluey/chromeos.fmd b/src/mainboard/google/bluey/chromeos.fmd
index 2396097aae..f29de156d0 100644
--- a/src/mainboard/google/bluey/chromeos.fmd
+++ b/src/mainboard/google/bluey/chromeos.fmd
@@ -13,10 +13,10 @@ FLASH@0x0 CONFIG_ROM_SIZE {
 		RO_VPD(PRESERVE) 16K
 	}
 
-	RW_MISC 120K {
-		UNIFIED_MRC_CACHE(PRESERVE) 64K {
-			RECOVERY_MRC_CACHE 32K
-			RW_MRC_CACHE 32K
+	RW_MISC 184K {
+		UNIFIED_MRC_CACHE(PRESERVE) 128K {
+			RECOVERY_MRC_CACHE 64K
+			RW_MRC_CACHE 64K
 		}
 		RW_ELOG(PRESERVE) 4K
 		RW_SHARED 4K {

From ece0072d1c48910b64167403230717f82db47b3e Mon Sep 17 00:00:00 2001
From: Luca Lai <luca.lai@lcfc.corp-partner.google.com>
Date: Thu, 31 Jul 2025 19:06:01 +0800
Subject: [PATCH 1764/3886] mb/google/trulo/var/pujjolo: Update verb table to
 fix pop noise

Because there is a pop noise when bios booting stage, so modify
verb table to fix the issue.

Change description by vendor:
The Class-D K DC function has been added (which is the main solution
this time), along with enabling silence detect to filter out noise
below -84 dB to prevent it from being played through the speaker.

BUG=b:430749506
TEST= Build and boot to OS, and check by EE and Realtek vendor.

Change-Id: I3ac6cc82daf2ea78e73392ad67a5f4da131ddef5
Signed-off-by: Luca Lai <luca.lai@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88623
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
---
 .../google/brya/variants/pujjolo/hda_verb.c         | 13 +++++++++++--
 1 file changed, 11 insertions(+), 2 deletions(-)

diff --git a/src/mainboard/google/brya/variants/pujjolo/hda_verb.c b/src/mainboard/google/brya/variants/pujjolo/hda_verb.c
index d7f73667f6..ccbf6aacb4 100644
--- a/src/mainboard/google/brya/variants/pujjolo/hda_verb.c
+++ b/src/mainboard/google/brya/variants/pujjolo/hda_verb.c
@@ -6,7 +6,7 @@ const u32 cim_verb_data[] = {
 	/* coreboot specific header */
 	0x10ec0257,	// Codec Vendor / Device ID: Realtek ALC257
 	0x10ec0257,	// Subsystem ID
-	0x00000011,	// Number of jacks (NID entries)
+	0x00000012,	// Number of jacks (NID entries)
 
 	AZALIA_RESET(0x1),
 	/* NID 0x01, HDA Codec Subsystem ID Verb table */
@@ -35,6 +35,10 @@ const u32 cim_verb_data[] = {
 	0x0204C003,
 	0x0205001A,
 	0x0204C003,
+	0x05850000,
+	0x0584F880,
+	0x05850000,
+	0x0584F880,
 	//==========Widget node 0x20 - 1 : ClassD 2W
 	0x02050038,
 	0x02048981,
@@ -59,7 +63,7 @@ const u32 cim_verb_data[] = {
 	0x02050037,
 	0x0204FE15,
 	0x02050030,
-	0x02041000,
+	0x02049004,
 };
 
 const u32 pc_beep_verbs[] = {
@@ -73,6 +77,11 @@ const u32 pc_beep_verbs[] = {
 	0x0143B000,
 	0x01470C02,
 	0x01470C02,
+	/* Dos beep path - 3 */
+	0x0205000C,
+	0x020401FF,
+	0x00170503,
+	0x00170503,
 };
 
 AZALIA_ARRAY_SIZES;

From b486c84b23d2053efd3b6f5d1e1ee2db1c0f3dda Mon Sep 17 00:00:00 2001
From: Luca Lai <luca.lai@lcfc.corp-partner.google.com>
Date: Thu, 24 Jul 2025 18:46:07 +0800
Subject: [PATCH 1765/3886] mb/google/trulo/var/pujjolo: Update DTT settings
 for thermal control

The DPTF parameters were defined by the thermal team.
Based on thermal table in b:420800911#comment1

BUG=b:420800911
TEST=emerge-nissa coreboot chromeos-bootimage

Change-Id: I5fe20642505be50194084cd859e8fa20b4127dd0
Signed-off-by: Luca Lai <luca.lai@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88554
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 .../brya/variants/pujjolo/overridetree.cb     | 49 +++++++++++++++++++
 1 file changed, 49 insertions(+)

diff --git a/src/mainboard/google/brya/variants/pujjolo/overridetree.cb b/src/mainboard/google/brya/variants/pujjolo/overridetree.cb
index 30a8af33be..e64e3af278 100644
--- a/src/mainboard/google/brya/variants/pujjolo/overridetree.cb
+++ b/src/mainboard/google/brya/variants/pujjolo/overridetree.cb
@@ -170,6 +170,55 @@ chip soc/intel/alderlake
 	}"
 
 	device domain 0 on
+		device ref dtt on
+			chip drivers/intel/dptf
+				## sensor information
+				register "options.tsr[0].desc" = ""CPU""
+				register "options.tsr[1].desc" = ""DDR""
+				register "options.tsr[2].desc" = ""5VCharger""
+
+				## Passive Policy
+				register "policies.passive" = "{
+					[0] = DPTF_PASSIVE(CPU,         CPU,           90, 10000),
+					[1] = DPTF_PASSIVE(CPU,         TEMP_SENSOR_0, 80, 60000),
+					[2] = DPTF_PASSIVE(CPU,		TEMP_SENSOR_1, 80, 60000),
+					[3] = DPTF_PASSIVE(CHARGER,	TEMP_SENSOR_2, 75, 15000),
+				}"
+
+				## Critical Policy
+				register "policies.critical" = "{
+					[0] = DPTF_CRITICAL(CPU,               105, SHUTDOWN),
+					[1] = DPTF_CRITICAL(TEMP_SENSOR_0,     100, SHUTDOWN),
+					[2] = DPTF_CRITICAL(TEMP_SENSOR_1,     100, SHUTDOWN),
+					[3] = DPTF_CRITICAL(TEMP_SENSOR_2,     100, SHUTDOWN),
+				}"
+				register "controls.power_limits" = "{
+					.pl1 = {
+							.min_power = 3000,
+							.max_power = 6000,
+							.time_window_min = 1 * MSECS_PER_SEC,
+							.time_window_max = 1 * MSECS_PER_SEC,
+							.granularity = 200,
+						},
+					.pl2 = {
+							.min_power = 25000,
+							.max_power = 25000,
+							.time_window_min = 1 * MSECS_PER_SEC,
+							.time_window_max = 1 * MSECS_PER_SEC,
+							.granularity = 1000,
+						}
+				}"
+
+				## Charger Performance Control (Control, mA)
+				register "controls.charger_perf" = "{
+					[0] = { 255, 3000 },
+					[1] = {  24, 2000 },
+					[2] = {  16, 1500 },
+					[3] = {   8, 1000 }
+				}"
+				device generic 0 alias dptf_policy on end
+			end
+		end
 		device ref ipu on
 			chip drivers/intel/mipi_camera
 				register "acpi_uid" = "0x50000"

From fe6fa365044b037668997760a9ef137df47c11d6 Mon Sep 17 00:00:00 2001
From: Fabian Meyer <fabian.meyer@student.kit.edu>
Date: Thu, 15 May 2025 12:16:57 +0200
Subject: [PATCH 1766/3886] mb/asrock: Add SPR 1S server board ASRock Rack
 SPC741D8-2L2T/BCM

SPC741D8-2L2T/BCM is a Xeon SP 4th/5th gen (Eagle Stream) platform with:
- 1 SPR socket, 8 DDR5 DIMMs each
- 4x PCIe 5.0 / CXL 1.1 x16 slots
- 2x MCIO PCIe 5.0 x8 and 1 MCIO on PCH
- 2x M.2 PCH PCIe slots
- 2x 10 Gbit/s NIC and 2x 1 Gbit/s i210 NIC

It has an AST2600 BMC for remote management and most SuperIO functions
such as serial and an additional Nuvoton NCT6796D-E for others.

Working:
- All CPU cores of a 4/5th-gen Xeon SP are available at full speed
- All 8 memory DIMMs (KSM48R40BS8KMM-16HMR) with 32 bit execution
- All 4 PCIe slots
- On-board USB ports
- Video output via the AST2600 (on-board VGA)
- M.2 devices

Untested:
- TPM header

Not working:
- Serial port I/O, related to the AST2600 SuperIO not being located at
  the default address of 0x2E (it uses 0x4E instead).
- PC speaker (buzzer), for the same reason.
- M.2 SSDs only use PCIe 3.0 x2, however, they should be capable of
  PCIe 3.0 x4 speeds, which can be observed using the vendor firmware.
- Using more than 1 DIMM with 64 bit execution (the FSP
  temp_ram_exit function never returns)

TEST=build/boot to Linux 6.12 using mainline edk2

Change-Id: I5b00a6f4ee68f71203940644860bf095615a9412
Signed-off-by: Fabian Meyer <fabian.meyer@student.kit.edu>
Co-authored-by: Yussuf Khalil <yussuf.khalil@kit.edu>
Co-authored-by: Felix Zimmer <felix.zimmer@student.kit.edu>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87747
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
---
 configs/builder/config.asrock.spc741d8        |  16 ++
 src/mainboard/asrock/spc741d8/Kconfig         |  39 +++
 src/mainboard/asrock/spc741d8/Kconfig.name    |   2 +
 src/mainboard/asrock/spc741d8/Makefile.mk     |   8 +
 .../asrock/spc741d8/acpi/platform.asl         |  29 ++
 src/mainboard/asrock/spc741d8/board.fmd       |  17 ++
 src/mainboard/asrock/spc741d8/board_info.txt  |   7 +
 src/mainboard/asrock/spc741d8/bootblock.c     |  50 ++++
 src/mainboard/asrock/spc741d8/devicetree.cb   |  31 ++
 src/mainboard/asrock/spc741d8/dsdt.asl        |  27 ++
 src/mainboard/asrock/spc741d8/gpio.h          | 270 ++++++++++++++++++
 .../asrock/spc741d8/include/mainboard_iio.h   | 106 +++++++
 src/mainboard/asrock/spc741d8/ramstage.c      |  42 +++
 src/mainboard/asrock/spc741d8/romstage.c      |  68 +++++
 src/mainboard/asrock/spc741d8/util.c          |  10 +
 15 files changed, 722 insertions(+)
 create mode 100644 configs/builder/config.asrock.spc741d8
 create mode 100644 src/mainboard/asrock/spc741d8/Kconfig
 create mode 100644 src/mainboard/asrock/spc741d8/Kconfig.name
 create mode 100644 src/mainboard/asrock/spc741d8/Makefile.mk
 create mode 100644 src/mainboard/asrock/spc741d8/acpi/platform.asl
 create mode 100644 src/mainboard/asrock/spc741d8/board.fmd
 create mode 100644 src/mainboard/asrock/spc741d8/board_info.txt
 create mode 100644 src/mainboard/asrock/spc741d8/bootblock.c
 create mode 100644 src/mainboard/asrock/spc741d8/devicetree.cb
 create mode 100644 src/mainboard/asrock/spc741d8/dsdt.asl
 create mode 100644 src/mainboard/asrock/spc741d8/gpio.h
 create mode 100644 src/mainboard/asrock/spc741d8/include/mainboard_iio.h
 create mode 100644 src/mainboard/asrock/spc741d8/ramstage.c
 create mode 100644 src/mainboard/asrock/spc741d8/romstage.c
 create mode 100644 src/mainboard/asrock/spc741d8/util.c

diff --git a/configs/builder/config.asrock.spc741d8 b/configs/builder/config.asrock.spc741d8
new file mode 100644
index 0000000000..4b6a468ff0
--- /dev/null
+++ b/configs/builder/config.asrock.spc741d8
@@ -0,0 +1,16 @@
+# This config is intended for ASRock Rack SPC741D8-2L2T boards based on Intel
+# Sapphire Rapids Scalable Processor (SPR-SP) chipset.
+#
+# Type this in coreboot root directory to get a working .config:
+#   make defconfig KBUILD_DEFCONFIG=configs/builder/config.asrock.spc741d8
+
+CONFIG_VENDOR_ASROCK=y
+CONFIG_BOARD_ASROCK_SPC741D8=y
+CONFIG_HAVE_IFD_BIN=y
+CONFIG_PAYLOAD_EDK2=y
+CONFIG_HAVE_ME_BIN=y
+CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION=y
+CONFIG_IFD_BIN_PATH="site-local/eaglestream/descriptor.bin"
+CONFIG_ME_BIN_PATH="site-local/eaglestream/me.bin"
+CONFIG_VALIDATE_INTEL_DESCRIPTOR=y
+CONFIG_GENERIC_LINEAR_FRAMEBUFFER=y
diff --git a/src/mainboard/asrock/spc741d8/Kconfig b/src/mainboard/asrock/spc741d8/Kconfig
new file mode 100644
index 0000000000..219b2603b8
--- /dev/null
+++ b/src/mainboard/asrock/spc741d8/Kconfig
@@ -0,0 +1,39 @@
+if BOARD_ASROCK_SPC741D8
+
+config BOARD_SPECIFIC_OPTIONS
+	def_bool y
+	select BOARD_ROMSIZE_KB_65536
+	select IPMI_KCS
+	select IPMI_KCS_ROMSTAGE
+	select IPMI_OCP
+	select MEMORY_MAPPED_TPM
+	select MAINBOARD_HAS_TPM2
+	select PLATFORM_USES_FSP2_X86_32
+	select SOC_INTEL_SAPPHIRERAPIDS_SP
+	select SUPERIO_ASPEED_AST2400
+	select DRIVERS_ASPEED_AST2050
+	select SUPERIO_NUVOTON_NCT6791D
+	select HAVE_ACPI_TABLES
+	select OCP_EWL
+	select HAVE_INTEL_FSP_REPO
+	select HAVE_X86_64_SUPPORT
+	select PAGE_TABLES_IN_CBFS
+
+config MAINBOARD_DIR
+	default "asrock/spc741d8"
+
+config MAINBOARD_PART_NUMBER
+	default "SPC741D8-2L2T/BCM"
+
+config FMDFILE
+	string
+	default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/board.fmd"
+
+config FSP_FD_PATH
+	default "3rdparty/fsp/EagleStreamFspBinPkg/Fsp.fd"
+
+config MAX_SOCKET
+	int
+	default 1
+
+endif
diff --git a/src/mainboard/asrock/spc741d8/Kconfig.name b/src/mainboard/asrock/spc741d8/Kconfig.name
new file mode 100644
index 0000000000..7723156609
--- /dev/null
+++ b/src/mainboard/asrock/spc741d8/Kconfig.name
@@ -0,0 +1,2 @@
+config BOARD_ASROCK_SPC741D8
+	bool "SPC741D8-2L2T/BCM"
diff --git a/src/mainboard/asrock/spc741d8/Makefile.mk b/src/mainboard/asrock/spc741d8/Makefile.mk
new file mode 100644
index 0000000000..b28d73c27a
--- /dev/null
+++ b/src/mainboard/asrock/spc741d8/Makefile.mk
@@ -0,0 +1,8 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
+bootblock-y += bootblock.c
+romstage-y += romstage.c
+romstage-y += util.c
+ramstage-y += ramstage.c
+ramstage-y += util.c
+CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/include
diff --git a/src/mainboard/asrock/spc741d8/acpi/platform.asl b/src/mainboard/asrock/spc741d8/acpi/platform.asl
new file mode 100644
index 0000000000..4853874f8c
--- /dev/null
+++ b/src/mainboard/asrock/spc741d8/acpi/platform.asl
@@ -0,0 +1,29 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+/* Enable ACPI _SWS methods */
+#include <soc/intel/common/acpi/acpi_wake_source.asl>
+#include <southbridge/intel/common/acpi/sleepstates.asl>
+
+/* Port 80 POST */
+OperationRegion (DBG0, SystemIO, 0x80, 0x02)
+Field (DBG0, ByteAcc, Lock, Preserve)
+{
+	IO80, 8,
+	IO81, 8
+}
+
+/*
+ * The _PTS method (Prepare To Sleep) is called before the OS is
+ * entering a sleep state. The sleep state number is passed in Arg0
+ */
+
+Method (_PTS, 1)
+{
+}
+
+/* The _WAK method is called on system wakeup */
+
+Method (_WAK, 1)
+{
+	Return (Package (){ 0, 0 })
+}
diff --git a/src/mainboard/asrock/spc741d8/board.fmd b/src/mainboard/asrock/spc741d8/board.fmd
new file mode 100644
index 0000000000..1c4f264c6f
--- /dev/null
+++ b/src/mainboard/asrock/spc741d8/board.fmd
@@ -0,0 +1,17 @@
+FLASH 64M {
+	SI_ALL@0x0 0x03000000 {
+		SI_DESC@0x0 0x1000
+		# SI_GBE@0x1000 0x2000
+		# SI_ME@0x3000 0x2fed000
+		SI_ME@0x1000 0x2fef000
+		SI_PT@0x2ff0000 0x10000
+	}
+	RW_MRC_CACHE@0x3000000 0x10000
+	SMMSTORE(PRESERVE) 256K
+	FMAP 0x800
+	RW_VPD(PRESERVE) 0x4000
+	RO_VPD(PRESERVE) 0x4000
+	# For CONSOLE_SPI_FLASH support
+	CONSOLE 0x20000
+	COREBOOT(CBFS)
+}
diff --git a/src/mainboard/asrock/spc741d8/board_info.txt b/src/mainboard/asrock/spc741d8/board_info.txt
new file mode 100644
index 0000000000..ae7ac07b9a
--- /dev/null
+++ b/src/mainboard/asrock/spc741d8/board_info.txt
@@ -0,0 +1,7 @@
+Vendor name: ASRock Rack
+Board name: SPC741D8-2L2T/BCM
+Category: server
+ROM protocol: SPI
+ROM package: SOIC-16
+ROM socketed: y
+Flashrom support: y
diff --git a/src/mainboard/asrock/spc741d8/bootblock.c b/src/mainboard/asrock/spc741d8/bootblock.c
new file mode 100644
index 0000000000..987d7c2374
--- /dev/null
+++ b/src/mainboard/asrock/spc741d8/bootblock.c
@@ -0,0 +1,50 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <bootblock_common.h>
+#include <device/pci_ops.h>
+#include <intelblocks/lpc_lib.h>
+#include <intelblocks/pcr.h>
+#include <soc/intel/common/block/lpc/lpc_def.h>
+#include <soc/pci_devs.h>
+#include <soc/pcr_ids.h>
+#include <superio/aspeed/ast2400/ast2400.h>
+#include <superio/aspeed/common/aspeed.h>
+#include <superio/nuvoton/common/nuvoton.h>
+#include <superio/nuvoton/nct6791d/nct6791d.h>
+#include <device/pnp_ops.h>
+
+#define PCR_DMI_LPCIOD	0x2770
+#define PCR_DMI_LPCIOE	0x2774
+
+void bootblock_mainboard_early_init(void)
+{
+	/*
+	 * Set up decoding windows on PCH over PCR. The CPU uses two of AST2600 SIO ports,
+	 * one is connected to debug header (SUART1) and another is used as SOL (SUART2).
+	 */
+	const uint16_t lpciod = (LPC_IOD_COMB_RANGE | LPC_IOD_COMA_RANGE);
+	const uint16_t lpcioe = (LPC_IOE_EC_4E_4F | LPC_IOE_COMB_EN | LPC_IOE_COMA_EN);
+
+	/* Open IO windows: 0x3f8 for com1 and 02f8 for com2 */
+	pcr_or32(PID_DMI, PCR_DMI_LPCIOD, lpciod);
+	/* LPC I/O enable: com1 and com2 */
+	pcr_or32(PID_DMI, PCR_DMI_LPCIOE, lpcioe);
+
+	/* Enable com1 (0x3f8), com2 (0x2f8) and superio (0x4e) */
+	pci_write_config16(PCH_DEV_LPC, LPC_IO_DECODE, lpciod);
+	pci_write_config16(PCH_DEV_LPC, LPC_IO_ENABLES, lpcioe);
+
+	/*
+	 * Disable the Nuvoton NCT6791D SuperIO UART1.  It is enabled by
+	 * default, but the AST2600's is connected to the serial port.
+	 */
+	const pnp_devfn_t nvt_serial_dev = PNP_DEV(0x2E, NCT6791D_SP1);
+	nuvoton_pnp_enter_conf_state(nvt_serial_dev);
+	pnp_set_logical_device(nvt_serial_dev);
+	pnp_set_enable(nvt_serial_dev, 0);
+	nuvoton_pnp_exit_conf_state(nvt_serial_dev);
+
+	/* Enable AST2600 SuperIO UART1 */
+	const pnp_devfn_t ast_serial_dev = PNP_DEV(0x4E, AST2400_SUART1);
+	aspeed_enable_serial(ast_serial_dev, CONFIG_TTYS0_BASE);
+}
diff --git a/src/mainboard/asrock/spc741d8/devicetree.cb b/src/mainboard/asrock/spc741d8/devicetree.cb
new file mode 100644
index 0000000000..0aef44c1de
--- /dev/null
+++ b/src/mainboard/asrock/spc741d8/devicetree.cb
@@ -0,0 +1,31 @@
+## SPDX-License-Identifier: GPL-2.0-or-later
+
+chip soc/intel/xeon_sp/spr
+	device domain 0 on
+		device pci 1f.0 on         # Intel device 1b81: PCH eSPI controller
+			chip superio/common
+				device pnp 4e.0 on
+					chip superio/aspeed/ast2400
+						register "use_espi" = "1"
+						device pnp 4e.2 on	# SUART1
+							io 0x60 = 0x3f8
+							irq 0x70 = 0x04
+						end
+						device pnp 4e.3 on # SUART2
+							io 0x60 = 0x2f8
+							irq 0x70 = 0x03
+						end
+					end
+				end
+			end
+			chip drivers/ipmi # BMC KCS
+				device pnp ca2.0 on end
+				register "bmc_i2c_address" = "0x20"
+				register "bmc_boot_timeout" = "60"
+			end
+			chip drivers/pc80/tpm # TPM
+				device pnp 0c31.0 on end
+			end
+		end
+	end
+end
diff --git a/src/mainboard/asrock/spc741d8/dsdt.asl b/src/mainboard/asrock/spc741d8/dsdt.asl
new file mode 100644
index 0000000000..817c61bff9
--- /dev/null
+++ b/src/mainboard/asrock/spc741d8/dsdt.asl
@@ -0,0 +1,27 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <acpi/acpi.h>
+DefinitionBlock(
+	"dsdt.aml",
+	"DSDT",
+	ACPI_DSDT_REV_2,
+	OEM_ID,
+	ACPI_TABLE_CREATOR,
+	0x20110725
+)
+{
+	#include <acpi/dsdt_top.asl>
+	#include "acpi/platform.asl"
+
+	#include <soc/intel/common/block/acpi/acpi/globalnvs.asl>
+
+	#include <cpu/intel/common/acpi/cpu.asl>
+
+	#include <soc/intel/xeon_sp/spr/acpi/uncore.asl>
+
+	// LPC related entries
+	Scope (\_SB.PC00)
+	{
+		#include <soc/intel/xeon_sp/spr/acpi/pch.asl>
+	}
+}
diff --git a/src/mainboard/asrock/spc741d8/gpio.h b/src/mainboard/asrock/spc741d8/gpio.h
new file mode 100644
index 0000000000..78c93f8889
--- /dev/null
+++ b/src/mainboard/asrock/spc741d8/gpio.h
@@ -0,0 +1,270 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef CFG_GPIO_H
+#define CFG_GPIO_H
+
+#include <gpio.h>
+
+#ifndef PAD_CFG_GPIO_BIDIRECT
+#define PAD_CFG_GPIO_BIDIRECT(pad, val, pull, rst, trig, own)		\
+	_PAD_CFG_STRUCT(pad,						\
+		PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_TRIG(trig) |	\
+		PAD_BUF(NO_DISABLE) | val,				\
+		PAD_PULL(pull) | PAD_CFG_OWN_GPIO(own))
+#endif
+
+/* Pad configuration was generated automatically using intelp2m utility */
+static const struct pad_config gpio_table[] = {
+
+	/* ------- GPIO Community 0 ------- */
+
+	/* ------- GPIO Group GPPC_A ------- */
+	PAD_CFG_NF(GPPC_A0, NONE, RSMRST, NF1),	/* ESPI_ALERT0_N */
+	PAD_CFG_NF(GPPC_A1, NONE, RSMRST, NF1),	/* ESPI_ALERT1_N */
+	PAD_CFG_NF(GPPC_A2, NONE, RSMRST, NF1),	/* ESPI_IO_0 */
+	PAD_CFG_NF(GPPC_A3, NONE, RSMRST, NF1),	/* ESPI_IO_1 */
+	PAD_CFG_NF(GPPC_A4, NONE, RSMRST, NF1),	/* ESPI_IO_2 */
+	PAD_CFG_NF(GPPC_A5, NONE, RSMRST, NF1),	/* ESPI_IO_3 */
+	PAD_CFG_NF(GPPC_A6, NONE, RSMRST, NF1),	/* ESPI_CS0_N */
+	PAD_CFG_NF(GPPC_A7, NONE, RSMRST, NF1),	/* ESPI_CS1_N */
+	PAD_CFG_NF(GPPC_A8, NONE, RSMRST, NF1),	/* ESPI_RESET_N */
+	PAD_CFG_NF(GPPC_A9, NONE, RSMRST, NF1),	/* ESPI_CLK */
+	PAD_CFG_GPI_TRIG_OWN(GPPC_A10, NONE, RSMRST, OFF, ACPI),	/* GPIO */
+	PAD_CFG_GPI_TRIG_OWN(GPPC_A11, NONE, RSMRST, OFF, ACPI),	/* GPIO */
+	PAD_CFG_GPI_TRIG_OWN(GPPC_A12, NONE, RSMRST, OFF, ACPI),	/* GPIO */
+	PAD_CFG_GPO(GPPC_A13, 0, RSMRST),	/* GPIO */
+	PAD_NC(GPPC_A14, NONE),	/* GPIO */
+	PAD_NC(GPPC_A15, NONE),	/* GPIO */
+	PAD_CFG_GPIO_BIDIRECT(GPPC_A16, 0, NONE, DEEP, OFF, ACPI),	/* GPIO */
+	PAD_CFG_GPI_TRIG_OWN(GPPC_A17, NONE, RSMRST, OFF, ACPI),	/* GPIO */
+	PAD_CFG_GPI_TRIG_OWN(GPPC_A18, NONE, RSMRST, OFF, ACPI),	/* GPIO */
+	PAD_CFG_GPI_TRIG_OWN(GPPC_A19, NONE, RSMRST, OFF, ACPI),	/* GPIO */
+
+	/* ------- GPIO Group GPPC_B ------- */
+	PAD_CFG_GPI_TRIG_OWN(GPPC_B0, NONE, RSMRST, OFF, ACPI),	/* GPIO */
+	PAD_CFG_GPI_TRIG_OWN(GPPC_B1, NONE, RSMRST, OFF, ACPI),	/* GPIO */
+	PAD_CFG_GPI_TRIG_OWN(GPPC_B2, NONE, RSMRST, OFF, ACPI),	/* GPIO */
+	PAD_CFG_GPI_TRIG_OWN(GPPC_B3, NONE, RSMRST, OFF, ACPI),	/* GPIO */
+	PAD_CFG_GPI_TRIG_OWN(GPPC_B4, NONE, RSMRST, OFF, ACPI),	/* GPIO */
+	PAD_CFG_NF(GPPC_B5, NONE, RSMRST, NF1),	/* USB2_OC0_N */
+	PAD_CFG_NF(GPPC_B6, NONE, RSMRST, NF1),	/* USB2_OC1_N */
+	PAD_CFG_NF(GPPC_B7, NONE, RSMRST, NF1),	/* USB2_OC2_N */
+	PAD_CFG_GPI_TRIG_OWN(GPPC_B8, NONE, RSMRST, OFF, ACPI),	/* GPIO */
+	PAD_CFG_GPI_TRIG_OWN(GPPC_B9, NONE, RSMRST, OFF, ACPI),	/* GPIO */
+	PAD_CFG_GPI_TRIG_OWN(GPPC_B10, NONE, RSMRST, OFF, ACPI),	/* GPIO */
+	PAD_CFG_GPO(GPPC_B11, 1, PLTRST),	/* GPIO */
+	PAD_CFG_NF(GPPC_B12, NONE, DEEP, NF4),	/* 1P8_PTI_DATA5 */
+	PAD_CFG_NF(GPPC_B13, NONE, DEEP, NF4),	/* 1P8_PTI_DATA6 */
+	PAD_CFG_NF(GPPC_B14, NONE, DEEP, NF4),	/* 1P8_PTI_DATA7 */
+	PAD_CFG_NF(GPPC_B15, NONE, DEEP, NF4),	/* 1P8_PTI_DATA8 */
+	PAD_CFG_GPI_TRIG_OWN(GPPC_B16, NONE, RSMRST, OFF, ACPI),	/* GPIO */
+	PAD_CFG_GPI_TRIG_OWN(GPPC_B17, NONE, RSMRST, OFF, ACPI),	/* GPIO */
+	PAD_CFG_GPI_TRIG_OWN(GPPC_B18, NONE, RSMRST, OFF, ACPI),	/* GPIO */
+	PAD_CFG_GPI_TRIG_OWN(GPPC_B19, NONE, RSMRST, OFF, ACPI),	/* GPIO */
+	PAD_CFG_GPI_TRIG_OWN(GPPC_B20, NONE, RSMRST, OFF, ACPI),	/* GPIO */
+	PAD_CFG_GPI_TRIG_OWN(GPPC_B21, NONE, RSMRST, OFF, ACPI),	/* GPIO */
+	PAD_CFG_GPO(GPPC_B22, 0, RSMRST),	/* GPIO */
+	PAD_CFG_GPI_TRIG_OWN(GPPC_B23, NONE, RSMRST, OFF, ACPI),	/* GPIO */
+
+	/* ------- GPIO Group GPPC_S ------- */
+	PAD_CFG_GPI_TRIG_OWN(GPPC_S0, NONE, RSMRST, OFF, ACPI),	/* GPIO */
+	PAD_CFG_NF(GPPC_S1, NONE, DEEP, NF1),	/* SPRK */
+	PAD_CFG_GPI_TRIG_OWN(GPPC_S2, NONE, RSMRST, OFF, ACPI),	/* GPIO */
+	PAD_CFG_GPI_TRIG_OWN(GPPC_S3, NONE, DEEP, OFF, ACPI),	/* GPIO */
+	PAD_CFG_GPI_TRIG_OWN(GPPC_S4, NONE, RSMRST, OFF, ACPI),	/* GPIO */
+	PAD_CFG_GPI_TRIG_OWN(GPPC_S5, NONE, RSMRST, OFF, ACPI),	/* GPIO */
+	PAD_CFG_GPI_TRIG_OWN(GPPC_S6, NONE, RSMRST, OFF, ACPI),	/* GPIO */
+	PAD_CFG_NF(GPPC_S7, NONE, RSMRST, NF1),	/* SUSACK_N */
+	PAD_CFG_NF(GPPC_S8, NONE, RSMRST, NF1),	/* NMI_N */
+	PAD_CFG_GPI_SMI(GPPC_S9, NONE, DEEP, LEVEL, INVERT),	/* GPIO */
+	PAD_CFG_GPI_TRIG_OWN(GPPC_S10, NONE, RSMRST, OFF, ACPI),	/* GPIO */
+	PAD_CFG_GPI_TRIG_OWN(GPPC_S11, NONE, RSMRST, OFF, ACPI),	/* GPIO */
+
+	/* ------- GPIO Community 1 ------- */
+
+	/* ------- GPIO Group GPPC_C ------- */
+	/* GPPC_C0 - RESERVED */
+	/* GPPC_C1 - RESERVED */
+	PAD_CFG_NF(GPPC_C2, NONE, DEEP, NF1),	/* ME_SML0ALERT_N */
+	PAD_CFG_GPI_TRIG_OWN(GPPC_C3, NONE, RSMRST, OFF, ACPI),	/* GPIO */
+	PAD_CFG_GPI_TRIG_OWN(GPPC_C4, NONE, RSMRST, OFF, ACPI),	/* GPIO */
+	PAD_CFG_GPO(GPPC_C5, 1, PLTRST),	/* GPIO */
+	/* GPPC_C6 - RESERVED */
+	/* GPPC_C7 - RESERVED */
+	/* GPPC_C8 - RESERVED */
+	PAD_NC(GPPC_C9, NONE),	/* GPIO */
+	PAD_CFG_GPI_TRIG_OWN(GPPC_C10, NONE, RSMRST, OFF, ACPI),	/* GPIO */
+	/* GPPC_C11 - RESERVED */
+	/* GPPC_C12 - RESERVED */
+	/* GPPC_C13 - RESERVED */
+	/* GPPC_C14 - RESERVED */
+	PAD_NC(GPPC_C15, NONE),	/* GPIO */
+	PAD_NC(GPPC_C16, NONE),	/* GPIO */
+	PAD_CFG_GPO(GPPC_C17, 0, RSMRST),	/* GPIO */
+	PAD_CFG_GPI_TRIG_OWN(GPPC_C18, NONE, RSMRST, OFF, ACPI),	/* GPIO */
+	PAD_CFG_GPI_TRIG_OWN(GPPC_C19, NONE, RSMRST, OFF, ACPI),	/* GPIO */
+	PAD_CFG_GPI_TRIG_OWN(GPPC_C20, NONE, RSMRST, OFF, ACPI),	/* GPIO */
+	PAD_CFG_GPI_SCI(GPPC_C21, NONE, DEEP, LEVEL, INVERT),	/* GPIO */
+
+	/* ------- GPIO Group GPP_D ------- */
+	/* GPP_D0 - RESERVED */
+	/* GPP_D1 - RESERVED */
+	PAD_CFG_GPI_TRIG_OWN(GPP_D2, NONE, RSMRST, OFF, ACPI),	/* GPIO */
+	PAD_CFG_GPI_TRIG_OWN(GPP_D3, NONE, RSMRST, OFF, ACPI),	/* GPIO */
+	PAD_CFG_GPI_TRIG_OWN(GPP_D4, NONE, RSMRST, OFF, ACPI),	/* GPIO */
+	PAD_CFG_GPI_TRIG_OWN(GPP_D5, NONE, RSMRST, OFF, ACPI),	/* GPIO */
+	PAD_CFG_GPI_TRIG_OWN(GPP_D6, NONE, RSMRST, OFF, ACPI),	/* GPIO */
+	PAD_CFG_GPI_TRIG_OWN(GPP_D7, NONE, RSMRST, OFF, ACPI),	/* GPIO */
+	PAD_CFG_NF(GPP_D8, NONE, RSMRST, NF1),	/* CRASHLOG_TRIG_N */
+	PAD_CFG_GPI_TRIG_OWN(GPP_D9, NONE, RSMRST, OFF, ACPI),	/* GPIO */
+	PAD_CFG_GPI_TRIG_OWN(GPP_D10, NONE, RSMRST, OFF, ACPI),	/* GPIO */
+	PAD_CFG_NF(GPP_D11, NONE, RSMRST, NF1),	/* PLTRST_N */
+	PAD_CFG_NF(GPP_D12, NONE, RSMRST, NF1),	/* PCHHOT_N */
+	/* GPP_D13 - RESERVED */
+	PAD_CFG_NF(GPP_D14, NONE, RSMRST, NF1),	/* ADR_TRIGGER */
+	PAD_CFG_GPI_TRIG_OWN(GPP_D15, NONE, RSMRST, OFF, ACPI),	/* GPIO */
+	PAD_CFG_NF(GPP_D16, NONE, RSMRST, NF1),	/* ADR_ACK */
+	/* GPP_D17 - RESERVED */
+	PAD_CFG_GPI_TRIG_OWN(GPP_D18, NONE, RSMRST, OFF, ACPI),	/* GPIO */
+	PAD_CFG_GPI_TRIG_OWN(GPP_D19, NONE, RSMRST, OFF, ACPI),	/* GPIO */
+	PAD_CFG_GPI_TRIG_OWN(GPP_D20, NONE, RSMRST, OFF, ACPI),	/* GPIO */
+	PAD_CFG_NF(GPP_D21, NONE, RSMRST, NF1),	/* GLB_RST_WARN_N */
+	PAD_CFG_GPI_TRIG_OWN(GPP_D22, NONE, RSMRST, OFF, ACPI),	/* GPIO */
+	PAD_CFG_GPI_TRIG_OWN(GPP_D23, NONE, RSMRST, OFF, ACPI),	/* GPIO */
+
+	/* ------- GPIO Community 3 ------- */
+
+	/* ------- GPIO Group GPP_E ------- */
+	PAD_CFG_GPI_NMI(GPP_E0, NONE, PLTRST, LEVEL, INVERT),	/* GPIO */
+	PAD_CFG_GPI_TRIG_OWN(GPP_E1, NONE, RSMRST, OFF, ACPI),	/* GPIO */
+	PAD_CFG_NF(GPP_E2, NONE, RSMRST, NF1),	/* SATA1_XPCIE_2 */
+	PAD_CFG_NF(GPP_E3, NONE, RSMRST, NF1),	/* SATA1_XPCIE_3 */
+	PAD_CFG_NF(GPP_E4, NONE, RSMRST, NF1),	/* SATA0_XPCIE_2 */
+	PAD_CFG_NF(GPP_E5, NONE, RSMRST, NF1),	/* SATA0_XPCIE_1 */
+	PAD_CFG_NF(GPP_E6, NONE, RSMRST, NF1),	/* SATA0_USB3_XPCIE_0 */
+	PAD_CFG_NF(GPP_E7, NONE, RSMRST, NF1),	/* SATA0_USB3_XPCIE_1 */
+	PAD_CFG_NF(GPP_E8, NONE, PLTRST, NF2),	/* SATA0_LED_N */
+	PAD_CFG_GPI_TRIG_OWN(GPP_E9, NONE, PLTRST, OFF, ACPI),	/* GPIO */
+	PAD_CFG_GPI_TRIG_OWN(GPP_E10, NONE, PLTRST, OFF, ACPI),	/* GPIO */
+	PAD_CFG_GPI_TRIG_OWN(GPP_E11, NONE, PLTRST, OFF, ACPI),	/* GPIO */
+	PAD_CFG_GPI_TRIG_OWN(GPP_E12, NONE, PLTRST, OFF, ACPI),	/* GPIO */
+	PAD_CFG_GPI_TRIG_OWN(GPP_E13, NONE, PLTRST, OFF, ACPI),	/* GPIO */
+	PAD_CFG_GPI_TRIG_OWN(GPP_E14, NONE, PLTRST, OFF, ACPI),	/* GPIO */
+	PAD_CFG_GPI_TRIG_OWN(GPP_E15, NONE, PLTRST, OFF, ACPI),	/* GPIO */
+	PAD_CFG_GPI_TRIG_OWN(GPP_E16, NONE, PLTRST, OFF, ACPI),	/* GPIO */
+	PAD_CFG_GPI_TRIG_OWN(GPP_E17, NONE, RSMRST, OFF, ACPI),	/* GPIO */
+	PAD_CFG_GPI_TRIG_OWN(GPP_E18, NONE, RSMRST, OFF, ACPI),	/* GPIO */
+	PAD_CFG_GPI_TRIG_OWN(GPP_E19, NONE, RSMRST, OFF, ACPI),	/* GPIO */
+
+	/* ------- GPIO Group JTAG ------- */
+
+	/* ------- GPIO Community 4 ------- */
+
+	/* ------- GPIO Group GPPC_H ------- */
+	PAD_CFG_GPI_TRIG_OWN(GPPC_H0, NONE, RSMRST, OFF, ACPI),	/* GPIO */
+	/* GPPC_H1 - RESERVED */
+	PAD_CFG_GPI_TRIG_OWN(GPPC_H2, NONE, RSMRST, OFF, ACPI),	/* GPIO */
+	PAD_CFG_GPI_TRIG_OWN(GPPC_H3, NONE, RSMRST, OFF, ACPI),	/* GPIO */
+	PAD_CFG_GPI_TRIG_OWN(GPPC_H4, NONE, RSMRST, OFF, ACPI),	/* GPIO */
+	PAD_CFG_GPI_TRIG_OWN(GPPC_H5, NONE, RSMRST, OFF, ACPI),	/* GPIO */
+	PAD_CFG_GPI_TRIG_OWN(GPPC_H6, NONE, RSMRST, OFF, ACPI),	/* GPIO */
+	PAD_CFG_GPI_TRIG_OWN(GPPC_H7, NONE, RSMRST, OFF, ACPI),	/* GPIO */
+	PAD_CFG_GPI_TRIG_OWN(GPPC_H8, NONE, RSMRST, OFF, ACPI),	/* GPIO */
+	PAD_CFG_GPI_TRIG_OWN(GPPC_H9, NONE, RSMRST, OFF, ACPI),	/* GPIO */
+	PAD_CFG_GPI_TRIG_OWN(GPPC_H10, NONE, RSMRST, OFF, ACPI),	/* GPIO */
+	PAD_CFG_GPI_TRIG_OWN(GPPC_H11, NONE, RSMRST, OFF, ACPI),	/* GPIO */
+	PAD_CFG_GPI_TRIG_OWN(GPPC_H12, NONE, RSMRST, OFF, ACPI),	/* GPIO */
+	PAD_CFG_GPI_TRIG_OWN(GPPC_H13, NONE, RSMRST, OFF, ACPI),	/* GPIO */
+	PAD_CFG_GPI_TRIG_OWN(GPPC_H14, NONE, RSMRST, OFF, ACPI),	/* GPIO */
+	PAD_CFG_GPO(GPPC_H15, 0, PLTRST),	/* GPIO */
+	PAD_CFG_GPI_TRIG_OWN(GPPC_H16, NONE, RSMRST, OFF, ACPI),	/* GPIO */
+	PAD_CFG_GPI_TRIG_OWN(GPPC_H17, NONE, RSMRST, OFF, ACPI),	/* GPIO */
+	PAD_CFG_GPO(GPPC_H18, 0, PLTRST),	/* GPIO */
+	PAD_CFG_GPI_TRIG_OWN(GPPC_H19, NONE, RSMRST, OFF, ACPI),	/* GPIO */
+
+	/* ------- GPIO Group GPP_J ------- */
+	PAD_CFG_NF(GPP_J0, NONE, DEEP, NF1),	/* CPUPWRGD */
+	/* GPP_J1 - RESERVED */
+	PAD_CFG_NF(GPP_J2, NONE, DEEP, NF1),	/* PLTRST_CPU_N */
+	PAD_CFG_NF(GPP_J3, NONE, DEEP, NF1),	/* TRIGGER0_N */
+	PAD_CFG_NF(GPP_J4, NONE, DEEP, NF1),	/* TRIGGER1_N */
+	/* GPP_J5 - RESERVED */
+	PAD_CFG_GPI_TRIG_OWN(GPP_J6, NONE, DEEP, OFF, ACPI),	/* GPIO */
+	PAD_CFG_GPI_TRIG_OWN(GPP_J7, NONE, DEEP, OFF, ACPI),	/* GPIO */
+	/* GPP_J8 - RESERVED */
+	PAD_CFG_GPI_TRIG_OWN(GPP_J9, NONE, DEEP, OFF, ACPI),	/* GPIO */
+	PAD_CFG_GPI_TRIG_OWN(GPP_J10, NONE, DEEP, OFF, ACPI),	/* GPIO */
+	PAD_CFG_GPI_TRIG_OWN(GPP_J11, NONE, DEEP, OFF, ACPI),	/* GPIO */
+	PAD_CFG_GPI_TRIG_OWN(GPP_J12, UP_20K, DEEP, OFF, ACPI),	/* GPIO */
+	PAD_CFG_GPI_TRIG_OWN(GPP_J13, NONE, DEEP, OFF, ACPI),	/* GPIO */
+	PAD_CFG_GPI_TRIG_OWN(GPP_J14, UP_20K, DEEP, OFF, ACPI),	/* GPIO */
+	PAD_CFG_GPI_TRIG_OWN(GPP_J15, UP_20K, DEEP, OFF, ACPI),	/* GPIO */
+
+	/* ------- GPIO Community 5 ------- */
+
+	/* ------- GPIO Group GPP_I ------- */
+	PAD_CFG_GPI_TRIG_OWN(GPP_I0, NONE, RSMRST, OFF, ACPI),	/* GPIO */
+	PAD_CFG_GPI_TRIG_OWN(GPP_I1, NONE, RSMRST, OFF, ACPI),	/* GPIO */
+	PAD_CFG_GPI_TRIG_OWN(GPP_I2, NONE, RSMRST, OFF, ACPI),	/* GPIO */
+	PAD_CFG_GPI_TRIG_OWN(GPP_I3, NONE, RSMRST, OFF, ACPI),	/* GPIO */
+	PAD_CFG_GPI_TRIG_OWN(GPP_I4, NONE, RSMRST, OFF, ACPI),	/* GPIO */
+	PAD_CFG_GPI_TRIG_OWN(GPP_I5, NONE, RSMRST, OFF, ACPI),	/* GPIO */
+	PAD_CFG_GPI_TRIG_OWN(GPP_I6, NONE, RSMRST, OFF, ACPI),	/* GPIO */
+	PAD_CFG_GPI_TRIG_OWN(GPP_I7, NONE, RSMRST, OFF, ACPI),	/* GPIO */
+	PAD_CFG_GPI_TRIG_OWN(GPP_I8, NONE, RSMRST, OFF, ACPI),	/* GPIO */
+	PAD_CFG_GPI_TRIG_OWN(GPP_I9, NONE, RSMRST, OFF, ACPI),	/* GPIO */
+	PAD_CFG_GPI_TRIG_OWN(GPP_I10, NONE, RSMRST, OFF, ACPI),	/* GPIO */
+	PAD_CFG_GPI_TRIG_OWN(GPP_I11, NONE, RSMRST, OFF, ACPI),	/* GPIO */
+	PAD_CFG_GPI_TRIG_OWN(GPP_I12, NONE, RSMRST, OFF, ACPI),	/* GPIO */
+	PAD_CFG_GPI_TRIG_OWN(GPP_I13, NONE, RSMRST, OFF, ACPI),	/* GPIO */
+	PAD_CFG_GPI_TRIG_OWN(GPP_I14, NONE, RSMRST, OFF, ACPI),	/* GPIO */
+	PAD_CFG_GPI_TRIG_OWN(GPP_I15, NONE, RSMRST, OFF, ACPI),	/* GPIO */
+	PAD_CFG_GPI_TRIG_OWN(GPP_I16, NONE, RSMRST, OFF, ACPI),	/* GPIO */
+	PAD_CFG_GPI_TRIG_OWN(GPP_I17, NONE, RSMRST, OFF, ACPI),	/* GPIO */
+	PAD_CFG_GPI_TRIG_OWN(GPP_I18, NONE, RSMRST, OFF, ACPI),	/* GPIO */
+	PAD_CFG_GPI_TRIG_OWN(GPP_I19, NONE, RSMRST, OFF, ACPI),	/* GPIO */
+	PAD_CFG_GPI_TRIG_OWN(GPP_I20, NONE, RSMRST, OFF, ACPI),	/* GPIO */
+	PAD_CFG_GPI_TRIG_OWN(GPP_I21, NONE, RSMRST, OFF, ACPI),	/* GPIO */
+	PAD_CFG_GPI_TRIG_OWN(GPP_I22, NONE, RSMRST, OFF, ACPI),	/* GPIO */
+	PAD_CFG_GPI_TRIG_OWN(GPP_I23, NONE, RSMRST, OFF, ACPI),	/* GPIO */
+
+	/* ------- GPIO Group GPP_L ------- */
+	/* GPP_L0 - RESERVED */
+	/* GPP_L1 - RESERVED */
+	PAD_CFG_GPI_TRIG_OWN(GPP_L2, NONE, RSMRST, OFF, ACPI),	/* GPIO */
+	PAD_CFG_GPI_TRIG_OWN(GPP_L3, NONE, RSMRST, OFF, ACPI),	/* GPIO */
+	/* GPP_L4 - RESERVED */
+	PAD_CFG_GPI_TRIG_OWN(GPP_L5, NONE, RSMRST, OFF, ACPI),	/* GPIO */
+	PAD_CFG_GPI_TRIG_OWN(GPP_L6, NONE, RSMRST, OFF, ACPI),	/* GPIO */
+	PAD_CFG_GPI_TRIG_OWN(GPP_L7, NONE, RSMRST, OFF, ACPI),	/* GPIO */
+	PAD_CFG_GPI_TRIG_OWN(GPP_L8, NONE, RSMRST, OFF, ACPI),	/* GPIO */
+
+	/* ------- GPIO Group GPP_M ------- */
+	PAD_CFG_GPI_TRIG_OWN(GPP_M0, NONE, RSMRST, OFF, ACPI),	/* GPIO */
+	PAD_CFG_GPI_TRIG_OWN(GPP_M1, NONE, RSMRST, OFF, ACPI),	/* GPIO */
+	PAD_CFG_GPI_TRIG_OWN(GPP_M2, NONE, RSMRST, OFF, ACPI),	/* GPIO */
+	PAD_CFG_GPI_TRIG_OWN(GPP_M3, NONE, RSMRST, OFF, ACPI),	/* GPIO */
+	PAD_CFG_GPI_TRIG_OWN(GPP_M4, NONE, RSMRST, OFF, ACPI),	/* GPIO */
+	PAD_CFG_GPI_TRIG_OWN(GPP_M5, NONE, RSMRST, OFF, ACPI),	/* GPIO */
+	PAD_CFG_GPI_TRIG_OWN(GPP_M6, NONE, RSMRST, OFF, ACPI),	/* GPIO */
+	PAD_CFG_GPI_TRIG_OWN(GPP_M7, NONE, RSMRST, OFF, ACPI),	/* GPIO */
+	PAD_CFG_GPI_TRIG_OWN(GPP_M8, NONE, RSMRST, OFF, ACPI),	/* GPIO */
+	PAD_CFG_GPI_TRIG_OWN(GPP_M9, NONE, RSMRST, OFF, ACPI),	/* GPIO */
+	PAD_CFG_GPI_TRIG_OWN(GPP_M10, NONE, RSMRST, OFF, ACPI),	/* GPIO */
+	PAD_CFG_GPI_TRIG_OWN(GPP_M11, NONE, RSMRST, OFF, ACPI),	/* GPIO */
+	PAD_CFG_GPI_TRIG_OWN(GPP_M12, NONE, RSMRST, OFF, ACPI),	/* GPIO */
+	PAD_CFG_GPI_TRIG_OWN(GPP_M13, NONE, RSMRST, OFF, ACPI),	/* GPIO */
+	PAD_CFG_GPI_TRIG_OWN(GPP_M14, NONE, RSMRST, OFF, ACPI),	/* GPIO */
+	PAD_CFG_GPI_TRIG_OWN(GPP_M15, NONE, RSMRST, OFF, ACPI),	/* GPIO */
+	PAD_CFG_GPI_TRIG_OWN(GPP_M16, NONE, RSMRST, OFF, ACPI),	/* GPIO */
+	PAD_CFG_GPI_TRIG_OWN(GPP_M17, NONE, RSMRST, OFF, ACPI),	/* GPIO */
+
+	/* ------- GPIO Group GPP_N ------- */
+	PAD_CFG_GPI_TRIG_OWN(GPP_N0, NONE, RSMRST, OFF, ACPI),	/* GPIO */
+	PAD_CFG_GPI_TRIG_OWN(GPP_N1, NONE, RSMRST, OFF, ACPI),	/* GPIO */
+	PAD_CFG_GPI_TRIG_OWN(GPP_N2, NONE, RSMRST, OFF, ACPI),	/* GPIO */
+	PAD_CFG_GPI_TRIG_OWN(GPP_N3, NONE, RSMRST, OFF, ACPI),	/* GPIO */
+	PAD_CFG_GPI_TRIG_OWN(GPP_N4, NONE, RSMRST, OFF, ACPI),	/* GPIO */
+};
+
+#endif /* CFG_GPIO_H */
diff --git a/src/mainboard/asrock/spc741d8/include/mainboard_iio.h b/src/mainboard/asrock/spc741d8/include/mainboard_iio.h
new file mode 100644
index 0000000000..940e9331c4
--- /dev/null
+++ b/src/mainboard/asrock/spc741d8/include/mainboard_iio.h
@@ -0,0 +1,106 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#ifndef _MAINBOARD_IIO_H_
+#define _MAINBOARD_IIO_H_
+
+#include <defs_iio.h>
+#include <soc/soc_util.h>
+
+/* For now only set 3 fields and hard-coded others, should be extended in the future */
+#define CFG_UPD_PCIE_PORT(pexphide, slotimp, slotpsp)	\
+	{						\
+		.SLOTEIP = 0,				\
+		.SLOTHPCAP = 0,				\
+		.SLOTHPSUP = 0,				\
+		.SLOTPIP = 0,				\
+		.SLOTAIP = 0,				\
+		.SLOTMRLSP = 0,				\
+		.SLOTPCP = 0,				\
+		.SLOTABP = 0,				\
+		.SLOTIMP = slotimp,			\
+		.SLOTSPLS = 0,				\
+		.SLOTSPLV = 0,				\
+		.SLOTPSP = slotpsp,			\
+		.VppEnabled = 0,			\
+		.VppPort = 0,				\
+		.VppAddress = 0,			\
+		.MuxAddress = 0,			\
+		.ChannelID = 0,				\
+		.PciePortEnable = 1,			\
+		.PEXPHIDE = pexphide,			\
+		.HidePEXPMenu = 0,			\
+		.PciePortOwnership = 0,			\
+		.RetimerConnectCount = 0,		\
+		.PcieMaxPayload = 0x7,			\
+		.PciePortLinkSpeed = 0,			\
+		.DfxDnTxPresetGen3 = 0xFF		\
+	}
+
+#define CFG_UPD_PCIE_PORT_DISABLED CFG_UPD_PCIE_PORT(1, 0, 0)
+
+/*
+ * SPC741D8-2L2T IIO PCIe Port Table
+ */
+static const UPD_IIO_PCIE_PORT_CONFIG_ENTRY iio_pci_port[CONFIG_MAX_SOCKET][IIO_PORT_SETTINGS] = {
+	{
+	/* DMI port: array index 0 */
+	CFG_UPD_PCIE_PORT(0, 0, 0),
+	/* IOU0 (PE0): array index 1 ~ 8 */
+	CFG_UPD_PCIE_PORT(0, 1, 1), /* 15:01.0 */
+	CFG_UPD_PCIE_PORT_DISABLED,
+	CFG_UPD_PCIE_PORT_DISABLED,
+	CFG_UPD_PCIE_PORT_DISABLED,
+	CFG_UPD_PCIE_PORT_DISABLED,
+	CFG_UPD_PCIE_PORT_DISABLED,
+	CFG_UPD_PCIE_PORT_DISABLED,
+	CFG_UPD_PCIE_PORT_DISABLED,
+	/* IOU1 (PE1): array index 9 ~ 16 */
+	CFG_UPD_PCIE_PORT(0, 1, 9), /* 26:01.0 */
+	CFG_UPD_PCIE_PORT_DISABLED,
+	CFG_UPD_PCIE_PORT_DISABLED,
+	CFG_UPD_PCIE_PORT_DISABLED,
+	CFG_UPD_PCIE_PORT_DISABLED,
+	CFG_UPD_PCIE_PORT_DISABLED,
+	CFG_UPD_PCIE_PORT_DISABLED,
+	CFG_UPD_PCIE_PORT_DISABLED,
+	/* IOU2 (PE2): array index 17 ~ 24 */
+	CFG_UPD_PCIE_PORT(0, 1, 17), /* 37:01.0 */
+	CFG_UPD_PCIE_PORT_DISABLED,
+	CFG_UPD_PCIE_PORT_DISABLED,
+	CFG_UPD_PCIE_PORT_DISABLED,
+	CFG_UPD_PCIE_PORT_DISABLED,
+	CFG_UPD_PCIE_PORT_DISABLED,
+	CFG_UPD_PCIE_PORT_DISABLED,
+	CFG_UPD_PCIE_PORT_DISABLED,
+	/* IOU3 (PE3): array index 25 ~ 32 */
+	CFG_UPD_PCIE_PORT(0, 1, 25), /* 48:01.0 */
+	CFG_UPD_PCIE_PORT_DISABLED,
+	CFG_UPD_PCIE_PORT_DISABLED,
+	CFG_UPD_PCIE_PORT_DISABLED,
+	CFG_UPD_PCIE_PORT_DISABLED,
+	CFG_UPD_PCIE_PORT_DISABLED,
+	CFG_UPD_PCIE_PORT_DISABLED,
+	CFG_UPD_PCIE_PORT_DISABLED,
+	/* IOU4 (PE4): array index 33 ~ 40 */
+	CFG_UPD_PCIE_PORT(0, 1, 33), /* 59:01.0 */
+	CFG_UPD_PCIE_PORT_DISABLED,
+	CFG_UPD_PCIE_PORT_DISABLED,
+	CFG_UPD_PCIE_PORT_DISABLED,
+	CFG_UPD_PCIE_PORT(0, 1, 37), /* 59:05.0 */
+	CFG_UPD_PCIE_PORT_DISABLED,
+	CFG_UPD_PCIE_PORT_DISABLED,
+	CFG_UPD_PCIE_PORT_DISABLED,
+	},
+};
+
+static const UINT8 iio_bifur[CONFIG_MAX_SOCKET][5] = {
+	// Note: When changing, also update port configurations above.
+	{
+		IIO_BIFURCATE_xxxxxx16, /* physical slot PCIE3 */
+		IIO_BIFURCATE_xxxxxx16, /* physical slot PCIE5 */
+		IIO_BIFURCATE_xxxxxx16, /* physical slot PCIE1 (farthest from CPU) */
+		IIO_BIFURCATE_xxxxxx16, /* physical slot PCIE7 (closest to CPU) */
+		IIO_BIFURCATE_xxx8xxx8, /* MCIO */
+	},
+};
+#endif /*  _MAINBOARD_IIO_H_ */
diff --git a/src/mainboard/asrock/spc741d8/ramstage.c b/src/mainboard/asrock/spc741d8/ramstage.c
new file mode 100644
index 0000000000..e622c9647a
--- /dev/null
+++ b/src/mainboard/asrock/spc741d8/ramstage.c
@@ -0,0 +1,42 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <cpu/x86/smm.h>
+#include <soc/ramstage.h>
+#include <soc/smmrelocate.h>
+#include <device/i2c_simple.h>
+#include "gpio.h"
+
+void mainboard_silicon_init_params(FSPS_UPD *params)
+{
+	/* configure Emmitsburg PCH GPIO controller after FSP-M */
+	gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table));
+}
+
+void smm_mainboard_pci_resource_store_init(struct smm_pci_resource_info *slots, size_t size)
+{
+	soc_ubox_store_resources(slots, size);
+}
+
+void smbios_fill_dimm_locator(const struct dimm_info *dimm, struct smbios_type17 *t)
+{
+	const u8 so = dimm->soc_num;
+	const u8 ch = dimm->channel_num;
+	const u8 mm = dimm->dimm_num;
+
+	// generate locator strings matching OEM firmware (CPU1_DIMM_A1, CPU1_DIMM_B1, ..., CPU1_DIMM_H1)
+	char dev_loc[40] = { "\x00" };
+	snprintf(dev_loc, sizeof(dev_loc), "CPU%u_DIMM_%c%u", so + 1, 'A' + ch, mm + 1);
+	t->device_locator = smbios_add_string(t->eos, dev_loc);
+
+	// memory controllers are numbered 0-3 (e.g. "NODE 0" used for DIMMs A1 and B1, "NODE 1" for C1 and D1, ...)
+	char bnk_loc[40] = { "\x00" };
+	snprintf(bnk_loc, sizeof(bnk_loc), "NODE %u", ch / 2);
+	t->bank_locator = smbios_add_string(t->eos, bnk_loc);
+}
+
+int platform_i2c_transfer(unsigned int bus, struct i2c_msg *segments, int count)
+{
+	// GENERIC_LINEAR_FRAMEBUFFER enables I2C compilation for the Aspeed VGA controller.
+	// This is not supported (or needed) on the SPC741D8, so stub the function.
+	return -1;
+}
diff --git a/src/mainboard/asrock/spc741d8/romstage.c b/src/mainboard/asrock/spc741d8/romstage.c
new file mode 100644
index 0000000000..785a905241
--- /dev/null
+++ b/src/mainboard/asrock/spc741d8/romstage.c
@@ -0,0 +1,68 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <drivers/ocp/ewl/ocp_ewl.h>
+#include <soc/romstage.h>
+#include <soc/ddr.h>
+#include <defs_cxl.h>
+#include <defs_iio.h>
+#include <mainboard_iio.h>
+
+void mainboard_ewl_check(void)
+{
+	get_ewl();
+}
+
+static void mainboard_config_iio(FSPM_UPD *mupd)
+{
+	/* Set socket 0 IIO PCIe PE0,PE1,PE2,PE3 to CXL mode */
+	mupd->FspmConfig.IioPcieSubSystemMode0[0] = IIO_MODE_CXL;
+	mupd->FspmConfig.IioPcieSubSystemMode1[0] = IIO_MODE_CXL;
+	mupd->FspmConfig.IioPcieSubSystemMode2[0] = IIO_MODE_CXL;
+	mupd->FspmConfig.IioPcieSubSystemMode3[0] = IIO_MODE_CXL;
+
+	mupd->FspmConfig.DfxCxlHeaderBypass = 0;
+	mupd->FspmConfig.DfxCxlSecLvl = CXL_SECURITY_FULLY_TRUSTED;
+
+	mupd->FspmConfig.DelayAfterPCIeLinkTraining = 2000; /* ms */
+}
+
+void mainboard_memory_init_params(FSPM_UPD *mupd)
+{
+	/* Send FSP log message to main serial port */
+	mupd->FspmConfig.SerialIoUartDebugEnable = 1;
+	mupd->FspmConfig.SerialIoUartDebugIoBase = CONFIG_TTYS0_BASE;
+
+	/* Set Rank Margin Tool to disable. */
+	mupd->FspmConfig.EnableRMT = 0x0;
+	/* Enable - Portions of memory reference code will be skipped
+	 * when possible to increase boot speed on warm boots.
+	 * Disable - Disables this feature.
+	 * Auto - Sets it to the MRC default setting.
+	 */
+	mupd->FspmConfig.AttemptFastBoot = 0x1;
+	mupd->FspmConfig.AttemptFastBootCold = 0x1;
+
+	/* Set Adv MemTest Option to 0. */
+	mupd->FspmConfig.AdvMemTestOptions = 0x0;
+	/* Set MRC Promote Warnings to disable.
+	   Determines if MRC warnings are promoted to system level. */
+	mupd->FspmConfig.promoteMrcWarnings = 0x0;
+	/* Set Promote Warnings to disable.
+	   Determines if warnings are promoted to system level. */
+	mupd->FspmConfig.promoteWarnings = 0x0;
+	soc_config_iio(mupd, iio_pci_port, iio_bifur);
+	mainboard_config_iio(mupd);
+}
+
+bool mainboard_dimm_slot_exists(uint8_t socket, uint8_t channel, uint8_t dimm)
+{
+	if (socket >= CONFIG_MAX_SOCKET)
+		return false;
+	// SPC741D8 supports 8 channels with 1 DIMM each
+	if (channel >= 8)
+		return false;
+	if (dimm >= 1)
+		return false;
+
+	return true;
+}
diff --git a/src/mainboard/asrock/spc741d8/util.c b/src/mainboard/asrock/spc741d8/util.c
new file mode 100644
index 0000000000..ca27f725c3
--- /dev/null
+++ b/src/mainboard/asrock/spc741d8/util.c
@@ -0,0 +1,10 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <soc/config.h>
+
+#if CONFIG(SOC_INTEL_HAS_CXL)
+enum xeonsp_cxl_mode get_cxl_mode(void)
+{
+	return XEONSP_CXL_SYS_MEM;
+}
+#endif

From cd2a969c82755e5b60d5e66be6a56c4965a68a1b Mon Sep 17 00:00:00 2001
From: Sowmya Aralguppe <sowmya.aralguppe@intel.com>
Date: Mon, 21 Jul 2025 15:25:37 +0530
Subject: [PATCH 1767/3886] soc/intel/pantherlake: Remove storage-off related
 code

Crashlog storage and power management in PTL is changed to a unified
and persistent model,removing the need for manual SRAM power-down
commands after crashlog extraction.

Change-Id: I5bea1c816bbb68a4b2b21cc3be6cf118b4282fe7
Signed-off-by: Sowmya Aralguppe <sowmya.aralguppe@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88512
Reviewed-by: Jamie Ryu <jamie.m.ryu@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
---
 src/soc/intel/pantherlake/crashlog.c | 30 +++++-----------------------
 1 file changed, 5 insertions(+), 25 deletions(-)

diff --git a/src/soc/intel/pantherlake/crashlog.c b/src/soc/intel/pantherlake/crashlog.c
index a57a16863f..da2cbccb32 100644
--- a/src/soc/intel/pantherlake/crashlog.c
+++ b/src/soc/intel/pantherlake/crashlog.c
@@ -438,32 +438,12 @@ void cpu_cl_rearm(void)
 
 void cpu_cl_cleanup(void)
 {
-	/* Perform any SOC specific cleanup after reading the crashlog data from SRAM */
-	uintptr_t ctrl_sts_intfc_addr = get_control_status_interface();
-
-	if (!ctrl_sts_intfc_addr) {
-		printk(BIOS_ERR, "CPU crashlog control and status interface address not valid\n");
-		return;
-	}
-
-	/* If storage-off is supported, turn off the PUNIT SRAM
-	 * stroage to save power. This clears crashlog records also.
+	/*
+	 * Crashlog storage and power management in PTL is changed to a unified
+	 * and persistent model,removing the need for manual SRAM power-down
+	 * commands after crashlog extraction.
 	 */
-
-	if (!cpu_cl_disc_tab.header.fields.storage_off_support) {
-		printk(BIOS_INFO, "CPU crashlog storage_off not supported\n");
-		return;
-	}
-
-	cl_punit_control_interface_t punit_ctrl_intfc;
-	memset(&punit_ctrl_intfc, 0, sizeof(cl_punit_control_interface_t));
-	punit_ctrl_intfc.fields.set_storage_off = 1;
-	write32p(ctrl_sts_intfc_addr, punit_ctrl_intfc.data);
-
-	if (!wait_and_check(CRASHLOG_PUNIT_STORAGE_OFF_MASK))
-		printk(BIOS_ERR, "CPU crashlog storage_off not asserted\n");
-	else
-		printk(BIOS_DEBUG, "CPU crashlog storage_off asserted\n");
+	/* Does nothing. */
 }
 
 pmc_ipc_discovery_buf_t cl_get_pmc_discovery_buf(void)

From 2339508b6cdef5a9d5144b1d50646868eeb3f4a4 Mon Sep 17 00:00:00 2001
From: Luca Lai <luca.lai@lcfc.corp-partner.google.com>
Date: Thu, 7 Aug 2025 14:50:26 +0800
Subject: [PATCH 1768/3886] mb/google/trulo/var/pujjolo: Update P-sensor
 parameters

Because RF team verified the P-sensor related function and
give suggestion that follow pujjoga's setting.

BUG=b:411558536
TEST=Build and boot to OS and check with RF team.

Change-Id: I938505af02d9d3f5ba98f34fef58b67b48f049db
Signed-off-by: Luca Lai <luca.lai@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88703
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
---
 .../brya/variants/pujjolo/overridetree.cb     | 58 ++++++++++---------
 1 file changed, 32 insertions(+), 26 deletions(-)

diff --git a/src/mainboard/google/brya/variants/pujjolo/overridetree.cb b/src/mainboard/google/brya/variants/pujjolo/overridetree.cb
index e64e3af278..c8479ee655 100644
--- a/src/mainboard/google/brya/variants/pujjolo/overridetree.cb
+++ b/src/mainboard/google/brya/variants/pujjolo/overridetree.cb
@@ -309,32 +309,33 @@ chip soc/intel/alderlake
 				register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_H19_IRQ)"
 				register "speed" = "I2C_SPEED_FAST"
 				register "uid" = "1"
-				register "reg_irq_cfg0" = "0x00"
-				register "reg_irq_cfg1" = "0x80"
-				register "reg_irq_cfg2" = "0x00"
 				register "reg_gnrl_ctrl0" = "0x16"
-				register "reg_gnrl_ctrl1" = "0x25"
-				register "reg_afe_ctrl0" = "0x20"
+				register "reg_gnrl_ctrl1" = "0x21"
+				register "reg_afe_ctrl0" = "0x00"
 				register "reg_afe_ctrl1" = "0x10"
 				register "reg_afe_ctrl2" = "0x00"
 				register "reg_afe_ctrl3" = "0x00"
-				register "reg_afe_ctrl4" = "0x86"
+				register "reg_afe_ctrl4" = "0x47"
 				register "reg_afe_ctrl5" = "0x00"
 				register "reg_afe_ctrl6" = "0x00"
-				register "reg_afe_ctrl7" = "0x86"
+				register "reg_afe_ctrl7" = "0x47"
 				register "reg_afe_ctrl8" = "0x12"
-				register "reg_afe_ctrl9" = "0x0F"
-				register "reg_prox_ctrl0" = "0x09"
-				register "reg_prox_ctrl1" = "0x09"
-				register "reg_prox_ctrl2" = "0x20"
+				register "reg_afe_ctrl9" = "0x08"
+				register "reg_afe_ph0" = "0x3d"
+				register "reg_afe_ph1" = "0x1b"
+				register "reg_afe_ph2" = "0x1f"
+				register "reg_afe_ph3" = "0x3d"
+				register "reg_prox_ctrl0" = "0x0b"
+				register "reg_prox_ctrl1" = "0x0a"
+				register "reg_prox_ctrl2" = "0x90"
 				register "reg_prox_ctrl3" = "0x60"
 				register "reg_prox_ctrl4" = "0x0c"
 				register "reg_prox_ctrl5" = "0x00"
-				register "reg_prox_ctrl6" = "0x2C"
-				register "reg_prox_ctrl7" = "0xFF"
+				register "reg_prox_ctrl6" = "0x19"
+				register "reg_prox_ctrl7" = "0x58"
 				register "reg_adv_ctrl0" = "0x00"
 				register "reg_adv_ctrl1" = "0x00"
-				register "reg_adv_ctrl2" = "0x04"
+				register "reg_adv_ctrl2" = "0x00"
 				register "reg_adv_ctrl3" = "0x00"
 				register "reg_adv_ctrl4" = "0x00"
 				register "reg_adv_ctrl5" = "0x05"
@@ -345,24 +346,29 @@ chip soc/intel/alderlake
 				register "reg_adv_ctrl10" = "0x00"
 				register "reg_adv_ctrl11" = "0x00"
 				register "reg_adv_ctrl12" = "0x00"
-				register "reg_adv_ctrl16" = "0x00"
-				register "reg_adv_ctrl17" = "0x00"
-				register "reg_adv_ctrl18" = "0x00"
+				register "reg_adv_ctrl13" = "0x00"
+				register "reg_adv_ctrl14" = "0x80"
+				register "reg_adv_ctrl15" = "0x0c"
+				register "reg_adv_ctrl16" = "0x08"
+				register "reg_adv_ctrl17" = "0x56"
+				register "reg_adv_ctrl18" = "0x33"
+				register "reg_adv_ctrl19" = "0x00"
+				register "reg_adv_ctrl20" = "0x00"
 
-				register "ph0_pin" = "{3, 1, 3}"
-				register "ph1_pin" = "{1, 3, 3}"
+				register "ph0_pin" = "{1, 3, 3}"
+				register "ph1_pin" = "{3, 2, 1}"
 				register "ph2_pin" = "{3, 3, 1}"
-				register "ph3_pin" = "{3, 3, 3}"
-				register "ph01_resolution" = "512"
-				register "ph23_resolution" = "512"
+				register "ph3_pin" = "{1, 3, 3}"
+				register "ph01_resolution" = "1024"
+				register "ph23_resolution" = "1024"
 				register "startup_sensor" = "1"
-				register "ph01_proxraw_strength" = "1"
-				register "ph23_proxraw_strength" = "1"
+				register "ph01_proxraw_strength" = "3"
+				register "ph23_proxraw_strength" = "2"
 				register "avg_pos_strength" = "256"
-				register "cs_idle_sleep" = ""gnd""
+				register "cs_idle_sleep" = ""hi-z""
 				register "int_comp_resistor" = ""lowest""
 				register "input_precharge_resistor_ohms" = "4000"
-				register "input_analog_gain" = "3"
+				register "input_analog_gain" = "1"
 				device i2c 28 on end
 			end
 		end

From 4b46a0690eba39430ed98b6688a9f3b3578a0028 Mon Sep 17 00:00:00 2001
From: Walter Sonius <walterav1984@gmail.com>
Date: Sat, 2 Aug 2025 21:47:31 +0200
Subject: [PATCH 1769/3886] mb/hp: Add HP ProDesk 600 G1 SFF Business PC
 (Haswell / NPCD379 SIO)

The HP ProDesk 600 G1 SFF comes with a mainboard named "Merlin Rev.A"
which is also used by the EliteDesk 800 G1 SFF and Z230 SFF series.
Differences are in available USB2, USB3 and SATA (headers / ports)
, PCIe (slots / length), video outputs (number / type) or chipset used.
While the EliteDesk 800 G1 SFF shares the same OEM BIOS update file, the
Z230 SFF differs. This port was made on a model with 2 DP / DP++, 1 VGA,
4 USB2 and 2 USB3 backpanel ports, 4 SATA ports and 4 PCIe slots
(1 16x and 3 1x length) using a Q85 chipset (without heat sink).

Model: HP ProDesk 600 G1 SFF Business PC
Regulatory Model: TPC-F046-SF
Product No. J0E94ET#ABH, PROMO600PDeSi54590500hq4X46k NL (C8T44AV)
Mainboard: Merlin Rev.A, 795972-001

Pure autoport (initial commit) doesn't boot, more patches will bring up
general Haswell fixes, vendor/product naming corrected, RAM SPD MAP
slot detection, devicetree edits enabled all PCIe ports and some NPCD379
code from other HP desktops makes most superio related functions work.

Flash instructions:
After setting the FDO jumper on the motherboard the whole ROM can be
dumped, however writing is locked for some part of the BIOS region.
An external flasher ch341a_spi (3.3v mod) was used with a SOIC 8 pomona
probe to flash the MX25L12873F in situ without any issues. Only the
power of the USB programmer was used, and the board's main PSU was
disconnected during flash!

Tested:
 - coreboot 25.06-77-g812d0e2f626d as base
 - EDK2 (MrChromebox/2502)
 - SeaBIOS 1.16.3
 - Broadwell mrc.bin (tidus)
 - Haswell mrc.bin (peppy)
 - Haswell NRI
 - libgfxinit textmode (SeaBIOS) / framebuffer (EDK2)
 - both DP / DP++ (HDMI) & VGA output available during POST, BOOT and OS
 - Pentium G3220 / Xeon E3-1225 v3 / Xeon E3-1231 v3
 - RAM 1/2/3/4 slots filled using mixed 1.35 / 1.5v 1333 / 1600MHz DIMMs
	(NRI & mrc.bin)
	0/1: 4GB DDR3-1600 - Samsung M378B5173BH0-CK0 (2013-W30)
	0&2: 4GB DDR3-1600 - Kingston 9905402-174.A00G (2015-W33)
	1/2: 2GB DDR3-1333 - Kingston 99U5458-001.A00LF (2010-W29)
	0/3: 2GB DDR3-1600 - Micron 8JTF25664AZ-1G6M1 (2013-W37)
 - Fedora MATE 42 (Kernel 6.14)
 - KDE NEON 6.4 (Kernel 6.11)
 - MS Windows 10 / 11
 - Audio Outputs: 2x DP, Headphone, Line Out, Speaker (left&right chan.)
 - Audio Input: Line In (back)
 - USB2/3 all ports (including internal headers)
 - Intel I217-LM Gb LAN
 - SATA 4 ports
 - PCIe 16x slot @2.5GT/s (or 8x @8GT/s) and three 1x slots @5GT/s
 - dGPU nVidia GeForce GT640-2GD3 / AMD Radeon RX460 4GB (PCIe 8x)
	(disabled Hide PEG devices, option ROMs load in SeaBIOS & EDK2)
 - PS/2 ports (both Keyboard and Mouse)
 - Serial port (coreboot console & OS)
 - PowerButton (Poweron/Poweroff/Wake)
 - LEDs HDD & POWER (both off during suspend)
 - Shutdown/Reboot/Suspend
 - power_on_after_fail= Disable / Enable / Keep
 - Strip down the Intel ME/TXE firmware (make menuconfig)
 - Disabling ME HECI (manually disable in devicetree.cb)
 - flashrom -p internal -c "MX25L12835F/MX25L12873F" #(read & write)

Not tested:
 - COMB (serial port header)
 - PAR (parallel port header)
 - Audio Input Microphone Port (front)
 - USBDEBUG PORT
 - VBIOS

Not working:
 - CMOS checksum errors only on psu_fan_lvl resets to defaults sometimes
 - dual GPU (iGPU shows visual glitches while dGPU works fine)
	This occurs on both Broadwell, Haswell mrc.bin and Haswell NRI,
	may show i915 error in dmesg after waking from suspend!
	All dGPU testing have been done with a cheap PCIe riser cable!
 - Disable Intel ME PCI interface (make menuconfig)
 - PSU FAN control its either full OFF or full ON see instruction!
 - TPM Windows 10/11 detects it but "bios failed to communicate error"
 - Wake on LAN (Power on from coldboot work, but not wake from suspend)

PSU FAN instructions:
If the superio HWM (devicetree.cb node pnp 2e.8) is set to on, the FAN
will turn OFF during post and stays OFF. If the superio HWM pnp 2e.8 is
set to off the FAN will stay ON and will rampup after post in roughly a
minute to its maximum RPM and will stay that way (current default)!

NRI note:
EDK2 shows 0GB instead of the actual RAM amount installed. While using
Haswell mrc.bin EDK2 shows the correct amount of RAM. The earlier noted
RAM modules have also been tested using NRI in Memtest86+ v7.20 which
still correctly displays and test the total amount of RAM.

The data.vbt blob was extracted using debugfs from the OEM firmware
v2.65 enabling both Displayport / DP++ (HDMI) and VGA video outputs.

Theoretically like the "compaq_8200_elite_sff" it should be possible
to flash internally using a 2 step flash procedure using a minimized ME
a small SeaBIOS based coreboot and a temporary flash layout inside the
writeable BIOS region.

Change-Id: If1082e0b56364f32e43f954b589fa627cbaee50c
Signed-off-by: Walter Sonius <walterav1984@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88616
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/hp/prodesk_600_g1_sff/Kconfig   |  32 +++
 .../hp/prodesk_600_g1_sff/Kconfig.name        |   4 +
 .../hp/prodesk_600_g1_sff/Makefile.mk         |   6 +
 .../hp/prodesk_600_g1_sff/acpi/ec.asl         |   3 +
 .../hp/prodesk_600_g1_sff/acpi/platform.asl   |  10 +
 .../hp/prodesk_600_g1_sff/acpi/superio.asl    |   3 +
 .../hp/prodesk_600_g1_sff/board_info.txt      |   8 +
 .../hp/prodesk_600_g1_sff/bootblock.c         |  13 ++
 .../hp/prodesk_600_g1_sff/cmos.default        |   7 +
 .../hp/prodesk_600_g1_sff/cmos.layout         |  51 ++++
 src/mainboard/hp/prodesk_600_g1_sff/data.vbt  | Bin 0 -> 6144 bytes
 .../hp/prodesk_600_g1_sff/devicetree.cb       | 149 ++++++++++++
 src/mainboard/hp/prodesk_600_g1_sff/dsdt.asl  |  27 +++
 .../hp/prodesk_600_g1_sff/gma-mainboard.ads   |  19 ++
 src/mainboard/hp/prodesk_600_g1_sff/gpio.c    | 221 ++++++++++++++++++
 .../hp/prodesk_600_g1_sff/hda_verb.c          |  24 ++
 .../hp/prodesk_600_g1_sff/romstage.c          |  35 +++
 17 files changed, 612 insertions(+)
 create mode 100644 src/mainboard/hp/prodesk_600_g1_sff/Kconfig
 create mode 100644 src/mainboard/hp/prodesk_600_g1_sff/Kconfig.name
 create mode 100644 src/mainboard/hp/prodesk_600_g1_sff/Makefile.mk
 create mode 100644 src/mainboard/hp/prodesk_600_g1_sff/acpi/ec.asl
 create mode 100644 src/mainboard/hp/prodesk_600_g1_sff/acpi/platform.asl
 create mode 100644 src/mainboard/hp/prodesk_600_g1_sff/acpi/superio.asl
 create mode 100644 src/mainboard/hp/prodesk_600_g1_sff/board_info.txt
 create mode 100644 src/mainboard/hp/prodesk_600_g1_sff/bootblock.c
 create mode 100644 src/mainboard/hp/prodesk_600_g1_sff/cmos.default
 create mode 100644 src/mainboard/hp/prodesk_600_g1_sff/cmos.layout
 create mode 100644 src/mainboard/hp/prodesk_600_g1_sff/data.vbt
 create mode 100644 src/mainboard/hp/prodesk_600_g1_sff/devicetree.cb
 create mode 100644 src/mainboard/hp/prodesk_600_g1_sff/dsdt.asl
 create mode 100644 src/mainboard/hp/prodesk_600_g1_sff/gma-mainboard.ads
 create mode 100644 src/mainboard/hp/prodesk_600_g1_sff/gpio.c
 create mode 100644 src/mainboard/hp/prodesk_600_g1_sff/hda_verb.c
 create mode 100644 src/mainboard/hp/prodesk_600_g1_sff/romstage.c

diff --git a/src/mainboard/hp/prodesk_600_g1_sff/Kconfig b/src/mainboard/hp/prodesk_600_g1_sff/Kconfig
new file mode 100644
index 0000000000..851ecc8ecf
--- /dev/null
+++ b/src/mainboard/hp/prodesk_600_g1_sff/Kconfig
@@ -0,0 +1,32 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
+if BOARD_HP_PRODESK_600_G1_SFF
+
+config BOARD_SPECIFIC_OPTIONS
+	def_bool y
+	select BOARD_ROMSIZE_KB_16384
+	select CPU_INTEL_HASWELL
+	select HAVE_ACPI_RESUME
+	select HAVE_ACPI_TABLES
+	select HAVE_CMOS_DEFAULT
+	select HAVE_OPTION_TABLE
+	select INTEL_GMA_HAVE_VBT
+	select MAINBOARD_HAS_LIBGFXINIT
+	select MAINBOARD_HAS_TPM1
+	select MAINBOARD_USES_IFD_GBE_REGION
+	select MEMORY_MAPPED_TPM
+	select NORTHBRIDGE_INTEL_HASWELL
+	select SERIRQ_CONTINUOUS_MODE
+	select SOUTHBRIDGE_INTEL_LYNXPOINT
+	select SUPERIO_NUVOTON_NPCD378
+
+config MAINBOARD_DIR
+	default "hp/prodesk_600_g1_sff"
+
+config MAINBOARD_PART_NUMBER
+	default "ProDesk 600 G1 SFF"
+
+config USBDEBUG_HCD_INDEX # FIXME: check this
+	default 2
+
+endif
diff --git a/src/mainboard/hp/prodesk_600_g1_sff/Kconfig.name b/src/mainboard/hp/prodesk_600_g1_sff/Kconfig.name
new file mode 100644
index 0000000000..8f3b29102b
--- /dev/null
+++ b/src/mainboard/hp/prodesk_600_g1_sff/Kconfig.name
@@ -0,0 +1,4 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
+config BOARD_HP_PRODESK_600_G1_SFF
+	bool "ProDesk 600 G1 SFF"
diff --git a/src/mainboard/hp/prodesk_600_g1_sff/Makefile.mk b/src/mainboard/hp/prodesk_600_g1_sff/Makefile.mk
new file mode 100644
index 0000000000..c3cf55d397
--- /dev/null
+++ b/src/mainboard/hp/prodesk_600_g1_sff/Makefile.mk
@@ -0,0 +1,6 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
+bootblock-y += bootblock.c
+bootblock-y += gpio.c
+romstage-y += gpio.c
+ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads
diff --git a/src/mainboard/hp/prodesk_600_g1_sff/acpi/ec.asl b/src/mainboard/hp/prodesk_600_g1_sff/acpi/ec.asl
new file mode 100644
index 0000000000..16990d45f4
--- /dev/null
+++ b/src/mainboard/hp/prodesk_600_g1_sff/acpi/ec.asl
@@ -0,0 +1,3 @@
+/* SPDX-License-Identifier: CC-PDDC */
+
+/* Please update the license if adding licensable material. */
diff --git a/src/mainboard/hp/prodesk_600_g1_sff/acpi/platform.asl b/src/mainboard/hp/prodesk_600_g1_sff/acpi/platform.asl
new file mode 100644
index 0000000000..aff432b6f4
--- /dev/null
+++ b/src/mainboard/hp/prodesk_600_g1_sff/acpi/platform.asl
@@ -0,0 +1,10 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+Method(_WAK, 1)
+{
+	Return(Package() {0, 0})
+}
+
+Method(_PTS, 1)
+{
+}
diff --git a/src/mainboard/hp/prodesk_600_g1_sff/acpi/superio.asl b/src/mainboard/hp/prodesk_600_g1_sff/acpi/superio.asl
new file mode 100644
index 0000000000..55b1db5b11
--- /dev/null
+++ b/src/mainboard/hp/prodesk_600_g1_sff/acpi/superio.asl
@@ -0,0 +1,3 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <drivers/pc80/pc/ps2_controller.asl>
diff --git a/src/mainboard/hp/prodesk_600_g1_sff/board_info.txt b/src/mainboard/hp/prodesk_600_g1_sff/board_info.txt
new file mode 100644
index 0000000000..ee4cd0ac38
--- /dev/null
+++ b/src/mainboard/hp/prodesk_600_g1_sff/board_info.txt
@@ -0,0 +1,8 @@
+Category: desktop
+Board URL: https://support.hp.com/us-en/product/setup-user-guides/hp-prodesk-600-g1-small-form-factor-pc/model/5387451
+ROM IC: MX25L12873F
+ROM protocol: SPI
+Flashrom support: y
+ROM package: SOIC8
+ROM socketed: no
+Release year: 2013
diff --git a/src/mainboard/hp/prodesk_600_g1_sff/bootblock.c b/src/mainboard/hp/prodesk_600_g1_sff/bootblock.c
new file mode 100644
index 0000000000..a27e99e338
--- /dev/null
+++ b/src/mainboard/hp/prodesk_600_g1_sff/bootblock.c
@@ -0,0 +1,13 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <southbridge/intel/lynxpoint/pch.h>
+#include <superio/nuvoton/npcd378/npcd378.h>
+#include <superio/nuvoton/common/nuvoton.h>
+
+#define SERIAL_DEV PNP_DEV(0x2e, NPCD378_SP2)
+
+void mainboard_config_superio(void)
+{
+	if (CONFIG(CONSOLE_SERIAL))
+		nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
+}
diff --git a/src/mainboard/hp/prodesk_600_g1_sff/cmos.default b/src/mainboard/hp/prodesk_600_g1_sff/cmos.default
new file mode 100644
index 0000000000..5ee1084b15
--- /dev/null
+++ b/src/mainboard/hp/prodesk_600_g1_sff/cmos.default
@@ -0,0 +1,7 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
+boot_option=Fallback
+debug_level=Debug
+nmi=Enable
+power_on_after_fail=Disable
+psu_fan_lvl=3
diff --git a/src/mainboard/hp/prodesk_600_g1_sff/cmos.layout b/src/mainboard/hp/prodesk_600_g1_sff/cmos.layout
new file mode 100644
index 0000000000..45d4905d2f
--- /dev/null
+++ b/src/mainboard/hp/prodesk_600_g1_sff/cmos.layout
@@ -0,0 +1,51 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
+# -----------------------------------------------------------------
+entries
+
+# -----------------------------------------------------------------
+0	120	r	0	reserved_memory
+
+# -----------------------------------------------------------------
+# RTC_BOOT_BYTE (coreboot hardcoded)
+384	1	e	4	boot_option
+388	4	h	0	reboot_counter
+
+# -----------------------------------------------------------------
+# coreboot config options: console
+395	4	e	6	debug_level
+400	3	h	0	psu_fan_lvl
+
+# coreboot config options: southbridge
+408	1	e	1	nmi
+409	2	e	7	power_on_after_fail
+
+# coreboot config options: check sums
+984	16	h	0	check_sum
+
+# -----------------------------------------------------------------
+
+enumerations
+
+#ID	value	text
+1	0	Disable
+1	1	Enable
+4	0	Fallback
+4	1	Normal
+6	0	Emergency
+6	1	Alert
+6	2	Critical
+6	3	Error
+6	4	Warning
+6	5	Notice
+6	6	Info
+6	7	Debug
+6	8	Spew
+7	0	Disable
+7	1	Enable
+7	2	Keep
+
+# -----------------------------------------------------------------
+checksums
+
+checksum 392 415 984
diff --git a/src/mainboard/hp/prodesk_600_g1_sff/data.vbt b/src/mainboard/hp/prodesk_600_g1_sff/data.vbt
new file mode 100644
index 0000000000000000000000000000000000000000..242f062fdd6e80763c1f481cc4106e3a7076e675
GIT binary patch
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diff --git a/src/mainboard/hp/prodesk_600_g1_sff/devicetree.cb b/src/mainboard/hp/prodesk_600_g1_sff/devicetree.cb
new file mode 100644
index 0000000000..2b751ecf58
--- /dev/null
+++ b/src/mainboard/hp/prodesk_600_g1_sff/devicetree.cb
@@ -0,0 +1,149 @@
+chip northbridge/intel/haswell
+	register "gpu_ddi_e_connected" = "1"
+	register "spd_addresses" = "{0x53, 0x52, 0x51, 0x50}"
+	chip cpu/intel/haswell
+		device cpu_cluster 0 on ops haswell_cpu_bus_ops end
+	end
+	device domain 0 on
+		ops haswell_pci_domain_ops
+		subsystemid 0x103c 0x18e7 inherit
+		device pci 00.0 on end # Host bridge
+		device pci 01.0 on end # X16PCIEXP1
+		device pci 02.0 on end # Internal graphics VGA controller
+		device pci 03.0 on end # Mini-HD audio
+		chip southbridge/intel/lynxpoint # Intel Series 8 Lynx Point PCH
+			register "gen1_dec" = "0x00fc0a01"
+			register "gen2_dec" = "0x00fc0801"
+			register "gpe0_en_1" = "0x0146"
+			register "sata_port0_gen3_dtle" = "0x5"
+			register "sata_port1_gen3_dtle" = "0x5"
+			register "sata_port_map" = "0x3f"
+			device pci 14.0 on  end	# xHCI Controller
+			device pci 16.0 on  end	# Management Engine Interface 1
+			device pci 16.1 off end	# Management Engine Interface 2
+			device pci 16.2 off end	# Management Engine IDE-R
+			device pci 16.3 on  end	# Management Engine KT
+			device pci 19.0 on  end	# Intel Gigabit Ethernet I217-LM
+			device pci 1a.0 on  end	# USB2 EHCI #2
+			device pci 1b.0 on  end	# High Definition Audio
+			device pci 1c.0 on  end	# PCIe Port #1
+			device pci 1c.1 on  end	# X1PCIEXP2
+			device pci 1c.2 off end	# PCIe Port #3
+			device pci 1c.3 on  end	# X1PCIEXP1
+			device pci 1c.4 on  end	# X1PCIEXP3
+			device pci 1c.5 off end	# PCIe Port #6
+			device pci 1c.6 off end	# PCIe Port #7
+			device pci 1c.7 off end	# PCIe Port #8
+			device pci 1d.0 on  end	# USB2 EHCI #1
+			device pci 1f.0 on	# LPC bridge
+				chip superio/common
+					device pnp 2e.ff on # passes SIO base addr to SSDT gen
+						chip superio/nuvoton/npcd378
+							device pnp 2e.0 off end		# Floppy
+							device pnp 2e.1 on		# Parallel port
+								# global
+
+								# serialice: Vendor writes:
+								irq 0x14 = 0x9c
+								irq 0x1c = 0xa8
+								irq 0x1d = 0x08
+								irq 0x22 = 0x3f
+								irq 0x1a = 0xb0
+								# dumped from superiotool:
+								irq 0x1b = 0x1e
+								irq 0x27 = 0x08
+								irq 0x2a = 0x20
+								irq 0x2d = 0x01
+								# parallel port
+								io 0x60 = 0x378
+								irq 0x70 = 0x07
+								drq 0x74 = 0x04
+							end
+							device pnp 2e.2 off		# COM1
+								io 0x60 = 0x2f8
+								irq 0x70 = 3
+							end
+							device pnp 2e.3 on		# COM2, IR
+								io 0x60 = 0x3f8
+								irq 0x70 = 4
+							end
+							device pnp 2e.4 on		# LED control
+								io 0x60 = 0x0a00
+								# IOBASE[0h] = bit0 LED red / green
+								# IOBASE[0h] = bit1-4 LED PWM duty cycle
+								# IOBASE[1h] = bit6 SWCC
+
+								io 0x62 = 0x0a10
+								# IOBASE [0h] = GPES
+								# IOBASE [1h] = GPEE
+								# IOBASE [4h:7h] = 32bit upcounter at 1Mhz
+								# IOBASE [8h:bh] = GPS
+								# IOBASE [ch:fh] = GPE
+							end
+							device pnp 2e.5 on		# Mouse
+								irq 0x70 = 0xc
+							end
+							device pnp 2e.6 on		# Keyboard
+								io 0x60 = 0x0060
+								io 0x62 = 0x0064
+								irq 0x70 = 0x01
+								# serialice: Vendor writes:
+								drq 0xf0 = 0x40
+							end
+							device pnp 2e.7 on		#  WDT ?
+								io 0x60 = 0x0a20
+							end
+							device pnp 2e.8 off		# HWM
+								io 0x60 = 0x800
+								# IOBASE[0h:feh] HWM page
+								# IOBASE[ffh] bit0-bit3 page selector
+
+								drq 0xf0 = 0x20
+								drq 0xf1 = 0x01
+								drq 0xf2 = 0x40
+								drq 0xf3 = 0x01
+
+								drq 0xf4 = 0x66
+								drq 0xf5 = 0x67
+								drq 0xf6 = 0x66
+								drq 0xf7 = 0x01
+							end
+							device pnp 2e.f on		# GPIO OD ?
+								drq 0xf1 = 0x97
+								drq 0xf2 = 0x01
+								drq 0xf5 = 0x08
+								drq 0xfe = 0x80
+							end
+							device pnp 2e.15 on		# BUS ?
+								io 0x60 = 0x0a80
+								io 0x62 = 0x0a90
+							end
+							device pnp 2e.1c on		# Suspend Control ?
+								io 0x60 = 0x0a40
+								# writing to IOBASE[5h]
+								#  0x0: Power off
+								#  0x9: Power off and bricked until CMOS battery removed
+							end
+							device pnp 2e.1e on		# GPIO ?
+								io 0x60 = 0x0a60
+								drq 0xf4 = 0x01
+								# skip the following, as it
+								# looks like remapped registers
+								#drq 0xf5 = 0x06
+								#drq 0xf6 = 0x60
+								#drq 0xfe = 0x03
+							end
+						end
+					end
+				end
+				chip drivers/pc80/tpm
+					device pnp 4e.0 on end # TPM module
+				end
+			end
+			device pci 1f.2 on  end	# SATA Controller (AHCI)
+			device pci 1f.3 on  end	# SMBus
+			device pci 1f.5 off end	# SATA Controller (Legacy)
+			device pci 1f.6 off end	# Thermal
+		end
+	end
+end
diff --git a/src/mainboard/hp/prodesk_600_g1_sff/dsdt.asl b/src/mainboard/hp/prodesk_600_g1_sff/dsdt.asl
new file mode 100644
index 0000000000..2eb0805cf2
--- /dev/null
+++ b/src/mainboard/hp/prodesk_600_g1_sff/dsdt.asl
@@ -0,0 +1,27 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <acpi/acpi.h>
+
+DefinitionBlock(
+	"dsdt.aml",
+	"DSDT",
+	ACPI_DSDT_REV_2,
+	OEM_ID,
+	ACPI_TABLE_CREATOR,
+	0x20141018
+)
+{
+	#include <acpi/dsdt_top.asl>
+	#include "acpi/platform.asl"
+	#include <cpu/intel/common/acpi/cpu.asl>
+	#include <southbridge/intel/common/acpi/platform.asl>
+	/* global NVS and variables. */
+	#include <southbridge/intel/lynxpoint/acpi/globalnvs.asl>
+	#include <southbridge/intel/common/acpi/sleepstates.asl>
+
+	Device (\_SB.PCI0)
+	{
+		#include <northbridge/intel/haswell/acpi/hostbridge.asl>
+		#include <southbridge/intel/lynxpoint/acpi/pch.asl>
+	}
+}
diff --git a/src/mainboard/hp/prodesk_600_g1_sff/gma-mainboard.ads b/src/mainboard/hp/prodesk_600_g1_sff/gma-mainboard.ads
new file mode 100644
index 0000000000..74b50645e6
--- /dev/null
+++ b/src/mainboard/hp/prodesk_600_g1_sff/gma-mainboard.ads
@@ -0,0 +1,19 @@
+-- SPDX-License-Identifier: GPL-2.0-or-later
+
+with HW.GFX.GMA;
+with HW.GFX.GMA.Display_Probing;
+
+use HW.GFX.GMA;
+use HW.GFX.GMA.Display_Probing;
+
+private package GMA.Mainboard is
+
+   ports : constant Port_List :=
+     (DP1,
+      DP2,
+      HDMI1,
+      HDMI2,
+      Analog,
+      others => Disabled);
+
+end GMA.Mainboard;
diff --git a/src/mainboard/hp/prodesk_600_g1_sff/gpio.c b/src/mainboard/hp/prodesk_600_g1_sff/gpio.c
new file mode 100644
index 0000000000..a3eca1249f
--- /dev/null
+++ b/src/mainboard/hp/prodesk_600_g1_sff/gpio.c
@@ -0,0 +1,221 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <southbridge/intel/common/gpio.h>
+
+static const struct pch_gpio_set1 pch_gpio_set1_mode = {
+	.gpio0 = GPIO_MODE_GPIO,
+	.gpio1 = GPIO_MODE_GPIO,
+	.gpio2 = GPIO_MODE_GPIO,
+	.gpio3 = GPIO_MODE_GPIO,
+	.gpio4 = GPIO_MODE_GPIO,
+	.gpio5 = GPIO_MODE_GPIO,
+	.gpio6 = GPIO_MODE_GPIO,
+	.gpio7 = GPIO_MODE_GPIO,
+	.gpio8 = GPIO_MODE_GPIO,
+	.gpio9 = GPIO_MODE_NATIVE,
+	.gpio10 = GPIO_MODE_NATIVE,
+	.gpio11 = GPIO_MODE_GPIO,
+	.gpio12 = GPIO_MODE_NATIVE,
+	.gpio13 = GPIO_MODE_GPIO,
+	.gpio14 = GPIO_MODE_NATIVE,
+	.gpio15 = GPIO_MODE_GPIO,
+	.gpio16 = GPIO_MODE_GPIO,
+	.gpio17 = GPIO_MODE_GPIO,
+	.gpio18 = GPIO_MODE_GPIO,
+	.gpio19 = GPIO_MODE_GPIO,
+	.gpio20 = GPIO_MODE_NATIVE,
+	.gpio21 = GPIO_MODE_GPIO,
+	.gpio22 = GPIO_MODE_GPIO,
+	.gpio23 = GPIO_MODE_NATIVE,
+	.gpio24 = GPIO_MODE_GPIO,
+	.gpio25 = GPIO_MODE_GPIO,
+	.gpio26 = GPIO_MODE_GPIO,
+	.gpio27 = GPIO_MODE_GPIO,
+	.gpio28 = GPIO_MODE_GPIO,
+	.gpio29 = GPIO_MODE_NATIVE,
+	.gpio30 = GPIO_MODE_NATIVE,
+	.gpio31 = GPIO_MODE_GPIO,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_direction = {
+	.gpio0 = GPIO_DIR_INPUT,
+	.gpio1 = GPIO_DIR_INPUT,
+	.gpio2 = GPIO_DIR_OUTPUT,
+	.gpio3 = GPIO_DIR_OUTPUT,
+	.gpio4 = GPIO_DIR_INPUT,
+	.gpio5 = GPIO_DIR_INPUT,
+	.gpio6 = GPIO_DIR_INPUT,
+	.gpio7 = GPIO_DIR_INPUT,
+	.gpio8 = GPIO_DIR_INPUT,
+	.gpio11 = GPIO_DIR_INPUT,
+	.gpio13 = GPIO_DIR_INPUT,
+	.gpio15 = GPIO_DIR_OUTPUT,
+	.gpio16 = GPIO_DIR_INPUT,
+	.gpio17 = GPIO_DIR_INPUT,
+	.gpio18 = GPIO_DIR_INPUT,
+	.gpio19 = GPIO_DIR_INPUT,
+	.gpio21 = GPIO_DIR_INPUT,
+	.gpio22 = GPIO_DIR_INPUT,
+	.gpio24 = GPIO_DIR_OUTPUT,
+	.gpio25 = GPIO_DIR_INPUT,
+	.gpio26 = GPIO_DIR_INPUT,
+	.gpio27 = GPIO_DIR_INPUT,
+	.gpio28 = GPIO_DIR_OUTPUT,
+	.gpio31 = GPIO_DIR_INPUT,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_level = {
+	.gpio2 = GPIO_LEVEL_HIGH,
+	.gpio3 = GPIO_LEVEL_HIGH,
+	.gpio15 = GPIO_LEVEL_LOW,
+	.gpio24 = GPIO_LEVEL_LOW,
+	.gpio28 = GPIO_LEVEL_LOW,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_reset = {
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_invert = {
+	.gpio0 = GPIO_INVERT,
+	.gpio1 = GPIO_INVERT,
+	.gpio4 = GPIO_INVERT,
+	.gpio5 = GPIO_INVERT,
+	.gpio6 = GPIO_INVERT,
+	.gpio7 = GPIO_INVERT,
+	.gpio11 = GPIO_INVERT,
+	.gpio13 = GPIO_INVERT,
+	.gpio17 = GPIO_INVERT,
+	.gpio19 = GPIO_INVERT,
+	.gpio21 = GPIO_INVERT,
+	.gpio22 = GPIO_INVERT,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_blink = {
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_mode = {
+	.gpio32 = GPIO_MODE_GPIO,
+	.gpio33 = GPIO_MODE_GPIO,
+	.gpio34 = GPIO_MODE_GPIO,
+	.gpio35 = GPIO_MODE_GPIO,
+	.gpio36 = GPIO_MODE_GPIO,
+	.gpio37 = GPIO_MODE_GPIO,
+	.gpio38 = GPIO_MODE_GPIO,
+	.gpio39 = GPIO_MODE_GPIO,
+	.gpio40 = GPIO_MODE_NATIVE,
+	.gpio41 = GPIO_MODE_NATIVE,
+	.gpio42 = GPIO_MODE_NATIVE,
+	.gpio43 = GPIO_MODE_GPIO,
+	.gpio44 = GPIO_MODE_GPIO,
+	.gpio45 = GPIO_MODE_GPIO,
+	.gpio46 = GPIO_MODE_GPIO,
+	.gpio47 = GPIO_MODE_NATIVE,
+	.gpio48 = GPIO_MODE_GPIO,
+	.gpio49 = GPIO_MODE_GPIO,
+	.gpio50 = GPIO_MODE_GPIO,
+	.gpio51 = GPIO_MODE_GPIO,
+	.gpio52 = GPIO_MODE_GPIO,
+	.gpio53 = GPIO_MODE_GPIO,
+	.gpio54 = GPIO_MODE_GPIO,
+	.gpio55 = GPIO_MODE_GPIO,
+	.gpio56 = GPIO_MODE_NATIVE,
+	.gpio57 = GPIO_MODE_GPIO,
+	.gpio58 = GPIO_MODE_NATIVE,
+	.gpio59 = GPIO_MODE_NATIVE,
+	.gpio60 = GPIO_MODE_GPIO,
+	.gpio61 = GPIO_MODE_GPIO,
+	.gpio62 = GPIO_MODE_NATIVE,
+	.gpio63 = GPIO_MODE_NATIVE,
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_direction = {
+	.gpio32 = GPIO_DIR_OUTPUT,
+	.gpio33 = GPIO_DIR_INPUT,
+	.gpio34 = GPIO_DIR_INPUT,
+	.gpio35 = GPIO_DIR_INPUT,
+	.gpio36 = GPIO_DIR_INPUT,
+	.gpio37 = GPIO_DIR_INPUT,
+	.gpio38 = GPIO_DIR_INPUT,
+	.gpio39 = GPIO_DIR_INPUT,
+	.gpio43 = GPIO_DIR_INPUT,
+	.gpio44 = GPIO_DIR_INPUT,
+	.gpio45 = GPIO_DIR_INPUT,
+	.gpio46 = GPIO_DIR_INPUT,
+	.gpio48 = GPIO_DIR_INPUT,
+	.gpio49 = GPIO_DIR_INPUT,
+	.gpio50 = GPIO_DIR_INPUT,
+	.gpio51 = GPIO_DIR_OUTPUT,
+	.gpio52 = GPIO_DIR_INPUT,
+	.gpio53 = GPIO_DIR_OUTPUT,
+	.gpio54 = GPIO_DIR_INPUT,
+	.gpio55 = GPIO_DIR_OUTPUT,
+	.gpio57 = GPIO_DIR_INPUT,
+	.gpio60 = GPIO_DIR_OUTPUT,
+	.gpio61 = GPIO_DIR_INPUT,
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_level = {
+	.gpio32 = GPIO_LEVEL_HIGH,
+	.gpio51 = GPIO_LEVEL_HIGH,
+	.gpio53 = GPIO_LEVEL_HIGH,
+	.gpio55 = GPIO_LEVEL_HIGH,
+	.gpio60 = GPIO_LEVEL_HIGH,
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_reset = {
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_mode = {
+	.gpio64 = GPIO_MODE_NATIVE,
+	.gpio65 = GPIO_MODE_NATIVE,
+	.gpio66 = GPIO_MODE_NATIVE,
+	.gpio67 = GPIO_MODE_NATIVE,
+	.gpio68 = GPIO_MODE_GPIO,
+	.gpio69 = GPIO_MODE_GPIO,
+	.gpio70 = GPIO_MODE_GPIO,
+	.gpio71 = GPIO_MODE_GPIO,
+	.gpio72 = GPIO_MODE_GPIO,
+	.gpio73 = GPIO_MODE_GPIO,
+	.gpio74 = GPIO_MODE_GPIO,
+	.gpio75 = GPIO_MODE_NATIVE,
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_direction = {
+	.gpio68 = GPIO_DIR_INPUT,
+	.gpio69 = GPIO_DIR_INPUT,
+	.gpio70 = GPIO_DIR_INPUT,
+	.gpio71 = GPIO_DIR_INPUT,
+	.gpio72 = GPIO_DIR_OUTPUT,
+	.gpio73 = GPIO_DIR_INPUT,
+	.gpio74 = GPIO_DIR_INPUT,
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_level = {
+	.gpio72 = GPIO_LEVEL_LOW,
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_reset = {
+};
+
+const struct pch_gpio_map mainboard_gpio_map = {
+	.set1 = {
+		.mode		= &pch_gpio_set1_mode,
+		.direction	= &pch_gpio_set1_direction,
+		.level		= &pch_gpio_set1_level,
+		.blink		= &pch_gpio_set1_blink,
+		.invert		= &pch_gpio_set1_invert,
+		.reset		= &pch_gpio_set1_reset,
+	},
+	.set2 = {
+		.mode		= &pch_gpio_set2_mode,
+		.direction	= &pch_gpio_set2_direction,
+		.level		= &pch_gpio_set2_level,
+		.reset		= &pch_gpio_set2_reset,
+	},
+	.set3 = {
+		.mode		= &pch_gpio_set3_mode,
+		.direction	= &pch_gpio_set3_direction,
+		.level		= &pch_gpio_set3_level,
+		.reset		= &pch_gpio_set3_reset,
+	},
+};
diff --git a/src/mainboard/hp/prodesk_600_g1_sff/hda_verb.c b/src/mainboard/hp/prodesk_600_g1_sff/hda_verb.c
new file mode 100644
index 0000000000..8152a76175
--- /dev/null
+++ b/src/mainboard/hp/prodesk_600_g1_sff/hda_verb.c
@@ -0,0 +1,24 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <device/azalia_device.h>
+
+const u32 cim_verb_data[] = {
+	0x10ec0221,	/* Codec Vendor / Device ID: Realtek */
+	0x103c18e7,	/* Subsystem ID */
+	11,		/* Number of 4 dword sets */
+	AZALIA_SUBVENDOR(0, 0x103c18e7),
+	AZALIA_PIN_CFG(0, 0x12, 0x403c0000),
+	AZALIA_PIN_CFG(0, 0x14, 0x01014020),
+	AZALIA_PIN_CFG(0, 0x17, 0x90170110),
+	AZALIA_PIN_CFG(0, 0x18, AZALIA_PIN_CFG_NC(0)),
+	AZALIA_PIN_CFG(0, 0x19, AZALIA_PIN_CFG_NC(0)),
+	AZALIA_PIN_CFG(0, 0x1a, 0x02a1103f),
+	AZALIA_PIN_CFG(0, 0x1b, 0x01813030),
+	AZALIA_PIN_CFG(0, 0x1d, 0x40400001),
+	AZALIA_PIN_CFG(0, 0x1e, AZALIA_PIN_CFG_NC(0)),
+	AZALIA_PIN_CFG(0, 0x21, 0x0221102f),
+};
+
+const u32 pc_beep_verbs[0] = {};
+
+AZALIA_ARRAY_SIZES;
diff --git a/src/mainboard/hp/prodesk_600_g1_sff/romstage.c b/src/mainboard/hp/prodesk_600_g1_sff/romstage.c
new file mode 100644
index 0000000000..417e7c5a9c
--- /dev/null
+++ b/src/mainboard/hp/prodesk_600_g1_sff/romstage.c
@@ -0,0 +1,35 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <southbridge/intel/lynxpoint/pch.h>
+
+void mainboard_config_rcba(void)
+{
+}
+
+const struct usb2_port_config mainboard_usb2_ports[MAX_USB2_PORTS] = {
+	/* FIXME: Length and Location are computed from IOBP values, may be inaccurate */
+	/* Length, Enable, OCn#, Location */
+	{ 0x0040, 1, 0, USB_PORT_FLEX },
+	{ 0x0040, 1, 0, USB_PORT_FLEX },
+	{ 0x0110, 1, 0, USB_PORT_BACK_PANEL },
+	{ 0x0040, 1, 0, USB_PORT_BACK_PANEL },
+	{ 0x0040, 1, 3, USB_PORT_FLEX },
+	{ 0x0040, 1, 3, USB_PORT_FLEX },
+	{ 0x0040, 1, 3, USB_PORT_BACK_PANEL },
+	{ 0x0040, 1, 3, USB_PORT_BACK_PANEL },
+	{ 0x0040, 1, 5, USB_PORT_BACK_PANEL },
+	{ 0x0040, 1, 5, USB_PORT_BACK_PANEL },
+	{ 0x0040, 1, 5, USB_PORT_FLEX },
+	{ 0x0040, 1, 5, USB_PORT_FLEX },
+	{ 0x0110, 1, 7, USB_PORT_BACK_PANEL },
+	{ 0x0110, 1, 7, USB_PORT_BACK_PANEL },
+};
+
+const struct usb3_port_config mainboard_usb3_ports[MAX_USB3_PORTS] = {
+	{ 1, 0 },
+	{ 1, 0 },
+	{ 0, 3 },
+	{ 0, 3 },
+	{ 1, 5 },
+	{ 1, 5 },
+};

From b74d2b77d2d6468f602f0ebae7a6b9ab614cff5f Mon Sep 17 00:00:00 2001
From: Eren Peng <peng.eren@inventec.corp-partner.google.com>
Date: Thu, 7 Aug 2025 10:00:59 +0800
Subject: [PATCH 1770/3886] mb/google/trulo/var/kaladin: Add WIFI SAR table

Add WIFI SAR table for intel WIFI SAR table

BUG=b:434861866
TEST=Build and flash to DUT, check that SAR table is loaded by cbmem -c | grep SAR

Change-Id: Idf48254ec43535ff51859ecbec3ea75b7c35e70c
Signed-off-by: Eren Peng <peng.eren@inventec.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88702
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
---
 src/mainboard/google/brya/variants/kaladin/Makefile.mk   | 1 +
 .../google/brya/variants/kaladin/overridetree.cb         | 4 ++++
 src/mainboard/google/brya/variants/kaladin/variant.c     | 9 +++++++++
 3 files changed, 14 insertions(+)
 create mode 100644 src/mainboard/google/brya/variants/kaladin/variant.c

diff --git a/src/mainboard/google/brya/variants/kaladin/Makefile.mk b/src/mainboard/google/brya/variants/kaladin/Makefile.mk
index 936c557f19..bf8808508a 100644
--- a/src/mainboard/google/brya/variants/kaladin/Makefile.mk
+++ b/src/mainboard/google/brya/variants/kaladin/Makefile.mk
@@ -4,5 +4,6 @@ bootblock-y += gpio.c
 romstage-y += gpio.c
 romstage-y += memory.c
 ramstage-y += gpio.c
+ramstage-y += variant.c
 ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_HDA_VERB) += hda_verb.c
 ramstage-$(CONFIG_FW_CONFIG) += fw_config.c
diff --git a/src/mainboard/google/brya/variants/kaladin/overridetree.cb b/src/mainboard/google/brya/variants/kaladin/overridetree.cb
index 4a8ad625c0..08cb01231c 100644
--- a/src/mainboard/google/brya/variants/kaladin/overridetree.cb
+++ b/src/mainboard/google/brya/variants/kaladin/overridetree.cb
@@ -11,6 +11,10 @@ fw_config
 		option TOUCH_ELAN_TOP   0
 		option TOUCH_ELAN_DBTS  1
 	end
+	field WIFI_SAR 13 15
+		option WIFI_SAR_ID_0 0
+		option WIFI_SAR_ID_1 1
+	end
 	field STORAGE 30 31
 		option STORAGE_EMMC		0
 		option STORAGE_NVME		1
diff --git a/src/mainboard/google/brya/variants/kaladin/variant.c b/src/mainboard/google/brya/variants/kaladin/variant.c
new file mode 100644
index 0000000000..1443b03cfa
--- /dev/null
+++ b/src/mainboard/google/brya/variants/kaladin/variant.c
@@ -0,0 +1,9 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <fw_config.h>
+#include <sar.h>
+
+const char *get_wifi_sar_cbfs_filename(void)
+{
+	return get_wifi_sar_fw_config_filename(FW_CONFIG_FIELD(WIFI_SAR));
+}

From ecbca16bf40b3234d6b848776dc7ad2f88ebae4e Mon Sep 17 00:00:00 2001
From: Elyes Haouas <ehaouas@noos.fr>
Date: Sat, 9 Aug 2025 09:59:33 +0200
Subject: [PATCH 1771/3886] tree: Replace union {0} initializers with {} for
 C23 compliance

This change addresses GCC-15 behavior where {0} union initializers only
clear the first member, leaving padding bits uninitialized. The new {}
initializer ensures full union clearing as required by C23.

Change-Id: I1d9b063d8bdd3d2f0b0f67e6c20eb484ff6a5cc5
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88732
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
---
 payloads/libpayload/curses/PDCurses/dos/pdcutil.c | 2 +-
 src/drivers/wifi/generic/acpi.c                   | 2 +-
 src/soc/mediatek/common/dp/dptx_common.c          | 2 +-
 3 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/payloads/libpayload/curses/PDCurses/dos/pdcutil.c b/payloads/libpayload/curses/PDCurses/dos/pdcutil.c
index b209352a39..98df72a0d2 100644
--- a/payloads/libpayload/curses/PDCurses/dos/pdcutil.c
+++ b/payloads/libpayload/curses/PDCurses/dos/pdcutil.c
@@ -88,7 +88,7 @@ void setdosmemword(int offset, unsigned short w)
 
 void PDC_dpmi_int(int vector, pdc_dpmi_regs *rmregs)
 {
-    union REGPACK regs = {0};
+    union REGPACK regs = {};
 
     rmregs->w.ss = 0;
     rmregs->w.sp = 0;
diff --git a/src/drivers/wifi/generic/acpi.c b/src/drivers/wifi/generic/acpi.c
index 753492abad..fd57120594 100644
--- a/src/drivers/wifi/generic/acpi.c
+++ b/src/drivers/wifi/generic/acpi.c
@@ -1246,7 +1246,7 @@ static void wifi_ssdt_write_properties(const struct device *dev, const char *sco
 	struct dsm_uuid dsm_ids[MAX_DSM_FUNCS];
 
 	/* Retrieve the SAR limits data */
-	union wifi_sar_limits sar_limits = {0};
+	union wifi_sar_limits sar_limits = {};
 	bool sar_loaded = false;
 	if (CONFIG(USE_SAR)) {
 		if (get_wifi_sar_limits(&sar_limits) < 0)
diff --git a/src/soc/mediatek/common/dp/dptx_common.c b/src/soc/mediatek/common/dp/dptx_common.c
index d6747f78bc..c2d6f5119b 100644
--- a/src/soc/mediatek/common/dp/dptx_common.c
+++ b/src/soc/mediatek/common/dp/dptx_common.c
@@ -356,7 +356,7 @@ static void dptx_set_tu(struct mtk_dp *mtk_dp)
 static void dptx_set_misc(struct mtk_dp *mtk_dp)
 {
 	u8 format, depth;
-	union misc_t dptx_misc = { .cmisc = {0} };
+	union misc_t dptx_misc = { .cmisc = {} };
 
 	format = mtk_dp->info.format;
 	depth = mtk_dp->info.depth;

From 281b01ce5e338d4a8902f3e1c9af54ee11e457f2 Mon Sep 17 00:00:00 2001
From: Subrata Banik <subratabanik@google.com>
Date: Sun, 10 Aug 2025 15:03:02 +0530
Subject: [PATCH 1772/3886] soc/qualcomm/x1p42100: Remove unused PMIC file from
 CBFS

This commit removes the Pmic.bin file from the coreboot filesystem
(CBFS) and the Makefile.mk for the Qualcomm x1p42100 SoC.

The PMIC file is no longer used in the boot process. It's safe to
remove it to reduce the size of the final coreboot image and clean
up the build configuration.

TEST=Able to build and boot google/quenbi.

Change-Id: Iac8e4b32677f36959323a5dd3a5c7f88a6359720
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88736
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/soc/qualcomm/x1p42100/Makefile.mk | 8 --------
 1 file changed, 8 deletions(-)

diff --git a/src/soc/qualcomm/x1p42100/Makefile.mk b/src/soc/qualcomm/x1p42100/Makefile.mk
index 51770fd8f7..a69a87daf7 100644
--- a/src/soc/qualcomm/x1p42100/Makefile.mk
+++ b/src/soc/qualcomm/x1p42100/Makefile.mk
@@ -97,14 +97,6 @@ $(QCLIB_CBFS)-type := stage
 $(QCLIB_CBFS)-compression := $(CBFS_PRERAM_COMPRESS_FLAG)
 cbfs-files-y += $(QCLIB_CBFS)
 
-################################################################################
-PMIC_FILE := $(X1P42100_BLOB)/boot/Pmic.bin
-PMIC_CBFS := $(CONFIG_CBFS_PREFIX)/pmiccfg
-$(PMIC_CBFS)-file := $(PMIC_FILE)
-$(PMIC_CBFS)-type := raw
-$(PMIC_CBFS)-compression := $(CBFS_COMPRESS_FLAG)
-cbfs-files-y += $(PMIC_CBFS)
-
 ################################################################################
 DCB_FILE := $(X1P42100_BLOB)/boot/dcb.bin
 DCB_CBFS := $(CONFIG_CBFS_PREFIX)/dcb

From 2e61995b2f62251472c02a93a24fa540e2f29c41 Mon Sep 17 00:00:00 2001
From: Subrata Banik <subratabanik@google.com>
Date: Sun, 10 Aug 2025 15:32:06 +0530
Subject: [PATCH 1773/3886] soc/qualcomm/x1p42100: Add support for Hamoa SoC

Introduce a new `SOC_QUALCOMM_HAMOA` Kconfig option and refactor the
Qualcomm SoC build to support Hamoa.

This change prepares the groundwork for Hamoa-based mainboards by:

- Creating a common base: A new `SOC_QUALCOMM_BASE` Kconfig option
  is introduced to group configurations shared between Qualcomm SoCs.
- Separating SoC-specific blobs: The build process now dynamically
  selects the correct device tree blob (DTB) and display control blob
  (DCB) files for Hamoa via a new `DTB_DCB_BLOB_PATH` variable in the
  `Makefile.mk`.
- Enabling future mainboards: This allows mainboards built on the Hamoa
  SoC to be configured and built within the existing Qualcomm SoC
  directory.

BUG=b:437662790
TEST=Able to build and boot google/quenbi.

Change-Id: Ife983495b757fbf06ad96f0ca15fd89bf41c77c0
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88737
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/soc/qualcomm/x1p42100/Kconfig     | 18 ++++++++++++++++--
 src/soc/qualcomm/x1p42100/Makefile.mk | 14 ++++++++++----
 2 files changed, 26 insertions(+), 6 deletions(-)

diff --git a/src/soc/qualcomm/x1p42100/Kconfig b/src/soc/qualcomm/x1p42100/Kconfig
index 636f6032e2..26bcb22920 100644
--- a/src/soc/qualcomm/x1p42100/Kconfig
+++ b/src/soc/qualcomm/x1p42100/Kconfig
@@ -1,6 +1,6 @@
 ## SPDX-License-Identifier: GPL-2.0-only
 
-config SOC_QUALCOMM_X1P42100
+config SOC_QUALCOMM_BASE
 	bool
 	default n
 	select ARCH_BOOTBLOCK_ARMV8_64
@@ -29,7 +29,21 @@ config SOC_QUALCOMM_X1P42100
 	select SDHCI_CONTROLLER
 	select SOC_QUALCOMM_COMMON
 
-if SOC_QUALCOMM_X1P42100
+config SOC_QUALCOMM_X1P42100
+	bool
+	select SOC_QUALCOMM_BASE
+	default n
+	help
+	  Choose this option if the mainboard is built using Qualcomm X1P42100 system-on-a-chip SoC.
+
+config SOC_QUALCOMM_HAMOA
+	bool
+	select SOC_QUALCOMM_BASE
+	default n
+	help
+	  Choose this option if the mainboard is built using Qualcomm Hamoa system-on-a-chip SoC.
+
+if SOC_QUALCOMM_BASE
 
 config QC_BLOBS_UPSTREAM
 	bool "QC blobs are available in upstream repository"
diff --git a/src/soc/qualcomm/x1p42100/Makefile.mk b/src/soc/qualcomm/x1p42100/Makefile.mk
index a69a87daf7..62930c9c33 100644
--- a/src/soc/qualcomm/x1p42100/Makefile.mk
+++ b/src/soc/qualcomm/x1p42100/Makefile.mk
@@ -1,5 +1,5 @@
 ## SPDX-License-Identifier: GPL-2.0-only
-ifeq ($(CONFIG_SOC_QUALCOMM_X1P42100),y)
+ifeq ($(CONFIG_SOC_QUALCOMM_BASE),y)
 
 decompressor-y += decompressor.c
 decompressor-y += mmu.c
@@ -57,6 +57,12 @@ ifeq ($(CONFIG_USE_QC_BLOBS),y)
 # TODO: Upload X1P42100 SoC blobs
 X1P42100_BLOB := $(top)/3rdparty/qc_blobs/x1p42100
 
+ifeq ($(CONFIG_SOC_QUALCOMM_HAMOA),y)
+DTB_DCB_BLOB_PATH := hamoa
+else
+DTB_DCB_BLOB_PATH := x1p42100
+endif
+
 ifeq ($(CONFIG_QC_SDI_ENABLE),y)
 BL31_MAKEARGS += QTI_SDI_BUILD=1
 BL31_MAKEARGS += QTISECLIB_PATH=$(X1P42100_BLOB)/qtiseclib/libqtisec_dbg.a
@@ -98,7 +104,7 @@ $(QCLIB_CBFS)-compression := $(CBFS_PRERAM_COMPRESS_FLAG)
 cbfs-files-y += $(QCLIB_CBFS)
 
 ################################################################################
-DCB_FILE := $(X1P42100_BLOB)/boot/dcb.bin
+DCB_FILE := $(X1P42100_BLOB)/boot/$(DTB_DCB_BLOB_PATH)/dcb.bin
 DCB_CBFS := $(CONFIG_CBFS_PREFIX)/dcb
 $(DCB_CBFS)-file := $(DCB_FILE)
 $(DCB_CBFS)-type := raw
@@ -106,7 +112,7 @@ $(DCB_CBFS)-compression := $(CBFS_COMPRESS_FLAG)
 cbfs-files-y += $(DCB_CBFS)
 
 ################################################################################
-DTB_FILE := $(X1P42100_BLOB)/boot/pre-ddr.dtb
+DTB_FILE := $(X1P42100_BLOB)/boot/$(DTB_DCB_BLOB_PATH)/pre-ddr.dtb
 DTB_CBFS := $(CONFIG_CBFS_PREFIX)/dtb
 $(DTB_CBFS)-file := $(DTB_FILE)
 $(DTB_CBFS)-type := raw
@@ -215,4 +221,4 @@ cbfs-files-y += $(GSI_FW_CBFS)
 endif # ifeq ($(CONFIG_USE_QC_BLOBS),y)
 
 endif # ifeq ($(CONFIG_QC_BLOBS_UPSTREAM),y)
-endif # ifeq ($(CONFIG_SOC_QUALCOMM_X1P42100),y)
+endif # ifeq ($(CONFIG_SOC_QUALCOMM_BASE),y)

From 90589d44d2eddc7332633091f4cc506a9a782893 Mon Sep 17 00:00:00 2001
From: Swathi Tamilselvan <tswathi@qualcomm.corp-partner.google.com>
Date: Fri, 8 Aug 2025 13:58:48 +0530
Subject: [PATCH 1774/3886] soc/qualcomm/x1p42100: Reserve DDR memory regions
 for AOP and BL31

Updated the memory layout file to include necessary DDR region
reservations for AOP and BL31.

TEST=Create an image.serial.bin and ensure it boots on X1P42100.

Change-Id: I67b0210dfc563c0a0e8f879b1f41693e1d0e6384
Signed-off-by: Swathi Tamilselvan <tswathi@qualcomm.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88724
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
---
 src/soc/qualcomm/x1p42100/memlayout.ld | 3 ++-
 src/soc/qualcomm/x1p42100/soc.c        | 5 ++++-
 2 files changed, 6 insertions(+), 2 deletions(-)

diff --git a/src/soc/qualcomm/x1p42100/memlayout.ld b/src/soc/qualcomm/x1p42100/memlayout.ld
index 664ef3570c..0e44bd6e8b 100644
--- a/src/soc/qualcomm/x1p42100/memlayout.ld
+++ b/src/soc/qualcomm/x1p42100/memlayout.ld
@@ -57,7 +57,8 @@ SECTIONS
 	REGION(shrm, 0x24040000, 128K , 4K)
 
 	DRAM_START(0x80000000)
+	REGION(dram_aop, 0x81c00000, 0x0a0000, 0x1000)
 	POSTRAM_CBFS_CACHE(0x9F800000, 16M)
 	RAMSTAGE(0xA0800000, 16M)
-	BL31(0xC0000000, 1M)
+	BL31(0xD80D6000, 1M)
 }
diff --git a/src/soc/qualcomm/x1p42100/soc.c b/src/soc/qualcomm/x1p42100/soc.c
index f43d348684..0dd4a4035b 100644
--- a/src/soc/qualcomm/x1p42100/soc.c
+++ b/src/soc/qualcomm/x1p42100/soc.c
@@ -1,6 +1,8 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
 #include <device/device.h>
+#include <soc/mmu.h>
+#include <soc/mmu_common.h>
 #include <soc/symbols_common.h>
 #include <soc/pcie.h>
 
@@ -12,7 +14,8 @@ static struct device_operations pci_domain_ops = {
 };
 static void soc_read_resources(struct device *dev)
 {
-	/* placeholder */
+	ram_range(dev, 0, (uintptr_t)region_offset(ddr_region), region_sz(ddr_region));
+	reserved_ram_range(dev, 1, (uintptr_t)_dram_aop, REGION_SIZE(dram_aop));
 }
 
 static void soc_init(struct device *dev)

From 13897bde9a1acfaa3c08a232884cb888776e61c2 Mon Sep 17 00:00:00 2001
From: Luca Lai <luca.lai@lcfc.corp-partner.google.com>
Date: Mon, 11 Aug 2025 16:59:00 +0800
Subject: [PATCH 1775/3886] mb/google/trulo/var/pujjolo: Add wlan rtd3 setting

Because of preventing S0ix fail caused by wlan, so according to
intel suggestion, add wlan rtd3 setting.

BUG=b:422600523
TEST= Build and boot to OS and check S0ix test using
`suspend_stress_test -c 5` work fine.

Change-Id: I959da35d60e0da058727519d6db082ea415dbe2a
Signed-off-by: Luca Lai <luca.lai@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88743
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
---
 src/mainboard/google/brya/variants/pujjolo/overridetree.cb | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/src/mainboard/google/brya/variants/pujjolo/overridetree.cb b/src/mainboard/google/brya/variants/pujjolo/overridetree.cb
index c8479ee655..0ccb3c634a 100644
--- a/src/mainboard/google/brya/variants/pujjolo/overridetree.cb
+++ b/src/mainboard/google/brya/variants/pujjolo/overridetree.cb
@@ -548,6 +548,12 @@ chip soc/intel/alderlake
 				register "add_acpi_dma_property" = "true"
 				device pci 00.0 on end
 			end
+			chip soc/intel/common/block/pcie/rtd3
+				register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E10)"
+				register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_H20)"
+				register "srcclk_pin" = "3"
+				device generic 0 on end
+			end
 		end
 		device ref pcie_rp7 on
 			# Enable SD Card PCIE 7 using clk 3

From bdcf19f404a69283fa7c9ff245912d562474cfca Mon Sep 17 00:00:00 2001
From: Luca Lai <luca.lai@lcfc.corp-partner.google.com>
Date: Wed, 6 Aug 2025 11:21:52 +0800
Subject: [PATCH 1776/3886] mb/google/trulo/var/pujjolo: Add fw config for PDC

Because the EQ tuning is different from type-c C1 port in
pujjolo and pujjoquince daughter board, so use fw config to
assign the specific PDC fw.

BUG=b:436445362
TEST= Build and boot to OS and check PDC FW version.

Change-Id: Id9ce85e40e919ab572ce1c560b4daf3c977de682
Signed-off-by: Luca Lai <luca.lai@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88698
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/google/brya/variants/pujjolo/overridetree.cb | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/src/mainboard/google/brya/variants/pujjolo/overridetree.cb b/src/mainboard/google/brya/variants/pujjolo/overridetree.cb
index 0ccb3c634a..d9cd5cb22c 100644
--- a/src/mainboard/google/brya/variants/pujjolo/overridetree.cb
+++ b/src/mainboard/google/brya/variants/pujjolo/overridetree.cb
@@ -8,6 +8,10 @@ fw_config
 		option WIFI_SAR_TABLE_AX211	0
 		option WIFI_SAR_TABLE_AX203	1
 	end
+	field PDC 21 22
+		option PDC_PUJJOQUINCE        0
+		option PDC_PUJJOLO       1
+	end
 	field FP 24
 		option FP_ABSENT	0
 		option FP_PRESENT	1

From e31fbc493de4b37eec8a8f3696d874774f62832f Mon Sep 17 00:00:00 2001
From: Swathi Tamilselvan <tswathi@qualcomm.corp-partner.google.com>
Date: Sun, 10 Aug 2025 23:03:20 -0700
Subject: [PATCH 1777/3886] soc/qualcomm/cmn/qclib: Support reuse of existing
 DDR training data

This patch adds support to skip DDR training when valid training data
is available in flash.

The exact size of the training data is passed to ensure accurate hash
computation. A hash is computed on the DDR training data using the
specified size and compared with the stored hash in the header. This
requires passing only the exact training data size to ensure correct
validation.

TEST=Create an image.serial.bin and ensure it boots on X1P42100. Verify
that the DDR training is skipped when valid data is available in flash.

w/o this patch: doing RW_MRC_CACHE update in every boot.

```
[DEBUG]  MRC: Checking cached data update for 'RW_MRC_CACHE'.
[DEBUG]  read SPI 0xc1f290 0xf27c: 5010 us, 12390 KB/s, 99.120 Mbps
[DEBUG]  MRC: cache data 'RW_MRC_CACHE' needs update.
[DEBUG]  MRC: updated 'RW_MRC_CACHE'.
```

w/ this patch: no need to perform RW_MRC_CACHE update.

```
[DEBUG]  FMAP: area RW_MRC_CACHE found @ c10000 (65536 bytes)
[DEBUG]  read SPI 0xc10024 0xf268: 5016 us, 12371 KB/s, 98.968 Mbps
```

Change-Id: I1a5ad0766ea77b22e6a8cb97c24a90c24629dfd0
Signed-off-by: Swathi Tamilselvan <tswathi@qualcomm.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88742
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
Reviewed-by: Jayvik Desai <jayvik@google.com>
Reviewed-by: Pranava Y N <pranavayn@google.com>
---
 src/soc/qualcomm/common/qclib.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/src/soc/qualcomm/common/qclib.c b/src/soc/qualcomm/common/qclib.c
index 6a1df18d8a..8d73f04d34 100644
--- a/src/soc/qualcomm/common/qclib.c
+++ b/src/soc/qualcomm/common/qclib.c
@@ -252,9 +252,10 @@ void qclib_load_and_run(void)
 	if (data_size < 0) {
 		printk(BIOS_ERR, "Unable to load previous training data.\n");
 		memset(_ddr_training, 0, REGION_SIZE(ddr_training));
+		data_size = REGION_SIZE(ddr_training);
 	}
 	qclib_add_if_table_entry(QCLIB_TE_DDR_TRAINING_DATA,
-				 _ddr_training, REGION_SIZE(ddr_training), 0);
+			_ddr_training, data_size, 0);
 
 	/* Address and size of this entry will be filled in by QcLib. */
 	qclib_add_if_table_entry(QCLIB_TE_MEM_CHIP_INFO, NULL, 0, 0);

From 77b52ed3cce7c5bac1f591ab4fa994adc4a0a73b Mon Sep 17 00:00:00 2001
From: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Date: Mon, 4 Aug 2025 13:57:08 +0800
Subject: [PATCH 1778/3886] mb/google/brox/var/caboc: HDA: Correct number of
 jacks to 35
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Commit 32b944b77a3b ("mb/google/brox/var/caboc: Update hda_verb table"), CB:88627 didn’t update the number of jacks, so do it now.

BUG=b:435345756
TEST=emerge-brox coreboot
     check system audio output is fine

Change-Id: Id559ceba2d5c21b120c76147bf042520e57865a7
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88644
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
---
 .../google/brox/variants/caboc/include/variant/hda_verb.h       | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/mainboard/google/brox/variants/caboc/include/variant/hda_verb.h b/src/mainboard/google/brox/variants/caboc/include/variant/hda_verb.h
index 495d3b7dab..5a6c2745ee 100644
--- a/src/mainboard/google/brox/variants/caboc/include/variant/hda_verb.h
+++ b/src/mainboard/google/brox/variants/caboc/include/variant/hda_verb.h
@@ -9,7 +9,7 @@ const u32 cim_verb_data[] = {
 	/* coreboot specific header */
 	0x10ec0236,	// Codec Vendor / Device ID: Realtek ALC236
 	0x103C8C60,	// Subsystem ID
-	0x00000017,	// Number of jacks (NID entries)
+	0x00000023,	// Number of jacks (NID entries)
 
 	AZALIA_RESET(0x1),
 	/* NID 0x01, HDA Codec Subsystem ID Verb table */

From c418a3b843aa169c6b7ee4d77280b993f4e68a9c Mon Sep 17 00:00:00 2001
From: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Date: Thu, 7 Aug 2025 16:23:08 +0800
Subject: [PATCH 1779/3886] mb/google/brox/var/caboc: Update WWAN gpio

Caboc schematic 0702 uses a MOS reverse pin to connect
GPP_A21(WWAN_FWUPD) to WWAN(PERST). The WWAN_PERST is a low active pin.
Change GPP_A21 and overridtree setting based on the above description.

BUG=b:437017620
TEST=emerge-brox coreboot
     WWAN module is enumerated in lspci
     modem status can find WWAN module

Change-Id: I3b75b53f0e5731b2fec48634c672a6432acdde7f
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88706
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
---
 src/mainboard/google/brox/variants/caboc/gpio.c          | 6 +++---
 src/mainboard/google/brox/variants/caboc/overridetree.cb | 4 ++--
 2 files changed, 5 insertions(+), 5 deletions(-)

diff --git a/src/mainboard/google/brox/variants/caboc/gpio.c b/src/mainboard/google/brox/variants/caboc/gpio.c
index e2127d0ceb..49934999cf 100644
--- a/src/mainboard/google/brox/variants/caboc/gpio.c
+++ b/src/mainboard/google/brox/variants/caboc/gpio.c
@@ -17,7 +17,7 @@ static const struct pad_config override_gpio_table[] = {
 	/* GPP_A17 : [NF4: DISP_MISCC NF6: USB_C_GPP_A17] ==> WWAN_TRANSMIT_OFF(WAN_RF_DISABLE_ODL) */
 	PAD_CFG_GPO(GPP_A17, 1, DEEP),
 	/* GPP_A21 : [NF1: DDPC_CTRLCLK NF6: USB_C_GPP_A21] ==> WWAN_ASPM_EXIT(WWAN_PERST_L) */
-	PAD_CFG_GPO(GPP_A21, 1, DEEP),
+	PAD_CFG_GPO(GPP_A21, 0, DEEP),
 
 	/* GPP_D4 : [NF1: IMGCLKOUT0 NF2: BK4 NF5: SBK4 NF6: USB_C_GPP_D4] ==> WWAN_GPS_XMIT_OFF */
 	PAD_CFG_GPO(GPP_D4, 0, DEEP),
@@ -75,7 +75,7 @@ static const struct pad_config early_gpio_table[] = {
 	/* F21 : [NF1: Reserved NF6: USB_C_GPP_F21] ==> WWAN_OFF#(WWAN_FCPO_L) */
 	PAD_CFG_GPO(GPP_F21, 0, DEEP),
 	/* GPP_A21 : [NF1: DDPC_CTRLCLK NF6: USB_C_GPP_A21] ==> WWAN_ASPM_EXIT(WWAN_PERST_L) */
-	PAD_CFG_GPO(GPP_A21, 0, DEEP),
+	PAD_CFG_GPO(GPP_A21, 1, DEEP),
 	/* GPP_D19 : [NF1: I2S_MCLK1_OUT NF6: USB_C_GPP_D19] ==> WWAM_FWUPD#(WWAN_RST_L) */
 	PAD_CFG_GPO(GPP_D19, 0, DEEP),
 
@@ -140,7 +140,7 @@ static const struct pad_config romstage_gpio_table[] = {
 	/* F21 : [NF1: Reserved NF6: USB_C_GPP_F21] ==> WWAN_OFF#(WWAN_FCPO_L) */
 	PAD_CFG_GPO(GPP_F21, 1, DEEP),
 	/* GPP_A21 : [NF1: DDPC_CTRLCLK NF6: USB_C_GPP_A21] ==> WWAN_ASPM_EXIT(WWAN_PERST_L) */
-	PAD_CFG_GPO(GPP_A21, 0, DEEP),
+	PAD_CFG_GPO(GPP_A21, 1, DEEP),
 	/* GPP_D19 : [NF1: I2S_MCLK1_OUT NF6: USB_C_GPP_D19] ==> WWAM_FWUPD#(WWAN_RST_L) */
 	PAD_CFG_GPO(GPP_D19, 0, DEEP),
 
diff --git a/src/mainboard/google/brox/variants/caboc/overridetree.cb b/src/mainboard/google/brox/variants/caboc/overridetree.cb
index 1270765c9a..c70aeca5d1 100644
--- a/src/mainboard/google/brox/variants/caboc/overridetree.cb
+++ b/src/mainboard/google/brox/variants/caboc/overridetree.cb
@@ -252,7 +252,7 @@ chip soc/intel/alderlake
 				.flags = PCIE_RP_LTR | PCIE_RP_AER,
 			}"
 			chip soc/intel/common/block/pcie/rtd3
-				register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A21)"
+				register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A21)"
 				register "reset_off_delay_ms" = "20"
 				register "srcclk_pin" = "6"
 				register "ext_pm_support" = "ACPI_PCIE_RP_EMIT_ALL"
@@ -265,7 +265,7 @@ chip soc/intel/alderlake
 			chip drivers/wwan/fm
 				register "fcpo_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_F21)"
 				register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D19)"
-				register "perst_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A21)"
+				register "perst_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A21)"
 				register "wake_gpio" = "ACPI_GPIO_IRQ_EDGE_LOW(GPP_E5)"
 				register "add_acpi_dma_property" = "true"
 				use rp4_rtd3 as rtd3dev

From e49e8c6355d2b0bd72897f496607ed94a49212fc Mon Sep 17 00:00:00 2001
From: Subrata Banik <subratabanik@google.com>
Date: Tue, 12 Aug 2025 13:38:20 +0530
Subject: [PATCH 1780/3886] soc/qc/x1p42100: Add memory layouts for CPUCP and
 TZ regions

The commit adds new memory regions for the CPUCP (CPU Subsystem Control
Processor) and TZ (TrustZone) components to the x1p42100 SoC. This is
necessary to properly reserve the memory used by these firmware
components during boot.

The changes involve:
 - Declaring new memory regions dram_cpucp_dtbs, dram_cpucp, dram_tz,
   and dram_tz_rem in the symbols_common.h header.
 - Defining the base addresses and sizes for these new regions in
   memlayout.ld.

Registering these memory ranges as reserved in the soc_read_resources
function in soc.c so that coreboot does not overwrite them.

TEST=Able to load aop firmware while booting google/quenbi without
boot hang.

Change-Id: I1ecbc1e5ea420b7bdd5518612082ca0e14b35f6e
Signed-off-by: Subrata Banik <subratabanik@google.com>
Suggested-by: Swathi Tamilselvan <tswathi@qualcomm.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88750
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
---
 src/soc/qualcomm/common/include/soc/symbols_common.h | 3 +++
 src/soc/qualcomm/x1p42100/memlayout.ld               | 6 +++++-
 src/soc/qualcomm/x1p42100/soc.c                      | 8 +++++++-
 3 files changed, 15 insertions(+), 2 deletions(-)

diff --git a/src/soc/qualcomm/common/include/soc/symbols_common.h b/src/soc/qualcomm/common/include/soc/symbols_common.h
index 461ffb7d0e..9d39db255e 100644
--- a/src/soc/qualcomm/common/include/soc/symbols_common.h
+++ b/src/soc/qualcomm/common/include/soc/symbols_common.h
@@ -26,7 +26,10 @@ DECLARE_REGION(dram_modem_extra)
 DECLARE_REGION(dram_wlan)
 DECLARE_REGION(dram_wpss)
 DECLARE_REGION(shrm)
+DECLARE_REGION(dram_cpucp_dtbs)
 DECLARE_REGION(dram_cpucp)
 DECLARE_REGION(dram_modem)
+DECLARE_REGION(dram_tz)
+DECLARE_REGION(dram_tz_rem)
 
 #endif // _SOC_QUALCOMM_SYMBOLS_COMMON_H_
diff --git a/src/soc/qualcomm/x1p42100/memlayout.ld b/src/soc/qualcomm/x1p42100/memlayout.ld
index 0e44bd6e8b..27f4be7e1a 100644
--- a/src/soc/qualcomm/x1p42100/memlayout.ld
+++ b/src/soc/qualcomm/x1p42100/memlayout.ld
@@ -57,8 +57,12 @@ SECTIONS
 	REGION(shrm, 0x24040000, 128K , 4K)
 
 	DRAM_START(0x80000000)
-	REGION(dram_aop, 0x81c00000, 0x0a0000, 0x1000)
+	REGION(dram_cpucp_dtbs, 0x81240000, 0x2000, 0x1000)
+	REGION(dram_cpucp, 0x81250000, 0x80000, 0x1000)
+	REGION(dram_aop, 0x81C00000, 0xF780000, 0x1000)
 	POSTRAM_CBFS_CACHE(0x9F800000, 16M)
 	RAMSTAGE(0xA0800000, 16M)
+	REGION(dram_tz, 0xD8000000, 0xD6000, 0x1000)
 	BL31(0xD80D6000, 1M)
+	REGION(dram_tz_rem, 0xD81D6000, 0x72EA000, 0x1000)
 }
diff --git a/src/soc/qualcomm/x1p42100/soc.c b/src/soc/qualcomm/x1p42100/soc.c
index 0dd4a4035b..a30c1b0ba4 100644
--- a/src/soc/qualcomm/x1p42100/soc.c
+++ b/src/soc/qualcomm/x1p42100/soc.c
@@ -15,7 +15,13 @@ static struct device_operations pci_domain_ops = {
 static void soc_read_resources(struct device *dev)
 {
 	ram_range(dev, 0, (uintptr_t)region_offset(ddr_region), region_sz(ddr_region));
-	reserved_ram_range(dev, 1, (uintptr_t)_dram_aop, REGION_SIZE(dram_aop));
+	reserved_ram_range(dev, 1, (uintptr_t)_dram_cpucp_dtbs, REGION_SIZE(dram_cpucp_dtbs));
+	reserved_ram_range(dev, 2, (uintptr_t)_dram_cpucp, REGION_SIZE(dram_cpucp));
+
+	reserved_ram_range(dev, 3, (uintptr_t)_dram_tz, REGION_SIZE(dram_tz));
+	reserved_ram_range(dev, 4, (uintptr_t)_dram_tz_rem, REGION_SIZE(dram_tz_rem));
+
+	reserved_ram_range(dev, 5, (uintptr_t)_dram_aop, REGION_SIZE(dram_aop));
 }
 
 static void soc_init(struct device *dev)

From 6bb1ba95e1600e94e9d9e4effef96d4488ef201e Mon Sep 17 00:00:00 2001
From: Yidi Lin <yidilin@google.com>
Date: Mon, 28 Jul 2025 11:48:44 +0800
Subject: [PATCH 1781/3886] soc/mediatek/common/dp: Move mtk_edp_init to
 dptx_common.c

mtk_edp_init is similar in dptx_v1.c and dptx_v2.c. Make mtk_edp_init
common by

1. Extract dptx_set_tx_power_con and dptx_set_26mhz_clock to
   edp_power_on.
2. Add dptx_hal_phy_init weak function for the platform which does not
   require initialization.

TEST=emerge-cherry coreboot && emerge-rauru coreboot

Change-Id: I686208c6bf8538354fb4fd238755899b0ef8f86b
Signed-off-by: Yidi Lin <yidilin@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88582
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
---
 src/soc/mediatek/common/dp/dptx_common.c      | 61 ++++++++++++++++++-
 src/soc/mediatek/common/dp/dptx_hal_common.c  |  2 +
 src/soc/mediatek/common/dp/dptx_v1.c          | 46 +-------------
 src/soc/mediatek/common/dp/dptx_v2.c          | 54 +---------------
 .../common/dp/include/soc/dptx_common.h       |  4 +-
 .../common/dp/include/soc/dptx_hal_common.h   |  1 +
 .../common/dp/include/soc/dptx_hal_v2.h       |  1 -
 7 files changed, 67 insertions(+), 102 deletions(-)

diff --git a/src/soc/mediatek/common/dp/dptx_common.c b/src/soc/mediatek/common/dp/dptx_common.c
index c2d6f5119b..5326fb55e7 100644
--- a/src/soc/mediatek/common/dp/dptx_common.c
+++ b/src/soc/mediatek/common/dp/dptx_common.c
@@ -70,7 +70,7 @@ bool dptx_auxread_dpcd(struct mtk_dp *mtk_dp, u8 cmd, u32 dpcd_addr,
 	return ret;
 }
 
-int dptx_get_edid(struct mtk_dp *mtk_dp, struct edid *out)
+static int dptx_get_edid(struct mtk_dp *mtk_dp, struct edid *out)
 {
 	int ret;
 	u8 edid[EDID_BUF_SIZE];
@@ -401,7 +401,7 @@ static void dptx_set_dptxout(struct mtk_dp *mtk_dp)
 	dptx_set_tu(mtk_dp);
 }
 
-void dptx_check_sinkcap(struct mtk_dp *mtk_dp)
+static void dptx_check_sinkcap(struct mtk_dp *mtk_dp)
 {
 	u8 buffer[16];
 
@@ -511,3 +511,60 @@ void dptx_video_config(struct mtk_dp *mtk_dp)
 	dptx_set_color_depth(mtk_dp, mtk_dp->info.depth);
 	dptx_set_color_format(mtk_dp, mtk_dp->info.format);
 }
+
+static void dptx_init_port(struct mtk_dp *mtk_dp)
+{
+	dptx_hal_phy_setidlepattern(mtk_dp, true);
+	dptx_hal_init_setting(mtk_dp);
+	dptx_hal_aux_setting(mtk_dp);
+	dptx_hal_digital_setting(mtk_dp);
+	dptx_hal_phy_init(mtk_dp);
+	dptx_hal_phy_setting(mtk_dp);
+	dptx_hal_hpd_detect_setting(mtk_dp);
+
+	dptx_hal_digital_swreset(mtk_dp);
+
+	dptx_hal_analog_power_en(mtk_dp, true);
+	dptx_hal_hpd_int_en(mtk_dp, true);
+}
+
+__weak void dptx_power_on(void) { /* do nothing */ };
+
+int mtk_edp_init(struct mtk_dp *mtk_dp, struct edid *edid)
+{
+	dptx_power_on();
+	dptx_init_variable(mtk_dp);
+	dptx_init_port(mtk_dp);
+
+	if (!dptx_hal_hpd_high(mtk_dp)) {
+		printk(BIOS_ERR, "HPD is low\n");
+		return -1;
+	}
+
+	dptx_check_sinkcap(mtk_dp);
+
+	if (dptx_get_edid(mtk_dp, edid) != 0) {
+		printk(BIOS_ERR, "Failed to get EDID\n");
+		return -1;
+	}
+
+	if (dptx_set_trainingstart(mtk_dp) != DPTX_PASS) {
+		printk(BIOS_ERR, "%s: Failed to set training start\n", __func__);
+		return -1;
+	}
+
+	dp_intf_config(edid);
+	dptx_video_config(mtk_dp);
+
+	return 0;
+}
+
+int mtk_edp_enable(struct mtk_dp *mtk_dp)
+{
+	if (!mtk_dp) {
+		printk(BIOS_ERR, "%s: eDP is not initialized\n", __func__);
+		return -1;
+	}
+	dptx_video_enable(mtk_dp, true);
+	return 0;
+}
diff --git a/src/soc/mediatek/common/dp/dptx_hal_common.c b/src/soc/mediatek/common/dp/dptx_hal_common.c
index 3e2a0b374a..42208a14b2 100644
--- a/src/soc/mediatek/common/dp/dptx_hal_common.c
+++ b/src/soc/mediatek/common/dp/dptx_hal_common.c
@@ -563,3 +563,5 @@ void dptx_hal_analog_power_en(struct mtk_dp *mtk_dp, bool enable)
 		DP_WRITE2BYTE(mtk_dp, 0x0038, 0x555);
 	}
 }
+
+__weak void dptx_hal_phy_init(struct mtk_dp *mtk_dp) { /* do nothing */ }
diff --git a/src/soc/mediatek/common/dp/dptx_v1.c b/src/soc/mediatek/common/dp/dptx_v1.c
index 7001282128..bf95eff967 100644
--- a/src/soc/mediatek/common/dp/dptx_v1.c
+++ b/src/soc/mediatek/common/dp/dptx_v1.c
@@ -357,7 +357,7 @@ static void dptx_training_changemode(struct mtk_dp *mtk_dp)
 	mdelay(2);
 }
 
-static int dptx_set_trainingstart(struct mtk_dp *mtk_dp)
+int dptx_set_trainingstart(struct mtk_dp *mtk_dp)
 {
 	u8 lanecount;
 	u8 linkrate;
@@ -453,47 +453,3 @@ static int dptx_set_trainingstart(struct mtk_dp *mtk_dp)
 
 	return DPTX_TRANING_FAIL;
 }
-
-static void dptx_init_port(struct mtk_dp *mtk_dp)
-{
-	dptx_hal_phy_setidlepattern(mtk_dp, true);
-	dptx_hal_init_setting(mtk_dp);
-	dptx_hal_aux_setting(mtk_dp);
-	dptx_hal_digital_setting(mtk_dp);
-	dptx_hal_phy_setting(mtk_dp);
-	dptx_hal_hpd_detect_setting(mtk_dp);
-
-	dptx_hal_digital_swreset(mtk_dp);
-	dptx_hal_analog_power_en(mtk_dp, true);
-	dptx_hal_hpd_int_en(mtk_dp, true);
-}
-
-int mtk_edp_init(struct mtk_dp *mtk_dp, struct edid *edid)
-{
-	dptx_init_variable(mtk_dp);
-	dptx_init_port(mtk_dp);
-
-	if (!dptx_hal_hpd_high(mtk_dp)) {
-		printk(BIOS_ERR, "HPD is low\n");
-		return -1;
-	}
-
-	dptx_check_sinkcap(mtk_dp);
-
-	if (dptx_get_edid(mtk_dp, edid) != 0) {
-		printk(BIOS_ERR, "Failed to get EDID\n");
-		return -1;
-	}
-
-	dptx_set_trainingstart(mtk_dp);
-	dp_intf_config(edid);
-	dptx_video_config(mtk_dp);
-
-	return 0;
-}
-
-int mtk_edp_enable(struct mtk_dp *mtk_dp)
-{
-	dptx_video_enable(mtk_dp, true);
-	return 0;
-}
diff --git a/src/soc/mediatek/common/dp/dptx_v2.c b/src/soc/mediatek/common/dp/dptx_v2.c
index ab41b86ed2..adea70d140 100644
--- a/src/soc/mediatek/common/dp/dptx_v2.c
+++ b/src/soc/mediatek/common/dp/dptx_v2.c
@@ -247,7 +247,7 @@ static int mtk_edp_train_eq(struct mtk_dp *mtk_dp, u8 lane_count)
 	return DPTX_TIMEOUT;
 }
 
-static int dptx_set_trainingstart(struct mtk_dp *mtk_dp)
+int dptx_set_trainingstart(struct mtk_dp *mtk_dp)
 {
 	u8 lanecount;
 	u8 linkrate;
@@ -354,59 +354,9 @@ static int dptx_set_trainingstart(struct mtk_dp *mtk_dp)
 	return DPTX_PASS;
 }
 
-static void dptx_init_port(struct mtk_dp *mtk_dp)
-{
-	dptx_hal_phy_setidlepattern(mtk_dp, true);
-	dptx_hal_init_setting(mtk_dp);
-	dptx_hal_aux_setting(mtk_dp);
-	dptx_hal_digital_setting(mtk_dp);
-	dptx_hal_phy_init(mtk_dp);
-	dptx_hal_phy_setting(mtk_dp);
-	dptx_hal_hpd_detect_setting(mtk_dp);
-
-	dptx_hal_digital_swreset(mtk_dp);
-
-	dptx_hal_analog_power_en(mtk_dp, true);
-	dptx_hal_hpd_int_en(mtk_dp, true);
-}
-
-int mtk_edp_init(struct mtk_dp *mtk_dp, struct edid *edid)
+void dptx_power_on(void)
 {
 	dptx_set_tx_power_con();
 	dptx_set_26mhz_clock();
 	udelay(50);
-	dptx_init_variable(mtk_dp);
-	dptx_init_port(mtk_dp);
-
-	if (!dptx_hal_hpd_high(mtk_dp)) {
-		printk(BIOS_ERR, "HPD is low\n");
-		return -1;
-	}
-
-	dptx_check_sinkcap(mtk_dp);
-
-	if (dptx_get_edid(mtk_dp, edid) != 0) {
-		printk(BIOS_ERR, "Failed to get EDID\n");
-		return -1;
-	}
-
-	if (dptx_set_trainingstart(mtk_dp) != DPTX_PASS) {
-		printk(BIOS_ERR, "%s: Failed to set training start\n", __func__);
-		return -1;
-	}
-
-	dp_intf_config(edid);
-	dptx_video_config(mtk_dp);
-
-	return 0;
-}
-
-int mtk_edp_enable(struct mtk_dp *mtk_dp)
-{
-	if (!mtk_dp) {
-		printk(BIOS_ERR, "%s: eDP is not initialized\n", __func__);
-		return -1;
-	}
-	dptx_video_enable(mtk_dp, true);
-	return 0;
 }
diff --git a/src/soc/mediatek/common/dp/include/soc/dptx_common.h b/src/soc/mediatek/common/dp/include/soc/dptx_common.h
index 6dcd6adb73..b65948fbad 100644
--- a/src/soc/mediatek/common/dp/include/soc/dptx_common.h
+++ b/src/soc/mediatek/common/dp/include/soc/dptx_common.h
@@ -223,19 +223,19 @@ int mtk_edp_enable(struct mtk_dp *mtk_dp);
 
 void dptx_set_tx_power_con(void);
 void dptx_set_26mhz_clock(void);
+int dptx_set_trainingstart(struct mtk_dp *mtk_dp);
 bool dptx_auxread_dpcd(struct mtk_dp *mtk_dp, u8 cmd, u32 dpcd_addr,
 		       size_t length, u8 *rxbuf);
 bool dptx_auxwrite_dpcd(struct mtk_dp *mtk_dp, u8 cmd, u32 dpcd_addr,
 			size_t length, u8 *data);
 bool dptx_channel_eq_ok(const u8 link_status[DP_LINK_STATUS_SIZE],
 			int lane_count);
-void dptx_check_sinkcap(struct mtk_dp *mtk_dp);
 bool dptx_clock_recovery_ok(const u8 link_status[DP_LINK_STATUS_SIZE],
 			    int lane_count);
 void dptx_init_variable(struct mtk_dp *mtk_dp);
-int dptx_get_edid(struct mtk_dp *mtk_dp, struct edid *out);
 void dptx_link_train_channel_eq_delay(const u8 dpcd[DP_RECEIVER_CAP_SIZE]);
 void dptx_link_train_clock_recovery_delay(const u8 dpcd[DP_RECEIVER_CAP_SIZE]);
+void dptx_power_on(void);
 void dptx_video_config(struct mtk_dp *mtk_dp);
 void dptx_video_enable(struct mtk_dp *mtk_dp, bool enable);
 
diff --git a/src/soc/mediatek/common/dp/include/soc/dptx_hal_common.h b/src/soc/mediatek/common/dp/include/soc/dptx_hal_common.h
index ecd1132bdf..daece24e20 100644
--- a/src/soc/mediatek/common/dp/include/soc/dptx_hal_common.h
+++ b/src/soc/mediatek/common/dp/include/soc/dptx_hal_common.h
@@ -102,5 +102,6 @@ void dptx_hal_set_color_depth(struct mtk_dp *mtk_dp, u8 color_depth);
 void dptx_hal_set_color_format(struct mtk_dp *mtk_dp, u8 color_format);
 void dptx_hal_set_txrate(struct mtk_dp *mtk_dp, u8 value);
 void dptx_hal_analog_power_en(struct mtk_dp *mtk_dp, bool enable);
+void dptx_hal_phy_init(struct mtk_dp *mtk_dp);
 
 #endif /* SOC_MEDIATEK_COMMON_DP_DPTX_HAL_COMMON_H */
diff --git a/src/soc/mediatek/common/dp/include/soc/dptx_hal_v2.h b/src/soc/mediatek/common/dp/include/soc/dptx_hal_v2.h
index 1727b84eb6..b5149b812b 100644
--- a/src/soc/mediatek/common/dp/include/soc/dptx_hal_v2.h
+++ b/src/soc/mediatek/common/dp/include/soc/dptx_hal_v2.h
@@ -20,7 +20,6 @@ extern const int dptx_hal_driving_offset[];
 extern const int dptx_hal_driving_offset_size;
 
 void dptx_hal_swing_emp_reset(struct mtk_dp *mtk_dp);
-void dptx_hal_phy_init(struct mtk_dp *mtk_dp);
 void dptx_hal_phy_set_idle_pattern(struct mtk_dp *mtk_dp, u8 lane_count, bool enable);
 void dptx_hal_phy_set_lanes(struct mtk_dp *mtk_dp, u8 lane_count);
 

From a70bf82036b17ea3f12074306f853e92492dad2f Mon Sep 17 00:00:00 2001
From: Yidi Lin <yidilin@google.com>
Date: Mon, 28 Jul 2025 15:09:56 +0800
Subject: [PATCH 1782/3886] soc/mediatek/common: Measure eDP initialization
 time

Meaure the execution time for following eDP functions.
- dptx_check_sinkcap
- dptx_get_edid
- dptx_set_trainingstart
- mtk_edp_init

These dptx_* functions are the primary contributors to the execution
time of mtk_edp_init, which is only called in dev/recovery mode. This
insight can be used for future boot time optimization by breaking down
the eDP initialization process.

TEST=Boot with DEV mode using the boot image without serial console
support.
TEST=cbmem -c|grep "done after"
[INFO ]  dptx_check_sinkcap done after 38 msecs
[INFO ]  dptx_get_edid done after 294 msecs
[INFO ]  dptx_set_trainingstart done after 100 msecs
[INFO ]  mtk_edp_init done after 438 msecs

Change-Id: I7aabf3a33b9628f20fe16980033b00de9afc44e6
Signed-off-by: Yidi Lin <yidilin@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88584
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
---
 src/soc/mediatek/common/dp/dptx_common.c | 15 +++++++++++++++
 src/soc/mediatek/common/dp/dptx_v1.c     |  5 +++++
 src/soc/mediatek/common/dp/dptx_v2.c     |  6 +++++-
 3 files changed, 25 insertions(+), 1 deletion(-)

diff --git a/src/soc/mediatek/common/dp/dptx_common.c b/src/soc/mediatek/common/dp/dptx_common.c
index 5326fb55e7..9c6cdcba4d 100644
--- a/src/soc/mediatek/common/dp/dptx_common.c
+++ b/src/soc/mediatek/common/dp/dptx_common.c
@@ -11,6 +11,7 @@
 #include <soc/dptx_reg.h>
 #include <soc/dp_intf.h>
 #include <string.h>
+#include <timer.h>
 
 static bool dptx_auxwrite_bytes(struct mtk_dp *mtk_dp, u8 cmd, u32 dpcd_addr,
 			 size_t length, u8 *data)
@@ -77,7 +78,9 @@ static int dptx_get_edid(struct mtk_dp *mtk_dp, struct edid *out)
 	u8 tmp = 0;
 	u8 extblock = 0;
 	size_t total_size;
+	struct stopwatch sw;
 
+	stopwatch_init(&sw);
 	dptx_auxwrite_dpcd(mtk_dp, DP_AUX_I2C_WRITE, 0x50, 0x1, &tmp);
 
 	/* Read 1st block */
@@ -111,6 +114,9 @@ static int dptx_get_edid(struct mtk_dp *mtk_dp, struct edid *out)
 	}
 
 	mtk_dp->edid = out;
+	printk(BIOS_INFO, "%s done after %lld msecs\n", __func__,
+	       stopwatch_duration_msecs(&sw));
+
 	return 0;
 }
 
@@ -404,7 +410,9 @@ static void dptx_set_dptxout(struct mtk_dp *mtk_dp)
 static void dptx_check_sinkcap(struct mtk_dp *mtk_dp)
 {
 	u8 buffer[16];
+	struct stopwatch sw;
 
+	stopwatch_init(&sw);
 	memset(buffer, 0x0, sizeof(buffer));
 
 	buffer[0] = 0x1;
@@ -473,6 +481,8 @@ static void dptx_check_sinkcap(struct mtk_dp *mtk_dp)
 
 	dptx_auxread_dpcd(mtk_dp, DP_AUX_NATIVE_READ,
 			  DPCD_00200, 0x2, buffer);
+	printk(BIOS_INFO, "%s done after %lld msecs\n", __func__,
+	       stopwatch_duration_msecs(&sw));
 }
 
 void dptx_video_enable(struct mtk_dp *mtk_dp, bool enable)
@@ -532,6 +542,9 @@ __weak void dptx_power_on(void) { /* do nothing */ };
 
 int mtk_edp_init(struct mtk_dp *mtk_dp, struct edid *edid)
 {
+	struct stopwatch sw;
+
+	stopwatch_init(&sw);
 	dptx_power_on();
 	dptx_init_variable(mtk_dp);
 	dptx_init_port(mtk_dp);
@@ -555,6 +568,8 @@ int mtk_edp_init(struct mtk_dp *mtk_dp, struct edid *edid)
 
 	dp_intf_config(edid);
 	dptx_video_config(mtk_dp);
+	printk(BIOS_INFO, "%s done after %lld msecs\n", __func__,
+	       stopwatch_duration_msecs(&sw));
 
 	return 0;
 }
diff --git a/src/soc/mediatek/common/dp/dptx_v1.c b/src/soc/mediatek/common/dp/dptx_v1.c
index bf95eff967..76a324a9bb 100644
--- a/src/soc/mediatek/common/dp/dptx_v1.c
+++ b/src/soc/mediatek/common/dp/dptx_v1.c
@@ -12,6 +12,7 @@
 #include <soc/dptx_reg.h>
 #include <soc/dp_intf.h>
 #include <string.h>
+#include <timer.h>
 
 static void dptx_training_checkswingpre(struct mtk_dp *mtk_dp,
 					u8 target_lane_count,
@@ -364,7 +365,9 @@ int dptx_set_trainingstart(struct mtk_dp *mtk_dp)
 	u8 buffer;
 	u8 limit;
 	u8 max_linkrate;
+	struct stopwatch sw;
 
+	stopwatch_init(&sw);
 	buffer = 0x1;
 	dptx_auxwrite_dpcd(mtk_dp, DP_AUX_NATIVE_WRITE,
 			   DPCD_00600, 0x1, &buffer);
@@ -447,6 +450,8 @@ int dptx_set_trainingstart(struct mtk_dp *mtk_dp)
 			else
 				return DPTX_TRANING_FAIL;
 		} else {
+			printk(BIOS_INFO, "%s done after %lld msecs\n", __func__,
+			       stopwatch_duration_msecs(&sw));
 			return DPTX_PASS;
 		}
 	} while (--limit > 0);
diff --git a/src/soc/mediatek/common/dp/dptx_v2.c b/src/soc/mediatek/common/dp/dptx_v2.c
index adea70d140..5b917a501a 100644
--- a/src/soc/mediatek/common/dp/dptx_v2.c
+++ b/src/soc/mediatek/common/dp/dptx_v2.c
@@ -11,6 +11,7 @@
 #include <soc/dptx.h>
 #include <soc/dptx_hal.h>
 #include <soc/dptx_reg.h>
+#include <timer.h>
 
 static void mtk_edp_pattern(struct mtk_dp *mtk_dp, u8 lane_count, u8 pattern)
 {
@@ -255,7 +256,9 @@ int dptx_set_trainingstart(struct mtk_dp *mtk_dp)
 	u8 train_limit;
 	u8 max_linkrate;
 	int ret;
+	struct stopwatch sw;
 
+	stopwatch_init(&sw);
 	buffer = 0x1;
 	dptx_auxwrite_dpcd(mtk_dp, DP_AUX_NATIVE_WRITE, DPCD_00600, 0x1, &buffer);
 
@@ -349,7 +352,8 @@ int dptx_set_trainingstart(struct mtk_dp *mtk_dp)
 	dptx_hal_setscramble(mtk_dp, true);
 	dptx_hal_set_ef_mode(mtk_dp, ENABLE_DPTX_EF_MODE);
 
-	printk(BIOS_INFO, "%s: done\n", __func__);
+	printk(BIOS_INFO, "%s done after %lld msecs\n", __func__,
+	       stopwatch_duration_msecs(&sw));
 
 	return DPTX_PASS;
 }

From df7bf9404d5805c84a1d37d00ad44df35cd5e92b Mon Sep 17 00:00:00 2001
From: Yidi Lin <yidilin@google.com>
Date: Mon, 11 Aug 2025 14:54:03 +0800
Subject: [PATCH 1783/3886] soc/mediatek/common: Remove 200 ms delay from eDP
 init path

According to MediaTek, this delay was added in the driver bring-up stage
to mitigate the display garbage issue. Now, the delay can be removed.

BUG=b:434574691
TEST=Check FW screen on Navi

Change-Id: I5408d95be7a4aaf8bb4bb639c319320514c4fd99
Signed-off-by: Yidi Lin <yidilin@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88744
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
---
 src/soc/mediatek/common/display.c | 1 -
 1 file changed, 1 deletion(-)

diff --git a/src/soc/mediatek/common/display.c b/src/soc/mediatek/common/display.c
index 417a764499..c805c6d664 100644
--- a/src/soc/mediatek/common/display.c
+++ b/src/soc/mediatek/common/display.c
@@ -90,7 +90,6 @@ int mtk_display_init(void)
 	process_panel_quirks(&mtk_edp, panel);
 
 	if (panel->disp_path == DISP_PATH_EDP) {
-		mdelay(200);
 		if (mtk_edp_init(&mtk_edp, &edid) < 0) {
 			printk(BIOS_ERR, "%s: Failed to initialize eDP\n", __func__);
 			return -1;

From 609eb4c5f1a33f740bfb895ad7c7fe35de0e99ba Mon Sep 17 00:00:00 2001
From: Sowmya Aralguppe <sowmya.aralguppe@intel.com>
Date: Tue, 5 Aug 2025 14:39:32 +0530
Subject: [PATCH 1784/3886] mb/google/ocelot/var/ocelot:  Remove unused I2C
 controllers

Set I2C2, I2C3, and I2C4 controllers to disabled in serial_io_i2c_mode
Remove configuration for I2C2, I2C3, and I2C4 from common_soc_config

Schematic version: schematic_1433518
Platform Mapping Document : Rev0p86

BUG=b: None
TEST= Build Ocelot and verify it compiles without any error.

Change-Id: Ibe26bde3ffbd4b188584369cdd686ffb116d6a7d
Signed-off-by: Sowmya Aralguppe <sowmya.aralguppe@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88650
Reviewed-by: Pranava Y N <pranavayn@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Avi Uday <aviuday@google.com>
---
 .../google/ocelot/variants/ocelot/overridetree.cb | 15 +++------------
 1 file changed, 3 insertions(+), 12 deletions(-)

diff --git a/src/mainboard/google/ocelot/variants/ocelot/overridetree.cb b/src/mainboard/google/ocelot/variants/ocelot/overridetree.cb
index d20e0297ea..2e0114badc 100644
--- a/src/mainboard/google/ocelot/variants/ocelot/overridetree.cb
+++ b/src/mainboard/google/ocelot/variants/ocelot/overridetree.cb
@@ -92,9 +92,9 @@ chip soc/intel/pantherlake
 	register "serial_io_i2c_mode" = "{
 		[PchSerialIoIndexI2C0]  = PchSerialIoPci,
 		[PchSerialIoIndexI2C1]  = PchSerialIoPci,
-		[PchSerialIoIndexI2C2]  = PchSerialIoPci,
-		[PchSerialIoIndexI2C3]  = PchSerialIoPci,
-		[PchSerialIoIndexI2C4]  = PchSerialIoPci,
+		[PchSerialIoIndexI2C2]  = PchSerialIoDisabled,
+		[PchSerialIoIndexI2C3]  = PchSerialIoDisabled,
+		[PchSerialIoIndexI2C4]  = PchSerialIoDisabled,
 		[PchSerialIoIndexI2C5]  = PchSerialIoPci,
 	}"
 
@@ -118,15 +118,6 @@ chip soc/intel/pantherlake
 			.speed = I2C_SPEED_FAST,
 			.early_init = 1,
 		},
-		.i2c[2] = {
-			.speed = I2C_SPEED_FAST,
-		},
-		.i2c[3] = {
-			.speed = I2C_SPEED_FAST,
-		},
-		.i2c[4] = {
-			.speed = I2C_SPEED_FAST,
-		},
 		.i2c[5] = {
 			.speed = I2C_SPEED_FAST,
 		},

From 510686add4d4874afd9abc3d1490ea876597768a Mon Sep 17 00:00:00 2001
From: Sowmya Aralguppe <sowmya.aralguppe@intel.com>
Date: Mon, 21 Jul 2025 19:26:22 +0530
Subject: [PATCH 1785/3886] soc/intel/pantherlake: Rearm crashlog using watcher

After crashlog data is extracted, CPU rearm command is issued to
prepare the crash logging mechanism for future events. Instead of
command and response polling of mailbox, watcher interface which is a
direct MMIO based, low latency control register is used for efficiency.
In PTL, a Crashlog watcher providing control the same way provided by
Crashlog Mailbox Interface used by (mainly) BIOS is used for all CPU
crashlog control requests from BIOS to PUNIT.

BUG=b: None
TEST= Manually trigger crash using command
iotools mmio_write32 (baraddress + watcher offset=0x10) 0x20000000
followed by warm boot, check rearm status - which is 25th bit of
*(bar_address)

Change-Id: I89dd23fad144c1c7122b5536f1ac848ea66ea6b1
Signed-off-by: Sowmya Aralguppe <sowmya.aralguppe@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88515
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
---
 src/soc/intel/pantherlake/crashlog.c | 22 +++-------------------
 1 file changed, 3 insertions(+), 19 deletions(-)

diff --git a/src/soc/intel/pantherlake/crashlog.c b/src/soc/intel/pantherlake/crashlog.c
index da2cbccb32..d02c369286 100644
--- a/src/soc/intel/pantherlake/crashlog.c
+++ b/src/soc/intel/pantherlake/crashlog.c
@@ -20,6 +20,7 @@
 #define CRASHLOG_CONSUMED_BIOS_MASK	BIT(27)
 #define CRASHLOG_SET_CLEAR_TRIGGER_MASK	BIT(30)
 #define CRASHLOG_SET_CONSUMED_MASK	BIT(18)
+#define CRASHLOG_REARM_TRIGGER_MASK	BIT(28)
 
 /* Global crashLog info */
 static bool m_pmc_crash_log_support;
@@ -385,13 +386,6 @@ int cl_get_total_data_size(void)
 	return m_pmc_crash_log_size + m_cpu_crash_log_size;
 }
 
-static uintptr_t get_control_status_interface(void)
-{
-	if (disc_tab_addr)
-		return (disc_tab_addr + CONTROL_INTERFACE_OFFSET * sizeof(u32));
-	return 0;
-}
-
 int cpu_cl_clear_data(void)
 {
 	/* Clear all crashlog data and CRASHLOG_SET_CONSUMED = 1 -> sets CONSUMED_BIOS bit */
@@ -417,18 +411,8 @@ static bool wait_and_check(u32 bit_mask)
 
 void cpu_cl_rearm(void)
 {
-	uintptr_t ctrl_sts_intfc_addr = get_control_status_interface();
-
-	if (!ctrl_sts_intfc_addr) {
-		printk(BIOS_ERR, "CPU crashlog control and status interface address not valid\n");
-		return;
-	}
-
-	/* Rearm the CPU crashlog. Crashlog does not get collected if rearming fails */
-	cl_punit_control_interface_t punit_ctrl_intfc;
-	memset(&punit_ctrl_intfc, 0, sizeof(cl_punit_control_interface_t));
-	punit_ctrl_intfc.fields.set_re_arm = 1;
-	write32p(ctrl_sts_intfc_addr, punit_ctrl_intfc.data);
+	setbits64p(cl_get_cpu_bar_addr() + CRASHLOG_WATCHER_CONTROL_OFFSET,
+			CRASHLOG_REARM_TRIGGER_MASK);
 
 	if (!wait_and_check(CRASHLOG_RE_ARM_STATUS_MASK))
 		printk(BIOS_ERR, "CPU crashlog re_arm not asserted\n");

From e38a216368d24c3e55febbda05f04429d2e76600 Mon Sep 17 00:00:00 2001
From: Sowmya Aralguppe <sowmya.aralguppe@intel.com>
Date: Mon, 21 Jul 2025 22:17:13 +0530
Subject: [PATCH 1786/3886] soc/intel/pantherlake: Rearm and clear only for
 valid crashlog in PMC

Rearm and clear functions are called only if a valid crashlog is
present and extracted. If there is no valid crashlog, rearming will
lead to incorrect notification and skipping of the next crashlog event

BUG=b: None
TEST= PMC discovery buffer - rearmed status bit (trig_armed_sts)
      MMIO read of Bit position 25 is rearmed status bit
	  MMIO read of desc_table_addr = (bar_address + offset)
	  desc_table_addr = 0x9c198000 +  0x1d00 = 0x9c199d00
	  :1 for cold boot and
	  :0 for warm boot after manual crash

Change-Id: I42da487abd383567d7945835b738557e2e3fa714
Signed-off-by: Sowmya Aralguppe <sowmya.aralguppe@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88519
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
---
 src/soc/intel/pantherlake/crashlog.c | 15 ++++++++++-----
 1 file changed, 10 insertions(+), 5 deletions(-)

diff --git a/src/soc/intel/pantherlake/crashlog.c b/src/soc/intel/pantherlake/crashlog.c
index d02c369286..471608f21a 100644
--- a/src/soc/intel/pantherlake/crashlog.c
+++ b/src/soc/intel/pantherlake/crashlog.c
@@ -161,11 +161,16 @@ void cl_get_pmc_sram_data(cl_node_t *head)
 	update_new_pmc_crashlog_size(&pmc_crashLog_size);
 
 pmc_send_re_arm_after_reset:
-	/* When bit 7 of discov cmd resp is set -> bit 2 of size field */
-	cl_pmc_re_arm_after_reset();
-
-	/* Clear the SSRAM region after copying the error log */
-	cl_pmc_clear();
+	/* Re-arm and clear only if crashlog is present and valid*/
+	if (!pmc_crashLog_size) {
+		printk(BIOS_DEBUG, "No valid crashlog data found in PMC SRAM\n");
+		return;
+	} else {
+		/* When bit 7 of discov cmd resp is set -> bit 2 of size field */
+		cl_pmc_re_arm_after_reset();
+		/* Clear the SSRAM region after copying the error log */
+		cl_pmc_clear();
+	}
 }
 
 bool pmc_cl_discovery(void)

From 8097809c8aa976d425b0d75459f1e9c06c39e73d Mon Sep 17 00:00:00 2001
From: Julius Werner <jwerner@chromium.org>
Date: Fri, 8 Aug 2025 19:34:48 -0700
Subject: [PATCH 1787/3886] libpayload: Fix strsep() edge cases

Our strsep() function is slightly incorrect in that it leaves the
`stringp` pointer pointing to the terminating NUL byte after parsing the
last token. The man page for official implementations says:

> In case no delimiter was found, the token is taken to be the entire
> string *stringp, and *stringp is made NULL.

This doesn't affect things in practice much because we also
(incorrectly) return NULL when called with `**stringp == '\0'`, meaning
the usual pattern of calling `strsep()` in a row without checking
results first still works when there are less tokens than expected,
since we terminate early from that case instead. But it does break the
edge cases where the caller wants to check if there were extra bytes
beyond the last token (`stringp == NULL`), and where we call `strsep()`
on a pointer pointing directly to a terminating NUL byte already
(supposed to return an empty string but our implementation actually
returns NULL). It doesn't look like these edge cases occur anywhere in
current libpayload or depthcharge code.

This patch fixes the issue and also adds a unit test to ensure it
remains correct in the future. (Also move the definition of the `errno`
variable from lib.c into string.c, because `perror()` in string.c is the
only function that actually needs that, and the crazy linker error you
get when only linking one but not the other into a test will waste you
half an hour to figure out.)

Change-Id: I610b5117710c110bcba4fac2a0bb6c13f4f8d046
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88729
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 payloads/libpayload/libc/lib.c               |  2 -
 payloads/libpayload/libc/string.c            | 13 +++++--
 payloads/libpayload/tests/libc/Makefile.mk   |  5 ++-
 payloads/libpayload/tests/libc/string-test.c | 39 ++++++++++++++++++++
 4 files changed, 52 insertions(+), 7 deletions(-)
 create mode 100644 payloads/libpayload/tests/libc/string-test.c

diff --git a/payloads/libpayload/libc/lib.c b/payloads/libpayload/libc/lib.c
index f1d85745ad..0475789c00 100644
--- a/payloads/libpayload/libc/lib.c
+++ b/payloads/libpayload/libc/lib.c
@@ -124,8 +124,6 @@ void __noreturn abort(void)
 	halt();
 }
 
-int errno;
-
 char *getenv(const char *name)
 {
 	return NULL;
diff --git a/payloads/libpayload/libc/string.c b/payloads/libpayload/libc/string.c
index a1b7d4d59d..d641431e7d 100644
--- a/payloads/libpayload/libc/string.c
+++ b/payloads/libpayload/libc/string.c
@@ -290,7 +290,7 @@ char *strsep(char **stringp, const char *delim)
 {
 	char *walk, *token;
 
-	if (!stringp || !*stringp || !**stringp)
+	if (!stringp || !*stringp)
 		return NULL;
 
 	token = walk = *stringp;
@@ -302,11 +302,12 @@ char *strsep(char **stringp, const char *delim)
 	if (*walk) {
 		/* NUL terminate */
 		*walk = '\0';
-		walk++;
+		*stringp = walk + 1;
+	} else {
+		/* Set to NULL after last token. */
+		*stringp = NULL;
 	}
 
-	*stringp = walk;
-
 	return token;
 }
 
@@ -547,6 +548,10 @@ char *strtok(char *str, const char *delim)
 	return strtok_r(str, delim, &strtok_ptr);
 }
 
+/* errno isn't actually used anywhere other than perror() below, and just here
+   for compatibility with libc-targeting code wanting to incidentally print it. */
+int errno;
+
 /**
  * Print error message and error number
  * @param s Error message to print
diff --git a/payloads/libpayload/tests/libc/Makefile.mk b/payloads/libpayload/tests/libc/Makefile.mk
index 5f92bdf0a8..8d88af9f30 100644
--- a/payloads/libpayload/tests/libc/Makefile.mk
+++ b/payloads/libpayload/tests/libc/Makefile.mk
@@ -1,3 +1,6 @@
-tests-y += fmap_locate_area-test
+tests-y += fmap_locate_area-test string-test
 
 fmap_locate_area-test-srcs += tests/libc/fmap_locate_area-test.c
+
+string-test-srcs += tests/libc/string-test.c
+string-test-srcs += libc/string.c
diff --git a/payloads/libpayload/tests/libc/string-test.c b/payloads/libpayload/tests/libc/string-test.c
new file mode 100644
index 0000000000..2fe7c6bace
--- /dev/null
+++ b/payloads/libpayload/tests/libc/string-test.c
@@ -0,0 +1,39 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <libpayload.h>
+#include <tests/test.h>
+
+static void test_strsep(void **state)
+{
+	/* Use `char x[] = ` instead of `char *x = ` to avoid writing to .rodata. */
+	char test1[] = "abc,def|ghi jklm,\no";
+	const char *delim = ", \n";
+
+	char *stringp = test1;
+	assert_string_equal(strsep(&stringp, delim), "abc");
+	assert_ptr_equal(stringp, test1 + 4);
+	assert_string_equal(strsep(&stringp, delim), "def|ghi");
+	assert_ptr_equal(stringp, test1 + 12);
+	assert_string_equal(strsep(&stringp, delim), "jklm");
+	assert_ptr_equal(stringp, test1 + 17);
+	assert_string_equal(strsep(&stringp, delim), "");
+	assert_ptr_equal(stringp, test1 + 18);
+	assert_string_equal(strsep(&stringp, delim), "o");
+	assert_null(stringp);
+	assert_null(strsep(&stringp, delim));
+	assert_null(stringp);
+
+	char test2[] = "";
+	stringp = test2;
+	assert_string_equal(strsep(&stringp, delim), "");
+	assert_null(strsep(&stringp, delim));
+}
+
+int main(void)
+{
+	const struct CMUnitTest tests[] = {
+		cmocka_unit_test(test_strsep),
+	};
+
+	return lp_run_group_tests(tests, NULL, NULL);
+}

From b65b98ace663b2cc6ba69e70b37c1e459175a6bb Mon Sep 17 00:00:00 2001
From: Nick Vaccaro <nvaccaro@google.com>
Date: Tue, 12 Aug 2025 12:42:32 -0700
Subject: [PATCH 1788/3886] mb/goog/ocelot/var/ocelot: switch to H58G56BK8BX068
 memory part

Switch the DRAM_ID 0 memory part from the H58G56BK7BX068 memory part
to H58G56BK8BX068 for ocelot.

BUG=b:437989448
TEST=`emerge-ocelot coreboot chromeos-bootimage', flash and boot
ocelot and verify it's able to train memory without error.

Change-Id: I979a75f770cc5bf82b7c5537e4c36651ecc21ea6
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88759
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/google/ocelot/variants/ocelot/memory/Makefile.mk  | 2 +-
 .../google/ocelot/variants/ocelot/memory/dram_id.generated.txt  | 2 +-
 .../google/ocelot/variants/ocelot/memory/mem_parts_used.txt     | 2 +-
 3 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/src/mainboard/google/ocelot/variants/ocelot/memory/Makefile.mk b/src/mainboard/google/ocelot/variants/ocelot/memory/Makefile.mk
index 23bc544fc6..2059568629 100644
--- a/src/mainboard/google/ocelot/variants/ocelot/memory/Makefile.mk
+++ b/src/mainboard/google/ocelot/variants/ocelot/memory/Makefile.mk
@@ -4,4 +4,4 @@
 # ./util/spd_tools/bin/part_id_gen PTL lp5 src/mainboard/google/ocelot/variants/ocelot/memory src/mainboard/google/ocelot/variants/ocelot/memory/mem_parts_used.txt
 
 SPD_SOURCES =
-SPD_SOURCES += spd/lp5/set-0/spd-7.hex      # ID = 0(0b0000)  Parts = H58G56BK7BX068
+SPD_SOURCES += spd/lp5/set-0/spd-11.hex      # ID = 0(0b0000)  Parts = H58G56BK8BX068
diff --git a/src/mainboard/google/ocelot/variants/ocelot/memory/dram_id.generated.txt b/src/mainboard/google/ocelot/variants/ocelot/memory/dram_id.generated.txt
index 8bdcd1a2f8..c7351b2c76 100644
--- a/src/mainboard/google/ocelot/variants/ocelot/memory/dram_id.generated.txt
+++ b/src/mainboard/google/ocelot/variants/ocelot/memory/dram_id.generated.txt
@@ -4,4 +4,4 @@
 # ./util/spd_tools/bin/part_id_gen PTL lp5 src/mainboard/google/ocelot/variants/ocelot/memory src/mainboard/google/ocelot/variants/ocelot/memory/mem_parts_used.txt
 
 DRAM Part Name                 ID to assign
-H58G56BK7BX068                 0 (0000)
+H58G56BK8BX068                 0 (0000)
diff --git a/src/mainboard/google/ocelot/variants/ocelot/memory/mem_parts_used.txt b/src/mainboard/google/ocelot/variants/ocelot/memory/mem_parts_used.txt
index 17ee7efc60..ae8eff2d96 100644
--- a/src/mainboard/google/ocelot/variants/ocelot/memory/mem_parts_used.txt
+++ b/src/mainboard/google/ocelot/variants/ocelot/memory/mem_parts_used.txt
@@ -9,4 +9,4 @@
 # See util/spd_tools/README.md for more details and instructions.
 
 # Part Name
-H58G56BK7BX068
+H58G56BK8BX068

From 17a7c351b8517ced7865aed060753285cc714284 Mon Sep 17 00:00:00 2001
From: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Date: Tue, 5 Aug 2025 08:30:51 +0900
Subject: [PATCH 1789/3886] mb/google/brya/var/kaladin/hda_verb.c: Correct
 number of entries to 21

Counting the entries on the verb table, there are 10 "AZALIA_" macros
and 44 32-bit values. Therefore, the correct amount of entries should be
10 + (44 / 4) = 21.

Change-Id: Ic858d9076d12755014caa28e428d57dde0ef375d
Signed-off-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88645
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/google/brya/variants/kaladin/hda_verb.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/mainboard/google/brya/variants/kaladin/hda_verb.c b/src/mainboard/google/brya/variants/kaladin/hda_verb.c
index d2b9f33f7a..710153a42f 100644
--- a/src/mainboard/google/brya/variants/kaladin/hda_verb.c
+++ b/src/mainboard/google/brya/variants/kaladin/hda_verb.c
@@ -6,7 +6,7 @@ const u32 cim_verb_data[] = {
 	/* coreboot specific header */
 	0x10ec0236,	// Codec Vendor / Device ID: Realtek ALC236
 	0x103C8C60,	// Subsystem ID
-	0x00000017,	// Number of jacks (NID entries)
+	0x00000015,	// Number of jacks (NID entries)
 
 	AZALIA_RESET(0x1),
 	/* NID 0x01, HDA Codec Subsystem ID Verb table */

From 4a82f37525d0a8ee95fa7d9390f90ff140509ac3 Mon Sep 17 00:00:00 2001
From: Shon Wang <shon.wang@quanta.corp-partner.google.com>
Date: Wed, 13 Aug 2025 18:38:55 +0800
Subject: [PATCH 1790/3886] mb/google/nissa/var/quandiso: Generate new RAM ID

Generate RAM ID for
IC SDRAM(315P) MT62F1G32D2DS-023 WT:C
IC SDRAM(315P) H58G56CK8BX146
IC SDRAM(315P) K3KL8L80EM-MGCU(FBGA)

DRAM Part Name                 ID to assign
MT62F1G32D2DS-023 WT:C         7 (0111)
H58G56CK8BX146                 7 (0111)
K3KL8L80EM-MGCU                7 (0111)

BUG=b:438402880
BRANCH=firmware-nissa-15217.B
TEST=emerge-nissa coreboot

Change-Id: I7ff2f2d43784a6034c1262913dbeaffc1dc3036f
Signed-off-by: Shon Wang <shon.wang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88766
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
---
 .../google/brya/variants/quandiso/memory/Makefile.mk       | 1 +
 .../brya/variants/quandiso/memory/dram_id.generated.txt    | 7 ++++---
 .../brya/variants/quandiso/memory/mem_parts_used.txt       | 3 +++
 3 files changed, 8 insertions(+), 3 deletions(-)

diff --git a/src/mainboard/google/brya/variants/quandiso/memory/Makefile.mk b/src/mainboard/google/brya/variants/quandiso/memory/Makefile.mk
index 0aa403852a..7dbd0d33f3 100644
--- a/src/mainboard/google/brya/variants/quandiso/memory/Makefile.mk
+++ b/src/mainboard/google/brya/variants/quandiso/memory/Makefile.mk
@@ -11,3 +11,4 @@ SPD_SOURCES += spd/lp5/set-0/spd-7.hex      # ID = 3(0b0011)  Parts = H58G56BK7B
 SPD_SOURCES += spd/lp5/set-0/spd-8.hex      # ID = 4(0b0100)  Parts = H58G66BK7BX067, MT62F2G32D4DS-026 WT:B, K3KL9L90CM-MGCT
 SPD_SOURCES += spd/lp5/set-0/spd-6.hex      # ID = 5(0b0101)  Parts = H58G66AK6BX070
 SPD_SOURCES += spd/lp5/set-0/spd-9.hex      # ID = 6(0b0110)  Parts = K3KL6L60GM-MGCT
+SPD_SOURCES += spd/lp5/set-0/spd-11.hex      # ID = 7(0b0111)  Parts = MT62F1G32D2DS-023 WT:C, H58G56CK8BX146, K3KL8L80EM-MGCU
diff --git a/src/mainboard/google/brya/variants/quandiso/memory/dram_id.generated.txt b/src/mainboard/google/brya/variants/quandiso/memory/dram_id.generated.txt
index 576ef70d35..aebf863aac 100644
--- a/src/mainboard/google/brya/variants/quandiso/memory/dram_id.generated.txt
+++ b/src/mainboard/google/brya/variants/quandiso/memory/dram_id.generated.txt
@@ -1,9 +1,7 @@
 # SPDX-License-Identifier: GPL-2.0-or-later
 # This is an auto-generated file. Do not edit!!
 # Generated by:
-# ./util/spd_tools/bin/part_id_gen ADL lp5
-src/mainboard/google/brya/variants/quandiso/memory
-src/mainboard/google/brya/variants/quandiso/memory/mem_parts_used.txt
+# ./util/spd_tools/bin/part_id_gen ADL lp5 src/mainboard/google/brya/variants/quandiso/memory src/mainboard/google/brya/variants/quandiso/memory/mem_parts_used.txt
 
 DRAM Part Name                 ID to assign
 MT62F512M32D2DR-031 WT:B       0 (0000)
@@ -19,3 +17,6 @@ MT62F2G32D4DS-026 WT:B         4 (0100)
 K3KL9L90CM-MGCT                4 (0100)
 H58G66AK6BX070                 5 (0101)
 K3KL6L60GM-MGCT                6 (0110)
+MT62F1G32D2DS-023 WT:C         7 (0111)
+H58G56CK8BX146                 7 (0111)
+K3KL8L80EM-MGCU                7 (0111)
diff --git a/src/mainboard/google/brya/variants/quandiso/memory/mem_parts_used.txt b/src/mainboard/google/brya/variants/quandiso/memory/mem_parts_used.txt
index bf50ea472b..79ac769995 100644
--- a/src/mainboard/google/brya/variants/quandiso/memory/mem_parts_used.txt
+++ b/src/mainboard/google/brya/variants/quandiso/memory/mem_parts_used.txt
@@ -22,3 +22,6 @@ MT62F2G32D4DS-026 WT:B
 K3KL9L90CM-MGCT
 H58G66AK6BX070
 K3KL6L60GM-MGCT
+MT62F1G32D2DS-023 WT:C
+H58G56CK8BX146
+K3KL8L80EM-MGCU

From 6e9c0a26e397b434bd4e2e31eb0486b3928d491d Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Wed, 13 Aug 2025 12:34:29 -0500
Subject: [PATCH 1791/3886] device/device_util: Fix format specifier for
 DEVICE_PATH_GICC_V3

dev->path.gicc_v3.mpidr is an unsigned long long, so the format
specifier should be %llx, not %x. Keep the minimum 2 digit output.

BUG=CID 1611971

Change-Id: I126b0281efcba2c3e41cf6da4d006b8d2eb7215b
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88769
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
---
 src/device/device_util.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/device/device_util.c b/src/device/device_util.c
index 864e64c4bb..12fcd18652 100644
--- a/src/device/device_util.c
+++ b/src/device/device_util.c
@@ -232,7 +232,7 @@ const char *dev_path(const struct device *dev)
 			snprintf(buffer, sizeof(buffer), "MDIO: %02x", dev->path.mdio.addr);
 			break;
 		case DEVICE_PATH_GICC_V3:
-			snprintf(buffer, sizeof(buffer), "GICV3: %02x", dev->path.gicc_v3.mpidr);
+			snprintf(buffer, sizeof(buffer), "GICV3: %02llx", dev->path.gicc_v3.mpidr);
 			break;
 		default:
 			printk(BIOS_ERR, "Unknown device path type: %d\n",

From 8df079c609ac60b3e2c248032864e0004efe7990 Mon Sep 17 00:00:00 2001
From: Alicja Michalska <alicja.michalska@9elements.com>
Date: Wed, 2 Jul 2025 20:19:56 +0200
Subject: [PATCH 1792/3886] mb/lattepanda/mu: Enable CRB TPM (Intel fTPM)

While helping with board bringup, I noticed that CRB is enabled in mFIT
but it was missing in board code.

Change-Id: I8f34cac2508ef15f5b6f6542a912fb12af3c2dbf
Signed-off-by: Alicja Michalska <alicja.michalska@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88275
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: KunYi Chen <kunyi.chen@gmail.com>
---
 src/mainboard/lattepanda/mu/Kconfig       | 2 ++
 src/mainboard/lattepanda/mu/devicetree.cb | 3 +++
 2 files changed, 5 insertions(+)

diff --git a/src/mainboard/lattepanda/mu/Kconfig b/src/mainboard/lattepanda/mu/Kconfig
index aa98fcf2cf..0d8560504a 100644
--- a/src/mainboard/lattepanda/mu/Kconfig
+++ b/src/mainboard/lattepanda/mu/Kconfig
@@ -5,6 +5,7 @@ if BOARD_LATTEPANDA_MU
 config BOARD_SPECIFIC_OPTIONS
 	def_bool y
 	select BOARD_ROMSIZE_KB_16384
+	select CRB_TPM
 	select DRIVERS_INTEL_PMC
 	select DRIVERS_SPI_ACPI
 	select DRIVERS_UART_8250IO
@@ -13,6 +14,7 @@ config BOARD_SPECIFIC_OPTIONS
 	select HAVE_ACPI_RESUME
 	select HAVE_ACPI_TABLES
 	select HAVE_SPD_IN_CBFS
+	select HAVE_INTEL_PTT
 	select INTEL_GMA_HAVE_VBT
 	select PMC_IPC_ACPI_INTERFACE
 	select REALTEK_8168_RESET
diff --git a/src/mainboard/lattepanda/mu/devicetree.cb b/src/mainboard/lattepanda/mu/devicetree.cb
index 563d8fbd2e..1db9519084 100644
--- a/src/mainboard/lattepanda/mu/devicetree.cb
+++ b/src/mainboard/lattepanda/mu/devicetree.cb
@@ -150,5 +150,8 @@ chip soc/intel/alderlake
 				device pnp 2e.a off end # CIR
 			end
 		end
+		chip drivers/crb
+			device mmio 0xfed40000 on end
+		end
 	end
 end

From e5ff7cb186c6c4dd80bcec1816926a51c76eecbb Mon Sep 17 00:00:00 2001
From: Sowmya Aralguppe <sowmya.aralguppe@intel.com>
Date: Tue, 5 Aug 2025 12:09:04 +0530
Subject: [PATCH 1793/3886] mb/google/ocelot/var/ocelot: Update DDI port
 Configuration

This patch enables DDC only for HDMI (Port B) to support EDID/DDC
communication so that the system can communicate with the monitor and
set up the display properly.

Schematic version: schematic_1433518
Platform Mapping Document : Rev0p86

BUG=b: None
TEST= Build Ocelot and verify it compiles without any error.

Change-Id: I6bf7c249dd154ab12a4b2539ecb7872392c132fa
Signed-off-by: Sowmya Aralguppe <sowmya.aralguppe@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88648
Reviewed-by: Pranava Y N <pranavayn@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/google/ocelot/variants/ocelot/overridetree.cb | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/src/mainboard/google/ocelot/variants/ocelot/overridetree.cb b/src/mainboard/google/ocelot/variants/ocelot/overridetree.cb
index 2e0114badc..33bf88704e 100644
--- a/src/mainboard/google/ocelot/variants/ocelot/overridetree.cb
+++ b/src/mainboard/google/ocelot/variants/ocelot/overridetree.cb
@@ -80,13 +80,12 @@ chip soc/intel/pantherlake
 	register "tcss_cap_policy[0]" = "TCSS_TYPE_C_PORT_FULL_FUN"
 	register "tcss_cap_policy[1]" = "TCSS_TYPE_C_PORT_FULL_FUN"
 
-
 	# Enable EDP in PortA & HDMI in Port B
 	register "ddi_port_A_config" = "1"
 	register "ddi_port_B_config" = "1"
 	register "ddi_ports_config" = "{
 		[DDI_PORT_A] = DDI_ENABLE_HPD,
-		[DDI_PORT_B] = DDI_ENABLE_HPD,
+		[DDI_PORT_B] = DDI_ENABLE_HPD | DDI_ENABLE_DDC,
 	}"
 
 	register "serial_io_i2c_mode" = "{

From 25e0a4642ceb1d637d0b5bc2bbadca4aa532a02e Mon Sep 17 00:00:00 2001
From: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Date: Fri, 8 Aug 2025 11:52:18 +0800
Subject: [PATCH 1794/3886] mb/google/brox/var/caboc: Update LAN LED behavior

Value is from vendor, change to 0x0807 the LED behavior meets spec:
LED0: Green when connected.
LED2: Blink amber when active.

BUG:b=437217680
TEST=emerge-brox coreboot
     Check firmware log output
     [DEBUG]  r8168: Customized LED 0x807
     [DEBUG]  r8168: read back LED setting as 0x807
     Verified the LED behavior of LAN actions meets spec.

Change-Id: I37a3c62b38cd7a3a23b4f8a9c3cb2432393c7a27
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88720
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
---
 src/mainboard/google/brox/variants/caboc/overridetree.cb | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/mainboard/google/brox/variants/caboc/overridetree.cb b/src/mainboard/google/brox/variants/caboc/overridetree.cb
index c70aeca5d1..45fbb167a0 100644
--- a/src/mainboard/google/brox/variants/caboc/overridetree.cb
+++ b/src/mainboard/google/brox/variants/caboc/overridetree.cb
@@ -307,7 +307,7 @@ chip soc/intel/alderlake
 				.flags = PCIE_RP_LTR | PCIE_RP_AER,
 			}"
 			chip drivers/net
-				register "customized_leds" = "0x05af"
+				register "customized_leds" = "0x0807"
 				register "device_index" = "0"
 				register "enable_aspm_l1_2" = "1"
 				register "add_acpi_dma_property" = "true"

From 73de3f95acc1e121b5ed7760a2ef030fd0c02522 Mon Sep 17 00:00:00 2001
From: Subrata Banik <subratabanik@google.com>
Date: Thu, 14 Aug 2025 15:44:14 +0530
Subject: [PATCH 1795/3886] mb/google/bluey: Support hardware watchdog logging

This patch adds support for hardware watchdog event logging which is
useful while debugging crashes or abnormal shutdown.

TEST=Able to build and boot google/bluey.

Change-Id: Iaa60e4eb564a1f517b979c2007707746f3453092
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88775
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/google/bluey/romstage.c | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/src/mainboard/google/bluey/romstage.c b/src/mainboard/google/bluey/romstage.c
index 4487b76cf9..b76dfba1f2 100644
--- a/src/mainboard/google/bluey/romstage.c
+++ b/src/mainboard/google/bluey/romstage.c
@@ -6,9 +6,13 @@
 #include <soc/aop_common.h>
 #include <soc/qclib_common.h>
 #include <soc/shrm.h>
+#include <soc/watchdog.h>
 
 void platform_romstage_main(void)
 {
+	/* Watchdog must be checked first to avoid erasing watchdog info later. */
+	check_wdog();
+
 	shrm_fw_load_reset();
 
 	/* QCLib: DDR init & train */

From 11c8d423d12ee56a2e59dc7b32c153e9d3e31f9f Mon Sep 17 00:00:00 2001
From: Subrata Banik <subratabanik@google.com>
Date: Wed, 13 Aug 2025 12:19:54 +0530
Subject: [PATCH 1796/3886] soc/qc/common: Remove ddr_base from
 qc_mmu_dram_config_post_dram_init

This commit refactors the qc_mmu_dram_config_post_dram_init function
to remove the ddr_base parameter. The function can now retrieve the
base address of the DRAM from the ddr_region global variable, which
is already available.

TEST=Able to build and boot google/quenbi.

Change-Id: I97159dee6a035ed3e38cbfca1e44b8e671d15fc1
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88765
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
---
 src/soc/qualcomm/common/include/soc/mmu_common.h | 2 +-
 src/soc/qualcomm/common/mmu.c                    | 8 ++++----
 src/soc/qualcomm/common/qclib.c                  | 3 +--
 3 files changed, 6 insertions(+), 7 deletions(-)

diff --git a/src/soc/qualcomm/common/include/soc/mmu_common.h b/src/soc/qualcomm/common/include/soc/mmu_common.h
index b6c8aabf4f..99a74116e0 100644
--- a/src/soc/qualcomm/common/include/soc/mmu_common.h
+++ b/src/soc/qualcomm/common/include/soc/mmu_common.h
@@ -13,7 +13,7 @@
 static struct region * const ddr_region = (struct region *)_ddr_information;
 
 void soc_mmu_dram_config_post_dram_init(void);
-void qc_mmu_dram_config_post_dram_init(void *ddr_base, size_t ddr_size);
+void qc_mmu_dram_config_post_dram_init(size_t ddr_size);
 bool soc_modem_carve_out(void **start, void **end);
 
 #endif  /* _SOC_QUALCOMM_MMU_COMMON_H_ */
diff --git a/src/soc/qualcomm/common/mmu.c b/src/soc/qualcomm/common/mmu.c
index 0f12555a7f..f87cebb47b 100644
--- a/src/soc/qualcomm/common/mmu.c
+++ b/src/soc/qualcomm/common/mmu.c
@@ -7,16 +7,16 @@
 
 __weak bool soc_modem_carve_out(void **start, void **end) { return false; }
 
-void qc_mmu_dram_config_post_dram_init(void *ddr_base, size_t ddr_size)
+void qc_mmu_dram_config_post_dram_init(size_t ddr_size)
 {
 	void *start = NULL;
 	void *end = NULL;
 
 	if (!soc_modem_carve_out(&start, &end)) {
-		mmu_config_range((void *)ddr_base, ddr_size, CACHED_RAM);
+		mmu_config_range((void *)_dram, ddr_size, CACHED_RAM);
 	} else {
-		mmu_config_range(ddr_base, start - ddr_base, CACHED_RAM);
-		mmu_config_range(end, ddr_base + ddr_size - end, CACHED_RAM);
+		mmu_config_range((void *)_dram, start - (void *)_dram, CACHED_RAM);
+		mmu_config_range(end, (void *)_dram + ddr_size - end, CACHED_RAM);
 	}
 
 	mmu_config_range((void *)_aop_code_ram, REGION_SIZE(aop_code_ram),
diff --git a/src/soc/qualcomm/common/qclib.c b/src/soc/qualcomm/common/qclib.c
index 8d73f04d34..3470741f7c 100644
--- a/src/soc/qualcomm/common/qclib.c
+++ b/src/soc/qualcomm/common/qclib.c
@@ -117,8 +117,7 @@ static void write_ddr_information(struct qclib_cb_if_table_entry *te)
 	*ddr_region = region_create(te->blob_address, ddr_size * MiB);
 
 	/* Use DDR info to configure MMU */
-	qc_mmu_dram_config_post_dram_init(
-		(void *)(uintptr_t)region_offset(ddr_region), region_sz(ddr_region));
+	qc_mmu_dram_config_post_dram_init(region_sz(ddr_region));
 }
 
 static void write_qclib_log_to_cbmemc(struct qclib_cb_if_table_entry *te)

From b4347f11d908e5ec9c8f810047a0acdf7b201f49 Mon Sep 17 00:00:00 2001
From: Subrata Banik <subratabanik@google.com>
Date: Wed, 13 Aug 2025 09:19:10 +0530
Subject: [PATCH 1797/3886] include: Make DRAM an explicit region

This patch makes DRAM an explicit region by introducing
DECLARE_OPTIONAL_REGION(dram) and DRAM_END().

Note: many SoC platforms determine DRAM size and layout dynamically
during boot, making a static compile-time value is not feasible always.
Attempting to use REGION_SIZE(dram) in this scenario would result in a
missing symbol `_dram_size` error.

By making dram an optional region, we allow its size and address to be
defined only when available, preventing build failures on platforms
that configure DRAM dynamically.

The old extern u8 _dram[] is removed, as it's now covered by the new
region definition.

This is a preparatory step for future changes that will make use of
the new DRAM_END() macro.

This symbol is necessary for systems that require
the DRAM size to be known and accessible from the linker script or
other parts of the build system.

Additionally, a new macro DRAM_END(addr) is defined in memlayout.h.
This macro provides a consistent way to mark the end of the DRAM
region, similar to how REGION_END and other start/end macros are used
throughout the codebase.

TEST=Able to build and boot google/quenbi.

Change-Id: Ib98ec4b991eed56385c83be6a9ca39ff1380ff1b
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88751
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
---
 src/include/memlayout.h | 2 ++
 src/include/symbols.h   | 3 +--
 2 files changed, 3 insertions(+), 2 deletions(-)

diff --git a/src/include/memlayout.h b/src/include/memlayout.h
index 6280b200eb..07addbbcde 100644
--- a/src/include/memlayout.h
+++ b/src/include/memlayout.h
@@ -60,6 +60,8 @@
 #define SRAM_END(addr) REGION_END(sram, addr)
 
 #define DRAM_START(addr) REGION_START(dram, addr)
+/* This should rarely be used because DRAM-size is usually not compile-time constant. */
+#define DRAM_END(addr) REGION_END(dram, addr)
 
 #define TIMESTAMP(addr, size) \
 	REGION(timestamp, addr, size, 8) \
diff --git a/src/include/symbols.h b/src/include/symbols.h
index 36e4c109cf..48ff832afd 100644
--- a/src/include/symbols.h
+++ b/src/include/symbols.h
@@ -5,8 +5,6 @@
 
 #include <types.h>
 
-extern u8 _dram[];
-
 #define REGION_SIZE(name) ((size_t)_##name##_size)
 
 #define DECLARE_REGION(name)	\
@@ -28,6 +26,7 @@ extern u8 _dram[];
 	__maybe_unused __weak extern u8 _##name##_size[];
 
 DECLARE_REGION(sram)
+DECLARE_OPTIONAL_REGION(dram)
 DECLARE_OPTIONAL_REGION(timestamp)
 DECLARE_REGION(preram_cbmem_console)
 DECLARE_REGION(cbmem_init_hooks)

From 276432faf710efefa6eaef553650b2dda62f8f07 Mon Sep 17 00:00:00 2001
From: Subrata Banik <subratabanik@google.com>
Date: Tue, 12 Aug 2025 22:02:41 +0530
Subject: [PATCH 1798/3886] soc/qualcomm/common: Add MMU configuration for
 fragmented DRAM regions

Stating with Qualcomm X1P42100 SoC generation, the DRAM memory map is
not expected to be contiguous (unlike previous generations) therefore,
the memory map could be something like this.

1. Assume hardware design has 4GB of DRAM then the memory map would
look like:
  - DDR_SPACE (2 GB) :  0x80000000 - 0x100000000
  - DDR_SPACE_1 (2 GB) : 0x880000000 - 0x900000000

2. Assume hardware design has 16GB of DRAM then the memory map would
look like:
  - DDR_SPACE (2 GB) :  0x80000000 - 0x100000000
  - DDR_SPACE_1 (14 GB) : 0x880000000 - 0x400000000

3. Assume hardware design has 64GB of DRAM then the memory map would
look like:
  - DDR_SPACE (2 GB) :  0x80000000 - 0x100000000
  - DDR_SPACE_1 (30 GB) : 0x880000000 - 0x1000000000
  - DDR_SPACE_2 (32 GB) : 0x8800000000 - 0x9000000000

This commit introduces logic to handle systems with fragmented DRAM
configurations. Previously, the Memory Management Unit (MMU) was
configured assuming a single, contiguous block of DRAM.

This change extends the MMU setup to properly configure multiple,
non-contiguous DRAM regions.

The changes include:

- Declaring dram_space_1 and dram_space_2 as optional regions, allowing
the dynamic allocation for these DRAM ranges based on DRAM capacity of
the platform.

- Introduce `qc_get_soc_dram_space_config` function that takes care of
DRAM based resource splitting as per `_dram`, `_dram_space_1` and
`_dram_space_2` region limit.

- Modifying qc_mmu_dram_config_post_dram_init() to check for these
optional regions and configure them individually. This ensures all
available DRAM is correctly mapped and accessible to the system.

This approach improves flexibility and allows coreboot to support a
wider range of Qualcomm platforms with different memory layouts.

TEST=Able to boot google/quenbi to OS.

Change-Id: If3788f4c77535f9a5e47ad2034ab9a8e0fe85b51
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88752
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 .../qualcomm/common/include/soc/mmu_common.h  |  1 +
 .../common/include/soc/symbols_common.h       |  8 +++
 src/soc/qualcomm/common/mmu.c                 | 56 ++++++++++++++++++-
 3 files changed, 62 insertions(+), 3 deletions(-)

diff --git a/src/soc/qualcomm/common/include/soc/mmu_common.h b/src/soc/qualcomm/common/include/soc/mmu_common.h
index 99a74116e0..1954c5db53 100644
--- a/src/soc/qualcomm/common/include/soc/mmu_common.h
+++ b/src/soc/qualcomm/common/include/soc/mmu_common.h
@@ -12,6 +12,7 @@
 
 static struct region * const ddr_region = (struct region *)_ddr_information;
 
+struct region *qc_get_soc_dram_space_config(size_t ddr_size, int *count);
 void soc_mmu_dram_config_post_dram_init(void);
 void qc_mmu_dram_config_post_dram_init(size_t ddr_size);
 bool soc_modem_carve_out(void **start, void **end);
diff --git a/src/soc/qualcomm/common/include/soc/symbols_common.h b/src/soc/qualcomm/common/include/soc/symbols_common.h
index 9d39db255e..caa1e7d174 100644
--- a/src/soc/qualcomm/common/include/soc/symbols_common.h
+++ b/src/soc/qualcomm/common/include/soc/symbols_common.h
@@ -32,4 +32,12 @@ DECLARE_REGION(dram_modem)
 DECLARE_REGION(dram_tz)
 DECLARE_REGION(dram_tz_rem)
 
+/*
+ * DDR_SPACE (2 GB) aka `_dram`:  0x80000000 - 0x100000000
+ * DDR_SPACE_1 (30 GB) aka `_dram_space_1`: 0x880000000 - 0x1000000000
+ * DDR_SPACE_2 (480 GB) aka `dram_space_2`: 0x8800000000 - 0x10000000000
+ */
+DECLARE_OPTIONAL_REGION(dram_space_1)
+DECLARE_OPTIONAL_REGION(dram_space_2)
+
 #endif // _SOC_QUALCOMM_SYMBOLS_COMMON_H_
diff --git a/src/soc/qualcomm/common/mmu.c b/src/soc/qualcomm/common/mmu.c
index f87cebb47b..ff8d5dc98e 100644
--- a/src/soc/qualcomm/common/mmu.c
+++ b/src/soc/qualcomm/common/mmu.c
@@ -1,22 +1,72 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
 #include <arch/mmu.h>
+#include <console/console.h>
 #include <soc/mmu.h>
 #include <soc/mmu_common.h>
 #include <soc/symbols_common.h>
 
+/* DRAM region: DDR_SPACE, DDR_SPACE_1 and DDR_SPACE_2 */
+#define MAX_DRAM_SPACE_INDEX 3
+
 __weak bool soc_modem_carve_out(void **start, void **end) { return false; }
 
+struct region *qc_get_soc_dram_space_config(size_t ddr_size, int *count)
+{
+	static struct region config[MAX_DRAM_SPACE_INDEX];
+	static int populated_count = 0;
+	int i;
+
+	if (!populated_count) {
+		void *region_start[MAX_DRAM_SPACE_INDEX] = {
+				_dram,
+				_dram_space_1,
+				_dram_space_2
+		};
+		size_t size[MAX_DRAM_SPACE_INDEX] = {
+				REGION_SIZE(dram),
+				REGION_SIZE(dram_space_1),
+				REGION_SIZE(dram_space_2)
+		};
+
+		/* Handle the case where DDR space is contiguous */
+		if (!_edram)
+			size[0] = ddr_size;
+
+		for (i = 0; i < MAX_DRAM_SPACE_INDEX && ddr_size > 0; i++) {
+			config[i].offset = (size_t)region_start[i];
+			size_t to_map = MIN(ddr_size, size[i]);
+			config[i].size = to_map;
+			ddr_size -= to_map;
+		}
+
+		populated_count = i;
+
+		if (ddr_size)
+			printk(BIOS_CRIT, "Too much DRAM for available windows (%zu bytes left over)!\n",
+				    ddr_size);
+	}
+
+	*count = populated_count;
+
+	return config;
+}
+
 void qc_mmu_dram_config_post_dram_init(size_t ddr_size)
 {
 	void *start = NULL;
 	void *end = NULL;
 
-	if (!soc_modem_carve_out(&start, &end)) {
-		mmu_config_range((void *)_dram, ddr_size, CACHED_RAM);
-	} else {
+	if (soc_modem_carve_out(&start, &end)) {
+		if (_dram_space_1)
+			die("Using carve out together with DRAM windows not supported");
 		mmu_config_range((void *)_dram, start - (void *)_dram, CACHED_RAM);
 		mmu_config_range(end, (void *)_dram + ddr_size - end, CACHED_RAM);
+	} else {
+		int count;
+		struct region *config = qc_get_soc_dram_space_config(ddr_size, &count);
+		for (int i = 0; i < count; i++)
+			mmu_config_range((void *)config[i].offset, config[i].size, CACHED_RAM);
 	}
 
 	mmu_config_range((void *)_aop_code_ram, REGION_SIZE(aop_code_ram),

From 1b760645b932d217d99224b5b7854a5c8ca33e4b Mon Sep 17 00:00:00 2001
From: Subrata Banik <subratabanik@google.com>
Date: Fri, 15 Aug 2025 00:51:57 +0530
Subject: [PATCH 1799/3886] soc/qc/x1p42100: Dynamically configure DRAM
 resources in ramstage

This commit updates the x1p42100 platform to support a dynamic memory
layout for DRAM. This is a crucial step toward supporting different
board variants with varying memory capacities.

The changes involve:

- ramstage build: The mmu.c source file is now included in the ramstage
build, providing the necessary functions to configure the Memory
Management Unit (MMU) for fragmented memory regions.

- Linker Script (memlayout.ld): The dram_space_1 and dram_space_2
regions are statically defined with their maximum possible sizes.

- SoC Initialization (soc.c): The soc_read_resources function is
refactored to use a new helper function, qc_get_soc_dram_space_config,
to retrieve a list of available DRAM regions. It then iterates through
this list to dynamically register each memory region with ram_range.
This replaces the previous static ram_range call with a more flexible
approach that can handle fragmented memory maps. Reserved regions are
also updated to use a dynamic index.

This refactoring allows the system to correctly handle memory maps for
devices with more than 2GB of DRAM, which was a limitation of the
previous static configuration.

TEST=Able to build and boot google/quenbi w/ 16GB of DRAM (using
DDR_SPACE and DDR_SPACE_1 regions).

Change-Id: If94644110272713f77db5a0dd6d23ec0798a15f0
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88753
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/soc/qualcomm/x1p42100/Makefile.mk  |  1 +
 src/soc/qualcomm/x1p42100/memlayout.ld | 19 +++++++++++++++++++
 src/soc/qualcomm/x1p42100/soc.c        | 20 ++++++++++++++------
 3 files changed, 34 insertions(+), 6 deletions(-)

diff --git a/src/soc/qualcomm/x1p42100/Makefile.mk b/src/soc/qualcomm/x1p42100/Makefile.mk
index 62930c9c33..d96dd8d760 100644
--- a/src/soc/qualcomm/x1p42100/Makefile.mk
+++ b/src/soc/qualcomm/x1p42100/Makefile.mk
@@ -40,6 +40,7 @@ romstage-$(CONFIG_DRIVERS_UART) += ../common/qupv3_uart.c
 ################################################################################
 ramstage-y += soc.c
 ramstage-y += cbmem.c
+ramstage-y += ../common/mmu.c
 ramstage-$(CONFIG_DRIVERS_UART) += ../common/qupv3_uart.c
 ramstage-$(CONFIG_PCI) += ../common/pcie_common.c
 ramstage-$(CONFIG_PCI) += pcie.c
diff --git a/src/soc/qualcomm/x1p42100/memlayout.ld b/src/soc/qualcomm/x1p42100/memlayout.ld
index 27f4be7e1a..ea21c27331 100644
--- a/src/soc/qualcomm/x1p42100/memlayout.ld
+++ b/src/soc/qualcomm/x1p42100/memlayout.ld
@@ -65,4 +65,23 @@ SECTIONS
 	REGION(dram_tz, 0xD8000000, 0xD6000, 0x1000)
 	BL31(0xD80D6000, 1M)
 	REGION(dram_tz_rem, 0xD81D6000, 0x72EA000, 0x1000)
+	DRAM_END(0x100000000)
+
+	/*
+	 * Define the address range limits for fragmented DRAM regions.
+	 *
+	 * These regions, `dram_space_1` and `dram_space_2`, are used to map physical
+	 * memory beyond the initial `_dram` region. The MMU configuration logic in
+	 * `mmu.c` uses `REGION_SIZE()` to dynamically size these ranges based on the
+	 * total system DRAM capacity, which is determined by the QCLib.
+	 *
+	 * Example for a 16GB DRAM system:
+	 * - `_dram` (2GB):          0x80000000 - 0x100000000
+	 * - `_dram_space_1` (14GB): 0x880000000 - 0x440000000 (0x880000000 + 14GB)
+	 *
+	 * Note: The example memory addresses are for illustration and depend on the
+	 * platform's specific memory map.
+	 */
+	REGION(dram_space_1, 0x880000000, 0x780000000, 4K)
+	REGION(dram_space_2, 0x8800000000, 0x7800000000, 4K)
 }
diff --git a/src/soc/qualcomm/x1p42100/soc.c b/src/soc/qualcomm/x1p42100/soc.c
index a30c1b0ba4..fd429cc465 100644
--- a/src/soc/qualcomm/x1p42100/soc.c
+++ b/src/soc/qualcomm/x1p42100/soc.c
@@ -12,16 +12,24 @@ static struct device_operations pci_domain_ops = {
 	.scan_bus = &pci_host_bridge_scan_bus,
 	.enable = &qcom_setup_pcie_host,
 };
+
 static void soc_read_resources(struct device *dev)
 {
-	ram_range(dev, 0, (uintptr_t)region_offset(ddr_region), region_sz(ddr_region));
-	reserved_ram_range(dev, 1, (uintptr_t)_dram_cpucp_dtbs, REGION_SIZE(dram_cpucp_dtbs));
-	reserved_ram_range(dev, 2, (uintptr_t)_dram_cpucp, REGION_SIZE(dram_cpucp));
+	int index = 0;
+	int count;
+	struct region *config = qc_get_soc_dram_space_config(region_sz(ddr_region),
+				 &count);
 
-	reserved_ram_range(dev, 3, (uintptr_t)_dram_tz, REGION_SIZE(dram_tz));
-	reserved_ram_range(dev, 4, (uintptr_t)_dram_tz_rem, REGION_SIZE(dram_tz_rem));
+	for (int i = 0; i < count; i++)
+		ram_range(dev, index++, (uintptr_t)config[i].offset, config[i].size);
 
-	reserved_ram_range(dev, 5, (uintptr_t)_dram_aop, REGION_SIZE(dram_aop));
+	reserved_ram_range(dev, index++, (uintptr_t)_dram_cpucp_dtbs, REGION_SIZE(dram_cpucp_dtbs));
+	reserved_ram_range(dev, index++, (uintptr_t)_dram_cpucp, REGION_SIZE(dram_cpucp));
+
+	reserved_ram_range(dev, index++, (uintptr_t)_dram_tz, REGION_SIZE(dram_tz));
+	reserved_ram_range(dev, index++, (uintptr_t)_dram_tz_rem, REGION_SIZE(dram_tz_rem));
+
+	reserved_ram_range(dev, index++, (uintptr_t)_dram_aop, REGION_SIZE(dram_aop));
 }
 
 static void soc_init(struct device *dev)

From d6ec4f108d2aa8e4809e7c9f9dd0079f68c5dbff Mon Sep 17 00:00:00 2001
From: Subrata Banik <subratabanik@google.com>
Date: Fri, 15 Aug 2025 01:12:54 +0530
Subject: [PATCH 1800/3886] soc/qualcomm/x1p42100: Mark additional reserved
 memory ranges

This commit refactors the DRAM memory layout to reserve additional
regions critical for platform functionality and debugging. It
consolidates several CPUCP-related memory areas and adds new
reservations for Ramdump and Shared Memory.

- Ramdump and Shared Memory: New reserved regions, dram_ramdump and
  dram_smem, are added to protect memory used for crash dumps and
  inter-processor communication.

- CPUCP Optimization: The individual NCC, CPUCP, and CPUCP-DTS regions
  are consolidated into a single, contiguous dram_cpucp region from
  0x80A00000 to 0x815A0000. This simplifies the memory map and
  optimizes resource allocation.

Reserving these regions is crucial to prevent other bootloader stages
or the kernel from overwriting critical firmware data, which could lead
to unexpected behavior or system instability.

BUG=b:437948495
TEST=Able to ensure booting google/quenbi till kernel.

Change-Id: I80f6d288dd054a34a1e60736c8b14f072559c1ac
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88779
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/soc/qualcomm/common/include/soc/symbols_common.h | 2 ++
 src/soc/qualcomm/x1p42100/memlayout.ld               | 5 +++--
 src/soc/qualcomm/x1p42100/soc.c                      | 5 ++++-
 3 files changed, 9 insertions(+), 3 deletions(-)

diff --git a/src/soc/qualcomm/common/include/soc/symbols_common.h b/src/soc/qualcomm/common/include/soc/symbols_common.h
index caa1e7d174..64cb7ae38b 100644
--- a/src/soc/qualcomm/common/include/soc/symbols_common.h
+++ b/src/soc/qualcomm/common/include/soc/symbols_common.h
@@ -31,6 +31,8 @@ DECLARE_REGION(dram_cpucp)
 DECLARE_REGION(dram_modem)
 DECLARE_REGION(dram_tz)
 DECLARE_REGION(dram_tz_rem)
+DECLARE_REGION(dram_ramdump)
+DECLARE_REGION(dram_smem)
 
 /*
  * DDR_SPACE (2 GB) aka `_dram`:  0x80000000 - 0x100000000
diff --git a/src/soc/qualcomm/x1p42100/memlayout.ld b/src/soc/qualcomm/x1p42100/memlayout.ld
index ea21c27331..0fdfca25f9 100644
--- a/src/soc/qualcomm/x1p42100/memlayout.ld
+++ b/src/soc/qualcomm/x1p42100/memlayout.ld
@@ -57,14 +57,15 @@ SECTIONS
 	REGION(shrm, 0x24040000, 128K , 4K)
 
 	DRAM_START(0x80000000)
-	REGION(dram_cpucp_dtbs, 0x81240000, 0x2000, 0x1000)
-	REGION(dram_cpucp, 0x81250000, 0x80000, 0x1000)
+	REGION(dram_cpucp, 0x80A00000, 0xBA0000, 0x1000)
+	REGION(dram_ramdump, 0x81A00000, 0x200000, 0x1000)
 	REGION(dram_aop, 0x81C00000, 0xF780000, 0x1000)
 	POSTRAM_CBFS_CACHE(0x9F800000, 16M)
 	RAMSTAGE(0xA0800000, 16M)
 	REGION(dram_tz, 0xD8000000, 0xD6000, 0x1000)
 	BL31(0xD80D6000, 1M)
 	REGION(dram_tz_rem, 0xD81D6000, 0x72EA000, 0x1000)
+	REGION(dram_smem, 0xFF800000, 0x800000, 0x1000)
 	DRAM_END(0x100000000)
 
 	/*
diff --git a/src/soc/qualcomm/x1p42100/soc.c b/src/soc/qualcomm/x1p42100/soc.c
index fd429cc465..8066084fee 100644
--- a/src/soc/qualcomm/x1p42100/soc.c
+++ b/src/soc/qualcomm/x1p42100/soc.c
@@ -23,13 +23,16 @@ static void soc_read_resources(struct device *dev)
 	for (int i = 0; i < count; i++)
 		ram_range(dev, index++, (uintptr_t)config[i].offset, config[i].size);
 
-	reserved_ram_range(dev, index++, (uintptr_t)_dram_cpucp_dtbs, REGION_SIZE(dram_cpucp_dtbs));
 	reserved_ram_range(dev, index++, (uintptr_t)_dram_cpucp, REGION_SIZE(dram_cpucp));
 
+	reserved_ram_range(dev, index++, (uintptr_t)_dram_ramdump, REGION_SIZE(dram_ramdump));
+
 	reserved_ram_range(dev, index++, (uintptr_t)_dram_tz, REGION_SIZE(dram_tz));
 	reserved_ram_range(dev, index++, (uintptr_t)_dram_tz_rem, REGION_SIZE(dram_tz_rem));
 
 	reserved_ram_range(dev, index++, (uintptr_t)_dram_aop, REGION_SIZE(dram_aop));
+
+	reserved_ram_range(dev, index++, (uintptr_t)_dram_smem, REGION_SIZE(dram_smem));
 }
 
 static void soc_init(struct device *dev)

From b25939786d8a22735b57c271b39274c4f3c0e663 Mon Sep 17 00:00:00 2001
From: Subrata Banik <subratabanik@google.com>
Date: Fri, 15 Aug 2025 01:29:35 +0530
Subject: [PATCH 1801/3886] soc/qualcomm/x1p42100: Refactor CBMEM top address
 to use linker symbols

This commit refactors how the CBMEM top address is determined. Instead
of using a hardcoded value, the CBMEM top address is now starts at
offset `_dram_smem`.

Note: CBMEM region grows from top to bottom hence, starting cbmem_top
at offset `_dram_smem` won't override the SMEM reserved range.

The hardcoded value is problematic as it overrides the SMEM reserved
range and resulted into the boot halt.

The changes include:

- cbmem.c: The cbmem_top_chipset() function is updated to return the
address of the `_dram_smem` linker symbol plus its size.

This refactoring removes a magic number from the code, improving
readability, maintainability, and consistency with how other memory
regions are handled.

BUG=b:437948495
TEST=Able to ensure booting google/quenbi till kernel w/o
abrupt shutdown.

```
[DEBUG]  CBMEM:
[DEBUG]  IMD: root @ 0xff7ff000 254 entries.
[DEBUG]  IMD: root @ 0xff7fec00 62 entries.
```

Change-Id: Idb6a8a47f38d873c6ad4f0d995e77e657cc00ac0
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88780
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
---
 src/soc/qualcomm/x1p42100/cbmem.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/src/soc/qualcomm/x1p42100/cbmem.c b/src/soc/qualcomm/x1p42100/cbmem.c
index 5fff371d58..27a46f6f17 100644
--- a/src/soc/qualcomm/x1p42100/cbmem.c
+++ b/src/soc/qualcomm/x1p42100/cbmem.c
@@ -1,8 +1,9 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
 #include <cbmem.h>
+#include <soc/symbols_common.h>
 
 uintptr_t cbmem_top_chipset(void)
 {
-	return (uintptr_t)4 * GiB;
+	return (uintptr_t)_dram_smem;
 }

From d220b65b8fb69e3588dccba84e544fbc766de5d6 Mon Sep 17 00:00:00 2001
From: Subrata Banik <subratabanik@google.com>
Date: Sat, 16 Aug 2025 11:30:59 +0530
Subject: [PATCH 1802/3886] soc/qualcomm/qcs405: Add common include path

Add the common Qualcomm SoC include path to the qcs405 Makefile.
This allows the SoC-specific code to use shared headers located in
`src/soc/qualcomm/common/include`, promoting better code reuse and
organization.

TEST=Build for qcs405 target successfully.

Change-Id: Ie4bc9f3a4fc259adcdc4107c92aab0cb5c8676c1
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88789
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
---
 src/soc/qualcomm/qcs405/Makefile.mk | 1 +
 1 file changed, 1 insertion(+)

diff --git a/src/soc/qualcomm/qcs405/Makefile.mk b/src/soc/qualcomm/qcs405/Makefile.mk
index 5512af5650..6010759ca5 100644
--- a/src/soc/qualcomm/qcs405/Makefile.mk
+++ b/src/soc/qualcomm/qcs405/Makefile.mk
@@ -27,5 +27,6 @@ ramstage-y += usb.c
 ################################################################################
 
 CPPFLAGS_common += -Isrc/soc/qualcomm/qcs405/include
+CPPFLAGS_common += -Isrc/soc/qualcomm/common/include
 
 endif

From 6925fd69f86787bfb79e3e14bb2d019cd766a2af Mon Sep 17 00:00:00 2001
From: Subrata Banik <subratabanik@google.com>
Date: Sat, 16 Aug 2025 11:01:43 +0530
Subject: [PATCH 1803/3886] soc/qualcomm: Move common region macros to
 `soc/memlayout.h`

The `SSRAM_START/END`, `BSRAM_START/END`, and `AOPSRAM_START/END`
macros were redefined across multiple Qualcomm SoC `memlayout.ld` files.

To reduce code duplication and improve maintainability, this commit
moves these common macros into the shared `<soc/memlayout.h>` header
part of the Qualcomm common code.

The SoC-specific linker scripts are updated to remove the local
definitions.

TEST=Built for all affected SoCs (qcs405, sc7180, sc7280, x1p42100)

Change-Id: I8638b8e03e1e51f57b7e91a072f3d9cdb4ec6200
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88782
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/soc/qualcomm/common/include/soc/memlayout.h | 17 +++++++++++++++++
 src/soc/qualcomm/qcs405/memlayout.ld            |  9 +--------
 src/soc/qualcomm/sc7180/memlayout.ld            | 13 +------------
 src/soc/qualcomm/sc7280/memlayout.ld            | 13 +------------
 src/soc/qualcomm/x1p42100/memlayout.ld          | 15 +--------------
 5 files changed, 21 insertions(+), 46 deletions(-)
 create mode 100644 src/soc/qualcomm/common/include/soc/memlayout.h

diff --git a/src/soc/qualcomm/common/include/soc/memlayout.h b/src/soc/qualcomm/common/include/soc/memlayout.h
new file mode 100644
index 0000000000..83aaf913c5
--- /dev/null
+++ b/src/soc/qualcomm/common/include/soc/memlayout.h
@@ -0,0 +1,17 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+/* This file contains macro definitions for Qualcomm SoC memlayout.ld linker scripts. */
+
+#ifndef _SOC_QUALCOMM_MEMLAYOUT_H_
+#define _SOC_QUALCOMM_MEMLAYOUT_H_
+
+#define SSRAM_START(addr) REGION_START(ssram, addr)
+#define SSRAM_END(addr) REGION_END(ssram, addr)
+
+#define BSRAM_START(addr) REGION_START(bsram, addr)
+#define BSRAM_END(addr) REGION_END(bsram, addr)
+
+#define AOPSRAM_START(addr) REGION_START(aopsram, addr)
+#define AOPSRAM_END(addr) REGION_END(aopsram, addr)
+
+#endif  /* _SOC_QUALCOMM_MEMLAYOUT_H_ */
diff --git a/src/soc/qualcomm/qcs405/memlayout.ld b/src/soc/qualcomm/qcs405/memlayout.ld
index d883e24e2f..45d497e050 100644
--- a/src/soc/qualcomm/qcs405/memlayout.ld
+++ b/src/soc/qualcomm/qcs405/memlayout.ld
@@ -2,14 +2,7 @@
 
 #include <memlayout.h>
 #include <arch/header.ld>
-
-/* SYSTEM_IMEM : 0x8600000 - 0x8607FFF */
-#define SSRAM_START(addr) REGION_START(ssram, addr)
-#define SSRAM_END(addr) REGION_END(ssram, addr)
-
-/* BOOT_IMEM   : 0x8C00000 - 0x8D80000 */
-#define BSRAM_START(addr) REGION_START(bsram, addr)
-#define BSRAM_END(addr) REGION_END(bsram, addr)
+#include <soc/memlayout.h>
 
 SECTIONS
 {
diff --git a/src/soc/qualcomm/sc7180/memlayout.ld b/src/soc/qualcomm/sc7180/memlayout.ld
index 9c500c2b78..c65f415d7d 100644
--- a/src/soc/qualcomm/sc7180/memlayout.ld
+++ b/src/soc/qualcomm/sc7180/memlayout.ld
@@ -2,18 +2,7 @@
 
 #include <memlayout.h>
 #include <arch/header.ld>
-
-/* SYSTEM_IMEM : 0x14680000 - 0x146AE000 */
-#define SSRAM_START(addr) REGION_START(ssram, addr)
-#define SSRAM_END(addr) REGION_END(ssram, addr)
-
-/* BOOT_IMEM   : 0x14800000 - 0x14980000 */
-#define BSRAM_START(addr) REGION_START(bsram, addr)
-#define BSRAM_END(addr) REGION_END(bsram, addr)
-
-/* AOP : 0x0B000000 - 0x0B100000 */
-#define AOPSRAM_START(addr) REGION_START(aopsram, addr)
-#define AOPSRAM_END(addr) REGION_END(aopsram, addr)
+#include <soc/memlayout.h>
 
 SECTIONS
 {
diff --git a/src/soc/qualcomm/sc7280/memlayout.ld b/src/soc/qualcomm/sc7280/memlayout.ld
index b37b4816bb..731761c029 100644
--- a/src/soc/qualcomm/sc7280/memlayout.ld
+++ b/src/soc/qualcomm/sc7280/memlayout.ld
@@ -2,18 +2,7 @@
 
 #include <memlayout.h>
 #include <arch/header.ld>
-
-/* SYSTEM_IMEM : 0x14680000 - 0x146AB000 */
-#define SSRAM_START(addr) REGION_START(ssram, addr)
-#define SSRAM_END(addr) REGION_END(ssram, addr)
-
-/* BOOT_IMEM   : 0x14800000 - 0x14980000 */
-#define BSRAM_START(addr) REGION_START(bsram, addr)
-#define BSRAM_END(addr) REGION_END(bsram, addr)
-
-/* AOP : 0x0B000000 - 0x0B100000 */
-#define AOPSRAM_START(addr) REGION_START(aopsram, addr)
-#define AOPSRAM_END(addr) REGION_END(aopsram, addr)
+#include <soc/memlayout.h>
 
 SECTIONS
 {
diff --git a/src/soc/qualcomm/x1p42100/memlayout.ld b/src/soc/qualcomm/x1p42100/memlayout.ld
index 0fdfca25f9..36fb9a797a 100644
--- a/src/soc/qualcomm/x1p42100/memlayout.ld
+++ b/src/soc/qualcomm/x1p42100/memlayout.ld
@@ -2,20 +2,7 @@
 
 #include <memlayout.h>
 #include <arch/header.ld>
-
-/* Copied from Qualcomm previous generation SoC SC7280 and need cleanup */
-
-/* SYSTEM_IMEM : 0x14680000 - 0x146AB000 */
-#define SSRAM_START(addr) REGION_START(ssram, addr)
-#define SSRAM_END(addr) REGION_END(ssram, addr)
-
-/* BOOT_IMEM   : 0x14800000 - 0x14980000 */
-#define BSRAM_START(addr) REGION_START(bsram, addr)
-#define BSRAM_END(addr) REGION_END(bsram, addr)
-
-/* AOP : 0x0B000000 - 0x0B100000 */
-#define AOPSRAM_START(addr) REGION_START(aopsram, addr)
-#define AOPSRAM_END(addr) REGION_END(aopsram, addr)
+#include <soc/memlayout.h>
 
 SECTIONS
 {

From 2146ecc8e1f896a95246509be9aba10996ef50da Mon Sep 17 00:00:00 2001
From: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Date: Wed, 13 Aug 2025 13:35:08 +0800
Subject: [PATCH 1804/3886] mb/google/brox/caboc: Enable PEG60 with PEG62

Currently the SSD is preventing the system from entering S0ix sleep,
the system PKG C-State is stuck at PC3.

Intel RDC#642067 reveals while PEG60 is NDA but PEG62 is DA, need to
keep default PEG60 enabled and assign an unused CLKREQ# for port PEG60.

PEG60 is 00:06.0 (CPU PCIe Root port A).
PEG62 is 00:06.2 (CPU PCIe Root port B).
Caboc connectd SSD to PEG62 while PEG60 is not used.

As described above, follow RDC to assign the unused CLKREQ#5 for port
PEG60 and enable its related settings including pcie4_0, GPP_H23 NF2
as SRCCLKREQ#5, vGPIO and confirm the SSD can enter suspend.

BUG=b:435567235
TEST= emerge-brox coreboot
      suspend_stress_test pass 100 cycles on SSD sku.
      Measured the Boot/Resume time has improved.
      seconds_power_on_to_kernel (Boot time)
      Before/After 2.616/1.609
      seconds_system_resume (Resume time)
      Before/After s0ix error/0.338123

Change-Id: I26afeffd466cb2d8e0a0e4213214bde3b0a3b25b
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88764
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Simon Yang <simon1.yang@intel.com>
---
 .../google/brox/variants/caboc/gpio.c         | 25 +++++++++++++++++++
 .../brox/variants/caboc/overridetree.cb       | 10 ++++++++
 2 files changed, 35 insertions(+)

diff --git a/src/mainboard/google/brox/variants/caboc/gpio.c b/src/mainboard/google/brox/variants/caboc/gpio.c
index 49934999cf..c13b80cc02 100644
--- a/src/mainboard/google/brox/variants/caboc/gpio.c
+++ b/src/mainboard/google/brox/variants/caboc/gpio.c
@@ -67,6 +67,9 @@ static const struct pad_config override_gpio_table[] = {
 	PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1),
 	/* F21 : [NF1: Reserved NF6: USB_C_GPP_F21] ==> WWAN_OFF#(WWAN_FCPO_L)*/
 	PAD_CFG_GPO(GPP_F21, 1, DEEP),
+
+	/* GPP_H23 : SRCCLKREQ5_L ==>  */
+	PAD_CFG_NF(GPP_H23, NONE, DEEP, NF2),
 };
 
 /* Early pad configuration in bootblock */
@@ -129,6 +132,28 @@ static const struct pad_config early_gpio_table[] = {
 	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_73, NONE, PLTRST, NF1),
 	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_74, NONE, PLTRST, NF1),
 	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_75, NONE, PLTRST, NF1),
+
+	/* CPU PCIe vGPIO for PEG60 */
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_48, NONE, PLTRST, NF1),
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_49, NONE, PLTRST, NF1),
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_50, NONE, PLTRST, NF1),
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_51, NONE, PLTRST, NF1),
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_52, NONE, PLTRST, NF1),
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_53, NONE, PLTRST, NF1),
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_54, NONE, PLTRST, NF1),
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_55, NONE, PLTRST, NF1),
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_56, NONE, PLTRST, NF1),
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_57, NONE, PLTRST, NF1),
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_58, NONE, PLTRST, NF1),
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_59, NONE, PLTRST, NF1),
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_60, NONE, PLTRST, NF1),
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_61, NONE, PLTRST, NF1),
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_62, NONE, PLTRST, NF1),
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_63, NONE, PLTRST, NF1),
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_76, NONE, PLTRST, NF1),
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_77, NONE, PLTRST, NF1),
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_78, NONE, PLTRST, NF1),
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_79, NONE, PLTRST, NF1),
 };
 
 static const struct pad_config romstage_gpio_table[] = {
diff --git a/src/mainboard/google/brox/variants/caboc/overridetree.cb b/src/mainboard/google/brox/variants/caboc/overridetree.cb
index 45fbb167a0..e8be0e8990 100644
--- a/src/mainboard/google/brox/variants/caboc/overridetree.cb
+++ b/src/mainboard/google/brox/variants/caboc/overridetree.cb
@@ -233,6 +233,16 @@ chip soc/intel/alderlake
 				end
 			end
 		end
+		device ref pcie4_0 on
+			# Enable CPU PCIE RP 1 using CLK 5
+			register "cpu_pcie_rp[CPU_RP(1)]" = "{
+				.clk_req = 5,
+				.clk_src = 5,
+				.flags = PCIE_RP_LTR | PCIE_RP_AER,
+			}"
+			probe STORAGE STORAGE_NVME
+			probe unprovisioned
+		end
 		device ref pcie4_1 on
 			# Enable CPU PCIE RP 3 using CLK 0
 			register "cpu_pcie_rp[CPU_RP(3)]" = "{

From cdd42ccde89ba228aade96f68f61df524858d171 Mon Sep 17 00:00:00 2001
From: Subrata Banik <subratabanik@google.com>
Date: Sun, 17 Aug 2025 09:19:19 +0530
Subject: [PATCH 1805/3886] soc/qualcomm/x1p42100: Use 4K for memory region
 alignment

The alignment for several memory regions in the linker script was
specified using numeric values like `4096` or the hexadecimal `0x1000`.
Replace these values with the more readable `4K` shorthand. This change
improves consistency within the file and has no functional impact on
the generated binary.

TEST=Build and boot google/quenbi.

Change-Id: I28fdf3714d96f5e68a615d1550cf47d975ab5685
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88803
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
---
 src/soc/qualcomm/x1p42100/memlayout.ld | 16 ++++++++--------
 1 file changed, 8 insertions(+), 8 deletions(-)

diff --git a/src/soc/qualcomm/x1p42100/memlayout.ld b/src/soc/qualcomm/x1p42100/memlayout.ld
index 36fb9a797a..9101bd3bb8 100644
--- a/src/soc/qualcomm/x1p42100/memlayout.ld
+++ b/src/soc/qualcomm/x1p42100/memlayout.ld
@@ -7,8 +7,8 @@
 SECTIONS
 {
 	AOPSRAM_START(0x0B000000)
-	REGION(aop_code_ram, 0x0B000000, 0x80000, 4096)
-	REGION(aop_data_ram, 0x0B0E0000, 0x20000, 4096)
+	REGION(aop_code_ram, 0x0B000000, 0x80000, 4K)
+	REGION(aop_data_ram, 0x0B0E0000, 0x20000, 4K)
 	AOPSRAM_END(0x0B100000)
 
 	SSRAM_START(0x14680000)
@@ -44,15 +44,15 @@ SECTIONS
 	REGION(shrm, 0x24040000, 128K , 4K)
 
 	DRAM_START(0x80000000)
-	REGION(dram_cpucp, 0x80A00000, 0xBA0000, 0x1000)
-	REGION(dram_ramdump, 0x81A00000, 0x200000, 0x1000)
-	REGION(dram_aop, 0x81C00000, 0xF780000, 0x1000)
+	REGION(dram_cpucp, 0x80A00000, 0xBA0000, 4K)
+	REGION(dram_ramdump, 0x81A00000, 0x200000, 4K)
+	REGION(dram_aop, 0x81C00000, 0xF780000, 4K)
 	POSTRAM_CBFS_CACHE(0x9F800000, 16M)
 	RAMSTAGE(0xA0800000, 16M)
-	REGION(dram_tz, 0xD8000000, 0xD6000, 0x1000)
+	REGION(dram_tz, 0xD8000000, 0xD6000, 4K)
 	BL31(0xD80D6000, 1M)
-	REGION(dram_tz_rem, 0xD81D6000, 0x72EA000, 0x1000)
-	REGION(dram_smem, 0xFF800000, 0x800000, 0x1000)
+	REGION(dram_tz_rem, 0xD81D6000, 0x72EA000, 4K)
+	REGION(dram_smem, 0xFF800000, 0x800000, 4K)
 	DRAM_END(0x100000000)
 
 	/*

From 7eb832b1dc813df4d8ea16617da28ede14c5dacd Mon Sep 17 00:00:00 2001
From: Cong Yang <yangcong5@huaqin.corp-partner.google.com>
Date: Thu, 14 Aug 2025 13:56:29 +0800
Subject: [PATCH 1806/3886] mb/google/skywalker: Configure GPIO
 GPIO_AP_EDP_BKLTEN as output

Config GPIO GPIO_AP_EDP_BKLTEN as output low. When skipping firmware
display, it can prevent leakage to GPIO_AP_EDP_BKLTEN and cause it
to be pulled up to a 0.6 V step.

BUG=b:438353560
BRANCH=none
TEST=skip fw display check GPIO_AP_EDP_BKLTEN Waveform

Change-Id: Icea1e035d62c89ea26bc58afa1d64ab8a448cc04
Signed-off-by: Cong Yang <yangcong5@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88772
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Haikun Zhou <zhouhaikun5@huaqin.corp-partner.google.com>
---
 src/mainboard/google/skywalker/chromeos.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/src/mainboard/google/skywalker/chromeos.c b/src/mainboard/google/skywalker/chromeos.c
index 2bf47ed797..d5a04371df 100644
--- a/src/mainboard/google/skywalker/chromeos.c
+++ b/src/mainboard/google/skywalker/chromeos.c
@@ -33,6 +33,7 @@ void setup_chromeos_gpios(void)
 	gpio_output(GPIO_EN_PWR_FP, 0);
 	gpio_output(GPIO_FP_RST_1V8_S3_L, 0);
 	gpio_output(GPIO_EN_SPKR, 0);
+	gpio_output(GPIO_AP_EDP_BKLTEN, 0);
 }
 
 void fill_lb_gpios(struct lb_gpios *gpios)

From 74d91d0b766da4d478ffda83d8a570c25fdcf667 Mon Sep 17 00:00:00 2001
From: Daniel Peng <Daniel_Peng@pegatron.corp-partner.google.com>
Date: Fri, 15 Aug 2025 11:21:47 +0800
Subject: [PATCH 1807/3886] mb/google/nissa/var/glassway: Support Memory MICRON
 MT62F512M32D2DR-031WT:B

Add the new memory support: MICRON MT62F512M32D2DR-031WT:B

BUG=b:438654646
BRANCH=firmware-nissa-15217.B
TEST=Run command "go run ./util/spd_tools/src/part_id_gen/\
     part_id_gen.go ADL lp5 \
     src/mainboard/google/brya/variants/glassway/memory/ \
     src/mainboard/google/brya/variants/glassway/memory/\
     mem_parts_used.txt"

Change-Id: I3ffb5001596776ac4cfd9b3ffa2bb1c486b33b6f
Signed-off-by: Daniel Peng <Daniel_Peng@pegatron.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88781
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 .../google/brya/variants/glassway/memory/Makefile.mk          | 4 ++--
 .../brya/variants/glassway/memory/dram_id.generated.txt       | 3 ++-
 .../google/brya/variants/glassway/memory/mem_parts_used.txt   | 1 +
 3 files changed, 5 insertions(+), 3 deletions(-)

diff --git a/src/mainboard/google/brya/variants/glassway/memory/Makefile.mk b/src/mainboard/google/brya/variants/glassway/memory/Makefile.mk
index 63f419cd62..6e641062b0 100644
--- a/src/mainboard/google/brya/variants/glassway/memory/Makefile.mk
+++ b/src/mainboard/google/brya/variants/glassway/memory/Makefile.mk
@@ -1,13 +1,13 @@
 # SPDX-License-Identifier: GPL-2.0-or-later
 # This is an auto-generated file. Do not edit!!
 # Generated by:
-# /tmp/go-build4146048213/b001/exe/part_id_gen ADL lp5 src/mainboard/google/brya/variants/glassway/memory/ src/mainboard/google/brya/variants/glassway/memory/mem_parts_used.txt
+# /tmp/go-build2000974284/b001/exe/part_id_gen ADL lp5 src/mainboard/google/brya/variants/glassway/memory/ src/mainboard/google/brya/variants/glassway/memory/mem_parts_used.txt
 
 SPD_SOURCES =
 SPD_SOURCES += spd/lp5/set-0/spd-7.hex      # ID = 0(0b0000)  Parts = K3KL8L80CM-MGCT
 SPD_SOURCES += spd/lp5/set-0/spd-9.hex      # ID = 1(0b0001)  Parts = K3KL6L60GM-MGCT
 SPD_SOURCES += spd/lp5/set-0/spd-3.hex      # ID = 2(0b0010)  Parts = H58G56AK6BX069, K3LKBKB0BM-MGCP
-SPD_SOURCES += spd/lp5/set-0/spd-1.hex      # ID = 3(0b0011)  Parts = H9JCNNNBK3MLYR-N6E
+SPD_SOURCES += spd/lp5/set-0/spd-1.hex      # ID = 3(0b0011)  Parts = H9JCNNNBK3MLYR-N6E, MT62F512M32D2DR-031 WT:B
 SPD_SOURCES += spd/lp5/set-0/spd-6.hex      # ID = 4(0b0100)  Parts = H58G66AK6BX070
 SPD_SOURCES += spd/lp5/set-0/spd-8.hex      # ID = 5(0b0101)  Parts = K3KL9L90CM-MGCT
 SPD_SOURCES += spd/lp5/set-0/spd-11.hex      # ID = 6(0b0110)  Parts = H58G56CK8BX146
diff --git a/src/mainboard/google/brya/variants/glassway/memory/dram_id.generated.txt b/src/mainboard/google/brya/variants/glassway/memory/dram_id.generated.txt
index 7f1ca2ba39..681bc75870 100644
--- a/src/mainboard/google/brya/variants/glassway/memory/dram_id.generated.txt
+++ b/src/mainboard/google/brya/variants/glassway/memory/dram_id.generated.txt
@@ -1,7 +1,7 @@
 # SPDX-License-Identifier: GPL-2.0-or-later
 # This is an auto-generated file. Do not edit!!
 # Generated by:
-# /tmp/go-build4146048213/b001/exe/part_id_gen ADL lp5 src/mainboard/google/brya/variants/glassway/memory/ src/mainboard/google/brya/variants/glassway/memory/mem_parts_used.txt
+# /tmp/go-build2000974284/b001/exe/part_id_gen ADL lp5 src/mainboard/google/brya/variants/glassway/memory/ src/mainboard/google/brya/variants/glassway/memory/mem_parts_used.txt
 
 DRAM Part Name                 ID to assign
 K3KL8L80CM-MGCT                0 (0000)
@@ -12,3 +12,4 @@ H58G66AK6BX070                 4 (0100)
 K3KL9L90CM-MGCT                5 (0101)
 K3LKBKB0BM-MGCP                2 (0010)
 H58G56CK8BX146                 6 (0110)
+MT62F512M32D2DR-031 WT:B       3 (0011)
diff --git a/src/mainboard/google/brya/variants/glassway/memory/mem_parts_used.txt b/src/mainboard/google/brya/variants/glassway/memory/mem_parts_used.txt
index 796d10a21c..7f045dd656 100644
--- a/src/mainboard/google/brya/variants/glassway/memory/mem_parts_used.txt
+++ b/src/mainboard/google/brya/variants/glassway/memory/mem_parts_used.txt
@@ -17,3 +17,4 @@ H58G66AK6BX070
 K3KL9L90CM-MGCT
 K3LKBKB0BM-MGCP
 H58G56CK8BX146
+MT62F512M32D2DR-031 WT:B

From 9868417d5ed764be23d568b6cfed726414a2c59d Mon Sep 17 00:00:00 2001
From: Kapil Porwal <kapilporwal@google.com>
Date: Sat, 16 Aug 2025 00:45:37 +0530
Subject: [PATCH 1808/3886] mb/google/bluey: Refactor Kconfig for Hamoa SoC

BUG=b:436402120
TEST=Build Google/Quenbi.

Change-Id: Ia9cb040930be1609a9b2a0c9934b30e85386a2d6
Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88785
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
---
 src/mainboard/google/bluey/Kconfig | 27 ++++++++++++++++++---------
 1 file changed, 18 insertions(+), 9 deletions(-)

diff --git a/src/mainboard/google/bluey/Kconfig b/src/mainboard/google/bluey/Kconfig
index 356ec0705d..6e9cc6168d 100644
--- a/src/mainboard/google/bluey/Kconfig
+++ b/src/mainboard/google/bluey/Kconfig
@@ -4,7 +4,6 @@ config BOARD_GOOGLE_BLUEY_COMMON
 	def_bool n
 	select COMMON_CBFS_SPI_WRAPPER
 	select MAINBOARD_HAS_CHROMEOS
-	select SOC_QUALCOMM_X1P42100
 	select SPI_FLASH
 	select SPI_FLASH_FORCE_4_BYTE_ADDR_MODE
 
@@ -12,14 +11,20 @@ config BOARD_GOOGLE_BASEBOARD_BLUEY
 	def_bool n
 	select BOARD_GOOGLE_BLUEY_COMMON
 
-config BOARD_GOOGLE_BLUEY
+config BOARD_GOOGLE_MODEL_BLUEY
+	def_bool n
 	select BOARD_GOOGLE_BASEBOARD_BLUEY
 	select BOARD_ROMSIZE_KB_65536
 	select MAINBOARD_HAS_FINGERPRINT_VIA_USB
 	select MISSING_BOARD_RESET
 	select SPI_FLASH_MACRONIX
 
-config BOARD_GOOGLE_QUENBI
+config BOARD_GOOGLE_BLUEY
+	select BOARD_GOOGLE_MODEL_BLUEY
+	select SOC_QUALCOMM_X1P42100
+
+config BOARD_GOOGLE_MODEL_QUENBI
+	def_bool n
 	select BOARD_GOOGLE_BASEBOARD_BLUEY
 	select BOARD_ROMSIZE_KB_32768
 	select MAINBOARD_HAS_CHROME_EC
@@ -27,6 +32,10 @@ config BOARD_GOOGLE_QUENBI
 	select MAINBOARD_HAS_GOOGLE_TPM
 	select SPI_FLASH_WINBOND
 
+config BOARD_GOOGLE_QUENBI
+	select BOARD_GOOGLE_MODEL_QUENBI
+	select SOC_QUALCOMM_X1P42100
+
 if BOARD_GOOGLE_BLUEY_COMMON
 
 config MAINBOARD_DIR
@@ -84,7 +93,7 @@ config MAINBOARD_VENDOR
 	default "Google"
 
 config VBOOT
-	select VBOOT_NO_BOARD_SUPPORT if BOARD_GOOGLE_BLUEY
+	select VBOOT_NO_BOARD_SUPPORT if BOARD_GOOGLE_MODEL_BLUEY
 	select VBOOT_VBNV_FLASH
 
 ##########################################################
@@ -92,13 +101,13 @@ config VBOOT
 ##########################################################
 
 config MAINBOARD_PART_NUMBER
-	default "Bluey" if BOARD_GOOGLE_BLUEY
-	default "Quenbi" if BOARD_GOOGLE_QUENBI
+	default "Bluey" if BOARD_GOOGLE_MODEL_BLUEY
+	default "Quenbi" if BOARD_GOOGLE_MODEL_QUENBI
 
 config DRIVER_TPM_I2C_BUS
 	depends on I2C_TPM
 	hex
-	default 0xa if BOARD_GOOGLE_QUENBI
+	default 0xa if BOARD_GOOGLE_MODEL_QUENBI
 	default 0x10
 
 config DRIVER_TPM_I2C_ADDR
@@ -107,13 +116,13 @@ config DRIVER_TPM_I2C_ADDR
 config EC_GOOGLE_CHROMEEC_SPI_BUS
 	depends on EC_GOOGLE_CHROMEEC
 	hex
-	default 0xd if BOARD_GOOGLE_QUENBI
+	default 0xd if BOARD_GOOGLE_MODEL_QUENBI
 	default 0xb
 
 config MAINBOARD_GPIO_PIN_FOR_GSC_AP_INTERRUPT
 	depends on TPM_GOOGLE_TI50
 	int
-	default 91 if BOARD_GOOGLE_QUENBI
+	default 91 if BOARD_GOOGLE_MODEL_QUENBI
 	default 34
 	help
 	  This option specifies the GPIO pin number on the mainboard that is

From 9edf49b008bf231d0f3545730b3bca52e62ad0ac Mon Sep 17 00:00:00 2001
From: Kapil Porwal <kapilporwal@google.com>
Date: Sat, 16 Aug 2025 00:55:21 +0530
Subject: [PATCH 1809/3886] mb/google/bluey: Add BlueyH board

BUG=b:436402120
TEST=Build Google/BlueyH.

Change-Id: Ifceb70a2f25cff6d404bb6691146b2bb2109a957
Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88786
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/google/bluey/Kconfig      | 4 ++++
 src/mainboard/google/bluey/Kconfig.name | 3 +++
 2 files changed, 7 insertions(+)

diff --git a/src/mainboard/google/bluey/Kconfig b/src/mainboard/google/bluey/Kconfig
index 6e9cc6168d..aedee2a91a 100644
--- a/src/mainboard/google/bluey/Kconfig
+++ b/src/mainboard/google/bluey/Kconfig
@@ -23,6 +23,10 @@ config BOARD_GOOGLE_BLUEY
 	select BOARD_GOOGLE_MODEL_BLUEY
 	select SOC_QUALCOMM_X1P42100
 
+config BOARD_GOOGLE_BLUEYH
+	select BOARD_GOOGLE_MODEL_BLUEY
+	select SOC_QUALCOMM_HAMOA
+
 config BOARD_GOOGLE_MODEL_QUENBI
 	def_bool n
 	select BOARD_GOOGLE_BASEBOARD_BLUEY
diff --git a/src/mainboard/google/bluey/Kconfig.name b/src/mainboard/google/bluey/Kconfig.name
index 7196403480..d8d6d56765 100644
--- a/src/mainboard/google/bluey/Kconfig.name
+++ b/src/mainboard/google/bluey/Kconfig.name
@@ -7,3 +7,6 @@ config BOARD_GOOGLE_BLUEY
 
 config BOARD_GOOGLE_QUENBI
 	bool "->  Quenbi"
+
+config BOARD_GOOGLE_BLUEYH
+	bool "->  BlueyH"

From c61a762a47fdfe5344889550ea3bb7b805c4ab5e Mon Sep 17 00:00:00 2001
From: Kapil Porwal <kapilporwal@google.com>
Date: Sat, 16 Aug 2025 01:02:00 +0530
Subject: [PATCH 1810/3886] mb/google/bluey: Add QuenbiH board

BUG=b:436402120
TEST=Build Google/QuenbiH.

Change-Id: Ie4f3d6e41192e0865cd82285047f184bc2a8f425
Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88787
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
---
 src/mainboard/google/bluey/Kconfig      | 4 ++++
 src/mainboard/google/bluey/Kconfig.name | 3 +++
 2 files changed, 7 insertions(+)

diff --git a/src/mainboard/google/bluey/Kconfig b/src/mainboard/google/bluey/Kconfig
index aedee2a91a..096b3d9616 100644
--- a/src/mainboard/google/bluey/Kconfig
+++ b/src/mainboard/google/bluey/Kconfig
@@ -40,6 +40,10 @@ config BOARD_GOOGLE_QUENBI
 	select BOARD_GOOGLE_MODEL_QUENBI
 	select SOC_QUALCOMM_X1P42100
 
+config BOARD_GOOGLE_QUENBIH
+	select BOARD_GOOGLE_MODEL_QUENBI
+	select SOC_QUALCOMM_HAMOA
+
 if BOARD_GOOGLE_BLUEY_COMMON
 
 config MAINBOARD_DIR
diff --git a/src/mainboard/google/bluey/Kconfig.name b/src/mainboard/google/bluey/Kconfig.name
index d8d6d56765..3c173e0cc1 100644
--- a/src/mainboard/google/bluey/Kconfig.name
+++ b/src/mainboard/google/bluey/Kconfig.name
@@ -10,3 +10,6 @@ config BOARD_GOOGLE_QUENBI
 
 config BOARD_GOOGLE_BLUEYH
 	bool "->  BlueyH"
+
+config BOARD_GOOGLE_QUENBIH
+	bool "->  QuenbiH"

From d315f2621740175c6b52f17a1c781d19f6eedac7 Mon Sep 17 00:00:00 2001
From: Martin Kepplinger <martink@posteo.de>
Date: Tue, 1 Jul 2025 10:50:36 +0200
Subject: [PATCH 1811/3886] payload/seabios: Update from 1.16.3 to 1.17.0

from the project's Releases.md file:
* Prefer PCI IO allocations above 4Gig on 64bit capable machines.
* Multiple simultaneous USB keyboard and mouse support.
* Legacy support for internally generated ACPI tables has been removed.
* SeaVGABIOS support for VBE get/set palette data.
* Several bug fixes and code cleanups.

TEST=Successfully booted lenovo/t530

Change-Id: Ie1f0620ce46ebdafc84e8e13a79aa21c0526c235
Signed-off-by: Martin Kepplinger <martink@posteo.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88256
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
---
 payloads/external/SeaBIOS/Kconfig  | 2 +-
 payloads/external/SeaBIOS/Makefile | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/payloads/external/SeaBIOS/Kconfig b/payloads/external/SeaBIOS/Kconfig
index b12af46a14..38c7f7f36a 100644
--- a/payloads/external/SeaBIOS/Kconfig
+++ b/payloads/external/SeaBIOS/Kconfig
@@ -17,7 +17,7 @@ choice
 	default SEABIOS_STABLE
 
 config SEABIOS_STABLE
-	bool "1.16.3"
+	bool "1.17.0"
 	help
 	  Stable SeaBIOS version
 config SEABIOS_MASTER
diff --git a/payloads/external/SeaBIOS/Makefile b/payloads/external/SeaBIOS/Makefile
index 7926f3fb90..bd31f52c72 100644
--- a/payloads/external/SeaBIOS/Makefile
+++ b/payloads/external/SeaBIOS/Makefile
@@ -1,5 +1,5 @@
 TAG-$(CONFIG_SEABIOS_MASTER)=origin/master
-TAG-$(CONFIG_SEABIOS_STABLE)=a6ed6b701f0a57db0569ab98b0661c12a6ec3ff8
+TAG-$(CONFIG_SEABIOS_STABLE)=b52ca86e094d19b58e2304417787e96b940e39c6
 TAG-$(CONFIG_SEABIOS_REVISION)=$(CONFIG_SEABIOS_REVISION_ID)
 
 project_git_repo=https://review.coreboot.org/seabios.git

From 7c0f7e0b3f039fed9cf03db5956112e1bf3e2872 Mon Sep 17 00:00:00 2001
From: alokagar <alok.agarwal@intel.com>
Date: Fri, 1 Aug 2025 15:22:01 +0530
Subject: [PATCH 1812/3886] vc/intel/fsp: Update PTL FSP headers to FSP 3272_04

Update header files for FSP for Panther Lake platform to FSP 3272_04
from FSP 3182_01

Details:
-Update FspmUpd.h: Add below variable
   -MsHashInterleaveBit, MsHashMask, LogoPixelHeight, LogoPixelWidth,
    LogoXPosition, VgaGraphicsMode12ImagePtr, LogoYPosition,
    IsWckIdleExitEnabled, ChannelToCkdQckMapping, PhyClockToCkdDimm
-Update FspsUpd.h: Update the definition of PchTsnEnable
-Update MemInfoHob.h:
  - Add structure for RMT_VAR and related defintions.

BUG=b:435593291
TEST=Able to build google/fatcat with the partial header changes

Change-Id: Ibd9f32798e07d53a7e0e12b5828435c6d70f5f57
Signed-off-by: Alok Agarwal <alok.agarwal@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88632
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
---
 .../intel/fsp/fsp2_0/pantherlake/FspmUpd.h    | 107 ++++++++++++++----
 .../intel/fsp/fsp2_0/pantherlake/FspsUpd.h    |   4 +-
 .../intel/fsp/fsp2_0/pantherlake/MemInfoHob.h |  13 +++
 3 files changed, 101 insertions(+), 23 deletions(-)

diff --git a/src/vendorcode/intel/fsp/fsp2_0/pantherlake/FspmUpd.h b/src/vendorcode/intel/fsp/fsp2_0/pantherlake/FspmUpd.h
index 2e420cbec8..a2f8ce7572 100644
--- a/src/vendorcode/intel/fsp/fsp2_0/pantherlake/FspmUpd.h
+++ b/src/vendorcode/intel/fsp/fsp2_0/pantherlake/FspmUpd.h
@@ -636,9 +636,12 @@ typedef struct {
 **/
   UINT8                       ScramblerSupport;
 
-/** Offset 0x020B - Reserved
+/** Offset 0x020B - Memory Slice Hash Override
+  Memory Slice (Controller) Hash Mask and LSB Override. 0 = Use default memory slice
+  hash mask / lsb, 1 = Use values from MsHashMask and MsHashInterleaveBit
+  $EN_DIS
 **/
-  UINT8                       Reserved11;
+  UINT8                       MsHashOverride;
 
 /** Offset 0x020C - Memory Voltage
   DRAM voltage (Vdd) (supply voltage for input buffers and core logic of the DRAM
@@ -676,7 +679,7 @@ typedef struct {
 
 /** Offset 0x0213 - Reserved
 **/
-  UINT8                       Reserved12;
+  UINT8                       Reserved11;
 
 /** Offset 0x0214 - Ch Hash Override
   Select if Channel Hash setting values will be taken from input parameters or automatically
@@ -687,7 +690,7 @@ typedef struct {
 
 /** Offset 0x0215 - Reserved
 **/
-  UINT8                       Reserved13[2];
+  UINT8                       Reserved12[2];
 
 /** Offset 0x0217 - DQS Rise/Fall
   Enables/Disable DQS Rise/Fall
@@ -697,7 +700,7 @@ typedef struct {
 
 /** Offset 0x0218 - Reserved
 **/
-  UINT8                       Reserved14[2];
+  UINT8                       Reserved13[2];
 
 /** Offset 0x021A - Functional Duty Cycle Correction for DDR5 CLK
   Enable/Disable Functional Duty Cycle Correction for DDR5 CLK
@@ -729,7 +732,7 @@ typedef struct {
 
 /** Offset 0x021F - Reserved
 **/
-  UINT8                       Reserved15;
+  UINT8                       Reserved14;
 
 /** Offset 0x0220 - Functional Duty Cycle Correction for Data DQ
   Enable/Disable Functional Duty Cycle Correction for Data DQ
@@ -739,7 +742,7 @@ typedef struct {
 
 /** Offset 0x0221 - Reserved
 **/
-  UINT8                       Reserved16[5];
+  UINT8                       Reserved15[5];
 
 /** Offset 0x0226 - Unmatched Rx Calibration
   Enable/Disable Rx Unmatched Calibration
@@ -749,7 +752,24 @@ typedef struct {
 
 /** Offset 0x0227 - Reserved
 **/
-  UINT8                       Reserved17[26];
+  UINT8                       Reserved16[10];
+
+/** Offset 0x0231 - Memory Slice Hash LSB Bit
+  Memory Slice (Controller) Hash LSB bit. Valid values are 0..7 for BITS 6..13; used
+  when MsHashOverride is set
+  0:BIT6, 1:BIT7, 2:BIT8, 3:BIT9, 4:BIT10, 5:BIT11, 6:BIT12, 7:BIT13
+**/
+  UINT8                       MsHashInterleaveBit;
+
+/** Offset 0x0232 - Memory Slice Hash Mask
+  Memory Slice (Controller) Hash Mask: 0x0001=BIT6 set(Minimal), 0x3FFF=BIT[19:6]
+  set(Maximum); used when MsHashOverride is set
+**/
+  UINT16                      MsHashMask;
+
+/** Offset 0x0234 - Reserved
+**/
+  UINT8                      Reserved17[13];
 
 /** Offset 0x0241 - LVR Auto Trim
   Enable/disable LVR Auto Trim
@@ -1427,9 +1447,15 @@ typedef struct {
 **/
   UINT8                       Use1p5ReadPostamble;
 
-/** Offset 0x031D - Reserved
+/** Offset 0x031D - IsWckIdleExitEnabled
+  Enables/Disables WCK Idle Exit
+  $EN_DIS
 **/
-  UINT8                       Reserved32[18];
+  UINT8                       IsWckIdleExitEnabled;
+
+/** Offset 0x031E - Reserved
+**/
+  UINT8                       Reserved32[17];
 
 /** Offset 0x032F - Board Type
   MrcBoardType, Options are 0=Mobile/Mobile Halo, 1=Desktop/DT Halo, 5=ULT/ULX/Mobile
@@ -2716,14 +2742,37 @@ typedef struct {
 /** Offset 0x0A71 - Control SOL VGA Initialition sequence
   Initialise SOL Init, BIT0 - (0 : Disable VGA Support, 1 : Enable VGA Support),,
   BIT1 - (0 : VGA Text Mode 3, 1 : VGA Graphics Mode 12), BIT2 - (0 : VGA Exit Supported,
-  1: NO VGA Exit)
+  1: NO VGA Exit), BIT3 - (0 : VGA Init During Display Init, 1 - VGA Init During
+  MRC Cold Boot), BIT4 - (0 : Enable Progress Bar, 1 : Disable Progress Bar)
   0:VGA Disable, 1:Mode 3 VGA, 2:Mode 12 VGA
 **/
   UINT8                       VgaInitControl;
 
-/** Offset 0x0A72 - Reserved
+/** Offset 0x0A72 - SOL VGA Graphics Mode 12 LogoPixelHeight
+  Heigh of VGA Graphics Mode 12 Logo
 **/
-  UINT8                      Reserved84[16];
+  UINT16                      LogoPixelHeight;
+
+/** Offset 0x0A74 - SOL VGA Graphics Mode 12 LogoPixelWidth
+  Width of VGA Graphics Mode 12 Logo
+**/
+  UINT16                      LogoPixelWidth;
+
+/** Offset 0x0A76 - SOL VGA Graphics Mode 12 Image X Position
+  X position of Image on Display
+**/
+  UINT16                      LogoXPosition;
+
+/** Offset 0x0A78 - SOL VGA Graphics Mode 12 Image Pointer
+  Points to SOL VGA Graphics Graphics 12 Image, VgaPlanarImage200x58[4][58][25] for
+  58Hx200W as example,
+**/
+  UINT64                      VgaGraphicsMode12ImagePtr;
+
+/** Offset 0x0A80 - SOL VGA Graphics Mode 12 Image Y Position
+  Y position of Image on Display
+**/
+  UINT16                      LogoYPosition;
 
 /** Offset 0x0A82 - TCSS USB HOST (xHCI) Enable
   Set TCSS XHCI. 0:Disabled  1:Enabled - Must be enabled if xDCI is enabled below
@@ -2733,7 +2782,7 @@ typedef struct {
 
 /** Offset 0x0A83 - Reserved
 **/
-  UINT8                       Reserved85[4];
+  UINT8                       Reserved84[4];
 
 /** Offset 0x0A87 - TCSS Type C Port 0
   Set TCSS Type C Port 0 Type, Options are 0=DISABLE, 1=DP_ONLY, 2=NO_TBT, 3=NO_PCIE,
@@ -2765,7 +2814,7 @@ typedef struct {
 
 /** Offset 0x0A8B - Reserved
 **/
-  UINT8                       Reserved86;
+  UINT8                       Reserved85;
 
 /** Offset 0x0A8C - TypeC port GPIO setting
   GPIO Pin number for Type C Aux orientation setting, use the GpioPad that is defined
@@ -2833,7 +2882,7 @@ typedef struct {
 
 /** Offset 0x0AC9 - Reserved
 **/
-  UINT8                       Reserved87;
+  UINT8                       Reserved86;
 
 /** Offset 0x0ACA - DLL Weak Lock Support
   Enables/Disable DLL Weak Lock Support
@@ -2843,7 +2892,7 @@ typedef struct {
 
 /** Offset 0x0ACB - Reserved
 **/
-  UINT8                       Reserved88;
+  UINT8                       Reserved87;
 
 /** Offset 0x0ACC - Rx DQS Delay Comp Support
   Enables/Disable Rx DQS Delay Comp Support
@@ -2853,7 +2902,7 @@ typedef struct {
 
 /** Offset 0x0ACD - Reserved
 **/
-  UINT8                       Reserved89[2];
+  UINT8                       Reserved88[2];
 
 /** Offset 0x0ACF - Mrc Failure On Unsupported Dimm
   Enables/Disable Mrc Failure On Unsupported Dimm
@@ -2863,7 +2912,7 @@ typedef struct {
 
 /** Offset 0x0AD0 - Reserved
 **/
-  UINT8                      Reserved90[4];
+  UINT8                      Reserved89[4];
 
 /** Offset 0x0AD4 - DynamicMemoryBoost
   Enable/Disable Dynamic Memory Boost Feature. Only valid if SpdProfileSelected is
@@ -2881,7 +2930,7 @@ typedef struct {
 
 /** Offset 0x0ADC - Reserved
 **/
-  UINT8                      Reserved91[9];
+  UINT8                      Reserved90[9];
 
 /** Offset 0x0AE5 - Vref Offset
   Offset to be applied to DDRDATACH0_CR_DDRCRDATAOFFSETTRAIN.VrefOffset
@@ -2892,7 +2941,7 @@ typedef struct {
 
 /** Offset 0x0AE6 - Reserved
 **/
-  UINT8                       Reserved92[2];
+  UINT8                       Reserved91[2];
 
 /** Offset 0x0AE8 - tRRSG Delta
   Delay between Read-to-Read commands in the same Bank Group. 0 - Auto. Signed TAT
@@ -3008,7 +3057,21 @@ typedef struct {
 
 /** Offset 0x0AF8 - Reserved
 **/
-  UINT8                       Reserved93[112];
+  UINT8                       Reserved92[41];
+
+/** Offset 0x0B21 - Channel to CKD QCK Mapping
+  Specify Channel to CKD QCK Mapping for CH0D0/CH0D1/CH1D0&CH1D1
+**/
+  UINT8                       ChannelToCkdQckMapping[8];
+
+/** Offset 0x0B29 - DDRIO Clock to CKD DIMM
+  Specify DDRIO Clock to CKD DIMM for CH0D0/CH0D1/CH1D0&CH1D1
+**/
+  UINT8                       PhyClockToCkdDimm[8];
+
+/** Offset 0x0B31 - Reserved
+**/
+  UINT8                       Reserved93[55];
 } FSP_M_CONFIG;
 
 /** Fsp M UPD Configuration
diff --git a/src/vendorcode/intel/fsp/fsp2_0/pantherlake/FspsUpd.h b/src/vendorcode/intel/fsp/fsp2_0/pantherlake/FspsUpd.h
index 8e6541ba1c..0b540c7e14 100644
--- a/src/vendorcode/intel/fsp/fsp2_0/pantherlake/FspsUpd.h
+++ b/src/vendorcode/intel/fsp/fsp2_0/pantherlake/FspsUpd.h
@@ -1667,7 +1667,9 @@ typedef struct {
 **/
   UINT16                      PchTemperatureHotLevel;
 
-/** Offset 0x1226
+/** Offset 0x1226 - Enable PCH TSN
+  Enable/disable TSN on the PCH.
+  $EN_DIS
 **/
   UINT8                       PchTsnEnable[4];
 
diff --git a/src/vendorcode/intel/fsp/fsp2_0/pantherlake/MemInfoHob.h b/src/vendorcode/intel/fsp/fsp2_0/pantherlake/MemInfoHob.h
index f36dc915e3..4171f4a1da 100644
--- a/src/vendorcode/intel/fsp/fsp2_0/pantherlake/MemInfoHob.h
+++ b/src/vendorcode/intel/fsp/fsp2_0/pantherlake/MemInfoHob.h
@@ -392,6 +392,19 @@ typedef struct {
   UINT8                *Buffer;
 } MEMORY_PLATFORM_DATA_HOB;
 
+#define EFI_RMT_OS_VARIABLE_NAME        L"Rmt"
+#define RMT_ENABLE  1
+#define RMT_DISABLE 0
+
+extern EFI_GUID gRmtVariableGuid;
+
+//Structure of RMT UEFI variable which should be R/W by OS
+//EnDsRmt - To enable Memory margining support
+
+typedef struct {
+  UINT8                EnDsRmt;
+} RMT_VAR;
+
 #pragma pack (pop)
 
 #endif // _MEM_INFO_HOB_H_

From e37a53a2fc9faa944aa3a224cf942d0c89bf9414 Mon Sep 17 00:00:00 2001
From: Patrick Rudolph <patrick.rudolph@9elements.com>
Date: Sat, 16 Aug 2025 09:21:25 +0200
Subject: [PATCH 1813/3886] arch/x86/memcpy: Fix undefined behaviour

Clear DF flag before invoking MOVS instruction to make sure it
increments %esi/%edi on each mov.

Change-Id: I209f50dec2003ea9846e5958d3e77b8979f338df
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88796
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/arch/x86/memcpy.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/src/arch/x86/memcpy.c b/src/arch/x86/memcpy.c
index 9da2a7512e..3b5a64d163 100644
--- a/src/arch/x86/memcpy.c
+++ b/src/arch/x86/memcpy.c
@@ -16,6 +16,7 @@ void *memcpy(void *dest, const void *src, size_t n)
 
 #if ENV_X86_64
 	asm volatile(
+		"cld\n\t"
 		"rep ; movsq\n\t"
 		"mov %4,%%rcx\n\t"
 		"rep ; movsb\n\t"
@@ -25,6 +26,7 @@ void *memcpy(void *dest, const void *src, size_t n)
 	);
 #else
 	asm volatile(
+		"cld\n\t"
 		"rep ; movsl\n\t"
 		"movl %4,%%ecx\n\t"
 		"rep ; movsb\n\t"

From eee5be070a0561cdd6b030f9c8954f3010f68e88 Mon Sep 17 00:00:00 2001
From: Patrick Rudolph <patrick.rudolph@9elements.com>
Date: Sun, 17 Aug 2025 14:54:33 +0200
Subject: [PATCH 1814/3886] cpu/intel: Use mtrr_use_temp_range()

Cover the SPIROM with a temporary MTRR to speed up SPI flash accesses
after MPinit has removed the MTRR that was installed for postcar stage.

TEST=Booted on Lenovo X220 and measured using cbmem -t:
Before:
  16:finished LZMA decompress (ignore for x86)         1,391,520 (366,351)

After:
  16:finished LZMA decompress (ignore for x86)         1,218,418 (210,054)

Boots 156msec faster than before.

Change-Id: Ia3df06b5c2a09e05c76361f3e38be83475122ee7
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88811
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/cpu/intel/haswell/haswell_init.c         | 4 ++++
 src/cpu/intel/model_2065x/model_2065x_init.c | 4 ++++
 src/cpu/intel/model_206ax/model_206ax_init.c | 4 ++++
 3 files changed, 12 insertions(+)

diff --git a/src/cpu/intel/haswell/haswell_init.c b/src/cpu/intel/haswell/haswell_init.c
index 8232453a57..a54a01ad8f 100644
--- a/src/cpu/intel/haswell/haswell_init.c
+++ b/src/cpu/intel/haswell/haswell_init.c
@@ -579,6 +579,10 @@ void mp_init_cpus(struct bus *cpu_bus)
 	cpu_cluster = cpu_bus->dev;
 	/* TODO: Handle mp_init_with_smm failure? */
 	mp_init_with_smm(cpu_bus, &mp_ops);
+
+	/* pre_mp_init made the flash not cacheable. Reset to WP for performance. */
+	mtrr_use_temp_range(CACHE_ROM_BASE, CAR_CACHE_ROM_SIZE,
+			    MTRR_TYPE_WRPROT);
 }
 
 static struct device_operations cpu_dev_ops = {
diff --git a/src/cpu/intel/model_2065x/model_2065x_init.c b/src/cpu/intel/model_2065x/model_2065x_init.c
index cb74854346..70a2d1ae80 100644
--- a/src/cpu/intel/model_2065x/model_2065x_init.c
+++ b/src/cpu/intel/model_2065x/model_2065x_init.c
@@ -167,6 +167,10 @@ void mp_init_cpus(struct bus *cpu_bus)
 {
 	/* TODO: Handle mp_init_with_smm failure? */
 	mp_init_with_smm(cpu_bus, &mp_ops);
+
+	/* pre_mp_init made the flash not cacheable. Reset to WP for performance. */
+	mtrr_use_temp_range(CACHE_ROM_BASE, CAR_CACHE_ROM_SIZE,
+			    MTRR_TYPE_WRPROT);
 }
 
 static struct device_operations cpu_dev_ops = {
diff --git a/src/cpu/intel/model_206ax/model_206ax_init.c b/src/cpu/intel/model_206ax/model_206ax_init.c
index 23310a303b..21a13f3d11 100644
--- a/src/cpu/intel/model_206ax/model_206ax_init.c
+++ b/src/cpu/intel/model_206ax/model_206ax_init.c
@@ -547,6 +547,10 @@ void mp_init_cpus(struct bus *cpu_bus)
 {
 	/* TODO: Handle mp_init_with_smm failure? */
 	mp_init_with_smm(cpu_bus, &mp_ops);
+
+	/* pre_mp_init made the flash not cacheable. Reset to WP for performance. */
+	mtrr_use_temp_range(CACHE_ROM_BASE, CAR_CACHE_ROM_SIZE,
+			    MTRR_TYPE_WRPROT);
 }
 
 static struct device_operations cpu_dev_ops = {

From 244a34b3d0e5f5278194e0902870060448c347eb Mon Sep 17 00:00:00 2001
From: NyeonWoo Kim <knw0507@naver.com>
Date: Sat, 16 Aug 2025 13:34:35 +0900
Subject: [PATCH 1815/3886] cpu/x86/mp_init: Refactor ICR wait logic

Extracted ICR wait logic into a new function 'icr_wait_timeout'.

Change-Id: Ie48899f7afb125061fd7efd44c83f5775c05d254
Signed-off-by: NyeonWoo Kim <knw0507@naver.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88788
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
---
 src/cpu/x86/mp_init.c | 32 ++++++++++++++------------------
 1 file changed, 14 insertions(+), 18 deletions(-)

diff --git a/src/cpu/x86/mp_init.c b/src/cpu/x86/mp_init.c
index f223ccc6e5..23880c74c8 100644
--- a/src/cpu/x86/mp_init.c
+++ b/src/cpu/x86/mp_init.c
@@ -424,8 +424,7 @@ static enum cb_err apic_wait_timeout(int total_delay, int delay_step)
 	return CB_SUCCESS;
 }
 
-/* Send Startup IPI to APs */
-static enum cb_err send_sipi_to_aps(int ap_count, atomic_t *num_aps, int sipi_vector)
+static enum cb_err icr_wait_timeout(void)
 {
 	if (lapic_busy()) {
 		printk(BIOS_DEBUG, "Waiting for ICR not to be busy...\n");
@@ -436,6 +435,15 @@ static enum cb_err send_sipi_to_aps(int ap_count, atomic_t *num_aps, int sipi_ve
 		printk(BIOS_DEBUG, "done.\n");
 	}
 
+	return CB_SUCCESS;
+}
+
+/* Send Startup IPI to APs */
+static enum cb_err send_sipi_to_aps(int ap_count, atomic_t *num_aps, int sipi_vector)
+{
+	if (icr_wait_timeout() != CB_SUCCESS)
+		return CB_ERR;
+
 	lapic_send_ipi_others(LAPIC_INT_ASSERT | LAPIC_MT_STARTUP | sipi_vector);
 	printk(BIOS_DEBUG, "Waiting for SIPI to complete...\n");
 	if (apic_wait_timeout(10000 /* 10 ms */, 50 /* us */) != CB_SUCCESS) {
@@ -466,14 +474,8 @@ static enum cb_err start_aps(struct bus *cpu_bus, int ap_count, atomic_t *num_ap
 
 	printk(BIOS_DEBUG, "Attempting to start %d APs\n", ap_count);
 
-	if (lapic_busy()) {
-		printk(BIOS_DEBUG, "Waiting for ICR not to be busy...\n");
-		if (apic_wait_timeout(1000 /* 1 ms */, 50) != CB_SUCCESS) {
-			printk(BIOS_ERR, "timed out. Aborting.\n");
-			return CB_ERR;
-		}
-		printk(BIOS_DEBUG, "done.\n");
-	}
+	if (icr_wait_timeout() != CB_SUCCESS)
+		return CB_ERR;
 
 	/* Send INIT IPI to all but self. */
 	lapic_send_ipi_others(LAPIC_INT_ASSERT | LAPIC_MT_INIT);
@@ -651,14 +653,8 @@ static enum cb_err mp_init(struct bus *cpu_bus, struct mp_params *p)
 
 void smm_initiate_relocation_parallel(void)
 {
-	if (lapic_busy()) {
-		printk(BIOS_DEBUG, "Waiting for ICR not to be busy...");
-		if (apic_wait_timeout(1000 /* 1 ms */, 50) != CB_SUCCESS) {
-			printk(BIOS_DEBUG, "timed out. Aborting.\n");
-			return;
-		}
-		printk(BIOS_DEBUG, "done.\n");
-	}
+	if (icr_wait_timeout() != CB_SUCCESS)
+		return;
 
 	lapic_send_ipi_self(LAPIC_INT_ASSERT | LAPIC_MT_SMI);
 

From 40d0ec0fa4b6aa22a815b52a4c2dcb63fa0d2b10 Mon Sep 17 00:00:00 2001
From: Yu-Ping Wu <yupingso@google.com>
Date: Mon, 18 Aug 2025 03:44:08 +0000
Subject: [PATCH 1816/3886] Revert "soc/mediatek/common: Remove 200 ms delay
 from eDP init path"

This reverts commit df7bf9404d5805c84a1d37d00ad44df35cd5e92b.

Reason for revert: This breaks Skywalker firmware display.

Change-Id: I92cb26533c73f4e0c552f3c41d9c1f408ca2d083
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88812
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/soc/mediatek/common/display.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/src/soc/mediatek/common/display.c b/src/soc/mediatek/common/display.c
index c805c6d664..417a764499 100644
--- a/src/soc/mediatek/common/display.c
+++ b/src/soc/mediatek/common/display.c
@@ -90,6 +90,7 @@ int mtk_display_init(void)
 	process_panel_quirks(&mtk_edp, panel);
 
 	if (panel->disp_path == DISP_PATH_EDP) {
+		mdelay(200);
 		if (mtk_edp_init(&mtk_edp, &edid) < 0) {
 			printk(BIOS_ERR, "%s: Failed to initialize eDP\n", __func__);
 			return -1;

From 6acf07022d8f996de91ff39323a5d271f4269b63 Mon Sep 17 00:00:00 2001
From: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Date: Thu, 14 Aug 2025 21:12:08 +0900
Subject: [PATCH 1817/3886] Doc/contributing: Add clarification on how to
 reference other commits

This should address the following open action item from the coreboot
leadership meetings[1]:

> Add clarification to docs, "do not use gerrit change-id or CB: format
> in reference to already-merged patches".

[1] https://mail.coreboot.org/archives/list/coreboot@coreboot.org/thread/YCA55MINAFK5M56OAUA2NMM7WDMDEGXI/

Change-Id: Ie742caca70e284254bb7f8a070c3a441b6a80c58
Signed-off-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88776
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 Documentation/contributing/git_commit_messages.md | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/Documentation/contributing/git_commit_messages.md b/Documentation/contributing/git_commit_messages.md
index a007b2a20c..fc53bdb148 100644
--- a/Documentation/contributing/git_commit_messages.md
+++ b/Documentation/contributing/git_commit_messages.md
@@ -47,8 +47,9 @@ to go over everything again. There are other tutorials that cover that.
 
 - Make sure the problem being solved by the commit is described. While
   it may be obvious to the committer, it may not be obvious to others.
-- Reference other commits with either CB:XXXXX or a 10 character hash
-  and the subject.
+- When referencing other commits use a 12 character hash and the subject
+  (e.g. `commit XXXXXXXXXXXX ("some commit")`). However, use `CB:XXXXX`
+  when referring to an open or abandoned change on Gerrit.
 - When using a URL in a commit message, use archive.org when possible.
   URLs often get changed or go stale, so this keeps them stable.
 - Make sure that all changes in a patch are addressed in the commit

From 48207895af70611186459c8a2de7c6233bb5fc59 Mon Sep 17 00:00:00 2001
From: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Date: Fri, 8 Aug 2025 07:31:39 +0900
Subject: [PATCH 1818/3886] lint: Warn about using change IDs for merged
 changes

This script will warn and suggest fixes when a CB:<change-id> of an
already merged change is found in the commit message. This should
enforce the clarification that was added to the documentation in
CB:88776.

This script requires a JSON parser (i.e. jq) to parse Gerrit's
REST API[1]. While it may be possible to grep the values, we chose to
use a proper parser to ensure there would be no false-positives.

TEST=
Prepare a commit with the following commit message:

  Here are some open changes: CB:88614 CB:88717 CB:87282
  Here are some abandoned changes: CB:88413 CB:84504 CB:82136
  Here are some merged changes: CB:88566 CB:88598 CB:88697
  Here are some old merged commits: CB:1 CB:50 CB:950
  Here are some wrong stuff: CL:100 CB:TEST CB:99999

The script produces the following result (may change in the future when
open changes are merged etc):

  Using a change ID (CB:88566) for an already merged commit; please replace it with:
  commit 21639c377120 ("mb/getac/p470: Use common gpio functions")
  Using a change ID (CB:88598) for an already merged commit; please replace it with:
  commit 05a38e2af3f0 ("mb/google/fatcat: Disable memory training progress bar")
  Using a change ID (CB:88697) for an already merged commit; please replace it with:
  commit 1da2f46db869 ("soc/intel/alderlake: Restore mem_init_override_channel_mask()")
  Using a change ID (CB:1) for an already merged commit; please replace it with:
  commit 140a990a612e ("Teach abuild to emit JUnit formatted build reports")
  Using a change ID (CB:50) for an already merged commit; please replace it with:
  commit 7c634ae8c18d ("msrtool: added support for Intel CPUs")
  Using a change ID (CB:950) for an already merged commit; please replace it with:
  commit c31384e62c98 ("Fix up Sandybridge C state generation code")
  CB:99999 does not exist

[1] https://gerrit-review.googlesource.com/Documentation/rest-api.html

Change-Id: I1c72f739b1f47b1227ef1e158b1553aa56945d7e
Signed-off-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88715
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
---
 util/lint/lint-extended-025-merged-change-ids | 97 +++++++++++++++++++
 1 file changed, 97 insertions(+)
 create mode 100755 util/lint/lint-extended-025-merged-change-ids

diff --git a/util/lint/lint-extended-025-merged-change-ids b/util/lint/lint-extended-025-merged-change-ids
new file mode 100755
index 0000000000..10f9d793b3
--- /dev/null
+++ b/util/lint/lint-extended-025-merged-change-ids
@@ -0,0 +1,97 @@
+#!/usr/bin/env sh
+# SPDX-License-Identifier: GPL-2.0-or-later
+#
+# DESCR: Check that CB:<change-id> does not refer to a merged change
+
+
+LINTDIR="$(
+  cd -- "$(dirname "$0")" > /dev/null 2>&1 || return
+  pwd -P
+)"
+
+# shellcheck source=helper_functions.sh
+. "${LINTDIR}/helper_functions.sh"
+
+if [ "${IN_GIT_TREE}" -eq 0 ]; then
+	exit 0
+fi
+
+if ! command -v jq > /dev/null; then
+	printf 'This script requires "jq" to be installed\n' >&2
+	exit 1
+fi
+
+GERRIT_REST_API_URL="https://review.coreboot.org"
+# Excerpt from documentation[1]:
+#
+# > To prevent against Cross Site Script Inclusion (XSSI) attacks, the JSON
+# > response body starts with a magic prefix line that must be stripped before
+# > feeding the rest of the response body to a JSON parser.
+#
+# [1] https://gerrit-review.googlesource.com/Documentation/rest-api.html#output
+GERRIT_REST_API_MAGIC_PREFIX=")]}'"
+
+api_request() {
+	api="$1"
+	curl --silent "${GERRIT_REST_API_URL}/${api}" \
+	    | sed "s/^${GERRIT_REST_API_MAGIC_PREFIX}//"
+}
+
+# Fetch git log in the format specified by the Linux kernel guidelines[1], which
+# coreboot follows, for referencing merged commits.
+#
+# [1] https://www.kernel.org/doc/html/v4.10/process/submitting-patches.html
+search_commit() {
+	${GIT} log -n 1 --abbrev=12 --pretty='commit %h ("%s")' "$@" 2> /dev/null
+}
+
+get_commit_reference() {
+	change_id="$1"
+	response="$(api_request "changes/coreboot~${change_id}/revisions/current/commit")"
+
+	hash="$(echo "${response}" | jq --raw-output .commit)"
+	reference="$(search_commit "${hash}")"
+
+	# Earlier changes merged through Gerrit (around < CB:1000) did not
+	# update the patchset once being cherry-picked into the codebase.
+	# Therefore, the pre-merged commit remains in Gerrit's database (what we
+	# query with the REST API) and causes problems, as the commit hash would
+	# be different from the one found in the main branch.
+	#
+	# To workaround this issue, we attempt to find the corresponding commit
+	# by grepping for a commit message that contains a specific "Change-Id".
+	if [ -z "${reference}" ]; then
+		hash="$(echo "${response}" \
+		    | jq .message          \
+		    | sed -E 's/.*Change-Id: ([[:alnum:]]+).*/\1/')"
+		reference="$(search_commit --grep "${hash}")"
+	fi
+
+	if [ -z "${reference}" ]; then
+		reference="(cannot find commit; probably requires a rebase)"
+	fi
+
+	echo "${reference}"
+}
+
+# This test is mainly for the jenkins server
+for change_id in $(${GIT} log -n 1 | grep -Eo 'CB:[0-9]+'); do
+	change_id="${change_id#CB:}" # strip "CB:" prefix from change ID
+
+	response="$(api_request "changes/coreboot~${change_id}")"
+
+	if echo "${response}" | grep -qF 'Not found'; then
+		printf 'CB:%d does not exist\n' "${change_id}"
+		continue
+	fi
+
+	status="$(echo "${response}" | jq --raw-output .status)"
+
+	if [ "${status}" = "MERGED" ]; then
+		reference="$(get_commit_reference "${change_id}")"
+
+		printf 'Using a change ID (CB:%d) for an already merged change; please replace it with:\n' \
+		    "${change_id}"
+		printf '%s\n' "${reference}"
+	fi
+done

From 5de5b519ca8f4470821933ec442987dbad59965f Mon Sep 17 00:00:00 2001
From: Elyes Haouas <ehaouas@noos.fr>
Date: Tue, 19 Aug 2025 18:42:55 +0200
Subject: [PATCH 1819/3886] mb/prodrive/atlas/vpd.c: Replace union {0}
 initializers with {} for C23 compliance

This change addresses GCC-15 behavior where {0} union initializers only
clear the first member, leaving padding bits uninitialized. The new {}
initializer ensures full union clearing as required by C23.

Change-Id: I1d2761856e0c9bf9cc7045cc8e3af622582bd1ed
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88860
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/prodrive/atlas/vpd.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/mainboard/prodrive/atlas/vpd.c b/src/mainboard/prodrive/atlas/vpd.c
index badbc6e3d1..b2e4a1d1c5 100644
--- a/src/mainboard/prodrive/atlas/vpd.c
+++ b/src/mainboard/prodrive/atlas/vpd.c
@@ -19,7 +19,7 @@ const struct emi_eeprom_vpd *get_emi_eeprom_vpd(void)
 	static union {
 		struct emi_eeprom_vpd layout;
 		uint8_t raw[sizeof(struct emi_eeprom_vpd)];
-	} vpd = {0};
+	} vpd = {};
 
 	/* Check if cached VPD is valid */
 	if (vpd.layout.header.revision == VPD_LATEST_REVISION)

From 3f4c84513d85278b2bc52286e015c726ffed1a92 Mon Sep 17 00:00:00 2001
From: Swathi Tamilselvan <tswathi@qualcomm.corp-partner.google.com>
Date: Tue, 19 Aug 2025 09:51:55 +0530
Subject: [PATCH 1820/3886] soc/qualcomm/x1p42100/qclib: Support to pack AOP
 config and meta in CBFS

Add support to pack AOP config and AOP config metadata. Reserve
region for aop blob meta load in memlayout.

Change-Id: Iafa4d878d6bf515824681b24f6078ab868c26bf6
Signed-off-by: Swathi Tamilselvan <tswathi@qualcomm.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88814
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
---
 src/soc/qualcomm/x1p42100/Makefile.mk  | 22 ++++++++++++++++++++++
 src/soc/qualcomm/x1p42100/memlayout.ld |  1 +
 2 files changed, 23 insertions(+)

diff --git a/src/soc/qualcomm/x1p42100/Makefile.mk b/src/soc/qualcomm/x1p42100/Makefile.mk
index d96dd8d760..1c0d3fe762 100644
--- a/src/soc/qualcomm/x1p42100/Makefile.mk
+++ b/src/soc/qualcomm/x1p42100/Makefile.mk
@@ -166,6 +166,28 @@ $(AOP_META_CBFS)-type := raw
 $(AOP_META_CBFS)-compression := $(CBFS_COMPRESS_FLAG)
 cbfs-files-y += $(AOP_META_CBFS)
 
+################################################################################
+AOP_CFG_FILE := $(X1P42100_BLOB)/aop/aop_devcfg.mbn
+AOP_CFG_CBFS := $(CONFIG_CBFS_PREFIX)/aop_cfg
+$(AOP_CFG_CBFS)-file := $(AOP_CFG_FILE)
+$(AOP_CFG_CBFS)-type := payload
+$(AOP_CFG_CBFS)-compression := $(CBFS_COMPRESS_FLAG)
+cbfs-files-y += $(AOP_CFG_CBFS)
+
+################################################################################
+# Rule to create aop_meta from aop_devcfg.mbn
+# This rule depends on aop_devcfg.mbn built and the extractor script existing.
+$(obj)/mainboard/$(MAINBOARDDIR)/aop_devcfg_meta: $(X1P42100_BLOB)/aop/aop_devcfg.mbn util/qualcomm/elf_segment_extractor.py
+	@echo "Extracting ELF headers and hash table segment from $< to $@"
+	@util/qualcomm/elf_segment_extractor.py --eh --pht --hashtable $< $@
+
+AOP_DEVCFG_META_FILE := $(obj)/mainboard/$(MAINBOARDDIR)/aop_devcfg_meta
+AOP_DEVCFG_META_CBFS := $(CONFIG_CBFS_PREFIX)/aop_devcfg_meta
+$(AOP_DEVCFG_META_CBFS)-file := $(AOP_DEVCFG_META_FILE)
+$(AOP_DEVCFG_META_CBFS)-type := raw
+$(AOP_DEVCFG_META_CBFS)-compression := $(CBFS_COMPRESS_FLAG)
+cbfs-files-y += $(AOP_DEVCFG_META_CBFS)
+
 ################################################################################
 CPUCP_FILE := $(X1P42100_BLOB)/cpucp/cpucp.elf
 CPUCP_CBFS := $(CONFIG_CBFS_PREFIX)/cpucp
diff --git a/src/soc/qualcomm/x1p42100/memlayout.ld b/src/soc/qualcomm/x1p42100/memlayout.ld
index 9101bd3bb8..4154534f2b 100644
--- a/src/soc/qualcomm/x1p42100/memlayout.ld
+++ b/src/soc/qualcomm/x1p42100/memlayout.ld
@@ -34,6 +34,7 @@ SECTIONS
 	REGION(dtb, 0x14870000, 32K, 4K)
 	REGION(ddr_training, 0x14878000, 64K, 4K)
 	REGION(qc_blob_meta, 0x14888000, 16K, 4K)
+	REGION(aop_blob_meta, 0x1488c000, 16K, 4K)
 	REGION(qclib, 0x14897000, 1536K, 4K)
 	PRERAM_CBMEM_CONSOLE(0x14A30000, 32K)
 	OVERLAP_DECOMPRESSOR_VERSTAGE_ROMSTAGE(0x14A38000, 132K)

From ee347d88120bca22d64a1581cd91eee786e2d7db Mon Sep 17 00:00:00 2001
From: Swathi Tamilselvan <tswathi@qualcomm.corp-partner.google.com>
Date: Tue, 19 Aug 2025 09:53:54 +0530
Subject: [PATCH 1821/3886] soc/qualcomm/common/qclib: Support to load AOP
 config and meta in CBFS

Add support to load AOP config and AOP config metadata.

TEST=Create an image.serial.bin and ensure it boots on X1P42100.

Change-Id: Ic6a7eaa771178f20920df7936685cb212467b055
Signed-off-by: Swathi Tamilselvan <tswathi@qualcomm.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88856
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
---
 .../qualcomm/common/include/soc/qclib_common.h |  2 ++
 .../common/include/soc/symbols_common.h        |  1 +
 src/soc/qualcomm/common/qclib.c                | 18 ++++++++++++++++++
 3 files changed, 21 insertions(+)

diff --git a/src/soc/qualcomm/common/include/soc/qclib_common.h b/src/soc/qualcomm/common/include/soc/qclib_common.h
index fc2ed93399..9f5ee52bfc 100644
--- a/src/soc/qualcomm/common/include/soc/qclib_common.h
+++ b/src/soc/qualcomm/common/include/soc/qclib_common.h
@@ -26,6 +26,7 @@
 #define QCLIB_TE_DTB_SETTINGS      "dtb"
 #define QCLIB_TE_SHRM_META_SETTINGS	"shrm_metadata"
 #define QCLIB_TE_AOP_META_SETTINGS      "aop_metadata"
+#define QCLIB_TE_AOP_DEVCFG_META_SETTINGS	"aop_cfg_metadata"
 
 /* BA_BMASK_VALUES (blob_attributes bit mask values) */
 #define QCLIB_BA_SAVE_TO_STORAGE 0x00000001
@@ -38,6 +39,7 @@ enum qclib_cbfs_file {
 	QCLIB_CBFS_DTB,
 	QCLIB_CBFS_SHRM_META,
 	QCLIB_CBFS_AOP_META,
+	QCLIB_CBFS_AOP_DEVCFG_META,
 	QCLIB_CBFS_MAX
 };
 
diff --git a/src/soc/qualcomm/common/include/soc/symbols_common.h b/src/soc/qualcomm/common/include/soc/symbols_common.h
index 64cb7ae38b..10a4e41298 100644
--- a/src/soc/qualcomm/common/include/soc/symbols_common.h
+++ b/src/soc/qualcomm/common/include/soc/symbols_common.h
@@ -15,6 +15,7 @@ DECLARE_REGION(dram_soc)
 DECLARE_REGION(dcb)
 DECLARE_REGION(dtb)
 DECLARE_REGION(qc_blob_meta)
+DECLARE_REGION(aop_blob_meta)
 DECLARE_OPTIONAL_REGION(pmic)
 DECLARE_REGION(limits_cfg)
 DECLARE_REGION(aop)
diff --git a/src/soc/qualcomm/common/qclib.c b/src/soc/qualcomm/common/qclib.c
index 3470741f7c..e2b5ac00cc 100644
--- a/src/soc/qualcomm/common/qclib.c
+++ b/src/soc/qualcomm/common/qclib.c
@@ -88,6 +88,8 @@ const char *qclib_file_default(enum qclib_cbfs_file file)
 		return CONFIG_CBFS_PREFIX "/shrm_meta";
 	case QCLIB_CBFS_AOP_META:
 		return CONFIG_CBFS_PREFIX "/aop_meta";
+	case QCLIB_CBFS_AOP_DEVCFG_META:
+		return CONFIG_CBFS_PREFIX "/aop_devcfg_meta";
 	default:
 		die("unknown QcLib file %d", file);
 	}
@@ -331,6 +333,12 @@ void qclib_rerun(void)
 
 	init_qclib_cb_if_table(&qclib_cb_if_table);
 
+	struct prog aop_cfg_fw_prog =
+				PROG_INIT(PROG_PAYLOAD, CONFIG_CBFS_PREFIX "/aop_cfg");
+
+	if (!selfload(&aop_cfg_fw_prog))
+		die("SOC image: AOP load failed");
+
 	/* Attempt to load aop_meta Blob (reuse the qc_blob_meta region). */
 	data_size = cbfs_load(qclib_file(QCLIB_CBFS_AOP_META),
 			_qc_blob_meta, REGION_SIZE(qc_blob_meta));
@@ -341,6 +349,16 @@ void qclib_rerun(void)
 
 	qclib_add_if_table_entry(QCLIB_TE_AOP_META_SETTINGS, _qc_blob_meta, data_size, 0);
 
+	/* Attempt to load aop_devcfg_meta Blob. */
+	data_size = cbfs_load(qclib_file(QCLIB_CBFS_AOP_DEVCFG_META),
+			_aop_blob_meta, REGION_SIZE(aop_blob_meta));
+	if (!data_size) {
+		printk(BIOS_ERR, "[%s] /aop_devcfg_meta failed\n", __func__);
+		goto fail;
+	}
+
+	qclib_add_if_table_entry(QCLIB_TE_AOP_DEVCFG_META_SETTINGS, _aop_blob_meta, data_size, 0);
+
 	/* Set up the system and jump into QcLib */
 	printk(BIOS_DEBUG, "\n\n\nRe-enter QCLib to bring up AOP\n");
 	qclib_prepare_and_run();

From 6ba2df9be55dc90694067c76763918e8b26decc1 Mon Sep 17 00:00:00 2001
From: Vince Liu <vince-wl.liu@mediatek.corp-partner.google.com>
Date: Tue, 19 Aug 2025 18:08:02 +0800
Subject: [PATCH 1822/3886] soc/mediatek/common: Use polling to reduce eDP HPD
 wait time

Some eDP panels assert HPD (Hot Plug Detect) after panel VCC is enabled,
typically around 200ms. To reduce boot time, this commit replaces the
original fixed 200ms delay with polling for the HPD status, shortening
the waiting period to approximately 70ms.

Once the HPD pin is detected high, an additional delay of around 1ms is
introduced to ensure the AUX channel is ready for EDID reading.

BUG=b:434574691,b:439535227,b:439476647
BRANCH=none
TEST=Check firmware display on Navi and Skywalker

Signed-off-by: Bincai Liu <bincai.liu@mediatek.corp-partner.google.com>
Signed-off-by: Vince Liu <vince-wl.liu@mediatek.corp-partner.google.com>
Change-Id: I6702c79416700b44d4bfbc763b6fc6003feb69b5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88864
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
---
 src/soc/mediatek/common/display.c                    | 1 -
 src/soc/mediatek/common/dp/dptx_common.c             | 3 ++-
 src/soc/mediatek/common/dp/include/soc/dptx_common.h | 3 +++
 3 files changed, 5 insertions(+), 2 deletions(-)

diff --git a/src/soc/mediatek/common/display.c b/src/soc/mediatek/common/display.c
index 417a764499..c805c6d664 100644
--- a/src/soc/mediatek/common/display.c
+++ b/src/soc/mediatek/common/display.c
@@ -90,7 +90,6 @@ int mtk_display_init(void)
 	process_panel_quirks(&mtk_edp, panel);
 
 	if (panel->disp_path == DISP_PATH_EDP) {
-		mdelay(200);
 		if (mtk_edp_init(&mtk_edp, &edid) < 0) {
 			printk(BIOS_ERR, "%s: Failed to initialize eDP\n", __func__);
 			return -1;
diff --git a/src/soc/mediatek/common/dp/dptx_common.c b/src/soc/mediatek/common/dp/dptx_common.c
index 9c6cdcba4d..342f742a2c 100644
--- a/src/soc/mediatek/common/dp/dptx_common.c
+++ b/src/soc/mediatek/common/dp/dptx_common.c
@@ -549,10 +549,11 @@ int mtk_edp_init(struct mtk_dp *mtk_dp, struct edid *edid)
 	dptx_init_variable(mtk_dp);
 	dptx_init_port(mtk_dp);
 
-	if (!dptx_hal_hpd_high(mtk_dp)) {
+	if (!wait_ms(HPD_WAIT_TIMEOUT_MS, dptx_hal_hpd_high(mtk_dp))) {
 		printk(BIOS_ERR, "HPD is low\n");
 		return -1;
 	}
+	mdelay(WAIT_AUX_READY_TIME_MS);
 
 	dptx_check_sinkcap(mtk_dp);
 
diff --git a/src/soc/mediatek/common/dp/include/soc/dptx_common.h b/src/soc/mediatek/common/dp/include/soc/dptx_common.h
index b65948fbad..8a42a63996 100644
--- a/src/soc/mediatek/common/dp/include/soc/dptx_common.h
+++ b/src/soc/mediatek/common/dp/include/soc/dptx_common.h
@@ -69,6 +69,9 @@
 
 #define MAX_LANECOUNT				4
 
+#define HPD_WAIT_TIMEOUT_MS			200
+#define WAIT_AUX_READY_TIME_MS			1
+
 enum {
 	DP_LANECOUNT_1	= 0x1,
 	DP_LANECOUNT_2	= 0x2,

From a2b6e205098d1f188f729f5eab3ce6a3e8f23e4b Mon Sep 17 00:00:00 2001
From: Niklaus Liu <niklaus.liu@mediatek.corp-partner.google.com>
Date: Sat, 16 Aug 2025 15:04:16 +0800
Subject: [PATCH 1823/3886] soc/mediatek/common: Increase per-channel SPMI max
 byte count to 2

In the scenario of suspend, when the SPM firmware attempts to turn off
the VDDQ and VMDDR power supplies, the command sent is rejected by PMIF,
resulting in a system hang. The reason is that SPM simultaneously wrote
two registers (two bytes), while the original configuration only allowed
reading or writing one byte at a time.

Modify the maximum number of bytes that an SPMI user can read or write
in a single operation to meet the requirement of reading or writing 16
bits at once.

BUG=b:420874944
BRANCH=skywalker
TEST=2-byte R/W passed; suspend-resume verified successfully.

Change-Id: I46ace45564328c46ab340b74d73e3574957e36ef
Signed-off-by: Niklaus Liu <niklaus.liu@mediatek.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88790
Reviewed-by: Vince Liu <vince-wl.liu@mediatek.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Niklaus Liu <niklaus.liu@mediatek.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
---
 src/soc/mediatek/common/pmif_spmi.c | 16 +++++++++-------
 1 file changed, 9 insertions(+), 7 deletions(-)

diff --git a/src/soc/mediatek/common/pmif_spmi.c b/src/soc/mediatek/common/pmif_spmi.c
index d6318eaa8c..6bc3e31524 100644
--- a/src/soc/mediatek/common/pmif_spmi.c
+++ b/src/soc/mediatek/common/pmif_spmi.c
@@ -104,14 +104,16 @@ static void pmif_spmi_enable(struct pmif *arb)
 	pmif_spmi_config(arb);
 
 	/*
-	 * set bytecnt max limitation.
-	 * hw bytecnt indicate when we set 0, it can send 1 byte;
-	 * set 1, it can send 2 byte.
+	 * Set max bytecnt. For each 32-bit reg, 4 bits indicate one channel.
+	 * 0x0 means max bytecnt = 1.
+	 * 0x1 means max bytecnt = 2.
+	 * Here we set max bytecnt to 2 for all channels.
 	 */
-	write32(&arb->mtk_pmif->inf_max_bytecnt_per_0, 0);
-	write32(&arb->mtk_pmif->inf_max_bytecnt_per_1, 0);
-	write32(&arb->mtk_pmif->inf_max_bytecnt_per_2, 0);
-	write32(&arb->mtk_pmif->inf_max_bytecnt_per_3, 0);
+
+	write32(&arb->mtk_pmif->inf_max_bytecnt_per_0, 0x11111111);
+	write32(&arb->mtk_pmif->inf_max_bytecnt_per_1, 0x11111111);
+	write32(&arb->mtk_pmif->inf_max_bytecnt_per_2, 0x11111111);
+	write32(&arb->mtk_pmif->inf_max_bytecnt_per_3, 0x11111111);
 
 	/* Add latency limitation */
 	write32(&arb->mtk_pmif->lat_cnter_en, PMIF_SPMI_INF);

From cec34128d0d8cf771cbd68eee1c18ffef8211635 Mon Sep 17 00:00:00 2001
From: Swathi Tamilselvan <tswathi@qualcomm.corp-partner.google.com>
Date: Mon, 18 Aug 2025 12:48:25 +0530
Subject: [PATCH 1824/3886] soc/qualcomm/x1p42100: Support to load CPUCP
 firmware in x1p42100

CPUCP firmware along with its corresponding DTB must be loaded
and then taken out of reset from coreboot to initialize the CPUCP
subsystem. This patch adds support to load CPUCP and CPUCP DTB
firmware in X1P42100. The register details are part of
HRD-X1P42100-S1 document.
https://docs.qualcomm.com/bundle/resource/topics/HRD-X1P42100-S1/

TEST=1. Create an image.serial.bin and ensure it boots on X1P42100.
2. Verified using CPUCP load log from coreboot.
```
[INFO ]  CBFS: Found 'fallback/cpucp_dtbs' @0xe5580 size 0x163 in mcache
		 @0xff7dd714
[INFO ]  VB2:vb2_secdata_kernel_get() VB2_SECDATA_KERNEL_FLAGS not
		supported for secdata_kernel v0, return 0
[INFO ]  VB2:vb2_digest_init() 355 bytes, hash algo 2, HW acceleration
		forbidden
[DEBUG]  Loading segment from ROM address 0x9f8040f8
[DEBUG]    code (compression=1)
[DEBUG]    New segment dstaddr 0x81240000 memsize 0x103c srcaddr
		0x9f804130 filesize 0x12b
[DEBUG]  Loading Segment: addr: 0x81240000 memsz: 0x000000000000103c
		filesz: 0x000000000000012b
[DEBUG]  using LZMA
[SPEW ]  [ 0x81240000, 8124103c, 0x8124103c) <- 9f804130
[DEBUG]  Loading segment from ROM address 0x9f804114
[DEBUG]    Entry Point 0x81240000
[SPEW ]  Loaded segments
[DEBUG]  SOC:CPUCP DTBS image loaded successfully.
[INFO ]  CBFS: Found 'fallback/cpucp' @0xbe8c0 size 0x2607d in mcache
		@0xff7dd658
[DEBUG]  read SPI 0xcee914 0x2607d: 12635 us, 12328 KB/s, 98.624 Mbps
[INFO ]  VB2:vb2_secdata_kernel_get() VB2_SECDATA_KERNEL_FLAGS not
		supported for secdata_kernel v0, return 0
[INFO ]  VB2:vb2_digest_init() 155773 bytes, hash algo 2, HW
		acceleration forbidden
[DEBUG]  Loading segment from ROM address 0x9f8040f8
[DEBUG]    code (compression=1)
[DEBUG]    New segment dstaddr 0x1cb00000 memsize 0x2a628 srcaddr
		0x9f8041f4 filesize 0x11c6f
[DEBUG]  Loading Segment: addr: 0x1cb00000 memsz: 0x000000000002a628
		filesz: 0x0000000000011c6f
[DEBUG]  using LZMA
[SPEW ]  [ 0x1cb00000, 1cb21950, 0x1cb2a628) <- 9f8041f4
[DEBUG]  Clearing Segment: addr: 0x000000001cb21950 memsz:
		0x0000000000008cd8
[DEBUG]  Loading segment from ROM address 0x9f804114
[DEBUG]    data (compression=1)
[DEBUG]    New segment dstaddr 0x1cb2b000 memsize 0xb520 srcaddr
		0x9f815e63 filesize 0x134e
[DEBUG]  Loading Segment: addr: 0x1cb2b000 memsz: 0x000000000000b520
		filesz: 0x000000000000134e
[DEBUG]  using LZMA
[SPEW ]  [ 0x1cb2b000, 1cb36520, 0x1cb36520) <- 9f815e63
[DEBUG]  Loading segment from ROM address 0x9f804130
[DEBUG]    data (compression=1)
[DEBUG]    New segment dstaddr 0x1cb3e000 memsize 0x890 srcaddr
		0x9f8171b1 filesize 0x23
[DEBUG]  Loading Segment: addr: 0x1cb3e000 memsz: 0x0000000000000890
		filesz: 0x0000000000000023
[DEBUG]  using LZMA
[SPEW ]  [ 0x1cb3e000, 1cb3e890, 0x1cb3e890) <- 9f8171b1
[DEBUG]  Loading segment from ROM address 0x9f80414c
[DEBUG]    BSS 0x1cb3f000 (4096 byte)
[DEBUG]  Loading Segment: addr: 0x1cb3f000 memsz: 0x0000000000001000
		filesz: 0x0000000000000000
[DEBUG]  it's not compressed!
[SPEW ]  [ 0x1cb3f000, 1cb3f000, 0x1cb40000) <- 9f8171d4
[DEBUG]  Clearing Segment: addr: 0x000000001cb3f000 memsz:
		0x0000000000001000
[DEBUG]  Loading segment from ROM address 0x9f804168
[DEBUG]    BSS 0x81200000 (38916 byte)
[DEBUG]  Loading Segment: addr: 0x81200000 memsz: 0x0000000000009804
		filesz: 0x0000000000000000
[DEBUG]  it's not compressed!
[SPEW ]  [ 0x81200000, 81200000, 0x81209804) <- 9f8171d4
[DEBUG]  Clearing Segment: addr: 0x0000000081200000 memsz:
		0x0000000000009804
[DEBUG]  Loading segment from ROM address 0x9f804184
[DEBUG]    data (compression=1)
[DEBUG]    New segment dstaddr 0x81250000 memsize 0x11068 srcaddr
		0x9f8171d4 filesize 0xe59
[DEBUG]  Loading Segment: addr: 0x81250000 memsz: 0x0000000000011068
		filesz: 0x0000000000000e59
[DEBUG]  using LZMA
[SPEW ]  [ 0x81250000, 81261068, 0x81261068) <- 9f8171d4
[DEBUG]  Loading segment from ROM address 0x9f8041a0
[DEBUG]    data (compression=1)
[DEBUG]    New segment dstaddr 0x81280000 memsize 0xc628 srcaddr
		0x9f81802d filesize 0x6d09
[DEBUG]  Loading Segment: addr: 0x81280000 memsz: 0x000000000000c628
		filesz: 0x0000000000006d09
[DEBUG]  using LZMA
[SPEW ]  [ 0x81280000, 8128c628, 0x8128c628) <- 9f81802d
[DEBUG]  Loading segment from ROM address 0x9f8041bc
[DEBUG]    data (compression=1)
[DEBUG]    New segment dstaddr 0x81290000 memsize 0x31bf8 srcaddr
		0x9f81ed36 filesize 0xb43f
[DEBUG]  Loading Segment: addr: 0x81290000 memsz: 0x0000000000031bf8
		filesz: 0x000000000000b43f
[DEBUG]  using LZMA
[SPEW ]  [ 0x81290000, 812c1bf8, 0x812c1bf8) <- 9f81ed36
[DEBUG]  Loading segment from ROM address 0x9f8041d8
[DEBUG]    Entry Point 0x1cb00000
[SPEW ]  Loaded segments
[DEBUG]  SOC:CPUCP image loaded successfully.
[DEBUG]  CPU_CLUSTER: 0 init finished in 735 msecs
```

Change-Id: I195f038b2380de7796691f0194cf3e39f8d9a991
Signed-off-by: Swathi Tamilselvan <tswathi@qualcomm.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88815
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/soc/qualcomm/x1p42100/Makefile.mk         |  7 +++++
 src/soc/qualcomm/x1p42100/cpucp_load_reset.c  | 28 +++++++++++++++----
 .../x1p42100/include/soc/addressmap.h         |  6 ++++
 src/soc/qualcomm/x1p42100/soc.c               |  3 +-
 4 files changed, 37 insertions(+), 7 deletions(-)

diff --git a/src/soc/qualcomm/x1p42100/Makefile.mk b/src/soc/qualcomm/x1p42100/Makefile.mk
index 1c0d3fe762..36d2578cf5 100644
--- a/src/soc/qualcomm/x1p42100/Makefile.mk
+++ b/src/soc/qualcomm/x1p42100/Makefile.mk
@@ -210,6 +210,13 @@ $(CPUCP_META_CBFS)-type := raw
 $(CPUCP_META_CBFS)-compression := $(CBFS_COMPRESS_FLAG)
 cbfs-files-y += $(CPUCP_META_CBFS)
 
+################################################################################
+CPUCP_DTBS_FILE := $(X1P42100_BLOB)/cpucp/cpucp_dtbs.elf
+CPUCP_DTBS_CBFS := $(CONFIG_CBFS_PREFIX)/cpucp_dtbs
+$(CPUCP_DTBS_CBFS)-file := $(CPUCP_DTBS_FILE)
+$(CPUCP_DTBS_CBFS)-type := payload
+$(CPUCP_DTBS_CBFS)-compression := $(CBFS_COMPRESS_FLAG)
+cbfs-files-y += $(CPUCP_DTBS_CBFS)
 
 ################################################################################
 SHRM_FILE := $(X1P42100_BLOB)/shrm/shrm.elf
diff --git a/src/soc/qualcomm/x1p42100/cpucp_load_reset.c b/src/soc/qualcomm/x1p42100/cpucp_load_reset.c
index f415bb8555..804c992425 100644
--- a/src/soc/qualcomm/x1p42100/cpucp_load_reset.c
+++ b/src/soc/qualcomm/x1p42100/cpucp_load_reset.c
@@ -1,13 +1,29 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
+#include <console/console.h>
+#include <program_loading.h>
 #include <soc/cpucp.h>
-
-void cpucp_prepare(void)
-{
-	/* Placeholder */
-}
+#include <device/mmio.h>
+#include <soc/addressmap.h>
 
 void cpucp_fw_load_reset(void)
 {
-	/* Placeholder */
+	struct prog cpucp_dtbs_prog =
+		PROG_INIT(PROG_PAYLOAD, CONFIG_CBFS_PREFIX "/cpucp_dtbs");
+
+	if (!selfload(&cpucp_dtbs_prog))
+		die("SOC image: CPUCP DTBS load failed");
+
+	printk(BIOS_DEBUG, "SOC image: CPUCP DTBS image loaded successfully.\n");
+
+	struct prog cpucp_fw_prog =
+		PROG_INIT(PROG_PAYLOAD, CONFIG_CBFS_PREFIX "/cpucp");
+
+	if (!selfload(&cpucp_fw_prog))
+		die("SOC image: CPUCP load failed");
+
+	printk(BIOS_DEBUG, "SOC image: CPUCP image loaded successfully.\n");
+
+	write32((void *) HWIO_APSS_CPUCP_CPUCP_LPM_SEQ_WAIT_EVT_CTRL_MASK_ADDR, 0x0);
+	setbits32((void *) HWIO_APSS_CPUCP_CPUCP_SW_WAKEUP_REQ_ADDR, 0x1);
 }
diff --git a/src/soc/qualcomm/x1p42100/include/soc/addressmap.h b/src/soc/qualcomm/x1p42100/include/soc/addressmap.h
index e0cc910d44..79e2b782e9 100644
--- a/src/soc/qualcomm/x1p42100/include/soc/addressmap.h
+++ b/src/soc/qualcomm/x1p42100/include/soc/addressmap.h
@@ -15,6 +15,12 @@
 #define NCC0_NCC_CMU_NCC_PLL_CFG	0x199A2010
 #define NCC0_NCC_CMU_NCC_CLK_CFG	0x199A2030
 
+/* CPUCP */
+#define APSS_HM_BASE						0x17000000
+#define APSS_CPUCP_LPM_BFSM_REG_BASE				(APSS_HM_BASE + 0x019d0000)
+#define HWIO_APSS_CPUCP_CPUCP_LPM_SEQ_WAIT_EVT_CTRL_MASK_ADDR	(APSS_CPUCP_LPM_BFSM_REG_BASE + 0x161c)
+#define HWIO_APSS_CPUCP_CPUCP_SW_WAKEUP_REQ_ADDR		(APSS_CPUCP_LPM_BFSM_REG_BASE + 0x1688)
+
 /* X1P42100 QSPI GPIO PINS */
 #define QSPI_CS				GPIO(132)
 #define QSPI_DATA_0			GPIO(128)
diff --git a/src/soc/qualcomm/x1p42100/soc.c b/src/soc/qualcomm/x1p42100/soc.c
index 8066084fee..e8bc4c0996 100644
--- a/src/soc/qualcomm/x1p42100/soc.c
+++ b/src/soc/qualcomm/x1p42100/soc.c
@@ -5,6 +5,7 @@
 #include <soc/mmu_common.h>
 #include <soc/symbols_common.h>
 #include <soc/pcie.h>
+#include <soc/cpucp.h>
 
 static struct device_operations pci_domain_ops = {
 	.read_resources = &qcom_pci_domain_read_resources,
@@ -37,7 +38,7 @@ static void soc_read_resources(struct device *dev)
 
 static void soc_init(struct device *dev)
 {
-	/* placeholder */
+	cpucp_fw_load_reset();
 }
 
 static struct device_operations soc_ops = {

From e7cdf035fb565da370a4fb84d295df592d36a6b0 Mon Sep 17 00:00:00 2001
From: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Date: Thu, 14 Aug 2025 14:33:55 +0800
Subject: [PATCH 1825/3886] mb/google/brox/var/caboc: Enable RTD3 for SSD to
 resolve S0ix issue

Some SSDs block the CPU from reaching PC10 during the S0ix suspend
without the RTD3 configuration. Add PCIe RTD3 support so NVMe gets
placed into D3 state when entering S0ix.

Enable and reset GPIOs are configured as per pin mapping in gpio.c.

Disable GPP_F20 (EN_PP3300_SSD) and GPP_H23 (SRCCLKREQ#5) by fw_config
for Non-SSD sku.

BUG=b:435567235
TEST= emerge-brox coreboot
      suspend_stress_test verify that the device suspends to S0ix.

suspend_stress_test w/o this CL
(with Kioxia PCIE Gen4 SSD KBG60ZNV512G)
  Suspend failed, pc10 count did not increment from 0
  Package C-States Now :
  Package C2 : 26205917
  Package C3 : 0
  Package C6 : 0
  Package C7 : 0
  Package C8 : 0
  Package C9 : 0
  Package C10 : 0
  Substate   Residency
  S0i2.0     0
  S0i3.0     0

suspend_stress_test w/ this CL
  Device suspends to S0ix.
  Substate   Residency
  S0i2.0     0
  S0i3.0     12020538

Change-Id: Iecffa89ae7865bc63b1b0dd974a439f35e9ca7f4
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88771
Reviewed-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com>
Reviewed-by: sridhar siricilla <siricillasridhar@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
---
 src/mainboard/google/brox/variants/caboc/fw_config.c     | 4 ++++
 src/mainboard/google/brox/variants/caboc/gpio.c          | 4 ++++
 src/mainboard/google/brox/variants/caboc/overridetree.cb | 7 +++++++
 3 files changed, 15 insertions(+)

diff --git a/src/mainboard/google/brox/variants/caboc/fw_config.c b/src/mainboard/google/brox/variants/caboc/fw_config.c
index 0f77546624..092c45ba69 100644
--- a/src/mainboard/google/brox/variants/caboc/fw_config.c
+++ b/src/mainboard/google/brox/variants/caboc/fw_config.c
@@ -49,8 +49,12 @@ static const struct pad_config lte_disable_pads[] = {
 static const struct pad_config nvme_disable_pads[] = {
 	/* GPP_F9 : SSD_PERST_L */
 	PAD_NC(GPP_F9, NONE),
+	/* GPP_F20 : EN_PP3300_SSD */
+	PAD_NC(GPP_F20, NONE),
 	/* GPP_D5 : SSD_CLKREQ_ODL */
 	PAD_NC(GPP_D5, NONE),
+	/* GPP_H23 : SSD_CLKREQ5_ODL */
+	PAD_NC(GPP_H23, NONE),
 };
 
 static void fw_config_handle(void *unused)
diff --git a/src/mainboard/google/brox/variants/caboc/gpio.c b/src/mainboard/google/brox/variants/caboc/gpio.c
index c13b80cc02..7a683eacc4 100644
--- a/src/mainboard/google/brox/variants/caboc/gpio.c
+++ b/src/mainboard/google/brox/variants/caboc/gpio.c
@@ -65,6 +65,8 @@ static const struct pad_config override_gpio_table[] = {
 	PAD_CFG_NF_LOCK(GPP_F16, NONE, NF4, LOCK_CONFIG),
 	/* GPP_F19 : SRCCLKREQ6 ==> PCIE_CLKREQ_WWAN */
 	PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1),
+	/* GPP_F20 : [NF1: Reserved NF6: USB_C_GPP_F20] ==> EN_PP3300_SSD */
+	PAD_CFG_GPO(GPP_F20, 1, DEEP),
 	/* F21 : [NF1: Reserved NF6: USB_C_GPP_F21] ==> WWAN_OFF#(WWAN_FCPO_L)*/
 	PAD_CFG_GPO(GPP_F21, 1, DEEP),
 
@@ -100,6 +102,8 @@ static const struct pad_config early_gpio_table[] = {
 	PAD_CFG_GPI_LOCK(GPP_E8, NONE, LOCK_CONFIG),
 	/* GPP_F9 : [NF1: BOOTMPC NF6: USB_C_GPP_F9] ==> SSD_PERST_L */
 	PAD_CFG_GPO(GPP_F9, 0, DEEP),
+	/* GPP_F20 : [NF1: Reserved NF6: USB_C_GPP_F20] ==> EN_PP3300_SSD */
+	PAD_CFG_GPO(GPP_F20, 1, DEEP),
 	/* GPP_H8 : [NF1: I2C4_SDA NF2: CNV_MFUART2_RXD NF6: USB_C_GPP_H8] ==> PCH_I2C_GSC_SDA */
 	PAD_CFG_NF(GPP_H8, NONE, DEEP, NF1),
 	/* GPP_H9 : [NF1: I2C4_SCL NF2: CNV_MFUART2_TXD] ==> PCH_I2C_GSC_SCL */
diff --git a/src/mainboard/google/brox/variants/caboc/overridetree.cb b/src/mainboard/google/brox/variants/caboc/overridetree.cb
index e8be0e8990..575b865205 100644
--- a/src/mainboard/google/brox/variants/caboc/overridetree.cb
+++ b/src/mainboard/google/brox/variants/caboc/overridetree.cb
@@ -251,6 +251,13 @@ chip soc/intel/alderlake
 				.flags = PCIE_RP_LTR | PCIE_RP_AER,
 				.pcie_rp_aspm = ASPM_L1,
 			}"
+			chip soc/intel/common/block/pcie/rtd3
+				register "is_storage" = "true"
+				register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_F20)"
+				register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_F9)"
+				register "srcclk_pin" = "0"
+				device generic 0 on end
+			end
 			probe STORAGE STORAGE_NVME
 			probe unprovisioned
 		end

From dc04ee827b59f4c2831e42fb6f7054976d39c534 Mon Sep 17 00:00:00 2001
From: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Date: Wed, 20 Aug 2025 08:31:25 +0800
Subject: [PATCH 1826/3886] mb/google/fatcat/var/kinmen: Generate SPD ID for
 memory modules

Add 2 memory parts in mem_parts_used.txt, and generate SPD id
for these parts.

1. H58G56CK8BX146 (Hynix)
2. MT62F2G32D4DS-023 WT:C (Micron)

BUG=b:422831379
TEST=Run part_id_gen tool and check the generated files.

Change-Id: Ia6ee285f558a456c423586ccd7e970d14dd3cfea
Signed-off-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88865
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Pranava Y N <pranavayn@google.com>
---
 .../google/fatcat/variants/kinmen/memory/Makefile.mk          | 4 ++--
 .../fatcat/variants/kinmen/memory/dram_id.generated.txt       | 2 ++
 .../google/fatcat/variants/kinmen/memory/mem_parts_used.txt   | 2 ++
 3 files changed, 6 insertions(+), 2 deletions(-)

diff --git a/src/mainboard/google/fatcat/variants/kinmen/memory/Makefile.mk b/src/mainboard/google/fatcat/variants/kinmen/memory/Makefile.mk
index bc3362d843..62885ed4de 100644
--- a/src/mainboard/google/fatcat/variants/kinmen/memory/Makefile.mk
+++ b/src/mainboard/google/fatcat/variants/kinmen/memory/Makefile.mk
@@ -5,5 +5,5 @@
 
 SPD_SOURCES =
 SPD_SOURCES += spd/lp5/set-0/spd-7.hex      # ID = 0(0b0000)  Parts = H58G56BK7BX068
-SPD_SOURCES += spd/lp5/set-0/spd-11.hex      # ID = 1(0b0001)  Parts = MT62F1G32D2DS-023 WT:C
-SPD_SOURCES += spd/lp5/set-0/spd-10.hex      # ID = 2(0b0010)  Parts = MT62F2G32D4DS-020 WT:F
+SPD_SOURCES += spd/lp5/set-0/spd-11.hex      # ID = 1(0b0001)  Parts = MT62F1G32D2DS-023 WT:C, H58G56CK8BX146
+SPD_SOURCES += spd/lp5/set-0/spd-10.hex      # ID = 2(0b0010)  Parts = MT62F2G32D4DS-020 WT:F, MT62F2G32D4DS-023 WT:C
diff --git a/src/mainboard/google/fatcat/variants/kinmen/memory/dram_id.generated.txt b/src/mainboard/google/fatcat/variants/kinmen/memory/dram_id.generated.txt
index 8cfde18141..24ab2ffdaf 100644
--- a/src/mainboard/google/fatcat/variants/kinmen/memory/dram_id.generated.txt
+++ b/src/mainboard/google/fatcat/variants/kinmen/memory/dram_id.generated.txt
@@ -7,3 +7,5 @@ DRAM Part Name                 ID to assign
 H58G56BK7BX068                 0 (0000)
 MT62F1G32D2DS-023 WT:C         1 (0001)
 MT62F2G32D4DS-020 WT:F         2 (0010)
+H58G56CK8BX146                 1 (0001)
+MT62F2G32D4DS-023 WT:C         2 (0010)
diff --git a/src/mainboard/google/fatcat/variants/kinmen/memory/mem_parts_used.txt b/src/mainboard/google/fatcat/variants/kinmen/memory/mem_parts_used.txt
index 5ab8b585a3..f4a5069bb5 100644
--- a/src/mainboard/google/fatcat/variants/kinmen/memory/mem_parts_used.txt
+++ b/src/mainboard/google/fatcat/variants/kinmen/memory/mem_parts_used.txt
@@ -12,3 +12,5 @@
 H58G56BK7BX068
 MT62F1G32D2DS-023 WT:C
 MT62F2G32D4DS-020 WT:F
+H58G56CK8BX146
+MT62F2G32D4DS-023 WT:C

From a484a6529c61d5c750a1e91d0f876bb91d81e553 Mon Sep 17 00:00:00 2001
From: Swathi Tamilselvan <tswathi@qualcomm.corp-partner.google.com>
Date: Wed, 20 Aug 2025 15:12:26 +0530
Subject: [PATCH 1827/3886] soc/qualcomm/common/qclib: Support to declare
 cpr_settings region

CPR image is required by Qclib for PMIC initialization. This patch
adds support to declare cpr_settings region and create CBFS prefix
for CPR.

Change-Id: Ia92717715eacaf05d33db040d99cf81d8d288111
Signed-off-by: Swathi Tamilselvan <tswathi@qualcomm.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88869
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
---
 src/soc/qualcomm/common/include/soc/qclib_common.h   | 2 ++
 src/soc/qualcomm/common/include/soc/symbols_common.h | 1 +
 src/soc/qualcomm/common/qclib.c                      | 2 ++
 3 files changed, 5 insertions(+)

diff --git a/src/soc/qualcomm/common/include/soc/qclib_common.h b/src/soc/qualcomm/common/include/soc/qclib_common.h
index 9f5ee52bfc..e05663bae1 100644
--- a/src/soc/qualcomm/common/include/soc/qclib_common.h
+++ b/src/soc/qualcomm/common/include/soc/qclib_common.h
@@ -24,6 +24,7 @@
 #define QCLIB_TE_QCSDI             "qcsdi"
 #define QCLIB_TE_MEM_CHIP_INFO     "mem_chip_info"
 #define QCLIB_TE_DTB_SETTINGS      "dtb"
+#define QCLIB_TE_CPR_SETTINGS	   "cpr_settings"
 #define QCLIB_TE_SHRM_META_SETTINGS	"shrm_metadata"
 #define QCLIB_TE_AOP_META_SETTINGS      "aop_metadata"
 #define QCLIB_TE_AOP_DEVCFG_META_SETTINGS	"aop_cfg_metadata"
@@ -37,6 +38,7 @@ enum qclib_cbfs_file {
 	QCLIB_CBFS_QCLIB,
 	QCLIB_CBFS_DCB,
 	QCLIB_CBFS_DTB,
+	QCLIB_CBFS_CPR,
 	QCLIB_CBFS_SHRM_META,
 	QCLIB_CBFS_AOP_META,
 	QCLIB_CBFS_AOP_DEVCFG_META,
diff --git a/src/soc/qualcomm/common/include/soc/symbols_common.h b/src/soc/qualcomm/common/include/soc/symbols_common.h
index 10a4e41298..bdd4be5979 100644
--- a/src/soc/qualcomm/common/include/soc/symbols_common.h
+++ b/src/soc/qualcomm/common/include/soc/symbols_common.h
@@ -14,6 +14,7 @@ DECLARE_REGION(dram_aop)
 DECLARE_REGION(dram_soc)
 DECLARE_REGION(dcb)
 DECLARE_REGION(dtb)
+DECLARE_REGION(cpr_settings)
 DECLARE_REGION(qc_blob_meta)
 DECLARE_REGION(aop_blob_meta)
 DECLARE_OPTIONAL_REGION(pmic)
diff --git a/src/soc/qualcomm/common/qclib.c b/src/soc/qualcomm/common/qclib.c
index e2b5ac00cc..cb694e356d 100644
--- a/src/soc/qualcomm/common/qclib.c
+++ b/src/soc/qualcomm/common/qclib.c
@@ -84,6 +84,8 @@ const char *qclib_file_default(enum qclib_cbfs_file file)
 		return CONFIG_CBFS_PREFIX "/dcb";
 	case QCLIB_CBFS_DTB:
 		return CONFIG_CBFS_PREFIX "/dtb";
+	case QCLIB_CBFS_CPR:
+		return CONFIG_CBFS_PREFIX "/cpr";
 	case QCLIB_CBFS_SHRM_META:
 		return CONFIG_CBFS_PREFIX "/shrm_meta";
 	case QCLIB_CBFS_AOP_META:

From 8d2df573a8d2e4821136a88295c062c37195115e Mon Sep 17 00:00:00 2001
From: Swathi Tamilselvan <tswathi@qualcomm.corp-partner.google.com>
Date: Wed, 20 Aug 2025 14:59:35 +0530
Subject: [PATCH 1828/3886] soc/qualcomm/x1p42100/qclib: Support to pack and
 load CPR binary in CBFS

CPR image is required by Qclib for PMIC initialization. This patch adds
support to pack and load the CPR binary, reserves memory for CPR
settings in the memory layout and adds CPR entry in if_table which
is passed to Qclib.

TEST=1. Create an image.serial.bin and ensure it boots on X1P42100.
2. Verified using CPR load log from coreboot.
```
[INFO ]  CBFS: Found 'fallback/cpr' @0xa3900 size 0x46d in mcache
		@0x1485e340
[INFO ]  VB2:vb2_secdata_kernel_get() VB2_SECDATA_KERNEL_FLAGS not
		supported for secdata_kernel v0, return 0
[INFO ]  VB2:vb2_digest_init() 1133 bytes, hash algo 2, HW acceleration
		forbidden
[INFO ]  CBFS: Found 'fallback/shrm_meta' @0xebb80 size 0xb0d in mcache
		@0x1485e7c0
```

Change-Id: I58161a1d05222c84e077ada1024db50440e783f1
Signed-off-by: Swathi Tamilselvan <tswathi@qualcomm.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88870
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/soc/qualcomm/x1p42100/Makefile.mk  | 8 ++++++++
 src/soc/qualcomm/x1p42100/memlayout.ld | 1 +
 src/soc/qualcomm/x1p42100/qclib.c      | 8 ++++++++
 3 files changed, 17 insertions(+)

diff --git a/src/soc/qualcomm/x1p42100/Makefile.mk b/src/soc/qualcomm/x1p42100/Makefile.mk
index 36d2578cf5..c483b5f691 100644
--- a/src/soc/qualcomm/x1p42100/Makefile.mk
+++ b/src/soc/qualcomm/x1p42100/Makefile.mk
@@ -120,6 +120,14 @@ $(DTB_CBFS)-type := raw
 $(DTB_CBFS)-compression := $(CBFS_COMPRESS_FLAG)
 cbfs-files-y += $(DTB_CBFS)
 
+################################################################################
+CPR_FILE := $(X1P42100_BLOB)/boot/$(DTB_DCB_BLOB_PATH)/cpr.bin
+CPR_CBFS := $(CONFIG_CBFS_PREFIX)/cpr
+$(CPR_CBFS)-file := $(CPR_FILE)
+$(CPR_CBFS)-type := raw
+$(CPR_CBFS)-compression := $(CBFS_PRERAM_COMPRESS_FLAG)
+cbfs-files-y += $(CPR_CBFS)
+
 ################################################################################
 UART_FW_FILE := $(X1P42100_BLOB)/qup_fw/uart_fw.bin
 UART_FW_CBFS := $(CONFIG_CBFS_PREFIX)/uart_fw
diff --git a/src/soc/qualcomm/x1p42100/memlayout.ld b/src/soc/qualcomm/x1p42100/memlayout.ld
index 4154534f2b..b543c51c1e 100644
--- a/src/soc/qualcomm/x1p42100/memlayout.ld
+++ b/src/soc/qualcomm/x1p42100/memlayout.ld
@@ -36,6 +36,7 @@ SECTIONS
 	REGION(qc_blob_meta, 0x14888000, 16K, 4K)
 	REGION(aop_blob_meta, 0x1488c000, 16K, 4K)
 	REGION(qclib, 0x14897000, 1536K, 4K)
+	REGION(cpr_settings, 0x14A17000, 12K, 4K)
 	PRERAM_CBMEM_CONSOLE(0x14A30000, 32K)
 	OVERLAP_DECOMPRESSOR_VERSTAGE_ROMSTAGE(0x14A38000, 132K)
 	REGION(auth_metadata,0x14A7D000 , 8K, 4K)
diff --git a/src/soc/qualcomm/x1p42100/qclib.c b/src/soc/qualcomm/x1p42100/qclib.c
index 961f822a4f..ea1424c402 100644
--- a/src/soc/qualcomm/x1p42100/qclib.c
+++ b/src/soc/qualcomm/x1p42100/qclib.c
@@ -19,6 +19,14 @@ int qclib_soc_override(struct qclib_cb_if_table *table)
 	}
 	qclib_add_if_table_entry(QCLIB_TE_DTB_SETTINGS, _dtb, data_size, 0);
 
+	/* Attempt to load CPR Blob */
+	data_size = cbfs_load(qclib_file(QCLIB_CBFS_CPR), _cpr_settings, REGION_SIZE(cpr_settings));
+	if (!data_size) {
+		printk(BIOS_ERR, "[%s] /cpr failed\n", __func__);
+		return -1;
+	}
+	qclib_add_if_table_entry(QCLIB_TE_CPR_SETTINGS, _cpr_settings, data_size, 0);
+
 	/* Attempt to load shrm_meta Blob */
 	data_size = cbfs_load(qclib_file(QCLIB_CBFS_SHRM_META),
 			_qc_blob_meta, REGION_SIZE(qc_blob_meta));

From 9999a4aebb81587aa25342af6e56e7e5f0fb1fc2 Mon Sep 17 00:00:00 2001
From: Zhongtian Wu <wuzhongtian@huaqin.corp-partner.google.com>
Date: Thu, 21 Aug 2025 16:44:03 +0800
Subject: [PATCH 1829/3886] mb/google/nissa/var/pujjocento: Change touchscreen
 properties

Disabling fw splash caused touchscreen malfunctions.
Removing stop_delay_ms restored touchscreen functionality.
This modification reduces reset->i2c communication time
(before: 580ms; after: 300ms).

BUG=b:431870029,b:431870484
BRANCH=none
TEST=Build and boot to pujjocento. Verify touchpanel sequence

Change-Id: I838390f003d71bc63af0613ecf72515487a70492
Signed-off-by: Zhongtian Wu <wuzhongtian@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88878
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kun Liu <liukun11@huaqin.corp-partner.google.com>
---
 src/mainboard/google/brya/variants/pujjocento/overridetree.cb | 1 -
 1 file changed, 1 deletion(-)

diff --git a/src/mainboard/google/brya/variants/pujjocento/overridetree.cb b/src/mainboard/google/brya/variants/pujjocento/overridetree.cb
index 961ffa86bd..a648520a43 100644
--- a/src/mainboard/google/brya/variants/pujjocento/overridetree.cb
+++ b/src/mainboard/google/brya/variants/pujjocento/overridetree.cb
@@ -548,7 +548,6 @@ chip soc/intel/alderlake
 				register "generic.reset_delay_ms" = "20"
 				register "generic.reset_off_delay_ms" = "2"
 				register "generic.stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C4)"
-				register "generic.stop_delay_ms" = "280"
 				register "generic.stop_off_delay_ms" = "2"
 				register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C0)"
 				register "generic.enable_delay_ms" = "1"

From 51a8e238b06c333337452dbc8c50118ad13efee6 Mon Sep 17 00:00:00 2001
From: Subrata Banik <subratabanik@google.com>
Date: Fri, 22 Aug 2025 00:59:01 +0530
Subject: [PATCH 1830/3886] lib: Correct logo bottom margin handling for all
 panel orientations

This patch fixes a bug in load_and_render_logo_to_framebuffer where the
logo_bottom_margin was only correctly applied to the NORMAL
orientations.

For other orientations, the margin was incorrectly applied, resulting
in the logo not being positioned as expected.

TEST=Able to see logo footer in alignment with the logo center while
booting google/felino.

Change-Id: Ia886ef5305166b1307fcf5b0acd12582b4b6ad80
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88889
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
---
 src/lib/render_bmp.c | 17 +++++++++++++----
 1 file changed, 13 insertions(+), 4 deletions(-)

diff --git a/src/lib/render_bmp.c b/src/lib/render_bmp.c
index 7dc808b13c..3a7e245eca 100644
--- a/src/lib/render_bmp.c
+++ b/src/lib/render_bmp.c
@@ -651,11 +651,20 @@ static int load_and_render_logo_to_framebuffer(
 		 config->vertical_resolution, logo_width, logo_height, halignment, valignment);
 
 	if (logo_bottom_margin) {
-		if (config->panel_orientation == LB_FB_ORIENTATION_BOTTOM_UP ||
-				 config->panel_orientation == LB_FB_ORIENTATION_NORMAL)
-			logo_coords.y -= logo_bottom_margin;
-		else
+		switch (config->panel_orientation) {
+		case LB_FB_ORIENTATION_RIGHT_UP:
+			logo_coords.x = logo_bottom_margin;
+			break;
+		case LB_FB_ORIENTATION_LEFT_UP:
 			logo_coords.x -= logo_bottom_margin;
+			break;
+		case LB_FB_ORIENTATION_BOTTOM_UP:
+			logo_coords.y = logo_bottom_margin;
+			break;
+		default: /* LB_FB_ORIENTATION_NORMAL (default) */
+			logo_coords.y -= logo_bottom_margin;
+			break;
+		}
 	}
 
 	copy_logo_to_framebuffer(config->framebuffer_base, config->bytes_per_scanline, blt_buffer,

From bdee19ba8724358de4e55d2cbca4b6736ffd90f2 Mon Sep 17 00:00:00 2001
From: Subrata Banik <subratabanik@google.com>
Date: Fri, 15 Aug 2025 14:47:22 +0530
Subject: [PATCH 1831/3886] soc/qualcomm/x1p42100: Add ASCII memory map diagram
 to memlayout.ld

The memlayout.ld for X1P42100 was copied from a previous SoC and
lacked clear documentation about the platform's specific memory
organization.

This commit adds a detailed ASCII art diagram that provides a visual
representation of the complete memory map. The diagram clarifies the
locations of all major regions, such as AOPSRAM, SSRAM, BSRAM, SHRM,
and the various DRAM segments, which greatly improves the clarity and
maintainability of the linker script.

TEST=Builds successfully for x1p42100.

Change-Id: Ia1714f8da25a22a13f5960d056df33463dd99f31
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88783
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/soc/qualcomm/x1p42100/memlayout.ld | 133 +++++++++++++++++++++++++
 1 file changed, 133 insertions(+)

diff --git a/src/soc/qualcomm/x1p42100/memlayout.ld b/src/soc/qualcomm/x1p42100/memlayout.ld
index b543c51c1e..2a9ac452d3 100644
--- a/src/soc/qualcomm/x1p42100/memlayout.ld
+++ b/src/soc/qualcomm/x1p42100/memlayout.ld
@@ -4,6 +4,139 @@
 #include <arch/header.ld>
 #include <soc/memlayout.h>
 
+
+/*
+ * The linker script below configures the memory layout for the Qualcomm X1P42100 SoC.
+ *
+ * The memory map and addressing scheme are implemented according to the official Qualcomm
+ * Hardware Reference Document (HRD) for this specific SoC.
+ *
+ * 0x10000000000 +----------------------------------------------------------+ <--------------
+ *               |                      dram_space_2                        | DRAM Space 2  ^
+ * 0x8800000000  +----------------------------------------------------------+ <---------    |
+ *               |         ... (Memory not mapped: Unavailable) ...         |  XXXXXXXXX    |
+ * 0x1000000000  +----------------------------------------------------------+ <---------    |
+ *               |                      dram_space_1                        | DRAM Space 1  |
+ * 0x880000000   +----------------------------------------------------------+ <---------    |
+ *               |         ... (Memory not mapped: Unavailable) ...         |  XXXXXXXXX    |
+ * 0x100000000   +----------------------------------------------------------+ <---------    |
+ *               |                 dram_smem (Shared Memory)                |      ^        |
+ * 0xFF800000    +----------------------------------------------------------+      |        |
+ *               |                        CBMEM                             |      |        |
+ *               +----------------------------------------------------------+      |        |
+ *               |                ... Usable memory ...                     |      |        |
+ * 0xDF4C0000    +----------------------------------------------------------+      |        |
+ *               |               dram_tz_rem (TrustZone Remainder)          |      |        |
+ * 0xD81D6000    +----------------------------------------------------------+      |        |
+ *               |                 BL31 (ARM Trusted Firmware)              |      |        |
+ * 0xD80D6000    +----------------------------------------------------------+      |        |
+ *               |                  dram_tz (TrustZone)                     |      |        |
+ * 0xD8000000    +----------------------------------------------------------+      |      DRAM
+ *               |               ... Usable memory ...                      |      |        |
+ * 0xD7800000    +----------------------------------------------------------+      |        |
+ *               |                 Linux Kernel Reserve                     |      |        |
+ * 0xC7800000    +----------------------------------------------------------+      |        |
+ *               |                ... Usable memory ...                     |      |        |
+ * 0xA1800000    +----------------------------------------------------------+      |        |
+ *               |                      RAMSTAGE                            | DRAM Space 0  |
+ * 0xA0800000    +----------------------------------------------------------+      |        |
+ *               |                 POSTRAM_CBFS_CACHE                       |      |        |
+ * 0x9F800000    +----------------------------------------------------------+      |        |
+ *               |                ... Usable memory ...                     |      |        |
+ * 0x91380000    +----------------------------------------------------------+      |        |
+ *               |                       dram_aop                           |      |        |
+ * 0x81C00000    +----------------------------------------------------------+      |        |
+ *               |                     dram_ramdump                         |      |        |
+ * 0x81A00000    +----------------------------------------------------------+      |        |
+ *               |                ... Usable memory ...                     |      |        |
+ * 0x815A0000    +----------------------------------------------------------+      |        |
+ *               |                      dram_cpucp                          |      |        |
+ * 0x80A00000    +----------------------------------------------------------+      |        |
+ *               |                ... Usable memory ...                     |      v        v
+ * 0x80000000    +----------------------------------------------------------+ <--------------
+ *               |         ... (Memory not mapped: Unavailable) ...         | XXXXXXXXX
+ * 0x24060000    +----------------------------------------------------------+ <---------
+ *               |                         shrm                             |    SHRM
+ * 0x24040000    +----------------------------------------------------------+ <---------
+ *               |         ... (Memory not mapped: Unavailable) ...         | XXXXXXXXX
+ * 0x14A80000    +----------------------------------------------------------+ <---------
+ *               |                     debug_policy                         |      ^
+ * 0x14A7F000    +----------------------------------------------------------+      |
+ *               |                    auth_metadata                         |      |
+ * 0x14A7D000    +----------------------------------------------------------+      |
+ *               |                ... Usable memory ...                     |      |
+ * 0x14A59000    +----------------------------------------------------------+      |
+ *               |         OVERLAP_DECOMPRESSOR_VERSTAGE_ROMSTAGE           |      |
+ * 0x14A38000    +----------------------------------------------------------+      |
+ *               |                 PRERAM_CBMEM_CONSOLE                     |      |
+ * 0x14A30000    +----------------------------------------------------------+      |
+ *               |                ... Usable memory ...                     |      |
+ * 0x14A1A000    +----------------------------------------------------------+      |
+ *               |                        CPR                               |      |
+ * 0x14A17000    +----------------------------------------------------------+      |
+ *               |                       qclib                              |      |
+ * 0x14897000    +----------------------------------------------------------+      |
+ *               |                ... Usable memory ...                     |      |
+ * 0x1488C000    +----------------------------------------------------------+      |
+ *               |                    qc_blob_meta                          |      |
+ * 0x14888000    +----------------------------------------------------------+      |
+ *               |                    ddr_training                          |      |
+ * 0x14878000    +----------------------------------------------------------+      |
+ *               |               dtb (Device Tree Blob)                     |      |
+ * 0x14870000    +----------------------------------------------------------+      |
+ *               |                dcb (DDR Config Block)                    |      |
+ * 0x14862000    +----------------------------------------------------------+      |
+ *               |                ... Usable memory ...                     |      |
+ * 0x14860C00    +----------------------------------------------------------+      |
+ *               |                     FMAP_CACHE                           |      |
+ * 0x14860400    +----------------------------------------------------------+      |
+ *               |                   ddr_information                        |      |
+ * 0x14860000    +----------------------------------------------------------+    BSRAM
+ *               |                    CBFS_MCACHE                           |      |
+ * 0x1485C000    +----------------------------------------------------------+      |
+ *               |                  qclib_serial_log                        |      |
+ * 0x1485B000    +----------------------------------------------------------+      |
+ *               |                ... Usable memory ...                     |      |
+ * 0x14859000    +----------------------------------------------------------+      |
+ *               |                    DMA_COHERENT                          |      |
+ * 0x14857000    +----------------------------------------------------------+      |
+ *               |                    VBOOT2_WORK                           |      |
+ * 0x14854000    +----------------------------------------------------------+      |
+ *               |                       STACK                              |      |
+ * 0x14850000    +----------------------------------------------------------+      |
+ *               |             TTB (Translation Table Base)                 |      |
+ * 0x14842000    +----------------------------------------------------------+      |
+ *               |                     TIMESTAMP                            |      |
+ * 0x14841C00    +----------------------------------------------------------+      |
+ *               |                 PRERAM_CBFS_CACHE                        |      |
+ * 0x14828000    +----------------------------------------------------------+      |
+ *               |                     BOOTBLOCK                            |      |
+ * 0x14819000    +----------------------------------------------------------+      |
+ *               |                 WATCHDOG_TOMBSTONE                       |      |
+ * 0x14818FFC    +----------------------------------------------------------+      |
+ *               |                ... Usable memory ...                     |      |
+ * 0x14815000    +----------------------------------------------------------+      |
+ *               |                   pbl_timestamps                         |      v
+ * 0x14800000    +----------------------------------------------------------+ <---------
+ *               |              ... (Large Address Gap) ...                 |
+ * 0x146AB000    +----------------------------------------------------------+ <---------
+ *               |                     shared_imem                          |      ^
+ * 0x146A8000    +----------------------------------------------------------+      |
+ *               |                ... Usable memory ...                     |    SSRAM
+ * 0x146A5000    +----------------------------------------------------------+      |
+ *               |                       qcsdi                              |      v
+ * 0x14699000    +----------------------------------------------------------+ <---------
+ *               |         ... (Memory not mapped: Unavailable) ...         | XXXXXXXXX
+ * 0x0B100000    +----------------------------------------------------------+ <---------
+ *               |                    aop_data_ram                          |      ^
+ * 0x0B0E0000    +----------------------------------------------------------+      |
+ *               |                ... Usable memory ...                     |   AOP SRAM
+ * 0x0B080000    +----------------------------------------------------------+      |
+ *               |                    aop_code_ram                          |      v
+ * 0x0B000000    +----------------------------------------------------------+ <---------
+ *
+ */
+
 SECTIONS
 {
 	AOPSRAM_START(0x0B000000)

From de98da43fa41d3518a62374fb50bcdb4be9c3dee Mon Sep 17 00:00:00 2001
From: Felix Singer <felixsinger@posteo.net>
Date: Fri, 22 Aug 2025 23:54:41 +0000
Subject: [PATCH 1832/3886] 3rdparty/intel-microcode: Update to upstream main

Updating from commit id eeb93b7a818b:
2025-05-12 11:40:14 -0600 - (microcode-20250512 Release)

to commit id 4ded52b4b0e1:
2025-08-11 17:00:18 -0600 - (microcode-20250812 Release)

This brings in 1 new commits:
4ded52b4b0e1 microcode-20250812 Release

Change-Id: I869a8d707ff54aa93518d3bac40d7d471e663bd5
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88911
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
---
 3rdparty/intel-microcode | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/3rdparty/intel-microcode b/3rdparty/intel-microcode
index eeb93b7a81..4ded52b4b0 160000
--- a/3rdparty/intel-microcode
+++ b/3rdparty/intel-microcode
@@ -1 +1 @@
-Subproject commit eeb93b7a818bb27cb6b7a2be0454f8a0a75f1bd6
+Subproject commit 4ded52b4b0e1d60e83259cc88d1f5ad22f71a63e

From 4a6a0de02937b4478097e5c555852fe2c5539532 Mon Sep 17 00:00:00 2001
From: Felix Singer <felixsinger@posteo.net>
Date: Fri, 22 Aug 2025 23:55:16 +0000
Subject: [PATCH 1833/3886] 3rdparty/fsp: Update to upstream master

Updating from commit id cc36ae2b5775:
2025-05-28 10:49:43 +0800 - (Edge Platforms RPL-S/RPL-S Refresh IPU 2025.3 (6073_04) FSP)

to commit id 9623d524500c:
2025-08-21 11:29:54 -0700 - (BirchStream FSP (0041D92))

This brings in 21 new commits:
9623d524500c BirchStream FSP (0041D92)
b7098dda5432 Edge Platforms RPL-S/RPL-S Refresh IPU 2025.4 (6074_00) FSP
2041cc51bc13 Edge Platforms RPL-P IPU 2025.4 (6074_00) FSP
f0b6387ff36d Edge Platforms ADL-PS IPU 2025.4 (6074_01) FSP
65d94a063083 Edge Platforms ADL-S IPU 2025.4 (6074_00) FSP
94d6d59e8c55 Edge Platforms ADL-P IPU 2025.4 (6074_00) FSP
fdf1b314e645 Merge branch 'master' of https://github.com/intel/FSP
0a2a0a885fb5 Edge Platforms RPL-PS IPU2025.4 (6074_01) FSP
5446654ac8c9 CedarIslandFspBinPkg: Fix warnings when building with GCC
fcaccc628262 ECG BTL-S Hybrid MR1 (6073_02) FSP
7d1f30bbc86a ECG BTL-S Hybrid MR1 (6073_02) FSP
da161ac1fa54 ECG BTL-S Hybrid MR1 (6073_02) FSP
a71309861345 ECG ARL-UH MR1 (5124_47) FSP
b05a45da7198 ECG ARL-S MR1 (5124_46) FSP
3a98ea9c8bb3 ECG ARL-S MR1 (5124_46) FSP
9c289110ee1a AZB IPU 2025.4 (6251_01) FSP
570ac0f5fa03 Edge Platforms MTL-UH_MTL-PS MR3 (5124_47) FSP
8681dceeca0f Edge Platforms TGL-UP3/H IPU 2025.3 (8063_02) FSP
70df3004b137 IoT RPL-PS MR2 (5276_01) FSP
4ab112d1df66 IPU2025.3
15848ee4934a IoT ADL-N IPU25.3 (6114_00)

Change-Id: I9858f4460de1d75ebb858c42d0767f17aa346ecd
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88912
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
---
 3rdparty/fsp | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/3rdparty/fsp b/3rdparty/fsp
index cc36ae2b57..9623d52450 160000
--- a/3rdparty/fsp
+++ b/3rdparty/fsp
@@ -1 +1 @@
-Subproject commit cc36ae2b5775fa7400cb3282680afc0f6cb37a3c
+Subproject commit 9623d524500c140a6b11d2c727cb282b54962f09

From 5f7b5fcb198dfdea45db8505c18ff09445597471 Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Fri, 15 Aug 2025 12:13:32 +0100
Subject: [PATCH 1834/3886] mb/starlabs/byte: Lower the PL4 value to 65W

This should be 65W to match the standard 65W GaN chargers.

Change-Id: I9a2be32b3b377090694cf23c4a4b85db47108c48
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88784
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/starlabs/byte_adl/Kconfig | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/mainboard/starlabs/byte_adl/Kconfig b/src/mainboard/starlabs/byte_adl/Kconfig
index cb1b21953d..28aa10a108 100644
--- a/src/mainboard/starlabs/byte_adl/Kconfig
+++ b/src/mainboard/starlabs/byte_adl/Kconfig
@@ -89,7 +89,7 @@ config ME_BIN_PATH
 
 config PL4_WATTS
 	int
-	default 84 if BOARD_STARLABS_BYTE_TWL
+	default 65 if BOARD_STARLABS_BYTE_TWL
 	default 36
 
 config POWER_STATE_DEFAULT_ON_AFTER_FAILURE

From 850979800641a7ebab6d0f137bb6961755e23ba1 Mon Sep 17 00:00:00 2001
From: Patrick Rudolph <patrick.rudolph@9elements.com>
Date: Sun, 17 Aug 2025 14:51:14 +0200
Subject: [PATCH 1835/3886] sb/intel/common/smbus: Use proper delay instruction

Use udelay() over reading port 80h to delay CPU operation.

Since SMBUS runs at 100Khz a typical operation takes about
200usec or more to complete. Using udelay(1) doesn't delay
the boot for too long.

TEST=Booted on Lenovo X220. No additional boot delay was found.

Change-Id: Ied745927b1c54b53d7450b8e0c0a03d648a3ebba
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88810
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/southbridge/intel/common/smbus.c | 12 ++++--------
 1 file changed, 4 insertions(+), 8 deletions(-)

diff --git a/src/southbridge/intel/common/smbus.c b/src/southbridge/intel/common/smbus.c
index 944e360a0f..57325f7063 100644
--- a/src/southbridge/intel/common/smbus.c
+++ b/src/southbridge/intel/common/smbus.c
@@ -2,6 +2,7 @@
 
 #include <arch/io.h>
 #include <console/console.h>
+#include <delay.h>
 #include <device/smbus_def.h>
 #include <device/smbus_host.h>
 #include <types.h>
@@ -66,11 +67,6 @@
 #define BLOCK_WRITE	(1 << 0)
 #define BLOCK_I2C	(1 << 1)
 
-static void smbus_delay(void)
-{
-	inb(0x80);
-}
-
 static void host_outb(uintptr_t base, u8 reg, u8 value)
 {
 	outb(value, base + reg);
@@ -142,7 +138,7 @@ static int setup_command(uintptr_t base, u8 ctrl, u8 xmitadd)
 	u8 host_busy;
 
 	do {
-		smbus_delay();
+		udelay(1);
 		host_busy = host_inb(base, SMBHSTSTAT) & SMBHSTSTS_HOST_BUSY;
 	} while (--loops && host_busy);
 
@@ -172,7 +168,7 @@ static int execute_command(uintptr_t base)
 
 	/* Poll for it to start. */
 	do {
-		smbus_delay();
+		udelay(1);
 
 		/* If we poll too slow, we could miss HOST_BUSY flag
 		 * set and detect INTR or x_ERR flags instead here.
@@ -194,7 +190,7 @@ static int complete_command(uintptr_t base)
 	u8 status;
 
 	do {
-		smbus_delay();
+		udelay(1);
 		status = host_inb(base, SMBHSTSTAT);
 	} while (--loops && !host_completed(status));
 

From 42a5c189b24b6648253ea61a5c31fc19023beef3 Mon Sep 17 00:00:00 2001
From: Patrick Rudolph <patrick.rudolph@9elements.com>
Date: Fri, 22 Aug 2025 08:14:45 +0200
Subject: [PATCH 1836/3886] mb/lenovo/X220: Add CFR support

TEST=Booted on Lenovo X220 and found the UEFI menu working.

Change-Id: I194ff7b663c092c90882de4e7408b4c1e907984e
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88903
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
---
 src/mainboard/lenovo/x220/Makefile.mk |  2 +
 src/mainboard/lenovo/x220/cfr.c       | 58 +++++++++++++++++++++++++++
 2 files changed, 60 insertions(+)
 create mode 100644 src/mainboard/lenovo/x220/cfr.c

diff --git a/src/mainboard/lenovo/x220/Makefile.mk b/src/mainboard/lenovo/x220/Makefile.mk
index 7e59707915..8629040434 100644
--- a/src/mainboard/lenovo/x220/Makefile.mk
+++ b/src/mainboard/lenovo/x220/Makefile.mk
@@ -3,6 +3,8 @@
 bootblock-y += variants/$(VARIANT_DIR)/gpio.c
 romstage-y += variants/$(VARIANT_DIR)/gpio.c
 
+ramstage-$(CONFIG_DRIVERS_OPTION_CFR) += cfr.c
+
 ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads
 bootblock-y += early_init.c
 romstage-y += early_init.c
diff --git a/src/mainboard/lenovo/x220/cfr.c b/src/mainboard/lenovo/x220/cfr.c
new file mode 100644
index 0000000000..6d43c17856
--- /dev/null
+++ b/src/mainboard/lenovo/x220/cfr.c
@@ -0,0 +1,58 @@
+
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <boot/coreboot_tables.h>
+#include <drivers/option/cfr_frontend.h>
+#include <ec/lenovo/h8/cfr.h>
+#include <ec/lenovo/pmh7/cfr.h>
+#include <northbridge/intel/sandybridge/cfr.h>
+#include <southbridge/intel/bd82x6x/cfr.h>
+
+static struct sm_obj_form ec = {
+	.ui_name = "Embedded Controller",
+	.obj_list = (const struct sm_object *[]) {
+		&bluetooth,
+		&usb_always_on,
+		&wlan,
+		&wwan,
+		&pm_beeps,
+		&battery_beep,
+		&fn_ctrl_swap,
+		&sticky_fn,
+		&f1_to_f12_as_primary,
+		&touchpad,
+		&trackpoint,
+		NULL
+	},
+};
+
+static struct sm_obj_form system = {
+	.ui_name = "System",
+	.obj_list = (const struct sm_object *[]) {
+		&gfx_uma_size,
+		&me_state,
+		&nmi,
+		&sata_mode,
+		NULL
+	},
+};
+
+static struct sm_obj_form power = {
+	.ui_name = "Power",
+	.obj_list = (const struct sm_object *[]) {
+		&power_on_after_fail,
+		NULL
+	},
+};
+
+static struct sm_obj_form *sm_root[] = {
+	&system,
+	&power,
+	&ec,
+	NULL
+};
+
+void mb_cfr_setup_menu(struct lb_cfr *cfr_root)
+{
+	cfr_write_setup_menu(cfr_root, sm_root);
+}

From 36624072a692cff6c5609686d256816e47cef43b Mon Sep 17 00:00:00 2001
From: Luca Lai <luca.lai@lcfc.corp-partner.google.com>
Date: Tue, 19 Aug 2025 16:12:22 +0800
Subject: [PATCH 1837/3886] mb/google/trulo/var/pujjolo: Update wlan rtd3
 settings

Correct srcclk pin setting.

BUG=b:422600523
TEST=Build and boot to OS, check suspend funtion work fine using
suspend_stress_test -c 5 command.

Change-Id: I15e56f124de8b89a6a7f042128fc09fa8c613fc7
Signed-off-by: Luca Lai <luca.lai@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88857
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/google/brya/variants/pujjolo/overridetree.cb | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/mainboard/google/brya/variants/pujjolo/overridetree.cb b/src/mainboard/google/brya/variants/pujjolo/overridetree.cb
index d9cd5cb22c..7e009e001f 100644
--- a/src/mainboard/google/brya/variants/pujjolo/overridetree.cb
+++ b/src/mainboard/google/brya/variants/pujjolo/overridetree.cb
@@ -555,7 +555,7 @@ chip soc/intel/alderlake
 			chip soc/intel/common/block/pcie/rtd3
 				register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E10)"
 				register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_H20)"
-				register "srcclk_pin" = "3"
+				register "srcclk_pin" = "2"
 				device generic 0 on end
 			end
 		end

From 7d573335291bb65431b90011835a44169ec716f7 Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Thu, 21 Aug 2025 21:00:22 +0100
Subject: [PATCH 1838/3886] ec/starlabs/merlin: Add a "off" mode for the power
 LED

Users have requested to be able to disable the power LED, so add
this as an option.

Change-Id: I74da148c7891ab3dd5e5b692239670c9937ab302
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88890
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/ec/starlabs/merlin/cfr.h | 1 +
 src/ec/starlabs/merlin/ec.h  | 1 +
 src/ec/starlabs/merlin/ite.c | 5 +++--
 3 files changed, 5 insertions(+), 2 deletions(-)

diff --git a/src/ec/starlabs/merlin/cfr.h b/src/ec/starlabs/merlin/cfr.h
index b56e7d2e52..f53ec5fa4c 100644
--- a/src/ec/starlabs/merlin/cfr.h
+++ b/src/ec/starlabs/merlin/cfr.h
@@ -109,6 +109,7 @@ static const struct sm_object power_led = SM_DECLARE_ENUM({
 	.values		= (const struct sm_enum_value[]) {
 				{ "Normal",		0		},
 				{ "Reduced",		1		},
+				{ "Off",		2		},
 				SM_ENUM_VALUE_END,
 	},
 });
diff --git a/src/ec/starlabs/merlin/ec.h b/src/ec/starlabs/merlin/ec.h
index 82572bde73..4b6b791771 100644
--- a/src/ec/starlabs/merlin/ec.h
+++ b/src/ec/starlabs/merlin/ec.h
@@ -111,6 +111,7 @@
 /* Power LED Brightness */
 #define LED_NORMAL		0x00
 #define LED_REDUCED		0x01
+#define LED_OFF			0x02
 
 uint16_t ec_get_version(void);
 
diff --git a/src/ec/starlabs/merlin/ite.c b/src/ec/starlabs/merlin/ite.c
index 6eaa3e9915..f034a0505a 100644
--- a/src/ec/starlabs/merlin/ite.c
+++ b/src/ec/starlabs/merlin/ite.c
@@ -337,13 +337,14 @@ static void merlin_init(struct device *dev)
 	 *
 	 * Setting:	power_led
 	 *
-	 * Values:	0, 1
+	 * Values:	0, 1, 2
 	 * Default:	0
 	 *
 	 */
 	const uint8_t power_led[] = {
 		LED_NORMAL,
-		LED_REDUCED
+		LED_REDUCED,
+		LED_OFF
 	};
 
 	if (CONFIG(EC_STARLABS_POWER_LED))

From 234eb53ed909ac95b748bf62a9fea30702fce8dc Mon Sep 17 00:00:00 2001
From: Patrick Rudolph <patrick.rudolph@9elements.com>
Date: Thu, 14 Aug 2025 18:49:43 +0200
Subject: [PATCH 1839/3886] nb/intel/sandybridge/raminit: Speed up reading SPD
 EEPROMs

Use i2c_eeprom_read() to speed up reading the SPD EEPROMs.

TEST=Booted on Lenovo X220 and used cbmem -t:
Before:
 940:waiting for ME acknowledgment of raminit          116,514 (62,804)
After:
 940:waiting for ME acknowledgment of raminit          110,212 (57,612)

Boots 5msec faster when MRC cache is present.

Change-Id: I500d7ff7a66b08b5036c0031e4fa20746d06df19
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88795
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
---
 src/northbridge/intel/sandybridge/raminit.c | 13 +++++++++----
 1 file changed, 9 insertions(+), 4 deletions(-)

diff --git a/src/northbridge/intel/sandybridge/raminit.c b/src/northbridge/intel/sandybridge/raminit.c
index 9ec8fb6f6e..cd6d173046 100644
--- a/src/northbridge/intel/sandybridge/raminit.c
+++ b/src/northbridge/intel/sandybridge/raminit.c
@@ -143,11 +143,16 @@ static void read_spd(spd_ddr3_raw_data *spd, u8 addr, bool id_only)
 {
 	int j;
 	if (id_only) {
-		for (j = SPD_DDR3_MOD_ID1; j < 128; j++)
-			(*spd)[j] = smbus_read_byte(addr, j);
+		u8 *dest = &(*spd)[SPD_DDR3_MOD_ID1];
+		if (i2c_eeprom_read(addr, SPD_DDR3_MOD_ID1, 128 - SPD_DDR3_MOD_ID1, dest) < 0) {
+			for (j = SPD_DDR3_MOD_ID1; j < 128; j++)
+				(*spd)[j] = smbus_read_byte(addr, j);
+		}
 	} else {
-		for (j = 0; j < SPD_SIZE_MAX_DDR3; j++)
-			(*spd)[j] = smbus_read_byte(addr, j);
+		if (i2c_eeprom_read(addr, 0, SPD_SIZE_MAX_DDR3, *spd) < 0) {
+			for (j = 0; j < SPD_SIZE_MAX_DDR3; j++)
+				(*spd)[j] = smbus_read_byte(addr, j);
+		}
 	}
 }
 

From 4931b978d91e6f0780b6534bd5f9f5f351597532 Mon Sep 17 00:00:00 2001
From: Ingo Reitz <9l@9lo.re>
Date: Sun, 24 Aug 2025 02:42:30 +0200
Subject: [PATCH 1840/3886] soc/mediatek: Increase CBFS cache to 8MB in
 memlayout.ld

Increase the CBFS cache in the memory layout of MediaTek Chromebook SoCs
to allow larger payloads like LinuxBoot to be loaded correctly.

TEST=Build and boot coreboot with LinuxBoot payload for
Google/Cherry/Tomato.

Change-Id: I4ce15e04cc19612ef1eed0fa0674ef8a7fd21fbe
Signed-off-by: Ingo Reitz <9l@9lo.re>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88916
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
---
 src/soc/mediatek/mt8183/memlayout.ld             | 4 ++--
 src/soc/mediatek/mt8186/include/soc/memlayout.ld | 4 ++--
 src/soc/mediatek/mt8192/include/soc/memlayout.ld | 4 ++--
 src/soc/mediatek/mt8195/include/soc/memlayout.ld | 4 ++--
 4 files changed, 8 insertions(+), 8 deletions(-)

diff --git a/src/soc/mediatek/mt8183/memlayout.ld b/src/soc/mediatek/mt8183/memlayout.ld
index b1b9027798..5697519b93 100644
--- a/src/soc/mediatek/mt8183/memlayout.ld
+++ b/src/soc/mediatek/mt8183/memlayout.ld
@@ -26,8 +26,8 @@ SECTIONS
 
 	DRAM_START(0x40000000)
 	DRAM_DMA(0x40000000, 1M)
-	POSTRAM_CBFS_CACHE(0x40100000, 1M)
-	RAMSTAGE(0x40200000, 2M)
+	POSTRAM_CBFS_CACHE(0x40100000, 8M)
+	RAMSTAGE(0x40900000, 2M)
 
 	BL31(0x54600000, 0x60000)
 }
diff --git a/src/soc/mediatek/mt8186/include/soc/memlayout.ld b/src/soc/mediatek/mt8186/include/soc/memlayout.ld
index a47e7c5ae4..da020dd5c0 100644
--- a/src/soc/mediatek/mt8186/include/soc/memlayout.ld
+++ b/src/soc/mediatek/mt8186/include/soc/memlayout.ld
@@ -44,8 +44,8 @@ SECTIONS
 
 	DRAM_START(0x40000000)
 	DRAM_DMA(0x40000000, 1M)
-	POSTRAM_CBFS_CACHE(0x40100000, 2M)
-	RAMSTAGE(0x40300000, 2M)
+	POSTRAM_CBFS_CACHE(0x40100000, 8M)
+	RAMSTAGE(0x40900000, 2M)
 
 	BL31(0x54600000, 0x60000)
 }
diff --git a/src/soc/mediatek/mt8192/include/soc/memlayout.ld b/src/soc/mediatek/mt8192/include/soc/memlayout.ld
index b1beef0970..2442e307c5 100644
--- a/src/soc/mediatek/mt8192/include/soc/memlayout.ld
+++ b/src/soc/mediatek/mt8192/include/soc/memlayout.ld
@@ -53,8 +53,8 @@ SECTIONS
 
 	DRAM_START(0x40000000)
 	DRAM_DMA(0x40000000, 1M)
-	POSTRAM_CBFS_CACHE(0x40100000, 2M)
-	RAMSTAGE(0x40300000, 2M)
+	POSTRAM_CBFS_CACHE(0x40100000, 8M)
+	RAMSTAGE(0x40900000, 2M)
 
 	BL31(0x54600000, 0x60000)
 }
diff --git a/src/soc/mediatek/mt8195/include/soc/memlayout.ld b/src/soc/mediatek/mt8195/include/soc/memlayout.ld
index ec8fa9c992..1a1948e3e1 100644
--- a/src/soc/mediatek/mt8195/include/soc/memlayout.ld
+++ b/src/soc/mediatek/mt8195/include/soc/memlayout.ld
@@ -44,8 +44,8 @@ SECTIONS
 
 	DRAM_START(0x40000000)
 	DRAM_DMA(0x40000000, 1M)
-	POSTRAM_CBFS_CACHE(0x40100000, 2M)
-	RAMSTAGE(0x40300000, 2M)
+	POSTRAM_CBFS_CACHE(0x40100000, 8M)
+	RAMSTAGE(0x40900000, 2M)
 
 	BL31(0x54600000, 0x60000)
 }

From 0eebd5596b5e01d04431eeb82e73ad22b275243d Mon Sep 17 00:00:00 2001
From: Hualin Wei <weihualin@huaqin.corp-partner.google.com>
Date: Mon, 23 Jun 2025 17:28:15 +0800
Subject: [PATCH 1841/3886] mb/google/fatcat: Create lapis variant

Create the lapis variant of the fatcat reference board by copying
the fatcat files to a new directory named for the variant.

BUG=b:438785495
TEST=1. util/abuild/abuild -p none -t google/fatcat -x -a
        make sure the build includes GOOGLE_LAPIS
     2. Run part_id_gen tool without any errors

Change-Id: Iabcc673a1868cea1d8a650af213d583cc2e27c28
Signed-off-by: Hualin Wei <weihualin@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88893
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
---
 src/mainboard/google/fatcat/Kconfig           |  11 +
 src/mainboard/google/fatcat/Kconfig.name      |   3 +
 .../baseboard/fatcat/include/baseboard/gpio.h |   5 +
 .../google/fatcat/variants/lapis/Makefile.mk  |   6 +
 .../google/fatcat/variants/lapis/gpio.c       | 439 ++++++++++++++++++
 .../google/fatcat/variants/lapis/hda_verb.c   |  13 +
 .../variants/lapis/include/variant/ec.h       |   8 +
 .../variants/lapis/include/variant/gpio.h     |  11 +
 .../google/fatcat/variants/lapis/memory.c     | 103 ++++
 .../fatcat/variants/lapis/memory/Makefile.mk  |   7 +
 .../lapis/memory/dram_id.generated.txt        |   9 +
 .../variants/lapis/memory/mem_parts_used.txt  |  14 +
 .../fatcat/variants/lapis/overridetree.cb     | 388 ++++++++++++++++
 13 files changed, 1017 insertions(+)
 create mode 100644 src/mainboard/google/fatcat/variants/lapis/Makefile.mk
 create mode 100644 src/mainboard/google/fatcat/variants/lapis/gpio.c
 create mode 100644 src/mainboard/google/fatcat/variants/lapis/hda_verb.c
 create mode 100644 src/mainboard/google/fatcat/variants/lapis/include/variant/ec.h
 create mode 100644 src/mainboard/google/fatcat/variants/lapis/include/variant/gpio.h
 create mode 100644 src/mainboard/google/fatcat/variants/lapis/memory.c
 create mode 100644 src/mainboard/google/fatcat/variants/lapis/memory/Makefile.mk
 create mode 100644 src/mainboard/google/fatcat/variants/lapis/memory/dram_id.generated.txt
 create mode 100644 src/mainboard/google/fatcat/variants/lapis/memory/mem_parts_used.txt
 create mode 100644 src/mainboard/google/fatcat/variants/lapis/overridetree.cb

diff --git a/src/mainboard/google/fatcat/Kconfig b/src/mainboard/google/fatcat/Kconfig
index 372b27ccd1..eba870feba 100644
--- a/src/mainboard/google/fatcat/Kconfig
+++ b/src/mainboard/google/fatcat/Kconfig
@@ -131,6 +131,13 @@ config BOARD_GOOGLE_KINMEN4ES
 config BOARD_GOOGLE_KINMEN
 	select BOARD_GOOGLE_MODEL_KINMEN
 
+config BOARD_GOOGLE_LAPIS
+	select BOARD_GOOGLE_BASEBOARD_FATCAT
+	select FSP_UGOP_EARLY_SIGN_OF_LIFE
+	select DRIVERS_INTEL_TOUCH
+	select HAVE_SLP_S0_GATE
+	select MAINBOARD_HAS_GOOGLE_STRAUSS_KEYBOARD
+
 if BOARD_GOOGLE_FATCAT_COMMON
 
 config BASEBOARD_DIR
@@ -168,6 +175,7 @@ config DRIVER_TPM_I2C_BUS
 	default 0x01 if BOARD_GOOGLE_FRANCKA
 	default 0x01 if BOARD_GOOGLE_MODEL_FELINO
 	default 0x03 if BOARD_GOOGLE_MODEL_KINMEN
+	default 0x03 if BOARD_GOOGLE_LAPIS
 
 config HAVE_SLP_S0_GATE
 	def_bool n
@@ -184,6 +192,7 @@ config MAINBOARD_PART_NUMBER
 	default "Francka" if BOARD_GOOGLE_FRANCKA
 	default "Felino" if BOARD_GOOGLE_MODEL_FELINO
 	default "Kinmen" if BOARD_GOOGLE_MODEL_KINMEN
+	default "Lapis" if BOARD_GOOGLE_LAPIS
 
 config MEMORY_SOLDERDOWN
 	def_bool n
@@ -196,6 +205,7 @@ config TPM_TIS_ACPI_INTERRUPT
 	default 79 if BOARD_GOOGLE_MODEL_FELINO # GPE0_DW2_15 (GPP_F15)
 	default 11 if BOARD_GOOGLE_FRANCKA # GPE0_DW0_11 (GPP_H11)
 	default 66 if BOARD_GOOGLE_MODEL_KINMEN # GPE0_DW2_02 (GPP_E02)
+	default 66 if BOARD_GOOGLE_LAPIS # GPE0_DW2_02 (GPP_E02)
 
 # FIXME: update as per board schematics
 config UART_FOR_CONSOLE
@@ -211,6 +221,7 @@ config VARIANT_DIR
 	default "francka" if BOARD_GOOGLE_FRANCKA
 	default "felino" if BOARD_GOOGLE_MODEL_FELINO
 	default "kinmen" if BOARD_GOOGLE_MODEL_KINMEN
+	default "lapis" if BOARD_GOOGLE_LAPIS
 
 config OVERRIDE_DEVICETREE
 	default "variants/\$(CONFIG_VARIANT_DIR)/overridetree.cb"
diff --git a/src/mainboard/google/fatcat/Kconfig.name b/src/mainboard/google/fatcat/Kconfig.name
index b7090069d4..06e24e70f6 100644
--- a/src/mainboard/google/fatcat/Kconfig.name
+++ b/src/mainboard/google/fatcat/Kconfig.name
@@ -37,3 +37,6 @@ config BOARD_GOOGLE_KINMEN4ES
 
 config BOARD_GOOGLE_KINMEN
 	bool "-> Kinmen"
+
+config BOARD_GOOGLE_LAPIS
+	bool "-> Lapis"
diff --git a/src/mainboard/google/fatcat/variants/baseboard/fatcat/include/baseboard/gpio.h b/src/mainboard/google/fatcat/variants/baseboard/fatcat/include/baseboard/gpio.h
index f0a91b0ff7..beffed62a1 100644
--- a/src/mainboard/google/fatcat/variants/baseboard/fatcat/include/baseboard/gpio.h
+++ b/src/mainboard/google/fatcat/variants/baseboard/fatcat/include/baseboard/gpio.h
@@ -37,6 +37,11 @@
  #define GPIO_PCH_WP	GPP_D02
 /* Used to gate SoC's SLP_S0# signal */
 #define GPIO_SLP_S0_GATE	GPP_V17
+#elif CONFIG(BOARD_GOOGLE_LAPIS)
+ #define EC_SYNC_IRQ	GPP_E07_IRQ
+ #define GPIO_PCH_WP	GPP_D02
+/* Used to gate SoC's SLP_S0# signal */
+#define GPIO_SLP_S0_GATE	GPP_V17
 #endif
 
 #endif /* __BASEBOARD_GPIO_H__ */
diff --git a/src/mainboard/google/fatcat/variants/lapis/Makefile.mk b/src/mainboard/google/fatcat/variants/lapis/Makefile.mk
new file mode 100644
index 0000000000..4c33dad4db
--- /dev/null
+++ b/src/mainboard/google/fatcat/variants/lapis/Makefile.mk
@@ -0,0 +1,6 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
+bootblock-y += gpio.c
+romstage-y += gpio.c
+romstage-y += memory.c
+ramstage-y += gpio.c
diff --git a/src/mainboard/google/fatcat/variants/lapis/gpio.c b/src/mainboard/google/fatcat/variants/lapis/gpio.c
new file mode 100644
index 0000000000..faaa5e0d5b
--- /dev/null
+++ b/src/mainboard/google/fatcat/variants/lapis/gpio.c
@@ -0,0 +1,439 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <baseboard/gpio.h>
+#include <baseboard/variants.h>
+#include <boardid.h>
+#include <soc/gpio.h>
+
+/* Pad configuration in ramstage*/
+static const struct pad_config gpio_table[] = {
+	/* GPP_A00:     ESPI_IO0_EC_R */
+	/*  GPP_A00 : GPP_A00 ==> ESPI_IO0_EC_R configured on reset, do not touch */
+
+	/* GPP_A01:     ESPI_IO1_EC_R */
+	/*  GPP_A01 : GPP_A01 ==> ESPI_IO1_EC_R configured on reset, do not touch */
+
+	/* GPP_A02:     ESPI_IO2_EC_R */
+	/*  GPP_A02 : GPP_A02 ==> ESPI_IO2_EC_R configured on reset, do not touch */
+
+	/* GPP_A03:     ESPI_IO3_EC_R */
+	/*  GPP_A03 : GPP_A03 ==> ESPI_IO3_EC_R configured on reset, do not touch */
+
+	/* GPP_A04:     ESPI_CS0_EC_R_N */
+	/*  GPP_A04 : GPP_A04 ==> ESPI_CS0_HDR_L configured on reset, do not touch */
+
+	/* GPP_A05:     ESPI_CLK_EC_R */
+	/*  GPP_A05 : GPP_A05 ==> ESPI_CLK_HDR configured on reset, do not touch */
+
+	/* GPP_A06:     ESPI_RST_EC_R_N */
+	/*  GPP_A06 : GPP_A06 ==> ESPI_RST_HDR configured on reset, do not touch */
+
+	/* GPP_A08:     Not used */
+	PAD_NC(GPP_A08, NONE),
+	/* GPP_A09:     Not used */
+	PAD_NC(GPP_A09, NONE),
+	/* GPP_A10:     Not used */
+	PAD_NC(GPP_A10, NONE),
+	/* GPP_A11:     Not used */
+	PAD_NC(GPP_A11, NONE),
+	/* GPP_A12:     WIFI_WAKE_N ==> TOUCHPANEL_SYNC */ /* NC */
+	PAD_NC(GPP_A12, NONE),
+	/* GPP_A13:     MEM_STRAP_0 */
+	PAD_CFG_GPI(GPP_A13, NONE, DEEP),
+	/* GPP_A15:     GPP_A15_DNX_FORCE_RELOAD ==> EPD_ON_GCD_OUT*/ /* NC */
+	/* PAD_CFG_NF(GPP_A15, NONE, DEEP, NF1), */
+	/* GPP_A16:     BT_DISABLE_L ==> BT_ON_WLAN */
+	PAD_CFG_GPO(GPP_A16, 1, DEEP),
+	/* GPP_A17:     WIFI_DISABLE_L ==> WLAN_ON_PCH */
+	PAD_CFG_GPO(GPP_A17, 1, DEEP),
+
+	/* GPP_B00:     PMC_I2C_PD_SCL ==> PD_SMB1_CLK */
+	PAD_CFG_NF(GPP_B00, NONE, DEEP, NF1),
+	/* GPP_B01:     PMC_I2C_PD_SDA ==> PD_SMB1_DATA */
+	PAD_CFG_NF(GPP_B01, NONE, DEEP, NF1),
+	/* GPP_B02:     ISH_I2C0_SDA_SNSR_HDR ==> NC  */ /* may be connect to EC */
+	/* NOTE: IOSSTAGE: 'Ignore' for S0ix */
+	PAD_NC(GPP_B02, NONE),
+	/* GPP_B03:     ISH_I2C0_SCL_SNSR_HDR ==> NC  */
+	/* NOTE: IOSSTAGE: 'Ignore' for S0ix */
+	PAD_NC(GPP_B03, NONE),
+	/* GPP_B04:     ISH_GP_0_SNSR_HDR ==> NC*/ /* maybe disable ISH */
+	PAD_NC(GPP_B04, NONE),
+	/* GPP_B05:     ISH_GP_1_SNSR_HDR ==>  NC */
+	PAD_NC(GPP_B05, NONE),
+	/* GPP_B06:     ISH_GP_2_SNSR_HDR ==> NC*/
+	PAD_NC(GPP_B06, NONE),
+	/* GPP_B07:     ISH_GP_3_SNSR_HDR ==> NC */
+	PAD_NC(GPP_B07, NONE),
+	/* GPP_B08:     ISH_GP_4_SNSR_HDR ==> GPP_B08_TBT_LOW_POWER_MODE */
+	PAD_CFG_NF(GPP_B08, NONE, DEEP, NF4),
+	/* GPP_B09:     M2_GEN5_SSD_RESET_N ==> SSD_GEN5_PERST_L */
+	PAD_CFG_GPO(GPP_B09, 1, PLTRST),
+	/* GPP_B10:     GEN4_SSD_PWREN */ /* may be NC */
+	PAD_CFG_NF(GPP_B10, NONE, DEEP, NF2),
+	/* GPP_B11:     MOD_TCSS1_DISP_HPD3 ==> USB_OC1 */ /* may be change to USB_OC1 */
+	PAD_CFG_NF(GPP_B11, NONE, DEEP, NF2),
+	/* GPP_B12:     PM_SLP_S0_N ==> PCH_SLP_S0# */
+	PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1),
+	/* GPP_B13:     PLT_RST_N */
+	PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1),
+	/* GPP_B14:     MOD_TCSS2_DISP_HPD4 ==> HDMI_HPD_CPU# */
+	PAD_CFG_NF(GPP_B14, NONE, DEEP, NF2),
+	/* GPP_B15:     Not used */
+	PAD_NC(GPP_B15, NONE),
+	/* GPP_B16:     EN_PP3300_SSD ==> EN_PP3300_SSD_GEN5 */
+	PAD_CFG_GPO(GPP_B16, 1, PLTRST),
+	/* GPP_B17:     Not used ==> GPP_B17_TBT_LOW_POWER_MODE */
+	PAD_CFG_NF(GPP_B17, NONE, DEEP, NF4),
+	/* GPP_B18:     Not used */
+	PAD_NC(GPP_B18, NONE),
+	/* GPP_B19:     Not used */
+	PAD_NC(GPP_B19, NONE),
+	/* GPP_B20:     Not used */
+	PAD_NC(GPP_B20, NONE),
+	/* GPP_B21:     USB4_RT_FORCE_PWR ==> TBT_FORCE_PWR */
+	PAD_CFG_GPO(GPP_B21, 0, DEEP),
+	/* GPP_B22:     Not used */
+	PAD_NC(GPP_B22, NONE),
+	/* GPP_B17:     Not used */
+	PAD_NC(GPP_B23, NONE),
+	/* GPP_B24:     MEM_STRAP_3 */
+	PAD_CFG_GPI(GPP_B24, NONE, DEEP),
+	/* GPP_B25:     DIMM_SEL2 */
+	PAD_CFG_GPI(GPP_B25, NONE, DEEP),
+
+	/* GPP_C00:     GPP_C0_SMBCLK ==> SMB_CLK */
+	PAD_CFG_NF(GPP_C00, NONE, DEEP, NF1),
+	/* GPP_C01:     GPP_C1_SMBDATA ==> SMB_DAT */
+	PAD_CFG_NF(GPP_C01, NONE, DEEP, NF1),
+	/* GPP_C02:     Not used */
+	PAD_NC(GPP_C02, NONE),
+	/* GPP_C03:     TBT_SMB_CLK */
+	PAD_CFG_NF(GPP_C03, NONE, DEEP, NF1),
+	/* GPP_C04:     TBT_SMB_DATA */
+	PAD_CFG_NF(GPP_C04, NONE, DEEP, NF1),
+	/* GPP_C06:     CAM_PWR_EN */ /* TBD */
+	PAD_CFG_GPO(GPP_C06, 1, DEEP),
+	/* GPP_C07:     MEM_CH_SEL */
+	PAD_CFG_GPI(GPP_C07, NONE, DEEP),
+	/* GPP_C08:     Not used */
+	PAD_NC(GPP_C08, NONE),
+	/* GPP_C09:     SSD_GEN5_CLKREQ_ODL ==> CLKREQ0_SSD1# */
+	PAD_CFG_NF(GPP_C09, NONE, DEEP, NF1),
+	/* GPP_C10:     Not used */
+	PAD_NC(GPP_C10, NONE),
+	/* GPP_C11:     Not used */
+	PAD_NC(GPP_C11, NONE),
+	/* GPP_C12:     Not used */
+	PAD_NC(GPP_C12, NONE),
+	/* GPP_C13:     Not used */
+	PAD_NC(GPP_C13, NONE),
+	/* GPP_C14:     Not used */
+	PAD_NC(GPP_C14, NONE),
+	/* GPP_C16:     USB_C0_LSX_TX  ==> TBT_LSX0_TXD */
+	PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1),
+	/* GPP_C17:     USB_C0_LSX_RX  ==> TBT_LSX0_RXD */
+	PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1),
+	/* GPP_C18:     Not used */
+	PAD_NC(GPP_C18, NONE),
+	/* GPP_C19:     Not used */
+	PAD_NC(GPP_C19, NONE),
+	/* GPP_C20:     USB_C1_LSX_TX ==> TBT_LSX2_TXD */
+	PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1),
+	/* GPP_C21:     USB_C1_LSX_RX ==> TBT_LSX2_RXD */
+	PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1),
+	/* GPP_C22:     DDP3_HDMI_CTRLCLK ==> HDMI_X1_CLK*/
+	PAD_CFG_NF(GPP_C22, NONE, DEEP, NF2),
+	/* GPP_C23:     DDP3_HDMI_CTRLDATA ==> HDMI_X1_DATA */
+	PAD_CFG_NF(GPP_C23, NONE, DEEP, NF2),
+
+	/* GPP_D00:     Not used */
+	PAD_NC(GPP_D00, NONE),
+	/* GPP_D01:     Not used */
+	PAD_NC(GPP_D01, NONE),
+	/* GPP_D02:     SOC_WP_OD ==> FLASH_WP_CPU */
+	PAD_CFG_GPI(GPP_D02, NONE, DEEP),
+	/* GPP_D03:     Not used */
+	PAD_NC(GPP_D03, NONE),
+	/* GPP_D04:     Not used */
+	PAD_NC(GPP_D04, NONE),
+	/* GPP_D05:     Not used  */
+	PAD_NC(GPP_D05, NONE),
+	/* GPP_D06:     Not used  */
+	PAD_NC(GPP_D06, NONE),
+	/* GPP_D07:     Not used */
+	PAD_NC(GPP_D07, NONE),
+	/* GPP_D08:     Not used */
+	PAD_NC(GPP_D08, NONE),
+	/* GPP_D09:     Not used ==> CPU_ID0 */
+	PAD_NC(GPP_D09, NONE),
+	/* GPP_D10:     Not used ==> CPU_ID1*/
+	PAD_NC(GPP_D10, NONE),
+	/* GPP_D11:     Not used ==> CPU_ID2*/
+	PAD_NC(GPP_D11, NONE),
+	/* GPP_D12:     Not used ==> HDA_SDO_PCH */
+	PAD_NC(GPP_D12, NONE),
+	/* GPP_D13:     Not used ==> HDA_SDI_PCH */
+	PAD_NC(GPP_D13, NONE),
+	/* GPP_D14:     Not used */
+	PAD_NC(GPP_D14, NONE),
+	/* GPP_D15:     Not used */
+	PAD_NC(GPP_D15, NONE),
+	/* GPP_D16:     Not used  */ /* DMIC connect to Audio Codec */
+	PAD_NC(GPP_D16, NONE),
+	/* GPP_D17:     Not used  */ /* DMIC connect to Audio Codec */
+	PAD_NC(GPP_D17, NONE),
+	/* GPP_D18:     Not used */
+	PAD_NC(GPP_D18, NONE),
+	/* GPP_D19:     Not used */
+	PAD_NC(GPP_D19, NONE),
+	/* GPP_D20:     EC_SOC_REC_SWITCH_ODL */
+	PAD_CFG_GPI(GPP_D20, NONE, DEEP),
+	/* GPP_D21:     Not used */
+	PAD_NC(GPP_D21, NONE),
+	/* GPP_D22:     Not used ==> VPRO_ID0 */
+	PAD_NC(GPP_D22, NONE),
+	/* GPP_D23:     Not used ==> VPRO_ID1 */
+	PAD_NC(GPP_D23, NONE),
+	/* GPP_D24:     DIMM_SEL1 */
+	PAD_CFG_GPI(GPP_D24, NONE, DEEP),
+	/* GPP_D25:     DIMM_SEL0 */
+	PAD_CFG_GPI(GPP_D25, NONE, DEEP),
+
+	/* GPP_E01:     Not used */
+	PAD_NC(GPP_E01, NONE),
+	/* GPP_E02:     GSC_SOC_INT_ODL  */ /* locked */
+	/* PAD_CFG_GPI_APIC_LOCK(GPP_E02, NONE, LEVEL, INVERT, LOCK_CONFIG), */
+	/* GPP_E03:     Not used */
+	PAD_NC(GPP_E03, NONE),
+	/* GPP_E06:     Not used */
+	PAD_NC(GPP_E06, NONE),
+	/* GPP_E07:     EC_SOC_INT_ODL */
+	PAD_CFG_GPI_SCI_LOW(GPP_E07, NONE, DEEP, LEVEL),
+	/* GPP_E08:     Not used */
+	PAD_NC(GPP_E08, NONE),
+	/* GPP_E09:     USBA0_OC_ODL ==> USB_OC0# */
+	PAD_CFG_NF(GPP_E09, NONE, DEEP, NF1),
+	/* GPP_E10:     Not used */ /* TPM */
+	PAD_NC(GPP_E10, NONE),
+	/* GPP_E11:     EN_TCHSCR_PWR ==> TOUCH_ENABLE */
+	PAD_CFG_GPO(GPP_E11, 1, PLTRST),
+	/* GPP_E12:     SOC_I2C_TCHPAD_SCL ==> THC_I2C0_SCL_TOUCH_EDP */
+	PAD_CFG_NF(GPP_E12, NONE, DEEP, NF1),
+	/* GPP_E13:     SOC_I2C_TCHPAD_SDA ==> THC_I2C0_SDA_TOUCH_EDP*/
+	PAD_CFG_NF(GPP_E13, NONE, DEEP, NF1),
+	/* GPP_E14:     Not used */
+	PAD_NC(GPP_E14, NONE),
+	/* GPP_E15:     Not used */
+	PAD_NC(GPP_E15, NONE),
+	/* GPP_E16:     Not used */
+	PAD_NC(GPP_E16, NONE),
+	/* GPP_E17:     Not used ==> TOUCHPAD_INTR */
+	PAD_CFG_GPI_APIC(GPP_E17, NONE, PLTRST, LEVEL, NONE),
+	/* GPP_E18:     TCHPAD_INT_ODL_LS ==> Not used */
+	PAD_NC(GPP_E18, NONE),
+	/* GPP_E19:     Not used ==> PANEL_ID0 */
+	PAD_NC(GPP_E19, NONE),
+	/* GPP_E20:     Not used ==> PANEL_ID1 */
+	PAD_NC(GPP_E20, NONE),
+	/* GPP_E21:     PMC_I2C_PD_INT_ODL ==> PD_SMB1_INT# */
+	PAD_CFG_NF(GPP_E21, NONE, DEEP, NF1),
+	/* GPP_E22:     Not used */
+	PAD_NC(GPP_E22, NONE),
+
+	/* GPP_F00:     M.2_CNV_BRI_DT_BT_UART2_RTS_N */
+	/* NOTE: IOSSTAGE: 'Ignore' for S0ix */
+	PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_F00, NONE, DEEP, NF1),
+	/* GPP_F01:     M.2_CNV_BRI_RSP_BT_UART2_RXD */
+	/* NOTE: IOSSTAGE: 'Ignore' for S0ix */
+	PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_F01, NONE, DEEP, NF1),
+	/* GPP_F02:     M.2_CNV_RGI_DT_BT_UART2_TXD */
+	/* NOTE: IOSSTAGE: 'Ignore' for S0ix */
+	PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_F02, NONE, DEEP, NF1),
+	/* GPP_F03:     M.2_CNV_RGI_RSP_BT_UART2_CTS_N */
+	/* NOTE: IOSSTAGE: 'Ignore' for S0ix */
+	PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_F03, NONE, DEEP, NF1),
+	/* GPP_F04:     CNV_RF_RESET_R_N */
+	/* NOTE: IOSSTAGE: 'Ignore' for S0ix */
+	PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_F04, NONE, DEEP, NF1),
+	/* GPP_F05:     CRF_CLKREQ_R */
+	/* NOTE: IOSSTAGE: 'Ignore' for S0ix */
+	PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_F05, NONE, DEEP, NF3),
+	/* GPP_F06:     Not used */
+	PAD_NC(GPP_F06, NONE),
+	/* GPP_F07:     Not used */
+	PAD_NC(GPP_F07, NONE),
+	/* GPP_F08:     Not used */
+	PAD_NC(GPP_F08, NONE),
+	/* GPP_F09:     NC */
+	PAD_NC(GPP_F09, NONE),
+	/* GPP_F10:     NC */
+	PAD_NC(GPP_F10, NONE),
+	/* GPP_F11:     NC */
+	PAD_NC(GPP_F11, NONE),
+	/* GPP_F12:     THC_I2C1_SCL_TCH_PAD */
+	PAD_CFG_NF(GPP_F12, NONE, DEEP, NF8),
+	/* GPP_F13:     THC_I2C1_SDA_TCH_PAD */
+	PAD_CFG_NF(GPP_F13, NONE, DEEP, NF8),
+	/* GPP_F14:     NC */
+	PAD_NC(GPP_F14, NONE),
+	/* GPP_F15:     NC */
+	PAD_NC(GPP_F15, NONE),
+	/* GPP_F16:     THC0_SPI1_RST_N_TCH_PNL1 */
+	/* THC NOTE: use GPO instead of GPO for THC0 Rst */
+	PAD_CFG_GPO(GPP_F16, 1, DEEP),
+	/* GPP_F17:     CODEC_INT_N ==> NC */
+	PAD_NC(GPP_F17, NONE),
+	/* GPP_F18:     SOC_TCHSCR_INT */
+	PAD_CFG_GPI_APIC(GPP_F18, NONE, PLTRST, LEVEL, INVERT),
+	/* GPP_F19:     NC */
+	PAD_NC(GPP_F19, NONE),
+	/* GPP_F20:     NC */
+	PAD_NC(GPP_F20, NONE),
+	/* GPP_F22:     NC */
+	PAD_NC(GPP_F22, NONE),
+
+	/* GPP_H00:     Not used */
+	PAD_NC(GPP_H00, NONE),
+	/* GPP_H01:     Not used */
+	PAD_NC(GPP_H01, NONE),
+	/* GPP_H02:     Not used */
+	PAD_NC(GPP_H02, NONE),
+	/* GPP_H03:     Not used */
+	PAD_NC(GPP_H03, NONE),
+	/* GPP_H04:     Not used */
+	PAD_NC(GPP_H04, NONE),
+	/* GPP_H05:     Not used */
+	PAD_NC(GPP_H05, NONE),
+	/* GPP_H06:     SOC_I2C_TPM_SDA */
+	PAD_CFG_NF(GPP_H06, NONE, DEEP, NF1),
+	/* GPP_H07:     SOC_I2C_TPM_SCL */
+	PAD_CFG_NF(GPP_H07, NONE, DEEP, NF1),
+	/* GPP_H08:     UART_DBG_TX_SOC_RX_U */
+	PAD_CFG_NF(GPP_H08, NONE, DEEP, NF1),
+	/* GPP_H09:     UART_SOC_TX_DBG_RX_U */
+	PAD_CFG_NF(GPP_H09, NONE, DEEP, NF1),
+	/* GPP_H10:     Not used */
+	PAD_NC(GPP_H10, NONE),
+	/* GPP_H11:     Not used */
+	PAD_NC(GPP_H11, NONE),
+	/* GPP_H13:     CPU_C10_GATE_L */
+	PAD_CFG_NF(GPP_H13, NONE, DEEP, NF1),
+	/* GPP_H14:     NC */
+	PAD_NC(GPP_H14, NONE),
+	/* GPP_H15:     NC */
+	PAD_NC(GPP_H15, NONE),
+	/* GPP_H16:     NC */
+	PAD_NC(GPP_H16, NONE),
+	/* GPP_H17:     NC */
+	PAD_NC(GPP_H17, NONE),
+	/* GPP_H19:     NC */
+	PAD_NC(GPP_H19, NONE),
+	/* GPP_H20:     NC */
+	PAD_NC(GPP_H20, NONE),
+	/* GPP_H21:     NC */ /* Audio Codec */
+	PAD_NC(GPP_H21, NONE),
+	/* GPP_H22:     NC */ /* Audio Codec */
+	PAD_NC(GPP_H22, NONE),
+
+	/* GPP_S00:     SNDW3_CLK_CODEC */
+	PAD_CFG_NF(GPP_S00, NONE, DEEP, NF1),
+	/* GPP_S01:     SNDW3_DATA0_CODEC */
+	PAD_CFG_NF(GPP_S01, NONE, DEEP, NF1),
+	/* GPP_S02:     SNDW3_DATA1_CODEC */
+	PAD_CFG_NF(GPP_S02, NONE, DEEP, NF1),
+	/* GPP_S03:     NC */
+	PAD_NC(GPP_S03, NONE),
+	/* GPP_S04:     SNDW2_CLK */
+	PAD_CFG_NF(GPP_S04, NONE, DEEP, NF2),
+	/* GPP_S05:     SNDW2_DATA0 */
+	PAD_CFG_NF(GPP_S05, NONE, DEEP, NF2),
+	/* GPP_S06:     SNDW1_CLK */
+	PAD_NC(GPP_S06, NONE),
+	/* GPP_S07:     SNDW1_DATA0 */
+	PAD_NC(GPP_S07, NONE),
+
+	/* GPP_V00:     BATLOW_L */
+	PAD_CFG_NF(GPP_V00, NONE, DEEP, NF1),
+	/* GPP_V01:     ACPRESENT */
+	PAD_CFG_NF(GPP_V01, NONE, DEEP, NF1),
+	/* GPP_V02:     LANWAKE_N_R */
+	PAD_CFG_NF(GPP_V02, NONE, DEEP, NF1),
+	/* GPP_V03:     EC_SOC_PWR_BTN_ODL */
+	PAD_CFG_NF(GPP_V03, NONE, DEEP, NF1),
+	/* GPP_V04:     PM_SLP_S3_N */
+	PAD_CFG_NF(GPP_V04, NONE, DEEP, NF1),
+	/* GPP_V05:     PM_SLP_S4_N */
+	PAD_CFG_NF(GPP_V05, NONE, DEEP, NF1),
+	/* GPP_V06:     PM_SLP_A_N */
+	PAD_CFG_NF(GPP_V06, NONE, DEEP, NF1),
+	/* GPP_V07:     SUS_CLK */
+	PAD_CFG_NF(GPP_V07, NONE, DEEP, NF1),
+	/* GPP_V08:     SLP_WLAN_N */ /* NC */
+	PAD_CFG_NF(GPP_V08, NONE, DEEP, NF1),
+	/* GPP_V09:     PM_SLP_S5_N */
+	PAD_CFG_NF(GPP_V09, NONE, DEEP, NF1),
+	/* GPP_V10:     LANPHYPC_R_N */ /* NC */
+	PAD_CFG_NF(GPP_V10, NONE, DEEP, NF1),
+	/* GPP_V11:     PM_SLP_LAN_N */ /* NC */
+	PAD_CFG_NF(GPP_V11, NONE, DEEP, NF1),
+	/* GPP_V12:     SOC_WAKE_L */
+	PAD_CFG_NF(GPP_V12, NONE, DEEP, NF1),
+	/* GPP_V16:     EN_VCCST */
+	PAD_CFG_NF(GPP_V16, NONE, DEEP, NF1),
+	/* GPP_V17:     SLP_S0_GATE_R */
+	PAD_CFG_GPO(GPP_V17, 1, DEEP),
+
+	/* GPP_VGPIO3_THC0: THC0_WOT */
+	PAD_CFG_GPI_APIC_DRIVER(GPP_VGPIO3_THC0, NONE, PLTRST, LEVEL, NONE),
+	/* GPP_VGPIO3_THC1: THC1_WOT */
+	PAD_CFG_GPI_APIC_DRIVER(GPP_VGPIO3_THC1, NONE, PLTRST, LEVEL, NONE),
+};
+
+/* Early pad configuration in bootblock */
+static const struct pad_config early_gpio_table[] = {
+	/* GPP_H08:     UART0_BUF_RXD */
+	PAD_CFG_NF(GPP_H08, NONE, DEEP, NF1),
+	/* GPP_H09:     UART0_BUF_TXD */
+	PAD_CFG_NF(GPP_H09, NONE, DEEP, NF1),
+
+	/* GPP_H06: SOC_I2C_TPM_SDA */
+	PAD_CFG_NF(GPP_H06, NONE, DEEP, NF1),
+	/* GPP_H07: SOC_I2C_TPM_SCL */
+	PAD_CFG_NF(GPP_H07, NONE, DEEP, NF1),
+	/* GPP_E02:     GSC_SOC_INT_ODL  */
+	PAD_CFG_GPI_APIC_LOCK(GPP_E02, NONE, LEVEL, INVERT, LOCK_CONFIG),
+};
+
+/* Pad configuration in romstage */
+static const struct pad_config romstage_gpio_table[] = {
+};
+
+const struct pad_config *variant_gpio_table(size_t *num)
+{
+	*num = ARRAY_SIZE(gpio_table);
+	return gpio_table;
+}
+
+const struct pad_config *variant_early_gpio_table(size_t *num)
+{
+	*num = ARRAY_SIZE(early_gpio_table);
+	return early_gpio_table;
+}
+
+/* Create the stub for romstage gpio, typically use for power sequence */
+const struct pad_config *variant_romstage_gpio_table(size_t *num)
+{
+	*num = ARRAY_SIZE(romstage_gpio_table);
+	return romstage_gpio_table;
+}
+
+static const struct cros_gpio cros_gpios[] = {
+	CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE0_NAME),
+	CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE1_NAME),
+	CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE2_NAME),
+	CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE3_NAME),
+	CROS_GPIO_WP_AH(GPIO_PCH_WP, CROS_GPIO_DEVICE4_NAME),
+};
+
+DECLARE_CROS_GPIOS(cros_gpios);
diff --git a/src/mainboard/google/fatcat/variants/lapis/hda_verb.c b/src/mainboard/google/fatcat/variants/lapis/hda_verb.c
new file mode 100644
index 0000000000..2c7c96f74e
--- /dev/null
+++ b/src/mainboard/google/fatcat/variants/lapis/hda_verb.c
@@ -0,0 +1,13 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <device/azalia_device.h>
+
+const u32 cim_verb_data[] = {
+
+};
+
+const u32 pc_beep_verbs[] = {
+
+};
+
+AZALIA_ARRAY_SIZES;
diff --git a/src/mainboard/google/fatcat/variants/lapis/include/variant/ec.h b/src/mainboard/google/fatcat/variants/lapis/include/variant/ec.h
new file mode 100644
index 0000000000..4fc0622f15
--- /dev/null
+++ b/src/mainboard/google/fatcat/variants/lapis/include/variant/ec.h
@@ -0,0 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#ifndef MAINBOARD_EC_H
+#define MAINBOARD_EC_H
+
+#include <baseboard/ec.h>
+
+#endif /* MAINBOARD_GPIO_H */
diff --git a/src/mainboard/google/fatcat/variants/lapis/include/variant/gpio.h b/src/mainboard/google/fatcat/variants/lapis/include/variant/gpio.h
new file mode 100644
index 0000000000..cced66807a
--- /dev/null
+++ b/src/mainboard/google/fatcat/variants/lapis/include/variant/gpio.h
@@ -0,0 +1,11 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#ifndef __MAINBOARD_GPIO_H__
+#define __MAINBOARD_GPIO_H__
+
+#include <baseboard/gpio.h>
+
+/* EC wake is LAN_WAKE# which is a special DeepSX wake pin */
+#define GPE_EC_WAKE	GPE0_LAN_WAK
+
+#endif /* __MAINBOARD_GPIO_H__ */
diff --git a/src/mainboard/google/fatcat/variants/lapis/memory.c b/src/mainboard/google/fatcat/variants/lapis/memory.c
new file mode 100644
index 0000000000..f2a03ae4ea
--- /dev/null
+++ b/src/mainboard/google/fatcat/variants/lapis/memory.c
@@ -0,0 +1,103 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <baseboard/variants.h>
+#include <soc/romstage.h>
+#include <soc/meminit.h>
+
+static const struct mb_cfg lp5_mem_config = {
+	.type = MEM_TYPE_LP5X,
+
+	.lpx_dq_map = {
+		.ddr0 = {
+			.dq0 = {  13,  14,  12,  15, 11,  10,  8,  9, },
+			.dq1 = {  7,  5,  4,  6,  0,  3,  1,  2 },
+		},
+		.ddr1 = {
+			.dq0 = {  1,  3,  0,  2,  7,  4,  6,  5, },
+			.dq1 = {  12,  13,  14,  15,  11,  10,  9,  8 },
+		},
+		.ddr2 = {
+			.dq0 = {  0,  2,  1,  3,  6,  4,  7,  5 },
+			.dq1 = {  14,  13,  15,  12,  8,  11,  10,  9, },
+		},
+		.ddr3 = {
+			.dq0 = {  6,  5,  7,  4,  2,  3,  1,  0, },
+			.dq1 = {  10,  8,  11,  9,  12,  15,  13,  14 },
+		},
+		.ddr4 = {
+			.dq0 = {  2,  1,  3,  0,  4,  7,  5,  6 },
+			.dq1 = {  15,  14,  12,  13,  9,  11,  10,  8, },
+		},
+		.ddr5 = {
+			.dq0 = {  6,  5,  7,  4,  3,  1,  0,  2, },
+			.dq1 = {  10,  9,  11,  8,  13,  14,  12,  15 },
+		},
+		.ddr6 = {
+			.dq0 = {  9,  10,  11,  8,  14,  12,  13, 15, },
+			.dq1 = {  0,  1,  2,  3,  5,  7,  4,  6 },
+		},
+		.ddr7 = {
+			.dq0 = {  0,  1,  2,  3,  7,  5,  6,  4, },
+			.dq1 = {  14,  13,  15,  12,  10,  8,  11,  9 },
+		},
+	},
+
+	.lpx_dqs_map = {
+		.ddr0 = { .dqs0 = 1, .dqs1 = 0 },
+		.ddr1 = { .dqs0 = 0, .dqs1 = 1 },
+		.ddr2 = { .dqs0 = 0, .dqs1 = 1 },
+		.ddr3 = { .dqs0 = 0, .dqs1 = 1 },
+		.ddr4 = { .dqs0 = 0, .dqs1 = 1 },
+		.ddr5 = { .dqs0 = 0, .dqs1 = 1 },
+		.ddr6 = { .dqs0 = 1, .dqs1 = 0 },
+		.ddr7 = { .dqs0 = 0, .dqs1 = 1 }
+	},
+
+	.ect = true, /* Early Command Training */
+
+	.lp_ddr_dq_dqs_re_training = 1,
+
+	.user_bd = BOARD_TYPE_ULT_ULX,
+
+	.lp5x_config = {
+		.ccc_config = 0xFF,
+	},
+};
+
+const struct mb_cfg *variant_memory_params(void)
+{
+	return &lp5_mem_config;
+}
+
+int variant_memory_sku(void)
+{
+	/*
+	 * Memory configuration board straps
+	 * MEM_STRAP_0	GPP_A13
+	 * MEM_STRAP_3	GPP_B24
+	 * DIMM_SEL0	GPP_D25
+	 * DIMM_SEL1	GPP_D24
+	 * DIMM_SEL2	GPP_B25
+	 */
+	gpio_t spd_gpios[] = {
+		GPP_A13,
+		GPP_B24,
+		GPP_D25,
+		GPP_D24,
+		GPP_B25,
+	};
+
+	return gpio_base2_value(spd_gpios, ARRAY_SIZE(spd_gpios));
+}
+
+void variant_get_spd_info(struct mem_spd *spd_info)
+{
+	spd_info->topo = MEM_TOPO_MEMORY_DOWN;
+	spd_info->cbfs_index = variant_memory_sku();
+}
+
+bool variant_is_half_populated(void)
+{
+	/* GPIO_MEM_CH_SEL GPP_C07 */
+	return gpio_get(GPP_C07);
+}
diff --git a/src/mainboard/google/fatcat/variants/lapis/memory/Makefile.mk b/src/mainboard/google/fatcat/variants/lapis/memory/Makefile.mk
new file mode 100644
index 0000000000..d1cc1e3fd4
--- /dev/null
+++ b/src/mainboard/google/fatcat/variants/lapis/memory/Makefile.mk
@@ -0,0 +1,7 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+# This is an auto-generated file. Do not edit!!
+# Generated by:
+# util/spd_tools/bin/part_id_gen PTL lp5 src/mainboard/google/fatcat/variants/lapis/memory src/mainboard/google/fatcat/variants/lapis/memory/mem_parts_used.txt
+
+SPD_SOURCES =
+SPD_SOURCES += spd/lp5/set-0/spd-10.hex      # ID = 0(0b0000)  Parts = H58G66CK8BX147, K3KL9L90EM-MGCU, MT62F2G32D4DS-023 WT:C
diff --git a/src/mainboard/google/fatcat/variants/lapis/memory/dram_id.generated.txt b/src/mainboard/google/fatcat/variants/lapis/memory/dram_id.generated.txt
new file mode 100644
index 0000000000..1b44fd47f4
--- /dev/null
+++ b/src/mainboard/google/fatcat/variants/lapis/memory/dram_id.generated.txt
@@ -0,0 +1,9 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+# This is an auto-generated file. Do not edit!!
+# Generated by:
+# util/spd_tools/bin/part_id_gen PTL lp5 src/mainboard/google/fatcat/variants/lapis/memory src/mainboard/google/fatcat/variants/lapis/memory/mem_parts_used.txt
+
+DRAM Part Name                 ID to assign
+H58G66CK8BX147                 0 (0000)
+K3KL9L90EM-MGCU                0 (0000)
+MT62F2G32D4DS-023 WT:C         0 (0000)
diff --git a/src/mainboard/google/fatcat/variants/lapis/memory/mem_parts_used.txt b/src/mainboard/google/fatcat/variants/lapis/memory/mem_parts_used.txt
new file mode 100644
index 0000000000..2a5856956b
--- /dev/null
+++ b/src/mainboard/google/fatcat/variants/lapis/memory/mem_parts_used.txt
@@ -0,0 +1,14 @@
+# This is a CSV file containing a list of memory parts used by this variant.
+# One part per line with an optional fixed ID in column 2.
+# Only include a fixed ID if it is required for legacy reasons!
+# Generated IDs are dependent on the order of parts in this file,
+# so new parts must always be added at the end of the file!
+#
+# Generate an updated Makefile.mk and dram_id.generated.txt by running the
+# part_id_gen tool from util/spd_tools.
+# See util/spd_tools/README.md for more details and instructions.
+
+# Part Name
+H58G66CK8BX147
+K3KL9L90EM-MGCU
+MT62F2G32D4DS-023 WT:C
diff --git a/src/mainboard/google/fatcat/variants/lapis/overridetree.cb b/src/mainboard/google/fatcat/variants/lapis/overridetree.cb
new file mode 100644
index 0000000000..3231689c82
--- /dev/null
+++ b/src/mainboard/google/fatcat/variants/lapis/overridetree.cb
@@ -0,0 +1,388 @@
+chip soc/intel/pantherlake
+
+	register "power_limits_config[PTL_U_1_CORE]" = "{
+		.tdp_pl1_override = 15,
+		.tdp_pl2_override = 25,
+	}"
+
+	register "power_limits_config[PTL_H_1_CORE]" = "{
+		.tdp_pl1_override = 25,
+		.tdp_pl2_override = 25,
+	}"
+
+	register "power_limits_config[PTL_H_2_CORE]" = "{
+		.tdp_pl1_override = 25,
+		.tdp_pl2_override = 25,
+	}"
+
+	register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC_SKIP)" # USB2_C0
+	register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC_SKIP)" # USB2_C1
+	register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # LED
+	register "usb2_ports[3]" = "USB2_PORT_MID(OC_SKIP)" # Type-A Port A0 (MB)
+	register "usb2_ports[4]" = "USB2_PORT_MID(OC_SKIP)" # Type-A Port A1 (DB)
+	register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)" # USB HUB (USB2 Camera)
+	register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" # Fingerprint
+	register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # Discrete Bluetooth
+
+	register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB3.2 x1 Type-A Con #1 (MB)/
+	register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB3.2 x1 Type-A Con #2 (DB)/
+
+	register "tcss_ports[0]" = "TCSS_PORT_DEFAULT(OC_SKIP)"
+	register "tcss_ports[2]" = "TCSS_PORT_DEFAULT(OC_SKIP)"
+
+	register "tcss_cap_policy[0]" = "TCSS_TYPE_C_PORT_FULL_FUN"
+	register "tcss_cap_policy[2]" = "TCSS_TYPE_C_PORT_FULL_FUN"
+
+	# Enable EDP in PortA
+	register "ddi_port_A_config" = "1"
+	register "ddi_ports_config" = "{
+			[DDI_PORT_A] = DDI_ENABLE_HPD,
+	}"
+
+	# Enable CNVi Wi-Fi and Bluetooth
+	register "cnvi_wifi_core" = "true"
+	register "cnvi_bt_core" = "true"
+
+	register "serial_io_i2c_mode" = "{
+		[PchSerialIoIndexI2C0]  = PchSerialIoPci,
+		[PchSerialIoIndexI2C3]  = PchSerialIoPci,
+	}"
+
+	# Intel Common SoC Config
+	#+-------------------+---------------------------+
+	#| Field             |  Value                    |
+	#+-------------------+---------------------------+
+	#| I2C3              | cr50 TPM.                 |
+	#+-------------------+---------------------------+
+	register "common_soc_config" = "{
+		.logo_valignment = FW_SPLASH_VALIGNMENT_MIDDLE,
+		.i2c[3] = {
+			.speed = I2C_SPEED_FAST,
+		},
+	}"
+
+	device domain 0 on
+		device ref dtt on
+			chip drivers/intel/dptf
+				## sensor information
+				register "options.tsr[0].desc" = ""DDR_SOC""
+				register "options.tsr[1].desc" = ""Ambient""
+				register "options.tsr[2].desc" = ""Charger""
+				register "options.tsr[3].desc" = ""wwan""
+
+				## Active Policy
+				# FIXME: below values are initial reference values only
+				register "policies.active" = "{
+						[0] = {
+							.target = DPTF_TEMP_SENSOR_0,
+							.thresholds = {
+									TEMP_PCT(70, 97),
+									TEMP_PCT(65, 90),
+									TEMP_PCT(60, 80),
+									TEMP_PCT(55, 75),
+									TEMP_PCT(50, 65),
+									TEMP_PCT(45, 45),
+									TEMP_PCT(43, 30),
+								}
+							},
+						[1] = {
+							.target = DPTF_TEMP_SENSOR_1,
+							.thresholds = {
+									TEMP_PCT(70, 97),
+									TEMP_PCT(65, 90),
+									TEMP_PCT(60, 80),
+									TEMP_PCT(55, 75),
+									TEMP_PCT(50, 65),
+									TEMP_PCT(45, 45),
+									TEMP_PCT(43, 30),
+								}
+							},
+						[2] = {
+							.target = DPTF_TEMP_SENSOR_2,
+							.thresholds = {
+									TEMP_PCT(75, 90),
+									TEMP_PCT(70, 80),
+									TEMP_PCT(65, 70),
+									TEMP_PCT(60, 50),
+								}
+							},
+						[3] = {
+							.target = DPTF_TEMP_SENSOR_3,
+							.thresholds = {
+									TEMP_PCT(75, 90),
+									TEMP_PCT(70, 80),
+									TEMP_PCT(65, 70),
+									TEMP_PCT(60, 60),
+									TEMP_PCT(55, 50),
+									TEMP_PCT(50, 40),
+									TEMP_PCT(45, 30),
+								}
+							}
+				}"
+
+				## Passive Policy
+				# TODO: below values are initial reference values only
+				register "policies.passive" = "{
+						[0] = DPTF_PASSIVE(CPU,         CPU,           95, 5000),
+						[1] = DPTF_PASSIVE(CPU,         TEMP_SENSOR_0, 80, 5000),
+						[2] = DPTF_PASSIVE(CPU,         TEMP_SENSOR_1, 80, 5000),
+						[3] = DPTF_PASSIVE(CHARGER,     TEMP_SENSOR_2, 75, 5000),
+						[4] = DPTF_PASSIVE(CPU,         TEMP_SENSOR_3, 80, 5000),
+				}"
+
+				## Critical Policy
+				# TODO: below values are initial reference values only
+				register "policies.critical" = "{
+						[0] = DPTF_CRITICAL(CPU,          105, SHUTDOWN),
+						[1] = DPTF_CRITICAL(TEMP_SENSOR_0, 85, SHUTDOWN),
+						[2] = DPTF_CRITICAL(TEMP_SENSOR_1, 85, SHUTDOWN),
+						[3] = DPTF_CRITICAL(TEMP_SENSOR_2, 85, SHUTDOWN),
+						[4] = DPTF_CRITICAL(TEMP_SENSOR_3, 85, SHUTDOWN),
+				}"
+
+				## Power Limits Control
+				register "controls.power_limits" = "{
+						.pl1 = {
+							.min_power = 25000,
+							.max_power = 25000,
+							.time_window_min = 28 * MSECS_PER_SEC,
+							.time_window_max = 32 * MSECS_PER_SEC,
+							.granularity = 200,
+						},
+						.pl2 = {
+							.min_power = 95000,
+							.max_power = 95000,
+							.time_window_min = 28 * MSECS_PER_SEC,
+							.time_window_max = 32 * MSECS_PER_SEC,
+							.granularity = 1000,
+						}
+				}"
+
+				## Charger Performance Control (Control, mA)
+				register "controls.charger_perf" = "{
+						[0] = { 255, 3000 },
+						[1] = {  24, 1500 },
+						[2] = {  16, 1000 },
+						[3] = {   8,  500 }
+				}"
+
+				## Fan Performance Control (Percent, Speed, Noise, Power)
+				register "controls.fan_perf" = "{
+						[0] = {  90, 6700, 220, 2200, },
+						[1] = {  80, 5800, 180, 1800, },
+						[2] = {  70, 5000, 145, 1450, },
+						[3] = {  60, 4900, 115, 1150, },
+						[4] = {  50, 3838,  90,  900, },
+						[5] = {  40, 2904,  55,  550, },
+						[6] = {  30, 2337,  30,  300, },
+						[7] = {  20, 1608,  15,  150, },
+						[8] = {  10,  800,  10,  100, },
+						[9] = {   0,    0,   0,   50, }
+				}"
+
+				## Fan options
+				register "options.fan.fine_grained_control" = "true"
+				register "options.fan.step_size" = "2"
+
+				device generic 0 alias dptf_policy on end
+			end
+		end
+		device ref igpu on
+			chip drivers/gfx/generic
+				register "device_count" = "4"
+				# DDIA for eDP
+				register "device[0].name" = ""LCD0""
+				register "device[0].type" = "panel"
+				# DDIB for HDMI
+				# If HDMI is not enumerated in the kernel, then no GFX device should be added for DDIB
+				register "device[1].name" = ""DD01""
+				# TCP0 (DP-1) for port C0
+				register "device[2].name" = ""DD02""
+				register "device[2].use_pld" = "true"
+				register "device[2].pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(2, 1))"
+				# TCP1 (DP-2) for port C1
+				register "device[3].name" = ""DD03""
+				register "device[3].use_pld" = "true"
+				register "device[3].pld" = "ACPI_PLD_TYPE_C(LEFT, RIGHT, ACPI_PLD_GROUP(1, 1))"
+				device generic 0 on end
+			end
+		end
+		device ref ipu on end
+		device ref iaa off end
+		device ref tbt_pcie_rp0 on end
+		device ref tbt_pcie_rp2 on end
+		device ref tcss_xhci on
+			chip drivers/usb/acpi
+				device ref tcss_root_hub on
+					chip drivers/usb/acpi
+						register "desc" = ""USB3 Type-C Port C1""
+						register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
+						register "group" = "ACPI_PLD_GROUP(1, 2)"
+						device ref tcss_usb3_port0 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB3 Type-C Port C0""
+						register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
+						register "group" = "ACPI_PLD_GROUP(2, 2)"
+						device ref tcss_usb3_port2 on end
+					end
+				end
+			end
+		end
+
+		device ref tcss_dma0 on
+			chip drivers/intel/usb4/retimer
+				register "dfp[0].power_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B21)"
+				use tcss_usb3_port0 as dfp[0].typec_port
+				device generic 0 on end
+			end
+		end
+		device ref tcss_dma1 on
+			chip drivers/intel/usb4/retimer
+				register "dfp[0].power_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B21)"
+				use tcss_usb3_port2 as dfp[0].typec_port
+				device generic 0 on end
+			end
+		end
+
+		device ref xhci on
+			chip drivers/usb/acpi
+				device ref xhci_root_hub on
+					chip drivers/usb/acpi
+						register "desc" = ""USB2 Type-C Port C1""
+						register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
+						register "group" = "ACPI_PLD_GROUP(1, 1)"
+						device ref usb2_port1 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB2 Type-C Port C0""
+						register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
+						register "group" = "ACPI_PLD_GROUP(2, 1)"
+						device ref usb2_port2 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB2 LED""
+						register "type" = "UPC_TYPE_INTERNAL"
+						register "group" = "ACPI_PLD_GROUP(3, 1)"
+						device ref usb2_port3 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB2 Type-A Port 0""
+						register "type" = "UPC_TYPE_A"
+						register "group" = "ACPI_PLD_GROUP(4, 1)"
+						device ref usb2_port4 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB2 Type-A Port 1""
+						register "type" = "UPC_TYPE_A"
+						register "group" = "ACPI_PLD_GROUP(5, 1)"
+						device ref usb2_port5 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""User Facing Camera""
+						register "type" = "UPC_TYPE_INTERNAL"
+						register "has_power_resource" = "true"
+						register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C06)"
+						register "enable_delay_ms" = "20"
+						device ref usb2_port6 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB2 Fingerprint""
+						register "type" = "UPC_TYPE_INTERNAL"
+						register "group" = "ACPI_PLD_GROUP(7, 1)"
+						device ref usb2_port7 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB2 Bluetooth""
+						register "type" = "UPC_TYPE_INTERNAL"
+						register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A16)"
+						device ref usb2_port8 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB3 Type-A Port 0""
+						register "type" = "UPC_TYPE_USB3_A"
+						register "group" = "ACPI_PLD_GROUP(4, 2)"
+						device ref usb3_port1 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB3 Type-A Port 1""
+						register "type" = "UPC_TYPE_USB3_A"
+						register "group" = "ACPI_PLD_GROUP(5, 2)"
+						device ref usb3_port2 on end
+					end
+				end
+			end
+		end
+
+		device ref pcie_rp9 on
+			register "pcie_rp[PCIE_RP(9)]" = "{
+			.clk_src = 0,
+			.clk_req = 0,
+			.flags = PCIE_RP_CLK_REQ_DETECT | PCIE_RP_LTR | PCIE_RP_AER,
+			}"
+			chip soc/intel/common/block/pcie/rtd3
+				register "is_storage" = "true"
+				register "srcclk_pin" = "0"
+				device generic 0 on end
+			end
+		end # Gen4 SSD
+
+		device ref cnvi_wifi on
+			chip drivers/wifi/generic
+				register "wake" = "GPE0_PME_B0"
+				register "add_acpi_dma_property" = "true"
+				register "enable_cnvi_ddr_rfim" = "true"
+				use cnvi_bluetooth as bluetooth_companion
+				device generic 0 on end
+			end
+		end # CNVi
+
+		device ref cnvi_bluetooth on end
+
+		device ref thc0 on
+			register "thc_wake_on_touch[0]" = "true"
+			# THC0 is function 0; hence it needs to be enabled when THC1 is to be enabled.
+			chip drivers/intel/touch
+				register "name" = "INTEL_THC0_NAME"
+				register "mode" = "THC_HID_I2C_MODE"
+				register "dev_hidi2c.hid" = ""RAYD0001""
+				register "dev_hidi2c.cid" = ""PNP0C50""
+				register "dev_hidi2c.intf.hidi2c.addr" = "0x39"
+				register "dev_hidi2c.intf.hidi2c.descriptor_address" = "0x1"
+				register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E11)"
+				register "wake_on_touch" = "true"
+				# NOTE: Use GpioInt() in _CRS and does not use GPE.
+				register "wake_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW_WAKE(GPP_VGPIO3_THC0)"
+				register "active_ltr" = "1"
+				register "idle_ltr" = "0"
+				register "connected_device" = "TH_SENSOR_GENERIC"
+				register "add_acpi_dma_property" = "true"
+				device generic 0 on end
+			end
+		end #Touchpenal
+		device ref thc1 on
+			register "thc_wake_on_touch[1]" = "true"
+			chip drivers/intel/touch
+				register "name" = "INTEL_THC1_NAME"
+				register "mode" = "THC_HID_I2C_MODE"
+				register "wake_on_touch" = "true"
+				# NOTE: Use GpioInt() in _CRS and does not use GPE.
+				register "wake_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW_WAKE(GPP_VGPIO3_THC1)"
+				register "active_ltr" = "1"
+				register "idle_ltr" = "0"
+				register "connected_device" = "TH_SENSOR_GENERIC"
+				register "add_acpi_dma_property" = "true"
+				device generic 0 on end
+			end
+		end #Touchpad
+
+		device ref i2c0 on end
+		device ref i2c3 on
+			chip drivers/i2c/tpm
+				register "hid" = ""GOOG0005""
+				register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_E02_IRQ)"
+				device i2c 50 on end
+			end
+		end # I2C3
+	end
+end

From c1128ae64918b2fdb50d7d29b2fff11f55c5a1b7 Mon Sep 17 00:00:00 2001
From: Kapil Porwal <kapilporwal@google.com>
Date: Mon, 25 Aug 2025 09:34:13 +0530
Subject: [PATCH 1842/3886] soc/qualcomm/cmn: Add SPMI driver

Add Qualcomm PMIC ARB driver.

BUG=b:438004604
TEST=Communicate with IPMI slaves.

Change-Id: Id872068ea377175a791e478b45e02aa9fcc4327d
Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88926
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 .../qualcomm/common/include/soc/qcom_spmi.h   |  12 ++
 src/soc/qualcomm/common/spmi.c                | 127 ++++++++++++++++++
 2 files changed, 139 insertions(+)
 create mode 100644 src/soc/qualcomm/common/include/soc/qcom_spmi.h
 create mode 100644 src/soc/qualcomm/common/spmi.c

diff --git a/src/soc/qualcomm/common/include/soc/qcom_spmi.h b/src/soc/qualcomm/common/include/soc/qcom_spmi.h
new file mode 100644
index 0000000000..1c0ae6121f
--- /dev/null
+++ b/src/soc/qualcomm/common/include/soc/qcom_spmi.h
@@ -0,0 +1,12 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#ifndef __SOC_QCOM_SPMI_H__
+#define __SOC_QCOM_SPMI_H__
+
+#include <stddef.h>
+#include <stdint.h>
+
+int spmi_read8(uint32_t addr);
+int spmi_write8(uint32_t addr, uint8_t data);
+
+#endif	// __SOC_QCOM_SPMI_H__
diff --git a/src/soc/qualcomm/common/spmi.c b/src/soc/qualcomm/common/spmi.c
new file mode 100644
index 0000000000..51a37058b0
--- /dev/null
+++ b/src/soc/qualcomm/common/spmi.c
@@ -0,0 +1,127 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+
+#include <arch/mmio.h>
+#include <commonlib/bsd/stdlib.h>
+#include <soc/addressmap.h>
+#include <soc/qcom_spmi.h>
+#include <timer.h>
+
+#define PPID_MASK		(0xfffU << 8)
+
+/* These are opcodes specific to this SPMI arbitrator, *not* SPMI commands. */
+#define OPC_EXT_WRITEL		0
+#define OPC_EXT_READL		1
+
+#define ARB_STATUS_DONE		BIT(0)
+#define ARB_STATUS_FAILURE	BIT(1)
+#define ARB_STATUS_DENIED	BIT(2)
+#define ARB_STATUS_DROPPED	BIT(3)
+
+#define ERROR_APID_NOT_FOUND	(-(int)BIT(8))
+#define ERROR_TIMEOUT		(-(int)BIT(9))
+
+#define ARB_COMMAND_TIMEOUT_MS	100
+
+// Individual register block per APID
+struct qcom_spmi_regs {
+	uint32_t cmd;
+	uint32_t config;
+	uint32_t status;
+	uint32_t _reserved0;
+	uint32_t wdata0;
+	uint32_t wdata1;
+	uint32_t rdata0;
+	uint32_t rdata1;
+	uint8_t _reserved_empty_until_next_apid[SPMI_PMIC_ARB_CHANNEL_SIZE - 0x20];
+};
+check_member(qcom_spmi_regs, rdata1, 0x1c);
+_Static_assert(sizeof(struct qcom_spmi_regs) == SPMI_PMIC_ARB_CHANNEL_SIZE,
+	       "struct qcom_spmi_regs must be " STRINGIFY(SPMI_PMIC_ARB_CHANNEL_SIZE) " bytes per APID");
+
+struct qcom_spmi {
+	struct qcom_spmi_regs *regs_per_apid;	// indexed by APID
+	uint32_t *apid_map;
+	size_t num_apid;
+};
+
+struct qcom_spmi qcom_spmi = {
+	(void *) SPMI_PMIC_ARB_CHANNEL_BASE,
+	(void *) SPMI_PMIC_ARB_APID_MAP_BASE,
+	SPMI_PMIC_ARB_APID_COUNT
+};
+
+static struct qcom_spmi_regs *find_apid(uint32_t addr)
+{
+	size_t i;
+
+	for (i = 0U; i < qcom_spmi.num_apid; i++) {
+		uint32_t reg = read32(&qcom_spmi.apid_map[i]);
+		if ((reg != 0U) && ((addr & PPID_MASK) == (reg & PPID_MASK)))
+			return &qcom_spmi.regs_per_apid[i];
+	}
+
+	return NULL;
+}
+
+static int wait_for_done(struct qcom_spmi_regs *regs)
+{
+	struct stopwatch sw;
+
+	stopwatch_init_msecs_expire(&sw, ARB_COMMAND_TIMEOUT_MS);
+	while (!stopwatch_expired(&sw)) {
+		uint32_t status = read32(&regs->status);
+		if ((status & ARB_STATUS_DONE) != 0U) {
+			if ((status & ARB_STATUS_FAILURE) != 0U ||
+			    (status & ARB_STATUS_DENIED) != 0U ||
+			    (status & ARB_STATUS_DROPPED) != 0U)
+				return -(int)(status & 0xff);
+			return 0;
+		}
+	}
+	printk(BIOS_ERR, "ERROR: SPMI_ARB timeout!\n");
+	return ERROR_TIMEOUT;
+}
+
+static void arb_command(struct qcom_spmi_regs *regs, uint8_t opcode, uint32_t addr,
+			uint8_t bytes)
+{
+	write32(&regs->cmd, (uint32_t)opcode << 27 |
+			    (addr & 0xff) << 4 | (bytes - 1));
+}
+
+int spmi_read8(uint32_t addr)
+{
+	struct qcom_spmi_regs *regs = find_apid(addr);
+
+	if (!regs)
+		return ERROR_APID_NOT_FOUND;
+
+	arb_command(regs, OPC_EXT_READL, addr, 1);
+
+	int ret = wait_for_done(regs);
+	if (ret != 0) {
+		printk(BIOS_ERR, "ERROR: SPMI_ARB read error [0x%x]: 0x%x\n", addr, ret);
+		return ret;
+	}
+
+	return read32(&regs->rdata0) & 0xff;
+}
+
+int spmi_write8(uint32_t addr, uint8_t data)
+{
+	struct qcom_spmi_regs *regs = find_apid(addr);
+
+	if (!regs)
+		return ERROR_APID_NOT_FOUND;
+
+	write32(&regs->wdata0, data);
+	arb_command(regs, OPC_EXT_WRITEL, addr, 1);
+
+	int ret = wait_for_done(regs);
+	if (ret != 0) {
+		printk(BIOS_ERR, "ERROR: SPMI_ARB write error [0x%x] = 0x%x: 0x%x\n",
+			addr, data, ret);
+	}
+
+	return ret;
+}

From 17a88540fd81154284838d836a6771dd93b074a5 Mon Sep 17 00:00:00 2001
From: Kapil Porwal <kapilporwal@google.com>
Date: Mon, 25 Aug 2025 09:38:33 +0530
Subject: [PATCH 1843/3886] soc/qualcomm/x1p42100: Use SPMI driver

Use SPMI PMIC ARB driver to communicate with SPMI slave devices.

BUG=b:438004604
TEST=Communicate with SPMI slaves.

Change-Id: I44b7249d82abdbb82cb53d9c9aa04ce8bbff068b
Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88927
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
---
 src/soc/qualcomm/x1p42100/Makefile.mk              | 1 +
 src/soc/qualcomm/x1p42100/include/soc/addressmap.h | 9 +++++++++
 2 files changed, 10 insertions(+)

diff --git a/src/soc/qualcomm/x1p42100/Makefile.mk b/src/soc/qualcomm/x1p42100/Makefile.mk
index c483b5f691..86aeb36fa4 100644
--- a/src/soc/qualcomm/x1p42100/Makefile.mk
+++ b/src/soc/qualcomm/x1p42100/Makefile.mk
@@ -36,6 +36,7 @@ romstage-y += qclib.c
 romstage-y += mmu.c
 romstage-y += ../common/aop_load_reset.c
 romstage-$(CONFIG_DRIVERS_UART) += ../common/qupv3_uart.c
+romstage-y += ../common/spmi.c
 
 ################################################################################
 ramstage-y += soc.c
diff --git a/src/soc/qualcomm/x1p42100/include/soc/addressmap.h b/src/soc/qualcomm/x1p42100/include/soc/addressmap.h
index 79e2b782e9..bfb51ad7b2 100644
--- a/src/soc/qualcomm/x1p42100/include/soc/addressmap.h
+++ b/src/soc/qualcomm/x1p42100/include/soc/addressmap.h
@@ -113,4 +113,13 @@
 #define TCSR_GCC_PCIE_4L_CLKREF_EN_PCIE_ENABLE           ((void *)0x1FD512C)
 #define TCSR_PCIE_CTRL_4LN_CONFIG_SEL            ((void *)0x1FDA000)
 
+/* SPMI PMIC ARB */
+#define SPMI_PMIC_ARB_CORE_BASE		0x0C400000
+#define FIRST_APID_MAP_OFFSET		0x2000
+#define LAST_APID_MAP_OFFSET		0x3000
+#define SPMI_PMIC_ARB_APID_COUNT	((LAST_APID_MAP_OFFSET - FIRST_APID_MAP_OFFSET) / 4)
+#define SPMI_PMIC_ARB_APID_MAP_BASE	(SPMI_PMIC_ARB_CORE_BASE + FIRST_APID_MAP_OFFSET)
+#define SPMI_PMIC_ARB_CHANNEL_BASE	0x0C500000
+#define SPMI_PMIC_ARB_CHANNEL_SIZE	0x1000
+
 #endif /*  __SOC_QUALCOMM_X1P42100_ADDRESS_MAP_H__ */

From 6781f458eec800e6be897cc0b82f0c644d998991 Mon Sep 17 00:00:00 2001
From: Luca Lai <luca.lai@lcfc.corp-partner.google.com>
Date: Sat, 23 Aug 2025 00:06:30 +0800
Subject: [PATCH 1844/3886] mb/google/trulo/var/pujjolo: Enable fivr settings

Add fivr related setting based on schematics 500E_S3A0_TWL_MB_FVT_20250527.pdf

BUG=b:437881361
TEST=Build and boot to OS, check suspend funtion work fine using
suspend_stress_test -c 5 command.

Change-Id: I6c7f2807cc6a9c7c82e28d26205b33d068792522
Signed-off-by: Luca Lai <luca.lai@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88907
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
---
 src/mainboard/google/brya/variants/pujjolo/overridetree.cb | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/src/mainboard/google/brya/variants/pujjolo/overridetree.cb b/src/mainboard/google/brya/variants/pujjolo/overridetree.cb
index 7e009e001f..9b88e4b54a 100644
--- a/src/mainboard/google/brya/variants/pujjolo/overridetree.cb
+++ b/src/mainboard/google/brya/variants/pujjolo/overridetree.cb
@@ -91,6 +91,10 @@ chip soc/intel/alderlake
 	register "pch_hda_sdi_enable[0]" = "true"
 	register "pch_hda_sdi_enable[1]" = "true"
 
+	# Configure external V1P05/Vnn/VnnSx Rails for Pujjolo
+	register "ext_fivr_settings" = "{
+		.configure_ext_fivr = 1,
+	}"
 
 	# Intel Common SoC Config
 	#+-------------------+---------------------------+

From f94469c2a937497dd4172fc21951c3896571cf63 Mon Sep 17 00:00:00 2001
From: Luca Lai <luca.lai@lcfc.corp-partner.google.com>
Date: Sat, 23 Aug 2025 01:14:58 +0800
Subject: [PATCH 1845/3886] mb/google/nissa/var/pujjolo/pujjoquince: Add wifi
 sar table

Add AX211 and BE200 wifi sar table for pujjolo/pujjoquince
wifi sar config. Use fw_config to separate different wifi card settings.

WIFI_SAR_TABLE_PUJJOLO_AX211		:0
WIFI_SAR_TABLE_PUJJOLO_BE200		:1
WIFI_SAR_TABLE_PUJJOQUINCE_AX211	:2
option WIFI_SAR_TABLE_PUJJOQUINCE_BE200	:3

BUG=b:428071905
Test=emerge-nissa coreboot

Change-Id: Iea8b32a19c4c2116afb5e5e4014dbc32e484ae3e
Signed-off-by: Luca Lai <luca.lai@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88908
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
---
 src/mainboard/google/brya/variants/pujjolo/overridetree.cb | 6 ++++--
 src/mainboard/google/brya/variants/pujjolo/variant.c       | 5 +++++
 2 files changed, 9 insertions(+), 2 deletions(-)

diff --git a/src/mainboard/google/brya/variants/pujjolo/overridetree.cb b/src/mainboard/google/brya/variants/pujjolo/overridetree.cb
index 9b88e4b54a..2b8d56cf10 100644
--- a/src/mainboard/google/brya/variants/pujjolo/overridetree.cb
+++ b/src/mainboard/google/brya/variants/pujjolo/overridetree.cb
@@ -5,8 +5,10 @@ fw_config
 		option 5G_PRESENT		2
 	end
 	field WIFI_SAR_ID 17 20
-		option WIFI_SAR_TABLE_AX211	0
-		option WIFI_SAR_TABLE_AX203	1
+		option WIFI_SAR_TABLE_PUJJOLO_AX211		0
+		option WIFI_SAR_TABLE_PUJJOLO_BE200		1
+		option WIFI_SAR_TABLE_PUJJOQUINCE_AX211		2
+		option WIFI_SAR_TABLE_PUJJOQUINCE_BE200		3
 	end
 	field PDC 21 22
 		option PDC_PUJJOQUINCE        0
diff --git a/src/mainboard/google/brya/variants/pujjolo/variant.c b/src/mainboard/google/brya/variants/pujjolo/variant.c
index e92119ae8c..e4af9cd12d 100644
--- a/src/mainboard/google/brya/variants/pujjolo/variant.c
+++ b/src/mainboard/google/brya/variants/pujjolo/variant.c
@@ -2,6 +2,7 @@
 
 #include <baseboard/variants.h>
 #include <chip.h>
+#include <sar.h>
 #include <fw_config.h>
 #include <soc/gpio_soc_defs.h>
 #include <intelblocks/graphics.h>
@@ -9,6 +10,10 @@
 #include <acpi/acpigen.h>
 #include <variant/gpio.h>
 
+const char *get_wifi_sar_cbfs_filename(void)
+{
+	return get_wifi_sar_fw_config_filename(FW_CONFIG_FIELD(WIFI_SAR_ID));
+}
 
 void variant_generate_s0ix_hook(enum s0ix_entry entry)
 {

From a1dd6bfc22cebeea4a623b1e222dbd709224e92d Mon Sep 17 00:00:00 2001
From: Kilian Krause <kilian.krause@siemens.com>
Date: Wed, 4 Jun 2025 10:22:20 +0200
Subject: [PATCH 1846/3886] mb/siemens/mc_rpl1: Adjust PCIe settings in
 devicetree

This mainboard does not utilize CKLREQ signaling for PCIe. Only three
PCIe clock sources are used on this board. Configure the Root Ports
accordingly to hardware implementation.

Change-Id: If4241a05dd0c5df258d4a7018d71a21f7d314e69
Signed-off-by: Kilian Krause <kilian.krause@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88879
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/siemens/mc_rpl/devicetree.cb    | 67 -------------------
 .../mc_rpl/variants/mc_rpl1/overridetree.cb   | 55 ++++++++++++++-
 2 files changed, 54 insertions(+), 68 deletions(-)

diff --git a/src/mainboard/siemens/mc_rpl/devicetree.cb b/src/mainboard/siemens/mc_rpl/devicetree.cb
index fd582dfbb1..8b701d7638 100644
--- a/src/mainboard/siemens/mc_rpl/devicetree.cb
+++ b/src/mainboard/siemens/mc_rpl/devicetree.cb
@@ -32,65 +32,6 @@ chip soc/intel/alderlake
 	register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC0)"	# USB3/2 Type A port3
 	register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)"	# M.2 WWAN
 
-	# Enable PCH PCIE RP 5 using CLK 2
-	register "pch_pcie_rp[PCH_RP(5)]" = "{
-		.clk_src = 2,
-		.clk_req = 2,
-		.flags = PCIE_RP_CLK_REQ_DETECT,
-	}"
-
-	# Enable PCH PCIE RP 6 using CLK 5
-	register "pch_pcie_rp[PCH_RP(6)]" = "{
-		.clk_src = 5,
-		.clk_req = 5,
-		.flags = PCIE_RP_CLK_REQ_DETECT,
-	}"
-
-	# NOTE: requires GPP_A7 set to Native Function 1 for SRCCLK_OE7
-	register "pch_pcie_rp[PCH_RP(8)]" = "{
-                .clk_src = 7,
-                .clk_req = 7,
-                .flags = PCIE_RP_CLK_REQ_DETECT | PCIE_RP_LTR,
-                .PcieRpL1Substates = L1_SS_L1_2,
-		.pcie_rp_detect_timeout_ms = 50,
-	}"
-
-	# Enable PCH PCIE RP 9 using CLK 1
-	register "pch_pcie_rp[PCH_RP(9)]" = "{
-		.clk_src = 1,
-		.clk_req = 1,
-		.flags = PCIE_RP_CLK_REQ_DETECT,
-	}"
-
-	# Enable PCH PCIE RP 11 for optane
-	register "pch_pcie_rp[PCH_RP(11)]" = "{
-		.flags = PCIE_RP_CLK_SRC_UNUSED,
-	}"
-
-	# Hybrid storage mode
-	register "hybrid_storage_mode" = "true"
-
-	# Enable CPU PCIE RP 1 using CLK 0
-	register "cpu_pcie_rp[CPU_RP(1)]" = "{
-		.clk_req = 0,
-		.clk_src = 0,
-		.flags = PCIE_RP_LTR | PCIE_RP_AER,
-	}"
-
-	# Enable CPU PCIE RP 2 using CLK 3
-	register "cpu_pcie_rp[CPU_RP(2)]" = "{
-		.clk_req = 3,
-		.clk_src = 3,
-		.flags = PCIE_RP_LTR | PCIE_RP_AER,
-	}"
-
-	# Enable CPU PCIE RP 3 using CLK 4
-	register "cpu_pcie_rp[CPU_RP(3)]" = "{
-		.clk_req = 4,
-		.clk_src = 4,
-		.flags = PCIE_RP_LTR | PCIE_RP_AER,
-	}"
-
 	register "sata_salp_support" = "1"
 
 	register "sata_ports_enable" = "{
@@ -185,7 +126,6 @@ chip soc/intel/alderlake
 	}"
 
 	device domain 0 on
-		device ref pcie5_0 on end
 		device ref igpu on end
 		device ref dtt on
 			chip drivers/intel/dptf
@@ -297,8 +237,6 @@ chip soc/intel/alderlake
 				device generic 0 on end
 			end
 		end
-		device ref pcie4_0 on end
-		device ref pcie4_1 on end
 		device ref crashlog off end
 		device ref xhci on
 			chip drivers/usb/acpi
@@ -409,11 +347,6 @@ chip soc/intel/alderlake
 				device i2c 36 on end
 			end
 		end
-		device ref pcie_rp5 on end
-		device ref pcie_rp6 on end
-		device ref pcie_rp8 on end
-		device ref pcie_rp9 on end
-		device ref pcie_rp11 on end
 		device ref uart0 on end
 		device ref gspi0 on end
 		device ref p2sb on end
diff --git a/src/mainboard/siemens/mc_rpl/variants/mc_rpl1/overridetree.cb b/src/mainboard/siemens/mc_rpl/variants/mc_rpl1/overridetree.cb
index 8747164f32..be098df1f2 100644
--- a/src/mainboard/siemens/mc_rpl/variants/mc_rpl1/overridetree.cb
+++ b/src/mainboard/siemens/mc_rpl/variants/mc_rpl1/overridetree.cb
@@ -3,5 +3,58 @@ chip soc/intel/alderlake
 	# seen on J0 and Q0 SKUs
 	register "disable_package_c_state_demotion" = "true"
 
-	device domain 0 on end
+	device domain 0 on
+		register "pcie_clk_config_flag[0]" = "PCIE_CLK_FREE_RUNNING"
+		register "pcie_clk_config_flag[1]" = "PCIE_CLK_FREE_RUNNING"
+		register "pcie_clk_config_flag[2]" = "PCIE_CLK_FREE_RUNNING"
+
+		device ref pcie4_0 on
+			register "cpu_pcie_rp[CPU_RP(1)]" = "{
+				.clk_src = 0,
+				.flags = PCIE_RP_CLK_REQ_UNUSED,
+			}"
+		end
+		device ref pcie4_1 on
+			register "cpu_pcie_rp[CPU_RP(2)]" = "{
+				.clk_src = 0,
+				.flags = PCIE_RP_CLK_REQ_UNUSED,
+			}"
+		end
+		device ref pcie_rp3 on
+			register "pch_pcie_rp[PCH_RP(3)]" = "{
+				.clk_src = 0,
+				.flags = PCIE_RP_CLK_REQ_UNUSED,
+			}"
+		end
+		device ref pcie_rp4 on
+			register "pch_pcie_rp[PCH_RP(4)]" = "{
+				.clk_src = 0,
+				.flags = PCIE_RP_CLK_REQ_UNUSED,
+			}"
+		end
+		device ref pcie_rp5 on
+			register "pch_pcie_rp[PCH_RP(5)]" = "{
+				.clk_src = 1,
+				.flags = PCIE_RP_CLK_REQ_UNUSED,
+			}"
+		end
+		device ref pcie_rp6 on
+			register "pch_pcie_rp[PCH_RP(6)]" = "{
+				.clk_src = 0,
+				.flags = PCIE_RP_CLK_REQ_UNUSED,
+			}"
+		end
+		device ref pcie_rp7 on
+			register "pch_pcie_rp[PCH_RP(7)]" = "{
+				.clk_src = 0,
+				.flags = PCIE_RP_CLK_REQ_UNUSED,
+			}"
+		end
+		device ref pcie_rp8 on
+			register "pch_pcie_rp[PCH_RP(8)]" = "{
+				.clk_src = 0,
+				.flags = PCIE_RP_CLK_REQ_UNUSED,
+			}"
+		end
+	end
 end

From 296f5968d3f79004ca1fc89cf2d7df489249c843 Mon Sep 17 00:00:00 2001
From: Kilian Krause <kilian.krause@siemens.com>
Date: Mon, 23 Jun 2025 10:30:35 +0200
Subject: [PATCH 1847/3886] mb/siemens/mc_rpl1: Adjust I2C bus enablement in
 devicetree

This mainboard only uses I2C0 and I2C1. Disable all the others. Move I2C
configuration from baseboard to variant.

Change-Id: I0c554ea4da948bc96d6a392c39bcb07a25a79eb4
Signed-off-by: Kilian Krause <kilian.krause@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88880
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/siemens/mc_rpl/devicetree.cb    | 112 ------------------
 .../mc_rpl/variants/mc_rpl1/overridetree.cb   |  21 ++++
 2 files changed, 21 insertions(+), 112 deletions(-)

diff --git a/src/mainboard/siemens/mc_rpl/devicetree.cb b/src/mainboard/siemens/mc_rpl/devicetree.cb
index 8b701d7638..ff7e9f636d 100644
--- a/src/mainboard/siemens/mc_rpl/devicetree.cb
+++ b/src/mainboard/siemens/mc_rpl/devicetree.cb
@@ -58,15 +58,6 @@ chip soc/intel/alderlake
 	register "s0ix_enable" = "true"
 	register "dptf_enable" = "true"
 
-	register "serial_io_i2c_mode" = "{
-		[PchSerialIoIndexI2C0] = PchSerialIoPci,
-		[PchSerialIoIndexI2C1] = PchSerialIoPci,
-		[PchSerialIoIndexI2C2] = PchSerialIoPci,
-		[PchSerialIoIndexI2C3] = PchSerialIoPci,
-		[PchSerialIoIndexI2C4] = PchSerialIoDisabled,
-		[PchSerialIoIndexI2C5] = PchSerialIoPci,
-	}"
-
 	register "serial_io_gspi_mode" = "{
 		[PchSerialIoIndexGSPI0] = PchSerialIoPci,
 		[PchSerialIoIndexGSPI1] = PchSerialIoPci,
@@ -108,21 +99,6 @@ chip soc/intel/alderlake
 			.speed_mhz = 1,
 			.early_init = 1,
 		},
-		.i2c[0] = {
-			.speed = I2C_SPEED_FAST,
-		},
-		.i2c[1] = {
-			.speed = I2C_SPEED_FAST,
-		},
-		.i2c[2] = {
-			.speed = I2C_SPEED_FAST,
-		},
-		.i2c[3] = {
-			.speed = I2C_SPEED_FAST,
-		},
-		.i2c[5] = {
-			.speed = I2C_SPEED_FAST,
-		},
 	}"
 
 	device domain 0 on
@@ -257,96 +233,8 @@ chip soc/intel/alderlake
 				device generic 0 on end
 			end
 		end
-		device ref i2c0 on end
-		device ref i2c1 on
-			chip drivers/intel/mipi_camera
-				register "acpi_hid" = ""OVTI5675""
-				register "acpi_uid" = "0"
-				register "acpi_name" = ""CAM0""
-				register "chip_name" = ""Ov 5675 Camera""
-				register "device_type" = "INTEL_ACPI_CAMERA_SENSOR"
-
-				register "ssdb.lanes_used" = "2"
-				register "ssdb.vcm_type" = "0x0C"
-				register "vcm_name" = ""VCM0""
-				register "num_freq_entries" = "1"
-				register "link_freq[0]" = "450000000"
-				register "remote_name" = ""IPU0""
-
-				register "has_power_resource" = "true"
-				#Controls
-				register "clk_panel.clks[0].clknum" = "0" #IMGCLKOUT_0
-				register "clk_panel.clks[0].freq" = "1" #19.2 Mhz
-				register "gpio_panel.gpio[0].gpio_num" = "GPP_B23" #power_enable
-				register "gpio_panel.gpio[1].gpio_num" = "GPP_R5" #reset
-
-				#_ON
-				register "on_seq.ops_cnt" = "4"
-				register "on_seq.ops[0]" = "SEQ_OPS_CLK_ENABLE(0, 0)"
-				register "on_seq.ops[1]" = "SEQ_OPS_GPIO_ENABLE(0, 2)"
-				register "on_seq.ops[2]" = "SEQ_OPS_GPIO_DISABLE(1, 1)"
-				register "on_seq.ops[3]" = "SEQ_OPS_GPIO_ENABLE(1, 1)"
-
-				#_OFF
-				register "off_seq.ops_cnt" = "3"
-				register "off_seq.ops[0]" = "SEQ_OPS_CLK_DISABLE(0, 0)"
-				register "off_seq.ops[1]" = "SEQ_OPS_GPIO_DISABLE(1, 0)"
-				register "off_seq.ops[2]" = "SEQ_OPS_GPIO_DISABLE(0, 0)"
-
-				device i2c 36 on end
-			end
-			chip drivers/intel/mipi_camera
-				register "acpi_uid" = "3"
-				register "acpi_name" = ""VCM0""
-				register "chip_name" = ""DW AF VCM""
-				register "device_type" = "INTEL_ACPI_CAMERA_VCM"
-
-				register "pr0" = ""\\_SB.PCI0.I2C1.CAM0.PRIC""
-				register "vcm_compat" = ""dongwoon,dw9714""
-
-				device i2c 0C on end
-			end
-		end
-		device ref i2c2 on end
-		device ref i2c3 on end
 		device ref heci1 on end
 		device ref sata on end
-		device ref i2c5 on
-			chip drivers/intel/mipi_camera
-				register "acpi_hid" = ""OVTI5675""
-				register "acpi_uid" = "0"
-				register "acpi_name" = ""CAM1""
-				register "chip_name" = ""Ov 5675 Camera""
-				register "device_type" = "INTEL_ACPI_CAMERA_SENSOR"
-
-				register "ssdb.lanes_used" = "2"
-				register "num_freq_entries" = "1"
-				register "link_freq[0]" = "450000000"
-				register "remote_name" = ""IPU0""
-
-				register "has_power_resource" = "true"
-				#Controls
-				register "clk_panel.clks[0].clknum" = "1" #IMGCLKOUT_1
-				register "clk_panel.clks[0].freq" = "1" #19.2 Mhz
-				register "gpio_panel.gpio[0].gpio_num" = "GPP_E16" #power_enable
-				register "gpio_panel.gpio[1].gpio_num" = "GPP_E15" #reset
-
-				#_ON
-				register "on_seq.ops_cnt" = "4"
-				register "on_seq.ops[0]" = "SEQ_OPS_CLK_ENABLE(0, 0)"
-				register "on_seq.ops[1]" = "SEQ_OPS_GPIO_ENABLE(0, 2)"
-				register "on_seq.ops[2]" = "SEQ_OPS_GPIO_DISABLE(1, 1)"
-				register "on_seq.ops[3]" = "SEQ_OPS_GPIO_ENABLE(1, 1)"
-
-				#_OFF
-				register "off_seq.ops_cnt" = "3"
-				register "off_seq.ops[0]" = "SEQ_OPS_CLK_DISABLE(0, 0)"
-				register "off_seq.ops[1]" = "SEQ_OPS_GPIO_DISABLE(1, 0)"
-				register "off_seq.ops[2]" = "SEQ_OPS_GPIO_DISABLE(0, 0)"
-
-				device i2c 36 on end
-			end
-		end
 		device ref uart0 on end
 		device ref gspi0 on end
 		device ref p2sb on end
diff --git a/src/mainboard/siemens/mc_rpl/variants/mc_rpl1/overridetree.cb b/src/mainboard/siemens/mc_rpl/variants/mc_rpl1/overridetree.cb
index be098df1f2..b4e7a34b19 100644
--- a/src/mainboard/siemens/mc_rpl/variants/mc_rpl1/overridetree.cb
+++ b/src/mainboard/siemens/mc_rpl/variants/mc_rpl1/overridetree.cb
@@ -3,6 +3,25 @@ chip soc/intel/alderlake
 	# seen on J0 and Q0 SKUs
 	register "disable_package_c_state_demotion" = "true"
 
+	register "serial_io_i2c_mode" = "{
+		[PchSerialIoIndexI2C0] = PchSerialIoPci,
+		[PchSerialIoIndexI2C1] = PchSerialIoPci,
+		[PchSerialIoIndexI2C2] = PchSerialIoDisabled,
+		[PchSerialIoIndexI2C3] = PchSerialIoDisabled,
+		[PchSerialIoIndexI2C4] = PchSerialIoDisabled,
+		[PchSerialIoIndexI2C5] = PchSerialIoDisabled,
+	}"
+
+	# Intel Common SoC Config
+	register "common_soc_config" = "{
+		.i2c[0] = {
+			.speed = I2C_SPEED_FAST,
+		},
+		.i2c[1] = {
+			.speed = I2C_SPEED_FAST,
+		},
+	}"
+
 	device domain 0 on
 		register "pcie_clk_config_flag[0]" = "PCIE_CLK_FREE_RUNNING"
 		register "pcie_clk_config_flag[1]" = "PCIE_CLK_FREE_RUNNING"
@@ -56,5 +75,7 @@ chip soc/intel/alderlake
 				.flags = PCIE_RP_CLK_REQ_UNUSED,
 			}"
 		end
+		device ref i2c0 on end
+		device ref i2c1 on end
 	end
 end

From 71c4619045d9c79a86c7c2f1b6b76d1996e8b32b Mon Sep 17 00:00:00 2001
From: Kilian Krause <kilian.krause@siemens.com>
Date: Mon, 23 Jun 2025 18:16:36 +0200
Subject: [PATCH 1848/3886] mb/siemens/mc_rpl: Remove unused devices from
 devicetree and Kconfig

Remove unused device entries from devicetree.cb and Kconfig files for
PCIe, audio, camera, WiFi and Bluetooth.

Change-Id: I8c45736e0f7f6887a0863c72c4ca2e6854b4349d
Signed-off-by: Kilian Krause <kilian.krause@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88881
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/siemens/mc_rpl/Kconfig       | 25 ---------
 src/mainboard/siemens/mc_rpl/devicetree.cb | 62 +---------------------
 2 files changed, 1 insertion(+), 86 deletions(-)

diff --git a/src/mainboard/siemens/mc_rpl/Kconfig b/src/mainboard/siemens/mc_rpl/Kconfig
index d775a470f0..2a14f332de 100644
--- a/src/mainboard/siemens/mc_rpl/Kconfig
+++ b/src/mainboard/siemens/mc_rpl/Kconfig
@@ -5,25 +5,16 @@ config BOARD_SIEMENS_BASEBOARD_MC_RPL
 	select BOARD_ROMSIZE_KB_16384
 	select CPU_INTEL_SOCKET_LGA1700
 	select DRIVERS_I2C_GENERIC
-	select DRIVERS_I2C_HID
-	select DRIVERS_I2C_MAX98373
 	select DRIVERS_INTEL_DPTF
-	select DRIVERS_INTEL_MIPI_CAMERA
-	select DRIVERS_INTEL_SOUNDWIRE
-	select DRIVERS_SOUNDWIRE_ALC_BASE_7XX
 	select DRIVERS_SPI_ACPI
 	select DRIVERS_USB_ACPI
 	select HAVE_ACPI_RESUME
 	select HAVE_ACPI_TABLES
-	select SOC_INTEL_COMMON_BLOCK_IPU
-	select SOC_INTEL_CSE_LITE_SKU
 	select USE_SIEMENS_HWILIB
 
 
 config BOARD_SIEMENS_MC_RPL1
 	select BOARD_SIEMENS_BASEBOARD_MC_RPL
-	select DRIVERS_UART_8250IO
-	select GEN3_EXTERNAL_CLOCK_BUFFER
 	select SOC_INTEL_ALDERLAKE_PCH_P
 	select SOC_INTEL_RAPTORLAKE
 
@@ -68,20 +59,4 @@ config DRIVER_TPM_SPI_BUS
 
 config USE_PM_ACPI_TIMER
 	default n if BOARD_SIEMENS_MC_RPL1
-
-config GEN3_EXTERNAL_CLOCK_BUFFER
-	bool
-	depends on SOC_INTEL_ALDERLAKE_PCH_P
-	default n
-	help
-	  Support external Gen-3 clock chip for ADL-P.
-	  `CONFIG_CLKSRC_FOR_EXTERNAL_BUFFER` provides feed clock to discrete buffer
-	  for further distribution to platform. SRCCLKREQB[7:9] maps to internal
-	  SRCCLKREQB[6]. If any of them asserted, SRC buffer
-	  `CONFIG_CLKSRC_FOR_EXTERNAL_BUFFER` gets enabled.
-
-config CLKSRC_FOR_EXTERNAL_BUFFER
-	depends on GEN3_EXTERNAL_CLOCK_BUFFER
-	int
-	default 6  # CLKSRC 6
 endif
diff --git a/src/mainboard/siemens/mc_rpl/devicetree.cb b/src/mainboard/siemens/mc_rpl/devicetree.cb
index ff7e9f636d..8f84038f10 100644
--- a/src/mainboard/siemens/mc_rpl/devicetree.cb
+++ b/src/mainboard/siemens/mc_rpl/devicetree.cb
@@ -10,9 +10,6 @@ chip soc/intel/alderlake
 
 	# FSP configuration
 
-	# Enable CNVi BT
-	register "cnvi_bt_core" = "true"
-
 	# Sagv Configuration
 	register "sagv" = "SaGv_Enabled"
 
@@ -48,13 +45,6 @@ chip soc/intel/alderlake
 		[3] = 1,
 	}"
 
-	# Enable EDP in PortA
-	register "ddi_portA_config" = "1"
-	# Enable HDMI in Port B
-	register "ddi_ports_config" = "{
-		[DDI_PORT_B] = DDI_ENABLE_HPD | DDI_ENABLE_DDC,
-	}"
-
 	register "s0ix_enable" = "true"
 	register "dptf_enable" = "true"
 
@@ -85,14 +75,6 @@ chip soc/intel/alderlake
 		[PchSerialIoIndexUART2] = PchSerialIoDisabled,
 	}"
 
-	# HD Audio
-	register "pch_hda_dsp_enable" = "1"
-	register "pch_hda_idisp_link_tmode" = "HDA_TMODE_8T"
-	register "pch_hda_idisp_link_frequency" = "HDA_LINKFREQ_96MHZ"
-	register "pch_hda_idisp_codec_enable" = "1"
-
-	register "cnvi_bt_audio_offload" = "true"
-
 	# Intel Common SoC Config
 	register "common_soc_config" = "{
 		.gspi[1] = {
@@ -198,42 +180,14 @@ chip soc/intel/alderlake
 				device generic 0 alias dptf_policy on end
 			end
 		end
-		device ref ipu on
-			chip drivers/intel/mipi_camera
-				register "acpi_uid" = "0x50000"
-				register "acpi_name" = ""IPU0""
-				register "device_type" = "INTEL_ACPI_CAMERA_CIO2"
-
-				register "cio2_num_ports" = "2"
-				register "cio2_lanes_used" = "{2,2}"
-				register "cio2_lane_endpoint[0]" = ""^I2C5.CAM1""
-				register "cio2_lane_endpoint[1]" = ""^I2C1.CAM0""
-				register "cio2_prt[0]" = "2"
-				register "cio2_prt[1]" = "1"
-				device generic 0 on end
-			end
-		end
 		device ref crashlog off end
 		device ref xhci on
 			chip drivers/usb/acpi
 				register "desc" = ""Root Hub""
 				register "type" = "UPC_TYPE_HUB"
-				device ref xhci_root_hub on
-					chip drivers/usb/acpi
-						register "desc" = ""Bluetooth""
-						register "type" = "UPC_TYPE_INTERNAL"
-						device ref usb2_port10 on end
-					end
-				end
+				device ref xhci_root_hub on end
 			end
 		end
-		device ref cnvi_wifi on
-			chip drivers/wifi/generic
-				register "wake" = "GPE0_PME_B0"
-				device generic 0 on end
-			end
-		end
-		device ref heci1 on end
 		device ref sata on end
 		device ref uart0 on end
 		device ref gspi0 on end
@@ -246,20 +200,6 @@ chip soc/intel/alderlake
 				device spi 0 on end
 			end
 		end
-		device ref hda on
-			chip drivers/intel/soundwire
-				device generic 0 on
-					chip drivers/soundwire/alc711
-						# SoundWire Link 0 ID 1
-						register "desc" = ""Headset Codec""
-						register "alc711_address.version" = "SOUNDWIRE_VERSION_1_1"
-						register "alc711_address.class" = "MIPI_CLASS_NONE"
-						register "alc711_address.part_id" = "MIPI_DEV_ID_REALTEK_ALC711"
-						device generic 0.1 on end
-					end
-				end
-			end
-		end
 		device ref smbus on end
 	end
 end

From 6427e51c4fb11a0b450c0b0a00557f64472c9def Mon Sep 17 00:00:00 2001
From: Kilian Krause <kilian.krause@siemens.com>
Date: Thu, 5 Jun 2025 13:13:19 +0200
Subject: [PATCH 1849/3886] mb/siemens/mc_rpl1: Adjust USB port settings in
 devicetree

In total three USB ports are used:
- Port 1: Type A connector connected to USB2/USB3 port 0
- Port 2: Type A connector connected to USB2/USB3 port 1
- Onboard: connected to USB2 port 2
Overcurrent reporting is not supported for these ports.

Remove the appropriate UPDs in devicetree and move them to the
variant level to match the hardware configuration.

Change-Id: I9ab02780cfc11f88ddd2bb52bd7fbfb3fdd450ef
Signed-off-by: Kilian Krause <kilian.krause@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88882
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
---
 src/mainboard/siemens/mc_rpl/devicetree.cb    | 23 --------------
 .../mc_rpl/variants/mc_rpl1/overridetree.cb   | 30 +++++++++++++++++++
 2 files changed, 30 insertions(+), 23 deletions(-)

diff --git a/src/mainboard/siemens/mc_rpl/devicetree.cb b/src/mainboard/siemens/mc_rpl/devicetree.cb
index 8f84038f10..20526071c9 100644
--- a/src/mainboard/siemens/mc_rpl/devicetree.cb
+++ b/src/mainboard/siemens/mc_rpl/devicetree.cb
@@ -13,22 +13,6 @@ chip soc/intel/alderlake
 	# Sagv Configuration
 	register "sagv" = "SaGv_Enabled"
 
-	register "usb2_ports[0]" = "USB2_PORT_MID(OC0)"		# Type-C Port1
-	register "usb2_ports[1]" = "USB2_PORT_MID(OC0)"		# Type-C Port2
-	register "usb2_ports[2]" = "USB2_PORT_MID(OC3)"		# Type-C Port3
-	register "usb2_ports[3]" = "USB2_PORT_MID(OC_SKIP)"	# M.2 WWAN
-	register "usb2_ports[4]" = "USB2_PORT_MID(OC3)"		# Type-C Port4
-	register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)"	# FPS connector
-	register "usb2_ports[6]" = "USB2_PORT_MID(OC0)"		# USB3/2 Type A port1
-	register "usb2_ports[7]" = "USB2_PORT_MID(OC0)"		# USB3/2 Type A port2
-	register "usb2_ports[8]" = "USB2_PORT_MID(OC3)"		# USB3/2 Type A port3
-	register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)"	# M.2 WLAN
-
-	register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC3)"	# USB3/2 Type A port1
-	register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC0)"	# USB3/2 Type A port2
-	register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC0)"	# USB3/2 Type A port3
-	register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)"	# M.2 WWAN
-
 	register "sata_salp_support" = "1"
 
 	register "sata_ports_enable" = "{
@@ -181,13 +165,6 @@ chip soc/intel/alderlake
 			end
 		end
 		device ref crashlog off end
-		device ref xhci on
-			chip drivers/usb/acpi
-				register "desc" = ""Root Hub""
-				register "type" = "UPC_TYPE_HUB"
-				device ref xhci_root_hub on end
-			end
-		end
 		device ref sata on end
 		device ref uart0 on end
 		device ref gspi0 on end
diff --git a/src/mainboard/siemens/mc_rpl/variants/mc_rpl1/overridetree.cb b/src/mainboard/siemens/mc_rpl/variants/mc_rpl1/overridetree.cb
index b4e7a34b19..e6ac72007d 100644
--- a/src/mainboard/siemens/mc_rpl/variants/mc_rpl1/overridetree.cb
+++ b/src/mainboard/siemens/mc_rpl/variants/mc_rpl1/overridetree.cb
@@ -3,6 +3,22 @@ chip soc/intel/alderlake
 	# seen on J0 and Q0 SKUs
 	register "disable_package_c_state_demotion" = "true"
 
+	register "usb2_ports[0]" = "USB2_PORT_MID(OC_SKIP)"	# Port1
+	register "usb2_ports[1]" = "USB2_PORT_MID(OC_SKIP)"	# Port2
+	register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)"	# Onboard USB
+	register "usb2_ports[3]" = "USB2_PORT_EMPTY"		# Port is unused
+	register "usb2_ports[4]" = "USB2_PORT_EMPTY"		# Port is unused
+	register "usb2_ports[5]" = "USB2_PORT_EMPTY"		# Port is unused
+	register "usb2_ports[6]" = "USB2_PORT_EMPTY"		# Port is unused
+	register "usb2_ports[7]" = "USB2_PORT_EMPTY"		# Port is unused
+	register "usb2_ports[8]" = "USB2_PORT_EMPTY"		# Port is unused
+	register "usb2_ports[9]" = "USB2_PORT_EMPTY"		# Port is unused
+
+	register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB3/2 Type A port1
+	register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB3/2 Type A port2
+	register "usb3_ports[2]" = "USB3_PORT_EMPTY"		# Port is unused
+	register "usb3_ports[3]" = "USB3_PORT_EMPTY"		# Port is unused
+
 	register "serial_io_i2c_mode" = "{
 		[PchSerialIoIndexI2C0] = PchSerialIoPci,
 		[PchSerialIoIndexI2C1] = PchSerialIoPci,
@@ -77,5 +93,19 @@ chip soc/intel/alderlake
 		end
 		device ref i2c0 on end
 		device ref i2c1 on end
+		device ref xhci on
+			chip drivers/usb/acpi
+				register "desc" = ""Root Hub""
+				register "type" = "UPC_TYPE_HUB"
+				device ref xhci_root_hub on
+					chip drivers/usb/acpi
+						device ref usb3_port1 on end
+					end
+					chip drivers/usb/acpi
+						device ref usb3_port2 on end
+					end
+				end
+			end
+		end
 	end
 end

From c7cd4e33059342b9a9a90307a525045524950d34 Mon Sep 17 00:00:00 2001
From: Kilian Krause <kilian.krause@siemens.com>
Date: Mon, 21 Jul 2025 10:29:28 +0200
Subject: [PATCH 1850/3886] mb/siemens/mc_rpl: Move SOC selection to baseboard

Move the SOC-specific Kconfig options from the variant to the baseboard
configuration. This ensures all variants will inherit the correct SOC
selection.

This simplifies configuration and ensures consistency across variants.

Change-Id: Icf13ebd022dbe35f7c5deadfb425f1f9b572ed86
Signed-off-by: Kilian Krause <kilian.krause@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88883
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
---
 src/mainboard/siemens/mc_rpl/Kconfig | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/mainboard/siemens/mc_rpl/Kconfig b/src/mainboard/siemens/mc_rpl/Kconfig
index 2a14f332de..66cea4d8c8 100644
--- a/src/mainboard/siemens/mc_rpl/Kconfig
+++ b/src/mainboard/siemens/mc_rpl/Kconfig
@@ -11,12 +11,12 @@ config BOARD_SIEMENS_BASEBOARD_MC_RPL
 	select HAVE_ACPI_RESUME
 	select HAVE_ACPI_TABLES
 	select USE_SIEMENS_HWILIB
+	select SOC_INTEL_ALDERLAKE_PCH_P
+	select SOC_INTEL_RAPTORLAKE
 
 
 config BOARD_SIEMENS_MC_RPL1
 	select BOARD_SIEMENS_BASEBOARD_MC_RPL
-	select SOC_INTEL_ALDERLAKE_PCH_P
-	select SOC_INTEL_RAPTORLAKE
 
 if BOARD_SIEMENS_BASEBOARD_MC_RPL
 

From 524fd18bd6abe1d93b02f64dfc5ef3e181cfbaaf Mon Sep 17 00:00:00 2001
From: Kilian Krause <kilian.krause@siemens.com>
Date: Tue, 17 Jun 2025 14:35:54 +0200
Subject: [PATCH 1851/3886] mb/siemens/mc_rpl1: Create variant specific Kconfig
 file

A variant specific Kconfig file is introduced. This improves
configuration management by separating variant-specific options from the
baseboard.

Change-Id: I3760bf0ec2d16722ba99459244968ef2db249453
Signed-off-by: Kilian Krause <kilian.krause@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88884
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
---
 src/mainboard/siemens/mc_rpl/Kconfig                  | 2 ++
 src/mainboard/siemens/mc_rpl/variants/mc_rpl1/Kconfig | 8 ++++++++
 2 files changed, 10 insertions(+)
 create mode 100644 src/mainboard/siemens/mc_rpl/variants/mc_rpl1/Kconfig

diff --git a/src/mainboard/siemens/mc_rpl/Kconfig b/src/mainboard/siemens/mc_rpl/Kconfig
index 66cea4d8c8..ca02e06124 100644
--- a/src/mainboard/siemens/mc_rpl/Kconfig
+++ b/src/mainboard/siemens/mc_rpl/Kconfig
@@ -18,6 +18,8 @@ config BOARD_SIEMENS_BASEBOARD_MC_RPL
 config BOARD_SIEMENS_MC_RPL1
 	select BOARD_SIEMENS_BASEBOARD_MC_RPL
 
+source "src/mainboard/siemens/mc_rpl/variants/*/Kconfig"
+
 if BOARD_SIEMENS_BASEBOARD_MC_RPL
 
 config MAINBOARD_DIR
diff --git a/src/mainboard/siemens/mc_rpl/variants/mc_rpl1/Kconfig b/src/mainboard/siemens/mc_rpl/variants/mc_rpl1/Kconfig
new file mode 100644
index 0000000000..bee8ace103
--- /dev/null
+++ b/src/mainboard/siemens/mc_rpl/variants/mc_rpl1/Kconfig
@@ -0,0 +1,8 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
+if BOARD_SIEMENS_MC_RPL1
+
+config BOARD_SPECIFIC_OPTIONS
+	def_bool y
+
+endif # BOARD_SIEMENS_MC_RPL1

From 2bcd7f15221735e19983b9bd8e50dd9b6d87bbf3 Mon Sep 17 00:00:00 2001
From: Kilian Krause <kilian.krause@siemens.com>
Date: Thu, 5 Jun 2025 15:08:31 +0200
Subject: [PATCH 1852/3886] mb/siemens/mc_rpl1: Adjust UART settings and enable
 LPSS UART

Enable UART0, UART1 and UART2 in the devicetree. Adjust current UART
console configuration from UART0 to UART2. Additionally, enable LPSS
UART for the coreboot console on UART2.

Change-Id: I4ba521b3edd6a37f726a256a26051d5ab9acadfc
Signed-off-by: Kilian Krause <kilian.krause@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88885
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/siemens/mc_rpl/Kconfig                     | 5 -----
 src/mainboard/siemens/mc_rpl/devicetree.cb               | 7 -------
 src/mainboard/siemens/mc_rpl/variants/mc_rpl1/Kconfig    | 5 +++++
 .../siemens/mc_rpl/variants/mc_rpl1/overridetree.cb      | 9 +++++++++
 4 files changed, 14 insertions(+), 12 deletions(-)

diff --git a/src/mainboard/siemens/mc_rpl/Kconfig b/src/mainboard/siemens/mc_rpl/Kconfig
index ca02e06124..4902b49a44 100644
--- a/src/mainboard/siemens/mc_rpl/Kconfig
+++ b/src/mainboard/siemens/mc_rpl/Kconfig
@@ -14,7 +14,6 @@ config BOARD_SIEMENS_BASEBOARD_MC_RPL
 	select SOC_INTEL_ALDERLAKE_PCH_P
 	select SOC_INTEL_RAPTORLAKE
 
-
 config BOARD_SIEMENS_MC_RPL1
 	select BOARD_SIEMENS_BASEBOARD_MC_RPL
 
@@ -48,10 +47,6 @@ config OVERRIDE_DEVICETREE
 config FMDFILE
 	default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/mc_rpl.fmd"
 
-config UART_FOR_CONSOLE
-	int
-	default 0
-
 config DIMM_SPD_SIZE
 	int
 	default 256
diff --git a/src/mainboard/siemens/mc_rpl/devicetree.cb b/src/mainboard/siemens/mc_rpl/devicetree.cb
index 20526071c9..46c8b7bbae 100644
--- a/src/mainboard/siemens/mc_rpl/devicetree.cb
+++ b/src/mainboard/siemens/mc_rpl/devicetree.cb
@@ -53,12 +53,6 @@ chip soc/intel/alderlake
 		[PchSerialIoIndexGSPI3] = 0,
 	}"
 
-	register "serial_io_uart_mode" = "{
-		[PchSerialIoIndexUART0] = PchSerialIoSkipInit,
-		[PchSerialIoIndexUART1] = PchSerialIoDisabled,
-		[PchSerialIoIndexUART2] = PchSerialIoDisabled,
-	}"
-
 	# Intel Common SoC Config
 	register "common_soc_config" = "{
 		.gspi[1] = {
@@ -166,7 +160,6 @@ chip soc/intel/alderlake
 		end
 		device ref crashlog off end
 		device ref sata on end
-		device ref uart0 on end
 		device ref gspi0 on end
 		device ref p2sb on end
 		device ref gspi1 on
diff --git a/src/mainboard/siemens/mc_rpl/variants/mc_rpl1/Kconfig b/src/mainboard/siemens/mc_rpl/variants/mc_rpl1/Kconfig
index bee8ace103..9f2d691d0e 100644
--- a/src/mainboard/siemens/mc_rpl/variants/mc_rpl1/Kconfig
+++ b/src/mainboard/siemens/mc_rpl/variants/mc_rpl1/Kconfig
@@ -4,5 +4,10 @@ if BOARD_SIEMENS_MC_RPL1
 
 config BOARD_SPECIFIC_OPTIONS
 	def_bool y
+	select INTEL_LPSS_UART_FOR_CONSOLE
+
+config UART_FOR_CONSOLE
+	int
+	default 2
 
 endif # BOARD_SIEMENS_MC_RPL1
diff --git a/src/mainboard/siemens/mc_rpl/variants/mc_rpl1/overridetree.cb b/src/mainboard/siemens/mc_rpl/variants/mc_rpl1/overridetree.cb
index e6ac72007d..e95e8b8a22 100644
--- a/src/mainboard/siemens/mc_rpl/variants/mc_rpl1/overridetree.cb
+++ b/src/mainboard/siemens/mc_rpl/variants/mc_rpl1/overridetree.cb
@@ -28,6 +28,12 @@ chip soc/intel/alderlake
 		[PchSerialIoIndexI2C5] = PchSerialIoDisabled,
 	}"
 
+	register "serial_io_uart_mode" = "{
+		[PchSerialIoIndexUART0] = PchSerialIoSkipInit,
+		[PchSerialIoIndexUART1] = PchSerialIoSkipInit,
+		[PchSerialIoIndexUART2] = PchSerialIoSkipInit,
+	}"
+
 	# Intel Common SoC Config
 	register "common_soc_config" = "{
 		.i2c[0] = {
@@ -107,5 +113,8 @@ chip soc/intel/alderlake
 				end
 			end
 		end
+		device ref uart0 on end
+		device ref uart1 on end
+		device ref uart2 on end
 	end
 end

From 2b26ea0eda2d1065ce7e84929f4e80b4584bb92f Mon Sep 17 00:00:00 2001
From: Kilian Krause <kilian.krause@siemens.com>
Date: Tue, 10 Jun 2025 12:15:51 +0200
Subject: [PATCH 1853/3886] mb/siemens/mc_rpl1: Configure SPI and implement TPM
 support

Configure SPI according to the mainboard wiring. Disable GSPI completely
as it is unused on this platform. Enable FSPI and configure it to
interface with the TPM device.

Implement TPM measured boot functionality starting from bootblock to
ensure secure boot chain validation from the earliest boot stage.

Change-Id: I89b60101c94393816b51154459f39bb22d5b976d
Signed-off-by: Kilian Krause <kilian.krause@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88886
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
---
 src/mainboard/siemens/mc_rpl/Kconfig          |  3 --
 src/mainboard/siemens/mc_rpl/devicetree.cb    | 38 -------------------
 .../siemens/mc_rpl/variants/mc_rpl1/Kconfig   |  4 ++
 .../mc_rpl/variants/mc_rpl1/overridetree.cb   | 12 ++++++
 4 files changed, 16 insertions(+), 41 deletions(-)

diff --git a/src/mainboard/siemens/mc_rpl/Kconfig b/src/mainboard/siemens/mc_rpl/Kconfig
index 4902b49a44..5281bb5d86 100644
--- a/src/mainboard/siemens/mc_rpl/Kconfig
+++ b/src/mainboard/siemens/mc_rpl/Kconfig
@@ -51,9 +51,6 @@ config DIMM_SPD_SIZE
 	int
 	default 256
 
-config DRIVER_TPM_SPI_BUS
-	default 0x2 if BOARD_SIEMENS_MC_RPL1
-
 config USE_PM_ACPI_TIMER
 	default n if BOARD_SIEMENS_MC_RPL1
 endif
diff --git a/src/mainboard/siemens/mc_rpl/devicetree.cb b/src/mainboard/siemens/mc_rpl/devicetree.cb
index 46c8b7bbae..a5af508a2f 100644
--- a/src/mainboard/siemens/mc_rpl/devicetree.cb
+++ b/src/mainboard/siemens/mc_rpl/devicetree.cb
@@ -32,35 +32,6 @@ chip soc/intel/alderlake
 	register "s0ix_enable" = "true"
 	register "dptf_enable" = "true"
 
-	register "serial_io_gspi_mode" = "{
-		[PchSerialIoIndexGSPI0] = PchSerialIoPci,
-		[PchSerialIoIndexGSPI1] = PchSerialIoPci,
-		[PchSerialIoIndexGSPI2] = PchSerialIoDisabled,
-		[PchSerialIoIndexGSPI3] = PchSerialIoDisabled,
-	}"
-
-	register "serial_io_gspi_cs_mode" = "{
-		[PchSerialIoIndexGSPI0] = 0,
-		[PchSerialIoIndexGSPI1] = 1,
-		[PchSerialIoIndexGSPI2] = 0,
-		[PchSerialIoIndexGSPI3] = 0,
-	}"
-
-	register "serial_io_gspi_cs_state" = "{
-		[PchSerialIoIndexGSPI0] = 0,
-		[PchSerialIoIndexGSPI1] = 0,
-		[PchSerialIoIndexGSPI2] = 0,
-		[PchSerialIoIndexGSPI3] = 0,
-	}"
-
-	# Intel Common SoC Config
-	register "common_soc_config" = "{
-		.gspi[1] = {
-			.speed_mhz = 1,
-			.early_init = 1,
-		},
-	}"
-
 	device domain 0 on
 		device ref igpu on end
 		device ref dtt on
@@ -160,16 +131,7 @@ chip soc/intel/alderlake
 		end
 		device ref crashlog off end
 		device ref sata on end
-		device ref gspi0 on end
 		device ref p2sb on end
-		device ref gspi1 on
-			chip drivers/spi/acpi
-				register "hid" = "ACPI_DT_NAMESPACE_HID"
-				register "compat_string" = ""google,cr50""
-				register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_E3_IRQ)"
-				device spi 0 on end
-			end
-		end
 		device ref smbus on end
 	end
 end
diff --git a/src/mainboard/siemens/mc_rpl/variants/mc_rpl1/Kconfig b/src/mainboard/siemens/mc_rpl/variants/mc_rpl1/Kconfig
index 9f2d691d0e..f57e2cbf0d 100644
--- a/src/mainboard/siemens/mc_rpl/variants/mc_rpl1/Kconfig
+++ b/src/mainboard/siemens/mc_rpl/variants/mc_rpl1/Kconfig
@@ -5,6 +5,10 @@ if BOARD_SIEMENS_MC_RPL1
 config BOARD_SPECIFIC_OPTIONS
 	def_bool y
 	select INTEL_LPSS_UART_FOR_CONSOLE
+	select MAINBOARD_HAS_TPM2
+	select MEMORY_MAPPED_TPM
+	select TPM_MEASURED_BOOT
+	select TPM_MEASURED_BOOT_INIT_BOOTBLOCK
 
 config UART_FOR_CONSOLE
 	int
diff --git a/src/mainboard/siemens/mc_rpl/variants/mc_rpl1/overridetree.cb b/src/mainboard/siemens/mc_rpl/variants/mc_rpl1/overridetree.cb
index e95e8b8a22..b6ba91a40d 100644
--- a/src/mainboard/siemens/mc_rpl/variants/mc_rpl1/overridetree.cb
+++ b/src/mainboard/siemens/mc_rpl/variants/mc_rpl1/overridetree.cb
@@ -19,6 +19,13 @@ chip soc/intel/alderlake
 	register "usb3_ports[2]" = "USB3_PORT_EMPTY"		# Port is unused
 	register "usb3_ports[3]" = "USB3_PORT_EMPTY"		# Port is unused
 
+	register "serial_io_gspi_mode" = "{
+		[PchSerialIoIndexGSPI0] = PchSerialIoDisabled,
+		[PchSerialIoIndexGSPI1] = PchSerialIoDisabled,
+		[PchSerialIoIndexGSPI2] = PchSerialIoDisabled,
+		[PchSerialIoIndexGSPI3] = PchSerialIoDisabled,
+	}"
+
 	register "serial_io_i2c_mode" = "{
 		[PchSerialIoIndexI2C0] = PchSerialIoPci,
 		[PchSerialIoIndexI2C1] = PchSerialIoPci,
@@ -116,5 +123,10 @@ chip soc/intel/alderlake
 		device ref uart0 on end
 		device ref uart1 on end
 		device ref uart2 on end
+		device ref fast_spi on
+			chip drivers/pc80/tpm   # SPI TPM header
+				device pnp 0c31.0 on end
+			end
+		end
 	end
 end

From dcb7c317c2ec3034b926945c0faf2334a0b9b7d6 Mon Sep 17 00:00:00 2001
From: Kilian Krause <kilian.krause@siemens.com>
Date: Tue, 10 Jun 2025 17:18:10 +0200
Subject: [PATCH 1854/3886] mb/siemens/mc_rpl1: Enable Intel I210 MACPHY driver

Enable the i210 driver for this variant which uses I210 MACPHYs.
Additionally, add a function to retrieve a valid MAC Address for the
given MACPHY.

Change-Id: If519194f52910e4ace59095a997bafff7eab44ca
Signed-off-by: Kilian Krause <kilian.krause@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88887
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
---
 src/mainboard/siemens/mc_rpl/mainboard.c      | 79 +++++++++++++++++++
 .../siemens/mc_rpl/variants/mc_rpl1/Kconfig   |  1 +
 2 files changed, 80 insertions(+)

diff --git a/src/mainboard/siemens/mc_rpl/mainboard.c b/src/mainboard/siemens/mc_rpl/mainboard.c
index 46741323c8..fe3e1e6216 100644
--- a/src/mainboard/siemens/mc_rpl/mainboard.c
+++ b/src/mainboard/siemens/mc_rpl/mainboard.c
@@ -6,6 +6,85 @@
 #include <soc/gpio.h>
 #include <stdint.h>
 #include <stdio.h>
+#include <hwilib.h>
+#include <i210.h>
+
+
+#define MAX_PATH_DEPTH		12
+#define MAX_NUM_MAPPINGS	10
+
+/** \brief This function can decide if a given MAC address is valid or not.
+*	  Currently, addresses filled with 0xff or 0x00 are not valid.
+ * @param  mac	Buffer to the MAC address to check
+ * @return 0	if address is not valid, otherwise 1
+ */
+static uint8_t is_mac_adr_valid(uint8_t mac[MAC_ADDR_LEN])
+{
+	for (size_t i = 0; i < MAC_ADDR_LEN; i++) {
+		if (mac[i] != 0x00 && mac[i] != 0xff)
+			return 1;
+		if (mac[i] != mac[0])
+			return 1;
+	}
+	return 0;
+}
+
+/** \brief This function will search for a MAC address which can be assigned
+ *	   to a MACPHY.
+ * @param  dev	   pointer to PCI device
+ * @param  mac	   buffer where to store the MAC address
+ * @return cb_err  CB_ERR or CB_SUCCESS
+ */
+
+enum cb_err mainboard_get_mac_address(struct device *dev, uint8_t mac[MAC_ADDR_LEN])
+{
+	struct bus *parent = dev->upstream;
+	uint8_t buf[16], mapping[16], i = 0, chain_len = 0;
+
+	memset(buf, 0, sizeof(buf));
+	memset(mapping, 0, sizeof(mapping));
+
+	/* The first entry in the tree is the device itself. */
+	buf[0] = dev->path.pci.devfn;
+	chain_len = 1;
+	for (i = 1; i < MAX_PATH_DEPTH && parent->dev->upstream->subordinate; i++) {
+		buf[i] = parent->dev->path.pci.devfn;
+		chain_len++;
+		parent = parent->dev->upstream;
+	}
+	if (i == MAX_PATH_DEPTH) {
+		/* The path is deeper than MAX_PATH_DEPTH devices, error. */
+		printk(BIOS_ERR, "Too many bridges for %s\n", dev_path(dev));
+		return CB_ERR;
+	}
+	/*
+	* Now construct the mapping based on the device chain starting from
+	* root bridge device to the device itself.
+	*/
+	mapping[0] = 1;
+	mapping[1] = chain_len;
+	for (i = 0; i < chain_len; i++)
+		mapping[i + 4] = buf[chain_len - i - 1];
+
+	/* Open main hwinfo block */
+	if (hwilib_find_blocks("hwinfo.hex") != CB_SUCCESS)
+		return CB_ERR;
+	/* Now try to find a valid MAC address in hwinfo for this mapping. */
+	for (i = 0; i < MAX_NUM_MAPPINGS; i++) {
+		if (hwilib_get_field(XMac1Mapping + i, buf, 16) != 16)
+			continue;
+		if (memcmp(buf, mapping, chain_len + 4))
+			continue;
+		/* There is a matching mapping available, get MAC address. */
+		if (hwilib_get_field(XMac1 + i, mac, MAC_ADDR_LEN) == MAC_ADDR_LEN) {
+			if (is_mac_adr_valid(mac))
+				return CB_SUCCESS;
+		}
+		return CB_ERR;
+	}
+	/* No MAC address found for */
+	return CB_ERR;
+}
 
 static void mainboard_init(void *chip_info)
 {
diff --git a/src/mainboard/siemens/mc_rpl/variants/mc_rpl1/Kconfig b/src/mainboard/siemens/mc_rpl/variants/mc_rpl1/Kconfig
index f57e2cbf0d..a56d4c5b7a 100644
--- a/src/mainboard/siemens/mc_rpl/variants/mc_rpl1/Kconfig
+++ b/src/mainboard/siemens/mc_rpl/variants/mc_rpl1/Kconfig
@@ -9,6 +9,7 @@ config BOARD_SPECIFIC_OPTIONS
 	select MEMORY_MAPPED_TPM
 	select TPM_MEASURED_BOOT
 	select TPM_MEASURED_BOOT_INIT_BOOTBLOCK
+	select DRIVER_INTEL_I210
 
 config UART_FOR_CONSOLE
 	int

From b67d88aecbd3396ef35c952a1c5af0734f7663aa Mon Sep 17 00:00:00 2001
From: Kapil Porwal <kapilporwal@google.com>
Date: Mon, 25 Aug 2025 09:44:44 +0530
Subject: [PATCH 1855/3886] mb/google/bluey: Enable PMIC based slow charging in
 romstage

Enable PMIC based slow charging in romstage until we have fast charging
solution enabled.

BUG=b:438004604
TEST=Verify battery charging during romstage.

Change-Id: Idb8ea7151a2a467194aee2b357d8a5f24e691717
Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88928
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/google/bluey/romstage.c | 25 +++++++++++++++++++++++++
 1 file changed, 25 insertions(+)

diff --git a/src/mainboard/google/bluey/romstage.c b/src/mainboard/google/bluey/romstage.c
index b76dfba1f2..67d19aa1e6 100644
--- a/src/mainboard/google/bluey/romstage.c
+++ b/src/mainboard/google/bluey/romstage.c
@@ -5,9 +5,32 @@
 #include <gpio.h>
 #include <soc/aop_common.h>
 #include <soc/qclib_common.h>
+#include <soc/qcom_spmi.h>
 #include <soc/shrm.h>
 #include <soc/watchdog.h>
 
+#define SMB1_SLAVE_ID 0x07
+#define SMB2_SLAVE_ID 0x0A
+#define SCHG_CHGR_MAX_FAST_CHARGE_CURRENT_CFG 0x2666
+#define SMB1_CHGR_MAX_FCC_CFG ((SMB1_SLAVE_ID << 16) | SCHG_CHGR_MAX_FAST_CHARGE_CURRENT_CFG)
+#define SMB2_CHGR_MAX_FCC_CFG ((SMB2_SLAVE_ID << 16) | SCHG_CHGR_MAX_FAST_CHARGE_CURRENT_CFG)
+#define SCHG_CHGR_CHARGING_ENABLE_CMD 0x2642
+#define SMB1_CHGR_CHRG_EN_CMD ((SMB1_SLAVE_ID << 16) | SCHG_CHGR_CHARGING_ENABLE_CMD)
+#define SMB2_CHGR_CHRG_EN_CMD ((SMB2_SLAVE_ID << 16) | SCHG_CHGR_CHARGING_ENABLE_CMD)
+
+#define FCC_1A_STEP_50MA 0x14
+#define CHRG_ENABLE 0x01
+
+static void enable_battery_charging(void)
+{
+	/* Configure FCC and enable charging */
+	printk(BIOS_INFO, "Use slow charging without fast charge support\n");
+	spmi_write8(SMB1_CHGR_MAX_FCC_CFG, FCC_1A_STEP_50MA);
+	spmi_write8(SMB2_CHGR_MAX_FCC_CFG, FCC_1A_STEP_50MA);
+	spmi_write8(SMB1_CHGR_CHRG_EN_CMD, CHRG_ENABLE);
+	spmi_write8(SMB2_CHGR_CHRG_EN_CMD, CHRG_ENABLE);
+}
+
 void platform_romstage_main(void)
 {
 	/* Watchdog must be checked first to avoid erasing watchdog info later. */
@@ -22,6 +45,8 @@ void platform_romstage_main(void)
 
 	qclib_rerun();
 
+	enable_battery_charging();
+
 	/*
 	 * Enable this power rail now for FPMCU stability prior to
 	 * its reset being deasserted in ramstage. This applies

From 691d5e84cd802c9fe0255a34502274da94a4a6d0 Mon Sep 17 00:00:00 2001
From: Avi Uday <aviuday@google.com>
Date: Mon, 25 Aug 2025 18:01:59 +0530
Subject: [PATCH 1856/3886] mainboard/google/oceot: Drop redundant
 logo_valignment selection

This commit removes the explicit `logo_valignment` setting from the
`common_soc_config` for Ocelot.

The default vertical alignment for the splash screen logo is
`FW_SPLASH_VALIGNMENT_CENTER`, which is the desired behavior for ocelot.

Change-Id: I967c6f0b6926d23a399d01197dbed9e40b979aff
Signed-off-by: Avi Uday <aviuday@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88935
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Pranava Y N <pranavayn@google.com>
---
 src/mainboard/google/ocelot/variants/ocelot/overridetree.cb | 1 -
 1 file changed, 1 deletion(-)

diff --git a/src/mainboard/google/ocelot/variants/ocelot/overridetree.cb b/src/mainboard/google/ocelot/variants/ocelot/overridetree.cb
index 33bf88704e..149d0859e2 100644
--- a/src/mainboard/google/ocelot/variants/ocelot/overridetree.cb
+++ b/src/mainboard/google/ocelot/variants/ocelot/overridetree.cb
@@ -111,7 +111,6 @@ chip soc/intel/pantherlake
 	#| I2C5              | Touchpad                  |
 	#+-------------------+---------------------------+
 	register "common_soc_config" = "{
-		.logo_valignment = FW_SPLASH_VALIGNMENT_MIDDLE,
 		.chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT,
 		.i2c[1] = {
 			.speed = I2C_SPEED_FAST,

From 73961bf6800c06aaa6860d5e91a26e9bc2e0a661 Mon Sep 17 00:00:00 2001
From: Avi Uday <aviuday@google.com>
Date: Mon, 25 Aug 2025 19:01:33 +0530
Subject: [PATCH 1857/3886] mb/google/ocelot: Use same mainboard part number
 for all ocelot variants

This patch unifies all the ocelot variants based on
`BOARD_GOOGLE_MODEL_OCELOT` to use the same mainboard part number
`Ocelot` for code cleanliness.

TEST=Verify that ocelot builds without any error
Change-Id: I461a8142b93b10200b28bfe8855363ce2a30051d
Signed-off-by: Avi Uday <aviuday@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88939
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/google/ocelot/Kconfig | 7 +------
 1 file changed, 1 insertion(+), 6 deletions(-)

diff --git a/src/mainboard/google/ocelot/Kconfig b/src/mainboard/google/ocelot/Kconfig
index 8a61867757..bfcb9af577 100644
--- a/src/mainboard/google/ocelot/Kconfig
+++ b/src/mainboard/google/ocelot/Kconfig
@@ -130,12 +130,7 @@ config MAINBOARD_FAMILY
 	default "Google_Ocelot"
 
 config MAINBOARD_PART_NUMBER
-	default "Ocelot" if BOARD_GOOGLE_OCELOT
-	default "Ocelot4ES" if BOARD_GOOGLE_OCELOT4ES
-	default "Ocelotite4ES" if BOARD_GOOGLE_OCELOTITE4ES
-	default "Ocelotmchp4ES" if BOARD_GOOGLE_OCELOTMCHP4ES
-	default "Ocelotite" if BOARD_GOOGLE_OCELOTITE
-	default "Ocelotmchp" if BOARD_GOOGLE_OCELOTMCHP
+	default "Ocelot" if BOARD_GOOGLE_MODEL_OCELOT
 
 config MEMORY_SOLDERDOWN
 	def_bool n

From c732f406c7ab5855ae2a44d1920f2a22f2de8bf9 Mon Sep 17 00:00:00 2001
From: Avi Uday <aviuday@google.com>
Date: Mon, 25 Aug 2025 19:14:52 +0530
Subject: [PATCH 1858/3886] mb/google/ocelot: ec.h: Disable sync IRQ, sync IRQ
 wake capable for OCELOT4ES

This commit introduces changes to support the OCELOT4ES variant by
adding a conditional check in the EC header file for enabling this
new variant.

TEST=Verify that ocelot builds without any error
Change-Id: Id7b27ce405df8e67675834a069133c87af71fd37
Signed-off-by: Avi Uday <aviuday@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88940
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Pranava Y N <pranavayn@google.com>
---
 .../ocelot/variants/baseboard/ocelot/include/baseboard/ec.h     | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/mainboard/google/ocelot/variants/baseboard/ocelot/include/baseboard/ec.h b/src/mainboard/google/ocelot/variants/baseboard/ocelot/include/baseboard/ec.h
index 5804b303d0..1302946b93 100644
--- a/src/mainboard/google/ocelot/variants/baseboard/ocelot/include/baseboard/ec.h
+++ b/src/mainboard/google/ocelot/variants/baseboard/ocelot/include/baseboard/ec.h
@@ -75,7 +75,7 @@
 /* Enable EC backed PD MCU device in ACPI */
 #define EC_ENABLE_PD_MCU_DEVICE
 
-#if !CONFIG(BOARD_GOOGLE_OCELOT)
+#if !CONFIG(BOARD_GOOGLE_OCELOT) && !CONFIG(BOARD_GOOGLE_OCELOT4ES)
  #define EC_ENABLE_SYNC_IRQ      /* Enable tight timestamp / wake support */
  #define EC_SYNC_IRQ_WAKE_CAPABLE /* Let the OS know ec_sync is wake capable */
 #endif

From 42ba7a9e48420298e95d0b65c7b5255e2097b318 Mon Sep 17 00:00:00 2001
From: Shuo Liu <shuo.liu@intel.com>
Date: Sat, 23 Aug 2025 04:56:50 +0800
Subject: [PATCH 1859/3886] soc/intel/xeon_sp/gnr: Add Kconfig symbols for SKUs
 GNR-AP and GNR-SP

Granite Rapids SoC has 2 SKUs, a.k.a. GNR-AP and GNR-SP, which
use different FSP headers/binaries. Add Kconfig items to support
these SKU types.

Change-Id: Ie3a2d603f0a2c303e8f3c0911598742fbc25d73a
Signed-off-by: Shuo Liu <shuo.liu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88897
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Wilson-MiTACComputing <wilson.chien@mitaccomputing.com>
Reviewed-by: Mark Chang <mark.chang@mitaccomputing.com>
Reviewed-by: Schumi Chu
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/intel/avenuecity_crb/Kconfig    |  2 +-
 src/mainboard/intel/beechnutcity_crb/Kconfig  |  2 +-
 src/mainboard/mitaccomputing/r520g6sb/Kconfig |  2 +-
 src/mainboard/mitaccomputing/sc513g6/Kconfig  |  2 +-
 src/soc/intel/xeon_sp/gnr/Kconfig             | 12 ++++++++++++
 5 files changed, 16 insertions(+), 4 deletions(-)

diff --git a/src/mainboard/intel/avenuecity_crb/Kconfig b/src/mainboard/intel/avenuecity_crb/Kconfig
index fff244e92e..a8ac41af99 100644
--- a/src/mainboard/intel/avenuecity_crb/Kconfig
+++ b/src/mainboard/intel/avenuecity_crb/Kconfig
@@ -5,7 +5,7 @@ if BOARD_INTEL_AVENUECITY_CRB
 config BOARD_SPECIFIC_OPTIONS
 	def_bool y
 	select BOARD_ROMSIZE_KB_65536
-	select SOC_INTEL_GRANITERAPIDS
+	select SOC_INTEL_GRANITERAPIDS_AP
 	select SUPERIO_ASPEED_AST2400
 	select HAVE_ACPI_TABLES
 	select IPMI_KCS
diff --git a/src/mainboard/intel/beechnutcity_crb/Kconfig b/src/mainboard/intel/beechnutcity_crb/Kconfig
index 3c2f02a9ea..9530e3bd99 100644
--- a/src/mainboard/intel/beechnutcity_crb/Kconfig
+++ b/src/mainboard/intel/beechnutcity_crb/Kconfig
@@ -5,7 +5,7 @@ if BOARD_INTEL_BEECHNUTCITY_CRB
 config BOARD_SPECIFIC_OPTIONS
 	def_bool y
 	select BOARD_ROMSIZE_KB_65536
-	select SOC_INTEL_GRANITERAPIDS
+	select SOC_INTEL_GRANITERAPIDS_SP
 	select SUPERIO_ASPEED_AST2400
 	select HAVE_ACPI_TABLES
 	select IPMI_KCS
diff --git a/src/mainboard/mitaccomputing/r520g6sb/Kconfig b/src/mainboard/mitaccomputing/r520g6sb/Kconfig
index c88c310c61..65dfee575b 100644
--- a/src/mainboard/mitaccomputing/r520g6sb/Kconfig
+++ b/src/mainboard/mitaccomputing/r520g6sb/Kconfig
@@ -5,7 +5,7 @@ if BOARD_MITAC_COMPUTING_R520G6SB
 config BOARD_SPECIFIC_OPTIONS
 	def_bool y
 	select BOARD_ROMSIZE_KB_65536
-	select SOC_INTEL_GRANITERAPIDS
+	select SOC_INTEL_GRANITERAPIDS_SP
 	select SUPERIO_ASPEED_AST2400
 	select CONSOLE_OVERRIDE_LOGLEVEL
 	select HAVE_ACPI_TABLES
diff --git a/src/mainboard/mitaccomputing/sc513g6/Kconfig b/src/mainboard/mitaccomputing/sc513g6/Kconfig
index a201c8b6bc..8f8079e238 100644
--- a/src/mainboard/mitaccomputing/sc513g6/Kconfig
+++ b/src/mainboard/mitaccomputing/sc513g6/Kconfig
@@ -5,7 +5,7 @@ if BOARD_MITAC_COMPUTING_SC513G6
 config BOARD_SPECIFIC_OPTIONS
 	def_bool y
 	select BOARD_ROMSIZE_KB_65536
-	select SOC_INTEL_GRANITERAPIDS
+	select SOC_INTEL_GRANITERAPIDS_SP
 	select SUPERIO_ASPEED_AST2400
 	select CONSOLE_OVERRIDE_LOGLEVEL
 	select HAVE_ACPI_TABLES
diff --git a/src/soc/intel/xeon_sp/gnr/Kconfig b/src/soc/intel/xeon_sp/gnr/Kconfig
index e55f458164..3d855b20ff 100644
--- a/src/soc/intel/xeon_sp/gnr/Kconfig
+++ b/src/soc/intel/xeon_sp/gnr/Kconfig
@@ -18,6 +18,18 @@ config SOC_INTEL_GRANITERAPIDS
 	help
 	  Intel Granite Rapids support
 
+config SOC_INTEL_GRANITERAPIDS_AP
+	bool
+	select SOC_INTEL_GRANITERAPIDS
+	help
+	  Intel Granite Rapids AP support
+
+config SOC_INTEL_GRANITERAPIDS_SP
+	bool
+	select SOC_INTEL_GRANITERAPIDS
+	help
+	  Intel Granite Rapids SP support
+
 if SOC_INTEL_GRANITERAPIDS
 
 config CHIPSET_DEVICETREE

From 179b8444c31fc08965abefaabde530206f8fd6f7 Mon Sep 17 00:00:00 2001
From: Jincheng Li <jincheng.li@intel.com>
Date: Sat, 23 Aug 2025 00:05:00 +0800
Subject: [PATCH 1860/3886] soc/intel/xeon-sp/gnr: Hook up public FSP bin and
 headers
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

GNR-AP public FSP
- https://github.com/intel/FSP/tree/master/BirchStreamFspBinPkg/ap

GNR-SP public FSP
- https://github.com/intel/FSP/tree/master/BirchStreamFspBinPkg/sp

GNR mainboards will by default use public FSP bin and headers.
If needing to use site-local FSP bin and headers, apply below
settings in the defconfig (use beechnutcity CRB as example),

CONFIG_FSP_USE_REPO=n
CONFIG_ADD_FSP_BINARIES=y
CONFIG_FSP_T_FILE="site-local/beechnutcity/Server_T.fd"
CONFIG_FSP_M_FILE="site-local/beechnutcity/Server_M.fd"
CONFIG_FSP_S_FILE="site-local/beechnutcity/Server_S.fd"
CONFIG_FSP_HEADER_PATH="src/vendorcode/intel/fsp/fsp2_0/
graniterapids/sp/"

TEST=Build and boot on intel/avenuecity CRB
TEST=Build and boot on intel/beechnutcity CRB

Change-Id: I88701316e21ec4737539294d17926aa0abe8c1fd
Signed-off-by: Jincheng Li <jincheng.li@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88898
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Reviewed-by: Hancockc <hancock.chang@mitaccomputing.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Schumi Chu
Reviewed-by: Wilson-MiTACComputing <wilson.chien@mitaccomputing.com>
Reviewed-by: Mark Chang <mark.chang@mitaccomputing.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 configs/builder/config.intel.crb.avc |  6 ------
 configs/builder/config.intel.crb.bnc |  6 ------
 src/soc/intel/xeon_sp/gnr/Kconfig    | 13 +++++++++++--
 3 files changed, 11 insertions(+), 14 deletions(-)

diff --git a/configs/builder/config.intel.crb.avc b/configs/builder/config.intel.crb.avc
index 433f06dac7..c29d1066f1 100644
--- a/configs/builder/config.intel.crb.avc
+++ b/configs/builder/config.intel.crb.avc
@@ -15,7 +15,6 @@ CONFIG_NO_GFX_INIT=y
 CONFIG_HAVE_IFD_BIN=y
 CONFIG_HAVE_PBP_BIN=y
 CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION=y
-CONFIG_ADD_FSP_BINARIES=y
 CONFIG_PAYLOAD_LINUX=y
 
 CONFIG_UART_FOR_CONSOLE=0
@@ -26,11 +25,6 @@ CONFIG_CONSOLE_SERIAL_115200=y
 #
 CONFIG_IFD_BIN_PATH="site-local/avenuecity/descriptor.bin"
 CONFIG_PBP_BIN_PATH="site-local/avenuecity/pbp.bin"
-CONFIG_FSP_T_FILE="site-local/avenuecity/Server_T.fd"
-CONFIG_FSP_M_FILE="site-local/avenuecity/Server_M.fd"
-CONFIG_FSP_S_FILE="site-local/avenuecity/Server_S.fd"
-CONFIG_FSP_HEADER_PATH="src/vendorcode/intel/fsp/fsp2_0/graniterapids/ap/"
-
 CONFIG_PAYLOAD_FILE="site-local/avenuecity/linuxboot_bzImage"
 CONFIG_LINUX_COMMAND_LINE="loglevel=7 earlyprintk=serial,ttyS0,115200 console=ttyS0,115200"
 
diff --git a/configs/builder/config.intel.crb.bnc b/configs/builder/config.intel.crb.bnc
index 80ec39133e..b41921902f 100644
--- a/configs/builder/config.intel.crb.bnc
+++ b/configs/builder/config.intel.crb.bnc
@@ -15,7 +15,6 @@ CONFIG_NO_GFX_INIT=y
 CONFIG_HAVE_IFD_BIN=y
 CONFIG_HAVE_PBP_BIN=y
 CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION=y
-CONFIG_ADD_FSP_BINARIES=y
 CONFIG_PAYLOAD_LINUX=y
 
 CONFIG_UART_FOR_CONSOLE=0
@@ -26,11 +25,6 @@ CONFIG_CONSOLE_SERIAL_115200=y
 #
 CONFIG_IFD_BIN_PATH="site-local/beechnutcity/descriptor.bin"
 CONFIG_PBP_BIN_PATH="site-local/beechnutcity/pbp.bin"
-CONFIG_FSP_T_FILE="site-local/beechnutcity/Server_T.fd"
-CONFIG_FSP_M_FILE="site-local/beechnutcity/Server_M.fd"
-CONFIG_FSP_S_FILE="site-local/beechnutcity/Server_S.fd"
-CONFIG_FSP_HEADER_PATH="src/vendorcode/intel/fsp/fsp2_0/graniterapids/sp/"
-
 CONFIG_PAYLOAD_FILE="site-local/beechnutcity/linuxboot_bzImage"
 CONFIG_LINUX_COMMAND_LINE="loglevel=7 earlyprintk=serial,ttyS0,115200 console=ttyS0,115200"
 
diff --git a/src/soc/intel/xeon_sp/gnr/Kconfig b/src/soc/intel/xeon_sp/gnr/Kconfig
index 3d855b20ff..2b59f2c5bb 100644
--- a/src/soc/intel/xeon_sp/gnr/Kconfig
+++ b/src/soc/intel/xeon_sp/gnr/Kconfig
@@ -15,6 +15,7 @@ config SOC_INTEL_GRANITERAPIDS
 	select HAVE_IOAT_DOMAINS
 	select FSP_SPEC_VIOLATION_XEON_SP_HEAP_WORKAROUND
 	select DRAM_SUPPORT_DDR5
+	select HAVE_INTEL_FSP_REPO
 	help
 	  Intel Granite Rapids support
 
@@ -36,9 +37,17 @@ config CHIPSET_DEVICETREE
 	string
 	default "soc/intel/xeon_sp/gnr/chipset.cb"
 
+if FSP_USE_REPO
+
 config FSP_HEADER_PATH
-	string "Location of FSP headers"
-	default "src/vendorcode/intel/fsp/fsp2_0/graniterapids/ap"
+	default "3rdparty/fsp/BirchStreamFspBinPkg/ap/Include" if SOC_INTEL_GRANITERAPIDS_AP
+	default "3rdparty/fsp/BirchStreamFspBinPkg/sp/Include" if SOC_INTEL_GRANITERAPIDS_SP
+
+config FSP_FD_PATH
+	default "3rdparty/fsp/BirchStreamFspBinPkg/ap/Fsp.fd" if SOC_INTEL_GRANITERAPIDS_AP
+	default "3rdparty/fsp/BirchStreamFspBinPkg/sp/Fsp.fd" if SOC_INTEL_GRANITERAPIDS_SP
+
+endif
 
 config MAX_CPUS
 	int

From 762a5355517a410e27a2b3810e7e113c05eb4c7a Mon Sep 17 00:00:00 2001
From: Alicja Michalska <alicja.michalska@9elements.com>
Date: Thu, 7 Aug 2025 23:43:46 +0200
Subject: [PATCH 1861/3886] mb/erying/tgl: Clean up the GPIO table

Looks nicer, fixes DisplayPort and edge-cases where PCIe devices weren't
detected at random.

Change-Id: Ie00f2258e95eb6a44e1f71f462c8ca33c4184870
Signed-off-by: Alicja Michalska <alicja.michalska@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88714
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
---
 src/mainboard/erying/tgl/gpio.h | 440 +++++++++++++++-----------------
 1 file changed, 209 insertions(+), 231 deletions(-)

diff --git a/src/mainboard/erying/tgl/gpio.h b/src/mainboard/erying/tgl/gpio.h
index 201b4b4535..d6a0a14121 100644
--- a/src/mainboard/erying/tgl/gpio.h
+++ b/src/mainboard/erying/tgl/gpio.h
@@ -3,93 +3,89 @@
 #include <soc/gpio.h>
 
 static const struct pad_config gpio_table[] = {
-
-	/* ------- GPIO Community 0 ------- */
-
 	/* ------- GPIO Group GPP_A ------- */
-	PAD_CFG_NF(GPP_A0, NATIVE, DEEP, NF1),	// ESPI_IO0
-	PAD_CFG_NF(GPP_A1, NATIVE, DEEP, NF1),	// ESPI_IO1
-	PAD_CFG_NF(GPP_A2, NATIVE, DEEP, NF1),	// ESPI_IO2
-	PAD_CFG_NF(GPP_A3, NATIVE, DEEP, NF1),	// ESPI_IO3
-	PAD_CFG_NF(GPP_A4, NATIVE, DEEP, NF1),	// ESPI_CS0#
-	PAD_CFG_NF(GPP_A5, NATIVE, DEEP, NF1),	// ESPI_CLK
-	PAD_CFG_NF(GPP_A6, NATIVE, DEEP, NF1),	// ESPI_RESET#
-	PAD_CFG_NF(GPP_A7, NATIVE, DEEP, NF1),	// ESPI_CS1#
-	PAD_CFG_NF(GPP_A8, UP_20K, DEEP, NF1),	// ESPI_CS2#
-	PAD_CFG_NF(GPP_A9, UP_20K, DEEP, NF1),	// ESPI_CS3#
-	PAD_CFG_NF(GPP_A10, UP_20K, DEEP, NF1),	// ESPI_ALERT0#
-	PAD_CFG_NF(GPP_A11, UP_20K, DEEP, NF1),	// ESPI_ALERT1#
-	PAD_CFG_NF(GPP_A12, UP_20K, DEEP, NF1),	// ESPI_ALERT2#
-	PAD_CFG_NF(GPP_A13, DN_20K, DEEP, NF1),	// ESPI_ALERT3#
-	_PAD_CFG_STRUCT(GPP_A14, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),	/* n/a */
-
-	/* ------- GPIO Group GPP_R ------- */
-	PAD_CFG_NF(GPP_R0, NONE, DEEP, NF1),	// HDA_BITCLK
-	PAD_CFG_NF(GPP_R1, NATIVE, DEEP, NF1),	// HDA_SYNC
-	PAD_CFG_NF(GPP_R2, NATIVE, DEEP, NF1),	// HDA_SDOUT
-	PAD_CFG_NF(GPP_R3, NATIVE, DEEP, NF1),	// HDA_SDIN0
-	PAD_CFG_NF(GPP_R4, NONE, DEEP, NF1),	// HDA_RST#
-	PAD_NC(GPP_R5, NONE),
-	_PAD_CFG_STRUCT(GPP_R6, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_BUF(TX_RX_DISABLE), 0),	/* n/a */
-	_PAD_CFG_STRUCT(GPP_R7, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_BUF(TX_RX_DISABLE), 0),	/* n/a */
-	_PAD_CFG_STRUCT(GPP_R8, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),	/* n/a */
-	PAD_CFG_NF(GPP_R9, NATIVE, DEEP, NF1),	// PCIE_LNK_DOWN
-	PAD_CFG_NF(GPP_R10, NATIVE, DEEP, NF1),	// ISH_UART0_RTS#
-	PAD_CFG_NF(GPP_R11, NATIVE, DEEP, NF1),	// SX_EXIT_HOLDOFF#
-	_PAD_CFG_STRUCT(GPP_R12, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),	/* CLKOUT_48 */
-	_PAD_CFG_STRUCT(GPP_R13, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),	/* ISH_GP7 */
-	PAD_NC(GPP_R14, NONE),
-	PAD_NC(GPP_R15, NONE),
-	PAD_NC(GPP_R16, NONE),
-	PAD_NC(GPP_R17, NONE),
-	PAD_CFG_GPO(GPP_R18, 1, PLTRST),	/* GPIO */
-	PAD_NC(GPP_R19, NONE),
+	PAD_CFG_NF(GPP_A0, NATIVE, DEEP, NF1),		// ESPI_IO0
+	PAD_CFG_NF(GPP_A1, NATIVE, DEEP, NF1),		// ESPI_IO1
+	PAD_CFG_NF(GPP_A2, NATIVE, DEEP, NF1),		// ESPI_IO2
+	PAD_CFG_NF(GPP_A3, NATIVE, DEEP, NF1),		// ESPI_IO3
+	PAD_CFG_NF(GPP_A4, NATIVE, DEEP, NF1),		// ESPI_CS0#
+	PAD_CFG_NF(GPP_A5, NATIVE, DEEP, NF1),		// ESPI_CLK
+	PAD_CFG_NF(GPP_A6, NATIVE, DEEP, NF1),		// ESPI_RESET#
+	PAD_CFG_NF(GPP_A7, NATIVE, DEEP, NF1),		// ESPI_CS1#
+	PAD_CFG_NF(GPP_A8, UP_20K, DEEP, NF1),		// ESPI_CS2#
+	PAD_CFG_NF(GPP_A9, UP_20K, DEEP, NF1),		// ESPI_CS3#
+	PAD_CFG_NF(GPP_A10, UP_20K, DEEP, NF1),		// ESPI_ALERT0#
+	PAD_CFG_NF(GPP_A11, UP_20K, DEEP, NF1),		// ESPI_ALERT1#
+	PAD_CFG_NF(GPP_A12, UP_20K, DEEP, NF1),		// ESPI_ALERT2#
+	PAD_CFG_NF(GPP_A13, DN_20K, DEEP, NF1),		// ESPI_ALERT3#
+	PAD_CFG_NF(GPP_A14, NATIVE, DEEP, NF1),		// Unknown
 
 	/* ------- GPIO Group GPP_B ------- */
-	PAD_CFG_GPO(GPP_B0, 1, PLTRST),	/* GPIO */
+	PAD_CFG_GPO(GPP_B0, 1, PLTRST),			// GPO, some kind of VR?
 	PAD_NC(GPP_B1, NONE),
 	PAD_NC(GPP_B2, NONE),
 	PAD_NC(GPP_B3, NONE),
 	PAD_NC(GPP_B4, NONE),
-	PAD_NC(GPP_B5, NONE),
-	PAD_NC(GPP_B6, NONE),
-	PAD_NC(GPP_B7, NONE),
-	PAD_CFG_NF(GPP_B8, NONE, DEEP, NF1),	// SRCCLKREQ3
-	PAD_NC(GPP_B9, NONE),
-	PAD_NC(GPP_B10, NONE),
-	PAD_CFG_GPO(GPP_B11, 1, DEEP),	/* GPIO */
-	PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1),	// SLP_S0#
-	PAD_NC(GPP_B13, NONE),
-	PAD_NC(GPP_B14, NONE),
+
+	// We don't know the mapping of SRCCLKREQs because vendor refused to share schematics. Leave their configuration to the FSP.
+
+	PAD_CFG_GPO(GPP_B11, 1, DEEP),			// GPO, some kind of VR?
+	PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1),		// SLP_S0#
+	PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1),		// PLT_RST#
+	PAD_CFG_NF(GPP_B14, NONE, DEEP, NF1),		// SPK_BEEP
 	PAD_NC(GPP_B15, NONE),
 	PAD_NC(GPP_B16, NONE),
 	PAD_NC(GPP_B17, NONE),
 	PAD_NC(GPP_B18, NONE),
 	PAD_NC(GPP_B19, NONE),
-	_PAD_CFG_STRUCT(GPP_B20, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),	/* GSPI1_CLK */
-	_PAD_CFG_STRUCT(GPP_B21, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),	/* GSPI1_MISO */
-	_PAD_CFG_STRUCT(GPP_B22, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), 0),	/* GSPI1_MOSI */
-	PAD_CFG_GPO(GPP_B23, 1, PLTRST),	/* GPIO */
+	PAD_NC(GPP_B20, NONE),
+	PAD_NC(GPP_B21, NONE),
+	PAD_NC(GPP_B22, NONE),
+	PAD_CFG_GPO(GPP_B23, 1, PLTRST),		/* GPIO */
 
-	/* ------- GPIO Community 1 ------- */
+	/* ------- GPIO Group GPP_C ------- */
+	PAD_CFG_NF(GPP_C0, NONE, PLTRST, NF1),		// SMBCLK
+	PAD_CFG_NF(GPP_C1, NONE, PLTRST, NF1),		// SMBDATA
+	PAD_CFG_NF(GPP_C2, NONE, PLTRST, NF1),		// SMBALERT#
+	PAD_CFG_NF(GPP_C3, NONE, DEEP, NF3),		// I2C2_SDA
+	PAD_CFG_NF(GPP_C4, NONE, DEEP, NF3),		// I2C2_SCL
+	PAD_CFG_NF(GPP_C5, NONE, DEEP, NF1),		// SML0ALERT#
+	PAD_CFG_NF(GPP_C3, NONE, DEEP, NF2),		// I2C3_SDA
+	PAD_CFG_NF(GPP_C4, NONE, DEEP, NF2),		// I2C3_SCL
+	PAD_NC(GPP_C8, NONE),
+	PAD_NC(GPP_C9, NONE),
+	PAD_NC(GPP_C10, NONE),
+	PAD_NC(GPP_C11, NONE),
+	PAD_CFG_GPO(GPP_C12, 1, PLTRST),		/* GPIO */
+	PAD_CFG_GPO(GPP_C13, 1, PLTRST),		/* GPIO */
+	PAD_CFG_GPO(GPP_C14, 1, PLTRST),		/* GPIO */
+	PAD_CFG_GPO(GPP_C15, 1, PLTRST),		/* GPIO */
+	PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1),		// I2C0_SDA
+	PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1),		// I2C0_SCL
+	PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1),		// I2C1_SDA
+	PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1),		// I2C1_SCL
+	PAD_NC(GPP_C20, NONE),
+	PAD_NC(GPP_C21, NONE),
+	PAD_NC(GPP_C22, NONE),
+	PAD_NC(GPP_C23, NONE),
 
 	/* ------- GPIO Group GPP_D ------- */
 	PAD_NC(GPP_D0, NONE),
 	PAD_NC(GPP_D1, NONE),
 	PAD_NC(GPP_D2, NONE),
 	PAD_NC(GPP_D3, NONE),
-	_PAD_CFG_STRUCT(GPP_D4, PAD_FUNC(NF1) | PAD_RESET(RSMRST) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0),	/* SML1CLK */
-	_PAD_CFG_STRUCT(GPP_D5, PAD_FUNC(NF2) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),	/* CNV_RF_RESET# */
-	_PAD_CFG_STRUCT(GPP_D6, PAD_FUNC(NF2) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),	/* MODEM_CLKREQ */
+	PAD_CFG_NF(GPP_D4, NONE, RSMRST, NF1),		// SML1CLK
+	PAD_CFG_NF(GPP_D5, NONE, DEEP, NF2),		// CNV_RF_RESET#
+	PAD_CFG_NF(GPP_D6, NONE, DEEP, NF2),		// MODEM_CLKREQ
 	PAD_NC(GPP_D7, NONE),
 	PAD_NC(GPP_D8, NONE),
-	_PAD_CFG_STRUCT(GPP_D9, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0),	/* SML0CLK */
-	_PAD_CFG_STRUCT(GPP_D10, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0),	/* SML0DATA */
-	PAD_CFG_GPO(GPP_D11, 1, PLTRST),	/* GPIO */
-	PAD_CFG_GPO(GPP_D12, 1, PLTRST),	/* GPIO */
+	PAD_CFG_NF(GPP_D9, NONE, DEEP, NF1),		// SML0CLK
+	PAD_CFG_NF(GPP_D10, NONE, DEEP, NF1),		// SML0DATA
+	PAD_CFG_GPO(GPP_D11, 1, PLTRST),		/* GPIO */
+	PAD_CFG_GPO(GPP_D12, 1, PLTRST),		/* GPIO */
 	PAD_NC(GPP_D13, NONE),
 	PAD_NC(GPP_D14, NONE),
-	_PAD_CFG_STRUCT(GPP_D15, PAD_FUNC(NF1) | PAD_RESET(RSMRST) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0),	/* SML1DATA */
+	PAD_CFG_NF(GPP_D15, NONE, RSMRST, NF1),		// SML1DATA
 	PAD_NC(GPP_D16, NONE),
 	PAD_NC(GPP_D17, NONE),
 	PAD_NC(GPP_D18, NONE),
@@ -99,41 +95,46 @@ static const struct pad_config gpio_table[] = {
 	PAD_NC(GPP_D22, NONE),
 	PAD_NC(GPP_D23, NONE),
 
-	/* ------- GPIO Group GPP_C ------- */
-	_PAD_CFG_STRUCT(GPP_C0, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0),	/* SMBCLK */
-	_PAD_CFG_STRUCT(GPP_C1, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0),	/* SMBDATA */
-	PAD_CFG_GPO(GPP_C2, 1, PLTRST),	/* GPIO */
-	_PAD_CFG_STRUCT(GPP_C3, PAD_FUNC(NF3) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0),	/* I2C2_SDA */
-	_PAD_CFG_STRUCT(GPP_C4, PAD_FUNC(NF3) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0),	/* I2C2_SCL */
-	PAD_CFG_GPO(GPP_C5, 0, DEEP),	/* GPIO */
-	_PAD_CFG_STRUCT(GPP_C6, PAD_FUNC(NF2) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),	/* I2C3_SDA */
-	_PAD_CFG_STRUCT(GPP_C7, PAD_FUNC(NF2) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),	/* I2C3_SCL */
-	PAD_NC(GPP_C8, NONE),
-	PAD_NC(GPP_C9, NONE),
-	PAD_NC(GPP_C10, NONE),
-	PAD_NC(GPP_C11, NONE),
-	PAD_CFG_GPO(GPP_C12, 1, PLTRST),	/* GPIO */
-	PAD_CFG_GPO(GPP_C13, 1, PLTRST),	/* GPIO */
-	PAD_CFG_GPO(GPP_C14, 1, PLTRST),	/* GPIO */
-	PAD_CFG_GPO(GPP_C15, 1, PLTRST),	/* GPIO */
-	_PAD_CFG_STRUCT(GPP_C16, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),	/* I2C0_SDA */
-	_PAD_CFG_STRUCT(GPP_C17, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),	/* I2C0_SCL */
-	_PAD_CFG_STRUCT(GPP_C18, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),	/* I2C1_SDA */
-	_PAD_CFG_STRUCT(GPP_C19, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),	/* I2C1_SCL */
-	PAD_NC(GPP_C20, NONE),
-	PAD_NC(GPP_C21, NONE),
-	PAD_NC(GPP_C22, NONE),
-	PAD_NC(GPP_C23, NONE),
+	/* ------- GPIO Group GPP_E ------- */
+	PAD_CFG_NF(GPP_E0, NONE, PLTRST, NF1),		// SATAXPCIE0
+	PAD_CFG_NF(GPP_E1, NONE, PLTRST, NF1),		// SATAXPCIE1
+	PAD_CFG_GPO(GPP_E2, 1, PLTRST),			/* GPIO */
+	PAD_CFG_GPO(GPP_E3, 1, PLTRST),			/* GPIO */
+	PAD_CFG_NF(GPP_E4, NONE, PWROK, NF1),		// SATA_DEVSLP0
+	PAD_CFG_NF(GPP_E5, NONE, PWROK, NF1),		// SATA_DEVSLP1
+	PAD_CFG_GPO(GPP_E6, 1, PLTRST),			/* GPIO */
+	PAD_NC(GPP_E7, NONE),
+	PAD_CFG_NF(GPP_E8, NONE, DEEP, NF1),		// SATALED#
+	PAD_CFG_NF(GPP_E9, NONE, PLTRST, NF1),		// USB_OC0#
+	PAD_CFG_NF(GPP_E10, NONE, PLTRST, NF1),		// USB_OC1#
+	PAD_CFG_NF(GPP_E11, NONE, PLTRST, NF1),		// USB_OC2#
+	PAD_CFG_NF(GPP_E12, NONE, PLTRST, NF1),		// USB_OC3#
 
-	/* ------- GPIO Group GPP_S ------- */
-	_PAD_CFG_STRUCT(GPP_S0, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),	/* SNDW1_CLK */
-	_PAD_CFG_STRUCT(GPP_S1, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),	/* SNDW1_DATA */
-	_PAD_CFG_STRUCT(GPP_S2, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),	/* SNDW2_CLK */
-	_PAD_CFG_STRUCT(GPP_S3, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),	/* SNDW2_DATA */
-	_PAD_CFG_STRUCT(GPP_S4, PAD_FUNC(NF2) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),	/* DMIC_CLKA1 */
-	_PAD_CFG_STRUCT(GPP_S5, PAD_FUNC(NF2) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),	/* DMIC_DATA1 */
-	_PAD_CFG_STRUCT(GPP_S6, PAD_FUNC(NF2) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),	/* DMIC_CLKA0 */
-	_PAD_CFG_STRUCT(GPP_S7, PAD_FUNC(NF2) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),	/* DMIC_DATA0 */
+	/* ------- GPIO Group GPP_F ------- */
+	PAD_CFG_NF(GPP_F0, NONE, PLTRST, NF1),		// SATAXPCIE3
+	PAD_CFG_NF(GPP_F1, NONE, PLTRST, NF1),		// SATAXPCIE4
+	PAD_CFG_NF(GPP_F2, NONE, PLTRST, NF1),		// SATAXPCIE5
+	PAD_CFG_GPO(GPP_F3, 0, PLTRST),			/* GPIO */
+	PAD_CFG_GPO(GPP_F4, 1, PLTRST),			/* GPIO */
+	PAD_CFG_GPO(GPP_F5, 1, PLTRST),			/* GPIO */
+	PAD_NC(GPP_F6, NONE),
+	PAD_CFG_GPO(GPP_F7, 1, PLTRST),			/* GPIO */
+	PAD_NC(GPP_F8, NONE),
+	PAD_CFG_GPO(GPP_F9, 1, PLTRST),			/* GPIO */
+	PAD_NC(GPP_F10, NONE),
+	PAD_CFG_GPO(GPP_F11, 1, PLTRST),		/* GPIO */
+	PAD_CFG_GPO(GPP_F12, 1, DEEP),			/* GPIO */
+	PAD_CFG_GPO(GPP_F13, 1, PLTRST),		/* GPIO */
+	PAD_CFG_NF(GPP_F14, NONE, PLTRST, NF1),		// PS_ON#
+	PAD_CFG_GPI_TRIG_OWN(GPP_F15, NONE, DEEP, OFF, ACPI),	/* GPIO */
+	PAD_CFG_GPO(GPP_F16, 1, PLTRST),		/* GPIO */
+	PAD_NC(GPP_F17, NONE),
+	PAD_CFG_GPO(GPP_F18, 1, PLTRST),		/* GPIO */
+	PAD_NC(GPP_F19, NONE),
+	PAD_NC(GPP_F20, NONE),
+	PAD_NC(GPP_F21, NONE),
+	PAD_NC(GPP_F22, NONE),
+	PAD_CFG_GPO(GPP_F23, 1, PLTRST),		/* GPIO */
 
 	/* ------- GPIO Group GPP_G ------- */
 	PAD_NC(GPP_G0, NONE),
@@ -141,148 +142,125 @@ static const struct pad_config gpio_table[] = {
 	PAD_CFG_GPO(GPP_G2, 0, PLTRST),	/* GPIO */
 	PAD_CFG_GPO(GPP_G3, 1, PLTRST),	/* GPIO */
 	PAD_CFG_GPO(GPP_G4, 1, PLTRST),	/* GPIO */
-	_PAD_CFG_STRUCT(GPP_G5, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),	/* SLP_DRAM# */
+	PAD_CFG_NF(GPP_G5, NONE, PLTRST, NF1),		// SLP_DRAM#
 	PAD_CFG_GPO(GPP_G6, 1, PLTRST),	/* GPIO */
 	PAD_CFG_GPO(GPP_G7, 1, PLTRST),	/* GPIO */
-	_PAD_CFG_STRUCT(GPP_G8, PAD_FUNC(NF2) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(NATIVE)),	/* DDP3_CTRLCLK */
-	_PAD_CFG_STRUCT(GPP_G9, PAD_FUNC(NF2) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(NATIVE)),	/* DDP3_CTRLDATA */
-	_PAD_CFG_STRUCT(GPP_G10, PAD_FUNC(NF2) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(NATIVE)),	/* DDP4_CTRLCLK */
-	_PAD_CFG_STRUCT(GPP_G11, PAD_FUNC(NF2) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(NATIVE)),	/* DDP4_CTRLDATA */
-	_PAD_CFG_STRUCT(GPP_G12, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(NATIVE)),	/* DDP1_CTRLCLK */
-	_PAD_CFG_STRUCT(GPP_G13, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(NATIVE)),	/* DDP1_CTRLDATA */
-	_PAD_CFG_STRUCT(GPP_G14, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(NATIVE)),	/* DDP2_CTRLCLK */
-	_PAD_CFG_STRUCT(GPP_G15, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(NATIVE)),	/* DDP2_CTRLDATA */
-
-	/* ------- GPIO Community 2 ------- */
-
-	/* ------- GPIO Group GPD ------- */
-	PAD_CFG_NF(GPD0, UP_20K, PWROK, NF1),	/* BATLOW# */
-	PAD_CFG_NF(GPD1, NATIVE, PWROK, NF1),	/* ACPRESENT */
-	PAD_CFG_NF(GPD2, NATIVE, PWROK, NF1),	/* LAN_WAKE# */
-	PAD_CFG_NF(GPD3, UP_20K, PWROK, NF1),	/* PWRBTN# */
-	PAD_CFG_NF(GPD4, NONE, PWROK, NF1),	/* SLP_S3# */
-	PAD_CFG_NF(GPD5, NONE, PWROK, NF1),	/* SLP_S4# */
-	PAD_CFG_NF(GPD6, NONE, PWROK, NF1),	/* SLP_A# */
-	PAD_CFG_GPO(GPD7, 0, PWROK),		/* GPIO */
-	PAD_CFG_NF(GPD8, NONE, PWROK, NF1),	/* SUSCLK */
-	PAD_CFG_NF(GPD9, NONE, PWROK, NF1),	/* SLP_WLAN# */
-	PAD_CFG_NF(GPD10, NONE, PWROK, NF1),	/* SLP_S5# */
-	PAD_CFG_NF(GPD11, NONE, PWROK, NF1),	/* LANPHYPC */
-	PAD_NC(GPD12, NONE),			/* GPIO */
-
-	/* ------- GPIO Community 3 ------- */
-
-	/* ------- GPIO Group GPP_E ------- */
-	PAD_CFG_NF(GPP_E0, NONE, DEEP, NF1),	/* SATAXPCIE0 */
-	PAD_CFG_NF(GPP_E1, NONE, PLTRST, NF1),	/* SATAXPCIE1 */
-	PAD_CFG_GPO(GPP_E2, 1, PLTRST),		/* GPIO */
-	PAD_CFG_GPO(GPP_E3, 1, PLTRST),		/* GPIO */
-	PAD_CFG_GPO(GPP_E4, 1, PLTRST),		/* SATA_DEVSLP0 */
-	PAD_CFG_NF(GPP_E5, NONE, RSMRST, NF1),	/* SATA_DEVSLP1 */
-	PAD_CFG_GPO(GPP_E6, 1, PLTRST),		/* GPIO */
-	PAD_NC(GPP_E7, NONE),
-	PAD_CFG_NF(GPP_E8, NONE, DEEP, NF2),	/* SATALED# */
-	PAD_CFG_NF(GPP_E9, NONE, PLTRST, NF1),	/* USB_OC0# */
-	PAD_CFG_NF(GPP_E10, NONE, PLTRST, NF1),	/* USB_OC1# */
-	PAD_CFG_NF(GPP_E11, NONE, PLTRST, NF1),	/* USB_OC2# */
-	PAD_CFG_NF(GPP_E12, NONE, PLTRST, NF1),	/* USB_OC3# */
-
-	/* ------- GPIO Group GPP_F ------- */
-	_PAD_CFG_STRUCT(GPP_F0, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0),	/* SATAXPCIE3 */
-	_PAD_CFG_STRUCT(GPP_F1, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0),	/* SATAXPCIE4 */
-	_PAD_CFG_STRUCT(GPP_F2, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0),	/* SATAXPCIE5 */
-	PAD_CFG_GPO(GPP_F3, 0, PLTRST),		/* GPIO */
-	PAD_CFG_GPO(GPP_F4, 1, PLTRST),		/* GPIO */
-	PAD_CFG_GPO(GPP_F5, 1, PLTRST),		/* GPIO */
-	PAD_NC(GPP_F6, NONE),
-	PAD_CFG_GPO(GPP_F7, 1, PLTRST),		/* GPIO */
-	PAD_NC(GPP_F8, NONE),
-	PAD_CFG_GPO(GPP_F9, 1, PLTRST),		/* GPIO */
-	PAD_NC(GPP_F10, NONE),
-	PAD_CFG_GPO(GPP_F11, 1, PLTRST),	/* GPIO */
-	PAD_CFG_GPO(GPP_F12, 1, DEEP),		/* GPIO */
-	PAD_CFG_GPO(GPP_F13, 1, PLTRST),	/* GPIO */
-	PAD_CFG_NF(GPP_F14, NONE, PLTRST, NF1),	/* PS_ON# */
-	PAD_CFG_GPI_TRIG_OWN(GPP_F15, NONE, DEEP, OFF, ACPI),	/* GPIO */
-	PAD_CFG_GPO(GPP_F16, 1, PLTRST),	/* GPIO */
-	PAD_NC(GPP_F17, NONE),
-	PAD_CFG_GPO(GPP_F18, 1, PLTRST),	/* GPIO */
-	_PAD_CFG_STRUCT(GPP_F19, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),	/* eDP_VDDEN */
-	_PAD_CFG_STRUCT(GPP_F20, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),	/* eDP_BKLTEN */
-	_PAD_CFG_STRUCT(GPP_F21, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),	/* eDP_BKLTCTL */
-	PAD_NC(GPP_F22, NONE),
-	PAD_CFG_GPO(GPP_F23, 1, PLTRST),	/* GPIO */
-
-	/* ------- GPIO Community 4 ------- */
+	PAD_NC(GPP_G8, NONE),
+	PAD_NC(GPP_G9, NONE),
+	PAD_NC(GPP_G10, NONE),
+	PAD_NC(GPP_G11, NONE),
+	PAD_CFG_NF(GPP_G12, NATIVE, DEEP, NF1),		// DDP1_CTRLCLK
+	PAD_CFG_NF(GPP_G13, NATIVE, DEEP, NF1),		// DDP1_CTRLDATA
+	PAD_CFG_NF(GPP_G14, NATIVE, DEEP, NF1),		// DDP2_CTRLCLK
+	PAD_CFG_NF(GPP_G15, NATIVE, DEEP, NF1),		// DDP2_CTRLDATA
 
 	/* ------- GPIO Group GPP_H ------- */
-	PAD_NC(GPP_H0, NONE),
-	PAD_NC(GPP_H1, NONE),
-	PAD_NC(GPP_H2, NONE),
-	PAD_NC(GPP_H3, NONE),
-	PAD_NC(GPP_H4, NONE),
-	PAD_NC(GPP_H5, NONE),
-	PAD_CFG_NF(GPP_H6, NONE, DEEP, NF1),	// SRCCLKREQ12
-	PAD_CFG_NF(GPP_H7, NONE, DEEP, NF1),	// SRCCLKREQ13
-	PAD_CFG_NF(GPP_H8, NONE, DEEP, NF1),	// SRCCLKREQ14
-	PAD_CFG_NF(GPP_H9, NONE, DEEP, NF1),	// SRCCLKREQ15
-	PAD_CFG_GPO(GPP_H10, 1, PLTRST),	// GPIO */
+
+	// We don't know the mapping of SRCCLKREQs because vendor refused to share schematics. Leave their configuration to the FSP.
+
+	PAD_CFG_GPO(GPP_H10, 1, PLTRST),		// GPIO */
 	PAD_NC(GPP_H11, NONE),
-	PAD_CFG_GPO(GPP_H12, 1, PLTRST),	/* GPIO */
-	PAD_CFG_GPO(GPP_H13, 1, PLTRST),	/* GPIO */
-	PAD_CFG_GPO(GPP_H14, 0, PLTRST),	/* GPIO */
-	PAD_CFG_GPO(GPP_H15, 1, PLTRST),	/* GPIO */
-	PAD_CFG_GPO(GPP_H16, 1, PLTRST),	/* GPIO */
-	PAD_CFG_GPO(GPP_H17, 1, PLTRST),	/* GPIO */
-	PAD_CFG_GPO(GPP_H18, 0, PLTRST),	/* GPIO */
+	PAD_CFG_GPO(GPP_H12, 1, PLTRST),		/* GPIO */
+	PAD_CFG_GPO(GPP_H13, 1, PLTRST),		/* GPIO */
+	PAD_CFG_GPO(GPP_H14, 0, PLTRST),		/* GPIO */
+	PAD_CFG_GPO(GPP_H15, 1, PLTRST),		/* GPIO */
+	PAD_CFG_GPO(GPP_H16, 1, PLTRST),		/* GPIO */
+	PAD_CFG_GPO(GPP_H17, 1, PLTRST),		/* GPIO */
+	PAD_CFG_GPO(GPP_H18, 0, PLTRST),		/* GPIO */
 	PAD_NC(GPP_H19, NONE),
 	PAD_NC(GPP_H20, NONE),
 	PAD_NC(GPP_H21, NONE),
 	PAD_NC(GPP_H22, NONE),
-	PAD_CFG_GPO(GPP_H23, 1, PLTRST),	/* GPIO */
-
-	/* ------- GPIO Group GPP_J ------- */
-	PAD_CFG_GPO(GPP_J0, 1, PLTRST),	/* GPIO */
-	_PAD_CFG_STRUCT(GPP_J1, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),	/* CPU_C10_GATE# */
-	_PAD_CFG_STRUCT(GPP_J2, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),	/* CNV_BRI_DT */
-	_PAD_CFG_STRUCT(GPP_J3, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), PAD_PULL(UP_20K)),	/* CNV_BRI_RSP */
-	_PAD_CFG_STRUCT(GPP_J4, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),	/* CNV_RGI_DT */
-	_PAD_CFG_STRUCT(GPP_J5, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), PAD_PULL(UP_20K)),	/* CNV_RGI_RSP */
-	PAD_NC(GPP_J6, NONE),
-	PAD_CFG_GPI_TRIG_OWN(GPP_J7, NONE, RSMRST, OFF, ACPI),	/* GPIO */
-	PAD_CFG_GPO(GPP_J8, 1, PLTRST),	/* GPIO */
-	PAD_CFG_GPO(GPP_J9, 1, PLTRST),	/* GPIO */
-
-	/* ------- GPIO Group GPP_K ------- */
-	PAD_CFG_GPO(GPP_K0, 1, PLTRST),	/* GPIO */
-	PAD_CFG_GPO(GPP_K1, 1, PLTRST),	/* GPIO */
-	PAD_CFG_GPO(GPP_K2, 1, PLTRST),	/* GPIO */
-	PAD_CFG_GPO(GPP_K3, 1, PLTRST),	/* GPIO */
-	PAD_CFG_GPO(GPP_K4, 1, PLTRST),	/* GPIO */
-	PAD_CFG_GPO(GPP_K5, 1, PLTRST),	/* GPIO */
-	_PAD_CFG_STRUCT(GPP_K6, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),	/* DDSP_HPDA */
-	_PAD_CFG_STRUCT(GPP_K7, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),	/* DDSP_HPDB */
-	_PAD_CFG_STRUCT(GPP_K8, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),	/* CORE_VID0 */
-	_PAD_CFG_STRUCT(GPP_K9, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),	/* CORE_VID1 */
-	PAD_CFG_GPO(GPP_K10, 1, PLTRST),	/* GPIO */
-	PAD_NC(GPP_K11, NONE),
-
-	/* ------- GPIO Community 5 ------- */
+	PAD_CFG_GPO(GPP_H23, 1, PLTRST),		/* GPIO */
 
 	/* ------- GPIO Group GPP_I ------- */
-	_PAD_CFG_STRUCT(GPP_I0, PAD_FUNC(NF1) | PAD_RESET(RSMRST) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0),	/* PMCALERT# */
-	_PAD_CFG_STRUCT(GPP_I1, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),	/* DDSP_HPD1 */
-	_PAD_CFG_STRUCT(GPP_I2, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0),	/* DDSP_HPD2 */
-	_PAD_CFG_STRUCT(GPP_I3, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),	/* DDSP_HPD3 */
-	_PAD_CFG_STRUCT(GPP_I4, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),	/* DDSP_HPD4 */
-	_PAD_CFG_STRUCT(GPP_I5, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),	/* DDPB_CTRLCLK */
-	_PAD_CFG_STRUCT(GPP_I6, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), 0),	/* DDPB_CTRLDATA */
-	PAD_NC(GPP_I7, NONE),
-	PAD_CFG_GPO(GPP_I8, 1, PLTRST),	/* GPIO */
-	PAD_CFG_GPO(GPP_I9, 1, PLTRST),	/* GPIO */
-	PAD_CFG_GPO(GPP_I10, 1, PLTRST),	/* GPIO */
-	_PAD_CFG_STRUCT(GPP_I11, PAD_FUNC(NF2) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0),	/* I2C4_SDA */
-	_PAD_CFG_STRUCT(GPP_I12, PAD_FUNC(NF2) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0),	/* I2C4_SCL */
-	_PAD_CFG_STRUCT(GPP_I13, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0),	/* USB_OC6# */
-	_PAD_CFG_STRUCT(GPP_I14, PAD_FUNC(NF2) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0),	/* I2C5_SCL */
+	PAD_CFG_NF(GPP_I0, NONE, RSMRST, NF1),		// PMCALERT#
+	PAD_CFG_NF(GPP_I1, NONE, DEEP, NF1),		// DDSP_HPD1
+	PAD_CFG_NF(GPP_I2, NONE, DEEP, NF1),		// DDSP_HPD2
+	PAD_NC(GPP_I3, NONE),
+	PAD_NC(GPP_I4, NONE),
+	PAD_CFG_NF(GPP_I5, NATIVE, DEEP, NF1),		// DDPB_CTRLCLK
+	PAD_CFG_NF(GPP_I6, NATIVE, DEEP, NF1),		// DDPB_CTRLDATA
+	PAD_CFG_NF(GPP_I7, NATIVE, DEEP, NF1),		// DDPC_CTRLCLK
+	PAD_CFG_NF(GPP_I8, NATIVE, DEEP, NF1),		// DDPC_CTRLDATA
+	PAD_CFG_GPO(GPP_I9, 1, PLTRST),			/* GPIO */
+	PAD_CFG_GPO(GPP_I10, 1, PLTRST),		/* GPIO */
+	PAD_CFG_NF(GPP_I11, NONE, DEEP, NF2),		// I2C4_SDA
+	PAD_CFG_NF(GPP_I12, NONE, DEEP, NF2),		// I2C4_SCL
+	PAD_CFG_NF(GPP_I13, NONE, DEEP, NF1),		// USB_OC6#
+	PAD_CFG_NF(GPP_I14, NONE, DEEP, NF2),		// I2C5_SCL
+
+	/* ------- GPIO Group GPP_J ------- */
+	PAD_CFG_GPO(GPP_J0, 1, PLTRST),			/* GPIO */
+	PAD_CFG_NF(GPP_J1, NONE, DEEP, NF1),		// CPU_C10_GATE#
+	PAD_CFG_NF(GPP_J2, NONE, DEEP, NF1),		// CNVI_BRI_DT
+	PAD_CFG_NF(GPP_J3, UP_20K, DEEP, NF1),		// CNVI_BRI_RSP
+	PAD_CFG_NF(GPP_J4, NONE, DEEP, NF1),		// CNVI_RGI_DT
+	PAD_CFG_NF(GPP_J5, UP_20K, DEEP, NF1),		// CNVI_RGI_RSP
+	PAD_CFG_NF(GPP_J6, NONE, DEEP, NF1),		// CNVI_MFUART2_RXD
+	PAD_CFG_NF(GPP_J7, NONE, DEEP, NF1),		// CNVI_MFUART2_TXD
+	PAD_CFG_GPO(GPP_J8, 1, PLTRST),			/* GPIO */
+	PAD_CFG_GPO(GPP_J9, 1, PLTRST),			/* GPIO */
+
+	/* ------- GPIO Group GPP_K ------- */
+	PAD_CFG_GPO(GPP_K0, 1, PLTRST),			/* GPIO */
+	PAD_CFG_GPO(GPP_K1, 1, PLTRST),			/* GPIO */
+	PAD_CFG_GPO(GPP_K2, 1, PLTRST),			/* GPIO */
+	PAD_CFG_GPO(GPP_K3, 1, PLTRST),			/* GPIO */
+	PAD_CFG_GPO(GPP_K4, 1, PLTRST),			/* GPIO */
+	PAD_CFG_GPO(GPP_K5, 1, PLTRST),			/* GPIO */
+	PAD_NC(GPP_K6, NONE),
+	PAD_CFG_NF(GPP_K7, NONE, DEEP, NF1),		// DDSP_HPDB
+	PAD_CFG_NF(GPP_K8, NONE, DEEP, NF1),		// CORE_VID0
+	PAD_CFG_NF(GPP_K9, NONE, DEEP, NF1),		// CORE_VID1
+	PAD_CFG_NF(GPP_K10, NONE, DEEP, NF1),		// DDSP_HPDC
+	PAD_NC(GPP_K11, NONE),
+
+	/* ------- GPIO Group GPP_R ------- */
+	PAD_CFG_NF(GPP_R0, NONE, DEEP, NF1),		// HDA_BCLK
+	PAD_CFG_NF(GPP_R1, NATIVE, DEEP, NF1),		// HDA_SYNC
+	PAD_CFG_NF(GPP_R2, NATIVE, DEEP, NF1),		// HDA_SDO
+	PAD_CFG_NF(GPP_R3, NATIVE, DEEP, NF1),		// HDA_SDI
+	PAD_CFG_NF(GPP_R4, NONE, DEEP, NF1),		// HDA_RST#
+	// Using HDA instead of SOF, disable I2S
+	PAD_NC(GPP_R5, NONE),
+	PAD_NC(GPP_R6, NONE),
+	PAD_NC(GPP_R7, NONE),
+	PAD_NC(GPP_R8, NONE),
+	PAD_CFG_NF(GPP_R9, NATIVE, DEEP, NF1),		// PCIE_LNK_DOWN
+	PAD_CFG_NF(GPP_R10, NATIVE, DEEP, NF1),		// ISH_UART0_RTS#
+	PAD_CFG_NF(GPP_R11, NATIVE, DEEP, NF1),		// SX_EXIT_HOLDOFF#
+	PAD_CFG_NF(GPP_R12, NATIVE, DEEP, NF1),		// CLKOUT_48
+	PAD_CFG_NF(GPP_R13, NATIVE, DEEP, NF1),		// ISH_GP7
+	PAD_NC(GPP_R14, NONE),
+	PAD_NC(GPP_R15, NONE),
+	PAD_NC(GPP_R16, NONE),
+	PAD_NC(GPP_R17, NONE),
+	PAD_CFG_GPO(GPP_R18, 1, PLTRST),		// GPO, some kind of VR?
+	PAD_NC(GPP_R19, NONE),
+
+	/* ------- GPIO Group GPP_S (SoundWire - unused) ------- */
+	PAD_NC(GPP_S0, NONE),
+	PAD_NC(GPP_S1, NONE),
+	PAD_NC(GPP_S2, NONE),
+	PAD_NC(GPP_S3, NONE),
+	PAD_NC(GPP_S4, NONE),
+	PAD_NC(GPP_S5, NONE),
+	PAD_NC(GPP_S6, NONE),
+	PAD_NC(GPP_S7, NONE),
+
+	/* ------- GPIO Group GPD ------- */
+	PAD_CFG_NF(GPD0, UP_20K, PWROK, NF1),		// BATLOW#
+	PAD_CFG_NF(GPD1, NATIVE, PWROK, NF1),		// ACPRESENT
+	PAD_CFG_NF(GPD2, NATIVE, PLTRST, NF1),		// LAN_WAKE#
+	PAD_CFG_NF(GPD3, UP_20K, PLTRST, NF1),		// PWRBTN#
+	PAD_CFG_NF(GPD4, NONE, PLTRST, NF1),		// SLP_S3#
+	PAD_CFG_NF(GPD5, NONE, PLTRST, NF1),		// SLP_S4#
+	PAD_CFG_NF(GPD6, NONE, PLTRST, NF1),		// SLP_A#
+	PAD_CFG_GPO(GPD7, 1, PLTRST),			// GPIO
+	PAD_CFG_NF(GPD8, NONE, PLTRST, NF1),		// SUSCLK
+	PAD_CFG_NF(GPD9, NONE, PLTRST, NF1),		// SLP_WLAN#
+	PAD_CFG_NF(GPD10, NONE, PLTRST, NF1),		// SLP_S5#
+	PAD_CFG_NF(GPD11, NONE, PLTRST, NF1),		// LANPHYPC
+	PAD_NC(GPD12, NONE),				// GPIO
 };

From 23e92a5ac0f94e6914b1eafa5c86d9e5091f990d Mon Sep 17 00:00:00 2001
From: Alicja Michalska <alicja.michalska@9elements.com>
Date: Fri, 8 Aug 2025 02:30:50 +0200
Subject: [PATCH 1862/3886] mb/erying/tgl: Map remaining USB ports

All USB ports are working \o/

Change-Id: I49aa8a245f656b8b6e47ce3a0e69899c052cf3f3
Signed-off-by: Alicja Michalska <alicja.michalska@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88716
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
---
 src/mainboard/erying/tgl/devicetree.cb | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/src/mainboard/erying/tgl/devicetree.cb b/src/mainboard/erying/tgl/devicetree.cb
index c6cd68d1ae..2558bd6c62 100644
--- a/src/mainboard/erying/tgl/devicetree.cb
+++ b/src/mainboard/erying/tgl/devicetree.cb
@@ -74,10 +74,13 @@ chip soc/intel/tigerlake
 				[3] = USB2_PORT_MID(OC_SKIP),		/* NIC right */
 				[4] = USB2_PORT_MID(OC_SKIP),		/* Front Panel 1 */
 				[5] = USB2_PORT_MID(OC_SKIP),		/* Front Panel 2 */
+				[6] = USB2_PORT_MID(OC_SKIP),		/* Front Panel 3 */
+				[7] = USB2_PORT_MID(OC_SKIP),		/* Front Panel 4 */
 				[8] = USB2_PORT_MID(OC_SKIP),		/* Front Panel 1 (USB3) */
 				[9] = USB2_PORT_MID(OC_SKIP),		/* Front Panel 2 (USB3) */
 				[10] = USB2_PORT_MID(OC_SKIP),		/* Rear, top left */
 				[11] = USB2_PORT_MID(OC_SKIP),		/* Rear, top right */
+				[12] = USB2_PORT_MID(OC_SKIP),		/* M.2 NGFF (Bluetooth) */
 			}"
 
 			register "usb3_ports" = "{

From 261b6b4fd1d0d30bb3a94f2350002748e390df9b Mon Sep 17 00:00:00 2001
From: Felix Singer <felixsinger@posteo.net>
Date: Wed, 26 Jun 2024 04:24:31 +0200
Subject: [PATCH 1863/3886] soc/intel/skylake: Allow generating USB ACPI code

Hook up to the USB ACPI driver and enable the generation of ACPI code
for enabled USB devices.

Change-Id: I53fc73046e4b107064fa8c3c617ba6d9b807b71d
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83211
Reviewed-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
---
 src/soc/intel/skylake/Kconfig    |  1 +
 src/soc/intel/skylake/chipset.cb | 56 +++++++++++++++++++++++++++++++-
 2 files changed, 56 insertions(+), 1 deletion(-)

diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig
index 4977e8d25d..7c530f2c75 100644
--- a/src/soc/intel/skylake/Kconfig
+++ b/src/soc/intel/skylake/Kconfig
@@ -12,6 +12,7 @@ config SOC_INTEL_COMMON_SKYLAKE_BASE
 	select CPU_SUPPORTS_PM_TIMER_EMULATION
 	select DRAM_SUPPORT_DDR3
 	select DRAM_SUPPORT_DDR4
+	select DRIVERS_USB_ACPI
 	select EDK2_CPU_TIMER_LIB if PAYLOAD_EDK2
 	select FSP_COMPRESS_FSP_S_LZ4
 	select FSP_M_XIP
diff --git a/src/soc/intel/skylake/chipset.cb b/src/soc/intel/skylake/chipset.cb
index 6538a1475b..dfb81d496e 100644
--- a/src/soc/intel/skylake/chipset.cb
+++ b/src/soc/intel/skylake/chipset.cb
@@ -13,7 +13,61 @@ chip soc/intel/skylake
 		device pci 07.0 alias chap         off                     end
 		device pci 08.0 alias gmm          off                     end # Gaussian Mixture Model
 		device pci 13.0 alias ish          off                     end # SensorHub
-		device pci 14.0 alias south_xhci   off ops usb_xhci_ops    end
+		device pci 14.0 alias south_xhci   off ops usb_xhci_ops
+			chip drivers/usb/acpi
+				register "type" = "UPC_TYPE_HUB"
+				device usb 0.0 alias xhci_root_hub off
+					chip drivers/usb/acpi
+						device usb 2.0 alias usb2_port1 off end
+					end
+					chip drivers/usb/acpi
+						device usb 2.1 alias usb2_port2 off end
+					end
+					chip drivers/usb/acpi
+						device usb 2.2 alias usb2_port3 off end
+					end
+					chip drivers/usb/acpi
+						device usb 2.3 alias usb2_port4 off end
+					end
+					chip drivers/usb/acpi
+						device usb 2.4 alias usb2_port5 off end
+					end
+					chip drivers/usb/acpi
+						device usb 2.5 alias usb2_port6 off end
+					end
+					chip drivers/usb/acpi
+						device usb 2.6 alias usb2_port7 off end
+					end
+					chip drivers/usb/acpi
+						device usb 2.7 alias usb2_port8 off end
+					end
+					chip drivers/usb/acpi
+						device usb 2.8 alias usb2_port9 off end
+					end
+					chip drivers/usb/acpi
+						device usb 2.9 alias usb2_port10 off end
+					end
+					chip drivers/usb/acpi
+						device usb 3.0 alias usb3_port1 off end
+					end
+					chip drivers/usb/acpi
+						device usb 3.1 alias usb3_port2 off end
+					end
+					chip drivers/usb/acpi
+						device usb 3.2 alias usb3_port3 off end
+					end
+					chip drivers/usb/acpi
+						device usb 3.3 alias usb3_port4 off end
+					end
+					chip drivers/usb/acpi
+						device usb 3.4 alias usb3_port5 off end
+					end
+					chip drivers/usb/acpi
+						device usb 3.5 alias usb3_port6 off end
+					end
+				end
+			end
+		end
 		device pci 14.1 alias south_xdci   off ops usb_xdci_ops    end
 		device pci 14.2 alias thermal      off                     end
 		device pci 14.3 alias cio          off                     end

From 23cf7c64f9ef834258a90502782a6abeea73c6c7 Mon Sep 17 00:00:00 2001
From: Alicja Michalska <alicja.michalska@9elements.com>
Date: Fri, 8 Aug 2025 02:32:07 +0200
Subject: [PATCH 1864/3886] mb/erying/tgl: Use booleans in devicetree

Looks a bit neater

Change-Id: Ia76e003ba70b4a2be7e5414ffa13e65f15baccc8
Signed-off-by: Alicja Michalska <alicja.michalska@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88717
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/erying/tgl/devicetree.cb | 24 ++++++++++++------------
 1 file changed, 12 insertions(+), 12 deletions(-)

diff --git a/src/mainboard/erying/tgl/devicetree.cb b/src/mainboard/erying/tgl/devicetree.cb
index 2558bd6c62..7bf1566823 100644
--- a/src/mainboard/erying/tgl/devicetree.cb
+++ b/src/mainboard/erying/tgl/devicetree.cb
@@ -14,8 +14,8 @@ chip soc/intel/tigerlake
 	register "tcc_offset" = "8"
 
 	# FSP configuration
-	register "eist_enable" = "1"
-	register "enable_c6dram" = "1"
+	register "eist_enable" = "true"
+	register "enable_c6dram" = "true"
 
 	register "deep_s3_enable_ac" = "true"
 	register "deep_s3_enable_dc" = "true"
@@ -36,20 +36,20 @@ chip soc/intel/tigerlake
 		.vnn_supported_voltage_bitmap = 0,
 		.v1p05_icc_max_ma = 500,
 		.vnn_sx_voltage_mv = 1050,
-        }"
+	}"
 
 	device cpu_cluster 0 on end
 	device domain 0 on
 		device ref igpu on
 			register "DdiPortBConfig" = "DDI_PORT_CFG_NO_LFP" # DP
-			register "DdiPortBHpd" = "1"
-			register "DdiPortBDdc" = "1"
+			register "DdiPortBHpd" = "true"
+			register "DdiPortBDdc" = "true"
 
-			register "DdiPortCHpd" = "1" # HDMI
-			register "DdiPortCDdc" = "1"
+			register "DdiPortCHpd" = "true" # HDMI
+			register "DdiPortCDdc" = "true"
 
-			register "DdiPort1Hpd" = "1" # HDMI
-			register "DdiPort1Ddc" = "1"
+			register "DdiPort1Hpd" = "true" # HDMI
+			register "DdiPort1Ddc" = "true"
 		end
 
 		device ref peg0 on	# SoC M.2 (Gen4)
@@ -63,7 +63,7 @@ chip soc/intel/tigerlake
 		end
 
 		device ref north_xhci on
-			 register "TcssXhciEn" = "1"
+			 register "TcssXhciEn" = "true"
 		end
 
 		device ref south_xhci on
@@ -108,7 +108,7 @@ chip soc/intel/tigerlake
 				[2] = 1,
 				[3] = 1,
 			}"
-			register "SataSalpSupport" = "1"
+			register "SataSalpSupport" = "true"
 		end
 
 		device ref pcie_rp5 on		# PCH M.2 (Gen3)
@@ -198,7 +198,7 @@ chip soc/intel/tigerlake
 		device ref p2sb hidden end
 		device ref hda on
 			subsystemid 0x10ec 0x3000
-			register "PchHdaAudioLinkHdaEnable" = "1"
+			register "PchHdaAudioLinkHdaEnable" = "true"
 		end
 		device ref smbus on end
 	end

From 73cba1fdea7059aba04ef05ca273650f1d697544 Mon Sep 17 00:00:00 2001
From: Alicja Michalska <alicja.michalska@9elements.com>
Date: Fri, 8 Aug 2025 04:14:23 +0200
Subject: [PATCH 1865/3886] mb/erying/tgl: Introduce CFR

Change-Id: I26e502d26d3498c623730f0a2fbc39bb96706c57
Signed-off-by: Alicja Michalska <alicja.michalska@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88718
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
---
 src/mainboard/erying/tgl/Makefile.mk |  1 +
 src/mainboard/erying/tgl/cfr.c       | 56 ++++++++++++++++++++++++++++
 2 files changed, 57 insertions(+)
 create mode 100644 src/mainboard/erying/tgl/cfr.c

diff --git a/src/mainboard/erying/tgl/Makefile.mk b/src/mainboard/erying/tgl/Makefile.mk
index 9bda2eb52b..8fb83ba37b 100644
--- a/src/mainboard/erying/tgl/Makefile.mk
+++ b/src/mainboard/erying/tgl/Makefile.mk
@@ -5,3 +5,4 @@ bootblock-y += bootblock.c
 romstage-y += romstage_fsp_params.c
 
 ramstage-y += ramstage.c
+ramstage-$(CONFIG_DRIVERS_OPTION_CFR) += cfr.c
diff --git a/src/mainboard/erying/tgl/cfr.c b/src/mainboard/erying/tgl/cfr.c
new file mode 100644
index 0000000000..e27f8b399a
--- /dev/null
+++ b/src/mainboard/erying/tgl/cfr.c
@@ -0,0 +1,56 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <boot/coreboot_tables.h>
+#include <drivers/option/cfr_frontend.h>
+#include <intelblocks/cfr.h>
+#include <soc/cfr.h>
+
+static struct sm_obj_form platform = {
+	.ui_name = "Platform",
+	.obj_list = (const struct sm_object *[]) {
+		&me_state,
+		&me_state_counter,
+		&legacy_8254_timer,
+		&vtd,
+		NULL
+	},
+};
+
+static struct sm_obj_form igpu = {
+	.ui_name = "Integrated Graphics",
+	.obj_list = (const struct sm_object *[]) {
+		&igd_dvmt,
+		&igd_aperture,
+		NULL
+	},
+};
+
+static struct sm_obj_form performance = {
+	.ui_name = "Performance",
+	.obj_list = (const struct sm_object *[]) {
+		&hyper_threading,
+		&pciexp_speed,
+		NULL
+	},
+};
+
+static struct sm_obj_form power = {
+	.ui_name = "Power",
+	.obj_list = (const struct sm_object *[]) {
+		&power_on_after_fail,
+		NULL
+	},
+};
+
+static struct sm_obj_form *sm_root[] = {
+	&platform,
+	&igpu,
+	&performance,
+	&power,
+	NULL
+};
+
+void mb_cfr_setup_menu(struct lb_cfr *cfr_root)
+{
+	cfr_write_setup_menu(cfr_root, sm_root);
+}

From 7e73d4ef3029aa11a2ec5a4d4e9d7b960fe7cc76 Mon Sep 17 00:00:00 2001
From: Alicja Michalska <alicja.michalska@9elements.com>
Date: Fri, 8 Aug 2025 05:57:13 +0200
Subject: [PATCH 1866/3886] Documentation: mb/erying/tgl: Update documentation

EDK2 driver for loading OpROMs have been merged into Matt's tree, and
should also be merged into main UefiPayloadPkg repo in upcoming
days/weeks.

With recent patches, DP and USB ports are working perfectly.

Change-Id: I9bef2c7e5a84660231abad9da69c0ec73e8b6507
Signed-off-by: Alicja Michalska <alicja.michalska@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88719
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Reviewed-by: Nicholas <nic.c3.14@gmail.com>
---
 .../mainboard/erying/tgl/tgl_matx.md          | 75 +++++++------------
 1 file changed, 27 insertions(+), 48 deletions(-)

diff --git a/Documentation/mainboard/erying/tgl/tgl_matx.md b/Documentation/mainboard/erying/tgl/tgl_matx.md
index 76437fb607..2bb1b64e0a 100644
--- a/Documentation/mainboard/erying/tgl/tgl_matx.md
+++ b/Documentation/mainboard/erying/tgl/tgl_matx.md
@@ -20,29 +20,23 @@ To build full working image of coreboot, the following blobs are required:
 +-----------------+---------------------------------+----------------------+
 ```
 
-Microcode for those SoCs cannot be generated from the tree.
-While boards with D1 (production) stepping may work, microcode Intel had
-included in their tree is too old, which causes issues with APIC
-(Advanced Programmable Interrupt Controller), resulting in overall instability.
+Microcode for D0 stepping cannot be generated from the tree.
+Therefore, including external microcode is **mandatory** for boards sold with
+D0 stepping (Engineering Sample).
 
-This is **required** for boards sold with D0 SoC revision (Engineering Sample).
 Maintainer of this port had included publicly-available [microcodes] in
 `3rdparty/blobs` coreboot repository, which are being pulled as submodule.
 
-To choose appropriate microcode for your system, you should choose:
-1. If your motherboard uses Engineering Sample (D0) stepping:
-	- `cpu806D0_platC2_ver00000054_2021-05-07_PRD_B0F9E245.bin`
-2. If your motherboard uses retail (D1) stepping:
-	- `cpu806D1_platC2_ver00000046_2023-02-27_PRD_08E6188A.bin`
+Microcode binary for D0 stepping is called
+`cpu806D0_platC2_ver00000054_2021-05-07_PRD_B0F9E245.bin`.
 
-By going to `Chipset -> Include CPU microcode in CBFS
-(Include external microcode binary)`
+It should be selected by going to:
+`Chipset -> Include CPU microcode in CBFS (Include external microcode binary)`.
 
-Failure to choose an appropriate microcode may result in:
-- Bricked (unbootable) board
-- Issues with APIC, resulting in random freezes
-- MCE (Machine Check Exception) errors
-- Unstable system RAM, leading to bit flips and data corruption
+Failure to choose an appropriate microcode will result in:
+- MCE (Machine Check Exception) errors.
+- Issues with APIC, resulting in random hangs.
+- Unstable system RAM, leading to bit flips and data corruption.
 
 There are no extra steps required for FSP.
 Both SKUs work perfectly with FSP Intel publishes in their public repository.
@@ -88,7 +82,7 @@ despite using mobile SoC and PCH.
 - RS232 serial output from IT8613E for debugging (cbmem, Linux)
 - Fan control from userspace (IT8613E Environment Controller)
 - USB2.0 and 3.0
-- HDMI (iGPU, including audio)
+- HDMI, DisplayPort (iGPU, including audio)
 - Realtek RTL8111 (GbE NIC)
 - Realtek ALC897 (integrated audio)
 - PCIe x16 4.0 (SoC)
@@ -106,19 +100,14 @@ despite using mobile SoC and PCH.
 - XMP Profiles (some people reported issues, despite successful tests).
 You can enable it by setting `SpdProfileSelected` in `romstage_fsp_params.c`.
 See [FSP XMP flags] for configuration options, proceed with caution.
-- GOP init on external GPUs (most EDK2 branches do not include module
-necessary to load external Option ROMs)
-- Sleep states (which were broken on stock as well)
-- USB3.2 might take few tries to get detected at full speed
-- iGPU DisplayPort (very simple fix, did not have time to fix GPIO)
-- Automatic fan control (fans will always spin at 50% - see below)
-- 2x USB2.0 FP and M.2 NGFF USB2.0 not mapped (yet)
-- PCIe ASPM (results in AER spam in dmesg)
+- Sleep states (which were broken on stock as well, RAM loses power in S3).
+- Automatic fan control (fans will always spin at 50% - see below).
+- PCIe ASPM (results in AER spam in dmesg).
 
 Please ensure to:
-- Disable sleep state in your OS to prevent data loss
+- Disable sleep state in your OS.
 - Configure automatic fan control using pwmconfig
-(`modprobe it87 force_id=0x8603`)
+(`modprobe it87 force_id=0x8603`).
 - Append `pcie_aspm=off` to your kernel commandline to avoid dmesg spam.
 
 ## Notes
@@ -126,7 +115,7 @@ Please ensure to:
 1. Required blobs, if flashing the entire flash chip.
    They can be skipped safely if you are planning on flashing
    only the `SI_BIOS` region.
-    - Intel Flash Descriptor (IFD): `descriptor.bin`
+    - Intel Flash Descriptor (IFD): `fd.bin`
     - Intel Management Engine (ME): `me.bin`
 
     Both blobs included in `3rdparty/blobs` repository were extracted
@@ -151,29 +140,21 @@ Please ensure to:
     - U-Boot
     - LinuxBoot (U-Root + Linux kernel)
 
-If you would like to see output on your iGPU before that stage
-(for picking a different boot medium or toggling Secure Boot setting),
-you need to use [MrChromebox's EDK2] fork and include [GOP driver] for
-TigerLake iGPU in your build.
-
-This will allow you to see output of EDK2 (payload, boot picker)
-on your monitor connected to iGPU.
-
 If you're planning to primarly use an external card, disable iGPU by
 enabling `Chipset -> Disable Integrated GFX Controller (0:2:0)`
-and use [elly's EDK2] tree.
+and use [MrChromebox's EDK2] tree.
 
-In order to enable loading Option ROMs from PCIe devices, go to:
-`Payload -> edk2 additional custom build parameters`
-and add the string: `-D LOAD_OPTION_ROMS=TRUE`
+In order to enable loading Option ROMs from PCIe devices, enable:
+`Payload -> Load and Execute OpROMs on PCIe devices`
 
 This functionality has been tested with following graphics cards,
 with following results:
-- Nvidia GeForce RTX3080, RTX3090: Works perfectly
-- AMD Radeon RX6600XT, RX7800XT: Works with ReBAR disabled,
-no output in EDK2 with ReBAR enabled
-- Intel Arc A580: Works with ReBAR disabled,
-corrupted framebuffer before modprobing with ReBAR enabled
+- Nvidia GeForce RTX3080, RTX3090: Works perfectly.
+- AMD Radeon RX6600XT, RX7800XT: Works, but requires
+`Extend resource window for PCIe devices above 4G` if `Support PCIe
+Resizable BARs` is enabled.
+- Intel Arc A580: Works, but option
+`Extend resource window for PCIe devices above 4G` is **mandatory**.
 
 ## Specification
 
@@ -197,7 +178,5 @@ corrupted framebuffer before modprobing with ReBAR enabled
 [microcodes]: https://github.com/platomav/CPUMicrocodes/tree/master/Intel
 [FSP XMP Flags]: https://github.com/intel/FSP/blob/master/TigerLakeFspBinPkg/Client/Include/FspmUpd.h#L586-L591
 [MrChromebox's EDK2]: https://github.com/MrChromebox/edk2
-[elly's EDK2]: https://github.com/ellyq/edk2
-[GOP driver]: https://github.com/MrChromebox/blobs/blob/master/soc/intel/tgl/IntelGopDriver.efi
 [flashrom]: https://flashrom.org/
 [flashprog]: https://flashprog.org/wiki/Flashprog

From 482a2d65488c5eb877c88e10ddaebe91879d4510 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Micha=C5=82=20=C5=BBygowski?= <michal.zygowski@3mdeb.com>
Date: Sat, 26 Apr 2025 20:07:08 +0200
Subject: [PATCH 1867/3886] nb/intel/sandybridge/northbridge.c: Disable
 non-active PEG devices
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

TXT SINIT ACM checks the PEG bridge memory ranges whether they are
correctly assigned in the MMIO space. If the bridge is enabled but no
device is attached to it, coreboot will not assign any resources (if
hotplug is not enabled). When SINIT ACM checks the ranges, it fails
on prefetchable range check.

Hide the PEG devices if the bridge is not active. PCIe bridges should
generally be hidden if hotplug is not enabled and there is no
downstream device.

TEST=Perform successful measured launch of Xen with Intel TXT on Dell
OptiPlex 9010.

Change-Id: I0bd104ab416376e96102738f2e47c8ce041497a2
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87472
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
---
 src/northbridge/intel/sandybridge/northbridge.c | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/src/northbridge/intel/sandybridge/northbridge.c b/src/northbridge/intel/sandybridge/northbridge.c
index 3db90865f7..998562cbed 100644
--- a/src/northbridge/intel/sandybridge/northbridge.c
+++ b/src/northbridge/intel/sandybridge/northbridge.c
@@ -267,17 +267,17 @@ static void disable_peg(void)
 	reg = pci_read_config32(dev, DEVEN);
 
 	dev = pcidev_on_root(1, 2);
-	if (!dev || !dev->enabled) {
+	if (!dev_is_active_bridge(dev)) {
 		printk(BIOS_DEBUG, "Disabling PEG12.\n");
 		reg &= ~DEVEN_PEG12;
 	}
 	dev = pcidev_on_root(1, 1);
-	if (!dev || !dev->enabled) {
+	if (!dev_is_active_bridge(dev)) {
 		printk(BIOS_DEBUG, "Disabling PEG11.\n");
 		reg &= ~DEVEN_PEG11;
 	}
 	dev = pcidev_on_root(1, 0);
-	if (!dev || !dev->enabled) {
+	if (!dev_is_active_bridge(dev)) {
 		printk(BIOS_DEBUG, "Disabling PEG10.\n");
 		reg &= ~DEVEN_PEG10;
 	}
@@ -292,7 +292,7 @@ static void disable_peg(void)
 		reg &= ~DEVEN_D4EN;
 	}
 	dev = pcidev_on_root(6, 0);
-	if (!dev || !dev->enabled) {
+	if (!dev_is_active_bridge(dev)) {
 		printk(BIOS_DEBUG, "Disabling PEG60.\n");
 		reg &= ~DEVEN_PEG60;
 	}

From bf0ee592f5487916f55000e46188b44b83ef7892 Mon Sep 17 00:00:00 2001
From: Kilian Krause <kilian.krause@siemens.com>
Date: Mon, 21 Jul 2025 10:49:08 +0200
Subject: [PATCH 1868/3886] soc/intel/alderlake: Make SATA speed limit
 configurable
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Add support for limiting SATA interface speed through the FSP parameter
'SataSpeedLimit'. This is useful for mainboards with physical design
constraints that require operating at lower speeds than what the
controller and drives support.

The implementation adds a new chip config option that mainboards can
set in their devicetree to control this behavior.

Change-Id: Ib0a058d006b752975c57851f2418a4e94b3bfcca
Signed-off-by: Kilian Krause <kilian.krause@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88951
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/soc/intel/alderlake/chip.h       | 7 +++++++
 src/soc/intel/alderlake/fsp_params.c | 1 +
 2 files changed, 8 insertions(+)

diff --git a/src/soc/intel/alderlake/chip.h b/src/soc/intel/alderlake/chip.h
index 25e0f6ed28..db8965e40e 100644
--- a/src/soc/intel/alderlake/chip.h
+++ b/src/soc/intel/alderlake/chip.h
@@ -341,6 +341,12 @@ enum slew_rate {
 	SLEW_FAST_16
 };
 
+enum sata_speed_limit {
+	SATA_DEFAULT,
+	SATA_GEN1,	/* 1.5 Gbps */
+	SATA_GEN2	/* 3.0 Gbps */
+};
+
 struct soc_intel_alderlake_config {
 	/* Common struct containing soc config data required by common code */
 	struct soc_intel_common_config common_soc_config;
@@ -416,6 +422,7 @@ struct soc_intel_alderlake_config {
 	bool sata_salp_support;
 	bool sata_ports_enable[8];
 	bool sata_ports_dev_slp[8];
+	enum sata_speed_limit sata_speed;
 
 	/*
 	 * Enable(0)/Disable(1) SATA Power Optimizer on PCH side.
diff --git a/src/soc/intel/alderlake/fsp_params.c b/src/soc/intel/alderlake/fsp_params.c
index 6382322786..bd6f1d548a 100644
--- a/src/soc/intel/alderlake/fsp_params.c
+++ b/src/soc/intel/alderlake/fsp_params.c
@@ -778,6 +778,7 @@ static void fill_fsps_sata_params(FSP_S_CONFIG *s_cfg,
 	if (s_cfg->SataEnable) {
 		s_cfg->SataMode = config->sata_mode;
 		s_cfg->SataSalpSupport = config->sata_salp_support;
+		s_cfg->SataSpeedLimit = config->sata_speed;
 		memcpy(s_cfg->SataPortsEnable, config->sata_ports_enable,
 			sizeof(s_cfg->SataPortsEnable));
 		memcpy(s_cfg->SataPortsDevSlp, config->sata_ports_dev_slp,

From fbcf0311811e7bb4a6d2c3945972a940d11cd360 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Carlos=20L=C3=B3pez?= <carlos.lopez@openchip.com>
Date: Tue, 17 Dec 2024 14:07:22 +0100
Subject: [PATCH 1869/3886] mb/qemu-riscv: set PCI_IOBASE
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

The correct value for the IO base is at 0x3000000, so set it. Otherwise,
I/O operations (e.g. inb(), outb(), etc.) won't work.

Change-Id: I5106fa95401de53e70f0859d27e07d2b8fde9ca0
Signed-off-by: Carlos López <carlos.lopez@openchip.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85675
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
---
 src/mainboard/emulation/qemu-riscv/Kconfig | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/src/mainboard/emulation/qemu-riscv/Kconfig b/src/mainboard/emulation/qemu-riscv/Kconfig
index 286e68441e..18eaaf081d 100644
--- a/src/mainboard/emulation/qemu-riscv/Kconfig
+++ b/src/mainboard/emulation/qemu-riscv/Kconfig
@@ -79,4 +79,8 @@ config OPENSBI_TEXT_START
 	hex
 	default 0x80020000
 
+config PCI_IOBASE
+	hex
+	default 0x3000000
+
 endif #  BOARD_EMULATION_QEMU_RISCV

From c13eadeadb0a1054bc0bef3dc6002fed2a093f57 Mon Sep 17 00:00:00 2001
From: Patrick Rudolph <patrick.rudolph@amd.com>
Date: Tue, 8 Jul 2025 08:25:27 +0200
Subject: [PATCH 1870/3886] soc/amd/common/block/psp/psp_smi_flash: Fix busy
 check

The busy check is only supported on Fam 17h Picasso and Raven Ridge.
On other platforms the register might not exist and the bits always
read as ones. This prevents the PSP SMI handler from accessing
the SPI flash.

TEST: Ensured that the code does not block on 1Ah platforms.

Signed-off-by: Patrick Rudolph <patrick.rudolph@amd.com>
Change-Id: I063b7cd66a5058ae558ad36e4a7dd89a48f718a7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88356
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
---
 src/soc/amd/common/block/psp/psp_smi_flash.c | 11 ++++++++---
 1 file changed, 8 insertions(+), 3 deletions(-)

diff --git a/src/soc/amd/common/block/psp/psp_smi_flash.c b/src/soc/amd/common/block/psp/psp_smi_flash.c
index a32ba217d2..9f9f31d94c 100644
--- a/src/soc/amd/common/block/psp/psp_smi_flash.c
+++ b/src/soc/amd/common/block/psp/psp_smi_flash.c
@@ -94,10 +94,15 @@ static enum mbox_p2c_status find_psp_spi_flash_device_region(uint64_t target_nv_
 
 static bool spi_controller_busy(void)
 {
-	const bool busy = (spi_read8(SPI_MISC_CNTRL) & SPI_SEMAPHORE_DRIVER_LOCKED);
+	bool busy = false;
 
-	if (busy)
-		printk(BIOS_NOTICE, "PSP: SPI controller busy\n");
+	if (CONFIG(SOC_AMD_PICASSO)) {
+		// Only implemented on Picasso and Raven Ridge
+		busy = (spi_read8(SPI_MISC_CNTRL) & SPI_SEMAPHORE_DRIVER_LOCKED);
+
+		if (busy)
+			printk(BIOS_NOTICE, "PSP: SPI controller busy\n");
+	}
 
 	return busy;
 }

From 00217275b20433b3a318559138fa1058ef05c029 Mon Sep 17 00:00:00 2001
From: Patrick Rudolph <patrick.rudolph@amd.com>
Date: Mon, 14 Jul 2025 17:11:12 +0200
Subject: [PATCH 1871/3886] soc/amd/common/block: Don't clobber SPI registers

Since the PSP SMI can trigger any time, even when ring 0 uses the SPI
controller backup and restore the SPI MMIO space in SMM, making
sure to not corrupt ongoing SPI transfers in ring 0.

There's still the possibility of register clobbering when the SPI
controller was busy and became ready before the SMI handler could
check the status bit.

TEST: Booted on AMD glinda with CONSOLE_SERIAL enabled and observed
      no boot failure.

Signed-off-by: Patrick Rudolph <patrick.rudolph@amd.com>
Change-Id: Iaa5270d93d4934b2e7ebdf04151f1c0d9f57cfb3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88435
Reviewed-by: Andy Ebrahiem <ahmet.ebrahiem@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
---
 src/soc/amd/cezanne/smihandler.c              | 10 ++++++++
 .../amd/common/block/include/amdblocks/spi.h  |  2 ++
 src/soc/amd/common/block/spi/fch_spi_ctrl.c   | 25 +++++++++++++++++++
 src/soc/amd/genoa_poc/smihandler.c            | 13 ++++++++++
 src/soc/amd/glinda/smihandler.c               | 13 ++++++++++
 src/soc/amd/mendocino/smihandler.c            | 13 ++++++++++
 src/soc/amd/phoenix/smihandler.c              | 13 ++++++++++
 src/soc/amd/picasso/smihandler.c              | 13 ++++++++++
 8 files changed, 102 insertions(+)

diff --git a/src/soc/amd/cezanne/smihandler.c b/src/soc/amd/cezanne/smihandler.c
index 1b6e91cb4c..51c660829c 100644
--- a/src/soc/amd/cezanne/smihandler.c
+++ b/src/soc/amd/cezanne/smihandler.c
@@ -7,6 +7,7 @@
 #include <amdblocks/smi.h>
 #include <amdblocks/smm.h>
 #include <amdblocks/smu.h>
+#include <amdblocks/spi.h>
 #include <arch/hlt.h>
 #include <arch/io.h>
 #include <console/console.h>
@@ -134,4 +135,13 @@ void smm_soc_early_init(void)
 {
 	if (CONFIG(VBOOT_STARTS_BEFORE_BOOTBLOCK) && __CBMEM_CONSOLE_ENABLE__)
 		replay_transfer_buffer_cbmemc();
+
+	if (CONFIG(SPI_FLASH_SMM))
+		fch_spi_backup_registers();
+}
+
+void smm_soc_exit(void)
+{
+	if (CONFIG(SPI_FLASH_SMM))
+		fch_spi_restore_registers();
 }
diff --git a/src/soc/amd/common/block/include/amdblocks/spi.h b/src/soc/amd/common/block/include/amdblocks/spi.h
index 4fefc2f536..83d09e90d7 100644
--- a/src/soc/amd/common/block/include/amdblocks/spi.h
+++ b/src/soc/amd/common/block/include/amdblocks/spi.h
@@ -129,6 +129,8 @@ void spi_write32(uint8_t reg, uint32_t val);
 uint8_t fch_spi_rom_remapping(void);
 
 void fch_spi_config_modes(void);
+void fch_spi_backup_registers(void);
+void fch_spi_restore_registers(void);
 void mainboard_spi_cfg_override(uint8_t *fast_speed, uint8_t *read_mode);
 
 /* Ensure you hold the mutex when performing SPI transactions */
diff --git a/src/soc/amd/common/block/spi/fch_spi_ctrl.c b/src/soc/amd/common/block/spi/fch_spi_ctrl.c
index ec3eef6ba3..aa07542a54 100644
--- a/src/soc/amd/common/block/spi/fch_spi_ctrl.c
+++ b/src/soc/amd/common/block/spi/fch_spi_ctrl.c
@@ -122,6 +122,31 @@ void spi_init(void)
 	printk(BIOS_DEBUG, "%s: SPI BAR at 0x%08lx\n", __func__, spi_get_bar());
 }
 
+static uint8_t cmd_code;
+static uint8_t tx_byte_count;
+static uint8_t rx_byte_count;
+static uint8_t fifo[SPI_FIFO_DEPTH];
+
+void fch_spi_backup_registers(void)
+{
+	cmd_code = spi_read8(SPI_CMD_CODE);
+	tx_byte_count = spi_read8(SPI_TX_BYTE_COUNT);
+	rx_byte_count = spi_read8(SPI_RX_BYTE_COUNT);
+
+	for (int count = 0; count < SPI_FIFO_DEPTH; count++)
+		fifo[count] = spi_read8(SPI_FIFO + count);
+}
+
+void fch_spi_restore_registers(void)
+{
+	spi_write8(SPI_CMD_CODE, cmd_code);
+	spi_write8(SPI_TX_BYTE_COUNT, tx_byte_count);
+	spi_write8(SPI_RX_BYTE_COUNT, rx_byte_count);
+
+	for (int count = 0; count < SPI_FIFO_DEPTH; count++)
+		spi_write8(SPI_FIFO + count, fifo[count]);
+}
+
 static int spi_ctrlr_xfer(const struct spi_slave *slave, const void *dout,
 			size_t bytesout, void *din, size_t bytesin)
 {
diff --git a/src/soc/amd/genoa_poc/smihandler.c b/src/soc/amd/genoa_poc/smihandler.c
index 1eb051317b..08ac70b096 100644
--- a/src/soc/amd/genoa_poc/smihandler.c
+++ b/src/soc/amd/genoa_poc/smihandler.c
@@ -6,6 +6,7 @@
 #include <amdblocks/psp.h>
 #include <amdblocks/smi.h>
 #include <amdblocks/smm.h>
+#include <amdblocks/spi.h>
 #include <arch/hlt.h>
 #include <arch/io.h>
 #include <console/console.h>
@@ -94,3 +95,15 @@ void *get_smi_source_handler(int source)
 
 	return NULL;
 }
+
+void smm_soc_early_init(void)
+{
+	if (CONFIG(SPI_FLASH_SMM))
+		fch_spi_backup_registers();
+}
+
+void smm_soc_exit(void)
+{
+	if (CONFIG(SPI_FLASH_SMM))
+		fch_spi_restore_registers();
+}
diff --git a/src/soc/amd/glinda/smihandler.c b/src/soc/amd/glinda/smihandler.c
index 8591de766c..ffe94b75ac 100644
--- a/src/soc/amd/glinda/smihandler.c
+++ b/src/soc/amd/glinda/smihandler.c
@@ -8,6 +8,7 @@
 #include <amdblocks/psp.h>
 #include <amdblocks/smi.h>
 #include <amdblocks/smm.h>
+#include <amdblocks/spi.h>
 #include <arch/hlt.h>
 #include <arch/io.h>
 #include <console/console.h>
@@ -125,3 +126,15 @@ void *get_smi_source_handler(int source)
 
 	return NULL;
 }
+
+void smm_soc_early_init(void)
+{
+	if (CONFIG(SPI_FLASH_SMM))
+		fch_spi_backup_registers();
+}
+
+void smm_soc_exit(void)
+{
+	if (CONFIG(SPI_FLASH_SMM))
+		fch_spi_restore_registers();
+}
diff --git a/src/soc/amd/mendocino/smihandler.c b/src/soc/amd/mendocino/smihandler.c
index 12b958cd29..85a345912e 100644
--- a/src/soc/amd/mendocino/smihandler.c
+++ b/src/soc/amd/mendocino/smihandler.c
@@ -8,6 +8,7 @@
 #include <amdblocks/psp.h>
 #include <amdblocks/smi.h>
 #include <amdblocks/smm.h>
+#include <amdblocks/spi.h>
 #include <arch/hlt.h>
 #include <arch/io.h>
 #include <console/console.h>
@@ -125,3 +126,15 @@ void *get_smi_source_handler(int source)
 
 	return NULL;
 }
+
+void smm_soc_early_init(void)
+{
+	if (CONFIG(SPI_FLASH_SMM))
+		fch_spi_backup_registers();
+}
+
+void smm_soc_exit(void)
+{
+	if (CONFIG(SPI_FLASH_SMM))
+		fch_spi_restore_registers();
+}
diff --git a/src/soc/amd/phoenix/smihandler.c b/src/soc/amd/phoenix/smihandler.c
index 454dadd719..b28f015e8e 100644
--- a/src/soc/amd/phoenix/smihandler.c
+++ b/src/soc/amd/phoenix/smihandler.c
@@ -8,6 +8,7 @@
 #include <amdblocks/psp.h>
 #include <amdblocks/smi.h>
 #include <amdblocks/smm.h>
+#include <amdblocks/spi.h>
 #include <arch/hlt.h>
 #include <arch/io.h>
 #include <console/console.h>
@@ -125,3 +126,15 @@ void *get_smi_source_handler(int source)
 
 	return NULL;
 }
+
+void smm_soc_early_init(void)
+{
+	if (CONFIG(SPI_FLASH_SMM))
+		fch_spi_backup_registers();
+}
+
+void smm_soc_exit(void)
+{
+	if (CONFIG(SPI_FLASH_SMM))
+		fch_spi_restore_registers();
+}
diff --git a/src/soc/amd/picasso/smihandler.c b/src/soc/amd/picasso/smihandler.c
index 507068edaf..b983ad11bf 100644
--- a/src/soc/amd/picasso/smihandler.c
+++ b/src/soc/amd/picasso/smihandler.c
@@ -6,6 +6,7 @@
 #include <amdblocks/psp.h>
 #include <amdblocks/smi.h>
 #include <amdblocks/smm.h>
+#include <amdblocks/spi.h>
 #include <arch/hlt.h>
 #include <arch/io.h>
 #include <console/console.h>
@@ -127,3 +128,15 @@ void *get_smi_source_handler(int source)
 
 	return NULL;
 }
+
+void smm_soc_early_init(void)
+{
+	if (CONFIG(SPI_FLASH_SMM))
+		fch_spi_backup_registers();
+}
+
+void smm_soc_exit(void)
+{
+	if (CONFIG(SPI_FLASH_SMM))
+		fch_spi_restore_registers();
+}

From 8dcfa915f292b4e1546f159e32ac078b5628dbfd Mon Sep 17 00:00:00 2001
From: Patrick Rudolph <patrick.rudolph@amd.com>
Date: Tue, 15 Jul 2025 09:29:01 +0200
Subject: [PATCH 1872/3886] soc/amd/common/block/psp: Probe SPI flash early

When SOC_AMD_COMMON_BLOCK_PSP_SMI is enabled probe for the SPI
flash before actually servicing PSP SMI requests. This allows
to check the SPI flash status register in the following SMIs
if the flash is busy without needing to probe it first.

Signed-off-by: Patrick Rudolph <patrick.rudolph@amd.com>
Change-Id: Iff01d0ea46f1bd2c32dbf4c4f65f9851fdf024e1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88436
Reviewed-by: Andy Ebrahiem <ahmet.ebrahiem@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
---
 src/soc/amd/common/block/psp/psp_smm.c | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/src/soc/amd/common/block/psp/psp_smm.c b/src/soc/amd/common/block/psp/psp_smm.c
index 671942b0f8..7fade174d7 100644
--- a/src/soc/amd/common/block/psp/psp_smm.c
+++ b/src/soc/amd/common/block/psp/psp_smm.c
@@ -8,6 +8,7 @@
 #include <amdblocks/psp.h>
 #include <amdblocks/smi.h>
 #include <soc/iomap.h>
+#include <spi_flash.h>
 #include <string.h>
 
 #include "psp_def.h"
@@ -93,6 +94,9 @@ int psp_notify_smm(void)
 	if (CONFIG(SOC_AMD_COMMON_BLOCK_PSP_SMI)) {
 		configure_psp_smi();
 		enable_psp_smi();
+
+		/* Probe for SPI flash now as it's likely not busy */
+		assert(boot_device_spi_flash());
 	}
 
 	printk(BIOS_DEBUG, "PSP: Notify SMM info... ");

From 76d45a8219373cfe6219ff1ee7b9b8995a69302b Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Micha=C5=82=20=C5=BBygowski?= <michal.zygowski@3mdeb.com>
Date: Wed, 9 Jul 2025 10:40:20 +0200
Subject: [PATCH 1873/3886] soc/amd/genoa_poc/root_complex.c: Explain the order
 of IOHCs
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

At first glance the order of IOHCs seems peculiar. However, the
order is not random. Explain the reasoning of the IOHC order in the
comment.

Change-Id: Ic8e567d48a0f8d95ff9785cdd0c5489ea3016f1a
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88369
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
---
 src/soc/amd/genoa_poc/root_complex.c | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/src/soc/amd/genoa_poc/root_complex.c b/src/soc/amd/genoa_poc/root_complex.c
index 3171febe9f..868e9c5db8 100644
--- a/src/soc/amd/genoa_poc/root_complex.c
+++ b/src/soc/amd/genoa_poc/root_complex.c
@@ -4,6 +4,16 @@
 #include <amdblocks/root_complex.h>
 #include <types.h>
 
+/*
+ * The order of IOHCs here is not random. They are sorted so that:
+ * 1. The First IOHC is the one with primary FCH. We want the LPC/SMBUS
+ *    devices be on bus 0.
+ * 2. The rest of IOHCs are listed in an order so that ECAM MMIO region is one
+ *    continuous block for all domains.
+ *
+ * AGESA/OpenSIL sets up the PCI configuration decoding ranges in line with
+ * this.
+ */
 static const struct domain_iohc_info iohc_info[] = {
 	[0] = {
 		.fabric_id = 0x22,

From acb86babdf1232028af56a6dfe4622fd5e9b400a Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Micha=C5=82=20=C5=BBygowski?= <michal.zygowski@3mdeb.com>
Date: Fri, 19 Jun 2020 14:38:36 +0200
Subject: [PATCH 1874/3886] mb/protectli/vault_kbl/mainboard.c: bring back the
 beep

This commit is cherry-picked from:
https://github.com/Dasharo/coreboot.git

Branch: protectli_vault_kbl/release

Original commit hash: b2b0a2bafbbe9be640f0fd0d02d85c81c90b796b

Then it was modified after code review, to:
* make it configurable
* remove code duplication

Signed-off-by: Purdea Andrei <andrei@purdea.ro>
Change-Id: I1350df3407aaa9b1fdaf9383972fac3a708bea96
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88221
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/protectli/vault_kbl/Kconfig     |  8 ++++++++
 src/mainboard/protectli/vault_kbl/mainboard.c | 14 ++++++++++++++
 2 files changed, 22 insertions(+)
 create mode 100644 src/mainboard/protectli/vault_kbl/mainboard.c

diff --git a/src/mainboard/protectli/vault_kbl/Kconfig b/src/mainboard/protectli/vault_kbl/Kconfig
index 10f8c400b7..e905be9bdc 100644
--- a/src/mainboard/protectli/vault_kbl/Kconfig
+++ b/src/mainboard/protectli/vault_kbl/Kconfig
@@ -47,4 +47,12 @@ config CBFS_SIZE
 config USE_PM_ACPI_TIMER
 	default n
 
+config BEEP_ON_BOOT
+	bool "Beep on successful boot"
+	default y
+	help
+	  Make the platform beep using the PC speaker in final coreboot phase.
+	  May serve as a useful indicator in headless mode that platform is
+	  properly booting.
+
 endif
diff --git a/src/mainboard/protectli/vault_kbl/mainboard.c b/src/mainboard/protectli/vault_kbl/mainboard.c
new file mode 100644
index 0000000000..f99c716c80
--- /dev/null
+++ b/src/mainboard/protectli/vault_kbl/mainboard.c
@@ -0,0 +1,14 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <device/device.h>
+#include <pc80/i8254.h>
+
+static void mainboard_final(void *unused)
+{
+	if (CONFIG(BEEP_ON_BOOT))
+		beep(1500, 100);
+}
+
+struct chip_operations mainboard_ops = {
+	.final = mainboard_final,
+};

From 921027e09b60b17cfd5794187b6c57341b13896c Mon Sep 17 00:00:00 2001
From: NyeonWoo Kim <knw0507@naver.com>
Date: Sat, 5 Jul 2025 16:16:25 +0900
Subject: [PATCH 1875/3886] src/lib/cbmem_common: Delete a space(' ') in the
 source code

I found a space(' ') that was probably added unintentionally
in the cbmem_run_init_hooks().

So i deleted it to make the code cleaner.

P.S. It seems that clang-format can correct issues like it but
     clang-format is unusable currently. See util/lint/check-style.
     And this style issue of the code hasn't been corrected since 2015.
     So i decided to correct it manually for now.

Change-Id: I788047d51c1f2586c3480efc4a31848e287c5894
Signed-off-by: NyeonWoo Kim <knw0507@naver.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88325
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/lib/cbmem_common.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/lib/cbmem_common.c b/src/lib/cbmem_common.c
index bc3bfc911d..454c1d58c1 100644
--- a/src/lib/cbmem_common.c
+++ b/src/lib/cbmem_common.c
@@ -13,7 +13,7 @@ void cbmem_run_init_hooks(int is_recovery)
 	if (REGION_SIZE(cbmem_init_hooks) == 0)
 		return;
 
-	while (init_hook_ptr !=  einit_hook_ptr) {
+	while (init_hook_ptr != einit_hook_ptr) {
 		(*init_hook_ptr)(is_recovery);
 		init_hook_ptr++;
 	}

From 44ec0905516479644fd401c95ff11ba826401a77 Mon Sep 17 00:00:00 2001
From: Krystian Hebel <krystian.hebel@3mdeb.com>
Date: Tue, 16 Feb 2021 18:22:22 +0100
Subject: [PATCH 1876/3886] ppc64: Kconfig switch for bootblock in SEEPROM,
 zero HRMOR

On PPC64 each address is logically OR'ed with HRMOR (Hypervisor Real
Mode Offset Register) before it is dispatched to the underlying memory,
meaning that memory space overlaps at the least significant bit set in
HRMOR. coreboot is entered with HRMOR = 4GB-128MB both on hardware
(when started by hostboot bootloader) and in Qemu in hb-mode. This means
that memory overlaps every 128MB in this particular case. HRMOR can be
explicitly ignored when MSB of an address is set, but this would require
using different memory model for linking.

If we zero HRMOR in bootblock, linking can be done against real address.
This greatly simplifies memory layout and allows to forget about HRMOR
from that point on.

Signed-off-by: Krystian Hebel <krystian.hebel@3mdeb.com>
Signed-off-by: Maciej Pijanowski <maciej.pijanowski@3mdeb.com>
Signed-off-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com>
Change-Id: I0170463968c91b943c4b0dc15fe73fa616a164da
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67067
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/arch/ppc64/Makefile.mk                    |   9 ++
 src/arch/ppc64/bootblock_crt0.S               | 111 +++++++++++++++---
 .../emulation/qemu-power8/memlayout.ld        |  75 ++++++++++--
 .../emulation/qemu-power9/memlayout.ld        |  81 ++++++++++---
 src/mainboard/raptor-cs/talos-2/Kconfig       |  13 ++
 .../talos-2/board-bootblock-in-seeprom.fmd    |  15 +++
 src/mainboard/raptor-cs/talos-2/board.fmd     |  18 +++
 src/mainboard/raptor-cs/talos-2/memlayout.ld  |  75 ++++++++++--
 src/soc/ibm/power9/Makefile.mk                |  12 +-
 9 files changed, 352 insertions(+), 57 deletions(-)
 create mode 100644 src/mainboard/raptor-cs/talos-2/board-bootblock-in-seeprom.fmd
 create mode 100644 src/mainboard/raptor-cs/talos-2/board.fmd

diff --git a/src/arch/ppc64/Makefile.mk b/src/arch/ppc64/Makefile.mk
index 4299e7409c..4a118b638a 100644
--- a/src/arch/ppc64/Makefile.mk
+++ b/src/arch/ppc64/Makefile.mk
@@ -1,6 +1,15 @@
 ## SPDX-License-Identifier: GPL-2.0-only
 
 ppc64_flags = -I$(src)/arch/ppc64/ -mbig-endian -mcpu=power8 -mtune=power8
+ifeq ($(CONFIG_COMPILER_GCC),y)
+# disable use of %r11 for static chains on invoking nested functions through
+# pointers
+ppc64_flags += -mno-pointers-to-nested-functions
+else ifeq ($(CONFIG_COMPILER_LLVM_CLANG),y)
+# use GNU assember at least until LLVM's integrated PPC64 assember will be able
+# to handle "slbia" instruction with an argument
+ppc64_flags += -fno-integrated-as
+endif
 
 ppc64_asm_flags =
 
diff --git a/src/arch/ppc64/bootblock_crt0.S b/src/arch/ppc64/bootblock_crt0.S
index 5a9496024e..f5e269fbea 100644
--- a/src/arch/ppc64/bootblock_crt0.S
+++ b/src/arch/ppc64/bootblock_crt0.S
@@ -27,15 +27,67 @@
 	oris    r,r, (e)@h;			\
 	ori     r,r, (e)@l;
 
+/* Load an immediate 32-bit value into a register */
+#define LOAD_IMM32(r, e)			\
+	li      r, 0;				\
+	oris    r,r, (e)@h;			\
+	ori     r,r, (e)@l;
+
+/*
+ * On POWER, 0 is wherever HRMOR points to rather than physical DRAM start.
+ * HRMOR is ORed with address, not added to it, meaning that memory space
+ * overlaps after 2^(least significant set bit of HRMOR). This becomes
+ * chaotic when nonconsecutive bits are set...
+ *
+ * Two and a half possible cases:
+ * 0. bootblock started with QEMU in hb-mode
+ *    - NIA =                          0x10  (bug?)
+ *    - HRMOR =                  0x08000000  (128M)
+ *    - no physical memory to enable/train, everything accessible from start
+ * 1. bootblock loaded by HBBL
+ *    - NIA =                             0
+ *    - HRMOR =                  0xF8000000  (4G - 128M)
+ *    - initialized L3 =           0x400000  (4M)
+ *    - top address before RAM = 0xF8400000
+ * 2. bootblock in SEEPROM, loaded by SBE
+ *    - NIA =                        0x3000  (placeholder for int. vectors)
+ *    - HRMOR =                  0xF8200000  (4G - 128 M + 2 M)
+ *    - initialized L3 =             0x8000  (bootblock/HBBL size = 32K)
+ *    - no way 32K will be enough, must initialize more L3 in bootblock
+ *    - HRMOR still applies, so memory overlaps every 2M
+ *
+ * Common subset (assuming 2. initializes as much memory as possible) is
+ * 0xF8200000-0xF8400000. 2M should be more than enough for pre-RAM code,
+ * but it isn't enough to load ramstage. We could implement postcar stage,
+ * but KISS: initialize L3 from _ebootblock to 0xF8980000: up to 9.5M into
+ * cache, leaving bottom 2M (0xF8000000-0xF8200000) either uninitialized
+ * (when started from SEEPROM) or just unused for anything but bootblock
+ * (loaded by HBBL). Last 0.5M of L3 cache is left for interrupt vectors
+ * normally located at address 0.
+ *
+ * Set HRMOR to 0 before jumping to C code in bootblock and forget it even
+ * exists.
+ *
+ * For QEMU s/0xF8/0x08/ in above description but code remains the same.
+ * L3 initialization is unnecessary in this case but won't break anything.
+ *
+ * TODO: there is a structure with SBE->HBBL data at 0 in 2nd option. It
+ * holds some useful data like XSCOM BAR and LPC BAR. If, for any reason,
+ * these addresses are different than default, they should be used instead
+ * of predefined values.
+ */
+
 .section ".text._start", "ax", %progbits
 .globl _start
 _start:
 	/* QEMU with hb-mode=on starts at address 0x10, while hardware at 0x0 */
+#if !CONFIG(BOOTBLOCK_IN_SEEPROM)
 	nop
 	nop
 	nop
 	nop
 	FIXUP_ENDIAN
+#endif
 
 	/* Store FDT address provided by QEMU in %r3 to pass it later to
 	 * payload */
@@ -44,32 +96,54 @@ _start:
 	/* Set program priority to medium */
 	or	%r2, %r2, %r2
 
-	/* Stack */
-	lis	%r1, _estack@ha
-	addi	%r1, %r1, _estack@l
+	li	%r10, 1
+	rotldi	%r10, %r10, 63		/* MSB is "ignore HRMOR" */
 
-	/* Clear .bss section */
-	/* Currently not needed, .bss is zeroed in the file. If it were to be
-	 * used, make sure that .bss is 128B aligned (size of cache line),
-	 * otherwise dcbz will clear (part of) .opd section! */
-/*
-	lis	%r5, _bss@ha
-	addi	%r5, %r5, _bss@l
-	lis	%r6, _ebss@ha
-	addi	%r6, %r6, _ebss@l
+	/* Assumption: we are linked at address that isn't changed by HRMOR */
+	LOAD_IMM32(%r7, ignoreHRMOR)
+	or	%r9, %r7, %r10
+
+	mtlr %r9
+	blr
+
+ignoreHRMOR:
+	/* Now we are at 0x8000000000000000 | linked address */
+	li	%r0, 0
+	mtspr	SPR_HRMOR, %r0		/* Clear HRMOR */
+	isync
+
+	/* We can't just "b stopIgnoringHRMOR", it would use relative offset */
+	addi	%r9, %r7, stopIgnoringHRMOR - ignoreHRMOR
+	mtlr	%r9
+	blr
+
+stopIgnoringHRMOR:
+	/* Now we are at linked address */
+	slbia 7
+	sync
+	isync
+
+	/*
+	 * When coming from SBE, L3 cache is invalid except for [2M, end of HBBL]
+	 * range. Make the rest of it valid, or embrace the checkstops.
+	 */
+
+	/* Validate and initialize to zeroes [end of HBBL, 9.5M] range */
+	LOAD_IMM32(%r5, _ebootblock)	/* Assume it is at least 128B aligned */
+	LOAD_IMM32(%r6, _epreram_cbfs_cache)	/* Same */
 	addi	%r6, %r6, -1
 1:
 	dcbz	0, %r5
 	addi	%r5, %r5, 128
 	cmpld	cr7, %r5, %r6
 	blt	cr7, 1b
-*/
+
+	/* Stack */
+	LOAD_IMM32(%r1, _estack)
 
 	/* This is tested by checkstack() just before jumping to payload */
 	LOAD_IMM64(%r3, 0xDEADBEEFDEADBEEF)
-	lis	%r5, _stack@ha
-	addi	%r5, %r5, _stack@l
-	subi	%r5, %r5, 8
+	LOAD_IMM32(%r5, _stack - 8)
 	sub	%r4, %r1, %r5
 	sradi	%r4, %r4, 3		/* Divide by 8 */
 	mtctr	%r4
@@ -87,11 +161,10 @@ _start:
 	mfmsr	%r3
 	ori	%r3, %r3, 0x2000	/* FP = 1 */
 	oris	%r3, %r3, 0x0280	/* VEC = 1, VSX = 1 */
-	mtmsr	%r3
+	mtmsrd	%r3
 
 	/* Load official procedure descriptor address for main() */
-	lis	%r12, main@ha
-	addi	%r12, %r12, main@l
+	LOAD_IMM32(%r12, main)
 
 	/* Load TOC pointer and jump to main() */
 	ld	%r2, 8(%r12)
diff --git a/src/mainboard/emulation/qemu-power8/memlayout.ld b/src/mainboard/emulation/qemu-power8/memlayout.ld
index 66f2c7577b..5aca5408b1 100644
--- a/src/mainboard/emulation/qemu-power8/memlayout.ld
+++ b/src/mainboard/emulation/qemu-power8/memlayout.ld
@@ -4,15 +4,74 @@
 
 #include <arch/header.ld>
 
-// TODO: fill in these blanks for Power8.
 SECTIONS
 {
 	DRAM_START(0x0)
-	BOOTBLOCK(0x100, 64K)
-	ROMSTAGE(0x20000, 128K)
-	STACK(0x40000, 0x3ff00)
-	PRERAM_CBMEM_CONSOLE(0x80000, 8K)
-	FMAP_CACHE(0x82000, 2K)
-	CBFS_MCACHE(0x82800, 8K)
-	RAMSTAGE(0x100000, 16M)
+
+	/*
+	 * On POWER, 0 is wherever HRMOR points to rather than physical DRAM start.
+	 * HRMOR is ORed with address, not added to it, meaning that memory space
+	 * overlaps after 2^(least significant set bit of HRMOR). This becomes
+	 * chaotic when nonconsecutive bits are set...
+	 *
+	 * Two and a half possible cases:
+	 * 0. bootblock started with QEMU in hb-mode
+	 *    - NIA =                          0x10  (bug?)
+	 *    - HRMOR =                  0x08000000  (128M)
+	 *    - no physical memory to enable/train, everything accessible from start
+	 * 1. bootblock loaded by HBBL
+	 *    - NIA =                             0
+	 *    - HRMOR =                  0xF8000000  (4G - 128M)
+	 *    - initialized L3 =           0x400000  (4M)
+	 *    - top address before RAM = 0xF8400000
+	 * 2. bootblock in SEEPROM, loaded by SBE
+	 *    - NIA =                        0x3000  (placeholder for int. vectors)
+	 *    - HRMOR =                  0xF8200000  (4G - 128 M + 2 M)
+	 *    - initialized L3 =             0x8000  (bootblock/HBBL size = 32K)
+	 *    - no way 32K will be enough, must initialize more L3 in bootblock
+	 *    - HRMOR still applies, so memory overlaps every 2M
+	 *
+	 * Common subset (assuming 2. initializes as much memory as possible) is
+	 * 0xF8200000-0xF8400000. 2M should be more than enough for pre-RAM code,
+	 * but it isn't enough to load ramstage. We could implement postcar stage,
+	 * but KISS: initialize L3 from _ebootblock to 0xF8980000: up to 9.5M into
+	 * cache, leaving bottom 2M (0xF8000000-0xF8200000) either uninitialized
+	 * (when started from SEEPROM) or just unused for anything but bootblock
+	 * (loaded by HBBL). Last 0.5M of L3 cache is left for interrupt vectors
+	 * normally located at address 0.
+	 *
+	 * Set HRMOR to 0 before jumping to C code in bootblock and forget it even
+	 * exists.
+	 *
+	 * For QEMU s/0xF8/0x08/ in above description but code remains the same.
+	 * L3 initialization is unnecessary in this case but won't break anything.
+	 *
+	 * TODO: there is a structure with SBE->HBBL data at 0 in 2nd option. It
+	 * holds some useful data like XSCOM BAR and LPC BAR. If, for any reason,
+	 * these addresses are different than default, they should be used instead
+	 * of predefined values.
+	 */
+
+#if !CONFIG(BOOTBLOCK_IN_SEEPROM)
+	BOOTBLOCK(           0x08000000, 32K)
+#else
+	BOOTBLOCK(           0x08203000, 20K)
+#endif
+
+	STACK(               0x08208000, 32K)
+	PRERAM_CBMEM_CONSOLE(0x08210000, 128K)
+	FMAP_CACHE(          0x08230000, 4K)
+	CBFS_MCACHE(         0x08231000, 8K)
+	TIMESTAMP(           0x08233000, 4K)
+
+	ROMSTAGE(            0x08240000, 256K)
+
+	/*
+	 * bootblock_crt0.S assumes this is the last part of L3, leaving for
+	 * interrupt vectors at least 0.5M because of cache associativity. If
+	 * more CBFS_CACHE is needed, split this into pre-/postram caches.
+	 */
+	CBFS_CACHE(          0x08280000, 7M)
+
+	RAMSTAGE(            0x09000000, 2M)
 }
diff --git a/src/mainboard/emulation/qemu-power9/memlayout.ld b/src/mainboard/emulation/qemu-power9/memlayout.ld
index d9c2a7167a..5aca5408b1 100644
--- a/src/mainboard/emulation/qemu-power9/memlayout.ld
+++ b/src/mainboard/emulation/qemu-power9/memlayout.ld
@@ -8,27 +8,70 @@ SECTIONS
 {
 	DRAM_START(0x0)
 
-	BOOTBLOCK(0, 32K)
+	/*
+	 * On POWER, 0 is wherever HRMOR points to rather than physical DRAM start.
+	 * HRMOR is ORed with address, not added to it, meaning that memory space
+	 * overlaps after 2^(least significant set bit of HRMOR). This becomes
+	 * chaotic when nonconsecutive bits are set...
+	 *
+	 * Two and a half possible cases:
+	 * 0. bootblock started with QEMU in hb-mode
+	 *    - NIA =                          0x10  (bug?)
+	 *    - HRMOR =                  0x08000000  (128M)
+	 *    - no physical memory to enable/train, everything accessible from start
+	 * 1. bootblock loaded by HBBL
+	 *    - NIA =                             0
+	 *    - HRMOR =                  0xF8000000  (4G - 128M)
+	 *    - initialized L3 =           0x400000  (4M)
+	 *    - top address before RAM = 0xF8400000
+	 * 2. bootblock in SEEPROM, loaded by SBE
+	 *    - NIA =                        0x3000  (placeholder for int. vectors)
+	 *    - HRMOR =                  0xF8200000  (4G - 128 M + 2 M)
+	 *    - initialized L3 =             0x8000  (bootblock/HBBL size = 32K)
+	 *    - no way 32K will be enough, must initialize more L3 in bootblock
+	 *    - HRMOR still applies, so memory overlaps every 2M
+	 *
+	 * Common subset (assuming 2. initializes as much memory as possible) is
+	 * 0xF8200000-0xF8400000. 2M should be more than enough for pre-RAM code,
+	 * but it isn't enough to load ramstage. We could implement postcar stage,
+	 * but KISS: initialize L3 from _ebootblock to 0xF8980000: up to 9.5M into
+	 * cache, leaving bottom 2M (0xF8000000-0xF8200000) either uninitialized
+	 * (when started from SEEPROM) or just unused for anything but bootblock
+	 * (loaded by HBBL). Last 0.5M of L3 cache is left for interrupt vectors
+	 * normally located at address 0.
+	 *
+	 * Set HRMOR to 0 before jumping to C code in bootblock and forget it even
+	 * exists.
+	 *
+	 * For QEMU s/0xF8/0x08/ in above description but code remains the same.
+	 * L3 initialization is unnecessary in this case but won't break anything.
+	 *
+	 * TODO: there is a structure with SBE->HBBL data at 0 in 2nd option. It
+	 * holds some useful data like XSCOM BAR and LPC BAR. If, for any reason,
+	 * these addresses are different than default, they should be used instead
+	 * of predefined values.
+	 */
 
-	ROMSTAGE(0x1f00000, 1M)
-
-#if !ENV_RAMSTAGE
-	STACK(0x2000000, 32K)
+#if !CONFIG(BOOTBLOCK_IN_SEEPROM)
+	BOOTBLOCK(           0x08000000, 32K)
+#else
+	BOOTBLOCK(           0x08203000, 20K)
 #endif
 
-	FMAP_CACHE(0x2108000, 4K)
-	CBFS_MCACHE(0x2109000, 8K)
-	TIMESTAMP(0x210b000, 4K)
-	CBFS_CACHE(0x210c000, 512K)
-	PRERAM_CBMEM_CONSOLE(0x218c000, 128K)
+	STACK(               0x08208000, 32K)
+	PRERAM_CBMEM_CONSOLE(0x08210000, 128K)
+	FMAP_CACHE(          0x08230000, 4K)
+	CBFS_MCACHE(         0x08231000, 8K)
+	TIMESTAMP(           0x08233000, 4K)
 
-	/* By default all memory addresses are affected by the value of HRMOR
-	 * (Hypervisor Real Mode Offset Register) which is ORed to them. HRMOR
-	 * has initial value of 0x8000000 in QEMU and is changed to 0 in
-	 * ramstage. This means that before ramstage 0 actually points to
-	 * 0x8000000. */
-#if ENV_RAMSTAGE
-	STACK(0xa000000, 32K)
-#endif
-	RAMSTAGE(0xa008000, 2M)
+	ROMSTAGE(            0x08240000, 256K)
+
+	/*
+	 * bootblock_crt0.S assumes this is the last part of L3, leaving for
+	 * interrupt vectors at least 0.5M because of cache associativity. If
+	 * more CBFS_CACHE is needed, split this into pre-/postram caches.
+	 */
+	CBFS_CACHE(          0x08280000, 7M)
+
+	RAMSTAGE(            0x09000000, 2M)
 }
diff --git a/src/mainboard/raptor-cs/talos-2/Kconfig b/src/mainboard/raptor-cs/talos-2/Kconfig
index 46513945e0..b0fd7d3e22 100644
--- a/src/mainboard/raptor-cs/talos-2/Kconfig
+++ b/src/mainboard/raptor-cs/talos-2/Kconfig
@@ -2,6 +2,14 @@
 
 if BOARD_RAPTOR_CS_TALOS_2
 
+config BOOTBLOCK_IN_SEEPROM
+	bool "Bootblock in SEEPROM"
+	default n
+	help
+	  Enable this option if coreboot shall build image with separate
+	  bootblock (i.e. not in coreboot.rom) to be put into SEEPROM
+	  directly.
+
 config BOARD_SPECIFIC_OPTIONS
 	def_bool y
 	select CPU_POWER9
@@ -15,6 +23,11 @@ config BOARD_SPECIFIC_OPTIONS
 config MEMLAYOUT_LD_FILE
 	default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/memlayout.ld"
 
+config FMDFILE
+	string
+	default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/board-bootblock-in-seeprom.fmd"	if BOOTBLOCK_IN_SEEPROM
+	default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/board.fmd"			if !BOOTBLOCK_IN_SEEPROM
+
 config MAINBOARD_DIR
 	default "raptor-cs/talos-2"
 
diff --git a/src/mainboard/raptor-cs/talos-2/board-bootblock-in-seeprom.fmd b/src/mainboard/raptor-cs/talos-2/board-bootblock-in-seeprom.fmd
new file mode 100644
index 0000000000..8884751120
--- /dev/null
+++ b/src/mainboard/raptor-cs/talos-2/board-bootblock-in-seeprom.fmd
@@ -0,0 +1,15 @@
+# layout for firmware when flash address space matches used address layout
+# +-------------+ <-- 0
+# | unspecified |
+# +-------------+ <-- BIOS_BASE
+# | FMAP        |
+# +-------------+ <-- BIOS_BASE + 128K + FMAP_SIZE
+# | CBFS        |
+# +-------------+ <-- ROM_SIZE
+
+FLASH@0 CONFIG_ROM_SIZE {
+	BIOS@0 CONFIG_ROM_SIZE {
+		FMAP 0x200
+		COREBOOT(CBFS)
+	}
+}
diff --git a/src/mainboard/raptor-cs/talos-2/board.fmd b/src/mainboard/raptor-cs/talos-2/board.fmd
new file mode 100644
index 0000000000..462cdea751
--- /dev/null
+++ b/src/mainboard/raptor-cs/talos-2/board.fmd
@@ -0,0 +1,18 @@
+# layout for firmware when flash address space matches used address layout
+# +-------------+ <-- 0
+# | unspecified |
+# +-------------+ <-- BIOS_BASE
+# | bootblock   |
+# +-------------+ <-- BIOS_BASE + 128K
+# | FMAP        |
+# +-------------+ <-- BIOS_BASE + 128K + FMAP_SIZE
+# | CBFS        |
+# +-------------+ <-- ROM_SIZE
+
+FLASH@0 CONFIG_ROM_SIZE {
+	BIOS@0 CONFIG_ROM_SIZE {
+		BOOTBLOCK 128K
+		FMAP 0x200
+		COREBOOT(CBFS)
+	}
+}
diff --git a/src/mainboard/raptor-cs/talos-2/memlayout.ld b/src/mainboard/raptor-cs/talos-2/memlayout.ld
index c5136b9d14..c9e7c9502e 100644
--- a/src/mainboard/raptor-cs/talos-2/memlayout.ld
+++ b/src/mainboard/raptor-cs/talos-2/memlayout.ld
@@ -4,15 +4,74 @@
 
 #include <arch/header.ld>
 
-// TODO: fill in these blanks for Power9.
 SECTIONS
 {
 	DRAM_START(0x0)
-	BOOTBLOCK(0, 64K)
-	ROMSTAGE(0x120000, 128K)
-	STACK(0x140000, 0x3ff00)
-	PRERAM_CBMEM_CONSOLE(0x180000, 8K)
-	FMAP_CACHE(0x182000, 2K)
-	CBFS_MCACHE(0x182800, 8K)
-	RAMSTAGE(0x200000, 16M)
+
+	/*
+	 * On POWER, 0 is wherever HRMOR points to rather than physical DRAM start.
+	 * HRMOR is ORed with address, not added to it, meaning that memory space
+	 * overlaps after 2^(least significant set bit of HRMOR). This becomes
+	 * chaotic when nonconsecutive bits are set...
+	 *
+	 * Two and a half possible cases:
+	 * 0. bootblock started with QEMU in hb-mode
+	 *    - NIA =                          0x10  (bug?)
+	 *    - HRMOR =                  0x08000000  (128M)
+	 *    - no physical memory to enable/train, everything accessible from start
+	 * 1. bootblock loaded by HBBL
+	 *    - NIA =                             0
+	 *    - HRMOR =                  0xF8000000  (4G - 128M)
+	 *    - initialized L3 =           0x400000  (4M)
+	 *    - top address before RAM = 0xF8400000
+	 * 2. bootblock in SEEPROM, loaded by SBE
+	 *    - NIA =                        0x3000  (placeholder for int. vectors)
+	 *    - HRMOR =                  0xF8200000  (4G - 128 M + 2 M)
+	 *    - initialized L3 =             0x8000  (bootblock/HBBL size = 32K)
+	 *    - no way 32K will be enough, must initialize more L3 in bootblock
+	 *    - HRMOR still applies, so memory overlaps every 2M
+	 *
+	 * Common subset (assuming 2. initializes as much memory as possible) is
+	 * 0xF8200000-0xF8400000. 2M should be more than enough for pre-RAM code,
+	 * but it isn't enough to load ramstage. We could implement postcar stage,
+	 * but KISS: initialize L3 from _ebootblock to 0xF8980000: up to 9.5M into
+	 * cache, leaving bottom 2M (0xF8000000-0xF8200000) either uninitialized
+	 * (when started from SEEPROM) or just unused for anything but bootblock
+	 * (loaded by HBBL). Last 0.5M of L3 cache is left for interrupt vectors
+	 * normally located at address 0.
+	 *
+	 * Set HRMOR to 0 before jumping to C code in bootblock and forget it even
+	 * exists.
+	 *
+	 * For QEMU s/0xF8/0x08/ in above description but code remains the same.
+	 * L3 initialization is unnecessary in this case but won't break anything.
+	 *
+	 * TODO: there is a structure with SBE->HBBL data at 0 in 2nd option. It
+	 * holds some useful data like XSCOM BAR and LPC BAR. If, for any reason,
+	 * these addresses are different than default, they should be used instead
+	 * of predefined values.
+	 */
+
+#if !CONFIG(BOOTBLOCK_IN_SEEPROM)
+	BOOTBLOCK(           0xF8000000, 32K)
+#else
+	BOOTBLOCK(           0xF8203000, 20K)
+#endif
+
+	STACK(               0xF8208000, 32K)
+	PRERAM_CBMEM_CONSOLE(0xF8210000, 128K)
+	FMAP_CACHE(          0xF8230000, 4K)
+	CBFS_MCACHE(         0xF8231000, 8K)
+	TIMESTAMP(           0xF8233000, 4K)
+
+	ROMSTAGE(            0xF8240000, 256K)
+
+	/*
+	 * bootblock_crt0.S assumes this is the last part of L3, leaving for
+	 * interrupt vectors at least 0.5M because of cache associativity. If
+	 * more CBFS_CACHE is needed, split this into pre-/postram caches.
+	 */
+	CBFS_CACHE(          0xF8280000, 7M)
+
+	RAMSTAGE(            0xF9000000, 2M)
 }
diff --git a/src/soc/ibm/power9/Makefile.mk b/src/soc/ibm/power9/Makefile.mk
index b2aa581afa..9a3961d87d 100644
--- a/src/soc/ibm/power9/Makefile.mk
+++ b/src/soc/ibm/power9/Makefile.mk
@@ -30,18 +30,24 @@ endif
 	[ -e "$(KEYDIR)/hw_key_b.key" ] || ( echo "error: $(KEYDIR)/hw_key_b.key" is missing; exit 1 )
 	[ -e "$(KEYDIR)/hw_key_c.key" ] || ( echo "error: $(KEYDIR)/hw_key_c.key" is missing; exit 1 )
 	[ -e "$(KEYDIR)/sw_key_p.key" ] || ( echo "error: $(KEYDIR)/sw_key_p.key" is missing; exit 1 )
-	$(CREATE_CONTAINER) -a $(KEYDIR)/hw_key_a.key -b $(KEYDIR)/hw_key_b.key -c $(KEYDIR)/hw_key_c.key \
-	                    -p $(KEYDIR)/sw_key_p.key --payload $(objcbfs)/bootblock.bin \
-	                    --imagefile $(obj)/bootblock.signed
 	$(CREATE_CONTAINER) -a $(KEYDIR)/hw_key_a.key -b $(KEYDIR)/hw_key_b.key -c $(KEYDIR)/hw_key_c.key \
 	                    -p $(KEYDIR)/sw_key_p.key --payload $< --imagefile $<.signed
 	@printf "    ECC     $(subst $(obj)/,,$<)\n"
 	$(ECCTOOL) --inject $<.signed --output $<.signed.ecc --p8
+ifeq ($(CONFIG_BOOTBLOCK_IN_SEEPROM),y)
+	@printf "    ECC     bootblock\n"
+	$(ECCTOOL) --inject $(objcbfs)/bootblock.bin --output $(obj)/bootblock.ecc --p8
+else
+	@printf "    SBSIGN  bootblock\n"
+	$(CREATE_CONTAINER) -a $(KEYDIR)/hw_key_a.key -b $(KEYDIR)/hw_key_b.key -c $(KEYDIR)/hw_key_c.key \
+	                    -p $(KEYDIR)/sw_key_p.key --payload $(objcbfs)/bootblock.bin \
+	                    --imagefile $(obj)/bootblock.signed
 	$(ECCTOOL) --inject $< --output $<.ecc --p8
 	@printf "    ECC     bootblock\n"
 	dd if=$(obj)/bootblock.signed of=$(obj)/bootblock.signed.pad ibs=25486 conv=sync 2> /dev/null
 	$(ECCTOOL) --inject $(obj)/bootblock.signed.pad --output $(obj)/bootblock.signed.ecc --p8
 	rm $(obj)/bootblock.signed $(obj)/bootblock.signed.pad
+endif # CONFIG_BOOTBLOCK_IN_SEEPROM
 
 files_added:: sign_and_add_ecc
 

From 8f2633cd60b9c11f4b09fba177b4e88728451c2a Mon Sep 17 00:00:00 2001
From: Krystian Hebel <krystian.hebel@3mdeb.com>
Date: Fri, 9 Oct 2020 19:13:03 +0200
Subject: [PATCH 1877/3886] soc/power9/rom_media.c: find CBFS in PNOR

Tested on QEMU with ECC. Use mmap_helper to handle loading of compressed
ramstage. Bootblock fits in SEEPROM with both console and LZ4
romstage compression, but not with verbose CBFS debug messages.

Signed-off-by: Krystian Hebel <krystian.hebel@3mdeb.com>
Change-Id: I91c72c52849eb1e3fafe43390351537d04382e46
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67069
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
---
 src/arch/ppc64/include/arch/io.h |   2 +
 src/soc/ibm/power9/rom_media.c   | 440 ++++++++++++++++++++++++++++++-
 2 files changed, 441 insertions(+), 1 deletion(-)

diff --git a/src/arch/ppc64/include/arch/io.h b/src/arch/ppc64/include/arch/io.h
index cfaae33f60..bc122f1201 100644
--- a/src/arch/ppc64/include/arch/io.h
+++ b/src/arch/ppc64/include/arch/io.h
@@ -8,7 +8,9 @@
 /* Set MSB to 1 to ignore HRMOR */
 #define MMIO_GROUP0_CHIP0_LPC_BASE_ADDR 0x8006030000000000
 #define LPCHC_IO_SPACE 0xD0010000
+#define LPCHC_FW_SPACE 0xF0000000
 #define FLASH_IO_SPACE 0xFC000000
+#define FW_SPACE_SIZE  0x10000000
 #define LPC_BASE_ADDR (MMIO_GROUP0_CHIP0_LPC_BASE_ADDR + LPCHC_IO_SPACE)
 #define FLASH_BASE_ADDR (MMIO_GROUP0_CHIP0_LPC_BASE_ADDR + FLASH_IO_SPACE)
 #define MMIO_GROUP0_CHIP0_SCOM_BASE_ADDR 0x800603FC00000000
diff --git a/src/soc/ibm/power9/rom_media.c b/src/soc/ibm/power9/rom_media.c
index c07af1bbf0..df82484db1 100644
--- a/src/soc/ibm/power9/rom_media.c
+++ b/src/soc/ibm/power9/rom_media.c
@@ -1,8 +1,446 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
+#include <string.h>
 #include <boot_device.h>
+#include <arch/io.h>
+#include <console/console.h>
+#include <endian.h>
+#include <cbfs.h>
+#include <symbols.h>
+#include "../../../../3rdparty/ffs/ffs/ffs.h"
+
+#define LPC_FLASH_MIN (MMIO_GROUP0_CHIP0_LPC_BASE_ADDR + LPCHC_FW_SPACE)
+#define LPC_FLASH_TOP (LPC_FLASH_MIN + FW_SPACE_SIZE)
+
+#define CBFS_PARTITION_NAME "HBI"
+
+/* ffs_entry is not complete in included ffs.h, it lacks user data layout.
+ * See https://github.com/open-power/skiboot/blob/master/libflash/ffs.h */
+
+/* Data integrity flags */
+#define FFS_ENRY_INTEG_ECC 0x8000
+
+/* Version Checking : 1 byte */
+#define FFS_VERS_SHA512 0x80
+
+enum ecc_status {
+	CLEAN = 0,          //< No ECC Error was detected.
+	CORRECTED = 1,      //< ECC error detected and corrected.
+	UNCORRECTABLE = 2   //< ECC error detected and uncorrectable.
+};
+typedef enum  ecc_status ecc_status_t;
+
+enum ecc_bitfields {
+	GD = 0xff,      //< Good, ECC matches.
+	UE = 0xfe,      //< Uncorrectable.
+	E0 = 71,        //< Error in ECC bit 0
+	E1 = 70,        //< Error in ECC bit 1
+	E2 = 69,        //< Error in ECC bit 2
+	E3 = 68,        //< Error in ECC bit 3
+	E4 = 67,        //< Error in ECC bit 4
+	E5 = 66,        //< Error in ECC bit 5
+	E6 = 65,        //< Error in ECC bit 6
+	E7 = 64         //< Error in ECC bit 7
+};
+
+/*
+static uint64_t ecc_matrix[] = {
+	//0000000000000000111010000100001000111100000011111001100111111111
+	0x0000e8423c0f99ff,
+	//0000000011101000010000100011110000001111100110011111111100000000
+	0x00e8423c0f99ff00,
+	//1110100001000010001111000000111110011001111111110000000000000000
+	0xe8423c0f99ff0000,
+	//0100001000111100000011111001100111111111000000000000000011101000
+	0x423c0f99ff0000e8,
+	//0011110000001111100110011111111100000000000000001110100001000010
+	0x3c0f99ff0000e842,
+	//0000111110011001111111110000000000000000111010000100001000111100
+	0x0f99ff0000e8423c,
+	//1001100111111111000000000000000011101000010000100011110000001111
+	0x99ff0000e8423c0f,
+	//1111111100000000000000001110100001000010001111000000111110011001
+	0xff0000e8423c0f99
+};
+*/
+
+/*
+ * Compressed version of table above, saves 48 bytes. Rotating value in register
+ * results in exactly the same size as full table, due to cost of loading values
+ * into registers.
+ */
+static uint8_t ecc_matrix[] = {
+	0x00, 0x00, 0xe8, 0x42, 0x3c, 0x0f, 0x99, 0xff,
+	0x00, 0x00, 0xe8, 0x42, 0x3c, 0x0f, 0x99
+};
+
+static uint8_t syndrome_matrix[] = {
+	GD, E7, E6, UE, E5, UE, UE, 47, E4, UE, UE, 37, UE, 35, 39, UE,
+	E3, UE, UE, 48, UE, 30, 29, UE, UE, 57, 27, UE, 31, UE, UE, UE,
+	E2, UE, UE, 17, UE, 18, 40, UE, UE, 58, 22, UE, 21, UE, UE, UE,
+	UE, 16, 49, UE, 19, UE, UE, UE, 23, UE, UE, UE, UE, 20, UE, UE,
+	E1, UE, UE, 51, UE, 46,  9, UE, UE, 34, 10, UE, 32, UE, UE, 36,
+	UE, 62, 50, UE, 14, UE, UE, UE, 13, UE, UE, UE, UE, UE, UE, UE,
+	UE, 61,  8, UE, 41, UE, UE, UE, 11, UE, UE, UE, UE, UE, UE, UE,
+	15, UE, UE, UE, UE, UE, UE, UE, UE, UE, 12, UE, UE, UE, UE, UE,
+	E0, UE, UE, 55, UE, 45, 43, UE, UE, 56, 38, UE,  1, UE, UE, UE,
+	UE, 25, 26, UE,  2, UE, UE, UE, 24, UE, UE, UE, UE, UE, 28, UE,
+	UE, 59, 54, UE, 42, UE, UE, 44,  6, UE, UE, UE, UE, UE, UE, UE,
+	 5, UE, UE, UE, UE, UE, UE, UE, UE, UE, UE, UE, UE, UE, UE, UE,
+	UE, 63, 53, UE,  0, UE, UE, UE, 33, UE, UE, UE, UE, UE, UE, UE,
+	 3, UE, UE, 52, UE, UE, UE, UE, UE, UE, UE, UE, UE, UE, UE, UE,
+	 7, UE, UE, UE, UE, UE, UE, UE, UE, 60, UE, UE, UE, UE, UE, UE,
+	UE, UE, UE, UE,  4, UE, UE, UE, UE, UE, UE, UE, UE, UE, UE, UE,
+};
+
+static inline uint32_t rd32(void *addr)
+{
+	uint64_t ret;
+
+	/* Cache-inhibited load word */
+	asm volatile("lwzcix %0, 0, %1"
+				 : "=r" (ret)
+				 : "r" (addr)
+				 : );
+
+	return ret;
+}
+
+static uint64_t rd64_unaligned(void *addr, int first_read)
+{
+	static uint64_t tmp1;	/* static is used to reduce number of PNOR reads */
+	uint64_t tmp2;
+	uint64_t ret;
+	uint64_t addr_aligned = ALIGN_DOWN((uint64_t)addr, 8);
+	unsigned int shift = 8 * ((uint64_t) addr - addr_aligned);
+
+	if (shift == 0			/* Previous tmp2 ended with ECC byte */
+	    || first_read) {	/* or it is the first invocation from remove_ecc */
+		asm volatile("ldcix %0, 0, %1"
+					 : "=r" (tmp1)
+					 : "r" (addr_aligned)
+					 : );
+	}
+
+	asm volatile("ldcix %0, 0, %1"
+				 : "=r" (tmp2)
+				 : "r" (addr_aligned+8)
+				 : );
+
+	ret = (tmp1 << shift) | (tmp2 >> (64 - shift));
+	tmp1 = tmp2;
+
+	return ret;
+}
+
+/*
+ * memcpy from cache-inhibited source
+ *
+ * Assume src is 8B-aligned and does not overlap with dest. Copies ALIGN(n,8)
+ * bytes, make sure dest is big enough.
+ */
+static inline void memcpy_ci_src(void *dest, const void *src, size_t n)
+{
+	int i;
+	uint64_t tmp;
+	for (i = 0; i < n; i += 8) {
+		asm volatile("ldcix %0, %1, %2"
+					 : "=r" (tmp)
+					 : "b"(src), "r" (i));
+		asm volatile("stdx %0, %1, %2"
+					 :: "r" (tmp), "b"(dest), "r" (i)
+					 : "memory");
+	}
+}
+
+static uint8_t generate_ecc(uint64_t i_data)
+{
+	uint8_t result = 0;
+
+	for (int i = 0; i < 8; i++)
+		result |= __builtin_parityll((*(uint64_t *)&ecc_matrix[i]) & i_data) << i;
+	return result;
+}
+
+static uint8_t verify_ecc(uint64_t i_data, uint8_t i_ecc)
+{
+	return syndrome_matrix[generate_ecc(i_data) ^ i_ecc];
+}
+
+static uint8_t correct_ecc(uint64_t *io_data, uint8_t *io_ecc)
+{
+	uint8_t bad_bit = verify_ecc(*io_data, *io_ecc);
+
+	if ((bad_bit != GD) && (bad_bit != UE)) { /* Good is done, UE is hopeless */
+		/* Determine if the ECC or data part is bad, do bit flip. */
+		if (bad_bit >= E7)
+			*io_ecc ^= (1 << (bad_bit - E7));
+		else
+			*io_data ^= (1ull << (63 - bad_bit));
+	}
+	return bad_bit;
+}
+
+static ecc_status_t remove_ecc(uint8_t *io_src, size_t i_srcSz,
+			       uint8_t *o_dst, size_t i_dstSz)
+{
+	ecc_status_t rc = CLEAN;
+	int first_read = 1;
+
+	for (size_t i = 0, o = 0; i < i_srcSz;
+	     i += sizeof(uint64_t) + sizeof(uint8_t), o += sizeof(uint64_t)) {
+		/*
+		 * Read data and ECC parts. Reads from cache-inhibited storage always
+		 * have to be aligned!
+		 */
+		uint64_t data = rd64_unaligned(&io_src[i], first_read);
+		first_read = 0;
+
+		uint8_t ecc = io_src[i + sizeof(uint64_t)];
+
+		/* Calculate failing bit and fix data */
+		uint8_t bad_bit = correct_ecc(&data, &ecc);
+
+		/* Perform correction and status update */
+		if (bad_bit == UE)
+			rc = UNCORRECTABLE;
+		/* Unused, our source is not writable */
+		/*
+		else if (bad_bit != GD)
+		{
+			if (rc != UNCORRECTABLE)
+			{
+				rc = CORRECTED;
+			}
+
+			*(uint64_t*)(&io_src[i]) = data;
+			io_src[i + sizeof(uint64_t)] = ecc;
+		}
+		*/
+
+		/* Copy fixed data to destination buffer */
+		*(uint64_t *)(&o_dst[o]) = data;
+	}
+	return rc;
+}
+
+static char *pnor_base;
+
+/*
+ * PNOR has to be accessed with Cache Inhibited forms of instructions, and they
+ * require that the address is aligned, so we can just memcpy the data.
+ */
+static ssize_t no_ecc_readat(const struct region_device *rd, void *b,
+			     size_t offset, size_t size)
+{
+	uint8_t tmp[8];
+	offset -= rd->region.offset;
+	size_t off_a = ALIGN_DOWN(offset, 8);
+	size_t size_left = size;
+	char *part_base = pnor_base + rd->region.offset;
+
+	/* If offset is not 8B-aligned */
+	if (offset & 0x7) {
+		int i;
+		memcpy_ci_src(tmp, &part_base[off_a], 8);
+		for (i = 8 - (offset & 7); i < 8; i++) {
+			*((uint8_t *)(b++)) = tmp[i];
+			if (!--size_left)
+				return size;
+		}
+		off_a += 8;
+	}
+
+	/* Align down size_left to 8B */
+	memcpy_ci_src(b, &part_base[off_a], ALIGN_DOWN(size_left, 8));
+
+	/* Copy the rest of requested unaligned data, if any */
+	if (size_left & 7) {
+		off_a += ALIGN_DOWN(size_left, 8);
+		b += ALIGN_DOWN(size_left, 8);
+		int i;
+		memcpy_ci_src(tmp, &part_base[off_a], 8);
+		for (i = 0; i < (size_left & 7); i++)
+			*((uint8_t *)(b++)) = tmp[i];
+	}
+
+	return size;
+}
+
+static ssize_t ecc_readat(const struct region_device *rd, void *b,
+				size_t offset, size_t size)
+{
+	uint8_t tmp[8];
+	offset -= rd->region.offset;
+	size_t off_a = ALIGN_DOWN(offset, 8);
+	size_t size_left = size;
+	char *part_base = pnor_base + rd->region.offset;
+
+	/* If offset is not 8B-aligned */
+	if (offset & 0x7) {
+		int i;
+		remove_ecc((uint8_t *) &part_base[(off_a * 9)/8], 9, tmp, 8);
+		for (i = 8 - (offset & 7); i < 8; i++) {
+			*((uint8_t *)(b++)) = tmp[i];
+			if (!--size_left)
+				return size;
+		}
+		off_a += 8;
+	}
+
+	/* Align down size_left to 8B */
+	remove_ecc((uint8_t *) &part_base[(off_a * 9)/8],
+		   (ALIGN_DOWN(size_left, 8) * 9) / 8,
+		   b,
+		   ALIGN_DOWN(size_left, 8));
+
+	/* Copy the rest of requested unaligned data, if any */
+	if (size_left & 7) {
+		off_a += ALIGN_DOWN(size_left, 8);
+		b += ALIGN_DOWN(size_left, 8);
+		int i;
+		remove_ecc((uint8_t *) &part_base[(off_a * 9)/8], 9, tmp, 8);
+		for (i = 0; i < (size_left & 7); i++)
+			*((uint8_t *)(b++)) = tmp[i];
+	}
+
+	return size;
+}
+
+static struct region_device_ops no_ecc_rdev_ops = {
+	.mmap = mmap_helper_rdev_mmap,
+	.munmap = mmap_helper_rdev_munmap,
+	.readat = no_ecc_readat,
+};
+
+static struct region_device_ops ecc_rdev_ops = {
+	.mmap = mmap_helper_rdev_mmap,
+	.munmap = mmap_helper_rdev_munmap,
+	.readat = ecc_readat,
+};
+
+static void mount_part_from_pnor(const char *part_name,
+				 struct mmap_helper_region_device *mdev)
+{
+	size_t base, size;
+	unsigned int i, block_size, entry_count = 0;
+	struct ffs_hdr *hdr_pnor = (struct ffs_hdr *)LPC_FLASH_TOP;
+
+	/* This loop could be skipped if we may assume that PNOR is always 64M */
+	while (hdr_pnor > (struct ffs_hdr *)LPC_FLASH_MIN) {
+		uint32_t csum = 0;
+		/* Size is aligned up to 8 because of how memcpy_ci_src works */
+		uint8_t buffer[ALIGN(FFS_HDR_SIZE, 8)];
+		struct ffs_hdr *hdr = (struct ffs_hdr *)buffer;
+
+		/* Assume block_size = 4K */
+		hdr_pnor = (struct ffs_hdr *)(((char *)hdr_pnor) - 0x1000);
+
+		if (rd32(&hdr_pnor->magic) != FFS_MAGIC)
+			continue;
+
+		if (rd32(&hdr_pnor->version) != FFS_VERSION_1)
+			continue;
+
+		/* Copy the header so we won't have to rd32() for further accesses */
+		memcpy_ci_src(buffer, hdr_pnor, FFS_HDR_SIZE);
+		csum = hdr->magic ^ hdr->version ^ hdr->size ^ hdr->entry_size ^
+		       hdr->entry_count ^ hdr->block_size ^ hdr->block_count ^
+		       hdr->resvd[0] ^ hdr->resvd[1] ^ hdr->resvd[2] ^ hdr->resvd[3] ^
+		       hdr->checksum;
+		if (csum != 0)
+			continue;
+
+		pnor_base = (char *) LPC_FLASH_TOP - hdr->block_size * hdr->block_count;
+		entry_count = hdr->entry_count;
+		block_size = hdr->block_size;
+
+		/* Every byte counts when building for SEEPROM */
+		if (!CONFIG(BOOTBLOCK_IN_SEEPROM)) {
+			printk(BIOS_DEBUG, "FFS header at %p\n", hdr_pnor);
+			printk(BIOS_SPEW, "    size %x\n", hdr->size);
+			printk(BIOS_SPEW, "    entry_size %x\n", hdr->entry_size);
+			printk(BIOS_SPEW, "    entry_count %x\n", hdr->entry_count);
+			printk(BIOS_SPEW, "    block_size %x\n", hdr->block_size);
+			printk(BIOS_SPEW, "    block_count %x\n", hdr->block_count);
+			printk(BIOS_DEBUG, "PNOR base at %p\n", pnor_base);
+		}
+
+		break;
+	}
+
+	if (hdr_pnor <= (struct ffs_hdr *)LPC_FLASH_MIN)
+		die("FFS header not found!\n");
+
+	for (i = 0; i < entry_count; i++) {
+		uint32_t *val, csum = 0;
+		int j;
+		/* Size is aligned up to 8 because of how memcpy_ci_src works */
+		uint8_t buffer[ALIGN(FFS_ENTRY_SIZE, 8)];
+		struct ffs_entry *e = (struct ffs_entry *)buffer;
+
+		/* Copy the entry so we won't have to rd32() for further accesses */
+		memcpy_ci_src(buffer, &hdr_pnor->entries[i], FFS_ENTRY_SIZE);
+
+		/* Every byte counts when building for SEEPROM */
+		if (!CONFIG(BOOTBLOCK_IN_SEEPROM)) {
+			printk(BIOS_SPEW, "%s: base %x, size %x  (%x)\n\t type %x, flags %x\n",
+			       e->name, e->base, e->size, e->actual, e->type, e->flags);
+		}
+
+		if (strcmp(e->name, part_name) != 0)
+			continue;
+
+		val = (uint32_t *) e;
+		for (j = 0; j < (FFS_ENTRY_SIZE / sizeof(uint32_t)); j++)
+			csum ^= val[j];
+
+		if (csum != 0)
+			continue;
+
+		base = block_size * e->base;
+		/* This is size of the partition, it does not include header or ECC */
+		size = e->actual;
+
+		mdev->rdev.ops = &no_ecc_rdev_ops;
+
+		if (e->user.data[0] & FFS_ENRY_INTEG_ECC) {
+			printk(BIOS_DEBUG, "%s partition has ECC\n", part_name);
+			mdev->rdev.ops = &ecc_rdev_ops;
+			size = size / 9 * 8;
+		}
+
+		if ((e->user.data[1] >> 24) & FFS_VERS_SHA512) {
+			/* Skip PNOR partition header */
+			base += 0x1000;
+
+			/* Possibly skip ECC of the header */
+			if (e->user.data[0] & FFS_ENRY_INTEG_ECC)
+				base += 0x200;
+		}
+
+		mdev->rdev.region.offset = base;
+		mdev->rdev.region.size = size;
+
+		break;
+	}
+}
+
+static struct mmap_helper_region_device boot_mdev = MMAP_HELPER_DEV_INIT(
+	&no_ecc_rdev_ops, 0, CONFIG_ROM_SIZE, &cbfs_cache);
+
+void boot_device_init(void)
+{
+	static int init_done;
+	if (init_done)
+		return;
+
+	mount_part_from_pnor(CBFS_PARTITION_NAME, &boot_mdev);
+
+	init_done = 1;
+}
 
 const struct region_device *boot_device_ro(void)
 {
-	return NULL;
+	return &boot_mdev.rdev;
 }

From 152b58416754a5460459e4c5a41e202d4301097a Mon Sep 17 00:00:00 2001
From: Nick Vaccaro <nvaccaro@google.com>
Date: Tue, 19 Aug 2025 19:29:10 -0700
Subject: [PATCH 1878/3886] mb/goog/ocelot/var/ocelot: Add
 AUDIO_MAX98360_ALC5682I_I2S

Add new FW_CONFIG option AUDIO_MAX98360_ALC5682I_I2S.

BUG=b:438738151
TEST=`emerge-ocelot coreboot` and verify it builds without error.

Change-Id: Icc35dea9e9334fb3ed980bc92e311a42bb7006ac
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88866
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
---
 .../google/ocelot/variants/ocelot/fw_config.c | 37 ++++++++++
 .../ocelot/variants/ocelot/overridetree.cb    | 69 ++++++++++---------
 2 files changed, 72 insertions(+), 34 deletions(-)

diff --git a/src/mainboard/google/ocelot/variants/ocelot/fw_config.c b/src/mainboard/google/ocelot/variants/ocelot/fw_config.c
index 1e7756769c..5e9559803b 100644
--- a/src/mainboard/google/ocelot/variants/ocelot/fw_config.c
+++ b/src/mainboard/google/ocelot/variants/ocelot/fw_config.c
@@ -11,6 +11,40 @@
 /* t: table */
 #define GPIO_CONFIGURE_PADS(t) gpio_configure_pads(t, ARRAY_SIZE(t))
 
+static const struct pad_config i2s_enable_pads[] = {
+	/* I2S_MCLK1_OUT */
+	PAD_CFG_NF(GPP_D09, NONE, DEEP, NF2),
+	/* I2S0_SCLK_HDR */
+	PAD_CFG_NF(GPP_D10, NONE, DEEP, NF1),
+	/* I2S0_SFRM_HDR */
+	PAD_CFG_NF(GPP_D11, NONE, DEEP, NF1),
+	/* I2S0_TXD_HDR */
+	PAD_CFG_NF(GPP_D12, NONE, DEEP, NF1),
+	/* I2S0_RXD_HDR */
+	PAD_CFG_NF(GPP_D13, NONE, DEEP, NF1),
+	/* I2S1_TXD_HDR */
+	PAD_CFG_NF(GPP_S00, NONE, DEEP, NF1),
+	/* I2S1_RXD_HDR */
+	PAD_CFG_NF(GPP_S01, NONE, DEEP, NF1),
+	/* I2S1_SCLK_HDR */
+	PAD_CFG_NF(GPP_S02, NONE, DEEP, NF1),
+	/* I2S1_SFRM_HDR */
+	PAD_CFG_NF(GPP_S03, NONE, DEEP, NF1),
+	/* I2S2_SCLK_HDR */
+	PAD_CFG_NF(GPP_S04, NONE, DEEP, NF1),
+	/* I2S2_SFRM_HDR */
+	PAD_CFG_NF(GPP_S05, NONE, DEEP, NF1),
+	/* I2S2_TXD_HDR */
+	PAD_NC(GPP_S06, NONE),
+	/* I2S2_RXD_HDR */
+	PAD_NC(GPP_S07, NONE),
+
+	/* DMIC_CLK */
+	PAD_NC(GPP_D16, NONE),
+	/* DMIC_DATA */
+	PAD_NC(GPP_D17, NONE),
+};
+
 static const struct pad_config hda_enable_pads[] = {
 	/* GPP_D10:     HDA_BCLK (HDR) */
 	PAD_CFG_NF(GPP_D10, NONE, DEEP, NF1),
@@ -484,6 +518,9 @@ void fw_config_gpio_padbased_override(struct pad_config *padbased_table)
 		GPIO_PADBASED_OVERRIDE(padbased_table, sndw_alc721_enable_pads);
 	} else if (fw_config_probe(FW_CONFIG(AUDIO, AUDIO_ALC256_HDA))) {
 		GPIO_PADBASED_OVERRIDE(padbased_table, hda_enable_pads);
+	} else if (fw_config_probe(FW_CONFIG(AUDIO, AUDIO_MAX98360_ALC5682I_I2S))) {
+		printk(BIOS_INFO, "Configure GPIOs for I2S MAX98360 ALC5682 audio.\n");
+		GPIO_PADBASED_OVERRIDE(padbased_table, i2s_enable_pads);
 	}
 
 	if (fw_config_probe(FW_CONFIG(WIFI, WIFI_PCIE_6)) ||
diff --git a/src/mainboard/google/ocelot/variants/ocelot/overridetree.cb b/src/mainboard/google/ocelot/variants/ocelot/overridetree.cb
index 149d0859e2..510d8aeb95 100644
--- a/src/mainboard/google/ocelot/variants/ocelot/overridetree.cb
+++ b/src/mainboard/google/ocelot/variants/ocelot/overridetree.cb
@@ -1,61 +1,62 @@
 fw_config
 	field AUDIO 0 1
-		option AUDIO_NONE		0
-		option AUDIO_ALC721_SNDW	1
-		option AUDIO_ALC256_HDA		2
+		option AUDIO_NONE			0
+		option AUDIO_ALC721_SNDW		1
+		option AUDIO_ALC256_HDA			2
+		option AUDIO_MAX98360_ALC5682I_I2S	3
 	end
 	field WIFI 2 4
-		option WIFI_NONE		0
-		option WIFI_CNVI_6		1
-		option WIFI_PCIE_6		2
-		option WIFI_CNVI_7		3
-		option WIFI_PCIE_7		4
+		option WIFI_NONE			0
+		option WIFI_CNVI_6			1
+		option WIFI_PCIE_6			2
+		option WIFI_CNVI_7			3
+		option WIFI_PCIE_7			4
 	end
 	field CELLULAR 5 6
-		option CELLULAR_ABSENT		0
-		option CELLULAR_USB		1
-		option CELLULAR_PCIE		2
+		option CELLULAR_ABSENT			0
+		option CELLULAR_USB			1
+		option CELLULAR_PCIE			2
 	end
 	field TOUCHSCREEN 7 8
-		option TOUCHSCREEN_NONE		0
-		option TOUCHSCREEN_THC_SPI	1
-		option TOUCHSCREEN_THC_I2C	2
+		option TOUCHSCREEN_NONE			0
+		option TOUCHSCREEN_THC_SPI		1
+		option TOUCHSCREEN_THC_I2C		2
 	end
 	field TOUCHPAD 9 10
-		option TOUCHPAD_NONE		0
-		option TOUCHPAD_THC_I2C		1
-		option TOUCHPAD_LPSS_I2C	2
+		option TOUCHPAD_NONE			0
+		option TOUCHPAD_THC_I2C			1
+		option TOUCHPAD_LPSS_I2C		2
 	end
 	field SD 11 12
-		option SD_NONE			0
-		option SD_GENSYS		1
-		option SD_BAYHUB		2
+		option SD_NONE				0
+		option SD_GENSYS			1
+		option SD_BAYHUB			2
 	end
 	field STORAGE 13 14
-		option STORAGE_UNKNOWN		0
-		option STORAGE_NVME_GEN4	1
-		option STORAGE_UFS		2
+		option STORAGE_UNKNOWN			0
+		option STORAGE_NVME_GEN4		1
+		option STORAGE_UFS			2
 	end
 	field FP 15
-		option FP_ABSENT		0
-		option FP_PRESENT		1
+		option FP_ABSENT			0
+		option FP_PRESENT			1
 	end
 	field DISPLAY 16 17
-		option DISPLAY_ABSENT		0
-		option DISPLAY_TOUCH_PRESENT	1
-		option DISPLAY_NO_TOUCH_PRESENT	2
+		option DISPLAY_ABSENT			0
+		option DISPLAY_TOUCH_PRESENT		1
+		option DISPLAY_NO_TOUCH_PRESENT		2
 	end
 	field ISH 18
-		option ISH_DISABLE		0
-		option ISH_ENABLE		1
+		option ISH_DISABLE			0
+		option ISH_ENABLE			1
 	end
 	field KB 19
-		option KB_ABSENT		0
-		option KB_PRESENT		1
+		option KB_ABSENT			0
+		option KB_PRESENT			1
 	end
 	field PSU 20
-		option PSU_USBC			0
-		option PSU_BJ			1
+		option PSU_USBC				0
+		option PSU_BJ				1
 	end
 end
 

From 5f168e9441d5b52ababb9035cfc661f24d7ddf8f Mon Sep 17 00:00:00 2001
From: Avi Uday <aviuday@google.com>
Date: Mon, 25 Aug 2025 14:26:09 +0530
Subject: [PATCH 1879/3886] mb/google/ocelot/var/ocelot: Conditionally init
 ALC256 HDA using fw_config

This commit implements `mainboard_is_hda_codec_enabled()` for the
Google Ocelot mainboard variant. This overrides the default weak HDA
common initialization.

Change-Id: I11f9d8ae00d1a3d7f03e068aa3980ecd98a47ecd
Signed-off-by: Avi Uday <aviuday@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88933
Reviewed-by: Pranava Y N <pranavayn@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 .../google/ocelot/variants/ocelot/variant.c   | 20 +++++++++++++++++++
 1 file changed, 20 insertions(+)

diff --git a/src/mainboard/google/ocelot/variants/ocelot/variant.c b/src/mainboard/google/ocelot/variants/ocelot/variant.c
index cb3908277e..5765b29c4a 100644
--- a/src/mainboard/google/ocelot/variants/ocelot/variant.c
+++ b/src/mainboard/google/ocelot/variants/ocelot/variant.c
@@ -4,6 +4,7 @@
 #include <ec/google/chromeec/ec.h>
 #include <fsp/api.h>
 #include <fw_config.h>
+#include <intelblocks/hda.h>
 #include <sar.h>
 #include <soc/gpio_soc_defs.h>
 #include <drivers/intel/touch/chip.h>
@@ -71,3 +72,22 @@ bool variant_is_barrel_charger_present(void)
 	else
 		return false;
 }
+
+/*
+ * HDA verb table loading is supported based on the firmware configuration.
+ *
+ * This function determines if the current platform has an HDA codec enabled by
+ * examining the `FW_CONFIG` value. Specifically, it checks if the
+ * `FW_CONFIG` includes the `AUDIO_ALC256_HDA` value, which is used to identify
+ * Fatcat SKUs with HDA codec support.
+ *
+ * Return true if the `FW_CONFIG` indicates HDA support (i.e., contains
+ * `AUDIO_ALC256_HDA`), false otherwise.
+ */
+bool mainboard_is_hda_codec_enabled(void)
+{
+	if (fw_config_probe(FW_CONFIG(AUDIO, AUDIO_ALC256_HDA)))
+		return true;
+
+	return false;
+}

From ec69479bdb79c2dec7a03d243ca902ffb2a259aa Mon Sep 17 00:00:00 2001
From: Avi Uday <aviuday@google.com>
Date: Mon, 25 Aug 2025 18:21:34 +0530
Subject: [PATCH 1880/3886] mb/google/ocelot: Drop redundant SNDW GPIO mapping

This patch removes redundant SNDW GPIO mapping that was already present
in fw_config.c and applied as per FW_CONFIG.

TEST=Verify that ocelot builds without any error
Change-Id: I8ba76d77764d4b9cec22c79b977ad9e486ae804e
Signed-off-by: Avi Uday <aviuday@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88937
Reviewed-by: Pranava Y N <pranavayn@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 .../google/ocelot/variants/ocelot/gpio.c       | 18 ------------------
 1 file changed, 18 deletions(-)

diff --git a/src/mainboard/google/ocelot/variants/ocelot/gpio.c b/src/mainboard/google/ocelot/variants/ocelot/gpio.c
index dcef9f7579..41c21a1b39 100644
--- a/src/mainboard/google/ocelot/variants/ocelot/gpio.c
+++ b/src/mainboard/google/ocelot/variants/ocelot/gpio.c
@@ -296,24 +296,6 @@ static const struct pad_config gpio_table[] = {
 	/* GPP_H24:     TP */
 	PAD_CFG_NF(GPP_H24, NONE, DEEP, NF1),
 
-	/* GPP_S */
-	/* GPP_S00:     SNDW3_CLK_CODEC (HDR) */
-	PAD_CFG_NF(GPP_S00, NONE, DEEP, NF1),
-	/* GPP_S01:     SNDW3_DATA0_CODEC (HDR) */
-	PAD_CFG_NF(GPP_S01, NONE, DEEP, NF1),
-	/* GPP_S02:     SNDW3_DATA1_CODEC (HDR) */
-	PAD_CFG_NF(GPP_S02, NONE, DEEP, NF1),
-	/* GPP_S03:     SNDW3_DATA2_CODEC (HDR) */
-	PAD_CFG_NF(GPP_S03, NONE, DEEP, NF1),
-	/* GPP_S04:     DMIC0_CLK (HDR) */
-	PAD_CFG_NF(GPP_S04, NONE, DEEP, NF5),
-	/* GPP_S05:     DMIC0_DATA (HDR) */
-	PAD_CFG_NF(GPP_S05, NONE, DEEP, NF5),
-	/* GPP_S06:     DMIC1_CLK (HDR) */
-	PAD_CFG_NF(GPP_S06, NONE, DEEP, NF5),
-	/* GPP_S07:     DMIC1_DATA (HDR) */
-	PAD_CFG_NF(GPP_S07, NONE, DEEP, NF5),
-
 	/* GPP_V */
 	/* GPP_V00:     PM_BATLOW_N */
 	PAD_CFG_NF(GPP_V00, NONE, DEEP, NF1),

From 67afbf5f96cf42a6a2d42206b59e9266190d82eb Mon Sep 17 00:00:00 2001
From: Simon Yang <simon1.yang@intel.com>
Date: Mon, 25 Aug 2025 13:48:40 +0800
Subject: [PATCH 1881/3886] soc/intel/pantherlake: Add TDP mappings for Panther
 Lake-U SKUs

This commit addresses incorrect Thermal Design Power (TDP) mappings for
Panther Lake-U SKUs. Both 15W and 25W TDPs are now correctly mapped to
the same Power Limit configurations, ensuring consistent handling of
these SKUs.

Below is the collection of documents utilized to address this issue:
1. 815002 Panther Lake H Processor - External Design Specification
   Revision. 1.52
2. 813278 Panther Lake H Power Map - Rev 1p6

BUG=None
TEST=Do not see error log "Could not find the SKU power map" and warning
     "Skipped power limits configuration for SA PCI ID: 0xb003"

Change-Id: I995183a04b47967dd22ee6f4f3820da7eeb175bf
Signed-off-by: Simon Yang <simon1.yang@intel.com>
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88930
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Bora Guvendik <bora.guvendik@intel.corp-partner.google.com>
---
 src/soc/intel/pantherlake/chip.h | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/src/soc/intel/pantherlake/chip.h b/src/soc/intel/pantherlake/chip.h
index b424cb1ebc..e9a73a1635 100644
--- a/src/soc/intel/pantherlake/chip.h
+++ b/src/soc/intel/pantherlake/chip.h
@@ -85,8 +85,11 @@ static const struct soc_intel_pantherlake_power_map {
 	enum soc_intel_pantherlake_sku sku;
 } cpuid_to_ptl[] = {
 	{ PCI_DID_INTEL_PTL_U_ID_1, PTL_U_1_CORE, TDP_15W, PTL_H404_SKU },
+	{ PCI_DID_INTEL_PTL_U_ID_1, PTL_U_1_CORE, TDP_25W, PTL_H404_SKU },
 	{ PCI_DID_INTEL_PTL_U_ID_2, PTL_U_2_CORE, TDP_15W, PTL_H204_SKU },
+	{ PCI_DID_INTEL_PTL_U_ID_2, PTL_U_2_CORE, TDP_25W, PTL_H204_SKU },
 	{ PCI_DID_INTEL_PTL_U_ID_3, PTL_U_2_CORE, TDP_15W, PTL_H404_SKU },
+	{ PCI_DID_INTEL_PTL_U_ID_3, PTL_U_2_CORE, TDP_25W, PTL_H404_SKU },
 	{ PCI_DID_INTEL_PTL_H_ID_1, PTL_H_1_CORE, TDP_25W, PTL_H12XE_SKU },
 	{ PCI_DID_INTEL_PTL_H_ID_2, PTL_H_1_CORE, TDP_25W, PTL_H484_SKU },
 	{ PCI_DID_INTEL_PTL_H_ID_3, PTL_H_2_CORE, TDP_25W, PTL_H12XE_SKU },

From 1c571446ec1402f4908aae1eb714d779f337acbe Mon Sep 17 00:00:00 2001
From: Subrata Banik <subratabanik@google.com>
Date: Wed, 27 Aug 2025 23:07:25 +0530
Subject: [PATCH 1882/3886] soc/intel/common/block/systemagent: Increase MTRR
 region size to 32 MiB
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

This patch increases the hardcoded MTRR region size from 16 MiB to 32
MiB. This ensures a larger portion of memory is cached after the DRAM
phase, which helps in avoiding performance issues in memory-constrained
boots like the pre-DRAM stage. This change is crucial for optimal system
performance.

TEST=Able to boot google/fatcat and save 13ms of the boot time.

w/o this patch:

```
    31:device enumeration            1,183,804 (13,341)
```

w/ this patch:

```
    31:device enumeration            1,159,612 (359)
```

Change-Id: I25463f1b9e3b82b1a05a8fb7a44df4d188b4731a
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88971
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Pranava Y N <pranavayn@google.com>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
---
 src/soc/intel/common/block/systemagent/memmap.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/soc/intel/common/block/systemagent/memmap.c b/src/soc/intel/common/block/systemagent/memmap.c
index ca9f680195..3b0fb6e8ae 100644
--- a/src/soc/intel/common/block/systemagent/memmap.c
+++ b/src/soc/intel/common/block/systemagent/memmap.c
@@ -65,7 +65,7 @@ void fill_postcar_frame(struct postcar_frame *pcf)
 	/*
 	 * We need to make sure ramstage will be run cached. At this
 	 * point exact location of ramstage in cbmem is not known.
-	 * Instruct postcar to cache 16 megs below cbmem top which is
+	 * Instruct postcar to cache 32 megs below cbmem top which is
 	 * a safe bet to cover ramstage.
 	 */
 	printk(BIOS_DEBUG, "top_of_ram = 0x%lx\n", top_of_ram);
@@ -77,7 +77,7 @@ void fill_postcar_frame(struct postcar_frame *pcf)
 	if (ENV_CREATES_CBMEM && CONFIG(SOC_INTEL_COMMON_BASECODE_RAMTOP))
 		update_ramtop(top_of_ram);
 
-	postcar_frame_add_mtrr(pcf, top_of_ram - 16 * MiB, 16 * MiB, MTRR_TYPE_WRBACK);
+	postcar_frame_add_mtrr(pcf, top_of_ram - 32 * MiB, 32 * MiB, MTRR_TYPE_WRBACK);
 
 	/* Cache the TSEG region */
 	postcar_enable_tseg_cache(pcf);

From 5f0225a7b57b837517fb6e0b3cfd3bccb1fc4a8a Mon Sep 17 00:00:00 2001
From: Subrata Banik <subratabanik@google.com>
Date: Thu, 28 Aug 2025 16:06:15 +0530
Subject: [PATCH 1883/3886] drivers/intel/fsp2_0: Refactor for earlier graphics
 memory WC MTRR
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Moves the MTRR setup for graphics memory (GMADR) from the
`soc_load_logo_by_coreboot()` function to `do_silicon_init()`. This
refactors the logic into a new helper function,
`soc_mark_gfx_memory()`, which acquires a temporary Write-Combine
(WC) MTRR.

The MTRR is now configured earlier in the silicon initialization
process, making the setup and cleanup independent of the
`soc_load_logo_by_coreboot()` function itself.

This improves FSP-S performance and ensures the MTRR is correctly
managed within the silicon initialization flow which was earlier
missed when platform selects `USE_COREBOOT_FOR_BMP_RENDERING` aka
rendering the BMP logo using coreboot driver and not using FSP driver
logic.

The cleanup of the MTRR is also moved to `do_silicon_init()` to pair
with the earlier setup.

TEST=Successfully boot to OS on google/fatcat using coreboot for logo
rendering.

w/o this patch

```
    963:returning from FspMultiPhaseSiInit    1,164,839 (123,244)
```

w/ this patch

```
    963:returning from FspMultiPhaseSiInit    1,143,974 (115,443)
```

Change-Id: I5da3178c622f5fd6cb3d7f3f574e59f9ed5a5b3d
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88982
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Reviewed-by: Pranava Y N <pranavayn@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/drivers/intel/fsp2_0/cb_logo.c         | 30 ++++++++++++++--------
 src/drivers/intel/fsp2_0/include/fsp/api.h |  2 ++
 src/drivers/intel/fsp2_0/silicon_init.c    |  9 +++++++
 3 files changed, 30 insertions(+), 11 deletions(-)

diff --git a/src/drivers/intel/fsp2_0/cb_logo.c b/src/drivers/intel/fsp2_0/cb_logo.c
index c77e55eeed..33563d5271 100644
--- a/src/drivers/intel/fsp2_0/cb_logo.c
+++ b/src/drivers/intel/fsp2_0/cb_logo.c
@@ -39,11 +39,29 @@ static void program_igd_lmembar(uint32_t base)
 	pci_or_config16(SA_DEV_IGD, PCI_COMMAND, enable_mask);
 }
 
+/*
+ * Marks the GMADR range as Write-Combine (WC) memory.
+ *
+ * This function acquires and configures a temporary MTRR for the GMADR range.
+ *
+ * @return valid MTRR index on success, -1 on failure.
+ */
+int soc_mark_gfx_memory(void)
+{
+	/* Set up a temporary Write Combine (WC) MTRR for the GMADR range */
+	int temp_mtrr_index = acquire_and_configure_mtrr(GMADR_BASE, GMADR_SIZE, MTRR_TYPE_WRCOMB);
+	if (temp_mtrr_index < 0) {
+		printk(BIOS_ERR, "Failed to configure WC MTRR for GMADR.\n");
+		return -1;
+	}
+
+	return temp_mtrr_index;
+}
+
 void soc_load_logo_by_coreboot(void)
 {
 	const struct hob_graphics_info *ginfo;
 	struct soc_intel_common_config *config = chip_get_common_soc_structure();
-	int temp_mtrr_index = -1;
 	struct logo_config logo_cfg;
 	size_t size;
 
@@ -57,13 +75,6 @@ void soc_load_logo_by_coreboot(void)
 	/* Program the IGD LMEMBAR */
 	program_igd_lmembar(GMADR_BASE);
 
-	/* Set up a temporary Write Combine (WC) MTRR for the GMADR range */
-	temp_mtrr_index = acquire_and_configure_mtrr(GMADR_BASE, GMADR_SIZE, MTRR_TYPE_WRCOMB);
-	if (temp_mtrr_index < 0) {
-		printk(BIOS_ERR, "Failed to configure WC MTRR for GMADR.\n");
-		return;
-	}
-
 	/*
 	 * Adjusts panel orientation for external display when the lid is closed.
 	 *
@@ -88,7 +99,4 @@ void soc_load_logo_by_coreboot(void)
 	logo_cfg.logo_bottom_margin = config->logo_bottom_margin;
 
 	render_logo_to_framebuffer(&logo_cfg);
-
-	/* Clear temporary Write Combine (WC) MTRR */
-	clear_var_mtrr(temp_mtrr_index);
 }
diff --git a/src/drivers/intel/fsp2_0/include/fsp/api.h b/src/drivers/intel/fsp2_0/include/fsp/api.h
index 9ff32be6fc..84edb640b2 100644
--- a/src/drivers/intel/fsp2_0/include/fsp/api.h
+++ b/src/drivers/intel/fsp2_0/include/fsp/api.h
@@ -108,8 +108,10 @@ void soc_load_logo_by_fsp(FSPS_UPD *supd);
  */
 #if CONFIG(USE_COREBOOT_FOR_BMP_RENDERING)
 void soc_load_logo_by_coreboot(void);
+int soc_mark_gfx_memory(void);
 #else
 static inline void soc_load_logo_by_coreboot(void) { /* nop */ }
+static inline int soc_mark_gfx_memory(void) { return -1; }
 #endif
 
 /* Update the SOC specific memory config param for mma. */
diff --git a/src/drivers/intel/fsp2_0/silicon_init.c b/src/drivers/intel/fsp2_0/silicon_init.c
index 6de71c9202..ea179bd945 100644
--- a/src/drivers/intel/fsp2_0/silicon_init.c
+++ b/src/drivers/intel/fsp2_0/silicon_init.c
@@ -6,6 +6,7 @@
 #include <cbfs.h>
 #include <cbmem.h>
 #include <commonlib/fsp.h>
+#include <cpu/x86/mtrr.h>
 #include <stdlib.h>
 #include <console/console.h>
 #include <fsp/api.h>
@@ -96,6 +97,7 @@ static void do_silicon_init(struct fsp_header *hdr)
 	fsp_multi_phase_init_fn multi_phase_si_init;
 	struct fsp_multi_phase_params multi_phase_params;
 	struct fsp_multi_phase_get_number_of_phases_params multi_phase_get_number;
+	int temp_mtrr_index = -1;
 
 	supd = (FSPS_UPD *)(uintptr_t)(hdr->cfg_region_offset + hdr->image_base);
 
@@ -123,6 +125,9 @@ static void do_silicon_init(struct fsp_header *hdr)
 	/* Give SoC/mainboard a chance to populate entries */
 	platform_fsp_silicon_init_params_cb(upd);
 
+	if (CONFIG(BMP_LOGO) && CONFIG(USE_COREBOOT_FOR_BMP_RENDERING))
+		temp_mtrr_index = soc_mark_gfx_memory();
+
 	/*
 	 * Populate UPD entries for the logo if the platform utilizes
 	 * the FSP's capability for rendering bitmap (BMP) images.
@@ -229,6 +234,10 @@ static void do_silicon_init(struct fsp_header *hdr)
 		 * the rendering.
 		 */
 		timestamp_add_now(TS_FIRMWARE_SPLASH_RENDERED);
+
+		/* Clear temporary Write Combine (WC) MTRR */
+		if (temp_mtrr_index >= 0)
+			clear_var_mtrr(temp_mtrr_index);
 	}
 
 	/* Reinitialize CPUs if FSP-S has done MP Init */

From 22fe08c04b4ccd6d3d96b0856620760e67dd92e8 Mon Sep 17 00:00:00 2001
From: Vince Liu <vince-wl.liu@mediatek.corp-partner.google.com>
Date: Wed, 27 Aug 2025 14:34:44 +0800
Subject: [PATCH 1884/3886] soc/mediatek/mt8189: Implement UFS power-off API
 for non-UFS SKUs

On MT8189, UFS power is enabled by default. For SKUs that do not use UFS
as storage, keeping UFS power enabled can cause suspend failures and
unnecessary power consumption. This change implements a UFS power-off
API to ensure UFS can be properly powered down on non-UFS SKUs.

BUG=b:430421429
BRANCH=skywalker
TEST=Suspend flow works correctly, and SoC power consumption is 34 mW,
     meeting expectations on Anakin.

Signed-off-by: Vince Liu <vince-wl.liu@mediatek.corp-partner.google.com>
Signed-off-by: Irving-ch Lin <irving-ch.lin@mediatek.corp-partner.google.com>
Change-Id: Ib5ccbeaf951c3a095905e472bc096eeb2dee47a8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88976
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
---
 src/soc/mediatek/common/include/soc/mtcmos.h  |  4 ++
 src/soc/mediatek/common/mtcmos.c              | 71 +++++++++++++++++++
 .../mediatek/mt8189/include/soc/spm_mtcmos.h  |  1 +
 src/soc/mediatek/mt8189/mtcmos.c              | 63 ++++++++++++----
 4 files changed, 127 insertions(+), 12 deletions(-)

diff --git a/src/soc/mediatek/common/include/soc/mtcmos.h b/src/soc/mediatek/common/include/soc/mtcmos.h
index 15b4367fc4..a38d3f7ac2 100644
--- a/src/soc/mediatek/common/include/soc/mtcmos.h
+++ b/src/soc/mediatek/common/include/soc/mtcmos.h
@@ -5,6 +5,8 @@
 
 struct bus_protect {
 	void *clr_addr;
+	void *set_addr;
+	void *rdy_addr;
 	u32 mask;
 };
 
@@ -28,9 +30,11 @@ struct power_domain_data {
 void mtcmos_set_scpd_ext_buck_iso(const struct power_domain_data *pd);
 
 void mtcmos_power_on(const struct power_domain_data *pd);
+void mtcmos_power_off(const struct power_domain_data *pd);
 void mtcmos_adsp_power_on(void);
 void mtcmos_audio_power_on(void);
 void mtcmos_display_power_on(void);
+void mtcmos_ufs_power_off(void);
 
 void mtcmos_protect_adsp_bus(void);
 void mtcmos_protect_audio_bus(void);
diff --git a/src/soc/mediatek/common/mtcmos.c b/src/soc/mediatek/common/mtcmos.c
index f69e84fab7..0172e24981 100644
--- a/src/soc/mediatek/common/mtcmos.c
+++ b/src/soc/mediatek/common/mtcmos.c
@@ -1,8 +1,14 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
+#include <assert.h>
+#include <console/console.h>
 #include <delay.h>
 #include <device/mmio.h>
 #include <soc/spm.h>
+#include <timer.h>
+
+#define MTCMOS_TIMEOUT_US	500
+#define MTCMOS_ETIMEDOUT	25
 
 enum {
 	SRAM_ISOINT_B	= 1U << 6,
@@ -19,6 +25,20 @@ __weak void mtcmos_set_scpd_ext_buck_iso(const struct power_domain_data *pd)
 	/* do nothing */
 }
 
+static int mtcmos_wait_for_state(u32 *reg, u32 mask, bool is_set)
+{
+	u32 expect = is_set ? mask : 0;
+
+	if (!wait_us(MTCMOS_TIMEOUT_US, ((read32(reg) & mask) == expect))) {
+		printk(BIOS_ERR,
+		       "%s (0x%p, %#x, %d) timeout after %d us, reg_val=%#x\n",
+		       __func__, reg, mask, is_set, MTCMOS_TIMEOUT_US, read32(reg));
+		return -MTCMOS_ETIMEDOUT;
+	}
+
+	return 0;
+}
+
 static void release_bus_protection(const struct power_domain_data *pd)
 {
 	int i;
@@ -27,6 +47,19 @@ static void release_bus_protection(const struct power_domain_data *pd)
 		write32(pd->bp_table[i].clr_addr, pd->bp_table[i].mask);
 }
 
+static void set_bus_protection(const struct power_domain_data *pd)
+{
+	int i;
+
+	for (i = pd->bp_steps - 1; i >= 0; i--) {
+		const struct bus_protect *bp = &pd->bp_table[i];
+		assert(bp->set_addr && bp->rdy_addr);
+		write32(bp->set_addr, bp->mask);
+		mtcmos_wait_for_state(bp->rdy_addr, bp->mask, true);
+	}
+}
+
+
 void mtcmos_power_on(const struct power_domain_data *pd)
 {
 	u32 *pwr_status;
@@ -70,6 +103,44 @@ void mtcmos_power_on(const struct power_domain_data *pd)
 	release_bus_protection(pd);
 }
 
+void mtcmos_power_off(const struct power_domain_data *pd)
+{
+	u32 *pwr_status;
+	u32 *pwr_status_2nd;
+
+	write32(&mtk_spm->poweron_config_set,
+		(SPM_PROJECT_CODE << 16) | (1U << 0));
+
+	set_bus_protection(pd);
+
+	if (pd->sram_pdn_mask) {
+		if (pd->caps & SCPD_SRAM_ISO) {
+			setbits32(pd->pwr_con, SRAM_CKISO);
+			clrbits32(pd->pwr_con, SRAM_ISOINT_B);
+			udelay(1);
+		}
+		setbits32(pd->pwr_con, pd->sram_pdn_mask);
+		mtcmos_wait_for_state(pd->pwr_con, pd->sram_ack_mask, true);
+	}
+
+	setbits32(pd->pwr_con, PWR_ISO);
+	setbits32(pd->pwr_con, PWR_CLK_DIS);
+	clrbits32(pd->pwr_con, PWR_RST_B);
+
+	if (pd->pwr_status && pd->pwr_status_2nd) {
+		pwr_status = pd->pwr_status;
+		pwr_status_2nd = pd->pwr_status_2nd;
+	} else {
+		pwr_status = &mtk_spm->pwr_status;
+		pwr_status_2nd = &mtk_spm->pwr_status_2nd;
+	}
+
+	clrbits32(pd->pwr_con, PWR_ON);
+	mtcmos_wait_for_state(pwr_status, pd->pwr_sta_mask, false);
+	clrbits32(pd->pwr_con, PWR_ON_2ND);
+	mtcmos_wait_for_state(pwr_status_2nd, pd->pwr_sta_mask, false);
+}
+
 void mtcmos_display_power_on(void)
 {
 	int i;
diff --git a/src/soc/mediatek/mt8189/include/soc/spm_mtcmos.h b/src/soc/mediatek/mt8189/include/soc/spm_mtcmos.h
index e68b531bb9..9c9b6d8afc 100644
--- a/src/soc/mediatek/mt8189/include/soc/spm_mtcmos.h
+++ b/src/soc/mediatek/mt8189/include/soc/spm_mtcmos.h
@@ -24,6 +24,7 @@ struct mtk_vlpcfg_regs {
 	u32 bus_vlp_topaxi_protecten;
 	u32 bus_vlp_topaxi_protecten_set;
 	u32 bus_vlp_topaxi_protecten_clr;
+	u32 bus_vlp_topaxi_protecten_sta0;
 	u32 bus_vlp_topaxi_protecten_sta1;
 };
 check_member(mtk_vlpcfg_regs, vlp_test_ck_ctrl, 0x0004);
diff --git a/src/soc/mediatek/mt8189/mtcmos.c b/src/soc/mediatek/mt8189/mtcmos.c
index 8b89e58ad2..b212b72a59 100644
--- a/src/soc/mediatek/mt8189/mtcmos.c
+++ b/src/soc/mediatek/mt8189/mtcmos.c
@@ -11,24 +11,55 @@
 #include <soc/spm_mtcmos.h>
 
 static const struct bus_protect bp_ufs[] = {
-	{&mtk_vlpcfg->bus_vlp_topaxi_protecten_clr, BIT(6)},
-	{&mtk_infracfg_ao->perisys_protect.clr, BIT(4)},
-	{&mtk_vlpcfg->bus_vlp_topaxi_protecten_clr, BIT(5)},
+	{
+		.clr_addr = &mtk_vlpcfg->bus_vlp_topaxi_protecten_clr,
+		.set_addr = &mtk_vlpcfg->bus_vlp_topaxi_protecten_set,
+		.rdy_addr = &mtk_vlpcfg->bus_vlp_topaxi_protecten_sta1,
+		.mask = BIT(6),
+	},
+	{
+		.clr_addr = &mtk_infracfg_ao->perisys_protect.clr,
+		.set_addr = &mtk_infracfg_ao->perisys_protect.set,
+		.rdy_addr = &mtk_infracfg_ao->perisys_protect.ready,
+		.mask = BIT(4),
+	},
+	{
+		.clr_addr = &mtk_vlpcfg->bus_vlp_topaxi_protecten_clr,
+		.set_addr = &mtk_vlpcfg->bus_vlp_topaxi_protecten_set,
+		.rdy_addr = &mtk_vlpcfg->bus_vlp_topaxi_protecten_sta1,
+		.mask = BIT(5),
+	},
 };
 
 static const struct bus_protect bp_mminfra[] = {
-	{&mtk_infracfg_ao->emisys_protect.clr, BIT(20) | BIT(21)},
-	{&mtk_infracfg_ao->infrasys_protect[0].clr, BIT(16)},
-	{&mtk_infracfg_ao->mmsys_protect[1].clr,
-	 BIT(0) | BIT(7) | BIT(8) | BIT(9) | BIT(10) |
-	 BIT(11) | BIT(12) | BIT(13) | BIT(14) | BIT(15)},
-	{&mtk_infracfg_ao->infrasys_protect[1].clr, BIT(11)},
-	{&mtk_infracfg_ao->mmsys_protect[1].clr,
-	 BIT(1) | BIT(2) | BIT(3)},
+	{
+		.clr_addr = &mtk_infracfg_ao->emisys_protect.clr,
+		.mask = BIT(20) | BIT(21),
+	},
+	{
+		.clr_addr = &mtk_infracfg_ao->infrasys_protect[0].clr,
+		.mask = BIT(16),
+	},
+	{
+		.clr_addr = &mtk_infracfg_ao->mmsys_protect[1].clr,
+		.mask = BIT(0) | BIT(7) | BIT(8) | BIT(9) | BIT(10) |
+			BIT(11) | BIT(12) | BIT(13) | BIT(14) | BIT(15),
+	},
+	{
+		.clr_addr = &mtk_infracfg_ao->infrasys_protect[1].clr,
+		.mask = BIT(11),
+	},
+	{
+		.clr_addr = &mtk_infracfg_ao->mmsys_protect[1].clr,
+		.mask = BIT(1) | BIT(2) | BIT(3),
+	},
 };
 
 static const struct bus_protect bp_ssusb[] = {
-	{&mtk_infracfg_ao->perisys_protect.clr, BIT(7)},
+	{
+		.clr_addr = &mtk_infracfg_ao->perisys_protect.clr,
+		.mask = BIT(7),
+	},
 };
 
 static const struct power_domain_data pd_plat[] = {
@@ -81,6 +112,14 @@ void mtcmos_init(void)
 		mtcmos_power_on(&pd_plat[i]);
 }
 
+void mtcmos_ufs_power_off(void)
+{
+	/* ufs0_phy */
+	mtcmos_power_off(&pd_plat[1]);
+	/* ufs0 */
+	mtcmos_power_off(&pd_plat[0]);
+}
+
 void mtcmos_protect_audio_bus(void)
 {
 	write32(&mtk_infracfg_ao->perisys_protect.clr, BIT(6));

From 7896f4950cd760778aae735871c7a0126824c122 Mon Sep 17 00:00:00 2001
From: Vince Liu <vince-wl.liu@mediatek.corp-partner.google.com>
Date: Wed, 27 Aug 2025 15:31:50 +0800
Subject: [PATCH 1885/3886] mb/google/skywalker: Turn off UFS power for eMMC
 SKUs

On MT8189, UFS power is enabled by default. For SKUs that use eMMC for
storage and do not need UFS, it is necessary to disable UFS power;
otherwise, the system will fail to suspend properly. Disabling UFS
power in these cases both saves power and ensures correct suspend
functionality.

BUG=b:430421429
BRANCH=skywalker
TEST=Suspend flow works correctly, and SoC power consumption is 34 mW,
     meeting expectations on Anakin.

Signed-off-by: Vince Liu <vince-wl.liu@mediatek.corp-partner.google.com>
Change-Id: Ie932a939f663e159e098fd13c7e26e9a2089e7bd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88977
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/google/skywalker/mainboard.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/src/mainboard/google/skywalker/mainboard.c b/src/mainboard/google/skywalker/mainboard.c
index fb5316201a..ba6b66fd18 100644
--- a/src/mainboard/google/skywalker/mainboard.c
+++ b/src/mainboard/google/skywalker/mainboard.c
@@ -88,8 +88,10 @@ enum mtk_storage_type mainboard_get_storage_type(void)
 
 static void mainboard_init(struct device *dev)
 {
-	if (mainboard_get_storage_type() == STORAGE_EMMC)
+	if (mainboard_get_storage_type() == STORAGE_EMMC) {
 		mtk_msdc_configure_emmc(true);
+		mtcmos_ufs_power_off();
+	}
 
 	dpm_init();
 	setup_usb_host();

From 8a52418e9a34c962a6e3688263f7c37aec5946f6 Mon Sep 17 00:00:00 2001
From: Yu-Ping Wu <yupingso@chromium.org>
Date: Tue, 26 Aug 2025 16:43:03 +0800
Subject: [PATCH 1886/3886] commonlib/device_tree: Fix memory leak in
 fdt_unflatten()

When the passed `blob` is not a valid FDT, the memory allocated for
`tree` should be freed. Move the allocation after the fdt_is_valid()
check to avoid the problem.

Also remove the unnecessary cast to 'const struct fdt_header *'.

Change-Id: If591172cd511ae2a1ca9c26f2addef8d67fd0b69
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88948
Reviewed-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
---
 src/commonlib/device_tree.c | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/src/commonlib/device_tree.c b/src/commonlib/device_tree.c
index fb1e78f590..a6fdd0cb61 100644
--- a/src/commonlib/device_tree.c
+++ b/src/commonlib/device_tree.c
@@ -766,13 +766,13 @@ bool fdt_is_valid(const void *blob)
 
 struct device_tree *fdt_unflatten(const void *blob)
 {
-	struct device_tree *tree = xzalloc(sizeof(*tree));
-	const struct fdt_header *header = (const struct fdt_header *)blob;
-	tree->header = header;
-
 	if (!fdt_is_valid(blob))
 		return NULL;
 
+	const struct fdt_header *header = blob;
+	struct device_tree *tree = xzalloc(sizeof(*tree));
+	tree->header = header;
+
 	uint32_t struct_offset = be32toh(header->structure_offset);
 	uint32_t strings_offset = be32toh(header->strings_offset);
 	uint32_t reserve_offset = be32toh(header->reserve_map_offset);

From ad10d4a97703142581b23a8b4e7005c9d711d588 Mon Sep 17 00:00:00 2001
From: Ravi Sarawadi <ravishankar.sarawadi@intel.com>
Date: Wed, 7 Aug 2024 22:06:30 -0700
Subject: [PATCH 1887/3886] soc/intel/cmn/blk/graphics: Reserve memory
 compression region

This commit reserves memory resources associated with the memory
bandwidth compression functionality for Intel Integrated Graphics
Devices (IGD). The reservation is achieved by identifying the memory
region in the Resource Hand-Off Blocks (HOB) through a specific GUID,
provided in the FSP integration guide, and then marking it as
reserved. This ensures that the memory compression functionality can
operate without interference from other processes.

BUG=b:441695812
TEST=On a Fatcat device with the MemoryBandwidthCompression UPD set to
     1, coreboot logs show both the detection of the HOB and the related
     memory resource marked as reserved.

     [DEBUG]  Memory Compression HOB found: base=0x100000000
              length=0x02400000
     [...]
     [DEBUG]  19. 0000000100000000-00000001023fffff: RESERVED

Change-Id: I21f247dd8aaa88d4ae4da70eb78f7decc1793777
Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com>
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88909
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-by: Bora Guvendik <bora.guvendik@intel.corp-partner.google.com>
---
 .../intel/common/block/graphics/graphics.c    | 19 +++++++++++++++++++
 1 file changed, 19 insertions(+)

diff --git a/src/soc/intel/common/block/graphics/graphics.c b/src/soc/intel/common/block/graphics/graphics.c
index 9666c49f96..251483d18d 100644
--- a/src/soc/intel/common/block/graphics/graphics.c
+++ b/src/soc/intel/common/block/graphics/graphics.c
@@ -12,9 +12,19 @@
 #include <intelblocks/cfg.h>
 #include <intelblocks/graphics.h>
 #include <fsp/graphics.h>
+#include <fsp/util.h>
 #include <soc/pci_devs.h>
 #include <types.h>
 
+/*
+ * This GUID is used to identify memory resources related to the memory bandwidth
+ * compression functionality for Intel Integrated Graphics Devices (IGD).
+ */
+static const uint8_t memory_compression_guid[16] = {
+	0x79, 0x15, 0x9f, 0x8a, 0x72, 0xea, 0xb5, 0x4b,
+	0x90, 0x69, 0x54, 0x9a, 0x1b, 0xf7, 0xc4, 0xfd
+};
+
 /* Display Type:
 *  0 - only internal display aka eDP attached
 *  1 - only external display aka HDMI/USB-C attached
@@ -288,6 +298,15 @@ static void graphics_dev_read_resources(struct device *dev)
 		pci_dev_set_resources(dev);
 		res_bar0->flags |= IORESOURCE_FIXED;
 	}
+
+	const struct hob_resource *res =
+		fsp_find_resource_hob_by_guid(memory_compression_guid);
+	if (res) {
+		printk(BIOS_DEBUG,
+		       "Memory Compression HOB found: base=0x%08llx length=0x%08llx\n",
+		       res->addr, res->length);
+		reserved_ram_range(dev, 0, res->addr, res->length);
+	}
 }
 
 static void graphics_join_mbus(void)

From ebab858d92077dd6141712818449edf182884c56 Mon Sep 17 00:00:00 2001
From: Jeremy Compostella <jeremy.compostella@intel.com>
Date: Fri, 22 Aug 2025 14:39:14 -0700
Subject: [PATCH 1888/3886] soc/intel/pantherlake: Enable memory bandwidth
 compression for IGD

The commit enables memory bandwidth compression for Integrated Graphics
Device (IGD) when IGD is active. This change intends to improve graphics
performance.

BUG=b:431221875
TEST=On a Fatcat device, activating memory bandwidth compression leads
     to graphics performance improvements ranging from 20% to 65% on
     some graphics workloads.

Change-Id: Ia74fb6bac880a5eb9fe833f071bd129e69345d28
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88910
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Bora Guvendik <bora.guvendik@intel.corp-partner.google.com>
---
 src/soc/intel/pantherlake/romstage/fsp_params.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/soc/intel/pantherlake/romstage/fsp_params.c b/src/soc/intel/pantherlake/romstage/fsp_params.c
index 13401eb125..22f1ec2cc3 100644
--- a/src/soc/intel/pantherlake/romstage/fsp_params.c
+++ b/src/soc/intel/pantherlake/romstage/fsp_params.c
@@ -50,8 +50,8 @@ static void fill_fspm_igd_params(FSP_M_CONFIG *m_cfg,
 			*ddi_port_upds[i].hpd = !!(config->ddi_ports_config[i] &
 						   DDI_ENABLE_HPD);
 		}
-		/* Disable memory bandwidth compression */
-		m_cfg->MemoryBandwidthCompression = 0;
+		/* Enable memory bandwidth compression */
+		m_cfg->MemoryBandwidthCompression = 1;
 	} else {
 		/* IGD is disabled, skip IGD init in FSP. */
 		m_cfg->IgdDvmt50PreAlloc = 0;

From c2110e31611553fdc94b6d483fd7b259958712d7 Mon Sep 17 00:00:00 2001
From: Elyes Haouas <ehaouas@noos.fr>
Date: Wed, 5 Feb 2025 09:02:37 +0100
Subject: [PATCH 1889/3886] tree: Use true, false for PcieRpClkReqSupport

PcieRpClkReqSupport[] is a boolean, so use true/false.

Change-Id: I541ac5361dc0a929459edef7bb1f49c57b137c14
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86281
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/51nb/x210/devicetree.cb                |  6 +++---
 src/mainboard/acer/aspire_vn7_572g/devicetree.cb     |  8 ++++----
 src/mainboard/asrock/h110m/devicetree.cb             |  8 ++++----
 .../clevo/kbl-u/variants/n13xwu/devicetree.cb        |  8 ++++----
 src/mainboard/dell/optiplex_3050/devicetree.cb       |  6 +++---
 src/mainboard/facebook/monolith/devicetree.cb        |  6 +++---
 src/mainboard/google/eve/devicetree.cb               |  4 ++--
 .../google/fizz/variants/baseboard/devicetree.cb     | 12 ++++++------
 .../google/fizz/variants/endeavour/overridetree.cb   |  6 +++---
 src/mainboard/google/glados/devicetree.cb            |  2 +-
 .../google/poppy/variants/atlas/devicetree.cb        |  2 +-
 .../google/poppy/variants/baseboard/devicetree.cb    |  2 +-
 .../google/poppy/variants/nami/devicetree.cb         |  6 +++---
 .../google/poppy/variants/nautilus/devicetree.cb     |  2 +-
 .../google/poppy/variants/nocturne/devicetree.cb     |  4 ++--
 .../google/poppy/variants/rammus/devicetree.cb       |  2 +-
 .../google/poppy/variants/soraka/devicetree.cb       |  2 +-
 .../intel/kblrvp/variants/rvp11/overridetree.cb      | 12 ++++++------
 .../intel/kblrvp/variants/rvp3/overridetree.cb       | 10 +++++-----
 .../intel/kblrvp/variants/rvp7/overridetree.cb       | 10 +++++-----
 .../intel/kblrvp/variants/rvp8/overridetree.cb       |  8 ++++----
 src/mainboard/intel/kunimitsu/devicetree.cb          |  4 ++--
 src/mainboard/intel/saddlebrook/devicetree.cb        |  8 ++++----
 .../sklkbl_thinkpad/variants/t480/overridetree.cb    | 10 +++++-----
 .../sklkbl_thinkpad/variants/t480s/overridetree.cb   | 10 +++++-----
 src/mainboard/protectli/vault_kbl/devicetree.cb      |  2 +-
 .../librem_skl/variants/librem15/overridetree.cb     |  2 +-
 .../starlabs/starbook/variants/kbl/devicetree.cb     |  4 ++--
 src/mainboard/system76/kbl-u/devicetree.cb           |  8 ++++----
 29 files changed, 87 insertions(+), 87 deletions(-)

diff --git a/src/mainboard/51nb/x210/devicetree.cb b/src/mainboard/51nb/x210/devicetree.cb
index a2e08bf862..35cb0fef4c 100644
--- a/src/mainboard/51nb/x210/devicetree.cb
+++ b/src/mainboard/51nb/x210/devicetree.cb
@@ -89,7 +89,7 @@ chip soc/intel/skylake
 		end
 		device ref pcie_rp3	on
 			# Ethernet controller
-			register "PcieRpClkReqSupport[2]" = "1"
+			register "PcieRpClkReqSupport[2]" = "true"
 			register "PcieRpClkReqNumber[2]" = "0"
 			register "PcieRpClkSrcNumber[2]" = "0"
 			register "PcieRpAdvancedErrorReporting[2]" = "1"
@@ -97,7 +97,7 @@ chip soc/intel/skylake
 		end
 		device ref pcie_rp4	on
 			# Wireless controller
-			register "PcieRpClkReqSupport[3]" = "1"
+			register "PcieRpClkReqSupport[3]" = "true"
 			register "PcieRpClkReqNumber[3]" = "1"
 			register "PcieRpClkSrcNumber[3]" = "1"
 			register "PcieRpAdvancedErrorReporting[3]" = "1"
@@ -105,7 +105,7 @@ chip soc/intel/skylake
 		end
 		device ref pcie_rp9	on
 			# NVMe controller
-			register "PcieRpClkReqSupport[8]" = "1"
+			register "PcieRpClkReqSupport[8]" = "true"
 			register "PcieRpClkReqNumber[8]" = "4"
 			register "PcieRpClkSrcNumber[8]" = "4"
 			register "PcieRpAdvancedErrorReporting[8]" = "1"
diff --git a/src/mainboard/acer/aspire_vn7_572g/devicetree.cb b/src/mainboard/acer/aspire_vn7_572g/devicetree.cb
index f308894c5b..ea23fe56e6 100644
--- a/src/mainboard/acer/aspire_vn7_572g/devicetree.cb
+++ b/src/mainboard/acer/aspire_vn7_572g/devicetree.cb
@@ -253,7 +253,7 @@ chip soc/intel/skylake
 			# dGPU; x4
 			register "PcieRpAdvancedErrorReporting[0]" = "1"
 			register "PcieRpLtrEnable[0]" = "true"
-			register "PcieRpClkReqSupport[0]" = "1"
+			register "PcieRpClkReqSupport[0]" = "true"
 			register "PcieRpClkReqNumber[0]" = "0"
 			register "PcieRpMaxPayload[0]" = "RpMaxPayload_256"
 		end
@@ -261,7 +261,7 @@ chip soc/intel/skylake
 			# NGFF; x2
 			register "PcieRpAdvancedErrorReporting[6]" = "1"
 			register "PcieRpLtrEnable[6]" = "true"
-			register "PcieRpClkReqSupport[6]" = "1"
+			register "PcieRpClkReqSupport[6]" = "true"
 			register "PcieRpClkReqNumber[6]" = "3"
 			register "PcieRpMaxPayload[6]" = "RpMaxPayload_256"
 		end
@@ -269,7 +269,7 @@ chip soc/intel/skylake
 			# LAN
 			register "PcieRpAdvancedErrorReporting[8]" = "1"
 			register "PcieRpLtrEnable[8]" = "true"
-			register "PcieRpClkReqSupport[8]" = "1"
+			register "PcieRpClkReqSupport[8]" = "true"
 			register "PcieRpClkReqNumber[8]" = "1"
 			register "PcieRpMaxPayload[8]" = "RpMaxPayload_256"
 		end
@@ -277,7 +277,7 @@ chip soc/intel/skylake
 			# WLAN
 			register "PcieRpAdvancedErrorReporting[9]" = "1"
 			register "PcieRpLtrEnable[9]" = "true"
-			register "PcieRpClkReqSupport[9]" = "1"
+			register "PcieRpClkReqSupport[9]" = "true"
 			register "PcieRpClkReqNumber[9]" = "2"
 			register "PcieRpMaxPayload[9]" = "RpMaxPayload_256"
 			# ASPM L0s is broken/unsupported on Qualcomm Atheros QCA6174 (AER: corrected errors)
diff --git a/src/mainboard/asrock/h110m/devicetree.cb b/src/mainboard/asrock/h110m/devicetree.cb
index 9be53d7b7d..1a7dc62846 100644
--- a/src/mainboard/asrock/h110m/devicetree.cb
+++ b/src/mainboard/asrock/h110m/devicetree.cb
@@ -50,7 +50,7 @@ chip soc/intel/skylake
 			register "Peg0MaxLinkWidth" = "Peg0_x16"
 
 			# Configure PCIe clockgen in PCH
-			register "PcieRpClkReqSupport[0]"	= "1"
+			register "PcieRpClkReqSupport[0]"	= "true"
 			register "PcieRpClkReqNumber[0]"	= "0"
 			register "PcieRpClkSrcNumber[0]"	= "0"
 		end
@@ -113,7 +113,7 @@ chip soc/intel/skylake
 		end
 		device ref pcie_rp1	on	end
 		device ref pcie_rp5	on
-			register "PcieRpClkReqSupport[4]"		= "1"
+			register "PcieRpClkReqSupport[4]"		= "true"
 			register "PcieRpClkReqNumber[4]"		= "2"
 			register "PcieRpAdvancedErrorReporting[4]"	= "1"
 			register "PcieRpLtrEnable[4]"			= "true"
@@ -123,13 +123,13 @@ chip soc/intel/skylake
 		device ref pcie_rp6	on
 
 			# Disable CLKREQ#, since onboard LAN is always present
-			register "PcieRpClkReqSupport[5]"		= "0"
+			register "PcieRpClkReqSupport[5]"		= "false"
 			register "PcieRpAdvancedErrorReporting[5]"	= "1"
 			register "PcieRpLtrEnable[5]"			= "true"
 			register "PcieRpClkSrcNumber[5]"		= "1"
 		end
 		device ref pcie_rp7	on
-			register "PcieRpClkReqSupport[6]"		= "1"
+			register "PcieRpClkReqSupport[6]"		= "true"
 			register "PcieRpClkReqNumber[6]"		= "3"
 			register "PcieRpAdvancedErrorReporting[6]"	= "1"
 			register "PcieRpLtrEnable[6]"			= "true"
diff --git a/src/mainboard/clevo/kbl-u/variants/n13xwu/devicetree.cb b/src/mainboard/clevo/kbl-u/variants/n13xwu/devicetree.cb
index 54c59ddf40..7494c6cb43 100644
--- a/src/mainboard/clevo/kbl-u/variants/n13xwu/devicetree.cb
+++ b/src/mainboard/clevo/kbl-u/variants/n13xwu/devicetree.cb
@@ -66,7 +66,7 @@ chip soc/intel/skylake
 		device ref uart2	on	end
 		device ref pcie_rp1	on
 			device pci 00.0 on end # x4 TBT
-			register "PcieRpClkReqSupport[0]" = "1"
+			register "PcieRpClkReqSupport[0]" = "true"
 			register "PcieRpClkReqNumber[0]" = "4"
 			register "PcieRpClkSrcNumber[0]" = "4"
 			register "PcieRpHotPlug[0]" = "1"
@@ -75,14 +75,14 @@ chip soc/intel/skylake
 		end
 		device ref pcie_rp5	on
 			device pci 00.0 on end # x1 LAN
-			register "PcieRpClkReqSupport[4]" = "1"
+			register "PcieRpClkReqSupport[4]" = "true"
 			register "PcieRpClkReqNumber[4]" = "3"
 			register "PcieRpClkSrcNumber[4]" = "3"
 			register "PcieRpLtrEnable[4]" = "true"
 		end
 		device ref pcie_rp6	on
 			device pci 00.0 on end # x1 WLAN
-			register "PcieRpClkReqSupport[5]" = "1"
+			register "PcieRpClkReqSupport[5]" = "true"
 			register "PcieRpClkReqNumber[5]" = "2"
 			register "PcieRpClkSrcNumber[5]" = "2"
 			register "PcieRpLtrEnable[5]" = "true"
@@ -90,7 +90,7 @@ chip soc/intel/skylake
 		end
 		device ref pcie_rp9	on
 			device pci 00.0 on end # x4 M.2/M (J_SSD1)
-			register "PcieRpClkReqSupport[8]" = "1"
+			register "PcieRpClkReqSupport[8]" = "true"
 			register "PcieRpClkReqNumber[8]" = "5"
 			register "PcieRpClkSrcNumber[8]" = "5"
 			register "PcieRpLtrEnable[8]" = "true"
diff --git a/src/mainboard/dell/optiplex_3050/devicetree.cb b/src/mainboard/dell/optiplex_3050/devicetree.cb
index 0d2adff74a..dda5583a16 100644
--- a/src/mainboard/dell/optiplex_3050/devicetree.cb
+++ b/src/mainboard/dell/optiplex_3050/devicetree.cb
@@ -39,7 +39,7 @@ chip soc/intel/skylake
 
 		# M.2 SSD
 		device ref pcie_rp21 on
-			register "PcieRpClkReqSupport[20]"              = "1"
+			register "PcieRpClkReqSupport[20]"              = "true"
 			register "PcieRpClkReqNumber[20]"               = "3"
 			register "PcieRpAdvancedErrorReporting[20]"     = "1"
 			register "PcieRpLtrEnable[20]"                  = "true"
@@ -49,13 +49,13 @@ chip soc/intel/skylake
 
 		# Realtek LAN
 		device ref pcie_rp5 on
-			register "PcieRpClkReqSupport[4]"		= "0"
+			register "PcieRpClkReqSupport[4]"		= "false"
 			register "PcieRpHotPlug[4]"			= "0"
 		end
 
 		# M.2 WiFi
 		device ref pcie_rp8 on
-			register "PcieRpClkReqSupport[7]"		= "0"
+			register "PcieRpClkReqSupport[7]"		= "false"
 			register "PcieRpHotPlug[7]"			= "1"
 		end
 
diff --git a/src/mainboard/facebook/monolith/devicetree.cb b/src/mainboard/facebook/monolith/devicetree.cb
index 6cacba505a..2ad39a3eea 100644
--- a/src/mainboard/facebook/monolith/devicetree.cb
+++ b/src/mainboard/facebook/monolith/devicetree.cb
@@ -157,7 +157,7 @@ chip soc/intel/skylake
 		device ref pcie_rp3	on
 			# x1 baseboard WWAN
 			# PCIE Port 3 x1 -> Module x1 : Mapped to PCIe 2 on the baseboard
-			register "PcieRpClkReqSupport[2]" = "0"
+			register "PcieRpClkReqSupport[2]" = "false"
 			register "PcieRpMaxPayload[2]" = "RpMaxPayload_256"
 			register "PcieRpLtrEnable[2]" = "true"
 			register "PcieRpAdvancedErrorReporting[2]" = "1"
@@ -166,7 +166,7 @@ chip soc/intel/skylake
 		device ref pcie_rp6	on
 			# x1 baseboard i210
 			# PCIE Port 6 x1 -> BASEBOARD x1 i210 : Mapped to PCIe 4 on the baseboard
-			register "PcieRpClkReqSupport[5]" = "0"
+			register "PcieRpClkReqSupport[5]" = "false"
 			register "PcieRpMaxPayload[5]" = "RpMaxPayload_256"
 			register "PcieRpLtrEnable[5]" = "true"
 			register "PcieRpAdvancedErrorReporting[5]" = "1"
@@ -175,7 +175,7 @@ chip soc/intel/skylake
 		device ref pcie_rp9	on
 			# x4 FPGA
 			# PCIE Port 9 x4 -> BASEBOARD PEG0-3 FPGA
-			register "PcieRpClkReqSupport[8]" = "0"
+			register "PcieRpClkReqSupport[8]" = "false"
 			register "PcieRpHotPlug[8]" = "1"
 			register "PcieRpMaxPayload[8]" = "RpMaxPayload_256"
 			register "PcieRpLtrEnable[8]" = "true"
diff --git a/src/mainboard/google/eve/devicetree.cb b/src/mainboard/google/eve/devicetree.cb
index 15e2ff6095..41c5cb0377 100644
--- a/src/mainboard/google/eve/devicetree.cb
+++ b/src/mainboard/google/eve/devicetree.cb
@@ -336,7 +336,7 @@ chip soc/intel/skylake
 			end
 		end # I2C #4
 		device ref pcie_rp1	on
-			register "PcieRpClkReqSupport[0]" = "1"
+			register "PcieRpClkReqSupport[0]" = "true"
 			register "PcieRpClkReqNumber[0]" = "1"
 			register "PcieRpAdvancedErrorReporting[0]" = "1"
 			register "PcieRpLtrEnable[0]" = "true"
@@ -348,7 +348,7 @@ chip soc/intel/skylake
 			end
 		end
 		device ref pcie_rp5	on
-			register "PcieRpClkReqSupport[4]" = "1"
+			register "PcieRpClkReqSupport[4]" = "true"
 			register "PcieRpClkReqNumber[4]" = "4"
 			register "PcieRpAdvancedErrorReporting[4]" = "1"
 			register "PcieRpLtrEnable[4]" = "true"
diff --git a/src/mainboard/google/fizz/variants/baseboard/devicetree.cb b/src/mainboard/google/fizz/variants/baseboard/devicetree.cb
index 8cf8d27da6..4a6d058d59 100644
--- a/src/mainboard/google/fizz/variants/baseboard/devicetree.cb
+++ b/src/mainboard/google/fizz/variants/baseboard/devicetree.cb
@@ -289,7 +289,7 @@ chip soc/intel/skylake
 		device ref pcie_rp3	on
 			# LAN, will be swapped to port 1 by FSP
 			# x1
-			register "PcieRpClkReqSupport[2]" = "1"
+			register "PcieRpClkReqSupport[2]" = "true"
 			register "PcieRpClkReqNumber[2]" = "0"
 			register "PcieRpAdvancedErrorReporting[2]" = "1"
 			register "PcieRpLtrEnable[2]" = "true"
@@ -303,7 +303,7 @@ chip soc/intel/skylake
 		end
 		device ref pcie_rp4	on
 			# x1 WLAN
-			register "PcieRpClkReqSupport[3]" = "1"
+			register "PcieRpClkReqSupport[3]" = "true"
 			register "PcieRpClkReqNumber[3]" = "5"
 			register "PcieRpAdvancedErrorReporting[3]" = "1"
 			register "PcieRpLtrEnable[3]" = "true"
@@ -315,7 +315,7 @@ chip soc/intel/skylake
 		end
 		device ref pcie_rp5	on
 			# x4 NVMe
-			register "PcieRpClkReqSupport[4]" = "1"
+			register "PcieRpClkReqSupport[4]" = "true"
 			register "PcieRpClkReqNumber[4]" = "1"
 			register "PcieRpAdvancedErrorReporting[4]" = "1"
 			register "PcieRpLtrEnable[4]" = "true"
@@ -323,7 +323,7 @@ chip soc/intel/skylake
 		end
 		device ref pcie_rp9	on
 			# 2nd LAN
-			register "PcieRpClkReqSupport[8]" = "1"
+			register "PcieRpClkReqSupport[8]" = "true"
 			register "PcieRpClkReqNumber[8]" = "2"
 			register "PcieRpAdvancedErrorReporting[8]" = "1"
 			register "PcieRpLtrEnable[8]" = "true"
@@ -335,14 +335,14 @@ chip soc/intel/skylake
 			end
 		end
 		device ref pcie_rp11	on
-			register "PcieRpClkReqSupport[10]" = "1"
+			register "PcieRpClkReqSupport[10]" = "true"
 			register "PcieRpClkReqNumber[10]" = "2"
 			register "PcieRpAdvancedErrorReporting[10]" = "1"
 			register "PcieRpLtrEnable[10]" = "true"
 			register "PcieRpClkSrcNumber[10]" = "2"
 		end
 		device ref pcie_rp12	on
-			register "PcieRpClkReqSupport[11]" = "1"
+			register "PcieRpClkReqSupport[11]" = "true"
 			register "PcieRpClkReqNumber[11]" = "2"
 			register "PcieRpAdvancedErrorReporting[11]" = "1"
 			register "PcieRpLtrEnable[11]" = "true"
diff --git a/src/mainboard/google/fizz/variants/endeavour/overridetree.cb b/src/mainboard/google/fizz/variants/endeavour/overridetree.cb
index 8421ae477e..05e17bf0b3 100644
--- a/src/mainboard/google/fizz/variants/endeavour/overridetree.cb
+++ b/src/mainboard/google/fizz/variants/endeavour/overridetree.cb
@@ -116,7 +116,7 @@ chip soc/intel/skylake
 		end
 		device ref pcie_rp7 on
 			# x1 TPU1
-			register "PcieRpClkReqSupport[6]" = "1"
+			register "PcieRpClkReqSupport[6]" = "true"
 			register "PcieRpClkReqNumber[6]" = "4"
 			register "PcieRpAdvancedErrorReporting[6]" = "1"
 			register "PcieRpLtrEnable[6]" = "true"
@@ -124,7 +124,7 @@ chip soc/intel/skylake
 		end
 		device ref pcie_rp8 on
 			# x1 TPU0
-			register "PcieRpClkReqSupport[7]" = "1"
+			register "PcieRpClkReqSupport[7]" = "true"
 			register "PcieRpClkReqNumber[7]" = "2"
 			register "PcieRpAdvancedErrorReporting[7]" = "1"
 			register "PcieRpLtrEnable[7]" = "true"
@@ -132,7 +132,7 @@ chip soc/intel/skylake
 		end
 		device ref pcie_rp9 on
 			# x4 i350 LAN
-			register "PcieRpClkReqSupport[8]" = "0"
+			register "PcieRpClkReqSupport[8]" = "false"
 			register "PcieRpAdvancedErrorReporting[8]" = "1"
 			register "PcieRpLtrEnable[8]" = "true"
 			register "PcieRpClkSrcNumber[8]" = "2"
diff --git a/src/mainboard/google/glados/devicetree.cb b/src/mainboard/google/glados/devicetree.cb
index 5bbcd2cf17..bfae974feb 100644
--- a/src/mainboard/google/glados/devicetree.cb
+++ b/src/mainboard/google/glados/devicetree.cb
@@ -78,7 +78,7 @@ chip soc/intel/skylake
 		device ref uart2	on  end
 		device ref i2c4		on  end
 		device ref pcie_rp1	on
-			register "PcieRpClkReqSupport[0]" = "1"
+			register "PcieRpClkReqSupport[0]" = "true"
 			register "PcieRpClkReqNumber[0]" = "1"
 			chip drivers/wifi/generic
 				register "wake" = "GPE0_DW0_16"
diff --git a/src/mainboard/google/poppy/variants/atlas/devicetree.cb b/src/mainboard/google/poppy/variants/atlas/devicetree.cb
index 0ef59f8a91..b9e18becb4 100644
--- a/src/mainboard/google/poppy/variants/atlas/devicetree.cb
+++ b/src/mainboard/google/poppy/variants/atlas/devicetree.cb
@@ -310,7 +310,7 @@ chip soc/intel/skylake
 		end
 		device ref pcie_rp1		on
 			# WLAN
-			register "PcieRpClkReqSupport[0]" = "1"
+			register "PcieRpClkReqSupport[0]" = "true"
 			register "PcieRpClkReqNumber[0]" = "1"
 			register "PcieRpClkSrcNumber[0]" = "1"
 			register "PcieRpAdvancedErrorReporting[0]" = "1"
diff --git a/src/mainboard/google/poppy/variants/baseboard/devicetree.cb b/src/mainboard/google/poppy/variants/baseboard/devicetree.cb
index 5bc4bdce00..f3c30c5437 100644
--- a/src/mainboard/google/poppy/variants/baseboard/devicetree.cb
+++ b/src/mainboard/google/poppy/variants/baseboard/devicetree.cb
@@ -323,7 +323,7 @@ chip soc/intel/skylake
 		end
 		device ref i2c4			on end
 		device ref pcie_rp1		on
-			register "PcieRpClkReqSupport[0]" = "1"
+			register "PcieRpClkReqSupport[0]" = "true"
 			register "PcieRpClkReqNumber[0]" = "1"
 			register "PcieRpAdvancedErrorReporting[0]" = "1"
 			register "PcieRpLtrEnable[0]" = "true"
diff --git a/src/mainboard/google/poppy/variants/nami/devicetree.cb b/src/mainboard/google/poppy/variants/nami/devicetree.cb
index 2e7726ec1d..942e1459a8 100644
--- a/src/mainboard/google/poppy/variants/nami/devicetree.cb
+++ b/src/mainboard/google/poppy/variants/nami/devicetree.cb
@@ -366,7 +366,7 @@ chip soc/intel/skylake
 		device ref pcie_rp1		on  end
 		device ref pcie_rp4		on
 			# x1
-			register "PcieRpClkReqSupport[3]" = "1"
+			register "PcieRpClkReqSupport[3]" = "true"
 			register "PcieRpClkReqNumber[3]" = "1"
 			register "PcieRpClkSrcNumber[3]" = "1"
 			register "PcieRpAdvancedErrorReporting[3]" = "1"
@@ -378,7 +378,7 @@ chip soc/intel/skylake
 		end
 		device ref pcie_rp5		on
 			# x4
-			register "PcieRpClkReqSupport[4]" = "1"
+			register "PcieRpClkReqSupport[4]" = "true"
 			register "PcieRpClkReqNumber[4]" = "3"
 			register "PcieRpClkSrcNumber[4]" = "3"
 			register "PcieRpAdvancedErrorReporting[4]" = "1"
@@ -386,7 +386,7 @@ chip soc/intel/skylake
 		end
 		device ref pcie_rp9		on
 			# x2
-			register "PcieRpClkReqSupport[8]" = "1"
+			register "PcieRpClkReqSupport[8]" = "true"
 			register "PcieRpClkReqNumber[8]" = "2"
 			register "PcieRpClkSrcNumber[8]" = "2"
 			register "PcieRpAdvancedErrorReporting[8]" = "1"
diff --git a/src/mainboard/google/poppy/variants/nautilus/devicetree.cb b/src/mainboard/google/poppy/variants/nautilus/devicetree.cb
index b226e6b6a6..610301524f 100644
--- a/src/mainboard/google/poppy/variants/nautilus/devicetree.cb
+++ b/src/mainboard/google/poppy/variants/nautilus/devicetree.cb
@@ -361,7 +361,7 @@ chip soc/intel/skylake
 			end
 		end
 		device ref pcie_rp1		on
-			register "PcieRpClkReqSupport[0]" = "1"
+			register "PcieRpClkReqSupport[0]" = "true"
 			register "PcieRpClkReqNumber[0]" = "1"
 			register "PcieRpClkSrcNumber[0]" = "1"
 			register "PcieRpAdvancedErrorReporting[0]" = "1"
diff --git a/src/mainboard/google/poppy/variants/nocturne/devicetree.cb b/src/mainboard/google/poppy/variants/nocturne/devicetree.cb
index fd95a61b45..d5149d85a1 100644
--- a/src/mainboard/google/poppy/variants/nocturne/devicetree.cb
+++ b/src/mainboard/google/poppy/variants/nocturne/devicetree.cb
@@ -325,7 +325,7 @@ chip soc/intel/skylake
 			end
 		end
 		device ref pcie_rp1		on
-			register "PcieRpClkReqSupport[0]" = "1"
+			register "PcieRpClkReqSupport[0]" = "true"
 			register "PcieRpClkReqNumber[0]" = "1"
 			register "PcieRpClkSrcNumber[0]" = "1"
 			register "PcieRpAdvancedErrorReporting[0]" = "1"
@@ -337,7 +337,7 @@ chip soc/intel/skylake
 		end
 		device ref pcie_rp9		on
 			# x2
-			register "PcieRpClkReqSupport[8]" = "1"
+			register "PcieRpClkReqSupport[8]" = "true"
 			register "PcieRpClkReqNumber[8]" = "2"
 			register "PcieRpClkSrcNumber[8]" = "3"
 			register "PcieRpAdvancedErrorReporting[8]" = "1"
diff --git a/src/mainboard/google/poppy/variants/rammus/devicetree.cb b/src/mainboard/google/poppy/variants/rammus/devicetree.cb
index a84e45748c..ebf086d032 100644
--- a/src/mainboard/google/poppy/variants/rammus/devicetree.cb
+++ b/src/mainboard/google/poppy/variants/rammus/devicetree.cb
@@ -314,7 +314,7 @@ chip soc/intel/skylake
 			end
 		end
 		device ref pcie_rp1		on
-			register "PcieRpClkReqSupport[0]" = "1"
+			register "PcieRpClkReqSupport[0]" = "true"
 			register "PcieRpClkReqNumber[0]" = "1"
 			register "PcieRpClkSrcNumber[0]" = "1"
 			register "PcieRpAdvancedErrorReporting[0]" = "1"
diff --git a/src/mainboard/google/poppy/variants/soraka/devicetree.cb b/src/mainboard/google/poppy/variants/soraka/devicetree.cb
index 29d6974bc1..c5370e9350 100644
--- a/src/mainboard/google/poppy/variants/soraka/devicetree.cb
+++ b/src/mainboard/google/poppy/variants/soraka/devicetree.cb
@@ -305,7 +305,7 @@ chip soc/intel/skylake
 		end
 		device ref i2c4			on  end
 		device ref pcie_rp1		on
-			register "PcieRpClkReqSupport[0]" = "1"
+			register "PcieRpClkReqSupport[0]" = "true"
 			register "PcieRpClkReqNumber[0]" = "1"
 			register "PcieRpAdvancedErrorReporting[0]" = "1"
 			register "PcieRpLtrEnable[0]" = "true"
diff --git a/src/mainboard/intel/kblrvp/variants/rvp11/overridetree.cb b/src/mainboard/intel/kblrvp/variants/rvp11/overridetree.cb
index cc3d9555be..95787c3914 100644
--- a/src/mainboard/intel/kblrvp/variants/rvp11/overridetree.cb
+++ b/src/mainboard/intel/kblrvp/variants/rvp11/overridetree.cb
@@ -75,32 +75,32 @@ chip soc/intel/skylake
 		end
 		device ref i2c4		off end
 		device ref pcie_rp6	on
-			register "PcieRpClkReqSupport[5]" = "1"
+			register "PcieRpClkReqSupport[5]" = "true"
 			register "PcieRpClkReqNumber[5]" = "1"
 			register "PcieRpClkSrcNumber[5]" = "1"
 		end
 		device ref pcie_rp7	on
-			register "PcieRpClkReqSupport[6]" = "1"
+			register "PcieRpClkReqSupport[6]" = "true"
 			register "PcieRpClkReqNumber[6]" = "2"
 			register "PcieRpClkSrcNumber[6]" = "2"
 		end
 		device ref pcie_rp8	on
-			register "PcieRpClkReqSupport[7]" = "1"
+			register "PcieRpClkReqSupport[7]" = "true"
 			register "PcieRpClkReqNumber[7]" = "3"
 			register "PcieRpClkSrcNumber[7]" = "3"
 		end
 		device ref pcie_rp9	on
-			register "PcieRpClkReqSupport[8]" = "1"
+			register "PcieRpClkReqSupport[8]" = "true"
 			register "PcieRpClkReqNumber[8]" = "4"
 			register "PcieRpClkSrcNumber[8]" = "4"
 		end
 		device ref pcie_rp14	on
-			register "PcieRpClkReqSupport[13]" = "1"
+			register "PcieRpClkReqSupport[13]" = "true"
 			register "PcieRpClkReqNumber[13]" = "5"
 			register "PcieRpClkSrcNumber[13]" = "5"
 		end
 		device ref pcie_rp17	on
-			register "PcieRpClkReqSupport[16]" = "1"
+			register "PcieRpClkReqSupport[16]" = "true"
 			register "PcieRpClkReqNumber[16]" = "7"
 			register "PcieRpClkSrcNumber[16]" = "7"
 		end
diff --git a/src/mainboard/intel/kblrvp/variants/rvp3/overridetree.cb b/src/mainboard/intel/kblrvp/variants/rvp3/overridetree.cb
index 93e62e2776..0d9695b8f7 100644
--- a/src/mainboard/intel/kblrvp/variants/rvp3/overridetree.cb
+++ b/src/mainboard/intel/kblrvp/variants/rvp3/overridetree.cb
@@ -77,31 +77,31 @@ chip soc/intel/skylake
 		device ref cio		on  end
 		device ref pcie_rp1	on
 			# PCIE x4 -> SLOT1
-			register "PcieRpClkReqSupport[0]" = "1"
+			register "PcieRpClkReqSupport[0]" = "true"
 			register "PcieRpClkReqNumber[0]" = "2"
 			register "PcieRpClkSrcNumber[0]" = "2"
 		end
 		device ref pcie_rp5	on
 			# PCIE x1 -> SLOT2/LAN
-			register "PcieRpClkReqSupport[4]" = "1"
+			register "PcieRpClkReqSupport[4]" = "true"
 			register "PcieRpClkReqNumber[4]" = "3"
 			register "PcieRpClkSrcNumber[4]" = "3"
 		end
 		device ref pcie_rp6	on
 			# PCIE x1 -> SLOT3
-			register "PcieRpClkReqSupport[5]" = "1"
+			register "PcieRpClkReqSupport[5]" = "true"
 			register "PcieRpClkReqNumber[5]" = "1"
 			register "PcieRpClkSrcNumber[5]" = "1"
 		end
 		device ref pcie_rp9	on
 			# PCIE x1 -> WLAN
-			register "PcieRpClkReqSupport[8]" = "1"
+			register "PcieRpClkReqSupport[8]" = "true"
 			register "PcieRpClkReqNumber[8]" = "5"
 			register "PcieRpClkSrcNumber[8]" = "5"
 		end
 		device ref pcie_rp10	on
 			# PCIE x1 -> WiGig
-			register "PcieRpClkReqSupport[9]" = "1"
+			register "PcieRpClkReqSupport[9]" = "true"
 			register "PcieRpClkReqNumber[9]" = "4"
 			register "PcieRpClkSrcNumber[9]" = "4"
 		end
diff --git a/src/mainboard/intel/kblrvp/variants/rvp7/overridetree.cb b/src/mainboard/intel/kblrvp/variants/rvp7/overridetree.cb
index a5d30d3640..96ddbb7b91 100644
--- a/src/mainboard/intel/kblrvp/variants/rvp7/overridetree.cb
+++ b/src/mainboard/intel/kblrvp/variants/rvp7/overridetree.cb
@@ -124,27 +124,27 @@ chip soc/intel/skylake
 			}"
 		end
 		device ref pcie_rp3	on
-			register "PcieRpClkReqSupport[2]" = "1"
+			register "PcieRpClkReqSupport[2]" = "true"
 			register "PcieRpClkReqNumber[2]" = "5"
 			register "PcieRpClkSrcNumber[2]" = "5"
 		end
 		device ref pcie_rp4	on
-			register "PcieRpClkReqSupport[3]" = "1"
+			register "PcieRpClkReqSupport[3]" = "true"
 			register "PcieRpClkReqNumber[3]" = "2"
 			register "PcieRpClkSrcNumber[3]" = "2"
 		end
 		device ref pcie_rp5	on
-			register "PcieRpClkReqSupport[4]" = "1"
+			register "PcieRpClkReqSupport[4]" = "true"
 			register "PcieRpClkReqNumber[4]" = "3"
 			register "PcieRpClkSrcNumber[4]" = "3"
 		end
 		device ref pcie_rp6	on
-			register "PcieRpClkReqSupport[5]" = "1"
+			register "PcieRpClkReqSupport[5]" = "true"
 			register "PcieRpClkReqNumber[5]" = "4"
 			register "PcieRpClkSrcNumber[5]" = "4"
 		end
 		device ref pcie_rp9	on
-			register "PcieRpClkReqSupport[8]" = "1"
+			register "PcieRpClkReqSupport[8]" = "true"
 			register "PcieRpClkReqNumber[8]" = "1"
 			register "PcieRpClkSrcNumber[8]" = "1"
 		end
diff --git a/src/mainboard/intel/kblrvp/variants/rvp8/overridetree.cb b/src/mainboard/intel/kblrvp/variants/rvp8/overridetree.cb
index 2d8a9c1263..397205eec1 100644
--- a/src/mainboard/intel/kblrvp/variants/rvp8/overridetree.cb
+++ b/src/mainboard/intel/kblrvp/variants/rvp8/overridetree.cb
@@ -148,19 +148,19 @@ chip soc/intel/skylake
 		device ref pcie_rp1	off end
 		device ref pcie_rp3	on  end
 		device ref pcie_rp4	on
-			register "PcieRpClkReqSupport[3]" = "1"
+			register "PcieRpClkReqSupport[3]" = "true"
 			register "PcieRpClkReqNumber[3]" = "2"
 		end
 		device ref pcie_rp5	on
-			register "PcieRpClkReqSupport[4]" = "1"
+			register "PcieRpClkReqSupport[4]" = "true"
 			register "PcieRpClkReqNumber[4]" = "1"
 		end
 		device ref pcie_rp9	on
-			register "PcieRpClkReqSupport[8]" = "1"
+			register "PcieRpClkReqSupport[8]" = "true"
 			register "PcieRpClkReqNumber[8]" = "6"
 		end
 		device ref pcie_rp17	on
-			register "PcieRpClkReqSupport[16]" = "1"
+			register "PcieRpClkReqSupport[16]" = "true"
 			register "PcieRpClkReqNumber[16]" = "7"
 		end
 		device ref emmc		off end
diff --git a/src/mainboard/intel/kunimitsu/devicetree.cb b/src/mainboard/intel/kunimitsu/devicetree.cb
index c52b290d93..bde6d5690e 100644
--- a/src/mainboard/intel/kunimitsu/devicetree.cb
+++ b/src/mainboard/intel/kunimitsu/devicetree.cb
@@ -210,7 +210,7 @@ chip soc/intel/skylake
 			end
 		end
 		device ref pcie_rp1	on
-			register "PcieRpClkReqSupport[0]" = "1"
+			register "PcieRpClkReqSupport[0]" = "true"
 			register "PcieRpClkReqNumber[0]" = "1"
 			chip drivers/wifi/generic
 				register "wake" = "GPE0_DW0_16"
@@ -218,7 +218,7 @@ chip soc/intel/skylake
 			end
 		end
 		device ref pcie_rp5	on
-			register "PcieRpClkReqSupport[4]" = "1"
+			register "PcieRpClkReqSupport[4]" = "true"
 			register "PcieRpClkReqNumber[4]" = "2"
 		end
 		device ref uart0	on end
diff --git a/src/mainboard/intel/saddlebrook/devicetree.cb b/src/mainboard/intel/saddlebrook/devicetree.cb
index b6000910e7..370ab6d6b1 100644
--- a/src/mainboard/intel/saddlebrook/devicetree.cb
+++ b/src/mainboard/intel/saddlebrook/devicetree.cb
@@ -186,21 +186,21 @@ chip soc/intel/skylake
 		device ref i2c4		on end
 		device ref pcie_rp1	on end
 		device ref pcie_rp6	on
-			register "PcieRpClkReqSupport[5]" = "1"
+			register "PcieRpClkReqSupport[5]" = "true"
 			register "PcieRpClkReqNumber[5]" = "0"
 		end
 		device ref pcie_rp8	on
 			# x1
-			register "PcieRpClkReqSupport[7]" = "1"
+			register "PcieRpClkReqSupport[7]" = "true"
 			register "PcieRpClkReqNumber[7]" = "3"
 		end
 		device ref pcie_rp9	on
 			# x4
-			register "PcieRpClkReqSupport[8]" = "1"
+			register "PcieRpClkReqSupport[8]" = "true"
 			register "PcieRpClkReqNumber[8]" = "4"
 		end
 		device ref pcie_rp13	on
-			register "PcieRpClkReqSupport[12]" = "1"
+			register "PcieRpClkReqSupport[12]" = "true"
 			register "PcieRpClkReqNumber[12]" = "1"
 		end
 		device ref uart0	on end
diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480/overridetree.cb b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480/overridetree.cb
index 9acb823c10..14cbb7a050 100644
--- a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480/overridetree.cb
+++ b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480/overridetree.cb
@@ -37,7 +37,7 @@ chip soc/intel/skylake
 
 		# dGPU - x4
 		device ref pcie_rp1 on
-			register "PcieRpClkReqSupport[0]"		= "1"
+			register "PcieRpClkReqSupport[0]"		= "true"
 			register "PcieRpClkReqNumber[0]"		= "0"
 			register "PcieRpClkSrcNumber[0]"		= "0"
 			register "PcieRpAdvancedErrorReporting[0]"	= "1"
@@ -55,7 +55,7 @@ chip soc/intel/skylake
 
 		# M.2 WLAN - x1
 		device ref pcie_rp7 on
-			register "PcieRpClkReqSupport[6]"		= "1"
+			register "PcieRpClkReqSupport[6]"		= "true"
 			register "PcieRpClkReqNumber[6]"		= "2"
 			register "PcieRpClkSrcNumber[6]"		= "2"
 			register "PcieRpAdvancedErrorReporting[6]"	= "1"
@@ -64,7 +64,7 @@ chip soc/intel/skylake
 
 		# M.2 WWAN - x2
 		device ref pcie_rp5 on
-			register "PcieRpClkReqSupport[4]"		= "1"
+			register "PcieRpClkReqSupport[4]"		= "true"
 			register "PcieRpClkReqNumber[4]"		= "3"
 			register "PcieRpClkSrcNumber[4]"		= "3"
 			register "PcieRpAdvancedErrorReporting[4]"	= "1"
@@ -73,7 +73,7 @@ chip soc/intel/skylake
 
 		# TB3 (Alpine Ridge LP) - x2
 		device ref pcie_rp9 on
-			register "PcieRpClkReqSupport[8]"		= "1"
+			register "PcieRpClkReqSupport[8]"		= "true"
 			register "PcieRpClkReqNumber[8]"		= "4"
 			register "PcieRpClkSrcNumber[8]"		= "4"
 			register "PcieRpAdvancedErrorReporting[8]"	= "1"
@@ -83,7 +83,7 @@ chip soc/intel/skylake
 
 		# M.2 2280 caddy - x2
 		device ref pcie_rp11 on
-			register "PcieRpClkReqSupport[10]"		= "1"
+			register "PcieRpClkReqSupport[10]"		= "true"
 			register "PcieRpClkReqNumber[10]"		= "5"
 			register "PcieRpClkSrcNumber[10]"		= "5"
 			register "PcieRpAdvancedErrorReporting[10]"	= "1"
diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/overridetree.cb b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/overridetree.cb
index 14fcf371c7..50de1a09d7 100644
--- a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/overridetree.cb
+++ b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/overridetree.cb
@@ -37,7 +37,7 @@ chip soc/intel/skylake
 
 		# dGPU - x2
 		device ref pcie_rp1 on
-			register "PcieRpClkReqSupport[0]"		= "1"
+			register "PcieRpClkReqSupport[0]"		= "true"
 			register "PcieRpClkReqNumber[0]"		= "0"
 			register "PcieRpClkSrcNumber[0]"		= "0"
 			register "PcieRpAdvancedErrorReporting[0]"	= "1"
@@ -47,7 +47,7 @@ chip soc/intel/skylake
 
 		# M.2 WWAN - x1
 		device ref pcie_rp4 on
-			register "PcieRpClkReqSupport[3]"		= "1"
+			register "PcieRpClkReqSupport[3]"		= "true"
 			register "PcieRpClkReqNumber[3]"		= "1"
 			register "PcieRpClkSrcNumber[3]"		= "1"
 			register "PcieRpAdvancedErrorReporting[3]"	= "1"
@@ -64,7 +64,7 @@ chip soc/intel/skylake
 
 		# M.2 WLAN - x1
 		device ref pcie_rp7 on
-			register "PcieRpClkReqSupport[6]"		= "1"
+			register "PcieRpClkReqSupport[6]"		= "true"
 			register "PcieRpClkReqNumber[6]"		= "3"
 			register "PcieRpClkSrcNumber[6]"		= "3"
 			register "PcieRpAdvancedErrorReporting[6]"	= "1"
@@ -73,7 +73,7 @@ chip soc/intel/skylake
 
 		# TB3 (Alpine Ridge LP) - x2
 		device ref pcie_rp5 on
-			register "PcieRpClkReqSupport[4]"		= "1"
+			register "PcieRpClkReqSupport[4]"		= "true"
 			register "PcieRpClkReqNumber[4]"		= "4"
 			register "PcieRpClkSrcNumber[4]"		= "4"
 			register "PcieRpAdvancedErrorReporting[4]"	= "1"
@@ -83,7 +83,7 @@ chip soc/intel/skylake
 
 		# M.2 2280 SSD - x2
 		device ref pcie_rp9 on
-			register "PcieRpClkReqSupport[8]"		= "1"
+			register "PcieRpClkReqSupport[8]"		= "true"
 			register "PcieRpClkReqNumber[8]"		= "5"
 			register "PcieRpClkSrcNumber[8]"		= "5"
 			register "PcieRpAdvancedErrorReporting[8]"	= "1"
diff --git a/src/mainboard/protectli/vault_kbl/devicetree.cb b/src/mainboard/protectli/vault_kbl/devicetree.cb
index b47c53c7b5..2dcfa7e73e 100644
--- a/src/mainboard/protectli/vault_kbl/devicetree.cb
+++ b/src/mainboard/protectli/vault_kbl/devicetree.cb
@@ -181,7 +181,7 @@ chip soc/intel/skylake
 			register "PcieRpAdvancedErrorReporting[8]" = "1"
 			register "PcieRpLtrEnable[8]" = "true"
 			register "PcieRpClkSrcNumber[8]" = "5"
-			register "PcieRpClkReqSupport[8]" = "1"
+			register "PcieRpClkReqSupport[8]" = "true"
 			register "PcieRpClkReqNumber[8]" = "0"
 			smbios_slot_desc
 				"SlotTypePciExpressMini52pinWithoutBSKO"
diff --git a/src/mainboard/purism/librem_skl/variants/librem15/overridetree.cb b/src/mainboard/purism/librem_skl/variants/librem15/overridetree.cb
index 8a2bf282b4..37be8cdb9a 100644
--- a/src/mainboard/purism/librem_skl/variants/librem15/overridetree.cb
+++ b/src/mainboard/purism/librem_skl/variants/librem15/overridetree.cb
@@ -24,7 +24,7 @@ chip soc/intel/skylake
 		end
 		device ref pcie_rp5 on  end
 		device ref pcie_rp9 on
-			register "PcieRpClkReqSupport[8]" = "0"
+			register "PcieRpClkReqSupport[8]" = "false"
 			register "PcieRpClkReqNumber[8]" = "2"
 		end
 	end
diff --git a/src/mainboard/starlabs/starbook/variants/kbl/devicetree.cb b/src/mainboard/starlabs/starbook/variants/kbl/devicetree.cb
index f80003f05a..213cf56960 100644
--- a/src/mainboard/starlabs/starbook/variants/kbl/devicetree.cb
+++ b/src/mainboard/starlabs/starbook/variants/kbl/devicetree.cb
@@ -88,7 +88,7 @@ chip soc/intel/skylake
 		end
 		device ref uart2	on  end
 		device ref pcie_rp6	on
-			register "PcieRpClkReqSupport[5]"	= "1"
+			register "PcieRpClkReqSupport[5]"	= "true"
 			register "PcieRpClkReqNumber[5]"	= "4"
 			register "PcieRpClkSrcNumber[5]"	= "4"
 			register "PcieRpLtrEnable[5]"		= "true"
@@ -99,7 +99,7 @@ chip soc/intel/skylake
 			end
 		end
 		device ref pcie_rp9	on
-			register "PcieRpClkReqSupport[8]"	= "1"
+			register "PcieRpClkReqSupport[8]"	= "true"
 			register "PcieRpClkReqNumber[8]"	= "0"
 			register "PcieRpClkSrcNumber[8]"	= "0"
 			register "PcieRpLtrEnable[8]"		= "true"
diff --git a/src/mainboard/system76/kbl-u/devicetree.cb b/src/mainboard/system76/kbl-u/devicetree.cb
index 968e460130..30e1bb0cee 100644
--- a/src/mainboard/system76/kbl-u/devicetree.cb
+++ b/src/mainboard/system76/kbl-u/devicetree.cb
@@ -133,7 +133,7 @@ chip soc/intel/skylake
 		end
 		device ref pcie_rp1 on
 			# Root port #1 x4 (TBT)
-			register "PcieRpClkReqSupport[0]" = "1"
+			register "PcieRpClkReqSupport[0]" = "true"
 			register "PcieRpClkReqNumber[0]" = "4"
 			register "PcieRpClkSrcNumber[0]" = "4"
 			register "PcieRpAdvancedErrorReporting[0]" = "1"
@@ -142,7 +142,7 @@ chip soc/intel/skylake
 		end
 		device ref pcie_rp5 on
 			# Root port #5 x1 (LAN)
-			register "PcieRpClkReqSupport[4]" = "1"
+			register "PcieRpClkReqSupport[4]" = "true"
 			register "PcieRpClkReqNumber[4]" = "3"
 			register "PcieRpClkSrcNumber[4]" = "3"
 			register "PcieRpAdvancedErrorReporting[4]" = "1"
@@ -150,7 +150,7 @@ chip soc/intel/skylake
 		end
 		device ref pcie_rp6 on
 			# Root port #6 x1 (WLAN)
-			register "PcieRpClkReqSupport[5]" = "1"
+			register "PcieRpClkReqSupport[5]" = "true"
 			register "PcieRpClkReqNumber[5]" = "2"
 			register "PcieRpClkSrcNumber[5]" = "2"
 			register "PcieRpAdvancedErrorReporting[5]" = "1"
@@ -159,7 +159,7 @@ chip soc/intel/skylake
 		end
 		device ref pcie_rp9 on
 			# Root port #9 x4 (NVMe)
-			register "PcieRpClkReqSupport[8]" = "1"
+			register "PcieRpClkReqSupport[8]" = "true"
 			register "PcieRpClkReqNumber[8]" = "5"
 			register "PcieRpClkSrcNumber[8]" = "5"
 			register "PcieRpAdvancedErrorReporting[8]" = "1"

From 699c28c01d1ed1fbf19c8503e3d9d58249889eef Mon Sep 17 00:00:00 2001
From: Angel Pons <th3fanbus@gmail.com>
Date: Wed, 6 Jan 2021 01:43:21 +0100
Subject: [PATCH 1890/3886] sb/intel/bd82x6x: Fix replay issues

Rewrite suspicious register handling as per reference code. Proper
handling of the value in the RPC register needs some IOBP operations,
and will be done in a follow-up once `pch_iobp_update` can be used.

TEST=Still boots on Lenovo X220.

Change-Id: I7cf8851e98e3971593734dc2a46f7e0b43d8cdca
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88899
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
---
 src/southbridge/intel/bd82x6x/early_pch.c | 45 ++++++++++++-----------
 1 file changed, 23 insertions(+), 22 deletions(-)

diff --git a/src/southbridge/intel/bd82x6x/early_pch.c b/src/southbridge/intel/bd82x6x/early_pch.c
index 414b2382cf..cf31d4ed13 100644
--- a/src/southbridge/intel/bd82x6x/early_pch.c
+++ b/src/southbridge/intel/bd82x6x/early_pch.c
@@ -67,13 +67,17 @@ void early_pch_init_native_dmi_pre(void)
 
 void early_pch_init_native_dmi_post(void)
 {
-	RCBA32(CIR0);	// !!! = 0x01200654
-	RCBA32(CIR0) = 0x01200654;
-	RCBA32(CIR0);	// !!! = 0x01200654
-	RCBA32(CIR0) = 0x012a0654;
-	RCBA32(CIR0);	// !!! = 0x012a0654
-	RCBA8(UPDCR);	// !!! = 0x00
-	RCBA8(UPDCR) = 0x05;
+	u32 reg32;
+
+	reg32 = RCBA32(CIR0);
+	reg32 &= ~(0xff << 16 | 0xfff);
+	reg32 |= 0x654;		/* Set the recommended TC encoding */
+	reg32 |= 0x20 << 16;
+	reg32 |= 0x0a << 16;	/* VCp enabled */
+	RCBA32(CIR0) = reg32;
+	RCBA32(CIR0);		/* Read back for posted write to take effect */
+
+	RCBA8(UPDCR) = RCBA8(UPDCR) | 1 << 2 | 1 << 0;
 
 	/*
 	 * Virtual Channel resources must match settings in DMIBAR!
@@ -138,27 +142,24 @@ void early_pch_init_native(void)
 	const u16 dev_id = pci_read_config16(PCH_LPC_DEV, PCI_DEVICE_ID);
 	u8 pcie_ports = (dev_id == PCI_DEVICE_ID_INTEL_UM77) ? 4 : 8;
 
-	pci_write_config8(SOUTHBRIDGE, 0xa6, pci_read_config8(SOUTHBRIDGE, 0xa6) | 2);
-
 	/* Clear this bit early for PCIe device detection */
 	for (uint8_t i = 0; i < pcie_ports; i++)
 		pci_update_config32(PCH_PCIE_DEV(i), 0x338, ~(1 << 26), 0);
 
-	RCBA32(CIR1) = 0x00109000;
-	RCBA32(REC); // !!! = 0x00000000
-	RCBA32(REC) = 0x40000000;
+	/* Lock down PMBASE */
+	pci_or_config8(PCH_LPC_DEV, GEN_PMCON_LOCK, 1 << 1);
+
+	RCBA32(CIR1) = 0x00109000;	/* Mask some errors */
+	RCBA32_OR(REC, 1 << 30);
 	RCBA32(0x100c) = 0x01110000;
-	RCBA8(0x2340) = 0x1b;
-	RCBA32(CIR6); // !!! = 0x0a080000
-	RCBA32(CIR6) = 0x0a280000;
-	RCBA32(0x2310); // !!! = 0xc809605b
-	RCBA32(0x2310) = 0xa809605b;
+	RCBA8(0x2340) = 0x1b;		/* Set Gen 1 Common Clock N_FTS */
+	RCBA32_OR(CIR6, 1 << 21);
+	RCBA32_AND_OR(0x2310, ~(3 << 29), 1 << 29);
 	RCBA32(DMC2) = 0x00854c74;
-	RCBA8(RPC);  // !!! = 0x00
-	RCBA32(0x2310); // !!! = 0xa809605b
-	RCBA32(0x2310) = 0xa809605b;
-	RCBA32(0x2310); // !!! = 0xa809605b
-	RCBA32(0x2310) = 0xa809605b;
+
+	/* TODO: Handle non-zero cases */
+	RCBA32_AND_OR(0x2310, ~(3 << 22), 0);
+	RCBA32_AND_OR(0x2310, ~(3 << 20), 0);
 
 	write_iobp(0xea007f62, 0x00590133);
 	write_iobp(0xec007f62, 0x00590133);

From e03f50bf5fbbcefb00d4eb726a418a4072cede78 Mon Sep 17 00:00:00 2001
From: Kilian Krause <kilian.krause@siemens.com>
Date: Wed, 11 Jun 2025 11:07:17 +0200
Subject: [PATCH 1891/3886] mb/siemens/mc_rpl: Enable Siemens NC_FPGA driver

Activate NC_FPGA driver in the baseboard as it will be used by
all variants.

Change-Id: Ia6538dfc752f661411687d5c5cf635e6d4c0ac16
Signed-off-by: Kilian Krause <kilian.krause@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88950
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/siemens/mc_rpl/Kconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/src/mainboard/siemens/mc_rpl/Kconfig b/src/mainboard/siemens/mc_rpl/Kconfig
index 5281bb5d86..fa596b122a 100644
--- a/src/mainboard/siemens/mc_rpl/Kconfig
+++ b/src/mainboard/siemens/mc_rpl/Kconfig
@@ -13,6 +13,7 @@ config BOARD_SIEMENS_BASEBOARD_MC_RPL
 	select USE_SIEMENS_HWILIB
 	select SOC_INTEL_ALDERLAKE_PCH_P
 	select SOC_INTEL_RAPTORLAKE
+	select DRIVER_SIEMENS_NC_FPGA
 
 config BOARD_SIEMENS_MC_RPL1
 	select BOARD_SIEMENS_BASEBOARD_MC_RPL

From 993a9c9e14ab9a6ca5dd70e43a7c93dbe1f91ed9 Mon Sep 17 00:00:00 2001
From: Kilian Krause <kilian.krause@siemens.com>
Date: Wed, 11 Jun 2025 12:26:24 +0200
Subject: [PATCH 1892/3886] mb/siemens/mc_rpl1: Configure SATA Ports

This board does only use SATA Port 0 and SATA Port 1. The rest is
disabled. In addition, power management features like DevSlp and
Aggressive Link Power management are not supported on this motherboard
and are deactivated accordingly.

TEST=Verified SATA config: `dmesg | grep -i "sata link"` shows ports
0-1 active at 3.0 Gbps (Gen2 limit).

Change-Id: I4567328c25f195fac8edc02518a6a812922f48e5
Signed-off-by: Kilian Krause <kilian.krause@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88952
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
---
 src/mainboard/siemens/mc_rpl/devicetree.cb      | 17 -----------------
 .../mc_rpl/variants/mc_rpl1/overridetree.cb     |  9 +++++++++
 2 files changed, 9 insertions(+), 17 deletions(-)

diff --git a/src/mainboard/siemens/mc_rpl/devicetree.cb b/src/mainboard/siemens/mc_rpl/devicetree.cb
index a5af508a2f..fdd62466aa 100644
--- a/src/mainboard/siemens/mc_rpl/devicetree.cb
+++ b/src/mainboard/siemens/mc_rpl/devicetree.cb
@@ -13,22 +13,6 @@ chip soc/intel/alderlake
 	# Sagv Configuration
 	register "sagv" = "SaGv_Enabled"
 
-	register "sata_salp_support" = "1"
-
-	register "sata_ports_enable" = "{
-		[0] = 1,
-		[1] = 1,
-		[2] = 1,
-		[3] = 1,
-	}"
-
-	register "sata_ports_dev_slp" = "{
-		[0] = 1,
-		[1] = 1,
-		[2] = 1,
-		[3] = 1,
-	}"
-
 	register "s0ix_enable" = "true"
 	register "dptf_enable" = "true"
 
@@ -130,7 +114,6 @@ chip soc/intel/alderlake
 			end
 		end
 		device ref crashlog off end
-		device ref sata on end
 		device ref p2sb on end
 		device ref smbus on end
 	end
diff --git a/src/mainboard/siemens/mc_rpl/variants/mc_rpl1/overridetree.cb b/src/mainboard/siemens/mc_rpl/variants/mc_rpl1/overridetree.cb
index b6ba91a40d..9e8da22920 100644
--- a/src/mainboard/siemens/mc_rpl/variants/mc_rpl1/overridetree.cb
+++ b/src/mainboard/siemens/mc_rpl/variants/mc_rpl1/overridetree.cb
@@ -3,6 +3,14 @@ chip soc/intel/alderlake
 	# seen on J0 and Q0 SKUs
 	register "disable_package_c_state_demotion" = "true"
 
+	register "sata_salp_support" = "0"
+	register "sata_speed" = "SATA_GEN2"
+
+	register "sata_ports_enable" = "{
+		[0] = 1,
+		[1] = 1,
+	}"
+
 	register "usb2_ports[0]" = "USB2_PORT_MID(OC_SKIP)"	# Port1
 	register "usb2_ports[1]" = "USB2_PORT_MID(OC_SKIP)"	# Port2
 	register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)"	# Onboard USB
@@ -128,5 +136,6 @@ chip soc/intel/alderlake
 				device pnp 0c31.0 on end
 			end
 		end
+		device ref sata on end
 	end
 end

From 66a3f2a1b14eb8d7bf0e5f1233c2ea97962a6f3e Mon Sep 17 00:00:00 2001
From: Kilian Krause <kilian.krause@siemens.com>
Date: Wed, 11 Jun 2025 15:30:53 +0200
Subject: [PATCH 1893/3886] mb/siemens/mc_rpl: Disable SaGv

Disable SaGv at baseboard level to improve realtime performance.

Change-Id: I0fd587aa8beb0c86ba88553cfeddac786b4c8948
Signed-off-by: Kilian Krause <kilian.krause@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88953
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
---
 src/mainboard/siemens/mc_rpl/devicetree.cb | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/mainboard/siemens/mc_rpl/devicetree.cb b/src/mainboard/siemens/mc_rpl/devicetree.cb
index fdd62466aa..1d7eec4a1f 100644
--- a/src/mainboard/siemens/mc_rpl/devicetree.cb
+++ b/src/mainboard/siemens/mc_rpl/devicetree.cb
@@ -11,7 +11,7 @@ chip soc/intel/alderlake
 	# FSP configuration
 
 	# Sagv Configuration
-	register "sagv" = "SaGv_Enabled"
+	register "sagv" = "SaGv_Disabled"
 
 	register "s0ix_enable" = "true"
 	register "dptf_enable" = "true"

From 1b14664311bf97e31d71ae56af1a6a6e832b0557 Mon Sep 17 00:00:00 2001
From: Kilian Krause <kilian.krause@siemens.com>
Date: Fri, 13 Jun 2025 10:33:20 +0200
Subject: [PATCH 1894/3886] mb/siemens/mc_rpl: Remove unused DPTF settings

Since the CPU does not control any fans and the mainboard does not
implement a charger, remove all unnecessary DPTF UPDs. DPTF will be used
for limitting PL1 and PL2 in the future.

Change-Id: I22e1167cb2986f5c56ff6085236792adbb9a19cc
Signed-off-by: Kilian Krause <kilian.krause@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88954
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/siemens/mc_rpl/devicetree.cb | 72 ----------------------
 1 file changed, 72 deletions(-)

diff --git a/src/mainboard/siemens/mc_rpl/devicetree.cb b/src/mainboard/siemens/mc_rpl/devicetree.cb
index 1d7eec4a1f..8cacb34b04 100644
--- a/src/mainboard/siemens/mc_rpl/devicetree.cb
+++ b/src/mainboard/siemens/mc_rpl/devicetree.cb
@@ -20,52 +20,6 @@ chip soc/intel/alderlake
 		device ref igpu on end
 		device ref dtt on
 			chip drivers/intel/dptf
-
-				## sensor information
-				register "options.tsr[0].desc" = ""Ambient""
-				register "options.tsr[1].desc" = ""Battery""
-				register "options.tsr[2].desc" = ""DDR""
-				register "options.tsr[3].desc" = ""Skin""
-
-				## Active Policy
-				# TODO: below values are initial reference values only
-				register "policies.active" = "{
-					[0] = {
-							.target = DPTF_CPU,
-							.thresholds = {
-								TEMP_PCT(95, 90),
-								TEMP_PCT(90, 80),
-							}
-						},
-					[1] = {
-							.target = DPTF_TEMP_SENSOR_0,
-							.thresholds = {
-								TEMP_PCT(80, 90),
-								TEMP_PCT(70, 80),
-							}
-						}
-				}"
-
-				## Passive Policy
-				# TODO: below values are initial reference values only
-				register "policies.passive" = "{
-					[0] = DPTF_PASSIVE(CPU,		CPU,	       95, 10000),
-					[1] = DPTF_PASSIVE(CPU,		TEMP_SENSOR_0, 85, 50000),
-					[2] = DPTF_PASSIVE(CHARGER,	TEMP_SENSOR_1, 85, 50000),
-					[3] = DPTF_PASSIVE(CPU,		TEMP_SENSOR_2, 85, 50000),
-					[4] = DPTF_PASSIVE(CPU,		TEMP_SENSOR_3, 85, 50000),
-				}"
-
-				## Critical Policy
-				# TODO: below values are initial reference values only
-				register "policies.critical" = "{
-					[0] = DPTF_CRITICAL(CPU,	  105, SHUTDOWN),
-					[1] = DPTF_CRITICAL(TEMP_SENSOR_0, 95, SHUTDOWN),
-					[2] = DPTF_CRITICAL(TEMP_SENSOR_1, 95, SHUTDOWN),
-					[3] = DPTF_CRITICAL(TEMP_SENSOR_2, 95, SHUTDOWN),
-					[4] = DPTF_CRITICAL(TEMP_SENSOR_3, 95, SHUTDOWN),
-				}"
-
 				## Power Limits Control
 				register "controls.power_limits" = "{
 					.pl1 = {
@@ -84,32 +38,6 @@ chip soc/intel/alderlake
 					}
 				}"
 
-				## Charger Performance Control (Control, mA)
-				register "controls.charger_perf" = "{
-					[0] = { 255, 3000 },
-					[1] = {  24, 1500 },
-					[2] = {  16, 1000 },
-					[3] = {   8,  500 }
-				}"
-
-				## Fan Performance Control (Percent, Speed, Noise, Power)
-				register "controls.fan_perf" = "{
-					[0] = {  90, 6700, 220, 2200, },
-					[1] = {  80, 5800, 180, 1800, },
-					[2] = {  70, 5000, 145, 1450, },
-					[3] = {  60, 4900, 115, 1150, },
-					[4] = {  50, 3838,  90,  900, },
-					[5] = {  40, 2904,  55,  550, },
-					[6] = {  30, 2337,  30,  300, },
-					[7] = {  20, 1608,  15,  150, },
-					[8] = {  10,  800,  10,  100, },
-					[9] = {   0,    0,   0,   50, }
-				}"
-
-				## Fan options
-				register "options.fan.fine_grained_control" = "true"
-				register "options.fan.step_size" = "2"
-
 				device generic 0 alias dptf_policy on end
 			end
 		end

From 2f9273f1f4dda4e973ff2c0f179add6f675c8879 Mon Sep 17 00:00:00 2001
From: Kilian Krause <kilian.krause@siemens.com>
Date: Fri, 13 Jun 2025 15:44:40 +0200
Subject: [PATCH 1895/3886] mb/siemens/mc_rpl: Select FSP_TYPE_IOT

All mc_rpl variants use IoT FSP.

Change-Id: I615fdf27079a65222c931f26216dd049519be3c5
Signed-off-by: Kilian Krause <kilian.krause@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88955
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/siemens/mc_rpl/Kconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/src/mainboard/siemens/mc_rpl/Kconfig b/src/mainboard/siemens/mc_rpl/Kconfig
index fa596b122a..76e2845420 100644
--- a/src/mainboard/siemens/mc_rpl/Kconfig
+++ b/src/mainboard/siemens/mc_rpl/Kconfig
@@ -14,6 +14,7 @@ config BOARD_SIEMENS_BASEBOARD_MC_RPL
 	select SOC_INTEL_ALDERLAKE_PCH_P
 	select SOC_INTEL_RAPTORLAKE
 	select DRIVER_SIEMENS_NC_FPGA
+	select FSP_TYPE_IOT
 
 config BOARD_SIEMENS_MC_RPL1
 	select BOARD_SIEMENS_BASEBOARD_MC_RPL

From d7a996cf449489d2a81dee253b6c2e4ab5b33c5d Mon Sep 17 00:00:00 2001
From: Kilian Krause <kilian.krause@siemens.com>
Date: Thu, 10 Jul 2025 14:40:18 +0200
Subject: [PATCH 1896/3886] mb/siemens/mc_rpl1: Enable 4 P-Cores, disable
 E-Cores

Set the active core configuration for the processor on this variant to
use 4 P-cores and 0 E-cores. This ensures that only the performance
cores are enabled, which matches the intended use case for this specific
board variant.

Change-Id: If79b13fea16bcd369feb438aab4ab11dd63d4fab
Signed-off-by: Kilian Krause <kilian.krause@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88958
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 .../siemens/mc_rpl/include/baseboard/variants.h     |  1 +
 src/mainboard/siemens/mc_rpl/romstage_fsp_params.c  |  2 ++
 .../siemens/mc_rpl/variants/mc_rpl1/Makefile.mk     |  1 +
 .../siemens/mc_rpl/variants/mc_rpl1/variant.c       | 13 +++++++++++++
 4 files changed, 17 insertions(+)
 create mode 100644 src/mainboard/siemens/mc_rpl/variants/mc_rpl1/variant.c

diff --git a/src/mainboard/siemens/mc_rpl/include/baseboard/variants.h b/src/mainboard/siemens/mc_rpl/include/baseboard/variants.h
index bb2c3f62b0..e27b1773ba 100644
--- a/src/mainboard/siemens/mc_rpl/include/baseboard/variants.h
+++ b/src/mainboard/siemens/mc_rpl/include/baseboard/variants.h
@@ -34,6 +34,7 @@ void variant_configure_early_gpio_pads(void);
 size_t variant_memory_sku(void);
 const struct mb_cfg *variant_memory_params(void);
 void rpl_memory_params(FSPM_UPD *memupd);
+void variant_configure_fspm(FSPM_UPD *memupd);
 
 /* Modify devictree settings during ramstage */
 void variant_devtree_update(void);
diff --git a/src/mainboard/siemens/mc_rpl/romstage_fsp_params.c b/src/mainboard/siemens/mc_rpl/romstage_fsp_params.c
index 962b514d2f..0026821820 100644
--- a/src/mainboard/siemens/mc_rpl/romstage_fsp_params.c
+++ b/src/mainboard/siemens/mc_rpl/romstage_fsp_params.c
@@ -61,4 +61,6 @@ void mainboard_memory_init_params(FSPM_UPD *memupd)
 
 	if (CONFIG(GEN3_EXTERNAL_CLOCK_BUFFER))
 		configure_external_clksrc(m_cfg);
+
+	variant_configure_fspm(memupd);
 }
diff --git a/src/mainboard/siemens/mc_rpl/variants/mc_rpl1/Makefile.mk b/src/mainboard/siemens/mc_rpl/variants/mc_rpl1/Makefile.mk
index 45c478178a..248d22b18c 100644
--- a/src/mainboard/siemens/mc_rpl/variants/mc_rpl1/Makefile.mk
+++ b/src/mainboard/siemens/mc_rpl/variants/mc_rpl1/Makefile.mk
@@ -2,3 +2,4 @@
 
 bootblock-y += early_gpio.c
 ramstage-y += gpio.c
+romstage-y += variant.c
diff --git a/src/mainboard/siemens/mc_rpl/variants/mc_rpl1/variant.c b/src/mainboard/siemens/mc_rpl/variants/mc_rpl1/variant.c
new file mode 100644
index 0000000000..91f5cbd496
--- /dev/null
+++ b/src/mainboard/siemens/mc_rpl/variants/mc_rpl1/variant.c
@@ -0,0 +1,13 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <console/console.h>
+#include <fsp/api.h>
+#include <baseboard/variants.h>
+
+void variant_configure_fspm(FSPM_UPD *memupd)
+{
+	FSP_M_CONFIG *m_cfg = &memupd->FspmConfig;
+
+	m_cfg->ActiveCoreCount = 4;
+	m_cfg->ActiveSmallCoreCount = 0;
+}

From c15006eb0cf97d9b60c0ecc05beae610cf2efb40 Mon Sep 17 00:00:00 2001
From: Kilian Krause <kilian.krause@siemens.com>
Date: Fri, 4 Jul 2025 10:59:48 +0200
Subject: [PATCH 1897/3886] soc/intel/alderlake: Add 28W TDP support for RPL-P
 ID 8 (0xa716)

Add voltage regulator configuration for Intel Raptor Lake-P processor
with MCH ID 0xa716 (RPL_P_ID_8) at 28W TDP. This processor has a
4+4 core configuration.

- Add the MCH ID mapping to the 28W TDP processor variant
- Add VR configurations for loadline, ICC, TDC timewindow, and
  TDC current limit tables

The VR configuration is adapted from the existing 28W variants.

TEST=Built and booted on hardware with MCH ID 0xa716. Verified
resolution of "Unknown MCH" errors and correct power limit
configuration. System boots successfully to OS.

Before:
[DEBUG] BS: BS_DEV_INIT_CHIPS entry times (exec / console): 649 / 543 ms
[DEBUG] All HSPHY ports disabled, skipping HSPHY loading
[INFO ] Disabling PCH PCIE ClockGating+PowerGating.
[ERROR] Unknown MCH (0xa716) in load_table
[ERROR] Unknown MCH (0xa716) in load_table
[ERROR] Unknown MCH (0xa716) in load_table
[ERROR] Unknown MCH (0xa716) in load_table
[ERROR] Unknown MCH (0xa716) in load_table
[ERROR] Unknown MCH (0xa716) in load_table
[ERROR] Unknown MCH (0xa716) in load_table
[ERROR] Unknown MCH (0xa716) in load_table
[ERROR] Unknown MCH (0xa716) in load_table
[ERROR] Unknown MCH (0xa716) in load_table
[INFO ] PCI  1.0, PIN A, using IRQ #16

...

[DEBUG] BS: BS_DEV_ENABLE exit times (exec / console): 20 / 4 ms
[INFO ] Initializing devices...
[DEBUG] PCI: 00:00:00.0 init
[ERROR] unknown SA ID: 0xa716, skipped power limits configuration.
[DEBUG] PCI: 00:00:00.0 init finished in 7 msecs

After:
[DEBUG] BS: BS_DEV_INIT_CHIPS entry times (exec / console): 542 / 537 ms
[DEBUG] All HSPHY ports disabled, skipping HSPHY loading
[INFO ] Disabling PCH PCIE ClockGating+PowerGating.
[INFO ] PCI  1.0, PIN A, using IRQ #16

...

[DEBUG] BS: BS_DEV_ENABLE exit times (exec / console): 21 / 4 ms
[INFO ] Initializing devices...
[DEBUG] PCI: 00:00:00.0 init
[INFO ] CPU TDP = 28 Watts
[INFO ] CPU PL1 = 28 Watts
[INFO ] CPU PL2 = 28 Watts
[INFO ] CPU PL4 = 64 Watts
[DEBUG] PCI: 00:00:00.0 init finished in 14 msecs

Change-Id: I9d6f32f2f3fbf73e46a25d77e4dba7711ed70d5f
Signed-off-by: Kilian Krause <kilian.krause@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88957
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
---
 src/soc/intel/alderlake/chip.h      | 1 +
 src/soc/intel/alderlake/vr_config.c | 4 ++++
 2 files changed, 5 insertions(+)

diff --git a/src/soc/intel/alderlake/chip.h b/src/soc/intel/alderlake/chip.h
index db8965e40e..8e143f0f65 100644
--- a/src/soc/intel/alderlake/chip.h
+++ b/src/soc/intel/alderlake/chip.h
@@ -198,6 +198,7 @@ static const struct {
 	{ PCI_DID_INTEL_RPL_P_ID_6, RPL_P_682_642_482_45W_CORE, TDP_45W },
 	{ PCI_DID_INTEL_RPL_P_ID_7, RPL_P_682_642_482_45W_CORE, TDP_45W },
 	{ PCI_DID_INTEL_RPL_P_ID_8, RPL_P_682_642_482_45W_CORE, TDP_45W },
+	{ PCI_DID_INTEL_RPL_P_ID_8, RPL_P_682_482_282_28W_CORE, TDP_28W },
 	{ PCI_DID_INTEL_RPL_S_ID_1, RPL_S_8161_35W_CORE, TDP_35W },
 	{ PCI_DID_INTEL_RPL_S_ID_1, RPL_S_8161_65W_CORE, TDP_65W },
 	{ PCI_DID_INTEL_RPL_S_ID_1, RPL_S_8161_95W_CORE, TDP_95W },
diff --git a/src/soc/intel/alderlake/vr_config.c b/src/soc/intel/alderlake/vr_config.c
index 6a29a02960..06fddc864b 100644
--- a/src/soc/intel/alderlake/vr_config.c
+++ b/src/soc/intel/alderlake/vr_config.c
@@ -159,6 +159,7 @@ static const struct vr_lookup vr_config_ll[] = {
 	{ PCI_DID_INTEL_RPL_P_ID_6, 45, VR_CFG_ALL_DOMAINS_LOADLINE(2.3, 3.2) },
 	{ PCI_DID_INTEL_RPL_P_ID_7, 45, VR_CFG_ALL_DOMAINS_LOADLINE(2.3, 3.2) },
 	{ PCI_DID_INTEL_RPL_P_ID_8, 45, VR_CFG_ALL_DOMAINS_LOADLINE(2.3, 3.2) },
+	{ PCI_DID_INTEL_RPL_P_ID_8, 28, VR_CFG_ALL_DOMAINS_LOADLINE(2.3, 3.2) },
 	{ PCI_DID_INTEL_ADL_S_ID_1,  150, VR_CFG_ALL_DOMAINS_LOADLINE(1.1, 4.0) },
 	{ PCI_DID_INTEL_ADL_S_ID_1,  125, VR_CFG_ALL_DOMAINS_LOADLINE(1.1, 4.0) },
 	{ PCI_DID_INTEL_ADL_S_ID_1,  65,  VR_CFG_ALL_DOMAINS_LOADLINE(1.1, 4.0) },
@@ -231,6 +232,7 @@ static const struct vr_lookup vr_config_icc[] = {
 	{ PCI_DID_INTEL_RPL_P_ID_6, 45, VR_CFG_ALL_DOMAINS_ICC(160, 55) },
 	{ PCI_DID_INTEL_RPL_P_ID_7, 45, VR_CFG_ALL_DOMAINS_ICC(160, 55) },
 	{ PCI_DID_INTEL_RPL_P_ID_8, 45, VR_CFG_ALL_DOMAINS_ICC(160, 55) },
+	{ PCI_DID_INTEL_RPL_P_ID_8, 28, VR_CFG_ALL_DOMAINS_ICC(102, 55) },
 	{ PCI_DID_INTEL_ADL_S_ID_1,  150, VR_CFG_ALL_DOMAINS_ICC(280, 30) },
 	{ PCI_DID_INTEL_ADL_S_ID_1,  125, VR_CFG_ALL_DOMAINS_ICC(280, 30) },
 	{ PCI_DID_INTEL_ADL_S_ID_1,  65,  VR_CFG_ALL_DOMAINS_ICC(240, 30) },
@@ -303,6 +305,7 @@ static const struct vr_lookup vr_config_tdc_timewindow[] = {
 	{ PCI_DID_INTEL_RPL_P_ID_6, 45, VR_CFG_ALL_DOMAINS_TDC(28000, 28000) },
 	{ PCI_DID_INTEL_RPL_P_ID_7, 45, VR_CFG_ALL_DOMAINS_TDC(28000, 28000) },
 	{ PCI_DID_INTEL_RPL_P_ID_8, 45, VR_CFG_ALL_DOMAINS_TDC(28000, 28000) },
+	{ PCI_DID_INTEL_RPL_P_ID_8, 28, VR_CFG_ALL_DOMAINS_TDC(28000, 28000) },
 	{ PCI_DID_INTEL_ADL_S_ID_1,  150, VR_CFG_ALL_DOMAINS_TDC(56000, 56000) },
 	{ PCI_DID_INTEL_ADL_S_ID_1,  125, VR_CFG_ALL_DOMAINS_TDC(56000, 56000) },
 	{ PCI_DID_INTEL_ADL_S_ID_1,  65,  VR_CFG_ALL_DOMAINS_TDC(56000, 56000) },
@@ -375,6 +378,7 @@ static const struct vr_lookup vr_config_tdc_currentlimit[] = {
 	{ PCI_DID_INTEL_RPL_P_ID_6, 45, VR_CFG_ALL_DOMAINS_TDC_CURRENT(86, 86) },
 	{ PCI_DID_INTEL_RPL_P_ID_7, 45, VR_CFG_ALL_DOMAINS_TDC_CURRENT(86, 86) },
 	{ PCI_DID_INTEL_RPL_P_ID_8, 45, VR_CFG_ALL_DOMAINS_TDC_CURRENT(86, 86) },
+	{ PCI_DID_INTEL_RPL_P_ID_8, 28, VR_CFG_ALL_DOMAINS_TDC_CURRENT(33, 33) },
 	{ PCI_DID_INTEL_ADL_S_ID_1,  150, VR_CFG_ALL_DOMAINS_TDC_CURRENT(132, 22) },
 	{ PCI_DID_INTEL_ADL_S_ID_1,  125, VR_CFG_ALL_DOMAINS_TDC_CURRENT(132, 22) },
 	{ PCI_DID_INTEL_ADL_S_ID_1,  65,  VR_CFG_ALL_DOMAINS_TDC_CURRENT(89, 22) },

From 0a328282ec68c38cd63dcd4a5d1592a7dbd5bf26 Mon Sep 17 00:00:00 2001
From: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Date: Thu, 21 Aug 2025 08:42:47 +0900
Subject: [PATCH 1898/3886] device/azalia: Add enums for HDA verb and parameter
 IDs

This is a purely cosmetic change to make things slightly more easier to
read. We also only add the IDs which are actively used in the codebase.

TEST=Timeless build produces identical binaries

Change-Id: I4ec0a570020059c85768bab913dff1ba1977e9f9
Signed-off-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88917
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
---
 src/device/azalia_device.c         |  3 +-
 src/include/device/azalia_device.h | 62 ++++++++++++++++++++----------
 2 files changed, 42 insertions(+), 23 deletions(-)

diff --git a/src/device/azalia_device.c b/src/device/azalia_device.c
index dadcda918e..f634908daa 100644
--- a/src/device/azalia_device.c
+++ b/src/device/azalia_device.c
@@ -249,8 +249,7 @@ static bool codec_is_operative(u8 *base, const int addr)
 		return false;
 	}
 
-	const u32 reg32 = (addr << 28) | 0x000f0000;
-	write32(base + HDA_IC_REG, reg32);
+	write32(base + HDA_IC_REG, AZALIA_VERB_GET_VENDOR_ID(addr));
 
 	if (wait_for_valid(base) < 0) {
 		printk(BIOS_NOTICE, "azalia_audio: codec #%d doesn't respond\n", addr);
diff --git a/src/include/device/azalia_device.h b/src/include/device/azalia_device.h
index 7fe6514ed2..21d00b0dae 100644
--- a/src/include/device/azalia_device.h
+++ b/src/include/device/azalia_device.h
@@ -37,12 +37,29 @@ extern const u32 cim_verb_data_size;
 extern const u32 pc_beep_verbs[];
 extern const u32 pc_beep_verbs_size;
 
-/*
- * The tables found in this file are derived from the Intel High Definition
- * Audio Specification Revision 1.0a, published 17 June 2010
- *
- * 7.3.3.31 Configuration Default (page 177)
- */
+/* The tables found in this file are derived from the Intel High Definition
+   Audio Specification Revision 1.0a, published 17 June 2010 */
+
+/* Reference: 7.3.3 Controls (page 141) */
+enum azalia_verb_id {
+	AZALIA_GET_PARAMETER               = 0xf00,
+	AZALIA_SET_SUBSYSTEM_ID_1          = 0x720,
+	AZALIA_SET_SUBSYSTEM_ID_2          = 0x721,
+	AZALIA_SET_SUBSYSTEM_ID_3          = 0x722,
+	AZALIA_SET_SUBSYSTEM_ID_4          = 0x723,
+	AZALIA_SET_CONFIGURATION_DEFAULT_1 = 0x71c,
+	AZALIA_SET_CONFIGURATION_DEFAULT_2 = 0x71d,
+	AZALIA_SET_CONFIGURATION_DEFAULT_3 = 0x71e,
+	AZALIA_SET_CONFIGURATION_DEFAULT_4 = 0x71f,
+	AZALIA_FUNCTION_RESET              = 0x7ff,
+};
+
+/* Reference: 7.3.4 Parameters (page 198) */
+enum azalia_parameter_id {
+	AZALIA_PARAMETER_VENDOR_ID = 0x00,
+};
+
+/* Reference: 7.3.3.31 Configuration Default (page 177) */
 enum azalia_pin_connection {
 	AZALIA_JACK                = 0x0,
 	AZALIA_NC                  = 0x1,
@@ -151,24 +168,27 @@ enum azalia_pin_misc {
 #define AZALIA_VERB_12B(codec, pin, verb, val)		\
 	((codec) << 28 | (pin) << 20 | (verb) << 8 | (val))
 
-#define AZALIA_PIN_CFG(codec, pin, val)					\
-	AZALIA_VERB_12B(codec, pin, 0x71c, ((val) >>  0) & 0xff),	\
-	AZALIA_VERB_12B(codec, pin, 0x71d, ((val) >>  8) & 0xff),	\
-	AZALIA_VERB_12B(codec, pin, 0x71e, ((val) >> 16) & 0xff),	\
-	AZALIA_VERB_12B(codec, pin, 0x71f, ((val) >> 24) & 0xff)
+#define AZALIA_VERB_GET_VENDOR_ID(codec) \
+	AZALIA_VERB_12B(codec, 0, AZALIA_GET_PARAMETER, AZALIA_PARAMETER_VENDOR_ID)
+
+#define AZALIA_PIN_CFG(codec, pin, val)								\
+	AZALIA_VERB_12B(codec, pin, AZALIA_SET_CONFIGURATION_DEFAULT_1, ((val) >>  0) & 0xff),	\
+	AZALIA_VERB_12B(codec, pin, AZALIA_SET_CONFIGURATION_DEFAULT_2, ((val) >>  8) & 0xff),	\
+	AZALIA_VERB_12B(codec, pin, AZALIA_SET_CONFIGURATION_DEFAULT_3, ((val) >> 16) & 0xff),	\
+	AZALIA_VERB_12B(codec, pin, AZALIA_SET_CONFIGURATION_DEFAULT_4, ((val) >> 24) & 0xff)
 
 #define AZALIA_PIN_CFG_NC(n)   (0x411111f0 | ((n) & 0xf))
 
-#define AZALIA_RESET(pin)			\
-	AZALIA_VERB_12B(0, pin, 0x7ff, 0),	\
-	AZALIA_VERB_12B(0, pin, 0x7ff, 0),	\
-	AZALIA_VERB_12B(0, pin, 0x7ff, 0),	\
-	AZALIA_VERB_12B(0, pin, 0x7ff, 0)
+#define AZALIA_RESET(pin)					\
+	AZALIA_VERB_12B(0, pin, AZALIA_FUNCTION_RESET, 0),	\
+	AZALIA_VERB_12B(0, pin, AZALIA_FUNCTION_RESET, 0),	\
+	AZALIA_VERB_12B(0, pin, AZALIA_FUNCTION_RESET, 0),	\
+	AZALIA_VERB_12B(0, pin, AZALIA_FUNCTION_RESET, 0)
 
-#define AZALIA_SUBVENDOR(codec, val)				\
-	AZALIA_VERB_12B(codec, 1, 0x720, ((val) >>  0) & 0xff),	\
-	AZALIA_VERB_12B(codec, 1, 0x721, ((val) >>  8) & 0xff),	\
-	AZALIA_VERB_12B(codec, 1, 0x722, ((val) >> 16) & 0xff),	\
-	AZALIA_VERB_12B(codec, 1, 0x723, ((val) >> 24) & 0xff)
+#define AZALIA_SUBVENDOR(codec, val)							\
+	AZALIA_VERB_12B(codec, 1, AZALIA_SET_SUBSYSTEM_ID_1, ((val) >>  0) & 0xff),	\
+	AZALIA_VERB_12B(codec, 1, AZALIA_SET_SUBSYSTEM_ID_2, ((val) >>  8) & 0xff),	\
+	AZALIA_VERB_12B(codec, 1, AZALIA_SET_SUBSYSTEM_ID_3, ((val) >> 16) & 0xff),	\
+	AZALIA_VERB_12B(codec, 1, AZALIA_SET_SUBSYSTEM_ID_4, ((val) >> 24) & 0xff)
 
 #endif /* DEVICE_AZALIA_H */

From cbf852734576dc1a7fddfab8549a4cdcb3aab0b7 Mon Sep 17 00:00:00 2001
From: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Date: Sun, 24 Aug 2025 11:00:37 +0900
Subject: [PATCH 1899/3886] device/azalia: Amend the mistake of
 codec_is_operative()

One of my previous commits attempted to simplify azalia_codec_init(),
but resulted in illogical code which also introduced a bug in certain
cases.

To summarize, codec_is_operative() tells the controller to get the
vendor ID of a specific codec. While doing so, this also checks how the
controller and codec respond to see if they are functioning. However, we
read the response in azalia_codec_init(). Therefore, these functions
must be called sequentially in order to initialize the codecs correctly.

In certain cases, we would attempt to read the response without
requesting the vendor ID in the first place. This possibly caused
these verbs to not get loaded at all.

These are the areas affected by the bug:
 - northbridge/intel/haswell/minihd.c
 - soc/intel/broadwell/minihd.c

TEST=Verbs were loaded on HP ProBook 450 G3

Fixes: 516d05f43dad ("device/azalia: Separate codec checking and initialization")

Change-Id: I82ada9e6eca0539b854b5bc61f6f7a88ffd1cdc5
Signed-off-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88918
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/device/azalia_device.c | 28 +++++-----------------------
 1 file changed, 5 insertions(+), 23 deletions(-)

diff --git a/src/device/azalia_device.c b/src/device/azalia_device.c
index f634908daa..fb31d8f7ca 100644
--- a/src/device/azalia_device.c
+++ b/src/device/azalia_device.c
@@ -242,25 +242,12 @@ __weak void mainboard_azalia_program_runtime_verbs(u8 *base, u32 viddid)
 {
 }
 
-static bool codec_is_operative(u8 *base, const int addr)
-{
-	if (wait_for_ready(base) < 0) {
-		printk(BIOS_WARNING, "azalia_audio: controller not ready\n");
-		return false;
-	}
-
-	write32(base + HDA_IC_REG, AZALIA_VERB_GET_VENDOR_ID(addr));
-
-	if (wait_for_valid(base) < 0) {
-		printk(BIOS_NOTICE, "azalia_audio: codec #%d doesn't respond\n", addr);
-		return false;
-	}
-	return true;
-}
-
 void azalia_codec_init(u8 *base, int addr, const u32 *verb_table, u32 verb_table_bytes)
 {
-	const u32 viddid = read32(base + HDA_IR_REG);
+	if (azalia_write_verb(base, AZALIA_VERB_GET_VENDOR_ID(addr)) < 0)
+		return;
+	u32 viddid = read32(base + HDA_IR_REG);
+
 	const u32 *verb;
 	u32 verb_size;
 
@@ -283,15 +270,10 @@ void azalia_codec_init(u8 *base, int addr, const u32 *verb_table, u32 verb_table
 	mainboard_azalia_program_runtime_verbs(base, viddid);
 }
 
-static bool codec_can_init(const u16 codec_mask, u8 *base, const int addr)
-{
-	return codec_mask & (1 << addr) && codec_is_operative(base, addr);
-}
-
 void azalia_codecs_init(u8 *base, u16 codec_mask)
 {
 	for (int i = AZALIA_MAX_CODECS - 1; i >= 0; i--) {
-		if (codec_can_init(codec_mask, base, i))
+		if (codec_mask & BIT(i))
 			azalia_codec_init(base, i, cim_verb_data, cim_verb_data_size);
 	}
 

From 1a9008b2619579368c5901b24f3a90708e3e7503 Mon Sep 17 00:00:00 2001
From: Nico Huber <nico.h@gmx.de>
Date: Sat, 20 Jul 2024 13:17:05 +0200
Subject: [PATCH 1900/3886] device/azalia: Use clrsetbits32() and friends

TEST=Timeless build produces identical binaries

Change-Id: Ic6b0329191598f40d991ce41985ce8ebdf89d68b
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88921
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/device/azalia_device.c | 15 +++------------
 1 file changed, 3 insertions(+), 12 deletions(-)

diff --git a/src/device/azalia_device.c b/src/device/azalia_device.c
index fb31d8f7ca..f894895d6c 100644
--- a/src/device/azalia_device.c
+++ b/src/device/azalia_device.c
@@ -14,12 +14,7 @@ static enum cb_err azalia_set_bits(void *port, u32 mask, u32 val)
 	struct stopwatch sw;
 	u32 reg32;
 
-	/* Write (val & mask) to port */
-	val &= mask;
-	reg32 = read32(port);
-	reg32 &= ~mask;
-	reg32 |= val;
-	write32(port, reg32);
+	clrsetbits32(port, mask, val);
 
 	/* Wait for readback of register to match what was just written to it */
 	stopwatch_init_msecs_expire(&sw, 50);
@@ -71,9 +66,7 @@ static u16 codec_detect(u8 *base)
 	write16(base + HDA_GCAP_REG, read16(base + HDA_GCAP_REG));
 
 	/* clear STATESTS bits (BAR + 0x0e)[14:0] */
-	reg16 = read16(base + HDA_STATESTS_REG);
-	reg16 |= 0x7fff;
-	write16(base + HDA_STATESTS_REG, reg16);
+	setbits16(base + HDA_STATESTS_REG, 0x7fff);
 
 	/* Wait for readback of register to
 	 * match what was just written to it
@@ -183,9 +176,7 @@ static int wait_for_valid(u8 *base)
 	u32 reg32;
 
 	/* Send the verb to the codec */
-	reg32 = read32(base + HDA_ICII_REG);
-	reg32 |= HDA_ICII_BUSY | HDA_ICII_VALID;
-	write32(base + HDA_ICII_REG, reg32);
+	setbits32(base + HDA_ICII_REG, HDA_ICII_BUSY | HDA_ICII_VALID);
 
 	/*
 	 * The timeout is never reached when the codec is functioning properly.

From a8bce33b82c3d4b40d0177169224f70229528c5b Mon Sep 17 00:00:00 2001
From: Kilian Krause <kilian.krause@siemens.com>
Date: Thu, 10 Jul 2025 15:24:30 +0200
Subject: [PATCH 1901/3886] mb/siemens/mc_rpl: Disable Intel Turbo Boost

Disable Intel Turbo Boost on this platform as a first step toward
consistent frequency behavior. This platform requires deterministic
performance characteristics rather than dynamic frequency scaling.

TEST=Boot into OS, read MSR 0x1A0 (IA32_MISC_ENABLE) and verify that bit
38 (Turbo Disable) is set.

Change-Id: I6e89cdaaa56b5e5c70461ac67159c0fc3975a429
Signed-off-by: Kilian Krause <kilian.krause@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88959
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
---
 src/mainboard/siemens/mc_rpl/mainboard.c | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/src/mainboard/siemens/mc_rpl/mainboard.c b/src/mainboard/siemens/mc_rpl/mainboard.c
index fe3e1e6216..e5c399f269 100644
--- a/src/mainboard/siemens/mc_rpl/mainboard.c
+++ b/src/mainboard/siemens/mc_rpl/mainboard.c
@@ -8,6 +8,7 @@
 #include <stdio.h>
 #include <hwilib.h>
 #include <i210.h>
+#include <soc/ramstage.h>
 
 
 #define MAX_PATH_DEPTH		12
@@ -86,6 +87,11 @@ enum cb_err mainboard_get_mac_address(struct device *dev, uint8_t mac[MAC_ADDR_L
 	return CB_ERR;
 }
 
+void mainboard_silicon_init_params(FSP_S_CONFIG *params)
+{
+	params->TurboMode = 0;
+}
+
 static void mainboard_init(void *chip_info)
 {
 	variant_configure_gpio_pads();

From 62b6d1e336aebae7328beba3bacad571ea9476d5 Mon Sep 17 00:00:00 2001
From: Kilian Krause <kilian.krause@siemens.com>
Date: Wed, 16 Jul 2025 14:14:33 +0200
Subject: [PATCH 1902/3886] mb/siemens/mc_rpl: Enable master bit in PCI config
 space if allowed

Some legacy devices need to have the master bit set in the PCI config
due to old drivers not setting it correctly. Set the master bit if the
feature is enabled via Kconfig switch PCI_ALLOW_BUS_MASTER_ANY_DEVICE.

This implementation is similar to the approach used in an earlier
Siemens platform, as implemented in commit 78ec750610e1
("mb/siemens/mc_ehl: Enable master bit in PCI config space if allowed").

TEST=Confirmed bus master enabled via lspci after boot.

Change-Id: I6d358ba7147860fd1383abe667a7006d9a30d542
Signed-off-by: Kilian Krause <kilian.krause@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88963
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/siemens/mc_rpl/mainboard.c | 18 +++++++++++++++++-
 1 file changed, 17 insertions(+), 1 deletion(-)

diff --git a/src/mainboard/siemens/mc_rpl/mainboard.c b/src/mainboard/siemens/mc_rpl/mainboard.c
index e5c399f269..26d1947e73 100644
--- a/src/mainboard/siemens/mc_rpl/mainboard.c
+++ b/src/mainboard/siemens/mc_rpl/mainboard.c
@@ -9,7 +9,9 @@
 #include <hwilib.h>
 #include <i210.h>
 #include <soc/ramstage.h>
-
+#include <device/pci_def.h>
+#include <device/pci_ops.h>
+#include <device/pci_ids.h>
 
 #define MAX_PATH_DEPTH		12
 #define MAX_NUM_MAPPINGS	10
@@ -92,6 +94,19 @@ void mainboard_silicon_init_params(FSP_S_CONFIG *params)
 	params->TurboMode = 0;
 }
 
+static void mainboard_final(void *chip_info)
+{
+	struct device *dev;
+
+	if (CONFIG(PCI_ALLOW_BUS_MASTER_ANY_DEVICE)) {
+		/* Enable bus mastering - target OS requires firmware initialization */
+		dev = dev_find_device(PCI_VID_SIEMENS, 0x403f, 0);
+		if (dev)
+			pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER);
+	}
+}
+
+
 static void mainboard_init(void *chip_info)
 {
 	variant_configure_gpio_pads();
@@ -106,4 +121,5 @@ void __weak variant_devtree_update(void)
 
 struct chip_operations mainboard_ops = {
 	.init = mainboard_init,
+	.final = mainboard_final,
 };

From 4fd3cb35c268ac291c971a8067aa71c6d2540050 Mon Sep 17 00:00:00 2001
From: Jakub Czapiga <czapiga@google.com>
Date: Thu, 28 Aug 2025 09:50:34 +0000
Subject: [PATCH 1903/3886] util/cbmem: Change abort() to exit(1) in die()

Call to abort() in die() causes many tools to assume that the cbmem util
crashed even in case of just incorrect parameters. Changing it to
exit(1) allows for easier error handling by just getting the exit code
instead of having to handle SIGABRT.

Change-Id: Ic59e3479dcbe090a43878bf773409781729146c8
Signed-off-by: Jakub Czapiga <czapiga@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88981
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
---
 util/cbmem/cbmem_util.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/util/cbmem/cbmem_util.h b/util/cbmem/cbmem_util.h
index 738e7d35b9..3df0eabe7d 100644
--- a/util/cbmem/cbmem_util.h
+++ b/util/cbmem/cbmem_util.h
@@ -20,7 +20,7 @@ extern int cbmem_util_verbose;
 #define die(x...)                   \
 	do {                        \
 		fprintf(stderr, x); \
-		abort();            \
+		exit(1);            \
 	} while (0)
 
 struct cbmem_console {

From 00d954977c9572f2af3e2bcfe374e2691717963e Mon Sep 17 00:00:00 2001
From: Benjamin Doron <benjamin.doron@9elements.com>
Date: Fri, 11 Jul 2025 15:20:00 -0400
Subject: [PATCH 1904/3886] util/smmstoretool: Support other block sizes

smmstoretool is effectively a UEFI variable store writing tool, with
a specific emphasis on the SMMSTORE backend implementation.

However, it could also support other backends. Since it's typical for
the variable store to be `n / 2 - 1` blocks, but not typical how large
each block should be, allow this to be overridden on the command line.

This is necessary because in EDK2, the module producing the firmware
volume block protocol, the backend, will initialise a HOB or set PCDs to
indicate the size of the store to the rest of the stack, and an
assertion will be hit if the store has been preseeded by smmstoretool
using differently-sized blocks.

For example, `make CFLAGS=-DSMM_BLOCK_SIZE=8192` builds this for a
firmware volume block protocol implementation with 8K blocks.

Change-Id: I08b78cfb0b591641f09fcf86f40dd31e6b6c9b30
Signed-off-by: Benjamin Doron <benjamin.doron@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88427
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
---
 util/smmstoretool/fv.c | 12 ++++++++----
 1 file changed, 8 insertions(+), 4 deletions(-)

diff --git a/util/smmstoretool/fv.c b/util/smmstoretool/fv.c
index 2744292761..b7744a57e0 100644
--- a/util/smmstoretool/fv.c
+++ b/util/smmstoretool/fv.c
@@ -11,7 +11,9 @@
 #include "udk2017.h"
 
 // The same as in `smmstore.h` header, which isn't in `commonlib`.
+#ifndef SMM_BLOCK_SIZE
 #define SMM_BLOCK_SIZE (64 * 1024)
+#endif
 
 static const EFI_GUID EfiVariableGuid = EFI_VARIABLE_GUID;
 
@@ -37,10 +39,12 @@ bool fv_init(struct mem_range_t fv)
 {
 	if (fv.length % SMM_BLOCK_SIZE != 0) {
 		fprintf(stderr,
-			"Firmware Volume size is not a multiple of 64KiB\n");
+			"Firmware Volume size is not a multiple of the block size (%dKiB)\n",
+			SMM_BLOCK_SIZE / 1024);
 		return false;
 	}
 
+	uint32_t number_of_blocks = fv.length / SMM_BLOCK_SIZE;
 	memset(fv.start, 0xff, fv.length);
 
 	const EFI_FIRMWARE_VOLUME_HEADER vol_hdr = {
@@ -58,7 +62,7 @@ bool fv_init(struct mem_range_t fv)
 			      + sizeof(EFI_FV_BLOCK_MAP_ENTRY),
 		.Revision = EFI_FVH_REVISION,
 		.BlockMap[0] = {
-			.NumBlocks = fv.length / SMM_BLOCK_SIZE,
+			.NumBlocks = number_of_blocks,
 			.Length = SMM_BLOCK_SIZE,
 		},
 	};
@@ -74,9 +78,9 @@ bool fv_init(struct mem_range_t fv)
 
 	const VARIABLE_STORE_HEADER var_store_hdr = {
 		.Signature = EfiAuthenticatedVariableGuid,
-		// Actual size of the storage is block size, the rest is
+		// Actual size of the storage is `n / 2 - 1` blocks, the rest is
 		// Fault Tolerant Write (FTW) space and the FTW spare space.
-		.Size = SMM_BLOCK_SIZE - vol_hdr.HeaderLength,
+		.Size = ((number_of_blocks / 2 - 1) * SMM_BLOCK_SIZE) - vol_hdr.HeaderLength,
 		.Format = VARIABLE_STORE_FORMATTED,
 		.State = VARIABLE_STORE_HEALTHY,
 	};

From 9d67120078242832b3fff7740955a67652042bc4 Mon Sep 17 00:00:00 2001
From: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
Date: Thu, 28 Aug 2025 12:17:48 +0800
Subject: [PATCH 1905/3886] mb/google/moonstone: Create moonstone variant

Create the moonstone variant of the fatcat reference board by copying
the kinmen files to a new directory named for the variant.

BUG=b:441010542
TEST=1. util/abuild/abuild -p none -t google/fatcat -x -a
        make sure the build includes GOOGLE_MOONSTONE
     2. Run part_id_gen tool without any errors

Change-Id: Iad11c892270f6abc53dee12366691a8c987879f0
Signed-off-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88978
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/google/fatcat/Kconfig           |   7 +
 src/mainboard/google/fatcat/Kconfig.name      |   3 +
 .../fatcat/variants/moonstone/Makefile.mk     |   7 +
 .../google/fatcat/variants/moonstone/gpio.c   | 456 ++++++++++++++++++
 .../fatcat/variants/moonstone/hda_verb.c      | 126 +++++
 .../variants/moonstone/include/variant/ec.h   |   8 +
 .../variants/moonstone/include/variant/gpio.h |  11 +
 .../google/fatcat/variants/moonstone/memory.c |  95 ++++
 .../variants/moonstone/memory/Makefile.mk     |   9 +
 .../moonstone/memory/dram_id.generated.txt    |  11 +
 .../moonstone/memory/mem_parts_used.txt       |  16 +
 .../fatcat/variants/moonstone/overridetree.cb | 323 +++++++++++++
 .../fatcat/variants/moonstone/variant.c       |   9 +
 13 files changed, 1081 insertions(+)
 create mode 100644 src/mainboard/google/fatcat/variants/moonstone/Makefile.mk
 create mode 100644 src/mainboard/google/fatcat/variants/moonstone/gpio.c
 create mode 100644 src/mainboard/google/fatcat/variants/moonstone/hda_verb.c
 create mode 100644 src/mainboard/google/fatcat/variants/moonstone/include/variant/ec.h
 create mode 100644 src/mainboard/google/fatcat/variants/moonstone/include/variant/gpio.h
 create mode 100644 src/mainboard/google/fatcat/variants/moonstone/memory.c
 create mode 100644 src/mainboard/google/fatcat/variants/moonstone/memory/Makefile.mk
 create mode 100644 src/mainboard/google/fatcat/variants/moonstone/memory/dram_id.generated.txt
 create mode 100644 src/mainboard/google/fatcat/variants/moonstone/memory/mem_parts_used.txt
 create mode 100644 src/mainboard/google/fatcat/variants/moonstone/overridetree.cb
 create mode 100644 src/mainboard/google/fatcat/variants/moonstone/variant.c

diff --git a/src/mainboard/google/fatcat/Kconfig b/src/mainboard/google/fatcat/Kconfig
index eba870feba..346d88d575 100644
--- a/src/mainboard/google/fatcat/Kconfig
+++ b/src/mainboard/google/fatcat/Kconfig
@@ -138,6 +138,9 @@ config BOARD_GOOGLE_LAPIS
 	select HAVE_SLP_S0_GATE
 	select MAINBOARD_HAS_GOOGLE_STRAUSS_KEYBOARD
 
+config BOARD_GOOGLE_MOONSTONE
+	select BOARD_GOOGLE_MODEL_KINMEN
+
 if BOARD_GOOGLE_FATCAT_COMMON
 
 config BASEBOARD_DIR
@@ -176,6 +179,7 @@ config DRIVER_TPM_I2C_BUS
 	default 0x01 if BOARD_GOOGLE_MODEL_FELINO
 	default 0x03 if BOARD_GOOGLE_MODEL_KINMEN
 	default 0x03 if BOARD_GOOGLE_LAPIS
+	default 0x03 if BOARD_GOOGLE_MOONSTONE
 
 config HAVE_SLP_S0_GATE
 	def_bool n
@@ -193,6 +197,7 @@ config MAINBOARD_PART_NUMBER
 	default "Felino" if BOARD_GOOGLE_MODEL_FELINO
 	default "Kinmen" if BOARD_GOOGLE_MODEL_KINMEN
 	default "Lapis" if BOARD_GOOGLE_LAPIS
+	default "Moonstone" if BOARD_GOOGLE_MOONSTONE
 
 config MEMORY_SOLDERDOWN
 	def_bool n
@@ -206,6 +211,7 @@ config TPM_TIS_ACPI_INTERRUPT
 	default 11 if BOARD_GOOGLE_FRANCKA # GPE0_DW0_11 (GPP_H11)
 	default 66 if BOARD_GOOGLE_MODEL_KINMEN # GPE0_DW2_02 (GPP_E02)
 	default 66 if BOARD_GOOGLE_LAPIS # GPE0_DW2_02 (GPP_E02)
+	default 66 if BOARD_GOOGLE_MOONSTONE # GPE0_DW2_02 (GPP_E02)
 
 # FIXME: update as per board schematics
 config UART_FOR_CONSOLE
@@ -222,6 +228,7 @@ config VARIANT_DIR
 	default "felino" if BOARD_GOOGLE_MODEL_FELINO
 	default "kinmen" if BOARD_GOOGLE_MODEL_KINMEN
 	default "lapis" if BOARD_GOOGLE_LAPIS
+	default "moonstone" if BOARD_GOOGLE_MOONSTONE
 
 config OVERRIDE_DEVICETREE
 	default "variants/\$(CONFIG_VARIANT_DIR)/overridetree.cb"
diff --git a/src/mainboard/google/fatcat/Kconfig.name b/src/mainboard/google/fatcat/Kconfig.name
index 06e24e70f6..46b7158971 100644
--- a/src/mainboard/google/fatcat/Kconfig.name
+++ b/src/mainboard/google/fatcat/Kconfig.name
@@ -40,3 +40,6 @@ config BOARD_GOOGLE_KINMEN
 
 config BOARD_GOOGLE_LAPIS
 	bool "-> Lapis"
+
+config BOARD_GOOGLE_MOONSTONE
+	bool "-> Moonstone"
diff --git a/src/mainboard/google/fatcat/variants/moonstone/Makefile.mk b/src/mainboard/google/fatcat/variants/moonstone/Makefile.mk
new file mode 100644
index 0000000000..cbe8155bd4
--- /dev/null
+++ b/src/mainboard/google/fatcat/variants/moonstone/Makefile.mk
@@ -0,0 +1,7 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
+bootblock-y += gpio.c
+romstage-y += gpio.c
+romstage-y += memory.c
+ramstage-y += gpio.c
+ramstage-$(CONFIG_FW_CONFIG) += variant.c
diff --git a/src/mainboard/google/fatcat/variants/moonstone/gpio.c b/src/mainboard/google/fatcat/variants/moonstone/gpio.c
new file mode 100644
index 0000000000..9a28421783
--- /dev/null
+++ b/src/mainboard/google/fatcat/variants/moonstone/gpio.c
@@ -0,0 +1,456 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <baseboard/gpio.h>
+#include <baseboard/variants.h>
+#include <boardid.h>
+#include <soc/gpio.h>
+
+/* Pad configuration in ramstage*/
+static const struct pad_config gpio_table[] = {
+	/* GPP_A00:     ESPI_IO0_EC_R */
+	/*  GPP_A00 : GPP_A00 ==> ESPI_IO0_EC_R configured on reset, do not touch */
+
+	/* GPP_A01:     ESPI_IO1_EC_R */
+	/*  GPP_A01 : GPP_A01 ==> ESPI_IO1_EC_R configured on reset, do not touch */
+
+	/* GPP_A02:     ESPI_IO2_EC_R */
+	/*  GPP_A02 : GPP_A02 ==> ESPI_IO2_EC_R configured on reset, do not touch */
+
+	/* GPP_A03:     ESPI_IO3_EC_R */
+	/*  GPP_A03 : GPP_A03 ==> ESPI_IO3_EC_R configured on reset, do not touch */
+
+	/* GPP_A04:     ESPI_CS0_EC_R_N */
+	/*  GPP_A04 : GPP_A04 ==> ESPI_CS0_HDR_L configured on reset, do not touch */
+
+	/* GPP_A05:     ESPI_CLK_EC_R */
+	/*  GPP_A05 : GPP_A05 ==> ESPI_CLK_HDR configured on reset, do not touch */
+
+	/* GPP_A06:     ESPI_RST_EC_R_N */
+	/*  GPP_A06 : GPP_A06 ==> ESPI_RST_HDR configured on reset, do not touch */
+
+	/* GPP_A08:     NC */
+	PAD_NC(GPP_A08, NONE),
+	/* GPP_A09:     NC */
+	PAD_NC(GPP_A09, NONE),
+	/* GPP_A10:     NC */
+	PAD_NC(GPP_A10, NONE),
+	/* GPP_A11:     NC */
+	PAD_NC(GPP_A11, NONE),
+	/* GPP_A12:     NC */
+	PAD_NC(GPP_A12, NONE),
+	/* GPP_A13:     MEM_STRAP_0 */
+	PAD_CFG_GPI(GPP_A13, NONE, DEEP),
+	/* GPP_A15:     NC */
+	PAD_NC(GPP_A15, NONE),
+	/* GPP_A16:     BT_RF_KILL_N */
+	PAD_CFG_GPO(GPP_A16, 1, DEEP),
+	/* GPP_A17:     WIFI_RF_KILL_N */
+	PAD_CFG_GPO(GPP_A17, 1, DEEP),
+
+	/* GPP_B00:     USBC_SML_CLK_PD */
+	PAD_CFG_NF(GPP_B00, NONE, DEEP, NF1),
+	/* GPP_B01:     USBC_SML_DATA_PD */
+	PAD_CFG_NF(GPP_B01, NONE, DEEP, NF1),
+	/* GPP_B02:     NC */
+	PAD_NC(GPP_B02, NONE),
+	/* GPP_B03:     NC */
+	PAD_NC(GPP_B03, NONE),
+	/* GPP_B04:     NC */
+	PAD_NC(GPP_B04, NONE),
+	/* GPP_B05:     ISH_GP_1_SNSR_HDR */
+	PAD_CFG_NF(GPP_B05, NONE, DEEP, NF4),
+	/* GPP_B06:     NC */
+	PAD_NC(GPP_B06, NONE),
+	/* GPP_B07:     NC */
+	PAD_NC(GPP_B07, NONE),
+	/* GPP_B08:     NC */
+	PAD_NC(GPP_B08, NONE),
+	/* GPP_B09:     NC */
+	PAD_NC(GPP_B09, NONE),
+	/* GPP_B10:     NC */
+	PAD_NC(GPP_B10, NONE),
+	/* GPP_B11:     USB_OC1 */
+	PAD_CFG_NF(GPP_B11, NONE, DEEP, NF1),
+	/* GPP_B12:     PM_SLP_S0_N */
+	PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1),
+	/* GPP_B13:     PLT_RST_N */
+	PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1),
+	/* GPP_B14:     DISP_HPD4 */
+	PAD_CFG_NF(GPP_B14, NONE, DEEP, NF2),
+	/* GPP_B15:     NC */
+	PAD_NC(GPP_B15, NONE),
+	/* GPP_B16:     GEN5_SSD_PWREN */
+	PAD_CFG_GPO(GPP_B16, 1, PLTRST),
+	/* GPP_B17:     NC */
+	PAD_NC(GPP_B17, NONE),
+	/* GPP_B18:     ISH_I2C2_SDA_SNSR_HDR */
+	/* NOTE: IOSSTAGE: 'Ignore' for S0ix */
+	PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_B18, NONE, DEEP, NF1),
+	/* GPP_B19:     ISH_I2C2_SCL_SNSR_HDR */
+	/* NOTE: IOSSTAGE: 'Ignore' for S0ix */
+	PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_B19, NONE, DEEP, NF1),
+	/* GPP_B20:     NC */
+	PAD_NC(GPP_B20, NONE),
+	/* GPP_B21:     TCP_RETIMER_FORCE_PWR */
+	PAD_CFG_GPO(GPP_B21, 0, DEEP),
+	/* GPP_B22:     ISH_GP_5_SNSR_HDR */
+	PAD_CFG_NF(GPP_B22, NONE, DEEP, NF4),
+	/* GPP_B23:     NC */
+	PAD_NC(GPP_B23, NONE),
+	/* GPP_B24:     MEM_STRAP_3 */
+	PAD_CFG_GPI(GPP_B24, NONE, DEEP),
+	/* GPP_B25:     MEM_STRAP_2 */
+	PAD_CFG_GPI(GPP_B25, NONE, DEEP),
+
+	/* GPP_C00:     NC */
+	PAD_NC(GPP_C00, NONE),
+	/* GPP_C01:     NC */
+	PAD_NC(GPP_C01, NONE),
+	/* GPP_C02:     NC */
+	PAD_NC(GPP_C02, NONE),
+	/* GPP_C03:     NC */
+	PAD_NC(GPP_C03, NONE),
+	/* GPP_C04:     NC */
+	PAD_NC(GPP_C04, NONE),
+	/* GPP_C05:     NC */
+	PAD_NC(GPP_C05, NONE),
+	/* GPP_C06:     EN_FCAM_PWR */
+	PAD_CFG_GPO(GPP_C06, 1, DEEP),
+	/* GPP_C07:     MEM_CH_SEL */
+	PAD_CFG_GPI(GPP_C07, NONE, DEEP),
+	/* GPP_C08:     NC */
+	PAD_NC(GPP_C08, NONE),
+	/* GPP_C09:     NC */
+	PAD_NC(GPP_C09, NONE),
+	/* GPP_C10:     CLKREQ1_X4_GEN5_M2_SSD_N */
+	PAD_CFG_NF(GPP_C10, NONE, DEEP, NF1),
+	/* GPP_C11:     NC */
+	PAD_NC(GPP_C11, NONE),
+	/* GPP_C12:     NC */
+	PAD_NC(GPP_C12, NONE),
+	/* GPP_C13:     CLKREQ4_X1_GEN4_M2_WLAN_N */
+	PAD_CFG_NF(GPP_C13, NONE, DEEP, NF1),
+	/* GPP_C14:     NC */
+	PAD_NC(GPP_C14, NONE),
+	/* GPP_C15:     FPS_RST_N */
+	PAD_CFG_GPO_LOCK(GPP_C15, 1, LOCK_CONFIG),
+	/* GPP_C16:     TBT_LSX0_TXD  */
+	PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1),
+	/* GPP_C17:     TBT_LSX0_RXD  */
+	PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1),
+	/* GPP_C18:     NC */
+	PAD_NC(GPP_C18, NONE),
+	/* GPP_C19:     NC */
+	PAD_NC(GPP_C19, NONE),
+	/* GPP_C20:     TBT_LSX2_TXD */
+	PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1),
+	/* GPP_C21:     TBT_LSX2_RXD */
+	PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1),
+	/* GPP_C22:     DDP3_CTRLCLK */
+	PAD_CFG_NF(GPP_C22, NONE, DEEP, NF2),
+	/* GPP_C23:     DDP3_CTRLDATA */
+	PAD_CFG_NF(GPP_C23, NONE, DEEP, NF2),
+
+	/* GPP_D00:     NC */
+	PAD_NC(GPP_D00, NONE),
+	/* GPP_D01:     NC */
+	PAD_NC(GPP_D01, NONE),
+	/* GPP_D02:     SOC_WP_OD */
+	PAD_CFG_GPI(GPP_D02, NONE, DEEP),
+	/* GPP_D03:     NC */
+	PAD_NC(GPP_D03, NONE),
+	/* GPP_D04:     NC */
+	PAD_NC(GPP_D04, NONE),
+	/* GPP_D05:     disable ISH_UART0_RXD */
+	PAD_NC(GPP_D05, NONE),
+	/* GPP_D07:     NC */
+	PAD_NC(GPP_D07, NONE),
+	/* GPP_D08:     NC */
+	PAD_NC(GPP_D08, NONE),
+	/* GPP_D09:     I2S_MCLK1_OUT */
+	PAD_CFG_NF(GPP_D09, NONE, DEEP, NF2),
+	/* GPP_D10:     HDA_BCLK */
+	PAD_CFG_NF(GPP_D10, NONE, DEEP, NF1),
+	/* GPP_D11:     HDA_SYNC */
+	PAD_CFG_NF(GPP_D11, NONE, DEEP, NF1),
+	/* GPP_D12:     HDA_SDO */
+	PAD_CFG_NF(GPP_D12, NONE, DEEP, NF1),
+	/* GPP_D13:     HDA_SDI0 */
+	PAD_CFG_NF(GPP_D13, NONE, DEEP, NF1),
+	/* GPP_D14:     NC */
+	PAD_NC(GPP_D14, NONE),
+	/* GPP_D15:     NC */
+	PAD_NC(GPP_D15, NONE),
+	/* GPP_D16:	DMIC_CLK */
+	PAD_CFG_NF(GPP_D16, NONE, DEEP, NF3),
+	/* GPP_D17:	DMIC_DATA */
+	PAD_CFG_NF(GPP_D17, NONE, DEEP, NF3),
+	/* GPP_D18:     NC */
+	PAD_NC(GPP_D18, NONE),
+	/* GPP_D19:     NC */
+	PAD_NC(GPP_D19, NONE),
+	/* GPP_D20:     CSE_EARLY_SW */
+	PAD_CFG_GPI_SCI_HIGH(GPP_D20, NONE, DEEP, LEVEL),
+	/* GPP_D21:     NC */
+	PAD_NC(GPP_D21, NONE),
+	/* GPP_D22:     NC */
+	PAD_NC(GPP_D22, NONE),
+	/* GPP_D23:     NC */
+	PAD_NC(GPP_D23, NONE),
+	/* GPP_D24:     MEM_STRAP_1 */
+	PAD_CFG_GPI(GPP_D24, NONE, DEEP),
+	/* GPP_D25:     NC */
+	PAD_NC(GPP_D25, NONE),
+
+	/* GPP_E01:     NC */
+	PAD_NC(GPP_E01, NONE),
+	/* GPP_E02:     GSC_SOC_INT_ODL */
+	PAD_CFG_GPI_APIC_LOCK(GPP_E02, NONE, LEVEL, INVERT, LOCK_CONFIG),
+	/* GPP_E03:     GEN5_SSD_RESET_N */
+	PAD_CFG_GPO(GPP_E03, 1, PLTRST),
+	/* GPP_E05:     TCHSCR_RPT_EN */
+	PAD_CFG_GPO(GPP_E05, 0, PLTRST),
+	/* GPP_E06:     NC */
+	PAD_NC(GPP_E06, NONE),
+	/* GPP_E07 : [] ==> EC_SOC_INT_ODL */
+	PAD_CFG_GPI_APIC_LOCK(GPP_E07, NONE, LEVEL, INVERT, LOCK_CONFIG),
+	/* GPP_E08:     NC */
+	PAD_NC(GPP_E08, NONE),
+	/* GPP_E09:     USB_OC0 */
+	PAD_CFG_NF(GPP_E09, NONE, DEEP, NF1),
+	/* GPP_E10:     NC */
+	PAD_NC(GPP_E10, NONE),
+	/* GPP_E11:     GPSI0_CLK */
+	PAD_CFG_NF(GPP_E11, NONE, DEEP, NF5),
+	/* GPP_E12:     TCHPAD_I2C4_SCL */
+	PAD_CFG_NF(GPP_E12, NONE, DEEP, NF8),
+	/* GPP_E13:     TCHPAD_I2C4_SDA */
+	PAD_CFG_NF(GPP_E13, NONE, DEEP, NF8),
+	/* GPP_E14:     NC */
+	PAD_NC(GPP_E14, NONE),
+	/* GPP_E15:     NC */
+	PAD_NC(GPP_E15, NONE),
+	/* GPP_E16:     NC */
+	PAD_NC(GPP_E16, NONE),
+	/* GPP_E17:     GSPI0_CS0 */
+	PAD_CFG_NF(GPP_E17, NONE, DEEP, NF5),
+	/* GPP_E18:     TCHPAD_INT# */
+	PAD_CFG_GPI_APIC(GPP_E18, NONE, PLTRST, LEVEL, INVERT),
+	/* GPP_E19:     FPMCU_PWREN */
+	PAD_CFG_GPO(GPP_E19, 1, DEEP),
+	/* GPP_E20:     FPMCU_FW_UPDATE */
+	PAD_CFG_GPO_LOCK(GPP_E20, 0, LOCK_CONFIG),
+	/* GPP_E21:     I2C_PMC_PD_INT_N */
+	PAD_CFG_NF(GPP_E21, NONE, DEEP, NF1),
+	/* GPP_E22:     FPS_SOC_INT_L */
+	PAD_CFG_GPI_IRQ_WAKE(GPP_E22, NONE, PWROK, LEVEL, INVERT),
+
+	/* GPP_F00:     M.2_CNV_BRI_DT_BT_UART2_RTS_N */
+	/* NOTE: IOSSTAGE: 'Ignore' for S0ix */
+	PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_F00, NONE, DEEP, NF1),
+	/* GPP_F01:     M.2_CNV_BRI_RSP_BT_UART2_RXD */
+	/* NOTE: IOSSTAGE: 'Ignore' for S0ix */
+	PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_F01, NONE, DEEP, NF1),
+	/* GPP_F02:     M.2_CNV_RGI_DT_BT_UART2_TXD */
+	/* NOTE: IOSSTAGE: 'Ignore' for S0ix */
+	PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_F02, NONE, DEEP, NF1),
+	/* GPP_F03:     M.2_CNV_RGI_RSP_BT_UART2_CTS_N */
+	/* NOTE: IOSSTAGE: 'Ignore' for S0ix */
+	PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_F03, NONE, DEEP, NF1),
+	/* GPP_F04:     CNV_RF_RESET_R_N */
+	/* NOTE: IOSSTAGE: 'Ignore' for S0ix */
+	PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_F04, NONE, DEEP, NF1),
+	/* GPP_F05:     CRF_CLKREQ_R */
+	/* NOTE: IOSSTAGE: 'Ignore' for S0ix */
+	PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_F05, NONE, DEEP, NF3),
+	/* GPP_F06:     NC */
+	PAD_NC(GPP_F06, NONE),
+	/* GPP_F07:     NC */
+	PAD_NC(GPP_F07, NONE),
+	/* GPP_F08:     EN_TCHSCR_PWR */
+	PAD_CFG_GPO(GPP_F08, 1, DEEP),
+	/* GPP_F09:     NC */
+	PAD_NC(GPP_F09, NONE),
+	/* GPP_F10:     ISH_GP_6_SNSR_HDR */
+	PAD_CFG_NF(GPP_F10, NONE, DEEP, NF8),
+	/* GPP_F11:     NC */
+	PAD_NC(GPP_F11, NONE),
+	/* GPP_F12:     TCHSCR_I2C5_SCL */
+	PAD_CFG_NF(GPP_F12, NONE, DEEP, NF8),
+	/* GPP_F13:     TCHSCR_I2C5_SDA */
+	PAD_CFG_NF(GPP_F13, NONE, DEEP, NF8),
+	/* GPP_F14:     GPSI0A_MOSI */
+	PAD_CFG_NF(GPP_F14, NONE, DEEP, NF8),
+	/* GPP_F15:     GSPI0A_MISO */
+	PAD_CFG_NF(GPP_F15, NONE, DEEP, NF8),
+	/* GPP_F16:     TCHSCR_RST_L */
+	PAD_CFG_GPO(GPP_F16, 1, DEEP),
+	/* GPP_F17:     NC */
+	PAD_NC(GPP_F17, NONE),
+	/* GPP_F18:     TCHSCR_INT_L */
+	PAD_CFG_GPI_APIC(GPP_F18, NONE, PLTRST, LEVEL, NONE),
+	/* GPP_F19:     NC */
+	PAD_NC(GPP_F19, NONE),
+	/* GPP_F20:     NC */
+	PAD_NC(GPP_F20, NONE),
+	/* GPP_F22:     NC */
+	PAD_NC(GPP_F22, NONE),
+	/* GPP_F23:     NC */
+	PAD_NC(GPP_F23, NONE),
+
+	/* GPP_H00:     NC */
+	PAD_NC(GPP_H00, NONE),
+	/* GPP_H01:     NC */
+	PAD_NC(GPP_H01, NONE),
+	/* GPP_H02:     NC */
+	PAD_NC(GPP_H02, NONE),
+	/* GPP_H03:     NC */
+	PAD_NC(GPP_H03, NONE),
+	/* GPP_H04:     NC */
+	PAD_NC(GPP_H04, NONE),
+	/* GPP_H05:     NC */
+	PAD_NC(GPP_H05, NONE),
+	/* GPP_H06:     I2C3_SDA_PSS */
+	PAD_CFG_NF(GPP_H06, NONE, DEEP, NF1),
+	/* GPP_H07:     I2C3_SCL_PSS */
+	PAD_CFG_NF(GPP_H07, NONE, DEEP, NF1),
+	/* GPP_H08:     UART0_BUF_RXD */
+	PAD_CFG_NF(GPP_H08, NONE, DEEP, NF1),
+	/* GPP_H09:     UART0_BUF_TXD */
+	PAD_CFG_NF(GPP_H09, NONE, DEEP, NF1),
+	/* GPP_H10:     NC */
+	PAD_NC(GPP_H10, NONE),
+	/* GPP_H11:     NC */
+	PAD_NC(GPP_H11, NONE),
+	/* GPP_H13:     CPU_C10_GATE_N_R */
+	PAD_CFG_NF(GPP_H13, NONE, DEEP, NF1),
+	/* GPP_H14:     NC */
+	PAD_NC(GPP_H14, NONE),
+	/* GPP_H15:     NC */
+	PAD_NC(GPP_H15, NONE),
+	/* GPP_H16:     NC */
+	PAD_NC(GPP_H16, NONE),
+	/* GPP_H17:     NC */
+	PAD_NC(GPP_H17, NONE),
+	/* GPP_H19:     NC */
+	PAD_NC(GPP_H19, NONE),
+	/* GPP_H20:     NC */
+	PAD_NC(GPP_H20, NONE),
+	/* GPP_H21:     NC */
+	PAD_NC(GPP_H21, NONE),
+	/* GPP_H22:     NC */
+	PAD_NC(GPP_H22, NONE),
+
+	/* GPP_S00:     SNDW3_CLK_CODEC */
+	PAD_CFG_NF(GPP_S00, NONE, DEEP, NF1),
+	/* GPP_S01:     SNDW3_DATA0_CODEC */
+	PAD_CFG_NF(GPP_S01, NONE, DEEP, NF1),
+	/* GPP_S02:     SNDW3_DATA1_CODEC */
+	PAD_CFG_NF(GPP_S02, NONE, DEEP, NF1),
+	/* GPP_S03:     SNDW3_DATA2_CODEC */
+	PAD_CFG_NF(GPP_S03, NONE, DEEP, NF1),
+	/* GPP_S04:	DMIC_CLK_A0 */
+	PAD_CFG_NF(GPP_S04, NONE, DEEP, NF5),
+	/* GPP_S05:	DMIC_DATA_0 */
+	PAD_CFG_NF(GPP_S05, NONE, DEEP, NF5),
+	/* GPP_S06:     NC */
+	PAD_NC(GPP_S06, NONE),
+	/* GPP_S07:     NC */
+	PAD_NC(GPP_S07, NONE),
+
+	/* GPP_V00:     PM_BATLOW_N */
+	PAD_CFG_NF(GPP_V00, NONE, DEEP, NF1),
+	/* GPP_V01:     BC_ACOK_MCP */
+	PAD_CFG_NF(GPP_V01, NONE, DEEP, NF1),
+	/* GPP_V02:     LANWAKE_N_R */
+	PAD_CFG_NF(GPP_V02, NONE, DEEP, NF1),
+	/* GPP_V03:     PWRBTN_MCP_N */
+	PAD_CFG_NF(GPP_V03, NONE, DEEP, NF1),
+	/* GPP_V04:     PM_SLP_S3_N */
+	PAD_CFG_NF(GPP_V04, NONE, DEEP, NF1),
+	/* GPP_V05:     PM_SLP_S4_N */
+	PAD_CFG_NF(GPP_V05, NONE, DEEP, NF1),
+	/* GPP_V06:     PM_SLP_A_N */
+	PAD_CFG_NF(GPP_V06, NONE, DEEP, NF1),
+	/* GPP_V07:     SUSCLK */
+	PAD_CFG_NF(GPP_V07, NONE, DEEP, NF1),
+	/* GPP_V08:     SLP_WLAN_N */
+	PAD_CFG_NF(GPP_V08, NONE, DEEP, NF1),
+	/* GPP_V09:     PM_SLP_S5_N */
+	PAD_CFG_NF(GPP_V09, NONE, DEEP, NF1),
+	/* GPP_V10:     LANPHYPC_R_N */
+	PAD_CFG_NF(GPP_V10, NONE, DEEP, NF1),
+	/* GPP_V11:     PM_SLP_LAN_N */
+	PAD_CFG_NF(GPP_V11, NONE, DEEP, NF1),
+	/* GPP_V12:     WAKE_N */
+	PAD_CFG_NF(GPP_V12, NONE, DEEP, NF1),
+	/* GPP_V13:     GPP_V13_CATERR_N */
+	PAD_CFG_NF(GPP_V13, NONE, DEEP, NF1),
+	/* GPP_V14:     GPP_V14_FORCEPR_N */
+	PAD_CFG_NF(GPP_V14, NONE, DEEP, NF1),
+	/* GPP_V15:     GPP_V15_THERMTRIP_N */
+	PAD_CFG_NF(GPP_V15, NONE, DEEP, NF1),
+	/* GPP_V16:     GPP_V16_VCCST_EN */
+	PAD_CFG_NF(GPP_V16, NONE, DEEP, NF1),
+	/* GPP_V17:     SLP_S0_GATE_R */
+	PAD_CFG_GPO(GPP_V17, 1, PLTRST),
+};
+
+/* Early pad configuration in bootblock */
+static const struct pad_config early_gpio_table[] = {
+	/* GPP_H08:     UART0_BUF_RXD */
+	PAD_CFG_NF(GPP_H08, NONE, DEEP, NF1),
+	/* GPP_H09:     UART0_BUF_TXD */
+	PAD_CFG_NF(GPP_H09, NONE, DEEP, NF1),
+	/* GPP_H06: I2C3_SDA_PSS */
+	PAD_CFG_NF(GPP_H06, NONE, DEEP, NF1),
+	/* GPP_H07: I2C3_SCL_PSS */
+	PAD_CFG_NF(GPP_H07, NONE, DEEP, NF1),
+	/* GPP_E02: GSC_SOC_INT_ODL */
+	PAD_CFG_GPI_APIC(GPP_E02, NONE, PLTRST, LEVEL, INVERT),
+};
+
+/* Pad configuration in romstage */
+static const struct pad_config romstage_gpio_table[] = {
+	/* GPP_B16:     GEN5_SSD_PWREN */
+	PAD_CFG_GPO(GPP_B16, 1, PLTRST),
+	/* GPP_C00:     GPP_C0_SMBCLK */
+	PAD_CFG_NF(GPP_C00, NONE, DEEP, NF1),
+	/* GPP_C01:     GPP_C1_SMBDATA */
+	PAD_CFG_NF(GPP_C01, NONE, DEEP, NF1),
+	/* GPP_E03:     GEN5_SSD_RESET_N */
+	PAD_CFG_GPO(GPP_E03, 1, PLTRST),
+	/* GPP_E19:     FPMCU_PWREN */
+	PAD_CFG_GPO(GPP_E19, 0, DEEP),
+	/* GPP_C15:     FPS_RST_N */
+	PAD_CFG_GPO(GPP_C15, 0, DEEP),
+};
+
+const struct pad_config *variant_gpio_table(size_t *num)
+{
+	*num = ARRAY_SIZE(gpio_table);
+	return gpio_table;
+}
+
+const struct pad_config *variant_early_gpio_table(size_t *num)
+{
+	*num = ARRAY_SIZE(early_gpio_table);
+	return early_gpio_table;
+}
+
+/* Create the stub for romstage gpio, typically use for power sequence */
+const struct pad_config *variant_romstage_gpio_table(size_t *num)
+{
+	*num = ARRAY_SIZE(romstage_gpio_table);
+	return romstage_gpio_table;
+}
+
+static const struct cros_gpio cros_gpios[] = {
+	CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE0_NAME),
+	CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE1_NAME),
+	CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE2_NAME),
+	CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE3_NAME),
+	CROS_GPIO_WP_AH(GPIO_PCH_WP, CROS_GPIO_DEVICE4_NAME),
+};
+
+DECLARE_CROS_GPIOS(cros_gpios);
diff --git a/src/mainboard/google/fatcat/variants/moonstone/hda_verb.c b/src/mainboard/google/fatcat/variants/moonstone/hda_verb.c
new file mode 100644
index 0000000000..2f703b78ee
--- /dev/null
+++ b/src/mainboard/google/fatcat/variants/moonstone/hda_verb.c
@@ -0,0 +1,126 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <device/azalia_device.h>
+
+const u32 cim_verb_data[] = {
+	/* coreboot specific header */
+	0x10ec0256,	/* Codec Vendor / Device ID: Realtek ALC256 */
+	0x10ec12ac,	/* Subsystem ID */
+	0x00000013,	/* Number of jacks (NID entries) */
+
+	AZALIA_RESET(0x1),
+	/* NID 0x01, HDA Codec Subsystem ID Verb Table */
+	AZALIA_SUBVENDOR(0, 0x10ec12ac),
+
+	/* Pin Widget Verb Table */
+	/*
+	 * DMIC
+	 * Requirement is to use PCH DMIC. Hence,
+	 * commented out codec's Internal DMIC.
+	 * AZALIA_PIN_CFG(0, 0x12, 0x90A60130),
+	 * AZALIA_PIN_CFG(0, 0x13, 0x40000000),
+	 */
+	/* Pin widget 0x14 - Front (Port-D) */
+	AZALIA_PIN_CFG(0, 0x14, 0x90170110),
+	/* Pin widget 0x18 - NPC */
+	AZALIA_PIN_CFG(0, 0x18, 0x411111F0),
+	/* Pin widget 0x19 - MIC2 (Port-F) */
+	AZALIA_PIN_CFG(0, 0x19, 0x04A11040),
+	/* Pin widget 0x1A - LINE1 (Port-C) */
+	AZALIA_PIN_CFG(0, 0x1a, 0x411111F0),
+	/* Pin widget 0x1B - NPC */
+	AZALIA_PIN_CFG(0, 0x1b, 0x411111F0),
+	/* Pin widget 0x1D - BEEP-IN */
+	AZALIA_PIN_CFG(0, 0x1d, 0x40610041),
+	/* Pin widget 0x1E - NPC */
+	AZALIA_PIN_CFG(0, 0x1e, 0x411111F0),
+	/* Pin widget 0x21 - HP1-OUT (Port-I) */
+	AZALIA_PIN_CFG(0, 0x21, 0x04211020),
+	/*
+	 * Widget node 0x20 - 1
+	 * Codec hidden reset and speaker power 2W/4ohm
+	 */
+	0x0205001A,
+	0x0204C003,
+	0x02050038,
+	0x02047901,
+	/*
+	 * Widget node 0x20 - 2
+	 * Class D power on Reset
+	 */
+	0x0205003C,
+	0x02040354,
+	0x0205003C,
+	0x02040314,
+	/*
+	 * Widget node 0x20 - 3
+	 * Disable AGC and set AGC limit to -1.5dB
+	 */
+	0x02050016,
+	0x02040C50,
+	0x02050012,
+	0x0204EBC1,
+	/*
+	 * Widget node 0x20 - 4
+	 * Set AGC Post gain +1.5dB then Enable AGC
+	 */
+	0x02050013,
+	0x02044023,
+	0x02050016,
+	0x02040E50,
+	/*
+	 * Widget node 0x20 - 5
+	 * Silence detector enabling + Set EAPD to verb control
+	 */
+	0x02050037,
+	0x0204FE15,
+	0x02050010,
+	0x02040020,
+	/*
+	 * Widget node 0x20 - 6
+	 * Silence data mode Threshold (-90dB)
+	 */
+	0x02050030,
+	0x0204A000,
+	0x0205001B,
+	0x02040A4B,
+	/*
+	 * Widget node 0x20 - 7
+	 * Default setting-1
+	 */
+	0x05750003,
+	0x05740DA3,
+	0x02050046,
+	0x02040004,
+	/*
+	 * Widget node 0x20 - 8
+	 * support 1 pin detect two port
+	 */
+	0x02050009,
+	0x0204E003,
+	0x0205000A,
+	0x02047770,
+	/*
+	 * Widget node 0x20 - 9
+	 * To set LDO1/LDO2 as default
+	 */
+	0x02050008,
+	0x02046A0C,
+	0x02050008,
+	0x02046A0C,
+};
+
+const u32 pc_beep_verbs[] = {
+	/* Dos beep path - 1 */
+	0x01470C00,
+	0x02050036,
+	0x02047151,
+	0x01470740,
+	/* Dos beep path - 2 */
+	0x0143b000,
+	0x01470C02,
+	0x01470C02,
+	0x01470C02,
+};
+
+AZALIA_ARRAY_SIZES;
diff --git a/src/mainboard/google/fatcat/variants/moonstone/include/variant/ec.h b/src/mainboard/google/fatcat/variants/moonstone/include/variant/ec.h
new file mode 100644
index 0000000000..4fc0622f15
--- /dev/null
+++ b/src/mainboard/google/fatcat/variants/moonstone/include/variant/ec.h
@@ -0,0 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#ifndef MAINBOARD_EC_H
+#define MAINBOARD_EC_H
+
+#include <baseboard/ec.h>
+
+#endif /* MAINBOARD_GPIO_H */
diff --git a/src/mainboard/google/fatcat/variants/moonstone/include/variant/gpio.h b/src/mainboard/google/fatcat/variants/moonstone/include/variant/gpio.h
new file mode 100644
index 0000000000..cced66807a
--- /dev/null
+++ b/src/mainboard/google/fatcat/variants/moonstone/include/variant/gpio.h
@@ -0,0 +1,11 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#ifndef __MAINBOARD_GPIO_H__
+#define __MAINBOARD_GPIO_H__
+
+#include <baseboard/gpio.h>
+
+/* EC wake is LAN_WAKE# which is a special DeepSX wake pin */
+#define GPE_EC_WAKE	GPE0_LAN_WAK
+
+#endif /* __MAINBOARD_GPIO_H__ */
diff --git a/src/mainboard/google/fatcat/variants/moonstone/memory.c b/src/mainboard/google/fatcat/variants/moonstone/memory.c
new file mode 100644
index 0000000000..4637347562
--- /dev/null
+++ b/src/mainboard/google/fatcat/variants/moonstone/memory.c
@@ -0,0 +1,95 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <baseboard/variants.h>
+#include <soc/romstage.h>
+#include <soc/meminit.h>
+
+static const struct mb_cfg lp5_mem_config = {
+	.type = MEM_TYPE_LP5X,
+
+	.lpx_dq_map = {
+		.ddr0 = {
+			.dq0 = {  13,  14,  12,  15, 11,  10,  8,  9, },
+			.dq1 = {  7,  5,  4,  6,  0,  3,  1,  2 },
+		},
+		.ddr1 = {
+			.dq0 = {  1,  3,  0,  2,  7,  4,  6,  5, },
+			.dq1 = {  12,  13,  14,  15,  11,  10,  9,  8 },
+		},
+		.ddr2 = {
+			.dq0 = {  0,  2,  1,  3,  6,  4,  7,  5 },
+			.dq1 = {  14,  13,  15,  12,  8,  11,  10,  9, },
+		},
+		.ddr3 = {
+			.dq0 = {  6,  5,  7,  4,  2,  3,  1,  0, },
+			.dq1 = {  10,  8,  11,  9,  12,  15,  13,  14 },
+		},
+		.ddr4 = {
+			.dq0 = {  2,  1,  3,  0,  4,  7,  5,  6 },
+			.dq1 = {  15,  14,  12,  13,  9,  11,  10,  8, },
+		},
+		.ddr5 = {
+			.dq0 = {  6,  5,  7,  4,  3,  1,  0,  2, },
+			.dq1 = {  10,  9,  11,  8,  13,  14,  12,  15 },
+		},
+		.ddr6 = {
+			.dq0 = {  9,  8,  11,  10,  14,  12,  13, 15, },
+			.dq1 = {  6,  4,  5,  7,  1,  3,  0,  2 },
+		},
+		.ddr7 = {
+			.dq0 = {  0,  1,  2,  3,  7,  5,  6,  4, },
+			.dq1 = {  14,  13,  15,  12,  10,  8,  11,  9 },
+		},
+	},
+
+	.lpx_dqs_map = {
+		.ddr0 = { .dqs0 = 1, .dqs1 = 0 },
+		.ddr1 = { .dqs0 = 0, .dqs1 = 1 },
+		.ddr2 = { .dqs0 = 0, .dqs1 = 1 },
+		.ddr3 = { .dqs0 = 0, .dqs1 = 1 },
+		.ddr4 = { .dqs0 = 0, .dqs1 = 1 },
+		.ddr5 = { .dqs0 = 0, .dqs1 = 1 },
+		.ddr6 = { .dqs0 = 1, .dqs1 = 0 },
+		.ddr7 = { .dqs0 = 0, .dqs1 = 1 }
+	},
+
+	.ect = true, /* Early Command Training */
+
+	.lp_ddr_dq_dqs_re_training = 1,
+
+	.user_bd = BOARD_TYPE_ULT_ULX,
+
+	.lp5x_config = {
+		.ccc_config = 0xFF,
+	},
+};
+
+const struct mb_cfg *variant_memory_params(void)
+{
+	return &lp5_mem_config;
+}
+
+int variant_memory_sku(void)
+{
+	/*
+	 * Memory configuration board straps
+	 * GPIO_MEM_CONFIG_0	GPP_A13
+	 * GPIO_MEM_CONFIG_1	GPP_D24
+	 * GPIO_MEM_CONFIG_2	GPP_B25
+	 * GPIO_MEM_CONFIG_3    GPP_B24
+	 */
+	gpio_t spd_gpios[] = {
+		GPP_A13,
+		GPP_D24,
+		GPP_B25,
+		GPP_B24,
+	};
+
+	return gpio_base2_value(spd_gpios, ARRAY_SIZE(spd_gpios));
+}
+
+bool variant_is_half_populated(void)
+{
+	/* GPIO_MEM_CH_SEL GPP_C07 */
+	return gpio_get(GPP_C07);
+}
diff --git a/src/mainboard/google/fatcat/variants/moonstone/memory/Makefile.mk b/src/mainboard/google/fatcat/variants/moonstone/memory/Makefile.mk
new file mode 100644
index 0000000000..da3bfa3b2d
--- /dev/null
+++ b/src/mainboard/google/fatcat/variants/moonstone/memory/Makefile.mk
@@ -0,0 +1,9 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+# This is an auto-generated file. Do not edit!!
+# Generated by:
+# util/spd_tools/bin/part_id_gen PTL lp5 src/mainboard/google/fatcat/variants/moonstone/memory src/mainboard/google/fatcat/variants/moonstone/memory/mem_parts_used.txt
+
+SPD_SOURCES =
+SPD_SOURCES += spd/lp5/set-0/spd-7.hex      # ID = 0(0b0000)  Parts = H58G56BK7BX068
+SPD_SOURCES += spd/lp5/set-0/spd-11.hex      # ID = 1(0b0001)  Parts = MT62F1G32D2DS-023 WT:C, H58G56CK8BX146
+SPD_SOURCES += spd/lp5/set-0/spd-10.hex      # ID = 2(0b0010)  Parts = MT62F2G32D4DS-020 WT:F, MT62F2G32D4DS-023 WT:C
diff --git a/src/mainboard/google/fatcat/variants/moonstone/memory/dram_id.generated.txt b/src/mainboard/google/fatcat/variants/moonstone/memory/dram_id.generated.txt
new file mode 100644
index 0000000000..b90e238b88
--- /dev/null
+++ b/src/mainboard/google/fatcat/variants/moonstone/memory/dram_id.generated.txt
@@ -0,0 +1,11 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+# This is an auto-generated file. Do not edit!!
+# Generated by:
+# util/spd_tools/bin/part_id_gen PTL lp5 src/mainboard/google/fatcat/variants/moonstone/memory src/mainboard/google/fatcat/variants/moonstone/memory/mem_parts_used.txt
+
+DRAM Part Name                 ID to assign
+H58G56BK7BX068                 0 (0000)
+MT62F1G32D2DS-023 WT:C         1 (0001)
+MT62F2G32D4DS-020 WT:F         2 (0010)
+H58G56CK8BX146                 1 (0001)
+MT62F2G32D4DS-023 WT:C         2 (0010)
diff --git a/src/mainboard/google/fatcat/variants/moonstone/memory/mem_parts_used.txt b/src/mainboard/google/fatcat/variants/moonstone/memory/mem_parts_used.txt
new file mode 100644
index 0000000000..f4a5069bb5
--- /dev/null
+++ b/src/mainboard/google/fatcat/variants/moonstone/memory/mem_parts_used.txt
@@ -0,0 +1,16 @@
+# This is a CSV file containing a list of memory parts used by this variant.
+# One part per line with an optional fixed ID in column 2.
+# Only include a fixed ID if it is required for legacy reasons!
+# Generated IDs are dependent on the order of parts in this file,
+# so new parts must always be added at the end of the file!
+#
+# Generate an updated Makefile.mk and dram_id.generated.txt by running the
+# part_id_gen tool from util/spd_tools.
+# See util/spd_tools/README.md for more details and instructions.
+
+# Part Name
+H58G56BK7BX068
+MT62F1G32D2DS-023 WT:C
+MT62F2G32D4DS-020 WT:F
+H58G56CK8BX146
+MT62F2G32D4DS-023 WT:C
diff --git a/src/mainboard/google/fatcat/variants/moonstone/overridetree.cb b/src/mainboard/google/fatcat/variants/moonstone/overridetree.cb
new file mode 100644
index 0000000000..624fa76f3b
--- /dev/null
+++ b/src/mainboard/google/fatcat/variants/moonstone/overridetree.cb
@@ -0,0 +1,323 @@
+fw_config
+	field WIFI 2 2
+		option WIFI_CNVI_7		0
+	end
+	field AUDIO 3 5
+		option AUDIO_UNKNOWN		0
+		option AUDIO_ALC721_SNDW	1
+	end
+end
+
+chip soc/intel/pantherlake
+
+	# The initial version temporarily uses the PTL-H,
+	# but the thermal design is based on the PTL-U.
+	# Apply PTL-U's thermal settings here to avoid thermal issues.
+	register "power_limits_config[PTL_H_1_CORE]" = "{
+		.tdp_pl1_override = 15,
+		.tdp_pl2_override = 55,
+		.tdp_pl4 = 152,
+	}"
+
+	register "power_limits_config[PTL_H_2_CORE]" = "{
+		.tdp_pl1_override = 15,
+		.tdp_pl2_override = 55,
+		.tdp_pl4 = 152,
+	}"
+
+	register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC_SKIP)"	# USB2_C0
+	register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC_SKIP)"	# USB2_C1
+	register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)"	# USB_CAMERA
+	register "usb2_ports[4]" = "USB2_PORT_MID(OC0)"		# Type-A Port A0
+	register "usb2_ports[5]" = "USB2_PORT_MID(OC1)"		# Type-A Port A1
+
+	register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)" # USB3.2 Type-A Port A0
+	register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC1)" # USB3.2 Type-A Port A1
+
+	register "tcss_ports[0]" = "TCSS_PORT_DEFAULT(OC_SKIP)" # USB3_C0
+	register "tcss_ports[2]" = "TCSS_PORT_DEFAULT(OC_SKIP)" # USB3_C1
+
+	register "tcss_cap_policy[0]" = "TCSS_TYPE_C_PORT_FULL_FUN"
+	register "tcss_cap_policy[2]" = "TCSS_TYPE_C_PORT_FULL_FUN"
+	register "tcss_cap_policy[3]" = "TCSS_TYPE_C_PORT_FULL_FUN"
+
+	# Enable EDP in PortA
+	register "ddi_port_A_config" = "1"
+	register "ddi_ports_config" = "{
+                [DDI_PORT_A] = DDI_ENABLE_HPD,
+	}"
+
+	# Enable CNVi Wi-Fi and Bluetooth
+	register "cnvi_wifi_core" = "true"
+	register "cnvi_bt_core" = "true"
+
+	register "serial_io_i2c_mode" = "{
+		[PchSerialIoIndexI2C0]  = PchSerialIoPci,
+		[PchSerialIoIndexI2C1] = PchSerialIoDisabled,
+		[PchSerialIoIndexI2C2] = PchSerialIoDisabled,
+		[PchSerialIoIndexI2C3]  = PchSerialIoPci,
+		[PchSerialIoIndexI2C4]  = PchSerialIoPci,
+		[PchSerialIoIndexI2C5]  = PchSerialIoPci,
+	}"
+
+	register "serial_io_gspi_mode" = "{
+		[PchSerialIoIndexGSPI0] = PchSerialIoPci,
+		[PchSerialIoIndexGSPI1] = PchSerialIoDisabled,
+		[PchSerialIoIndexGSPI0A] = PchSerialIoDisabled,
+	}"
+
+	# Intel Common SoC Config
+	#+-------------------+---------------------------+
+	#| Field             |  Value                    |
+	#+-------------------+---------------------------+
+	#| I2C3              | TPM(cr50)                 |
+	#| I2C4              | Touchpad                  |
+	#| I2C5              | Touchscreen               |
+	#+-------------------+---------------------------+
+	register "common_soc_config" = "{
+		/* Render OEM footer logo 100px above from the edge */
+		.logo_bottom_margin = 100,
+		.chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT,
+		.i2c[3] = {
+			.early_init = 1,
+			.speed = I2C_SPEED_FAST,
+		},
+		.i2c[4] = {
+			.speed = I2C_SPEED_FAST,
+		},
+		.i2c[5] = {
+			.speed = I2C_SPEED_FAST,
+		},
+	}"
+
+	device domain 0 on
+		device ref igpu on
+			chip drivers/gfx/generic
+				register "device_count" = "4"
+				# DDIA for eDP
+				register "device[0].name" = ""LCD0""
+				register "device[0].type" = "panel"
+				# HDMI
+				# If HDMI is not enumerated in the kernel, then no GFX device should be added for DDIB
+				register "device[1].name" = ""DD01""
+				# TCP0 (DP-1) for port C0
+				register "device[2].name" = ""DD02""
+				register "device[2].use_pld" = "true"
+				register "device[2].pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(1, 1))"
+				# TCP2 (DP-2) for port C1
+				register "device[3].name" = ""DD03""
+				register "device[3].use_pld" = "true"
+				register "device[3].pld" = "ACPI_PLD_TYPE_C(LEFT, RIGHT, ACPI_PLD_GROUP(2, 1))"
+				device generic 0 on end
+			end
+		end
+
+		device ref iaa off end
+		device ref tbt_pcie_rp0 on end
+		device ref tbt_pcie_rp2 on end
+		device ref tbt_pcie_rp3 on end
+		device ref tcss_xhci on
+			chip drivers/usb/acpi
+				device ref tcss_root_hub on
+					chip drivers/usb/acpi
+						register "desc" = ""USB3 Type-C Port C0""
+						register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
+						register "group" = "ACPI_PLD_GROUP(1, 2)"
+						device ref tcss_usb3_port0 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB3 Type-C Port C1""
+						register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
+						register "group" = "ACPI_PLD_GROUP(2, 2)"
+						device ref tcss_usb3_port2 on end
+					end
+				end
+			end
+		end
+
+		device ref tcss_dma0 on
+			chip drivers/intel/usb4/retimer
+				register "dfp[0].power_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B21)"
+				use tcss_usb3_port0 as dfp[0].typec_port
+				device generic 0 on end
+			end
+		end
+		device ref tcss_dma1 on
+			chip drivers/intel/usb4/retimer
+				register "dfp[0].power_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B21)"
+				use tcss_usb3_port2 as dfp[0].typec_port
+				device generic 0 on end
+			end
+		end
+
+		device ref ish on
+			chip drivers/intel/ish
+				register "add_acpi_dma_property" = "true"
+				device generic 0 on end
+			end
+		end
+
+		device ref xhci on
+			chip drivers/usb/acpi
+				device ref xhci_root_hub on
+					chip drivers/usb/acpi
+						register "desc" = ""USB2 Type-C Port C0""
+						register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
+						register "group" = "ACPI_PLD_GROUP(1, 1)"
+						device ref usb2_port1 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB2 Type-C Port C1""
+						register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
+						register "group" = "ACPI_PLD_GROUP(2, 1)"
+						device ref usb2_port2 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB2 Camera""
+						register "type" = "UPC_TYPE_INTERNAL"
+						register "has_power_resource" = "true"
+						register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C06)"
+						device ref usb2_port3 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB2 Type-A Port 0""
+						register "type" = "UPC_TYPE_A"
+						register "group" = "ACPI_PLD_GROUP(3, 1)"
+						device ref usb2_port5 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB2 Type-A Port 1""
+						register "type" = "UPC_TYPE_A"
+						register "group" = "ACPI_PLD_GROUP(4, 1)"
+						device ref usb2_port6 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB3 Type-A Port 0""
+						register "type" = "UPC_TYPE_USB3_A"
+						register "group" = "ACPI_PLD_GROUP(3, 2)"
+						device ref usb3_port1 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB3 Type-A Port 1""
+						register "type" = "UPC_TYPE_USB3_A"
+						register "group" = "ACPI_PLD_GROUP(4, 2)"
+						device ref usb3_port2 on end
+					end
+				end
+			end
+		end
+
+		device ref pcie_rp9 on
+			register "pcie_rp[PCIE_RP(9)]" = "{
+			.clk_src = 1,
+			.clk_req = 1,
+			.flags = PCIE_RP_CLK_REQ_DETECT | PCIE_RP_LTR | PCIE_RP_AER,
+			}"
+			chip soc/intel/common/block/pcie/rtd3
+				register "is_storage" = "true"
+				register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B16)"
+				register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_E03)"
+				register "srcclk_pin" = "1"
+				device generic 0 on end
+			end
+		end # Gen5 M.2 SSD
+		device ref cnvi_wifi on
+			chip drivers/wifi/generic
+				register "wake" = "GPE0_PME_B0"
+				register "add_acpi_dma_property" = "true"
+				register "enable_cnvi_ddr_rfim" = "true"
+				use cnvi_bluetooth as bluetooth_companion
+				device generic 0 on end
+			end
+		end # CNVi
+
+		device ref cnvi_bluetooth on end
+
+		# NOTE: i2c0 is function 0; hence it needs to be enabled when any of i2c1-5 is enabled.
+		# TPM device is under i2c3. Therefore, i2c0 needs to be enabled anyways.
+		device ref i2c0 on end
+		device ref i2c3 on
+			chip drivers/i2c/tpm
+				register "hid" = ""GOOG0005""
+				register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_E02_IRQ)"
+				device i2c 50 on end
+			end
+		end # I2C3
+		device ref i2c4 on
+			chip drivers/i2c/hid
+				register "generic.hid" = ""PIXA2305""
+				register "generic.desc" = ""PIXA Touchpad""
+				register "generic.irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_E18_IRQ)"
+				# NOTE: pmc_gpe0_dw2 is GPP_E in baseboard devicetree.cb.
+				register "generic.wake" = "GPE0_DW2_18"
+				register "generic.detect" = "1"
+				register "hid_desc_reg_offset" = "0x20"
+				device i2c 68 on end
+			end
+			chip drivers/i2c/hid
+				register "generic.hid" = ""PNP0C50""
+				register "generic.desc" = ""Synaptics Touchpad""
+				register "generic.irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_E18_IRQ)"
+				register "generic.wake" = "GPE0_DW2_18"
+				register "generic.detect" = "1"
+				register "hid_desc_reg_offset" = "0x20"
+				device i2c 2c on end
+			end
+		end # I2C4
+		device ref i2c5 on
+			chip drivers/i2c/hid
+				register "generic.hid" = ""ELAN9004""
+				register "generic.desc" = ""ELAN Touchscreen""
+				register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_F18_IRQ)"
+				register "generic.detect" = "1"
+				register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_F16)"
+				register "generic.reset_delay_ms" = "150"
+				register "generic.reset_off_delay_ms" = "1"
+				register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_F08)"
+				register "generic.enable_delay_ms" = "6"
+				register "generic.enable_off_delay_ms" = "30"
+				register "generic.stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_E05)"
+				register "generic.stop_off_delay_ms" = "1"
+				register "generic.has_power_resource" = "1"
+				register "generic.use_gpio_for_status" = "true"
+				register "hid_desc_reg_offset" = "0x01"
+				device i2c 0x10 on end
+			end
+		end # I2C5
+		device ref gspi0 on
+			chip drivers/spi/acpi
+				register "name" = ""CRFP""
+				register "hid" = "ACPI_DT_NAMESPACE_HID"
+				register "uid" = "1"
+				register "compat_string" = ""google,cros-ec-spi""
+				register "irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_E22_IRQ)"
+				register "wake" = "GPE0_DW2_22"
+				register "has_power_resource" = "true"
+				register "use_gpio_for_status" = "true"
+				register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C15)"
+				register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E19)"
+				register "enable_delay_ms" = "3"
+				device spi 0 on end
+			end
+		end
+
+		device ref smbus on end
+		device ref hda on
+			probe AUDIO AUDIO_ALC721_SNDW
+			chip drivers/intel/soundwire
+				device generic 0 on
+					chip drivers/soundwire/alc711
+						register "desc" = ""Headset Codec""
+						register "alc711_address.version" = "SOUNDWIRE_VERSION_1_2"
+						register "alc711_address.class" = "MIPI_CLASS_SDCA"
+						register "alc711_address.part_id" = "MIPI_DEV_ID_REALTEK_ALC721"
+						# SoundWire Link 3 ID 1
+						device generic 3.1 on
+							probe AUDIO AUDIO_ALC721_SNDW
+						end
+					end
+				end
+			end
+		end
+	end
+end
diff --git a/src/mainboard/google/fatcat/variants/moonstone/variant.c b/src/mainboard/google/fatcat/variants/moonstone/variant.c
new file mode 100644
index 0000000000..4221a5bf8e
--- /dev/null
+++ b/src/mainboard/google/fatcat/variants/moonstone/variant.c
@@ -0,0 +1,9 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <fw_config.h>
+#include <sar.h>
+
+const char *get_wifi_sar_cbfs_filename(void)
+{
+	return get_wifi_sar_fw_config_filename(FW_CONFIG_FIELD(WIFI));
+}

From 4853f16a59a925f518e815a1ee07ff4b0b3ed701 Mon Sep 17 00:00:00 2001
From: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Date: Thu, 28 Aug 2025 14:14:34 +0800
Subject: [PATCH 1906/3886] mb/google/fatcat/var/kinmen: Support new schematic
 changes

Add FW_config support to distinguish schematic changes.
Refer to schamtics MB_V20250826 and DB_V20250821

BUG=b:406050657, b:409148565
TEST=emerge-fatcat coreboot

Change-Id: I074e3aa466c10ad041b70be04ec3abdcab24dc96
Signed-off-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88979
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 .../google/fatcat/variants/kinmen/Makefile.mk |   2 +
 .../google/fatcat/variants/kinmen/fw_config.c | 139 ++++++++++++++++++
 .../google/fatcat/variants/kinmen/gpio.c      |  32 ----
 .../fatcat/variants/kinmen/overridetree.cb    |  86 ++++++++++-
 .../google/fatcat/variants/kinmen/variant.c   |  59 ++++++++
 5 files changed, 278 insertions(+), 40 deletions(-)
 create mode 100644 src/mainboard/google/fatcat/variants/kinmen/fw_config.c

diff --git a/src/mainboard/google/fatcat/variants/kinmen/Makefile.mk b/src/mainboard/google/fatcat/variants/kinmen/Makefile.mk
index cbe8155bd4..eb361dfe89 100644
--- a/src/mainboard/google/fatcat/variants/kinmen/Makefile.mk
+++ b/src/mainboard/google/fatcat/variants/kinmen/Makefile.mk
@@ -3,5 +3,7 @@
 bootblock-y += gpio.c
 romstage-y += gpio.c
 romstage-y += memory.c
+romstage-$(CONFIG_FW_CONFIG) += fw_config.c
 ramstage-y += gpio.c
 ramstage-$(CONFIG_FW_CONFIG) += variant.c
+ramstage-$(CONFIG_FW_CONFIG) += fw_config.c
diff --git a/src/mainboard/google/fatcat/variants/kinmen/fw_config.c b/src/mainboard/google/fatcat/variants/kinmen/fw_config.c
new file mode 100644
index 0000000000..9e7d8f4b03
--- /dev/null
+++ b/src/mainboard/google/fatcat/variants/kinmen/fw_config.c
@@ -0,0 +1,139 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <baseboard/variants.h>
+#include <console/console.h>
+#include <fw_config.h>
+#include <gpio.h>
+#include <inttypes.h>
+
+/* t: base table; o: override table */
+#define GPIO_PADBASED_OVERRIDE(t, o) gpio_padbased_override(t, o, ARRAY_SIZE(o))
+/* t: table */
+#define GPIO_CONFIGURE_PADS(t) gpio_configure_pads(t, ARRAY_SIZE(t))
+
+static const struct pad_config fp_spi_disable_pads[] = {
+	PAD_NC(GPP_C15, NONE),
+	PAD_NC(GPP_E11, NONE),
+	PAD_NC(GPP_E17, NONE),
+	PAD_NC(GPP_E20, NONE),
+	PAD_NC(GPP_E22, NONE),
+	PAD_NC(GPP_F14, NONE),
+	PAD_NC(GPP_F15, NONE),
+};
+
+static const struct pad_config fp_spi_enable_pads[] = {
+	/* GPP_C15:     FPS_RST_N */
+	PAD_CFG_GPO_LOCK(GPP_C15, 1, LOCK_CONFIG),
+	/* GPP_E11:     GPSI0_CLK */
+	PAD_CFG_NF(GPP_E11, NONE, DEEP, NF5),
+	/* GPP_E17:     GSPI0_CS0 */
+	PAD_CFG_NF(GPP_E17, NONE, DEEP, NF5),
+	/* GPP_E20:     FPMCU_FW_UPDATE */
+	PAD_CFG_GPO_LOCK(GPP_E20, 0, LOCK_CONFIG),
+	/* GPP_E22:     FPS_SOC_INT_L */
+	PAD_CFG_GPI_IRQ_WAKE(GPP_E22, NONE, PWROK, LEVEL, INVERT),
+	/* GPP_F14:     GPSI0A_MOSI */
+	PAD_CFG_NF(GPP_F14, NONE, DEEP, NF8),
+	/* GPP_F15:     GSPI0A_MISO */
+	PAD_CFG_NF(GPP_F15, NONE, DEEP, NF8),
+
+};
+
+static const struct pad_config use_usb3c_enable_pads[] = {
+	/* GPP_C20:     NC */
+	PAD_NC(GPP_C20, NONE),
+	/* GPP_C21:     NC */
+	PAD_NC(GPP_C21, NONE),
+	/* GPP_C22:     TBT_LSX3_TXD  */
+	PAD_CFG_NF(GPP_C22, NONE, DEEP, NF1),
+	/* GPP_C23:     TBT_LSX3_RXD  */
+	PAD_CFG_NF(GPP_C23, NONE, DEEP, NF1),
+	/* GPP_B14:     NC */
+	PAD_NC(GPP_B14, NONE),
+	/* GPP_B11:     NC */
+	PAD_NC(GPP_B11, NONE),
+	/* GPP_E09:     NC */
+	PAD_NC(GPP_E09, NONE),
+};
+
+static const struct pad_config use_usb2a2c_hdmi_enable_pads[] = {
+	/* GPP_C20:     TBT_LSX2_TXD */
+	PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1),
+	/* GPP_C21:     TBT_LSX2_RXD */
+	PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1),
+	/* GPP_C22:     DDP3_CTRLCLK */
+	PAD_CFG_NF(GPP_C22, NONE, DEEP, NF2),
+	/* GPP_C23:     DDP3_CTRLDATA */
+	PAD_CFG_NF(GPP_C23, NONE, DEEP, NF2),
+	/* GPP_B14:     DISP_HPD4 */
+	PAD_CFG_NF(GPP_B14, NONE, DEEP, NF2),
+	/* GPP_B11:     USB_OC1 */
+	PAD_CFG_NF(GPP_B11, NONE, DEEP, NF1),
+	/* GPP_E09:     USB_OC0 */
+	PAD_CFG_NF(GPP_E09, NONE, DEEP, NF1),
+};
+
+static const struct pad_config pre_mem_fp_spi_enable_pads[] = {
+	/* GPP_C15:     FPS_RST_N */
+	PAD_CFG_GPO(GPP_C15, 0, DEEP),
+};
+
+void fw_config_configure_pre_mem_gpio(void)
+{
+	if (!fw_config_is_provisioned()) {
+		printk(BIOS_WARNING, "FW_CONFIG is not provisioned, Exiting\n");
+		return;
+	}
+
+	if (fw_config_probe(FW_CONFIG(FPMCU, FP_SPI)))
+		GPIO_CONFIGURE_PADS(pre_mem_fp_spi_enable_pads);
+
+}
+
+void fw_config_gpio_padbased_override(struct pad_config *padbased_table)
+{
+	if (!fw_config_is_provisioned()) {
+		printk(BIOS_WARNING, "FW_CONFIG is not provisioned, Exiting\n");
+		return;
+	}
+	/*
+	 *+-------+--------+-------------+
+	 *|       | FP_SPI | FP_USB      |
+	 *+-------+--------+-------------+
+	 *| FPMCU | GSPI0  | usb2_port6  |
+	 *+-------+--------+-------------+
+	 */
+	if (fw_config_probe(FW_CONFIG(FPMCU, FP_SPI))) {
+		GPIO_PADBASED_OVERRIDE(padbased_table, fp_spi_enable_pads);
+	} else {
+		GPIO_PADBASED_OVERRIDE(padbased_table, fp_spi_disable_pads);
+	}
+	/* Probe fw_config : "IO_PORT" to reconfigure port settings accordingly.
+	 * proto0  : IO_PORT => "USB2A2C_HDMI:0"
+	 * porot1.5: IO_PORT => "USB3C:1"
+	 * +-----------------+------------------+------------------+
+	 *| IO_PORT         | USB2A2C_HDMI     |  USB3C           |
+	 *+-----------------+------------------+------------------+
+	 *| tcss_usb3_port0 | USB4_C0 (MB-TBT) | USB4_C0 (MB-TBT) |
+	 *+-----------------+------------------+------------------+
+	 *| tcss_usb3_port1 | N/A              | USB3.2 C2 (DB)   |
+	 *+-----------------+------------------+------------------+
+	 *| tcss_usb3_port2 | USB4_C1 (MB-TBT) | N/A              |
+	 *+-----------------+------------------+------------------+
+	 *| tcss_usb3_port3 | Fixed HDMI       | USB4_C1 (MB-TBT) |
+	 *+-----------------+------------------+------------------+
+	 *| usb3_port1      | USB3_A0          | N/A              |
+	 *+-----------------+------------------+------------------+
+	 *| usb3_port2      | USB3_A1          | N/A              |
+	 *+-----------------+------------------+------------------+
+	 *| usb2_port5      | USB2_A0          | USB2_C2 (DB)     |
+	 *+-----------------+------------------+------------------+
+	 *| usb2_port6      | USB2_A1          | USB_FP           |
+	 *+-----------------+------------------+------------------+
+	 */
+	if (fw_config_probe(FW_CONFIG(IO_PORT, USB3C))) {
+		GPIO_PADBASED_OVERRIDE(padbased_table, use_usb3c_enable_pads);
+	} else {
+		GPIO_PADBASED_OVERRIDE(padbased_table, use_usb2a2c_hdmi_enable_pads);
+	}
+}
diff --git a/src/mainboard/google/fatcat/variants/kinmen/gpio.c b/src/mainboard/google/fatcat/variants/kinmen/gpio.c
index 9a28421783..7f6aa0cdb7 100644
--- a/src/mainboard/google/fatcat/variants/kinmen/gpio.c
+++ b/src/mainboard/google/fatcat/variants/kinmen/gpio.c
@@ -69,14 +69,10 @@ static const struct pad_config gpio_table[] = {
 	PAD_NC(GPP_B09, NONE),
 	/* GPP_B10:     NC */
 	PAD_NC(GPP_B10, NONE),
-	/* GPP_B11:     USB_OC1 */
-	PAD_CFG_NF(GPP_B11, NONE, DEEP, NF1),
 	/* GPP_B12:     PM_SLP_S0_N */
 	PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1),
 	/* GPP_B13:     PLT_RST_N */
 	PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1),
-	/* GPP_B14:     DISP_HPD4 */
-	PAD_CFG_NF(GPP_B14, NONE, DEEP, NF2),
 	/* GPP_B15:     NC */
 	PAD_NC(GPP_B15, NONE),
 	/* GPP_B16:     GEN5_SSD_PWREN */
@@ -132,8 +128,6 @@ static const struct pad_config gpio_table[] = {
 	PAD_CFG_NF(GPP_C13, NONE, DEEP, NF1),
 	/* GPP_C14:     NC */
 	PAD_NC(GPP_C14, NONE),
-	/* GPP_C15:     FPS_RST_N */
-	PAD_CFG_GPO_LOCK(GPP_C15, 1, LOCK_CONFIG),
 	/* GPP_C16:     TBT_LSX0_TXD  */
 	PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1),
 	/* GPP_C17:     TBT_LSX0_RXD  */
@@ -142,14 +136,6 @@ static const struct pad_config gpio_table[] = {
 	PAD_NC(GPP_C18, NONE),
 	/* GPP_C19:     NC */
 	PAD_NC(GPP_C19, NONE),
-	/* GPP_C20:     TBT_LSX2_TXD */
-	PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1),
-	/* GPP_C21:     TBT_LSX2_RXD */
-	PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1),
-	/* GPP_C22:     DDP3_CTRLCLK */
-	PAD_CFG_NF(GPP_C22, NONE, DEEP, NF2),
-	/* GPP_C23:     DDP3_CTRLDATA */
-	PAD_CFG_NF(GPP_C23, NONE, DEEP, NF2),
 
 	/* GPP_D00:     NC */
 	PAD_NC(GPP_D00, NONE),
@@ -216,12 +202,8 @@ static const struct pad_config gpio_table[] = {
 	PAD_CFG_GPI_APIC_LOCK(GPP_E07, NONE, LEVEL, INVERT, LOCK_CONFIG),
 	/* GPP_E08:     NC */
 	PAD_NC(GPP_E08, NONE),
-	/* GPP_E09:     USB_OC0 */
-	PAD_CFG_NF(GPP_E09, NONE, DEEP, NF1),
 	/* GPP_E10:     NC */
 	PAD_NC(GPP_E10, NONE),
-	/* GPP_E11:     GPSI0_CLK */
-	PAD_CFG_NF(GPP_E11, NONE, DEEP, NF5),
 	/* GPP_E12:     TCHPAD_I2C4_SCL */
 	PAD_CFG_NF(GPP_E12, NONE, DEEP, NF8),
 	/* GPP_E13:     TCHPAD_I2C4_SDA */
@@ -232,18 +214,12 @@ static const struct pad_config gpio_table[] = {
 	PAD_NC(GPP_E15, NONE),
 	/* GPP_E16:     NC */
 	PAD_NC(GPP_E16, NONE),
-	/* GPP_E17:     GSPI0_CS0 */
-	PAD_CFG_NF(GPP_E17, NONE, DEEP, NF5),
 	/* GPP_E18:     TCHPAD_INT# */
 	PAD_CFG_GPI_APIC(GPP_E18, NONE, PLTRST, LEVEL, INVERT),
 	/* GPP_E19:     FPMCU_PWREN */
 	PAD_CFG_GPO(GPP_E19, 1, DEEP),
-	/* GPP_E20:     FPMCU_FW_UPDATE */
-	PAD_CFG_GPO_LOCK(GPP_E20, 0, LOCK_CONFIG),
 	/* GPP_E21:     I2C_PMC_PD_INT_N */
 	PAD_CFG_NF(GPP_E21, NONE, DEEP, NF1),
-	/* GPP_E22:     FPS_SOC_INT_L */
-	PAD_CFG_GPI_IRQ_WAKE(GPP_E22, NONE, PWROK, LEVEL, INVERT),
 
 	/* GPP_F00:     M.2_CNV_BRI_DT_BT_UART2_RTS_N */
 	/* NOTE: IOSSTAGE: 'Ignore' for S0ix */
@@ -279,10 +255,6 @@ static const struct pad_config gpio_table[] = {
 	PAD_CFG_NF(GPP_F12, NONE, DEEP, NF8),
 	/* GPP_F13:     TCHSCR_I2C5_SDA */
 	PAD_CFG_NF(GPP_F13, NONE, DEEP, NF8),
-	/* GPP_F14:     GPSI0A_MOSI */
-	PAD_CFG_NF(GPP_F14, NONE, DEEP, NF8),
-	/* GPP_F15:     GSPI0A_MISO */
-	PAD_CFG_NF(GPP_F15, NONE, DEEP, NF8),
 	/* GPP_F16:     TCHSCR_RST_L */
 	PAD_CFG_GPO(GPP_F16, 1, DEEP),
 	/* GPP_F17:     NC */
@@ -420,10 +392,6 @@ static const struct pad_config romstage_gpio_table[] = {
 	PAD_CFG_NF(GPP_C01, NONE, DEEP, NF1),
 	/* GPP_E03:     GEN5_SSD_RESET_N */
 	PAD_CFG_GPO(GPP_E03, 1, PLTRST),
-	/* GPP_E19:     FPMCU_PWREN */
-	PAD_CFG_GPO(GPP_E19, 0, DEEP),
-	/* GPP_C15:     FPS_RST_N */
-	PAD_CFG_GPO(GPP_C15, 0, DEEP),
 };
 
 const struct pad_config *variant_gpio_table(size_t *num)
diff --git a/src/mainboard/google/fatcat/variants/kinmen/overridetree.cb b/src/mainboard/google/fatcat/variants/kinmen/overridetree.cb
index 624fa76f3b..18a506700f 100644
--- a/src/mainboard/google/fatcat/variants/kinmen/overridetree.cb
+++ b/src/mainboard/google/fatcat/variants/kinmen/overridetree.cb
@@ -6,6 +6,15 @@ fw_config
 		option AUDIO_UNKNOWN		0
 		option AUDIO_ALC721_SNDW	1
 	end
+	field FPMCU 6 7
+		option FP_ABSENT		0
+		option FP_SPI			1
+		option FP_USB			2
+	end
+	field IO_PORT 12 12
+		option USB2A2C_HDMI		0
+		option USB3C			1
+	end
 end
 
 chip soc/intel/pantherlake
@@ -38,6 +47,7 @@ chip soc/intel/pantherlake
 	register "tcss_ports[2]" = "TCSS_PORT_DEFAULT(OC_SKIP)" # USB3_C1
 
 	register "tcss_cap_policy[0]" = "TCSS_TYPE_C_PORT_FULL_FUN"
+	register "tcss_cap_policy[1]" = "TCSS_TYPE_C_PORT_FULL_FUN"
 	register "tcss_cap_policy[2]" = "TCSS_TYPE_C_PORT_FULL_FUN"
 	register "tcss_cap_policy[3]" = "TCSS_TYPE_C_PORT_FULL_FUN"
 
@@ -114,7 +124,12 @@ chip soc/intel/pantherlake
 
 		device ref iaa off end
 		device ref tbt_pcie_rp0 on end
-		device ref tbt_pcie_rp2 on end
+		device ref tbt_pcie_rp1 on
+			probe IO_PORT USB3C
+		end
+		device ref tbt_pcie_rp2 on
+			probe IO_PORT USB2A2C_HDMI
+		end
 		device ref tbt_pcie_rp3 on end
 		device ref tcss_xhci on
 			chip drivers/usb/acpi
@@ -125,11 +140,29 @@ chip soc/intel/pantherlake
 						register "group" = "ACPI_PLD_GROUP(1, 2)"
 						device ref tcss_usb3_port0 on end
 					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB3 Type-C Port C2""
+						register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
+						register "group" = "ACPI_PLD_GROUP(3, 2)"
+						device ref tcss_usb3_port1 on
+							probe IO_PORT USB3C
+						end
+					end
 					chip drivers/usb/acpi
 						register "desc" = ""USB3 Type-C Port C1""
 						register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
 						register "group" = "ACPI_PLD_GROUP(2, 2)"
-						device ref tcss_usb3_port2 on end
+						device ref tcss_usb3_port2 on
+							probe IO_PORT USB2A2C_HDMI
+						end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB3 Type-C Port C1""
+						register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
+						register "group" = "ACPI_PLD_GROUP(2, 2)"
+						device ref tcss_usb3_port3 on
+							probe IO_PORT USB3C
+						end
 					end
 				end
 			end
@@ -146,7 +179,16 @@ chip soc/intel/pantherlake
 			chip drivers/intel/usb4/retimer
 				register "dfp[0].power_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B21)"
 				use tcss_usb3_port2 as dfp[0].typec_port
-				device generic 0 on end
+				device generic 0 on
+					probe IO_PORT USB2A2C_HDMI
+				end
+			end
+			chip drivers/intel/usb4/retimer
+				register "dfp[0].power_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B21)"
+				use tcss_usb3_port3 as dfp[0].typec_port
+				device generic 0 on
+					probe IO_PORT USB3C
+				end
 			end
 		end
 
@@ -172,6 +214,14 @@ chip soc/intel/pantherlake
 						register "group" = "ACPI_PLD_GROUP(2, 1)"
 						device ref usb2_port2 on end
 					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB2 Type-C Port C2""
+						register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
+						register "group" = "ACPI_PLD_GROUP(3, 1)"
+						device ref usb2_port5 on
+							probe IO_PORT USB3C
+						end
+					end
 					chip drivers/usb/acpi
 						register "desc" = ""USB2 Camera""
 						register "type" = "UPC_TYPE_INTERNAL"
@@ -183,25 +233,42 @@ chip soc/intel/pantherlake
 						register "desc" = ""USB2 Type-A Port 0""
 						register "type" = "UPC_TYPE_A"
 						register "group" = "ACPI_PLD_GROUP(3, 1)"
-						device ref usb2_port5 on end
+						device ref usb2_port5 on
+							probe IO_PORT USB2A2C_HDMI
+						end
 					end
 					chip drivers/usb/acpi
 						register "desc" = ""USB2 Type-A Port 1""
 						register "type" = "UPC_TYPE_A"
 						register "group" = "ACPI_PLD_GROUP(4, 1)"
-						device ref usb2_port6 on end
+						device ref usb2_port6 on
+							probe IO_PORT USB2A2C_HDMI
+						end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB2 FPMCU""
+						register "type" = "UPC_TYPE_INTERNAL"
+						register "has_power_resource" = "true"
+						register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E19)"
+						device ref usb2_port6 on
+							probe FPMCU FP_USB
+						end
 					end
 					chip drivers/usb/acpi
 						register "desc" = ""USB3 Type-A Port 0""
 						register "type" = "UPC_TYPE_USB3_A"
 						register "group" = "ACPI_PLD_GROUP(3, 2)"
-						device ref usb3_port1 on end
+						device ref usb3_port1 on
+							probe IO_PORT USB2A2C_HDMI
+						end
 					end
 					chip drivers/usb/acpi
 						register "desc" = ""USB3 Type-A Port 1""
 						register "type" = "UPC_TYPE_USB3_A"
 						register "group" = "ACPI_PLD_GROUP(4, 2)"
-						device ref usb3_port2 on end
+						device ref usb3_port2 on
+							probe IO_PORT USB2A2C_HDMI
+						end
 					end
 				end
 			end
@@ -285,6 +352,7 @@ chip soc/intel/pantherlake
 			end
 		end # I2C5
 		device ref gspi0 on
+			probe FPMCU FP_SPI
 			chip drivers/spi/acpi
 				register "name" = ""CRFP""
 				register "hid" = "ACPI_DT_NAMESPACE_HID"
@@ -297,7 +365,9 @@ chip soc/intel/pantherlake
 				register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C15)"
 				register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E19)"
 				register "enable_delay_ms" = "3"
-				device spi 0 on end
+				device spi 0 on
+					probe FPMCU FP_SPI
+				end
 			end
 		end
 
diff --git a/src/mainboard/google/fatcat/variants/kinmen/variant.c b/src/mainboard/google/fatcat/variants/kinmen/variant.c
index 4221a5bf8e..bf159c7e76 100644
--- a/src/mainboard/google/fatcat/variants/kinmen/variant.c
+++ b/src/mainboard/google/fatcat/variants/kinmen/variant.c
@@ -1,5 +1,8 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
+#include <baseboard/gpio.h>
+#include <baseboard/variants.h>
+#include <console/console.h>
 #include <fw_config.h>
 #include <sar.h>
 
@@ -7,3 +10,59 @@ const char *get_wifi_sar_cbfs_filename(void)
 {
 	return get_wifi_sar_fw_config_filename(FW_CONFIG_FIELD(WIFI));
 }
+
+void variant_update_soc_chip_config(struct soc_intel_pantherlake_config *config)
+{
+	/*
+	 *+-------+--------+-------------+
+	 *|       | FP_SPI | FP_USB      |
+	 *+-------+--------+-------------+
+	 *| FPMCU | GSPI0  | usb2_port6  |
+	 *+-------+--------+-------------+
+	 */
+	if (fw_config_probe(FW_CONFIG(FPMCU, FP_USB))) {
+		printk(BIOS_INFO, "Disable GSPI\n");
+		config->serial_io_gspi_mode[PchSerialIoIndexGSPI0] = PchSerialIoDisabled;
+		printk(BIOS_INFO, "usb2_port6 to FP\n");
+		config->usb2_ports[5] = (struct usb2_port_config) USB2_PORT_MID(OC_SKIP);
+	}
+	/* Probe fw_config : "IO_PORT" to reconfigure port settings accordingly.
+	 * proto0  : IO_PORT => "USB2A2C_HDMI:0"
+	 * porot1.5: IO_PORT => "USB3C:1"
+	 * +-----------------+------------------+------------------+
+	 *| IO_PORT         | USB2A2C_HDMI     |  USB3C           |
+	 *+-----------------+------------------+------------------+
+	 *| tcss_usb3_port0 | USB4_C0 (MB-TBT) | USB4_C0 (MB-TBT) |
+	 *+-----------------+------------------+------------------+
+	 *| tcss_usb3_port1 | N/A              | USB3.2 C2 (DB)   |
+	 *+-----------------+------------------+------------------+
+	 *| tcss_usb3_port2 | USB4_C1 (MB-TBT) | N/A              |
+	 *+-----------------+------------------+------------------+
+	 *| tcss_usb3_port3 | Fixed HDMI       | USB4_C1 (MB-TBT) |
+	 *+-----------------+------------------+------------------+
+	 *| usb3_port1      | USB3_A0          | N/A              |
+	 *+-----------------+------------------+------------------+
+	 *| usb3_port2      | USB3_A1          | N/A              |
+	 *+-----------------+------------------+------------------+
+	 *| usb2_port5      | USB2_A0          | USB2_C2 (DB)     |
+	 *+-----------------+------------------+------------------+
+	 *| usb2_port6      | USB2_A1          | USB_FP           |
+	 *+-----------------+------------------+------------------+
+	 */
+
+	if (fw_config_probe(FW_CONFIG(IO_PORT, USB3C))) {
+		printk(BIOS_INFO, "Disable Type-A Port A0/A1\n");
+		config->usb3_ports[0] = (struct usb3_port_config) USB3_PORT_EMPTY;
+		config->usb3_ports[1] = (struct usb3_port_config) USB3_PORT_EMPTY;
+
+		printk(BIOS_INFO, "usb2_port5 to USB2_C2(DB).\n");
+		config->usb2_ports[4] = (struct usb2_port_config) USB2_PORT_TYPE_C(OC_SKIP);
+
+		printk(BIOS_INFO, "Enable tcss_usb3_port1 to USB3_C2(DB)\n");
+		config->tcss_ports[1] = (struct tcss_port_config) TCSS_PORT_DEFAULT(OC_SKIP);
+		printk(BIOS_INFO, "Disable tcss_usb3_port2\n");
+		config->tcss_ports[2] = (struct tcss_port_config) TCSS_PORT_EMPTY;
+		printk(BIOS_INFO, "Enable tcss_usb3_port3 to USB3_C1(MB)\n");
+		config->tcss_ports[3] = (struct tcss_port_config) TCSS_PORT_DEFAULT(OC_SKIP);
+	}
+}

From 8e5e87a1cf4172177338909273dca2dfcf310cb5 Mon Sep 17 00:00:00 2001
From: Kilian Krause <kilian.krause@siemens.com>
Date: Mon, 14 Jul 2025 15:16:13 +0200
Subject: [PATCH 1907/3886] mb/siemens/mc_rpl1: Configure CPU power limits to
 28W TDP

Set the CPU power limits configuration at the variant level to use 28W
for PL1, PL2. Set PL4 to 64W. This ensures consistent thermal
performance and power management behaviour.

Change-Id: I355f12ad66e9682f3d50356028baea01b42bffa3
Signed-off-by: Kilian Krause <kilian.krause@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88961
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 .../siemens/mc_rpl/variants/mc_rpl1/overridetree.cb         | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/src/mainboard/siemens/mc_rpl/variants/mc_rpl1/overridetree.cb b/src/mainboard/siemens/mc_rpl/variants/mc_rpl1/overridetree.cb
index 9e8da22920..c57481fb41 100644
--- a/src/mainboard/siemens/mc_rpl/variants/mc_rpl1/overridetree.cb
+++ b/src/mainboard/siemens/mc_rpl/variants/mc_rpl1/overridetree.cb
@@ -3,6 +3,12 @@ chip soc/intel/alderlake
 	# seen on J0 and Q0 SKUs
 	register "disable_package_c_state_demotion" = "true"
 
+	register "power_limits_config[RPL_P_682_482_282_28W_CORE]" = "{
+		.tdp_pl1_override = 28,
+		.tdp_pl2_override = 28,
+		.tdp_pl4 = 64,
+	}"
+
 	register "sata_salp_support" = "0"
 	register "sata_speed" = "SATA_GEN2"
 

From c58c988b8e9e3f044a2f717255c17150cf96360e Mon Sep 17 00:00:00 2001
From: Kilian Krause <kilian.krause@siemens.com>
Date: Wed, 16 Jul 2025 14:05:46 +0200
Subject: [PATCH 1908/3886] mb/siemens/mc_rpl: Remove unused code and power
 limit functionality

Remove unused implementation files and declarations:

- Delete ramstage.c containing DPTF power limit configuration
- Remove corresponding ramstage.c reference from Makefile.mk
- Remove unused ADL board ID enumeration in variants.h
- Remove cpu_power_limits structure and variant_update_power_limits()
- Remove variant_devtree_update() function and its weak implementation

The removed code was related to device tree updates and power limit
configurations that are not used by this mainboard.

Change-Id: I1b1c742a4b62022b91de8215d30a4df4f8cf68f0
Signed-off-by: Kilian Krause <kilian.krause@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88962
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/siemens/mc_rpl/Makefile.mk      |  1 -
 .../mc_rpl/include/baseboard/variants.h       | 34 ----------
 src/mainboard/siemens/mc_rpl/mainboard.c      |  6 --
 src/mainboard/siemens/mc_rpl/ramstage.c       | 68 -------------------
 4 files changed, 109 deletions(-)
 delete mode 100644 src/mainboard/siemens/mc_rpl/ramstage.c

diff --git a/src/mainboard/siemens/mc_rpl/Makefile.mk b/src/mainboard/siemens/mc_rpl/Makefile.mk
index b52fe96f2e..75988f66ca 100644
--- a/src/mainboard/siemens/mc_rpl/Makefile.mk
+++ b/src/mainboard/siemens/mc_rpl/Makefile.mk
@@ -6,7 +6,6 @@ romstage-y += romstage_fsp_params.c
 romstage-y += memory.c
 
 ramstage-y += mainboard.c
-ramstage-y += ramstage.c
 
 CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/include
 
diff --git a/src/mainboard/siemens/mc_rpl/include/baseboard/variants.h b/src/mainboard/siemens/mc_rpl/include/baseboard/variants.h
index e27b1773ba..55c68e5e25 100644
--- a/src/mainboard/siemens/mc_rpl/include/baseboard/variants.h
+++ b/src/mainboard/siemens/mc_rpl/include/baseboard/variants.h
@@ -7,26 +7,6 @@
 #include <soc/meminit.h>
 #include <stdint.h>
 
-enum adl_boardid {
-	/* ADL-P LPDDR4 RVPs */
-	ADL_P_LP4_1 = 0x10,
-	ADL_P_LP4_2 = 0x11,
-	/* ADL-P DDR5 RVPs */
-	ADL_P_DDR5_1 = 0x12,
-	ADL_P_DDR5_2 = 0x16,
-	/* ADL-P LPDDR5 RVP */
-	ADL_P_LP5_1 = 0x13,
-	ADL_P_LP5_2 = 0x17,
-	/* ADL-P DDR4 RVPs */
-	ADL_P_DDR4_1 = 0x14,
-	ADL_P_DDR4_2 = 0x3F,
-	/* ADL-M LP4 and LP5 RVPs */
-	ADL_M_LP4 = 0x1,
-	ADL_M_LP5 = 0x2,
-	/* ADL-N LP5 RVP */
-	ADL_N_LP5 = 0x7,
-};
-
 /* Functions to configure GPIO as per variant schematics */
 void variant_configure_gpio_pads(void);
 void variant_configure_early_gpio_pads(void);
@@ -36,18 +16,4 @@ const struct mb_cfg *variant_memory_params(void);
 void rpl_memory_params(FSPM_UPD *memupd);
 void variant_configure_fspm(FSPM_UPD *memupd);
 
-/* Modify devictree settings during ramstage */
-void variant_devtree_update(void);
-struct cpu_power_limits {
-	uint16_t mchid;
-	u8 cpu_tdp;
-	unsigned int pl1_min_power;
-	unsigned int pl1_max_power;
-	unsigned int pl2_min_power;
-	unsigned int pl2_max_power;
-	unsigned int pl4_power;
-};
-/* Modify Power Limit devictree settings during ramstage */
-void variant_update_power_limits(void);
-
 #endif /*__BASEBOARD_VARIANTS_H__ */
diff --git a/src/mainboard/siemens/mc_rpl/mainboard.c b/src/mainboard/siemens/mc_rpl/mainboard.c
index 26d1947e73..0e14064684 100644
--- a/src/mainboard/siemens/mc_rpl/mainboard.c
+++ b/src/mainboard/siemens/mc_rpl/mainboard.c
@@ -111,12 +111,6 @@ static void mainboard_init(void *chip_info)
 {
 	variant_configure_gpio_pads();
 
-	variant_devtree_update();
-}
-
-void __weak variant_devtree_update(void)
-{
-	/* Override dev tree settings per board */
 }
 
 struct chip_operations mainboard_ops = {
diff --git a/src/mainboard/siemens/mc_rpl/ramstage.c b/src/mainboard/siemens/mc_rpl/ramstage.c
deleted file mode 100644
index c1d50f0a00..0000000000
--- a/src/mainboard/siemens/mc_rpl/ramstage.c
+++ /dev/null
@@ -1,68 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-or-later */
-
-#include <acpi/acpi_device.h>
-#include <baseboard/variants.h>
-#include <console/console.h>
-#include <device/pci_ids.h>
-#include <device/pci_ops.h>
-#include <soc/gpio_soc_defs.h>
-#include <soc/pci_devs.h>
-#include <soc/soc_chip.h>
-#include <static.h>
-#include <string.h>
-#include <drivers/intel/dptf/chip.h>
-#include <intelblocks/power_limit.h>
-
-const struct cpu_power_limits limits[] = {
-	/* SKU_ID, TDP (Watts), pl1_min, pl1_max, pl2_min, pl2_max, PL4 */
-	/* PL2 values are for performance configuration */
-	{ PCI_DID_INTEL_ADL_P_ID_7, 15, 3000, 15000,  55000,  55000, 123000 },
-	{ PCI_DID_INTEL_ADL_P_ID_6, 15, 3000, 15000,  55000,  55000, 123000 },
-	{ PCI_DID_INTEL_ADL_P_ID_5, 28, 4000, 28000,  64000,  64000, 140000 },
-	{ PCI_DID_INTEL_ADL_P_ID_3, 28, 4000, 28000,  64000,  64000, 140000 },
-	{ PCI_DID_INTEL_ADL_P_ID_3, 45, 5000, 45000, 115000, 115000, 215000 },
-	{ PCI_DID_INTEL_ADL_N_ID_1, 15, 3000, 15000,  35000,  35000,  83000 },
-	{ PCI_DID_INTEL_ADL_N_ID_2,  6, 3000,  6000,  25000,  25000,  78000 },
-	{ PCI_DID_INTEL_ADL_N_ID_3,  6, 3000,  6000,  25000,  25000,  78000 },
-	{ PCI_DID_INTEL_ADL_N_ID_4,  6, 3000,  6000,  25000,  25000,  78000 },
-	{ PCI_DID_INTEL_ADL_N_ID_5,  6, 3000,  6000,  25000,  25000,  78000 },
-};
-
-WEAK_DEV_PTR(dptf_policy);
-void variant_update_power_limits(void)
-{
-	const struct device *policy_dev = DEV_PTR(dptf_policy);
-	if (!policy_dev)
-		return;
-
-	struct drivers_intel_dptf_config *config = config_of(policy_dev);
-
-	uint16_t mchid = pci_s_read_config16(PCI_DEV(0, 0, 0), PCI_DEVICE_ID);
-
-	u8 tdp = get_cpu_tdp();
-
-	for (size_t i = 0; i < ARRAY_SIZE(limits); i++) {
-		if (mchid == limits[i].mchid && tdp == limits[i].cpu_tdp) {
-			struct dptf_power_limits *settings = &config->controls.power_limits;
-			config_t *conf = config_of_soc();
-			struct soc_power_limits_config *soc_config = conf->power_limits_config;
-			settings->pl1.min_power = limits[i].pl1_min_power;
-			settings->pl1.max_power = limits[i].pl1_max_power;
-			settings->pl2.min_power = limits[i].pl2_min_power;
-			settings->pl2.max_power = limits[i].pl2_max_power;
-			soc_config->tdp_pl4 = DIV_ROUND_UP(limits[i].pl4_power,
-									MILLIWATTS_TO_WATTS);
-			printk(BIOS_INFO, "Overriding power limits PL1 (%u, %u) PL2 (%u, %u) PL4 (%u)\n",
-					limits[i].pl1_min_power,
-					limits[i].pl1_max_power,
-					limits[i].pl2_min_power,
-					limits[i].pl2_max_power,
-					limits[i].pl4_power);
-		}
-	}
-}
-
-void variant_devtree_update(void)
-{
-	variant_update_power_limits();
-}

From 9996fc58fd28d54198728038dc88718f346ec22b Mon Sep 17 00:00:00 2001
From: Kilian Krause <kilian.krause@siemens.com>
Date: Tue, 22 Jul 2025 14:48:50 +0200
Subject: [PATCH 1909/3886] mb/siemens/mc_rpl: Disable C1E state via
 MSR_POWER_CTL

This change disables the C1E (Enhanced Halt State) power saving feature
by clearing bit 1 in the MSR_POWER_CTL register. Disabling C1E prevents
the processor from automatically transitioning to a lower
voltage/frequency when all cores are halted, improving deterministic
behaviour.

For this platform, disabling C1E is always required, so the direct MSR
approach avoids FSP reliability issues and configuration complexity
that would come with using the existing devicetree "enable_c1e"
parameter.

TEST=Booted into OS and verified register MSR_POWER_CTL Bit 1 cleared:
- Used rdmsr tool: rdmsr 0x1FC showed bit 1 = 0
- Confirmed across all CPU cores

Change-Id: If076f0bb42f3a0d4b8f895703e88eaf145e4a762
Signed-off-by: Kilian Krause <kilian.krause@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88964
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
---
 src/mainboard/siemens/mc_rpl/mainboard.c | 14 +++++++++++++-
 1 file changed, 13 insertions(+), 1 deletion(-)

diff --git a/src/mainboard/siemens/mc_rpl/mainboard.c b/src/mainboard/siemens/mc_rpl/mainboard.c
index 0e14064684..28068395c0 100644
--- a/src/mainboard/siemens/mc_rpl/mainboard.c
+++ b/src/mainboard/siemens/mc_rpl/mainboard.c
@@ -12,6 +12,8 @@
 #include <device/pci_def.h>
 #include <device/pci_ops.h>
 #include <device/pci_ids.h>
+#include <cpu/x86/msr.h>
+#include <soc/msr.h>
 
 #define MAX_PATH_DEPTH		12
 #define MAX_NUM_MAPPINGS	10
@@ -94,6 +96,15 @@ void mainboard_silicon_init_params(FSP_S_CONFIG *params)
 	params->TurboMode = 0;
 }
 
+static void disable_c1e(void)
+{
+	msr_t msr;
+
+	msr = rdmsr(MSR_POWER_CTL);
+	msr.lo &= ~(1 << 1);
+	wrmsr(MSR_POWER_CTL, msr);
+}
+
 static void mainboard_final(void *chip_info)
 {
 	struct device *dev;
@@ -104,8 +115,9 @@ static void mainboard_final(void *chip_info)
 		if (dev)
 			pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER);
 	}
-}
 
+	disable_c1e();
+}
 
 static void mainboard_init(void *chip_info)
 {

From c590e8e75cf496b91c57355487ea12916ed7d453 Mon Sep 17 00:00:00 2001
From: John Su <john_su@compal.corp-partner.google.com>
Date: Mon, 25 Aug 2025 17:55:15 +0800
Subject: [PATCH 1910/3886] mb/brya/var/uldrenite: Increase Touch IC enable
 delay time
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

According to the datasheet and the LCD team’s response, increase Touch
IC enable delay time to resolve touch failure after resume.

BUG=b:441010546
TEST=Checked the waveform and suspend stress test, both checked OK.
Meet seconds_system_resume < 0.5 sec, boot time < 1.3 sec.

Change-Id: I778fd79f7bad3ad1873880b7412c0c49dcb40b1f
Signed-off-by: John Su <john_su@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88934
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
---
 .../google/brya/variants/uldrenite/overridetree.cb          | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/src/mainboard/google/brya/variants/uldrenite/overridetree.cb b/src/mainboard/google/brya/variants/uldrenite/overridetree.cb
index 8b17bd94c2..6dc7d4218f 100644
--- a/src/mainboard/google/brya/variants/uldrenite/overridetree.cb
+++ b/src/mainboard/google/brya/variants/uldrenite/overridetree.cb
@@ -367,7 +367,7 @@ chip soc/intel/alderlake
 				register "stop_delay_ms" = "150"
 				register "stop_off_delay_ms" = "2"
 				register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E17)"
-				register "enable_delay_ms" = "1"
+				register "enable_delay_ms" = "6"
 				register "has_power_resource" = "true"
 				device i2c 10 on
 					probe TOUCHSCREEN TOUCHSCREEN_UNKNOWN
@@ -418,7 +418,7 @@ chip soc/intel/alderlake
 				register "generic.stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A21)"
 				register "generic.stop_delay_ms" = "130"
 				register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E17)"
-				register "generic.enable_delay_ms" = "1"
+				register "generic.enable_delay_ms" = "10"
 				register "generic.has_power_resource" = "1"
 				register "hid_desc_reg_offset" = "0x20"
 				device i2c 2c on
@@ -435,7 +435,7 @@ chip soc/intel/alderlake
 				register "generic.stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A21)"
 				register "generic.stop_delay_ms" = "130"
 				register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E17)"
-				register "generic.enable_delay_ms" = "1"
+				register "generic.enable_delay_ms" = "10"
 				register "generic.has_power_resource" = "1"
 				register "hid_desc_reg_offset" = "0x20"
 				device i2c 3c on

From eb9a673a8e8db1b9a2d61ad2f9e00acfcde55f44 Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Fri, 22 Aug 2025 17:44:11 -0500
Subject: [PATCH 1911/3886] soc/amd/cezanne: Add a Kconfig option for
 SERIRQ_CONTINUOUS_MODE

Add a Kconfig to enable mainboards to select SERIRQ_CONTINUOUS_MODE,
which will be used by a to-be-added Cezanne-based Starlabs Starbook
variant in a subsequent commit.

Change-Id: Ia4da699e836e8e3ca408b4b5744320723e17ca62
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88972
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
---
 src/soc/amd/cezanne/Kconfig | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/src/soc/amd/cezanne/Kconfig b/src/soc/amd/cezanne/Kconfig
index ebe96e40d9..5588262119 100644
--- a/src/soc/amd/cezanne/Kconfig
+++ b/src/soc/amd/cezanne/Kconfig
@@ -478,4 +478,11 @@ config RWB_REGION_ONLY
 
 endif # VBOOT_SLOTS_RW_AB && VBOOT_STARTS_BEFORE_BOOTBLOCK
 
+config SERIRQ_CONTINUOUS_MODE
+	bool
+	default n
+	help
+	  Set this option to y for serial IRQ in continuous mode.
+	  Otherwise it is in quiet mode.
+
 endif # SOC_AMD_CEZANNE

From c3071b7150329be7cada85e74fe197e9a39379ca Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Wed, 27 Aug 2025 15:40:26 -0500
Subject: [PATCH 1912/3886] soc/amd/cezanne/fsp_m_params: add UPD pointer
 parameter to mb callback

This allows the mainboard code to change FSP-M parameters depending on
parameters that are only known at run time and not at build time.

Mirrors change previous done for Mendocino and newer SoCs.

Change-Id: I6790648da3724a06a127c1cef939366588668440
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88973
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
---
 src/mainboard/google/guybrush/romstage.c               | 2 +-
 src/soc/amd/cezanne/fsp_m_params.c                     | 4 ++--
 src/soc/amd/cezanne/include/soc/platform_descriptors.h | 2 +-
 3 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/src/mainboard/google/guybrush/romstage.c b/src/mainboard/google/guybrush/romstage.c
index 96ac0e6b7a..e02c12c0d5 100644
--- a/src/mainboard/google/guybrush/romstage.c
+++ b/src/mainboard/google/guybrush/romstage.c
@@ -3,7 +3,7 @@
 #include <baseboard/variants.h>
 #include <soc/platform_descriptors.h>
 
-void mb_pre_fspm(void)
+void mb_pre_fspm(FSP_M_CONFIG *mcfg)
 {
 	size_t base_num_gpios, override_num_gpios;
 	const struct soc_amd_gpio *base_gpios, *override_gpios;
diff --git a/src/soc/amd/cezanne/fsp_m_params.c b/src/soc/amd/cezanne/fsp_m_params.c
index 5349a166f6..5b20439931 100644
--- a/src/soc/amd/cezanne/fsp_m_params.c
+++ b/src/soc/amd/cezanne/fsp_m_params.c
@@ -16,7 +16,7 @@
 #include <vendorcode/amd/fsp/cezanne/FspUsb.h>
 #include "chip.h"
 
-__weak void mb_pre_fspm(void)
+__weak void mb_pre_fspm(FSP_M_CONFIG *mcfg)
 {
 }
 
@@ -181,5 +181,5 @@ void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version)
 
 	fsp_fill_pcie_ddi_descriptors(mcfg);
 	fsp_assign_ioapic_upds(mcfg);
-	mb_pre_fspm();
+	mb_pre_fspm(mcfg);
 }
diff --git a/src/soc/amd/cezanne/include/soc/platform_descriptors.h b/src/soc/amd/cezanne/include/soc/platform_descriptors.h
index d6d65f05be..7914798712 100644
--- a/src/soc/amd/cezanne/include/soc/platform_descriptors.h
+++ b/src/soc/amd/cezanne/include/soc/platform_descriptors.h
@@ -12,6 +12,6 @@ void mainboard_get_dxio_ddi_descriptors(
 		const fsp_dxio_descriptor **dxio_descs, size_t *dxio_num,
 		const fsp_ddi_descriptor **ddi_descs, size_t *ddi_num);
 
-void mb_pre_fspm(void);
+void mb_pre_fspm(FSP_M_CONFIG *mcfg);
 
 #endif /* AMD_CEZANNE_PLATFORM_DESCRIPTORS_H */

From fc62ffab4824b6685fad95e164bb68cad70f84b1 Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Wed, 27 Aug 2025 16:09:28 -0500
Subject: [PATCH 1913/3886] soc/amd/common/fsp/dmi: Skip parsing when memory
 type UNKNOWN

FSP sets the MemoryType to 0x2 (MEMORY_TYPE_UNKNOWN) when a DIMM is not
present in a given slot, so skip parsing of any DMI records with that
type set.

TEST=build/boot out-of-tree Starlabs Cezanne-based board with a single
sodimm installed, verify the DMI record for the empty slot is not
parsed/inserted into the SMBIOS tables.

Change-Id: I683c7bf65cc261b6a4fc4cb74e7b4b5f96283f61
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88974
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/soc/amd/common/fsp/dmi.c | 9 ++++++---
 1 file changed, 6 insertions(+), 3 deletions(-)

diff --git a/src/soc/amd/common/fsp/dmi.c b/src/soc/amd/common/fsp/dmi.c
index f820e73139..fa630ff02e 100644
--- a/src/soc/amd/common/fsp/dmi.c
+++ b/src/soc/amd/common/fsp/dmi.c
@@ -218,9 +218,12 @@ static void prepare_dmi_16_17(void *unused)
 	for (unsigned int channel = 0; channel < AGESA_STRUCT_CHANNELS_PER_SOCKET; channel++) {
 		for (unsigned int dimm = 0; dimm < AGESA_STRUCT_DIMMS_PER_CHANNEL; dimm++) {
 			type17_dmi_info = &dmi_table->T17[0][channel][dimm];
-			/* DIMMs that are present will have a non-zero
-			   handle. */
-			if (type17_dmi_info->Handle == 0)
+			/*
+			 * DIMMs that are present will always have a non-zero handle.
+			 * FSP will set the MemoryType to UNKNOWN if DIMM not present.
+			 */
+			if (type17_dmi_info->Handle == 0 ||
+					type17_dmi_info->MemoryType == MEMORY_TYPE_UNKNOWN)
 				continue;
 			print_dmi_info(type17_dmi_info);
 			dimm_info = &mem_info->dimm[dimm_cnt];

From f02e755364702fa4dabdbb1c024ff50428ee538d Mon Sep 17 00:00:00 2001
From: Schumi Chu <schumi.chu@mitaccomputing.com>
Date: Thu, 28 Aug 2025 11:27:35 +0800
Subject: [PATCH 1914/3886] config/builder/mitac: Hook up public FSP repo and
 microcode

For following Mitac Computing platforms:
  sc513g6 and r520g6sb

TEST=Build and boot on Mitac Computing/sc513g6 platform
TEST=Build and boot on Mitac Computing/r520g6sb platform

Change-Id: I57b82e8e836e3ee798c026d3aa43fb8ab969e2c6
Signed-off-by: Schumi Chu <schumi.chu@mitaccomputing.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88975
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
---
 configs/builder/config.mitaccomputing.r520g6sb | 8 --------
 configs/builder/config.mitaccomputing.sc513g6  | 8 --------
 2 files changed, 16 deletions(-)

diff --git a/configs/builder/config.mitaccomputing.r520g6sb b/configs/builder/config.mitaccomputing.r520g6sb
index cf1f9402c0..2fe558cbcc 100644
--- a/configs/builder/config.mitaccomputing.r520g6sb
+++ b/configs/builder/config.mitaccomputing.r520g6sb
@@ -15,8 +15,6 @@ CONFIG_NO_GFX_INIT=y
 CONFIG_HAVE_IFD_BIN=y
 CONFIG_HAVE_PBP_BIN=n
 CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION=y
-CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y
-CONFIG_ADD_FSP_BINARIES=y
 CONFIG_PAYLOAD_LINUX=y
 
 CONFIG_UART_FOR_CONSOLE=0
@@ -29,12 +27,6 @@ CONFIG_COREBOOT_ROMSIZE_KB_65536=y
 #
 CONFIG_IFD_BIN_PATH="site-local/r520g6sb/descriptor.bin"
 CONFIG_PBP_BIN_PATH=""
-CONFIG_CPU_UCODE_BINARIES="site-local/r520g6sb/ucode.mcb"
-CONFIG_FSP_T_FILE="site-local/r520g6sb/Server_T.fd"
-CONFIG_FSP_M_FILE="site-local/r520g6sb/Server_M.fd"
-CONFIG_FSP_S_FILE="site-local/r520g6sb/Server_S.fd"
-CONFIG_FSP_HEADER_PATH="src/vendorcode/intel/fsp/fsp2_0/graniterapids/sp/"
-
 CONFIG_PAYLOAD_FILE="site-local/r520g6sb/bzImage"
 CONFIG_LINUX_COMMAND_LINE="loglevel=7 earlyprintk=serial,ttyS0,115200 console=ttyS0,115200"
 
diff --git a/configs/builder/config.mitaccomputing.sc513g6 b/configs/builder/config.mitaccomputing.sc513g6
index 63334687b9..fbec481500 100644
--- a/configs/builder/config.mitaccomputing.sc513g6
+++ b/configs/builder/config.mitaccomputing.sc513g6
@@ -15,8 +15,6 @@ CONFIG_NO_GFX_INIT=y
 CONFIG_HAVE_IFD_BIN=y
 CONFIG_HAVE_PBP_BIN=n
 CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION=y
-CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y
-CONFIG_ADD_FSP_BINARIES=y
 CONFIG_PAYLOAD_LINUX=y
 
 CONFIG_UART_FOR_CONSOLE=0
@@ -29,12 +27,6 @@ CONFIG_COREBOOT_ROMSIZE_KB_65536=y
 #
 CONFIG_IFD_BIN_PATH="site-local/sc513g6/descriptor.bin"
 CONFIG_PBP_BIN_PATH=""
-CONFIG_CPU_UCODE_BINARIES="site-local/sc513g6/ucode.mcb"
-CONFIG_FSP_T_FILE="site-local/sc513g6/Server_T.fd"
-CONFIG_FSP_M_FILE="site-local/sc513g6/Server_M.fd"
-CONFIG_FSP_S_FILE="site-local/sc513g6/Server_S.fd"
-CONFIG_FSP_HEADER_PATH="src/vendorcode/intel/fsp/fsp2_0/graniterapids/sp/"
-
 CONFIG_PAYLOAD_FILE="site-local/sc513g6/bzImage"
 CONFIG_LINUX_COMMAND_LINE="loglevel=7 earlyprintk=serial,ttyS0,115200 console=ttyS0,115200"
 

From 725ab7b06604639d4e4dfbc4e833353914bf00de Mon Sep 17 00:00:00 2001
From: Ingo Reitz <9l@9lo.re>
Date: Fri, 29 Aug 2025 05:35:06 +0200
Subject: [PATCH 1915/3886] soc/mediatek/common: Increase
 WAIT_AUX_READY_TIME_MS

Increase WAIT_AUX_READY_TIME_MS from 1 ms to 3 ms fix a 20s timeout bug
on Google/Cherry/Tomato and possibly other MediaTek Chromebooks
introduced in commit 6ba2df9be5 (soc/mediatek/common: Use polling to
reduce eDP HPD wait time).

Change-Id: I6f41c3733e67c85e4aea3ce3b641a98cad94715c
Signed-off-by: Ingo Reitz <9l@9lo.re>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88991
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
---
 src/soc/mediatek/common/dp/include/soc/dptx_common.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/soc/mediatek/common/dp/include/soc/dptx_common.h b/src/soc/mediatek/common/dp/include/soc/dptx_common.h
index 8a42a63996..fb3c1daf57 100644
--- a/src/soc/mediatek/common/dp/include/soc/dptx_common.h
+++ b/src/soc/mediatek/common/dp/include/soc/dptx_common.h
@@ -70,7 +70,7 @@
 #define MAX_LANECOUNT				4
 
 #define HPD_WAIT_TIMEOUT_MS			200
-#define WAIT_AUX_READY_TIME_MS			1
+#define WAIT_AUX_READY_TIME_MS			3
 
 enum {
 	DP_LANECOUNT_1	= 0x1,

From 87f5d4c54a28727d1b844ff855dae3d034e2e10a Mon Sep 17 00:00:00 2001
From: Elyes Haouas <ehaouas@noos.fr>
Date: Sat, 30 Aug 2025 16:11:24 +0200
Subject: [PATCH 1916/3886] tree: use boolean for PcieRpLtrEnable[]

PcieRpLtrEnable[] is a boolean, so use true false.

Change-Id: I3ccc64d7bb1a756efe8fc109c51c029a5483c316
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89000
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
---
 .../sklkbl_thinkpad/variants/t480/overridetree.cb      | 10 +++++-----
 .../sklkbl_thinkpad/variants/t480s/overridetree.cb     | 10 +++++-----
 .../starlabs/starbook/variants/tgl/devicetree.cb       |  2 +-
 3 files changed, 11 insertions(+), 11 deletions(-)

diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480/overridetree.cb b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480/overridetree.cb
index 14cbb7a050..3b05ae9fdc 100644
--- a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480/overridetree.cb
+++ b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480/overridetree.cb
@@ -41,7 +41,7 @@ chip soc/intel/skylake
 			register "PcieRpClkReqNumber[0]"		= "0"
 			register "PcieRpClkSrcNumber[0]"		= "0"
 			register "PcieRpAdvancedErrorReporting[0]"	= "1"
-			register "PcieRpLtrEnable[0]"			= "1"
+			register "PcieRpLtrEnable[0]"			= "true"
 			device generic 0 alias dgpu on end
 		end
 
@@ -59,7 +59,7 @@ chip soc/intel/skylake
 			register "PcieRpClkReqNumber[6]"		= "2"
 			register "PcieRpClkSrcNumber[6]"		= "2"
 			register "PcieRpAdvancedErrorReporting[6]"	= "1"
-			register "PcieRpLtrEnable[6]"			= "1"
+			register "PcieRpLtrEnable[6]"			= "true"
 		end
 
 		# M.2 WWAN - x2
@@ -68,7 +68,7 @@ chip soc/intel/skylake
 			register "PcieRpClkReqNumber[4]"		= "3"
 			register "PcieRpClkSrcNumber[4]"		= "3"
 			register "PcieRpAdvancedErrorReporting[4]"	= "1"
-			register "PcieRpLtrEnable[4]"			= "1"
+			register "PcieRpLtrEnable[4]"			= "true"
 		end
 
 		# TB3 (Alpine Ridge LP) - x2
@@ -77,7 +77,7 @@ chip soc/intel/skylake
 			register "PcieRpClkReqNumber[8]"		= "4"
 			register "PcieRpClkSrcNumber[8]"		= "4"
 			register "PcieRpAdvancedErrorReporting[8]"	= "1"
-			register "PcieRpLtrEnable[8]"			= "1"
+			register "PcieRpLtrEnable[8]"			= "true"
 			register "PcieRpHotPlug[8]"			= "1"
 		end
 
@@ -87,7 +87,7 @@ chip soc/intel/skylake
 			register "PcieRpClkReqNumber[10]"		= "5"
 			register "PcieRpClkSrcNumber[10]"		= "5"
 			register "PcieRpAdvancedErrorReporting[10]"	= "1"
-			register "PcieRpLtrEnable[10]"			= "1"
+			register "PcieRpLtrEnable[10]"			= "true"
 		end
 	end
 end
diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/overridetree.cb b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/overridetree.cb
index 50de1a09d7..6a933c42c8 100644
--- a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/overridetree.cb
+++ b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/overridetree.cb
@@ -41,7 +41,7 @@ chip soc/intel/skylake
 			register "PcieRpClkReqNumber[0]"		= "0"
 			register "PcieRpClkSrcNumber[0]"		= "0"
 			register "PcieRpAdvancedErrorReporting[0]"	= "1"
-			register "PcieRpLtrEnable[0]"			= "1"
+			register "PcieRpLtrEnable[0]"			= "true"
 			device generic 0 alias dgpu on end
 		end
 
@@ -51,7 +51,7 @@ chip soc/intel/skylake
 			register "PcieRpClkReqNumber[3]"		= "1"
 			register "PcieRpClkSrcNumber[3]"		= "1"
 			register "PcieRpAdvancedErrorReporting[3]"	= "1"
-			register "PcieRpLtrEnable[3]"			= "1"
+			register "PcieRpLtrEnable[3]"			= "true"
 		end
 
 		# Ethernet (clobbers RP8)
@@ -68,7 +68,7 @@ chip soc/intel/skylake
 			register "PcieRpClkReqNumber[6]"		= "3"
 			register "PcieRpClkSrcNumber[6]"		= "3"
 			register "PcieRpAdvancedErrorReporting[6]"	= "1"
-			register "PcieRpLtrEnable[6]"			= "1"
+			register "PcieRpLtrEnable[6]"			= "true"
 		end
 
 		# TB3 (Alpine Ridge LP) - x2
@@ -77,7 +77,7 @@ chip soc/intel/skylake
 			register "PcieRpClkReqNumber[4]"		= "4"
 			register "PcieRpClkSrcNumber[4]"		= "4"
 			register "PcieRpAdvancedErrorReporting[4]"	= "1"
-			register "PcieRpLtrEnable[4]"			= "1"
+			register "PcieRpLtrEnable[4]"			= "true"
 			register "PcieRpHotPlug[4]"			= "1"
 		end
 
@@ -87,7 +87,7 @@ chip soc/intel/skylake
 			register "PcieRpClkReqNumber[8]"		= "5"
 			register "PcieRpClkSrcNumber[8]"		= "5"
 			register "PcieRpAdvancedErrorReporting[8]"	= "1"
-			register "PcieRpLtrEnable[8]"			= "1"
+			register "PcieRpLtrEnable[8]"			= "true"
 		end
 	end
 end
diff --git a/src/mainboard/starlabs/starbook/variants/tgl/devicetree.cb b/src/mainboard/starlabs/starbook/variants/tgl/devicetree.cb
index 16df1ef5c6..37dc077d2d 100644
--- a/src/mainboard/starlabs/starbook/variants/tgl/devicetree.cb
+++ b/src/mainboard/starlabs/starbook/variants/tgl/devicetree.cb
@@ -179,7 +179,7 @@ chip soc/intel/tigerlake
 		device ref uart2	on  end
 		device ref pcie_rp9	on
 			register "HybridStorageMode"			= "0"
-			register "PcieRpLtrEnable[8]"			= "1"
+			register "PcieRpLtrEnable[8]"			= "true"
 			register "PcieClkSrcUsage[3]"			= "0x08"
 			register "PcieClkSrcClkReq[3]"			= "3"
 			register "PcieRpSlotImplemented[8]"		= "true"

From 70ce81c86f625bd4b63a6991545238f74926c57a Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Sat, 30 Aug 2025 09:39:09 -0500
Subject: [PATCH 1917/3886] mb/google/dedede/var/dita: Add and use VBT

Extracted from coreboot-Google_Dita.13606.639.0.bin

TEST=build google/dita, verify image built with VBT.

Change-Id: Idbc25deeaa011581221019119dbe4923db428850
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89002
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/google/dedede/Kconfig              |   1 +
 .../google/dedede/variants/dita/data.vbt         | Bin 0 -> 7680 bytes
 2 files changed, 1 insertion(+)
 create mode 100644 src/mainboard/google/dedede/variants/dita/data.vbt

diff --git a/src/mainboard/google/dedede/Kconfig b/src/mainboard/google/dedede/Kconfig
index 2f94fa65d2..2bff7fb7c9 100644
--- a/src/mainboard/google/dedede/Kconfig
+++ b/src/mainboard/google/dedede/Kconfig
@@ -135,6 +135,7 @@ config BOARD_GOOGLE_DITA
 	select RT8168_GET_MAC_FROM_VPD
 	select RT8168_SET_LED_MODE
 	select GEO_SAR_ENABLE if CHROMEOS_WIFI_SAR
+	select INTEL_GMA_HAVE_VBT
 
 config BOARD_GOOGLE_DRAWCIA
 	select BOARD_GOOGLE_BASEBOARD_DEDEDE_CR50
diff --git a/src/mainboard/google/dedede/variants/dita/data.vbt b/src/mainboard/google/dedede/variants/dita/data.vbt
new file mode 100644
index 0000000000000000000000000000000000000000..31bf65379b1657f2a46cd89332086fcc291b1ace
GIT binary patch
literal 7680
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literal 0
HcmV?d00001


From a7b6590aca8c6f3913b47c93b3c9dd590924ed41 Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Sat, 30 Aug 2025 10:04:03 -0500
Subject: [PATCH 1918/3886]  mb/google/dedede/var/dexi: Add and use VBT

Extracted from coreboot-Google_Dexi.13606.639.0.bin

TEST=build google/dexi, verify image built with VBT.

Change-Id: I7ed620cb4b8a9b42ca97a96df4b5d30196945084
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89003
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
---
 src/mainboard/google/dedede/Kconfig              |   1 +
 .../google/dedede/variants/dexi/data.vbt         | Bin 0 -> 7680 bytes
 2 files changed, 1 insertion(+)
 create mode 100644 src/mainboard/google/dedede/variants/dexi/data.vbt

diff --git a/src/mainboard/google/dedede/Kconfig b/src/mainboard/google/dedede/Kconfig
index 2bff7fb7c9..19dd260f4b 100644
--- a/src/mainboard/google/dedede/Kconfig
+++ b/src/mainboard/google/dedede/Kconfig
@@ -121,6 +121,7 @@ config BOARD_GOOGLE_DEXI
 	select RT8168_GET_MAC_FROM_VPD
 	select RT8168_SET_LED_MODE
 	select GEO_SAR_ENABLE if CHROMEOS_WIFI_SAR
+	select INTEL_GMA_HAVE_VBT
 
 config BOARD_GOOGLE_DIBBI
 	select BOARD_GOOGLE_BASEBOARD_DEDEDE_CR50
diff --git a/src/mainboard/google/dedede/variants/dexi/data.vbt b/src/mainboard/google/dedede/variants/dexi/data.vbt
new file mode 100644
index 0000000000000000000000000000000000000000..31bf65379b1657f2a46cd89332086fcc291b1ace
GIT binary patch
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zQ?g{{Ure@5BCv+C+ALXeNdQe&1r1R)Y~C!{(*Xiw(mLq{6K$zNnYHIN@OghG37B#M
ze>YLYtjgHAi8Aw+0EXR?ZP;qick7ckli3mk5>k?c;6AK~)re`W9hr>zpvha{hA_%v
zOdHwq@2I$JqWoeZi%SBRs%VW^hOPGEQrgXIaii}I&~9tUvh%^`0&bG=R}CH@m!K`y
U;*()Mum4^L8M>IK(;9()0BrnW3IG5A

literal 0
HcmV?d00001


From ee1446a79164dae3031cf948c254f6b87b5c5b9c Mon Sep 17 00:00:00 2001
From: Benjamin Doron <benjamin.doron@9elements.com>
Date: Fri, 29 Aug 2025 11:38:42 -0400
Subject: [PATCH 1919/3886] mainboard/emulation/qemu-q35: Do not compile memmap
 into SMM

This file contains functions related to PCIe and SMM, and so it's
needed by bootblock and ramstage, and possibly romstage. It's not needed
by SMM, and in a follow-up, the SMI handler will define `smm_region`,
causing a function redefinition error.

As this file isn't needed in SMM, and the SMI handler's function
will work for this board too, as it works for all silicon (it returns
values populated during ramstage, by board/silicon implementations
of the function), drop this compilation unit from SMM.

Change-Id: I0195e7d42b0669d675879fb4d2596aa4607095b9
Signed-off-by: Benjamin Doron <benjamin.doron@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88995
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/emulation/qemu-q35/Makefile.mk | 1 -
 1 file changed, 1 deletion(-)

diff --git a/src/mainboard/emulation/qemu-q35/Makefile.mk b/src/mainboard/emulation/qemu-q35/Makefile.mk
index fc85e642b8..2ad19b92d6 100644
--- a/src/mainboard/emulation/qemu-q35/Makefile.mk
+++ b/src/mainboard/emulation/qemu-q35/Makefile.mk
@@ -21,5 +21,4 @@ all-y += ../qemu-i440fx/bootmode.c
 ramstage-$(CONFIG_CHROMEOS) += chromeos.c
 
 smm-y += ../qemu-i440fx/rom_media.c
-smm-y += memmap.c
 smm-y += smihandler.c

From 77061d8427b54da958452b1576794cc2904a5763 Mon Sep 17 00:00:00 2001
From: Derek Huang <derekhuang@google.com>
Date: Thu, 28 Aug 2025 15:05:13 +0000
Subject: [PATCH 1920/3886] mb/google/bluey: Add Quartz board (Qualcomm Hamoa)

BUG=b:441716957
TEST=build quartz board

Change-Id: I515c60c9d840084ffebae8cc2064f8f5b823c8c6
Signed-off-by: Derek Huang <derekhuang@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88983
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
---
 src/mainboard/google/bluey/Kconfig      | 13 +++++++++++++
 src/mainboard/google/bluey/Kconfig.name |  3 +++
 2 files changed, 16 insertions(+)

diff --git a/src/mainboard/google/bluey/Kconfig b/src/mainboard/google/bluey/Kconfig
index 096b3d9616..e40a253493 100644
--- a/src/mainboard/google/bluey/Kconfig
+++ b/src/mainboard/google/bluey/Kconfig
@@ -36,6 +36,15 @@ config BOARD_GOOGLE_MODEL_QUENBI
 	select MAINBOARD_HAS_GOOGLE_TPM
 	select SPI_FLASH_WINBOND
 
+config BOARD_GOOGLE_MODEL_QUARTZ
+	def_bool n
+	select BOARD_GOOGLE_BASEBOARD_BLUEY
+	select BOARD_ROMSIZE_KB_32768
+	select MAINBOARD_HAS_CHROME_EC
+	select MAINBOARD_HAS_FINGERPRINT_VIA_SPI
+	select MAINBOARD_HAS_GOOGLE_TPM
+	select SPI_FLASH_WINBOND
+
 config BOARD_GOOGLE_QUENBI
 	select BOARD_GOOGLE_MODEL_QUENBI
 	select SOC_QUALCOMM_X1P42100
@@ -44,6 +53,10 @@ config BOARD_GOOGLE_QUENBIH
 	select BOARD_GOOGLE_MODEL_QUENBI
 	select SOC_QUALCOMM_HAMOA
 
+config BOARD_GOOGLE_QUARTZ
+	select BOARD_GOOGLE_MODEL_QUARTZ
+	select SOC_QUALCOMM_HAMOA
+
 if BOARD_GOOGLE_BLUEY_COMMON
 
 config MAINBOARD_DIR
diff --git a/src/mainboard/google/bluey/Kconfig.name b/src/mainboard/google/bluey/Kconfig.name
index 3c173e0cc1..3925717a65 100644
--- a/src/mainboard/google/bluey/Kconfig.name
+++ b/src/mainboard/google/bluey/Kconfig.name
@@ -13,3 +13,6 @@ config BOARD_GOOGLE_BLUEYH
 
 config BOARD_GOOGLE_QUENBIH
 	bool "->  QuenbiH"
+
+config BOARD_GOOGLE_QUARTZ
+	bool "->  Quartz"

From e73b4579c6601527b36ab634413bcad0acc8371a Mon Sep 17 00:00:00 2001
From: Kilian Krause <kilian.krause@siemens.com>
Date: Mon, 14 Jul 2025 15:11:35 +0200
Subject: [PATCH 1921/3886] mb/siemens/mc_rpl: Disable DPTF

Disable DPTF for mc_rpl platform. In this context, the DPTF
configuration is removed as well. DPTF is deactivated to improve
realtime performance.

Change-Id: I5f9c2d1d82e9c18eafb9761df87a0709bded5964
Signed-off-by: Kilian Krause <kilian.krause@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88960
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
---
 src/mainboard/siemens/mc_rpl/devicetree.cb | 26 ++--------------------
 1 file changed, 2 insertions(+), 24 deletions(-)

diff --git a/src/mainboard/siemens/mc_rpl/devicetree.cb b/src/mainboard/siemens/mc_rpl/devicetree.cb
index 8cacb34b04..3ce7301e0b 100644
--- a/src/mainboard/siemens/mc_rpl/devicetree.cb
+++ b/src/mainboard/siemens/mc_rpl/devicetree.cb
@@ -13,34 +13,12 @@ chip soc/intel/alderlake
 	# Sagv Configuration
 	register "sagv" = "SaGv_Disabled"
 
+	register "dptf_enable" = "false"
+
 	register "s0ix_enable" = "true"
-	register "dptf_enable" = "true"
 
 	device domain 0 on
 		device ref igpu on end
-		device ref dtt on
-			chip drivers/intel/dptf
-				## Power Limits Control
-				register "controls.power_limits" = "{
-					.pl1 = {
-							.min_power = 35000,
-							.max_power = 45000,
-							.time_window_min = 28 * MSECS_PER_SEC,
-							.time_window_max = 32 * MSECS_PER_SEC,
-							.granularity = 200,
-					},
-					.pl2 = {
-							.min_power = 56000,
-							.max_power = 56000,
-							.time_window_min = 28 * MSECS_PER_SEC,
-							.time_window_max = 32 * MSECS_PER_SEC,
-							.granularity = 1000,
-					}
-				}"
-
-				device generic 0 alias dptf_policy on end
-			end
-		end
 		device ref crashlog off end
 		device ref p2sb on end
 		device ref smbus on end

From c71071397fa1a757e724a7c11274307a137ef627 Mon Sep 17 00:00:00 2001
From: Kilian Krause <kilian.krause@siemens.com>
Date: Wed, 13 Aug 2025 16:58:47 +0200
Subject: [PATCH 1922/3886] soc/intel/common/fast_spi: Add static bus scanning
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Add scan_bus operation to fast_spi device operations to enable
discovery of statically defined child devices.

This allows device drivers such as drivers/pc80/tpm that are
physically connected to the fast_spi bus to be properly
enumerated and initialized during device tree scanning.

Without this change, child devices defined in devicetree under
fast_spi would not be discovered, preventing proper driver
binding and initialization.

Example devicetree configuration:
```
                device ref fast_spi on
                        chip drivers/pc80/tpm   # SPI TPM header
                                device pnp 0c31.0 on end
                        end
                end
```

Without a .scan_bus hook in fast_spi_dev_ops, coreboot's
BS_DEV_ENUMERATE phase never creates the pnp 0c31.0 device. As a
result, in BS_DEV_RESOURCES you see, that the device PNP 0c31.0
is missing its function "read_resources":

```
(in BS_DEV_ENUMERATE)

[DEBUG]  scan_bus: bus PCI: 00:00:1f.4 finished in 11 msecs
[DEBUG]  scan_bus: bus DOMAIN: 00000000 finished in 1510 msecs
[SPEW ]  scan_static_bus for Root Device done

... (in BS_DEV_RESOURCES)

[SPEW ]  PCI: 00:00:1f.5 read_resources segment group 0 bus 0
[ERROR]  PNP: 0c31.0 missing read_resources
[SPEW ]  PCI: 00:00:1f.5 read_resources segment group 0 bus 0 done
[SPEW ]  DOMAIN: 00000000 read_resources segment group 0 bus 0 done
[SPEW ]  Root Device read_resources segment group 0 bus 0 done
[INFO ]  Done reading resources.
```

With the implementation of scan_bus, the log shows that the resources
are allocated correctly:

```
(in BS_DEV_ENUMERATE)

[DEBUG]  scan_bus: bus PCI: 00:00:1f.4 finished in 11 msecs
[DEBUG]  PCI: 00:00:1f.5 scanning...
[SPEW ]  scan_static_bus for PCI: 00:00:1f.5
[DEBUG]  PNP: 0c31.0 enabled
[SPEW ]  scan_static_bus for PCI: 00:00:1f.5 done
[DEBUG]  scan_bus: bus PCI: 00:00:1f.5 finished in 14 msecs
[DEBUG]  scan_bus: bus DOMAIN: 00000000 finished in 1536 msecs
[SPEW ]  scan_static_bus for Root Device done

... (in BS_DEV_RESOURCES)

[SPEW ]  PCI: 00:00:1f.5 read_resources segment group 0 bus 0
[SPEW ]  dev: PNP: 0c31.0, index: 0x0, base: 0xfed40000, size: 0x5000
[SPEW ]  PCI: 00:00:1f.5 read_resources segment group 0 bus 0 done
[SPEW ]  DOMAIN: 00000000 read_resources segment group 0 bus 0 done
[SPEW ]  Root Device read_resources segment group 0 bus 0 done
[INFO ]  Done reading resources.
```

TEST=Verified on Siemens mc_rpl1 mainboard. TPM device properly
enumerated with scan_bus implementation.


Change-Id: I4049d2d3cd5132362a7efd551dc9dd78cd24b9eb
Signed-off-by: Kilian Krause <kilian.krause@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88966
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
---
 src/soc/intel/common/block/fast_spi/fast_spi.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/src/soc/intel/common/block/fast_spi/fast_spi.c b/src/soc/intel/common/block/fast_spi/fast_spi.c
index f7abaa2743..627ab28e9b 100644
--- a/src/soc/intel/common/block/fast_spi/fast_spi.c
+++ b/src/soc/intel/common/block/fast_spi/fast_spi.c
@@ -558,6 +558,7 @@ static struct device_operations fast_spi_dev_ops = {
 	.acpi_fill_ssdt			= fast_spi_fill_ssdt,
 	.acpi_name			= fast_spi_acpi_name,
 	.ops_pci			= &pci_dev_ops_pci,
+	.scan_bus			= scan_static_bus,
 };
 
 static const unsigned short pci_device_ids[] = {

From e6f8900c2d2ca69595077f0b99fdbabb1a420747 Mon Sep 17 00:00:00 2001
From: Kilian Krause <kilian.krause@siemens.com>
Date: Wed, 25 Jun 2025 10:36:53 +0200
Subject: [PATCH 1923/3886] mb/siemens/mc_rpl: Disable S0ix power states

Disable S0ix power states at baseboard level.

TEST=Booted into linux and verified S0ix is disabled:
- FADT Low Power S0 Idle (V5) = 0

Change-Id: I34243137c8b06efa476dda74763d358f88bfe6a5
Signed-off-by: Kilian Krause <kilian.krause@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88956
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/siemens/mc_rpl/devicetree.cb | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/mainboard/siemens/mc_rpl/devicetree.cb b/src/mainboard/siemens/mc_rpl/devicetree.cb
index 3ce7301e0b..35a09f3a5e 100644
--- a/src/mainboard/siemens/mc_rpl/devicetree.cb
+++ b/src/mainboard/siemens/mc_rpl/devicetree.cb
@@ -15,7 +15,7 @@ chip soc/intel/alderlake
 
 	register "dptf_enable" = "false"
 
-	register "s0ix_enable" = "true"
+	register "s0ix_enable" = "false"
 
 	device domain 0 on
 		device ref igpu on end

From a1b7f5e1b8b1b5ad0f9739d8d59e118d5a773cb1 Mon Sep 17 00:00:00 2001
From: Kilian Krause <kilian.krause@siemens.com>
Date: Wed, 30 Jul 2025 13:16:18 +0200
Subject: [PATCH 1924/3886] mb/siemens/mc_rpl: Disable EIST to improve
 deterministic behavior

Disable Enhanced Intel SpeedStep Technology (EIST) to prevent
OS-controlled P-state transitions. This improves consistent CPU
frequency bevahior across all cores, which is critical for real-time
applictaions requiring deterministic performance.

The existing devicetree parameter 'eist_enable' only configures the
IA32_MISC_ENABLE register but does not affect the FSP-S parameter
'Eist'. This results in FSP re-enabling EIST during silicon
initialization, overriding the register setting.

Override the FSP-S 'Eist' parameter at mainboard level rather than
fixing it in SoC code, since devicetree parameters default to 0 when
unset and would disable EIST on boards that rely on FSP defaults.

Change-Id: Ic83246d88607a8ed0c9815e306934bcf0bf8f016
Signed-off-by: Kilian Krause <kilian.krause@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88965
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/siemens/mc_rpl/devicetree.cb | 2 ++
 src/mainboard/siemens/mc_rpl/mainboard.c   | 1 +
 2 files changed, 3 insertions(+)

diff --git a/src/mainboard/siemens/mc_rpl/devicetree.cb b/src/mainboard/siemens/mc_rpl/devicetree.cb
index 35a09f3a5e..5477b4697a 100644
--- a/src/mainboard/siemens/mc_rpl/devicetree.cb
+++ b/src/mainboard/siemens/mc_rpl/devicetree.cb
@@ -13,6 +13,8 @@ chip soc/intel/alderlake
 	# Sagv Configuration
 	register "sagv" = "SaGv_Disabled"
 
+	register "eist_enable" = "false"
+
 	register "dptf_enable" = "false"
 
 	register "s0ix_enable" = "false"
diff --git a/src/mainboard/siemens/mc_rpl/mainboard.c b/src/mainboard/siemens/mc_rpl/mainboard.c
index 28068395c0..a96ab859cd 100644
--- a/src/mainboard/siemens/mc_rpl/mainboard.c
+++ b/src/mainboard/siemens/mc_rpl/mainboard.c
@@ -93,6 +93,7 @@ enum cb_err mainboard_get_mac_address(struct device *dev, uint8_t mac[MAC_ADDR_L
 
 void mainboard_silicon_init_params(FSP_S_CONFIG *params)
 {
+	params->Eist = 0;
 	params->TurboMode = 0;
 }
 

From 53810448fc7f132def7942d40ef2c38e2ab327d2 Mon Sep 17 00:00:00 2001
From: Arthur Heymans <arthur@aheymans.xyz>
Date: Wed, 26 Apr 2023 23:41:11 +0200
Subject: [PATCH 1925/3886] cpu/x86/reset16.S: Remove handcoded reset vector

Only 3 bytes should be used for the reset vector and it looks like
modern tooling has no problem with using a regular relative jump
instruction.

TESTED: Qemu Q35 still boots fine.

Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Change-Id: Ie371000c60d66c032a8dcccb98e7627df09d3aa4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74797
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
---
 src/cpu/x86/reset16.S | 9 +--------
 1 file changed, 1 insertion(+), 8 deletions(-)

diff --git a/src/cpu/x86/reset16.S b/src/cpu/x86/reset16.S
index 38580146b4..9cc85c9746 100644
--- a/src/cpu/x86/reset16.S
+++ b/src/cpu/x86/reset16.S
@@ -4,11 +4,4 @@
 	.code16
 .globl	_start
 _start:
-	.byte  0xe9
-	.int   _start16bit - ( . + 2 )
-	/* Note: The above jump is hand coded to work around bugs in binutils.
-	 * 5 byte are used for a 3 byte instruction.  This works because x86
-	 * is little endian and allows us to use supported 32bit relocations
-	 * instead of the weird 16 bit relocations that binutils does not
-	 * handle consistently between versions because they are used so rarely.
-	 */
+	jmp   _start16bit

From 2709ae443bb9cbb6f5e14fded1b73aa692e580f6 Mon Sep 17 00:00:00 2001
From: Elyes Haouas <ehaouas@noos.fr>
Date: Mon, 1 Sep 2025 17:00:18 +0200
Subject: [PATCH 1926/3886] cpu/x86/entry16.S: Move reset vector to this file

This makes the code easier to follow.

Change-Id: I5a4b7fe99875a1addf611f569990ff9a3beda3ba
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74800
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/cpu/x86/Makefile.mk | 1 -
 src/cpu/x86/entry16.S   | 6 ++++++
 src/cpu/x86/reset16.S   | 7 -------
 3 files changed, 6 insertions(+), 8 deletions(-)
 delete mode 100644 src/cpu/x86/reset16.S

diff --git a/src/cpu/x86/Makefile.mk b/src/cpu/x86/Makefile.mk
index 26e5d9c9c2..d9fbf2fddc 100644
--- a/src/cpu/x86/Makefile.mk
+++ b/src/cpu/x86/Makefile.mk
@@ -34,7 +34,6 @@ subdirs-$(CONFIG_CPU_INTEL_COMMON_SMM) += ../intel/smm
 
 bootblock-y += entry32.S
 bootblock-y += entry16.S
-bootblock-y += reset16.S
 
 additional-dirs += $(obj)/cpu/x86
 
diff --git a/src/cpu/x86/entry16.S b/src/cpu/x86/entry16.S
index b19ffa5d6a..ca2eb6067b 100644
--- a/src/cpu/x86/entry16.S
+++ b/src/cpu/x86/entry16.S
@@ -151,3 +151,9 @@ nullidt:
 	.word	0	/* limit */
 	.long	0
 	.word	0
+
+  /* This is the first instruction the CPU runs when coming out of reset. */
+.section ".reset", "ax", %progbits
+.globl _start
+_start:
+	jmp		_start16bit
diff --git a/src/cpu/x86/reset16.S b/src/cpu/x86/reset16.S
deleted file mode 100644
index 9cc85c9746..0000000000
--- a/src/cpu/x86/reset16.S
+++ /dev/null
@@ -1,7 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-	.section ".reset", "ax", %progbits
-	.code16
-.globl	_start
-_start:
-	jmp   _start16bit

From 283c25beec0b618909227ea86fc4d3f243da664d Mon Sep 17 00:00:00 2001
From: Eren Peng <peng.eren@inventec.corp-partner.google.com>
Date: Mon, 1 Sep 2025 14:59:16 +0800
Subject: [PATCH 1927/3886] mb/google/trulo/var/kaladin: Select Strauss
 keyboard to show G icon

Because the machine shows circle icon instead of G icon in 'Setting'
->'Device'->'View keyboard shortcuts'.
So add MAINBOARD_HAS_GOOGLE_STRAUSS_KEYBOARD to enable G icon.

BUG=b:442310345
BRANCH=none
TEST= Build and boot to OS and enter 'Setting'->'Device'
->'View keyboard shortcuts' to see G icon.

Change-Id: I77e2ce1556ded97c4d146b3e12f751958f31db80
Signed-off-by: Eren Peng <peng.eren@inventec.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89008
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
---
 src/mainboard/google/brya/Kconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/src/mainboard/google/brya/Kconfig b/src/mainboard/google/brya/Kconfig
index 9d2d40c397..a581bd36db 100644
--- a/src/mainboard/google/brya/Kconfig
+++ b/src/mainboard/google/brya/Kconfig
@@ -325,6 +325,7 @@ config BOARD_GOOGLE_KALADIN
 	select BOARD_GOOGLE_BASEBOARD_TRULO
 	select CHROMEOS_WIFI_SAR if CHROMEOS
 	select DRIVERS_GENERIC_GPIO_KEYS
+	select MAINBOARD_HAS_GOOGLE_STRAUSS_KEYBOARD
 	select SOC_INTEL_COMMON_BLOCK_HDA_VERB
 	select SOC_INTEL_TCSS_USE_PDC_PMC_USBC_MUX_CONFIGURATION
 	select SOC_INTEL_TWINLAKE

From 16318a32cec7ba8eac6f96d0a73ad37e050454e3 Mon Sep 17 00:00:00 2001
From: Shon Wang <shon.wang@quanta.corp-partner.google.com>
Date: Mon, 25 Aug 2025 10:24:43 +0800
Subject: [PATCH 1928/3886] spd/lp5x: Generate initial SPD for
 MT62F512M32D1DS-023 WT:E

Generate initial SPD for MT62F512M32D1DS-023 WT:E

BUG=b:438402880
BRANCH=firmware-nissa-15217.B
TEST=util/spd_tools/bin/spd_gen spd/lp5/memory_parts.json lp5

Change-Id: I9c67dadf75b15fc1e0392566be60a776e1ee8a35
Signed-off-by: Shon Wang <shon.wang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88924
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
---
 spd/lp5/memory_parts.json                      | 11 +++++++++++
 spd/lp5/set-0/parts_spd_manifest.generated.txt |  1 +
 spd/lp5/set-1/parts_spd_manifest.generated.txt |  1 +
 3 files changed, 13 insertions(+)

diff --git a/spd/lp5/memory_parts.json b/spd/lp5/memory_parts.json
index 9f11ee5e61..946e03345a 100644
--- a/spd/lp5/memory_parts.json
+++ b/spd/lp5/memory_parts.json
@@ -328,6 +328,17 @@
                 "speedMbps": 8533,
                 "lp5x": true
             }
+        },
+        {
+            "name": "MT62F512M32D1DS-023 WT:E",
+            "attribs": {
+                "densityPerDieGb": 16,
+                "diesPerPackage": 2,
+                "bitWidthPerChannel": 16,
+                "ranksPerChannel": 1,
+                "speedMbps": 8533,
+                "lp5x": true
+            }
         }
     ]
 }
diff --git a/spd/lp5/set-0/parts_spd_manifest.generated.txt b/spd/lp5/set-0/parts_spd_manifest.generated.txt
index f2f396099a..68eec96b47 100644
--- a/spd/lp5/set-0/parts_spd_manifest.generated.txt
+++ b/spd/lp5/set-0/parts_spd_manifest.generated.txt
@@ -32,3 +32,4 @@ K3KL8L80EM-MGCU,spd-11.hex
 K3KL9L90EM-MGCU,spd-10.hex
 H58G66CK8BX147,spd-10.hex
 MT62F2G32D4DS-023 WT:C,spd-10.hex
+MT62F512M32D1DS-023 WT:E,spd-11.hex
diff --git a/spd/lp5/set-1/parts_spd_manifest.generated.txt b/spd/lp5/set-1/parts_spd_manifest.generated.txt
index f2f396099a..68eec96b47 100644
--- a/spd/lp5/set-1/parts_spd_manifest.generated.txt
+++ b/spd/lp5/set-1/parts_spd_manifest.generated.txt
@@ -32,3 +32,4 @@ K3KL8L80EM-MGCU,spd-11.hex
 K3KL9L90EM-MGCU,spd-10.hex
 H58G66CK8BX147,spd-10.hex
 MT62F2G32D4DS-023 WT:C,spd-10.hex
+MT62F512M32D1DS-023 WT:E,spd-11.hex

From 9ecf04c2bc99e98161ae7b93ca214fe5fb480f1f Mon Sep 17 00:00:00 2001
From: Shon Wang <shon.wang@quanta.corp-partner.google.com>
Date: Mon, 25 Aug 2025 10:30:43 +0800
Subject: [PATCH 1929/3886] mb/google/nissa/var/quandiso: Generate RAM ID for
 MT62F512M32D1DS-023 WT:E

Generate RAM ID for MT62F512M32D1DS-023 WT:E

DRAM Part Name                 ID to assign
MT62F512M32D1DS-023 WT:E       7 (0111)

BUG=b:438402880
BRANCH=firmware-nissa-15217.B
TEST=emerge-nissa coreboot

Change-Id: I6786bff4a03179e3f682ade57d795a449df14bbc
Signed-off-by: Shon Wang <shon.wang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88925
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/google/brya/variants/quandiso/memory/Makefile.mk  | 2 +-
 .../google/brya/variants/quandiso/memory/dram_id.generated.txt  | 1 +
 .../google/brya/variants/quandiso/memory/mem_parts_used.txt     | 1 +
 3 files changed, 3 insertions(+), 1 deletion(-)

diff --git a/src/mainboard/google/brya/variants/quandiso/memory/Makefile.mk b/src/mainboard/google/brya/variants/quandiso/memory/Makefile.mk
index 7dbd0d33f3..166769396f 100644
--- a/src/mainboard/google/brya/variants/quandiso/memory/Makefile.mk
+++ b/src/mainboard/google/brya/variants/quandiso/memory/Makefile.mk
@@ -11,4 +11,4 @@ SPD_SOURCES += spd/lp5/set-0/spd-7.hex      # ID = 3(0b0011)  Parts = H58G56BK7B
 SPD_SOURCES += spd/lp5/set-0/spd-8.hex      # ID = 4(0b0100)  Parts = H58G66BK7BX067, MT62F2G32D4DS-026 WT:B, K3KL9L90CM-MGCT
 SPD_SOURCES += spd/lp5/set-0/spd-6.hex      # ID = 5(0b0101)  Parts = H58G66AK6BX070
 SPD_SOURCES += spd/lp5/set-0/spd-9.hex      # ID = 6(0b0110)  Parts = K3KL6L60GM-MGCT
-SPD_SOURCES += spd/lp5/set-0/spd-11.hex      # ID = 7(0b0111)  Parts = MT62F1G32D2DS-023 WT:C, H58G56CK8BX146, K3KL8L80EM-MGCU
+SPD_SOURCES += spd/lp5/set-0/spd-11.hex      # ID = 7(0b0111)  Parts = MT62F1G32D2DS-023 WT:C, H58G56CK8BX146, K3KL8L80EM-MGCU, MT62F512M32D1DS-023 WT:E
diff --git a/src/mainboard/google/brya/variants/quandiso/memory/dram_id.generated.txt b/src/mainboard/google/brya/variants/quandiso/memory/dram_id.generated.txt
index aebf863aac..362ef9ea21 100644
--- a/src/mainboard/google/brya/variants/quandiso/memory/dram_id.generated.txt
+++ b/src/mainboard/google/brya/variants/quandiso/memory/dram_id.generated.txt
@@ -20,3 +20,4 @@ K3KL6L60GM-MGCT                6 (0110)
 MT62F1G32D2DS-023 WT:C         7 (0111)
 H58G56CK8BX146                 7 (0111)
 K3KL8L80EM-MGCU                7 (0111)
+MT62F512M32D1DS-023 WT:E       7 (0111)
diff --git a/src/mainboard/google/brya/variants/quandiso/memory/mem_parts_used.txt b/src/mainboard/google/brya/variants/quandiso/memory/mem_parts_used.txt
index 79ac769995..76c6d3f316 100644
--- a/src/mainboard/google/brya/variants/quandiso/memory/mem_parts_used.txt
+++ b/src/mainboard/google/brya/variants/quandiso/memory/mem_parts_used.txt
@@ -25,3 +25,4 @@ K3KL6L60GM-MGCT
 MT62F1G32D2DS-023 WT:C
 H58G56CK8BX146
 K3KL8L80EM-MGCU
+MT62F512M32D1DS-023 WT:E

From b0a63052b726c893d49a3341828f501b16ae448b Mon Sep 17 00:00:00 2001
From: Patrick Rudolph <patrick.rudolph@9elements.com>
Date: Thu, 14 Aug 2025 15:14:48 +0200
Subject: [PATCH 1930/3886] sb/intel/bd82x6x: Fix CPU replaced check

Check if CPU has been replaced before doing ram init. When it
has been replaced disable MRC cache and do a full memory training.

Also use get_us_since_boot() to skip waiting additional 50msec
when not necessary. Setting up NEM in bootblock is so slow that
50msec might already have passed.

Before:
 940:waiting for ME acknowledgment of raminit          116,514 (62,804)
After:
 940:waiting for ME acknowledgment of raminit          68,708 (7,211)

Boots 48msec faster than before.

Change-Id: I2d9729792c3546dc9bf23192c42619cd7d639d1c
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88794
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
---
 src/northbridge/intel/sandybridge/raminit.c |  3 +
 src/southbridge/intel/bd82x6x/early_me.c    | 72 ++++++++++++++-------
 src/southbridge/intel/bd82x6x/me.h          |  2 +-
 3 files changed, 54 insertions(+), 23 deletions(-)

diff --git a/src/northbridge/intel/sandybridge/raminit.c b/src/northbridge/intel/sandybridge/raminit.c
index cd6d173046..dd6b36b25b 100644
--- a/src/northbridge/intel/sandybridge/raminit.c
+++ b/src/northbridge/intel/sandybridge/raminit.c
@@ -411,6 +411,9 @@ static void init_dram_ddr3(int s3resume, const u32 cpuid)
 		fast_boot = s3resume;
 	}
 
+	if (fast_boot && intel_early_me_cpu_replaced())
+		fast_boot = false;
+
 	if (fast_boot) {
 		printk(BIOS_DEBUG, "Trying stored timings.\n");
 		memcpy(&ctrl, ctrl_cached, sizeof(ctrl));
diff --git a/src/southbridge/intel/bd82x6x/early_me.c b/src/southbridge/intel/bd82x6x/early_me.c
index 866996f913..206e032476 100644
--- a/src/southbridge/intel/bd82x6x/early_me.c
+++ b/src/southbridge/intel/bd82x6x/early_me.c
@@ -85,6 +85,56 @@ int intel_early_me_uma_size(void)
 	return 0;
 }
 
+/**
+ * Check if ME reports that CPU has been replaced.
+ *
+ * @return TRUE when CPU was replaced and full
+ *         memory training is required.
+ */
+bool intel_early_me_cpu_replaced(void)
+{
+	u32 millisec;
+	union me_gmes gmes;
+
+	gmes.raw = pci_read_config32(PCH_ME_DEV, PCI_ME_GMES);
+
+	/*
+	 * Poll CPU replaced status until 50 ms have elapsed since boot.
+	 * The ME FW should've had enough time to wake up at this point.
+	 */
+	millisec = get_us_since_boot() / 1000;
+	while (!gmes.cpu_replaced_valid && millisec < 50) {
+		udelay(1000);
+		gmes.raw = pci_read_config32(PCH_ME_DEV, PCI_ME_GMES);
+		millisec++;
+	}
+
+	if (gmes.cpu_replaced_valid) {
+		if (gmes.warm_rst_req_for_df) {
+			/*
+			 * DF (Dynamic Fusing) is when the ME updates the CAPID0
+			 * register in the host bridge depending on the PCH SKU.
+			 */
+			printk(BIOS_NOTICE, "CPU was replaced & warm reset required...\n");
+
+			/* Indicate DRAM init not done for MRC */
+			pci_and_config8(PCH_LPC_DEV, GEN_PMCON_2, 0x7f);
+			set_global_reset(0);
+			system_reset();
+			return true;
+		}
+
+		if (gmes.cpu_replaced_sts) {
+			printk(BIOS_NOTICE, "Full memory training required\n");
+			return true;
+		}
+	} else {
+		/* CPU replaced is still not valid (bad ME FW?) */
+		printk(BIOS_NOTICE, "CPU replaced is not valid, assuming CPU was not replaced...\n");
+	}
+	return false;
+}
+
 int intel_early_me_init_done(u8 status)
 {
 	u8 reset, errorcode, opmode;
@@ -128,28 +178,6 @@ int intel_early_me_init_done(u8 status)
 	printk(BIOS_NOTICE, "ME:  Current PM event: 0x%x\n", (me_fws2 & 0xf000000) >> 24);
 	printk(BIOS_NOTICE, "ME:  Progress code   : 0x%x\n", (me_fws2 & 0xf0000000) >> 28);
 
-	/* Poll CPU replaced for 50ms */
-	millisec = 0;
-	while ((((me_fws2 & 0x100) >> 8) == 0) && millisec < 50) {
-		udelay(1000);
-		me_fws2 = pci_read_config32(PCH_ME_DEV, PCI_ME_GMES);
-		millisec++;
-	}
-	if (millisec >= 50 || ((me_fws2 & 0x100) >> 8) == 0x0) {
-		printk(BIOS_NOTICE, "Waited long enough, or CPU was not replaced, continue...\n");
-	} else if ((me_fws2 & 0x100) == 0x100) {
-		if ((me_fws2 & 0x80) == 0x80) {
-			printk(BIOS_NOTICE, "CPU was replaced & warm reset required...\n");
-			pci_and_config16(PCH_LPC_DEV, GEN_PMCON_2, ~0x80);
-			set_global_reset(0);
-			system_reset();
-		}
-
-		if (((me_fws2 & 0x10) == 0x10) && (me_fws2 & 0x80) == 0x00) {
-			printk(BIOS_NOTICE, "Full training required\n");
-		}
-	}
-
 	printk(BIOS_NOTICE, "PASSED! Tell ME that DRAM is ready\n");
 
 	/* MEBASE from MESEG_BASE[35:20] */
diff --git a/src/southbridge/intel/bd82x6x/me.h b/src/southbridge/intel/bd82x6x/me.h
index 4edaad9739..85ecd96c17 100644
--- a/src/southbridge/intel/bd82x6x/me.h
+++ b/src/southbridge/intel/bd82x6x/me.h
@@ -293,7 +293,7 @@ void intel_early_me_status(void);
 int intel_early_me_init(void);
 int intel_early_me_uma_size(void);
 int intel_early_me_init_done(u8 status);
-
+bool intel_early_me_cpu_replaced(void);
 void intel_me_finalize_smm(void);
 
 typedef struct {

From 3b2962929b9402ecaaea1b9e2fa72d6ca47cc29e Mon Sep 17 00:00:00 2001
From: Patrick Rudolph <patrick.rudolph@9elements.com>
Date: Sat, 16 Aug 2025 15:15:43 +0200
Subject: [PATCH 1931/3886] lib/timestamp: Init TSC frequency early on x86
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

When get_us_since_boot() is called in pre-ram stages on x86 init
the TSC frequency. The TSC frequency is necessary to calculate
the time spent since boot.

When get_us_since_boot() is not used in pre-ram stages the function
timestamp_tick_freq_mhz() will also be dropped by the linker, thus
there's no code size increase for common code.

Will be used in the following commit in pre-ram stages.

Change-Id: I7fd9eeadf3063a629dd589498fcb957b9bd66536
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88793
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
---
 src/lib/timestamp.c | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/src/lib/timestamp.c b/src/lib/timestamp.c
index c7e1c0cf4c..e25aaec412 100644
--- a/src/lib/timestamp.c
+++ b/src/lib/timestamp.c
@@ -274,6 +274,16 @@ uint32_t get_us_since_boot(void)
 {
 	struct timestamp_table *ts = timestamp_table_get();
 
+	/*
+	 * Bootbock size is limited on some platforms, thus only
+	 * enable get_us_since_boot() in PRERAM stages on x86 platforms
+	 * for now. When get_us_since_boot() isn't used in preram the linker
+	 * will drop timestamp_tick_freq_mhz().
+	 */
+	if (CONFIG(ARCH_X86) && ENV_ROMSTAGE_OR_BEFORE &&
+	    ts && ts->tick_freq_mhz == 0)
+		ts->tick_freq_mhz = timestamp_tick_freq_mhz();
+
 	if (ts == NULL || ts->tick_freq_mhz == 0)
 		return 0;
 	return (timestamp_get() - ts->base_time) / ts->tick_freq_mhz;

From d5a92542aaf56c3262ed4a05c6646cf0ea60e55e Mon Sep 17 00:00:00 2001
From: Zhixing Ma <zhixing.ma@intel.com>
Date: Thu, 28 Aug 2025 14:38:41 -0700
Subject: [PATCH 1932/3886] mb/google/fatcat/var/fatcat: Disable ALC721 &
 ALC722 clock stop support

There is an issue with headset detection on Soundwire audio codec.
Specifically, if the audio is not active (playback/capture is not
ongoing), then 3.5 mm headset detection fails. There is a fix for
Francka (PTL design). Similar implementation is needed for Fatcat.

Port commit a23be7a6fe12 (mb/google/fatcat/var/francka: Disable ALC721 &
ALC722 clock stop support to francka. This allows the flag to be
overridden via devicetree, instead of relying on the default value in
alc711_slave. It helps fix the missing event issue when plugging or
unplugging the 3.5mm headphone jack.)

BUG=NONE
TEST=After boot to OS, verified headphone detection working using
"getevent" command. Seeing headset jack detected in output:

add device 3: /dev/input/event7
  name:     "sof-soundwire Headset Jack"

Change-Id: I717f31f8d492bd0b2523c77b7492e46f50de991e
Signed-off-by: Zhixing Ma <zhixing.ma@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88986
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
---
 src/mainboard/google/fatcat/variants/fatcat/overridetree.cb | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/src/mainboard/google/fatcat/variants/fatcat/overridetree.cb b/src/mainboard/google/fatcat/variants/fatcat/overridetree.cb
index 12c293b4a4..a3e94ca659 100644
--- a/src/mainboard/google/fatcat/variants/fatcat/overridetree.cb
+++ b/src/mainboard/google/fatcat/variants/fatcat/overridetree.cb
@@ -936,6 +936,7 @@ chip soc/intel/pantherlake
 						register "alc711_address.version" = "SOUNDWIRE_VERSION_1_2"
 						register "alc711_address.class" = "MIPI_CLASS_SDCA"
 						register "alc711_address.part_id" = "MIPI_DEV_ID_REALTEK_ALC722"
+						register "disable_clkstop_sm_support" = "true"
 						# SoundWire Link 1 ID 1
 						device generic 1.1 on
 							probe AUDIO AUDIO_ALC722_SNDW
@@ -946,6 +947,7 @@ chip soc/intel/pantherlake
 						register "alc711_address.version" = "SOUNDWIRE_VERSION_1_2"
 						register "alc711_address.class" = "MIPI_CLASS_SDCA"
 						register "alc711_address.part_id" = "MIPI_DEV_ID_REALTEK_ALC721"
+						register "disable_clkstop_sm_support" = "true"
 						# SoundWire Link 3 ID 1
 						device generic 3.1 on
 							probe AUDIO AUDIO_ALC721_SNDW

From d8de1c4974311b5c259036a63d2f5e99b8db06ca Mon Sep 17 00:00:00 2001
From: Patrick Rudolph <patrick.rudolph@9elements.com>
Date: Fri, 29 Aug 2025 18:57:47 +0200
Subject: [PATCH 1933/3886] ec/lenovo/h8: Disable POST codes
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

The EC doesn't care about POST codes send to port 80h and there's
no POST code display on the laptops, thus disable POST codes at all.

TEST=Lenovo X220 still boots.

Change-Id: Idf666796d3cbb504c6e68d84521359d7e2fe98d0
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88999
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
---
 src/ec/lenovo/h8/Kconfig | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/src/ec/lenovo/h8/Kconfig b/src/ec/lenovo/h8/Kconfig
index c8626cc75b..439ede5a20 100644
--- a/src/ec/lenovo/h8/Kconfig
+++ b/src/ec/lenovo/h8/Kconfig
@@ -6,6 +6,9 @@ config EC_LENOVO_H8
 
 if EC_LENOVO_H8
 
+config NO_POST
+	default y
+
 config SEABIOS_PS2_TIMEOUT
 	int
 	depends on PAYLOAD_SEABIOS

From f2d30516315903ab23b19ccd7a3073fe21e5c164 Mon Sep 17 00:00:00 2001
From: Patrick Rudolph <patrick.rudolph@9elements.com>
Date: Fri, 29 Aug 2025 17:56:45 +0200
Subject: [PATCH 1934/3886] ec/lenovo/h8: Turn on PWR LED

On warm reboot the PWR LED isn't automatically turned on by the EC.
Turn it on in the ramstage code, which allows to see when the reboot
has happened.

TEST=PWR LED is on after warm reboot on Lenovo X220.

Change-Id: Ia5fe3a52a6be622785c9588a94242ac0de0e19fa
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88998
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
---
 src/ec/lenovo/h8/h8.c | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/src/ec/lenovo/h8/h8.c b/src/ec/lenovo/h8/h8.c
index 155a013bac..acf5ce5408 100644
--- a/src/ec/lenovo/h8/h8.c
+++ b/src/ec/lenovo/h8/h8.c
@@ -248,6 +248,12 @@ static void h8_enable(struct device *dev)
 	ec_write(H8_CONFIG2, conf->config2);
 	ec_write(H8_CONFIG3, conf->config3);
 
+	/*
+	 * Reset LEDs to power on state.
+	 * (Without this warm reboot leaves LEDs off)
+	 */
+	ec_write(H8_LED_CONTROL, H8_LED_CONTROL_ON | H8_LED_CONTROL_POWER_LED);
+
 	beepmask0 = conf->beepmask0;
 	beepmask1 = conf->beepmask1;
 

From ac5bb861d80ddab29edd846e27014c2f25dc4c0f Mon Sep 17 00:00:00 2001
From: John Su <john_su@compal.corp-partner.google.com>
Date: Tue, 26 Aug 2025 15:05:32 +0800
Subject: [PATCH 1935/3886] mb/google/brya/var/uldrenite: Update HDA verb table

Update HDA verb table (ALC3204_RTK20250805) from Realtek.
1. Modify Pin widget 0x12 - DMIC1-2
2. Modify ALC3204 Speaker output power
3. Remove H/W AGC setting
4. Remove EQ setting

BUG=b:374203133
TEST= Chromebook approved Vendor List (AVL) qualification pass
(including output voltage, frequency, magnitude response, and
noise level during system activity)

Change-Id: Id8eab4a763bcb07b747eb50cd464c8e2b2de0b57
Signed-off-by: John Su <john_su@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88947
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
---
 .../google/brya/variants/uldrenite/hda_verb.c | 48 ++-----------------
 1 file changed, 4 insertions(+), 44 deletions(-)

diff --git a/src/mainboard/google/brya/variants/uldrenite/hda_verb.c b/src/mainboard/google/brya/variants/uldrenite/hda_verb.c
index 3fb63d6ee7..a571d549b6 100644
--- a/src/mainboard/google/brya/variants/uldrenite/hda_verb.c
+++ b/src/mainboard/google/brya/variants/uldrenite/hda_verb.c
@@ -6,7 +6,7 @@ const u32 cim_verb_data[] = {
 	/* coreboot specific header */
 	0x10ec0236,	// Codec Vendor ID: Realtek ALC3204
 	0x10280D76,	// Subsystem ID
-	0x00000021,	// Number of jacks (NID entries)
+	0x00000019,	// Number of jacks (NID entries)
 
 	AZALIA_RESET(0x1),
 	/* NID 0x01, HDA Codec Subsystem ID Verb table */
@@ -20,7 +20,7 @@ const u32 cim_verb_data[] = {
 	 * AZALIA_PIN_CFG(0, 0x12, 0x90A60130),
 	 * AZALIA_PIN_CFG(0, 0x13, 0x40000000),
 	 */
-	AZALIA_PIN_CFG(0, 0x12, 0x90a60140),
+	AZALIA_PIN_CFG(0, 0x12, 0x411111f0),
 	AZALIA_PIN_CFG(0, 0x13, 0x40000000),
 	AZALIA_PIN_CFG(0, 0x14, 0x90170110),
 	AZALIA_PIN_CFG(0, 0x18, 0x411111f0),
@@ -52,22 +52,12 @@ const u32 cim_verb_data[] = {
 	0x02050034,
 	0x0204023C,
 	/* ALC3204 Speaker output power - 4 ohm
-	 * 2W (+12dB gain) + Combo Jack TRS setting
+	 * 2W + Combo Jack default setting
 	 */
 	0x02050038,
-	0x02043901,
+	0x02047901,
 	0x02050045,
 	0x02045089,
-	/* H/W AGC setting-1 */
-	0x02050016,
-	0x02040C50,
-	0x02050012,
-	0x0204EBC2,
-	/* H/W AGC setting-2 */
-	0x02050013,
-	0x0204401D,
-	0x02050016,
-	0x02044E50,
 	/* Zero data  + EAPD to verb-control */
 	0x02050037,
 	0x0204FE15,
@@ -108,36 +98,6 @@ const u32 cim_verb_data[] = {
 	0x020401EF,
 	0x0205000C,
 	0x020401EF,
-	/* EQ Bypass + EQ HPF cutoff 250Hz */
-	0x05350000,
-	0x0534201A,
-	0x0535001d,
-	0x05340800,
-	/* EQ-2 */
-	0x0535001e,
-	0x05340800,
-	0x05350003,
-	0x05341EF8,
-	/* EQ-3 */
-	0x05350004,
-	0x05340000,
-	0x05450000,
-	0x05442000,
-	/* EQ-4 */
-	0x0545001d,
-	0x05440800,
-	0x0545001e,
-	0x05440800,
-	/* EQ-5 */
-	0x05450003,
-	0x05441EF8,
-	0x05450004,
-	0x05440000,
-	/* EQ Update */
-	0x05350000,
-	0x0534E01A,
-	0x05350000,
-	0x0534E01A,
 };
 
 const u32 pc_beep_verbs[] = {

From 9fb306f53ce3497b66549cd587bc531b6c417529 Mon Sep 17 00:00:00 2001
From: Subrata Banik <subratabanik@google.com>
Date: Wed, 3 Sep 2025 11:03:55 +0530
Subject: [PATCH 1936/3886] soc/qualcomm/x1p42100: Add SPMI driver to ramstage

The SPMI (System Power Management Interface) driver is necessary
for power management functionalities on the Qualcomm x1p42100 SoC.
This commit adds spmi.c to the ramstage-y list in the Makefile.mk,
ensuring that the SPMI driver is compiled and available during the
ramstage of the coreboot execution.

TEST=Able to build and boot google/quenbi.

Change-Id: Iba0a423e4a25d7ec9c55e24a1463a4fd4c53cc4f
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89020
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
---
 src/soc/qualcomm/x1p42100/Makefile.mk | 1 +
 1 file changed, 1 insertion(+)

diff --git a/src/soc/qualcomm/x1p42100/Makefile.mk b/src/soc/qualcomm/x1p42100/Makefile.mk
index 86aeb36fa4..fb82673a15 100644
--- a/src/soc/qualcomm/x1p42100/Makefile.mk
+++ b/src/soc/qualcomm/x1p42100/Makefile.mk
@@ -44,6 +44,7 @@ ramstage-y += cbmem.c
 ramstage-y += ../common/mmu.c
 ramstage-$(CONFIG_DRIVERS_UART) += ../common/qupv3_uart.c
 ramstage-$(CONFIG_PCI) += ../common/pcie_common.c
+ramstage-y += ../common/spmi.c
 ramstage-$(CONFIG_PCI) += pcie.c
 ramstage-y += cpucp_load_reset.c
 

From 45d1f9cce46144bd1b8b1be2b9dc9e9d05f13208 Mon Sep 17 00:00:00 2001
From: Subrata Banik <subratabanik@google.com>
Date: Wed, 3 Sep 2025 10:40:35 +0530
Subject: [PATCH 1937/3886] mb/google/bluey: Move charging functions to
 dedicated file

This patch isolates all charging-related functionality, including
enabling and disabling charging and reading SPMI registers, into a new
dedicated file, charging.c. This improves code organization and
readability by separating concerns, making the codebase easier to
maintain.

Additionally, `enable_battery_charging` is renamed to
`enable_slow_battery_charging` to explicitly state the maximum current
is 1A. The charging enablement logic is also moved to occur before
the AOP firmware is loaded.

TEST=Able to build and boot google/quenbi.

Change-Id: Ieb374cb34814e8eab8dc2ad6f5fb435190167bc7
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89021
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/google/bluey/Makefile.mk |  2 ++
 src/mainboard/google/bluey/board.h     |  1 +
 src/mainboard/google/bluey/charging.c  | 29 ++++++++++++++++++++++++++
 src/mainboard/google/bluey/romstage.c  | 27 ++----------------------
 4 files changed, 34 insertions(+), 25 deletions(-)
 create mode 100644 src/mainboard/google/bluey/charging.c

diff --git a/src/mainboard/google/bluey/Makefile.mk b/src/mainboard/google/bluey/Makefile.mk
index 6018c9152a..556509b3cb 100644
--- a/src/mainboard/google/bluey/Makefile.mk
+++ b/src/mainboard/google/bluey/Makefile.mk
@@ -10,4 +10,6 @@ bootblock-y += bootblock.c
 
 romstage-y += romstage.c
 
+romstage-y += charging.c
+
 ramstage-y += mainboard.c
diff --git a/src/mainboard/google/bluey/board.h b/src/mainboard/google/bluey/board.h
index b5b719d7bc..2a7120a719 100644
--- a/src/mainboard/google/bluey/board.h
+++ b/src/mainboard/google/bluey/board.h
@@ -38,5 +38,6 @@
 #endif
 
 void setup_chromeos_gpios(void);
+void enable_slow_battery_charging(void);
 
 #endif /* MAINBOARD_GOOGLE_BLUEY_BOARD_H */
diff --git a/src/mainboard/google/bluey/charging.c b/src/mainboard/google/bluey/charging.c
new file mode 100644
index 0000000000..3b9e4492b9
--- /dev/null
+++ b/src/mainboard/google/bluey/charging.c
@@ -0,0 +1,29 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include "board.h"
+#include <soc/qcom_spmi.h>
+
+#define SMB1_SLAVE_ID 0x07
+#define SMB2_SLAVE_ID 0x0A
+#define SCHG_CHGR_MAX_FAST_CHARGE_CURRENT_CFG 0x2666
+#define SMB1_CHGR_MAX_FCC_CFG ((SMB1_SLAVE_ID << 16) | SCHG_CHGR_MAX_FAST_CHARGE_CURRENT_CFG)
+#define SMB2_CHGR_MAX_FCC_CFG ((SMB2_SLAVE_ID << 16) | SCHG_CHGR_MAX_FAST_CHARGE_CURRENT_CFG)
+#define SCHG_CHGR_CHARGING_ENABLE_CMD 0x2642
+#define SMB1_CHGR_CHRG_EN_CMD ((SMB1_SLAVE_ID << 16) | SCHG_CHGR_CHARGING_ENABLE_CMD)
+#define SMB2_CHGR_CHRG_EN_CMD ((SMB2_SLAVE_ID << 16) | SCHG_CHGR_CHARGING_ENABLE_CMD)
+
+#define FCC_1A_STEP_50MA 0x14
+#define CHRG_ENABLE 0x01
+
+/*
+ * Enable charging w/ 1A Icurrent supply at max.
+ */
+void enable_slow_battery_charging(void)
+{
+	/* Configure FCC and enable charging */
+	printk(BIOS_INFO, "Use slow charging without fast charge support\n");
+	spmi_write8(SMB1_CHGR_MAX_FCC_CFG, FCC_1A_STEP_50MA);
+	spmi_write8(SMB2_CHGR_MAX_FCC_CFG, FCC_1A_STEP_50MA);
+	spmi_write8(SMB1_CHGR_CHRG_EN_CMD, CHRG_ENABLE);
+	spmi_write8(SMB2_CHGR_CHRG_EN_CMD, CHRG_ENABLE);
+}
diff --git a/src/mainboard/google/bluey/romstage.c b/src/mainboard/google/bluey/romstage.c
index 67d19aa1e6..da87261fef 100644
--- a/src/mainboard/google/bluey/romstage.c
+++ b/src/mainboard/google/bluey/romstage.c
@@ -5,32 +5,9 @@
 #include <gpio.h>
 #include <soc/aop_common.h>
 #include <soc/qclib_common.h>
-#include <soc/qcom_spmi.h>
 #include <soc/shrm.h>
 #include <soc/watchdog.h>
 
-#define SMB1_SLAVE_ID 0x07
-#define SMB2_SLAVE_ID 0x0A
-#define SCHG_CHGR_MAX_FAST_CHARGE_CURRENT_CFG 0x2666
-#define SMB1_CHGR_MAX_FCC_CFG ((SMB1_SLAVE_ID << 16) | SCHG_CHGR_MAX_FAST_CHARGE_CURRENT_CFG)
-#define SMB2_CHGR_MAX_FCC_CFG ((SMB2_SLAVE_ID << 16) | SCHG_CHGR_MAX_FAST_CHARGE_CURRENT_CFG)
-#define SCHG_CHGR_CHARGING_ENABLE_CMD 0x2642
-#define SMB1_CHGR_CHRG_EN_CMD ((SMB1_SLAVE_ID << 16) | SCHG_CHGR_CHARGING_ENABLE_CMD)
-#define SMB2_CHGR_CHRG_EN_CMD ((SMB2_SLAVE_ID << 16) | SCHG_CHGR_CHARGING_ENABLE_CMD)
-
-#define FCC_1A_STEP_50MA 0x14
-#define CHRG_ENABLE 0x01
-
-static void enable_battery_charging(void)
-{
-	/* Configure FCC and enable charging */
-	printk(BIOS_INFO, "Use slow charging without fast charge support\n");
-	spmi_write8(SMB1_CHGR_MAX_FCC_CFG, FCC_1A_STEP_50MA);
-	spmi_write8(SMB2_CHGR_MAX_FCC_CFG, FCC_1A_STEP_50MA);
-	spmi_write8(SMB1_CHGR_CHRG_EN_CMD, CHRG_ENABLE);
-	spmi_write8(SMB2_CHGR_CHRG_EN_CMD, CHRG_ENABLE);
-}
-
 void platform_romstage_main(void)
 {
 	/* Watchdog must be checked first to avoid erasing watchdog info later. */
@@ -41,12 +18,12 @@ void platform_romstage_main(void)
 	/* QCLib: DDR init & train */
 	qclib_load_and_run();
 
+	enable_slow_battery_charging();
+
 	aop_fw_load_reset();
 
 	qclib_rerun();
 
-	enable_battery_charging();
-
 	/*
 	 * Enable this power rail now for FPMCU stability prior to
 	 * its reset being deasserted in ramstage. This applies

From 6e61ea65a8933048f288593f50786ddabb76d57a Mon Sep 17 00:00:00 2001
From: Subrata Banik <subratabanik@google.com>
Date: Wed, 3 Sep 2025 11:06:38 +0530
Subject: [PATCH 1938/3886] mb/google/bluey: Add disable slow charging support

This commit adds a new function, disable_slow_battery_charging, to
disable charging on the Bluey mainboard. This function writes a disable
command to the SMBUS chargers, turning off the charging process.

Additionally, this patch makes the following changes to support this
new functionality:
 - The charging.c file is now compiled in both the romstage and
   ramstage phases.
 - The new disable_slow_battery_charging function is declared in
   board.h.
 - A new charging_status enum is introduced to clearly define the
   charging states.

These changes ensure that the system can now properly control charging,
allowing it to be disabled when necessary.

BUG=b:439819922
TEST=Able to build and boot google/quenbi.

Change-Id: Ic0c59e0509889e6d166becf76279718b853021cc
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89022
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/google/bluey/Makefile.mk |  2 ++
 src/mainboard/google/bluey/board.h     |  1 +
 src/mainboard/google/bluey/charging.c  | 16 +++++++++++++++-
 3 files changed, 18 insertions(+), 1 deletion(-)

diff --git a/src/mainboard/google/bluey/Makefile.mk b/src/mainboard/google/bluey/Makefile.mk
index 556509b3cb..87d58149af 100644
--- a/src/mainboard/google/bluey/Makefile.mk
+++ b/src/mainboard/google/bluey/Makefile.mk
@@ -12,4 +12,6 @@ romstage-y += romstage.c
 
 romstage-y += charging.c
 
+ramstage-y += charging.c
+
 ramstage-y += mainboard.c
diff --git a/src/mainboard/google/bluey/board.h b/src/mainboard/google/bluey/board.h
index 2a7120a719..31b6212256 100644
--- a/src/mainboard/google/bluey/board.h
+++ b/src/mainboard/google/bluey/board.h
@@ -39,5 +39,6 @@
 
 void setup_chromeos_gpios(void);
 void enable_slow_battery_charging(void);
+void disable_slow_battery_charging(void);
 
 #endif /* MAINBOARD_GOOGLE_BLUEY_BOARD_H */
diff --git a/src/mainboard/google/bluey/charging.c b/src/mainboard/google/bluey/charging.c
index 3b9e4492b9..2c1e447585 100644
--- a/src/mainboard/google/bluey/charging.c
+++ b/src/mainboard/google/bluey/charging.c
@@ -13,7 +13,11 @@
 #define SMB2_CHGR_CHRG_EN_CMD ((SMB2_SLAVE_ID << 16) | SCHG_CHGR_CHARGING_ENABLE_CMD)
 
 #define FCC_1A_STEP_50MA 0x14
-#define CHRG_ENABLE 0x01
+
+enum charging_status {
+	CHRG_DISABLE,
+	CHRG_ENABLE,
+};
 
 /*
  * Enable charging w/ 1A Icurrent supply at max.
@@ -27,3 +31,13 @@ void enable_slow_battery_charging(void)
 	spmi_write8(SMB1_CHGR_CHRG_EN_CMD, CHRG_ENABLE);
 	spmi_write8(SMB2_CHGR_CHRG_EN_CMD, CHRG_ENABLE);
 }
+
+/*
+ * Disable charging.
+ */
+void disable_slow_battery_charging(void)
+{
+	printk(BIOS_INFO, "Disable slow charge support\n");
+	spmi_write8(SMB1_CHGR_CHRG_EN_CMD, CHRG_DISABLE);
+	spmi_write8(SMB2_CHGR_CHRG_EN_CMD, CHRG_DISABLE);
+}

From f8685bb2ee9da104c896c45529716919df0e23c0 Mon Sep 17 00:00:00 2001
From: Zexin Wang <ot_zexin.wang@mediatek.corp-partner.google.com>
Date: Sun, 17 Aug 2025 12:43:53 +0800
Subject: [PATCH 1939/3886] soc/mediatek/mt8189: Enable lastbus debug hardware

Lastbus is a bus debug tool. When the bus hangs, the bus transmission
information before resetting will be recorded. The watchdog cannot
clear it and it will be printed out on the serial console for bus
hanging analysis. On MT8189, this feature is enabled by using the
common driver lastbusv2.

BUG=b:379008996
BRANCH=skywalker
TEST=When detected bus timeout, lastbus show:
debug_ctrl_ao_INFRA_AO 0x10023000 43
3a8a4f33
a8a48000
00080003
13018200
af99e400
0003fc90
00001104
0009c7e1
30c00033
00000001
00000003
00003294
003c00a3
019f9ccf
00000000
00200000
f007fffe
0000001f
0e800000
80143800
070c2002
ff9215de
001f9215
00009860
00000033
60000000
3a2e4919
000150c5
00000026
01416600
81438640
00000000
d6450001
0000000c
818b1501
00000540
80000000
fff70001
fff00000
fe00011e
000001ff
11040003
00004e67

timestamp: 0x22c18b05c

Signed-off-by: Zexin Wang <ot_zexin.wang@mediatek.corp-partner.google.com>
Change-Id: I8e0d8aa925e413459044737ffe4ef142fca8d627
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89024
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
---
 src/soc/mediatek/mt8189/Makefile.mk           |  1 +
 src/soc/mediatek/mt8189/bootblock.c           |  2 +
 .../mediatek/mt8189/include/soc/addressmap.h  |  5 ++
 src/soc/mediatek/mt8189/lastbus.c             | 46 +++++++++++++++++++
 4 files changed, 54 insertions(+)
 create mode 100644 src/soc/mediatek/mt8189/lastbus.c

diff --git a/src/soc/mediatek/mt8189/Makefile.mk b/src/soc/mediatek/mt8189/Makefile.mk
index 57666fc1d2..0a5a652d92 100644
--- a/src/soc/mediatek/mt8189/Makefile.mk
+++ b/src/soc/mediatek/mt8189/Makefile.mk
@@ -12,6 +12,7 @@ all-y += ../common/uart.c
 
 bootblock-y += ../common/bootblock.c bootblock.c
 bootblock-y += efuse.c
+bootblock-y += ../common/lastbus_v2.c lastbus.c
 bootblock-y += ../common/mmu_operations.c
 bootblock-y += ../common/mtcmos.c mtcmos.c
 bootblock-y += ../common/wdt.c ../common/wdt_req.c wdt.c
diff --git a/src/soc/mediatek/mt8189/bootblock.c b/src/soc/mediatek/mt8189/bootblock.c
index 8465a4974f..adf3938187 100644
--- a/src/soc/mediatek/mt8189/bootblock.c
+++ b/src/soc/mediatek/mt8189/bootblock.c
@@ -1,6 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0-only OR MIT */
 
 #include <bootblock_common.h>
+#include <soc/lastbus_v2.h>
 #include <soc/mmu_operations.h>
 #include <soc/pll.h>
 #include <soc/spm_mtcmos.h>
@@ -9,6 +10,7 @@
 void bootblock_soc_init(void)
 {
 	mtk_mmu_init();
+	lastbus_init();
 	mtk_wdt_init();
 	mt_pll_init();
 	mtcmos_init();
diff --git a/src/soc/mediatek/mt8189/include/soc/addressmap.h b/src/soc/mediatek/mt8189/include/soc/addressmap.h
index 8c633c5f17..abc9f972f0 100644
--- a/src/soc/mediatek/mt8189/include/soc/addressmap.h
+++ b/src/soc/mediatek/mt8189/include/soc/addressmap.h
@@ -33,8 +33,11 @@ enum {
 	APMIXED_BASE			= IO_PHYS + 0x0000C000,
 	DEVAPC_INFRA_SECU_AO_BASE	= IO_PHYS + 0x0001C000,
 	INFRA_AO_BCRM_BASE		= IO_PHYS + 0x00022000,
+	INFRA_AO_DEBUG_BASE		= IO_PHYS + 0x00023000,
+	INFRA_AO1_DEBUG_BASE		= IO_PHYS + 0x0002B000,
 	DEVAPC_INFRA_AO_BASE		= IO_PHYS + 0x00030000,
 	DEVAPC_INFRA_AO1_BASE		= IO_PHYS + 0x00034000,
+	EMISYS_NAO_DEBUG_BASE		= IO_PHYS + 0x00042000,
 	INFRACFG_BASE			= IO_PHYS + 0x0020E000,
 	EMI0_BASE			= IO_PHYS + 0x00219000,
 	EMI0_MPU_BASE			= IO_PHYS + 0x00226000,
@@ -58,6 +61,7 @@ enum {
 	AUXADC_BASE			= IO_PHYS + 0x01019000,
 	PERI_AO_BCRM_BASE		= IO_PHYS + 0x01035000,
 	PERICFG_AO_BASE			= IO_PHYS + 0x01036000,
+	PERI_PAR_AO_DEBUG_BASE		= IO_PHYS + 0x01037000,
 	DEVAPC_PERI_PAR_AO_BASE		= IO_PHYS + 0x0103C000,
 	AUDIO_BASE			= IO_PHYS + 0x01050000,
 	SSUSB_IPPC_BASE_P0		= IO_PHYS + 0x01203E00,
@@ -137,6 +141,7 @@ enum {
 	VLP_CK_BASE			= IO_PHYS + 0x0C012000,
 	PMICSPI_MST_BASE		= IO_PHYS + 0x0C013000,
 	DEVAPC_VLP_AO_BASE		= IO_PHYS + 0x0C018000,
+	VLP_AO_DEBUG_BASE		= IO_PHYS + 0x0C01D000,
 	SSPM_SRAM_BASE			= IO_PHYS + 0x0C300000,
 	SSPM_CFG_BASE			= IO_PHYS + 0x0C340000,
 	SCP_IIC_BASE			= IO_PHYS + 0x0C80A000,
diff --git a/src/soc/mediatek/mt8189/lastbus.c b/src/soc/mediatek/mt8189/lastbus.c
new file mode 100644
index 0000000000..f488ecee8a
--- /dev/null
+++ b/src/soc/mediatek/mt8189/lastbus.c
@@ -0,0 +1,46 @@
+/* SPDX-License-Identifier: GPL-2.0-only OR MIT */
+
+#include <device/mmio.h>
+#include <soc/addressmap.h>
+#include <soc/lastbus_v2.h>
+
+static const struct lastbus_monitor monitors[] = {
+	{
+		.name = "debug_ctrl_ao_INFRA_AO",
+		.base = INFRA_AO_DEBUG_BASE,
+		.num_ports = 43,
+		.bus_freq_mhz = 78,
+	},
+	{
+		.name = "debug_ctrl_ao_INFRA_AO1",
+		.base = INFRA_AO1_DEBUG_BASE,
+		.num_ports = 12,
+		.bus_freq_mhz = 78,
+	},
+	{
+		.name = "debug_ctrl_ao_EMISYS_NAO",
+		.base = EMISYS_NAO_DEBUG_BASE,
+		.num_ports = 11,
+		.bus_freq_mhz = 728,
+	},
+	{
+		.name = "debug_ctrl_ao_PERI_PAR_AO",
+		.base = PERI_PAR_AO_DEBUG_BASE,
+		.num_ports = 23,
+		.bus_freq_mhz = 78,
+	},
+	{
+		.name = "debug_ctrl_ao_VLP_AO",
+		.base = VLP_AO_DEBUG_BASE,
+		.num_ports = 12,
+		.bus_freq_mhz = 156,
+	},
+};
+
+const struct lastbus_config lastbus_cfg = {
+	.latch_platform = "MT8189",
+	.timeout_ms = 200,
+	.timeout_type = 0,
+	.num_used_monitors = ARRAY_SIZE(monitors),
+	.monitors = monitors,
+};

From baf159a1c8cef3e20b58b435ce7239306e752e06 Mon Sep 17 00:00:00 2001
From: Kapil Porwal <kapilporwal@google.com>
Date: Wed, 3 Sep 2025 09:33:01 +0530
Subject: [PATCH 1940/3886] mb/google/bluey: Configure GSC and EC for Quartz

BUG=b:441716957
TEST=build quartz board

Change-Id: I4a295112724fdb9d81d4aea168690acede94a5b7
Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89018
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/google/bluey/Kconfig | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/src/mainboard/google/bluey/Kconfig b/src/mainboard/google/bluey/Kconfig
index e40a253493..856589873a 100644
--- a/src/mainboard/google/bluey/Kconfig
+++ b/src/mainboard/google/bluey/Kconfig
@@ -124,11 +124,13 @@ config VBOOT
 config MAINBOARD_PART_NUMBER
 	default "Bluey" if BOARD_GOOGLE_MODEL_BLUEY
 	default "Quenbi" if BOARD_GOOGLE_MODEL_QUENBI
+	default "Quartz" if BOARD_GOOGLE_MODEL_QUARTZ
 
 config DRIVER_TPM_I2C_BUS
 	depends on I2C_TPM
 	hex
 	default 0xa if BOARD_GOOGLE_MODEL_QUENBI
+	default 0xa if BOARD_GOOGLE_MODEL_QUARTZ
 	default 0x10
 
 config DRIVER_TPM_I2C_ADDR
@@ -138,12 +140,14 @@ config EC_GOOGLE_CHROMEEC_SPI_BUS
 	depends on EC_GOOGLE_CHROMEEC
 	hex
 	default 0xd if BOARD_GOOGLE_MODEL_QUENBI
+	default 0xd if BOARD_GOOGLE_MODEL_QUARTZ
 	default 0xb
 
 config MAINBOARD_GPIO_PIN_FOR_GSC_AP_INTERRUPT
 	depends on TPM_GOOGLE_TI50
 	int
 	default 91 if BOARD_GOOGLE_MODEL_QUENBI
+	default 91 if BOARD_GOOGLE_MODEL_QUARTZ
 	default 34
 	help
 	  This option specifies the GPIO pin number on the mainboard that is

From 517185eca24b166be251236e31d71fe33ddd64c0 Mon Sep 17 00:00:00 2001
From: Kapil Porwal <kapilporwal@google.com>
Date: Wed, 3 Sep 2025 11:06:44 +0530
Subject: [PATCH 1941/3886] mb/google/bluey: Configure touchpad power GPIO

BUG=b:441716957
TEST=build quartz board

Change-Id: Icf9fea2c10a60b6aa798822f6d36f04f43608e9c
Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89019
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/google/bluey/Kconfig     | 8 ++++++++
 src/mainboard/google/bluey/board.h     | 3 +++
 src/mainboard/google/bluey/mainboard.c | 4 ++++
 3 files changed, 15 insertions(+)

diff --git a/src/mainboard/google/bluey/Kconfig b/src/mainboard/google/bluey/Kconfig
index 856589873a..b3e8cc0637 100644
--- a/src/mainboard/google/bluey/Kconfig
+++ b/src/mainboard/google/bluey/Kconfig
@@ -143,6 +143,14 @@ config EC_GOOGLE_CHROMEEC_SPI_BUS
 	default 0xd if BOARD_GOOGLE_MODEL_QUARTZ
 	default 0xb
 
+config MAINBOARD_GPIO_PIN_FOR_TOUCHPAD_POWER
+	int
+	default 36 if BOARD_GOOGLE_MODEL_QUARTZ
+	default 0
+	help
+	  This option specifies the GPIO pin number on the mainboard that is
+	  used for enabling power to the touchpad. Set it to 0 if unused.
+
 config MAINBOARD_GPIO_PIN_FOR_GSC_AP_INTERRUPT
 	depends on TPM_GOOGLE_TI50
 	int
diff --git a/src/mainboard/google/bluey/board.h b/src/mainboard/google/bluey/board.h
index 31b6212256..4a84e6333d 100644
--- a/src/mainboard/google/bluey/board.h
+++ b/src/mainboard/google/bluey/board.h
@@ -10,6 +10,9 @@
 #define GSC_AP_INT(x)		GPIO(x)
 #define GPIO_GSC_AP_INT		GSC_AP_INT(CONFIG_MAINBOARD_GPIO_PIN_FOR_GSC_AP_INTERRUPT)
 
+#define TP_POWER_GPIO(x)	GPIO(x)
+#define GPIO_TP_POWER_EN	TP_POWER_GPIO(CONFIG_MAINBOARD_GPIO_PIN_FOR_TOUCHPAD_POWER)
+
 /* Fingerprint-specific GPIOs. Only for fingerprint-enabled devices. */
 #if CONFIG(MAINBOARD_HAS_FINGERPRINT)
 #define GPIO_FP_RST_L		GPIO(25)
diff --git a/src/mainboard/google/bluey/mainboard.c b/src/mainboard/google/bluey/mainboard.c
index 9950f88545..1ff845c541 100644
--- a/src/mainboard/google/bluey/mainboard.c
+++ b/src/mainboard/google/bluey/mainboard.c
@@ -43,6 +43,10 @@ static void mainboard_init(struct device *dev)
 	if (CONFIG(MAINBOARD_HAS_FINGERPRINT_VIA_SPI))
 		qupv3_se_fw_load_and_init(QUPV3_2_SE2, SE_PROTOCOL_SPI, MIXED); /* Fingerprint SPI */
 
+	/* Enable touchpad power */
+	if (CONFIG_MAINBOARD_GPIO_PIN_FOR_TOUCHPAD_POWER)
+		gpio_output(GPIO_TP_POWER_EN, 1);
+
 	/*
 	 * Deassert FPMCU reset. Power applied in romstage
 	 * has now stabilized.

From ffbf40f6c0af6e49ab1d4ace8090ee8e0ef386bd Mon Sep 17 00:00:00 2001
From: Kapil Porwal <kapilporwal@google.com>
Date: Mon, 1 Sep 2025 11:18:32 +0530
Subject: [PATCH 1942/3886] ec/google/chromeec: Update EC headers

Generated using update_ec_headers.sh [EC-DIR]

The original include/ec_commands.h version in the EC repo is:
  9b00e297ee chipset: Add a host command to issue AP shutdown
The original include/ec_cmd_api.h version in the EC repo is:
  0c77d31000 UCSI/PPM: Add ucsi_host_cmd tests

Change-Id: I9b27cdd946c2e20a996ef338ec57d08de4e26059
Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89007
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
---
 src/ec/google/chromeec/ec_cmd_api.h  |   6 +
 src/ec/google/chromeec/ec_commands.h | 515 +++++++++++++++++++++------
 2 files changed, 406 insertions(+), 115 deletions(-)

diff --git a/src/ec/google/chromeec/ec_cmd_api.h b/src/ec/google/chromeec/ec_cmd_api.h
index cab69b724b..a74ba441e5 100644
--- a/src/ec/google/chromeec/ec_cmd_api.h
+++ b/src/ec/google/chromeec/ec_cmd_api.h
@@ -373,8 +373,12 @@ _CROS_EC_CV_F_P_R(EC_CMD_MOTION_SENSE_CMD, 4, motion_sense_cmd_v4, motion_sense,
 _CROS_EC_CV_F_P(EC_CMD_OVERRIDE_DEDICATED_CHARGER_LIMIT, 0,
 		override_dedicated_charger_limit, dedicated_charger_limit);
 _CROS_EC_C0_F_RF(EC_CMD_PCHG_COUNT, pchg_count);
+_CROS_EC_C0_F_PF_RF(EC_CMD_PDC_TRACE_MSG_ENABLE, pdc_trace_msg_enable);
+_CROS_EC_C0_F_RF(EC_CMD_PDC_TRACE_MSG_GET_ENTRIES, pdc_trace_msg_get_entries);
 _CROS_EC_CV_F_P(EC_CMD_PD_CHARGE_PORT_OVERRIDE, 0, pd_charge_port_override,
 		charge_port_override);
+_CROS_EC_CV_F_P_R(EC_CMD_PD_CHIP_INFO, 3, pd_chip_info_v3, pd_chip_info,
+		  pd_chip_info_v3);
 _CROS_EC_CV_F_P_R(EC_CMD_PD_CHIP_INFO, 2, pd_chip_info_v2, pd_chip_info,
 		  pd_chip_info_v2);
 _CROS_EC_CV_F_P_R(EC_CMD_PD_CHIP_INFO, 1, pd_chip_info_v1, pd_chip_info,
@@ -446,6 +450,8 @@ _CROS_EC_C0_F_PF(EC_CMD_USB_PD_RW_HASH_ENTRY, usb_pd_rw_hash_entry);
 _CROS_EC_C0_F_PF_RF(EC_CMD_VBOOT_HASH, vboot_hash);
 _CROS_EC_C0_F_PF_RF(EC_CMD_VSTORE_READ, vstore_read);
 _CROS_EC_C0_F_PF(EC_CMD_VSTORE_WRITE, vstore_write);
+_CROS_EC_C0_F_PF(EC_CMD_UCSI_PPM_SET, ucsi_ppm_set);
+_CROS_EC_C0_F_PF(EC_CMD_UCSI_PPM_GET, ucsi_ppm_get);
 
 #ifdef __cplusplus
 }
diff --git a/src/ec/google/chromeec/ec_commands.h b/src/ec/google/chromeec/ec_commands.h
index 1673c8b362..cff113c56f 100644
--- a/src/ec/google/chromeec/ec_commands.h
+++ b/src/ec/google/chromeec/ec_commands.h
@@ -5,12 +5,6 @@
 
 /* Host communication command constants for Chrome EC */
 
-/*
- * TODO(b/272518464): Work around coreboot GCC preprocessor bug.
- * #line marks the *next* line, so it is off by one.
- */
-#line 13
-
 #ifndef __CROS_EC_EC_COMMANDS_H
 #define __CROS_EC_EC_COMMANDS_H
 
@@ -148,6 +142,8 @@ extern "C" {
 #define EC_MEMMAP_SIZE 255 /* ACPI IO buffer max is 255 bytes */
 #define EC_MEMMAP_TEXT_MAX 8 /* Size of a string in the memory map */
 
+#define EC_LPC_ADDR_MEMMAP_INDEXED_IO 0x380
+
 /* The offset address of each type of data in mapped memory. */
 #define EC_MEMMAP_TEMP_SENSOR 0x00 /* Temp sensors 0x00 - 0x0f */
 #define EC_MEMMAP_FAN 0x10 /* Fan speeds 0x10 - 0x17 */
@@ -272,10 +268,21 @@ extern "C" {
 #define EC_BATT_FLAG_INVALID_DATA 0x20
 #define EC_BATT_FLAG_CUT_OFF 0x40
 
+/*
+ * Value written to EC_MEMMAP_BATT_DCAP, EC_MEMMAP_BATT_DVLT, EC_MEMMAP_CCNT,
+ * EC_MEMMAP_BATT_VOLT, EC_MEMMAP_BATT_RATE, EC_MEMMAP_BATT_CAP, and
+ * EC_MEMMAP_BATT_LFCC if the actual value is unknown.
+ *
+ * This corresponds with the unknown value specified by ACPI release 6.5
+ * 10.2.2 (and earlier versions), to match expectations of ACPI firmware.
+ */
+#define EC_MEMMAP_BATT_UNKNOWN_VALUE (-1)
+
 /* Switch flags at EC_MEMMAP_SWITCHES */
 #define EC_SWITCH_LID_OPEN 0x01
 #define EC_SWITCH_POWER_BUTTON_PRESSED 0x02
-#define EC_SWITCH_WRITE_PROTECT_DISABLED 0x04
+/* Was write protect disabled; now unused. */
+#define EC_SWITCH_IGNORE2 0x04
 /* Was recovery requested via keyboard; now unused. */
 #define EC_SWITCH_IGNORE1 0x08
 /* Recovery requested via dedicated signal (from servo board) */
@@ -526,6 +533,65 @@ extern "C" {
 #define EC_ACPI_MEM_USB_RETIMER_OP(x) \
 	(((x) & 0xf0) >> USB_RETIMER_FW_UPDATE_OP_SHIFT)
 
+/*
+ * Offset 0x15 is reserved for PBOK, added to coreboot in
+ * https://crrev.com/c/3840943 and proposed for inclusion here
+ * in https://crrev.com/c/3547317.
+ */
+
+/*
+ * Get extended strings from the EC.
+ * Write:
+ *     String index, or 0 to probe for EC support.
+ * Read:
+ *     String bytes, following by repeating null bytes.
+ *
+ * Writing a byte (EC_ACPI_MEM_STRINGS_FIFO_ID_*) selects a string, and the
+ * following reads return the non-null bytes of the string in sequence until
+ * the end of the string is reached. After the end of the string, reads 0 until
+ * another byte is written. This interface allows ACPI firmware to read longer
+ * strings from the EC than can reasonably fit into the shared memory region.
+ *
+ * To probe for EC support, write FIFO_ID_VERSION and read will return at least
+ * one nonzero (MEM_STRINGS_FIFO_V1 for example) if MEM_STRINGS_FIFO is
+ * supported. Returned values will indicate which strings are supported. If the
+ * first byte is 0xff, the strings FIFO is unsupported.
+ */
+#define EC_ACPI_MEM_STRINGS_FIFO 0x16
+
+/* String index to probe EC support. */
+#define EC_ACPI_MEM_STRINGS_FIFO_ID_VERSION 0
+#define EC_ACPI_MEM_STRINGS_FIFO_V1 1
+/*
+ * 0xff is the value the EC returns for unimplemented reads, indicating
+ * the current EC firmware does not implement this command.
+ */
+#define EC_ACPI_MEM_STRINGS_FIFO_UNSUPPORTED 0xff
+
+/*
+ * Battery model number for the selected battery. Supported since V1.
+ * Presents the same data as EC_MEMMAP_BATT_MODEL, but can provide more
+ * than 8 bytes.
+ *
+ * This and the other FIFO_ID_BATTERY strings can select one of multiple
+ * batteries by changing the value at EC_MEMMAP_BATT_INDEX. Once that index
+ * is changed, reads of these strings will return information for the
+ * corresponding battery, if present.
+ */
+#define EC_ACPI_MEM_STRINGS_FIFO_ID_BATTERY_MODEL 1
+/*
+ * Battery serial number for the selected battery. Supported since V1.
+ * Presents the same data as EC_MEMMAP_BATT_SERIAL, but can provide more
+ * than 8 bytes.
+ */
+#define EC_ACPI_MEM_STRINGS_FIFO_ID_BATTERY_SERIAL 2
+/*
+ * Battery manufacturer for the selected battery. Supported since V1.
+ * Presents the same data as EC_MEMMAP_BATT_MFGR, but can provide more
+ * than 8 bytes.
+ */
+#define EC_ACPI_MEM_STRINGS_FIFO_ID_BATTERY_MANUFACTURER 3
+
 /*
  * ACPI addresses 0x20 - 0xff map to EC_MEMMAP offset 0x00 - 0xdf.  This data
  * is read-only from the AP.  Added in EC_ACPI_MEM_VERSION 2.
@@ -874,7 +940,7 @@ enum host_event_code {
 };
 
 /* Host event mask */
-#define EC_HOST_EVENT_MASK(event_code) BIT_ULL((event_code)-1)
+#define EC_HOST_EVENT_MASK(event_code) BIT_ULL((event_code) - 1)
 
 /* clang-format off */
 #define HOST_EVENT_TEXT                                                        \
@@ -1701,6 +1767,14 @@ enum ec_feature_code {
 	 * The EC supports UCSI PPM.
 	 */
 	EC_FEATURE_UCSI_PPM = 54,
+	/*
+	 * The EC supports Strauss keyboard.
+	 */
+	EC_FEATURE_STRAUSS = 55,
+	/*
+	 * The EC supports PoE.
+	 */
+	EC_FEATURE_POE = 56,
 };
 
 #define EC_FEATURE_MASK_0(event_code) BIT(event_code % 32)
@@ -1836,7 +1910,7 @@ struct ec_response_flash_info_2 {
 	uint16_t num_banks_total;
 	/* Number of banks described in banks array. */
 	uint16_t num_banks_desc;
-	struct ec_flash_bank banks[0];
+	struct ec_flash_bank banks[FLEXIBLE_ARRAY_MEMBER_SIZE];
 } __ec_align4;
 
 /*
@@ -2274,6 +2348,16 @@ struct ec_response_pwm_get_duty {
 	uint16_t duty; /* Duty cycle, EC_PWM_MAX_DUTY = 100% */
 } __ec_align2;
 
+#define EC_CMD_PWM_GET_FAN_DUTY 0x0027
+
+struct ec_params_pwm_get_fan_duty {
+	uint8_t fan_idx;
+} __ec_align1;
+
+struct ec_response_pwm_get_fan_duty {
+	uint32_t percent; /* Percentage of duty cycle, ranging from 0 ~ 100 */
+} __ec_align4;
+
 /*****************************************************************************/
 /*
  * Lightbar commands. This looks worse than it is. Since we only use one HOST
@@ -2607,6 +2691,8 @@ enum ec_led_id {
 	EC_LED_ID_RECOVERY_HW_REINIT_LED,
 	/* LED to indicate sysrq debug mode. */
 	EC_LED_ID_SYSRQ_DEBUG_LED,
+	/* LED strip for advanced patterns. */
+	EC_LED_ID_LIGHTBAR_LED,
 
 	EC_LED_ID_COUNT,
 };
@@ -3058,7 +3144,7 @@ struct ec_params_motion_sense {
 		 */
 		struct __ec_todo_unpacked {
 			/* Data to set or EC_MOTION_SENSE_NO_VALUE to read.
-			 * kb_wake_angle: angle to wakup AP.
+			 * kb_wake_angle: angle to wakeup AP.
 			 */
 			int16_t data;
 		} kb_wake_angle;
@@ -3704,14 +3790,31 @@ struct ec_params_thermal_set_threshold_v1 {
 
 /****************************************************************************/
 
-/* Toggle automatic fan control */
+/* Set or get fan control mode */
 #define EC_CMD_THERMAL_AUTO_FAN_CTRL 0x0052
 
+enum ec_auto_fan_ctrl_cmd {
+	EC_AUTO_FAN_CONTROL_CMD_SET = 0,
+	EC_AUTO_FAN_CONTROL_CMD_GET,
+};
+
 /* Version 1 of input params */
 struct ec_params_auto_fan_ctrl_v1 {
 	uint8_t fan_idx;
 } __ec_align1;
 
+/* Version 2 of input params */
+struct ec_params_auto_fan_ctrl_v2 {
+	uint8_t fan_idx;
+	uint8_t cmd; /* enum ec_auto_fan_ctrl_cmd */
+	uint8_t set_auto; /* only used with EC_AUTO_FAN_CONTROL_CMD_SET - bool
+			   */
+} __ec_align4;
+
+struct ec_response_auto_fan_control {
+	uint8_t is_auto; /* bool */
+} __ec_align1;
+
 /* Get/Set TMP006 calibration data */
 #define EC_CMD_TMP006_GET_CALIBRATION 0x0053
 #define EC_CMD_TMP006_SET_CALIBRATION 0x0054
@@ -3752,7 +3855,7 @@ struct ec_response_tmp006_get_calibration_v1 {
 	uint8_t algorithm;
 	uint8_t num_params;
 	uint8_t reserved[2];
-	float val[0];
+	float val[FLEXIBLE_ARRAY_MEMBER_SIZE];
 } __ec_align4;
 
 struct ec_params_tmp006_set_calibration_v1 {
@@ -3760,7 +3863,7 @@ struct ec_params_tmp006_set_calibration_v1 {
 	uint8_t algorithm;
 	uint8_t num_params;
 	uint8_t reserved;
-	float val[0];
+	float val[FLEXIBLE_ARRAY_MEMBER_SIZE];
 } __ec_align4;
 
 /* Read raw TMP006 data */
@@ -3947,7 +4050,8 @@ struct ec_params_keyscan_seq_ctrl {
 			 * start of the sequence.
 			 */
 			uint32_t time_us;
-			uint8_t scan[0]; /* keyscan data */
+			/* keyscan data */
+			uint8_t scan[FLEXIBLE_ARRAY_MEMBER_SIZE];
 		} add;
 		struct __ec_align1 {
 			uint8_t start_item; /* First item to return */
@@ -3961,7 +4065,7 @@ struct ec_result_keyscan_seq_ctrl {
 		struct __ec_todo_unpacked {
 			uint8_t num_items; /* Number of items */
 			/* Data for each item */
-			struct ec_collect_item item[0];
+			struct ec_collect_item item[FLEXIBLE_ARRAY_MEMBER_SIZE];
 		} collect;
 	};
 } __ec_todo_packed;
@@ -4783,14 +4887,15 @@ struct ec_params_i2c_passthru_msg {
 struct ec_params_i2c_passthru {
 	uint8_t port; /* I2C port number */
 	uint8_t num_msgs; /* Number of messages */
-	struct ec_params_i2c_passthru_msg msg[];
+	struct ec_params_i2c_passthru_msg msg[FLEXIBLE_ARRAY_MEMBER_SIZE];
 	/* Data to write for all messages is concatenated here */
 } __ec_align2;
 
 struct ec_response_i2c_passthru {
 	uint8_t i2c_status; /* Status flags (EC_I2C_STATUS_...) */
 	uint8_t num_msgs; /* Number of messages processed */
-	uint8_t data[]; /* Data read by messages concatenated here */
+	/* Data read by messages concatenated here */
+	uint8_t data[FLEXIBLE_ARRAY_MEMBER_SIZE];
 } __ec_align1;
 
 /*****************************************************************************/
@@ -4881,6 +4986,33 @@ enum charge_state_params {
 	 */
 	CS_PARAM_LIMIT_POWER,
 
+	/* min value of charger voltage limit (READ ONLY) */
+	CS_PARAM_CHG_VOLTAGE_MIN,
+
+	/* max value of charger voltage limit (READ ONLY) */
+	CS_PARAM_CHG_VOLTAGE_MAX,
+
+	/* step value of charger voltage limit (READ ONLY) */
+	CS_PARAM_CHG_VOLTAGE_STEP,
+
+	/* min value of charger current limit (READ ONLY) */
+	CS_PARAM_CHG_CURRENT_MIN,
+
+	/* max value of charger current limit (READ ONLY) */
+	CS_PARAM_CHG_CURRENT_MAX,
+
+	/* step value of charger current limit (READ ONLY) */
+	CS_PARAM_CHG_CURRENT_STEP,
+
+	/* min value of charger input current limit (READ ONLY) */
+	CS_PARAM_CHG_INPUT_CURRENT_MIN,
+
+	/* max value of charger input current limit (READ ONLY) */
+	CS_PARAM_CHG_INPUT_CURRENT_MAX,
+
+	/* step value of charger input current limit (READ ONLY) */
+	CS_PARAM_CHG_INPUT_CURRENT_STEP,
+
 	/* How many so far? */
 	CS_NUM_BASE_PARAMS,
 
@@ -5786,6 +5918,44 @@ struct ec_params_memory_dump_read_memory {
 	uint32_t size;
 } __ec_align4;
 
+#define EC_CMD_PANIC_LOG_INFO 0x00E0
+
+/*
+ * Parameters for configuring the panic log.
+ * Freeze and unfreeze are mutually exclusive.
+ */
+struct ec_params_panic_log_info {
+	/* Reset panic log */
+	uint8_t reset;
+	/* Freeze panic log */
+	uint8_t freeze;
+	/* Unfreeze panic log */
+	uint8_t unfreeze;
+} __ec_align1;
+
+/*
+ * Returns the panic log info before applying the configuration
+ * in ec_params_panic_log_info.
+ */
+struct ec_response_panic_log_info {
+	uint32_t version;
+	uint32_t capacity;
+	uint32_t length;
+	uint8_t valid;
+	uint8_t frozen;
+} __ec_align4;
+
+#define EC_CMD_PANIC_LOG_READ 0x00E1
+
+/*
+ * Read from panic log at given byte offset. Will read up to the end of the
+ * panic log or response max. Use EC_CMD_PANIC_LOG_INFO command to freeze
+ * the log and get the length before reading.
+ */
+struct ec_params_panic_log_read {
+	uint32_t offset;
+} __ec_align4;
+
 /*
  * EC_CMD_MEMORY_DUMP_READ_MEMORY response buffer is written directly into
  * host_cmd_handler_args.response and host_cmd_handler_args.response_size.
@@ -5861,6 +6031,7 @@ struct ec_response_pd_status {
 #define PD_EVENT_DATA_SWAP BIT(3)
 #define PD_EVENT_TYPEC BIT(4)
 #define PD_EVENT_PPM BIT(5)
+#define PD_EVENT_INIT BIT(6)
 
 struct ec_response_host_event_status {
 	uint32_t status; /* PD MCU host event status */
@@ -6132,7 +6303,8 @@ struct ec_response_pd_log {
 	uint8_t type; /* event type : see PD_EVENT_xx below */
 	uint8_t size_port; /* [7:5] port number [4:0] payload size in bytes */
 	uint16_t data; /* type-defined data payload */
-	uint8_t payload[0]; /* optional additional data payload: 0..16 bytes */
+	/* optional additional data payload: 0..16 bytes */
+	uint8_t payload[FLEXIBLE_ARRAY_MEMBER_SIZE];
 } __ec_align4;
 
 /* The timestamp is the microsecond counter shifted to get about a ms. */
@@ -6343,6 +6515,7 @@ struct ec_response_pd_chip_info_v1 {
  *  does NOT include a NUL-terminator.
  */
 #define USB_PD_CHIP_INFO_PROJECT_NAME_LEN 12
+
 struct ec_response_pd_chip_info_v2 {
 	uint16_t vendor_id;
 	uint16_t product_id;
@@ -6363,6 +6536,33 @@ struct ec_response_pd_chip_info_v2 {
 	char fw_name_str[USB_PD_CHIP_INFO_PROJECT_NAME_LEN + 1];
 } __ec_align2;
 
+/** Maximum length of a driver/chip name reported in the pd_chip_info
+ *  response
+ */
+#define USB_PD_CHIP_INFO_DRIVER_NAME_LEN 24
+
+struct ec_response_pd_chip_info_v3 {
+	uint16_t vendor_id;
+	uint16_t product_id;
+	uint16_t device_id;
+	union {
+		uint8_t fw_version_string[8];
+		uint64_t fw_version_number;
+	} __ec_align2;
+	union {
+		uint8_t min_req_fw_version_string[8];
+		uint64_t min_req_fw_version_number;
+	} __ec_align2;
+	/** Flag to control the FW update process for this chip. */
+	uint16_t fw_update_flags;
+	/** Project name string associated with the chip's FW. Add an extra
+	 *  byte for a NUL-terminator.
+	 */
+	char fw_name_str[USB_PD_CHIP_INFO_PROJECT_NAME_LEN + 1];
+	/** Driver/chip string, plus room for a NUL-terminator */
+	char driver_name[USB_PD_CHIP_INFO_DRIVER_NAME_LEN + 1];
+} __ec_align2;
+
 /* Run RW signature verification and get status */
 #define EC_CMD_RWSIG_CHECK_STATUS 0x011C
 
@@ -6413,31 +6613,22 @@ enum cbi_data_tag {
 	/* Second Source Factory Cache */
 	CBI_TAG_SSFC = 8, /* uint32_t bit field */
 	CBI_TAG_REWORK_ID = 9, /* uint64_t or smaller */
-	CBI_TAG_FACTORY_CALIBRATION_DATA = 10, /* uint32_t bit field */
-
-	/*
-	 * A uint32_t field reserved for controlling common features at runtime.
-	 * It shouldn't be used at board-level. See union ec_common_control for
-	 * the bit definitions.
-	 */
-	CBI_TAG_COMMON_CONTROL = 11,
-
+	CBI_TAG_FACTORY_CALIBRATION_DATA = 10, /* Deprecated */
+	CBI_TAG_COMMON_CONTROL = 11, /* Deprecated */
 	/* struct board_batt_params */
 	CBI_TAG_BATTERY_CONFIG = 12,
 	/* CBI_TAG_BATTERY_CONFIG_1 ~ 15 will use 13 ~ 27. */
 	CBI_TAG_BATTERY_CONFIG_15 = 27,
 
+	/* CBI_TAG_PROVISION_MATRIX_VERSION
+	 * Version of the current provision matrix
+	 */
+	CBI_TAG_PROVISION_MATRIX_VERSION = 28, /* uint32_t bit field */
+
 	/* Last entry */
 	CBI_TAG_COUNT,
 };
 
-union ec_common_control {
-	struct {
-		uint32_t ucsi_enabled : 1;
-	};
-	uint32_t raw_value;
-};
-
 /*
  * Flags to control read operation
  *
@@ -6466,7 +6657,7 @@ struct ec_params_set_cbi {
 	uint32_t tag; /* enum cbi_data_tag */
 	uint32_t flag; /* CBI_SET_* */
 	uint32_t size; /* Data size */
-	uint8_t data[]; /* For string and raw data */
+	uint8_t data[FLEXIBLE_ARRAY_MEMBER_SIZE]; /* For string and raw data */
 } __ec_align1;
 
 /*
@@ -6498,7 +6689,7 @@ struct ec_params_set_cbi_bin {
 	uint32_t offset; /* Data offset */
 	uint32_t size; /* Data size */
 	uint8_t flags; /* bit field for EC_CBI_BIN_COMMIT_FLAG_* */
-	uint8_t data[]; /* For string and raw data */
+	uint8_t data[FLEXIBLE_ARRAY_MEMBER_SIZE]; /* For string and raw data */
 } __ec_align1;
 
 /*
@@ -6596,6 +6787,8 @@ enum chipset_shutdown_reason {
 	CHIPSET_SHUTDOWN_THERMAL,
 	/* Force a chipset shutdown from the power button through EC */
 	CHIPSET_SHUTDOWN_BUTTON,
+	/* Force a chipset shutdown, because the AP wants to. */
+	CHIPSET_SHUTDOWN_HOST_CMD,
 
 	CHIPSET_SHUTDOWN_COUNT, /* End of shutdown reasons. */
 };
@@ -7113,7 +7306,7 @@ struct ec_response_typec_discovery {
 	uint8_t svid_count; /* Number of SVIDs partner sent */
 	uint16_t reserved;
 	uint32_t discovery_vdo[VDO_MAX_OBJECTS];
-	struct svid_mode_info svids[0];
+	struct svid_mode_info svids[FLEXIBLE_ARRAY_MEMBER_SIZE];
 } __ec_align1;
 
 /* USB Type-C commands for AP-controlled device policy. */
@@ -7625,7 +7818,7 @@ struct ec_params_pchg_update {
 	/* Size of <data> */
 	uint32_t size;
 	/* Partial data of new firmware */
-	uint8_t data[];
+	uint8_t data[FLEXIBLE_ARRAY_MEMBER_SIZE];
 } __ec_align4;
 
 BUILD_ASSERT(EC_PCHG_UPDATE_CMD_COUNT <
@@ -7759,7 +7952,7 @@ struct ec_params_rgbkbd_set_color {
 	/* Specifies # of elements in <color>. */
 	uint8_t length;
 	/* RGB color data array of length up to MAX_KEY_COUNT. */
-	struct rgb_s color[];
+	struct rgb_s color[FLEXIBLE_ARRAY_MEMBER_SIZE];
 } __ec_align1;
 
 /*
@@ -7976,7 +8169,7 @@ struct ec_params_ap_fw_state {
 /* The data size is stored in the host command protocol header. */
 struct ec_params_ucsi_ppm_set {
 	uint16_t offset;
-	uint8_t data[];
+	uint8_t data[FLEXIBLE_ARRAY_MEMBER_SIZE];
 } __ec_align2;
 
 #define EC_CMD_UCSI_PPM_GET 0x0141
@@ -7994,6 +8187,82 @@ struct ec_params_set_alarm_slp_s0_dbg {
 	uint32_t time;
 } __ec_align2;
 
+/*
+ * Control PDC tracing.
+ *   EC_PDC_TRACE_MSG_PORT_NONE disable tracing
+ *   EC_PDC_TRACE_MSG_PORT_ALL enable tracing on all ports
+ *   else, enable tracing on a specific port.
+ */
+
+#define EC_CMD_PDC_TRACE_MSG_ENABLE 0x0143
+
+#define EC_PDC_TRACE_MSG_PORT_NONE 0xff
+#define EC_PDC_TRACE_MSG_PORT_ALL 0xfe
+
+struct ec_params_pdc_trace_msg_enable {
+	uint8_t port;
+};
+
+struct ec_response_pdc_trace_msg_enable {
+	/* Previous port value. */
+	uint8_t port;
+	uint8_t reserved;
+	/* Number of free bytes in FIFO. */
+	uint16_t fifo_free;
+	/* Running total of dropped messages (may wrap). */
+	uint32_t dropped_count;
+} __ec_align4;
+
+/*
+ * Fetch multiple PDC trace entries.
+ *
+ * If no entries are available, pl_size is 0.
+ * At most MAX_HC_PDC_TRACE_MSG_GET_PAYLOAD bytes worth of entries
+ * are returned. Only whole entries are returned.
+ */
+
+#define EC_CMD_PDC_TRACE_MSG_GET_ENTRIES 0x0144
+#define MAX_HC_PDC_TRACE_MSG_GET_PAYLOAD 240
+
+struct ec_response_pdc_trace_msg_get_entries {
+	/* Total bytes of payload. */
+	uint16_t pl_size;
+	/* Packed array of pdc_trace_msg_entry structs. */
+	uint8_t payload[FLEXIBLE_ARRAY_MEMBER_SIZE];
+};
+
+enum pdc_trace_msg_direction {
+	PDC_TRACE_MSG_DIR_IN = 0,
+	PDC_TRACE_MSG_DIR_OUT = 1,
+};
+
+struct pdc_trace_msg_entry {
+	/*
+	 * Timestamp - least significant 32 bits of EC epoch time
+	 * (microseconds, will wrap around).
+	 */
+	uint32_t time32_us;
+	/* Entry sequence number (wraps around). */
+	uint16_t seq_num;
+	/* Port number associated with this entry. */
+	uint8_t port_num;
+	/* Direction of message (enum pdc_trace_msg_direction) */
+	uint8_t direction;
+	/* Format of pdc_data (PDC chip identifier). */
+	uint8_t msg_type;
+	/* Bytes in pdc_data. */
+	uint8_t pdc_data_size;
+	/* Captured PDC message. */
+	uint8_t pdc_data[FLEXIBLE_ARRAY_MEMBER_SIZE];
+} __ec_align1;
+
+/* Enable/disable Ethernet POE power */
+#define EC_CMD_SWITCH_ENABLE_POE 0x0145
+
+struct ec_params_switch_enable_poe {
+	uint8_t enabled;
+} __ec_align1;
+
 /*****************************************************************************/
 /* The command range 0x200-0x2FF is reserved for Rotor. */
 
@@ -8019,7 +8288,7 @@ struct ec_params_set_alarm_slp_s0_dbg {
 struct ec_params_fp_passthru {
 	uint16_t len; /* Number of bytes to write then read */
 	uint16_t flags; /* EC_FP_FLAG_xxx */
-	uint8_t data[]; /* Data to send */
+	uint8_t data[FLEXIBLE_ARRAY_MEMBER_SIZE]; /* Data to send */
 } __ec_align2;
 
 /* Configure the Fingerprint MCU behavior */
@@ -8052,9 +8321,9 @@ struct ec_params_fp_passthru {
 	 FP_MODE_MATCH | FP_MODE_RESET_SENSOR | FP_MODE_SENSOR_MAINTENANCE | \
 	 FP_MODE_DONT_CHANGE)
 
-/* Capture types defined in bits [30..28] */
-#define FP_MODE_CAPTURE_TYPE_SHIFT 28
-#define FP_MODE_CAPTURE_TYPE_MASK (0x7 << FP_MODE_CAPTURE_TYPE_SHIFT)
+/* Capture types defined in bits [30..26] */
+#define FP_MODE_CAPTURE_TYPE_SHIFT 26
+#define FP_MODE_CAPTURE_TYPE_MASK (0x1F << FP_MODE_CAPTURE_TYPE_SHIFT)
 /**
  * enum fp_capture_type - Specifies the "mode" when capturing images.
  *
@@ -8062,6 +8331,9 @@ struct ec_params_fp_passthru {
  * image (produces 'frame_size' bytes)
  * @FP_CAPTURE_SIMPLE_IMAGE: Simple raw image capture (produces width x height x
  * bpp bits)
+ * @FP_CAPTURE_DEFECT_PXL_TEST: Capture for check defect pixel test
+ * @FP_CAPTURE_ABNORMAL_TEST: Capture for check abnormal pixel test
+ * @FP_CAPTURE_NOISE_TEST: Capture for check noise test
  * @FP_CAPTURE_PATTERN0: Self test pattern (e.g. checkerboard)
  * @FP_CAPTURE_PATTERN1: Self test pattern (e.g. inverted checkerboard)
  * @FP_CAPTURE_QUALITY_TEST: Capture for Quality test with fixed contrast
@@ -8073,16 +8345,24 @@ struct ec_params_fp_passthru {
  */
 enum fp_capture_type {
 	FP_CAPTURE_VENDOR_FORMAT = 0,
-	FP_CAPTURE_SIMPLE_IMAGE = 1,
-	FP_CAPTURE_PATTERN0 = 2,
-	FP_CAPTURE_PATTERN1 = 3,
-	FP_CAPTURE_QUALITY_TEST = 4,
-	FP_CAPTURE_RESET_TEST = 5,
+	FP_CAPTURE_DEFECT_PXL_TEST = 1,
+	FP_CAPTURE_ABNORMAL_TEST = 2,
+	FP_CAPTURE_NOISE_TEST = 3,
+	FP_CAPTURE_SIMPLE_IMAGE = 4,
+	FP_CAPTURE_PATTERN0 = 8,
+	FP_CAPTURE_PATTERN1 = 12,
+	FP_CAPTURE_QUALITY_TEST = 16,
+	FP_CAPTURE_RESET_TEST = 20,
 	FP_CAPTURE_TYPE_MAX,
 };
+
+/* The maximum number of capture types in enum fp_capture_type */
+#define FP_MAX_CAPTURE_TYPES 9
+
 /* Extracts the capture type from the sensor 'mode' word */
-#define FP_CAPTURE_TYPE(mode) \
-	(((mode) & FP_MODE_CAPTURE_TYPE_MASK) >> FP_MODE_CAPTURE_TYPE_SHIFT)
+#define FP_CAPTURE_TYPE(mode)                                          \
+	(enum fp_capture_type)(((mode) & FP_MODE_CAPTURE_TYPE_MASK) >> \
+			       FP_MODE_CAPTURE_TYPE_SHIFT)
 
 struct ec_params_fp_mode {
 	uint32_t mode; /* as defined by FP_MODE_ constants */
@@ -8095,10 +8375,14 @@ struct ec_response_fp_mode {
 /* Retrieve Fingerprint sensor information */
 #define EC_CMD_FP_INFO 0x0403
 
+/* Mask for dead pixels */
+#define FP_ERROR_DEAD_PIXELS_MASK 0x3FF
+/* Maximum number of dead pixels */
+#define FP_ERROR_DEAD_PIXELS_MAX (FP_ERROR_DEAD_PIXELS_MASK - 1)
 /* Number of dead pixels detected on the last maintenance */
-#define FP_ERROR_DEAD_PIXELS(errors) ((errors) & 0x3FF)
+#define FP_ERROR_DEAD_PIXELS(errors) ((errors) & FP_ERROR_DEAD_PIXELS_MASK)
 /* Unknown number of dead pixels detected on the last maintenance */
-#define FP_ERROR_DEAD_PIXELS_UNKNOWN (0x3FF)
+#define FP_ERROR_DEAD_PIXELS_UNKNOWN (FP_ERROR_DEAD_PIXELS_MASK)
 /* No interrupt from the sensor */
 #define FP_ERROR_NO_IRQ BIT(12)
 /* SPI communication error */
@@ -8144,6 +8428,51 @@ struct ec_response_fp_info {
 	uint32_t template_version; /* version of the template format */
 } __ec_align4;
 
+struct fp_sensor_info {
+	/* Sensor identification */
+	uint32_t vendor_id;
+	uint32_t product_id;
+	uint32_t model_id;
+	uint32_t version;
+	uint16_t num_capture_types; /* number of image capture types */
+	uint16_t errors; /* see FP_ERROR_ flags above */
+} __ec_align4;
+BUILD_ASSERT(sizeof(struct fp_sensor_info) == 20);
+
+struct fp_template_info {
+	/* Template/finger current information */
+	uint32_t template_size; /* max template size in bytes */
+	uint16_t template_max; /* maximum number of fingers/templates */
+	uint16_t template_valid; /* number of valid fingers/templates */
+	uint32_t template_dirty; /* bitmap of templates with MCU side changes */
+	uint32_t template_version; /* version of the template format */
+} __ec_align4;
+BUILD_ASSERT(sizeof(struct fp_template_info) == 16);
+
+struct fp_image_frame_params {
+	/* Image frame characteristics */
+	uint32_t frame_size;
+	uint32_t pixel_format; /* using V4L2_PIX_FMT_ */
+	uint16_t width;
+	uint16_t height;
+	uint16_t bpp;
+	/** Type of image capture from enum fp_capture_type. */
+	uint8_t fp_capture_type;
+	uint8_t reserved; /**< padding for alignment */
+} __ec_align4;
+BUILD_ASSERT(sizeof(struct fp_image_frame_params) == 16);
+
+struct ec_response_fp_info_v2 {
+	/* Sensor identification */
+	struct fp_sensor_info sensor_info;
+	/* Template/finger current information */
+	struct fp_template_info template_info;
+	/* fingerprint image frame parameters */
+	struct fp_image_frame_params
+		image_frame_params[FLEXIBLE_ARRAY_MEMBER_SIZE];
+} __ec_align4;
+BUILD_ASSERT(sizeof(struct ec_response_fp_info_v2) == 36);
+
 /* Get the last captured finger frame or a template content */
 #define EC_CMD_FP_FRAME 0x0404
 
@@ -8205,7 +8534,7 @@ struct ec_params_fp_frame {
 struct ec_params_fp_template {
 	uint32_t offset;
 	uint32_t size;
-	uint8_t data[];
+	uint8_t data[FLEXIBLE_ARRAY_MEMBER_SIZE];
 } __ec_align4;
 
 /* Clear the current fingerprint user context and set a new one */
@@ -8260,16 +8589,12 @@ struct ec_params_fp_seed {
 
 /* FP TPM seed has been set or not */
 #define FP_ENC_STATUS_SEED_SET BIT(0)
-/* FP using nonce context or not */
-#define FP_CONTEXT_STATUS_NONCE_CONTEXT_SET BIT(1)
-/* FP match had been processed or not */
-#define FP_CONTEXT_STATUS_MATCH_PROCESSED_SET BIT(2)
-/* FP auth_nonce had been set or not*/
-#define FP_CONTEXT_AUTH_NONCE_SET BIT(3)
+/* Session was established or not */
+#define FP_CONTEXT_STATUS_SESSION_ESTABLISHED BIT(1)
+/* FP session_nonce had been set or not*/
+#define FP_CONTEXT_SESSION_NONCE_SET BIT(2)
 /* FP user_id had been set or not*/
-#define FP_CONTEXT_USER_ID_SET BIT(4)
-/* FP templates are unlocked for nonce context or not */
-#define FP_CONTEXT_TEMPLATE_UNLOCKED_SET BIT(5)
+#define FP_CONTEXT_USER_ID_SET BIT(3)
 
 struct ec_response_fp_encryption_status {
 	/* Used bits in encryption engine status */
@@ -8327,7 +8652,6 @@ struct fp_encrypted_private_key {
 
 struct ec_response_fp_establish_pairing_key_keygen {
 	struct fp_elliptic_curve_public_key pubkey;
-	struct fp_encrypted_private_key encrypted_private_key;
 } __ec_align4;
 
 #define FP_PAIRING_KEY_LEN 32
@@ -8341,7 +8665,6 @@ struct ec_fp_encrypted_pairing_key {
 
 struct ec_params_fp_establish_pairing_key_wrap {
 	struct fp_elliptic_curve_public_key peers_pubkey;
-	struct fp_encrypted_private_key encrypted_private_key;
 } __ec_align4;
 
 struct ec_response_fp_establish_pairing_key_wrap {
@@ -8353,62 +8676,21 @@ struct ec_response_fp_establish_pairing_key_wrap {
 typedef struct ec_response_fp_establish_pairing_key_wrap
 	ec_params_fp_load_pairing_key;
 
-#define FP_CK_AUTH_NONCE_LEN 32
+#define FP_CK_SESSION_NONCE_LEN 32
 
 #define EC_CMD_FP_GENERATE_NONCE 0x0413
 struct ec_response_fp_generate_nonce {
-	uint8_t nonce[FP_CK_AUTH_NONCE_LEN];
+	uint8_t nonce[FP_CK_SESSION_NONCE_LEN];
 } __ec_align4;
 
-#define FP_CONTEXT_USERID_LEN 32
-#define FP_CONTEXT_USERID_IV_LEN 16
-#define FP_CONTEXT_KEY_LEN 32
-
-#define EC_CMD_FP_NONCE_CONTEXT 0x0414
-struct ec_params_fp_nonce_context {
-	uint8_t gsc_nonce[FP_CK_AUTH_NONCE_LEN];
-	uint8_t enc_user_id[FP_CONTEXT_USERID_LEN];
-	uint8_t enc_user_id_iv[FP_CONTEXT_USERID_IV_LEN];
+#define EC_CMD_FP_ESTABLISH_SESSION 0x0414
+struct ec_params_fp_establish_session {
+	uint8_t peer_nonce[FP_CK_SESSION_NONCE_LEN];
+	uint8_t enc_tpm_seed[FP_CONTEXT_TPM_BYTES];
+	uint8_t nonce[FP_AES_KEY_NONCE_BYTES];
+	uint8_t tag[FP_AES_KEY_TAG_BYTES];
 } __ec_align4;
 
-#define FP_ELLIPTIC_CURVE_PUBLIC_KEY_IV_LEN 16
-
-#define EC_CMD_FP_READ_MATCH_SECRET_WITH_PUBKEY 0x0415
-
-struct ec_params_fp_read_match_secret_with_pubkey {
-	uint16_t fgr;
-	uint16_t reserved;
-	struct fp_elliptic_curve_public_key pubkey;
-} __ec_align4;
-
-struct ec_response_fp_read_match_secret_with_pubkey {
-	struct fp_elliptic_curve_public_key pubkey;
-	uint8_t iv[FP_ELLIPTIC_CURVE_PUBLIC_KEY_IV_LEN];
-	uint8_t enc_secret[FP_POSITIVE_MATCH_SECRET_BYTES];
-} __ec_align4;
-
-/* Unlock the fpsensor template with the current nonce context */
-#define EC_CMD_FP_UNLOCK_TEMPLATE 0x0417
-
-struct ec_params_fp_unlock_template {
-	uint16_t fgr_num;
-} __ec_align4;
-
-/*
- * Migrate a legacy FP template (here, legacy refers to being generated in a
- * raw user_id context instead of a nonce context) by wiping its match secret
- * salt and treating it as a newly-enrolled template.
- * The legacy FP template needs to be uploaded by FP_TEMPLATE command first
- * without committing, then this command will commit it.
- */
-#define EC_CMD_FP_MIGRATE_TEMPLATE_TO_NONCE_CONTEXT 0x0418
-
-struct ec_params_fp_migrate_template_to_nonce_context {
-	/* The context userid used to encrypt this template when it was created.
-	 */
-	uint32_t userid[FP_CONTEXT_USERID_WORDS];
-};
-
 /*****************************************************************************/
 /* Touchpad MCU commands: range 0x0500-0x05FF */
 
@@ -8420,7 +8702,7 @@ struct ec_params_fp_migrate_template_to_nonce_context {
 
 struct ec_response_tp_frame_info {
 	uint32_t n_frames;
-	uint32_t frame_sizes[0];
+	uint32_t frame_sizes[FLEXIBLE_ARRAY_MEMBER_SIZE];
 } __ec_align4;
 
 /* Create a snapshot of current frame readings */
@@ -8603,6 +8885,9 @@ struct ec_response_get_boot_time {
 	uint16_t cnt;
 } __ec_align4;
 
+/* Issue AP shutdown */
+#define EC_CMD_AP_SHUTDOWN 0x0605
+
 /*****************************************************************************/
 /*
  * Reserve a range of host commands for board-specific, experimental, or

From cd48dc7d69f2c257fb30f75742b6e27084947e49 Mon Sep 17 00:00:00 2001
From: David Wu <david_wu@quanta.corp-partner.google.com>
Date: Wed, 3 Sep 2025 08:44:35 +0800
Subject: [PATCH 1943/3886] mb/google/rex/var/karis: Add H58G66CK8BX147 to RAM
 ID table

Add the new memory support: Hynix H58G66CK8BX147

BUG=b:441882141
TEST=Run part_id_gen tool and check the generated files.

Change-Id: I5188192974409044e41ac169c3c45660f85b2b0b
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89017
Reviewed-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/google/rex/variants/karis/memory/Makefile.mk       | 1 +
 .../google/rex/variants/karis/memory/dram_id.generated.txt       | 1 +
 .../google/rex/variants/karis/memory/mem_parts_used.txt          | 1 +
 3 files changed, 3 insertions(+)

diff --git a/src/mainboard/google/rex/variants/karis/memory/Makefile.mk b/src/mainboard/google/rex/variants/karis/memory/Makefile.mk
index 210dbe5fd4..b56247ea44 100644
--- a/src/mainboard/google/rex/variants/karis/memory/Makefile.mk
+++ b/src/mainboard/google/rex/variants/karis/memory/Makefile.mk
@@ -7,3 +7,4 @@ SPD_SOURCES =
 SPD_SOURCES += spd/lp5/set-0/spd-11.hex      # ID = 0(0b0000)  Parts = MT62F1G32D2DS-023 WT:B, H58G56BK8BX068
 SPD_SOURCES += spd/lp5/set-0/spd-1.hex      # ID = 1(0b0001)  Parts = H9JCNNNBK3MLYR-N6E, MT62F512M32D2DR-031 WT:B
 SPD_SOURCES += spd/lp5/set-0/spd-7.hex      # ID = 2(0b0010)  Parts = K3KL8L80CM-MGCT
+SPD_SOURCES += spd/lp5/set-0/spd-10.hex      # ID = 3(0b0011)  Parts = H58G66CK8BX147
diff --git a/src/mainboard/google/rex/variants/karis/memory/dram_id.generated.txt b/src/mainboard/google/rex/variants/karis/memory/dram_id.generated.txt
index 95ab79273d..8a32e1fd77 100644
--- a/src/mainboard/google/rex/variants/karis/memory/dram_id.generated.txt
+++ b/src/mainboard/google/rex/variants/karis/memory/dram_id.generated.txt
@@ -9,3 +9,4 @@ H9JCNNNBK3MLYR-N6E             1 (0001)
 H58G56BK8BX068                 0 (0000)
 K3KL8L80CM-MGCT                2 (0010)
 MT62F512M32D2DR-031 WT:B       1 (0001)
+H58G66CK8BX147                 3 (0011)
diff --git a/src/mainboard/google/rex/variants/karis/memory/mem_parts_used.txt b/src/mainboard/google/rex/variants/karis/memory/mem_parts_used.txt
index 42d8a4ee05..217cd83e72 100644
--- a/src/mainboard/google/rex/variants/karis/memory/mem_parts_used.txt
+++ b/src/mainboard/google/rex/variants/karis/memory/mem_parts_used.txt
@@ -14,3 +14,4 @@ H9JCNNNBK3MLYR-N6E
 H58G56BK8BX068
 K3KL8L80CM-MGCT
 MT62F512M32D2DR-031 WT:B
+H58G66CK8BX147

From 97dbfd3098ae12ef3f51e5f95cd6d66c25214205 Mon Sep 17 00:00:00 2001
From: Patrick Rudolph <patrick.rudolph@9elements.com>
Date: Wed, 13 Aug 2025 15:37:41 +0200
Subject: [PATCH 1944/3886] cpu/intel/car/non-evict: Improve CAR setup
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

On older CPUs lacking ESRM (Enhanced Short Rep Mov) the rep stos
instructions are very slow. Since the MTRR that covers the SPI ROM
is disabled when setting up the NEM, the CPU will run with cache
disabled and is even slower.

The Sandy Bridge BWG and the Sandy Bridge UEFI reference code do not
disable the MTRR on the XiP, allowing the CPU to run at full speed
when setting up CAR. On UEFI the CAR is set up by touching each
cache-line once. It doesn't clear the CAR while doing so.

Do the same to speed up setting CAR:
- Invalidate the cache
- Enable the SPI ROM XiP MTRR
- Set CR0.CD=0
- Touch one spot in each cache-line
- Clear CAR after NEM has been set up

To ensure that the CAR MTRR area is 64-byte aligned add an ALIGN to
the linker script. All existing boards should use a 64-byte alignment
for CAR.

TEST=Booted on Lenovo X220 and measured with cbmem -t:

TODO: Test on platforms that have FSRM (Ivy Bridge and newer).

Before:
   0:1st timestamp                                     1,083 (0)
  11:start of bootblock                                93,765 (92,681)

After:
   0:1st timestamp                                     0
  11:start of bootblock                                24,027

Boots 69msec faster than before or about 4 times faster.

Change-Id: Ia8baef28fd736ef6bb02d8a100d752ac0392e1cf
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88792
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
---
 src/arch/x86/car.ld                        |  1 +
 src/cpu/intel/car/non-evict/cache_as_ram.S | 71 ++++++++++++----------
 2 files changed, 39 insertions(+), 33 deletions(-)

diff --git a/src/arch/x86/car.ld b/src/arch/x86/car.ld
index 9d54037b7a..bbfd682934 100644
--- a/src/arch/x86/car.ld
+++ b/src/arch/x86/car.ld
@@ -122,6 +122,7 @@ _car_region_end = . + CONFIG_DCACHE_RAM_SIZE - (. - _car_region_start)
 }
 
 #if ENV_BOOTBLOCK
+. = ALIGN(64);
 _car_mtrr_end = .;
 _car_mtrr_start = _car_region_start;
 
diff --git a/src/cpu/intel/car/non-evict/cache_as_ram.S b/src/cpu/intel/car/non-evict/cache_as_ram.S
index 7186422595..91035dabb4 100644
--- a/src/cpu/intel/car/non-evict/cache_as_ram.S
+++ b/src/cpu/intel/car/non-evict/cache_as_ram.S
@@ -151,21 +151,16 @@ update_microcode:
 	jmp	update_bsp_microcode
 end_microcode_update:
 #endif
-	/* Disable caching to change MTRR's. */
+
+	/* Disable caching. */
 	movl	%cr0, %eax
 	orl	$CR0_CacheDisable, %eax
 	movl	%eax, %cr0
 
-	/* Clear the mask valid to disable the MTRR */
-	movl	$MTRR_PHYS_MASK(1), %ecx
-	rdmsr
-	andl	$(~MTRR_PHYS_MASK_VALID), %eax
-	wrmsr
-
-	/* Enable cache. */
-	movl	%cr0, %eax
-	andl	$(~(CR0_CacheDisable | CR0_NoWriteThrough)), %eax
 	invd
+
+	/* Enable caching */
+	andl	$(~(CR0_CacheDisable | CR0_NoWriteThrough)), %eax
 	movl	%eax, %cr0
 
 	/* enable the 'no eviction' mode */
@@ -175,36 +170,46 @@ end_microcode_update:
 	andl	$~2, %eax
 	wrmsr
 
-	/* Clear the cache memory region. This will also fill up the cache. */
-	cld
-	xorl	%eax, %eax
+	/* Fill up the cache next. */
 	movl	$_car_mtrr_start, %edi
-	movl	$_car_mtrr_size, %ecx
-	shr	$2, %ecx
-	rep	stosl
 
-	/* enable the 'no eviction run' state */
+	/* Number of loops. */
+	movl	$_car_mtrr_size, %ecx
+	shr	$6, %ecx
+	xorl	%ebx, %ebx
+	mov	$64, %bl
+
+1:
+	/*
+	 * BWG: *One* location in each 64-byte cache line must be written
+	 * to set all cached values to modified state.
+	 *
+	 * Value of %eax doesn't matter here. CAR is zeroed later.
+	 *
+	 * Zeroing the whole cache here *not* work when CR0.CD = 0.
+	 * Zeroing the whole cache here *does* work when CR0.CD = 1,
+	 * but will be a couple of times slower (4 times on Sandy Bridge).
+	 */
+	movl	%eax, (%edi)
+	addl	%ebx, %edi
+
+	loop	1b
+
+	/* enable the 'no eviction run' state. */
 	movl	$NoEvictMod_MSR, %ecx
 	rdmsr
-	orl	$3, %eax
-	wrmsr
-
-	post_code(POSTCODE_SOC_DISABLE_CACHE)
-	/* Enable Cache-as-RAM mode by disabling cache. */
-	movl	%cr0, %eax
-	orl	$CR0_CacheDisable, %eax
-	movl	%eax, %cr0
-
-	movl	$MTRR_PHYS_MASK(1), %ecx
-	rdmsr
-	orl	$MTRR_PHYS_MASK_VALID, %eax
+	or	$3, %al
 	wrmsr
 
 	post_code(POSTCODE_SOC_ENABLE_CACHE)
-	/* Enable cache. */
-	movl	%cr0, %eax
-	andl	$(~(CR0_CacheDisable | CR0_NoWriteThrough)), %eax
-	movl	%eax, %cr0
+
+	/* Now that CAR is enabled clear it. */
+	movl	$_car_mtrr_start, %edi
+	movl	$_car_mtrr_size, %ecx
+	cld
+	xorl	%eax, %eax
+	shr	$2, %ecx
+	rep	stosl
 
 	/* Setup the stack. */
 	mov	$_ecar_stack, %esp

From afaef0b904057aa848f50f55a7b8ae0b8ebb38d2 Mon Sep 17 00:00:00 2001
From: Appukuttan V K <appukuttan.vk@intel.com>
Date: Thu, 21 Aug 2025 12:14:16 +0530
Subject: [PATCH 1945/3886] mainboard/google/ocelot: Update GPIO configuration
 for SLP_S0_GATE

This commit updates the GPIO configuration for the Ocelot baseboard
variant. It changes the definition of `GPIO_SLP_S0_GATE` from
being not connected (0) to `GPP_C08`. This GPIO will be used as
an indicator for the EC.

References:
  - Schematic version: schematic_1433518

BUG=b:440270606
TEST=Perform an S0ix sequence on the system and verify that the
power state is properly reported on the EC console.

Change-Id: I303322f233824e6980ff6078e62f66eba36203ed
Signed-off-by: Appukuttan V K <appukuttan.vk@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88875
Reviewed-by: Pranava Y N <pranavayn@google.com>
Reviewed-by: Sowmya Aralguppe <sowmya.aralguppe@intel.com>
Reviewed-by: sridhar siricilla <siricillasridhar@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Krishna P Bhat D <krishna.p.bhat.d@intel.com>
Reviewed-by: Usha P <usha.p@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 .../ocelot/variants/baseboard/ocelot/include/baseboard/gpio.h   | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/mainboard/google/ocelot/variants/baseboard/ocelot/include/baseboard/gpio.h b/src/mainboard/google/ocelot/variants/baseboard/ocelot/include/baseboard/gpio.h
index ddc771eed8..cf5924634d 100644
--- a/src/mainboard/google/ocelot/variants/baseboard/ocelot/include/baseboard/gpio.h
+++ b/src/mainboard/google/ocelot/variants/baseboard/ocelot/include/baseboard/gpio.h
@@ -17,6 +17,6 @@
  #define EC_SYNC_IRQ	0 /* Not Connected */
 #endif
 #define GPIO_PCH_WP	GPP_D02
-#define GPIO_SLP_S0_GATE	0 /* Not Connected */
+#define GPIO_SLP_S0_GATE	GPP_C08
 
 #endif /* __BASEBOARD_GPIO_H__ */

From 8c717df03a4a21b2cad77f15255759382c7319b6 Mon Sep 17 00:00:00 2001
From: Appukuttan V K <appukuttan.vk@intel.com>
Date: Thu, 28 Aug 2025 12:31:06 +0530
Subject: [PATCH 1946/3886] soc/intel/ptl: Update Wildcat Lake PCIe root port
 numbering
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

This commit updates the PCIe root port numbering for Wildcat Lake
as per the revised EDS document. This update ensures alignment with
the PCIe root port architecture.

Current:
- Bus-Device-Function: 0h – 6h – 0h = Root Port 5
- Bus-Device-Function: 0h – 6h – 1h = Root Port 6
New:
- Bus-Device-Function: 0h – 6h – 0h = Root Port 9
- Bus-Device-Function: 0h – 6h – 1h = Root Port 10

This resolves the warning shown during PCIe enumeration in boot
logs.

References:
- Wildcat Lake Platform Message of the Week (#844458)
- Wildcat Lake Processor EDS Volume 1 (#842271)
- Wildcat Lake External Design Specification (EDS) Volume 2 (#829345)

BUG=b:433687705
TEST=Boot the system with the updated firmware and verify that
below warning is not reported for the PCIe root ports:
"[WARN ]  pcie_rp_original_idx: Unexpected root-port number '9' at
PCI: 00:06.0, ignoring."

Change-Id: Icf5e3ae3d008f8d79480959bef7b4768fb34b4a8
Signed-off-by: Appukuttan V K <appukuttan.vk@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88980
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Pranava Y N <pranavayn@google.com>
Reviewed-by: Usha P <usha.p@intel.com>
---
 src/soc/intel/pantherlake/pcie_rp.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/src/soc/intel/pantherlake/pcie_rp.c b/src/soc/intel/pantherlake/pcie_rp.c
index cacbab83ad..35702391e2 100644
--- a/src/soc/intel/pantherlake/pcie_rp.c
+++ b/src/soc/intel/pantherlake/pcie_rp.c
@@ -25,6 +25,8 @@ static const struct pcie_rp_group ptl_rp_groups[] = {
 #endif
 #if CONFIG(SOC_INTEL_PANTHERLAKE_U_H)
 	{ .slot = PCI_DEV_SLOT_PCIE_2,	.count = 4, .lcap_port_base = 1 },
+#elif CONFIG(SOC_INTEL_WILDCATLAKE)
+	{ .slot = PCI_DEV_SLOT_PCIE_2, .count = 2, .lcap_port_base = 5 },
 #else
 	{ .slot = PCI_DEV_SLOT_PCIE_2, .count = 2, .lcap_port_base = 1 },
 #endif

From c73f30e74b5ee2942dc1c544e02c24379d1ea1ca Mon Sep 17 00:00:00 2001
From: David Wu <david_wu@quanta.corp-partner.google.com>
Date: Tue, 2 Sep 2025 09:47:08 +0800
Subject: [PATCH 1947/3886] mb/google/nissa/var/riven: Add H58G56CK8BX146 to
 RAM ID table

Add the new memory support: Hynix H58G56CK8BX146

BUG=b:442335706
BRANCH=firmware-nissa-15217.B
TEST=Run part_id_gen tool and check the generated files.

Change-Id: I8002c2c8e89882f4a705c7aae881544009f84e3b
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89013
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
---
 src/mainboard/google/brya/variants/riven/memory/Makefile.mk     | 2 +-
 .../google/brya/variants/riven/memory/dram_id.generated.txt     | 1 +
 .../google/brya/variants/riven/memory/mem_parts_used.txt        | 1 +
 3 files changed, 3 insertions(+), 1 deletion(-)

diff --git a/src/mainboard/google/brya/variants/riven/memory/Makefile.mk b/src/mainboard/google/brya/variants/riven/memory/Makefile.mk
index ecca8b52ff..47474d7f79 100644
--- a/src/mainboard/google/brya/variants/riven/memory/Makefile.mk
+++ b/src/mainboard/google/brya/variants/riven/memory/Makefile.mk
@@ -9,4 +9,4 @@ SPD_SOURCES += spd/lp5/set-0/spd-1.hex      # ID = 1(0b0001)  Parts = MT62F512M3
 SPD_SOURCES += spd/lp5/set-0/spd-5.hex      # ID = 2(0b0010)  Parts = K3LKLKL0EM-MGCN
 SPD_SOURCES += spd/lp5/set-0/spd-3.hex      # ID = 3(0b0011)  Parts = K3LKBKB0BM-MGCP
 SPD_SOURCES += spd/lp5/set-0/spd-7.hex      # ID = 4(0b0100)  Parts = K3KL8L80CM-MGCT
-SPD_SOURCES += spd/lp5/set-0/spd-11.hex      # ID = 5(0b0101)  Parts = H58G56BK8BX068
+SPD_SOURCES += spd/lp5/set-0/spd-11.hex      # ID = 5(0b0101)  Parts = H58G56BK8BX068, H58G56CK8BX146
diff --git a/src/mainboard/google/brya/variants/riven/memory/dram_id.generated.txt b/src/mainboard/google/brya/variants/riven/memory/dram_id.generated.txt
index 7f8976c97a..0832ee921f 100644
--- a/src/mainboard/google/brya/variants/riven/memory/dram_id.generated.txt
+++ b/src/mainboard/google/brya/variants/riven/memory/dram_id.generated.txt
@@ -12,3 +12,4 @@ K3LKBKB0BM-MGCP                3 (0011)
 H9JCNNNCP3MLYR-N6E             0 (0000)
 K3KL8L80CM-MGCT                4 (0100)
 H58G56BK8BX068                 5 (0101)
+H58G56CK8BX146                 5 (0101)
diff --git a/src/mainboard/google/brya/variants/riven/memory/mem_parts_used.txt b/src/mainboard/google/brya/variants/riven/memory/mem_parts_used.txt
index 2c18a19d34..96ddbf738d 100644
--- a/src/mainboard/google/brya/variants/riven/memory/mem_parts_used.txt
+++ b/src/mainboard/google/brya/variants/riven/memory/mem_parts_used.txt
@@ -17,3 +17,4 @@ K3LKBKB0BM-MGCP
 H9JCNNNCP3MLYR-N6E
 K3KL8L80CM-MGCT
 H58G56BK8BX068
+H58G56CK8BX146

From a45c8441af2aad933210d7ca1da78cff45743549 Mon Sep 17 00:00:00 2001
From: Subrata Banik <subratabanik@google.com>
Date: Tue, 2 Sep 2025 12:14:21 +0000
Subject: [PATCH 1948/3886] lib: Add boot mode information to coreboot tables

This change introduces `LB_TAG_BOOT_MODE` to the coreboot tables to
convey platform boot information to the payload. The new `lb_boot_mode`
struct uses `enum boot_mode_t` to specify whether the device is booting
in `normal mode`, `low-battery mode` or `off-mode charging`.

This is crucial for platforms where the Application Processor (AP)
manages the charging solution, as it provides the necessary context for
the payload's charger driver. By passing this data through the coreboot
table, we avoid redundant implementation and ensure consistent battery
and charging information is available across both coreboot and the
payload.

A new weak function, `lb_add_boot_mode`, is also introduced. This
function can be overridden by platforms that require this data to add
the boot mode information to the coreboot table.

TEST=Able to build and boot google/quenbi.

Change-Id: I5aea72c02b4d6c856e2504f4007de584c59ee89f
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88992
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
---
 .../include/commonlib/coreboot_tables.h       | 19 +++++++++++++++++++
 src/include/boot/coreboot_tables.h            |  3 +++
 src/lib/coreboot_table.c                      |  9 +++++++++
 3 files changed, 31 insertions(+)

diff --git a/src/commonlib/include/commonlib/coreboot_tables.h b/src/commonlib/include/commonlib/coreboot_tables.h
index fefafb87e1..ab57ed0270 100644
--- a/src/commonlib/include/commonlib/coreboot_tables.h
+++ b/src/commonlib/include/commonlib/coreboot_tables.h
@@ -96,6 +96,7 @@ enum {
 	LB_TAG_OPTION_ENUM		= 0x00ca,
 	LB_TAG_OPTION_DEFAULTS		= 0x00cb,
 	LB_TAG_OPTION_CHECKSUM		= 0x00cc,
+	LB_TAG_BOOT_MODE		= 0x00cd,
 };
 
 /* All table entry base addresses and sizes must be 4-byte aligned. */
@@ -621,4 +622,22 @@ struct lb_cfr {
 	/* struct lb_cfr_option_form		forms[] */
 };
 
+enum boot_mode_t {
+	LB_BOOT_MODE_NORMAL,
+	LB_BOOT_MODE_LOW_BATTERY,
+	LB_BOOT_MODE_OFFMODE_CHARGING,
+};
+
+/*
+ * Boot Mode: Pass the platform boot mode information to payload about
+ * booting in low-battery mode or off-mode charging. These information
+ * is useful for payload to implement charger driver.
+ */
+struct lb_boot_mode {
+	uint32_t tag;
+	uint32_t size;
+
+	enum boot_mode_t boot_mode;
+};
+
 #endif
diff --git a/src/include/boot/coreboot_tables.h b/src/include/boot/coreboot_tables.h
index 9c258c687e..be737b0bb9 100644
--- a/src/include/boot/coreboot_tables.h
+++ b/src/include/boot/coreboot_tables.h
@@ -53,6 +53,9 @@ struct lb_record *lb_new_record(struct lb_header *header);
 /* Add VBOOT VBNV offsets. */
 void lb_table_add_vbnv_cmos(struct lb_header *header);
 
+/* Add Boot Mode information */
+void lb_add_boot_mode(struct lb_header *header);
+
 /* Define this in mainboard.c to add board specific CFR entries */
 void mb_cfr_setup_menu(struct lb_cfr *cfr_root);
 
diff --git a/src/lib/coreboot_table.c b/src/lib/coreboot_table.c
index 3902c88eff..d8ecdce868 100644
--- a/src/lib/coreboot_table.c
+++ b/src/lib/coreboot_table.c
@@ -464,6 +464,13 @@ static void lb_add_acpi_rsdp(struct lb_header *head)
 	acpi_rsdp->rsdp_pointer = get_coreboot_rsdp();
 }
 
+/*
+ * Not all platform would need to fill in the boot mode information.
+ * This is useful for platform that would like to implement battery
+ * charging solution in AP firmware.
+ */
+void __weak lb_add_boot_mode(struct lb_header *header) { /* NOOP */ }
+
 size_t write_coreboot_forwarding_table(uintptr_t entry, uintptr_t target)
 {
 	struct lb_header *head;
@@ -585,6 +592,8 @@ static uintptr_t write_coreboot_table(uintptr_t rom_table_end)
 	if (CONFIG(HAVE_ACPI_TABLES))
 		lb_add_acpi_rsdp(head);
 
+	lb_add_boot_mode(head);
+
 	/* Remember where my valid memory ranges are */
 	return lb_table_fini(head);
 }

From 893a2b008a0f2c5f2dc43cbcedcb6cb5afb7dcad Mon Sep 17 00:00:00 2001
From: Subrata Banik <subratabanik@google.com>
Date: Tue, 2 Sep 2025 12:16:50 +0000
Subject: [PATCH 1949/3886] libpayload: Add coreboot boot mode table

This commit adds a new coreboot table, CB_TAG_BOOT_MODE, to pass
platform boot mode information to the payload.

The new table defines flags for low-battery mode and off-mode charging,
which are essential for a payload to properly initialize the charger
driver.

The cb_parse_boot_mode function is added to read this information, and
the sysinfo_t structure is updated to store the parsed boot mode data.

This ensures that the payload can accurately determine the system's
power state at boot and payload operations are also in sync with the
boot firmware.

The following scenarios were tested and verified:

Scenario 1: Low-battery, no charger
 - coreboot detects the low-battery state and performs an immediate
   shutdown after displaying the low-battery splash screen.

Scenario 2: Low-battery, charger attached
 - coreboot detects the low-battery state but continues booting because
   a charger is present. The payload receives the low-battery
   information (using the same source as coreboot) and correctly
   initiates the charging process.

Scenario 3: Off-mode charging
 - The system boots directly from an S5 state due to a charger being
   plugged in. coreboot detects the off-mode state, skips the firmware
   splash screen, and hands off control to the payload, which then
   starts charging.

Scenario 4: Normal boot
 - The system boots without any low-battery or off-mode conditions.
   coreboot and the payload both detect a normal boot (using the same
   information), bypass charging initialization, and proceed to boot the
   operating system.

TEST=Able to build and boot on google/quenbi device and verify the boot
mode flag is correctly passed.

Change-Id: Iec25c6fdfcdc5ea7c397d2430ac7b545e1e068f2
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89015
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 payloads/libpayload/include/coreboot_tables.h | 18 ++++++++++++++++++
 payloads/libpayload/include/sysinfo.h         |  1 +
 payloads/libpayload/libc/coreboot.c           | 10 ++++++++++
 3 files changed, 29 insertions(+)

diff --git a/payloads/libpayload/include/coreboot_tables.h b/payloads/libpayload/include/coreboot_tables.h
index b43a558b49..04d205c053 100644
--- a/payloads/libpayload/include/coreboot_tables.h
+++ b/payloads/libpayload/include/coreboot_tables.h
@@ -90,6 +90,7 @@ enum {
 	CB_TAG_OPTION_ENUM		= 0x00ca,
 	CB_TAG_OPTION_DEFAULTS		= 0x00cb,
 	CB_TAG_OPTION_CHECKSUM		= 0x00cc,
+	CB_TAG_BOOT_MODE		= 0x00cd,
 };
 
 typedef __aligned(4) uint64_t cb_uint64_t;
@@ -443,6 +444,23 @@ struct cb_acpi_rsdp {
 	cb_uint64_t rsdp_pointer; /* Address of the ACPI RSDP */
 };
 
+enum boot_mode_t {
+	CB_BOOT_MODE_NORMAL,
+	CB_BOOT_MODE_LOW_BATTERY,
+	CB_BOOT_MODE_OFFMODE_CHARGING,
+};
+
+/*
+ * Boot Mode: Pass the platform boot mode information to payload about
+ * booting in low-battery mode or off-mode charging. These information
+ * is useful for payload to implement charger driver.
+ */
+struct cb_boot_mode {
+	uint32_t tag;
+	uint32_t size;
+
+	enum boot_mode_t boot_mode;
+};
 
 /* Helpful inlines */
 
diff --git a/payloads/libpayload/include/sysinfo.h b/payloads/libpayload/include/sysinfo.h
index 2db306eba9..7c47074aa1 100644
--- a/payloads/libpayload/include/sysinfo.h
+++ b/payloads/libpayload/include/sysinfo.h
@@ -173,6 +173,7 @@ struct sysinfo_t {
 	/* pvmfw buffer location */
 	uintptr_t pvmfw;
 	uint32_t pvmfw_size;
+	enum boot_mode_t boot_mode;
 };
 
 extern struct sysinfo_t lib_sysinfo;
diff --git a/payloads/libpayload/libc/coreboot.c b/payloads/libpayload/libc/coreboot.c
index 2788f870be..11703ee178 100644
--- a/payloads/libpayload/libc/coreboot.c
+++ b/payloads/libpayload/libc/coreboot.c
@@ -285,6 +285,13 @@ static void cb_parse_pcie(void *ptr, struct sysinfo_t *info)
 	info->pcie_ctrl_base = pcie->ctrl_base;
 }
 
+static void cb_parse_boot_mode(void *ptr, struct sysinfo_t *info)
+{
+	const struct cb_boot_mode *mode = ptr;
+
+	info->boot_mode = mode->boot_mode;
+}
+
 static void cb_parse_rsdp(void *ptr, struct sysinfo_t *info)
 {
 	const struct cb_acpi_rsdp *cb_acpi_rsdp = ptr;
@@ -437,6 +444,9 @@ int cb_parse_header(void *addr, int len, struct sysinfo_t *info)
 		case CB_TAG_PCIE:
 			cb_parse_pcie(ptr, info);
 			break;
+		case CB_TAG_BOOT_MODE:
+			cb_parse_boot_mode(ptr, info);
+			break;
 		default:
 			cb_parse_arch_specific(rec, info);
 			break;

From e82338b0a2173c6a72b6ff4496b746df3da8c872 Mon Sep 17 00:00:00 2001
From: Subrata Banik <subratabanik@google.com>
Date: Tue, 2 Sep 2025 12:15:04 +0000
Subject: [PATCH 1950/3886] mb/google/bluey: Add boot mode to coreboot tables

This change implements `lb_add_boot_mode` for the `bluey` mainboard,
which adds the platform's boot mode information to the coreboot tables.

This is done by checking the EC (Embedded Controller) to determine if
the battery is below a critical threshold.

If the battery is critically low, the `LB_BOOT_MODE_LOW_BATTERY` flag
is set. This information is then passed to the payload, allowing it to
take specific actions, such as displaying a low-battery charging
screen.

TEST=Able to build and boot the `bluey` mainboard.

Change-Id: I473cec7645954e753e160467aa8b83b67b28ab76
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88994
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/google/bluey/mainboard.c | 18 ++++++++++++++++++
 1 file changed, 18 insertions(+)

diff --git a/src/mainboard/google/bluey/mainboard.c b/src/mainboard/google/bluey/mainboard.c
index 1ff845c541..6d2f705a41 100644
--- a/src/mainboard/google/bluey/mainboard.c
+++ b/src/mainboard/google/bluey/mainboard.c
@@ -1,14 +1,32 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
+#include <boot/coreboot_tables.h>
 #include <bootmode.h>
 #include <console/console.h>
 #include <device/device.h>
+#include <ec/google/chromeec/ec.h>
 #include <gpio.h>
 #include <soc/pcie.h>
 #include <soc/qupv3_config_common.h>
 #include <soc/qup_se_handlers_common.h>
 #include "board.h"
 
+void lb_add_boot_mode(struct lb_header *header)
+{
+	if (!CONFIG(EC_GOOGLE_CHROMEEC))
+		return;
+
+	struct lb_boot_mode *mode = (struct lb_boot_mode *)lb_new_record(header);
+	memset(mode, 0, sizeof(*mode));
+
+	mode->tag = LB_TAG_BOOT_MODE;
+	mode->size = sizeof(*mode);
+	mode->boot_mode = LB_BOOT_MODE_NORMAL;
+
+	if (google_chromeec_is_below_critical_threshold())
+		mode->boot_mode = LB_BOOT_MODE_LOW_BATTERY;
+}
+
 bool mainboard_needs_pcie_init(void)
 {
 	return true;

From 29ca9c8bfa4a5178765d9f69589bffac1a7449ab Mon Sep 17 00:00:00 2001
From: Subrata Banik <subratabanik@google.com>
Date: Wed, 3 Sep 2025 11:09:12 +0530
Subject: [PATCH 1951/3886] mb/google/bluey: Disable charging during normal
 boot

This commit adds a call to disable_slow_battery_charging() in the
lb_add_boot_mode function.

The logic ensures that charging is disabled if the system is booting in
a normal mode, where neither the LB_BOOT_MODE_LOW_BATTERY nor
LB_BOOT_MODE_OFFMODE_CHARGING flags are set.

This prevents unintended charging by the AP firmware when the device
is not in a low-battery state or booting from off-mode charging to
avoid battery unmanaged health related problem.

TEST=Able to build and boot google/quenbi.

Change-Id: I648dc72a35ad2773f803792248fa87351333828f
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89023
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/google/bluey/mainboard.c | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/src/mainboard/google/bluey/mainboard.c b/src/mainboard/google/bluey/mainboard.c
index 6d2f705a41..58035a3290 100644
--- a/src/mainboard/google/bluey/mainboard.c
+++ b/src/mainboard/google/bluey/mainboard.c
@@ -25,6 +25,10 @@ void lb_add_boot_mode(struct lb_header *header)
 
 	if (google_chromeec_is_below_critical_threshold())
 		mode->boot_mode = LB_BOOT_MODE_LOW_BATTERY;
+
+	/* Booting into normal mode hence disable charging */
+	if (mode->boot_mode == LB_BOOT_MODE_NORMAL)
+		disable_slow_battery_charging();
 }
 
 bool mainboard_needs_pcie_init(void)

From b748a5e10b56f0b9feac8f6fda44a0d5d8b524be Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Thu, 4 Sep 2025 21:09:25 +0100
Subject: [PATCH 1952/3886] mb/starlabs/{starbook,starfighter}/rpl: Disable
 GPIO override

The Raptor Lake FSP doesn't seem to honour not touching GPIOs, so set
this to avoid major issues such as the SSD not being recognised and
causing an indefinite hang.

Change-Id: I50edc788c7a4c6ee5a2d74aa76b9e33fb56ed15e
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89052
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
---
 src/mainboard/starlabs/starbook/variants/rpl/romstage.c    | 1 +
 src/mainboard/starlabs/starfighter/variants/rpl/romstage.c | 1 +
 2 files changed, 2 insertions(+)

diff --git a/src/mainboard/starlabs/starbook/variants/rpl/romstage.c b/src/mainboard/starlabs/starbook/variants/rpl/romstage.c
index 20d518c5c3..5038a526b7 100644
--- a/src/mainboard/starlabs/starbook/variants/rpl/romstage.c
+++ b/src/mainboard/starlabs/starbook/variants/rpl/romstage.c
@@ -46,4 +46,5 @@ void mainboard_memory_init_params(FSPM_UPD *mupd)
 	}
 
 	mupd->FspmConfig.DmiMaxLinkSpeed = 4;
+	mupd->FspmConfig.GpioOverride = 0;
 };
diff --git a/src/mainboard/starlabs/starfighter/variants/rpl/romstage.c b/src/mainboard/starlabs/starfighter/variants/rpl/romstage.c
index f6d872533f..785a8d135b 100644
--- a/src/mainboard/starlabs/starfighter/variants/rpl/romstage.c
+++ b/src/mainboard/starlabs/starfighter/variants/rpl/romstage.c
@@ -140,4 +140,5 @@ void mainboard_memory_init_params(FSPM_UPD *mupd)
 	}
 
 	mupd->FspmConfig.DmiMaxLinkSpeed = 4;
+	mupd->FspmConfig.GpioOverride = 0;
 };

From 6f11c313546810989a950a0cc15f75ec11a46a69 Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Thu, 4 Sep 2025 10:55:45 -0500
Subject: [PATCH 1953/3886] mb/starlabs/starbook/mtl: Update HDA verb table

Remove presence detection flag for the DMIC and internal speakers.
Update the subsystem ID to match that used by the AMI UEFI Firmware.
While we're at it, fix the (non-functional) descriptive flags for
those two verbs as well. Remove unnecessary line continuations.

TEST=build/boot Win11 and Linux on Starbook MTL, verify speaker and
intermal mic working, as well as headphones/jack mic when plugged in.

Change-Id: I7621a6b57fb525892e84d06470eab5a9bdd32065
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89042
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 .../starbook/variants/mtl/devicetree.cb       |  2 +-
 .../starlabs/starbook/variants/mtl/hda_verb.c | 76 +++++++++----------
 2 files changed, 39 insertions(+), 39 deletions(-)

diff --git a/src/mainboard/starlabs/starbook/variants/mtl/devicetree.cb b/src/mainboard/starlabs/starbook/variants/mtl/devicetree.cb
index dbb7dca439..2865a3d4b1 100644
--- a/src/mainboard/starlabs/starbook/variants/mtl/devicetree.cb
+++ b/src/mainboard/starlabs/starbook/variants/mtl/devicetree.cb
@@ -280,7 +280,7 @@ chip soc/intel/meteorlake
 			end
 		end
 		device ref hda		on
-			subsystemid 0x1e50 0x7038
+			subsystemid 0x1025 0x174e
 			register "pch_hda_sdi_enable[0]"		= "true"
 			register "pch_hda_dsp_enable"			= "true"
 			register "pch_hda_audio_link_hda_enable"	= "true"
diff --git a/src/mainboard/starlabs/starbook/variants/mtl/hda_verb.c b/src/mainboard/starlabs/starbook/variants/mtl/hda_verb.c
index 89de21c1d4..eb16aaf3e9 100644
--- a/src/mainboard/starlabs/starbook/variants/mtl/hda_verb.c
+++ b/src/mainboard/starlabs/starbook/variants/mtl/hda_verb.c
@@ -17,57 +17,57 @@
 const u32 cim_verb_data[] = {
 	/* coreboot specific header */
 	0x10ec0269,	/* Codec Vendor / Device ID: Realtek ALC269 */
-	0x1e507038,	/* Subsystem ID */
+	0x1025174e,	/* Subsystem ID */
 	18,		/* Number of verb entries */
 
 	/* Reset Codec First */
 	AZALIA_RESET(0x1),
 
 	/* HDA Codec Subsystem ID */
-	AZALIA_SUBVENDOR(0, 0x1e507038),
+	AZALIA_SUBVENDOR(0, 0x1025174e),
 
 	AZALIA_PIN_CFG(0, 0x01,		0x00000000),
-	AZALIA_PIN_CFG(0, DMIC,		AZALIA_PIN_DESC(					\
-						AZALIA_INTEGRATED,				\
-						AZALIA_INTERNAL | AZALIA_TOP,			\
-						AZALIA_MIC_IN,					\
-						AZALIA_TYPE_UNKNOWN,				\
-						AZALIA_BLACK,					\
-						AZALIA_JACK_PRESENCE_DETECT,			\
-						3,						\
-						0						\
+	AZALIA_PIN_CFG(0, DMIC,		AZALIA_PIN_DESC(
+						AZALIA_INTEGRATED,
+						AZALIA_MOBILE_LID_INSIDE,
+						AZALIA_MIC_IN,
+						AZALIA_OTHER_DIGITAL,
+						AZALIA_COLOR_UNKNOWN,
+						AZALIA_NO_JACK_PRESENCE_DETECT,
+						3,
+						0
 					)),
 
-	AZALIA_PIN_CFG(0, SPEAKERS,	AZALIA_PIN_DESC(					\
-						AZALIA_INTEGRATED,				\
-						AZALIA_INTERNAL | AZALIA_FRONT,			\
-						AZALIA_SPEAKER,					\
-						AZALIA_TYPE_UNKNOWN,				\
-						AZALIA_BLACK,					\
-						AZALIA_JACK_PRESENCE_DETECT,			\
-						1,						\
-						0						\
+	AZALIA_PIN_CFG(0, SPEAKERS,	AZALIA_PIN_DESC(
+						AZALIA_INTEGRATED,
+						AZALIA_INTERNAL | AZALIA_TOP,
+						AZALIA_SPEAKER,
+						AZALIA_OTHER_ANALOG,
+						AZALIA_COLOR_UNKNOWN,
+						AZALIA_NO_JACK_PRESENCE_DETECT,
+						1,
+						0
 					)),
-	AZALIA_PIN_CFG(0, HEADPHONE,	AZALIA_PIN_DESC(					\
-						AZALIA_JACK,					\
-						AZALIA_EXTERNAL_PRIMARY_CHASSIS | AZALIA_RIGHT,	\
-						AZALIA_HP_OUT,					\
-						AZALIA_STEREO_MONO_1_8,				\
-						AZALIA_BLACK,					\
-						AZALIA_JACK_PRESENCE_DETECT,			\
-						2,						\
-						0						\
+	AZALIA_PIN_CFG(0, HEADPHONE,	AZALIA_PIN_DESC(
+						AZALIA_JACK,
+						AZALIA_EXTERNAL_PRIMARY_CHASSIS | AZALIA_RIGHT,
+						AZALIA_HP_OUT,
+						AZALIA_STEREO_MONO_1_8,
+						AZALIA_BLACK,
+						AZALIA_JACK_PRESENCE_DETECT,
+						2,
+						0
 					)),
 	AZALIA_PIN_CFG(0, MONO,		AZALIA_PIN_CFG_NC(0)),
-	AZALIA_PIN_CFG(0, MIC1,		AZALIA_PIN_DESC(					\
-						AZALIA_JACK,					\
-						AZALIA_EXTERNAL_PRIMARY_CHASSIS | AZALIA_RIGHT,	\
-						AZALIA_MIC_IN,					\
-						AZALIA_STEREO_MONO_1_8,				\
-						AZALIA_BLACK,					\
-						AZALIA_JACK_PRESENCE_DETECT,			\
-						4,						\
-						0						\
+	AZALIA_PIN_CFG(0, MIC1,		AZALIA_PIN_DESC(
+						AZALIA_JACK,
+						AZALIA_EXTERNAL_PRIMARY_CHASSIS | AZALIA_RIGHT,
+						AZALIA_MIC_IN,
+						AZALIA_STEREO_MONO_1_8,
+						AZALIA_BLACK,
+						AZALIA_JACK_PRESENCE_DETECT,
+						4,
+						0
 					)),
 	AZALIA_PIN_CFG(0, MIC2,		AZALIA_PIN_CFG_NC(0)),
 	AZALIA_PIN_CFG(0, LINE1,	AZALIA_PIN_CFG_NC(0)),

From 4626c053ddaf88f9d3af0a127ed62925a8013e94 Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Thu, 4 Sep 2025 10:58:39 -0500
Subject: [PATCH 1954/3886] mb/starlabs/starbook/adl_n: Update HDA verb table

Remove presence detection flag for the DMIC and internal speakers.
While we're at it, fix the (non-functional) descriptive flags for
those two verbs as well. Remove unnecessary line continuations.

TEST=build/boot Win11 and Linux on Starbook ADL-N, verify speaker and
intermal mic working, as well as headphones/jack mic when plugged in.

Change-Id: If91c723b6a2fa145c640e06a21198c5ff30a34f2
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89043
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
---
 .../starbook/variants/adl_n/hda_verb.c        | 72 +++++++++----------
 1 file changed, 36 insertions(+), 36 deletions(-)

diff --git a/src/mainboard/starlabs/starbook/variants/adl_n/hda_verb.c b/src/mainboard/starlabs/starbook/variants/adl_n/hda_verb.c
index 89de21c1d4..1d03e21a55 100644
--- a/src/mainboard/starlabs/starbook/variants/adl_n/hda_verb.c
+++ b/src/mainboard/starlabs/starbook/variants/adl_n/hda_verb.c
@@ -27,47 +27,47 @@ const u32 cim_verb_data[] = {
 	AZALIA_SUBVENDOR(0, 0x1e507038),
 
 	AZALIA_PIN_CFG(0, 0x01,		0x00000000),
-	AZALIA_PIN_CFG(0, DMIC,		AZALIA_PIN_DESC(					\
-						AZALIA_INTEGRATED,				\
-						AZALIA_INTERNAL | AZALIA_TOP,			\
-						AZALIA_MIC_IN,					\
-						AZALIA_TYPE_UNKNOWN,				\
-						AZALIA_BLACK,					\
-						AZALIA_JACK_PRESENCE_DETECT,			\
-						3,						\
-						0						\
+	AZALIA_PIN_CFG(0, DMIC,		AZALIA_PIN_DESC(
+						AZALIA_INTEGRATED,
+						AZALIA_MOBILE_LID_INSIDE,
+						AZALIA_MIC_IN,
+						AZALIA_OTHER_DIGITAL,
+						AZALIA_COLOR_UNKNOWN,
+						AZALIA_NO_JACK_PRESENCE_DETECT,
+						3,
+						0
 					)),
 
-	AZALIA_PIN_CFG(0, SPEAKERS,	AZALIA_PIN_DESC(					\
-						AZALIA_INTEGRATED,				\
-						AZALIA_INTERNAL | AZALIA_FRONT,			\
-						AZALIA_SPEAKER,					\
-						AZALIA_TYPE_UNKNOWN,				\
-						AZALIA_BLACK,					\
-						AZALIA_JACK_PRESENCE_DETECT,			\
-						1,						\
-						0						\
+	AZALIA_PIN_CFG(0, SPEAKERS,	AZALIA_PIN_DESC(
+						AZALIA_INTEGRATED,
+						AZALIA_INTERNAL | AZALIA_FRONT,
+						AZALIA_SPEAKER,
+						AZALIA_OTHER_ANALOG,
+						AZALIA_COLOR_UNKNOWN,
+						AZALIA_NO_JACK_PRESENCE_DETECT,
+						1,
+						0
 					)),
-	AZALIA_PIN_CFG(0, HEADPHONE,	AZALIA_PIN_DESC(					\
-						AZALIA_JACK,					\
-						AZALIA_EXTERNAL_PRIMARY_CHASSIS | AZALIA_RIGHT,	\
-						AZALIA_HP_OUT,					\
-						AZALIA_STEREO_MONO_1_8,				\
-						AZALIA_BLACK,					\
-						AZALIA_JACK_PRESENCE_DETECT,			\
-						2,						\
-						0						\
+	AZALIA_PIN_CFG(0, HEADPHONE,	AZALIA_PIN_DESC(
+						AZALIA_JACK,
+						AZALIA_EXTERNAL_PRIMARY_CHASSIS | AZALIA_RIGHT,
+						AZALIA_HP_OUT,
+						AZALIA_STEREO_MONO_1_8,
+						AZALIA_BLACK,
+						AZALIA_JACK_PRESENCE_DETECT,
+						2,
+						0
 					)),
 	AZALIA_PIN_CFG(0, MONO,		AZALIA_PIN_CFG_NC(0)),
-	AZALIA_PIN_CFG(0, MIC1,		AZALIA_PIN_DESC(					\
-						AZALIA_JACK,					\
-						AZALIA_EXTERNAL_PRIMARY_CHASSIS | AZALIA_RIGHT,	\
-						AZALIA_MIC_IN,					\
-						AZALIA_STEREO_MONO_1_8,				\
-						AZALIA_BLACK,					\
-						AZALIA_JACK_PRESENCE_DETECT,			\
-						4,						\
-						0						\
+	AZALIA_PIN_CFG(0, MIC1,		AZALIA_PIN_DESC(
+						AZALIA_JACK,
+						AZALIA_EXTERNAL_PRIMARY_CHASSIS | AZALIA_RIGHT,
+						AZALIA_MIC_IN,
+						AZALIA_STEREO_MONO_1_8,
+						AZALIA_BLACK,
+						AZALIA_JACK_PRESENCE_DETECT,
+						4,
+						0
 					)),
 	AZALIA_PIN_CFG(0, MIC2,		AZALIA_PIN_CFG_NC(0)),
 	AZALIA_PIN_CFG(0, LINE1,	AZALIA_PIN_CFG_NC(0)),

From 5e2f5050ba29a7c40cd0f1e04b3713e339b965ff Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Thu, 4 Sep 2025 11:01:32 -0500
Subject: [PATCH 1955/3886] mb/starlabs/starbook/kbl: Update HDA verb table

Remove presence detection flag for the DMIC and internal speakers.
While we're at it, fix the (non-functional) descriptive flags for
those two verbs as well. Remove unnecessary line continuations.

TEST=build/boot Win11 and Linux on Starbook KBL, verify speaker and
intermal mic working, as well as headphones/jack mic when plugged in.

Change-Id: I4d4a41736faac944b3165a56fe5846f24c20f549
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89044
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
---
 .../starlabs/starbook/variants/kbl/hda_verb.c | 72 +++++++++----------
 1 file changed, 36 insertions(+), 36 deletions(-)

diff --git a/src/mainboard/starlabs/starbook/variants/kbl/hda_verb.c b/src/mainboard/starlabs/starbook/variants/kbl/hda_verb.c
index 7da0991336..82071822a4 100644
--- a/src/mainboard/starlabs/starbook/variants/kbl/hda_verb.c
+++ b/src/mainboard/starlabs/starbook/variants/kbl/hda_verb.c
@@ -27,47 +27,47 @@ const u32 cim_verb_data[] = {
 	AZALIA_SUBVENDOR(0, 0x1e507038),
 
 	AZALIA_PIN_CFG(0, 0x01,		0x00000000),
-	AZALIA_PIN_CFG(0, DMIC,		AZALIA_PIN_DESC(					\
-						AZALIA_INTEGRATED,				\
-						AZALIA_INTERNAL | AZALIA_TOP,			\
-						AZALIA_MIC_IN,					\
-						AZALIA_TYPE_UNKNOWN,				\
-						AZALIA_BLACK,					\
-						AZALIA_JACK_PRESENCE_DETECT,			\
-						3,						\
-						0						\
+	AZALIA_PIN_CFG(0, DMIC,		AZALIA_PIN_DESC(
+						AZALIA_INTEGRATED,
+						AZALIA_MOBILE_LID_INSIDE,
+						AZALIA_MIC_IN,
+						AZALIA_OTHER_DIGITAL,
+						AZALIA_COLOR_UNKNOWN,
+						AZALIA_NO_JACK_PRESENCE_DETECT,
+						3,
+						0
 					)),
 
-	AZALIA_PIN_CFG(0, SPEAKERS,	AZALIA_PIN_DESC(					\
-						AZALIA_INTEGRATED,				\
-						AZALIA_INTERNAL | AZALIA_FRONT,			\
-						AZALIA_SPEAKER,					\
-						AZALIA_TYPE_UNKNOWN,				\
-						AZALIA_BLACK,					\
-						AZALIA_JACK_PRESENCE_DETECT,			\
-						1,						\
-						0						\
+	AZALIA_PIN_CFG(0, SPEAKERS,	AZALIA_PIN_DESC(
+						AZALIA_INTEGRATED,
+						AZALIA_INTERNAL | AZALIA_FRONT,
+						AZALIA_SPEAKER,
+						AZALIA_OTHER_ANALOG,
+						AZALIA_COLOR_UNKNOWN,
+						AZALIA_NO_JACK_PRESENCE_DETECT,
+						1,
+						0
 					)),
-	AZALIA_PIN_CFG(0, HEADPHONE,	AZALIA_PIN_DESC(					\
-						AZALIA_JACK,					\
-						AZALIA_EXTERNAL_PRIMARY_CHASSIS | AZALIA_RIGHT,	\
-						AZALIA_HP_OUT,					\
-						AZALIA_STEREO_MONO_1_8,				\
-						AZALIA_BLACK,					\
-						AZALIA_JACK_PRESENCE_DETECT,			\
-						2,						\
-						0						\
+	AZALIA_PIN_CFG(0, HEADPHONE,	AZALIA_PIN_DESC(
+						AZALIA_JACK,
+						AZALIA_EXTERNAL_PRIMARY_CHASSIS | AZALIA_RIGHT,
+						AZALIA_HP_OUT,
+						AZALIA_STEREO_MONO_1_8,
+						AZALIA_BLACK,
+						AZALIA_JACK_PRESENCE_DETECT,
+						2,
+						0
 					)),
 	AZALIA_PIN_CFG(0, MONO,		AZALIA_PIN_CFG_NC(0)),
-	AZALIA_PIN_CFG(0, MIC1,		AZALIA_PIN_DESC(					\
-						AZALIA_JACK,					\
-						AZALIA_EXTERNAL_PRIMARY_CHASSIS | AZALIA_RIGHT,	\
-						AZALIA_MIC_IN,					\
-						AZALIA_STEREO_MONO_1_8,				\
-						AZALIA_BLACK,					\
-						AZALIA_JACK_PRESENCE_DETECT,			\
-						4,						\
-						0						\
+	AZALIA_PIN_CFG(0, MIC1,		AZALIA_PIN_DESC(
+						AZALIA_JACK,
+						AZALIA_EXTERNAL_PRIMARY_CHASSIS | AZALIA_RIGHT,
+						AZALIA_MIC_IN,
+						AZALIA_STEREO_MONO_1_8,
+						AZALIA_BLACK,
+						AZALIA_JACK_PRESENCE_DETECT,
+						4,
+						0
 					)),
 	AZALIA_PIN_CFG(0, MIC2,		AZALIA_PIN_CFG_NC(0)),
 	AZALIA_PIN_CFG(0, LINE1,	AZALIA_PIN_CFG_NC(0)),

From 621633af9b8910573c071f061577de05f1331d6d Mon Sep 17 00:00:00 2001
From: Jeremy Compostella <jeremy.compostella@intel.com>
Date: Thu, 28 Aug 2025 15:23:45 -0700
Subject: [PATCH 1956/3886] mainboard/google/fatcat: Remove UFS support

Unified Flash Storage (UFS) has been descoped from Panther Lake
configurations. This commit removes UFS-related configurations and GPIO
pad settings across relevant files.

BUG=b:442891168

Change-Id: Icf66dfc736a5b3a45c324fa494e7cf44b0178593
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88987
Reviewed-by: Jamie Ryu <jamie.m.ryu@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Reviewed-by: Cliff Huang <cliff.huang@intel.com>
---
 src/mainboard/google/fatcat/variants/fatcat/fw_config.c   | 8 +-------
 .../google/fatcat/variants/fatcat/overridetree.cb         | 7 +------
 .../google/fatcat/variants/felino/overridetree.cb         | 2 +-
 3 files changed, 3 insertions(+), 14 deletions(-)

diff --git a/src/mainboard/google/fatcat/variants/fatcat/fw_config.c b/src/mainboard/google/fatcat/variants/fatcat/fw_config.c
index e10dfbb389..d1f40ec06d 100644
--- a/src/mainboard/google/fatcat/variants/fatcat/fw_config.c
+++ b/src/mainboard/google/fatcat/variants/fatcat/fw_config.c
@@ -247,11 +247,6 @@ static const struct pad_config gen4_ssd_pads[] = {
 	PAD_CFG_GPO(GPP_B09, 1, PLTRST),
 };
 
-static const struct pad_config ufs_enable_pads[] = {
-	/* GPP_D21:     GPP_D21_UFS_REFCLK */
-	PAD_CFG_NF(GPP_D21, NONE, DEEP, NF1),
-};
-
 /* Gen5 NVME: at the bottom M.2 slot */
 static const struct pad_config pre_mem_gen5_ssd_pwr_pads[] = {
 	/* GPP_B16:     GEN5_SSD_PWREN */
@@ -613,11 +608,10 @@ void fw_config_gpio_padbased_override(struct pad_config *padbased_table)
 	} else if (fw_config_probe(FW_CONFIG(STORAGE, STORAGE_NVME_GEN5))) {
 		GPIO_PADBASED_OVERRIDE(padbased_table, gen5_ssd_pads);
 	} else if (fw_config_probe(FW_CONFIG(STORAGE, STORAGE_UFS))) {
-		GPIO_PADBASED_OVERRIDE(padbased_table, ufs_enable_pads);
+		die("UFS is not supported on Panther Lake\n");
 	} else if (fw_config_probe(FW_CONFIG(STORAGE, STORAGE_UNKNOWN))) {
 		GPIO_PADBASED_OVERRIDE(padbased_table, gen4_ssd_pads);
 		GPIO_PADBASED_OVERRIDE(padbased_table, gen5_ssd_pads);
-		GPIO_PADBASED_OVERRIDE(padbased_table, ufs_enable_pads);
 	}
 
 	if (fw_config_probe(FW_CONFIG(AUDIO, AUDIO_NONE))) {
diff --git a/src/mainboard/google/fatcat/variants/fatcat/overridetree.cb b/src/mainboard/google/fatcat/variants/fatcat/overridetree.cb
index a3e94ca659..f553c39d3c 100644
--- a/src/mainboard/google/fatcat/variants/fatcat/overridetree.cb
+++ b/src/mainboard/google/fatcat/variants/fatcat/overridetree.cb
@@ -39,7 +39,7 @@ fw_config
 		option STORAGE_UNKNOWN		0
 		option STORAGE_NVME_GEN4	1
 		option STORAGE_NVME_GEN5	2
-		option STORAGE_UFS		3
+		option STORAGE_UFS		3 # Not supported
 	end
 	field FP 17
 		option FP_ABSENT		0
@@ -524,11 +524,6 @@ chip soc/intel/pantherlake
 			end
 		end
 
-		device ref ufs on
-			probe STORAGE STORAGE_UFS
-			probe STORAGE STORAGE_UNKNOWN
-		end
-
 		device ref pcie_rp2 on
 			probe CELLULAR CELLULAR_PCIE
 			register "pcie_rp[PCIE_RP(2)]" = "{
diff --git a/src/mainboard/google/fatcat/variants/felino/overridetree.cb b/src/mainboard/google/fatcat/variants/felino/overridetree.cb
index 743877db5a..d2bbc80767 100644
--- a/src/mainboard/google/fatcat/variants/felino/overridetree.cb
+++ b/src/mainboard/google/fatcat/variants/felino/overridetree.cb
@@ -25,7 +25,7 @@ fw_config
 		option STORAGE_UNKNOWN		0
 		option STORAGE_NVME_GEN4	1
 		option STORAGE_NVME_GEN5	2
-		option STORAGE_UFS		3
+		option STORAGE_UFS		3 # Not supported
 	end
 	field KB 10 11
 		option KB_UNKNOWN		0

From 5b46caef93ae4aa1f0a1df7a1480fe80a5f7ec8e Mon Sep 17 00:00:00 2001
From: Jeremy Compostella <jeremy.compostella@intel.com>
Date: Thu, 28 Aug 2025 16:13:49 -0700
Subject: [PATCH 1957/3886] mainboard/intel/ptlrvp: Remove UFS support

Unified Flash Storage (UFS) has been descoped from Panther Lake
configurations. This commit removes UFS-related configurations and GPIO
pad settings across relevant files.

BUG=b:442891168

Change-Id: I5de2878aa44e2d48879b9ecf274aebedfbf551ca
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88989
Reviewed-by: Jamie Ryu <jamie.m.ryu@intel.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Reviewed-by: Cliff Huang <cliff.huang@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/intel/ptlrvp/variants/ptlrvp/fw_config.c    | 8 +-------
 .../intel/ptlrvp/variants/ptlrvp/overridetree.cb          | 7 +------
 .../intel/ptlrvp/variants/ptlrvp_chromeec/overridetree.cb | 7 +------
 3 files changed, 3 insertions(+), 19 deletions(-)

diff --git a/src/mainboard/intel/ptlrvp/variants/ptlrvp/fw_config.c b/src/mainboard/intel/ptlrvp/variants/ptlrvp/fw_config.c
index afd8a63084..a0f12c2a8b 100644
--- a/src/mainboard/intel/ptlrvp/variants/ptlrvp/fw_config.c
+++ b/src/mainboard/intel/ptlrvp/variants/ptlrvp/fw_config.c
@@ -248,11 +248,6 @@ static const struct pad_config gen4_ssd_pads[] = {
 	PAD_CFG_GPO(GPP_B09, 1, PLTRST),
 };
 
-static const struct pad_config ufs_enable_pads[] = {
-	/* GPP_D21:     GPP_D21_UFS_REFCLK */
-	PAD_CFG_NF(GPP_D21, NONE, DEEP, NF1),
-};
-
 /* Gen5 NVME: at the bottom M.2 slot */
 static const struct pad_config pre_mem_gen5_ssd_pwr_pads[] = {
 	/* GPP_B16:     GEN5_SSD_PWREN */
@@ -601,11 +596,10 @@ void fw_config_gpio_padbased_override(struct pad_config *padbased_table)
 	} else if (fw_config_probe(FW_CONFIG(STORAGE, STORAGE_NVME_GEN5))) {
 		GPIO_PADBASED_OVERRIDE(padbased_table, gen5_ssd_pads);
 	} else if (fw_config_probe(FW_CONFIG(STORAGE, STORAGE_UFS))) {
-		GPIO_PADBASED_OVERRIDE(padbased_table, ufs_enable_pads);
+		die("UFS is not supported on Panther Lake\n");
 	} else if (fw_config_probe(FW_CONFIG(STORAGE, STORAGE_UNKNOWN))) {
 		GPIO_PADBASED_OVERRIDE(padbased_table, gen4_ssd_pads);
 		GPIO_PADBASED_OVERRIDE(padbased_table, gen5_ssd_pads);
-		GPIO_PADBASED_OVERRIDE(padbased_table, ufs_enable_pads);
 	}
 
 	if (fw_config_probe(FW_CONFIG(AUDIO, AUDIO_NONE))) {
diff --git a/src/mainboard/intel/ptlrvp/variants/ptlrvp/overridetree.cb b/src/mainboard/intel/ptlrvp/variants/ptlrvp/overridetree.cb
index 68136d26ea..6a945727aa 100644
--- a/src/mainboard/intel/ptlrvp/variants/ptlrvp/overridetree.cb
+++ b/src/mainboard/intel/ptlrvp/variants/ptlrvp/overridetree.cb
@@ -39,7 +39,7 @@ fw_config
 		option STORAGE_UNKNOWN		0
 		option STORAGE_NVME_GEN4	1
 		option STORAGE_NVME_GEN5	2
-		option STORAGE_UFS		3
+		option STORAGE_UFS		3 # Not supported
 	end
 	field FP 17
 		option FP_ABSENT		0
@@ -518,11 +518,6 @@ chip soc/intel/pantherlake
 			end
 		end
 
-		device ref ufs on
-			probe STORAGE STORAGE_UFS
-			probe STORAGE STORAGE_UNKNOWN
-		end
-
 		device ref pcie_rp2 on
 			probe CELLULAR CELLULAR_PCIE
 			register "pcie_rp[PCIE_RP(2)]" = "{
diff --git a/src/mainboard/intel/ptlrvp/variants/ptlrvp_chromeec/overridetree.cb b/src/mainboard/intel/ptlrvp/variants/ptlrvp_chromeec/overridetree.cb
index 033a0b475b..52af027cad 100644
--- a/src/mainboard/intel/ptlrvp/variants/ptlrvp_chromeec/overridetree.cb
+++ b/src/mainboard/intel/ptlrvp/variants/ptlrvp_chromeec/overridetree.cb
@@ -39,7 +39,7 @@ fw_config
 		option STORAGE_UNKNOWN		0
 		option STORAGE_NVME_GEN4	1
 		option STORAGE_NVME_GEN5	2
-		option STORAGE_UFS		3
+		option STORAGE_UFS		3 # Not supported
 	end
 	field FP 17
 		option FP_ABSENT		0
@@ -518,11 +518,6 @@ chip soc/intel/pantherlake
 			end
 		end
 
-		device ref ufs on
-			probe STORAGE STORAGE_UFS
-			probe STORAGE STORAGE_UNKNOWN
-		end
-
 		device ref pcie_rp2 on
 			probe CELLULAR CELLULAR_PCIE
 			register "pcie_rp[PCIE_RP(2)]" = "{

From 56dbafcff418d70f7069fd2c805395dbab0c4d84 Mon Sep 17 00:00:00 2001
From: Jeremy Compostella <jeremy.compostella@intel.com>
Date: Thu, 28 Aug 2025 15:27:57 -0700
Subject: [PATCH 1958/3886] soc/intel/pantherlake: Remove UFS support

Unified Flash Storage (UFS) has been descoped from Panther Lake
configurations, limiting UFS functionality to Wildcat Lake. This change
removes Panther Lake's UFS configuration options and references,
ensuring proper alignment with the current product specifications.

BUG=b:442891168

Change-Id: Ib7e7498a57c8fbc924d6dcf70e374611733918c0
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88988
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Cliff Huang <cliff.huang@intel.com>
Reviewed-by: Jamie Ryu <jamie.m.ryu@intel.com>
---
 src/soc/intel/pantherlake/Kconfig                | 1 +
 src/soc/intel/pantherlake/acpi/southbridge.asl   | 2 +-
 src/soc/intel/pantherlake/chipset_ptl.cb         | 1 -
 src/soc/intel/pantherlake/fsp_params.c           | 4 ++--
 src/soc/intel/pantherlake/include/soc/pci_devs.h | 2 +-
 5 files changed, 5 insertions(+), 5 deletions(-)

diff --git a/src/soc/intel/pantherlake/Kconfig b/src/soc/intel/pantherlake/Kconfig
index d604edb555..d4c60022f3 100644
--- a/src/soc/intel/pantherlake/Kconfig
+++ b/src/soc/intel/pantherlake/Kconfig
@@ -453,6 +453,7 @@ config SOC_PHYSICAL_ADDRESS_WIDTH
 
 config SOC_INTEL_UFS_CLK_FREQ_HZ
 	int
+	depends on SOC_INTEL_WILDCATLAKE
 	default 38400000
 
 # Override DEBUG Kconfig to avoid false alarm about stack overflow.
diff --git a/src/soc/intel/pantherlake/acpi/southbridge.asl b/src/soc/intel/pantherlake/acpi/southbridge.asl
index 302099373d..f2ad16b36b 100644
--- a/src/soc/intel/pantherlake/acpi/southbridge.asl
+++ b/src/soc/intel/pantherlake/acpi/southbridge.asl
@@ -54,6 +54,6 @@
 #endif
 
 /* UFS 0:17:0 */
-#if (CONFIG(SOC_INTEL_PANTHERLAKE_U_H) || CONFIG(SOC_INTEL_WILDCATLAKE))
+#if CONFIG(SOC_INTEL_WILDCATLAKE)
 #include <soc/intel/common/block/acpi/acpi/ufs.asl>
 #endif
diff --git a/src/soc/intel/pantherlake/chipset_ptl.cb b/src/soc/intel/pantherlake/chipset_ptl.cb
index 1b81b739bb..e7cac8dd64 100644
--- a/src/soc/intel/pantherlake/chipset_ptl.cb
+++ b/src/soc/intel/pantherlake/chipset_ptl.cb
@@ -173,7 +173,6 @@ chip soc/intel/pantherlake
 		device pci 16.1 alias heci2 off end
 		device pci 16.4 alias heci3 off end
 		device pci 16.5 alias heci4 off end
-		device pci 17.0 alias ufs off end
 		device pci 18.0 alias eheci1 off end
 		device pci 18.1 alias eheci2 off end
 		device pci 18.2 alias eheci3 off end
diff --git a/src/soc/intel/pantherlake/fsp_params.c b/src/soc/intel/pantherlake/fsp_params.c
index b5dfd4d4df..e423986d53 100644
--- a/src/soc/intel/pantherlake/fsp_params.c
+++ b/src/soc/intel/pantherlake/fsp_params.c
@@ -212,7 +212,7 @@ static const struct slot_irq_constraints irq_constraints[] = {
 			ANY_PIRQ(PCI_DEVFN_CSE_4),
 		},
 	},
-#if (CONFIG(SOC_INTEL_PANTHERLAKE_U_H) || CONFIG(SOC_INTEL_WILDCATLAKE))
+#if (CONFIG(SOC_INTEL_WILDCATLAKE))
 	{
 		.slot = PCI_DEV_SLOT_UFS,
 		.fns = {
@@ -741,7 +741,7 @@ static void fill_fsps_iax_params(FSP_S_CONFIG *s_cfg,
 static void fill_fsps_ufs_params(FSP_S_CONFIG *s_cfg,
 		const struct soc_intel_pantherlake_config *config)
 {
-#if (CONFIG(SOC_INTEL_PANTHERLAKE_U_H) || CONFIG(SOC_INTEL_WILDCATLAKE))
+#if CONFIG(SOC_INTEL_WILDCATLAKE)
 	/* Setting FSP UPD (1,0) to enable controller 0 */
 	s_cfg->UfsEnable[0] = is_devfn_enabled(PCI_DEVFN_UFS);
 	s_cfg->UfsEnable[1] = 0;
diff --git a/src/soc/intel/pantherlake/include/soc/pci_devs.h b/src/soc/intel/pantherlake/include/soc/pci_devs.h
index 7dc55e1045..4d7d2301b0 100644
--- a/src/soc/intel/pantherlake/include/soc/pci_devs.h
+++ b/src/soc/intel/pantherlake/include/soc/pci_devs.h
@@ -150,7 +150,7 @@
 #define  PCI_DEV_CSE_3		_PCI_DEV(CSE, 4)
 #define  PCI_DEV_CSE_4		_PCI_DEV(CSE, 5)
 
-#if (CONFIG(SOC_INTEL_PANTHERLAKE_U_H) || CONFIG(SOC_INTEL_WILDCATLAKE))
+#if CONFIG(SOC_INTEL_WILDCATLAKE)
 #define PCI_DEV_SLOT_UFS	0x17
 #define  PCI_DEVFN_UFS		_PCI_DEVFN(UFS, 0)
 #define  PCI_DEV_UFS		_PCI_DEV(UFS, 0)

From ed59c1de34b16fd1a79536e653f46df7220d92c0 Mon Sep 17 00:00:00 2001
From: smadhesu <smadhesu@qualcomm.corp-partner.google.com>
Date: Wed, 3 Sep 2025 22:53:26 +0530
Subject: [PATCH 1959/3886] soc/qualcomm/x1p42100: Update TF-A memory
 reservation

This patch updates the DRAM memory reservation range for TF-A
to align with the latest Bluey memory layout specifications.

TEST=Verified boot up on google/bluey.

Change-Id: Ifb67e591d0f3d28cd6b0856198b29af49c2aab4c
Signed-off-by: smadhesu <smadhesu@qualcomm.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89029
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
---
 src/soc/qualcomm/x1p42100/memlayout.ld | 10 +++++-----
 1 file changed, 5 insertions(+), 5 deletions(-)

diff --git a/src/soc/qualcomm/x1p42100/memlayout.ld b/src/soc/qualcomm/x1p42100/memlayout.ld
index 2a9ac452d3..58e37a36c5 100644
--- a/src/soc/qualcomm/x1p42100/memlayout.ld
+++ b/src/soc/qualcomm/x1p42100/memlayout.ld
@@ -25,11 +25,11 @@
  *               |                        CBMEM                             |      |        |
  *               +----------------------------------------------------------+      |        |
  *               |                ... Usable memory ...                     |      |        |
- * 0xDF4C0000    +----------------------------------------------------------+      |        |
+ * 0xD8600000    +----------------------------------------------------------+      |        |
+ *               |                 BL31 (ARM Trusted Firmware)              |      |        |
+ * 0xD856A000    +----------------------------------------------------------+      |        |
  *               |               dram_tz_rem (TrustZone Remainder)          |      |        |
  * 0xD81D6000    +----------------------------------------------------------+      |        |
- *               |                 BL31 (ARM Trusted Firmware)              |      |        |
- * 0xD80D6000    +----------------------------------------------------------+      |        |
  *               |                  dram_tz (TrustZone)                     |      |        |
  * 0xD8000000    +----------------------------------------------------------+      |      DRAM
  *               |               ... Usable memory ...                      |      |        |
@@ -185,8 +185,8 @@ SECTIONS
 	POSTRAM_CBFS_CACHE(0x9F800000, 16M)
 	RAMSTAGE(0xA0800000, 16M)
 	REGION(dram_tz, 0xD8000000, 0xD6000, 4K)
-	BL31(0xD80D6000, 1M)
-	REGION(dram_tz_rem, 0xD81D6000, 0x72EA000, 4K)
+	REGION(dram_tz_rem, 0xD81D6000, 0x394000, 4K)
+	BL31(0xD856A000, 600K)
 	REGION(dram_smem, 0xFF800000, 0x800000, 4K)
 	DRAM_END(0x100000000)
 

From 80df8c336f0a8725358ecd8202a54c20cf00e65e Mon Sep 17 00:00:00 2001
From: Bora Guvendik <bora.guvendik@intel.com>
Date: Tue, 26 Aug 2025 16:06:53 -0700
Subject: [PATCH 1960/3886] mb/intel/ptlrvp: Update Kconfig for
 ptlrvp_chromeec4s and ptlrvp4es support
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Added support for new mainboard configurations, `ptlrvp_chromeec4es`
and `ptlrvp4es`, to the Intel PTLRVP platform. These configurations
extend the existing options for pre-production silicon of the
Panther Lake SoC.

BUG=none
TEST=Build with new configurations to ensure successful compilation and
correct feature selections.

Change-Id: I3f716ab71a97d02b1694858d966f8111f18adff3
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88997
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/intel/ptlrvp/Kconfig      | 39 ++++++++++++++++++++-----
 src/mainboard/intel/ptlrvp/Kconfig.name |  6 ++++
 src/mainboard/intel/ptlrvp/Makefile.mk  |  7 +++--
 3 files changed, 41 insertions(+), 11 deletions(-)

diff --git a/src/mainboard/intel/ptlrvp/Kconfig b/src/mainboard/intel/ptlrvp/Kconfig
index 476313f60d..ec30b29491 100644
--- a/src/mainboard/intel/ptlrvp/Kconfig
+++ b/src/mainboard/intel/ptlrvp/Kconfig
@@ -56,8 +56,14 @@ config BOARD_INTEL_MODEL_PTLRVP
 
 config BOARD_INTEL_PTLRVP
 	select BOARD_INTEL_MODEL_PTLRVP
-	select MAINBOARD_USES_IFD_EC_REGION
 	select FW_CONFIG_SOURCE_CBFS
+	select MAINBOARD_USES_IFD_EC_REGION
+
+config BOARD_INTEL_PTLRVP4ES
+	select BOARD_INTEL_MODEL_PTLRVP
+	select FW_CONFIG_SOURCE_CBFS
+	select MAINBOARD_USES_IFD_EC_REGION
+	select SOC_INTEL_PANTHERLAKE_PRE_PRODUCTION_SILICON
 
 config BOARD_INTEL_PTLRVP_CHROMEEC
 	select BOARD_INTEL_MODEL_PTLRVP
@@ -73,6 +79,21 @@ config BOARD_INTEL_PTLRVP_CHROMEEC
 	select MAINBOARD_USES_IFD_EC_REGION
 	select TPM_GOOGLE_TI50
 
+config BOARD_INTEL_PTLRVP_CHROMEEC4ES
+	select BOARD_INTEL_MODEL_PTLRVP
+	select EC_GOOGLE_CHROMEEC
+	select EC_GOOGLE_CHROMEEC_BOARDID
+	select EC_GOOGLE_CHROMEEC_ESPI
+	select EC_GOOGLE_CHROMEEC_MEC
+	select EC_GOOGLE_CHROMEEC_SKUID
+	select EC_GOOGLE_CHROMEEC_SMBIOS
+	select FW_CONFIG_SOURCE_CHROMEEC_CBI
+	select I2C_TPM
+	select MAINBOARD_HAS_TPM2
+	select MAINBOARD_USES_IFD_EC_REGION
+	select TPM_GOOGLE_TI50
+	select SOC_INTEL_PANTHERLAKE_PRE_PRODUCTION_SILICON
+
 if BOARD_INTEL_PTLRVP_COMMON
 
 config BASEBOARD_DIR
@@ -80,7 +101,7 @@ config BASEBOARD_DIR
 	default "ptlrvp"
 
 config CHROMEOS
-	select EC_GOOGLE_CHROMEEC_SWITCHES if BOARD_INTEL_PTLRVP_CHROMEEC
+	select EC_GOOGLE_CHROMEEC_SWITCHES if EC_GOOGLE_CHROMEEC
 	select GBB_FLAG_DISABLE_EC_SOFTWARE_SYNC if EC_GOOGLE_CHROMEEC_MEC
 	select GBB_FLAG_FORCE_DEV_BOOT_USB
 	select GBB_FLAG_FORCE_MANUAL_RECOVERY
@@ -102,11 +123,11 @@ config DIMM_SPD_SIZE
 
 config DRIVER_TPM_I2C_ADDR
 	hex
-	default 0x50 if BOARD_INTEL_PTLRVP_CHROMEEC
+	default 0x50 if EC_GOOGLE_CHROMEEC
 
 config DRIVER_TPM_I2C_BUS
 	hex
-	default 0x03 if BOARD_INTEL_PTLRVP_CHROMEEC
+	default 0x03 if EC_GOOGLE_CHROMEEC
 
 config HAVE_SLP_S0_GATE
 	def_bool n
@@ -120,7 +141,9 @@ config MAINBOARD_FAMILY
 
 config MAINBOARD_PART_NUMBER
 	default "Ptlrvp" if BOARD_INTEL_PTLRVP
+	default "Ptlrvp4es" if BOARD_INTEL_PTLRVP4ES
 	default "Ptlrvp_chromeec" if BOARD_INTEL_PTLRVP_CHROMEEC
+	default "Ptlrvp_chromeec4es" if BOARD_INTEL_PTLRVP_CHROMEEC4ES
 
 config MEMORY_SOLDERDOWN
 	def_bool n
@@ -129,7 +152,7 @@ config MEMORY_SOLDERDOWN
 
 config TPM_TIS_ACPI_INTERRUPT
 	int
-	default 47 if BOARD_INTEL_PTLRVP_CHROMEEC # GPE0_DW1_15 (GPP_D15)
+	default 47 if EC_GOOGLE_CHROMEEC # GPE0_DW1_15 (GPP_D15)
 
 # FIXME: update as per board schematics
 config UART_FOR_CONSOLE
@@ -144,11 +167,11 @@ config VARIANT_DIR
 	default "ptlrvp" if BOARD_INTEL_MODEL_PTLRVP
 
 config OVERRIDE_DEVICETREE
-	default "variants/\$(CONFIG_VARIANT_DIR)/overridetree.cb" if BOARD_INTEL_PTLRVP
-	default "variants/\$(CONFIG_VARIANT_DIR)_chromeec/overridetree.cb" if BOARD_INTEL_PTLRVP_CHROMEEC
+	default "variants/\$(CONFIG_VARIANT_DIR)/overridetree.cb" if BOARD_INTEL_PTLRVP || BOARD_INTEL_PTLRVP4ES
+	default "variants/\$(CONFIG_VARIANT_DIR)_chromeec/overridetree.cb" if BOARD_INTEL_PTLRVP_CHROMEEC || BOARD_INTEL_PTLRVP_CHROMEEC4ES
 
 config VBOOT
 	select VBOOT_LID_SWITCH
-	select VBOOT_MOCK_SECDATA if BOARD_INTEL_PTLRVP
+	select VBOOT_MOCK_SECDATA if !EC_GOOGLE_CHROMEEC
 
 endif # BOARD_INTEL_PTLRVP_COMMON
diff --git a/src/mainboard/intel/ptlrvp/Kconfig.name b/src/mainboard/intel/ptlrvp/Kconfig.name
index 9bcf99b2f2..a8aebf12f0 100644
--- a/src/mainboard/intel/ptlrvp/Kconfig.name
+++ b/src/mainboard/intel/ptlrvp/Kconfig.name
@@ -5,5 +5,11 @@ comment "Ptlrvp"
 config BOARD_INTEL_PTLRVP
 	bool "-> Ptlrvp"
 
+config BOARD_INTEL_PTLRVP4ES
+	bool "-> Ptlrvp4es"
+
 config BOARD_INTEL_PTLRVP_CHROMEEC
 	bool "-> Google Chrome EC"
+
+config BOARD_INTEL_PTLRVP_CHROMEEC4ES
+	bool "-> Google Chrome EC for Early Silicon"
diff --git a/src/mainboard/intel/ptlrvp/Makefile.mk b/src/mainboard/intel/ptlrvp/Makefile.mk
index d2c78f4411..37c7a5d2a2 100644
--- a/src/mainboard/intel/ptlrvp/Makefile.mk
+++ b/src/mainboard/intel/ptlrvp/Makefile.mk
@@ -3,17 +3,18 @@
 bootblock-y += bootblock.c
 
 verstage-$(CONFIG_CHROMEOS) += chromeos.c
-verstage-$(CONFIG_BOARD_INTEL_PTLRVP) += intel.c
+verstage-$(if $(filter y,$(CONFIG_EC_GOOGLE_CHROMEEC)),n,y) += intel.c
 
 romstage-y += romstage.c
 romstage-$(CONFIG_CHROMEOS) += chromeos.c
-romstage-$(CONFIG_BOARD_INTEL_PTLRVP) += intel.c
+romstage-$(if $(filter y,$(CONFIG_EC_GOOGLE_CHROMEEC)),n,y) += intel.c
 
 ramstage-y += mainboard.c
 ramstage-$(CONFIG_CHROMEOS) += chromeos.c
 ramstage-y += ec.c
 ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_HDA_VERB) += variants/$(VARIANT_DIR)/hda_verb.c
-ramstage-$(CONFIG_BOARD_INTEL_PTLRVP) += intel.c
+ramstage-$(if $(filter y,$(CONFIG_EC_GOOGLE_CHROMEEC)),n,y) += intel.c
+
 
 smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c
 

From 58726e58e4abb183611fcf9c8a2f63602a790631 Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Thu, 4 Sep 2025 21:31:27 +0100
Subject: [PATCH 1961/3886] mb/starlabs/starbook/mtl: Adjust the VBT to fix hot
 plug

* Reorder Child Device mappings to prioritise EFP displays.
* Enable DRRS and DMRRS.
* Change eDP panel colour depth from 18-bit to 24-bit (8 bpc).
* Change minimum brightness from 6 to 0.
* Enable PSR
* Clear unused flags

Change-Id: I96429f0848bc810d35028f31720911d2636db681
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89053
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 .../starlabs/starbook/variants/mtl/data.vbt   | Bin 7680 -> 7680 bytes
 .../starbook/variants/mtl/data_native_res.vbt | Bin 7680 -> 7680 bytes
 2 files changed, 0 insertions(+), 0 deletions(-)

diff --git a/src/mainboard/starlabs/starbook/variants/mtl/data.vbt b/src/mainboard/starlabs/starbook/variants/mtl/data.vbt
index 9dec888c9da82bd7889c8f9008e15ab335e05a04..b9189a74b0c9f171e61e4d1fd3bd689d313c45fd 100644
GIT binary patch
delta 120
zcmZp$X|S0f#mvcIFu9OXc%y+hqcRHv2ZI9;D=@GCX$LT^0OT_O`3yil1B1e3MrP^B
zt&B!Y3=ETZGVWz$m|V`J&d9KNKGQU2MuEwRY?_<n+449TQzoC|vj@uZ@i%e)2LlF%
L|C?v>r}F^-_%a+o

delta 128
zcmZp$X|S0f#oWSRFu9OXc%y+hqap(X3j+g#0}v|!F$a*x0pxK2c`QKMfk9!iBb)5x
zRz@QxHi^kQ8TT?WPcCOtXJp<ypJ^KNWD^mI$pvgeo8#H?I40lZ)0upik7u$VzsY1-
aexAv${N9|u|Ns8~|33r6@69v$)A;~UP9T~9

diff --git a/src/mainboard/starlabs/starbook/variants/mtl/data_native_res.vbt b/src/mainboard/starlabs/starbook/variants/mtl/data_native_res.vbt
index 228f85636c4363007d73c609814be32874765ef3..6a5f830b12a6c6a1206faec687fb07163f76a06b 100644
GIT binary patch
delta 120
zcmZp$X|S0f#mvQEFu9OXc%y+hqcRHv2ZI9;D=@GCX$LT^0OT_O`3yil1B1e3MrP^B
zt&B!Y3=ETZGVWz$m|V`J&d9KNKGQU2MuEwRY?_<n+449TQzoC|vj@uZ@i%e)2LlF%
L|C?v>r}F^-_@f*_

delta 128
zcmZp$X|S0f#oWqZFu9OXc%y+hqap(X3j+g#0}v|!F$a*x0pxK2c`QKMfk9!iBb)5x
zRz@QxHi^kQ8TT?WPcCOtXJp<ypJ^KNWD^mI$pvgeo8#H?I40lZ)0upik7u$VzsY1-
aexAv${N9|u|Ns8~|33r6@69v$)A;~U#~_;k


From 183589dcbd98b52a38d7dc95800cf1556dce1f73 Mon Sep 17 00:00:00 2001
From: Elyes Haouas <ehaouas@noos.fr>
Date: Sat, 23 Aug 2025 08:55:37 +0200
Subject: [PATCH 1962/3886] smbios.h: Update smbios_memory_form_factor

Add CAMM, CUDIMM and CSODIMM from factors.

Change-Id: I5719998583da9312f4de80a4fbe79f0b3cf0bfba
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88914
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/include/smbios.h | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/src/include/smbios.h b/src/include/smbios.h
index 353c3cf40b..2cf29399f8 100644
--- a/src/include/smbios.h
+++ b/src/include/smbios.h
@@ -187,6 +187,9 @@ typedef enum {
 	MEMORY_FORMFACTOR_SRIMM = 0x0e,
 	MEMORY_FORMFACTOR_FBDIMM = 0x0f,
 	MEMORY_FORMFACTOR_DIE = 0x10,
+	MEMORY_FORMFACTOR_CAMM = 0x11,
+	MEMORY_FORMFACTOR_CUDIMM = 0x12,
+	MEMORY_FORMFACTOR_CSODIMM = 0x13,
 } smbios_memory_form_factor;
 
 typedef enum {

From d4da53347368da1ee3236586bf163e2a9581d3f1 Mon Sep 17 00:00:00 2001
From: Elyes Haouas <ehaouas@noos.fr>
Date: Sat, 23 Aug 2025 09:06:34 +0200
Subject: [PATCH 1963/3886] smbios.h: Update smbios_memory_type

Add MRDIMM memory device type.

Change-Id: I3cfa3b9278ecebd4bc67c95dd2fb794556e80922
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88915
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
---
 src/include/smbios.h | 1 +
 1 file changed, 1 insertion(+)

diff --git a/src/include/smbios.h b/src/include/smbios.h
index 2cf29399f8..b9dbc0bdf6 100644
--- a/src/include/smbios.h
+++ b/src/include/smbios.h
@@ -226,6 +226,7 @@ typedef enum {
 	MEMORY_TYPE_DDR5 = 0x22,
 	MEMORY_TYPE_LPDDR5 = 0x23,
 	MEMORY_TYPE_HBM3 = 0x24,
+	MEMORY_TYPE_MRDIMM = 0x25,
 } smbios_memory_type;
 
 typedef enum {

From 73dd7bb0463d3138fc8bd61dcc6e1127685f7e10 Mon Sep 17 00:00:00 2001
From: Alexander Goncharov <chat@joursoir.net>
Date: Wed, 30 Jul 2025 12:13:11 +0300
Subject: [PATCH 1964/3886] util/amdfwtool/amdfwread: add initial parsing for
 EFW structure
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Intel ifdtool can dump the Intel Firmware Descriptor, which is helpful
for debugging and inspecting firmware binaries. This utility lacked
similar functionality, so this patch introduces a `--dump` CLI option
to display decoded information from the embedded firmware header.

Currently, the output includes SPI frequency and read mode for various
AMD family models.

Change-Id: Ideb1076f1d580496dac293882007cfa4672d188b
Signed-off-by: Alexander Goncharov <chat@joursoir.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88610
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
---
 util/amdfwtool/amdfwread.c | 116 ++++++++++++++++++++++++++++++++++++-
 1 file changed, 115 insertions(+), 1 deletion(-)

diff --git a/util/amdfwtool/amdfwread.c b/util/amdfwtool/amdfwread.c
index f581c1b8d3..7013318f81 100644
--- a/util/amdfwtool/amdfwread.c
+++ b/util/amdfwtool/amdfwread.c
@@ -12,6 +12,26 @@
 
 #define ERR(...) fprintf(stderr, __VA_ARGS__)
 
+enum spi_frequency {
+	SPI_FREQUENCY_66_66MHZ = 0,
+	SPI_FREQUENCY_33_33MHZ = 1,
+	SPI_FREQUENCY_22_22MHZ = 2,
+	SPI_FREQUENCY_16_66MHZ = 3,
+	SPI_FREQUENCY_100MHZ = 4,
+	SPI_FREQUENCY_800KHZ = 5,
+};
+
+enum spi_read_mode {
+	SPI_READ_MODE_NORMAL_33 = 0,
+	SPI_READ_MODE_RESERVED = 1,
+	SPI_READ_MODE_DUAL_1_1_2 = 2,
+	SPI_READ_MODE_QUAD_1_1_4 = 3,
+	SPI_READ_MODE_DUAL_1_2_2 = 4,
+	SPI_READ_MODE_QUAD_1_4_4 = 5,
+	SPI_READ_MODE_NORMAL_66 = 6,
+	SPI_READ_MODE_FAST = 7,
+};
+
 /* Possible locations for the header */
 const uint32_t fw_header_offsets[] = {
 	0xfa0000,
@@ -401,16 +421,102 @@ static int list_amdfw_ro(FILE *fw, const embedded_firmware *fw_header)
 	return 0;
 }
 
+static void decode_spi_frequency(unsigned int freq)
+{
+	switch (freq) {
+	case SPI_FREQUENCY_66_66MHZ:
+		printf("66.66MHz");
+		break;
+	case SPI_FREQUENCY_33_33MHZ:
+		printf("33.33MHz");
+		break;
+	case SPI_FREQUENCY_22_22MHZ:
+		printf("22.22MHz");
+		break;
+	case SPI_FREQUENCY_16_66MHZ:
+		printf("16.66MHz");
+		break;
+	case SPI_FREQUENCY_100MHZ:
+		printf("100MHz");
+		break;
+	case SPI_FREQUENCY_800KHZ:
+		printf("800kHz");
+		break;
+	default:
+		printf("unknown<%x>MHz", freq);
+	}
+}
+
+static void decode_spi_read_mode(unsigned int mode)
+{
+	switch (mode) {
+	case SPI_READ_MODE_NORMAL_33:
+		printf("Normal read (up to 33M)");
+		break;
+	case SPI_READ_MODE_RESERVED:
+		printf("Reserved");
+		break;
+	case SPI_READ_MODE_DUAL_1_1_2:
+		printf("Dual IO (1-1-2)");
+		break;
+	case SPI_READ_MODE_QUAD_1_1_4:
+		printf("Quad IO (1-1-4)");
+		break;
+	case SPI_READ_MODE_DUAL_1_2_2:
+		printf("Dual IO (1-2-2)");
+		break;
+	case SPI_READ_MODE_QUAD_1_4_4:
+		printf("Quad IO (1-4-4)");
+		break;
+	case SPI_READ_MODE_NORMAL_66:
+		printf("Normal read (up to 66M)");
+		break;
+	case SPI_READ_MODE_FAST:
+		printf("Fast Read");
+		break;
+	default:
+		printf("unknown<%x>mode", mode);
+	}
+}
+
+static int dump_efw(const embedded_firmware *fw_header)
+{
+	printf("EFS Generation:    %s\n", fw_header->efs_gen.gen ? "first" : "second");
+
+	printf("\nFamily 15h Models 60h-6Fh");
+	printf("\n  SPI Read Mode          ");
+	decode_spi_read_mode(fw_header->spi_readmode_f15_mod_60_6f);
+	printf("\n  SPI Frequency:         ");
+	decode_spi_frequency(fw_header->fast_speed_new_f15_mod_60_6f);
+
+	printf("\n\nFamily 17h Models 00h-0Fh, 10h-1Fh");
+	printf("\n  SPI Read Mode:         ");
+	decode_spi_read_mode(fw_header->spi_readmode_f17_mod_00_2f);
+	printf("\n  Fast Speed New:        ");
+	decode_spi_frequency(fw_header->spi_fastspeed_f17_mod_00_2f);
+	printf("\n  QPR_Dummy Cycle configure:    0x%02x\n", fw_header->qpr_dummy_cycle_f17_mod_00_2f);
+
+	printf("\nFamily 17h Models 30h-3Fh and later Families");
+	printf("\n  SPI Read Mode:         ");
+	decode_spi_read_mode(fw_header->spi_readmode_f17_mod_30_3f);
+	printf("\n  SPI Fast Speed:        ");
+	decode_spi_frequency(fw_header->spi_fastspeed_f17_mod_30_3f);
+	printf("\n  Micron Detect Flag:    0x%02x\n", fw_header->micron_detect_f17_mod_30_3f);
+	return 0;
+}
+
 enum {
 	AMDFW_OPT_HELP = 'h',
+	AMDFW_OPT_DUMP = 'd',
 	AMDFW_OPT_SOFT_FUSE = 1UL << 0, /* Print Softfuse */
 	AMDFW_OPT_RO_LIST = 1UL << 1, /* List entries in AMDFW RO */
 };
 
-static char const optstring[] = {AMDFW_OPT_HELP};
+static const char optstring[] = {AMDFW_OPT_HELP, AMDFW_OPT_DUMP};
 
 static struct option long_options[] = {
 	{"help", no_argument, 0, AMDFW_OPT_HELP},
+	{"dump", no_argument, 0, AMDFW_OPT_DUMP},
 	{"soft-fuse", no_argument, 0, AMDFW_OPT_SOFT_FUSE},
 	{"ro-list", no_argument, 0, AMDFW_OPT_RO_LIST},
 };
@@ -419,6 +525,7 @@ static void print_usage(void)
 {
 	printf("amdfwread: Examine AMD firmware images\n");
 	printf("Usage: amdfwread [options] <file>\n");
+	printf("-d | --dump                Dump Embedded Firmware Structure\n");
 	printf("--soft-fuse                Print soft fuse value\n");
 	printf("--ro-list                  List the programs under AMDFW in RO region\n");
 }
@@ -426,6 +533,7 @@ static void print_usage(void)
 int main(int argc, char **argv)
 {
 	char *fw_file = NULL;
+	int mode_dump = 0;
 
 	int selected_functions = 0;
 	while (1) {
@@ -447,6 +555,9 @@ int main(int argc, char **argv)
 		case AMDFW_OPT_HELP:
 			print_usage();
 			return 0;
+		case AMDFW_OPT_DUMP:
+			mode_dump = 1;
+			break;
 
 		case AMDFW_OPT_SOFT_FUSE:
 		case AMDFW_OPT_RO_LIST:
@@ -480,6 +591,9 @@ int main(int argc, char **argv)
 		return 1;
 	}
 
+	if (mode_dump)
+		dump_efw(&fw_header);
+
 	if (selected_functions & AMDFW_OPT_SOFT_FUSE) {
 		if (read_soft_fuse(fw, &fw_header) != 0) {
 			fclose(fw);

From 97cf4a19198475fb0ff2a944c1e2eb87f4f5f565 Mon Sep 17 00:00:00 2001
From: Alexander Goncharov <chat@joursoir.net>
Date: Mon, 4 Aug 2025 17:56:48 +0300
Subject: [PATCH 1965/3886] util/amdfwtool/amdfwread: fix offset decision for
 PSP/BIOS directory lookup
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

According to AMD documentation, starting from Family 17h Models
00h-0Fh, the PSP on-chip boot loader reads the PSP directory pointer
from offset 0x14 in the Embedded Firmware structure, replacing the
previous offset 0x10.

The docs do not specify any special value indicating a change of
offset. Some AMI binaries use a zero address in this directory field,
which caused incorrect offset handling.

Change-Id: I67ab763d070a9580a8269b525b203c932c5b1b95
Signed-off-by: Alexander Goncharov <chat@joursoir.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88868
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
---
 util/amdfwtool/amdfwread.c | 15 ++++++++-------
 1 file changed, 8 insertions(+), 7 deletions(-)

diff --git a/util/amdfwtool/amdfwread.c b/util/amdfwtool/amdfwread.c
index 7013318f81..88ccf3a78d 100644
--- a/util/amdfwtool/amdfwread.c
+++ b/util/amdfwtool/amdfwread.c
@@ -166,8 +166,8 @@ static int read_soft_fuse(FILE *fw, const embedded_firmware *fw_header)
 	size_t num_current_entries = 0;
 
 	uint32_t psp_offset = 0;
-	/* 0xffffffff indicates that the offset is in new_psp_directory */
-	if (fw_header->psp_directory != 0xffffffff)
+	/* 0xffffffff or 0x00000000 indicates that the offset is in new_psp_directory */
+	if (fw_header->psp_directory != 0xffffffff && fw_header->psp_directory != 0x00000000)
 		psp_offset = fw_header->psp_directory;
 	else
 		psp_offset = fw_header->new_psp_directory;
@@ -390,8 +390,8 @@ static int list_amdfw_psp_dir(FILE *fw, const embedded_firmware *fw_header)
 {
 	uint32_t psp_offset = 0;
 
-	/* 0xffffffff indicates that the offset is in new_psp_directory */
-	if (fw_header->psp_directory != 0xffffffff)
+	/* 0xffffffff or 0x00000000 indicates that the offset is in new_psp_directory */
+	if (fw_header->psp_directory != 0xffffffff && fw_header->psp_directory != 0x00000000)
 		psp_offset = fw_header->psp_directory;
 	else
 		psp_offset = fw_header->new_psp_directory;
@@ -403,9 +403,10 @@ static int list_amdfw_psp_dir(FILE *fw, const embedded_firmware *fw_header)
 
 static int list_amdfw_bios_dir(FILE *fw, const embedded_firmware *fw_header)
 {
-	/* 0xffffffff implies that the SoC uses recovery A/B layout. Only BIOS L2 directory
-	   is present and that too as part of PSP L2 directory. */
-	if (fw_header->bios3_entry != 0xffffffff) {
+	/* 0xffffffff or 0x00000000 implies that the SoC uses recovery A/B
+	   layout. Only BIOS L2 directory is present and that too as part of
+	   PSP L2 directory. */
+	if (fw_header->bios3_entry != 0xffffffff && fw_header->bios3_entry != 0x00000000) {
 		printf("BIOSL1: Dir  0x%08x\n", fw_header->bios3_entry);
 		amdfw_bios_dir_walk(fw, fw_header->bios3_entry, BHD_COOKIE, 0);
 	}

From 46b03e682cd9cfc166425f0200336e786bcee65c Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Micha=C5=82=20=C5=BBygowski?= <michal.zygowski@3mdeb.com>
Date: Thu, 4 Sep 2025 14:26:13 +0200
Subject: [PATCH 1966/3886] util/amdfwtool: Handle address mode properly for
 Turin
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Trying to read a firmware binary for Turin platform results in
"Invalid address(41400) or mode(0)" error. The utility does not
respect the address mode set by the directory header. The address
mode of th entries is valid only if the address mode of the directory
is equal to 2 or 3.

Check the address mode of the directory and use it for entries only
when its value is less than 2.

TEST=Successfuly parse vendor BIOS for Gigabyte MZ33-AR1.

Change-Id: I479bc846bfb334231fdc707274a8ac44b6c384d4
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89039
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Benjamin Doron <benjamin.doron00@gmail.com>
---
 util/amdfwtool/amdfwread.c | 20 +++++++++++++++++++-
 util/amdfwtool/amdfwtool.h | 22 +++++++++++++++++++---
 2 files changed, 38 insertions(+), 4 deletions(-)

diff --git a/util/amdfwtool/amdfwread.c b/util/amdfwtool/amdfwread.c
index 88ccf3a78d..ddd0bc3fb0 100644
--- a/util/amdfwtool/amdfwread.c
+++ b/util/amdfwtool/amdfwread.c
@@ -263,18 +263,27 @@ static int amdfw_bios_dir_walk(FILE *fw, uint32_t bios_offset, uint32_t cookie,
 	size_t num_current_entries = 0;
 	bios_directory_hdr header;
 	uint32_t l2_dir_offset = 0;
+	uint64_t dir_mode = 0;
 	char indent[MAX_INDENTATION_LEN] = {0};
 
 	if (read_bios_directory(fw, bios_offset, cookie, &header,
 		       &current_entries, &num_current_entries) != 0)
 		return 1;
 
+	if (header.additional_info_fields.version == 1)
+		dir_mode = header.additional_info_fields_v1.address_mode;
+	else
+		dir_mode = header.additional_info_fields.address_mode;
+
 	do_indentation_string(indent, level);
 	for (size_t i = 0; i < num_current_entries; i++) {
 		uint32_t type = current_entries[i].type;
 		uint64_t mode = current_entries[i].address_mode;
 		uint64_t addr = current_entries[i].source;
 
+		if (dir_mode < 2)
+			mode = dir_mode;
+
 		if (type == AMD_BIOS_APOB || type == AMD_BIOS_PSP_SHARED_MEM)
 			printf("%sBIOS%s: 0x%02x 0x%lx(DRAM-Address)\n",
 				indent, cookie == BHD_COOKIE ? "L1" : "L2",
@@ -313,22 +322,31 @@ static int amdfw_psp_dir_walk(FILE *fw, uint32_t psp_offset, uint32_t cookie, ui
 	uint32_t bios_dir_offset = 0;
 	uint32_t ish_dir_offset = 0;
 	ish_directory_table ish_dir;
+	uint64_t dir_mode = 0;
 	char indent[MAX_INDENTATION_LEN] = {0};
 
 	if (read_psp_directory(fw, psp_offset, cookie, &header,
 		       &current_entries, &num_current_entries) != 0)
 		return 1;
 
+	if (header.additional_info_fields.version == 1)
+		dir_mode = header.additional_info_fields_v1.address_mode;
+	else
+		dir_mode = header.additional_info_fields.address_mode;
+
 	do_indentation_string(indent, level);
 	for (size_t i = 0; i < num_current_entries; i++) {
 		uint32_t type = current_entries[i].type;
 		uint64_t mode = current_entries[i].address_mode;
 		uint64_t addr = current_entries[i].addr;
 
+		if (dir_mode < 2)
+			mode = dir_mode;
+
 		if (type == AMD_PSP_FUSE_CHAIN)
 			printf("%sPSP%s: 0x%02x 0x%lx(Soft-fuse)\n",
 				indent, cookie == PSP_COOKIE ? "L1" : "L2",
-				type, mode << 62 | addr);
+				type, (uint64_t)current_entries[i].address_mode << 62 | addr);
 		else
 			printf("%sPSP%s: 0x%02x 0x%08lx 0x%08x\n",
 				indent, cookie == PSP_COOKIE ? "L1" : "L2",
diff --git a/util/amdfwtool/amdfwtool.h b/util/amdfwtool/amdfwtool.h
index 9897721607..2327584813 100644
--- a/util/amdfwtool/amdfwtool.h
+++ b/util/amdfwtool/amdfwtool.h
@@ -210,8 +210,16 @@ typedef struct _psp_directory_header {
 			uint32_t spi_block_size:4;
 			uint32_t base_addr:15;
 			uint32_t address_mode:2;
-			uint32_t not_used:1;
+			uint32_t version:1;
 		} __attribute__((packed)) additional_info_fields;
+		struct {
+			uint32_t dir_size:16;
+			uint32_t spi_block_size:4;
+			uint32_t dir_header_size:4;
+			uint32_t address_mode:2;
+			uint32_t reserved:5;
+			uint32_t version:1;
+		} __attribute__((packed)) additional_info_fields_v1;
 	};
 } __attribute__((packed, aligned(16))) psp_directory_header;
 
@@ -272,8 +280,16 @@ typedef struct _bios_directory_hdr {
 			uint32_t spi_block_size:4;
 			uint32_t base_addr:15;
 			uint32_t address_mode:2;
-			uint32_t not_used:1;
+			uint32_t version:1;
 		} __attribute__((packed)) additional_info_fields;
+		struct {
+			uint32_t dir_size:16;
+			uint32_t spi_block_size:4;
+			uint32_t dir_header_size:4;
+			uint32_t address_mode:2;
+			uint32_t reserved:5;
+			uint32_t version:1;
+		} __attribute__((packed)) additional_info_fields_v1;
 	};
 } __attribute__((packed, aligned(16))) bios_directory_hdr;
 
@@ -459,7 +475,7 @@ typedef struct _amd_cb_config {
 typedef struct _context {
 	char *rom;		/* target buffer, size of flash device */
 	uint32_t rom_size;	/* size of flash device */
-	uint32_t address_mode;	/* 0:abs address; 1:relative to flash; 2: relative to table */
+	uint32_t address_mode;	/* 0:abs address; 1:relative to flash; 2: relative to table 3: relative to partition */
 	uint32_t current;	/* pointer within flash & proxy buffer */
 	uint32_t current_pointer_saved;
 	uint32_t current_table;

From 5cb36eb16c505cab3491c6eb6ae4eb405b32f5cd Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Thu, 4 Sep 2025 20:48:15 +0100
Subject: [PATCH 1967/3886] util/lint: Don't check for board_info.txt in common
 directory

Adjust the linter to skip `common` directories, as a board_info.txt
serves no purpose there.

This also changes `sort | uniq` to `sort -u` for efficiency.

Change-Id: I29639d8b620bcd4f2f7032802f375d79ac391535
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89050
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
---
 util/lint/lint-stable-005-board-status | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/util/lint/lint-stable-005-board-status b/util/lint/lint-stable-005-board-status
index 08cbc92c66..a772352b31 100755
--- a/util/lint/lint-stable-005-board-status
+++ b/util/lint/lint-stable-005-board-status
@@ -12,7 +12,9 @@ LINTDIR="$(
 # shellcheck source=helper_functions.sh
 . "${LINTDIR}/helper_functions.sh"
 
-for mobodir in $(${FIND_FILES} src/mainboard | sed -n 's,^\(src/mainboard/[^/]*/[^/]*\)/.*$,\1,p'|sort|uniq); do
+for mobodir in $(${FIND_FILES} src/mainboard | sed -n 's,^\(src/mainboard/[^/]*/[^/]*\)/.*$,\1,p' \
+    | grep -v '/common$' | sort -u); do
+
     board_info="$mobodir/board_info.txt"
     if ! [ -f "$board_info" ]; then
        echo "No $board_info found"

From ef1d48ee1d618a94ac5800760dd0a147c0aa951b Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Thu, 4 Sep 2025 20:50:35 +0100
Subject: [PATCH 1968/3886] util/lint: Don't check for Kconfig.name in common
 directory

`src/mainboard/*/common` doesn't need a Kconfig.name, so don't check
for one.

Change-Id: I6c69c174287f7f068e28ed9c33b9b5542c87ca60
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89051
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
---
 util/lint/lint-stable-006-board-name | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/util/lint/lint-stable-006-board-name b/util/lint/lint-stable-006-board-name
index 6f4e4b6751..6a93f4e42a 100755
--- a/util/lint/lint-stable-006-board-name
+++ b/util/lint/lint-stable-006-board-name
@@ -17,6 +17,10 @@ for i in src/mainboard/*/; do
 done
 
 for i in src/mainboard/*/*/; do
+  case "$i" in
+    */common/) continue ;;
+  esac
+
   if [ -r $i/Kconfig ]; then
     if [ ! -r $i/Kconfig.name ]; then
       BOARD="$(grep -A2 MAINBOARD_PART_NUMBER $i/Kconfig | tail -1 | cut -f2 -d\")"

From 97f9ebb5c24fda9de613ea51e6fe3784260e7704 Mon Sep 17 00:00:00 2001
From: Varun Upadhyay <varun.upadhyay@intel.com>
Date: Tue, 29 Jul 2025 09:01:53 +0530
Subject: [PATCH 1969/3886] mb/google/ocelot: Create ojal variant

Create the ojal variant of the ocelot reference board by copying the
ocelot files to a new directory named for the variant.

BUG=b:437459757
TEST=1. Build emerge-ocelot
     2. Run part_id_gen tool without any errors

Change-Id: Ic2fc86d89facae21b9bed898ebe518d316d953da
Signed-off-by: Varun Upadhyay <varun.upadhyay@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88600
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Pranava Y N <pranavayn@google.com>
---
 src/ec/google/chromeec/rtk.c                  |   6 +-
 src/mainboard/google/ocelot/Kconfig           |  17 +
 src/mainboard/google/ocelot/Kconfig.name      |   3 +
 src/mainboard/google/ocelot/bootblock.c       |   8 +
 .../baseboard/ocelot/include/baseboard/ec.h   |   3 +-
 .../baseboard/ocelot/include/baseboard/gpio.h |   2 +-
 .../google/ocelot/variants/ojal/Makefile.mk   |   6 +
 .../google/ocelot/variants/ojal/gpio.c        | 409 ++++++++++++++++++
 .../google/ocelot/variants/ojal/hda_verb.c    | 126 ++++++
 .../ocelot/variants/ojal/include/variant/ec.h |   8 +
 .../variants/ojal/include/variant/gpio.h      |  11 +
 .../google/ocelot/variants/ojal/memory.c      |  59 +++
 .../ocelot/variants/ojal/memory/Makefile.mk   |   7 +
 .../ojal/memory/dram_id.generated.txt         |   7 +
 .../variants/ojal/memory/mem_parts_used.txt   |  12 +
 .../ocelot/variants/ojal/overridetree.cb      |   5 +
 16 files changed, 685 insertions(+), 4 deletions(-)
 create mode 100644 src/mainboard/google/ocelot/variants/ojal/Makefile.mk
 create mode 100644 src/mainboard/google/ocelot/variants/ojal/gpio.c
 create mode 100644 src/mainboard/google/ocelot/variants/ojal/hda_verb.c
 create mode 100644 src/mainboard/google/ocelot/variants/ojal/include/variant/ec.h
 create mode 100644 src/mainboard/google/ocelot/variants/ojal/include/variant/gpio.h
 create mode 100644 src/mainboard/google/ocelot/variants/ojal/memory.c
 create mode 100644 src/mainboard/google/ocelot/variants/ojal/memory/Makefile.mk
 create mode 100644 src/mainboard/google/ocelot/variants/ojal/memory/dram_id.generated.txt
 create mode 100644 src/mainboard/google/ocelot/variants/ojal/memory/mem_parts_used.txt
 create mode 100644 src/mainboard/google/ocelot/variants/ojal/overridetree.cb

diff --git a/src/ec/google/chromeec/rtk.c b/src/ec/google/chromeec/rtk.c
index 96ffbe5364..bd2f87d0ed 100644
--- a/src/ec/google/chromeec/rtk.c
+++ b/src/ec/google/chromeec/rtk.c
@@ -71,7 +71,8 @@ bool chipset_emi_read_bytes(u16 port, size_t length, u8 *dest, u8 *csum)
 	printk(BIOS_DEBUG, "RTS5915: read port 0x%x, size %zu\n", port, length);
 
 	if (port >= EMI_RANGE_START && port <= EMI_RANGE_END) {
-		uint8_t *p = (uint8_t *)(HOSTCMD_PARAM_MEM_BASE + (port - EMI_RANGE_START));
+		uint8_t *p = (uint8_t *)(uintptr_t)(HOSTCMD_PARAM_MEM_BASE
+				+ (port - EMI_RANGE_START));
 		for (i = 0; i < length; ++i) {
 			dest[i] = p[i];
 			if (csum)
@@ -91,7 +92,8 @@ bool chipset_emi_write_bytes(u16 port, size_t length, u8 *msg, u8 *csum)
 	printk(BIOS_DEBUG, "RTS5915: write port 0x%x, size %zu\n", port, length);
 
 	if (port >= EMI_RANGE_START && port <= EMI_RANGE_END) {
-		uint8_t *p = (uint8_t *)(HOSTCMD_PARAM_MEM_BASE + (port - EMI_RANGE_START));
+		uint8_t *p = (uint8_t *)(uintptr_t)(HOSTCMD_PARAM_MEM_BASE
+				+ (port - EMI_RANGE_START));
 		for (i = 0; i < length; ++i) {
 			p[i] = msg[i];
 			if (csum)
diff --git a/src/mainboard/google/ocelot/Kconfig b/src/mainboard/google/ocelot/Kconfig
index bfcb9af577..131948e44a 100644
--- a/src/mainboard/google/ocelot/Kconfig
+++ b/src/mainboard/google/ocelot/Kconfig
@@ -64,6 +64,16 @@ config BOARD_GOOGLE_MODEL_OCELOT
 	select DRIVERS_INTEL_TOUCH
 	select FSP_UGOP_EARLY_SIGN_OF_LIFE
 
+config BOARD_GOOGLE_MODEL_OJAL
+	def_bool n
+	select BOARD_GOOGLE_BASEBOARD_OCELOT
+	select DRIVERS_GENERIC_BAYHUB_LV2
+	select DRIVERS_GENERIC_MAX98357A
+	select DRIVERS_INTEL_TOUCH
+	select FSP_UGOP_EARLY_SIGN_OF_LIFE
+	select EC_GOOGLE_CHROMEEC_RTK
+	select EC_GOOGLE_CHROMEEC_LPC_GENERIC_MEMORY_RANGE
+
 config BOARD_GOOGLE_OCELOT
 	select BOARD_GOOGLE_MODEL_OCELOT
 
@@ -84,6 +94,9 @@ config BOARD_GOOGLE_OCELOTMCHP4ES
 	select BOARD_GOOGLE_MODEL_OCELOT
 	select EC_GOOGLE_CHROMEEC_MEC
 
+config BOARD_GOOGLE_OJAL
+	select BOARD_GOOGLE_MODEL_OJAL
+
 if BOARD_GOOGLE_OCELOT_COMMON
 
 config BASEBOARD_DIR
@@ -118,6 +131,7 @@ config DRIVER_TPM_I2C_ADDR
 config DRIVER_TPM_I2C_BUS
 	hex
 	default 0x01 if BOARD_GOOGLE_MODEL_OCELOT
+	default 0x01 if BOARD_GOOGLE_MODEL_OJAL
 
 config HAVE_SLP_S0_GATE
 	def_bool n
@@ -131,6 +145,7 @@ config MAINBOARD_FAMILY
 
 config MAINBOARD_PART_NUMBER
 	default "Ocelot" if BOARD_GOOGLE_MODEL_OCELOT
+	default "Ojal" if BOARD_GOOGLE_OJAL
 
 config MEMORY_SOLDERDOWN
 	def_bool n
@@ -140,6 +155,7 @@ config MEMORY_SOLDERDOWN
 config TPM_TIS_ACPI_INTERRUPT
 	int
 	default 49 if BOARD_GOOGLE_MODEL_OCELOT # GPE0_DW1_17 (GPP_B17)
+	default 49 if BOARD_GOOGLE_MODEL_OJAL # GPE0_DW1_17 (GPP_B17)
 
 config UART_FOR_CONSOLE
 	int
@@ -151,6 +167,7 @@ config USE_PM_ACPI_TIMER
 config VARIANT_DIR
 	string
 	default "ocelot" if BOARD_GOOGLE_MODEL_OCELOT
+	default "ojal" if BOARD_GOOGLE_MODEL_OJAL
 
 config OVERRIDE_DEVICETREE
 	default "variants/\$(CONFIG_VARIANT_DIR)/overridetree.cb"
diff --git a/src/mainboard/google/ocelot/Kconfig.name b/src/mainboard/google/ocelot/Kconfig.name
index 71a69cb31a..2645d9c7f0 100644
--- a/src/mainboard/google/ocelot/Kconfig.name
+++ b/src/mainboard/google/ocelot/Kconfig.name
@@ -11,6 +11,9 @@ config BOARD_GOOGLE_OCELOTITE
 config BOARD_GOOGLE_OCELOTMCHP
 	bool "-> Ocelotmchp"
 
+config BOARD_GOOGLE_OJAL
+	bool "-> Ojal"
+
 config BOARD_GOOGLE_OCELOT4ES
 	bool "-> Ocelot4ES"
 
diff --git a/src/mainboard/google/ocelot/bootblock.c b/src/mainboard/google/ocelot/bootblock.c
index 6ee655ee58..e414937b83 100644
--- a/src/mainboard/google/ocelot/bootblock.c
+++ b/src/mainboard/google/ocelot/bootblock.c
@@ -2,6 +2,7 @@
 
 #include <baseboard/variants.h>
 #include <bootblock_common.h>
+#include <intelblocks/lpc_lib.h>
 
 void bootblock_mainboard_early_init(void)
 {
@@ -11,3 +12,10 @@ void bootblock_mainboard_early_init(void)
 	pads = variant_early_gpio_table(&num);
 	gpio_configure_pads(pads, num);
 }
+
+void bootblock_mainboard_init(void)
+{
+	if (CONFIG(EC_GOOGLE_CHROMEEC_LPC_GENERIC_MEMORY_RANGE))
+		lpc_open_mmio_window(CONFIG_EC_GOOGLE_CHROMEEC_LPC_GENERIC_MEMORY_BASE,
+			CONFIG_EC_GOOGLE_CHROMEEC_LPC_GENERIC_MEMORY_SIZE);
+}
diff --git a/src/mainboard/google/ocelot/variants/baseboard/ocelot/include/baseboard/ec.h b/src/mainboard/google/ocelot/variants/baseboard/ocelot/include/baseboard/ec.h
index 1302946b93..aa8f052b47 100644
--- a/src/mainboard/google/ocelot/variants/baseboard/ocelot/include/baseboard/ec.h
+++ b/src/mainboard/google/ocelot/variants/baseboard/ocelot/include/baseboard/ec.h
@@ -75,7 +75,8 @@
 /* Enable EC backed PD MCU device in ACPI */
 #define EC_ENABLE_PD_MCU_DEVICE
 
-#if !CONFIG(BOARD_GOOGLE_OCELOT) && !CONFIG(BOARD_GOOGLE_OCELOT4ES)
+#if !CONFIG(BOARD_GOOGLE_OCELOT) && !CONFIG(BOARD_GOOGLE_OCELOT4ES) && \
+!CONFIG(BOARD_GOOGLE_OJAL)
  #define EC_ENABLE_SYNC_IRQ      /* Enable tight timestamp / wake support */
  #define EC_SYNC_IRQ_WAKE_CAPABLE /* Let the OS know ec_sync is wake capable */
 #endif
diff --git a/src/mainboard/google/ocelot/variants/baseboard/ocelot/include/baseboard/gpio.h b/src/mainboard/google/ocelot/variants/baseboard/ocelot/include/baseboard/gpio.h
index cf5924634d..e72f1ba74d 100644
--- a/src/mainboard/google/ocelot/variants/baseboard/ocelot/include/baseboard/gpio.h
+++ b/src/mainboard/google/ocelot/variants/baseboard/ocelot/include/baseboard/gpio.h
@@ -13,7 +13,7 @@
  * GPIO_PCH_WP - WP signal to PCH
  */
 //TODO for Nuvo: #define EC_SYNC_IRQ	GPP_E07_IRQ
-#if CONFIG(BOARD_GOOGLE_MODEL_OCELOT)
+#if CONFIG(BOARD_GOOGLE_MODEL_OCELOT) || CONFIG(BOARD_GOOGLE_MODEL_OJAL)
  #define EC_SYNC_IRQ	0 /* Not Connected */
 #endif
 #define GPIO_PCH_WP	GPP_D02
diff --git a/src/mainboard/google/ocelot/variants/ojal/Makefile.mk b/src/mainboard/google/ocelot/variants/ojal/Makefile.mk
new file mode 100644
index 0000000000..4c33dad4db
--- /dev/null
+++ b/src/mainboard/google/ocelot/variants/ojal/Makefile.mk
@@ -0,0 +1,6 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
+bootblock-y += gpio.c
+romstage-y += gpio.c
+romstage-y += memory.c
+ramstage-y += gpio.c
diff --git a/src/mainboard/google/ocelot/variants/ojal/gpio.c b/src/mainboard/google/ocelot/variants/ojal/gpio.c
new file mode 100644
index 0000000000..dcef9f7579
--- /dev/null
+++ b/src/mainboard/google/ocelot/variants/ojal/gpio.c
@@ -0,0 +1,409 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <baseboard/gpio.h>
+#include <baseboard/variants.h>
+#include <boardid.h>
+#include <soc/gpio.h>
+
+/* Pad configuration in ramstage*/
+static const struct pad_config gpio_table[] = {
+	/* GPP_A */
+	/* GPP_A00:     ESPI_IO0_AIC */
+	/*  GPP_A00 : GPP_A00 ==> ESPI_IO0_EC_R configured on reset, do not touch */
+
+	/* GPP_A01:     ESPI_IO1_AIC */
+	/*  GPP_A01 : GPP_A01 ==> ESPI_IO1_EC_R configured on reset, do not touch */
+
+	/* GPP_A02:     ESPI_IO2_AIC */
+	/*  GPP_A02 : GPP_A02 ==> ESPI_IO2_EC_R configured on reset, do not touch */
+
+	/* GPP_A03:     ESPI_IO3_AIC */
+	/*  GPP_A03 : GPP_A03 ==> ESPI_IO3_EC_R configured on reset, do not touch */
+
+	/* GPP_A04:     ESPI_CS0_AIC_N */
+	/*  GPP_A04 : GPP_A04 ==> ESPI_CS0_HDR_L configured on reset, do not touch */
+
+	/* GPP_A05:     ESPI_CLK_AIC */
+	/*  GPP_A05 : GPP_A05 ==> ESPI_CLK_HDR configured on reset, do not touch */
+
+	/* GPP_A06:     ESPI_RST_AIC_N */
+	/*  GPP_A06 : GPP_A06 ==> ESPI_RST_HDR configured on reset, do not touch */
+
+	/* GPP_A08:     M2_GEN4_SSD_RESET_N */
+	PAD_CFG_GPO(GPP_A08, 1, PLTRST),
+	/* GPP_A09:     M.2_WWAN_FCP_OFF_N */
+	PAD_CFG_GPO(GPP_A09, 1, PLTRST),
+	/* GPP_A10:     WWAN_DISABLE_N */
+	PAD_CFG_GPO(GPP_A10, 1, PLTRST),
+	/* GPP_A11:     WLAN_RST_N */
+	PAD_CFG_GPO(GPP_A11, 1, PLTRST),
+	/* GPP_A12:     WIFI_WAKE_N */
+	PAD_CFG_GPI_SCI_LOW(GPP_A12, NONE, DEEP, LEVEL),
+	/* GPP_A13:     PCIE_LNK_DOWN */
+	PAD_CFG_NF_OWNERSHIP(GPP_A13, NONE, DEEP, NF2, ACPI),
+	/* GPP_A15:     CODEC_GPIO_EN */
+	PAD_CFG_GPO(GPP_A15, 1, DEEP),
+
+	/* GPP_B */
+	/* GPP_B00:     USBC_SML_CLK_PD */
+	PAD_CFG_NF(GPP_B00, NONE, DEEP, NF1),
+	/* GPP_B01:     USBC_SML_DATA_PD */
+	PAD_CFG_NF(GPP_B01, NONE, DEEP, NF1),
+	/* GPP_B02:     ISH_I2C0_SDA_SNSR_HDR */
+	PAD_NC(GPP_B02, NONE),
+	/* GPP_B03:     ISH_I2C0_SCL_SNSR_HDR */
+	PAD_NC(GPP_B03, NONE),
+	/* GPP_B04:     ISH_GP_0_SNSR_HDR */
+	PAD_NC(GPP_B04, NONE),
+	/* GPP_B06:     SOC_PDB_CTRL */
+	PAD_CFG_GPO(GPP_B06, 0, DEEP),
+	/* GPP_B08:     ISH_GP_4_SNSR_HDR */
+	PAD_NC(GPP_B08, NONE),
+	/* GPP_B09:     BT_RF_KILL_N */
+	PAD_CFG_GPO(GPP_B09, 1, DEEP),
+	/* GPP_B10:     NC */
+	PAD_NC(GPP_B10, NONE),
+	/* GPP_B12:     PM_SLP_S0_N */
+	PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1),
+	/* GPP_B13:     PLT_RST_N */
+	PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1),
+	/* GPP_B14:     GPP_B14_DDSP_HPDB */
+	PAD_CFG_NF(GPP_B14, NONE, DEEP, NF2),
+	/* GPP_B16:     COINLESS_MODE_SELECT */
+	PAD_CFG_GPI(GPP_B16, NONE, DEEP),
+	/* GPP_B17:     SPI_TPM_INT_N */
+	PAD_CFG_GPI_APIC_LOCK(GPP_B17, NONE, LEVEL, INVERT, LOCK_CONFIG),
+	/* GPP_B20:     WWAN_RST_N */
+	PAD_CFG_GPO(GPP_B20, 1, PLTRST),
+	/* GPP_B21:     TCP_RETIMER_FORCE_PWR */
+	PAD_CFG_GPO(GPP_B21, 0, DEEP),
+	/* GPP_B24:     ESPI_ALERT0_EC_R_N */
+	PAD_NC(GPP_B24, NONE),
+	/* GPP_B25:     None */
+	PAD_NC(GPP_B25, NONE),
+
+	/* GPP_C */
+	/* GPP_C00:     SPD_SMB_CLK */
+	PAD_CFG_NF(GPP_C00, NONE, DEEP, NF1),
+	/* GPP_C01:     SPD_SMB_DATA */
+	PAD_CFG_NF(GPP_C01, NONE, DEEP, NF1),
+	/* GPP_C02:     NC */
+	PAD_NC(GPP_C02, NONE),
+	/* GPP_C03:     TCP_LAN_SML0_SCL_R */
+	PAD_CFG_NF(GPP_C03, NONE, DEEP, NF1),
+	/* GPP_C04:     TCP_LAN_SML0_SDA_R */
+	PAD_CFG_NF(GPP_C04, NONE, DEEP, NF1),
+	/* GPP_C05:     NC */
+	PAD_NC(GPP_C05, NONE),
+	/* GPP_C06:     NC */
+	PAD_NC(GPP_C06, NONE),
+	/* GPP_C07:     NC */
+	PAD_NC(GPP_C07, NONE),
+	/* GPP_C08:     PM_SLP_S0_N_GPP_CNTRL */
+	PAD_CFG_GPO(GPP_C08, 1, PLTRST),
+	/* GPP_C09:     CLKREQ0_X1_GEN4_M2_WLAN_N */
+	PAD_CFG_NF(GPP_C09, NONE, DEEP, NF1),
+	/* GPP_C10:     WIFI_RF_KILL_N */
+	PAD_CFG_GPO(GPP_C10, 1, DEEP),
+	/* GPP_C11:     CLKREQ2_X4_GEN4_DT_CEM_SLOT1_N */
+	PAD_CFG_NF(GPP_C11, NONE, DEEP, NF1),
+	/* GPP_C12:     CLKREQ3_X4_GEN4_M2_SSD_N */
+	PAD_CFG_NF(GPP_C12, NONE, DEEP, NF1),
+	/* GPP_C13:     CLKREQ4_X4_GEN4_DT_CEM_SLOT2_N */
+	PAD_CFG_NF(GPP_C13, NONE, DEEP, NF1),
+	/* GPP_C14:     CLKREQ5_X1_GEN1_GBE_LAN_N */
+	PAD_CFG_NF(GPP_C14, NONE, DEEP, NF1),
+	/* GPP_C15:     FPS_RST_N */
+	PAD_CFG_GPO_LOCK(GPP_C15, 1, LOCK_CONFIG),
+	/* GPP_C16:     MOD_TCSS1_LS_TX_DDC_SCL */
+	PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1),
+	/* GPP_C17:     MOD_TCSS1_LS_RX_DDC_SDA */
+	PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1),
+	/* GPP_C18:     MOD_TCSS2_LS_TX_DDC_SCL */
+	PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1),
+	/* GPP_C19:     MOD_TCSS2_LS_RX_DDC_SDA */
+	PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1),
+	/* GPP_C22:     DDPB_HDMI_CTRLCLK */
+	PAD_CFG_NF(GPP_C22, NONE, DEEP, NF2),
+	/* GPP_C23:     DDPB_HDMI_CTRLDATA */
+	PAD_CFG_NF(GPP_C23, NONE, DEEP, NF2),
+
+	/* GPP_D */
+	/* GPP_D01:     MOD_TCSS1_TYP_A_VBUS_EN */
+	PAD_CFG_GPO(GPP_D01, 1, DEEP),
+	/* GPP_D02:     SOC_WP_OD */
+	PAD_CFG_GPO(GPP_D02, 0, DEEP),
+	/* GPP_D03:     X4_SLOT_WAKE_N */
+	PAD_CFG_GPI_SCI_LOW(GPP_D03, NONE, DEEP, LEVEL),
+	/* GPP_D07:     ISH_UART0_RTS_N_SNSR_HDR */
+	PAD_NC(GPP_D07, NONE),
+	/* GPP_D08:     ISH_UART0_CTS_N_SNSR_HDR */
+	PAD_NC(GPP_D08, NONE),
+	/* GPP_D09:     I2S_MCLK_HDR */
+	PAD_CFG_NF(GPP_D09, NONE, DEEP, NF1),
+	/* GPP_D10:     HDA_BCLK (HDR) */
+	PAD_CFG_NF(GPP_D10, NONE, DEEP, NF1),
+	/* GPP_D11:     HDA_SYNC (HDR) */
+	PAD_CFG_NF(GPP_D11, NONE, DEEP, NF1),
+	/* GPP_D12:     HDA_SDO (HDR) */
+	PAD_CFG_NF(GPP_D12, NONE, DEEP, NF1),
+	/* GPP_D13:     HDA_SDI0 (HDR) */
+	PAD_CFG_NF(GPP_D13, NONE, DEEP, NF1),
+	/* GPP_D16:     HDA_RST_N (HDR) */
+	PAD_CFG_NF(GPP_D16, NONE, DEEP, NF1),
+	/* GPP_D17:     HDA_SDI1 (HDR) */
+	PAD_CFG_NF(GPP_D17, NONE, DEEP, NF1),
+	/* GPP_D19:     NC */
+	PAD_NC(GPP_D19, NONE),
+	/* GPP_D21:     GPP_D21_UFS_REFCLK_R */
+	PAD_CFG_NF(GPP_D21, NONE, DEEP, NF1),
+
+	/* GPP_E */
+	/* GPP_E01:     PM_SLP_DRAM_N */
+	PAD_CFG_NF(GPP_E01, NONE, DEEP, NF2),
+	/* GPP_E02:     NC */
+	PAD_NC(GPP_E02, NONE),
+	/* GPP_E03:     X4_DT_PCIE_RST_N */
+	PAD_CFG_GPO(GPP_E03, 1, PLTRST),
+	/* GPP_E05:     GPP_E5_FPS_PWREN */
+	PAD_CFG_GPO(GPP_E05, 1, DEEP),
+	/* GPP_E06:     GPP_E6_PEN_DETECT */
+	PAD_CFG_GPI_TRIG_OWN(GPP_E06, NONE, DEEP, LEVEL, ACPI),
+	/* GPP_E07:     LAN_GPIO_RST_N */
+	PAD_CFG_GPO(GPP_E07, 1, PLTRST),
+	/* GPP_E08:     EC_SOC_INT_ODL */
+	PAD_CFG_GPI(GPP_E08, NONE, DEEP),
+	/* GPP_E09:     USB_FP_CONN_1_CONN_2_OC0_N */
+	PAD_CFG_NF(GPP_E09, NONE, DEEP, NF1),
+	/* GPP_E10:     M2_UFS_DET_SEL_N */
+	PAD_CFG_GPI(GPP_E10, NONE, DEEP),
+	/* GPP_E11:     THC0_SPI1_CLK_TCH_PNL1 */
+	PAD_CFG_NF(GPP_E11, NONE, DEEP, NF3),
+	/* GPP_E12:     THC_I2C0_SCL_TCH_PNL1 */
+	PAD_CFG_NF(GPP_E12, NONE, DEEP, NF3),
+	/* GPP_E13:     THC_I2C0_SDA_TCH_PNL1 */
+	PAD_CFG_NF(GPP_E13, NONE, DEEP, NF3),
+	/* GPP_E14:     THC0_SPI1_IO_2_TCH_PNL1 */
+	PAD_CFG_NF(GPP_E14, NONE, DEEP, NF3),
+	/* GPP_E15:     THC0_SPI1_IO_3_TCH_PNL1 */
+	PAD_CFG_NF(GPP_E15, NONE, DEEP, NF3),
+	/* GPP_E16:     THC0_SPI1_RST_N_TCH_PNL1 */
+	PAD_CFG_NF(GPP_E16, NONE, PLTRST, NF1),
+	/* GPP_E17:     GPP_E17_GSPI0A_CS0 */
+	PAD_CFG_NF(GPP_E17, NONE, DEEP, NF5),
+	/* GPP_E18:     THC0_SPI1_INT_N_TCH_PNL1 */
+	PAD_CFG_NF(GPP_E18, NONE, DEEP, NF3),
+	/* GPP_E19:     FPS_INT_N */
+	PAD_CFG_GPI_IRQ_WAKE(GPP_E19, NONE, PWROK, LEVEL, INVERT),
+	/* GPP_E20:     FPS_FW_UPDATE */
+	PAD_CFG_GPO_LOCK(GPP_E20, 0, LOCK_CONFIG),
+	/* GPP_E21:     I2C_PMC_PD_INT_N */
+	PAD_CFG_NF(GPP_E21, NONE, DEEP, NF1),
+	/* GPP_E22:     NC */
+	PAD_NC(GPP_E22, NONE),
+
+	/* GPP_F */
+	/* GPP_F00:     M.2_CNV_BRI_DT_BT_UART2_RTS_N */
+	PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_F00, NONE, DEEP, NF1),
+	/* GPP_F01:     M.2_CNV_BRI_RSP_BT_UART2_RXD */
+	PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_F01, NONE, DEEP, NF1),
+	/* GPP_F02:     M.2_CNV_RGI_DT_BT_UART2_TXD */
+	PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_F02, NONE, DEEP, NF1),
+	/* GPP_F03:     M.2_CNV_RGI_RSP_BT_UART2_CTS_N */
+	PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_F03, NONE, DEEP, NF1),
+	/* GPP_F04:     CNV_RF_RESET_R_N */
+	PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_F04, NONE, DEEP, NF1),
+	/* GPP_F05:     CRF_CLKREQ_R */
+	PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_F05, NONE, DEEP, NF3),
+	/* GPP_F06:     DISC_WLAN_WWAN_COEX3 */
+	PAD_CFG_NF(GPP_F06, NONE, DEEP, NF1),
+	/* GPP_F07:     FUSA_DIAGTEST_EN_HDR */
+	PAD_CFG_NF(GPP_F07, NONE, DEEP, NF2),
+	/* GPP_F08:     TCH_PNL1_PWR_EN */
+	PAD_CFG_GPO(GPP_F08, 1, PLTRST),
+	/* GPP_F09:     M2_UFS_RST_N */
+	PAD_CFG_GPO(GPP_F09, 1, DEEP),
+	/* GPP_F10:     X4_PCIE_SLOT1_PWR_EN */
+	PAD_CFG_GPO(GPP_F10, 1, PLTRST),
+	/* GPP_F11:     THC1_SPI2_CLK_TCH_PNL2 */
+	PAD_CFG_NF(GPP_F11, NONE, DEEP, NF11),
+	/* GPP_F12:     THC_I2C1_SCL_TCH_PAD */
+	PAD_CFG_NF(GPP_F12, NONE, DEEP, NF8),
+	/* GPP_F13:     THC_I2C1_SDA_TCH_PAD */
+	PAD_CFG_NF(GPP_F13, NONE, DEEP, NF8),
+	/* GPP_F14:     GPP_F14_GPSI0A_MOSI */
+	PAD_CFG_NF(GPP_F14, NONE, DEEP, NF8),
+	/* GPP_F15:     GPP_F15_GSPI0A_MISO */
+	PAD_CFG_NF(GPP_F15, NONE, DEEP, NF8),
+	/* GPP_F16:     GPP_F16_GSPI0A_CLK */
+	PAD_CFG_NF(GPP_F16, NONE, DEEP, NF8),
+	/* GPP_F17:     CODEC_IRQ_HDR */
+	PAD_CFG_GPI(GPP_F17, NONE, DEEP),
+	/* GPP_F18:     TCH_PAD_INT_N */
+	PAD_CFG_GPI_APIC_DRIVER(GPP_F18, NONE, PLTRST, EDGE_SINGLE, INVERT),
+	/* GPP_F19:     NC */
+	PAD_NC(GPP_F19, NONE),
+	/* GPP_F20:     CSE_EARLY_SW */
+	PAD_CFG_GPI(GPP_F20, NONE, DEEP),
+	/* GPP_F22:     THC1_SPI2_DSYNC */
+	PAD_CFG_NF(GPP_F22, NONE, DEEP, NF3),
+
+	/* GPP_H */
+	/* GPP_H00:     NC */
+	PAD_NC(GPP_H00, NONE),
+	/* GPP_H01:     M2_UFS_SLP_N */
+	PAD_CFG_GPO(GPP_H01, 1, DEEP),
+	/* GPP_H02:     DEBUG_TRACE_PNP */
+	PAD_CFG_GPO(GPP_H02, 1, PLTRST),
+	/* GPP_H03:     MIC MUTE */
+	PAD_CFG_NF(GPP_H03, NONE, DEEP, NF1),
+	/* GPP_H04:     CNV_MFUART2_RXD */
+	PAD_CFG_NF(GPP_H04, NONE, DEEP, NF1),
+	/* GPP_H05:     CNV_MFUART2_TXD */
+	PAD_CFG_NF(GPP_H05, NONE, DEEP, NF1),
+	/* GPP_H06:     I2C3_SCL_AUDIO_HDR */
+	PAD_CFG_NF(GPP_H06, NONE, DEEP, NF1),
+	/* GPP_H07:     I2C3_SDA_AUDIO_HDR */
+	PAD_CFG_NF(GPP_H07, NONE, DEEP, NF1),
+	/* GPP_H08:     SOC_BIOS_LOG_TTK_UART_RX */
+	PAD_CFG_NF(GPP_H08, NONE, DEEP, NF1),
+	/* GPP_H09:     SOC_BIOS_LOG_TTK_UART_TX */
+	PAD_CFG_NF(GPP_H09, NONE, DEEP, NF1),
+	/* GPP_H10:     UART0_BUF_RTS */
+	PAD_CFG_NF(GPP_H10, NONE, DEEP, NF1),
+	/* GPP_H11:     UART0_BUF_CTS */
+	PAD_CFG_NF(GPP_H11, NONE, DEEP, NF1),
+	/* GPP_H13:     CPU_C10_GATE_N_R */
+	PAD_CFG_NF(GPP_H13, NONE, DEEP, NF1),
+	/* GPP_H14:     ISH_I3C1_SDA_SNSR_HDR */
+	PAD_NC(GPP_H14, NONE),
+	/* GPP_H15:     ISH_I3C1_SCL_SNSR_HDR */
+	PAD_NC(GPP_H15, NONE),
+	/* GPP_H17:     MIC MUTE LED */
+	PAD_CFG_NF(GPP_H17, NONE, DEEP, NF1),
+	/* GPP_H18:     GEN4_SSD_PWREN */
+	PAD_CFG_GPO(GPP_H18, 1, DEEP),
+	/* GPP_H19:     I3C0_SDA_HDR */
+	PAD_CFG_NF(GPP_H19, NONE, DEEP, NF2),
+	/* GPP_H20:     I3C0_SCL_HDR */
+	PAD_CFG_NF(GPP_H20, NONE, DEEP, NF2),
+	/* GPP_H21:     I2C1_SDA_TTK_CHROME */
+	PAD_CFG_NF(GPP_H21, NONE, DEEP, NF1),
+	/* GPP_H22:     I2C1_SCL_TTK_CHROME */
+	PAD_CFG_NF(GPP_H22, NONE, DEEP, NF1),
+	/* GPP_H23:     TP */
+	PAD_CFG_NF(GPP_H23, NONE, DEEP, NF1),
+	/* GPP_H24:     TP */
+	PAD_CFG_NF(GPP_H24, NONE, DEEP, NF1),
+
+	/* GPP_S */
+	/* GPP_S00:     SNDW3_CLK_CODEC (HDR) */
+	PAD_CFG_NF(GPP_S00, NONE, DEEP, NF1),
+	/* GPP_S01:     SNDW3_DATA0_CODEC (HDR) */
+	PAD_CFG_NF(GPP_S01, NONE, DEEP, NF1),
+	/* GPP_S02:     SNDW3_DATA1_CODEC (HDR) */
+	PAD_CFG_NF(GPP_S02, NONE, DEEP, NF1),
+	/* GPP_S03:     SNDW3_DATA2_CODEC (HDR) */
+	PAD_CFG_NF(GPP_S03, NONE, DEEP, NF1),
+	/* GPP_S04:     DMIC0_CLK (HDR) */
+	PAD_CFG_NF(GPP_S04, NONE, DEEP, NF5),
+	/* GPP_S05:     DMIC0_DATA (HDR) */
+	PAD_CFG_NF(GPP_S05, NONE, DEEP, NF5),
+	/* GPP_S06:     DMIC1_CLK (HDR) */
+	PAD_CFG_NF(GPP_S06, NONE, DEEP, NF5),
+	/* GPP_S07:     DMIC1_DATA (HDR) */
+	PAD_CFG_NF(GPP_S07, NONE, DEEP, NF5),
+
+	/* GPP_V */
+	/* GPP_V00:     PM_BATLOW_N */
+	PAD_CFG_NF(GPP_V00, NONE, DEEP, NF1),
+	/* GPP_V01:     BC_ACOK_MCP */
+	PAD_CFG_NF(GPP_V01, NONE, DEEP, NF1),
+	/* GPP_V02:     LANWAKE_N_R */
+	PAD_CFG_NF(GPP_V02, NONE, DEEP, NF1),
+	/* GPP_V03:     PWRBTN_MCP_N */
+	PAD_CFG_NF(GPP_V03, NONE, DEEP, NF1),
+	/* GPP_V04:     PM_SLP_S3_N */
+	PAD_CFG_NF(GPP_V04, NONE, DEEP, NF1),
+	/* GPP_V05:     PM_SLP_S4_N */
+	PAD_CFG_NF(GPP_V05, NONE, DEEP, NF1),
+	/* GPP_V06:     PM_SLP_A_N */
+	PAD_CFG_NF(GPP_V06, NONE, DEEP, NF1),
+	/* GPP_V07:     M.2_BTWIFI_SUS_CLK_LS */
+	PAD_CFG_NF(GPP_V07, NONE, DEEP, NF1),
+	/* GPP_V08:     SLP_WLAN_N */
+	PAD_CFG_NF(GPP_V08, NONE, DEEP, NF1),
+	/* GPP_V09:     PM_SLP_S5_N */
+	PAD_CFG_NF(GPP_V09, NONE, DEEP, NF1),
+	/* GPP_V10:     LANPHYPC_R_N */
+	PAD_CFG_NF(GPP_V10, NONE, DEEP, NF1),
+	/* GPP_V11:     PM_SLP_LAN_N */
+	PAD_CFG_NF(GPP_V11, NONE, DEEP, NF1),
+	/* GPP_V12:     WAKE_N */
+	PAD_CFG_NF(GPP_V12, NONE, DEEP, NF1),
+	/* GPP_V13:     GPP_V13_CATERR_N */
+	PAD_CFG_NF(GPP_V13, NONE, DEEP, NF1),
+	/* GPP_V14:     GPP_V14_FORCEPR_N */
+	PAD_CFG_NF(GPP_V14, NONE, DEEP, NF1),
+	/* GPP_V15:     GPP_V15_THERMTRIP_N */
+	PAD_CFG_NF(GPP_V15, NONE, DEEP, NF1),
+	/* GPP_V16:     GPP_V16_VCCST_EN */
+	PAD_CFG_NF(GPP_V16, NONE, DEEP, NF1),
+};
+
+/* Early pad configuration in bootblock */
+static const struct pad_config early_gpio_table[] = {
+	/* GPP_B17:     SPI_TPM_INT_N */
+	PAD_CFG_GPI_APIC(GPP_B17, NONE, DEEP, LEVEL, INVERT),
+	/* GPP_H06: I2C3_SDA_PSS */
+	PAD_CFG_NF(GPP_H06, NONE, DEEP, NF1),
+	/* GPP_H07: I2C3_SCL_PSS */
+	PAD_CFG_NF(GPP_H07, NONE, DEEP, NF1),
+	/* GPP_H08:     SOC_BIOS_LOG_TTK_UART_RX */
+	PAD_CFG_NF(GPP_H08, NONE, DEEP, NF1),
+	/* GPP_H09:     SOC_BIOS_LOG_TTK_UART_TX */
+	PAD_CFG_NF(GPP_H09, NONE, DEEP, NF1),
+	/* GPP_H21:     I2C1_SDA_TTK_CHROME */
+	PAD_CFG_NF(GPP_H21, NONE, DEEP, NF1),
+	/* GPP_H22:     I2C1_SCL_TTK_CHROME */
+	PAD_CFG_NF(GPP_H22, NONE, DEEP, NF1),
+};
+
+/* Pad configuration in romstage */
+static const struct pad_config romstage_gpio_table[] = {
+	/* GPP_C00:     SPD_SMB_CLK */
+	PAD_CFG_NF(GPP_C00, NONE, DEEP, NF1),
+	/* GPP_C01:     SPD_SMB_DATA */
+	PAD_CFG_NF(GPP_C01, NONE, DEEP, NF1),
+	/* GPP_C15:     FPS_RST_N */
+	PAD_CFG_GPO(GPP_C15, 0, PLTRST),
+};
+
+const struct pad_config *variant_gpio_table(size_t *num)
+{
+	*num = ARRAY_SIZE(gpio_table);
+	return gpio_table;
+}
+
+const struct pad_config *variant_early_gpio_table(size_t *num)
+{
+	*num = ARRAY_SIZE(early_gpio_table);
+	return early_gpio_table;
+}
+
+/* Create the stub for romstage gpio, typically use for power sequence */
+const struct pad_config *variant_romstage_gpio_table(size_t *num)
+{
+	*num = ARRAY_SIZE(romstage_gpio_table);
+	return romstage_gpio_table;
+}
+
+static const struct cros_gpio cros_gpios[] = {
+	CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE0_NAME),
+	CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE1_NAME),
+	CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE2_NAME),
+	CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE3_NAME),
+	CROS_GPIO_WP_AH(GPIO_PCH_WP, CROS_GPIO_DEVICE4_NAME),
+};
+
+DECLARE_CROS_GPIOS(cros_gpios);
diff --git a/src/mainboard/google/ocelot/variants/ojal/hda_verb.c b/src/mainboard/google/ocelot/variants/ojal/hda_verb.c
new file mode 100644
index 0000000000..2f703b78ee
--- /dev/null
+++ b/src/mainboard/google/ocelot/variants/ojal/hda_verb.c
@@ -0,0 +1,126 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <device/azalia_device.h>
+
+const u32 cim_verb_data[] = {
+	/* coreboot specific header */
+	0x10ec0256,	/* Codec Vendor / Device ID: Realtek ALC256 */
+	0x10ec12ac,	/* Subsystem ID */
+	0x00000013,	/* Number of jacks (NID entries) */
+
+	AZALIA_RESET(0x1),
+	/* NID 0x01, HDA Codec Subsystem ID Verb Table */
+	AZALIA_SUBVENDOR(0, 0x10ec12ac),
+
+	/* Pin Widget Verb Table */
+	/*
+	 * DMIC
+	 * Requirement is to use PCH DMIC. Hence,
+	 * commented out codec's Internal DMIC.
+	 * AZALIA_PIN_CFG(0, 0x12, 0x90A60130),
+	 * AZALIA_PIN_CFG(0, 0x13, 0x40000000),
+	 */
+	/* Pin widget 0x14 - Front (Port-D) */
+	AZALIA_PIN_CFG(0, 0x14, 0x90170110),
+	/* Pin widget 0x18 - NPC */
+	AZALIA_PIN_CFG(0, 0x18, 0x411111F0),
+	/* Pin widget 0x19 - MIC2 (Port-F) */
+	AZALIA_PIN_CFG(0, 0x19, 0x04A11040),
+	/* Pin widget 0x1A - LINE1 (Port-C) */
+	AZALIA_PIN_CFG(0, 0x1a, 0x411111F0),
+	/* Pin widget 0x1B - NPC */
+	AZALIA_PIN_CFG(0, 0x1b, 0x411111F0),
+	/* Pin widget 0x1D - BEEP-IN */
+	AZALIA_PIN_CFG(0, 0x1d, 0x40610041),
+	/* Pin widget 0x1E - NPC */
+	AZALIA_PIN_CFG(0, 0x1e, 0x411111F0),
+	/* Pin widget 0x21 - HP1-OUT (Port-I) */
+	AZALIA_PIN_CFG(0, 0x21, 0x04211020),
+	/*
+	 * Widget node 0x20 - 1
+	 * Codec hidden reset and speaker power 2W/4ohm
+	 */
+	0x0205001A,
+	0x0204C003,
+	0x02050038,
+	0x02047901,
+	/*
+	 * Widget node 0x20 - 2
+	 * Class D power on Reset
+	 */
+	0x0205003C,
+	0x02040354,
+	0x0205003C,
+	0x02040314,
+	/*
+	 * Widget node 0x20 - 3
+	 * Disable AGC and set AGC limit to -1.5dB
+	 */
+	0x02050016,
+	0x02040C50,
+	0x02050012,
+	0x0204EBC1,
+	/*
+	 * Widget node 0x20 - 4
+	 * Set AGC Post gain +1.5dB then Enable AGC
+	 */
+	0x02050013,
+	0x02044023,
+	0x02050016,
+	0x02040E50,
+	/*
+	 * Widget node 0x20 - 5
+	 * Silence detector enabling + Set EAPD to verb control
+	 */
+	0x02050037,
+	0x0204FE15,
+	0x02050010,
+	0x02040020,
+	/*
+	 * Widget node 0x20 - 6
+	 * Silence data mode Threshold (-90dB)
+	 */
+	0x02050030,
+	0x0204A000,
+	0x0205001B,
+	0x02040A4B,
+	/*
+	 * Widget node 0x20 - 7
+	 * Default setting-1
+	 */
+	0x05750003,
+	0x05740DA3,
+	0x02050046,
+	0x02040004,
+	/*
+	 * Widget node 0x20 - 8
+	 * support 1 pin detect two port
+	 */
+	0x02050009,
+	0x0204E003,
+	0x0205000A,
+	0x02047770,
+	/*
+	 * Widget node 0x20 - 9
+	 * To set LDO1/LDO2 as default
+	 */
+	0x02050008,
+	0x02046A0C,
+	0x02050008,
+	0x02046A0C,
+};
+
+const u32 pc_beep_verbs[] = {
+	/* Dos beep path - 1 */
+	0x01470C00,
+	0x02050036,
+	0x02047151,
+	0x01470740,
+	/* Dos beep path - 2 */
+	0x0143b000,
+	0x01470C02,
+	0x01470C02,
+	0x01470C02,
+};
+
+AZALIA_ARRAY_SIZES;
diff --git a/src/mainboard/google/ocelot/variants/ojal/include/variant/ec.h b/src/mainboard/google/ocelot/variants/ojal/include/variant/ec.h
new file mode 100644
index 0000000000..4fc0622f15
--- /dev/null
+++ b/src/mainboard/google/ocelot/variants/ojal/include/variant/ec.h
@@ -0,0 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#ifndef MAINBOARD_EC_H
+#define MAINBOARD_EC_H
+
+#include <baseboard/ec.h>
+
+#endif /* MAINBOARD_GPIO_H */
diff --git a/src/mainboard/google/ocelot/variants/ojal/include/variant/gpio.h b/src/mainboard/google/ocelot/variants/ojal/include/variant/gpio.h
new file mode 100644
index 0000000000..cced66807a
--- /dev/null
+++ b/src/mainboard/google/ocelot/variants/ojal/include/variant/gpio.h
@@ -0,0 +1,11 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#ifndef __MAINBOARD_GPIO_H__
+#define __MAINBOARD_GPIO_H__
+
+#include <baseboard/gpio.h>
+
+/* EC wake is LAN_WAKE# which is a special DeepSX wake pin */
+#define GPE_EC_WAKE	GPE0_LAN_WAK
+
+#endif /* __MAINBOARD_GPIO_H__ */
diff --git a/src/mainboard/google/ocelot/variants/ojal/memory.c b/src/mainboard/google/ocelot/variants/ojal/memory.c
new file mode 100644
index 0000000000..1315639496
--- /dev/null
+++ b/src/mainboard/google/ocelot/variants/ojal/memory.c
@@ -0,0 +1,59 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <baseboard/variants.h>
+#include <boardid.h>
+#include <soc/meminit.h>
+#include <soc/romstage.h>
+
+#define SMBUS_ADDR_DIMM	0x50
+
+static const struct mb_cfg lp5_mem_config = {
+	.type = MEM_TYPE_LP5X,
+
+	.lpx_dq_map = {
+		.ddr0 = {
+			.dq0 = {  10,  11,  8,  9,  15,  14,  12,  13, },
+			.dq1 = {  7,  4,  5,  6,  3,  0,  2,  1 },
+		},
+		.ddr1 = {
+			.dq0 = {  8,  11,  10,  9,  15,  12,  13,  14, },
+			.dq1 = {  6,  7,  5,  4,  1,  3,  0,  2 },
+		},
+		.ddr2 = {
+			.dq0 = {  3,  2,  1,  0,  6,  7,  5,  4, },
+			.dq1 = {  9,  8,  10,  11,  15,  12,  13,  14 },
+		},
+		.ddr3 = {
+			.dq0 = {  8,  11,  10,  9,  15,  13,  12,  14, },
+			.dq1 = {  4,  5,  6,  7,  1,  3,  2,  0 },
+		},
+	},
+
+	.lpx_dqs_map = {
+		.ddr0 = { .dqs0 = 1, .dqs1 = 0 },
+		.ddr1 = { .dqs0 = 1, .dqs1 = 0 },
+		.ddr2 = { .dqs0 = 0, .dqs1 = 1 },
+		.ddr3 = { .dqs0 = 1, .dqs1 = 0 },
+	},
+
+	.ect = true, /* Early Command Training */
+
+	.lp_ddr_dq_dqs_re_training = 1,
+
+	.user_bd = BOARD_TYPE_ULT_ULX,
+
+	.lp5x_config = {
+		.ccc_config = 0xFF,
+	},
+};
+
+const struct mb_cfg *variant_memory_params(void)
+{
+	return &lp5_mem_config;
+}
+
+void variant_get_spd_info(struct mem_spd *spd_info)
+{
+	spd_info->topo = MEM_TOPO_MEMORY_DOWN;
+	spd_info->cbfs_index = 0;
+}
diff --git a/src/mainboard/google/ocelot/variants/ojal/memory/Makefile.mk b/src/mainboard/google/ocelot/variants/ojal/memory/Makefile.mk
new file mode 100644
index 0000000000..aa231270d4
--- /dev/null
+++ b/src/mainboard/google/ocelot/variants/ojal/memory/Makefile.mk
@@ -0,0 +1,7 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+# This is an auto-generated file. Do not edit!!
+# Generated by:
+# ./util/spd_tools/bin/part_id_gen PTL lp5 src/mainboard/google/ocelot/variants/ojal/memory src/mainboard/google/ocelot/variants/ojal/memory/mem_parts_used.txt
+
+SPD_SOURCES =
+SPD_SOURCES += spd/lp5/set-0/spd-10.hex      # ID = 0(0b0000)  Parts = H58G66BK8BX067
diff --git a/src/mainboard/google/ocelot/variants/ojal/memory/dram_id.generated.txt b/src/mainboard/google/ocelot/variants/ojal/memory/dram_id.generated.txt
new file mode 100644
index 0000000000..593ce55be7
--- /dev/null
+++ b/src/mainboard/google/ocelot/variants/ojal/memory/dram_id.generated.txt
@@ -0,0 +1,7 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+# This is an auto-generated file. Do not edit!!
+# Generated by:
+# ./util/spd_tools/bin/part_id_gen PTL lp5 src/mainboard/google/ocelot/variants/ojal/memory src/mainboard/google/ocelot/variants/ojal/memory/mem_parts_used.txt
+
+DRAM Part Name                 ID to assign
+H58G66BK8BX067                 0 (0000)
diff --git a/src/mainboard/google/ocelot/variants/ojal/memory/mem_parts_used.txt b/src/mainboard/google/ocelot/variants/ojal/memory/mem_parts_used.txt
new file mode 100644
index 0000000000..821d48ec13
--- /dev/null
+++ b/src/mainboard/google/ocelot/variants/ojal/memory/mem_parts_used.txt
@@ -0,0 +1,12 @@
+# This is a CSV file containing a list of memory parts used by this variant.
+# One part per line with an optional fixed ID in column 2.
+# Only include a fixed ID if it is required for legacy reasons!
+# Generated IDs are dependent on the order of parts in this file,
+# so new parts must always be added at the end of the file!
+#
+# Generate an updated Makefile.mk and dram_id.generated.txt by running the
+# part_id_gen tool from util/spd_tools.
+# See util/spd_tools/README.md for more details and instructions.
+
+# Part Name
+H58G66BK8BX067
diff --git a/src/mainboard/google/ocelot/variants/ojal/overridetree.cb b/src/mainboard/google/ocelot/variants/ojal/overridetree.cb
new file mode 100644
index 0000000000..47cdd94f4b
--- /dev/null
+++ b/src/mainboard/google/ocelot/variants/ojal/overridetree.cb
@@ -0,0 +1,5 @@
+chip soc/intel/pantherlake
+
+        device domain 0 on
+        end
+end

From 382a7caff3b9f11136be2fe5a0950f19b078574a Mon Sep 17 00:00:00 2001
From: Zexin Wang <ot_zexin.wang@mediatek.corp-partner.google.com>
Date: Wed, 3 Sep 2025 17:20:07 +0800
Subject: [PATCH 1970/3886] soc/mediatek/mt8196: Refactor tracker driver to
 support new platform

Extract the common parts of the mt8196 tracker driver into tracker_v3 to
improve code reusability.

BUG=b:379008996
BRANCH=skywalker
TEST=build passed.

Signed-off-by: Zexin Wang <ot_zexin.wang@mediatek.corp-partner.google.com>
Change-Id: If71bffe03cd2c30a0e9b3057c39667c1c2fdcb62
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89032
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
---
 .../mediatek/common/include/soc/tracker_v3.h  | 20 +++++
 src/soc/mediatek/common/tracker_v3.c          | 76 ++++++++++++++++++
 src/soc/mediatek/mt8196/Makefile.mk           |  2 +-
 src/soc/mediatek/mt8196/include/soc/tracker.h | 13 +---
 src/soc/mediatek/mt8196/tracker.c             | 77 ++-----------------
 5 files changed, 104 insertions(+), 84 deletions(-)
 create mode 100644 src/soc/mediatek/common/include/soc/tracker_v3.h
 create mode 100644 src/soc/mediatek/common/tracker_v3.c

diff --git a/src/soc/mediatek/common/include/soc/tracker_v3.h b/src/soc/mediatek/common/include/soc/tracker_v3.h
new file mode 100644
index 0000000000..51a0972d86
--- /dev/null
+++ b/src/soc/mediatek/common/include/soc/tracker_v3.h
@@ -0,0 +1,20 @@
+/* SPDX-License-Identifier: GPL-2.0-only OR MIT */
+
+#ifndef SOC_MEDIATEK_TRACKER_V3_H
+#define SOC_MEDIATEK_TRACKER_V3_H
+
+#include <stdint.h>
+
+#define TRACKER_V3_OFFSETS_SIZE		8
+#define AR_TRACK_LOG_OFFSET		0x0200
+#define AR_ENTRY_ID_OFFSET		0x0300
+#define AR_TRACK_L_OFFSET		0x0400
+#define AR_TRACK_H_OFFSET		0x0600
+#define AW_TRACK_LOG_OFFSET		0x0800
+#define AW_ENTRY_ID_OFFSET		0x0900
+#define AW_TRACK_L_OFFSET		0x0A00
+#define AW_TRACK_H_OFFSET		0x0C00
+
+extern const u32 tracker_v3_offsets[];
+
+#endif
diff --git a/src/soc/mediatek/common/tracker_v3.c b/src/soc/mediatek/common/tracker_v3.c
new file mode 100644
index 0000000000..7dca4b4d05
--- /dev/null
+++ b/src/soc/mediatek/common/tracker_v3.c
@@ -0,0 +1,76 @@
+/* SPDX-License-Identifier: GPL-2.0-only OR MIT */
+
+#include <commonlib/bsd/helpers.h>
+#include <console/console.h>
+#include <device/mmio.h>
+#include <soc/addressmap.h>
+#include <soc/tracker.h>
+
+/*
+ * for systracker:
+ * offset[0] dump from offset 0x100 ~ 0x2F8
+ * offset[1] dump from offset 0x300 ~ 0x4FC
+ *
+ * for infra tracker:
+ * offset[0] dump from offset 0x100 ~ 0x1F8
+ * offset[1] dump from offset 0x300 ~ 0x3FC
+ *
+ * for vlpsys tracker:
+ * offset[0] dump from offset 0x100 ~ 0x2F8
+ * offset[1] dump from offset 0x300 ~ 0x4FC
+ */
+
+const u32 tracker_v3_offsets[TRACKER_V3_OFFSETS_SIZE] = {
+	AR_TRACK_LOG_OFFSET, AR_ENTRY_ID_OFFSET, AR_TRACK_L_OFFSET,
+	AR_TRACK_H_OFFSET, AW_TRACK_LOG_OFFSET, AW_ENTRY_ID_OFFSET,
+	AW_TRACK_L_OFFSET, AW_TRACK_H_OFFSET,
+};
+
+__weak void tracker_setup(void)
+{
+	/* do nothing. */
+}
+
+static void tracker_dump_data(void)
+{
+	u64 reg_entry;
+	int i, j;
+	uintptr_t reg_log, reg_id, reg_low, reg_high;
+	struct tracker *tra;
+
+	for (j = 0; j < TRACKER_NUM; j++) {
+		tra = &tracker_data[j];
+
+		if (!(read32p(tra->base_addr) & tra->timeout))
+			continue;
+		printk(BIOS_INFO, "**Dump %s ar debug register start**\n", tra->str);
+		for (i = 0; i < tra->entry; i++) {
+			reg_log = tra->base_addr + tra->offsets[0] + i * 4;
+			reg_id = tra->base_addr + tra->offsets[1] + i * 4;
+			reg_low = tra->base_addr + tra->offsets[2] + i * 4;
+			reg_high = tra->base_addr + tra->offsets[3] + i * 4;
+			reg_entry = ((u64)read32p(reg_high)) << 32 | read32p(reg_low);
+			printk(BIOS_INFO, "%#lx:%#x:%#x:%#x:%#x:%#llx\n",
+			       reg_low, read32p(reg_log), read32p(reg_id), read32p(reg_low),
+			       read32p(reg_high), reg_entry);
+		}
+		printk(BIOS_INFO, "**Dump %s aw debug register start**\n", tra->str);
+		for (i = 0; i < tra->entry; i++) {
+			reg_log = tra->base_addr + tra->offsets[4] + i * 4;
+			reg_id = tra->base_addr + tra->offsets[5] + i * 4;
+			reg_low = tra->base_addr + tra->offsets[6] + i * 4;
+			reg_high = tra->base_addr + tra->offsets[7] + i * 4;
+			reg_entry = ((u64)read32p(reg_high)) << 32 | read32p(reg_low);
+			printk(BIOS_INFO, "%#lx:%#x:%#x:%#x:%#x:%#llx\n",
+			       reg_low, read32p(reg_log), read32p(reg_id), read32p(reg_low),
+			       read32p(reg_high), reg_entry);
+		}
+		printk(BIOS_INFO, "**Dump %s debug register end**\n", tra->str);
+	}
+}
+
+void bustracker_init(void)
+{
+	tracker_dump_data();
+	tracker_setup();
+}
diff --git a/src/soc/mediatek/mt8196/Makefile.mk b/src/soc/mediatek/mt8196/Makefile.mk
index b6cefb37f1..5517b092e4 100644
--- a/src/soc/mediatek/mt8196/Makefile.mk
+++ b/src/soc/mediatek/mt8196/Makefile.mk
@@ -21,7 +21,7 @@ bootblock-y += mminfra.c
 bootblock-y += ../common/mmu_operations.c
 bootblock-y += mtcmos.c
 bootblock-$(CONFIG_PCI) += ../common/pcie.c pcie.c
-bootblock-y += tracker.c
+bootblock-y += ../common/tracker_v3.c tracker.c
 bootblock-y += ../common/wdt.c ../common/wdt_req.c wdt.c
 
 romstage-y += ../common/cbmem.c
diff --git a/src/soc/mediatek/mt8196/include/soc/tracker.h b/src/soc/mediatek/mt8196/include/soc/tracker.h
index c82ee83dc3..2927b0c481 100644
--- a/src/soc/mediatek/mt8196/include/soc/tracker.h
+++ b/src/soc/mediatek/mt8196/include/soc/tracker.h
@@ -4,7 +4,7 @@
 #define SOC_MEDIATEK_MT8196_TRACKER_H
 
 #include <soc/tracker_common.h>
-#include <stdint.h>
+#include <soc/tracker_v3.h>
 
 #define BUS_DBG_CON			0x000
 #define BUS_TRACE_CON_AO_PRESCALE	0x8f8
@@ -21,17 +21,6 @@
 #define INFRA_ENTRY_NUM			32
 #define VLP_ENTRY_NUM			4
 
-#define AR_TRACK_LOG_OFFSET		0x0200
-#define AR_ENTRY_ID_OFFSET		0x0300
-#define AR_TRACK_L_OFFSET		0x0400
-#define AR_TRACK_H_OFFSET		0x0600
-#define AW_TRACK_LOG_OFFSET		0x0800
-#define AW_ENTRY_ID_OFFSET		0x0900
-#define AW_TRACK_L_OFFSET		0x0A00
-#define AW_TRACK_H_OFFSET		0x0C00
-
-#define BUSTRACKER_TIMEOUT		0x300
-
 enum {
 	TRACKER_SYSTRACKER = 0,
 	TRACKER_INFRATRACKER,
diff --git a/src/soc/mediatek/mt8196/tracker.c b/src/soc/mediatek/mt8196/tracker.c
index 1fc03b99d2..1fad46a32f 100644
--- a/src/soc/mediatek/mt8196/tracker.c
+++ b/src/soc/mediatek/mt8196/tracker.c
@@ -1,54 +1,33 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
-#include <commonlib/bsd/helpers.h>
 #include <console/console.h>
 #include <device/mmio.h>
 #include <soc/addressmap.h>
 #include <soc/tracker.h>
 
-/*
- * for systracker:
- * offset[0] dump from offset 0x100 ~ 0x2F8
- * offset[1] dump from offset 0x300 ~ 0x4FC
- *
- * for infra tracker:
- * offset[0] dump from offset 0x100 ~ 0x1F8
- * offset[1] dump from offset 0x300 ~ 0x3FC
- *
- * for vlpsys tracker:
- * offset[0] dump from offset 0x100 ~ 0x2F8
- * offset[1] dump from offset 0x300 ~ 0x4FC
- */
-
-static const u32 offsets[] = {
-	AR_TRACK_LOG_OFFSET, AR_ENTRY_ID_OFFSET, AR_TRACK_L_OFFSET,
-	AR_TRACK_H_OFFSET, AW_TRACK_LOG_OFFSET, AW_ENTRY_ID_OFFSET,
-	AW_TRACK_L_OFFSET, AW_TRACK_H_OFFSET,
-};
-
 struct tracker tracker_data[TRACKER_NUM] = {
 	[TRACKER_SYSTRACKER] = {
 		.base_addr = INFRA_TRACKER_BASE,
 		.timeout = BUS_DBG_CON_TIMEOUT,
 		.entry = SYS_TRACK_ENTRY,
-		.offsets = offsets,
-		.offsets_size = ARRAY_SIZE(offsets),
+		.offsets = tracker_v3_offsets,
+		.offsets_size = TRACKER_V3_OFFSETS_SIZE,
 		.str = "systracker",
 	},
 	[TRACKER_INFRATRACKER] = {
 		.base_addr = INFRA_TRACKER_BASE,
 		.timeout = BUS_DBG_CON_TIMEOUT,
 		.entry = INFRA_ENTRY_NUM,
-		.offsets = offsets,
-		.offsets_size = ARRAY_SIZE(offsets),
+		.offsets = tracker_v3_offsets,
+		.offsets_size = TRACKER_V3_OFFSETS_SIZE,
 		.str = "infra_tracker",
 	},
 	[TRACKER_VLPSYSTRACKER] = {
 		.base_addr = VLP_TRACKER_BASE,
 		.timeout = BUS_DBG_CON_TIMEOUT,
 		.entry = VLP_ENTRY_NUM,
-		.offsets = offsets,
-		.offsets_size = ARRAY_SIZE(offsets),
+		.offsets = tracker_v3_offsets,
+		.offsets_size = TRACKER_V3_OFFSETS_SIZE,
 		.str = "vlp_tracker",
 	},
 };
@@ -83,47 +62,3 @@ void tracker_setup(void)
 	write32p(BUS_TRACE_MONITOR_BASE + BUS_TRACE_CON_AO_1, val);
 	write32p(BUS_TRACE_MONITOR_BASE + BUS_TRACE_CON_AO_2, val);
 }
-
-static void tracker_dump_data(void)
-{
-	u64 reg_entry;
-	int i, j;
-	uintptr_t reg_log, reg_id, reg_low, reg_high;
-	struct tracker *tra;
-
-	for (j = 0; j < TRACKER_NUM; j++) {
-		tra = &tracker_data[j];
-
-		if (!(read32p(tra->base_addr) & tra->timeout))
-			continue;
-		printk(BIOS_INFO, "**Dump %s ar debug register start**\n", tra->str);
-		for (i = 0; i < tra->entry; i++) {
-			reg_log = tra->base_addr + tra->offsets[0] + i * 4;
-			reg_id = tra->base_addr + tra->offsets[1] + i * 4;
-			reg_low = tra->base_addr + tra->offsets[2] + i * 4;
-			reg_high = tra->base_addr + tra->offsets[3] + i * 4;
-			reg_entry = ((u64)read32p(reg_high)) << 32 | read32p(reg_low);
-			printk(BIOS_INFO, "%#lx:%#x:%#x:%#x:%#x:%#llx\n",
-			       reg_low, read32p(reg_log), read32p(reg_id), read32p(reg_low),
-			       read32p(reg_high), reg_entry);
-		}
-		printk(BIOS_INFO, "**Dump %s aw debug register start**\n", tra->str);
-		for (i = 0; i < tra->entry; i++) {
-			reg_log = tra->base_addr + tra->offsets[4] + i * 4;
-			reg_id = tra->base_addr + tra->offsets[5] + i * 4;
-			reg_low = tra->base_addr + tra->offsets[6] + i * 4;
-			reg_high = tra->base_addr + tra->offsets[7] + i * 4;
-			reg_entry = ((u64)read32p(reg_high)) << 32 | read32p(reg_low);
-			printk(BIOS_INFO, "%#lx:%#x:%#x:%#x:%#x:%#llx\n",
-			       reg_low, read32p(reg_log), read32p(reg_id), read32p(reg_low),
-			       read32p(reg_high), reg_entry);
-		}
-		printk(BIOS_INFO, "**Dump %s debug register end**\n", tra->str);
-	}
-}
-
-void bustracker_init(void)
-{
-	tracker_dump_data();
-	tracker_setup();
-}

From cf11722e6846404bf66549347bec386dffec4d41 Mon Sep 17 00:00:00 2001
From: Zexin Wang <ot_zexin.wang@mediatek.corp-partner.google.com>
Date: Wed, 3 Sep 2025 17:27:57 +0800
Subject: [PATCH 1971/3886] soc/mediatek/mt8189: Enable tracker debug hardware

Tracker is a debugging tool, including AP/INFRA tracker. When bus
timeout occurs, the system reboots and latches some values which could
be used for debug. On MT8189, this feature is enabled by using the
common driver tracker_v3.

BUG=b:379008996
BRANCH=skywalker
TEST=When detected bus timeout, tracker show:
**Dump systracker aw debug register start**
0x10208ae0:0x0:0x0:0x0:0x0:0x0
0x10208ae4:0x0:0x0:0x0:0x0:0x0
0x10208ae8:0x0:0x0:0x0:0x0:0x0
0x10208aec:0x0:0x0:0x0:0x0:0x0
0x10208af0:0x0:0x0:0x0:0x0:0x0
0x10208af4:0x0:0x0:0x0:0x0:0x0
0x10208af8:0xc0000020:0x5:0x101e80:0x0
0x10208afc:0xc0000120:0x100:0x1cc10040
**Dump systracker debug register end**

Signed-off-by: Zexin Wang <ot_zexin.wang@mediatek.corp-partner.google.com>
Change-Id: Icb34c87adc099172abdfc9868ff8e30287e61be0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89033
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
---
 src/soc/mediatek/mt8189/Makefile.mk           |  1 +
 src/soc/mediatek/mt8189/bootblock.c           |  2 +
 .../mediatek/mt8189/include/soc/addressmap.h  |  3 +
 src/soc/mediatek/mt8189/include/soc/tracker.h | 24 ++++++++
 src/soc/mediatek/mt8189/tracker.c             | 55 +++++++++++++++++++
 5 files changed, 85 insertions(+)
 create mode 100644 src/soc/mediatek/mt8189/include/soc/tracker.h
 create mode 100644 src/soc/mediatek/mt8189/tracker.c

diff --git a/src/soc/mediatek/mt8189/Makefile.mk b/src/soc/mediatek/mt8189/Makefile.mk
index 0a5a652d92..8eda710cc2 100644
--- a/src/soc/mediatek/mt8189/Makefile.mk
+++ b/src/soc/mediatek/mt8189/Makefile.mk
@@ -15,6 +15,7 @@ bootblock-y += efuse.c
 bootblock-y += ../common/lastbus_v2.c lastbus.c
 bootblock-y += ../common/mmu_operations.c
 bootblock-y += ../common/mtcmos.c mtcmos.c
+bootblock-y += ../common/tracker_v3.c tracker.c
 bootblock-y += ../common/wdt.c ../common/wdt_req.c wdt.c
 
 romstage-y += ../common/cbmem.c
diff --git a/src/soc/mediatek/mt8189/bootblock.c b/src/soc/mediatek/mt8189/bootblock.c
index adf3938187..c410ce1493 100644
--- a/src/soc/mediatek/mt8189/bootblock.c
+++ b/src/soc/mediatek/mt8189/bootblock.c
@@ -5,11 +5,13 @@
 #include <soc/mmu_operations.h>
 #include <soc/pll.h>
 #include <soc/spm_mtcmos.h>
+#include <soc/tracker.h>
 #include <soc/wdt.h>
 
 void bootblock_soc_init(void)
 {
 	mtk_mmu_init();
+	bustracker_init();
 	lastbus_init();
 	mtk_wdt_init();
 	mt_pll_init();
diff --git a/src/soc/mediatek/mt8189/include/soc/addressmap.h b/src/soc/mediatek/mt8189/include/soc/addressmap.h
index abc9f972f0..d6a464d68e 100644
--- a/src/soc/mediatek/mt8189/include/soc/addressmap.h
+++ b/src/soc/mediatek/mt8189/include/soc/addressmap.h
@@ -9,6 +9,7 @@ enum {
 	MCUPM_SRAM_BASE			= 0x0C540000,
 	MCUPM_CFG_BASE			= 0x0C580000,
 	DBGAO_BASE			= 0x0D01A000,
+	BUS_TRACE_MONITOR_BASE		= 0x0D040000,
 	DEM_BASE			= 0x0D0A0000,
 	IO_PHYS				= 0x10000000,
 };
@@ -38,11 +39,13 @@ enum {
 	DEVAPC_INFRA_AO_BASE		= IO_PHYS + 0x00030000,
 	DEVAPC_INFRA_AO1_BASE		= IO_PHYS + 0x00034000,
 	EMISYS_NAO_DEBUG_BASE		= IO_PHYS + 0x00042000,
+	AP_TRACKER_BASE			= IO_PHYS + 0x00208000,
 	INFRACFG_BASE			= IO_PHYS + 0x0020E000,
 	EMI0_BASE			= IO_PHYS + 0x00219000,
 	EMI0_MPU_BASE			= IO_PHYS + 0x00226000,
 	DRAMC_CHA_AO_BASE		= IO_PHYS + 0x00230000,
 	EMICFG_AO_MEM_BASE		= IO_PHYS + 0x00270000,
+	INFRA_TRACKER_BASE		= IO_PHYS + 0x00314000,
 	THERM_CTRL_BASE			= IO_PHYS + 0x00315000,
 	DPM_PM_SRAM_BASE		= IO_PHYS + 0x00900000,
 	DPM_DM_SRAM_BASE		= IO_PHYS + 0x00920000,
diff --git a/src/soc/mediatek/mt8189/include/soc/tracker.h b/src/soc/mediatek/mt8189/include/soc/tracker.h
new file mode 100644
index 0000000000..a3c836ed79
--- /dev/null
+++ b/src/soc/mediatek/mt8189/include/soc/tracker.h
@@ -0,0 +1,24 @@
+/* SPDX-License-Identifier: GPL-2.0-only OR MIT */
+
+#ifndef SOC_MEDIATEK_MT8189_TRACKER_H
+#define SOC_MEDIATEK_MT8189_TRACKER_H
+
+#include <soc/tracker_common.h>
+#include <soc/tracker_v3.h>
+
+#define BUS_DBG_CON			0x000
+#define BUS_DBG_TIMER_CON0_26M		0x050
+#define BUS_TRACE_CON_AO_1		0x8FC
+#define BUS_TRACE_CON_AO_2		0x9FC
+#define BUS_TRACE_EN			16
+
+#define SYS_TRACK_ENTRY			64
+#define INFRA_ENTRY_NUM			32
+
+enum {
+	TRACKER_SYSTRACKER = 0,
+	TRACKER_INFRATRACKER,
+	TRACKER_NUM,
+};
+
+#endif
diff --git a/src/soc/mediatek/mt8189/tracker.c b/src/soc/mediatek/mt8189/tracker.c
new file mode 100644
index 0000000000..da9445db84
--- /dev/null
+++ b/src/soc/mediatek/mt8189/tracker.c
@@ -0,0 +1,55 @@
+/* SPDX-License-Identifier: GPL-2.0-only OR MIT */
+
+#include <console/console.h>
+#include <device/mmio.h>
+#include <soc/addressmap.h>
+#include <soc/tracker.h>
+
+struct tracker tracker_data[TRACKER_NUM] = {
+	[TRACKER_SYSTRACKER] = {
+		.base_addr = AP_TRACKER_BASE,
+		.timeout = BUS_DBG_CON_TIMEOUT,
+		.entry = SYS_TRACK_ENTRY,
+		.offsets = tracker_v3_offsets,
+		.offsets_size = TRACKER_V3_OFFSETS_SIZE,
+		.str = "systracker",
+	},
+	[TRACKER_INFRATRACKER] = {
+		.base_addr = INFRA_TRACKER_BASE,
+		.timeout = BUS_DBG_CON_TIMEOUT,
+		.entry = INFRA_ENTRY_NUM,
+		.offsets = tracker_v3_offsets,
+		.offsets_size = TRACKER_V3_OFFSETS_SIZE,
+		.str = "infra_tracker",
+	},
+};
+
+void tracker_setup(void)
+{
+	u32 val;
+	/*
+	 * Set ap/infra tracker timeout.
+	 * timeout = clock_in_mhz / 15 * timeout_in_us
+	 *
+	 * timeout: 200ms
+	 * ap tracker clock: 26MHz
+	 * infra tracker clock: 26MHz
+	 */
+	val = 26 / 15 * 200000;
+
+	write32p(AP_TRACKER_BASE + BUS_DBG_TIMER_CON0_26M, val);
+	write32p(INFRA_TRACKER_BASE + BUS_DBG_TIMER_CON0_26M, val);
+
+	/*
+	 * Enable infra/peri tracker.
+	 * bit[0] - BUS_DBG_EN
+	 * bit[1] - TIMEOUT_EN
+	 * bit[2] - SLV_ERR_EN
+	 * bit[9] - TIMER_CLOCK_SEL
+	 * bit[13] - HALT_ON_TIMEOUT_EN
+	 * bit[14] - BUS_OT_WEN_CTRL
+	 */
+	val = BIT(0) | BIT(1) | BIT(2) | BIT(9) | BIT(13) | BIT(14);
+	write32p(BUS_TRACE_MONITOR_BASE + BUS_TRACE_CON_AO_1, val);
+	write32p(BUS_TRACE_MONITOR_BASE + BUS_TRACE_CON_AO_2, val);
+}

From a0bdf3961cd29d833c40a0edef0f0d95cd492bfb Mon Sep 17 00:00:00 2001
From: Hari L <haril@qualcomm.corp-partner.google.com>
Date: Mon, 8 Sep 2025 16:09:33 +0530
Subject: [PATCH 1972/3886] soc/qualcomm/common: Add clock reset function
 support

Implements clock-based reset control via CLK_CTL_ARES_SHFT bit
in CBC, enabling reset of cores receiving CBC-generated clocks.
This is required for proper initialization of clocks needed for
subsystems like USB Type-A.

TEST: Verified on x1p42100 CRD by asserting CLK_ARES through CBC
register writes during USB Type-A enablement. Confirmed USB
enumeration and reset functionality serial console.


Change-Id: If878994eaa24a21061470f962a4883f29be5476f
Signed-off-by: Hari L <haril@qualcomm.corp-partner.google.com>
:wq
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89102
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/soc/qualcomm/common/clock.c                    | 9 +++++++++
 src/soc/qualcomm/common/include/soc/clock_common.h | 4 ++++
 2 files changed, 13 insertions(+)

diff --git a/src/soc/qualcomm/common/clock.c b/src/soc/qualcomm/common/clock.c
index 1768566f7c..200e16e5c7 100644
--- a/src/soc/qualcomm/common/clock.c
+++ b/src/soc/qualcomm/common/clock.c
@@ -59,6 +59,15 @@ void clock_reset_bcr(void *bcr_addr, bool assert)
 		clrbits32(bcr_addr, BIT(CLK_CTL_BCR_BLK_SHFT));
 }
 
+/* Clock Reset Operations */
+void clock_reset(void *cbcr_addr, bool assert)
+{
+	if (assert)
+		setbits32(cbcr_addr, BIT(CLK_CTL_ARES_SHFT));
+	else
+		clrbits32(cbcr_addr, BIT(CLK_CTL_ARES_SHFT));
+}
+
 /* Clock GDSC Operations */
 enum cb_err enable_and_poll_gdsc_status(void *gdscr_addr)
 {
diff --git a/src/soc/qualcomm/common/include/soc/clock_common.h b/src/soc/qualcomm/common/include/soc/clock_common.h
index 6dd9bfecc8..10ae134c70 100644
--- a/src/soc/qualcomm/common/include/soc/clock_common.h
+++ b/src/soc/qualcomm/common/include/soc/clock_common.h
@@ -115,8 +115,10 @@ enum clk_ctl_cmd_rcgr {
 
 enum clk_ctl_cbcr {
 	CLK_CTL_EN_SHFT  = 0,
+	CLK_CTL_ARES_SHFT = 2,
 	CLK_CTL_OFF_SHFT = 31,
 	CLK_CTL_EN_BMSK = 0x1,
+	CLK_CTL_ARES_BMSK = 0x1 << CLK_CTL_ARES_SHFT,
 	CLK_CTL_OFF_BMSK = 0x80000000,
 };
 
@@ -148,6 +150,8 @@ enum cb_err enable_and_poll_gdsc_status(void *gdscr_addr);
 
 void clock_reset_bcr(void *bcr_addr, bool assert);
 
+void clock_reset(void *cbcr_addr, bool assert);
+
 /*
  * clock_configure(): Configure the clock at the given clock speed (hz).  If hz
  * does not match any entries in the clk_cfg array, will throw and error and die().

From 05cd5a7ab940f4d026ceeadae4fcf97056e7baf0 Mon Sep 17 00:00:00 2001
From: wangzhao5 <wangzhao5@huaqin.corp-partner.google.com>
Date: Wed, 3 Sep 2025 15:40:40 +0800
Subject: [PATCH 1973/3886] mb/google/nissa/var/telith: Generate RAM IDs for
 telith

Generate RAM ID for H58G56CK8BX146 and H58G66CK8BX147

BUG=b:431945026
BRANCH=None
TEST=boot to kernel success

Change-Id: I9d90fbb1b0d1ffafff53755d2b3e95241c88ac2d
Signed-off-by: wangzhao5 <wangzhao5@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89026
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Kun Liu <liukun11@huaqin.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/google/brya/variants/telith/memory/Makefile.mk  | 4 +++-
 .../google/brya/variants/telith/memory/dram_id.generated.txt  | 4 +++-
 .../google/brya/variants/telith/memory/mem_parts_used.txt     | 2 ++
 3 files changed, 8 insertions(+), 2 deletions(-)

diff --git a/src/mainboard/google/brya/variants/telith/memory/Makefile.mk b/src/mainboard/google/brya/variants/telith/memory/Makefile.mk
index 3b7dc39124..948e9947b6 100644
--- a/src/mainboard/google/brya/variants/telith/memory/Makefile.mk
+++ b/src/mainboard/google/brya/variants/telith/memory/Makefile.mk
@@ -1,7 +1,7 @@
 # SPDX-License-Identifier: GPL-2.0-or-later
 # This is an auto-generated file. Do not edit!!
 # Generated by:
-# util/spd_tools/bin/part_id_gen ADL lp5 src/mainboard/google/brya/variants/teliks/memory src/mainboard/google/brya/variants/teliks/memory/mem_parts_used.txt
+# util/spd_tools/bin/part_id_gen ADL lp5 src/mainboard/google/brya/variants/telith/memory src/mainboard/google/brya/variants/telith/memory/mem_parts_used.txt
 
 SPD_SOURCES =
 SPD_SOURCES += spd/lp5/set-0/spd-1.hex      # ID = 0(0b0000)  Parts = MT62F512M32D2DR-031 WT:B, H9JCNNNBK3MLYR-N6E
@@ -10,3 +10,5 @@ SPD_SOURCES += spd/lp5/set-0/spd-4.hex      # ID = 2(0b0010)  Parts = H9JCNNNFA5
 SPD_SOURCES += spd/lp5/set-0/spd-9.hex      # ID = 3(0b0011)  Parts = K3KL6L60GM-MGCT
 SPD_SOURCES += spd/lp5/set-0/spd-7.hex      # ID = 4(0b0100)  Parts = MT62F1G32D2DS-026 WT:B, K3KL8L80CM-MGCT, H58G56BK7BX068
 SPD_SOURCES += spd/lp5/set-0/spd-8.hex      # ID = 5(0b0101)  Parts = MT62F2G32D4DS-026 WT:B, K3KL9L90CM-MGCT, H58G66BK7BX067
+SPD_SOURCES += spd/lp5/set-0/spd-11.hex      # ID = 6(0b0110)  Parts = H58G56CK8BX146
+SPD_SOURCES += spd/lp5/set-0/spd-10.hex      # ID = 7(0b0111)  Parts = H58G66CK8BX147
diff --git a/src/mainboard/google/brya/variants/telith/memory/dram_id.generated.txt b/src/mainboard/google/brya/variants/telith/memory/dram_id.generated.txt
index 773f11b676..2eb20d169e 100644
--- a/src/mainboard/google/brya/variants/telith/memory/dram_id.generated.txt
+++ b/src/mainboard/google/brya/variants/telith/memory/dram_id.generated.txt
@@ -1,7 +1,7 @@
 # SPDX-License-Identifier: GPL-2.0-or-later
 # This is an auto-generated file. Do not edit!!
 # Generated by:
-# util/spd_tools/bin/part_id_gen ADL lp5 src/mainboard/google/brya/variants/teliks/memory src/mainboard/google/brya/variants/teliks/memory/mem_parts_used.txt
+# util/spd_tools/bin/part_id_gen ADL lp5 src/mainboard/google/brya/variants/telith/memory src/mainboard/google/brya/variants/telith/memory/mem_parts_used.txt
 
 DRAM Part Name                 ID to assign
 MT62F512M32D2DR-031 WT:B       0 (0000)
@@ -17,3 +17,5 @@ H58G56BK7BX068                 4 (0100)
 MT62F2G32D4DS-026 WT:B         5 (0101)
 K3KL9L90CM-MGCT                5 (0101)
 H58G66BK7BX067                 5 (0101)
+H58G56CK8BX146                 6 (0110)
+H58G66CK8BX147                 7 (0111)
diff --git a/src/mainboard/google/brya/variants/telith/memory/mem_parts_used.txt b/src/mainboard/google/brya/variants/telith/memory/mem_parts_used.txt
index 8aee4de40e..4566426d26 100644
--- a/src/mainboard/google/brya/variants/telith/memory/mem_parts_used.txt
+++ b/src/mainboard/google/brya/variants/telith/memory/mem_parts_used.txt
@@ -22,3 +22,5 @@ H58G56BK7BX068
 MT62F2G32D4DS-026 WT:B
 K3KL9L90CM-MGCT
 H58G66BK7BX067
+H58G56CK8BX146
+H58G66CK8BX147

From 3507992d1dcc6f474bafb9f281b18be32f23ffb3 Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Sun, 7 Sep 2025 20:46:47 +0100
Subject: [PATCH 1974/3886] mb/starlabs/starbook/adl_n: Adjust the VBT

* Reorder Child Device mappings to prioritise EFP displays.
* Disable EFP3 as it is not present
* Change eDP panel colour depth from 18-bit to 24-bit (8 bpc).
* Change POST brightness from 255 to 100.
* Change minimum brightness from 6 to 0.
* Change DPST aggresiveness to 6 to 2.
* Enable PSR

Change-Id: I895fc61dff120e0ae989f45b37c0c5cde3c5e2ce
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89095
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 .../starlabs/starbook/variants/adl_n/data.vbt | Bin 9216 -> 9216 bytes
 .../variants/adl_n/data_native_res.vbt        | Bin 9216 -> 9216 bytes
 2 files changed, 0 insertions(+), 0 deletions(-)

diff --git a/src/mainboard/starlabs/starbook/variants/adl_n/data.vbt b/src/mainboard/starlabs/starbook/variants/adl_n/data.vbt
index 6cf0f8be2b47494c42021df9001fc998ebd2df45..1e9e797faec9ba9bed5f962b2cf0c3505be043e4 100644
GIT binary patch
delta 253
zcmZqhXz-XI#azr_Fu9OXc%y+hqc95t2ZI9x3lMWKFaT)=28YRsY}%7s84Z~j7$)yv
zH0EMwU;r{14loEz{>o?uWNy}FN@q-GWC97(jQkG-T&EehCOfjUY_4Zn!^kKAbeQJm
tP_{e{#+1ni_{=%kfUW{zhDrS9ldbt9MTF1*1H=FSK%a_i-ox)A0ssUmBZ&Y2

delta 262
zcmZqhXz-XI#r%rFU~(d(@J0i1Mnwh&4h9w=b^u}pAd3OWVgRxjfb0e!TLGw2c5*AD
zArqU#<Q<I0T#P^|AUMFlF!?K^8Pl<h&ALqKjOh$aK*&HdaupD8oo3*g?8wrxxt?VW
z<K#p(t<9lqc^s3k^Qla}&nGfjm|tVEJio+bYyL<PF*Lxy@c%#1BO;sk@Vkfr0K+pT
AzW@LL

diff --git a/src/mainboard/starlabs/starbook/variants/adl_n/data_native_res.vbt b/src/mainboard/starlabs/starbook/variants/adl_n/data_native_res.vbt
index d4b86ca2169d2f724e70f3fdb3dfdc7e784700f1..f82018ef8b785284d4b305e438de3a665e4dede3 100644
GIT binary patch
delta 290
zcmZqhXz-XI#azN*Fu9OXc%y+hqc95t2ZI9x3lMWKFaT)=28YRsY}%7s84Z~j7$)yv
zH0EMwU;r{14loEz{>o?uWNy}FN@q-GWC97(jQkG-T&EehCOfjUY_4Zn!^kKAbeQJm
zP_{e{#+1ni_{=%kfUW{zhDrS9ldbt9MTF1*1H=FSK%a_i-otOs$lU<+hy~DxCT7f&
O6NIbK@#X~K1p)xaj4k^B

delta 299
zcmZqhXz-XI#k`KeU~(d(@J0i1Mnwh&4h9w=b^u}pAd3OWVgRxjfb0e!TLGw2c5*AD
zArqU#<Q<I0T#P^|AUMFlF!?K^8Pl<h&ALqKjOh$aK*&HdaupD8oo3*g?8wrxxt?VW
z<K#p(t<9lqc^s3k^Qla}&nGfjm|tVEJio+bYyL<PF*Lxy@c%#1BO;sk@S8JogWL}S
SCT7f&6NIbK@#X~K1p)w_b}%sj


From d3cea61907aa87feaee7ee00805323311f8adf9b Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Sun, 7 Sep 2025 21:02:48 +0100
Subject: [PATCH 1975/3886] mb/starlabs/starlite_adl: Adjust the VBT

* Reorder Child Device mappings to prioritise EFP displays.
* Change eDP panel colour depth from 18-bit to 24-bit (8 bpc).
* Change minimum brightness from 6 to 0.
* Clear unused flags

Change-Id: Ifca1f55962ae312073eddcfc74134795cabc884a
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89096
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 .../variants/mk_v/data_native_res.vbt         | Bin 9216 -> 9216 bytes
 1 file changed, 0 insertions(+), 0 deletions(-)

diff --git a/src/mainboard/starlabs/starlite_adl/variants/mk_v/data_native_res.vbt b/src/mainboard/starlabs/starlite_adl/variants/mk_v/data_native_res.vbt
index 556fa45c615329baa9a00e20c58f7318887d2ef7..4f5a52e969536baa2f61403f78f0ab79a19a7abb 100644
GIT binary patch
delta 518
zcmcIgJxc>Y5Ph?E7n6(R77s-W!zE1&Ht_=^h>(Cnda<w&5=mj<SF4RdYz1}5Z?Fz$
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I*8Ma63$NB-VgLXD

delta 486
zcmcIgu}T9$5S`h*4M~*TatZM)E<^<nA;krPS}3uJ#71l^Bw#Fpb`n9bO=Tm3GLYIj
zMMMsJ?Sz0uiWGi93c<!gNO8^{vC!VPu>0QbzBj{k>Ye(HtK{Ma1ayYk+d!)c<YD+w
z6G%;5rgp+jiYpWrfKS)x(<AzU1;ZoI8kQC`7$AV)<B3_3`46^W6o0EyMtEgeoXW=3
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zDoqD+^CZ>cYY{j5Uwe-cqSZq&mh`O7=|knHl5=^IPS{MGCb3JenJUfOCGzZ9s@diB
zU3lN-#&#eL`>+QsC}9`I5~66rD~f=bLH-Y@Z@b}}y@oS)iU-N_tE|dUJ7Xm6e1>1y
Iq~@}PZ>a=Tng9R*


From 0b8ad35ac1e33a544bef45de800795dc5be72974 Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Sun, 7 Sep 2025 21:09:15 +0100
Subject: [PATCH 1976/3886] mb/starlabs/byte_adl: Adjust the VBT

* Reorder Child Device mappings to prioritise EFP displays.
* Disable LFP1 as it is not present

Change-Id: Ib998bc6df5430d08f9ded4d1e84f5aaa57b8be3d
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89097
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 .../starlabs/byte_adl/variants/mk_ii/data.vbt | Bin 9216 -> 9216 bytes
 1 file changed, 0 insertions(+), 0 deletions(-)

diff --git a/src/mainboard/starlabs/byte_adl/variants/mk_ii/data.vbt b/src/mainboard/starlabs/byte_adl/variants/mk_ii/data.vbt
index 657e3a4918a2058955aa86c291d576f3532c055a..5c9db50c93300f512c58a713d068ecc6f6e605cf 100644
GIT binary patch
delta 221
zcmZqhXz-XI#Vo>LFqx5Ac%y+hqp$;m1A_ts3m7v1*$fN{lM~srC$};dG73!o&bUDc
zC?p`ja8^+O$bf*!j!Ytx&oW(%W@KVuVql;Nx%nrv4HM7>iENsi<Js~!7*i&n<FjXE
Sn9RpNK|lx%Y+lD7Bmw~N4;oki

delta 278
zcmZqhXz-XI#VpKVFgcM?c%y+hqYVRt0|NsCBM`FySu8-70}z8~1)wlQ9HIuuXAl5l
zCLjihGcZnWW-Ml8nEah_gTl201_1$vvx*=E3=CWl6$cm`7!|-u873cRx*iSG3erpq
za`R7S8>Y!7A`+7e7=<>+v*mG2zR9OE`7R&NWI=wD$+G-BlU?~E1;o(6=5_o*A^>Xv
BA4LEF


From 159afbc5d5f1ccea22b21f8ca77be1b2054e216e Mon Sep 17 00:00:00 2001
From: Patrick Rudolph <patrick.rudolph@9elements.com>
Date: Sun, 17 Aug 2025 20:01:32 +0200
Subject: [PATCH 1977/3886] lib/lzmadecode: Increase decoding speed by 30%

When CONFIG_SSE is enabled use the "prefetchnta" instruction to load
the next chunk of data into the CPU cache. This only works when the
input stream is covered by an MTRR. In case the input stream is read
from the SPI ROM MMIO area it allows to keep the SPI controller
busy fetching new data, which is automatically placed into the CPU
cache, resulting in less I/O wait on the CPU side and faster
decompression.

When the input stream is not cachable the prefetch instruction has no
effect.

The SPI interfaces on the tested device runs at 100Mbit/s and the
Sandy Bridge mobile CPU has quite some work to do decompressing the
LZMA stream.
That gives the SPI controller enough time to preload data into the
cache.

The payload of 1100213 bytes is now read in 164msec, resulting in an
input bandwidth of 53MBit/s.

TEST=Booted on Lenovo X220 and used cbmem -t:
Before:
  16:finished LZMA decompress (ignore for x86)   1,218,418 (210,054)
After:
  16:finished LZMA decompress (ignore for x86)   1,170,949 (164,868)

Boots 46msec faster than before or 30% faster than before.

Change-Id: I3b2ed7fe0883f271553ecd1ab4191e4848ad0299
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88813
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
---
 src/lib/lzmadecode.c | 16 ++++++++++++++++
 1 file changed, 16 insertions(+)

diff --git a/src/lib/lzmadecode.c b/src/lib/lzmadecode.c
index 5c6baa4160..f68cab61c4 100644
--- a/src/lib/lzmadecode.c
+++ b/src/lib/lzmadecode.c
@@ -25,6 +25,17 @@
   #define __lzma_attribute_Ofast__
 #endif
 
+/* When the input stream is covered by an MTRR the "prefetch" instruction
+ * will load the next chunk of data into the CPU cache ahead of time.
+ * On a 100MBit/s SPI interface this reduces the time spent in I/O wait
+ * by 5usec for every cache-line (64bytes) prefetched.
+ */
+#if CONFIG(SSE)
+  #define __lzma_prefetch(x) {asm volatile("prefetchnta %0" :: "m" (x));}
+#else
+  #define __lzma_prefetch(x)
+#endif
+
 #include "lzmadecode.h"
 #include <types.h>
 
@@ -68,6 +79,11 @@
 		RC_TEST;				\
 		Range <<= 8;				\
 		Code = (Code << 8) | RC_READ_BYTE;	\
+		if (!((uintptr_t)Buffer & 63)) {		\
+			if ((BufferLim - Buffer) >= 128) {	\
+				__lzma_prefetch(Buffer[64]);	\
+			}					\
+		}					\
 	}
 
 #define IfBit0(p)						\

From 2e2490256f3f172bf29b73dac2ac4dcf132b03b7 Mon Sep 17 00:00:00 2001
From: Hari L <haril@qualcomm.corp-partner.google.com>
Date: Mon, 8 Sep 2025 16:29:55 +0530
Subject: [PATCH 1978/3886] soc/qualcomm/x1p42100: Add USB clock support for
 X1P42100

Add support for USB controller, PHY and NOC clocks.

The register details are part of HRD-X1P42100-S1 document.
https://docs.qualcomm.com/bundle/resource/topics/HRD-X1P42100-S1/

TEST=Verify the boot process on the X1P42100 by creating an
image.serial.bin. After booting, confirm that the USB clocks are
on by inspecting the Clock Branch Control Register (CBCR) for
each clock. The status is indicated by BIT31, where a low value
means the clock is on.

Change-Id: Ic78e75c2c9963311530172d802aabb03f540060c
Signed-off-by: Hari L <haril@qualcomm.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88906
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
---
 src/soc/qualcomm/x1p42100/clock.c             |  77 +++++++++
 src/soc/qualcomm/x1p42100/include/soc/clock.h | 150 ++++++++++++++----
 2 files changed, 200 insertions(+), 27 deletions(-)

diff --git a/src/soc/qualcomm/x1p42100/clock.c b/src/soc/qualcomm/x1p42100/clock.c
index 0e6fa8e0a7..81c406282d 100644
--- a/src/soc/qualcomm/x1p42100/clock.c
+++ b/src/soc/qualcomm/x1p42100/clock.c
@@ -5,6 +5,7 @@
 #include <device/mmio.h>
 #include <soc/clock.h>
 #include <types.h>
+#include <stdbool.h>
 
 static struct clock_freq_config qspi_core_cfg[] = {
 	{
@@ -234,6 +235,30 @@ struct pcie pcie_cfg[] = {
 	},
 };
 
+static u32 *usb_gdsc[MAX_USB_GDSC] = {
+	[USB30_MP_GDSC] = &gcc->gcc_usb30_mp_gdscr,
+	[USB3_SS0_PHY_GDSC] = &gcc->gcc_usb3_mp_ss0_phy_gdscr,
+	[USB3_SS1_PHY_GDSC] = &gcc->gcc_usb3_mp_ss1_phy_gdscr,
+};
+
+static u32 *usb_cbcr[USB_CLK_COUNT] = {
+	[USB30_MP_MASTER_CBCR] = &gcc->gcc_usb30_mp_master_cbcr,
+	[USB30_MP_SLEEP_CBCR] = &gcc->gcc_usb30_mp_sleep_cbcr,
+	[USB30_MP_MOCK_UTMI_CBCR] = &gcc->gcc_usb30_mp_mock_utmi_cbcr,
+	[USB3_MP_PHY_AUX_CBCR] = &gcc->gcc_usb3_mp_phy_aux_cbcr,
+	[USB3_MP_PHY_COM_AUX_CBCR] = &gcc->gcc_usb3_mp_phy_com_aux_cbcr,
+	[USB3_MP_PHY_PIPE_0_CBCR] = &gcc->gcc_usb3_mp_phy_pipe_0_cbcr,
+	[USB3_MP_PHY_PIPE_1_CBCR] = &gcc->gcc_usb3_mp_phy_pipe_1_cbcr,
+	[CFG_NOC_USB3_MP_AXI_CBCR] = &gcc->gcc_cfg_noc_usb3_mp_axi_cbcr,
+	[AGGRE_USB3_MP_AXI_CBCR] = &gcc->gcc_aggre_usb3_mp_axi_cbcr,
+	[SYS_NOC_USB_AXI_CBCR] = &gcc->gcc_sys_noc_usb_axi_cbcr,
+	[CFG_NOC_USB_ANOC_NORTH_AHB_CBCR] = &gcc->gcc_cfg_noc_usb_anoc_north_ahb_cbcr,
+	[CFG_NOC_USB_ANOC_SOUTH_AHB_CBCR] = &gcc->gcc_cfg_noc_usb_anoc_south_ahb_cbcr,
+	[AGGRE_USB_NOC_AXI_CBCR] = &gcc->gcc_aggre_usb_noc_axi_cbcr,
+	[AGGRE_NOC_USB_SOUTH_AXI_CBCR] = &gcc->gcc_aggre_noc_usb_south_axi_cbcr,
+	[AGGRE_NOC_USB_NORTH_AXI_CBCR] = &gcc->gcc_aggre_noc_usb_north_axi_cbcr,
+};
+
 static struct clock_freq_config pcie_core_cfg[] = {
 	{
 		.hz = 100 * MHz,
@@ -242,6 +267,14 @@ static struct clock_freq_config pcie_core_cfg[] = {
 	},
 };
 
+static struct clock_freq_config usb_core_cfg[] = {
+	{
+		.hz = CLK_200MHZ,
+		.src = SRC_GPLL0_MAIN_600MHZ,
+		.div = QCOM_CLOCK_DIV(3),
+	},
+};
+
 void clock_configure_qspi(uint32_t hz)
 {
 	clock_configure(&gcc->qspi_core, qspi_core_cfg, hz, ARRAY_SIZE(qspi_core_cfg));
@@ -339,6 +372,50 @@ void clock_configure_pcie(void)
 			pcie_core_cfg, PCIE_PHY_RCHNG_FREQ, ARRAY_SIZE(pcie_core_cfg));
 }
 
+enum cb_err clock_enable_usb_gdsc(enum clk_usb_gdsc gdsc_type)
+{
+	if (gdsc_type >= MAX_USB_GDSC)
+		return CB_ERR;
+
+	return enable_and_poll_gdsc_status(usb_gdsc[gdsc_type]);
+}
+
+enum cb_err usb_clock_enable(enum clk_usb clk_type)
+{
+	if (clk_type >= USB_CLK_COUNT)
+		return CB_ERR;
+
+	return clock_enable(usb_cbcr[clk_type]);
+}
+
+void usb_clock_reset(enum clk_usb clk_type, bool assert)
+{
+	clock_reset(usb_cbcr[clk_type], assert);
+}
+
+void clock_configure_usb(void)
+{
+	clock_configure(&gcc->usb30_mp_master_rcg,
+		usb_core_cfg, USB3_MASTER_CLK_MIN_FREQ_HZ, ARRAY_SIZE(usb_core_cfg));
+}
+
+enum cb_err usb_clock_configure_mux(enum clk_pipe_usb clk_type, u32 src_type)
+{
+	switch (clk_type) {
+	case USB3_PHY_PIPE_0:
+		write32(&gcc->gcc_usb3_mp_phy_pipe_0_muxr, src_type);
+		break;
+	case USB3_PHY_PIPE_1:
+		write32(&gcc->gcc_usb3_mp_phy_pipe_1_muxr, src_type);
+		break;
+	default:
+		printk(BIOS_ERR, "Unhandled clk_type: %d, src_type: %u\n", clk_type, src_type);
+		return CB_ERR;
+	}
+
+	return CB_SUCCESS;
+}
+
 static enum cb_err pll_init_and_set(struct x1p42100_ncc0_clock *ncc0, u32 l_val)
 {
 	int ret;
diff --git a/src/soc/qualcomm/x1p42100/include/soc/clock.h b/src/soc/qualcomm/x1p42100/include/soc/clock.h
index e9b827b0fe..2076699769 100644
--- a/src/soc/qualcomm/x1p42100/include/soc/clock.h
+++ b/src/soc/qualcomm/x1p42100/include/soc/clock.h
@@ -12,11 +12,13 @@
 #define GPLL0_EVEN_HZ		(300 * MHz)
 #define GPLL0_MAIN_HZ		(600 * MHz)
 #define CLK_100MHZ		(100 * MHz)
+#define CLK_200MHZ		(200 * MHz)
 
 /* CPU PLL*/
 #define L_VAL_1363P2MHz		0x47
 
 #define PCIE_PHY_RCHNG_FREQ CLK_100MHZ
+#define USB3_MASTER_CLK_MIN_FREQ_HZ CLK_200MHZ
 
 #define QUPV3_WRAP0_CLK_ENA_S(idx)		(10 + idx)
 #define QUPV3_WRAP1_CLK_ENA_S(idx)		(22 + idx)
@@ -215,68 +217,117 @@ struct x1p42100_gcc {
 	struct x1p42100_gpll gpll0;
 	u8 _res0[0x10004 - 0x0002c];
 	struct x1p42100_pcie_noc pcie_noc;
-	u8 _res1[0x18004 - 0x10054];
-
+	u8 _res1[0x1200C - 0x10054];
+	u32 qusb2phy_hs0_mp_bcr;
+	u32 qusb2phy_hs1_mp_bcr;
+	u8 _res2[0x17000 - 0x12014];
+	u32 gcc_usb30_mp_bcr;
+	u32 gcc_usb30_mp_gdscr;
+	u8 _res3[0x17018 - 0x17008];
+	u32 gcc_usb30_mp_master_cbcr;
+	u8 _res4[0x17024 - 0x1701C];
+	u32 gcc_usb30_mp_sleep_cbcr;
+	u32 gcc_usb30_mp_mock_utmi_cbcr;
+	struct clock_rcg usb30_mp_master_rcg;
+	u8 _res5[0x17288 - 0x17034];
+	u32 gcc_usb3_mp_phy_aux_cbcr;
+	u32 gcc_usb3_mp_phy_com_aux_cbcr;
+	u32 gcc_usb3_mp_phy_pipe_0_cbcr;
+	u32 gcc_usb3_mp_phy_pipe_0_muxr;
+	u32 gcc_usb3_mp_phy_pipe_1_cbcr;
+	u32 gcc_usb3_mp_phy_pipe_1_muxr;
+	u8 _res6[0x173CC - 0x172A0];
+	u32 gcc_cfg_noc_usb3_mp_axi_cbcr;
+	u32 gcc_aggre_usb3_mp_axi_cbcr;
+	u8 _res7[0x18004 - 0x173D4];
 	struct qupv3_clock qup_wrap1_s[8];
-	u8 _res2[0x1e004 - 0x189c4];
+	u8 _res8[0x19000 - 0x189c4];
+	u32 usb3_uniphy_mp0_bcr;
+	u32 usb3uniphy_phy_mp0_bcr;
+	u8 _res9[0x1900c - 0x19008];
+	u32 gcc_usb3_mp_ss0_phy_gdscr;
+	u8 _res10[0x1e004 - 0x19010];
 	struct qupv3_clock qup_wrap2_s[8];
-	u8 _res3[0x23000 - 0x1e9c4];
+	u8 _res11[0x23000 - 0x1e9c4];
 	u32 qup_wrap0_m_ahb_cbcr;
 	u32 qup_wrap0_s_ahb_cbcr;
 	u32 qup_wrap0_core_cbcr;
-	u8 _res4[0x23014 - 0x2300c];
+	u8 _res12[0x23014 - 0x2300c];
 	u32 qup_wrap0_core_cdivr;
 	u32 qup_wrap0_core_2x_cbcr;
-	u8 _res5[0x23024 - 0x2301c];
+	u8 _res13[0x23024 - 0x2301c];
 	struct clock_rcg qup_wrap0_core_2x;
-	u8 _res6[0x23150 - 0x2302c];
+	u8 _res14[0x23150 - 0x2302c];
 	u32 qup_wrap1_m_ahb_cbcr;
 	u32 qup_wrap1_s_ahb_cbcr;
 	u32 qup_wrap1_core_cbcr;
-	u8 _res7[0x23164 - 0x2315c];
+	u8 _res15[0x23164 - 0x2315c];
 	u32 qup_wrap1_core_cdivr;
 	u32 qup_wrap1_core_2x_cbcr;
-	u8 _res8[0x23174 - 0x2316c];
+	u8 _res16[0x23174 - 0x2316c];
 	struct clock_rcg qup_wrap1_core_2x;
-	u8 _res9[0x232a0 - 0x2317c];
+	u8 _res17[0x232a0 - 0x2317c];
 	u32 qup_wrap2_m_ahb_cbcr;
 	u32 qup_wrap2_s_ahb_cbcr;
 	u32 qup_wrap2_core_cbcr;
-	u8 _res10[0x232b4 - 0x232ac];
+	u8 _res18[0x232b4 - 0x232ac];
 	u32 qup_wrap2_core_cdivr;
 	u32 qup_wrap2_core_2x_cbcr;
-	u8 _res11[0x232c4 - 0x232bc];
+	u8 _res19[0x232c4 - 0x232bc];
 	struct clock_rcg qup_wrap2_core_2x;
-	u8 _res12[0x31000 - 0x232cc];
+	u8 _res20[0x2D014 - 0x232cc];
+	u32 gcc_sys_noc_usb_axi_cbcr;
+	u8 _res21[0x2D028 - 0x2D018];
+	u32 gcc_cfg_noc_usb_anoc_north_ahb_cbcr;
+	u32 gcc_cfg_noc_usb_anoc_south_ahb_cbcr;
+	u8 _res22[0x2D034 - 0x2D030];
+	u32 gcc_aggre_usb_noc_axi_cbcr;
+	u8 _res23[0x2D174 - 0x2D038];
+	u32 gcc_aggre_noc_usb_south_axi_cbcr;
+	u8 _res24[0x2D17C - 0x2D178];
+	u32 gcc_aggre_noc_usb_north_axi_cbcr;
+	u8 _res25[0x31000 - 0x2D180];
 	struct x1p42100_pcie pcie_6a;
-	u8  res13[0x42004-0x3108c];
+	u8  res26[0x39000-0x3108c];
+	u32 usb30_prim_bcr;
+	u8  res27[0x42004-0x39004];
 	struct qupv3_clock qup_wrap0_s[8];
-	u8 _res14[0x4b000 - 0x429c4];
+	u8 _res28[0x4b000 - 0x429c4];
 	u32 qspi_bcr;
 	u32 qspi_cnoc_ahb_cbcr;
 	u32 qspi_core_cbcr;
 	struct clock_rcg qspi_core;
-	u8 _res15[0x52000 - 0x4b014];
+	u8 _res29[0x52000 - 0x4b014];
 	u32 apcs_clk_br_en;
-	u8 _res16[0x52008 - 0x52004];
+	u8 _res30[0x52008 - 0x52004];
 	u32 apcs_clk_br_en1;
-	u8 _res17[0x52010 - 0x5200c];
+	u8 _res31[0x52010 - 0x5200c];
 	u32 apcs_clk_br_en2;
-	u8 _res18[0x52018 - 0x52014];
+	u8 _res32[0x52018 - 0x52014];
 	u32 apcs_clk_br_en3;
-	u8 _res19[0x52020 - 0x5201c];
+	u8 _res33[0x52020 - 0x5201c];
 	u32 apcs_clk_br_en4;
-	u8 _res20[0x52028 - 0x52024];
+	u8 _res34[0x52028 - 0x52024];
 	u32 apcs_clk_br_en5;
-	u8 _res21[0x52030 - 0x5202c];
+	u8 _res35[0x52030 - 0x5202c];
 	u32 apcs_pll_br_en;
-	u8 _res22[0x8e000 - 0x52034];
+	u8 _res36[0x54000 - 0x52034];
+	u32 usb3_uniphy_mp1_bcr;
+	u32 usb3uniphy_phy_mp1_bcr;
+	u32 gcc_usb3_mp_ss1_phy_bcr;
+	u32 gcc_usb3_mp_ss1_phy_gdscr;
+	u8 _res37[0x8e000 - 0x54010];
 	u32 pcie_6_phy_gdscr;
-	u8 _res23[0xac01c - 0x8e004];
+	u8 _res38[0xac01c - 0x8e004];
 	u32 pcie_6a_phy_bcr;
 };
-
+check_member(x1p42100_gcc, qusb2phy_hs1_mp_bcr, 0x12010);
+check_member(x1p42100_gcc, gcc_usb30_mp_bcr, 0x17000);
 check_member(x1p42100_gcc, qup_wrap1_s, 0x18004);
+check_member(x1p42100_gcc, gcc_usb30_mp_master_cbcr, 0x17018);
+check_member(x1p42100_gcc, gcc_usb30_mp_sleep_cbcr, 0x17024);
+check_member(x1p42100_gcc, gcc_usb3_mp_phy_aux_cbcr, 0x17288);
+check_member(x1p42100_gcc, gcc_cfg_noc_usb3_mp_axi_cbcr, 0x173CC);
 check_member(x1p42100_gcc, qup_wrap2_s, 0x1e004);
 check_member(x1p42100_gcc, qup_wrap0_m_ahb_cbcr, 0x23000);
 check_member(x1p42100_gcc, qup_wrap0_core_cdivr, 0x23014);
@@ -287,6 +338,11 @@ check_member(x1p42100_gcc, qup_wrap1_core_2x, 0x23174);
 check_member(x1p42100_gcc, qup_wrap2_m_ahb_cbcr, 0x232a0);
 check_member(x1p42100_gcc, qup_wrap2_core_cdivr, 0x232b4);
 check_member(x1p42100_gcc, qup_wrap2_core_2x, 0x232c4);
+check_member(x1p42100_gcc, gcc_sys_noc_usb_axi_cbcr, 0x2D014);
+check_member(x1p42100_gcc, gcc_cfg_noc_usb_anoc_north_ahb_cbcr, 0x2D028);
+check_member(x1p42100_gcc, gcc_aggre_usb_noc_axi_cbcr, 0x2D034);
+check_member(x1p42100_gcc, gcc_aggre_noc_usb_south_axi_cbcr, 0x2D174);
+check_member(x1p42100_gcc, gcc_aggre_noc_usb_north_axi_cbcr, 0x2D17C);
 check_member(x1p42100_gcc, qup_wrap0_s, 0x42004);
 check_member(x1p42100_gcc, qspi_bcr, 0x4b000);
 check_member(x1p42100_gcc, apcs_clk_br_en, 0x52000);
@@ -376,21 +432,61 @@ enum clk_pcie {
 	PCIE_6A_PIPE_MUXR,
 	PCIE_CLK_COUNT,
 };
+
+enum clk_usb_gdsc {
+	USB30_MP_GDSC,
+	USB3_SS0_PHY_GDSC,
+	USB3_SS1_PHY_GDSC,
+	MAX_USB_GDSC,
+};
+enum clk_usb {
+	USB30_MP_MASTER_CBCR,
+	USB30_MP_SLEEP_CBCR,
+	USB30_MP_MOCK_UTMI_CBCR,
+	USB3_MP_PHY_AUX_CBCR,
+	USB3_MP_PHY_COM_AUX_CBCR,
+	USB3_MP_PHY_PIPE_0_CBCR,
+	USB3_MP_PHY_PIPE_1_CBCR,
+	CFG_NOC_USB3_MP_AXI_CBCR,
+	AGGRE_USB3_MP_AXI_CBCR,
+	SYS_NOC_USB_AXI_CBCR,
+	CFG_NOC_USB_ANOC_NORTH_AHB_CBCR,
+	CFG_NOC_USB_ANOC_SOUTH_AHB_CBCR,
+	AGGRE_USB_NOC_AXI_CBCR,
+	AGGRE_NOC_USB_SOUTH_AXI_CBCR,
+	AGGRE_NOC_USB_NORTH_AXI_CBCR,
+	USB_CLK_COUNT,
+};
+
+enum clk_pipe_usb {
+	USB3_PHY_PIPE_0,
+	USB3_PHY_PIPE_1,
+	USB3_PIPE_CLK_COUNT
+};
+
+enum clk_usb_phy_src_sel {
+		USB_PHY_PIPE_SRC_SEL = 0,
+		USB_PHY_XO_SRC_SEL = 2,
+};
+
 enum subsystem_reset {
 	AOP_RESET_SHFT,
 	CORE_SW_RESET,
 };
 
-/* TODO: update as per datasheet */
 void clock_init(void);
 void clock_configure_qspi(uint32_t hz);
 void clock_enable_qup(int qup);
 void clock_configure_dfsr(int qup);
 void clock_configure_pcie(void);
+void clock_configure_usb(void);
 enum cb_err clock_enable_gdsc(enum clk_gdsc gdsc_type);
 enum cb_err clock_enable_pcie(enum clk_pcie clk_type);
 enum cb_err clock_configure_mux(enum clk_pcie clk_type, u32 src_type);
-
+enum cb_err usb_clock_configure_mux(enum clk_pipe_usb clk_type, u32 src_type);
+enum cb_err usb_clock_enable(enum clk_usb clk_type);
+enum cb_err clock_enable_usb_gdsc(enum clk_usb_gdsc gdsc_type);
+void usb_clock_reset(enum clk_usb clk_type, bool assert);
 /* Subsystem Reset */
 static struct aoss *const aoss = (void *)AOSS_CC_BASE;
 static struct x1p42100_gcc *const gcc = (void *)GCC_BASE;

From 84ec1493a30473e1f92876c12184bf3352dd5e02 Mon Sep 17 00:00:00 2001
From: Jeremy Compostella <jeremy.compostella@intel.com>
Date: Thu, 4 Sep 2025 11:42:19 -0700
Subject: [PATCH 1979/3886] drivers/wifi/generic: Fix typo in header guard
 comment

The header guard comment in the chip.h file was incorrect, using
_GENERIC_WIFI_H_ instead of the correct _WIFI_GENERIC_H_. This
commit corrects the typo to ensure consistency.

Change-Id: I00a93e811608ddf449065bc92441648f7332fc4b
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89055
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jamie Ryu <jamie.m.ryu@intel.com>
---
 src/drivers/wifi/generic/chip.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/drivers/wifi/generic/chip.h b/src/drivers/wifi/generic/chip.h
index e53459a864..0de153aa3c 100644
--- a/src/drivers/wifi/generic/chip.h
+++ b/src/drivers/wifi/generic/chip.h
@@ -32,4 +32,4 @@ struct drivers_wifi_generic_config {
 	DEVTREE_CONST struct device *bluetooth_companion;
 };
 
-#endif /* _GENERIC_WIFI_H_ */
+#endif /* _WIFI_GENERIC_H_ */

From 3f926bc11056bdb6e3912dec778c37f28320d171 Mon Sep 17 00:00:00 2001
From: Jeremy Compostella <jeremy.compostella@intel.com>
Date: Thu, 4 Sep 2025 14:51:26 -0700
Subject: [PATCH 1980/3886] commonlib/bsd: Add Bluetooth wake source in ELOG
 event data

This commit introduces a new constant, ELOG_WAKE_SOURCE_PME_BLUETOOTH,
with the value 0x31 to represent Bluetooth as a wake source in the ELOG
event data structure. This change facilitates diagnostics and
event logging related to Bluetooth activity.

The cbfstool eventlog has been updated to include "PME - BLUETOOTH" in
the wake source types for event data printing.

Change-Id: Ib628502ddcccb4a781394a39b2aee6efa05ecf84
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89059
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jamie Ryu <jamie.m.ryu@intel.com>
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
---
 src/commonlib/bsd/include/commonlib/bsd/elog.h | 1 +
 util/cbfstool/eventlog.c                       | 1 +
 2 files changed, 2 insertions(+)

diff --git a/src/commonlib/bsd/include/commonlib/bsd/elog.h b/src/commonlib/bsd/include/commonlib/bsd/elog.h
index 01f97f6957..4b45f8dda6 100644
--- a/src/commonlib/bsd/include/commonlib/bsd/elog.h
+++ b/src/commonlib/bsd/include/commonlib/bsd/elog.h
@@ -197,6 +197,7 @@ struct elog_ec_event {
 #define  ELOG_WAKE_SOURCE_PME_TCSS_XHCI    0x2e
 #define  ELOG_WAKE_SOURCE_PME_TCSS_XDCI    0x2f
 #define  ELOG_WAKE_SOURCE_PME_TCSS_DMA     0x30
+#define  ELOG_WAKE_SOURCE_PME_BLUETOOTH    0x31
 
 struct elog_event_data_wake {
 	uint8_t source;
diff --git a/util/cbfstool/eventlog.c b/util/cbfstool/eventlog.c
index 2312b75f8b..74112fb468 100644
--- a/util/cbfstool/eventlog.c
+++ b/util/cbfstool/eventlog.c
@@ -321,6 +321,7 @@ static int eventlog_print_data(const struct event_header *event)
 		{ELOG_WAKE_SOURCE_PME_TCSS_XHCI, "PME - TCSS XHCI"},
 		{ELOG_WAKE_SOURCE_PME_TCSS_XDCI, "PME - TCSS XDCI"},
 		{ELOG_WAKE_SOURCE_PME_TCSS_DMA, "PME - TCSS DMA"},
+		{ELOG_WAKE_SOURCE_PME_BLUETOOTH, "PME - BLUETOOTH"},
 		{0, NULL},
 	};
 	static const struct valstr ec_event_types[] = {

From 1028f3e846d6f4619387b46738aa51c1e9601835 Mon Sep 17 00:00:00 2001
From: Jeremy Compostella <jeremy.compostella@intel.com>
Date: Thu, 4 Sep 2025 14:36:49 -0700
Subject: [PATCH 1981/3886] soc/intel/pantherlake: Add Bluetooth to PME wake
 source mapping

This commit adds support for logging Bluetooth device wake events in the
Pantherlake platform. It improves visibility into wake events triggered
by Bluetooth devices, which is crucial for debugging and power
management analysis.

Change-Id: I36bb08075e79ab3151cfdaf41ace2121aaac0973
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89057
Reviewed-by: Cliff Huang <cliff.huang@intel.com>
Reviewed-by: Jamie Ryu <jamie.m.ryu@intel.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/soc/intel/pantherlake/elog.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/src/soc/intel/pantherlake/elog.c b/src/soc/intel/pantherlake/elog.c
index e5a6a9a3cf..90c5068643 100644
--- a/src/soc/intel/pantherlake/elog.c
+++ b/src/soc/intel/pantherlake/elog.c
@@ -64,6 +64,7 @@ static void pch_log_pme_internal_wake_source(void)
 		{ PCI_DEVFN_XHCI,	ELOG_WAKE_SOURCE_PME_XHCI },
 		{ PCI_DEVFN_USBOTG,	ELOG_WAKE_SOURCE_PME_XDCI },
 		{ PCI_DEVFN_CNVI_WIFI,	ELOG_WAKE_SOURCE_PME_WIFI },
+		{ PCI_DEVFN_CNVI_BT,	ELOG_WAKE_SOURCE_PME_BLUETOOTH },
 #if CONFIG(SOC_INTEL_PANTHERLAKE)
 		{ PCI_DEVFN_TCSS_XDCI,	ELOG_WAKE_SOURCE_PME_TCSS_XDCI },
 #endif

From a6c15129a79757e764726a0109b3f995bb4f1705 Mon Sep 17 00:00:00 2001
From: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
Date: Tue, 9 Sep 2025 18:15:07 +0800
Subject: [PATCH 1982/3886] mb/google/fatcat/var/moonstone: Generate SPD ID for
 memory module

Add the memory parts: H58G66CK8BX147 (Hynix) in mem_parts_used.txt
,and generate SPD id for the parts.

BUG=none
TEST=Run part_id_gen tool and check the generated files.

Change-Id: I485d8f947b6d8efc5b43ea1ddf1e4187eb4cf2bb
Signed-off-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89119
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
---
 .../google/fatcat/variants/moonstone/memory/Makefile.mk         | 2 +-
 .../fatcat/variants/moonstone/memory/dram_id.generated.txt      | 1 +
 .../google/fatcat/variants/moonstone/memory/mem_parts_used.txt  | 1 +
 3 files changed, 3 insertions(+), 1 deletion(-)

diff --git a/src/mainboard/google/fatcat/variants/moonstone/memory/Makefile.mk b/src/mainboard/google/fatcat/variants/moonstone/memory/Makefile.mk
index da3bfa3b2d..4b3374bf05 100644
--- a/src/mainboard/google/fatcat/variants/moonstone/memory/Makefile.mk
+++ b/src/mainboard/google/fatcat/variants/moonstone/memory/Makefile.mk
@@ -6,4 +6,4 @@
 SPD_SOURCES =
 SPD_SOURCES += spd/lp5/set-0/spd-7.hex      # ID = 0(0b0000)  Parts = H58G56BK7BX068
 SPD_SOURCES += spd/lp5/set-0/spd-11.hex      # ID = 1(0b0001)  Parts = MT62F1G32D2DS-023 WT:C, H58G56CK8BX146
-SPD_SOURCES += spd/lp5/set-0/spd-10.hex      # ID = 2(0b0010)  Parts = MT62F2G32D4DS-020 WT:F, MT62F2G32D4DS-023 WT:C
+SPD_SOURCES += spd/lp5/set-0/spd-10.hex      # ID = 2(0b0010)  Parts = MT62F2G32D4DS-020 WT:F, MT62F2G32D4DS-023 WT:C, H58G66CK8BX147
diff --git a/src/mainboard/google/fatcat/variants/moonstone/memory/dram_id.generated.txt b/src/mainboard/google/fatcat/variants/moonstone/memory/dram_id.generated.txt
index b90e238b88..b1e522b4f7 100644
--- a/src/mainboard/google/fatcat/variants/moonstone/memory/dram_id.generated.txt
+++ b/src/mainboard/google/fatcat/variants/moonstone/memory/dram_id.generated.txt
@@ -9,3 +9,4 @@ MT62F1G32D2DS-023 WT:C         1 (0001)
 MT62F2G32D4DS-020 WT:F         2 (0010)
 H58G56CK8BX146                 1 (0001)
 MT62F2G32D4DS-023 WT:C         2 (0010)
+H58G66CK8BX147                 2 (0010)
diff --git a/src/mainboard/google/fatcat/variants/moonstone/memory/mem_parts_used.txt b/src/mainboard/google/fatcat/variants/moonstone/memory/mem_parts_used.txt
index f4a5069bb5..a78826b02c 100644
--- a/src/mainboard/google/fatcat/variants/moonstone/memory/mem_parts_used.txt
+++ b/src/mainboard/google/fatcat/variants/moonstone/memory/mem_parts_used.txt
@@ -14,3 +14,4 @@ MT62F1G32D2DS-023 WT:C
 MT62F2G32D4DS-020 WT:F
 H58G56CK8BX146
 MT62F2G32D4DS-023 WT:C
+H58G66CK8BX147

From 859cc31e3a4476d4fc85904bb263acdb1d813739 Mon Sep 17 00:00:00 2001
From: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
Date: Mon, 8 Sep 2025 18:00:04 +0800
Subject: [PATCH 1983/3886] mb/google/brox/jubilant: Generate RAM IDs

Generate RAM IDs of lp5 memory Hyinx H58G56CK8BX146

BUG=b:424055256
TEST=Run part_id_gen tool and check the generated files.

Change-Id: Ieb4cf2a317afaee81add0c99557f8a4cdbba042f
Signed-off-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89101
Reviewed-by: Kenneth Chan <kenneth.chan@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
---
 src/mainboard/google/brox/variants/jubilant/memory/Makefile.mk  | 2 +-
 .../google/brox/variants/jubilant/memory/dram_id.generated.txt  | 1 +
 .../google/brox/variants/jubilant/memory/mem_parts_used.txt     | 1 +
 3 files changed, 3 insertions(+), 1 deletion(-)

diff --git a/src/mainboard/google/brox/variants/jubilant/memory/Makefile.mk b/src/mainboard/google/brox/variants/jubilant/memory/Makefile.mk
index 38855d85a0..095dd3282a 100644
--- a/src/mainboard/google/brox/variants/jubilant/memory/Makefile.mk
+++ b/src/mainboard/google/brox/variants/jubilant/memory/Makefile.mk
@@ -6,5 +6,5 @@
 SPD_SOURCES =
 SPD_SOURCES += spd/lp5/set-0/spd-1.hex      # ID = 0(0b0000)  Parts = MT62F512M32D2DR-031 WT:B, H9JCNNNBK3MLYR-N6E
 SPD_SOURCES += spd/lp5/set-0/spd-2.hex      # ID = 1(0b0001)  Parts = MT62F1G32D4DR-031 WT:B
-SPD_SOURCES += spd/lp5/set-0/spd-11.hex      # ID = 2(0b0010)  Parts = MT62F1G32D2DS-023 WT:B, H58G56BK8BX068
+SPD_SOURCES += spd/lp5/set-0/spd-11.hex      # ID = 2(0b0010)  Parts = MT62F1G32D2DS-023 WT:B, H58G56BK8BX068, H58G56CK8BX146
 SPD_SOURCES += spd/lp5/set-0/spd-7.hex      # ID = 3(0b0011)  Parts = K3KL8L80CM-MGCT
diff --git a/src/mainboard/google/brox/variants/jubilant/memory/dram_id.generated.txt b/src/mainboard/google/brox/variants/jubilant/memory/dram_id.generated.txt
index 589410b2b1..7c8f85d4c9 100644
--- a/src/mainboard/google/brox/variants/jubilant/memory/dram_id.generated.txt
+++ b/src/mainboard/google/brox/variants/jubilant/memory/dram_id.generated.txt
@@ -10,3 +10,4 @@ MT62F1G32D4DR-031 WT:B         1 (0001)
 MT62F1G32D2DS-023 WT:B         2 (0010)
 H58G56BK8BX068                 2 (0010)
 K3KL8L80CM-MGCT                3 (0011)
+H58G56CK8BX146                 2 (0010)
diff --git a/src/mainboard/google/brox/variants/jubilant/memory/mem_parts_used.txt b/src/mainboard/google/brox/variants/jubilant/memory/mem_parts_used.txt
index a09fd75298..a1a7a9932f 100644
--- a/src/mainboard/google/brox/variants/jubilant/memory/mem_parts_used.txt
+++ b/src/mainboard/google/brox/variants/jubilant/memory/mem_parts_used.txt
@@ -4,3 +4,4 @@ MT62F1G32D4DR-031 WT:B
 MT62F1G32D2DS-023 WT:B
 H58G56BK8BX068
 K3KL8L80CM-MGCT
+H58G56CK8BX146

From 7fc414c886cc7b5b75305ed2fabb5b4e8de6e548 Mon Sep 17 00:00:00 2001
From: "wu.garen" <wu.garen@inventec.corp-partner.google.com>
Date: Wed, 27 Aug 2025 18:21:46 +0800
Subject: [PATCH 1984/3886] mb/google/trulo/var/kaladin: Enable EC keyboard
 backlight

Enable EC keyboard backlight for kaladin.

BUG=b:439234109
TEST=emerge-nissa coreboot chromeos-bootimage
     confirm KBLT device appear in DSDT table

Change-Id: I981ca717405a84794390388bf62a97d1c23f33a7
Signed-off-by: wu.garen <wu.garen@inventec.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88970
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 .../google/brya/variants/kaladin/include/variant/ec.h          | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/src/mainboard/google/brya/variants/kaladin/include/variant/ec.h b/src/mainboard/google/brya/variants/kaladin/include/variant/ec.h
index 7a2a6ff8b7..6f104d5da4 100644
--- a/src/mainboard/google/brya/variants/kaladin/include/variant/ec.h
+++ b/src/mainboard/google/brya/variants/kaladin/include/variant/ec.h
@@ -5,4 +5,7 @@
 
 #include <baseboard/ec.h>
 
+/* Enable EC backed Keyboard Backlight in ACPI */
+#define EC_ENABLE_KEYBOARD_BACKLIGHT
+
 #endif

From 2908a955e5b0571a0cb813422849bb6c69f11887 Mon Sep 17 00:00:00 2001
From: David Wu <david_wu@quanta.corp-partner.google.com>
Date: Tue, 9 Sep 2025 10:22:16 +0800
Subject: [PATCH 1985/3886] mb/google/rex/var/kanix: Add H58G56CK8BX146 to RAM
 ID table

Add the new memory support: Hynix H58G56CK8BX146

BUG=b:443613820
TEST=Run part_id_gen tool and check the generated files.

Change-Id: I9fb1b3fb212f0c45e73103d1e13a3abc1e3a3d74
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89104
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/google/rex/variants/kanix/memory/Makefile.mk      | 2 +-
 .../google/rex/variants/kanix/memory/dram_id.generated.txt      | 1 +
 .../google/rex/variants/kanix/memory/mem_parts_used.txt         | 1 +
 3 files changed, 3 insertions(+), 1 deletion(-)

diff --git a/src/mainboard/google/rex/variants/kanix/memory/Makefile.mk b/src/mainboard/google/rex/variants/kanix/memory/Makefile.mk
index 97caca3e72..790f8b7cbe 100644
--- a/src/mainboard/google/rex/variants/kanix/memory/Makefile.mk
+++ b/src/mainboard/google/rex/variants/kanix/memory/Makefile.mk
@@ -4,6 +4,6 @@
 # util/spd_tools/bin/part_id_gen MTL lp5 src/mainboard/google/rex/variants/kanix/memory src/mainboard/google/rex/variants/kanix/memory/mem_parts_used.txt
 
 SPD_SOURCES =
-SPD_SOURCES += spd/lp5/set-0/spd-11.hex      # ID = 0(0b0000)  Parts = MT62F1G32D2DS-023 WT:B, H58G56BK8BX068
+SPD_SOURCES += spd/lp5/set-0/spd-11.hex      # ID = 0(0b0000)  Parts = MT62F1G32D2DS-023 WT:B, H58G56BK8BX068, H58G56CK8BX146
 SPD_SOURCES += spd/lp5/set-0/spd-1.hex      # ID = 1(0b0001)  Parts = H9JCNNNBK3MLYR-N6E, MT62F512M32D2DR-031 WT:B
 SPD_SOURCES += spd/lp5/set-0/spd-7.hex      # ID = 2(0b0010)  Parts = K3KL8L80CM-MGCT
diff --git a/src/mainboard/google/rex/variants/kanix/memory/dram_id.generated.txt b/src/mainboard/google/rex/variants/kanix/memory/dram_id.generated.txt
index 2cc130c2f9..7587b991a8 100644
--- a/src/mainboard/google/rex/variants/kanix/memory/dram_id.generated.txt
+++ b/src/mainboard/google/rex/variants/kanix/memory/dram_id.generated.txt
@@ -9,3 +9,4 @@ H9JCNNNBK3MLYR-N6E             1 (0001)
 H58G56BK8BX068                 0 (0000)
 K3KL8L80CM-MGCT                2 (0010)
 MT62F512M32D2DR-031 WT:B       1 (0001)
+H58G56CK8BX146                 0 (0000)
diff --git a/src/mainboard/google/rex/variants/kanix/memory/mem_parts_used.txt b/src/mainboard/google/rex/variants/kanix/memory/mem_parts_used.txt
index 42d8a4ee05..b1d3b93dfb 100644
--- a/src/mainboard/google/rex/variants/kanix/memory/mem_parts_used.txt
+++ b/src/mainboard/google/rex/variants/kanix/memory/mem_parts_used.txt
@@ -14,3 +14,4 @@ H9JCNNNBK3MLYR-N6E
 H58G56BK8BX068
 K3KL8L80CM-MGCT
 MT62F512M32D2DR-031 WT:B
+H58G56CK8BX146

From 96eb6a3ac19118c7c6b94cc7b104f60dbe6e6a44 Mon Sep 17 00:00:00 2001
From: Hari L <haril@qualcomm.corp-partner.google.com>
Date: Wed, 10 Sep 2025 17:57:07 +0530
Subject: [PATCH 1986/3886] soc/qualcomm/x1p42100: Add USB Type-A Host support

Add support for HS-PHY/SS-PHY and DWC3 USB controllers
for USB Type A Host support.

TEST = Ensure that pipe/utmi clocks are ON and check
port link status to confirm USB connect.

Change-Id: Ife08801062da5a8f87491b020b3828c246aadea8
Signed-off-by: Hari L <haril@qualcomm.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89132
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/soc/qualcomm/x1p42100/Makefile.mk         |   3 +
 .../x1p42100/include/soc/addressmap.h         |  39 +-
 .../x1p42100/include/soc/usb/qmp_usb_phy.h    |  36 ++
 .../x1p42100/include/soc/usb/snps_usb_phy.h   | 125 +++++
 .../qualcomm/x1p42100/include/soc/usb/usb.h   |  76 +++
 src/soc/qualcomm/x1p42100/usb/qmpv4_usb_phy.c | 498 ++++++++++++++++++
 src/soc/qualcomm/x1p42100/usb/snps_usb_phy.c  | 239 +++++++++
 src/soc/qualcomm/x1p42100/usb/usb.c           | 327 ++++++++++++
 8 files changed, 1338 insertions(+), 5 deletions(-)
 create mode 100644 src/soc/qualcomm/x1p42100/include/soc/usb/qmp_usb_phy.h
 create mode 100644 src/soc/qualcomm/x1p42100/include/soc/usb/snps_usb_phy.h
 create mode 100644 src/soc/qualcomm/x1p42100/include/soc/usb/usb.h
 create mode 100644 src/soc/qualcomm/x1p42100/usb/qmpv4_usb_phy.c
 create mode 100644 src/soc/qualcomm/x1p42100/usb/snps_usb_phy.c
 create mode 100644 src/soc/qualcomm/x1p42100/usb/usb.c

diff --git a/src/soc/qualcomm/x1p42100/Makefile.mk b/src/soc/qualcomm/x1p42100/Makefile.mk
index fb82673a15..c7e39a8a12 100644
--- a/src/soc/qualcomm/x1p42100/Makefile.mk
+++ b/src/soc/qualcomm/x1p42100/Makefile.mk
@@ -43,6 +43,9 @@ ramstage-y += soc.c
 ramstage-y += cbmem.c
 ramstage-y += ../common/mmu.c
 ramstage-$(CONFIG_DRIVERS_UART) += ../common/qupv3_uart.c
+ramstage-y += usb/usb.c
+ramstage-y += usb/snps_usb_phy.c
+ramstage-y += usb/qmpv4_usb_phy.c
 ramstage-$(CONFIG_PCI) += ../common/pcie_common.c
 ramstage-y += ../common/spmi.c
 ramstage-$(CONFIG_PCI) += pcie.c
diff --git a/src/soc/qualcomm/x1p42100/include/soc/addressmap.h b/src/soc/qualcomm/x1p42100/include/soc/addressmap.h
index bfb51ad7b2..21341df24d 100644
--- a/src/soc/qualcomm/x1p42100/include/soc/addressmap.h
+++ b/src/soc/qualcomm/x1p42100/include/soc/addressmap.h
@@ -31,9 +31,7 @@
 #define GPIO_FUNC_QSPI_DATA_1		GPIO129_FUNC_QSPI0_DATA_1
 #define GPIO_FUNC_QSPI_CLK		GPIO127_FUNC_QSPI0_CLK
 
-/*
- * QUP SERIAL ENGINE BASE ADDRESSES
- */
+/* QUP SERIAL ENGINE BASE ADDRESSES */
 /* QUPV3_0 */
 #define QUP_SERIAL0_BASE		0x00B80000
 #define QUP_SERIAL1_BASE		0x00B84000
@@ -70,6 +68,22 @@
 #define QUP_WRAP2_BASE			0x008C0000
 #define QUP_2_GSI_BASE			0x00804000
 
+/* USB BASE ADDRESSES */
+#define HS_USB_MP0_PHY_BASE		0x088e1000
+#define HS_USB_MP1_PHY_BASE		0x088E2000
+#define QMP_PHY_MP0_QSERDES_COM_REG_BASE	0x088E3000
+#define QMP_PHY_MP0_QSERDES_TX_REG_BASE		0x088E3E00
+#define QMP_PHY_MP0_QSERDES_RX_REG_BASE		0x088E4000
+#define QMP_PHY_MP0_PCS_REG_BASE			0x088E3200
+#define QMP_PHY_MP0_PCS_USB3_REG_BASE		0x088E4200
+#define USB_HOST_DWC3_BASE					0x0a40c100
+
+#define QMP_PHY_MP1_QSERDES_COM_REG_BASE	0x088E5000
+#define QMP_PHY_MP1_QSERDES_TX_REG_BASE		0x088E5E00
+#define QMP_PHY_MP1_QSERDES_RX_REG_BASE		0x088E6000
+#define QMP_PHY_MP1_PCS_REG_BASE			0x088E5200
+#define QMP_PHY_MP1_PCS_USB3_REG_BASE		0x088E6200
+
 /* PCIE 6A */
 #define PCIE6A_PCIE_PARF		0x01BF8000
 #define PCIE6A_GEN1X4_PCIE_DBI		0x70000000
@@ -110,8 +124,23 @@
 #define PCIE6A_BQPHY_PCS_PCIE_LANE1	0x01BFFE00
 
 /* TCSR */
-#define TCSR_GCC_PCIE_4L_CLKREF_EN_PCIE_ENABLE           ((void *)0x1FD512C)
-#define TCSR_PCIE_CTRL_4LN_CONFIG_SEL            ((void *)0x1FDA000)
+#define TCSR_GCC_PCIE_4L_CLKREF_EN_PCIE_ENABLE	((void *)0x1FD512C)
+#define TCSR_PCIE_CTRL_4LN_CONFIG_SEL	((void *)0x1FDA000)
+
+#define TCSR_GCC_CXO_1_REFGEN_BIAS_SEL__SEL_REFGEN_ADDR		((void *)0x1FD511C)
+#define TCSR_GCC_CXO_0_REFGEN_BIAS_SEL__SEL_REFGEN_ADDR		((void *)0x1FD5134)
+
+#define TCSR_QREFS_CXO_0_RPT3_CONFIG_ADDR			((void *)0x1FD5014)
+#define TCSR_QREFS_CXO_0_RPT4_CONFIG_ADDR			((void *)0x1FD5018)
+#define TCSR_QREFS_CXO_1_RPT0_CONFIG_ADDR			((void *)0x1FD5000)
+#define TCSR_QREFS_CXO_1_RX3_CONFIG_ADDR			((void *)0x1FD502C)
+#define TCSR_QREFS_CXO_1_RX0_CONFIG_ADDR			((void *)0x1FD5020)
+#define TCSR_QREFS_CXO_0_RX3_CONFIG_ADDR			((void *)0x1FD5030)
+#define TCSR_QREFS_CXO_0_RX4_CONFIG_ADDR			((void *)0x1FD5034)
+
+#define TCSR_GCC_USB3_MP0_CLKREF_EN_ADDR	((void *)0x1FD510C)
+#define TCSR_GCC_USB3_MP1_CLKREF_EN_ADDR	((void *)0x1FD5110)
+#define USB3_CLKREF_ENABLE_VALUE			0x1
 
 /* SPMI PMIC ARB */
 #define SPMI_PMIC_ARB_CORE_BASE		0x0C400000
diff --git a/src/soc/qualcomm/x1p42100/include/soc/usb/qmp_usb_phy.h b/src/soc/qualcomm/x1p42100/include/soc/usb/qmp_usb_phy.h
new file mode 100644
index 0000000000..e463c61b82
--- /dev/null
+++ b/src/soc/qualcomm/x1p42100/include/soc/usb/qmp_usb_phy.h
@@ -0,0 +1,36 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <device/mmio.h>
+
+/* USB3PHY_PCIE_USB3_PCS_PCS_STATUS bit */
+#define USB3_PCS_PHYSTATUS		BIT(6)
+
+/* Define qmp_phy_init_tbl to use offsets instead of absolute addresses.
+This makes the tables generic and reusable */
+typedef struct qmp_phy_init_tbl {
+	u32 offset; // Offset from the base address of the register block
+	u32 val;
+} qmp_phy_init_tbl_t;
+
+/* Structure to encapsulate base addresses and configuration tables for a specific PHY instance */
+struct ss_usb_phy_reg {
+	void *com_base;
+	void *tx_base;
+	void *rx_base;
+	void *pcs_base;
+	void *pcs_usb3_base;
+	const char *name;
+	/* Init sequence for QMP PHY blocks - serdes, tx, rx, pcs */
+	const qmp_phy_init_tbl_t *serdes_tbl;
+	int serdes_tbl_num;
+	const qmp_phy_init_tbl_t *tx_tbl;
+	int tx_tbl_num;
+	const qmp_phy_init_tbl_t *rx_tbl;
+	int rx_tbl_num;
+	const qmp_phy_init_tbl_t *pcs_tbl;
+	int pcs_tbl_num;
+	const qmp_phy_init_tbl_t *pcs_usb3_tbl;
+	int pcs_usb3_tbl_num;
+};
+/* Initialize a specific QMP USB3 PHY instance */
+bool ss_qmp_phy_init(u32 phy_idx);
diff --git a/src/soc/qualcomm/x1p42100/include/soc/usb/snps_usb_phy.h b/src/soc/qualcomm/x1p42100/include/soc/usb/snps_usb_phy.h
new file mode 100644
index 0000000000..cb62b68b1f
--- /dev/null
+++ b/src/soc/qualcomm/x1p42100/include/soc/usb/snps_usb_phy.h
@@ -0,0 +1,125 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <device/mmio.h>
+
+struct hs_usb_phy_reg {
+	/* Revision ID registers */
+	u32 usb_phy_revision_id0;		/* 0x000 */
+	u32 usb_phy_revision_id1;		/* 0x004 */
+	u32 usb_phy_revision_id2;		/* 0x008 */
+	u32 usb_phy_revision_id3;		/* 0x00c */
+
+	/* Debug bus status registers */
+	u32 usb_phy_debug_bus_stat0;		/* 0x010 */
+	u32 usb_phy_debug_bus_stat1;		/* 0x014 */
+	u32 usb_phy_debug_bus_stat2;		/* 0x018 */
+	u32 usb_phy_debug_bus_stat3;		/* 0x01c */
+
+	/* Test and status registers */
+	u32 usb_phy_hs_rx_tester_out_1;	/* 0x020 */
+	u32 usb_phy_charging_det_output;	/* 0x024 */
+	u32 usb_phy_hs_phy_test_out_1;		/* 0x028 */
+	u32 usb_phy_refclk_rxtap_test_status;	/* 0x02c */
+
+	/* UTMI RX status registers */
+	u32 usb_phy_utmi_rx_datal_status;	/* 0x030 */
+	u32 usb_phy_utmi_rx_datah_status;	/* 0x034 */
+	u32 usb_phy_utmi_rx_port_status;	/* 0x038 */
+
+	/* Original UTMI control registers */
+	u32 utmi_ctrl0;				/* 0x03c */
+	u32 utmi_ctrl1;				/* 0x040 */
+
+	/* Extended UTMI control registers */
+	u32 utmi_ctrl2;				/* 0x044 */
+	u32 utmi_ctrl3;				/* 0x048 */
+	u32 utmi_ctrl4;				/* 0x04c */
+	u32 utmi_ctrl5;				/* 0x050 */
+
+	/* HS PHY control registers */
+	u32 hs_phy_ctrl_common0;		/* 0x054 */
+
+	/* Configuration control registers */
+	u32 cfg_ctrl_1;				/* 0x058 */
+	u32 cfg_ctrl_2;				/* 0x05c */
+	u32 cfg_ctrl_3;				/* 0x060 */
+	u32 hs_phy_ctrl2;			/* 0x064 */
+	u32 cfg_ctrl_4;				/* 0x068 */
+
+	/* Additional configuration control registers */
+	u32 cfg_ctrl_5;				/* 0x06c */
+	u32 cfg_ctrl_6;				/* 0x070 */
+	u32 cfg_ctrl_7;				/* 0x074 */
+	u32 cfg_ctrl_8;				/* 0x078 */
+	u32 cfg_ctrl_9;				/* 0x07c */
+	u32 cfg_ctrl_10;			/* 0x080 */
+
+	u32 hs_phy_test1;		/* 0x084 */
+	u32 rx_tester_1_reg0;	/* 0x088 */
+	u32 rx_tester_1_reg1;	/* 0x08c */
+	u32 rx_tester_1_reg2;	/* 0x090 */
+
+	/* Original cfg0 register */
+	u32 cfg0;				/* 0x094 */
+
+	/* Common control registers */
+	u32 utmi_phy_cmn_ctrl0;			/* 0x098 */
+	u32 utmi_phy_cmn_ctrl1;			/* 0x09c */
+
+	/* Original refclk_ctrl register */
+	u32 refclk_ctrl;			/* 0x0a0 */
+
+	/* Power and reset control registers */
+	u32 usb_phy_pwrdown_ctrl;		/* 0x0a4 */
+	u32 usb_phy_test_debug_ctrl;		/* 0x0a8 */
+	u32 usb_phy_reset_ctrl;			/* 0x0ac */
+	u32 usb_phy_ac_en;			/* 0x0b0 */
+	u32 cfg_ctrl_11;			/* 0x0b4 */
+	u32 usb_phy_fsel_sel;			/* 0x0b8 */
+
+	/* Skitter control registers */
+	u32 usb_phy_skitter_ctrl_1;		/* 0x0bc */
+	u32 usb_phy_skitter_ctrl_2;		/* 0x0c0 */
+	u32 usb_phy_skitter_ctrl_3;		/* 0x0c4 */
+	u32 usb_phy_skitter_sticky_no_lsb;	/* 0x0c8 */
+	u32 usb_phy_skitter_sticky_no_msb;	/* 0x0cc */
+	u32 usb_phy_skitter_calib_counter_lsb;	/* 0x0d0 */
+	u32 usb_phy_skitter_calib_counter_msb;	/* 0x0d4 */
+	u32 usb_phy_skitter_mul_cons_lsb;	/* 0x0d8 */
+	u32 usb_phy_skitter_mul_cons_msb;	/* 0x0dc */
+	u32 usb_phy_skitter_mfs_misc_1;		/* 0x0e0 */
+	u32 usb_phy_skitter_mfs_misc_2;		/* 0x0e4 */
+	u32 usb_phy_skitter_spread_detect_range; /* 0x0e8 */
+	u32 usb_phy_skitter_jitter_thrhold;	/* 0x0ec */
+	u32 usb_phy_skitter_status;		/* 0x0f0 */
+	u32 usb_phy_inv_dly_lsb;		/* 0x0f4 */
+	u32 usb_phy_inv_dly_msb;		/* 0x0f8 */
+	u32 usb_phy_eud_connected;		/* 0x0fc */
+	u32 usb_phy_skitter_jitter;		/* 0x100 */
+	u32 usb_phy_test_debug_ctrl_2;		/* 0x104 */
+	u32 eud_present_sel;			/* 0x108 */
+	u32 usb_phy_skitter_tie_jitter_lsb;	/* 0x10c */
+	u32 usb_phy_skitter_tie_jitter_msb;	/* 0x110 */
+	u32 usb_phy_skitter_calib_rodly_1;	/* 0x114 */
+	u32 usb_phy_skitter_calib_rodly_2;	/* 0x118 */
+	u32 usb_phy_skitter_calib_rodly_3;	/* 0x11c */
+
+	/* Reserved registers */
+	u32 usb_phy_reserved_0;			/* 0x120 */
+	u32 usb_phy_reserved_1;			/* 0x124 */
+	u32 usb_phy_reserved_2;			/* 0x128 */
+	u32 usb_phy_reserved_3;			/* 0x12c */
+
+	/* APB access registers */
+	u32 usb_phy_apb_access_cmd;		/* 0x130 */
+	u32 usb_phy_apb_access_status;		/* 0x134 */
+	u32 usb_phy_apb_address;		/* 0x138 */
+	u32 usb_phy_apb_wrdata_lsb;		/* 0x13c */
+	u32 usb_phy_apb_wrdata_msb;		/* 0x140 */
+	u32 usb_phy_apb_rddata_lsb;		/* 0x144 */
+	u32 usb_phy_apb_rddata_msb;		/* 0x148 */
+
+	/* Final skitter registers */
+	u32 usb_phy_skitter_insertion_dly_corr;	/* 0x14c */
+	u32 usb_phy_skitter_pos_edge_corr1;	/* 0x150 */
+};
diff --git a/src/soc/qualcomm/x1p42100/include/soc/usb/usb.h b/src/soc/qualcomm/x1p42100/include/soc/usb/usb.h
new file mode 100644
index 0000000000..4b62392d2f
--- /dev/null
+++ b/src/soc/qualcomm/x1p42100/include/soc/usb/usb.h
@@ -0,0 +1,76 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include "qmp_usb_phy.h"
+
+/* QSCRATCH_GENERAL_CFG register bit offset */
+#define PIPE_UTMI_CLK_SEL			BIT(0)
+#define PIPE3_PHYSTATUS_SW			BIT(3)
+#define PIPE_UTMI_CLK_DIS			BIT(8)
+
+/* Global USB3 Control  Registers */
+#define DWC3_GUSB3PIPECTL_DELAYP1TRANS		BIT(18)
+#define DWC3_GUSB3PIPECTL_PHYSOFTRS		BIT(31)
+#define DWC3_GUSB3PIPECTL_UX_EXIT_IN_PX		BIT(27)
+#define DWC3_GUSB3PIPECTL_P3EXSIGP2		BIT(10)
+#define DWC3_GCTL_PRTCAPDIR(n)			((n) << 12)
+#define DWC3_GCTL_PRTCAP_OTG			3
+#define DWC3_GCTL_PRTCAP_HOST			1
+
+/* Global USB2 PHY Configuration Register */
+#define DWC3_GUSB2PHYCFG_USBTRDTIM(n)		((n) << 10)
+#define DWC3_GUSB2PHYCFG_USB2TRDTIM_MASK	DWC3_GUSB2PHYCFG_USBTRDTIM(0xf)
+#define DWC3_GUSB2PHYCFG_PHYIF(n)		((n) << 3)
+#define DWC3_GUSB2PHYCFG_PHYIF_MASK		DWC3_GUSB2PHYCFG_PHYIF(1)
+#define USBTRDTIM_UTMI_8_BIT			9
+#define UTMI_PHYIF_8_BIT			0
+#define DWC3_GUSB2PHYCFG_ENBLSLPM_MASK	        (0x1 << 0x8)
+#define DWC3_GCTL_SCALEDOWN(n)			((n) << 4)
+#define DWC3_GCTL_SCALEDOWN_MASK		DWC3_GCTL_SCALEDOWN(3)
+#define DWC3_GCTL_DISSCRAMBLE			(1 << 3)
+#define DWC3_GCTL_U2EXIT_LFPS			(1 << 2)
+#define DWC3_GCTL_DSBLCLKGTNG			(1 << 0)
+#define UTMI_CLK_DIS_0					(1 << 8)
+#define UTMI_CLK_SEL_0					(1 << 0)
+#define PIPE3_PHYSTATUS_SW_0			(1 << 3)
+#define PIPE3_SET_PHYSTATUS_SW_0		(1 << 9)
+#define USB3_MP_CGCTL_REG_ADDR			((void *)0x0A4F8828)
+#define USB3_MP_DBM_FSM_EN_BIT			(1 << 1)
+#define USB3_MP_LINK_REGS_1_LU3LFPSRXTIM_ADDR	((void *)0X0A40D090)
+#define USB3_MP_LINK_REGS_0_LU3LFPSRXTIM_ADDR	((void *)0X0A40D010)
+
+#define GEN2_U3_EXIT_RSP_RX_CLK_MASK			(0xFF << 16)
+#define GEN1_U3_EXIT_RSP_RX_CLK_MASK			(0xFF << 0)
+
+#define GEN2_U3_EXIT_RSP_RX_CLK_VALUE			(0x06 << 16)
+#define GEN1_U3_EXIT_RSP_RX_CLK_VALUE			(0x05 << 0)
+
+#define LFPS_RSP_RX_CLK_CLR_MASK				(GEN2_U3_EXIT_RSP_RX_CLK_MASK | GEN1_U3_EXIT_RSP_RX_CLK_MASK)
+#define LFPS_RSP_RX_CLK_SET_MASK				(GEN2_U3_EXIT_RSP_RX_CLK_VALUE | GEN1_U3_EXIT_RSP_RX_CLK_VALUE)
+
+#define DWC3_GUCTL1_CLR_MASK	(BIT(31) | BIT(24) | (0x7 << 21))
+#define DWC3_GUCTL1_DEV_L1_EXIT_BY_HW		BIT(24)
+#define DWC3_GUCTL1_IP_GAP_ADD_ON(val)		((val & 0x7) << 21)
+#define DWC3_GUCTL1_DEV_DECOUPLE_L1L2_EVT	BIT(31)
+
+#define DWC3_GUCTL1_SET_MASK	(DWC3_GUCTL1_DEV_L1_EXIT_BY_HW | \
+								DWC3_GUCTL1_IP_GAP_ADD_ON(0x3) | \
+								DWC3_GUCTL1_DEV_DECOUPLE_L1L2_EVT)
+
+#define USB_HOST_DWC3_GENERAL_CFG_ADDR		0X0A4F8808
+#define USB3_MP_GUSB2PHYCFG_REGS_1_ADDR		((void *)0x0A40C204)
+#define GUSB2PHYCFG_ENBLSLPM_BIT		BIT(8)
+#define USB3_MP_GUSB2PHYCFG_REGS_0_ADDR		((void *)0x0A40C200)
+#define USB3_MP_PORTSC_20_REGS_0_ADDR	((void *)0x0A400420)
+#define USB3_MP_PORTSC_20_REGS_1_ADDR	((void *)0x0A400430)
+#define USB3_MP_PORTSC_30_REGS_0_ADDR	((void *)0x0A400440)
+#define USB3_MP_PORTSC_30_REGS_1_ADDR	((void *)0x0A400450)
+#define USB3_PORTSC_WCE_BIT				BIT(25)
+
+/* Initializes a specific HS PHY instance */
+void hs_usb_phy_init(int index);
+/* Initializes and configures the USB HOST0 controller */
+void setup_usb_host0(void);
+/* Enable USB GDSC/Clocks */
+int qcom_enable_usb_clk(void);
+/* Enable TCSR REFGEN */
+void enable_clock_tcsr(void);
diff --git a/src/soc/qualcomm/x1p42100/usb/qmpv4_usb_phy.c b/src/soc/qualcomm/x1p42100/usb/qmpv4_usb_phy.c
new file mode 100644
index 0000000000..38556b8b4d
--- /dev/null
+++ b/src/soc/qualcomm/x1p42100/usb/qmpv4_usb_phy.c
@@ -0,0 +1,498 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <console/console.h>
+#include <timer.h>
+#include <delay.h>
+#include <soc/usb/qmp_usb_phy.h>
+#include <soc/addressmap.h>
+
+/* Only for QMP V4 PHY - QSERDES COM registers */
+struct usb3_phy_qserdes_com_reg_layout {
+	u32 com_ssc_step_size1_mode1;
+	u32 com_ssc_step_size2_mode1;
+	u32 com_ssc_step_size3_mode1;
+	u32 com_clk_ep_div_mode1;
+	u32 com_cp_ctrl_mode1;
+	u32 com_pll_rctrl_mode1;
+	u32 com_pll_cctrl_mode1;
+	u32 com_coreclk_div_mode1;
+	u32 com_lock_cmp1_mode1;
+	u32 com_lock_cmp2_mode1;
+	u32 com_dec_start_mode1;
+	u32 com_dec_start_msb_mode1;
+	u32 com_div_frac_start1_mode1;
+	u32 com_div_frac_start2_mode1;
+	u32 com_div_frac_start3_mode1;
+	u32 com_hsclk_sel_1;
+	u32 com_integloop_gain0_mode1;
+	u32 com_integloop_gain1_mode1;
+	u32 com_vco_tune1_mode1;
+	u32 com_vco_tune2_mode1;
+	u32 com_bin_vcocal_cmp_code1_mode1;
+	u32 com_bin_vcocal_cmp_code2_mode1;
+	u32 com_bin_vcocal_cmp_code1_mode0;
+	u32 com_bin_vcocal_cmp_code2_mode0;
+	u32 com_ssc_step_size1_mode0;
+	u32 com_ssc_step_size2_mode0;
+	u32 com_ssc_step_size3_mode0;
+	u32 com_clk_ep_div_mode0;
+	u32 com_cp_ctrl_mode0;
+	u32 com_pll_rctrl_mode0;
+	u32 com_pll_cctrl_mode0;
+	u32 com_coreclk_div_mode0;
+	u32 com_lock_cmp1_mode0;
+	u32 com_lock_cmp2_mode0;
+	u32 com_dec_start_mode0;
+	u32 com_dec_start_msb_mode0;
+	u32 com_div_frac_start1_mode0;
+	u32 com_div_frac_start2_mode0;
+	u32 com_div_frac_start3_mode0;
+	u32 com_hsclk_hs_switch_sel_1;
+	u32 com_integloop_gain0_mode0;
+	u32 com_integloop_gain1_mode0;
+	u32 com_vco_tune1_mode0;
+	u32 com_vco_tune2_mode0;
+	u32 com_atb_sel1;
+	u32 com_atb_sel2;
+	u32 com_freq_update;
+	u32 com_bg_timer;
+	u32 com_ssc_en_center;
+	u32 com_ssc_adj_per1;
+	u32 com_ssc_adj_per2;
+	u32 com_ssc_per1;
+	u32 com_ssc_per2;
+	u8 _reserved1[20];
+	u32 com_sysclk_buf_enable;
+	u8 _reserved2[36];
+	u32 com_sysclk_en_sel;
+	u8 _reserved3[16];
+	u32 com_lock_cmp_cfg;
+	u8 _reserved4[24];
+	u32 com_vco_tune_map;
+	u8 _reserved5[44];
+	u32 com_core_clk_en;
+	u32 com_cmn_config_1;
+	u8 _reserved6[44];
+	u32 com_auto_gain_adj_ctrl_1;
+	u32 com_auto_gain_adj_ctrl_2;
+	u32 com_auto_gain_adj_ctrl_3;
+	u32 com_auto_gain_adj_ctrl_4;
+	u32 com_additional_misc;
+};
+
+check_member(usb3_phy_qserdes_com_reg_layout, com_ssc_step_size1_mode1, 0x00);
+check_member(usb3_phy_qserdes_com_reg_layout, com_sysclk_buf_enable, 0xe8);
+check_member(usb3_phy_qserdes_com_reg_layout, com_sysclk_en_sel, 0x110);
+check_member(usb3_phy_qserdes_com_reg_layout, com_lock_cmp_cfg, 0x124);
+check_member(usb3_phy_qserdes_com_reg_layout, com_integloop_gain0_mode0, 0x0a0);
+check_member(usb3_phy_qserdes_com_reg_layout, com_vco_tune_map, 0x0140);
+check_member(usb3_phy_qserdes_com_reg_layout, com_core_clk_en, 0x170);
+check_member(usb3_phy_qserdes_com_reg_layout, com_auto_gain_adj_ctrl_1, 0x1a4);
+
+/* Only for QMP V4 PHY - TX registers */
+struct usb3_phy_qserdes_tx_reg_layout {
+	u8 _reserved1[52];
+	u32 tx_res_code_lane_tx;
+	u32 tx_res_code_lane_rx;
+	u32 tx_res_code_lane_offset_tx;
+	u32 tx_res_code_lane_offset_rx;
+	u8 _reserved2[64];
+	u32 tx_lane_mode_1;
+	u32 tx_lane_mode_2;
+	u32 tx_lane_mode_3;
+	u32 tx_lane_mode_4;
+	u32 tx_lane_mode_5;
+	u8 _reserved3[12];
+	u32 tx_rcv_detect_lvl_2;
+	u8 _reserved4[60];
+	u32 tx_pi_qec_ctrl;
+};
+check_member(usb3_phy_qserdes_tx_reg_layout, tx_res_code_lane_tx, 0x034);
+check_member(usb3_phy_qserdes_tx_reg_layout, tx_lane_mode_1, 0x084);
+check_member(usb3_phy_qserdes_tx_reg_layout, tx_rcv_detect_lvl_2, 0x0a4);
+check_member(usb3_phy_qserdes_tx_reg_layout, tx_pi_qec_ctrl, 0x0e4);
+
+/* Only for QMP V4 PHY - RX registers */
+struct usb3_phy_qserdes_rx_reg_layout {
+	u8 _reserved1[8];
+	u32 rx_ucdr_fo_gain;
+	u8 _reserved2[8];
+	u32 rx_ucdr_so_gain;
+	u8 _reserved3[24];
+	u32 rx_ucdr_fastlock_fo_gain;
+	u32 rx_ucdr_so_saturation_and_enable;
+	u32 rx_ucdr_fo_to_so_delay;
+	u32 rx_ucdr_fastlock_count_low;
+	u32 rx_ucdr_fastlock_count_high;
+	u32 rx_ucdr_pi_controls;
+	u32 rx_ucdr_pi_ctrl2;
+	u32 rx_ucdr_sb2_thresh1;
+	u32 rx_ucdr_sb2_thresh2;
+	u32 rx_ucdr_sb2_gain1;
+	u32 rx_ucdr_sb2_gain2;
+	u32 rx_aux_control;
+	u32 rx_aux_data_tcoarse_tfine;
+	u8 _reserved4[112];
+	u32 rx_vga_cal_cntrl1;
+	u32 rx_vga_cal_cntrl2;
+	u32 rx_gm_cal;
+	u8 _reserved5[12];
+	u32 rx_rx_equ_adaptor_cntrl2;
+	u32 rx_rx_equ_adaptor_cntrl3;
+	u32 rx_rx_equ_adaptor_cntrl4;
+	u32 rx_rx_idac_tsettle_low;
+	u32 rx_rx_idac_tsettle_high;
+	u8 _reserved6[16];
+	u32 rx_rx_eq_offset_adaptor_cntrl1;
+	u32 rx_rx_offset_adaptor_cntrl2;
+	u32 rx_sigdet_enables;
+	u32 rx_sigdet_cntrl;
+	u32 rx_sigdet_lvl;
+	u32 rx_sigdet_deglitch_cntrl;
+	u8 _reserved7[52];
+	u32 rx_rx_mode_00_low;
+	u32 rx_rx_mode_00_high;
+	u32 rx_rx_mode_00_high2;
+	u32 rx_rx_mode_00_high3;
+	u32 rx_rx_mode_00_high4;
+	u32 rx_rx_mode_01_low;
+	u32 rx_rx_mode_01_high;
+	u32 rx_rx_mode_01_high2;
+	u32 rx_rx_mode_01_high3;
+	u32 rx_rx_mode_01_high4;
+	u32 rx_rx_mode_10_low;
+	u32 rx_rx_mode_10_high;
+	u32 rx_rx_mode_10_high2;
+	u32 rx_rx_mode_10_high3;
+	u32 rx_rx_mode_10_high4;
+	u8 _reserved8[8];
+	u32 rx_dfe_en_timer;
+	u32 rx_dfe_ctle_post_cal_offset;
+	u32 rx_dcc_ctrl1;
+	u32 rx_dcc_ctrl2;
+	u32 rx_vth_code;
+	u8 _reserved9[48];
+	u32 rx_sigdet_cal_ctrl1;
+	u8 _reserved10[16];
+	u32 rx_sigdet_cal_trim;
+};
+
+check_member(usb3_phy_qserdes_rx_reg_layout, rx_ucdr_so_gain, 0x014);
+check_member(usb3_phy_qserdes_rx_reg_layout, rx_ucdr_fastlock_fo_gain, 0x030);
+check_member(usb3_phy_qserdes_rx_reg_layout, rx_vga_cal_cntrl1, 0x0d4);
+check_member(usb3_phy_qserdes_rx_reg_layout, rx_rx_equ_adaptor_cntrl2, 0x0ec);
+check_member(usb3_phy_qserdes_rx_reg_layout, rx_rx_equ_adaptor_cntrl3, 0x0f0);
+check_member(usb3_phy_qserdes_rx_reg_layout, rx_rx_equ_adaptor_cntrl4, 0x0f4);
+check_member(usb3_phy_qserdes_rx_reg_layout, rx_rx_eq_offset_adaptor_cntrl1, 0x110);
+check_member(usb3_phy_qserdes_rx_reg_layout, rx_sigdet_cntrl, 0x11c);
+check_member(usb3_phy_qserdes_rx_reg_layout, rx_rx_mode_00_low, 0x15c);
+check_member(usb3_phy_qserdes_rx_reg_layout, rx_dfe_en_timer, 0x1a0);
+check_member(usb3_phy_qserdes_rx_reg_layout, rx_dcc_ctrl1, 0x1a8);
+check_member(usb3_phy_qserdes_rx_reg_layout, rx_vth_code, 0x1b0);
+check_member(usb3_phy_qserdes_rx_reg_layout, rx_sigdet_cal_trim, 0x1f8);
+
+/* Only for QMP V4 PHY - PCS registers */
+struct usb3_phy_pcs_reg_layout {
+	u32 pcs_sw_reset;
+	u8 _reserved1[16];
+	u32 pcs_pcs_status1;
+	u8 _reserved2[40];
+	u32 pcs_power_down_control;
+	u32 pcs_start_control;
+	u8 _reserved3[124];
+	u32 pcs_lock_detect_config1;
+	u32 pcs_lock_detect_config2;
+	u32 pcs_lock_detect_config3;
+	u8 _reserved4[8];
+	u32 pcs_lock_detect_config6;
+	u32 pcs_refgen_req_config1;
+	u8 _reserved5[168];
+	u32 pcs_rx_sigdet_lvl;
+	u8 _reserved6[4];
+	u32 pcs_rcvr_dtct_dly_p1u2_l;
+	u32 pcs_rcvr_dtct_dly_p1u2_h;
+	u8 _reserved7[24];
+	u32 pcs_cdr_reset_time;
+	u8 _reserved8[12];
+	u32 pcs_align_detect_config1;
+	u32 pcs_align_detect_config2;
+	u8 _reserved9[8];
+	u32 pcs_pcs_tx_rx_config;
+	u8 _reserved10[8];
+	u32 pcs_eq_config1;
+	u8 _reserved11[12];
+	u32 pcs_eq_config5;
+};
+
+check_member(usb3_phy_pcs_reg_layout, pcs_pcs_status1, 0x014);
+check_member(usb3_phy_pcs_reg_layout, pcs_power_down_control, 0x040);
+check_member(usb3_phy_pcs_reg_layout, pcs_lock_detect_config1, 0x0c4);
+check_member(usb3_phy_pcs_reg_layout, pcs_lock_detect_config6, 0x0d8);
+check_member(usb3_phy_pcs_reg_layout, pcs_rx_sigdet_lvl, 0x188);
+check_member(usb3_phy_pcs_reg_layout, pcs_cdr_reset_time, 0x1b0);
+check_member(usb3_phy_pcs_reg_layout, pcs_align_detect_config1, 0x1c0);
+check_member(usb3_phy_pcs_reg_layout, pcs_pcs_tx_rx_config, 0x1d0);
+check_member(usb3_phy_pcs_reg_layout, pcs_eq_config1, 0x1dc);
+check_member(usb3_phy_pcs_reg_layout, pcs_eq_config5, 0x1ec);
+
+
+struct usb3_phy_pcs_usb3_reg_layout {
+	u32 reserved[6];
+	u32 pcs_usb3_lfps_det_high_count_val;
+	u32 reserved1[8];
+	u32 pcs_usb3_rxeqtraining_dfe_time_s2;
+	u32 pcs_usb3_rcvr_dtct_dly_u3_l;
+	u32 pcs_usb3_rcvr_dtct_dly_u3_h;
+};
+
+/* Definition of the shared initialization tables using offsets */
+static const qmp_phy_init_tbl_t qmp_v4_usb3_serdes_tbl[] = {
+	{(u32)offsetof(struct usb3_phy_qserdes_com_reg_layout, com_ssc_step_size1_mode1), 0xc0},
+	{(u32)offsetof(struct usb3_phy_qserdes_com_reg_layout, com_ssc_step_size2_mode1), 0x01},
+	{(u32)offsetof(struct usb3_phy_qserdes_com_reg_layout, com_cp_ctrl_mode1), 0x02},
+	{(u32)offsetof(struct usb3_phy_qserdes_com_reg_layout, com_pll_rctrl_mode1), 0x16},
+	{(u32)offsetof(struct usb3_phy_qserdes_com_reg_layout, com_pll_cctrl_mode1), 0x36},
+	{(u32)offsetof(struct usb3_phy_qserdes_com_reg_layout, com_coreclk_div_mode1), 0x04},
+	{(u32)offsetof(struct usb3_phy_qserdes_com_reg_layout, com_lock_cmp1_mode1), 0x16},
+	{(u32)offsetof(struct usb3_phy_qserdes_com_reg_layout, com_lock_cmp2_mode1), 0x41},
+	{(u32)offsetof(struct usb3_phy_qserdes_com_reg_layout, com_dec_start_mode1), 0x41},
+	{(u32)offsetof(struct usb3_phy_qserdes_com_reg_layout, com_div_frac_start1_mode1), 0x55},
+	{(u32)offsetof(struct usb3_phy_qserdes_com_reg_layout, com_div_frac_start2_mode1), 0x75},
+	{(u32)offsetof(struct usb3_phy_qserdes_com_reg_layout, com_div_frac_start3_mode1), 0x01},
+	{(u32)offsetof(struct usb3_phy_qserdes_com_reg_layout, com_hsclk_sel_1), 0x01},
+	{(u32)offsetof(struct usb3_phy_qserdes_com_reg_layout, com_vco_tune1_mode1), 0x25},
+	{(u32)offsetof(struct usb3_phy_qserdes_com_reg_layout, com_vco_tune2_mode1), 0x02},
+	{(u32)offsetof(struct usb3_phy_qserdes_com_reg_layout, com_bin_vcocal_cmp_code1_mode1), 0x5c},
+	{(u32)offsetof(struct usb3_phy_qserdes_com_reg_layout, com_bin_vcocal_cmp_code2_mode1), 0x0f},
+	{(u32)offsetof(struct usb3_phy_qserdes_com_reg_layout, com_bin_vcocal_cmp_code1_mode0), 0x5c},
+	{(u32)offsetof(struct usb3_phy_qserdes_com_reg_layout, com_bin_vcocal_cmp_code2_mode0), 0x0f},
+	{(u32)offsetof(struct usb3_phy_qserdes_com_reg_layout, com_ssc_step_size1_mode0), 0xc0},
+	{(u32)offsetof(struct usb3_phy_qserdes_com_reg_layout, com_ssc_step_size2_mode0), 0x01},
+	{(u32)offsetof(struct usb3_phy_qserdes_com_reg_layout, com_cp_ctrl_mode0), 0x02},
+	{(u32)offsetof(struct usb3_phy_qserdes_com_reg_layout, com_pll_rctrl_mode0), 0x16},
+	{(u32)offsetof(struct usb3_phy_qserdes_com_reg_layout, com_pll_cctrl_mode0), 0x36},
+	{(u32)offsetof(struct usb3_phy_qserdes_com_reg_layout, com_lock_cmp1_mode0), 0x08},
+	{(u32)offsetof(struct usb3_phy_qserdes_com_reg_layout, com_lock_cmp2_mode0), 0x1a},
+	{(u32)offsetof(struct usb3_phy_qserdes_com_reg_layout, com_dec_start_mode0), 0x41},
+	{(u32)offsetof(struct usb3_phy_qserdes_com_reg_layout, com_div_frac_start1_mode0), 0x55},
+	{(u32)offsetof(struct usb3_phy_qserdes_com_reg_layout, com_div_frac_start2_mode0), 0x75},
+	{(u32)offsetof(struct usb3_phy_qserdes_com_reg_layout, com_div_frac_start3_mode0), 0x01},
+	{(u32)offsetof(struct usb3_phy_qserdes_com_reg_layout, com_vco_tune1_mode0), 0x25},
+	{(u32)offsetof(struct usb3_phy_qserdes_com_reg_layout, com_vco_tune2_mode0), 0x02},
+	{(u32)offsetof(struct usb3_phy_qserdes_com_reg_layout, com_bg_timer), 0x0a},
+	{(u32)offsetof(struct usb3_phy_qserdes_com_reg_layout, com_ssc_en_center), 0x01},
+	{(u32)offsetof(struct usb3_phy_qserdes_com_reg_layout, com_ssc_per1), 0x62},
+	{(u32)offsetof(struct usb3_phy_qserdes_com_reg_layout, com_ssc_per2), 0x02},
+	{(u32)offsetof(struct usb3_phy_qserdes_com_reg_layout, com_sysclk_buf_enable), 0x0a},
+	{(u32)offsetof(struct usb3_phy_qserdes_com_reg_layout, com_sysclk_en_sel), 0x1a},
+	{(u32)offsetof(struct usb3_phy_qserdes_com_reg_layout, com_lock_cmp_cfg), 0x14},
+	{(u32)offsetof(struct usb3_phy_qserdes_com_reg_layout, com_vco_tune_map), 0x04},
+	{(u32)offsetof(struct usb3_phy_qserdes_com_reg_layout, com_core_clk_en), 0x20},
+	{(u32)offsetof(struct usb3_phy_qserdes_com_reg_layout, com_cmn_config_1), 0x16},
+	{(u32)offsetof(struct usb3_phy_qserdes_com_reg_layout, com_auto_gain_adj_ctrl_1), 0xb6},
+	{(u32)offsetof(struct usb3_phy_qserdes_com_reg_layout, com_auto_gain_adj_ctrl_2), 0x4b},
+	{(u32)offsetof(struct usb3_phy_qserdes_com_reg_layout, com_auto_gain_adj_ctrl_3), 0x37},
+	{(u32)offsetof(struct usb3_phy_qserdes_com_reg_layout, com_additional_misc), 0x0c},
+};
+
+static const qmp_phy_init_tbl_t qmp_v4_usb3_tx_tbl[] = {
+	{(u32)offsetof(struct usb3_phy_qserdes_tx_reg_layout, tx_res_code_lane_tx), 0x00},
+	{(u32)offsetof(struct usb3_phy_qserdes_tx_reg_layout, tx_res_code_lane_rx), 0x00},
+	{(u32)offsetof(struct usb3_phy_qserdes_tx_reg_layout, tx_res_code_lane_offset_tx), 0x1f},
+	{(u32)offsetof(struct usb3_phy_qserdes_tx_reg_layout, tx_res_code_lane_offset_rx), 0x09},
+	{(u32)offsetof(struct usb3_phy_qserdes_tx_reg_layout, tx_lane_mode_1), 0xf5},
+	{(u32)offsetof(struct usb3_phy_qserdes_tx_reg_layout, tx_lane_mode_3), 0x3f},
+	{(u32)offsetof(struct usb3_phy_qserdes_tx_reg_layout, tx_lane_mode_4), 0x3f},
+	{(u32)offsetof(struct usb3_phy_qserdes_tx_reg_layout, tx_lane_mode_5), 0x5f},
+	{(u32)offsetof(struct usb3_phy_qserdes_tx_reg_layout, tx_rcv_detect_lvl_2), 0x12},
+	{(u32)offsetof(struct usb3_phy_qserdes_tx_reg_layout, tx_pi_qec_ctrl), 0x21},
+};
+
+static const qmp_phy_init_tbl_t qmp_v4_usb3_rx_tbl[] = {
+	{(u32)offsetof(struct usb3_phy_qserdes_rx_reg_layout, rx_ucdr_fo_gain), 0x0a},
+	{(u32)offsetof(struct usb3_phy_qserdes_rx_reg_layout, rx_ucdr_so_gain), 0x06},
+	{(u32)offsetof(struct usb3_phy_qserdes_rx_reg_layout, rx_ucdr_fastlock_fo_gain), 0x2f},
+	{(u32)offsetof(struct usb3_phy_qserdes_rx_reg_layout, rx_ucdr_so_saturation_and_enable), 0x7f},
+	{(u32)offsetof(struct usb3_phy_qserdes_rx_reg_layout, rx_ucdr_fastlock_count_low), 0xff},
+	{(u32)offsetof(struct usb3_phy_qserdes_rx_reg_layout, rx_ucdr_fastlock_count_high), 0x0f},
+	{(u32)offsetof(struct usb3_phy_qserdes_rx_reg_layout, rx_ucdr_pi_controls), 0x99},
+	{(u32)offsetof(struct usb3_phy_qserdes_rx_reg_layout, rx_ucdr_sb2_thresh1), 0x08},
+	{(u32)offsetof(struct usb3_phy_qserdes_rx_reg_layout, rx_ucdr_sb2_thresh2), 0x08},
+	{(u32)offsetof(struct usb3_phy_qserdes_rx_reg_layout, rx_ucdr_sb2_gain1), 0x00},
+	{(u32)offsetof(struct usb3_phy_qserdes_rx_reg_layout, rx_ucdr_sb2_gain2), 0x0a},
+	{(u32)offsetof(struct usb3_phy_qserdes_rx_reg_layout, rx_aux_data_tcoarse_tfine), 0xa0},
+	{(u32)offsetof(struct usb3_phy_qserdes_rx_reg_layout, rx_vga_cal_cntrl1), 0x54},
+	{(u32)offsetof(struct usb3_phy_qserdes_rx_reg_layout, rx_vga_cal_cntrl2), 0x0f},
+	{(u32)offsetof(struct usb3_phy_qserdes_rx_reg_layout, rx_gm_cal), 0x13},
+	{(u32)offsetof(struct usb3_phy_qserdes_rx_reg_layout, rx_rx_equ_adaptor_cntrl2), 0x0f},
+	{(u32)offsetof(struct usb3_phy_qserdes_rx_reg_layout, rx_rx_equ_adaptor_cntrl3), 0x4a},
+	{(u32)offsetof(struct usb3_phy_qserdes_rx_reg_layout, rx_rx_equ_adaptor_cntrl4), 0x0a},
+	{(u32)offsetof(struct usb3_phy_qserdes_rx_reg_layout, rx_rx_idac_tsettle_low), 0x07},
+	{(u32)offsetof(struct usb3_phy_qserdes_rx_reg_layout, rx_rx_idac_tsettle_high), 0x00},
+	{(u32)offsetof(struct usb3_phy_qserdes_rx_reg_layout, rx_rx_eq_offset_adaptor_cntrl1), 0x47},
+	{(u32)offsetof(struct usb3_phy_qserdes_rx_reg_layout, rx_sigdet_cntrl), 0x04},
+	{(u32)offsetof(struct usb3_phy_qserdes_rx_reg_layout, rx_sigdet_deglitch_cntrl), 0x0e},
+	{(u32)offsetof(struct usb3_phy_qserdes_rx_reg_layout, rx_rx_mode_00_low), 0x3f},
+	{(u32)offsetof(struct usb3_phy_qserdes_rx_reg_layout, rx_rx_mode_00_high), 0xbf},
+	{(u32)offsetof(struct usb3_phy_qserdes_rx_reg_layout, rx_rx_mode_00_high2), 0xff},
+	{(u32)offsetof(struct usb3_phy_qserdes_rx_reg_layout, rx_rx_mode_00_high3), 0xdf},
+	{(u32)offsetof(struct usb3_phy_qserdes_rx_reg_layout, rx_rx_mode_00_high4), 0xed},
+	{(u32)offsetof(struct usb3_phy_qserdes_rx_reg_layout, rx_rx_mode_01_low), 0xdc},
+	{(u32)offsetof(struct usb3_phy_qserdes_rx_reg_layout, rx_rx_mode_01_high), 0x5c},
+	{(u32)offsetof(struct usb3_phy_qserdes_rx_reg_layout, rx_rx_mode_01_high2), 0x9c},
+	{(u32)offsetof(struct usb3_phy_qserdes_rx_reg_layout, rx_rx_mode_01_high3), 0x1d},
+	{(u32)offsetof(struct usb3_phy_qserdes_rx_reg_layout, rx_rx_mode_01_high4), 0x09},
+	{(u32)offsetof(struct usb3_phy_qserdes_rx_reg_layout, rx_dfe_en_timer), 0x04},
+	{(u32)offsetof(struct usb3_phy_qserdes_rx_reg_layout, rx_dfe_ctle_post_cal_offset), 0x38},
+	{(u32)offsetof(struct usb3_phy_qserdes_rx_reg_layout, rx_dcc_ctrl1), 0x0c},
+	{(u32)offsetof(struct usb3_phy_qserdes_rx_reg_layout, rx_vth_code), 0x10},
+	{(u32)offsetof(struct usb3_phy_qserdes_rx_reg_layout, rx_sigdet_cal_ctrl1), 0x14},
+	{(u32)offsetof(struct usb3_phy_qserdes_rx_reg_layout, rx_sigdet_cal_trim), 0x08},
+};
+
+static const qmp_phy_init_tbl_t qmp_v4_usb3_pcs_tbl[] = {
+	{(u32)offsetof(struct usb3_phy_pcs_reg_layout, pcs_lock_detect_config1), 0xc4},
+	{(u32)offsetof(struct usb3_phy_pcs_reg_layout, pcs_lock_detect_config2), 0x89},
+	{(u32)offsetof(struct usb3_phy_pcs_reg_layout, pcs_lock_detect_config3), 0x20},
+	{(u32)offsetof(struct usb3_phy_pcs_reg_layout, pcs_lock_detect_config6), 0x13},
+	{(u32)offsetof(struct usb3_phy_pcs_reg_layout, pcs_refgen_req_config1), 0x21},
+	{(u32)offsetof(struct usb3_phy_pcs_reg_layout, pcs_rx_sigdet_lvl), 0xaa},
+	{(u32)offsetof(struct usb3_phy_pcs_reg_layout, pcs_rcvr_dtct_dly_p1u2_l), 0xe7},
+	{(u32)offsetof(struct usb3_phy_pcs_reg_layout, pcs_rcvr_dtct_dly_p1u2_h), 0x03},
+	{(u32)offsetof(struct usb3_phy_pcs_reg_layout, pcs_cdr_reset_time), 0x0a},
+	{(u32)offsetof(struct usb3_phy_pcs_reg_layout, pcs_align_detect_config1), 0x88},
+	{(u32)offsetof(struct usb3_phy_pcs_reg_layout, pcs_align_detect_config2), 0x13},
+	{(u32)offsetof(struct usb3_phy_pcs_reg_layout, pcs_pcs_tx_rx_config), 0x0c},
+	{(u32)offsetof(struct usb3_phy_pcs_reg_layout, pcs_eq_config1), 0x4b},
+	{(u32)offsetof(struct usb3_phy_pcs_reg_layout, pcs_eq_config5), 0x10},
+};
+
+static const qmp_phy_init_tbl_t qmp_v4_usb3_pcs_usb3_tbl[] = {
+	{(u32)offsetof(struct usb3_phy_pcs_usb3_reg_layout, pcs_usb3_lfps_det_high_count_val), 0xf8},
+	{(u32)offsetof(struct usb3_phy_pcs_usb3_reg_layout, pcs_usb3_rxeqtraining_dfe_time_s2), 0x07},
+	{(u32)offsetof(struct usb3_phy_pcs_usb3_reg_layout, pcs_usb3_rcvr_dtct_dly_u3_l), 0x40},
+	{(u32)offsetof(struct usb3_phy_pcs_usb3_reg_layout, pcs_usb3_rcvr_dtct_dly_u3_h), 0x00},
+};
+
+/* Global instances of PHY data with their respective configuration tables */
+static const struct ss_usb_phy_reg qmp_phy_instances[] = {
+	{
+		.com_base = (void *)QMP_PHY_MP0_QSERDES_COM_REG_BASE,
+		.tx_base = (void *)QMP_PHY_MP0_QSERDES_TX_REG_BASE,
+		.rx_base = (void *)QMP_PHY_MP0_QSERDES_RX_REG_BASE,
+		.pcs_base = (void *)QMP_PHY_MP0_PCS_REG_BASE,
+		.pcs_usb3_base = (void *)QMP_PHY_MP0_PCS_USB3_REG_BASE,
+		.name = "MP0",
+		.serdes_tbl = qmp_v4_usb3_serdes_tbl,
+		.serdes_tbl_num = ARRAY_SIZE(qmp_v4_usb3_serdes_tbl),
+		.tx_tbl = qmp_v4_usb3_tx_tbl,
+		.tx_tbl_num = ARRAY_SIZE(qmp_v4_usb3_tx_tbl),
+		.rx_tbl = qmp_v4_usb3_rx_tbl,
+		.rx_tbl_num = ARRAY_SIZE(qmp_v4_usb3_rx_tbl),
+		.pcs_tbl = qmp_v4_usb3_pcs_tbl,
+		.pcs_tbl_num = ARRAY_SIZE(qmp_v4_usb3_pcs_tbl),
+		.pcs_usb3_tbl = qmp_v4_usb3_pcs_usb3_tbl,
+		.pcs_usb3_tbl_num = ARRAY_SIZE(qmp_v4_usb3_pcs_usb3_tbl),
+	},
+	{
+		.com_base = (void *)QMP_PHY_MP1_QSERDES_COM_REG_BASE,
+		.tx_base = (void *)QMP_PHY_MP1_QSERDES_TX_REG_BASE,
+		.rx_base = (void *)QMP_PHY_MP1_QSERDES_RX_REG_BASE,
+		.pcs_base = (void *)QMP_PHY_MP1_PCS_REG_BASE,
+		.pcs_usb3_base = (void *)QMP_PHY_MP1_PCS_USB3_REG_BASE,
+		.name = "MP1",
+		.serdes_tbl = qmp_v4_usb3_serdes_tbl,
+		.serdes_tbl_num = ARRAY_SIZE(qmp_v4_usb3_serdes_tbl),
+		.tx_tbl = qmp_v4_usb3_tx_tbl,
+		.tx_tbl_num = ARRAY_SIZE(qmp_v4_usb3_tx_tbl),
+		.rx_tbl = qmp_v4_usb3_rx_tbl,
+		.rx_tbl_num = ARRAY_SIZE(qmp_v4_usb3_rx_tbl),
+		.pcs_tbl = qmp_v4_usb3_pcs_tbl,
+		.pcs_tbl_num = ARRAY_SIZE(qmp_v4_usb3_pcs_tbl),
+		.pcs_usb3_tbl = qmp_v4_usb3_pcs_usb3_tbl,
+		.pcs_usb3_tbl_num = ARRAY_SIZE(qmp_v4_usb3_pcs_usb3_tbl),
+	},
+};
+
+/* Modified configure function to accept a base address for the current block */
+static void qcom_qmp_phy_configure(void *base_addr, const qmp_phy_init_tbl_t tbl[], unsigned int num)
+{
+	int i;
+	const qmp_phy_init_tbl_t *t = tbl;
+
+	if (!t)
+		return;
+
+	for (i = 0; i < num; i++, t++)
+		write32((void *)((unsigned long)base_addr + t->offset), t->val);
+}
+
+/* Unified PHY initialization function that takes PHY instance data */
+static bool ss_qmp_phy_init_common(const struct ss_usb_phy_reg *ss_phy_reg)
+{
+	bool ret = true;
+	/* Use the PCS base address from ss_phy_reg to cast to the PCS register layout */
+	struct usb3_phy_pcs_reg_layout *current_pcs_reg = (struct usb3_phy_pcs_reg_layout *)ss_phy_reg->pcs_base;
+
+	printk(BIOS_DEBUG, "QMP PHY %s init\n", ss_phy_reg->name);
+
+	/* power up USB3 PHY */
+	write32(&current_pcs_reg->pcs_power_down_control, 0x01);
+
+	/* Serdes configuration */
+	qcom_qmp_phy_configure(ss_phy_reg->com_base, ss_phy_reg->serdes_tbl,
+		ss_phy_reg->serdes_tbl_num);
+
+	/* Tx, Rx, and PCS configurations */
+	qcom_qmp_phy_configure(ss_phy_reg->pcs_base, ss_phy_reg->pcs_tbl,
+		ss_phy_reg->pcs_tbl_num);
+	qcom_qmp_phy_configure(ss_phy_reg->tx_base, ss_phy_reg->tx_tbl,
+		ss_phy_reg->tx_tbl_num);
+	qcom_qmp_phy_configure(ss_phy_reg->rx_base, ss_phy_reg->rx_tbl,
+		ss_phy_reg->rx_tbl_num);
+	qcom_qmp_phy_configure(ss_phy_reg->pcs_usb3_base, ss_phy_reg->pcs_usb3_tbl,
+		ss_phy_reg->pcs_usb3_tbl_num);
+
+	udelay(100);
+
+	/* perform software reset of PCS/Serdes */
+	write32(&current_pcs_reg->pcs_sw_reset, 0x00);
+	/* start PCS/Serdes to operation mode */
+	write32(&current_pcs_reg->pcs_start_control, 0x03);
+
+	udelay(100);
+	/*
+	 * Wait for PHY initialization to be done
+	 * PCS_STATUS: wait for 1ms for PHY STATUS;
+	 * SW can continuously check for PHYSTATUS = 1.b0.
+	 */
+	long lock_us = wait_us(10000,
+			!(read32(&current_pcs_reg->pcs_pcs_status1)&
+			USB3_PCS_PHYSTATUS));
+	if (!lock_us) {
+		ret = false;
+		printk(BIOS_ERR, "QMP PHY %s PLL LOCK fails:\n", ss_phy_reg->name);
+	} else {
+		printk(BIOS_DEBUG, "QMP PHY %s initialized and locked in %ldus\n",
+				ss_phy_reg->name, lock_us);
+	}
+	return ret;
+}
+
+/* Unified ss_qmp_phy_init function to initialize a specific PHY instance
+Pass 0 for MP0, or 1 for MP1. */
+bool ss_qmp_phy_init(u32 phy_idx)
+{
+	bool ret = true;
+
+	/* Ensure the provided index is valid */
+	if (phy_idx >= ARRAY_SIZE(qmp_phy_instances)) {
+		printk(BIOS_ERR, "Invalid PHY index provided: %u\n", phy_idx);
+		return false;
+	}
+
+	if (!ss_qmp_phy_init_common(&qmp_phy_instances[phy_idx])) {
+		ret = false;
+	}
+	return ret;
+}
diff --git a/src/soc/qualcomm/x1p42100/usb/snps_usb_phy.c b/src/soc/qualcomm/x1p42100/usb/snps_usb_phy.c
new file mode 100644
index 0000000000..2fc35ad077
--- /dev/null
+++ b/src/soc/qualcomm/x1p42100/usb/snps_usb_phy.c
@@ -0,0 +1,239 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <console/console.h>
+#include <soc/usb/snps_usb_phy.h>
+#include <soc/addressmap.h>
+#include <commonlib/helpers.h>
+#include <soc/usb/usb.h>
+#include <delay.h>
+
+#define SLEEPM BIT(0)
+
+#define TERMSEL BIT(5)
+
+#define POR BIT(1)
+
+/* Updated FSEL_MASK based on the table feedback (GENMASK(6,4) for 38.4MHz) */
+#define FSEL_MASK GENMASK(6, 4)
+#define FSEL_DEFAULT (0x3 << 4) /* Original value, may not be used directly */
+
+#define VBUSVLDEXTSEL0 BIT(4)
+#define PLLBTUNE BIT(5)
+
+#define VREGBYPASS BIT(0)
+
+#define VBUSVLDEXT0 BIT(0)
+
+/* Updated macros for clarity as per feedback */
+#define USB2_SUSPEND_N_BIT BIT(2)
+#define USB2_SUSPEND_N_SEL_BIT BIT(3)
+
+#define UTMI_PHY_CMN_CTRL_OVERRIDE_EN BIT(1)
+
+#define REFCLK_SEL_MASK GENMASK(1, 0)
+#define REFCLK_SEL_DEFAULT (0x2 << 0)
+
+#define PARAM_OVRD_MASK 0xFF
+
+/* Streamlined macros for common control bits (from previous feedback) */
+#define USB_PHY_ENABLE_BIT BIT(0)
+#define USB_PHY_RETENABLEN_BIT BIT(3)
+#define APB_LOGIC_RESET_BIT BIT(2)
+#define TESTBURNIN_BIT BIT(6)
+#define FSEL_SEL_BIT BIT(0)
+
+/* New macros from table requirements (to be used in sequence) */
+#define FSEL_38_4_MHZ_VAL (0x4 << 4) /* 3'b100 for bits 6:4 -> 0x4, shifted by 4 */
+#define SIDDQ_SEL_BIT BIT(1)
+#define SIDDQ_DISABLE_BIT BIT(2) /* SIDDQ is set to 0, means power up analog blocks */
+
+#define CFG_CTRL_2_VALUE 0xC8 /* For phy_cfg_pll_fb_div_7_0 */
+
+#define CFG_CTRL_3_FB_DIV_MASK GENMASK(3, 0)
+#define CFG_CTRL_3_FB_DIV_VALUE 0x0 /* 4'b0000 */
+
+#define CFG_CTRL_3_REF_DIV_MASK GENMASK(7, 4)
+#define CFG_CTRL_3_REF_DIV_VALUE (0x0 << 4) /* 4'b0000 shifted to bits 7:4 */
+
+#define CFG_CTRL_1_PLL_CPBIAS_MASK GENMASK(7, 1)
+#define CFG_CTRL_1_PLL_CPBIAS_VALUE (0x0 << 1) /* 7'b0000000 shifted to bits 7:1 */
+
+#define CFG_CTRL_4_PLL_VCO_GAIN_MASK GENMASK(1, 0)
+#define CFG_CTRL_4_PLL_VCO_GAIN_VALUE 0x1 /* 2'b01 */
+
+#define CFG_CTRL_4_PLL_INT_GAIN_MASK GENMASK(7, 2)
+#define CFG_CTRL_4_PLL_INT_GAIN_VALUE (0x8 << 2) /* 6'b001000 shifted to bits 7:2 */
+
+#define CFG_CTRL_5_PLL_PROP_GAIN_MASK GENMASK(5, 0)
+#define CFG_CTRL_5_PLL_PROP_GAIN_VALUE 0x10 /* 6'b010000 */
+
+#define CFG_CTRL_6_PLL_VCO_CFG_MASK GENMASK(2, 0)
+#define CFG_CTRL_6_PLL_VCO_CFG_VALUE 0x0 /* 3'b000 */
+
+#define CFG_CTRL_5_PLL_VREF_TUNE_MASK GENMASK(7, 6)
+#define CFG_CTRL_5_PLL_VREF_TUNE_VALUE (0x1 << 6) /* 2'b01 shifted to bits 7:6 */
+
+#define VBUS_DET_EXT_SEL_BIT BIT(4)
+#define VBUS_VALID_EXT_BIT BIT(0)
+
+#define CFG_CTRL_9_TX_PREEMP_MASK GENMASK(2, 0)
+#define CFG_CTRL_9_TX_PREEMP_VALUE 0x0 /* 3'b000 */
+
+#define CFG_CTRL_8_TX_HS_VREF_MASK GENMASK(5, 3)
+#define CFG_CTRL_8_TX_HS_VREF_VALUE (0x3 << 3) /* 3'b011 shifted to bits 5:3 */
+
+#define CFG_CTRL_9_TX_RISE_TUNE_MASK GENMASK(6, 5)
+#define CFG_CTRL_9_TX_RISE_TUNE_VALUE (0x2 << 5) /* 2'b10 shifted to bits 6:5 */
+
+#define CFG_CTRL_8_TX_HS_XV_TUNE_MASK GENMASK(7, 6)
+#define CFG_CTRL_8_TX_HS_XV_TUNE_VALUE (0x0 << 6) /* 2'b00 shifted to bits 7:6 */
+
+#define CFG_CTRL_9_TX_RES_TUNE_MASK GENMASK(4, 3)
+#define CFG_CTRL_9_TX_RES_TUNE_VALUE (0x1 << 3) /* 2'b01 shifted to bits 4:3 */
+
+
+struct hs_usb_phy_reg *hs_phy_reg = NULL;
+void hs_usb_phy_init(int index)
+{
+	if (index == 0)
+		hs_phy_reg = (void *)HS_USB_MP0_PHY_BASE;
+	else
+		hs_phy_reg = (void *)HS_USB_MP1_PHY_BASE;
+
+	/*
+	 * This sequence initializes the USB HS PHY.
+	 */
+
+	/* Step 1: USB_PHY_CFG0[1] = 1'b1 (UTMI_PHY_CMN_CNTRL_OVERRIDE_EN=1) */
+	/* This is a MUX select signal to enable software override of UTMI PHY common control. */
+	clrsetbits32(&hs_phy_reg->cfg0, UTMI_PHY_CMN_CTRL_OVERRIDE_EN,
+		UTMI_PHY_CMN_CTRL_OVERRIDE_EN);
+
+	/* Step 2: USB_PHY_UTMI_CTRL5[1] = 1'b1 (POR asserted) */
+	/* Assert the PHY reset. This reset must be held for at least 10us after all supplies ramp up. */
+	clrsetbits32(&hs_phy_reg->utmi_ctrl5, POR, POR);
+	udelay(10); /* Hold POR for 10us */
+
+	/* Step 3: USB_PHY_HS_PHY_CTRL_COMMON0[0] = 1'b1 (phy_enable='1') */
+	/* Asynchronous enable for the PHY. If low during POR de-assertion, PHY remains inactive. */
+	clrsetbits32(&hs_phy_reg->hs_phy_ctrl_common0, USB_PHY_ENABLE_BIT, USB_PHY_ENABLE_BIT);
+
+	/* Step 4: USB_PHY_HS_PHY_CTRL_COMMON0[3] = 1'b1 (Retention Mode Enable) */
+	/* Set retenable_n = 1'b1. This signal must be high when VDD supply is powered. */
+	clrsetbits32(&hs_phy_reg->hs_phy_ctrl_common0, USB_PHY_RETENABLEN_BIT, USB_PHY_RETENABLEN_BIT);
+
+	/* Step 5: USB_PHY_APB_ACCESS_CMD[2] = 1'b1 (APB Logic Reset) */
+	/* Reset all APB related logic, including SNPS APB FSM but not the APB registers. */
+	clrsetbits32(&hs_phy_reg->usb_phy_apb_access_cmd, APB_LOGIC_RESET_BIT, APB_LOGIC_RESET_BIT);
+
+	/* Step 6: UTMI_PHY_CMN_CTRL0[6] = 1'b0 (Burn-in Test Enable - clear the bit) */
+	/* De-assert test_burnin. If asserted, PHY performs power-on-reset and enters HS Loopback mode. */
+	clrsetbits32(&hs_phy_reg->utmi_phy_cmn_ctrl0, TESTBURNIN_BIT, 0);
+
+	/* Step 7: USB_PHY_FSEL_SEL = 1'b1 (FSEL MUX select for SW override) */
+	/* Select software override for frequency selection. */
+	clrsetbits32(&hs_phy_reg->usb_phy_fsel_sel, FSEL_SEL_BIT, FSEL_SEL_BIT);
+
+	/* Step 8: USB_PHY_HS_PHY_CTRL_COMMON0[6:4] = 3'b100 (Sets refclk frequency to 38.4 MHz) */
+	/* Configure the reference clock frequency. */
+	clrsetbits32(&hs_phy_reg->hs_phy_ctrl_common0, FSEL_MASK, FSEL_38_4_MHZ_VAL);
+
+	/* Step 9: USB_PHY_CFG_CTRL_2[7:0] = 8'b11001000 (Control of the feedback multiplication ratio) */
+	/* Configure phy_cfg_pll_fb_div_7_0. */
+	clrsetbits32(&hs_phy_reg->cfg_ctrl_2, 0xFF, CFG_CTRL_2_VALUE); /* Using 0xFF for full 8-bit mask */
+
+	/* Step 10: USB_PHY_CFG_CTRL_3[3:0] = 4'b0000 (Control of the feedback multiplication ratio) */
+	/* Configure phy_cfg_pll_fb_div_11_8. */
+	clrsetbits32(&hs_phy_reg->cfg_ctrl_3, CFG_CTRL_3_FB_DIV_MASK, CFG_CTRL_3_FB_DIV_VALUE);
+
+	/* Step 11: USB_PHY_CFG_CTRL_3[7:4] = 4'b0000 (Control of the input frequency division ratio) */
+	/* Configure phy_cfg_pll_ref_div. */
+	clrsetbits32(&hs_phy_reg->cfg_ctrl_3, CFG_CTRL_3_REF_DIV_MASK, CFG_CTRL_3_REF_DIV_VALUE);
+
+	/* Step 12: USB_PHY_CFG_CTRL_1[7:1] = 7'b0000000 (PLL loop bias configuration) */
+	/* Configure phy_cfg_pll_cpbias_cntrl. */
+	clrsetbits32(&hs_phy_reg->cfg_ctrl_1, CFG_CTRL_1_PLL_CPBIAS_MASK, CFG_CTRL_1_PLL_CPBIAS_VALUE);
+
+	/* Step 13: USB_PHY_CFG_CTRL_4[1:0] = 2'b01 (PLL vco source gain) */
+	/* Configure phy_cfg_pll_gmp_cntrl. */
+	clrsetbits32(&hs_phy_reg->cfg_ctrl_4, CFG_CTRL_4_PLL_VCO_GAIN_MASK, CFG_CTRL_4_PLL_VCO_GAIN_VALUE);
+
+	/* Step 14: USB_PHY_CFG_CTRL_4[7:2] = 6'b001000 (Gain of PLL Integral Charge Pump) */
+	/* Configure phy_cfg_pll_int_cntrl. */
+	clrsetbits32(&hs_phy_reg->cfg_ctrl_4, CFG_CTRL_4_PLL_INT_GAIN_MASK, CFG_CTRL_4_PLL_INT_GAIN_VALUE);
+
+	/* Step 15: USB_PHY_CFG_CTRL_5[5:0] = 6'b010000 (Gain of PLL Proportional Charge Pump) */
+	/* Configure phy_cfg_pll_prop_cntrl. */
+	clrsetbits32(&hs_phy_reg->cfg_ctrl_5, CFG_CTRL_5_PLL_PROP_GAIN_MASK, CFG_CTRL_5_PLL_PROP_GAIN_VALUE);
+
+	/* Step 16: USB_PHY_CFG_CTRL_6[2:0] = 3'b000 (PLL VCO configuration) */
+	/* Configure phy_cfg_pll_vco_cntrl. */
+	clrsetbits32(&hs_phy_reg->cfg_ctrl_6, CFG_CTRL_6_PLL_VCO_CFG_MASK, CFG_CTRL_6_PLL_VCO_CFG_VALUE);
+
+	/* Step 17: USB_PHY_CFG_CTRL_5[7:6] = 2'b01 (Configuration for PLL voltage reference level) */
+	/* Configure phy_cfg_pll_vref_tune. */
+	clrsetbits32(&hs_phy_reg->cfg_ctrl_5, CFG_CTRL_5_PLL_VREF_TUNE_MASK, CFG_CTRL_5_PLL_VREF_TUNE_VALUE);
+
+	/* Step 18: Selects UTMI data bus width. Wordinterface<#> = 0; for 8 bits interface (60 MHz)
+	 * No register control, tied at chip top.
+	 */
+
+	/* Step 19: USB_PHY_HS_PHY_CTRL2[4] = 1'b1 (VBUS MUX Selection) */
+	/* Select software control for VBUS detection. */
+	clrsetbits32(&hs_phy_reg->hs_phy_ctrl2, VBUS_DET_EXT_SEL_BIT, VBUS_DET_EXT_SEL_BIT);
+
+	/* Step 20: USB_PHY_HS_PHY_CTRL2[0] = 1'b1 (VBUS valid indication) */
+	/* Software writes this bit to indicate VBUS status. */
+	clrsetbits32(&hs_phy_reg->hs_phy_ctrl2, VBUS_VALID_EXT_BIT, VBUS_VALID_EXT_BIT);
+
+	/* Step 21: USB_PHY_CFG_CTRL_9[2:0] = 3'b000 (HS Transmitter Pre-Emphasis Control) */
+	/* Set HS Transmitter pre-emphasis to off (design default). */
+	clrsetbits32(&hs_phy_reg->cfg_ctrl_9, CFG_CTRL_9_TX_PREEMP_MASK, CFG_CTRL_9_TX_PREEMP_VALUE);
+
+	/* Step 22: USB_PHY_CFG_CTRL_8[5:3] = 3'b011 (HS DC Voltage Level Adjustment) */
+	/* Set HS DC Voltage Level to default (increased). */
+	clrsetbits32(&hs_phy_reg->cfg_ctrl_8, CFG_CTRL_8_TX_HS_VREF_MASK, CFG_CTRL_8_TX_HS_VREF_VALUE);
+
+	/* Step 23: USB_PHY_CFG_CTRL_9[6:5] = 2'b10 (HS Transmitter Rise/Fall Time Adjustment) */
+	/* Set HS Transmitter Rise/Fall Time Adjustment to default. */
+	clrsetbits32(&hs_phy_reg->cfg_ctrl_9, CFG_CTRL_9_TX_RISE_TUNE_MASK, CFG_CTRL_9_TX_RISE_TUNE_VALUE);
+
+	/* Step 24: USB_PHY_CFG_CTRL_8[7:6] = 2'b00 (Transmitter High-Speed Crossover Adjustment) */
+	/* Set Transmitter High-Speed Crossover Adjustment to default (0V). */
+	clrsetbits32(&hs_phy_reg->cfg_ctrl_8, CFG_CTRL_8_TX_HS_XV_TUNE_MASK, CFG_CTRL_8_TX_HS_XV_TUNE_VALUE);
+
+	/* Step 25: USB_PHY_CFG_CTRL_9[4:3] = 2'b01 (USB Source Impedance Adjustment) */
+	/* Set USB Source Impedance Adjustment to default. */
+	clrsetbits32(&hs_phy_reg->cfg_ctrl_9, CFG_CTRL_9_TX_RES_TUNE_MASK, CFG_CTRL_9_TX_RES_TUNE_VALUE);
+
+	/* Step 26: USB_PHY_HS_PHY_CTRL2[3] = 1'b1 (USB2_SUSPEND_N_SEL) */
+	/* Select SW option for suspend_n signal. */
+	clrsetbits32(&hs_phy_reg->hs_phy_ctrl2, USB2_SUSPEND_N_SEL_BIT, USB2_SUSPEND_N_SEL_BIT);
+
+	/* Step 27: USB_PHY_HS_PHY_CTRL2[2] = 1'b1 (USB2_SUSPEND_N) */
+	/* Assert USB2_SUSPEND_N. */
+	clrsetbits32(&hs_phy_reg->hs_phy_ctrl2, USB2_SUSPEND_N_BIT, USB2_SUSPEND_N_BIT);
+
+	/* Step 28: USB_PHY_UTMI_CTRL0[0] = 1'b1 (SLEEPM) */
+	/* Set sleepm = 1; until PHYCLOCK is available. */
+	clrsetbits32(&hs_phy_reg->utmi_ctrl0, SLEEPM, SLEEPM);
+
+	/* Step 29: USB_PHY_HS_PHY_CTRL_COMMON0[1] = 1'b1 (SIDDQ MUX Selection) */
+	/* Select internal CSR register (SIDDQ) for SIDDQ control. */
+	clrsetbits32(&hs_phy_reg->hs_phy_ctrl_common0, SIDDQ_SEL_BIT, SIDDQ_SEL_BIT);
+
+	/* Step 30: USB_PHY_HS_PHY_CTRL_COMMON0[2] = 1'b0 (SIDDQ set to 0) */
+	/* Power up the analog blocks by setting SIDDQ to 0. */
+	clrsetbits32(&hs_phy_reg->hs_phy_ctrl_common0, SIDDQ_DISABLE_BIT, 0);
+
+	/* Step 31: USB_PHY_UTMI_CTRL5[1] = 1'b0 (POR release) */
+	/* Release the POR from high to low. */
+	clrsetbits32(&hs_phy_reg->utmi_ctrl5, POR, 0);
+
+	/* Step 32: USB_PHY_HS_PHY_CTRL2[3] = 1'b0 (USB2_SUSPEND_N_SEL de-selects SW override) */
+	/* De-select SW override for suspend_n, allowing HW control. */
+	clrsetbits32(&hs_phy_reg->hs_phy_ctrl2, USB2_SUSPEND_N_SEL_BIT, 0);
+
+	udelay(20);
+	printk(BIOS_DEBUG, "USB HS PHY initialized for index %d\n", index);
+}
diff --git a/src/soc/qualcomm/x1p42100/usb/usb.c b/src/soc/qualcomm/x1p42100/usb/usb.c
new file mode 100644
index 0000000000..c969693c4f
--- /dev/null
+++ b/src/soc/qualcomm/x1p42100/usb/usb.c
@@ -0,0 +1,327 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <console/console.h>
+#include <device/mmio.h>
+#include <soc/usb/usb.h>
+#include <soc/addressmap.h>
+#include <soc/clock.h>
+#include <delay.h>
+#include <gpio.h>
+
+struct usb_dwc3 {
+	u32 sbuscfg0;
+	u32 sbuscfg1;
+	u32 txthrcfg;
+	u32 rxthrcfg;
+	u32 ctl;
+	u32 pmsts;
+	u32 sts;
+	u32 uctl1;
+	u32 snpsid;
+	u32 gpio;
+	u32 uid;
+	u32 uctl;
+	u64 buserraddr;
+	u64 prtbimap;
+	u8 reserved1[32];
+	u32 dbgfifospace;
+	u32 dbgltssm;
+	u32 dbglnmcc;
+	u32 dbgbmu;
+	u32 dbglspmux;
+	u32 dbglsp;
+	u32 dbgepinfo0;
+	u32 dbgepinfo1;
+	u64 prtbimap_hs;
+	u64 prtbimap_fs;
+	u8 reserved2[112];
+	u32 usb2phycfg;
+	u32 usb2phycfg_mp1;
+	u8 reserved3[120];
+	u32 usb2phyacc;
+	u8 reserved4[60];
+	u32 usb3pipectl;
+	u32 usb3pipectl_mp1;
+	u8 reserved5[56];
+};
+check_member(usb_dwc3, usb2phycfg_mp1, 0x104);
+check_member(usb_dwc3, usb3pipectl_mp1, 0x1c4);
+
+struct usb_dwc3_cfg {
+	struct usb_dwc3 *usb_host_dwc3;
+	u32 *usb3_bcr;
+	u32 *qusb2phy_bcr;
+	u32 *qusb2phy1_bcr;
+	u32 *gcc_usb3phy_bcr_reg;
+	u32 *gcc_qmpphy_bcr_reg;
+	u32 *gcc_usb3phy1_bcr_reg;
+	u32 *gcc_qmpphy1_bcr_reg;
+	u32 *qusb2secphy_bcr;
+	u32 *gcc_usb3secphy_bcr_reg;
+	u32 *gcc_qmpsecphy_bcr_reg;
+};
+
+static struct usb_dwc3_cfg usb_port0 = {
+	.usb_host_dwc3 =	(void *)USB_HOST_DWC3_BASE,
+	.usb3_bcr =		&gcc->gcc_usb30_mp_bcr,
+	.qusb2phy_bcr =		&gcc->qusb2phy_hs0_mp_bcr,
+	.gcc_usb3phy_bcr_reg =	&gcc->usb3uniphy_phy_mp0_bcr,
+	.gcc_qmpphy_bcr_reg =	&gcc->usb3_uniphy_mp0_bcr,
+	.qusb2phy1_bcr =		&gcc->qusb2phy_hs1_mp_bcr,
+	.gcc_usb3phy1_bcr_reg =	&gcc->usb3uniphy_phy_mp1_bcr,
+	.gcc_qmpphy1_bcr_reg =	&gcc->usb3_uniphy_mp1_bcr,
+};
+
+bool hs_speed_only = false;
+u32 *usb3_general_cfg_addr = (void *)USB_HOST_DWC3_GENERAL_CFG_ADDR;
+
+/* Enables Repeaters /Refgen blocks for USB */
+void enable_clock_tcsr(void)
+{
+	write32(TCSR_GCC_CXO_1_REFGEN_BIAS_SEL__SEL_REFGEN_ADDR, 0x00000001);
+	write32(TCSR_GCC_CXO_0_REFGEN_BIAS_SEL__SEL_REFGEN_ADDR, 0x00000001);
+
+	write32(TCSR_QREFS_CXO_0_RPT3_CONFIG_ADDR, 0x3);
+	write32(TCSR_QREFS_CXO_0_RPT4_CONFIG_ADDR, 0x3);
+	write32(TCSR_QREFS_CXO_1_RPT0_CONFIG_ADDR, 0x3);
+	write32(TCSR_QREFS_CXO_1_RX3_CONFIG_ADDR, 0x3);
+	write32(TCSR_QREFS_CXO_1_RX0_CONFIG_ADDR, 0x3);
+	write32(TCSR_QREFS_CXO_0_RX3_CONFIG_ADDR, 0x3);
+	write32(TCSR_QREFS_CXO_0_RX4_CONFIG_ADDR, 0x3);
+}
+/*
+ * qcom_enable_usb_clk - Enables USB clocks and GDSCs for Qualcomm SoCs.
+ * @return 0 on success, or a negative error code on failure.
+ */
+int32_t qcom_enable_usb_clk(void)
+{
+	int32_t ret, clk, gdsc;
+
+	/* Enable USB GDSCs before enabling USB clocks */
+	for (gdsc = USB30_MP_GDSC; gdsc < MAX_USB_GDSC; gdsc++) {
+		ret = clock_enable_usb_gdsc(gdsc);
+		if (ret) {
+			printk(BIOS_ERR, "Failed to enable USB GDSC %d\n", gdsc);
+			return ret;
+		}
+	}
+
+	clock_configure_usb();
+	/* Set USB3 PHY PIPE 0 clock source to X0  */
+	if (usb_clock_configure_mux(USB3_PHY_PIPE_0, USB_PHY_XO_SRC_SEL)) {
+		printk(BIOS_ERR, "%s(): USB3 PHY PIPE 0 clock enable failed\n", __func__);
+		return -1;
+	}
+	if (usb_clock_configure_mux(USB3_PHY_PIPE_1, USB_PHY_XO_SRC_SEL)) {
+		printk(BIOS_ERR, "%s(): USB3 PHY PIPE 0 clock enable failed\n", __func__);
+		return -1;
+	}
+	/* Enable USB MP clocks */
+	for (clk = USB30_MP_MASTER_CBCR; clk < USB_CLK_COUNT; clk++) {
+		ret = usb_clock_enable(clk);
+		if (ret) {
+			printk(BIOS_ERR, "Failed to enable %d clock\n", clk);
+			return ret;
+		}
+	}
+
+	write32(TCSR_GCC_USB3_MP0_CLKREF_EN_ADDR, USB3_CLKREF_ENABLE_VALUE);
+	write32(TCSR_GCC_USB3_MP1_CLKREF_EN_ADDR, USB3_CLKREF_ENABLE_VALUE);
+	/* Set USB3 PHY PIPE 1 clock source to USB PHY */
+
+	if (usb_clock_configure_mux(USB3_PHY_PIPE_0, USB_PHY_PIPE_SRC_SEL)) {
+		printk(BIOS_ERR, "%s(): USB3 PHY PIPE 1 clock enable failed\n", __func__);
+		return -1;
+	}
+
+	if (usb_clock_configure_mux(USB3_PHY_PIPE_1, USB_PHY_PIPE_SRC_SEL)) {
+		printk(BIOS_ERR, "%s(): USB3 PHY PIPE 1 clock enable failed\n", __func__);
+		return -1;
+	}
+
+	return ret;
+}
+
+/*
+ * setup_dwc3 - Configures the DWC3 USB controller.
+ * @dwc3: Pointer to the USB DWC3 configuration structure.
+ * Handles high-speed operation, power management, and sets to host mode.
+ */
+
+static void setup_dwc3(struct usb_dwc3 *dwc3)
+{
+	u32 *reg = usb3_general_cfg_addr;
+	if (hs_speed_only) {
+		/* Set UTMI_CLK_DIS_0 */
+		setbits32(reg, UTMI_CLK_DIS_0);
+		udelay(10);
+
+		/* Set UTMI_CLK_SEL_0 */
+		setbits32(reg, UTMI_CLK_SEL_0);
+
+		/* Set PIPE3_PHYSTATUS_SW_0 */
+		setbits32(reg, PIPE3_PHYSTATUS_SW_0);
+
+		/* Clear PIPE3_SET_PHYSTATUS_SW_0 */
+		clrbits32(reg, PIPE3_SET_PHYSTATUS_SW_0);
+		udelay(10);
+
+		/* Clear UTMI_CLK_DIS_0 */
+		clrbits32(reg, UTMI_CLK_DIS_0);
+	} else {
+		/* core exits U1/U2/U3 only in PHY power state P1/P2/P3 respectively */
+		clrsetbits32(&dwc3->usb3pipectl,
+			DWC3_GUSB3PIPECTL_DELAYP1TRANS,
+			DWC3_GUSB3PIPECTL_UX_EXIT_IN_PX);
+
+		clrsetbits32(&dwc3->usb3pipectl_mp1,
+			DWC3_GUSB3PIPECTL_DELAYP1TRANS,
+			DWC3_GUSB3PIPECTL_UX_EXIT_IN_PX);
+	}
+	/*
+	 * Configure USB phy interface of DWC3 core.
+	 * 1. Select UTMI+ PHY with 16-bit interface.
+	 * 2. Set USBTRDTIM to the corresponding value
+	 * according to the UTMI+ PHY interface.
+	 */
+	clrsetbits32(&dwc3->usb2phycfg,
+			(DWC3_GUSB2PHYCFG_USB2TRDTIM_MASK |
+			DWC3_GUSB2PHYCFG_PHYIF_MASK |
+		    DWC3_GUSB2PHYCFG_ENBLSLPM_MASK),
+			(DWC3_GUSB2PHYCFG_PHYIF(UTMI_PHYIF_8_BIT) |
+			DWC3_GUSB2PHYCFG_USBTRDTIM(USBTRDTIM_UTMI_8_BIT)));
+
+	clrsetbits32(&dwc3->usb2phycfg_mp1,
+			(DWC3_GUSB2PHYCFG_USB2TRDTIM_MASK |
+			DWC3_GUSB2PHYCFG_PHYIF_MASK |
+		    DWC3_GUSB2PHYCFG_ENBLSLPM_MASK),
+			(DWC3_GUSB2PHYCFG_PHYIF(UTMI_PHYIF_8_BIT) |
+			DWC3_GUSB2PHYCFG_USBTRDTIM(USBTRDTIM_UTMI_8_BIT)));
+	/*
+	To save power, enable the hardware-based clock gating (not relevant for PBL):
+	a. usb30_reg_cgctl[DBM_FSM_EN] = 0x1
+	*/
+	setbits32(USB3_MP_CGCTL_REG_ADDR, USB3_MP_DBM_FSM_EN_BIT);
+	//Disable clock gating: DWC_USB3_GCTL.DSBLCLKGTNG = 1
+	clrsetbits32(&dwc3->ctl, (DWC3_GCTL_SCALEDOWN_MASK |
+			DWC3_GCTL_DISSCRAMBLE),
+			DWC3_GCTL_U2EXIT_LFPS | DWC3_GCTL_DSBLCLKGTNG);
+
+	//Allow PHY to transition to P2 from suspend (P3) state.
+	setbits32(&dwc3->usb3pipectl,
+		(DWC3_GUSB3PIPECTL_P3EXSIGP2|
+		DWC3_GUSB3PIPECTL_UX_EXIT_IN_PX));
+
+	setbits32(&dwc3->usb3pipectl_mp1,
+		(DWC3_GUSB3PIPECTL_P3EXSIGP2|
+		DWC3_GUSB3PIPECTL_UX_EXIT_IN_PX));
+
+	// Reduce U3 exit handshake timer to 300ns
+	clrsetbits32(USB3_MP_LINK_REGS_0_LU3LFPSRXTIM_ADDR,
+				LFPS_RSP_RX_CLK_CLR_MASK, LFPS_RSP_RX_CLK_SET_MASK);
+
+	clrsetbits32(USB3_MP_LINK_REGS_1_LU3LFPSRXTIM_ADDR,
+				LFPS_RSP_RX_CLK_CLR_MASK, LFPS_RSP_RX_CLK_SET_MASK);
+
+	clrsetbits32(&dwc3->uctl1,
+					DWC3_GUCTL1_CLR_MASK, // Clear L1 exit and IP gap bits
+					DWC3_GUCTL1_SET_MASK);
+
+	clrbits32(USB3_MP_GUSB2PHYCFG_REGS_0_ADDR, GUSB2PHYCFG_ENBLSLPM_BIT);
+
+	clrbits32(USB3_MP_GUSB2PHYCFG_REGS_1_ADDR, GUSB2PHYCFG_ENBLSLPM_BIT);
+
+	/* configure controller in Host mode */
+	clrsetbits32(&dwc3->ctl, (DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_OTG)),
+			DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_HOST));
+	printk(BIOS_SPEW, "Configure USB in Host mode\n");
+
+	setbits32(USB3_MP_PORTSC_20_REGS_0_ADDR, USB3_PORTSC_WCE_BIT);
+
+	setbits32(USB3_MP_PORTSC_20_REGS_1_ADDR, USB3_PORTSC_WCE_BIT);
+
+	setbits32(USB3_MP_PORTSC_30_REGS_0_ADDR, USB3_PORTSC_WCE_BIT);
+
+	setbits32(USB3_MP_PORTSC_30_REGS_1_ADDR, USB3_PORTSC_WCE_BIT);
+
+}
+
+/* Initialization of DWC3 Core and PHY */
+static void setup_usb_host(struct usb_dwc3_cfg *dwc3)
+{
+	/* Call Clock Enable */
+	qcom_enable_usb_clk();
+
+	enable_clock_tcsr();
+
+	/* Clear core reset. */
+	clock_reset_bcr(dwc3->usb3_bcr, 1);
+	udelay(10);
+	clock_reset_bcr(dwc3->usb3_bcr, 0);
+	udelay(10);
+
+	/* Repeater enable MP0*/
+	gpio_output(GPIO(6), 0x1);
+
+	/* Repeater enable MP1*/
+	gpio_output(GPIO(184), 0x1);
+
+	/* Clear QUSB PHY reset. */
+	clock_reset_bcr(dwc3->qusb2phy_bcr, 1);
+	clock_reset_bcr(dwc3->qusb2phy1_bcr, 1);
+	udelay(10);
+	clock_reset_bcr(dwc3->qusb2phy_bcr, 0);
+	clock_reset_bcr(dwc3->qusb2phy1_bcr, 0);
+
+	/* Initialize HS PHY */
+	hs_usb_phy_init(0);
+	hs_usb_phy_init(1);
+
+	/* Clear QMP PHY resets. */
+	usb_clock_reset(USB3_MP_PHY_PIPE_0_CBCR, 1);
+	usb_clock_reset(USB3_MP_PHY_PIPE_1_CBCR, 1);
+	udelay(10);
+
+	usb_clock_reset(USB30_MP_MASTER_CBCR, 1);
+	usb_clock_reset(USB30_MP_MASTER_CBCR, 0);
+	udelay(10);
+
+	clock_reset_bcr(dwc3->gcc_usb3phy_bcr_reg, 1);
+	clock_reset_bcr(dwc3->gcc_qmpphy_bcr_reg, 1);
+
+	clock_reset_bcr(dwc3->gcc_usb3phy1_bcr_reg, 1);
+	clock_reset_bcr(dwc3->gcc_qmpphy1_bcr_reg, 1);
+	udelay(10);
+
+	clock_reset_bcr(dwc3->gcc_usb3phy_bcr_reg, 0);
+	clock_reset_bcr(dwc3->gcc_qmpphy_bcr_reg, 0);
+
+	clock_reset_bcr(dwc3->gcc_usb3phy1_bcr_reg, 0);
+	clock_reset_bcr(dwc3->gcc_qmpphy1_bcr_reg, 0);
+	udelay(10);
+
+	usb_clock_reset(USB3_MP_PHY_PIPE_0_CBCR, 0);
+	usb_clock_reset(USB3_MP_PHY_PIPE_1_CBCR, 0);
+
+	/* Initialize QMP PHY */
+	bool ret0 = ss_qmp_phy_init(0);
+	bool ret1 = ss_qmp_phy_init(1);
+
+	/* If SS PHY init fails fall back to HS speed */
+	if (!ret0 || !ret1)
+		hs_speed_only = true;
+
+	setup_dwc3(dwc3->usb_host_dwc3);
+
+	printk(BIOS_INFO, "DWC3 and PHY setup finished\n");
+}
+/*
+ * setup_usb_host0 - Sets up USB HOST0 controller.
+ * Initializes and configures the USB HOST0 controller, including clocks,
+ * PHY resets, and DWC3 core for host mode.
+*/
+void setup_usb_host0(void)
+{
+	printk(BIOS_INFO, "Setting up USB HOST0 controller.\n");
+	setup_usb_host(&usb_port0);
+}

From 492826771e835052c1adffb6303f4e4b7bc29445 Mon Sep 17 00:00:00 2001
From: Hari L <haril@qualcomm.corp-partner.google.com>
Date: Thu, 11 Sep 2025 11:39:16 +0530
Subject: [PATCH 1987/3886] mb/google/bluey: Enable USB support

BUG=b:440996061
TEST=Ensure that pipe/utmi clocks are ON and check
port link status to confirm USB connect.

Change-Id: If0997ecb43eb5f687f1416abe42764fa31b1eaf5
Signed-off-by: Hari L <haril@qualcomm.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89146
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
---
 src/mainboard/google/bluey/mainboard.c | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/src/mainboard/google/bluey/mainboard.c b/src/mainboard/google/bluey/mainboard.c
index 58035a3290..1c9a87f844 100644
--- a/src/mainboard/google/bluey/mainboard.c
+++ b/src/mainboard/google/bluey/mainboard.c
@@ -10,6 +10,12 @@
 #include <soc/qupv3_config_common.h>
 #include <soc/qup_se_handlers_common.h>
 #include "board.h"
+#include <soc/usb/usb.h>
+
+static void setup_usb(void)
+{
+	setup_usb_host0();
+}
 
 void lb_add_boot_mode(struct lb_header *header)
 {
@@ -76,6 +82,9 @@ static void mainboard_init(struct device *dev)
 	if (CONFIG(MAINBOARD_HAS_FINGERPRINT))
 		gpio_output(GPIO_FP_RST_L, 1);
 
+	/* Setup USB related initial config */
+	setup_usb();
+
 	display_startup();
 }
 

From 164b4a1d90f1f564879cd97fa1d9e7b3a8f38ef6 Mon Sep 17 00:00:00 2001
From: David Wu <david_wu@quanta.corp-partner.google.com>
Date: Mon, 1 Sep 2025 19:12:49 +0800
Subject: [PATCH 1988/3886] mb/google/nissa/var/craask: Add parade touchscreen
 support

This change adds the necessary configuration for the parade
touchscreen (PRT3406) device, connected to I2C bus 24.

It includes settings for:
* HID descriptor
* Device description
* IRQ configuration
* Detection
* Reset, stop and enable GPIOs with their respective delays
* Power resource handling
* HID descriptor register offset

BUG=b:431660019
TEST=emerge-nissa coreboot and parade touchscreen can work well

Change-Id: Iaaf740032de973461b616e186ac628436cbbc2a5
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89009
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
---
 .../brya/variants/craask/overridetree.cb      | 21 +++++++++++++++++++
 1 file changed, 21 insertions(+)

diff --git a/src/mainboard/google/brya/variants/craask/overridetree.cb b/src/mainboard/google/brya/variants/craask/overridetree.cb
index 677abedb47..7014e6a77f 100644
--- a/src/mainboard/google/brya/variants/craask/overridetree.cb
+++ b/src/mainboard/google/brya/variants/craask/overridetree.cb
@@ -39,6 +39,7 @@ fw_config
 		option TS_GTCH7503		1
 		option TS_ILTK0001		2
 		option TS_FTSC1000		3
+		option TS_PRT3406		4
 	end
 end
 
@@ -449,6 +450,26 @@ chip soc/intel/alderlake
 					probe TS_SOURCE TS_FTSC1000
 				end
 			end
+			chip drivers/i2c/hid
+				register "generic.hid" = ""PRT3406""
+				register "generic.desc" = ""Parade Touchscreen""
+				register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_C7_IRQ)"
+				register "generic.detect" = "1"
+				register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C1)"
+				register "generic.reset_delay_ms" = "130"
+				register "generic.reset_off_delay_ms" = "2"
+				register "generic.stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C6)"
+				register "generic.stop_delay_ms" = "280"
+				register "generic.stop_off_delay_ms" = "2"
+				register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C0)"
+				register "generic.enable_delay_ms" = "1"
+				register "generic.has_power_resource" = "1"
+				register "generic.use_gpio_for_status" = "true"
+				register "hid_desc_reg_offset" = "0x01"
+				device i2c 24 on
+					probe TS_SOURCE TS_PRT3406
+				end
+			end
 		end
 		device ref i2c2 on
 			chip drivers/intel/mipi_camera

From c1f76dd87ea6659f1648a7e87702b722be118d86 Mon Sep 17 00:00:00 2001
From: David Wu <david_wu@quanta.corp-partner.google.com>
Date: Thu, 11 Sep 2025 14:21:44 +0800
Subject: [PATCH 1989/3886] mb/google/brya/var/dochi: Add H58G56CK8BX146 to RAM
 ID table

Add the new memory support: Hynix H58G56CK8BX146

BUG=b:444335746
BRANCH=firmware-brya-14505.B
TEST=Run part_id_gen tool and check the generated files.

Change-Id: Id473adafffc1dabcb8f8e9a1f548966a0ba5a334
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89147
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/google/brya/variants/dochi/memory/Makefile.mk     | 2 +-
 .../google/brya/variants/dochi/memory/dram_id.generated.txt     | 1 +
 .../google/brya/variants/dochi/memory/mem_parts_used.txt        | 1 +
 3 files changed, 3 insertions(+), 1 deletion(-)

diff --git a/src/mainboard/google/brya/variants/dochi/memory/Makefile.mk b/src/mainboard/google/brya/variants/dochi/memory/Makefile.mk
index 32849a32d3..3e7981c6cb 100644
--- a/src/mainboard/google/brya/variants/dochi/memory/Makefile.mk
+++ b/src/mainboard/google/brya/variants/dochi/memory/Makefile.mk
@@ -4,5 +4,5 @@
 # ./util/spd_tools/bin/part_id_gen ADL lp5 src/mainboard/google/brya/variants/dochi/memory src/mainboard/google/brya/variants/dochi/memory/mem_parts_used.txt
 
 SPD_SOURCES =
-SPD_SOURCES += spd/lp5/set-0/spd-11.hex      # ID = 0(0b0000)  Parts = MT62F1G32D2DS-023 WT:B, H58G56BK8BX068
+SPD_SOURCES += spd/lp5/set-0/spd-11.hex      # ID = 0(0b0000)  Parts = MT62F1G32D2DS-023 WT:B, H58G56BK8BX068, H58G56CK8BX146
 SPD_SOURCES += spd/lp5/set-0/spd-7.hex      # ID = 1(0b0001)  Parts = K3KL8L80CM-MGCT
diff --git a/src/mainboard/google/brya/variants/dochi/memory/dram_id.generated.txt b/src/mainboard/google/brya/variants/dochi/memory/dram_id.generated.txt
index b64aa5a20e..bf2d83fffe 100644
--- a/src/mainboard/google/brya/variants/dochi/memory/dram_id.generated.txt
+++ b/src/mainboard/google/brya/variants/dochi/memory/dram_id.generated.txt
@@ -7,3 +7,4 @@ DRAM Part Name                 ID to assign
 MT62F1G32D2DS-023 WT:B         0 (0000)
 K3KL8L80CM-MGCT                1 (0001)
 H58G56BK8BX068                 0 (0000)
+H58G56CK8BX146                 0 (0000)
diff --git a/src/mainboard/google/brya/variants/dochi/memory/mem_parts_used.txt b/src/mainboard/google/brya/variants/dochi/memory/mem_parts_used.txt
index 74dc4266e1..dda58b6991 100644
--- a/src/mainboard/google/brya/variants/dochi/memory/mem_parts_used.txt
+++ b/src/mainboard/google/brya/variants/dochi/memory/mem_parts_used.txt
@@ -12,3 +12,4 @@
 MT62F1G32D2DS-023 WT:B
 K3KL8L80CM-MGCT
 H58G56BK8BX068
+H58G56CK8BX146

From 18ae0c48e110117270b043c25127bf6f178e205c Mon Sep 17 00:00:00 2001
From: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
Date: Tue, 9 Sep 2025 19:06:19 +0800
Subject: [PATCH 1990/3886] mb/google/fatcat/var/moonstone: Support new
 schematic changes

Add FW_config support to distinguish schematic changes.
Refer to schamtics MB_V20250826 and DB_V20250821

BUG=b:442964982
TEST=emerge-fatcat coreboot

Change-Id: I0dd354cb1512521474a929bf4d1cfc786eb0a33c
Signed-off-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89128
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 .../fatcat/variants/moonstone/Makefile.mk     |   2 +
 .../fatcat/variants/moonstone/fw_config.c     | 137 ++++++++++++++++++
 .../google/fatcat/variants/moonstone/gpio.c   |  32 ----
 .../fatcat/variants/moonstone/overridetree.cb |  86 ++++++++++-
 .../fatcat/variants/moonstone/variant.c       |  59 ++++++++
 5 files changed, 276 insertions(+), 40 deletions(-)
 create mode 100644 src/mainboard/google/fatcat/variants/moonstone/fw_config.c

diff --git a/src/mainboard/google/fatcat/variants/moonstone/Makefile.mk b/src/mainboard/google/fatcat/variants/moonstone/Makefile.mk
index cbe8155bd4..eb361dfe89 100644
--- a/src/mainboard/google/fatcat/variants/moonstone/Makefile.mk
+++ b/src/mainboard/google/fatcat/variants/moonstone/Makefile.mk
@@ -3,5 +3,7 @@
 bootblock-y += gpio.c
 romstage-y += gpio.c
 romstage-y += memory.c
+romstage-$(CONFIG_FW_CONFIG) += fw_config.c
 ramstage-y += gpio.c
 ramstage-$(CONFIG_FW_CONFIG) += variant.c
+ramstage-$(CONFIG_FW_CONFIG) += fw_config.c
diff --git a/src/mainboard/google/fatcat/variants/moonstone/fw_config.c b/src/mainboard/google/fatcat/variants/moonstone/fw_config.c
new file mode 100644
index 0000000000..02fc5c82e2
--- /dev/null
+++ b/src/mainboard/google/fatcat/variants/moonstone/fw_config.c
@@ -0,0 +1,137 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <baseboard/variants.h>
+#include <console/console.h>
+#include <fw_config.h>
+#include <gpio.h>
+#include <inttypes.h>
+
+/* t: base table; o: override table */
+#define GPIO_PADBASED_OVERRIDE(t, o) gpio_padbased_override(t, o, ARRAY_SIZE(o))
+/* t: table */
+#define GPIO_CONFIGURE_PADS(t) gpio_configure_pads(t, ARRAY_SIZE(t))
+
+static const struct pad_config fp_spi_disable_pads[] = {
+	PAD_NC(GPP_C15, NONE),
+	PAD_NC(GPP_E11, NONE),
+	PAD_NC(GPP_E17, NONE),
+	PAD_NC(GPP_E20, NONE),
+	PAD_NC(GPP_E22, NONE),
+	PAD_NC(GPP_F14, NONE),
+	PAD_NC(GPP_F15, NONE),
+};
+
+static const struct pad_config fp_spi_enable_pads[] = {
+	/* GPP_C15:     FPS_RST_N */
+	PAD_CFG_GPO_LOCK(GPP_C15, 1, LOCK_CONFIG),
+	/* GPP_E11:     GPSI0_CLK */
+	PAD_CFG_NF(GPP_E11, NONE, DEEP, NF5),
+	/* GPP_E17:     GSPI0_CS0 */
+	PAD_CFG_NF(GPP_E17, NONE, DEEP, NF5),
+	/* GPP_E20:     FPMCU_FW_UPDATE */
+	PAD_CFG_GPO_LOCK(GPP_E20, 0, LOCK_CONFIG),
+	/* GPP_E22:     FPS_SOC_INT_L */
+	PAD_CFG_GPI_IRQ_WAKE(GPP_E22, NONE, PWROK, LEVEL, INVERT),
+	/* GPP_F14:     GPSI0A_MOSI */
+	PAD_CFG_NF(GPP_F14, NONE, DEEP, NF8),
+	/* GPP_F15:     GSPI0A_MISO */
+	PAD_CFG_NF(GPP_F15, NONE, DEEP, NF8),
+};
+
+static const struct pad_config use_usb3c_enable_pads[] = {
+	/* GPP_C20:     NC */
+	PAD_NC(GPP_C20, NONE),
+	/* GPP_C21:     NC */
+	PAD_NC(GPP_C21, NONE),
+	/* GPP_C22:     TBT_LSX3_TXD  */
+	PAD_CFG_NF(GPP_C22, NONE, DEEP, NF1),
+	/* GPP_C23:     TBT_LSX3_RXD  */
+	PAD_CFG_NF(GPP_C23, NONE, DEEP, NF1),
+	/* GPP_B14:     NC */
+	PAD_NC(GPP_B14, NONE),
+	/* GPP_B11:     NC */
+	PAD_NC(GPP_B11, NONE),
+	/* GPP_E09:     NC */
+	PAD_NC(GPP_E09, NONE),
+};
+
+static const struct pad_config use_usb2a2c_hdmi_enable_pads[] = {
+	/* GPP_C20:     TBT_LSX2_TXD */
+	PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1),
+	/* GPP_C21:     TBT_LSX2_RXD */
+	PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1),
+	/* GPP_C22:     DDP3_CTRLCLK */
+	PAD_CFG_NF(GPP_C22, NONE, DEEP, NF2),
+	/* GPP_C23:     DDP3_CTRLDATA */
+	PAD_CFG_NF(GPP_C23, NONE, DEEP, NF2),
+	/* GPP_B14:     DISP_HPD4 */
+	PAD_CFG_NF(GPP_B14, NONE, DEEP, NF2),
+	/* GPP_B11:     USB_OC1 */
+	PAD_CFG_NF(GPP_B11, NONE, DEEP, NF1),
+	/* GPP_E09:     USB_OC0 */
+	PAD_CFG_NF(GPP_E09, NONE, DEEP, NF1),
+};
+
+static const struct pad_config pre_mem_fp_spi_enable_pads[] = {
+	/* GPP_C15:     FPS_RST_N */
+	PAD_CFG_GPO(GPP_C15, 0, DEEP),
+};
+
+void fw_config_configure_pre_mem_gpio(void)
+{
+	if (!fw_config_is_provisioned()) {
+		printk(BIOS_WARNING, "FW_CONFIG is not provisioned, Exiting\n");
+		return;
+	}
+
+	if (fw_config_probe(FW_CONFIG(FPMCU, FP_SPI)))
+		GPIO_CONFIGURE_PADS(pre_mem_fp_spi_enable_pads);
+
+}
+
+void fw_config_gpio_padbased_override(struct pad_config *padbased_table)
+{
+	if (!fw_config_is_provisioned()) {
+		printk(BIOS_WARNING, "FW_CONFIG is not provisioned, Exiting\n");
+		return;
+	}
+	/*
+	 *+-------+--------+-------------+
+	 *|       | FP_SPI | FP_USB      |
+	 *+-------+--------+-------------+
+	 *| FPMCU | GSPI0  | usb2_port6  |
+	 *+-------+--------+-------------+
+	 */
+	if (fw_config_probe(FW_CONFIG(FPMCU, FP_SPI))) {
+		GPIO_PADBASED_OVERRIDE(padbased_table, fp_spi_enable_pads);
+	} else {
+		GPIO_PADBASED_OVERRIDE(padbased_table, fp_spi_disable_pads);
+	}
+	/* Probe fw_config : "IO_PORT" to reconfigure port settings accordingly.
+	 * proto0  : IO_PORT => "USB2A2C_HDMI:0"
+	 * porot1.5: IO_PORT => "USB3C:1"
+	 * +-----------------+------------------+------------------+
+	 *| IO_PORT         | USB2A2C_HDMI     |  USB3C           |
+	 *+-----------------+------------------+------------------+
+	 *| tcss_usb3_port0 | USB4_C0 (MB-TBT) | USB4_C0 (MB-TBT) |
+	 *+-----------------+------------------+------------------+
+	 *| tcss_usb3_port1 | N/A              | USB3.2 C2 (DB)   |
+	 *+-----------------+------------------+------------------+
+	 *| tcss_usb3_port2 | USB4_C1 (MB-TBT) | N/A              |
+	 *+-----------------+------------------+------------------+
+	 *| tcss_usb3_port3 | Fixed HDMI       | USB4_C1 (MB-TBT) |
+	 *+-----------------+------------------+------------------+
+	 *| usb3_port1      | USB3_A0          | N/A              |
+	 *+-----------------+------------------+------------------+
+	 *| usb3_port2      | USB3_A1          | N/A              |
+	 *+-----------------+------------------+------------------+
+	 *| usb2_port5      | USB2_A0          | USB2_C2 (DB)     |
+	 *+-----------------+------------------+------------------+
+	 *| usb2_port6      | USB2_A1          | USB_FP           |
+	 *+-----------------+------------------+------------------+
+	 */
+	if (fw_config_probe(FW_CONFIG(IO_PORT, USB3C)))
+		GPIO_PADBASED_OVERRIDE(padbased_table, use_usb3c_enable_pads);
+	else
+		GPIO_PADBASED_OVERRIDE(padbased_table, use_usb2a2c_hdmi_enable_pads);
+}
diff --git a/src/mainboard/google/fatcat/variants/moonstone/gpio.c b/src/mainboard/google/fatcat/variants/moonstone/gpio.c
index 9a28421783..7f6aa0cdb7 100644
--- a/src/mainboard/google/fatcat/variants/moonstone/gpio.c
+++ b/src/mainboard/google/fatcat/variants/moonstone/gpio.c
@@ -69,14 +69,10 @@ static const struct pad_config gpio_table[] = {
 	PAD_NC(GPP_B09, NONE),
 	/* GPP_B10:     NC */
 	PAD_NC(GPP_B10, NONE),
-	/* GPP_B11:     USB_OC1 */
-	PAD_CFG_NF(GPP_B11, NONE, DEEP, NF1),
 	/* GPP_B12:     PM_SLP_S0_N */
 	PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1),
 	/* GPP_B13:     PLT_RST_N */
 	PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1),
-	/* GPP_B14:     DISP_HPD4 */
-	PAD_CFG_NF(GPP_B14, NONE, DEEP, NF2),
 	/* GPP_B15:     NC */
 	PAD_NC(GPP_B15, NONE),
 	/* GPP_B16:     GEN5_SSD_PWREN */
@@ -132,8 +128,6 @@ static const struct pad_config gpio_table[] = {
 	PAD_CFG_NF(GPP_C13, NONE, DEEP, NF1),
 	/* GPP_C14:     NC */
 	PAD_NC(GPP_C14, NONE),
-	/* GPP_C15:     FPS_RST_N */
-	PAD_CFG_GPO_LOCK(GPP_C15, 1, LOCK_CONFIG),
 	/* GPP_C16:     TBT_LSX0_TXD  */
 	PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1),
 	/* GPP_C17:     TBT_LSX0_RXD  */
@@ -142,14 +136,6 @@ static const struct pad_config gpio_table[] = {
 	PAD_NC(GPP_C18, NONE),
 	/* GPP_C19:     NC */
 	PAD_NC(GPP_C19, NONE),
-	/* GPP_C20:     TBT_LSX2_TXD */
-	PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1),
-	/* GPP_C21:     TBT_LSX2_RXD */
-	PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1),
-	/* GPP_C22:     DDP3_CTRLCLK */
-	PAD_CFG_NF(GPP_C22, NONE, DEEP, NF2),
-	/* GPP_C23:     DDP3_CTRLDATA */
-	PAD_CFG_NF(GPP_C23, NONE, DEEP, NF2),
 
 	/* GPP_D00:     NC */
 	PAD_NC(GPP_D00, NONE),
@@ -216,12 +202,8 @@ static const struct pad_config gpio_table[] = {
 	PAD_CFG_GPI_APIC_LOCK(GPP_E07, NONE, LEVEL, INVERT, LOCK_CONFIG),
 	/* GPP_E08:     NC */
 	PAD_NC(GPP_E08, NONE),
-	/* GPP_E09:     USB_OC0 */
-	PAD_CFG_NF(GPP_E09, NONE, DEEP, NF1),
 	/* GPP_E10:     NC */
 	PAD_NC(GPP_E10, NONE),
-	/* GPP_E11:     GPSI0_CLK */
-	PAD_CFG_NF(GPP_E11, NONE, DEEP, NF5),
 	/* GPP_E12:     TCHPAD_I2C4_SCL */
 	PAD_CFG_NF(GPP_E12, NONE, DEEP, NF8),
 	/* GPP_E13:     TCHPAD_I2C4_SDA */
@@ -232,18 +214,12 @@ static const struct pad_config gpio_table[] = {
 	PAD_NC(GPP_E15, NONE),
 	/* GPP_E16:     NC */
 	PAD_NC(GPP_E16, NONE),
-	/* GPP_E17:     GSPI0_CS0 */
-	PAD_CFG_NF(GPP_E17, NONE, DEEP, NF5),
 	/* GPP_E18:     TCHPAD_INT# */
 	PAD_CFG_GPI_APIC(GPP_E18, NONE, PLTRST, LEVEL, INVERT),
 	/* GPP_E19:     FPMCU_PWREN */
 	PAD_CFG_GPO(GPP_E19, 1, DEEP),
-	/* GPP_E20:     FPMCU_FW_UPDATE */
-	PAD_CFG_GPO_LOCK(GPP_E20, 0, LOCK_CONFIG),
 	/* GPP_E21:     I2C_PMC_PD_INT_N */
 	PAD_CFG_NF(GPP_E21, NONE, DEEP, NF1),
-	/* GPP_E22:     FPS_SOC_INT_L */
-	PAD_CFG_GPI_IRQ_WAKE(GPP_E22, NONE, PWROK, LEVEL, INVERT),
 
 	/* GPP_F00:     M.2_CNV_BRI_DT_BT_UART2_RTS_N */
 	/* NOTE: IOSSTAGE: 'Ignore' for S0ix */
@@ -279,10 +255,6 @@ static const struct pad_config gpio_table[] = {
 	PAD_CFG_NF(GPP_F12, NONE, DEEP, NF8),
 	/* GPP_F13:     TCHSCR_I2C5_SDA */
 	PAD_CFG_NF(GPP_F13, NONE, DEEP, NF8),
-	/* GPP_F14:     GPSI0A_MOSI */
-	PAD_CFG_NF(GPP_F14, NONE, DEEP, NF8),
-	/* GPP_F15:     GSPI0A_MISO */
-	PAD_CFG_NF(GPP_F15, NONE, DEEP, NF8),
 	/* GPP_F16:     TCHSCR_RST_L */
 	PAD_CFG_GPO(GPP_F16, 1, DEEP),
 	/* GPP_F17:     NC */
@@ -420,10 +392,6 @@ static const struct pad_config romstage_gpio_table[] = {
 	PAD_CFG_NF(GPP_C01, NONE, DEEP, NF1),
 	/* GPP_E03:     GEN5_SSD_RESET_N */
 	PAD_CFG_GPO(GPP_E03, 1, PLTRST),
-	/* GPP_E19:     FPMCU_PWREN */
-	PAD_CFG_GPO(GPP_E19, 0, DEEP),
-	/* GPP_C15:     FPS_RST_N */
-	PAD_CFG_GPO(GPP_C15, 0, DEEP),
 };
 
 const struct pad_config *variant_gpio_table(size_t *num)
diff --git a/src/mainboard/google/fatcat/variants/moonstone/overridetree.cb b/src/mainboard/google/fatcat/variants/moonstone/overridetree.cb
index 624fa76f3b..18a506700f 100644
--- a/src/mainboard/google/fatcat/variants/moonstone/overridetree.cb
+++ b/src/mainboard/google/fatcat/variants/moonstone/overridetree.cb
@@ -6,6 +6,15 @@ fw_config
 		option AUDIO_UNKNOWN		0
 		option AUDIO_ALC721_SNDW	1
 	end
+	field FPMCU 6 7
+		option FP_ABSENT		0
+		option FP_SPI			1
+		option FP_USB			2
+	end
+	field IO_PORT 12 12
+		option USB2A2C_HDMI		0
+		option USB3C			1
+	end
 end
 
 chip soc/intel/pantherlake
@@ -38,6 +47,7 @@ chip soc/intel/pantherlake
 	register "tcss_ports[2]" = "TCSS_PORT_DEFAULT(OC_SKIP)" # USB3_C1
 
 	register "tcss_cap_policy[0]" = "TCSS_TYPE_C_PORT_FULL_FUN"
+	register "tcss_cap_policy[1]" = "TCSS_TYPE_C_PORT_FULL_FUN"
 	register "tcss_cap_policy[2]" = "TCSS_TYPE_C_PORT_FULL_FUN"
 	register "tcss_cap_policy[3]" = "TCSS_TYPE_C_PORT_FULL_FUN"
 
@@ -114,7 +124,12 @@ chip soc/intel/pantherlake
 
 		device ref iaa off end
 		device ref tbt_pcie_rp0 on end
-		device ref tbt_pcie_rp2 on end
+		device ref tbt_pcie_rp1 on
+			probe IO_PORT USB3C
+		end
+		device ref tbt_pcie_rp2 on
+			probe IO_PORT USB2A2C_HDMI
+		end
 		device ref tbt_pcie_rp3 on end
 		device ref tcss_xhci on
 			chip drivers/usb/acpi
@@ -125,11 +140,29 @@ chip soc/intel/pantherlake
 						register "group" = "ACPI_PLD_GROUP(1, 2)"
 						device ref tcss_usb3_port0 on end
 					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB3 Type-C Port C2""
+						register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
+						register "group" = "ACPI_PLD_GROUP(3, 2)"
+						device ref tcss_usb3_port1 on
+							probe IO_PORT USB3C
+						end
+					end
 					chip drivers/usb/acpi
 						register "desc" = ""USB3 Type-C Port C1""
 						register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
 						register "group" = "ACPI_PLD_GROUP(2, 2)"
-						device ref tcss_usb3_port2 on end
+						device ref tcss_usb3_port2 on
+							probe IO_PORT USB2A2C_HDMI
+						end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB3 Type-C Port C1""
+						register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
+						register "group" = "ACPI_PLD_GROUP(2, 2)"
+						device ref tcss_usb3_port3 on
+							probe IO_PORT USB3C
+						end
 					end
 				end
 			end
@@ -146,7 +179,16 @@ chip soc/intel/pantherlake
 			chip drivers/intel/usb4/retimer
 				register "dfp[0].power_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B21)"
 				use tcss_usb3_port2 as dfp[0].typec_port
-				device generic 0 on end
+				device generic 0 on
+					probe IO_PORT USB2A2C_HDMI
+				end
+			end
+			chip drivers/intel/usb4/retimer
+				register "dfp[0].power_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B21)"
+				use tcss_usb3_port3 as dfp[0].typec_port
+				device generic 0 on
+					probe IO_PORT USB3C
+				end
 			end
 		end
 
@@ -172,6 +214,14 @@ chip soc/intel/pantherlake
 						register "group" = "ACPI_PLD_GROUP(2, 1)"
 						device ref usb2_port2 on end
 					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB2 Type-C Port C2""
+						register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
+						register "group" = "ACPI_PLD_GROUP(3, 1)"
+						device ref usb2_port5 on
+							probe IO_PORT USB3C
+						end
+					end
 					chip drivers/usb/acpi
 						register "desc" = ""USB2 Camera""
 						register "type" = "UPC_TYPE_INTERNAL"
@@ -183,25 +233,42 @@ chip soc/intel/pantherlake
 						register "desc" = ""USB2 Type-A Port 0""
 						register "type" = "UPC_TYPE_A"
 						register "group" = "ACPI_PLD_GROUP(3, 1)"
-						device ref usb2_port5 on end
+						device ref usb2_port5 on
+							probe IO_PORT USB2A2C_HDMI
+						end
 					end
 					chip drivers/usb/acpi
 						register "desc" = ""USB2 Type-A Port 1""
 						register "type" = "UPC_TYPE_A"
 						register "group" = "ACPI_PLD_GROUP(4, 1)"
-						device ref usb2_port6 on end
+						device ref usb2_port6 on
+							probe IO_PORT USB2A2C_HDMI
+						end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB2 FPMCU""
+						register "type" = "UPC_TYPE_INTERNAL"
+						register "has_power_resource" = "true"
+						register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E19)"
+						device ref usb2_port6 on
+							probe FPMCU FP_USB
+						end
 					end
 					chip drivers/usb/acpi
 						register "desc" = ""USB3 Type-A Port 0""
 						register "type" = "UPC_TYPE_USB3_A"
 						register "group" = "ACPI_PLD_GROUP(3, 2)"
-						device ref usb3_port1 on end
+						device ref usb3_port1 on
+							probe IO_PORT USB2A2C_HDMI
+						end
 					end
 					chip drivers/usb/acpi
 						register "desc" = ""USB3 Type-A Port 1""
 						register "type" = "UPC_TYPE_USB3_A"
 						register "group" = "ACPI_PLD_GROUP(4, 2)"
-						device ref usb3_port2 on end
+						device ref usb3_port2 on
+							probe IO_PORT USB2A2C_HDMI
+						end
 					end
 				end
 			end
@@ -285,6 +352,7 @@ chip soc/intel/pantherlake
 			end
 		end # I2C5
 		device ref gspi0 on
+			probe FPMCU FP_SPI
 			chip drivers/spi/acpi
 				register "name" = ""CRFP""
 				register "hid" = "ACPI_DT_NAMESPACE_HID"
@@ -297,7 +365,9 @@ chip soc/intel/pantherlake
 				register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C15)"
 				register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E19)"
 				register "enable_delay_ms" = "3"
-				device spi 0 on end
+				device spi 0 on
+					probe FPMCU FP_SPI
+				end
 			end
 		end
 
diff --git a/src/mainboard/google/fatcat/variants/moonstone/variant.c b/src/mainboard/google/fatcat/variants/moonstone/variant.c
index 4221a5bf8e..bf159c7e76 100644
--- a/src/mainboard/google/fatcat/variants/moonstone/variant.c
+++ b/src/mainboard/google/fatcat/variants/moonstone/variant.c
@@ -1,5 +1,8 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
+#include <baseboard/gpio.h>
+#include <baseboard/variants.h>
+#include <console/console.h>
 #include <fw_config.h>
 #include <sar.h>
 
@@ -7,3 +10,59 @@ const char *get_wifi_sar_cbfs_filename(void)
 {
 	return get_wifi_sar_fw_config_filename(FW_CONFIG_FIELD(WIFI));
 }
+
+void variant_update_soc_chip_config(struct soc_intel_pantherlake_config *config)
+{
+	/*
+	 *+-------+--------+-------------+
+	 *|       | FP_SPI | FP_USB      |
+	 *+-------+--------+-------------+
+	 *| FPMCU | GSPI0  | usb2_port6  |
+	 *+-------+--------+-------------+
+	 */
+	if (fw_config_probe(FW_CONFIG(FPMCU, FP_USB))) {
+		printk(BIOS_INFO, "Disable GSPI\n");
+		config->serial_io_gspi_mode[PchSerialIoIndexGSPI0] = PchSerialIoDisabled;
+		printk(BIOS_INFO, "usb2_port6 to FP\n");
+		config->usb2_ports[5] = (struct usb2_port_config) USB2_PORT_MID(OC_SKIP);
+	}
+	/* Probe fw_config : "IO_PORT" to reconfigure port settings accordingly.
+	 * proto0  : IO_PORT => "USB2A2C_HDMI:0"
+	 * porot1.5: IO_PORT => "USB3C:1"
+	 * +-----------------+------------------+------------------+
+	 *| IO_PORT         | USB2A2C_HDMI     |  USB3C           |
+	 *+-----------------+------------------+------------------+
+	 *| tcss_usb3_port0 | USB4_C0 (MB-TBT) | USB4_C0 (MB-TBT) |
+	 *+-----------------+------------------+------------------+
+	 *| tcss_usb3_port1 | N/A              | USB3.2 C2 (DB)   |
+	 *+-----------------+------------------+------------------+
+	 *| tcss_usb3_port2 | USB4_C1 (MB-TBT) | N/A              |
+	 *+-----------------+------------------+------------------+
+	 *| tcss_usb3_port3 | Fixed HDMI       | USB4_C1 (MB-TBT) |
+	 *+-----------------+------------------+------------------+
+	 *| usb3_port1      | USB3_A0          | N/A              |
+	 *+-----------------+------------------+------------------+
+	 *| usb3_port2      | USB3_A1          | N/A              |
+	 *+-----------------+------------------+------------------+
+	 *| usb2_port5      | USB2_A0          | USB2_C2 (DB)     |
+	 *+-----------------+------------------+------------------+
+	 *| usb2_port6      | USB2_A1          | USB_FP           |
+	 *+-----------------+------------------+------------------+
+	 */
+
+	if (fw_config_probe(FW_CONFIG(IO_PORT, USB3C))) {
+		printk(BIOS_INFO, "Disable Type-A Port A0/A1\n");
+		config->usb3_ports[0] = (struct usb3_port_config) USB3_PORT_EMPTY;
+		config->usb3_ports[1] = (struct usb3_port_config) USB3_PORT_EMPTY;
+
+		printk(BIOS_INFO, "usb2_port5 to USB2_C2(DB).\n");
+		config->usb2_ports[4] = (struct usb2_port_config) USB2_PORT_TYPE_C(OC_SKIP);
+
+		printk(BIOS_INFO, "Enable tcss_usb3_port1 to USB3_C2(DB)\n");
+		config->tcss_ports[1] = (struct tcss_port_config) TCSS_PORT_DEFAULT(OC_SKIP);
+		printk(BIOS_INFO, "Disable tcss_usb3_port2\n");
+		config->tcss_ports[2] = (struct tcss_port_config) TCSS_PORT_EMPTY;
+		printk(BIOS_INFO, "Enable tcss_usb3_port3 to USB3_C1(MB)\n");
+		config->tcss_ports[3] = (struct tcss_port_config) TCSS_PORT_DEFAULT(OC_SKIP);
+	}
+}

From 8159b2e06cfd72ee24dedbbb7ec8f5befc485cb9 Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Fri, 5 Sep 2025 10:46:52 -0500
Subject: [PATCH 1991/3886] device/azalia_codec: Add header with enums for
 Realtek node IDs

Add enums for the output pin widget node IDs for Realtek ALC256 and
ALC269 codecs, to be used in HDA verb tables.

Sources:
ALC256-CG Datasheet Rev 1.1
ALC269-VB Datasheet Rev 0.14N
ALC269-VC Datasheet Rev 0.83

Change-Id: I1b60dd1ce2c1c790e22058d10234856f8b9b9416
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89075
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
---
 src/include/device/azalia_codec/realtek.h | 32 +++++++++++++++++++++++
 1 file changed, 32 insertions(+)
 create mode 100644 src/include/device/azalia_codec/realtek.h

diff --git a/src/include/device/azalia_codec/realtek.h b/src/include/device/azalia_codec/realtek.h
new file mode 100644
index 0000000000..12c9ed2d0a
--- /dev/null
+++ b/src/include/device/azalia_codec/realtek.h
@@ -0,0 +1,32 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef DEVICE_AZALIA_CODEC_REALTEK_H
+#define DEVICE_AZALIA_CODEC_REALTEK_H
+
+enum alc256_pin_widget {
+	ALC256_DMIC12		= 0x12,
+	ALC256_DMIC34		= 0x13,
+	ALC256_SPEAKERS		= 0x14,	// Port-D
+	ALC256_MIC2		= 0x19,	// Port-F
+	ALC256_LINE1		= 0x1a,	// Port-C
+	ALC256_LINE2		= 0x1b,	// Port-E
+	ALC256_PC_BEEP		= 0x1d,
+	ALC256_SPDIF_OUT	= 0x1e,
+	ALC256_HP_OUT		= 0x21,	// Port-I
+};
+
+enum alc269_pin_widget {
+	ALC269_DMIC12		= 0x12,
+	ALC269_SPEAKERS		= 0x14,	// Port-D
+	ALC269_VC_HP_OUT	= 0x15,	// Port-A, ALC269-VCx only
+	ALC269_MONO		= 0x17,	// Port-H
+	ALC269_MIC1		= 0x18,	// Port-B
+	ALC269_MIC2		= 0x19,	// Port-F
+	ALC269_LINE1		= 0x1a,	// Port-C
+	ALC269_LINE2		= 0x1b,	// Port-E
+	ALC269_PC_BEEP		= 0x1d,
+	ALC269_SPDIF_OUT	= 0x1e,
+	ALC269_VB_HP_OUT	= 0x21,	// Port-I, ALC269-VBx only
+};
+
+#endif /* DEVICE_AZALIA_CODEC_REALTEK_H */

From b849c9daa1ed7ba07f32574268d6b8d8e658f5df Mon Sep 17 00:00:00 2001
From: Subrata Banik <subratabanik@google.com>
Date: Thu, 11 Sep 2025 02:08:22 +0000
Subject: [PATCH 1992/3886] 3rdparty/qc_blobs: Update submodule to upstream
 main

Updating from commit id a252198:
2025-05-23 16:29:11 2023 +0530 - (sc7180/boot: Update qclib blobs binaries from 50 to 55)

to commit id 6379308:
2025-09-10 15:44:44 2025 +0000 - (qc_blobs: Add Qualcomm x1p42100 and Hamoa blobs)

This brings in 3 new commits:
6379308 qc_blobs: Add Qualcomm x1p42100 and Hamoa blobs
c9bf12e qc_blobs: Initial commit for x1p42100
0edd032 sc7180/qtiseclib: Update qtiseclib blobs and release notes from 69 to 71

Change-Id: Iff930f6dd2bb30be197358d078132babd4d6652e
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89141
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 3rdparty/qc_blobs | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/3rdparty/qc_blobs b/3rdparty/qc_blobs
index a252198ec6..6379308814 160000
--- a/3rdparty/qc_blobs
+++ b/3rdparty/qc_blobs
@@ -1 +1 @@
-Subproject commit a252198ec6544e13904cfe831cec3e784aaa715d
+Subproject commit 6379308814bd00a8b6e36a4715bdb86ba019a3a7

From 89a3ae3d801c0afb3eb97c19972a6451e4233ced Mon Sep 17 00:00:00 2001
From: erin liang <erin.liang@lcfc.corp-partner.google.com>
Date: Tue, 2 Sep 2025 14:18:44 +0800
Subject: [PATCH 1993/3886] mb/google/trulo/var/pujjolo: Update GPP_D15 setting

During the ACPI initialization phase at boot, the driver
is pulled, causing the LED of the WFC camera flash.
This issue can be resolved by replacing GPP_D15 with
GPP_D16 in the mipi settings.

BUG=b:434106137
TEST= Build and boot to OS, and check the Chromebook
logo will not flash

Change-Id: I2fce7f7c9c5c852efbdef3e5ef757cab3433f4c6
Signed-off-by: erin liang <erin.liang@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89014
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 .../google/brya/variants/pujjolo/overridetree.cb         | 9 +++------
 1 file changed, 3 insertions(+), 6 deletions(-)

diff --git a/src/mainboard/google/brya/variants/pujjolo/overridetree.cb b/src/mainboard/google/brya/variants/pujjolo/overridetree.cb
index 2b8d56cf10..423b79fa6e 100644
--- a/src/mainboard/google/brya/variants/pujjolo/overridetree.cb
+++ b/src/mainboard/google/brya/variants/pujjolo/overridetree.cb
@@ -439,18 +439,15 @@ chip soc/intel/alderlake
 				register "max_dstate_for_probe" = "ACPI_DEVICE_SLEEP_D3_COLD"
 
 				# Controls
-				register "gpio_panel.gpio[0].gpio_num" = "GPP_D15"  # EN_PP2800_WCAM_X
-				register "gpio_panel.gpio[1].gpio_num" = "GPP_D16"  # EN_PP1800_PP1200_WCAM_X
+				register "gpio_panel.gpio[0].gpio_num" = "GPP_D16"  # EN_PP2800_WCAM_X and EN_PP1800_PP1200_WCAM_X
 
 				# _ON
-				register "on_seq.ops_cnt" = "2"
+				register "on_seq.ops_cnt" = "1"
 				register "on_seq.ops[0]" = "SEQ_OPS_GPIO_ENABLE(0, 5)"
-				register "on_seq.ops[1]" = "SEQ_OPS_GPIO_ENABLE(1, 5)"
 
 				# _OFF
-				register "off_seq.ops_cnt" = "2"
+				register "off_seq.ops_cnt" = "1"
 				register "off_seq.ops[0]" = "SEQ_OPS_GPIO_DISABLE(1, 0)"
-				register "off_seq.ops[1]" = "SEQ_OPS_GPIO_DISABLE(0, 0)"
 
 				device i2c 0C on
 					probe WFC WFC_MIPI_OVTI8856

From 599d660c4b92e26d90905e5bacd8e46c0a72f4a5 Mon Sep 17 00:00:00 2001
From: Hualin Wei <weihualin@huaqin.corp-partner.google.com>
Date: Thu, 3 Jul 2025 15:49:20 +0800
Subject: [PATCH 1994/3886] mb/google/fatcat: Enable support for Realtek EC

Add support for Realtek EC on fatcat board.

BUG=b:438785495
TEST=emerge-fatcat coreboot

Change-Id: Id289e243640dbe86f989114bfc3a8d969cfbe1e0
Signed-off-by: Hualin Wei <weihualin@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88894
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Pranava Y N <pranavayn@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/google/fatcat/Kconfig     | 4 +++-
 src/mainboard/google/fatcat/bootblock.c | 8 ++++++++
 2 files changed, 11 insertions(+), 1 deletion(-)

diff --git a/src/mainboard/google/fatcat/Kconfig b/src/mainboard/google/fatcat/Kconfig
index 346d88d575..7b83976ba6 100644
--- a/src/mainboard/google/fatcat/Kconfig
+++ b/src/mainboard/google/fatcat/Kconfig
@@ -133,8 +133,10 @@ config BOARD_GOOGLE_KINMEN
 
 config BOARD_GOOGLE_LAPIS
 	select BOARD_GOOGLE_BASEBOARD_FATCAT
-	select FSP_UGOP_EARLY_SIGN_OF_LIFE
 	select DRIVERS_INTEL_TOUCH
+	select EC_GOOGLE_CHROMEEC_RTK
+	select EC_GOOGLE_CHROMEEC_LPC_GENERIC_MEMORY_RANGE
+	select FSP_UGOP_EARLY_SIGN_OF_LIFE
 	select HAVE_SLP_S0_GATE
 	select MAINBOARD_HAS_GOOGLE_STRAUSS_KEYBOARD
 
diff --git a/src/mainboard/google/fatcat/bootblock.c b/src/mainboard/google/fatcat/bootblock.c
index 6ee655ee58..e414937b83 100644
--- a/src/mainboard/google/fatcat/bootblock.c
+++ b/src/mainboard/google/fatcat/bootblock.c
@@ -2,6 +2,7 @@
 
 #include <baseboard/variants.h>
 #include <bootblock_common.h>
+#include <intelblocks/lpc_lib.h>
 
 void bootblock_mainboard_early_init(void)
 {
@@ -11,3 +12,10 @@ void bootblock_mainboard_early_init(void)
 	pads = variant_early_gpio_table(&num);
 	gpio_configure_pads(pads, num);
 }
+
+void bootblock_mainboard_init(void)
+{
+	if (CONFIG(EC_GOOGLE_CHROMEEC_LPC_GENERIC_MEMORY_RANGE))
+		lpc_open_mmio_window(CONFIG_EC_GOOGLE_CHROMEEC_LPC_GENERIC_MEMORY_BASE,
+			CONFIG_EC_GOOGLE_CHROMEEC_LPC_GENERIC_MEMORY_SIZE);
+}

From 241b940ac7e4cf465fe60980d65ee1a99eeee35f Mon Sep 17 00:00:00 2001
From: Rui Zhou <zhourui@huaqin.corp-partner.google.com>
Date: Wed, 10 Sep 2025 15:29:49 +0800
Subject: [PATCH 1995/3886] mb/google/nissa/var/rull: add RAM ID H58G56CK8BX146

Add RAM ID for DDR H58G56CK8BX146

BUG=b:442974182
BRANCH=None
TEST=boot to kernel success

Change-Id: I52252b1967898be949eddbf9e814853de3bcae9f
Signed-off-by: Rui Zhou <zhourui@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89130
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kun Liu <liukun11@huaqin.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
---
 src/mainboard/google/brya/variants/rull/memory/Makefile.mk      | 2 +-
 .../google/brya/variants/rull/memory/dram_id.generated.txt      | 1 +
 .../google/brya/variants/rull/memory/mem_parts_used.txt         | 1 +
 3 files changed, 3 insertions(+), 1 deletion(-)

diff --git a/src/mainboard/google/brya/variants/rull/memory/Makefile.mk b/src/mainboard/google/brya/variants/rull/memory/Makefile.mk
index 6796492e26..ae7be6dcd1 100644
--- a/src/mainboard/google/brya/variants/rull/memory/Makefile.mk
+++ b/src/mainboard/google/brya/variants/rull/memory/Makefile.mk
@@ -8,4 +8,4 @@ SPD_SOURCES += spd/lp5/set-0/spd-1.hex      # ID = 0(0b0000)  Parts = MT62F512M3
 SPD_SOURCES += spd/lp5/set-0/spd-7.hex      # ID = 1(0b0001)  Parts = K3KL8L80CM-MGCT, H58G56BK7BX068
 SPD_SOURCES += spd/lp5/set-0/spd-8.hex      # ID = 2(0b0010)  Parts = K3KL9L90CM-MGCT
 SPD_SOURCES += spd/lp5/set-0/spd-10.hex      # ID = 3(0b0011)  Parts = H58G66BK8BX067
-SPD_SOURCES += spd/lp5/set-0/spd-11.hex      # ID = 4(0b0100)  Parts = H58G56BK8BX068, MT62F1G32D2DS-023 WT:B
+SPD_SOURCES += spd/lp5/set-0/spd-11.hex      # ID = 4(0b0100)  Parts = H58G56BK8BX068, MT62F1G32D2DS-023 WT:B, H58G56CK8BX146
diff --git a/src/mainboard/google/brya/variants/rull/memory/dram_id.generated.txt b/src/mainboard/google/brya/variants/rull/memory/dram_id.generated.txt
index 8aedd8277f..6a8d4b9db2 100644
--- a/src/mainboard/google/brya/variants/rull/memory/dram_id.generated.txt
+++ b/src/mainboard/google/brya/variants/rull/memory/dram_id.generated.txt
@@ -12,3 +12,4 @@ K3KL9L90CM-MGCT                2 (0010)
 H58G66BK8BX067                 3 (0011)
 H58G56BK8BX068                 4 (0100)
 MT62F1G32D2DS-023 WT:B         4 (0100)
+H58G56CK8BX146                 4 (0100)
diff --git a/src/mainboard/google/brya/variants/rull/memory/mem_parts_used.txt b/src/mainboard/google/brya/variants/rull/memory/mem_parts_used.txt
index baaec96c62..4946ff0ab9 100644
--- a/src/mainboard/google/brya/variants/rull/memory/mem_parts_used.txt
+++ b/src/mainboard/google/brya/variants/rull/memory/mem_parts_used.txt
@@ -17,3 +17,4 @@ K3KL9L90CM-MGCT
 H58G66BK8BX067
 H58G56BK8BX068
 MT62F1G32D2DS-023 WT:B
+H58G56CK8BX146

From bdbe8b9b6ffebec53ec4a8c66fe344f9ffcf8499 Mon Sep 17 00:00:00 2001
From: Dmytro Aleksandrov <alkersan@gmail.com>
Date: Sun, 31 Aug 2025 18:05:20 -0400
Subject: [PATCH 1996/3886] util/kconfig: Fix xconfig

The QT based xconfig util is broken for several reasons.

1. On systems with qt6 (which is a majority on modern distros),
the qconf-cfg.sh script appends a c++17 flag to the output file,
which makes the value of $(HOSTCXXFLAGS_qconf.o) - a multiline string.
This causes problem during compiler invocation, thus we can observe:
  'g++: fatal error: no input files'
Flattening the HOSTCXXFLAGS_ with $strip function resolves the problem

2. The missing Qt's Meta-Object file "qconf-moc.cc",
which should be autogenerated during build by invoking "moc" tool.
The current set of recipes in Makefile.mk aren't triggering
the moc generation. Explicitly adding "qconf-moc.o" target,
with dependency on "qconf-moc.cc" resolves the problem.

3. "$(call if_changed,moc)" used to invoke "moc" tool isn't working,
due to missing "if_changed" macro.
Replace it with direct call to "cmd_moc" in "Makefile.real".
Bringing the full implementation of "if_changed" seem to be impractical,
as it uses too many dependent functions and macros.

BUG=https://ticket.coreboot.org/issues/518

Change-Id: I7eb1e71aeb6a92b8d3c194a369bd3bd6dc708863
Signed-off-by: Dmytro Aleksandrov <alkersan@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89006
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 util/kconfig/Makefile.mk | 9 +++++----
 1 file changed, 5 insertions(+), 4 deletions(-)

diff --git a/util/kconfig/Makefile.mk b/util/kconfig/Makefile.mk
index 83fad884b7..4fb8631167 100644
--- a/util/kconfig/Makefile.mk
+++ b/util/kconfig/Makefile.mk
@@ -20,6 +20,7 @@ $(objk)/Makefile.real: $(dir $(lastword $(MAKEFILE_LIST)))Makefile
 		-e "s,\$$(srctree)/arch/\$$(SRCARCH)/configs/\$$(KBUILD_DEFCONFIG),\$$(KBUILD_DEFCONFIG)," \
 		-e "s,--defconfig=arch/\$$(SRCARCH)/configs/\$$(KBUILD_DEFCONFIG),--defconfig=\$$(KBUILD_DEFCONFIG)," \
 		-e "/^unexport CONFIG_$$/d" \
+		-e "s/if_changed,moc/cmd_moc/g" \
 		$< > $@.tmp
 	mv $@.tmp $@
 
@@ -57,16 +58,16 @@ FORCE:
 filechk=$< > $@
 
 $(objk)/%.o: $(srck)/%.c
-	$(HOSTCC) -I $(srck) -I $(objk) -c $(HOSTCFLAGS_$(notdir $@)) -o $@ $<
+	$(HOSTCC) -I $(srck) -I $(objk) -c $(strip $(HOSTCFLAGS_$(notdir $@))) -o $@ $<
 
 $(objk)/%.o: $(srck)/%.cc
-	$(HOSTCXX) -I $(srck) -I $(objk) -c $(HOSTCXXFLAGS_$(notdir $@)) -o $@ $<
+	$(HOSTCXX) -I $(srck) -I $(objk) -c $(strip $(HOSTCXXFLAGS_$(notdir $@))) -o $@ $<
 
 $(objk)/%.o: $(objk)/%.c
 	$(HOSTCC) -I $(srck) -I $(objk) -c -o $@ $<
 
-$(objk)/%.moc: $(srck)/%.h | $(objk)/qconf-cfg
-	$(call cmd_moc)
+$(objk)/qconf-moc.o: $(objk)/qconf-moc.cc
+	$(HOSTCXX) -I $(srck) -I $(objk) -c $(strip $(HOSTCXXFLAGS_$(notdir $@))) -o $@ $<
 
 define hostprogs_template
 # $1 entry in hostprogs

From 1c0186f28064415b0d491d3f59a71118ac37909f Mon Sep 17 00:00:00 2001
From: Jeremy Compostella <jeremy.compostella@intel.com>
Date: Thu, 4 Sep 2025 12:13:25 -0700
Subject: [PATCH 1997/3886] soc/intel/common/block/cnvi: Add CNVi chip
 configuration support

This commit introduces a new configuration structure for the
Connectivity Integration (CNVi) block in Intel SoCs.

The added soc_intel_common_block_cnvi_config structure, located in
chip.h, defines a wake pin that specifies the ACPI Power Resources for
Wake (_PRW), enabling wake-up capabilities from sleep states.

This enhancement provides a structured way to handle CNVi
configurations, which is crucial for managing device power states and
ensuring proper wake functionalities as defined by ACPI standards.

Change-Id: Ide6dea04cb089d73fe6aad9fb91044f9eb43edc6
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89056
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
---
 src/soc/intel/common/block/cnvi/chip.h | 19 +++++++++++
 src/soc/intel/common/block/cnvi/cnvi.c | 44 ++++++++++++++++++++++++++
 2 files changed, 63 insertions(+)
 create mode 100644 src/soc/intel/common/block/cnvi/chip.h

diff --git a/src/soc/intel/common/block/cnvi/chip.h b/src/soc/intel/common/block/cnvi/chip.h
new file mode 100644
index 0000000000..7f50ffb946
--- /dev/null
+++ b/src/soc/intel/common/block/cnvi/chip.h
@@ -0,0 +1,19 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef _SOC_INTEL_COMMON_BLOCK_CNVI_H_
+#define _SOC_INTEL_COMMON_BLOCK_CNVI_H_
+
+/**
+ * struct soc_intel_common_block_cnvi_config - Configuration structure for CNVi
+ * @wake: Specifies the wake pin used for ACPI Power Resources for Wake (_PRW).
+ *
+ * This structure holds the configuration data required for setting up the
+ * Connectivity Integration (CNVi) block in Intel SoCs. The wake pin is
+ * utilized to enable wake-up capabilities from sleep states as defined
+ * by the ACPI specification.
+ */
+struct soc_intel_common_block_cnvi_config {
+	unsigned int wake;
+};
+
+#endif /* SOC_INTEL_COMMON_BLOCK_CNVI_H_ */
diff --git a/src/soc/intel/common/block/cnvi/cnvi.c b/src/soc/intel/common/block/cnvi/cnvi.c
index 6ca91b1190..9314c989ed 100644
--- a/src/soc/intel/common/block/cnvi/cnvi.c
+++ b/src/soc/intel/common/block/cnvi/cnvi.c
@@ -10,6 +10,8 @@
 #include <soc/cnvi.h>
 #include <soc/pcr_ids.h>
 
+#include "chip.h"
+
 static const char *cnvi_wifi_acpi_name(const struct device *dev)
 {
 	return "CNVW";
@@ -871,3 +873,45 @@ static const struct pci_driver pch_cnvi_bt __pci_driver = {
 	.vendor			= PCI_VID_INTEL,
 	.devices		= bt_pci_device_ids,
 };
+
+static const char *cnvi_acpi_name(const struct device *dev)
+{
+	const struct device *parent = dev->upstream->dev;
+	return parent->ops->acpi_name(parent);
+}
+
+static void cnvi_acpi_fill_ssdt(const struct device *dev)
+{
+	const struct device *parent = dev->upstream->dev;
+	const char *scope = acpi_device_path(parent);
+	acpigen_write_scope(scope);
+
+	const struct soc_intel_common_block_cnvi_config *config = dev->chip_info;
+	if (config) {
+/*		Name (_PRW, Package (0x02)  // _PRW: Power Resources for Wake
+ *		{
+ *		    $(config->wake),
+ *		    0x03
+ *		})
+ */
+		acpigen_write_PRW(config->wake, ACPI_S3);
+	}
+	acpigen_write_scope_end();
+}
+
+static struct device_operations cnvi_ops = {
+	.read_resources = noop_read_resources,
+	.set_resources = noop_set_resources,
+	.acpi_fill_ssdt = cnvi_acpi_fill_ssdt,
+	.acpi_name = cnvi_acpi_name,
+};
+
+static void cnvi_enable_dev(struct device *dev)
+{
+	dev->ops = &cnvi_ops;
+}
+
+struct chip_operations soc_intel_common_block_cnvi_ops = {
+	.name = "CNVi Device",
+	.enable_dev = cnvi_enable_dev,
+};

From a262cdbc27face9ecc8b551cd0a4f7ad89f7966e Mon Sep 17 00:00:00 2001
From: Jeremy Compostella <jeremy.compostella@intel.com>
Date: Thu, 4 Sep 2025 17:47:53 -0700
Subject: [PATCH 1998/3886] mb/intel/ptlrvp: Add wake configuration to
 cnvi_bluetooth

This commit adds a wake configuration to the cnvi_bluetooth device for
all the ptlrvp board variants. The "wake" setting is now registered to
"GPE0_PME_B0" using the common CNVi block. This enhancement ensures that
the cnvi_bluetooth device can properly wake the system.

TEST=Able to wake up the device from a low power state using a keyboard
     Bluetooth device.

Change-Id: I4c17ca926a4409cedfaef24a802330ef463703ac
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89061
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jamie Ryu <jamie.m.ryu@intel.com>
Reviewed-by: Cliff Huang <cliff.huang@intel.com>
---
 src/mainboard/intel/ptlrvp/variants/ptlrvp/overridetree.cb    | 4 ++++
 .../intel/ptlrvp/variants/ptlrvp_chromeec/overridetree.cb     | 4 ++++
 2 files changed, 8 insertions(+)

diff --git a/src/mainboard/intel/ptlrvp/variants/ptlrvp/overridetree.cb b/src/mainboard/intel/ptlrvp/variants/ptlrvp/overridetree.cb
index 6a945727aa..1f8611979f 100644
--- a/src/mainboard/intel/ptlrvp/variants/ptlrvp/overridetree.cb
+++ b/src/mainboard/intel/ptlrvp/variants/ptlrvp/overridetree.cb
@@ -629,6 +629,10 @@ chip soc/intel/pantherlake
 		device ref cnvi_bluetooth on
 			probe WIFI WIFI_CNVI_6
 			probe WIFI WIFI_CNVI_7
+			chip soc/intel/common/block/cnvi
+				register "wake" = "GPE0_PME_B0"
+				device generic 0 on end
+			end
 		end
 
 		# NOTE: i2c0 is function 0; hence it needs to be enabled when any of i2c1-5 is enabled.
diff --git a/src/mainboard/intel/ptlrvp/variants/ptlrvp_chromeec/overridetree.cb b/src/mainboard/intel/ptlrvp/variants/ptlrvp_chromeec/overridetree.cb
index 52af027cad..4d8ae44266 100644
--- a/src/mainboard/intel/ptlrvp/variants/ptlrvp_chromeec/overridetree.cb
+++ b/src/mainboard/intel/ptlrvp/variants/ptlrvp_chromeec/overridetree.cb
@@ -629,6 +629,10 @@ chip soc/intel/pantherlake
 		device ref cnvi_bluetooth on
 			probe WIFI WIFI_CNVI_6
 			probe WIFI WIFI_CNVI_7
+			chip soc/intel/common/block/cnvi
+				register "wake" = "GPE0_PME_B0"
+				device generic 0 on end
+			end
 		end
 
 		# NOTE: i2c0 is function 0; hence it needs to be enabled when any of i2c1-5 is enabled.

From f373faa9c8bc718300b6a15b89c7f7ba2a280fca Mon Sep 17 00:00:00 2001
From: John Su <john_su@compal.corp-partner.google.com>
Date: Thu, 21 Aug 2025 16:43:13 +0800
Subject: [PATCH 1999/3886] mb/google/trulo/var/uldrenite: Add fw_config probe
 for storage

Add FW Config probe for uldrenite14 storage.

BUG=b:437006063
TEST=emerge-nissa coreboot

Change-Id: I744a4e32702175f9c42c884bc76c69a968e74678
Signed-off-by: John Su <john_su@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88877
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
---
 .../brya/variants/uldrenite/overridetree.cb   | 15 ++++++++-
 .../google/brya/variants/uldrenite/variant.c  | 32 +++++++++++++++++++
 2 files changed, 46 insertions(+), 1 deletion(-)

diff --git a/src/mainboard/google/brya/variants/uldrenite/overridetree.cb b/src/mainboard/google/brya/variants/uldrenite/overridetree.cb
index 6dc7d4218f..8b9f69ab10 100644
--- a/src/mainboard/google/brya/variants/uldrenite/overridetree.cb
+++ b/src/mainboard/google/brya/variants/uldrenite/overridetree.cb
@@ -19,6 +19,12 @@ fw_config
 		option ISH_DISABLE		0
 		option ISH_ENABLE		1
 	end
+	field STORAGE 30 31
+		option STORAGE_EMMC		0
+		option STORAGE_NVME		1
+		option STORAGE_UFS		2
+		option STORAGE_UNKNOWN		3
+	end
 end
 
 chip soc/intel/alderlake
@@ -500,7 +506,14 @@ chip soc/intel/alderlake
 		device ref shared_sram on end
 		device ref heci1 on end
 		device ref pmc hidden end
-		device ref emmc on end
+		device ref emmc on
+			probe STORAGE STORAGE_EMMC
+			probe STORAGE STORAGE_UNKNOWN
+		end
+		device ref ufs on
+			probe STORAGE STORAGE_UFS
+			probe STORAGE STORAGE_UNKNOWN
+		end
 		device ref uart0 on end
 		device ref pch_espi on
 			chip ec/google/chromeec
diff --git a/src/mainboard/google/brya/variants/uldrenite/variant.c b/src/mainboard/google/brya/variants/uldrenite/variant.c
index a7927eb0d3..0cc6b3972f 100644
--- a/src/mainboard/google/brya/variants/uldrenite/variant.c
+++ b/src/mainboard/google/brya/variants/uldrenite/variant.c
@@ -86,6 +86,33 @@ static const struct pad_config ish_uart1_disable_pads[] = {
 	PAD_NC_LOCK(GPP_E9, NONE, LOCK_CONFIG),
 };
 
+static const struct pad_config emmc_disable_pads[] = {
+	/* I7  : EMMC_CMD */
+	PAD_NC(GPP_I7, NONE),
+	/* I8  : EMMC_D0 */
+	PAD_NC(GPP_I8, NONE),
+	/* I9  : EMMC_D1 */
+	PAD_NC(GPP_I9, NONE),
+	/* I10 : EMMC_D2 */
+	PAD_NC(GPP_I10, NONE),
+	/* I11 : EMMC_D3 */
+	PAD_NC(GPP_I11, NONE),
+	/* I12 : EMMC_D4 */
+	PAD_NC(GPP_I12, NONE),
+	/* I13 : EMMC_D5 */
+	PAD_NC(GPP_I13, NONE),
+	/* I14 : EMMC_D6 */
+	PAD_NC(GPP_I14, NONE),
+	/* I15 : EMMC_D7 */
+	PAD_NC(GPP_I15, NONE),
+	/* I16 : EMMC_RCLK */
+	PAD_NC(GPP_I16, NONE),
+	/* I17 : EMMC_CLK */
+	PAD_NC(GPP_I17, NONE),
+	/* I18 : EMMC_RST_L */
+	PAD_NC(GPP_I18, NONE),
+};
+
 void fw_config_gpio_padbased_override(struct pad_config *padbased_table)
 {
 	uint32_t board_version = board_id();
@@ -100,6 +127,11 @@ void fw_config_gpio_padbased_override(struct pad_config *padbased_table)
 		gpio_padbased_override(padbased_table, lte_disable_pads,
 				ARRAY_SIZE(lte_disable_pads));
 	}
+	if (fw_config_probe(FW_CONFIG(STORAGE, STORAGE_UFS))) {
+		printk(BIOS_INFO, "Disable eMMC GPIO pins.\n");
+		gpio_padbased_override(padbased_table, emmc_disable_pads,
+				ARRAY_SIZE(emmc_disable_pads));
+	}
 
 	/* b/415605630: Support different ISH UART mappings according the board id */
 	if (board_version < 2) {

From 7f74155aa42af41399df83d1005ff7599c0da5ae Mon Sep 17 00:00:00 2001
From: John Su <john_su@compal.corp-partner.google.com>
Date: Mon, 25 Aug 2025 15:20:06 +0800
Subject: [PATCH 2000/3886] mb/google/trulo/var/uldrenite: Select
 USE_UNIFIED_AP_FIRMWARE_FOR_UFS_AND_NON_UFS

Uldrenite14 need to set this config since we use unified firmware
for UFS and eMMC skus.

BUG=b:437006063
TEST=emerge-nissa coreboot

Change-Id: I86f41a4e6c9c136f031eb3813efa3c06043237b9
Signed-off-by: John Su <john_su@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88932
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/google/brya/Kconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/src/mainboard/google/brya/Kconfig b/src/mainboard/google/brya/Kconfig
index a581bd36db..f9ee23d8c2 100644
--- a/src/mainboard/google/brya/Kconfig
+++ b/src/mainboard/google/brya/Kconfig
@@ -720,6 +720,7 @@ config BOARD_GOOGLE_ULDRENITE
 	select MAINBOARD_HAS_GOOGLE_STRAUSS_KEYBOARD
 	select SOC_INTEL_COMMON_BLOCK_HDA_VERB
 	select SOC_INTEL_TCSS_USE_PDC_PMC_USBC_MUX_CONFIGURATION
+	select USE_UNIFIED_AP_FIRMWARE_FOR_UFS_AND_NON_UFS
 
 config BOARD_GOOGLE_VELL
 	select BOARD_GOOGLE_BASEBOARD_BRYA

From 17c623277b271bd4c38996c44c308bb43f252588 Mon Sep 17 00:00:00 2001
From: Luca Lai <luca.lai@lcfc.corp-partner.google.com>
Date: Wed, 10 Sep 2025 13:37:33 +0800
Subject: [PATCH 2001/3886] mb/google/trulo/var/pujjolo: Change stylus settings

Change stylus gpio and wake source setting to let eventlog could
show GPE #12 message when interrupt suspend by stylus.

BUG=b:439761057
TEST=Build and boot to OS, do the suspend_stress_test and check
eventlog show wake source information. And do warmboot/coldboot/
suspend 500 times stress test all pass.

Change-Id: I8d16e867fd56f1072b09bb6ab71b6d08a7d38376
Signed-off-by: Luca Lai <luca.lai@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89129
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/google/brya/variants/pujjolo/gpio.c          | 2 +-
 src/mainboard/google/brya/variants/pujjolo/overridetree.cb | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/mainboard/google/brya/variants/pujjolo/gpio.c b/src/mainboard/google/brya/variants/pujjolo/gpio.c
index efab7a15b6..427a1701b9 100644
--- a/src/mainboard/google/brya/variants/pujjolo/gpio.c
+++ b/src/mainboard/google/brya/variants/pujjolo/gpio.c
@@ -27,7 +27,7 @@ static const struct pad_config override_gpio_table[] = {
 	/* A11 : EN_SPK_PA ==> NC */
 	PAD_NC(GPP_A11, NONE),
 	/* A12 : SOC_PEN_DETECT_ODL */
-	PAD_CFG_GPI_SCI_HIGH(GPP_A12, NONE, PLTRST, EDGE_BOTH),
+	PAD_CFG_GPI_SCI_HIGH(GPP_A12, NONE, PLTRST, EDGE_SINGLE),
 	/* A13 : GPP_A13 ==> GSC_SOC_INT_ODL */
 	PAD_CFG_GPI_APIC(GPP_A13, NONE, PLTRST, LEVEL, INVERT),
 	/* A14 : USB_OC1# ==> NC */
diff --git a/src/mainboard/google/brya/variants/pujjolo/overridetree.cb b/src/mainboard/google/brya/variants/pujjolo/overridetree.cb
index 423b79fa6e..3b8bd5f0ce 100644
--- a/src/mainboard/google/brya/variants/pujjolo/overridetree.cb
+++ b/src/mainboard/google/brya/variants/pujjolo/overridetree.cb
@@ -303,7 +303,7 @@ chip soc/intel/alderlake
 			chip drivers/generic/gpio_keys
 				register "name" = ""PENH""
 				register "gpio" = "ACPI_GPIO_INPUT_ACTIVE_LOW(GPP_E0)"
-				register "key.wake_gpe" = "GPE0_DW2_15"
+				register "key.wake_gpe" = "GPE0_DW0_12"
 				register "key.wakeup_route" = "WAKEUP_ROUTE_SCI"
 				register "key.wakeup_event_action" = "EV_ACT_DEASSERTED"
 				register "key.dev_name" = ""EJCT""

From b69e66721de9f17f15b580cb7a13fbfacd7e1af4 Mon Sep 17 00:00:00 2001
From: Derek Huang <derekhuang@google.com>
Date: Tue, 9 Sep 2025 10:00:18 +0000
Subject: [PATCH 2002/3886] mb/google/brya: Update GPIO_PCH_WP configuration in
 trulo baseboard

Change GPIO_PCH_WP from GPP_E3 to GPP_E12 to align with trulo
reference hardware schematic.

BUG=b:443677716, b:435612546
TEST=Build pujjolo and kaladin firmware and verify SPI ROM
     write-protect

Change-Id: I935d74cb5447f45f297fe45506c14623095d7127
Signed-off-by: Derek Huang <derekhuang@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89117
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 .../brya/variants/baseboard/trulo/include/baseboard/gpio.h      | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/mainboard/google/brya/variants/baseboard/trulo/include/baseboard/gpio.h b/src/mainboard/google/brya/variants/baseboard/trulo/include/baseboard/gpio.h
index 6bfcc8169a..387784ff15 100644
--- a/src/mainboard/google/brya/variants/baseboard/trulo/include/baseboard/gpio.h
+++ b/src/mainboard/google/brya/variants/baseboard/trulo/include/baseboard/gpio.h
@@ -11,7 +11,7 @@
 /* EC wake is EC_SOC_WAKE_ODL which is routed to GPP_F17 */
 #define GPE_EC_WAKE		GPE0_DW2_17
 /* WP signal to PCH */
-#define GPIO_PCH_WP		GPP_E3
+#define GPIO_PCH_WP		GPP_E12
 /* EC in RW or RO */
 #define GPIO_EC_IN_RW		GPP_F18
 /* GPIO IRQ for tight timestamps, MKBP interrupts */

From 76e0f640353a63b859770aebfdc7b2cbf3870662 Mon Sep 17 00:00:00 2001
From: Derek Huang <derekhuang@google.com>
Date: Tue, 9 Sep 2025 10:16:10 +0000
Subject: [PATCH 2003/3886] mb/google/brya: Update GPIO_PCH_WP for trulo
 variants

Update GPIO_PCH_WP configuration for trulo varaints as the value
in the baseboard is changed.

BUG=b:443677716, b:435612546
TEST=Build uldrenite, pujjocento and orisa firmware successfully

Change-Id: I7fb35091000b1df1b8008f26488e9290be3efe2d
Signed-off-by: Derek Huang <derekhuang@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89118
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
---
 .../google/brya/variants/orisa/include/variant/gpio.h         | 3 +++
 .../google/brya/variants/pujjocento/include/variant/gpio.h    | 3 ---
 .../google/brya/variants/uldrenite/include/variant/gpio.h     | 4 ++++
 3 files changed, 7 insertions(+), 3 deletions(-)

diff --git a/src/mainboard/google/brya/variants/orisa/include/variant/gpio.h b/src/mainboard/google/brya/variants/orisa/include/variant/gpio.h
index c4fe342621..fc0624a22d 100644
--- a/src/mainboard/google/brya/variants/orisa/include/variant/gpio.h
+++ b/src/mainboard/google/brya/variants/orisa/include/variant/gpio.h
@@ -4,5 +4,8 @@
 #define VARIANT_GPIO_H
 
 #include <baseboard/gpio.h>
+#undef GPIO_PCH_WP
+/* WP signal to PCH */
+#define GPIO_PCH_WP GPP_E3
 
 #endif
diff --git a/src/mainboard/google/brya/variants/pujjocento/include/variant/gpio.h b/src/mainboard/google/brya/variants/pujjocento/include/variant/gpio.h
index 351bb879c3..66cfef0274 100644
--- a/src/mainboard/google/brya/variants/pujjocento/include/variant/gpio.h
+++ b/src/mainboard/google/brya/variants/pujjocento/include/variant/gpio.h
@@ -4,9 +4,6 @@
 #define VARIANT_GPIO_H
 
 #include <baseboard/gpio.h>
-#undef GPIO_PCH_WP
-/* WP signal to PCH */
-#define GPIO_PCH_WP		GPP_E12
 
 #define WWAN_FCPO	GPP_D6 /* FULL_CARD_POWER_OFF# */
 #define WWAN_RST	GPP_E17
diff --git a/src/mainboard/google/brya/variants/uldrenite/include/variant/gpio.h b/src/mainboard/google/brya/variants/uldrenite/include/variant/gpio.h
index e7524565d0..8baa5466ff 100644
--- a/src/mainboard/google/brya/variants/uldrenite/include/variant/gpio.h
+++ b/src/mainboard/google/brya/variants/uldrenite/include/variant/gpio.h
@@ -5,6 +5,10 @@
 
 #include <baseboard/gpio.h>
 
+#undef GPIO_PCH_WP
+/* WP signal to PCH */
+#define GPIO_PCH_WP	GPP_E3
+
 #define WWAN_FCPO	GPP_H23
 #define WWAN_RST	GPP_F12
 #define WWAN_PERST	GPP_F13

From 6074ca18d3101c13963c4caf2da317f901f2d982 Mon Sep 17 00:00:00 2001
From: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Date: Mon, 8 Sep 2025 10:10:10 +0800
Subject: [PATCH 2004/3886] mb/google/ocelot: Create matsu variant

Create the matsu variant of the ocelot reference board by copying
the ocelot files to a new directory named for the variant.

BUG=b:443612246
TEST=1. util/abuild/abuild -p none -t google/ocelot -x -a
        make sure the build includes GOOGLE_MATSU
     2. Run part_id_gen tool without any errors

Change-Id: I81d010fdda927db56d7b41ddc527c1c40b2cf768
Signed-off-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89099
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Pranava Y N <pranavayn@google.com>
---
 src/mainboard/google/ocelot/Kconfig           |  13 +
 src/mainboard/google/ocelot/Kconfig.name      |   3 +
 .../baseboard/ocelot/include/baseboard/gpio.h |   2 +
 .../google/ocelot/variants/matsu/Makefile.mk  |   6 +
 .../google/ocelot/variants/matsu/gpio.c       | 391 ++++++++++++++++++
 .../google/ocelot/variants/matsu/hda_verb.c   | 126 ++++++
 .../variants/matsu/include/variant/ec.h       |   8 +
 .../variants/matsu/include/variant/gpio.h     |  11 +
 .../google/ocelot/variants/matsu/memory.c     |  69 ++++
 .../ocelot/variants/matsu/memory/Makefile.mk  |   7 +
 .../matsu/memory/dram_id.generated.txt        |   7 +
 .../variants/matsu/memory/mem_parts_used.txt  |  12 +
 .../ocelot/variants/matsu/overridetree.cb     |   5 +
 13 files changed, 660 insertions(+)
 create mode 100644 src/mainboard/google/ocelot/variants/matsu/Makefile.mk
 create mode 100644 src/mainboard/google/ocelot/variants/matsu/gpio.c
 create mode 100644 src/mainboard/google/ocelot/variants/matsu/hda_verb.c
 create mode 100644 src/mainboard/google/ocelot/variants/matsu/include/variant/ec.h
 create mode 100644 src/mainboard/google/ocelot/variants/matsu/include/variant/gpio.h
 create mode 100644 src/mainboard/google/ocelot/variants/matsu/memory.c
 create mode 100644 src/mainboard/google/ocelot/variants/matsu/memory/Makefile.mk
 create mode 100644 src/mainboard/google/ocelot/variants/matsu/memory/dram_id.generated.txt
 create mode 100644 src/mainboard/google/ocelot/variants/matsu/memory/mem_parts_used.txt
 create mode 100644 src/mainboard/google/ocelot/variants/matsu/overridetree.cb

diff --git a/src/mainboard/google/ocelot/Kconfig b/src/mainboard/google/ocelot/Kconfig
index 131948e44a..9f26a2d8f3 100644
--- a/src/mainboard/google/ocelot/Kconfig
+++ b/src/mainboard/google/ocelot/Kconfig
@@ -56,6 +56,12 @@ config BOARD_GOOGLE_BASEBOARD_OCELOT
 	select SYSTEM_TYPE_LAPTOP
 	select TPM_GOOGLE_TI50
 
+config BOARD_GOOGLE_MODEL_MATSU
+	def_bool n
+	select BOARD_GOOGLE_BASEBOARD_OCELOT
+	select FSP_UGOP_EARLY_SIGN_OF_LIFE
+	select MAINBOARD_HAS_GOOGLE_STRAUSS_KEYBOARD
+
 config BOARD_GOOGLE_MODEL_OCELOT
 	def_bool n
 	select BOARD_GOOGLE_BASEBOARD_OCELOT
@@ -74,6 +80,9 @@ config BOARD_GOOGLE_MODEL_OJAL
 	select EC_GOOGLE_CHROMEEC_RTK
 	select EC_GOOGLE_CHROMEEC_LPC_GENERIC_MEMORY_RANGE
 
+config BOARD_GOOGLE_MATSU
+	select BOARD_GOOGLE_MODEL_MATSU
+
 config BOARD_GOOGLE_OCELOT
 	select BOARD_GOOGLE_MODEL_OCELOT
 
@@ -130,6 +139,7 @@ config DRIVER_TPM_I2C_ADDR
 
 config DRIVER_TPM_I2C_BUS
 	hex
+	default 0x01 if BOARD_GOOGLE_MODEL_MATSU
 	default 0x01 if BOARD_GOOGLE_MODEL_OCELOT
 	default 0x01 if BOARD_GOOGLE_MODEL_OJAL
 
@@ -144,6 +154,7 @@ config MAINBOARD_FAMILY
 	default "Google_Ocelot"
 
 config MAINBOARD_PART_NUMBER
+	default "Matsu" if BOARD_GOOGLE_MODEL_MATSU
 	default "Ocelot" if BOARD_GOOGLE_MODEL_OCELOT
 	default "Ojal" if BOARD_GOOGLE_OJAL
 
@@ -154,6 +165,7 @@ config MEMORY_SOLDERDOWN
 
 config TPM_TIS_ACPI_INTERRUPT
 	int
+	default 78 if BOARD_GOOGLE_MODEL_MATSU # GPE0_DW2_14 (GPP_E14)
 	default 49 if BOARD_GOOGLE_MODEL_OCELOT # GPE0_DW1_17 (GPP_B17)
 	default 49 if BOARD_GOOGLE_MODEL_OJAL # GPE0_DW1_17 (GPP_B17)
 
@@ -166,6 +178,7 @@ config USE_PM_ACPI_TIMER
 
 config VARIANT_DIR
 	string
+	default "matsu" if BOARD_GOOGLE_MODEL_MATSU
 	default "ocelot" if BOARD_GOOGLE_MODEL_OCELOT
 	default "ojal" if BOARD_GOOGLE_MODEL_OJAL
 
diff --git a/src/mainboard/google/ocelot/Kconfig.name b/src/mainboard/google/ocelot/Kconfig.name
index 2645d9c7f0..6f6f45fb6e 100644
--- a/src/mainboard/google/ocelot/Kconfig.name
+++ b/src/mainboard/google/ocelot/Kconfig.name
@@ -2,6 +2,9 @@
 
 comment "Ocelot"
 
+config BOARD_GOOGLE_MATSU
+	bool "-> Matsu"
+
 config BOARD_GOOGLE_OCELOT
 	bool "-> Ocelot"
 
diff --git a/src/mainboard/google/ocelot/variants/baseboard/ocelot/include/baseboard/gpio.h b/src/mainboard/google/ocelot/variants/baseboard/ocelot/include/baseboard/gpio.h
index e72f1ba74d..48dbafc8d3 100644
--- a/src/mainboard/google/ocelot/variants/baseboard/ocelot/include/baseboard/gpio.h
+++ b/src/mainboard/google/ocelot/variants/baseboard/ocelot/include/baseboard/gpio.h
@@ -15,6 +15,8 @@
 //TODO for Nuvo: #define EC_SYNC_IRQ	GPP_E07_IRQ
 #if CONFIG(BOARD_GOOGLE_MODEL_OCELOT) || CONFIG(BOARD_GOOGLE_MODEL_OJAL)
  #define EC_SYNC_IRQ	0 /* Not Connected */
+#elif CONFIG(BOARD_GOOGLE_MODEL_MATSU)
+ #define EC_SYNC_IRQ	GPP_E08_IRQ
 #endif
 #define GPIO_PCH_WP	GPP_D02
 #define GPIO_SLP_S0_GATE	GPP_C08
diff --git a/src/mainboard/google/ocelot/variants/matsu/Makefile.mk b/src/mainboard/google/ocelot/variants/matsu/Makefile.mk
new file mode 100644
index 0000000000..4c33dad4db
--- /dev/null
+++ b/src/mainboard/google/ocelot/variants/matsu/Makefile.mk
@@ -0,0 +1,6 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
+bootblock-y += gpio.c
+romstage-y += gpio.c
+romstage-y += memory.c
+ramstage-y += gpio.c
diff --git a/src/mainboard/google/ocelot/variants/matsu/gpio.c b/src/mainboard/google/ocelot/variants/matsu/gpio.c
new file mode 100644
index 0000000000..41c21a1b39
--- /dev/null
+++ b/src/mainboard/google/ocelot/variants/matsu/gpio.c
@@ -0,0 +1,391 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <baseboard/gpio.h>
+#include <baseboard/variants.h>
+#include <boardid.h>
+#include <soc/gpio.h>
+
+/* Pad configuration in ramstage*/
+static const struct pad_config gpio_table[] = {
+	/* GPP_A */
+	/* GPP_A00:     ESPI_IO0_AIC */
+	/*  GPP_A00 : GPP_A00 ==> ESPI_IO0_EC_R configured on reset, do not touch */
+
+	/* GPP_A01:     ESPI_IO1_AIC */
+	/*  GPP_A01 : GPP_A01 ==> ESPI_IO1_EC_R configured on reset, do not touch */
+
+	/* GPP_A02:     ESPI_IO2_AIC */
+	/*  GPP_A02 : GPP_A02 ==> ESPI_IO2_EC_R configured on reset, do not touch */
+
+	/* GPP_A03:     ESPI_IO3_AIC */
+	/*  GPP_A03 : GPP_A03 ==> ESPI_IO3_EC_R configured on reset, do not touch */
+
+	/* GPP_A04:     ESPI_CS0_AIC_N */
+	/*  GPP_A04 : GPP_A04 ==> ESPI_CS0_HDR_L configured on reset, do not touch */
+
+	/* GPP_A05:     ESPI_CLK_AIC */
+	/*  GPP_A05 : GPP_A05 ==> ESPI_CLK_HDR configured on reset, do not touch */
+
+	/* GPP_A06:     ESPI_RST_AIC_N */
+	/*  GPP_A06 : GPP_A06 ==> ESPI_RST_HDR configured on reset, do not touch */
+
+	/* GPP_A08:     M2_GEN4_SSD_RESET_N */
+	PAD_CFG_GPO(GPP_A08, 1, PLTRST),
+	/* GPP_A09:     M.2_WWAN_FCP_OFF_N */
+	PAD_CFG_GPO(GPP_A09, 1, PLTRST),
+	/* GPP_A10:     WWAN_DISABLE_N */
+	PAD_CFG_GPO(GPP_A10, 1, PLTRST),
+	/* GPP_A11:     WLAN_RST_N */
+	PAD_CFG_GPO(GPP_A11, 1, PLTRST),
+	/* GPP_A12:     WIFI_WAKE_N */
+	PAD_CFG_GPI_SCI_LOW(GPP_A12, NONE, DEEP, LEVEL),
+	/* GPP_A13:     PCIE_LNK_DOWN */
+	PAD_CFG_NF_OWNERSHIP(GPP_A13, NONE, DEEP, NF2, ACPI),
+	/* GPP_A15:     CODEC_GPIO_EN */
+	PAD_CFG_GPO(GPP_A15, 1, DEEP),
+
+	/* GPP_B */
+	/* GPP_B00:     USBC_SML_CLK_PD */
+	PAD_CFG_NF(GPP_B00, NONE, DEEP, NF1),
+	/* GPP_B01:     USBC_SML_DATA_PD */
+	PAD_CFG_NF(GPP_B01, NONE, DEEP, NF1),
+	/* GPP_B02:     ISH_I2C0_SDA_SNSR_HDR */
+	PAD_NC(GPP_B02, NONE),
+	/* GPP_B03:     ISH_I2C0_SCL_SNSR_HDR */
+	PAD_NC(GPP_B03, NONE),
+	/* GPP_B04:     ISH_GP_0_SNSR_HDR */
+	PAD_NC(GPP_B04, NONE),
+	/* GPP_B06:     SOC_PDB_CTRL */
+	PAD_CFG_GPO(GPP_B06, 0, DEEP),
+	/* GPP_B08:     ISH_GP_4_SNSR_HDR */
+	PAD_NC(GPP_B08, NONE),
+	/* GPP_B09:     BT_RF_KILL_N */
+	PAD_CFG_GPO(GPP_B09, 1, DEEP),
+	/* GPP_B10:     NC */
+	PAD_NC(GPP_B10, NONE),
+	/* GPP_B12:     PM_SLP_S0_N */
+	PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1),
+	/* GPP_B13:     PLT_RST_N */
+	PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1),
+	/* GPP_B14:     GPP_B14_DDSP_HPDB */
+	PAD_CFG_NF(GPP_B14, NONE, DEEP, NF2),
+	/* GPP_B16:     COINLESS_MODE_SELECT */
+	PAD_CFG_GPI(GPP_B16, NONE, DEEP),
+	/* GPP_B17:     SPI_TPM_INT_N */
+	PAD_CFG_GPI_APIC_LOCK(GPP_B17, NONE, LEVEL, INVERT, LOCK_CONFIG),
+	/* GPP_B20:     WWAN_RST_N */
+	PAD_CFG_GPO(GPP_B20, 1, PLTRST),
+	/* GPP_B21:     TCP_RETIMER_FORCE_PWR */
+	PAD_CFG_GPO(GPP_B21, 0, DEEP),
+	/* GPP_B24:     ESPI_ALERT0_EC_R_N */
+	PAD_NC(GPP_B24, NONE),
+	/* GPP_B25:     None */
+	PAD_NC(GPP_B25, NONE),
+
+	/* GPP_C */
+	/* GPP_C00:     SPD_SMB_CLK */
+	PAD_CFG_NF(GPP_C00, NONE, DEEP, NF1),
+	/* GPP_C01:     SPD_SMB_DATA */
+	PAD_CFG_NF(GPP_C01, NONE, DEEP, NF1),
+	/* GPP_C02:     NC */
+	PAD_NC(GPP_C02, NONE),
+	/* GPP_C03:     TCP_LAN_SML0_SCL_R */
+	PAD_CFG_NF(GPP_C03, NONE, DEEP, NF1),
+	/* GPP_C04:     TCP_LAN_SML0_SDA_R */
+	PAD_CFG_NF(GPP_C04, NONE, DEEP, NF1),
+	/* GPP_C05:     NC */
+	PAD_NC(GPP_C05, NONE),
+	/* GPP_C06:     NC */
+	PAD_NC(GPP_C06, NONE),
+	/* GPP_C07:     NC */
+	PAD_NC(GPP_C07, NONE),
+	/* GPP_C08:     PM_SLP_S0_N_GPP_CNTRL */
+	PAD_CFG_GPO(GPP_C08, 1, PLTRST),
+	/* GPP_C09:     CLKREQ0_X1_GEN4_M2_WLAN_N */
+	PAD_CFG_NF(GPP_C09, NONE, DEEP, NF1),
+	/* GPP_C10:     WIFI_RF_KILL_N */
+	PAD_CFG_GPO(GPP_C10, 1, DEEP),
+	/* GPP_C11:     CLKREQ2_X4_GEN4_DT_CEM_SLOT1_N */
+	PAD_CFG_NF(GPP_C11, NONE, DEEP, NF1),
+	/* GPP_C12:     CLKREQ3_X4_GEN4_M2_SSD_N */
+	PAD_CFG_NF(GPP_C12, NONE, DEEP, NF1),
+	/* GPP_C13:     CLKREQ4_X4_GEN4_DT_CEM_SLOT2_N */
+	PAD_CFG_NF(GPP_C13, NONE, DEEP, NF1),
+	/* GPP_C14:     CLKREQ5_X1_GEN1_GBE_LAN_N */
+	PAD_CFG_NF(GPP_C14, NONE, DEEP, NF1),
+	/* GPP_C15:     FPS_RST_N */
+	PAD_CFG_GPO_LOCK(GPP_C15, 1, LOCK_CONFIG),
+	/* GPP_C16:     MOD_TCSS1_LS_TX_DDC_SCL */
+	PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1),
+	/* GPP_C17:     MOD_TCSS1_LS_RX_DDC_SDA */
+	PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1),
+	/* GPP_C18:     MOD_TCSS2_LS_TX_DDC_SCL */
+	PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1),
+	/* GPP_C19:     MOD_TCSS2_LS_RX_DDC_SDA */
+	PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1),
+	/* GPP_C22:     DDPB_HDMI_CTRLCLK */
+	PAD_CFG_NF(GPP_C22, NONE, DEEP, NF2),
+	/* GPP_C23:     DDPB_HDMI_CTRLDATA */
+	PAD_CFG_NF(GPP_C23, NONE, DEEP, NF2),
+
+	/* GPP_D */
+	/* GPP_D01:     MOD_TCSS1_TYP_A_VBUS_EN */
+	PAD_CFG_GPO(GPP_D01, 1, DEEP),
+	/* GPP_D02:     SOC_WP_OD */
+	PAD_CFG_GPO(GPP_D02, 0, DEEP),
+	/* GPP_D03:     X4_SLOT_WAKE_N */
+	PAD_CFG_GPI_SCI_LOW(GPP_D03, NONE, DEEP, LEVEL),
+	/* GPP_D07:     ISH_UART0_RTS_N_SNSR_HDR */
+	PAD_NC(GPP_D07, NONE),
+	/* GPP_D08:     ISH_UART0_CTS_N_SNSR_HDR */
+	PAD_NC(GPP_D08, NONE),
+	/* GPP_D09:     I2S_MCLK_HDR */
+	PAD_CFG_NF(GPP_D09, NONE, DEEP, NF1),
+	/* GPP_D10:     HDA_BCLK (HDR) */
+	PAD_CFG_NF(GPP_D10, NONE, DEEP, NF1),
+	/* GPP_D11:     HDA_SYNC (HDR) */
+	PAD_CFG_NF(GPP_D11, NONE, DEEP, NF1),
+	/* GPP_D12:     HDA_SDO (HDR) */
+	PAD_CFG_NF(GPP_D12, NONE, DEEP, NF1),
+	/* GPP_D13:     HDA_SDI0 (HDR) */
+	PAD_CFG_NF(GPP_D13, NONE, DEEP, NF1),
+	/* GPP_D16:     HDA_RST_N (HDR) */
+	PAD_CFG_NF(GPP_D16, NONE, DEEP, NF1),
+	/* GPP_D17:     HDA_SDI1 (HDR) */
+	PAD_CFG_NF(GPP_D17, NONE, DEEP, NF1),
+	/* GPP_D19:     NC */
+	PAD_NC(GPP_D19, NONE),
+	/* GPP_D21:     GPP_D21_UFS_REFCLK_R */
+	PAD_CFG_NF(GPP_D21, NONE, DEEP, NF1),
+
+	/* GPP_E */
+	/* GPP_E01:     PM_SLP_DRAM_N */
+	PAD_CFG_NF(GPP_E01, NONE, DEEP, NF2),
+	/* GPP_E02:     NC */
+	PAD_NC(GPP_E02, NONE),
+	/* GPP_E03:     X4_DT_PCIE_RST_N */
+	PAD_CFG_GPO(GPP_E03, 1, PLTRST),
+	/* GPP_E05:     GPP_E5_FPS_PWREN */
+	PAD_CFG_GPO(GPP_E05, 1, DEEP),
+	/* GPP_E06:     GPP_E6_PEN_DETECT */
+	PAD_CFG_GPI_TRIG_OWN(GPP_E06, NONE, DEEP, LEVEL, ACPI),
+	/* GPP_E07:     LAN_GPIO_RST_N */
+	PAD_CFG_GPO(GPP_E07, 1, PLTRST),
+	/* GPP_E08:     EC_SOC_INT_ODL */
+	PAD_CFG_GPI(GPP_E08, NONE, DEEP),
+	/* GPP_E09:     USB_FP_CONN_1_CONN_2_OC0_N */
+	PAD_CFG_NF(GPP_E09, NONE, DEEP, NF1),
+	/* GPP_E10:     M2_UFS_DET_SEL_N */
+	PAD_CFG_GPI(GPP_E10, NONE, DEEP),
+	/* GPP_E11:     THC0_SPI1_CLK_TCH_PNL1 */
+	PAD_CFG_NF(GPP_E11, NONE, DEEP, NF3),
+	/* GPP_E12:     THC_I2C0_SCL_TCH_PNL1 */
+	PAD_CFG_NF(GPP_E12, NONE, DEEP, NF3),
+	/* GPP_E13:     THC_I2C0_SDA_TCH_PNL1 */
+	PAD_CFG_NF(GPP_E13, NONE, DEEP, NF3),
+	/* GPP_E14:     THC0_SPI1_IO_2_TCH_PNL1 */
+	PAD_CFG_NF(GPP_E14, NONE, DEEP, NF3),
+	/* GPP_E15:     THC0_SPI1_IO_3_TCH_PNL1 */
+	PAD_CFG_NF(GPP_E15, NONE, DEEP, NF3),
+	/* GPP_E16:     THC0_SPI1_RST_N_TCH_PNL1 */
+	PAD_CFG_NF(GPP_E16, NONE, PLTRST, NF1),
+	/* GPP_E17:     GPP_E17_GSPI0A_CS0 */
+	PAD_CFG_NF(GPP_E17, NONE, DEEP, NF5),
+	/* GPP_E18:     THC0_SPI1_INT_N_TCH_PNL1 */
+	PAD_CFG_NF(GPP_E18, NONE, DEEP, NF3),
+	/* GPP_E19:     FPS_INT_N */
+	PAD_CFG_GPI_IRQ_WAKE(GPP_E19, NONE, PWROK, LEVEL, INVERT),
+	/* GPP_E20:     FPS_FW_UPDATE */
+	PAD_CFG_GPO_LOCK(GPP_E20, 0, LOCK_CONFIG),
+	/* GPP_E21:     I2C_PMC_PD_INT_N */
+	PAD_CFG_NF(GPP_E21, NONE, DEEP, NF1),
+	/* GPP_E22:     NC */
+	PAD_NC(GPP_E22, NONE),
+
+	/* GPP_F */
+	/* GPP_F00:     M.2_CNV_BRI_DT_BT_UART2_RTS_N */
+	PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_F00, NONE, DEEP, NF1),
+	/* GPP_F01:     M.2_CNV_BRI_RSP_BT_UART2_RXD */
+	PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_F01, NONE, DEEP, NF1),
+	/* GPP_F02:     M.2_CNV_RGI_DT_BT_UART2_TXD */
+	PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_F02, NONE, DEEP, NF1),
+	/* GPP_F03:     M.2_CNV_RGI_RSP_BT_UART2_CTS_N */
+	PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_F03, NONE, DEEP, NF1),
+	/* GPP_F04:     CNV_RF_RESET_R_N */
+	PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_F04, NONE, DEEP, NF1),
+	/* GPP_F05:     CRF_CLKREQ_R */
+	PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_F05, NONE, DEEP, NF3),
+	/* GPP_F06:     DISC_WLAN_WWAN_COEX3 */
+	PAD_CFG_NF(GPP_F06, NONE, DEEP, NF1),
+	/* GPP_F07:     FUSA_DIAGTEST_EN_HDR */
+	PAD_CFG_NF(GPP_F07, NONE, DEEP, NF2),
+	/* GPP_F08:     TCH_PNL1_PWR_EN */
+	PAD_CFG_GPO(GPP_F08, 1, PLTRST),
+	/* GPP_F09:     M2_UFS_RST_N */
+	PAD_CFG_GPO(GPP_F09, 1, DEEP),
+	/* GPP_F10:     X4_PCIE_SLOT1_PWR_EN */
+	PAD_CFG_GPO(GPP_F10, 1, PLTRST),
+	/* GPP_F11:     THC1_SPI2_CLK_TCH_PNL2 */
+	PAD_CFG_NF(GPP_F11, NONE, DEEP, NF11),
+	/* GPP_F12:     THC_I2C1_SCL_TCH_PAD */
+	PAD_CFG_NF(GPP_F12, NONE, DEEP, NF8),
+	/* GPP_F13:     THC_I2C1_SDA_TCH_PAD */
+	PAD_CFG_NF(GPP_F13, NONE, DEEP, NF8),
+	/* GPP_F14:     GPP_F14_GPSI0A_MOSI */
+	PAD_CFG_NF(GPP_F14, NONE, DEEP, NF8),
+	/* GPP_F15:     GPP_F15_GSPI0A_MISO */
+	PAD_CFG_NF(GPP_F15, NONE, DEEP, NF8),
+	/* GPP_F16:     GPP_F16_GSPI0A_CLK */
+	PAD_CFG_NF(GPP_F16, NONE, DEEP, NF8),
+	/* GPP_F17:     CODEC_IRQ_HDR */
+	PAD_CFG_GPI(GPP_F17, NONE, DEEP),
+	/* GPP_F18:     TCH_PAD_INT_N */
+	PAD_CFG_GPI_APIC_DRIVER(GPP_F18, NONE, PLTRST, EDGE_SINGLE, INVERT),
+	/* GPP_F19:     NC */
+	PAD_NC(GPP_F19, NONE),
+	/* GPP_F20:     CSE_EARLY_SW */
+	PAD_CFG_GPI(GPP_F20, NONE, DEEP),
+	/* GPP_F22:     THC1_SPI2_DSYNC */
+	PAD_CFG_NF(GPP_F22, NONE, DEEP, NF3),
+
+	/* GPP_H */
+	/* GPP_H00:     NC */
+	PAD_NC(GPP_H00, NONE),
+	/* GPP_H01:     M2_UFS_SLP_N */
+	PAD_CFG_GPO(GPP_H01, 1, DEEP),
+	/* GPP_H02:     DEBUG_TRACE_PNP */
+	PAD_CFG_GPO(GPP_H02, 1, PLTRST),
+	/* GPP_H03:     MIC MUTE */
+	PAD_CFG_NF(GPP_H03, NONE, DEEP, NF1),
+	/* GPP_H04:     CNV_MFUART2_RXD */
+	PAD_CFG_NF(GPP_H04, NONE, DEEP, NF1),
+	/* GPP_H05:     CNV_MFUART2_TXD */
+	PAD_CFG_NF(GPP_H05, NONE, DEEP, NF1),
+	/* GPP_H06:     I2C3_SCL_AUDIO_HDR */
+	PAD_CFG_NF(GPP_H06, NONE, DEEP, NF1),
+	/* GPP_H07:     I2C3_SDA_AUDIO_HDR */
+	PAD_CFG_NF(GPP_H07, NONE, DEEP, NF1),
+	/* GPP_H08:     SOC_BIOS_LOG_TTK_UART_RX */
+	PAD_CFG_NF(GPP_H08, NONE, DEEP, NF1),
+	/* GPP_H09:     SOC_BIOS_LOG_TTK_UART_TX */
+	PAD_CFG_NF(GPP_H09, NONE, DEEP, NF1),
+	/* GPP_H10:     UART0_BUF_RTS */
+	PAD_CFG_NF(GPP_H10, NONE, DEEP, NF1),
+	/* GPP_H11:     UART0_BUF_CTS */
+	PAD_CFG_NF(GPP_H11, NONE, DEEP, NF1),
+	/* GPP_H13:     CPU_C10_GATE_N_R */
+	PAD_CFG_NF(GPP_H13, NONE, DEEP, NF1),
+	/* GPP_H14:     ISH_I3C1_SDA_SNSR_HDR */
+	PAD_NC(GPP_H14, NONE),
+	/* GPP_H15:     ISH_I3C1_SCL_SNSR_HDR */
+	PAD_NC(GPP_H15, NONE),
+	/* GPP_H17:     MIC MUTE LED */
+	PAD_CFG_NF(GPP_H17, NONE, DEEP, NF1),
+	/* GPP_H18:     GEN4_SSD_PWREN */
+	PAD_CFG_GPO(GPP_H18, 1, DEEP),
+	/* GPP_H19:     I3C0_SDA_HDR */
+	PAD_CFG_NF(GPP_H19, NONE, DEEP, NF2),
+	/* GPP_H20:     I3C0_SCL_HDR */
+	PAD_CFG_NF(GPP_H20, NONE, DEEP, NF2),
+	/* GPP_H21:     I2C1_SDA_TTK_CHROME */
+	PAD_CFG_NF(GPP_H21, NONE, DEEP, NF1),
+	/* GPP_H22:     I2C1_SCL_TTK_CHROME */
+	PAD_CFG_NF(GPP_H22, NONE, DEEP, NF1),
+	/* GPP_H23:     TP */
+	PAD_CFG_NF(GPP_H23, NONE, DEEP, NF1),
+	/* GPP_H24:     TP */
+	PAD_CFG_NF(GPP_H24, NONE, DEEP, NF1),
+
+	/* GPP_V */
+	/* GPP_V00:     PM_BATLOW_N */
+	PAD_CFG_NF(GPP_V00, NONE, DEEP, NF1),
+	/* GPP_V01:     BC_ACOK_MCP */
+	PAD_CFG_NF(GPP_V01, NONE, DEEP, NF1),
+	/* GPP_V02:     LANWAKE_N_R */
+	PAD_CFG_NF(GPP_V02, NONE, DEEP, NF1),
+	/* GPP_V03:     PWRBTN_MCP_N */
+	PAD_CFG_NF(GPP_V03, NONE, DEEP, NF1),
+	/* GPP_V04:     PM_SLP_S3_N */
+	PAD_CFG_NF(GPP_V04, NONE, DEEP, NF1),
+	/* GPP_V05:     PM_SLP_S4_N */
+	PAD_CFG_NF(GPP_V05, NONE, DEEP, NF1),
+	/* GPP_V06:     PM_SLP_A_N */
+	PAD_CFG_NF(GPP_V06, NONE, DEEP, NF1),
+	/* GPP_V07:     M.2_BTWIFI_SUS_CLK_LS */
+	PAD_CFG_NF(GPP_V07, NONE, DEEP, NF1),
+	/* GPP_V08:     SLP_WLAN_N */
+	PAD_CFG_NF(GPP_V08, NONE, DEEP, NF1),
+	/* GPP_V09:     PM_SLP_S5_N */
+	PAD_CFG_NF(GPP_V09, NONE, DEEP, NF1),
+	/* GPP_V10:     LANPHYPC_R_N */
+	PAD_CFG_NF(GPP_V10, NONE, DEEP, NF1),
+	/* GPP_V11:     PM_SLP_LAN_N */
+	PAD_CFG_NF(GPP_V11, NONE, DEEP, NF1),
+	/* GPP_V12:     WAKE_N */
+	PAD_CFG_NF(GPP_V12, NONE, DEEP, NF1),
+	/* GPP_V13:     GPP_V13_CATERR_N */
+	PAD_CFG_NF(GPP_V13, NONE, DEEP, NF1),
+	/* GPP_V14:     GPP_V14_FORCEPR_N */
+	PAD_CFG_NF(GPP_V14, NONE, DEEP, NF1),
+	/* GPP_V15:     GPP_V15_THERMTRIP_N */
+	PAD_CFG_NF(GPP_V15, NONE, DEEP, NF1),
+	/* GPP_V16:     GPP_V16_VCCST_EN */
+	PAD_CFG_NF(GPP_V16, NONE, DEEP, NF1),
+};
+
+/* Early pad configuration in bootblock */
+static const struct pad_config early_gpio_table[] = {
+	/* GPP_B17:     SPI_TPM_INT_N */
+	PAD_CFG_GPI_APIC(GPP_B17, NONE, DEEP, LEVEL, INVERT),
+	/* GPP_H06: I2C3_SDA_PSS */
+	PAD_CFG_NF(GPP_H06, NONE, DEEP, NF1),
+	/* GPP_H07: I2C3_SCL_PSS */
+	PAD_CFG_NF(GPP_H07, NONE, DEEP, NF1),
+	/* GPP_H08:     SOC_BIOS_LOG_TTK_UART_RX */
+	PAD_CFG_NF(GPP_H08, NONE, DEEP, NF1),
+	/* GPP_H09:     SOC_BIOS_LOG_TTK_UART_TX */
+	PAD_CFG_NF(GPP_H09, NONE, DEEP, NF1),
+	/* GPP_H21:     I2C1_SDA_TTK_CHROME */
+	PAD_CFG_NF(GPP_H21, NONE, DEEP, NF1),
+	/* GPP_H22:     I2C1_SCL_TTK_CHROME */
+	PAD_CFG_NF(GPP_H22, NONE, DEEP, NF1),
+};
+
+/* Pad configuration in romstage */
+static const struct pad_config romstage_gpio_table[] = {
+	/* GPP_C00:     SPD_SMB_CLK */
+	PAD_CFG_NF(GPP_C00, NONE, DEEP, NF1),
+	/* GPP_C01:     SPD_SMB_DATA */
+	PAD_CFG_NF(GPP_C01, NONE, DEEP, NF1),
+	/* GPP_C15:     FPS_RST_N */
+	PAD_CFG_GPO(GPP_C15, 0, PLTRST),
+};
+
+const struct pad_config *variant_gpio_table(size_t *num)
+{
+	*num = ARRAY_SIZE(gpio_table);
+	return gpio_table;
+}
+
+const struct pad_config *variant_early_gpio_table(size_t *num)
+{
+	*num = ARRAY_SIZE(early_gpio_table);
+	return early_gpio_table;
+}
+
+/* Create the stub for romstage gpio, typically use for power sequence */
+const struct pad_config *variant_romstage_gpio_table(size_t *num)
+{
+	*num = ARRAY_SIZE(romstage_gpio_table);
+	return romstage_gpio_table;
+}
+
+static const struct cros_gpio cros_gpios[] = {
+	CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE0_NAME),
+	CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE1_NAME),
+	CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE2_NAME),
+	CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE3_NAME),
+	CROS_GPIO_WP_AH(GPIO_PCH_WP, CROS_GPIO_DEVICE4_NAME),
+};
+
+DECLARE_CROS_GPIOS(cros_gpios);
diff --git a/src/mainboard/google/ocelot/variants/matsu/hda_verb.c b/src/mainboard/google/ocelot/variants/matsu/hda_verb.c
new file mode 100644
index 0000000000..2f703b78ee
--- /dev/null
+++ b/src/mainboard/google/ocelot/variants/matsu/hda_verb.c
@@ -0,0 +1,126 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <device/azalia_device.h>
+
+const u32 cim_verb_data[] = {
+	/* coreboot specific header */
+	0x10ec0256,	/* Codec Vendor / Device ID: Realtek ALC256 */
+	0x10ec12ac,	/* Subsystem ID */
+	0x00000013,	/* Number of jacks (NID entries) */
+
+	AZALIA_RESET(0x1),
+	/* NID 0x01, HDA Codec Subsystem ID Verb Table */
+	AZALIA_SUBVENDOR(0, 0x10ec12ac),
+
+	/* Pin Widget Verb Table */
+	/*
+	 * DMIC
+	 * Requirement is to use PCH DMIC. Hence,
+	 * commented out codec's Internal DMIC.
+	 * AZALIA_PIN_CFG(0, 0x12, 0x90A60130),
+	 * AZALIA_PIN_CFG(0, 0x13, 0x40000000),
+	 */
+	/* Pin widget 0x14 - Front (Port-D) */
+	AZALIA_PIN_CFG(0, 0x14, 0x90170110),
+	/* Pin widget 0x18 - NPC */
+	AZALIA_PIN_CFG(0, 0x18, 0x411111F0),
+	/* Pin widget 0x19 - MIC2 (Port-F) */
+	AZALIA_PIN_CFG(0, 0x19, 0x04A11040),
+	/* Pin widget 0x1A - LINE1 (Port-C) */
+	AZALIA_PIN_CFG(0, 0x1a, 0x411111F0),
+	/* Pin widget 0x1B - NPC */
+	AZALIA_PIN_CFG(0, 0x1b, 0x411111F0),
+	/* Pin widget 0x1D - BEEP-IN */
+	AZALIA_PIN_CFG(0, 0x1d, 0x40610041),
+	/* Pin widget 0x1E - NPC */
+	AZALIA_PIN_CFG(0, 0x1e, 0x411111F0),
+	/* Pin widget 0x21 - HP1-OUT (Port-I) */
+	AZALIA_PIN_CFG(0, 0x21, 0x04211020),
+	/*
+	 * Widget node 0x20 - 1
+	 * Codec hidden reset and speaker power 2W/4ohm
+	 */
+	0x0205001A,
+	0x0204C003,
+	0x02050038,
+	0x02047901,
+	/*
+	 * Widget node 0x20 - 2
+	 * Class D power on Reset
+	 */
+	0x0205003C,
+	0x02040354,
+	0x0205003C,
+	0x02040314,
+	/*
+	 * Widget node 0x20 - 3
+	 * Disable AGC and set AGC limit to -1.5dB
+	 */
+	0x02050016,
+	0x02040C50,
+	0x02050012,
+	0x0204EBC1,
+	/*
+	 * Widget node 0x20 - 4
+	 * Set AGC Post gain +1.5dB then Enable AGC
+	 */
+	0x02050013,
+	0x02044023,
+	0x02050016,
+	0x02040E50,
+	/*
+	 * Widget node 0x20 - 5
+	 * Silence detector enabling + Set EAPD to verb control
+	 */
+	0x02050037,
+	0x0204FE15,
+	0x02050010,
+	0x02040020,
+	/*
+	 * Widget node 0x20 - 6
+	 * Silence data mode Threshold (-90dB)
+	 */
+	0x02050030,
+	0x0204A000,
+	0x0205001B,
+	0x02040A4B,
+	/*
+	 * Widget node 0x20 - 7
+	 * Default setting-1
+	 */
+	0x05750003,
+	0x05740DA3,
+	0x02050046,
+	0x02040004,
+	/*
+	 * Widget node 0x20 - 8
+	 * support 1 pin detect two port
+	 */
+	0x02050009,
+	0x0204E003,
+	0x0205000A,
+	0x02047770,
+	/*
+	 * Widget node 0x20 - 9
+	 * To set LDO1/LDO2 as default
+	 */
+	0x02050008,
+	0x02046A0C,
+	0x02050008,
+	0x02046A0C,
+};
+
+const u32 pc_beep_verbs[] = {
+	/* Dos beep path - 1 */
+	0x01470C00,
+	0x02050036,
+	0x02047151,
+	0x01470740,
+	/* Dos beep path - 2 */
+	0x0143b000,
+	0x01470C02,
+	0x01470C02,
+	0x01470C02,
+};
+
+AZALIA_ARRAY_SIZES;
diff --git a/src/mainboard/google/ocelot/variants/matsu/include/variant/ec.h b/src/mainboard/google/ocelot/variants/matsu/include/variant/ec.h
new file mode 100644
index 0000000000..4fc0622f15
--- /dev/null
+++ b/src/mainboard/google/ocelot/variants/matsu/include/variant/ec.h
@@ -0,0 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#ifndef MAINBOARD_EC_H
+#define MAINBOARD_EC_H
+
+#include <baseboard/ec.h>
+
+#endif /* MAINBOARD_GPIO_H */
diff --git a/src/mainboard/google/ocelot/variants/matsu/include/variant/gpio.h b/src/mainboard/google/ocelot/variants/matsu/include/variant/gpio.h
new file mode 100644
index 0000000000..cced66807a
--- /dev/null
+++ b/src/mainboard/google/ocelot/variants/matsu/include/variant/gpio.h
@@ -0,0 +1,11 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#ifndef __MAINBOARD_GPIO_H__
+#define __MAINBOARD_GPIO_H__
+
+#include <baseboard/gpio.h>
+
+/* EC wake is LAN_WAKE# which is a special DeepSX wake pin */
+#define GPE_EC_WAKE	GPE0_LAN_WAK
+
+#endif /* __MAINBOARD_GPIO_H__ */
diff --git a/src/mainboard/google/ocelot/variants/matsu/memory.c b/src/mainboard/google/ocelot/variants/matsu/memory.c
new file mode 100644
index 0000000000..59fa99f0eb
--- /dev/null
+++ b/src/mainboard/google/ocelot/variants/matsu/memory.c
@@ -0,0 +1,69 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <baseboard/variants.h>
+#include <soc/meminit.h>
+#include <soc/romstage.h>
+
+static const struct mb_cfg lp5_mem_config = {
+	.type = MEM_TYPE_LP5X,
+
+	.lpx_dq_map = {
+		.ddr0 = {
+			.dq0 = {  10,  11,  8,  9,  15,  14,  12,  13, },
+			.dq1 = {  7,  4,  5,  6,  3,  0,  2,  1 },
+		},
+		.ddr1 = {
+			.dq0 = {  8,  11,  10,  9,  15,  12,  13,  14, },
+			.dq1 = {  6,  7,  5,  4,  1,  3,  0,  2 },
+		},
+		.ddr2 = {
+			.dq0 = {  3,  2,  1,  0,  6,  7,  5,  4, },
+			.dq1 = {  9,  8,  10,  11,  15,  12,  13,  14 },
+		},
+		.ddr3 = {
+			.dq0 = {  8,  11,  10,  9,  15,  13,  12,  14, },
+			.dq1 = {  4,  5,  6,  7,  1,  3,  2,  0 },
+		},
+	},
+
+	.lpx_dqs_map = {
+		.ddr0 = { .dqs0 = 1, .dqs1 = 0 },
+		.ddr1 = { .dqs0 = 1, .dqs1 = 0 },
+		.ddr2 = { .dqs0 = 0, .dqs1 = 1 },
+		.ddr3 = { .dqs0 = 1, .dqs1 = 0 },
+	},
+
+	.ect = true, /* Early Command Training */
+
+	.lp_ddr_dq_dqs_re_training = 1,
+
+	.user_bd = BOARD_TYPE_ULT_ULX,
+
+	.lp5x_config = {
+		.ccc_config = 0xFF,
+	},
+};
+
+const struct mb_cfg *variant_memory_params(void)
+{
+	return &lp5_mem_config;
+}
+
+int variant_memory_sku(void)
+{
+	/*
+	 * Memory configuration board straps
+	 * GPIO_MEM_CONFIG_0	GPP_H23
+	 * GPIO_MEM_CONFIG_1	GPP_H24
+	 * GPIO_MEM_CONFIG_2	GPP_B06
+	 * GPIO_MEM_CONFIG_3    GPP_B08
+	 */
+	gpio_t spd_gpios[] = {
+		GPP_H23,
+		GPP_H24,
+		GPP_B06,
+		GPP_B08,
+	};
+
+	return gpio_base2_value(spd_gpios, ARRAY_SIZE(spd_gpios));
+}
diff --git a/src/mainboard/google/ocelot/variants/matsu/memory/Makefile.mk b/src/mainboard/google/ocelot/variants/matsu/memory/Makefile.mk
new file mode 100644
index 0000000000..4a2c289d2f
--- /dev/null
+++ b/src/mainboard/google/ocelot/variants/matsu/memory/Makefile.mk
@@ -0,0 +1,7 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+# This is an auto-generated file. Do not edit!!
+# Generated by:
+# ./util/spd_tools/bin/part_id_gen PTL lp5 src/mainboard/google/ocelot/variants/matsu/memory src/mainboard/google/ocelot/variants/matsu/memory/mem_parts_used.txt
+
+SPD_SOURCES =
+SPD_SOURCES += spd/lp5/set-0/spd-11.hex      # ID = 0(0b0000)  Parts = H58G56BK8BX068
diff --git a/src/mainboard/google/ocelot/variants/matsu/memory/dram_id.generated.txt b/src/mainboard/google/ocelot/variants/matsu/memory/dram_id.generated.txt
new file mode 100644
index 0000000000..7dd01b0eee
--- /dev/null
+++ b/src/mainboard/google/ocelot/variants/matsu/memory/dram_id.generated.txt
@@ -0,0 +1,7 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+# This is an auto-generated file. Do not edit!!
+# Generated by:
+# ./util/spd_tools/bin/part_id_gen PTL lp5 src/mainboard/google/ocelot/variants/matsu/memory src/mainboard/google/ocelot/variants/matsu/memory/mem_parts_used.txt
+
+DRAM Part Name                 ID to assign
+H58G56BK8BX068                 0 (0000)
diff --git a/src/mainboard/google/ocelot/variants/matsu/memory/mem_parts_used.txt b/src/mainboard/google/ocelot/variants/matsu/memory/mem_parts_used.txt
new file mode 100644
index 0000000000..ae8eff2d96
--- /dev/null
+++ b/src/mainboard/google/ocelot/variants/matsu/memory/mem_parts_used.txt
@@ -0,0 +1,12 @@
+# This is a CSV file containing a list of memory parts used by this variant.
+# One part per line with an optional fixed ID in column 2.
+# Only include a fixed ID if it is required for legacy reasons!
+# Generated IDs are dependent on the order of parts in this file,
+# so new parts must always be added at the end of the file!
+#
+# Generate an updated Makefile.mk and dram_id.generated.txt by running the
+# part_id_gen tool from util/spd_tools.
+# See util/spd_tools/README.md for more details and instructions.
+
+# Part Name
+H58G56BK8BX068
diff --git a/src/mainboard/google/ocelot/variants/matsu/overridetree.cb b/src/mainboard/google/ocelot/variants/matsu/overridetree.cb
new file mode 100644
index 0000000000..bfd637ae50
--- /dev/null
+++ b/src/mainboard/google/ocelot/variants/matsu/overridetree.cb
@@ -0,0 +1,5 @@
+chip soc/intel/pantherlake
+
+	device domain 0 on
+	end
+end

From b1fe32dd9e5b9c5a381962b8e34ef19ad40f9da4 Mon Sep 17 00:00:00 2001
From: Bora Guvendik <bora.guvendik@intel.com>
Date: Mon, 8 Sep 2025 14:15:33 -0700
Subject: [PATCH 2005/3886] mb/{intel,google}/{fatcat,ptlrvp}: Update GPP_A15
 GPIO configuration

As per Intel document 853127, EPD_ON_GCD_OUT (previously GPP_A15)
is no longer available for other functions. Updated GPIO
configuration accordingly.

Reference: Intel doc 853127

BUG=none
TEST=Build and boot test on fatcat hardware

Change-Id: Ie4a3967ceecd10905ba0424d85d8f1392625bf16
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89103
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Reviewed-by: Pranava Y N <pranavayn@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/google/fatcat/variants/fatcat/gpio.c | 4 ++--
 src/mainboard/intel/ptlrvp/variants/ptlrvp/gpio.c  | 4 ++--
 2 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/src/mainboard/google/fatcat/variants/fatcat/gpio.c b/src/mainboard/google/fatcat/variants/fatcat/gpio.c
index 62fc5aed49..eb03641251 100644
--- a/src/mainboard/google/fatcat/variants/fatcat/gpio.c
+++ b/src/mainboard/google/fatcat/variants/fatcat/gpio.c
@@ -36,8 +36,8 @@ static const struct pad_config gpio_table[] = {
 	PAD_CFG_GPO(GPP_A11, 1, PLTRST),
 	/* GPP_A12:     WIFI_WAKE_N */
 	PAD_CFG_GPI_SCI_LOW(GPP_A12, NONE, DEEP, LEVEL),
-	/* GPP_A15:     GPP_A15_DNX_FORCE_RELOAD */
-	PAD_CFG_NF(GPP_A15, NONE, DEEP, NF1),
+	/* GPP_A15:     NC */
+	PAD_NC(GPP_A15, NONE),
 	/* GPP_A16:     BT_RF_KILL_N */
 	PAD_CFG_GPO(GPP_A16, 1, DEEP),
 	/* GPP_A17:     WIFI_RF_KILL_N */
diff --git a/src/mainboard/intel/ptlrvp/variants/ptlrvp/gpio.c b/src/mainboard/intel/ptlrvp/variants/ptlrvp/gpio.c
index 7dcf6d7873..c2913c48d3 100644
--- a/src/mainboard/intel/ptlrvp/variants/ptlrvp/gpio.c
+++ b/src/mainboard/intel/ptlrvp/variants/ptlrvp/gpio.c
@@ -37,8 +37,8 @@ static const struct pad_config t3_gpio_table[] = {
 	PAD_CFG_GPO(GPP_A11, 1, PLTRST),
 	/* GPP_A12:     WIFI_WAKE_N */
 	PAD_CFG_GPI_SCI_LOW(GPP_A12, NONE, DEEP, LEVEL),
-	/* GPP_A15:     GPP_A15_DNX_FORCE_RELOAD */
-	PAD_CFG_NF(GPP_A15, NONE, DEEP, NF1),
+	/* GPP_A15:     NC */
+	PAD_NC(GPP_A15, NONE),
 	/* GPP_A16:     BT_RF_KILL_N */
 	PAD_CFG_GPO(GPP_A16, 1, DEEP),
 	/* GPP_A17:     WIFI_RF_KILL_N */

From f8574f714533d07d1e839c5f920665f9ca950774 Mon Sep 17 00:00:00 2001
From: Sowmya Aralguppe <sowmya.aralguppe@intel.com>
Date: Tue, 19 Aug 2025 23:36:55 +0530
Subject: [PATCH 2006/3886] soc/intel/ptl: Add Wildcat Lake SKU power map
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Add mapping of different SKUs based on CPU ID and TDP values.
Add PowerLimits (PL) values.
Add i_trip value for Fast Vmode.

Note: The i_trip value, the value at which the Voltage Regulator (VR)
or SoC will trigger a protective action such as throttling or
entering Fast Vmode is, due to not being documented, currently set at
70% of the maximum current the VR is designed to support for a rail.
The actual i_trip value to be updated once it is available.

Ref=858124 Power Delivery Guide Rev1p0
    830097 Powermap Rev1p1

BUG=b:433211504
TEST= Build Ocelot and verify it compiles without any error.
check CPU log for the following error

    [ERROR]  Could not find the SKU power map

With the current patch this error line is not seen in the CPU log
anymore.

Change-Id: I8c54efc8eb360ed6f814a336448bb204d5ab0268
Signed-off-by: Sowmya Aralguppe <sowmya.aralguppe@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88858
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Appukuttan V K <appukuttan.vk@intel.com>
Reviewed-by: Usha P <usha.p@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
---
 src/include/device/pci_ids.h                        |  2 ++
 .../ocelot/variants/baseboard/ocelot/devicetree.cb  | 11 +++++++++++
 .../intel/common/block/systemagent/systemagent.c    |  2 ++
 .../intel/pantherlake/bootblock/report_platform.c   |  2 ++
 src/soc/intel/pantherlake/chip.h                    | 13 ++++++++++++-
 src/soc/intel/pantherlake/chipset_wcl.cb            |  6 +++++-
 6 files changed, 34 insertions(+), 2 deletions(-)

diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h
index a63df081a8..2c3723afa6 100644
--- a/src/include/device/pci_ids.h
+++ b/src/include/device/pci_ids.h
@@ -4687,6 +4687,8 @@
 #define PCI_DID_INTEL_WCL_ID_1			0xfd00
 #define PCI_DID_INTEL_WCL_ID_2			0xfd01
 #define PCI_DID_INTEL_WCL_ID_3			0xfd02
+#define PCI_DID_INTEL_WCL_ID_4			0xfd03
+#define PCI_DID_INTEL_WCL_ID_5			0xfd04
 
 /* Intel SMBUS device Ids */
 #define PCI_DID_INTEL_LPT_H_SMBUS			0x8c22
diff --git a/src/mainboard/google/ocelot/variants/baseboard/ocelot/devicetree.cb b/src/mainboard/google/ocelot/variants/baseboard/ocelot/devicetree.cb
index 2939a065fa..18708eb7f4 100644
--- a/src/mainboard/google/ocelot/variants/baseboard/ocelot/devicetree.cb
+++ b/src/mainboard/google/ocelot/variants/baseboard/ocelot/devicetree.cb
@@ -63,6 +63,17 @@ chip soc/intel/pantherlake
 	# Enable Energy Reporting
 	register "pch_pm_energy_report_enable" = "true"
 
+	# Reference: 858124 Power Delivery Guide Rev1p0, 830097 Powermap Rev1p1
+	# fast_vmode_i_trip values are derived from ICCMax with a safety margin.
+	# ITRIP_NOM is approximately 0.70 of ICCMax
+	# TODO: Update with actual i_trip values.
+
+	register "fast_vmode_i_trip[WCL_CORE]" = "{
+		[VR_DOMAIN_IA] = 35 * 4,
+		[VR_DOMAIN_GT] = 35 * 4,
+		[VR_DOMAIN_SA] = 24 * 4
+	}"
+
 	register "serial_io_uart_mode" = "{
 		[PchSerialIoIndexUART0] = PchSerialIoSkipInit,
 		[PchSerialIoIndexUART1] = PchSerialIoDisabled,
diff --git a/src/soc/intel/common/block/systemagent/systemagent.c b/src/soc/intel/common/block/systemagent/systemagent.c
index 30acf30f49..749e9c6ad9 100644
--- a/src/soc/intel/common/block/systemagent/systemagent.c
+++ b/src/soc/intel/common/block/systemagent/systemagent.c
@@ -428,6 +428,8 @@ static const unsigned short systemagent_ids[] = {
 	PCI_DID_INTEL_WCL_ID_1,
 	PCI_DID_INTEL_WCL_ID_2,
 	PCI_DID_INTEL_WCL_ID_3,
+	PCI_DID_INTEL_WCL_ID_4,
+	PCI_DID_INTEL_WCL_ID_5,
 	PCI_DID_INTEL_PTL_U_ID_1,
 	PCI_DID_INTEL_PTL_U_ID_2,
 	PCI_DID_INTEL_PTL_U_ID_3,
diff --git a/src/soc/intel/pantherlake/bootblock/report_platform.c b/src/soc/intel/pantherlake/bootblock/report_platform.c
index d6cae4afad..30639d5668 100644
--- a/src/soc/intel/pantherlake/bootblock/report_platform.c
+++ b/src/soc/intel/pantherlake/bootblock/report_platform.c
@@ -44,6 +44,8 @@ static struct {
 	{ PCI_DID_INTEL_WCL_ID_1, "Wildcatlake" },
 	{ PCI_DID_INTEL_WCL_ID_2, "Wildcatlake" },
 	{ PCI_DID_INTEL_WCL_ID_3, "Wildcatlake" },
+	{ PCI_DID_INTEL_WCL_ID_4, "Wildcatlake" },
+	{ PCI_DID_INTEL_WCL_ID_5, "Wildcatlake" },
 };
 
 static struct {
diff --git a/src/soc/intel/pantherlake/chip.h b/src/soc/intel/pantherlake/chip.h
index e9a73a1635..c837ec6da9 100644
--- a/src/soc/intel/pantherlake/chip.h
+++ b/src/soc/intel/pantherlake/chip.h
@@ -58,6 +58,7 @@ enum soc_intel_pantherlake_power_limits {
 	PTL_H_1_CORE,
 	PTL_H_2_CORE,
 	PTL_H_3_CORE,
+	WCL_CORE,
 	PTL_POWER_LIMITS_COUNT,
 };
 
@@ -74,7 +75,12 @@ enum soc_intel_pantherlake_sku {
 	PTL_H484_SKU,
 	PTL_H4XE_SKU,
 	PTL_H204_SKU,
-	MAX_PTL_SKUS
+	WCL_SKU_1,
+	WCL_SKU_2,
+	WCL_SKU_3,
+	WCL_SKU_4,
+	WCL_SKU_5,
+	MAX_PTL_SKUS,
 };
 
 /* Mapping of different SKUs based on CPU ID and TDP values */
@@ -98,6 +104,11 @@ static const struct soc_intel_pantherlake_power_map {
 	{ PCI_DID_INTEL_PTL_H_ID_6, PTL_H_2_CORE, TDP_25W, PTL_H4XE_SKU },
 	{ PCI_DID_INTEL_PTL_H_ID_7, PTL_H_2_CORE, TDP_25W, PTL_H4XE_SKU },
 	{ PCI_DID_INTEL_PTL_H_ID_8, PTL_H_2_CORE, TDP_25W, PTL_H12XE_SKU },
+	{ PCI_DID_INTEL_WCL_ID_1, WCL_CORE, TDP_15W, WCL_SKU_1},
+	{ PCI_DID_INTEL_WCL_ID_2, WCL_CORE, TDP_15W, WCL_SKU_2},
+	{ PCI_DID_INTEL_WCL_ID_3, WCL_CORE, TDP_15W, WCL_SKU_3},
+	{ PCI_DID_INTEL_WCL_ID_4, WCL_CORE, TDP_15W, WCL_SKU_4},
+	{ PCI_DID_INTEL_WCL_ID_5, WCL_CORE, TDP_15W, WCL_SKU_5},
 };
 
 /* Types of display ports */
diff --git a/src/soc/intel/pantherlake/chipset_wcl.cb b/src/soc/intel/pantherlake/chipset_wcl.cb
index c5f1d2bd11..31abe5be94 100644
--- a/src/soc/intel/pantherlake/chipset_wcl.cb
+++ b/src/soc/intel/pantherlake/chipset_wcl.cb
@@ -2,7 +2,11 @@ chip soc/intel/pantherlake
 
 	device cpu_cluster 0 on end
 
-	# TODO: Add WCL power limits
+	register "power_limits_config[WCL_CORE]" = "{
+		.tdp_pl1_override = 15,
+		.tdp_pl2_override = 35,
+		.tdp_pl4 = 93,
+	}"
 
 	# Reduce the size of BasicMemoryTests to speed up the boot time.
 	register "lower_basic_mem_test_size" = "true"

From 2c03fd06a9fd607b5942316f0bcf156bb99e1f2b Mon Sep 17 00:00:00 2001
From: Eren Peng <peng.eren@inventec.corp-partner.google.com>
Date: Fri, 5 Sep 2025 16:09:35 +0800
Subject: [PATCH 2007/3886] mb/google/trulo/var/kaladin: Disable ISH via
 firmware config

Kelsier shares the same firmware with Kaladin so coreboot loads the same
loader firmware to ISH. Since Kelsier is a sensor-less design, change
it to load lite_ish.bin and disable ISH related GPIOs depending on
firmware config.

BUG=b:441613379
TEST=flash and boot to DUT, check suspend function works normally on
kelsier

Change-Id: I04c77db813fcd993217b5c366872cc583e265939
Signed-off-by: Eren Peng <peng.eren@inventec.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89067
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Derek Huang <derekhuang@google.com>
---
 .../brya/variants/kaladin/overridetree.cb     | 15 ++++++-
 .../google/brya/variants/kaladin/variant.c    | 42 +++++++++++++++++++
 2 files changed, 56 insertions(+), 1 deletion(-)

diff --git a/src/mainboard/google/brya/variants/kaladin/overridetree.cb b/src/mainboard/google/brya/variants/kaladin/overridetree.cb
index 08cb01231c..6a707cedb2 100644
--- a/src/mainboard/google/brya/variants/kaladin/overridetree.cb
+++ b/src/mainboard/google/brya/variants/kaladin/overridetree.cb
@@ -1,4 +1,8 @@
 fw_config
+	field TABLET_MODE 0 0
+		option TABLET_MODE_ABSENT 0
+		option TABLET_MODE_PRESENT 1
+	end
 	field THERMAL_SOLUTION 1 1
 		option THERMAL_SOLUTION_6W	0
 		option THERMAL_SOLUTION_15W	1
@@ -535,7 +539,16 @@ chip soc/intel/alderlake
 			chip drivers/intel/ish
 				register "firmware_name" = ""kaladin_ish.bin""
 				register "add_acpi_dma_property" = "true"
-				device generic 0 on end
+				device generic 0 on
+					probe TABLET_MODE TABLET_MODE_PRESENT
+				end
+			end
+			chip drivers/intel/ish
+				register "firmware_name" = ""lite_ish.bin""
+				register "add_acpi_dma_property" = "true"
+				device generic 0 on
+					probe TABLET_MODE TABLET_MODE_ABSENT
+				end
 			end
 		end
 		device ref ufs on
diff --git a/src/mainboard/google/brya/variants/kaladin/variant.c b/src/mainboard/google/brya/variants/kaladin/variant.c
index 1443b03cfa..909d2e0fdd 100644
--- a/src/mainboard/google/brya/variants/kaladin/variant.c
+++ b/src/mainboard/google/brya/variants/kaladin/variant.c
@@ -1,5 +1,8 @@
 /* SPDX-License-Identifier: GPL-2.0-or-later */
 
+#include <baseboard/gpio.h>
+#include <baseboard/variants.h>
+#include <console/console.h>
 #include <fw_config.h>
 #include <sar.h>
 
@@ -7,3 +10,42 @@ const char *get_wifi_sar_cbfs_filename(void)
 {
 	return get_wifi_sar_fw_config_filename(FW_CONFIG_FIELD(WIFI_SAR));
 }
+
+static const struct pad_config ish_disable_pads[] = {
+	/* B3  : ISH_IMU_INT_L ==>NC */
+	PAD_NC(GPP_B3, NONE),
+	/* B4  : ISH_ACC_INT_L ==>NC */
+	PAD_NC(GPP_B4, NONE),
+	/* B5  : GPP_B5 ==> NC */
+	PAD_NC(GPP_B5, NONE),
+	/* B6  : GPP_B6 ==> NC */
+	PAD_NC(GPP_B6, NONE),
+	/* D1  : ISH_GP1 ==> NC */
+	PAD_NC(GPP_D1, NONE),
+	/* D13  : UART0_ISH_RXD ==> NC */
+	PAD_NC(GPP_D13, NONE),
+	/* D14  : UART0_ISH_TXD ==> NC */
+	PAD_NC(GPP_D14, NONE),
+};
+
+void fw_config_gpio_padbased_override(struct pad_config *padbased_table)
+{
+	if (fw_config_probe(FW_CONFIG(TABLET_MODE, TABLET_MODE_ABSENT))) {
+		printk(BIOS_INFO, "Disable ISH GPIO pins.\n");
+		gpio_padbased_override(padbased_table, ish_disable_pads, ARRAY_SIZE(ish_disable_pads));
+	}
+}
+
+void variant_configure_pads(void)
+{
+	const struct pad_config *base_pads;
+	struct pad_config *padbased_table;
+	size_t base_num;
+
+	padbased_table = new_padbased_table();
+	base_pads = variant_gpio_table(&base_num);
+	gpio_padbased_override(padbased_table, base_pads, base_num);
+	fw_config_gpio_padbased_override(padbased_table);
+	gpio_configure_pads_with_padbased(padbased_table);
+	free(padbased_table);
+}

From f3211e9639d1e8a4e7dcda9b9106421f659a0492 Mon Sep 17 00:00:00 2001
From: Bora Guvendik <bora.guvendik@intel.com>
Date: Tue, 9 Sep 2025 10:35:22 -0700
Subject: [PATCH 2008/3886] soc/intel/pantherlake: Add support for Acoustic
 Noise Mitigation UPDs
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

SlowSlewRate, AcousticNoiseMitigation and FastPkgCRampDisable upds
can be overwritten with this patch.

BUG=none
TEST=Able to override the acoustic noise UPDs.

Change-Id: I5bfa98834f8d7cfcaab3fdbb7dde914d78529581
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89123
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
---
 src/soc/intel/pantherlake/romstage/fsp_params.c | 16 ++++++++++++++++
 1 file changed, 16 insertions(+)

diff --git a/src/soc/intel/pantherlake/romstage/fsp_params.c b/src/soc/intel/pantherlake/romstage/fsp_params.c
index 22f1ec2cc3..ba6c110f2e 100644
--- a/src/soc/intel/pantherlake/romstage/fsp_params.c
+++ b/src/soc/intel/pantherlake/romstage/fsp_params.c
@@ -356,6 +356,21 @@ void platform_display_early_shutdown_notification(void *arg)
 }
 #endif
 
+static void fill_fsps_acoustic_params(FSP_M_CONFIG *m_cfg,
+				   const struct soc_intel_pantherlake_config *config)
+{
+	if (!config->enable_acoustic_noise_mitigation)
+		return;
+
+	m_cfg->AcousticNoiseMitigation = config->enable_acoustic_noise_mitigation;
+
+	for (size_t i = 0; i < ARRAY_SIZE(config->disable_fast_pkgc_ramp); i++) {
+		m_cfg->FastPkgCRampDisable[i] = config->disable_fast_pkgc_ramp[i];
+		m_cfg->SlowSlewRate[i] = config->slow_slew_rate_config[i];
+	}
+}
+
+
 static void soc_memory_init_params(FSP_M_CONFIG *m_cfg,
 				   const struct soc_intel_pantherlake_config *config)
 {
@@ -377,6 +392,7 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg,
 		fill_fspm_trace_params,
 		fill_fspm_thermal_params,
 		fill_fspm_vr_config_params,
+		fill_fsps_acoustic_params,
 	};
 
 	for (size_t i = 0; i < ARRAY_SIZE(fill_fspm_params); i++)

From 2b84d26f55dd5b2c45ca7508f1ce0e194b582f63 Mon Sep 17 00:00:00 2001
From: Sergii Dmytruk <sergii.dmytruk@3mdeb.com>
Date: Sat, 20 Jul 2024 20:43:52 +0300
Subject: [PATCH 2009/3886] payloads/edk2: configure capsule updates

This requires version of EDK2 in use to understand those defines, but
the build isn't affected negatively if they aren't handled.

Upstream EDK2 has CAPSULE_SUPPORT for a while and modifications that
make it enable FMP capsules are already merged to be part of the next
stable release (the one after edk2-stable202508 which should be
edk2-stable202511).

The `sed` part is updated because GUID contains dashes just like option
names, so need to take leading spaces into account to avoid processing
dashes in values.  This doesn't cover all possible cases, but should be
good enough.

Change-Id: I1c684cb8929842a5d3c4b06e8a9c0a748470ea41
Signed-off-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83682
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Benjamin Doron <benjamin.doron00@gmail.com>
---
 payloads/external/Makefile.mk   | 2 ++
 payloads/external/edk2/Makefile | 8 +++++++-
 2 files changed, 9 insertions(+), 1 deletion(-)

diff --git a/payloads/external/Makefile.mk b/payloads/external/Makefile.mk
index 655e14df03..4c93298fac 100644
--- a/payloads/external/Makefile.mk
+++ b/payloads/external/Makefile.mk
@@ -200,6 +200,8 @@ $(obj)/UEFIPAYLOAD.fd: $(DOTCONFIG)
 		CONFIG_EDK2_PCO_MMIO_EMMC=$(CONFIG_EDK2_PCO_MMIO_EMMC) \
 		CONFIG_EDK2_USE_LAPIC_TIMER=$(CONFIG_EDK2_USE_LAPIC_TIMER) \
 		CONFIG_SOC_AMD_COMMON_BLOCK_PSP_GEN2=$(CONFIG_SOC_AMD_COMMON_BLOCK_PSP_GEN2) \
+		CONFIG_DRIVERS_EFI_UPDATE_CAPSULES=$(CONFIG_DRIVERS_EFI_UPDATE_CAPSULES) \
+		CONFIG_DRIVERS_EFI_MAIN_FW_GUID=$(CONFIG_DRIVERS_EFI_MAIN_FW_GUID) \
 		GCC_CC_x86_32=$(GCC_CC_x86_32) \
 		GCC_CC_x86_64=$(GCC_CC_x86_64) \
 		GCC_CC_arm=$(GCC_CC_arm) \
diff --git a/payloads/external/edk2/Makefile b/payloads/external/edk2/Makefile
index 7c87c3469e..168c511562 100644
--- a/payloads/external/edk2/Makefile
+++ b/payloads/external/edk2/Makefile
@@ -122,6 +122,12 @@ endif
 ifeq ($(CONFIG_SOC_AMD_COMMON_BLOCK_PSP_GEN2), y)
 BUILD_STR += --pcd gPcAtChipsetPkgTokenSpaceGuid.PcdInitialValueRtcRegisterD=0x80
 endif
+# CAPSULE_SUPPORT		= FALSE
+# CAPSULE_MAIN_FW_GUID	=
+ifeq ($(CONFIG_DRIVERS_EFI_UPDATE_CAPSULES),y)
+BUILD_STR += -D CAPSULE_SUPPORT=TRUE
+BUILD_STR += -D CAPSULE_MAIN_FW_GUID=$(CONFIG_DRIVERS_EFI_MAIN_FW_GUID)
+endif
 
 #
 # The MrChromebox repository has the following addition options:
@@ -276,7 +282,7 @@ print:
 	echo "   Branch:         $(CONFIG_EDK2_TAG_OR_REV)"
 	echo "   Packages path:  $(PACKAGES_PATH)"
 	echo " $(BUILD_STR)" | \
-		sed -e 's/--/-/g' -e 's/-/\n   /g' | sort | sed \
+		sed -e 's/ --/ -/g' -e 's/ -/ \n   /g' | sort | sed \
 		-e 's/a /Architecture:   /g' \
 		-e 's/b /Release:        /g' \
 		-e 's/D /Option:         /g' \

From 8bc0eddf1572676fd850eaba767eef7674d1c4f0 Mon Sep 17 00:00:00 2001
From: Jeremy Compostella <jeremy.compostella@intel.com>
Date: Thu, 11 Sep 2025 14:39:31 -0700
Subject: [PATCH 2010/3886] soc/intel/pantherlake: Add support for a new
 Panther Lake B0 SKU

This commit adds support for a new Panther Lake B0 SKU CPUID c06c3.

BUG=b:444497427
TEST=Successfully boot a fatcat device with new Panther Lake B0.
     coreboot displays the following log:
     CPU: ID c06c3, Pantherlake B0, ucode: 0000010c

Change-Id: Id2c1caf8d6845bb16a94314c4e9a214def06efee
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89150
Reviewed-by: Jamie Ryu <jamie.m.ryu@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
---
 src/include/cpu/intel/cpu_ids.h                       | 1 +
 src/soc/intel/common/block/cpu/mp_init.c              | 1 +
 src/soc/intel/pantherlake/bootblock/report_platform.c | 1 +
 3 files changed, 3 insertions(+)

diff --git a/src/include/cpu/intel/cpu_ids.h b/src/include/cpu/intel/cpu_ids.h
index 70e5b7b0c3..d8b067c1fa 100644
--- a/src/include/cpu/intel/cpu_ids.h
+++ b/src/include/cpu/intel/cpu_ids.h
@@ -89,6 +89,7 @@
 #define CPUID_PANTHERLAKE_A0		0xc06c0
 #define CPUID_PANTHERLAKE_B0_1		0xc06c1
 #define CPUID_PANTHERLAKE_B0_2		0xc06c2
+#define CPUID_PANTHERLAKE_B0_3		0xc06c3
 #define CPUID_SNOWRIDGE_A0		0x80660
 #define CPUID_SNOWRIDGE_A1		0x80661
 #define CPUID_SNOWRIDGE_A2		0x80662
diff --git a/src/soc/intel/common/block/cpu/mp_init.c b/src/soc/intel/common/block/cpu/mp_init.c
index 638aa07f29..b4ee88a0ad 100644
--- a/src/soc/intel/common/block/cpu/mp_init.c
+++ b/src/soc/intel/common/block/cpu/mp_init.c
@@ -36,6 +36,7 @@ static const struct cpu_device_id cpu_table[] = {
 	{ X86_VENDOR_INTEL, CPUID_PANTHERLAKE_A0, CPUID_EXACT_MATCH_MASK },
 	{ X86_VENDOR_INTEL, CPUID_PANTHERLAKE_B0_1, CPUID_EXACT_MATCH_MASK },
 	{ X86_VENDOR_INTEL, CPUID_PANTHERLAKE_B0_2, CPUID_EXACT_MATCH_MASK },
+	{ X86_VENDOR_INTEL, CPUID_PANTHERLAKE_B0_3, CPUID_EXACT_MATCH_MASK },
 	{ X86_VENDOR_INTEL, CPUID_LUNARLAKE_A0_1, CPUID_EXACT_MATCH_MASK },
 	{ X86_VENDOR_INTEL, CPUID_LUNARLAKE_A0_2, CPUID_EXACT_MATCH_MASK },
 	{ X86_VENDOR_INTEL, CPUID_METEORLAKE_A0_1, CPUID_EXACT_MATCH_MASK },
diff --git a/src/soc/intel/pantherlake/bootblock/report_platform.c b/src/soc/intel/pantherlake/bootblock/report_platform.c
index 30639d5668..871d19306f 100644
--- a/src/soc/intel/pantherlake/bootblock/report_platform.c
+++ b/src/soc/intel/pantherlake/bootblock/report_platform.c
@@ -23,6 +23,7 @@ static struct {
 	{ CPUID_PANTHERLAKE_A0, "Pantherlake A0" },
 	{ CPUID_PANTHERLAKE_B0_1, "Pantherlake B0" },
 	{ CPUID_PANTHERLAKE_B0_2, "Pantherlake B0" },
+	{ CPUID_PANTHERLAKE_B0_3, "Pantherlake B0" },
 	{ CPUID_WILDCATLAKE_A0, "Wildcatlake A0" },
 };
 

From 4b61d4de5ff0a1a1a83be602b660f3bdf91fa647 Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Fri, 5 Sep 2025 12:09:22 -0500
Subject: [PATCH 2011/3886] mb/starlabs/starbook/adl: Use macros for HDA verb
 table

Rework the HDA verb table using macros. Explicitly disable all
pin widgets not used. Use consistent formatting and verbiage in
comments.

TEST=build/boot Win11, Ubuntu 25.04 on Starbook ADL, verify all audio
inputs/outputs working as expected. Verify verbs loaded via cbmem log.

Change-Id: I728c835361f1fa6fe813255973b33131e2a008e2
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89077
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
---
 .../starlabs/starbook/variants/adl/hda_verb.c | 75 ++++++++++++++-----
 1 file changed, 56 insertions(+), 19 deletions(-)

diff --git a/src/mainboard/starlabs/starbook/variants/adl/hda_verb.c b/src/mainboard/starlabs/starbook/variants/adl/hda_verb.c
index 507a0bcf8b..662d268727 100644
--- a/src/mainboard/starlabs/starbook/variants/adl/hda_verb.c
+++ b/src/mainboard/starlabs/starbook/variants/adl/hda_verb.c
@@ -1,32 +1,68 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
 #include <device/azalia_device.h>
-#include <stdint.h>
+#include <device/azalia_codec/realtek.h>
 
 const u32 cim_verb_data[] = {
 	/* coreboot specific header */
-	0x10ec0269, /* Codec Vendor / Device ID: Realtek ALC269 */
-	0x1e507007, /* Subsystem ID */
-	17,	    /* Number of jacks (NID entries) */
+	0x10ec0269,	/* Codec Vendor / Device ID: Realtek ALC269 */
+	0x1e507007,	/* Subsystem ID */
+	17,		/* Number of verb entries */
 
 	/* Reset Codec First */
 	AZALIA_RESET(0x1),
 
-	/* HDA Codec Subsystem ID Verb-table */
+	/* HDA Codec Subsystem ID */
 	AZALIA_SUBVENDOR(0, 0x1e507007),
 
 	/* Pin Widget Verb-table */
-	AZALIA_PIN_CFG(0, 0x01, 0x00000000),
-	AZALIA_PIN_CFG(0, 0x12, 0x90a61120),
-	AZALIA_PIN_CFG(0, 0x14, 0x90171110),
-	AZALIA_PIN_CFG(0, 0x17, 0x40000000),
-	AZALIA_PIN_CFG(0, 0x18, 0x04a19030),
-	AZALIA_PIN_CFG(0, 0x19, 0x04ab1020),
-	AZALIA_PIN_CFG(0, 0x1a, AZALIA_PIN_CFG_NC(0)),
-	AZALIA_PIN_CFG(0, 0x1b, AZALIA_PIN_CFG_NC(0)),
-	AZALIA_PIN_CFG(0, 0x1d, AZALIA_PIN_CFG_NC(0)),
-	AZALIA_PIN_CFG(0, 0x1e, AZALIA_PIN_CFG_NC(0)),
-	AZALIA_PIN_CFG(0, 0x21, 0x042b1010),
+	AZALIA_PIN_CFG(0, ALC269_DMIC12,	AZALIA_PIN_DESC(
+							AZALIA_INTEGRATED,
+							AZALIA_MOBILE_LID_INSIDE,
+							AZALIA_MIC_IN,
+							AZALIA_OTHER_DIGITAL,
+							AZALIA_COLOR_UNKNOWN,
+							AZALIA_NO_JACK_PRESENCE_DETECT,
+							3,
+							0
+						)),
+	AZALIA_PIN_CFG(0, ALC269_SPEAKERS,	AZALIA_PIN_DESC(
+							AZALIA_INTEGRATED,
+							AZALIA_INTERNAL | AZALIA_FRONT,
+							AZALIA_SPEAKER,
+							AZALIA_OTHER_ANALOG,
+							AZALIA_COLOR_UNKNOWN,
+							AZALIA_NO_JACK_PRESENCE_DETECT,
+							1,
+							0
+						)),
+	AZALIA_PIN_CFG(0, ALC269_MIC1,		AZALIA_PIN_DESC(
+							AZALIA_JACK,
+							AZALIA_EXTERNAL_PRIMARY_CHASSIS | AZALIA_RIGHT,
+							AZALIA_MIC_IN,
+							AZALIA_STEREO_MONO_1_8,
+							AZALIA_BLACK,
+							AZALIA_JACK_PRESENCE_DETECT,
+							2,
+							0
+						)),
+	AZALIA_PIN_CFG(0, ALC269_VB_HP_OUT,	AZALIA_PIN_DESC(
+							AZALIA_JACK,
+							AZALIA_EXTERNAL_PRIMARY_CHASSIS | AZALIA_RIGHT,
+							AZALIA_HP_OUT,
+							AZALIA_STEREO_MONO_1_8,
+							AZALIA_BLACK,
+							AZALIA_JACK_PRESENCE_DETECT,
+							1,
+							0
+						)),
+	AZALIA_PIN_CFG(0, ALC269_MONO,		AZALIA_PIN_CFG_NC(0)),
+	AZALIA_PIN_CFG(0, ALC269_VC_HP_OUT,	AZALIA_PIN_CFG_NC(0)),
+	AZALIA_PIN_CFG(0, ALC269_MIC2,		AZALIA_PIN_CFG_NC(0)),
+	AZALIA_PIN_CFG(0, ALC269_LINE1,		AZALIA_PIN_CFG_NC(0)),
+	AZALIA_PIN_CFG(0, ALC269_LINE2,		AZALIA_PIN_CFG_NC(0)),
+	AZALIA_PIN_CFG(0, ALC269_PC_BEEP,	AZALIA_PIN_CFG_NC(0)),
+	AZALIA_PIN_CFG(0, ALC269_SPDIF_OUT,	AZALIA_PIN_CFG_NC(0)),
 
 	/* ALC269 Default 1 */
 	0x02050011,
@@ -52,9 +88,10 @@ const u32 cim_verb_data[] = {
 	0x02050005,
 	0x020400c0,
 
-	0x80862815, /* Codec Vendor / Device ID: Intel */
-	0x80860101, /* Subsystem ID */
-	10,	    /* Number of 4 dword sets */
+	/* Intel ADL IGD HDMI */
+	0x80862815,	/* Codec Vendor / Device ID: Intel */
+	0x80860101,	/* Subsystem ID */
+	10,		/* Number of verb entries */
 
 	AZALIA_SUBVENDOR(2, 0x80860101),
 

From 515f566840aeced4b2ff519acfe31f00ea3498c5 Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Thu, 4 Sep 2025 10:58:39 -0500
Subject: [PATCH 2012/3886] mb/starlabs/starbook/adl_n: Use macros for HDA verb
 table

Rework the HDA verb table using macros. Explicitly disable all
pin widgets not used. Use consistent formatting and verbiage in
comments. Group raw verbs in sets of 4 to make verification of verb
count easier.

TEST=build/boot Win11, Ubuntu 25.04 on Starbook ADL-N, verify all audio
outputs working as expected. Verify verbs loaded via cbmem log.

Change-Id: Ie0961a6ebc4aa8df0c2fedeff8fd5bacd16fc01e
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89078
Reviewed-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
---
 .../starbook/variants/adl_n/hda_verb.c        | 114 ++++++++----------
 1 file changed, 50 insertions(+), 64 deletions(-)

diff --git a/src/mainboard/starlabs/starbook/variants/adl_n/hda_verb.c b/src/mainboard/starlabs/starbook/variants/adl_n/hda_verb.c
index 1d03e21a55..53c7cd8d6b 100644
--- a/src/mainboard/starlabs/starbook/variants/adl_n/hda_verb.c
+++ b/src/mainboard/starlabs/starbook/variants/adl_n/hda_verb.c
@@ -1,18 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
 #include <device/azalia_device.h>
-#include <stdint.h>
-
-#define DMIC		0x12
-#define SPEAKERS	0x14
-#define HEADPHONE	0x15
-#define MONO		0x17
-#define MIC1		0x18
-#define MIC2		0x19
-#define LINE1		0x1a
-#define LINE2		0x1b
-#define PC_BEEP		0x1d
-#define S_PDIF		0x1e
+#include <device/azalia_codec/realtek.h>
 
 const u32 cim_verb_data[] = {
 	/* coreboot specific header */
@@ -26,76 +15,72 @@ const u32 cim_verb_data[] = {
 	/* HDA Codec Subsystem ID */
 	AZALIA_SUBVENDOR(0, 0x1e507038),
 
-	AZALIA_PIN_CFG(0, 0x01,		0x00000000),
-	AZALIA_PIN_CFG(0, DMIC,		AZALIA_PIN_DESC(
-						AZALIA_INTEGRATED,
-						AZALIA_MOBILE_LID_INSIDE,
-						AZALIA_MIC_IN,
-						AZALIA_OTHER_DIGITAL,
-						AZALIA_COLOR_UNKNOWN,
-						AZALIA_NO_JACK_PRESENCE_DETECT,
-						3,
-						0
-					)),
-
-	AZALIA_PIN_CFG(0, SPEAKERS,	AZALIA_PIN_DESC(
-						AZALIA_INTEGRATED,
-						AZALIA_INTERNAL | AZALIA_FRONT,
-						AZALIA_SPEAKER,
-						AZALIA_OTHER_ANALOG,
-						AZALIA_COLOR_UNKNOWN,
-						AZALIA_NO_JACK_PRESENCE_DETECT,
-						1,
-						0
-					)),
-	AZALIA_PIN_CFG(0, HEADPHONE,	AZALIA_PIN_DESC(
-						AZALIA_JACK,
-						AZALIA_EXTERNAL_PRIMARY_CHASSIS | AZALIA_RIGHT,
-						AZALIA_HP_OUT,
-						AZALIA_STEREO_MONO_1_8,
-						AZALIA_BLACK,
-						AZALIA_JACK_PRESENCE_DETECT,
-						2,
-						0
-					)),
-	AZALIA_PIN_CFG(0, MONO,		AZALIA_PIN_CFG_NC(0)),
-	AZALIA_PIN_CFG(0, MIC1,		AZALIA_PIN_DESC(
-						AZALIA_JACK,
-						AZALIA_EXTERNAL_PRIMARY_CHASSIS | AZALIA_RIGHT,
-						AZALIA_MIC_IN,
-						AZALIA_STEREO_MONO_1_8,
-						AZALIA_BLACK,
-						AZALIA_JACK_PRESENCE_DETECT,
-						4,
-						0
-					)),
-	AZALIA_PIN_CFG(0, MIC2,		AZALIA_PIN_CFG_NC(0)),
-	AZALIA_PIN_CFG(0, LINE1,	AZALIA_PIN_CFG_NC(0)),
-	AZALIA_PIN_CFG(0, LINE2,	AZALIA_PIN_CFG_NC(0)),
-	AZALIA_PIN_CFG(0, PC_BEEP,	AZALIA_PIN_CFG_NC(0)),
-	AZALIA_PIN_CFG(0, S_PDIF,	AZALIA_PIN_CFG_NC(0)),
+	/* Pin Widget Verb-table */
+	AZALIA_PIN_CFG(0, ALC269_DMIC12,	AZALIA_PIN_DESC(
+							AZALIA_INTEGRATED,
+							AZALIA_MOBILE_LID_INSIDE,
+							AZALIA_MIC_IN,
+							AZALIA_OTHER_DIGITAL,
+							AZALIA_COLOR_UNKNOWN,
+							AZALIA_NO_JACK_PRESENCE_DETECT,
+							3,
+							0
+						)),
+	AZALIA_PIN_CFG(0, ALC269_SPEAKERS,	AZALIA_PIN_DESC(
+							AZALIA_INTEGRATED,
+							AZALIA_INTERNAL | AZALIA_FRONT,
+							AZALIA_SPEAKER,
+							AZALIA_OTHER_ANALOG,
+							AZALIA_COLOR_UNKNOWN,
+							AZALIA_NO_JACK_PRESENCE_DETECT,
+							1,
+							0
+						)),
+	AZALIA_PIN_CFG(0, ALC269_VC_HP_OUT,	AZALIA_PIN_DESC(
+							AZALIA_JACK,
+							AZALIA_EXTERNAL_PRIMARY_CHASSIS | AZALIA_RIGHT,
+							AZALIA_HP_OUT,
+							AZALIA_STEREO_MONO_1_8,
+							AZALIA_BLACK,
+							AZALIA_JACK_PRESENCE_DETECT,
+							2,
+							0
+						)),
+	AZALIA_PIN_CFG(0, ALC269_MIC1,		AZALIA_PIN_DESC(
+							AZALIA_JACK,
+							AZALIA_EXTERNAL_PRIMARY_CHASSIS | AZALIA_RIGHT,
+							AZALIA_MIC_IN,
+							AZALIA_STEREO_MONO_1_8,
+							AZALIA_BLACK,
+							AZALIA_JACK_PRESENCE_DETECT,
+							4,
+							0
+						)),
+	AZALIA_PIN_CFG(0, ALC269_MONO,		AZALIA_PIN_CFG_NC(0)),
+	AZALIA_PIN_CFG(0, ALC269_MIC2,		AZALIA_PIN_CFG_NC(0)),
+	AZALIA_PIN_CFG(0, ALC269_LINE1,		AZALIA_PIN_CFG_NC(0)),
+	AZALIA_PIN_CFG(0, ALC269_LINE2,		AZALIA_PIN_CFG_NC(0)),
+	AZALIA_PIN_CFG(0, ALC269_PC_BEEP,	AZALIA_PIN_CFG_NC(0)),
+	AZALIA_PIN_CFG(0, ALC269_SPDIF_OUT,	AZALIA_PIN_CFG_NC(0)),
+	AZALIA_PIN_CFG(0, ALC269_VB_HP_OUT,	AZALIA_PIN_CFG_NC(0)),
 
 	0x02050018,
 	0x02040184,
-
 	0x0205001C,
 	0x02044b00,
 
 	0x02050024,
 	0x02040000,
-
 	0x02050004,
 	0x02040080,
 
 	0x02050008,
 	0x02040000,
-
 	0x0205000C,
 	0x02043F00,
 
 	0x02050015,
 	0x02048002,
-
 	0x02050015,
 	0x02048002,
 
@@ -104,6 +89,7 @@ const u32 cim_verb_data[] = {
 	0x00D37080,
 	0x00370610,
 
+	/* Intel ADL-N IGD HDMI */
 	0x8086280d,	/* Codec Vendor / Device ID: Intel */
 	0x80860101,	/* Subsystem ID */
 	4,		/* Number of 4 dword sets */

From 6d7c8f547774eb793f62a8b1fe51e8b4feebcb7b Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Fri, 5 Sep 2025 12:21:02 -0500
Subject: [PATCH 2013/3886] mb/starlabs/starbook/cml: Use macros for HDA verb
 table

Rework the HDA verb table using macros. Explicitly disable all
pin widgets not used. Use consistent formatting and verbiage in
comments. Update the verb count.

TEST=build/boot Win11, Ubuntu 25.04 on Starbook CML, verify all audio
inputs/outputs working as expected. Verify verbs loaded via cbmem log.

Change-Id: I1ee05afe9805ca6531d49150f1ead8722c4393b2
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89079
Reviewed-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
---
 .../starlabs/starbook/variants/cml/hda_verb.c | 70 ++++++++++++++-----
 1 file changed, 53 insertions(+), 17 deletions(-)

diff --git a/src/mainboard/starlabs/starbook/variants/cml/hda_verb.c b/src/mainboard/starlabs/starbook/variants/cml/hda_verb.c
index 980cd2a094..6713477593 100644
--- a/src/mainboard/starlabs/starbook/variants/cml/hda_verb.c
+++ b/src/mainboard/starlabs/starbook/variants/cml/hda_verb.c
@@ -1,12 +1,13 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
 #include <device/azalia_device.h>
+#include <device/azalia_codec/realtek.h>
 
 const u32 cim_verb_data[] = {
 	/* coreboot specific header */
-	0x10ec0256, /* Codec Vendor / Device ID: Realtek ALC256 */
-	0x10ec1200, /* Subsystem ID */
-	38,	    /* Number of jacks (NID entries) */
+	0x10ec0256,	/* Codec Vendor / Device ID: Realtek ALC256 */
+	0x10ec1200,	/* Subsystem ID */
+	36,		/* Number of verb entries */
 
 	/* Reset Codec First */
 	AZALIA_RESET(0x1),
@@ -15,17 +16,51 @@ const u32 cim_verb_data[] = {
 	AZALIA_SUBVENDOR(0, 0x10ec1200),
 
 	/* Pin Widget Verb-table */
-	AZALIA_PIN_CFG(0, 0x01, 0x00000000),
-	AZALIA_PIN_CFG(0, 0x12, 0x90a61120),
-	AZALIA_PIN_CFG(0, 0x13, 0x40000000),
-	AZALIA_PIN_CFG(0, 0x14, 0x90171110),
-	AZALIA_PIN_CFG(0, 0x18, AZALIA_PIN_CFG_NC(0)),
-	AZALIA_PIN_CFG(0, 0x19, 0x04ab1020),
-	AZALIA_PIN_CFG(0, 0x1a, AZALIA_PIN_CFG_NC(0)),
-	AZALIA_PIN_CFG(0, 0x1b, 0x40700001),
-	AZALIA_PIN_CFG(0, 0x1d, AZALIA_PIN_CFG_NC(0)),
-	AZALIA_PIN_CFG(0, 0x1e, AZALIA_PIN_CFG_NC(0)),
-	AZALIA_PIN_CFG(0, 0x21, 0x042b1010),
+	AZALIA_PIN_CFG(0, ALC256_DMIC12,	AZALIA_PIN_DESC(
+							AZALIA_INTEGRATED,
+							AZALIA_MOBILE_LID_INSIDE,
+							AZALIA_MIC_IN,
+							AZALIA_OTHER_DIGITAL,
+							AZALIA_COLOR_UNKNOWN,
+							AZALIA_NO_JACK_PRESENCE_DETECT,
+							3,
+							0
+						)),
+	AZALIA_PIN_CFG(0, ALC256_SPEAKERS,	AZALIA_PIN_DESC(
+							AZALIA_INTEGRATED,
+							AZALIA_INTERNAL | AZALIA_FRONT,
+							AZALIA_SPEAKER,
+							AZALIA_OTHER_ANALOG,
+							AZALIA_COLOR_UNKNOWN,
+							AZALIA_NO_JACK_PRESENCE_DETECT,
+							1,
+							0
+						)),
+	AZALIA_PIN_CFG(0, ALC256_MIC2,		AZALIA_PIN_DESC(
+							AZALIA_JACK,
+							AZALIA_EXTERNAL_PRIMARY_CHASSIS | AZALIA_RIGHT,
+							AZALIA_MIC_IN,
+							AZALIA_STEREO_MONO_1_8,
+							AZALIA_BLACK,
+							AZALIA_JACK_PRESENCE_DETECT,
+							2,
+							0
+						)),
+	AZALIA_PIN_CFG(0, ALC256_HP_OUT,	AZALIA_PIN_DESC(
+							AZALIA_JACK,
+							AZALIA_EXTERNAL_PRIMARY_CHASSIS | AZALIA_RIGHT,
+							AZALIA_HP_OUT,
+							AZALIA_STEREO_MONO_1_8,
+							AZALIA_BLACK,
+							AZALIA_JACK_PRESENCE_DETECT,
+							1,
+							0
+						)),
+	AZALIA_PIN_CFG(0, ALC256_DMIC34,	AZALIA_PIN_CFG_NC(0)),
+	AZALIA_PIN_CFG(0, ALC256_LINE1,		AZALIA_PIN_CFG_NC(0)),
+	AZALIA_PIN_CFG(0, ALC256_LINE2,		AZALIA_PIN_CFG_NC(0)),
+	AZALIA_PIN_CFG(0, ALC256_PC_BEEP,	AZALIA_PIN_CFG_NC(0)),
+	AZALIA_PIN_CFG(0, ALC256_SPDIF_OUT,	AZALIA_PIN_CFG_NC(0)),
 
 	/* Reset to D0 */
 	0x00170500,
@@ -205,9 +240,10 @@ const u32 cim_verb_data[] = {
 	0x02050020,
 	0x020451FF,
 
-	0x8086280b, /* Codec Vendor / Device ID: Intel */
-	0x80860101, /* Subsystem ID */
-	4,	    /* Number of 4 dword sets */
+	/* Intel CML IGD HDMI */
+	0x8086280b,	/* Codec Vendor / Device ID: Intel */
+	0x80860101,	/* Subsystem ID */
+	4,		/* Number of verb entries */
 
 	AZALIA_SUBVENDOR(2, 0x80860101),
 

From 543f6c2a522ef6163f2bdbd5579ecfcd44cb4f25 Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Thu, 4 Sep 2025 11:01:32 -0500
Subject: [PATCH 2014/3886] mb/starlabs/starbook/kbl: Use macros for HDA verb
 table

Rework the HDA verb table using macros. Explicitly disable all
pin widgets not used. Use consistent formatting and verbiage in
comments. Group raw verbs in sets of 4 to make verification of verb
count easier.

TEST=build/boot Win11, Ubuntu 25.04 on Starbook KBL, verify all audio
inputs/outputs working as expected. Verify verbs loaded via cbmem log.

Change-Id: I3cf96ce12250d6a5cd7afa39070681606266fb2b
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89080
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
---
 .../starlabs/starbook/variants/kbl/hda_verb.c | 114 ++++++++----------
 1 file changed, 50 insertions(+), 64 deletions(-)

diff --git a/src/mainboard/starlabs/starbook/variants/kbl/hda_verb.c b/src/mainboard/starlabs/starbook/variants/kbl/hda_verb.c
index 82071822a4..746b68b351 100644
--- a/src/mainboard/starlabs/starbook/variants/kbl/hda_verb.c
+++ b/src/mainboard/starlabs/starbook/variants/kbl/hda_verb.c
@@ -1,18 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
 #include <device/azalia_device.h>
-#include <stdint.h>
-
-#define DMIC		0x12
-#define SPEAKERS	0x14
-#define HEADPHONE	0x15
-#define MONO		0x17
-#define MIC1		0x18
-#define MIC2		0x19
-#define LINE1		0x1a
-#define LINE2		0x1b
-#define PC_BEEP		0x1d
-#define S_PDIF		0x1e
+#include <device/azalia_codec/realtek.h>
 
 const u32 cim_verb_data[] = {
 	/* coreboot specific header */
@@ -26,76 +15,72 @@ const u32 cim_verb_data[] = {
 	/* HDA Codec Subsystem ID */
 	AZALIA_SUBVENDOR(0, 0x1e507038),
 
-	AZALIA_PIN_CFG(0, 0x01,		0x00000000),
-	AZALIA_PIN_CFG(0, DMIC,		AZALIA_PIN_DESC(
-						AZALIA_INTEGRATED,
-						AZALIA_MOBILE_LID_INSIDE,
-						AZALIA_MIC_IN,
-						AZALIA_OTHER_DIGITAL,
-						AZALIA_COLOR_UNKNOWN,
-						AZALIA_NO_JACK_PRESENCE_DETECT,
-						3,
-						0
+	/* Pin Widget Verb-table */
+	AZALIA_PIN_CFG(0, ALC269_DMIC12,	AZALIA_PIN_DESC(
+							AZALIA_INTEGRATED,
+							AZALIA_MOBILE_LID_INSIDE,
+							AZALIA_MIC_IN,
+							AZALIA_OTHER_DIGITAL,
+							AZALIA_COLOR_UNKNOWN,
+							AZALIA_NO_JACK_PRESENCE_DETECT,
+							3,
+							0
+						)),
+	AZALIA_PIN_CFG(0, ALC269_SPEAKERS,	AZALIA_PIN_DESC(
+							AZALIA_INTEGRATED,
+							AZALIA_INTERNAL | AZALIA_FRONT,
+							AZALIA_SPEAKER,
+							AZALIA_OTHER_ANALOG,
+							AZALIA_COLOR_UNKNOWN,
+							AZALIA_NO_JACK_PRESENCE_DETECT,
+							1,
+							0
 					)),
-
-	AZALIA_PIN_CFG(0, SPEAKERS,	AZALIA_PIN_DESC(
-						AZALIA_INTEGRATED,
-						AZALIA_INTERNAL | AZALIA_FRONT,
-						AZALIA_SPEAKER,
-						AZALIA_OTHER_ANALOG,
-						AZALIA_COLOR_UNKNOWN,
-						AZALIA_NO_JACK_PRESENCE_DETECT,
-						1,
-						0
-					)),
-	AZALIA_PIN_CFG(0, HEADPHONE,	AZALIA_PIN_DESC(
-						AZALIA_JACK,
-						AZALIA_EXTERNAL_PRIMARY_CHASSIS | AZALIA_RIGHT,
-						AZALIA_HP_OUT,
-						AZALIA_STEREO_MONO_1_8,
-						AZALIA_BLACK,
-						AZALIA_JACK_PRESENCE_DETECT,
-						2,
-						0
-					)),
-	AZALIA_PIN_CFG(0, MONO,		AZALIA_PIN_CFG_NC(0)),
-	AZALIA_PIN_CFG(0, MIC1,		AZALIA_PIN_DESC(
-						AZALIA_JACK,
-						AZALIA_EXTERNAL_PRIMARY_CHASSIS | AZALIA_RIGHT,
-						AZALIA_MIC_IN,
-						AZALIA_STEREO_MONO_1_8,
-						AZALIA_BLACK,
-						AZALIA_JACK_PRESENCE_DETECT,
-						4,
-						0
-					)),
-	AZALIA_PIN_CFG(0, MIC2,		AZALIA_PIN_CFG_NC(0)),
-	AZALIA_PIN_CFG(0, LINE1,	AZALIA_PIN_CFG_NC(0)),
-	AZALIA_PIN_CFG(0, LINE2,	AZALIA_PIN_CFG_NC(0)),
-	AZALIA_PIN_CFG(0, PC_BEEP,	AZALIA_PIN_CFG_NC(0)),
-	AZALIA_PIN_CFG(0, S_PDIF,	AZALIA_PIN_CFG_NC(0)),
+	AZALIA_PIN_CFG(0, ALC269_VC_HP_OUT,	AZALIA_PIN_DESC(
+							AZALIA_JACK,
+							AZALIA_EXTERNAL_PRIMARY_CHASSIS | AZALIA_RIGHT,
+							AZALIA_HP_OUT,
+							AZALIA_STEREO_MONO_1_8,
+							AZALIA_BLACK,
+							AZALIA_JACK_PRESENCE_DETECT,
+							2,
+							0
+						)),
+	AZALIA_PIN_CFG(0, ALC269_MIC1,		AZALIA_PIN_DESC(
+							AZALIA_JACK,
+							AZALIA_EXTERNAL_PRIMARY_CHASSIS | AZALIA_RIGHT,
+							AZALIA_MIC_IN,
+							AZALIA_STEREO_MONO_1_8,
+							AZALIA_BLACK,
+							AZALIA_JACK_PRESENCE_DETECT,
+							4,
+							0
+						)),
+	AZALIA_PIN_CFG(0, ALC269_MONO,		AZALIA_PIN_CFG_NC(0)),
+	AZALIA_PIN_CFG(0, ALC269_MIC2,		AZALIA_PIN_CFG_NC(0)),
+	AZALIA_PIN_CFG(0, ALC269_LINE1,		AZALIA_PIN_CFG_NC(0)),
+	AZALIA_PIN_CFG(0, ALC269_LINE2,		AZALIA_PIN_CFG_NC(0)),
+	AZALIA_PIN_CFG(0, ALC269_PC_BEEP,	AZALIA_PIN_CFG_NC(0)),
+	AZALIA_PIN_CFG(0, ALC269_SPDIF_OUT,	AZALIA_PIN_CFG_NC(0)),
+	AZALIA_PIN_CFG(0, ALC269_VB_HP_OUT,	AZALIA_PIN_CFG_NC(0)),
 
 	0x02050018,
 	0x02040184,
-
 	0x0205001C,
 	0x02044b00,
 
 	0x02050024,
 	0x02040000,
-
 	0x02050004,
 	0x02040080,
 
 	0x02050008,
 	0x02040000,
-
 	0x0205000C,
 	0x02043F00,
 
 	0x02050015,
 	0x02048002,
-
 	0x02050015,
 	0x02048002,
 
@@ -104,9 +89,10 @@ const u32 cim_verb_data[] = {
 	0x00D37080,
 	0x00370610,
 
+	/* Intel KBL IGD HDMI */
 	0x8086280d,	/* Codec Vendor / Device ID: Intel */
 	0x80860101,	/* Subsystem ID */
-	4,		/* Number of 4 dword sets */
+	4,		/* Number of verb entries */
 
 	AZALIA_SUBVENDOR(2, 0x80860101),
 

From 6d6a280ab2746c11f72c9b39640d955066267e41 Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Thu, 4 Sep 2025 10:55:45 -0500
Subject: [PATCH 2015/3886] mb/starlabs/starbook/mtl: Use macros for HDA verb
 table

Rework the HDA verb table using macros. Explicitly disable all
pin widgets not used. Use consistent formatting and verbiage in
comments. Group raw verbs in sets of 4 to make verification of verb
count easier.

TEST=build/boot Win11, ubuntu 25.04 on Starbook MTL, verify all audio
inputs/outputs function as expected. Verify verbs loaded via cbmem log.

Change-Id: I0805d943009de1963c8e6da5acf56dd7a5ea83ac
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89081
Reviewed-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 .../starlabs/starbook/variants/mtl/hda_verb.c | 114 ++++++++----------
 1 file changed, 50 insertions(+), 64 deletions(-)

diff --git a/src/mainboard/starlabs/starbook/variants/mtl/hda_verb.c b/src/mainboard/starlabs/starbook/variants/mtl/hda_verb.c
index eb16aaf3e9..64d7754120 100644
--- a/src/mainboard/starlabs/starbook/variants/mtl/hda_verb.c
+++ b/src/mainboard/starlabs/starbook/variants/mtl/hda_verb.c
@@ -1,18 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
 #include <device/azalia_device.h>
-#include <stdint.h>
-
-#define DMIC		0x12
-#define SPEAKERS	0x14
-#define HEADPHONE	0x15
-#define MONO		0x17
-#define MIC1		0x18
-#define MIC2		0x19
-#define LINE1		0x1a
-#define LINE2		0x1b
-#define PC_BEEP		0x1d
-#define S_PDIF		0x1e
+#include <device/azalia_codec/realtek.h>
 
 const u32 cim_verb_data[] = {
 	/* coreboot specific header */
@@ -26,76 +15,72 @@ const u32 cim_verb_data[] = {
 	/* HDA Codec Subsystem ID */
 	AZALIA_SUBVENDOR(0, 0x1025174e),
 
-	AZALIA_PIN_CFG(0, 0x01,		0x00000000),
-	AZALIA_PIN_CFG(0, DMIC,		AZALIA_PIN_DESC(
-						AZALIA_INTEGRATED,
-						AZALIA_MOBILE_LID_INSIDE,
-						AZALIA_MIC_IN,
-						AZALIA_OTHER_DIGITAL,
-						AZALIA_COLOR_UNKNOWN,
-						AZALIA_NO_JACK_PRESENCE_DETECT,
-						3,
-						0
-					)),
-
-	AZALIA_PIN_CFG(0, SPEAKERS,	AZALIA_PIN_DESC(
-						AZALIA_INTEGRATED,
-						AZALIA_INTERNAL | AZALIA_TOP,
-						AZALIA_SPEAKER,
-						AZALIA_OTHER_ANALOG,
-						AZALIA_COLOR_UNKNOWN,
-						AZALIA_NO_JACK_PRESENCE_DETECT,
-						1,
-						0
-					)),
-	AZALIA_PIN_CFG(0, HEADPHONE,	AZALIA_PIN_DESC(
-						AZALIA_JACK,
-						AZALIA_EXTERNAL_PRIMARY_CHASSIS | AZALIA_RIGHT,
-						AZALIA_HP_OUT,
-						AZALIA_STEREO_MONO_1_8,
-						AZALIA_BLACK,
-						AZALIA_JACK_PRESENCE_DETECT,
-						2,
-						0
-					)),
-	AZALIA_PIN_CFG(0, MONO,		AZALIA_PIN_CFG_NC(0)),
-	AZALIA_PIN_CFG(0, MIC1,		AZALIA_PIN_DESC(
-						AZALIA_JACK,
-						AZALIA_EXTERNAL_PRIMARY_CHASSIS | AZALIA_RIGHT,
-						AZALIA_MIC_IN,
-						AZALIA_STEREO_MONO_1_8,
-						AZALIA_BLACK,
-						AZALIA_JACK_PRESENCE_DETECT,
-						4,
-						0
-					)),
-	AZALIA_PIN_CFG(0, MIC2,		AZALIA_PIN_CFG_NC(0)),
-	AZALIA_PIN_CFG(0, LINE1,	AZALIA_PIN_CFG_NC(0)),
-	AZALIA_PIN_CFG(0, LINE2,	AZALIA_PIN_CFG_NC(0)),
-	AZALIA_PIN_CFG(0, PC_BEEP,	AZALIA_PIN_CFG_NC(0)),
-	AZALIA_PIN_CFG(0, S_PDIF,	AZALIA_PIN_CFG_NC(0)),
+	/* Pin Widget Verb-table */
+	AZALIA_PIN_CFG(0, ALC269_DMIC12,	AZALIA_PIN_DESC(
+							AZALIA_INTEGRATED,
+							AZALIA_MOBILE_LID_INSIDE,
+							AZALIA_MIC_IN,
+							AZALIA_OTHER_DIGITAL,
+							AZALIA_COLOR_UNKNOWN,
+							AZALIA_NO_JACK_PRESENCE_DETECT,
+							3,
+							0
+						)),
+	AZALIA_PIN_CFG(0, ALC269_SPEAKERS,	AZALIA_PIN_DESC(
+							AZALIA_INTEGRATED,
+							AZALIA_INTERNAL | AZALIA_TOP,
+							AZALIA_SPEAKER,
+							AZALIA_OTHER_ANALOG,
+							AZALIA_COLOR_UNKNOWN,
+							AZALIA_NO_JACK_PRESENCE_DETECT,
+							1,
+							0
+						)),
+	AZALIA_PIN_CFG(0, ALC269_VC_HP_OUT,	AZALIA_PIN_DESC(
+							AZALIA_JACK,
+							AZALIA_EXTERNAL_PRIMARY_CHASSIS | AZALIA_RIGHT,
+							AZALIA_HP_OUT,
+							AZALIA_STEREO_MONO_1_8,
+							AZALIA_BLACK,
+							AZALIA_JACK_PRESENCE_DETECT,
+							2,
+							0
+						)),
+	AZALIA_PIN_CFG(0, ALC269_MIC1,		AZALIA_PIN_DESC(
+							AZALIA_JACK,
+							AZALIA_EXTERNAL_PRIMARY_CHASSIS | AZALIA_RIGHT,
+							AZALIA_MIC_IN,
+							AZALIA_STEREO_MONO_1_8,
+							AZALIA_BLACK,
+							AZALIA_JACK_PRESENCE_DETECT,
+							4,
+							0
+						)),
+	AZALIA_PIN_CFG(0, ALC269_MONO,		AZALIA_PIN_CFG_NC(0)),
+	AZALIA_PIN_CFG(0, ALC269_MIC2,		AZALIA_PIN_CFG_NC(0)),
+	AZALIA_PIN_CFG(0, ALC269_LINE1,		AZALIA_PIN_CFG_NC(0)),
+	AZALIA_PIN_CFG(0, ALC269_LINE2,		AZALIA_PIN_CFG_NC(0)),
+	AZALIA_PIN_CFG(0, ALC269_PC_BEEP,	AZALIA_PIN_CFG_NC(0)),
+	AZALIA_PIN_CFG(0, ALC269_SPDIF_OUT,	AZALIA_PIN_CFG_NC(0)),
+	AZALIA_PIN_CFG(0, ALC269_VB_HP_OUT,	AZALIA_PIN_CFG_NC(0)),
 
 	0x02050018,
 	0x02040184,
-
 	0x0205001C,
 	0x02044b00,
 
 	0x02050024,
 	0x02040000,
-
 	0x02050004,
 	0x02040080,
 
 	0x02050008,
 	0x02040000,
-
 	0x0205000C,
 	0x02043F00,
 
 	0x02050015,
 	0x02048002,
-
 	0x02050015,
 	0x02048002,
 
@@ -104,6 +89,7 @@ const u32 cim_verb_data[] = {
 	0x00D37080,
 	0x00370610,
 
+	/* Intel MTL IGD HDMI */
 	0x8086280d,	/* Codec Vendor / Device ID: Intel */
 	0x80860101,	/* Subsystem ID */
 	4,		/* Number of 4 dword sets */

From 15111ebb21b401ff38801fb5083b01e7a2c290ea Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Fri, 5 Sep 2025 13:15:40 -0500
Subject: [PATCH 2016/3886] mb/starlabs/starbook/rpl: Use macros for HDA verb
 table

Rework the HDA verb table using macros. Explicitly disable all
pin widgets not used. Use consistent formatting and verbiage in
comments.

TEST=build/boot Win11, Ubuntu 25.04 on Starbook RPL, verify all audio
inputs/outputs working as expected. Verify verbs loaded via cbmem log.

Change-Id: I4ccc604f7db4ec85d8e5f311c7f8fd5c913ec04b
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89082
Reviewed-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
---
 .../starlabs/starbook/variants/rpl/hda_verb.c | 75 ++++++++++++++-----
 1 file changed, 56 insertions(+), 19 deletions(-)

diff --git a/src/mainboard/starlabs/starbook/variants/rpl/hda_verb.c b/src/mainboard/starlabs/starbook/variants/rpl/hda_verb.c
index 507a0bcf8b..96b7a4d202 100644
--- a/src/mainboard/starlabs/starbook/variants/rpl/hda_verb.c
+++ b/src/mainboard/starlabs/starbook/variants/rpl/hda_verb.c
@@ -1,32 +1,68 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
 #include <device/azalia_device.h>
-#include <stdint.h>
+#include <device/azalia_codec/realtek.h>
 
 const u32 cim_verb_data[] = {
 	/* coreboot specific header */
-	0x10ec0269, /* Codec Vendor / Device ID: Realtek ALC269 */
-	0x1e507007, /* Subsystem ID */
-	17,	    /* Number of jacks (NID entries) */
+	0x10ec0269,	/* Codec Vendor / Device ID: Realtek ALC269 */
+	0x1e507007,	/* Subsystem ID */
+	17,		/* Number of verb entries */
 
 	/* Reset Codec First */
 	AZALIA_RESET(0x1),
 
-	/* HDA Codec Subsystem ID Verb-table */
+	/* HDA Codec Subsystem ID */
 	AZALIA_SUBVENDOR(0, 0x1e507007),
 
 	/* Pin Widget Verb-table */
-	AZALIA_PIN_CFG(0, 0x01, 0x00000000),
-	AZALIA_PIN_CFG(0, 0x12, 0x90a61120),
-	AZALIA_PIN_CFG(0, 0x14, 0x90171110),
-	AZALIA_PIN_CFG(0, 0x17, 0x40000000),
-	AZALIA_PIN_CFG(0, 0x18, 0x04a19030),
-	AZALIA_PIN_CFG(0, 0x19, 0x04ab1020),
-	AZALIA_PIN_CFG(0, 0x1a, AZALIA_PIN_CFG_NC(0)),
-	AZALIA_PIN_CFG(0, 0x1b, AZALIA_PIN_CFG_NC(0)),
-	AZALIA_PIN_CFG(0, 0x1d, AZALIA_PIN_CFG_NC(0)),
-	AZALIA_PIN_CFG(0, 0x1e, AZALIA_PIN_CFG_NC(0)),
-	AZALIA_PIN_CFG(0, 0x21, 0x042b1010),
+	AZALIA_PIN_CFG(0, ALC269_DMIC12,	AZALIA_PIN_DESC(
+							AZALIA_INTEGRATED,
+							AZALIA_MOBILE_LID_INSIDE,
+							AZALIA_MIC_IN,
+							AZALIA_OTHER_DIGITAL,
+							AZALIA_COLOR_UNKNOWN,
+							AZALIA_NO_JACK_PRESENCE_DETECT,
+							3,
+							0
+						)),
+	AZALIA_PIN_CFG(0, ALC269_SPEAKERS,	AZALIA_PIN_DESC(
+							AZALIA_INTEGRATED,
+							AZALIA_INTERNAL | AZALIA_TOP,
+							AZALIA_SPEAKER,
+							AZALIA_OTHER_ANALOG,
+							AZALIA_COLOR_UNKNOWN,
+							AZALIA_NO_JACK_PRESENCE_DETECT,
+							1,
+							0
+						)),
+	AZALIA_PIN_CFG(0, ALC269_MIC1,		AZALIA_PIN_DESC(
+							AZALIA_JACK,
+							AZALIA_EXTERNAL_PRIMARY_CHASSIS | AZALIA_RIGHT,
+							AZALIA_MIC_IN,
+							AZALIA_STEREO_MONO_1_8,
+							AZALIA_BLACK,
+							AZALIA_JACK_PRESENCE_DETECT,
+							4,
+							0
+						)),
+	AZALIA_PIN_CFG(0, ALC269_VB_HP_OUT,	AZALIA_PIN_DESC(
+							AZALIA_JACK,
+							AZALIA_EXTERNAL_PRIMARY_CHASSIS | AZALIA_RIGHT,
+							AZALIA_HP_OUT,
+							AZALIA_STEREO_MONO_1_8,
+							AZALIA_BLACK,
+							AZALIA_JACK_PRESENCE_DETECT,
+							2,
+							0
+						)),
+	AZALIA_PIN_CFG(0, ALC269_MONO,		AZALIA_PIN_CFG_NC(0)),
+	AZALIA_PIN_CFG(0, ALC269_VC_HP_OUT,	AZALIA_PIN_CFG_NC(0)),
+	AZALIA_PIN_CFG(0, ALC269_MIC2,		AZALIA_PIN_CFG_NC(0)),
+	AZALIA_PIN_CFG(0, ALC269_LINE1,		AZALIA_PIN_CFG_NC(0)),
+	AZALIA_PIN_CFG(0, ALC269_LINE2,		AZALIA_PIN_CFG_NC(0)),
+	AZALIA_PIN_CFG(0, ALC269_PC_BEEP,	AZALIA_PIN_CFG_NC(0)),
+	AZALIA_PIN_CFG(0, ALC269_SPDIF_OUT,	AZALIA_PIN_CFG_NC(0)),
 
 	/* ALC269 Default 1 */
 	0x02050011,
@@ -52,9 +88,10 @@ const u32 cim_verb_data[] = {
 	0x02050005,
 	0x020400c0,
 
-	0x80862815, /* Codec Vendor / Device ID: Intel */
-	0x80860101, /* Subsystem ID */
-	10,	    /* Number of 4 dword sets */
+	/* Intel RPL IGD HDMI */
+	0x80862815,	/* Codec Vendor / Device ID: Intel */
+	0x80860101,	/* Subsystem ID */
+	10,		/* Number of verb entries */
 
 	AZALIA_SUBVENDOR(2, 0x80860101),
 

From c30163daceb45858aaf5f3824f600d6bdf92696a Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Fri, 5 Sep 2025 11:03:41 -0500
Subject: [PATCH 2017/3886] mb/starlabs/starbook/tgl: Use macros for HDA verb
 table

Rework the HDA verb table using macros. Explicitly disable all
pin widgets not used. Use consistent formatting and verbiage in
comments. Update verb count. Add HDA verbs for Intel IGD HDMI audio
output.

TEST=build/boot Win11, ubuntu 25.04 on Starbook TGL, verify all audio
inputs/outputs function as expected. Verify verbs loaded via cbmem log.

Change-Id: Id9a08c8bd32e0c75f92e8d6b3b8ff6c033608a4f
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89083
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
---
 .../starlabs/starbook/variants/tgl/hda_verb.c | 73 +++++++++++++++----
 1 file changed, 58 insertions(+), 15 deletions(-)

diff --git a/src/mainboard/starlabs/starbook/variants/tgl/hda_verb.c b/src/mainboard/starlabs/starbook/variants/tgl/hda_verb.c
index 71b96231e5..60df1a44e2 100644
--- a/src/mainboard/starlabs/starbook/variants/tgl/hda_verb.c
+++ b/src/mainboard/starlabs/starbook/variants/tgl/hda_verb.c
@@ -1,31 +1,66 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
 #include <device/azalia_device.h>
+#include <device/azalia_codec/realtek.h>
 
 const u32 cim_verb_data[] = {
 	/* coreboot specific header */
-	0x10ec0256, /* Codec Vendor / Device ID: Realtek ALC256 */
-	0x10ec1200, /* Subsystem ID */
-	38,	    /* Number of jacks (NID entries) */
+	0x10ec0256,	/* Codec Vendor / Device ID: Realtek ALC256 */
+	0x10ec1200,	/* Subsystem ID */
+	36,		/* Number of verb entries */
 
 	/* Reset Codec First */
 	AZALIA_RESET(0x1),
 
-	/* HDA Codec Subsystem ID: 0x10EC1200 */
+	/* HDA Codec Subsystem ID */
 	AZALIA_SUBVENDOR(0, 0x10ec1200),
 
 	/* Pin Widget Verb-table */
-	AZALIA_PIN_CFG(0, 0x01, 0x00000000),
-	AZALIA_PIN_CFG(0, 0x12, 0x90a61120),
-	AZALIA_PIN_CFG(0, 0x13, 0x40000000),
-	AZALIA_PIN_CFG(0, 0x14, 0x90171110),
-	AZALIA_PIN_CFG(0, 0x18, AZALIA_PIN_CFG_NC(0)),
-	AZALIA_PIN_CFG(0, 0x19, 0x04ab1020),
-	AZALIA_PIN_CFG(0, 0x1a, AZALIA_PIN_CFG_NC(0)),
-	AZALIA_PIN_CFG(0, 0x1b, 0x40700001),
-	AZALIA_PIN_CFG(0, 0x1d, AZALIA_PIN_CFG_NC(0)),
-	AZALIA_PIN_CFG(0, 0x1e, AZALIA_PIN_CFG_NC(0)),
-	AZALIA_PIN_CFG(0, 0x21, 0x042b1010),
+	AZALIA_PIN_CFG(0, ALC256_DMIC12,	AZALIA_PIN_DESC(
+							AZALIA_INTEGRATED,
+							AZALIA_MOBILE_LID_INSIDE,
+							AZALIA_MIC_IN,
+							AZALIA_OTHER_DIGITAL,
+							AZALIA_COLOR_UNKNOWN,
+							AZALIA_NO_JACK_PRESENCE_DETECT,
+							3,
+							0
+						)),
+	AZALIA_PIN_CFG(0, ALC256_SPEAKERS,	AZALIA_PIN_DESC(
+							AZALIA_INTEGRATED,
+							AZALIA_INTERNAL | AZALIA_FRONT,
+							AZALIA_SPEAKER,
+							AZALIA_OTHER_ANALOG,
+							AZALIA_COLOR_UNKNOWN,
+							AZALIA_NO_JACK_PRESENCE_DETECT,
+							1,
+							0
+						)),
+	AZALIA_PIN_CFG(0, ALC256_MIC2,		AZALIA_PIN_DESC(
+							AZALIA_JACK,
+							AZALIA_EXTERNAL_PRIMARY_CHASSIS | AZALIA_RIGHT,
+							AZALIA_MIC_IN,
+							AZALIA_STEREO_MONO_1_8,
+							AZALIA_BLACK,
+							AZALIA_JACK_PRESENCE_DETECT,
+							2,
+							0
+						)),
+	AZALIA_PIN_CFG(0, ALC256_HP_OUT,	AZALIA_PIN_DESC(
+							AZALIA_JACK,
+							AZALIA_EXTERNAL_PRIMARY_CHASSIS | AZALIA_RIGHT,
+							AZALIA_HP_OUT,
+							AZALIA_STEREO_MONO_1_8,
+							AZALIA_BLACK,
+							AZALIA_JACK_PRESENCE_DETECT,
+							1,
+							0
+						)),
+	AZALIA_PIN_CFG(0, ALC256_DMIC34,	AZALIA_PIN_CFG_NC(0)),
+	AZALIA_PIN_CFG(0, ALC256_LINE1,		AZALIA_PIN_CFG_NC(0)),
+	AZALIA_PIN_CFG(0, ALC256_LINE2,		AZALIA_PIN_CFG_NC(0)),
+	AZALIA_PIN_CFG(0, ALC256_PC_BEEP,	AZALIA_PIN_CFG_NC(0)),
+	AZALIA_PIN_CFG(0, ALC256_SPDIF_OUT,	AZALIA_PIN_CFG_NC(0)),
 
 	/* Reset to D0 */
 	0x00170500,
@@ -204,6 +239,14 @@ const u32 cim_verb_data[] = {
 	0x0204EBC4,
 	0x02050020,
 	0x020451FF,
+
+	/* Intel TGL IGD HDMI */
+	0x80862812,	/* Codec Vendor / Device ID: Intel */
+	0x80860101,	/* Subsystem ID */
+	2,		/* Number of 4 dword sets */
+
+	AZALIA_SUBVENDOR(2, 0x80860101),
+	AZALIA_PIN_CFG(2, 0x04, 0x18560010),
 };
 
 const u32 pc_beep_verbs[] = {};

From ca8d6a75123a7bfddd0560ffb38f1ca0ea47582d Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Fri, 5 Sep 2025 17:18:11 -0500
Subject: [PATCH 2018/3886] mb/starlabs/starfighter/rpl: Use macros for HDA
 verb table

Rework the HDA verb table using macros. Explicitly disable all
pin widgets not used. Use consistent formatting and verbiage in
comments. Update the verb count.

TEST=build/boot Win11, Ubuntu 25.04 on Starfighter RPL, verify all audio
inputs/outputs working as expected. Verify verbs loaded via cbmem log.

Change-Id: I2b96318df4431bc155af5a8f92935900031e0bfa
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89084
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
---
 .../starfighter/variants/rpl/hda_verb.c       | 74 ++++++++++++++-----
 1 file changed, 56 insertions(+), 18 deletions(-)

diff --git a/src/mainboard/starlabs/starfighter/variants/rpl/hda_verb.c b/src/mainboard/starlabs/starfighter/variants/rpl/hda_verb.c
index d67676febc..93b3cbf3ac 100644
--- a/src/mainboard/starlabs/starfighter/variants/rpl/hda_verb.c
+++ b/src/mainboard/starlabs/starfighter/variants/rpl/hda_verb.c
@@ -1,30 +1,67 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
 #include <device/azalia_device.h>
+#include <device/azalia_codec/realtek.h>
 
 const u32 cim_verb_data[] = {
 	/* coreboot specific header */
-	0x10ec0256, /* Codec Vendor / Device ID: Realtek ALC256 */
-	0x10ec1200, /* Subsystem ID */
-	32,	/* Number of jacks (NID entries) */
+	0x10ec0256,	/* Codec Vendor / Device ID: Realtek ALC256 */
+	0x10ec1200,	/* Subsystem ID */
+	30,		/* Number of verb entries */
 
 	/* Reset Codec First */
 	AZALIA_RESET(0x1),
 
-	/* HDA Codec Subsystem ID: 0x10EC1200 */
+	/* HDA Codec Subsystem ID */
 	AZALIA_SUBVENDOR(0, 0x10ec1200),
 
-	AZALIA_PIN_CFG(0, 0x01, 0x00000000),
-	AZALIA_PIN_CFG(0, 0x12, 0x90a60130),
-	AZALIA_PIN_CFG(0, 0x13, 0x40000000),
-	AZALIA_PIN_CFG(0, 0x14, 0x411111f0),
-	AZALIA_PIN_CFG(0, 0x18, 0x411111f0),
-	AZALIA_PIN_CFG(0, 0x19, 0x04a19040),
-	AZALIA_PIN_CFG(0, 0x1a,	0x411111f0),
-	AZALIA_PIN_CFG(0, 0x1b, 0x90170110),
-	AZALIA_PIN_CFG(0, 0x1d, 0x40689a6d),
-	AZALIA_PIN_CFG(0, 0x1e, 0x411111f0),
-	AZALIA_PIN_CFG(0, 0x21, 0x04214020),
+	/* Pin Widget Verb-table */
+	AZALIA_PIN_CFG(0, ALC256_DMIC12,	AZALIA_PIN_DESC(
+							AZALIA_INTEGRATED,
+							AZALIA_MOBILE_LID_INSIDE,
+							AZALIA_MIC_IN,
+							AZALIA_OTHER_DIGITAL,
+							AZALIA_COLOR_UNKNOWN,
+							AZALIA_NO_JACK_PRESENCE_DETECT,
+							3,
+							0
+						)),
+	AZALIA_PIN_CFG(0, ALC256_MIC2,		AZALIA_PIN_DESC(
+							AZALIA_JACK,
+							AZALIA_EXTERNAL_PRIMARY_CHASSIS | AZALIA_RIGHT,
+							AZALIA_MIC_IN,
+							AZALIA_STEREO_MONO_1_8,
+							AZALIA_BLACK,
+							AZALIA_JACK_PRESENCE_DETECT,
+							4,
+							0
+						)),
+	/* Internal speakers are connected to LINE2 and external amps */
+	AZALIA_PIN_CFG(0, ALC256_LINE2,		AZALIA_PIN_DESC(
+							AZALIA_INTEGRATED,
+							AZALIA_INTERNAL | AZALIA_FRONT,
+							AZALIA_SPEAKER,
+							AZALIA_OTHER_ANALOG,
+							AZALIA_COLOR_UNKNOWN,
+							AZALIA_NO_JACK_PRESENCE_DETECT,
+							1,
+							0
+						)),
+	AZALIA_PIN_CFG(0, ALC256_HP_OUT,	AZALIA_PIN_DESC(
+							AZALIA_JACK,
+							AZALIA_EXTERNAL_PRIMARY_CHASSIS | AZALIA_RIGHT,
+							AZALIA_HP_OUT,
+							AZALIA_STEREO_MONO_1_8,
+							AZALIA_BLACK,
+							AZALIA_JACK_PRESENCE_DETECT,
+							2,
+							0
+						)),
+	AZALIA_PIN_CFG(0, ALC256_DMIC34,	AZALIA_PIN_CFG_NC(0)),
+	AZALIA_PIN_CFG(0, ALC256_SPEAKERS,	AZALIA_PIN_CFG_NC(0)),
+	AZALIA_PIN_CFG(0, ALC256_LINE1,		AZALIA_PIN_CFG_NC(0)),
+	AZALIA_PIN_CFG(0, ALC256_PC_BEEP,	AZALIA_PIN_CFG_NC(0)),
+	AZALIA_PIN_CFG(0, ALC256_SPDIF_OUT,	AZALIA_PIN_CFG_NC(0)),
 
 	/* Reset and Set LDO3 output to 1.2V */
 	0x0205001a,
@@ -162,9 +199,10 @@ const u32 cim_verb_data[] = {
 	0x02050020,
 	0x020451FF,
 
-	0x80862815, /* Codec Vendor / Device ID: Intel */
-	0x80860101, /* Subsystem ID */
-	10,	    /* Number of 4 dword sets */
+	/* Intel RPL IGD HDMI */
+	0x80862815,	/* Codec Vendor / Device ID: Intel */
+	0x80860101,	/* Subsystem ID */
+	10,		/* Number of verb entries */
 
 	AZALIA_SUBVENDOR(2, 0x80860101),
 

From 4ba1b615dbd95fe71027a39dfc51b0b875d77af5 Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Thu, 4 Sep 2025 18:08:57 -0500
Subject: [PATCH 2019/3886] mb/starlabs/starlite_adl: Use macros for HDA verb
 table

Rework the HDA verb table using macros. Explicitly disable all
pin widgets not used. Use consistent formatting and verbiage in
comments.

TEST=build/boot Win11, Ubuntu 25.04 on Starbook RPL, verify all audio
inputs/outputs working as expected. Verify verbs loaded via cbmem log.

Change-Id: I54fb60026de953db7dc85ee64823b9584af04a69
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89060
Reviewed-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 .../starlite_adl/variants/mk_v/hda_verb.c     | 61 +++++++++++++++----
 1 file changed, 50 insertions(+), 11 deletions(-)

diff --git a/src/mainboard/starlabs/starlite_adl/variants/mk_v/hda_verb.c b/src/mainboard/starlabs/starlite_adl/variants/mk_v/hda_verb.c
index 29546d894e..9e2ba5e53a 100644
--- a/src/mainboard/starlabs/starlite_adl/variants/mk_v/hda_verb.c
+++ b/src/mainboard/starlabs/starlite_adl/variants/mk_v/hda_verb.c
@@ -1,6 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
 #include <device/azalia_device.h>
+#include <device/azalia_codec/realtek.h>
 
 const u32 cim_verb_data[] = {
 	/* coreboot specific header */
@@ -15,17 +16,54 @@ const u32 cim_verb_data[] = {
 	AZALIA_SUBVENDOR(0, 0x1e507038),
 
 	/* Pin Widget Verb-table */
-	AZALIA_PIN_CFG(0, 0x01, 0x00000000),
-	AZALIA_PIN_CFG(0, 0x12, 0x90a60130),
-	AZALIA_PIN_CFG(0, 0x14, 0x90170110),
-	AZALIA_PIN_CFG(0, 0x15, 0x04214020),
-	AZALIA_PIN_CFG(0, 0x17, 0x40000000),
-	AZALIA_PIN_CFG(0, 0x18, 0x04a19040),
-	AZALIA_PIN_CFG(0, 0x19, 0x011111f0),
-	AZALIA_PIN_CFG(0, 0x1a, 0x411111f0),
-	AZALIA_PIN_CFG(0, 0x1b, 0x411111f0),
-	AZALIA_PIN_CFG(0, 0x1d, 0x40e38205),
-	AZALIA_PIN_CFG(0, 0x1e, 0x411111f0),
+	AZALIA_PIN_CFG(0, ALC269_DMIC12,	AZALIA_PIN_DESC(
+							AZALIA_INTEGRATED,
+							AZALIA_INTERNAL | AZALIA_FRONT,
+							AZALIA_MIC_IN,
+							AZALIA_OTHER_DIGITAL,
+							AZALIA_COLOR_UNKNOWN,
+							AZALIA_NO_JACK_PRESENCE_DETECT,
+							3,
+							0
+						)),
+
+	AZALIA_PIN_CFG(0, ALC269_SPEAKERS,	AZALIA_PIN_DESC(
+							AZALIA_INTEGRATED,
+							AZALIA_INTERNAL | AZALIA_FRONT,
+							AZALIA_SPEAKER,
+							AZALIA_OTHER_ANALOG,
+							AZALIA_COLOR_UNKNOWN,
+							AZALIA_NO_JACK_PRESENCE_DETECT,
+							1,
+							0
+						)),
+	AZALIA_PIN_CFG(0, ALC269_VC_HP_OUT,	AZALIA_PIN_DESC(
+							AZALIA_JACK,
+							AZALIA_EXTERNAL_PRIMARY_CHASSIS | AZALIA_RIGHT,
+							AZALIA_HP_OUT,
+							AZALIA_STEREO_MONO_1_8,
+							AZALIA_BLACK,
+							AZALIA_JACK_PRESENCE_DETECT,
+							2,
+							0
+						)),
+	AZALIA_PIN_CFG(0, ALC269_MIC1,		AZALIA_PIN_DESC(
+							AZALIA_JACK,
+							AZALIA_EXTERNAL_PRIMARY_CHASSIS | AZALIA_RIGHT,
+							AZALIA_MIC_IN,
+							AZALIA_STEREO_MONO_1_8,
+							AZALIA_BLACK,
+							AZALIA_JACK_PRESENCE_DETECT,
+							4,
+							0
+						)),
+	AZALIA_PIN_CFG(0, ALC269_MONO,		AZALIA_PIN_CFG_NC(0)),
+	AZALIA_PIN_CFG(0, ALC269_MIC2,		AZALIA_PIN_CFG_NC(0)),
+	AZALIA_PIN_CFG(0, ALC269_LINE1,		AZALIA_PIN_CFG_NC(0)),
+	AZALIA_PIN_CFG(0, ALC269_LINE2,		AZALIA_PIN_CFG_NC(0)),
+	AZALIA_PIN_CFG(0, ALC269_PC_BEEP,	AZALIA_PIN_CFG_NC(0)),
+	AZALIA_PIN_CFG(0, ALC269_SPDIF_OUT,	AZALIA_PIN_CFG_NC(0)),
+	AZALIA_PIN_CFG(0, ALC269_VB_HP_OUT,	AZALIA_PIN_CFG_NC(0)),
 
 	/* ALC269 Default 1 */
 	0x02050018,
@@ -53,6 +91,7 @@ const u32 cim_verb_data[] = {
 	0x00d37080,
 	0x00370610,
 
+	/* Intel ADL-N IGD HDMI */
 	0x8086280d,	/* Codec Vendor / Device ID: Intel */
 	0x80860101,	/* Subsystem ID */
 	4,		/* Number of 4 dword sets */

From 092fca321082df584f4caab5add0cc7ce559a967 Mon Sep 17 00:00:00 2001
From: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Date: Thu, 4 Sep 2025 16:01:31 +0800
Subject: [PATCH 2020/3886] mb/google/fatcat/var/kinmen: Add support ALC1320
 Smart Amp

Enable Realtek ALC1320 as speaker Amplifier.
Use ALC721 as codec and ALC1320 as Amplifier on SoundWire Link 3.

BUG=b:435094908
TEST=emerge-fatcat coreboot
1. Set fw_config AUDIO bits to AUDIO_ALC1320_ALC721_SNDW
2. Check the SSDT.dsl:
   PCI0.HDAS.SNDW including 0x000331025D072101 & 0x000332025D132001

Change-Id: I82c0fb014c4b5ee5eec378acf0843893dd7aa2ac
Signed-off-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89036
Reviewed-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/google/fatcat/Kconfig             |  1 +
 .../fatcat/variants/kinmen/overridetree.cb      | 17 +++++++++++++++--
 2 files changed, 16 insertions(+), 2 deletions(-)

diff --git a/src/mainboard/google/fatcat/Kconfig b/src/mainboard/google/fatcat/Kconfig
index 7b83976ba6..ff26903a46 100644
--- a/src/mainboard/google/fatcat/Kconfig
+++ b/src/mainboard/google/fatcat/Kconfig
@@ -76,6 +76,7 @@ config BOARD_GOOGLE_MODEL_FELINO
 config BOARD_GOOGLE_MODEL_KINMEN
 	def_bool n
 	select BOARD_GOOGLE_BASEBOARD_FATCAT
+	select DRIVERS_SOUNDWIRE_ALC1320
 	select FSP_UGOP_EARLY_SIGN_OF_LIFE
 	select HAVE_SLP_S0_GATE
 	select MAINBOARD_HAS_GOOGLE_STRAUSS_KEYBOARD
diff --git a/src/mainboard/google/fatcat/variants/kinmen/overridetree.cb b/src/mainboard/google/fatcat/variants/kinmen/overridetree.cb
index 18a506700f..b06207f9ed 100644
--- a/src/mainboard/google/fatcat/variants/kinmen/overridetree.cb
+++ b/src/mainboard/google/fatcat/variants/kinmen/overridetree.cb
@@ -3,8 +3,9 @@ fw_config
 		option WIFI_CNVI_7		0
 	end
 	field AUDIO 3 5
-		option AUDIO_UNKNOWN		0
-		option AUDIO_ALC721_SNDW	1
+		option AUDIO_UNKNOWN				0
+		option AUDIO_ALC721_SNDW			1
+		option AUDIO_ALC1320_ALC721_SNDW	2
 	end
 	field FPMCU 6 7
 		option FP_ABSENT		0
@@ -374,6 +375,7 @@ chip soc/intel/pantherlake
 		device ref smbus on end
 		device ref hda on
 			probe AUDIO AUDIO_ALC721_SNDW
+			probe AUDIO AUDIO_ALC1320_ALC721_SNDW
 			chip drivers/intel/soundwire
 				device generic 0 on
 					chip drivers/soundwire/alc711
@@ -384,8 +386,19 @@ chip soc/intel/pantherlake
 						# SoundWire Link 3 ID 1
 						device generic 3.1 on
 							probe AUDIO AUDIO_ALC721_SNDW
+							probe AUDIO AUDIO_ALC1320_ALC721_SNDW
 						end
 					end
+					chip drivers/soundwire/alc1320
+						register "desc" = ""Speaker Amp""
+						register "alc1320_address.version" = "SOUNDWIRE_VERSION_1_2"
+						register "alc1320_address.class" = "MIPI_CLASS_SDCA"
+						register "alc1320_address.part_id" = "MIPI_DEV_ID_REALTEK_ALC1320"
+						# SoundWire Link 3 ID 2
+						device generic 3.2 on
+							probe AUDIO AUDIO_ALC1320_ALC721_SNDW
+						end # ALC1320 Smart Amp
+					end
 				end
 			end
 		end

From be3148575e4e171c37c07d47c1aa7c40ca399dfa Mon Sep 17 00:00:00 2001
From: Avi Uday <aviuday@google.com>
Date: Mon, 25 Aug 2025 18:13:30 +0530
Subject: [PATCH 2021/3886] mainboard/google/ocelot: Set OEM footer logo bottom
 margin

Apply a `logo_bottom_margin` of 100 pixels to the `common_soc_config`
for Ocelot. This configures the OEM footer logo to be rendered 100
pixels above the bottom edge of the screen.

Change-Id: Ia7436ab267f91771ee2c0e91743ddaf43280cc87
Signed-off-by: Avi Uday <aviuday@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88936
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Pranava Y N <pranavayn@google.com>
---
 src/mainboard/google/ocelot/variants/ocelot/overridetree.cb | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/src/mainboard/google/ocelot/variants/ocelot/overridetree.cb b/src/mainboard/google/ocelot/variants/ocelot/overridetree.cb
index 510d8aeb95..c83925326c 100644
--- a/src/mainboard/google/ocelot/variants/ocelot/overridetree.cb
+++ b/src/mainboard/google/ocelot/variants/ocelot/overridetree.cb
@@ -112,6 +112,8 @@ chip soc/intel/pantherlake
 	#| I2C5              | Touchpad                  |
 	#+-------------------+---------------------------+
 	register "common_soc_config" = "{
+		/* Render OEM footer logo 100px above from the edge */
+		.logo_bottom_margin = 100,
 		.chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT,
 		.i2c[1] = {
 			.speed = I2C_SPEED_FAST,

From f3a49c8b3d54e66ae6a7bb68d31cfce5a5693fdf Mon Sep 17 00:00:00 2001
From: Avi Uday <aviuday@google.com>
Date: Mon, 25 Aug 2025 18:40:29 +0530
Subject: [PATCH 2022/3886] mb/google/ocelot/var/ocelot: Disable audio for
 invalid Audio FW_CONFIG

This commit modifies the Ocelot mainboard configuration to ensure the
Audio controller is only enabled when a valid `FW_CONFIG` is selected.

This change introduces audio probe statements that allow the
system to boot successfully even if `FW_CONFIG` is set to
`AUDIO_UNKNOWN`, effectively disabling the audio controller in such
cases.

This prevents potential boot failures when an unsupported or unknown
audio codec is selected, improving system robustness.

BUG=b:412736286
TEST=Verify that ocelot builds without any error
Change-Id: I7c125c67b70a0e0f3df3629cb0002bfdaa57fdc9
Signed-off-by: Avi Uday <aviuday@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88938
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Pranava Y N <pranavayn@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/google/ocelot/variants/ocelot/overridetree.cb | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/src/mainboard/google/ocelot/variants/ocelot/overridetree.cb b/src/mainboard/google/ocelot/variants/ocelot/overridetree.cb
index c83925326c..59273e4bd3 100644
--- a/src/mainboard/google/ocelot/variants/ocelot/overridetree.cb
+++ b/src/mainboard/google/ocelot/variants/ocelot/overridetree.cb
@@ -559,6 +559,9 @@ chip soc/intel/pantherlake
 
 		device ref smbus on end
 		device ref hda on
+			probe AUDIO AUDIO_ALC721_SNDW
+			probe AUDIO AUDIO_ALC256_HDA
+			probe AUDIO AUDIO_MAX98360_ALC5682I_I2S
 			chip drivers/intel/soundwire
 				device generic 0 on
 					chip drivers/soundwire/alc711

From 883103c77f16a070a7d92ee20a4089edf8d16e48 Mon Sep 17 00:00:00 2001
From: Avi Uday <aviuday@google.com>
Date: Mon, 25 Aug 2025 19:25:45 +0530
Subject: [PATCH 2023/3886] mb/google/ocelot: Disable memory training progress
 bar

Set disable_progress_bar to disable the memory progress bar for ocelot
board as this is an OEM feature and might not be used by all.

TEST=Verify that ocelot builds without any error
Change-Id: Ifef7a2645dce696f32cea42fd928a1f858fd0333
Signed-off-by: Avi Uday <aviuday@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88941
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Pranava Y N <pranavayn@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
---
 .../google/ocelot/variants/baseboard/ocelot/devicetree.cb       | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/src/mainboard/google/ocelot/variants/baseboard/ocelot/devicetree.cb b/src/mainboard/google/ocelot/variants/baseboard/ocelot/devicetree.cb
index 18708eb7f4..75c7641552 100644
--- a/src/mainboard/google/ocelot/variants/baseboard/ocelot/devicetree.cb
+++ b/src/mainboard/google/ocelot/variants/baseboard/ocelot/devicetree.cb
@@ -91,6 +91,8 @@ chip soc/intel/pantherlake
 	register "pch_hda_idisp_link_frequency" = "HDA_LINKFREQ_96MHZ"
 	register "pch_hda_idisp_codec_enable" = "true"
 
+	register "disable_progress_bar" = "true"
+
 	device domain 0 on
 		device ref dtt on end
 		device ref npu on end

From 258da6b1ef9c26fd03be67974794b2030365c0df Mon Sep 17 00:00:00 2001
From: Nick Vaccaro <nvaccaro@google.com>
Date: Fri, 12 Sep 2025 16:26:46 -0700
Subject: [PATCH 2024/3886] mb/goog/ocelot/var/ocelot: add H58G66BK7BX067
 memory option

Add H58G66BK7BX067 memory part as DRAM ID 1.

BUG=b:443646405
TEST=None

Change-Id: I3ab13e65b94dd4b46ed788df31085c9013d84848
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89158
Reviewed-by: Avi Uday <aviuday@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Appukuttan V K <appukuttan.vk@intel.com>
Reviewed-by: Pranava Y N <pranavayn@google.com>
---
 src/mainboard/google/ocelot/variants/ocelot/memory/Makefile.mk   | 1 +
 .../google/ocelot/variants/ocelot/memory/dram_id.generated.txt   | 1 +
 .../google/ocelot/variants/ocelot/memory/mem_parts_used.txt      | 1 +
 3 files changed, 3 insertions(+)

diff --git a/src/mainboard/google/ocelot/variants/ocelot/memory/Makefile.mk b/src/mainboard/google/ocelot/variants/ocelot/memory/Makefile.mk
index 2059568629..dd0d2ca609 100644
--- a/src/mainboard/google/ocelot/variants/ocelot/memory/Makefile.mk
+++ b/src/mainboard/google/ocelot/variants/ocelot/memory/Makefile.mk
@@ -5,3 +5,4 @@
 
 SPD_SOURCES =
 SPD_SOURCES += spd/lp5/set-0/spd-11.hex      # ID = 0(0b0000)  Parts = H58G56BK8BX068
+SPD_SOURCES += spd/lp5/set-0/spd-8.hex      # ID = 1(0b0001)  Parts = H58G66BK7BX067
diff --git a/src/mainboard/google/ocelot/variants/ocelot/memory/dram_id.generated.txt b/src/mainboard/google/ocelot/variants/ocelot/memory/dram_id.generated.txt
index c7351b2c76..591cb7650f 100644
--- a/src/mainboard/google/ocelot/variants/ocelot/memory/dram_id.generated.txt
+++ b/src/mainboard/google/ocelot/variants/ocelot/memory/dram_id.generated.txt
@@ -5,3 +5,4 @@
 
 DRAM Part Name                 ID to assign
 H58G56BK8BX068                 0 (0000)
+H58G66BK7BX067                 1 (0001)
diff --git a/src/mainboard/google/ocelot/variants/ocelot/memory/mem_parts_used.txt b/src/mainboard/google/ocelot/variants/ocelot/memory/mem_parts_used.txt
index ae8eff2d96..4b06f23814 100644
--- a/src/mainboard/google/ocelot/variants/ocelot/memory/mem_parts_used.txt
+++ b/src/mainboard/google/ocelot/variants/ocelot/memory/mem_parts_used.txt
@@ -10,3 +10,4 @@
 
 # Part Name
 H58G56BK8BX068
+H58G66BK7BX067

From 684530ebdcac2b4fe722492b273f0844980d93b0 Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Wed, 10 Sep 2025 10:02:54 -0500
Subject: [PATCH 2025/3886] mb/starlabs/starbook/adl: Drop HDMI entries from
 verb table

These are not programmed by coreboot, so drop them.

Change-Id: I577634eef5e0f218be81323bbd5c6d8a0651549c
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89134
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 .../starlabs/starbook/variants/adl/hda_verb.c   | 17 -----------------
 1 file changed, 17 deletions(-)

diff --git a/src/mainboard/starlabs/starbook/variants/adl/hda_verb.c b/src/mainboard/starlabs/starbook/variants/adl/hda_verb.c
index 662d268727..37b8a42346 100644
--- a/src/mainboard/starlabs/starbook/variants/adl/hda_verb.c
+++ b/src/mainboard/starlabs/starbook/variants/adl/hda_verb.c
@@ -87,23 +87,6 @@ const u32 cim_verb_data[] = {
 	0x020400af,
 	0x02050005,
 	0x020400c0,
-
-	/* Intel ADL IGD HDMI */
-	0x80862815,	/* Codec Vendor / Device ID: Intel */
-	0x80860101,	/* Subsystem ID */
-	10,		/* Number of verb entries */
-
-	AZALIA_SUBVENDOR(2, 0x80860101),
-
-	AZALIA_PIN_CFG(2, 0x04, 0x18560010),
-	AZALIA_PIN_CFG(2, 0x06, 0x18560010),
-	AZALIA_PIN_CFG(2, 0x08, 0x18561010),
-	AZALIA_PIN_CFG(2, 0x0a, 0x18561010),
-	AZALIA_PIN_CFG(2, 0x0b, 0x18561010),
-	AZALIA_PIN_CFG(2, 0x0c, 0x18561010),
-	AZALIA_PIN_CFG(2, 0x0d, 0x18561010),
-	AZALIA_PIN_CFG(2, 0x0e, 0x18561010),
-	AZALIA_PIN_CFG(2, 0x0f, 0x18560010),
 };
 
 const u32 pc_beep_verbs[] = {};

From 90f94287fdcffb1c497ea5fe7924143a537653b7 Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Wed, 10 Sep 2025 10:02:13 -0500
Subject: [PATCH 2026/3886] mb/starlabs/starbook/adl_n: Drop HDMI entries from
 verb table

These are not programmed by coreboot, so drop them.

Change-Id: If1c68f183012d78b3e8847e8fe103280fe0103ec
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89135
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
---
 .../starlabs/starbook/variants/adl_n/hda_verb.c       | 11 -----------
 1 file changed, 11 deletions(-)

diff --git a/src/mainboard/starlabs/starbook/variants/adl_n/hda_verb.c b/src/mainboard/starlabs/starbook/variants/adl_n/hda_verb.c
index 53c7cd8d6b..45c631ea2a 100644
--- a/src/mainboard/starlabs/starbook/variants/adl_n/hda_verb.c
+++ b/src/mainboard/starlabs/starbook/variants/adl_n/hda_verb.c
@@ -88,17 +88,6 @@ const u32 cim_verb_data[] = {
 	0x00270610,
 	0x00D37080,
 	0x00370610,
-
-	/* Intel ADL-N IGD HDMI */
-	0x8086280d,	/* Codec Vendor / Device ID: Intel */
-	0x80860101,	/* Subsystem ID */
-	4,		/* Number of 4 dword sets */
-
-	AZALIA_SUBVENDOR(2, 0x80860101),
-
-	AZALIA_PIN_CFG(2, 0x05, 0x18560010),
-	AZALIA_PIN_CFG(2, 0x06, 0x18560020),
-	AZALIA_PIN_CFG(2, 0x07, 0x18560030),
 };
 
 const u32 pc_beep_verbs[] = {

From a88d9e1033d8ab585ce88e6a1f7fc9214d1e96f1 Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Wed, 10 Sep 2025 10:00:40 -0500
Subject: [PATCH 2027/3886] mb/starlabs/starbook/mtl: Drop HDMI entries from
 verb table

These are not programmed by coreboot, so drop them.

Change-Id: Ifdcbb52cf1823692296775895130fcec8be59c85
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89136
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
---
 .../starlabs/starbook/variants/mtl/hda_verb.c         | 11 -----------
 1 file changed, 11 deletions(-)

diff --git a/src/mainboard/starlabs/starbook/variants/mtl/hda_verb.c b/src/mainboard/starlabs/starbook/variants/mtl/hda_verb.c
index 64d7754120..d4592edb23 100644
--- a/src/mainboard/starlabs/starbook/variants/mtl/hda_verb.c
+++ b/src/mainboard/starlabs/starbook/variants/mtl/hda_verb.c
@@ -88,17 +88,6 @@ const u32 cim_verb_data[] = {
 	0x00270610,
 	0x00D37080,
 	0x00370610,
-
-	/* Intel MTL IGD HDMI */
-	0x8086280d,	/* Codec Vendor / Device ID: Intel */
-	0x80860101,	/* Subsystem ID */
-	4,		/* Number of 4 dword sets */
-
-	AZALIA_SUBVENDOR(2, 0x80860101),
-
-	AZALIA_PIN_CFG(2, 0x05, 0x18560010),
-	AZALIA_PIN_CFG(2, 0x06, 0x18560020),
-	AZALIA_PIN_CFG(2, 0x07, 0x18560030),
 };
 
 const u32 pc_beep_verbs[] = {

From fc3a64757909906196fcd6305a4226958c911918 Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Wed, 10 Sep 2025 09:59:44 -0500
Subject: [PATCH 2028/3886] mb/starlabs/starbook/rpl: Drop HDMI entries from
 verb table

These are not programmed by coreboot, so drop them.

Change-Id: I1ad4f33565ce1d5a67ac7f066fd5140a7cb2faf8
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89137
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
---
 .../starlabs/starbook/variants/rpl/hda_verb.c   | 17 -----------------
 1 file changed, 17 deletions(-)

diff --git a/src/mainboard/starlabs/starbook/variants/rpl/hda_verb.c b/src/mainboard/starlabs/starbook/variants/rpl/hda_verb.c
index 96b7a4d202..c4864ac3dd 100644
--- a/src/mainboard/starlabs/starbook/variants/rpl/hda_verb.c
+++ b/src/mainboard/starlabs/starbook/variants/rpl/hda_verb.c
@@ -87,23 +87,6 @@ const u32 cim_verb_data[] = {
 	0x020400af,
 	0x02050005,
 	0x020400c0,
-
-	/* Intel RPL IGD HDMI */
-	0x80862815,	/* Codec Vendor / Device ID: Intel */
-	0x80860101,	/* Subsystem ID */
-	10,		/* Number of verb entries */
-
-	AZALIA_SUBVENDOR(2, 0x80860101),
-
-	AZALIA_PIN_CFG(2, 0x04, 0x18560010),
-	AZALIA_PIN_CFG(2, 0x06, 0x18560010),
-	AZALIA_PIN_CFG(2, 0x08, 0x18561010),
-	AZALIA_PIN_CFG(2, 0x0a, 0x18561010),
-	AZALIA_PIN_CFG(2, 0x0b, 0x18561010),
-	AZALIA_PIN_CFG(2, 0x0c, 0x18561010),
-	AZALIA_PIN_CFG(2, 0x0d, 0x18561010),
-	AZALIA_PIN_CFG(2, 0x0e, 0x18561010),
-	AZALIA_PIN_CFG(2, 0x0f, 0x18560010),
 };
 
 const u32 pc_beep_verbs[] = {};

From 461c6a7d31070ce4975a182a7cb08f8e3277e980 Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Wed, 10 Sep 2025 09:57:59 -0500
Subject: [PATCH 2029/3886] mb/starlabs/starfighter/rpl: Drop HDMI entries from
 verb table

These are not programmed by coreboot, so drop them.

Change-Id: Id3f870c531f0cfd078c899953ff65b406e7e5bb6
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89138
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 .../starfighter/variants/rpl/hda_verb.c         | 17 -----------------
 1 file changed, 17 deletions(-)

diff --git a/src/mainboard/starlabs/starfighter/variants/rpl/hda_verb.c b/src/mainboard/starlabs/starfighter/variants/rpl/hda_verb.c
index 93b3cbf3ac..995fb75a93 100644
--- a/src/mainboard/starlabs/starfighter/variants/rpl/hda_verb.c
+++ b/src/mainboard/starlabs/starfighter/variants/rpl/hda_verb.c
@@ -198,23 +198,6 @@ const u32 cim_verb_data[] = {
 	0x0204EBC4,
 	0x02050020,
 	0x020451FF,
-
-	/* Intel RPL IGD HDMI */
-	0x80862815,	/* Codec Vendor / Device ID: Intel */
-	0x80860101,	/* Subsystem ID */
-	10,		/* Number of verb entries */
-
-	AZALIA_SUBVENDOR(2, 0x80860101),
-
-	AZALIA_PIN_CFG(2, 0x04, 0x18560010),
-	AZALIA_PIN_CFG(2, 0x06, 0x18560010),
-	AZALIA_PIN_CFG(2, 0x08, 0x18561010),
-	AZALIA_PIN_CFG(2, 0x0a, 0x18561010),
-	AZALIA_PIN_CFG(2, 0x0b, 0x18561010),
-	AZALIA_PIN_CFG(2, 0x0c, 0x18561010),
-	AZALIA_PIN_CFG(2, 0x0d, 0x18561010),
-	AZALIA_PIN_CFG(2, 0x0e, 0x18561010),
-	AZALIA_PIN_CFG(2, 0x0f, 0x18560010),
 };
 
 const u32 pc_beep_verbs[] = {};

From b9af91dfe1160ede3c2f12d1f4e59ff64c4def75 Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Wed, 10 Sep 2025 10:03:45 -0500
Subject: [PATCH 2030/3886] mb/starlabs/starlite_adl: Drop HDMI entries from
 verb table

These are not programmed by coreboot, so drop them.

Change-Id: If7b371aa6f64a7f034344a6e926ca0662fa717c2
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89139
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
---
 .../starlabs/starlite_adl/variants/mk_v/hda_verb.c    | 11 -----------
 1 file changed, 11 deletions(-)

diff --git a/src/mainboard/starlabs/starlite_adl/variants/mk_v/hda_verb.c b/src/mainboard/starlabs/starlite_adl/variants/mk_v/hda_verb.c
index 9e2ba5e53a..24d23ae55d 100644
--- a/src/mainboard/starlabs/starlite_adl/variants/mk_v/hda_verb.c
+++ b/src/mainboard/starlabs/starlite_adl/variants/mk_v/hda_verb.c
@@ -90,17 +90,6 @@ const u32 cim_verb_data[] = {
 	0x00270610,
 	0x00d37080,
 	0x00370610,
-
-	/* Intel ADL-N IGD HDMI */
-	0x8086280d,	/* Codec Vendor / Device ID: Intel */
-	0x80860101,	/* Subsystem ID */
-	4,		/* Number of 4 dword sets */
-
-	AZALIA_SUBVENDOR(2, 0x80860101),
-
-	AZALIA_PIN_CFG(2, 0x05, 0x18560010),
-	AZALIA_PIN_CFG(2, 0x06, 0x18560020),
-	AZALIA_PIN_CFG(2, 0x07, 0x18560030),
 };
 
 const u32 pc_beep_verbs[] = {

From 858559159604d2af139ebddf836103afd0e16414 Mon Sep 17 00:00:00 2001
From: Subrata Banik <subratabanik@google.com>
Date: Fri, 12 Sep 2025 09:49:10 +0000
Subject: [PATCH 2031/3886] mb/google/fatcat/var/lapis: Set GPP_A15 as not used

The GPP_A15 pin on the Fatcat mainboard variant Lapis is not used,
according to schematics dated 08/30.

Update the GPIO table to reflect this and explicitly set the pin to
not connected (NC).

TEST=Able to build google/lapis.

Change-Id: Ib89421952f5844283809fe99a902e36a17f55fae
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89154
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
---
 src/mainboard/google/fatcat/variants/lapis/gpio.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/mainboard/google/fatcat/variants/lapis/gpio.c b/src/mainboard/google/fatcat/variants/lapis/gpio.c
index faaa5e0d5b..ea6c89f7dd 100644
--- a/src/mainboard/google/fatcat/variants/lapis/gpio.c
+++ b/src/mainboard/google/fatcat/variants/lapis/gpio.c
@@ -40,8 +40,8 @@ static const struct pad_config gpio_table[] = {
 	PAD_NC(GPP_A12, NONE),
 	/* GPP_A13:     MEM_STRAP_0 */
 	PAD_CFG_GPI(GPP_A13, NONE, DEEP),
-	/* GPP_A15:     GPP_A15_DNX_FORCE_RELOAD ==> EPD_ON_GCD_OUT*/ /* NC */
-	/* PAD_CFG_NF(GPP_A15, NONE, DEEP, NF1), */
+	/* GPP_A15:     Not used */
+	PAD_NC(GPP_A15, NONE),
 	/* GPP_A16:     BT_DISABLE_L ==> BT_ON_WLAN */
 	PAD_CFG_GPO(GPP_A16, 1, DEEP),
 	/* GPP_A17:     WIFI_DISABLE_L ==> WLAN_ON_PCH */

From 3639648f8153c3dba99103716151fe5d576115a3 Mon Sep 17 00:00:00 2001
From: Subrata Banik <subratabanik@google.com>
Date: Fri, 12 Sep 2025 10:00:04 +0000
Subject: [PATCH 2032/3886] mb/google/fatcat/var/felino: Set GPP_A15 and
 GPP_B23 as not used

GPP_B23 and GPP_A15 GPIOs in Felino design being used for MEM
straping selection but Felino supports only one mem id (index 0)
hence, these GPIO reads were never needed in felino code.

The GPP_A15 and GPP_B23 pins on the Fatcat mainboard variant Felino
are no longer used. Update the GPIO table to reflect this and
explicitly set the pins to not connected (NC) as per schematics
dated 08/30.

TEST=Able to build and boot google/felino.

Change-Id: I9d8ed19aab612f7104227544c24c37d19024cfb0
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89155
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
---
 src/mainboard/google/fatcat/variants/felino/gpio.c | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/src/mainboard/google/fatcat/variants/felino/gpio.c b/src/mainboard/google/fatcat/variants/felino/gpio.c
index 8b05f1dfc8..3a82f97155 100644
--- a/src/mainboard/google/fatcat/variants/felino/gpio.c
+++ b/src/mainboard/google/fatcat/variants/felino/gpio.c
@@ -40,8 +40,8 @@ static const struct pad_config gpio_table[] = {
 	PAD_CFG_GPI_SCI_LOW(GPP_A12, NONE, DEEP, LEVEL),
 	/* GPP_A13:     Not used */
 	PAD_NC(GPP_A13, NONE),
-	/* GPP_A15:     HW_ID1 */
-	PAD_CFG_GPI(GPP_A15, NONE, PLTRST),
+	/* GPP_A15:     Not used */
+	PAD_NC(GPP_A15, NONE),
 	/* GPP_A16:     BT_RF_KILL_N */
 	PAD_CFG_GPO(GPP_A16, 1, DEEP),
 	/* GPP_A17:     PCH_WLAN_OFF_N */
@@ -93,8 +93,8 @@ static const struct pad_config gpio_table[] = {
 	PAD_CFG_GPO(GPP_B21, 0, DEEP),
 	/* GPP_B22:     Not used */
 	PAD_NC(GPP_B22, NONE),
-	/* GPP_B23:     HW_ID0 */
-	PAD_CFG_GPI(GPP_B23, NONE, PLTRST),
+	/* GPP_B23:     Not used */
+	PAD_NC(GPP_B23, NONE),
 	/* GPP_B24:     ESPI_ALERT0_N */
 	PAD_CFG_NF_IOSSTATE(GPP_B24, UP_20K, DEEP, NF1, IGNORE),
 	/* GPP_B25:     Not used */

From 16db59ccef2b2a84ed02f9762d531d3a7d245d03 Mon Sep 17 00:00:00 2001
From: David Wu <david_wu@quanta.corp-partner.google.com>
Date: Fri, 12 Sep 2025 19:05:30 +0800
Subject: [PATCH 2033/3886] mb/google/rex/var/karis: Add K3KL8L80EM-MGCU to RAM
 ID table

Add the new memory support: Samsung K3KL8L80EM-MGCU

BUG=b:412311178
TEST=Run part_id_gen tool and check the generated files.

Change-Id: Id46274ddac59df887be5580853c03ac34ef790b6
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89156
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/google/rex/variants/karis/memory/Makefile.mk      | 2 +-
 .../google/rex/variants/karis/memory/dram_id.generated.txt      | 1 +
 .../google/rex/variants/karis/memory/mem_parts_used.txt         | 1 +
 3 files changed, 3 insertions(+), 1 deletion(-)

diff --git a/src/mainboard/google/rex/variants/karis/memory/Makefile.mk b/src/mainboard/google/rex/variants/karis/memory/Makefile.mk
index b56247ea44..45f30a7e89 100644
--- a/src/mainboard/google/rex/variants/karis/memory/Makefile.mk
+++ b/src/mainboard/google/rex/variants/karis/memory/Makefile.mk
@@ -4,7 +4,7 @@
 # util/spd_tools/bin/part_id_gen MTL lp5 src/mainboard/google/rex/variants/karis/memory src/mainboard/google/rex/variants/karis/memory/mem_parts_used.txt
 
 SPD_SOURCES =
-SPD_SOURCES += spd/lp5/set-0/spd-11.hex      # ID = 0(0b0000)  Parts = MT62F1G32D2DS-023 WT:B, H58G56BK8BX068
+SPD_SOURCES += spd/lp5/set-0/spd-11.hex      # ID = 0(0b0000)  Parts = MT62F1G32D2DS-023 WT:B, H58G56BK8BX068, K3KL8L80EM-MGCU
 SPD_SOURCES += spd/lp5/set-0/spd-1.hex      # ID = 1(0b0001)  Parts = H9JCNNNBK3MLYR-N6E, MT62F512M32D2DR-031 WT:B
 SPD_SOURCES += spd/lp5/set-0/spd-7.hex      # ID = 2(0b0010)  Parts = K3KL8L80CM-MGCT
 SPD_SOURCES += spd/lp5/set-0/spd-10.hex      # ID = 3(0b0011)  Parts = H58G66CK8BX147
diff --git a/src/mainboard/google/rex/variants/karis/memory/dram_id.generated.txt b/src/mainboard/google/rex/variants/karis/memory/dram_id.generated.txt
index 8a32e1fd77..d7b77d7c83 100644
--- a/src/mainboard/google/rex/variants/karis/memory/dram_id.generated.txt
+++ b/src/mainboard/google/rex/variants/karis/memory/dram_id.generated.txt
@@ -10,3 +10,4 @@ H58G56BK8BX068                 0 (0000)
 K3KL8L80CM-MGCT                2 (0010)
 MT62F512M32D2DR-031 WT:B       1 (0001)
 H58G66CK8BX147                 3 (0011)
+K3KL8L80EM-MGCU                0 (0000)
diff --git a/src/mainboard/google/rex/variants/karis/memory/mem_parts_used.txt b/src/mainboard/google/rex/variants/karis/memory/mem_parts_used.txt
index 217cd83e72..e839b0975c 100644
--- a/src/mainboard/google/rex/variants/karis/memory/mem_parts_used.txt
+++ b/src/mainboard/google/rex/variants/karis/memory/mem_parts_used.txt
@@ -15,3 +15,4 @@ H58G56BK8BX068
 K3KL8L80CM-MGCT
 MT62F512M32D2DR-031 WT:B
 H58G66CK8BX147
+K3KL8L80EM-MGCU

From a348ef46dbccb1cdbdc678643b627f30ce8b992b Mon Sep 17 00:00:00 2001
From: Luca Lai <luca.lai@lcfc.corp-partner.google.com>
Date: Fri, 5 Sep 2025 22:37:45 +0800
Subject: [PATCH 2034/3886] mb/google/trulo/var/pujjolo: Change setting for
 lite ISH fw

Use fw config bit 29 to identify different ish files in pujjolo
when ISH_PRESENT and pujjoquince when ISH_ABSENT.

ISH_PRESENT : pujjolo_ish.bin
ISH_ABSENT : lite_ish.bin

BUG=b:437881361
TEST=Build and boot to OS, check pujjolo and pujjoquince load
corresponding ish file using command ectool --name=cros_ish version and test warmboot/coldboot/suspend pass.

Change-Id: I61b90881abcad368dd668f2631f061b0ea00b57f
Signed-off-by: Luca Lai <luca.lai@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89074
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
---
 .../google/brya/variants/pujjolo/overridetree.cb         | 9 ++++++++-
 1 file changed, 8 insertions(+), 1 deletion(-)

diff --git a/src/mainboard/google/brya/variants/pujjolo/overridetree.cb b/src/mainboard/google/brya/variants/pujjolo/overridetree.cb
index 3b8bd5f0ce..b897edbd5d 100644
--- a/src/mainboard/google/brya/variants/pujjolo/overridetree.cb
+++ b/src/mainboard/google/brya/variants/pujjolo/overridetree.cb
@@ -518,10 +518,17 @@ chip soc/intel/alderlake
 			chip drivers/intel/ish
 				register "add_acpi_dma_property" = "true"
 				register "firmware_name" = ""pujjolo_ish.bin""
-				device generic 0 on
+				device generic 1 on
 					probe ISH ISH_PRESENT
 				end
 			end
+			chip drivers/intel/ish
+				register "add_acpi_dma_property" = "true"
+				register "firmware_name" = ""lite_ish.bin""
+				device generic 0 on
+					probe ISH ISH_ABSENT
+				end
+			end
 		end
 		device ref ufs on end
 		device ref igpu on

From e7d598ba2c15f2c4ca98100ffc81464efdfef042 Mon Sep 17 00:00:00 2001
From: "roccochen@chromium.com" <roccochen@chromium.org>
Date: Thu, 2 Nov 2023 15:49:02 +0800
Subject: [PATCH 2035/3886] Reland "tests: Allow specifying vboot source
 directory"

Respect VBOOT_SOURCE while including generic headers.

This reverts commit 26e7c1eae4120b0d7212d28f6dfa25f14484d319.

BUG=none
TEST=make clean-unit-tests &&
     VBOOT_SOURCE=/path/to/vboot_reference/ make unit-tests -j
TEST=make clean-unit-tests && make unit-tests -j
BRANCH=none

Change-Id: I686575f7c5e22bee519e910f71a4ac579b5c6a50
Signed-off-by: Hsuan Ting Chen <roccochen@chromium.org>
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89176
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hsuan-ting Chen <roccochen@google.com>
---
 Makefile              | 1 +
 Makefile.mk           | 1 -
 tests/Makefile.common | 2 +-
 3 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/Makefile b/Makefile
index 24b7c9624b..7c63040790 100644
--- a/Makefile
+++ b/Makefile
@@ -15,6 +15,7 @@ absobj := $(abspath $(obj))
 
 additional-dirs :=
 
+VBOOT_SOURCE ?= 3rdparty/vboot
 VBOOT_HOST_BUILD ?= $(abspath $(objutil)/vboot_lib)
 
 COREBOOT_EXPORTS := COREBOOT_EXPORTS
diff --git a/Makefile.mk b/Makefile.mk
index 218e388bb5..1c5b8f05d5 100644
--- a/Makefile.mk
+++ b/Makefile.mk
@@ -484,7 +484,6 @@ CPPFLAGS_common += -Isrc/include
 CPPFLAGS_common += -Isrc/commonlib/include
 CPPFLAGS_common += -Isrc/commonlib/bsd/include
 CPPFLAGS_common += -I$(obj)
-VBOOT_SOURCE ?= 3rdparty/vboot
 CPPFLAGS_common += -I$(VBOOT_SOURCE)/firmware/include
 CPPFLAGS_common += -include $(src)/include/kconfig.h
 CPPFLAGS_common += -include $(src)/include/rules.h
diff --git a/tests/Makefile.common b/tests/Makefile.common
index dd7cca29f4..74a3c5a7a9 100644
--- a/tests/Makefile.common
+++ b/tests/Makefile.common
@@ -36,7 +36,7 @@ TEST_INCLUDES += -I$(testsrc)/include/mocks -I$(testsrc)/include
 
 TEST_INCLUDES += -I$(src) -I$(src)/include -I$(src)/commonlib/include \
 	-I$(src)/commonlib/bsd/include -I$(src)/arch/x86/include \
-	-I$(top)/3rdparty/vboot/firmware/include
+	-I$(abspath $(VBOOT_SOURCE))/firmware/include
 
 # Path for Kconfig autoheader
 TEST_INCLUDES += -I$(dir $(TEST_KCONFIG_AUTOHEADER))

From f4a123f0554aa331906717eaf53f4b71db4ab388 Mon Sep 17 00:00:00 2001
From: "roccochen@chromium.com" <roccochen@chromium.org>
Date: Tue, 14 Nov 2023 19:29:45 +0800
Subject: [PATCH 2036/3886] tests: Allow specifying using system Cmocka or
 building from source

Add a flag "USE_SYSTEM_CMOCKA" in the Makefile of tests. (default 1)

If USE_SYSTEM_CMOCKA=1, we will check if the system has Cmocka module,
and link it directly. If the system doesn't have Cmocka, we will set the
flag to 0 and print a warning message.

If USE_SYSTEM_CMOCKA=0, we will build Cmocka from 3rdparty source code.

BUG=none
TEST=make unit-tests -j
TEST=USE_SYSTEM_CMOCKA=0 make unit-tests -j
BRANCH=none

Signed-off-by: roccochen@chromium.com <roccochen@chromium.org>
Change-Id: I091784ca541e2590e3db0a18ceea83e7895ed0c2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79019
Reviewed-by: Jakub "Kuba" Czapiga <czapiga@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 tests/Makefile.common |  5 ++++-
 tests/Makefile.mk     | 10 ++++++++++
 2 files changed, 14 insertions(+), 1 deletion(-)

diff --git a/tests/Makefile.common b/tests/Makefile.common
index 74a3c5a7a9..a8bb19c4f1 100644
--- a/tests/Makefile.common
+++ b/tests/Makefile.common
@@ -157,11 +157,14 @@ $($(1)-sysobjs): $(testobj)/$(1)/%.o: $$$$*.c $$($(1)-config-file)
 
 # Link against Cmocka if not disabled
 ifeq ($(strip $(filter-out 0 n no,$($(1)-no_test_framework))),)
+ifneq ($(USE_SYSTEM_CMOCKA),)
 $($(1)-objs): TEST_CFLAGS += -I$(cmockasrc)/include
-$($(1)-bin): TEST_LDFLAGS += -L$(cmockaobj)/src -lcmocka -Wl,-rpath=$(cmockaobj)/src
+$($(1)-bin): TEST_LDFLAGS += -L$(cmockaobj)/src -Wl,-rpath=$(cmockaobj)/src
 $($(1)-bin): TEST_CFLAGS += -I$(cmockasrc)/include
 $($(1)-bin): $(CMOCKA_LIB)
 endif
+$($(1)-bin): TEST_LDFLAGS += -lcmocka
+endif
 
 $($(1)-bin): $($(1)-objs) $($(1)-sysobjs)
 	$(HOSTCC) $$^ $($(1)-cflags) $$(TEST_LDFLAGS) -o $$@
diff --git a/tests/Makefile.mk b/tests/Makefile.mk
index f838f8336b..f3f122dd38 100644
--- a/tests/Makefile.mk
+++ b/tests/Makefile.mk
@@ -24,6 +24,15 @@ TEST_CFLAGS += --coverage
 TEST_LDFLAGS += --coverage
 endif
 
+# Use system cmoka in default, or build from 3rdparty source code if requested
+USE_SYSTEM_CMOCKA ?= 1
+ifeq ($(USE_SYSTEM_CMOCKA),1)
+ifeq ($(shell $(HOSTPKG_CONFIG) --exists cmocka || echo 1),1)
+$(warning No system cmocka, build from 3rdparty instead...)
+USE_SYSTEM_CMOCKA=0
+endif
+endif
+
 stages := decompressor bootblock romstage smm verstage
 stages += ramstage rmodule postcar libagesa
 
@@ -186,6 +195,7 @@ help-unit-tests help::
 	@echo  '*** coreboot unit-tests targets ***'
 	@echo  '  Use "COV=1 make [target]" to enable code coverage for unit tests'
 	@echo  '  Use "GDB_DEBUG=1 make [target]" to build with debug symbols'
+	@echo  '  Use "USE_SYSTEM_CMOCKA=0 make [target]" to build Cmocka from source'
 	@echo  '  unit-tests            - Run all unit-tests from tests/'
 	@echo  '  clean-unit-tests      - Remove unit-tests build artifacts'
 	@echo  '  list-unit-tests       - List all unit-tests'

From fe70426dd77262f5daab3840be92cece5e0a2933 Mon Sep 17 00:00:00 2001
From: Vince Liu <vince-wl.liu@mediatek.corp-partner.google.com>
Date: Mon, 15 Sep 2025 11:12:42 +0800
Subject: [PATCH 2037/3886] soc/mediatek/common: Add support for regulator
 VCN18
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

To provide power to MIPI panel, add support for regulator VCN18.

BUG=b:432353024
BRANCH=skywalker
TEST=Use an oscilloscope to confirm that the regulator’s output
voltage is 1.8V.

Signed-off-by: Niklaus Liu <niklaus.liu@mediatek.corp-partner.google.com>
Signed-off-by: Vince Liu <vince-wl.liu@mediatek.corp-partner.google.com>
Change-Id: I4d90b3c053f1a06ae0c65d6ce6d800c22d6d3442
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89171
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/soc/mediatek/common/include/soc/mt6359p.h | 11 +++++++
 .../mediatek/common/include/soc/regulator.h   |  1 +
 src/soc/mediatek/common/mt6359p.c             | 33 +++++++++++++++++++
 3 files changed, 45 insertions(+)

diff --git a/src/soc/mediatek/common/include/soc/mt6359p.h b/src/soc/mediatek/common/include/soc/mt6359p.h
index 017e6c8d61..a2e50638ae 100644
--- a/src/soc/mediatek/common/include/soc/mt6359p.h
+++ b/src/soc/mediatek/common/include/soc/mt6359p.h
@@ -35,12 +35,14 @@ enum {
 	PMIC_VSRAM_PROC1_ELR	= 0x1b44,
 	PMIC_VSRAM_PROC2_ELR	= 0x1b46,
 	PMIC_VSRAM_MD_ELR	= 0x1b4a,
+	PMIC_VCN18_CON0		= 0x1c2e,
 	PMIC_VSIM1_CON0		= 0x1cd0,
 	PMIC_VM18_CON0		= 0x1d88,
 	PMIC_VSRAM_PROC1_VOSEL1	= 0x1e90,
 	PMIC_VSRAM_PROC2_VOSEL1	= 0x1eb0,
 	PMIC_VSRAM_MD_VOSEL1	= 0x1f36,
 	PMIC_VSIM1_ANA_CON0	= 0x1fa2,
+	PMIC_VCN18_ANA_CON0	= 0x2010,
 	PMIC_VM18_ANA_CON0	= 0x2020,
 };
 
@@ -68,6 +70,7 @@ enum {
 	MT6359P_VM18,
 	MT6359P_VMODEM,
 	MT6359P_VSRAM_MD,
+	MT6359P_VCN18,
 	MT6359P_MAX,
 };
 
@@ -78,6 +81,11 @@ enum {
 #define VM18_VOL_REG_SHIFT  8
 #define VM18_VOL_OFFSET 600
 
+#define VCN18_VOL_UV_MAX	1900000
+#define VCN18_VOL_UV_MIN	1800000
+#define VCN18_VOL_MV_OFFSET	600
+#define VCN18_VOL_SHIFT		8
+
 #define EFUSE_WAIT_US 5000
 #define EFUSE_BUSY 1
 
@@ -90,9 +98,12 @@ void mt6359p_set_vm18_voltage(u32 vm18_uv);
 u32 mt6359p_get_vm18_voltage(void);
 void mt6359p_set_vsim1_voltage(u32 vsim1_uv);
 u32 mt6359p_get_vsim1_voltage(void);
+void mt6359p_set_vcn18_voltage(u32 vcn18_uv);
+u32 mt6359p_get_vcn18_voltage(void);
 void mt6359p_enable_vpa(bool enable);
 void mt6359p_enable_vsim1(bool enable);
 void mt6359p_enable_vm18(bool enable);
+void mt6359p_enable_vcn18(bool enable);
 void mt6359p_init_pmif_arb(void);
 u32 mt6359p_read_field(u32 reg, u32 mask, u32 shift);
 void mt6359p_write_field(u32 reg, u32 val, u32 mask, u32 shift);
diff --git a/src/soc/mediatek/common/include/soc/regulator.h b/src/soc/mediatek/common/include/soc/regulator.h
index 3cec8f06eb..152ba34d7b 100644
--- a/src/soc/mediatek/common/include/soc/regulator.h
+++ b/src/soc/mediatek/common/include/soc/regulator.h
@@ -21,6 +21,7 @@ enum mtk_regulator {
 	MTK_REGULATOR_VSRAM_PROC11,
 	MTK_REGULATOR_VSRAM_PROC12,
 	MTK_REGULATOR_VRF12,
+	MTK_REGULATOR_VCN18,
 	MTK_REGULATOR_VCN33,
 	MTK_REGULATOR_VDD18,
 	MTK_REGULATOR_VIO18,
diff --git a/src/soc/mediatek/common/mt6359p.c b/src/soc/mediatek/common/mt6359p.c
index 8026f29915..5dad6a44cb 100644
--- a/src/soc/mediatek/common/mt6359p.c
+++ b/src/soc/mediatek/common/mt6359p.c
@@ -336,6 +336,34 @@ u32 mt6359p_get_vsim1_voltage(void)
 	return 1000 * (reg_offset + reg_vol + reg_cali);
 }
 
+u32 mt6359p_get_vcn18_voltage(void)
+{
+	u32 reg_vol, reg_cali;
+	if (!pmif_arb)
+		die("[%s] ERROR: pmif_arb not initialized", __func__);
+
+	reg_vol = 100 * mt6359p_read_field(PMIC_VCN18_ANA_CON0, 0xF, VCN18_VOL_SHIFT);
+	reg_cali = 10 * mt6359p_read_field(PMIC_VCN18_ANA_CON0, 0xF, 0);
+	return 1000 * (VCN18_VOL_MV_OFFSET + reg_vol + reg_cali);
+}
+
+void mt6359p_set_vcn18_voltage(u32 vcn18_uv)
+{
+	u32 reg_vol, reg_cali;
+	if (!pmif_arb)
+		die("[%s] ERROR: pmif_arb not initialized", __func__);
+
+	if (vcn18_uv < VCN18_VOL_UV_MIN || vcn18_uv > VCN18_VOL_UV_MAX) {
+		printk(BIOS_ERR,
+		       "%s: VCN18 voltage %d is out of range (%d uV - %d uV)\n",
+		       __func__, vcn18_uv, VCN18_VOL_UV_MIN, VCN18_VOL_UV_MAX);
+		return;
+	}
+	reg_vol = (vcn18_uv / 1000 - VCN18_VOL_MV_OFFSET) / 100;
+	reg_cali = (vcn18_uv / 1000) % 100 / 10;
+	mt6359p_write(PMIC_VCN18_ANA_CON0, (reg_vol << VCN18_VOL_SHIFT) | reg_cali);
+}
+
 void mt6359p_enable_vpa(bool enable)
 {
 	mt6359p_write_field(PMIC_VPA_CON0, enable, 0x1, 0);
@@ -351,6 +379,11 @@ void mt6359p_enable_vm18(bool enable)
 	mt6359p_write_field(PMIC_VM18_CON0, enable, 0x1, 0);
 }
 
+void mt6359p_enable_vcn18(bool enable)
+{
+	mt6359p_write_field(PMIC_VCN18_CON0, enable, 0x1, 0);
+}
+
 void mt6359p_init_pmif_arb(void)
 {
 	if (pmif_arb)

From 1da045f6a557696160b3685464f2bfdd50f86277 Mon Sep 17 00:00:00 2001
From: Vince Liu <vince-wl.liu@mediatek.corp-partner.google.com>
Date: Mon, 15 Sep 2025 10:51:28 +0800
Subject: [PATCH 2038/3886] mb/google/skywalker: Add API support for regulator
 VCN18
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Add the VNC18 regulator API for the MIPI panel usage.

BUG=b:432353024
BRANCH=skywalker
TEST=Use an oscilloscope to confirm that the regulator’s output
voltage is 1.8V.

Change-Id: Ib2065d8b4f92f4ad266976883cb2927107330a69
Signed-off-by: Niklaus Liu <niklaus.liu@mediatek.corp-partner.google.com>
Signed-off-by: Vince Liu <vince-wl.liu@mediatek.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89172
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
---
 src/mainboard/google/skywalker/regulator.c | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/src/mainboard/google/skywalker/regulator.c b/src/mainboard/google/skywalker/regulator.c
index 46d0e2b8a2..63d17afac0 100644
--- a/src/mainboard/google/skywalker/regulator.c
+++ b/src/mainboard/google/skywalker/regulator.c
@@ -17,6 +17,8 @@ static int get_mt6359p_regulator_id(enum mtk_regulator regulator)
 		return MT6359P_PA;
 	case MTK_REGULATOR_VMC:
 		return MT6359P_SIM1;
+	case MTK_REGULATOR_VCN18:
+		return MT6359P_VCN18;
 	default:
 		return MTK_REGULATOR_INVALID;
 	}
@@ -45,6 +47,9 @@ void mainboard_set_regulator_voltage(enum mtk_regulator regulator, uint32_t volt
 	case MT6359P_SIM1:
 		mt6359p_set_vsim1_voltage(voltage_uv);
 		break;
+	case MT6359P_VCN18:
+		mt6359p_set_vcn18_voltage(voltage_uv);
+		break;
 	default:
 		printk(BIOS_ERR, "%s: Regulator ID %d: not supported\n", __func__, regulator);
 		break;
@@ -70,6 +75,8 @@ uint32_t mainboard_get_regulator_voltage(enum mtk_regulator regulator)
 		return mt6359p_buck_get_voltage(MT6359P_PA);
 	case MT6359P_SIM1:
 		return mt6359p_get_vsim1_voltage();
+	case MT6359P_VCN18:
+		return mt6359p_get_vcn18_voltage();
 	default:
 		printk(BIOS_ERR, "%s: Regulator ID %d: not supported\n", __func__, regulator);
 		return 0;
@@ -93,6 +100,9 @@ int mainboard_enable_regulator(enum mtk_regulator regulator, bool enable)
 	case MT6359P_SIM1:
 		mt6359p_enable_vsim1(enable);
 		break;
+	case MT6359P_VCN18:
+		mt6359p_enable_vcn18(enable);
+		break;
 	default:
 		printk(BIOS_ERR, "%s: Regulator ID %d: not supported\n", __func__, regulator);
 		break;

From d3d2f0f1c8dd3f085aa47d8d5d9c1e13d39b6827 Mon Sep 17 00:00:00 2001
From: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
Date: Fri, 12 Sep 2025 16:15:28 +0800
Subject: [PATCH 2039/3886] mb/google/fatcat/var/moonstone: Add to support
 ALC1320 Smart Amp

Enable Realtek ALC1320 as speaker Amplifier.
Use ALC721 as codec and ALC1320 as Amplifier on SoundWire Link 3.

BUG=b:442964982
TEST=emerge-fatcat coreboot
1.Set fw_config AUDIO bits to AUDIO_ALC1320_ALC721_SNDW
2.check the SSDT.dsl:
  PCI0.HDAS.SNDW including 0x000331025D072101 & 0x000332025D132001

Change-Id: I4c6b5c3f2d9acb7eaf8f77844526bc9de3ae1f99
Signed-off-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89177
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 .../fatcat/variants/moonstone/overridetree.cb   | 17 +++++++++++++++--
 1 file changed, 15 insertions(+), 2 deletions(-)

diff --git a/src/mainboard/google/fatcat/variants/moonstone/overridetree.cb b/src/mainboard/google/fatcat/variants/moonstone/overridetree.cb
index 18a506700f..b06207f9ed 100644
--- a/src/mainboard/google/fatcat/variants/moonstone/overridetree.cb
+++ b/src/mainboard/google/fatcat/variants/moonstone/overridetree.cb
@@ -3,8 +3,9 @@ fw_config
 		option WIFI_CNVI_7		0
 	end
 	field AUDIO 3 5
-		option AUDIO_UNKNOWN		0
-		option AUDIO_ALC721_SNDW	1
+		option AUDIO_UNKNOWN				0
+		option AUDIO_ALC721_SNDW			1
+		option AUDIO_ALC1320_ALC721_SNDW	2
 	end
 	field FPMCU 6 7
 		option FP_ABSENT		0
@@ -374,6 +375,7 @@ chip soc/intel/pantherlake
 		device ref smbus on end
 		device ref hda on
 			probe AUDIO AUDIO_ALC721_SNDW
+			probe AUDIO AUDIO_ALC1320_ALC721_SNDW
 			chip drivers/intel/soundwire
 				device generic 0 on
 					chip drivers/soundwire/alc711
@@ -384,8 +386,19 @@ chip soc/intel/pantherlake
 						# SoundWire Link 3 ID 1
 						device generic 3.1 on
 							probe AUDIO AUDIO_ALC721_SNDW
+							probe AUDIO AUDIO_ALC1320_ALC721_SNDW
 						end
 					end
+					chip drivers/soundwire/alc1320
+						register "desc" = ""Speaker Amp""
+						register "alc1320_address.version" = "SOUNDWIRE_VERSION_1_2"
+						register "alc1320_address.class" = "MIPI_CLASS_SDCA"
+						register "alc1320_address.part_id" = "MIPI_DEV_ID_REALTEK_ALC1320"
+						# SoundWire Link 3 ID 2
+						device generic 3.2 on
+							probe AUDIO AUDIO_ALC1320_ALC721_SNDW
+						end # ALC1320 Smart Amp
+					end
 				end
 			end
 		end

From 93c147c5e6e6bf6821eeffdc6fbc9863b93199ba Mon Sep 17 00:00:00 2001
From: Yidi Lin <yidilin@google.com>
Date: Fri, 12 Sep 2025 13:08:54 +0800
Subject: [PATCH 2040/3886] commonlib/device_tree: Add dt_add_iommu_addr_prop
 function

`dt_add_reg_prop` and the newly introduced `dt_add_iommu_addr_prop`
share identical logic for building the binary data buffer, differing
only in the property name written to the Device Tree. Therefore,
refactor the shared logic into a new static helper function,
`dt_add_addr_and_size_prop`.

The existing `dt_add_reg_prop` is converted to a wrapper around this new
helper.

`dt_add_iommu_addr_prop` is introduced as a separate wrapper to
specifically add the `iommu-addresses` property. This property defines
reserved IOVA ranges or identity-mapped regions, such as a display
framebuffer configured by the bootloader. It is typically utilized
within the `reserved-memory` subsystem.

BUG=b:435289727
TEST=The below translation fault does not occur.
[    0.171028] arm-smmu-v3 30800000.iommu: TBU_id-2-fault_id:0x2000008(0x8), TF read in NORMAL world, iova:0xa3000000,  sid:144, ssid:0, ssidv:0, secsidv:0

Change-Id: Icedcce5681a7b659b11b7e7208663bc1d920ce3b
Signed-off-by: Yidi Lin <yidilin@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89152
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/commonlib/device_tree.c                   | 52 ++++++++++++++-----
 src/commonlib/include/commonlib/device_tree.h |  4 +-
 2 files changed, 41 insertions(+), 15 deletions(-)

diff --git a/src/commonlib/device_tree.c b/src/commonlib/device_tree.c
index a6fdd0cb61..d244ad9954 100644
--- a/src/commonlib/device_tree.c
+++ b/src/commonlib/device_tree.c
@@ -1533,21 +1533,12 @@ void dt_add_u64_prop(struct device_tree_node *node, const char *name, u64 val)
 	dt_add_bin_prop(node, name, val_ptr, sizeof(*val_ptr));
 }
 
-/*
- * Add a 'reg' address list property to a node, or update it if it exists.
- *
- * @param node		The device tree node to add to.
- * @param regions       Array of address values to be stored in the property.
- * @param sizes		Array of corresponding size values to 'addrs'.
- * @param count		Number of values in 'addrs' and 'sizes' (must be equal).
- * @param addr_cells	Value of #address-cells property valid for this node.
- * @param size_cells	Value of #size-cells property valid for this node.
- */
-void dt_add_reg_prop(struct device_tree_node *node, u64 *addrs, u64 *sizes,
-		     int count, u32 addr_cells, u32 size_cells)
+static void dt_add_addr_and_size_prop(struct device_tree_node *node, const char *prop_name,
+				      const u64 *addrs, const u64 *sizes, int count,
+				      u32 addr_cells, u32 size_cells)
 {
 	int i;
-	size_t length = (addr_cells + size_cells) * sizeof(u32) * count;
+	size_t length = (size_t)(addr_cells + size_cells) * sizeof(u32) * count;
 	u8 *data = xmalloc(length);
 	u8 *cur = data;
 
@@ -1558,7 +1549,40 @@ void dt_add_reg_prop(struct device_tree_node *node, u64 *addrs, u64 *sizes,
 		cur += size_cells * sizeof(u32);
 	}
 
-	dt_add_bin_prop(node, "reg", data, length);
+	dt_add_bin_prop(node, prop_name, data, length);
+}
+
+/*
+ * Add a 'reg' address list property to a node, or update it if it exists.
+ *
+ * @param node		The device tree node to add to.
+ * @param regions       Array of address values to be stored in the property.
+ * @param sizes		Array of corresponding size values to 'addrs'.
+ * @param count		Number of values in 'addrs' and 'sizes' (must be equal).
+ * @param addr_cells	Value of #address-cells property valid for this node.
+ * @param size_cells	Value of #size-cells property valid for this node.
+ */
+void dt_add_reg_prop(struct device_tree_node *node, const u64 *addrs, const u64 *sizes,
+		     int count, u32 addr_cells, u32 size_cells)
+{
+	dt_add_addr_and_size_prop(node, "reg", addrs, sizes, count, addr_cells, size_cells);
+}
+
+/*
+ * Add a 'iommu-addresses' address list property to a node, or update it if it exists.
+ *
+ * @param node		The device tree node to add to.
+ * @param regions       Array of address values to be stored in the property.
+ * @param sizes		Array of corresponding size values to 'addrs'.
+ * @param count		Number of values in 'addrs' and 'sizes' (must be equal).
+ * @param addr_cells	Value of #address-cells property valid for this node.
+ * @param size_cells	Value of #size-cells property valid for this node.
+ */
+void dt_add_iommu_addr_prop(struct device_tree_node *node, const u64 *addrs, const u64 *sizes,
+			    int count, u32 addr_cells, u32 size_cells)
+{
+	dt_add_addr_and_size_prop(node, "iommu-addresses", addrs, sizes, count, addr_cells,
+				  size_cells);
 }
 
 /*
diff --git a/src/commonlib/include/commonlib/device_tree.h b/src/commonlib/include/commonlib/device_tree.h
index 5ab5fbf294..be945d93da 100644
--- a/src/commonlib/include/commonlib/device_tree.h
+++ b/src/commonlib/include/commonlib/device_tree.h
@@ -189,8 +189,10 @@ void dt_add_string_prop(struct device_tree_node *node, const char *name,
 			const char *str);
 void dt_add_u32_prop(struct device_tree_node *node, const char *name, u32 val);
 void dt_add_u64_prop(struct device_tree_node *node, const char *name, u64 val);
-void dt_add_reg_prop(struct device_tree_node *node, u64 *addrs, u64 *sizes,
+void dt_add_reg_prop(struct device_tree_node *node, const u64 *addrs, const u64 *sizes,
 		     int count, u32 addr_cells, u32 size_cells);
+void dt_add_iommu_addr_prop(struct device_tree_node *node, const u64 *addrs, const u64 *sizes,
+			    int count, u32 addr_cells, u32 size_cells);
 int dt_set_bin_prop_by_path(struct device_tree *tree, const char *path,
 			    void *data, size_t size, int create);
 

From 56700713de9fbecf263b74c4881f6161835438c5 Mon Sep 17 00:00:00 2001
From: Eren Peng <peng.eren@inventec.corp-partner.google.com>
Date: Fri, 5 Sep 2025 16:20:19 +0800
Subject: [PATCH 2041/3886] mb/google/trulo/var/kaladin: Disable eMMC GPIOs via
 firmware config

Disable eMMC related GPIO pins via firmware config on non-eMMC skus

BUG=b:443202137
TEST=flash and boot successfully on all kaladin SKU

Change-Id: Ia98702368208649fc0891417c7e8c6c3685d40be
Signed-off-by: Eren Peng <peng.eren@inventec.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89069
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 .../google/brya/variants/kaladin/variant.c    | 31 +++++++++++++++++++
 1 file changed, 31 insertions(+)

diff --git a/src/mainboard/google/brya/variants/kaladin/variant.c b/src/mainboard/google/brya/variants/kaladin/variant.c
index 909d2e0fdd..7bed12678b 100644
--- a/src/mainboard/google/brya/variants/kaladin/variant.c
+++ b/src/mainboard/google/brya/variants/kaladin/variant.c
@@ -11,6 +11,33 @@ const char *get_wifi_sar_cbfs_filename(void)
 	return get_wifi_sar_fw_config_filename(FW_CONFIG_FIELD(WIFI_SAR));
 }
 
+static const struct pad_config emmc_disable_pads[] = {
+	/* I7  : EMMC_CMD */
+	PAD_NC(GPP_I7, NONE),
+	/* I8  : EMMC_D0 */
+	PAD_NC(GPP_I8, NONE),
+	/* I9  : EMMC_D1 */
+	PAD_NC(GPP_I9, NONE),
+	/* I10 : EMMC_D2 */
+	PAD_NC(GPP_I10, NONE),
+	/* I11 : EMMC_D3 */
+	PAD_NC(GPP_I11, NONE),
+	/* I12 : EMMC_D4 */
+	PAD_NC(GPP_I12, NONE),
+	/* I13 : EMMC_D5 */
+	PAD_NC(GPP_I13, NONE),
+	/* I14 : EMMC_D6 */
+	PAD_NC(GPP_I14, NONE),
+	/* I15 : EMMC_D7 */
+	PAD_NC(GPP_I15, NONE),
+	/* I16 : EMMC_RCLK */
+	PAD_NC(GPP_I16, NONE),
+	/* I17 : EMMC_CLK */
+	PAD_NC(GPP_I17, NONE),
+	/* I18 : EMMC_RST_L */
+	PAD_NC(GPP_I18, NONE),
+};
+
 static const struct pad_config ish_disable_pads[] = {
 	/* B3  : ISH_IMU_INT_L ==>NC */
 	PAD_NC(GPP_B3, NONE),
@@ -34,6 +61,10 @@ void fw_config_gpio_padbased_override(struct pad_config *padbased_table)
 		printk(BIOS_INFO, "Disable ISH GPIO pins.\n");
 		gpio_padbased_override(padbased_table, ish_disable_pads, ARRAY_SIZE(ish_disable_pads));
 	}
+	if (!fw_config_probe(FW_CONFIG(STORAGE, STORAGE_EMMC)) && !fw_config_probe(FW_CONFIG(STORAGE, STORAGE_UNKNOWN))) {
+		printk(BIOS_INFO, "Disable eMMC GPIO pins.\n");
+		gpio_padbased_override(padbased_table, emmc_disable_pads, ARRAY_SIZE(emmc_disable_pads));
+	}
 }
 
 void variant_configure_pads(void)

From 751afeb06099ce353ef5d4d8a19b7625049ecda3 Mon Sep 17 00:00:00 2001
From: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Date: Wed, 10 Sep 2025 09:10:43 +0800
Subject: [PATCH 2042/3886] mb/google/brox/var/caboc: Update HDA verb table

Table is from vendor. Update HWEQ and AGC setting.

BUG=b:435345756
TEST=emerge-brox coreboot
     check system audio output is fine

Change-Id: I0869a4902e38e8010274769de7f8e7b9a4160aae
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89127
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
---
 .../variants/caboc/include/variant/hda_verb.h | 67 +++++--------------
 1 file changed, 16 insertions(+), 51 deletions(-)

diff --git a/src/mainboard/google/brox/variants/caboc/include/variant/hda_verb.h b/src/mainboard/google/brox/variants/caboc/include/variant/hda_verb.h
index 5a6c2745ee..04942c5038 100644
--- a/src/mainboard/google/brox/variants/caboc/include/variant/hda_verb.h
+++ b/src/mainboard/google/brox/variants/caboc/include/variant/hda_verb.h
@@ -9,7 +9,7 @@ const u32 cim_verb_data[] = {
 	/* coreboot specific header */
 	0x10ec0236,	// Codec Vendor / Device ID: Realtek ALC236
 	0x103C8C60,	// Subsystem ID
-	0x00000023,	// Number of jacks (NID entries)
+	0x0000001A,	// Number of jacks (NID entries)
 
 	AZALIA_RESET(0x1),
 	/* NID 0x01, HDA Codec Subsystem ID Verb table */
@@ -77,36 +77,16 @@ const u32 cim_verb_data[] = {
 	0x057409A3,
 	/* disable EQ first */
 	0x05350000,
-	0x0534203A,
+	0x0534201A,
 	/* Left Channel */
 	0x0535001d,
 	0x05340800,
 	0x0535001e,
 	0x05340800,
 	0x05350003,
-	0x05341F95,
+	0x05341EC4,
 	0x05350004,
 	0x05340000,
-	0x05350005,
-	0x053403F6,
-	0x05350006,
-	0x0534854C,
-	0x05350007,
-	0x05341E09,
-	0x05350008,
-	0x05346472,
-	0x05350009,
-	0x053401FB,
-	0x0535000A,
-	0x05344836,
-	0x0535000B,
-	0x05341C00,
-	0x0535000C,
-	0x05340000,
-	0x0535000D,
-	0x05340200,
-	0x0535000E,
-	0x05340000,
 	/* Right Channel */
 	0x05450000,
 	0x05442000,
@@ -115,45 +95,30 @@ const u32 cim_verb_data[] = {
 	0x0545001e,
 	0x05440800,
 	0x05450003,
-	0x05441F95,
+	0x05441EC4,
 	0x05450004,
 	0x05440000,
-	0x05450005,
-	0x054403F6,
-	0x05450006,
-	0x0544854C,
-	0x05450007,
-	0x05441E09,
-	0x05450008,
-	0x05446472,
-	0x05450009,
-	0x054401FB,
-	0x0545000A,
-	0x05444836,
-	0x0545000B,
-	0x05441C00,
-	0x0545000C,
-	0x05440000,
-	0x0545000D,
-	0x05440200,
-	0x0545000E,
-	0x05440000,
 	/* enable EQ */
 	0x05350000,
-	0x0534E03A,
+	0x0534E01A,
 	/* 2.2W/4ohm */
 	0x02050038,
 	0x02046901,
-	/* AGC Enable */
-	0x0205004C,
-	0x0204465C,
+	/* Disable AGC and set AGC limit to 0dB  */
+	0x02050016,
+	0x02044C50,
+	0x02050012,
+	0x0204EBC0,
+	/* Set AGC Front and Post gain 0dB then Enable AGC */
+	0x02050013,
+	0x0204401F,
 	0x02050016,
 	0x02044E50,
-	0x02050020,
-	0x020451FF,
 	/* Headphone Pop */
 	0x05750007,
 	0x057412B2,
+	0x05750007,	/* Padding */
+	0x057412B2,	/* Padding */
 };
 
 const u32 pc_beep_verbs[] = {
@@ -161,7 +126,7 @@ const u32 pc_beep_verbs[] = {
 	0x02050036,
 	0x02047151,
 	0x02050010,
-	0x02040020,
+	0x02040320,
 	/* Dos beep path - 2 */
 	0x0143B000,
 	0x01470740,

From bcb32630783a6ebfc7d37ff87b7a089258cf6e53 Mon Sep 17 00:00:00 2001
From: Nick Vaccaro <nvaccaro@google.com>
Date: Mon, 15 Sep 2025 11:48:45 -0700
Subject: [PATCH 2043/3886] mb/goog/ocelot/var/ocelot: add H58G66BK8BX067
 memory option

Add H58G66BK8BX067 memory part as DRAM ID 2.

BUG=b:445200980
TEST=None

Change-Id: Ica4c253ebed922f204e4782bbfeb1f09f12f5723
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89182
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Avi Uday <aviuday@google.com>
Reviewed-by: Pranava Y N <pranavayn@google.com>
---
 src/mainboard/google/ocelot/variants/ocelot/memory/Makefile.mk | 3 ++-
 .../google/ocelot/variants/ocelot/memory/dram_id.generated.txt | 3 ++-
 .../google/ocelot/variants/ocelot/memory/mem_parts_used.txt    | 1 +
 3 files changed, 5 insertions(+), 2 deletions(-)

diff --git a/src/mainboard/google/ocelot/variants/ocelot/memory/Makefile.mk b/src/mainboard/google/ocelot/variants/ocelot/memory/Makefile.mk
index dd0d2ca609..9184097b25 100644
--- a/src/mainboard/google/ocelot/variants/ocelot/memory/Makefile.mk
+++ b/src/mainboard/google/ocelot/variants/ocelot/memory/Makefile.mk
@@ -1,8 +1,9 @@
 # SPDX-License-Identifier: GPL-2.0-or-later
 # This is an auto-generated file. Do not edit!!
 # Generated by:
-# ./util/spd_tools/bin/part_id_gen PTL lp5 src/mainboard/google/ocelot/variants/ocelot/memory src/mainboard/google/ocelot/variants/ocelot/memory/mem_parts_used.txt
+# ./util/spd_tools/src/part_id_gen/part_id_gen PTL lp5 src/mainboard/google/ocelot/variants/ocelot/memory src/mainboard/google/ocelot/variants/ocelot/memory/mem_parts_used.txt
 
 SPD_SOURCES =
 SPD_SOURCES += spd/lp5/set-0/spd-11.hex      # ID = 0(0b0000)  Parts = H58G56BK8BX068
 SPD_SOURCES += spd/lp5/set-0/spd-8.hex      # ID = 1(0b0001)  Parts = H58G66BK7BX067
+SPD_SOURCES += spd/lp5/set-0/spd-10.hex      # ID = 2(0b0010)  Parts = H58G66BK8BX067
diff --git a/src/mainboard/google/ocelot/variants/ocelot/memory/dram_id.generated.txt b/src/mainboard/google/ocelot/variants/ocelot/memory/dram_id.generated.txt
index 591cb7650f..e86908c913 100644
--- a/src/mainboard/google/ocelot/variants/ocelot/memory/dram_id.generated.txt
+++ b/src/mainboard/google/ocelot/variants/ocelot/memory/dram_id.generated.txt
@@ -1,8 +1,9 @@
 # SPDX-License-Identifier: GPL-2.0-or-later
 # This is an auto-generated file. Do not edit!!
 # Generated by:
-# ./util/spd_tools/bin/part_id_gen PTL lp5 src/mainboard/google/ocelot/variants/ocelot/memory src/mainboard/google/ocelot/variants/ocelot/memory/mem_parts_used.txt
+# ./util/spd_tools/src/part_id_gen/part_id_gen PTL lp5 src/mainboard/google/ocelot/variants/ocelot/memory src/mainboard/google/ocelot/variants/ocelot/memory/mem_parts_used.txt
 
 DRAM Part Name                 ID to assign
 H58G56BK8BX068                 0 (0000)
 H58G66BK7BX067                 1 (0001)
+H58G66BK8BX067                 2 (0010)
diff --git a/src/mainboard/google/ocelot/variants/ocelot/memory/mem_parts_used.txt b/src/mainboard/google/ocelot/variants/ocelot/memory/mem_parts_used.txt
index 4b06f23814..951d24f620 100644
--- a/src/mainboard/google/ocelot/variants/ocelot/memory/mem_parts_used.txt
+++ b/src/mainboard/google/ocelot/variants/ocelot/memory/mem_parts_used.txt
@@ -11,3 +11,4 @@
 # Part Name
 H58G56BK8BX068
 H58G66BK7BX067
+H58G66BK8BX067

From f1b83c87591b96da12276bcd3095de600e12cc8c Mon Sep 17 00:00:00 2001
From: David Wu <david_wu@quanta.corp-partner.google.com>
Date: Mon, 15 Sep 2025 20:20:01 +0800
Subject: [PATCH 2044/3886] mb/google/rex/var/kanix: Add K3KL8L80EM-MGCU to RAM
 ID table

Add the new memory support: Samsung K3KL8L80EM-MGCU

BUG=b:412311178
TEST=Run part_id_gen tool and check the generated files.

Change-Id: Ib14a388bd4f1ef884db401b36067a6ea0ac9fe9b
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89178
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
---
 src/mainboard/google/rex/variants/kanix/memory/Makefile.mk      | 2 +-
 .../google/rex/variants/kanix/memory/dram_id.generated.txt      | 1 +
 .../google/rex/variants/kanix/memory/mem_parts_used.txt         | 1 +
 3 files changed, 3 insertions(+), 1 deletion(-)

diff --git a/src/mainboard/google/rex/variants/kanix/memory/Makefile.mk b/src/mainboard/google/rex/variants/kanix/memory/Makefile.mk
index 790f8b7cbe..f818a38d02 100644
--- a/src/mainboard/google/rex/variants/kanix/memory/Makefile.mk
+++ b/src/mainboard/google/rex/variants/kanix/memory/Makefile.mk
@@ -4,6 +4,6 @@
 # util/spd_tools/bin/part_id_gen MTL lp5 src/mainboard/google/rex/variants/kanix/memory src/mainboard/google/rex/variants/kanix/memory/mem_parts_used.txt
 
 SPD_SOURCES =
-SPD_SOURCES += spd/lp5/set-0/spd-11.hex      # ID = 0(0b0000)  Parts = MT62F1G32D2DS-023 WT:B, H58G56BK8BX068, H58G56CK8BX146
+SPD_SOURCES += spd/lp5/set-0/spd-11.hex      # ID = 0(0b0000)  Parts = MT62F1G32D2DS-023 WT:B, H58G56BK8BX068, H58G56CK8BX146, K3KL8L80EM-MGCU
 SPD_SOURCES += spd/lp5/set-0/spd-1.hex      # ID = 1(0b0001)  Parts = H9JCNNNBK3MLYR-N6E, MT62F512M32D2DR-031 WT:B
 SPD_SOURCES += spd/lp5/set-0/spd-7.hex      # ID = 2(0b0010)  Parts = K3KL8L80CM-MGCT
diff --git a/src/mainboard/google/rex/variants/kanix/memory/dram_id.generated.txt b/src/mainboard/google/rex/variants/kanix/memory/dram_id.generated.txt
index 7587b991a8..74e7f23d8b 100644
--- a/src/mainboard/google/rex/variants/kanix/memory/dram_id.generated.txt
+++ b/src/mainboard/google/rex/variants/kanix/memory/dram_id.generated.txt
@@ -10,3 +10,4 @@ H58G56BK8BX068                 0 (0000)
 K3KL8L80CM-MGCT                2 (0010)
 MT62F512M32D2DR-031 WT:B       1 (0001)
 H58G56CK8BX146                 0 (0000)
+K3KL8L80EM-MGCU                0 (0000)
diff --git a/src/mainboard/google/rex/variants/kanix/memory/mem_parts_used.txt b/src/mainboard/google/rex/variants/kanix/memory/mem_parts_used.txt
index b1d3b93dfb..3fa9bc7335 100644
--- a/src/mainboard/google/rex/variants/kanix/memory/mem_parts_used.txt
+++ b/src/mainboard/google/rex/variants/kanix/memory/mem_parts_used.txt
@@ -15,3 +15,4 @@ H58G56BK8BX068
 K3KL8L80CM-MGCT
 MT62F512M32D2DR-031 WT:B
 H58G56CK8BX146
+K3KL8L80EM-MGCU

From bb760bc9f33c0eaac1d0653fb7a4d4fc1937a31a Mon Sep 17 00:00:00 2001
From: Subrata Banik <subratabanik@google.com>
Date: Mon, 15 Sep 2025 20:45:04 +0000
Subject: [PATCH 2045/3886] Kconfig: Introduce HAVE_CBFS_FILE_OPTION_BACKEND

Introduce a new Kconfig option, `HAVE_CBFS_FILE_OPTION_BACKEND`, to
explicitly select the capability of using a CBFS file for option
storage.

This capability is currently only used by ChromeOS boards leveraging
FSP 2.0. By decoupling the capability check from the choice default
selection logic, we can simplify the configuration of the option
backend choice:

- The new capability config is set to 'y' only if `CHROMEOS &&
  PLATFORM_USES_FSP2_0`.
- The 'Option backend to use' choice now depends on this new capability
  config.

This change allows other SoC platforms beyond Intel to leverage this
feature.

TEST=Build all ChromeOS FSP 2.0 boards and confirm the default option
backend is still USE_CBFS_FILE_OPTION_BACKEND.

Change-Id: Ia55e0feae8fd462411ed3e9306d19ed6d1cfcaf1
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89184
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
---
 src/Kconfig | 16 +++++++++++++++-
 1 file changed, 15 insertions(+), 1 deletion(-)

diff --git a/src/Kconfig b/src/Kconfig
index 1a49a8ba55..a7a34b26a5 100644
--- a/src/Kconfig
+++ b/src/Kconfig
@@ -149,7 +149,7 @@ config UTIL_GENPARSER
 
 choice
 	prompt "Option backend to use"
-	default USE_CBFS_FILE_OPTION_BACKEND if CHROMEOS && PLATFORM_USES_FSP2_0
+	default USE_CBFS_FILE_OPTION_BACKEND if HAVE_CBFS_FILE_OPTION_BACKEND
 	default USE_MAINBOARD_SPECIFIC_OPTION_BACKEND if HAVE_MAINBOARD_SPECIFIC_OPTION_BACKEND
 	default USE_OPTION_TABLE if NVRAMCUI_SECONDARY_PAYLOAD
 	default USE_UEFI_VARIABLE_STORE if DRIVERS_EFI_VARIABLE_STORE && \
@@ -864,6 +864,20 @@ config HAVE_MAINBOARD_SPECIFIC_OPTION_BACKEND
 	  to access the values for runtime-configurable options. For example, a
 	  custom BMC interface or an EEPROM with an externally-imposed layout.
 
+config HAVE_CBFS_FILE_OPTION_BACKEND
+	bool
+	default y if CHROMEOS && PLATFORM_USES_FSP2_0
+	default n
+	help
+	  Select this option if the platform uses CBFS file-based option backend
+	  for storing configuration values at run time.
+
+	  This feature allows for storing and retrieving configuration data
+	  within a dedicated file inside the CBFS.
+
+	  At present this feature is typically used by ChromeOS devices that
+	  use Intel's Firmware Support Package (FSP).
+
 config HAVE_OPTION_TABLE
 	bool
 	default n

From 47fb46e0e452920c145123ac3ebe02e6ad278936 Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Sun, 7 Sep 2025 20:25:33 +0100
Subject: [PATCH 2046/3886] vc/intel/fsp/mtl: Update the headers to 5124_47
 (13.0.228.64)
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Update MTL headers from 4122_21 to 5124_47.

- PCIe EQ controls added/reworked:
  - New per-RP EQ bypass/phase controls for Gen3/4/5: Phase2, Phase3,
    Phase2–3, and overall Phase enable arrays (multiple 29-byte
    arrays)
  - New Gen3/4/5 PCET timers and TS Lock timers per-RP
  - Added PcieGen5EqPh2LocalTxOverridePreset[29]
  - Added PcieRpLtrOverrideSpecComplaint[29] (LTR override based on EP
    capability)
  - Added PcieFomsCp[29] (FOMS control policy)
  - Added PCIe configuration dump toggle (PcieCfgDump[12])
  - Added PcieClockGating[29], PciePowerGating[29], LinkDownGpios[29]
  - Added PcieFiaProgramming and PcieSetSecuredRegisterLock toggles

- Power/ASPM/LTR and platform policy:
  - Added PchDmiAspm control
  - Added ASPM Optionality Compliance test array
    (PcieRpTestAspmOc[12])
  - Added PchLanWOLFastSupport and WoWLAN DeepSx/LAN wake/Deep Sx
    policy controls
  - Added CPPM Force Alignment (CppmFaEn), PlatformAtxTelemetryUnit
  - Multiple “Reserved” fields renamed to RsvdXXX with adjusted sizes

- Thermal throttling (SoC/PCH/IOE/SATA):
  - New enable/suggested-setting toggles, customizable T0/T1/T2
    levels, and locks for SoC, PCH, IOE thermal throttling
  - SATA thermal suggested setting retained; minor reserved rename
    around it

- Storage/IO:
  - Added UfsInlineEncryption[2] enable/disable

- PMC/ADR and low-power:
  - Added comprehensive PMC ADR controls (enable, timer enable/values,
    source override/select, host reset partition) and PMC WDT enable
  - Added PmcLpmS0ixSubStateEnableMask and
    PmcPchLpmS0ixSubStateEnableMask
  - Added PchPmErDebugMode

- CPU/Power management:
  - Added CcfAutoGv, ThreeStrikeCounter, HwpLock
  - Added StepDownMode, PowerFloorManagement,
    PowerFloorDisplayDisconnect, EnableRp, PowerFloorPcieGenDowngrade
  - Added SecurityPostMemRsvd, MePostMemRsvd, various
    ReservedCpuPostMem* placeholders

- Turbo ratio controls:
  - Added TurboRatioLimitRatio[8]/NumCore[8] for P-cores and
    AtomTurboRatio* arrays for E-cores

- Graphics/Media:
  - Added ConfigureGT toggle, RC1pGtFreqEnable, RC1pMediaFreqEnable
  - Added ConfigureMedia toggle, MediaStandby
  - Added PEI logo HorizontalResolution/VerticalResolution exports

- EC hooks:
  - Added EcProvisionEav and EcBiosGuardCmdLock function pointers

- USB/Type‑C:
  - Added EnableTcssCovTypeA[4] (convert Type‑C to Type‑A option)

- Misc renames/cleanups:
  - Numerous fields renamed from generic “ReservedXX” to more explicit
    RsvdXXX arrays with adjusted sizes.

Change-Id: I76748abdf6ddcae9c7f74975e09324bb45b5f9bd
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89093
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
---
 .../fsp/fsp2_0/meteorlake/x86_32/FspUpd.h     |    2 +-
 .../fsp/fsp2_0/meteorlake/x86_32/FspmUpd.h    | 2504 +++++++++++++++--
 .../fsp/fsp2_0/meteorlake/x86_32/FspsUpd.h    | 1665 ++++++++++-
 3 files changed, 3846 insertions(+), 325 deletions(-)

diff --git a/src/vendorcode/intel/fsp/fsp2_0/meteorlake/x86_32/FspUpd.h b/src/vendorcode/intel/fsp/fsp2_0/meteorlake/x86_32/FspUpd.h
index c4ca19b8b2..8cec707c7e 100644
--- a/src/vendorcode/intel/fsp/fsp2_0/meteorlake/x86_32/FspUpd.h
+++ b/src/vendorcode/intel/fsp/fsp2_0/meteorlake/x86_32/FspUpd.h
@@ -1,6 +1,6 @@
 /** @file
 
-Copyright (c) 2023, Intel Corporation. All rights reserved.<BR>
+Copyright (c) 2025, Intel Corporation. All rights reserved.<BR>
 
 Redistribution and use in source and binary forms, with or without modification,
 are permitted provided that the following conditions are met:
diff --git a/src/vendorcode/intel/fsp/fsp2_0/meteorlake/x86_32/FspmUpd.h b/src/vendorcode/intel/fsp/fsp2_0/meteorlake/x86_32/FspmUpd.h
index e0fa76b811..f73ca585c8 100644
--- a/src/vendorcode/intel/fsp/fsp2_0/meteorlake/x86_32/FspmUpd.h
+++ b/src/vendorcode/intel/fsp/fsp2_0/meteorlake/x86_32/FspmUpd.h
@@ -1,6 +1,6 @@
 /** @file
 
-Copyright (c) 2024, Intel Corporation. All rights reserved.<BR>
+Copyright (c) 2025, Intel Corporation. All rights reserved.<BR>
 
 Redistribution and use in source and binary forms, with or without modification,
 are permitted provided that the following conditions are met:
@@ -72,9 +72,12 @@ typedef struct {
 **/
   UINT8                       EnableAbove4GBMmio;
 
-/** Offset 0x004B - Reserved
+/** Offset 0x004B - Ibecc Ec Dis
+  This option enables or disables the Ibecc Control register Ec Dis field. Default
+  0 = Enabled.
+  $EN_DIS
 **/
-  UINT8                       Reserved0;
+  UINT8                       IbeccEcDis;
 
 /** Offset 0x004C - Memory SPD Pointer Controller 0 Channel 0 Dimm 0
   Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00
@@ -278,9 +281,21 @@ typedef struct {
 **/
   UINT8                       TrainTrace;
 
-/** Offset 0x012D - Reserved
+/** Offset 0x012D - RxVrefTempCoeff
+  Default = 6. Range from 0-255
 **/
-  UINT8                       Reserved1[3];
+  UINT8                       RxVrefTempCoeff;
+
+/** Offset 0x012E - CaParityPatternRotation
+  Default = 0 (Auto). 1 for High stress pattern rotation, 2 for no rotation.
+**/
+  UINT8                       CaParityPatternRotation;
+
+/** Offset 0x012F - WCK Offset
+  This option enables the WCK Offset WA for Hynix32 with freq >= 5600.
+  $EN_DIS
+**/
+  UINT8                       WckOffsetWa;
 
 /** Offset 0x0130 - Tseg Size
   Size of SMRAM memory reserved. 0x400000 for Release build and 0x1000000 for Debug build
@@ -331,9 +346,11 @@ typedef struct {
 **/
   UINT8                       DciEn;
 
-/** Offset 0x014A - Reserved
+/** Offset 0x014A - DCI Clock Enable
+  Enable/Disable DCI clock in lowest power state
+  $EN_DIS
 **/
-  UINT8                       Reserved2;
+  UINT8                       DciClkEnable;
 
 /** Offset 0x014B - DCI DbC Mode
   Disabled: Clear both USB2/3DBCEN; USB2: set USB2DBCEN; USB3: set USB3DBCEN; Both:
@@ -377,9 +394,16 @@ typedef struct {
 **/
   UINT16                      SocTraceHubMemReg1Size;
 
-/** Offset 0x0152 - Reserved
+/** Offset 0x0152 - Keep Early Trace
+  Trace is activated by default. When enable, keep early trace data and keep tracing,
+  may block s0ix.\n
+  When disabled will abandon trace data and stop tracing which allows enter s0ix\n
+  \n
+  noted:enable this option will not enable TraceHub; When probe is connected, keep
+  early trace will then be configured by tool, this option will not take effect.
+  $EN_DIS
 **/
-  UINT8                       Reserved3;
+  UINT8                       KeepEarlyTrace;
 
 /** Offset 0x0153 - PCH Trace Hub Mode
   Enable/Disable PCH TraceHub
@@ -409,9 +433,30 @@ typedef struct {
 **/
   UINT16                      PchTraceHubMemReg1Size;
 
-/** Offset 0x0158 - Reserved
+/** Offset 0x0158 - IOE Debug Enable
+  Enable/Disable IOE Debug. When enabled, IOE D2D Dfx link will keep up and clock
+  is enabled
+  $EN_DIS
 **/
-  UINT8                       Reserved4[4];
+  UINT8                       IoeDebugEn;
+
+/** Offset 0x0159 - Pmode Clock Enable
+  Enable/Disable PMODE clock. When enabled, Pmode clock will toggle for XDP use
+  $EN_DIS
+**/
+  UINT8                       PmodeClkEn;
+
+/** Offset 0x015A - AET Trace Hub Mode Select
+  Select AET to Trace Hub destination.
+  0:SOC Trace Hub, 1:PCH Trace Hub
+**/
+  UINT8                       AetTraceHubMode;
+
+/** Offset 0x015B - BIOS trace destination
+  Select BIOS trace destination.
+  0:SOC Trace Hub, 1:PCH Trace Hub
+**/
+  UINT8                       BiosTraceSinkMode;
 
 /** Offset 0x015C - HD Audio DMIC Link Clock Select
   Determines DMIC<N> Clock Source. 0: Both, 1: ClkA, 2: ClkB
@@ -470,9 +515,11 @@ typedef struct {
 **/
   UINT8                       InternalGfx;
 
-/** Offset 0x0189 - Reserved
+/** Offset 0x0189 - Oem T12 Dealy Override
+  Oem T12 Dealy Override. 0(Default)=Disable  1=Enable
+  $EN_DIS
 **/
-  UINT8                       Reserved5;
+  UINT8                       OemT12DelayOverride;
 
 /** Offset 0x018A - Board Type
   MrcBoardType, Options are 0=Mobile/Mobile Halo, 1=Desktop/DT Halo, 5=ULT/ULX/Mobile
@@ -481,9 +528,14 @@ typedef struct {
 **/
   UINT8                       UserBd;
 
-/** Offset 0x018B - Reserved
+/** Offset 0x018B - MRC Retraining on RTC Power Loss
+  Specifies whether MRC memory training will occur when RTC power loss is detected.
+  Options are 0=Memory will be re-trained if RTC power loss is detected. 1=Memory
+  will not be re-trained when RTC power loss is detected. (Typically used on board
+  designs without a dedicated RTC battery)
+  0:Disabled, 1:Enabled
 **/
-  UINT8                       Reserved6;
+  UINT8                       DisableMrcRetrainingOnRtcPowerLoss;
 
 /** Offset 0x018C - DDR Frequency Limit
   Maximum Memory Frequency Selections in Mhz. Options are 1067, 1333, 1600, 1867,
@@ -580,9 +632,257 @@ typedef struct {
 **/
   UINT8                       SpdProfileSelected;
 
-/** Offset 0x019C - Reserved
+/** Offset 0x019C - Dynamic Memory Boost
+  0(Default): Disable, 1: Enable. When enabled, MRC will train the Default SPD Profile,
+  and also the profile selected by SpdProfileSelected, to allow automatic switching
+  during runtime. Only valid if SpdProfileSelected is an XMP Profile, otherwise ignored.
+  $EN_DIS
 **/
-  UINT8                       Reserved7[102];
+  UINT8                       DynamicMemoryBoost;
+
+/** Offset 0x019D - Realtime Memory Frequency
+  0(Default): Disabled, 1: Enabled. Ignored unless SpdProfileSelected is XMP Profile
+  1. If enabled, MRC will train the Default SPD Profile, and also XMP Profile 1,
+  to allow manually triggered switching between frequencies at runtime.
+  $EN_DIS
+**/
+  UINT8                       RealtimeMemoryFrequency;
+
+/** Offset 0x019E - OC Safe Mode
+  Bitmap: Ignored unless SpdProfileSelected is an XMP Profile. Bit 0: Use safe tCL,
+  Bit 1: Limit tWR, tRTP, tCCD_L, tCCD_L_WR, tCL to of freq 6400 when programming
+  Dimm MR if DIMM doesn't support new spec.
+  $EN_DIS
+**/
+  UINT8                       OCSafeMode;
+
+/** Offset 0x019F - tRRSG Delta
+  Delay between Read-to-Read commands in the same Bank Group. 0 - Auto. Signed TAT
+  delta is (Value - 128). Input value range of [0..255] will give a TAT delta range
+  of [-127..127]
+**/
+  UINT8                       tRRSG;
+
+/** Offset 0x01A0 - tRRDG Delta
+  Delay between Read-to-Read commands in different Bank Group. 0 - Auto. Signed TAT
+  delta is (Value - 128). Input value range of [0..255] will give a TAT delta range
+  of [-127..127]
+**/
+  UINT8                       tRRDG;
+
+/** Offset 0x01A1 - tRRDR Delta
+  Delay between Read-to-Read commands in different Ranks. 0 - Auto. Signed TAT delta
+  is (Value - 128). Input value range of [0..255] will give a TAT delta range of
+  [-127..127]
+**/
+  UINT8                       tRRDR;
+
+/** Offset 0x01A2 - tRRDD Delta
+  Delay between Read-to-Read commands in different DIMMs. 0 - Auto. Signed TAT delta
+  is (Value - 128). Input value range of [0..255] will give a TAT delta range of
+  [-127..127]
+**/
+  UINT8                       tRRDD;
+
+/** Offset 0x01A3 - tWRSG Delta
+  Delay between Write-to-Read commands in the same Bank Group. 0 - Auto. Signed TAT
+  delta is (Value - 128). Input value range of [0..255] will give a TAT delta range
+  of [-127..127]
+**/
+  UINT8                       tWRSG;
+
+/** Offset 0x01A4 - tWRDG Delta
+  Delay between Write-to-Read commands in different Bank Group. 0 - Auto. Signed TAT
+  delta is (Value - 128). Input value range of [0..255] will give a TAT delta range
+  of [-127..127]
+**/
+  UINT8                       tWRDG;
+
+/** Offset 0x01A5 - tWRDR Delta
+  Delay between Write-to-Read commands in different Ranks. 0 - Auto. Signed TAT delta
+  is (Value - 128). Input value range of [0..255] will give a TAT delta range of
+  [-127..127]
+**/
+  UINT8                       tWRDR;
+
+/** Offset 0x01A6 - tWRDD Delta
+  Delay between Write-to-Read commands in different DIMMs. 0 - Auto. Signed TAT delta
+  is (Value - 128). Input value range of [0..255] will give a TAT delta range of
+  [-127..127]
+**/
+  UINT8                       tWRDD;
+
+/** Offset 0x01A7 - tWWSG Delta
+  Delay between Write-to-Write commands in the same Bank Group. 0 - Auto. Signed TAT
+  delta is (Value - 128). Input value range of [0..255] will give a TAT delta range
+  of [-127..127]
+**/
+  UINT8                       tWWSG;
+
+/** Offset 0x01A8 - tWWDG Delta
+  Delay between Write-to-Write commands in different Bank Group. 0 - Auto. Signed
+  TAT delta is (Value - 128). Input value range of [0..255] will give a TAT delta
+  range of [-127..127]
+**/
+  UINT8                       tWWDG;
+
+/** Offset 0x01A9 - tWWDR Delta
+  Delay between Write-to-Write commands in different Ranks. 0 - Auto. Signed TAT delta
+  is (Value - 128). Input value range of [0..255] will give a TAT delta range of
+  [-127..127]
+**/
+  UINT8                       tWWDR;
+
+/** Offset 0x01AA - tWWDD Delta
+  Delay between Write-to-Write commands in different DIMMs. 0 - Auto. Signed TAT delta
+  is (Value - 128). Input value range of [0..255] will give a TAT delta range of
+  [-127..127]
+**/
+  UINT8                       tWWDD;
+
+/** Offset 0x01AB - tRWSG Delta
+  Delay between Read-to-Write commands in the same Bank Group. 0 - Auto. Signed TAT
+  delta is (Value - 128). Input value range of [0..255] will give a TAT delta range
+  of [-127..127]
+**/
+  UINT8                       tRWSG;
+
+/** Offset 0x01AC - tRWDG Delta
+  Delay between Read-to-Write commands in different Bank Group. 0 - Auto. Signed TAT
+  delta is (Value - 128). Input value range of [0..255] will give a TAT delta range
+  of [-127..127]
+**/
+  UINT8                       tRWDG;
+
+/** Offset 0x01AD - tRWDR Delta
+  Delay between Read-to-Write commands in different Ranks. 0 - Auto. Signed TAT delta
+  is (Value - 128). Input value range of [0..255] will give a TAT delta range of
+  [-127..127]
+**/
+  UINT8                       tRWDR;
+
+/** Offset 0x01AE - tRWDD Delta
+  Delay between Read-to-Write commands in different DIMMs. 0 - Auto. Signed TAT delta
+  is (Value - 128). Input value range of [0..255] will give a TAT delta range of
+  [-127..127]
+**/
+  UINT8                       tRWDD;
+
+/** Offset 0x01AF
+**/
+  UINT8                       Rsvd031[1];
+
+/** Offset 0x01B0 - tREFI32
+  Refresh Interval, 0: AUTO, max: 131071. Only used if FspmUpd->FspmConfig.SpdProfileSelected
+  == 1 (Custom Profile).
+**/
+  UINT32                      tREFI32;
+
+/** Offset 0x01B4 - Vddq Voltage Override for NMOS
+  # is multiple of 1mV where 0 means Auto.
+**/
+  UINT16                      VddqNmosVoltageOverride;
+
+/** Offset 0x01B6 - Config BitMask to limit max freq at 3200
+  BitMask where BIT0: 1R1R_8GB, BIT1: 1R1R_12GB, BIT2: 1R1R_16GB, BIT3: 1R1R_24GB,
+  BIT4: 1R1R_8GB_12GB, BIT5: 1R1R_8GB_16GB, BIT6: 1R1R_8GB_24GB, BIT7: 1R1R_12GB_16GB,
+  BIT8: 1R1R_12GB_24GB, BIT9: 1R1R_16GB_24GB, BIT10: 2R2R_32GB, BIT11: 2R2R_48GB,
+  BIT12: 2R2R_32GB_48GB
+**/
+  UINT16                      FreqLimit3200Mask;
+
+/** Offset 0x01B8 - Config BitMask to limit max freq at 3600
+  BitMask where BIT0: 1R1R_8GB, BIT1: 1R1R_12GB, BIT2: 1R1R_16GB, BIT3: 1R1R_24GB,
+  BIT4: 1R1R_8GB_12GB, BIT5: 1R1R_8GB_16GB, BIT6: 1R1R_8GB_24GB, BIT7: 1R1R_12GB_16GB,
+  BIT8: 1R1R_12GB_24GB, BIT9: 1R1R_16GB_24GB, BIT10: 2R2R_32GB, BIT11: 2R2R_48GB,
+  BIT12: 2R2R_32GB_48GB
+**/
+  UINT16                      FreqLimit3600Mask;
+
+/** Offset 0x01BA - Config BitMask to limit max freq at 4000
+  BitMask where BIT0: 1R1R_8GB, BIT1: 1R1R_12GB, BIT2: 1R1R_16GB, BIT3: 1R1R_24GB,
+  BIT4: 1R1R_8GB_12GB, BIT5: 1R1R_8GB_16GB, BIT6: 1R1R_8GB_24GB, BIT7: 1R1R_12GB_16GB,
+  BIT8: 1R1R_12GB_24GB, BIT9: 1R1R_16GB_24GB, BIT10: 2R2R_32GB, BIT11: 2R2R_48GB,
+  BIT12: 2R2R_32GB_48GB
+**/
+  UINT16                      FreqLimit4000Mask;
+
+/** Offset 0x01BC - Config BitMask to limit max freq at 4400
+  BitMask where BIT0: 1R1R_8GB, BIT1: 1R1R_12GB, BIT2: 1R1R_16GB, BIT3: 1R1R_24GB,
+  BIT4: 1R1R_8GB_12GB, BIT5: 1R1R_8GB_16GB, BIT6: 1R1R_8GB_24GB, BIT7: 1R1R_12GB_16GB,
+  BIT8: 1R1R_12GB_24GB, BIT9: 1R1R_16GB_24GB, BIT10: 2R2R_32GB, BIT11: 2R2R_48GB,
+  BIT12: 2R2R_32GB_48GB
+**/
+  UINT16                      FreqLimit4400Mask;
+
+/** Offset 0x01BE - Config BitMask to limit max freq at 4800
+  BitMask where BIT0: 1R1R_8GB, BIT1: 1R1R_12GB, BIT2: 1R1R_16GB, BIT3: 1R1R_24GB,
+  BIT4: 1R1R_8GB_12GB, BIT5: 1R1R_8GB_16GB, BIT6: 1R1R_8GB_24GB, BIT7: 1R1R_12GB_16GB,
+  BIT8: 1R1R_12GB_24GB, BIT9: 1R1R_16GB_24GB, BIT10: 2R2R_32GB, BIT11: 2R2R_48GB,
+  BIT12: 2R2R_32GB_48GB
+**/
+  UINT16                      FreqLimit4800Mask;
+
+/** Offset 0x01C0 - Config BitMask to limit max freq at 5200
+  BitMask where BIT0: 1R1R_8GB, BIT1: 1R1R_12GB, BIT2: 1R1R_16GB, BIT3: 1R1R_24GB,
+  BIT4: 1R1R_8GB_12GB, BIT5: 1R1R_8GB_16GB, BIT6: 1R1R_8GB_24GB, BIT7: 1R1R_12GB_16GB,
+  BIT8: 1R1R_12GB_24GB, BIT9: 1R1R_16GB_24GB, BIT10: 2R2R_32GB, BIT11: 2R2R_48GB,
+  BIT12: 2R2R_32GB_48GB
+**/
+  UINT16                      FreqLimit5200Mask;
+
+/** Offset 0x01C2 - Config BitMask to limit max freq at 5600
+  BitMask where BIT0: 1R1R_8GB, BIT1: 1R1R_12GB, BIT2: 1R1R_16GB, BIT3: 1R1R_24GB,
+  BIT4: 1R1R_8GB_12GB, BIT5: 1R1R_8GB_16GB, BIT6: 1R1R_8GB_24GB, BIT7: 1R1R_12GB_16GB,
+  BIT8: 1R1R_12GB_24GB, BIT9: 1R1R_16GB_24GB, BIT10: 2R2R_32GB, BIT11: 2R2R_48GB,
+  BIT12: 2R2R_32GB_48GB
+**/
+  UINT16                      FreqLimit5600Mask;
+
+/** Offset 0x01C4 - 2DPC Enhanced Frequency Limit
+  Enable/Disable Enhanced FreqLimit for 2DPC
+  $EN_DIS
+**/
+  UINT8                       FreqLimitMaskEn;
+
+/** Offset 0x01C5 - LP5x DRAM glitch workaround
+  TA#814867 DRAM vendor-specific workaround, will increase boot time.
+  $EN_DIS
+**/
+  UINT8                       lp5GlitchWAEnable;
+
+/** Offset 0x01C6 - Initial DDR5 TxVref Override
+  Override for initial DDR5 TxVref value , 0 = Auto (default), valid range from 350
+  to 975, in increments of 5
+**/
+  UINT16                      TxVrefOverride;
+
+/** Offset 0x01C8 - Force CKD in Bypass Mode
+  Enable/Disable Force CKD in Bypass Mode
+  $EN_DIS
+**/
+  UINT8                       IsForceCkdBypass;
+
+/** Offset 0x01C9 - VendorForceDdr5G4
+  Default = 0. Range from 0-2
+**/
+  UINT8                       VendorForceDdr5G4;
+
+/** Offset 0x01CA - Increase External Coarse WrLvl sweep
+  Enable/Disable Increase two extra clocks to External Coarse WrLvl sweep
+  $EN_DIS
+**/
+  UINT8                       Ddr5WrLvlMinLimit;
+
+/** Offset 0x01CB
+**/
+  UINT8                       Rsvd036[53];
+
+/** Offset 0x0200 - Vdd2Mv
+  VDD2 in MilliVolts. <b>0=Platform Default (no override), 1200=1.2V, 1350=1.35V etc.
+  0:Default, 1200:1.20 Volts, 1350:1.35 Volts ...
+**/
+  UINT16                      Vdd2Mv;
 
 /** Offset 0x0202 - Memory Reference Clock
   100MHz, 133MHz.
@@ -590,9 +890,44 @@ typedef struct {
 **/
   UINT8                       RefClk;
 
-/** Offset 0x0203 - Reserved
+/** Offset 0x0203
 **/
-  UINT8                       Reserved8[9];
+  UINT8                       Rsvd032[1];
+
+/** Offset 0x0204 - Safe Loading Bios Enable State
+  0: Disabled(Default), 1: Enabled. If enabled, Memory diagnostic will perform for
+  TSEG Region.
+  $EN_DIS
+**/
+  UINT8                       SafeLoadingBiosEnableState;
+
+/** Offset 0x0205 - Ppr Recovery Status Enable
+  0: Disabled(Default), 1: Enabled.  If enabled, PPR Recovery flow will get Trigger.
+  $EN_DIS
+**/
+  UINT8                       PprRecoveryStatusEnable;
+
+/** Offset 0x0206 - Tseg Memory Test Status
+   If enabled, PPR Recovery flow will get Trigger
+  0: PASS, 1: FAIL(Default)
+**/
+  UINT8                       TsegMemoryTestStatus;
+
+/** Offset 0x0207 - Mrc Ppr Status
+   Get Mrc PPR Status after PPR Recovery flow will get Trigger
+  0: PASS, 1: FAIL(Default)
+**/
+  UINT8                       MrcPprStatus;
+
+/** Offset 0x0208 - Tseg Retry Count
+  Tseg Retry count will increase based on TSEG Region Fail count
+  0: Default, 1:3
+**/
+  UINT8                       RetryCount;
+
+/** Offset 0x0209
+**/
+  UINT8                       Rsvd035[3];
 
 /** Offset 0x020C - Memory Vdd Voltage
   DRAM voltage (Vdd) (supply voltage for input buffers and core logic of the DRAM
@@ -602,9 +937,17 @@ typedef struct {
 **/
   UINT16                      VddVoltage;
 
-/** Offset 0x020E - Reserved
+/** Offset 0x020E - Memory VDDQ Voltage
+  DRAM voltage (Vddq) (supply voltage for DQ/DQS of the DRAM chips) in millivolts
+  from 0 - default to 1435mv.
 **/
-  UINT8                      Reserved9[4];
+  UINT16                      VddqVoltage;
+
+/** Offset 0x0210 - Memory VPP Voltage
+  DRAM voltage (Vpp) (supply voltage for VPP of the DRAM chips) in millivolts from
+  0 - default to 2135mv.
+**/
+  UINT16                      VppVoltage;
 
 /** Offset 0x0212 - Memory Ratio
   Automatic or the frequency will equal ratio times reference clock. Set to Auto to
@@ -643,9 +986,9 @@ typedef struct {
 **/
   UINT8                       tRCDtRP;
 
-/** Offset 0x021B - Reserved
+/** Offset 0x021B
 **/
-  UINT8                       Reserved10;
+  UINT8                       Rsvd040[1];
 
 /** Offset 0x021C - tREFI
   Obsolete, use tREFI32 instead. Refresh Interval, 0: AUTO, max: 65535. Only used
@@ -685,9 +1028,59 @@ typedef struct {
 **/
   UINT8                       tWTR;
 
-/** Offset 0x0224 - Reserved
+/** Offset 0x0224 - tRFCpb
+  Min Internal per bank refresh recovery delay time, 0: AUTO, max: 0xFFFF. Only used
+  if FspmUpd->FspmConfig.SpdProfileSelected == 1 (Custom Profile).
 **/
-  UINT8                      Reserved11[12];
+  UINT16                      tRFCpb;
+
+/** Offset 0x0226 - tRFC2
+  Min Internal refresh recovery delay time, 0: AUTO, max: 0xFFFF. Only used if FspmUpd->FspmConfig.SpdProfileSelected
+  == 1 (Custom Profile).
+**/
+  UINT16                      tRFC2;
+
+/** Offset 0x0228 - tRFC4
+  Min Internal refresh recovery delay time, 0: AUTO, max: 0xFFFF. Only used if FspmUpd->FspmConfig.SpdProfileSelected
+  == 1 (Custom Profile).
+**/
+  UINT16                      tRFC4;
+
+/** Offset 0x022A - tRRD_L
+  Min Internal row active to row active delay time for same bank groups, 0: AUTO,
+  max: 80. Only used if FspmUpd->FspmConfig.SpdProfileSelected == 1 (Custom Profile).
+**/
+  UINT8                       tRRD_L;
+
+/** Offset 0x022B - tRRD_S
+  Min Internal row active to row active delay time for different bank groups, 0: AUTO,
+  max: 80. Only used if FspmUpd->FspmConfig.SpdProfileSelected == 1 (Custom Profile).
+**/
+  UINT8                       tRRD_S;
+
+/** Offset 0x022C - tWTR_L
+  Min Internal write to read command delay time for same bank groups, 0: AUTO, max:
+  127. Only used if FspmUpd->FspmConfig.SpdProfileSelected == 1 (Custom Profile).
+**/
+  UINT8                       tWTR_L;
+
+/** Offset 0x022D - tCCD_L
+  Min Internal CAS-to-CAS delay for same bank group, 0: AUTO, max: 80. Only used if
+  FspmUpd->FspmConfig.SpdProfileSelected == 1 (Custom Profile).
+**/
+  UINT8                       tCCD_L;
+
+/** Offset 0x022E - tCCD_L_WR
+  Min Internal Write-to-Write delay for same bank group, 0: AUTO, max: 150. Only used
+  if FspmUpd->FspmConfig.SpdProfileSelected == 1 (Custom Profile).
+**/
+  UINT8                       tCCD_L_WR;
+
+/** Offset 0x022F - tWTR_S
+  Min Internal write to read command delay time for different bank groups, 0: AUTO,
+  max: 50. Only used if FspmUpd->FspmConfig.SpdProfileSelected == 1 (Custom Profile).
+**/
+  UINT8                       tWTR_S;
 
 /** Offset 0x0230 - NMode
   System command rate, range 0-2, 0 means auto, 1 = 1N, 2 = 2N
@@ -706,9 +1099,21 @@ typedef struct {
 **/
   UINT8                       PchIshEnable;
 
-/** Offset 0x0233 - Reserved
+/** Offset 0x0233 - Dimm DFE Tap1 Step Size Setting
+  Dimm DFE Tap1 setting: Memory-dependent, positive value will be converted to minus
+  values by *-1 automatically
 **/
-  UINT8                       Reserved12[7];
+  UINT8                       DFETap1StepSize;
+
+/** Offset 0x0234 - Dimm DFE Tap2 Step Size Setting
+  Dimm DFE Tap2 setting: Memory-dependent, positive value will be converted to minus
+  values by *-1 automatically
+**/
+  UINT8                       DFETap2StepSize;
+
+/** Offset 0x0235
+**/
+  UINT8                       Rsvd041[5];
 
 /** Offset 0x023A - SAGV Gear Ratio
   Gear Selection for SAGV points. 0 - Auto, 2-Gear 2, 4-Gear 4
@@ -725,9 +1130,62 @@ typedef struct {
 **/
   UINT8                       GearRatio;
 
-/** Offset 0x0247 - Reserved
+/** Offset 0x0247 - LPDDR ODT RttWr
+  Initial RttWr for LP4/5 in Ohms. 0x0 - Auto
 **/
-  UINT8                       Reserved13[69];
+  UINT8                       LpddrRttWr;
+
+/** Offset 0x0248 - LPDDR ODT RttCa
+  Initial RttCa for LP4/5 in Ohms. 0x0 - Auto
+**/
+  UINT8                       LpddrRttCa;
+
+/** Offset 0x0249 - Dimm Odt settings
+  Dimm Odt settings of 2 DIMMs of a channel: Memory-dependent, 0: AUTO, max: 0xFFFF
+  meaning disabling
+**/
+  UINT8                       DimmOdt[44];
+
+/** Offset 0x0275 - Dimm DFE Tap1 settings Deprecated
+  Dimm DFE Tap1 settings: Memory-dependent, positive values will be converted to minus
+  values by *-1 automatically
+**/
+  UINT8                       DFETap1[8];
+
+/** Offset 0x027D - Dimm DFE Tap2 settings Deprecated
+  Dimm DFE Tap2 settings: Memory-dependent, positive values will be converted to minus
+  values by *-1 automatically
+**/
+  UINT8                       DFETap2[8];
+
+/** Offset 0x0285 - CsVrefLow
+  DDR5 Cs Sweep Low Vref Value, 0: AUTO, max: 125.
+**/
+  UINT8                       CsVrefLow;
+
+/** Offset 0x0286 - CsVrefHigh
+  DDR5 Cs Sweep High Vref Value, 0: AUTO, max: 125.
+**/
+  UINT8                       CsVrefHigh;
+
+/** Offset 0x0287 - CaVrefLow
+  DDR5 Ca Sweep Low Vref Value, 0: AUTO, max: 125.
+**/
+  UINT8                       CaVrefLow;
+
+/** Offset 0x0288 - CaVrefHigh
+  DDR5 Ca Sweep High Vref Value, 0: AUTO, max: 125.
+**/
+  UINT8                       CaVrefHigh;
+
+/** Offset 0x0289
+**/
+  UINT8                       Rsvd050[1];
+
+/** Offset 0x028A - RxVrefOffset
+  DDR5 RxVref Offset Value, 0: AUTO, max: 1600.
+**/
+  UINT16                      RxVrefOffset;
 
 /** Offset 0x028C - MMIO size adjustment for AUTO mode
   Positive number means increasing MMIO size, Negative value means decreasing MMIO
@@ -741,9 +1199,12 @@ typedef struct {
 **/
   UINT8                       PrimaryDisplay;
 
-/** Offset 0x028F - Reserved
+/** Offset 0x028F - Internal Graphics Data Stolen Memory GSM2
+  Size of memory preallocated for internal graphics GSM2.
+  0:2GB, 1:4GB, 2:6GB, 3:8GB, 4:10GB, 5:12GB, 6:14GB, 7:16GB, 8:18GB, 9:20GB, 10:22GB,
+  11:24GB, 12:26GB, 13:28GB, 14:30GB, 15:32GB, 0xFF:No Allocation
 **/
-  UINT8                       Reserved14;
+  UINT8                       IgdGsm2Size;
 
 /** Offset 0x0290 - Temporary MMIO address for GMADR
   Obsolete field now and it has been extended to 64 bit address, used LMemBar
@@ -814,9 +1275,9 @@ typedef struct {
 **/
   UINT8                       RealtimeMemoryTiming;
 
-/** Offset 0x02A6 - Reserved
+/** Offset 0x02A6
 **/
-  UINT8                       Reserved15;
+  UINT8                       Rsvd065;
 
 /** Offset 0x02A7 - Enable/Disable SA IPU
   Enable(Default): Enable SA IPU, Disable: Disable SA IPU
@@ -933,9 +1394,22 @@ typedef struct {
 **/
   UINT8                       DisplayGpioPinMux;
 
-/** Offset 0x02BF - Reserved
+/** Offset 0x02BF - FrameBuffer via DSM or LMem, when FrameBuffer is pointing to DSM region this option should be enabled
+  0=Disable, 1(Default)=Enable
+  $EN_DIS
 **/
-  UINT8                       Reserved16[17];
+  UINT8                       ConfigureDsmMtrr;
+
+/** Offset 0x02C0
+**/
+  UINT8                       Rsvd070[8];
+
+/** Offset 0x02C8 - Temporary MMIO address for GMADR
+  The reference code will use this as Temporary MMIO address space to access GMADR
+  Registers.Platform should provide conflict free Temporary MMIO Range: GmAdr to
+  (GmAdr + 256MB). Default is (PciExpressBaseAddress - 256MB) to (PciExpressBaseAddress - 0x1)
+**/
+  UINT64                      LMemBar;
 
 /** Offset 0x02D0 - Per-core HT Disable
   Defines the per-core HT disable mask where: 1 - Disable selected logical core HT,
@@ -945,9 +1419,27 @@ typedef struct {
 **/
   UINT16                      PerCoreHtDisable;
 
-/** Offset 0x02D2 - Reserved
+/** Offset 0x02D2 - SA/Uncore voltage mode
+  SA/Uncore voltage mode; <b>0: Adaptive</b>; 1: Override.
+  $EN_DIS
 **/
-  UINT8                       Reserved17[6];
+  UINT8                       SaVoltageMode;
+
+/** Offset 0x02D3
+**/
+  UINT8                       Rsvd080[1];
+
+/** Offset 0x02D4 - SA/Uncore Voltage Override
+  The SA/Uncore voltage override applicable when SA/Uncore voltage mode is in Override
+  mode. Valid Range 0 to 2000
+**/
+  UINT16                      SaVoltageOverride;
+
+/** Offset 0x02D6 - SA/Uncore Adaptive voltage
+  Adaptive voltage applicable when SA/Uncore voltage mode is in Adaptive mode. Valid
+  Range 0 to 2000
+**/
+  UINT16                      SaAdaptiveVoltage;
 
 /** Offset 0x02D8 - Thermal Velocity Boost Ratio clipping
   0: Disabled, 1(Default): Enabled. This service controls Core frequency reduction
@@ -964,9 +1456,22 @@ typedef struct {
 **/
   UINT8                       TvbVoltageOptimization;
 
-/** Offset 0x02DA - Reserved
+/** Offset 0x02DA - PCIE Resizable BAR Support
+  Enable/Disable PCIE Resizable BAR Support.0: Disable; 1: Enable; 2: Auto(Default).
+  $EN_DIS
 **/
-  UINT8                       Reserved18[45];
+  UINT8                       PcieResizableBarSupport;
+
+/** Offset 0x02DB - PCH DMI Gen3 Root port preset values per lane
+  Used for programming DMI Gen3 preset values per lane. Range: 0-9, 4 is default for each lane
+**/
+  UINT8                       PchDmiGen4RootPortPreset[8];
+
+/** Offset 0x02E3 - SaPreMemProductionRsvd
+  Reserved for SA Pre-Mem Production
+  $EN_DIS
+**/
+  UINT8                       SaPreMemProductionRsvd[36];
 
 /** Offset 0x0307 - DMI Max Link Speed
   Auto (Default)(0x0): Maximum possible link speed, Gen1(0x1): Limit Link to Gen1
@@ -1020,9 +1525,11 @@ typedef struct {
 **/
   UINT8                       DmiAspm;
 
-/** Offset 0x0324 - Reserved
+/** Offset 0x0324 - PCH DMI ASPM Configuration:{Combo
+  Set ASPM Configuration
+  0:Disabled, 1:L0s, 2:L1, 3:L1L0s
 **/
-  UINT8                       Reserved19;
+  UINT8                       PchDmiAspm;
 
 /** Offset 0x0325 - Enable/Disable DMI GEN3 Hardware Eq
   Enable/Disable DMI GEN3 Hardware Eq. Disabled(0x0): Disable Hardware Eq, Enabled(0x1)(Default):
@@ -1073,9 +1580,43 @@ typedef struct {
 **/
   UINT8                       DmiGen3Ltcpo[8];
 
-/** Offset 0x033A - Reserved
+/** Offset 0x033A - Enable/Disable DMI Gen3 EQ Local Transmitter Coefficient Override Enable
+  Program Gen3 EQ Local Transmitter Coefficient Override. Disabled(0x0): Disable Local
+  Transmitter Coefficient Override, Enabled(0x1)(Default): Enable  Local Transmitter
+  Coefficient Override
+  $EN_DIS
 **/
-  UINT8                       Reserved20[34];
+  UINT8                       PchDmiGen3LtcoEnable;
+
+/** Offset 0x033B - Enable/Disable DMI Gen3 EQ Remote Transmitter Coefficient/Preset Override Enable
+  Program Remote Transmitter Coefficient/Preset Override. Disabled(0x0)(Default):
+  Disable Remote Transmitter Coefficient/Preset Override, Enabled(0x1): Enable  Remote
+  Transmitter Coefficient/Preset Override
+  $EN_DIS
+**/
+  UINT8                       PchDmiGen3RtcoRtpoEnable;
+
+/** Offset 0x033C - PCH DMI Gen3 Transmitter Pre-Cursor Coefficient
+  Used for programming DMI Gen3 Transmitter Pre-Cursor Coefficient . Range: 0-10,
+  2 is default for each lane
+**/
+  UINT8                       PchDmiGen3Ltcpre[8];
+
+/** Offset 0x0344 - PCH DMI Gen3 Transmitter Post-Cursor Coefficient
+  Used for programming Transmitter Post-Cursor Coefficient. Range: 0-9, 2 is default
+  for each lane
+**/
+  UINT8                       PchDmiGen3Ltcpo[8];
+
+/** Offset 0x034C - PCIE Hw Eq Gen3 CoeffList Cm
+  DMI_EQ_PARAM. Coefficient C-1.
+**/
+  UINT8                       DmiHwEqGen3CoeffListCm[8];
+
+/** Offset 0x0354 - PCIE Hw Eq Gen3 CoeffList Cp
+  DMI_EQ_PARAM. Coefficient C+1.
+**/
+  UINT8                       DmiHwEqGen3CoeffListCp[8];
 
 /** Offset 0x035C - Enable/Disable DMI GEN3 DmiGen3DsPresetEnable
   Enable/Disable DMI GEN3 DmiGen3DsPreset. Auto(0x0)(Default): DmiGen3DsPresetEnable,
@@ -1115,18 +1656,181 @@ typedef struct {
 **/
   UINT8                       DmiGen3UsPortTxPreset[8];
 
-/** Offset 0x037E - Reserved
+/** Offset 0x037E - DMI Hw Eq Gen4 CoeffList Cm
+  DMI_EQ_PARAM. Coefficient C-1.
 **/
-  UINT8                       Reserved21[54];
+  UINT8                       DmiHwEqGen4CoeffListCm[8];
+
+/** Offset 0x0386 - DMI Hw Eq Gen4 CoeffList Cp
+  DMI_EQ_PARAM. Coefficient C+1.
+**/
+  UINT8                       DmiHwEqGen4CoeffListCp[8];
+
+/** Offset 0x038E - Enable/Disable DMI GEN4 Phase 23 Bypass
+  DMI GEN4 Phase 23 Bypass. Disabled(0x0)(Default): Disable Phase 23 Bypass, Enabled(0x1):
+  Enable  Phase 23 Bypass
+  $EN_DIS
+**/
+  UINT8                       Gen4EqPhase23Bypass;
+
+/** Offset 0x038F - Enable/Disable DMI GEN4 Phase 3 Bypass
+  DMI GEN3 Phase 4 Bypass. Disabled(0x0)(Default): Disable Phase 3 Bypass, Enabled(0x1):
+  Enable  Phase 3 Bypass
+  $EN_DIS
+**/
+  UINT8                       Gen4EqPhase3Bypass;
+
+/** Offset 0x0390 - Enable/Disable DMI GEN4 DmiGen4DsPresetEnable
+  Enable/Disable DMI GEN4 DmiGen4DsPreset. Auto(0x0)(Default): DmiGen4DsPresetEnable,
+  Manual(0x1): Enable DmiGen4DsPresetEnable
+  $EN_DIS
+**/
+  UINT8                       DmiGen4DsPresetEnable;
+
+/** Offset 0x0391 - DMI Gen4 Root port preset Tx values per lane
+  Used for programming DMI Gen4 preset values per lane. Range: 0-10, 7 is default
+  for each lane
+**/
+  UINT8                       DmiGen4DsPortTxPreset[8];
+
+/** Offset 0x0399 - Enable/Disable DMI Gen4 EQ Remote Transmitter Coefficient/Preset Override Enable
+  Program Remote Transmitter Coefficient/Preset Override. Disabled(0x0)(Default):
+  Disable Remote Transmitter Coefficient/Preset Override, Enabled(0x1): Enable  Remote
+  Transmitter Coefficient/Preset Override
+  $EN_DIS
+**/
+  UINT8                       Gen4RtcoRtpoEnable;
+
+/** Offset 0x039A - Enable/Disable DMI Gen4 EQ Local Transmitter Coefficient Override Enable
+  Program Gen3 EQ Local Transmitter Coefficient Override. Disabled(0x0)(Default):
+  Disable Local Transmitter Coefficient Override, Enabled(0x1): Enable  Local Transmitter
+  Coefficient Override
+  $EN_DIS
+**/
+  UINT8                       Gen4LtcoEnable;
+
+/** Offset 0x039B - DMI Gen4 Transmitter Pre-Cursor Coefficient
+  Used for programming DMI Gen4 Transmitter Pre-Cursor Coefficient . Range: 0-10,
+  0 is default for each lane
+**/
+  UINT8                       DmiGen4Ltcpre[8];
+
+/** Offset 0x03A3 - DMI Gen4 Transmitter Post-Cursor Coefficient
+  Used for programming DMI Gen4 Transmitter Post-Cursor Coefficient. Range: 0-9, 8
+  is default for each lane
+**/
+  UINT8                       DmiGen4Ltcpo[8];
+
+/** Offset 0x03AB - Enable/Disable DMI GEN4 DmiGen4UsPresetEnable
+  Enable/Disable DMI GEN4 DmiGen4UsPreset. Auto(0x0)(Default): DmiGen4UsPresetEnable,
+  Manual(0x1): Enable DmiGen4UsPresetEnable
+  $EN_DIS
+**/
+  UINT8                       DmiGen4UsPresetEnable;
+
+/** Offset 0x03AC - DMI Gen4 Root port preset Tx values per lane
+  Used for programming DMI Gen4 preset values per lane. Range: 0-10, 1 is default
+  for each lane
+**/
+  UINT8                       DmiGen4UsPortTxPreset[8];
 
 /** Offset 0x03B4 - DMI ASPM L1 exit Latency
   Range: 0-7, 4 is default L1 exit Latency
 **/
   UINT8                       DmiAspmL1ExitLatency;
 
-/** Offset 0x03B5 - Reserved
+/** Offset 0x03B5 - Enable/Disable PCH DMI Gen4 EQ Remote Transmitter Coefficient/Preset Override Enable
+  Program Remote Transmitter Coefficient/Preset Override. Disabled(0x0)(Default):
+  Disable Remote Transmitter Coefficient/Preset Override, Enabled(0x1): Enable  Remote
+  Transmitter Coefficient/Preset Override
+  $EN_DIS
 **/
-  UINT8                       Reserved22[63];
+  UINT8                       PchDmiGen4RtcoRtpoEnable;
+
+/** Offset 0x03B6 - Enable/Disable PCH DMI Gen4 EQ Local Transmitter Coefficient Override Enable
+  Program Gen3 EQ Local Transmitter Coefficient Override. Disabled(0x0)(Default):
+  Disable Local Transmitter Coefficient Override, Enabled(0x1): Enable  Local Transmitter
+  Coefficient Override
+  $EN_DIS
+**/
+  UINT8                       PchDmiGen4LtcoEnable;
+
+/** Offset 0x03B7 - PCH DMI Gen4 Transmitter Post-Cursor Coefficient
+  Used for programming DMI Gen4 Transmitter Post-Cursor Coefficient. Range: 0-9, 8
+  is default for each lane
+**/
+  UINT8                       PchDmiGen4Ltcpo[8];
+
+/** Offset 0x03BF - PCH DMI ASPM L1 exit Latency
+  Range: 0-7, 4 is default L1 exit Latency
+**/
+  UINT8                       PchDmiAspmL1ExitLatency;
+
+/** Offset 0x03C0 - PCH DMI Gen4 Transmitter Pre-Cursor Coefficient
+  Used for programming DMI Gen4 Transmitter Pre-Cursor Coefficient . Range: 0-10,
+  0 is default for each lane
+**/
+  UINT8                       PchDmiGen4Ltcpre[8];
+
+/** Offset 0x03C8 - L1SS State Control Policy
+  Choose the L1SS State Control Policy, <b>Default = 0 </b>
+  0: Auto, 1: L1.2
+**/
+  UINT8                       DmiL1ssEnable;
+
+/** Offset 0x03C9
+**/
+  UINT8                       Rsvd085[7];
+
+/** Offset 0x03D0 - Temporary address for NvmeHcPeiMmioBase
+  The reference code will use this as Temporary address space
+**/
+  UINT32                      NvmeHcPeiMmioBase;
+
+/** Offset 0x03D4 - Temporary address for NvmeHcPeiMmioLimit
+  The reference code will use this as Temporary address space
+**/
+  UINT32                      NvmeHcPeiMmioLimit;
+
+/** Offset 0x03D8 - Temporary address for AhciPeiMmioBase
+  The reference code will use this as Temporary address space
+**/
+  UINT32                      AhciPeiMmioBase;
+
+/** Offset 0x03DC - Temporary address for AhciPeiMmioLimit
+  The reference code will use this as Temporary address space
+**/
+  UINT32                      AhciPeiMmioLimit;
+
+/** Offset 0x03E0 - Temporary address for EcExtraIoBase
+  The reference code will use this as Temporary address space
+**/
+  UINT16                      EcExtraIoBase;
+
+/** Offset 0x03E2 - Temporary address for SioBaseAddress
+  The reference code will use this as Temporary address space
+**/
+  UINT16                      SioBaseAddress;
+
+/** Offset 0x03E4 - Temporary address for ApicLocalAddress
+  The reference code will use this as Temporary address space
+**/
+  UINT32                      ApicLocalAddress;
+
+/** Offset 0x03E8 - Temporary CfgBar address for VMD
+  The reference code will use this as Temporary address space
+**/
+  UINT32                      VmdCfgBarBar;
+
+/** Offset 0x03EC - Temporary MemBar1 address for VMD
+  The reference code will use this as Temporary address space
+**/
+  UINT32                      VmdMemBar1Bar;
+
+/** Offset 0x03F0 - Temporary MemBar2 address for VMD
+  The reference code will use this as Temporary address space
+**/
+  UINT32                      VmdMemBar2Bar;
 
 /** Offset 0x03F4 - BIST on Reset
   Enable/Disable BIST (Built-In Self Test) on reset. <b>0: Disable</b>; 1: Enable.
@@ -1189,9 +1893,11 @@ typedef struct {
 **/
   UINT8                       CpuRatio;
 
-/** Offset 0x03FE - Reserved
+/** Offset 0x03FE - Boot max frequency
+  Enable Boot Maximum Frequency in CPU strap. 0: Disable; <b>1: Enable</b>
+  $EN_DIS
 **/
-  UINT8                       Reserved23;
+  UINT8                       BootMaxFrequency;
 
 /** Offset 0x03FF - Number of active big cores
   Number of P-cores to enable in each processor package. Note: Number of P-Cores and
@@ -1233,9 +1939,9 @@ typedef struct {
 **/
   UINT8                       BclkAdaptiveVoltage;
 
-/** Offset 0x0405 - Reserved
+/** Offset 0x0405
 **/
-  UINT8                       Reserved24;
+  UINT8                       Rsvd090[1];
 
 /** Offset 0x0406 - core voltage override
   The core voltage override which is applied to the entire range of cpu core frequencies.
@@ -1321,9 +2027,49 @@ typedef struct {
 **/
   UINT8                       DebugInterfaceLockEnable;
 
-/** Offset 0x041A - Reserved
+/** Offset 0x041A - DFD Enable
+  Enable or Disable DFD. <b>0: Disable</b>, 1:Enable
+  $EN_DIS
 **/
-  UINT8                       Reserved25[67];
+  UINT8                       DfdEnable;
+
+/** Offset 0x041B
+**/
+  UINT8                       Rsvd100[1];
+
+/** Offset 0x041C - Per-Atom-Cluster VF Offset
+  Array used to specifies the selected Atom Core Cluster Offset Voltage. This voltage
+  is specified in millivolts.
+**/
+  UINT16                      PerAtomClusterVoltageOffset[8];
+
+/** Offset 0x042C - Per-Atom-Cluster VF Offset Prefix
+  Sets the PerAtomCLusterVoltageOffset value as positive or negative for the selected
+  Core; <b>0: Positive </b>; 1: Negative.
+**/
+  UINT8                       PerAtomClusterVoltageOffsetPrefix[8];
+
+/** Offset 0x0434 - Per-Atom-Cluster Voltage Mode
+  Array used to specifies the selected Atom Core ClusterVoltage Mode.
+**/
+  UINT8                       PerAtomClusterVoltageMode[8];
+
+/** Offset 0x043C - Per-Atom-Cluster Voltage Override
+  Array used to specifies the selected Atom Core Cluster Voltage Override.
+**/
+  UINT16                      PerAtomClusterVoltageOverride[8];
+
+/** Offset 0x044C - Per-Atom-Cluster Adaptive Voltage
+  Array used to specifies the selected Atom Core Cluster Adaptive Voltage.
+**/
+  UINT16                      PerAtomClusterAdaptiveVoltage[8];
+
+/** Offset 0x045C - Number of active small cores
+  Number of E-cores to enable in each processor package. Note: Number of P-Cores and
+  E-Cores are looked at together. When both are {0,0
+  0:Disable all small cores, 1:1, 2:2, 3:3, 0xFF:Active all small cores
+**/
+  UINT8                       ActiveSmallCoreCount;
 
 /** Offset 0x045D - Core VF Point Offset Mode
   Selects Core Voltage & Frequency Offset mode between Legacy and Selection modes.
@@ -1356,9 +2102,24 @@ typedef struct {
 **/
   UINT8                       CoreVfPointCount;
 
-/** Offset 0x049B - Reserved
+/** Offset 0x049B - Core VF Configuration Scope
+  Alows both all-core VF curve or per-core VF curve configuration; <b>0: All-core</b>;
+  1: Per-core.
+  0:All-core, 1:Per-core
 **/
-  UINT8                       Reserved26[25];
+  UINT8                       CoreVfConfigScope;
+
+/** Offset 0x049C - Per-core VF Offset
+  Array used to specifies the selected Core Offset Voltage. This voltage is specified
+  in millivolts.
+**/
+  UINT16                      PerCoreVoltageOffset[8];
+
+/** Offset 0x04AC - Per-core VF Offset Prefix
+  Sets the PerCoreVoltageOffset value as positive or negative for the selected Core;
+  <b>0: Positive </b>; 1: Negative.
+**/
+  UINT8                       PerCoreVoltageOffsetPrefix[8];
 
 /** Offset 0x04B4 - Per Core Max Ratio override
   Enable or disable Per Core PState OC supported by writing OCMB 0x1D to program new
@@ -1367,18 +2128,113 @@ typedef struct {
 **/
   UINT8                       PerCoreRatioOverride;
 
-/** Offset 0x04B5 - Reserved
+/** Offset 0x04B5 - Per-core Voltage Mode
+  Array used to specifies the selected Core Voltage Mode.
 **/
-  UINT8                       Reserved27[41];
+  UINT8                       PerCoreVoltageMode[8];
+
+/** Offset 0x04BD
+**/
+  UINT8                       Rsvd110[1];
+
+/** Offset 0x04BE - Per-core Voltage Override
+  Array used to specifies the selected Core Voltage Override.
+**/
+  UINT16                      PerCoreVoltageOverride[8];
+
+/** Offset 0x04CE - Per-core Adaptive Voltage
+  Array used to specifies the selected Core Adaptive Voltage.
+**/
+  UINT16                      PerCoreAdaptiveVoltage[8];
 
 /** Offset 0x04DE - Per Core Current Max Ratio
   Array for the Per Core Max Ratio
 **/
   UINT8                       PerCoreRatio[8];
 
-/** Offset 0x04E6 - Reserved
+/** Offset 0x04E6 - OC TVB
+  Enable/Disable for OC TVB parameter programming using OCMB 0x24/0x25. <b>0:Disable
+  </b>; 1:Enable.
+  $EN_DIS
 **/
-  UINT8                       Reserved28[54];
+  UINT8                       OcTvb;
+
+/** Offset 0x04E7 - Pcore TVB Temperature Threshold 0
+  Pcore TVB Temp (in degrees C) - Temperature Threshold 0. Running ABOVE this temperature
+  will clip delta Down Bins for Threshold 0 from the resolved OC Ratio, when TVB
+  ratio clipping is enabled. Default is 70.
+**/
+  UINT8                       PcoreTvbTempThreshold0;
+
+/** Offset 0x04E8 - Pcore TVB Temperature Threshold 1
+  Pcore TVB Temp (in degrees C) - Temperature Threshold 1. Running ABOVE this temperature
+  will clip delta Down Bins for Threshold 1 from the resolved OC Ratio, when TVB
+  ratio clipping is enabled. Default is 100.
+**/
+  UINT8                       PcoreTvbTempThreshold1;
+
+/** Offset 0x04E9 - Ecore TVB Temperature Threshold 0
+  Ecore TVB Temp (in degrees C) - Temperature Threshold 0. Running ABOVE this temperature
+  will clip delta Down Bins for Threshold 0 from the resolved OC Ratio, when TVB
+  ratio clipping is enabled. Default is 70.
+**/
+  UINT8                       EcoreTvbTempThreshold0;
+
+/** Offset 0x04EA - Ecore TVB Temperature Threshold 1
+  Ecore TVB Temp (in degrees C) - Temperature Threshold 1. Running ABOVE this temperature
+  will clip delta Down Bins for Threshold 1 from the resolved OC Ratio, when TVB
+  ratio clipping is enabled. Default is 100.
+**/
+  UINT8                       EcoreTvbTempThreshold1;
+
+/** Offset 0x04EB - OC TVB Configuration Limit Selection
+  Select one of the two OC TVB Configuration limits, between Per CCP Module or Per
+  P-core Group. <b>0: Per CCP Module</b>; 1: Per P-core Group.
+  0:Per CCP Module, 1:Per P-core Group
+**/
+  UINT8                       TvbConfigLimitSelect;
+
+/** Offset 0x04EC - Per Pcore Ratio Down Bin Above T0
+  Array for the Per Pcore Down Bins (delta) for Temperature Threshold 0. When running
+  above Temperature Threshold 0, the ratio will be clipped by MAX_RATIO[n]-This value,
+  when TVB ratio clipping is enabled. Default is 1.
+**/
+  UINT8                       PerPcoreRatioDownBinAboveT0[8];
+
+/** Offset 0x04F4 - Per Pcore Ratio Down Bin Above T1
+  Array for the Per Pcore Down Bins (delta) for Temperature Threshold 1. When running
+  above Temperature Threshold 1, the ratio will be clipped by MAX_RATIO[n]-This value,
+  when TVB ratio clipping is enabled. Default is 2.
+**/
+  UINT8                       PerPcoreRatioDownBinAboveT1[8];
+
+/** Offset 0x04FC - Per Pcore Group Ratio Down Bin Above T0
+  Array for the Per Pcore Group Down Bins (delta) for Temperature Threshold 0. When
+  running above Temperature Threshold 0, the ratio will be clipped by MAX_RATIO[n]-This
+  value, when TVB ratio clipping is enabled. Default is 1.
+**/
+  UINT8                       PerPcoreGrRatioDownBinAboveT0[8];
+
+/** Offset 0x0504 - Per Pcore Group Ratio Down Bin Above T1
+  Array for the Per Pcore Group Down Bins (delta) for Temperature Threshold 1. When
+  running above Temperature Threshold 1, the ratio will be clipped by MAX_RATIO[n]-This
+  value, when TVB ratio clipping is enabled. Default is 2.
+**/
+  UINT8                       PerPcoreGrRatioDownBinAboveT1[8];
+
+/** Offset 0x050C - Per Ecore CCP Ratio Down Bin Above T0
+  Array for the Per Ecore CCP Down Bins (delta) for Temperature Threshold 0. When
+  running above Temperature Threshold 0, the ratio will be clipped by MAX_RATIO[n]-This
+  value, when TVB ratio clipping is enabled. Default is 0.
+**/
+  UINT8                       PerEcoreCcpRatioDownBinAboveT0[8];
+
+/** Offset 0x0514 - Per Ecore CCP Ratio Down Bin Above T1
+  Array for the Per Ecore Group Down Bins (delta) for Temperature Threshold 1. When
+  running above Temperature Threshold 1, the ratio will be clipped by MAX_RATIO[n]-This
+  value, when TVB ratio clipping is enabled. Default is 0.
+**/
+  UINT8                       PerEcoreCcpRatioDownBinAboveT1[8];
 
 /** Offset 0x051C - Margin Limit Check
   Margin Limit Check. Choose level of margin check
@@ -1386,9 +2242,27 @@ typedef struct {
 **/
   UINT8                       MarginLimitCheck;
 
-/** Offset 0x051D - Reserved
+/** Offset 0x051D
 **/
-  UINT8                       Reserved29[14];
+  UINT8                       Rsvd120[3];
+
+/** Offset 0x0520 - Margin Limit L2
+  % of L1 check for margin limit check
+**/
+  UINT16                      MarginLimitL2;
+
+/** Offset 0x0522 - Atom Cluster Max Ratio
+  Array for Atom Cluster Max Ratio, 4 ATOM cores are in the same Cluster and their
+  max core ratio will be aligned.
+**/
+  UINT8                       AtomClusterRatio[8];
+
+/** Offset 0x052A - Core Ratio Extension Mode
+  Enable or disable Core Ratio above 85 Extension Mode by writing BIOS MB 0x37 to
+  enable FULL_RANGE_MULTIPLIER_UNLOCK_EN. <b>0: Disable</b>, 1: enable
+  $EN_DIS
+**/
+  UINT8                       CoreRatioExtensionMode;
 
 /** Offset 0x052B - Pvd Ratio Threshold for SOC/CPU die
   Array of Pvd Ratio Threshold for SOC/CPU die is the threshold value for input ratio
@@ -1399,9 +2273,69 @@ typedef struct {
 **/
   UINT8                       PvdRatioThreshold[2];
 
-/** Offset 0x052D - Reserved
+/** Offset 0x052D - Pvd Mode SOC/CPU die
+  Array of PVD Mode. Value from 0 to 3 for SOC/CPU. 0x0 = div-1 (VCO = Output clock),
+  0x1 = div-2 (VCO = 2x Output clock), 0x2 = div-4 (VCO = 4x Output clock), 0x3 =
+  div-8 (VCO = 8x Output clock).
 **/
-  UINT8                       Reserved30[68];
+  UINT8                       PvdMode[2];
+
+/** Offset 0x052F - FLL Overclock Mode
+  Select FLL Mode Value from 0 to 3. 0x0 = no overclocking, 0x1 = ratio overclocking
+  with nominal (0.5-1x) reference clock frequency, 0x2 = BCLK overclocking with elevated
+  (1-3x) reference clock frequency, 0x3 = BCLK overclocking with extreme elevated
+  (3-5x) reference clock frequency and ratio limited to 63.
+**/
+  UINT8                       FllOverclockMode;
+
+/** Offset 0x0530 - Number of Soc-North Atom cores
+  Number of SOC-North E-cores to enable in SOC North. 0: Disable all Soc-North Atom
+  cores; 1: 1; 2: 2; <b>0xFF: Active all Soc-North Atom cores</b>
+  0:Disable all Soc-North Atom cores, 1:1, 2:2, 0xFF:Active all cores
+**/
+  UINT8                       ActiveSocNorthAtomCoreCount;
+
+/** Offset 0x0531 - Ring VF Point Offset Mode
+  Selects Ring Voltage & Frequency Offset mode between Legacy and Selection modes.
+  In Legacy Mode, setting a global offset for the entire VF curve. In Selection Mode,
+  setting a selected VF point; <b>0: Legacy</b>; 1: Selection.
+  0:Legacy, 1:Selection
+**/
+  UINT8                       RingVfPointOffsetMode;
+
+/** Offset 0x0532 - Ring VF Point Offset
+  Array used to specifies the Ring Voltage Offset applied to the each selected VF
+  Point. This voltage is specified in millivolts.
+**/
+  UINT16                      RingVfPointOffset[15];
+
+/** Offset 0x0550 - Ring VF Point Offset Prefix
+  Sets the RingVfPointOffset value as positive or negative for corresponding core
+  VF Point; <b>0: Positive </b>; 1: Negative.
+**/
+  UINT8                       RingVfPointOffsetPrefix[15];
+
+/** Offset 0x055F - Ring VF Point Ratio
+  Array for the each selected Ring VF Point to display the ration.
+**/
+  UINT8                       RingVfPointRatio[15];
+
+/** Offset 0x056E - Ring VF Point Count
+  Number of supported Ring Voltage & Frequency Point Offset
+**/
+  UINT8                       RingVfPointCount;
+
+/** Offset 0x056F - Compute Die SSC enable
+  Enable/Dsiable Compute-Die SSC Configuration. 0(Default)=Disable, 1=Enable
+  $EN_DIS
+**/
+  UINT8                       ComputeDieSscEnable;
+
+/** Offset 0x0570 - Soc Die SSC enable
+  Enable/Dsiable Soc-Die SSC Configuration. 0(Default)=Disable, 1=Enable
+  $EN_DIS
+**/
+  UINT8                       SocDieSscEnable;
 
 /** Offset 0x0571 - GPIO Override
   Gpio Override Level - FSP will not configure any GPIOs and rely on GPIO setings
@@ -1410,9 +2344,9 @@ typedef struct {
 **/
   UINT8                       GpioOverride;
 
-/** Offset 0x0572 - Reserved
+/** Offset 0x0572
 **/
-  UINT8                       Reserved31[10];
+  UINT8                       Rsvd130[10];
 
 /** Offset 0x057C - CPU BCLK OC Frequency
   CPU BCLK OC Frequency in KHz units. 98000000Hz = 98MHz <b>0 - Auto</b>. Range is
@@ -1420,9 +2354,11 @@ typedef struct {
 **/
   UINT32                      CpuBclkOcFrequency;
 
-/** Offset 0x0580 - Reserved
+/** Offset 0x0580 - SOC BCLK OC Frequency
+  SOC BCLK OC Frequency in KHz units. 98000000Hz = 98MHz <b>0 - Auto</b>. Range is
+  40Mhz-1000Mhz.
 **/
-  UINT8                      Reserved32[4];
+  UINT32                      SocBclkOcFrequency;
 
 /** Offset 0x0584 - Enable CPU CrashLog GPRs dump
   Enable or Disable CPU CrashLog GPRs dump; <b>0: Disable</b>; 1: Enable; 2: Only
@@ -1431,9 +2367,163 @@ typedef struct {
 **/
   UINT8                       CrashLogGprs;
 
-/** Offset 0x0585 - Reserved
+/** Offset 0x0585
 **/
-  UINT8                       Reserved33[142];
+  UINT8                       Rsvd140[11];
+
+/** Offset 0x0590 - Bitmask of disable cores
+  Core mask is a bitwise indication of which core should be disabled. <b>0x00=Default</b>;
+  Bit 0 - core 0, bit 7 - core 7.
+**/
+  UINT64                      DisablePerCoreMask;
+
+/** Offset 0x0598 - Support IA Unlimited ICCMAX
+  Support IA Unlimited ICCMAX up to maximum value 512A; <b>0: Disabled</b>; 1: Enabled.
+  $EN_DIS
+**/
+  UINT8                       IaIccUnlimitedMode;
+
+/** Offset 0x0599
+**/
+  UINT8                       Rsvd150[1];
+
+/** Offset 0x059A - IA ICCMAX
+  IA ICCMAX value is represented in 1/4 A increments. A value of 400 = 100A. <b>0
+  (HW default)</b>. Range is 4-2047.
+**/
+  UINT16                      IaIccMax;
+
+/** Offset 0x059C - Support GT Unlimited ICCMAX
+  Support GT Unlimited ICCMAX up to maximum value 512A; <b>0: Disabled</b>; 1: Enabled.
+  $EN_DIS
+**/
+  UINT8                       GtIccUnlimitedMode;
+
+/** Offset 0x059D
+**/
+  UINT8                       Rsvd160[1];
+
+/** Offset 0x059E - GT ICCMAX
+  GT ICCMAX value is represented in 1/4 A increments. A value of 400 = 100A. <b>0
+  (HW default)</b>. Range is 4-2047.
+**/
+  UINT16                      GtIccMax;
+
+/** Offset 0x05A0 - Support SA Unlimited ICCMAX
+  Support SA Unlimited ICCMAX up to maximum value 512A; <b>0: Disabled</b>; 1: Enabled.
+  $EN_DIS
+**/
+  UINT8                       SaIccUnlimitedMode;
+
+/** Offset 0x05A1
+**/
+  UINT8                       Rsvd161[1];
+
+/** Offset 0x05A2 - SA ICCMAX
+  SA ICCMAX value is represented in 1/4 A increments. A value of 400 = 100A. <b>0
+  (HW default)</b>. Range is 4-2047.
+**/
+  UINT16                      SaIccMax;
+
+/** Offset 0x05A4 - Memory Subsystem VF Point Offset
+  Array used to specifies the Memory Subsystem Voltage Offset applied to the each
+  selected VF Point. This voltage is specified in millivolts.
+**/
+  UINT16                      MemSSVfPointOffset[15];
+
+/** Offset 0x05C2 - Memory Subsystem VF Point Offset Prefix
+  Sets the MemSSVfPointOffset value as positive or negative for corresponding core
+  VF Point; <b>0: Positive </b>; 1: Negative.
+**/
+  UINT8                       MemSSVfPointOffsetPrefix[15];
+
+/** Offset 0x05D1 - Memory Subsystem VF Point Ratio
+  Array for the each selected Memory Subsystem VF Point to display the ration.
+**/
+  UINT8                       MemSSVfPointRatio[15];
+
+/** Offset 0x05E0 - Memory Subsystem VF Point Count
+  Number of supported Memory Subsystem Voltage & Frequency Point Offset
+**/
+  UINT8                       MemSSVfPointCount;
+
+/** Offset 0x05E1 - VCCSA Boot Voltage
+  <b> Default: 0: Nominal </b> 1: High Voltage(up to 1.2/1.3V) to support the voltage
+  needed for VCCSA boot voltage.
+  0: Nominal , 1: High Voltage(up to 1.2/1.3V)
+**/
+  UINT8                       VccsaBootVoltageSel;
+
+/** Offset 0x05E2 - CPU D2D ratio setting
+  0(Default)=No setting, 15=Minimal, 40=Maximum
+**/
+  UINT8                       CpuD2dRatio;
+
+/** Offset 0x05E3 - CPU Bandgap Reference Mode
+  <b> Default: 0: Normal </b> 1: Bandgap Bypassed) to support CPU Bandgap Reference Mode.
+  0: Normal , 1: Bandgap Bypassed
+**/
+  UINT8                       CpuBandgapRefMode;
+
+/** Offset 0x05E4 - VCCIA Boot Voltage
+  <b> Default: 0: Nominal </b> 1: High Voltage to support the voltage higher than
+  1.65v (max 2.01v))
+  0: Nominal , 1: High Voltage
+**/
+  UINT8                       VcciaBootVoltageSel;
+
+/** Offset 0x05E5 - Granular Ratio Override
+  Enable or disable OC Granular Ratio Override. <b>0: Disable</b>, 1: enable
+  $EN_DIS
+**/
+  UINT8                       GranularRatioOverride;
+
+/** Offset 0x05E6 - Granularity Bins Override for Core
+  Array used to specifies the selected Core Granularity Bins.
+**/
+  UINT8                       PerCoreGranularityBins[8];
+
+/** Offset 0x05EE - Granularity Bins Override for AtomCluster
+  Array used to specifies the selected AtomCluster Granularity Bins.
+**/
+  UINT8                       PerAtomClusterGranularityBins[8];
+
+/** Offset 0x05F6 - Sa PLL Frequency
+  Configure Sa PLL Frequency. <b>0: 2400MHz </b>, 1: 1600MHz
+  0: 2400MHz, 1: 1600MHz
+**/
+  UINT8                       SaPllFreqOverride;
+
+/** Offset 0x05F7 - TSC HW Fixup disable
+  TSC HW Fixup disable during TSC copy from PMA to APIC. <b>0: Enable</b>; 1: Disable
+  0:Enable, 1:Disable
+**/
+  UINT8                       TscDisableHwFixup;
+
+/** Offset 0x05F8 - Process Vmax Limit
+  Setting this bit will allow user to set any voltage. Note: Disabling the voltage
+  limit checks may cause permanent damage to processor. <b>1: Enable</b>; 0: Disable
+  1:Enable, 0:Disable
+**/
+  UINT8                       ProcessVmaxLimit;
+
+/** Offset 0x05F9 - P-Core Power Density Throttle
+  This control allow user to disable P-core Power Density Throttling for overclocking.
+  <b>1: Enable</b>; 0: Disable
+  1:Enable, 0:Disable
+**/
+  UINT8                       PcorePowerDensityThrottle;
+
+/** Offset 0x05FA - Request Core Min Ratio
+  0(Default)=No Request
+**/
+  UINT8                       CoreMinRatio;
+
+/** Offset 0x05FB - ReservedCpuPreMem
+  Reserved for Cpu Pre-Mem
+  $EN_DIS
+**/
+  UINT8                       ReservedCpuPreMem[24];
 
 /** Offset 0x0613 - Acoustic Noise Mitigation feature
   Enabling this option will help mitigate acoustic noise on certain SKUs when the
@@ -1442,9 +2532,15 @@ typedef struct {
 **/
   UINT8                       AcousticNoiseMitigation;
 
-/** Offset 0x0614 - Reserved
+/** Offset 0x0614 - Platform Psys slope correction
+  PSYS Slope defined in 1/100 increments. <b>0 - Auto</b> Specified in 1/100 increment
+  values. Range is 0-200. 125 = 1.25
 **/
-  UINT8                       Reserved34[2];
+  UINT8                       PsysSlope;
+
+/** Offset 0x0615
+**/
+  UINT8                       Rsvd170[1];
 
 /** Offset 0x0616 - Platform Power Pmax
   PSYS PMax power, defined in 1/8 Watt increments. <b>0 - Auto</b> Specified in 1/8
@@ -1452,9 +2548,12 @@ typedef struct {
 **/
   UINT16                      PsysPmax;
 
-/** Offset 0x0618 - Reserved
+/** Offset 0x0618 - Thermal Design Current current limit
+  TDC Current Limit, defined in 1/8A increments. Range 0-32767. For a TDC Current
+  Limit of 125A, enter 1000. 0 = 0 Amps. <b>0: Auto</b>. [0] for IA, [1] for GT,
+  [2] for SA, [3] through [5] are Reserved.
 **/
-  UINT8                      Reserved35[12];
+  UINT16                      TdcCurrentLimit[6];
 
 /** Offset 0x0624 - AcLoadline
   AC Loadline defined in 1/100 mOhms. A value of 100 = 1.00 mOhm, and 1255 = 12.55
@@ -1491,9 +2590,36 @@ typedef struct {
 **/
   UINT16                      Psi3Threshold[6];
 
-/** Offset 0x0660 - Reserved
+/** Offset 0x0660 - Power State 3 enable/disable
+  PS3 Enable/Disable. 0 - Disabled, 1 - Enabled. [0] for IA, [1] for GT, [2] for SA,
+  [3] through [5] are Reserved.
 **/
-  UINT8                       Reserved36[54];
+  UINT8                       Psi3Enable[6];
+
+/** Offset 0x0666 - Power State 4 enable/disable
+  PS4 Enable/Disable. 0 - Disabled, 1 - Enabled. [0] for IA, [1] for GT, [2] for SA,
+  [3] through [5] are Reserved.
+**/
+  UINT8                       Psi4Enable[6];
+
+/** Offset 0x066C - Imon slope correction
+  IMON Slope defined in 1/100 increments. Range is 0-200. For a 1.25 slope, enter
+  125. <b>0: Auto</b>. [0] for IA, [1] for GT, [2] for SA, [3] through [5] are Reserved.
+**/
+  UINT16                      ImonSlope[6];
+
+/** Offset 0x0678 - Imon offset correction
+  IMON Offset is an 32-bit signed value (2's complement). Units 1/1000, Range is [-128000,
+  127999]. For an offset of 25.348, enter 25348. <b>0: Auto</b>. [0] for IA, [1]
+  for GT, [2] for SA, [3] through [5] are Reserved.
+**/
+  UINT32                      ImonOffset[6];
+
+/** Offset 0x0690 - Enable/Disable BIOS configuration of VR
+  VR Config Enable. [0] for IA, [1] for GT, [2] for SA, [3] through [5] are Reserved.
+  <b>0: Disable</b>; 1: Enable.
+**/
+  UINT8                       VrConfigEnable[6];
 
 /** Offset 0x0696 - Thermal Design Current enable/disable
   Thermal Design Current enable/disable; <b>0: Disable</b>; 1: Enable. [0] for IA,
@@ -1507,9 +2633,130 @@ typedef struct {
 **/
   UINT32                      TdcTimeWindow[6];
 
-/** Offset 0x06B4 - Reserved
+/** Offset 0x06B4 - Thermal Design Current Lock
+  Thermal Design Current Lock; <b>0: Disable</b>; 1: Enable. For all VR Indexes
 **/
-  UINT8                       Reserved37[128];
+  UINT8                       TdcLock[6];
+
+/** Offset 0x06BA - DLVR RFI Frequency
+  DLVR RFI Frequency in MHz. <b>0x055A: 1370 MHz</b>.
+**/
+  UINT16                      DlvrRfiFrequency;
+
+/** Offset 0x06BC - DLVR RFI Spread Spectrum Percentage
+  DLVR SSC in percentage with multiple of 0.25%. 0 = 0%, 31 = 7.75%. <b>0x06: 1.5%</b>;
+  u3.2 value from 0% - 7.75%.
+**/
+  UINT8                       DlvrSpreadSpectrumPercentage;
+
+/** Offset 0x06BD - DLVR RFI Enable
+  Enable/Disable DLVR RFI frequency hopping. 0: Disable; <b>1: Enable</b>.
+  $EN_DIS
+**/
+  UINT8                       DlvrRfiEnable;
+
+/** Offset 0x06BE - Pre Wake Randomization time
+  Set the maximum Pre Wake randomization time in micro ticks. This is for acoustic
+  noise mitigation Dynamic Perodicity Alteration (DPA) tuning. Range 0-255 <b>0</b>.
+**/
+  UINT8                       PreWake;
+
+/** Offset 0x06BF - Ramp Up Randomization time
+  Set the maximum Ramp Up randomization time in micro ticks. This is for acoustic
+  noise mitigation Dynamic Perodicity Alteration (DPA) tuning. Range 0-255 <b>0</b>.
+**/
+  UINT8                       RampUp;
+
+/** Offset 0x06C0 - Ramp Down Randomization time
+  Set the maximum Ramp Down randomization time in micro ticks. This is for acoustic
+  noise mitigation Dynamic Perodicity Alteration (DPA) tuning. Range 0-255 <b>0</b>.
+**/
+  UINT8                       RampDown;
+
+/** Offset 0x06C1 - Available power delivery segments
+  This field is required to be non-zero on Desktop platforms. Used to communicate
+  the power delivery design capability of the board. This value is an enum of the
+  available power delivery segments that are defined in the Platform Design Guide.
+  <b>0: Disable.</b>.
+**/
+  UINT8                       VrPowerDeliveryDesign;
+
+/** Offset 0x06C2 - VR Voltage Limit
+  Voltage Limit (VMAX). This value represents the Maximum instantaneous voltage allowed
+  at any given time. Range is 0 - 7999mV. [0] for IA, [1] for GT, [2] for SA, [3]
+  through [5] are Reserved.
+**/
+  UINT16                      VrVoltageLimit[6];
+
+/** Offset 0x06CE - Enable/Disable PS1 to PS0 Dynamic Cutoff
+  PS1 to PS0 Dynamic Cutoff Enable/Disable. <b>0: Disable</b>; 1: Enable. [0] for
+  IA, [1] for GT, [2] for SA, [3] through [5] are Reserved.
+**/
+  UINT8                       PS1toPS0DynamicCutoffEnable[6];
+
+/** Offset 0x06D4 - PS1 to PS0 Dynamic Cutoff M Coef
+  PS1 to PS0 Dynamic Cutoff M Coef, This number is in M*100 units. For 12.50, enter
+  1250. Range: 0-4096. [0] for IA, [1] for GT, [2] for SA, [3] through [5] are Reserved.
+**/
+  UINT16                      PS1toPS0MCoef[6];
+
+/** Offset 0x06E0 - PS1 to PS0 Dynamic Cutoff C Coef
+  PS1 to PS0 Dynamic Cutoff C Coef, This number is in C*100 units. For 12.50, enter
+  1250. If your value bigger than 2047, it will minus 4096. For -12.50, enter 2846,
+  range:0-4096. [0] for IA, [1] for GT, [2] for SA, [3] through [5] are Reserved.
+**/
+  UINT16                      PS1toPS0CCoef[6];
+
+/** Offset 0x06EC - Enable/Disable PS2 to PS1 Dynamic Cutoff
+  PS2 to PS1 Dynamic Cutoff Enable/Disable. <b>0: Disable</b>; 1: Enable. [0] for
+  IA, [1] for GT, [2] for SA, [3] through [5] are Reserved.
+**/
+  UINT8                       PS2toPS1DynamicCutoffEnable[6];
+
+/** Offset 0x06F2 - PS2 to PS1 Dynamic Cutoff M Coef
+  PS2 to PS1 Dynamic Cutoff M Coef, This number is in M*100 units. For 12.50, enter
+  1250, range:0-4096. [0] for IA, [1] for GT, [2] for SA, [3] through [5] are Reserved.
+**/
+  UINT16                      PS2toPS1MCoef[6];
+
+/** Offset 0x06FE - PS2 to PS1 Dynamic Cutoff C Coef
+  PS2 to PS1 Dynamic Cutoff C Coef, This number is in C*100 units. For 12.50, enter
+  1250. If your value bigger than 2047, it will minus 4096. For -12.50, enter 2846,
+  range:0-4096. [0] for IA, [1] for GT, [2] for SA, [3] through [5] are Reserved.
+**/
+  UINT16                      PS2toPS1CCoef[6];
+
+/** Offset 0x070A - VCCIN Demotion
+  DEPRECATED. En/Dis VCCIN Demotion. 0: Disable, <b>1: Enable with default threshold</b>,
+  2: Enable with user configured threshold. [0] for IA, [1] for GT, [2] for SA, [3]
+  through [5] are Reserved.
+**/
+  UINT8                       VccInDemotionEnable[6];
+
+/** Offset 0x0710 - VCCIN Demotion Quiescent Power in mW
+  DEPRECATED. User configured platform quiescent threshold in milli-watt when VCC
+  Demotion is enabled. Range is 0-255mW. [0] for IA, [1] for GT, [2] for SA, [3]
+  through [5] are Reserved.
+**/
+  UINT8                       VccInDemotionQuiescentPowerInMw[6];
+
+/** Offset 0x0716
+**/
+  UINT8                       Rsvd190[2];
+
+/** Offset 0x0718 - VCCIN Demotion Capacitance in uF
+  DEPRECATED. User configured VR's quiescent power threshold in micro-farad when VCC
+  Demotion is enabled. Range: 0-2000uF. [0] for IA, [1] for GT, [2] for SA, [3] through
+  [5] are Reserved.
+**/
+  UINT32                      VccInDemotionCapacitanceInUf[6];
+
+/** Offset 0x0730 - Platform Psys offset correction
+  PSYS Offset defined in 1/1000 increments. <b>0 - Auto</b> This is an 32-bit signed
+  value (2's complement). Units 1/1000, Range is [-128000, 127999]. For an offset
+  of 25.348, enter 25348.
+**/
+  UINT32                      PsysOffset;
 
 /** Offset 0x0734 - Disable Fast Slew Rate for Deep Package C States for VR domains
   This option needs to be configured to reduce acoustic noise during deeper C states.
@@ -1529,9 +2776,39 @@ typedef struct {
 **/
   UINT8                       SlowSlewRate[6];
 
-/** Offset 0x0740 - Reserved
+/** Offset 0x0740 - Icc Max limit
+  Voltage Regulator Current Limit (Icc Max). This value represents the Maximum instantaneous
+  current allowed at any given time. The value is represented in 1/4 A increments.
+  A value of 400 = 100A. 0 means AUTO. IA and GT, range 0-2047. SA range 0-1023.
+  [0] for IA, [1] for GT, [2] for SA, [3] through [5] are Reserved.
 **/
-  UINT8                      Reserved38[26];
+  UINT16                      IccMax[6];
+
+/** Offset 0x074C - VR Fast Vmode Offset
+  Voltage Regulator Fast Vmode Offset. This value represents the ICC Max Offset(dV/dT)
+  to be configured if Fast Vmode is enabled. The value is represented in 1 mV increments.
+  0 = Use processor default setting. Highly recommend to keep at the default setting.
+  IA, GT and SA, range 0-255. [0] for IA, [1] for GT, [2] for SA, [3] through [5]
+  are Reserved.
+**/
+  UINT8                       FastVmodeOffset[6];
+
+/** Offset 0x0752 - SVID Stabiliation Delay
+  Configure SVID Stabiliation Delay being used for the FVM feature when it is enabled.
+  Note that this delay applies to all SVID domains equally (no unique values possible
+  for IA/GT/SA).The value is represented in 1 us increments. IA, GT and SA, range 0-255.
+**/
+  UINT8                       SvidStabilizationDelay;
+
+/** Offset 0x0753 - VCC Demotion Shutdown Threshold in msec
+  User configured time threshold in msec. Range is 0-255 msec. [0] for IA, [1] for
+  GT, [2] for SA, [3] through [5] are Reserved.
+**/
+  UINT8                       VccDemotionShutdownThreshold[6];
+
+/** Offset 0x0759
+**/
+  UINT8                       Rsvd200[1];
 
 /** Offset 0x075A - VR Fast Vmode ICC Limit support
   Voltage Regulator Fast Vmode ICC Limit. A value of 400 = 100A. A value of 0 corresponds
@@ -1555,9 +2832,163 @@ typedef struct {
 **/
   UINT8                       CepEnable[6];
 
-/** Offset 0x0772 - Reserved
+/** Offset 0x0772 - Enable SIRP
+  Enable/Disable SIRP (SoC Iccmax Reactive Protection) Support. <b>0: Disable</b>;
+  1: Enable. [0] for IA, [1] for GT, [2] for SA, [3] through [5] are Reserved.
+  $EN_DIS
 **/
-  UINT8                       Reserved39[146];
+  UINT8                       SirpEnable[6];
+
+/** Offset 0x0778 - Enable IRMS
+  Enable/Disable IRMS for VR domains - Current root mean square. <b>0: Disable</b>;
+  1: Enable. [0] for IA, [1] for GT, [2] for SA, [3] through [5] are Reserved.
+**/
+  UINT8                       Irms[6];
+
+/** Offset 0x077E - UnderVolt Protection
+  When UnderVolt Protection is enabled, user will be not be able to program under
+  voltage in OS runtime. 0: Disabled; <b>1: Enabled</b>
+  $EN_DIS
+**/
+  UINT8                       UnderVoltProtection;
+
+/** Offset 0x077F - Vsys Critical
+  PCODE MMIO Mailbox: Vsys Critical. <b>0: Disable</b>; 1: Enable Range is 0-255.
+**/
+  UINT8                       EnableVsysCritical;
+
+/** Offset 0x0780 - Vsys Full Scale
+  Vsys Full Scale, Range is 0-255000mV
+**/
+  UINT32                      VsysFullScale;
+
+/** Offset 0x0784 - Vsys Critical Threshold
+  Vsys Critical Threshold, Range is 0-255000mV
+**/
+  UINT32                      VsysCriticalThreshold;
+
+/** Offset 0x0788 - Psys Full Scale
+  Vsys Full Scale, Range is 0-255000mV
+**/
+  UINT32                      PsysFullScale;
+
+/** Offset 0x078C - Psys Critical Threshold
+  Vsys Critical Threshold, Range is 0-255000mV
+**/
+  UINT32                      PsysCriticalThreshold;
+
+/** Offset 0x0790 - Assertion Deglitch Mantissa
+  Assertion Deglitch Mantissa, Range is 0-255
+**/
+  UINT8                       VsysAssertionDeglitchMantissa;
+
+/** Offset 0x0791 - Assertion Deglitch Exponent
+  Assertion Deglitch Exponent, Range is 0-255
+**/
+  UINT8                       VsysAssertionDeglitchExponent;
+
+/** Offset 0x0792 - De assertion Deglitch Mantissa
+  De assertion Deglitch Mantissa, Range is 0-255
+**/
+  UINT8                       VsysDeassertionDeglitchMantissa;
+
+/** Offset 0x0793 - De assertion Deglitch Exponent
+  De assertion Deglitch Exponent, Range is 0-255
+**/
+  UINT8                       VsysDeassertionDeglitchExponent;
+
+/** Offset 0x0794 - Per Core Max OC Ratio
+  Array for the Per Core Max OC Ratio
+**/
+  UINT8                       PerCoreMaxRatio[8];
+
+/** Offset 0x079C - Per Atom Cluster Max OC Ratio
+  Array for the Per Atom Cluster Max OC Ratio
+**/
+  UINT8                       PerAtomClusterMaxRatio[8];
+
+/** Offset 0x07A4 - OC Max Voltage limits
+  OC Max Voltage limits
+**/
+  UINT16                      MaxVoltageLimit[8];
+
+/** Offset 0x07B4 - Core PLL Current Reference Tuning Offset
+  Core PLL Current Reference Tuning Offset. <b>0: No offset</b>. Range 0-15
+**/
+  UINT8                       CorePllCurrentRefTuningOffset;
+
+/** Offset 0x07B5 - Ring PLL Current Reference Tuning Offset
+  DEPRECATED. Ring PLL Current Reference Tuning Offset. <b>0: No offset</b>. Range 0-15
+**/
+  UINT8                       RingPllCurrentRefTuningOffset;
+
+/** Offset 0x07B6 - IaAtom PLL Current Reference Tuning Offset
+  IaAtom PLL Current Reference Tuning Offset. <b>0: No offset</b>. Range 0-15
+**/
+  UINT8                       IaAtomPllCurrentRefTuningOffset;
+
+/** Offset 0x07B7 - Per Core Disable Configuration
+  This configuration can be used only when OC is enabled,user can either use legacy
+  num of cores option or the OC specific per core disable configuration. <b>0: Disable</b>, 1: Enable
+**/
+  UINT8                       PerCoreDisableConfiguration;
+
+/** Offset 0x07B8 - Maximum Npu turbo ratio override
+  DEPRECATED. Maximum Npu turbo ratio override allows to increase NPU frequency beyond
+  the fused max turbo ratio limit. <b>0: Hardware defaults.</b>  Range: 0-120
+**/
+  UINT8                       NpuMaxOcRatio;
+
+/** Offset 0x07B9 - NPU voltage mode
+  DEPRECATED. NPU voltage mode; <b>0: Adaptive</b>; 1: Override.
+  $EN_DIS
+**/
+  UINT8                       NpuVoltageMode;
+
+/** Offset 0x07BA - NPU voltage override
+  DEPRECATED. The NPU voltage override which is applied to the entire range of cpu
+  NPU frequencies. Valid Range 0 to 2000
+**/
+  UINT16                      NpuVoltageOverride;
+
+/** Offset 0x07BC - adaptive voltage applied during turbo frequencies
+  DEPRECATED. 0(Default)=Minimal, 2000=Maximum
+**/
+  UINT16                      NpuAdaptiveVoltage;
+
+/** Offset 0x07BE - NPU Turbo voltage Offset
+  DEPRECATED. The voltage offset applied to the NPU while operating in turbo mode.
+  Valid Range 0 to 1000
+**/
+  UINT16                      NpuVoltageOffset;
+
+/** Offset 0x07C0 - OC Max Voltage limits
+  DEPRECATED. OC Max Voltage limits
+**/
+  UINT16                      MaxVoltageLimitNew[9];
+
+/** Offset 0x07D2 - Force Pcore Residency
+  Enable/Disable Force Pcore Residency. <b>0: Disable</b>; 1: Enable.
+  $EN_DIS
+**/
+  UINT8                       ForcePcoreResidency;
+
+/** Offset 0x07D3 - VR Limit Bypass
+  Enable/Disable VR Limit Bypass. <b>0: Disable</b>; 1: Enable.
+  $EN_DIS
+**/
+  UINT8                       VrLimitBypass;
+
+/** Offset 0x07D4 - Turbo Thermal Protection
+  This control allow user to disable Turbo Thermal Protection (TTP) for overclocking.
+  <b>1: Enable</b>; 0: Disable
+  1:Enable, 0:Disable
+**/
+  UINT8                       TurboThermalProtection;
+
+/** Offset 0x07D5
+**/
+  UINT8                       CpuFspmUpdRsvd[47];
 
 /** Offset 0x0804 - BiosGuard
   Enable/Disable. 0: Disable, Enable/Disable BIOS Guard feature, 1: enable
@@ -1577,9 +3008,9 @@ typedef struct {
 **/
   UINT8                       Txt;
 
-/** Offset 0x0807 - Reserved
+/** Offset 0x0807
 **/
-  UINT8                       Reserved40;
+  UINT8                       Rsvd210[1];
 
 /** Offset 0x0808 - PrmrrSize
   Enable/Disable. 0: Disable, define default value of PrmrrSize , 1: enable
@@ -1591,9 +3022,9 @@ typedef struct {
 **/
   UINT32                      SinitMemorySize;
 
-/** Offset 0x0810 - Reserved
+/** Offset 0x0810
 **/
-  UINT8                       Reserved41[8];
+  UINT8                       Rsvd220[8];
 
 /** Offset 0x0818 - TxtDprMemoryBase
   Enable/Disable. 0: Disable, define default value of TxtDprMemoryBase , 1: enable
@@ -1646,9 +3077,11 @@ typedef struct {
 **/
   UINT8                       IsTPMPresence;
 
-/** Offset 0x0849 - Reserved
+/** Offset 0x0849 - ReservedSecurityPreMem
+  Reserved for Security Pre-Mem
+  $EN_DIS
 **/
-  UINT8                       Reserved42[32];
+  UINT8                       ReservedSecurityPreMem[32];
 
 /** Offset 0x0869 - Enable PCH HSIO PCIE Rx Set Ctle
   Enable PCH PCIe Gen 3 Set CTLE Value.
@@ -1833,9 +3266,9 @@ typedef struct {
 **/
   UINT8                       PchNumRsvdSmbusAddresses;
 
-/** Offset 0x0A85 - Reserved
+/** Offset 0x0A85
 **/
-  UINT8                       Reserved43;
+  UINT8                       Rsvd230[1];
 
 /** Offset 0x0A86 - SMBUS Base Address
   SMBUS Base Address (IO space).
@@ -1853,18 +3286,39 @@ typedef struct {
 **/
   UINT8                       PcieClkSrcUsage[16];
 
-/** Offset 0x0A99 - Reserved
+/** Offset 0x0A99 - Usage type for PCH ClkSrc
+  0-23: PCIe rootport, 0x70:LAN, 0x80: unspecified but in use (free running), 0xFF: not used
 **/
-  UINT8                       Reserved44[16];
+  UINT8                       PchPcieClkSrcUsage[16];
 
 /** Offset 0x0AA9 - SOC/IOE ClkReq-to-ClkSrc mapping
   Number of ClkReq signal assigned to ClkSrc
 **/
   UINT8                       PcieClkSrcClkReq[16];
 
-/** Offset 0x0AB9 - Reserved
+/** Offset 0x0AB9 - PCH ClkReq-to-ClkSrc mapping
+  Number of ClkReq signal assigned to ClkSrc
 **/
-  UINT8                       Reserved45[55];
+  UINT8                       PchPcieClkSrcClkReq[16];
+
+/** Offset 0x0AC9
+**/
+  UINT8                       Rsvd240[1];
+
+/** Offset 0x0ACA - PCH additional MMIO reserved
+  Additional MMIO reserved for PCH usage (i.e dTBT) in MB
+**/
+  UINT16                      PchAdditionalMmioRsvd;
+
+/** Offset 0x0ACC - Clk Req GPIO Pin
+  Select Clk Req Pin. Refer to GPIO_*_MUXING_SRC_CLKREQ_x* for possible values.
+**/
+  UINT32                      PcieClkReqGpioMux[8];
+
+/** Offset 0x0AEC - Point of RsvdSmbusAddressTable
+  Array of addresses reserved for non-ARP-capable SMBus devices.
+**/
+  UINT32                      RsvdSmbusAddressTablePtr;
 
 /** Offset 0x0AF0 - Enable PCH PCIE RP Mask
   Enable/disable PCH PCIE Root Ports. 0: disable, 1: enable. One bit for each port,
@@ -1914,9 +3368,15 @@ typedef struct {
 **/
   UINT8                       PchHdaAudioLinkDmicEnable[2];
 
-/** Offset 0x0AFE - Reserved
+/** Offset 0x0AFE - Discrete BT Offload Enabled
+  Enable/disable Discrete BT Offload.
 **/
-  UINT8                       Reserved46[2];
+  UINT8                       HdaDiscBtOffEnabled;
+
+/** Offset 0x0AFF - PCH additional IO reserved
+  Additional IO reserved for PCH usage in KB
+**/
+  UINT8                       PchAdditionalIoRsvd;
 
 /** Offset 0x0B00 - DMIC<N> ClkA Pin Muxing (N - DMIC number)
   Determines DMIC<N> ClkA Pin muxing. See  GPIO_*_MUXING_DMIC<N>_CLKA_*
@@ -1934,9 +3394,16 @@ typedef struct {
 **/
   UINT8                       PchHdaDspEnable;
 
-/** Offset 0x0B11 - Reserved
+/** Offset 0x0B11 - Discrete BT Offload Ssp Link
+  Select SSP link instance for Discrete BT Offload. Note that this SSP instance must
+  also be enabled.
 **/
-  UINT8                       Reserved47[3];
+  UINT8                       HdaDiscBtOffSspLink;
+
+/** Offset 0x0B12 - SoC additional MMIO reserved
+  Additional MMIO reserved for SoC usage (i.e TBT) in MB
+**/
+  UINT16                      SocAdditionalMmioRsvd;
 
 /** Offset 0x0B14 - DMIC<N> Data Pin Muxing
   Determines DMIC<N> Data Pin muxing. See GPIO_*_MUXING_DMIC<N>_DATA_*
@@ -1959,9 +3426,12 @@ typedef struct {
 **/
   UINT8                       PchHdaIDispLinkFrequency;
 
-/** Offset 0x0B27 - Reserved
+/** Offset 0x0B27 - Sndw0 Multiline enablement
+  SoundWire Link 0 Multiline enablement. Default is DISABLE. 0: DISABLE, 1: Two lines
+  enabled, 2: Three lines enabled, 3: Four Lines enabled.
+  $EN_DIS
 **/
-  UINT8                       Reserved48;
+  UINT8                       PchHdAudioSndwMultilaneEnable;
 
 /** Offset 0x0B28 - iDisp-Link T-mode
   iDisp-Link T-Mode (PCH_HDAUDIO_IDISP_TMODE enum): 0: 2T, 2: 4T, 3: 8T, 4: 16T
@@ -1975,9 +3445,14 @@ typedef struct {
 **/
   UINT8                       PchHdaIDispCodecDisconnect;
 
-/** Offset 0x0B2A - Reserved
+/** Offset 0x0B2A
 **/
-  UINT8                       Reserved49[2];
+  UINT8                       Rsvd260[1];
+
+/** Offset 0x0B2B - SoC additional IO reserved
+  Additional IO reserved for SoC usage in KB
+**/
+  UINT8                       SocAdditionalIoRsvd;
 
 /** Offset 0x0B2C - Audio Sub System IDs
   Set default Audio Sub System IDs. If its set to 0 then value from Strap is used.
@@ -1990,9 +3465,32 @@ typedef struct {
 **/
   UINT8                       CnviDdrRfim;
 
-/** Offset 0x0B31 - Reserved
+/** Offset 0x0B31 - Extended BIOS Support
+  Enable/Disable Extended BIOS Region Support. Default is DISABLE. 0: DISABLE, 1: ENABLE
+  $EN_DIS
 **/
-  UINT8                       Reserved50[11];
+  UINT8                       ExtendedBiosDecodeRange;
+
+/** Offset 0x0B32 - Extented BIOS Direct Read Decode enable
+  Enable/Disable access to bigger than 16MB BIOS Region through Direct Memory Reads.
+  0: disabled (default), 1: enabled
+  $EN_DIS
+**/
+  UINT8                       PchSpiExtendedBiosDecodeRangeEnable;
+
+/** Offset 0x0B33
+**/
+  UINT8                       Rsvd270[1];
+
+/** Offset 0x0B34 - Extended BIOS Direct Read Decode Range base
+  Bits of 31:16 of a memory address that'll be a base for Extended BIOS Direct Read Decode.
+**/
+  UINT32                      PchSpiExtendedBiosDecodeRangeBase;
+
+/** Offset 0x0B38 - Extended BIOS Direct Read Decode Range limit
+  Bits of 31:16 of a memory address that'll be a limit for Extended BIOS Direct Read Decode.
+**/
+  UINT32                      PchSpiExtendedBiosDecodeRangeLimit;
 
 /** Offset 0x0B3C - Debug Interfaces
   Debug Interfaces. BIT0-RAM, BIT1-UART, BIT3-USB3, BIT4-Serial IO, BIT5-TraceHub,
@@ -2012,9 +3510,9 @@ typedef struct {
 **/
   UINT8                       SerialIoUartDebugAutoFlow;
 
-/** Offset 0x0B3F - Reserved
+/** Offset 0x0B3F
 **/
-  UINT8                       Reserved51;
+  UINT8                       Rsvd280[1];
 
 /** Offset 0x0B40 - Serial Io Uart Debug BaudRate
   Set default BaudRate Supported from 0 - default to 6000000. Recommended values 9600,
@@ -2040,9 +3538,11 @@ typedef struct {
 **/
   UINT8                       SerialIoUartDebugDataBits;
 
-/** Offset 0x0B47 - Reserved
+/** Offset 0x0B47 - SerialIo Uart PowerGating
+  Select SerialIo Uart Powergating mode
+  0:Disabled, 1:Enabled, 2:Auto
 **/
-  UINT8                       Reserved52;
+  UINT8                       SerialIoUartPowerGating;
 
 /** Offset 0x0B48 - Serial Io Uart Debug Mmio Base
   Select SerialIo Uart default MMIO resource in SEC/PEI phase when PcdSerialIoUartMode
@@ -2056,9 +3556,10 @@ typedef struct {
 **/
   UINT8                       PcdIsaSerialUartBase;
 
-/** Offset 0x0B4D - Reserved
+/** Offset 0x0B4D - CPU SA PLL voltage offset
+  Core PLL voltage offset. <b>0: No offset</b>. Range 0-15
 **/
-  UINT8                       Reserved53;
+  UINT8                       CpuSaPllVoltageOffset;
 
 /** Offset 0x0B4E - Ring PLL voltage offset
   Core PLL voltage offset. <b>0: No offset</b>. Range 0-15
@@ -2070,9 +3571,10 @@ typedef struct {
 **/
   UINT8                       SaPllVoltageOffset;
 
-/** Offset 0x0B50 - Reserved
+/** Offset 0x0B50 - IA Atom PLL voltage offset
+  IA Atom PLL voltage offset. <b>0: No offset</b>. Range 0-15
 **/
-  UINT8                       Reserved54;
+  UINT8                       IaAtomPllVoltageOffset;
 
 /** Offset 0x0B51 - Memory Controller PLL voltage offset
   Core PLL voltage offset. <b>0: No offset</b>. Range 0-15
@@ -2188,9 +3690,11 @@ typedef struct {
 **/
   UINT8                       ERDTC2D;
 
-/** Offset 0x0B64 - Reserved
+/** Offset 0x0B64 - Unmatched Write Time Centering 1D
+  Enable/Disable {Unmatched Write Time Centering 1D
+  $EN_DIS
 **/
-  UINT8                       Reserved55;
+  UINT8                       UNMATCHEDWRTC1D;
 
 /** Offset 0x0B65 - Write Timing Centering 1D
   Enables/Disable Write Timing Centering 1D
@@ -2216,9 +3720,33 @@ typedef struct {
 **/
   UINT8                       RDVC1D;
 
-/** Offset 0x0B69 - Reserved
+/** Offset 0x0B69 - DDR5 ODT Timing Config
+  Enable/Disable DDR5 ODT TIMING CONFIG
+  $EN_DIS
 **/
-  UINT8                       Reserved56[10];
+  UINT8                       DDR5ODTTIMING;
+
+/** Offset 0x0B6A - View Pin Calibration
+  Enables/Disable View Pin Calibration
+  $EN_DIS
+**/
+  UINT8                       VIEWPINCAL;
+
+/** Offset 0x0B6B - Read DQS ODT Training
+  Enables/Disable Read DQS ODT Training
+  $EN_DIS
+**/
+  UINT8                       RDDQSODTT;
+
+/** Offset 0x0B6C
+**/
+  UINT8                       Rsvd290[6];
+
+/** Offset 0x0B72 - Read DQ ODT Training
+  Enables/Disable Read DQ ODT Training
+  $EN_DIS
+**/
+  UINT8                       RDDQODTT;
 
 /** Offset 0x0B73 - Read Equalization Training
   Enables/Disable Read Equalization Training
@@ -2226,9 +3754,17 @@ typedef struct {
 **/
   UINT8                       RDEQT;
 
-/** Offset 0x0B74 - Reserved
+/** Offset 0x0B74 - Read CTLE Training
+  Enables/Disable Read CTLE Training
+  $EN_DIS
 **/
-  UINT8                       Reserved57[2];
+  UINT8                       RDCTLET;
+
+/** Offset 0x0B75 - Hard Post Package Repair
+  Enables/Disable Hard Post Package Repair
+  $EN_DIS
+**/
+  UINT8                       PPR;
 
 /** Offset 0x0B76 - Write Timing Centering 2D
   Enables/Disable Write Timing Centering 2D
@@ -2254,9 +3790,11 @@ typedef struct {
 **/
   UINT8                       RDVC2D;
 
-/** Offset 0x0B7A - Reserved
+/** Offset 0x0B7A - RxVref Per-Bit Training
+  Enable/Disable RxVref Per-Bit Training
+  $EN_DIS
 **/
-  UINT8                       Reserved58;
+  UINT8                       RXVREFPERBIT;
 
 /** Offset 0x0B7B - Command Voltage Centering
   Enables/Disable Command Voltage Centering
@@ -2282,9 +3820,11 @@ typedef struct {
 **/
   UINT8                       RMT;
 
-/** Offset 0x0B7F - Reserved
+/** Offset 0x0B7F - LVR Auto Trim
+  Enable/disable LVR Auto Trim
+  $EN_DIS
 **/
-  UINT8                       Reserved59;
+  UINT8                       LVRAUTOTRIM;
 
 /** Offset 0x0B80 - DIMM SPD Alias Test
   Enables/Disable DIMM SPD Alias Test
@@ -2334,9 +3874,17 @@ typedef struct {
 **/
   UINT8                       CMDSR;
 
-/** Offset 0x0B88 - Reserved
+/** Offset 0x0B88 - CMD Drive Strength
+  Enable/Disable CMD Drive Strength
+  $EN_DIS
 **/
-  UINT8                       Reserved60[2];
+  UINT8                       CMDDS;
+
+/** Offset 0x0B89 - CMD Tx Equalization
+  Enable/Disable CMD Tx Equalization
+  $EN_DIS
+**/
+  UINT8                       CMDTXEQ;
 
 /** Offset 0x0B8A - DIMM CA ODT Training
   Enable/Disable DIMM CA ODT Training
@@ -2344,9 +3892,23 @@ typedef struct {
 **/
   UINT8                       DIMMODTCA;
 
-/** Offset 0x0B8B - Reserved
+/** Offset 0x0B8B - Write DQ/DQS Retraining
+  Enable/Disable Write DQ/DQS Retraining
+  $EN_DIS
 **/
-  UINT8                       Reserved61[3];
+  UINT8                       WRTRETRAIN;
+
+/** Offset 0x0B8C - Power Saving Meter Update
+  Enable/Disable Power Saving Meter Update
+  $EN_DIS
+**/
+  UINT8                       PWRMETER;
+
+/** Offset 0x0B8D - Pre-Training Comp Calibration
+  Enable/Disable Pre-Training Comp Calibration
+  $EN_DIS
+**/
+  UINT8                       DDRPRECOMP;
 
 /** Offset 0x0B8E - Read Vref Decap Training
   Enable/Disable Read Vref Decap Training
@@ -2366,9 +3928,29 @@ typedef struct {
 **/
   UINT8                       RMTBIT;
 
-/** Offset 0x0B91 - Reserved
+/** Offset 0x0B91 - DQ/DQS Swizzle Training
+  Enable/Disable DQ/DQS Swizzle Training
+  $EN_DIS
 **/
-  UINT8                       Reserved62[4];
+  UINT8                       DQDQSSWZ;
+
+/** Offset 0x0B92 - Ref PI Calibration
+  Enable/Disable Ref PI Calibration
+  $EN_DIS
+**/
+  UINT8                       REFPI;
+
+/** Offset 0x0B93 - Rx SAL Calibration
+  Enable/Disable Rx SAL Calibration
+  0:Disable, 1:Enable
+**/
+  UINT8                       RXSALCAL;
+
+/** Offset 0x0B94 - VccClk FF Offset Correction
+  Enable/Disable VccClk FF Offset Correction
+  0:Disable, 1:Enable
+**/
+  UINT8                       VCCCLKFF;
 
 /** Offset 0x0B95 - Duty Cycle Correction Training
   Enable/Disable Duty Cycle Correction Training
@@ -2376,9 +3958,105 @@ typedef struct {
 **/
   UINT8                       DCC;
 
-/** Offset 0x0B96 - Reserved
+/** Offset 0x0B96 - Duty Cycle Correction Downstream Training
+  Enable/Disable Duty Cycle Correction Downstream - PI Serializer/LUT
+  $EN_DIS
 **/
-  UINT8                       Reserved63[17];
+  UINT8                       DCCDOWNSTREAM;
+
+/** Offset 0x0B97 - Duty Cycle Correction QCLK Calibration
+  Enable/Disable Duty Cycle Correction QCLK Calbration
+  $EN_DIS
+**/
+  UINT8                       DCCQCLK;
+
+/** Offset 0x0B98 - Duty Cycle Correction Rise/Fall Training
+  Enable/Disable Duty Cycle Correction Rise/Fall Training
+  $EN_DIS
+**/
+  UINT8                       DCCRISEFALL;
+
+/** Offset 0x0B99 - Functional Duty Cycle Correction for DDR5 DQS
+  Enable/Disable Functional Duty Cycle Correction for DDR5 DQS
+  0:Disable, 1:Enable
+**/
+  UINT8                       FUNCDCCDQS;
+
+/** Offset 0x0B9A - Functional Duty Cycle Correction for DDR5 CLK
+  Enable/Disable Functional Duty Cycle Correction for DDR5 CLK
+  0:Disable, 1:Enable
+**/
+  UINT8                       FUNCDCCCLK;
+
+/** Offset 0x0B9B
+**/
+  UINT8                       FUNCDCCWCK;
+
+/** Offset 0x0B9C - Functional Duty Cycle Correction for Data DQ
+  Enable/Disable Functional Duty Cycle Correction for Data DQ
+  0:Disable, 1:Enable
+**/
+  UINT8                       FUNCDCCDQ;
+
+/** Offset 0x0B9D - Data PI Linearity Calibration
+  Enable/Disable {ata PI Linearity Calibration
+  $EN_DIS
+**/
+  UINT8                       DATAPILIN;
+
+/** Offset 0x0B9E - Ddr5 Rx Cross-Talk Cancellation
+  Enable/Disable Ddr5 Rx Cross-Talk Cancellation
+  $EN_DIS
+**/
+  UINT8                       DDR5XTALK;
+
+/** Offset 0x0B9F - Duty Cycle Correction for LP5 DCA
+  Enable/Disable Duty Cycle Correction for LP5 DCA
+  $EN_DIS
+**/
+  UINT8                       DCCLP5WCKDCA;
+
+/** Offset 0x0BA0 - Unmatched Rx Calibration
+  Enable/Disable Rx Unmatched Calibration
+  $EN_DIS
+**/
+  UINT8                       RXUNMATCHEDCAL;
+
+/** Offset 0x0BA1 - Write Rank-to-Rank Training
+  Enable/Disable Write Rank-to-Rank Training
+  $EN_DIS
+**/
+  UINT8                       TXRK2RK;
+
+/** Offset 0x0BA2 - Read Rank-to-Rank Training
+  Enable/Disable Read Rank-to-Rank Training
+  $EN_DIS
+**/
+  UINT8                       RXRK2RK;
+
+/** Offset 0x0BA3 - Compensation Optimization
+  Enable/Disable Compensation Optimization
+  $EN_DIS
+**/
+  UINT8                       OPTIMIZECOMP;
+
+/** Offset 0x0BA4 - DIMM DFE Training
+  Enable/Disable DIMM DFE Training
+  $EN_DIS
+**/
+  UINT8                       WRTDIMMDFE;
+
+/** Offset 0x0BA5 - Write Drive Strength
+  Enables/Disable Write Drive Strength
+  $EN_DIS
+**/
+  UINT8                       WRTDS;
+
+/** Offset 0x0BA6 - Write Equalization
+  Enables/Disable Write Equalization
+  $EN_DIS
+**/
+  UINT8                       WRTEQ;
 
 /** Offset 0x0BA7 - ECC Support
   Enables/Disable ECC Support
@@ -2410,9 +4088,11 @@ typedef struct {
 **/
   UINT8                       IbeccProtectedRegionEnable[8];
 
-/** Offset 0x0BB3 - Reserved
+/** Offset 0x0BB3 - WckTCO Comp Training
+  Enable/Disable WckTCO Comp Training
+  $EN_DIS
 **/
-  UINT8                       Reserved64;
+  UINT8                       WCKTCO;
 
 /** Offset 0x0BB4 - IbeccProtectedRegionBases
   IBECC Protected Region Bases per IBECC instance
@@ -2502,9 +4182,29 @@ typedef struct {
 **/
   UINT8                       ExitOnFailure;
 
-/** Offset 0x0BF0 - Reserved
+/** Offset 0x0BF0 - DCC Single Rank Tracking
+  Force DCC to track single rank only
+  $EN_DIS
 **/
-  UINT8                       Reserved65[4];
+  UINT8                       DccSingleRankTrack;
+
+/** Offset 0x0BF1 - DDR5 supports MR7 WICA 0.5 tCK offset
+  DDR5 DRAM Device supports MR7 WICA 0.5 tCK offset, <b>0:False</b>, 1:True
+  0:False, 1:True
+**/
+  UINT8                       IsDdr5MR7WicaSupported;
+
+/** Offset 0x0BF2 - Write0 feature
+  Enables/Disable Write0 feature
+  $EN_DIS
+**/
+  UINT8                       Write0;
+
+/** Offset 0x0BF3 - Select if CLK0 is shared between Rank0 and Rank1 in DDR4 DDP
+  Select if CLK0 is shared between Rank0 and Rank1 in DDR4 DDP
+  $EN_DIS
+**/
+  UINT8                       DdpSharedClock;
 
 /** Offset 0x0BF4 - Select if ZQ pin is shared between Rank0 and Rank1 in DDR4 DDP
   ESelect if ZQ pin is shared between Rank0 and Rank1 in DDR4 DDP
@@ -2761,9 +4461,16 @@ typedef struct {
 **/
   UINT8                       ThrtCkeMinTmr;
 
-/** Offset 0x0C2B - Reserved
+/** Offset 0x0C2B - Allow Opp Ref Below Write Threhold
+  Allow opportunistic refreshes while we don't exit power down.
+  $EN_DIS
 **/
-  UINT8                       Reserved66[2];
+  UINT8                       AllowOppRefBelowWriteThrehold;
+
+/** Offset 0x0C2C - Write Threshold
+  Number of writes that can be accumulated while CKE is low before CKE is asserted.
+**/
+  UINT8                       WriteThreshold;
 
 /** Offset 0x0C2D - Rapl Power Floor Ch0
   Power budget ,range[255;0],(0= 5.3W Def)
@@ -2812,9 +4519,11 @@ typedef struct {
 **/
   UINT8                       UserBudgetEnable;
 
-/** Offset 0x0C35 - Reserved
+/** Offset 0x0C35 - Opportunistic Self Refresh
+  Enable\Disable Opportunistic Self Refresh.
+  0:Disabled, 1:Enabled
 **/
-  UINT8                       Reserved67;
+  UINT8                       OpportunisticSref;
 
 /** Offset 0x0C36 - Power Down Mode
   This option controls command bus tristating during idle periods
@@ -2849,9 +4558,47 @@ typedef struct {
 **/
   UINT8                       PcdSerialDebugLevel;
 
-/** Offset 0x0C3B - Reserved
+/** Offset 0x0C3B - MRC Safe Mode Override
+  SafeModeOverride[0] Enable DdrSafeMode override, SafeModeOverride[1] Enable McSafeMode
+  override, SafeModeOverride[2] Enable MrcSafeMode override, SafeModeOverride[3]
+  Enable Training Algorithm (TrainingEnables) safe mode override, SafeModeOverride[4]
+  Enable SaGv safe mode override
 **/
-  UINT8                       Reserved68[8];
+  UINT8                       SafeModeOverride;
+
+/** Offset 0x0C3C - MRC Safe Mode Support
+  MrcSafeMode[0]: Safe Frequency, MrcSafeMode[1]: Safe Gear, SafeMode[2]: Safe VCC
+  IOG/CLK, SafeMode[3]: Safe VCC DDQ
+**/
+  UINT8                       MrcSafeMode;
+
+/** Offset 0x0C3D - Retrain On Working Channel
+  Enables/Disable Retrain On Working Channel feature
+  $EN_DIS
+**/
+  UINT8                       RetrainToWorkingChannel;
+
+/** Offset 0x0C3E - DDR Phy Safe Mode Support
+  DdrSafeMode[0]: Basic PM Features, DdrSafeMode[1]: Spine Gating, DdrSafeMode[2]:
+  Advanced DCC, DdrSafeMode[3]: R2R Training, DdrSafeMode[4]: Transformer Mode, DdrSafeMode[5]:
+  PLL Operation, DdrSafeMode[6]: Safe ODT/SenseAmp Timing, DdrSafeMode[7]: Vtt Termination,
+  DdrSafeMode[8]: Periodic Comp
+**/
+  UINT16                      DdrSafeMode;
+
+/** Offset 0x0C40 - Mc Safe Mode Support
+  McSafeMode[0]: Clk Gate / BGF, McSafeMode[1]: CKE Pdwn, McSafeMode[2]: Tristate,
+  McSafeMode[3]: PHY Power States / Clock Spine, McSafeMode[4]: Same Rank TA, McSafeMode[5]:
+  Different Rank TA, McSafeMode[6]: MR4_Period / ZQCAL_Period McSafeMode[7]: LP5
+  Wck Mode, SafeMode[8]: Self Refresh, McSafeMode[9]: WR/RD Retraining, McSafeMode[10]:
+  Power Saving
+**/
+  UINT16                      McSafeMode;
+
+/** Offset 0x0C42 - Board Stack Up
+  0: Typical, 1: Frequency Limited
+**/
+  UINT8                       BoardStackUp;
 
 /** Offset 0x0C43 - Ask MRC to clear memory content
   Ask MRC to clear memory content <b>0: Do not Clear Memory;</b> 1: Clear Memory.
@@ -2864,9 +4611,11 @@ typedef struct {
 **/
   UINT8                       UsbTcPortEnPreMem;
 
-/** Offset 0x0C45 - Reserved
+/** Offset 0x0C45 - Power Down Mode
+  This option controls command bus tristating during idle periods
+  0x0:Enable, 0x1:Disable, 0x2:Auto
 **/
-  UINT8                       Reserved69;
+  UINT8                       PwDownMode;
 
 /** Offset 0x0C46 - Post Code Output Port
   This option configures Post Code Output Port
@@ -2884,9 +4633,10 @@ typedef struct {
 **/
   UINT8                       CridEnable;
 
-/** Offset 0x0C4A - Reserved
+/** Offset 0x0C4A - Pwr Down Idle Timer
+  Default 0 = AUTO. Range is 30 to 2000(in us)
 **/
-  UINT8                      Reserved70[2];
+  UINT16                      PwDownIdleTimer;
 
 /** Offset 0x0C4C - BCLK RFI Frequency
   Bclk RFI Frequency for each SAGV point in Hz units. 98000000Hz = 98MHz <b>0 - No
@@ -2927,18 +4677,60 @@ typedef struct {
 **/
   UINT8                       SerialDebugMrcLevel;
 
-/** Offset 0x0C62 - Reserved
+/** Offset 0x0C62 - DdrOneDpc
+  DDR 1DPC performance feature for 2R DIMMs. Can be enabled on DIMM0 or DIMM1 only,
+  or on both (default)
+  0: Disabled, 1: Enabled on DIMM0 only, 2: Enabled on DIMM1 only, 3: Enabled
 **/
-  UINT8                       Reserved71[11];
+  UINT8                       DdrOneDpc;
+
+/** Offset 0x0C63 - Override Driver Type
+  Override Driver Type. 0=Auto, 1=CMOS, 2=NMOS
+**/
+  UINT8                       OverrideDriverType;
+
+/** Offset 0x0C64 - Lp5 Bypass Vddq Limits
+  Bypass Lp5 Vccddq Fuse limits. Advised to keep disabled
+**/
+  UINT8                       Lp5BypassVddqLimits;
+
+/** Offset 0x0C65 - Enable/Disable I2cPostcode
+  Enable (Default): Postcode via I2C, Disable: Postcode via Port80
+  $EN_DIS
+**/
+  UINT8                       I2cPostCodeEnable;
+
+/** Offset 0x0C66 - Vddq Voltage Override for CMOS
+  # is multiple of 1mV where 0 means Auto.
+**/
+  UINT16                      VddqVoltageOverride;
+
+/** Offset 0x0C68 - VccIog Voltage Override
+  # is multiple of 1mV where 0 means Auto.
+**/
+  UINT16                      VccIogVoltageOverride;
+
+/** Offset 0x0C6A - VccClk Voltage Override
+  # is multiple of 1mV where 0 means Auto.
+**/
+  UINT16                      VccClkVoltageOverride;
+
+/** Offset 0x0C6C - Extended Bank Hashing
+  Eanble/Disable ExtendedBankHashing
+  $EN_DIS
+**/
+  UINT8                       ExtendedBankHashing;
 
 /** Offset 0x0C6D - RH pTRR LFSR1 Mask
   Row Hammer pTRR LFSR1 Mask, 1/2^(value)
 **/
   UINT8                       Lfsr1Mask;
 
-/** Offset 0x0C6E - Reserved
+/** Offset 0x0C6E - Refresh Watermarks
+  Refresh Watermarks: 0-Low, 1-High (default)
+  0:Set Refresh Watermarks to Low, 1:Set Refresh Watermarks to High (Default)
 **/
-  UINT8                       Reserved72;
+  UINT8                       RefreshWm;
 
 /** Offset 0x0C6F - Command Pins Mapping
   BitMask where bits [3:0] are Controller 0 Channel [3:0] and bits [7:4] are Controller
@@ -2952,9 +4744,17 @@ typedef struct {
 **/
   UINT8                       CmdMirror;
 
-/** Offset 0x0C71 - Reserved
+/** Offset 0x0C71 - Skip override boot mode When Fw Update.
+  When set to TRUE and boot mode is BOOT_ON_FLASH_UPDATE, skip setting boot mode to
+  BOOT_WITH_FULL_CONFIGURATION in PEI memory init.
+  $EN_DIS
 **/
-  UINT8                       Reserved73[3];
+  UINT8                       SiSkipOverrideBootModeWhenFwUpdate;
+
+/** Offset 0x0C72 - Opportunistic Self Refresh IdleTimer
+  Default 0 = AUTO. Range is 500 to 10000(in us)
+**/
+  UINT16                      OppSrefIdleTmr;
 
 /** Offset 0x0C74 - LowerBasicMemTestSize
   Reduce BasicMemoryTest size WA: 0(Default)=Disable, 1=Enable
@@ -2962,9 +4762,33 @@ typedef struct {
 **/
   UINT8                       LowerBasicMemTestSize;
 
-/** Offset 0x0C75 - Reserved
+/** Offset 0x0C75 - Board Topology
+  0: Daisy, 1: Tee
 **/
-  UINT8                       Reserved74[20];
+  UINT8                       BoardTopology;
+
+/** Offset 0x0C76 - RxDqsDelayTempCoeff
+  Default = 4. Range from 0-255
+**/
+  UINT8                       RxDqsDelayTempCoeff;
+
+/** Offset 0x0C77
+**/
+  UINT8                       MrcFspmUpdRsvd[15];
+
+/** Offset 0x0C86 - PPR Test Type
+  Select memory tests used in Post Package Repair flow. This option is only valid
+  if PPR=1, otherwise ignored. Bit 0: WCMATS8 test, Bit 1: Data Retention test, Bit
+  2: X March test, Bit 3: X March G test, Bit 4: Y March Short test, Bit 5: Y March
+  Long test. Default=0x3, WCMATS8 and data retention
+**/
+  UINT8                       PprTestType;
+
+/** Offset 0x0C87 - PreMemRsvd
+  Reserved for Pre-Mem
+  $EN_DIS
+**/
+  UINT8                       ReservedFspmUpd[2];
 
 /** Offset 0x0C89 - Skip external display device scanning
   Enable: Do not scan for external display device, Disable (Default): Scan external
@@ -2998,9 +4822,9 @@ typedef struct {
 **/
   UINT8                       BdatTestType;
 
-/** Offset 0x0C8E - Reserved
+/** Offset 0x0C8E
 **/
-  UINT8                       Reserved75[2];
+  UINT8                       Rsvd330[2];
 
 /** Offset 0x0C90 - PMR Size
   Size of PMR memory buffer. 0x400000 for normal boot and 0x200000 for S3 boot
@@ -3012,9 +4836,21 @@ typedef struct {
 **/
   UINT8                       PreBootDmaMask;
 
-/** Offset 0x0C95 - Reserved
+/** Offset 0x0C95
 **/
-  UINT8                       Reserved76[5];
+  UINT8                       Rsvd340[1];
+
+/** Offset 0x0C96 - Delta T12 Power Cycle Delay required in ms
+  Select the value for delay required. 0= No delay, 0xFFFF(Default) = Auto calculate
+  T12 Delay to max 500ms
+  0 : No Delay, 0xFFFF : Auto Calulate T12 Delay
+**/
+  UINT16                      DeltaT12PowerCycleDelay;
+
+/** Offset 0x0C98 - HgSubSystemId
+  Hybrid Graphics SubSystemId
+**/
+  UINT16                      HgSubSystemId;
 
 /** Offset 0x0C9A - Platform LID Status for LFP Displays.
   LFP Display Lid Status (LID_STATUS enum): 0 (Default): LidClosed, 1: LidOpen.
@@ -3044,9 +4880,108 @@ typedef struct {
 **/
   UINT32                      VgaMessage;
 
-/** Offset 0x0CA8 - Reserved
+/** Offset 0x0CA8 - SaPreMemTestRsvd
+  Reserved for SA Pre-Mem Test
+  $EN_DIS
 **/
-  UINT8                       Reserved77[124];
+  UINT8                       SaPreMemTestRsvd[75];
+
+/** Offset 0x0CF3 - PPR Run Once
+  When Eanble, PPR will run only once and then is disabled at next training cycle
+  $EN_DIS
+**/
+  UINT8                       PprRunOnce;
+
+/** Offset 0x0CF4 - PPR Run During Fastboot
+  When Eanble, PPR will run during fastboot
+  $EN_DIS
+**/
+  UINT8                       PprRunAtFastboot;
+
+/** Offset 0x0CF5 - PPR Repair Type
+  PPR Repair Type: 0:Do not Repair (Default), 1:Soft Repair, 2:Hard Repair
+  0:Do not Repair (Default), 1:Soft Repair, 2:Hard Repair
+**/
+  UINT8                       PprRepairType;
+
+/** Offset 0x0CF6 - PPR Error Injection
+  When Eanble, PPR will inject bad rows during testing
+  $EN_DIS
+**/
+  UINT8                       PprErrorInjection;
+
+/** Offset 0x0CF7 - PPR ForceRepair
+  When Eanble, PPR will force repair some rows many times (90)
+  $EN_DIS
+**/
+  UINT8                       PprForceRepair;
+
+/** Offset 0x0CF8 - PPR Repair Controller
+  PPR repair controller: User chooses to force repair specifc address
+**/
+  UINT8                       PprRepairController;
+
+/** Offset 0x0CF9 - PPR Repair Channel
+  PPR repair Channel: User chooses to force repair specifc address
+**/
+  UINT8                       PprRepairChannel;
+
+/** Offset 0x0CFA - PPR Repair Dimm
+  PPR repair Dimm: User chooses to force repair specifc address
+**/
+  UINT8                       PprRepairDimm;
+
+/** Offset 0x0CFB - PPR Repair Rank
+  PPR repair Rank: User chooses to force repair specifc address
+**/
+  UINT8                       PprRepairRank;
+
+/** Offset 0x0CFC - PPR Repair Row
+  PPR repair Row: User chooses to force repair specifc address
+**/
+  UINT32                      PprRepairRow;
+
+/** Offset 0x0D00 - PPR Repair Physical Address Low
+  PPR repair Physical Address Low: User chooses to force repair specifc address
+**/
+  UINT32                      PprRepairPhysicalAddrLow;
+
+/** Offset 0x0D04 - PPR Repair Physical Address High
+  PPR repair Physical Address High: User chooses to force repair specifc address
+**/
+  UINT32                      PprRepairPhysicalAddrHigh;
+
+/** Offset 0x0D08 - PPR Repair BankGroup
+  PPR repair BankGroup: User chooses to force repair specifc address
+**/
+  UINT8                       PprRepairBankGroup;
+
+/** Offset 0x0D09 - PPR Repair Bank
+  PPR repair Bank: User chooses to force repair specifc address
+**/
+  UINT8                       PprRepairBank;
+
+/** Offset 0x0D0A - DIMM CA ODT Split Training
+  Enable/Disable DIMM CA ODT Split Training
+  $EN_DIS
+**/
+  UINT8                       DIMMODTCASPLIT;
+
+/** Offset 0x0D0B - CMD Drive Strength Split
+  Enable/Disable CMD Drive Strength Split
+  $EN_DIS
+**/
+  UINT8                       CMDDSSPLIT;
+
+/** Offset 0x0D0C - CMD Slew Rate Split Training
+  Enable/Disable CMD Slew Rate Split Training
+  $EN_DIS
+**/
+  UINT8                       CMDSRSPLIT;
+
+/** Offset 0x0D0D
+**/
+  UINT8                       SaFspmUpdRsvd[23];
 
 /** Offset 0x0D24 - TotalFlashSize
   Enable/Disable. 0: Disable, define default value of TotalFlashSize , 1: enable
@@ -3060,9 +4995,15 @@ typedef struct {
 **/
   UINT16                      BiosSize;
 
-/** Offset 0x0D28 - Reserved
+/** Offset 0x0D28 - SecurityTestRsvd
+  Reserved for SA Pre-Mem Test
+  $EN_DIS
 **/
-  UINT8                       Reserved78[28];
+  UINT8                       SecurityTestRsvd[12];
+
+/** Offset 0x0D34
+**/
+  UINT8                       SecFspmUpdRsvd[16];
 
 /** Offset 0x0D44 - Smbus dynamic power gating
   Disable or Enable Smbus dynamic power gating.
@@ -3076,9 +5017,17 @@ typedef struct {
 **/
   UINT8                       WdtDisableAndLock;
 
-/** Offset 0x0D46 - Reserved
+/** Offset 0x0D46 - SoC BCLK PLL configuration
+  Configure SoC BCLK PLL state
+  $EN_DIS
 **/
-  UINT8                       Reserved79[2];
+  UINT8                       SocBclkPllOn;
+
+/** Offset 0x0D47 - CPU BCLK PLL configuration
+  Configure CPU BCLK PLL state
+  $EN_DIS
+**/
+  UINT8                       CpuBclkPllOn;
 
 /** Offset 0x0D48 - SMBUS SPD Write Disable
   Set/Clear Smbus SPD Write Disable. 0: leave SPD Write Disable bit; 1: set SPD Write
@@ -3087,9 +5036,35 @@ typedef struct {
 **/
   UINT8                       SmbusSpdWriteDisable;
 
-/** Offset 0x0D49 - Reserved
+/** Offset 0x0D49 - Dmi Tran Co Over En
+  Enable/Disable Lane Transmitter Coefficient.
 **/
-  UINT8                       Reserved80[34];
+  UINT8                       PchDmiTranCoOverEn[8];
+
+/** Offset 0x0D51 - Dmi Tran Co Over Post Cur
+  Lane Transmitter Post-Cursor Coefficient Override.
+**/
+  UINT8                       PchDmiTranCoOverPostCur[8];
+
+/** Offset 0x0D59 - Dmi Tran Co Over Pre Cur
+  Lane Transmitter Pre-Cursor Coefficient Override.
+**/
+  UINT8                       PchDmiTranCoOverPreCur[8];
+
+/** Offset 0x0D61 - Dmi Up Port Tran Preset
+  Upstream Port Lane Transmitter Preset.
+**/
+  UINT8                       PchDmiUpPortTranPreset[8];
+
+/** Offset 0x0D69 - Dmi UpPort Tran Preset En
+  0: POR setting, 1: force enable, 2: force disable.
+**/
+  UINT8                       PchDmiUpPortTranPresetEn;
+
+/** Offset 0x0D6A - Dmi Rtlepceb
+  DMI Remote Transmit Link Equalization Preset/Coefficient Evaluation Bypass (RTLEPCEB).
+**/
+  UINT8                       PchDmiRtlepceb;
 
 /** Offset 0x0D6B - HECI Timeouts
   0: Disable, 1: Enable (Default) timeout check for HECI
@@ -3140,9 +5115,9 @@ typedef struct {
 **/
   UINT8                       SkipCpuReplacementCheck;
 
-/** Offset 0x0D73 - Reserved
+/** Offset 0x0D73
 **/
-  UINT8                       Reserved81[100];
+  UINT8                       PchMeFspmUpdRsvd[100];
 
 /** Offset 0x0DD7 - Avx2 Voltage Guardband Scaling Factor
   AVX2 Voltage Guardband Scale factor applied to AVX2 workloads. Range is 0-200 in
@@ -3163,9 +5138,9 @@ typedef struct {
 **/
   UINT8                       SerialIoUartDebugMode;
 
-/** Offset 0x0DDA - Reserved
+/** Offset 0x0DDA
 **/
-  UINT8                      Reserved82[2];
+  UINT16                      Rsvd391;
 
 /** Offset 0x0DDC - SerialIoUartDebugRxPinMux - FSPM
   Select RX pin muxing for SerialIo UART used for debug
@@ -3189,9 +5164,177 @@ typedef struct {
 **/
   UINT32                      SerialIoUartDebugCtsPinMux;
 
-/** Offset 0x0DEC - Reserved
+/** Offset 0x0DEC - Serial Io Uart Debug Pci Base
+  Specify PciCfgBase address. Allows for SerialIO UART functionality outside Bus 0
 **/
-  UINT8                      Reserved83[164];
+  UINT32                      SerialIoUartDebugPciCfgBase;
+
+/** Offset 0x0DF0 - Memory Subsystem voltage mode
+  Memory Subsystem voltage mode; <b>0: Adaptive</b>; 1: Override.
+  $EN_DIS
+**/
+  UINT8                       MemSSVoltageMode;
+
+/** Offset 0x0DF1
+**/
+  UINT8                       Rsvd390;
+
+/** Offset 0x0DF2 - Memory Subsystem Adaptive Voltage
+  Adaptive voltage applied to the memory when the cpu is operating in adaptive mode.
+  Valid Range 0 to 2000
+**/
+  UINT16                      MemSSAdaptiveVoltage;
+
+/** Offset 0x0DF4 - Memory Subsystem voltage override
+  The Memory Subsystem voltage override which is applied to the entire range of memory
+  frequencies. Valid Range 0 to 2000
+**/
+  UINT16                      MemSSVoltageOverride;
+
+/** Offset 0x0DF6 - Memory Subsystem VF Point Offset Mode
+  Selects Memory Subsystem Voltage & Frequency Offset mode between Legacy and Selection
+  modes. In Legacy Mode, setting a global offset for the entire VF curve. In Selection
+  Mode, setting a selected VF point; <b>0: Legacy</b>; 1: Selection.
+  0:Legacy, 1:Selection
+**/
+  UINT8                       MemSSVfPointOffsetMode;
+
+/** Offset 0x0DF7 - Maximum Memory Subsystem turbo ratio override
+  Maximum Memory Subsystem turbo ratio override allows to increase memory frequency
+  beyond the fused max turbo ratio limit. <b>0: Hardware defaults.</b>  Range: 0-85
+**/
+  UINT8                       MemSSMaxOcRatio;
+
+/** Offset 0x0DF8 - Memory Subsystem Turbo voltage Offset
+  The voltage offset applied to the memory while operating in turbo mode. Valid Range 0 to 1000
+**/
+  UINT16                      MemSSVoltageOffset;
+
+/** Offset 0x0DFA - Select Core(s) and RING DLVR Mode
+  DEPRECATED. Select Core(s) and RING DLVR Mode). <b>0: Regulation Mode</b>; 1: Power Gate Mode
+  0:Regulation Mode, 1:Power Gate Mode
+**/
+  UINT8                       CpuDlvrMode;
+
+/** Offset 0x0DFB - Maximum clr turbo ratio override
+  Maximum clr turbo ratio override allows to increase CPU clr frequency beyond the
+  fused max turbo ratio limit. <b>0: Hardware defaults.</b>  Range: 0-85
+**/
+  UINT8                       NguMaxOcRatio;
+
+/** Offset 0x0DFC - NGU voltage mode
+  NGU voltage mode; <b>0: Adaptive</b>; 1: Override.
+  $EN_DIS
+**/
+  UINT8                       NguVoltageMode;
+
+/** Offset 0x0DFD - NGU Ratio
+  Sets the Ratio for NGU when SAGV is enabled, using SAVG B2P Mailbox cmd 0x22 and
+  subcommand 0x1. When this value is zero, dynamic mode is selected and NGU ratio
+  can be modified using OCMB cmd 0x11. When valid ratio value is set, static mode
+  is selected with the fixed ratio specified by this value.. <b>0: Hardware defaults.</b>
+  Range: 0-85
+**/
+  UINT8                       NguRatio;
+
+/** Offset 0x0DFE - NGU voltage override
+  The NGU voltage override which is applied to the entire range of cpu NGU frequencies.
+  Valid Range 0 to 2000
+**/
+  UINT16                      NguVoltageOverride;
+
+/** Offset 0x0E00 - adaptive voltage applied during turbo frequencies
+  0(Default)=Minimal, 2000=Maximum
+**/
+  UINT16                      NguAdaptiveVoltage;
+
+/** Offset 0x0E02 - NGU Turbo voltage Offset
+  The voltage offset applied to the NGU while operating in turbo mode. Valid Range 0 to 1000
+**/
+  UINT16                      NguVoltageOffset;
+
+/** Offset 0x0E04 - NGU VF Point Offset Mode
+  Selects NGU Voltage & Frequency Offset mode between Legacy and Selection modes.
+  In Legacy Mode, setting a global offset for the entire VF curve. In Selection Mode,
+  setting a selected VF point; <b>0: Legacy</b>; 1: Selection.
+  0:Legacy, 1:Selection
+**/
+  UINT8                       NguVfPointOffsetMode;
+
+/** Offset 0x0E05
+**/
+  UINT8                       Rsvd410[1];
+
+/** Offset 0x0E06 - NGU VF Point Offset
+  Array used to specifies the NGU Voltage Offset applied to the each selected VF Point.
+  This voltage is specified in millivolts.
+**/
+  UINT16                      NguVfPointOffset[15];
+
+/** Offset 0x0E24 - NGU VF Point Offset Prefix
+  Sets the NguVfPointOffset value as positive or negative for corresponding core VF
+  Point; <b>0: Positive </b>; 1: Negative.
+**/
+  UINT8                       NguVfPointOffsetPrefix[15];
+
+/** Offset 0x0E33 - NGU VF Point Ratio
+  Array for the each selected NGU VF Point to display the ration.
+**/
+  UINT8                       NguVfPointRatio[15];
+
+/** Offset 0x0E42 - NGU VF Point Count
+  Number of supported NGU Voltage & Frequency Point Offset
+**/
+  UINT8                       NguVfPointCount;
+
+/** Offset 0x0E43
+**/
+  UINT8                       Rsvd420[11];
+
+/** Offset 0x0E4E - GT VF Point Offset Mode
+  Selects GT Voltage & Frequency Offset mode between Legacy and Selection modes. In
+  Legacy Mode, setting a global offset for the entire VF curve. In Selection Mode,
+  setting a selected VF point; <b>0: Legacy</b>; 1: Selection.
+  0:Legacy, 1:Selection
+**/
+  UINT8                       GtVfPointOffsetMode;
+
+/** Offset 0x0E4F
+**/
+  UINT8                       Rsvd430[1];
+
+/** Offset 0x0E50 - GT VF Point Offset
+  Array used to specifies the GT Voltage Offset applied to the each selected VF Point.
+  This voltage is specified in millivolts.
+**/
+  UINT16                      GtVfPointOffset[15];
+
+/** Offset 0x0E6E - GT VF Point Offset Prefix
+  Sets the GtVfPointOffset value as positive or negative for corresponding core VF
+  Point; <b>0: Positive </b>; 1: Negative.
+**/
+  UINT8                       GtVfPointOffsetPrefix[15];
+
+/** Offset 0x0E7D - GT VF Point Ratio
+  Array for the each selected GT VF Point to display the ration.
+**/
+  UINT8                       GtVfPointRatio[15];
+
+/** Offset 0x0E8C - GT VF Point Count
+  Number of supported GT Voltage & Frequency Point Offset
+**/
+  UINT8                       GtVfPointCount;
+
+/** Offset 0x0E8D - Time Measure
+  Time Measure: 0(Default)=Disable, 1=Enable
+  $EN_DIS
+**/
+  UINT8                       MrcTimeMeasure;
+
+/** Offset 0x0E8E - Must use static SPD data from VPD
+  Must use static SPD data from VPD and Spd Address is correct: Each bit maps to one dimm
+**/
+  UINT16                      MrcMustStaticSpdData;
 
 /** Offset 0x0E90 - TME Exclude Base Address
   TME Exclude Base Address.
@@ -3209,9 +5352,24 @@ typedef struct {
 **/
   UINT8                       GenerateNewTmeKey;
 
-/** Offset 0x0EA1 - Reserved
+/** Offset 0x0EA1 - CkdAddress Tabl
+  Specify CKD Address table for CH0D0/CH0D1/CH1D0&CH1D1
 **/
-  UINT8                       Reserved84[23];
+  UINT8                       CkdAddressTable[16];
+
+/** Offset 0x0EB1 - Channel to CKD QCK Mapping
+  Specify Channel to CKD QCK Mapping for CH0D0/CH0D1/CH1D0&CH1D1
+**/
+  UINT8                       ChannelToCkdQckMapping[8];
+
+/** Offset 0x0EB9 - DDRIO Clock to CKD DIMM
+  Specify DDRIO Clock to CKD DIMM for CH0D0/CH0D1/CH1D0&CH1D1
+**/
+  UINT8                       PhyClockToCkdDimm[8];
+
+/** Offset 0x0EC1
+**/
+  UINT8                       ReservedFspmUpd2[7];
 } FSP_M_CONFIG;
 
 /** Fsp M UPD Configuration
@@ -3230,11 +5388,11 @@ typedef struct {
 **/
   FSP_M_CONFIG                FspmConfig;
 
-/** Offset 0x0EB8
+/** Offset 0x0EC8
 **/
   UINT8                       Rsvd500[6];
 
-/** Offset 0x0EBE
+/** Offset 0x0ECE
 **/
   UINT16                      UpdTerminator;
 } FSPM_UPD;
diff --git a/src/vendorcode/intel/fsp/fsp2_0/meteorlake/x86_32/FspsUpd.h b/src/vendorcode/intel/fsp/fsp2_0/meteorlake/x86_32/FspsUpd.h
index e5c5847d06..797695d32c 100644
--- a/src/vendorcode/intel/fsp/fsp2_0/meteorlake/x86_32/FspsUpd.h
+++ b/src/vendorcode/intel/fsp/fsp2_0/meteorlake/x86_32/FspsUpd.h
@@ -1,6 +1,6 @@
 /** @file
 
-Copyright (c) 2024, Intel Corporation. All rights reserved.<BR>
+Copyright (c) 2025, Intel Corporation. All rights reserved.<BR>
 
 Redistribution and use in source and binary forms, with or without modification,
 are permitted provided that the following conditions are met:
@@ -123,9 +123,9 @@ typedef struct {
 **/
   UINT8                       ShowSpiController;
 
-/** Offset 0x0056 - Reserved
+/** Offset 0x0056
 **/
-  UINT8                       Reserved0[2];
+  UINT8                       Rsvd010[2];
 
 /** Offset 0x0058 - MicrocodeRegionBase
   Memory Base of Microcode Updates
@@ -161,9 +161,14 @@ typedef struct {
 **/
   UINT8                       SataPortsDevSlp[8];
 
-/** Offset 0x0072 - Reserved
+/** Offset 0x0072
 **/
-  UINT8                       Reserved1[34];
+  UINT8                       Rsvd020[2];
+
+/** Offset 0x0074 - SATA DEVSLP GPIO Pin
+  Select SATA DEVSLP Pin. Refer to GPIO_*_MUXING_SATA_DEVSLP_x* for possible values.
+**/
+  UINT32                      SataPortDevSlpPinMux[8];
 
 /** Offset 0x0094 - Enable USB2 ports
   Enable/disable per USB2 ports. One byte for each port, byte0 for port0, byte1 for
@@ -183,9 +188,9 @@ typedef struct {
 **/
   UINT8                       XdciEnable;
 
-/** Offset 0x00AF - Reserved
+/** Offset 0x00AF
 **/
-  UINT8                       Reserved2;
+  UINT8                       Rsvd030;
 
 /** Offset 0x00B0 - Address of PCH_DEVICE_INTERRUPT_CONFIG table.
   The address of the table of PCH_DEVICE_INTERRUPT_CONFIG.
@@ -231,9 +236,9 @@ typedef struct {
 **/
   UINT8                       PchHdaVerbTableEntryNum;
 
-/** Offset 0x00C2 - Reserved
+/** Offset 0x00C2
 **/
-  UINT8                       Reserved3[2];
+  UINT8                       Rsvd040[2];
 
 /** Offset 0x00C4 - PCH HDA Verb Table Pointer
   Pointer to Array of pointers to Verb Table.
@@ -292,9 +297,33 @@ typedef struct {
 **/
   UINT8                       SerialIoSpiCsState[7];
 
-/** Offset 0x0103 - Reserved
+/** Offset 0x0103
 **/
-  UINT8                       Reserved4[141];
+  UINT8                       Rsvd050[1];
+
+/** Offset 0x0104 - Serial IO SPI CS Pin Muxing
+  Select SerialIo SPI CS pin muxing. Refer to GPIO_*_MUXING_SERIALIO_SPIx_CS* for
+  possible values.
+**/
+  UINT32                      SerialIoSpiCsPinMux[14];
+
+/** Offset 0x013C - Serial IO SPI CLK Pin Muxing
+  Select SerialIo SPI CS pin muxing. Refer to GPIO_*_MUXING_SERIALIO_SPIx_CLK* for
+  possible values.
+**/
+  UINT32                      SerialIoSpiClkPinMux[7];
+
+/** Offset 0x0158 - Serial IO SPI MISO Pin Muxing
+  Select SerialIo SPI MISO pin muxing. Refer to GPIO_*_MUXING_SERIALIO_SPIx_MISO*
+  for possible values.
+**/
+  UINT32                      SerialIoSpiMisoPinMux[7];
+
+/** Offset 0x0174 - Serial IO SPI MOSI Pin Muxing
+  Select SerialIo SPI MOSI pin muxing. Refer to GPIO_*_MUXING_SERIALIO_SPIx_MOSI*
+  for possible values.
+**/
+  UINT32                      SerialIoSpiMosiPinMux[7];
 
 /** Offset 0x0190 - UARTn Device Mode
   Selects Uart operation mode. N represents controller index: Uart0, Uart1, ... Available
@@ -303,9 +332,9 @@ typedef struct {
 **/
   UINT8                       SerialIoUartMode[7];
 
-/** Offset 0x0197 - Reserved
+/** Offset 0x0197
 **/
-  UINT8                       Reserved5;
+  UINT8                       Rsvd060[1];
 
 /** Offset 0x0198 - Default BaudRate for each Serial IO UART
   Set default BaudRate Supported from 0 - default to 6000000
@@ -343,9 +372,9 @@ typedef struct {
 **/
   UINT8                       SerialIoUartAutoFlow[7];
 
-/** Offset 0x01DE - Reserved
+/** Offset 0x01DE
 **/
-  UINT8                       Reserved6[2];
+  UINT8                       Rsvd070[2];
 
 /** Offset 0x01E0 - SerialIoUartRtsPinMuxPolicy
   Select SerialIo Uart Rts pin muxing. Refer to GPIO_*_MUXING_SERIALIO_UARTx_RTS*
@@ -383,9 +412,9 @@ typedef struct {
 **/
   UINT8                       SerialIoI2cMode[8];
 
-/** Offset 0x025F - Reserved
+/** Offset 0x025F
 **/
-  UINT8                       Reserved7;
+  UINT8                       Rsvd080[1];
 
 /** Offset 0x0260 - Serial IO I2C SDA Pin Muxing
   Select SerialIo I2c Sda pin muxing. Refer to GPIO_*_MUXING_SERIALIO_I2Cx_SDA* for
@@ -412,9 +441,60 @@ typedef struct {
 **/
   UINT8                       SerialIoI3cMode[2];
 
-/** Offset 0x02AA - Reserved
+/** Offset 0x02AA
 **/
-  UINT8                       Reserved8[38];
+  UINT8                       Rsvd090[2];
+
+/** Offset 0x02AC - Serial IO I3C SDA Pin Muxing
+  Select SerialIo I3c Sda pin muxing. Refer to GPIO_*_MUXING_SERIALIO_I3Cx_SDA* for
+  possible values.
+**/
+  UINT32                      SerialIoI3cSdaPinMux[2];
+
+/** Offset 0x02B4 - Serial IO I3C SDA Pad Termination
+  0x0: Hardware default, 0x1: None, 0x13: 1kOhm weak pull-up, 0x15: 5kOhm weak pull-up,
+  0x19: 20kOhm weak pull-up - Enable/disable SerialIo I3C0,I3C1,... pads termination
+  respectively. One byte for each controller, byte0 for I3C0, byte1 for I3C1, and so on.
+**/
+  UINT8                       SerialIoI3cSdaPadTermination[2];
+
+/** Offset 0x02B6
+**/
+  UINT8                       Rsvd100[2];
+
+/** Offset 0x02B8 - Serial IO I3C SCL Pin Muxing
+  Select SerialIo I3c Scl pin muxing. Refer to GPIO_*_MUXING_SERIALIO_I3Cx_SCL* for
+  possible values.
+**/
+  UINT32                      SerialIoI3cSclPinMux[2];
+
+/** Offset 0x02C0 - Serial IO I3C SCL Pad Termination
+  0x0: Hardware default, 0x1: None, 0x13: 1kOhm weak pull-up, 0x15: 5kOhm weak pull-up,
+  0x19: 20kOhm weak pull-up - Enable/disable SerialIo I3C0,I3C1,... pads termination
+  respectively. One byte for each controller, byte0 for I3C0, byte1 for I3C1, and so on.
+**/
+  UINT8                       SerialIoI3cSclPadTermination[2];
+
+/** Offset 0x02C2
+**/
+  UINT8                       Rsvd110[2];
+
+/** Offset 0x02C4 - Serial IO I3C SCL FB Pin Muxing
+  Select SerialIo I3c SclFb pin muxing. Refer to GPIO_*_MUXING_SERIALIO_I3Cx_SCL FB*
+  for possible values.
+**/
+  UINT32                      SerialIoI3cSclFbPinMux[2];
+
+/** Offset 0x02CC - Serial IO I3C SCL FB Pad Termination
+  0x0: Hardware default, 0x1: None, 0x13: 1kOhm weak pull-up, 0x15: 5kOhm weak pull-up,
+  0x19: 20kOhm weak pull-up - Enable/disable SerialIo I3C0,I3C1,... pads termination
+  respectively. One byte for each controller, byte0 for I3C0, byte1 for I3C1, and so on.
+**/
+  UINT8                       SerialIoI3cSclFbPadTermination[2];
+
+/** Offset 0x02CE
+**/
+  UINT8                       Rsvd120[2];
 
 /** Offset 0x02D0 - ISH GP GPIO Pin Muxing
   Determines ISH GP GPIO Pin muxing. See GPIO_*_MUXING_ISH_GP_x_GPIO_*. 'x' are GP_NUMBER
@@ -451,9 +531,15 @@ typedef struct {
 **/
   UINT32                      IshI2cSclPinMuxing[3];
 
-/** Offset 0x0348 - Reserved
+/** Offset 0x0348 - ISH I3C SDA Pin Muxing
+  Select ISH I3C SDA Pin muxing. Refer to GPIO_*_MUXING_ISH_I3Cx_SDA_* for possible values.
 **/
-  UINT8                      Reserved9[8];
+  UINT32                      IshI3cSdaPinMuxing;
+
+/** Offset 0x034C - ISH I3C SCL Pin Muxing
+  Select ISH I3C SCL Pin muxing. Refer to GPIO_*_MUXING_ISH_I3Cx_SCL_* for possible values.
+**/
+  UINT32                      IshI3cSclPinMuxing;
 
 /** Offset 0x0350 - ISH SPI MOSI Pin Muxing
   Select ISH SPI MOSI Pin muxing. Refer to GPIO_*_MUXING_ISH_SPIx_MOSI_* for possible values.
@@ -524,9 +610,13 @@ typedef struct {
 **/
   UINT8                       IshI2cSdaPadTermination[3];
 
-/** Offset 0x0393 - Reserved
+/** Offset 0x0393 - ISH I3C SDA Pad termination
+  0x0: Hardware default, 0x1: None, 0x13: 1kOhm weak pull-up, 0x15: 5kOhm weak pull-up,
+  0x19: 20kOhm weak pull-up - Enable/disable SerialIo I2C#N Sda pads termination
+  respectively. #N-byte for each controller, byte0 for I2C0 Sda, byte1 for I2C1 Sda,
+  and so on.
 **/
-  UINT8                       Reserved10;
+  UINT8                       IshI3cSdaPadTermination;
 
 /** Offset 0x0394 - ISH I2C SCL Pad termination
   0x0: Hardware default, 0x1: None, 0x13: 1kOhm weak pull-up, 0x15: 5kOhm weak pull-up,
@@ -536,9 +626,13 @@ typedef struct {
 **/
   UINT8                       IshI2cSclPadTermination[3];
 
-/** Offset 0x0397 - Reserved
+/** Offset 0x0397 - ISH I3C SCL Pad termination
+  0x0: Hardware default, 0x1: None, 0x13: 1kOhm weak pull-up, 0x15: 5kOhm weak pull-up,
+  0x19: 20kOhm weak pull-up - Enable/disable SerialIo I2C#N Scl pads termination
+  respectively. #N-byte for each controller, byte0 for I2C0 Scl, byte1 for I2C1 Scl,
+  and so on.
 **/
-  UINT8                       Reserved11;
+  UINT8                       IshI3cSclPadTermination;
 
 /** Offset 0x0398 - ISH SPI MOSI Pad termination
   0x0: Hardware default, 0x1: None, 0x13: 1kOhm weak pull-up, 0x15: 5kOhm weak pull-up,
@@ -676,18 +770,44 @@ typedef struct {
 **/
   UINT8                       PchTsnLinkSpeed;
 
-/** Offset 0x0461 - Reserved
+/** Offset 0x0461
 **/
-  UINT8                       Reserved12[19];
+  UINT8                       Rsvd130[3];
+
+/** Offset 0x0464 - PCH TSN MAC Address High Bits
+  Set TSN MAC Address High.
+**/
+  UINT32                      PchTsnMacAddressHigh;
+
+/** Offset 0x0468 - PCH TSN MAC Address Low Bits
+  Set TSN MAC Address Low.
+**/
+  UINT32                      PchTsnMacAddressLow;
+
+/** Offset 0x046C - PCH TSN MAC Address High Bits
+  Set TSN MAC Address High.
+**/
+  UINT32                      PchTsn1MacAddressHigh;
+
+/** Offset 0x0470 - PCH TSN MAC Address Low Bits
+  Set TSN MAC Address Low.
+**/
+  UINT32                      PchTsn1MacAddressLow;
 
 /** Offset 0x0474 - PCIe PTM enable/disable
   Enable/disable Precision Time Measurement for PCIE Root Ports.
 **/
   UINT8                       PciePtm[29];
 
-/** Offset 0x0491 - Reserved
+/** Offset 0x0491 - Disable DMI Power Gating
+  Enable/disable DMI Power Gating Disable.
+  $EN_DIS
 **/
-  UINT8                       Reserved13[29];
+  UINT8                       DmiPowerGatingDis;
+
+/** Offset 0x0492
+**/
+  UINT8                       Rsvd135[28];
 
 /** Offset 0x04AE - USB PDO Programming
   Enable/disable PDO programming for USB in PEI phase. Disabling will allow for programming
@@ -696,9 +816,9 @@ typedef struct {
 **/
   UINT8                       UsbPdoProgramming;
 
-/** Offset 0x04AF - Reserved
+/** Offset 0x04AF
 **/
-  UINT8                       Reserved14[5];
+  UINT8                       Rsvd140[5];
 
 /** Offset 0x04B4 - Power button debounce configuration
   Debounce time for PWRBTN in microseconds. For values not supported by HW, they will
@@ -706,9 +826,11 @@ typedef struct {
 **/
   UINT32                      PmcPowerButtonDebounce;
 
-/** Offset 0x04B8 - Reserved
+/** Offset 0x04B8 - PCH eSPI Host and Device BME enabled
+  PCH eSPI Host and Device BME enabled
+  $EN_DIS
 **/
-  UINT8                       Reserved15;
+  UINT8                       PchEspiBmeHostDeviceEnabled;
 
 /** Offset 0x04B9 - PCH eSPI Link Configuration Lock (SBLCL)
   Enable/Disable lock of communication through SET_CONFIG/GET_CONFIG to eSPI target
@@ -747,9 +869,9 @@ typedef struct {
 **/
   UINT8                       PchFivrExtVnnRailSupportedVoltageStates;
 
-/** Offset 0x04C1 - Reserved
+/** Offset 0x04C1
 **/
-  UINT8                       Reserved16;
+  UINT8                       Rsvd150;
 
 /** Offset 0x04C2 - External Vnn Voltage Value that will be used in S0ix/Sx states
   Value is given in 2.5mV increments (0=0mV, 1=2.5mV, 2=5mV...), Default is set to 420
@@ -809,9 +931,9 @@ typedef struct {
 **/
   UINT8                       PmcDbgMsgEn;
 
-/** Offset 0x04CF - Reserved
+/** Offset 0x04CF
 **/
-  UINT8                       Reserved17;
+  UINT8                       Rsvd160;
 
 /** Offset 0x04D0 - Pointer to ChipsetInit Binary
   ChipsetInit Binary Pointer.
@@ -823,9 +945,25 @@ typedef struct {
 **/
   UINT32                      ChipsetInitBinLen;
 
-/** Offset 0x04D8 - Reserved
+/** Offset 0x04D8 - Pointer to NPHY Binary
+  Nphy Binary Pointer.
 **/
-  UINT8                      Reserved18[16];
+  UINT32                      NphyBinPtr;
+
+/** Offset 0x04DC - Length of NPHY Binary
+  Nphy Binary Length.
+**/
+  UINT32                      NphyBinLen;
+
+/** Offset 0x04E0 - Pointer to SYNPS PHY Binary
+  Synps Binary Pointer.
+**/
+  UINT32                      SynpsPhyBinPtr;
+
+/** Offset 0x04E4 - Length of SYNPS PHY Binary
+  Synps Binary Length.
+**/
+  UINT32                      SynpsPhyBinLen;
 
 /** Offset 0x04E8 - FIVR Dynamic Power Management
   Enable/Disable FIVR Dynamic Power Management.
@@ -833,9 +971,9 @@ typedef struct {
 **/
   UINT8                       PchFivrDynPm;
 
-/** Offset 0x04E9 - Reserved
+/** Offset 0x04E9
 **/
-  UINT8                       Reserved19;
+  UINT8                       Rsvd170;
 
 /** Offset 0x04EA - External V1P05 Icc Max Value
   Granularity of this setting is 1mA and maximal possible value is 500mA
@@ -853,9 +991,37 @@ typedef struct {
 **/
   UINT16                      PchFivrExtVnnRailSxIccMaximum;
 
-/** Offset 0x04F0 - Reserved
+/** Offset 0x04F0 - USB Audio Offload enable
+  Enable/Disable USB Audio Offload capabilites. 0: disabled, 1: enabled (default)
+  $EN_DIS
 **/
-  UINT8                       Reserved20[14];
+  UINT8                       PchXhciUaolEnable;
+
+/** Offset 0x04F1 - PCH xHCI enable HS Interrupt IN Alarm
+  PCH xHCI enable HS Interrupt IN Alarm. 0: disabled (default), 1: enabled
+  $EN_DIS
+**/
+  UINT8                       PchXhciHsiiEnable;
+
+/** Offset 0x04F2
+**/
+  UINT8                       Rsvd175[2];
+
+/** Offset 0x04F4 - PCH GPIOV2 Unlock Data Buffer Address
+  Address of GPIO Unlock Data buffer
+**/
+  UINT32                      PchGpioUnlockDataPtr;
+
+/** Offset 0x04F8 - PCH GPIOV2 Unlock Data Buffer Size
+  Size of PCH GPIO Unlock Data Buffer
+**/
+  UINT32                      PchGpioUnlockDataSize;
+
+/** Offset 0x04FC - PchPostMemRsvd
+  Reserved for PCH Post-Mem
+  $EN_DIS
+**/
+  UINT8                       PchPostMemRsvd[2];
 
 /** Offset 0x04FE - CNVi Configuration
   This option allows for automatic detection of Connectivity Solution. [Auto Detection]
@@ -882,9 +1048,9 @@ typedef struct {
 **/
   UINT8                       CnviBtAudioOffload;
 
-/** Offset 0x0502 - Reserved
+/** Offset 0x0502
 **/
-  UINT8                       Reserved21[2];
+  UINT8                       Rsvd180[2];
 
 /** Offset 0x0504 - CNVi RF_RESET pin muxing
   Select CNVi RF_RESET# pin depending on board routing. LP/P/M: GPP_A8 = 0x2942E408(default)
@@ -988,9 +1154,9 @@ typedef struct {
 **/
   UINT8                       AmtSolEnabled;
 
-/** Offset 0x0521 - Reserved
+/** Offset 0x0521
 **/
-  UINT8                       Reserved22;
+  UINT8                       Rsvd190;
 
 /** Offset 0x0522 - OS Timer
   16 bits Value, Set OS watchdog timer. Setting is invalid if AmtEnabled is 0.
@@ -1018,9 +1184,9 @@ typedef struct {
 **/
   UINT8                       PcieRpEnableCpm[29];
 
-/** Offset 0x057D - Reserved
+/** Offset 0x057D
 **/
-  UINT8                       Reserved23[3];
+  UINT8                       Rsvd200[3];
 
 /** Offset 0x0580 - PCIE RP Detect Timeout Ms
   The number of milliseconds within 0~65535 in reference code will wait for link to
@@ -1075,9 +1241,9 @@ typedef struct {
 **/
   UINT8                       GnaEnable;
 
-/** Offset 0x05C1 - Reserved
+/** Offset 0x05C1
 **/
-  UINT8                       Reserved24[3];
+  UINT8                       Rsvd210[3];
 
 /** Offset 0x05C4 - TypeC port GPIO setting
   GPIO Ping number for Type C Aux Oritation setting, use the GpioPad that is defined
@@ -1120,9 +1286,15 @@ typedef struct {
 **/
   UINT8                       TcCstateLimit;
 
-/** Offset 0x0601 - Reserved
+/** Offset 0x0601 - Display port support policy in TCSS
+  This policy will enable/disable Display port support in IOM
+  $EN_DIS
 **/
-  UINT8                       Reserved25[3];
+  UINT8                       TcNotifyIgd;
+
+/** Offset 0x0602
+**/
+  UINT8                       Rsvd220[2];
 
 /** Offset 0x0604 - Intel Graphics VBT (Video BIOS Table) Size
   Size of Internal Graphics VBT Image
@@ -1135,9 +1307,11 @@ typedef struct {
 **/
   UINT8                       LidStatus;
 
-/** Offset 0x0609 - Reserved
+/** Offset 0x0609 - PchPostMemRsvd
+  Reserved for PCH Post-Mem
+  $EN_DIS
 **/
-  UINT8                       Reserved26[8];
+  UINT8                       SaPostMemRsvd[8];
 
 /** Offset 0x0611 - Enable VMD controller
   Enable/disable to VMD controller.0: Disable; 1: Enable(Default)
@@ -1157,9 +1331,10 @@ typedef struct {
 **/
   UINT8                       VmdPort[31];
 
-/** Offset 0x0632 - Reserved
+/** Offset 0x0632 - VMD Port Bus
+  VMD Root port bus number.
 **/
-  UINT8                       Reserved27[31];
+  UINT8                       VmdPortBus[31];
 
 /** Offset 0x0651 - VMD Port Device
   VMD Root port device number.
@@ -1171,9 +1346,9 @@ typedef struct {
 **/
   UINT8                       VmdPortFunc[31];
 
-/** Offset 0x068F - Reserved
+/** Offset 0x068F
 **/
-  UINT8                       Reserved28;
+  UINT8                       Rsvd230;
 
 /** Offset 0x0690 - VMD Variable
   VMD Variable Pointer.
@@ -1195,9 +1370,12 @@ typedef struct {
 **/
   UINT32                      VmdMemBar2Base;
 
-/** Offset 0x06A0 - Reserved
+/** Offset 0x06A0 - TCSS CPU USB PDO Programming
+  Enable/disable PDO programming for TCSS CPU USB in PEI phase. Disabling will allow
+  for programming during later phase. 1: enable, 0: disable
+  $EN_DIS
 **/
-  UINT8                       Reserved29;
+  UINT8                       TcssCpuUsbPdoProgramming;
 
 /** Offset 0x06A1 - Enable/Disable PMC-PD Solution
   This policy will enable/disable PMC-PD Solution vs EC-TCPC Solution
@@ -1250,18 +1428,20 @@ typedef struct {
 **/
   UINT8                       VccSt;
 
-/** Offset 0x06B1 - Reserved
+/** Offset 0x06B1
 **/
-  UINT8                       Reserved30;
+  UINT8                       Rsvd240[1];
 
 /** Offset 0x06B2 - ITBT DMA LTR
   TCSS DMA1, DMA2 LTR value
 **/
   UINT16                      ITbtDmaLtr[2];
 
-/** Offset 0x06B6 - Reserved
+/** Offset 0x06B6 - Enable/Disable CrashLog
+  Enable(Default): Enable CPU CrashLog, Disable: Disable CPU CrashLog
+  $EN_DIS
 **/
-  UINT8                       Reserved31;
+  UINT8                       CpuCrashLogEnable;
 
 /** Offset 0x06B7 - Enable/Disable PTM
   This policy will enable/disable Precision Time Measurement for TCSS PCIe Root Ports
@@ -1284,9 +1464,9 @@ typedef struct {
 **/
   UINT8                       SaPcieItbtRpSnoopLatencyOverrideMultiplier[4];
 
-/** Offset 0x06C7 - Reserved
+/** Offset 0x06C7
 **/
-  UINT8                       Reserved32;
+  UINT8                       Rsvd250[1];
 
 /** Offset 0x06C8 - PCIE RP Snoop Latency Override Value
   Latency Tolerance Reporting, Snoop Latency Override Value.
@@ -1326,9 +1506,9 @@ typedef struct {
 **/
   UINT8                       TxtEnable;
 
-/** Offset 0x06E9 - Reserved
+/** Offset 0x06E9
 **/
-  UINT8                       Reserved33[3];
+  UINT8                       Rsvd260[3];
 
 /** Offset 0x06EC - CpuBistData
   Pointer CPU BIST Data
@@ -1342,9 +1522,20 @@ typedef struct {
 **/
   UINT32                      CpuMpPpi;
 
-/** Offset 0x06F4 - Reserved
+/** Offset 0x06F4 - Boot frequency
+  Select the performance state that the BIOS will set starting from reset vector.
+  0: Maximum battery performance. 1: Maximum non-turbo performance. <b>2: Turbo performance </b>
+  0:0, 1:1, 2:2
 **/
-  UINT8                       Reserved34[4];
+  UINT8                       BootFrequency;
+
+/** Offset 0x06F5
+**/
+  UINT8                       CpuPostMemRsvd[2];
+
+/** Offset 0x06F7
+**/
+  UINT8                       Rsvd270[1];
 
 /** Offset 0x06F8 - PpinSupport to view Protected Processor Inventory Number
   PPIN Feature Support to view Protected Processor Inventory Number. Disable to turn
@@ -1355,9 +1546,13 @@ typedef struct {
 **/
   UINT8                       PpinSupport;
 
-/** Offset 0x06F9 - Reserved
+/** Offset 0x06F9 - Memory size per thread allocated for Processor Trace
+  Memory size per thread for Processor Trace. Processor Trace requires 2^N alignment
+  and size in bytes per thread, from 4KB to 128MB.\n
+  <b> 0xff:none </b>, 0:4k, 0x1:8k, 0x2:16k, 0x3:32k, 0x4:64k, 0x5:128k, 0x6:256k,
+  0x7:512k, 0x8:1M, 0x9:2M, 0xa:4M. 0xb:8M, 0xc:16M, 0xd:32M, 0xe:64M, 0xf:128M
 **/
-  UINT8                       Reserved35;
+  UINT8                       ProcessorTraceMemSize;
 
 /** Offset 0x06FA - Smbios Type4 Max Speed Override
   Provide the option for platform to override the MaxSpeed field of Smbios Type 4.
@@ -1377,9 +1572,25 @@ typedef struct {
 **/
   UINT8                       AvxDisable;
 
-/** Offset 0x06FE - Reserved
+/** Offset 0x06FE - X2ApicEnable
+  Enable/Disable X2APIC Operating Mode. When this option is configured as 'Enabled',
+  'VT-d' option must be 'Enabled' and 'X2APIC Opt Out' option must be 'Disabled' as well.
+  $EN_DIS
 **/
-  UINT8                       Reserved36[58];
+  UINT8                       X2ApicEnable;
+
+/** Offset 0x06FF - ProcHot Demotion Algorithm configuration
+  ProcHot Demotion Algorithm configuration. Hardware Default/Disable; 0: Disable;<b>
+  1: Hardware Default</b>
+  0: Disable, 1: Hardware Default
+**/
+  UINT8                       ProcHotDemotion;
+
+/** Offset 0x0700 - ReservedCpuPostMemProduction
+  Reserved for CPU Post-Mem Production
+  $EN_DIS
+**/
+  UINT8                       ReservedCpuPostMemProduction[56];
 
 /** Offset 0x0738 - Enable Power Optimizer
   Enable DMI Power Optimizer on PCH side.
@@ -1397,9 +1608,9 @@ typedef struct {
 **/
   UINT8                       PchReadProtectionEnable[5];
 
-/** Offset 0x0743 - Reserved
+/** Offset 0x0743
 **/
-  UINT8                       Reserved37;
+  UINT8                       Rsvd280[1];
 
 /** Offset 0x0744 - PCH Protect Range Limit
   Left shifted address by 12 bits with address bits 11:0 are assumed to be FFFh for
@@ -1471,9 +1682,11 @@ typedef struct {
 **/
   UINT8                       PchIshPdtUnlock;
 
-/** Offset 0x0771 - Reserved
+/** Offset 0x0771 - PCH ISH Disable MSI Interrupts
+  0: False; 1: True.
+  $EN_DIS
 **/
-  UINT8                       Reserved38;
+  UINT8                       PchIshMsiInterrupt;
 
 /** Offset 0x0772 - Enable PCH Lan LTR capabilty of PCH internal LAN
   0: Disable; 1: Enable.
@@ -1578,9 +1791,11 @@ typedef struct {
 **/
   UINT8                       ThcAssignment[2];
 
-/** Offset 0x08F2 - Reserved
+/** Offset 0x08F2 - Touch Host Controller Interrupt Pin Mux
+  Set THC Pin Muxing Value if signal can be enabled on multiple pads. Refer to GPIO_*_MUXING_THC_SPIx_INTB_*
+  for possible values.
 **/
-  UINT8                       Reserved39[8];
+  UINT8                       ThcInterruptPinMuxing[8];
 
 /** Offset 0x08FA - Touch Host Controller Mode
   Switch between Intel THC protocol and Industry standard HID Over SPI protocol. 0x0:Thc, 0x1:Hid
@@ -1593,9 +1808,82 @@ typedef struct {
 **/
   UINT8                       ThcWakeOnTouch[2];
 
-/** Offset 0x08FE - Reserved
+/** Offset 0x08FE
 **/
-  UINT8                       Reserved40[110];
+  UINT8                       Rsvd290[2];
+
+/** Offset 0x0900 - Touch Host Controller Active Ltr
+  Expose Active Ltr for OS driver to set
+**/
+  UINT32                      ThcActiveLtr[2];
+
+/** Offset 0x0908 - Touch Host Controller Idle Ltr
+  Expose Idle Ltr for OS driver to set
+**/
+  UINT32                      ThcIdleLtr[2];
+
+/** Offset 0x0910 - Touch Host Controller Hid Over Spi ResetPad
+  Hid Over Spi ResetPad
+**/
+  UINT32                      ThcResetPad[2];
+
+/** Offset 0x0918 - Touch Host Controller Hid Over Spi ResetPad Trigger
+  Hid Over Spi Reset Pad Trigger 0x0:Low, 0x1:High
+**/
+  UINT32                      ThcResetPadTrigger[2];
+
+/** Offset 0x0920 - Touch Host Controller Hid Over Spi Connection Speed
+  Hid Over Spi Connection Speed - SPI Frequency
+**/
+  UINT32                      ThcHidSpiConnectionSpeed[2];
+
+/** Offset 0x0928 - Touch Host Controller Hid Over Spi Limit PacketSize
+  When set, limits SPI read & write packet size to 64B. Otherwise, THC uses Max Soc
+  packet size for SPI Read and Write 0x0- Max Soc Packet Size,  0x11 - 64 Bytes
+**/
+  UINT32                      ThcHidSpiLimitPacketSize[2];
+
+/** Offset 0x0930 - Touch Host Controller Hid Over Spi Limit PacketSize
+  Minimum amount of delay the THC/QUICKSPI driver must wait between end of write operation
+  and begin of read operation. This value shall be in 10us multiples 0x0: Disabled,
+  1-65535 (0xFFFF) - up to 655350 us
+**/
+  UINT32                      ThcPerformanceLimitation[2];
+
+/** Offset 0x0938 - Touch Host Controller Hid Over Spi Input Report Header Address
+  Hid Over Spi Input Report Header Address
+**/
+  UINT32                      ThcHidSpiInputReportHeaderAddress[2];
+
+/** Offset 0x0940 - Touch Host Controller Hid Over Spi Input Report Body Address
+  Hid Over Spi Input Report Body Address
+**/
+  UINT32                      ThcHidSpiInputReportBodyAddress[2];
+
+/** Offset 0x0948 - Touch Host Controller Hid Over Spi Output Report Address
+  Hid Over Spi Output Report Address
+**/
+  UINT32                      ThcHidSpiOutputReportAddress[2];
+
+/** Offset 0x0950 - Touch Host Controller Hid Over Spi Read Opcode
+  Hid Over Spi Read Opcode
+**/
+  UINT32                      ThcHidSpiReadOpcode[2];
+
+/** Offset 0x0958 - Touch Host Controller Hid Over Spi Write Opcode
+  Hid Over Spi Write Opcode
+**/
+  UINT32                      ThcHidSpiWriteOpcode[2];
+
+/** Offset 0x0960 - Touch Host Controller Hid Over Spi Flags
+  Hid Over Spi Flags 0x0:Single SPI Mode, 0x4000:Dual SPI Mode, 0x8000:Quad SPI Mode
+**/
+  UINT32                      ThcHidSpiFlags[2];
+
+/** Offset 0x0968 - Touch Host Controller Hid Over Spi Reset Sequencing Delay [ms]
+  Policy control for reset sequencing delay (ACPI _INI, _RST) default 300ms
+**/
+  UINT16                      ThcResetSequencingDelay[2];
 
 /** Offset 0x096C - PCIE RP Pcie Speed
   Determines each PCIE Port speed capability. 0: Auto; 1: Gen1; 2: Gen2; 3: Gen3 (see:
@@ -1641,9 +1929,707 @@ typedef struct {
 **/
   UINT8                       PcieEqOverrideDefault[29];
 
-/** Offset 0x0A54 - Reserved
+/** Offset 0x0A54 - PCIE RP choose EQ method
+  Choose PCIe EQ method
+  0: HardwareEq, 1: FixedEq
 **/
-  UINT8                       Reserved41[3767];
+  UINT8                       PcieGen3EqMethod[29];
+
+/** Offset 0x0A71 - PCIE RP choose EQ mode
+  Choose PCIe EQ mode
+  0: PresetEq, 1: CoefficientEq
+**/
+  UINT8                       PcieGen3EqMode[29];
+
+/** Offset 0x0A8E - PCIE RP EQ local transmitter override
+  Enable/Disable local transmitter override
+  $EN_DIS
+**/
+  UINT8                       PcieGen3EqLocalTxOverrideEn[29];
+
+/** Offset 0x0AAB - PCI RP number of valid list entries
+  Select number of presets or coefficients depending on the mode
+**/
+  UINT8                       PcieGen3EqPh3NoOfPresetOrCoeff[29];
+
+/** Offset 0x0AC8 - PCIE RP pre-cursor coefficient list
+  Provide a list of pre-cursor coefficients to be used during phase 3 EQ
+**/
+  UINT8                       PcieGen3EqPh3PreCursor0List[29];
+
+/** Offset 0x0AE5 - PCIE RP post-cursor coefficient list
+  Provide a list of post-cursor coefficients to be used during phase 3 EQ
+**/
+  UINT8                       PcieGen3EqPh3PostCursor0List[29];
+
+/** Offset 0x0B02 - PCIE RP pre-cursor coefficient list
+  Provide a list of pre-cursor coefficients to be used during phase 3 EQ
+**/
+  UINT8                       PcieGen3EqPh3PreCursor1List[29];
+
+/** Offset 0x0B1F - PCIE RP post-cursor coefficient list
+  Provide a list of post-cursor coefficients to be used during phase 3 EQ
+**/
+  UINT8                       PcieGen3EqPh3PostCursor1List[29];
+
+/** Offset 0x0B3C - PCIE RP pre-cursor coefficient list
+  Provide a list of pre-cursor coefficients to be used during phase 3 EQ
+**/
+  UINT8                       PcieGen3EqPh3PreCursor2List[29];
+
+/** Offset 0x0B59 - PCIE RP post-cursor coefficient list
+  Provide a list of post-cursor coefficients to be used during phase 3 EQ
+**/
+  UINT8                       PcieGen3EqPh3PostCursor2List[29];
+
+/** Offset 0x0B76 - PCIR RP pre-cursor coefficient list
+  Provide a list of pre-cursor coefficients to be used during phase 3 EQ
+**/
+  UINT8                       PcieGen3EqPh3PreCursor3List[29];
+
+/** Offset 0x0B93 - PCIE RP post-cursor coefficient list
+  Provide a list of post-cursor coefficients to be used during phase 3 EQ
+**/
+  UINT8                       PcieGen3EqPh3PostCursor3List[29];
+
+/** Offset 0x0BB0 - PCIE RP pre-cursor coefficient list
+  Provide a list of pre-cursor coefficients to be used during phase 3 EQ
+**/
+  UINT8                       PcieGen3EqPh3PreCursor4List[29];
+
+/** Offset 0x0BCD - PCIE RP post-cursor coefficient list
+  Provide a list of post-cursor coefficients to be used during phase 3 EQ
+**/
+  UINT8                       PcieGen3EqPh3PostCursor4List[29];
+
+/** Offset 0x0BEA - PCIE RP pre-cursor coefficient list
+  Provide a list of pre-cursor coefficients to be used during phase 3 EQ
+**/
+  UINT8                       PcieGen3EqPh3PreCursor5List[29];
+
+/** Offset 0x0C07 - PCIE RP post-cursor coefficient list
+  Provide a list of post-cursor coefficients to be used during phase 3 EQ
+**/
+  UINT8                       PcieGen3EqPh3PostCursor5List[29];
+
+/** Offset 0x0C24 - PCIE RP pre-cursor coefficient list
+  Provide a list of pre-cursor coefficients to be used during phase 3 EQ
+**/
+  UINT8                       PcieGen3EqPh3PreCursor6List[29];
+
+/** Offset 0x0C41 - PCIe post-cursor coefficient list
+  Provide a list of post-cursor coefficients to be used during phase 3 EQ
+**/
+  UINT8                       PcieGen3EqPh3PostCursor6List[29];
+
+/** Offset 0x0C5E - PCIE RP pre-cursor coefficient list
+  Provide a list of pre-cursor coefficients to be used during phase 3 EQ
+**/
+  UINT8                       PcieGen3EqPh3PreCursor7List[29];
+
+/** Offset 0x0C7B - PCIE RP post-cursor coefficient list
+  Provide a list of post-cursor coefficients to be used during phase 3 EQ
+**/
+  UINT8                       PcieGen3EqPh3PostCursor7List[29];
+
+/** Offset 0x0C98 - PCIE RP pre-cursor coefficient list
+  Provide a list of pre-cursor coefficients to be used during phase 3 EQ
+**/
+  UINT8                       PcieGen3EqPh3PreCursor8List[29];
+
+/** Offset 0x0CB5 - PCIE RP post-cursor coefficient list
+  Provide a list of post-cursor coefficients to be used during phase 3 EQ
+**/
+  UINT8                       PcieGen3EqPh3PostCursor8List[29];
+
+/** Offset 0x0CD2 - PCIE RP pre-cursor coefficient list
+  Provide a list of pre-cursor coefficients to be used during phase 3 EQ
+**/
+  UINT8                       PcieGen3EqPh3PreCursor9List[29];
+
+/** Offset 0x0CEF - PCIE RP post-cursor coefficient list
+  Provide a list of post-cursor coefficients to be used during phase 3 EQ
+**/
+  UINT8                       PcieGen3EqPh3PostCursor9List[29];
+
+/** Offset 0x0D0C - PCIE RP preset list
+  Provide a list of presets to be used during phase 3 EQ
+**/
+  UINT8                       PcieGen3EqPh3Preset0List[29];
+
+/** Offset 0x0D29 - PCIe preset list
+  Provide a list of presets to be used during phase 3 EQ
+**/
+  UINT8                       PcieGen3EqPh3Preset1List[29];
+
+/** Offset 0x0D46 - PCIE RP preset list
+  Provide a list of presets to be used during phase 3 EQ
+**/
+  UINT8                       PcieGen3EqPh3Preset2List[29];
+
+/** Offset 0x0D63 - PCIE RP preset list
+  Provide a list of presets to be used during phase 3 EQ
+**/
+  UINT8                       PcieGen3EqPh3Preset3List[29];
+
+/** Offset 0x0D80 - PCIE RP preset list
+  Provide a list of presets to be used during phase 3 EQ
+**/
+  UINT8                       PcieGen3EqPh3Preset4List[29];
+
+/** Offset 0x0D9D - PCIE RP preset list
+  Provide a list of presets to be used during phase 3 EQ
+**/
+  UINT8                       PcieGen3EqPh3Preset5List[29];
+
+/** Offset 0x0DBA - PCIE RP preset list
+  Provide a list of presets to be used during phase 3 EQ
+**/
+  UINT8                       PcieGen3EqPh3Preset6List[29];
+
+/** Offset 0x0DD7 - PCIE RP preset list
+  Provide a list of presets to be used during phase 3 EQ
+**/
+  UINT8                       PcieGen3EqPh3Preset7List[29];
+
+/** Offset 0x0DF4 - PCIE RP preset list
+  Provide a list of presets to be used during phase 3 EQ
+**/
+  UINT8                       PcieGen3EqPh3Preset8List[29];
+
+/** Offset 0x0E11 - PCIE RP preset list
+  Provide a list of presets to be used during phase 3 EQ
+**/
+  UINT8                       PcieGen3EqPh3Preset9List[29];
+
+/** Offset 0x0E2E - PCIE RP preset list
+  Provide a list of presets to be used during phase 3 EQ
+**/
+  UINT8                       PcieGen3EqPh3Preset10List[29];
+
+/** Offset 0x0E4B - PCIe EQ phase 1 downstream transmitter port preset
+  Allows to select the downstream port preset value that will be used during phase
+  1 of equalization
+**/
+  UINT8                       PcieGen3EqPh1DpTxPreset[29];
+
+/** Offset 0x0E68 - PCIE RP EQ phase 1 upstream tranmitter port preset
+  Allows to select the upstream port preset value that will be used during phase 1
+  of equalization
+**/
+  UINT8                       PcieGen3EqPh1UpTxPreset[29];
+
+/** Offset 0x0E85 - PCIE RP EQ phase 2 local transmitter override preset
+  Allows to select the value of the preset used during phase 2 local transmitter override
+**/
+  UINT8                       PcieGen3EqPh2LocalTxOverridePreset[29];
+
+/** Offset 0x0EA2 - PCIE RP choose EQ method
+  Choose PCIe EQ method
+  0: HardwareEq, 1: FixedEq
+**/
+  UINT8                       PcieGen4EqMethod[29];
+
+/** Offset 0x0EBF - PCIE RP choose EQ mode
+  Choose PCIe EQ mode
+  0: PresetEq, 1: CoefficientEq
+**/
+  UINT8                       PcieGen4EqMode[29];
+
+/** Offset 0x0EDC - PCIE RP EQ local transmitter override
+  Enable/Disable local transmitter override
+  $EN_DIS
+**/
+  UINT8                       PcieGen4EqLocalTxOverrideEn[29];
+
+/** Offset 0x0EF9 - PCI RP number of valid list entries
+  Select number of presets or coefficients depending on the mode
+**/
+  UINT8                       PcieGen4EqPh3NoOfPresetOrCoeff[29];
+
+/** Offset 0x0F16 - PCIE RP pre-cursor coefficient list
+  Provide a list of pre-cursor coefficients to be used during phase 3 EQ
+**/
+  UINT8                       PcieGen4EqPh3PreCursor0List[29];
+
+/** Offset 0x0F33 - PCIE RP post-cursor coefficient list
+  Provide a list of post-cursor coefficients to be used during phase 3 EQ
+**/
+  UINT8                       PcieGen4EqPh3PostCursor0List[29];
+
+/** Offset 0x0F50 - PCIE RP pre-cursor coefficient list
+  Provide a list of pre-cursor coefficients to be used during phase 3 EQ
+**/
+  UINT8                       PcieGen4EqPh3PreCursor1List[29];
+
+/** Offset 0x0F6D - PCIE RP post-cursor coefficient list
+  Provide a list of post-cursor coefficients to be used during phase 3 EQ
+**/
+  UINT8                       PcieGen4EqPh3PostCursor1List[29];
+
+/** Offset 0x0F8A - PCIE RP pre-cursor coefficient list
+  Provide a list of pre-cursor coefficients to be used during phase 3 EQ
+**/
+  UINT8                       PcieGen4EqPh3PreCursor2List[29];
+
+/** Offset 0x0FA7 - PCIE RP post-cursor coefficient list
+  Provide a list of post-cursor coefficients to be used during phase 3 EQ
+**/
+  UINT8                       PcieGen4EqPh3PostCursor2List[29];
+
+/** Offset 0x0FC4 - PCIR RP pre-cursor coefficient list
+  Provide a list of pre-cursor coefficients to be used during phase 3 EQ
+**/
+  UINT8                       PcieGen4EqPh3PreCursor3List[29];
+
+/** Offset 0x0FE1 - PCIE RP post-cursor coefficient list
+  Provide a list of post-cursor coefficients to be used during phase 3 EQ
+**/
+  UINT8                       PcieGen4EqPh3PostCursor3List[29];
+
+/** Offset 0x0FFE - PCIE RP pre-cursor coefficient list
+  Provide a list of pre-cursor coefficients to be used during phase 3 EQ
+**/
+  UINT8                       PcieGen4EqPh3PreCursor4List[29];
+
+/** Offset 0x101B - PCIE RP post-cursor coefficient list
+  Provide a list of post-cursor coefficients to be used during phase 3 EQ
+**/
+  UINT8                       PcieGen4EqPh3PostCursor4List[29];
+
+/** Offset 0x1038 - PCIE RP pre-cursor coefficient list
+  Provide a list of pre-cursor coefficients to be used during phase 3 EQ
+**/
+  UINT8                       PcieGen4EqPh3PreCursor5List[29];
+
+/** Offset 0x1055 - PCIE RP post-cursor coefficient list
+  Provide a list of post-cursor coefficients to be used during phase 3 EQ
+**/
+  UINT8                       PcieGen4EqPh3PostCursor5List[29];
+
+/** Offset 0x1072 - PCIE RP pre-cursor coefficient list
+  Provide a list of pre-cursor coefficients to be used during phase 3 EQ
+**/
+  UINT8                       PcieGen4EqPh3PreCursor6List[29];
+
+/** Offset 0x108F - PCIe post-cursor coefficient list
+  Provide a list of post-cursor coefficients to be used during phase 3 EQ
+**/
+  UINT8                       PcieGen4EqPh3PostCursor6List[29];
+
+/** Offset 0x10AC - PCIE RP pre-cursor coefficient list
+  Provide a list of pre-cursor coefficients to be used during phase 3 EQ
+**/
+  UINT8                       PcieGen4EqPh3PreCursor7List[29];
+
+/** Offset 0x10C9 - PCIE RP post-cursor coefficient list
+  Provide a list of post-cursor coefficients to be used during phase 3 EQ
+**/
+  UINT8                       PcieGen4EqPh3PostCursor7List[29];
+
+/** Offset 0x10E6 - PCIE RP pre-cursor coefficient list
+  Provide a list of pre-cursor coefficients to be used during phase 3 EQ
+**/
+  UINT8                       PcieGen4EqPh3PreCursor8List[29];
+
+/** Offset 0x1103 - PCIE RP post-cursor coefficient list
+  Provide a list of post-cursor coefficients to be used during phase 3 EQ
+**/
+  UINT8                       PcieGen4EqPh3PostCursor8List[29];
+
+/** Offset 0x1120 - PCIE RP pre-cursor coefficient list
+  Provide a list of pre-cursor coefficients to be used during phase 3 EQ
+**/
+  UINT8                       PcieGen4EqPh3PreCursor9List[29];
+
+/** Offset 0x113D - PCIE RP post-cursor coefficient list
+  Provide a list of post-cursor coefficients to be used during phase 3 EQ
+**/
+  UINT8                       PcieGen4EqPh3PostCursor9List[29];
+
+/** Offset 0x115A - PCIE RP preset list
+  Provide a list of presets to be used during phase 3 EQ
+**/
+  UINT8                       PcieGen4EqPh3Preset0List[29];
+
+/** Offset 0x1177 - PCIe preset list
+  Provide a list of presets to be used during phase 3 EQ
+**/
+  UINT8                       PcieGen4EqPh3Preset1List[29];
+
+/** Offset 0x1194 - PCIE RP preset list
+  Provide a list of presets to be used during phase 3 EQ
+**/
+  UINT8                       PcieGen4EqPh3Preset2List[29];
+
+/** Offset 0x11B1 - PCIE RP preset list
+  Provide a list of presets to be used during phase 3 EQ
+**/
+  UINT8                       PcieGen4EqPh3Preset3List[29];
+
+/** Offset 0x11CE - PCIE RP preset list
+  Provide a list of presets to be used during phase 3 EQ
+**/
+  UINT8                       PcieGen4EqPh3Preset4List[29];
+
+/** Offset 0x11EB - PCIE RP preset list
+  Provide a list of presets to be used during phase 3 EQ
+**/
+  UINT8                       PcieGen4EqPh3Preset5List[29];
+
+/** Offset 0x1208 - PCIE RP preset list
+  Provide a list of presets to be used during phase 3 EQ
+**/
+  UINT8                       PcieGen4EqPh3Preset6List[29];
+
+/** Offset 0x1225 - PCIE RP preset list
+  Provide a list of presets to be used during phase 3 EQ
+**/
+  UINT8                       PcieGen4EqPh3Preset7List[29];
+
+/** Offset 0x1242 - PCIE RP preset list
+  Provide a list of presets to be used during phase 3 EQ
+**/
+  UINT8                       PcieGen4EqPh3Preset8List[29];
+
+/** Offset 0x125F - PCIE RP preset list
+  Provide a list of presets to be used during phase 3 EQ
+**/
+  UINT8                       PcieGen4EqPh3Preset9List[29];
+
+/** Offset 0x127C - PCIE RP preset list
+  Provide a list of presets to be used during phase 3 EQ
+**/
+  UINT8                       PcieGen4EqPh3Preset10List[29];
+
+/** Offset 0x1299 - PCIe EQ phase 1 downstream transmitter port preset
+  Allows to select the downstream port preset value that will be used during phase
+  1 of equalization
+**/
+  UINT8                       PcieGen4EqPh1DpTxPreset[29];
+
+/** Offset 0x12B6 - PCIE RP EQ phase 1 upstream tranmitter port preset
+  Allows to select the upstream port preset value that will be used during phase 1
+  of equalization
+**/
+  UINT8                       PcieGen4EqPh1UpTxPreset[29];
+
+/** Offset 0x12D3 - PCIE RP EQ phase 2 local transmitter override preset
+  Allows to select the value of the preset used during phase 2 local transmitter override
+**/
+  UINT8                       PcieGen4EqPh2LocalTxOverridePreset[29];
+
+/** Offset 0x12F0 - PCIE RP choose EQ method
+  Choose PCIe EQ method
+  0: HardwareEq, 1: FixedEq
+**/
+  UINT8                       PcieGen5EqMethod[29];
+
+/** Offset 0x130D - PCIE RP choose EQ mode
+  Choose PCIe EQ mode
+  0: PresetEq, 1: CoefficientEq
+**/
+  UINT8                       PcieGen5EqMode[29];
+
+/** Offset 0x132A - PCIE RP EQ local transmitter override
+  Enable/Disable local transmitter override
+  $EN_DIS
+**/
+  UINT8                       PcieGen5EqLocalTxOverrideEn[29];
+
+/** Offset 0x1347 - PCI RP number of valid list entries
+  Select number of presets or coefficients depending on the mode
+**/
+  UINT8                       PcieGen5EqPh3NoOfPresetOrCoeff[29];
+
+/** Offset 0x1364 - PCIE RP pre-cursor coefficient list
+  Provide a list of pre-cursor coefficients to be used during phase 3 EQ
+**/
+  UINT8                       PcieGen5EqPh3PreCursor0List[29];
+
+/** Offset 0x1381 - PCIE RP post-cursor coefficient list
+  Provide a list of post-cursor coefficients to be used during phase 3 EQ
+**/
+  UINT8                       PcieGen5EqPh3PostCursor0List[29];
+
+/** Offset 0x139E - PCIE RP pre-cursor coefficient list
+  Provide a list of pre-cursor coefficients to be used during phase 3 EQ
+**/
+  UINT8                       PcieGen5EqPh3PreCursor1List[29];
+
+/** Offset 0x13BB - PCIE RP post-cursor coefficient list
+  Provide a list of post-cursor coefficients to be used during phase 3 EQ
+**/
+  UINT8                       PcieGen5EqPh3PostCursor1List[29];
+
+/** Offset 0x13D8 - PCIE RP pre-cursor coefficient list
+  Provide a list of pre-cursor coefficients to be used during phase 3 EQ
+**/
+  UINT8                       PcieGen5EqPh3PreCursor2List[29];
+
+/** Offset 0x13F5 - PCIE RP post-cursor coefficient list
+  Provide a list of post-cursor coefficients to be used during phase 3 EQ
+**/
+  UINT8                       PcieGen5EqPh3PostCursor2List[29];
+
+/** Offset 0x1412 - PCIR RP pre-cursor coefficient list
+  Provide a list of pre-cursor coefficients to be used during phase 3 EQ
+**/
+  UINT8                       PcieGen5EqPh3PreCursor3List[29];
+
+/** Offset 0x142F - PCIE RP post-cursor coefficient list
+  Provide a list of post-cursor coefficients to be used during phase 3 EQ
+**/
+  UINT8                       PcieGen5EqPh3PostCursor3List[29];
+
+/** Offset 0x144C - PCIE RP pre-cursor coefficient list
+  Provide a list of pre-cursor coefficients to be used during phase 3 EQ
+**/
+  UINT8                       PcieGen5EqPh3PreCursor4List[29];
+
+/** Offset 0x1469 - PCIE RP post-cursor coefficient list
+  Provide a list of post-cursor coefficients to be used during phase 3 EQ
+**/
+  UINT8                       PcieGen5EqPh3PostCursor4List[29];
+
+/** Offset 0x1486 - PCIE RP pre-cursor coefficient list
+  Provide a list of pre-cursor coefficients to be used during phase 3 EQ
+**/
+  UINT8                       PcieGen5EqPh3PreCursor5List[29];
+
+/** Offset 0x14A3 - PCIE RP post-cursor coefficient list
+  Provide a list of post-cursor coefficients to be used during phase 3 EQ
+**/
+  UINT8                       PcieGen5EqPh3PostCursor5List[29];
+
+/** Offset 0x14C0 - PCIE RP pre-cursor coefficient list
+  Provide a list of pre-cursor coefficients to be used during phase 3 EQ
+**/
+  UINT8                       PcieGen5EqPh3PreCursor6List[29];
+
+/** Offset 0x14DD - PCIe post-cursor coefficient list
+  Provide a list of post-cursor coefficients to be used during phase 3 EQ
+**/
+  UINT8                       PcieGen5EqPh3PostCursor6List[29];
+
+/** Offset 0x14FA - PCIE RP pre-cursor coefficient list
+  Provide a list of pre-cursor coefficients to be used during phase 3 EQ
+**/
+  UINT8                       PcieGen5EqPh3PreCursor7List[29];
+
+/** Offset 0x1517 - PCIE RP post-cursor coefficient list
+  Provide a list of post-cursor coefficients to be used during phase 3 EQ
+**/
+  UINT8                       PcieGen5EqPh3PostCursor7List[29];
+
+/** Offset 0x1534 - PCIE RP pre-cursor coefficient list
+  Provide a list of pre-cursor coefficients to be used during phase 3 EQ
+**/
+  UINT8                       PcieGen5EqPh3PreCursor8List[29];
+
+/** Offset 0x1551 - PCIE RP post-cursor coefficient list
+  Provide a list of post-cursor coefficients to be used during phase 3 EQ
+**/
+  UINT8                       PcieGen5EqPh3PostCursor8List[29];
+
+/** Offset 0x156E - PCIE RP pre-cursor coefficient list
+  Provide a list of pre-cursor coefficients to be used during phase 3 EQ
+**/
+  UINT8                       PcieGen5EqPh3PreCursor9List[29];
+
+/** Offset 0x158B - PCIE RP post-cursor coefficient list
+  Provide a list of post-cursor coefficients to be used during phase 3 EQ
+**/
+  UINT8                       PcieGen5EqPh3PostCursor9List[29];
+
+/** Offset 0x15A8 - PCIE RP preset list
+  Provide a list of presets to be used during phase 3 EQ
+**/
+  UINT8                       PcieGen5EqPh3Preset0List[29];
+
+/** Offset 0x15C5 - PCIe preset list
+  Provide a list of presets to be used during phase 3 EQ
+**/
+  UINT8                       PcieGen5EqPh3Preset1List[29];
+
+/** Offset 0x15E2 - PCIE RP preset list
+  Provide a list of presets to be used during phase 3 EQ
+**/
+  UINT8                       PcieGen5EqPh3Preset2List[29];
+
+/** Offset 0x15FF - PCIE RP preset list
+  Provide a list of presets to be used during phase 3 EQ
+**/
+  UINT8                       PcieGen5EqPh3Preset3List[29];
+
+/** Offset 0x161C - PCIE RP preset list
+  Provide a list of presets to be used during phase 3 EQ
+**/
+  UINT8                       PcieGen5EqPh3Preset4List[29];
+
+/** Offset 0x1639 - PCIE RP preset list
+  Provide a list of presets to be used during phase 3 EQ
+**/
+  UINT8                       PcieGen5EqPh3Preset5List[29];
+
+/** Offset 0x1656 - PCIE RP preset list
+  Provide a list of presets to be used during phase 3 EQ
+**/
+  UINT8                       PcieGen5EqPh3Preset6List[29];
+
+/** Offset 0x1673 - PCIE RP preset list
+  Provide a list of presets to be used during phase 3 EQ
+**/
+  UINT8                       PcieGen5EqPh3Preset7List[29];
+
+/** Offset 0x1690 - PCIE RP preset list
+  Provide a list of presets to be used during phase 3 EQ
+**/
+  UINT8                       PcieGen5EqPh3Preset8List[29];
+
+/** Offset 0x16AD - PCIE RP preset list
+  Provide a list of presets to be used during phase 3 EQ
+**/
+  UINT8                       PcieGen5EqPh3Preset9List[29];
+
+/** Offset 0x16CA - PCIE RP preset list
+  Provide a list of presets to be used during phase 3 EQ
+**/
+  UINT8                       PcieGen5EqPh3Preset10List[29];
+
+/** Offset 0x16E7 - PCIe EQ phase 1 downstream transmitter port preset
+  Allows to select the downstream port preset value that will be used during phase
+  1 of equalization
+**/
+  UINT8                       PcieGen5EqPh1DpTxPreset[29];
+
+/** Offset 0x1704 - PCIE RP EQ phase 1 upstream tranmitter port preset
+  Allows to select the upstream port preset value that will be used during phase 1
+  of equalization
+**/
+  UINT8                       PcieGen5EqPh1UpTxPreset[29];
+
+/** Offset 0x1721 - PCIE RP EQ phase 2 local transmitter override preset
+  Allows to select the value of the preset used during phase 2 local transmitter override
+**/
+  UINT8                       PcieGen5EqPh2LocalTxOverridePreset[29];
+
+/** Offset 0x173E - Phase3 RP Gen3 EQ enable
+  Phase3 Gen3 EQ enable. Disabled(0x0)(Default): Disable phase 3, Enabled(0x1): Enable phase 3
+  0:Disable, 1:Enable, 2:Auto
+**/
+  UINT8                       PcieRpGen3EqPh3Bypass[29];
+
+/** Offset 0x175B - Phase3 RP Gen3 EQ enable
+  Phase3 Gen3 EQ enable. Disabled(0x0)(Default): Disable phase 3, Enabled(0x1): Enable phase 3
+  0:Disable, 1:Enable, 2:Auto
+**/
+  UINT8                       PcieRpGen4EqPh3Bypass[29];
+
+/** Offset 0x1778 - Phase3 RP Gen5 EQ enable
+  Phase3 Gen5 EQ enable. Disabled(0x0)(Default): Disable phase 3, Enabled(0x1): Enable phase 3
+  0:Disable, 1:Enable, 2:Auto
+**/
+  UINT8                       PcieRpGen5EqPh3Bypass[29];
+
+/** Offset 0x1795 - Phase2-3 RP Gen3 EQ enable
+  Phase2-3 Gen3 EQ enable. Disabled(0x0)(Default): Disable Phase2-3, Enabled(0x1):
+  Enable Phase2-3
+  0:Disable, 1:Enable, 2:Auto
+**/
+  UINT8                       PcieRpGen3EqPh23Bypass[29];
+
+/** Offset 0x17B2 - Phase2-3 RP Gen4 EQ enable
+  Phase2-3 Gen4 EQ enable. Disabled(0x0)(Default): Disable Phase2-3, Enabled(0x1):
+  Enable Phase2-3
+  0:Disable, 1:Enable, 2:Auto
+**/
+  UINT8                       PcieRpGen4EqPh23Bypass[29];
+
+/** Offset 0x17CF - Phase2-3 RP Gen5 EQ enable
+  Phase2-3 Gen5 EQ enable. Disabled(0x0)(Default): Disable Phase2-3, Enabled(0x1):
+  Enable Phase2-3
+  0:Disable, 1:Enable, 2:Auto
+**/
+  UINT8                       PcieRpGen5EqPh23Bypass[29];
+
+/** Offset 0x17EC - RP Gen3 EQ Phase enable
+  Gen3 EQ Phase enable. Disabled(0x0)(Default): Disable Eq Phase, Enabled(0x1): Enable Eq Phase
+  0:Disable, 1:Enable, 2:Auto
+**/
+  UINT8                       PcieRpGen3EqPhBypass[29];
+
+/** Offset 0x1809 - RP Gen4 EQ Phase enable
+  Gen4 EQ Phase enable. Disabled(0x0)(Default): Disable Eq Phase, Enabled(0x1): Enable Eq Phase
+  0:Disable, 1:Enable, 2:Auto
+**/
+  UINT8                       PcieRpGen4EqPhBypass[29];
+
+/** Offset 0x1826 - RP Gen5 EQ Phase enable
+  Gen5 EQ Phase enable. Disabled(0x0)(Default): Disable Eq Phase, Enabled(0x1): Enable Eq Phase
+  0:Disable, 1:Enable, 2:Auto
+**/
+  UINT8                       PcieRpGen5EqPhBypass[29];
+
+/** Offset 0x1843 - PCET Timer
+  Preset/Coefficient Evaluation Timeout Gen3 PCET Timer. See PCIE_GEN3_PCET. Default
+  is 0x0(2ms)
+**/
+  UINT8                       PcieGen3PcetTimer[29];
+
+/** Offset 0x1860 - Gen4 PCET Timer
+  Preset/Coefficient Evaluation Timeout - Gen4 PCET Timer. See PCIE_GEN4_PCET. Default
+  is 0x0(2ms)
+**/
+  UINT8                       PcieGen4PcetTimer[29];
+
+/** Offset 0x187D - Gen5 PCET Timer
+  Preset/Coefficient Evaluation Timeout - Gen5 PCET Timer. See PCIE_GEN5_PCET. Default
+  is 0x0(2ms)
+**/
+  UINT8                       PcieGen5PcetTimer[29];
+
+/** Offset 0x189A - TS Lock Timer for Gen3
+  Training Sequence Wait Latency For Presets/Coefficients Evaluation - Gen3 TS Lock
+  Timer. See PCIE_GEN3_TS_LOCK_TIMER. Default is 0x0
+**/
+  UINT8                       PcieGen3TsLockTimer[29];
+
+/** Offset 0x18B7 - PTS Lock Timer for Gen4
+  Training Sequence Wait Latency For Presets/Coefficients Evaluation - Gen4 TS Lock
+  Timer. See PCIE_GEN4_TS_LCOK_TIMER. Default is 0x0
+**/
+  UINT8                       PcieGen4TsLockTimer[29];
+
+/** Offset 0x18D4 - PTS Lock Timer for Gen5
+  Training Sequence Wait Latency For Presets/Coefficients Evaluation - Gen5 TS Lock
+  Timer. See PCIE_GEN5_TS_LCOK_TIMER. Default is 0x0
+**/
+  UINT8                       PcieGen5TsLockTimer[29];
+
+/** Offset 0x18F1 - PCIE Secure Register Lock
+  Describes whether Secure Register Lock is enaled or disabled. When it will be enbaled,
+  load PcieRpSetSecuredRegisterLock recipe. 0: Disable(Default); 1: Enable
+  $EN_DIS
+**/
+  UINT8                       PcieSetSecuredRegisterLock;
+
+/** Offset 0x18F2 - DG Wait
+  0(Default) = Disable, 1 = Enable
+  $EN_DIS
+**/
+  UINT8                       DGWait;
+
+/** Offset 0x18F3 - Enable/Disable ASPM Optionality Compliance
+  Enable/Disable ASPM Optionality Compliance.
+**/
+  UINT8                       PcieRpTestAspmOc[12];
+
+/** Offset 0x18FF - PCIe Configuration Dump
+  Enable/Disable ASPM Optionality Compliance.
+  0:Disable, 1:Enable
+**/
+  UINT8                       PcieCfgDump[12];
 
 /** Offset 0x190B - PCIE RP Enable Peer Memory Write
   This member describes whether Peer Memory Writes are enabled on the platform.
@@ -1664,9 +2650,11 @@ typedef struct {
 **/
   UINT8                       PcieRpFunctionSwap;
 
-/** Offset 0x1919 - Reserved
+/** Offset 0x1919 - PCIe Fia Programming
+  Load Fia configuration if enable. 0: Disable; 1: Enable(Default).
+  $EN_DIS
 **/
-  UINT8                       Reserved42;
+  UINT8                       PcieFiaProgramming;
 
 /** Offset 0x191A - PCH Pm PME_B0_S5_DIS
   When cleared (default), wake events from PME_B0_STS are allowed in S5 if PME_B0_EN = 1.
@@ -1697,9 +2685,30 @@ typedef struct {
 **/
   UINT8                       PchPmWoWlanEnable;
 
-/** Offset 0x191F - Reserved
+/** Offset 0x191F - PCH Pm WoW lan DeepSx Enable
+  Determine if WLAN wake from DeepSx, corresponds to the DSX_WLAN_PP_EN bit in the
+  PWRM_CFG3 register.
+  $EN_DIS
 **/
-  UINT8                       Reserved43[4];
+  UINT8                       PchPmWoWlanDeepSxEnable;
+
+/** Offset 0x1920 - PCH Pm Lan Wake From DeepSx
+  Determine if enable LAN to wake from deep Sx.
+  $EN_DIS
+**/
+  UINT8                       PchPmLanWakeFromDeepSx;
+
+/** Offset 0x1921 - PCH Pm Deep Sx Pol
+  Deep Sx Policy.
+  $EN_DIS
+**/
+  UINT8                       PchPmDeepSxPol;
+
+/** Offset 0x1922 - PCH Pm Disable Dsx Ac Present Pulldown
+  When Disable, PCH will internal pull down AC_PRESENT in deep SX and during G3 exit.
+  $EN_DIS
+**/
+  UINT8                       PchPmDisableDsxAcPresentPulldown;
 
 /** Offset 0x1923 - PCH Pm Slp S3 Min Assert
   SLP_S3 Minimum Assertion Width Policy. Default is PchSlpS350ms.
@@ -1833,9 +2842,15 @@ typedef struct {
 **/
   UINT8                       SataPortsDmVal[8];
 
-/** Offset 0x196C - Reserved
+/** Offset 0x196C - Pch Dmi Aspm Ctrl
+  ASPM configuration on the PCH side of the DMI/OPI Link. Default is <b>PchPcieAspmAutoConfig</b>
+  0:Disabled, 1:L0s, 2:L1, 3:L0sL1, 4:Auto
 **/
-  UINT8                       Reserved44[2];
+  UINT8                       PchDmiAspm;
+
+/** Offset 0x196D
+**/
+  UINT8                       Rsvd300[1];
 
 /** Offset 0x196E - Enable SATA Port DmVal
   DEVSLP Idle Timeout (DITO), Default is 625.
@@ -1875,9 +2890,13 @@ typedef struct {
 **/
   UINT8                       UfsEnable[2];
 
-/** Offset 0x1992 - Reserved
+/** Offset 0x1992 - UFS Inline Encryption enable/disable
+  Enable/Disable UFS Inline Encryption feature, One byte for each Controller - (1,0)
+  to enable Inline Encryption for controller 0 and (0,1) to enable Inline Encryption
+  for controller 1
+  $EN_DIS
 **/
-  UINT8                       Reserved45[2];
+  UINT8                       UfsInlineEncryption[2];
 
 /** Offset 0x1994 - IEH Mode
   Integrated Error Handler Mode, 0: Bypass, 1: Enable
@@ -1885,9 +2904,53 @@ typedef struct {
 **/
   UINT8                       IehMode;
 
-/** Offset 0x1995 - Reserved
+/** Offset 0x1995 - SOC Thermal Throttling Suggested Setting
+  Thermal Throttling Suggested Setting. When it is enabled, customized throttle levels
+  are ignored but with native settings.
+  $EN_DIS
 **/
-  UINT8                       Reserved46[11];
+  UINT8                       SocTTSuggestedSetting;
+
+/** Offset 0x1996 - SOC Thermal Throttling Custimized T0Level Value
+  Custimized T0Level value.
+**/
+  UINT16                      SocT0Level;
+
+/** Offset 0x1998 - SOC Thermal Throttling Custimized T1Level Value
+  Custimized T1Level value.
+**/
+  UINT16                      SocT1Level;
+
+/** Offset 0x199A - SOC Thermal Throttling Custimized T2Level Value
+  Custimized T2Level value.
+**/
+  UINT16                      SocT2Level;
+
+/** Offset 0x199C - Enable SOC Thermal Throttle
+  Enable thermal throttle function.
+  $EN_DIS
+**/
+  UINT8                       SocTTEnable;
+
+/** Offset 0x199D - SOC PMSync State 13
+  When set to 1 and the programmed GPIO pin is a 1, then PMSync state 13 will force
+  at least T2 state.
+  $EN_DIS
+**/
+  UINT8                       SocTTState13Enable;
+
+/** Offset 0x199E - SOC Thermal Throttle Lock
+  Thermal Throttle Lock.
+  $EN_DIS
+**/
+  UINT8                       SocTTLock;
+
+/** Offset 0x199F - PCH Thermal Throttling Suggested Setting
+  Thermal Throttling Suggested Setting. When it is enabled, customized throttle levels
+  are ignored but with native settings.
+  $EN_DIS
+**/
+  UINT8                       PchTTSuggestedSetting;
 
 /** Offset 0x19A0 - PCH Thermal Throttling Custimized T0Level Value
   Custimized T0Level value.
@@ -1923,9 +2986,39 @@ typedef struct {
 **/
   UINT8                       PchTTLock;
 
-/** Offset 0x19A9 - Reserved
+/** Offset 0x19A9 - IOE Thermal Throttling Suggested Setting
+  IOE Thermal Throttling Suggested Setting. When it is enabled, customized throttle
+  levels are ignored but with native settings.
+  $EN_DIS
 **/
-  UINT8                       Reserved47[9];
+  UINT8                       IoeTTSuggestedSetting;
+
+/** Offset 0x19AA - IOE Thermal Throttling Custimized T0Level Value
+  Custimized IOE T0Level value.
+**/
+  UINT16                      IoeT0Level;
+
+/** Offset 0x19AC - IOE Thermal Throttling Custimized T1Level Value
+  Custimized IOE T1Level value.
+**/
+  UINT16                      IoeT1Level;
+
+/** Offset 0x19AE - IOE Thermal Throttling Custimized T2Level Value
+  Custimized IOE T2Level value.
+**/
+  UINT16                      IoeT2Level;
+
+/** Offset 0x19B0 - Enable IOE Thermal Throttle
+  Enable thermal throttle function.
+  $EN_DIS
+**/
+  UINT8                       IoeTTEnable;
+
+/** Offset 0x19B1 - IOE Thermal Throttle Lock
+  Thermal Throttle Lock.
+  $EN_DIS
+**/
+  UINT8                       IoeTTLock;
 
 /** Offset 0x19B2 - DMI Thermal Sensor Autonomous Width Enable
   DMI Thermal Sensor Autonomous Width Enable.
@@ -2031,9 +3124,9 @@ typedef struct {
 **/
   UINT8                       SataThermalSuggestedSetting;
 
-/** Offset 0x19C5 - Reserved
+/** Offset 0x19C5
 **/
-  UINT8                       Reserved48;
+  UINT8                       Rsvd310;
 
 /** Offset 0x19C6 - Thermal Device Temperature
   Decides the temperature.
@@ -2056,9 +3149,9 @@ typedef struct {
 **/
   UINT8                       PchUsbLtrOverrideEnable;
 
-/** Offset 0x19E3 - Reserved
+/** Offset 0x19E3
 **/
-  UINT8                       Reserved49;
+  UINT8                       Rsvd320[1];
 
 /** Offset 0x19E4 - xHCI High Idle Time LTR override
   Value used for overriding LTR recommendation for xHCI High Idle Time LTR setting
@@ -2099,9 +3192,9 @@ typedef struct {
 **/
   UINT8                       EnableTcoTimer;
 
-/** Offset 0x19F3 - Reserved
+/** Offset 0x19F3
 **/
-  UINT8                       Reserved50[5];
+  UINT8                       Rsvd330[5];
 
 /** Offset 0x19F8 - BgpdtHash[4]
   BgpdtHash values
@@ -2113,9 +3206,9 @@ typedef struct {
 **/
   UINT32                      BiosGuardAttr;
 
-/** Offset 0x1A1C - Reserved
+/** Offset 0x1A1C
 **/
-  UINT8                       Reserved51[4];
+  UINT8                       Rsvd340[4];
 
 /** Offset 0x1A20 - BiosGuardModulePtr
   BiosGuardModulePtr default values
@@ -2139,9 +3232,22 @@ typedef struct {
 **/
   UINT8                       EcCmdLock;
 
-/** Offset 0x1A32 - Reserved
+/** Offset 0x1A32
 **/
-  UINT8                       Reserved52[22];
+  UINT8                       Rsvd350[6];
+
+/** Offset 0x1A38 - EcProvisionEav
+  EcProvisionEav function pointer. \n
+  @code typedef EFI_STATUS (EFIAPI *EC_PROVISION_EAV) (IN UINT32 Eav, OUT UINT8
+  *ReturnValue); @endcode
+**/
+  UINT64                      EcProvisionEav;
+
+/** Offset 0x1A40 - EcBiosGuardCmdLock
+  EcBiosGuardCmdLock function pointer. \n
+  @code typedef EFI_STATUS (EFIAPI *EC_CMD_LOCK) (OUT UINT8 *ReturnValue); @endcode
+**/
+  UINT64                      EcBiosGuardCmdLock;
 
 /** Offset 0x1A48 - Skip Ssid Programming.
   When set to TRUE, silicon code will not do any SSID programming and platform code
@@ -2150,9 +3256,9 @@ typedef struct {
 **/
   UINT8                       SiSkipSsidProgramming;
 
-/** Offset 0x1A49 - Reserved
+/** Offset 0x1A49
 **/
-  UINT8                       Reserved53;
+  UINT8                       Rsvd360;
 
 /** Offset 0x1A4A - Change Default SVID
   Change the default SVID used in FSP to programming internal devices. This is only
@@ -2166,9 +3272,9 @@ typedef struct {
 **/
   UINT16                      SiCustomizedSsid;
 
-/** Offset 0x1A4E - Reserved
+/** Offset 0x1A4E
 **/
-  UINT8                       Reserved54[2];
+  UINT8                       Rsvd370[2];
 
 /** Offset 0x1A50 - SVID SDID table Poniter.
   The address of the table of SVID SDID to customize each SVID SDID entry. This is
@@ -2240,9 +3346,77 @@ typedef struct {
 **/
   UINT8                       PchPmLatchEventsC10Exit;
 
-/** Offset 0x1A6E - Reserved
+/** Offset 0x1A6E - PMC ADR enable
+  Enable/disable asynchronous DRAM refresh
+  $EN_DIS
 **/
-  UINT8                       Reserved55[127];
+  UINT8                       PmcAdrEn;
+
+/** Offset 0x1A6F - PMC ADR timer configuration enable
+  Enable/disable ADR timer configuration
+  $EN_DIS
+**/
+  UINT8                       PmcAdrTimerEn;
+
+/** Offset 0x1A70 - PMC ADR phase 1 timer value
+  Enable/disable ADR timer configuration
+**/
+  UINT8                       PmcAdrTimer1Val;
+
+/** Offset 0x1A71 - PMC ADR phase 1 timer multiplier value
+  Specify the multiplier value for phase 1 ADR timer
+**/
+  UINT8                       PmcAdrMultiplier1Val;
+
+/** Offset 0x1A72 - PMC ADR host reset partition enable
+  Specify whether PMC should set ADR_RST_STS bit after receiving Reset_Warn_Ack DMI message
+  $EN_DIS
+**/
+  UINT8                       PmcAdrHostPartitionReset;
+
+/** Offset 0x1A73 - PMC ADR source select override enable
+  Tells the FSP to update the source select with platform value
+  $EN_DIS
+**/
+  UINT8                       PmcAdrSrcOverride;
+
+/** Offset 0x1A74 - PMC ADR source selection
+  Specify which sources should cause ADR flow
+**/
+  UINT32                      PmcAdrSrcSel;
+
+/** Offset 0x1A78 - PMC WDT enable
+  Enable/disable PMC WDT configuration
+  $EN_DIS
+**/
+  UINT8                       PmcWdtTimerEn;
+
+/** Offset 0x1A79 - PCIe RootPort Clock Gating
+  Describes whether the PCI Express Clock Gating for each root port is enabled by
+  platform modules. 0: Disable; 1: Enable(Default).
+  $EN_DIS
+**/
+  UINT8                       PcieClockGating[29];
+
+/** Offset 0x1A96 - PCIe RootPort Power Gating
+  Describes whether the PCI Express Power Gating for each root port is enabled by
+  platform modules. 0: Disable; 1: Enable(Default).
+  $EN_DIS
+**/
+  UINT8                       PciePowerGating[29];
+
+/** Offset 0x1AB3 - FOMS Control Policy
+  Choose the Foms Control Policy, <b>Default = 0 </b>
+  0: Auto, 1: Gen3 Foms, 2: Gen4 Foms, 3: Gen3 and Gen4 Foms
+**/
+  UINT8                       PcieFomsCp[29];
+
+/** Offset 0x1AD0 - PCIe GPIO Assertion in Link Down
+  Describes whether the PCIe GPIO Assertion in Link Down programming is enabled for
+  each root portby platform modules. 0: Disable; 1: Enable(Default).
+  $EN_DIS
+**/
+  UINT8                       LinkDownGpios[29];
 
 /** Offset 0x1AED - Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 3
   Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 3, Each
@@ -2305,9 +3479,11 @@ typedef struct {
 **/
   UINT8                       RenderStandby;
 
-/** Offset 0x1B3F - Reserved
+/** Offset 0x1B3F - Enable/Disable GT Configuration
+  Enable(Default): Configure GT for use, Disable: Skip GT Configuration
+  $EN_DIS
 **/
-  UINT8                       Reserved56;
+  UINT8                       ConfigureGT;
 
 /** Offset 0x1B40 - GT Frequency Limit
   0xFF: Auto(Default), 2: 100 Mhz, 3: 150 Mhz, 4: 200 Mhz, 5: 250 Mhz, 6: 300 Mhz,
@@ -2329,9 +3505,17 @@ typedef struct {
 **/
   UINT8                       DisableTurboGt;
 
-/** Offset 0x1B42 - Reserved
+/** Offset 0x1B42 - Enable RC1p GT frequency request to PMA (provided all other conditions are met)
+  0(Default)=Disable, 1=Enable
+  $EN_DIS
 **/
-  UINT8                       Reserved57[2];
+  UINT8                       RC1pGtFreqEnable;
+
+/** Offset 0x1B43 - Enable RC1p Media frequency request to PMA (provided all other conditions are met)
+  0(Default)=Disable, 1=Enable
+  $EN_DIS
+**/
+  UINT8                       RC1pMediaFreqEnable;
 
 /** Offset 0x1B44 - Enable TSN Multi-VC
   Enable/disable Multi Virtual Channels(VC) in TSN.
@@ -2339,9 +3523,15 @@ typedef struct {
 **/
   UINT8                       PchTsnMultiVcEnable;
 
-/** Offset 0x1B45 - Reserved
+/** Offset 0x1B45 - PMC Limit Powergating
+  Enable/disable Limit PSF powergating to C3 and deeper states
+  $EN_DIS
 **/
-  UINT8                       Reserved58[11];
+  UINT8                       PmcLimitC3AndDeeperWA;
+
+/** Offset 0x1B46
+**/
+  UINT8                       Rsvd380[10];
 
 /** Offset 0x1B50 - LogoPixelHeight Address
   Address of LogoPixelHeight
@@ -2353,18 +3543,46 @@ typedef struct {
 **/
   UINT32                      LogoPixelWidth;
 
-/** Offset 0x1B58 - Reserved
+/** Offset 0x1B58 - Enable/Disable Media Configuration
+  Enable(Default): Configure Media for use, Disable: Skip Media Configuration
+  $EN_DIS
 **/
-  UINT8                       Reserved59;
+  UINT8                       ConfigureMedia;
 
 /** Offset 0x1B59 - ITbt Usb4CmMode value
   ITbt Usb4CmMode value. 0:Firmware CM, 1:Software CM
 **/
   UINT8                       Usb4CmMode;
 
-/** Offset 0x1B5A - Reserved
+/** Offset 0x1B5A
 **/
-  UINT8                       Reserved60[75];
+  UINT8                       Rsvd390[2];
+
+/** Offset 0x1B5C - HorizontalResolution for PEI Logo
+  HorizontalResolution from PEIm Gfx for PEI Logo
+**/
+  UINT32                      HorizontalResolution;
+
+/** Offset 0x1B60 - VerticalResolution for PEI Logo
+  VerticalResolution from PEIm Gfx for PEI Logo
+**/
+  UINT32                      VerticalResolution;
+
+/** Offset 0x1B64 - Enable/Disable IGFX Media Standby
+  Enable(Default): Enable IGFX Media Standby, Disable: Disable IGFX MediaStandby
+  $EN_DIS
+**/
+  UINT8                       MediaStandby;
+
+/** Offset 0x1B65 - SaPostMemTestRsvd
+  Reserved for SA Post-Mem Test
+  $EN_DIS
+**/
+  UINT8                       SaPostMemTestRsvd[32];
+
+/** Offset 0x1B85
+**/
+  UINT8                       SaFspsUpdRsvd[32];
 
 /** Offset 0x1BA5 - RSR feature
   Enable or Disable RSR feature; 0: Disable; <b>1: Enable </b>
@@ -2372,9 +3590,11 @@ typedef struct {
 **/
   UINT8                       EnableRsr;
 
-/** Offset 0x1BA6 - Reserved
+/** Offset 0x1BA6 - ReservedCpuPostMem1
+  Reserved for CPU Post-Mem 1
+  $EN_DIS
 **/
-  UINT8                       Reserved61[4];
+  UINT8                       ReservedCpuPostMem1[4];
 
 /** Offset 0x1BAA - Enable or Disable HWP
   Enable/Disable Intel(R) Speed Shift Technology support. Enabling will expose the
@@ -2769,9 +3989,9 @@ typedef struct {
 **/
   UINT8                       StateRatioMax16[16];
 
-/** Offset 0x1C1A - Reserved
+/** Offset 0x1C1A
 **/
-  UINT8                       Reserved62[2];
+  UINT8                       Rsvd400[2];
 
 /** Offset 0x1C1C - Package Long duration turbo mode power limit
   Power Limit 1 in Milli Watts. BIOS will round to the nearest 1/8W when programming.
@@ -2809,9 +4029,15 @@ typedef struct {
 **/
   UINT32                      PowerLimit4;
 
-/** Offset 0x1C2C - Reserved
+/** Offset 0x1C2C - Package PL4 boost configuration
+  Configure Power Limit 4 Boost in Watts. Valid Range 0 to 1023 in step size of 1
+  Watt. The value 0 means disable.
 **/
-  UINT8                      Reserved63[4];
+  UINT16                      PowerLimit4Boost;
+
+/** Offset 0x1C2E
+**/
+  UINT8                       Rsvd410[2];
 
 /** Offset 0x1C30 - Tcc Offset Time Window for RATL
 **/
@@ -2886,9 +4112,11 @@ typedef struct {
 **/
   UINT32                      PsysPowerLimit2Power;
 
-/** Offset 0x1C54 - Reserved
+/** Offset 0x1C54 - CCF AutoGV
+  Enable/Disable CCF AutoGV; 0: Disable; <b>1: Enable</b>
+  $EN_DIS
 **/
-  UINT8                       Reserved64;
+  UINT8                       CcfAutoGv;
 
 /** Offset 0x1C55 - Race To Halt
   Enable/Disable Race To Halt feature. RTH will dynamically increase CPU frequency
@@ -2898,9 +4126,12 @@ typedef struct {
 **/
   UINT8                       RaceToHalt;
 
-/** Offset 0x1C56 - Reserved
+/** Offset 0x1C56 - Enable or Disable Three Strike Counter
+  Enable (default): Three Strike counter will be incremented. Disable: Prevents Three
+  Strike counter from incrementing; 0: Disable; <b>1: Enable</b>
+  $EN_DIS
 **/
-  UINT8                       Reserved65;
+  UINT8                       ThreeStrikeCounter;
 
 /** Offset 0x1C57 - Set HW P-State Interrupts Enabled for for MISC_PWR_MGMT
   Set HW P-State Interrupts Enabled for for MISC_PWR_MGMT; <b>0: Disable</b>; 1: Enable.
@@ -2908,9 +4139,11 @@ typedef struct {
 **/
   UINT8                       HwpInterruptControl;
 
-/** Offset 0x1C58 - Reserved
+/** Offset 0x1C58 - ReservedCpuPostMem2
+  Reserved for CPU Post-Mem 2
+  $EN_DIS
 **/
-  UINT8                       Reserved66[4];
+  UINT8                       ReservedCpuPostMem2[4];
 
 /** Offset 0x1C5C - Enable or Disable C1 Cstate Demotion
   Enable or Disable C1 Cstate Auto Demotion. Disable; <b>1: Enable</b>
@@ -2966,9 +4199,12 @@ typedef struct {
 **/
   UINT8                       ApplyConfigTdp;
 
-/** Offset 0x1C64 - Reserved
+/** Offset 0x1C64 - Misc Power Management MSR Lock
+  Enable/Disable HWP Lock support in Misc Power Management MSR. 0: Disable, <b>1:
+  Enable </b>
+  $EN_DIS
 **/
-  UINT8                       Reserved67;
+  UINT8                       HwpLock;
 
 /** Offset 0x1C65 - Dual Tau Boost
   Enable Dual Tau Boost feature. This is only applicable for Desktop 35W/65W/125W
@@ -2977,9 +4213,51 @@ typedef struct {
 **/
   UINT8                       DualTauBoost;
 
-/** Offset 0x1C66 - Reserved
+/** Offset 0x1C66 - Response Mode
+  Use Response Mode to adjust Psys_PL3 power reduction behavior. Battery-enabled systems
+  use Gradual Power Reduction. <b>0: Gradual Power Reduction</b> ; 1: Aggressive
+  Power Reduction
+  0: Gradual Power Reduction, 1: Aggressive Power Reduction
 **/
-  UINT8                       Reserved68[34];
+  UINT8                       StepDownMode;
+
+/** Offset 0x1C67 - Power Floor Managment for SOC
+  Option to disable Power Floor Managment for SOC. Disabling this might effectively
+  raise power floor of the SoC and may lead to stability issues. 0: Disable, <b>1:
+  Enable </b>
+  $EN_DIS
+**/
+  UINT8                       PowerFloorManagement;
+
+/** Offset 0x1C68 - Power Floor Disaplay Disconnect
+  SoC can disconnect secondary/external display to lower SoC floor power (Default
+  enabled).  0: Disable: Display disconnect will not be used by SoC., <b>1: Enable </b>
+  $EN_DIS
+**/
+  UINT8                       PowerFloorDisplayDisconnect;
+
+/** Offset 0x1C69 - Resource Priority Feature
+  Enable/Disable Resource Priority Feature. Enable/Disable;  <b>0: Disable</b> ; 1:Enable
+  $EN_DIS
+**/
+  UINT8                       EnableRp;
+
+/** Offset 0x1C6A - Power Floor PCIe Gen Downgrade
+  SoC can downgrade PCIe gen speed to lower SoC floor power (Default enabled).  0:
+  Disable: Reduction in PCIe gen speed will not be used by SoC., <b>1: Enable </b>
+  $EN_DIS
+**/
+  UINT8                       PowerFloorPcieGenDowngrade;
+
+/** Offset 0x1C6B - ReservedCpuPostMemTest
+  Reserved for CPU Post-Mem Test
+  $EN_DIS
+**/
+  UINT8                       ReservedCpuPostMemTest[13];
+
+/** Offset 0x1C78
+**/
+  UINT8                       SecurityPostMemRsvd[16];
 
 /** Offset 0x1C88 - End of Post message
   Test, Send End of Post message. Disable(0x0): Disable EOP message, Send in PEI(0x1):
@@ -3015,9 +4293,17 @@ typedef struct {
 **/
   UINT8                       EnforceEDebugMode;
 
-/** Offset 0x1C8D - Reserved
+/** Offset 0x1C8D - CSE Data Resilience Support
+  0: Disable CSE Data Resilience Support. <b>1: Enable CSE Data Resilience Support.</b>
+  $EN_DIS
 **/
-  UINT8                       Reserved69[17];
+  UINT8                       CseDataResilience;
+
+/** Offset 0x1C8E - MePostMemRsvd
+  Reserved for ME Post-Mem
+  $EN_DIS
+**/
+  UINT8                       MePostMemRsvd[16];
 
 /** Offset 0x1C9E - Enable LOCKDOWN SMI
   Enable SMI_LOCK bit to prevent writes to the Global SMI Enable bit.
@@ -3044,9 +4330,9 @@ typedef struct {
 **/
   UINT8                       PchSbAccessUnlock;
 
-/** Offset 0x1CA2 - Reserved
+/** Offset 0x1CA2
 **/
-  UINT8                       Reserved70[2];
+  UINT8                       Rsvd420[2];
 
 /** Offset 0x1CA4 - PCIE RP Ltr Max Snoop Latency
   Latency Tolerance Reporting, Max Snoop Latency.
@@ -3093,9 +4379,9 @@ typedef struct {
 **/
   UINT8                       PcieRpSlotPowerLimitScale[29];
 
-/** Offset 0x1E1D - Reserved
+/** Offset 0x1E1D
 **/
-  UINT8                       Reserved71;
+  UINT8                       Rsvd430[1];
 
 /** Offset 0x1E1E - PCIE RP Slot Power Limit Value
   Specifies upper limit on power supplie by slot. Leave as 0 to set to default.
@@ -3140,9 +4426,46 @@ typedef struct {
 **/
   UINT8                       PmcLpmS0ixSubStateEnableMask;
 
-/** Offset 0x1E5E - Reserved
+/** Offset 0x1E5E - Low Power Mode Enable/Disable config mask
+  Configure if respective S0i2/3 sub-states are to be supported. Each bit corresponds
+  to one sub-state (LPMx - BITx): LPM0-s0i2.0, LPM1-s0i2.1, LPM2-s0i2.2, LPM3-s0i3.0,
+  LPM4-s0i3.1, LPM5-s0i3.2, LPM6-s0i3.3, LPM7-s0i3.4.
 **/
-  UINT8                       Reserved72[105];
+  UINT8                       PmcPchLpmS0ixSubStateEnableMask;
+
+/** Offset 0x1E5F - PCH PMC ER Debug mode
+  Disable/Enable Energy Reporting Debug Mode.
+  $EN_DIS
+**/
+  UINT8                       PchPmErDebugMode;
+
+/** Offset 0x1E60 - CPPM Forced Alignment Enable
+  Enable/Disable CPPM Force Alignment. When enabled, PMC allows stalling of the backbone
+  or blocking the DMI transmit arbiter
+  $EN_DIS
+**/
+  UINT8                       CppmFaEn;
+
+/** Offset 0x1E61 - PCH Lan WOL Fast Support
+  Enables bit B_PCH_ACPI_GPE0_EN_127_96_PME_B0 during PchLanSxCallback in PchLanSxSmm.
+  $EN_DIS
+**/
+  UINT8                       PchLanWOLFastSupport;
+
+/** Offset 0x1E62 - Platform ATX Telemetry Unit
+  Set ATX Telemetry Unit in Watts or Percentage; <b>0: Watts</b>; 1: Percent
+  $EN_DIS
+**/
+  UINT8                       PlatformAtxTelemetryUnit;
+
+/** Offset 0x1E63 - PCIE RP LTR Override Spec Complaint
+  Override LTR based on Ep capability.
+**/
+  UINT8                       PcieRpLtrOverrideSpecComplaint[29];
+
+/** Offset 0x1E80
+**/
+  UINT8                       PchMeFspsUpdRsvd[71];
 
 /** Offset 0x1EC7 - PMC C10 dynamic threshold dajustment enable
   Set if you want to enable PMC C10 dynamic threshold adjustment. Only works on supported SKUs
@@ -3150,18 +4473,58 @@ typedef struct {
 **/
   UINT8                       PmcC10DynamicThresholdAdjustment;
 
-/** Offset 0x1EC8 - Reserved
+/** Offset 0x1EC8 - Turbo Ratio Limit Ratio array
+  Performance-core Turbo Ratio Limit Ratio0-7 (TRLR) defines the turbo ratio (max
+  is 85 in normal mode and 120 in core extension mode). Ratio[0]: This Turbo Ratio
+  Limit Ratio0 must be greater than or equal all other ratio values. If this value
+  is invalid, thn set all other active cores to minimum. Otherwise, align the Ratio
+  Limit to 0. Please check each active cores. Ratio[1~7]: This Turbo Ratio Limit
+  Ratio1 must be <= to Turbo Ratio Limit Ratio0~6.
 **/
-  UINT8                       Reserved73[36];
+  UINT8                       TurboRatioLimitRatio[8];
+
+/** Offset 0x1ED0 - Turbo Ratio Limit Num Core array
+  Performance-core Turbo Ratio Limit Core0~7 defines the core range, the turbo ratio
+  is defined in Turbo Ratio Limit Ratio0~7. If value is zero, this entry is ignored.
+**/
+  UINT8                       TurboRatioLimitNumCore[8];
+
+/** Offset 0x1ED8 - ATOM Turbo Ratio Limit Ratio array
+  Efficient-core Turbo Ratio Limit Ratio0-7 defines the turbo ratio (max is 85 irrespective
+  of the core extension mode), the core range is defined in E-core Turbo Ratio Limit
+  CoreCount0-7.
+**/
+  UINT8                       AtomTurboRatioLimitRatio[8];
+
+/** Offset 0x1EE0 - ATOM Turbo Ratio Limit Num Core array
+  Efficient-core Turbo Ratio Limit CoreCount0-7 defines the core range, the turbo
+  ratio is defined in E-core Turbo Ratio Limit Ratio0-7. If value is zero, this entry
+  is ignored.
+**/
+  UINT8                       AtomTurboRatioLimitNumCore[8];
+
+/** Offset 0x1EE8
+**/
+  UINT8                       Rsvd440[4];
 
 /** Offset 0x1EEC - FspEventHandler
   <b>Optional</b> pointer to the boot loader's implementation of FSP_EVENT_HANDLER.
 **/
   UINT32                      FspEventHandler;
 
-/** Offset 0x1EF0 - Reserved
+/** Offset 0x1EF0 - Type C Port x Convert to TypeA
+  Enable / Disable(default) Type C Port x Convert to TypeA
+  $EN_DIS
 **/
-  UINT8                       Reserved74[32];
+  UINT8                       EnableTcssCovTypeA[4];
+
+/** Offset 0x1EF4
+**/
+  UINT8                       Rsvd450[16];
+
+/** Offset 0x1F04
+**/
+  UINT8                       ReservedFspsUpd[12];
 } FSP_S_CONFIG;
 
 /** Fsp S UPD Configuration

From 2e10ddb1eeca89f4f6efaace72b4477d26160bbd Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Thu, 4 Sep 2025 21:34:59 +0100
Subject: [PATCH 2047/3886] mb/starlabs/starbook/mtl: Make TCSS notify the IGD
 of changes

Set the UPD `TcNotifyIgd` to `2` (Auto), so that the TCSS subsystem
will notify the Integrated Graphics of display changes.

Change-Id: I2b47a534f0816545fe58bde8963c56f0455871eb
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89054
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/starlabs/starbook/variants/mtl/Makefile.mk | 1 +
 src/mainboard/starlabs/starbook/variants/mtl/ramstage.c  | 9 +++++++++
 2 files changed, 10 insertions(+)
 create mode 100644 src/mainboard/starlabs/starbook/variants/mtl/ramstage.c

diff --git a/src/mainboard/starlabs/starbook/variants/mtl/Makefile.mk b/src/mainboard/starlabs/starbook/variants/mtl/Makefile.mk
index 53efc2f0fe..bfea7ef255 100644
--- a/src/mainboard/starlabs/starbook/variants/mtl/Makefile.mk
+++ b/src/mainboard/starlabs/starbook/variants/mtl/Makefile.mk
@@ -7,5 +7,6 @@ romstage-y += romstage.c
 ramstage-y += devtree.c
 ramstage-y += gpio.c
 ramstage-y += hda_verb.c
+ramstage-y += ramstage.c
 
 $(call add_vbt_to_cbfs, vbt_native_res.bin, data_native_res.vbt)
diff --git a/src/mainboard/starlabs/starbook/variants/mtl/ramstage.c b/src/mainboard/starlabs/starbook/variants/mtl/ramstage.c
new file mode 100644
index 0000000000..0d400f3977
--- /dev/null
+++ b/src/mainboard/starlabs/starbook/variants/mtl/ramstage.c
@@ -0,0 +1,9 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <option.h>
+#include <soc/ramstage.h>
+
+void mainboard_silicon_init_params(FSP_S_CONFIG *supd)
+{
+	supd->TcNotifyIgd = 2; // Auto
+}

From d1967d927a9988ca9845ad2732a086174a7ca21b Mon Sep 17 00:00:00 2001
From: Varun Upadhyay <varun.upadhyay@intel.com>
Date: Wed, 3 Sep 2025 22:09:50 +0530
Subject: [PATCH 2048/3886] spd/lp5: Add SPD for MT62F1G32D2DS-031 WT:C and
 MT62F2G32D4DS-031 WT:C

Add  MT62F1G32D2DS-031 WT:C and MT62F2G32D4DS-031 WT:C in the
memory_parts.json and re-generate the SPD.

TEST=util/spd_tools/bin/spd_gen spd/lp5/memory_parts.json lp5

Change-Id: I0db533908fbea2bc04a55191960aaeec8461f47d
Signed-off-by: Varun Upadhyay <varun.upadhyay@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89027
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Usha P <usha.p@intel.com>
Reviewed-by: Krishna P Bhat D <krishna.p.bhat.d@intel.com>
---
 spd/lp5/memory_parts.json                     | 22 ++++++++++++++++++-
 .../set-0/parts_spd_manifest.generated.txt    |  2 ++
 .../set-1/parts_spd_manifest.generated.txt    |  2 ++
 3 files changed, 25 insertions(+), 1 deletion(-)

diff --git a/spd/lp5/memory_parts.json b/spd/lp5/memory_parts.json
index 946e03345a..a4a74a4391 100644
--- a/spd/lp5/memory_parts.json
+++ b/spd/lp5/memory_parts.json
@@ -339,6 +339,26 @@
                 "speedMbps": 8533,
                 "lp5x": true
             }
-        }
+	},
+	{
+	    "name": "MT62F1G32D2DS-031 WT:C",
+            "attribs": {
+                  "densityPerDieGb": 16,
+                  "diesPerPackage": 2,
+                  "bitWidthPerChannel": 16,
+                  "ranksPerChannel": 1,
+                  "speedMbps": 6400
+             }
+	},
+	{
+	    "name": "MT62F2G32D4DS-031 WT:C",
+            "attribs": {
+                  "densityPerDieGb": 16,
+                  "diesPerPackage": 4,
+                  "bitWidthPerChannel": 16,
+                  "ranksPerChannel": 2,
+                  "speedMbps": 6400
+             }
+	}
     ]
 }
diff --git a/spd/lp5/set-0/parts_spd_manifest.generated.txt b/spd/lp5/set-0/parts_spd_manifest.generated.txt
index 68eec96b47..d0aa4078c0 100644
--- a/spd/lp5/set-0/parts_spd_manifest.generated.txt
+++ b/spd/lp5/set-0/parts_spd_manifest.generated.txt
@@ -33,3 +33,5 @@ K3KL9L90EM-MGCU,spd-10.hex
 H58G66CK8BX147,spd-10.hex
 MT62F2G32D4DS-023 WT:C,spd-10.hex
 MT62F512M32D1DS-023 WT:E,spd-11.hex
+MT62F1G32D2DS-031 WT:C,spd-3.hex
+MT62F2G32D4DS-031 WT:C,spd-6.hex
diff --git a/spd/lp5/set-1/parts_spd_manifest.generated.txt b/spd/lp5/set-1/parts_spd_manifest.generated.txt
index 68eec96b47..d0aa4078c0 100644
--- a/spd/lp5/set-1/parts_spd_manifest.generated.txt
+++ b/spd/lp5/set-1/parts_spd_manifest.generated.txt
@@ -33,3 +33,5 @@ K3KL9L90EM-MGCU,spd-10.hex
 H58G66CK8BX147,spd-10.hex
 MT62F2G32D4DS-023 WT:C,spd-10.hex
 MT62F512M32D1DS-023 WT:E,spd-11.hex
+MT62F1G32D2DS-031 WT:C,spd-3.hex
+MT62F2G32D4DS-031 WT:C,spd-6.hex

From e924021e694ee970951f75557b4323387b4a42f0 Mon Sep 17 00:00:00 2001
From: Eren Peng <peng.eren@inventec.corp-partner.google.com>
Date: Tue, 16 Sep 2025 10:02:29 +0800
Subject: [PATCH 2049/3886] mb/google/trulo/var/kaladin: Add GTH1563 and
 GTH7503

Add 2 touch panels GTH1563 and GTH7503

BUG=b:444136795
TEST=flash and boot on kaladin, execute evtest to see correct HID and
verify touch function works fine

Cq-Depend:chromium:6953071, chrome-internal:8592598
Change-Id: I9b33b5c8e216c5c8e7a6d9e38cd8d01b85dec67e
Signed-off-by: Eren Peng <peng.eren@inventec.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89187
Reviewed-by: Derek Huang <derekhuang@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 .../brya/variants/kaladin/overridetree.cb     | 44 ++++++++++++++++++-
 1 file changed, 42 insertions(+), 2 deletions(-)

diff --git a/src/mainboard/google/brya/variants/kaladin/overridetree.cb b/src/mainboard/google/brya/variants/kaladin/overridetree.cb
index 6a707cedb2..ca3fa2658c 100644
--- a/src/mainboard/google/brya/variants/kaladin/overridetree.cb
+++ b/src/mainboard/google/brya/variants/kaladin/overridetree.cb
@@ -12,8 +12,10 @@ fw_config
 		option MB_USB_2C_1A 1
 	end
 	field TOUCH_PANEL 4 5
-		option TOUCH_ELAN_TOP   0
-		option TOUCH_ELAN_DBTS  1
+		option TOUCH_ELAN_TOP   	0
+		option TOUCH_ELAN_DBTS  	1
+		option TOUCH_GTH1563_TOP	2
+		option TOUCH_GTH7503_TOP	3
 	end
 	field WIFI_SAR 13 15
 		option WIFI_SAR_ID_0 0
@@ -494,6 +496,44 @@ chip soc/intel/alderlake
 					probe TOUCH_PANEL TOUCH_ELAN_TOP
 				end
 			end
+			chip drivers/i2c/hid
+				register "generic.hid" = ""GTH1563""
+				register "generic.desc" = ""G2TOUCH Touchscreen""
+				register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_E11_IRQ)"
+				register "generic.detect" = "1"
+				register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C1)"
+				register "generic.reset_delay_ms" = "70"
+				register "generic.reset_off_delay_ms" = "2"
+				register "generic.stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C4)"
+				register "generic.stop_delay_ms" = "280"
+				register "generic.stop_off_delay_ms" = "2"
+				register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C0)"
+				register "generic.enable_delay_ms" = "1"
+				register "generic.has_power_resource" = "1"
+				register "hid_desc_reg_offset" = "0x01"
+				device i2c 10 on
+					probe TOUCH_PANEL TOUCH_GTH1563_TOP
+				end
+			end
+			chip drivers/i2c/hid
+				register "generic.hid" = ""GTH7503""
+				register "generic.desc" = ""G2TOUCH Touchscreen""
+				register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_E11_IRQ)"
+				register "generic.detect" = "1"
+				register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C1)"
+				register "generic.reset_delay_ms" = "70"
+				register "generic.reset_off_delay_ms" = "2"
+				register "generic.stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C4)"
+				register "generic.stop_delay_ms" = "280"
+				register "generic.stop_off_delay_ms" = "2"
+				register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C0)"
+				register "generic.enable_delay_ms" = "1"
+				register "generic.has_power_resource" = "1"
+				register "hid_desc_reg_offset" = "0x01"
+				device i2c 10 on
+					probe TOUCH_PANEL TOUCH_GTH7503_TOP
+				end
+			end
 			chip drivers/i2c/hid
 				register "generic.hid" = ""ELAN2513""
 				register "generic.desc" = ""ELAN Touchscreen""

From a3b73464b5144e6d960f72a79d2d988bd331199d Mon Sep 17 00:00:00 2001
From: Kapil Porwal <kapilporwal@google.com>
Date: Tue, 16 Sep 2025 08:25:38 +0530
Subject: [PATCH 2050/3886] soc/qualcomm/x1p42100/usb: Fix code comments and
 debug messages

Fix code comments and debug messages.

BUG=none
TEST=Build Google/Quenbi.

Debug logs:
```
[INFO ]  Setting up USB HOST0 controller.
[DEBUG]  USB HS PHY initialized for index 0
[DEBUG]  USB HS PHY initialized for index 1
[DEBUG]  QMP PHY MP0 init
[DEBUG]  QMP PHY MP0 initialized and locked in 1674us
[DEBUG]  QMP PHY MP1 init
[DEBUG]  QMP PHY MP1 initialized and locked in 1674us
[SPEW ]  Configure USB in Host mode
[INFO ]  DWC3 and PHY setup finished
```

Change-Id: If606a247657ffe39203101a5ff38439348deba29
Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89188
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/soc/qualcomm/x1p42100/usb/qmpv4_usb_phy.c | 11 +++++++----
 1 file changed, 7 insertions(+), 4 deletions(-)

diff --git a/src/soc/qualcomm/x1p42100/usb/qmpv4_usb_phy.c b/src/soc/qualcomm/x1p42100/usb/qmpv4_usb_phy.c
index 38556b8b4d..0f85389828 100644
--- a/src/soc/qualcomm/x1p42100/usb/qmpv4_usb_phy.c
+++ b/src/soc/qualcomm/x1p42100/usb/qmpv4_usb_phy.c
@@ -463,7 +463,7 @@ static bool ss_qmp_phy_init_common(const struct ss_usb_phy_reg *ss_phy_reg)
 	udelay(100);
 	/*
 	 * Wait for PHY initialization to be done
-	 * PCS_STATUS: wait for 1ms for PHY STATUS;
+	 * PCS_STATUS: wait for 10ms for PHY STATUS;
 	 * SW can continuously check for PHYSTATUS = 1.b0.
 	 */
 	long lock_us = wait_us(10000,
@@ -471,7 +471,8 @@ static bool ss_qmp_phy_init_common(const struct ss_usb_phy_reg *ss_phy_reg)
 			USB3_PCS_PHYSTATUS));
 	if (!lock_us) {
 		ret = false;
-		printk(BIOS_ERR, "QMP PHY %s PLL LOCK fails:\n", ss_phy_reg->name);
+		printk(BIOS_ERR, "QMP PHY %s PLL LOCK failed after %ldus\n",
+				ss_phy_reg->name, lock_us);
 	} else {
 		printk(BIOS_DEBUG, "QMP PHY %s initialized and locked in %ldus\n",
 				ss_phy_reg->name, lock_us);
@@ -479,8 +480,10 @@ static bool ss_qmp_phy_init_common(const struct ss_usb_phy_reg *ss_phy_reg)
 	return ret;
 }
 
-/* Unified ss_qmp_phy_init function to initialize a specific PHY instance
-Pass 0 for MP0, or 1 for MP1. */
+/*
+ * Unified ss_qmp_phy_init function to initialize a specific PHY
+ * instance. Pass 0 for MP0 and 1 for MP1.
+ */
 bool ss_qmp_phy_init(u32 phy_idx)
 {
 	bool ret = true;

From 6c06602c75b074012700640b46e960b628577d52 Mon Sep 17 00:00:00 2001
From: John Su <john_su@compal.corp-partner.google.com>
Date: Tue, 9 Sep 2025 16:04:46 +0800
Subject: [PATCH 2051/3886] mb/google/brya/var/uldrenite: Add fw_config probe
 for touchpad

Because the touchpad includes two touch chips with the same I2C slave
address, the firmware configuration is used to differentiate them.

BUG=b:437025836
TEST=emerge-nissa coreboot

Change-Id: If1e414594a2866bdc122d48d5f3e2f36066cd3d5
Signed-off-by: John Su <john_su@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89106
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 .../brya/variants/uldrenite/overridetree.cb   | 19 ++++++++++++++++++-
 1 file changed, 18 insertions(+), 1 deletion(-)

diff --git a/src/mainboard/google/brya/variants/uldrenite/overridetree.cb b/src/mainboard/google/brya/variants/uldrenite/overridetree.cb
index 8b9f69ab10..be87bc8bb4 100644
--- a/src/mainboard/google/brya/variants/uldrenite/overridetree.cb
+++ b/src/mainboard/google/brya/variants/uldrenite/overridetree.cb
@@ -19,6 +19,10 @@ fw_config
 		option ISH_DISABLE		0
 		option ISH_ENABLE		1
 	end
+	field SERIES 9 9
+		option SERIES_ULDRENITE		0
+		option SERIES_ULDRINO		1
+	end
 	field STORAGE 30 31
 		option STORAGE_EMMC		0
 		option STORAGE_NVME		1
@@ -357,7 +361,20 @@ chip soc/intel/alderlake
 				register "generic.detect" = "1"
 				register "generic.wake" = "GPE0_DW1_03"
 				register "hid_desc_reg_offset" = "0x20"
-				device i2c 2c on end
+				device i2c 2c on
+					probe SERIES SERIES_ULDRENITE
+				end
+			end
+			chip drivers/i2c/hid
+				register "generic.hid" = ""GDIX0000""
+				register "generic.desc" = ""Goodix Touchpad""
+				register "generic.irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_B3_IRQ)"
+				register "generic.detect" = "1"
+				register "generic.wake" = "GPE0_DW1_03"
+				register "hid_desc_reg_offset" = "0x20"
+				device i2c 2c on
+					probe SERIES SERIES_ULDRINO
+				end
 			end
 		end # I2C1
 		device ref i2c5 on

From 2a7a0e86cd5c2030c04ed4e7fe7f9fe96a623732 Mon Sep 17 00:00:00 2001
From: Bora Guvendik <bora.guvendik@intel.com>
Date: Tue, 9 Sep 2025 10:52:03 -0700
Subject: [PATCH 2052/3886] mb/google/fatcat: Configure Acoustic noise
 mitigation

As per Intel doc 861712, enable acoustic noise mitigation for fatcat,
disable fast PKG C state ramp and set slew rate to Fast/2 for VR
domain.
Reference: Intel doc 861712

TEST=Able to build and boot google/fatcat.

Before:

AcousticNoiseMitigation : 0x0
FastPkgCRampDisable for Index = 1 : 0x2
SlowSlewRate for Index = 1 : 0x0

After:

AcousticNoiseMitigation : 0x1
FastPkgCRampDisable for Index = 1 : 0x1
SlowSlewRate for Index = 1 : 0x0

Change-Id: I63c51354cb70c87f9c9c239cb56d5c64f0eabe32
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89124
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
---
 .../google/fatcat/variants/baseboard/fatcat/devicetree.cb   | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/src/mainboard/google/fatcat/variants/baseboard/fatcat/devicetree.cb b/src/mainboard/google/fatcat/variants/baseboard/fatcat/devicetree.cb
index fd9a6b4513..68bf4a112e 100644
--- a/src/mainboard/google/fatcat/variants/baseboard/fatcat/devicetree.cb
+++ b/src/mainboard/google/fatcat/variants/baseboard/fatcat/devicetree.cb
@@ -30,6 +30,12 @@ chip soc/intel/pantherlake
 	register "tcss_ports[2]" = "TCSS_PORT_EMPTY"	# Disable USB-C Port 2
 	register "tcss_ports[3]" = "TCSS_PORT_EMPTY"	# Disable USB-C Port 3
 
+	# Acoustic Noise settings and slew rate configuration:
+	# Slew rate for GT Domain: Fast/2
+	register "enable_acoustic_noise_mitigation" = "true"
+	register "disable_fast_pkgc_ramp[VR_DOMAIN_GT]" = "true"
+	register "slow_slew_rate_config[VR_DOMAIN_GT]" = "SLEW_FAST_2"
+
 	# Enable SAGv
 	register "sagv" = "SAGV_ENABLED"
 

From 2b1809e026f2ba4b9b54dcee9db07b4b7a2b5e6f Mon Sep 17 00:00:00 2001
From: Bora Guvendik <bora.guvendik@intel.com>
Date: Tue, 9 Sep 2025 11:41:50 -0700
Subject: [PATCH 2053/3886] mb/google/fatcat: Increase Fast VMode I_TRIP
 threshold to 63A

Change I_TRIP value from 38A to 63A.
Reference: Intel doc 861712

Bug=none
TEST=Boot to OS and verify I_TRIP value via boot logs

Before: IccLimit[0] : 0x98

After: IccLimit[0] : 0xFC

Change-Id: I88687bd481f6e8fc7ef0c9289e7066e59b2a8ea5
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89125
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 .../google/fatcat/variants/baseboard/fatcat/devicetree.cb       | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/mainboard/google/fatcat/variants/baseboard/fatcat/devicetree.cb b/src/mainboard/google/fatcat/variants/baseboard/fatcat/devicetree.cb
index 68bf4a112e..a097ea7142 100644
--- a/src/mainboard/google/fatcat/variants/baseboard/fatcat/devicetree.cb
+++ b/src/mainboard/google/fatcat/variants/baseboard/fatcat/devicetree.cb
@@ -91,7 +91,7 @@ chip soc/intel/pantherlake
 		[VR_DOMAIN_SA] = 38 * 4
 	}"
 	register "fast_vmode_i_trip[PTL_U_2_CORE]" = "{
-		[VR_DOMAIN_IA] = 38 * 4,
+		[VR_DOMAIN_IA] = 63 * 4,
 		[VR_DOMAIN_GT] = 38 * 4,
 		[VR_DOMAIN_SA] = 38 * 4
 	}"

From cf3af46e504f6c78d17af1e0a3af5f4143a8b900 Mon Sep 17 00:00:00 2001
From: Yang Wu <wuyang5@huaqin.corp-partner.google.com>
Date: Mon, 15 Sep 2025 21:36:02 +0800
Subject: [PATCH 2054/3886] mb/google/skywalker: Create variant Padme

Create the variant Padme.

BUG=b:440994425
TEST=emerge-jedi coreboot chromeos-bootimage
BRANCH=None

Change-Id: I1a02979f612b4da2ea699d142fae3a89ace4d49b
Signed-off-by: Yang Wu <wuyang5@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89179
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
---
 src/mainboard/google/skywalker/Kconfig      | 2 ++
 src/mainboard/google/skywalker/Kconfig.name | 3 +++
 2 files changed, 5 insertions(+)

diff --git a/src/mainboard/google/skywalker/Kconfig b/src/mainboard/google/skywalker/Kconfig
index 34e3b5355c..81b49ba513 100644
--- a/src/mainboard/google/skywalker/Kconfig
+++ b/src/mainboard/google/skywalker/Kconfig
@@ -5,6 +5,7 @@ config BOARD_GOOGLE_SKYWALKER_COMMON
 	def_bool BOARD_GOOGLE_ANAKIN || \
 		 BOARD_GOOGLE_BAZE || \
 		 BOARD_GOOGLE_OBIWAN || \
+		 BOARD_GOOGLE_PADME || \
 		 BOARD_GOOGLE_SKYWALKER || \
 		 BOARD_GOOGLE_TARKIN || \
 		 BOARD_GOOGLE_YODA
@@ -50,6 +51,7 @@ config MAINBOARD_PART_NUMBER
 	default "Anakin" if BOARD_GOOGLE_ANAKIN
 	default "Baze" if BOARD_GOOGLE_BAZE
 	default "Obiwan" if BOARD_GOOGLE_OBIWAN
+	default "Padme" if BOARD_GOOGLE_PADME
 	default "Skywalker" if BOARD_GOOGLE_SKYWALKER
 	default "Tarkin" if BOARD_GOOGLE_TARKIN
 	default "Yoda" if BOARD_GOOGLE_YODA
diff --git a/src/mainboard/google/skywalker/Kconfig.name b/src/mainboard/google/skywalker/Kconfig.name
index d77b880023..8343e47a03 100644
--- a/src/mainboard/google/skywalker/Kconfig.name
+++ b/src/mainboard/google/skywalker/Kconfig.name
@@ -11,6 +11,9 @@ config BOARD_GOOGLE_BAZE
 config BOARD_GOOGLE_OBIWAN
 	bool "->  Obiwan"
 
+config BOARD_GOOGLE_PADME
+	bool "-> Padme"
+
 config BOARD_GOOGLE_SKYWALKER
 	bool "->  Skywalker"
 

From bf83dd99270dbaa4f0ed9c7134cef5b44b0f7013 Mon Sep 17 00:00:00 2001
From: Subrata Banik <subratabanik@google.com>
Date: Mon, 15 Sep 2025 20:48:52 +0000
Subject: [PATCH 2055/3886] soc/qualcomm/common/qclib: Introduce runtime debug
 log level control

Introduce a new static function, `qclib_debug_log_level`, that
checks a runtime-configurable option, "qclib_debug_level", to
control whether QCLib enables serial logging.

This allows for dynamic control of QCLib's verbose output via a
coreboot option instead of relying solely on the static
`CONFIG(CONSOLE_SERIAL)` Kconfig option. This is necessary because
while the serial console might be enabled for general coreboot
logging, the user may want to suppress the often extensive and
low-level output from QCLib to keep the console clean during normal
operations.

The check for enabling QCLib's serial output is updated from
`if (CONFIG(CONSOLE_SERIAL))` to
`if (CONFIG(CONSOLE_SERIAL) && qclib_debug_log_level())`

The option value is read using
`get_uint_option("qclib_debug_level", 1)`, meaning the default
behavior is to enable QCLib logging if `CONSOLE_SERIAL` is set,
maintaining backward compatibility unless the option is explicitly
set to 0 at runtime.

BUG=b:445211186
TEST=Build and boot a Qualcomm platform with CONFIG_CONSOLE_SERIAL
enabled. Confirmed QCLib logs are present by default.
Set option "qclib_debug_level" to 0 via CBFS option and confirmed
QCLib logs are suppressed while coreboot serial output remains
active.

Change-Id: I2c7326fae889508f09e1eb5e3863456cf54f5c29
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89185
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
---
 src/soc/qualcomm/common/qclib.c | 10 ++++++++--
 1 file changed, 8 insertions(+), 2 deletions(-)

diff --git a/src/soc/qualcomm/common/qclib.c b/src/soc/qualcomm/common/qclib.c
index cb694e356d..1daa14b328 100644
--- a/src/soc/qualcomm/common/qclib.c
+++ b/src/soc/qualcomm/common/qclib.c
@@ -9,6 +9,7 @@
 #include <console/console.h>
 #include <fmap.h>
 #include <mrc_cache.h>
+#include <option.h>
 #include <reset.h>
 #include <security/vboot/misc.h>
 #include <soc/mmu.h>
@@ -182,6 +183,11 @@ static void dump_te_table(void)
 
 __weak int qclib_soc_override(struct qclib_cb_if_table *table) { return 0; }
 
+static bool qclib_debug_log_level(void)
+{
+	return get_uint_option("qclib_debug_level", 1);
+}
+
 struct prog qclib; /* This will be re-used by qclib_rerun() */
 
 static void qclib_prepare_and_run(void)
@@ -195,8 +201,8 @@ static void qclib_prepare_and_run(void)
 				_qclib_serial_log,
 				REGION_SIZE(qclib_serial_log), 0);
 
-	/* Enable QCLib serial output, based on Kconfig */
-	if (CONFIG(CONSOLE_SERIAL))
+	/* Enable QCLib serial output, if below condition is met */
+	if (CONFIG(CONSOLE_SERIAL) && qclib_debug_log_level())
 		qclib_cb_if_table.global_attributes =
 			QCLIB_GA_ENABLE_UART_LOGGING;
 

From 81bb2663b7598c497e2f6893d21fd4d76117c9e6 Mon Sep 17 00:00:00 2001
From: Subrata Banik <subratabanik@google.com>
Date: Mon, 15 Sep 2025 20:51:11 +0000
Subject: [PATCH 2056/3886] soc/qualcomm/x1p42100: Select
 HAVE_CBFS_FILE_OPTION_BACKEND

Select the newly introduced `HAVE_CBFS_FILE_OPTION_BACKEND` capability
for the Qualcomm x1p42100 SoC family.

This SoC is used in ChromeOS devices that rely on the CBFS file backend
to store and retrieve runtime configuration options (like the QCLib
configuration data). Selecting this capability ensures the correct
option backend is chosen in the Kconfig `Option backend to use` choice.

TEST=Build and boot a board using the x1p42100 SoC (e.g., bluey).
     Confirm the `CONFIG_USE_CBFS_FILE_OPTION_BACKEND` option is enabled
     in the build.

Change-Id: Ie0dee155a504da215669a79d7100cdbaf97d5261
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89186
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
---
 src/soc/qualcomm/x1p42100/Kconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/src/soc/qualcomm/x1p42100/Kconfig b/src/soc/qualcomm/x1p42100/Kconfig
index 26bcb22920..c02c2a649b 100644
--- a/src/soc/qualcomm/x1p42100/Kconfig
+++ b/src/soc/qualcomm/x1p42100/Kconfig
@@ -17,6 +17,7 @@ config SOC_QUALCOMM_BASE
 	select GENERIC_GPIO_LIB
 	select GENERIC_UDELAY
 	select HAS_RECOVERY_MRC_CACHE
+	select HAVE_CBFS_FILE_OPTION_BACKEND
 	select HAVE_LINEAR_FRAMEBUFFER
 	select HAVE_MONOTONIC_TIMER
 	select HAVE_UART_SPECIAL

From 79119456a255cfa40f63c63634115e8d4ff10610 Mon Sep 17 00:00:00 2001
From: Benjamin Doron <benjamin.doron@9elements.com>
Date: Tue, 9 Sep 2025 10:17:47 -0400
Subject: [PATCH 2057/3886] soc/amd/common/block/iommu: Add missing newline to
 debug print

This makes the log easier to parse.

Change-Id: I1ac3e186b7830dc79f22540810f121806d36175f
Signed-off-by: Benjamin Doron <benjamin.doron@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89120
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/soc/amd/common/block/iommu/iommu.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/soc/amd/common/block/iommu/iommu.c b/src/soc/amd/common/block/iommu/iommu.c
index 43eda7cbb0..c041d753fe 100644
--- a/src/soc/amd/common/block/iommu/iommu.c
+++ b/src/soc/amd/common/block/iommu/iommu.c
@@ -28,7 +28,7 @@ static void iommu_enable_resources(struct device *dev)
 	uint32_t base = pci_read_config32(dev, IOMMU_CAP_BASE_LO);
 	base |= IOMMU_ENABLE;
 	pci_write_config32(dev, IOMMU_CAP_BASE_LO, base);
-	printk(BIOS_DEBUG, "%s -> mmio enable: %08X", __func__,
+	printk(BIOS_DEBUG, "%s -> mmio enable: %08X\n", __func__,
 	       pci_read_config32(dev, IOMMU_CAP_BASE_LO));
 	pci_dev_enable_resources(dev);
 }

From 5a9ca2b0405651d8962dad2362eddf49f589f4ba Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Wed, 17 Sep 2025 11:26:50 +0100
Subject: [PATCH 2058/3886] mb/starlabs/starbook/mtl: Set SPD size to 512

We only need the first 512, so skip reading the rest to save
boot time. With 96GB, it reduces time in FSP-M from 906,307
to 326,302.

Change-Id: Ia226402fdf613ba4b851fa9c4c7d9354d599be7c
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89220
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
---
 src/mainboard/starlabs/starbook/Kconfig | 1 -
 1 file changed, 1 deletion(-)

diff --git a/src/mainboard/starlabs/starbook/Kconfig b/src/mainboard/starlabs/starbook/Kconfig
index bfb986fc6f..8f19501996 100644
--- a/src/mainboard/starlabs/starbook/Kconfig
+++ b/src/mainboard/starlabs/starbook/Kconfig
@@ -143,7 +143,6 @@ config DEVICETREE
 	default "variants/\$(CONFIG_VARIANT_DIR)/devicetree.cb"
 
 config DIMM_SPD_SIZE
-	default 1024 if BOARD_STARLABS_STARBOOK_MTL
 	default 512
 
 config DRIVER_TPM_SPI_CHIP

From 0fec287327f5e3027bd7f6019458b3e5d660a674 Mon Sep 17 00:00:00 2001
From: David Wu <david_wu@quanta.corp-partner.google.com>
Date: Thu, 4 Sep 2025 14:32:33 +0800
Subject: [PATCH 2059/3886] mb/google/nissa/var/dirks: Drive GPIO GPP_D2 high
 to fix noise issue

Due to a GPIO configuration issue, the buzzer continues to operate
after the OS boots, producing noise from the capacitor.

The buzzer is driven by the GPIO pin and P_MOS, so it should be set
to high in the coreboot.

For the schematics, please refer to b:442747023#comment4.

BUG=b:442747023
TEST=Can not hear abnormal noise.

Change-Id: I720e5cc0e8c499d654a2b3002c3647d37e2ae8d3
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89035
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Derek Huang <derekhuang@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/google/brya/variants/dirks/gpio.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/mainboard/google/brya/variants/dirks/gpio.c b/src/mainboard/google/brya/variants/dirks/gpio.c
index 77ddade671..52b75b1447 100644
--- a/src/mainboard/google/brya/variants/dirks/gpio.c
+++ b/src/mainboard/google/brya/variants/dirks/gpio.c
@@ -37,7 +37,7 @@ static const struct pad_config override_gpio_table[] = {
 	PAD_NC(GPP_C7, NONE),
 
 	/* D2  :  PWM_PP3300_BUZZER */
-	PAD_CFG_GPO(GPP_D2, 0, DEEP),
+	PAD_CFG_GPO(GPP_D2, 1, DEEP),
 	/* D3  : ISH_GP3 ==> NC */
 	PAD_NC(GPP_D3, NONE),
 	/* D6  : SRCCLKREQ1# ==> NC */

From ddf5987c1e994d241541348a6372d2afe8e4cf7c Mon Sep 17 00:00:00 2001
From: Yang Wu <wuyang5@huaqin.corp-partner.google.com>
Date: Tue, 16 Sep 2025 18:16:43 +0800
Subject: [PATCH 2060/3886] drivers/mipi: Add support for TM_TL121BVMS07_00C
 panel

Add TM panel TM_TL121BVMS07_00C serializable data to CBFS.
Datasheet: Preliminary+specification+TL121BVMS07+-00+V01+20250721.pdf

The developer/recovery screen is not functional yet as the vendor is
still debugging it. This change is proposed to enable firmware build.

[INFO ]  CBFS: Found 'panel-TM_TL121BVMS07_00C' @0x81f80 size 0x77
in mcache @0xfffdd540


BUG=b:428854543
TEST=build and check the CBFS include the panel
BRANCH=skywalker

Change-Id: I50e56aef1576722b7f2fb811c5d9df2a5697edae
Signed-off-by: Yang Wu <wuyang5@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89216
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
---
 src/drivers/mipi/Kconfig                    |  3 ++
 src/drivers/mipi/Makefile.mk                |  2 ++
 src/drivers/mipi/panel-TM_TL121BVMS07_00C.c | 38 +++++++++++++++++++++
 3 files changed, 43 insertions(+)
 create mode 100644 src/drivers/mipi/panel-TM_TL121BVMS07_00C.c

diff --git a/src/drivers/mipi/Kconfig b/src/drivers/mipi/Kconfig
index 1d271c7ee7..62b28e5cf1 100644
--- a/src/drivers/mipi/Kconfig
+++ b/src/drivers/mipi/Kconfig
@@ -72,5 +72,8 @@ config MIPI_PANEL_STA_HIMAX83102_J02
 config MIPI_PANEL_STA_ILI9882T
 	bool
 
+config MIPI_PANEL_TM_TL121BVMS07_00C
+	bool
+
 config MIPI_PANEL_VIS_RM69299
 	bool
diff --git a/src/drivers/mipi/Makefile.mk b/src/drivers/mipi/Makefile.mk
index 9464421bb9..2d1ac9429a 100644
--- a/src/drivers/mipi/Makefile.mk
+++ b/src/drivers/mipi/Makefile.mk
@@ -36,6 +36,8 @@ panel-params-$(CONFIG_MIPI_PANEL_STA_ER88577) += panel-STA_ER88577
 panel-params-$(CONFIG_MIPI_PANEL_STA_HIMAX83102_J02) += panel-STA_HIMAX83102_J02
 panel-params-$(CONFIG_MIPI_PANEL_STA_ILI9882T) += panel-STA_ILI9882T
 
+panel-params-$(CONFIG_MIPI_PANEL_TM_TL121BVMS07_00C) += panel-TM_TL121BVMS07_00C
+
 panel-params-$(CONFIG_MIPI_PANEL_VIS_RM69299) += panel-VIS_RM69299
 
 $(foreach params,$(panel-params-y), \
diff --git a/src/drivers/mipi/panel-TM_TL121BVMS07_00C.c b/src/drivers/mipi/panel-TM_TL121BVMS07_00C.c
new file mode 100644
index 0000000000..22f6d87a42
--- /dev/null
+++ b/src/drivers/mipi/panel-TM_TL121BVMS07_00C.c
@@ -0,0 +1,38 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <mipi/panel.h>
+
+struct panel_serializable_data TM_TL121BVMS07_00C = {
+	.edid = {
+		.ascii_string = "TL121BVMS07",
+		.manufacturer_name = "TM",
+		.panel_bits_per_color = 8,
+		.panel_bits_per_pixel = 24,
+		.mode = {
+			.pixel_clock = 4400560,
+			.lvds_dual_channel = 0,
+			.refresh = 60,
+			.ha = 1600, .hbl = 44, .hso = 20, .hspw = 4,
+			.va = 2560, .vbl = 120, .vso = 82, .vspw = 2,
+			.phsync = '-', .pvsync = '-',
+			.x_mm = 163, .y_mm = 261,
+		},
+	},
+	.init = {
+		PANEL_DELAY(24),
+		PANEL_DCS(0xFF, 0x5A, 0xA5, 0x06),
+		PANEL_DCS(0x3E, 0x62),
+		PANEL_DCS(0xFF, 0x5A, 0xA5, 0x02),
+		PANEL_DCS(0x1B, 0x20),
+		PANEL_DCS(0x5D, 0x00),
+		PANEL_DCS(0x5E, 0x40),
+		PANEL_DCS(0xFF, 0x5A, 0xA5, 0x07),
+		PANEL_DCS(0X29, 0x00),
+		PANEL_DCS(0xFF, 0x5A, 0xA5, 0x00),
+		PANEL_DCS(0x11),
+		PANEL_DELAY(120),
+		PANEL_DCS(0x29),
+		PANEL_DELAY(20),
+		PANEL_END,
+	},
+};

From 3b4c446fbb644b44162f34da384c373931202272 Mon Sep 17 00:00:00 2001
From: Kapil Porwal <kapilporwal@google.com>
Date: Thu, 18 Sep 2025 00:02:25 +0530
Subject: [PATCH 2061/3886] mb/google/bluey: Configure QUP0 SE1 as I2C

USB-A retimer, which is an I2C device, is connected to QUP0 SE1.

BUG=b:445441291
TEST=Build and boot to Google/Quenbi.

Debug log:
```
[INFO ]  VB2:vb2_digest_init() 3872 bytes, hash algo 2, HW acceleration enabled
[INFO ]  CBFS: Found 'fallback/i2c_fw' @0xa9500 size 0x576 in mcache @0xff7dd470
```

Change-Id: Ic1f7c22b6e453b703892af8af7dc3aadddf1f056
Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89225
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
---
 src/mainboard/google/bluey/mainboard.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/src/mainboard/google/bluey/mainboard.c b/src/mainboard/google/bluey/mainboard.c
index 1c9a87f844..123e39854d 100644
--- a/src/mainboard/google/bluey/mainboard.c
+++ b/src/mainboard/google/bluey/mainboard.c
@@ -68,6 +68,7 @@ static void mainboard_init(struct device *dev)
 	qupv3_se_fw_load_and_init(QUPV3_1_SE0, SE_PROTOCOL_I2C, MIXED); /* Touch I2C */
 	qupv3_se_fw_load_and_init(QUPV3_1_SE6, SE_PROTOCOL_UART, FIFO); /* BT UART */
 	qupv3_se_fw_load_and_init(QUPV3_0_SE0, SE_PROTOCOL_I2C, MIXED); /* Trackpad I2C */
+	qupv3_se_fw_load_and_init(QUPV3_0_SE1, SE_PROTOCOL_I2C, MIXED); /* USB-A retimer */
 	if (CONFIG(MAINBOARD_HAS_FINGERPRINT_VIA_SPI))
 		qupv3_se_fw_load_and_init(QUPV3_2_SE2, SE_PROTOCOL_SPI, MIXED); /* Fingerprint SPI */
 

From 9af9e1d1f423ef7c63d9f95e38df7d7a9a06bbf4 Mon Sep 17 00:00:00 2001
From: Doris Hsu <doris.hsu@intel.com>
Date: Thu, 4 Sep 2025 14:35:12 +0800
Subject: [PATCH 2062/3886] mb/google/trulo/var/kaladin: Add eMMC DLL settings

Configure eMMC DLL tuning values for Kaladin project.
Sending different speed TX/RX command/data signal to eMMC and check the response is success or not.
Based on the test result from each eMMC source used in the project as the tuning value.
Refer to EDS-Vol2-42.3

BUG=b:440126134
TEST=Pass on 2500 cycle of cold boot stress on all eMMC sku

Change-Id: I6295b36500053356a28d51b48a9758ee32b82b53
Signed-off-by: Doris Hsu <doris.hsu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89034
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyle Lin <kylelinck@google.com>
---
 .../brya/variants/kaladin/overridetree.cb     | 45 +++++++++++++++++++
 1 file changed, 45 insertions(+)

diff --git a/src/mainboard/google/brya/variants/kaladin/overridetree.cb b/src/mainboard/google/brya/variants/kaladin/overridetree.cb
index ca3fa2658c..85867c9fd7 100644
--- a/src/mainboard/google/brya/variants/kaladin/overridetree.cb
+++ b/src/mainboard/google/brya/variants/kaladin/overridetree.cb
@@ -32,6 +32,51 @@ end
 chip soc/intel/alderlake
 	register "sagv" = "SaGv_Enabled"
 
+	# EMMC Tx CMD Delay
+	# Refer to EDS-Vol2-42.3.7.
+	# [14:8] steps of delay for DDR mode, each 125ps, range: 0 - 39.
+	# [6:0] steps of delay for SDR mode, each 125ps, range: 0 - 39.
+	register "common_soc_config.emmc_dll.emmc_tx_cmd_cntl" = "0x505"
+
+	# EMMC TX DATA Delay 1
+	# Refer to EDS-Vol2-42.3.8.
+	# [14:8] steps of delay for HS400, each 125ps, range: 0 - 78.
+	# [6:0] steps of delay for SDR104/HS200, each 125ps, range: 0 - 79.
+	register "common_soc_config.emmc_dll.emmc_tx_data_cntl1" = "0x909"
+
+	# EMMC TX DATA Delay 2
+	# Refer to EDS-Vol2-42.3.9.
+	# [30:24] steps of delay for SDR50, each 125ps, range: 0 - 79.
+	# [22:16] steps of delay for DDR50, each 125ps, range: 0 - 78.
+	# [14:8] steps of delay for SDR25/HS50, each 125ps, range: 0 -79.
+	# [6:0] steps of delay for SDR12, each 125ps. Range: 0 - 79.
+	register "common_soc_config.emmc_dll.emmc_tx_data_cntl2" = "0x1C2A2828"
+
+	# EMMC RX CMD/DATA Delay 1
+	# Refer to EDS-Vol2-42.3.10.
+	# [30:24] steps of delay for SDR50, each 125ps, range: 0 - 119.
+	# [22:16] steps of delay for DDR50, each 125ps, range: 0 - 78.
+	# [14:8] steps of delay for SDR25/HS50, each 125ps, range: 0 - 119.
+	# [6:0] steps of delay for SDR12, each 125ps, range: 0 - 119.
+	register "common_soc_config.emmc_dll.emmc_rx_cmd_data_cntl1" = "0x1C1B1D3C"
+
+	# EMMC RX CMD/DATA Delay 2
+	# Refer to EDS-Vol2-42.3.12.
+	# [17:16] stands for Rx Clock before Output Buffer,
+	#         00: Rx clock after output buffer,
+	#         01: Rx clock before output buffer,
+	#         10: Automatic selection based on working mode.
+	#         11: Reserved
+	# [14:8] steps of delay for Auto Tuning Mode, each 125ps, range: 0 - 39.
+	# [6:0] steps of delay for HS200, each 125ps, range: 0 - 79.
+	register "common_soc_config.emmc_dll.emmc_rx_cmd_data_cntl2" = "0x1004C"
+
+	# EMMC Rx Strobe Delay
+	# Refer to EDS-Vol2-42.3.11.
+	# [14:8] Rx Strobe Delay DLL 1(HS400 Mode), each 125ps, range: 0 - 39.
+	# [6:0] Rx Strobe Delay DLL 2(HS400 Mode), each 125ps, range: 0 - 39.
+	register "common_soc_config.emmc_dll.emmc_rx_strobe_cntl" = "0x01515"
+
 	# GPE configuration
 	register "pmc_gpe0_dw0" = "GPP_A"
 	register "pmc_gpe0_dw1" = "GPP_H"

From 9a8402adf9148705db12040d806fee1c547833fd Mon Sep 17 00:00:00 2001
From: "wu.garen" <wu.garen@inventec.corp-partner.google.com>
Date: Tue, 16 Sep 2025 14:46:01 +0800
Subject: [PATCH 2063/3886] mb/google/trulo/var/kaladin: Update HDA verb table

Update HDA verb table for Realtek 3247 audio codec.
1. Class-d output power from 2.0W/4ohm to 2.2W/4ohm
2. AGC setting from pre-gain +6dB, limit -6dB, post-gain +6dB
   to pre-gain +0dB, limit -0dB, post-gain +0dB

BUG=b:445090513
TEST= emerge-nissa coreboot and verify alsa-dump as expected

Change-Id: Ie100b7fb0738d7092997100dd4259360f8603f05
Signed-off-by: wu.garen <wu.garen@inventec.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89213
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
---
 .../google/brya/variants/kaladin/hda_verb.c   | 21 ++++++++++++-------
 1 file changed, 13 insertions(+), 8 deletions(-)

diff --git a/src/mainboard/google/brya/variants/kaladin/hda_verb.c b/src/mainboard/google/brya/variants/kaladin/hda_verb.c
index 710153a42f..bb978b8120 100644
--- a/src/mainboard/google/brya/variants/kaladin/hda_verb.c
+++ b/src/mainboard/google/brya/variants/kaladin/hda_verb.c
@@ -6,7 +6,7 @@ const u32 cim_verb_data[] = {
 	/* coreboot specific header */
 	0x10ec0236,	// Codec Vendor / Device ID: Realtek ALC236
 	0x103C8C60,	// Subsystem ID
-	0x00000015,	// Number of jacks (NID entries)
+	0x00000016,	// Number of jacks (NID entries)
 
 	AZALIA_RESET(0x1),
 	/* NID 0x01, HDA Codec Subsystem ID Verb table */
@@ -87,19 +87,24 @@ const u32 cim_verb_data[] = {
 	/* enable EQ */
 	0x05350000,
 	0x0534E01A,
-	/* 1.8W/4ohm */
+	/* 2.2W/4ohm */
 	0x02050038,
-	0x02047901,
-	/* AGC Enable */
-	0x0205004C,
-	0x0204465C,
+	0x02046901,
+	/* Disable AGC and set AGC limit to 0dB */
+	0x02050016,
+	0x02044C50,
+	0x02050012,
+	0x0204EBC0,
+	/* Set AGC Front and Post gain 0dB then Enable AGC */
+	0x02050013,
+	0x0204401F,
 	0x02050016,
 	0x02044E50,
-	0x02050020,
-	0x020451FF,
 	/* Headphone Pop */
 	0x05750007,
 	0x057412B2,
+	0x05750007,	/* Padding */
+	0x057412B2,	/* Padding */
 };
 
 const u32 pc_beep_verbs[] = {

From 6185983028edf8b7856de9b5ca9615c2bb3de44e Mon Sep 17 00:00:00 2001
From: Sowmya <sowmya.aralguppe@intel.com>
Date: Thu, 18 Sep 2025 19:07:31 +0530
Subject: [PATCH 2064/3886] soc/intel/pantherlake: Standardize macros for core
 count and SKUs
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

This patch updates macro names and enum values to follow consistent
naming conventions and improve code maintainability. Core count macros
and SKUs are renamed for clarity:
	PTL_U_1_CORE -> PTL_CORE_1
	PTL_U_2_CORE -> PTL_CORE_2
	PTL_H_1_CORE -> PTL_CORE_3
	PTL_H_2_CORE -> PTL_CORE_4
The soc_intel_pantherlake_sku enumeration is updated to use
standardized naming patterns. All references have been updated
accordingly.

Change-Id: Ibd8935715ff78571c0cce8617851da86ea11ded2
Signed-off-by: Sowmya <sowmya.aralguppe@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89266
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Reviewed-by: Usha P <usha.p@intel.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 .../variants/baseboard/fatcat/devicetree.cb   |  6 +--
 .../variants/baseboard/fatcat/ramstage.c      | 22 ++++-----
 .../fatcat/variants/felino/overridetree.cb    |  6 +--
 .../fatcat/variants/kinmen/overridetree.cb    |  4 +-
 .../fatcat/variants/lapis/overridetree.cb     |  6 +--
 .../fatcat/variants/moonstone/overridetree.cb |  4 +-
 .../pantherlake/bootblock/report_platform.c   | 12 ++---
 src/soc/intel/pantherlake/chip.h              | 48 +++++++++----------
 src/soc/intel/pantherlake/chipset_ptl.cb      | 20 ++++----
 9 files changed, 62 insertions(+), 66 deletions(-)

diff --git a/src/mainboard/google/fatcat/variants/baseboard/fatcat/devicetree.cb b/src/mainboard/google/fatcat/variants/baseboard/fatcat/devicetree.cb
index a097ea7142..90091d06f6 100644
--- a/src/mainboard/google/fatcat/variants/baseboard/fatcat/devicetree.cb
+++ b/src/mainboard/google/fatcat/variants/baseboard/fatcat/devicetree.cb
@@ -85,17 +85,17 @@ chip soc/intel/pantherlake
 	register "cep_enable[VR_DOMAIN_GT]" = "true"
 	register "enable_fast_vmode[VR_DOMAIN_SA]" = "true"
 	register "cep_enable[VR_DOMAIN_SA]" = "true"
-	register "fast_vmode_i_trip[PTL_U_1_CORE]" = "{
+	register "fast_vmode_i_trip[PTL_CORE_1]" = "{
 		[VR_DOMAIN_IA] = 63 * 4,
 		[VR_DOMAIN_GT] = 38 * 4,
 		[VR_DOMAIN_SA] = 38 * 4
 	}"
-	register "fast_vmode_i_trip[PTL_U_2_CORE]" = "{
+	register "fast_vmode_i_trip[PTL_CORE_2]" = "{
 		[VR_DOMAIN_IA] = 63 * 4,
 		[VR_DOMAIN_GT] = 38 * 4,
 		[VR_DOMAIN_SA] = 38 * 4
 	}"
-	register "fast_vmode_i_trip[PTL_H_1_CORE]" = "{
+	register "fast_vmode_i_trip[PTL_CORE_3]" = "{
 		[VR_DOMAIN_IA] = 75 * 4,
 		[VR_DOMAIN_GT] = 75 * 4,
 		[VR_DOMAIN_SA] = 38 * 4
diff --git a/src/mainboard/google/fatcat/variants/baseboard/fatcat/ramstage.c b/src/mainboard/google/fatcat/variants/baseboard/fatcat/ramstage.c
index f83d9bdd48..224dda7443 100644
--- a/src/mainboard/google/fatcat/variants/baseboard/fatcat/ramstage.c
+++ b/src/mainboard/google/fatcat/variants/baseboard/fatcat/ramstage.c
@@ -25,67 +25,67 @@ const struct cpu_tdp_power_limits power_optimized_limits[] = {
 	{
 		.mch_id = PCI_DID_INTEL_PTL_H_ID_1,
 		.cpu_tdp = TDP_25W,
-		.power_limits_index = PTL_H_1_CORE,
+		.power_limits_index = PTL_CORE_3,
 		COMMON_PTL_H_POWER_LIMITS
 	},
 	{
 		.mch_id = PCI_DID_INTEL_PTL_H_ID_2,
 		.cpu_tdp = TDP_25W,
-		.power_limits_index = PTL_H_1_CORE,
+		.power_limits_index = PTL_CORE_3,
 		COMMON_PTL_H_POWER_LIMITS
 	},
 	{
 		.mch_id = PCI_DID_INTEL_PTL_H_ID_3,
 		.cpu_tdp = TDP_25W,
-		.power_limits_index = PTL_H_2_CORE,
+		.power_limits_index = PTL_CORE_4,
 		COMMON_PTL_H_POWER_LIMITS
 	},
 	{
 		.mch_id = PCI_DID_INTEL_PTL_H_ID_4,
 		.cpu_tdp = TDP_25W,
-		.power_limits_index = PTL_H_2_CORE,
+		.power_limits_index = PTL_CORE_4,
 		COMMON_PTL_H_POWER_LIMITS
 	},
 	{
 		.mch_id = PCI_DID_INTEL_PTL_H_ID_5,
 		.cpu_tdp = TDP_25W,
-		.power_limits_index = PTL_H_2_CORE,
+		.power_limits_index = PTL_CORE_4,
 		COMMON_PTL_H_POWER_LIMITS
 	},
 	{
 		.mch_id = PCI_DID_INTEL_PTL_H_ID_6,
 		.cpu_tdp = TDP_25W,
-		.power_limits_index = PTL_H_2_CORE,
+		.power_limits_index = PTL_CORE_4,
 		COMMON_PTL_H_POWER_LIMITS
 	},
 	{
 		.mch_id = PCI_DID_INTEL_PTL_H_ID_7,
 		.cpu_tdp = TDP_25W,
-		.power_limits_index = PTL_H_2_CORE,
+		.power_limits_index = PTL_CORE_4,
 		COMMON_PTL_H_POWER_LIMITS
 	},
 	{
 		.mch_id = PCI_DID_INTEL_PTL_H_ID_8,
 		.cpu_tdp = TDP_25W,
-		.power_limits_index = PTL_H_2_CORE,
+		.power_limits_index = PTL_CORE_4,
 		COMMON_PTL_H_POWER_LIMITS
 	},
 	{
 		.mch_id = PCI_DID_INTEL_PTL_U_ID_1,
 		.cpu_tdp = TDP_15W,
-		.power_limits_index = PTL_U_1_CORE,
+		.power_limits_index = PTL_CORE_1,
 		COMMON_PTL_U_POWER_LIMITS
 	},
 	{
 		.mch_id = PCI_DID_INTEL_PTL_U_ID_2,
 		.cpu_tdp = TDP_15W,
-		.power_limits_index = PTL_U_2_CORE,
+		.power_limits_index = PTL_CORE_2,
 		COMMON_PTL_U_POWER_LIMITS
 	},
 	{
 		.mch_id = PCI_DID_INTEL_PTL_U_ID_3,
 		.cpu_tdp = TDP_15W,
-		.power_limits_index = PTL_U_2_CORE,
+		.power_limits_index = PTL_CORE_2,
 		COMMON_PTL_U_POWER_LIMITS
 	},
 };
diff --git a/src/mainboard/google/fatcat/variants/felino/overridetree.cb b/src/mainboard/google/fatcat/variants/felino/overridetree.cb
index d2bbc80767..7e8c97268c 100644
--- a/src/mainboard/google/fatcat/variants/felino/overridetree.cb
+++ b/src/mainboard/google/fatcat/variants/felino/overridetree.cb
@@ -43,17 +43,17 @@ end
 
 chip soc/intel/pantherlake
 
-	register "power_limits_config[PTL_U_1_CORE]" = "{
+	register "power_limits_config[PTL_CORE_1]" = "{
 		.tdp_pl1_override = 15,
 		.tdp_pl2_override = 25,
 	}"
 
-	register "power_limits_config[PTL_H_1_CORE]" = "{
+	register "power_limits_config[PTL_CORE_3]" = "{
 		.tdp_pl1_override = 25,
 		.tdp_pl2_override = 25,
 	}"
 
-	register "power_limits_config[PTL_H_2_CORE]" = "{
+	register "power_limits_config[PTL_CORE_4]" = "{
 		.tdp_pl1_override = 25,
 		.tdp_pl2_override = 25,
 	}"
diff --git a/src/mainboard/google/fatcat/variants/kinmen/overridetree.cb b/src/mainboard/google/fatcat/variants/kinmen/overridetree.cb
index b06207f9ed..c1ed2a9400 100644
--- a/src/mainboard/google/fatcat/variants/kinmen/overridetree.cb
+++ b/src/mainboard/google/fatcat/variants/kinmen/overridetree.cb
@@ -23,13 +23,13 @@ chip soc/intel/pantherlake
 	# The initial version temporarily uses the PTL-H,
 	# but the thermal design is based on the PTL-U.
 	# Apply PTL-U's thermal settings here to avoid thermal issues.
-	register "power_limits_config[PTL_H_1_CORE]" = "{
+	register "power_limits_config[PTL_CORE_3]" = "{
 		.tdp_pl1_override = 15,
 		.tdp_pl2_override = 55,
 		.tdp_pl4 = 152,
 	}"
 
-	register "power_limits_config[PTL_H_2_CORE]" = "{
+	register "power_limits_config[PTL_CORE_4]" = "{
 		.tdp_pl1_override = 15,
 		.tdp_pl2_override = 55,
 		.tdp_pl4 = 152,
diff --git a/src/mainboard/google/fatcat/variants/lapis/overridetree.cb b/src/mainboard/google/fatcat/variants/lapis/overridetree.cb
index 3231689c82..cf2ad628fa 100644
--- a/src/mainboard/google/fatcat/variants/lapis/overridetree.cb
+++ b/src/mainboard/google/fatcat/variants/lapis/overridetree.cb
@@ -1,16 +1,16 @@
 chip soc/intel/pantherlake
 
-	register "power_limits_config[PTL_U_1_CORE]" = "{
+	register "power_limits_config[PTL_CORE_1]" = "{
 		.tdp_pl1_override = 15,
 		.tdp_pl2_override = 25,
 	}"
 
-	register "power_limits_config[PTL_H_1_CORE]" = "{
+	register "power_limits_config[PTL_CORE_3]" = "{
 		.tdp_pl1_override = 25,
 		.tdp_pl2_override = 25,
 	}"
 
-	register "power_limits_config[PTL_H_2_CORE]" = "{
+	register "power_limits_config[PTL_CORE_4]" = "{
 		.tdp_pl1_override = 25,
 		.tdp_pl2_override = 25,
 	}"
diff --git a/src/mainboard/google/fatcat/variants/moonstone/overridetree.cb b/src/mainboard/google/fatcat/variants/moonstone/overridetree.cb
index b06207f9ed..c1ed2a9400 100644
--- a/src/mainboard/google/fatcat/variants/moonstone/overridetree.cb
+++ b/src/mainboard/google/fatcat/variants/moonstone/overridetree.cb
@@ -23,13 +23,13 @@ chip soc/intel/pantherlake
 	# The initial version temporarily uses the PTL-H,
 	# but the thermal design is based on the PTL-U.
 	# Apply PTL-U's thermal settings here to avoid thermal issues.
-	register "power_limits_config[PTL_H_1_CORE]" = "{
+	register "power_limits_config[PTL_CORE_3]" = "{
 		.tdp_pl1_override = 15,
 		.tdp_pl2_override = 55,
 		.tdp_pl4 = 152,
 	}"
 
-	register "power_limits_config[PTL_H_2_CORE]" = "{
+	register "power_limits_config[PTL_CORE_4]" = "{
 		.tdp_pl1_override = 15,
 		.tdp_pl2_override = 55,
 		.tdp_pl4 = 152,
diff --git a/src/soc/intel/pantherlake/bootblock/report_platform.c b/src/soc/intel/pantherlake/bootblock/report_platform.c
index 871d19306f..540358238d 100644
--- a/src/soc/intel/pantherlake/bootblock/report_platform.c
+++ b/src/soc/intel/pantherlake/bootblock/report_platform.c
@@ -54,9 +54,9 @@ static struct {
 	const char *name;
 } pch_table[] = {
 	{ PCI_DID_INTEL_PTL_U_H_ESPI_0, "Pantherlake SOC-UH" },
-	{ PCI_DID_INTEL_PTL_U_H_ESPI_1, "Pantherlake SOC-UH SuperSKU" },
-	{ PCI_DID_INTEL_PTL_U_H_ESPI_2, "Pantherlake SOC-UH Premium" },
-	{ PCI_DID_INTEL_PTL_U_H_ESPI_3, "Pantherlake SOC-UH Base" },
+	{ PCI_DID_INTEL_PTL_U_H_ESPI_1, "Pantherlake SOC-UH" },
+	{ PCI_DID_INTEL_PTL_U_H_ESPI_2, "Pantherlake SOC-UH" },
+	{ PCI_DID_INTEL_PTL_U_H_ESPI_3, "Pantherlake SOC-UH" },
 	{ PCI_DID_INTEL_PTL_U_H_ESPI_4, "Pantherlake SOC-UH" },
 	{ PCI_DID_INTEL_PTL_U_H_ESPI_5, "Pantherlake SOC-UH" },
 	{ PCI_DID_INTEL_PTL_U_H_ESPI_6, "Pantherlake SOC-UH" },
@@ -86,9 +86,9 @@ static struct {
 	{ PCI_DID_INTEL_PTL_U_H_ESPI_30, "Pantherlake SOC-UH" },
 	{ PCI_DID_INTEL_PTL_U_H_ESPI_31, "Pantherlake SOC-UH" },
 	{ PCI_DID_INTEL_PTL_H_ESPI_0, "Pantherlake SOC-H" },
-	{ PCI_DID_INTEL_PTL_H_ESPI_1, "Pantherlake SOC-H SuperSKU" },
-	{ PCI_DID_INTEL_PTL_H_ESPI_2, "Pantherlake SOC-H Premium" },
-	{ PCI_DID_INTEL_PTL_H_ESPI_3, "Pantherlake SOC-H Base" },
+	{ PCI_DID_INTEL_PTL_H_ESPI_1, "Pantherlake SOC-H" },
+	{ PCI_DID_INTEL_PTL_H_ESPI_2, "Pantherlake SOC-H" },
+	{ PCI_DID_INTEL_PTL_H_ESPI_3, "Pantherlake SOC-H" },
 	{ PCI_DID_INTEL_PTL_H_ESPI_4, "Pantherlake SOC-H" },
 	{ PCI_DID_INTEL_PTL_H_ESPI_5, "Pantherlake SOC-H" },
 	{ PCI_DID_INTEL_PTL_H_ESPI_6, "Pantherlake SOC-H" },
diff --git a/src/soc/intel/pantherlake/chip.h b/src/soc/intel/pantherlake/chip.h
index c837ec6da9..cb37155adb 100644
--- a/src/soc/intel/pantherlake/chip.h
+++ b/src/soc/intel/pantherlake/chip.h
@@ -53,11 +53,11 @@ enum soc_intel_pantherlake_sagv_gears {
 };
 
 enum soc_intel_pantherlake_power_limits {
-	PTL_U_1_CORE,
-	PTL_U_2_CORE,
-	PTL_H_1_CORE,
-	PTL_H_2_CORE,
-	PTL_H_3_CORE,
+	PTL_CORE_1,
+	PTL_CORE_2,
+	PTL_CORE_3,
+	PTL_CORE_4,
+	PTL_CORE_5,
 	WCL_CORE,
 	PTL_POWER_LIMITS_COUNT,
 };
@@ -70,11 +70,11 @@ enum soc_intel_pantherlake_cpu_tdps {
 };
 
 enum soc_intel_pantherlake_sku {
-	PTL_H404_SKU,
-	PTL_H12XE_SKU,
-	PTL_H484_SKU,
-	PTL_H4XE_SKU,
-	PTL_H204_SKU,
+	PTL_SKU_1,
+	PTL_SKU_2,
+	PTL_SKU_3,
+	PTL_SKU_4,
+	PTL_SKU_5,
 	WCL_SKU_1,
 	WCL_SKU_2,
 	WCL_SKU_3,
@@ -90,20 +90,20 @@ static const struct soc_intel_pantherlake_power_map {
 	enum soc_intel_pantherlake_cpu_tdps cpu_tdp;
 	enum soc_intel_pantherlake_sku sku;
 } cpuid_to_ptl[] = {
-	{ PCI_DID_INTEL_PTL_U_ID_1, PTL_U_1_CORE, TDP_15W, PTL_H404_SKU },
-	{ PCI_DID_INTEL_PTL_U_ID_1, PTL_U_1_CORE, TDP_25W, PTL_H404_SKU },
-	{ PCI_DID_INTEL_PTL_U_ID_2, PTL_U_2_CORE, TDP_15W, PTL_H204_SKU },
-	{ PCI_DID_INTEL_PTL_U_ID_2, PTL_U_2_CORE, TDP_25W, PTL_H204_SKU },
-	{ PCI_DID_INTEL_PTL_U_ID_3, PTL_U_2_CORE, TDP_15W, PTL_H404_SKU },
-	{ PCI_DID_INTEL_PTL_U_ID_3, PTL_U_2_CORE, TDP_25W, PTL_H404_SKU },
-	{ PCI_DID_INTEL_PTL_H_ID_1, PTL_H_1_CORE, TDP_25W, PTL_H12XE_SKU },
-	{ PCI_DID_INTEL_PTL_H_ID_2, PTL_H_1_CORE, TDP_25W, PTL_H484_SKU },
-	{ PCI_DID_INTEL_PTL_H_ID_3, PTL_H_2_CORE, TDP_25W, PTL_H12XE_SKU },
-	{ PCI_DID_INTEL_PTL_H_ID_4, PTL_H_2_CORE, TDP_25W, PTL_H12XE_SKU },
-	{ PCI_DID_INTEL_PTL_H_ID_5, PTL_H_2_CORE, TDP_25W, PTL_H4XE_SKU },
-	{ PCI_DID_INTEL_PTL_H_ID_6, PTL_H_2_CORE, TDP_25W, PTL_H4XE_SKU },
-	{ PCI_DID_INTEL_PTL_H_ID_7, PTL_H_2_CORE, TDP_25W, PTL_H4XE_SKU },
-	{ PCI_DID_INTEL_PTL_H_ID_8, PTL_H_2_CORE, TDP_25W, PTL_H12XE_SKU },
+	{ PCI_DID_INTEL_PTL_U_ID_1, PTL_CORE_1, TDP_15W, PTL_SKU_1 },
+	{ PCI_DID_INTEL_PTL_U_ID_1, PTL_CORE_1, TDP_25W, PTL_SKU_1 },
+	{ PCI_DID_INTEL_PTL_U_ID_2, PTL_CORE_2, TDP_15W, PTL_SKU_5 },
+	{ PCI_DID_INTEL_PTL_U_ID_2, PTL_CORE_2, TDP_25W, PTL_SKU_5 },
+	{ PCI_DID_INTEL_PTL_U_ID_3, PTL_CORE_2, TDP_15W, PTL_SKU_1 },
+	{ PCI_DID_INTEL_PTL_U_ID_3, PTL_CORE_2, TDP_25W, PTL_SKU_1 },
+	{ PCI_DID_INTEL_PTL_H_ID_1, PTL_CORE_3, TDP_25W, PTL_SKU_2 },
+	{ PCI_DID_INTEL_PTL_H_ID_2, PTL_CORE_3, TDP_25W, PTL_SKU_3 },
+	{ PCI_DID_INTEL_PTL_H_ID_3, PTL_CORE_4, TDP_25W, PTL_SKU_2 },
+	{ PCI_DID_INTEL_PTL_H_ID_4, PTL_CORE_4, TDP_25W, PTL_SKU_2 },
+	{ PCI_DID_INTEL_PTL_H_ID_5, PTL_CORE_4, TDP_25W, PTL_SKU_4 },
+	{ PCI_DID_INTEL_PTL_H_ID_6, PTL_CORE_4, TDP_25W, PTL_SKU_4 },
+	{ PCI_DID_INTEL_PTL_H_ID_7, PTL_CORE_4, TDP_25W, PTL_SKU_4 },
+	{ PCI_DID_INTEL_PTL_H_ID_8, PTL_CORE_4, TDP_25W, PTL_SKU_2 },
 	{ PCI_DID_INTEL_WCL_ID_1, WCL_CORE, TDP_15W, WCL_SKU_1},
 	{ PCI_DID_INTEL_WCL_ID_2, WCL_CORE, TDP_15W, WCL_SKU_2},
 	{ PCI_DID_INTEL_WCL_ID_3, WCL_CORE, TDP_15W, WCL_SKU_3},
diff --git a/src/soc/intel/pantherlake/chipset_ptl.cb b/src/soc/intel/pantherlake/chipset_ptl.cb
index e7cac8dd64..3ab98a260c 100644
--- a/src/soc/intel/pantherlake/chipset_ptl.cb
+++ b/src/soc/intel/pantherlake/chipset_ptl.cb
@@ -2,48 +2,44 @@ chip soc/intel/pantherlake
 
 	device cpu_cluster 0 on end
 
-	# H404
-	register "power_limits_config[PTL_U_1_CORE]" = "{
+	register "power_limits_config[PTL_CORE_1]" = "{
 		.tdp_pl1_override = 15,
 		.tdp_pl2_override = 55,
 		.tdp_pl4 = 163,
 		.tdp_pl4_fastvmode = 150,
 	}"
-	register "thermal_design_current[PTL_H404_SKU]" = "{
+	register "thermal_design_current[PTL_SKU_1]" = "{
 		[VR_DOMAIN_IA] = 34 * 8,
 		[VR_DOMAIN_GT] = 23 * 8
 	}"
 
-	# H204
-	register "power_limits_config[PTL_U_2_CORE]" = "{
+	register "power_limits_config[PTL_CORE_2]" = "{
 		.tdp_pl1_override = 15,
 		.tdp_pl2_override = 45,
 		.tdp_pl4 = 105,
 		.tdp_pl4_fastvmode = 95,
 	}"
-	register "thermal_design_current[PTL_H204_SKU]" = "{
+	register "thermal_design_current[PTL_SKU_5]" = "{
 		[VR_DOMAIN_IA] = 23 * 8,
 		[VR_DOMAIN_GT] = 23 * 8
 	}"
 
-	# H12Xe and H484
-	register "power_limits_config[PTL_H_1_CORE]" = "{
+	register "power_limits_config[PTL_CORE_3]" = "{
 		.tdp_pl1_override = 25,
 		.tdp_pl2_override = 64,
 		.tdp_pl4 = 175,
 		.tdp_pl4_fastvmode = 160,
 	}"
-	register "thermal_design_current[PTL_H12XE_SKU]" = "{
+	register "thermal_design_current[PTL_SKU_2]" = "{
 		[VR_DOMAIN_IA] = 39 * 8,
 		[VR_DOMAIN_GT] = 44 * 8
 	}"
-	register "thermal_design_current[PTL_H484_SKU]" = "{
+	register "thermal_design_current[PTL_SKU_3]" = "{
 		[VR_DOMAIN_IA] = 39 * 8,
 		[VR_DOMAIN_GT] = 23 * 8
 	}"
 
-	# H4XE
-	register "power_limits_config[PTL_H_2_CORE]" = "{
+	register "power_limits_config[PTL_CORE_4]" = "{
 		.tdp_pl1_override = 25,
 		.tdp_pl2_override = 64,
 		.tdp_pl4 = 154,

From c77d3d67cfd4d4081822568293d4c92057eb9027 Mon Sep 17 00:00:00 2001
From: Yang Wu <wuyang5@huaqin.corp-partner.google.com>
Date: Tue, 16 Sep 2025 20:31:16 +0800
Subject: [PATCH 2065/3886] mb/google/skywalker: Report panel ID and SKU ID for
 padme
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

The panel id is sampled with AUX_IN4 (PANEL_ID_LOW_CHANNEL) and AUX_IN5
(PANEL_ID_HIGH_CHANNEL). Introduce 3 voltage thresholds to distinguish
different panels:

  - v < 0.5V        -> id = 0
  - 0.5V ≤ v < 1.0V -> id = 1
  - v ≥ 1.0V        -> id = 2

BUG=b:433405205
TEST=Tested by booting with the payload and confirming the kernel get
the correct skuid.

Change-Id: I590a19b6cade3cae15a58a9b3541ff471e038435
Signed-off-by: Yang Wu <wuyang5@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89217
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
---
 src/mainboard/google/skywalker/boardid.c | 76 +++++++++++++++++++++---
 src/mainboard/google/skywalker/panel.h   |  8 +++
 2 files changed, 76 insertions(+), 8 deletions(-)
 create mode 100644 src/mainboard/google/skywalker/panel.h

diff --git a/src/mainboard/google/skywalker/boardid.c b/src/mainboard/google/skywalker/boardid.c
index 437f64e302..e2ba9e13d4 100644
--- a/src/mainboard/google/skywalker/boardid.c
+++ b/src/mainboard/google/skywalker/boardid.c
@@ -6,13 +6,18 @@
 #include <ec/google/chromeec/ec.h>
 #include <soc/auxadc_common.h>
 
+#include "panel.h"
 #include "storage.h"
 
 #define ADC_LEVELS 8
+#define PANEL_ADC_LEVELS 3
 
 enum {
 	/* STORAGE IDs */
 	STORAGE_ID_CHANNEL = 2,
+	/* SKU IDs */
+	PANEL_ID_LOW_CHANNEL = 4,
+	PANEL_ID_HIGH_CHANNEL = 5,
 };
 
 static const unsigned int storage_voltages[ADC_LEVELS] = {
@@ -27,8 +32,17 @@ static const unsigned int storage_voltages[ADC_LEVELS] = {
 	[7] = 1342600,
 };
 
+static const unsigned int panel_voltages[PANEL_ADC_LEVELS] = {
+	/* ID : Voltage (unit: uV) */
+	[0] =       0,
+	[1] =  500000,
+	[2] = 1000000,
+};
+
 static const unsigned int *adc_voltages[] = {
 	[STORAGE_ID_CHANNEL] = storage_voltages,
+	[PANEL_ID_LOW_CHANNEL] = panel_voltages,
+	[PANEL_ID_HIGH_CHANNEL] = panel_voltages,
 };
 
 static uint32_t get_adc_index(unsigned int channel)
@@ -62,20 +76,66 @@ uint32_t storage_id(void)
 	return cached_storage_id;
 }
 
+static uint32_t cal_panel_id(unsigned int channel)
+{
+	unsigned int value = auxadc_get_voltage_uv(channel);
+	const unsigned int *voltages;
+
+	assert(channel < ARRAY_SIZE(adc_voltages));
+	voltages = adc_voltages[channel];
+	assert(voltages);
+
+	uint32_t id;
+
+	for (id = 0; id < PANEL_ADC_LEVELS - 1; id++) {
+		if (value < voltages[id + 1]) {
+			printk(BIOS_DEBUG, "ADC[%u]: Raw value=%u ID=%u\n",
+			       channel, value, id);
+			return id;
+		}
+	}
+	printk(BIOS_DEBUG, "ADC[%u]: Raw value=%u ID=%u\n", channel, value, id);
+	return PANEL_ADC_LEVELS - 1;
+}
+
+uint8_t panel_id(void)
+{
+	static uint32_t cached_panel_id = BOARD_ID_INIT;
+
+	if (cached_panel_id == BOARD_ID_INIT) {
+		uint32_t high_id = cal_panel_id(PANEL_ID_HIGH_CHANNEL);
+		uint32_t low_id  = cal_panel_id(PANEL_ID_LOW_CHANNEL);
+		cached_panel_id = (high_id & 0xF) << 4 | (low_id & 0xF);
+	}
+
+	return cached_panel_id;
+}
+
 uint32_t sku_id(void)
 {
 	static uint32_t cached_sku_code = BOARD_ID_INIT;
 
-	if (cached_sku_code == BOARD_ID_INIT) {
-		cached_sku_code = google_chromeec_get_board_sku();
+	if (cached_sku_code != BOARD_ID_INIT)
+		return cached_sku_code;
 
-		if (cached_sku_code == CROS_SKU_UNKNOWN ||
-		    cached_sku_code == CROS_SKU_UNPROVISIONED) {
-			printk(BIOS_WARNING, "Failed to get SKU code from EC\n");
-			cached_sku_code = CROS_SKU_UNPROVISIONED;
-		}
-		printk(BIOS_DEBUG, "SKU Code: %#02x\n", cached_sku_code);
+	const uint32_t cbi_sku_id = google_chromeec_get_board_sku();
+	const uint32_t panel = panel_id();
+	uint32_t effective_sku = cbi_sku_id;
+
+	if (cbi_sku_id == CROS_SKU_UNKNOWN ||
+	    cbi_sku_id == CROS_SKU_UNPROVISIONED) {
+		printk(BIOS_WARNING, "Failed to get SKU code from EC\n");
+		effective_sku = CROS_SKU_UNPROVISIONED;
 	}
+	if (CONFIG(BOARD_GOOGLE_PADME)) {
+		/* Reserve last 8 bits to report PANEL_IDs */
+		cached_sku_code = (effective_sku & 0xFFFFFF00) | (panel_id() & 0xFF);
+	} else {
+		cached_sku_code = effective_sku;
+	}
+	printk(BIOS_DEBUG,
+	       "CBI SKU ID: %#02x, panel ID: %#02x, cached SKU code: %#02x\n",
+	       cbi_sku_id, panel, cached_sku_code);
 
 	return cached_sku_code;
 }
diff --git a/src/mainboard/google/skywalker/panel.h b/src/mainboard/google/skywalker/panel.h
new file mode 100644
index 0000000000..6a969b323e
--- /dev/null
+++ b/src/mainboard/google/skywalker/panel.h
@@ -0,0 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef __MAINBOARD_GOOGLE_SKYWALKER_PANEL_H__
+#define __MAINBOARD_GOOGLE_SKYWALKER_PANEL_H__
+
+uint8_t panel_id(void);
+
+#endif

From 7acc99c3d265ef4b95487b6263700d3bfedd76c6 Mon Sep 17 00:00:00 2001
From: Patrick Rudolph <patrick.rudolph@9elements.com>
Date: Sat, 20 Sep 2025 15:00:06 +0200
Subject: [PATCH 2066/3886] acpi/acpi_pm: Fix compilation without SMBIOS

smbios_mainboard_enclosure_type() is not linked when SMBIOS
is disabled. Fixes a linker error when the user disabled SMBIOS
table generation in Kconfig.

Change-Id: Ic3e70c658d01a839eb37f0862f31ee9f65a84300
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89280
Reviewed-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/acpi/acpi_pm.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/src/acpi/acpi_pm.c b/src/acpi/acpi_pm.c
index 722d8f6b62..afa9a313d6 100644
--- a/src/acpi/acpi_pm.c
+++ b/src/acpi/acpi_pm.c
@@ -21,6 +21,9 @@ void __weak mainboard_suspend_resume(void)
 /* Default mapping to ACPI FADT preferred_pm_profile field. */
 uint8_t acpi_get_preferred_pm_profile(void)
 {
+	if (!CONFIG(GENERATE_SMBIOS_TABLES))
+		return PM_UNSPECIFIED;
+
 	switch (smbios_mainboard_enclosure_type()) {
 	case SMBIOS_ENCLOSURE_LAPTOP:
 	case SMBIOS_ENCLOSURE_CONVERTIBLE:

From f4110cebf6a249844c9648356df55f0549a56f6d Mon Sep 17 00:00:00 2001
From: Appukuttan V K <appukuttan.vk@intel.com>
Date: Fri, 19 Sep 2025 13:24:54 +0530
Subject: [PATCH 2067/3886] spd/lp5: Add SPD for H58GE6AK8BX104

Add  H58GE6AK8BX104 in the memory_parts.json and re-generate
the SPD.

BUG=b:445211686
TEST=util/spd_tools/bin/spd_gen spd/lp5/memory_parts.json lp5

Change-Id: I4bf1d0fc3325ec2d4247a0263a44a81934a3a90e
Signed-off-by: Appukuttan V K <appukuttan.vk@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89267
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
---
 spd/lp5/memory_parts.json                     | 25 +++++++++++----
 .../set-0/parts_spd_manifest.generated.txt    |  1 +
 spd/lp5/set-0/spd-12.hex                      | 32 +++++++++++++++++++
 .../set-1/parts_spd_manifest.generated.txt    |  1 +
 spd/lp5/set-1/spd-12.hex                      | 32 +++++++++++++++++++
 5 files changed, 84 insertions(+), 7 deletions(-)
 create mode 100644 spd/lp5/set-0/spd-12.hex
 create mode 100644 spd/lp5/set-1/spd-12.hex

diff --git a/spd/lp5/memory_parts.json b/spd/lp5/memory_parts.json
index a4a74a4391..6c5e127bdf 100644
--- a/spd/lp5/memory_parts.json
+++ b/spd/lp5/memory_parts.json
@@ -339,9 +339,9 @@
                 "speedMbps": 8533,
                 "lp5x": true
             }
-	},
-	{
-	    "name": "MT62F1G32D2DS-031 WT:C",
+    },
+    {
+        "name": "MT62F1G32D2DS-031 WT:C",
             "attribs": {
                   "densityPerDieGb": 16,
                   "diesPerPackage": 2,
@@ -349,9 +349,9 @@
                   "ranksPerChannel": 1,
                   "speedMbps": 6400
              }
-	},
-	{
-	    "name": "MT62F2G32D4DS-031 WT:C",
+    },
+    {
+        "name": "MT62F2G32D4DS-031 WT:C",
             "attribs": {
                   "densityPerDieGb": 16,
                   "diesPerPackage": 4,
@@ -359,6 +359,17 @@
                   "ranksPerChannel": 2,
                   "speedMbps": 6400
              }
-	}
+    },
+    {
+        "name":  "H58GE6AK8BX104",
+        "attribs": {
+            "densityPerDieGb": 12,
+            "diesPerPackage": 4,
+            "bitWidthPerChannel": 16,
+            "ranksPerChannel": 2,
+            "speedMbps": 8533,
+            "lp5x": true
+        }
+    }
     ]
 }
diff --git a/spd/lp5/set-0/parts_spd_manifest.generated.txt b/spd/lp5/set-0/parts_spd_manifest.generated.txt
index d0aa4078c0..7e2ab8d761 100644
--- a/spd/lp5/set-0/parts_spd_manifest.generated.txt
+++ b/spd/lp5/set-0/parts_spd_manifest.generated.txt
@@ -35,3 +35,4 @@ MT62F2G32D4DS-023 WT:C,spd-10.hex
 MT62F512M32D1DS-023 WT:E,spd-11.hex
 MT62F1G32D2DS-031 WT:C,spd-3.hex
 MT62F2G32D4DS-031 WT:C,spd-6.hex
+H58GE6AK8BX104,spd-12.hex
diff --git a/spd/lp5/set-0/spd-12.hex b/spd/lp5/set-0/spd-12.hex
new file mode 100644
index 0000000000..4a9edfe471
--- /dev/null
+++ b/spd/lp5/set-0/spd-12.hex
@@ -0,0 +1,32 @@
+23 10 15 0E 18 22 B5 08 00 00 00 00 0A 01 00 00
+00 00 08 00 00 00 00 00 AD 00 90 A8 90 C0 08 60
+04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 B6 00 C1 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 20 20 20 20 20 20 20
+20 20 20 20 20 20 20 20 20 20 20 20 20 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
diff --git a/spd/lp5/set-1/parts_spd_manifest.generated.txt b/spd/lp5/set-1/parts_spd_manifest.generated.txt
index d0aa4078c0..7e2ab8d761 100644
--- a/spd/lp5/set-1/parts_spd_manifest.generated.txt
+++ b/spd/lp5/set-1/parts_spd_manifest.generated.txt
@@ -35,3 +35,4 @@ MT62F2G32D4DS-023 WT:C,spd-10.hex
 MT62F512M32D1DS-023 WT:E,spd-11.hex
 MT62F1G32D2DS-031 WT:C,spd-3.hex
 MT62F2G32D4DS-031 WT:C,spd-6.hex
+H58GE6AK8BX104,spd-12.hex
diff --git a/spd/lp5/set-1/spd-12.hex b/spd/lp5/set-1/spd-12.hex
new file mode 100644
index 0000000000..3b41672adb
--- /dev/null
+++ b/spd/lp5/set-1/spd-12.hex
@@ -0,0 +1,32 @@
+23 11 13 0E 88 21 B5 18 00 40 00 00 0A 02 00 00
+00 00 02 00 00 00 00 00 2C 00 90 A8 90 C0 08 60
+04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 8A 00 F0 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 20 20 20 20 20 20 20
+20 20 20 20 20 20 20 20 20 20 20 20 20 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00

From d8a3f2aedd578d54b2c2aaad459a39227928fb43 Mon Sep 17 00:00:00 2001
From: Appukuttan V K <appukuttan.vk@intel.com>
Date: Fri, 19 Sep 2025 13:29:03 +0530
Subject: [PATCH 2068/3886] mb/goog/ocelot/var/ocelot: add H58GE6AK8BX104
 memory option

Add H58GE6AK8BX104 memory part as DRAM ID 3.

BUG=b:445211686
TEST=None

Change-Id: I10876384f67d9201b14dc19213cfc77d62213070
Signed-off-by: Appukuttan V K <appukuttan.vk@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89268
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Avi Uday <aviuday@google.com>
---
 src/mainboard/google/ocelot/variants/ocelot/memory/Makefile.mk | 3 ++-
 .../google/ocelot/variants/ocelot/memory/dram_id.generated.txt | 3 ++-
 .../google/ocelot/variants/ocelot/memory/mem_parts_used.txt    | 1 +
 3 files changed, 5 insertions(+), 2 deletions(-)

diff --git a/src/mainboard/google/ocelot/variants/ocelot/memory/Makefile.mk b/src/mainboard/google/ocelot/variants/ocelot/memory/Makefile.mk
index 9184097b25..2f9613f7b5 100644
--- a/src/mainboard/google/ocelot/variants/ocelot/memory/Makefile.mk
+++ b/src/mainboard/google/ocelot/variants/ocelot/memory/Makefile.mk
@@ -1,9 +1,10 @@
 # SPDX-License-Identifier: GPL-2.0-or-later
 # This is an auto-generated file. Do not edit!!
 # Generated by:
-# ./util/spd_tools/src/part_id_gen/part_id_gen PTL lp5 src/mainboard/google/ocelot/variants/ocelot/memory src/mainboard/google/ocelot/variants/ocelot/memory/mem_parts_used.txt
+# ./util/spd_tools/bin/part_id_gen PTL lp5 src/mainboard/google/ocelot/variants/ocelot/memory src/mainboard/google/ocelot/variants/ocelot/memory/mem_parts_used.txt
 
 SPD_SOURCES =
 SPD_SOURCES += spd/lp5/set-0/spd-11.hex      # ID = 0(0b0000)  Parts = H58G56BK8BX068
 SPD_SOURCES += spd/lp5/set-0/spd-8.hex      # ID = 1(0b0001)  Parts = H58G66BK7BX067
 SPD_SOURCES += spd/lp5/set-0/spd-10.hex      # ID = 2(0b0010)  Parts = H58G66BK8BX067
+SPD_SOURCES += spd/lp5/set-0/spd-12.hex      # ID = 3(0b0011)  Parts = H58GE6AK8BX104
diff --git a/src/mainboard/google/ocelot/variants/ocelot/memory/dram_id.generated.txt b/src/mainboard/google/ocelot/variants/ocelot/memory/dram_id.generated.txt
index e86908c913..7cc94836cf 100644
--- a/src/mainboard/google/ocelot/variants/ocelot/memory/dram_id.generated.txt
+++ b/src/mainboard/google/ocelot/variants/ocelot/memory/dram_id.generated.txt
@@ -1,9 +1,10 @@
 # SPDX-License-Identifier: GPL-2.0-or-later
 # This is an auto-generated file. Do not edit!!
 # Generated by:
-# ./util/spd_tools/src/part_id_gen/part_id_gen PTL lp5 src/mainboard/google/ocelot/variants/ocelot/memory src/mainboard/google/ocelot/variants/ocelot/memory/mem_parts_used.txt
+# ./util/spd_tools/bin/part_id_gen PTL lp5 src/mainboard/google/ocelot/variants/ocelot/memory src/mainboard/google/ocelot/variants/ocelot/memory/mem_parts_used.txt
 
 DRAM Part Name                 ID to assign
 H58G56BK8BX068                 0 (0000)
 H58G66BK7BX067                 1 (0001)
 H58G66BK8BX067                 2 (0010)
+H58GE6AK8BX104                 3 (0011)
diff --git a/src/mainboard/google/ocelot/variants/ocelot/memory/mem_parts_used.txt b/src/mainboard/google/ocelot/variants/ocelot/memory/mem_parts_used.txt
index 951d24f620..9346d22713 100644
--- a/src/mainboard/google/ocelot/variants/ocelot/memory/mem_parts_used.txt
+++ b/src/mainboard/google/ocelot/variants/ocelot/memory/mem_parts_used.txt
@@ -12,3 +12,4 @@
 H58G56BK8BX068
 H58G66BK7BX067
 H58G66BK8BX067
+H58GE6AK8BX104

From 508c399bc1d4ce87573d042aa4890567ec0ea811 Mon Sep 17 00:00:00 2001
From: Appukuttan V K <appukuttan.vk@intel.com>
Date: Fri, 19 Sep 2025 13:41:27 +0530
Subject: [PATCH 2069/3886] mb/goog/ocelot/var/ocelot: add H58G66CK8BX147
 memory option

Add H58G66CK8BX147 memory part as DRAM ID 2.

BUG=b:446088494
TEST=None

Change-Id: Ice18fd3209b0552be8f8612aaa3ff30ba76c8b83
Signed-off-by: Appukuttan V K <appukuttan.vk@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89269
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Avi Uday <aviuday@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/google/ocelot/variants/ocelot/memory/Makefile.mk  | 2 +-
 .../google/ocelot/variants/ocelot/memory/dram_id.generated.txt  | 1 +
 .../google/ocelot/variants/ocelot/memory/mem_parts_used.txt     | 1 +
 3 files changed, 3 insertions(+), 1 deletion(-)

diff --git a/src/mainboard/google/ocelot/variants/ocelot/memory/Makefile.mk b/src/mainboard/google/ocelot/variants/ocelot/memory/Makefile.mk
index 2f9613f7b5..3712de7a49 100644
--- a/src/mainboard/google/ocelot/variants/ocelot/memory/Makefile.mk
+++ b/src/mainboard/google/ocelot/variants/ocelot/memory/Makefile.mk
@@ -6,5 +6,5 @@
 SPD_SOURCES =
 SPD_SOURCES += spd/lp5/set-0/spd-11.hex      # ID = 0(0b0000)  Parts = H58G56BK8BX068
 SPD_SOURCES += spd/lp5/set-0/spd-8.hex      # ID = 1(0b0001)  Parts = H58G66BK7BX067
-SPD_SOURCES += spd/lp5/set-0/spd-10.hex      # ID = 2(0b0010)  Parts = H58G66BK8BX067
+SPD_SOURCES += spd/lp5/set-0/spd-10.hex      # ID = 2(0b0010)  Parts = H58G66BK8BX067, H58G66CK8BX147
 SPD_SOURCES += spd/lp5/set-0/spd-12.hex      # ID = 3(0b0011)  Parts = H58GE6AK8BX104
diff --git a/src/mainboard/google/ocelot/variants/ocelot/memory/dram_id.generated.txt b/src/mainboard/google/ocelot/variants/ocelot/memory/dram_id.generated.txt
index 7cc94836cf..263b46efc9 100644
--- a/src/mainboard/google/ocelot/variants/ocelot/memory/dram_id.generated.txt
+++ b/src/mainboard/google/ocelot/variants/ocelot/memory/dram_id.generated.txt
@@ -8,3 +8,4 @@ H58G56BK8BX068                 0 (0000)
 H58G66BK7BX067                 1 (0001)
 H58G66BK8BX067                 2 (0010)
 H58GE6AK8BX104                 3 (0011)
+H58G66CK8BX147                 2 (0010)
diff --git a/src/mainboard/google/ocelot/variants/ocelot/memory/mem_parts_used.txt b/src/mainboard/google/ocelot/variants/ocelot/memory/mem_parts_used.txt
index 9346d22713..097cfc1128 100644
--- a/src/mainboard/google/ocelot/variants/ocelot/memory/mem_parts_used.txt
+++ b/src/mainboard/google/ocelot/variants/ocelot/memory/mem_parts_used.txt
@@ -13,3 +13,4 @@ H58G56BK8BX068
 H58G66BK7BX067
 H58G66BK8BX067
 H58GE6AK8BX104
+H58G66CK8BX147

From b3ad2aa3e7087484d532917b8c6b69f81abeb64d Mon Sep 17 00:00:00 2001
From: Varun Upadhyay <varun.upadhyay@intel.com>
Date: Thu, 4 Sep 2025 13:46:04 +0530
Subject: [PATCH 2070/3886] mb/google/ocelot: GPIO config for headphone jack
 detection

This commit updates GPP_F17 (CODEC_INIT_N) configuration to fix an issue with the 3.5mm headphone jack on the I2S codec AIC not detecting headphone plug/unplug events.
Specifically, we need to configure GPP_F17 to have interrupt capability, edge detection to detect plug and unplug events, and power state persistence.

TEST=After booting to OS, plug and unplug a headphone to the I2S codec add-in card, headphone is getting detected.

Change-Id: I263f7e9e2da0440801404dddfcf534b9ea79d470
Signed-off-by: Varun Upadhyay <varun.upadhyay@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89038
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Usha P <usha.p@intel.com>
---
 src/mainboard/google/ocelot/variants/ocelot/gpio.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/mainboard/google/ocelot/variants/ocelot/gpio.c b/src/mainboard/google/ocelot/variants/ocelot/gpio.c
index 41c21a1b39..9da94aff9a 100644
--- a/src/mainboard/google/ocelot/variants/ocelot/gpio.c
+++ b/src/mainboard/google/ocelot/variants/ocelot/gpio.c
@@ -237,8 +237,8 @@ static const struct pad_config gpio_table[] = {
 	PAD_CFG_NF(GPP_F15, NONE, DEEP, NF8),
 	/* GPP_F16:     GPP_F16_GSPI0A_CLK */
 	PAD_CFG_NF(GPP_F16, NONE, DEEP, NF8),
-	/* GPP_F17:     CODEC_IRQ_HDR */
-	PAD_CFG_GPI(GPP_F17, NONE, DEEP),
+	/* GPP_F17:     CODEC_INT_N */
+	PAD_CFG_GPI_INT(GPP_F17, NONE, PLTRST, EDGE_BOTH),
 	/* GPP_F18:     TCH_PAD_INT_N */
 	PAD_CFG_GPI_APIC_DRIVER(GPP_F18, NONE, PLTRST, EDGE_SINGLE, INVERT),
 	/* GPP_F19:     NC */

From ef0c650edf7769107820382d44cbe23adeec196b Mon Sep 17 00:00:00 2001
From: Jeremy Compostella <jeremy.compostella@intel.com>
Date: Fri, 22 Aug 2025 16:52:08 -0700
Subject: [PATCH 2071/3886] soc/intel/cmn/blk/fast_spi: Cancel DMA transfer
 before locking

This commit addresses a potential low power state over-consumption
issue. This issue could arise if SPI DMA has been locked down while a
transfer was still marked as active, typically if a SPI DMA transfer
failed and hung.

The fast_spi_dma_lock() function now checks if a DMA transfer is ongoing
and ensures that it is marked as complete before locking the DMA control
register.

Change-Id: I5e08991b2160a43013b129d302c46fc229f2286d
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88913
Reviewed-by: Zhixing Ma <zhixing.ma@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
---
 src/soc/intel/common/block/fast_spi/fast_spi_dma.c | 13 +++++++++++++
 1 file changed, 13 insertions(+)

diff --git a/src/soc/intel/common/block/fast_spi/fast_spi_dma.c b/src/soc/intel/common/block/fast_spi/fast_spi_dma.c
index e4eea9d704..ffb68f05f4 100644
--- a/src/soc/intel/common/block/fast_spi/fast_spi_dma.c
+++ b/src/soc/intel/common/block/fast_spi/fast_spi_dma.c
@@ -516,6 +516,19 @@ static void fast_spi_dma_lock(void *unused)
 	if (control.fields.lock)
 		return;
 
+	/* Ensure that any ongoing DMA transfer is marked as complete before locking. */
+	if (control.fields.start) {
+		union fast_spi_dma_status status = {fast_spi_read(FAST_SPI_DMA_STATUS)};
+		if (!status.fields.complete) {
+			status.data = 0;
+			status.fields.complete = 1;
+			fast_spi_write(FAST_SPI_DMA_STATUS, status.data);
+		}
+
+		control.fields.start = 0;
+		fast_spi_write(FAST_SPI_DMA_CONTROL, control.data);
+	}
+
 	control.fields.lock = 1;
 	fast_spi_write(FAST_SPI_DMA_CONTROL, control.data);
 

From 8953c772cf8c6e28fe81d7e6ffda4c56b67824ca Mon Sep 17 00:00:00 2001
From: Pranava Y N <pranavayn@google.com>
Date: Mon, 22 Sep 2025 18:35:07 +0530
Subject: [PATCH 2072/3886] lib: Fix bad whitespace in
 add_bmp_logo_file_to_cbfs_call

The multi-line `$(eval $(call ...))` for adding the default BMP logo
contained extraneous whitespace. This included a leading space before
`logo.bmp` and, more critically, a newline, tab, and non-breaking
spaces before `CONFIG_BMP_LOGO_FILE_NAME`.

This problematic whitespace was passed as part of the third argument
(`$(3)`) to the `add_bmp_logo_file_to_cbfs` macro. Inside the
macro, the deferred variable expansion `$$($(3))` would fail because it
was searching for a variable name with leading non-breaking spaces.

This resulted in the `logo.bmp-file` variable being set to an empty
string, causing a build failure when the cbfs tool tried to find the
logo file.

This commit collapses the function call onto a single line to remove
all line continuations and problematic whitespace, ensuring the
correct, clean arguments are passed to the macro.

BUG=b:444655145
TEST=Able to verify that 'logo.bmp' is added correctly to the CBFS,
and also verify the FW splash screen visible on redrix device.

Change-Id: Ia91b927dd0248909fc1c75534a7e7b00dab0fc09
Signed-off-by: Pranava Y N <pranavayn@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89292
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
---
 src/lib/Makefile.mk | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/src/lib/Makefile.mk b/src/lib/Makefile.mk
index ecb06c4765..d9792dbea4 100644
--- a/src/lib/Makefile.mk
+++ b/src/lib/Makefile.mk
@@ -442,8 +442,7 @@ $(2)-compression := $$(BMP_LOGO_COMPRESS_FLAG)
 endef
 
 ifneq ($(CONFIG_HAVE_CUSTOM_BMP_LOGO),y)
-$(eval $(call add_bmp_logo_file_to_cbfs,CONFIG_BMP_LOGO, logo.bmp,\
-	      CONFIG_BMP_LOGO_FILE_NAME))
+$(eval $(call add_bmp_logo_file_to_cbfs,CONFIG_BMP_LOGO,logo.bmp,CONFIG_BMP_LOGO_FILE_NAME))
 endif
 
 $(eval $(call add_bmp_logo_file_to_cbfs,CONFIG_PLATFORM_HAS_LOW_BATTERY_INDICATOR, \

From d2345e0c60089bbd0c16a7fbd1e9c780c0e53061 Mon Sep 17 00:00:00 2001
From: Subrata Banik <subratabanik@google.com>
Date: Thu, 21 Aug 2025 17:33:44 +0530
Subject: [PATCH 2073/3886] mb/google/fatcat: Set `SkipExtGfxScan` FSP-M UPD
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

This patch overrides `SkipExtGfxScan` UPD as the Fatcat device is
equipped with an on-board graphics device hence, skip scanning
external GFX devices.

TEST=Able to save ~10ms+ boot time on google/fatcat.

FSP FPDT Data is showing the timestamp between those function calls.

Without this patch:
  50b8	680462	42	76f18bda-2195-4fb6-9a940e0bacdeecab
  50b9	696649	16187	76f18bda-2195-4fb6-9a940e0bacdeecab

With this patch:

    `CheckOffboardPcieVga` is not getting called.

Change-Id: I198a99ac5596ff98a9cc673dbd84889d7c5386cb
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88888
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Pranava Y N <pranavayn@google.com>
---
 .../google/fatcat/variants/baseboard/fatcat/devicetree.cb      | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/src/mainboard/google/fatcat/variants/baseboard/fatcat/devicetree.cb b/src/mainboard/google/fatcat/variants/baseboard/fatcat/devicetree.cb
index 90091d06f6..6ccd7c2e18 100644
--- a/src/mainboard/google/fatcat/variants/baseboard/fatcat/devicetree.cb
+++ b/src/mainboard/google/fatcat/variants/baseboard/fatcat/devicetree.cb
@@ -101,6 +101,9 @@ chip soc/intel/pantherlake
 		[VR_DOMAIN_SA] = 38 * 4
 	}"
 
+	# Set on-board graphics as primary display
+	register "skip_ext_gfx_scan" = "true"
+
 	# Enable CNVi BT
 	register "cnvi_bt_core" = "true"
 

From ffae0f7d73cf6061fb75650eec38beeecd698bc2 Mon Sep 17 00:00:00 2001
From: Derek Huang <derekhuang@google.com>
Date: Mon, 22 Sep 2025 15:05:47 +0000
Subject: [PATCH 2074/3886] security/vboot: Extend CROS_EC_HASH_TIMEOUT_MS

The ITE EC may take more than 2 seconds to complete EC FW
hash calculation in some corner cases. For example, boot with
a dead battery, EC even takes more than 10 seconds to complte
the hash calculation. Extend the timeout from 2 seconds to 12
seconds to cover the ITE EC cases, it should not impact boot
time and functionalities.

BUG=b:445034279, b:444392807

Change-Id: I4f6e23dc3096cbba04c33c8f3cc36c90aa83462a
Signed-off-by: Derek Huang <derekhuang@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89293
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Pranava Y N <pranavayn@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/security/vboot/ec_sync.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/security/vboot/ec_sync.c b/src/security/vboot/ec_sync.c
index 47c21c7c23..e1d435e7cf 100644
--- a/src/security/vboot/ec_sync.c
+++ b/src/security/vboot/ec_sync.c
@@ -20,8 +20,8 @@
 
 /* Wait 10 ms between attempts to check if EC's hash is ready */
 #define CROS_EC_HASH_CHECK_DELAY_MS 10
-/* Give the EC 2 seconds to finish calculating its hash */
-#define CROS_EC_HASH_TIMEOUT_MS 2000
+/* Give the EC 12 seconds to finish calculating its hash */
+#define CROS_EC_HASH_TIMEOUT_MS 12000
 
 /* Wait 3 seconds after software sync for EC to clear the limit power flag. */
 #define LIMIT_POWER_WAIT_TIMEOUT_MS 3000

From 2859a5cba5e043e4cf124a49ec9df4ab3f17e606 Mon Sep 17 00:00:00 2001
From: NaveenVenturi1203 <venturi.naveen@intel.com>
Date: Wed, 10 Sep 2025 08:26:35 +0000
Subject: [PATCH 2075/3886] mb/{google,intel}/{fatcat,ptlrvp}: Prevent access
 to disconnected camera

Camera sensor gets enumerated even if the hardware is not connected and
makes it available for the user, leading to a black screen when the user
tries to open the camera.

This commit changes the probing power state for the OV13B Camera Sensor
to the D0 Power State in order for the driver to validate the physical
hardware connection. This change helps prevent unnecessary enumeration
when hardware is not connected.

TEST=On a Fatcat device with an OV13B camera sensor disconnected, the OS
     does not offer to use this video device.

Change-Id: Iabd8ffa6fd50367ff77325a2e1d9ae05e31eac93
Signed-off-by: Venturi Naveen <venturi.naveen@intel.com>
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89142
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
---
 src/mainboard/google/fatcat/variants/fatcat/overridetree.cb   | 4 ++--
 src/mainboard/intel/ptlrvp/variants/ptlrvp/overridetree.cb    | 4 ++--
 .../intel/ptlrvp/variants/ptlrvp_chromeec/overridetree.cb     | 4 ++--
 3 files changed, 6 insertions(+), 6 deletions(-)

diff --git a/src/mainboard/google/fatcat/variants/fatcat/overridetree.cb b/src/mainboard/google/fatcat/variants/fatcat/overridetree.cb
index f553c39d3c..47da1d98ba 100644
--- a/src/mainboard/google/fatcat/variants/fatcat/overridetree.cb
+++ b/src/mainboard/google/fatcat/variants/fatcat/overridetree.cb
@@ -655,7 +655,7 @@ chip soc/intel/pantherlake
 				register "num_freq_entries" = "1"
 				register "link_freq[0]" = "560 * MHz" # 560 MHz
 				register "remote_name" = ""IPU0""
-				register "max_dstate_for_probe" = "ACPI_DEVICE_SLEEP_D3_COLD"
+				register "max_dstate_for_probe" = "ACPI_DEVICE_SLEEP_D0"
 
 				register "has_power_resource" = "true"
 				#Controls
@@ -756,7 +756,7 @@ chip soc/intel/pantherlake
 				register "num_freq_entries" = "1"
 				register "link_freq[0]" = "560 * MHz" # 560 MHz
 				register "remote_name" = ""IPU0""
-				register "max_dstate_for_probe" = "ACPI_DEVICE_SLEEP_D3_COLD"
+				register "max_dstate_for_probe" = "ACPI_DEVICE_SLEEP_D0"
 
 				register "has_power_resource" = "true"
 				#Controls
diff --git a/src/mainboard/intel/ptlrvp/variants/ptlrvp/overridetree.cb b/src/mainboard/intel/ptlrvp/variants/ptlrvp/overridetree.cb
index 1f8611979f..62a7b59a81 100644
--- a/src/mainboard/intel/ptlrvp/variants/ptlrvp/overridetree.cb
+++ b/src/mainboard/intel/ptlrvp/variants/ptlrvp/overridetree.cb
@@ -653,7 +653,7 @@ chip soc/intel/pantherlake
 				register "num_freq_entries" = "1"
 				register "link_freq[0]" = "560 * MHz" # 560 MHz
 				register "remote_name" = ""IPU0""
-				register "max_dstate_for_probe" = "ACPI_DEVICE_SLEEP_D3_COLD"
+				register "max_dstate_for_probe" = "ACPI_DEVICE_SLEEP_D0"
 
 				register "has_power_resource" = "true"
 				#Controls
@@ -754,7 +754,7 @@ chip soc/intel/pantherlake
 				register "num_freq_entries" = "1"
 				register "link_freq[0]" = "560 * MHz" # 560 MHz
 				register "remote_name" = ""IPU0""
-				register "max_dstate_for_probe" = "ACPI_DEVICE_SLEEP_D3_COLD"
+				register "max_dstate_for_probe" = "ACPI_DEVICE_SLEEP_D0"
 
 				register "has_power_resource" = "true"
 				#Controls
diff --git a/src/mainboard/intel/ptlrvp/variants/ptlrvp_chromeec/overridetree.cb b/src/mainboard/intel/ptlrvp/variants/ptlrvp_chromeec/overridetree.cb
index 4d8ae44266..de6cf416f8 100644
--- a/src/mainboard/intel/ptlrvp/variants/ptlrvp_chromeec/overridetree.cb
+++ b/src/mainboard/intel/ptlrvp/variants/ptlrvp_chromeec/overridetree.cb
@@ -653,7 +653,7 @@ chip soc/intel/pantherlake
 				register "num_freq_entries" = "1"
 				register "link_freq[0]" = "560 * MHz" # 560 MHz
 				register "remote_name" = ""IPU0""
-				register "max_dstate_for_probe" = "ACPI_DEVICE_SLEEP_D3_COLD"
+				register "max_dstate_for_probe" = "ACPI_DEVICE_SLEEP_D0"
 
 				register "has_power_resource" = "true"
 				#Controls
@@ -754,7 +754,7 @@ chip soc/intel/pantherlake
 				register "num_freq_entries" = "1"
 				register "link_freq[0]" = "560 * MHz" # 560 MHz
 				register "remote_name" = ""IPU0""
-				register "max_dstate_for_probe" = "ACPI_DEVICE_SLEEP_D3_COLD"
+				register "max_dstate_for_probe" = "ACPI_DEVICE_SLEEP_D0"
 
 				register "has_power_resource" = "true"
 				#Controls

From 14e6c62c1008f9d7c0c9a951ac29fcb7390927c7 Mon Sep 17 00:00:00 2001
From: Yu-Ping Wu <yupingso@chromium.org>
Date: Mon, 22 Sep 2025 12:49:08 +0800
Subject: [PATCH 2076/3886] mb/google/skywalker: Define all GPIO pins

Define all GPIO pins in gpio.h by their names defined in the AP pinmux
table. For example, the name of GPIO12 is "EN_PWR_FP".

BUG=none
TEST=emerge-skywalker coreboot
BRANCH=skywalker

Change-Id: I3936cc667d3695ff1609c3fd0fac59a204d511a5
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89285
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/google/skywalker/chromeos.c  |   8 +-
 src/mainboard/google/skywalker/gpio.h      | 183 +++++++++++++++++----
 src/mainboard/google/skywalker/mainboard.c |  14 +-
 src/mainboard/google/skywalker/panel.c     |   2 +-
 4 files changed, 161 insertions(+), 46 deletions(-)

diff --git a/src/mainboard/google/skywalker/chromeos.c b/src/mainboard/google/skywalker/chromeos.c
index d5a04371df..c6a891b8f7 100644
--- a/src/mainboard/google/skywalker/chromeos.c
+++ b/src/mainboard/google/skywalker/chromeos.c
@@ -26,20 +26,20 @@ void setup_chromeos_gpios(void)
 	gpio_input(GPIO_HDMI_HPD_1V8_ODL);
 
 	gpio_output(GPIO_AP_EC_WARM_RST_REQ, 0);
-	gpio_output(GPIO_XHCI_INIT_DONE, 0);
+	gpio_output(GPIO_AP_XHCI_INIT_DONE, 0);
 	gpio_output(GPIO_AP_SUSPEND_L, 1);
 	gpio_output(GPIO_AP_HDMI_RST_ODL, 0);
 	gpio_output(GPIO_AP_FP_FW_UP_STRAP, 0);
 	gpio_output(GPIO_EN_PWR_FP, 0);
 	gpio_output(GPIO_FP_RST_1V8_S3_L, 0);
 	gpio_output(GPIO_EN_SPKR, 0);
-	gpio_output(GPIO_AP_EDP_BKLTEN, 0);
+	gpio_output(GPIO_EDP_BL_EN_1V8, 0);
 }
 
 void fill_lb_gpios(struct lb_gpios *gpios)
 {
 	struct lb_gpio chromeos_gpios[] = {
-		{GPIO_XHCI_INIT_DONE.id, ACTIVE_HIGH, -1, "XHCI init done"},
+		{GPIO_AP_XHCI_INIT_DONE.id, ACTIVE_HIGH, -1, "XHCI init done"},
 		{GPIO_EC_AP_INT_ODL.id, ACTIVE_LOW, -1, "EC interrupt"},
 		{GPIO_GSC_AP_INT_ODL.id, ACTIVE_HIGH, -1, "TPM interrupt"},
 	};
@@ -71,7 +71,7 @@ void fill_lb_gpios(struct lb_gpios *gpios)
 
 	struct lb_gpio edp_pwm_backlight_gpios[] = {
 		{GPIO_BL_PWM_1V8.id, ACTIVE_HIGH, -1, "PWM control"},
-		{GPIO_AP_EDP_BKLTEN.id, ACTIVE_HIGH, -1, "backlight enable"},
+		{GPIO_EDP_BL_EN_1V8.id, ACTIVE_HIGH, -1, "backlight enable"},
 	};
 	lb_add_gpios(gpios, edp_pwm_backlight_gpios, ARRAY_SIZE(edp_pwm_backlight_gpios));
 }
diff --git a/src/mainboard/google/skywalker/gpio.h b/src/mainboard/google/skywalker/gpio.h
index a55a01aab1..5e412a21cd 100644
--- a/src/mainboard/google/skywalker/gpio.h
+++ b/src/mainboard/google/skywalker/gpio.h
@@ -5,40 +5,155 @@
 
 #include <soc/gpio.h>
 
-#define GPIO_XHCI_INIT_DONE		GPIO(GBE_MDC)
-#define GPIO_USB3_HUB_RST_L		GPIO(GPIO07)
-#define GPIO_EC_AP_INT_ODL		GPIO(GBE_MDIO)
-#define GPIO_AP_EC_WARM_RST_REQ		GPIO(GBE_AUX_PPS0)
-#define GPIO_GSC_AP_INT_ODL		GPIO(GBE_AUX_PPS1)
-#define GPIO_AP_SUSPEND_L		GPIO(CONN_TOP_DATA)
-#define GPIO_FP_RST_1V8_S3_L		GPIO(GBE_RXER)
-#define GPIO_AP_FP_FW_UP_STRAP		GPIO(GBE_TXER)
-#define GPIO_EN_PWR_FP			GPIO(GPIO12)
-#define GPIO_HP_INT_ODL			GPIO(GPIO04)
-#define GPIO_SPKR_INT_ODL		GPIO(GPIO08)
-#define GPIO_SAR_INT_ODL		GPIO(GPIO09)
-#define GPIO_PEN_EJECT_OD		GPIO(GPIO11)
-#define GPIO_TCHSCR_INT_1V8_ODL		GPIO(GPIO15)
-#define GPIO_AP_WP_ODL			GPIO(GPIO16)
-#define GPIO_EC_AP_DPOC_EN_ODL		GPIO(GPIO17)
-#define GPIO_TCHPAD_INT_ODL		GPIO(GBE_RXD1)
-#define GPIO_HDMI_AP_INT_ODL		GPIO(GBE_RXC)
-#define GPIO_FP_AP_INT_1V8_S3_ODL	GPIO(GBE_RXDV)
-#define GPIO_SD_CD_ODL			GPIO(GBE_INTR)
-#define GPIO_HDMI_HPD_1V8_ODL		GPIO(CONN_TOP_CLK)
-#define GPIO_AP_HDMI_RST_ODL		GPIO(GBE_TXC)
-#define GPIO_EN_SPKR			GPIO(GPIO05)
-#define GPIO_I2SOUT1_BCK		GPIO(DMIC0_DAT0)
-#define GPIO_I2SOUT1_LRCK		GPIO(DMIC1_CLK)
-#define GPIO_I2SOUT1_DOUT		GPIO(DMIC1_DAT0)
-#define GPIO_I2SOUT0_MCK		GPIO(I2SOUT0_MCK)
-#define GPIO_I2SOUT0_BCK		GPIO(I2SOUT0_BCK)
-#define GPIO_I2SOUT0_LRCK		GPIO(I2SOUT0_LRCK)
-#define GPIO_I2SOUT0_DOUT		GPIO(I2SOUT0_DO)
-#define GPIO_BL_PWM_1V8			GPIO(DISP_PWM0)
-#define GPIO_AP_EDP_BKLTEN		GPIO(GPIO13)
-#define GPIO_EN_PP3300_EDP_X		GPIO(DSI_LCM_RST)
-#define GPIO_EDP_HPD_1V8		GPIO(EDP_TX_HPD)
+#define GPIO_IMU_INT_SCP_L			GPIO(GPIO00)
+#define GPIO_LID_ACCEL_INT_SCP_L		GPIO(GPIO01)
+#define GPIO_AP_SCP_GPIO02			GPIO(GPIO02)
+#define GPIO_AP_SCP_GPIO03			GPIO(GPIO03)
+#define GPIO_HP_INT_ODL				GPIO(GPIO04)
+#define GPIO_EN_SPKR				GPIO(GPIO05)
+#define GPIO_RST_SPKR_L				GPIO(GPIO06)
+#define GPIO_USB3_HUB_RST_L			GPIO(GPIO07)
+#define GPIO_SPKR_INT_ODL			GPIO(GPIO08)
+#define GPIO_SAR_INT_ODL			GPIO(GPIO09)
+#define GPIO_WWAN_RESET_L			GPIO(GPIO10)
+#define GPIO_PEN_EJECT_OD			GPIO(GPIO11)
+#define GPIO_EN_PWR_FP				GPIO(GPIO12)
+#define GPIO_EDP_BL_EN_1V8			GPIO(GPIO13)
+#define GPIO_TCHSCR_REPORT_DISABLE		GPIO(GPIO14)
+#define GPIO_TCHSCR_INT_1V8_ODL			GPIO(GPIO15)
+#define GPIO_AP_WP_ODL				GPIO(GPIO16)
+#define GPIO_EC_AP_DPOC_EN_ODL			GPIO(GPIO17)
+#define GPIO_EN_PP3300_EDP_X			GPIO(DSI_LCM_RST)
+#define GPIO_EC_AP_DP_HPD_L			GPIO(DP_TX_HPD)
+#define GPIO_EDP_HPD_1V8			GPIO(EDP_TX_HPD)
+#define GPIO_BL_PWM_1V8				GPIO(DISP_PWM0)
+#define GPIO_CODEC_PWR_SOC_EN			GPIO(DISP_PWM1)
+#define GPIO_UART_AP_TX_GSC_DBG_RX		GPIO(UART0_TXD)
+#define GPIO_UART_GSC_DBG_TX_AP_RX		GPIO(UART0_RXD)
+#define GPIO_AP_UART1_TXD			GPIO(UART1_TXD)
+#define GPIO_AP_UART1_RXD			GPIO(UART1_RXD)
+#define GPIO_AP_UART2_TXD			GPIO(UART2_TXD)
+#define GPIO_AP_UART2_RXD			GPIO(UART2_RXD)
+#define GPIO_AP_UART3_TXD			GPIO(UART3_TXD)
+#define GPIO_AP_UART3_RXD			GPIO(UART3_RXD)
+#define GPIO_AP_JTAG_TMS			GPIO(JTMS)
+#define GPIO_AP_JTAG_TCK			GPIO(JTCK)
+#define GPIO_AP_JTAG_TDI			GPIO(JTDI)
+#define GPIO_AP_JTAG_TDO			GPIO(JTDO)
+#define GPIO_AP_JTAG_TRST_L			GPIO(JTRST)
+#define GPIO_AP_KPCOL0				GPIO(KPCOL0)
+#define GPIO_AP_KPCOL1 				GPIO(KPCOL1)
+#define GPIO_AP_KPROW0 				GPIO(KPROW0)
+#define GPIO_AP_KPROW1 				GPIO(KPROW1)
+#define GPIO_PCIE_WLAN_WAKE_OBFF_1V8_ODL	GPIO(PCIE_WAKE_N)
+#define GPIO_PCIE_WLAN_RST_1V8_L		GPIO(PCIE_PERESET_N)
+#define GPIO_PCIE_WLAN_CLKREQ_1V8_ODL		GPIO(PCIE_CLKREQ_N)
+#define GPIO_SCP_I2C_SENSOR_SCL_1V8		GPIO(SCP_SCL0)
+#define GPIO_SCP_I2C_SENSOR_SDA_1V8		GPIO(SCP_SDA0)
+#define GPIO_AP_SCP_I2C1_SCL 			GPIO(SCP_SCL1)
+#define GPIO_AP_SCP_I2C1_SDA 			GPIO(SCP_SDA1)
+#define GPIO_AP_I2C_AUD_SCL_1V8			GPIO(SCL2)
+#define GPIO_AP_I2C_AUD_SDA_1V8			GPIO(SDA2)
+#define GPIO_AP_I2C_TPM_SCL_1V8			GPIO(SCL3)
+#define GPIO_AP_I2C_TPM_SDA_1V8			GPIO(SDA3)
+#define GPIO_AP_I2C_TCHSCR_SCL_1V8		GPIO(SCL4)
+#define GPIO_AP_I2C_TCHSCR_SDA_1V8		GPIO(SDA4)
+#define GPIO_AP_I2C_SAR_SCL_1V8			GPIO(SCL5)
+#define GPIO_AP_I2C_SAR_SDA_1V8			GPIO(SDA5)
+#define GPIO_AP_I2C_HDMI_SCL_1V8		GPIO(SCL6)
+#define GPIO_AP_I2C_HDMI_SDA_1V8		GPIO(SDA6)
+#define GPIO_AP_I2C_TCHPAD_SCL_1V8		GPIO(SCL7)
+#define GPIO_AP_I2C_TCHPAD_SDA_1V8		GPIO(SDA7)
+#define GPIO_AP_I2C8_SCL_1V8 			GPIO(SCL8)
+#define GPIO_AP_I2C8_SDA_1V8 			GPIO(SDA8)
+#define GPIO_SPI_AP_CS_EC_L			GPIO(SPIM0_CSB)
+#define GPIO_SPI_AP_CLK_EC			GPIO(SPIM0_CLK)
+#define GPIO_SPI_AP_DO_EC_DI			GPIO(SPIM0_MOSI)
+#define GPIO_SPI_AP_DI_EC_DO			GPIO(SPIM0_MISO)
+#define GPIO_SPI_AP_CS_FP_1V8_L			GPIO(SPIM1_CSB)
+#define GPIO_SPI_AP_CLK_FP_1V8			GPIO(SPIM1_CLK)
+#define GPIO_SPI_AP_DO_FP_DI_1V8		GPIO(SPIM1_MOSI)
+#define GPIO_SPI_AP_DI_FP_DO_1V8		GPIO(SPIM1_MISO)
+#define GPIO_SPI_AP_CS_TCHSCR_L			GPIO(SPIM2_CSB)
+#define GPIO_SPI_AP_CLK_TCHSCR			GPIO(SPIM2_CLK)
+#define GPIO_SPI_AP_DO_TCHSCR_DI		GPIO(SPIM2_MOSI)
+#define GPIO_SPI_AP_DI_TCHSCR_DO		GPIO(SPIM2_MISO)
+#define GPIO_PWRAP_SPI_CS_L			GPIO(PWRAP_SPI_CSN)
+#define GPIO_PWRAP_SPI_CK			GPIO(PWRAP_SPI_CK)
+#define GPIO_PWRAP_SPI_MOSI			GPIO(PWRAP_SPI_MO)
+#define GPIO_PWRAP_SPI_MISO			GPIO(PWRAP_SPI_MI)
+#define GPIO_SRCLKENA0				GPIO(PMIC_SRCLKENA0)
+#define GPIO_SRCLKENA1				GPIO(PMIC_SRCLKENA1)
+#define GPIO_SCP_VREQ_VAO			GPIO(SCP_VREQ_VAO)
+#define GPIO_AP_RTC_CLK32K			GPIO(PMIC_RTC32K_CK)
+#define GPIO_AP_PMIC_WDTRST_L			GPIO(PMIC_WATCHDOG)
+#define GPIO_AUD_CLK_MOSI 			GPIO(AUD_CLK_MOSI)
+#define GPIO_AUD_SYNC_MOSI 			GPIO(AUD_SYNC_MOSI)
+#define GPIO_AUD_DAT_MOSI0 			GPIO(AUD_DAT_MOSI0)
+#define GPIO_AUD_DAT_MOSI1 			GPIO(AUD_DAT_MOSI1)
+#define GPIO_AUD_DAT_MISO0 			GPIO(AUD_DAT_MISO0)
+#define GPIO_AUD_DAT_MISO1 			GPIO(AUD_DAT_MISO1)
+#define GPIO_AP_I2SIN0_MCK 			GPIO(I2SIN0_MCK)
+#define GPIO_AP_I2SIN0_BCk 			GPIO(I2SIN0_BCK)
+#define GPIO_AP_I2SIN0_LRCK 			GPIO(I2SIN0_LRCK)
+#define GPIO_I2S_HP_DI				GPIO(I2SIN0_DI)
+#define GPIO_I2S_HP_MCK				GPIO(I2SOUT0_MCK)
+#define GPIO_I2S_HP_BCK				GPIO(I2SOUT0_BCK)
+#define GPIO_I2S_HP_LRCK			GPIO(I2SOUT0_LRCK)
+#define GPIO_I2S_HP_DO				GPIO(I2SOUT0_DO)
+#define GPIO_I2S_SPKR_MCK			GPIO(DMIC0_CLK)
+#define GPIO_I2S_SPKR_BCK			GPIO(DMIC0_DAT0)
+#define GPIO_I2S_SPKR_LRCK			GPIO(DMIC1_CLK)
+#define GPIO_I2S_SPKR_DO			GPIO(DMIC1_DAT0)
+#define GPIO_PCM_HDMI_CLK			GPIO(PCM_CLK)
+#define GPIO_PCM_HDMI_SYNC			GPIO(PCM_SYNC)
+#define GPIO_AP_PCM_DI 				GPIO(PCM_DI)
+#define GPIO_PCM_HDMI_DO			GPIO(PCM_DO)
+#define GPIO_DMIC0_CLK				GPIO(GBE_TXD3)
+#define GPIO_DMIC0_DATA				GPIO(GBE_TXD2)
+#define GPIO_EN_PP3300_WWAN_X			GPIO(GBE_TXD1)
+#define GPIO_DMIC1_CLK				GPIO(GBE_TXD0)
+#define GPIO_DMIC1_DATA				GPIO(GBE_RXD3)
+#define GPIO_WWAN_SAR_DETECT_L			GPIO(GBE_RXD2)
+#define GPIO_TCHPAD_INT_ODL			GPIO(GBE_RXD1)
+#define GPIO_TCHSCR_RST_1V8_L			GPIO(GBE_RXD0)
+#define GPIO_AP_HDMI_RST_ODL			GPIO(GBE_TXC)
+#define GPIO_HDMI_AP_INT_ODL			GPIO(GBE_RXC)
+#define GPIO_FP_AP_INT_1V8_S3_ODL		GPIO(GBE_RXDV)
+#define GPIO_I2S_SPKR_DI			GPIO(GBE_TXEN)
+#define GPIO_AP_XHCI_INIT_DONE			GPIO(GBE_MDC)
+#define GPIO_EC_AP_INT_ODL			GPIO(GBE_MDIO)
+#define GPIO_AP_FP_FW_UP_STRAP			GPIO(GBE_TXER)
+#define GPIO_FP_RST_1V8_S3_L			GPIO(GBE_RXER)
+#define GPIO_EN_HDMI_PWR			GPIO(GBE_COL)
+#define GPIO_SD_CD_ODL				GPIO(GBE_INTR)
+#define GPIO_AP_EC_WARM_RST_REQ			GPIO(GBE_AUX_PPS0)
+#define GPIO_GSC_AP_INT_ODL			GPIO(GBE_AUX_PPS1)
+#define GPIO_HDMI_HPD_1V8_ODL			GPIO(CONN_TOP_CLK)
+#define GPIO_AP_SUSPEND_L 			GPIO(CONN_TOP_DATA)
+#define GPIO_EC_AP_RSVD0_ODL			GPIO(CONN_BT_CLK)
+#define GPIO_EC_AP_RSVD1_ODL			GPIO(CONN_BT_DATA)
+#define GPIO_MT6319B_INT			GPIO(CONN_HRST_B)
+#define GPIO_MT6319C_INT			GPIO(CONN_WB_PTA)
+#define GPIO_BT_KILL_1V8_L			GPIO(CONN_WF_CTRL0)
+#define GPIO_WIFI_KILL_1V8_L			GPIO(CONN_WF_CTRL1)
+#define GPIO_WWAN_PWR_OFF_L			GPIO(CONN_WF_CTRL2)
+#define GPIO_WWAN_W_DISABLE_L			GPIO(CONN_WF_CTRL3)
+#define GPIO_SPI_AP_CLK_BIOS			GPIO(SPINOR_CK)
+#define GPIO_SPI_AP_CS_BIOS_L			GPIO(SPINOR_CS)
+#define GPIO_SPI_AP_DO_BIOS_DI			GPIO(SPINOR_IO0)
+#define GPIO_SPI_AP_DI_BIOS_DO			GPIO(SPINOR_IO1)
+#define GPIO_AP_SPINOR_IO2 			GPIO(SPINOR_IO2)
+#define GPIO_AP_SPINOR_IO3 			GPIO(SPINOR_IO3)
+#define GPIO_SD_CMD				GPIO(MSDC1_CMD)
+#define GPIO_SD_CLK				GPIO(MSDC1_CLK)
+#define GPIO_SD_DATA0				GPIO(MSDC1_DAT0)
+#define GPIO_SD_DATA1				GPIO(MSDC1_DAT1)
+#define GPIO_SD_DATA2				GPIO(MSDC1_DAT2)
+#define GPIO_SD_DATA3				GPIO(MSDC1_DAT3)
+#define GPIO_SPMI_SCL				GPIO(SPMI_P_SCL)
+#define GPIO_SPMI_SDA				GPIO(SPMI_P_SDA)
+#define GPIO_EMI_RESET_N			GPIO(EMI_RESETB)
 
 void setup_chromeos_gpios(void);
 
diff --git a/src/mainboard/google/skywalker/mainboard.c b/src/mainboard/google/skywalker/mainboard.c
index ba6b66fd18..99c45cf17a 100644
--- a/src/mainboard/google/skywalker/mainboard.c
+++ b/src/mainboard/google/skywalker/mainboard.c
@@ -24,9 +24,9 @@
 static void configure_rt9123_rt1019(void)
 {
 	/* SoC I2S */
-	gpio_set_mode(GPIO_I2SOUT1_BCK, GPIO_FUNC(DMIC0_DAT0, I2SOUT1_BCK));
-	gpio_set_mode(GPIO_I2SOUT1_LRCK, GPIO_FUNC(DMIC1_CLK, I2SOUT1_LRCK));
-	gpio_set_mode(GPIO_I2SOUT1_DOUT, GPIO_FUNC(DMIC1_DAT0, I2SOUT1_DO));
+	gpio_set_mode(GPIO_I2S_SPKR_BCK, GPIO_FUNC(DMIC0_DAT0, I2SOUT1_BCK));
+	gpio_set_mode(GPIO_I2S_SPKR_LRCK, GPIO_FUNC(DMIC1_CLK, I2SOUT1_LRCK));
+	gpio_set_mode(GPIO_I2S_SPKR_DO, GPIO_FUNC(DMIC1_DAT0, I2SOUT1_DO));
 
 	printk(BIOS_INFO, "%s: AMP configuration done\n", __func__);
 }
@@ -34,10 +34,10 @@ static void configure_rt9123_rt1019(void)
 static void configure_alc5645(void)
 {
 	/* SoC I2S */
-	gpio_set_mode(GPIO_I2SOUT0_MCK, GPIO_FUNC(I2SOUT0_MCK, I2SOUT0_MCK));
-	gpio_set_mode(GPIO_I2SOUT0_BCK, GPIO_FUNC(I2SOUT0_BCK, I2SOUT0_BCK));
-	gpio_set_mode(GPIO_I2SOUT0_LRCK, GPIO_FUNC(I2SOUT0_LRCK, I2SOUT0_LRCK));
-	gpio_set_mode(GPIO_I2SOUT0_DOUT, GPIO_FUNC(I2SOUT0_DO, I2SOUT0_DO));
+	gpio_set_mode(GPIO_I2S_HP_MCK, GPIO_FUNC(I2SOUT0_MCK, I2SOUT0_MCK));
+	gpio_set_mode(GPIO_I2S_HP_BCK, GPIO_FUNC(I2SOUT0_BCK, I2SOUT0_BCK));
+	gpio_set_mode(GPIO_I2S_HP_LRCK, GPIO_FUNC(I2SOUT0_LRCK, I2SOUT0_LRCK));
+	gpio_set_mode(GPIO_I2S_HP_DO, GPIO_FUNC(I2SOUT0_DO, I2SOUT0_DO));
 
 	/* Init I2C bus timing register for audio codecs */
 	mtk_i2c_bus_init(I2C2, I2C_SPEED_STANDARD);
diff --git a/src/mainboard/google/skywalker/panel.c b/src/mainboard/google/skywalker/panel.c
index b0cb052881..35313c23f6 100644
--- a/src/mainboard/google/skywalker/panel.c
+++ b/src/mainboard/google/skywalker/panel.c
@@ -8,7 +8,7 @@
 /* Set up backlight control pins as output pins, and set them to power off by default */
 static void configure_backlight(void)
 {
-	gpio_output(GPIO_AP_EDP_BKLTEN, 0);
+	gpio_output(GPIO_EDP_BL_EN_1V8, 0);
 	gpio_output(GPIO_BL_PWM_1V8, 0);
 }
 

From 1e7908fa9fc034f1851f5e32159139e8382051c1 Mon Sep 17 00:00:00 2001
From: Yu-Ping Wu <yupingso@chromium.org>
Date: Mon, 22 Sep 2025 12:34:59 +0800
Subject: [PATCH 2077/3886] mb/google/skywalker: Set up all output GPIOs

Set up all output GPIOs. The initial values are set consistently with
the values in kernel to avoid voltage steps in the bootup process. The
GPIOs are sorted by their EINT IDs.

BUG=none
TEST=emerge-skywalker coreboot
BRANCH=skywalker

Change-Id: Iacc1808108a33ca66f06ba5b3a4b082ed4e2673f
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89286
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
---
 src/mainboard/google/skywalker/chromeos.c | 28 +++++++++++++++++------
 1 file changed, 21 insertions(+), 7 deletions(-)

diff --git a/src/mainboard/google/skywalker/chromeos.c b/src/mainboard/google/skywalker/chromeos.c
index c6a891b8f7..07341d9ee8 100644
--- a/src/mainboard/google/skywalker/chromeos.c
+++ b/src/mainboard/google/skywalker/chromeos.c
@@ -25,15 +25,29 @@ void setup_chromeos_gpios(void)
 	gpio_input(GPIO_SD_CD_ODL);
 	gpio_input(GPIO_HDMI_HPD_1V8_ODL);
 
-	gpio_output(GPIO_AP_EC_WARM_RST_REQ, 0);
-	gpio_output(GPIO_AP_XHCI_INIT_DONE, 0);
-	gpio_output(GPIO_AP_SUSPEND_L, 1);
-	gpio_output(GPIO_AP_HDMI_RST_ODL, 0);
-	gpio_output(GPIO_AP_FP_FW_UP_STRAP, 0);
-	gpio_output(GPIO_EN_PWR_FP, 0);
-	gpio_output(GPIO_FP_RST_1V8_S3_L, 0);
 	gpio_output(GPIO_EN_SPKR, 0);
+	gpio_output(GPIO_RST_SPKR_L, 0);
+	gpio_output(GPIO_USB3_HUB_RST_L, 0);
+	gpio_output(GPIO_WWAN_RESET_L, 0);
+	gpio_output(GPIO_EN_PWR_FP, 0);
 	gpio_output(GPIO_EDP_BL_EN_1V8, 0);
+	gpio_output(GPIO_TCHSCR_REPORT_DISABLE, 1);
+	gpio_output(GPIO_CODEC_PWR_SOC_EN, 0);
+	gpio_output(GPIO_EN_PP3300_EDP_X, 0);
+	gpio_output(GPIO_EN_PP3300_WWAN_X, 0);
+	gpio_output(GPIO_WWAN_SAR_DETECT_L, 1);
+	gpio_output(GPIO_TCHSCR_RST_1V8_L, 0);
+	gpio_output(GPIO_AP_HDMI_RST_ODL, 0);
+	gpio_output(GPIO_AP_XHCI_INIT_DONE, 0);
+	gpio_output(GPIO_AP_FP_FW_UP_STRAP, 0);
+	gpio_output(GPIO_FP_RST_1V8_S3_L, 0);
+	gpio_output(GPIO_EN_HDMI_PWR, 0);
+	gpio_output(GPIO_AP_EC_WARM_RST_REQ, 0);
+	gpio_output(GPIO_AP_SUSPEND_L, 1);
+	gpio_output(GPIO_BT_KILL_1V8_L, 0);
+	gpio_output(GPIO_WIFI_KILL_1V8_L, 0);
+	gpio_output(GPIO_WWAN_PWR_OFF_L, 0);
+	gpio_output(GPIO_WWAN_W_DISABLE_L, 0);
 }
 
 void fill_lb_gpios(struct lb_gpios *gpios)

From d8ed9773589afc4778ff3acb61b0943452727b71 Mon Sep 17 00:00:00 2001
From: Yu-Ping Wu <yupingso@chromium.org>
Date: Tue, 23 Sep 2025 15:03:49 +0800
Subject: [PATCH 2078/3886] mb/google/skywalker: Remove space before tabs in
 gpio.h

BUG=none
TEST=emerge-skywalker coreboot
BRANCH=skywalker

Change-Id: Id46f7a87d452aa94799abc2e3972387edf7228f9
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89310
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
---
 src/mainboard/google/skywalker/gpio.h | 40 +++++++++++++--------------
 1 file changed, 20 insertions(+), 20 deletions(-)

diff --git a/src/mainboard/google/skywalker/gpio.h b/src/mainboard/google/skywalker/gpio.h
index 5e412a21cd..58315677a2 100644
--- a/src/mainboard/google/skywalker/gpio.h
+++ b/src/mainboard/google/skywalker/gpio.h
@@ -42,16 +42,16 @@
 #define GPIO_AP_JTAG_TDO			GPIO(JTDO)
 #define GPIO_AP_JTAG_TRST_L			GPIO(JTRST)
 #define GPIO_AP_KPCOL0				GPIO(KPCOL0)
-#define GPIO_AP_KPCOL1 				GPIO(KPCOL1)
-#define GPIO_AP_KPROW0 				GPIO(KPROW0)
-#define GPIO_AP_KPROW1 				GPIO(KPROW1)
+#define GPIO_AP_KPCOL1				GPIO(KPCOL1)
+#define GPIO_AP_KPROW0				GPIO(KPROW0)
+#define GPIO_AP_KPROW1				GPIO(KPROW1)
 #define GPIO_PCIE_WLAN_WAKE_OBFF_1V8_ODL	GPIO(PCIE_WAKE_N)
 #define GPIO_PCIE_WLAN_RST_1V8_L		GPIO(PCIE_PERESET_N)
 #define GPIO_PCIE_WLAN_CLKREQ_1V8_ODL		GPIO(PCIE_CLKREQ_N)
 #define GPIO_SCP_I2C_SENSOR_SCL_1V8		GPIO(SCP_SCL0)
 #define GPIO_SCP_I2C_SENSOR_SDA_1V8		GPIO(SCP_SDA0)
-#define GPIO_AP_SCP_I2C1_SCL 			GPIO(SCP_SCL1)
-#define GPIO_AP_SCP_I2C1_SDA 			GPIO(SCP_SDA1)
+#define GPIO_AP_SCP_I2C1_SCL			GPIO(SCP_SCL1)
+#define GPIO_AP_SCP_I2C1_SDA			GPIO(SCP_SDA1)
 #define GPIO_AP_I2C_AUD_SCL_1V8			GPIO(SCL2)
 #define GPIO_AP_I2C_AUD_SDA_1V8			GPIO(SDA2)
 #define GPIO_AP_I2C_TPM_SCL_1V8			GPIO(SCL3)
@@ -64,8 +64,8 @@
 #define GPIO_AP_I2C_HDMI_SDA_1V8		GPIO(SDA6)
 #define GPIO_AP_I2C_TCHPAD_SCL_1V8		GPIO(SCL7)
 #define GPIO_AP_I2C_TCHPAD_SDA_1V8		GPIO(SDA7)
-#define GPIO_AP_I2C8_SCL_1V8 			GPIO(SCL8)
-#define GPIO_AP_I2C8_SDA_1V8 			GPIO(SDA8)
+#define GPIO_AP_I2C8_SCL_1V8			GPIO(SCL8)
+#define GPIO_AP_I2C8_SDA_1V8			GPIO(SDA8)
 #define GPIO_SPI_AP_CS_EC_L			GPIO(SPIM0_CSB)
 #define GPIO_SPI_AP_CLK_EC			GPIO(SPIM0_CLK)
 #define GPIO_SPI_AP_DO_EC_DI			GPIO(SPIM0_MOSI)
@@ -87,15 +87,15 @@
 #define GPIO_SCP_VREQ_VAO			GPIO(SCP_VREQ_VAO)
 #define GPIO_AP_RTC_CLK32K			GPIO(PMIC_RTC32K_CK)
 #define GPIO_AP_PMIC_WDTRST_L			GPIO(PMIC_WATCHDOG)
-#define GPIO_AUD_CLK_MOSI 			GPIO(AUD_CLK_MOSI)
-#define GPIO_AUD_SYNC_MOSI 			GPIO(AUD_SYNC_MOSI)
-#define GPIO_AUD_DAT_MOSI0 			GPIO(AUD_DAT_MOSI0)
-#define GPIO_AUD_DAT_MOSI1 			GPIO(AUD_DAT_MOSI1)
-#define GPIO_AUD_DAT_MISO0 			GPIO(AUD_DAT_MISO0)
-#define GPIO_AUD_DAT_MISO1 			GPIO(AUD_DAT_MISO1)
-#define GPIO_AP_I2SIN0_MCK 			GPIO(I2SIN0_MCK)
-#define GPIO_AP_I2SIN0_BCk 			GPIO(I2SIN0_BCK)
-#define GPIO_AP_I2SIN0_LRCK 			GPIO(I2SIN0_LRCK)
+#define GPIO_AUD_CLK_MOSI			GPIO(AUD_CLK_MOSI)
+#define GPIO_AUD_SYNC_MOSI			GPIO(AUD_SYNC_MOSI)
+#define GPIO_AUD_DAT_MOSI0			GPIO(AUD_DAT_MOSI0)
+#define GPIO_AUD_DAT_MOSI1			GPIO(AUD_DAT_MOSI1)
+#define GPIO_AUD_DAT_MISO0			GPIO(AUD_DAT_MISO0)
+#define GPIO_AUD_DAT_MISO1			GPIO(AUD_DAT_MISO1)
+#define GPIO_AP_I2SIN0_MCK			GPIO(I2SIN0_MCK)
+#define GPIO_AP_I2SIN0_BCk			GPIO(I2SIN0_BCK)
+#define GPIO_AP_I2SIN0_LRCK			GPIO(I2SIN0_LRCK)
 #define GPIO_I2S_HP_DI				GPIO(I2SIN0_DI)
 #define GPIO_I2S_HP_MCK				GPIO(I2SOUT0_MCK)
 #define GPIO_I2S_HP_BCK				GPIO(I2SOUT0_BCK)
@@ -107,7 +107,7 @@
 #define GPIO_I2S_SPKR_DO			GPIO(DMIC1_DAT0)
 #define GPIO_PCM_HDMI_CLK			GPIO(PCM_CLK)
 #define GPIO_PCM_HDMI_SYNC			GPIO(PCM_SYNC)
-#define GPIO_AP_PCM_DI 				GPIO(PCM_DI)
+#define GPIO_AP_PCM_DI				GPIO(PCM_DI)
 #define GPIO_PCM_HDMI_DO			GPIO(PCM_DO)
 #define GPIO_DMIC0_CLK				GPIO(GBE_TXD3)
 #define GPIO_DMIC0_DATA				GPIO(GBE_TXD2)
@@ -130,7 +130,7 @@
 #define GPIO_AP_EC_WARM_RST_REQ			GPIO(GBE_AUX_PPS0)
 #define GPIO_GSC_AP_INT_ODL			GPIO(GBE_AUX_PPS1)
 #define GPIO_HDMI_HPD_1V8_ODL			GPIO(CONN_TOP_CLK)
-#define GPIO_AP_SUSPEND_L 			GPIO(CONN_TOP_DATA)
+#define GPIO_AP_SUSPEND_L			GPIO(CONN_TOP_DATA)
 #define GPIO_EC_AP_RSVD0_ODL			GPIO(CONN_BT_CLK)
 #define GPIO_EC_AP_RSVD1_ODL			GPIO(CONN_BT_DATA)
 #define GPIO_MT6319B_INT			GPIO(CONN_HRST_B)
@@ -143,8 +143,8 @@
 #define GPIO_SPI_AP_CS_BIOS_L			GPIO(SPINOR_CS)
 #define GPIO_SPI_AP_DO_BIOS_DI			GPIO(SPINOR_IO0)
 #define GPIO_SPI_AP_DI_BIOS_DO			GPIO(SPINOR_IO1)
-#define GPIO_AP_SPINOR_IO2 			GPIO(SPINOR_IO2)
-#define GPIO_AP_SPINOR_IO3 			GPIO(SPINOR_IO3)
+#define GPIO_AP_SPINOR_IO2			GPIO(SPINOR_IO2)
+#define GPIO_AP_SPINOR_IO3			GPIO(SPINOR_IO3)
 #define GPIO_SD_CMD				GPIO(MSDC1_CMD)
 #define GPIO_SD_CLK				GPIO(MSDC1_CLK)
 #define GPIO_SD_DATA0				GPIO(MSDC1_DAT0)

From c98155cbcdff5bf2e086be6ce00d5703e25ba941 Mon Sep 17 00:00:00 2001
From: Alicja Michalska <alicja.michalska@9elements.com>
Date: Wed, 17 Sep 2025 21:10:27 +0200
Subject: [PATCH 2079/3886] soc/intel/pantherlake: Generate TME keys only if
 TME is enabled
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

In order to build for PantherLake with TME disabled, key generation
needs to depend on TME Kconfig.

Change-Id: I0af438e279f422292302387442489bcbc1b1605f
Signed-off-by: Alicja Michalska <alicja.michalska@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89226
Reviewed-by: Pranava Y N <pranavayn@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
---
 src/soc/intel/pantherlake/Kconfig | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/soc/intel/pantherlake/Kconfig b/src/soc/intel/pantherlake/Kconfig
index d4c60022f3..60dc9e3390 100644
--- a/src/soc/intel/pantherlake/Kconfig
+++ b/src/soc/intel/pantherlake/Kconfig
@@ -106,7 +106,7 @@ config SOC_INTEL_PANTHERLAKE_BASE
 	select SOC_QDF_DYNAMIC_READ_PMC
 	select SSE2
 	select SUPPORT_CPU_UCODE_IN_CBFS
-	select TME_KEY_REGENERATION_ON_WARM_BOOT
+	select TME_KEY_REGENERATION_ON_WARM_BOOT if INTEL_TME
 	select TSC_MONOTONIC_TIMER
 	select UDELAY_TSC
 	select UDK_202302_BINDING

From fbb68982c95b1599ee70e8f8b5c5448c82ad2aa2 Mon Sep 17 00:00:00 2001
From: Appukuttan V K <appukuttan.vk@intel.com>
Date: Wed, 20 Aug 2025 22:31:16 +0530
Subject: [PATCH 2080/3886] mainboard/google/ocelot: Update PCIe root port for
 SD card interface

This commit updates the PCIe root port configuration for the SD card
interface in the overridetree.cb file for the Ocelot variant.
The reference is changed from `pcie_rp5` to `pcie_rp6`.

BUG=b:440042829
TEST=Boot the device with the updated firmware and verify that the
SD card is enumerated under pcie_rp6

Change-Id: I2b3c0b6e19409fef933aa7dc06f5df035f620738
Signed-off-by: Appukuttan V K <appukuttan.vk@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88873
Reviewed-by: Usha P <usha.p@intel.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Pranava Y N <pranavayn@google.com>
Reviewed-by: Krishna P Bhat D <krishna.p.bhat.d@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/google/ocelot/variants/ocelot/overridetree.cb | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/mainboard/google/ocelot/variants/ocelot/overridetree.cb b/src/mainboard/google/ocelot/variants/ocelot/overridetree.cb
index 59273e4bd3..011b03352a 100644
--- a/src/mainboard/google/ocelot/variants/ocelot/overridetree.cb
+++ b/src/mainboard/google/ocelot/variants/ocelot/overridetree.cb
@@ -478,10 +478,10 @@ chip soc/intel/pantherlake
 			end
 		end # Gen4 M.2 SSD
 
-		device ref pcie_rp5 on
+		device ref pcie_rp6 on
 			probe SD SD_GENSYS
 			probe SD SD_BAYHUB
-			register "pcie_rp[PCIE_RP(5)]" = "{
+			register "pcie_rp[PCIE_RP(6)]" = "{
 			.clk_src = 2,
 			.clk_req = 2,
 			.flags = PCIE_RP_CLK_REQ_DETECT | PCIE_RP_LTR | PCIE_RP_AER,

From 289c01e6fb3c56919fc4782a32660d154b7ab45d Mon Sep 17 00:00:00 2001
From: Nick Vaccaro <nvaccaro@google.com>
Date: Mon, 15 Sep 2025 11:04:12 -0700
Subject: [PATCH 2081/3886] mb/google/ocelot: implement variant_memory_sku()

Ocelot uses the CHROMEOS_DRAM_PART_NUMBER_IN_CBI Kconfig option
because the hardware does not have DRAM ID straps, but this option was
designed for boards that would only ever have a single memory option.

In order to support multiple memory parts, we need to create a table
that maps memory part number to DRAM id so that we can select the
correct SPD for the memory, and then override the variant_memory_sku()
routine so that we can determine and return the correct DRAM id for
the memory part number specified in the CBI.

BUG=b:443646405
TEST=Change DRAM part number in CBI to "H58G66BK7BX067", reboot ocelot
and verify the AP boot logs show that the SPD index = 1.

Change-Id: I18ba6c4891c6053f40e99dcde8a06b9efc1d95f4
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89183
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Appukuttan V K <appukuttan.vk@intel.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
---
 .../google/ocelot/variants/ocelot/Makefile.mk |  1 +
 .../google/ocelot/variants/ocelot/memory.c    |  2 +-
 .../variants/ocelot/part_num_to_dram_id.c     | 35 +++++++++++++++++++
 3 files changed, 37 insertions(+), 1 deletion(-)
 create mode 100644 src/mainboard/google/ocelot/variants/ocelot/part_num_to_dram_id.c

diff --git a/src/mainboard/google/ocelot/variants/ocelot/Makefile.mk b/src/mainboard/google/ocelot/variants/ocelot/Makefile.mk
index 3fdd4642c0..1ec5666ec1 100644
--- a/src/mainboard/google/ocelot/variants/ocelot/Makefile.mk
+++ b/src/mainboard/google/ocelot/variants/ocelot/Makefile.mk
@@ -4,6 +4,7 @@ bootblock-y += gpio.c
 romstage-y += gpio.c
 romstage-y += memory.c
 romstage-$(CONFIG_FW_CONFIG) += fw_config.c
+romstage-$(CONFIG_CHROMEOS_DRAM_PART_NUMBER_IN_CBI) += part_num_to_dram_id.c
 ramstage-y += gpio.c
 romstage-$(CONFIG_FW_CONFIG) += variant.c
 ramstage-$(CONFIG_FW_CONFIG) += variant.c
diff --git a/src/mainboard/google/ocelot/variants/ocelot/memory.c b/src/mainboard/google/ocelot/variants/ocelot/memory.c
index 7ac5ce95fd..43f40a9629 100644
--- a/src/mainboard/google/ocelot/variants/ocelot/memory.c
+++ b/src/mainboard/google/ocelot/variants/ocelot/memory.c
@@ -82,7 +82,7 @@ const struct mb_cfg *variant_memory_params(void)
 void variant_get_spd_info(struct mem_spd *spd_info)
 {
 	uint32_t id = board_id() & BOARD_ID_MASK;
-	spd_info->cbfs_index = 0;
+	spd_info->cbfs_index = variant_memory_sku();
 
 	switch (id) {
 	case BOARD_ID_DDR5:
diff --git a/src/mainboard/google/ocelot/variants/ocelot/part_num_to_dram_id.c b/src/mainboard/google/ocelot/variants/ocelot/part_num_to_dram_id.c
new file mode 100644
index 0000000000..c73e5c9a12
--- /dev/null
+++ b/src/mainboard/google/ocelot/variants/ocelot/part_num_to_dram_id.c
@@ -0,0 +1,35 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <baseboard/variants.h>
+
+struct part_num_spd_index {
+	const char part_num[DIMM_INFO_PART_NUMBER_SIZE];
+	int spd_index;
+};
+
+static const struct part_num_spd_index part_number_map[] = {
+	{ "H58G56BK8BX068", 0 },
+	{ "H58G66BK7BX067", 1 },
+	{ "H58G66BK8BX067", 2 },
+	{ "H58GE6AK8BX104", 3 },
+	{ "H58G66CK8BX147", 2 },
+};
+
+int variant_memory_sku(void)
+{
+	int index;
+	size_t num_elements = ARRAY_SIZE(part_number_map);
+	const char *part_num = mainboard_get_dram_part_num();
+
+	if (part_num == NULL)
+		die("No part number in CBI, halting boot.\n");
+
+	for (index = 0; index < num_elements; index++) {
+		if (!strcmp(part_num, part_number_map[index].part_num))
+			/* exact match found */
+			return part_number_map[index].spd_index;
+	}
+
+	/* We didn't find a match for part_num, halt boot */
+	die("No part number found looking for %s, halting boot.\n", part_num);
+}

From e3a2d1cecff285a5b568a0551316d969ae378317 Mon Sep 17 00:00:00 2001
From: Subrata Banik <subratabanik@google.com>
Date: Tue, 23 Sep 2025 18:08:58 +0530
Subject: [PATCH 2082/3886] soc/qualcomm/qclib: Improve logging on invalid MRC
 cache data

This patch downgrades the message severity from BIOS_ERR to
BIOS_WARNING when mrc_cache_load_current() returns an invalid size
(typically during the first boot or after firmware update).

The failure to load previously saved MRC training data from flash is
often non-fatal, as the system can typically proceed to perform a full
memory training run. Therefore, a warning is more appropriate.

The message is also updated to provide crucial diagnostic information,
including the actual and expected data sizes, which aids in debugging
cache corruption or version mismatch issues.

w/o this patch

```
[ERROR]  Unable to load previous training data.
```

w/ this patch

```
[WARN ]  qclib: Invalid MRC data in flash (size: 0xffffffffffffffff, expected: 0x10000)
```

Change-Id: I810c868adf923e4527abe06a857b15950aa8f17a
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89315
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
---
 src/soc/qualcomm/common/qclib.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/src/soc/qualcomm/common/qclib.c b/src/soc/qualcomm/common/qclib.c
index 1daa14b328..fa12ed9634 100644
--- a/src/soc/qualcomm/common/qclib.c
+++ b/src/soc/qualcomm/common/qclib.c
@@ -259,7 +259,8 @@ void qclib_load_and_run(void)
 	data_size = mrc_cache_load_current(MRC_TRAINING_DATA, QCLIB_VERSION,
 					   _ddr_training, REGION_SIZE(ddr_training));
 	if (data_size < 0) {
-		printk(BIOS_ERR, "Unable to load previous training data.\n");
+		printk(BIOS_WARNING, "qclib: Invalid MRC data in flash (size: %#zx, expected: %#zx)\n",
+		       data_size, REGION_SIZE(ddr_training));
 		memset(_ddr_training, 0, REGION_SIZE(ddr_training));
 		data_size = REGION_SIZE(ddr_training);
 	}

From 8e9ec16f4538ff06a20e566ca7c87b8e40a2d966 Mon Sep 17 00:00:00 2001
From: Luca Lai <luca.lai@lcfc.corp-partner.google.com>
Date: Wed, 17 Sep 2025 13:39:34 +0800
Subject: [PATCH 2083/3886] mb/google/trulo/var/pujjolo: Add tablet mode fw
 config for ish fw

Use fw config bit 15 to identify different ish files when enable
or disable tablet mode.

TABLET_ENABLE  : pujjolo_ish.bin
TABLET_DISABLE : lite_ish.bin

BUG=b:432649211
TEST=Build and boot to OS, check pujjolo and pujjoquince load
corresponding ish file using command ectool --name=cros_ish version
and test warmboot/coldboot/suspend pass.

Change-Id: Iffaadd5c772be6306cdcec08385de90c089f0489
Signed-off-by: Luca Lai <luca.lai@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89215
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Derek Huang <derekhuang@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
---
 .../google/brya/variants/pujjolo/overridetree.cb | 16 ++++++++--------
 1 file changed, 8 insertions(+), 8 deletions(-)

diff --git a/src/mainboard/google/brya/variants/pujjolo/overridetree.cb b/src/mainboard/google/brya/variants/pujjolo/overridetree.cb
index b897edbd5d..60f6393c48 100644
--- a/src/mainboard/google/brya/variants/pujjolo/overridetree.cb
+++ b/src/mainboard/google/brya/variants/pujjolo/overridetree.cb
@@ -4,6 +4,10 @@ fw_config
 		option LTE_PRESENT		1
 		option 5G_PRESENT		2
 	end
+	field TABLET_MODE 15
+		option TABLET_MODE_DISABLE		0
+		option TABLET_MODE_ENABLE		1
+	end
 	field WIFI_SAR_ID 17 20
 		option WIFI_SAR_TABLE_PUJJOLO_AX211		0
 		option WIFI_SAR_TABLE_PUJJOLO_BE200		1
@@ -26,10 +30,6 @@ fw_config
 		option WFC_ABSENT               0
 		option WFC_MIPI_OVTI8856        1
 	end
-	field ISH 29
-		option ISH_ABSENT	0
-		option ISH_PRESENT	1
-	end
 end
 chip soc/intel/alderlake
 
@@ -516,17 +516,17 @@ chip soc/intel/alderlake
 		end
 		device ref ish on
 			chip drivers/intel/ish
-				register "add_acpi_dma_property" = "true"
 				register "firmware_name" = ""pujjolo_ish.bin""
+				register "add_acpi_dma_property" = "true"
 				device generic 1 on
-					probe ISH ISH_PRESENT
+					probe TABLET_MODE TABLET_MODE_ENABLE
 				end
 			end
 			chip drivers/intel/ish
-				register "add_acpi_dma_property" = "true"
 				register "firmware_name" = ""lite_ish.bin""
+				register "add_acpi_dma_property" = "true"
 				device generic 0 on
-					probe ISH ISH_ABSENT
+					probe TABLET_MODE TABLET_MODE_DISABLE
 				end
 			end
 		end

From c4627e0ddaf340eae822e33bed10ba1417660aff Mon Sep 17 00:00:00 2001
From: Sowmya Aralguppe <sowmya.aralguppe@intel.com>
Date: Mon, 22 Sep 2025 14:50:09 +0530
Subject: [PATCH 2084/3886] mb/google/ocelot: Remove FP_PRESENT probe from ISH
 device configuration

The FP_PRESENT probe is not required for the ISH device as they are not
in the same BDF. ISH is in the rootport 0:18:0 and gspi0 is 0:30:2.

Change-Id: I00ee0825f60719fb5a34a215780a14645def8b4c
Signed-off-by: Sowmya Aralguppe <sowmya.aralguppe@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89289
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Pranava Y N <pranavayn@google.com>
Reviewed-by: Avi Uday <aviuday@google.com>
---
 src/mainboard/google/ocelot/variants/ocelot/overridetree.cb | 1 -
 1 file changed, 1 deletion(-)

diff --git a/src/mainboard/google/ocelot/variants/ocelot/overridetree.cb b/src/mainboard/google/ocelot/variants/ocelot/overridetree.cb
index 011b03352a..d466d836e5 100644
--- a/src/mainboard/google/ocelot/variants/ocelot/overridetree.cb
+++ b/src/mainboard/google/ocelot/variants/ocelot/overridetree.cb
@@ -379,7 +379,6 @@ chip soc/intel/pantherlake
 
 		device ref ish on
 			probe ISH ISH_ENABLE
-			probe FP FP_PRESENT
 			chip drivers/intel/ish
 				register "add_acpi_dma_property" = "true"
 				device generic 0 on end

From 59bd0e3206549d22fa95231f8d96aba392b70f1e Mon Sep 17 00:00:00 2001
From: Sowmya Aralguppe <sowmya.aralguppe@intel.com>
Date: Mon, 4 Aug 2025 11:55:56 +0530
Subject: [PATCH 2085/3886] mb/google/ocelot/var/ocelot: Update USB and TCSS
 port configuration

The list of changes are as follows
1. Modified USB2 port 7 from M.2 WLAN to discrete Bluetooth device.
2. Updated both Type-C ports to OC_SKIP to reflect virtual ports.
3. Adjusted Type-C port ACPI group assignments for USB3 ports.
4. Reduced display device count from 5 to 4 by removing DD04.
5. Updated comments and port usage to clarify Type-A and Type-C port
   assignments.

Schematic version: schematic_1433518
Platform Mapping Document : Rev0p86

BUG=b: None
TEST= Build Ocelot and verify it compiles without any error.

Change-Id: I1e8cc92463a462c9baa78cd6d79637004340f7e2
Signed-off-by: Sowmya Aralguppe <sowmya.aralguppe@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88642
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Pranava Y N <pranavayn@google.com>
---
 .../variants/baseboard/ocelot/devicetree.cb    |  2 --
 .../ocelot/variants/ocelot/overridetree.cb     | 18 +++++++-----------
 2 files changed, 7 insertions(+), 13 deletions(-)

diff --git a/src/mainboard/google/ocelot/variants/baseboard/ocelot/devicetree.cb b/src/mainboard/google/ocelot/variants/baseboard/ocelot/devicetree.cb
index 75c7641552..e2ea33173b 100644
--- a/src/mainboard/google/ocelot/variants/baseboard/ocelot/devicetree.cb
+++ b/src/mainboard/google/ocelot/variants/baseboard/ocelot/devicetree.cb
@@ -28,8 +28,6 @@ chip soc/intel/pantherlake
 
 	register "tcss_ports[0]" = "TCSS_PORT_EMPTY"	# Disable USB-C Port 0
 	register "tcss_ports[1]" = "TCSS_PORT_EMPTY"	# Disable USB-C Port 1
-	register "tcss_ports[2]" = "TCSS_PORT_EMPTY"	# Disable USB-C Port 2
-	register "tcss_ports[3]" = "TCSS_PORT_EMPTY"	# Disable USB-C Port 3
 
 	# Enable SAGv
 	register "sagv" = "SAGV_ENABLED"
diff --git a/src/mainboard/google/ocelot/variants/ocelot/overridetree.cb b/src/mainboard/google/ocelot/variants/ocelot/overridetree.cb
index d466d836e5..d7564f4602 100644
--- a/src/mainboard/google/ocelot/variants/ocelot/overridetree.cb
+++ b/src/mainboard/google/ocelot/variants/ocelot/overridetree.cb
@@ -69,14 +69,13 @@ chip soc/intel/pantherlake
 	register "usb2_ports[4]" = "USB2_PORT_MID(OC0)" # 2x5 USB2 HDR
 	register "usb2_ports[5]" = "USB2_PORT_MID(OC0)" # 2x5 USB2 HDR
 	register "usb2_ports[6]" = "USB2_PORT_MID(OC0)" # FPS
-	register "usb2_ports[7]" = "USB2_PORT_MID(OC0)" # M.2 WLAN
+	register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # Discrete Bluetooth
 
 	register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)" # USB 3.2 Gen2 x1 Type-A Con - # 1
 	register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC0)" # USB 3.2 Gen2 x1 Type-A Con - # 2 (redriver topology)
-	#register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC0)" # TCSS Module - Type-A over TCP module
 
-	register "tcss_ports[0]" = "TCSS_PORT_DEFAULT(OC0)"
-	register "tcss_ports[1]" = "TCSS_PORT_DEFAULT(OC_SKIP)"
+	register "tcss_ports[0]" = "TCSS_PORT_DEFAULT(OC_SKIP)" # Type-C Port 1 (Virtual OC)
+	register "tcss_ports[1]" = "TCSS_PORT_DEFAULT(OC_SKIP)" # Type-C Port 2 (Virtual OC)
 
 	register "tcss_cap_policy[0]" = "TCSS_TYPE_C_PORT_FULL_FUN"
 	register "tcss_cap_policy[1]" = "TCSS_TYPE_C_PORT_FULL_FUN"
@@ -129,7 +128,7 @@ chip soc/intel/pantherlake
 			probe DISPLAY DISPLAY_TOUCH_PRESENT
 			probe DISPLAY DISPLAY_NO_TOUCH_PRESENT
 			chip drivers/gfx/generic
-				register "device_count" = "5"
+				register "device_count" = "4"
 				# DDIA for eDP
 				register "device[0].name" = ""LCD0""
 				register "device[0].type" = "panel"
@@ -144,10 +143,7 @@ chip soc/intel/pantherlake
 				register "device[3].name" = ""DD03""
 				register "device[3].use_pld" = "true"
 				register "device[3].pld" = "ACPI_PLD_TYPE_C(LEFT, RIGHT, ACPI_PLD_GROUP(2, 1))"
-				# TCP2 (DP-3) for port C2
-				register "device[4].name" = ""DD04""
-				register "device[4].use_pld" = "true"
-				register "device[4].pld" = "ACPI_PLD_TYPE_C(RIGHT, LEFT, ACPI_PLD_GROUP(3, 1))"
+
 				device generic 0 on end
 			end
 		end
@@ -351,13 +347,13 @@ chip soc/intel/pantherlake
 					chip drivers/usb/acpi
 						register "desc" = ""USB3 Type-C Port C0""
 						register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
-						register "group" = "ACPI_PLD_GROUP(4, 2)"
+						register "group" = "ACPI_PLD_GROUP(2, 2)"
 						device ref tcss_usb3_port0 on end
 					end
 					chip drivers/usb/acpi
 						register "desc" = ""USB3 Type-C Port C1""
 						register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
-						register "group" = "ACPI_PLD_GROUP(3, 2)"
+						register "group" = "ACPI_PLD_GROUP(1, 2)"
 						device ref tcss_usb3_port1 on end
 					end
 				end

From 36d2dc7cb95e3a130f3c6f92028f281ce1d34d14 Mon Sep 17 00:00:00 2001
From: Sowmya Aralguppe <sowmya.aralguppe@intel.com>
Date: Mon, 22 Sep 2025 11:18:21 +0530
Subject: [PATCH 2086/3886] mb/google/ocelot: Update wake event mapping for
 gspi0

This change corrects the ACPI wake event mapping for the gspi0 device,
ensuring the wake signal is routed through GPE0_DW2_19 instead of
GPE0_DW1_19. This aligns with the platform's GPIO-to-GPE mapping in
devicetree.cb

Change-Id: I2c9b0168c01c4ff8f968f0efe5bc12b650842129
Signed-off-by: Sowmya Aralguppe <sowmya.aralguppe@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89287
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Avi Uday <aviuday@google.com>
Reviewed-by: Pranava Y N <pranavayn@google.com>
---
 src/mainboard/google/ocelot/variants/ocelot/overridetree.cb | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/mainboard/google/ocelot/variants/ocelot/overridetree.cb b/src/mainboard/google/ocelot/variants/ocelot/overridetree.cb
index d7564f4602..8867ca2178 100644
--- a/src/mainboard/google/ocelot/variants/ocelot/overridetree.cb
+++ b/src/mainboard/google/ocelot/variants/ocelot/overridetree.cb
@@ -541,7 +541,7 @@ chip soc/intel/pantherlake
 				register "uid" = "1"
 				register "compat_string" = ""google,cros-ec-spi""
 				register "irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_E19_IRQ)"
-				register "wake" = "GPE0_DW1_19"
+				register "wake" = "GPE0_DW2_19"
 				register "has_power_resource" = "true"
 				register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C15)"
 				register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E05)"

From 3a33217349b4f2e43de758c10e947729b0bb50d9 Mon Sep 17 00:00:00 2001
From: Hualin Wei <weihualin@huaqin.corp-partner.google.com>
Date: Mon, 22 Sep 2025 20:21:23 +0800
Subject: [PATCH 2087/3886] mb/google/fatcat/var/lapis: Update thermal strategy

According to the schematic diagram, lapis is designed
with five temperature detection nodes, so the initial
thermal strategy was updated.

BUG=b:438785495
TEST=emerge-fatcat coreboot

Change-Id: I908ab68766ef562ecc95085ed21658f3592937f4
Signed-off-by: Hualin Wei <weihualin@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89068
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Pranava Y N <pranavayn@google.com>
---
 .../fatcat/variants/lapis/overridetree.cb     | 31 ++++++++++++++-----
 1 file changed, 23 insertions(+), 8 deletions(-)

diff --git a/src/mainboard/google/fatcat/variants/lapis/overridetree.cb b/src/mainboard/google/fatcat/variants/lapis/overridetree.cb
index cf2ad628fa..f86cf47a79 100644
--- a/src/mainboard/google/fatcat/variants/lapis/overridetree.cb
+++ b/src/mainboard/google/fatcat/variants/lapis/overridetree.cb
@@ -65,10 +65,11 @@ chip soc/intel/pantherlake
 		device ref dtt on
 			chip drivers/intel/dptf
 				## sensor information
-				register "options.tsr[0].desc" = ""DDR_SOC""
-				register "options.tsr[1].desc" = ""Ambient""
-				register "options.tsr[2].desc" = ""Charger""
-				register "options.tsr[3].desc" = ""wwan""
+				register "options.tsr[0].desc" = ""VR""
+				register "options.tsr[1].desc" = ""DDR""
+				register "options.tsr[2].desc" = ""Top""
+				register "options.tsr[3].desc" = ""SSD""
+				register "options.tsr[4].desc" = ""Charger""
 
 				## Active Policy
 				# FIXME: below values are initial reference values only
@@ -108,6 +109,18 @@ chip soc/intel/pantherlake
 							},
 						[3] = {
 							.target = DPTF_TEMP_SENSOR_3,
+							.thresholds = {
+									TEMP_PCT(75, 90),
+									TEMP_PCT(70, 80),
+									TEMP_PCT(65, 70),
+									TEMP_PCT(60, 60),
+									TEMP_PCT(55, 50),
+									TEMP_PCT(50, 40),
+									TEMP_PCT(45, 30),
+								}
+							},
+						[4] = {
+							.target = DPTF_TEMP_SENSOR_4,
 							.thresholds = {
 									TEMP_PCT(75, 90),
 									TEMP_PCT(70, 80),
@@ -128,16 +141,18 @@ chip soc/intel/pantherlake
 						[2] = DPTF_PASSIVE(CPU,         TEMP_SENSOR_1, 80, 5000),
 						[3] = DPTF_PASSIVE(CHARGER,     TEMP_SENSOR_2, 75, 5000),
 						[4] = DPTF_PASSIVE(CPU,         TEMP_SENSOR_3, 80, 5000),
+						[5] = DPTF_PASSIVE(CPU,         TEMP_SENSOR_4, 80, 5000),
 				}"
 
 				## Critical Policy
 				# TODO: below values are initial reference values only
 				register "policies.critical" = "{
 						[0] = DPTF_CRITICAL(CPU,          105, SHUTDOWN),
-						[1] = DPTF_CRITICAL(TEMP_SENSOR_0, 85, SHUTDOWN),
-						[2] = DPTF_CRITICAL(TEMP_SENSOR_1, 85, SHUTDOWN),
-						[3] = DPTF_CRITICAL(TEMP_SENSOR_2, 85, SHUTDOWN),
-						[4] = DPTF_CRITICAL(TEMP_SENSOR_3, 85, SHUTDOWN),
+						[1] = DPTF_CRITICAL(TEMP_SENSOR_0, 91, SHUTDOWN),
+						[2] = DPTF_CRITICAL(TEMP_SENSOR_1, 91, SHUTDOWN),
+						[3] = DPTF_CRITICAL(TEMP_SENSOR_2, 91, SHUTDOWN),
+						[4] = DPTF_CRITICAL(TEMP_SENSOR_3, 91, SHUTDOWN),
+						[5] = DPTF_CRITICAL(TEMP_SENSOR_4, 91, SHUTDOWN),
 				}"
 
 				## Power Limits Control

From eb3497fae4815b3749cc3935363ddac3e61052b1 Mon Sep 17 00:00:00 2001
From: Hualin Wei <weihualin@huaqin.corp-partner.google.com>
Date: Mon, 22 Sep 2025 20:29:48 +0800
Subject: [PATCH 2088/3886] mb/google/fatcat/var/lapis: Update tpm i2c
 configuration

Make I2C3 enabled for early init.

BUG=b:438785495
TEST=emerge-fatcat coreboot

Change-Id: Ia5a48dde252f8d1dc552229bc2d33f1e7adf2e98
Signed-off-by: Hualin Wei <weihualin@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89290
Reviewed-by: Pranava Y N <pranavayn@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/google/fatcat/variants/lapis/overridetree.cb | 1 +
 1 file changed, 1 insertion(+)

diff --git a/src/mainboard/google/fatcat/variants/lapis/overridetree.cb b/src/mainboard/google/fatcat/variants/lapis/overridetree.cb
index f86cf47a79..429c546e99 100644
--- a/src/mainboard/google/fatcat/variants/lapis/overridetree.cb
+++ b/src/mainboard/google/fatcat/variants/lapis/overridetree.cb
@@ -57,6 +57,7 @@ chip soc/intel/pantherlake
 	register "common_soc_config" = "{
 		.logo_valignment = FW_SPLASH_VALIGNMENT_MIDDLE,
 		.i2c[3] = {
+			.early_init=1,
 			.speed = I2C_SPEED_FAST,
 		},
 	}"

From 78fb910fe2a21ffe7e78954f801fd3ef57a3c519 Mon Sep 17 00:00:00 2001
From: Hualin Wei <weihualin@huaqin.corp-partner.google.com>
Date: Mon, 22 Sep 2025 20:38:54 +0800
Subject: [PATCH 2089/3886] mb/google/fatcat/var/lapis: Update the
 configuration of fw_config

Use fw_config to probe WIFI and STORAGE Type. And Add get_wifi_sar_cbfs
filename function.

BUG=b:438785495
TEST=emerge-fatcat coreboot

Change-Id: If59e4ae2f328585525f3651699f84a4000e93dc5
Signed-off-by: Hualin Wei <weihualin@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89291
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Pranava Y N <pranavayn@google.com>
---
 .../google/fatcat/variants/lapis/Makefile.mk  |  2 +
 .../google/fatcat/variants/lapis/fw_config.c  |  9 ++++
 .../fatcat/variants/lapis/overridetree.cb     | 47 ++++++++++++++++++-
 3 files changed, 57 insertions(+), 1 deletion(-)
 create mode 100644 src/mainboard/google/fatcat/variants/lapis/fw_config.c

diff --git a/src/mainboard/google/fatcat/variants/lapis/Makefile.mk b/src/mainboard/google/fatcat/variants/lapis/Makefile.mk
index 4c33dad4db..dcd5ec7202 100644
--- a/src/mainboard/google/fatcat/variants/lapis/Makefile.mk
+++ b/src/mainboard/google/fatcat/variants/lapis/Makefile.mk
@@ -4,3 +4,5 @@ bootblock-y += gpio.c
 romstage-y += gpio.c
 romstage-y += memory.c
 ramstage-y += gpio.c
+romstage-$(CONFIG_FW_CONFIG) += fw_config.c
+ramstage-$(CONFIG_FW_CONFIG) += fw_config.c
diff --git a/src/mainboard/google/fatcat/variants/lapis/fw_config.c b/src/mainboard/google/fatcat/variants/lapis/fw_config.c
new file mode 100644
index 0000000000..4221a5bf8e
--- /dev/null
+++ b/src/mainboard/google/fatcat/variants/lapis/fw_config.c
@@ -0,0 +1,9 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <fw_config.h>
+#include <sar.h>
+
+const char *get_wifi_sar_cbfs_filename(void)
+{
+	return get_wifi_sar_fw_config_filename(FW_CONFIG_FIELD(WIFI));
+}
diff --git a/src/mainboard/google/fatcat/variants/lapis/overridetree.cb b/src/mainboard/google/fatcat/variants/lapis/overridetree.cb
index 429c546e99..4d40ef9f7a 100644
--- a/src/mainboard/google/fatcat/variants/lapis/overridetree.cb
+++ b/src/mainboard/google/fatcat/variants/lapis/overridetree.cb
@@ -1,3 +1,41 @@
+fw_config
+	field WIFI 2 3
+		option WIFI_CNVI_7		0
+		option WIFI_CNVI_7E		1
+	end
+	field TOUCHSCREEN 4 5
+		option NONE_TOUCH	0
+		option 14_TOUCH		1
+	end
+	field TOUCHPAD 6 7
+		option TOUCHPAD_UNKNOWN		0
+		option TOUCHPAD_LPSS_I2C	1
+		option TOUCHPAD_THC_I2C		2
+	end
+	field STORAGE 8 9
+		option STORAGE_UNKNOWN		0
+		option STORAGE_NVME_GEN4	1
+		option STORAGE_NVME_GEN5	2
+		option STORAGE_UFS		3
+	end
+	field KB 10 11
+		option KB_UNKNOWN	0
+		option KB_BL		1
+	end
+	field UFC 12 13
+		option UFC_UNKNOWN	0
+		option UFC_1080P	1
+	end
+	field FP 14 15
+		option FP_ABSENT	0
+		option FP_PRESENT	1
+	end
+	field STYLUS 16 16
+		option STYLUS_ABSENT	0
+		option STYLUS_PRESENT	1
+	end
+end
+
 chip soc/intel/pantherlake
 
 	register "power_limits_config[PTL_CORE_1]" = "{
@@ -331,6 +369,8 @@ chip soc/intel/pantherlake
 		end
 
 		device ref pcie_rp9 on
+			probe STORAGE STORAGE_UNKNOWN
+			probe STORAGE STORAGE_NVME_GEN4
 			register "pcie_rp[PCIE_RP(9)]" = "{
 			.clk_src = 0,
 			.clk_req = 0,
@@ -344,6 +384,8 @@ chip soc/intel/pantherlake
 		end # Gen4 SSD
 
 		device ref cnvi_wifi on
+			probe WIFI WIFI_CNVI_7
+			probe WIFI WIFI_CNVI_7E
 			chip drivers/wifi/generic
 				register "wake" = "GPE0_PME_B0"
 				register "add_acpi_dma_property" = "true"
@@ -353,7 +395,10 @@ chip soc/intel/pantherlake
 			end
 		end # CNVi
 
-		device ref cnvi_bluetooth on end
+		device ref cnvi_bluetooth on
+			probe WIFI WIFI_CNVI_7
+			probe WIFI WIFI_CNVI_7E
+		end
 
 		device ref thc0 on
 			register "thc_wake_on_touch[0]" = "true"

From c822148f2ba3f12336c719d7ec3f54109e75ac2e Mon Sep 17 00:00:00 2001
From: weihualin <weihualin@huaqin.corp-partner.google.com>
Date: Fri, 19 Sep 2025 09:35:16 +0800
Subject: [PATCH 2090/3886] mb/google/fatcat/var/lapis: Modify dq/dqs setting

Modify the memory's DQ/DQS setting according to the lapis circuit schematic.

BUG=b:438785495
Test='emerge-fatcat coreboot' and DUT can boot into kernel
Change-Id: I9b93fdda4c37327a89af2096a6549e9077dfb12a
Signed-off-by: weihualin <weihualin@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89288
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Pranava Y N <pranavayn@google.com>
---
 .../google/fatcat/variants/lapis/memory.c     | 36 +++++++++----------
 1 file changed, 18 insertions(+), 18 deletions(-)

diff --git a/src/mainboard/google/fatcat/variants/lapis/memory.c b/src/mainboard/google/fatcat/variants/lapis/memory.c
index f2a03ae4ea..4e2a1536ae 100644
--- a/src/mainboard/google/fatcat/variants/lapis/memory.c
+++ b/src/mainboard/google/fatcat/variants/lapis/memory.c
@@ -9,45 +9,45 @@ static const struct mb_cfg lp5_mem_config = {
 
 	.lpx_dq_map = {
 		.ddr0 = {
-			.dq0 = {  13,  14,  12,  15, 11,  10,  8,  9, },
-			.dq1 = {  7,  5,  4,  6,  0,  3,  1,  2 },
+			.dq0 = {  8,  10,  9,  11, 15,  12,  13,  14, },
+			.dq1 = {  6,  5,  7,  4,  3,  1,  0,  2 },
 		},
 		.ddr1 = {
-			.dq0 = {  1,  3,  0,  2,  7,  4,  6,  5, },
-			.dq1 = {  12,  13,  14,  15,  11,  10,  9,  8 },
+			.dq0 = {  0,  1,  2,  3,  4,  7,  5,  6, },
+			.dq1 = {  14,  13,  12,  15,  8,  9,  11,  10 },
 		},
 		.ddr2 = {
-			.dq0 = {  0,  2,  1,  3,  6,  4,  7,  5 },
-			.dq1 = {  14,  13,  15,  12,  8,  11,  10,  9, },
+			.dq0 = {  10,  9,  11,  8,  15,  12,  14,  13 },
+			.dq1 = {  6,  5,  4,  7,  1,  3,  0,  2, },
 		},
 		.ddr3 = {
-			.dq0 = {  6,  5,  7,  4,  2,  3,  1,  0, },
-			.dq1 = {  10,  8,  11,  9,  12,  15,  13,  14 },
+			.dq0 = {  5,  7,  4,  6,  3,  1,  0,  2, },
+			.dq1 = {  13,  14,  11,  12,  9,  8,  15,  10 },
 		},
 		.ddr4 = {
-			.dq0 = {  2,  1,  3,  0,  4,  7,  5,  6 },
-			.dq1 = {  15,  14,  12,  13,  9,  11,  10,  8, },
+			.dq0 = {  8,  9,  10,  11,  15,  12,  14,  13 },
+			.dq1 = {  6,  5,  4,  7,  2,  1,  3,  0, },
 		},
 		.ddr5 = {
-			.dq0 = {  6,  5,  7,  4,  3,  1,  0,  2, },
-			.dq1 = {  10,  9,  11,  8,  13,  14,  12,  15 },
+			.dq0 = {  0,  1,  3,  2,  5,  4,  6,  7, },
+			.dq1 = {  9,  8,  11,  10,  13,  15,  14,  12 },
 		},
 		.ddr6 = {
-			.dq0 = {  9,  10,  11,  8,  14,  12,  13, 15, },
-			.dq1 = {  0,  1,  2,  3,  5,  7,  4,  6 },
+			.dq0 = {  10,  11,  9,  8,  15,  12,  14, 13, },
+			.dq1 = {  6,  5,  7,  4,  2,  3,  0,  1 },
 		},
 		.ddr7 = {
-			.dq0 = {  0,  1,  2,  3,  7,  5,  6,  4, },
-			.dq1 = {  14,  13,  15,  12,  10,  8,  11,  9 },
+			.dq0 = {  0,  2,  3,  1,  7,  4,  5,  6, },
+			.dq1 = {  15,  14,  13,  12,  10,  11,  9,  8 },
 		},
 	},
 
 	.lpx_dqs_map = {
 		.ddr0 = { .dqs0 = 1, .dqs1 = 0 },
 		.ddr1 = { .dqs0 = 0, .dqs1 = 1 },
-		.ddr2 = { .dqs0 = 0, .dqs1 = 1 },
+		.ddr2 = { .dqs0 = 1, .dqs1 = 0 },
 		.ddr3 = { .dqs0 = 0, .dqs1 = 1 },
-		.ddr4 = { .dqs0 = 0, .dqs1 = 1 },
+		.ddr4 = { .dqs0 = 1, .dqs1 = 0 },
 		.ddr5 = { .dqs0 = 0, .dqs1 = 1 },
 		.ddr6 = { .dqs0 = 1, .dqs1 = 0 },
 		.ddr7 = { .dqs0 = 0, .dqs1 = 1 }

From 3d7b898ff4c0322c450745375fd437370de7ba6d Mon Sep 17 00:00:00 2001
From: "P, Usha" <usha.p@intel.com>
Date: Wed, 20 Aug 2025 10:04:39 +0530
Subject: [PATCH 2091/3886] mb/google/ocelot/var/ocelot: Disable ALC721 clock
 stop support

This change allows flag to be overridden via devicetree, instead of
relying on the default value in alc711_slave. It helps fix the
missing event issue when plugging or unplugging the 3.5mm headphone
jack.

TEST=Verified build and boot with ALC721.
Headphone path switches successfully via audio jack event.

Change-Id: Ib766363fd7462bb03905fa6cba805b27d10efa04
Signed-off-by: P, Usha <usha.p@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88867
Reviewed-by: Pranava Y N <pranavayn@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/google/ocelot/variants/ocelot/overridetree.cb | 1 +
 1 file changed, 1 insertion(+)

diff --git a/src/mainboard/google/ocelot/variants/ocelot/overridetree.cb b/src/mainboard/google/ocelot/variants/ocelot/overridetree.cb
index 8867ca2178..7a06471ea3 100644
--- a/src/mainboard/google/ocelot/variants/ocelot/overridetree.cb
+++ b/src/mainboard/google/ocelot/variants/ocelot/overridetree.cb
@@ -564,6 +564,7 @@ chip soc/intel/pantherlake
 						register "alc711_address.version" = "SOUNDWIRE_VERSION_1_2"
 						register "alc711_address.class" = "MIPI_CLASS_SDCA"
 						register "alc711_address.part_id" = "MIPI_DEV_ID_REALTEK_ALC721"
+						register "disable_clkstop_sm_support" = "true"
 						# SoundWire Link 3 ID 1
 						device generic 3.1 on
 							probe AUDIO AUDIO_ALC721_SNDW

From 21ca3c5f3de713f8d1195bbc132122198847a241 Mon Sep 17 00:00:00 2001
From: Bora Guvendik <bora.guvendik@intel.com>
Date: Fri, 19 Sep 2025 20:03:41 -0700
Subject: [PATCH 2092/3886] mb/intel/ptlrvp: Update CKD/QCK mapping parameters
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

The commit updates the DDR5 memory initialization parameters for the
Intel PTLRVP mainboard. Specifically, the ChannelToCkdQckMapping and
PhyClockToCkdDimm settings are overridden to ensure accurate mapping of
memory channels and PHY clocks to their respective Clock Driver and
DIMM connections.

BUG=none
TEST=Boot the PTLRVP board with DDR5 memory and verify memory
initialization.

Change-Id: I1be0a66a40e2613f10426dacd5494e345c5579db
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89275
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
---
 src/mainboard/intel/ptlrvp/romstage.c | 23 ++++++++++++++++++++---
 1 file changed, 20 insertions(+), 3 deletions(-)

diff --git a/src/mainboard/intel/ptlrvp/romstage.c b/src/mainboard/intel/ptlrvp/romstage.c
index 171465ec12..1172f006cb 100644
--- a/src/mainboard/intel/ptlrvp/romstage.c
+++ b/src/mainboard/intel/ptlrvp/romstage.c
@@ -23,13 +23,14 @@ __weak void variant_update_soc_memory_init_params(FSPM_UPD *memupd)
 	/* Nothing to do */
 }
 
-static void update_ddr5_sagv_points(FSP_M_CONFIG *m_cfg)
+static void update_ddr5_memory_params(FSP_M_CONFIG *m_cfg)
 {
 	int board_id = get_rvp_board_id();
 
 	if (board_id != PTLP_DDR5_RVP)
 		return;
 
+	/* Override FSP-M SaGv frequency and gear for DDR5 boards */
 	m_cfg->SaGvFreq[0] = 3200;
 	m_cfg->SaGvGear[0] = GEAR_4;
 
@@ -41,6 +42,22 @@ static void update_ddr5_sagv_points(FSP_M_CONFIG *m_cfg)
 
 	m_cfg->SaGvFreq[3] = 6400;
 	m_cfg->SaGvGear[3] = GEAR_4;
+
+	/*
+	 * Override FSP-M ChannelToCkdQckMapping to map memory channels
+	 * to Clock Driver (CKD) and Query Clock (QCK) signals.
+	 */
+	const uint8_t channel_to_ckd_qck[] = { 0, 0, 1, 0, 0, 0, 1, 0 };
+	memcpy(m_cfg->ChannelToCkdQckMapping,
+		   channel_to_ckd_qck, sizeof(channel_to_ckd_qck));
+
+	/*
+	 * Override FSP-M PhyClockToCkdDimm to map PHY clocks
+	 * to Clock Driver DIMM connections.
+	 */
+	const uint8_t phy_clock_to_ckd_dimm[] = { 0, 0, 0, 0, 0x8, 0, 0x8, 0 };
+	memcpy(m_cfg->PhyClockToCkdDimm,
+		   phy_clock_to_ckd_dimm, sizeof(phy_clock_to_ckd_dimm));
 }
 
 void mainboard_memory_init_params(FSPM_UPD *memupd)
@@ -61,8 +78,8 @@ void mainboard_memory_init_params(FSPM_UPD *memupd)
 
 	memcfg_init(memupd, mem_config, &spd_info, half_populated);
 
-	/* Override FSP-M SaGv frequency and gear for DDR5 boards */
-	update_ddr5_sagv_points(&memupd->FspmConfig);
+	/* Override FSP-M parameters for DDR5 boards */
+	update_ddr5_memory_params(&memupd->FspmConfig);
 
 	/* Override FSP-M UPD per board if required. */
 	variant_update_soc_memory_init_params(memupd);

From bbd72abae59cad321162f27f95cebd258946cc18 Mon Sep 17 00:00:00 2001
From: Kapil Porwal <kapilporwal@google.com>
Date: Mon, 22 Sep 2025 21:29:24 +0530
Subject: [PATCH 2093/3886] ec/google/chromeec: Update EC headers

Generated using update_ec_headers.sh [EC-DIR].

The original include/ec_commands.h version in the EC repo is:
  60aa7ccea9c include/ec_commands.h: Avoid lint errors
The original include/ec_cmd_api.h version in the EC repo is:
  f47d8af4fbb include/ec_cmd_api.h: Define new API for EC_CMD_AP_SHUTDOWN command

Change-Id: I31d08bf4a0318ca3ba8c5bb5563acfe65830523b
Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89296
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/ec/google/chromeec/ec_cmd_api.h  |  1 +
 src/ec/google/chromeec/ec_commands.h | 53 +++++++++++++++++++++++++++-
 2 files changed, 53 insertions(+), 1 deletion(-)

diff --git a/src/ec/google/chromeec/ec_cmd_api.h b/src/ec/google/chromeec/ec_cmd_api.h
index a74ba441e5..dd833e4605 100644
--- a/src/ec/google/chromeec/ec_cmd_api.h
+++ b/src/ec/google/chromeec/ec_cmd_api.h
@@ -260,6 +260,7 @@ _CROS_EC_C0_F_PF_RF(EC_CMD_ADC_READ, adc_read);
 _CROS_EC_CV_F_P(EC_CMD_ADD_ENTROPY, 0, add_entropy, rollback_add_entropy);
 _CROS_EC_C0_F_PF(EC_CMD_AP_FW_STATE, ap_fw_state);
 _CROS_EC_C0_F(EC_CMD_AP_RESET, ap_reset);
+_CROS_EC_C0_F(EC_CMD_AP_SHUTDOWN, ap_shutdown);
 _CROS_EC_CV_F_P(EC_CMD_BATTERY_CUT_OFF, 1, battery_cut_off_v1, battery_cutoff);
 _CROS_EC_C0_F(EC_CMD_BATTERY_CUT_OFF, battery_cut_off);
 _CROS_EC_CV_F_P_R(EC_CMD_BATTERY_GET_DYNAMIC, 0, battery_get_dynamic,
diff --git a/src/ec/google/chromeec/ec_commands.h b/src/ec/google/chromeec/ec_commands.h
index cff113c56f..fa17a4fb23 100644
--- a/src/ec/google/chromeec/ec_commands.h
+++ b/src/ec/google/chromeec/ec_commands.h
@@ -274,7 +274,8 @@ extern "C" {
  * EC_MEMMAP_BATT_LFCC if the actual value is unknown.
  *
  * This corresponds with the unknown value specified by ACPI release 6.5
- * 10.2.2 (and earlier versions), to match expectations of ACPI firmware.
+ * Section 10.2.2 (and earlier versions), to match expectations of ACPI
+ * firmware.
  */
 #define EC_MEMMAP_BATT_UNKNOWN_VALUE (-1)
 
@@ -6218,6 +6219,24 @@ struct ec_params_usb_pd_dps_control {
 	uint8_t enable;
 } __ec_align1;
 
+/*
+ * This command return the status of dynamic PDO selection.
+ */
+#define EC_CMD_USB_PD_DPS_STATUS 0x0107
+
+struct ec_response_usb_pd_dps_status {
+	int32_t is_enabled;
+	int32_t port;
+	int32_t requested_voltage;
+	int32_t requested_current;
+	int32_t input_power;
+	int32_t input_voltage;
+	int32_t input_current;
+	int32_t efficient_voltage;
+	int32_t battery_voltage;
+	int32_t max_voltage;
+} __ec_align4;
+
 /* Write USB-PD device FW */
 #define EC_CMD_USB_PD_FW_UPDATE 0x0110
 
@@ -8321,6 +8340,8 @@ struct ec_params_fp_passthru {
 	 FP_MODE_MATCH | FP_MODE_RESET_SENSOR | FP_MODE_SENSOR_MAINTENANCE | \
 	 FP_MODE_DONT_CHANGE)
 
+#define FP_MODES_WITH_AUTHENTICATION (FP_MODE_ENROLL_SESSION | FP_MODE_MATCH)
+
 /* Capture types defined in bits [30..26] */
 #define FP_MODE_CAPTURE_TYPE_SHIFT 26
 #define FP_MODE_CAPTURE_TYPE_MASK (0x1F << FP_MODE_CAPTURE_TYPE_SHIFT)
@@ -8364,10 +8385,17 @@ enum fp_capture_type {
 	(enum fp_capture_type)(((mode) & FP_MODE_CAPTURE_TYPE_MASK) >> \
 			       FP_MODE_CAPTURE_TYPE_SHIFT)
 
+#define FP_MAC_LENGTH 32
+
 struct ec_params_fp_mode {
 	uint32_t mode; /* as defined by FP_MODE_ constants */
 } __ec_align4;
 
+struct ec_params_fp_mode_v1 {
+	uint32_t mode; /* as defined by FP_MODE_ constants */
+	uint8_t mac[FP_MAC_LENGTH];
+} __ec_align4;
+
 struct ec_response_fp_mode {
 	uint32_t mode; /* as defined by FP_MODE_ constants */
 } __ec_align4;
@@ -8595,6 +8623,8 @@ struct ec_params_fp_seed {
 #define FP_CONTEXT_SESSION_NONCE_SET BIT(2)
 /* FP user_id had been set or not*/
 #define FP_CONTEXT_USER_ID_SET BIT(3)
+/* The operation authentication challenge was generated */
+#define FP_AUTH_CHALLENGE_SET BIT(4)
 
 struct ec_response_fp_encryption_status {
 	/* Used bits in encryption engine status */
@@ -8691,6 +8721,27 @@ struct ec_params_fp_establish_session {
 	uint8_t tag[FP_AES_KEY_TAG_BYTES];
 } __ec_align4;
 
+#define FP_CHALLENGE_SIZE 32
+
+#define EC_CMD_FP_GENERATE_CHALLENGE 0x0415
+struct ec_response_fp_generate_challenge {
+	uint8_t challenge[FP_CHALLENGE_SIZE];
+} __ec_align4;
+
+#define EC_CMD_FP_CONFIRM_TEMPLATE 0x0416
+struct ec_params_fp_confirm_template {
+	uint8_t mac[FP_MAC_LENGTH];
+} __ec_align4;
+
+#define EC_CMD_FP_SIGN_MATCH 0x0417
+struct ec_params_fp_sign_match {
+	uint8_t challenge[FP_CHALLENGE_SIZE];
+} __ec_align4;
+
+struct ec_response_fp_sign_match {
+	uint8_t signature[FP_MAC_LENGTH];
+} __ec_align4;
+
 /*****************************************************************************/
 /* Touchpad MCU commands: range 0x0500-0x05FF */
 

From 0d4c0ee7fc2d1705ff6663a2133ffa5c7323890e Mon Sep 17 00:00:00 2001
From: Kapil Porwal <kapilporwal@google.com>
Date: Wed, 17 Sep 2025 18:51:18 +0530
Subject: [PATCH 2094/3886] ec/google/chromeec: Add API for AP shutdown command

Adds the `google_chromeec_ap_poweroff()` helper function to the ChromeEC
driver.

This new API wraps the `EC_CMD_AP_SHUTDOWN` command and sends it to the
Embedded Controller (EC). This provides a cleaner, standardized way for
other coreboot components to initiate an Application Processor (AP)
power-off sequence via the EC.

After sending the shutdown command, the function calls `halt()` as the
AP is expected to power down immediately after the EC processes the
command.

BUG=b:439819922
TEST=Verify shutdown on Google/Quenbi.

Change-Id: Iace6a66972791bb7acdb978dfeea67b6ff0fec68
Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89223
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/ec/google/chromeec/ec.c | 7 +++++++
 src/ec/google/chromeec/ec.h | 2 ++
 2 files changed, 9 insertions(+)

diff --git a/src/ec/google/chromeec/ec.c b/src/ec/google/chromeec/ec.c
index 993bddf6ae..eeef4341f3 100644
--- a/src/ec/google/chromeec/ec.c
+++ b/src/ec/google/chromeec/ec.c
@@ -659,6 +659,13 @@ int google_chromeec_reboot(enum ec_reboot_cmd type, uint8_t flags)
 	return ec_cmd_reboot_ec(PLAT_EC, &params);
 }
 
+void google_chromeec_ap_poweroff(void)
+{
+	if (ec_cmd_ap_shutdown(PLAT_EC))
+		printk(BIOS_ERR, "Failed to power off the AP.\n");
+	halt();
+}
+
 static int cbi_get_uint32(uint32_t *id, uint32_t tag)
 {
 	struct ec_params_get_cbi params = {
diff --git a/src/ec/google/chromeec/ec.h b/src/ec/google/chromeec/ec.h
index 4b8d0958c3..febef6c1ab 100644
--- a/src/ec/google/chromeec/ec.h
+++ b/src/ec/google/chromeec/ec.h
@@ -94,6 +94,8 @@ int google_chromeec_vstore_write(int slot, uint8_t *data, size_t size);
    success, < 0 otherwise. */
 int google_chromeec_reboot(enum ec_reboot_cmd type, uint8_t flags);
 
+void google_chromeec_ap_poweroff(void);
+
 /**
  * Get data from Cros Board Info
  *

From cbd152912622879d7543954519b68766fad6cdfe Mon Sep 17 00:00:00 2001
From: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Date: Wed, 17 Sep 2025 16:10:42 +0800
Subject: [PATCH 2095/3886] mb/google/brox: Update Auxiliary Firmware Version
 check

Currently check_auxfw_ver_mismatch() expects the hash file to contain
only auxiliary firmware version and hence strictly checks for the size
of the auxiliary firmware version (3 bytes).

However, in some cases the hash file might contain other information
such as config_name.bin name which increases the hash file size.

Accommodate this scenario by checking the hash file size greater than
or equal to auxiliary firmware version size.

BUG=b:445606386
TEST=Build BIOS image with hash size of 3 and 11. Ensure that the
hints are provided correctly and 2 redundant resets are filtered out.

Change-Id: I287079cfc3cfbc75575ecde0603b98c57b42aa24
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89219
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
---
 src/mainboard/google/brox/variants/baseboard/brox/romstage.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/mainboard/google/brox/variants/baseboard/brox/romstage.c b/src/mainboard/google/brox/variants/baseboard/brox/romstage.c
index ce402af933..92fd56692d 100644
--- a/src/mainboard/google/brox/variants/baseboard/brox/romstage.c
+++ b/src/mainboard/google/brox/variants/baseboard/brox/romstage.c
@@ -36,7 +36,7 @@ static bool check_auxfw_ver_mismatch(void)
 
 	/* find bundled fw hash */
 	new_ver = cbfs_map(fwver_fname, &new_ver_size);
-	if (new_ver == NULL || new_ver_size != FWVER_SIZE)
+	if (new_ver == NULL || new_ver_size < FWVER_SIZE)
 		return mismatch;
 
 	/*

From 0a6f3e3868d49ba4315a8478b451cae2b363b259 Mon Sep 17 00:00:00 2001
From: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Date: Tue, 16 Sep 2025 15:37:55 +0800
Subject: [PATCH 2096/3886] mb/google/brox/var/caboc: Add PDC FW hash to hint
 romstage init

This CL follow Commit 2ba74b8c188b ("mb/google/brox: Hint romstage init
about upcoming reset") CB:84937 to add PDC FW hash in variant.c to hint
romstage init about upcoming reset.

BUG=b:445606386
TEST=Build Caboc BIOS image and boot to OS. Ensure that the hints are
provided correctly and 2 redundant resets are filtered out.

Change-Id: Ie029bf7faf991f520c42ffe22e610291ba98e078
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89190
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/google/brox/variants/caboc/variant.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/mainboard/google/brox/variants/caboc/variant.c b/src/mainboard/google/brox/variants/caboc/variant.c
index 666e370008..3142e8005d 100644
--- a/src/mainboard/google/brox/variants/caboc/variant.c
+++ b/src/mainboard/google/brox/variants/caboc/variant.c
@@ -21,5 +21,5 @@ const char *get_wifi_sar_cbfs_filename(void)
 
 const char *variant_get_auxfw_version_file(void)
 {
-	return NULL;
+	return "rts5453vb_GOOG0L01.hash";
 }

From 886bd1d1862ef1ba8fdd50a9d43da01a2ca74ecd Mon Sep 17 00:00:00 2001
From: Hualin Wei <weihualin@huaqin.corp-partner.google.com>
Date: Tue, 23 Sep 2025 10:12:58 +0800
Subject: [PATCH 2097/3886] spd/lp5: Add Samsung K3KLALA0EM-MGCU memory part

Add Samsung memory part K3KLALA0EM-MGCU in lp5 list.

BUG=438785495
TEST=util/spd_tools/bin/spd_gen spd/lp5/memory_parts.json lp5

Change-Id: I4cac57363fdedf9f216b8b01fb5ea091a511ebf2
Signed-off-by: Hualin Wei <weihualin@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89064
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
---
 spd/lp5/memory_parts.json                     | 11 +++++++
 .../set-0/parts_spd_manifest.generated.txt    |  1 +
 spd/lp5/set-0/spd-13.hex                      | 32 +++++++++++++++++++
 .../set-1/parts_spd_manifest.generated.txt    |  1 +
 spd/lp5/set-1/spd-13.hex                      | 32 +++++++++++++++++++
 5 files changed, 77 insertions(+)
 create mode 100644 spd/lp5/set-0/spd-13.hex
 create mode 100644 spd/lp5/set-1/spd-13.hex

diff --git a/spd/lp5/memory_parts.json b/spd/lp5/memory_parts.json
index 6c5e127bdf..31e6a6e723 100644
--- a/spd/lp5/memory_parts.json
+++ b/spd/lp5/memory_parts.json
@@ -370,6 +370,17 @@
             "speedMbps": 8533,
             "lp5x": true
         }
+    },
+    {
+        "name":  "K3KLALA0EM-MGCU",
+            "attribs": {
+                "densityPerDieGb": 16,
+                "diesPerPackage": 8,
+                "bitWidthPerChannel": 8,
+                "ranksPerChannel": 2,
+                "speedMbps": 8533,
+                "lp5x": true
+            }
     }
     ]
 }
diff --git a/spd/lp5/set-0/parts_spd_manifest.generated.txt b/spd/lp5/set-0/parts_spd_manifest.generated.txt
index 7e2ab8d761..9ea9aca301 100644
--- a/spd/lp5/set-0/parts_spd_manifest.generated.txt
+++ b/spd/lp5/set-0/parts_spd_manifest.generated.txt
@@ -36,3 +36,4 @@ MT62F512M32D1DS-023 WT:E,spd-11.hex
 MT62F1G32D2DS-031 WT:C,spd-3.hex
 MT62F2G32D4DS-031 WT:C,spd-6.hex
 H58GE6AK8BX104,spd-12.hex
+K3KLALA0EM-MGCU,spd-13.hex
diff --git a/spd/lp5/set-0/spd-13.hex b/spd/lp5/set-0/spd-13.hex
new file mode 100644
index 0000000000..65539494ff
--- /dev/null
+++ b/spd/lp5/set-0/spd-13.hex
@@ -0,0 +1,32 @@
+23 10 15 0E 16 2A F9 08 00 00 00 00 09 01 00 00
+00 00 08 00 00 00 00 00 AD 00 90 A8 90 C0 08 60
+04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 B6 00 C1 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 20 20 20 20 20 20 20
+20 20 20 20 20 20 20 20 20 20 20 20 20 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
diff --git a/spd/lp5/set-1/parts_spd_manifest.generated.txt b/spd/lp5/set-1/parts_spd_manifest.generated.txt
index 7e2ab8d761..9ea9aca301 100644
--- a/spd/lp5/set-1/parts_spd_manifest.generated.txt
+++ b/spd/lp5/set-1/parts_spd_manifest.generated.txt
@@ -36,3 +36,4 @@ MT62F512M32D1DS-023 WT:E,spd-11.hex
 MT62F1G32D2DS-031 WT:C,spd-3.hex
 MT62F2G32D4DS-031 WT:C,spd-6.hex
 H58GE6AK8BX104,spd-12.hex
+K3KLALA0EM-MGCU,spd-13.hex
diff --git a/spd/lp5/set-1/spd-13.hex b/spd/lp5/set-1/spd-13.hex
new file mode 100644
index 0000000000..5266fbaa96
--- /dev/null
+++ b/spd/lp5/set-1/spd-13.hex
@@ -0,0 +1,32 @@
+23 11 13 0E 86 29 F9 18 00 40 00 00 09 02 00 00
+00 00 02 00 00 00 00 00 2C 00 90 A8 90 C0 08 60
+04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 8A 00 F0 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 20 20 20 20 20 20 20
+20 20 20 20 20 20 20 20 20 20 20 20 20 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00

From 2764a508ad4f7abaf273e29b3abe29cb88290de7 Mon Sep 17 00:00:00 2001
From: Hualin Wei <weihualin@huaqin.corp-partner.google.com>
Date: Fri, 5 Sep 2025 14:11:16 +0800
Subject: [PATCH 2098/3886] mb/google/fatcat/var/lapis: Add 4 DDR modules to
 RAM id table

Add HYNIX H54G46CYRBX267 as id 1, and add Samsung K3KLALA0EM-MGCU
as id 2, resulting in the list below:

DRAM Part Name                 ID to assign
H58G66CK8BX147                 0 (0000)
K3KL9L90EM-MGCU                0 (0000)
MT62F2G32D4DS-023 WT:C         0 (0000)
H58G56CK8BX146                 1 (0001)
K3KL8L80EM-MGCU                1 (0001)
MT62F1G32D2DS-023 WT:C         1 (0001)
K3KLALA0EM-MGCU                2 (0010)

BUG=b:438785495
TEST=Use part_id_gen to generate related settings

Change-Id: I4179e31222d461b93f81c784511cc34071c10257
Signed-off-by: Hualin Wei <weihualin@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89065
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
---
 src/mainboard/google/fatcat/variants/lapis/memory/Makefile.mk | 2 ++
 .../google/fatcat/variants/lapis/memory/dram_id.generated.txt | 4 ++++
 .../google/fatcat/variants/lapis/memory/mem_parts_used.txt    | 4 ++++
 3 files changed, 10 insertions(+)

diff --git a/src/mainboard/google/fatcat/variants/lapis/memory/Makefile.mk b/src/mainboard/google/fatcat/variants/lapis/memory/Makefile.mk
index d1cc1e3fd4..3580f944f9 100644
--- a/src/mainboard/google/fatcat/variants/lapis/memory/Makefile.mk
+++ b/src/mainboard/google/fatcat/variants/lapis/memory/Makefile.mk
@@ -5,3 +5,5 @@
 
 SPD_SOURCES =
 SPD_SOURCES += spd/lp5/set-0/spd-10.hex      # ID = 0(0b0000)  Parts = H58G66CK8BX147, K3KL9L90EM-MGCU, MT62F2G32D4DS-023 WT:C
+SPD_SOURCES += spd/lp5/set-0/spd-11.hex      # ID = 1(0b0001)  Parts = H58G56CK8BX146, K3KL8L80EM-MGCU, MT62F1G32D2DS-023 WT:C
+SPD_SOURCES += spd/lp5/set-0/spd-13.hex      # ID = 2(0b0010)  Parts = K3KLALA0EM-MGCU
diff --git a/src/mainboard/google/fatcat/variants/lapis/memory/dram_id.generated.txt b/src/mainboard/google/fatcat/variants/lapis/memory/dram_id.generated.txt
index 1b44fd47f4..9d1f695535 100644
--- a/src/mainboard/google/fatcat/variants/lapis/memory/dram_id.generated.txt
+++ b/src/mainboard/google/fatcat/variants/lapis/memory/dram_id.generated.txt
@@ -7,3 +7,7 @@ DRAM Part Name                 ID to assign
 H58G66CK8BX147                 0 (0000)
 K3KL9L90EM-MGCU                0 (0000)
 MT62F2G32D4DS-023 WT:C         0 (0000)
+H58G56CK8BX146                 1 (0001)
+K3KL8L80EM-MGCU                1 (0001)
+MT62F1G32D2DS-023 WT:C         1 (0001)
+K3KLALA0EM-MGCU                2 (0010)
diff --git a/src/mainboard/google/fatcat/variants/lapis/memory/mem_parts_used.txt b/src/mainboard/google/fatcat/variants/lapis/memory/mem_parts_used.txt
index 2a5856956b..332be8dc20 100644
--- a/src/mainboard/google/fatcat/variants/lapis/memory/mem_parts_used.txt
+++ b/src/mainboard/google/fatcat/variants/lapis/memory/mem_parts_used.txt
@@ -12,3 +12,7 @@
 H58G66CK8BX147
 K3KL9L90EM-MGCU
 MT62F2G32D4DS-023 WT:C
+H58G56CK8BX146
+K3KL8L80EM-MGCU
+MT62F1G32D2DS-023 WT:C
+K3KLALA0EM-MGCU

From 4fc5f7a843afad33a758c9aa3d9f747d5f1a2322 Mon Sep 17 00:00:00 2001
From: Hualin Wei <weihualin@huaqin.corp-partner.google.com>
Date: Fri, 5 Sep 2025 15:06:40 +0800
Subject: [PATCH 2099/3886] mb/google/fatcat/var/lapis: Modify the gpio order
 of mem_id

According to the schematic diagram of lapis, refer to
the design of fatcat and modify the gpio order of mem_id.

BUG=b:438785495
TEST=emerge-fatcat coreboot
Change-Id: I715634e231725bbd009b35a0c520d19a894f569c
Signed-off-by: Hualin Wei <weihualin@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89066
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com>
---
 src/mainboard/google/fatcat/variants/lapis/memory.c | 8 +++-----
 1 file changed, 3 insertions(+), 5 deletions(-)

diff --git a/src/mainboard/google/fatcat/variants/lapis/memory.c b/src/mainboard/google/fatcat/variants/lapis/memory.c
index 4e2a1536ae..0c2a4e79fd 100644
--- a/src/mainboard/google/fatcat/variants/lapis/memory.c
+++ b/src/mainboard/google/fatcat/variants/lapis/memory.c
@@ -74,17 +74,15 @@ int variant_memory_sku(void)
 	/*
 	 * Memory configuration board straps
 	 * MEM_STRAP_0	GPP_A13
+	 * DIMM_SEL1	GPP_D24		(MEM_STRAP_1)
+	 * DIMM_SEL2	GPP_B25		(MEM_STRAP_2)
 	 * MEM_STRAP_3	GPP_B24
-	 * DIMM_SEL0	GPP_D25
-	 * DIMM_SEL1	GPP_D24
-	 * DIMM_SEL2	GPP_B25
 	 */
 	gpio_t spd_gpios[] = {
 		GPP_A13,
-		GPP_B24,
-		GPP_D25,
 		GPP_D24,
 		GPP_B25,
+		GPP_B24,
 	};
 
 	return gpio_base2_value(spd_gpios, ARRAY_SIZE(spd_gpios));

From 6af7d299b2df99f2d7e3365f874a5f3e4b88cd50 Mon Sep 17 00:00:00 2001
From: Yang Wu <wuyang5@huaqin.corp-partner.google.com>
Date: Tue, 16 Sep 2025 20:51:37 +0800
Subject: [PATCH 2100/3886] mb/google/skywalker: Add MIPI panel support with
 TM_TL121BVMS07_00C
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Add support for MIPI panel on padme and enable TM_TL121BVMS07_00C as
the default panel. The panel uses AW37503 as the bias IC, with supply
set to ±5.9V. Add AW37503 initialization and power-on sequence are
configured according to the specification.

The developer/recovery screen is not functional yet as the vendor is
still debugging it. This change is proposed to enable firmware build.

BUG=b:432353024
TEST=emerge-skywalker coreboot

Change-Id: I37a1c0352a8619ce5b10727cdeef524ccb1107ef
Signed-off-by: Yang Wu <wuyang5@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89218
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
---
 src/mainboard/google/skywalker/Kconfig       |  1 +
 src/mainboard/google/skywalker/Makefile.mk   |  2 +
 src/mainboard/google/skywalker/mainboard.c   |  3 +
 src/mainboard/google/skywalker/panel.c       | 60 +++++++++++++++++++-
 src/mainboard/google/skywalker/panel.h       | 18 ++++++
 src/mainboard/google/skywalker/panel_padme.c | 25 ++++++++
 6 files changed, 107 insertions(+), 2 deletions(-)
 create mode 100644 src/mainboard/google/skywalker/panel_padme.c

diff --git a/src/mainboard/google/skywalker/Kconfig b/src/mainboard/google/skywalker/Kconfig
index 81b49ba513..dd97f682b4 100644
--- a/src/mainboard/google/skywalker/Kconfig
+++ b/src/mainboard/google/skywalker/Kconfig
@@ -41,6 +41,7 @@ config BOARD_SPECIFIC_OPTIONS
 	select RTC
 	select COMMONLIB_STORAGE
 	select COMMONLIB_STORAGE_MMC
+	select MIPI_PANEL_TM_TL121BVMS07_00C if BOARD_GOOGLE_PADME
 
 config MAINBOARD_DIR
 	string
diff --git a/src/mainboard/google/skywalker/Makefile.mk b/src/mainboard/google/skywalker/Makefile.mk
index ff3c1701de..4a21a59187 100644
--- a/src/mainboard/google/skywalker/Makefile.mk
+++ b/src/mainboard/google/skywalker/Makefile.mk
@@ -13,3 +13,5 @@ ramstage-y += boardid.c
 ramstage-y += mainboard.c
 ramstage-y += panel.c
 ramstage-y += regulator.c
+
+ramstage-$(CONFIG_BOARD_GOOGLE_PADME) += panel_padme.c
diff --git a/src/mainboard/google/skywalker/mainboard.c b/src/mainboard/google/skywalker/mainboard.c
index 99c45cf17a..9952bfc1ec 100644
--- a/src/mainboard/google/skywalker/mainboard.c
+++ b/src/mainboard/google/skywalker/mainboard.c
@@ -17,6 +17,7 @@
 #include <soc/usb.h>
 
 #include "gpio.h"
+#include "panel.h"
 #include "storage.h"
 
 #define AFE_SE_SECURE_CON1	(AUDIO_BASE + 0x5634)
@@ -88,6 +89,8 @@ enum mtk_storage_type mainboard_get_storage_type(void)
 
 static void mainboard_init(struct device *dev)
 {
+	mt6359p_init_pmif_arb();
+
 	if (mainboard_get_storage_type() == STORAGE_EMMC) {
 		mtk_msdc_configure_emmc(true);
 		mtcmos_ufs_power_off();
diff --git a/src/mainboard/google/skywalker/panel.c b/src/mainboard/google/skywalker/panel.c
index 35313c23f6..deb392f281 100644
--- a/src/mainboard/google/skywalker/panel.c
+++ b/src/mainboard/google/skywalker/panel.c
@@ -1,12 +1,34 @@
 /* SPDX-License-Identifier: GPL-2.0-only OR MIT */
 
+#include <console/console.h>
+#include <delay.h>
+#include <device/i2c_simple.h>
+
 #include <gpio.h>
 #include <soc/display.h>
+#include <soc/regulator.h>
 
 #include "gpio.h"
+#include "panel.h"
+
+static void aw37503_init(unsigned int bus)
+{
+	i2c_write_field(bus, PMIC_AW37503_SLAVE, 0x00, 0x13, 0x1F, 0);
+	i2c_write_field(bus, PMIC_AW37503_SLAVE, 0x01, 0x13, 0x1F, 0);
+	i2c_write_field(bus, PMIC_AW37503_SLAVE, 0x21, 0x4C, 0xFF, 0);
+	i2c_write_field(bus, PMIC_AW37503_SLAVE, 0x03, 0x43, 0xFF, 0);
+	i2c_write_field(bus, PMIC_AW37503_SLAVE, 0x21, 0x00, 0xFF, 0);
+}
+
+static bool is_pmic_aw37503(unsigned int bus)
+{
+	u8 vendor_id;
+	return (!i2c_read_field(bus, PMIC_AW37503_SLAVE,
+				0x04, &vendor_id, 0x0F, 0) && vendor_id == 0x01);
+}
 
 /* Set up backlight control pins as output pins, and set them to power off by default */
-static void configure_backlight(void)
+void panel_configure_backlight(void)
 {
 	gpio_output(GPIO_EDP_BL_EN_1V8, 0);
 	gpio_output(GPIO_BL_PWM_1V8, 0);
@@ -19,8 +41,39 @@ static void power_on_panel(void)
 	gpio_set_pull(GPIO_EDP_HPD_1V8, GPIO_PULL_DISABLE, GPIO_PULL_UP);
 }
 
+void mipi_panel_power_on(void)
+{
+	struct aw37503_config config = {
+		.i2c_bus = PMIC_I2C_BUS,
+		.en = GPIO_TCHSCR_REPORT_DISABLE,
+	};
+	gpio_output(config.en, 0);
+	mdelay(1);
+
+	mainboard_set_regulator_voltage(MTK_REGULATOR_VCN18, 1800000);
+	mtk_i2c_bus_init(config.i2c_bus, I2C_SPEED_FAST);
+
+	mainboard_enable_regulator(MTK_REGULATOR_VCN18, true);
+	mdelay(5);
+
+	if (is_pmic_aw37503(config.i2c_bus)) {
+		printk(BIOS_DEBUG, "Initialize and power on PMIC AW37503\n");
+		aw37503_init(config.i2c_bus);
+		gpio_output(config.en, 1);
+		mdelay(10);
+	}
+	gpio_output(GPIO_EN_PP3300_EDP_X, 0);
+	mdelay(1);
+	gpio_output(GPIO_EN_PP3300_EDP_X, 1);
+	mdelay(1);
+	gpio_output(GPIO_TCHSCR_RST_1V8_L, 0);
+	mdelay(1);
+	gpio_output(GPIO_TCHSCR_RST_1V8_L, 1);
+	mdelay(6);
+}
+
 static struct panel_description panel = {
-	.configure_backlight = configure_backlight,
+	.configure_backlight = panel_configure_backlight,
 	.power_on = power_on_panel,
 	.disp_path = DISP_PATH_EDP,
 	.orientation = LB_FB_ORIENTATION_NORMAL,
@@ -28,5 +81,8 @@ static struct panel_description panel = {
 
 struct panel_description *get_active_panel(void)
 {
+	if (CONFIG(BOARD_GOOGLE_PADME))
+		return get_panel_description();
+
 	return &panel;
 }
diff --git a/src/mainboard/google/skywalker/panel.h b/src/mainboard/google/skywalker/panel.h
index 6a969b323e..77c8aed5e5 100644
--- a/src/mainboard/google/skywalker/panel.h
+++ b/src/mainboard/google/skywalker/panel.h
@@ -3,6 +3,24 @@
 #ifndef __MAINBOARD_GOOGLE_SKYWALKER_PANEL_H__
 #define __MAINBOARD_GOOGLE_SKYWALKER_PANEL_H__
 
+#include <gpio.h>
+#include <soc/display.h>
+#include <soc/i2c.h>
+
+#define PMIC_AW37503_SLAVE	0x3E
+#define PMIC_I2C_BUS		I2C6
+
+struct aw37503_config {
+	uint32_t i2c_bus;
+	gpio_t en;
+};
+
 uint8_t panel_id(void);
 
+void panel_configure_backlight(void);
+void mipi_panel_power_on(void);
+
+/* Return the mipi panel description */
+struct panel_description *get_panel_description(void);
+
 #endif
diff --git a/src/mainboard/google/skywalker/panel_padme.c b/src/mainboard/google/skywalker/panel_padme.c
new file mode 100644
index 0000000000..13fdaa62cf
--- /dev/null
+++ b/src/mainboard/google/skywalker/panel_padme.c
@@ -0,0 +1,25 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <console/console.h>
+
+#include "gpio.h"
+#include "panel.h"
+
+static struct panel_description padme_panels[] = {
+	[0x22] = {
+		.configure_backlight = panel_configure_backlight,
+		.power_on = mipi_panel_power_on,
+		.name = "TM_TL121BVMS07_00C",
+		.disp_path = DISP_PATH_MIPI,
+		.orientation = LB_FB_ORIENTATION_LEFT_UP,
+	},
+};
+
+struct panel_description *get_panel_description(void)
+{
+	uint8_t id = panel_id();
+	if (id >= ARRAY_SIZE(padme_panels))
+		return NULL;
+
+	return &padme_panels[id];
+}

From 865649edc0522c1382e6ff6e274e093f8146cfc1 Mon Sep 17 00:00:00 2001
From: Felix Singer <felixsinger@posteo.net>
Date: Wed, 24 Sep 2025 13:24:34 +0200
Subject: [PATCH 2101/3886] util/docker/jenkins-node: Use the correct branch
 for encapsulate

Change-Id: Ia137fd991c242ef52e354b2ef04d7cf50dcfdf23
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89326
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
---
 util/docker/coreboot-jenkins-node/Dockerfile | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/util/docker/coreboot-jenkins-node/Dockerfile b/util/docker/coreboot-jenkins-node/Dockerfile
index 51a4b27d63..06a2defe19 100644
--- a/util/docker/coreboot-jenkins-node/Dockerfile
+++ b/util/docker/coreboot-jenkins-node/Dockerfile
@@ -54,7 +54,7 @@ RUN mkdir /cb-build && \
 	echo "tmpfs /home/coreboot/.ccache tmpfs rw,mode=1777 0 0" >> /etc/fstab
 
 # Build encapsulate tool
-ADD https://raw.githubusercontent.com/coreboot/encapsulate/master/encapsulate.c /tmp/encapsulate.c
+ADD https://raw.githubusercontent.com/coreboot/encapsulate/main/encapsulate.c /tmp/encapsulate.c
 RUN gcc -o /usr/sbin/encapsulate /tmp/encapsulate.c && \
 	chown root /usr/sbin/encapsulate && \
 	chmod +s /usr/sbin/encapsulate

From 67e3579d611b59fe463054a93931895d67177242 Mon Sep 17 00:00:00 2001
From: Angel Pons <th3fanbus@gmail.com>
Date: Wed, 8 Sep 2021 15:39:35 +0200
Subject: [PATCH 2102/3886] sb/intel/lynxpoint: Enable PCIe Relaxed Order

Follow Lynx Point PCH reference code version 1.9.1 to enable PCIe
Relaxed Order.

Change-Id: If7ba4e826adfc8c220ecc68c4a456fbe3cb99667
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57504
Reviewed-by: Lean Sheng Tan <tanleansheng@outlook.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Benjamin Doron <benjamin.doron00@gmail.com>
---
 src/southbridge/intel/lynxpoint/lpc.c  | 9 +++++++++
 src/southbridge/intel/lynxpoint/pcie.c | 5 +++++
 2 files changed, 14 insertions(+)

diff --git a/src/southbridge/intel/lynxpoint/lpc.c b/src/southbridge/intel/lynxpoint/lpc.c
index 93b74233f7..bd6ac0729e 100644
--- a/src/southbridge/intel/lynxpoint/lpc.c
+++ b/src/southbridge/intel/lynxpoint/lpc.c
@@ -272,6 +272,15 @@ static void pch_power_options(struct device *dev)
 	reg16 = RCBA16(0x3f02);
 	reg16 &= ~0xf;
 	RCBA16(0x3f02) = reg16;
+
+	/* Enable PCIe Relaxed Order */
+	reg32 = RCBA32(0x2314);
+	reg32 |= 1 << 31 | 1 << 7;
+	RCBA32(0x2314) = reg32;
+
+	reg16 = RCBA16(0x1114);
+	reg16 |= 1 << 15 | 1 << 14;
+	RCBA16(0x1114) = reg16;
 }
 
 static void configure_dmi_pm(struct device *dev)
diff --git a/src/southbridge/intel/lynxpoint/pcie.c b/src/southbridge/intel/lynxpoint/pcie.c
index 645ae7e5bb..7aff60895c 100644
--- a/src/southbridge/intel/lynxpoint/pcie.c
+++ b/src/southbridge/intel/lynxpoint/pcie.c
@@ -685,8 +685,13 @@ static void pch_pcie_early(struct device *dev)
 			pci_update_config32(dev, 0x200, ~0xfffff, 0x001e);
 		else
 			pci_update_config32(dev, 0x200, ~0xfffff, 0);
+
+		pci_update_config32(dev, 0x320, ~(3 << 20 | 7 << 6), 1 << 20 | 3 << 6);
 	}
 
+	/* Enable PCIe Relaxed Order. */
+	pci_or_config32(dev, 0x320, 3 << 23);
+
 	/* Read and write back write-once capability registers. */
 	pci_update_config32(dev, 0x34, ~0, 0);
 	pci_update_config32(dev, 0x40, ~0, 0);

From 038262155e3105cb66027978aaab4c480321a0cb Mon Sep 17 00:00:00 2001
From: Patrick Rudolph <patrick.rudolph@amd.com>
Date: Tue, 15 Jul 2025 09:54:39 +0200
Subject: [PATCH 2103/3886] soc/amd/common/block/psp/psp_smi_flash: Fix flash
 busy check

Currently the PSP SMI handler works only if you are lucky. Since
ring 0 can start SPI flash transactions any time and the PSP SMI might
happen shortly after that, the SPI controller or SPI flash might be
busy. When the SPI flash is busy it cannot process certain commands,
for example reading the contents, causing the SPI flash memory map
to return all 0xffs.

By introducing the AMD fTPM code the PSP SMI happens more often at
boot and uncovered this issue. This issue was found when deleting
the MRC cache, which takes quite long, while the PSP SMI tried to
access the SPI flash. Adding small delays, as introduced by
CONSOLE_SERIAL, resolved the issue.

Add code to check if the SPI controller and the SPI flash are busy.
If so tell the PSP SMI to retry at a later point in time.

TEST: AMD glinda boots with CONSOLE_SERIAL disabled.
      Logging to CBMEM shows that the PSP SMI is fired 10 times
      before the SPI flash no longer reports that it's busy.

Signed-off-by: Patrick Rudolph <patrick.rudolph@amd.com>
Change-Id: I9122165e7c60b7c288d5b61b80d4cb582901841c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88437
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Benjamin Doron <benjamin.doron00@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 .../amd/common/block/include/amdblocks/spi.h  |  8 +++++
 src/soc/amd/common/block/psp/psp_smi_flash.c  | 36 ++++++++++++++++---
 src/soc/amd/common/block/spi/fch_spi_ctrl.c   |  7 ----
 3 files changed, 40 insertions(+), 11 deletions(-)

diff --git a/src/soc/amd/common/block/include/amdblocks/spi.h b/src/soc/amd/common/block/include/amdblocks/spi.h
index 83d09e90d7..70de548bf7 100644
--- a/src/soc/amd/common/block/include/amdblocks/spi.h
+++ b/src/soc/amd/common/block/include/amdblocks/spi.h
@@ -70,6 +70,14 @@ enum spi100_speed {
 #define SPI100_HOST_PREF_CONFIG		0x2c
 #define   SPI_RD4DW_EN_HOST		BIT(15)
 
+#define SPI_STATUS			0x4c
+#define   SPI_DONE_BYTE_COUNT_SHIFT	0
+#define   SPI_DONE_BYTE_COUNT_MASK	0xff
+#define   SPI_FIFO_WR_PTR_SHIFT		8
+#define   SPI_FIFO_WR_PTR_MASK		0x7f
+#define   SPI_FIFO_RD_PTR_SHIFT		16
+#define   SPI_FIFO_RD_PTR_MASK		0x7f
+
 #define SPI_ROM_PAGE			0x5c
 #define   SPI_ROM_PAGE_SEL		(BIT(0) | BIT(1))
 
diff --git a/src/soc/amd/common/block/psp/psp_smi_flash.c b/src/soc/amd/common/block/psp/psp_smi_flash.c
index 9f9f31d94c..7e0328330c 100644
--- a/src/soc/amd/common/block/psp/psp_smi_flash.c
+++ b/src/soc/amd/common/block/psp/psp_smi_flash.c
@@ -96,14 +96,42 @@ static bool spi_controller_busy(void)
 {
 	bool busy = false;
 
-	if (CONFIG(SOC_AMD_PICASSO)) {
+	/*
+	 * When ring0 is operating on the SPI flash and the controller is
+	 * busy, don't interrupt ongoing transfer.
+	 */
+	if (spi_read32(SPI_STATUS) & SPI_BUSY)
+		busy = true;
+
+	/*
+	 * Even when the SPI controller is not busy, the SPI flash
+	 * might be busy. When that's the case reading from the
+	 * memory mapped SPI flash doesn't work and returns all 0xffs.
+	 * Thus check if the SPI flash is busy.
+	 */
+	if (CONFIG(SPI_FLASH) && !busy) {
+		const struct spi_flash *spi_flash_dev;
+		uint8_t sr1 = 0;
+
+		spi_flash_dev = boot_device_spi_flash();
+		assert(spi_flash_dev);
+		if (spi_flash_dev) {
+			/* Read Status Register 1 */
+			if (spi_flash_status(spi_flash_dev, &sr1) < 0)
+				busy = true;
+			else if (sr1 & BIT(0))
+				busy = true;
+		}
+	}
+
+	if (CONFIG(SOC_AMD_PICASSO) && !busy) {
 		// Only implemented on Picasso and Raven Ridge
 		busy = (spi_read8(SPI_MISC_CNTRL) & SPI_SEMAPHORE_DRIVER_LOCKED);
-
-		if (busy)
-			printk(BIOS_NOTICE, "PSP: SPI controller busy\n");
 	}
 
+	if (busy)
+		printk(BIOS_NOTICE, "PSP: SPI controller or SPI flash busy\n");
+
 	return busy;
 }
 
diff --git a/src/soc/amd/common/block/spi/fch_spi_ctrl.c b/src/soc/amd/common/block/spi/fch_spi_ctrl.c
index aa07542a54..95b68ff050 100644
--- a/src/soc/amd/common/block/spi/fch_spi_ctrl.c
+++ b/src/soc/amd/common/block/spi/fch_spi_ctrl.c
@@ -22,13 +22,6 @@
 #define   SPI_CMD_TRIGGER_EXECUTE	BIT(7)
 #define SPI_TX_BYTE_COUNT		0x48
 #define SPI_RX_BYTE_COUNT		0x4b
-#define SPI_STATUS			0x4c
-#define   SPI_DONE_BYTE_COUNT_SHIFT	0
-#define   SPI_DONE_BYTE_COUNT_MASK	0xff
-#define   SPI_FIFO_WR_PTR_SHIFT		8
-#define   SPI_FIFO_WR_PTR_MASK		0x7f
-#define   SPI_FIFO_RD_PTR_SHIFT		16
-#define   SPI_FIFO_RD_PTR_MASK		0x7f
 
 enum spi_dump_state_phase {
 	SPI_DUMP_STATE_BEFORE_CMD,

From a17a41559a60ba34089d10ffeabf7e8b9a2a05cd Mon Sep 17 00:00:00 2001
From: Patrick Rudolph <patrick.rudolph@amd.com>
Date: Tue, 15 Jul 2025 12:11:28 +0200
Subject: [PATCH 2104/3886] soc/amd/common/block/psp: Add BIOS SPI flash
 semaphore

When coreboot is operating on the SPI flash lock the bus by
setting SPI_SEMAPHORE_BIOS_LOCKED in SPI_MISC_CNTRL. This prevents
SMM from accidentally corrupting SPI CTRL registers, even though
SMM backups and restores SPI CTRL registers.

TEST: Booted an AMD glinda and observed SMM not accessing the SPI
      controller as long as ring 0 is operating on it.

Signed-off-by: Patrick Rudolph <patrick.rudolph@amd.com>
Change-Id: Iaeda356b55d3f203c75f4056da7bde2abacebc41
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88438
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
---
 .../amd/common/block/include/amdblocks/spi.h  |  1 +
 src/soc/amd/common/block/psp/psp_smi_flash.c  |  9 +++-
 src/soc/amd/common/block/spi/fch_spi_ctrl.c   | 41 +++++++++++++++++++
 3 files changed, 50 insertions(+), 1 deletion(-)

diff --git a/src/soc/amd/common/block/include/amdblocks/spi.h b/src/soc/amd/common/block/include/amdblocks/spi.h
index 70de548bf7..bc395d75c7 100644
--- a/src/soc/amd/common/block/include/amdblocks/spi.h
+++ b/src/soc/amd/common/block/include/amdblocks/spi.h
@@ -89,6 +89,7 @@ enum spi100_speed {
 /* AMD has re-purposed this unused SPI controller register bit as a semaphore to synchronize
    access to the SPI controller between SMM and non-SMM software/OS driver. */
 #define   SPI_SEMAPHORE_DRIVER_LOCKED	BIT(4)
+#define   SPI_SEMAPHORE_BIOS_LOCKED	BIT(3)
 
 struct spi_config {
 	/*
diff --git a/src/soc/amd/common/block/psp/psp_smi_flash.c b/src/soc/amd/common/block/psp/psp_smi_flash.c
index 7e0328330c..0a1c0462e8 100644
--- a/src/soc/amd/common/block/psp/psp_smi_flash.c
+++ b/src/soc/amd/common/block/psp/psp_smi_flash.c
@@ -94,7 +94,14 @@ static enum mbox_p2c_status find_psp_spi_flash_device_region(uint64_t target_nv_
 
 static bool spi_controller_busy(void)
 {
-	bool busy = false;
+	bool busy;
+
+	/* When the firmware is using the SPI controller stop here */
+	busy = (spi_read8(SPI_MISC_CNTRL) & SPI_SEMAPHORE_BIOS_LOCKED);
+	if (busy) {
+		printk(BIOS_NOTICE, "PSP: SPI controller blocked by coreboot (ring 0)\n");
+		return true;
+	}
 
 	/*
 	 * When ring0 is operating on the SPI flash and the controller is
diff --git a/src/soc/amd/common/block/spi/fch_spi_ctrl.c b/src/soc/amd/common/block/spi/fch_spi_ctrl.c
index 95b68ff050..c4ec4cc9b8 100644
--- a/src/soc/amd/common/block/spi/fch_spi_ctrl.c
+++ b/src/soc/amd/common/block/spi/fch_spi_ctrl.c
@@ -4,6 +4,7 @@
 #include <spi_flash.h>
 #include <soc/pci_devs.h>
 #include <amdblocks/lpc.h>
+#include <amdblocks/smi.h>
 #include <amdblocks/spi.h>
 #include <device/pci_ops.h>
 #include <lib.h>
@@ -122,6 +123,10 @@ static uint8_t fifo[SPI_FIFO_DEPTH];
 
 void fch_spi_backup_registers(void)
 {
+	/* When bus is locked no need for backup */
+	if (ENV_SMM && (spi_read8(SPI_MISC_CNTRL) & SPI_SEMAPHORE_BIOS_LOCKED))
+		return;
+
 	cmd_code = spi_read8(SPI_CMD_CODE);
 	tx_byte_count = spi_read8(SPI_TX_BYTE_COUNT);
 	rx_byte_count = spi_read8(SPI_RX_BYTE_COUNT);
@@ -132,6 +137,10 @@ void fch_spi_backup_registers(void)
 
 void fch_spi_restore_registers(void)
 {
+	/* When bus is locked no need for backup */
+	if (ENV_SMM && (spi_read8(SPI_MISC_CNTRL) & SPI_SEMAPHORE_BIOS_LOCKED))
+		return;
+
 	spi_write8(SPI_CMD_CODE, cmd_code);
 	spi_write8(SPI_TX_BYTE_COUNT, tx_byte_count);
 	spi_write8(SPI_RX_BYTE_COUNT, rx_byte_count);
@@ -308,7 +317,39 @@ static int fch_spi_flash_protect(const struct spi_flash *flash, const struct reg
 	return 0;
 }
 
+/* Block PSP SMI while operating on the SPI flash */
+static int spi_ctrlr_claim_bus(const struct spi_slave *slave)
+{
+	uint8_t reg8;
+
+	if (CONFIG(SOC_AMD_COMMON_BLOCK_PSP_SMI)) {
+		if (ENV_RAMSTAGE || ENV_SMM) {
+			reg8 = spi_read8(SPI_MISC_CNTRL);
+
+			if (reg8 & SPI_SEMAPHORE_BIOS_LOCKED)
+				return -1;
+		}
+		if (ENV_RAMSTAGE)
+			spi_write8(SPI_MISC_CNTRL, reg8 | SPI_SEMAPHORE_BIOS_LOCKED);
+	}
+
+	return 0;
+}
+
+/* Allow PSP SMI when not operating on the SPI flash */
+static void spi_ctrlr_release_bus(const struct spi_slave *slave)
+{
+	uint8_t reg8;
+
+	if (ENV_RAMSTAGE && CONFIG(SOC_AMD_COMMON_BLOCK_PSP_SMI)) {
+		reg8 = spi_read8(SPI_MISC_CNTRL);
+		spi_write8(SPI_MISC_CNTRL, reg8 & ~SPI_SEMAPHORE_BIOS_LOCKED);
+	}
+}
+
 static const struct spi_ctrlr fch_spi_flash_ctrlr = {
+	.claim_bus = spi_ctrlr_claim_bus,
+	.release_bus = spi_ctrlr_release_bus,
 	.xfer_vector = xfer_vectors,
 	.max_xfer_size = SPI_FIFO_DEPTH,
 	.flags = SPI_CNTRLR_DEDUCT_CMD_LEN | SPI_CNTRLR_DEDUCT_OPCODE_LEN,

From 02980f0ea68c9386e524612d9a8e31f8f5ae7f4c Mon Sep 17 00:00:00 2001
From: Patrick Rudolph <patrick.rudolph@9elements.com>
Date: Mon, 21 Jul 2025 11:01:15 +0200
Subject: [PATCH 2105/3886] soc/amd/common/block/psp: Add comments

Explain when the MBOX_PSP return codes are send and which behaviour
is invoked by the PSP when seeing such return codes.

Change-Id: Ibe7ceb5d7cd025f3b3ab0c9167d23f6eb664c165
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88511
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/soc/amd/common/block/psp/psp_def.h       | 20 ++++++++++++++++----
 src/soc/amd/common/block/psp/psp_smi_flash.c |  8 ++++++++
 2 files changed, 24 insertions(+), 4 deletions(-)

diff --git a/src/soc/amd/common/block/psp/psp_def.h b/src/soc/amd/common/block/psp/psp_def.h
index 56c963dd7c..6120c92174 100644
--- a/src/soc/amd/common/block/psp/psp_def.h
+++ b/src/soc/amd/common/block/psp/psp_def.h
@@ -143,10 +143,22 @@ enum mbox_p2c_status {
 	MBOX_PSP_SUCCESS		= 0x00,
 	MBOX_PSP_INVALID_PARAMETER	= 0x01,
 	MBOX_PSP_CRC_ERROR		= 0x02,
-	MBOX_PSP_COMMAND_PROCESS_ERROR	= 0x04,
-	MBOX_PSP_UNSUPPORTED		= 0x08,
-	MBOX_PSP_SPI_BUSY_ASYNC		= 0x0a,
-	MBOX_PSP_SPI_BUSY		= 0x0b,
+	/*
+	 * Send to PSP when the requested SPI command in the psp_smi_handler()
+	 * handler failed due to an unknown error. The PSP usually doesn't like
+	 * seeing this return code and will stop operating.
+	 */
+	 MBOX_PSP_COMMAND_PROCESS_ERROR	= 0x04,
+	 MBOX_PSP_UNSUPPORTED		= 0x08,
+	 MBOX_PSP_SPI_BUSY_ASYNC	= 0x0a,
+	 /*
+	  * Send to PSP when the requested SPI command in the psp_smi_handler()
+	  * handler cannot be executed right away. This can happen when the SPI
+	  * flash is busy or the SPI controller is busy or being used by ring 0.
+	  *
+	  * The PSP will raise an SMI later again.
+	  */
+	 MBOX_PSP_SPI_BUSY		= 0x0b,
 };
 
 uintptr_t get_psp_mmio_base(void);
diff --git a/src/soc/amd/common/block/psp/psp_smi_flash.c b/src/soc/amd/common/block/psp/psp_smi_flash.c
index 0a1c0462e8..a2b718b160 100644
--- a/src/soc/amd/common/block/psp/psp_smi_flash.c
+++ b/src/soc/amd/common/block/psp/psp_smi_flash.c
@@ -92,6 +92,14 @@ static enum mbox_p2c_status find_psp_spi_flash_device_region(uint64_t target_nv_
 	return MBOX_PSP_SUCCESS;
 }
 
+/*
+ * Returns true when the SPI flash is busy, the SPI controller is busy or the SPI
+ * MMIO register access is blocked by ring0. When the SPI flash is busy all
+ * operations, including reading, would fail.
+ * Thus even memory mapped structures like FMAP would not be accessible
+ * from memory mapped SPI flash (ROM2/ROM3). Caller must return MBOX_PSP_SPI_BUSY
+ * to PSP when this function returns true.
+ */
 static bool spi_controller_busy(void)
 {
 	bool busy;

From 1f08b36f84ae1042ff0ef15f4feb32c42a746c65 Mon Sep 17 00:00:00 2001
From: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com>
Date: Thu, 25 Sep 2025 18:11:49 -0700
Subject: [PATCH 2106/3886] Documentation: Add coreboot release 25.12 template

This adds the release notes template for the upcoming December release
of coreboot.

Change-Id: Iffaa625137f4edf994d73984d847b1cf926f8078
Signed-off-by: Jason Glenesk <jason.glenesk@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89352
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 .../releases/coreboot-25.12-relnotes.md       | 96 +++++++++++++++++++
 Documentation/releases/index.md               |  3 +-
 2 files changed, 98 insertions(+), 1 deletion(-)
 create mode 100644 Documentation/releases/coreboot-25.12-relnotes.md

diff --git a/Documentation/releases/coreboot-25.12-relnotes.md b/Documentation/releases/coreboot-25.12-relnotes.md
new file mode 100644
index 0000000000..9fcc671278
--- /dev/null
+++ b/Documentation/releases/coreboot-25.12-relnotes.md
@@ -0,0 +1,96 @@
+Upcoming release - coreboot 25.12
+========================================================================
+
+The 25.12 release is scheduled for the end of December, 2025
+
+
+Update this document with changes that should be in the release notes.
+
+* Please use Markdown.
+* See the past few release notes for the general format.
+* The chip and board additions and removals will be updated right
+  before the release, so those do not need to be added.
+* Note that all changes before the release are done are marked upcoming.
+  A final version of the notes are done after the release.
+
+
+
+Significant or interesting changes
+----------------------------------
+
+* Add changes that need a full description here
+
+* This section should have full descriptions and can or should have
+  a link to the referenced commits.
+
+
+
+Additional coreboot changes
+---------------------------
+
+The following are changes across a number of patches, or changes worth
+noting, but not needing a full description.
+
+* Changes that only need a line or two of description go here.
+
+
+
+Changes to external resources
+-----------------------------
+
+### Toolchain updates
+
+
+
+### Git submodule pointers
+
+
+### External payloads
+
+
+
+Platform Updates
+----------------
+
+### Added mainboards:
+* To be filled in immediately before the release by the release team
+
+
+### Removed Mainboards
+* To be filled in immediately before the release by the release team
+
+
+### Updated SoCs
+* To be filled in immediately before the release by the release team
+
+
+
+Plans to move platform support to a branch
+------------------------------------------
+* To be filled in immediately before the release by the release team
+
+
+
+Statistics from the 25.09 to the 25.12 release
+--------------------------------------------
+* To be filled in immediately before the release by the release team
+
+
+
+Significant Known and Open Issues
+---------------------------------
+
+Issues from the coreboot bugtracker: <https://ticket.coreboot.org/>
+* To be filled in immediately before the release by the release team
+
+
+
+coreboot Links and Contact Information
+--------------------------------------
+
+* Main Web site: <https://www.coreboot.org>
+* Downloads: <https://coreboot.org/downloads.html>
+* Source control: <https://review.coreboot.org>
+* Documentation: <https://doc.coreboot.org>
+* Issue tracker: <https://ticket.coreboot.org/projects/coreboot>
+* Donations: <https://coreboot.org/donate.html>
diff --git a/Documentation/releases/index.md b/Documentation/releases/index.md
index b587ebcc36..8cf8678b2d 100644
--- a/Documentation/releases/index.md
+++ b/Documentation/releases/index.md
@@ -6,7 +6,7 @@ Please add to the release notes as changes are added:
 ```{toctree}
 :maxdepth: 1
 
-25.09  - September 2025 <coreboot-25.09-relnotes.md>
+25.12  - December 2025 <coreboot-25.12-relnotes.md>
 ```
 
 The [checklist] contains instructions to ensure that a release covers all
@@ -22,6 +22,7 @@ important is taken care of.
 ```{toctree}
 :maxdepth: 1
 
+25.09  - September 2025 <coreboot-25.09-relnotes.md>
 25.06  - June 2025 <coreboot-25.06-relnotes.md>
 25.03  - March 2025 <coreboot-25.03-relnotes.md>
 24.12  - December 2024 <coreboot-24.12-relnotes.md>

From 8f52c0774eaf2b2afb304cec6d8f99ab1f6548dc Mon Sep 17 00:00:00 2001
From: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com>
Date: Thu, 25 Sep 2025 19:26:29 -0700
Subject: [PATCH 2107/3886] docs/security/vboot: Update supported board list

Generated by util/vboot_list/vboot_list.sh.

Change-Id: I313b9a59b9a009257fa4a0969c91b334feb55b8b
Signed-off-by: Jason Glenesk <jason.glenesk@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89354
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
---
 Documentation/security/vboot/list_vboot.md | 25 ++++++++++++++++++++++
 1 file changed, 25 insertions(+)

diff --git a/Documentation/security/vboot/list_vboot.md b/Documentation/security/vboot/list_vboot.md
index c42352ddf5..667bbee5b0 100644
--- a/Documentation/security/vboot/list_vboot.md
+++ b/Documentation/security/vboot/list_vboot.md
@@ -39,10 +39,14 @@
 - Zako (HP Chromebox G1)
 - Bluey
 - Quenbi
+- BlueyH
+- QuenbiH
+- Quartz
 - Brox
 - Brox RTK EC
 - Brox EC ISH
 - Brox TI PDC
+- Caboc
 - Greenbayupoc
 - Jubilant
 - Lotso
@@ -71,6 +75,7 @@
 - Guren
 - Hades
 - Kano
+- Kaladin
 - Kinox
 - Kuldax
 - Joxer
@@ -157,12 +162,19 @@
 - Drallion
 - Eve (Google Pixelbook)
 - Fatcat
+- Fatcat4ES
 - Fatcat_ish
 - Fatcatite
+- Fatcatite4ES
 - Fatcatnuvo
+- Fatcatnuvo4ES
 - Felino
+- Felino4ES
 - Francka
+- Kinmen4ES
 - Kinmen
+- Lapis
+- Moonstone
 - Fizz
 - Karma
 - Endeavour
@@ -245,7 +257,14 @@
 - Oak
 - Elm (Acer Chromebook R13)
 - Hana (Lenovo N23 Yoga Chromebook)
+- Matsu
 - Ocelot
+- Ocelotite
+- Ocelotmchp
+- Ojal
+- Ocelot4ES
+- Ocelotite4ES
+- Ocelotmchp4ES
 - Parrot (Acer C7/C710 Chromebook)
 - Atlas (Google Pixelbook Go)
 - Poppy
@@ -297,8 +316,11 @@
 - Skyrim
 - Winterhold (Dell Latitude 3445 Chromebook)
 - Anakin
+- Baze
 - Obiwan
+- Padme
 - Skywalker
+- Tarkin
 - Yoda
 - Falco (HP Chromebook 14)
 - Leon (Toshiba Chromebook)
@@ -358,6 +380,7 @@
 - Woomax (ASUS Chromebook Flip CM5)
 
 ## HP
+- Compaq Pro 6300 SFF/MT
 - Compaq 8200 Elite SFF
 - Compaq 8200 Elite USDT
 - Compaq 8300 Elite SFF
@@ -393,7 +416,9 @@
 - Meteorlake-P RVP with Chrome EC for non-Prod Silicon
 - Meteorlake-P RVP with Microchip EC
 - Ptlrvp
+- Ptlrvp4es
 - Google Chrome EC
+- Google Chrome EC for Early Silicon
 - shadowmountain
 - Strago
 - Tigerlake UP3 RVP

From 07df08836eca9dd755cc32b6d78727760d201605 Mon Sep 17 00:00:00 2001
From: Martin Roth <gaumless@gmail.com>
Date: Sun, 21 Sep 2025 14:40:43 -0600
Subject: [PATCH 2108/3886] Docs/releases: Update release notes for 25.09
 release

These are the preliminary release notes. They'll need to be updated
with any changes done this week. We'll need another patch after the tag
to capture the final statistics. The notes will be changed from
"Upcoming release" after the tag is done.

Change-Id: I0b4a1ad351a5772059061837a32d3d8a08c43885
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89283
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 .../releases/coreboot-25.09-relnotes.md       | 235 ++++++++++++++----
 1 file changed, 193 insertions(+), 42 deletions(-)

diff --git a/Documentation/releases/coreboot-25.09-relnotes.md b/Documentation/releases/coreboot-25.09-relnotes.md
index 485f9cd412..fafbc1795b 100644
--- a/Documentation/releases/coreboot-25.09-relnotes.md
+++ b/Documentation/releases/coreboot-25.09-relnotes.md
@@ -1,28 +1,110 @@
 Upcoming release - coreboot 25.09
 ========================================================================
 
-The 25.09 release is scheduled for the end of September, 2025
+The coreboot project is pleased to announce the release of coreboot
+25.09, continuing our commitment to advancing open-source firmware
+development. This release incorporates over 680 commits from more than
+110 contributors, including more than 20 first time authors. This brings
+performance enhancements, improved boot functionality, and enhanced
+developer tooling. Key improvements include (up to) a 30% speed increase
+in LZMA decompression, new boot mode detection capabilities, and
+comprehensive utility tool enhancements that strengthen the development
+experience across all supported platforms.
 
+As always, the coreboot project extends our gratitude to all
+contributors who made this release possible. From experienced
+developers implementing complex optimizations to community members
+providing testing and feedback, your collective contributions drive
+the continued evolution of open firmware. The sustained engagement
+from our growing community demonstrates the vital importance of
+hardware freedom and transparent system initialization.
 
-Update this document with changes that should be in the release notes.
-
-* Please use Markdown.
-* See the past few release notes for the general format.
-* The chip and board additions and removals will be updated right
-  before the release, so those do not need to be added.
-* Note that all changes before the release are done are marked upcoming.
-  A final version of the notes are done after the release.
-
+The next coreboot release, 25.12, is scheduled for the end of December.
 
 
 Significant or interesting changes
 ----------------------------------
 
-* Add changes that need a full description here
+### SPI flash and payload loading performance improvements
 
-* This section should have full descriptions and can or should have
-  a link to the referenced commits.
+Multiple optimizations across the storage and decompression pipeline
+deliver significant boot time improvements. The most impactful change
+optimizes LZMA decompression (159afbc5d5) by using SSE prefetch
+instructions when CONFIG_SSE is enabled, allowing the SPI controller to
+preload data into CPU cache while decompression continues. This
+technique exploits the timing characteristics of SPI interfaces running
+at 100Mbit/s on Sandy Bridge mobile CPUs, achieving 46ms faster boot
+times, representing a 30% performance improvement during payload
+decompression. Testing on Lenovo X220 demonstrated the payload loading
+bandwidth increased to 53 Mbit/s.
 
+Intel Panther Lake platforms receive dedicated asynchronous file loading
+capabilities (2de0158eec) that utilize SPI DMA to preload the fsps.bin
+file while the CPU executes other boot tasks. This cooperative
+multithreading approach maintains boot predictability while improving
+performance by approximately 17-18 ms on tested Fatcat devices. The
+implementation strategically coordinates with chipset lockdown settings
+to ensure preloading completes before SPI DMA interfaces are locked,
+requiring special FSP binaries when CHIPSET_LOCKDOWN_COREBOOT is used.
+
+Supporting infrastructure improvements ensure robust and efficient DMA
+operations across platforms. A new synchronization function
+cbfs_preload_wait_for_all() (3b069d320c) provides safe shutdown points
+for asynchronous operations before storage backends are deactivated. The
+Fast SPI DMA subsystem gains a token-based transfer queue (eb1b5ee116)
+that minimizes gaps between consecutive DMA operations, creating more
+consistent and predictable boot performance. Additionally, CBFS cache
+buffer alignment was corrected (454079c3bc) to properly honor
+CONFIG_CBFS_CACHE_ALIGN requirements, ensuring optimal memory access
+patterns throughout the boot process.
+
+
+### lib: Enhanced boot mode information framework for payload coordination
+
+Implementation of comprehensive boot mode detection capabilities
+(a45c8441af, 893a2b008a) introduces the new `LB_TAG_BOOT_MODE` in
+coreboot tables, enabling platforms to communicate critical boot state
+information to payloads. The framework supports detection of normal
+mode, low-battery mode, and off-mode charging states through a
+standardized `enum boot_mode_t` interface.
+
+This enhancement is particularly valuable for platforms where the
+Application Processor manages charging solutions, as it eliminates the
+need for payloads to reimplement battery detection logic. By passing
+boot mode context through coreboot tables, the system ensures
+consistent battery and charging information availability across both
+firmware and payload phases.
+
+The implementation includes a new weak function `lb_add_boot_mode()`
+that platforms can override to provide specific boot mode detection
+logic. This approach maintains backward compatibility while enabling
+platforms to implement sophisticated power management strategies based
+on hardware capabilities and charging state requirements.
+
+
+### drivers/intel/fsp2_0: Optimized graphics memory initialization sequence
+
+A comprehensive refactoring of graphics memory MTRR management
+(5f0225a7b5) improves FSP-S initialization performance by moving Write-
+Combine MTRR setup for graphics memory from logo rendering functions to
+the silicon initialization phase. The new `soc_mark_gfx_memory()`
+helper function establishes temporary WC MTRRs earlier in the boot
+process, enabling better memory access patterns during graphics
+initialization.
+
+This optimization addresses performance issues specifically affecting
+platforms using `USE_COREBOOT_FOR_BMP_RENDERING` where logo rendering
+occurs through coreboot drivers rather than FSP logic. Testing
+demonstrated FSP Multi-Phase Silicon Init improvements from 123ms to
+115ms, representing a measurable reduction in graphics subsystem
+initialization time.
+
+The refactoring also improves code maintainability by decoupling MTRR
+management from logo rendering functions, creating a cleaner separation
+of concerns between memory configuration and graphics operations. This
+change enables more consistent performance across different graphics
+initialization scenarios while maintaining compatibility with existing
+platform configurations.
 
 
 Additional coreboot changes
@@ -31,8 +113,43 @@ Additional coreboot changes
 The following are changes across a number of patches, or changes worth
 noting, but not needing a full description.
 
-* Changes that only need a line or two of description go here.
-
+* AMD firmware tool (amdfwtool) enhancements for Turin platform support
+  with improved address mode handling and EFW structure parsing
+  capabilities (46b03e682c, 73dd7bb046, 97cf4a1919)
+* smmstoretool expansion supporting variable block sizes and secure
+  boot GUID aliasing for improved UEFI variable management
+  (00d954977c, 008f0ec078)
+* CBMEM utility robustness improvements replacing abort() with exit(1) for
+  better error handling in debugging scenarios (4fd3cb35c2)
+* Build system enhancements with improved sequential board building
+  support in abuild, and MediaTek platform build optimizations
+  (9c5557f982)
+* Memory subsystem improvements including SMBIOS memory type and form
+  factor updates (d4da533473, 183589dcbd), graphics memory compression
+  enablement for Panther Lake (ebab858d92, ad10d4a977), and enhanced
+  memory training capabilities (e31fbc493d, d5854e4139)
+* SPI flash handling improvements including addition of a 4-byte address
+  mode flag in `lb_spi_flash` and refactored 4-byte address mode entry/exit
+  handling (8dec5fcaf8, a01c368a8a, 8f09629fb1)
+* Expanded TPM support across multiple platforms with CRB TPM
+  enablement and improved fTPM integration for AMD platforms
+  (984c64295b, 4b58ec5ac2, 8df079c609)
+* Graphics and display improvements including enhanced logo rendering
+  with proper bottom margin handling (51a8e238b0) and QEMU bochs driver
+  architectural compatibility enhancements (5171098814)
+* cbfstool robustness improvements including overflow prevention when
+  sorting FIT table entries, bail-out on invalid ELF in amdcompress,
+  and fallback copying of segments when compression fails
+  (480ac15044, 69888bc7fc, f3ca3aa16b)
+* AMD PSP SPI flash semaphore implementation preventing SMM corruption
+  of SPI controller registers during concurrent access, with improved
+  flash busy checking in PSP SMI handler (a17a41559a, 038262155e)
+* Intel Fast SPI DMA transfer cleanup ensuring proper completion before
+  lockdown to prevent low power state over-consumption from hanging
+  transfers (ef0c650edf)
+* Numerous platform-specific enhancements for Intel, AMD, MediaTek, and
+  Qualcomm SoCs with improved power management, memory initialization,
+  and hardware interface support
 
 
 Changes to external resources
@@ -40,49 +157,83 @@ Changes to external resources
 
 ### Toolchain updates
 
+* Upgrade binutils from version 2.43 to 2.44 (0a94fcd2db)
+* Upgrade ACPICA from 20241212 to 20250404 (f2fed71533)
+* Upgrade MPFR from 4.2.1 to 4.2.2 (c3f5d7c1ee)
+* Enhanced compiler-rt build system using runtimes configuration (f1aa0a175b)
+* Improved build reliability with HOSTCFLAGS handling for GMP headers (ad9bfd4243)
+* Fixed IASL build initialization for OPT_LDFLAGS variable (07a8737cbd)
 
 
 ### Git submodule pointers
 
+* fsp: Update from commit id cc36ae2b57 to 9623d52450 (21 commits)
+* intel-microcode: Update from commit id eeb93b7a81 to 4ded52b4b0 (1 commit)
+* qc_blobs: Update from commit id a252198ec6 to 6379308814 (3 commits)
 
-### External payloads
 
+### Payloads
+
+* SeaBIOS: Update from 1.16.3 to 1.17.0, bringing improved hardware
+  compatibility with preferential PCI I/O allocation above 4GB on
+  64-bit capable machines, multiple simultaneous USB keyboard and mouse
+  support, SeaVGABIOS VBE palette data support, and removal of legacy
+  internally generated ACPI table support (d315f26217)
+* U-Boot: Upgrade from 2024.07 to 2025.07 (0e682859e7)
+* edk2: Configure capsule update support for FMP (Firmware Management
+  Protocol) capsules, with enhanced build system compatibility and
+  improved menu sizing for non-full-screen configurations
+* LinuxBoot: Build system improvements with corrected prerequisites
+  and target renaming for better maintainability (d233b6c903,
+  502d19be89, cba0f0b8b9)
+* Libpayload enhancements include coreboot boot mode table support for
+  improved payload coordination (893a2b008a), strsep() edge case fixes
+  for more robust string handling (8097809c8a), Qualcomm PCI driver ATU
+  configuration fix (53dd93ff14), cbmem console memory leak resolution
+  in error conditions (05396238da), and propagation of SPI flash address
+  mode flag to libpayload (61d74dc8f7)
 
 
 Platform Updates
 ----------------
 
 ### Added mainboards:
-* To be filled in immediately before the release by the release team
+
+* ASROCK SPC741D8-2L2T/BCM
+* GIGABYTE GA_H81M_D2W
+* Google BlueyH
+* Google Caboc
+* Google Kinmen4ES
+* Google Lapis
+* Google Matsu
+* Google Moonstone
+* Google Ojal
+* Google Padme
+* Google Quartz
+* Google QuenbiH
+* Google Tarkin
+* HP 260 G1 DM
+* HP Compaq Pro 6300 SFF/MT
+* HP ProDesk 600 G1 SFF
+* Intel Ptlrvp4es
+* Lenovo ThinkPad T480
+* Lenovo ThinkPad T480s
 
 
-### Removed Mainboards
-* To be filled in immediately before the release by the release team
-
-
-### Updated SoCs
-* To be filled in immediately before the release by the release team
-
-
-
-Plans to move platform support to a branch
-------------------------------------------
-* To be filled in immediately before the release by the release team
-
-
-
-Statistics from the 25.03 to the 25.06 release
+Statistics from the 25.06 to 25.09 release
 --------------------------------------------
-* To be filled in immediately before the release by the release team
-
-
-
-Significant Known and Open Issues
----------------------------------
-
-Issues from the coreboot bugtracker: <https://ticket.coreboot.org/>
-* To be filled in immediately before the release by the release team
 
+* Total Commits: 684
+* Average Commits per day: 7.55
+* Total lines added: 62999
+* Average lines added per commit: 92.10
+* Number of patches adding more than 100 lines: 73
+* Average lines added per small commit: 38.99
+* Total lines removed: 10251
+* Average lines removed per commit: 14.99
+* Total difference between added and removed: 52748
+* Total authors: 112
+* New authors: 21
 
 
 coreboot Links and Contact Information

From 4a7d779ed0c4cb68053ad5dae8ce5585dafa07b1 Mon Sep 17 00:00:00 2001
From: Shunxi Zhang <ot_shunxi.zhang@mediatek.corp-partner.google.com>
Date: Fri, 5 Sep 2025 18:00:43 +0800
Subject: [PATCH 2109/3886] soc/mediatek/mt8196: Set RTC EOSC calibration to 8
 seconds

Set the RTC EOSC (External Oscillator) calibration to 8 seconds in
rtc_boot flow to ensure the accuracy of the RTC time during long period
of suspend. Without this setting, default value is 0, meaning no EOSC
calibration.

BRANCH=rauru
BUG=b:441304060
TEST=emerge-rauru coreboot chromeos-bootimage, when suspend/
warmboot/coldboot, RTC boots and works normally.

Signed-off-by: Shunxi Zhang <ot_shunxi.zhang@mediatek.corp-partner.google.com>
Change-Id: Ia7f15a6056cfa6bd808bc5a91147c1d64aff1223
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89307
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
---
 src/soc/mediatek/mt8196/include/soc/mt6685_rtc.h | 2 ++
 src/soc/mediatek/mt8196/mt6685_rtc.c             | 5 +++++
 2 files changed, 7 insertions(+)

diff --git a/src/soc/mediatek/mt8196/include/soc/mt6685_rtc.h b/src/soc/mediatek/mt8196/include/soc/mt6685_rtc.h
index 612d2d424e..d6a48a96fc 100644
--- a/src/soc/mediatek/mt8196/include/soc/mt6685_rtc.h
+++ b/src/soc/mediatek/mt8196/include/soc/mt6685_rtc.h
@@ -120,6 +120,8 @@
 #define RTC_K_EOSC_RSV_1		(1 << 9)
 #define RTC_K_EOSC_RSV_2		(1 << 10)
 
+#define RTC_EOSC_CALI_TD_8SEC		(6 << 8)
+
 #define TMA_KEY				0x39e
 #define TMA_KEY_MASK			0xFF
 #define TMA_KEY_SHIFT			0
diff --git a/src/soc/mediatek/mt8196/mt6685_rtc.c b/src/soc/mediatek/mt8196/mt6685_rtc.c
index 36e29f5a2a..9837df4e59 100644
--- a/src/soc/mediatek/mt8196/mt6685_rtc.c
+++ b/src/soc/mediatek/mt8196/mt6685_rtc.c
@@ -570,6 +570,11 @@ void rtc_boot(void)
 		}
 	}
 
+	/* Set RTC EOSC calibration period = 8sec */
+	rtc_read(RTC_AL_DOW, &rdata);
+	rtc_write(RTC_AL_DOW, rdata | RTC_EOSC_CALI_TD_8SEC);
+	rtc_write_trigger();
+
 	/* Make sure RTC get the latest register info. */
 	rtc_read(RTC_BBPU, &rtc_bbpu);
 	rtc_write(RTC_BBPU, rtc_bbpu | RTC_BBPU_KEY | RTC_BBPU_RELOAD);

From 61488ffd57298b4a7882e1c5e12a502a0b2a5e6d Mon Sep 17 00:00:00 2001
From: Youwen Huang <huangyouwen5@huaqin.corp-partner.google.com>
Date: Fri, 19 Sep 2025 20:29:09 +0800
Subject: [PATCH 2110/3886] mb/google/skywalker: Add CS35L51 support for beep
 sound for Padme

Add the FW_CONFIG configuration for the Padme project of audio amp
and set up I2S for CS35L51.

BUG=b:422688421
TEST=emerge-jedi coreboot chromeos-bootimage
BRANCH=Skywalker

Change-Id: I3486561dcc8695d3d3585c4844654bb7c68a2979
Signed-off-by: Youwen Huang <huangyouwen5@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89273
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
---
 src/mainboard/google/skywalker/chromeos.c    |  5 ++++
 src/mainboard/google/skywalker/devicetree.cb |  1 +
 src/mainboard/google/skywalker/mainboard.c   | 24 ++++++++++++++++++--
 3 files changed, 28 insertions(+), 2 deletions(-)

diff --git a/src/mainboard/google/skywalker/chromeos.c b/src/mainboard/google/skywalker/chromeos.c
index 07341d9ee8..3a7510c5d0 100644
--- a/src/mainboard/google/skywalker/chromeos.c
+++ b/src/mainboard/google/skywalker/chromeos.c
@@ -81,6 +81,11 @@ void fill_lb_gpios(struct lb_gpios *gpios)
 			{GPIO_EN_SPKR.id, ACTIVE_HIGH, -1, "alc5645_spk_en"},
 		};
 		lb_add_gpios(gpios, alc5645_gpios, ARRAY_SIZE(alc5645_gpios));
+	} else if (fw_config_probe(FW_CONFIG(AUDIO_AMP, AMP_CS35L51))) {
+		struct lb_gpio cs35l51_gpios[] = {
+			{GPIO_RST_SPKR_L.id, ACTIVE_LOW, -1, "speaker reset"},
+		};
+		lb_add_gpios(gpios, cs35l51_gpios, ARRAY_SIZE(cs35l51_gpios));
 	}
 
 	struct lb_gpio edp_pwm_backlight_gpios[] = {
diff --git a/src/mainboard/google/skywalker/devicetree.cb b/src/mainboard/google/skywalker/devicetree.cb
index 16f2a688ba..e2618d1f19 100644
--- a/src/mainboard/google/skywalker/devicetree.cb
+++ b/src/mainboard/google/skywalker/devicetree.cb
@@ -9,6 +9,7 @@ fw_config
 		option AMP_RT9123 0
 		option AMP_RT1019 1
 		option AMP_ALC5645 3
+		option AMP_CS35L51 4
 	end
 
 	field STORAGE 30 31
diff --git a/src/mainboard/google/skywalker/mainboard.c b/src/mainboard/google/skywalker/mainboard.c
index 9952bfc1ec..9a1b0adb89 100644
--- a/src/mainboard/google/skywalker/mainboard.c
+++ b/src/mainboard/google/skywalker/mainboard.c
@@ -22,13 +22,31 @@
 
 #define AFE_SE_SECURE_CON1	(AUDIO_BASE + 0x5634)
 
-static void configure_rt9123_rt1019(void)
+static void setup_i2s_speaker(void)
 {
-	/* SoC I2S */
 	gpio_set_mode(GPIO_I2S_SPKR_BCK, GPIO_FUNC(DMIC0_DAT0, I2SOUT1_BCK));
 	gpio_set_mode(GPIO_I2S_SPKR_LRCK, GPIO_FUNC(DMIC1_CLK, I2SOUT1_LRCK));
 	gpio_set_mode(GPIO_I2S_SPKR_DO, GPIO_FUNC(DMIC1_DAT0, I2SOUT1_DO));
 
+	printk(BIOS_INFO, "%s: I2S configuration done\n", __func__);
+}
+
+static void configure_rt9123_rt1019(void)
+{
+	/* Set the SOC corresponding pin to I2S related function */
+	setup_i2s_speaker();
+
+	printk(BIOS_INFO, "%s: AMP configuration done\n", __func__);
+}
+
+static void configure_cs35l51(void)
+{
+	/* Set the SOC corresponding pin to I2S related function */
+	setup_i2s_speaker();
+
+	/* Init I2C bus timing register for audio codecs */
+	mtk_i2c_bus_init(I2C7, I2C_SPEED_STANDARD);
+
 	printk(BIOS_INFO, "%s: AMP configuration done\n", __func__);
 }
 
@@ -59,6 +77,8 @@ static void configure_audio(void)
 		configure_rt9123_rt1019();
 	else if (fw_config_probe(FW_CONFIG(AUDIO_AMP, AMP_ALC5645)))
 		configure_alc5645();
+	else if (fw_config_probe(FW_CONFIG(AUDIO_AMP, AMP_CS35L51)))
+		configure_cs35l51();
 	else
 		printk(BIOS_WARNING, "Unknown amp\n");
 }

From 3b34079b19b1e7e545b106066710a23aba3483be Mon Sep 17 00:00:00 2001
From: Eren Peng <peng.eren@inventec.corp-partner.google.com>
Date: Sat, 20 Sep 2025 13:52:26 +0800
Subject: [PATCH 2111/3886] mb/google/trulo/var/kaladin: Enable External bypass
 config2 settings

Enable External bypass config2 for kaladin and keep FIVR settings for kelsier, and set vccin_aux_imon_iccmax to PD_TIER_VOLUME based on intel
team suggestion.

BUG=b:445829422
TEST=build and flash to DUT, check suspend_stress_test -c 1 pass

Cq-Depend:chrome-internal:8601618
Change-Id: I79e4f61c4bef9b628756a882c8d8dc0a9cb2238c
Signed-off-by: Eren Peng <peng.eren@inventec.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89276
Reviewed-by: Doris <doris.hsu@intel.com>
Reviewed-by: Derek Huang <derekhuang@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
---
 .../google/brya/variants/kaladin/fw_config.c  | 23 +++++++++++++++++++
 .../brya/variants/kaladin/overridetree.cb     |  2 ++
 2 files changed, 25 insertions(+)

diff --git a/src/mainboard/google/brya/variants/kaladin/fw_config.c b/src/mainboard/google/brya/variants/kaladin/fw_config.c
index 6db352e3e9..7e15571ad4 100644
--- a/src/mainboard/google/brya/variants/kaladin/fw_config.c
+++ b/src/mainboard/google/brya/variants/kaladin/fw_config.c
@@ -1,9 +1,32 @@
+#include <boardid.h>
 #include <fw_config.h>
 #include <baseboard/variants.h>
 
 void variant_update_soc_chip_config(struct soc_intel_alderlake_config *config)
 {
+	uint32_t board_version = board_id();
+
 	if (fw_config_probe(FW_CONFIG(MB_USB, MB_USB_2C_1A))) {
 		config->tcss_ports[1] = (struct tcss_port_config) TCSS_PORT_DEFAULT(OC_SKIP);
 	}
+	if (fw_config_probe(FW_CONFIG(TABLET_MODE, TABLET_MODE_PRESENT)) && board_version >= 2) {
+		/* # Configure external V1P05/Vnn/VnnSx Rails */
+		config->ext_fivr_settings.configure_ext_fivr = 1;
+		config->ext_fivr_settings.v1p05_enable_bitmap =
+				FIVR_ENABLE_ALL_SX & ~FIVR_ENABLE_S0;
+		config->ext_fivr_settings.vnn_enable_bitmap =
+				FIVR_ENABLE_ALL_SX;
+		config->ext_fivr_settings.vnn_sx_enable_bitmap =
+				FIVR_ENABLE_ALL_SX;
+		config->ext_fivr_settings.v1p05_supported_voltage_bitmap =
+				FIVR_VOLTAGE_NORMAL;
+		config->ext_fivr_settings.vnn_supported_voltage_bitmap =
+				FIVR_VOLTAGE_MIN_ACTIVE;
+		config->ext_fivr_settings.v1p05_voltage_mv = 1050;
+		config->ext_fivr_settings.vnn_voltage_mv = 780;
+		config->ext_fivr_settings.vnn_sx_voltage_mv = 1050;
+		config->ext_fivr_settings.v1p05_icc_max_ma = 500;
+		config->ext_fivr_settings.vnn_icc_max_ma = 500;
+		printk(BIOS_INFO, "Configured External FIVR\n");
+	}
 }
diff --git a/src/mainboard/google/brya/variants/kaladin/overridetree.cb b/src/mainboard/google/brya/variants/kaladin/overridetree.cb
index 85867c9fd7..a31ed720c5 100644
--- a/src/mainboard/google/brya/variants/kaladin/overridetree.cb
+++ b/src/mainboard/google/brya/variants/kaladin/overridetree.cb
@@ -171,6 +171,8 @@ chip soc/intel/alderlake
 	register "pch_hda_idisp_link_frequency" = "HDA_LINKFREQ_96MHZ"
 	register "pch_hda_idisp_codec_enable" = "1"
 
+	register "vccin_aux_imon_iccmax" = "PD_TIER_VOLUME" # 27A
+
 	# Enable CNVi BT Audio offload
 	register "cnvi_bt_audio_offload" = "1"
 

From 3a84c93b5b8645c21d844df101b0f98923df02b5 Mon Sep 17 00:00:00 2001
From: Jeremy Compostella <jeremy.compostella@intel.com>
Date: Wed, 24 Sep 2025 13:56:39 -0700
Subject: [PATCH 2112/3886] soc/intel/pantherlake: Correct function naming and
 code style

Commit f3211e9639d1 ("soc/intel/pantherlake: Add support for Acoustic
Noise Mitigation UPDs") introduced minor coding convention
violations. These are being addressed as follows:

- Renames fill_fsps_acoustic_params to fill_fspm_acoustic_params to
  align with the naming conventions used for other FSP-M configuration
  functions.
- Removes an unnecessary empty line.
- Aligns function parameters.

Change-Id: I8652c2fee71c8e2742146b5e622633de78c1c17e
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89332
Reviewed-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Bora Guvendik <bora.guvendik@intel.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Pranava Y N <pranavayn@google.com>
---
 src/soc/intel/pantherlake/romstage/fsp_params.c | 7 +++----
 1 file changed, 3 insertions(+), 4 deletions(-)

diff --git a/src/soc/intel/pantherlake/romstage/fsp_params.c b/src/soc/intel/pantherlake/romstage/fsp_params.c
index ba6c110f2e..30b4eac48a 100644
--- a/src/soc/intel/pantherlake/romstage/fsp_params.c
+++ b/src/soc/intel/pantherlake/romstage/fsp_params.c
@@ -356,8 +356,8 @@ void platform_display_early_shutdown_notification(void *arg)
 }
 #endif
 
-static void fill_fsps_acoustic_params(FSP_M_CONFIG *m_cfg,
-				   const struct soc_intel_pantherlake_config *config)
+static void fill_fspm_acoustic_params(FSP_M_CONFIG *m_cfg,
+				      const struct soc_intel_pantherlake_config *config)
 {
 	if (!config->enable_acoustic_noise_mitigation)
 		return;
@@ -370,7 +370,6 @@ static void fill_fsps_acoustic_params(FSP_M_CONFIG *m_cfg,
 	}
 }
 
-
 static void soc_memory_init_params(FSP_M_CONFIG *m_cfg,
 				   const struct soc_intel_pantherlake_config *config)
 {
@@ -392,7 +391,7 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg,
 		fill_fspm_trace_params,
 		fill_fspm_thermal_params,
 		fill_fspm_vr_config_params,
-		fill_fsps_acoustic_params,
+		fill_fspm_acoustic_params,
 	};
 
 	for (size_t i = 0; i < ARRAY_SIZE(fill_fspm_params); i++)

From f61ffb68c985f4f3bdb3832e8c1daafc2975ec6b Mon Sep 17 00:00:00 2001
From: Bora Guvendik <bora.guvendik@intel.com>
Date: Wed, 24 Sep 2025 14:23:33 -0700
Subject: [PATCH 2113/3886] soc/intel/pantherlake: Remove unused TxDqDqs
 retraining parameter
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

This commit removes the unused `lp_ddr_dq_dqs_re_training` field from
various memory configuration structures across multiple mainboard
variants, including google/fatcat, google/ocelot, and intel/ptlrvp.
This change should reduce complexity and prevent unnecessary memory
operations related to DQ/DQS retraining.

Write DqDqs retraining is enabled in Intel FSP by default. This can be
verified with debug FSP logs by checking WRTRETRAIN and
"MRC task -- Write DQ/DQS Retraining -- Started." prints.

BUG=None
TEST=Boot to OS on google fatcat board and verify DQ/DQS retraining.

Change-Id: Ib298b06260f576bee1f078dc09b1e23a9772b431
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89334
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Zhixing Ma <zhixing.ma@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/google/fatcat/variants/fatcat/memory.c    | 2 --
 src/mainboard/google/fatcat/variants/felino/memory.c    | 2 --
 src/mainboard/google/fatcat/variants/francka/memory.c   | 2 --
 src/mainboard/google/fatcat/variants/kinmen/memory.c    | 2 --
 src/mainboard/google/fatcat/variants/lapis/memory.c     | 2 --
 src/mainboard/google/fatcat/variants/moonstone/memory.c | 2 --
 src/mainboard/google/ocelot/variants/matsu/memory.c     | 2 --
 src/mainboard/google/ocelot/variants/ocelot/memory.c    | 4 ----
 src/mainboard/google/ocelot/variants/ojal/memory.c      | 2 --
 src/mainboard/intel/ptlrvp/variants/ptlrvp/memory.c     | 8 --------
 src/soc/intel/pantherlake/include/soc/meminit.h         | 3 ---
 11 files changed, 31 deletions(-)

diff --git a/src/mainboard/google/fatcat/variants/fatcat/memory.c b/src/mainboard/google/fatcat/variants/fatcat/memory.c
index e0908adabd..414d3998c9 100644
--- a/src/mainboard/google/fatcat/variants/fatcat/memory.c
+++ b/src/mainboard/google/fatcat/variants/fatcat/memory.c
@@ -55,8 +55,6 @@ static const struct mb_cfg lp5_mem_config = {
 
 	.ect = true, /* Early Command Training */
 
-	.lp_ddr_dq_dqs_re_training = 1,
-
 	.user_bd = BOARD_TYPE_ULT_ULX,
 
 	.lp5x_config = {
diff --git a/src/mainboard/google/fatcat/variants/felino/memory.c b/src/mainboard/google/fatcat/variants/felino/memory.c
index e0908adabd..414d3998c9 100644
--- a/src/mainboard/google/fatcat/variants/felino/memory.c
+++ b/src/mainboard/google/fatcat/variants/felino/memory.c
@@ -55,8 +55,6 @@ static const struct mb_cfg lp5_mem_config = {
 
 	.ect = true, /* Early Command Training */
 
-	.lp_ddr_dq_dqs_re_training = 1,
-
 	.user_bd = BOARD_TYPE_ULT_ULX,
 
 	.lp5x_config = {
diff --git a/src/mainboard/google/fatcat/variants/francka/memory.c b/src/mainboard/google/fatcat/variants/francka/memory.c
index c5b8165ca4..d7f331f25c 100644
--- a/src/mainboard/google/fatcat/variants/francka/memory.c
+++ b/src/mainboard/google/fatcat/variants/francka/memory.c
@@ -55,8 +55,6 @@ static const struct mb_cfg lp5_mem_config = {
 
 	.ect = true, /* Early Command Training */
 
-	.lp_ddr_dq_dqs_re_training = 1,
-
 	.user_bd = BOARD_TYPE_ULT_ULX,
 
 	.lp5x_config = {
diff --git a/src/mainboard/google/fatcat/variants/kinmen/memory.c b/src/mainboard/google/fatcat/variants/kinmen/memory.c
index 4637347562..b62eb34261 100644
--- a/src/mainboard/google/fatcat/variants/kinmen/memory.c
+++ b/src/mainboard/google/fatcat/variants/kinmen/memory.c
@@ -55,8 +55,6 @@ static const struct mb_cfg lp5_mem_config = {
 
 	.ect = true, /* Early Command Training */
 
-	.lp_ddr_dq_dqs_re_training = 1,
-
 	.user_bd = BOARD_TYPE_ULT_ULX,
 
 	.lp5x_config = {
diff --git a/src/mainboard/google/fatcat/variants/lapis/memory.c b/src/mainboard/google/fatcat/variants/lapis/memory.c
index 0c2a4e79fd..2fddc62b40 100644
--- a/src/mainboard/google/fatcat/variants/lapis/memory.c
+++ b/src/mainboard/google/fatcat/variants/lapis/memory.c
@@ -55,8 +55,6 @@ static const struct mb_cfg lp5_mem_config = {
 
 	.ect = true, /* Early Command Training */
 
-	.lp_ddr_dq_dqs_re_training = 1,
-
 	.user_bd = BOARD_TYPE_ULT_ULX,
 
 	.lp5x_config = {
diff --git a/src/mainboard/google/fatcat/variants/moonstone/memory.c b/src/mainboard/google/fatcat/variants/moonstone/memory.c
index 4637347562..b62eb34261 100644
--- a/src/mainboard/google/fatcat/variants/moonstone/memory.c
+++ b/src/mainboard/google/fatcat/variants/moonstone/memory.c
@@ -55,8 +55,6 @@ static const struct mb_cfg lp5_mem_config = {
 
 	.ect = true, /* Early Command Training */
 
-	.lp_ddr_dq_dqs_re_training = 1,
-
 	.user_bd = BOARD_TYPE_ULT_ULX,
 
 	.lp5x_config = {
diff --git a/src/mainboard/google/ocelot/variants/matsu/memory.c b/src/mainboard/google/ocelot/variants/matsu/memory.c
index 59fa99f0eb..5bcb96121b 100644
--- a/src/mainboard/google/ocelot/variants/matsu/memory.c
+++ b/src/mainboard/google/ocelot/variants/matsu/memory.c
@@ -35,8 +35,6 @@ static const struct mb_cfg lp5_mem_config = {
 
 	.ect = true, /* Early Command Training */
 
-	.lp_ddr_dq_dqs_re_training = 1,
-
 	.user_bd = BOARD_TYPE_ULT_ULX,
 
 	.lp5x_config = {
diff --git a/src/mainboard/google/ocelot/variants/ocelot/memory.c b/src/mainboard/google/ocelot/variants/ocelot/memory.c
index 43f40a9629..4f0a78a088 100644
--- a/src/mainboard/google/ocelot/variants/ocelot/memory.c
+++ b/src/mainboard/google/ocelot/variants/ocelot/memory.c
@@ -39,8 +39,6 @@ static const struct mb_cfg lp5_mem_config = {
 
 	.ect = true, /* Early Command Training */
 
-	.lp_ddr_dq_dqs_re_training = 1,
-
 	.user_bd = BOARD_TYPE_ULT_ULX,
 
 	.lp5x_config = {
@@ -55,8 +53,6 @@ static const struct mb_cfg ddr5_mem_config = {
 
 	.user_bd = BOARD_TYPE_ULT_ULX,
 
-	.lp_ddr_dq_dqs_re_training = 1,
-
 	.ddr_config = {
 		.dq_pins_interleaved = false,
 	},
diff --git a/src/mainboard/google/ocelot/variants/ojal/memory.c b/src/mainboard/google/ocelot/variants/ojal/memory.c
index 1315639496..c36eadb60e 100644
--- a/src/mainboard/google/ocelot/variants/ojal/memory.c
+++ b/src/mainboard/google/ocelot/variants/ojal/memory.c
@@ -38,8 +38,6 @@ static const struct mb_cfg lp5_mem_config = {
 
 	.ect = true, /* Early Command Training */
 
-	.lp_ddr_dq_dqs_re_training = 1,
-
 	.user_bd = BOARD_TYPE_ULT_ULX,
 
 	.lp5x_config = {
diff --git a/src/mainboard/intel/ptlrvp/variants/ptlrvp/memory.c b/src/mainboard/intel/ptlrvp/variants/ptlrvp/memory.c
index 350405dc29..4882edb324 100644
--- a/src/mainboard/intel/ptlrvp/variants/ptlrvp/memory.c
+++ b/src/mainboard/intel/ptlrvp/variants/ptlrvp/memory.c
@@ -56,8 +56,6 @@ static const struct mb_cfg gcs_mem_config = {
 
 	.ect = true, /* Early Command Training */
 
-	.lp_ddr_dq_dqs_re_training = 1,
-
 	.user_bd = BOARD_TYPE_ULT_ULX,
 
 	.lp5x_config = {
@@ -116,8 +114,6 @@ static const struct mb_cfg lp5_t3_mem_config = {
 
 	.ect = true, /* Early Command Training */
 
-	.lp_ddr_dq_dqs_re_training = 1,
-
 	.user_bd = BOARD_TYPE_ULT_ULX,
 
 	.lp5x_config = {
@@ -176,8 +172,6 @@ static const struct mb_cfg lp5_t4_mem_config = {
 
 	.ect = true, /* Early Command Training */
 
-	.lp_ddr_dq_dqs_re_training = 1,
-
 	.user_bd = BOARD_TYPE_ULT_ULX,
 
 	.lp5x_config = {
@@ -196,8 +190,6 @@ static const struct mb_cfg ddr5_mem_config = {
 
 	.user_bd = BOARD_TYPE_ULT_ULX,
 
-	.lp_ddr_dq_dqs_re_training = 1,
-
 	.ddr_config = {
 		.dq_pins_interleaved = false,
 	}
diff --git a/src/soc/intel/pantherlake/include/soc/meminit.h b/src/soc/intel/pantherlake/include/soc/meminit.h
index 7b72f9991c..63404f8c17 100644
--- a/src/soc/intel/pantherlake/include/soc/meminit.h
+++ b/src/soc/intel/pantherlake/include/soc/meminit.h
@@ -102,9 +102,6 @@ struct mb_cfg {
 
 	/* Command Mirror */
 	uint8_t cmd_mirror;
-
-	/* Enable/Disable TxDqDqs Retraining for LP5 */
-	uint8_t lp_ddr_dq_dqs_re_training;
 };
 
 void memcfg_init(FSPM_UPD *memupd, const struct mb_cfg *mb_cfg,

From 69b054137502008c09d499d0d4773cf2d9388304 Mon Sep 17 00:00:00 2001
From: Keith Hui <buurin@gmail.com>
Date: Sat, 26 Jul 2025 23:57:51 -0400
Subject: [PATCH 2114/3886] sio/nuvoton/nct6779d: Add power loss resume support

Adds long overdue power loss resume support to nct6779d using
code from nct5572d.

Change-Id: I91bf01a176716b97c6ca6a841c68cd3d4a39d23d
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88701
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/superio/nuvoton/nct6779d/Kconfig   |  1 +
 src/superio/nuvoton/nct6779d/superio.c | 22 ++++++++++++++++++++++
 2 files changed, 23 insertions(+)

diff --git a/src/superio/nuvoton/nct6779d/Kconfig b/src/superio/nuvoton/nct6779d/Kconfig
index ce2af16627..9f20f7b936 100644
--- a/src/superio/nuvoton/nct6779d/Kconfig
+++ b/src/superio/nuvoton/nct6779d/Kconfig
@@ -3,3 +3,4 @@
 config SUPERIO_NUVOTON_NCT6779D
 	bool
 	select SUPERIO_NUVOTON_COMMON_PRE_RAM
+	select HAVE_POWER_STATE_AFTER_FAILURE
diff --git a/src/superio/nuvoton/nct6779d/superio.c b/src/superio/nuvoton/nct6779d/superio.c
index 13604769ab..0381be2beb 100644
--- a/src/superio/nuvoton/nct6779d/superio.c
+++ b/src/superio/nuvoton/nct6779d/superio.c
@@ -2,13 +2,20 @@
 
 #include <device/device.h>
 #include <device/pnp.h>
+#include <option.h>
 #include <pc80/keyboard.h>
 #include <superio/conf_mode.h>
 
 #include "nct6779d.h"
 
+#define MAINBOARD_POWER_OFF	0
+#define MAINBOARD_POWER_ON	1
+#define MAINBOARD_POWER_KEEP	2
+
 static void nct6779d_init(struct device *dev)
 {
+	uint8_t byte, power_status;
+
 	if (!dev->enabled)
 		return;
 
@@ -17,6 +24,21 @@ static void nct6779d_init(struct device *dev)
 	case NCT6779D_KBC:
 		pc_keyboard_init(NO_AUX_DEVICE);
 		break;
+	case NCT6779D_ACPI:
+		/* Set power state after power fail */
+		power_status = get_uint_option("power_on_after_fail",
+				CONFIG_MAINBOARD_POWER_FAILURE_STATE);
+		pnp_enter_conf_mode(dev);
+		pnp_set_logical_device(dev);
+		byte = pnp_read_config(dev, 0xe4) & ~0x60;
+		if (power_status == MAINBOARD_POWER_ON)
+			byte |= (MAINBOARD_POWER_ON << 5);
+		else if (power_status == MAINBOARD_POWER_KEEP)
+			byte |= (MAINBOARD_POWER_KEEP << 5);
+		pnp_write_config(dev, 0xe4, byte);
+		pnp_exit_conf_mode(dev);
+		printk(BIOS_INFO, "set power %s after power fail\n", power_status ? "on" : "off");
+		break;
 	}
 }
 

From 894c8069fc3729c690aa17c2d8ab99134a09b1ea Mon Sep 17 00:00:00 2001
From: Keith Hui <buurin@gmail.com>
Date: Sun, 29 Dec 2024 17:21:28 -0500
Subject: [PATCH 2115/3886] superio/nuvoton: Add NCT5535D

Found on many Asus P8x7x series mainboards, NCT5535D is a 64-pin LPC
super I/O chip with no publicly available datasheet. However, it appears
to share the same silicon as NCT6779D. With only half the pins of 6779,
it does not have parallel port, serial port B, or GPIOs 1 and 6.

This patch adds header and Kconfig option for 5535, and adapts 6779
code to also supply C code to 5535 as well.

asus/p8z77-v_lx2 still builds once modified for this chip, but is not
tested further.

Change-Id: I3fe0dd6fc3010a50b781ca7c5c39ea73b91978a5
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85834
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/superio/nuvoton/Makefile.mk               |   1 +
 src/superio/nuvoton/nct5535d/Kconfig          |  10 +
 src/superio/nuvoton/nct5535d/Makefile.mk      |   3 +
 src/superio/nuvoton/nct5535d/acpi/superio.asl | 175 ++++++++++++++++++
 src/superio/nuvoton/nct5535d/nct5535d.c       |  27 +++
 src/superio/nuvoton/nct5535d/nct5535d.h       |  32 ++++
 src/superio/nuvoton/nct6779d/Makefile.mk      |   3 +-
 src/superio/nuvoton/nct6779d/nct6779d.c       |  42 +++++
 src/superio/nuvoton/nct6779d/nct6779d.h       |   6 +-
 src/superio/nuvoton/nct6779d/superio.c        |  41 +---
 10 files changed, 300 insertions(+), 40 deletions(-)
 create mode 100644 src/superio/nuvoton/nct5535d/Kconfig
 create mode 100644 src/superio/nuvoton/nct5535d/Makefile.mk
 create mode 100644 src/superio/nuvoton/nct5535d/acpi/superio.asl
 create mode 100644 src/superio/nuvoton/nct5535d/nct5535d.c
 create mode 100644 src/superio/nuvoton/nct5535d/nct5535d.h
 create mode 100644 src/superio/nuvoton/nct6779d/nct6779d.c

diff --git a/src/superio/nuvoton/Makefile.mk b/src/superio/nuvoton/Makefile.mk
index 570102ad2a..3c8df4f8f1 100644
--- a/src/superio/nuvoton/Makefile.mk
+++ b/src/superio/nuvoton/Makefile.mk
@@ -6,6 +6,7 @@ romstage-$(CONFIG_SUPERIO_NUVOTON_COMMON_PRE_RAM) += common/early_serial.c
 
 subdirs-$(CONFIG_SUPERIO_NUVOTON_WPCM450) += wpcm450
 subdirs-$(CONFIG_SUPERIO_NUVOTON_NCT5104D) += nct5104d
+subdirs-$(CONFIG_SUPERIO_NUVOTON_NCT5535D) += nct5535d nct6779d
 subdirs-$(CONFIG_SUPERIO_NUVOTON_NCT5539D) += nct5539d
 subdirs-$(CONFIG_SUPERIO_NUVOTON_NCT5572D) += nct5572d
 subdirs-$(CONFIG_SUPERIO_NUVOTON_NCT6687D) += nct6687d
diff --git a/src/superio/nuvoton/nct5535d/Kconfig b/src/superio/nuvoton/nct5535d/Kconfig
new file mode 100644
index 0000000000..a8b40440c1
--- /dev/null
+++ b/src/superio/nuvoton/nct5535d/Kconfig
@@ -0,0 +1,10 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
+config SUPERIO_NUVOTON_NCT5535D
+	bool
+	select SUPERIO_NUVOTON_COMMON_PRE_RAM
+	select HAVE_POWER_STATE_AFTER_FAILURE
+	help
+	  NCT5535D is a cut-down version of NCT6779D and is otherwise supported by
+	  superio/nuvoton/nct6779d, which provides C code for initialization. This directory
+	  only provides consistently-named header and structures.
diff --git a/src/superio/nuvoton/nct5535d/Makefile.mk b/src/superio/nuvoton/nct5535d/Makefile.mk
new file mode 100644
index 0000000000..bfac11a5f6
--- /dev/null
+++ b/src/superio/nuvoton/nct5535d/Makefile.mk
@@ -0,0 +1,3 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+ramstage-$(CONFIG_SUPERIO_NUVOTON_NCT5535D) += nct5535d.c
diff --git a/src/superio/nuvoton/nct5535d/acpi/superio.asl b/src/superio/nuvoton/nct5535d/acpi/superio.asl
new file mode 100644
index 0000000000..c23c3b47bf
--- /dev/null
+++ b/src/superio/nuvoton/nct5535d/acpi/superio.asl
@@ -0,0 +1,175 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+/*
+ * Include this file into a mainboard's DSDT _SB device tree and it will
+ * expose the NCT5535D SuperIO and some of its functionality.
+ *
+ * It allows the change of IO ports, IRQs and DMA settings on logical
+ * devices, disabling and reenabling logical devices.
+ *
+ *   LDN		State
+ * 0x2 SP1		Implemented, untested
+ * 0x5 KBC		Implemented, untested
+ * 0x8 GPIO		Implemented, untested
+ * 0xb HWM		Implemented, untested
+ *
+ * Controllable through preprocessor defines:
+ * SUPERIO_DEV		Device identifier for this SIO (e.g. SIO0)
+ * SUPERIO_PNP_BASE	I/O address of the first PnP configuration register
+ * NCT5535D_SHOW_SP1	If defined, Serial Port 1 will be exposed.
+ * NCT5535D_SHOW_KBC	If defined, the Keyboard Controller will be exposed.
+ * NCT5535D_SHOW_GPIO	If defined, GPIO support will be exposed.
+ * NCT5535D_SHOW_HWM	If defined, the Environment Controller will be exposed.
+ */
+#include <superio/nuvoton/nct5535d/nct5535d.h>
+
+#undef SUPERIO_CHIP_NAME
+#define SUPERIO_CHIP_NAME NCT5535D
+#include <superio/acpi/pnp.asl>
+
+#undef PNP_DEFAULT_PSC
+#define PNP_DEFAULT_PSC Return (0) /* no power management */
+
+#define ENABLE_KEYBOARD_WAKEUP SKWK
+#define POWER_LOSS_CONTROL     SPWL
+
+Device(SUPERIO_DEV) {
+	Name (_HID, EisaId("PNP0A05"))
+	Name (_STR, Unicode("Nuvoton NCT5535D Super I/O"))
+	Name (_UID, SUPERIO_UID(SUPERIO_DEV,))
+
+	/* SuperIO configuration ports */
+	OperationRegion (CREG, SystemIO, SUPERIO_PNP_BASE, 2)
+	Field (CREG, ByteAcc, NoLock, Preserve)
+	{
+		PNP_ADDR_REG,	8,
+		PNP_DATA_REG,	8,
+	}
+	IndexField (PNP_ADDR_REG, PNP_DATA_REG, ByteAcc, NoLock, Preserve)
+	{
+		Offset (0x07),
+		PNP_LOGICAL_DEVICE,	8, /* Logical device selector */
+
+		Offset (0x30),
+		PNP_DEVICE_ACTIVE,	1, /* Logical device activation */
+		ACT1,			1, /* Logical device activation */
+		ACT2,			1, /* Logical device activation */
+		ACT3,			1, /* Logical device activation */
+		ACT4,			1, /* Logical device activation */
+		ACT5,			1, /* Logical device activation */
+		ACT6,			1, /* Logical device activation */
+		ACT7,			1, /* Logical device activation */
+
+		Offset (0x60),
+		PNP_IO0_HIGH_BYTE,	8, /* First I/O port base - high byte */
+		PNP_IO0_LOW_BYTE,	8, /* First I/O port base - low byte */
+		Offset (0x62),
+		PNP_IO1_HIGH_BYTE,	8, /* Second I/O port base - high byte */
+		PNP_IO1_LOW_BYTE,	8, /* Second I/O port base - low byte */
+
+		Offset (0x70),
+		PNP_IRQ0,		8, /* First IRQ */
+		Offset (0x72),
+		PNP_IRQ1,		8, /* Second IRQ */
+		Offset (0x74),
+		PNP_DMA0,		8, /* DRQ */
+		Offset (0xe0),		   /* Config register 0xe0 etc. */
+		,6,
+		ENABLE_KEYBOARD_WAKEUP,	1,
+		Offset (0xe4),
+		,5,
+		POWER_LOSS_CONTROL,	2,
+	}
+
+	Method (_CRS)
+	{
+		/* Announce the used I/O ports to the OS */
+		Return (ResourceTemplate () {
+			IO (Decode16, SUPERIO_PNP_BASE, SUPERIO_PNP_BASE, 0x01, 0x02)
+		})
+	}
+
+	Method (SIOS, 1, NotSerialized)
+	{
+		if (Arg0 == 5)
+		{
+			ENTER_CONFIG_MODE(NCT5535D_ACPI)
+			ENABLE_KEYBOARD_WAKEUP = 0
+			EXIT_CONFIG_MODE()
+		}
+	}
+
+	Method (SIOW, 1, NotSerialized)
+	{
+	}
+
+	#undef PNP_ENTER_MAGIC_1ST
+	#undef PNP_ENTER_MAGIC_2ND
+	#undef PNP_ENTER_MAGIC_3RD
+	#undef PNP_ENTER_MAGIC_4TH
+	#undef PNP_EXIT_MAGIC_1ST
+	#undef PNP_EXIT_SPECIAL_REG
+	#undef PNP_EXIT_SPECIAL_VAL
+	#define PNP_ENTER_MAGIC_1ST	0x87
+	#define PNP_ENTER_MAGIC_2ND	0x87
+	#define PNP_EXIT_MAGIC_1ST	0xaa
+	#include <superio/acpi/pnp_config.asl>
+
+#ifdef NCT5535D_SHOW_SP1
+	#undef SUPERIO_UART_LDN
+	#undef SUPERIO_UART_DDN
+	#undef SUPERIO_UART_PM_REG
+	#undef SUPERIO_UART_PM_VAL
+	#undef SUPERIO_UART_PM_LDN
+	#define SUPERIO_UART_LDN NCT5535D_SP1
+	#include <superio/acpi/pnp_uart.asl>
+#endif
+
+#ifdef NCT5535D_SHOW_KBC
+	#undef SUPERIO_KBC_LDN
+	#undef SUPERIO_KBC_PS2M
+	#undef SUPERIO_KBC_PS2LDN
+	#define SUPERIO_KBC_LDN NCT5535D_KBC
+	#define SUPERIO_KBC_PS2M
+	#include <superio/acpi/pnp_kbc.asl>
+#endif
+
+#ifdef NCT5535D_SHOW_HWM
+	#undef SUPERIO_PNP_HID
+	#undef SUPERIO_PNP_LDN
+	#undef SUPERIO_PNP_DDN
+	#undef SUPERIO_PNP_NO_DIS
+	#undef SUPERIO_PNP_PM_REG
+	#undef SUPERIO_PNP_PM_VAL
+	#undef SUPERIO_PNP_PM_LDN
+	#undef SUPERIO_PNP_IO0
+	#undef SUPERIO_PNP_IO1
+	#undef SUPERIO_PNP_IO2
+	#undef SUPERIO_PNP_IRQ0
+	#undef SUPERIO_PNP_IRQ1
+	#undef SUPERIO_PNP_DMA
+	#define SUPERIO_PNP_LDN NCT5535D_HWM_FPLED
+	#define SUPERIO_PNP_IO0 0x08, 0x08
+	#define SUPERIO_PNP_IO1 0x08, 0x08
+	#define SUPERIO_PNP_IRQ0
+	#include <superio/acpi/pnp_generic.asl>
+#endif
+
+#ifdef NCT5535D_SHOW_GPIO
+	#undef SUPERIO_PNP_HID
+	#undef SUPERIO_PNP_LDN
+	#undef SUPERIO_PNP_DDN
+	#undef SUPERIO_PNP_NO_DIS
+	#undef SUPERIO_PNP_PM_REG
+	#undef SUPERIO_PNP_PM_VAL
+	#undef SUPERIO_PNP_PM_LDN
+	#undef SUPERIO_PNP_IO0
+	#undef SUPERIO_PNP_IO1
+	#undef SUPERIO_PNP_IRQ0
+	#undef PNP_DEVICE_ACTIVE
+	#define PNP_DEVICE_ACTIVE ACT3
+	#define SUPERIO_PNP_LDN 8
+	#define SUPERIO_PNP_IO0 0x08, 0x08
+	#include <superio/acpi/pnp_generic.asl>
+#endif
+}
diff --git a/src/superio/nuvoton/nct5535d/nct5535d.c b/src/superio/nuvoton/nct5535d/nct5535d.c
new file mode 100644
index 0000000000..0b183a8bc1
--- /dev/null
+++ b/src/superio/nuvoton/nct5535d/nct5535d.c
@@ -0,0 +1,27 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <device/device.h>
+#include <device/pnp.h>
+
+#include "nct5535d.h"
+
+/* Initialization C code is provided by nct6779d */
+
+static struct pnp_info pnp_dev_info[] = {
+	{ NULL, NCT5535D_SP1, PNP_IO0 | PNP_IRQ0, 0x0ff8, },
+	{ NULL, NCT5535D_KBC, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_IRQ1,
+		0x0fff, 0x0fff, },
+	{ NULL, NCT5535D_HWM_FPLED, PNP_IO0 | PNP_IO1 | PNP_IRQ0,
+		0x0ffe, 0x0ffe, },
+	{ NULL, NCT5535D_GPIOBASE, PNP_IO0, 0x0ff8, },
+};
+
+static void enable_dev(struct device *dev)
+{
+	pnp_enable_devices(dev, &_nuvoton_nct6779d_ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info);
+}
+
+struct chip_operations superio_nuvoton_nct5535d_ops = {
+	.name = "NUVOTON NCT5535D Super I/O",
+	.enable_dev = enable_dev,
+};
diff --git a/src/superio/nuvoton/nct5535d/nct5535d.h b/src/superio/nuvoton/nct5535d/nct5535d.h
new file mode 100644
index 0000000000..a1c2aff8e9
--- /dev/null
+++ b/src/superio/nuvoton/nct5535d/nct5535d.h
@@ -0,0 +1,32 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#ifndef SUPERIO_NUVOTON_NCT5535D_H
+#define SUPERIO_NUVOTON_NCT5535D_H
+
+#include "../nct6779d/nct6779d.h"
+
+/* All aliases to NCT6779D numbers. */
+#define NCT5535D_SP1		NCT6779D_SP1
+#define NCT5535D_KBC		NCT6779D_KBC
+#define NCT5535D_GPIO78_V	NCT6779D_GPIO678_V
+#define NCT5535D_WDT1_V		NCT6779D_WDT1_GPIO01_V
+#define NCT5535D_GPIO_V		NCT6779D_GPIO12345678_V
+#define NCT5535D_ACPI		NCT6779D_ACPI
+#define NCT5535D_HWM_FPLED	NCT6779D_HWM_FPLED
+#define NCT5535D_WDT1_MASK	NCT6779D_WDT1
+#define NCT5535D_GPIO_PP_OD	NCT6779D_GPIO_PP_OD
+#define NCT5535D_PRT80		NCT6779D_PRT80
+#define NCT5535D_DSLP		NCT6779D_DSLP
+
+#ifndef __ACPI__
+#define NCT5535D_GPIOBASE	((3 << 8) | NCT5535D_WDT1_V)
+#define NCT5535D_WDT1		NCT5535D_WDT1_V
+#define NCT5535D_GPIO2		((2 << 8) | NCT5535D_GPIO_V)
+#define NCT5535D_GPIO3		((3 << 8) | NCT5535D_GPIO_V)
+#define NCT5535D_GPIO4		((4 << 8) | NCT5535D_GPIO_V)
+#define NCT5535D_GPIO5		((5 << 8) | NCT5535D_GPIO_V)
+#define NCT5535D_GPIO7		((7 << 8) | NCT5535D_GPIO_V)
+#define NCT5535D_GPIO8		((0 << 8) | NCT5535D_GPIO_V)
+#endif
+
+#endif /* SUPERIO_NUVOTON_NCT5535D_H */
diff --git a/src/superio/nuvoton/nct6779d/Makefile.mk b/src/superio/nuvoton/nct6779d/Makefile.mk
index d5476e4625..327081f7f9 100644
--- a/src/superio/nuvoton/nct6779d/Makefile.mk
+++ b/src/superio/nuvoton/nct6779d/Makefile.mk
@@ -1,3 +1,4 @@
 # SPDX-License-Identifier: GPL-2.0-or-later
 
-ramstage-$(CONFIG_SUPERIO_NUVOTON_NCT6779D) += superio.c
+ramstage-$(CONFIG_SUPERIO_NUVOTON_NCT6779D) += superio.c nct6779d.c
+ramstage-$(CONFIG_SUPERIO_NUVOTON_NCT5535D) += superio.c
diff --git a/src/superio/nuvoton/nct6779d/nct6779d.c b/src/superio/nuvoton/nct6779d/nct6779d.c
new file mode 100644
index 0000000000..940f600775
--- /dev/null
+++ b/src/superio/nuvoton/nct6779d/nct6779d.c
@@ -0,0 +1,42 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <device/device.h>
+#include <device/pnp.h>
+#include "nct6779d.h"
+
+static struct pnp_info pnp_dev_info[] = {
+	{ NULL, NCT6779D_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x0ff8, },
+	{ NULL, NCT6779D_SP1, PNP_IO0 | PNP_IRQ0, 0x0ff8, },
+	{ NULL, NCT6779D_SP2, PNP_IO0 | PNP_IRQ0, 0x0ff8, },
+	{ NULL, NCT6779D_KBC, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_IRQ1,
+		0x0fff, 0x0fff, },
+	{ NULL, NCT6779D_CIR, PNP_IO0 | PNP_IRQ0, 0x0ff8, },
+	{ NULL, NCT6779D_ACPI, PNP_MSC2,},
+	{ NULL, NCT6779D_HWM_FPLED, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_MSC0,
+		0x0ffe, 0x0ffe, },
+	{ NULL, NCT6779D_WDT1},
+	{ NULL, NCT6779D_CIRWKUP, PNP_IO0 | PNP_IRQ0, 0x0ff8, },
+	{ NULL, NCT6779D_GPIO_PP_OD},
+	{ NULL, NCT6779D_PRT80},
+	{ NULL, NCT6779D_DSLP},
+	{ NULL, NCT6779D_GPIOBASE, PNP_IO0, 0x0ff8, },
+	{ NULL, NCT6779D_GPIO0},
+	{ NULL, NCT6779D_GPIO1},
+	{ NULL, NCT6779D_GPIO2},
+	{ NULL, NCT6779D_GPIO3},
+	{ NULL, NCT6779D_GPIO4},
+	{ NULL, NCT6779D_GPIO5, PNP_MSC4 | PNP_MSC5},
+	{ NULL, NCT6779D_GPIO6, PNP_MSC4 | PNP_MSC5},
+	{ NULL, NCT6779D_GPIO7},
+	{ NULL, NCT6779D_GPIO8},
+};
+
+static void enable_dev(struct device *dev)
+{
+	pnp_enable_devices(dev, &_nuvoton_nct6779d_ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info);
+}
+
+struct chip_operations superio_nuvoton_nct6779d_ops = {
+	.name = "NUVOTON NCT6779D Super I/O",
+	.enable_dev = enable_dev,
+};
diff --git a/src/superio/nuvoton/nct6779d/nct6779d.h b/src/superio/nuvoton/nct6779d/nct6779d.h
index 30694ea5c8..133450a083 100644
--- a/src/superio/nuvoton/nct6779d/nct6779d.h
+++ b/src/superio/nuvoton/nct6779d/nct6779d.h
@@ -3,8 +3,10 @@
 #ifndef SUPERIO_NUVOTON_NCT6779D_H
 #define SUPERIO_NUVOTON_NCT6779D_H
 
+#include <device/device.h>
+
 /* Logical Device Numbers (LDN). */
-#define NCT6779D_PP			0x01 /* Parallel port */
+#define NCT6779D_PP		0x01 /* Parallel port */
 #define NCT6779D_SP1		0x02 /* Com1 */
 #define NCT6779D_SP2		0x03 /* Com2 & IR */
 #define NCT6779D_KBC		0x05 /* PS/2 keyboard and mouse */
@@ -34,4 +36,6 @@
 #define NCT6779D_GPIO7		((7 << 8) | NCT6779D_GPIO12345678_V)
 #define NCT6779D_GPIO8		((0 << 8) | NCT6779D_GPIO12345678_V)
 
+extern struct device_operations _nuvoton_nct6779d_ops;
+
 #endif /* SUPERIO_NUVOTON_NCT6779D_H */
diff --git a/src/superio/nuvoton/nct6779d/superio.c b/src/superio/nuvoton/nct6779d/superio.c
index 0381be2beb..262170770c 100644
--- a/src/superio/nuvoton/nct6779d/superio.c
+++ b/src/superio/nuvoton/nct6779d/superio.c
@@ -8,6 +8,8 @@
 
 #include "nct6779d.h"
 
+/* C code shared by NCT6779D and NCT5535D */
+
 #define MAINBOARD_POWER_OFF	0
 #define MAINBOARD_POWER_ON	1
 #define MAINBOARD_POWER_KEEP	2
@@ -42,7 +44,7 @@ static void nct6779d_init(struct device *dev)
 	}
 }
 
-static struct device_operations ops = {
+struct device_operations _nuvoton_nct6779d_ops = {
 	.read_resources   = pnp_read_resources,
 	.set_resources    = pnp_set_resources,
 	.enable_resources = pnp_enable_resources,
@@ -50,40 +52,3 @@ static struct device_operations ops = {
 	.init             = nct6779d_init,
 	.ops_pnp_mode     = &pnp_conf_mode_8787_aa,
 };
-
-static struct pnp_info pnp_dev_info[] = {
-	{ NULL, NCT6779D_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x0ff8, },
-	{ NULL, NCT6779D_SP1, PNP_IO0 | PNP_IRQ0, 0x0ff8, },
-	{ NULL, NCT6779D_SP2, PNP_IO0 | PNP_IRQ0, 0x0ff8, },
-	{ NULL, NCT6779D_KBC, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_IRQ1,
-		0x0fff, 0x0fff, },
-	{ NULL, NCT6779D_CIR, PNP_IO0 | PNP_IRQ0, 0x0ff8, },
-	{ NULL, NCT6779D_ACPI, PNP_MSC2,},
-	{ NULL, NCT6779D_HWM_FPLED, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_MSC0,
-		0x0ffe, 0x0ffe, },
-	{ NULL, NCT6779D_WDT1},
-	{ NULL, NCT6779D_CIRWKUP, PNP_IO0 | PNP_IRQ0, 0x0ff8, },
-	{ NULL, NCT6779D_GPIO_PP_OD},
-	{ NULL, NCT6779D_PRT80},
-	{ NULL, NCT6779D_DSLP},
-	{ NULL, NCT6779D_GPIOBASE, PNP_IO0, 0x0ff8, },
-	{ NULL, NCT6779D_GPIO0},
-	{ NULL, NCT6779D_GPIO1},
-	{ NULL, NCT6779D_GPIO2},
-	{ NULL, NCT6779D_GPIO3},
-	{ NULL, NCT6779D_GPIO4},
-	{ NULL, NCT6779D_GPIO5, PNP_MSC4 | PNP_MSC5},
-	{ NULL, NCT6779D_GPIO6, PNP_MSC4 | PNP_MSC5},
-	{ NULL, NCT6779D_GPIO7},
-	{ NULL, NCT6779D_GPIO8},
-};
-
-static void enable_dev(struct device *dev)
-{
-	pnp_enable_devices(dev, &ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info);
-}
-
-struct chip_operations superio_nuvoton_nct6779d_ops = {
-	.name = "NUVOTON NCT6779D Super I/O",
-	.enable_dev = enable_dev,
-};

From 7d44128b2ff104934b2f5f9a6e995be284af3dbf Mon Sep 17 00:00:00 2001
From: Keith Hui <buurin@gmail.com>
Date: Fri, 5 Sep 2025 19:50:51 -0400
Subject: [PATCH 2116/3886] mb/asus/p8z77-m_pro: Enable serial port A instead

Boardview shows the COM port header is connected to serial port A on the
super I/O chip while serial port B pins are unconnected, but it has been
coded for serial port B which cannot be correct.
Change to initialize serial port A instead.

This aligns it with other variants in the family, allowing it
to take advantage of future bootblock code unification.

Change-Id: I8c1a46bef7d9c89f423f8fea9a826b9549d783b4
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89085
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/asus/p8x7x-series/Kconfig                     | 1 +
 .../asus/p8x7x-series/variants/p8z77-m_pro/early_init.c     | 2 +-
 .../asus/p8x7x-series/variants/p8z77-m_pro/overridetree.cb  | 6 +++---
 3 files changed, 5 insertions(+), 4 deletions(-)

diff --git a/src/mainboard/asus/p8x7x-series/Kconfig b/src/mainboard/asus/p8x7x-series/Kconfig
index 112d861f94..cfff67a0dc 100644
--- a/src/mainboard/asus/p8x7x-series/Kconfig
+++ b/src/mainboard/asus/p8x7x-series/Kconfig
@@ -33,6 +33,7 @@ config BOARD_ASUS_P8Z77_M_PRO
 	select DRIVERS_ASMEDIA_ASM1061 # for ASM1061 eSATA
 	select MEMORY_MAPPED_TPM
 	select SUPERIO_NUVOTON_NCT6779D
+	select SUPERIO_NUVOTON_COMMON_COM_A
 
 config BOARD_ASUS_P8Z77_V_LX2
 	select BOARD_ASUS_P8X7X_SERIES
diff --git a/src/mainboard/asus/p8x7x-series/variants/p8z77-m_pro/early_init.c b/src/mainboard/asus/p8x7x-series/variants/p8z77-m_pro/early_init.c
index 73a4c80628..81d9a3a9c8 100644
--- a/src/mainboard/asus/p8x7x-series/variants/p8z77-m_pro/early_init.c
+++ b/src/mainboard/asus/p8x7x-series/variants/p8z77-m_pro/early_init.c
@@ -11,7 +11,7 @@
 #include <northbridge/intel/sandybridge/raminit.h>
 #include <northbridge/intel/sandybridge/pei_data.h>
 
-#define SERIAL_DEV PNP_DEV(CONFIG_SUPERIO_PNP_BASE, NCT6779D_SP2)
+#define SERIAL_DEV PNP_DEV(CONFIG_SUPERIO_PNP_BASE, NCT6779D_SP1)
 
 void bootblock_mainboard_early_init(void)
 {
diff --git a/src/mainboard/asus/p8x7x-series/variants/p8z77-m_pro/overridetree.cb b/src/mainboard/asus/p8x7x-series/variants/p8z77-m_pro/overridetree.cb
index 0483f4a87c..5cbfaa2b02 100644
--- a/src/mainboard/asus/p8x7x-series/variants/p8z77-m_pro/overridetree.cb
+++ b/src/mainboard/asus/p8x7x-series/variants/p8z77-m_pro/overridetree.cb
@@ -33,10 +33,10 @@ chip northbridge/intel/sandybridge
 			device ref lpc on
 				chip superio/nuvoton/nct6779d
 					device pnp 2e.1 off end	# Parallel
-					device pnp 2e.2 off end	# UART A
-					device pnp 2e.3 on	# UART B, IR
-						io 0x60 = 0x2f8		# COM2 address
+					device pnp 2e.2 on	# UART A
+						io 0x60 = 0x3f8
 					end
+					device pnp 2e.3 off end	# UART B, IR
 					device pnp 2e.5 on	# PS2 KBC
 						io  0x60 = 0x0060	# KBC1 base
 						io  0x62 = 0x0064	# KBC2 base

From a5252bd5b97673c9ab6aaa532e29689811d10118 Mon Sep 17 00:00:00 2001
From: Stefan Binding <sbinding@opensource.cirrus.com>
Date: Wed, 27 Aug 2025 16:51:45 +0100
Subject: [PATCH 2117/3886] drivers/soundwire/cs35l56: Support Cirrus Logic
 CS35L56 Smart Amplifier Family

Add support for Class-D Smart Amplifiers: CS35L56, CS35L57 and CS35L63.

CS35L56 and CS35L57 are 18.5 V Class D Smart Amplifiers with Multi-Cell
Battery Boost.

CS35L63 is a PC Smart Amplifier with Speaker Protection and Audio
Enhancement Algorithms.

The driver was written based on the Datasheets for these parts and
generates the audio SSDT information for the amplifiers. Since all
three parts are part of the same family they all have similar SoundWire
settings.

The user can configure which part, SSID and Speaker ID is generated in
ACPI, as well as define each amplifier's Soundwire Unique ID and Link
ID.

These parts support DisCo Version v2.1, but coreboot currently only
supports DisCo v1.0, so ACPI is only generated based on DisCo v1.0.

These parts also support the SDCA v1.0 Specification (from DisCo v2.1)
is also not currently supported by coreboot, therefore SDCA ACPI
properties are also not generated.

This is currently only tested using QEMU using example configuration:

chip drivers/soundwire/cs35l56
	# SoundWire Link 2 ID 3
	register "desc" = ""Left Speaker Amp""
	register "part_id" = "MIPI_DEV_ID_CIRRUS_CS35L56"
	register "sub" = ""12345678""
	device generic 2.3 on end
end

Which produces the ACPI:

Device (SW23)
{
    Name (_ADR, 0x00023301FA355601)  // _ADR: Address
    Name (_DDN, "Left Speaker Amp")  // _DDN: DOS Device Name
    Name (_SUB, "12345678")  // _SUB: Subsystem ID
    Method (_STA, 0, NotSerialized)  // _STA: Status
    {
        Return (0x0F)
    }

    Name (_DSD, Package (0x04)  // _DSD: Device-Specific Data
    {
        ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301") /* Device Properties for _DSD */,
        Package (0x0F)
        {
            Package (0x02)
            {
                "mipi-sdw-sw-interface-revision",
                0x00010000
            },

            [...]

            Package (0x02)
            {
                "mipi-sdw-source-port-list",
                0x18
            },

            Package (0x02)
            {
                "mipi-sdw-sink-port-list",
                0x06
            }
        },

        ToUUID ("dbb8e3e6-5886-4ba6-8795-1319f52a966b") /* Hierarchical Data Extension */,
        Package (0x06)
        {
            Package (0x02)
            {
                "mipi-sdw-port-bra-mode-0",
                "BRA0"
            },

            Package (0x02)
            {
                "mipi-sdw-dp-0-subproperties",
                "DP0"
            },

            Package (0x02)
            {
                "mipi-sdw-dp-1-sink-subproperties",
                "SNK1"
            },

            Package (0x02)
            {
                "mipi-sdw-dp-2-sink-subproperties",
                "SNK2"
            },

            Package (0x02)
            {
                "mipi-sdw-dp-3-source-subproperties",
                "SRC3"
            },

            Package (0x02)
            {
                "mipi-sdw-dp-4-source-subproperties",
                "SRC4"
            }
        }
    })
    Name (BRA0, Package (0x02)
    {
        ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301") /* Device Properties for _DSD */,
        Package (0x04)
        {
            Package (0x02)
            {
                "mipi-sdw-bra-mode-min-bus-frequency",
                Zero
            },

            Package (0x02)
            {
                "mipi-sdw-bra-mode-max-bus-frequency",
                Zero
            },

            Package (0x02)
            {
                "mipi-sdw-bra-mode-max-data-per-frame",
                0x01D6
            },

            Package (0x02)
            {
                "mipi-sdw-bra-mode-min-us-between-transactions",
                Zero
            }
        }
    })
    Name (DP0, Package (0x04)
    {
        ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301") /* Device Properties for _DSD */,
        Package (0x07)
        {
            Package (0x02)
            {
                "mipi-sdw-port-wordlength-configs",
                Package (0x03)
                {
                    0x08,
                    0x10,
                    0x18
                }
            },

            [...]
        },

        ToUUID ("dbb8e3e6-5886-4ba6-8795-1319f52a966b") /* Hierarchical Data Extension */,
        Package (0x01)
        {
            Package (0x02)
            {
                "mipi-sdw-port-bra-mode-0",
                "BRA0"
            }
        }
    })
    Name (SNK1, Package (0x02)
    {
        ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301") /* Device Properties for _DSD */,
        Package (0x0C)
        {
            Package (0x02)
            {
                "mipi-sdw-data-port-type",
                Zero
            },

            Package (0x02)
            {
                "mipi-sdw-max-grouping-supported",
                Zero
            },

            Package (0x02)
            {
                "mipi-sdw-imp-def-dpn-interrupts-supported",
                Zero
            },

            Package (0x02)
            {
                "mipi-sdw-modes-supported",
                One
            },

            Package (0x02)
            {
                "mipi-sdw-max-async-buffer",
                Zero
            },

            Package (0x02)
            {
                "mipi-sdw-block-packing-mode",
                One
            },

            Package (0x02)
            {
                "mipi-sdw-port-encoding-type",
                One
            },

            Package (0x02)
            {
                "mipi-sdw-port-wordlength-configs",
                Package (0x03)
                {
                    0x08,
                    0x10,
                    0x18
                }
            },

            Package (0x02)
            {
                "mipi-sdw-simplified-channelprepare-sm",
                Zero
            },

            Package (0x02)
            {
                "mipi-sdw-port-channelprepare-timeout",
                Zero
            },

            Package (0x02)
            {
                "mipi-sdw-channel-number-list",
                Package (0x02)
                {
                    Zero,
                    One
                }
            },

            Package (0x02)
            {
                "mipi-sdw-channel-combination-list",
                Package (0x01)
                {
                    0x03
                }
            }
        }
    })
    Name (SNK2, Package (0x02)
    {
        [... same as SNK1 ...]
    })
    Name (SRC3, Package (0x02)
    {
        [... same as SNK1 ...]
    })
    Name (SRC4, Package (0x02)
    {
        [... same as SNK1 ...]
    })
}

Change-Id: Ie04020f008862051f26e0101828b5944d212e706
Signed-off-by: Stefan Binding <sbinding@opensource.cirrus.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89131
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/drivers/soundwire/cs35l56/Kconfig     |  10 ++
 src/drivers/soundwire/cs35l56/Makefile.mk |   3 +
 src/drivers/soundwire/cs35l56/chip.h      |  26 ++++
 src/drivers/soundwire/cs35l56/cs35l56.c   | 161 ++++++++++++++++++++++
 src/include/mipi/ids.h                    |   3 +
 5 files changed, 203 insertions(+)
 create mode 100644 src/drivers/soundwire/cs35l56/Kconfig
 create mode 100644 src/drivers/soundwire/cs35l56/Makefile.mk
 create mode 100644 src/drivers/soundwire/cs35l56/chip.h
 create mode 100644 src/drivers/soundwire/cs35l56/cs35l56.c

diff --git a/src/drivers/soundwire/cs35l56/Kconfig b/src/drivers/soundwire/cs35l56/Kconfig
new file mode 100644
index 0000000000..f07b837f4c
--- /dev/null
+++ b/src/drivers/soundwire/cs35l56/Kconfig
@@ -0,0 +1,10 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
+config DRIVERS_SOUNDWIRE_CS35L56_FAMILY
+	bool
+	depends on HAVE_ACPI_TABLES
+	default n
+	help
+	  SoundWire CS35L56 Family audio amp SSDT generator.
+	  This supports the CS35L56, CS35L57, and CS35L63 audio amplifiers
+	  from Cirrus Logic.
diff --git a/src/drivers/soundwire/cs35l56/Makefile.mk b/src/drivers/soundwire/cs35l56/Makefile.mk
new file mode 100644
index 0000000000..86bd0c698f
--- /dev/null
+++ b/src/drivers/soundwire/cs35l56/Makefile.mk
@@ -0,0 +1,3 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
+ramstage-$(CONFIG_DRIVERS_SOUNDWIRE_CS35L56_FAMILY) += cs35l56.c
diff --git a/src/drivers/soundwire/cs35l56/chip.h b/src/drivers/soundwire/cs35l56/chip.h
new file mode 100644
index 0000000000..bbac391607
--- /dev/null
+++ b/src/drivers/soundwire/cs35l56/chip.h
@@ -0,0 +1,26 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef __DRIVERS_SOUNDWIRE_CS35L56_FAMILY_CHIP_H__
+#define __DRIVERS_SOUNDWIRE_CS35L56_FAMILY_CHIP_H__
+
+#include <acpi/acpi.h>
+#include <acpi/acpi_device.h>
+#include <mipi/ids.h>
+
+enum cs35l56_part_ids {
+	CS35L56_PART_ID_CS35L56 = MIPI_DEV_ID_CIRRUS_CS35L56,
+	CS35L56_PART_ID_CS35L57 = MIPI_DEV_ID_CIRRUS_CS35L57,
+	CS35L63_PART_ID_CS35L63 = MIPI_DEV_ID_CIRRUS_CS35L63
+};
+
+struct drivers_soundwire_cs35l56_config {
+	char acpi_name[ACPI_NAME_BUFFER_SIZE]; /* Set by the acpi_name ops */
+	const char *desc;
+	enum cs35l56_part_ids part_id;
+	const char *sub; /* SUB ID to uniquely identify system */
+
+	/* Use GPIO based spkid gpio */
+	struct acpi_gpio spkid_gpio;
+};
+
+#endif /* __DRIVERS_SOUNDWIRE_CS35L56_FAMILY_CHIP_H__ */
diff --git a/src/drivers/soundwire/cs35l56/cs35l56.c b/src/drivers/soundwire/cs35l56/cs35l56.c
new file mode 100644
index 0000000000..97997b09c8
--- /dev/null
+++ b/src/drivers/soundwire/cs35l56/cs35l56.c
@@ -0,0 +1,161 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <acpi/acpigen.h>
+#include <acpi/acpi_device.h>
+#include <acpi/acpi_soundwire.h>
+#include <device/device.h>
+#include <device/soundwire.h>
+#include <mipi/ids.h>
+#include <stdio.h>
+
+#include "chip.h"
+
+static struct soundwire_address cs35l56_address = {
+	.version = SOUNDWIRE_VERSION_1_2,
+	.manufacturer_id = MIPI_MFG_ID_CIRRUS,
+	.class = MIPI_CLASS_SDCA
+};
+
+static struct soundwire_slave cs35l56_slave = {
+	.wake_up_unavailable = false,
+	.test_mode_supported = false,
+	.clock_stop_mode1_supported = false,
+	.simplified_clockstopprepare_sm_supported = false,
+	.paging_supported = true,
+	.source_port_list = SOUNDWIRE_PORT(3) | SOUNDWIRE_PORT(4),
+	.sink_port_list = SOUNDWIRE_PORT(1) | SOUNDWIRE_PORT(2),
+};
+
+static struct soundwire_dp0 cs35l56_dp0 = {
+	.port_wordlength_configs_count = 3,
+	.port_wordlength_configs = {8, 16, 24},
+	.bra_flow_controlled = true,
+	.bra_imp_def_response_supported = true,
+	.bra_role_supported = true,
+	.imp_def_dp0_interrupts_supported = 0,
+	.imp_def_bpt_supported = false,
+	.bra_mode_count = 1,
+	.bra_mode_list = { 0 }
+};
+
+static struct soundwire_bra_mode cs35l56_dp0_bra_mode = {
+	.max_data_per_frame = 470,
+	.block_alignment = 4,
+};
+
+static struct soundwire_dpn cs35l56_dpn = {
+	.data_port_type = FULL_DATA_PORT,
+	.max_grouping_supported = BLOCK_GROUP_COUNT_1,
+	.modes_supported = MODE_ISOCHRONOUS,
+	.max_async_buffer = 0,
+	.block_packing_mode = true,
+	.port_encoding_type = ENCODE_TWOS_COMPLEMENT,
+	.port_wordlength_configs_count = 3,
+	.port_wordlength_configs = {8, 16, 24},
+	.simplified_channelprepare_sm = false,
+	.channel_number_list_count = 2,
+	.channel_number_list = {0, 1},
+	.channel_combination_list_count = 1,
+	.channel_combination_list = {0x3},
+	.port_audio_mode_count = 0,
+};
+
+static const struct soundwire_codec cs35l56_codec = {
+	.slave = &cs35l56_slave,
+	.dp0 = &cs35l56_dp0,
+	.dp0_bra_mode = { &cs35l56_dp0_bra_mode },
+	.dpn = {
+		{
+			/* Data Input for Speaker Path */
+			.port = 1,
+			.sink = &cs35l56_dpn
+		},
+		{
+			/* Data Input for Speaker Path */
+			.port = 2,
+			.sink = &cs35l56_dpn
+		},
+		{
+			/* Data Output for Feedback Path */
+			.port = 3,
+			.source = &cs35l56_dpn
+		},
+		{
+			/* Data Output for Feedback Path */
+			.port = 4,
+			.source = &cs35l56_dpn
+		}
+	}
+};
+
+static void soundwire_cs35l56_fill_ssdt(const struct device *dev)
+{
+	struct drivers_soundwire_cs35l56_config *config = dev->chip_info;
+	const char *scope = acpi_device_scope(dev);
+	struct acpi_dp *dsd;
+
+	if (!scope)
+		return;
+
+	acpigen_write_scope(scope);
+	acpigen_write_device(acpi_device_name(dev));
+
+	/* Set codec address IDs. */
+	cs35l56_address.link_id = dev->path.generic.id;
+	cs35l56_address.unique_id = dev->path.generic.subid;
+	cs35l56_address.part_id = config->part_id;
+
+	acpigen_write_ADR_soundwire_device(&cs35l56_address);
+	acpigen_write_name_string("_DDN", config->desc ? : dev->chip_ops->name);
+	acpigen_write_name_string("_SUB", config->sub);
+	acpigen_write_STA(acpi_device_status(dev));
+
+	/* for spkid gpio */
+	if (config->spkid_gpio.pin_count) {
+		acpigen_write_name("_CRS");
+		acpigen_write_resourcetemplate_header();
+		acpi_device_write_gpio(&config->spkid_gpio);
+		acpigen_write_resourcetemplate_footer();
+	}
+
+	dsd = acpi_dp_new_table("_DSD");
+	soundwire_gen_codec(dsd, &cs35l56_codec, NULL);
+
+	if (config->spkid_gpio.pin_count)
+		acpi_dp_add_gpio(dsd, "spk-id-gpios", acpi_device_path(dev),
+			 0,  /* Index = 0 */
+			 0,  /* Pin = 0 (There is a single pin in the GPIO resource). */
+			 config->spkid_gpio.active_low);
+
+	acpi_dp_write(dsd);
+
+	acpigen_pop_len(); /* Device */
+	acpigen_pop_len(); /* Scope */
+}
+
+static const char *soundwire_cs35l56_acpi_name(const struct device *dev)
+{
+	struct drivers_soundwire_cs35l56_config *config = dev->chip_info;
+	if (config->acpi_name[0] != 0)
+		return config->acpi_name;
+	snprintf(config->acpi_name, sizeof(config->acpi_name), "SW%1X%1X",
+		 dev->path.generic.id, dev->path.generic.subid);
+	return config->acpi_name;
+}
+
+static struct device_operations soundwire_cs35l56_ops = {
+	.read_resources		= noop_read_resources,
+	.set_resources		= noop_set_resources,
+	.acpi_name		= soundwire_cs35l56_acpi_name,
+	.acpi_fill_ssdt		= soundwire_cs35l56_fill_ssdt,
+};
+
+static void soundwire_cs35l56_enable(struct device *dev)
+{
+	dev->ops = &soundwire_cs35l56_ops;
+}
+
+struct chip_operations drivers_soundwire_cs35l56_ops = {
+	.name = "Cirrus CS35L56 SoundWire Amplifier",
+	.enable_dev = soundwire_cs35l56_enable
+};
diff --git a/src/include/mipi/ids.h b/src/include/mipi/ids.h
index 5118a13cf0..3bab96cffb 100644
--- a/src/include/mipi/ids.h
+++ b/src/include/mipi/ids.h
@@ -34,5 +34,8 @@
 
 #define MIPI_MFG_ID_CIRRUS			0x01fa
 #define MIPI_DEV_ID_CIRRUS_CS42L42		0x4242
+#define MIPI_DEV_ID_CIRRUS_CS35L56		0x3556
+#define MIPI_DEV_ID_CIRRUS_CS35L57		0x3557
+#define MIPI_DEV_ID_CIRRUS_CS35L63		0x3563
 
 #endif /* __MIPI_IDS_H__ */

From 15b903e1fd1219f357d37ce3b10c5170c8775811 Mon Sep 17 00:00:00 2001
From: Bora Guvendik <bora.guvendik@intel.com>
Date: Wed, 24 Sep 2025 11:23:31 -0700
Subject: [PATCH 2118/3886] soc/intel/pantherlake: Add DDR5 memory type debug
 message
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

This commit introduces a debug message to the DDR5 memory type
initialization process within the Panther Lake SoC. By adding this log,
developers can gain better insights when diagnosing issues related to
DDR5 memory configurations.

BUG=none
TEST=Verify the debug message is displayed during DDR5 initialization.

Change-Id: I77ceea0f7a29983dd2e4ad1af26a0383721d7ca0
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89331
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
---
 src/soc/intel/pantherlake/meminit.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/src/soc/intel/pantherlake/meminit.c b/src/soc/intel/pantherlake/meminit.c
index 8d1a933992..01c217be3d 100644
--- a/src/soc/intel/pantherlake/meminit.c
+++ b/src/soc/intel/pantherlake/meminit.c
@@ -196,6 +196,7 @@ void memcfg_init(FSPM_UPD *memupd, const struct mb_cfg *mb_cfg,
 
 	switch (mb_cfg->type) {
 	case MEM_TYPE_DDR5:
+		printk(BIOS_DEBUG, "%s: module type is DDR5\n", __func__);
 		meminit_ddr(mem_cfg, &mb_cfg->ddr_config);
 		dq_dqs_auto_detect = true;
 		/*

From cb899b0c4deb0b2d7639d15e79368593ee952668 Mon Sep 17 00:00:00 2001
From: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Date: Mon, 22 Sep 2025 11:48:02 +0800
Subject: [PATCH 2119/3886] mb/google/brox/var/caboc: Update HDA verb table

Table is from vendor.
Decrease HWEQ high pass filter from 300Hz to 125Hz.

BUG=b:435345756
TEST=emerge-brox coreboot
     check system audio output is fine

Change-Id: Id8f20af4b37cb84ec1720e7c36082c7f8cf9abb1
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89284
Reviewed-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 .../google/brox/variants/caboc/include/variant/hda_verb.h   | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/src/mainboard/google/brox/variants/caboc/include/variant/hda_verb.h b/src/mainboard/google/brox/variants/caboc/include/variant/hda_verb.h
index 04942c5038..e6b4d057bf 100644
--- a/src/mainboard/google/brox/variants/caboc/include/variant/hda_verb.h
+++ b/src/mainboard/google/brox/variants/caboc/include/variant/hda_verb.h
@@ -84,7 +84,7 @@ const u32 cim_verb_data[] = {
 	0x0535001e,
 	0x05340800,
 	0x05350003,
-	0x05341EC4,
+	0x05341F7B,
 	0x05350004,
 	0x05340000,
 	/* Right Channel */
@@ -95,7 +95,7 @@ const u32 cim_verb_data[] = {
 	0x0545001e,
 	0x05440800,
 	0x05450003,
-	0x05441EC4,
+	0x05441F7B,
 	0x05450004,
 	0x05440000,
 	/* enable EQ */
@@ -104,7 +104,7 @@ const u32 cim_verb_data[] = {
 	/* 2.2W/4ohm */
 	0x02050038,
 	0x02046901,
-	/* Disable AGC and set AGC limit to 0dB  */
+	/* Disable AGC and set AGC limit to 0dB */
 	0x02050016,
 	0x02044C50,
 	0x02050012,

From d4b6b559775edf3ae125eb17a55292a751fa8c5d Mon Sep 17 00:00:00 2001
From: Sergii Dmytruk <sergii.dmytruk@3mdeb.com>
Date: Sat, 30 Aug 2025 18:57:50 +0300
Subject: [PATCH 2120/3886] payloads/Kconfig: default to Skiboot payload on
 PPC64

PPC64 is not functional without [OPAL] with which Linux kernel
communicates to implement important functionality like a TPM driver.
In addition to providing runtime services via OPAL Skiboot also handles
some parts of the boot process (like extracting kernel from flash) and
adjusts device tree as needed.

coreboot does not currently implement OPAL and is not likely to do it
any time soon (if ever), so must use Skiboot as a second-stage firmware
to have a fully functional PPC64 device.

mb/raptor-cs/talos-2/Kconfig is updated because Skiboot doesn't fit into
512 KiB image.

[OPAL]: https://open-power.github.io/skiboot/doc/opal-spec.html

Change-Id: I49ad6094acaccf731ab6d6b45ac103d485a3179c
Signed-off-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67070
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 payloads/Kconfig                        | 3 ++-
 src/mainboard/raptor-cs/talos-2/Kconfig | 2 +-
 2 files changed, 3 insertions(+), 2 deletions(-)

diff --git a/payloads/Kconfig b/payloads/Kconfig
index 586e54a4dd..be902a1b4b 100644
--- a/payloads/Kconfig
+++ b/payloads/Kconfig
@@ -4,7 +4,7 @@ menu "Payload"
 
 config PAYLOAD_NONE
 	bool "Don't add a payload"
-	default y if !ARCH_X86
+	default y if !ARCH_X86 && !ARCH_PPC64
 	help
 	  Select this option if you want to create an "empty" coreboot
 	  ROM image for a certain mainboard, i.e. a coreboot ROM image
@@ -17,6 +17,7 @@ if !PAYLOAD_NONE
 choice
 	prompt "Payload to add"
 	default PAYLOAD_SEABIOS if ARCH_X86
+	default PAYLOAD_SKIBOOT if ARCH_PPC64
 
 config PAYLOAD_ELF
 	bool "An ELF executable payload"
diff --git a/src/mainboard/raptor-cs/talos-2/Kconfig b/src/mainboard/raptor-cs/talos-2/Kconfig
index b0fd7d3e22..de2bd9e4ed 100644
--- a/src/mainboard/raptor-cs/talos-2/Kconfig
+++ b/src/mainboard/raptor-cs/talos-2/Kconfig
@@ -14,7 +14,7 @@ config BOARD_SPECIFIC_OPTIONS
 	def_bool y
 	select CPU_POWER9
 	select SOC_IBM_POWER9
-	select BOARD_ROMSIZE_KB_512
+	select BOARD_ROMSIZE_KB_1024
 	select SUPERIO_ASPEED_AST2400
 	select BOOT_DEVICE_NOT_SPI_FLASH
 	select MISSING_BOARD_RESET

From 6d265ca31d0640dd664b1318a5b03b98a06d57ca Mon Sep 17 00:00:00 2001
From: NyeonWoo Kim <knw0507@naver.com>
Date: Sun, 21 Sep 2025 14:47:29 +0900
Subject: [PATCH 2121/3886] device/pci_device: Fix typo in comments

I found a typo in the comments, so I fixed it.
It seems that 'this operations' is a typographical error.

Change-Id: Ic272e122ce180dee8c0516ecea27cd10932c2363
Signed-off-by: NyeonWoo Kim <knw0507@naver.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89282
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
---
 src/device/pci_device.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/src/device/pci_device.c b/src/device/pci_device.c
index baa7a48ff9..202e8b5055 100644
--- a/src/device/pci_device.c
+++ b/src/device/pci_device.c
@@ -1156,13 +1156,13 @@ struct device *pci_probe_dev(struct device *dev, struct bus *bus,
 	} else {
 		/*
 		 * Enable/disable the device. Once we have found the device-
-		 * specific operations this operations we will disable the
-		 * device with those as well.
+		 * specific operations, we will disable the device
+		 * with those as well.
 		 *
 		 * This is geared toward devices that have subfunctions
 		 * that do not show up by default.
 		 *
-		 * If a device is a stuff option on the motherboard
+		 * If a device is a stuff option on the motherboard,
 		 * it may be absent and enable_dev() must cope.
 		 */
 		/* Run the magic enable sequence for the device. */

From 7f8c442a09b46e110a0c191160abcd4427ff341e Mon Sep 17 00:00:00 2001
From: Jeremy Compostella <jeremy.compostella@intel.com>
Date: Thu, 25 Sep 2025 08:52:25 -0700
Subject: [PATCH 2122/3886] soc/intel/meteorlake: Correct function naming

Renames fill_fsps_acoustic_params to fill_fspm_acoustic_params to align
with the naming conventions used for other FSP-M configuration
functions.

Change-Id: I0044c21a8f82dfa2308fade78adbd8bcf844cb63
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89351
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
---
 src/soc/intel/meteorlake/romstage/fsp_params.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/soc/intel/meteorlake/romstage/fsp_params.c b/src/soc/intel/meteorlake/romstage/fsp_params.c
index 57e56595a9..414c270dcd 100644
--- a/src/soc/intel/meteorlake/romstage/fsp_params.c
+++ b/src/soc/intel/meteorlake/romstage/fsp_params.c
@@ -394,7 +394,7 @@ static void fill_fspm_ibecc_params(FSP_M_CONFIG *m_cfg,
 	}
 }
 
-static void fill_fsps_acoustic_params(FSP_M_CONFIG *m_cfg,
+static void fill_fspm_acoustic_params(FSP_M_CONFIG *m_cfg,
 		const struct soc_intel_meteorlake_config *config)
 {
 	if (!config->enable_acoustic_noise_mitigation)
@@ -431,7 +431,7 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg,
 		fill_fspm_trace_params,
 		fill_fspm_vr_config_params,
 		fill_fspm_ibecc_params,
-		fill_fsps_acoustic_params,
+		fill_fspm_acoustic_params,
 	};
 
 	for (size_t i = 0; i < ARRAY_SIZE(fill_fspm_params); i++)

From 4f13f72dbc400004699e8fae83689003597003ac Mon Sep 17 00:00:00 2001
From: Yu-Ping Wu <yupingso@chromium.org>
Date: Fri, 26 Sep 2025 16:37:35 +0800
Subject: [PATCH 2123/3886] libpayload: Define UCHAR_MAX/CHAR_MIN/CHAR_MAX

Change-Id: Id26ef9aaad676d4369864e37afa514fc7f103432
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89358
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
---
 payloads/libpayload/include/limits.h | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/payloads/libpayload/include/limits.h b/payloads/libpayload/include/limits.h
index 53adfcb98c..c712b60bfd 100644
--- a/payloads/libpayload/include/limits.h
+++ b/payloads/libpayload/include/limits.h
@@ -41,6 +41,10 @@
 
 #define CHAR_BIT	8
 
+#define UCHAR_MAX	((unsigned char)~0U)
+#define CHAR_MIN	((char)(UCHAR_MAX & ~(UCHAR_MAX >> 1)))
+#define CHAR_MAX	((char)(UCHAR_MAX >> 1))
+
 #define USHRT_MAX	((unsigned short int)~0U)
 #define SHRT_MIN	((short int)(USHRT_MAX & ~(USHRT_MAX >> 1)))
 #define SHRT_MAX	((short int)(USHRT_MAX >> 1))

From 67a3fb6abef55f41a027222c7808ccb33cbe9817 Mon Sep 17 00:00:00 2001
From: Dodoid <git-noreply@dodoid.com>
Date: Sun, 14 Sep 2025 01:12:04 -0400
Subject: [PATCH 2124/3886] mb/asus: Add PRIME H610i-PLUS D4
 (Alderlake/LGA1700)

This port adds support for the ASUS PRIME H610i-PLUS D4, a Mini-ITX
LGA1700 motherboard with the H610 chipset. I have been using this
port on one of these boards as my primary workstation for around
the last month, and it generally works well apart from a lack of S3
sleep. I have not yet managed to figure out the issue with that,
and have been using suspend-to-disk instead.

This board is highly similar to the H610M-K ported by Mate Kukri in
#84243, and I have included the NCT6798D fan control setup from
that patchset with minimal modification.

Working:
- Console over onboard serial port
- PS/2 keyboard
- Port 80 POST codes over ASUS debug header
- All USB ports, including USB3 working, except front USB2
- All outputs (DP, HDMI, VGA) for iGPU
- M.2 slot
- PCIe WiFi card in WiFi slot
- Onboard Ethernet
- PCIe ASPM and clock power management for all devices
- x16 PCIe slot
- All SATA ports
- Hard drive indicator LED
- All audio including front panel
- Fan control
- ME disable with HAP bit in IFD
- HSPHY-in-FMAP when ME is disabled

Untested:
- CNVi WiFi card in WiFi slot
- Front USB2 ports (did not have an adapter on hand to test)
- Status LEDs in actual error states (they do show a normal status
normally)

Not working:
- S3 sleep

Change-Id: Ib2dd2916be06dc515863df85ecb06ec043a9bc6e
Signed-off-by: Dodoid <git-noreply@dodoid.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89167
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
---
 Documentation/mainboard/asus/h610i-plus-d4.md |  49 +++
 Documentation/mainboard/index.md              |   1 +
 src/mainboard/asus/h610i-plus-d4/Kconfig      |  34 ++
 src/mainboard/asus/h610i-plus-d4/Kconfig.name |   4 +
 src/mainboard/asus/h610i-plus-d4/Makefile.mk  |   5 +
 .../asus/h610i-plus-d4/board_info.txt         |   7 +
 src/mainboard/asus/h610i-plus-d4/bootblock.c  |  62 +++
 src/mainboard/asus/h610i-plus-d4/data.vbt     | Bin 0 -> 8704 bytes
 .../asus/h610i-plus-d4/devicetree.cb          | 191 ++++++++
 src/mainboard/asus/h610i-plus-d4/dsdt.asl     |  25 ++
 src/mainboard/asus/h610i-plus-d4/gpio.h       | 415 ++++++++++++++++++
 src/mainboard/asus/h610i-plus-d4/hda_verb.c   | 163 +++++++
 src/mainboard/asus/h610i-plus-d4/mainboard.c  | 240 ++++++++++
 .../asus/h610i-plus-d4/romstage_fsp_params.c  |  66 +++
 14 files changed, 1262 insertions(+)
 create mode 100644 Documentation/mainboard/asus/h610i-plus-d4.md
 create mode 100644 src/mainboard/asus/h610i-plus-d4/Kconfig
 create mode 100644 src/mainboard/asus/h610i-plus-d4/Kconfig.name
 create mode 100644 src/mainboard/asus/h610i-plus-d4/Makefile.mk
 create mode 100644 src/mainboard/asus/h610i-plus-d4/board_info.txt
 create mode 100644 src/mainboard/asus/h610i-plus-d4/bootblock.c
 create mode 100644 src/mainboard/asus/h610i-plus-d4/data.vbt
 create mode 100644 src/mainboard/asus/h610i-plus-d4/devicetree.cb
 create mode 100644 src/mainboard/asus/h610i-plus-d4/dsdt.asl
 create mode 100644 src/mainboard/asus/h610i-plus-d4/gpio.h
 create mode 100644 src/mainboard/asus/h610i-plus-d4/hda_verb.c
 create mode 100644 src/mainboard/asus/h610i-plus-d4/mainboard.c
 create mode 100644 src/mainboard/asus/h610i-plus-d4/romstage_fsp_params.c

diff --git a/Documentation/mainboard/asus/h610i-plus-d4.md b/Documentation/mainboard/asus/h610i-plus-d4.md
new file mode 100644
index 0000000000..d3467499f6
--- /dev/null
+++ b/Documentation/mainboard/asus/h610i-plus-d4.md
@@ -0,0 +1,49 @@
+# ASUS PRIME H610i-PLUS
+This is a Mini-ITX LGA1700 (Alder Lake/Raptor Lake) motherboard, using the H610 chipset and
+DDR4 RAM. It's a close relative of the H610M-K, and like it is also sold in DDR4 and DDR5
+variants.
+
+## Variants
+- *ASUS PRIME H610i-PLUS **D4***: uses DDR4 RAM, supported
+- *ASUS PRIME H610i-PLUS* (no "D4"): uses DDR5 RAM, not currently supported by this port
+
+## Flashing
+This mainboard uses a standard 3.3V SOIC-8 SPI flash chip. The vendor firmware enables write
+protection, thus for initial installation an external programmer is required. Thereafter,
+coreboot can be updated internally using `flashrom -p internal`.
+
+An external programmer can be connected using an ordinary chip clip, but for development or
+testing, it can be more convenient to flash via the TPM header. A pinout can be found on Page
+1-4 of the board's User's Manual - to select the flash chip, connect your CS line to
+F_SPI_CS0#_R. An adapter cable can be made using a 2x7-pin 2.0mm female header, or a set of
+2.0mm jumper wires. Beware, despite its similar appearance, this TPM header pinout is NOT
+compatible with the pinout found on the MSI Z690A and Z790P boards (adapters for flashing those
+boards over the SPI TPM header will not work on ASUS boards).
+
+## Feature Support
+### Working:
+- Console over onboard serial port
+- PS/2 keyboard
+- Port 80 POST codes over ASUS debug header
+- All USB ports, including USB3 working, except front USB2
+- All outputs (DP, HDMI, VGA) for iGPU
+- M.2 slot
+- PCIe WiFi card in WiFi slot
+- Onboard Ethernet
+- PCIe ASPM and clock power management for all devices
+- x16 PCIe slot
+- All SATA ports
+- Hard drive indicator LED
+- All audio including front panel
+- Fan control
+- ME disable with HAP bit in IFD
+- HSPHY-in-FMAP when ME is disabled
+
+### Untested:
+- CNVi WiFi card in WiFi slot
+- SPI TPM
+- Front USB2 ports (did not have an adapter on hand to test)
+- Status LEDs in actual error states (they do show a normal status normally)
+
+### Not working:
+- S3 sleep
\ No newline at end of file
diff --git a/Documentation/mainboard/index.md b/Documentation/mainboard/index.md
index 7412bc0f1d..d4fbddace5 100644
--- a/Documentation/mainboard/index.md
+++ b/Documentation/mainboard/index.md
@@ -43,6 +43,7 @@ IMB-1222 <asrock/imb-1222.md>
 
 A88XM-E <asus/a88xm-e.md>
 F2A85-M <asus/f2a85-m.md>
+H610i-PLUS D4 <asus/h610i-plus-d4>
 P2B-LS <asus/p2b-ls.md>
 P3B-F <asus/p3b-f.md>
 P5Q <asus/p5q.md>
diff --git a/src/mainboard/asus/h610i-plus-d4/Kconfig b/src/mainboard/asus/h610i-plus-d4/Kconfig
new file mode 100644
index 0000000000..e4f7598066
--- /dev/null
+++ b/src/mainboard/asus/h610i-plus-d4/Kconfig
@@ -0,0 +1,34 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
+config BOARD_ASUS_H610I_PLUS_D4
+	select BOARD_ROMSIZE_KB_16384
+	select DRIVERS_UART_8250IO
+	select HAVE_ACPI_RESUME
+	select HAVE_ACPI_TABLES
+	select INTEL_GMA_HAVE_VBT
+	select SOC_INTEL_ALDERLAKE_PCH_S
+	select SOC_INTEL_COMMON_BLOCK_HDA_VERB
+	select SUPERIO_NUVOTON_NCT6791D
+	select USE_LEGACY_8254_TIMER
+
+if BOARD_ASUS_H610I_PLUS_D4
+
+config MAINBOARD_DIR
+	default "asus/h610i-plus-d4"
+
+config MAINBOARD_PART_NUMBER
+	default "PRIME H610I-PLUS D4"
+
+config MAINBOARD_VENDOR
+	default "ASUS"
+
+config UART_FOR_CONSOLE
+	default 0
+
+config USE_PM_ACPI_TIMER
+	default n
+
+config CBFS_SIZE
+	default 0xB00000
+
+endif
diff --git a/src/mainboard/asus/h610i-plus-d4/Kconfig.name b/src/mainboard/asus/h610i-plus-d4/Kconfig.name
new file mode 100644
index 0000000000..b07cc83676
--- /dev/null
+++ b/src/mainboard/asus/h610i-plus-d4/Kconfig.name
@@ -0,0 +1,4 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
+config BOARD_ASUS_H610I_PLUS_D4
+	bool "PRIME H610I-PLUS D4"
diff --git a/src/mainboard/asus/h610i-plus-d4/Makefile.mk b/src/mainboard/asus/h610i-plus-d4/Makefile.mk
new file mode 100644
index 0000000000..9ac5be5afe
--- /dev/null
+++ b/src/mainboard/asus/h610i-plus-d4/Makefile.mk
@@ -0,0 +1,5 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
+bootblock-y += bootblock.c
+romstage-y += romstage_fsp_params.c
+ramstage-y += mainboard.c
diff --git a/src/mainboard/asus/h610i-plus-d4/board_info.txt b/src/mainboard/asus/h610i-plus-d4/board_info.txt
new file mode 100644
index 0000000000..27ce2a69b1
--- /dev/null
+++ b/src/mainboard/asus/h610i-plus-d4/board_info.txt
@@ -0,0 +1,7 @@
+Category: desktop
+Board URL: https://www.asus.com/us/motherboards-components/motherboards/prime/prime-h610i-plus-d4/
+ROM IC: W25Q128JVSQ
+ROM package: SOIC-8
+ROM socketed: no
+Flashrom support: yes
+Release year: 2022
diff --git a/src/mainboard/asus/h610i-plus-d4/bootblock.c b/src/mainboard/asus/h610i-plus-d4/bootblock.c
new file mode 100644
index 0000000000..0c723c17eb
--- /dev/null
+++ b/src/mainboard/asus/h610i-plus-d4/bootblock.c
@@ -0,0 +1,62 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <bootblock_common.h>
+#include <device/pnp_ops.h>
+#include <superio/nuvoton/common/nuvoton.h>
+
+// This board actually uses an NCT6798D, but NCT6791D seems compatible
+#include <superio/nuvoton/nct6791d/nct6791d.h>
+
+#define SERIAL_DEV PNP_DEV(0x2e, NCT6791D_SP1)
+#define P80_UART_DEV PNP_DEV(0x2e, NCT6791D_PORT80)
+#define ACPI_DEV PNP_DEV(0x2e, NCT6791D_ACPI)
+#define WDTMEM_DEV PNP_DEV(0x2e, NCT6791D_BCLK_WDT2_WDTMEM)
+#define CIRWUP_DEV PNP_DEV(0x2e, NCT6791D_CIRWUP)
+#define DS_DEV PNP_DEV(0x2e, NCT6791D_DS)
+
+void bootblock_mainboard_early_init(void)
+{
+	// Start configuring the SIO
+	nuvoton_pnp_enter_conf_state(P80_UART_DEV);
+
+	// Replicate vendor global config LDN
+	pnp_write_config(P80_UART_DEV, 0x07, 0x0b);
+	pnp_write_config(P80_UART_DEV, 0x10, 0xcf);
+	pnp_write_config(P80_UART_DEV, 0x11, 0xc3);
+	pnp_write_config(P80_UART_DEV, 0x13, 0x0c);
+	pnp_write_config(P80_UART_DEV, 0x14, 0xb8);
+	pnp_write_config(P80_UART_DEV, 0x1a, 0x10);
+	pnp_write_config(P80_UART_DEV, 0x1b, 0x00);
+	pnp_write_config(P80_UART_DEV, 0x1c, 0x10);
+	pnp_write_config(P80_UART_DEV, 0x24, 0x00);
+	pnp_write_config(P80_UART_DEV, 0x27, 0x00);
+	pnp_write_config(P80_UART_DEV, 0x2a, 0x58);
+	pnp_write_config(P80_UART_DEV, 0x2b, 0x02); // Enable the Port 80 UART
+	pnp_write_config(P80_UART_DEV, 0x2c, 0x0a);
+	pnp_write_config(P80_UART_DEV, 0x2d, 0x30);
+
+	// Configure the ACPI LD to match stock
+	pnp_set_logical_device(ACPI_DEV);
+	pnp_write_config(ACPI_DEV, 0xe5, 0x02);
+	pnp_write_config(ACPI_DEV, 0xe6, 0x1a);
+	pnp_write_config(ACPI_DEV, 0xf2, 0x5d);
+
+	// Configure BCLK/WDT2/WDTMEM
+	pnp_set_logical_device(WDTMEM_DEV);
+	pnp_write_config(WDTMEM_DEV, 0xe2, 0x03);
+	pnp_write_config(WDTMEM_DEV, 0xf0, 0x80);
+
+	// Configure CIR Wakeup
+	pnp_set_logical_device(CIRWUP_DEV);
+	pnp_write_config(CIRWUP_DEV, 0x30, 0x00);
+
+	// Configure Deep Sleep
+	pnp_set_logical_device(DS_DEV);
+	pnp_write_config(DS_DEV, 0x30, 0xa0); // Disable deep S5
+
+	nuvoton_pnp_exit_conf_state(ACPI_DEV);
+
+	// Enable serial port
+	if (CONFIG(CONSOLE_SERIAL))
+		nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
+}
diff --git a/src/mainboard/asus/h610i-plus-d4/data.vbt b/src/mainboard/asus/h610i-plus-d4/data.vbt
new file mode 100644
index 0000000000000000000000000000000000000000..f9992e2b335509f7b648d61393e15ac7a29607f4
GIT binary patch
literal 8704
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literal 0
HcmV?d00001

diff --git a/src/mainboard/asus/h610i-plus-d4/devicetree.cb b/src/mainboard/asus/h610i-plus-d4/devicetree.cb
new file mode 100644
index 0000000000..8a7fd7390e
--- /dev/null
+++ b/src/mainboard/asus/h610i-plus-d4/devicetree.cb
@@ -0,0 +1,191 @@
+chip soc/intel/alderlake
+	register "eist_enable" = "true"
+
+	# Sagv Configuration
+	register "sagv" = "SaGv_Enabled"
+	register "RMT" = "0"
+	register "enable_c6dram" = "1"
+
+	register "pmc_gpe0_dw0" = "GPP_J"
+	register "pmc_gpe0_dw1" = "GPP_VPGIO"
+	register "pmc_gpe0_dw2" = "GPD"
+
+	device domain 0 on
+		# USB Configuration - copied from ms7d25, all ports work but possibly excessive
+		device ref xhci on
+			register "usb2_ports" = "{
+				[0] = USB2_PORT_SHORT(OC2),
+				[1] = USB2_PORT_SHORT(OC1),
+				[2] = USB2_PORT_SHORT(OC0),
+				[3] = USB2_PORT_LONG(OC0),
+				[4] = USB2_PORT_SHORT(OC3),
+				[5] = USB2_PORT_LONG(OC3),
+				[6] = USB2_PORT_LONG(OC7),
+				[7] = USB2_PORT_LONG(OC0),
+				[8] = USB2_PORT_LONG(OC2),
+				[9] = USB2_PORT_LONG(OC7),
+				[10] = USB2_PORT_SHORT(OC0),
+				[11] = USB2_PORT_SHORT(OC0),
+				[12] = USB2_PORT_SHORT(OC0),
+				[13] = USB2_PORT_SHORT(OC0),
+				[14] = USB2_PORT_EMPTY,
+				[15] = USB2_PORT_EMPTY,
+			}"
+
+			register "usb3_ports" = "{
+				[0] = USB3_PORT_DEFAULT(OC2),
+				[1] = USB3_PORT_DEFAULT(OC2),
+				[2] = USB3_PORT_DEFAULT(OC3),
+				[3] = USB3_PORT_DEFAULT(OC0),
+				[4] = USB3_PORT_DEFAULT(OC7),
+				[5] = USB3_PORT_DEFAULT(OC7),
+				[6] = USB3_PORT_DEFAULT(OC2),
+				[7] = USB3_PORT_DEFAULT(OC2),
+				[8] = USB3_PORT_DEFAULT(OC0),
+				[9] = USB3_PORT_EMPTY,
+			}"
+		end
+
+		device ref sata on
+			register "sata_salp_support" = "1"
+
+			register "sata_ports_enable" = "{
+				[4] = 1,
+				[5] = 1,
+				[6] = 1,
+				[7] = 1,
+			}"
+
+			register "sata_ports_dev_slp" = "{
+				[4] = 0,
+				[5] = 0,
+				[6] = 0,
+				[7] = 0,
+			}"
+		end
+
+		# HDMI on port B
+		register "ddi_portB_config" = "1"
+		register "ddi_ports_config" = "{
+			[DDI_PORT_B] = DDI_ENABLE_HPD | DDI_ENABLE_DDC,
+			[DDI_PORT_C] = DDI_ENABLE_HPD | DDI_ENABLE_DDC,
+			[DDI_PORT_1] = DDI_ENABLE_HPD | DDI_ENABLE_DDC,
+			[DDI_PORT_2] = DDI_ENABLE_HPD,
+			[DDI_PORT_3] = DDI_ENABLE_HPD | DDI_ENABLE_DDC,
+			[DDI_PORT_4] = DDI_ENABLE_HPD,
+		}"
+
+		register "hybrid_storage_mode" = "true"
+		register "dmi_power_optimize_disable" = "true"
+
+		# FIVR configuration
+		register "fivr_rfi_frequency" = "1394"
+		register "fivr_spread_spectrum" = "FIVR_SS_1_5"
+		register "ext_fivr_settings" = "{
+			.configure_ext_fivr = 1,
+		}"
+
+		# PCIe x16 Slot
+		# PEG10 (dGPU)
+		device ref pcie5_0 on
+			register "cpu_pcie_rp[CPU_RP(2)]" = "{
+				.clk_src = 0,
+				.clk_req = 0,
+				.flags = PCIE_RP_LTR | PCIE_RP_AER,
+			}"
+			smbios_slot_desc "SlotTypePciExpressGen4x16" "SlotLengthLong"
+					 "PCI_E1" "SlotDataBusWidth16X"
+		end
+
+		device ref igpu on end
+
+		device ref crashlog off end
+
+		device ref cnvi_wifi on
+			# Enable CNVi BT
+			register "cnvi_bt_core" = "true"
+			register "cnvi_bt_audio_offload" = "false"
+			chip drivers/wifi/generic
+				register "wake" = "GPE0_PME_B0"
+				register "enable_cnvi_ddr_rfim" = "true"
+				device generic 0 on end
+			end
+		end
+
+		# HECI to ME
+		device ref heci1 on end
+
+		# M.2 Slot
+		device ref pcie_rp1 on
+			register "pch_pcie_rp[PCH_RP(1)]" = "{
+				.clk_src = 11,
+				.clk_req = 11,
+				.flags = PCIE_RP_LTR | PCIE_RP_AER,
+			}"
+			smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther"
+					 "M2_1" "SlotDataBusWidth4X"
+		end
+
+		# Onboard LAN
+		device ref pcie_rp5 on
+			register "pch_pcie_rp[PCH_RP(5)]" = "{
+				.clk_src = 4,
+				.clk_req = 4,
+				.flags = PCIE_RP_LTR | PCIE_RP_AER,
+			}"
+		end
+
+		# WLAN (when not using CNVi)
+		device ref pcie_rp6 on
+			register "pch_pcie_rp[PCH_RP(6)]" = "{
+				.clk_src = 12,
+				.clk_req = 12,
+				.flags = PCIE_RP_LTR | PCIE_RP_AER,
+			}"
+			smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther"
+					 "M2_1" "SlotDataBusWidth4X"
+		end
+
+		device ref pch_espi on
+			# HWM I/O decode range
+			register "gen1_dec" = "0x007c0281"
+
+			chip superio/nuvoton/nct6791d
+				device pnp 2e.1   off end # Parallel port (this line needed for super i/o init to work)
+				device pnp 2e.2   on      # UART A
+					io  0x60 = 0x03f8
+					irq 0x70 = 4
+
+					# Pin 121 is PECI
+					irq 0x2c = 0
+				end
+				device pnp 2e.5   on      # PS/2 KBC
+					io  0x60 = 0x0060
+					io  0x62 = 0x0064
+					irq 0x70 = 1
+					irq 0x72 = 12
+					irq 0xf0 = 0x82
+				end
+				device pnp 2e.b   on      # HWM
+					io  0x60 = 0x0290
+					io  0x62 = 0x0b00
+					io  0x64 = 0x0a00
+					irq 0xf0 = 0xfe
+				end
+			end
+		end
+
+		device ref p2sb on end
+
+		device ref hda on
+			register "pch_hda_audio_link_hda_enable" = "1"
+			register "pch_hda_sdi_enable[0]" = "1"
+			register "pch_hda_dsp_enable" = "0"
+			register "pch_hda_idisp_link_tmode" = "HDA_TMODE_8T"
+			register "pch_hda_idisp_link_frequency" = "HDA_LINKFREQ_96MHZ"
+			register "pch_hda_idisp_codec_enable" = "1"
+		end
+
+		device ref smbus on end
+	end
+end
diff --git a/src/mainboard/asus/h610i-plus-d4/dsdt.asl b/src/mainboard/asus/h610i-plus-d4/dsdt.asl
new file mode 100644
index 0000000000..e612ec09de
--- /dev/null
+++ b/src/mainboard/asus/h610i-plus-d4/dsdt.asl
@@ -0,0 +1,25 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <acpi/acpi.h>
+
+DefinitionBlock(
+	"dsdt.aml",
+	"DSDT",
+	ACPI_DSDT_REV_2,
+	OEM_ID,
+	ACPI_TABLE_CREATOR,
+	0x20110725
+)
+{
+	#include <acpi/dsdt_top.asl>
+	#include <soc/intel/common/block/acpi/acpi/platform.asl>
+	#include <soc/intel/common/block/acpi/acpi/globalnvs.asl>
+	#include <cpu/intel/common/acpi/cpu.asl>
+
+	Device (\_SB.PCI0) {
+		#include <soc/intel/common/block/acpi/acpi/northbridge.asl>
+		#include <soc/intel/alderlake/acpi/southbridge.asl>
+	}
+
+	#include <southbridge/intel/common/acpi/sleepstates.asl>
+}
diff --git a/src/mainboard/asus/h610i-plus-d4/gpio.h b/src/mainboard/asus/h610i-plus-d4/gpio.h
new file mode 100644
index 0000000000..c8aca70baa
--- /dev/null
+++ b/src/mainboard/asus/h610i-plus-d4/gpio.h
@@ -0,0 +1,415 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef CFG_GPIO_H
+#define CFG_GPIO_H
+
+#include <gpio.h>
+
+/* Pad configuration was generated automatically using intelp2m 2.5-149f0c750c */
+static const struct pad_config gpio_table[] = {
+	/* ------- GPIO Community 0 ------- */
+
+	/* ------- GPIO Group GPP_I ------- */
+	PAD_CFG_GPI_TRIG_OWN(GPP_I0, NONE, PLTRST, OFF, ACPI),
+	_PAD_CFG_STRUCT(GPP_I1, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0),
+	_PAD_CFG_STRUCT(GPP_I2, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), 0),
+	_PAD_CFG_STRUCT(GPP_I3, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), 0),
+	_PAD_CFG_STRUCT(GPP_I4, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), 0),
+	PAD_CFG_GPI_TRIG_OWN(GPP_I5, NONE, PLTRST, OFF, ACPI),
+	PAD_CFG_GPI_TRIG_OWN(GPP_I6, NONE, PLTRST, OFF, ACPI),
+	PAD_CFG_GPI_TRIG_OWN(GPP_I7, NONE, PLTRST, OFF, ACPI),
+	PAD_CFG_GPI_TRIG_OWN(GPP_I8, NONE, PLTRST, OFF, ACPI),
+	PAD_CFG_GPI_TRIG_OWN(GPP_I9, NONE, PLTRST, OFF, ACPI),
+	PAD_CFG_GPI_TRIG_OWN(GPP_I10, NONE, PLTRST, OFF, ACPI),
+	_PAD_CFG_STRUCT(GPP_I11, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0),
+	_PAD_CFG_STRUCT(GPP_I12, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0),
+	_PAD_CFG_STRUCT(GPP_I13, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0),
+	_PAD_CFG_STRUCT(GPP_I14, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0),
+	PAD_CFG_GPI_TRIG_OWN(GPP_I15, NONE, PLTRST, OFF, ACPI),
+	PAD_CFG_GPI_TRIG_OWN(GPP_I16, NONE, PLTRST, OFF, ACPI),
+	PAD_CFG_GPI_TRIG_OWN(GPP_I17, NONE, PLTRST, OFF, ACPI),
+	PAD_CFG_GPI_TRIG_OWN(GPP_I18, NONE, PLTRST, OFF, ACPI),
+	PAD_CFG_GPI_TRIG_OWN(GPP_I19, NONE, RSMRST, OFF, ACPI),
+	PAD_CFG_GPI_TRIG_OWN(GPP_I20, NONE, RSMRST, OFF, ACPI),
+	PAD_CFG_GPI_TRIG_OWN(GPP_I21, NONE, RSMRST, OFF, ACPI),
+	PAD_CFG_GPI_TRIG_OWN(GPP_I22, NONE, PLTRST, OFF, ACPI),
+
+	/* ------- GPIO Group GPP_R ------- */
+	_PAD_CFG_STRUCT(GPP_R0, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
+	_PAD_CFG_STRUCT(GPP_R1, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
+	_PAD_CFG_STRUCT(GPP_R2, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
+	_PAD_CFG_STRUCT(GPP_R3, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
+	_PAD_CFG_STRUCT(GPP_R4, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
+	PAD_CFG_GPI_TRIG_OWN(GPP_R5, NONE, PLTRST, OFF, ACPI),
+	PAD_CFG_GPI_TRIG_OWN(GPP_R6, NONE, PLTRST, OFF, ACPI),
+	PAD_CFG_GPI_TRIG_OWN(GPP_R7, NONE, PLTRST, OFF, ACPI),
+	PAD_CFG_GPI_TRIG_OWN(GPP_R8, NONE, PLTRST, OFF, ACPI),
+	PAD_CFG_GPI_TRIG_OWN(GPP_R9, NONE, PLTRST, OFF, ACPI),
+	PAD_CFG_GPI_TRIG_OWN(GPP_R10, NONE, PLTRST, OFF, ACPI),
+	PAD_CFG_GPI_TRIG_OWN(GPP_R11, NONE, PLTRST, OFF, ACPI),
+	PAD_CFG_GPI_TRIG_OWN(GPP_R12, NONE, PLTRST, OFF, ACPI),
+	PAD_CFG_GPI_TRIG_OWN(GPP_R13, NONE, PLTRST, OFF, ACPI),
+	PAD_CFG_GPI_TRIG_OWN(GPP_R14, NONE, PLTRST, OFF, ACPI),
+	PAD_CFG_GPI_TRIG_OWN(GPP_R15, NONE, PLTRST, OFF, ACPI),
+	_PAD_CFG_STRUCT(GPP_R16, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF), 0),
+	_PAD_CFG_STRUCT(GPP_R17, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | (1 << 1), 0),
+	_PAD_CFG_STRUCT(GPP_R18, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF), 0),
+	_PAD_CFG_STRUCT(GPP_R19, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | (1 << 1), 0),
+	PAD_CFG_GPI_TRIG_OWN(GPP_R20, NONE, PLTRST, OFF, ACPI),
+	PAD_CFG_GPI_TRIG_OWN(GPP_R21, NONE, PLTRST, OFF, ACPI),
+
+	/* ------- GPIO Group GPP_J ------- */
+	PAD_CFG_GPI_TRIG_OWN(GPP_J0, NONE, RSMRST, OFF, ACPI),
+	_PAD_CFG_STRUCT(GPP_J1, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), 0),
+	_PAD_CFG_STRUCT(GPP_J2, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
+	_PAD_CFG_STRUCT(GPP_J3, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0),
+	_PAD_CFG_STRUCT(GPP_J4, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
+	_PAD_CFG_STRUCT(GPP_J5, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0),
+	PAD_CFG_GPI_TRIG_OWN(GPP_J6, NONE, PLTRST, OFF, ACPI),
+	PAD_CFG_GPO(GPP_J7, 0, PLTRST),
+	PAD_CFG_GPI_TRIG_OWN(GPP_J8, NONE, PLTRST, OFF, ACPI),
+	PAD_CFG_GPI_TRIG_OWN(GPP_J9, NONE, PLTRST, OFF, ACPI),
+	PAD_CFG_GPI_TRIG_OWN(GPP_J10, NONE, PLTRST, OFF, ACPI),
+	PAD_CFG_GPI_TRIG_OWN(GPP_J11, NONE, PLTRST, OFF, ACPI),
+
+	/* ------- GPIO Group vGPIO ------- */
+
+	/* ------- GPIO Group vGPIO_0 ------- */
+
+	/* ------- GPIO Community 1 ------- */
+
+	/* ------- GPIO Group GPP_B ------- */
+	PAD_CFG_GPI_TRIG_OWN(GPP_B0, NONE, PLTRST, OFF, ACPI),
+	PAD_CFG_GPI_TRIG_OWN(GPP_B1, NONE, PLTRST, OFF, ACPI),
+	_PAD_CFG_STRUCT(GPP_B2, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0),
+	PAD_CFG_GPO(GPP_B3, 1, PLTRST),
+	PAD_CFG_GPI_TRIG_OWN(GPP_B4, NONE, PLTRST, OFF, ACPI),
+	_PAD_CFG_STRUCT(GPP_B5, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0),
+	PAD_CFG_GPI_TRIG_OWN(GPP_B6, NONE, PLTRST, OFF, ACPI),
+	_PAD_CFG_STRUCT(GPP_B7, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0),
+	PAD_CFG_GPI_TRIG_OWN(GPP_B8, NONE, PLTRST, OFF, ACPI),
+	PAD_CFG_GPI_TRIG_OWN(GPP_B9, NONE, PLTRST, OFF, ACPI),
+	PAD_CFG_GPI_TRIG_OWN(GPP_B10, NONE, PLTRST, OFF, ACPI),
+	PAD_CFG_GPI_TRIG_OWN(GPP_B11, NONE, PLTRST, OFF, ACPI),
+	_PAD_CFG_STRUCT(GPP_B12, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0),
+	_PAD_CFG_STRUCT(GPP_B13, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
+	_PAD_CFG_STRUCT(GPP_B14, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), PAD_PULL(DN_20K)),
+	PAD_CFG_GPI_TRIG_OWN(GPP_B15, NONE, PLTRST, OFF, ACPI),
+	PAD_CFG_GPI_TRIG_OWN(GPP_B16, NONE, PLTRST, OFF, ACPI),
+	PAD_CFG_GPI_TRIG_OWN(GPP_B17, NONE, PLTRST, OFF, ACPI),
+	_PAD_CFG_STRUCT(GPP_B18, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), PAD_PULL(UP_20K)),
+	_PAD_CFG_STRUCT(GPP_B19, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0),
+	PAD_CFG_GPO(GPP_B20, 0, PLTRST),
+	_PAD_CFG_STRUCT(GPP_B21, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | 1, 0),
+	PAD_CFG_GPO(GPP_B22, 0, PLTRST),
+	_PAD_CFG_STRUCT(GPP_B23, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0),
+
+	/* ------- GPIO Group GPP_G ------- */
+	PAD_CFG_GPI_TRIG_OWN(GPP_G0, NONE, PLTRST, OFF, ACPI),
+	_PAD_CFG_STRUCT(GPP_G1, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | 1, 0),
+	PAD_CFG_GPI_TRIG_OWN(GPP_G2, NONE, PLTRST, OFF, ACPI),
+	PAD_CFG_GPI_TRIG_OWN(GPP_G3, NONE, PLTRST, OFF, ACPI),
+	PAD_CFG_GPI_TRIG_OWN(GPP_G4, NONE, PLTRST, OFF, ACPI),
+	PAD_CFG_GPI_TRIG_OWN(GPP_G5, NONE, PLTRST, OFF, ACPI),
+	_PAD_CFG_STRUCT(GPP_G6, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0),
+	PAD_CFG_GPI_TRIG_OWN(GPP_G7, NONE, PLTRST, OFF, ACPI),
+
+	/* ------- GPIO Group GPP_H ------- */
+	PAD_CFG_GPI_TRIG_OWN(GPP_H0, NONE, PLTRST, OFF, ACPI),
+	PAD_CFG_GPI_TRIG_OWN(GPP_H1, NONE, PLTRST, OFF, ACPI),
+	PAD_CFG_GPI_TRIG_OWN(GPP_H2, NONE, PLTRST, OFF, ACPI),
+	PAD_CFG_GPI_TRIG_OWN(GPP_H3, NONE, PLTRST, OFF, ACPI),
+	PAD_CFG_GPI_TRIG_OWN(GPP_H4, NONE, PLTRST, OFF, ACPI),
+	_PAD_CFG_STRUCT(GPP_H5, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
+	_PAD_CFG_STRUCT(GPP_H6, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
+	PAD_CFG_GPI_TRIG_OWN(GPP_H7, NONE, PLTRST, OFF, ACPI),
+	PAD_CFG_GPI_TRIG_OWN(GPP_H8, NONE, PLTRST, OFF, ACPI),
+	PAD_CFG_GPI_TRIG_OWN(GPP_H9, NONE, PLTRST, OFF, ACPI),
+	PAD_CFG_GPI_TRIG_OWN(GPP_H10, NONE, PLTRST, OFF, ACPI),
+	_PAD_CFG_STRUCT(GPP_H11, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1) | 1, 0),
+	PAD_CFG_GPI_TRIG_OWN(GPP_H12, NONE, PLTRST, OFF, ACPI),
+	PAD_CFG_GPI_TRIG_OWN(GPP_H13, NONE, PLTRST, OFF, ACPI),
+	PAD_CFG_GPI_TRIG_OWN(GPP_H14, NONE, PLTRST, OFF, ACPI),
+	PAD_CFG_GPI_TRIG_OWN(GPP_H15, NONE, PLTRST, OFF, ACPI),
+	_PAD_CFG_STRUCT(GPP_H16, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | 1, 0),
+	PAD_CFG_GPI_TRIG_OWN(GPP_H17, NONE, PLTRST, OFF, ACPI),
+	PAD_CFG_GPI_TRIG_OWN(GPP_H18, NONE, PLTRST, OFF, ACPI),
+	PAD_CFG_GPI_TRIG_OWN(GPP_H19, NONE, RSMRST, OFF, ACPI),
+	PAD_CFG_GPI_TRIG_OWN(GPP_H20, NONE, RSMRST, OFF, ACPI),
+	PAD_CFG_GPI_TRIG_OWN(GPP_H21, NONE, RSMRST, OFF, ACPI),
+	PAD_CFG_GPI_TRIG_OWN(GPP_H22, NONE, PLTRST, OFF, ACPI),
+	PAD_CFG_GPI_TRIG_OWN(GPP_H23, NONE, PLTRST, OFF, ACPI),
+
+	/* ------- GPIO Community 2 ------- */
+
+	/* ------- GPIO Group GPD ------- */
+	PAD_CFG_GPI_TRIG_OWN(GPD0, NONE, PWROK, OFF, ACPI),	/* GPIO */
+	PAD_CFG_GPI_TRIG_OWN(GPD1, NONE, PWROK, OFF, ACPI),	/* GPIO */
+	PAD_CFG_NF(GPD2, NONE, PWROK, NF1),	/* LAN_WAKE# */
+	PAD_CFG_NF(GPD3, NONE, PWROK, NF1),	/* PWRBTN# */
+	PAD_CFG_NF(GPD4, NONE, PWROK, NF1),	/* SLP_S3# */
+	PAD_CFG_NF(GPD5, NONE, PWROK, NF1),	/* SLP_S4# */
+	PAD_CFG_GPI_TRIG_OWN(GPD6, NONE, PWROK, OFF, ACPI),	/* GPIO */
+	PAD_CFG_GPI_TRIG_OWN(GPD7, NONE, PWROK, OFF, ACPI),	/* GPIO */
+	PAD_CFG_NF(GPD8, NONE, PWROK, NF1),	/* SUSCLK */
+	PAD_CFG_GPI_TRIG_OWN(GPD9, NONE, PWROK, OFF, ACPI),	/* GPIO */
+	PAD_CFG_GPO(GPD10, 0, PWROK),	/* GPIO */
+	PAD_CFG_GPO(GPD11, 0, PWROK),	/* GPIO */
+	PAD_CFG_GPI_TRIG_OWN(GPD12, NONE, PWROK, OFF, ACPI),	/* GPIO */
+
+	/* ------- GPIO Community 3 ------- */
+
+	/* ------- GPIO Group SPI ------- */
+
+	/* ------- GPIO Group GPP_A ------- */
+	_PAD_CFG_STRUCT(GPP_A0, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(UP_20K)),
+	_PAD_CFG_STRUCT(GPP_A1, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), PAD_PULL(UP_20K)),
+	_PAD_CFG_STRUCT(GPP_A2, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(UP_20K)),
+	_PAD_CFG_STRUCT(GPP_A3, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(UP_20K)),
+	_PAD_CFG_STRUCT(GPP_A4, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(UP_20K)),
+	_PAD_CFG_STRUCT(GPP_A5, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(DN_20K)),
+	_PAD_CFG_STRUCT(GPP_A6, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
+	PAD_CFG_GPI_TRIG_OWN(GPP_A7, NONE, PLTRST, OFF, ACPI),
+	PAD_CFG_GPI_TRIG_OWN(GPP_A8, NONE, PLTRST, OFF, ACPI),
+	PAD_CFG_GPI_TRIG_OWN(GPP_A9, NONE, PLTRST, OFF, ACPI),
+	_PAD_CFG_STRUCT(GPP_A10, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), PAD_PULL(UP_20K)),
+	PAD_CFG_GPI_TRIG_OWN(GPP_A11, NONE, PLTRST, OFF, ACPI),
+	PAD_CFG_GPI_TRIG_OWN(GPP_A12, NONE, PLTRST, OFF, ACPI),
+	PAD_CFG_GPI_TRIG_OWN(GPP_A13, NONE, PLTRST, OFF, ACPI),
+	PAD_CFG_GPI_TRIG_OWN(GPP_A14, NONE, PLTRST, OFF, ACPI),
+
+	/* ------- GPIO Group GPP_C ------- */
+	_PAD_CFG_STRUCT(GPP_C0, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0),
+	_PAD_CFG_STRUCT(GPP_C1, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0),
+	_PAD_CFG_STRUCT(GPP_C2, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1) | 1, 0),
+	PAD_CFG_GPI_TRIG_OWN(GPP_C3, NONE, PLTRST, OFF, ACPI),
+	PAD_CFG_GPI_TRIG_OWN(GPP_C4, NONE, PLTRST, OFF, ACPI),
+	_PAD_CFG_STRUCT(GPP_C5, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), 0),
+	PAD_CFG_GPO(GPP_C6, 0, PLTRST),
+	PAD_CFG_GPI_TRIG_OWN(GPP_C7, NONE, PLTRST, OFF, ACPI),
+	_PAD_CFG_STRUCT(GPP_C8, PAD_FUNC(GPIO) | PAD_RESET(RSMRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0),
+	PAD_CFG_GPI_TRIG_OWN(GPP_C9, NONE, PLTRST, OFF, ACPI),
+	PAD_CFG_GPI_TRIG_OWN(GPP_C10, NONE, RSMRST, OFF, ACPI),
+	PAD_CFG_GPI_TRIG_OWN(GPP_C11, NONE, PLTRST, OFF, ACPI),
+	PAD_CFG_GPI_TRIG_OWN(GPP_C12, NONE, RSMRST, OFF, ACPI),
+	PAD_CFG_GPI_TRIG_OWN(GPP_C13, NONE, PLTRST, OFF, ACPI),
+	_PAD_CFG_STRUCT(GPP_C14, PAD_FUNC(GPIO) | PAD_RESET(RSMRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0),
+	PAD_CFG_GPI_TRIG_OWN(GPP_C15, NONE, PLTRST, OFF, ACPI),
+	_PAD_CFG_STRUCT(GPP_C16, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), 0),
+	_PAD_CFG_STRUCT(GPP_C17, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), 0),
+	PAD_CFG_GPI_TRIG_OWN(GPP_C18, NONE, PLTRST, OFF, ACPI),
+	PAD_CFG_GPI_TRIG_OWN(GPP_C19, NONE, PLTRST, OFF, ACPI),
+	PAD_CFG_GPI_TRIG_OWN(GPP_C20, NONE, PLTRST, OFF, ACPI),
+	PAD_CFG_GPI_TRIG_OWN(GPP_C21, NONE, PLTRST, OFF, ACPI),
+	PAD_CFG_GPI_TRIG_OWN(GPP_C22, NONE, PLTRST, OFF, ACPI),
+	PAD_CFG_GPI_TRIG_OWN(GPP_C23, NONE, PLTRST, OFF, ACPI),
+
+	/* ------- GPIO Group vGPIO_3 ------- */
+
+	/* ------- GPIO Community 4 ------- */
+
+	/* ------- GPIO Group GPP_S ------- */
+	PAD_CFG_GPI_TRIG_OWN(GPP_S0, NONE, PLTRST, OFF, ACPI),
+	PAD_CFG_GPI_TRIG_OWN(GPP_S1, NONE, PLTRST, OFF, ACPI),
+	PAD_CFG_GPI_TRIG_OWN(GPP_S2, NONE, PLTRST, OFF, ACPI),
+	PAD_CFG_GPI_TRIG_OWN(GPP_S3, NONE, PLTRST, OFF, ACPI),
+	PAD_CFG_GPI_TRIG_OWN(GPP_S4, NONE, PLTRST, OFF, ACPI),
+	PAD_CFG_GPI_TRIG_OWN(GPP_S5, NONE, PLTRST, OFF, ACPI),
+	PAD_CFG_GPI_TRIG_OWN(GPP_S6, NONE, PLTRST, OFF, ACPI),
+	PAD_CFG_GPI_TRIG_OWN(GPP_S7, NONE, PLTRST, OFF, ACPI),
+
+	/* ------- GPIO Group GPP_E ------- */
+	_PAD_CFG_STRUCT(GPP_E0, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1) | 1, 0),
+	_PAD_CFG_STRUCT(GPP_E1, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | 1, 0),
+	PAD_CFG_GPI_TRIG_OWN(GPP_E2, NONE, PLTRST, OFF, ACPI),
+	PAD_NC(GPP_E3, NONE),
+	_PAD_CFG_STRUCT(GPP_E4, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), 0),
+	PAD_CFG_GPI_TRIG_OWN(GPP_E5, NONE, PLTRST, OFF, ACPI),
+	PAD_CFG_GPI_TRIG_OWN(GPP_E6, NONE, PLTRST, OFF, ACPI),
+	PAD_CFG_GPI_TRIG_OWN(GPP_E7, NONE, PLTRST, OFF, ACPI),
+	_PAD_CFG_STRUCT(GPP_E8, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), 0),
+	_PAD_CFG_STRUCT(GPP_E9, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0),
+	_PAD_CFG_STRUCT(GPP_E10, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0),
+	_PAD_CFG_STRUCT(GPP_E11, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0),
+	_PAD_CFG_STRUCT(GPP_E12, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0),
+	PAD_CFG_GPI_TRIG_OWN(GPP_E13, NONE, PLTRST, OFF, ACPI),
+	PAD_CFG_GPI_TRIG_OWN(GPP_E14, NONE, PLTRST, OFF, ACPI),
+	PAD_CFG_GPI_TRIG_OWN(GPP_E15, NONE, PLTRST, OFF, ACPI),
+	PAD_CFG_GPI_TRIG_OWN(GPP_E16, NONE, PLTRST, OFF, ACPI),
+	PAD_CFG_GPI_TRIG_OWN(GPP_E17, NONE, PLTRST, OFF, ACPI),
+	PAD_CFG_GPI_TRIG_OWN(GPP_E18, NONE, PLTRST, OFF, ACPI),
+	PAD_CFG_GPO(GPP_E19, 0, PLTRST),
+	PAD_CFG_GPI_TRIG_OWN(GPP_E20, NONE, PLTRST, OFF, ACPI),
+	PAD_CFG_GPI_TRIG_OWN(GPP_E21, NONE, PLTRST, OFF, ACPI),
+
+	/* ------- GPIO Group GPP_K ------- */
+	PAD_CFG_GPI_TRIG_OWN(GPP_K0, NONE, PLTRST, OFF, ACPI),
+	PAD_CFG_GPI_TRIG_OWN(GPP_K1, NONE, PLTRST, OFF, ACPI),
+	_PAD_CFG_STRUCT(GPP_K2, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1) | 1, 0),
+	PAD_CFG_GPI_TRIG_OWN(GPP_K3, NONE, PLTRST, OFF, ACPI),
+	PAD_CFG_GPI_TRIG_OWN(GPP_K4, NONE, PLTRST, OFF, ACPI),
+	PAD_CFG_GPI_TRIG_OWN(GPP_K5, NONE, PLTRST, OFF, ACPI),
+	_PAD_CFG_STRUCT(GPP_K6, PAD_FUNC(NF2) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), PAD_PULL(UP_20K)),
+	_PAD_CFG_STRUCT(GPP_K7, PAD_FUNC(NF2) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(DN_20K)),
+	PAD_CFG_GPO(GPP_K8, 1, PLTRST),
+	_PAD_CFG_STRUCT(GPP_K9, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0),
+	_PAD_CFG_STRUCT(GPP_K10, PAD_FUNC(NF2) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), PAD_PULL(UP_20K)),
+	PAD_CFG_GPI_TRIG_OWN(GPP_K11, NONE, PLTRST, OFF, ACPI),
+
+	/* ------- GPIO Group GPP_F ------- */
+	PAD_CFG_GPI_TRIG_OWN(GPP_F0, NONE, PLTRST, OFF, ACPI),
+	PAD_CFG_GPI_TRIG_OWN(GPP_F1, NONE, PLTRST, OFF, ACPI),
+	PAD_CFG_GPI_TRIG_OWN(GPP_F2, NONE, PLTRST, OFF, ACPI),
+	PAD_CFG_GPI_TRIG_OWN(GPP_F3, NONE, PLTRST, OFF, ACPI),
+	PAD_CFG_GPI_TRIG_OWN(GPP_F4, NONE, PLTRST, OFF, ACPI),
+	PAD_CFG_GPI_TRIG_OWN(GPP_F5, NONE, PLTRST, OFF, ACPI),
+	PAD_CFG_GPI_TRIG_OWN(GPP_F6, NONE, PLTRST, OFF, ACPI),
+	PAD_CFG_GPI_TRIG_OWN(GPP_F7, NONE, PLTRST, OFF, ACPI),
+	PAD_CFG_GPI_TRIG_OWN(GPP_F8, NONE, PLTRST, OFF, ACPI),
+	PAD_CFG_GPI_TRIG_OWN(GPP_F9, NONE, PLTRST, OFF, ACPI),
+	PAD_CFG_GPI_TRIG_OWN(GPP_F10, NONE, PLTRST, OFF, ACPI),
+	PAD_CFG_GPI_TRIG_OWN(GPP_F11, NONE, PLTRST, OFF, ACPI),
+	PAD_CFG_GPI_TRIG_OWN(GPP_F12, NONE, PLTRST, OFF, ACPI),
+	PAD_CFG_GPI_TRIG_OWN(GPP_F13, NONE, PLTRST, OFF, ACPI),
+	PAD_CFG_GPI_TRIG_OWN(GPP_F14, NONE, PLTRST, OFF, ACPI),
+	PAD_CFG_GPI_TRIG_OWN(GPP_F15, NONE, PLTRST, OFF, ACPI),
+	PAD_CFG_GPI_TRIG_OWN(GPP_F16, NONE, PLTRST, OFF, ACPI),
+	PAD_CFG_GPI_TRIG_OWN(GPP_F17, NONE, PLTRST, OFF, ACPI),
+	PAD_CFG_GPI_TRIG_OWN(GPP_F18, NONE, PLTRST, OFF, ACPI),
+	PAD_CFG_GPI_TRIG_OWN(GPP_F19, NONE, PLTRST, OFF, ACPI),
+	PAD_CFG_GPI_TRIG_OWN(GPP_F20, NONE, PLTRST, OFF, ACPI),
+	PAD_CFG_GPI_TRIG_OWN(GPP_F21, NONE, PLTRST, OFF, ACPI),
+	_PAD_CFG_STRUCT(GPP_F22, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | 1, 0),
+	PAD_CFG_GPI_TRIG_OWN(GPP_F23, NONE, PLTRST, OFF, ACPI),
+
+	/* ------- GPIO Community 5 ------- */
+
+	/* ------- GPIO Group GPP_D ------- */
+	_PAD_CFG_STRUCT(GPP_D0, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0),
+	PAD_CFG_GPI_TRIG_OWN(GPP_D1, NONE, PLTRST, OFF, ACPI),
+	PAD_CFG_GPI_TRIG_OWN(GPP_D2, NONE, PLTRST, OFF, ACPI),
+	PAD_CFG_GPI_TRIG_OWN(GPP_D3, NONE, PLTRST, OFF, ACPI),
+	_PAD_CFG_STRUCT(GPP_D4, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0),
+	_PAD_CFG_STRUCT(GPP_D5, PAD_FUNC(NF2) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), 0),
+	_PAD_CFG_STRUCT(GPP_D6, PAD_FUNC(NF3) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), 0),
+	PAD_CFG_GPI_TRIG_OWN(GPP_D7, NONE, PLTRST, OFF, ACPI),
+	PAD_CFG_GPI_TRIG_OWN(GPP_D8, NONE, PLTRST, OFF, ACPI),
+	_PAD_CFG_STRUCT(GPP_D9, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0),
+	_PAD_CFG_STRUCT(GPP_D10, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0),
+	_PAD_CFG_STRUCT(GPP_D11, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
+	PAD_CFG_GPI_TRIG_OWN(GPP_D12, NONE, PLTRST, OFF, ACPI),
+	PAD_CFG_GPI_TRIG_OWN(GPP_D13, NONE, PLTRST, OFF, ACPI),
+	PAD_CFG_GPI_TRIG_OWN(GPP_D14, NONE, PLTRST, OFF, ACPI),
+	_PAD_CFG_STRUCT(GPP_D15, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0),
+	PAD_CFG_GPI_TRIG_OWN(GPP_D16, NONE, PLTRST, OFF, ACPI),
+	PAD_CFG_GPI_TRIG_OWN(GPP_D17, NONE, DEEP, OFF, ACPI),
+	PAD_CFG_GPI_TRIG_OWN(GPP_D18, NONE, PLTRST, OFF, ACPI),
+	PAD_CFG_GPI_TRIG_OWN(GPP_D19, NONE, PLTRST, OFF, ACPI),
+	PAD_CFG_GPI_TRIG_OWN(GPP_D20, NONE, PLTRST, OFF, ACPI),
+	PAD_CFG_GPI_TRIG_OWN(GPP_D21, NONE, RSMRST, OFF, ACPI),
+	PAD_CFG_GPI_TRIG_OWN(GPP_D22, NONE, PLTRST, OFF, ACPI),
+	PAD_CFG_GPI_TRIG_OWN(GPP_D23, NONE, PLTRST, OFF, ACPI),
+
+	/* ------- GPIO Group JTAG ------- */
+
+	/* ------- GPIO Group CPU ------- */
+};
+
+/* PCIe CLK REQs as per devicetree.cb */
+static const struct pad_config clkreq_disabled_table[] = {
+	/* GPP_D0 - SRCCLKREQ0# */
+	PAD_NC(GPP_D0, NONE),
+	/* GPP_H6 - SRCCLKREQ4# */
+	PAD_NC(GPP_D11, NONE),
+	/* GPP_H6 - SRCCLKREQ11# */
+	PAD_NC(GPP_H5, NONE),
+	/* GPP_H6 - SRCCLKREQ12# */
+	PAD_NC(GPP_H6, NONE),
+
+	/* CPU PCIe CLKREQ virtual wire message buses */
+	_PAD_CFG_STRUCT(VGPIO_PCIE_0,  PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),
+	_PAD_CFG_STRUCT(VGPIO_PCIE_1,  PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),
+	_PAD_CFG_STRUCT(VGPIO_PCIE_2,  PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),
+	_PAD_CFG_STRUCT(VGPIO_PCIE_3,  PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),
+	_PAD_CFG_STRUCT(VGPIO_PCIE_4,  PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),
+	_PAD_CFG_STRUCT(VGPIO_PCIE_5,  PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),
+	_PAD_CFG_STRUCT(VGPIO_PCIE_6,  PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),
+	_PAD_CFG_STRUCT(VGPIO_PCIE_7,  PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),
+	_PAD_CFG_STRUCT(VGPIO_PCIE_8,  PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),
+	_PAD_CFG_STRUCT(VGPIO_PCIE_9,  PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),
+	_PAD_CFG_STRUCT(VGPIO_PCIE_10, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),
+	_PAD_CFG_STRUCT(VGPIO_PCIE_11, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),
+	_PAD_CFG_STRUCT(VGPIO_PCIE_12, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),
+	_PAD_CFG_STRUCT(VGPIO_PCIE_13, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),
+	_PAD_CFG_STRUCT(VGPIO_PCIE_14, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),
+	_PAD_CFG_STRUCT(VGPIO_PCIE_15, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),
+	_PAD_CFG_STRUCT(VGPIO_PCIE_64, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),
+	_PAD_CFG_STRUCT(VGPIO_PCIE_65, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),
+	_PAD_CFG_STRUCT(VGPIO_PCIE_66, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),
+	_PAD_CFG_STRUCT(VGPIO_PCIE_67, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),
+
+	_PAD_CFG_STRUCT(VGPIO_PCIE_16, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),
+	_PAD_CFG_STRUCT(VGPIO_PCIE_17, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),
+	_PAD_CFG_STRUCT(VGPIO_PCIE_18, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),
+	_PAD_CFG_STRUCT(VGPIO_PCIE_19, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),
+	_PAD_CFG_STRUCT(VGPIO_PCIE_20, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),
+	_PAD_CFG_STRUCT(VGPIO_PCIE_21, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),
+	_PAD_CFG_STRUCT(VGPIO_PCIE_22, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),
+	_PAD_CFG_STRUCT(VGPIO_PCIE_23, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),
+	_PAD_CFG_STRUCT(VGPIO_PCIE_24, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),
+	_PAD_CFG_STRUCT(VGPIO_PCIE_25, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),
+	_PAD_CFG_STRUCT(VGPIO_PCIE_26, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),
+	_PAD_CFG_STRUCT(VGPIO_PCIE_27, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),
+	_PAD_CFG_STRUCT(VGPIO_PCIE_28, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),
+	_PAD_CFG_STRUCT(VGPIO_PCIE_29, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),
+	_PAD_CFG_STRUCT(VGPIO_PCIE_30, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),
+	_PAD_CFG_STRUCT(VGPIO_PCIE_31, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),
+	_PAD_CFG_STRUCT(VGPIO_PCIE_68, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),
+	_PAD_CFG_STRUCT(VGPIO_PCIE_69, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),
+	_PAD_CFG_STRUCT(VGPIO_PCIE_70, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),
+	_PAD_CFG_STRUCT(VGPIO_PCIE_71, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),
+
+	_PAD_CFG_STRUCT(VGPIO_PCIE_32, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),
+	_PAD_CFG_STRUCT(VGPIO_PCIE_33, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),
+	_PAD_CFG_STRUCT(VGPIO_PCIE_34, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),
+	_PAD_CFG_STRUCT(VGPIO_PCIE_35, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),
+	_PAD_CFG_STRUCT(VGPIO_PCIE_36, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),
+	_PAD_CFG_STRUCT(VGPIO_PCIE_37, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),
+	_PAD_CFG_STRUCT(VGPIO_PCIE_38, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),
+	_PAD_CFG_STRUCT(VGPIO_PCIE_39, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),
+	_PAD_CFG_STRUCT(VGPIO_PCIE_40, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),
+	_PAD_CFG_STRUCT(VGPIO_PCIE_41, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),
+	_PAD_CFG_STRUCT(VGPIO_PCIE_42, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),
+	_PAD_CFG_STRUCT(VGPIO_PCIE_43, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),
+	_PAD_CFG_STRUCT(VGPIO_PCIE_44, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),
+	_PAD_CFG_STRUCT(VGPIO_PCIE_45, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),
+	_PAD_CFG_STRUCT(VGPIO_PCIE_46, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),
+	_PAD_CFG_STRUCT(VGPIO_PCIE_47, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),
+	_PAD_CFG_STRUCT(VGPIO_PCIE_72, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),
+	_PAD_CFG_STRUCT(VGPIO_PCIE_73, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),
+	_PAD_CFG_STRUCT(VGPIO_PCIE_74, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),
+	_PAD_CFG_STRUCT(VGPIO_PCIE_75, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),
+
+	_PAD_CFG_STRUCT(VGPIO_PCIE_48, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),
+	_PAD_CFG_STRUCT(VGPIO_PCIE_49, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),
+	_PAD_CFG_STRUCT(VGPIO_PCIE_50, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),
+	_PAD_CFG_STRUCT(VGPIO_PCIE_51, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),
+	_PAD_CFG_STRUCT(VGPIO_PCIE_52, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),
+	_PAD_CFG_STRUCT(VGPIO_PCIE_53, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),
+	_PAD_CFG_STRUCT(VGPIO_PCIE_54, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),
+	_PAD_CFG_STRUCT(VGPIO_PCIE_55, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),
+	_PAD_CFG_STRUCT(VGPIO_PCIE_56, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),
+	_PAD_CFG_STRUCT(VGPIO_PCIE_57, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),
+	_PAD_CFG_STRUCT(VGPIO_PCIE_58, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),
+	_PAD_CFG_STRUCT(VGPIO_PCIE_59, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),
+	_PAD_CFG_STRUCT(VGPIO_PCIE_60, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),
+	_PAD_CFG_STRUCT(VGPIO_PCIE_61, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),
+	_PAD_CFG_STRUCT(VGPIO_PCIE_62, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),
+	_PAD_CFG_STRUCT(VGPIO_PCIE_63, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),
+	_PAD_CFG_STRUCT(VGPIO_PCIE_76, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),
+	_PAD_CFG_STRUCT(VGPIO_PCIE_77, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),
+	_PAD_CFG_STRUCT(VGPIO_PCIE_78, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),
+	_PAD_CFG_STRUCT(VGPIO_PCIE_79, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),
+};
+
+#endif /* CFG_GPIO_H */
diff --git a/src/mainboard/asus/h610i-plus-d4/hda_verb.c b/src/mainboard/asus/h610i-plus-d4/hda_verb.c
new file mode 100644
index 0000000000..173845d32e
--- /dev/null
+++ b/src/mainboard/asus/h610i-plus-d4/hda_verb.c
@@ -0,0 +1,163 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <device/azalia_device.h>
+
+const u32 cim_verb_data[] = {
+	0x10ec0897, // Vendor/Device ID: Realtek ALC897
+	0x10438803, // Subsystem ID
+	15,
+	AZALIA_SUBVENDOR(0, 0x10438803),
+
+	AZALIA_PIN_CFG(0, 0x11, AZALIA_PIN_CFG_NC(0)),
+	AZALIA_PIN_CFG(0, 0x12, 0x40330040), // does not describe a jack or internal device
+	AZALIA_PIN_CFG(0, 0x14, AZALIA_PIN_DESC(
+		AZALIA_JACK,
+		AZALIA_EXTERNAL_PRIMARY_CHASSIS | AZALIA_REAR,
+		AZALIA_LINE_OUT,
+		AZALIA_STEREO_MONO_1_8,
+		AZALIA_GREEN,
+		AZALIA_JACK_PRESENCE_DETECT,
+		1, 0
+	)),
+	AZALIA_PIN_CFG(0, 0x15, AZALIA_PIN_DESC(
+		AZALIA_JACK,
+		AZALIA_EXTERNAL_PRIMARY_CHASSIS | AZALIA_REAR,
+		AZALIA_LINE_IN,
+		AZALIA_STEREO_MONO_1_8,
+		AZALIA_BLUE,
+		AZALIA_JACK_PRESENCE_DETECT,
+		3, 15
+	)),
+	AZALIA_PIN_CFG(0, 0x16, AZALIA_PIN_CFG_NC(0)),
+	AZALIA_PIN_CFG(0, 0x17, AZALIA_PIN_CFG_NC(0)),
+	AZALIA_PIN_CFG(0, 0x18, AZALIA_PIN_DESC(
+		AZALIA_JACK,
+		AZALIA_EXTERNAL_PRIMARY_CHASSIS | AZALIA_REAR,
+		AZALIA_MIC_IN,
+		AZALIA_STEREO_MONO_1_8,
+		AZALIA_PINK,
+		AZALIA_JACK_PRESENCE_DETECT,
+		3, 0
+	)),
+	AZALIA_PIN_CFG(0, 0x19, AZALIA_PIN_DESC(
+		AZALIA_JACK,
+		AZALIA_EXTERNAL_PRIMARY_CHASSIS | AZALIA_FRONT,
+		AZALIA_MIC_IN,
+		AZALIA_STEREO_MONO_1_8,
+		AZALIA_PINK,
+		AZALIA_JACK_PRESENCE_DETECT,
+		4, 0
+	)),
+	AZALIA_PIN_CFG(0, 0x1a, AZALIA_PIN_DESC(
+		AZALIA_INTEGRATED,
+		AZALIA_INTERNAL,
+		AZALIA_SPEAKER,
+		AZALIA_OTHER_ANALOG,
+		AZALIA_COLOR_UNKNOWN,
+		AZALIA_NO_JACK_PRESENCE_DETECT,
+		1, 15
+	)),
+	AZALIA_PIN_CFG(0, 0x1b, AZALIA_PIN_DESC(
+		AZALIA_JACK,
+		AZALIA_EXTERNAL_PRIMARY_CHASSIS | AZALIA_FRONT,
+		AZALIA_HP_OUT,
+		AZALIA_STEREO_MONO_1_8,
+		AZALIA_GREEN,
+		AZALIA_JACK_PRESENCE_DETECT,
+		2, 0
+	)),
+	AZALIA_PIN_CFG(0, 0x1c, AZALIA_PIN_CFG_NC(0)),
+	AZALIA_PIN_CFG(0, 0x1d, 0x4048ee29), // does not describe a jack or internal device
+	AZALIA_PIN_CFG(0, 0x1e, AZALIA_PIN_CFG_NC(0)),
+	AZALIA_PIN_CFG(0, 0x1f, AZALIA_PIN_CFG_NC(0)),
+
+	0x80862815, // Vendor/Device ID: Intel Alderlake HDMI
+	0x80860101, // Subsystem ID
+	10,
+	AZALIA_SUBVENDOR(2, 0x80860101),
+
+	AZALIA_PIN_CFG(2, 0x04, AZALIA_PIN_DESC(
+		AZALIA_JACK,
+		AZALIA_DIGITAL_DISPLAY,
+		AZALIA_DIGITAL_OTHER_OUT,
+		AZALIA_OTHER_DIGITAL,
+		AZALIA_COLOR_UNKNOWN,
+		AZALIA_JACK_PRESENCE_DETECT,
+		1, 0
+	)),
+	AZALIA_PIN_CFG(2, 0x06, AZALIA_PIN_DESC(
+		AZALIA_JACK,
+		AZALIA_DIGITAL_DISPLAY,
+		AZALIA_DIGITAL_OTHER_OUT,
+		AZALIA_OTHER_DIGITAL,
+		AZALIA_COLOR_UNKNOWN,
+		AZALIA_JACK_PRESENCE_DETECT,
+		1, 0
+	)),
+	AZALIA_PIN_CFG(2, 0x08, AZALIA_PIN_DESC(
+		AZALIA_JACK,
+		AZALIA_DIGITAL_DISPLAY,
+		AZALIA_DIGITAL_OTHER_OUT,
+		AZALIA_OTHER_DIGITAL,
+		AZALIA_COLOR_UNKNOWN,
+		AZALIA_JACK_PRESENCE_DETECT,
+		1, 0
+	)),
+	AZALIA_PIN_CFG(2, 0x0a, AZALIA_PIN_DESC(
+		AZALIA_JACK,
+		AZALIA_DIGITAL_DISPLAY,
+		AZALIA_DIGITAL_OTHER_OUT,
+		AZALIA_OTHER_DIGITAL,
+		AZALIA_COLOR_UNKNOWN,
+		AZALIA_JACK_PRESENCE_DETECT,
+		1, 0
+	)),
+	AZALIA_PIN_CFG(2, 0x0b, AZALIA_PIN_DESC(
+		AZALIA_JACK,
+		AZALIA_DIGITAL_DISPLAY,
+		AZALIA_DIGITAL_OTHER_OUT,
+		AZALIA_OTHER_DIGITAL,
+		AZALIA_COLOR_UNKNOWN,
+		AZALIA_JACK_PRESENCE_DETECT,
+		1, 0
+	)),
+	AZALIA_PIN_CFG(2, 0x0c, AZALIA_PIN_DESC(
+		AZALIA_JACK,
+		AZALIA_DIGITAL_DISPLAY,
+		AZALIA_DIGITAL_OTHER_OUT,
+		AZALIA_OTHER_DIGITAL,
+		AZALIA_COLOR_UNKNOWN,
+		AZALIA_JACK_PRESENCE_DETECT,
+		1, 0
+	)),
+	AZALIA_PIN_CFG(2, 0x0d, AZALIA_PIN_DESC(
+		AZALIA_JACK,
+		AZALIA_DIGITAL_DISPLAY,
+		AZALIA_DIGITAL_OTHER_OUT,
+		AZALIA_OTHER_DIGITAL,
+		AZALIA_COLOR_UNKNOWN,
+		AZALIA_JACK_PRESENCE_DETECT,
+		1, 0
+	)),
+	AZALIA_PIN_CFG(2, 0x0e, AZALIA_PIN_DESC(
+		AZALIA_JACK,
+		AZALIA_DIGITAL_DISPLAY,
+		AZALIA_DIGITAL_OTHER_OUT,
+		AZALIA_OTHER_DIGITAL,
+		AZALIA_COLOR_UNKNOWN,
+		AZALIA_JACK_PRESENCE_DETECT,
+		1, 0
+	)),
+	AZALIA_PIN_CFG(2, 0x0f, AZALIA_PIN_DESC(
+		AZALIA_JACK,
+		AZALIA_DIGITAL_DISPLAY,
+		AZALIA_DIGITAL_OTHER_OUT,
+		AZALIA_OTHER_DIGITAL,
+		AZALIA_COLOR_UNKNOWN,
+		AZALIA_JACK_PRESENCE_DETECT,
+		1, 0
+	)),
+};
+
+const u32 pc_beep_verbs[] = {};
+AZALIA_ARRAY_SIZES;
diff --git a/src/mainboard/asus/h610i-plus-d4/mainboard.c b/src/mainboard/asus/h610i-plus-d4/mainboard.c
new file mode 100644
index 0000000000..ff24624972
--- /dev/null
+++ b/src/mainboard/asus/h610i-plus-d4/mainboard.c
@@ -0,0 +1,240 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <acpi/acpi.h>
+#include <device/device.h>
+#include <identity.h>
+#include <soc/pci_devs.h>
+#include <soc/ramstage.h>
+#include <smbios.h>
+#include <string.h>
+#include <bootstate.h>
+#include <superio/nuvoton/common/hwm.h>
+
+// This is the base address of the HWM registers (set in the device tree)
+#define HWM_IOBASE		0x290
+
+// The registers below are in a separate bank for each fan
+// On the H610I-PLUS and H610M-K only SYSFAN and CPUFAN are wired up
+#define BANK_SYSFAN		1
+#define BANK_CPUFAN		2
+
+#define FAN_SOURCE		0x00		// Fan control temperature source
+# define FAN_SOURCE_PECI0       0x10		// PECI Agent 0
+# define FAN_SOURCE_PECI0_CAL	0x1c		// PECI Agent 0 Calibration
+
+#define FAN_MODE_TEMP_TOLERANCE	0x02		// [7:4] = mode [2:0] temperature tolerance
+# define FAN_MODE_SFIV		4		// SmartFan IV
+#define FAN_STEP_UP_TIME	0x03		// In 0.1 sec
+#define FAN_STEP_DOWN_TIME	0x04		// In 0.1 sec
+#define FAN_DUTY_PER_STEP	0x66		// [7:4] step up val [3:0] step down val
+
+#define FAN_TEMP(i)		(0x21 + (i))	// Temperature points on the curve (4 points)
+#define FAN_DUTY(i)		(0x27 + (i))	// Corresponding duty for each temperature point
+
+#define FAN_CRIT_TEMP		0x35		// Critical temperature
+#define FAN_CRIT_DUTY_EN	0x36		// Use critical duty (or default to 255)
+#define FAN_CRIT_DUTY		0x37		// Critical duty
+#define FAN_CRIT_TEMP_TOLERANCE	0x38		// Critical temperature tolerance
+
+struct nct_fan {
+	const char *name;
+	uint8_t bank;
+
+	// Temperature source
+	uint8_t source;
+
+	// Temperature x duty cycle curve points
+	uint8_t temp[4];
+	uint8_t duty[4];
+
+	// Temperature tolerance
+	uint8_t temp_tolerance;
+
+	// Step up and down smoothing
+	uint8_t step_up_time;
+	uint8_t step_down_time;
+	uint8_t duty_per_step_up;
+	uint8_t duty_per_step_down;
+
+	// Critical mode
+	uint8_t crit_temp;
+	uint8_t crit_duty_en;
+	uint8_t crit_duty;
+	uint8_t crit_temp_tolerance;
+};
+
+#define PERCENT_TO_DUTY(perc)	((perc) * 255 / 100)
+
+// These fan curves have been adjusted from Mate Kukri's original values (for his i3-12100), and work well with my i7-12700
+static const struct nct_fan NCT_FANS[] = {
+	{
+		.name = "SYSFAN",
+		.bank = BANK_SYSFAN,
+		.source = FAN_SOURCE_PECI0,
+		.temp = {40, 60, 75, 90},
+		.duty = {PERCENT_TO_DUTY(20), PERCENT_TO_DUTY(40), PERCENT_TO_DUTY(70), PERCENT_TO_DUTY(100)},
+		.crit_temp = 100,
+		.crit_duty_en = 1,
+		.crit_duty = 255,
+		.crit_temp_tolerance = 2,
+	},
+	{
+		.name = "CPUFAN",
+		.bank = BANK_CPUFAN,
+		.source = FAN_SOURCE_PECI0,
+		.temp = {40, 60, 75, 90},
+		.duty = {PERCENT_TO_DUTY(20), PERCENT_TO_DUTY(40), PERCENT_TO_DUTY(70), PERCENT_TO_DUTY(100)},
+		.crit_temp = 100,
+		.crit_duty_en = 1,
+		.crit_duty = 255,
+		.crit_temp_tolerance = 2,
+	},
+};
+
+void mainboard_fill_fadt(acpi_fadt_t *fadt)
+{
+	fadt->preferred_pm_profile = PM_DESKTOP;
+	fadt->iapc_boot_arch |= ACPI_FADT_LEGACY_DEVICES | ACPI_FADT_8042;
+}
+
+static void mainboard_init(void *chip_info)
+{
+
+}
+
+static void mainboard_enable(struct device *dev)
+{
+
+}
+
+void mainboard_silicon_init_params(FSP_S_CONFIG *params)
+{
+	uint8_t aspm, aspm_l1;
+
+	/* ASPM L1 sub-states require CLKREQ, so CLK_PM should be enabled as well */
+	if (CONFIG(PCIEXP_L1_SUB_STATE) && CONFIG(PCIEXP_CLK_PM))
+		aspm_l1 = 2; // 2 - L1.1 and L1.2
+	else
+		aspm_l1 = 0;
+
+	if (CONFIG(PCIEXP_ASPM)) {
+		aspm = CONFIG(PCIEXP_L1_SUB_STATE) ? 3 : 1; // 3 - L0sL1, 1 - L0s
+	} else {
+		aspm = 0;
+		aspm_l1 = 0;
+	}
+
+	memset(params->PcieRpEnableCpm, 0, sizeof(params->PcieRpEnableCpm));
+	memset(params->CpuPcieRpEnableCpm, 0, sizeof(params->CpuPcieRpEnableCpm));
+	memset(params->CpuPcieClockGating, 0, sizeof(params->CpuPcieClockGating));
+	memset(params->CpuPciePowerGating, 0, sizeof(params->CpuPciePowerGating));
+
+	params->UsbPdoProgramming = 1;
+
+	params->CpuPcieFiaProgramming = 1;
+
+	params->PcieRpFunctionSwap = 0;
+	params->CpuPcieRpFunctionSwap = 0;
+
+	params->PchLegacyIoLowLatency = 1;
+	params->PchDmiAspmCtrl = 0;
+
+	params->CpuPcieRpPmSci[2] = 1; // PCI_E1
+	params->PcieRpPmSci[1]    = 1; // M2_1
+	params->PcieRpPmSci[5]    = 1; // Ethernet
+	params->PcieRpPmSci[6]    = 1; // WiFi
+
+	params->PcieRpMaxPayload[0]  = 1; // PCI_E2
+	params->PcieRpMaxPayload[1]  = 1; // M2_1
+	params->PcieRpMaxPayload[5]  = 1; // Ethernet
+	params->PcieRpMaxPayload[6]  = 1; // WiFi
+
+	params->CpuPcieRpTransmitterHalfSwing[2] = 1; // PCI_E1
+	params->PcieRpTransmitterHalfSwing[1]    = 1; // M2_1
+	params->PcieRpTransmitterHalfSwing[5]    = 1; // Ethernet
+	params->PcieRpTransmitterHalfSwing[6]    = 1; // WiFi
+
+	params->CpuPcieRpEnableCpm[2] = CONFIG(PCIEXP_CLK_PM); // PCI_E1
+	params->PcieRpEnableCpm[1]    = CONFIG(PCIEXP_CLK_PM); // M2_1
+	params->PcieRpEnableCpm[5]    = CONFIG(PCIEXP_CLK_PM); // Ethernet
+	params->PcieRpEnableCpm[6]    = CONFIG(PCIEXP_CLK_PM); // WiFi
+
+	params->CpuPcieRpL1Substates[2] = aspm_l1; // PCI_E1
+	params->PcieRpL1Substates[1]    = aspm_l1; // M2_1
+	params->PcieRpL1Substates[5]    = aspm_l1; // Ethernet
+	params->PcieRpL1Substates[6]    = aspm_l1; // WiFi
+
+	params->CpuPcieRpAspm[2] = aspm; // PCI_E1
+	params->PcieRpAspm[1]    = aspm; // M2_1
+	params->PcieRpAspm[5]    = aspm; // Ethernet
+	params->PcieRpAspm[6]    = aspm; // WiFi
+
+	params->PcieRpAcsEnabled[1]  = 1; // M2_1
+	params->PcieRpAcsEnabled[5]  = 1; // Ethernet
+	params->PcieRpAcsEnabled[6]  = 1; // WiFi
+
+	params->CpuPcieClockGating[2] = CONFIG(PCIEXP_CLK_PM);
+	params->CpuPciePowerGating[2] = CONFIG(PCIEXP_CLK_PM);
+	params->CpuPcieRpPeerToPeerMode[2] = 1;
+	params->CpuPcieRpMaxPayload[2] = 2; // 512B
+	params->CpuPcieRpAcsEnabled[2] = 1;
+
+	params->SataLedEnable = 1;
+}
+
+struct chip_operations mainboard_ops = {
+	.init = mainboard_init,
+	.enable_dev = mainboard_enable,
+};
+
+static void nct6798d_hwm_init(void *arg)
+{
+	printk(BIOS_DEBUG, "NCT6798D HWM configuration\n");
+
+	// Setup PECI
+	// Devicetree must set pin 121 to PECI mode first
+	nuvoton_hwm_select_bank(HWM_IOBASE, 7);
+	pnp_write_hwm5_index(HWM_IOBASE, 1, 0x85);
+	pnp_write_hwm5_index(HWM_IOBASE, 2, 0x02);
+	pnp_write_hwm5_index(HWM_IOBASE, 3, 0x10);
+	pnp_write_hwm5_index(HWM_IOBASE, 4, 0x00);
+	pnp_write_hwm5_index(HWM_IOBASE, 9, 0x64);
+
+	// Enable PECI temp reading
+	nuvoton_hwm_select_bank(HWM_IOBASE, 0);
+	pnp_write_hwm5_index(HWM_IOBASE, 0xae, 1);
+
+	// Program PECI Agent 0 Calibration
+	nuvoton_hwm_select_bank(HWM_IOBASE, 4);
+	pnp_write_hwm5_index(HWM_IOBASE, 0xf8, 0x50);
+	pnp_write_hwm5_index(HWM_IOBASE, 0xfa, 0x51);
+
+
+	// Program fan control profiles
+	for (const struct nct_fan *fan = NCT_FANS; fan < NCT_FANS + ARRAY_SIZE(NCT_FANS); ++fan) {
+		printk(BIOS_DEBUG, "Configuring NCT6798D fan %s\n", fan->name);
+
+		nuvoton_hwm_select_bank(HWM_IOBASE, fan->bank);
+
+		pnp_write_hwm5_index(HWM_IOBASE, FAN_SOURCE, fan->source);
+
+		for (size_t i = 0; i < 4; ++i)
+			pnp_write_hwm5_index(HWM_IOBASE, FAN_TEMP(i), fan->temp[i]);
+		for (size_t i = 0; i < 4; ++i)
+			pnp_write_hwm5_index(HWM_IOBASE, FAN_DUTY(i), fan->duty[i]);
+
+		pnp_write_hwm5_index(HWM_IOBASE, FAN_CRIT_TEMP, fan->crit_temp);
+		pnp_write_hwm5_index(HWM_IOBASE, FAN_CRIT_DUTY_EN, fan->crit_duty_en);
+		pnp_write_hwm5_index(HWM_IOBASE, FAN_CRIT_DUTY, fan->crit_duty);
+		pnp_write_hwm5_index(HWM_IOBASE, FAN_CRIT_TEMP_TOLERANCE, fan->crit_temp_tolerance);
+
+		pnp_write_hwm5_index(HWM_IOBASE, FAN_STEP_UP_TIME, fan->step_up_time);
+		pnp_write_hwm5_index(HWM_IOBASE, FAN_STEP_DOWN_TIME, fan->step_down_time);
+		pnp_write_hwm5_index(HWM_IOBASE, FAN_DUTY_PER_STEP, fan->duty_per_step_up << 4 | fan->duty_per_step_down);
+
+		// There are other modes supported by hardware, but always use SmartFan IV mode here
+		pnp_write_hwm5_index(HWM_IOBASE, FAN_MODE_TEMP_TOLERANCE, (FAN_MODE_SFIV << 4) | fan->temp_tolerance);
+	}
+}
+
+BOOT_STATE_INIT_ENTRY(BS_POST_DEVICE, BS_ON_EXIT, nct6798d_hwm_init, NULL);
diff --git a/src/mainboard/asus/h610i-plus-d4/romstage_fsp_params.c b/src/mainboard/asus/h610i-plus-d4/romstage_fsp_params.c
new file mode 100644
index 0000000000..8419772bc0
--- /dev/null
+++ b/src/mainboard/asus/h610i-plus-d4/romstage_fsp_params.c
@@ -0,0 +1,66 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <fsp/api.h>
+#include <soc/romstage.h>
+#include <soc/meminit.h>
+#include <string.h>
+
+#include "gpio.h"
+
+#define FSP_CLK_NOTUSED			0xFF
+#define FSP_CLK_FREE_RUNNING	0x80
+
+static const struct mb_cfg ddr4_mem_config = {
+	.type = MEM_TYPE_DDR4,
+	.UserBd = BOARD_TYPE_DESKTOP_1DPC,
+
+	.ddr_config = {
+		.dq_pins_interleaved = true,
+	},
+};
+
+static const struct mem_spd dimm_module_spd_info = {
+	.topo = MEM_TOPO_DIMM_MODULE,
+	.smbus = {
+		[0] = {
+			.addr_dimm[0] = 0x50,
+		},
+		[1] = {
+			.addr_dimm[0] = 0x52,
+		},
+	},
+};
+
+static void disable_pcie_clock_requests(FSP_M_CONFIG *m_cfg)
+{
+	memset(m_cfg->PcieClkSrcUsage, FSP_CLK_NOTUSED, sizeof(m_cfg->PcieClkSrcUsage));
+	memset(m_cfg->PcieClkSrcClkReq, FSP_CLK_NOTUSED, sizeof(m_cfg->PcieClkSrcClkReq));
+
+	/* PCIe CLK SRCes as per devicetree.cb */
+	m_cfg->PcieClkSrcUsage[0]  = FSP_CLK_FREE_RUNNING;
+	m_cfg->PcieClkSrcUsage[4]  = FSP_CLK_FREE_RUNNING;
+	m_cfg->PcieClkSrcUsage[11]  = FSP_CLK_FREE_RUNNING;
+	m_cfg->PcieClkSrcUsage[12] = FSP_CLK_FREE_RUNNING;
+
+	gpio_configure_pads(clkreq_disabled_table, ARRAY_SIZE(clkreq_disabled_table));
+}
+
+void mainboard_memory_init_params(FSPM_UPD *memupd)
+{
+	memupd->FspmConfig.CpuPcieRpClockReqMsgEnable[0] = CONFIG(PCIEXP_CLK_PM);
+	memupd->FspmConfig.CpuPcieRpClockReqMsgEnable[1] = CONFIG(PCIEXP_CLK_PM);
+	memupd->FspmConfig.CpuPcieRpClockReqMsgEnable[2] = CONFIG(PCIEXP_CLK_PM);
+	memupd->FspmConfig.DmiMaxLinkSpeed = 4; // Gen4 speed, undocumented
+	memupd->FspmConfig.DmiAspm = 0;
+	memupd->FspmConfig.DmiAspmCtrl = 0;
+	memupd->FspmConfig.SkipExtGfxScan = 0;
+
+	memupd->FspmConfig.PchHdaSdiEnable[0] = 1;
+
+	memcfg_init(memupd, &ddr4_mem_config, &dimm_module_spd_info, false);
+
+	gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table));
+
+	if (!CONFIG(PCIEXP_CLK_PM))
+		disable_pcie_clock_requests(&memupd->FspmConfig);
+}

From c1e03843676aa714d9354554a507346f50577ac5 Mon Sep 17 00:00:00 2001
From: Ziang Wang <wangziang.ok@bytedance.com>
Date: Thu, 25 Sep 2025 16:03:54 +0800
Subject: [PATCH 2125/3886] arch/riscv/include: Cast 'id' to int in OTHER_HLS()
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

The 'id' in OTHER_HSL macro is non-typed, downflow would occur when
‘id’ is unsigned and less greater than hart_id. Cast it to int.

Change-Id: I777337b7e374024aff6fb36de603b799b1a65371
Signed-off-by: Ziang Wang <wangziang.ok@bytedance.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89338
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
---
 src/arch/riscv/include/mcall.h | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/src/arch/riscv/include/mcall.h b/src/arch/riscv/include/mcall.h
index 69eb5741ef..7eb7f6c1eb 100644
--- a/src/arch/riscv/include/mcall.h
+++ b/src/arch/riscv/include/mcall.h
@@ -62,7 +62,8 @@ register uintptr_t current_stack_pointer asm("sp");
 
 // hart-local storage, at top of stack
 #define HLS() ((struct hls *)(MACHINE_STACK_TOP() - HLS_SIZE))
-#define OTHER_HLS(id) ((struct hls *)((void *)HLS() + RISCV_PGSIZE * ((id) - HLS()->hart_id)))
+#define OTHER_HLS(id) \
+	((struct hls *)((void *)HLS() + RISCV_PGSIZE * (((int)id) - HLS()->hart_id)))
 
 #define MACHINE_STACK_SIZE RISCV_PGSIZE
 

From ba3f529681d6dc6e911f89b68921384d773b0d1e Mon Sep 17 00:00:00 2001
From: Ziang Wang <wangziang.ok@bytedance.com>
Date: Thu, 25 Sep 2025 16:09:42 +0800
Subject: [PATCH 2126/3886] drivers/emulation/qemu: Adjust fw_cfg driver for
 Arm and RISCV

According to QEMU docs/specs/fw_cfg.rst, the selector and data register
offsets of Arm & RISCV should be 0x8 and 0x0. Besides, the selector
register should be in big-endian when using MMIO access.

TEST=build and run successfully on QEMU rvvirt machine. Using command
"qemu-system-riscv64 -machine virt -bios build/coreboot.rom -nographic
-drive if=pflash,file=./build/coreboot.rom,format=raw".

Change-Id: I1c4d40a4dbcac4067a7c69ba916e6ff0a21cdcb6
Signed-off-by: Dong Wei <weidong.wd@bytedance.com>
Signed-off-by: Ziang Wang <wangziang.ok@bytedance.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89339
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
---
 src/drivers/emulation/qemu/fw_cfg.c | 17 ++++++++++++++---
 1 file changed, 14 insertions(+), 3 deletions(-)

diff --git a/src/drivers/emulation/qemu/fw_cfg.c b/src/drivers/emulation/qemu/fw_cfg.c
index 98f2a7b94d..3947a54a11 100644
--- a/src/drivers/emulation/qemu/fw_cfg.c
+++ b/src/drivers/emulation/qemu/fw_cfg.c
@@ -11,10 +11,17 @@
 #include <device/fw_cfg.h>
 #include <device/fw_cfg_if.h>
 
+#if CONFIG(ARCH_ARM) || CONFIG(ARCH_RISCV)
+#define FW_CFG_PORT_CTL       0x08
+#define FW_CFG_PORT_DATA      0x00
+#define FW_CFG_DMA_ADDR_HIGH  0x10
+#define FW_CFG_DMA_ADDR_LOW   0x14
+#else
 #define FW_CFG_PORT_CTL       0x0510
 #define FW_CFG_PORT_DATA      0x0511
 #define FW_CFG_DMA_ADDR_HIGH  0x0514
 #define FW_CFG_DMA_ADDR_LOW   0x0518
+#endif
 
 static int fw_cfg_detected;
 static uint8_t fw_ver;
@@ -43,10 +50,14 @@ static int fw_cfg_present(void)
 
 static void fw_cfg_select(uint16_t entry)
 {
-	if (fw_ver & FW_CFG_VERSION_DMA)
+	if (fw_ver & FW_CFG_VERSION_DMA) {
 		fw_cfg_dma(FW_CFG_DMA_CTL_SELECT | entry << 16, NULL, 0);
-	else
-		outw(entry, FW_CFG_PORT_CTL);
+	} else {
+#ifdef __ARCH_GENERIC_IO_H__
+		entry = cpu_to_be16 (entry); // Big endian if MMIO
+#endif
+		outw(entry, FW_CFG_PORT_CTL); // Little endian if IO-port
+	}
 }
 
 static void fw_cfg_read(void *dst, int dstlen)

From 622c504a714bc65a80fae035bc7dbe5286f0c1e9 Mon Sep 17 00:00:00 2001
From: Ziang Wang <wangziang.ok@bytedance.com>
Date: Thu, 25 Sep 2025 17:04:35 +0800
Subject: [PATCH 2127/3886] mb/emulation/qemu-riscv: Select
 DRIVERS_EMULATION_QEMU_FW_CFG

This patch also provides valid 'io_port_mmio_base', which is the addr of
VIRT_FW_CFG device @0x1010_0000 used to convey ACPI & SMBIOS info.

TEST=build and run successfully on QEMU rvvirt machine.

Change-Id: I3cfd3020f1edacbc647188ab232c0a35dbd71f74
Signed-off-by: Ziang Wang <wangziang.ok@bytedance.com>
Signed-off-by: Dong Wei <weidong.wd@bytedance.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89344
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
---
 src/mainboard/emulation/qemu-riscv/Kconfig                  | 1 +
 src/mainboard/emulation/qemu-riscv/Makefile.mk              | 3 +++
 .../emulation/qemu-riscv/include/mainboard/addressmap.h     | 1 +
 src/mainboard/emulation/qemu-riscv/mmio.c                   | 6 ++++++
 4 files changed, 11 insertions(+)
 create mode 100644 src/mainboard/emulation/qemu-riscv/mmio.c

diff --git a/src/mainboard/emulation/qemu-riscv/Kconfig b/src/mainboard/emulation/qemu-riscv/Kconfig
index 18eaaf081d..c6ff42bdb2 100644
--- a/src/mainboard/emulation/qemu-riscv/Kconfig
+++ b/src/mainboard/emulation/qemu-riscv/Kconfig
@@ -37,6 +37,7 @@ config BOARD_SPECIFIC_OPTIONS
 	select ARCH_RAMSTAGE_RISCV
 	select RISCV_USE_ARCH_TIMER
 	select FLATTENED_DEVICE_TREE
+	select DRIVERS_EMULATION_QEMU_FW_CFG
 
 config MEMLAYOUT_LD_FILE
 	string
diff --git a/src/mainboard/emulation/qemu-riscv/Makefile.mk b/src/mainboard/emulation/qemu-riscv/Makefile.mk
index 0f240aacd1..90e5023feb 100644
--- a/src/mainboard/emulation/qemu-riscv/Makefile.mk
+++ b/src/mainboard/emulation/qemu-riscv/Makefile.mk
@@ -5,6 +5,7 @@ bootblock-y += uart.c
 bootblock-y += rom_media.c
 bootblock-y += clint.c
 bootblock-y += smp.c
+bootblock-y += mmio.c
 
 romstage-y += cbmem.c
 romstage-y += romstage.c
@@ -12,6 +13,7 @@ romstage-y += uart.c
 romstage-y += rom_media.c
 romstage-y += clint.c
 romstage-y += smp.c
+romstage-y += mmio.c
 
 ramstage-y += mainboard.c
 ramstage-y += uart.c
@@ -20,5 +22,6 @@ ramstage-y += clint.c
 ramstage-y += cbmem.c
 ramstage-y += chip.c
 ramstage-y += smp.c
+ramstage-y += mmio.c
 
 CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/include
diff --git a/src/mainboard/emulation/qemu-riscv/include/mainboard/addressmap.h b/src/mainboard/emulation/qemu-riscv/include/mainboard/addressmap.h
index 542e39592b..eb0e9f3440 100644
--- a/src/mainboard/emulation/qemu-riscv/include/mainboard/addressmap.h
+++ b/src/mainboard/emulation/qemu-riscv/include/mainboard/addressmap.h
@@ -4,5 +4,6 @@
 #define QEMU_VIRT_PLIC		0x0c000000
 #define QEMU_VIRT_UART0		0x10000000
 #define QEMU_VIRT_VIRTIO	0x10001000
+#define QEMU_VIRT_FW_CFG	0x10100000
 #define QEMU_VIRT_FLASH		0x20000000
 #define QEMU_VIRT_DRAM		0x80000000
diff --git a/src/mainboard/emulation/qemu-riscv/mmio.c b/src/mainboard/emulation/qemu-riscv/mmio.c
new file mode 100644
index 0000000000..86fc626d14
--- /dev/null
+++ b/src/mainboard/emulation/qemu-riscv/mmio.c
@@ -0,0 +1,6 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <types.h>
+#include <mainboard/addressmap.h>
+
+uintptr_t io_port_mmio_base = QEMU_VIRT_FW_CFG;

From 82a9e601bde4cf7e8d7856d366ddc8b2e1feea2b Mon Sep 17 00:00:00 2001
From: Varun Upadhyay <varun.upadhyay@intel.com>
Date: Wed, 10 Sep 2025 00:48:32 +0530
Subject: [PATCH 2128/3886] mb/google/ocelot/var/ojal: Add initial GPIOs config

Configure GPIOs according to schematics revision 0.9.
RDC kit no:840138

BUG=b:437459757
TEST=Build ojal board

Change-Id: I95c2f84c19b00847ce7fb11d62477b4920ad90ec
Signed-off-by: Varun Upadhyay <varun.upadhyay@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89126
Reviewed-by: Pranava Y N <pranavayn@google.com>
Reviewed-by: Usha P <usha.p@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 .../google/ocelot/variants/ojal/gpio.c        | 204 ++++++++----------
 1 file changed, 94 insertions(+), 110 deletions(-)

diff --git a/src/mainboard/google/ocelot/variants/ojal/gpio.c b/src/mainboard/google/ocelot/variants/ojal/gpio.c
index dcef9f7579..8c9686ea2d 100644
--- a/src/mainboard/google/ocelot/variants/ojal/gpio.c
+++ b/src/mainboard/google/ocelot/variants/ojal/gpio.c
@@ -31,18 +31,18 @@ static const struct pad_config gpio_table[] = {
 
 	/* GPP_A08:     M2_GEN4_SSD_RESET_N */
 	PAD_CFG_GPO(GPP_A08, 1, PLTRST),
-	/* GPP_A09:     M.2_WWAN_FCP_OFF_N */
-	PAD_CFG_GPO(GPP_A09, 1, PLTRST),
-	/* GPP_A10:     WWAN_DISABLE_N */
-	PAD_CFG_GPO(GPP_A10, 1, PLTRST),
-	/* GPP_A11:     WLAN_RST_N */
-	PAD_CFG_GPO(GPP_A11, 1, PLTRST),
-	/* GPP_A12:     WIFI_WAKE_N */
-	PAD_CFG_GPI_SCI_LOW(GPP_A12, NONE, DEEP, LEVEL),
-	/* GPP_A13:     PCIE_LNK_DOWN */
-	PAD_CFG_NF_OWNERSHIP(GPP_A13, NONE, DEEP, NF2, ACPI),
-	/* GPP_A15:     CODEC_GPIO_EN */
-	PAD_CFG_GPO(GPP_A15, 1, DEEP),
+	/* GPP_A09:     NC */
+	PAD_NC(GPP_A09, NONE),
+	/* GPP_A10:     NC */
+	PAD_NC(GPP_A10, NONE),
+	/* GPP_A11:     NC */
+	PAD_NC(GPP_A11, NONE),
+	/* GPP_A12:     NC */
+	PAD_NC(GPP_A12, NONE),
+	/* GPP_A13:     TCH_PAD_INT_N */
+	PAD_CFG_GPI_APIC_DRIVER(GPP_A13, NONE, PLTRST, EDGE_SINGLE, INVERT),
+	/* GPP_A15:     NC */
+	PAD_NC(GPP_A15, NONE),
 
 	/* GPP_B */
 	/* GPP_B00:     USBC_SML_CLK_PD */
@@ -57,7 +57,7 @@ static const struct pad_config gpio_table[] = {
 	PAD_NC(GPP_B04, NONE),
 	/* GPP_B06:     SOC_PDB_CTRL */
 	PAD_CFG_GPO(GPP_B06, 0, DEEP),
-	/* GPP_B08:     ISH_GP_4_SNSR_HDR */
+	/* GPP_B08:     NC */
 	PAD_NC(GPP_B08, NONE),
 	/* GPP_B09:     BT_RF_KILL_N */
 	PAD_CFG_GPO(GPP_B09, 1, DEEP),
@@ -69,14 +69,16 @@ static const struct pad_config gpio_table[] = {
 	PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1),
 	/* GPP_B14:     GPP_B14_DDSP_HPDB */
 	PAD_CFG_NF(GPP_B14, NONE, DEEP, NF2),
-	/* GPP_B16:     COINLESS_MODE_SELECT */
-	PAD_CFG_GPI(GPP_B16, NONE, DEEP),
+	/* GPP_B16:     NC */
+	PAD_NC(GPP_B16, NONE),
 	/* GPP_B17:     SPI_TPM_INT_N */
 	PAD_CFG_GPI_APIC_LOCK(GPP_B17, NONE, LEVEL, INVERT, LOCK_CONFIG),
-	/* GPP_B20:     WWAN_RST_N */
+	/* GPP_B20:     SOC_KB_MATRIX */
 	PAD_CFG_GPO(GPP_B20, 1, PLTRST),
 	/* GPP_B21:     TCP_RETIMER_FORCE_PWR */
 	PAD_CFG_GPO(GPP_B21, 0, DEEP),
+	/* GPP_B22:     SOC_CAM_WP */
+	PAD_CFG_GPO(GPP_B22, 0, DEEP),
 	/* GPP_B24:     ESPI_ALERT0_EC_R_N */
 	PAD_NC(GPP_B24, NONE),
 	/* GPP_B25:     None */
@@ -101,18 +103,18 @@ static const struct pad_config gpio_table[] = {
 	PAD_NC(GPP_C07, NONE),
 	/* GPP_C08:     PM_SLP_S0_N_GPP_CNTRL */
 	PAD_CFG_GPO(GPP_C08, 1, PLTRST),
-	/* GPP_C09:     CLKREQ0_X1_GEN4_M2_WLAN_N */
-	PAD_CFG_NF(GPP_C09, NONE, DEEP, NF1),
+	/* GPP_C09:     NC */
+	PAD_NC(GPP_C09, NONE),
 	/* GPP_C10:     WIFI_RF_KILL_N */
 	PAD_CFG_GPO(GPP_C10, 1, DEEP),
-	/* GPP_C11:     CLKREQ2_X4_GEN4_DT_CEM_SLOT1_N */
-	PAD_CFG_NF(GPP_C11, NONE, DEEP, NF1),
+	/* GPP_C11:     NC */
+	PAD_NC(GPP_C11, NONE),
 	/* GPP_C12:     CLKREQ3_X4_GEN4_M2_SSD_N */
 	PAD_CFG_NF(GPP_C12, NONE, DEEP, NF1),
-	/* GPP_C13:     CLKREQ4_X4_GEN4_DT_CEM_SLOT2_N */
-	PAD_CFG_NF(GPP_C13, NONE, DEEP, NF1),
-	/* GPP_C14:     CLKREQ5_X1_GEN1_GBE_LAN_N */
-	PAD_CFG_NF(GPP_C14, NONE, DEEP, NF1),
+	/* GPP_C13:     NC */
+	PAD_NC(GPP_C13, NONE),
+	/* GPP_C14:     NC */
+	PAD_NC(GPP_C14, NONE),
 	/* GPP_C15:     FPS_RST_N */
 	PAD_CFG_GPO_LOCK(GPP_C15, 1, LOCK_CONFIG),
 	/* GPP_C16:     MOD_TCSS1_LS_TX_DDC_SCL */
@@ -129,30 +131,30 @@ static const struct pad_config gpio_table[] = {
 	PAD_CFG_NF(GPP_C23, NONE, DEEP, NF2),
 
 	/* GPP_D */
-	/* GPP_D01:     MOD_TCSS1_TYP_A_VBUS_EN */
-	PAD_CFG_GPO(GPP_D01, 1, DEEP),
+	/* GPP_D01:     NC */
+	PAD_NC(GPP_D01, NONE),
 	/* GPP_D02:     SOC_WP_OD */
 	PAD_CFG_GPO(GPP_D02, 0, DEEP),
-	/* GPP_D03:     X4_SLOT_WAKE_N */
-	PAD_CFG_GPI_SCI_LOW(GPP_D03, NONE, DEEP, LEVEL),
-	/* GPP_D07:     ISH_UART0_RTS_N_SNSR_HDR */
+	/* GPP_D03:     NC */
+	PAD_NC(GPP_D03, NONE),
+	/* GPP_D07:     NC */
 	PAD_NC(GPP_D07, NONE),
-	/* GPP_D08:     ISH_UART0_CTS_N_SNSR_HDR */
+	/* GPP_D08:     NC */
 	PAD_NC(GPP_D08, NONE),
-	/* GPP_D09:     I2S_MCLK_HDR */
-	PAD_CFG_NF(GPP_D09, NONE, DEEP, NF1),
-	/* GPP_D10:     HDA_BCLK (HDR) */
-	PAD_CFG_NF(GPP_D10, NONE, DEEP, NF1),
-	/* GPP_D11:     HDA_SYNC (HDR) */
-	PAD_CFG_NF(GPP_D11, NONE, DEEP, NF1),
-	/* GPP_D12:     HDA_SDO (HDR) */
-	PAD_CFG_NF(GPP_D12, NONE, DEEP, NF1),
-	/* GPP_D13:     HDA_SDI0 (HDR) */
-	PAD_CFG_NF(GPP_D13, NONE, DEEP, NF1),
-	/* GPP_D16:     HDA_RST_N (HDR) */
-	PAD_CFG_NF(GPP_D16, NONE, DEEP, NF1),
-	/* GPP_D17:     HDA_SDI1 (HDR) */
-	PAD_CFG_NF(GPP_D17, NONE, DEEP, NF1),
+	/* GPP_D09:     NC */
+	PAD_NC(GPP_D09, NONE),
+	/* GPP_D10:     NC */
+	PAD_NC(GPP_D10, NONE),
+	/* GPP_D11:     NC */
+	PAD_NC(GPP_D11, NONE),
+	/* GPP_D12:     NONE */
+	PAD_NC(GPP_D12, NONE),
+	/* GPP_D13:     NC */
+	PAD_NC(GPP_D13, NONE),
+	/* GPP_D16:     NC */
+	PAD_NC(GPP_D16, NONE),
+	/* GPP_D17:     NC */
+	PAD_NC(GPP_D17, NONE),
 	/* GPP_D19:     NC */
 	PAD_NC(GPP_D19, NONE),
 	/* GPP_D21:     GPP_D21_UFS_REFCLK_R */
@@ -161,36 +163,36 @@ static const struct pad_config gpio_table[] = {
 	/* GPP_E */
 	/* GPP_E01:     PM_SLP_DRAM_N */
 	PAD_CFG_NF(GPP_E01, NONE, DEEP, NF2),
-	/* GPP_E02:     NC */
+	/* GPP_E02:     VR_ALERT#_R */
 	PAD_NC(GPP_E02, NONE),
-	/* GPP_E03:     X4_DT_PCIE_RST_N */
-	PAD_CFG_GPO(GPP_E03, 1, PLTRST),
-	/* GPP_E05:     GPP_E5_FPS_PWREN */
-	PAD_CFG_GPO(GPP_E05, 1, DEEP),
-	/* GPP_E06:     GPP_E6_PEN_DETECT */
-	PAD_CFG_GPI_TRIG_OWN(GPP_E06, NONE, DEEP, LEVEL, ACPI),
-	/* GPP_E07:     LAN_GPIO_RST_N */
-	PAD_CFG_GPO(GPP_E07, 1, PLTRST),
-	/* GPP_E08:     EC_SOC_INT_ODL */
-	PAD_CFG_GPI(GPP_E08, NONE, DEEP),
+	/* GPP_E03:     NC */
+	PAD_NC(GPP_E03, NONE),
+	/* GPP_E05:     NC */
+	PAD_NC(GPP_E05, NONE),
+	/* GPP_E06:     CAM_PRIVACY */
+	PAD_CFG_GPO(GPP_E06, 1, DEEP),
+	/* GPP_E07:     NC */
+	PAD_NC(GPP_E07, NONE),
+	/* GPP_E08:     NC */
+	PAD_NC(GPP_E08, NONE),
 	/* GPP_E09:     USB_FP_CONN_1_CONN_2_OC0_N */
 	PAD_CFG_NF(GPP_E09, NONE, DEEP, NF1),
-	/* GPP_E10:     M2_UFS_DET_SEL_N */
-	PAD_CFG_GPI(GPP_E10, NONE, DEEP),
-	/* GPP_E11:     THC0_SPI1_CLK_TCH_PNL1 */
-	PAD_CFG_NF(GPP_E11, NONE, DEEP, NF3),
+	/* GPP_E10:     NONE */
+	PAD_NC(GPP_E10, NONE),
+	/* GPP_E11:     NC */
+	PAD_NC(GPP_E11, NONE),
 	/* GPP_E12:     THC_I2C0_SCL_TCH_PNL1 */
 	PAD_CFG_NF(GPP_E12, NONE, DEEP, NF3),
 	/* GPP_E13:     THC_I2C0_SDA_TCH_PNL1 */
 	PAD_CFG_NF(GPP_E13, NONE, DEEP, NF3),
-	/* GPP_E14:     THC0_SPI1_IO_2_TCH_PNL1 */
-	PAD_CFG_NF(GPP_E14, NONE, DEEP, NF3),
-	/* GPP_E15:     THC0_SPI1_IO_3_TCH_PNL1 */
-	PAD_CFG_NF(GPP_E15, NONE, DEEP, NF3),
+	/* GPP_E14:     NC */
+	PAD_NC(GPP_E14, NONE),
+	/* GPP_E15:     NC */
+	PAD_NC(GPP_E15, NONE),
 	/* GPP_E16:     THC0_SPI1_RST_N_TCH_PNL1 */
 	PAD_CFG_NF(GPP_E16, NONE, PLTRST, NF1),
-	/* GPP_E17:     GPP_E17_GSPI0A_CS0 */
-	PAD_CFG_NF(GPP_E17, NONE, DEEP, NF5),
+	/* GPP_E17:     NC */
+	PAD_NC(GPP_E17, NONE),
 	/* GPP_E18:     THC0_SPI1_INT_N_TCH_PNL1 */
 	PAD_CFG_NF(GPP_E18, NONE, DEEP, NF3),
 	/* GPP_E19:     FPS_INT_N */
@@ -215,18 +217,18 @@ static const struct pad_config gpio_table[] = {
 	PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_F04, NONE, DEEP, NF1),
 	/* GPP_F05:     CRF_CLKREQ_R */
 	PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_F05, NONE, DEEP, NF3),
-	/* GPP_F06:     DISC_WLAN_WWAN_COEX3 */
-	PAD_CFG_NF(GPP_F06, NONE, DEEP, NF1),
-	/* GPP_F07:     FUSA_DIAGTEST_EN_HDR */
-	PAD_CFG_NF(GPP_F07, NONE, DEEP, NF2),
+	/* GPP_F06:     NC */
+	PAD_NC(GPP_F06, NONE),
+	/* GPP_F07:     NC */
+	PAD_NC(GPP_F07, NONE),
 	/* GPP_F08:     TCH_PNL1_PWR_EN */
 	PAD_CFG_GPO(GPP_F08, 1, PLTRST),
 	/* GPP_F09:     M2_UFS_RST_N */
 	PAD_CFG_GPO(GPP_F09, 1, DEEP),
-	/* GPP_F10:     X4_PCIE_SLOT1_PWR_EN */
-	PAD_CFG_GPO(GPP_F10, 1, PLTRST),
-	/* GPP_F11:     THC1_SPI2_CLK_TCH_PNL2 */
-	PAD_CFG_NF(GPP_F11, NONE, DEEP, NF11),
+	/* GPP_F10:     SOC_EC_INT */
+	PAD_CFG_GPI_APIC(GPP_F10, NONE, PLTRST, LEVEL, INVERT),
+	/* GPP_F11:     NC */
+	PAD_NC(GPP_F11, NONE),
 	/* GPP_F12:     THC_I2C1_SCL_TCH_PAD */
 	PAD_CFG_NF(GPP_F12, NONE, DEEP, NF8),
 	/* GPP_F13:     THC_I2C1_SDA_TCH_PAD */
@@ -237,10 +239,10 @@ static const struct pad_config gpio_table[] = {
 	PAD_CFG_NF(GPP_F15, NONE, DEEP, NF8),
 	/* GPP_F16:     GPP_F16_GSPI0A_CLK */
 	PAD_CFG_NF(GPP_F16, NONE, DEEP, NF8),
-	/* GPP_F17:     CODEC_IRQ_HDR */
-	PAD_CFG_GPI(GPP_F17, NONE, DEEP),
-	/* GPP_F18:     TCH_PAD_INT_N */
-	PAD_CFG_GPI_APIC_DRIVER(GPP_F18, NONE, PLTRST, EDGE_SINGLE, INVERT),
+	/* GPP_F17:     NC */
+	PAD_NC(GPP_F17, NONE),
+	/* GPP_F18:     GPP_F18_GSPI0A_CS0 */
+	PAD_CFG_NF(GPP_F18, NONE, DEEP, NF8),
 	/* GPP_F19:     NC */
 	PAD_NC(GPP_F19, NONE),
 	/* GPP_F20:     CSE_EARLY_SW */
@@ -257,10 +259,10 @@ static const struct pad_config gpio_table[] = {
 	PAD_CFG_GPO(GPP_H02, 1, PLTRST),
 	/* GPP_H03:     MIC MUTE */
 	PAD_CFG_NF(GPP_H03, NONE, DEEP, NF1),
-	/* GPP_H04:     CNV_MFUART2_RXD */
-	PAD_CFG_NF(GPP_H04, NONE, DEEP, NF1),
-	/* GPP_H05:     CNV_MFUART2_TXD */
-	PAD_CFG_NF(GPP_H05, NONE, DEEP, NF1),
+	/* GPP_H04:     NC */
+	PAD_NC(GPP_H04, NONE),
+	/* GPP_H05:     NC */
+	PAD_NC(GPP_H05, NONE),
 	/* GPP_H06:     I2C3_SCL_AUDIO_HDR */
 	PAD_CFG_NF(GPP_H06, NONE, DEEP, NF1),
 	/* GPP_H07:     I2C3_SDA_AUDIO_HDR */
@@ -269,10 +271,10 @@ static const struct pad_config gpio_table[] = {
 	PAD_CFG_NF(GPP_H08, NONE, DEEP, NF1),
 	/* GPP_H09:     SOC_BIOS_LOG_TTK_UART_TX */
 	PAD_CFG_NF(GPP_H09, NONE, DEEP, NF1),
-	/* GPP_H10:     UART0_BUF_RTS */
-	PAD_CFG_NF(GPP_H10, NONE, DEEP, NF1),
-	/* GPP_H11:     UART0_BUF_CTS */
-	PAD_CFG_NF(GPP_H11, NONE, DEEP, NF1),
+	/* GPP_H10:     NC */
+	PAD_NC(GPP_H10, NONE),
+	/* GPP_H11:     NC */
+	PAD_NC(GPP_H11, NONE),
 	/* GPP_H13:     CPU_C10_GATE_N_R */
 	PAD_CFG_NF(GPP_H13, NONE, DEEP, NF1),
 	/* GPP_H14:     ISH_I3C1_SDA_SNSR_HDR */
@@ -291,28 +293,10 @@ static const struct pad_config gpio_table[] = {
 	PAD_CFG_NF(GPP_H21, NONE, DEEP, NF1),
 	/* GPP_H22:     I2C1_SCL_TTK_CHROME */
 	PAD_CFG_NF(GPP_H22, NONE, DEEP, NF1),
-	/* GPP_H23:     TP */
-	PAD_CFG_NF(GPP_H23, NONE, DEEP, NF1),
-	/* GPP_H24:     TP */
-	PAD_CFG_NF(GPP_H24, NONE, DEEP, NF1),
-
-	/* GPP_S */
-	/* GPP_S00:     SNDW3_CLK_CODEC (HDR) */
-	PAD_CFG_NF(GPP_S00, NONE, DEEP, NF1),
-	/* GPP_S01:     SNDW3_DATA0_CODEC (HDR) */
-	PAD_CFG_NF(GPP_S01, NONE, DEEP, NF1),
-	/* GPP_S02:     SNDW3_DATA1_CODEC (HDR) */
-	PAD_CFG_NF(GPP_S02, NONE, DEEP, NF1),
-	/* GPP_S03:     SNDW3_DATA2_CODEC (HDR) */
-	PAD_CFG_NF(GPP_S03, NONE, DEEP, NF1),
-	/* GPP_S04:     DMIC0_CLK (HDR) */
-	PAD_CFG_NF(GPP_S04, NONE, DEEP, NF5),
-	/* GPP_S05:     DMIC0_DATA (HDR) */
-	PAD_CFG_NF(GPP_S05, NONE, DEEP, NF5),
-	/* GPP_S06:     DMIC1_CLK (HDR) */
-	PAD_CFG_NF(GPP_S06, NONE, DEEP, NF5),
-	/* GPP_S07:     DMIC1_DATA (HDR) */
-	PAD_CFG_NF(GPP_S07, NONE, DEEP, NF5),
+	/* GPP_H23:     NC */
+	PAD_NC(GPP_H23, NONE),
+	/* GPP_H24:     NC */
+	PAD_NC(GPP_H24, NONE),
 
 	/* GPP_V */
 	/* GPP_V00:     PM_BATLOW_N */
@@ -322,7 +306,7 @@ static const struct pad_config gpio_table[] = {
 	/* GPP_V02:     LANWAKE_N_R */
 	PAD_CFG_NF(GPP_V02, NONE, DEEP, NF1),
 	/* GPP_V03:     PWRBTN_MCP_N */
-	PAD_CFG_NF(GPP_V03, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_V03, UP_20K, DEEP, NF1),
 	/* GPP_V04:     PM_SLP_S3_N */
 	PAD_CFG_NF(GPP_V04, NONE, DEEP, NF1),
 	/* GPP_V05:     PM_SLP_S4_N */
@@ -335,8 +319,8 @@ static const struct pad_config gpio_table[] = {
 	PAD_CFG_NF(GPP_V08, NONE, DEEP, NF1),
 	/* GPP_V09:     PM_SLP_S5_N */
 	PAD_CFG_NF(GPP_V09, NONE, DEEP, NF1),
-	/* GPP_V10:     LANPHYPC_R_N */
-	PAD_CFG_NF(GPP_V10, NONE, DEEP, NF1),
+	/* GPP_V10:     NC */
+	PAD_NC(GPP_V10, NONE),
 	/* GPP_V11:     PM_SLP_LAN_N */
 	PAD_CFG_NF(GPP_V11, NONE, DEEP, NF1),
 	/* GPP_V12:     WAKE_N */

From bd933b641e435a9e4f0289e71564db96fd698c9a Mon Sep 17 00:00:00 2001
From: Varun Upadhyay <varun.upadhyay@intel.com>
Date: Mon, 15 Sep 2025 20:20:19 +0530
Subject: [PATCH 2129/3886] mb/google/ocelot/var/ojal: Add overridetree

BUG=b:437459757
TEST=Build ojal board

Change-Id: I24086c6986bf4ba3a1ca4a208b7ce1091b392a07
Signed-off-by: Varun Upadhyay <varun.upadhyay@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89189
Reviewed-by: Usha P <usha.p@intel.com>
Reviewed-by: Pranava Y N <pranavayn@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 .../google/ocelot/variants/ojal/Makefile.mk   |   4 +
 .../google/ocelot/variants/ojal/fw_config.c   | 112 ++++++++
 .../ocelot/variants/ojal/overridetree.cb      | 272 +++++++++++++++++-
 .../google/ocelot/variants/ojal/variant.c     |  36 +++
 4 files changed, 422 insertions(+), 2 deletions(-)
 create mode 100644 src/mainboard/google/ocelot/variants/ojal/fw_config.c
 create mode 100644 src/mainboard/google/ocelot/variants/ojal/variant.c

diff --git a/src/mainboard/google/ocelot/variants/ojal/Makefile.mk b/src/mainboard/google/ocelot/variants/ojal/Makefile.mk
index 4c33dad4db..3fdd4642c0 100644
--- a/src/mainboard/google/ocelot/variants/ojal/Makefile.mk
+++ b/src/mainboard/google/ocelot/variants/ojal/Makefile.mk
@@ -3,4 +3,8 @@
 bootblock-y += gpio.c
 romstage-y += gpio.c
 romstage-y += memory.c
+romstage-$(CONFIG_FW_CONFIG) += fw_config.c
 ramstage-y += gpio.c
+romstage-$(CONFIG_FW_CONFIG) += variant.c
+ramstage-$(CONFIG_FW_CONFIG) += variant.c
+ramstage-$(CONFIG_FW_CONFIG) += fw_config.c
diff --git a/src/mainboard/google/ocelot/variants/ojal/fw_config.c b/src/mainboard/google/ocelot/variants/ojal/fw_config.c
new file mode 100644
index 0000000000..a658e76542
--- /dev/null
+++ b/src/mainboard/google/ocelot/variants/ojal/fw_config.c
@@ -0,0 +1,112 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <baseboard/variants.h>
+#include <console/console.h>
+#include <fw_config.h>
+#include <gpio.h>
+#include <inttypes.h>
+
+/* t: base table; o: override table */
+#define GPIO_PADBASED_OVERRIDE(t, o) gpio_padbased_override(t, o, ARRAY_SIZE(o))
+/* t: table */
+#define GPIO_CONFIGURE_PADS(t) gpio_configure_pads(t, ARRAY_SIZE(t))
+
+static const struct pad_config pre_mem_gen4_ssd_pwr_pads[] = {
+	/* GPP_H18:     GEN4_SSD_PWREN */
+	PAD_CFG_GPO(GPP_H18, 0, PLTRST),
+};
+
+static const struct pad_config gen4_ssd_pads[] = {
+	/* GPP_H18:     GEN4_SSD_PWREN */
+	PAD_CFG_GPO(GPP_H18, 1, PLTRST),
+	/* GPP_A08:     M2_GEN4_SSD_RESET_N */
+	PAD_CFG_GPO(GPP_A08, 1, PLTRST),
+};
+
+static const struct pad_config ufs_enable_pads[] = {
+	/* GPP_D21:     GPP_D21_UFS_REFCLK */
+	PAD_CFG_NF(GPP_D21, NONE, DEEP, NF1),
+};
+
+static const struct pad_config cnvi_enable_pads[] = {
+	/* GPP_B09:     BT_RF_KILL_N */
+	PAD_CFG_GPO(GPP_B09, 1, DEEP),
+	/* GPP_C10:     WIFI_RF_KILL_N */
+	PAD_CFG_GPO(GPP_C10, 1, DEEP),
+	/* GPP_F00:     M.2_CNV_BRI_DT_BT_UART2_RTS_N */
+	PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_F00, NONE, DEEP, NF1),
+	/* GPP_F01:     M.2_CNV_BRI_RSP_BT_UART2_RXD */
+	/* NOTE: IOSSTAGE: 'Ignore' for S0ix */
+	PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_F01, NONE, DEEP, NF1),
+	/* GPP_F02:     M.2_CNV_RGI_DT_BT_UART2_TXD */
+	/* NOTE: IOSSTAGE: 'Ignore' for S0ix */
+	PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_F02, NONE, DEEP, NF1),
+	/* GPP_F03:     M.2_CNV_RGI_RSP_BT_UART2_CTS_N */
+	/* NOTE: IOSSTAGE: 'Ignore' for S0ix */
+	PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_F03, NONE, DEEP, NF1),
+	/* GPP_F04:     CNV_RF_RESET_R_N */
+	/* NOTE: IOSSTAGE: 'Ignore' for S0ix */
+	PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_F04, NONE, DEEP, NF1),
+	/* GPP_F05:     CRF_CLKREQ_R */
+	/* NOTE: IOSSTAGE: 'Ignore' for S0ix */
+	PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_F05, NONE, DEEP, NF3),
+};
+
+static const struct pad_config cnvi_disable_pads[] = {
+	/* GPP_B09:     BT_RF_KILL_N */
+	PAD_NC(GPP_B09, NONE),
+	/* GPP_C10:     WIFI_RF_KILL_N */
+	PAD_NC(GPP_C10, NONE),
+	/* GPP_F00:     M.2_CNV_BRI_DT_BT_UART2_RTS_N */
+	PAD_NC(GPP_F00, NONE),
+	/* GPP_F01:     M.2_CNV_BRI_RSP_BT_UART2_RXD */
+	PAD_NC(GPP_F01, NONE),
+	/* GPP_F02:     M.2_CNV_RGI_DT_BT_UART2_TXD */
+	PAD_NC(GPP_F02, NONE),
+	/* GPP_F03:     M.2_CNV_RGI_RSP_BT_UART2_CTS_N */
+	PAD_NC(GPP_F03, NONE),
+	/* GPP_F04:     CNV_RF_RESET_R_N */
+	PAD_NC(GPP_F04, NONE),
+	/* GPP_F05:     CRF_CLKREQ_R */
+	PAD_NC(GPP_F05, NONE),
+};
+
+void fw_config_configure_pre_mem_gpio(void)
+{
+	if (!fw_config_is_provisioned()) {
+		printk(BIOS_WARNING, "FW_CONFIG is not provisioned, Exiting\n");
+		return;
+	}
+
+	if (fw_config_probe(FW_CONFIG(STORAGE, STORAGE_NVME_GEN4))) {
+		GPIO_CONFIGURE_PADS(pre_mem_gen4_ssd_pwr_pads);
+	} else if (fw_config_probe(FW_CONFIG(STORAGE, STORAGE_UNKNOWN))) {
+		GPIO_CONFIGURE_PADS(pre_mem_gen4_ssd_pwr_pads);
+	}
+}
+
+void fw_config_gpio_padbased_override(struct pad_config *padbased_table)
+{
+	//const struct soc_intel_pantherlake_config *config = config_of_soc();
+
+	if (!fw_config_is_provisioned()) {
+		printk(BIOS_WARNING, "FW_CONFIG is not provisioned, Exiting\n");
+		return;
+	}
+
+	if (fw_config_probe(FW_CONFIG(STORAGE, STORAGE_NVME_GEN4))) {
+		GPIO_PADBASED_OVERRIDE(padbased_table, gen4_ssd_pads);
+	} else if (fw_config_probe(FW_CONFIG(STORAGE, STORAGE_UFS))) {
+		GPIO_PADBASED_OVERRIDE(padbased_table, ufs_enable_pads);
+	} else if (fw_config_probe(FW_CONFIG(STORAGE, STORAGE_UNKNOWN))) {
+		GPIO_PADBASED_OVERRIDE(padbased_table, gen4_ssd_pads);
+		GPIO_PADBASED_OVERRIDE(padbased_table, ufs_enable_pads);
+	}
+
+	if (fw_config_probe(FW_CONFIG(WIFI, WIFI_CNVI_6)) ||
+		fw_config_probe(FW_CONFIG(WIFI, WIFI_CNVI_7))) {
+		GPIO_PADBASED_OVERRIDE(padbased_table, cnvi_enable_pads);
+	} else if (fw_config_probe(FW_CONFIG(WIFI, WIFI_NONE)))  {
+		GPIO_PADBASED_OVERRIDE(padbased_table, cnvi_disable_pads);
+	}
+}
diff --git a/src/mainboard/google/ocelot/variants/ojal/overridetree.cb b/src/mainboard/google/ocelot/variants/ojal/overridetree.cb
index 47cdd94f4b..4394314a24 100644
--- a/src/mainboard/google/ocelot/variants/ojal/overridetree.cb
+++ b/src/mainboard/google/ocelot/variants/ojal/overridetree.cb
@@ -1,5 +1,273 @@
+fw_config
+	field AUDIO 0 1
+		option AUDIO_NONE		0
+		option AUDIO_CS42L43_SNDW	1
+		option AUDIO_ALC256_HDA		2
+	end
+	field WIFI 2 3
+		option WIFI_NONE		0
+		option WIFI_CNVI_6		1
+		option WIFI_CNVI_7		2
+	end
+	field TOUCHPAD 4 5
+		option TOUCHPAD_NONE		0
+		option TOUCHPAD_LPSS_I2C	1
+	end
+	field STORAGE 6 7
+		option STORAGE_UNKNOWN		0
+		option STORAGE_NVME_GEN4	1
+		option STORAGE_UFS		2
+	end
+	field FP 8
+		option FP_ABSENT		0
+		option FP_PRESENT		1
+	end
+	field DISPLAY 9
+		option DISPLAY_ABSENT		0
+		option DISPLAY_PRESENT		1
+	end
+	field ISH 10
+		option ISH_DISABLE		0
+		option ISH_ENABLE		1
+	end
+	field KB 11
+		option KB_ABSENT		0
+		option KB_PRESENT		1
+	end
+end
+
 chip soc/intel/pantherlake
 
-        device domain 0 on
-        end
+	register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Type C port - various configurations - TCP0
+	register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Type C port - various configurations - TCP1
+	register "usb2_ports[2]" = "USB2_PORT_MID(OC0)" # USB3.2 Gen2x1 Type-A Port
+	register "usb2_ports[3]" = "USB2_PORT_MID(OC0)" # USB3.2 Gen2x1 Type-A Port
+	register "usb2_ports[4]" = "USB2_PORT_MID(OC0)" # 2x5 USB2 HDR
+	register "usb2_ports[5]" = "USB2_PORT_MID(OC0)" # 2x5 USB2 HDR
+	register "usb2_ports[6]" = "USB2_PORT_MID(OC0)"
+	register "usb2_ports[7]" = "USB2_PORT_MID(OC0)"
+
+	register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)" # USB 3.2 Gen2 x1 Type-A Con - # 1
+	register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC0)" # USB 3.2 Gen2 x1 Type-A Con - # 2
+
+	register "tcss_ports[0]" = "TCSS_PORT_DEFAULT(OC0)"
+	register "tcss_ports[1]" = "TCSS_PORT_DEFAULT(OC_SKIP)"
+
+	register "tcss_cap_policy[0]" = "TCSS_TYPE_C_PORT_FULL_FUN"
+	register "tcss_cap_policy[1]" = "TCSS_TYPE_C_PORT_FULL_FUN"
+
+	# Enable EDP in PortA & HDMI in Port B
+	register "ddi_port_A_config" = "1"
+	register "ddi_port_B_config" = "1"
+	register "ddi_ports_config" = "{
+		[DDI_PORT_A] = DDI_ENABLE_HPD,
+		[DDI_PORT_B] = DDI_ENABLE_HPD | DDI_ENABLE_DDC,
+	}"
+
+	register "serial_io_i2c_mode" = "{
+		[PchSerialIoIndexI2C0]  = PchSerialIoPci,
+		[PchSerialIoIndexI2C1]  = PchSerialIoPci,
+		[PchSerialIoIndexI2C2]  = PchSerialIoDisabled,
+		[PchSerialIoIndexI2C3]  = PchSerialIoDisabled,
+		[PchSerialIoIndexI2C4]  = PchSerialIoDisabled,
+		[PchSerialIoIndexI2C5]  = PchSerialIoPci,
+	}"
+
+	register "serial_io_gspi_mode" = "{
+		[PchSerialIoIndexGSPI0] = PchSerialIoPci,
+		[PchSerialIoIndexGSPI1] = PchSerialIoDisabled,
+		[PchSerialIoIndexGSPI0A] = PchSerialIoDisabled,
+	}"
+
+	# Intel Common SoC Config
+	#+-------------------+---------------------------+
+	#| Field             |  Value                    |
+	#+-------------------+---------------------------+
+	#| I2C0              | Touchpad                   |
+	#| I2C1              | TPM(cr50)                  |
+	#+-------------------+---------------------------+
+	register "common_soc_config" = "{
+		/* Render OEM footer logo 100px above from the edge */
+		.logo_bottom_margin = 100,
+		.chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT,
+		.i2c[1] = {
+			.speed = I2C_SPEED_FAST,
+			.early_init = 1,
+		},
+		.i2c[5] = {
+			.speed = I2C_SPEED_FAST,
+		},
+	}"
+
+	device domain 0 on
+		device ref igpu on
+			probe DISPLAY DISPLAY_PRESENT
+			chip drivers/gfx/generic
+				register "device_count" = "5"
+				# DDIA for eDP
+				register "device[0].name" = ""LCD0""
+				register "device[0].type" = "panel"
+				# DDIB for HDMI
+				# If HDMI is not enumerated in the kernel, then no GFX device should be added for DDIB
+				register "device[1].name" = ""DD01""
+				# TCP0 (DP-1) for port C0
+				register "device[2].name" = ""DD02""
+				register "device[2].use_pld" = "true"
+				register "device[2].pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(1, 1))"
+				# TCP1 (DP-2) for port C1
+				register "device[3].name" = ""DD03""
+				register "device[3].use_pld" = "true"
+				register "device[3].pld" = "ACPI_PLD_TYPE_C(LEFT, RIGHT, ACPI_PLD_GROUP(2, 1))"
+				device generic 0 on end
+			end
+		end
+
+		device ref iaa off end
+
+		device ref tbt_pcie_rp0 on end
+		device ref tbt_pcie_rp1 on end
+		device ref tcss_xhci on
+			chip drivers/usb/acpi
+				device ref tcss_root_hub on
+					chip drivers/usb/acpi
+						register "desc" = ""USB3 Type-C Port C0""
+						register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
+						register "group" = "ACPI_PLD_GROUP(4, 2)"
+						device ref tcss_usb3_port0 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB3 Type-C Port C1""
+						register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
+						register "group" = "ACPI_PLD_GROUP(3, 2)"
+						device ref tcss_usb3_port1 on end
+					end
+				end
+			end
+		end
+
+		device ref tcss_dma0 on
+			chip drivers/intel/usb4/retimer
+				register "dfp[0].power_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B21)"
+				use tcss_usb3_port0 as dfp[0].typec_port
+				device generic 0 on end
+			end
+			chip drivers/intel/usb4/retimer
+				register "dfp[1].power_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B21)"
+				use tcss_usb3_port1 as dfp[1].typec_port
+				device generic 0 on end
+			end
+		end
+
+		device ref xhci on
+			chip drivers/usb/acpi
+				device ref xhci_root_hub on
+					chip drivers/usb/acpi
+						register "desc" = ""USB2 Type-C Port C0""
+						register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
+						register "group" = "ACPI_PLD_GROUP(1, 1)"
+						device ref usb2_port1 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB2 Type-C Port C1""
+						register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
+						register "group" = "ACPI_PLD_GROUP(2, 1)"
+						device ref usb2_port2 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB2 Type-A Port 1""
+						register "type" = "UPC_TYPE_A"
+						register "group" = "ACPI_PLD_GROUP(3, 1)"
+						device ref usb2_port3 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB2 Type-A Port 2""
+						register "type" = "UPC_TYPE_A"
+						register "group" = "ACPI_PLD_GROUP(4, 1)"
+						device ref usb2_port4 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB2 Type-A Port 3""
+						register "type" = "UPC_TYPE_A"
+						register "group" = "ACPI_PLD_GROUP(5, 1)"
+						device ref usb2_port5 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB2 Type-A Port 4""
+						register "type" = "UPC_TYPE_A"
+						register "group" = "ACPI_PLD_GROUP(6, 1)"
+						device ref usb2_port6 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB2 Type-A Port 5""
+						register "type" = "UPC_TYPE_A"
+						register "group" = "ACPI_PLD_GROUP(7, 1)"
+						device ref usb2_port7 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB3 Type-A Port 1""
+						register "type" = "UPC_TYPE_USB3_A"
+						register "group" = "ACPI_PLD_GROUP(1, 2)"
+						device ref usb3_port1 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB3 Type-A Port 2""
+						register "type" = "UPC_TYPE_USB3_A"
+						register "group" = "ACPI_PLD_GROUP(2, 2)"
+						device ref usb3_port2 on end
+					end
+				end
+			end
+		end
+
+		device ref ufs on
+			probe STORAGE STORAGE_UFS
+			probe STORAGE STORAGE_UNKNOWN
+		end
+
+		device ref pcie_rp1 on
+			probe STORAGE STORAGE_NVME_GEN4
+			probe STORAGE STORAGE_UNKNOWN
+			register "pcie_rp[PCIE_RP(1)]" = "{
+			.clk_src = 3,
+			.clk_req = 3,
+			.flags = PCIE_RP_CLK_REQ_DETECT | PCIE_RP_LTR | PCIE_RP_AER,
+			}"
+			chip soc/intel/common/block/pcie/rtd3
+				register "is_storage" = "true"
+				register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_H18)"
+				register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A08)"
+				register "srcclk_pin" = "3"
+				device generic 0 on end
+			end
+		end # Gen4 M.2 SSD
+
+		device ref cnvi_wifi on
+			probe WIFI WIFI_CNVI_6
+			probe WIFI WIFI_CNVI_7
+			chip drivers/wifi/generic
+				register "wake" = "GPE0_PME_B0"
+				register "add_acpi_dma_property" = "true"
+				register "enable_cnvi_ddr_rfim" = "true"
+				use cnvi_bluetooth as bluetooth_companion
+				device generic 0 on end
+			end
+		end # CNVi
+
+		device ref cnvi_bluetooth on
+			probe WIFI WIFI_CNVI_6
+			probe WIFI WIFI_CNVI_7
+		end
+
+		device ref i2c0 on end
+
+		device ref i2c1 on
+			chip drivers/i2c/tpm
+				register "hid" = ""GOOG0005""
+				register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_B17_IRQ)"
+				device i2c 50 on end
+			end
+		end
+
+		device ref smbus on end
+	end
 end
diff --git a/src/mainboard/google/ocelot/variants/ojal/variant.c b/src/mainboard/google/ocelot/variants/ojal/variant.c
new file mode 100644
index 0000000000..4aa9adeabe
--- /dev/null
+++ b/src/mainboard/google/ocelot/variants/ojal/variant.c
@@ -0,0 +1,36 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <baseboard/variants.h>
+#include <ec/google/chromeec/ec.h>
+#include <fsp/api.h>
+#include <fw_config.h>
+#include <sar.h>
+#include <soc/gpio_soc_defs.h>
+#include <drivers/intel/touch/chip.h>
+
+const char *get_wifi_sar_cbfs_filename(void)
+{
+	return get_wifi_sar_fw_config_filename(FW_CONFIG_FIELD(WIFI));
+}
+
+void variant_update_soc_chip_config(struct soc_intel_pantherlake_config *config)
+{
+	/* CNVi */
+	if (fw_config_probe(FW_CONFIG(WIFI, WIFI_CNVI_6)) ||
+			fw_config_probe(FW_CONFIG(WIFI, WIFI_CNVI_7))) {
+		config->cnvi_wifi_core = true;
+		config->cnvi_bt_core = true;
+	}
+}
+
+void variant_update_soc_memory_init_params(FSPM_UPD *memupd)
+{
+	FSP_M_CONFIG *m_cfg = &memupd->FspmConfig;
+
+	/* HDA Audio */
+	if (fw_config_probe(FW_CONFIG(AUDIO, AUDIO_ALC256_HDA))) {
+		printk(BIOS_INFO, "Overriding HDA SDI lanes.\n");
+		m_cfg->PchHdaSdiEnable[0] = true;
+		m_cfg->PchHdaSdiEnable[1] = false;
+	}
+}

From beb0951c1c56e15ac51adc66ccae3b306bd92e9f Mon Sep 17 00:00:00 2001
From: Varun Upadhyay <varun.upadhyay@intel.com>
Date: Tue, 23 Sep 2025 20:07:33 +0530
Subject: [PATCH 2130/3886] mb/google/ocelot/var/ojal: Update touchpad config

This patch enables ELAN touchpad in devicetree on I2C0 interface and updates FW config for GPIO's according to schematics revision 0.9.
Intel RDC kit no:840138

BUG=b:437459757
TEST=Build ojal board and test trackpad functionality

Change-Id: Idf84165877e98df31f71c8df916637a455ce84dc
Signed-off-by: Varun Upadhyay <varun.upadhyay@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89323
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Pranava Y N <pranavayn@google.com>
---
 .../google/ocelot/variants/ojal/fw_config.c   | 28 ++++++++++++++++
 .../ocelot/variants/ojal/overridetree.cb      | 32 ++++++++++++++-----
 2 files changed, 52 insertions(+), 8 deletions(-)

diff --git a/src/mainboard/google/ocelot/variants/ojal/fw_config.c b/src/mainboard/google/ocelot/variants/ojal/fw_config.c
index a658e76542..d374cf1dba 100644
--- a/src/mainboard/google/ocelot/variants/ojal/fw_config.c
+++ b/src/mainboard/google/ocelot/variants/ojal/fw_config.c
@@ -71,6 +71,28 @@ static const struct pad_config cnvi_disable_pads[] = {
 	PAD_NC(GPP_F05, NONE),
 };
 
+static const struct pad_config touchpad_lpss_i2c_enable_pads[] = {
+	/* GPP_H20:     SOC_I2C_0_SCL */
+	PAD_CFG_NF(GPP_H20, NONE, DEEP, NF1),
+	/* GPP_H19:     SOC_I2C_0_SDA */
+	PAD_CFG_NF(GPP_H19, NONE, DEEP, NF1),
+	/* GPP_A13:     TCH_PAD_INT_N */
+	PAD_CFG_GPI_APIC(GPP_A13, NONE, PLTRST, LEVEL, INVERT),
+	/* GPP_VGPIO3_THC1: THC1_WOT */
+	PAD_NC(GPP_VGPIO3_THC1, NONE),
+};
+
+static const struct pad_config touchpad_i2c_disable_pads[] = {
+	/* GPP_H20:     SOC_I2C_0_SCL */
+	PAD_NC(GPP_H20, NONE),
+	/* GPP_H19:     SOC_I2C_0_SDA */
+	PAD_NC(GPP_H19, NONE),
+	/* GPP_A13:     TCH_PAD_INT_N */
+	PAD_NC(GPP_A13, NONE),
+	/* GPP_VGPIO3_THC1: THC1_WOT */
+	PAD_NC(GPP_VGPIO3_THC1, NONE),
+};
+
 void fw_config_configure_pre_mem_gpio(void)
 {
 	if (!fw_config_is_provisioned()) {
@@ -109,4 +131,10 @@ void fw_config_gpio_padbased_override(struct pad_config *padbased_table)
 	} else if (fw_config_probe(FW_CONFIG(WIFI, WIFI_NONE)))  {
 		GPIO_PADBASED_OVERRIDE(padbased_table, cnvi_disable_pads);
 	}
+
+	if (fw_config_probe(FW_CONFIG(TOUCHPAD, TOUCHPAD_LPSS_I2C))) {
+		GPIO_PADBASED_OVERRIDE(padbased_table, touchpad_lpss_i2c_enable_pads);
+	} else {
+		GPIO_PADBASED_OVERRIDE(padbased_table, touchpad_i2c_disable_pads);
+	}
 }
diff --git a/src/mainboard/google/ocelot/variants/ojal/overridetree.cb b/src/mainboard/google/ocelot/variants/ojal/overridetree.cb
index 4394314a24..bf174848ef 100644
--- a/src/mainboard/google/ocelot/variants/ojal/overridetree.cb
+++ b/src/mainboard/google/ocelot/variants/ojal/overridetree.cb
@@ -56,6 +56,11 @@ chip soc/intel/pantherlake
 	register "tcss_cap_policy[0]" = "TCSS_TYPE_C_PORT_FULL_FUN"
 	register "tcss_cap_policy[1]" = "TCSS_TYPE_C_PORT_FULL_FUN"
 
+	#gpe configuration
+	register "pmc_gpe0_dw0" = "GPP_A"
+	register "pmc_gpe0_dw1" = "GPP_B"
+	register "pmc_gpe0_dw2" = "GPP_E"
+
 	# Enable EDP in PortA & HDMI in Port B
 	register "ddi_port_A_config" = "1"
 	register "ddi_port_B_config" = "1"
@@ -70,7 +75,7 @@ chip soc/intel/pantherlake
 		[PchSerialIoIndexI2C2]  = PchSerialIoDisabled,
 		[PchSerialIoIndexI2C3]  = PchSerialIoDisabled,
 		[PchSerialIoIndexI2C4]  = PchSerialIoDisabled,
-		[PchSerialIoIndexI2C5]  = PchSerialIoPci,
+		[PchSerialIoIndexI2C5]  = PchSerialIoDisabled,
 	}"
 
 	register "serial_io_gspi_mode" = "{
@@ -90,13 +95,13 @@ chip soc/intel/pantherlake
 		/* Render OEM footer logo 100px above from the edge */
 		.logo_bottom_margin = 100,
 		.chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT,
+		.i2c[0] = {
+			.speed = I2C_SPEED_FAST,
+		},
 		.i2c[1] = {
-			.speed = I2C_SPEED_FAST,
-			.early_init = 1,
-		},
-		.i2c[5] = {
-			.speed = I2C_SPEED_FAST,
-		},
+                        .speed = I2C_SPEED_FAST,
+                        .early_init = 1,
+                },
 	}"
 
 	device domain 0 on
@@ -258,7 +263,18 @@ chip soc/intel/pantherlake
 			probe WIFI WIFI_CNVI_7
 		end
 
-		device ref i2c0 on end
+		device ref i2c0 on
+			chip drivers/i2c/generic
+				register "hid" = ""ELAN0000""
+				register "desc" = ""ELAN Touchpad""
+				register "irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_A13_IRQ)"
+				register "wake" = "GPE0_DW0_13"
+				register "detect" = "1"
+				device i2c 15 on
+					probe TOUCHPAD TOUCHPAD_LPSS_I2C
+				end
+			end
+		end
 
 		device ref i2c1 on
 			chip drivers/i2c/tpm

From ec2875e38f0d376375c6ddfcb2fe84b81453d076 Mon Sep 17 00:00:00 2001
From: Varun Upadhyay <varun.upadhyay@intel.com>
Date: Wed, 24 Sep 2025 09:42:15 +0530
Subject: [PATCH 2131/3886] mb/google/ocelot/var/ojal: Enable FPS and update FW
 config

This patch enables fingerprint sensor in devicetree for ojal and updates FW config for GPIO's config according to schematics revision 0.9.
RDC kit no:840138

BUG=b:437459757
TEST=Build ojal board and check dmesg for FPS detection.

Change-Id: I44a24423f4d5b1fc85a5b3bb51f2d6646c82f9dc
Signed-off-by: Varun Upadhyay <varun.upadhyay@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89324
Reviewed-by: Pranava Y N <pranavayn@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 .../google/ocelot/variants/ojal/fw_config.c   | 48 +++++++++++++++++++
 .../ocelot/variants/ojal/overridetree.cb      | 17 +++++++
 2 files changed, 65 insertions(+)

diff --git a/src/mainboard/google/ocelot/variants/ojal/fw_config.c b/src/mainboard/google/ocelot/variants/ojal/fw_config.c
index d374cf1dba..36bc5183a9 100644
--- a/src/mainboard/google/ocelot/variants/ojal/fw_config.c
+++ b/src/mainboard/google/ocelot/variants/ojal/fw_config.c
@@ -93,6 +93,45 @@ static const struct pad_config touchpad_i2c_disable_pads[] = {
 	PAD_NC(GPP_VGPIO3_THC1, NONE),
 };
 
+static const struct pad_config fp_disable_pads[] = {
+	/* GPP_C15:     FPS_RST_N */
+	PAD_NC(GPP_C15, NONE),
+	/* GPP_E19:     FPS_SOC_INT_L */
+	PAD_NC(GPP_E19, NONE),
+	/* GPP_E20:     FPMCU_FW_UPDATE */
+	PAD_NC(GPP_E20, NONE),
+	/* GPP_F14:     GPP_F14_GPSI0A_MOSI */
+	PAD_NC(GPP_F14, NONE),
+	/* GPP_F15:     GPP_F15_GSPI0A_MISO */
+	PAD_NC(GPP_F15, NONE),
+	/* GPP_F16:     GPP_F16_GPSI0A_CLK */
+	PAD_NC(GPP_F16, NONE),
+	/* GPP_F18:     GPP_F18_GSPI0_CS0 */
+	PAD_NC(GPP_F18, NONE),
+};
+
+static const struct pad_config fp_enable_pads[] = {
+	/* GPP_C15:     FPS_RST_N */
+	PAD_CFG_GPO_LOCK(GPP_C15, 1, LOCK_CONFIG),
+	/* GPP_E19:     FPS_SOC_INT_L */
+	PAD_CFG_GPI_IRQ_WAKE(GPP_E19, NONE, PWROK, LEVEL, INVERT),
+	/* GPP_E20:     FPMCU_FW_UPDATE */
+	PAD_CFG_GPO_LOCK(GPP_E20, 0, LOCK_CONFIG),
+	/* GPP_F14:     GPP_F14_GPSI0A_MOSI */
+	PAD_CFG_NF(GPP_F14, NONE, DEEP, NF8),
+	/* GPP_F15:     GPP_F15_GSPI0A_MISO */
+	PAD_CFG_NF(GPP_F15, NONE, DEEP, NF8),
+	/* GPP_F16:     GPP_F16_GPSI0A_CLK */
+	PAD_CFG_NF(GPP_F16, NONE, DEEP, NF8),
+	/* GPP_F18:     GPP_F18_GSPI0_CS0 */
+	PAD_CFG_NF(GPP_F18, NONE, DEEP, NF8),
+};
+
+static const struct pad_config pre_mem_fp_enable_pads[] = {
+	/* GPP_C15:     FPS_RST_N */
+	PAD_CFG_GPO(GPP_C15, 0, DEEP),
+};
+
 void fw_config_configure_pre_mem_gpio(void)
 {
 	if (!fw_config_is_provisioned()) {
@@ -105,6 +144,9 @@ void fw_config_configure_pre_mem_gpio(void)
 	} else if (fw_config_probe(FW_CONFIG(STORAGE, STORAGE_UNKNOWN))) {
 		GPIO_CONFIGURE_PADS(pre_mem_gen4_ssd_pwr_pads);
 	}
+
+	if (fw_config_probe(FW_CONFIG(FP, FP_PRESENT)))
+		GPIO_CONFIGURE_PADS(pre_mem_fp_enable_pads);
 }
 
 void fw_config_gpio_padbased_override(struct pad_config *padbased_table)
@@ -137,4 +179,10 @@ void fw_config_gpio_padbased_override(struct pad_config *padbased_table)
 	} else {
 		GPIO_PADBASED_OVERRIDE(padbased_table, touchpad_i2c_disable_pads);
 	}
+
+	if (fw_config_probe(FW_CONFIG(FP, FP_PRESENT))) {
+		GPIO_PADBASED_OVERRIDE(padbased_table, fp_enable_pads);
+	} else {
+		GPIO_PADBASED_OVERRIDE(padbased_table, fp_disable_pads);
+	}
 }
diff --git a/src/mainboard/google/ocelot/variants/ojal/overridetree.cb b/src/mainboard/google/ocelot/variants/ojal/overridetree.cb
index bf174848ef..641acbf9ea 100644
--- a/src/mainboard/google/ocelot/variants/ojal/overridetree.cb
+++ b/src/mainboard/google/ocelot/variants/ojal/overridetree.cb
@@ -284,6 +284,23 @@ chip soc/intel/pantherlake
 			end
 		end
 
+		device ref gspi0 on
+			chip drivers/spi/acpi
+				register "name" = ""CRFP""
+				register "hid" = "ACPI_DT_NAMESPACE_HID"
+				register "uid" = "1"
+				register "compat_string" = ""google,cros-ec-spi""
+				register "irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_E19_IRQ)"
+				register "wake" = "GPE0_DW2_19"
+				register "has_power_resource" = "true"
+				register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C15)"
+				register "enable_delay_ms" = "3"
+				device spi 0 on
+					probe FP FP_PRESENT
+				end
+			end # FPMCU
+		end
+
 		device ref smbus on end
 	end
 end

From a3e2073591fb8076cbcf6533dfacaa0adb669fb4 Mon Sep 17 00:00:00 2001
From: Kapil Porwal <kapilporwal@google.com>
Date: Sun, 7 Sep 2025 19:37:28 +0530
Subject: [PATCH 2132/3886] lib/vga_gfx: Add API to render text on a bitmap
 buffer

This commit introduces a new library, `vga_gfx`, to handle text
rendering on a VGA planar buffer. The new functionality supports
displaying text with various screen orientations (Normal, Left Up,
Bottom Up, and Right Up).

The key features are:
- A new public API, `render_text_to_bitmap_buffer()`, that takes a
  text string, screen orientation, and buffer as input.
- Automatic text wrapping to fit the screen's effective width,
  considering the specified orientation.
- The `vga_gfx.c` library is conditionally compiled for both
  `romstage` and `ramstage` based on `CONFIG_VGA` and
  `CONFIG_ROMSTAGE_VGA` respectively.
- Text is rendered as a 1-bit-per-pixel bitmap and then cropped
  to its bounding box to optimize the output size.
- The `bootsplash.h` header file is updated with the new API
  prototype and related constants.

This implementation allows for flexible text display, which is
crucial for showing user notifications on devices that may
operate in a rotated display mode.

BUG=b:406725440
TEST=Verify VGA text rotation on Google/Felino.

Change-Id: I80fcf0a3f106a44f8e4ecdeec38f54ff09f86e6f
Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89089
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
---
 src/include/bootsplash.h |  14 ++
 src/lib/Makefile.mk      |   3 +
 src/lib/vga_gfx.c        | 368 +++++++++++++++++++++++++++++++++++++++
 3 files changed, 385 insertions(+)
 create mode 100644 src/lib/vga_gfx.c

diff --git a/src/include/bootsplash.h b/src/include/bootsplash.h
index 841dd50b7b..da51590345 100644
--- a/src/include/bootsplash.h
+++ b/src/include/bootsplash.h
@@ -169,4 +169,18 @@ bool platform_is_low_battery_shutdown_needed(void);
 static inline bool platform_is_low_battery_shutdown_needed(void) { return false; }
 #endif
 
+/*
+ * VGA Mode 12h (640x480 with 16 colors):
+ * As per page 13 of https://www.phatcode.net/res/221/files/vbe20.pdf
+ * "Standard VGA mode numbers are 7 bits wide and presently range from 00h to 13h."
+ * More details: https://wiki.osdev.org/VGA_Hardware#List_of_register_settings
+ */
+#define VGA12_WIDTH		640
+#define VGA12_HEIGHT		480
+#define VGA12_BITMAP_BUFFER_SZ	(VGA12_WIDTH * VGA12_HEIGHT / 8)
+
+void render_text_to_bitmap_buffer(unsigned char *image_bitmap_buffer,
+	enum lb_fb_orientation orientation, const char *text_to_render,
+	int *image_width, int *image_height);
+
 #endif
diff --git a/src/lib/Makefile.mk b/src/lib/Makefile.mk
index d9792dbea4..073d9fbb68 100644
--- a/src/lib/Makefile.mk
+++ b/src/lib/Makefile.mk
@@ -164,6 +164,9 @@ ramstage-$(CONFIG_ACPI_NHLT) += nhlt.c
 ramstage-$(CONFIG_PAYLOAD_FIT_SUPPORT) += fit.c
 ramstage-$(CONFIG_PAYLOAD_FIT_SUPPORT) += fit_payload.c
 
+ramstage-$(CONFIG_VGA) += vga_gfx.c
+romstage-$(CONFIG_ROMSTAGE_VGA) += vga_gfx.c
+
 romstage-$(CONFIG_TIMER_QUEUE) += timer_queue.c
 ramstage-$(CONFIG_TIMER_QUEUE) += timer_queue.c
 
diff --git a/src/lib/vga_gfx.c b/src/lib/vga_gfx.c
new file mode 100644
index 0000000000..9badc1bf8f
--- /dev/null
+++ b/src/lib/vga_gfx.c
@@ -0,0 +1,368 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <bootsplash.h>
+#include <console/console.h>
+#include <limits.h>
+#include <string.h>
+
+#define FONT_WIDTH 8
+#define FONT_HEIGHT 16
+#define FONT_PACK_SIZE 256
+
+#define SPACE_CHAR ' '
+#define NEWLINE_CHAR '\n'
+
+extern const unsigned char vga_font_8x16[FONT_PACK_SIZE][FONT_HEIGHT];
+
+/* Global variables */
+static enum lb_fb_orientation current_orientation;
+static unsigned char *buffer;
+static int buffer_width;
+static int buffer_height;
+
+/*
+ * Sets or clears a single pixel in the bitmap buffer,
+ * considering current screen orientation.
+ * @param x_logical The logical X coordinate of the pixel.
+ * @param y_logical The logical Y coordinate of the pixel.
+ * @param value 1 to set the pixel, 0 to clear it.
+ */
+static void set_pixel(int x_logical, int y_logical, int value)
+{
+	int buffer_x, buffer_y;
+
+	/*
+	 * Transform logical (x_logical, y_logical) to physical
+	 * (buffer_x, buffer_y) based on the current_orientation.
+	 * The physical buffer is always buffer_width x buffer_height.
+	 */
+	switch (current_orientation) {
+	case LB_FB_ORIENTATION_LEFT_UP:
+		/* Logical (x,y) -> Physical (buffer_width-1-y, x) */
+		buffer_x = buffer_width - 1 - y_logical;
+		buffer_y = x_logical;
+		break;
+	case LB_FB_ORIENTATION_BOTTOM_UP:
+		/*
+		 * Logical (x,y) ->
+		 * Physical (buffer_width-1-x, buffer_height-1-y)
+		 */
+		buffer_x = buffer_width - 1 - x_logical;
+		buffer_y = buffer_height - 1 - y_logical;
+		break;
+	case LB_FB_ORIENTATION_RIGHT_UP:
+		/* Logical (x,y) -> Physical (y, buffer_height-1-x) */
+		buffer_x = y_logical;
+		buffer_y = buffer_height - 1 - x_logical;
+		break;
+	case LB_FB_ORIENTATION_NORMAL:
+	default:
+		buffer_x = x_logical;
+		buffer_y = y_logical;
+		break;
+	}
+
+	/* Now, perform bounds checking against the physical buffer */
+	if (buffer_x >= 0 && buffer_x < buffer_width &&
+			buffer_y >= 0 && buffer_y < buffer_height) {
+		/*
+		 * Calculate the byte index
+		 * and bit position within that byte
+		 */
+		int pixel_index = buffer_y * buffer_width + buffer_x;
+		int byte_idx = pixel_index / BITS_PER_BYTE;
+		int bit_pos = (BITS_PER_BYTE - 1) - (pixel_index % BITS_PER_BYTE);
+
+		/* Set or clear the pixel */
+		if (value)
+			buffer[byte_idx] |= (1 << bit_pos);
+		else
+			buffer[byte_idx] &= ~(1 << bit_pos);
+	}
+}
+
+/*
+ * Draws a single character onto the bitmap buffer.
+ * @param x The X coordinate for the top-left corner of the character.
+ * @param y The Y coordinate for the top-left corner of the character.
+ * @param character The character to draw.
+ */
+static void draw_char(int x, int y, char character)
+{
+	const unsigned char *char_bitmap;
+	char_bitmap = vga_font_8x16[(uint8_t)character];
+	if (!char_bitmap)
+		return;
+
+	for (int row = 0; row < FONT_HEIGHT; row++) {
+		unsigned char row_data = char_bitmap[row];
+		for (int col = 0; col < FONT_WIDTH; col++) {
+			if ((row_data >> (FONT_WIDTH - 1 - col)) & 0x01)
+				set_pixel(x + col, y + row, 1);
+		}
+	}
+}
+
+/*
+ * Draws a single line of text onto the bitmap buffer.
+ * This function DOES NOT handle newlines or automatic wrapping.
+ * @param x The X coordinate for the top-left corner of the line.
+ * @param y The Y coordinate for the top-left corner of the line.
+ * @param text The single line string to draw (no newlines).
+ * @param length The length of the string.
+ * @param effective_width The current effective screen width.
+ */
+static void draw_string(int x, int y, const char *text,
+		int length, int effective_width)
+{
+	int current_x = x;
+	for (int i = 0; i < length; i++) {
+		char character = text[i];
+
+		/* Stop drawing if out of logical bounds horizontally */
+		if (current_x + FONT_WIDTH > effective_width)
+			break;
+
+		draw_char(current_x, y, character);
+
+		/* Move to the next character position */
+		current_x += FONT_WIDTH;
+	}
+}
+
+/*
+ * Reads a single raw pixel's value (0 or 1) from the bitmap
+ * buffer.
+ * @param x The X coordinate of the pixel.
+ * @param y The Y coordinate of the pixel.
+ * @return 1 if the pixel is set, 0 if it's clear.
+ */
+static int get_raw_pixel(int x, int y)
+{
+	/* Assuming the coordinates are within bounds */
+
+	/* Calculate bit position for the given coordinates */
+	int pixel_index = y * buffer_width + x;
+	int byte_idx = pixel_index / BITS_PER_BYTE;
+	int bit_pos = (BITS_PER_BYTE - 1) - (pixel_index % BITS_PER_BYTE);
+	return (buffer[byte_idx] >> bit_pos) & 0x01;
+}
+
+/*
+ * Truncates the content of the bitmap buffer in-place, moving
+ * set pixels to the top-left corner and clearing the rest.
+ * Ensures truncated width and height are multiples of 8.
+ * @param truncated_width Output pointer for the new width.
+ * @param truncated_height Output pointer for the new height.
+ */
+static void truncate_bitmap_buffer(
+	int *truncated_width, int *truncated_height)
+{
+	int min_pixel_x = INT_MAX, max_pixel_x = INT_MIN;
+	int min_pixel_y = INT_MAX, max_pixel_y = INT_MIN;
+	bool found_pixel = false;
+
+	/* Validate input params */
+	if (!truncated_width || !truncated_height)
+		return;
+
+	/* Scan the source buffer to find the actual bounding box of
+	 * set pixels
+	 */
+	for (int y = 0; y < buffer_height; y++) {
+		for (int x = 0; x < buffer_width; x++) {
+			if (get_raw_pixel(x, y)) {
+				min_pixel_x = MIN(min_pixel_x, x);
+				max_pixel_x = MAX(max_pixel_x, x);
+				min_pixel_y = MIN(min_pixel_y, y);
+				max_pixel_y = MAX(max_pixel_y, y);
+				found_pixel = true;
+			}
+		}
+	}
+
+	if (!found_pixel) {
+		/* No set pixels found, effectively empty. */
+		memset(buffer, 0, buffer_width * buffer_height / BITS_PER_BYTE);
+		*truncated_width = 0;
+		*truncated_height = 0;
+		printk(BIOS_ERR, "BITMAP: Unable to crop. No pixels\n");
+		return;
+	}
+
+	/*
+	 * The width of the truncated content in pixels, rounded up to
+	 * multiple of FONT_WIDTH.
+	 */
+	int min_byte_x = (min_pixel_x / BITS_PER_BYTE);
+	int max_byte_x = (max_pixel_x / BITS_PER_BYTE);
+	int new_content_width = (max_byte_x - min_byte_x + 1) * BITS_PER_BYTE;
+	new_content_width += FONT_WIDTH - 1;
+	new_content_width /= FONT_WIDTH;
+	new_content_width *= FONT_WIDTH;
+	new_content_width = MIN(new_content_width, buffer_width);
+
+	/*
+	 * The height of the truncated content in pixels, rounded up to
+	 * multiple of FONT_HEIGHT.
+	 */
+	int new_content_height = max_pixel_y - min_pixel_y + 1;
+	new_content_height += FONT_HEIGHT - 1;
+	new_content_height /= FONT_HEIGHT;
+	new_content_height *= FONT_HEIGHT;
+	new_content_height = MIN(new_content_height, buffer_height);
+
+	/* Calculate number of bytes per row */
+	int source_buffer_row_bytes = buffer_width / BITS_PER_BYTE;
+	int new_content_row_bytes = new_content_width / BITS_PER_BYTE;
+
+	/*
+	 * Perform the in-place byte copy (shift)
+	 * We copy bytes from their original location (aligned to
+	 * min_byte_x, min_pixel_y) to the top-left of the buffer
+	 * (0,0).
+	 */
+	for (int y_dest = 0; y_dest < new_content_height; y_dest++) {
+		/* Calculate source byte index */
+		int y_src_pixel = min_pixel_y + y_dest;
+		int src_row_start_byte_idx = y_src_pixel * source_buffer_row_bytes;
+		src_row_start_byte_idx += min_byte_x;
+
+		/* Calculate destination byte index */
+		int dest_row_start_byte_idx = y_dest * new_content_row_bytes;
+
+		/* Ensure we don't read past the end of the source buffer's data */
+		if (y_src_pixel < buffer_height) {
+			memcpy(&buffer[dest_row_start_byte_idx],
+				   &buffer[src_row_start_byte_idx],
+				   new_content_row_bytes);
+		}
+	}
+
+	/* Update the output pointers with the new effective dimensions */
+	*truncated_width = new_content_width;
+	*truncated_height = new_content_height;
+}
+
+/*
+ * Renders the given text onto the bitmap buffer with specified
+ * orientation and centers it.
+ * @param image_bitmap_buffer The 1-bit-per-pixel buffer (will be modified).
+ * @param orientation The screen orientation to apply.
+ * @param text_to_render The text string to render.
+ * @param image_width Image width (will be modified).
+ * @param image_height Image height (will be modified).
+ */
+void render_text_to_bitmap_buffer(unsigned char *image_bitmap_buffer,
+	enum lb_fb_orientation orientation, const char *text_to_render,
+	int *image_width, int *image_height)
+{
+	/* Input validation */
+	if (!image_bitmap_buffer) {
+		printk(BIOS_ERR, "BITMAP: Input buffer is NULL\n");
+		return;
+	}
+
+	if (!text_to_render || !image_width || !image_height) {
+		printk(BIOS_ERR, "BITMAP: Input params are NULL\n");
+		return;
+	}
+
+	printk(BIOS_INFO, "BITMAP: Rendering text - %s\n", text_to_render);
+
+	/* Set global variables to use for all the operations */
+	buffer = image_bitmap_buffer;
+	buffer_width = *image_width;
+	buffer_height = *image_height;
+	current_orientation = orientation;
+
+	/*
+	 * Determine the effective screen dimensions based on
+	 * orientation
+	 */
+	int effective_screen_width;
+	int effective_screen_height;
+	int effective_screen_chars;
+
+	switch (current_orientation) {
+	case LB_FB_ORIENTATION_LEFT_UP:
+	case LB_FB_ORIENTATION_RIGHT_UP:
+		effective_screen_width = buffer_height;
+		effective_screen_height = buffer_width;
+		break;
+	case LB_FB_ORIENTATION_NORMAL:
+	case LB_FB_ORIENTATION_BOTTOM_UP:
+	default:
+		effective_screen_width = buffer_width;
+		effective_screen_height = buffer_height;
+		break;
+	}
+
+	effective_screen_chars = effective_screen_width / FONT_WIDTH;
+
+	memset(buffer, 0, buffer_width * buffer_height / BITS_PER_BYTE);
+
+	int current_line_y = 0;
+	char *line_end = (char *)text_to_render;
+	char *line_start;
+
+	while (*line_end && current_line_y < effective_screen_height) {
+		/* Skip newline and extra space characters */
+		while ((*line_end) &&
+			((*line_end == NEWLINE_CHAR) ||
+			 (*line_end == SPACE_CHAR)))
+			line_end++;
+
+		line_start = line_end;
+
+		/* Find the end of the current word */
+		while (*line_end && *line_end != SPACE_CHAR && *line_end != NEWLINE_CHAR)
+			line_end++;
+
+		/* Handle words longer than the screen width */
+		if (line_end - line_start > effective_screen_chars)
+			line_end = line_start + effective_screen_chars;
+
+		/* Find the optimal line break point without splitting words. */
+		while (*line_end) {
+			char *word_end = line_end + 1;
+			/* Skip leading spaces */
+			while (*word_end && *word_end == SPACE_CHAR)
+				word_end++;
+			/* Find the end of the current word */
+			while (*word_end && *word_end != SPACE_CHAR &&
+				*word_end != NEWLINE_CHAR)
+				word_end++;
+
+			/* Count the word in if it fits into the current line */
+			if (word_end - line_start + 1 > effective_screen_chars)
+				break;
+
+			line_end = word_end;
+		}
+
+		/*
+		 * Consider newline character if it is within
+		 * current line
+		 */
+		char *newline_pos = strchr(line_start, NEWLINE_CHAR);
+		if (newline_pos && (newline_pos < line_end))
+			line_end = newline_pos;
+
+		int line_length = line_end - line_start;
+		if (line_length == 0)
+			continue;
+
+		/* Calculate x-cordinate for the current line */
+		int current_line_x = (effective_screen_width - line_length * FONT_WIDTH) / 2;
+
+		/* Draw the string on the buffer */
+		draw_string(current_line_x, current_line_y, line_start,
+				line_length, effective_screen_width);
+
+		/* Update the y-cordinate for the next line */
+		current_line_y += FONT_HEIGHT;
+	}
+
+	truncate_bitmap_buffer(image_width, image_height);
+}

From 50a59d4464917503847eeeb2df4320c35cf2f6cc Mon Sep 17 00:00:00 2001
From: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Date: Mon, 15 Sep 2025 16:25:21 +0900
Subject: [PATCH 2133/3886] device: Add Kconfig to prepare for reworked verb
 table implementation

Add a new Kconfig which tells the mainboard is using the "legacy" verb
table implementation. This is only needed during the transition towards
the reworked implementation, and will be removed once completed.

The Kconfigs were added manually and not with a script.

Change-Id: I3806cc8df4e244ee6542ad6796ccd9e36de557e5
Signed-off-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89174
Reviewed-by: Erik van den Bogaert <ebogaert@eltan.com>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
---
 src/device/Kconfig                                     | 4 ++++
 src/mainboard/51nb/x210/Kconfig                        | 1 +
 src/mainboard/acer/aspire_vn7_572g/Kconfig             | 1 +
 src/mainboard/acer/g43t-am3/Kconfig                    | 1 +
 src/mainboard/amd/bilby/Kconfig                        | 1 +
 src/mainboard/amd/mandolin/Kconfig                     | 1 +
 src/mainboard/amd/pademelon/Kconfig                    | 1 +
 src/mainboard/apple/macbook21/Kconfig                  | 1 +
 src/mainboard/apple/macbookair4_2/Kconfig              | 1 +
 src/mainboard/asrock/b75m-itx/Kconfig                  | 1 +
 src/mainboard/asrock/b75pro3-m/Kconfig                 | 1 +
 src/mainboard/asrock/b85m_pro4/Kconfig                 | 1 +
 src/mainboard/asrock/fatal1ty_z87_professional/Kconfig | 1 +
 src/mainboard/asrock/g41c-gs/Kconfig                   | 1 +
 src/mainboard/asrock/h110m/Kconfig                     | 1 +
 src/mainboard/asrock/h77pro4-m/Kconfig                 | 1 +
 src/mainboard/asrock/h81m-hds/Kconfig                  | 1 +
 src/mainboard/asrock/imb-1222/Kconfig                  | 1 +
 src/mainboard/asrock/z87_extreme3/Kconfig              | 1 +
 src/mainboard/asrock/z87_extreme4/Kconfig              | 1 +
 src/mainboard/asrock/z87_pro4/Kconfig                  | 1 +
 src/mainboard/asrock/z87e-itx/Kconfig                  | 1 +
 src/mainboard/asrock/z87m_extreme4/Kconfig             | 1 +
 src/mainboard/asrock/z87m_oc_formula/Kconfig           | 1 +
 src/mainboard/asrock/z97_extreme6/Kconfig              | 1 +
 src/mainboard/asrock/z97e-itx_ac/Kconfig               | 1 +
 src/mainboard/asus/h61-series/Kconfig                  | 1 +
 src/mainboard/asus/maximus_iv_gene-z/Kconfig           | 1 +
 src/mainboard/asus/p5gc-mx/Kconfig                     | 1 +
 src/mainboard/asus/p5qc/Kconfig                        | 1 +
 src/mainboard/asus/p5ql-em/Kconfig                     | 1 +
 src/mainboard/asus/p5qpl-am/Kconfig                    | 1 +
 src/mainboard/asus/p8x7x-series/Kconfig                | 1 +
 src/mainboard/biostar/th61-itx/Kconfig                 | 1 +
 src/mainboard/clevo/cml-u/Kconfig                      | 1 +
 src/mainboard/clevo/kbl-u/Kconfig                      | 1 +
 src/mainboard/clevo/tgl-u/Kconfig                      | 1 +
 src/mainboard/compulab/intense_pc/Kconfig              | 1 +
 src/mainboard/dell/gm45_latitude/Kconfig               | 1 +
 src/mainboard/dell/haswell_latitude/Kconfig            | 1 +
 src/mainboard/dell/optiplex_3050/Kconfig               | 1 +
 src/mainboard/dell/optiplex_9020/Kconfig               | 1 +
 src/mainboard/dell/snb_ivb_latitude/Kconfig            | 1 +
 src/mainboard/dell/snb_ivb_workstations/Kconfig        | 1 +
 src/mainboard/dell/xps_8300/Kconfig                    | 1 +
 src/mainboard/emulation/qemu-q35/Kconfig               | 1 +
 src/mainboard/erying/tgl/Kconfig                       | 1 +
 src/mainboard/facebook/fbg1701/Kconfig                 | 1 +
 src/mainboard/foxconn/d41s/Kconfig                     | 1 +
 src/mainboard/foxconn/g41s-k/Kconfig                   | 1 +
 src/mainboard/getac/p470/Kconfig                       | 1 +
 src/mainboard/gigabyte/ga-945gcm-s2l/Kconfig           | 1 +
 src/mainboard/gigabyte/ga-b75m-d3h/Kconfig             | 1 +
 src/mainboard/gigabyte/ga-d510ud/Kconfig               | 1 +
 src/mainboard/gigabyte/ga-g41m-es2l/Kconfig            | 1 +
 src/mainboard/gigabyte/ga-h61m-series/Kconfig          | 1 +
 src/mainboard/gigabyte/ga-h77m-d3h/Kconfig             | 1 +
 src/mainboard/gigabyte/ga-h81m-d2w/Kconfig             | 1 +
 src/mainboard/google/auron/Kconfig                     | 1 +
 src/mainboard/google/beltino/Kconfig                   | 1 +
 src/mainboard/google/brox/Kconfig                      | 1 +
 src/mainboard/google/brya/Kconfig                      | 1 +
 src/mainboard/google/butterfly/Kconfig                 | 1 +
 src/mainboard/google/drallion/Kconfig                  | 1 +
 src/mainboard/google/fatcat/Kconfig                    | 1 +
 src/mainboard/google/jecht/Kconfig                     | 1 +
 src/mainboard/google/link/Kconfig                      | 1 +
 src/mainboard/google/ocelot/Kconfig                    | 1 +
 src/mainboard/google/parrot/Kconfig                    | 1 +
 src/mainboard/google/sarien/Kconfig                    | 1 +
 src/mainboard/google/slippy/Kconfig                    | 1 +
 src/mainboard/google/stout/Kconfig                     | 1 +
 src/mainboard/hardkernel/odroid-h4/Kconfig             | 1 +
 src/mainboard/hp/260_g1_dm/Kconfig                     | 1 +
 src/mainboard/hp/280_g2/Kconfig                        | 1 +
 src/mainboard/hp/elitebook_820_g2/Kconfig              | 1 +
 src/mainboard/hp/folio_9480m/Kconfig                   | 1 +
 src/mainboard/hp/pro_3x00_series/Kconfig               | 1 +
 src/mainboard/hp/prodesk_600_g1_sff/Kconfig            | 1 +
 src/mainboard/hp/snb_ivb_desktops/Kconfig              | 1 +
 src/mainboard/hp/snb_ivb_laptops/Kconfig               | 1 +
 src/mainboard/ibase/mb899/Kconfig                      | 1 +
 src/mainboard/intel/baskingridge/Kconfig               | 1 +
 src/mainboard/intel/coffeelake_rvp/Kconfig             | 1 +
 src/mainboard/intel/d510mo/Kconfig                     | 1 +
 src/mainboard/intel/d945gclf/Kconfig                   | 1 +
 src/mainboard/intel/dcp847ske/Kconfig                  | 1 +
 src/mainboard/intel/dg41wv/Kconfig                     | 1 +
 src/mainboard/intel/dg43gt/Kconfig                     | 1 +
 src/mainboard/intel/dq67sw/Kconfig                     | 1 +
 src/mainboard/intel/emeraldlake2/Kconfig               | 1 +
 src/mainboard/intel/kblrvp/Kconfig                     | 1 +
 src/mainboard/intel/ptlrvp/Kconfig                     | 1 +
 src/mainboard/intel/wtm2/Kconfig                       | 1 +
 src/mainboard/kontron/986lcd-m/Kconfig                 | 1 +
 src/mainboard/kontron/ktqm77/Kconfig                   | 1 +
 src/mainboard/lenovo/haswell/Kconfig                   | 1 +
 src/mainboard/lenovo/l520/Kconfig                      | 1 +
 src/mainboard/lenovo/m900/Kconfig                      | 1 +
 src/mainboard/lenovo/m900_tiny/Kconfig                 | 1 +
 src/mainboard/lenovo/m920q/Kconfig                     | 1 +
 src/mainboard/lenovo/s230u/Kconfig                     | 1 +
 src/mainboard/lenovo/sklkbl_thinkpad/Kconfig           | 1 +
 src/mainboard/lenovo/t400/Kconfig                      | 1 +
 src/mainboard/lenovo/t410/Kconfig                      | 1 +
 src/mainboard/lenovo/t420/Kconfig                      | 1 +
 src/mainboard/lenovo/t420s/Kconfig                     | 1 +
 src/mainboard/lenovo/t430/Kconfig                      | 1 +
 src/mainboard/lenovo/t430s/Kconfig                     | 1 +
 src/mainboard/lenovo/t520/Kconfig                      | 1 +
 src/mainboard/lenovo/t530/Kconfig                      | 1 +
 src/mainboard/lenovo/t60/Kconfig                       | 1 +
 src/mainboard/lenovo/thinkcentre_a58/Kconfig           | 1 +
 src/mainboard/lenovo/thinkcentre_m710s/Kconfig         | 1 +
 src/mainboard/lenovo/x131e/Kconfig                     | 1 +
 src/mainboard/lenovo/x1_carbon_gen1/Kconfig            | 1 +
 src/mainboard/lenovo/x200/Kconfig                      | 1 +
 src/mainboard/lenovo/x201/Kconfig                      | 1 +
 src/mainboard/lenovo/x220/Kconfig                      | 1 +
 src/mainboard/lenovo/x230/Kconfig                      | 1 +
 src/mainboard/lenovo/x60/Kconfig                       | 1 +
 src/mainboard/msi/h81m-p33/Kconfig                     | 1 +
 src/mainboard/msi/ms7707/Kconfig                       | 1 +
 src/mainboard/msi/ms7d25/Kconfig                       | 1 +
 src/mainboard/msi/ms7e06/Kconfig                       | 1 +
 src/mainboard/novacustom/mtl-h/Kconfig                 | 1 +
 src/mainboard/packardbell/ms2290/Kconfig               | 1 +
 src/mainboard/portwell/m107/Kconfig                    | 1 +
 src/mainboard/prodrive/hermes/Kconfig                  | 1 +
 src/mainboard/protectli/vault_adl_p/Kconfig            | 1 +
 src/mainboard/protectli/vault_cml/Kconfig              | 1 +
 src/mainboard/purism/librem_bdw/Kconfig                | 1 +
 src/mainboard/purism/librem_cnl/Kconfig                | 1 +
 src/mainboard/purism/librem_jsl/Kconfig                | 1 +
 src/mainboard/purism/librem_skl/Kconfig                | 1 +
 src/mainboard/razer/blade_stealth_kbl/Kconfig          | 1 +
 src/mainboard/roda/rk886ex/Kconfig                     | 1 +
 src/mainboard/roda/rk9/Kconfig                         | 1 +
 src/mainboard/roda/rv11/Kconfig                        | 1 +
 src/mainboard/samsung/lumpy/Kconfig                    | 1 +
 src/mainboard/samsung/stumpy/Kconfig                   | 1 +
 src/mainboard/sapphire/pureplatinumh61/Kconfig         | 1 +
 src/mainboard/siemens/chili/Kconfig                    | 1 +
 src/mainboard/starlabs/byte_adl/Kconfig                | 1 +
 src/mainboard/starlabs/lite/Kconfig                    | 1 +
 src/mainboard/starlabs/starbook/Kconfig                | 1 +
 src/mainboard/starlabs/starfighter/Kconfig             | 1 +
 src/mainboard/starlabs/starlite_adl/Kconfig            | 1 +
 src/mainboard/supermicro/x10slm-f/Kconfig              | 1 +
 src/mainboard/supermicro/x9sae/Kconfig                 | 1 +
 src/mainboard/supermicro/x9scl/Kconfig                 | 1 +
 src/mainboard/system76/addw1/Kconfig                   | 1 +
 src/mainboard/system76/adl/Kconfig                     | 1 +
 src/mainboard/system76/bonw14/Kconfig                  | 1 +
 src/mainboard/system76/cml-u/Kconfig                   | 1 +
 src/mainboard/system76/gaze15/Kconfig                  | 1 +
 src/mainboard/system76/kbl-u/Kconfig                   | 1 +
 src/mainboard/system76/mtl/Kconfig                     | 1 +
 src/mainboard/system76/oryp5/Kconfig                   | 1 +
 src/mainboard/system76/oryp6/Kconfig                   | 1 +
 src/mainboard/system76/rpl/Kconfig                     | 1 +
 src/mainboard/system76/tgl-h/Kconfig                   | 1 +
 src/mainboard/system76/tgl-u/Kconfig                   | 1 +
 src/mainboard/system76/whl-u/Kconfig                   | 1 +
 src/mainboard/topton/adl/Kconfig                       | 1 +
 165 files changed, 168 insertions(+)

diff --git a/src/device/Kconfig b/src/device/Kconfig
index 1e869521b5..f185ecb4c3 100644
--- a/src/device/Kconfig
+++ b/src/device/Kconfig
@@ -602,6 +602,10 @@ config AZALIA_HDA_CODEC_SUPPORT
 	  mainboard directory to the build which contain the board-specific HD
 	  audio codec configuration.
 
+config AZALIA_USE_LEGACY_VERB_TABLE
+	bool
+	default n
+
 config PCIEXP_PLUGIN_SUPPORT
 	bool
 	default y
diff --git a/src/mainboard/51nb/x210/Kconfig b/src/mainboard/51nb/x210/Kconfig
index a9d18074eb..5f880e01e6 100644
--- a/src/mainboard/51nb/x210/Kconfig
+++ b/src/mainboard/51nb/x210/Kconfig
@@ -4,6 +4,7 @@ if BOARD_51NB_X210
 
 config BOARD_SPECIFIC_OPTIONS
 	def_bool y
+	select AZALIA_USE_LEGACY_VERB_TABLE
 	select BOARD_ROMSIZE_KB_8192
 	select EC_51NB_NPCE985LA0DX
 	select HAVE_ACPI_RESUME
diff --git a/src/mainboard/acer/aspire_vn7_572g/Kconfig b/src/mainboard/acer/aspire_vn7_572g/Kconfig
index cee7b7ec0a..166b9435af 100644
--- a/src/mainboard/acer/aspire_vn7_572g/Kconfig
+++ b/src/mainboard/acer/aspire_vn7_572g/Kconfig
@@ -4,6 +4,7 @@ if BOARD_ACER_VN7_572G
 
 config BOARD_SPECIFIC_OPTIONS
 	def_bool y
+	select AZALIA_USE_LEGACY_VERB_TABLE
 	select BOARD_ROMSIZE_KB_8192
 	select DRIVERS_I2C_HID
 	select DRIVERS_USB_ACPI
diff --git a/src/mainboard/acer/g43t-am3/Kconfig b/src/mainboard/acer/g43t-am3/Kconfig
index 77ce9d4ca1..466c5b9bf4 100644
--- a/src/mainboard/acer/g43t-am3/Kconfig
+++ b/src/mainboard/acer/g43t-am3/Kconfig
@@ -4,6 +4,7 @@ if BOARD_ACER_G43T_AM3 || BOARD_ACER_Q45T_AM
 
 config BOARD_SPECIFIC_OPTIONS
 	def_bool y
+	select AZALIA_USE_LEGACY_VERB_TABLE
 	select CPU_INTEL_SOCKET_LGA775
 	select NORTHBRIDGE_INTEL_X4X
 	select SOUTHBRIDGE_INTEL_I82801JX
diff --git a/src/mainboard/amd/bilby/Kconfig b/src/mainboard/amd/bilby/Kconfig
index 95732046b0..be80b70c27 100644
--- a/src/mainboard/amd/bilby/Kconfig
+++ b/src/mainboard/amd/bilby/Kconfig
@@ -4,6 +4,7 @@ if BOARD_AMD_BILBY
 
 config BOARD_SPECIFIC_OPTIONS
 	def_bool y
+	select AZALIA_USE_LEGACY_VERB_TABLE
 	select SOC_AMD_PICASSO
 	select BOARD_ROMSIZE_KB_16384
 	select AZALIA_HDA_CODEC_SUPPORT
diff --git a/src/mainboard/amd/mandolin/Kconfig b/src/mainboard/amd/mandolin/Kconfig
index ce3af3ba74..47d8debb68 100644
--- a/src/mainboard/amd/mandolin/Kconfig
+++ b/src/mainboard/amd/mandolin/Kconfig
@@ -4,6 +4,7 @@ if BOARD_AMD_MANDOLIN || BOARD_AMD_CEREME
 
 config BOARD_SPECIFIC_OPTIONS
 	def_bool y
+	select AZALIA_USE_LEGACY_VERB_TABLE
 	select SOC_AMD_COMMON_BLOCK_USE_ESPI
 	select SOC_AMD_PICASSO
 	select BOARD_ROMSIZE_KB_8192 if BOARD_AMD_MANDOLIN
diff --git a/src/mainboard/amd/pademelon/Kconfig b/src/mainboard/amd/pademelon/Kconfig
index b31971d95e..5a06a60bbe 100644
--- a/src/mainboard/amd/pademelon/Kconfig
+++ b/src/mainboard/amd/pademelon/Kconfig
@@ -4,6 +4,7 @@ if BOARD_AMD_PADEMELON
 
 config BOARD_SPECIFIC_OPTIONS
 	def_bool y
+	select AZALIA_USE_LEGACY_VERB_TABLE
 	select SOC_AMD_STONEYRIDGE
 	select AMD_APU_PKG_FP4
 	select BOARD_ROMSIZE_KB_8192
diff --git a/src/mainboard/apple/macbook21/Kconfig b/src/mainboard/apple/macbook21/Kconfig
index 330d8efae2..b8880120db 100644
--- a/src/mainboard/apple/macbook21/Kconfig
+++ b/src/mainboard/apple/macbook21/Kconfig
@@ -4,6 +4,7 @@ if BOARD_APPLE_MACBOOK11 || BOARD_APPLE_MACBOOK21 || BOARD_APPLE_IMAC52
 
 config BOARD_SPECIFIC_OPTIONS
 	def_bool y
+	select AZALIA_USE_LEGACY_VERB_TABLE
 	select SYSTEM_TYPE_LAPTOP
 	select CPU_INTEL_SOCKET_M
 	select NORTHBRIDGE_INTEL_I945
diff --git a/src/mainboard/apple/macbookair4_2/Kconfig b/src/mainboard/apple/macbookair4_2/Kconfig
index 39b14a2487..f340761bb1 100644
--- a/src/mainboard/apple/macbookair4_2/Kconfig
+++ b/src/mainboard/apple/macbookair4_2/Kconfig
@@ -4,6 +4,7 @@ if BOARD_APPLE_MACBOOKAIR4_2
 
 config BOARD_SPECIFIC_OPTIONS
 	def_bool y
+	select AZALIA_USE_LEGACY_VERB_TABLE
 	select BOARD_ROMSIZE_KB_8192
 	select EC_ACPI
 	select HAVE_ACPI_RESUME
diff --git a/src/mainboard/asrock/b75m-itx/Kconfig b/src/mainboard/asrock/b75m-itx/Kconfig
index b882d6b8fc..47634047a2 100644
--- a/src/mainboard/asrock/b75m-itx/Kconfig
+++ b/src/mainboard/asrock/b75m-itx/Kconfig
@@ -4,6 +4,7 @@ if BOARD_ASROCK_B75M_ITX
 
 config BOARD_SPECIFIC_OPTIONS
 	def_bool y
+	select AZALIA_USE_LEGACY_VERB_TABLE
 	select BOARD_ROMSIZE_KB_8192
 	select HAVE_ACPI_RESUME
 	select HAVE_ACPI_TABLES
diff --git a/src/mainboard/asrock/b75pro3-m/Kconfig b/src/mainboard/asrock/b75pro3-m/Kconfig
index 17d737f196..f7231c14d9 100644
--- a/src/mainboard/asrock/b75pro3-m/Kconfig
+++ b/src/mainboard/asrock/b75pro3-m/Kconfig
@@ -4,6 +4,7 @@ if BOARD_ASROCK_B75PRO3_M
 
 config BOARD_SPECIFIC_OPTIONS
 	def_bool y
+	select AZALIA_USE_LEGACY_VERB_TABLE
 	select BOARD_ROMSIZE_KB_8192
 	select DRIVERS_ASMEDIA_ASM1061
 	select HAVE_ACPI_RESUME
diff --git a/src/mainboard/asrock/b85m_pro4/Kconfig b/src/mainboard/asrock/b85m_pro4/Kconfig
index 65da20d4e0..883547fdd1 100644
--- a/src/mainboard/asrock/b85m_pro4/Kconfig
+++ b/src/mainboard/asrock/b85m_pro4/Kconfig
@@ -4,6 +4,7 @@ if BOARD_ASROCK_B85M_PRO4
 
 config BOARD_SPECIFIC_OPTIONS
 	def_bool y
+	select AZALIA_USE_LEGACY_VERB_TABLE
 	select BOARD_ROMSIZE_KB_8192
 	select HAVE_ACPI_RESUME
 	select HAVE_ACPI_TABLES
diff --git a/src/mainboard/asrock/fatal1ty_z87_professional/Kconfig b/src/mainboard/asrock/fatal1ty_z87_professional/Kconfig
index 56bdad2d40..0081c11934 100644
--- a/src/mainboard/asrock/fatal1ty_z87_professional/Kconfig
+++ b/src/mainboard/asrock/fatal1ty_z87_professional/Kconfig
@@ -3,6 +3,7 @@ if BOARD_ASROCK_FATAL1TY_Z87_PROFESSIONAL
 
 config BOARD_SPECIFIC_OPTIONS
 	def_bool y
+	select AZALIA_USE_LEGACY_VERB_TABLE
 	select BOARD_ROMSIZE_KB_8192
 	select DRIVERS_ASMEDIA_ASM1061
 	select HAVE_ACPI_RESUME
diff --git a/src/mainboard/asrock/g41c-gs/Kconfig b/src/mainboard/asrock/g41c-gs/Kconfig
index 7ae84614a2..11f7d4f1a9 100644
--- a/src/mainboard/asrock/g41c-gs/Kconfig
+++ b/src/mainboard/asrock/g41c-gs/Kconfig
@@ -6,6 +6,7 @@ if BOARD_ASROCK_G41C_GS || BOARD_ASROCK_G41C_GS_R2_0 || \
 
 config BOARD_SPECIFIC_OPTIONS
 	def_bool y
+	select AZALIA_USE_LEGACY_VERB_TABLE
 	select CPU_INTEL_SOCKET_LGA775
 	select NORTHBRIDGE_INTEL_X4X
 	select SOUTHBRIDGE_INTEL_I82801GX
diff --git a/src/mainboard/asrock/h110m/Kconfig b/src/mainboard/asrock/h110m/Kconfig
index a470b6628d..344831f03a 100644
--- a/src/mainboard/asrock/h110m/Kconfig
+++ b/src/mainboard/asrock/h110m/Kconfig
@@ -4,6 +4,7 @@ if BOARD_ASROCK_H110M_DVS
 
 config BOARD_SPECIFIC_OPTIONS
 	def_bool y
+	select AZALIA_USE_LEGACY_VERB_TABLE
 	select BOARD_ROMSIZE_KB_8192
 	select HAVE_ACPI_RESUME
 	select HAVE_ACPI_TABLES
diff --git a/src/mainboard/asrock/h77pro4-m/Kconfig b/src/mainboard/asrock/h77pro4-m/Kconfig
index a9918b5214..ab5d7b706a 100644
--- a/src/mainboard/asrock/h77pro4-m/Kconfig
+++ b/src/mainboard/asrock/h77pro4-m/Kconfig
@@ -4,6 +4,7 @@ if BOARD_ASROCK_H77PRO4_M
 
 config BOARD_SPECIFIC_OPTIONS
 	def_bool y
+	select AZALIA_USE_LEGACY_VERB_TABLE
 	select BOARD_ROMSIZE_KB_8192
 	select DRIVERS_ASMEDIA_ASM1061
 	select HAVE_ACPI_RESUME
diff --git a/src/mainboard/asrock/h81m-hds/Kconfig b/src/mainboard/asrock/h81m-hds/Kconfig
index 4edd2bc387..a3aff28514 100644
--- a/src/mainboard/asrock/h81m-hds/Kconfig
+++ b/src/mainboard/asrock/h81m-hds/Kconfig
@@ -4,6 +4,7 @@ if BOARD_ASROCK_H81M_HDS
 
 config BOARD_SPECIFIC_OPTIONS
 	def_bool y
+	select AZALIA_USE_LEGACY_VERB_TABLE
 	select BOARD_ROMSIZE_KB_4096
 	select HAVE_ACPI_RESUME
 	select HAVE_ACPI_TABLES
diff --git a/src/mainboard/asrock/imb-1222/Kconfig b/src/mainboard/asrock/imb-1222/Kconfig
index 93fe111acd..dc40a3bc4a 100644
--- a/src/mainboard/asrock/imb-1222/Kconfig
+++ b/src/mainboard/asrock/imb-1222/Kconfig
@@ -4,6 +4,7 @@ if BOARD_ASROCK_IMB_1222
 
 config BOARD_SPECIFIC_OPTIONS
 	def_bool y
+	select AZALIA_USE_LEGACY_VERB_TABLE
 	select BOARD_ROMSIZE_KB_32768
 	select HAVE_ACPI_RESUME
 	select HAVE_ACPI_TABLES
diff --git a/src/mainboard/asrock/z87_extreme3/Kconfig b/src/mainboard/asrock/z87_extreme3/Kconfig
index 0b03123a7d..42d10ccd2e 100644
--- a/src/mainboard/asrock/z87_extreme3/Kconfig
+++ b/src/mainboard/asrock/z87_extreme3/Kconfig
@@ -4,6 +4,7 @@ if BOARD_ASROCK_Z87_EXTREME3
 
 config BOARD_SPECIFIC_OPTIONS
 	def_bool y
+	select AZALIA_USE_LEGACY_VERB_TABLE
 	select BOARD_ROMSIZE_KB_8192
 	select HAVE_ACPI_RESUME
 	select HAVE_ACPI_TABLES
diff --git a/src/mainboard/asrock/z87_extreme4/Kconfig b/src/mainboard/asrock/z87_extreme4/Kconfig
index f2a2e7c723..518ddc8b21 100644
--- a/src/mainboard/asrock/z87_extreme4/Kconfig
+++ b/src/mainboard/asrock/z87_extreme4/Kconfig
@@ -4,6 +4,7 @@ if BOARD_ASROCK_Z87_EXTREME4
 
 config BOARD_SPECIFIC_OPTIONS
 	def_bool y
+	select AZALIA_USE_LEGACY_VERB_TABLE
 	select BOARD_ROMSIZE_KB_8192
 	select DRIVERS_ASMEDIA_ASM1061
 	select HAVE_ACPI_RESUME
diff --git a/src/mainboard/asrock/z87_pro4/Kconfig b/src/mainboard/asrock/z87_pro4/Kconfig
index dee318d726..f65674a2b7 100644
--- a/src/mainboard/asrock/z87_pro4/Kconfig
+++ b/src/mainboard/asrock/z87_pro4/Kconfig
@@ -4,6 +4,7 @@ if BOARD_ASROCK_Z87_PRO4
 
 config BOARD_SPECIFIC_OPTIONS
 	def_bool y
+	select AZALIA_USE_LEGACY_VERB_TABLE
 	select BOARD_ROMSIZE_KB_8192
 	select HAVE_ACPI_RESUME
 	select HAVE_ACPI_TABLES
diff --git a/src/mainboard/asrock/z87e-itx/Kconfig b/src/mainboard/asrock/z87e-itx/Kconfig
index 9eebc90e68..3e1b308cf2 100644
--- a/src/mainboard/asrock/z87e-itx/Kconfig
+++ b/src/mainboard/asrock/z87e-itx/Kconfig
@@ -4,6 +4,7 @@ if BOARD_ASROCK_Z87E_ITX
 
 config BOARD_SPECIFIC_OPTIONS
 	def_bool y
+	select AZALIA_USE_LEGACY_VERB_TABLE
 	select BOARD_ROMSIZE_KB_8192
 	select GFX_GMA_ANALOG_I2C_HDMI_B
 	select HAVE_ACPI_RESUME
diff --git a/src/mainboard/asrock/z87m_extreme4/Kconfig b/src/mainboard/asrock/z87m_extreme4/Kconfig
index e02ac39cf0..8b172fb62b 100644
--- a/src/mainboard/asrock/z87m_extreme4/Kconfig
+++ b/src/mainboard/asrock/z87m_extreme4/Kconfig
@@ -4,6 +4,7 @@ if BOARD_ASROCK_Z87M_EXTREME4
 
 config BOARD_SPECIFIC_OPTIONS
 	def_bool y
+	select AZALIA_USE_LEGACY_VERB_TABLE
 	select BOARD_ROMSIZE_KB_8192
 	select HAVE_ACPI_RESUME
 	select HAVE_ACPI_TABLES
diff --git a/src/mainboard/asrock/z87m_oc_formula/Kconfig b/src/mainboard/asrock/z87m_oc_formula/Kconfig
index c05f2fd85a..05f1536c00 100644
--- a/src/mainboard/asrock/z87m_oc_formula/Kconfig
+++ b/src/mainboard/asrock/z87m_oc_formula/Kconfig
@@ -4,6 +4,7 @@ if BOARD_ASROCK_Z87M_OC_FORMULA
 
 config BOARD_SPECIFIC_OPTIONS
 	def_bool y
+	select AZALIA_USE_LEGACY_VERB_TABLE
 	select BOARD_ROMSIZE_KB_8192
 	select HAVE_ACPI_RESUME
 	select HAVE_ACPI_TABLES
diff --git a/src/mainboard/asrock/z97_extreme6/Kconfig b/src/mainboard/asrock/z97_extreme6/Kconfig
index 3cef429d04..2a9162c81e 100644
--- a/src/mainboard/asrock/z97_extreme6/Kconfig
+++ b/src/mainboard/asrock/z97_extreme6/Kconfig
@@ -4,6 +4,7 @@ if BOARD_ASROCK_Z97_EXTREME6
 
 config BOARD_SPECIFIC_OPTIONS
 	def_bool y
+	select AZALIA_USE_LEGACY_VERB_TABLE
 	select BOARD_ROMSIZE_KB_8192
 	select GFX_GMA_ANALOG_I2C_HDMI_B
 	select HAVE_ACPI_RESUME
diff --git a/src/mainboard/asrock/z97e-itx_ac/Kconfig b/src/mainboard/asrock/z97e-itx_ac/Kconfig
index 810bfd0814..7e20680253 100644
--- a/src/mainboard/asrock/z97e-itx_ac/Kconfig
+++ b/src/mainboard/asrock/z97e-itx_ac/Kconfig
@@ -3,6 +3,7 @@ if BOARD_ASROCK_Z97E_ITX_AC
 
 config BOARD_SPECIFIC_OPTIONS
 	def_bool y
+	select AZALIA_USE_LEGACY_VERB_TABLE
 	select BOARD_ROMSIZE_KB_8192
 	select GFX_GMA_ANALOG_I2C_HDMI_B
 	select HAVE_ACPI_RESUME
diff --git a/src/mainboard/asus/h61-series/Kconfig b/src/mainboard/asus/h61-series/Kconfig
index d09ed1e244..6f21b75456 100644
--- a/src/mainboard/asus/h61-series/Kconfig
+++ b/src/mainboard/asus/h61-series/Kconfig
@@ -2,6 +2,7 @@
 
 config BOARD_ASUS_H61_SERIES
 	bool
+	select AZALIA_USE_LEGACY_VERB_TABLE
 	select HAVE_ACPI_RESUME
 	select HAVE_ACPI_TABLES
 	select INTEL_GMA_HAVE_VBT
diff --git a/src/mainboard/asus/maximus_iv_gene-z/Kconfig b/src/mainboard/asus/maximus_iv_gene-z/Kconfig
index b3b081c43b..97a531fd3c 100644
--- a/src/mainboard/asus/maximus_iv_gene-z/Kconfig
+++ b/src/mainboard/asus/maximus_iv_gene-z/Kconfig
@@ -4,6 +4,7 @@ if BOARD_ASUS_MAXIMUS_IV_GENE_Z
 
 config BOARD_SPECIFIC_OPTIONS
 	def_bool y
+	select AZALIA_USE_LEGACY_VERB_TABLE
 	select BOARD_ROMSIZE_KB_8192
 	select HAVE_ACPI_RESUME
 	select HAVE_ACPI_TABLES
diff --git a/src/mainboard/asus/p5gc-mx/Kconfig b/src/mainboard/asus/p5gc-mx/Kconfig
index 4f49dbbaa5..7fc801cc65 100644
--- a/src/mainboard/asus/p5gc-mx/Kconfig
+++ b/src/mainboard/asus/p5gc-mx/Kconfig
@@ -4,6 +4,7 @@ if BOARD_ASUS_P5GC_MX
 
 config BOARD_SPECIFIC_OPTIONS
 	def_bool y
+	select AZALIA_USE_LEGACY_VERB_TABLE
 	select CPU_INTEL_SOCKET_LGA775
 	select NORTHBRIDGE_INTEL_I945
 	select NORTHBRIDGE_INTEL_SUBTYPE_I945GC
diff --git a/src/mainboard/asus/p5qc/Kconfig b/src/mainboard/asus/p5qc/Kconfig
index c501b7a010..d5a2e6ecbd 100644
--- a/src/mainboard/asus/p5qc/Kconfig
+++ b/src/mainboard/asus/p5qc/Kconfig
@@ -4,6 +4,7 @@ if BOARD_ASUS_P5QC || BOARD_ASUS_P5Q_PRO || BOARD_ASUS_P5QL_PRO || BOARD_ASUS_P5
 
 config BOARD_SPECIFIC_OPTIONS
 	def_bool y
+	select AZALIA_USE_LEGACY_VERB_TABLE
 	select CPU_INTEL_SOCKET_LGA775
 	select NORTHBRIDGE_INTEL_X4X
 	select SOUTHBRIDGE_INTEL_I82801JX
diff --git a/src/mainboard/asus/p5ql-em/Kconfig b/src/mainboard/asus/p5ql-em/Kconfig
index 52ad800940..f297d2974d 100644
--- a/src/mainboard/asus/p5ql-em/Kconfig
+++ b/src/mainboard/asus/p5ql-em/Kconfig
@@ -4,6 +4,7 @@ if BOARD_ASUS_P5QL_EM
 
 config BOARD_SPECIFIC_OPTIONS
 	def_bool y
+	select AZALIA_USE_LEGACY_VERB_TABLE
 	select CPU_INTEL_SOCKET_LGA775
 	select NORTHBRIDGE_INTEL_X4X
 	select SOUTHBRIDGE_INTEL_I82801JX
diff --git a/src/mainboard/asus/p5qpl-am/Kconfig b/src/mainboard/asus/p5qpl-am/Kconfig
index 2359e324d8..aeafb4be4f 100644
--- a/src/mainboard/asus/p5qpl-am/Kconfig
+++ b/src/mainboard/asus/p5qpl-am/Kconfig
@@ -4,6 +4,7 @@ if BOARD_ASUS_P5QPL_AM || BOARD_ASUS_P5G41T_M_LX
 
 config BOARD_SPECIFIC_OPTIONS
 	def_bool y
+	select AZALIA_USE_LEGACY_VERB_TABLE
 	select CPU_INTEL_SOCKET_LGA775
 	select NORTHBRIDGE_INTEL_X4X
 	select SOUTHBRIDGE_INTEL_I82801GX
diff --git a/src/mainboard/asus/p8x7x-series/Kconfig b/src/mainboard/asus/p8x7x-series/Kconfig
index cfff67a0dc..6f1632e4be 100644
--- a/src/mainboard/asus/p8x7x-series/Kconfig
+++ b/src/mainboard/asus/p8x7x-series/Kconfig
@@ -2,6 +2,7 @@
 
 config BOARD_ASUS_P8X7X_SERIES
 	bool
+	select AZALIA_USE_LEGACY_VERB_TABLE
 	select HAVE_ACPI_RESUME
 	select HAVE_ACPI_TABLES
 	select HAVE_CMOS_DEFAULT
diff --git a/src/mainboard/biostar/th61-itx/Kconfig b/src/mainboard/biostar/th61-itx/Kconfig
index 43f07ff1c2..450d7dd558 100644
--- a/src/mainboard/biostar/th61-itx/Kconfig
+++ b/src/mainboard/biostar/th61-itx/Kconfig
@@ -4,6 +4,7 @@ if BOARD_BIOSTAR_TH61_ITX
 
 config BOARD_SPECIFIC_OPTIONS
 	def_bool y
+	select AZALIA_USE_LEGACY_VERB_TABLE
 	select BOARD_ROMSIZE_KB_4096
 	select HAVE_ACPI_RESUME
 	select HAVE_ACPI_TABLES
diff --git a/src/mainboard/clevo/cml-u/Kconfig b/src/mainboard/clevo/cml-u/Kconfig
index 5961b68cb4..0bf9807865 100644
--- a/src/mainboard/clevo/cml-u/Kconfig
+++ b/src/mainboard/clevo/cml-u/Kconfig
@@ -2,6 +2,7 @@
 
 config BOARD_CLEVO_CMLU_COMMON
 	def_bool n
+	select AZALIA_USE_LEGACY_VERB_TABLE
 	select BOARD_ROMSIZE_KB_16384
 	select DRIVERS_I2C_HID
 	select HAVE_ACPI_RESUME
diff --git a/src/mainboard/clevo/kbl-u/Kconfig b/src/mainboard/clevo/kbl-u/Kconfig
index 8de8be2c1f..dc2940ec3d 100644
--- a/src/mainboard/clevo/kbl-u/Kconfig
+++ b/src/mainboard/clevo/kbl-u/Kconfig
@@ -2,6 +2,7 @@
 
 config BOARD_CLEVO_KBLU_COMMON
 	def_bool n
+	select AZALIA_USE_LEGACY_VERB_TABLE
 	select BOARD_ROMSIZE_KB_8192
 	select EC_ACPI
 	select HAVE_ACPI_RESUME
diff --git a/src/mainboard/clevo/tgl-u/Kconfig b/src/mainboard/clevo/tgl-u/Kconfig
index 3ab0e9190f..e5b454c49e 100644
--- a/src/mainboard/clevo/tgl-u/Kconfig
+++ b/src/mainboard/clevo/tgl-u/Kconfig
@@ -2,6 +2,7 @@
 
 config BOARD_CLEVO_TGLU_COMMON
 	def_bool n
+	select AZALIA_USE_LEGACY_VERB_TABLE
 	select BOARD_ROMSIZE_KB_16384
 	select DRIVERS_I2C_HID
 	select DRIVERS_INTEL_PMC
diff --git a/src/mainboard/compulab/intense_pc/Kconfig b/src/mainboard/compulab/intense_pc/Kconfig
index 694b241a94..1aa6bef116 100644
--- a/src/mainboard/compulab/intense_pc/Kconfig
+++ b/src/mainboard/compulab/intense_pc/Kconfig
@@ -4,6 +4,7 @@ if BOARD_COMPULAB_INTENSE_PC
 
 config BOARD_SPECIFIC_OPTIONS
 	def_bool y
+	select AZALIA_USE_LEGACY_VERB_TABLE
 	select BOARD_ROMSIZE_KB_16384
 	select EC_ACPI
 	select HAVE_ACPI_RESUME
diff --git a/src/mainboard/dell/gm45_latitude/Kconfig b/src/mainboard/dell/gm45_latitude/Kconfig
index 98ad18849c..edc79b0d43 100644
--- a/src/mainboard/dell/gm45_latitude/Kconfig
+++ b/src/mainboard/dell/gm45_latitude/Kconfig
@@ -2,6 +2,7 @@
 
 config BOARD_DELL_GM45_LATITUDE_COMMON
 	def_bool n
+	select AZALIA_USE_LEGACY_VERB_TABLE
 	select SYSTEM_TYPE_LAPTOP
 	select CPU_INTEL_SOCKET_P
 	select NORTHBRIDGE_INTEL_GM45
diff --git a/src/mainboard/dell/haswell_latitude/Kconfig b/src/mainboard/dell/haswell_latitude/Kconfig
index 8ad18fb0b5..5ffd0229e7 100644
--- a/src/mainboard/dell/haswell_latitude/Kconfig
+++ b/src/mainboard/dell/haswell_latitude/Kconfig
@@ -2,6 +2,7 @@
 
 config BOARD_DELL_HASWELL_LATITUDE_COMMON
 	def_bool n
+	select AZALIA_USE_LEGACY_VERB_TABLE
 	select EC_DELL_MEC5035
 	select HAVE_ACPI_RESUME
 	select HAVE_ACPI_TABLES
diff --git a/src/mainboard/dell/optiplex_3050/Kconfig b/src/mainboard/dell/optiplex_3050/Kconfig
index 6c8e72956e..17cd2bee67 100644
--- a/src/mainboard/dell/optiplex_3050/Kconfig
+++ b/src/mainboard/dell/optiplex_3050/Kconfig
@@ -4,6 +4,7 @@ if BOARD_DELL_OPTIPLEX_3050
 
 config BOARD_SPECIFIC_OPTIONS
 	def_bool y
+	select AZALIA_USE_LEGACY_VERB_TABLE
 	select BOARD_ROMSIZE_KB_16384
 	select HAVE_ACPI_RESUME
 	select HAVE_ACPI_TABLES
diff --git a/src/mainboard/dell/optiplex_9020/Kconfig b/src/mainboard/dell/optiplex_9020/Kconfig
index 38c3281e70..cef02bfd6d 100644
--- a/src/mainboard/dell/optiplex_9020/Kconfig
+++ b/src/mainboard/dell/optiplex_9020/Kconfig
@@ -4,6 +4,7 @@ if BOARD_DELL_OPTIPLEX_9020_SFF || BOARD_DELL_OPTIPLEX_9020_MT
 
 config BOARD_SPECIFIC_OPTIONS
 	def_bool y
+	select AZALIA_USE_LEGACY_VERB_TABLE
 	select BOARD_ROMSIZE_KB_12288
 	select HAVE_ACPI_RESUME
 	select HAVE_ACPI_TABLES
diff --git a/src/mainboard/dell/snb_ivb_latitude/Kconfig b/src/mainboard/dell/snb_ivb_latitude/Kconfig
index f6e097930b..10ca0d4d98 100644
--- a/src/mainboard/dell/snb_ivb_latitude/Kconfig
+++ b/src/mainboard/dell/snb_ivb_latitude/Kconfig
@@ -2,6 +2,7 @@
 
 config BOARD_DELL_SNB_IVB_LATITUDE_COMMON
 	def_bool n
+	select AZALIA_USE_LEGACY_VERB_TABLE
 	select EC_ACPI
 	select EC_DELL_MEC5035
 	select GFX_GMA_PANEL_1_ON_LVDS
diff --git a/src/mainboard/dell/snb_ivb_workstations/Kconfig b/src/mainboard/dell/snb_ivb_workstations/Kconfig
index a1e446ebe0..0311896477 100644
--- a/src/mainboard/dell/snb_ivb_workstations/Kconfig
+++ b/src/mainboard/dell/snb_ivb_workstations/Kconfig
@@ -2,6 +2,7 @@
 
 config BOARD_DELL_SNB_IVB_WORKSTATIONS
 	def_bool n
+	select AZALIA_USE_LEGACY_VERB_TABLE
 	select BOARD_ROMSIZE_KB_12288
 	select HAVE_ACPI_RESUME
 	select HAVE_ACPI_TABLES
diff --git a/src/mainboard/dell/xps_8300/Kconfig b/src/mainboard/dell/xps_8300/Kconfig
index 09bd4c84cc..5185d738c3 100644
--- a/src/mainboard/dell/xps_8300/Kconfig
+++ b/src/mainboard/dell/xps_8300/Kconfig
@@ -4,6 +4,7 @@ if BOARD_DELL_XPS_8300
 
 config BOARD_SPECIFIC_OPTIONS
 	def_bool y
+	select AZALIA_USE_LEGACY_VERB_TABLE
 	select BOARD_ROMSIZE_KB_4096
 	select HAVE_ACPI_RESUME
 	select HAVE_ACPI_TABLES
diff --git a/src/mainboard/emulation/qemu-q35/Kconfig b/src/mainboard/emulation/qemu-q35/Kconfig
index 854c0533c3..0209e5026d 100644
--- a/src/mainboard/emulation/qemu-q35/Kconfig
+++ b/src/mainboard/emulation/qemu-q35/Kconfig
@@ -4,6 +4,7 @@ if BOARD_EMULATION_QEMU_X86_Q35
 
 config BOARD_SPECIFIC_OPTIONS
 	def_bool y
+	select AZALIA_USE_LEGACY_VERB_TABLE
 	select CPU_QEMU_X86
 	select SOUTHBRIDGE_INTEL_I82801IX
 	select HAVE_CMOS_DEFAULT
diff --git a/src/mainboard/erying/tgl/Kconfig b/src/mainboard/erying/tgl/Kconfig
index e8a2a1fd72..cff5598896 100644
--- a/src/mainboard/erying/tgl/Kconfig
+++ b/src/mainboard/erying/tgl/Kconfig
@@ -4,6 +4,7 @@ if BOARD_ERYING_POLESTAR_G613_PRO
 
 config BOARD_SPECIFIC_OPTIONS
 	def_bool y
+	select AZALIA_USE_LEGACY_VERB_TABLE
 	select BOARD_ROMSIZE_KB_16384
 	select SOC_INTEL_TIGERLAKE
 	select SOC_INTEL_TIGERLAKE_PCH_H
diff --git a/src/mainboard/facebook/fbg1701/Kconfig b/src/mainboard/facebook/fbg1701/Kconfig
index 1ea2ae6056..b498e99560 100644
--- a/src/mainboard/facebook/fbg1701/Kconfig
+++ b/src/mainboard/facebook/fbg1701/Kconfig
@@ -4,6 +4,7 @@ if BOARD_FACEBOOK_FBG1701
 
 config BOARD_SPECIFIC_OPTIONS
 	def_bool y
+	select AZALIA_USE_LEGACY_VERB_TABLE
 	select BOARD_ROMSIZE_KB_8192
 	select DISABLE_ACPI_HIBERNATE
 	select HAVE_ACPI_TABLES
diff --git a/src/mainboard/foxconn/d41s/Kconfig b/src/mainboard/foxconn/d41s/Kconfig
index 6ddc7dffc1..f64ecfb45e 100644
--- a/src/mainboard/foxconn/d41s/Kconfig
+++ b/src/mainboard/foxconn/d41s/Kconfig
@@ -4,6 +4,7 @@ if BOARD_FOXCONN_D41S
 
 config BOARD_SPECIFIC_OPTIONS
 	def_bool y
+	select AZALIA_USE_LEGACY_VERB_TABLE
 	select CPU_INTEL_SOCKET_FCBGA559
 	select NORTHBRIDGE_INTEL_PINEVIEW
 	select SOUTHBRIDGE_INTEL_I82801GX
diff --git a/src/mainboard/foxconn/g41s-k/Kconfig b/src/mainboard/foxconn/g41s-k/Kconfig
index b2237599a4..fffd3b5088 100644
--- a/src/mainboard/foxconn/g41s-k/Kconfig
+++ b/src/mainboard/foxconn/g41s-k/Kconfig
@@ -4,6 +4,7 @@ if BOARD_FOXCONN_G41S_K || BOARD_FOXCONN_G41M
 
 config BOARD_SPECIFIC_OPTIONS
 	def_bool y
+	select AZALIA_USE_LEGACY_VERB_TABLE
 	select CPU_INTEL_SOCKET_LGA775
 	select NORTHBRIDGE_INTEL_X4X
 	select SOUTHBRIDGE_INTEL_I82801GX
diff --git a/src/mainboard/getac/p470/Kconfig b/src/mainboard/getac/p470/Kconfig
index 6af53d85e0..648a277a9b 100644
--- a/src/mainboard/getac/p470/Kconfig
+++ b/src/mainboard/getac/p470/Kconfig
@@ -4,6 +4,7 @@ if BOARD_GETAC_P470
 
 config BOARD_SPECIFIC_OPTIONS
 	def_bool y
+	select AZALIA_USE_LEGACY_VERB_TABLE
 	select SYSTEM_TYPE_LAPTOP
 	select CPU_INTEL_SOCKET_M
 	select NORTHBRIDGE_INTEL_I945
diff --git a/src/mainboard/gigabyte/ga-945gcm-s2l/Kconfig b/src/mainboard/gigabyte/ga-945gcm-s2l/Kconfig
index 4b55c66f11..665b4afbca 100644
--- a/src/mainboard/gigabyte/ga-945gcm-s2l/Kconfig
+++ b/src/mainboard/gigabyte/ga-945gcm-s2l/Kconfig
@@ -4,6 +4,7 @@ if BOARD_GIGABYTE_GA_945GCM_S2L || BOARD_GIGABYTE_GA_945GCM_S2C
 
 config BOARD_SPECIFIC_OPTIONS
 	def_bool y
+	select AZALIA_USE_LEGACY_VERB_TABLE
 	select CPU_INTEL_SOCKET_LGA775
 	select NORTHBRIDGE_INTEL_I945
 	select NORTHBRIDGE_INTEL_SUBTYPE_I945GC
diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/Kconfig b/src/mainboard/gigabyte/ga-b75m-d3h/Kconfig
index 8668cb6811..09fe39bdc4 100644
--- a/src/mainboard/gigabyte/ga-b75m-d3h/Kconfig
+++ b/src/mainboard/gigabyte/ga-b75m-d3h/Kconfig
@@ -4,6 +4,7 @@ if BOARD_GIGABYTE_GA_B75M_D3H || BOARD_GIGABYTE_GA_B75M_D3V || BOARD_GIGABYTE_GA
 
 config BOARD_SPECIFIC_OPTIONS
 	def_bool y
+	select AZALIA_USE_LEGACY_VERB_TABLE
 	select NORTHBRIDGE_INTEL_SANDYBRIDGE
 	select USE_NATIVE_RAMINIT
 	select SOUTHBRIDGE_INTEL_C216
diff --git a/src/mainboard/gigabyte/ga-d510ud/Kconfig b/src/mainboard/gigabyte/ga-d510ud/Kconfig
index 731b9f40ee..1aed988655 100644
--- a/src/mainboard/gigabyte/ga-d510ud/Kconfig
+++ b/src/mainboard/gigabyte/ga-d510ud/Kconfig
@@ -4,6 +4,7 @@ if BOARD_GIGABYTE_GA_D510UD
 
 config BOARD_SPECIFIC_OPTIONS
 	def_bool y
+	select AZALIA_USE_LEGACY_VERB_TABLE
 	select BOARD_ROMSIZE_KB_512
 	select CPU_INTEL_SOCKET_FCBGA559
 	select HAVE_ACPI_RESUME
diff --git a/src/mainboard/gigabyte/ga-g41m-es2l/Kconfig b/src/mainboard/gigabyte/ga-g41m-es2l/Kconfig
index b34717820f..892027f801 100644
--- a/src/mainboard/gigabyte/ga-g41m-es2l/Kconfig
+++ b/src/mainboard/gigabyte/ga-g41m-es2l/Kconfig
@@ -4,6 +4,7 @@ if BOARD_GIGABYTE_GA_G41M_ES2L
 
 config BOARD_SPECIFIC_OPTIONS
 	def_bool y
+	select AZALIA_USE_LEGACY_VERB_TABLE
 	select CPU_INTEL_SOCKET_LGA775
 	select NORTHBRIDGE_INTEL_X4X
 	select SOUTHBRIDGE_INTEL_I82801GX
diff --git a/src/mainboard/gigabyte/ga-h61m-series/Kconfig b/src/mainboard/gigabyte/ga-h61m-series/Kconfig
index 09a06edc7f..cd6ef7526a 100644
--- a/src/mainboard/gigabyte/ga-h61m-series/Kconfig
+++ b/src/mainboard/gigabyte/ga-h61m-series/Kconfig
@@ -2,6 +2,7 @@
 
 config BOARD_GIGABYTE_GA_H61M_SERIES
 	def_bool n
+	select AZALIA_USE_LEGACY_VERB_TABLE
 	select BOARD_ROMSIZE_KB_4096
 	select HAVE_ACPI_RESUME
 	select HAVE_ACPI_TABLES
diff --git a/src/mainboard/gigabyte/ga-h77m-d3h/Kconfig b/src/mainboard/gigabyte/ga-h77m-d3h/Kconfig
index 6d7532a69a..0af3258648 100644
--- a/src/mainboard/gigabyte/ga-h77m-d3h/Kconfig
+++ b/src/mainboard/gigabyte/ga-h77m-d3h/Kconfig
@@ -4,6 +4,7 @@ if BOARD_GIGABYTE_GA_H77M_D3H
 
 config BOARD_SPECIFIC_OPTIONS
 	def_bool y
+	select AZALIA_USE_LEGACY_VERB_TABLE
 	select NORTHBRIDGE_INTEL_SANDYBRIDGE
 	select USE_NATIVE_RAMINIT
 	select SOUTHBRIDGE_INTEL_C216
diff --git a/src/mainboard/gigabyte/ga-h81m-d2w/Kconfig b/src/mainboard/gigabyte/ga-h81m-d2w/Kconfig
index 9b0d7e72d8..cc800d2d3f 100644
--- a/src/mainboard/gigabyte/ga-h81m-d2w/Kconfig
+++ b/src/mainboard/gigabyte/ga-h81m-d2w/Kconfig
@@ -4,6 +4,7 @@ if BOARD_GIGABYTE_GA_H81M_D2W
 
 config BOARD_SPECIFIC_OPTIONS
 	def_bool y
+	select AZALIA_USE_LEGACY_VERB_TABLE
 	select BOARD_ROMSIZE_KB_8192
 	select CPU_INTEL_HASWELL
 	select GFX_GMA_ANALOG_I2C_HDMI_B
diff --git a/src/mainboard/google/auron/Kconfig b/src/mainboard/google/auron/Kconfig
index 2381c797d9..ac77e1a523 100644
--- a/src/mainboard/google/auron/Kconfig
+++ b/src/mainboard/google/auron/Kconfig
@@ -2,6 +2,7 @@
 
 config BOARD_GOOGLE_BASEBOARD_AURON
 	def_bool n
+	select AZALIA_USE_LEGACY_VERB_TABLE
 	select ACPI_GNVS_USB_CHARGECTL
 	select BOARD_ROMSIZE_KB_8192
 	select BROADWELL_LPDDR3 if BOARD_GOOGLE_SAMUS
diff --git a/src/mainboard/google/beltino/Kconfig b/src/mainboard/google/beltino/Kconfig
index 2d5c3e9637..9f061c2aae 100644
--- a/src/mainboard/google/beltino/Kconfig
+++ b/src/mainboard/google/beltino/Kconfig
@@ -2,6 +2,7 @@
 
 config BOARD_GOOGLE_BASEBOARD_BELTINO
 	def_bool n
+	select AZALIA_USE_LEGACY_VERB_TABLE
 	select BOARD_ROMSIZE_KB_8192
 	select DRIVERS_OPTION_CFR_ENABLED if PAYLOAD_EDK2 && SMMSTORE
 	select HAVE_ACPI_RESUME
diff --git a/src/mainboard/google/brox/Kconfig b/src/mainboard/google/brox/Kconfig
index c37ccacb21..da73be5642 100644
--- a/src/mainboard/google/brox/Kconfig
+++ b/src/mainboard/google/brox/Kconfig
@@ -2,6 +2,7 @@
 
 config BOARD_GOOGLE_BROX_COMMON
 	def_bool n
+	select AZALIA_USE_LEGACY_VERB_TABLE
 	select DRIVERS_GENERIC_GPIO_KEYS
 	select DRIVERS_I2C_GENERIC
 	select DRIVERS_I2C_HID
diff --git a/src/mainboard/google/brya/Kconfig b/src/mainboard/google/brya/Kconfig
index f9ee23d8c2..156a9e4a45 100644
--- a/src/mainboard/google/brya/Kconfig
+++ b/src/mainboard/google/brya/Kconfig
@@ -2,6 +2,7 @@
 
 config BOARD_GOOGLE_BRYA_COMMON
 	def_bool n
+	select AZALIA_USE_LEGACY_VERB_TABLE
 	select DRIVERS_GENERIC_ALC1015
 	select DRIVERS_GENERIC_GPIO_KEYS
 	select DRIVERS_GENERIC_MAX98357A
diff --git a/src/mainboard/google/butterfly/Kconfig b/src/mainboard/google/butterfly/Kconfig
index 26ca3c625c..432374bb97 100644
--- a/src/mainboard/google/butterfly/Kconfig
+++ b/src/mainboard/google/butterfly/Kconfig
@@ -4,6 +4,7 @@ if BOARD_GOOGLE_BUTTERFLY
 
 config BOARD_SPECIFIC_OPTIONS
 	def_bool y
+	select AZALIA_USE_LEGACY_VERB_TABLE
 	select ACPI_GNVS_USB_CHARGECTL
 	select BOARD_ROMSIZE_KB_8192
 	select EC_QUANTA_ENE_KB3940Q
diff --git a/src/mainboard/google/drallion/Kconfig b/src/mainboard/google/drallion/Kconfig
index cd14d2c10e..365424f92e 100644
--- a/src/mainboard/google/drallion/Kconfig
+++ b/src/mainboard/google/drallion/Kconfig
@@ -2,6 +2,7 @@
 
 config BOARD_GOOGLE_BASEBOARD_DRALLION
 	def_bool n
+	select AZALIA_USE_LEGACY_VERB_TABLE
 	select BOARD_ROMSIZE_KB_32768
 	select DRIVERS_GFX_GENERIC
 	select DRIVERS_I2C_GENERIC
diff --git a/src/mainboard/google/fatcat/Kconfig b/src/mainboard/google/fatcat/Kconfig
index ff26903a46..f02925916d 100644
--- a/src/mainboard/google/fatcat/Kconfig
+++ b/src/mainboard/google/fatcat/Kconfig
@@ -2,6 +2,7 @@
 
 config BOARD_GOOGLE_FATCAT_COMMON
 	def_bool n
+	select AZALIA_USE_LEGACY_VERB_TABLE
 	select BOARD_ROMSIZE_KB_32768
 	select CPU_INTEL_SOCKET_OTHER
 	select DRIVERS_GFX_GENERIC
diff --git a/src/mainboard/google/jecht/Kconfig b/src/mainboard/google/jecht/Kconfig
index 9122e8750f..0ced2cd61d 100644
--- a/src/mainboard/google/jecht/Kconfig
+++ b/src/mainboard/google/jecht/Kconfig
@@ -2,6 +2,7 @@
 
 config BOARD_GOOGLE_BASEBOARD_JECHT
 	def_bool n
+	select AZALIA_USE_LEGACY_VERB_TABLE
 	select BOARD_ROMSIZE_KB_8192
 	select DRIVERS_OPTION_CFR_ENABLED if PAYLOAD_EDK2 && SMMSTORE
 	select HAVE_ACPI_RESUME
diff --git a/src/mainboard/google/link/Kconfig b/src/mainboard/google/link/Kconfig
index 0f98e1314a..17c41bd8dd 100644
--- a/src/mainboard/google/link/Kconfig
+++ b/src/mainboard/google/link/Kconfig
@@ -4,6 +4,7 @@ if BOARD_GOOGLE_LINK
 
 config BOARD_SPECIFIC_OPTIONS
 	def_bool y
+	select AZALIA_USE_LEGACY_VERB_TABLE
 	select ACPI_GNVS_USB_CHARGECTL
 	select BOARD_ROMSIZE_KB_8192
 	select EC_GOOGLE_CHROMEEC
diff --git a/src/mainboard/google/ocelot/Kconfig b/src/mainboard/google/ocelot/Kconfig
index 9f26a2d8f3..be6a8a6ace 100644
--- a/src/mainboard/google/ocelot/Kconfig
+++ b/src/mainboard/google/ocelot/Kconfig
@@ -2,6 +2,7 @@
 
 config BOARD_GOOGLE_OCELOT_COMMON
 	def_bool n
+	select AZALIA_USE_LEGACY_VERB_TABLE
 	select BOARD_ROMSIZE_KB_32768
 	select CPU_INTEL_SOCKET_OTHER
 	select DRIVERS_GFX_GENERIC
diff --git a/src/mainboard/google/parrot/Kconfig b/src/mainboard/google/parrot/Kconfig
index 19d3bbb055..dc0e8606fe 100644
--- a/src/mainboard/google/parrot/Kconfig
+++ b/src/mainboard/google/parrot/Kconfig
@@ -4,6 +4,7 @@ if BOARD_GOOGLE_PARROT
 
 config BOARD_SPECIFIC_OPTIONS
 	def_bool y
+	select AZALIA_USE_LEGACY_VERB_TABLE
 	select ACPI_GNVS_USB_CHARGECTL
 	select BOARD_ROMSIZE_KB_8192
 	select EC_COMPAL_ENE932
diff --git a/src/mainboard/google/sarien/Kconfig b/src/mainboard/google/sarien/Kconfig
index 666fb8f7f0..d01866bf8a 100644
--- a/src/mainboard/google/sarien/Kconfig
+++ b/src/mainboard/google/sarien/Kconfig
@@ -2,6 +2,7 @@
 
 config BOARD_GOOGLE_BASEBOARD_SARIEN
 	def_bool n
+	select AZALIA_USE_LEGACY_VERB_TABLE
 	select BOARD_ROMSIZE_KB_32768
 	select DRIVERS_GENERIC_BH720
 	select DRIVERS_GFX_GENERIC
diff --git a/src/mainboard/google/slippy/Kconfig b/src/mainboard/google/slippy/Kconfig
index 9ab6f1baa7..08239eb72f 100644
--- a/src/mainboard/google/slippy/Kconfig
+++ b/src/mainboard/google/slippy/Kconfig
@@ -2,6 +2,7 @@
 
 config BOARD_GOOGLE_BASEBOARD_SLIPPY
 	def_bool n
+	select AZALIA_USE_LEGACY_VERB_TABLE
 	select ACPI_GNVS_USB_CHARGECTL
 	select BOARD_ROMSIZE_KB_8192
 	select EC_GOOGLE_CHROMEEC
diff --git a/src/mainboard/google/stout/Kconfig b/src/mainboard/google/stout/Kconfig
index b0f635210b..2c354419d8 100644
--- a/src/mainboard/google/stout/Kconfig
+++ b/src/mainboard/google/stout/Kconfig
@@ -4,6 +4,7 @@ if BOARD_GOOGLE_STOUT
 
 config BOARD_SPECIFIC_OPTIONS
 	def_bool y
+	select AZALIA_USE_LEGACY_VERB_TABLE
 	select ACPI_GNVS_USB_CHARGECTL
 	select BOARD_ROMSIZE_KB_8192
 	select EC_QUANTA_IT8518
diff --git a/src/mainboard/hardkernel/odroid-h4/Kconfig b/src/mainboard/hardkernel/odroid-h4/Kconfig
index 9307ca4e29..8a60b1da30 100644
--- a/src/mainboard/hardkernel/odroid-h4/Kconfig
+++ b/src/mainboard/hardkernel/odroid-h4/Kconfig
@@ -4,6 +4,7 @@ if BOARD_HARDKERNEL_ODROID_H4
 
 config BOARD_SPECIFIC_OPTIONS
 	def_bool y
+	select AZALIA_USE_LEGACY_VERB_TABLE
 	select BOARD_ROMSIZE_KB_16384
 	select CRB_TPM
 	select DRIVERS_UART_8250IO
diff --git a/src/mainboard/hp/260_g1_dm/Kconfig b/src/mainboard/hp/260_g1_dm/Kconfig
index deae64a5a4..5ad4799607 100644
--- a/src/mainboard/hp/260_g1_dm/Kconfig
+++ b/src/mainboard/hp/260_g1_dm/Kconfig
@@ -4,6 +4,7 @@ if BOARD_HP_260_G1_DM
 
 config BOARD_SPECIFIC_OPTIONS
 	def_bool y
+	select AZALIA_USE_LEGACY_VERB_TABLE
 	select BOARD_ROMSIZE_KB_8192
 	select CPU_INTEL_HASWELL
 	select HAVE_ACPI_RESUME
diff --git a/src/mainboard/hp/280_g2/Kconfig b/src/mainboard/hp/280_g2/Kconfig
index 0db753d2cf..acf1f7f58e 100644
--- a/src/mainboard/hp/280_g2/Kconfig
+++ b/src/mainboard/hp/280_g2/Kconfig
@@ -4,6 +4,7 @@ if BOARD_HP_280_G2
 
 config BOARD_SPECIFIC_OPTIONS
 	def_bool y
+	select AZALIA_USE_LEGACY_VERB_TABLE
 	select BOARD_ROMSIZE_KB_8192
 	select HAVE_ACPI_RESUME
 	select HAVE_ACPI_TABLES
diff --git a/src/mainboard/hp/elitebook_820_g2/Kconfig b/src/mainboard/hp/elitebook_820_g2/Kconfig
index 98aed5ca1b..43ffa8be84 100644
--- a/src/mainboard/hp/elitebook_820_g2/Kconfig
+++ b/src/mainboard/hp/elitebook_820_g2/Kconfig
@@ -4,6 +4,7 @@ if BOARD_HP_ELITEBOOK_820_G2
 
 config BOARD_SPECIFIC_OPTIONS
 	def_bool y
+	select AZALIA_USE_LEGACY_VERB_TABLE
 	select BOARD_ROMSIZE_KB_12288
 	select EC_HP_KBC1126
 	select HAVE_ACPI_RESUME
diff --git a/src/mainboard/hp/folio_9480m/Kconfig b/src/mainboard/hp/folio_9480m/Kconfig
index 7d0b62e4ba..d2fe17a8a6 100644
--- a/src/mainboard/hp/folio_9480m/Kconfig
+++ b/src/mainboard/hp/folio_9480m/Kconfig
@@ -4,6 +4,7 @@ if BOARD_HP_FOLIO_9480M
 
 config BOARD_SPECIFIC_OPTIONS
 	def_bool y
+	select AZALIA_USE_LEGACY_VERB_TABLE
 	# The board has a 16MB flash, but the end of the flash needs
 	# to be reserved, so we use 12MB as default
 	select BOARD_ROMSIZE_KB_12288
diff --git a/src/mainboard/hp/pro_3x00_series/Kconfig b/src/mainboard/hp/pro_3x00_series/Kconfig
index 47f24db10d..97754429fe 100644
--- a/src/mainboard/hp/pro_3x00_series/Kconfig
+++ b/src/mainboard/hp/pro_3x00_series/Kconfig
@@ -2,6 +2,7 @@
 
 config BOARD_HP_PRO_3X00_SERIES_COMMON
 	def_bool n
+	select AZALIA_USE_LEGACY_VERB_TABLE
 	select HAVE_ACPI_RESUME
 	select HAVE_ACPI_TABLES
 	select HAVE_CMOS_DEFAULT
diff --git a/src/mainboard/hp/prodesk_600_g1_sff/Kconfig b/src/mainboard/hp/prodesk_600_g1_sff/Kconfig
index 851ecc8ecf..5cdbe41cfd 100644
--- a/src/mainboard/hp/prodesk_600_g1_sff/Kconfig
+++ b/src/mainboard/hp/prodesk_600_g1_sff/Kconfig
@@ -4,6 +4,7 @@ if BOARD_HP_PRODESK_600_G1_SFF
 
 config BOARD_SPECIFIC_OPTIONS
 	def_bool y
+	select AZALIA_USE_LEGACY_VERB_TABLE
 	select BOARD_ROMSIZE_KB_16384
 	select CPU_INTEL_HASWELL
 	select HAVE_ACPI_RESUME
diff --git a/src/mainboard/hp/snb_ivb_desktops/Kconfig b/src/mainboard/hp/snb_ivb_desktops/Kconfig
index 7973d7b3e8..028ee14128 100644
--- a/src/mainboard/hp/snb_ivb_desktops/Kconfig
+++ b/src/mainboard/hp/snb_ivb_desktops/Kconfig
@@ -2,6 +2,7 @@
 
 config BOARD_HP_SNB_IVB_DESKTOPS_COMMON
 	def_bool n
+	select AZALIA_USE_LEGACY_VERB_TABLE
 	select HAVE_ACPI_RESUME
 	select HAVE_ACPI_TABLES
 	select HAVE_CMOS_DEFAULT
diff --git a/src/mainboard/hp/snb_ivb_laptops/Kconfig b/src/mainboard/hp/snb_ivb_laptops/Kconfig
index f180bca87f..7f5c4cee8d 100644
--- a/src/mainboard/hp/snb_ivb_laptops/Kconfig
+++ b/src/mainboard/hp/snb_ivb_laptops/Kconfig
@@ -2,6 +2,7 @@
 
 config BOARD_HP_SNB_IVB_LAPTOPS_COMMON
 	def_bool n
+	select AZALIA_USE_LEGACY_VERB_TABLE
 	select EC_HP_KBC1126
 	select HAVE_ACPI_RESUME
 	select HAVE_ACPI_TABLES
diff --git a/src/mainboard/ibase/mb899/Kconfig b/src/mainboard/ibase/mb899/Kconfig
index 6ef54cb805..0f1fa20e6c 100644
--- a/src/mainboard/ibase/mb899/Kconfig
+++ b/src/mainboard/ibase/mb899/Kconfig
@@ -4,6 +4,7 @@ if BOARD_IBASE_MB899
 
 config BOARD_SPECIFIC_OPTIONS
 	def_bool y
+	select AZALIA_USE_LEGACY_VERB_TABLE
 	select CPU_INTEL_SOCKET_M
 	select NORTHBRIDGE_INTEL_I945
 	select NORTHBRIDGE_INTEL_SUBTYPE_I945GM
diff --git a/src/mainboard/intel/baskingridge/Kconfig b/src/mainboard/intel/baskingridge/Kconfig
index 301d66cffe..a12db043ab 100644
--- a/src/mainboard/intel/baskingridge/Kconfig
+++ b/src/mainboard/intel/baskingridge/Kconfig
@@ -4,6 +4,7 @@ if BOARD_INTEL_BASKING_RIDGE
 
 config BOARD_SPECIFIC_OPTIONS
 	def_bool y
+	select AZALIA_USE_LEGACY_VERB_TABLE
 	select NORTHBRIDGE_INTEL_HASWELL
 	select SOUTHBRIDGE_INTEL_LYNXPOINT
 	select BOARD_ROMSIZE_KB_8192
diff --git a/src/mainboard/intel/coffeelake_rvp/Kconfig b/src/mainboard/intel/coffeelake_rvp/Kconfig
index 6fcfd91e2c..37faac09f2 100644
--- a/src/mainboard/intel/coffeelake_rvp/Kconfig
+++ b/src/mainboard/intel/coffeelake_rvp/Kconfig
@@ -2,6 +2,7 @@
 
 config BOARD_INTEL_COFFEELAKE_RVP_COMMON
 	def_bool n
+	select AZALIA_USE_LEGACY_VERB_TABLE
 	select DRIVERS_GENERIC_MAX98357A
 	select DRIVERS_I2C_DA7219
 	select DRIVERS_I2C_GENERIC
diff --git a/src/mainboard/intel/d510mo/Kconfig b/src/mainboard/intel/d510mo/Kconfig
index 32ea8ce64d..14edbe0228 100644
--- a/src/mainboard/intel/d510mo/Kconfig
+++ b/src/mainboard/intel/d510mo/Kconfig
@@ -4,6 +4,7 @@ if BOARD_INTEL_D510MO
 
 config BOARD_SPECIFIC_OPTIONS
 	def_bool y
+	select AZALIA_USE_LEGACY_VERB_TABLE
 	select CPU_INTEL_SOCKET_FCBGA559
 	select NORTHBRIDGE_INTEL_PINEVIEW
 	select SOUTHBRIDGE_INTEL_I82801GX
diff --git a/src/mainboard/intel/d945gclf/Kconfig b/src/mainboard/intel/d945gclf/Kconfig
index 539e833b7a..74f192162c 100644
--- a/src/mainboard/intel/d945gclf/Kconfig
+++ b/src/mainboard/intel/d945gclf/Kconfig
@@ -4,6 +4,7 @@ if BOARD_INTEL_D945GCLF
 
 config BOARD_SPECIFIC_OPTIONS
 	def_bool y
+	select AZALIA_USE_LEGACY_VERB_TABLE
 	select CPU_INTEL_SOCKET_441
 	select NORTHBRIDGE_INTEL_I945
 	select NORTHBRIDGE_INTEL_SUBTYPE_I945GC
diff --git a/src/mainboard/intel/dcp847ske/Kconfig b/src/mainboard/intel/dcp847ske/Kconfig
index b8aeeb64fa..07e26e8e29 100644
--- a/src/mainboard/intel/dcp847ske/Kconfig
+++ b/src/mainboard/intel/dcp847ske/Kconfig
@@ -4,6 +4,7 @@ if BOARD_INTEL_DCP847SKE
 
 config BOARD_SPECIFIC_OPTIONS
 	def_bool y
+	select AZALIA_USE_LEGACY_VERB_TABLE
 	select BOARD_ROMSIZE_KB_8192
 	select SUPERIO_NUVOTON_NCT6776
 	select HAVE_ACPI_RESUME
diff --git a/src/mainboard/intel/dg41wv/Kconfig b/src/mainboard/intel/dg41wv/Kconfig
index bb201bc76d..f9cbe87373 100644
--- a/src/mainboard/intel/dg41wv/Kconfig
+++ b/src/mainboard/intel/dg41wv/Kconfig
@@ -4,6 +4,7 @@ if BOARD_INTEL_DG41WV
 
 config BOARD_SPECIFIC_OPTIONS
 	def_bool y
+	select AZALIA_USE_LEGACY_VERB_TABLE
 	select CPU_INTEL_SOCKET_LGA775
 	select NORTHBRIDGE_INTEL_X4X
 	select SOUTHBRIDGE_INTEL_I82801GX
diff --git a/src/mainboard/intel/dg43gt/Kconfig b/src/mainboard/intel/dg43gt/Kconfig
index c3c853cdeb..0be75cc279 100644
--- a/src/mainboard/intel/dg43gt/Kconfig
+++ b/src/mainboard/intel/dg43gt/Kconfig
@@ -4,6 +4,7 @@ if BOARD_INTEL_DG43GT
 
 config BOARD_SPECIFIC_OPTIONS
 	def_bool y
+	select AZALIA_USE_LEGACY_VERB_TABLE
 	select CPU_INTEL_SOCKET_LGA775
 	select NORTHBRIDGE_INTEL_X4X
 	select SOUTHBRIDGE_INTEL_I82801JX
diff --git a/src/mainboard/intel/dq67sw/Kconfig b/src/mainboard/intel/dq67sw/Kconfig
index 676f041c14..df45bbac06 100644
--- a/src/mainboard/intel/dq67sw/Kconfig
+++ b/src/mainboard/intel/dq67sw/Kconfig
@@ -4,6 +4,7 @@ if BOARD_INTEL_DQ67SW
 
 config BOARD_SPECIFIC_OPTIONS
 	def_bool y
+	select AZALIA_USE_LEGACY_VERB_TABLE
 	select BOARD_ROMSIZE_KB_8192
 	select GFX_GMA_ANALOG_I2C_HDMI_B
 	select HAVE_ACPI_RESUME
diff --git a/src/mainboard/intel/emeraldlake2/Kconfig b/src/mainboard/intel/emeraldlake2/Kconfig
index dbaf0ee895..d984fa7a5d 100644
--- a/src/mainboard/intel/emeraldlake2/Kconfig
+++ b/src/mainboard/intel/emeraldlake2/Kconfig
@@ -4,6 +4,7 @@ if BOARD_INTEL_EMERALDLAKE2
 
 config BOARD_SPECIFIC_OPTIONS
 	def_bool y
+	select AZALIA_USE_LEGACY_VERB_TABLE
 	select NORTHBRIDGE_INTEL_SANDYBRIDGE
 	select SOUTHBRIDGE_INTEL_C216
 	select SUPERIO_SMSC_SIO1007
diff --git a/src/mainboard/intel/kblrvp/Kconfig b/src/mainboard/intel/kblrvp/Kconfig
index 09d3aebe19..f0416d83dd 100644
--- a/src/mainboard/intel/kblrvp/Kconfig
+++ b/src/mainboard/intel/kblrvp/Kconfig
@@ -2,6 +2,7 @@
 
 config BOARD_INTEL_KBLRVP_COMMON
 	def_bool n
+	select AZALIA_USE_LEGACY_VERB_TABLE
 	select BOARD_ROMSIZE_KB_16384
 	select EC_ACPI
 	select HAVE_ACPI_RESUME
diff --git a/src/mainboard/intel/ptlrvp/Kconfig b/src/mainboard/intel/ptlrvp/Kconfig
index ec30b29491..cc0b9086bc 100644
--- a/src/mainboard/intel/ptlrvp/Kconfig
+++ b/src/mainboard/intel/ptlrvp/Kconfig
@@ -2,6 +2,7 @@
 
 config BOARD_INTEL_PTLRVP_COMMON
 	def_bool n
+	select AZALIA_USE_LEGACY_VERB_TABLE
 	select BOARD_ROMSIZE_KB_32768
 	select CPU_INTEL_SOCKET_OTHER
 	select DRIVERS_GFX_GENERIC
diff --git a/src/mainboard/intel/wtm2/Kconfig b/src/mainboard/intel/wtm2/Kconfig
index 1a10f931a7..97d40c9420 100644
--- a/src/mainboard/intel/wtm2/Kconfig
+++ b/src/mainboard/intel/wtm2/Kconfig
@@ -4,6 +4,7 @@ if BOARD_INTEL_WTM2
 
 config BOARD_SPECIFIC_OPTIONS
 	def_bool y
+	select AZALIA_USE_LEGACY_VERB_TABLE
 	select SOC_INTEL_BROADWELL
 	select BOARD_ROMSIZE_KB_8192
 	select HAVE_ACPI_TABLES
diff --git a/src/mainboard/kontron/986lcd-m/Kconfig b/src/mainboard/kontron/986lcd-m/Kconfig
index c48a9b42de..7fc2c6f65b 100644
--- a/src/mainboard/kontron/986lcd-m/Kconfig
+++ b/src/mainboard/kontron/986lcd-m/Kconfig
@@ -4,6 +4,7 @@ if BOARD_KONTRON_986LCD_M
 
 config BOARD_SPECIFIC_OPTIONS
 	def_bool y
+	select AZALIA_USE_LEGACY_VERB_TABLE
 	select CPU_INTEL_SOCKET_M
 	select NORTHBRIDGE_INTEL_I945
 	select NORTHBRIDGE_INTEL_SUBTYPE_I945GM
diff --git a/src/mainboard/kontron/ktqm77/Kconfig b/src/mainboard/kontron/ktqm77/Kconfig
index f7c41c1a63..77a43f1da3 100644
--- a/src/mainboard/kontron/ktqm77/Kconfig
+++ b/src/mainboard/kontron/ktqm77/Kconfig
@@ -4,6 +4,7 @@ if BOARD_KONTRON_KTQM77
 
 config BOARD_SPECIFIC_OPTIONS
 	def_bool y
+	select AZALIA_USE_LEGACY_VERB_TABLE
 	select NORTHBRIDGE_INTEL_SANDYBRIDGE
 	select SOUTHBRIDGE_INTEL_C216
 	select SUPERIO_WINBOND_W83627DHG
diff --git a/src/mainboard/lenovo/haswell/Kconfig b/src/mainboard/lenovo/haswell/Kconfig
index b2fc97d051..46da23cfd2 100644
--- a/src/mainboard/lenovo/haswell/Kconfig
+++ b/src/mainboard/lenovo/haswell/Kconfig
@@ -2,6 +2,7 @@
 
 config BOARD_LENOVO_HASWELL_COMMON
 	def_bool n
+	select AZALIA_USE_LEGACY_VERB_TABLE
 	select BOARD_ROMSIZE_KB_12288
 	select EC_LENOVO_H8
 	select EC_LENOVO_PMH7
diff --git a/src/mainboard/lenovo/l520/Kconfig b/src/mainboard/lenovo/l520/Kconfig
index 9912098b95..6f7c433828 100644
--- a/src/mainboard/lenovo/l520/Kconfig
+++ b/src/mainboard/lenovo/l520/Kconfig
@@ -4,6 +4,7 @@ if BOARD_LENOVO_L520
 
 config BOARD_SPECIFIC_OPTIONS
 	def_bool y
+	select AZALIA_USE_LEGACY_VERB_TABLE
 	select BOARD_ROMSIZE_KB_4096
 	select DRIVER_LENOVO_SERIALS
 	select EC_LENOVO_H8
diff --git a/src/mainboard/lenovo/m900/Kconfig b/src/mainboard/lenovo/m900/Kconfig
index 882f3131c7..2833052243 100644
--- a/src/mainboard/lenovo/m900/Kconfig
+++ b/src/mainboard/lenovo/m900/Kconfig
@@ -4,6 +4,7 @@ if BOARD_LENOVO_M900
 
 config BOARD_SPECIFIC_OPTIONS
 	def_bool y
+	select AZALIA_USE_LEGACY_VERB_TABLE
 	select BOARD_ROMSIZE_KB_16384
 	select HAVE_ACPI_RESUME
 	select HAVE_ACPI_TABLES
diff --git a/src/mainboard/lenovo/m900_tiny/Kconfig b/src/mainboard/lenovo/m900_tiny/Kconfig
index a99afa1b8b..8f018b5700 100644
--- a/src/mainboard/lenovo/m900_tiny/Kconfig
+++ b/src/mainboard/lenovo/m900_tiny/Kconfig
@@ -5,6 +5,7 @@ if BOARD_LENOVO_THINKCENTRE_M900_TINY
 # TODO: fix and enable DRIVER_LENOVO_SERIALS
 config BOARD_SPECIFIC_OPTIONS
 	def_bool y
+	select AZALIA_USE_LEGACY_VERB_TABLE
 	select BOARD_ROMSIZE_KB_16384
 	select DRIVERS_EFI_VARIABLE_STORE
 	select DRIVERS_OPTION_CFR
diff --git a/src/mainboard/lenovo/m920q/Kconfig b/src/mainboard/lenovo/m920q/Kconfig
index a83b477a54..53d74b821a 100644
--- a/src/mainboard/lenovo/m920q/Kconfig
+++ b/src/mainboard/lenovo/m920q/Kconfig
@@ -4,6 +4,7 @@ if BOARD_LENOVO_M920Q
 
 config BOARD_SPECIFIC_OPTIONS
 	def_bool y
+	select AZALIA_USE_LEGACY_VERB_TABLE
 	select BOARD_ROMSIZE_KB_24576
 	select DRIVERS_UART_8250IO
 	select HAVE_ACPI_RESUME
diff --git a/src/mainboard/lenovo/s230u/Kconfig b/src/mainboard/lenovo/s230u/Kconfig
index 49c8820613..5fc7570aa9 100644
--- a/src/mainboard/lenovo/s230u/Kconfig
+++ b/src/mainboard/lenovo/s230u/Kconfig
@@ -4,6 +4,7 @@ if BOARD_LENOVO_S230U
 
 config BOARD_SPECIFIC_OPTIONS
 	def_bool y
+	select AZALIA_USE_LEGACY_VERB_TABLE
 	select BOARD_ROMSIZE_KB_12288
 	select DRIVER_LENOVO_SERIALS
 	select EC_ACPI
diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/Kconfig b/src/mainboard/lenovo/sklkbl_thinkpad/Kconfig
index 6036ceb06d..9c454e6f7f 100644
--- a/src/mainboard/lenovo/sklkbl_thinkpad/Kconfig
+++ b/src/mainboard/lenovo/sklkbl_thinkpad/Kconfig
@@ -2,6 +2,7 @@
 
 config BOARD_LENOVO_SKLKBL_THINKPAD_COMMON
 	bool
+	select AZALIA_USE_LEGACY_VERB_TABLE
 	select BOARD_ROMSIZE_KB_16384
 	select DRIVERS_OPTION_CFR_ENABLED if PAYLOAD_EDK2 && SMMSTORE
 	select EC_LENOVO_H8
diff --git a/src/mainboard/lenovo/t400/Kconfig b/src/mainboard/lenovo/t400/Kconfig
index 12fbcbdee6..5e71743ce9 100644
--- a/src/mainboard/lenovo/t400/Kconfig
+++ b/src/mainboard/lenovo/t400/Kconfig
@@ -5,6 +5,7 @@ if BOARD_LENOVO_T400 || BOARD_LENOVO_T500 || BOARD_LENOVO_R400 \
 
 config BOARD_SPECIFIC_OPTIONS
 	def_bool y
+	select AZALIA_USE_LEGACY_VERB_TABLE
 	select SYSTEM_TYPE_LAPTOP
 	select CPU_INTEL_SOCKET_P
 	select NORTHBRIDGE_INTEL_GM45
diff --git a/src/mainboard/lenovo/t410/Kconfig b/src/mainboard/lenovo/t410/Kconfig
index 6f18528824..44d722c779 100644
--- a/src/mainboard/lenovo/t410/Kconfig
+++ b/src/mainboard/lenovo/t410/Kconfig
@@ -4,6 +4,7 @@ if BOARD_LENOVO_T410
 
 config BOARD_SPECIFIC_OPTIONS
 	def_bool y
+	select AZALIA_USE_LEGACY_VERB_TABLE
 	select SYSTEM_TYPE_LAPTOP
 	select NORTHBRIDGE_INTEL_IRONLAKE
 	select SOUTHBRIDGE_INTEL_IBEXPEAK
diff --git a/src/mainboard/lenovo/t420/Kconfig b/src/mainboard/lenovo/t420/Kconfig
index cbf07efab7..1b9ddd6e4c 100644
--- a/src/mainboard/lenovo/t420/Kconfig
+++ b/src/mainboard/lenovo/t420/Kconfig
@@ -4,6 +4,7 @@ if BOARD_LENOVO_T420
 
 config BOARD_SPECIFIC_OPTIONS
 	def_bool y
+	select AZALIA_USE_LEGACY_VERB_TABLE
 	select SYSTEM_TYPE_LAPTOP
 	select NORTHBRIDGE_INTEL_SANDYBRIDGE
 	select USE_NATIVE_RAMINIT
diff --git a/src/mainboard/lenovo/t420s/Kconfig b/src/mainboard/lenovo/t420s/Kconfig
index 37b3993a1a..21bbd87431 100644
--- a/src/mainboard/lenovo/t420s/Kconfig
+++ b/src/mainboard/lenovo/t420s/Kconfig
@@ -4,6 +4,7 @@ if BOARD_LENOVO_T420S
 
 config BOARD_SPECIFIC_OPTIONS
 	def_bool y
+	select AZALIA_USE_LEGACY_VERB_TABLE
 	select BOARD_ROMSIZE_KB_8192
 	select DRIVERS_LENOVO_HYBRID_GRAPHICS
 	select DRIVER_LENOVO_SERIALS
diff --git a/src/mainboard/lenovo/t430/Kconfig b/src/mainboard/lenovo/t430/Kconfig
index 1baa94a4c8..20726edb50 100644
--- a/src/mainboard/lenovo/t430/Kconfig
+++ b/src/mainboard/lenovo/t430/Kconfig
@@ -4,6 +4,7 @@ if BOARD_LENOVO_THINKPAD_T430
 
 config BOARD_SPECIFIC_OPTIONS
 	def_bool y
+	select AZALIA_USE_LEGACY_VERB_TABLE
 	select BOARD_ROMSIZE_KB_12288
 	select DRIVERS_LENOVO_HYBRID_GRAPHICS
 	select DRIVER_LENOVO_SERIALS
diff --git a/src/mainboard/lenovo/t430s/Kconfig b/src/mainboard/lenovo/t430s/Kconfig
index 3ab5d340bb..10ce88c6f1 100644
--- a/src/mainboard/lenovo/t430s/Kconfig
+++ b/src/mainboard/lenovo/t430s/Kconfig
@@ -4,6 +4,7 @@ if BOARD_LENOVO_T430S || BOARD_LENOVO_T431S
 
 config BOARD_SPECIFIC_OPTIONS
 	def_bool y
+	select AZALIA_USE_LEGACY_VERB_TABLE
 	select SYSTEM_TYPE_LAPTOP
 	select NORTHBRIDGE_INTEL_SANDYBRIDGE
 	select USE_NATIVE_RAMINIT
diff --git a/src/mainboard/lenovo/t520/Kconfig b/src/mainboard/lenovo/t520/Kconfig
index 384927989f..a93c859615 100644
--- a/src/mainboard/lenovo/t520/Kconfig
+++ b/src/mainboard/lenovo/t520/Kconfig
@@ -2,6 +2,7 @@
 
 config BOARD_LENOVO_BASEBOARD_T520
 	def_bool n
+	select AZALIA_USE_LEGACY_VERB_TABLE
 	select SYSTEM_TYPE_LAPTOP
 	select NORTHBRIDGE_INTEL_SANDYBRIDGE
 	select USE_NATIVE_RAMINIT
diff --git a/src/mainboard/lenovo/t530/Kconfig b/src/mainboard/lenovo/t530/Kconfig
index 9450fdddd7..801e931fbd 100644
--- a/src/mainboard/lenovo/t530/Kconfig
+++ b/src/mainboard/lenovo/t530/Kconfig
@@ -2,6 +2,7 @@
 
 config BOARD_LENOVO_BASEBOARD_T530
 	def_bool n
+	select AZALIA_USE_LEGACY_VERB_TABLE
 	select BOARD_ROMSIZE_KB_12288
 	select DRIVERS_LENOVO_HYBRID_GRAPHICS
 	select DRIVER_LENOVO_SERIALS
diff --git a/src/mainboard/lenovo/t60/Kconfig b/src/mainboard/lenovo/t60/Kconfig
index f1221191da..7508062818 100644
--- a/src/mainboard/lenovo/t60/Kconfig
+++ b/src/mainboard/lenovo/t60/Kconfig
@@ -4,6 +4,7 @@ if BOARD_LENOVO_T60 || BOARD_LENOVO_Z61T || BOARD_LENOVO_R60
 
 config BOARD_SPECIFIC_OPTIONS
 	def_bool y
+	select AZALIA_USE_LEGACY_VERB_TABLE
 	select SYSTEM_TYPE_LAPTOP
 	select CPU_INTEL_SOCKET_M
 	select NORTHBRIDGE_INTEL_I945
diff --git a/src/mainboard/lenovo/thinkcentre_a58/Kconfig b/src/mainboard/lenovo/thinkcentre_a58/Kconfig
index e24d502092..6bd6ce4ad9 100644
--- a/src/mainboard/lenovo/thinkcentre_a58/Kconfig
+++ b/src/mainboard/lenovo/thinkcentre_a58/Kconfig
@@ -4,6 +4,7 @@ if BOARD_LENOVO_THINKCENTRE_A58
 
 config BOARD_SPECIFIC_OPTIONS
 	def_bool y
+	select AZALIA_USE_LEGACY_VERB_TABLE
 	select CPU_INTEL_SOCKET_LGA775
 	select NORTHBRIDGE_INTEL_X4X
 	select SOUTHBRIDGE_INTEL_I82801GX
diff --git a/src/mainboard/lenovo/thinkcentre_m710s/Kconfig b/src/mainboard/lenovo/thinkcentre_m710s/Kconfig
index c01aaece08..85e281dcdf 100644
--- a/src/mainboard/lenovo/thinkcentre_m710s/Kconfig
+++ b/src/mainboard/lenovo/thinkcentre_m710s/Kconfig
@@ -4,6 +4,7 @@ if BOARD_LENOVO_THINKCENTRE_M710S
 
 config BOARD_SPECIFIC_OPTIONS
 	def_bool y
+	select AZALIA_USE_LEGACY_VERB_TABLE
 	select BOARD_ROMSIZE_KB_8192
 	select DRIVERS_USB_ACPI
 	select HAVE_ACPI_RESUME
diff --git a/src/mainboard/lenovo/x131e/Kconfig b/src/mainboard/lenovo/x131e/Kconfig
index 67d7980613..df435e9cfb 100644
--- a/src/mainboard/lenovo/x131e/Kconfig
+++ b/src/mainboard/lenovo/x131e/Kconfig
@@ -4,6 +4,7 @@ if BOARD_LENOVO_X131E
 
 config BOARD_SPECIFIC_OPTIONS
 	def_bool y
+	select AZALIA_USE_LEGACY_VERB_TABLE
 	select BOARD_ROMSIZE_KB_12288
 	select DRIVER_LENOVO_SERIALS
 	select EC_LENOVO_H8
diff --git a/src/mainboard/lenovo/x1_carbon_gen1/Kconfig b/src/mainboard/lenovo/x1_carbon_gen1/Kconfig
index f0dcb38ab4..902b92d5d3 100644
--- a/src/mainboard/lenovo/x1_carbon_gen1/Kconfig
+++ b/src/mainboard/lenovo/x1_carbon_gen1/Kconfig
@@ -4,6 +4,7 @@ if BOARD_LENOVO_X1_CARBON_GEN1
 
 config BOARD_SPECIFIC_OPTIONS
 	def_bool y
+	select AZALIA_USE_LEGACY_VERB_TABLE
 	select BOARD_ROMSIZE_KB_12288
 	select DRIVERS_RICOH_RCE822
 	select DRIVER_LENOVO_SERIALS
diff --git a/src/mainboard/lenovo/x200/Kconfig b/src/mainboard/lenovo/x200/Kconfig
index 148584ed5c..9e37d9a74c 100644
--- a/src/mainboard/lenovo/x200/Kconfig
+++ b/src/mainboard/lenovo/x200/Kconfig
@@ -4,6 +4,7 @@ if BOARD_LENOVO_X200 || BOARD_LENOVO_X301
 
 config BOARD_SPECIFIC_OPTIONS
 	def_bool y
+	select AZALIA_USE_LEGACY_VERB_TABLE
 	select SYSTEM_TYPE_LAPTOP
 	select CPU_INTEL_SOCKET_BGA956
 	select NORTHBRIDGE_INTEL_GM45
diff --git a/src/mainboard/lenovo/x201/Kconfig b/src/mainboard/lenovo/x201/Kconfig
index e91ec3e642..fb743443ad 100644
--- a/src/mainboard/lenovo/x201/Kconfig
+++ b/src/mainboard/lenovo/x201/Kconfig
@@ -4,6 +4,7 @@ if BOARD_LENOVO_X201
 
 config BOARD_SPECIFIC_OPTIONS
 	def_bool y
+	select AZALIA_USE_LEGACY_VERB_TABLE
 	select SYSTEM_TYPE_LAPTOP
 	select NORTHBRIDGE_INTEL_IRONLAKE
 	select SOUTHBRIDGE_INTEL_IBEXPEAK
diff --git a/src/mainboard/lenovo/x220/Kconfig b/src/mainboard/lenovo/x220/Kconfig
index a877546bb7..453afd4bef 100644
--- a/src/mainboard/lenovo/x220/Kconfig
+++ b/src/mainboard/lenovo/x220/Kconfig
@@ -4,6 +4,7 @@ if BOARD_LENOVO_X220 || BOARD_LENOVO_X220I || BOARD_LENOVO_X1
 
 config BOARD_SPECIFIC_OPTIONS
 	def_bool y
+	select AZALIA_USE_LEGACY_VERB_TABLE
 	select BOARD_ROMSIZE_KB_8192
 	select DRIVERS_RICOH_RCE822
 	select DRIVER_LENOVO_SERIALS
diff --git a/src/mainboard/lenovo/x230/Kconfig b/src/mainboard/lenovo/x230/Kconfig
index cb6395beb9..81049412df 100644
--- a/src/mainboard/lenovo/x230/Kconfig
+++ b/src/mainboard/lenovo/x230/Kconfig
@@ -4,6 +4,7 @@ if BOARD_LENOVO_X230 || BOARD_LENOVO_X230T || BOARD_LENOVO_X230S || BOARD_LENOVO
 
 config BOARD_SPECIFIC_OPTIONS
 	def_bool y
+	select AZALIA_USE_LEGACY_VERB_TABLE
 	select SYSTEM_TYPE_LAPTOP
 	select NORTHBRIDGE_INTEL_SANDYBRIDGE
 	select USE_NATIVE_RAMINIT
diff --git a/src/mainboard/lenovo/x60/Kconfig b/src/mainboard/lenovo/x60/Kconfig
index edacdcf234..55dd3e2d3e 100644
--- a/src/mainboard/lenovo/x60/Kconfig
+++ b/src/mainboard/lenovo/x60/Kconfig
@@ -4,6 +4,7 @@ if BOARD_LENOVO_X60
 
 config BOARD_SPECIFIC_OPTIONS
 	def_bool y
+	select AZALIA_USE_LEGACY_VERB_TABLE
 	select SYSTEM_TYPE_LAPTOP
 	select CPU_INTEL_SOCKET_M
 	select NORTHBRIDGE_INTEL_I945
diff --git a/src/mainboard/msi/h81m-p33/Kconfig b/src/mainboard/msi/h81m-p33/Kconfig
index ff3992d344..2b12dfd238 100644
--- a/src/mainboard/msi/h81m-p33/Kconfig
+++ b/src/mainboard/msi/h81m-p33/Kconfig
@@ -4,6 +4,7 @@ if BOARD_MSI_H81M_P33
 
 config BOARD_SPECIFIC_OPTIONS
 	def_bool y
+	select AZALIA_USE_LEGACY_VERB_TABLE
 	select BOARD_ROMSIZE_KB_8192
 	select CPU_INTEL_HASWELL
 	select HAVE_ACPI_RESUME
diff --git a/src/mainboard/msi/ms7707/Kconfig b/src/mainboard/msi/ms7707/Kconfig
index e784bbaf1a..261ad67531 100644
--- a/src/mainboard/msi/ms7707/Kconfig
+++ b/src/mainboard/msi/ms7707/Kconfig
@@ -4,6 +4,7 @@ if BOARD_MSI_MS7707
 
 config BOARD_SPECIFIC_OPTIONS
 	def_bool y
+	select AZALIA_USE_LEGACY_VERB_TABLE
 	select NORTHBRIDGE_INTEL_SANDYBRIDGE
 	select USE_NATIVE_RAMINIT
 	select SOUTHBRIDGE_INTEL_BD82X6X
diff --git a/src/mainboard/msi/ms7d25/Kconfig b/src/mainboard/msi/ms7d25/Kconfig
index 1b23f0354a..60339660fc 100644
--- a/src/mainboard/msi/ms7d25/Kconfig
+++ b/src/mainboard/msi/ms7d25/Kconfig
@@ -8,6 +8,7 @@ config BOARD_MSI_Z690_A_PRO_WIFI_DDR5
 
 config BOARD_MSI_MS7D25
 	def_bool n
+	select AZALIA_USE_LEGACY_VERB_TABLE
 	select SOC_INTEL_ALDERLAKE_PCH_S
 	select BOARD_ROMSIZE_KB_32768
 	select SOC_INTEL_COMMON_BLOCK_HDA_VERB
diff --git a/src/mainboard/msi/ms7e06/Kconfig b/src/mainboard/msi/ms7e06/Kconfig
index b0ba216356..2e163533f4 100644
--- a/src/mainboard/msi/ms7e06/Kconfig
+++ b/src/mainboard/msi/ms7e06/Kconfig
@@ -8,6 +8,7 @@ config BOARD_MSI_Z790_P_PRO_WIFI
 
 config BOARD_MSI_MS7E06
 	def_bool n
+	select AZALIA_USE_LEGACY_VERB_TABLE
 	select SOC_INTEL_RAPTORLAKE_PCH_S
 	select BOARD_ROMSIZE_KB_32768
 	select SOC_INTEL_COMMON_BLOCK_HDA_VERB
diff --git a/src/mainboard/novacustom/mtl-h/Kconfig b/src/mainboard/novacustom/mtl-h/Kconfig
index f08ce25c18..8f5181b34d 100644
--- a/src/mainboard/novacustom/mtl-h/Kconfig
+++ b/src/mainboard/novacustom/mtl-h/Kconfig
@@ -1,5 +1,6 @@
 config BOARD_NOVACUSTOM_MTLH_COMMON
 	def_bool n
+	select AZALIA_USE_LEGACY_VERB_TABLE
 	select BOARD_ROMSIZE_KB_32768
 	select DRIVERS_GENERIC_BAYHUB_LV2
 	select DRIVERS_GFX_GENERIC
diff --git a/src/mainboard/packardbell/ms2290/Kconfig b/src/mainboard/packardbell/ms2290/Kconfig
index 3930f2b968..40285f5b8f 100644
--- a/src/mainboard/packardbell/ms2290/Kconfig
+++ b/src/mainboard/packardbell/ms2290/Kconfig
@@ -4,6 +4,7 @@ if BOARD_PACKARDBELL_MS2290
 
 config BOARD_SPECIFIC_OPTIONS
 	def_bool y
+	select AZALIA_USE_LEGACY_VERB_TABLE
 	select SYSTEM_TYPE_LAPTOP
 	select NORTHBRIDGE_INTEL_IRONLAKE
 	select SOUTHBRIDGE_INTEL_IBEXPEAK
diff --git a/src/mainboard/portwell/m107/Kconfig b/src/mainboard/portwell/m107/Kconfig
index e2cd98886f..8acaa3344e 100644
--- a/src/mainboard/portwell/m107/Kconfig
+++ b/src/mainboard/portwell/m107/Kconfig
@@ -4,6 +4,7 @@ if BOARD_PORTWELL_M107
 
 config BOARD_SPECIFIC_OPTIONS
 	def_bool y
+	select AZALIA_USE_LEGACY_VERB_TABLE
 	select BOARD_ROMSIZE_KB_8192
 	select HAVE_ACPI_TABLES
 	select HAVE_OPTION_TABLE
diff --git a/src/mainboard/prodrive/hermes/Kconfig b/src/mainboard/prodrive/hermes/Kconfig
index c943f6fedc..9bb5a82288 100644
--- a/src/mainboard/prodrive/hermes/Kconfig
+++ b/src/mainboard/prodrive/hermes/Kconfig
@@ -2,6 +2,7 @@
 
 config BOARD_PRODRIVE_HERMES_BASEBOARD
 	def_bool n
+	select AZALIA_USE_LEGACY_VERB_TABLE
 	select SOC_INTEL_COFFEELAKE
 	select BOARD_ROMSIZE_KB_32768
 	select HAVE_ACPI_TABLES
diff --git a/src/mainboard/protectli/vault_adl_p/Kconfig b/src/mainboard/protectli/vault_adl_p/Kconfig
index 5b7d52d19f..e90d9da835 100644
--- a/src/mainboard/protectli/vault_adl_p/Kconfig
+++ b/src/mainboard/protectli/vault_adl_p/Kconfig
@@ -2,6 +2,7 @@ if BOARD_PROTECTLI_VP66XX
 
 config BOARD_SPECIFIC_OPTIONS
 	def_bool y
+	select AZALIA_USE_LEGACY_VERB_TABLE
 	select BOARD_ROMSIZE_KB_16384
 	select SOC_INTEL_ALDERLAKE_PCH_P
 	select SOC_INTEL_COMMON_BLOCK_HDA_VERB
diff --git a/src/mainboard/protectli/vault_cml/Kconfig b/src/mainboard/protectli/vault_cml/Kconfig
index 87de08829a..7001890070 100644
--- a/src/mainboard/protectli/vault_cml/Kconfig
+++ b/src/mainboard/protectli/vault_cml/Kconfig
@@ -4,6 +4,7 @@ if BOARD_PROTECTLI_VP46XX
 
 config BOARD_SPECIFIC_OPTIONS
 	def_bool y
+	select AZALIA_USE_LEGACY_VERB_TABLE
 	select BOARD_ROMSIZE_KB_16384
 	select GFX_GMA_IGNORE_PRESENCE_STRAPS
 	select SOC_INTEL_COMETLAKE_1_2
diff --git a/src/mainboard/purism/librem_bdw/Kconfig b/src/mainboard/purism/librem_bdw/Kconfig
index d1ba25a81a..8c8f5ec5fc 100644
--- a/src/mainboard/purism/librem_bdw/Kconfig
+++ b/src/mainboard/purism/librem_bdw/Kconfig
@@ -2,6 +2,7 @@
 
 config BOARD_PURISM_BASEBOARD_LIBREM_BDW
 	def_bool n
+	select AZALIA_USE_LEGACY_VERB_TABLE
 	select SYSTEM_TYPE_LAPTOP
 	select BOARD_ROMSIZE_KB_8192
 	select HAVE_ACPI_RESUME
diff --git a/src/mainboard/purism/librem_cnl/Kconfig b/src/mainboard/purism/librem_cnl/Kconfig
index a718678605..9495365575 100644
--- a/src/mainboard/purism/librem_cnl/Kconfig
+++ b/src/mainboard/purism/librem_cnl/Kconfig
@@ -2,6 +2,7 @@
 
 config BOARD_PURISM_BASEBOARD_LIBREM_CNL
 	def_bool n
+	select AZALIA_USE_LEGACY_VERB_TABLE
 	select BOARD_ROMSIZE_KB_16384
 	select DRIVERS_GENERIC_CBFS_SERIAL
 	select DRIVERS_USB_ACPI
diff --git a/src/mainboard/purism/librem_jsl/Kconfig b/src/mainboard/purism/librem_jsl/Kconfig
index 2198dd60f8..b971bda207 100644
--- a/src/mainboard/purism/librem_jsl/Kconfig
+++ b/src/mainboard/purism/librem_jsl/Kconfig
@@ -2,6 +2,7 @@
 
 config BOARD_PURISM_BASEBOARD_LIBREM_JSL
 	def_bool n
+	select AZALIA_USE_LEGACY_VERB_TABLE
 	select BOARD_ROMSIZE_KB_16384
 	select DRIVERS_GENERIC_CBFS_SERIAL
 	select DRIVERS_USB_ACPI
diff --git a/src/mainboard/purism/librem_skl/Kconfig b/src/mainboard/purism/librem_skl/Kconfig
index 5f3ed06cd4..f2f71572d5 100644
--- a/src/mainboard/purism/librem_skl/Kconfig
+++ b/src/mainboard/purism/librem_skl/Kconfig
@@ -2,6 +2,7 @@
 
 config BOARD_PURISM_BASEBOARD_LIBREM_SKL
 	def_bool n
+	select AZALIA_USE_LEGACY_VERB_TABLE
 	select BOARD_ROMSIZE_KB_16384
 	select DRIVERS_GENERIC_CBFS_SERIAL
 	select GFX_GMA_IGNORE_PRESENCE_STRAPS
diff --git a/src/mainboard/razer/blade_stealth_kbl/Kconfig b/src/mainboard/razer/blade_stealth_kbl/Kconfig
index a527a9d04d..b34843b1b0 100644
--- a/src/mainboard/razer/blade_stealth_kbl/Kconfig
+++ b/src/mainboard/razer/blade_stealth_kbl/Kconfig
@@ -2,6 +2,7 @@
 
 config BOARD_RAZER_BLADE_STEALTH_KBL
 	bool
+	select AZALIA_USE_LEGACY_VERB_TABLE
 	select SYSTEM_TYPE_LAPTOP
 	select BOARD_ROMSIZE_KB_8192
 	select SUPERIO_ITE_IT8528E
diff --git a/src/mainboard/roda/rk886ex/Kconfig b/src/mainboard/roda/rk886ex/Kconfig
index 9818614f18..0ac225d626 100644
--- a/src/mainboard/roda/rk886ex/Kconfig
+++ b/src/mainboard/roda/rk886ex/Kconfig
@@ -4,6 +4,7 @@ if BOARD_RODA_RK886EX
 
 config BOARD_SPECIFIC_OPTIONS
 	def_bool y
+	select AZALIA_USE_LEGACY_VERB_TABLE
 	select SYSTEM_TYPE_LAPTOP
 	select CPU_INTEL_SOCKET_M
 	select NORTHBRIDGE_INTEL_I945
diff --git a/src/mainboard/roda/rk9/Kconfig b/src/mainboard/roda/rk9/Kconfig
index 3f7aa49697..41a43cf1b6 100644
--- a/src/mainboard/roda/rk9/Kconfig
+++ b/src/mainboard/roda/rk9/Kconfig
@@ -4,6 +4,7 @@ if BOARD_RODA_RK9
 
 config BOARD_SPECIFIC_OPTIONS
 	def_bool y
+	select AZALIA_USE_LEGACY_VERB_TABLE
 	select SYSTEM_TYPE_LAPTOP
 	select CPU_INTEL_SOCKET_BGA956
 	select NORTHBRIDGE_INTEL_GM45
diff --git a/src/mainboard/roda/rv11/Kconfig b/src/mainboard/roda/rv11/Kconfig
index 177af82c68..775c34d00c 100644
--- a/src/mainboard/roda/rv11/Kconfig
+++ b/src/mainboard/roda/rv11/Kconfig
@@ -4,6 +4,7 @@ if BOARD_RODA_RV11 || BOARD_RODA_RW11
 
 config BOARD_SPECIFIC_OPTIONS
 	def_bool y
+	select AZALIA_USE_LEGACY_VERB_TABLE
 	select SYSTEM_TYPE_LAPTOP
 	select NORTHBRIDGE_INTEL_SANDYBRIDGE
 	select SOUTHBRIDGE_INTEL_C216
diff --git a/src/mainboard/samsung/lumpy/Kconfig b/src/mainboard/samsung/lumpy/Kconfig
index d602531e38..ed0793e684 100644
--- a/src/mainboard/samsung/lumpy/Kconfig
+++ b/src/mainboard/samsung/lumpy/Kconfig
@@ -4,6 +4,7 @@ if BOARD_SAMSUNG_LUMPY
 
 config BOARD_SPECIFIC_OPTIONS
 	def_bool y
+	select AZALIA_USE_LEGACY_VERB_TABLE
 	select SYSTEM_TYPE_LAPTOP
 	select BOARD_ROMSIZE_KB_8192
 	select MAINBOARD_HAS_CHROMEOS
diff --git a/src/mainboard/samsung/stumpy/Kconfig b/src/mainboard/samsung/stumpy/Kconfig
index 5d8bc32326..75d45a7493 100644
--- a/src/mainboard/samsung/stumpy/Kconfig
+++ b/src/mainboard/samsung/stumpy/Kconfig
@@ -4,6 +4,7 @@ if BOARD_SAMSUNG_STUMPY
 
 config BOARD_SPECIFIC_OPTIONS
 	def_bool y
+	select AZALIA_USE_LEGACY_VERB_TABLE
 	select BOARD_ROMSIZE_KB_8192
 	select DRIVERS_OPTION_CFR_ENABLED if PAYLOAD_EDK2 && SMMSTORE
 	select MAINBOARD_HAS_CHROMEOS
diff --git a/src/mainboard/sapphire/pureplatinumh61/Kconfig b/src/mainboard/sapphire/pureplatinumh61/Kconfig
index 4048d74a97..4acc40b164 100644
--- a/src/mainboard/sapphire/pureplatinumh61/Kconfig
+++ b/src/mainboard/sapphire/pureplatinumh61/Kconfig
@@ -4,6 +4,7 @@ if BOARD_SAPPHIRE_PUREPLATINUMH61
 
 config BOARD_SPECIFIC_OPTIONS
 	def_bool y
+	select AZALIA_USE_LEGACY_VERB_TABLE
 	select NORTHBRIDGE_INTEL_SANDYBRIDGE
 	select USE_NATIVE_RAMINIT
 	select SOUTHBRIDGE_INTEL_BD82X6X
diff --git a/src/mainboard/siemens/chili/Kconfig b/src/mainboard/siemens/chili/Kconfig
index bc1c02747e..f8c91f50e9 100644
--- a/src/mainboard/siemens/chili/Kconfig
+++ b/src/mainboard/siemens/chili/Kconfig
@@ -2,6 +2,7 @@
 
 config BOARD_SIEMENS_CHILI_COMMON
 	def_bool n
+	select AZALIA_USE_LEGACY_VERB_TABLE
 	select BOARD_ROMSIZE_KB_32768
 	select DRIVERS_I2C_GENERIC
 	select DRIVERS_I2C_HID
diff --git a/src/mainboard/starlabs/byte_adl/Kconfig b/src/mainboard/starlabs/byte_adl/Kconfig
index 28aa10a108..eb9280edc9 100644
--- a/src/mainboard/starlabs/byte_adl/Kconfig
+++ b/src/mainboard/starlabs/byte_adl/Kconfig
@@ -1,5 +1,6 @@
 config BOARD_STARLABS_BYTE_SERIES
 	def_bool n
+	select AZALIA_USE_LEGACY_VERB_TABLE
 	select BOARD_ROMSIZE_KB_16384
 	select CRB_TPM
 	select CSE_DEFAULT_CFR_OPTION_STATE_DISABLED
diff --git a/src/mainboard/starlabs/lite/Kconfig b/src/mainboard/starlabs/lite/Kconfig
index 09bc333e04..fa82f5eba2 100644
--- a/src/mainboard/starlabs/lite/Kconfig
+++ b/src/mainboard/starlabs/lite/Kconfig
@@ -2,6 +2,7 @@
 
 config BOARD_STARLABS_LITE_SERIES
 	def_bool n
+	select AZALIA_USE_LEGACY_VERB_TABLE
 	select BOARD_ROMSIZE_KB_8192
 	select DRIVERS_EFI_VARIABLE_STORE
 	select DRIVERS_OPTION_CFR_ENABLED
diff --git a/src/mainboard/starlabs/starbook/Kconfig b/src/mainboard/starlabs/starbook/Kconfig
index 8f19501996..d0180d9cd6 100644
--- a/src/mainboard/starlabs/starbook/Kconfig
+++ b/src/mainboard/starlabs/starbook/Kconfig
@@ -2,6 +2,7 @@
 
 config BOARD_STARLABS_STARBOOK_SERIES
 	def_bool n
+	select AZALIA_USE_LEGACY_VERB_TABLE
 	select CSE_DEFAULT_CFR_OPTION_STATE_DISABLED
 	select DRIVERS_EFI_VARIABLE_STORE
 	select DRIVERS_OPTION_CFR_ENABLED
diff --git a/src/mainboard/starlabs/starfighter/Kconfig b/src/mainboard/starlabs/starfighter/Kconfig
index 2d9d0bead6..06aee60633 100644
--- a/src/mainboard/starlabs/starfighter/Kconfig
+++ b/src/mainboard/starlabs/starfighter/Kconfig
@@ -2,6 +2,7 @@
 
 config BOARD_STARLABS_STARFIGHTER_SERIES
 	def_bool n
+	select AZALIA_USE_LEGACY_VERB_TABLE
 	select BOARD_ROMSIZE_KB_32768
 	select CSE_DEFAULT_CFR_OPTION_STATE_DISABLED
 	select DRIVERS_EFI_VARIABLE_STORE
diff --git a/src/mainboard/starlabs/starlite_adl/Kconfig b/src/mainboard/starlabs/starlite_adl/Kconfig
index 0a4d948fc2..d67a42a4f5 100644
--- a/src/mainboard/starlabs/starlite_adl/Kconfig
+++ b/src/mainboard/starlabs/starlite_adl/Kconfig
@@ -1,5 +1,6 @@
 config BOARD_STARLABS_STARLITE_SERIES
 	def_bool n
+	select AZALIA_USE_LEGACY_VERB_TABLE
 	select BOARD_ROMSIZE_KB_16384
 	select CRB_TPM
 	select CSE_DEFAULT_CFR_OPTION_STATE_DISABLED
diff --git a/src/mainboard/supermicro/x10slm-f/Kconfig b/src/mainboard/supermicro/x10slm-f/Kconfig
index 212fc90445..5f04c3cfd1 100644
--- a/src/mainboard/supermicro/x10slm-f/Kconfig
+++ b/src/mainboard/supermicro/x10slm-f/Kconfig
@@ -4,6 +4,7 @@ if BOARD_SUPERMICRO_X10SLM_PLUS_F
 
 config BOARD_SPECIFIC_OPTIONS
 	def_bool y
+	select AZALIA_USE_LEGACY_VERB_TABLE
 	select BOARD_ROMSIZE_KB_16384
 	select DRIVERS_ASPEED_AST2050 # Supports AST2400 too.
 	select HAVE_ACPI_RESUME
diff --git a/src/mainboard/supermicro/x9sae/Kconfig b/src/mainboard/supermicro/x9sae/Kconfig
index 0a60570054..1454a8282b 100644
--- a/src/mainboard/supermicro/x9sae/Kconfig
+++ b/src/mainboard/supermicro/x9sae/Kconfig
@@ -4,6 +4,7 @@ if BOARD_SUPERMICRO_X9SAE
 
 config BOARD_SPECIFIC_OPTIONS
 	def_bool y
+	select AZALIA_USE_LEGACY_VERB_TABLE
 	select BOARD_ROMSIZE_KB_16384
 	select HAVE_ACPI_RESUME
 	select HAVE_ACPI_TABLES
diff --git a/src/mainboard/supermicro/x9scl/Kconfig b/src/mainboard/supermicro/x9scl/Kconfig
index 1499012014..6fb4fb15f1 100644
--- a/src/mainboard/supermicro/x9scl/Kconfig
+++ b/src/mainboard/supermicro/x9scl/Kconfig
@@ -4,6 +4,7 @@ if BOARD_SUPERMICRO_X9SCL
 
 config BOARD_SPECIFIC_OPTIONS
 	def_bool y
+	select AZALIA_USE_LEGACY_VERB_TABLE
 	select BOARD_ROMSIZE_KB_8192
 	select HAVE_ACPI_TABLES
 	select NORTHBRIDGE_INTEL_SANDYBRIDGE
diff --git a/src/mainboard/system76/addw1/Kconfig b/src/mainboard/system76/addw1/Kconfig
index 089ca7aee0..a444da0441 100644
--- a/src/mainboard/system76/addw1/Kconfig
+++ b/src/mainboard/system76/addw1/Kconfig
@@ -4,6 +4,7 @@ if BOARD_SYSTEM76_ADDW1 || BOARD_SYSTEM76_ADDW2
 
 config BOARD_SPECIFIC_OPTIONS
 	def_bool y
+	select AZALIA_USE_LEGACY_VERB_TABLE
 	select BOARD_ROMSIZE_KB_16384
 	select DRIVERS_GENERIC_CBFS_SERIAL
 	select DRIVERS_GENERIC_CBFS_UUID
diff --git a/src/mainboard/system76/adl/Kconfig b/src/mainboard/system76/adl/Kconfig
index 56860a4bb2..18c5e9b2d1 100644
--- a/src/mainboard/system76/adl/Kconfig
+++ b/src/mainboard/system76/adl/Kconfig
@@ -2,6 +2,7 @@
 
 config BOARD_SYSTEM76_ADL_COMMON
 	def_bool n
+	select AZALIA_USE_LEGACY_VERB_TABLE
 	select BOARD_ROMSIZE_KB_32768
 	select DRIVERS_GENERIC_BAYHUB_LV2
 	select DRIVERS_GENERIC_CBFS_SERIAL
diff --git a/src/mainboard/system76/bonw14/Kconfig b/src/mainboard/system76/bonw14/Kconfig
index b12c514e3e..7c7e42e10b 100644
--- a/src/mainboard/system76/bonw14/Kconfig
+++ b/src/mainboard/system76/bonw14/Kconfig
@@ -4,6 +4,7 @@ if BOARD_SYSTEM76_BONW14
 
 config BOARD_SPECIFIC_OPTIONS
 	def_bool y
+	select AZALIA_USE_LEGACY_VERB_TABLE
 	select BOARD_ROMSIZE_KB_16384
 	select DRIVERS_GENERIC_CBFS_SERIAL
 	select DRIVERS_GENERIC_CBFS_UUID
diff --git a/src/mainboard/system76/cml-u/Kconfig b/src/mainboard/system76/cml-u/Kconfig
index 4bb4729675..ee435de5fa 100644
--- a/src/mainboard/system76/cml-u/Kconfig
+++ b/src/mainboard/system76/cml-u/Kconfig
@@ -4,6 +4,7 @@ if BOARD_SYSTEM76_DARP6 || BOARD_SYSTEM76_GALP4 || BOARD_SYSTEM76_LEMP9
 
 config BOARD_SPECIFIC_OPTIONS
 	def_bool y
+	select AZALIA_USE_LEGACY_VERB_TABLE
 	select BOARD_ROMSIZE_KB_16384
 	select DRIVERS_GENERIC_CBFS_SERIAL
 	select DRIVERS_GENERIC_CBFS_UUID
diff --git a/src/mainboard/system76/gaze15/Kconfig b/src/mainboard/system76/gaze15/Kconfig
index 09616c9170..ea0ef2ded7 100644
--- a/src/mainboard/system76/gaze15/Kconfig
+++ b/src/mainboard/system76/gaze15/Kconfig
@@ -4,6 +4,7 @@ if BOARD_SYSTEM76_GAZE14 || BOARD_SYSTEM76_GAZE15
 
 config BOARD_SPECIFIC_OPTIONS
 	def_bool y
+	select AZALIA_USE_LEGACY_VERB_TABLE
 	select BOARD_ROMSIZE_KB_16384
 	select DRIVERS_GENERIC_CBFS_SERIAL
 	select DRIVERS_GENERIC_CBFS_UUID
diff --git a/src/mainboard/system76/kbl-u/Kconfig b/src/mainboard/system76/kbl-u/Kconfig
index c8410f295e..0157d5c1ae 100644
--- a/src/mainboard/system76/kbl-u/Kconfig
+++ b/src/mainboard/system76/kbl-u/Kconfig
@@ -4,6 +4,7 @@ if BOARD_SYSTEM76_GALP2 || BOARD_SYSTEM76_GALP3 || BOARD_SYSTEM76_GALP3_B
 
 config BOARD_SPECIFIC_OPTIONS
 	def_bool y
+	select AZALIA_USE_LEGACY_VERB_TABLE
 	select BOARD_ROMSIZE_KB_8192
 	select DRIVERS_GENERIC_CBFS_SERIAL
 	select DRIVERS_GENERIC_CBFS_UUID
diff --git a/src/mainboard/system76/mtl/Kconfig b/src/mainboard/system76/mtl/Kconfig
index 2a0bada34e..761c599fda 100644
--- a/src/mainboard/system76/mtl/Kconfig
+++ b/src/mainboard/system76/mtl/Kconfig
@@ -2,6 +2,7 @@
 
 config BOARD_SYSTEM76_MTL_COMMON
 	def_bool n
+	select AZALIA_USE_LEGACY_VERB_TABLE
 	select BOARD_ROMSIZE_KB_32768
 	select DRIVERS_GENERIC_BAYHUB_LV2
 	select DRIVERS_GENERIC_CBFS_SERIAL
diff --git a/src/mainboard/system76/oryp5/Kconfig b/src/mainboard/system76/oryp5/Kconfig
index 91a36f387b..a74bea2339 100644
--- a/src/mainboard/system76/oryp5/Kconfig
+++ b/src/mainboard/system76/oryp5/Kconfig
@@ -4,6 +4,7 @@ if BOARD_SYSTEM76_ORYP5
 
 config BOARD_SPECIFIC_OPTIONS
 	def_bool y
+	select AZALIA_USE_LEGACY_VERB_TABLE
 	select BOARD_ROMSIZE_KB_16384
 	select DRIVERS_GENERIC_CBFS_SERIAL
 	select DRIVERS_GENERIC_CBFS_UUID
diff --git a/src/mainboard/system76/oryp6/Kconfig b/src/mainboard/system76/oryp6/Kconfig
index b096821fde..8fd023d56a 100644
--- a/src/mainboard/system76/oryp6/Kconfig
+++ b/src/mainboard/system76/oryp6/Kconfig
@@ -4,6 +4,7 @@ if BOARD_SYSTEM76_ORYP6 || BOARD_SYSTEM76_ORYP7
 
 config BOARD_SPECIFIC_OPTIONS
 	def_bool y
+	select AZALIA_USE_LEGACY_VERB_TABLE
 	select BOARD_ROMSIZE_KB_16384
 	select DRIVERS_GENERIC_CBFS_SERIAL
 	select DRIVERS_GENERIC_CBFS_UUID
diff --git a/src/mainboard/system76/rpl/Kconfig b/src/mainboard/system76/rpl/Kconfig
index a61e4efab4..f29c110596 100644
--- a/src/mainboard/system76/rpl/Kconfig
+++ b/src/mainboard/system76/rpl/Kconfig
@@ -2,6 +2,7 @@
 
 config BOARD_SYSTEM76_RPL_COMMON
 	def_bool n
+	select AZALIA_USE_LEGACY_VERB_TABLE
 	select BOARD_ROMSIZE_KB_32768
 	select DRIVERS_GENERIC_BAYHUB_LV2 if !BOARD_SYSTEM76_BONW15
 	select DRIVERS_GENERIC_CBFS_SERIAL
diff --git a/src/mainboard/system76/tgl-h/Kconfig b/src/mainboard/system76/tgl-h/Kconfig
index 9f9ee1dd30..7a0d3f5695 100644
--- a/src/mainboard/system76/tgl-h/Kconfig
+++ b/src/mainboard/system76/tgl-h/Kconfig
@@ -4,6 +4,7 @@ if BOARD_SYSTEM76_GAZE16_3050 || BOARD_SYSTEM76_GAZE16_3060 || BOARD_SYSTEM76_GA
 
 config BOARD_SPECIFIC_OPTIONS
 	def_bool y
+	select AZALIA_USE_LEGACY_VERB_TABLE
 	select BOARD_ROMSIZE_KB_16384
 	select DRIVERS_GENERIC_BAYHUB_LV2
 	select DRIVERS_GENERIC_CBFS_SERIAL
diff --git a/src/mainboard/system76/tgl-u/Kconfig b/src/mainboard/system76/tgl-u/Kconfig
index 4bce9a3f2d..56f516ff0a 100644
--- a/src/mainboard/system76/tgl-u/Kconfig
+++ b/src/mainboard/system76/tgl-u/Kconfig
@@ -4,6 +4,7 @@ if BOARD_SYSTEM76_DARP7 || BOARD_SYSTEM76_GALP5 || BOARD_SYSTEM76_LEMP10
 
 config BOARD_SPECIFIC_OPTIONS
 	def_bool y
+	select AZALIA_USE_LEGACY_VERB_TABLE
 	select BOARD_ROMSIZE_KB_16384
 	select DRIVERS_GENERIC_BAYHUB_LV2
 	select DRIVERS_GENERIC_CBFS_SERIAL
diff --git a/src/mainboard/system76/whl-u/Kconfig b/src/mainboard/system76/whl-u/Kconfig
index b8cb4fc33c..cacf252cd9 100644
--- a/src/mainboard/system76/whl-u/Kconfig
+++ b/src/mainboard/system76/whl-u/Kconfig
@@ -4,6 +4,7 @@ if BOARD_SYSTEM76_GALP3_C || BOARD_SYSTEM76_DARP5
 
 config BOARD_SPECIFIC_OPTIONS
 	def_bool y
+	select AZALIA_USE_LEGACY_VERB_TABLE
 	select BOARD_ROMSIZE_KB_16384
 	select DRIVERS_GENERIC_CBFS_SERIAL
 	select DRIVERS_GENERIC_CBFS_UUID
diff --git a/src/mainboard/topton/adl/Kconfig b/src/mainboard/topton/adl/Kconfig
index ffdfae1eee..29d15300a6 100644
--- a/src/mainboard/topton/adl/Kconfig
+++ b/src/mainboard/topton/adl/Kconfig
@@ -4,6 +4,7 @@ if BOARD_TOPTON_X2F_N100
 
 config BOARD_SPECIFIC_OPTIONS
 	def_bool y
+	select AZALIA_USE_LEGACY_VERB_TABLE
 	select BOARD_ROMSIZE_KB_16384
 	select DRIVERS_OPTION_CFR_ENABLED if PAYLOAD_EDK2 && SMMSTORE
 	select FSP_TYPE_IOT

From 31fc5b06a6be62b30739d33eeabe6c2727679bb1 Mon Sep 17 00:00:00 2001
From: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Date: Thu, 7 Aug 2025 08:31:24 +0900
Subject: [PATCH 2134/3886] device: Introduce reworked azalia verb table

The current implementation of the HDA verb table has been shown to have
some problems. The primary issue is that it requires the programmer to
keep track of the amount of verbs that are going to be loaded. While
this may sound simple, in practice there have been numerous cases where
this "count field" has been forgotten to be updated or miscounted. In
the case where the "count field" is incorrect, coreboot will start
looking for codecs in some random memory location, essentially making
loading further codecs impossible.

Another issue is the "count field" treats 4 32-bit values as a single
group, therefore the amount of verbs in the table must be a multiple
of 4. This makes intuitive sense when only using the AZALIA_PIN_CFG() or
AZALIA_SUBVENDOR() macros. However, once the verb table requires
"controls" that use < 4 verbs (e.g. "Coefficient Index"), we need to add
padding values to ensure the alignment is correct. This adds unnecessary
verbs to the table which can further lead to unnecessary processing.

Therefore, in this change we proprose a solution by separating the codec
entries in the verb table into structures, which allows us to separate
the verbs into an array and automatically calculate the "count field"
using the ARRAY_SIZE() macro. It also makes iteration and access to
member fields easier. We also now count the verbs and not 4 32-bit
groups, eliminating the aforementioned alignment issue.

Additionally, this change also changes the way coreboot searches for
entries in the verb table. Before, we searched the table for only a
matching vendor ID, but now we search for a matching vendor ID and
codec address pair. This allows a mainboard to be able to correctly load
multiple audio codecs that use the same chips.

To make reviewing this large rework easier, we temporarily keep both
implementations (legacy and reworked) and allow boards to choose which
implementation to use by selecting a Kconfig. Newer boards are
discouraged from using the legacy implementation, as it is not selected
by default. This allows us to slowly change the codebase instead of
changing everything at once.

TEST=
  1. Timeless build with AZALIA_USE_LEGACY_VERB_TABLE=y produces
     identical binaries (with INCLUDE_CONFIG_FILE=n)
  2. HP ProBook 450 G3 using reworked verb table was able to load all
     verbs successfully.

Change-Id: Ib16237de89956405afa3be5b4e3f64a4d62e6a48
Signed-off-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88656
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/device/azalia_device.c         | 60 ++++++++++++++++++++++++++++++
 src/include/device/azalia_device.h | 28 ++++++++++++++
 2 files changed, 88 insertions(+)

diff --git a/src/device/azalia_device.c b/src/device/azalia_device.c
index f894895d6c..82c6fdca41 100644
--- a/src/device/azalia_device.c
+++ b/src/device/azalia_device.c
@@ -233,6 +233,7 @@ __weak void mainboard_azalia_program_runtime_verbs(u8 *base, u32 viddid)
 {
 }
 
+#if CONFIG(AZALIA_USE_LEGACY_VERB_TABLE)
 void azalia_codec_init(u8 *base, int addr, const u32 *verb_table, u32 verb_table_bytes)
 {
 	if (azalia_write_verb(base, AZALIA_VERB_GET_VENDOR_ID(addr)) < 0)
@@ -270,6 +271,65 @@ void azalia_codecs_init(u8 *base, u16 codec_mask)
 
 	azalia_program_verb_table(base, pc_beep_verbs, pc_beep_verbs_size);
 }
+#else
+static struct azalia_codec *find_codec(struct azalia_codec *codecs, u32 vid, u8 addr)
+{
+	for (struct azalia_codec *codec = codecs; codec->vendor_id; codec++) {
+		if (codec->vendor_id == vid && codec->address == addr)
+			return codec;
+	}
+	return NULL;
+}
+
+void azalia_codec_init(u8 *base, struct azalia_codec *codec)
+{
+	/* Give a generic name if nothing was provided */
+	const char *name = codec->name ? codec->name : "codec";
+
+	printk(BIOS_DEBUG, "azalia_audio: initializing %s...\n", name);
+	printk(BIOS_DEBUG, "azalia_audio:  - vendor ID:    0x%08x\n", codec->vendor_id);
+	printk(BIOS_DEBUG, "azalia_audio:  - subsystem ID: 0x%08x\n", codec->subsystem_id);
+	printk(BIOS_DEBUG, "azalia_audio:  - address:      %u\n", codec->address);
+
+	if (azalia_program_verb_table(base, codec->verbs, codec->verb_count) < 0) {
+		printk(BIOS_WARNING, "azalia_audio: failed to load verbs\n");
+		return;
+	}
+
+	mainboard_azalia_program_runtime_verbs(base, codec->vendor_id);
+
+	printk(BIOS_DEBUG, "azalia_audio: done\n");
+}
+
+void azalia_custom_codecs_init(u8 *base, struct azalia_codec *codecs, u16 codec_mask)
+{
+	for (u8 i = 0; i < AZALIA_MAX_CODECS; i++) {
+		if (!(codec_mask & BIT(i)))
+			continue;
+
+		if (azalia_write_verb(base, AZALIA_VERB_GET_VENDOR_ID(i)) < 0)
+			continue;
+		u32 vid = read32(base + HDA_IR_REG);
+
+		struct azalia_codec *codec = find_codec(codecs, vid, i);
+		if (codec == NULL) {
+			printk(BIOS_WARNING,
+			       "azalia_audio: cannot find verbs for codec with vendor ID: 0x%08x (address %u)\n",
+			       vid, i);
+			continue;
+		}
+
+		azalia_codec_init(base, codec);
+	}
+
+	azalia_program_verb_table(base, pc_beep_verbs, pc_beep_verbs_size);
+}
+
+void azalia_codecs_init(u8 *base, u16 codec_mask)
+{
+	azalia_custom_codecs_init(base, mainboard_azalia_codecs, codec_mask);
+}
+#endif
 
 void azalia_audio_init(struct device *dev)
 {
diff --git a/src/include/device/azalia_device.h b/src/include/device/azalia_device.h
index 21d00b0dae..66126d2e8c 100644
--- a/src/include/device/azalia_device.h
+++ b/src/include/device/azalia_device.h
@@ -20,11 +20,30 @@
 
 #define AZALIA_MAX_CODECS	15
 
+/*
+ * The HDA specification refers to the vendor/device ID (similar to PCI IDs)
+ * collectively as "vendor ID". While this could be slightly confusing, we will
+ * call it "vendor ID" as the specification and most implementations do.
+ */
+struct azalia_codec {
+	const char *name;
+	u32 vendor_id;
+	u32 subsystem_id;
+	u8 address;
+	const u32 *verbs;
+	size_t verb_count;
+};
+
 enum cb_err azalia_enter_reset(u8 *base);
 enum cb_err azalia_exit_reset(u8 *base);
 u32 azalia_find_verb(const u32 *verb_table, u32 verb_table_bytes, u32 viddid, const u32 **verb);
 int azalia_program_verb_table(u8 *base, const u32 *verbs, u32 verb_size);
+#if CONFIG(AZALIA_USE_LEGACY_VERB_TABLE)
 void azalia_codec_init(u8 *base, int addr, const u32 *verb_table, u32 verb_table_bytes);
+#else
+void azalia_codec_init(u8 *base, struct azalia_codec *codec);
+void azalia_custom_codecs_init(u8 *base, struct azalia_codec *codecs, u16 codec_mask);
+#endif
 void azalia_codecs_init(u8 *base, u16 codec_mask);
 void azalia_audio_init(struct device *dev);
 extern struct device_operations default_azalia_audio_ops;
@@ -32,8 +51,12 @@ extern struct device_operations default_azalia_audio_ops;
 /* Optional hook to program codec settings that are only known at runtime */
 void mainboard_azalia_program_runtime_verbs(u8 *base, u32 viddid);
 
+#if CONFIG(AZALIA_USE_LEGACY_VERB_TABLE)
 extern const u32 cim_verb_data[];
 extern const u32 cim_verb_data_size;
+#else
+extern struct azalia_codec mainboard_azalia_codecs[];
+#endif
 extern const u32 pc_beep_verbs[];
 extern const u32 pc_beep_verbs_size;
 
@@ -161,9 +184,14 @@ enum azalia_pin_misc {
 	 (((association) <<  4) & 0x000000f0) |						\
 	 (((sequence)    <<  0) & 0x0000000f))
 
+#if CONFIG(AZALIA_USE_LEGACY_VERB_TABLE)
 #define AZALIA_ARRAY_SIZES const u32 pc_beep_verbs_size =	\
 	ARRAY_SIZE(pc_beep_verbs);				\
 	const u32 cim_verb_data_size = sizeof(cim_verb_data)
+#else
+#define AZALIA_ARRAY_SIZES const u32 pc_beep_verbs_size =	\
+	ARRAY_SIZE(pc_beep_verbs)
+#endif
 
 #define AZALIA_VERB_12B(codec, pin, verb, val)		\
 	((codec) << 28 | (pin) << 20 | (verb) << 8 | (val))

From 69781b9806808980b98a5b28bbe59465b9cfc668 Mon Sep 17 00:00:00 2001
From: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Date: Mon, 11 Aug 2025 10:22:40 +0900
Subject: [PATCH 2135/3886] soc/intel/broadwell/minihd.c: Add reworked verb
 table implementation

This rework is done gradually, and that means different mainboards will
use different implementations of the verb table. As this code is used by
multiple mainboards we need to keep both implementations and select
whichever implementation matches the one being used by the mainboard
currently being built.

It should be noted that we do not modifiy the verb tables in any case,
as it would break the regression test script mentioned in the TEST
section below.

For an overall rationale for this rework, see CB:88656.

TEST=
  1. Timeless build with AZALIA_USE_LEGACY_VERB_TABLE=y produces
     identical binaries (tested with google/auron_paine)
  2. Passed regression test (CB:88763)

Change-Id: I9ba3259defae66678c4490891b869b96b6c6ade3
Signed-off-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88738
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
---
 src/soc/intel/broadwell/minihd.c | 53 ++++++++++++++++++++++++++++++--
 1 file changed, 51 insertions(+), 2 deletions(-)

diff --git a/src/soc/intel/broadwell/minihd.c b/src/soc/intel/broadwell/minihd.c
index ee635019d5..881fdeb42c 100644
--- a/src/soc/intel/broadwell/minihd.c
+++ b/src/soc/intel/broadwell/minihd.c
@@ -10,6 +10,7 @@
 #include <soc/igd.h>
 #include <southbridge/intel/lynxpoint/hda_verb.h>
 
+#if CONFIG(AZALIA_USE_LEGACY_VERB_TABLE)
 static const u32 minihd_verb_table[] = {
 	/* coreboot specific header */
 	0x80862808,	/* Codec Vendor / Device ID: Intel Broadwell Mini-HD */
@@ -44,13 +45,56 @@ static const u32 minihd_verb_table[] = {
 	0x00878100,
 	0x00878100,
 };
+#else
+static const u32 display_audio_verbs[] = {
+	/* Enable 3rd Pin and Converter Widget */
+	0x00878101,
+
+	/* Pin Widget 5 - PORT B */
+	0x00571c10,
+	0x00571d00,
+	0x00571e56,
+	0x00571f18,
+
+	/* Pin Widget 6 - PORT C */
+	0x00671c20,
+	0x00671d00,
+	0x00671e56,
+	0x00671f18,
+
+	/* Pin Widget 7 - PORT D */
+	0x00771c30,
+	0x00771d00,
+	0x00771e56,
+	0x00771f18,
+
+	/* Disable 3rd Pin and Converter Widget */
+	0x00878100,
+
+	/* Dummy entries to fill out the table */
+	0x00878100,
+	0x00878100,
+};
+
+static struct azalia_codec minihd_codecs[] = {
+	{
+		.name         = "Intel Display Audio (HDMI/DP)",
+		.vendor_id    = 0x80862808,
+		.subsystem_id = 0x80860101,
+		.address      = 0,
+		.verbs        = display_audio_verbs,
+		.verb_count   = ARRAY_SIZE(display_audio_verbs),
+	},
+	{ /* terminator */ }
+};
+#endif
 
 static void minihd_init(struct device *dev)
 {
 	struct resource *res;
 	u32 reg32;
 	u8 *base;
-	int codec_mask, i;
+	int codec_mask;
 
 	/* Find base address */
 	res = probe_resource(dev, PCI_BASE_ADDRESS_0);
@@ -77,13 +121,18 @@ static void minihd_init(struct device *dev)
 	/* Init the codec and write the verb table */
 	codec_mask = hda_codec_detect(base);
 
+#if CONFIG(AZALIA_USE_LEGACY_VERB_TABLE)
 	if (codec_mask) {
-		for (i = 3; i >= 0; i--) {
+		for (int i = 3; i >= 0; i--) {
 			if (codec_mask & (1 << i))
 				azalia_codec_init(base, i, minihd_verb_table,
 						  sizeof(minihd_verb_table));
 		}
 	}
+#else
+	if (codec_mask)
+		azalia_custom_codecs_init(base, minihd_codecs, codec_mask);
+#endif
 
 	/* Set EM4/EM5 registers */
 	write32(base + 0x0100c, igd_get_reg_em4());

From bc92d9a6666615bcd20256711a1b408cba2593ac Mon Sep 17 00:00:00 2001
From: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Date: Mon, 11 Aug 2025 10:24:48 +0900
Subject: [PATCH 2136/3886] nb/intel/haswell/minihd.c: Add reworked verb table
 implementation

This rework is done gradually, and that means different mainboards will
use different implementations of the verb table. As this code is used by
multiple mainboards we need to keep both implementations and select
whichever implementation matches the one being used by the mainboard
currently being built.

It should be noted that we do not modifiy the verb tables in any case,
as it would break the regression test script mentioned in the TEST
section below.

For an overall rationale for this rework, see CB:88656.

TEST=
  1. Timeless build with AZALIA_USE_LEGACY_VERB_TABLE=y produces
     identical binaries (tested with google/slippy_falcon)
  2. Passed regression test (CB:88763)

Change-Id: I3bf8140a4ceb6edad71d57ab82e0a96f51159985
Signed-off-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88739
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
---
 src/northbridge/intel/haswell/minihd.c | 53 +++++++++++++++++++++++++-
 1 file changed, 51 insertions(+), 2 deletions(-)

diff --git a/src/northbridge/intel/haswell/minihd.c b/src/northbridge/intel/haswell/minihd.c
index 6abc6c1c85..eeed7155f8 100644
--- a/src/northbridge/intel/haswell/minihd.c
+++ b/src/northbridge/intel/haswell/minihd.c
@@ -9,6 +9,7 @@
 #include <device/mmio.h>
 #include <southbridge/intel/lynxpoint/hda_verb.h>
 
+#if CONFIG(AZALIA_USE_LEGACY_VERB_TABLE)
 static const u32 minihd_verb_table[] = {
 	/* coreboot specific header */
 	0x80862807,	/* Codec Vendor / Device ID: Intel Haswell Mini-HD */
@@ -43,13 +44,56 @@ static const u32 minihd_verb_table[] = {
 	0x00878100,
 	0x00878100,
 };
+#else
+static const u32 display_audio_verbs[] = {
+	/* Enable 3rd Pin and Converter Widget */
+	0x00878101,
+
+	/* Pin Widget 5 - PORT B */
+	0x00571c10,
+	0x00571d00,
+	0x00571e56,
+	0x00571f18,
+
+	/* Pin Widget 6 - PORT C */
+	0x00671c20,
+	0x00671d00,
+	0x00671e56,
+	0x00671f18,
+
+	/* Pin Widget 7 - PORT D */
+	0x00771c30,
+	0x00771d00,
+	0x00771e56,
+	0x00771f18,
+
+	/* Disable 3rd Pin and Converter Widget */
+	0x00878100,
+
+	/* Dummy entries to fill out the table */
+	0x00878100,
+	0x00878100,
+};
+
+static struct azalia_codec minihd_codecs[] = {
+	{
+		.name         = "Intel Display Audio (HDMI/DP)",
+		.vendor_id    = 0x80862807,
+		.subsystem_id = 0x80860101,
+		.address      = 0,
+		.verbs        = display_audio_verbs,
+		.verb_count   = ARRAY_SIZE(display_audio_verbs),
+	},
+	{ /* terminator */ }
+};
+#endif
 
 static void minihd_init(struct device *dev)
 {
 	struct resource *res;
 	u32 reg32;
 	u8 *base;
-	int codec_mask, i;
+	int codec_mask;
 
 	/* Find base address */
 	res = probe_resource(dev, PCI_BASE_ADDRESS_0);
@@ -76,13 +120,18 @@ static void minihd_init(struct device *dev)
 	/* Init the codec and write the verb table */
 	codec_mask = hda_codec_detect(base);
 
+#if CONFIG(AZALIA_USE_LEGACY_VERB_TABLE)
 	if (codec_mask) {
-		for (i = 3; i >= 0; i--) {
+		for (int i = 3; i >= 0; i--) {
 			if (codec_mask & (1 << i))
 				azalia_codec_init(base, i, minihd_verb_table,
 						  sizeof(minihd_verb_table));
 		}
 	}
+#else
+	if (codec_mask)
+		azalia_custom_codecs_init(base, minihd_codecs, codec_mask);
+#endif
 }
 
 static struct device_operations minihd_ops = {

From f3db3a19d5cbd642d13816320e32785df9af26d6 Mon Sep 17 00:00:00 2001
From: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Date: Thu, 7 Aug 2025 08:40:49 +0900
Subject: [PATCH 2137/3886] mb/51nb: Replace verb tables with reworked
 implementation

No modifications/assumptions about the codecs were made on these boards.

The Kconfigs were reverted using the following command:
  find src/mainboard/51nb -name 'Kconfig' | xargs git checkout main

It should be noted that we do not modifiy the verb tables in any case,
as it would break the regression test script mentioned in the TEST
section below.

For an overall rationale for this rework, see CB:88656.

TEST= All boards passed regression test (CB:88763)

Change-Id: Ib77a7d097b0ae68d250ebe0cb269249a587efcb3
Signed-off-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88657
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/51nb/x210/Kconfig    |  1 -
 src/mainboard/51nb/x210/hda_verb.c | 20 ++++++++++++++------
 2 files changed, 14 insertions(+), 7 deletions(-)

diff --git a/src/mainboard/51nb/x210/Kconfig b/src/mainboard/51nb/x210/Kconfig
index 5f880e01e6..a9d18074eb 100644
--- a/src/mainboard/51nb/x210/Kconfig
+++ b/src/mainboard/51nb/x210/Kconfig
@@ -4,7 +4,6 @@ if BOARD_51NB_X210
 
 config BOARD_SPECIFIC_OPTIONS
 	def_bool y
-	select AZALIA_USE_LEGACY_VERB_TABLE
 	select BOARD_ROMSIZE_KB_8192
 	select EC_51NB_NPCE985LA0DX
 	select HAVE_ACPI_RESUME
diff --git a/src/mainboard/51nb/x210/hda_verb.c b/src/mainboard/51nb/x210/hda_verb.c
index 730cc443a7..d689487582 100644
--- a/src/mainboard/51nb/x210/hda_verb.c
+++ b/src/mainboard/51nb/x210/hda_verb.c
@@ -2,12 +2,7 @@
 
 #include <device/azalia_device.h>
 
-const u32 cim_verb_data[] = {
-	/* coreboot specific header */
-	0x14f15069,	/* Codec Vendor / Device ID: Conexant CX20585 */
-	0x17aa2155,	/* Subsystem ID */
-	12,		/* Number of jacks (NID entries) */
-
+static const u32 conexant_cx20585_verbs[] = {
 	0x0017ff00,	/* Function Reset */
 	0x0017ff00,	/* Double Function Reset */
 	0x0017ff00,
@@ -36,4 +31,17 @@ const u32 cim_verb_data[] = {
 
 const u32 pc_beep_verbs[] = {
 };
+
+struct azalia_codec mainboard_azalia_codecs[] = {
+	{
+		.name         = "Conexant CX20585",
+		.vendor_id    = 0x14f15069,
+		.subsystem_id = 0x17aa2155,
+		.address      = 0,
+		.verbs        = conexant_cx20585_verbs,
+		.verb_count   = ARRAY_SIZE(conexant_cx20585_verbs),
+	},
+	{ /* terminator */ }
+};
+
 AZALIA_ARRAY_SIZES;

From 94beaa7ab313b1f790a41336288e75483ec2180a Mon Sep 17 00:00:00 2001
From: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Date: Thu, 7 Aug 2025 09:17:53 +0900
Subject: [PATCH 2138/3886] mb/acer: Replace verb tables with reworked
 implementation

Some boards did not provide the chip name for the audio codecs in the
comments, and were therefore identified using external sources:

  g43t-am3:
    - 0x10ec0888 -> Realtek ALC888[1]

The Kconfigs were reverted using the following command:
  find src/mainboard/acer -name 'Kconfig' | xargs git checkout main

It should be noted that we do not modifiy the verb tables in any case,
as it would break the regression test script mentioned in the TEST
section below.

For an overall rationale for this rework, see CB:88656.

References:
[1] coreboot board status: kernel_log.txt

TEST= All boards passed regression test (CB:88763)

Change-Id: I36cccc7033b3df523ff1c0d1891ef194090fe50e
Signed-off-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88658
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
---
 src/mainboard/acer/aspire_vn7_572g/Kconfig    |  1 -
 src/mainboard/acer/aspire_vn7_572g/hda_verb.c | 32 ++++++++++++-----
 src/mainboard/acer/g43t-am3/Kconfig           |  1 -
 src/mainboard/acer/g43t-am3/hda_verb.c        | 36 ++++++++++++-------
 4 files changed, 46 insertions(+), 24 deletions(-)

diff --git a/src/mainboard/acer/aspire_vn7_572g/Kconfig b/src/mainboard/acer/aspire_vn7_572g/Kconfig
index 166b9435af..cee7b7ec0a 100644
--- a/src/mainboard/acer/aspire_vn7_572g/Kconfig
+++ b/src/mainboard/acer/aspire_vn7_572g/Kconfig
@@ -4,7 +4,6 @@ if BOARD_ACER_VN7_572G
 
 config BOARD_SPECIFIC_OPTIONS
 	def_bool y
-	select AZALIA_USE_LEGACY_VERB_TABLE
 	select BOARD_ROMSIZE_KB_8192
 	select DRIVERS_I2C_HID
 	select DRIVERS_USB_ACPI
diff --git a/src/mainboard/acer/aspire_vn7_572g/hda_verb.c b/src/mainboard/acer/aspire_vn7_572g/hda_verb.c
index 20197d1d22..233e72d9fb 100644
--- a/src/mainboard/acer/aspire_vn7_572g/hda_verb.c
+++ b/src/mainboard/acer/aspire_vn7_572g/hda_verb.c
@@ -4,12 +4,8 @@
 
 #include <device/azalia_device.h>
 
-const u32 cim_verb_data[] = {
+static const u32 realtek_alc255_verbs[] = {
 	/* --- Codec #0 --- */
-	/* coreboot specific header */
-	0x10ec0255,	/* Codec Vendor / Device ID: Realtek ALC255 */
-	0x10251037,	/* Subsystem ID */
-	20,		/* Number of jacks (NID entries) */
 
 	/* Codec Address: Bits 31:28 */
 	/* Node ID: Bits 27:20 */
@@ -81,12 +77,10 @@ const u32 cim_verb_data[] = {
 	0x01470740,	/* Repeated for units? */
 	0x02050010,	/* Set coeff idx: 0x10 */
 	0x02040f20,	/* Set processing coeff: 0xf20 */
+};
 
+static const u32 intel_display_audio_verbs[] = {
 	/* --- Codec #2 --- */
-	/* coreboot specific header */
-	0x80862809,	/* Codec Vendor / Device ID: Intel Skylake HDMI */
-	0x80860101,	/* Subsystem ID */
-	5,		/* Number of jacks (NID entries) */
 
 	/* Codec Address: Bits 31:28 */
 	/* Node ID: Bits 27:20 */
@@ -115,4 +109,24 @@ const u32 cim_verb_data[] = {
 
 const u32 pc_beep_verbs[] = {};
 
+struct azalia_codec mainboard_azalia_codecs[] = {
+	{
+		.name         = "Realtek ALC255",
+		.vendor_id    = 0x10ec0255,
+		.subsystem_id = 0x10251037,
+		.address      = 0,
+		.verbs        = realtek_alc255_verbs,
+		.verb_count   = ARRAY_SIZE(realtek_alc255_verbs),
+	},
+	{
+		.name         = "Intel Display Audio (HDMI/DP)",
+		.vendor_id    = 0x80862809,
+		.subsystem_id = 0x80860101,
+		.address      = 2,
+		.verbs        = intel_display_audio_verbs,
+		.verb_count   = ARRAY_SIZE(intel_display_audio_verbs),
+	},
+	{ /* terminator */ }
+};
+
 AZALIA_ARRAY_SIZES;
diff --git a/src/mainboard/acer/g43t-am3/Kconfig b/src/mainboard/acer/g43t-am3/Kconfig
index 466c5b9bf4..77ce9d4ca1 100644
--- a/src/mainboard/acer/g43t-am3/Kconfig
+++ b/src/mainboard/acer/g43t-am3/Kconfig
@@ -4,7 +4,6 @@ if BOARD_ACER_G43T_AM3 || BOARD_ACER_Q45T_AM
 
 config BOARD_SPECIFIC_OPTIONS
 	def_bool y
-	select AZALIA_USE_LEGACY_VERB_TABLE
 	select CPU_INTEL_SOCKET_LGA775
 	select NORTHBRIDGE_INTEL_X4X
 	select SOUTHBRIDGE_INTEL_I82801JX
diff --git a/src/mainboard/acer/g43t-am3/hda_verb.c b/src/mainboard/acer/g43t-am3/hda_verb.c
index a47fe03865..38db6eb941 100644
--- a/src/mainboard/acer/g43t-am3/hda_verb.c
+++ b/src/mainboard/acer/g43t-am3/hda_verb.c
@@ -2,14 +2,7 @@
 
 #include <device/azalia_device.h>
 
-const u32 cim_verb_data[] = {
-	/* coreboot specific header */
-	0x10ec0888,
-	0x1025024c,	// Subsystem ID
-	14,	// Number of entries
-
-	/* Pin Widget Verb Table */
-
+static const u32 realtek_alc888_verbs[] = {
 	AZALIA_PIN_CFG(0, 0x11, 0x014b7140),
 	AZALIA_PIN_CFG(0, 0x12, AZALIA_PIN_CFG_NC(0)),
 	AZALIA_PIN_CFG(0, 0x14, 0x01014010),
@@ -24,15 +17,32 @@ const u32 cim_verb_data[] = {
 	AZALIA_PIN_CFG(0, 0x1d, AZALIA_PIN_CFG_NC(0)),
 	AZALIA_PIN_CFG(0, 0x1e, 0x18567130),
 	AZALIA_PIN_CFG(0, 0x1f, AZALIA_PIN_CFG_NC(0)),
+};
 
-	/* HDMI */
-	0x80862803,
-	0x80860101,
-	1,
-
+static const u32 intel_display_audio_verbs[] = {
 	AZALIA_PIN_CFG(0, 0x03, 0x18560010)
 };
 
 const u32 pc_beep_verbs[0] = {};
 
+struct azalia_codec mainboard_azalia_codecs[] = {
+	{
+		.name         = "Realtek ALC888",
+		.vendor_id    = 0x10ec0888,
+		.subsystem_id = 0x1025024c,
+		.address      = 0,
+		.verbs        = realtek_alc888_verbs,
+		.verb_count   = ARRAY_SIZE(realtek_alc888_verbs),
+	},
+	{
+		.name         = "Intel Display Audio (HDMI/DP)",
+		.vendor_id    = 0x80862803,
+		.subsystem_id = 0x80860101,
+		.address      = 0,
+		.verbs        = intel_display_audio_verbs,
+		.verb_count   = ARRAY_SIZE(intel_display_audio_verbs),
+	},
+	{ /* terminator */ }
+};
+
 AZALIA_ARRAY_SIZES;

From 970249694f85dd4ee1fbffedc84bfda6c08a9c19 Mon Sep 17 00:00:00 2001
From: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Date: Thu, 7 Aug 2025 09:18:03 +0900
Subject: [PATCH 2139/3886] mb/amd: Replace verb tables with reworked
 implementation

No modifications/assumptions about the codecs were made on these boards.

The Kconfigs were reverted using the following command:
  find src/mainboard/amd -name 'Kconfig' | xargs git checkout main

It should be noted that we do not modifiy the verb tables in any case,
as it would break the regression test script mentioned in the TEST
section below.

For an overall rationale for this rework, see CB:88656.

TEST= All boards passed regression test (CB:88763)

Change-Id: Ie8dcff7caa24ec9f671159ea39a46989a98a6fbc
Signed-off-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88659
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
---
 src/mainboard/amd/bilby/Kconfig        |  1 -
 src/mainboard/amd/bilby/hda_verb.c     | 36 ++++++++++++++++++--------
 src/mainboard/amd/mandolin/Kconfig     |  1 -
 src/mainboard/amd/mandolin/hda_verb.c  | 36 ++++++++++++++++++--------
 src/mainboard/amd/pademelon/Kconfig    |  1 -
 src/mainboard/amd/pademelon/hda_verb.c | 23 +++++++++-------
 6 files changed, 64 insertions(+), 34 deletions(-)

diff --git a/src/mainboard/amd/bilby/Kconfig b/src/mainboard/amd/bilby/Kconfig
index be80b70c27..95732046b0 100644
--- a/src/mainboard/amd/bilby/Kconfig
+++ b/src/mainboard/amd/bilby/Kconfig
@@ -4,7 +4,6 @@ if BOARD_AMD_BILBY
 
 config BOARD_SPECIFIC_OPTIONS
 	def_bool y
-	select AZALIA_USE_LEGACY_VERB_TABLE
 	select SOC_AMD_PICASSO
 	select BOARD_ROMSIZE_KB_16384
 	select AZALIA_HDA_CODEC_SUPPORT
diff --git a/src/mainboard/amd/bilby/hda_verb.c b/src/mainboard/amd/bilby/hda_verb.c
index b5c65e8098..7db6e172cd 100644
--- a/src/mainboard/amd/bilby/hda_verb.c
+++ b/src/mainboard/amd/bilby/hda_verb.c
@@ -2,12 +2,7 @@
 
 #include <device/azalia_device.h>
 
-const u32 cim_verb_data[] = {
-	/* Realtek ALC701 on mainboard */
-	0x10ec0701,
-	0x00000000,
-	0x00000016,
-
+static const u32 realtek_alc701_verbs[] = {
 	AZALIA_SUBVENDOR(0, 0x1022D001), // HDA Codec Subsystem ID: 0x1022D001
 
 	AZALIA_RESET(1), // Widget node 0x01 :
@@ -34,12 +29,9 @@ const u32 cim_verb_data[] = {
 	0x0205004a, 0x0204201b, 0x0205004a, 0x0204201b, // NID 0x20 - 2
 	0x02050010, 0x02040420, 0x01470c00, 0x02050036, // Dos beep path - 1
 	0x02047151, 0x01470740, 0x0143b000, 0x01470c02, // Dos beep path - 2
+};
 
-	/* Realtek ALC285 on extension card */
-	0x10ec0285,
-	0x00000000,
-	0x00000028,
-
+static const u32 realtek_alc285_verbs[] = {
 	AZALIA_SUBVENDOR(0, 0x1022D002),
 
 	AZALIA_RESET(1), // Widget node 0x01 :
@@ -94,4 +86,26 @@ const u32 cim_verb_data[] = {
 const u32 pc_beep_verbs[] = {
 };
 
+struct azalia_codec mainboard_azalia_codecs[] = {
+	{
+		/* Realtek ALC701 on mainboard */
+		.name         = "Realtek ALC701",
+		.vendor_id    = 0x10ec0701,
+		.subsystem_id = 0x00000000,
+		.address      = 0,
+		.verbs        = realtek_alc701_verbs,
+		.verb_count   = ARRAY_SIZE(realtek_alc701_verbs),
+	},
+	{
+		/* Realtek ALC285 on extension card */
+		.name         = "Realtek ALC285",
+		.vendor_id    = 0x10ec0285,
+		.subsystem_id = 0x00000000,
+		.address      = 0,
+		.verbs        = realtek_alc285_verbs,
+		.verb_count   = ARRAY_SIZE(realtek_alc285_verbs),
+	},
+	{ /* terminator */ }
+};
+
 AZALIA_ARRAY_SIZES;
diff --git a/src/mainboard/amd/mandolin/Kconfig b/src/mainboard/amd/mandolin/Kconfig
index 47d8debb68..ce3af3ba74 100644
--- a/src/mainboard/amd/mandolin/Kconfig
+++ b/src/mainboard/amd/mandolin/Kconfig
@@ -4,7 +4,6 @@ if BOARD_AMD_MANDOLIN || BOARD_AMD_CEREME
 
 config BOARD_SPECIFIC_OPTIONS
 	def_bool y
-	select AZALIA_USE_LEGACY_VERB_TABLE
 	select SOC_AMD_COMMON_BLOCK_USE_ESPI
 	select SOC_AMD_PICASSO
 	select BOARD_ROMSIZE_KB_8192 if BOARD_AMD_MANDOLIN
diff --git a/src/mainboard/amd/mandolin/hda_verb.c b/src/mainboard/amd/mandolin/hda_verb.c
index b5c65e8098..7db6e172cd 100644
--- a/src/mainboard/amd/mandolin/hda_verb.c
+++ b/src/mainboard/amd/mandolin/hda_verb.c
@@ -2,12 +2,7 @@
 
 #include <device/azalia_device.h>
 
-const u32 cim_verb_data[] = {
-	/* Realtek ALC701 on mainboard */
-	0x10ec0701,
-	0x00000000,
-	0x00000016,
-
+static const u32 realtek_alc701_verbs[] = {
 	AZALIA_SUBVENDOR(0, 0x1022D001), // HDA Codec Subsystem ID: 0x1022D001
 
 	AZALIA_RESET(1), // Widget node 0x01 :
@@ -34,12 +29,9 @@ const u32 cim_verb_data[] = {
 	0x0205004a, 0x0204201b, 0x0205004a, 0x0204201b, // NID 0x20 - 2
 	0x02050010, 0x02040420, 0x01470c00, 0x02050036, // Dos beep path - 1
 	0x02047151, 0x01470740, 0x0143b000, 0x01470c02, // Dos beep path - 2
+};
 
-	/* Realtek ALC285 on extension card */
-	0x10ec0285,
-	0x00000000,
-	0x00000028,
-
+static const u32 realtek_alc285_verbs[] = {
 	AZALIA_SUBVENDOR(0, 0x1022D002),
 
 	AZALIA_RESET(1), // Widget node 0x01 :
@@ -94,4 +86,26 @@ const u32 cim_verb_data[] = {
 const u32 pc_beep_verbs[] = {
 };
 
+struct azalia_codec mainboard_azalia_codecs[] = {
+	{
+		/* Realtek ALC701 on mainboard */
+		.name         = "Realtek ALC701",
+		.vendor_id    = 0x10ec0701,
+		.subsystem_id = 0x00000000,
+		.address      = 0,
+		.verbs        = realtek_alc701_verbs,
+		.verb_count   = ARRAY_SIZE(realtek_alc701_verbs),
+	},
+	{
+		/* Realtek ALC285 on extension card */
+		.name         = "Realtek ALC285",
+		.vendor_id    = 0x10ec0285,
+		.subsystem_id = 0x00000000,
+		.address      = 0,
+		.verbs        = realtek_alc285_verbs,
+		.verb_count   = ARRAY_SIZE(realtek_alc285_verbs),
+	},
+	{ /* terminator */ }
+};
+
 AZALIA_ARRAY_SIZES;
diff --git a/src/mainboard/amd/pademelon/Kconfig b/src/mainboard/amd/pademelon/Kconfig
index 5a06a60bbe..b31971d95e 100644
--- a/src/mainboard/amd/pademelon/Kconfig
+++ b/src/mainboard/amd/pademelon/Kconfig
@@ -4,7 +4,6 @@ if BOARD_AMD_PADEMELON
 
 config BOARD_SPECIFIC_OPTIONS
 	def_bool y
-	select AZALIA_USE_LEGACY_VERB_TABLE
 	select SOC_AMD_STONEYRIDGE
 	select AMD_APU_PKG_FP4
 	select BOARD_ROMSIZE_KB_8192
diff --git a/src/mainboard/amd/pademelon/hda_verb.c b/src/mainboard/amd/pademelon/hda_verb.c
index 5bef966e75..447896142b 100644
--- a/src/mainboard/amd/pademelon/hda_verb.c
+++ b/src/mainboard/amd/pademelon/hda_verb.c
@@ -2,15 +2,7 @@
 
 #include <device/azalia_device.h>
 
-const u32 cim_verb_data[] = {
-	/* coreboot specific header */
-	/* Realtek ALC662 rev1 */
-	0x10ec0662, /* Vendor ID */
-	0x80865756, /* Subsystem ID */
-	10, /* Number of entries */
-
-	/* Pin Widget Verb Table */
-
+static const u32 realtek_alc662_verbs[] = {
 	AZALIA_PIN_CFG(0, 0x14, 0x01014010),
 	AZALIA_PIN_CFG(0, 0x15, AZALIA_PIN_CFG_NC(0)),
 	AZALIA_PIN_CFG(0, 0x16, AZALIA_PIN_CFG_NC(0)),
@@ -23,6 +15,19 @@ const u32 cim_verb_data[] = {
 	AZALIA_PIN_CFG(0, 0x1e, 0x01441130),
 };
 
+
 const u32 pc_beep_verbs[0] = {};
 
+struct azalia_codec mainboard_azalia_codecs[] = {
+	{
+		.name         = "Realtek ALC662",
+		.vendor_id    = 0x10ec0662,
+		.subsystem_id = 0x80865756,
+		.address      = 0,
+		.verbs        = realtek_alc662_verbs,
+		.verb_count   = ARRAY_SIZE(realtek_alc662_verbs),
+	},
+	{ /* terminator */ }
+};
+
 AZALIA_ARRAY_SIZES;

From 2b7dbf80c981b7892d4a2077e0ccfe9775e1db1f Mon Sep 17 00:00:00 2001
From: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Date: Thu, 7 Aug 2025 09:18:32 +0900
Subject: [PATCH 2140/3886] mb/apple: Replace verb tables with reworked
 implementation

Some boards did not provide the chip name for the audio codecs in the
comments, and therefore we made the following assumptions based off the
vendor ID:

  macbookair4_2:
    - 0x10134206 -> Cirrus Logic CS4206[1]

It should be noted that some factors (e.g. revision) can cause the chip
name to differ even with the same vendor ID. This is especially common
for Realtek audio codecs.

The Kconfigs were reverted using the following command:
  find src/mainboard/apple -name 'Kconfig' | xargs git checkout main

It should be noted that we do not modifiy the verb tables in any case,
as it would break the regression test script mentioned in the TEST
section below.

For an overall rationale for this rework, see CB:88656.

References:
[1] Linux kernel: sound/hda/codecs/cirrus/cs420x.c:770

TEST= All boards passed regression test (CB:88763)

Change-Id: I1fcfa0e5e1af27dc5b0dc77bf471a7636b361cbe
Signed-off-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88660
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
---
 src/mainboard/apple/macbook21/Kconfig        |  1 -
 src/mainboard/apple/macbook21/hda_verb.c     | 28 ++++++++++++------
 src/mainboard/apple/macbookair4_2/Kconfig    |  1 -
 src/mainboard/apple/macbookair4_2/hda_verb.c | 30 +++++++++++++++-----
 4 files changed, 43 insertions(+), 17 deletions(-)

diff --git a/src/mainboard/apple/macbook21/Kconfig b/src/mainboard/apple/macbook21/Kconfig
index b8880120db..330d8efae2 100644
--- a/src/mainboard/apple/macbook21/Kconfig
+++ b/src/mainboard/apple/macbook21/Kconfig
@@ -4,7 +4,6 @@ if BOARD_APPLE_MACBOOK11 || BOARD_APPLE_MACBOOK21 || BOARD_APPLE_IMAC52
 
 config BOARD_SPECIFIC_OPTIONS
 	def_bool y
-	select AZALIA_USE_LEGACY_VERB_TABLE
 	select SYSTEM_TYPE_LAPTOP
 	select CPU_INTEL_SOCKET_M
 	select NORTHBRIDGE_INTEL_I945
diff --git a/src/mainboard/apple/macbook21/hda_verb.c b/src/mainboard/apple/macbook21/hda_verb.c
index 9146b3fdfc..d06fc0170f 100644
--- a/src/mainboard/apple/macbook21/hda_verb.c
+++ b/src/mainboard/apple/macbook21/hda_verb.c
@@ -2,11 +2,10 @@
 
 #include <device/azalia_device.h>
 
-const u32 cim_verb_data[] = {
-	0x83847680,	/* Codec Vendor / Device ID: SigmaTel STAC9221 A1 */
 #if CONFIG(BOARD_APPLE_MACBOOK11) || CONFIG(BOARD_APPLE_MACBOOK21)
-	0x106b2200,	/* Subsystem ID  */
-	11,		/* Number of 4 dword sets */
+static const u32 sigmatel_stac9221_a1_subsystem_id = 0x106b2200;
+
+static const u32 sigmatel_stac9221_a1_verbs[] = {
 	AZALIA_SUBVENDOR(0, 0x106b2200),
 	AZALIA_PIN_CFG(0, 0x0a, 0x0321e21f),
 	AZALIA_PIN_CFG(0, 0x0b, 0x03a1e02e),
@@ -18,9 +17,11 @@ const u32 cim_verb_data[] = {
 	AZALIA_PIN_CFG(0, 0x11, 0x13c5e240),
 	AZALIA_PIN_CFG(0, 0x15, 0x400000fc),
 	AZALIA_PIN_CFG(0, 0x1b, 0x400000fb),
+};
 #else /* CONFIG_BOARD_APPLE_IMAC52 */
-	0x106b0f00,	/* Subsystem ID  */
-	11,		/* Number of 4 dword sets */
+static const u32 sigmatel_stac9221_a1_subsystem_id = 0x106b0f00;
+
+static const u32 sigmatel_stac9221_a1_verbs[] = {
 	AZALIA_SUBVENDOR(0, 0x106b0f00),
 	AZALIA_PIN_CFG(0, 0x0a, 0x012be032),
 	AZALIA_PIN_CFG(0, 0x0b, 0x90afe111),
@@ -32,10 +33,21 @@ const u32 cim_verb_data[] = {
 	AZALIA_PIN_CFG(0, 0x11, 0x11cbc022),
 	AZALIA_PIN_CFG(0, 0x15, 0x4080e10f),
 	AZALIA_PIN_CFG(0, 0x1b, 0x4080e10f),
-#endif
-
 };
+#endif
 
 const u32 pc_beep_verbs[0] = {};
 
+struct azalia_codec mainboard_azalia_codecs[] = {
+	{
+		.name         = "Sigmatel STAC9221 A1",
+		.vendor_id    = 0x83847680,
+		.subsystem_id = sigmatel_stac9221_a1_subsystem_id,
+		.address      = 0,
+		.verbs        = sigmatel_stac9221_a1_verbs,
+		.verb_count   = ARRAY_SIZE(sigmatel_stac9221_a1_verbs),
+	},
+	{ /* terminator */ }
+};
+
 AZALIA_ARRAY_SIZES;
diff --git a/src/mainboard/apple/macbookair4_2/Kconfig b/src/mainboard/apple/macbookair4_2/Kconfig
index f340761bb1..39b14a2487 100644
--- a/src/mainboard/apple/macbookair4_2/Kconfig
+++ b/src/mainboard/apple/macbookair4_2/Kconfig
@@ -4,7 +4,6 @@ if BOARD_APPLE_MACBOOKAIR4_2
 
 config BOARD_SPECIFIC_OPTIONS
 	def_bool y
-	select AZALIA_USE_LEGACY_VERB_TABLE
 	select BOARD_ROMSIZE_KB_8192
 	select EC_ACPI
 	select HAVE_ACPI_RESUME
diff --git a/src/mainboard/apple/macbookair4_2/hda_verb.c b/src/mainboard/apple/macbookair4_2/hda_verb.c
index d2acefbaa7..d855862f49 100644
--- a/src/mainboard/apple/macbookair4_2/hda_verb.c
+++ b/src/mainboard/apple/macbookair4_2/hda_verb.c
@@ -2,10 +2,7 @@
 
 #include <device/azalia_device.h>
 
-const u32 cim_verb_data[] = {
-	0x10134206,	/* Codec Vendor / Device ID: Cirrus */
-	0x106b5b00,	/* Subsystem ID */
-	11,		/* Number of 4 dword sets */
+static const u32 cirrus_logic_cs4206_verbs[] = {
 	AZALIA_SUBVENDOR(0, 0x106b5b00),
 	AZALIA_PIN_CFG(0, 0x09, 0x012b4030),
 	AZALIA_PIN_CFG(0, 0x0a, 0x400000f0),
@@ -17,10 +14,9 @@ const u32 cim_verb_data[] = {
 	AZALIA_PIN_CFG(0, 0x10, 0x400000f0),
 	AZALIA_PIN_CFG(0, 0x12, 0x400000f0),
 	AZALIA_PIN_CFG(0, 0x15, 0x400000f0),
+};
 
-	0x80862805,	/* Codec Vendor / Device ID: Intel */
-	0x80860101,	/* Subsystem ID */
-	4,		/* Number of 4 dword sets */
+static const u32 intel_display_audio_verbs[] = {
 	AZALIA_SUBVENDOR(3, 0x80860101),
 	AZALIA_PIN_CFG(3, 0x05, 0x18560010),
 	AZALIA_PIN_CFG(3, 0x06, 0x18560010),
@@ -29,4 +25,24 @@ const u32 cim_verb_data[] = {
 
 const u32 pc_beep_verbs[0] = {};
 
+struct azalia_codec mainboard_azalia_codecs[] = {
+	{
+		.name         = "Cirrus Logic CS4206",
+		.vendor_id    = 0x10134206,
+		.subsystem_id = 0x106b5b00,
+		.address      = 0,
+		.verbs        = cirrus_logic_cs4206_verbs,
+		.verb_count   = ARRAY_SIZE(cirrus_logic_cs4206_verbs),
+	},
+	{
+		.name         = "Intel Display Audio (HDMI/DP)",
+		.vendor_id    = 0x80862805,
+		.subsystem_id = 0x80860101,
+		.address      = 3,
+		.verbs        = intel_display_audio_verbs,
+		.verb_count   = ARRAY_SIZE(intel_display_audio_verbs),
+	},
+	{ /* terminator */ }
+};
+
 AZALIA_ARRAY_SIZES;

From 20d4042458323eb2cfe8ed90f10ab762086a35f4 Mon Sep 17 00:00:00 2001
From: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Date: Thu, 7 Aug 2025 09:18:52 +0900
Subject: [PATCH 2141/3886] mb/asrock: Replace verb tables with reworked
 implementation

Some boards did not provide the chip name for the audio codecs in the
comments, and therefore we made the following assumptions based off the
vendor ID:

  fatal1ty_z87_professional:
    - 0x11020011 -> Creative CA0132[3]

It should be noted that some factors (e.g. revision) can cause the chip
name to differ even with the same vendor ID. This is especially common
for Realtek audio codecs.

The following chip names were identified using external sources:

  b75m-itx:
    - 0x10ec0892 -> Realtek ALC892[1][5]
  b75pro3-m:
    - 0x10ec0892 -> Realtek ALC892[2]
  z87_extreme3:
    - 0x10ec0892 -> Realtek ALC892[1][6]
  z87_extreme4:
    - 0x10ec0900 -> Realtek ALC1150[4][7]
  z87_pro4:
    - 0x10ec0892 -> Realtek ALC892[1][8]
  z87e-itx:
    - 0x10ec0900 -> Realtek ALC1150[4][9]
  z87m_extreme4:
    - 0x10ec0900 -> Realtek ALC1150[4][10]
  z87m_oc_formula:
    - 0x10ec0900 -> Realtek ALC1150[4][11]

The Kconfigs were reverted using the following command:
  find src/mainboard/asrock -name 'Kconfig' | xargs git checkout main

It should be noted that we do not modifiy the verb tables in any case,
as it would break the regression test script mentioned in the TEST
section below.

For an overall rationale for this rework, see CB:88656.

References:
[1]  Linux kernel: sound/hda/codecs/realtek/alc662.c:1101
[2]  coreboot board status: kernel_log.txt
[3]  Linux kernel: sound/hda/codecs/ca0132.c:10144
[4]  Linux kernel: sound/hda/codecs/realtek/alc882.c:844
[5]  https://www.asrock.com/mb/Intel/B75M-ITX/index.asp
[6]  https://www.asrock.com/mb/intel/Z87%20Extreme3/
[7]  https://www.asrock.com/mb/intel/Z87%20Extreme4/
[8]  https://www.asrock.com/mb/Intel/Z87%20Pro4/
[9]  https://www.asrock.com/mb/Intel/Z87E-ITX/
[10] https://www.asrock.com/mb/Intel/Z87M%20Extreme4/index.asp
[11] https://www.asrock.com/mb/intel/z87m%20oc%20formula/

TEST= All boards passed regression test (CB:88763)

Change-Id: I60ba4e8e048dfbf8ca5969251fd448ce3644d9e0
Signed-off-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88661
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
---
 src/mainboard/asrock/b75m-itx/Kconfig         |  1 -
 src/mainboard/asrock/b75m-itx/hda_verb.c      | 30 +++++++---
 src/mainboard/asrock/b75pro3-m/Kconfig        |  1 -
 src/mainboard/asrock/b75pro3-m/hda_verb.c     | 30 +++++++---
 src/mainboard/asrock/b85m_pro4/Kconfig        |  1 -
 src/mainboard/asrock/b85m_pro4/hda_verb.c     | 43 ++++++++++----
 .../asrock/fatal1ty_z87_professional/Kconfig  |  1 -
 .../fatal1ty_z87_professional/hda_verb.c      | 18 ++++--
 src/mainboard/asrock/g41c-gs/Kconfig          |  1 -
 src/mainboard/asrock/g41c-gs/hda_verb.c       | 57 +++++++++++--------
 src/mainboard/asrock/h110m/Kconfig            |  1 -
 src/mainboard/asrock/h110m/hda_verb.c         | 31 +++++++---
 src/mainboard/asrock/h77pro4-m/Kconfig        |  1 -
 src/mainboard/asrock/h77pro4-m/hda_verb.c     | 30 +++++++---
 src/mainboard/asrock/h81m-hds/Kconfig         |  1 -
 src/mainboard/asrock/h81m-hds/hda_verb.c      | 17 ++++--
 src/mainboard/asrock/imb-1222/Kconfig         |  1 -
 src/mainboard/asrock/imb-1222/hda_verb.c      | 30 +++++++---
 src/mainboard/asrock/z87_extreme3/Kconfig     |  1 -
 src/mainboard/asrock/z87_extreme3/hda_verb.c  | 17 ++++--
 src/mainboard/asrock/z87_extreme4/Kconfig     |  1 -
 src/mainboard/asrock/z87_extreme4/hda_verb.c  | 17 ++++--
 src/mainboard/asrock/z87_pro4/Kconfig         |  1 -
 src/mainboard/asrock/z87_pro4/hda_verb.c      | 17 ++++--
 src/mainboard/asrock/z87e-itx/Kconfig         |  1 -
 src/mainboard/asrock/z87e-itx/hda_verb.c      | 17 ++++--
 src/mainboard/asrock/z87m_extreme4/Kconfig    |  1 -
 src/mainboard/asrock/z87m_extreme4/hda_verb.c | 17 ++++--
 src/mainboard/asrock/z87m_oc_formula/Kconfig  |  1 -
 .../asrock/z87m_oc_formula/hda_verb.c         | 17 ++++--
 src/mainboard/asrock/z97_extreme6/Kconfig     |  1 -
 src/mainboard/asrock/z97_extreme6/hda_verb.c  | 17 ++++--
 src/mainboard/asrock/z97e-itx_ac/Kconfig      |  1 -
 src/mainboard/asrock/z97e-itx_ac/hda_verb.c   | 17 ++++--
 34 files changed, 312 insertions(+), 127 deletions(-)

diff --git a/src/mainboard/asrock/b75m-itx/Kconfig b/src/mainboard/asrock/b75m-itx/Kconfig
index 47634047a2..b882d6b8fc 100644
--- a/src/mainboard/asrock/b75m-itx/Kconfig
+++ b/src/mainboard/asrock/b75m-itx/Kconfig
@@ -4,7 +4,6 @@ if BOARD_ASROCK_B75M_ITX
 
 config BOARD_SPECIFIC_OPTIONS
 	def_bool y
-	select AZALIA_USE_LEGACY_VERB_TABLE
 	select BOARD_ROMSIZE_KB_8192
 	select HAVE_ACPI_RESUME
 	select HAVE_ACPI_TABLES
diff --git a/src/mainboard/asrock/b75m-itx/hda_verb.c b/src/mainboard/asrock/b75m-itx/hda_verb.c
index 37f763ed65..b06bb37a5b 100644
--- a/src/mainboard/asrock/b75m-itx/hda_verb.c
+++ b/src/mainboard/asrock/b75m-itx/hda_verb.c
@@ -2,10 +2,7 @@
 
 #include <device/azalia_device.h>
 
-const u32 cim_verb_data[] = {
-	0x10ec0892,	/* Codec Vendor / Device ID: Realtek */
-	0x18498892,	/* Subsystem ID */
-	15,		/* Number of 4 dword sets */
+static const u32 realtek_alc892_verbs[] = {
 	AZALIA_SUBVENDOR(0, 0x18498892),
 	AZALIA_PIN_CFG(0, 0x11, AZALIA_PIN_CFG_NC(0)),
 	AZALIA_PIN_CFG(0, 0x12, AZALIA_PIN_CFG_NC(0)),
@@ -21,10 +18,9 @@ const u32 cim_verb_data[] = {
 	AZALIA_PIN_CFG(0, 0x1d, 0x4005e601),
 	AZALIA_PIN_CFG(0, 0x1e, 0x01452130),
 	AZALIA_PIN_CFG(0, 0x1f, AZALIA_PIN_CFG_NC(0)),
+};
 
-	0x80862806,	/* Codec Vendor / Device ID: Intel */
-	0x80860101,	/* Subsystem ID */
-	4,		/* Number of 4 dword sets */
+static const u32 intel_display_audio_verbs[] = {
 	AZALIA_SUBVENDOR(3, 0x80860101),
 	AZALIA_PIN_CFG(3, 0x05, 0x18560010),
 	AZALIA_PIN_CFG(3, 0x06, 0x18560020),
@@ -33,4 +29,24 @@ const u32 cim_verb_data[] = {
 
 const u32 pc_beep_verbs[0] = {};
 
+struct azalia_codec mainboard_azalia_codecs[] = {
+	{
+		.name         = "Realtek ALC892",
+		.vendor_id    = 0x10ec0892,
+		.subsystem_id = 0x18498892,
+		.address      = 0,
+		.verbs        = realtek_alc892_verbs,
+		.verb_count   = ARRAY_SIZE(realtek_alc892_verbs),
+	},
+	{
+		.name         = "Intel Display Audio (HDMI/DP)",
+		.vendor_id    = 0x80862806,
+		.subsystem_id = 0x80860101,
+		.address      = 3,
+		.verbs        = intel_display_audio_verbs,
+		.verb_count   = ARRAY_SIZE(intel_display_audio_verbs),
+	},
+	{ /* terminator */ }
+};
+
 AZALIA_ARRAY_SIZES;
diff --git a/src/mainboard/asrock/b75pro3-m/Kconfig b/src/mainboard/asrock/b75pro3-m/Kconfig
index f7231c14d9..17d737f196 100644
--- a/src/mainboard/asrock/b75pro3-m/Kconfig
+++ b/src/mainboard/asrock/b75pro3-m/Kconfig
@@ -4,7 +4,6 @@ if BOARD_ASROCK_B75PRO3_M
 
 config BOARD_SPECIFIC_OPTIONS
 	def_bool y
-	select AZALIA_USE_LEGACY_VERB_TABLE
 	select BOARD_ROMSIZE_KB_8192
 	select DRIVERS_ASMEDIA_ASM1061
 	select HAVE_ACPI_RESUME
diff --git a/src/mainboard/asrock/b75pro3-m/hda_verb.c b/src/mainboard/asrock/b75pro3-m/hda_verb.c
index a3d894d6a1..d4250c185b 100644
--- a/src/mainboard/asrock/b75pro3-m/hda_verb.c
+++ b/src/mainboard/asrock/b75pro3-m/hda_verb.c
@@ -2,10 +2,7 @@
 
 #include <device/azalia_device.h>
 
-const u32 cim_verb_data[] = {
-	0x10ec0892,	/* Codec Vendor / Device ID: Realtek */
-	0x18498892,	/* Subsystem ID */
-	15,		/* Number of 4 dword sets */
+static const u32 realtek_alc892_verbs[] = {
 	AZALIA_SUBVENDOR(0, 0x18498892),
 	AZALIA_PIN_CFG(0, 0x11, AZALIA_PIN_CFG_NC(0)),
 	AZALIA_PIN_CFG(0, 0x12, AZALIA_PIN_CFG_NC(0)),
@@ -21,10 +18,9 @@ const u32 cim_verb_data[] = {
 	AZALIA_PIN_CFG(0, 0x1d, 0x4005e601),
 	AZALIA_PIN_CFG(0, 0x1e, 0x01452130),
 	AZALIA_PIN_CFG(0, 0x1f, AZALIA_PIN_CFG_NC(0)),
+};
 
-	0x80862806,	/* Codec Vendor / Device ID: Intel */
-	0x80860101,	/* Subsystem ID */
-	4,		/* Number of 4 dword sets */
+static const u32 intel_display_audio_verbs[] = {
 	AZALIA_SUBVENDOR(3, 0x80860101),
 	AZALIA_PIN_CFG(3, 0x05, 0x18560010),
 	AZALIA_PIN_CFG(3, 0x06, 0x18560020),
@@ -33,4 +29,24 @@ const u32 cim_verb_data[] = {
 
 const u32 pc_beep_verbs[0] = {};
 
+struct azalia_codec mainboard_azalia_codecs[] = {
+	{
+		.name         = "Realtek ALC892",
+		.vendor_id    = 0x10ec0892,
+		.subsystem_id = 0x18498892,
+		.address      = 0,
+		.verbs        = realtek_alc892_verbs,
+		.verb_count   = ARRAY_SIZE(realtek_alc892_verbs),
+	},
+	{
+		.name         = "Intel Display Audio (HDMI/DP)",
+		.vendor_id    = 0x80862806,
+		.subsystem_id = 0x80860101,
+		.address      = 3,
+		.verbs        = intel_display_audio_verbs,
+		.verb_count   = ARRAY_SIZE(intel_display_audio_verbs),
+	},
+	{ /* terminator */ }
+};
+
 AZALIA_ARRAY_SIZES;
diff --git a/src/mainboard/asrock/b85m_pro4/Kconfig b/src/mainboard/asrock/b85m_pro4/Kconfig
index 883547fdd1..65da20d4e0 100644
--- a/src/mainboard/asrock/b85m_pro4/Kconfig
+++ b/src/mainboard/asrock/b85m_pro4/Kconfig
@@ -4,7 +4,6 @@ if BOARD_ASROCK_B85M_PRO4
 
 config BOARD_SPECIFIC_OPTIONS
 	def_bool y
-	select AZALIA_USE_LEGACY_VERB_TABLE
 	select BOARD_ROMSIZE_KB_8192
 	select HAVE_ACPI_RESUME
 	select HAVE_ACPI_TABLES
diff --git a/src/mainboard/asrock/b85m_pro4/hda_verb.c b/src/mainboard/asrock/b85m_pro4/hda_verb.c
index 8b908c516c..39425d2e41 100644
--- a/src/mainboard/asrock/b85m_pro4/hda_verb.c
+++ b/src/mainboard/asrock/b85m_pro4/hda_verb.c
@@ -2,10 +2,7 @@
 
 #include <device/azalia_device.h>
 
-const u32 cim_verb_data[] = {
-	0x10ec0892,	/* Codec Vendor / Device ID: Realtek ALC892 */
-	0x1849c892,	/* Subsystem ID */
-	11,		/* Number of 4 dword sets */
+static const u32 realtek_alc892_verbs[] = {
 	AZALIA_SUBVENDOR(0, 0x1849c892),
 	AZALIA_PIN_CFG(0, 0x12, AZALIA_PIN_CFG_NC(0)),
 	AZALIA_PIN_CFG(0, 0x14, 0x01014020),
@@ -17,10 +14,9 @@ const u32 cim_verb_data[] = {
 	AZALIA_PIN_CFG(0, 0x1d, 0x598301f0),
 	AZALIA_PIN_CFG(0, 0x1e, AZALIA_PIN_CFG_NC(0)),
 	AZALIA_PIN_CFG(0, 0x21, 0x0221102f),
+};
 
-	0x10ec0887,	/* Codec Vendor / Device ID: Realtek ALC887 */
-	0x1458a002,	/* Subsystem ID */
-	15,		/* Number of 4 dword sets */
+static const u32 realtek_alc887_verbs[] = {
 	AZALIA_SUBVENDOR(2, 0x1458a002),
 	AZALIA_PIN_CFG(2, 0x11, 0x411110f0),
 	AZALIA_PIN_CFG(2, 0x12, AZALIA_PIN_CFG_NC(0)),
@@ -36,10 +32,9 @@ const u32 cim_verb_data[] = {
 	AZALIA_PIN_CFG(2, 0x1d, 0x4004c601),
 	AZALIA_PIN_CFG(2, 0x1e, AZALIA_PIN_CFG_NC(0)),
 	AZALIA_PIN_CFG(2, 0x1f, 0x41c46060),
+};
 
-	0x80862806,	/* Codec Vendor / Device ID: Intel Haswell HDMI */
-	0x80860101,	/* Subsystem ID */
-	4,		/* Number of 4 dword sets */
+static const u32 intel_display_audio_verbs[] = {
 	AZALIA_SUBVENDOR(3, 0x80860101),
 	AZALIA_PIN_CFG(3, 0x05, 0x58560010),
 	AZALIA_PIN_CFG(3, 0x06, 0x18560020),
@@ -48,4 +43,32 @@ const u32 cim_verb_data[] = {
 
 const u32 pc_beep_verbs[0] = {};
 
+struct azalia_codec mainboard_azalia_codecs[] = {
+	{
+		.name         = "Realtek ALC892",
+		.vendor_id    = 0x10ec0892,
+		.subsystem_id = 0x1849c892,
+		.address      = 0,
+		.verbs        = realtek_alc892_verbs,
+		.verb_count   = ARRAY_SIZE(realtek_alc892_verbs),
+	},
+	{
+		.name         = "Realtek ALC887",
+		.vendor_id    = 0x10ec0887,
+		.subsystem_id = 0x1458a002,
+		.address      = 2,
+		.verbs        = realtek_alc887_verbs,
+		.verb_count   = ARRAY_SIZE(realtek_alc887_verbs),
+	},
+	{
+		.name         = "Intel Display Audio (HDMI/DP)",
+		.vendor_id    = 0x80862806,
+		.subsystem_id = 0x80860101,
+		.address      = 3,
+		.verbs        = intel_display_audio_verbs,
+		.verb_count   = ARRAY_SIZE(intel_display_audio_verbs),
+	},
+	{ /* terminator */ }
+};
+
 AZALIA_ARRAY_SIZES;
diff --git a/src/mainboard/asrock/fatal1ty_z87_professional/Kconfig b/src/mainboard/asrock/fatal1ty_z87_professional/Kconfig
index 0081c11934..56bdad2d40 100644
--- a/src/mainboard/asrock/fatal1ty_z87_professional/Kconfig
+++ b/src/mainboard/asrock/fatal1ty_z87_professional/Kconfig
@@ -3,7 +3,6 @@ if BOARD_ASROCK_FATAL1TY_Z87_PROFESSIONAL
 
 config BOARD_SPECIFIC_OPTIONS
 	def_bool y
-	select AZALIA_USE_LEGACY_VERB_TABLE
 	select BOARD_ROMSIZE_KB_8192
 	select DRIVERS_ASMEDIA_ASM1061
 	select HAVE_ACPI_RESUME
diff --git a/src/mainboard/asrock/fatal1ty_z87_professional/hda_verb.c b/src/mainboard/asrock/fatal1ty_z87_professional/hda_verb.c
index 9c381e650d..9566ac3d07 100644
--- a/src/mainboard/asrock/fatal1ty_z87_professional/hda_verb.c
+++ b/src/mainboard/asrock/fatal1ty_z87_professional/hda_verb.c
@@ -2,10 +2,7 @@
 
 #include <device/azalia_device.h>
 
-const u32 cim_verb_data[] = {
-	0x11020011,	/* Codec Vendor / Device ID: Creative */
-	0x18491020,	/* Subsystem ID */
-	11,		/* Number of 4 dword sets */
+static const u32 creative_ca0132_verbs[] = {
 	AZALIA_SUBVENDOR(0, 0x18491020),
 	AZALIA_PIN_CFG(0, 0x0b, 0x01014010),
 	AZALIA_PIN_CFG(0, 0x0c, 0x014580f0),
@@ -17,9 +14,20 @@ const u32 cim_verb_data[] = {
 	AZALIA_PIN_CFG(0, 0x12, 0x37a791f0),
 	AZALIA_PIN_CFG(0, 0x13, 0x908700f0),
 	AZALIA_PIN_CFG(0, 0x18, 0x500000f0),
-
 };
 
 const u32 pc_beep_verbs[0] = {};
 
+struct azalia_codec mainboard_azalia_codecs[] = {
+	{
+		.name         = "Creative CA0132",
+		.vendor_id    = 0x11020011,
+		.subsystem_id = 0x18491020,
+		.address      = 0,
+		.verbs        = creative_ca0132_verbs,
+		.verb_count   = ARRAY_SIZE(creative_ca0132_verbs),
+	},
+	{ /* terminator */ }
+};
+
 AZALIA_ARRAY_SIZES;
diff --git a/src/mainboard/asrock/g41c-gs/Kconfig b/src/mainboard/asrock/g41c-gs/Kconfig
index 11f7d4f1a9..7ae84614a2 100644
--- a/src/mainboard/asrock/g41c-gs/Kconfig
+++ b/src/mainboard/asrock/g41c-gs/Kconfig
@@ -6,7 +6,6 @@ if BOARD_ASROCK_G41C_GS || BOARD_ASROCK_G41C_GS_R2_0 || \
 
 config BOARD_SPECIFIC_OPTIONS
 	def_bool y
-	select AZALIA_USE_LEGACY_VERB_TABLE
 	select CPU_INTEL_SOCKET_LGA775
 	select NORTHBRIDGE_INTEL_X4X
 	select SOUTHBRIDGE_INTEL_I82801GX
diff --git a/src/mainboard/asrock/g41c-gs/hda_verb.c b/src/mainboard/asrock/g41c-gs/hda_verb.c
index 134c34092f..467e9b3543 100644
--- a/src/mainboard/asrock/g41c-gs/hda_verb.c
+++ b/src/mainboard/asrock/g41c-gs/hda_verb.c
@@ -2,15 +2,7 @@
 
 #include <device/azalia_device.h>
 
-const u32 cim_verb_data[] = {
-	/* coreboot specific header */
-	/* Realtek ALC662 rev1 */
-	0x10ec0662, /* Vendor ID */
-	0x18493662, /* Subsystem ID */
-	10, /* Number of entries */
-
-	/* Pin Widget Verb Table */
-
+static const u32 realtek_alc662_verbs_1[] = {
 	AZALIA_PIN_CFG(0, 0x14, 0x01014010),
 	AZALIA_PIN_CFG(0, 0x15, AZALIA_PIN_CFG_NC(0)),
 	AZALIA_PIN_CFG(0, 0x16, AZALIA_PIN_CFG_NC(0)),
@@ -21,24 +13,13 @@ const u32 cim_verb_data[] = {
 	AZALIA_PIN_CFG(0, 0x1c, 0x593301f0),
 	AZALIA_PIN_CFG(0, 0x1d, 0x4004c601),
 	AZALIA_PIN_CFG(0, 0x1e, AZALIA_PIN_CFG_NC(0)),
+};
 
-	/* coreboot specific header */
-	/* Intel Eaglelake HDMI */
-	0x80862803, /* Vendor ID */
-	0x80860101, /* Subsystem ID */
-	0x00000001, /* Number of entries */
-
-	/* Pin Widget Verb Table */
-
+static const u32 intel_display_audio_verbs[] = {
 	AZALIA_PIN_CFG(1, 0x03, 0x18560010),
+};
 
-	/* coreboot specific header */
-	/* Realtek ALC662 rev1 */
-	0x10ec0662, /* Vendor ID */
-	0x1565821e, /* Subsystem ID */
-	10, /* Number of entries */
-
-	/* Pin Widget Verb Table */
+static const u32 realtek_alc662_verbs_2[] = {
 	AZALIA_PIN_CFG(2, 0x14, 0x01014410),
 	AZALIA_PIN_CFG(2, 0x15, AZALIA_PIN_CFG_NC(0)),
 	AZALIA_PIN_CFG(2, 0x16, AZALIA_PIN_CFG_NC(0)),
@@ -53,4 +34,32 @@ const u32 cim_verb_data[] = {
 
 const u32 pc_beep_verbs[0] = {};
 
+struct azalia_codec mainboard_azalia_codecs[] = {
+	{
+		.name         = "Realtek ALC662",
+		.vendor_id    = 0x10ec0662,
+		.subsystem_id = 0x18493662,
+		.address      = 0,
+		.verbs        = realtek_alc662_verbs_1,
+		.verb_count   = ARRAY_SIZE(realtek_alc662_verbs_1),
+	},
+	{
+		.name         = "Intel Display Audio (HDMI/DP)",
+		.vendor_id    = 0x80862803,
+		.subsystem_id = 0x80860101,
+		.address      = 1,
+		.verbs        = intel_display_audio_verbs,
+		.verb_count   = ARRAY_SIZE(intel_display_audio_verbs),
+	},
+	{
+		.name         = "Realtek ALC662",
+		.vendor_id    = 0x10ec0662,
+		.subsystem_id = 0x1565821e,
+		.address      = 2,
+		.verbs        = realtek_alc662_verbs_2,
+		.verb_count   = ARRAY_SIZE(realtek_alc662_verbs_2),
+	},
+	{ /* terminator */ }
+};
+
 AZALIA_ARRAY_SIZES;
diff --git a/src/mainboard/asrock/h110m/Kconfig b/src/mainboard/asrock/h110m/Kconfig
index 344831f03a..a470b6628d 100644
--- a/src/mainboard/asrock/h110m/Kconfig
+++ b/src/mainboard/asrock/h110m/Kconfig
@@ -4,7 +4,6 @@ if BOARD_ASROCK_H110M_DVS
 
 config BOARD_SPECIFIC_OPTIONS
 	def_bool y
-	select AZALIA_USE_LEGACY_VERB_TABLE
 	select BOARD_ROMSIZE_KB_8192
 	select HAVE_ACPI_RESUME
 	select HAVE_ACPI_TABLES
diff --git a/src/mainboard/asrock/h110m/hda_verb.c b/src/mainboard/asrock/h110m/hda_verb.c
index a19634e6f4..cf346a82d2 100644
--- a/src/mainboard/asrock/h110m/hda_verb.c
+++ b/src/mainboard/asrock/h110m/hda_verb.c
@@ -2,10 +2,7 @@
 
 #include <device/azalia_device.h>
 
-const u32 cim_verb_data[] = {
-	0x10ec0887,	/* Codec Vendor / Device ID: Realtek ALC887 */
-	0x10438445,	/* Subsystem ID */
-	15,		/* Number of 4 dword sets */
+static const u32 realtek_alc887_verbs[] = {
 	AZALIA_SUBVENDOR(0, 0x10438445),
 	AZALIA_PIN_CFG(0, 0x11, 0x40000000),
 	AZALIA_PIN_CFG(0, 0x12, AZALIA_PIN_CFG_NC(0)),
@@ -21,10 +18,9 @@ const u32 cim_verb_data[] = {
 	AZALIA_PIN_CFG(0, 0x1d, 0x4026c629),
 	AZALIA_PIN_CFG(0, 0x1e, AZALIA_PIN_CFG_NC(0)),
 	AZALIA_PIN_CFG(0, 0x1f, AZALIA_PIN_CFG_NC(0)),
+};
 
-	0x80862809,	/* Codec Vendor / Device ID: Intel Skylake HDMI */
-	0x80860101,	/* Subsystem ID */
-	4,		/* Number of 4 dword sets */
+static const u32 intel_display_audio_verbs[] = {
 	AZALIA_SUBVENDOR(2, 0x80860101),
 	AZALIA_PIN_CFG(2, 0x05, 0x18560010),
 	AZALIA_PIN_CFG(2, 0x06, 0x18560020),
@@ -33,4 +29,25 @@ const u32 cim_verb_data[] = {
 
 const u32 pc_beep_verbs[] = {
 };
+
+struct azalia_codec mainboard_azalia_codecs[] = {
+	{
+		.name         = "Realtek ALC887",
+		.vendor_id    = 0x10ec0887,
+		.subsystem_id = 0x10438445,
+		.address      = 0,
+		.verbs        = realtek_alc887_verbs,
+		.verb_count   = ARRAY_SIZE(realtek_alc887_verbs),
+	},
+	{
+		.name         = "Intel Display Audio (HDMI/DP)",
+		.vendor_id    = 0x80862809,
+		.subsystem_id = 0x80860101,
+		.address      = 2,
+		.verbs        = intel_display_audio_verbs,
+		.verb_count   = ARRAY_SIZE(intel_display_audio_verbs),
+	},
+	{ /* terminator */ }
+};
+
 AZALIA_ARRAY_SIZES;
diff --git a/src/mainboard/asrock/h77pro4-m/Kconfig b/src/mainboard/asrock/h77pro4-m/Kconfig
index ab5d7b706a..a9918b5214 100644
--- a/src/mainboard/asrock/h77pro4-m/Kconfig
+++ b/src/mainboard/asrock/h77pro4-m/Kconfig
@@ -4,7 +4,6 @@ if BOARD_ASROCK_H77PRO4_M
 
 config BOARD_SPECIFIC_OPTIONS
 	def_bool y
-	select AZALIA_USE_LEGACY_VERB_TABLE
 	select BOARD_ROMSIZE_KB_8192
 	select DRIVERS_ASMEDIA_ASM1061
 	select HAVE_ACPI_RESUME
diff --git a/src/mainboard/asrock/h77pro4-m/hda_verb.c b/src/mainboard/asrock/h77pro4-m/hda_verb.c
index 7fbb3310a8..912ff52cf3 100644
--- a/src/mainboard/asrock/h77pro4-m/hda_verb.c
+++ b/src/mainboard/asrock/h77pro4-m/hda_verb.c
@@ -2,10 +2,7 @@
 
 #include <device/azalia_device.h>
 
-const u32 cim_verb_data[] = {
-	0x10ec0892,	/* Codec Vendor / Device ID: Realtek ALC892 */
-	0x18498892,	/* Subsystem ID */
-	15,		/* Number of 4 dword sets */
+static const u32 realtek_alc892_verbs[] = {
 	AZALIA_SUBVENDOR(0, 0x18498892),
 	AZALIA_PIN_CFG(0, 0x11, AZALIA_PIN_CFG_NC(0)),
 	AZALIA_PIN_CFG(0, 0x12, AZALIA_PIN_CFG_NC(0)),
@@ -21,10 +18,9 @@ const u32 cim_verb_data[] = {
 	AZALIA_PIN_CFG(0, 0x1d, 0x4005e601),
 	AZALIA_PIN_CFG(0, 0x1e, 0x01452130),
 	AZALIA_PIN_CFG(0, 0x1f, AZALIA_PIN_CFG_NC(0)),
+};
 
-	0x80862806,	/* Codec Vendor / Device ID: Intel */
-	0x80860101,	/* Subsystem ID */
-	4,		/* Number of 4 dword sets */
+static const u32 intel_display_audio_verbs[] = {
 	AZALIA_SUBVENDOR(3, 0x80860101),
 	AZALIA_PIN_CFG(3, 0x05, 0x18560010),
 	AZALIA_PIN_CFG(3, 0x06, 0x58560020),
@@ -33,4 +29,24 @@ const u32 cim_verb_data[] = {
 
 const u32 pc_beep_verbs[0] = {};
 
+struct azalia_codec mainboard_azalia_codecs[] = {
+	{
+		.name         = "Realtek ALC892",
+		.vendor_id    = 0x10ec0892,
+		.subsystem_id = 0x18498892,
+		.address      = 0,
+		.verbs        = realtek_alc892_verbs,
+		.verb_count   = ARRAY_SIZE(realtek_alc892_verbs),
+	},
+	{
+		.name         = "Intel Display Audio (HDMI/DP)",
+		.vendor_id    = 0x80862806,
+		.subsystem_id = 0x80860101,
+		.address      = 3,
+		.verbs        = intel_display_audio_verbs,
+		.verb_count   = ARRAY_SIZE(intel_display_audio_verbs),
+	},
+	{ /* terminator */ }
+};
+
 AZALIA_ARRAY_SIZES;
diff --git a/src/mainboard/asrock/h81m-hds/Kconfig b/src/mainboard/asrock/h81m-hds/Kconfig
index a3aff28514..4edd2bc387 100644
--- a/src/mainboard/asrock/h81m-hds/Kconfig
+++ b/src/mainboard/asrock/h81m-hds/Kconfig
@@ -4,7 +4,6 @@ if BOARD_ASROCK_H81M_HDS
 
 config BOARD_SPECIFIC_OPTIONS
 	def_bool y
-	select AZALIA_USE_LEGACY_VERB_TABLE
 	select BOARD_ROMSIZE_KB_4096
 	select HAVE_ACPI_RESUME
 	select HAVE_ACPI_TABLES
diff --git a/src/mainboard/asrock/h81m-hds/hda_verb.c b/src/mainboard/asrock/h81m-hds/hda_verb.c
index eea210d1d0..1a5620fd29 100644
--- a/src/mainboard/asrock/h81m-hds/hda_verb.c
+++ b/src/mainboard/asrock/h81m-hds/hda_verb.c
@@ -3,10 +3,7 @@
 #include <stdint.h>
 #include <device/azalia_device.h>
 
-const u32 cim_verb_data[] = {
-	0x10ec0662,	/* Realtek ALC662 rev1 */
-	0x18497662,	/* Subsystem ID */
-	11,		/* Number of entries */
+static const u32 realtek_alc662_verbs[] = {
 	AZALIA_SUBVENDOR(1, 0x18497662),
 	AZALIA_PIN_CFG(1, 0x14, 0x01014010),
 	AZALIA_PIN_CFG(1, 0x15, 0x40000000),
@@ -22,4 +19,16 @@ const u32 cim_verb_data[] = {
 
 const u32 pc_beep_verbs[] = {};
 
+struct azalia_codec mainboard_azalia_codecs[] = {
+	{
+		.name         = "Realtek ALC662",
+		.vendor_id    = 0x10ec0662,
+		.subsystem_id = 0x18497662,
+		.address      = 1,
+		.verbs        = realtek_alc662_verbs,
+		.verb_count   = ARRAY_SIZE(realtek_alc662_verbs),
+	},
+	{ /* terminator */ }
+};
+
 AZALIA_ARRAY_SIZES;
diff --git a/src/mainboard/asrock/imb-1222/Kconfig b/src/mainboard/asrock/imb-1222/Kconfig
index dc40a3bc4a..93fe111acd 100644
--- a/src/mainboard/asrock/imb-1222/Kconfig
+++ b/src/mainboard/asrock/imb-1222/Kconfig
@@ -4,7 +4,6 @@ if BOARD_ASROCK_IMB_1222
 
 config BOARD_SPECIFIC_OPTIONS
 	def_bool y
-	select AZALIA_USE_LEGACY_VERB_TABLE
 	select BOARD_ROMSIZE_KB_32768
 	select HAVE_ACPI_RESUME
 	select HAVE_ACPI_TABLES
diff --git a/src/mainboard/asrock/imb-1222/hda_verb.c b/src/mainboard/asrock/imb-1222/hda_verb.c
index c058d5e9ea..9997db894c 100644
--- a/src/mainboard/asrock/imb-1222/hda_verb.c
+++ b/src/mainboard/asrock/imb-1222/hda_verb.c
@@ -2,10 +2,7 @@
 
 #include <device/azalia_device.h>
 
-const u32 cim_verb_data[] = {
-	0x10ec0887,	/* Realtek ALC887-VD */
-	0x1849588a,	/* Subsystem ID */
-	15,		/* Number of 4 dword sets */
+static const u32 realtek_alc887_vd_verbs[] = {
 	AZALIA_SUBVENDOR(0, 0x1849588a),
 	AZALIA_PIN_CFG(0, 0x11, 0x40000000),
 	AZALIA_PIN_CFG(0, 0x12, AZALIA_PIN_CFG_NC(0)),
@@ -21,10 +18,9 @@ const u32 cim_verb_data[] = {
 	AZALIA_PIN_CFG(0, 0x1d, 0x4024c601),
 	AZALIA_PIN_CFG(0, 0x1e, 0x01451140),
 	AZALIA_PIN_CFG(0, 0x1f, AZALIA_PIN_CFG_NC(0)),
+};
 
-	0x8086280b,	/* Intel Kabylake HDMI */
-	0x80860101,	/* Subsystem ID */
-	4,		/* Number of 4 dword sets */
+static const u32 intel_display_audio_verbs[] = {
 	AZALIA_SUBVENDOR(2, 0x80860101),
 	AZALIA_PIN_CFG(2, 0x05, 0x18560010),
 	AZALIA_PIN_CFG(2, 0x06, 0x18560020),
@@ -34,4 +30,24 @@ const u32 cim_verb_data[] = {
 const u32 pc_beep_verbs[] = {
 };
 
+struct azalia_codec mainboard_azalia_codecs[] = {
+	{
+		.name         = "Realtek ALC887-VD",
+		.vendor_id    = 0x10ec0887,
+		.subsystem_id = 0x1849588a,
+		.address      = 0,
+		.verbs        = realtek_alc887_vd_verbs,
+		.verb_count   = ARRAY_SIZE(realtek_alc887_vd_verbs),
+	},
+	{
+		.name         = "Intel Display Audio (HDMI/DP)",
+		.vendor_id    = 0x8086280b,
+		.subsystem_id = 0x80860101,
+		.address      = 2,
+		.verbs        = intel_display_audio_verbs,
+		.verb_count   = ARRAY_SIZE(intel_display_audio_verbs),
+	},
+	{ /* terminator */ }
+};
+
 AZALIA_ARRAY_SIZES;
diff --git a/src/mainboard/asrock/z87_extreme3/Kconfig b/src/mainboard/asrock/z87_extreme3/Kconfig
index 42d10ccd2e..0b03123a7d 100644
--- a/src/mainboard/asrock/z87_extreme3/Kconfig
+++ b/src/mainboard/asrock/z87_extreme3/Kconfig
@@ -4,7 +4,6 @@ if BOARD_ASROCK_Z87_EXTREME3
 
 config BOARD_SPECIFIC_OPTIONS
 	def_bool y
-	select AZALIA_USE_LEGACY_VERB_TABLE
 	select BOARD_ROMSIZE_KB_8192
 	select HAVE_ACPI_RESUME
 	select HAVE_ACPI_TABLES
diff --git a/src/mainboard/asrock/z87_extreme3/hda_verb.c b/src/mainboard/asrock/z87_extreme3/hda_verb.c
index 8c07b9822b..550c58923d 100644
--- a/src/mainboard/asrock/z87_extreme3/hda_verb.c
+++ b/src/mainboard/asrock/z87_extreme3/hda_verb.c
@@ -2,10 +2,7 @@
 
 #include <device/azalia_device.h>
 
-const u32 cim_verb_data[] = {
-	0x10ec0892,	/* Codec Vendor / Device ID: Realtek */
-	0x1849c892,	/* Subsystem ID */
-	15,		/* Number of 4 dword sets */
+static const u32 realtek_alc892_verbs[] = {
 	AZALIA_SUBVENDOR(0, 0x1849c892),
 	AZALIA_PIN_CFG(0, 0x11, 0x411111f0),
 	AZALIA_PIN_CFG(0, 0x12, 0x411111f0),
@@ -25,4 +22,16 @@ const u32 cim_verb_data[] = {
 
 const u32 pc_beep_verbs[0] = {};
 
+struct azalia_codec mainboard_azalia_codecs[] = {
+	{
+		.name         = "Realtek ALC892",
+		.vendor_id    = 0x10ec0892,
+		.subsystem_id = 0x1849c892,
+		.address      = 0,
+		.verbs        = realtek_alc892_verbs,
+		.verb_count   = ARRAY_SIZE(realtek_alc892_verbs),
+	},
+	{ /* terminator */ }
+};
+
 AZALIA_ARRAY_SIZES;
diff --git a/src/mainboard/asrock/z87_extreme4/Kconfig b/src/mainboard/asrock/z87_extreme4/Kconfig
index 518ddc8b21..f2a2e7c723 100644
--- a/src/mainboard/asrock/z87_extreme4/Kconfig
+++ b/src/mainboard/asrock/z87_extreme4/Kconfig
@@ -4,7 +4,6 @@ if BOARD_ASROCK_Z87_EXTREME4
 
 config BOARD_SPECIFIC_OPTIONS
 	def_bool y
-	select AZALIA_USE_LEGACY_VERB_TABLE
 	select BOARD_ROMSIZE_KB_8192
 	select DRIVERS_ASMEDIA_ASM1061
 	select HAVE_ACPI_RESUME
diff --git a/src/mainboard/asrock/z87_extreme4/hda_verb.c b/src/mainboard/asrock/z87_extreme4/hda_verb.c
index ab7da869de..1399a3f3fb 100644
--- a/src/mainboard/asrock/z87_extreme4/hda_verb.c
+++ b/src/mainboard/asrock/z87_extreme4/hda_verb.c
@@ -2,10 +2,7 @@
 
 #include <device/azalia_device.h>
 
-const u32 cim_verb_data[] = {
-	0x10ec0900,	/* Codec Vendor / Device ID: Realtek */
-	0x18491151,	/* Subsystem ID */
-	11,		/* Number of 4 dword sets */
+static const u32 realtek_alc1150_verbs[] = {
 	AZALIA_SUBVENDOR(0, 0x18491151),
 	AZALIA_PIN_CFG(0, 0x11, 0x40000000),
 	AZALIA_PIN_CFG(0, 0x14, 0x01014010),
@@ -21,4 +18,16 @@ const u32 cim_verb_data[] = {
 
 const u32 pc_beep_verbs[0] = {};
 
+struct azalia_codec mainboard_azalia_codecs[] = {
+	{
+		.name         = "Realtek ALC1150",
+		.vendor_id    = 0x10ec0900,
+		.subsystem_id = 0x18491151,
+		.address      = 0,
+		.verbs        = realtek_alc1150_verbs,
+		.verb_count   = ARRAY_SIZE(realtek_alc1150_verbs),
+	},
+	{ /* terminator */ }
+};
+
 AZALIA_ARRAY_SIZES;
diff --git a/src/mainboard/asrock/z87_pro4/Kconfig b/src/mainboard/asrock/z87_pro4/Kconfig
index f65674a2b7..dee318d726 100644
--- a/src/mainboard/asrock/z87_pro4/Kconfig
+++ b/src/mainboard/asrock/z87_pro4/Kconfig
@@ -4,7 +4,6 @@ if BOARD_ASROCK_Z87_PRO4
 
 config BOARD_SPECIFIC_OPTIONS
 	def_bool y
-	select AZALIA_USE_LEGACY_VERB_TABLE
 	select BOARD_ROMSIZE_KB_8192
 	select HAVE_ACPI_RESUME
 	select HAVE_ACPI_TABLES
diff --git a/src/mainboard/asrock/z87_pro4/hda_verb.c b/src/mainboard/asrock/z87_pro4/hda_verb.c
index 038ad1f01f..2ac4972e4b 100644
--- a/src/mainboard/asrock/z87_pro4/hda_verb.c
+++ b/src/mainboard/asrock/z87_pro4/hda_verb.c
@@ -2,10 +2,7 @@
 
 #include <device/azalia_device.h>
 
-const u32 cim_verb_data[] = {
-	0x10ec0892,	/* Codec Vendor / Device ID: Realtek */
-	0x18498892,	/* Subsystem ID */
-	15,		/* Number of 4 dword sets */
+static const u32 realtek_alc892_verbs[] = {
 	AZALIA_SUBVENDOR(0, 0x18498892),
 	AZALIA_PIN_CFG(0, 0x11, 0x40000000),
 	AZALIA_PIN_CFG(0, 0x12, 0x411111f0),
@@ -25,4 +22,16 @@ const u32 cim_verb_data[] = {
 
 const u32 pc_beep_verbs[0] = {};
 
+struct azalia_codec mainboard_azalia_codecs[] = {
+	{
+		.name         = "Realtek ALC892",
+		.vendor_id    = 0x10ec0892,
+		.subsystem_id = 0x18498892,
+		.address      = 0,
+		.verbs        = realtek_alc892_verbs,
+		.verb_count   = ARRAY_SIZE(realtek_alc892_verbs),
+	},
+	{ /* terminator */ }
+};
+
 AZALIA_ARRAY_SIZES;
diff --git a/src/mainboard/asrock/z87e-itx/Kconfig b/src/mainboard/asrock/z87e-itx/Kconfig
index 3e1b308cf2..9eebc90e68 100644
--- a/src/mainboard/asrock/z87e-itx/Kconfig
+++ b/src/mainboard/asrock/z87e-itx/Kconfig
@@ -4,7 +4,6 @@ if BOARD_ASROCK_Z87E_ITX
 
 config BOARD_SPECIFIC_OPTIONS
 	def_bool y
-	select AZALIA_USE_LEGACY_VERB_TABLE
 	select BOARD_ROMSIZE_KB_8192
 	select GFX_GMA_ANALOG_I2C_HDMI_B
 	select HAVE_ACPI_RESUME
diff --git a/src/mainboard/asrock/z87e-itx/hda_verb.c b/src/mainboard/asrock/z87e-itx/hda_verb.c
index 7164c57149..ff58f69989 100644
--- a/src/mainboard/asrock/z87e-itx/hda_verb.c
+++ b/src/mainboard/asrock/z87e-itx/hda_verb.c
@@ -2,10 +2,7 @@
 
 #include <device/azalia_device.h>
 
-const u32 cim_verb_data[] = {
-	0x10ec0900,	/* Codec Vendor / Device ID: Realtek */
-	0x18491150,	/* Subsystem ID */
-	11,		/* Number of 4 dword sets */
+static const u32 realtek_alc1150_verbs[] = {
 	AZALIA_SUBVENDOR(0, 0x18491150),
 	AZALIA_PIN_CFG(0, 0x11, 0x40000000),
 	AZALIA_PIN_CFG(0, 0x14, 0x01014010),
@@ -21,4 +18,16 @@ const u32 cim_verb_data[] = {
 
 const u32 pc_beep_verbs[0] = {};
 
+struct azalia_codec mainboard_azalia_codecs[] = {
+	{
+		.name         = "Realtek ALC1150",
+		.vendor_id    = 0x10ec0900,
+		.subsystem_id = 0x18491150,
+		.address      = 0,
+		.verbs        = realtek_alc1150_verbs,
+		.verb_count   = ARRAY_SIZE(realtek_alc1150_verbs),
+	},
+	{ /* terminator */ }
+};
+
 AZALIA_ARRAY_SIZES;
diff --git a/src/mainboard/asrock/z87m_extreme4/Kconfig b/src/mainboard/asrock/z87m_extreme4/Kconfig
index 8b172fb62b..e02ac39cf0 100644
--- a/src/mainboard/asrock/z87m_extreme4/Kconfig
+++ b/src/mainboard/asrock/z87m_extreme4/Kconfig
@@ -4,7 +4,6 @@ if BOARD_ASROCK_Z87M_EXTREME4
 
 config BOARD_SPECIFIC_OPTIONS
 	def_bool y
-	select AZALIA_USE_LEGACY_VERB_TABLE
 	select BOARD_ROMSIZE_KB_8192
 	select HAVE_ACPI_RESUME
 	select HAVE_ACPI_TABLES
diff --git a/src/mainboard/asrock/z87m_extreme4/hda_verb.c b/src/mainboard/asrock/z87m_extreme4/hda_verb.c
index 912961cb09..b9d9e9d889 100644
--- a/src/mainboard/asrock/z87m_extreme4/hda_verb.c
+++ b/src/mainboard/asrock/z87m_extreme4/hda_verb.c
@@ -2,10 +2,7 @@
 
 #include <device/azalia_device.h>
 
-const u32 cim_verb_data[] = {
-	0x10ec0900,	/* Codec Vendor / Device ID: Realtek */
-	0x18491151,	/* Subsystem ID */
-	11,		/* Number of 4 dword sets */
+static const u32 realtek_alc1150_verbs[] = {
 	AZALIA_SUBVENDOR(0, 0x18491151),
 	AZALIA_PIN_CFG(0, 0x11, 0x40000000),
 	AZALIA_PIN_CFG(0, 0x14, 0x01014010),
@@ -21,4 +18,16 @@ const u32 cim_verb_data[] = {
 
 const u32 pc_beep_verbs[0] = {};
 
+struct azalia_codec mainboard_azalia_codecs[] = {
+	{
+		.name         = "Realtek ALC1150",
+		.vendor_id    = 0x10ec0900,
+		.subsystem_id = 0x18491151,
+		.address      = 0,
+		.verbs        = realtek_alc1150_verbs,
+		.verb_count   = ARRAY_SIZE(realtek_alc1150_verbs),
+	},
+	{ /* terminator */ }
+};
+
 AZALIA_ARRAY_SIZES;
diff --git a/src/mainboard/asrock/z87m_oc_formula/Kconfig b/src/mainboard/asrock/z87m_oc_formula/Kconfig
index 05f1536c00..c05f2fd85a 100644
--- a/src/mainboard/asrock/z87m_oc_formula/Kconfig
+++ b/src/mainboard/asrock/z87m_oc_formula/Kconfig
@@ -4,7 +4,6 @@ if BOARD_ASROCK_Z87M_OC_FORMULA
 
 config BOARD_SPECIFIC_OPTIONS
 	def_bool y
-	select AZALIA_USE_LEGACY_VERB_TABLE
 	select BOARD_ROMSIZE_KB_8192
 	select HAVE_ACPI_RESUME
 	select HAVE_ACPI_TABLES
diff --git a/src/mainboard/asrock/z87m_oc_formula/hda_verb.c b/src/mainboard/asrock/z87m_oc_formula/hda_verb.c
index ab7da869de..1399a3f3fb 100644
--- a/src/mainboard/asrock/z87m_oc_formula/hda_verb.c
+++ b/src/mainboard/asrock/z87m_oc_formula/hda_verb.c
@@ -2,10 +2,7 @@
 
 #include <device/azalia_device.h>
 
-const u32 cim_verb_data[] = {
-	0x10ec0900,	/* Codec Vendor / Device ID: Realtek */
-	0x18491151,	/* Subsystem ID */
-	11,		/* Number of 4 dword sets */
+static const u32 realtek_alc1150_verbs[] = {
 	AZALIA_SUBVENDOR(0, 0x18491151),
 	AZALIA_PIN_CFG(0, 0x11, 0x40000000),
 	AZALIA_PIN_CFG(0, 0x14, 0x01014010),
@@ -21,4 +18,16 @@ const u32 cim_verb_data[] = {
 
 const u32 pc_beep_verbs[0] = {};
 
+struct azalia_codec mainboard_azalia_codecs[] = {
+	{
+		.name         = "Realtek ALC1150",
+		.vendor_id    = 0x10ec0900,
+		.subsystem_id = 0x18491151,
+		.address      = 0,
+		.verbs        = realtek_alc1150_verbs,
+		.verb_count   = ARRAY_SIZE(realtek_alc1150_verbs),
+	},
+	{ /* terminator */ }
+};
+
 AZALIA_ARRAY_SIZES;
diff --git a/src/mainboard/asrock/z97_extreme6/Kconfig b/src/mainboard/asrock/z97_extreme6/Kconfig
index 2a9162c81e..3cef429d04 100644
--- a/src/mainboard/asrock/z97_extreme6/Kconfig
+++ b/src/mainboard/asrock/z97_extreme6/Kconfig
@@ -4,7 +4,6 @@ if BOARD_ASROCK_Z97_EXTREME6
 
 config BOARD_SPECIFIC_OPTIONS
 	def_bool y
-	select AZALIA_USE_LEGACY_VERB_TABLE
 	select BOARD_ROMSIZE_KB_8192
 	select GFX_GMA_ANALOG_I2C_HDMI_B
 	select HAVE_ACPI_RESUME
diff --git a/src/mainboard/asrock/z97_extreme6/hda_verb.c b/src/mainboard/asrock/z97_extreme6/hda_verb.c
index db4364c4e3..1399a3f3fb 100644
--- a/src/mainboard/asrock/z97_extreme6/hda_verb.c
+++ b/src/mainboard/asrock/z97_extreme6/hda_verb.c
@@ -2,10 +2,7 @@
 
 #include <device/azalia_device.h>
 
-const u32 cim_verb_data[] = {
-	0x10ec0900,	/* Codec Vendor / Device ID: Realtek ALC1150 */
-	0x18491151,	/* Subsystem ID */
-	11,		/* Number of 4 dword sets */
+static const u32 realtek_alc1150_verbs[] = {
 	AZALIA_SUBVENDOR(0, 0x18491151),
 	AZALIA_PIN_CFG(0, 0x11, 0x40000000),
 	AZALIA_PIN_CFG(0, 0x14, 0x01014010),
@@ -21,4 +18,16 @@ const u32 cim_verb_data[] = {
 
 const u32 pc_beep_verbs[0] = {};
 
+struct azalia_codec mainboard_azalia_codecs[] = {
+	{
+		.name         = "Realtek ALC1150",
+		.vendor_id    = 0x10ec0900,
+		.subsystem_id = 0x18491151,
+		.address      = 0,
+		.verbs        = realtek_alc1150_verbs,
+		.verb_count   = ARRAY_SIZE(realtek_alc1150_verbs),
+	},
+	{ /* terminator */ }
+};
+
 AZALIA_ARRAY_SIZES;
diff --git a/src/mainboard/asrock/z97e-itx_ac/Kconfig b/src/mainboard/asrock/z97e-itx_ac/Kconfig
index 7e20680253..810bfd0814 100644
--- a/src/mainboard/asrock/z97e-itx_ac/Kconfig
+++ b/src/mainboard/asrock/z97e-itx_ac/Kconfig
@@ -3,7 +3,6 @@ if BOARD_ASROCK_Z97E_ITX_AC
 
 config BOARD_SPECIFIC_OPTIONS
 	def_bool y
-	select AZALIA_USE_LEGACY_VERB_TABLE
 	select BOARD_ROMSIZE_KB_8192
 	select GFX_GMA_ANALOG_I2C_HDMI_B
 	select HAVE_ACPI_RESUME
diff --git a/src/mainboard/asrock/z97e-itx_ac/hda_verb.c b/src/mainboard/asrock/z97e-itx_ac/hda_verb.c
index 1eeed4cdf9..ff58f69989 100644
--- a/src/mainboard/asrock/z97e-itx_ac/hda_verb.c
+++ b/src/mainboard/asrock/z97e-itx_ac/hda_verb.c
@@ -2,10 +2,7 @@
 
 #include <device/azalia_device.h>
 
-const u32 cim_verb_data[] = {
-	0x10ec0900,	/* Codec Vendor / Device ID: Realtek ALC1150 */
-	0x18491150,	/* Subsystem ID */
-	11,		/* Number of 4 dword sets */
+static const u32 realtek_alc1150_verbs[] = {
 	AZALIA_SUBVENDOR(0, 0x18491150),
 	AZALIA_PIN_CFG(0, 0x11, 0x40000000),
 	AZALIA_PIN_CFG(0, 0x14, 0x01014010),
@@ -21,4 +18,16 @@ const u32 cim_verb_data[] = {
 
 const u32 pc_beep_verbs[0] = {};
 
+struct azalia_codec mainboard_azalia_codecs[] = {
+	{
+		.name         = "Realtek ALC1150",
+		.vendor_id    = 0x10ec0900,
+		.subsystem_id = 0x18491150,
+		.address      = 0,
+		.verbs        = realtek_alc1150_verbs,
+		.verb_count   = ARRAY_SIZE(realtek_alc1150_verbs),
+	},
+	{ /* terminator */ }
+};
+
 AZALIA_ARRAY_SIZES;

From f634121fa47648e204dfe8d70c90aca3be7194c0 Mon Sep 17 00:00:00 2001
From: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Date: Thu, 7 Aug 2025 09:25:42 +0900
Subject: [PATCH 2142/3886] mb/purism: Replace verb tables with reworked
 implementation

No modifications/assumptions about the codecs were made on these boards.

The Kconfigs were reverted using the following command:
  find src/mainboard/purism -name 'Kconfig' | xargs git checkout main

It should be noted that we do not modifiy the verb tables in any case,
as it would break the regression test script mentioned in the TEST
section below.

For an overall rationale for this rework, see CB:88656.

TEST= All boards passed regression test (CB:88763)

Change-Id: I2ee7a93392a57e8194cc8116c3fc55116336234f
Signed-off-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88686
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/purism/librem_bdw/Kconfig       |  1 -
 src/mainboard/purism/librem_bdw/hda_verb.c    | 18 ++++---
 src/mainboard/purism/librem_cnl/Kconfig       |  1 -
 .../librem_cnl/variants/librem_14/hda_verb.c  | 49 +++++++++++++------
 .../variants/librem_mini/hda_verb.c           | 31 ++++++++----
 src/mainboard/purism/librem_jsl/Kconfig       |  1 -
 src/mainboard/purism/librem_jsl/hda_verb.c    | 31 ++++++++----
 src/mainboard/purism/librem_skl/Kconfig       |  1 -
 src/mainboard/purism/librem_skl/hda_verb.c    | 18 ++++---
 9 files changed, 102 insertions(+), 49 deletions(-)

diff --git a/src/mainboard/purism/librem_bdw/Kconfig b/src/mainboard/purism/librem_bdw/Kconfig
index 8c8f5ec5fc..d1ba25a81a 100644
--- a/src/mainboard/purism/librem_bdw/Kconfig
+++ b/src/mainboard/purism/librem_bdw/Kconfig
@@ -2,7 +2,6 @@
 
 config BOARD_PURISM_BASEBOARD_LIBREM_BDW
 	def_bool n
-	select AZALIA_USE_LEGACY_VERB_TABLE
 	select SYSTEM_TYPE_LAPTOP
 	select BOARD_ROMSIZE_KB_8192
 	select HAVE_ACPI_RESUME
diff --git a/src/mainboard/purism/librem_bdw/hda_verb.c b/src/mainboard/purism/librem_bdw/hda_verb.c
index a3e87aad7b..1cf41265d7 100644
--- a/src/mainboard/purism/librem_bdw/hda_verb.c
+++ b/src/mainboard/purism/librem_bdw/hda_verb.c
@@ -2,12 +2,7 @@
 
 #include <device/azalia_device.h>
 
-const u32 cim_verb_data[] = {
-	/* coreboot specific header */
-	0x10ec0269,	/* Codec Vendor / Device ID: Realtek ALC269 */
-	0x19910269,	/* Subsystem ID */
-	12,		/* Number of jacks (NID entries) */
-
+static const u32 realtek_alc269_verbs[] = {
 	AZALIA_RESET(1),
 	AZALIA_SUBVENDOR(0, 0x19910269),
 	AZALIA_PIN_CFG(0, 0x12, 0x40000000),
@@ -24,4 +19,15 @@ const u32 cim_verb_data[] = {
 
 const u32 pc_beep_verbs[] = {};
 
+struct azalia_codec mainboard_azalia_codecs[] = {
+	{
+		.name         = "Realtek ALC269",
+		.vendor_id    = 0x10ec0269,
+		.subsystem_id = 0x19910269,
+		.address      = 0,
+		.verbs        = realtek_alc269_verbs,
+		.verb_count   = ARRAY_SIZE(realtek_alc269_verbs),
+	},
+};
+
 AZALIA_ARRAY_SIZES;
diff --git a/src/mainboard/purism/librem_cnl/Kconfig b/src/mainboard/purism/librem_cnl/Kconfig
index 9495365575..a718678605 100644
--- a/src/mainboard/purism/librem_cnl/Kconfig
+++ b/src/mainboard/purism/librem_cnl/Kconfig
@@ -2,7 +2,6 @@
 
 config BOARD_PURISM_BASEBOARD_LIBREM_CNL
 	def_bool n
-	select AZALIA_USE_LEGACY_VERB_TABLE
 	select BOARD_ROMSIZE_KB_16384
 	select DRIVERS_GENERIC_CBFS_SERIAL
 	select DRIVERS_USB_ACPI
diff --git a/src/mainboard/purism/librem_cnl/variants/librem_14/hda_verb.c b/src/mainboard/purism/librem_cnl/variants/librem_14/hda_verb.c
index 70b3247c74..912f955710 100644
--- a/src/mainboard/purism/librem_cnl/variants/librem_14/hda_verb.c
+++ b/src/mainboard/purism/librem_cnl/variants/librem_14/hda_verb.c
@@ -4,12 +4,7 @@
 #include <ec/purism/librem-ec/librem_ec.h>
 #include <console/console.h>
 
-const u32 cim_verb_data[] = {
-	/* Board revision 01 has ALC256 */
-	0x10ec0256,	/* Codec Vendor/Device ID: Realtek ALC256 */
-	0x10ec0256,	/* Subsystem ID */
-	16,		/* Number of entries */
-
+static const u32 realtek_alc256_verbs[] = {
 	AZALIA_RESET(0x1),
 
 	AZALIA_SUBVENDOR(0, 0x10ec0256),
@@ -47,12 +42,9 @@ const u32 cim_verb_data[] = {
 	0x02046901,
 	0x02050007,
 	0x02040200,
+};
 
-	/* Board revision 02 has ALC269 */
-	0x10ec0269,	/* Codec Vendor/Device ID: Realtek ALC269 */
-	0x10ec0269,	/* Subsystem ID */
-	16,		/* Number of entries */
-
+static const u32 realtek_alc269_verbs[] = {
 	AZALIA_RESET(0x1),
 
 	AZALIA_SUBVENDOR(0, 0x10ec129e),
@@ -86,11 +78,9 @@ const u32 cim_verb_data[] = {
 	0x020400AF,
 	0x02050005,
 	0x020400C0,
+};
 
-	0x8086280b,	/* Codec Vendor/Device ID: Intel CometPoint HDMI */
-	0x80860101,	/* Subsystem ID */
-	4,		/* Number of entries */
-
+static const u32 intel_display_audio_verbs[] = {
 	AZALIA_SUBVENDOR(2, 0x80860101),
 	AZALIA_PIN_CFG(2, 0x05, 0x18560010),
 	AZALIA_PIN_CFG(2, 0x06, 0x18560010),
@@ -99,6 +89,35 @@ const u32 cim_verb_data[] = {
 
 const u32 pc_beep_verbs[] = {};
 
+struct azalia_codec mainboard_azalia_codecs[] = {
+	{
+		/* Board revision 01 has ALC256 */
+		.name         = "Realtek ALC256",
+		.vendor_id    = 0x10ec0256,
+		.subsystem_id = 0x10ec0256,
+		.address      = 0,
+		.verbs        = realtek_alc256_verbs,
+		.verb_count   = ARRAY_SIZE(realtek_alc256_verbs),
+	},
+	{
+		/* Board revision 02 has ALC269 */
+		.name         = "Realtek ALC269",
+		.vendor_id    = 0x10ec0269,
+		.subsystem_id = 0x10ec0269,
+		.address      = 0,
+		.verbs        = realtek_alc269_verbs,
+		.verb_count   = ARRAY_SIZE(realtek_alc269_verbs),
+	},
+	{
+		.name         = "Intel Display Audio (HDMI/DP)",
+		.vendor_id    = 0x8086280b,
+		.subsystem_id = 0x80860101,
+		.address      = 2,
+		.verbs        = intel_display_audio_verbs,
+		.verb_count   = ARRAY_SIZE(intel_display_audio_verbs),
+	},
+};
+
 AZALIA_ARRAY_SIZES;
 
 /* Older ALC256 verbs with no jack detect - needed if an older Librem EC is in
diff --git a/src/mainboard/purism/librem_cnl/variants/librem_mini/hda_verb.c b/src/mainboard/purism/librem_cnl/variants/librem_mini/hda_verb.c
index 4734390ceb..978a33c57d 100644
--- a/src/mainboard/purism/librem_cnl/variants/librem_mini/hda_verb.c
+++ b/src/mainboard/purism/librem_cnl/variants/librem_mini/hda_verb.c
@@ -2,11 +2,7 @@
 
 #include <device/azalia_device.h>
 
-const u32 cim_verb_data[] = {
-	0x10ec0269,	/* Codec Vendor/Device ID: Realtek ALC269 */
-	0x10ec0269,	/* Subsystem ID */
-	12,		/* Number of entries */
-
+static const u32 realtek_alc269_verbs[] = {
 	AZALIA_RESET(0x1),
 
 	AZALIA_SUBVENDOR(0, 0x10ec0269),
@@ -20,11 +16,9 @@ const u32 cim_verb_data[] = {
 	AZALIA_PIN_CFG(0, 0x1b, AZALIA_PIN_CFG_NC(0)), /* NC */
 	AZALIA_PIN_CFG(0, 0x1d, AZALIA_PIN_CFG_NC(0)), /* NC */
 	AZALIA_PIN_CFG(0, 0x1e, AZALIA_PIN_CFG_NC(0)), /* NC */
+};
 
-	0x8086280b,	/* Codec Vendor/Device ID: Intel CannonPoint HDMI */
-	0x80860101,	/* Subsystem ID */
-	4,		/* Number of entries */
-
+static const u32 intel_display_audio_verbs[] = {
 	AZALIA_SUBVENDOR(2, 0x80860101),
 	AZALIA_PIN_CFG(2, 0x05, 0x18560010),
 	AZALIA_PIN_CFG(2, 0x06, 0x18560010),
@@ -33,4 +27,23 @@ const u32 cim_verb_data[] = {
 
 const u32 pc_beep_verbs[] = {};
 
+struct azalia_codec mainboard_azalia_codecs[] = {
+	{
+		.name         = "Realtek ALC269",
+		.vendor_id    = 0x10ec0269,
+		.subsystem_id = 0x10ec0269,
+		.address      = 0,
+		.verbs        = realtek_alc269_verbs,
+		.verb_count   = ARRAY_SIZE(realtek_alc269_verbs),
+	},
+	{
+		.name         = "Intel Display Audio (HDMI/DP)",
+		.vendor_id    = 0x8086280b,
+		.subsystem_id = 0x80860101,
+		.address      = 2,
+		.verbs        = intel_display_audio_verbs,
+		.verb_count   = ARRAY_SIZE(intel_display_audio_verbs),
+	},
+};
+
 AZALIA_ARRAY_SIZES;
diff --git a/src/mainboard/purism/librem_jsl/Kconfig b/src/mainboard/purism/librem_jsl/Kconfig
index b971bda207..2198dd60f8 100644
--- a/src/mainboard/purism/librem_jsl/Kconfig
+++ b/src/mainboard/purism/librem_jsl/Kconfig
@@ -2,7 +2,6 @@
 
 config BOARD_PURISM_BASEBOARD_LIBREM_JSL
 	def_bool n
-	select AZALIA_USE_LEGACY_VERB_TABLE
 	select BOARD_ROMSIZE_KB_16384
 	select DRIVERS_GENERIC_CBFS_SERIAL
 	select DRIVERS_USB_ACPI
diff --git a/src/mainboard/purism/librem_jsl/hda_verb.c b/src/mainboard/purism/librem_jsl/hda_verb.c
index 81e950acff..293b090e94 100644
--- a/src/mainboard/purism/librem_jsl/hda_verb.c
+++ b/src/mainboard/purism/librem_jsl/hda_verb.c
@@ -2,11 +2,7 @@
 
 #include <device/azalia_device.h>
 
-const u32 cim_verb_data[] = {
-	0x10ec0269,	/* Codec Vendor/Device ID: Realtek ALC269 */
-	0x10ec0269,	/* Subsystem ID */
-	16,		/* Number of entries */
-
+static const u32 realtek_alc269_verbs[] = {
 	AZALIA_RESET(0x1),
 
 	AZALIA_SUBVENDOR(0, 0x10ec0269),
@@ -41,11 +37,9 @@ const u32 cim_verb_data[] = {
 	0x020400AF,
 	0x02050005,
 	0x020400C0,
+};
 
-	0x8086281a,	/* Codec Vendor/Device ID: Intel Jasper Lake HDMI */
-	0x80860101,	/* Subsystem ID */
-	6,		/* Number of entries */
-
+static const u32 intel_display_audio_verbs[] = {
 	AZALIA_SUBVENDOR(2, 0x80860101),
 	AZALIA_PIN_CFG(2, 0x04, 0x18560010),
 	AZALIA_PIN_CFG(2, 0x06, 0x18560010),
@@ -56,4 +50,23 @@ const u32 cim_verb_data[] = {
 
 const u32 pc_beep_verbs[] = {};
 
+struct azalia_codec mainboard_azalia_codecs[] = {
+	{
+		.name         = "Realtek ALC269",
+		.vendor_id    = 0x10ec0269,
+		.subsystem_id = 0x10ec0269,
+		.address      = 0,
+		.verbs        = realtek_alc269_verbs,
+		.verb_count   = ARRAY_SIZE(realtek_alc269_verbs),
+	},
+	{
+		.name         = "Intel Display Audio (HDMI/DP)",
+		.vendor_id    = 0x8086281a,
+		.subsystem_id = 0x80860101,
+		.address      = 2,
+		.verbs        = intel_display_audio_verbs,
+		.verb_count   = ARRAY_SIZE(intel_display_audio_verbs),
+	},
+};
+
 AZALIA_ARRAY_SIZES;
diff --git a/src/mainboard/purism/librem_skl/Kconfig b/src/mainboard/purism/librem_skl/Kconfig
index f2f71572d5..5f3ed06cd4 100644
--- a/src/mainboard/purism/librem_skl/Kconfig
+++ b/src/mainboard/purism/librem_skl/Kconfig
@@ -2,7 +2,6 @@
 
 config BOARD_PURISM_BASEBOARD_LIBREM_SKL
 	def_bool n
-	select AZALIA_USE_LEGACY_VERB_TABLE
 	select BOARD_ROMSIZE_KB_16384
 	select DRIVERS_GENERIC_CBFS_SERIAL
 	select GFX_GMA_IGNORE_PRESENCE_STRAPS
diff --git a/src/mainboard/purism/librem_skl/hda_verb.c b/src/mainboard/purism/librem_skl/hda_verb.c
index 28f0362641..e308482497 100644
--- a/src/mainboard/purism/librem_skl/hda_verb.c
+++ b/src/mainboard/purism/librem_skl/hda_verb.c
@@ -2,12 +2,7 @@
 
 #include <device/azalia_device.h>
 
-const u32 cim_verb_data[] = {
-	/* coreboot specific header */
-	0x10ec0269,	/* Codec Vendor / Device ID: Realtek ALC269 */
-	0x19910269,	/* Subsystem ID */
-	12,		/* Number of jacks (NID entries) */
-
+static const u32 realtek_alc269_verbs[] = {
 	AZALIA_RESET(1),
 	AZALIA_SUBVENDOR(0, 0x19910269),
 	AZALIA_PIN_CFG(0, 0x12, 0x40000000),
@@ -24,4 +19,15 @@ const u32 cim_verb_data[] = {
 
 const u32 pc_beep_verbs[] = {};
 
+struct azalia_codec mainboard_azalia_codecs[] = {
+	{
+		.name         = "Realtek ALC269",
+		.vendor_id    = 0x10ec0269,
+		.subsystem_id = 0x19910269,
+		.address      = 0,
+		.verbs        = realtek_alc269_verbs,
+		.verb_count   = ARRAY_SIZE(realtek_alc269_verbs),
+	},
+};
+
 AZALIA_ARRAY_SIZES;

From bcc7fce590ccb57b18f0f107f010ca6a1156eb42 Mon Sep 17 00:00:00 2001
From: Riku Viitanen <riku.viitanen@protonmail.com>
Date: Thu, 25 Sep 2025 22:45:37 +0300
Subject: [PATCH 2143/3886] mb/topton/adl: Add TWL variant (X2E_N150)

Seems to be the same board but with a Twin Lake processor.
VBT extracted from vendor firmware. This makes HDMI and
DisplayPort work.

Change-Id: I1018042802cbb8010888847226a2117fd9dfaeb0
Signed-off-by: Riku Viitanen <riku.viitanen@protonmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89281
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/topton/adl/Kconfig      |  14 ++++++++++----
 src/mainboard/topton/adl/Kconfig.name |   3 +++
 src/mainboard/topton/adl/data_twl.vbt | Bin 0 -> 9216 bytes
 3 files changed, 13 insertions(+), 4 deletions(-)
 create mode 100644 src/mainboard/topton/adl/data_twl.vbt

diff --git a/src/mainboard/topton/adl/Kconfig b/src/mainboard/topton/adl/Kconfig
index 29d15300a6..f3c361c154 100644
--- a/src/mainboard/topton/adl/Kconfig
+++ b/src/mainboard/topton/adl/Kconfig
@@ -1,6 +1,6 @@
 ## SPDX-License-Identifier: GPL-2.0-or-later
 
-if BOARD_TOPTON_X2F_N100
+if BOARD_TOPTON_X2F_N100 || BOARD_TOPTON_X2E_N150
 
 config BOARD_SPECIFIC_OPTIONS
 	def_bool y
@@ -13,6 +13,7 @@ config BOARD_SPECIFIC_OPTIONS
 	select SUPERIO_ITE_IT8625E
 	select DRIVERS_UART_8250IO
 	select SOC_INTEL_ALDERLAKE_PCH_N
+	select SOC_INTEL_TWINLAKE if BOARD_TOPTON_X2E_N150
 	select INTEL_GMA_HAVE_VBT
 	select SOC_INTEL_COMMON_BLOCK_HDA_VERB
 	select HAVE_INTEL_PTT
@@ -21,7 +22,12 @@ config BOARD_SPECIFIC_OPTIONS
 config MAINBOARD_DIR
 	default "topton/adl"
 
-config MAINBOARD_PART_NUMBER
-	default "X2F_N100"
+config INTEL_GMA_VBT_FILE
+	default "src/mainboard/\$(MAINBOARDDIR)/data.vbt" if BOARD_TOPTON_X2F_N100
+	default "src/mainboard/\$(MAINBOARDDIR)/data_twl.vbt" if BOARD_TOPTON_X2E_N150
 
-endif # BOARD_TOPTON_X2F_N100
+config MAINBOARD_PART_NUMBER
+	default "X2F_N100" if BOARD_TOPTON_X2F_N100
+	default "X2E_N150" if BOARD_TOPTON_X2E_N150
+
+endif # BOARD_TOPTON_X2F_N100 || BOARD_TOPTON_X2E_N150
diff --git a/src/mainboard/topton/adl/Kconfig.name b/src/mainboard/topton/adl/Kconfig.name
index 5b8b5ff602..db0eef29be 100644
--- a/src/mainboard/topton/adl/Kconfig.name
+++ b/src/mainboard/topton/adl/Kconfig.name
@@ -2,3 +2,6 @@
 
 config BOARD_TOPTON_X2F_N100
 	bool "X2F_N100"
+
+config BOARD_TOPTON_X2E_N150
+	bool "X2E_N150"
diff --git a/src/mainboard/topton/adl/data_twl.vbt b/src/mainboard/topton/adl/data_twl.vbt
new file mode 100644
index 0000000000000000000000000000000000000000..05fbd5807365b3343e55ecedbd12fabb8a3199e9
GIT binary patch
literal 9216
zcmeHML2MgE6#cVnZ(QS$EeWj~+AvA0;DjbwJ8eiKOI^oKsN1BmoiuVKP~6mpM!1bh
zQ<Ng4E+U6qkoHnYD<ljO5(<}a;EYcw2q9TTAPykqMyWV})EjNgpV_rtrwuVJg{InX
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zl5}+Z#Q<e|wa)$vQ|Tl<e&Ot7YNn4OiGpbAJ<!>GfKuNJT}pSCPw^f^OP{x=@8F?Y
zXJ{ZeG8_pH1;)Z7$LUCnhQgzP(b0k7{-KjJ5*s-Z?hlU*gle4?Aq1y07iXqkJu^!^
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zu(;sj=bJ>vv%T&)C=`C!rs;HbkL*aa7_FOnF5%qI$}TF#h0PhVbrihu-PEHslo*T|
z99(Q}+MFS|3)BF#D(;0IgTdW%N#t7rWUzycG5B%K+c*lP9TuaYs7eOcR3;b&He@B&
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literal 0
HcmV?d00001


From 6f042c6ae48d80c2824562dc3cef6673d1a0ec61 Mon Sep 17 00:00:00 2001
From: Paul Menzel <pmenzel@molgen.mpg.de>
Date: Wed, 17 Sep 2025 23:36:24 +0200
Subject: [PATCH 2144/3886] lib: coreboot_tables: Fix grammar of *These
 information* in comment

*information* does not have plural, so use *This* instead of *These*.

Change-Id: I966373371cac4edd681f3b503e5f3a637fc28913
Fixes: a45c8441af2a ("lib: Add boot mode information to coreboot tables")
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89227
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/commonlib/include/commonlib/coreboot_tables.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/commonlib/include/commonlib/coreboot_tables.h b/src/commonlib/include/commonlib/coreboot_tables.h
index ab57ed0270..20f192436e 100644
--- a/src/commonlib/include/commonlib/coreboot_tables.h
+++ b/src/commonlib/include/commonlib/coreboot_tables.h
@@ -630,7 +630,7 @@ enum boot_mode_t {
 
 /*
  * Boot Mode: Pass the platform boot mode information to payload about
- * booting in low-battery mode or off-mode charging. These information
+ * booting in low-battery mode or off-mode charging. This information
  * is useful for payload to implement charger driver.
  */
 struct lb_boot_mode {

From 6d816b3b43a61e0462c43b26d538ecf46f63a801 Mon Sep 17 00:00:00 2001
From: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Date: Mon, 29 Sep 2025 07:28:55 +0900
Subject: [PATCH 2145/3886] mb/asus/h610i-plus-d4: Add missing
 AZALIA_USE_LEGACY_VERB_TABLE

When commit 50a59d446491 ("device: Add Kconfig to prepare for reworked
verb table implementation") was created this mainboard was not in the
main branch and therefore was not accounted for. However, since it got
merged right before the commit mentioned above was merged, there was no
time to add it.

Add this Kconfig to fix the build system from failing.

Change-Id: If7382125122b4d54332f52d922d8af84ba51763c
Signed-off-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89368
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
---
 src/mainboard/asus/h610i-plus-d4/Kconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/src/mainboard/asus/h610i-plus-d4/Kconfig b/src/mainboard/asus/h610i-plus-d4/Kconfig
index e4f7598066..5d76d2b508 100644
--- a/src/mainboard/asus/h610i-plus-d4/Kconfig
+++ b/src/mainboard/asus/h610i-plus-d4/Kconfig
@@ -1,6 +1,7 @@
 ## SPDX-License-Identifier: GPL-2.0-only
 
 config BOARD_ASUS_H610I_PLUS_D4
+	select AZALIA_USE_LEGACY_VERB_TABLE
 	select BOARD_ROMSIZE_KB_16384
 	select DRIVERS_UART_8250IO
 	select HAVE_ACPI_RESUME

From 16bf80b9b1614e7a400b914229768a127dbc1a3e Mon Sep 17 00:00:00 2001
From: Elyes Haouas <ehaouas@noos.fr>
Date: Fri, 26 Sep 2025 08:43:44 +0200
Subject: [PATCH 2146/3886] tests/imd: Fix invalid NULL comparison on uintptr_t

Use 0 instead of NULL when testing or initializing uintptr_t
fields, since NULL is only defined for pointers.

"data.3.lzma.bin" file is regenerated using:
  util/cbfs-compression-tool compress file.bin /tmp/file.lzma.bin lzma
  dd if=/tmp/file.lzma.bin of=file.lzma.bin skip=8 ibs=1

Change-Id: Ia1e7cc5052e842c7ef97ec7cec34919bbe1e2228
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89356
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jakub "Kuba" Czapiga <czapiga@google.com>
---
 tests/data/lib/lzma-test/data.3.bin      |   4 ++--
 tests/data/lib/lzma-test/data.3.lzma.bin | Bin 3865 -> 3859 bytes
 tests/lib/imd-test.c                     |   2 +-
 3 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/tests/data/lib/lzma-test/data.3.bin b/tests/data/lib/lzma-test/data.3.bin
index 6da1ac926c..f628a519e0 100644
--- a/tests/data/lib/lzma-test/data.3.bin
+++ b/tests/data/lib/lzma-test/data.3.bin
@@ -67,7 +67,7 @@ static void test_imd_handle_init(void **state)
 		assert_ptr_equal(imd.lg.r, NULL);
 
 		/* Small allocations not initialized */
-		assert_ptr_equal(imd.sm.limit, NULL);
+		assert_ptr_equal(imd.sm.limit, 0);
 		assert_ptr_equal(imd.sm.r, NULL);
 	}
 }
@@ -234,7 +234,7 @@ static void test_imd_recover(void **state)
 	const struct imd_entry *lg_entry;
 
 	/* Fail when the limit for lg was not set. */
-	imd.lg.limit = (uintptr_t) NULL;
+	imd.lg.limit = 0;
 	assert_int_equal(-1, imd_recover(&imd));
 
 	/* Set the limit for lg. */
diff --git a/tests/data/lib/lzma-test/data.3.lzma.bin b/tests/data/lib/lzma-test/data.3.lzma.bin
index ca20babe82602ccaeccd37c37cd36e40e9b08ddc..f77f5b34b06e4185318b0df09dffac2e75cb3ce5 100644
GIT binary patch
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diff --git a/tests/lib/imd-test.c b/tests/lib/imd-test.c
index b95b7424a7..1d46f10fe7 100644
--- a/tests/lib/imd-test.c
+++ b/tests/lib/imd-test.c
@@ -68,7 +68,7 @@ static void test_imd_handle_init(void **state)
 		assert_ptr_equal(imd.lg.r, NULL);
 
 		/* Small allocations not initialized */
-		assert_ptr_equal(imd.sm.limit, NULL);
+		assert_ptr_equal(imd.sm.limit, 0);
 		assert_ptr_equal(imd.sm.r, NULL);
 	}
 }

From 691a23a272fbaf70d65c8f49040650238a5e6b89 Mon Sep 17 00:00:00 2001
From: Cliff Huang <cliff.huang@intel.com>
Date: Sat, 27 Sep 2025 02:00:54 -0700
Subject: [PATCH 2147/3886] mb/google/fatcat: Fix WIFI driver device settings
 under root port 4
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

The commit addresses an issue with discrete WIFI driver configuration
under root port 4 in the Google Fatcat mainboard. The problem involved
incorrect probe settings that allowed the WIFI driver device to remain
enabled even when its upstream device was disabled. This led to orphan
devices being misidentified as root devices within the Intel Power
Engine (PEP) structure, which in turn caused unnecessary MCHC devices
to be added under the root port.

The fix involves ensuring that the probe settings for the devices
managed by the driver are consistent with their upstream device
settings. Additionally, the RTD3 driver device type is now set to
generic, ensuring that only one PCI device exists under the root port.
This prevents the binding of device operations (ops) for the RTD3 driver
from interfering with the WIFI generic driver during the scan process.

The commit also resolves warnings related to leftover static devices and
prompts to check the devicetree.cb. The fix ensures that the probe
settings for WIFI_PCIE_6 and WIFI_PCIE_7 are properly configured,
preventing device misidentification and ensuring correct functionality.

BUG=none
TEST=Boot to OS and verify the DSDT tables. Ensure the _DSM function of
the PEPD Device returns only one MCHE in a package, specifically
\_SB.PCI0.MCHC. Check kernel boot messages for absence of errors like
AE_NOT_FOUND related to named reference package elements such as
\_SB_.PCI0.RP04.MCHC.

Signed-off-by: Cliff Huang <cliff.huang@intel.com>
Change-Id: I40be48c056355d9e2a38b604849eb16565b8699d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89373
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 .../google/fatcat/variants/fatcat/overridetree.cb      | 10 ++++++++--
 .../google/fatcat/variants/felino/overridetree.cb      | 10 ++++++++--
 2 files changed, 16 insertions(+), 4 deletions(-)

diff --git a/src/mainboard/google/fatcat/variants/fatcat/overridetree.cb b/src/mainboard/google/fatcat/variants/fatcat/overridetree.cb
index 47da1d98ba..4c75c332ca 100644
--- a/src/mainboard/google/fatcat/variants/fatcat/overridetree.cb
+++ b/src/mainboard/google/fatcat/variants/fatcat/overridetree.cb
@@ -579,13 +579,19 @@ chip soc/intel/pantherlake
 			chip soc/intel/common/block/pcie/rtd3
 				register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A11)"
 				register "srcclk_pin" = "4"
-				device pci 00.0 on end
+				device generic 0 on
+					probe WIFI WIFI_PCIE_6
+					probe WIFI WIFI_PCIE_7
+				end
 			end
 			chip drivers/wifi/generic
 				register "add_acpi_dma_property" = "true"
 				register "wake" = "GPE0_DW0_12" # GPP_A12
 				use usb2_port7 as bluetooth_companion
-				device pci 00.0 on end
+				device pci 00.0 on
+					probe WIFI WIFI_PCIE_6
+					probe WIFI WIFI_PCIE_7
+				end
 			end
 		end # discrete WLAN
 		device ref pcie_rp5 on
diff --git a/src/mainboard/google/fatcat/variants/felino/overridetree.cb b/src/mainboard/google/fatcat/variants/felino/overridetree.cb
index 7e8c97268c..7d80164942 100644
--- a/src/mainboard/google/fatcat/variants/felino/overridetree.cb
+++ b/src/mainboard/google/fatcat/variants/felino/overridetree.cb
@@ -225,13 +225,19 @@ device ref tbt_pcie_rp0 on end
 			chip soc/intel/common/block/pcie/rtd3
 				register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A11)"
 				register "srcclk_pin" = "4"
-				device pci 00.0 on end
+				device generic 0 on
+					probe WIFI WIFI_PCIE_6
+					probe WIFI WIFI_PCIE_7
+				end
 			end
 			chip drivers/wifi/generic
 				register "add_acpi_dma_property" = "true"
 				register "wake" = "GPE0_DW0_12" # GPP_A12
 				use usb2_port7 as bluetooth_companion
-				device pci 00.0 on end
+				device pci 00.0 on
+					probe WIFI WIFI_PCIE_6
+					probe WIFI WIFI_PCIE_7
+				end
 			end
 		end #  WLAN
 

From ce1ced7f6a49f7f0d5402de57c5519edac801789 Mon Sep 17 00:00:00 2001
From: Cliff Huang <cliff.huang@intel.com>
Date: Mon, 29 Sep 2025 11:58:33 -0700
Subject: [PATCH 2148/3886] mb/intel/ptlrvp: Fix WIFI driver device settings
 under root port 4
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

The commit addresses an issue with discrete WIFI driver configuration
under root port 4 in the Intel PtlRvp mainboard. The problem involved
incorrect probe settings that allowed the WIFI driver device to remain
enabled even when its upstream device was disabled. This led to orphan
devices being misidentified as root devices within the Intel Power
Engine (PEP) structure, which in turn caused unnecessary MCHC devices
to be added under the root port.

The fix involves ensuring that the probe settings for the devices
managed by the driver are consistent with their upstream device
settings. Additionally, the RTD3 driver device type is now set to
generic, ensuring that only one PCI device exists under the root port.
This prevents the binding of device operations (ops) for the RTD3 driver
from interfering with the WIFI generic driver during the scan process.

The commit also resolves warnings related to leftover static devices and
prompts to check the devicetree.cb. The fix ensures that the probe
settings for WIFI_PCIE_6 and WIFI_PCIE_7 are properly configured,
preventing device misidentification and ensuring correct functionality.

BUG=none
TEST=Boot to OS and verify the DSDT tables. Ensure the _DSM function of
the PEPD Device returns only one MCHE in a package, specifically
\_SB.PCI0.MCHC. Check kernel boot messages for absence of errors like
AE_NOT_FOUND related to named reference package elements such as
\_SB_.PCI0.RP04.MCHC.

Signed-off-by: Cliff Huang <cliff.huang@intel.com>
Change-Id: I0a38cfc9bd38393cbf44f0e560c9525526d6bbf2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89374
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 .../intel/ptlrvp/variants/ptlrvp/overridetree.cb       | 10 ++++++++--
 .../ptlrvp/variants/ptlrvp_chromeec/overridetree.cb    | 10 ++++++++--
 2 files changed, 16 insertions(+), 4 deletions(-)

diff --git a/src/mainboard/intel/ptlrvp/variants/ptlrvp/overridetree.cb b/src/mainboard/intel/ptlrvp/variants/ptlrvp/overridetree.cb
index 62a7b59a81..f88f10f522 100644
--- a/src/mainboard/intel/ptlrvp/variants/ptlrvp/overridetree.cb
+++ b/src/mainboard/intel/ptlrvp/variants/ptlrvp/overridetree.cb
@@ -573,13 +573,19 @@ chip soc/intel/pantherlake
 			chip soc/intel/common/block/pcie/rtd3
 				register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A11)"
 				register "srcclk_pin" = "4"
-				device pci 00.0 on end
+				device generic 0 on
+					probe WIFI WIFI_PCIE_6
+					probe WIFI WIFI_PCIE_7
+				end
 			end
 			chip drivers/wifi/generic
 				register "add_acpi_dma_property" = "true"
 				register "wake" = "GPE0_DW0_12" # GPP_A12
 				use usb2_port7 as bluetooth_companion
-				device pci 00.0 on end
+				device pci 00.0 on
+					probe WIFI WIFI_PCIE_6
+					probe WIFI WIFI_PCIE_7
+				end
 			end
 		end # discrete WLAN
 		device ref pcie_rp5 on
diff --git a/src/mainboard/intel/ptlrvp/variants/ptlrvp_chromeec/overridetree.cb b/src/mainboard/intel/ptlrvp/variants/ptlrvp_chromeec/overridetree.cb
index de6cf416f8..a3f2eaf5eb 100644
--- a/src/mainboard/intel/ptlrvp/variants/ptlrvp_chromeec/overridetree.cb
+++ b/src/mainboard/intel/ptlrvp/variants/ptlrvp_chromeec/overridetree.cb
@@ -573,13 +573,19 @@ chip soc/intel/pantherlake
 			chip soc/intel/common/block/pcie/rtd3
 				register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A11)"
 				register "srcclk_pin" = "4"
-				device pci 00.0 on end
+				device generic 0 on
+					probe WIFI WIFI_PCIE_6
+					probe WIFI WIFI_PCIE_7
+				end
 			end
 			chip drivers/wifi/generic
 				register "add_acpi_dma_property" = "true"
 				register "wake" = "GPE0_DW0_12" # GPP_A12
 				use usb2_port7 as bluetooth_companion
-				device pci 00.0 on end
+				device pci 00.0 on
+					probe WIFI WIFI_PCIE_6
+					probe WIFI WIFI_PCIE_7
+				end
 			end
 		end # discrete WLAN
 		device ref pcie_rp5 on

From 4431848ee6fa4c1bc7c17a7341c833d8142b6c43 Mon Sep 17 00:00:00 2001
From: Maximilian Brune <maximilian.brune@9elements.com>
Date: Tue, 10 Jun 2025 17:43:33 +0200
Subject: [PATCH 2149/3886] acpi: Move most of HEST ACPI table to common code
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

This moves most of the vendor and architecture independent code into
common ACPI code.

Change-Id: I7dca939612a5f3d8d6a148fa67bf0ce891952584
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88034
Reviewed-by: Anand Vaikar <a.vaikar2021@gmail.com>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/acpi/Kconfig                              | 13 +++
 src/acpi/acpi.c                               | 27 +++++--
 src/include/acpi/acpi.h                       |  6 +-
 src/include/acpi/acpi_apei.h                  | 36 +++++++++
 src/northbridge/amd/pi/00730F01/Kconfig       |  1 +
 src/northbridge/amd/pi/00730F01/northbridge.c | 20 ++---
 src/soc/amd/stoneyridge/Kconfig               |  1 +
 src/soc/amd/stoneyridge/northbridge.c         | 22 ++---
 src/soc/intel/xeon_sp/Kconfig                 |  3 +-
 src/soc/intel/xeon_sp/include/soc/hest.h      | 40 ---------
 src/soc/intel/xeon_sp/ras/Kconfig             | 20 -----
 src/soc/intel/xeon_sp/ras/Makefile.mk         |  2 +-
 src/soc/intel/xeon_sp/ras/hest.c              | 81 ++++++-------------
 src/soc/intel/xeon_sp/spr/acpi/uncore.asl     |  2 +-
 src/soc/intel/xeon_sp/uncore_acpi.c           |  6 --
 15 files changed, 113 insertions(+), 167 deletions(-)
 create mode 100644 src/include/acpi/acpi_apei.h
 delete mode 100644 src/soc/intel/xeon_sp/include/soc/hest.h
 delete mode 100644 src/soc/intel/xeon_sp/ras/Kconfig

diff --git a/src/acpi/Kconfig b/src/acpi/Kconfig
index 2bb56ba91d..0d3730baa1 100644
--- a/src/acpi/Kconfig
+++ b/src/acpi/Kconfig
@@ -127,3 +127,16 @@ config ACPI_WDAT_WDT
 	help
 	  Selected by platforms that support and fill ACPI Watchdog Action Table
 	  (WDAT).
+
+config ACPI_HEST
+	bool
+	depends on HAVE_ACPI_TABLES
+	help
+	  Selected by platforms that support and fill ACPI Hardware Error Source Table (HEST)
+
+config ACPI_HEST_ERROR_LOG_BUFFER_SIZE
+	hex
+	default 0x4000
+	depends on ACPI_HEST
+	help
+	  Define the size of the HEST ACPI error log buffer
diff --git a/src/acpi/acpi.c b/src/acpi/acpi.c
index 07e84f6d39..7dad21f12d 100644
--- a/src/acpi/acpi.c
+++ b/src/acpi/acpi.c
@@ -14,6 +14,8 @@
  */
 
 #include <acpi/acpi.h>
+#include <acpi/acpi_apei.h>
+#include <acpi/acpi_gnvs.h>
 #include <acpi/acpi_iort.h>
 #include <acpi/acpi_ivrs.h>
 #include <acpi/acpigen.h>
@@ -1062,20 +1064,32 @@ unsigned long acpi_create_hest_error_source(acpi_hest_t *hest,
 }
 
 /* ACPI 4.0 */
-void acpi_write_hest(acpi_hest_t *hest,
-		     unsigned long (*acpi_fill_hest)(acpi_hest_t *hest))
+static void acpi_create_hest(acpi_header_t *header, void *unused)
 {
-	acpi_header_t *header = &(hest->header);
+	if (!CONFIG(ACPI_HEST))
+		return;
+
+	/* Reserve memory for Enhanced error logging */
+	void *log_mem = cbmem_add(CBMEM_ID_ACPI_HEST, CONFIG_ACPI_HEST_ERROR_LOG_BUFFER_SIZE);
+	if (!log_mem) {
+		printk(BIOS_ERR, "Unable to allocate HEST memory\n");
+		return;
+	}
+	printk(BIOS_DEBUG, "HEST elog_addr: %p, size:%d\n", log_mem,
+		CONFIG_ACPI_HEST_ERROR_LOG_BUFFER_SIZE);
+
+	acpi_hest_t *hest = (acpi_hest_t *)header;
+	uintptr_t current = (uintptr_t)(hest + 1);
 
 	memset(hest, 0, sizeof(acpi_hest_t));
 
 	if (acpi_fill_header(header, "HEST", HEST, sizeof(acpi_hest_t)) != CB_SUCCESS)
 		return;
 
-	acpi_fill_hest(hest);
+	current = acpi_soc_fill_hest(hest, current, log_mem);
 
-	/* Calculate checksums. */
-	header->checksum = acpi_checksum((void *)hest, header->length);
+	/* (Re)calculate length. */
+	header->length = current - (uintptr_t)hest;
 }
 
 /* ACPI 3.0b */
@@ -1456,6 +1470,7 @@ unsigned long write_acpi_tables(const unsigned long start)
 		{ acpi_create_tpm2, NULL, sizeof(acpi_tpm2_t) },
 		{ acpi_create_lpit, NULL, sizeof(acpi_lpit_t) },
 		{ acpi_create_madt, NULL, sizeof(acpi_header_t) },
+		{ acpi_create_hest, NULL, sizeof(acpi_hest_t) },
 		{ acpi_create_bert, NULL, sizeof(acpi_bert_t) },
 		{ acpi_create_spcr, NULL, sizeof(acpi_spcr_t) },
 		{ acpi_create_gtdt, NULL, sizeof(acpi_gtdt_t) },
diff --git a/src/include/acpi/acpi.h b/src/include/acpi/acpi.h
index 06dba65738..1acdd7f7e7 100644
--- a/src/include/acpi/acpi.h
+++ b/src/include/acpi/acpi.h
@@ -1879,11 +1879,9 @@ unsigned long acpi_create_dmar_ds_ioapic_from_hw(unsigned long current,
 unsigned long acpi_create_dmar_ds_msi_hpet(unsigned long current,
 						u8 enumeration_id,
 						u8 bus, u8 dev, u8 fn);
-void acpi_write_hest(acpi_hest_t *hest,
-		     unsigned long (*acpi_fill_hest)(acpi_hest_t *hest));
 
-unsigned long acpi_create_hest_error_source(acpi_hest_t *hest,
-	acpi_hest_esd_t *esd, u16 type, void *data, u16 len);
+unsigned long acpi_create_hest_error_source(acpi_hest_t *hest, acpi_hest_esd_t *esd, u16 type,
+					    void *data, u16 len);
 
 unsigned long acpi_create_lpi_desc_ncst(acpi_lpi_desc_ncst_t *lpi_desc, uint16_t uid);
 
diff --git a/src/include/acpi/acpi_apei.h b/src/include/acpi/acpi_apei.h
new file mode 100644
index 0000000000..b2edc2dea3
--- /dev/null
+++ b/src/include/acpi/acpi_apei.h
@@ -0,0 +1,36 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+/*
+ * Contains ACPI Platform Error Interfaces (APEI) definitions and declarations.
+ * These are mostly used by:
+ * - BERT (Boot Error Record Table) ACPI Table.
+ * - HEST (Hardware Error Source Table) ACPI Table.
+ */
+
+#ifndef _ACPI_APEI_H_
+#define _ACPI_APEI_H_
+
+#include <acpi/acpi.h>
+
+/* Generic Hardware Error Source Descriptor */
+typedef struct acpi_ghes_esd {
+	u16 type;
+	u16 source_id;
+	u16 related_src_id;
+	u8 flags;
+	u8 enabled;
+	u32 prealloc_erecords;
+	u32 max_section_per_record;
+} __packed acpi_ghes_esd_t;
+
+typedef struct ghes_record {
+	acpi_ghes_esd_t esd;
+	u32 max_raw_data_length;
+	acpi_addr64_t sts_addr;
+	acpi_hest_hen_t notify;
+	u32 err_sts_blk_len;
+} __packed ghes_record_t;
+
+uintptr_t acpi_soc_fill_hest(acpi_hest_t *hest, uintptr_t current, void *log_mem);
+
+#endif
diff --git a/src/northbridge/amd/pi/00730F01/Kconfig b/src/northbridge/amd/pi/00730F01/Kconfig
index 3c2829efe7..76a0aa3260 100644
--- a/src/northbridge/amd/pi/00730F01/Kconfig
+++ b/src/northbridge/amd/pi/00730F01/Kconfig
@@ -3,6 +3,7 @@
 config NORTHBRIDGE_AMD_PI_00730F01
 	bool
 	select DRAM_SUPPORT_DDR3
+	select ACPI_HEST
 
 if NORTHBRIDGE_AMD_PI_00730F01
 
diff --git a/src/northbridge/amd/pi/00730F01/northbridge.c b/src/northbridge/amd/pi/00730F01/northbridge.c
index 826c19e862..c3914516bb 100644
--- a/src/northbridge/amd/pi/00730F01/northbridge.c
+++ b/src/northbridge/amd/pi/00730F01/northbridge.c
@@ -1,5 +1,6 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
+#include <acpi/acpi_apei.h>
 #include <commonlib/helpers.h>
 #include <console/console.h>
 #include <device/pci_ops.h>
@@ -91,22 +92,19 @@ static void northbridge_init(struct device *dev)
 	register_new_ioapic(IO_APIC2_ADDR);
 }
 
-static unsigned long acpi_fill_hest(acpi_hest_t *hest)
+uintptr_t acpi_soc_fill_hest(acpi_hest_t *hest, uintptr_t current, void *log_mem)
 {
-	void *addr, *current;
-
-	/* Skip the HEST header. */
-	current = (void *)(hest + 1);
+	void *addr;
 
 	addr = agesawrapper_getlateinitptr(PICK_WHEA_MCE);
 	if (addr != NULL)
-		current += acpi_create_hest_error_source(hest, current, 0, (void *)((u32)addr + 2), *(UINT16 *)addr - 2);
+		current += acpi_create_hest_error_source(hest, (acpi_hest_esd_t *)current, 0, (void *)((u32)addr + 2), *(UINT16 *)addr - 2);
 
 	addr = agesawrapper_getlateinitptr(PICK_WHEA_CMC);
 	if (addr != NULL)
-		current += acpi_create_hest_error_source(hest, current, 1, (void *)((u32)addr + 2), *(UINT16 *)addr - 2);
+		current += acpi_create_hest_error_source(hest, (acpi_hest_esd_t *)current, 1, (void *)((u32)addr + 2), *(UINT16 *)addr - 2);
 
-	return (unsigned long)current;
+	return current;
 }
 
 static unsigned long acpi_fill_ivrs_ioapic(acpi_ivrs_t *ivrs, unsigned long current)
@@ -430,12 +428,6 @@ static unsigned long agesa_write_acpi_tables(const struct device *device,
 	acpi_header_t *alib;
 	acpi_ivrs_t *ivrs;
 
-	/* HEST */
-	current = ALIGN_UP(current, 8);
-	acpi_write_hest((void *)current, acpi_fill_hest);
-	acpi_add_table(rsdp, (void *)current);
-	current += ((acpi_header_t *)current)->length;
-
 	/* IVRS */
 	if (is_dev_enabled(DEV_PTR(iommu))) {
 		current = ALIGN_UP(current, 8);
diff --git a/src/soc/amd/stoneyridge/Kconfig b/src/soc/amd/stoneyridge/Kconfig
index 2abd9d7985..1d236363a6 100644
--- a/src/soc/amd/stoneyridge/Kconfig
+++ b/src/soc/amd/stoneyridge/Kconfig
@@ -3,6 +3,7 @@
 config SOC_AMD_STONEYRIDGE
 	bool
 	select ACPI_SOC_NVS
+	select ACPI_HEST
 	select ARCH_X86
 	select BOOT_DEVICE_SUPPORTS_WRITES if BOOT_DEVICE_SPI_FLASH
 	select COLLECT_TIMESTAMPS_NO_TSC
diff --git a/src/soc/amd/stoneyridge/northbridge.c b/src/soc/amd/stoneyridge/northbridge.c
index b6ebf4db4b..e8c3110c0e 100644
--- a/src/soc/amd/stoneyridge/northbridge.c
+++ b/src/soc/amd/stoneyridge/northbridge.c
@@ -1,5 +1,6 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
+#include <acpi/acpi_apei.h>
 #include <assert.h>
 #include <amdblocks/acpi.h>
 #include <amdblocks/biosram.h>
@@ -102,24 +103,21 @@ static void acpi_fill_root_complex_tom(const struct device *device)
 	acpigen_pop_len();
 }
 
-static unsigned long acpi_fill_hest(acpi_hest_t *hest)
+uintptr_t acpi_soc_fill_hest(acpi_hest_t *hest, uintptr_t current, void *log_mem)
 {
-	void *addr, *current;
-
-	/* Skip the HEST header. */
-	current = (void *)(hest + 1);
+	void *addr;
 
 	addr = agesawrapper_getlateinitptr(PICK_WHEA_MCE);
 	if (addr != NULL)
-		current += acpi_create_hest_error_source(hest, current, 0,
+		current += acpi_create_hest_error_source(hest, (acpi_hest_esd_t *)current, 0,
 				(void *)((u32)addr + 2), *(uint16_t *)addr - 2);
 
 	addr = agesawrapper_getlateinitptr(PICK_WHEA_CMC);
 	if (addr != NULL)
-		current += acpi_create_hest_error_source(hest, current, 1,
+		current += acpi_create_hest_error_source(hest, (acpi_hest_esd_t *)current, 1,
 				(void *)((u32)addr + 2), *(uint16_t *)addr - 2);
 
-	return (unsigned long)current;
+	return current;
 }
 
 unsigned long soc_acpi_write_tables(const struct device *device, unsigned long current,
@@ -129,14 +127,6 @@ unsigned long soc_acpi_write_tables(const struct device *device, unsigned long c
 	acpi_slit_t *slit;
 	acpi_header_t *alib;
 	acpi_header_t *ivrs;
-	acpi_hest_t *hest;
-
-	/* HEST */
-	current = acpi_align_current(current);
-	hest = (acpi_hest_t *)current;
-	acpi_write_hest(hest, acpi_fill_hest);
-	acpi_add_table(rsdp, (void *)current);
-	current += hest->header.length;
 
 	current = acpi_align_current(current);
 	printk(BIOS_DEBUG, "ACPI:    * IVRS at %lx\n", current);
diff --git a/src/soc/intel/xeon_sp/Kconfig b/src/soc/intel/xeon_sp/Kconfig
index 24923a5a29..eed04fbc62 100644
--- a/src/soc/intel/xeon_sp/Kconfig
+++ b/src/soc/intel/xeon_sp/Kconfig
@@ -108,8 +108,7 @@ config HPET_MIN_TICKS
 
 config SOC_INTEL_XEON_RAS
 	bool
-	select SOC_ACPI_HEST
-	select SOC_RAS_ELOG
+	select ACPI_HEST
 
 config HAVE_IOAT_DOMAINS
 	bool
diff --git a/src/soc/intel/xeon_sp/include/soc/hest.h b/src/soc/intel/xeon_sp/include/soc/hest.h
deleted file mode 100644
index ad79d45fdf..0000000000
--- a/src/soc/intel/xeon_sp/include/soc/hest.h
+++ /dev/null
@@ -1,40 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-or-later */
-
-#ifndef _HEST_H_
-#define _HEST_H_
-#include <acpi/acpi.h>
-
-#define MCE_ERR_POLL_MS_INTERVAL	1000
-#define HEST_PCIE_RP_AER_DESC_TYPE	6
-#define HEST_GHES_DESC_TYPE		9
-#define GHES_MAX_RAW_DATA_LENGTH	(((CONFIG_ERROR_LOG_BUFFER_SIZE) >> 1) - 8)
-#define GHEST_ERROR_STATUS_BLOCK_LENGTH	((CONFIG_ERROR_LOG_BUFFER_SIZE) >> 1)
-#define GHEST_ASSIST			(1 << 2)
-#define FIRMWARE_FIRST			(1 << 0)
-#define MEM_VALID_BITS			0x66ff
-#define PCIE_VALID_BITS			0xef
-#define QWORD_ACCESS			4
-#define NOTIFY_TYPE_SCI			3
-
-/* Generic Error Source Descriptor */
-typedef struct acpi_ghes_esd {
-	u16 type;
-	u16 source_id;
-	u16 related_src_id;
-	u8 flags;
-	u8 enabled;
-	u32 prealloc_erecords;
-	u32 max_section_per_record;
-} __packed acpi_ghes_esd_t;
-
-typedef struct ghes_record {
-	acpi_ghes_esd_t esd;
-	u32 max_raw_data_length;
-	acpi_addr64_t sts_addr;
-	acpi_hest_hen_t notify;
-	u32 err_sts_blk_len;
-} __packed ghes_record_t;
-
-unsigned long hest_create(unsigned long current, struct acpi_rsdp *rsdp);
-
-#endif
diff --git a/src/soc/intel/xeon_sp/ras/Kconfig b/src/soc/intel/xeon_sp/ras/Kconfig
deleted file mode 100644
index 79c599c2fb..0000000000
--- a/src/soc/intel/xeon_sp/ras/Kconfig
+++ /dev/null
@@ -1,20 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0-or-later
-
-config SOC_ACPI_HEST
-	def_bool n
-	depends on HAVE_ACPI_TABLES
-	help
-	  This variable provides control for ACPI hardware error source table (HEST)
-
-config SOC_RAS_ELOG
-	def_bool n
-	depends on SOC_ACPI_HEST
-	help
-	  This variable provides enhanced error logging support used with HEST
-
-config ERROR_LOG_BUFFER_SIZE
-	hex
-	default 0x4000
-	depends on SOC_RAS_ELOG
-	help
-	  This variable allows a configurable error log based on system requirements
diff --git a/src/soc/intel/xeon_sp/ras/Makefile.mk b/src/soc/intel/xeon_sp/ras/Makefile.mk
index 93c8705f94..a4c2923eb2 100644
--- a/src/soc/intel/xeon_sp/ras/Makefile.mk
+++ b/src/soc/intel/xeon_sp/ras/Makefile.mk
@@ -1,3 +1,3 @@
 ## SPDX-License-Identifier: GPL-2.0-or-later
 
-ramstage-$(CONFIG_SOC_ACPI_HEST) += hest.c
+ramstage-$(CONFIG_ACPI_HEST) += hest.c
diff --git a/src/soc/intel/xeon_sp/ras/hest.c b/src/soc/intel/xeon_sp/ras/hest.c
index 2da720a744..eb46b00dad 100644
--- a/src/soc/intel/xeon_sp/ras/hest.c
+++ b/src/soc/intel/xeon_sp/ras/hest.c
@@ -1,29 +1,25 @@
 /* SPDX-License-Identifier: GPL-2.0-or-later */
 
-#include <soc/acpi.h>
+#include <acpi/acpi_apei.h>
 #include <acpi/acpi_gnvs.h>
 #include <cbmem.h>
 #include <console/console.h>
-#include <soc/hest.h>
 #include <intelblocks/nvs.h>
+#include <soc/acpi.h>
 
-static u64 hest_get_elog_addr(void)
-{
-	/* The elog address comes from reserved memory */
-	struct global_nvs *gnvs;
-	gnvs = acpi_get_gnvs();
-	if (!gnvs) {
-		printk(BIOS_ERR, "Unable to get gnvs\n");
-		return 0;
-	}
+#define MCE_ERR_POLL_MS_INTERVAL	1000
+#define HEST_PCIE_RP_AER_DESC_TYPE	6
+#define HEST_GHES_DESC_TYPE		9
+#define GHES_MAX_RAW_DATA_LENGTH	(((CONFIG_ACPI_HEST_ERROR_LOG_BUFFER_SIZE) >> 1) - 8)
+#define GHEST_ERROR_STATUS_BLOCK_LENGTH	((CONFIG_ACPI_HEST_ERROR_LOG_BUFFER_SIZE) >> 1)
+#define GHEST_ASSIST			(1 << 2)
+#define FIRMWARE_FIRST			(1 << 0)
+#define MEM_VALID_BITS			0x66ff
+#define PCIE_VALID_BITS			0xef
+#define QWORD_ACCESS			4
+#define NOTIFY_TYPE_SCI			3
 
-	/* Runtime logging address */
-	printk(BIOS_DEBUG, "\t status blk start addr = %llx\n", gnvs->hest_log_addr);
-	printk(BIOS_DEBUG, "\t size = %x\n", CONFIG_ERROR_LOG_BUFFER_SIZE);
-	return gnvs->hest_log_addr;
-}
-
-static u32 acpi_hest_add_ghes(void *current)
+static u32 acpi_hest_add_ghes(uintptr_t current, uintptr_t log_mem)
 {
 	ghes_record_t *rec = (ghes_record_t *)current;
 	u32 size = sizeof(ghes_record_t);
@@ -50,51 +46,22 @@ static u32 acpi_hest_add_ghes(void *current)
 	rec->err_sts_blk_len = GHEST_ERROR_STATUS_BLOCK_LENGTH;
 
 	/* error status block entries start address */
-	if (CONFIG(SOC_ACPI_HEST))
-		rec->sts_addr.addr = hest_get_elog_addr();
+	rec->sts_addr.addr = log_mem;
 
 	return size;
 }
 
-static unsigned long acpi_fill_hest(acpi_hest_t *hest)
+uintptr_t acpi_soc_fill_hest(acpi_hest_t *hest, uintptr_t current, void *log_mem)
 {
-	acpi_header_t *header = &(hest->header);
-	void *current;
-	current = (void *)(hest);
-	void *next = current;
-	next = hest + 1;
-	next += acpi_hest_add_ghes(next);
+	// fill ACPI global non volatile storage with hest elog addr
+	struct global_nvs *gnvs = acpi_get_gnvs();
+	if (gnvs)
+		gnvs->hest_log_addr = (uintptr_t)log_mem;
+	else
+		printk(BIOS_ERR, "ACPI fill HEST: Unable to get gnvs\n");
+
+	current = acpi_hest_add_ghes(current, (uintptr_t)log_mem);  // add first entry
 	hest->error_source_count += 1;
-	header->length = next - current;
-	return header->length;
-}
 
-unsigned long hest_create(unsigned long current, struct acpi_rsdp *rsdp)
-{
-	struct global_nvs *gnvs;
-	acpi_hest_t *hest;
-
-	/* Reserve memory for Enhanced error logging */
-	void *mem = cbmem_add(CBMEM_ID_ACPI_HEST, CONFIG_ERROR_LOG_BUFFER_SIZE);
-	if (!mem) {
-		printk(BIOS_ERR, "Unable to allocate HEST memory\n");
-		return current;
-	}
-
-	printk(BIOS_DEBUG, "HEST memory created: %p\n", mem);
-	gnvs = acpi_get_gnvs();
-	if (!gnvs) {
-		printk(BIOS_ERR, "Unable to get gnvs\n");
-		return current;
-	}
-	gnvs->hest_log_addr = (uintptr_t)mem;
-	printk(BIOS_DEBUG, "elog_addr: %llx, size:%x\n", gnvs->hest_log_addr,
-		CONFIG_ERROR_LOG_BUFFER_SIZE);
-
-	current = ALIGN_UP(current, 8);
-	hest = (acpi_hest_t *)current;
-	acpi_write_hest(hest, acpi_fill_hest);
-	acpi_add_table(rsdp, (void *)current);
-	current += hest->header.length;
 	return current;
 }
diff --git a/src/soc/intel/xeon_sp/spr/acpi/uncore.asl b/src/soc/intel/xeon_sp/spr/acpi/uncore.asl
index ab2c3eb68c..76066242e9 100644
--- a/src/soc/intel/xeon_sp/spr/acpi/uncore.asl
+++ b/src/soc/intel/xeon_sp/spr/acpi/uncore.asl
@@ -18,7 +18,7 @@ Scope (\_SB)
 	#include "iiostack.asl"
 	#undef SOCKET
 
-	#if CONFIG(SOC_ACPI_HEST)
+	#if CONFIG(ACPI_HEST)
 		Method (_OSC, 4, NotSerialized)
 		{
 			CreateDWordField (Arg3, 0x00, CDW1)
diff --git a/src/soc/intel/xeon_sp/uncore_acpi.c b/src/soc/intel/xeon_sp/uncore_acpi.c
index 86519448bf..7acae310b8 100644
--- a/src/soc/intel/xeon_sp/uncore_acpi.c
+++ b/src/soc/intel/xeon_sp/uncore_acpi.c
@@ -13,7 +13,6 @@
 #include <device/pci_ops.h>
 #include <soc/acpi.h>
 #include <soc/chip_common.h>
-#include <soc/hest.h>
 #include <soc/iomap.h>
 #include <soc/numa.h>
 #include <soc/pci_devs.h>
@@ -633,10 +632,5 @@ unsigned long northbridge_write_acpi_tables(const struct device *device, unsigne
 		}
 	}
 
-	if (CONFIG(SOC_ACPI_HEST)) {
-		printk(BIOS_DEBUG, "ACPI:    * HEST at %lx\n", current);
-		current = hest_create(current, rsdp);
-	}
-
 	return current;
 }

From b8a880015291b1a1bd607f95b8f5162667949c91 Mon Sep 17 00:00:00 2001
From: Hualin Wei <weihualin@huaqin.corp-partner.google.com>
Date: Tue, 23 Sep 2025 13:49:12 +0800
Subject: [PATCH 2150/3886] mb/google/fatcat/var/lapis: Configure gpio of
 fingerprint sensor

Configure PWR_EN and RST GPIO of fingerprint sensor.

BUG=b:438785495
TEST='emerge-fatcat coreboot' and boot into os,
fingerprint function is ok.

Change-Id: If896fa5c0600c4bef9ea2c67a30205bcf2689bd1
Signed-off-by: Hualin Wei <weihualin@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89305
Reviewed-by: Pranava Y N <pranavayn@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
---
 src/mainboard/google/fatcat/variants/lapis/gpio.c | 10 ++++++++--
 1 file changed, 8 insertions(+), 2 deletions(-)

diff --git a/src/mainboard/google/fatcat/variants/lapis/gpio.c b/src/mainboard/google/fatcat/variants/lapis/gpio.c
index ea6c89f7dd..b288420cda 100644
--- a/src/mainboard/google/fatcat/variants/lapis/gpio.c
+++ b/src/mainboard/google/fatcat/variants/lapis/gpio.c
@@ -130,6 +130,8 @@ static const struct pad_config gpio_table[] = {
 	PAD_NC(GPP_C13, NONE),
 	/* GPP_C14:     Not used */
 	PAD_NC(GPP_C14, NONE),
+	/* GPP_C15:     FP_RST_N */
+	PAD_CFG_GPO(GPP_C15, 1, DEEP),
 	/* GPP_C16:     USB_C0_LSX_TX  ==> TBT_LSX0_TXD */
 	PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1),
 	/* GPP_C17:     USB_C0_LSX_RX  ==> TBT_LSX0_RXD */
@@ -232,8 +234,6 @@ static const struct pad_config gpio_table[] = {
 	PAD_CFG_GPI_APIC(GPP_E17, NONE, PLTRST, LEVEL, NONE),
 	/* GPP_E18:     TCHPAD_INT_ODL_LS ==> Not used */
 	PAD_NC(GPP_E18, NONE),
-	/* GPP_E19:     Not used ==> PANEL_ID0 */
-	PAD_NC(GPP_E19, NONE),
 	/* GPP_E20:     Not used ==> PANEL_ID1 */
 	PAD_NC(GPP_E20, NONE),
 	/* GPP_E21:     PMC_I2C_PD_INT_ODL ==> PD_SMB1_INT# */
@@ -392,6 +392,12 @@ static const struct pad_config gpio_table[] = {
 
 /* Early pad configuration in bootblock */
 static const struct pad_config early_gpio_table[] = {
+	/* GPP_C15:     FP_RST_N */
+	PAD_CFG_GPO(GPP_C15, 0, DEEP),
+
+	/* GPP_E19:     FP_PWR_EN */
+	PAD_CFG_GPO(GPP_E19, 1, PLTRST),
+
 	/* GPP_H08:     UART0_BUF_RXD */
 	PAD_CFG_NF(GPP_H08, NONE, DEEP, NF1),
 	/* GPP_H09:     UART0_BUF_TXD */

From 88ad238eca3fb38bead19c02e10bd32c2bb35446 Mon Sep 17 00:00:00 2001
From: Yu-Ping Wu <yupingso@google.com>
Date: Wed, 1 Oct 2025 02:33:19 +0000
Subject: [PATCH 2151/3886] mb/google/skywalker: Fix incorrect
 GPIO_USB3_HUB_RST_L pull-down

commit 1e7908fa9fc0 ("mb/google/skywalker: Set up all output GPIOs") set
up all output GPIOs to the desired initial value. However, as the
GPIO_USB3_HUB_RST_L pin is already pulled high in usb3_hub_reset() right
before the setup_chromeos_gpios() call, we should not pull it low again.
Otherwise all the USB3 hubs would stop working.

Fix the issue by moving the configuration from usb3_hub_reset() to
setup_chromeos_gpios(), where GPIO_USB3_HUB_RST_L is pull high to reset
USB3 hub.

BUG=none
TEST=emerge-skywalker coreboot
TEST=USB3 hub working properly during bootup
BRANCH=skywalker

Change-Id: Id53ddb033166f7fdcf6b5fc50b538ee29d5d85bb
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89388
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/google/skywalker/bootblock.c | 6 ------
 src/mainboard/google/skywalker/chromeos.c  | 3 ++-
 2 files changed, 2 insertions(+), 7 deletions(-)

diff --git a/src/mainboard/google/skywalker/bootblock.c b/src/mainboard/google/skywalker/bootblock.c
index 330bd6a541..16926851ff 100644
--- a/src/mainboard/google/skywalker/bootblock.c
+++ b/src/mainboard/google/skywalker/bootblock.c
@@ -8,17 +8,11 @@
 
 #include "gpio.h"
 
-static void usb3_hub_reset(void)
-{
-	gpio_output(GPIO_USB3_HUB_RST_L, 1);
-}
-
 void bootblock_mainboard_init(void)
 {
 	mtk_i2c_bus_init(CONFIG_DRIVER_TPM_I2C_BUS, I2C_SPEED_FAST_PLUS);
 	mtk_spi_init(CONFIG_EC_GOOGLE_CHROMEEC_SPI_BUS, SPI_PAD0_MASK, 3 * MHz, 0);
 	mtk_snfc_init();
-	usb3_hub_reset();
 	setup_chromeos_gpios();
 	gpio_eint_configure(GPIO_GSC_AP_INT_ODL, IRQ_TYPE_EDGE_RISING);
 }
diff --git a/src/mainboard/google/skywalker/chromeos.c b/src/mainboard/google/skywalker/chromeos.c
index 3a7510c5d0..b364282dcb 100644
--- a/src/mainboard/google/skywalker/chromeos.c
+++ b/src/mainboard/google/skywalker/chromeos.c
@@ -27,7 +27,8 @@ void setup_chromeos_gpios(void)
 
 	gpio_output(GPIO_EN_SPKR, 0);
 	gpio_output(GPIO_RST_SPKR_L, 0);
-	gpio_output(GPIO_USB3_HUB_RST_L, 0);
+	/* Reset USB3 hub. */
+	gpio_output(GPIO_USB3_HUB_RST_L, 1);
 	gpio_output(GPIO_WWAN_RESET_L, 0);
 	gpio_output(GPIO_EN_PWR_FP, 0);
 	gpio_output(GPIO_EDP_BL_EN_1V8, 0);

From 58459b82108ecc3f72eb8968abca75a8e60fb2a4 Mon Sep 17 00:00:00 2001
From: Derek Huang <derekhuang@google.com>
Date: Wed, 1 Oct 2025 02:59:32 +0000
Subject: [PATCH 2152/3886] mb/var/uldrenite,orisa: Include the variant GPIO
 header

In 76e0f640353a63b859770aebfdc7b2cbf3870662, it overrides
GPIO_PCH_WP in variant/gpio.h, however gpio.c includes
baseboard/gpio.h instead of variant/gpio.h. The wrong GPIO header
causes the test firmware.WriteProtectCrossystem to fail with the
wrong GPIO_PCH_WP pin number. Corrects the header file included in
gpio.c to fix the issue.

BUG=b:448313028
TEST=Pass firmware.WriteProtectCrossystem

Change-Id: I94b2384d03f8ce83f662a2b9dba4039f3d551b07
Signed-off-by: Derek Huang <derekhuang@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89389
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/google/brya/variants/orisa/gpio.c     | 2 +-
 src/mainboard/google/brya/variants/uldrenite/gpio.c | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/mainboard/google/brya/variants/orisa/gpio.c b/src/mainboard/google/brya/variants/orisa/gpio.c
index 6f45dcc589..1801e82fdb 100644
--- a/src/mainboard/google/brya/variants/orisa/gpio.c
+++ b/src/mainboard/google/brya/variants/orisa/gpio.c
@@ -1,10 +1,10 @@
 /* SPDX-License-Identifier: GPL-2.0-or-later */
 
-#include <baseboard/gpio.h>
 #include <baseboard/variants.h>
 #include <soc/gpio.h>
 #include <types.h>
 #include <vendorcode/google/chromeos/chromeos.h>
+#include <variant/gpio.h>
 
 /* Pad configuration in ramstage */
 static const struct pad_config gpio_table[] = {
diff --git a/src/mainboard/google/brya/variants/uldrenite/gpio.c b/src/mainboard/google/brya/variants/uldrenite/gpio.c
index d21b0ebde3..57f9e94cf5 100644
--- a/src/mainboard/google/brya/variants/uldrenite/gpio.c
+++ b/src/mainboard/google/brya/variants/uldrenite/gpio.c
@@ -1,10 +1,10 @@
 /* SPDX-License-Identifier: GPL-2.0-or-later */
 
-#include <baseboard/gpio.h>
 #include <baseboard/variants.h>
 #include <soc/gpio.h>
 #include <types.h>
 #include <vendorcode/google/chromeos/chromeos.h>
+#include <variant/gpio.h>
 
 /* Pad configuration in ramstage */
 static const struct pad_config gpio_table[] = {

From 02059c2250a658ee04c19b22b7fe856140f7a048 Mon Sep 17 00:00:00 2001
From: Luca Lai <luca.lai@lcfc.corp-partner.google.com>
Date: Tue, 30 Sep 2025 13:51:59 +0800
Subject: [PATCH 2153/3886] mb/google/trulo/var/pujjoquince: Disable ISH gpio
 setting by fw_config

Because we use dummy ish in pujjoquince, so disable ish related gpio
when fw_config TABLET_MODE=TABLET_MODE_DISABLE

BUG=b:432649211
TEST=Build and boot to OS, check pujjoquince ish related gpio are closed.

Change-Id: Iab43f6d4ce3a6d31358ac0b902535ee3f5dad1e3
Signed-off-by: Luca Lai <luca.lai@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89378
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Derek Huang <derekhuang@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
---
 .../google/brya/variants/pujjolo/Makefile.mk  |  1 +
 .../google/brya/variants/pujjolo/fw_config.c  | 26 +++++++++++++++++++
 2 files changed, 27 insertions(+)
 create mode 100644 src/mainboard/google/brya/variants/pujjolo/fw_config.c

diff --git a/src/mainboard/google/brya/variants/pujjolo/Makefile.mk b/src/mainboard/google/brya/variants/pujjolo/Makefile.mk
index 4a6700c6ec..d57029b334 100644
--- a/src/mainboard/google/brya/variants/pujjolo/Makefile.mk
+++ b/src/mainboard/google/brya/variants/pujjolo/Makefile.mk
@@ -8,3 +8,4 @@ ramstage-y += gpio.c
 ramstage-y += variant.c
 ramstage-y += ramstage.c
 ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_HDA_VERB) += hda_verb.c
+ramstage-$(CONFIG_FW_CONFIG) += fw_config.c
diff --git a/src/mainboard/google/brya/variants/pujjolo/fw_config.c b/src/mainboard/google/brya/variants/pujjolo/fw_config.c
new file mode 100644
index 0000000000..02e159d14d
--- /dev/null
+++ b/src/mainboard/google/brya/variants/pujjolo/fw_config.c
@@ -0,0 +1,26 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <baseboard/gpio.h>
+#include <baseboard/variants.h>
+#include <console/console.h>
+#include <fw_config.h>
+
+static const struct pad_config ish_disable_pads[] = {
+	/* B3  : ISH_IMU_INT_L */
+	PAD_NC_LOCK(GPP_B3, NONE, LOCK_CONFIG),
+	/* B4  : ISH_ACC_INT_L */
+	PAD_NC_LOCK(GPP_B4, NONE, LOCK_CONFIG),
+	/* B5  : EC_I2C_SENSOR_SDA_SOC */
+	PAD_NC_LOCK(GPP_B5, NONE, LOCK_CONFIG),
+	/* B6  : EC_I2C_SENSOR_SCL_SOC */
+	PAD_NC_LOCK(GPP_B6, NONE, LOCK_CONFIG),
+};
+
+void fw_config_gpio_padbased_override(struct pad_config *padbased_table)
+{
+	if (fw_config_probe(FW_CONFIG(TABLET_MODE, TABLET_MODE_DISABLE))) {
+		printk(BIOS_INFO, "Disable ISH-related GPIO pins.\n");
+		gpio_padbased_override(padbased_table, ish_disable_pads,
+						ARRAY_SIZE(ish_disable_pads));
+	}
+}

From d5f1ecedf762a3eca59716cba29533cd500989f7 Mon Sep 17 00:00:00 2001
From: Maxim Polyakov <max.senia.poliak@gmail.com>
Date: Thu, 25 Sep 2025 15:08:28 +0300
Subject: [PATCH 2154/3886] {device/azalia_codec,mainboard}: Use node ID enums
 for Realtek ALC887

Add enums for the output pin widget node IDs for Realtek ALC887 [1] and
use these enums in the motherboard configuration.

[1] Figure 1, Block Diagram, ALC887-GR Datasheet, Rev. 1.0, 24 July 2008

Change-Id: Iaa2ebd7447a19dfc98b006c851f1605851c1ea5d
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89364
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
---
 src/include/device/azalia_codec/realtek.h     | 17 ++++++++++
 src/mainboard/asrock/b85m_pro4/hda_verb.c     | 29 ++++++++---------
 src/mainboard/asrock/h110m/hda_verb.c         | 29 ++++++++---------
 src/mainboard/asrock/imb-1222/hda_verb.c      | 29 ++++++++---------
 .../variants/h61m-a_usb3/hda_verb.c           | 29 ++++++++---------
 .../h61-series/variants/h61m-cs/hda_verb.c    | 29 ++++++++---------
 .../h61-series/variants/p8h61-m_lx/hda_verb.c | 29 ++++++++---------
 .../variants/p8h61-m_pro/hda_verb.c           | 29 ++++++++---------
 .../variants/p8h61-m_pro_cm6630/hda_verb.c    | 29 ++++++++---------
 src/mainboard/asus/p5qpl-am/hda_verb.c        | 29 ++++++++---------
 .../p8x7x-series/variants/p8z77-m/hda_verb.c  | 29 ++++++++---------
 .../variants/p8z77-v_lx2/hda_verb.c           | 29 ++++++++---------
 .../ga-b75-d3v/include/variant/hda_verb.h     | 31 ++++++++++---------
 .../ga-b75m-d3v/include/variant/hda_verb.h    | 31 ++++++++++---------
 src/mainboard/gigabyte/ga-d510ud/hda_verb.c   | 29 ++++++++---------
 .../gigabyte/ga-g41m-es2l/hda_verb.c          | 29 ++++++++---------
 .../variants/ga-h61m-ds2/hda_verb.c           | 29 ++++++++---------
 .../variants/ga-h61m-ds2v/hda_verb.c          | 29 ++++++++---------
 .../variants/ga-h61m-s2p-r3/hda_verb.c        | 29 ++++++++---------
 .../variants/ga-h61m-s2pv/hda_verb.c          | 29 ++++++++---------
 .../variants/ga-h61ma-d3v/hda_verb.c          | 29 ++++++++---------
 src/mainboard/gigabyte/ga-h81m-d2w/hda_verb.c | 29 ++++++++---------
 src/mainboard/msi/h81m-p33/hda_verb.c         | 29 ++++++++---------
 src/mainboard/msi/ms7707/hda_verb.c           | 29 ++++++++---------
 24 files changed, 366 insertions(+), 322 deletions(-)

diff --git a/src/include/device/azalia_codec/realtek.h b/src/include/device/azalia_codec/realtek.h
index 12c9ed2d0a..c7b622a332 100644
--- a/src/include/device/azalia_codec/realtek.h
+++ b/src/include/device/azalia_codec/realtek.h
@@ -29,4 +29,21 @@ enum alc269_pin_widget {
 	ALC269_VB_HP_OUT	= 0x21,	// Port-I, ALC269-VBx only
 };
 
+enum alc887_pin_widget {
+	ALC887_SPDIF_OUT2	= 0x11,
+	ALC887_DMIC_LR		= 0x12,
+	ALC887_FRONT		= 0x14, // Port-D
+	ALC887_SURROUND		= 0x15, // Port-A
+	ALC887_CENTER_LFE	= 0x16, // Port-G
+	ALC887_SIDE_SURROUND	= 0x17, // Port-H
+	ALC887_MIC1		= 0x18, // Port-B
+	ALC887_MIC2		= 0x19, // Port-F
+	ALC887_LINE1		= 0x1a, // Port-C
+	ALC887_LINE2		= 0x1b, // Port-E
+	ALC887_CD		= 0x1c,
+	ALC887_PC_BEEP		= 0x1d,
+	ALC887_SPDIF_OUT1	= 0x1e,
+	ALC887_SPDIF_IN		= 0x1f,
+};
+
 #endif /* DEVICE_AZALIA_CODEC_REALTEK_H */
diff --git a/src/mainboard/asrock/b85m_pro4/hda_verb.c b/src/mainboard/asrock/b85m_pro4/hda_verb.c
index 39425d2e41..76169be95b 100644
--- a/src/mainboard/asrock/b85m_pro4/hda_verb.c
+++ b/src/mainboard/asrock/b85m_pro4/hda_verb.c
@@ -1,6 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
 #include <device/azalia_device.h>
+#include <device/azalia_codec/realtek.h>
 
 static const u32 realtek_alc892_verbs[] = {
 	AZALIA_SUBVENDOR(0, 0x1849c892),
@@ -18,20 +19,20 @@ static const u32 realtek_alc892_verbs[] = {
 
 static const u32 realtek_alc887_verbs[] = {
 	AZALIA_SUBVENDOR(2, 0x1458a002),
-	AZALIA_PIN_CFG(2, 0x11, 0x411110f0),
-	AZALIA_PIN_CFG(2, 0x12, AZALIA_PIN_CFG_NC(0)),
-	AZALIA_PIN_CFG(2, 0x14, 0x01014410),
-	AZALIA_PIN_CFG(2, 0x15, AZALIA_PIN_CFG_NC(0)),
-	AZALIA_PIN_CFG(2, 0x16, AZALIA_PIN_CFG_NC(0)),
-	AZALIA_PIN_CFG(2, 0x17, AZALIA_PIN_CFG_NC(0)),
-	AZALIA_PIN_CFG(2, 0x18, 0x01a19c50),
-	AZALIA_PIN_CFG(2, 0x19, 0x02a19c60),
-	AZALIA_PIN_CFG(2, 0x1a, 0x0181345f),
-	AZALIA_PIN_CFG(2, 0x1b, 0x02214c20),
-	AZALIA_PIN_CFG(2, 0x1c, AZALIA_PIN_CFG_NC(0)),
-	AZALIA_PIN_CFG(2, 0x1d, 0x4004c601),
-	AZALIA_PIN_CFG(2, 0x1e, AZALIA_PIN_CFG_NC(0)),
-	AZALIA_PIN_CFG(2, 0x1f, 0x41c46060),
+	AZALIA_PIN_CFG(2, ALC887_SPDIF_OUT2, 0x411110f0),
+	AZALIA_PIN_CFG(2, ALC887_DMIC_LR, AZALIA_PIN_CFG_NC(0)),
+	AZALIA_PIN_CFG(2, ALC887_FRONT, 0x01014410),
+	AZALIA_PIN_CFG(2, ALC887_SURROUND, AZALIA_PIN_CFG_NC(0)),
+	AZALIA_PIN_CFG(2, ALC887_CENTER_LFE, AZALIA_PIN_CFG_NC(0)),
+	AZALIA_PIN_CFG(2, ALC887_SIDE_SURROUND, AZALIA_PIN_CFG_NC(0)),
+	AZALIA_PIN_CFG(2, ALC887_MIC1, 0x01a19c50),
+	AZALIA_PIN_CFG(2, ALC887_MIC2, 0x02a19c60),
+	AZALIA_PIN_CFG(2, ALC887_LINE1, 0x0181345f),
+	AZALIA_PIN_CFG(2, ALC887_LINE2, 0x02214c20),
+	AZALIA_PIN_CFG(2, ALC887_CD, AZALIA_PIN_CFG_NC(0)),
+	AZALIA_PIN_CFG(2, ALC887_PC_BEEP, 0x4004c601),
+	AZALIA_PIN_CFG(2, ALC887_SPDIF_OUT1, AZALIA_PIN_CFG_NC(0)),
+	AZALIA_PIN_CFG(2, ALC887_SPDIF_IN, 0x41c46060),
 };
 
 static const u32 intel_display_audio_verbs[] = {
diff --git a/src/mainboard/asrock/h110m/hda_verb.c b/src/mainboard/asrock/h110m/hda_verb.c
index cf346a82d2..95f432659e 100644
--- a/src/mainboard/asrock/h110m/hda_verb.c
+++ b/src/mainboard/asrock/h110m/hda_verb.c
@@ -1,23 +1,24 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
 #include <device/azalia_device.h>
+#include <device/azalia_codec/realtek.h>
 
 static const u32 realtek_alc887_verbs[] = {
 	AZALIA_SUBVENDOR(0, 0x10438445),
-	AZALIA_PIN_CFG(0, 0x11, 0x40000000),
-	AZALIA_PIN_CFG(0, 0x12, AZALIA_PIN_CFG_NC(0)),
-	AZALIA_PIN_CFG(0, 0x14, 0x01014020),
-	AZALIA_PIN_CFG(0, 0x15, 0x90170110),
-	AZALIA_PIN_CFG(0, 0x16, AZALIA_PIN_CFG_NC(0)),
-	AZALIA_PIN_CFG(0, 0x17, AZALIA_PIN_CFG_NC(0)),
-	AZALIA_PIN_CFG(0, 0x18, 0x01a19040),
-	AZALIA_PIN_CFG(0, 0x19, 0x02a19050),
-	AZALIA_PIN_CFG(0, 0x1a, 0x0181304f),
-	AZALIA_PIN_CFG(0, 0x1b, 0x02214030),
-	AZALIA_PIN_CFG(0, 0x1c, AZALIA_PIN_CFG_NC(0)),
-	AZALIA_PIN_CFG(0, 0x1d, 0x4026c629),
-	AZALIA_PIN_CFG(0, 0x1e, AZALIA_PIN_CFG_NC(0)),
-	AZALIA_PIN_CFG(0, 0x1f, AZALIA_PIN_CFG_NC(0)),
+	AZALIA_PIN_CFG(0, ALC887_SPDIF_OUT2, 0x40000000),
+	AZALIA_PIN_CFG(0, ALC887_DMIC_LR, AZALIA_PIN_CFG_NC(0)),
+	AZALIA_PIN_CFG(0, ALC887_FRONT, 0x01014020),
+	AZALIA_PIN_CFG(0, ALC887_SURROUND, 0x90170110),
+	AZALIA_PIN_CFG(0, ALC887_CENTER_LFE, AZALIA_PIN_CFG_NC(0)),
+	AZALIA_PIN_CFG(0, ALC887_SIDE_SURROUND, AZALIA_PIN_CFG_NC(0)),
+	AZALIA_PIN_CFG(0, ALC887_MIC1, 0x01a19040),
+	AZALIA_PIN_CFG(0, ALC887_MIC2, 0x02a19050),
+	AZALIA_PIN_CFG(0, ALC887_LINE1, 0x0181304f),
+	AZALIA_PIN_CFG(0, ALC887_LINE2, 0x02214030),
+	AZALIA_PIN_CFG(0, ALC887_CD, AZALIA_PIN_CFG_NC(0)),
+	AZALIA_PIN_CFG(0, ALC887_PC_BEEP, 0x4026c629),
+	AZALIA_PIN_CFG(0, ALC887_SPDIF_OUT1, AZALIA_PIN_CFG_NC(0)),
+	AZALIA_PIN_CFG(0, ALC887_SPDIF_IN, AZALIA_PIN_CFG_NC(0)),
 };
 
 static const u32 intel_display_audio_verbs[] = {
diff --git a/src/mainboard/asrock/imb-1222/hda_verb.c b/src/mainboard/asrock/imb-1222/hda_verb.c
index 9997db894c..1397b87a5a 100644
--- a/src/mainboard/asrock/imb-1222/hda_verb.c
+++ b/src/mainboard/asrock/imb-1222/hda_verb.c
@@ -1,23 +1,24 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
 #include <device/azalia_device.h>
+#include <device/azalia_codec/realtek.h>
 
 static const u32 realtek_alc887_vd_verbs[] = {
 	AZALIA_SUBVENDOR(0, 0x1849588a),
-	AZALIA_PIN_CFG(0, 0x11, 0x40000000),
-	AZALIA_PIN_CFG(0, 0x12, AZALIA_PIN_CFG_NC(0)),
-	AZALIA_PIN_CFG(0, 0x14, 0x01014020),
-	AZALIA_PIN_CFG(0, 0x15, 0x90170110),
-	AZALIA_PIN_CFG(0, 0x16, AZALIA_PIN_CFG_NC(0)),
-	AZALIA_PIN_CFG(0, 0x17, AZALIA_PIN_CFG_NC(0)),
-	AZALIA_PIN_CFG(0, 0x18, 0x01a19050),
-	AZALIA_PIN_CFG(0, 0x19, 0x02a19060),
-	AZALIA_PIN_CFG(0, 0x1a, AZALIA_PIN_CFG_NC(0)),
-	AZALIA_PIN_CFG(0, 0x1b, 0x02214030),
-	AZALIA_PIN_CFG(0, 0x1c, AZALIA_PIN_CFG_NC(0)),
-	AZALIA_PIN_CFG(0, 0x1d, 0x4024c601),
-	AZALIA_PIN_CFG(0, 0x1e, 0x01451140),
-	AZALIA_PIN_CFG(0, 0x1f, AZALIA_PIN_CFG_NC(0)),
+	AZALIA_PIN_CFG(0, ALC887_SPDIF_OUT2, 0x40000000),
+	AZALIA_PIN_CFG(0, ALC887_DMIC_LR, AZALIA_PIN_CFG_NC(0)),
+	AZALIA_PIN_CFG(0, ALC887_FRONT, 0x01014020),
+	AZALIA_PIN_CFG(0, ALC887_SURROUND, 0x90170110),
+	AZALIA_PIN_CFG(0, ALC887_CENTER_LFE, AZALIA_PIN_CFG_NC(0)),
+	AZALIA_PIN_CFG(0, ALC887_SIDE_SURROUND, AZALIA_PIN_CFG_NC(0)),
+	AZALIA_PIN_CFG(0, ALC887_MIC1, 0x01a19050),
+	AZALIA_PIN_CFG(0, ALC887_MIC2, 0x02a19060),
+	AZALIA_PIN_CFG(0, ALC887_LINE1, AZALIA_PIN_CFG_NC(0)),
+	AZALIA_PIN_CFG(0, ALC887_LINE2, 0x02214030),
+	AZALIA_PIN_CFG(0, ALC887_CD, AZALIA_PIN_CFG_NC(0)),
+	AZALIA_PIN_CFG(0, ALC887_PC_BEEP, 0x4024c601),
+	AZALIA_PIN_CFG(0, ALC887_SPDIF_OUT1, 0x01451140),
+	AZALIA_PIN_CFG(0, ALC887_SPDIF_IN, AZALIA_PIN_CFG_NC(0)),
 };
 
 static const u32 intel_display_audio_verbs[] = {
diff --git a/src/mainboard/asus/h61-series/variants/h61m-a_usb3/hda_verb.c b/src/mainboard/asus/h61-series/variants/h61m-a_usb3/hda_verb.c
index 1af52eb94e..b9177d0f5a 100644
--- a/src/mainboard/asus/h61-series/variants/h61m-a_usb3/hda_verb.c
+++ b/src/mainboard/asus/h61-series/variants/h61m-a_usb3/hda_verb.c
@@ -1,26 +1,27 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
 #include <device/azalia_device.h>
+#include <device/azalia_codec/realtek.h>
 
 const u32 cim_verb_data[] = {
 	0x10ec0887,	/* Codec Vendor / Device ID: Realtek */
 	0x10438445,	/* Subsystem ID */
 	15,		/* Number of 4 dword sets */
 	AZALIA_SUBVENDOR(0, 0x10438445),
-	AZALIA_PIN_CFG(0, 0x11, 0x40330000),
-	AZALIA_PIN_CFG(0, 0x12, AZALIA_PIN_CFG_NC(0)),
-	AZALIA_PIN_CFG(0, 0x14, 0x01014010),
-	AZALIA_PIN_CFG(0, 0x15, AZALIA_PIN_CFG_NC(0)),
-	AZALIA_PIN_CFG(0, 0x16, AZALIA_PIN_CFG_NC(0)),
-	AZALIA_PIN_CFG(0, 0x17, AZALIA_PIN_CFG_NC(0)),
-	AZALIA_PIN_CFG(0, 0x18, 0x01a19030),
-	AZALIA_PIN_CFG(0, 0x19, 0x02a19040),
-	AZALIA_PIN_CFG(0, 0x1a, 0x0181303f),
-	AZALIA_PIN_CFG(0, 0x1b, 0x02214020),
-	AZALIA_PIN_CFG(0, 0x1c, AZALIA_PIN_CFG_NC(0)),
-	AZALIA_PIN_CFG(0, 0x1d, 0x4024c601),
-	AZALIA_PIN_CFG(0, 0x1e, AZALIA_PIN_CFG_NC(0)),
-	AZALIA_PIN_CFG(0, 0x1f, AZALIA_PIN_CFG_NC(0)),
+	AZALIA_PIN_CFG(0, ALC887_SPDIF_OUT2, 0x40330000),
+	AZALIA_PIN_CFG(0, ALC887_DMIC_LR, AZALIA_PIN_CFG_NC(0)),
+	AZALIA_PIN_CFG(0, ALC887_FRONT, 0x01014010),
+	AZALIA_PIN_CFG(0, ALC887_SURROUND, AZALIA_PIN_CFG_NC(0)),
+	AZALIA_PIN_CFG(0, ALC887_CENTER_LFE, AZALIA_PIN_CFG_NC(0)),
+	AZALIA_PIN_CFG(0, ALC887_SIDE_SURROUND, AZALIA_PIN_CFG_NC(0)),
+	AZALIA_PIN_CFG(0, ALC887_MIC1, 0x01a19030),
+	AZALIA_PIN_CFG(0, ALC887_MIC2, 0x02a19040),
+	AZALIA_PIN_CFG(0, ALC887_LINE1, 0x0181303f),
+	AZALIA_PIN_CFG(0, ALC887_LINE2, 0x02214020),
+	AZALIA_PIN_CFG(0, ALC887_CD, AZALIA_PIN_CFG_NC(0)),
+	AZALIA_PIN_CFG(0, ALC887_PC_BEEP, 0x4024c601),
+	AZALIA_PIN_CFG(0, ALC887_SPDIF_OUT1, AZALIA_PIN_CFG_NC(0)),
+	AZALIA_PIN_CFG(0, ALC887_SPDIF_IN, AZALIA_PIN_CFG_NC(0)),
 
 	0x8086281c,	/* Codec Vendor / Device ID: Intel */
 	0x80860101,	/* Subsystem ID */
diff --git a/src/mainboard/asus/h61-series/variants/h61m-cs/hda_verb.c b/src/mainboard/asus/h61-series/variants/h61m-cs/hda_verb.c
index 05c9b296d4..956a716c76 100644
--- a/src/mainboard/asus/h61-series/variants/h61m-cs/hda_verb.c
+++ b/src/mainboard/asus/h61-series/variants/h61m-cs/hda_verb.c
@@ -2,26 +2,27 @@
 
 #include <stdint.h>
 #include <device/azalia_device.h>
+#include <device/azalia_codec/realtek.h>
 
 const u32 cim_verb_data[] = {
 	0x10ec0887,	/* Codec Vendor / Device ID: Realtek */
 	0x10438445,	/* Subsystem ID */
 	15,		/* Number of 4 dword sets */
 	AZALIA_SUBVENDOR(0, 0x10438445),
-	AZALIA_PIN_CFG(0, 0x11, 0x40330000),
-	AZALIA_PIN_CFG(0, 0x12, AZALIA_PIN_CFG_NC(0)),
-	AZALIA_PIN_CFG(0, 0x14, 0x01014010),
-	AZALIA_PIN_CFG(0, 0x15, AZALIA_PIN_CFG_NC(0)),
-	AZALIA_PIN_CFG(0, 0x16, AZALIA_PIN_CFG_NC(0)),
-	AZALIA_PIN_CFG(0, 0x17, AZALIA_PIN_CFG_NC(0)),
-	AZALIA_PIN_CFG(0, 0x18, 0x01a19030),
-	AZALIA_PIN_CFG(0, 0x19, 0x02a19040),
-	AZALIA_PIN_CFG(0, 0x1a, 0x0181303f),
-	AZALIA_PIN_CFG(0, 0x1b, 0x02214020),
-	AZALIA_PIN_CFG(0, 0x1c, AZALIA_PIN_CFG_NC(0)),
-	AZALIA_PIN_CFG(0, 0x1d, 0x4024c601),
-	AZALIA_PIN_CFG(0, 0x1e, AZALIA_PIN_CFG_NC(0)),
-	AZALIA_PIN_CFG(0, 0x1f, AZALIA_PIN_CFG_NC(0)),
+	AZALIA_PIN_CFG(0, ALC887_SPDIF_OUT2, 0x40330000),
+	AZALIA_PIN_CFG(0, ALC887_DMIC_LR, AZALIA_PIN_CFG_NC(0)),
+	AZALIA_PIN_CFG(0, ALC887_FRONT, 0x01014010),
+	AZALIA_PIN_CFG(0, ALC887_SURROUND, AZALIA_PIN_CFG_NC(0)),
+	AZALIA_PIN_CFG(0, ALC887_CENTER_LFE, AZALIA_PIN_CFG_NC(0)),
+	AZALIA_PIN_CFG(0, ALC887_SIDE_SURROUND, AZALIA_PIN_CFG_NC(0)),
+	AZALIA_PIN_CFG(0, ALC887_MIC1, 0x01a19030),
+	AZALIA_PIN_CFG(0, ALC887_MIC2, 0x02a19040),
+	AZALIA_PIN_CFG(0, ALC887_LINE1, 0x0181303f),
+	AZALIA_PIN_CFG(0, ALC887_LINE2, 0x02214020),
+	AZALIA_PIN_CFG(0, ALC887_CD, AZALIA_PIN_CFG_NC(0)),
+	AZALIA_PIN_CFG(0, ALC887_PC_BEEP, 0x4024c601),
+	AZALIA_PIN_CFG(0, ALC887_SPDIF_OUT1, AZALIA_PIN_CFG_NC(0)),
+	AZALIA_PIN_CFG(0, ALC887_SPDIF_IN, AZALIA_PIN_CFG_NC(0)),
 };
 
 const u32 pc_beep_verbs[0] = {};
diff --git a/src/mainboard/asus/h61-series/variants/p8h61-m_lx/hda_verb.c b/src/mainboard/asus/h61-series/variants/p8h61-m_lx/hda_verb.c
index dbd4a5af09..5647a31c96 100644
--- a/src/mainboard/asus/h61-series/variants/p8h61-m_lx/hda_verb.c
+++ b/src/mainboard/asus/h61-series/variants/p8h61-m_lx/hda_verb.c
@@ -2,26 +2,27 @@
 
 #include <stdint.h>
 #include <device/azalia_device.h>
+#include <device/azalia_codec/realtek.h>
 
 const u32 cim_verb_data[] = {
 	0x10ec0887,	/* Realtek ALC887-VD */
 	0x10438445,	/* Subsystem ID */
 	15,		/* Number of entries */
 	AZALIA_SUBVENDOR(0, 0x10438445),
-	AZALIA_PIN_CFG(0, 0x11, 0x99430130),
-	AZALIA_PIN_CFG(0, 0x12, AZALIA_PIN_CFG_NC(0)),
-	AZALIA_PIN_CFG(0, 0x14, 0x01014010),
-	AZALIA_PIN_CFG(0, 0x15, AZALIA_PIN_CFG_NC(0)),
-	AZALIA_PIN_CFG(0, 0x16, AZALIA_PIN_CFG_NC(0)),
-	AZALIA_PIN_CFG(0, 0x17, AZALIA_PIN_CFG_NC(0)),
-	AZALIA_PIN_CFG(0, 0x18, 0x01a19840),
-	AZALIA_PIN_CFG(0, 0x19, 0x02a19c50),
-	AZALIA_PIN_CFG(0, 0x1a, 0x0181304f),
-	AZALIA_PIN_CFG(0, 0x1b, 0x02214c20),
-	AZALIA_PIN_CFG(0, 0x1c, AZALIA_PIN_CFG_NC(0)),
-	AZALIA_PIN_CFG(0, 0x1d, 0x4004c601),
-	AZALIA_PIN_CFG(0, 0x1e, AZALIA_PIN_CFG_NC(0)),
-	AZALIA_PIN_CFG(0, 0x1f, AZALIA_PIN_CFG_NC(0)),
+	AZALIA_PIN_CFG(0, ALC887_SPDIF_OUT2, 0x99430130),
+	AZALIA_PIN_CFG(0, ALC887_DMIC_LR, AZALIA_PIN_CFG_NC(0)),
+	AZALIA_PIN_CFG(0, ALC887_FRONT, 0x01014010),
+	AZALIA_PIN_CFG(0, ALC887_SURROUND, AZALIA_PIN_CFG_NC(0)),
+	AZALIA_PIN_CFG(0, ALC887_CENTER_LFE, AZALIA_PIN_CFG_NC(0)),
+	AZALIA_PIN_CFG(0, ALC887_SIDE_SURROUND, AZALIA_PIN_CFG_NC(0)),
+	AZALIA_PIN_CFG(0, ALC887_MIC1, 0x01a19840),
+	AZALIA_PIN_CFG(0, ALC887_MIC2, 0x02a19c50),
+	AZALIA_PIN_CFG(0, ALC887_LINE1, 0x0181304f),
+	AZALIA_PIN_CFG(0, ALC887_LINE2, 0x02214c20),
+	AZALIA_PIN_CFG(0, ALC887_CD, AZALIA_PIN_CFG_NC(0)),
+	AZALIA_PIN_CFG(0, ALC887_PC_BEEP, 0x4004c601),
+	AZALIA_PIN_CFG(0, ALC887_SPDIF_OUT1, AZALIA_PIN_CFG_NC(0)),
+	AZALIA_PIN_CFG(0, ALC887_SPDIF_IN, AZALIA_PIN_CFG_NC(0)),
 };
 
 const u32 pc_beep_verbs[] = {};
diff --git a/src/mainboard/asus/h61-series/variants/p8h61-m_pro/hda_verb.c b/src/mainboard/asus/h61-series/variants/p8h61-m_pro/hda_verb.c
index 7b6e068992..e29bdcae14 100644
--- a/src/mainboard/asus/h61-series/variants/p8h61-m_pro/hda_verb.c
+++ b/src/mainboard/asus/h61-series/variants/p8h61-m_pro/hda_verb.c
@@ -1,26 +1,27 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
 #include <device/azalia_device.h>
+#include <device/azalia_codec/realtek.h>
 
 const u32 cim_verb_data[] = {
 	0x10ec0887,	/* Codec Vendor / Device ID: Realtek */
 	0x10438444,	/* Subsystem ID */
 	15,		/* Number of 4 dword sets */
 	AZALIA_SUBVENDOR(0, 0x10438444),
-	AZALIA_PIN_CFG(0, 0x11, 0x99430140),
-	AZALIA_PIN_CFG(0, 0x12, AZALIA_PIN_CFG_NC(0)),
-	AZALIA_PIN_CFG(0, 0x14, 0x01014010),
-	AZALIA_PIN_CFG(0, 0x15, 0x01011012),
-	AZALIA_PIN_CFG(0, 0x16, 0x01016011),
-	AZALIA_PIN_CFG(0, 0x17, 0x01012014),
-	AZALIA_PIN_CFG(0, 0x18, 0x01a19850),
-	AZALIA_PIN_CFG(0, 0x19, 0x02a19c60),
-	AZALIA_PIN_CFG(0, 0x1a, 0x0181305f),
-	AZALIA_PIN_CFG(0, 0x1b, 0x02214c20),
-	AZALIA_PIN_CFG(0, 0x1c, AZALIA_PIN_CFG_NC(0)),
-	AZALIA_PIN_CFG(0, 0x1d, 0x4005e601),
-	AZALIA_PIN_CFG(0, 0x1e, 0x01456130),
-	AZALIA_PIN_CFG(0, 0x1f, AZALIA_PIN_CFG_NC(0)),
+	AZALIA_PIN_CFG(0, ALC887_SPDIF_OUT2, 0x99430140),
+	AZALIA_PIN_CFG(0, ALC887_DMIC_LR, AZALIA_PIN_CFG_NC(0)),
+	AZALIA_PIN_CFG(0, ALC887_FRONT, 0x01014010),
+	AZALIA_PIN_CFG(0, ALC887_SURROUND, 0x01011012),
+	AZALIA_PIN_CFG(0, ALC887_CENTER_LFE, 0x01016011),
+	AZALIA_PIN_CFG(0, ALC887_SIDE_SURROUND, 0x01012014),
+	AZALIA_PIN_CFG(0, ALC887_MIC1, 0x01a19850),
+	AZALIA_PIN_CFG(0, ALC887_MIC2, 0x02a19c60),
+	AZALIA_PIN_CFG(0, ALC887_LINE1, 0x0181305f),
+	AZALIA_PIN_CFG(0, ALC887_LINE2, 0x02214c20),
+	AZALIA_PIN_CFG(0, ALC887_CD, AZALIA_PIN_CFG_NC(0)),
+	AZALIA_PIN_CFG(0, ALC887_PC_BEEP, 0x4005e601),
+	AZALIA_PIN_CFG(0, ALC887_SPDIF_OUT1, 0x01456130),
+	AZALIA_PIN_CFG(0, ALC887_SPDIF_IN, AZALIA_PIN_CFG_NC(0)),
 
 	0x80862805,	/* Codec Vendor / Device ID: Intel */
 	0x80860101,	/* Subsystem ID */
diff --git a/src/mainboard/asus/h61-series/variants/p8h61-m_pro_cm6630/hda_verb.c b/src/mainboard/asus/h61-series/variants/p8h61-m_pro_cm6630/hda_verb.c
index 87a6cd6e5c..0aa95d00a3 100644
--- a/src/mainboard/asus/h61-series/variants/p8h61-m_pro_cm6630/hda_verb.c
+++ b/src/mainboard/asus/h61-series/variants/p8h61-m_pro_cm6630/hda_verb.c
@@ -1,26 +1,27 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
 #include <device/azalia_device.h>
+#include <device/azalia_codec/realtek.h>
 
 const u32 cim_verb_data[] = {
 	0x10ec0887,	/* Codec Vendor / Device ID: Realtek ALC887 */
 	0x10438444,	/* Subsystem ID */
 	15,		/* Number of 4 dword sets */
 	AZALIA_SUBVENDOR(0, 0x10438444),
-	AZALIA_PIN_CFG(0, 0x11, 0x99430140),
-	AZALIA_PIN_CFG(0, 0x12, AZALIA_PIN_CFG_NC(0)),
-	AZALIA_PIN_CFG(0, 0x14, 0x01014010),
-	AZALIA_PIN_CFG(0, 0x15, 0x01011012),
-	AZALIA_PIN_CFG(0, 0x16, 0x01016011),
-	AZALIA_PIN_CFG(0, 0x17, 0x01012014),
-	AZALIA_PIN_CFG(0, 0x18, 0x01a19850),
-	AZALIA_PIN_CFG(0, 0x19, 0x02a19c60),
-	AZALIA_PIN_CFG(0, 0x1a, 0x0181305f),
-	AZALIA_PIN_CFG(0, 0x1b, 0x02214c20),
-	AZALIA_PIN_CFG(0, 0x1c, AZALIA_PIN_CFG_NC(0)),
-	AZALIA_PIN_CFG(0, 0x1d, 0x4005e601),
-	AZALIA_PIN_CFG(0, 0x1e, 0x01456130),
-	AZALIA_PIN_CFG(0, 0x1f, AZALIA_PIN_CFG_NC(0)),
+	AZALIA_PIN_CFG(0, ALC887_SPDIF_OUT2, 0x99430140),
+	AZALIA_PIN_CFG(0, ALC887_DMIC_LR, AZALIA_PIN_CFG_NC(0)),
+	AZALIA_PIN_CFG(0, ALC887_FRONT, 0x01014010),
+	AZALIA_PIN_CFG(0, ALC887_SURROUND, 0x01011012),
+	AZALIA_PIN_CFG(0, ALC887_CENTER_LFE, 0x01016011),
+	AZALIA_PIN_CFG(0, ALC887_SIDE_SURROUND, 0x01012014),
+	AZALIA_PIN_CFG(0, ALC887_MIC1, 0x01a19850),
+	AZALIA_PIN_CFG(0, ALC887_MIC2, 0x02a19c60),
+	AZALIA_PIN_CFG(0, ALC887_LINE1, 0x0181305f),
+	AZALIA_PIN_CFG(0, ALC887_LINE2, 0x02214c20),
+	AZALIA_PIN_CFG(0, ALC887_CD, AZALIA_PIN_CFG_NC(0)),
+	AZALIA_PIN_CFG(0, ALC887_PC_BEEP, 0x4005e601),
+	AZALIA_PIN_CFG(0, ALC887_SPDIF_OUT1, 0x01456130),
+	AZALIA_PIN_CFG(0, ALC887_SPDIF_IN, AZALIA_PIN_CFG_NC(0)),
 
 	0x80862805,	/* Codec Vendor / Device ID: Intel HDMI */
 	0x80860101,	/* Subsystem ID */
diff --git a/src/mainboard/asus/p5qpl-am/hda_verb.c b/src/mainboard/asus/p5qpl-am/hda_verb.c
index 525aab2c53..b49878a9a8 100644
--- a/src/mainboard/asus/p5qpl-am/hda_verb.c
+++ b/src/mainboard/asus/p5qpl-am/hda_verb.c
@@ -1,6 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0-or-later */
 
 #include <device/azalia_device.h>
+#include <device/azalia_codec/realtek.h>
 
 const u32 cim_verb_data[] = {
 	/* coreboot specific header */
@@ -11,20 +12,20 @@ const u32 cim_verb_data[] = {
 
 	/* Pin Widget Verb Table */
 
-	AZALIA_PIN_CFG(0, 0x11, AZALIA_PIN_CFG_NC(0)),
-	AZALIA_PIN_CFG(0, 0x12, AZALIA_PIN_CFG_NC(0)),
-	AZALIA_PIN_CFG(0, 0x14, 0x01014010),
-	AZALIA_PIN_CFG(0, 0x15, AZALIA_PIN_CFG_NC(0)),
-	AZALIA_PIN_CFG(0, 0x16, AZALIA_PIN_CFG_NC(0)),
-	AZALIA_PIN_CFG(0, 0x17, AZALIA_PIN_CFG_NC(0)),
-	AZALIA_PIN_CFG(0, 0x18, 0x01a19840),
-	AZALIA_PIN_CFG(0, 0x19, 0x02a19850),
-	AZALIA_PIN_CFG(0, 0x1a, 0x0181304f),
-	AZALIA_PIN_CFG(0, 0x1b, 0x02214020),
-	AZALIA_PIN_CFG(0, 0x1c, 0x593301f0),
-	AZALIA_PIN_CFG(0, 0x1d, 0x4004c601),
-	AZALIA_PIN_CFG(0, 0x1e, 0x99430130),
-	AZALIA_PIN_CFG(0, 0x1f, AZALIA_PIN_CFG_NC(0)),
+	AZALIA_PIN_CFG(0, ALC887_SPDIF_OUT2, AZALIA_PIN_CFG_NC(0)),
+	AZALIA_PIN_CFG(0, ALC887_DMIC_LR, AZALIA_PIN_CFG_NC(0)),
+	AZALIA_PIN_CFG(0, ALC887_FRONT, 0x01014010),
+	AZALIA_PIN_CFG(0, ALC887_SURROUND, AZALIA_PIN_CFG_NC(0)),
+	AZALIA_PIN_CFG(0, ALC887_CENTER_LFE, AZALIA_PIN_CFG_NC(0)),
+	AZALIA_PIN_CFG(0, ALC887_SIDE_SURROUND, AZALIA_PIN_CFG_NC(0)),
+	AZALIA_PIN_CFG(0, ALC887_MIC1, 0x01a19840),
+	AZALIA_PIN_CFG(0, ALC887_MIC2, 0x02a19850),
+	AZALIA_PIN_CFG(0, ALC887_LINE1, 0x0181304f),
+	AZALIA_PIN_CFG(0, ALC887_LINE2, 0x02214020),
+	AZALIA_PIN_CFG(0, ALC887_CD, 0x593301f0),
+	AZALIA_PIN_CFG(0, ALC887_PC_BEEP, 0x4004c601),
+	AZALIA_PIN_CFG(0, ALC887_SPDIF_OUT1, 0x99430130),
+	AZALIA_PIN_CFG(0, ALC887_SPDIF_IN, AZALIA_PIN_CFG_NC(0)),
 };
 
 const u32 pc_beep_verbs[0] = {};
diff --git a/src/mainboard/asus/p8x7x-series/variants/p8z77-m/hda_verb.c b/src/mainboard/asus/p8x7x-series/variants/p8z77-m/hda_verb.c
index b553b17a84..05efa2d5af 100644
--- a/src/mainboard/asus/p8x7x-series/variants/p8z77-m/hda_verb.c
+++ b/src/mainboard/asus/p8x7x-series/variants/p8z77-m/hda_verb.c
@@ -1,6 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0-or-later */
 
 #include <device/azalia_device.h>
+#include <device/azalia_codec/realtek.h>
 #include <stdint.h>
 
 #include <option.h>
@@ -10,20 +11,20 @@ const u32 cim_verb_data[] = {
 	0x104384a8, /* Subsystem ID */
 	15,         /* Number of 4 dword sets */
 	AZALIA_SUBVENDOR(0, 0x104384a8),
-	AZALIA_PIN_CFG(0, 0x11, 0x90430130),
-	AZALIA_PIN_CFG(0, 0x12, AZALIA_PIN_CFG_NC(0)),
-	AZALIA_PIN_CFG(0, 0x14, 0x01014410),
-	AZALIA_PIN_CFG(0, 0x15, AZALIA_PIN_CFG_NC(0)),
-	AZALIA_PIN_CFG(0, 0x16, AZALIA_PIN_CFG_NC(0)),
-	AZALIA_PIN_CFG(0, 0x17, AZALIA_PIN_CFG_NC(0)),
-	AZALIA_PIN_CFG(0, 0x18, 0x01a19c50),
-	AZALIA_PIN_CFG(0, 0x19, 0x02a19c60),
-	AZALIA_PIN_CFG(0, 0x1a, 0x0181345f),
-	AZALIA_PIN_CFG(0, 0x1b, 0x02214c20),
-	AZALIA_PIN_CFG(0, 0x1c, AZALIA_PIN_CFG_NC(0)),
-	AZALIA_PIN_CFG(0, 0x1d, 0x4016c629),
-	AZALIA_PIN_CFG(0, 0x1e, 0x01446140),
-	AZALIA_PIN_CFG(0, 0x1f, AZALIA_PIN_CFG_NC(0)),
+	AZALIA_PIN_CFG(0, ALC887_SPDIF_OUT2, 0x90430130),
+	AZALIA_PIN_CFG(0, ALC887_DMIC_LR, AZALIA_PIN_CFG_NC(0)),
+	AZALIA_PIN_CFG(0, ALC887_FRONT, 0x01014410),
+	AZALIA_PIN_CFG(0, ALC887_SURROUND, AZALIA_PIN_CFG_NC(0)),
+	AZALIA_PIN_CFG(0, ALC887_CENTER_LFE, AZALIA_PIN_CFG_NC(0)),
+	AZALIA_PIN_CFG(0, ALC887_SIDE_SURROUND, AZALIA_PIN_CFG_NC(0)),
+	AZALIA_PIN_CFG(0, ALC887_MIC1, 0x01a19c50),
+	AZALIA_PIN_CFG(0, ALC887_MIC2, 0x02a19c60),
+	AZALIA_PIN_CFG(0, ALC887_LINE1, 0x0181345f),
+	AZALIA_PIN_CFG(0, ALC887_LINE2, 0x02214c20),
+	AZALIA_PIN_CFG(0, ALC887_CD, AZALIA_PIN_CFG_NC(0)),
+	AZALIA_PIN_CFG(0, ALC887_PC_BEEP, 0x4016c629),
+	AZALIA_PIN_CFG(0, ALC887_SPDIF_OUT1, 0x01446140),
+	AZALIA_PIN_CFG(0, ALC887_SPDIF_IN, AZALIA_PIN_CFG_NC(0)),
 
 	0x80862806, /* Codec Vendor / Device ID: Intel */
 	0x80860101, /* Subsystem ID */
diff --git a/src/mainboard/asus/p8x7x-series/variants/p8z77-v_lx2/hda_verb.c b/src/mainboard/asus/p8x7x-series/variants/p8z77-v_lx2/hda_verb.c
index a474a7562c..c6f3b6b4c0 100644
--- a/src/mainboard/asus/p8x7x-series/variants/p8z77-v_lx2/hda_verb.c
+++ b/src/mainboard/asus/p8x7x-series/variants/p8z77-v_lx2/hda_verb.c
@@ -1,26 +1,27 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
 #include <device/azalia_device.h>
+#include <device/azalia_codec/realtek.h>
 
 const u32 cim_verb_data[] = {
 	0x10ec0887,	/* Codec Vendor / Device ID: Realtek ALC887 */
 	0x10438445,	/* Subsystem ID */
 	15,		/* Number of 4 dword sets */
 	AZALIA_SUBVENDOR(0, 0x10438445),
-	AZALIA_PIN_CFG(0, 0x11, 0x99430130),
-	AZALIA_PIN_CFG(0, 0x12, AZALIA_PIN_CFG_NC(0)),
-	AZALIA_PIN_CFG(0, 0x14, 0x01014010),
-	AZALIA_PIN_CFG(0, 0x15, AZALIA_PIN_CFG_NC(0)),
-	AZALIA_PIN_CFG(0, 0x16, AZALIA_PIN_CFG_NC(0)),
-	AZALIA_PIN_CFG(0, 0x17, AZALIA_PIN_CFG_NC(0)),
-	AZALIA_PIN_CFG(0, 0x18, 0x01a19840),
-	AZALIA_PIN_CFG(0, 0x19, 0x02a19c50),
-	AZALIA_PIN_CFG(0, 0x1a, 0x0181304f),
-	AZALIA_PIN_CFG(0, 0x1b, 0x02214c20),
-	AZALIA_PIN_CFG(0, 0x1c, AZALIA_PIN_CFG_NC(0)),
-	AZALIA_PIN_CFG(0, 0x1d, 0x4004c601),
-	AZALIA_PIN_CFG(0, 0x1e, AZALIA_PIN_CFG_NC(0)),
-	AZALIA_PIN_CFG(0, 0x1f, AZALIA_PIN_CFG_NC(0)),
+	AZALIA_PIN_CFG(0, ALC887_SPDIF_OUT2, 0x99430130),
+	AZALIA_PIN_CFG(0, ALC887_DMIC_LR, AZALIA_PIN_CFG_NC(0)),
+	AZALIA_PIN_CFG(0, ALC887_FRONT, 0x01014010),
+	AZALIA_PIN_CFG(0, ALC887_SURROUND, AZALIA_PIN_CFG_NC(0)),
+	AZALIA_PIN_CFG(0, ALC887_CENTER_LFE, AZALIA_PIN_CFG_NC(0)),
+	AZALIA_PIN_CFG(0, ALC887_SIDE_SURROUND, AZALIA_PIN_CFG_NC(0)),
+	AZALIA_PIN_CFG(0, ALC887_MIC1, 0x01a19840),
+	AZALIA_PIN_CFG(0, ALC887_MIC2, 0x02a19c50),
+	AZALIA_PIN_CFG(0, ALC887_LINE1, 0x0181304f),
+	AZALIA_PIN_CFG(0, ALC887_LINE2, 0x02214c20),
+	AZALIA_PIN_CFG(0, ALC887_CD, AZALIA_PIN_CFG_NC(0)),
+	AZALIA_PIN_CFG(0, ALC887_PC_BEEP, 0x4004c601),
+	AZALIA_PIN_CFG(0, ALC887_SPDIF_OUT1, AZALIA_PIN_CFG_NC(0)),
+	AZALIA_PIN_CFG(0, ALC887_SPDIF_IN, AZALIA_PIN_CFG_NC(0)),
 
 	0x80862806,	/* Codec Vendor / Device ID: Intel HDMI */
 	0x80860101,	/* Subsystem ID */
diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/variants/ga-b75-d3v/include/variant/hda_verb.h b/src/mainboard/gigabyte/ga-b75m-d3h/variants/ga-b75-d3v/include/variant/hda_verb.h
index cb807c2f33..aa227d307f 100644
--- a/src/mainboard/gigabyte/ga-b75m-d3h/variants/ga-b75-d3v/include/variant/hda_verb.h
+++ b/src/mainboard/gigabyte/ga-b75m-d3h/variants/ga-b75-d3v/include/variant/hda_verb.h
@@ -3,6 +3,9 @@
 #ifndef GA_B75_D3V_HDA_VERB_H
 #define GA_B75_D3V_HDA_VERB_H
 
+#include <device/azalia_device.h>
+#include <device/azalia_codec/realtek.h>
+
 const u32 cim_verb_data[] = {
 	/* coreboot specific header */
 	0x10ec0887,	// Realtek 887
@@ -13,20 +16,20 @@ const u32 cim_verb_data[] = {
 	AZALIA_SUBVENDOR(2, 0x1458a002),
 
 	/* Pin Widget Verb Table */
-	AZALIA_PIN_CFG(2, 0x11, 0x99430130),
-	AZALIA_PIN_CFG(2, 0x12, AZALIA_PIN_CFG_NC(0)),
-	AZALIA_PIN_CFG(2, 0x14, 0x01014410),
-	AZALIA_PIN_CFG(2, 0x15, AZALIA_PIN_CFG_NC(0)),
-	AZALIA_PIN_CFG(2, 0x16, AZALIA_PIN_CFG_NC(0)),
-	AZALIA_PIN_CFG(2, 0x17, AZALIA_PIN_CFG_NC(0)),
-	AZALIA_PIN_CFG(2, 0x18, 0x01a19c50),
-	AZALIA_PIN_CFG(2, 0x19, 0x02a19c60),
-	AZALIA_PIN_CFG(2, 0x1a, 0x0181345f),
-	AZALIA_PIN_CFG(2, 0x1b, 0x02214c20),
-	AZALIA_PIN_CFG(2, 0x1c, AZALIA_PIN_CFG_NC(0)),
-	AZALIA_PIN_CFG(2, 0x1d, 0x4004c601),
-	AZALIA_PIN_CFG(2, 0x1e, AZALIA_PIN_CFG_NC(0)),
-	AZALIA_PIN_CFG(2, 0x1f, AZALIA_PIN_CFG_NC(0)),
+	AZALIA_PIN_CFG(2, ALC887_SPDIF_OUT2, 0x99430130),
+	AZALIA_PIN_CFG(2, ALC887_DMIC_LR, AZALIA_PIN_CFG_NC(0)),
+	AZALIA_PIN_CFG(2, ALC887_FRONT, 0x01014410),
+	AZALIA_PIN_CFG(2, ALC887_SURROUND, AZALIA_PIN_CFG_NC(0)),
+	AZALIA_PIN_CFG(2, ALC887_CENTER_LFE, AZALIA_PIN_CFG_NC(0)),
+	AZALIA_PIN_CFG(2, ALC887_SIDE_SURROUND, AZALIA_PIN_CFG_NC(0)),
+	AZALIA_PIN_CFG(2, ALC887_MIC1, 0x01a19c50),
+	AZALIA_PIN_CFG(2, ALC887_MIC2, 0x02a19c60),
+	AZALIA_PIN_CFG(2, ALC887_LINE1, 0x0181345f),
+	AZALIA_PIN_CFG(2, ALC887_LINE2, 0x02214c20),
+	AZALIA_PIN_CFG(2, ALC887_CD, AZALIA_PIN_CFG_NC(0)),
+	AZALIA_PIN_CFG(2, ALC887_PC_BEEP, 0x4004c601),
+	AZALIA_PIN_CFG(2, ALC887_SPDIF_OUT1, AZALIA_PIN_CFG_NC(0)),
+	AZALIA_PIN_CFG(2, ALC887_SPDIF_IN, AZALIA_PIN_CFG_NC(0)),
 };
 
 #endif
diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/variants/ga-b75m-d3v/include/variant/hda_verb.h b/src/mainboard/gigabyte/ga-b75m-d3h/variants/ga-b75m-d3v/include/variant/hda_verb.h
index 8824a7e071..78e3effbd3 100644
--- a/src/mainboard/gigabyte/ga-b75m-d3h/variants/ga-b75m-d3v/include/variant/hda_verb.h
+++ b/src/mainboard/gigabyte/ga-b75m-d3h/variants/ga-b75m-d3v/include/variant/hda_verb.h
@@ -3,6 +3,9 @@
 #ifndef GA_B75M_D3V_HDA_VERB_H
 #define GA_B75M_D3V_HDA_VERB_H
 
+#include <device/azalia_device.h>
+#include <device/azalia_codec/realtek.h>
+
 const u32 cim_verb_data[] = {
 	/* coreboot specific header */
 	0x10ec0887,	// Realtek 887
@@ -10,20 +13,20 @@ const u32 cim_verb_data[] = {
 	0x0000000e,	// Number of entries
 
 	/* Pin Widget Verb Table */
-	AZALIA_PIN_CFG(0, 0x11, AZALIA_PIN_CFG_NC(0)),
-	AZALIA_PIN_CFG(0, 0x12, AZALIA_PIN_CFG_NC(0)),
-	AZALIA_PIN_CFG(0, 0x14, 0x01014410),
-	AZALIA_PIN_CFG(0, 0x15, AZALIA_PIN_CFG_NC(0)),
-	AZALIA_PIN_CFG(0, 0x16, AZALIA_PIN_CFG_NC(0)),
-	AZALIA_PIN_CFG(0, 0x17, AZALIA_PIN_CFG_NC(0)),
-	AZALIA_PIN_CFG(0, 0x18, 0x01a19c50),
-	AZALIA_PIN_CFG(0, 0x19, 0x02a19c60),
-	AZALIA_PIN_CFG(0, 0x1a, 0x0181345f),
-	AZALIA_PIN_CFG(0, 0x1b, 0x02214c20),
-	AZALIA_PIN_CFG(0, 0x1c, AZALIA_PIN_CFG_NC(0)),
-	AZALIA_PIN_CFG(0, 0x1d, 0x4004c601),
-	AZALIA_PIN_CFG(0, 0x1e, AZALIA_PIN_CFG_NC(0)),
-	AZALIA_PIN_CFG(0, 0x1f, AZALIA_PIN_CFG_NC(0))
+	AZALIA_PIN_CFG(0, ALC887_SPDIF_OUT2, AZALIA_PIN_CFG_NC(0)),
+	AZALIA_PIN_CFG(0, ALC887_DMIC_LR, AZALIA_PIN_CFG_NC(0)),
+	AZALIA_PIN_CFG(0, ALC887_FRONT, 0x01014410),
+	AZALIA_PIN_CFG(0, ALC887_SURROUND, AZALIA_PIN_CFG_NC(0)),
+	AZALIA_PIN_CFG(0, ALC887_CENTER_LFE, AZALIA_PIN_CFG_NC(0)),
+	AZALIA_PIN_CFG(0, ALC887_SIDE_SURROUND, AZALIA_PIN_CFG_NC(0)),
+	AZALIA_PIN_CFG(0, ALC887_MIC1, 0x01a19c50),
+	AZALIA_PIN_CFG(0, ALC887_MIC2, 0x02a19c60),
+	AZALIA_PIN_CFG(0, ALC887_LINE1, 0x0181345f),
+	AZALIA_PIN_CFG(0, ALC887_LINE2, 0x02214c20),
+	AZALIA_PIN_CFG(0, ALC887_CD, AZALIA_PIN_CFG_NC(0)),
+	AZALIA_PIN_CFG(0, ALC887_PC_BEEP, 0x4004c601),
+	AZALIA_PIN_CFG(0, ALC887_SPDIF_OUT1, AZALIA_PIN_CFG_NC(0)),
+	AZALIA_PIN_CFG(0, ALC887_SPDIF_IN, AZALIA_PIN_CFG_NC(0))
 };
 
 #endif
diff --git a/src/mainboard/gigabyte/ga-d510ud/hda_verb.c b/src/mainboard/gigabyte/ga-d510ud/hda_verb.c
index ff9e4ba97c..b6b888953b 100644
--- a/src/mainboard/gigabyte/ga-d510ud/hda_verb.c
+++ b/src/mainboard/gigabyte/ga-d510ud/hda_verb.c
@@ -1,26 +1,27 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
 #include <device/azalia_device.h>
+#include <device/azalia_codec/realtek.h>
 
 const u32 cim_verb_data[] = {
 	0x10ec0887,	/* Realtek ALC887 */
 	0x1458a002,	/* Subsystem ID */
 	15,		/* Number of 4 dword sets */
 	AZALIA_SUBVENDOR(2, 0x1458a002),
-	AZALIA_PIN_CFG(2, 0x11, AZALIA_PIN_CFG_NC(0)),
-	AZALIA_PIN_CFG(2, 0x12, AZALIA_PIN_CFG_NC(0)),
-	AZALIA_PIN_CFG(2, 0x14, 0x01014410),
-	AZALIA_PIN_CFG(2, 0x15, AZALIA_PIN_CFG_NC(0)),
-	AZALIA_PIN_CFG(2, 0x16, AZALIA_PIN_CFG_NC(0)),
-	AZALIA_PIN_CFG(2, 0x17, AZALIA_PIN_CFG_NC(0)),
-	AZALIA_PIN_CFG(2, 0x18, 0x01a19c30),
-	AZALIA_PIN_CFG(2, 0x19, 0x02a19c50),
-	AZALIA_PIN_CFG(2, 0x1a, 0x0181344f),
-	AZALIA_PIN_CFG(2, 0x1b, 0x02214c20),
-	AZALIA_PIN_CFG(2, 0x1c, 0x593301f0),
-	AZALIA_PIN_CFG(2, 0x1d, 0x4005c603),
-	AZALIA_PIN_CFG(2, 0x1e, AZALIA_PIN_CFG_NC(0)),
-	AZALIA_PIN_CFG(2, 0x1f, AZALIA_PIN_CFG_NC(0)),
+	AZALIA_PIN_CFG(2, ALC887_SPDIF_OUT2, AZALIA_PIN_CFG_NC(0)),
+	AZALIA_PIN_CFG(2, ALC887_DMIC_LR, AZALIA_PIN_CFG_NC(0)),
+	AZALIA_PIN_CFG(2, ALC887_FRONT, 0x01014410),
+	AZALIA_PIN_CFG(2, ALC887_SURROUND, AZALIA_PIN_CFG_NC(0)),
+	AZALIA_PIN_CFG(2, ALC887_CENTER_LFE, AZALIA_PIN_CFG_NC(0)),
+	AZALIA_PIN_CFG(2, ALC887_SIDE_SURROUND, AZALIA_PIN_CFG_NC(0)),
+	AZALIA_PIN_CFG(2, ALC887_MIC1, 0x01a19c30),
+	AZALIA_PIN_CFG(2, ALC887_MIC2, 0x02a19c50),
+	AZALIA_PIN_CFG(2, ALC887_LINE1, 0x0181344f),
+	AZALIA_PIN_CFG(2, ALC887_LINE2, 0x02214c20),
+	AZALIA_PIN_CFG(2, ALC887_CD, 0x593301f0),
+	AZALIA_PIN_CFG(2, ALC887_PC_BEEP, 0x4005c603),
+	AZALIA_PIN_CFG(2, ALC887_SPDIF_OUT1, AZALIA_PIN_CFG_NC(0)),
+	AZALIA_PIN_CFG(2, ALC887_SPDIF_IN, AZALIA_PIN_CFG_NC(0)),
 };
 
 const u32 pc_beep_verbs[] = {};
diff --git a/src/mainboard/gigabyte/ga-g41m-es2l/hda_verb.c b/src/mainboard/gigabyte/ga-g41m-es2l/hda_verb.c
index 71e34125b4..8acc12adf7 100644
--- a/src/mainboard/gigabyte/ga-g41m-es2l/hda_verb.c
+++ b/src/mainboard/gigabyte/ga-g41m-es2l/hda_verb.c
@@ -1,6 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0-or-later */
 
 #include <device/azalia_device.h>
+#include <device/azalia_codec/realtek.h>
 
 const u32 cim_verb_data[] = {
 	/* coreboot specific header */
@@ -10,20 +11,20 @@ const u32 cim_verb_data[] = {
 
 	/* Pin Widget Verb Table */
 
-	AZALIA_PIN_CFG(0, 0x11, 0x411110f0),
-	AZALIA_PIN_CFG(0, 0x12, AZALIA_PIN_CFG_NC(0)),
-	AZALIA_PIN_CFG(0, 0x14, 0x01014410),
-	AZALIA_PIN_CFG(0, 0x15, AZALIA_PIN_CFG_NC(0)),
-	AZALIA_PIN_CFG(0, 0x16, AZALIA_PIN_CFG_NC(0)),
-	AZALIA_PIN_CFG(0, 0x17, AZALIA_PIN_CFG_NC(0)),
-	AZALIA_PIN_CFG(0, 0x18, 0x01a19c40),
-	AZALIA_PIN_CFG(0, 0x19, 0x02a19c50),
-	AZALIA_PIN_CFG(0, 0x1a, 0x0181344f),
-	AZALIA_PIN_CFG(0, 0x1b, 0x02214c20),
-	AZALIA_PIN_CFG(0, 0x1c, 0x593301f0),
-	AZALIA_PIN_CFG(0, 0x1d, 0x4005c603),
-	AZALIA_PIN_CFG(0, 0x1e, 0x014b6130),
-	AZALIA_PIN_CFG(0, 0x1f, 0x01cb7160),
+	AZALIA_PIN_CFG(0, ALC887_SPDIF_OUT2, 0x411110f0),
+	AZALIA_PIN_CFG(0, ALC887_DMIC_LR, AZALIA_PIN_CFG_NC(0)),
+	AZALIA_PIN_CFG(0, ALC887_FRONT, 0x01014410),
+	AZALIA_PIN_CFG(0, ALC887_SURROUND, AZALIA_PIN_CFG_NC(0)),
+	AZALIA_PIN_CFG(0, ALC887_CENTER_LFE, AZALIA_PIN_CFG_NC(0)),
+	AZALIA_PIN_CFG(0, ALC887_SIDE_SURROUND, AZALIA_PIN_CFG_NC(0)),
+	AZALIA_PIN_CFG(0, ALC887_MIC1, 0x01a19c40),
+	AZALIA_PIN_CFG(0, ALC887_MIC2, 0x02a19c50),
+	AZALIA_PIN_CFG(0, ALC887_LINE1, 0x0181344f),
+	AZALIA_PIN_CFG(0, ALC887_LINE2, 0x02214c20),
+	AZALIA_PIN_CFG(0, ALC887_CD, 0x593301f0),
+	AZALIA_PIN_CFG(0, ALC887_PC_BEEP, 0x4005c603),
+	AZALIA_PIN_CFG(0, ALC887_SPDIF_OUT1, 0x014b6130),
+	AZALIA_PIN_CFG(0, ALC887_SPDIF_IN, 0x01cb7160),
 };
 
 const u32 pc_beep_verbs[0] = {};
diff --git a/src/mainboard/gigabyte/ga-h61m-series/variants/ga-h61m-ds2/hda_verb.c b/src/mainboard/gigabyte/ga-h61m-series/variants/ga-h61m-ds2/hda_verb.c
index 86bc679e37..a3efea95cf 100644
--- a/src/mainboard/gigabyte/ga-h61m-series/variants/ga-h61m-ds2/hda_verb.c
+++ b/src/mainboard/gigabyte/ga-h61m-series/variants/ga-h61m-ds2/hda_verb.c
@@ -1,26 +1,27 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
 #include <device/azalia_device.h>
+#include <device/azalia_codec/realtek.h>
 
 const u32 cim_verb_data[] = {
 	0x10ec0887,	/* Codec Vendor / Device ID: Realtek ALC887 */
 	0x1458a002,	/* Subsystem ID */
 	15,		/* Number of 4 dword sets */
 	AZALIA_SUBVENDOR(2, 0x1458a002),
-	AZALIA_PIN_CFG(2, 0x11, 0x411110f0),
-	AZALIA_PIN_CFG(2, 0x12, AZALIA_PIN_CFG_NC(0)),
-	AZALIA_PIN_CFG(2, 0x14, 0x01014410),
-	AZALIA_PIN_CFG(2, 0x15, AZALIA_PIN_CFG_NC(0)),
-	AZALIA_PIN_CFG(2, 0x16, AZALIA_PIN_CFG_NC(0)),
-	AZALIA_PIN_CFG(2, 0x17, AZALIA_PIN_CFG_NC(0)),
-	AZALIA_PIN_CFG(2, 0x18, 0x01a19c20),
-	AZALIA_PIN_CFG(2, 0x19, 0x02a19c30),
-	AZALIA_PIN_CFG(2, 0x1a, 0x0181342f),
-	AZALIA_PIN_CFG(2, 0x1b, 0x02214c1f),
-	AZALIA_PIN_CFG(2, 0x1c, AZALIA_PIN_CFG_NC(0)),
-	AZALIA_PIN_CFG(2, 0x1d, 0x4004c601),
-	AZALIA_PIN_CFG(2, 0x1e, AZALIA_PIN_CFG_NC(0)),
-	AZALIA_PIN_CFG(2, 0x1f, AZALIA_PIN_CFG_NC(0)),
+	AZALIA_PIN_CFG(2, ALC887_SPDIF_OUT2, 0x411110f0),
+	AZALIA_PIN_CFG(2, ALC887_DMIC_LR, AZALIA_PIN_CFG_NC(0)),
+	AZALIA_PIN_CFG(2, ALC887_FRONT, 0x01014410),
+	AZALIA_PIN_CFG(2, ALC887_SURROUND, AZALIA_PIN_CFG_NC(0)),
+	AZALIA_PIN_CFG(2, ALC887_CENTER_LFE, AZALIA_PIN_CFG_NC(0)),
+	AZALIA_PIN_CFG(2, ALC887_SIDE_SURROUND, AZALIA_PIN_CFG_NC(0)),
+	AZALIA_PIN_CFG(2, ALC887_MIC1, 0x01a19c20),
+	AZALIA_PIN_CFG(2, ALC887_MIC2, 0x02a19c30),
+	AZALIA_PIN_CFG(2, ALC887_LINE1, 0x0181342f),
+	AZALIA_PIN_CFG(2, ALC887_LINE2, 0x02214c1f),
+	AZALIA_PIN_CFG(2, ALC887_CD, AZALIA_PIN_CFG_NC(0)),
+	AZALIA_PIN_CFG(2, ALC887_PC_BEEP, 0x4004c601),
+	AZALIA_PIN_CFG(2, ALC887_SPDIF_OUT1, AZALIA_PIN_CFG_NC(0)),
+	AZALIA_PIN_CFG(2, ALC887_SPDIF_IN, AZALIA_PIN_CFG_NC(0)),
 };
 
 const u32 pc_beep_verbs[0] = {};
diff --git a/src/mainboard/gigabyte/ga-h61m-series/variants/ga-h61m-ds2v/hda_verb.c b/src/mainboard/gigabyte/ga-h61m-series/variants/ga-h61m-ds2v/hda_verb.c
index 3856bb0ca1..820276de6c 100644
--- a/src/mainboard/gigabyte/ga-h61m-series/variants/ga-h61m-ds2v/hda_verb.c
+++ b/src/mainboard/gigabyte/ga-h61m-series/variants/ga-h61m-ds2v/hda_verb.c
@@ -1,26 +1,27 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
 #include <device/azalia_device.h>
+#include <device/azalia_codec/realtek.h>
 
 const u32 cim_verb_data[] = {
 	0x10ec0887,	/* Realtek ALC887 */
 	0x1458a002,	/* Subsystem ID */
 	15,		/* Number of 4 dword sets */
 	AZALIA_SUBVENDOR(2, 0x1458a002),
-	AZALIA_PIN_CFG(2, 0x11, AZALIA_PIN_CFG_NC(0)),
-	AZALIA_PIN_CFG(2, 0x12, AZALIA_PIN_CFG_NC(0)),
-	AZALIA_PIN_CFG(2, 0x14, 0x01014410),
-	AZALIA_PIN_CFG(2, 0x15, AZALIA_PIN_CFG_NC(0)),
-	AZALIA_PIN_CFG(2, 0x16, AZALIA_PIN_CFG_NC(0)),
-	AZALIA_PIN_CFG(2, 0x17, AZALIA_PIN_CFG_NC(0)),
-	AZALIA_PIN_CFG(2, 0x18, 0x01a19c50),
-	AZALIA_PIN_CFG(2, 0x19, 0x02a19c60),
-	AZALIA_PIN_CFG(2, 0x1a, 0x0181345f),
-	AZALIA_PIN_CFG(2, 0x1b, 0x02214c20),
-	AZALIA_PIN_CFG(2, 0x1c, AZALIA_PIN_CFG_NC(0)),
-	AZALIA_PIN_CFG(2, 0x1d, 0x4004c601),
-	AZALIA_PIN_CFG(2, 0x1e, AZALIA_PIN_CFG_NC(0)),
-	AZALIA_PIN_CFG(2, 0x1f, AZALIA_PIN_CFG_NC(0)),
+	AZALIA_PIN_CFG(2, ALC887_SPDIF_OUT2, AZALIA_PIN_CFG_NC(0)),
+	AZALIA_PIN_CFG(2, ALC887_DMIC_LR, AZALIA_PIN_CFG_NC(0)),
+	AZALIA_PIN_CFG(2, ALC887_FRONT, 0x01014410),
+	AZALIA_PIN_CFG(2, ALC887_SURROUND, AZALIA_PIN_CFG_NC(0)),
+	AZALIA_PIN_CFG(2, ALC887_CENTER_LFE, AZALIA_PIN_CFG_NC(0)),
+	AZALIA_PIN_CFG(2, ALC887_SIDE_SURROUND, AZALIA_PIN_CFG_NC(0)),
+	AZALIA_PIN_CFG(2, ALC887_MIC1, 0x01a19c50),
+	AZALIA_PIN_CFG(2, ALC887_MIC2, 0x02a19c60),
+	AZALIA_PIN_CFG(2, ALC887_LINE1, 0x0181345f),
+	AZALIA_PIN_CFG(2, ALC887_LINE2, 0x02214c20),
+	AZALIA_PIN_CFG(2, ALC887_CD, AZALIA_PIN_CFG_NC(0)),
+	AZALIA_PIN_CFG(2, ALC887_PC_BEEP, 0x4004c601),
+	AZALIA_PIN_CFG(2, ALC887_SPDIF_OUT1, AZALIA_PIN_CFG_NC(0)),
+	AZALIA_PIN_CFG(2, ALC887_SPDIF_IN, AZALIA_PIN_CFG_NC(0)),
 };
 
 const u32 pc_beep_verbs[0] = {};
diff --git a/src/mainboard/gigabyte/ga-h61m-series/variants/ga-h61m-s2p-r3/hda_verb.c b/src/mainboard/gigabyte/ga-h61m-series/variants/ga-h61m-s2p-r3/hda_verb.c
index 3856bb0ca1..820276de6c 100644
--- a/src/mainboard/gigabyte/ga-h61m-series/variants/ga-h61m-s2p-r3/hda_verb.c
+++ b/src/mainboard/gigabyte/ga-h61m-series/variants/ga-h61m-s2p-r3/hda_verb.c
@@ -1,26 +1,27 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
 #include <device/azalia_device.h>
+#include <device/azalia_codec/realtek.h>
 
 const u32 cim_verb_data[] = {
 	0x10ec0887,	/* Realtek ALC887 */
 	0x1458a002,	/* Subsystem ID */
 	15,		/* Number of 4 dword sets */
 	AZALIA_SUBVENDOR(2, 0x1458a002),
-	AZALIA_PIN_CFG(2, 0x11, AZALIA_PIN_CFG_NC(0)),
-	AZALIA_PIN_CFG(2, 0x12, AZALIA_PIN_CFG_NC(0)),
-	AZALIA_PIN_CFG(2, 0x14, 0x01014410),
-	AZALIA_PIN_CFG(2, 0x15, AZALIA_PIN_CFG_NC(0)),
-	AZALIA_PIN_CFG(2, 0x16, AZALIA_PIN_CFG_NC(0)),
-	AZALIA_PIN_CFG(2, 0x17, AZALIA_PIN_CFG_NC(0)),
-	AZALIA_PIN_CFG(2, 0x18, 0x01a19c50),
-	AZALIA_PIN_CFG(2, 0x19, 0x02a19c60),
-	AZALIA_PIN_CFG(2, 0x1a, 0x0181345f),
-	AZALIA_PIN_CFG(2, 0x1b, 0x02214c20),
-	AZALIA_PIN_CFG(2, 0x1c, AZALIA_PIN_CFG_NC(0)),
-	AZALIA_PIN_CFG(2, 0x1d, 0x4004c601),
-	AZALIA_PIN_CFG(2, 0x1e, AZALIA_PIN_CFG_NC(0)),
-	AZALIA_PIN_CFG(2, 0x1f, AZALIA_PIN_CFG_NC(0)),
+	AZALIA_PIN_CFG(2, ALC887_SPDIF_OUT2, AZALIA_PIN_CFG_NC(0)),
+	AZALIA_PIN_CFG(2, ALC887_DMIC_LR, AZALIA_PIN_CFG_NC(0)),
+	AZALIA_PIN_CFG(2, ALC887_FRONT, 0x01014410),
+	AZALIA_PIN_CFG(2, ALC887_SURROUND, AZALIA_PIN_CFG_NC(0)),
+	AZALIA_PIN_CFG(2, ALC887_CENTER_LFE, AZALIA_PIN_CFG_NC(0)),
+	AZALIA_PIN_CFG(2, ALC887_SIDE_SURROUND, AZALIA_PIN_CFG_NC(0)),
+	AZALIA_PIN_CFG(2, ALC887_MIC1, 0x01a19c50),
+	AZALIA_PIN_CFG(2, ALC887_MIC2, 0x02a19c60),
+	AZALIA_PIN_CFG(2, ALC887_LINE1, 0x0181345f),
+	AZALIA_PIN_CFG(2, ALC887_LINE2, 0x02214c20),
+	AZALIA_PIN_CFG(2, ALC887_CD, AZALIA_PIN_CFG_NC(0)),
+	AZALIA_PIN_CFG(2, ALC887_PC_BEEP, 0x4004c601),
+	AZALIA_PIN_CFG(2, ALC887_SPDIF_OUT1, AZALIA_PIN_CFG_NC(0)),
+	AZALIA_PIN_CFG(2, ALC887_SPDIF_IN, AZALIA_PIN_CFG_NC(0)),
 };
 
 const u32 pc_beep_verbs[0] = {};
diff --git a/src/mainboard/gigabyte/ga-h61m-series/variants/ga-h61m-s2pv/hda_verb.c b/src/mainboard/gigabyte/ga-h61m-series/variants/ga-h61m-s2pv/hda_verb.c
index 3856bb0ca1..820276de6c 100644
--- a/src/mainboard/gigabyte/ga-h61m-series/variants/ga-h61m-s2pv/hda_verb.c
+++ b/src/mainboard/gigabyte/ga-h61m-series/variants/ga-h61m-s2pv/hda_verb.c
@@ -1,26 +1,27 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
 #include <device/azalia_device.h>
+#include <device/azalia_codec/realtek.h>
 
 const u32 cim_verb_data[] = {
 	0x10ec0887,	/* Realtek ALC887 */
 	0x1458a002,	/* Subsystem ID */
 	15,		/* Number of 4 dword sets */
 	AZALIA_SUBVENDOR(2, 0x1458a002),
-	AZALIA_PIN_CFG(2, 0x11, AZALIA_PIN_CFG_NC(0)),
-	AZALIA_PIN_CFG(2, 0x12, AZALIA_PIN_CFG_NC(0)),
-	AZALIA_PIN_CFG(2, 0x14, 0x01014410),
-	AZALIA_PIN_CFG(2, 0x15, AZALIA_PIN_CFG_NC(0)),
-	AZALIA_PIN_CFG(2, 0x16, AZALIA_PIN_CFG_NC(0)),
-	AZALIA_PIN_CFG(2, 0x17, AZALIA_PIN_CFG_NC(0)),
-	AZALIA_PIN_CFG(2, 0x18, 0x01a19c50),
-	AZALIA_PIN_CFG(2, 0x19, 0x02a19c60),
-	AZALIA_PIN_CFG(2, 0x1a, 0x0181345f),
-	AZALIA_PIN_CFG(2, 0x1b, 0x02214c20),
-	AZALIA_PIN_CFG(2, 0x1c, AZALIA_PIN_CFG_NC(0)),
-	AZALIA_PIN_CFG(2, 0x1d, 0x4004c601),
-	AZALIA_PIN_CFG(2, 0x1e, AZALIA_PIN_CFG_NC(0)),
-	AZALIA_PIN_CFG(2, 0x1f, AZALIA_PIN_CFG_NC(0)),
+	AZALIA_PIN_CFG(2, ALC887_SPDIF_OUT2, AZALIA_PIN_CFG_NC(0)),
+	AZALIA_PIN_CFG(2, ALC887_DMIC_LR, AZALIA_PIN_CFG_NC(0)),
+	AZALIA_PIN_CFG(2, ALC887_FRONT, 0x01014410),
+	AZALIA_PIN_CFG(2, ALC887_SURROUND, AZALIA_PIN_CFG_NC(0)),
+	AZALIA_PIN_CFG(2, ALC887_CENTER_LFE, AZALIA_PIN_CFG_NC(0)),
+	AZALIA_PIN_CFG(2, ALC887_SIDE_SURROUND, AZALIA_PIN_CFG_NC(0)),
+	AZALIA_PIN_CFG(2, ALC887_MIC1, 0x01a19c50),
+	AZALIA_PIN_CFG(2, ALC887_MIC2, 0x02a19c60),
+	AZALIA_PIN_CFG(2, ALC887_LINE1, 0x0181345f),
+	AZALIA_PIN_CFG(2, ALC887_LINE2, 0x02214c20),
+	AZALIA_PIN_CFG(2, ALC887_CD, AZALIA_PIN_CFG_NC(0)),
+	AZALIA_PIN_CFG(2, ALC887_PC_BEEP, 0x4004c601),
+	AZALIA_PIN_CFG(2, ALC887_SPDIF_OUT1, AZALIA_PIN_CFG_NC(0)),
+	AZALIA_PIN_CFG(2, ALC887_SPDIF_IN, AZALIA_PIN_CFG_NC(0)),
 };
 
 const u32 pc_beep_verbs[0] = {};
diff --git a/src/mainboard/gigabyte/ga-h61m-series/variants/ga-h61ma-d3v/hda_verb.c b/src/mainboard/gigabyte/ga-h61m-series/variants/ga-h61ma-d3v/hda_verb.c
index 3b00942080..93bf23c5d1 100644
--- a/src/mainboard/gigabyte/ga-h61m-series/variants/ga-h61ma-d3v/hda_verb.c
+++ b/src/mainboard/gigabyte/ga-h61m-series/variants/ga-h61ma-d3v/hda_verb.c
@@ -1,26 +1,27 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
 #include <device/azalia_device.h>
+#include <device/azalia_codec/realtek.h>
 
 const u32 cim_verb_data[] = {
 	0x10ec0887,	/* Realtek ALC887 */
 	0x1458a002,	/* Subsystem ID */
 	15,		/* Number of 4 dword sets */
 	AZALIA_SUBVENDOR(2, 0x1458a002),
-	AZALIA_PIN_CFG(2, 0x11, 0x411110f0),
-	AZALIA_PIN_CFG(2, 0x12, AZALIA_PIN_CFG_NC(0)),
-	AZALIA_PIN_CFG(2, 0x14, 0x01014410),
-	AZALIA_PIN_CFG(2, 0x15, AZALIA_PIN_CFG_NC(0)),
-	AZALIA_PIN_CFG(2, 0x16, AZALIA_PIN_CFG_NC(0)),
-	AZALIA_PIN_CFG(2, 0x17, AZALIA_PIN_CFG_NC(0)),
-	AZALIA_PIN_CFG(2, 0x18, 0x01a19c50),
-	AZALIA_PIN_CFG(2, 0x19, 0x02a19c60),
-	AZALIA_PIN_CFG(2, 0x1a, 0x0181345f),
-	AZALIA_PIN_CFG(2, 0x1b, 0x02214c20),
-	AZALIA_PIN_CFG(2, 0x1c, AZALIA_PIN_CFG_NC(0)),
-	AZALIA_PIN_CFG(2, 0x1d, 0x4004c601),
-	AZALIA_PIN_CFG(2, 0x1e, AZALIA_PIN_CFG_NC(0)),
-	AZALIA_PIN_CFG(2, 0x1f, 0x41c46060),
+	AZALIA_PIN_CFG(2, ALC887_SPDIF_OUT2, 0x411110f0),
+	AZALIA_PIN_CFG(2, ALC887_DMIC_LR, AZALIA_PIN_CFG_NC(0)),
+	AZALIA_PIN_CFG(2, ALC887_FRONT, 0x01014410),
+	AZALIA_PIN_CFG(2, ALC887_SURROUND, AZALIA_PIN_CFG_NC(0)),
+	AZALIA_PIN_CFG(2, ALC887_CENTER_LFE, AZALIA_PIN_CFG_NC(0)),
+	AZALIA_PIN_CFG(2, ALC887_SIDE_SURROUND, AZALIA_PIN_CFG_NC(0)),
+	AZALIA_PIN_CFG(2, ALC887_MIC1, 0x01a19c50),
+	AZALIA_PIN_CFG(2, ALC887_MIC2, 0x02a19c60),
+	AZALIA_PIN_CFG(2, ALC887_LINE1, 0x0181345f),
+	AZALIA_PIN_CFG(2, ALC887_LINE2, 0x02214c20),
+	AZALIA_PIN_CFG(2, ALC887_CD, AZALIA_PIN_CFG_NC(0)),
+	AZALIA_PIN_CFG(2, ALC887_PC_BEEP, 0x4004c601),
+	AZALIA_PIN_CFG(2, ALC887_SPDIF_OUT1, AZALIA_PIN_CFG_NC(0)),
+	AZALIA_PIN_CFG(2, ALC887_SPDIF_IN, 0x41c46060),
 };
 
 const u32 pc_beep_verbs[0] = {};
diff --git a/src/mainboard/gigabyte/ga-h81m-d2w/hda_verb.c b/src/mainboard/gigabyte/ga-h81m-d2w/hda_verb.c
index 5d6633955c..4b8c55c92f 100644
--- a/src/mainboard/gigabyte/ga-h81m-d2w/hda_verb.c
+++ b/src/mainboard/gigabyte/ga-h81m-d2w/hda_verb.c
@@ -1,26 +1,27 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
 #include <device/azalia_device.h>
+#include <device/azalia_codec/realtek.h>
 
 const u32 cim_verb_data[] = {
 	0x10ec0887,	/* Codec Vendor / Device ID: Realtek */
 	0x1458a002,	/* Subsystem ID */
 	15,		/* Number of 4 dword sets */
 	AZALIA_SUBVENDOR(0, 0x1458a002),
-	AZALIA_PIN_CFG(0, 0x11, 0x4037c040),
-	AZALIA_PIN_CFG(0, 0x12, AZALIA_PIN_CFG_NC(0)),
-	AZALIA_PIN_CFG(0, 0x14, 0x01014010),
-	AZALIA_PIN_CFG(0, 0x15, AZALIA_PIN_CFG_NC(0)),
-	AZALIA_PIN_CFG(0, 0x16, AZALIA_PIN_CFG_NC(0)),
-	AZALIA_PIN_CFG(0, 0x17, AZALIA_PIN_CFG_NC(0)),
-	AZALIA_PIN_CFG(0, 0x18, 0x01a19030),
-	AZALIA_PIN_CFG(0, 0x19, 0x02a19040),
-	AZALIA_PIN_CFG(0, 0x1a, 0x0181303f),
-	AZALIA_PIN_CFG(0, 0x1b, 0x02214020),
-	AZALIA_PIN_CFG(0, 0x1c, AZALIA_PIN_CFG_NC(0)),
-	AZALIA_PIN_CFG(0, 0x1d, 0x4024c601),
-	AZALIA_PIN_CFG(0, 0x1e, AZALIA_PIN_CFG_NC(0)),
-	AZALIA_PIN_CFG(0, 0x1f, AZALIA_PIN_CFG_NC(0)),
+	AZALIA_PIN_CFG(0, ALC887_SPDIF_OUT2, 0x4037c040),
+	AZALIA_PIN_CFG(0, ALC887_DMIC_LR, AZALIA_PIN_CFG_NC(0)),
+	AZALIA_PIN_CFG(0, ALC887_FRONT, 0x01014010),
+	AZALIA_PIN_CFG(0, ALC887_SURROUND, AZALIA_PIN_CFG_NC(0)),
+	AZALIA_PIN_CFG(0, ALC887_CENTER_LFE, AZALIA_PIN_CFG_NC(0)),
+	AZALIA_PIN_CFG(0, ALC887_SIDE_SURROUND, AZALIA_PIN_CFG_NC(0)),
+	AZALIA_PIN_CFG(0, ALC887_MIC1, 0x01a19030),
+	AZALIA_PIN_CFG(0, ALC887_MIC2, 0x02a19040),
+	AZALIA_PIN_CFG(0, ALC887_LINE1, 0x0181303f),
+	AZALIA_PIN_CFG(0, ALC887_LINE2, 0x02214020),
+	AZALIA_PIN_CFG(0, ALC887_CD, AZALIA_PIN_CFG_NC(0)),
+	AZALIA_PIN_CFG(0, ALC887_PC_BEEP, 0x4024c601),
+	AZALIA_PIN_CFG(0, ALC887_SPDIF_OUT1, AZALIA_PIN_CFG_NC(0)),
+	AZALIA_PIN_CFG(0, ALC887_SPDIF_IN, AZALIA_PIN_CFG_NC(0)),
 };
 
 const u32 pc_beep_verbs[0] = {};
diff --git a/src/mainboard/msi/h81m-p33/hda_verb.c b/src/mainboard/msi/h81m-p33/hda_verb.c
index 5c17ab3fee..4f5ac813ae 100644
--- a/src/mainboard/msi/h81m-p33/hda_verb.c
+++ b/src/mainboard/msi/h81m-p33/hda_verb.c
@@ -1,26 +1,27 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
 #include <device/azalia_device.h>
+#include <device/azalia_codec/realtek.h>
 
 const u32 cim_verb_data[] = {
 	0x10ec0887,	/* Codec Vendor / Device ID: Realtek ALC887-VD */
 	0x1462d817,	/* Subsystem ID */
 	15,		/* Number of 4 dword sets */
 	AZALIA_SUBVENDOR(0, 0x1462d817),
-	AZALIA_PIN_CFG(0, 0x11, 0x4037c040),
-	AZALIA_PIN_CFG(0, 0x12, AZALIA_PIN_CFG_NC(0)),
-	AZALIA_PIN_CFG(0, 0x14, 0x01014010),
-	AZALIA_PIN_CFG(0, 0x15, AZALIA_PIN_CFG_NC(0)),
-	AZALIA_PIN_CFG(0, 0x16, AZALIA_PIN_CFG_NC(0)),
-	AZALIA_PIN_CFG(0, 0x17, AZALIA_PIN_CFG_NC(0)),
-	AZALIA_PIN_CFG(0, 0x18, 0x01a19030),
-	AZALIA_PIN_CFG(0, 0x19, 0x02a19040),
-	AZALIA_PIN_CFG(0, 0x1a, 0x0181303f),
-	AZALIA_PIN_CFG(0, 0x1b, 0x02214020),
-	AZALIA_PIN_CFG(0, 0x1c, AZALIA_PIN_CFG_NC(0)),
-	AZALIA_PIN_CFG(0, 0x1d, 0x4025c603),
-	AZALIA_PIN_CFG(0, 0x1e, AZALIA_PIN_CFG_NC(0)),
-	AZALIA_PIN_CFG(0, 0x1f, AZALIA_PIN_CFG_NC(0)),
+	AZALIA_PIN_CFG(0, ALC887_SPDIF_OUT2, 0x4037c040),
+	AZALIA_PIN_CFG(0, ALC887_DMIC_LR, AZALIA_PIN_CFG_NC(0)),
+	AZALIA_PIN_CFG(0, ALC887_FRONT, 0x01014010),
+	AZALIA_PIN_CFG(0, ALC887_SURROUND, AZALIA_PIN_CFG_NC(0)),
+	AZALIA_PIN_CFG(0, ALC887_CENTER_LFE, AZALIA_PIN_CFG_NC(0)),
+	AZALIA_PIN_CFG(0, ALC887_SIDE_SURROUND, AZALIA_PIN_CFG_NC(0)),
+	AZALIA_PIN_CFG(0, ALC887_MIC1, 0x01a19030),
+	AZALIA_PIN_CFG(0, ALC887_MIC2, 0x02a19040),
+	AZALIA_PIN_CFG(0, ALC887_LINE1, 0x0181303f),
+	AZALIA_PIN_CFG(0, ALC887_LINE2, 0x02214020),
+	AZALIA_PIN_CFG(0, ALC887_CD, AZALIA_PIN_CFG_NC(0)),
+	AZALIA_PIN_CFG(0, ALC887_PC_BEEP, 0x4025c603),
+	AZALIA_PIN_CFG(0, ALC887_SPDIF_OUT1, AZALIA_PIN_CFG_NC(0)),
+	AZALIA_PIN_CFG(0, ALC887_SPDIF_IN, AZALIA_PIN_CFG_NC(0)),
 };
 
 const u32 pc_beep_verbs[0] = {};
diff --git a/src/mainboard/msi/ms7707/hda_verb.c b/src/mainboard/msi/ms7707/hda_verb.c
index bfbde22a11..9bd0a5adfe 100644
--- a/src/mainboard/msi/ms7707/hda_verb.c
+++ b/src/mainboard/msi/ms7707/hda_verb.c
@@ -1,26 +1,27 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
 #include <device/azalia_device.h>
+#include <device/azalia_codec/realtek.h>
 
 const u32 cim_verb_data[] = {
 	0x10ec0887,	/* Codec Vendor / Device ID: Realtek */
 	0x14627707,	/* Subsystem ID */
 	15,		/* Number of 4 dword sets */
 	AZALIA_SUBVENDOR(0, 0x14627707),
-	AZALIA_PIN_CFG(0, 0x11, AZALIA_PIN_CFG_NC(0)),
-	AZALIA_PIN_CFG(0, 0x12, AZALIA_PIN_CFG_NC(0)),
-	AZALIA_PIN_CFG(0, 0x14, 0x01014410),
-	AZALIA_PIN_CFG(0, 0x15, 0x01011412),
-	AZALIA_PIN_CFG(0, 0x16, 0x01016411),
-	AZALIA_PIN_CFG(0, 0x17, 0x01012414),
-	AZALIA_PIN_CFG(0, 0x18, 0x01813c40),
-	AZALIA_PIN_CFG(0, 0x19, 0x02a19c50),
-	AZALIA_PIN_CFG(0, 0x1a, AZALIA_PIN_CFG_NC(0)),
-	AZALIA_PIN_CFG(0, 0x1b, 0x02214c20),
-	AZALIA_PIN_CFG(0, 0x1c, AZALIA_PIN_CFG_NC(0)),
-	AZALIA_PIN_CFG(0, 0x1d, AZALIA_PIN_CFG_NC(0)),
-	AZALIA_PIN_CFG(0, 0x1e, 0x01454130),
-	AZALIA_PIN_CFG(0, 0x1f, AZALIA_PIN_CFG_NC(0)),
+	AZALIA_PIN_CFG(0, ALC887_SPDIF_OUT2, AZALIA_PIN_CFG_NC(0)),
+	AZALIA_PIN_CFG(0, ALC887_DMIC_LR, AZALIA_PIN_CFG_NC(0)),
+	AZALIA_PIN_CFG(0, ALC887_FRONT, 0x01014410),
+	AZALIA_PIN_CFG(0, ALC887_SURROUND, 0x01011412),
+	AZALIA_PIN_CFG(0, ALC887_CENTER_LFE, 0x01016411),
+	AZALIA_PIN_CFG(0, ALC887_SIDE_SURROUND, 0x01012414),
+	AZALIA_PIN_CFG(0, ALC887_MIC1, 0x01813c40),
+	AZALIA_PIN_CFG(0, ALC887_MIC2, 0x02a19c50),
+	AZALIA_PIN_CFG(0, ALC887_LINE1, AZALIA_PIN_CFG_NC(0)),
+	AZALIA_PIN_CFG(0, ALC887_LINE2, 0x02214c20),
+	AZALIA_PIN_CFG(0, ALC887_CD, AZALIA_PIN_CFG_NC(0)),
+	AZALIA_PIN_CFG(0, ALC887_PC_BEEP, AZALIA_PIN_CFG_NC(0)),
+	AZALIA_PIN_CFG(0, ALC887_SPDIF_OUT1, 0x01454130),
+	AZALIA_PIN_CFG(0, ALC887_SPDIF_IN, AZALIA_PIN_CFG_NC(0)),
 };
 
 const u32 pc_beep_verbs[0] = {};

From 8bc41fc937ef36c8d652e2ec9654edeab9c1c156 Mon Sep 17 00:00:00 2001
From: Kun Liu <liukun11@huaqin.corp-partner.google.com>
Date: Tue, 30 Sep 2025 15:24:21 +0800
Subject: [PATCH 2155/3886] mb/google/trulo/var/pujjocento: Update DTT settings
 for thermal control

The DPTF parameters were defined by the thermal team.
Based on thermal table in b:448253910 comment#1

BUG=b:448253910
TEST=emerge-nissa coreboot chromeos-bootimage

Change-Id: I91ad12bdb58432b3c2b867278ec5b396553ac2b9
Signed-off-by: Kun Liu <liukun11@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89380
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 .../google/brya/variants/pujjocento/overridetree.cb         | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/src/mainboard/google/brya/variants/pujjocento/overridetree.cb b/src/mainboard/google/brya/variants/pujjocento/overridetree.cb
index a648520a43..8b7382c8a0 100644
--- a/src/mainboard/google/brya/variants/pujjocento/overridetree.cb
+++ b/src/mainboard/google/brya/variants/pujjocento/overridetree.cb
@@ -215,8 +215,10 @@ chip soc/intel/alderlake
 				register "controls.charger_perf" = "{
 					[0] = { 255, 4700 },
 					[1] = {  40, 2500 },
-					[2] = {  16, 1000 },
-					[3] = {   8,  500 }
+					[2] = {  32, 2000 },
+					[3] = {  24, 1500 },
+					[4] = {  16, 1000 },
+					[5] = {   8,  500 }
 				}"
 
 				device generic 0 on

From 21f6ccf3a43d3e3ffc9db82ee28718f672acadf9 Mon Sep 17 00:00:00 2001
From: Jeremy Compostella <jeremy.compostella@intel.com>
Date: Mon, 29 Sep 2025 16:07:56 -0700
Subject: [PATCH 2156/3886] soc/intel/pantherlake: Use CPU ID mask for all
 stepping

This commit refactors the handling of CPU IDs for the Pantherlake and
Wildcat Lake series by using a single CPU ID mask instead of listing
each individual stepping. This change simplifies the code by reducing
redundancy and making it easier to manage CPU IDs.

Previously, each stepping of the Pantherlake series had its own entry,
which led to unnecessary complexity. By consolidating these into a
single entry with a mask, we improve maintainability and reduce
potential errors.

These modifications do not affect the existing functionality but
streamline the codebase for future updates and maintenance.

TEST=CPU ID c06c1 is properly identified as "Pantherlake".

Change-Id: Ie52ed860c096a3d157ae6580aeedf3acb8c723ab
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89375
Reviewed-by: Bora Guvendik <bora.guvendik@intel.corp-partner.google.com>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Reviewed-by: Jamie Ryu <jamie.m.ryu@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/include/cpu/intel/cpu_ids.h                       | 7 ++-----
 src/soc/intel/common/block/cpu/mp_init.c              | 7 ++-----
 src/soc/intel/pantherlake/bootblock/report_platform.c | 9 +++------
 3 files changed, 7 insertions(+), 16 deletions(-)

diff --git a/src/include/cpu/intel/cpu_ids.h b/src/include/cpu/intel/cpu_ids.h
index d8b067c1fa..ada3bfd216 100644
--- a/src/include/cpu/intel/cpu_ids.h
+++ b/src/include/cpu/intel/cpu_ids.h
@@ -86,10 +86,7 @@
 #define CPUID_LUNARLAKE_A0_1		0xb06d0
 #define CPUID_LUNARLAKE_A0_2		0xb06d1
 #define CPUID_ARROWLAKE_H_A0		0xc0652
-#define CPUID_PANTHERLAKE_A0		0xc06c0
-#define CPUID_PANTHERLAKE_B0_1		0xc06c1
-#define CPUID_PANTHERLAKE_B0_2		0xc06c2
-#define CPUID_PANTHERLAKE_B0_3		0xc06c3
+#define CPUID_PANTHERLAKE		0xc06c0
 #define CPUID_SNOWRIDGE_A0		0x80660
 #define CPUID_SNOWRIDGE_A1		0x80661
 #define CPUID_SNOWRIDGE_A2		0x80662
@@ -97,6 +94,6 @@
 #define CPUID_SNOWRIDGE_B0		0x80664
 #define CPUID_SNOWRIDGE_B1		0x80665
 #define CPUID_SNOWRIDGE_C0		0x80667
-#define CPUID_WILDCATLAKE_A0		0xd0650
+#define CPUID_WILDCATLAKE		0xd0650
 
 #endif /* CPU_INTEL_CPU_IDS_H */
diff --git a/src/soc/intel/common/block/cpu/mp_init.c b/src/soc/intel/common/block/cpu/mp_init.c
index b4ee88a0ad..fdee38d254 100644
--- a/src/soc/intel/common/block/cpu/mp_init.c
+++ b/src/soc/intel/common/block/cpu/mp_init.c
@@ -32,11 +32,8 @@ static struct device_operations cpu_dev_ops = {
 };
 
 static const struct cpu_device_id cpu_table[] = {
-	{ X86_VENDOR_INTEL, CPUID_WILDCATLAKE_A0, CPUID_EXACT_MATCH_MASK },
-	{ X86_VENDOR_INTEL, CPUID_PANTHERLAKE_A0, CPUID_EXACT_MATCH_MASK },
-	{ X86_VENDOR_INTEL, CPUID_PANTHERLAKE_B0_1, CPUID_EXACT_MATCH_MASK },
-	{ X86_VENDOR_INTEL, CPUID_PANTHERLAKE_B0_2, CPUID_EXACT_MATCH_MASK },
-	{ X86_VENDOR_INTEL, CPUID_PANTHERLAKE_B0_3, CPUID_EXACT_MATCH_MASK },
+	{ X86_VENDOR_INTEL, CPUID_WILDCATLAKE, CPUID_ALL_STEPPINGS_MASK },
+	{ X86_VENDOR_INTEL, CPUID_PANTHERLAKE, CPUID_ALL_STEPPINGS_MASK },
 	{ X86_VENDOR_INTEL, CPUID_LUNARLAKE_A0_1, CPUID_EXACT_MATCH_MASK },
 	{ X86_VENDOR_INTEL, CPUID_LUNARLAKE_A0_2, CPUID_EXACT_MATCH_MASK },
 	{ X86_VENDOR_INTEL, CPUID_METEORLAKE_A0_1, CPUID_EXACT_MATCH_MASK },
diff --git a/src/soc/intel/pantherlake/bootblock/report_platform.c b/src/soc/intel/pantherlake/bootblock/report_platform.c
index 540358238d..70d644ff52 100644
--- a/src/soc/intel/pantherlake/bootblock/report_platform.c
+++ b/src/soc/intel/pantherlake/bootblock/report_platform.c
@@ -20,11 +20,8 @@ static struct {
 	u32 cpuid;
 	const char *name;
 } cpu_table[] = {
-	{ CPUID_PANTHERLAKE_A0, "Pantherlake A0" },
-	{ CPUID_PANTHERLAKE_B0_1, "Pantherlake B0" },
-	{ CPUID_PANTHERLAKE_B0_2, "Pantherlake B0" },
-	{ CPUID_PANTHERLAKE_B0_3, "Pantherlake B0" },
-	{ CPUID_WILDCATLAKE_A0, "Wildcatlake A0" },
+	{ CPUID_PANTHERLAKE, "Pantherlake" },
+	{ CPUID_WILDCATLAKE, "Wildcatlake" },
 };
 
 static struct {
@@ -187,7 +184,7 @@ static void report_cpu_info(void)
 
 	/* Look for string to match the name */
 	for (i = 0; i < ARRAY_SIZE(cpu_table); i++) {
-		if (cpu_table[i].cpuid == cpu_id) {
+		if (cpuid_match(cpu_table[i].cpuid, cpu_id, CPUID_ALL_STEPPINGS_MASK)) {
 			cpu_type = cpu_table[i].name;
 			break;
 		}

From aef86a7e8944cc04198ac9ea6f1672d62e196a82 Mon Sep 17 00:00:00 2001
From: Nick Vaccaro <nvaccaro@google.com>
Date: Fri, 26 Sep 2025 12:55:39 -0700
Subject: [PATCH 2157/3886] mb/google/ocelot/var/ocelot: disable HDA GPIOs by
 default

Configure GPP_F10, GPP_F11, GPP_F12, GPP_F13, GPP_F16, and GPP_F17
as no-connects by default.  These GPIOs will be enabled in
fw_config.c if they are needed.

BUG=b:447648103
TEST='emerge-ocelot coreboot chromeos-bootimage`, flash and boot ocelot
and verify the AUDIO_ALC721_SNDW still works.

Change-Id: I7c07581e2b29bfc3e83314a065fba7d418e07c2a
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89359
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Avi Uday <aviuday@google.com>
Reviewed-by: Pranava Y N <pranavayn@google.com>
---
 src/mainboard/google/ocelot/variants/ocelot/gpio.c | 12 ++++++------
 1 file changed, 6 insertions(+), 6 deletions(-)

diff --git a/src/mainboard/google/ocelot/variants/ocelot/gpio.c b/src/mainboard/google/ocelot/variants/ocelot/gpio.c
index 9da94aff9a..e4592c7201 100644
--- a/src/mainboard/google/ocelot/variants/ocelot/gpio.c
+++ b/src/mainboard/google/ocelot/variants/ocelot/gpio.c
@@ -142,17 +142,17 @@ static const struct pad_config gpio_table[] = {
 	/* GPP_D09:     I2S_MCLK_HDR */
 	PAD_CFG_NF(GPP_D09, NONE, DEEP, NF1),
 	/* GPP_D10:     HDA_BCLK (HDR) */
-	PAD_CFG_NF(GPP_D10, NONE, DEEP, NF1),
+	PAD_NC(GPP_D10, NONE),
 	/* GPP_D11:     HDA_SYNC (HDR) */
-	PAD_CFG_NF(GPP_D11, NONE, DEEP, NF1),
+	PAD_NC(GPP_D11, NONE),
 	/* GPP_D12:     HDA_SDO (HDR) */
-	PAD_CFG_NF(GPP_D12, NONE, DEEP, NF1),
+	PAD_NC(GPP_D12, NONE),
 	/* GPP_D13:     HDA_SDI0 (HDR) */
-	PAD_CFG_NF(GPP_D13, NONE, DEEP, NF1),
+	PAD_NC(GPP_D13, NONE),
 	/* GPP_D16:     HDA_RST_N (HDR) */
-	PAD_CFG_NF(GPP_D16, NONE, DEEP, NF1),
+	PAD_NC(GPP_D16, NONE),
 	/* GPP_D17:     HDA_SDI1 (HDR) */
-	PAD_CFG_NF(GPP_D17, NONE, DEEP, NF1),
+	PAD_NC(GPP_D17, NONE),
 	/* GPP_D19:     NC */
 	PAD_NC(GPP_D19, NONE),
 	/* GPP_D21:     GPP_D21_UFS_REFCLK_R */

From fe5f8494f6433e6b41264c254f57cc5425acfd5b Mon Sep 17 00:00:00 2001
From: Nicholas Chin <nic.c3.14@gmail.com>
Date: Wed, 1 Oct 2025 22:36:00 -0600
Subject: [PATCH 2158/3886] docs/releases: Remove outdated "Upcoming release"
 in titles

coreboot 24.12, 24.08, and 4.21 have already been released, so the
"Upcoming release" text in their titles is outdated and unnecessary.

Change-Id: I19cb5585c838c64366e057ceeaf0a18e01372bfe
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89398
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
---
 Documentation/releases/coreboot-24.08-relnotes.md | 2 +-
 Documentation/releases/coreboot-24.12-relnotes.md | 2 +-
 Documentation/releases/coreboot-4.21-relnotes.md  | 2 +-
 3 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/Documentation/releases/coreboot-24.08-relnotes.md b/Documentation/releases/coreboot-24.08-relnotes.md
index 046b77b321..e2faeb0c7c 100644
--- a/Documentation/releases/coreboot-24.08-relnotes.md
+++ b/Documentation/releases/coreboot-24.08-relnotes.md
@@ -1,4 +1,4 @@
-Upcoming release - coreboot 24.08
+coreboot 24.08 release
 ========================================================================
 
 We are pleased to announce the release of coreboot 24.08, another significant
diff --git a/Documentation/releases/coreboot-24.12-relnotes.md b/Documentation/releases/coreboot-24.12-relnotes.md
index 51a581f84b..ef9c78b028 100644
--- a/Documentation/releases/coreboot-24.12-relnotes.md
+++ b/Documentation/releases/coreboot-24.12-relnotes.md
@@ -1,4 +1,4 @@
-Upcoming release - coreboot 24.12
+coreboot 24.12 release
 =================================
 
 We are pleased to announce the release of coreboot 24.12, another significant
diff --git a/Documentation/releases/coreboot-4.21-relnotes.md b/Documentation/releases/coreboot-4.21-relnotes.md
index 661c019c2a..95d0537040 100644
--- a/Documentation/releases/coreboot-4.21-relnotes.md
+++ b/Documentation/releases/coreboot-4.21-relnotes.md
@@ -1,4 +1,4 @@
-Upcoming release - coreboot 4.21
+coreboot 4.21 release
 ========================================================================
 
 The 4.21 release is scheduled for August 21st, 2023

From c94ca87d40ad50aa4de11e406add8156e992bf25 Mon Sep 17 00:00:00 2001
From: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Date: Wed, 1 Oct 2025 16:48:50 +0800
Subject: [PATCH 2159/3886] mb/google/fatcat/var/kinmen: Enable Intel DPTF
 support

Add initial thermal settings
- Remove fan control (handled by EC)
- Apply PL1/PL2 min & max values per thermal design

TEST=emerge-fatcat coreboot

Change-Id: I92b6f3a7aaab9fdf903215d09c941a13d591e413
Signed-off-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89391
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 .../fatcat/variants/kinmen/overridetree.cb    | 93 +++++++++++++++++++
 1 file changed, 93 insertions(+)

diff --git a/src/mainboard/google/fatcat/variants/kinmen/overridetree.cb b/src/mainboard/google/fatcat/variants/kinmen/overridetree.cb
index c1ed2a9400..e710082746 100644
--- a/src/mainboard/google/fatcat/variants/kinmen/overridetree.cb
+++ b/src/mainboard/google/fatcat/variants/kinmen/overridetree.cb
@@ -123,6 +123,99 @@ chip soc/intel/pantherlake
 			end
 		end
 
+		device ref dtt on
+			chip drivers/intel/dptf
+				## sensor information
+				register "options.tsr[0].desc" = ""DDR_SOC""
+				register "options.tsr[1].desc" = ""Ambient""
+				register "options.tsr[2].desc" = ""Charger""
+
+				## Active Policy
+				# FIXME: below values are initial reference values only
+				register "policies.active" = "{
+						[0] = {
+							.target = DPTF_TEMP_SENSOR_0,
+							.thresholds = {
+									TEMP_PCT(70, 97),
+									TEMP_PCT(65, 90),
+									TEMP_PCT(60, 80),
+									TEMP_PCT(55, 75),
+									TEMP_PCT(50, 65),
+									TEMP_PCT(45, 45),
+									TEMP_PCT(43, 30),
+								}
+							},
+						[1] = {
+							.target = DPTF_TEMP_SENSOR_1,
+							.thresholds = {
+									TEMP_PCT(70, 97),
+									TEMP_PCT(65, 90),
+									TEMP_PCT(60, 80),
+									TEMP_PCT(55, 75),
+									TEMP_PCT(50, 65),
+									TEMP_PCT(45, 45),
+									TEMP_PCT(43, 30),
+								}
+							},
+						[2] = {
+							.target = DPTF_TEMP_SENSOR_2,
+							.thresholds = {
+									TEMP_PCT(75, 90),
+									TEMP_PCT(70, 80),
+									TEMP_PCT(65, 70),
+									TEMP_PCT(60, 50),
+								}
+							}
+				}"
+
+				## Passive Policy
+				# TODO: below values are initial reference values only
+				register "policies.passive" = "{
+						[0] = DPTF_PASSIVE(CPU,         CPU,           95, 5000),
+						[1] = DPTF_PASSIVE(CPU,         TEMP_SENSOR_0, 80, 5000),
+						[2] = DPTF_PASSIVE(CPU,         TEMP_SENSOR_1, 80, 5000),
+						[3] = DPTF_PASSIVE(CHARGER,     TEMP_SENSOR_2, 75, 5000),
+				}"
+
+				## Critical Policy
+				# TODO: below values are initial reference values only
+				register "policies.critical" = "{
+						[0] = DPTF_CRITICAL(CPU,          105, SHUTDOWN),
+						[1] = DPTF_CRITICAL(TEMP_SENSOR_0, 85, SHUTDOWN),
+						[2] = DPTF_CRITICAL(TEMP_SENSOR_1, 85, SHUTDOWN),
+						[3] = DPTF_CRITICAL(TEMP_SENSOR_2, 85, SHUTDOWN),
+				}"
+
+				## Power Limits Control
+				register "controls.power_limits" = "{
+						.pl1 = {
+							.min_power = 12000,
+							.max_power = 15000,
+							.time_window_min = 28 * MSECS_PER_SEC,
+							.time_window_max = 32 * MSECS_PER_SEC,
+							.granularity = 200,
+						},
+						.pl2 = {
+							.min_power = 55000,
+							.max_power = 55000,
+							.time_window_min = 28 * MSECS_PER_SEC,
+							.time_window_max = 32 * MSECS_PER_SEC,
+							.granularity = 1000,
+						}
+				}"
+
+				## Charger Performance Control (Control, mA)
+				register "controls.charger_perf" = "{
+						[0] = { 255, 3000 },
+						[1] = {  24, 1500 },
+						[2] = {  16, 1000 },
+						[3] = {   8,  500 }
+				}"
+
+				device generic 0 alias dptf_policy on end
+			end
+		end
+
 		device ref iaa off end
 		device ref tbt_pcie_rp0 on end
 		device ref tbt_pcie_rp1 on

From a0c5669c1b2ec806be84a6c8a72965741530c12c Mon Sep 17 00:00:00 2001
From: Maxim Polyakov <max.senia.poliak@gmail.com>
Date: Mon, 29 Sep 2025 15:06:19 +0300
Subject: [PATCH 2160/3886] mb/asrock/imb-1222: Use macros for HDA verb table

Macros are generated using the hda-decoder utility.
TEST: update coreboot in ROM with this patch -> boot Ubuntu 24.04 again
      -> the hda-decoder output before and after the update are the same
      and the audio works.

Change-Id: I33d693a483c43a31d6dbb75a97b3ca5f5149fd69
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89371
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
---
 src/mainboard/asrock/imb-1222/hda_verb.c | 90 +++++++++++++++++++++---
 1 file changed, 81 insertions(+), 9 deletions(-)

diff --git a/src/mainboard/asrock/imb-1222/hda_verb.c b/src/mainboard/asrock/imb-1222/hda_verb.c
index 1397b87a5a..02db917b73 100644
--- a/src/mainboard/asrock/imb-1222/hda_verb.c
+++ b/src/mainboard/asrock/imb-1222/hda_verb.c
@@ -7,25 +7,97 @@ static const u32 realtek_alc887_vd_verbs[] = {
 	AZALIA_SUBVENDOR(0, 0x1849588a),
 	AZALIA_PIN_CFG(0, ALC887_SPDIF_OUT2, 0x40000000),
 	AZALIA_PIN_CFG(0, ALC887_DMIC_LR, AZALIA_PIN_CFG_NC(0)),
-	AZALIA_PIN_CFG(0, ALC887_FRONT, 0x01014020),
-	AZALIA_PIN_CFG(0, ALC887_SURROUND, 0x90170110),
+	AZALIA_PIN_CFG(0, ALC887_FRONT, AZALIA_PIN_DESC(
+		AZALIA_JACK,
+		AZALIA_EXTERNAL_PRIMARY_CHASSIS | AZALIA_REAR,
+		AZALIA_LINE_OUT,
+		AZALIA_STEREO_MONO_1_8,
+		AZALIA_GREEN,
+		AZALIA_JACK_PRESENCE_DETECT,
+		2, 0
+	)),
+	AZALIA_PIN_CFG(0, ALC887_SURROUND, AZALIA_PIN_DESC(
+		AZALIA_INTEGRATED,
+		AZALIA_INTERNAL,
+		AZALIA_SPEAKER,
+		AZALIA_OTHER_ANALOG,
+		AZALIA_COLOR_UNKNOWN,
+		AZALIA_NO_JACK_PRESENCE_DETECT,
+		1, 0
+	)),
 	AZALIA_PIN_CFG(0, ALC887_CENTER_LFE, AZALIA_PIN_CFG_NC(0)),
 	AZALIA_PIN_CFG(0, ALC887_SIDE_SURROUND, AZALIA_PIN_CFG_NC(0)),
-	AZALIA_PIN_CFG(0, ALC887_MIC1, 0x01a19050),
-	AZALIA_PIN_CFG(0, ALC887_MIC2, 0x02a19060),
+	AZALIA_PIN_CFG(0, ALC887_MIC1, AZALIA_PIN_DESC(
+		AZALIA_JACK,
+		AZALIA_EXTERNAL_PRIMARY_CHASSIS | AZALIA_REAR,
+		AZALIA_MIC_IN,
+		AZALIA_STEREO_MONO_1_8,
+		AZALIA_PINK,
+		AZALIA_JACK_PRESENCE_DETECT,
+		5, 0
+	)),
+	AZALIA_PIN_CFG(0, ALC887_MIC2, AZALIA_PIN_DESC(
+		AZALIA_JACK,
+		AZALIA_EXTERNAL_PRIMARY_CHASSIS | AZALIA_FRONT,
+		AZALIA_MIC_IN,
+		AZALIA_STEREO_MONO_1_8,
+		AZALIA_PINK,
+		AZALIA_JACK_PRESENCE_DETECT,
+		6, 0
+	)),
 	AZALIA_PIN_CFG(0, ALC887_LINE1, AZALIA_PIN_CFG_NC(0)),
-	AZALIA_PIN_CFG(0, ALC887_LINE2, 0x02214030),
+	AZALIA_PIN_CFG(0, ALC887_LINE2, AZALIA_PIN_DESC(
+		AZALIA_JACK,
+		AZALIA_EXTERNAL_PRIMARY_CHASSIS | AZALIA_FRONT,
+		AZALIA_HP_OUT,
+		AZALIA_STEREO_MONO_1_8,
+		AZALIA_GREEN,
+		AZALIA_JACK_PRESENCE_DETECT,
+		3, 0
+	)),
 	AZALIA_PIN_CFG(0, ALC887_CD, AZALIA_PIN_CFG_NC(0)),
 	AZALIA_PIN_CFG(0, ALC887_PC_BEEP, 0x4024c601),
-	AZALIA_PIN_CFG(0, ALC887_SPDIF_OUT1, 0x01451140),
+	AZALIA_PIN_CFG(0, ALC887_SPDIF_OUT1, AZALIA_PIN_DESC(
+		AZALIA_JACK,
+		AZALIA_EXTERNAL_PRIMARY_CHASSIS | AZALIA_REAR,
+		AZALIA_SPDIF_OUT,
+		AZALIA_OPTICAL,
+		AZALIA_BLACK,
+		AZALIA_NO_JACK_PRESENCE_DETECT,
+		4, 0
+	)),
 	AZALIA_PIN_CFG(0, ALC887_SPDIF_IN, AZALIA_PIN_CFG_NC(0)),
 };
 
 static const u32 intel_display_audio_verbs[] = {
 	AZALIA_SUBVENDOR(2, 0x80860101),
-	AZALIA_PIN_CFG(2, 0x05, 0x18560010),
-	AZALIA_PIN_CFG(2, 0x06, 0x18560020),
-	AZALIA_PIN_CFG(2, 0x07, 0x18560030),
+	AZALIA_PIN_CFG(2, 0x05, AZALIA_PIN_DESC(
+		AZALIA_JACK,
+		AZALIA_DIGITAL_DISPLAY,
+		AZALIA_DIGITAL_OTHER_OUT,
+		AZALIA_OTHER_DIGITAL,
+		AZALIA_COLOR_UNKNOWN,
+		AZALIA_JACK_PRESENCE_DETECT,
+		1, 0
+	)),
+	AZALIA_PIN_CFG(2, 0x06, AZALIA_PIN_DESC(
+		AZALIA_JACK,
+		AZALIA_DIGITAL_DISPLAY,
+		AZALIA_DIGITAL_OTHER_OUT,
+		AZALIA_OTHER_DIGITAL,
+		AZALIA_COLOR_UNKNOWN,
+		AZALIA_JACK_PRESENCE_DETECT,
+		2, 0
+	)),
+	AZALIA_PIN_CFG(2, 0x07, AZALIA_PIN_DESC(
+		AZALIA_JACK,
+		AZALIA_DIGITAL_DISPLAY,
+		AZALIA_DIGITAL_OTHER_OUT,
+		AZALIA_OTHER_DIGITAL,
+		AZALIA_COLOR_UNKNOWN,
+		AZALIA_JACK_PRESENCE_DETECT,
+		3, 0
+	)),
 };
 
 const u32 pc_beep_verbs[] = {

From 6a016a784b12f31e62e7b9f9f73bf9dccb88a048 Mon Sep 17 00:00:00 2001
From: Martin Roth <gaumless@gmail.com>
Date: Tue, 30 Sep 2025 18:31:04 -0600
Subject: [PATCH 2161/3886] Documentation: Finalize 25.09 release notes

This updates the statistics for actual release tag.

Change-Id: I84116caa35be2df28372dd4293ad73eb13ec9dd4
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89387
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
---
 .../releases/coreboot-25.09-relnotes.md          | 16 ++++++++--------
 1 file changed, 8 insertions(+), 8 deletions(-)

diff --git a/Documentation/releases/coreboot-25.09-relnotes.md b/Documentation/releases/coreboot-25.09-relnotes.md
index fafbc1795b..670b079fb8 100644
--- a/Documentation/releases/coreboot-25.09-relnotes.md
+++ b/Documentation/releases/coreboot-25.09-relnotes.md
@@ -1,4 +1,4 @@
-Upcoming release - coreboot 25.09
+coreboot 25.09 release
 ========================================================================
 
 The coreboot project is pleased to announce the release of coreboot
@@ -223,15 +223,15 @@ Platform Updates
 Statistics from the 25.06 to 25.09 release
 --------------------------------------------
 
-* Total Commits: 684
+* Total Commits: 687
 * Average Commits per day: 7.55
-* Total lines added: 62999
-* Average lines added per commit: 92.10
-* Number of patches adding more than 100 lines: 73
+* Total lines added: 63366
+* Average lines added per commit: 92.24
+* Number of patches adding more than 100 lines: 75
 * Average lines added per small commit: 38.99
-* Total lines removed: 10251
-* Average lines removed per commit: 14.99
-* Total difference between added and removed: 52748
+* Total lines removed: 10294
+* Average lines removed per commit: 14.98
+* Total difference between added and removed: 53072
 * Total authors: 112
 * New authors: 21
 

From 1f2408f573003a1a886d76e62fd08d89acfae315 Mon Sep 17 00:00:00 2001
From: Julius Werner <jwerner@chromium.org>
Date: Wed, 1 Oct 2025 13:03:13 -0700
Subject: [PATCH 2162/3886] console: Fix flushing for slow consoles

Commit 266041f0e622 ("console: Add compile-time fast path when only
CBMEM console is used") introduced a typo when refactoring CBMEM console
fast path code that effectively causes consoles to never get flushed.
The fact that nobody complained in 3 years shows that the flush callback
is probably not that important for most consoles in practice. Still,
it's a pretty bad bug and should be fixed.

Change-Id: Ib9b96cb744447ccba99c4186540442b542914e01
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89397
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/console/printk.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/console/printk.c b/src/console/printk.c
index 99710e60be..2ad70ae4c9 100644
--- a/src/console/printk.c
+++ b/src/console/printk.c
@@ -143,7 +143,7 @@ int vprintk(int msg_level, const char *fmt, va_list args)
 	console_time_run();
 
 	i = vtxprintf(wrap_putchar, fmt, args, state.as_ptr);
-	if (LOG_FAST(state))
+	if (!LOG_FAST(state))
 		console_tx_flush();
 
 	console_time_stop();

From d9b609b139c619ea1fe8f2b442469992a6487fe5 Mon Sep 17 00:00:00 2001
From: Elyes Haouas <ehaouas@noos.fr>
Date: Thu, 2 Oct 2025 15:01:22 +0200
Subject: [PATCH 2163/3886] nb/intel/haswell: Use boolean for cbmem_was_initted

Change-Id: I4a311ce924200d85a97806bb3c826a374e68d81c
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89399
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/northbridge/intel/haswell/broadwell_mrc/raminit.c | 2 +-
 src/northbridge/intel/haswell/haswell_mrc/raminit.c   | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/northbridge/intel/haswell/broadwell_mrc/raminit.c b/src/northbridge/intel/haswell/broadwell_mrc/raminit.c
index 5b2427b918..e96f1a3adf 100644
--- a/src/northbridge/intel/haswell/broadwell_mrc/raminit.c
+++ b/src/northbridge/intel/haswell/broadwell_mrc/raminit.c
@@ -422,7 +422,7 @@ void perform_raminit(const int s3resume)
 
 	intel_early_me_status();
 
-	int cbmem_was_initted = !cbmem_recovery(s3resume);
+	bool cbmem_was_initted = !cbmem_recovery(s3resume);
 	if (s3resume && !cbmem_was_initted) {
 		/* Failed S3 resume, reset to come up cleanly */
 		printk(BIOS_CRIT, "Failed to recover CBMEM in S3 resume.\n");
diff --git a/src/northbridge/intel/haswell/haswell_mrc/raminit.c b/src/northbridge/intel/haswell/haswell_mrc/raminit.c
index 3d5e46cdac..62aa89ca79 100644
--- a/src/northbridge/intel/haswell/haswell_mrc/raminit.c
+++ b/src/northbridge/intel/haswell/haswell_mrc/raminit.c
@@ -417,7 +417,7 @@ void perform_raminit(const int s3resume)
 
 	intel_early_me_status();
 
-	int cbmem_was_initted = !cbmem_recovery(s3resume);
+	bool cbmem_was_initted = !cbmem_recovery(s3resume);
 	if (s3resume && !cbmem_was_initted) {
 		/* Failed S3 resume, reset to come up cleanly */
 		printk(BIOS_CRIT, "Failed to recover CBMEM in S3 resume.\n");

From d9979ba6a3622bf7968f97734fe00e2864d6f843 Mon Sep 17 00:00:00 2001
From: Kilian Krause <kilian.krause@siemens.com>
Date: Tue, 30 Sep 2025 13:12:26 +0200
Subject: [PATCH 2164/3886] mb/siemens/mc_rpl: Sort includes alphabetically

Sort the #include statements alphabetically in multiple files to
improve code organization.

Change-Id: Ib9ed356a2ea84e54a43904a53c15c0ff10bc96b7
Signed-off-by: Kilian Krause <kilian.krause@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89392
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
---
 src/mainboard/siemens/mc_rpl/mainboard.c         | 16 ++++++++--------
 .../siemens/mc_rpl/romstage_fsp_params.c         |  4 ++--
 .../siemens/mc_rpl/variants/mc_rpl1/variant.c    |  2 +-
 3 files changed, 11 insertions(+), 11 deletions(-)

diff --git a/src/mainboard/siemens/mc_rpl/mainboard.c b/src/mainboard/siemens/mc_rpl/mainboard.c
index a96ab859cd..69670aa0ec 100644
--- a/src/mainboard/siemens/mc_rpl/mainboard.c
+++ b/src/mainboard/siemens/mc_rpl/mainboard.c
@@ -2,18 +2,18 @@
 
 #include <baseboard/gpio.h>
 #include <baseboard/variants.h>
+#include <cpu/x86/msr.h>
 #include <device/device.h>
-#include <soc/gpio.h>
-#include <stdint.h>
-#include <stdio.h>
+#include <device/pci_def.h>
+#include <device/pci_ids.h>
+#include <device/pci_ops.h>
 #include <hwilib.h>
 #include <i210.h>
-#include <soc/ramstage.h>
-#include <device/pci_def.h>
-#include <device/pci_ops.h>
-#include <device/pci_ids.h>
-#include <cpu/x86/msr.h>
+#include <soc/gpio.h>
 #include <soc/msr.h>
+#include <soc/ramstage.h>
+#include <stdint.h>
+#include <stdio.h>
 
 #define MAX_PATH_DEPTH		12
 #define MAX_NUM_MAPPINGS	10
diff --git a/src/mainboard/siemens/mc_rpl/romstage_fsp_params.c b/src/mainboard/siemens/mc_rpl/romstage_fsp_params.c
index 0026821820..5310746832 100644
--- a/src/mainboard/siemens/mc_rpl/romstage_fsp_params.c
+++ b/src/mainboard/siemens/mc_rpl/romstage_fsp_params.c
@@ -1,12 +1,12 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
+#include <baseboard/variants.h>
 #include <console/console.h>
 #include <fsp/api.h>
 #include <hwilib.h>
+#include <soc/meminit.h>
 #include <soc/romstage.h>
 #include <spd_bin.h>
-#include <soc/meminit.h>
-#include <baseboard/variants.h>
 
 /*
  * ADL-P silicon can support 7 SRC CLK's and 10 CLKREQ signals. Out of 7 SRCCLK's
diff --git a/src/mainboard/siemens/mc_rpl/variants/mc_rpl1/variant.c b/src/mainboard/siemens/mc_rpl/variants/mc_rpl1/variant.c
index 91f5cbd496..86e1ddf2eb 100644
--- a/src/mainboard/siemens/mc_rpl/variants/mc_rpl1/variant.c
+++ b/src/mainboard/siemens/mc_rpl/variants/mc_rpl1/variant.c
@@ -1,8 +1,8 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
+#include <baseboard/variants.h>
 #include <console/console.h>
 #include <fsp/api.h>
-#include <baseboard/variants.h>
 
 void variant_configure_fspm(FSPM_UPD *memupd)
 {

From 10361583b3226bfdca3e4f86b9669a5702fcbadc Mon Sep 17 00:00:00 2001
From: Kilian Krause <kilian.krause@siemens.com>
Date: Tue, 30 Sep 2025 16:12:12 +0200
Subject: [PATCH 2165/3886] mb/siemens/mc_rpl: Add code to wait for legacy
 devices before PCI scan

All mc_rpl boards have, like the mc_apl and mc_ehl variants, legacy
PCI devices which take longer to boot. To ensure their correct
enumeration, a delay is added before the PCI scan starts. The delay
value is provided by hwinfo.

TEST=Built and booted on mc_rpl board. Verified legacy PCI devices
enumerate correctly after delay implementation. Log excerpt while
testing function:

```
[INFO ]  tlcl2_extend: response is 0x0
[DEBUG]  TPM: Digest of `CBFS: hwinfo.hex` to PCR 3 measured
[NOTE ]  Wait remaining 6595702 of 10000000 us for legacy devices...done!
[DEBUG]  BS: BS_DEV_ENUMERATE entry times (exec / console): 6597 / 64 ms
[INFO ]  Enumerating buses...
```

Change-Id: I97885a7cf060bc69c7fef75a9fa917bc8a176582
Signed-off-by: Kilian Krause <kilian.krause@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89393
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
---
 src/mainboard/siemens/mc_rpl/mainboard.c | 30 ++++++++++++++++++++++++
 1 file changed, 30 insertions(+)

diff --git a/src/mainboard/siemens/mc_rpl/mainboard.c b/src/mainboard/siemens/mc_rpl/mainboard.c
index 69670aa0ec..44b11a0825 100644
--- a/src/mainboard/siemens/mc_rpl/mainboard.c
+++ b/src/mainboard/siemens/mc_rpl/mainboard.c
@@ -2,6 +2,7 @@
 
 #include <baseboard/gpio.h>
 #include <baseboard/variants.h>
+#include <bootstate.h>
 #include <cpu/x86/msr.h>
 #include <device/device.h>
 #include <device/pci_def.h>
@@ -14,6 +15,8 @@
 #include <soc/ramstage.h>
 #include <stdint.h>
 #include <stdio.h>
+#include <timer.h>
+#include <timestamp.h>
 
 #define MAX_PATH_DEPTH		12
 #define MAX_NUM_MAPPINGS	10
@@ -91,6 +94,31 @@ enum cb_err mainboard_get_mac_address(struct device *dev, uint8_t mac[MAC_ADDR_L
 	return CB_ERR;
 }
 
+static void wait_for_legacy_dev(void *unused)
+{
+	uint32_t legacy_delay_us, us_since_boot;
+	struct stopwatch sw;
+
+	/* Open main hwinfo block. */
+	if (hwilib_find_blocks("hwinfo.hex") != CB_SUCCESS)
+		return;
+
+	/* Get legacy delay parameter from hwinfo. */
+	if (hwilib_get_field(LegacyDelay, (uint8_t *)&legacy_delay_us,
+			sizeof(legacy_delay_us)) != sizeof(legacy_delay_us))
+		return;
+
+	us_since_boot = get_us_since_boot();
+	/* No need to wait if the time since boot is already long enough.*/
+	if (us_since_boot > legacy_delay_us)
+		return;
+	stopwatch_init_msecs_expire(&sw, (legacy_delay_us - us_since_boot) / 1000);
+	printk(BIOS_NOTICE, "Wait remaining %d of %d us for legacy devices...",
+			legacy_delay_us - us_since_boot, legacy_delay_us);
+	stopwatch_wait_until_expired(&sw);
+	printk(BIOS_NOTICE, " done!\n");
+}
+
 void mainboard_silicon_init_params(FSP_S_CONFIG *params)
 {
 	params->Eist = 0;
@@ -130,3 +158,5 @@ struct chip_operations mainboard_ops = {
 	.init = mainboard_init,
 	.final = mainboard_final,
 };
+
+BOOT_STATE_INIT_ENTRY(BS_DEV_ENUMERATE, BS_ON_ENTRY, wait_for_legacy_dev, NULL);

From 9c0c925fe6a29afbb8a5c86771fa2af50476cd3a Mon Sep 17 00:00:00 2001
From: Kilian Krause <kilian.krause@siemens.com>
Date: Wed, 1 Oct 2025 10:18:35 +0200
Subject: [PATCH 2166/3886] mb/siemens/mc_rpl1: Send POST codes to NC FPGA via
 PCI

This board uses PCI to send POST codes to the NC FPGA. Enable the
feature of sending the POST codes to the NC FPGA via PCI so that the
POST codes are visible in coreboot.

TEST=Built and booted on mc_rpl1. Check that the POST Codes are
correctly displayed on the 7-segment display.

Change-Id: I95a1ac7121560b812aea36485c37f39e13de535a
Signed-off-by: Kilian Krause <kilian.krause@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89394
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
---
 .../siemens/mc_rpl/variants/mc_rpl1/Kconfig      | 16 ++++++++++++++++
 .../siemens/mc_rpl/variants/mc_rpl1/Makefile.mk  |  2 ++
 .../siemens/mc_rpl/variants/mc_rpl1/post.c       | 10 ++++++++++
 3 files changed, 28 insertions(+)
 create mode 100644 src/mainboard/siemens/mc_rpl/variants/mc_rpl1/post.c

diff --git a/src/mainboard/siemens/mc_rpl/variants/mc_rpl1/Kconfig b/src/mainboard/siemens/mc_rpl/variants/mc_rpl1/Kconfig
index a56d4c5b7a..858cb3fce8 100644
--- a/src/mainboard/siemens/mc_rpl/variants/mc_rpl1/Kconfig
+++ b/src/mainboard/siemens/mc_rpl/variants/mc_rpl1/Kconfig
@@ -10,9 +10,25 @@ config BOARD_SPECIFIC_OPTIONS
 	select TPM_MEASURED_BOOT
 	select TPM_MEASURED_BOOT_INIT_BOOTBLOCK
 	select DRIVER_INTEL_I210
+	select NC_FPGA_POST_CODE
 
 config UART_FOR_CONSOLE
 	int
 	default 2
 
+config EARLY_PCI_BRIDGE_DEVICE
+	hex
+	depends on NC_FPGA_POST_CODE
+	default 0x1c
+
+config EARLY_PCI_BRIDGE_FUNCTION
+	hex
+	depends on NC_FPGA_POST_CODE
+	default 0x0
+
+config EARLY_PCI_MMIO_BASE
+	hex
+	depends on NC_FPGA_POST_CODE
+	default 0xfe400000
+
 endif # BOARD_SIEMENS_MC_RPL1
diff --git a/src/mainboard/siemens/mc_rpl/variants/mc_rpl1/Makefile.mk b/src/mainboard/siemens/mc_rpl/variants/mc_rpl1/Makefile.mk
index 248d22b18c..03a936c199 100644
--- a/src/mainboard/siemens/mc_rpl/variants/mc_rpl1/Makefile.mk
+++ b/src/mainboard/siemens/mc_rpl/variants/mc_rpl1/Makefile.mk
@@ -3,3 +3,5 @@
 bootblock-y += early_gpio.c
 ramstage-y += gpio.c
 romstage-y += variant.c
+
+all-$(CONFIG_NC_FPGA_POST_CODE) += post.c
diff --git a/src/mainboard/siemens/mc_rpl/variants/mc_rpl1/post.c b/src/mainboard/siemens/mc_rpl/variants/mc_rpl1/post.c
new file mode 100644
index 0000000000..c34e2539bc
--- /dev/null
+++ b/src/mainboard/siemens/mc_rpl/variants/mc_rpl1/post.c
@@ -0,0 +1,10 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <console/console.h>
+#include <nc_fpga.h>
+#include <types.h>
+
+void mainboard_post(uint8_t value)
+{
+	nc_fpga_post(value);
+}

From a927d124be1f295107cbfb3c43e2e83b31b5b0cb Mon Sep 17 00:00:00 2001
From: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Date: Thu, 7 Aug 2025 09:19:03 +0900
Subject: [PATCH 2167/3886] mb/asus: Replace verb tables with reworked
 implementation
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Some boards did not provide the chip name for the audio codecs in the
comments, and were therefore identified using external sources:

  h61m-a_usb3:
    - 0x10ec0887 -> Realtek ALC887[1][5]
  h61m-cs:
    - 0x10ec0887 -> Realtek ALC887[1][6]
  p8h61-m_pro:
    - 0x10ec0887 -> Realtek ALC887-VD[3]
  p8h67-i_deluxe:
    - 0x10ec0892 -> Realtek ALC892[3][7]
  p5gc-mx:
    - 0x10ec0892 -> Realtek ALC662[2]
  p5qc:
    - 0x10ec0888 -> Realtek ALC1200[2]
  p5ql-em:
    - 0x10ec0888 -> Realtek ALC1200[8]
  p8z77-m:
    - 0x10ec0887 -> Realtek ALC887[1][9]
  p8z77-v:
    - 0x10ec0892 -> Realtek ALC892[3][10]
  p8z77-v_le_plus:
    - 0x10ec0889 -> Realtek ALC889[4][11]

The Kconfigs were reverted using the following command:
  find src/mainboard/asus -name 'Kconfig' | xargs git checkout main

It should be noted that we do not modifiy the verb tables in any case,
as it would break the regression test script mentioned in the TEST
section below.

For an overall rationale for this rework, see commit 31fc5b06a6be
("device: Introduce reworked azalia verb table").

References:
[1]  Linux kernel: sound/hda/codecs/realtek/alc882.c:839
[2]  coreboot board status: kernel_log.txt
[3]  Linux kernel: sound/hda/codecs/realtek/alc662.c:1101
[4]  Linux kernel: sound/hda/codecs/realtek/alc882.c:842
[5]  H61M-A/USB3 User's Manual (English), Version E8184
[6]  H61M-CS User's Manual (English), Version E9069
[7]  P8H67-I Deluxe User's Manual (English), Version E6964
[8]  P5QL-EM user’s manual(English), Version E4165
[9]  P8Z77-M User's Manual (English), Version E7075
[10] P8Z77-V User's Manual (English), Version E7074
[11] P8Z77-V LE PLUS User's Manual (English), Version E8001

TEST= All boards passed regression test (CB:88763)

Change-Id: Id2d4895bb40885f83d602b3a80805a84e348771b
Signed-off-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88662
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
---
 src/mainboard/asus/h61-series/Kconfig         |  1 -
 .../variants/h61m-a_usb3/hda_verb.c           | 53 +++++++++++++++----
 .../h61-series/variants/h61m-cs/hda_verb.c    | 17 ++++--
 .../h61-series/variants/p8h61-m_lx/hda_verb.c | 17 ++++--
 .../variants/p8h61-m_lx3_r2_0/hda_verb.c      | 17 ++++--
 .../variants/p8h61-m_pro/hda_verb.c           | 30 ++++++++---
 .../variants/p8h61-m_pro_cm6630/hda_verb.c    | 30 ++++++++---
 .../variants/p8h67-i_deluxe/hda_verb.c        | 30 ++++++++---
 src/mainboard/asus/h610i-plus-d4/Kconfig      |  1 -
 src/mainboard/asus/h610i-plus-d4/hda_verb.c   | 31 ++++++++---
 src/mainboard/asus/maximus_iv_gene-z/Kconfig  |  1 -
 .../asus/maximus_iv_gene-z/hda_verb.c         | 30 ++++++++---
 src/mainboard/asus/p5gc-mx/Kconfig            |  1 -
 src/mainboard/asus/p5gc-mx/hda_verb.c         | 21 +++++---
 src/mainboard/asus/p5qc/Kconfig               |  1 -
 src/mainboard/asus/p5qc/hda_verb.c            | 21 +++++---
 src/mainboard/asus/p5ql-em/Kconfig            |  1 -
 src/mainboard/asus/p5ql-em/hda_verb.c         | 35 +++++++-----
 src/mainboard/asus/p5qpl-am/Kconfig           |  1 -
 src/mainboard/asus/p5qpl-am/hda_verb.c        | 22 ++++----
 src/mainboard/asus/p8x7x-series/Kconfig       |  1 -
 .../p8x7x-series/variants/p8c_ws/hda_verb.c   | 17 ++++--
 .../p8x7x-series/variants/p8h77-v/hda_verb.c  | 30 ++++++++---
 .../p8x7x-series/variants/p8z77-m/hda_verb.c  | 30 ++++++++---
 .../variants/p8z77-m_pro/hda_verb.c           | 30 ++++++++---
 .../p8x7x-series/variants/p8z77-v/hda_verb.c  | 31 ++++++++---
 .../variants/p8z77-v_le_plus/hda_verb.c       | 31 ++++++++---
 .../variants/p8z77-v_lx2/hda_verb.c           | 30 ++++++++---
 28 files changed, 411 insertions(+), 150 deletions(-)

diff --git a/src/mainboard/asus/h61-series/Kconfig b/src/mainboard/asus/h61-series/Kconfig
index 6f21b75456..d09ed1e244 100644
--- a/src/mainboard/asus/h61-series/Kconfig
+++ b/src/mainboard/asus/h61-series/Kconfig
@@ -2,7 +2,6 @@
 
 config BOARD_ASUS_H61_SERIES
 	bool
-	select AZALIA_USE_LEGACY_VERB_TABLE
 	select HAVE_ACPI_RESUME
 	select HAVE_ACPI_TABLES
 	select INTEL_GMA_HAVE_VBT
diff --git a/src/mainboard/asus/h61-series/variants/h61m-a_usb3/hda_verb.c b/src/mainboard/asus/h61-series/variants/h61m-a_usb3/hda_verb.c
index b9177d0f5a..df1fb43b95 100644
--- a/src/mainboard/asus/h61-series/variants/h61m-a_usb3/hda_verb.c
+++ b/src/mainboard/asus/h61-series/variants/h61m-a_usb3/hda_verb.c
@@ -3,10 +3,7 @@
 #include <device/azalia_device.h>
 #include <device/azalia_codec/realtek.h>
 
-const u32 cim_verb_data[] = {
-	0x10ec0887,	/* Codec Vendor / Device ID: Realtek */
-	0x10438445,	/* Subsystem ID */
-	15,		/* Number of 4 dword sets */
+static const u32 realtek_alc887_verbs[] = {
 	AZALIA_SUBVENDOR(0, 0x10438445),
 	AZALIA_PIN_CFG(0, ALC887_SPDIF_OUT2, 0x40330000),
 	AZALIA_PIN_CFG(0, ALC887_DMIC_LR, AZALIA_PIN_CFG_NC(0)),
@@ -22,10 +19,9 @@ const u32 cim_verb_data[] = {
 	AZALIA_PIN_CFG(0, ALC887_PC_BEEP, 0x4024c601),
 	AZALIA_PIN_CFG(0, ALC887_SPDIF_OUT1, AZALIA_PIN_CFG_NC(0)),
 	AZALIA_PIN_CFG(0, ALC887_SPDIF_IN, AZALIA_PIN_CFG_NC(0)),
+};
 
-	0x8086281c,	/* Codec Vendor / Device ID: Intel */
-	0x80860101,	/* Subsystem ID */
-	10,		/* Number of 4 dword sets */
+static const u32 intel_display_audio_1_verbs[] = {
 	AZALIA_SUBVENDOR(2, 0x80860101),
 	AZALIA_PIN_CFG(2, 0x04, 0x18560010),
 	AZALIA_PIN_CFG(2, 0x06, 0x18560010),
@@ -36,17 +32,52 @@ const u32 cim_verb_data[] = {
 	AZALIA_PIN_CFG(2, 0x0d, 0x18560010),
 	AZALIA_PIN_CFG(2, 0x0e, 0x18560010),
 	AZALIA_PIN_CFG(2, 0x0f, 0x18560010),
+};
 
-	0x80862805,	/* Codec Vendor / Device ID: Intel */
-	0x80860101,	/* Subsystem ID */
-	4,		/* Number of 4 dword sets */
+static const u32 intel_display_audio_2_verbs[] = {
 	AZALIA_SUBVENDOR(3, 0x80860101),
 	AZALIA_PIN_CFG(3, 0x05, 0x58560010),
 	AZALIA_PIN_CFG(3, 0x06, 0x58560020),
 	AZALIA_PIN_CFG(3, 0x07, 0x18560030),
-
 };
 
 const u32 pc_beep_verbs[0] = {};
 
+struct azalia_codec mainboard_azalia_codecs[] = {
+	{
+		.name         = "Realtek ALC887",
+		.vendor_id    = 0x10ec0887,
+		.subsystem_id = 0x10438445,
+		.address      = 0,
+		.verbs        = realtek_alc887_verbs,
+		.verb_count   = ARRAY_SIZE(realtek_alc887_verbs),
+	},
+	{
+		/*
+		 * TODO: This seems out of place, the vendor ID suggests this
+		 * codec is an Alder Lake P Intel Display Audio[1], and
+		 * the user manual[2] does not mention this codec. Could someone
+		 * with this board confirm what this is?
+		 *
+		 * [1] Linux kernel: sound/hda/codecs/hdmi/intelhdmi.c:789
+		 * [2] H61M-A/USB3 User's Manual (English), Version E8184
+		 */
+		.name         = "Intel Display Audio #1 (HDMI/DP)",
+		.vendor_id    = 0x8086281c,
+		.subsystem_id = 0x80860101,
+		.address      = 2,
+		.verbs        = intel_display_audio_1_verbs,
+		.verb_count   = ARRAY_SIZE(intel_display_audio_1_verbs),
+	},
+	{
+		.name         = "Intel Display Audio #2 (HDMI/DP)",
+		.vendor_id    = 0x80862805,
+		.subsystem_id = 0x80860101,
+		.address      = 3,
+		.verbs        = intel_display_audio_2_verbs,
+		.verb_count   = ARRAY_SIZE(intel_display_audio_2_verbs),
+	},
+	{ /* terminator */ }
+};
+
 AZALIA_ARRAY_SIZES;
diff --git a/src/mainboard/asus/h61-series/variants/h61m-cs/hda_verb.c b/src/mainboard/asus/h61-series/variants/h61m-cs/hda_verb.c
index 956a716c76..c2226c5d4b 100644
--- a/src/mainboard/asus/h61-series/variants/h61m-cs/hda_verb.c
+++ b/src/mainboard/asus/h61-series/variants/h61m-cs/hda_verb.c
@@ -4,10 +4,7 @@
 #include <device/azalia_device.h>
 #include <device/azalia_codec/realtek.h>
 
-const u32 cim_verb_data[] = {
-	0x10ec0887,	/* Codec Vendor / Device ID: Realtek */
-	0x10438445,	/* Subsystem ID */
-	15,		/* Number of 4 dword sets */
+static const u32 realtek_alc887_verbs[] = {
 	AZALIA_SUBVENDOR(0, 0x10438445),
 	AZALIA_PIN_CFG(0, ALC887_SPDIF_OUT2, 0x40330000),
 	AZALIA_PIN_CFG(0, ALC887_DMIC_LR, AZALIA_PIN_CFG_NC(0)),
@@ -27,4 +24,16 @@ const u32 cim_verb_data[] = {
 
 const u32 pc_beep_verbs[0] = {};
 
+struct azalia_codec mainboard_azalia_codecs[] = {
+	{
+		.name         = "Realtek ALC887",
+		.vendor_id    = 0x10ec0887,
+		.subsystem_id = 0x10438445,
+		.address      = 0,
+		.verbs        = realtek_alc887_verbs,
+		.verb_count   = ARRAY_SIZE(realtek_alc887_verbs),
+	},
+	{ /* terminator */ }
+};
+
 AZALIA_ARRAY_SIZES;
diff --git a/src/mainboard/asus/h61-series/variants/p8h61-m_lx/hda_verb.c b/src/mainboard/asus/h61-series/variants/p8h61-m_lx/hda_verb.c
index 5647a31c96..b351ed58b3 100644
--- a/src/mainboard/asus/h61-series/variants/p8h61-m_lx/hda_verb.c
+++ b/src/mainboard/asus/h61-series/variants/p8h61-m_lx/hda_verb.c
@@ -4,10 +4,7 @@
 #include <device/azalia_device.h>
 #include <device/azalia_codec/realtek.h>
 
-const u32 cim_verb_data[] = {
-	0x10ec0887,	/* Realtek ALC887-VD */
-	0x10438445,	/* Subsystem ID */
-	15,		/* Number of entries */
+static const u32 realtek_alc887_vd_verbs[] = {
 	AZALIA_SUBVENDOR(0, 0x10438445),
 	AZALIA_PIN_CFG(0, ALC887_SPDIF_OUT2, 0x99430130),
 	AZALIA_PIN_CFG(0, ALC887_DMIC_LR, AZALIA_PIN_CFG_NC(0)),
@@ -27,4 +24,16 @@ const u32 cim_verb_data[] = {
 
 const u32 pc_beep_verbs[] = {};
 
+struct azalia_codec mainboard_azalia_codecs[] = {
+	{
+		.name         = "Realtek ALC887-VD",
+		.vendor_id    = 0x10ec0887,
+		.subsystem_id = 0x10438445,
+		.address      = 0,
+		.verbs        = realtek_alc887_vd_verbs,
+		.verb_count   = ARRAY_SIZE(realtek_alc887_vd_verbs),
+	},
+	{ /* terminator */ }
+};
+
 AZALIA_ARRAY_SIZES;
diff --git a/src/mainboard/asus/h61-series/variants/p8h61-m_lx3_r2_0/hda_verb.c b/src/mainboard/asus/h61-series/variants/p8h61-m_lx3_r2_0/hda_verb.c
index 7988e2b4ad..ef63e3e9d1 100644
--- a/src/mainboard/asus/h61-series/variants/p8h61-m_lx3_r2_0/hda_verb.c
+++ b/src/mainboard/asus/h61-series/variants/p8h61-m_lx3_r2_0/hda_verb.c
@@ -2,10 +2,7 @@
 
 #include <device/azalia_device.h>
 
-const u32 cim_verb_data[] = {
-	0x11060397,	/* Codec Vendor / Device ID: VIA VT1708S */
-	0x10438415,	/* Subsystem ID */
-	12,		/* Number of 4 dword sets */
+static const u32 via_vt1708s_verbs[] = {
 	AZALIA_SUBVENDOR(0, 0x10438415),
 	AZALIA_PIN_CFG(0, 0x19, 0x410110f0),
 	AZALIA_PIN_CFG(0, 0x1a, 0x01a19036),
@@ -22,4 +19,16 @@ const u32 cim_verb_data[] = {
 
 const u32 pc_beep_verbs[0] = {};
 
+struct azalia_codec mainboard_azalia_codecs[] = {
+	{
+		.name         = "VIA VT1708S",
+		.vendor_id    = 0x11060397,
+		.subsystem_id = 0x10438415,
+		.address      = 0,
+		.verbs        = via_vt1708s_verbs,
+		.verb_count   = ARRAY_SIZE(via_vt1708s_verbs),
+	},
+	{ /* terminator */ }
+};
+
 AZALIA_ARRAY_SIZES;
diff --git a/src/mainboard/asus/h61-series/variants/p8h61-m_pro/hda_verb.c b/src/mainboard/asus/h61-series/variants/p8h61-m_pro/hda_verb.c
index e29bdcae14..ee94e3368e 100644
--- a/src/mainboard/asus/h61-series/variants/p8h61-m_pro/hda_verb.c
+++ b/src/mainboard/asus/h61-series/variants/p8h61-m_pro/hda_verb.c
@@ -3,10 +3,7 @@
 #include <device/azalia_device.h>
 #include <device/azalia_codec/realtek.h>
 
-const u32 cim_verb_data[] = {
-	0x10ec0887,	/* Codec Vendor / Device ID: Realtek */
-	0x10438444,	/* Subsystem ID */
-	15,		/* Number of 4 dword sets */
+static const u32 realtek_alc887_vd_verbs[] = {
 	AZALIA_SUBVENDOR(0, 0x10438444),
 	AZALIA_PIN_CFG(0, ALC887_SPDIF_OUT2, 0x99430140),
 	AZALIA_PIN_CFG(0, ALC887_DMIC_LR, AZALIA_PIN_CFG_NC(0)),
@@ -22,10 +19,9 @@ const u32 cim_verb_data[] = {
 	AZALIA_PIN_CFG(0, ALC887_PC_BEEP, 0x4005e601),
 	AZALIA_PIN_CFG(0, ALC887_SPDIF_OUT1, 0x01456130),
 	AZALIA_PIN_CFG(0, ALC887_SPDIF_IN, AZALIA_PIN_CFG_NC(0)),
+};
 
-	0x80862805,	/* Codec Vendor / Device ID: Intel */
-	0x80860101,	/* Subsystem ID */
-	4,		/* Number of 4 dword sets */
+static const u32 intel_display_audio_verbs[] = {
 	AZALIA_SUBVENDOR(3, 0x80860101),
 	AZALIA_PIN_CFG(3, 0x05, 0x58560010),
 	AZALIA_PIN_CFG(3, 0x06, 0x58560020),
@@ -34,4 +30,24 @@ const u32 cim_verb_data[] = {
 
 const u32 pc_beep_verbs[0] = {};
 
+struct azalia_codec mainboard_azalia_codecs[] = {
+	{
+		.name         = "Realtek ALC887-VD",
+		.vendor_id    = 0x10ec0887,
+		.subsystem_id = 0x10438444,
+		.address      = 0,
+		.verbs        = realtek_alc887_vd_verbs,
+		.verb_count   = ARRAY_SIZE(realtek_alc887_vd_verbs),
+	},
+	{
+		.name         = "Intel Display Audio (HDMI/DP)",
+		.vendor_id    = 0x80862805,
+		.subsystem_id = 0x80860101,
+		.address      = 3,
+		.verbs        = intel_display_audio_verbs,
+		.verb_count   = ARRAY_SIZE(intel_display_audio_verbs),
+	},
+	{ /* terminator */ }
+};
+
 AZALIA_ARRAY_SIZES;
diff --git a/src/mainboard/asus/h61-series/variants/p8h61-m_pro_cm6630/hda_verb.c b/src/mainboard/asus/h61-series/variants/p8h61-m_pro_cm6630/hda_verb.c
index 0aa95d00a3..7018c22ece 100644
--- a/src/mainboard/asus/h61-series/variants/p8h61-m_pro_cm6630/hda_verb.c
+++ b/src/mainboard/asus/h61-series/variants/p8h61-m_pro_cm6630/hda_verb.c
@@ -3,10 +3,7 @@
 #include <device/azalia_device.h>
 #include <device/azalia_codec/realtek.h>
 
-const u32 cim_verb_data[] = {
-	0x10ec0887,	/* Codec Vendor / Device ID: Realtek ALC887 */
-	0x10438444,	/* Subsystem ID */
-	15,		/* Number of 4 dword sets */
+static const u32 realtek_alc887_verbs[] = {
 	AZALIA_SUBVENDOR(0, 0x10438444),
 	AZALIA_PIN_CFG(0, ALC887_SPDIF_OUT2, 0x99430140),
 	AZALIA_PIN_CFG(0, ALC887_DMIC_LR, AZALIA_PIN_CFG_NC(0)),
@@ -22,10 +19,9 @@ const u32 cim_verb_data[] = {
 	AZALIA_PIN_CFG(0, ALC887_PC_BEEP, 0x4005e601),
 	AZALIA_PIN_CFG(0, ALC887_SPDIF_OUT1, 0x01456130),
 	AZALIA_PIN_CFG(0, ALC887_SPDIF_IN, AZALIA_PIN_CFG_NC(0)),
+};
 
-	0x80862805,	/* Codec Vendor / Device ID: Intel HDMI */
-	0x80860101,	/* Subsystem ID */
-	4,		/* Number of 4 dword sets */
+static const u32 intel_display_audio_verbs[] = {
 	AZALIA_SUBVENDOR(3, 0x80860101),
 	AZALIA_PIN_CFG(3, 0x05, 0x58560010),
 	AZALIA_PIN_CFG(3, 0x06, 0x58560020),
@@ -34,4 +30,24 @@ const u32 cim_verb_data[] = {
 
 const u32 pc_beep_verbs[0] = {};
 
+struct azalia_codec mainboard_azalia_codecs[] = {
+	{
+		.name         = "Realtek ALC887",
+		.vendor_id    = 0x10ec0887,
+		.subsystem_id = 0x10438444,
+		.address      = 0,
+		.verbs        = realtek_alc887_verbs,
+		.verb_count   = ARRAY_SIZE(realtek_alc887_verbs),
+	},
+	{
+		.name         = "Intel Display Audio (HDMI/DP)",
+		.vendor_id    = 0x80862805,
+		.subsystem_id = 0x80860101,
+		.address      = 3,
+		.verbs        = intel_display_audio_verbs,
+		.verb_count   = ARRAY_SIZE(intel_display_audio_verbs),
+	},
+	{ /* terminator */ }
+};
+
 AZALIA_ARRAY_SIZES;
diff --git a/src/mainboard/asus/h61-series/variants/p8h67-i_deluxe/hda_verb.c b/src/mainboard/asus/h61-series/variants/p8h67-i_deluxe/hda_verb.c
index 993767bcb7..7548c3addb 100644
--- a/src/mainboard/asus/h61-series/variants/p8h67-i_deluxe/hda_verb.c
+++ b/src/mainboard/asus/h61-series/variants/p8h67-i_deluxe/hda_verb.c
@@ -2,10 +2,7 @@
 
 #include <device/azalia_device.h>
 
-const u32 cim_verb_data[] = {
-	0x10ec0892,	/* Codec Vendor / Device ID: Realtek */
-	0x1043848d,	/* Subsystem ID */
-	15,		/* Number of 4 dword sets */
+static const u32 realtek_alc892_verbs[] = {
 	AZALIA_SUBVENDOR(0, 0x1043848d),
 	AZALIA_PIN_CFG(0, 0x11, 0x99430140),
 	AZALIA_PIN_CFG(0, 0x12, AZALIA_PIN_CFG_NC(0)),
@@ -21,10 +18,9 @@ const u32 cim_verb_data[] = {
 	AZALIA_PIN_CFG(0, 0x1d, 0x4004c601),
 	AZALIA_PIN_CFG(0, 0x1e, 0x01452130),
 	AZALIA_PIN_CFG(0, 0x1f, AZALIA_PIN_CFG_NC(0)),
+};
 
-	0x80862805,	/* Codec Vendor / Device ID: Intel */
-	0x80862805,	/* Subsystem ID */
-	4,		/* Number of 4 dword sets */
+static const u32 intel_display_audio_verbs[] = {
 	AZALIA_SUBVENDOR(3, 0x80862805),
 	AZALIA_PIN_CFG(3, 0x05, 0x58560010),
 	AZALIA_PIN_CFG(3, 0x06, 0x58560020),
@@ -34,4 +30,24 @@ const u32 cim_verb_data[] = {
 
 const u32 pc_beep_verbs[0] = {};
 
+struct azalia_codec mainboard_azalia_codecs[] = {
+	{
+		.name         = "Realtek ALC892",
+		.vendor_id    = 0x10ec0892,
+		.subsystem_id = 0x1043848d,
+		.address      = 0,
+		.verbs        = realtek_alc892_verbs,
+		.verb_count   = ARRAY_SIZE(realtek_alc892_verbs),
+	},
+	{
+		.name         = "Intel Display Audio (HDMI/DP)",
+		.vendor_id    = 0x80862805,
+		.subsystem_id = 0x80862805,
+		.address      = 3,
+		.verbs        = intel_display_audio_verbs,
+		.verb_count   = ARRAY_SIZE(intel_display_audio_verbs),
+	},
+	{ /* terminator */ }
+};
+
 AZALIA_ARRAY_SIZES;
diff --git a/src/mainboard/asus/h610i-plus-d4/Kconfig b/src/mainboard/asus/h610i-plus-d4/Kconfig
index 5d76d2b508..e4f7598066 100644
--- a/src/mainboard/asus/h610i-plus-d4/Kconfig
+++ b/src/mainboard/asus/h610i-plus-d4/Kconfig
@@ -1,7 +1,6 @@
 ## SPDX-License-Identifier: GPL-2.0-only
 
 config BOARD_ASUS_H610I_PLUS_D4
-	select AZALIA_USE_LEGACY_VERB_TABLE
 	select BOARD_ROMSIZE_KB_16384
 	select DRIVERS_UART_8250IO
 	select HAVE_ACPI_RESUME
diff --git a/src/mainboard/asus/h610i-plus-d4/hda_verb.c b/src/mainboard/asus/h610i-plus-d4/hda_verb.c
index 173845d32e..685e8fcd8b 100644
--- a/src/mainboard/asus/h610i-plus-d4/hda_verb.c
+++ b/src/mainboard/asus/h610i-plus-d4/hda_verb.c
@@ -2,10 +2,7 @@
 
 #include <device/azalia_device.h>
 
-const u32 cim_verb_data[] = {
-	0x10ec0897, // Vendor/Device ID: Realtek ALC897
-	0x10438803, // Subsystem ID
-	15,
+static const u32 realtek_alc897_verbs[] = {
 	AZALIA_SUBVENDOR(0, 0x10438803),
 
 	AZALIA_PIN_CFG(0, 0x11, AZALIA_PIN_CFG_NC(0)),
@@ -70,10 +67,9 @@ const u32 cim_verb_data[] = {
 	AZALIA_PIN_CFG(0, 0x1d, 0x4048ee29), // does not describe a jack or internal device
 	AZALIA_PIN_CFG(0, 0x1e, AZALIA_PIN_CFG_NC(0)),
 	AZALIA_PIN_CFG(0, 0x1f, AZALIA_PIN_CFG_NC(0)),
+};
 
-	0x80862815, // Vendor/Device ID: Intel Alderlake HDMI
-	0x80860101, // Subsystem ID
-	10,
+static const u32 intel_display_audio_verbs[] = {
 	AZALIA_SUBVENDOR(2, 0x80860101),
 
 	AZALIA_PIN_CFG(2, 0x04, AZALIA_PIN_DESC(
@@ -160,4 +156,25 @@ const u32 cim_verb_data[] = {
 };
 
 const u32 pc_beep_verbs[] = {};
+
+struct azalia_codec mainboard_azalia_codecs[] = {
+	{
+		.name         = "Realtek ALC897",
+		.vendor_id    = 0x10ec0897,
+		.subsystem_id = 0x10438803,
+		.address      = 0,
+		.verbs        = realtek_alc897_verbs,
+		.verb_count   = ARRAY_SIZE(realtek_alc897_verbs),
+	},
+	{
+		.name         = "Intel Display Audio (HDMI/DP)",
+		.vendor_id    = 0x80862815,
+		.subsystem_id = 0x80860101,
+		.address      = 2,
+		.verbs        = intel_display_audio_verbs,
+		.verb_count   = ARRAY_SIZE(intel_display_audio_verbs),
+	},
+	{ /* terminator */ }
+};
+
 AZALIA_ARRAY_SIZES;
diff --git a/src/mainboard/asus/maximus_iv_gene-z/Kconfig b/src/mainboard/asus/maximus_iv_gene-z/Kconfig
index 97a531fd3c..b3b081c43b 100644
--- a/src/mainboard/asus/maximus_iv_gene-z/Kconfig
+++ b/src/mainboard/asus/maximus_iv_gene-z/Kconfig
@@ -4,7 +4,6 @@ if BOARD_ASUS_MAXIMUS_IV_GENE_Z
 
 config BOARD_SPECIFIC_OPTIONS
 	def_bool y
-	select AZALIA_USE_LEGACY_VERB_TABLE
 	select BOARD_ROMSIZE_KB_8192
 	select HAVE_ACPI_RESUME
 	select HAVE_ACPI_TABLES
diff --git a/src/mainboard/asus/maximus_iv_gene-z/hda_verb.c b/src/mainboard/asus/maximus_iv_gene-z/hda_verb.c
index 11a14a2f3f..fd2abc36bd 100644
--- a/src/mainboard/asus/maximus_iv_gene-z/hda_verb.c
+++ b/src/mainboard/asus/maximus_iv_gene-z/hda_verb.c
@@ -3,10 +3,7 @@
 #include <stdint.h>
 #include <device/azalia_device.h>
 
-const u32 cim_verb_data[] = {
-	0x10ec0889,	/* Realtek ALC889 */
-	0x10ec0889,	/* Subsystem ID */
-	15,		/* Number of entries */
+static const u32 realtek_alc889_verbs[] = {
 	AZALIA_SUBVENDOR(0, 0x10ec0889),
 	AZALIA_PIN_CFG(0, 0x11, 0x414471f0),
 	AZALIA_PIN_CFG(0, 0x12, 0x59a3112e),
@@ -22,10 +19,9 @@ const u32 cim_verb_data[] = {
 	AZALIA_PIN_CFG(0, 0x1d, 0x59f00190),
 	AZALIA_PIN_CFG(0, 0x1e, 0x014471f0),
 	AZALIA_PIN_CFG(0, 0x1f, 0x41c451f0),
+};
 
-	0x80862805,	/* Intel CougarPoint HDMI */
-	0x80860101,	/* Subsystem ID */
-	4,		/* Number of entries */
+static const u32 intel_display_audio_verbs[] = {
 	AZALIA_SUBVENDOR(3, 0x80860101),
 	AZALIA_PIN_CFG(3, 0x05, 0x18560010),
 	AZALIA_PIN_CFG(3, 0x06, 0x18560010),
@@ -34,4 +30,24 @@ const u32 cim_verb_data[] = {
 
 const u32 pc_beep_verbs[] = {};
 
+struct azalia_codec mainboard_azalia_codecs[] = {
+	{
+		.name         = "Realtek ALC889",
+		.vendor_id    = 0x10ec0889,
+		.subsystem_id = 0x10ec0889,
+		.address      = 0,
+		.verbs        = realtek_alc889_verbs,
+		.verb_count   = ARRAY_SIZE(realtek_alc889_verbs),
+	},
+	{
+		.name         = "Intel Display Audio (HDMI/DP)",
+		.vendor_id    = 0x80862805,
+		.subsystem_id = 0x80860101,
+		.address      = 3,
+		.verbs        = intel_display_audio_verbs,
+		.verb_count   = ARRAY_SIZE(intel_display_audio_verbs),
+	},
+	{ /* terminator */ }
+};
+
 AZALIA_ARRAY_SIZES;
diff --git a/src/mainboard/asus/p5gc-mx/Kconfig b/src/mainboard/asus/p5gc-mx/Kconfig
index 7fc801cc65..4f49dbbaa5 100644
--- a/src/mainboard/asus/p5gc-mx/Kconfig
+++ b/src/mainboard/asus/p5gc-mx/Kconfig
@@ -4,7 +4,6 @@ if BOARD_ASUS_P5GC_MX
 
 config BOARD_SPECIFIC_OPTIONS
 	def_bool y
-	select AZALIA_USE_LEGACY_VERB_TABLE
 	select CPU_INTEL_SOCKET_LGA775
 	select NORTHBRIDGE_INTEL_I945
 	select NORTHBRIDGE_INTEL_SUBTYPE_I945GC
diff --git a/src/mainboard/asus/p5gc-mx/hda_verb.c b/src/mainboard/asus/p5gc-mx/hda_verb.c
index 9da73841b9..b7901a2b9a 100644
--- a/src/mainboard/asus/p5gc-mx/hda_verb.c
+++ b/src/mainboard/asus/p5gc-mx/hda_verb.c
@@ -2,13 +2,7 @@
 
 #include <device/azalia_device.h>
 
-const u32 cim_verb_data[] = {
-	/* coreboot specific header */
-	0x10ec0883,	/* Vendor ID */
-	0x104382c7,	/* Subsystem ID */
-	0x0000000c,	/* Number of entries */
-
-	/* Pin Widget Verb Table */
+static const u32 realtek_alc662_verbs[] = {
 	AZALIA_PIN_CFG(0, 0x14, 0x01014010),
 	AZALIA_PIN_CFG(0, 0x15, AZALIA_PIN_CFG_NC(0)),
 	AZALIA_PIN_CFG(0, 0x16, AZALIA_PIN_CFG_NC(0)),
@@ -24,4 +18,17 @@ const u32 cim_verb_data[] = {
 };
 
 const u32 pc_beep_verbs[0] = {};
+
+struct azalia_codec mainboard_azalia_codecs[] = {
+	{
+		.name         = "Realtek ALC662",
+		.vendor_id    = 0x10ec0883,
+		.subsystem_id = 0x104382c7,
+		.address      = 0,
+		.verbs        = realtek_alc662_verbs,
+		.verb_count   = ARRAY_SIZE(realtek_alc662_verbs),
+	},
+	{ /* terminator */ }
+};
+
 AZALIA_ARRAY_SIZES;
diff --git a/src/mainboard/asus/p5qc/Kconfig b/src/mainboard/asus/p5qc/Kconfig
index d5a2e6ecbd..c501b7a010 100644
--- a/src/mainboard/asus/p5qc/Kconfig
+++ b/src/mainboard/asus/p5qc/Kconfig
@@ -4,7 +4,6 @@ if BOARD_ASUS_P5QC || BOARD_ASUS_P5Q_PRO || BOARD_ASUS_P5QL_PRO || BOARD_ASUS_P5
 
 config BOARD_SPECIFIC_OPTIONS
 	def_bool y
-	select AZALIA_USE_LEGACY_VERB_TABLE
 	select CPU_INTEL_SOCKET_LGA775
 	select NORTHBRIDGE_INTEL_X4X
 	select SOUTHBRIDGE_INTEL_I82801JX
diff --git a/src/mainboard/asus/p5qc/hda_verb.c b/src/mainboard/asus/p5qc/hda_verb.c
index 9fc478fcf1..ce6cc0e0c7 100644
--- a/src/mainboard/asus/p5qc/hda_verb.c
+++ b/src/mainboard/asus/p5qc/hda_verb.c
@@ -2,14 +2,7 @@
 
 #include <device/azalia_device.h>
 
-const u32 cim_verb_data[] = {
-	/* coreboot specific header */
-	0x10ec0888,
-	0x104382fe,	// Subsystem ID
-	13,	// Number of entries
-
-	/* Pin Widget Verb Table */
-
+static const u32 realtek_alc1200_verbs[] = {
 	AZALIA_PIN_CFG(0, 0x11, 0x99430140),
 	AZALIA_PIN_CFG(0, 0x14, 0x01014010),
 	AZALIA_PIN_CFG(0, 0x15, 0x01011012),
@@ -27,4 +20,16 @@ const u32 cim_verb_data[] = {
 
 const u32 pc_beep_verbs[0] = {};
 
+struct azalia_codec mainboard_azalia_codecs[] = {
+	{
+		.name         = "Realtek ALC1200",
+		.vendor_id    = 0x10ec0888,
+		.subsystem_id = 0x104382fe,
+		.address      = 0,
+		.verbs        = realtek_alc1200_verbs,
+		.verb_count   = ARRAY_SIZE(realtek_alc1200_verbs),
+	},
+	{ /* terminator */ }
+};
+
 AZALIA_ARRAY_SIZES;
diff --git a/src/mainboard/asus/p5ql-em/Kconfig b/src/mainboard/asus/p5ql-em/Kconfig
index f297d2974d..52ad800940 100644
--- a/src/mainboard/asus/p5ql-em/Kconfig
+++ b/src/mainboard/asus/p5ql-em/Kconfig
@@ -4,7 +4,6 @@ if BOARD_ASUS_P5QL_EM
 
 config BOARD_SPECIFIC_OPTIONS
 	def_bool y
-	select AZALIA_USE_LEGACY_VERB_TABLE
 	select CPU_INTEL_SOCKET_LGA775
 	select NORTHBRIDGE_INTEL_X4X
 	select SOUTHBRIDGE_INTEL_I82801JX
diff --git a/src/mainboard/asus/p5ql-em/hda_verb.c b/src/mainboard/asus/p5ql-em/hda_verb.c
index 861b659527..8b80ae9e5f 100644
--- a/src/mainboard/asus/p5ql-em/hda_verb.c
+++ b/src/mainboard/asus/p5ql-em/hda_verb.c
@@ -2,13 +2,7 @@
 
 #include <device/azalia_device.h>
 
-const u32 cim_verb_data[] = {
-	/* coreboot specific header */
-	0x10ec0888,
-	0x104382fe,	// Subsystem ID
-	13,	// Number of entries
-
-	/* Pin Widget Verb Table */
+static const u32 realtek_alc1200_verbs[] = {
 	AZALIA_PIN_CFG(0, 0x11, 0x99430130),
 	AZALIA_PIN_CFG(0, 0x14, 0x01014010),
 	AZALIA_PIN_CFG(0, 0x15, 0x01011012),
@@ -22,15 +16,32 @@ const u32 cim_verb_data[] = {
 	AZALIA_PIN_CFG(0, 0x1d, 0x4015e601),
 	AZALIA_PIN_CFG(0, 0x1e, AZALIA_PIN_CFG_NC(0)),
 	AZALIA_PIN_CFG(0, 0x1f, AZALIA_PIN_CFG_NC(0)),
+};
 
-	/* HDMI audio */
-	0x80862803,
-	0x80860101,
-	1,
-
+static const u32 intel_display_audio_verbs[] = {
 	AZALIA_PIN_CFG(1, 0x03, 0x18560010),
 };
 
 const u32 pc_beep_verbs[0] = {};
 
+struct azalia_codec mainboard_azalia_codecs[] = {
+	{
+		.name         = "Realtek ALC1200",
+		.vendor_id    = 0x10ec0888,
+		.subsystem_id = 0x104382fe,
+		.address      = 0,
+		.verbs        = realtek_alc1200_verbs,
+		.verb_count   = ARRAY_SIZE(realtek_alc1200_verbs),
+	},
+	{
+		.name         = "Intel Display Audio (HDMI/DP)",
+		.vendor_id    = 0x80862803,
+		.subsystem_id = 0x80860101,
+		.address      = 1,
+		.verbs        = intel_display_audio_verbs,
+		.verb_count   = ARRAY_SIZE(intel_display_audio_verbs),
+	},
+	{ /* terminator */ }
+};
+
 AZALIA_ARRAY_SIZES;
diff --git a/src/mainboard/asus/p5qpl-am/Kconfig b/src/mainboard/asus/p5qpl-am/Kconfig
index aeafb4be4f..2359e324d8 100644
--- a/src/mainboard/asus/p5qpl-am/Kconfig
+++ b/src/mainboard/asus/p5qpl-am/Kconfig
@@ -4,7 +4,6 @@ if BOARD_ASUS_P5QPL_AM || BOARD_ASUS_P5G41T_M_LX
 
 config BOARD_SPECIFIC_OPTIONS
 	def_bool y
-	select AZALIA_USE_LEGACY_VERB_TABLE
 	select CPU_INTEL_SOCKET_LGA775
 	select NORTHBRIDGE_INTEL_X4X
 	select SOUTHBRIDGE_INTEL_I82801GX
diff --git a/src/mainboard/asus/p5qpl-am/hda_verb.c b/src/mainboard/asus/p5qpl-am/hda_verb.c
index b49878a9a8..f1413543eb 100644
--- a/src/mainboard/asus/p5qpl-am/hda_verb.c
+++ b/src/mainboard/asus/p5qpl-am/hda_verb.c
@@ -3,15 +3,7 @@
 #include <device/azalia_device.h>
 #include <device/azalia_codec/realtek.h>
 
-const u32 cim_verb_data[] = {
-	/* coreboot specific header */
-	/* Realtek ALC662 rev1 */
-	0x10ec0887, /* Vendor ID */
-	0x1043840b, /* Subsystem ID */
-	14, /* Number of entries */
-
-	/* Pin Widget Verb Table */
-
+static const u32 realtek_alc662_verbs[] = {
 	AZALIA_PIN_CFG(0, ALC887_SPDIF_OUT2, AZALIA_PIN_CFG_NC(0)),
 	AZALIA_PIN_CFG(0, ALC887_DMIC_LR, AZALIA_PIN_CFG_NC(0)),
 	AZALIA_PIN_CFG(0, ALC887_FRONT, 0x01014010),
@@ -30,4 +22,16 @@ const u32 cim_verb_data[] = {
 
 const u32 pc_beep_verbs[0] = {};
 
+struct azalia_codec mainboard_azalia_codecs[] = {
+	{
+		.name         = "Realtek ALC662",
+		.vendor_id    = 0x10ec0887,
+		.subsystem_id = 0x1043840b,
+		.address      = 0,
+		.verbs        = realtek_alc662_verbs,
+		.verb_count   = ARRAY_SIZE(realtek_alc662_verbs),
+	},
+	{ /* terminator */ }
+};
+
 AZALIA_ARRAY_SIZES;
diff --git a/src/mainboard/asus/p8x7x-series/Kconfig b/src/mainboard/asus/p8x7x-series/Kconfig
index 6f1632e4be..cfff67a0dc 100644
--- a/src/mainboard/asus/p8x7x-series/Kconfig
+++ b/src/mainboard/asus/p8x7x-series/Kconfig
@@ -2,7 +2,6 @@
 
 config BOARD_ASUS_P8X7X_SERIES
 	bool
-	select AZALIA_USE_LEGACY_VERB_TABLE
 	select HAVE_ACPI_RESUME
 	select HAVE_ACPI_TABLES
 	select HAVE_CMOS_DEFAULT
diff --git a/src/mainboard/asus/p8x7x-series/variants/p8c_ws/hda_verb.c b/src/mainboard/asus/p8x7x-series/variants/p8c_ws/hda_verb.c
index 03430f1c35..7bf810d49b 100644
--- a/src/mainboard/asus/p8x7x-series/variants/p8c_ws/hda_verb.c
+++ b/src/mainboard/asus/p8x7x-series/variants/p8c_ws/hda_verb.c
@@ -2,10 +2,7 @@
 
 #include <device/azalia_device.h>
 
-const u32 cim_verb_data[] = {
-	0x10ec0892,	/* Codec Vendor / Device ID: Realtek ALC892 */
-	0x104384fb,	/* Subsystem ID */
-	15,		/* Number of 4 dword sets */
+static const u32 realtek_alc892_verbs[] = {
 	AZALIA_SUBVENDOR(0, 0x104384fb),
 	AZALIA_PIN_CFG(0, 0x11, 0x99430140),
 	AZALIA_PIN_CFG(0, 0x12, AZALIA_PIN_CFG_NC(0)),
@@ -26,4 +23,16 @@ const u32 cim_verb_data[] = {
 
 const u32 pc_beep_verbs[0] = {};
 
+struct azalia_codec mainboard_azalia_codecs[] = {
+	{
+		.name         = "Realtek ALC892",
+		.vendor_id    = 0x10ec0892,
+		.subsystem_id = 0x104384fb,
+		.address      = 0,
+		.verbs        = realtek_alc892_verbs,
+		.verb_count   = ARRAY_SIZE(realtek_alc892_verbs),
+	},
+	{ /* terminator */ }
+};
+
 AZALIA_ARRAY_SIZES;
diff --git a/src/mainboard/asus/p8x7x-series/variants/p8h77-v/hda_verb.c b/src/mainboard/asus/p8x7x-series/variants/p8h77-v/hda_verb.c
index f246af7018..4a7bf2edb3 100644
--- a/src/mainboard/asus/p8x7x-series/variants/p8h77-v/hda_verb.c
+++ b/src/mainboard/asus/p8x7x-series/variants/p8h77-v/hda_verb.c
@@ -2,10 +2,7 @@
 
 #include <device/azalia_device.h>
 
-const u32 cim_verb_data[] = {
-	0x11060397,	/* Codec Vendor / Device ID: VIA VT1708S */
-	0x1043836c,	/* Subsystem ID */
-	12,		/* Number of 4 dword sets */
+static const u32 via_vt1708s_verbs[] = {
 	AZALIA_SUBVENDOR(0, 0x1043836c),
 	AZALIA_PIN_CFG(0, 0x19, 0x01011012),
 	AZALIA_PIN_CFG(0, 0x1a, 0x01a19036),
@@ -18,10 +15,9 @@ const u32 cim_verb_data[] = {
 	AZALIA_PIN_CFG(0, 0x21, 0x074521f0),
 	AZALIA_PIN_CFG(0, 0x22, 0x01016011),
 	AZALIA_PIN_CFG(0, 0x23, 0x01012014),
+};
 
-	0x80862806,	/* Codec Vendor / Device ID: Intel HDMI */
-	0x80860101,	/* Subsystem ID */
-	4,		/* Number of 4 dword sets */
+static const u32 intel_display_audio_verbs[] = {
 	AZALIA_SUBVENDOR(3, 0x80860101),
 	AZALIA_PIN_CFG(3, 0x05, 0x18560010),
 	AZALIA_PIN_CFG(3, 0x06, 0x58560020),
@@ -31,4 +27,24 @@ const u32 cim_verb_data[] = {
 
 const u32 pc_beep_verbs[0] = {};
 
+struct azalia_codec mainboard_azalia_codecs[] = {
+	{
+		.name         = "VIA VT1708S",
+		.vendor_id    = 0x11060397,
+		.subsystem_id = 0x1043836c,
+		.address      = 0,
+		.verbs        = via_vt1708s_verbs,
+		.verb_count   = ARRAY_SIZE(via_vt1708s_verbs),
+	},
+	{
+		.name         = "Intel Display Audio (HDMI/DP)",
+		.vendor_id    = 0x80862806,
+		.subsystem_id = 0x80860101,
+		.address      = 3,
+		.verbs        = intel_display_audio_verbs,
+		.verb_count   = ARRAY_SIZE(intel_display_audio_verbs),
+	},
+	{ /* terminator */ }
+};
+
 AZALIA_ARRAY_SIZES;
diff --git a/src/mainboard/asus/p8x7x-series/variants/p8z77-m/hda_verb.c b/src/mainboard/asus/p8x7x-series/variants/p8z77-m/hda_verb.c
index 05efa2d5af..25a7a4c87d 100644
--- a/src/mainboard/asus/p8x7x-series/variants/p8z77-m/hda_verb.c
+++ b/src/mainboard/asus/p8x7x-series/variants/p8z77-m/hda_verb.c
@@ -6,10 +6,7 @@
 
 #include <option.h>
 
-const u32 cim_verb_data[] = {
-	0x10ec0887, /* Codec Vendor / Device ID: Realtek */
-	0x104384a8, /* Subsystem ID */
-	15,         /* Number of 4 dword sets */
+static const u32 realtek_alc887_verbs[] = {
 	AZALIA_SUBVENDOR(0, 0x104384a8),
 	AZALIA_PIN_CFG(0, ALC887_SPDIF_OUT2, 0x90430130),
 	AZALIA_PIN_CFG(0, ALC887_DMIC_LR, AZALIA_PIN_CFG_NC(0)),
@@ -25,10 +22,9 @@ const u32 cim_verb_data[] = {
 	AZALIA_PIN_CFG(0, ALC887_PC_BEEP, 0x4016c629),
 	AZALIA_PIN_CFG(0, ALC887_SPDIF_OUT1, 0x01446140),
 	AZALIA_PIN_CFG(0, ALC887_SPDIF_IN, AZALIA_PIN_CFG_NC(0)),
+};
 
-	0x80862806, /* Codec Vendor / Device ID: Intel */
-	0x80860101, /* Subsystem ID */
-	4,          /* Number of 4 dword sets */
+static const u32 intel_display_audio_verbs[] = {
 	AZALIA_SUBVENDOR(3, 0x80860101),
 	AZALIA_PIN_CFG(3, 0x05, 0x58560010),
 	AZALIA_PIN_CFG(3, 0x06, 0x58560020),
@@ -37,6 +33,26 @@ const u32 cim_verb_data[] = {
 
 const u32 pc_beep_verbs[0] = {};
 
+struct azalia_codec mainboard_azalia_codecs[] = {
+	{
+		.name         = "Realtek ALC887",
+		.vendor_id    = 0x10ec0887,
+		.subsystem_id = 0x104384a8,
+		.address      = 0,
+		.verbs        = realtek_alc887_verbs,
+		.verb_count   = ARRAY_SIZE(realtek_alc887_verbs),
+	},
+	{
+		.name         = "Intel Display Audio (HDMI/DP)",
+		.vendor_id    = 0x80862806,
+		.subsystem_id = 0x80860101,
+		.address      = 3,
+		.verbs        = intel_display_audio_verbs,
+		.verb_count   = ARRAY_SIZE(intel_display_audio_verbs),
+	},
+	{ /* terminator */ }
+};
+
 AZALIA_ARRAY_SIZES;
 
 void mainboard_azalia_program_runtime_verbs(u8 *base, u32 viddid)
diff --git a/src/mainboard/asus/p8x7x-series/variants/p8z77-m_pro/hda_verb.c b/src/mainboard/asus/p8x7x-series/variants/p8z77-m_pro/hda_verb.c
index 696134b00a..67b5e930bc 100644
--- a/src/mainboard/asus/p8x7x-series/variants/p8z77-m_pro/hda_verb.c
+++ b/src/mainboard/asus/p8x7x-series/variants/p8z77-m_pro/hda_verb.c
@@ -2,10 +2,7 @@
 
 #include <device/azalia_device.h>
 
-const u32 cim_verb_data[] = {
-	0x10ec0892,	/* Codec Vendor / Device ID: Realtek */
-	0x10438436,	/* Subsystem ID */
-	15,		/* Number of 4 dword sets */
+static const u32 realtek_alc892_verbs[] = {
 	AZALIA_SUBVENDOR(0, 0x10438436),
 	AZALIA_PIN_CFG(0, 0x11, 0x99430140),
 	AZALIA_PIN_CFG(0, 0x12, AZALIA_PIN_CFG_NC(0)),
@@ -21,10 +18,9 @@ const u32 cim_verb_data[] = {
 	AZALIA_PIN_CFG(0, 0x1d, 0x4005e601),
 	AZALIA_PIN_CFG(0, 0x1e, 0x01456130),
 	AZALIA_PIN_CFG(0, 0x1f, AZALIA_PIN_CFG_NC(0)),
+};
 
-	0x80862806,	/* Codec Vendor / Device ID: Intel */
-	0x80860101,	/* Subsystem ID */
-	4,		/* Number of 4 dword sets */
+static const u32 intel_display_audio_verbs[] = {
 	AZALIA_SUBVENDOR(3, 0x80860101),
 	AZALIA_PIN_CFG(3, 0x05, 0x58560010),
 	AZALIA_PIN_CFG(3, 0x06, 0x58560020),
@@ -33,4 +29,24 @@ const u32 cim_verb_data[] = {
 
 const u32 pc_beep_verbs[0] = {};
 
+struct azalia_codec mainboard_azalia_codecs[] = {
+	{
+		.name         = "Realtek ALC892",
+		.vendor_id    = 0x10ec0892,
+		.subsystem_id = 0x10438436,
+		.address      = 0,
+		.verbs        = realtek_alc892_verbs,
+		.verb_count   = ARRAY_SIZE(realtek_alc892_verbs),
+	},
+	{
+		.name         = "Intel Display Audio (HDMI/DP)",
+		.vendor_id    = 0x80862806,
+		.subsystem_id = 0x80860101,
+		.address      = 3,
+		.verbs        = intel_display_audio_verbs,
+		.verb_count   = ARRAY_SIZE(intel_display_audio_verbs),
+	},
+	{ /* terminator */ }
+};
+
 AZALIA_ARRAY_SIZES;
diff --git a/src/mainboard/asus/p8x7x-series/variants/p8z77-v/hda_verb.c b/src/mainboard/asus/p8x7x-series/variants/p8z77-v/hda_verb.c
index efbf7bf979..89368c70b3 100644
--- a/src/mainboard/asus/p8x7x-series/variants/p8z77-v/hda_verb.c
+++ b/src/mainboard/asus/p8x7x-series/variants/p8z77-v/hda_verb.c
@@ -2,10 +2,7 @@
 
 #include <device/azalia_device.h>
 
-const u32 cim_verb_data[] = {
-	0x10ec0892,	/* Codec Vendor / Device ID: Realtek ALC892 */
-	0x104384fb,	/* Subsystem ID */
-	15,		/* Number of 4 dword sets */
+static const u32 realtek_alc892_verbs[] = {
 	AZALIA_SUBVENDOR(0, 0x104384fb),
 	AZALIA_PIN_CFG(0, 0x11, 0x99430140),
 	AZALIA_PIN_CFG(0, 0x12, AZALIA_PIN_CFG_NC(0)),
@@ -21,17 +18,35 @@ const u32 cim_verb_data[] = {
 	AZALIA_PIN_CFG(0, 0x1d, 0x4005e601),
 	AZALIA_PIN_CFG(0, 0x1e, 0x01456130),
 	AZALIA_PIN_CFG(0, 0x1f, AZALIA_PIN_CFG_NC(0)),
+};
 
-	0x80862806,	/* Codec Vendor / Device ID: Intel HDMI */
-	0x80860101,	/* Subsystem ID */
-	4,		/* Number of 4 dword sets */
+static const u32 intel_display_audio_verbs[] = {
 	AZALIA_SUBVENDOR(3, 0x80860101),
 	AZALIA_PIN_CFG(3, 0x05, 0x58560010),
 	AZALIA_PIN_CFG(3, 0x06, 0x18560020),
 	AZALIA_PIN_CFG(3, 0x07, 0x18560030),
-
 };
 
 const u32 pc_beep_verbs[0] = {};
 
+struct azalia_codec mainboard_azalia_codecs[] = {
+	{
+		.name         = "Realtek ALC892",
+		.vendor_id    = 0x10ec0892,
+		.subsystem_id = 0x104384fb,
+		.address      = 0,
+		.verbs        = realtek_alc892_verbs,
+		.verb_count   = ARRAY_SIZE(realtek_alc892_verbs),
+	},
+	{
+		.name         = "Intel Display Audio (HDMI/DP)",
+		.vendor_id    = 0x80862806,
+		.subsystem_id = 0x80860101,
+		.address      = 3,
+		.verbs        = intel_display_audio_verbs,
+		.verb_count   = ARRAY_SIZE(intel_display_audio_verbs),
+	},
+	{ /* terminator */ }
+};
+
 AZALIA_ARRAY_SIZES;
diff --git a/src/mainboard/asus/p8x7x-series/variants/p8z77-v_le_plus/hda_verb.c b/src/mainboard/asus/p8x7x-series/variants/p8z77-v_le_plus/hda_verb.c
index 5bfa977a98..39e12286d8 100644
--- a/src/mainboard/asus/p8x7x-series/variants/p8z77-v_le_plus/hda_verb.c
+++ b/src/mainboard/asus/p8x7x-series/variants/p8z77-v_le_plus/hda_verb.c
@@ -11,10 +11,7 @@ AZALIA_PIN_DESC(AZALIA_JACK, AZALIA_REAR, dev, AZALIA_STEREO_MONO_1_8, \
 AZALIA_PIN_DESC(AZALIA_JACK, AZALIA_FRONT, dev, AZALIA_STEREO_MONO_1_8, \
 		color, misc, association, sequence)
 
-const u32 cim_verb_data[] = {
-	0x10ec0889,	/* Realtek ALC889 */
-	0x1043841a,	/* Subsystem ID */
-	15,		/* Number of 4 dword sets */
+static const u32 realtek_alc889_verbs[] = {
 	AZALIA_SUBVENDOR(0, 0x1043841a),
 	AZALIA_PIN_CFG(0, 0x11, AZALIA_PIN_DESC(
 				AZALIA_INTEGRATED,
@@ -76,19 +73,37 @@ const u32 cim_verb_data[] = {
 				AZALIA_NO_JACK_PRESENCE_DETECT,
 				4, 0)), /* 0x01456140 */
 	AZALIA_PIN_CFG(0, 0x1f, AZALIA_PIN_CFG_NC(0)),
+};
 
-	0x80862806,	/* Intel */
-	0x80860101,	/* Subsystem ID */
-	4,		/* Number of 4 dword sets */
+static const u32 intel_display_audio_verbs[] = {
 	AZALIA_SUBVENDOR(3, 0x80860101),
 	AZALIA_PIN_CFG(3, 0x05, 0x18560010),
 	AZALIA_PIN_CFG(3, 0x06, 0x58560020),
 	AZALIA_PIN_CFG(3, 0x07, 0x18560030),
-
 };
 
 const u32 pc_beep_verbs[0] = {};
 
+struct azalia_codec mainboard_azalia_codecs[] = {
+	{
+		.name         = "Realtek ALC889",
+		.vendor_id    = 0x10ec0889,
+		.subsystem_id = 0x1043841a,
+		.address      = 0,
+		.verbs        = realtek_alc889_verbs,
+		.verb_count   = ARRAY_SIZE(realtek_alc889_verbs),
+	},
+	{
+		.name         = "Intel Display Audio (HDMI/DP)",
+		.vendor_id    = 0x80862806,
+		.subsystem_id = 0x80860101,
+		.address      = 3,
+		.verbs        = intel_display_audio_verbs,
+		.verb_count   = ARRAY_SIZE(intel_display_audio_verbs),
+	},
+	{ /* terminator */ }
+};
+
 AZALIA_ARRAY_SIZES;
 
 enum e_spdif2_dest {
diff --git a/src/mainboard/asus/p8x7x-series/variants/p8z77-v_lx2/hda_verb.c b/src/mainboard/asus/p8x7x-series/variants/p8z77-v_lx2/hda_verb.c
index c6f3b6b4c0..8a94dae4a5 100644
--- a/src/mainboard/asus/p8x7x-series/variants/p8z77-v_lx2/hda_verb.c
+++ b/src/mainboard/asus/p8x7x-series/variants/p8z77-v_lx2/hda_verb.c
@@ -3,10 +3,7 @@
 #include <device/azalia_device.h>
 #include <device/azalia_codec/realtek.h>
 
-const u32 cim_verb_data[] = {
-	0x10ec0887,	/* Codec Vendor / Device ID: Realtek ALC887 */
-	0x10438445,	/* Subsystem ID */
-	15,		/* Number of 4 dword sets */
+static const u32 realtek_alc887_verbs[] = {
 	AZALIA_SUBVENDOR(0, 0x10438445),
 	AZALIA_PIN_CFG(0, ALC887_SPDIF_OUT2, 0x99430130),
 	AZALIA_PIN_CFG(0, ALC887_DMIC_LR, AZALIA_PIN_CFG_NC(0)),
@@ -22,10 +19,9 @@ const u32 cim_verb_data[] = {
 	AZALIA_PIN_CFG(0, ALC887_PC_BEEP, 0x4004c601),
 	AZALIA_PIN_CFG(0, ALC887_SPDIF_OUT1, AZALIA_PIN_CFG_NC(0)),
 	AZALIA_PIN_CFG(0, ALC887_SPDIF_IN, AZALIA_PIN_CFG_NC(0)),
+};
 
-	0x80862806,	/* Codec Vendor / Device ID: Intel HDMI */
-	0x80860101,	/* Subsystem ID */
-	4,		/* Number of 4 dword sets */
+static const u32 intel_display_audio_verbs[] = {
 	AZALIA_SUBVENDOR(3, 0x80860101),
 	AZALIA_PIN_CFG(3, 0x05, 0x58560010),
 	AZALIA_PIN_CFG(3, 0x06, 0x58560020),
@@ -35,4 +31,24 @@ const u32 cim_verb_data[] = {
 
 const u32 pc_beep_verbs[0] = {};
 
+struct azalia_codec mainboard_azalia_codecs[] = {
+	{
+		.name         = "Realtek ALC887",
+		.vendor_id    = 0x10ec0887,
+		.subsystem_id = 0x10438445,
+		.address      = 0,
+		.verbs        = realtek_alc887_verbs,
+		.verb_count   = ARRAY_SIZE(realtek_alc887_verbs),
+	},
+	{
+		.name         = "Intel Display Audio (HDMI/DP)",
+		.vendor_id    = 0x80862806,
+		.subsystem_id = 0x80860101,
+		.address      = 3,
+		.verbs        = intel_display_audio_verbs,
+		.verb_count   = ARRAY_SIZE(intel_display_audio_verbs),
+	},
+	{ /* terminator */ }
+};
+
 AZALIA_ARRAY_SIZES;

From 4b93b36170720fa84e3d892fc215f7d4703b2e6f Mon Sep 17 00:00:00 2001
From: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Date: Mon, 29 Sep 2025 20:21:39 +0900
Subject: [PATCH 2168/3886] mb/purism: add missing terminators to azalia codec
 tables

This was supposed to be checked in the regression test script
(CB:88763), however it turns out Valgrind's Memcheck only works on the
heap memory and is unable to catch such errors.

The regression test script was modified to use AddressSanitizer which
can catch such errors, so this should not be a problem in subsequent
changes during the verb table rework.

To be safe, the previously merged commits were also checked with the new
regression test script:

  f634121fa476 ("mb/purism: Replace verb tables with reworked implementation")
  20d404245832 ("mb/asrock: Replace verb tables with reworked implementation")
  2b7dbf80c981 ("mb/apple: Replace verb tables with reworked implementation")
  970249694f85 ("mb/amd: Replace verb tables with reworked implementation")
  94beaa7ab313 ("mb/acer: Replace verb tables with reworked implementation")
  f3db3a19d5cb ("mb/51nb: Replace verb tables with reworked implementation")

However, the following mini-HD code was checked manually, as figuring
out how to strip out minihd_init() was not worth the effort:

  bc92d9a66666 ("nb/intel/haswell/minihd.c: Add reworked verb table implementation")
  69781b980680 ("soc/intel/broadwell/minihd.c: Add reworked verb table implementation")

Change-Id: Iea964fb8b92814b57d4c82412c47cf31fa48de66
Signed-off-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89376
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/purism/librem_bdw/hda_verb.c                      | 1 +
 src/mainboard/purism/librem_cnl/variants/librem_14/hda_verb.c   | 1 +
 src/mainboard/purism/librem_cnl/variants/librem_mini/hda_verb.c | 1 +
 src/mainboard/purism/librem_jsl/hda_verb.c                      | 1 +
 src/mainboard/purism/librem_skl/hda_verb.c                      | 1 +
 5 files changed, 5 insertions(+)

diff --git a/src/mainboard/purism/librem_bdw/hda_verb.c b/src/mainboard/purism/librem_bdw/hda_verb.c
index 1cf41265d7..053088d671 100644
--- a/src/mainboard/purism/librem_bdw/hda_verb.c
+++ b/src/mainboard/purism/librem_bdw/hda_verb.c
@@ -28,6 +28,7 @@ struct azalia_codec mainboard_azalia_codecs[] = {
 		.verbs        = realtek_alc269_verbs,
 		.verb_count   = ARRAY_SIZE(realtek_alc269_verbs),
 	},
+	{ /* terminator */ }
 };
 
 AZALIA_ARRAY_SIZES;
diff --git a/src/mainboard/purism/librem_cnl/variants/librem_14/hda_verb.c b/src/mainboard/purism/librem_cnl/variants/librem_14/hda_verb.c
index 912f955710..7d95f8130f 100644
--- a/src/mainboard/purism/librem_cnl/variants/librem_14/hda_verb.c
+++ b/src/mainboard/purism/librem_cnl/variants/librem_14/hda_verb.c
@@ -116,6 +116,7 @@ struct azalia_codec mainboard_azalia_codecs[] = {
 		.verbs        = intel_display_audio_verbs,
 		.verb_count   = ARRAY_SIZE(intel_display_audio_verbs),
 	},
+	{ /* terminator */ }
 };
 
 AZALIA_ARRAY_SIZES;
diff --git a/src/mainboard/purism/librem_cnl/variants/librem_mini/hda_verb.c b/src/mainboard/purism/librem_cnl/variants/librem_mini/hda_verb.c
index 978a33c57d..07de4900c8 100644
--- a/src/mainboard/purism/librem_cnl/variants/librem_mini/hda_verb.c
+++ b/src/mainboard/purism/librem_cnl/variants/librem_mini/hda_verb.c
@@ -44,6 +44,7 @@ struct azalia_codec mainboard_azalia_codecs[] = {
 		.verbs        = intel_display_audio_verbs,
 		.verb_count   = ARRAY_SIZE(intel_display_audio_verbs),
 	},
+	{ /* terminator */ }
 };
 
 AZALIA_ARRAY_SIZES;
diff --git a/src/mainboard/purism/librem_jsl/hda_verb.c b/src/mainboard/purism/librem_jsl/hda_verb.c
index 293b090e94..aaac56361e 100644
--- a/src/mainboard/purism/librem_jsl/hda_verb.c
+++ b/src/mainboard/purism/librem_jsl/hda_verb.c
@@ -67,6 +67,7 @@ struct azalia_codec mainboard_azalia_codecs[] = {
 		.verbs        = intel_display_audio_verbs,
 		.verb_count   = ARRAY_SIZE(intel_display_audio_verbs),
 	},
+	{ /* terminator */ }
 };
 
 AZALIA_ARRAY_SIZES;
diff --git a/src/mainboard/purism/librem_skl/hda_verb.c b/src/mainboard/purism/librem_skl/hda_verb.c
index e308482497..0b61fb12f9 100644
--- a/src/mainboard/purism/librem_skl/hda_verb.c
+++ b/src/mainboard/purism/librem_skl/hda_verb.c
@@ -28,6 +28,7 @@ struct azalia_codec mainboard_azalia_codecs[] = {
 		.verbs        = realtek_alc269_verbs,
 		.verb_count   = ARRAY_SIZE(realtek_alc269_verbs),
 	},
+	{ /* terminator */ }
 };
 
 AZALIA_ARRAY_SIZES;

From 386feb720ebec01bba029d4bc1f906455111d839 Mon Sep 17 00:00:00 2001
From: Jason Chen <jason-ch.chen@mediatek.corp-partner.google.com>
Date: Fri, 3 Oct 2025 09:16:36 +0800
Subject: [PATCH 2169/3886] soc/mediatek/mt8196: Add DVFS support for the
 second SoC SKU

Devices utilizing the second SKU of the SoC experience system hangs due
to missing DVFS support. This patch adds DVFS support for the second
SKU to resolve this issue.

BRANCH=rauru
BUG=b:443664123
TEST=verify booting on both original and second SoC SKUs

Change-Id: If17ecd4a8358e08a45c4662bb92138b7a939512e
Signed-off-by: Jason Chen <jason-ch.chen@mediatek.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89405
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: jason-ch chen <Jason-ch.Chen@mediatek.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/soc/mediatek/mt8196/dvfs.c | 6 +++++-
 1 file changed, 5 insertions(+), 1 deletion(-)

diff --git a/src/soc/mediatek/mt8196/dvfs.c b/src/soc/mediatek/mt8196/dvfs.c
index 255f95e4d9..6f609e4698 100644
--- a/src/soc/mediatek/mt8196/dvfs.c
+++ b/src/soc/mediatek/mt8196/dvfs.c
@@ -7,8 +7,12 @@
 void dvfs_init(void)
 {
 	uint32_t val;
+	uint32_t seg = read32p(EFUSEC_BASE + 0x50);
 
-	val = BIT(8) | BIT(0);
+	if (seg == 0x14)
+		val = BIT(9) | BIT(0);
+	else
+		val = BIT(8) | BIT(0);
 
 	write32p(CSRAM_BASE + 0x8, 0x55AA55AA);
 	write32p(CSRAM_BASE + 0xC, val);

From 5609174786343b9c76e40dcc6d0d6575f28935ff Mon Sep 17 00:00:00 2001
From: Wentao Qin <qinwentao@huaqin.corp-partner.google.com>
Date: Fri, 26 Sep 2025 12:08:07 +0800
Subject: [PATCH 2170/3886] mb/google/rauru: Create variant Sapphire

Create the variant Sapphire.

BUG=b:446522353
TEST=emerge-tanjiro coreboot chromeos-bootimage
BRANCH=None

Change-Id: I722292f505a67fa072b5e24f7dd470944201a8b8
Signed-off-by: Wentao Qin <qinwentao@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89355
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/google/rauru/Kconfig      | 4 +++-
 src/mainboard/google/rauru/Kconfig.name | 3 +++
 2 files changed, 6 insertions(+), 1 deletion(-)

diff --git a/src/mainboard/google/rauru/Kconfig b/src/mainboard/google/rauru/Kconfig
index 9bccc87893..2e23681354 100644
--- a/src/mainboard/google/rauru/Kconfig
+++ b/src/mainboard/google/rauru/Kconfig
@@ -4,7 +4,8 @@
 config BOARD_GOOGLE_RAURU_COMMON
 	def_bool BOARD_GOOGLE_HYLIA || \
 		 BOARD_GOOGLE_NAVI || \
-		 BOARD_GOOGLE_RAURU
+		 BOARD_GOOGLE_RAURU || \
+		 BOARD_GOOGLE_SAPPHIRE
 
 if BOARD_GOOGLE_RAURU_COMMON
 
@@ -47,6 +48,7 @@ config MAINBOARD_PART_NUMBER
 	default "Hylia" if BOARD_GOOGLE_HYLIA
 	default "Navi" if BOARD_GOOGLE_NAVI
 	default "Rauru" if BOARD_GOOGLE_RAURU
+	default "Sapphire" if BOARD_GOOGLE_SAPPHIRE
 
 config VARIANT_DIR
 	default "navi" if BOARD_GOOGLE_NAVI
diff --git a/src/mainboard/google/rauru/Kconfig.name b/src/mainboard/google/rauru/Kconfig.name
index 589e131f10..f09ee43e15 100644
--- a/src/mainboard/google/rauru/Kconfig.name
+++ b/src/mainboard/google/rauru/Kconfig.name
@@ -10,3 +10,6 @@ config BOARD_GOOGLE_NAVI
 
 config BOARD_GOOGLE_RAURU
 	bool "->  Rauru"
+
+config BOARD_GOOGLE_SAPPHIRE
+	bool "->  Sapphire"

From fba92daed3c0719bf224fe3ddb48123d40941ac8 Mon Sep 17 00:00:00 2001
From: Swathi Tamilselvan <tswathi@qualcomm.corp-partner.google.com>
Date: Wed, 24 Sep 2025 16:47:02 +0530
Subject: [PATCH 2171/3886] soc/qualcomm/x1p42100: Clean up DDR and IMEM memory
 layout

Align DDR and IMEM address definitions with memory layout
specifications. Modify CBMEM top address accordingly.

Changes include:
  - Declaring new memory regions in symbols_common.h.
  - Defining base addresses and sizes for these regions in memlayout.ld.
  - Marking these regions as reserved in soc_read_resources() to
  prevent overwrites by coreboot.
  - Modifying CBMEM top address.

TEST=Create an image.serial.bin and ensure it boots on X1P42100.

Change-Id: I77c95198d6e42635ab7ecaac41fbd29133cb0fa0
Signed-off-by: Swathi Tamilselvan <tswathi@qualcomm.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89348
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
---
 .../common/include/soc/symbols_common.h       |  12 +-
 src/soc/qualcomm/x1p42100/cbmem.c             |   3 +-
 .../x1p42100/include/soc/addressmap.h         |   1 +
 src/soc/qualcomm/x1p42100/memlayout.ld        | 104 +++++++++++++-----
 src/soc/qualcomm/x1p42100/soc.c               |  13 ++-
 5 files changed, 102 insertions(+), 31 deletions(-)

diff --git a/src/soc/qualcomm/common/include/soc/symbols_common.h b/src/soc/qualcomm/common/include/soc/symbols_common.h
index bdd4be5979..7df10ecde2 100644
--- a/src/soc/qualcomm/common/include/soc/symbols_common.h
+++ b/src/soc/qualcomm/common/include/soc/symbols_common.h
@@ -32,9 +32,19 @@ DECLARE_REGION(dram_cpucp_dtbs)
 DECLARE_REGION(dram_cpucp)
 DECLARE_REGION(dram_modem)
 DECLARE_REGION(dram_tz)
-DECLARE_REGION(dram_tz_rem)
 DECLARE_REGION(dram_ramdump)
 DECLARE_REGION(dram_smem)
+DECLARE_REGION(dram_ncc)
+DECLARE_REGION(dram_xbl_log)
+DECLARE_REGION(dram_tme_crashdump)
+DECLARE_REGION(dram_tme_log)
+DECLARE_REGION(dram_dc_log)
+DECLARE_REGION(dram_tz_static)
+DECLARE_REGION(dram_adsp_rpc_heap)
+DECLARE_REGION(dram_llcc_lpi)
+DECLARE_REGION(dram_ta)
+DECLARE_REGION(dram_pdp)
+DECLARE_REGION(dram_pil)
 
 /*
  * DDR_SPACE (2 GB) aka `_dram`:  0x80000000 - 0x100000000
diff --git a/src/soc/qualcomm/x1p42100/cbmem.c b/src/soc/qualcomm/x1p42100/cbmem.c
index 27a46f6f17..6836a3ca84 100644
--- a/src/soc/qualcomm/x1p42100/cbmem.c
+++ b/src/soc/qualcomm/x1p42100/cbmem.c
@@ -1,9 +1,10 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
 #include <cbmem.h>
+#include <soc/addressmap.h>
 #include <soc/symbols_common.h>
 
 uintptr_t cbmem_top_chipset(void)
 {
-	return (uintptr_t)_dram_smem;
+	return (uintptr_t)CBMEM_TOP;
 }
diff --git a/src/soc/qualcomm/x1p42100/include/soc/addressmap.h b/src/soc/qualcomm/x1p42100/include/soc/addressmap.h
index 21341df24d..cbb6aa33cd 100644
--- a/src/soc/qualcomm/x1p42100/include/soc/addressmap.h
+++ b/src/soc/qualcomm/x1p42100/include/soc/addressmap.h
@@ -11,6 +11,7 @@
 #define GCC_BASE			0x00100000
 #define NCC0_BASE			0x19A30000
 
+#define CBMEM_TOP			0xC7800000
 /* X1P42100 NCC0 PLL CONFIG ADDRESSES */
 #define NCC0_NCC_CMU_NCC_PLL_CFG	0x199A2010
 #define NCC0_NCC_CMU_NCC_CLK_CFG	0x199A2030
diff --git a/src/soc/qualcomm/x1p42100/memlayout.ld b/src/soc/qualcomm/x1p42100/memlayout.ld
index 58e37a36c5..9996889cfd 100644
--- a/src/soc/qualcomm/x1p42100/memlayout.ld
+++ b/src/soc/qualcomm/x1p42100/memlayout.ld
@@ -4,7 +4,6 @@
 #include <arch/header.ld>
 #include <soc/memlayout.h>
 
-
 /*
  * The linker script below configures the memory layout for the Qualcomm X1P42100 SoC.
  *
@@ -21,21 +20,23 @@
  *               |         ... (Memory not mapped: Unavailable) ...         |  XXXXXXXXX    |
  * 0x100000000   +----------------------------------------------------------+ <---------    |
  *               |                 dram_smem (Shared Memory)                |      ^        |
+ * 0xFFE00000    +----------------------------------------------------------+      |        |
+ *               |                     dram_llcc_lpi                        |      |        |
  * 0xFF800000    +----------------------------------------------------------+      |        |
- *               |                        CBMEM                             |      |        |
- *               +----------------------------------------------------------+      |        |
  *               |                ... Usable memory ...                     |      |        |
+ * 0xDF4C0000    +----------------------------------------------------------+      |        |
+ *               |                       dram_ta                            |      |        |
  * 0xD8600000    +----------------------------------------------------------+      |        |
  *               |                 BL31 (ARM Trusted Firmware)              |      |        |
  * 0xD856A000    +----------------------------------------------------------+      |        |
- *               |               dram_tz_rem (TrustZone Remainder)          |      |        |
- * 0xD81D6000    +----------------------------------------------------------+      |        |
  *               |                  dram_tz (TrustZone)                     |      |        |
  * 0xD8000000    +----------------------------------------------------------+      |      DRAM
  *               |               ... Usable memory ...                      |      |        |
  * 0xD7800000    +----------------------------------------------------------+      |        |
  *               |                 Linux Kernel Reserve                     |      |        |
  * 0xC7800000    +----------------------------------------------------------+      |        |
+ *               |                        CBMEM                             |      |        |
+ *               +----------------------------------------------------------+      |        |
  *               |                ... Usable memory ...                     |      |        |
  * 0xA1800000    +----------------------------------------------------------+      |        |
  *               |                      RAMSTAGE                            | DRAM Space 0  |
@@ -44,13 +45,39 @@
  * 0x9F800000    +----------------------------------------------------------+      |        |
  *               |                ... Usable memory ...                     |      |        |
  * 0x91380000    +----------------------------------------------------------+      |        |
+ *               |                       dram_pil                           |      |        |
+ * 0x866C0000    +----------------------------------------------------------+      |        |
+ *               |                ... Usable memory ...                     |      |        |
+ * 0x85F80000    +----------------------------------------------------------+      |        |
+ *               |                       dram_wlan                          |      |        |
+ * 0x85380000    +----------------------------------------------------------+      |        |
+ *               |                ... Usable memory ...                     |      |        |
+ * 0x82800000    +----------------------------------------------------------+      |        |
+ *               |                 dram_adsp_rpc_heap                       |      |        |
+ * 0x82000000    +----------------------------------------------------------+      |        |
+ *               |                   dram_tz_static                         |      |        |
+ * 0x81F00000    +----------------------------------------------------------+      |        |
+ *               |                       dram_pdp                           |      |        |
+ * 0x81E00000    +----------------------------------------------------------+      |        |
+ *               |                  ... Usable memory ...                   |      |        |
+ * 0x81CF4000    +----------------------------------------------------------+      |        |
+ *               |                       dram_dc_log                        |      |        |
+ * 0x81CE4000    +----------------------------------------------------------+      |        |
+ *               |                       dram_tme_log                       |      |        |
+ * 0x81CE0000    +----------------------------------------------------------+      |        |
+ *               |                  dram_tme_crashdump                      |      |        |
+ * 0x81CA0000    +----------------------------------------------------------+      |        |
  *               |                       dram_aop                           |      |        |
  * 0x81C00000    +----------------------------------------------------------+      |        |
  *               |                     dram_ramdump                         |      |        |
+ * 0x81A40000    +----------------------------------------------------------+      |        |
+ *               |                     dram_xbl_log                         |      |        |
  * 0x81A00000    +----------------------------------------------------------+      |        |
  *               |                ... Usable memory ...                     |      |        |
  * 0x815A0000    +----------------------------------------------------------+      |        |
  *               |                      dram_cpucp                          |      |        |
+ * 0x80E00000    +----------------------------------------------------------+      |        |
+ *               |                      dram_ncc                            |      |        |
  * 0x80A00000    +----------------------------------------------------------+      |        |
  *               |                ... Usable memory ...                     |      v        v
  * 0x80000000    +----------------------------------------------------------+ <--------------
@@ -60,9 +87,9 @@
  * 0x24040000    +----------------------------------------------------------+ <---------
  *               |         ... (Memory not mapped: Unavailable) ...         | XXXXXXXXX
  * 0x14A80000    +----------------------------------------------------------+ <---------
- *               |                     debug_policy                         |      ^
- * 0x14A7F000    +----------------------------------------------------------+      |
- *               |                    auth_metadata                         |      |
+ *               |                    auth_metadata                         |      ^
+ * 0x14A7E000    +----------------------------------------------------------+      |
+ *               |                     debug_policy                         |      |
  * 0x14A7D000    +----------------------------------------------------------+      |
  *               |                ... Usable memory ...                     |      |
  * 0x14A59000    +----------------------------------------------------------+      |
@@ -77,6 +104,8 @@
  *               |                       qclib                              |      |
  * 0x14897000    +----------------------------------------------------------+      |
  *               |                ... Usable memory ...                     |      |
+ * 0x14890000    +----------------------------------------------------------+      |
+ *               |                    aop_blob_meta                         |      |
  * 0x1488C000    +----------------------------------------------------------+      |
  *               |                    qc_blob_meta                          |      |
  * 0x14888000    +----------------------------------------------------------+      |
@@ -119,19 +148,23 @@
  *               |                   pbl_timestamps                         |      v
  * 0x14800000    +----------------------------------------------------------+ <---------
  *               |              ... (Large Address Gap) ...                 |
- * 0x146AB000    +----------------------------------------------------------+ <---------
- *               |                     shared_imem                          |      ^
- * 0x146A8000    +----------------------------------------------------------+      |
- *               |                ... Usable memory ...                     |    SSRAM
+ * 0x146AC000    +----------------------------------------------------------+ <---------
+ *               |                ... Usable memory ...                     |      ^
+ * 0x146AB000    +----------------------------------------------------------+      |
+ *               |                     shared_imem                          |      |
+ * 0x146AA000    +----------------------------------------------------------+    SSRAM
+ *               |                ... Usable memory ...                     |      |
  * 0x146A5000    +----------------------------------------------------------+      |
  *               |                       qcsdi                              |      v
  * 0x14699000    +----------------------------------------------------------+ <---------
  *               |         ... (Memory not mapped: Unavailable) ...         | XXXXXXXXX
  * 0x0B100000    +----------------------------------------------------------+ <---------
- *               |                    aop_data_ram                          |      ^
- * 0x0B0E0000    +----------------------------------------------------------+      |
- *               |                ... Usable memory ...                     |   AOP SRAM
- * 0x0B080000    +----------------------------------------------------------+      |
+ *               |                ... Usable memory ...                     |      ^
+ * 0x0B0E8000    +----------------------------------------------------------+      |
+ *               |                    aop_data_ram                          |      |
+ * 0x0B0E0000    +----------------------------------------------------------+   AOP SRAM
+ *               |                ... Usable memory ...                     |      |
+ * 0x0B018000    +----------------------------------------------------------+      |
  *               |                    aop_code_ram                          |      v
  * 0x0B000000    +----------------------------------------------------------+ <---------
  *
@@ -140,14 +173,14 @@
 SECTIONS
 {
 	AOPSRAM_START(0x0B000000)
-	REGION(aop_code_ram, 0x0B000000, 0x80000, 4K)
-	REGION(aop_data_ram, 0x0B0E0000, 0x20000, 4K)
+	REGION(aop_code_ram, 0x0B000000, 0x18000, 4K)
+	REGION(aop_data_ram, 0x0B0E0000, 0x8000, 4K)
 	AOPSRAM_END(0x0B100000)
 
 	SSRAM_START(0x14680000)
 	REGION(qcsdi, 0x14699000, 48K, 4K)
-	REGION(shared_imem, 0x146A8000, 12K, 4K)
-	SSRAM_END(0x146AB000)
+	REGION(shared_imem, 0x146AA000, 0x1000, 4K)
+	SSRAM_END(0x146AC000)
 
 	BSRAM_START(0x14800000)
 	REGION(pbl_timestamps, 0x14800000, 84K, 4K)
@@ -172,22 +205,37 @@ SECTIONS
 	REGION(cpr_settings, 0x14A17000, 12K, 4K)
 	PRERAM_CBMEM_CONSOLE(0x14A30000, 32K)
 	OVERLAP_DECOMPRESSOR_VERSTAGE_ROMSTAGE(0x14A38000, 132K)
-	REGION(auth_metadata,0x14A7D000 , 8K, 4K)
-	REGION(debug_policy, 0x14A7F000, 4K, 4K)
+	REGION(debug_policy, 0x14A7D000 , 4K, 4K)
+	REGION(auth_metadata, 0x14A7E000, 8K, 4K)
 	BSRAM_END(0x14A80000)
 
 	REGION(shrm, 0x24040000, 128K , 4K)
 
 	DRAM_START(0x80000000)
-	REGION(dram_cpucp, 0x80A00000, 0xBA0000, 4K)
-	REGION(dram_ramdump, 0x81A00000, 0x200000, 4K)
-	REGION(dram_aop, 0x81C00000, 0xF780000, 4K)
+	REGION(dram_ncc, 0x80A00000, 0x400000, 4K)
+	REGION(dram_cpucp, 0x80E00000, 0x7A0000, 4K)
+
+	REGION(dram_xbl_log, 0x81A00000, 0x40000, 4K)
+	REGION(dram_ramdump, 0x81A40000, 0x1C0000, 4K)
+
+	REGION(dram_aop, 0x81C00000, 0xA0000, 4K)
+	REGION(dram_tme_crashdump, 0x81CA0000, 0x40000, 4K)
+	REGION(dram_tme_log, 0x81CE0000, 0x4000, 4K)
+	REGION(dram_dc_log, 0x81CE4000, 0x10000, 4K)
+
+	REGION(dram_pdp, 0x81E00000, 0x100000, 4K)
+	REGION(dram_tz_static, 0x81F00000, 0x100000, 4K)
+	REGION(dram_adsp_rpc_heap, 0x82000000, 0x800000, 4K)
+	REGION(dram_wlan, 0x85380000, 0xC00000, 4K)
+	REGION(dram_pil, 0x866C0000, 0xACC0000, 4K)
+
 	POSTRAM_CBFS_CACHE(0x9F800000, 16M)
 	RAMSTAGE(0xA0800000, 16M)
-	REGION(dram_tz, 0xD8000000, 0xD6000, 4K)
-	REGION(dram_tz_rem, 0xD81D6000, 0x394000, 4K)
+	REGION(dram_tz, 0xD8000000, 0x56A000, 4K)
 	BL31(0xD856A000, 600K)
-	REGION(dram_smem, 0xFF800000, 0x800000, 4K)
+	REGION(dram_ta, 0xD8600000, 0x1000000, 4K)
+	REGION(dram_llcc_lpi, 0xFF800000, 0x600000, 4K)
+	REGION(dram_smem, 0xFFE00000, 0x200000, 4K)
 	DRAM_END(0x100000000)
 
 	/*
diff --git a/src/soc/qualcomm/x1p42100/soc.c b/src/soc/qualcomm/x1p42100/soc.c
index e8bc4c0996..f76ba44e24 100644
--- a/src/soc/qualcomm/x1p42100/soc.c
+++ b/src/soc/qualcomm/x1p42100/soc.c
@@ -24,15 +24,26 @@ static void soc_read_resources(struct device *dev)
 	for (int i = 0; i < count; i++)
 		ram_range(dev, index++, (uintptr_t)config[i].offset, config[i].size);
 
+	reserved_ram_range(dev, index++, (uintptr_t)_dram_ncc, REGION_SIZE(dram_ncc));
 	reserved_ram_range(dev, index++, (uintptr_t)_dram_cpucp, REGION_SIZE(dram_cpucp));
+	reserved_ram_range(dev, index++, (uintptr_t)_dram_xbl_log, REGION_SIZE(dram_xbl_log));
 
 	reserved_ram_range(dev, index++, (uintptr_t)_dram_ramdump, REGION_SIZE(dram_ramdump));
 
 	reserved_ram_range(dev, index++, (uintptr_t)_dram_tz, REGION_SIZE(dram_tz));
-	reserved_ram_range(dev, index++, (uintptr_t)_dram_tz_rem, REGION_SIZE(dram_tz_rem));
 
 	reserved_ram_range(dev, index++, (uintptr_t)_dram_aop, REGION_SIZE(dram_aop));
+	reserved_ram_range(dev, index++, (uintptr_t)_dram_tme_crashdump, REGION_SIZE(dram_tme_crashdump));
+	reserved_ram_range(dev, index++, (uintptr_t)_dram_tme_log, REGION_SIZE(dram_tme_log));
+	reserved_ram_range(dev, index++, (uintptr_t)_dram_dc_log, REGION_SIZE(dram_dc_log));
 
+	reserved_ram_range(dev, index++, (uintptr_t)_dram_pdp, REGION_SIZE(dram_pdp));
+	reserved_ram_range(dev, index++, (uintptr_t)_dram_tz_static, REGION_SIZE(dram_tz_static));
+	reserved_ram_range(dev, index++, (uintptr_t)_dram_adsp_rpc_heap, REGION_SIZE(dram_adsp_rpc_heap));
+	reserved_ram_range(dev, index++, (uintptr_t)_dram_wlan, REGION_SIZE(dram_wlan));
+	reserved_ram_range(dev, index++, (uintptr_t)_dram_pil, REGION_SIZE(dram_pil));
+	reserved_ram_range(dev, index++, (uintptr_t)_dram_ta, REGION_SIZE(dram_ta));
+	reserved_ram_range(dev, index++, (uintptr_t)_dram_llcc_lpi, REGION_SIZE(dram_llcc_lpi));
 	reserved_ram_range(dev, index++, (uintptr_t)_dram_smem, REGION_SIZE(dram_smem));
 }
 

From 59cbb073c22b366a760fbd8e88f7ae16ae96b54e Mon Sep 17 00:00:00 2001
From: Walter Sonius <walterav1984@gmail.com>
Date: Sun, 14 Sep 2025 12:04:46 +0200
Subject: [PATCH 2172/3886] util/chromeos/crosfirmware.sh: Fix download of
 ninja (baytrail) recovery

Because the name NINJA has 2 occurrences inside remote recovery.conf:
https://dl.google.com/dl/edgedl/chromeos/recovery/recovery.conf

Running 'crosfirmware.sh ninja' will list both NINJA and VORTININJA
"file= & url=" with a total of 4 lines instead of 2. Since the script
by default uses the last 2 lines it will prefer VORTININJA and download
the Octopus MEEP recovery image instead while NINJA was requested.

By adjusting 'grep' its matching control by adding '-w' restores the
correct behaviour of only showing 2 lines for the requested image.
Both NINJA, VORTININJA and a third recovery image TIDUS still download
and extract correctly when applying this fix.

TEST=crosfirmware.sh ninja #downloads and extract correct image

Change-Id: I9b55c5a2626339e70f0ada9b80c9488a5580d371
Signed-off-by: Walter Sonius <walterav1984@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89168
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
---
 util/chromeos/crosfirmware.sh | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/util/chromeos/crosfirmware.sh b/util/chromeos/crosfirmware.sh
index 6dbac40394..673f3b38a5 100755
--- a/util/chromeos/crosfirmware.sh
+++ b/util/chromeos/crosfirmware.sh
@@ -171,7 +171,7 @@ elif [ "$BOARD" != "" ]; then
 	get_inventory $CONF
 
 	echo Processing board $BOARD
-	eval $(grep -i $BOARD -A8 $CONF | grep '\(url=\|file=\)')
+	eval $(grep -i -w $BOARD -A8 $CONF | grep '\(url=\|file=\)')
 	do_one_board $BOARD $url $file
 
 	rm "$CONF"

From 217a7962d0e596da2ab5791c4d8ca7e082b8c7e4 Mon Sep 17 00:00:00 2001
From: Yu-Ping Wu <yupingso@chromium.org>
Date: Fri, 3 Oct 2025 07:38:08 +0800
Subject: [PATCH 2173/3886] ec/google/chromeec: Update EC headers

Generated using update_ec_headers.sh from EC repo commit:

  8be982a31008 (cbi: Add Unified Firmware and Second-source Config (UFSC))

BUG=b:448300592
TEST=emerge-skywalker coreboot
BRANCH=none

Change-Id: I212489c2fd732478b12deb3c47521a050bd379f6
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89403
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
---
 src/ec/google/chromeec/ec_cmd_api.h  |  8 ++++++++
 src/ec/google/chromeec/ec_commands.h | 20 ++++++++++++++++++++
 2 files changed, 28 insertions(+)

diff --git a/src/ec/google/chromeec/ec_cmd_api.h b/src/ec/google/chromeec/ec_cmd_api.h
index dd833e4605..89c2d11f4c 100644
--- a/src/ec/google/chromeec/ec_cmd_api.h
+++ b/src/ec/google/chromeec/ec_cmd_api.h
@@ -121,6 +121,14 @@ static inline int ec_cmd_fp_template(CROS_EC_COMMAND_INFO *h,
 {
 	return CROS_EC_COMMAND(h, EC_CMD_FP_TEMPLATE, 0, p, size, NULL, 0);
 }
+
+static inline int ec_cmd_fp_info_v2(CROS_EC_COMMAND_INFO *h,
+				    struct ec_response_fp_info_v2 *r,
+				    size_t resp_size)
+{
+	return CROS_EC_COMMAND(h, EC_CMD_FP_INFO, 2, NULL, 0, r, resp_size);
+}
+
 /*
  * Section 2: EC interface functions that can be generated with the help
  * of template macros.
diff --git a/src/ec/google/chromeec/ec_commands.h b/src/ec/google/chromeec/ec_commands.h
index fa17a4fb23..073ae597cf 100644
--- a/src/ec/google/chromeec/ec_commands.h
+++ b/src/ec/google/chromeec/ec_commands.h
@@ -5014,6 +5014,14 @@ enum charge_state_params {
 	/* step value of charger input current limit (READ ONLY) */
 	CS_PARAM_CHG_INPUT_CURRENT_STEP,
 
+	/* Minimum required voltage for hybrid boost chargers (READ ONLY) */
+	CS_PARAM_CHG_MIN_REQUIRED_MV,
+
+	/* For hybrid boost chargers returns !=0 when attached charger is
+	 * capable of charging the battery
+	 */
+	CS_PARAM_CHG_IS_ADAPTER_SUFFICIENT,
+
 	/* How many so far? */
 	CS_NUM_BASE_PARAMS,
 
@@ -6644,10 +6652,22 @@ enum cbi_data_tag {
 	 */
 	CBI_TAG_PROVISION_MATRIX_VERSION = 28, /* uint32_t bit field */
 
+	/* Unified Firmware and Second-source Config:
+	 * A fixed-size array of 5 uint32_t values.
+	 */
+	CBI_TAG_UFSC = 29,
+
 	/* Last entry */
 	CBI_TAG_COUNT,
 };
 
+#define CBI_UFSC_DATA_COUNT 5
+
+/* Unified Firmware and Second-source Config (UFSC) data structure */
+struct cbi_ufsc {
+	uint32_t data[CBI_UFSC_DATA_COUNT];
+};
+
 /*
  * Flags to control read operation
  *

From 2a791fcd667f02d2231fc730a1a2b3811f48e4b7 Mon Sep 17 00:00:00 2001
From: Maxim Polyakov <max.senia.poliak@gmail.com>
Date: Wed, 1 Oct 2025 09:26:35 +0300
Subject: [PATCH 2174/3886] mb/imb-1222/hda: Use AZALIA_PIN_CFG_NC() for
 disabled SPDIF_OUT2 pin

Change-Id: Id745f53c77228fdb3a31f8618211a7d5c7ee911d
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89390
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
---
 src/mainboard/asrock/imb-1222/hda_verb.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/mainboard/asrock/imb-1222/hda_verb.c b/src/mainboard/asrock/imb-1222/hda_verb.c
index 02db917b73..08fc7ea119 100644
--- a/src/mainboard/asrock/imb-1222/hda_verb.c
+++ b/src/mainboard/asrock/imb-1222/hda_verb.c
@@ -5,7 +5,7 @@
 
 static const u32 realtek_alc887_vd_verbs[] = {
 	AZALIA_SUBVENDOR(0, 0x1849588a),
-	AZALIA_PIN_CFG(0, ALC887_SPDIF_OUT2, 0x40000000),
+	AZALIA_PIN_CFG(0, ALC887_SPDIF_OUT2, AZALIA_PIN_CFG_NC(0)),
 	AZALIA_PIN_CFG(0, ALC887_DMIC_LR, AZALIA_PIN_CFG_NC(0)),
 	AZALIA_PIN_CFG(0, ALC887_FRONT, AZALIA_PIN_DESC(
 		AZALIA_JACK,

From c2fcf69e411f4d538888d35b7d08070551d5a85c Mon Sep 17 00:00:00 2001
From: Elyes Haouas <ehaouas@noos.fr>
Date: Thu, 2 Oct 2025 15:15:05 +0200
Subject: [PATCH 2175/3886] arch/x86: Use boolean for flag_is_changeable_p()

Change-Id: I7a2edd86ed509a5de7e3529fdc2ea68fe9c268e0
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89401
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/arch/x86/cpu.c        | 2 +-
 src/arch/x86/cpu_common.c | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/arch/x86/cpu.c b/src/arch/x86/cpu.c
index 91cbcb05fa..683b8855b2 100644
--- a/src/arch/x86/cpu.c
+++ b/src/arch/x86/cpu.c
@@ -15,7 +15,7 @@
 
 #if ENV_X86_32
 /* Standard macro to see if a specific flag is changeable */
-static inline int flag_is_changeable_p(uint32_t flag)
+static inline bool flag_is_changeable_p(uint32_t flag)
 {
 	uint32_t f1, f2;
 
diff --git a/src/arch/x86/cpu_common.c b/src/arch/x86/cpu_common.c
index d7d701d016..0403703b86 100644
--- a/src/arch/x86/cpu_common.c
+++ b/src/arch/x86/cpu_common.c
@@ -6,7 +6,7 @@
 
 #if ENV_X86_32
 /* Standard macro to see if a specific flag is changeable */
-static inline int flag_is_changeable_p(uint32_t flag)
+static inline bool flag_is_changeable_p(uint32_t flag)
 {
 	uint32_t f1, f2;
 

From 830ec89bca967927a2dbbb78a24dba03624714eb Mon Sep 17 00:00:00 2001
From: Kapil Porwal <kapilporwal@google.com>
Date: Wed, 1 Oct 2025 16:24:50 +0530
Subject: [PATCH 2176/3886] mb/google/bluey: Update mainboard part number for
 QuenbiH
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

BUG=none
TEST=Verify FDT match for Google/QuenbiH.

Change-Id: I799b6b4143d582c3e6a6bdd2048a04457155b1ac
Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89395
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kornel Dulęba <korneld@google.com>
---
 src/mainboard/google/bluey/Kconfig | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/src/mainboard/google/bluey/Kconfig b/src/mainboard/google/bluey/Kconfig
index b3e8cc0637..0decb59ef2 100644
--- a/src/mainboard/google/bluey/Kconfig
+++ b/src/mainboard/google/bluey/Kconfig
@@ -123,7 +123,8 @@ config VBOOT
 
 config MAINBOARD_PART_NUMBER
 	default "Bluey" if BOARD_GOOGLE_MODEL_BLUEY
-	default "Quenbi" if BOARD_GOOGLE_MODEL_QUENBI
+	default "Quenbi" if BOARD_GOOGLE_QUENBI
+	default "QuenbiH" if BOARD_GOOGLE_QUENBIH
 	default "Quartz" if BOARD_GOOGLE_MODEL_QUARTZ
 
 config DRIVER_TPM_I2C_BUS

From 984ee53de87fd7b20c0872dbf201bd66087fd992 Mon Sep 17 00:00:00 2001
From: Keith Hui <buurin@gmail.com>
Date: Sun, 31 Aug 2025 17:09:24 -0400
Subject: [PATCH 2177/3886] mb/asus/p8x7x-series: Introduce CFR setup menu

Options are organized to be as close to vendor firmware as possible.

Some options are not implemented for all variants. Those are either
excluded from build via preprocessor, or left visible but unused.
They will be squared off later.

TEST=abuild tested on the whole series.
TEST=Complete platform setup menu appears for mb/asus/p8z77-v_le_plus
with edk2/mrchromebox payload, with changes to front audio panel type
reflected in hardware.

Change-Id: I558012b28d098a90863e3ff6610017c2410c23ed
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89045
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
---
 src/mainboard/asus/p8x7x-series/Makefile.mk |   1 +
 src/mainboard/asus/p8x7x-series/cfr.c       | 118 ++++++++++++++++++++
 2 files changed, 119 insertions(+)
 create mode 100644 src/mainboard/asus/p8x7x-series/cfr.c

diff --git a/src/mainboard/asus/p8x7x-series/Makefile.mk b/src/mainboard/asus/p8x7x-series/Makefile.mk
index e339285620..3fc1de8f61 100644
--- a/src/mainboard/asus/p8x7x-series/Makefile.mk
+++ b/src/mainboard/asus/p8x7x-series/Makefile.mk
@@ -6,3 +6,4 @@ bootblock-y += variants/$(VARIANT_DIR)/gpio.c
 romstage-y  += variants/$(VARIANT_DIR)/gpio.c
 ramstage-y  += variants/$(VARIANT_DIR)/hda_verb.c
 ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += variants/$(VARIANT_DIR)/gma-mainboard.ads
+ramstage-$(CONFIG_DRIVERS_OPTION_CFR) += cfr.c
diff --git a/src/mainboard/asus/p8x7x-series/cfr.c b/src/mainboard/asus/p8x7x-series/cfr.c
new file mode 100644
index 0000000000..bba60a6610
--- /dev/null
+++ b/src/mainboard/asus/p8x7x-series/cfr.c
@@ -0,0 +1,118 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <boot/coreboot_tables.h>
+#include <drivers/option/cfr_frontend.h>
+#include <console/cfr.h>
+#include <northbridge/intel/sandybridge/cfr.h>
+#include <southbridge/intel/bd82x6x/cfr.h>
+
+#if CONFIG(USE_NATIVE_RAMINIT)
+static struct sm_obj_form sysagent = {
+	.ui_name = "Graphics Configuration",
+	.obj_list = (const struct sm_object *[]) {
+		&gfx_uma_size,
+		NULL
+	},
+};
+#else
+static const struct sm_object usb3_mode = SM_DECLARE_ENUM({
+	.opt_name	= "usb3_mode",
+	.ui_name	= "Intel xHCI Mode",
+	.default_value	= 3,
+	.values		= (const struct sm_enum_value[]) {
+				{ "Disable",	0	},
+				{ "Enable",	1	},
+				{ "Auto",	2	},
+				{ "Smart Auto",	3	},
+				SM_ENUM_VALUE_END	},
+});
+
+static const struct sm_object usb3_drv = SM_DECLARE_BOOL({
+	.opt_name	= "usb3_drv",
+	.ui_name	= "Legacy USB3.0 Support",
+	.ui_helptext	= "Enable/Disable USB3.0 (XHCI) Controller Legacy Support.",
+	.default_value	= 1,
+});
+
+static const struct sm_object usb3_streams = SM_DECLARE_BOOL({
+	.opt_name	= "usb3_streams",
+	.ui_name	= "xHCI Streams",
+	.default_value	= 1,
+});
+
+static struct sm_obj_form sysagent = {
+	.ui_name = "System Agent Configuration",
+	.obj_list = (const struct sm_object *[]) {
+		&gfx_uma_size,
+		&usb3_mode,
+		&usb3_drv,
+		&usb3_streams,
+		NULL
+	},
+};
+#endif
+
+/* Front audio panel */
+static const struct sm_object audio_panel_type = SM_DECLARE_ENUM({
+	.opt_name	= "audio_panel_type",
+	.ui_name	= "Front Panel Type",
+	.default_value	= 0,
+	.values		= (const struct sm_enum_value[]) {
+				{ "HD",	0	},
+				{ "AC97", 1	},
+				SM_ENUM_VALUE_END },
+});
+
+#if CONFIG(BOARD_ASUS_P8Z77_V_LE_PLUS)
+static const struct sm_object spdif_dest = SM_DECLARE_ENUM({
+	.opt_name	= "spdif_dest",
+	.ui_name	= "SPDIF Out Type",
+	.default_value	= 0,
+	.values		= (const struct sm_enum_value[]) {
+				{ "SPDIF",	0	},
+				{ "HDMI",	1	},
+				SM_ENUM_VALUE_END	},
+});
+#endif
+
+static struct sm_obj_form onboard_devices = {
+	.ui_name = "Onboard Devices Configuration",
+	.obj_list = (const struct sm_object *[]) {
+		&sata_mode,
+		&audio_panel_type,
+#if CONFIG(BOARD_ASUS_P8Z77_V_LE_PLUS)
+		&spdif_dest,
+#endif
+		NULL
+	},
+};
+
+static struct sm_obj_form power = {
+	.ui_name = "Power Management",
+	.obj_list = (const struct sm_object *[]) {
+		&power_on_after_fail,
+		NULL
+	},
+};
+
+static struct sm_obj_form system = {
+	.ui_name = "Other System Settings",
+	.obj_list = (const struct sm_object *[]) {
+		&nmi,
+		&debug_level,
+		NULL
+	},
+};
+
+static struct sm_obj_form *sm_root[] = {
+	&sysagent,
+	&onboard_devices,
+	&power,
+	&system,
+	NULL
+};
+
+void mb_cfr_setup_menu(struct lb_cfr *cfr_root)
+{
+	cfr_write_setup_menu(cfr_root, sm_root);
+}

From 98a54453284ef2a3c11fde2cd97e7ca41883f9c9 Mon Sep 17 00:00:00 2001
From: Nicholas Chin <nic.c3.14@gmail.com>
Date: Sun, 5 Oct 2025 20:33:06 -0600
Subject: [PATCH 2178/3886] MAINTAINERS: Correct paths for Dell Latitude
 mainboards

The E6400 and E7240 were updated to use a variant scheme in commit
f62734976ce8 ("mb/dell: Convert E6400 into a variant") and commit
511872dae3ea ("mb/dell: Convert Latitude E7240 into a variant"),
respectively, which changed the names of the directories they were
located in. Update MAINTAINERS to reflect this.

Change-Id: If35e5a0afe214fe623334e90969cc7f95d579a86
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89422
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
---
 MAINTAINERS | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/MAINTAINERS b/MAINTAINERS
index ddca248f82..dddfa099a8 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -273,9 +273,9 @@ F:	src/mainboard/dell/
 DELL LATITUDE MAINBOARDS
 M:	Nicholas Chin <nic.c3.14@gmail.com>
 S:	Maintained
-F:	src/mainboard/dell/e6400/
+F:	src/mainboard/dell/gm45_latitude/
 F:	src/mainboard/dell/snb_ivb_latitude/
-F:	src/mainboard/dell/e7240/
+F:	src/mainboard/dell/haswell_latitude/
 
 
 EMULATION MAINBOARDS

From 46ce812c1b6beb18dfb43d5a7e00fc9f921b413f Mon Sep 17 00:00:00 2001
From: Daniel Peng <Daniel_Peng@pegatron.corp-partner.google.com>
Date: Fri, 3 Oct 2025 11:10:33 +0800
Subject: [PATCH 2179/3886] mb/google/skywalker: Create variant Grogu

Create the variant Grogu for Starros/Grogu projects.

BUG=b:441547156
TEST=emerge-skywalker coreboot
     And local build bios successfully.
BRANCH=skywalker

Change-Id: I15cd5ee9bceb526c785f5ab34a6d35c138df78d1
Signed-off-by: Daniel Peng <Daniel_Peng@pegatron.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89408
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
---
 src/mainboard/google/skywalker/Kconfig      | 2 ++
 src/mainboard/google/skywalker/Kconfig.name | 3 +++
 2 files changed, 5 insertions(+)

diff --git a/src/mainboard/google/skywalker/Kconfig b/src/mainboard/google/skywalker/Kconfig
index dd97f682b4..c369c5b5c2 100644
--- a/src/mainboard/google/skywalker/Kconfig
+++ b/src/mainboard/google/skywalker/Kconfig
@@ -4,6 +4,7 @@
 config BOARD_GOOGLE_SKYWALKER_COMMON
 	def_bool BOARD_GOOGLE_ANAKIN || \
 		 BOARD_GOOGLE_BAZE || \
+		 BOARD_GOOGLE_GROGU || \
 		 BOARD_GOOGLE_OBIWAN || \
 		 BOARD_GOOGLE_PADME || \
 		 BOARD_GOOGLE_SKYWALKER || \
@@ -51,6 +52,7 @@ config MAINBOARD_PART_NUMBER
 	string
 	default "Anakin" if BOARD_GOOGLE_ANAKIN
 	default "Baze" if BOARD_GOOGLE_BAZE
+	default "Grogu" if BOARD_GOOGLE_GROGU
 	default "Obiwan" if BOARD_GOOGLE_OBIWAN
 	default "Padme" if BOARD_GOOGLE_PADME
 	default "Skywalker" if BOARD_GOOGLE_SKYWALKER
diff --git a/src/mainboard/google/skywalker/Kconfig.name b/src/mainboard/google/skywalker/Kconfig.name
index 8343e47a03..abdaf64209 100644
--- a/src/mainboard/google/skywalker/Kconfig.name
+++ b/src/mainboard/google/skywalker/Kconfig.name
@@ -8,6 +8,9 @@ config BOARD_GOOGLE_ANAKIN
 config BOARD_GOOGLE_BAZE
 	bool "->  Baze"
 
+config BOARD_GOOGLE_GROGU
+	bool "->  Grogu"
+
 config BOARD_GOOGLE_OBIWAN
 	bool "->  Obiwan"
 

From bca876849ac643512e3ffd6a3df57c59644588d2 Mon Sep 17 00:00:00 2001
From: Yidi Lin <yidilin@google.com>
Date: Thu, 2 Oct 2025 21:14:26 +0800
Subject: [PATCH 2180/3886] soc/mediatek/common: Add enable parameter for
 configure_backlight

This change refactors `configure_backlight` function to accept a boolean
'enable' parameter. This provides more explicit control over the
backlight state.

BUG=b:319511268,b:319511268
TEST=emerge-rauru coreboot

Change-Id: Ia713dc792186a9a8080fd9d7ee02738fd372f531
Signed-off-by: Yidi Lin <yidilin@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89409
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
---
 src/mainboard/google/cherry/mainboard.c       | 7 +++----
 src/mainboard/google/corsola/panel.c          | 7 +++----
 src/mainboard/google/corsola/panel.h          | 3 ++-
 src/mainboard/google/geralt/panel.c           | 6 +++---
 src/mainboard/google/geralt/panel.h           | 3 ++-
 src/mainboard/google/rauru/panel.c            | 7 +++----
 src/mainboard/google/skywalker/panel.c        | 7 +++----
 src/mainboard/google/skywalker/panel.h        | 3 ++-
 src/soc/mediatek/common/display.c             | 3 ++-
 src/soc/mediatek/common/include/soc/display.h | 3 ++-
 10 files changed, 25 insertions(+), 24 deletions(-)

diff --git a/src/mainboard/google/cherry/mainboard.c b/src/mainboard/google/cherry/mainboard.c
index 16eabbac37..a0d5f80990 100644
--- a/src/mainboard/google/cherry/mainboard.c
+++ b/src/mainboard/google/cherry/mainboard.c
@@ -53,11 +53,10 @@ bool mainboard_needs_pcie_init(void)
 	return false;
 }
 
-/* Set up backlight control pins as output pin and power-off by default */
-static void configure_backlight(void)
+static void configure_backlight(bool enable)
 {
-	gpio_output(GPIO_AP_EDP_BKLTEN, 0);
-	gpio_output(GPIO_BL_PWM_1V8, 0);
+	gpio_output(GPIO_AP_EDP_BKLTEN, enable);
+	gpio_output(GPIO_BL_PWM_1V8, enable);
 }
 
 static void power_on_panel(void)
diff --git a/src/mainboard/google/corsola/panel.c b/src/mainboard/google/corsola/panel.c
index e77cb97989..5e773e3a1f 100644
--- a/src/mainboard/google/corsola/panel.c
+++ b/src/mainboard/google/corsola/panel.c
@@ -28,11 +28,10 @@ bool is_pmic_aw37503(unsigned int bus)
 				0x04, &vendor_id, 0x0F, 0) && vendor_id == 0x01);
 }
 
-void backlight_control(void)
+void backlight_control(bool enable)
 {
-	/* Set up backlight control pins as output pin and power-off by default */
-	gpio_output(GPIO_AP_EDP_BKLTEN, 0);
-	gpio_output(GPIO_BL_PWM_1V8, 0);
+	gpio_output(GPIO_AP_EDP_BKLTEN, enable);
+	gpio_output(GPIO_BL_PWM_1V8, enable);
 }
 
 struct panel_description *get_active_panel(void)
diff --git a/src/mainboard/google/corsola/panel.h b/src/mainboard/google/corsola/panel.h
index 01606f4dab..9190a23782 100644
--- a/src/mainboard/google/corsola/panel.h
+++ b/src/mainboard/google/corsola/panel.h
@@ -6,6 +6,7 @@
 #include <soc/display.h>
 #include <soc/i2c.h>
 #include <soc/tps65132s.h>
+#include <stdbool.h>
 
 #define BRIDGE_I2C		I2C0
 #define PMIC_AW37503_SLAVE	0x3E
@@ -14,7 +15,7 @@
 void aw37503_init(unsigned int bus);
 bool is_pmic_aw37503(unsigned int bus);
 uint32_t panel_id(void);
-void backlight_control(void);
+void backlight_control(bool enable);
 void tps65132s_power_on(struct tps65132s_cfg *config);
 
 /* Return the mipi panel description from given panel id */
diff --git a/src/mainboard/google/geralt/panel.c b/src/mainboard/google/geralt/panel.c
index 82f49ab09e..6168a42acc 100644
--- a/src/mainboard/google/geralt/panel.c
+++ b/src/mainboard/google/geralt/panel.c
@@ -27,10 +27,10 @@ struct panel_description *get_active_panel(void)
 	return get_panel_description(active_panel_id);
 }
 
-void configure_mipi_pwm_backlight(void)
+void configure_mipi_pwm_backlight(bool enable)
 {
-	gpio_output(GPIO_AP_DISP_BKLTEN, 0);
-	gpio_output(GPIO_MIPI_BL_PWM_1V8, 0);
+	gpio_output(GPIO_AP_DISP_BKLTEN, enable);
+	gpio_output(GPIO_MIPI_BL_PWM_1V8, enable);
 }
 
 void fill_lp_backlight_gpios(struct lb_gpios *gpios)
diff --git a/src/mainboard/google/geralt/panel.h b/src/mainboard/google/geralt/panel.h
index 7e07fb1684..381de0d3a7 100644
--- a/src/mainboard/google/geralt/panel.h
+++ b/src/mainboard/google/geralt/panel.h
@@ -5,8 +5,9 @@
 
 #include <soc/display.h>
 #include <soc/tps65132s.h>
+#include <stdbool.h>
 
-void configure_mipi_pwm_backlight(void);
+void configure_mipi_pwm_backlight(bool enable);
 void fill_lp_backlight_gpios(struct lb_gpios *gpios);
 void power_on_mipi_panel(const struct tps65132s_cfg *cfg);
 uint32_t panel_id(void);
diff --git a/src/mainboard/google/rauru/panel.c b/src/mainboard/google/rauru/panel.c
index cb7042ae3c..60afca61bb 100644
--- a/src/mainboard/google/rauru/panel.c
+++ b/src/mainboard/google/rauru/panel.c
@@ -9,11 +9,10 @@
 #include "gpio.h"
 #include "panel.h"
 
-/* Set up backlight control pins as output pin and power-off by default */
-static void configure_backlight(void)
+static void configure_backlight(bool enable)
 {
-	gpio_output(GPIO_AP_EDP_BKLTEN, 0);
-	gpio_output(GPIO_BL_PWM_1V8, 0);
+	gpio_output(GPIO_AP_EDP_BKLTEN, enable);
+	gpio_output(GPIO_BL_PWM_1V8, enable);
 }
 
 static void power_on_panel(void)
diff --git a/src/mainboard/google/skywalker/panel.c b/src/mainboard/google/skywalker/panel.c
index deb392f281..bd4ef3374f 100644
--- a/src/mainboard/google/skywalker/panel.c
+++ b/src/mainboard/google/skywalker/panel.c
@@ -27,11 +27,10 @@ static bool is_pmic_aw37503(unsigned int bus)
 				0x04, &vendor_id, 0x0F, 0) && vendor_id == 0x01);
 }
 
-/* Set up backlight control pins as output pins, and set them to power off by default */
-void panel_configure_backlight(void)
+void panel_configure_backlight(bool enable)
 {
-	gpio_output(GPIO_EDP_BL_EN_1V8, 0);
-	gpio_output(GPIO_BL_PWM_1V8, 0);
+	gpio_output(GPIO_EDP_BL_EN_1V8, enable);
+	gpio_output(GPIO_BL_PWM_1V8, enable);
 }
 
 static void power_on_panel(void)
diff --git a/src/mainboard/google/skywalker/panel.h b/src/mainboard/google/skywalker/panel.h
index 77c8aed5e5..f38f50404d 100644
--- a/src/mainboard/google/skywalker/panel.h
+++ b/src/mainboard/google/skywalker/panel.h
@@ -6,6 +6,7 @@
 #include <gpio.h>
 #include <soc/display.h>
 #include <soc/i2c.h>
+#include <stdbool.h>
 
 #define PMIC_AW37503_SLAVE	0x3E
 #define PMIC_I2C_BUS		I2C6
@@ -17,7 +18,7 @@ struct aw37503_config {
 
 uint8_t panel_id(void);
 
-void panel_configure_backlight(void);
+void panel_configure_backlight(bool enable);
 void mipi_panel_power_on(void);
 
 /* Return the mipi panel description */
diff --git a/src/soc/mediatek/common/display.c b/src/soc/mediatek/common/display.c
index c805c6d664..84981f059e 100644
--- a/src/soc/mediatek/common/display.c
+++ b/src/soc/mediatek/common/display.c
@@ -81,8 +81,9 @@ int mtk_display_init(void)
 	mtcmos_display_power_on();
 	mtcmos_protect_display_bus();
 
+	/* Set up backlight control pins as output pin and turn-off the backlight */
 	if (panel->configure_backlight)
-		panel->configure_backlight();
+		panel->configure_backlight(false);
 	if (panel->power_on)
 		panel->power_on();
 
diff --git a/src/soc/mediatek/common/include/soc/display.h b/src/soc/mediatek/common/include/soc/display.h
index 0d06a3cd2c..a874412aff 100644
--- a/src/soc/mediatek/common/include/soc/display.h
+++ b/src/soc/mediatek/common/include/soc/display.h
@@ -5,6 +5,7 @@
 
 #include <commonlib/coreboot_tables.h>
 #include <mipi/panel.h>
+#include <stdbool.h>
 
 enum disp_path_sel {
 	DISP_PATH_NONE = 0,
@@ -16,7 +17,7 @@ enum disp_path_sel {
 
 struct panel_description {
 	const char *name;
-	void (*configure_backlight)(void);
+	void (*configure_backlight)(bool enable);
 	void (*power_on)(void);
 	int (*get_edid)(struct edid *edid);
 	int (*post_power_on)(const struct edid *edid);

From 28a8eaa57b971c6201fc78c5c9efe58358d42665 Mon Sep 17 00:00:00 2001
From: Yidi Lin <yidilin@google.com>
Date: Fri, 3 Oct 2025 13:22:55 +0800
Subject: [PATCH 2181/3886] soc/mediatek/mt8192: Clean up memlayout.ld

The macros being removed are already defined in the soc/memlayout.h.
Remove the duplicated definitions and include the common header instead.

BUG=none
TEST=emerge-asurada coreboot

Change-Id: I38d9ca2310fbc60bb453b9731203ffb0251cb444
Signed-off-by: Yidi Lin <yidilin@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89410
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 .../mediatek/mt8192/include/soc/memlayout.ld  | 19 +------------------
 1 file changed, 1 insertion(+), 18 deletions(-)

diff --git a/src/soc/mediatek/mt8192/include/soc/memlayout.ld b/src/soc/mediatek/mt8192/include/soc/memlayout.ld
index 2442e307c5..6d819a0765 100644
--- a/src/soc/mediatek/mt8192/include/soc/memlayout.ld
+++ b/src/soc/mediatek/mt8192/include/soc/memlayout.ld
@@ -1,23 +1,6 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
-#include <memlayout.h>
-
-#include <arch/header.ld>
-
-/*
- * SRAM_L2C is the half part of L2 cache that we borrow to be used as SRAM.
- * It will be returned before starting the ramstage.
- * SRAM_L2C and SRAM can be cached, but only SRAM is DMA-able.
- */
-#define SRAM_L2C_START(addr) REGION_START(sram_l2c, addr)
-#define SRAM_L2C_END(addr) REGION_END(sram_l2c, addr)
-#define DRAM_INIT_CODE(addr, size) \
-	REGION(dram_init_code, addr, size, 64K)
-
-#define DRAM_DMA(addr, size) \
-	REGION(dram_dma, addr, size, 4K) \
-	_ = ASSERT(size % 4K == 0, \
-		"DRAM DMA buffer should be multiple of smallest page size (4K)!");
+#include <soc/memlayout.h>
 
 SECTIONS
 {

From b48532c6941cde0fdf6b3530a87be3215749a65b Mon Sep 17 00:00:00 2001
From: Yidi Lin <yidilin@google.com>
Date: Fri, 3 Oct 2025 13:57:21 +0800
Subject: [PATCH 2182/3886] soc/mediatek: Refactor MMU configuration for DMA
 region

This patch refactors the MMU configuration for the DMA region by moving
the logic from mmu_cmops.c to the common/mmu_operations.c. This
centralization simplifies the code and removes duplication.

The following changes are included:
- Deleted src/soc/mediatek/common/mmu_cmops.c
- Moved DMA region configuration to mtk_mmu_after_dram
- Updated Makefiles to remove references to the deleted file

BRANCH=none
BUG=none
TEST=emerge-kukui coreboot -j && emerge-elm  coreboot -j && \
     emerge-rauru coreboot -j

Change-Id: I06289afa74248d55fc1eabeef2f6591bc805a8cf
Signed-off-by: Yidi Lin <yidilin@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89411
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/soc/mediatek/common/mmu_cmops.c      | 11 -----------
 src/soc/mediatek/common/mmu_operations.c |  2 ++
 src/soc/mediatek/mt8173/mmu_operations.c |  5 -----
 src/soc/mediatek/mt8186/Makefile.mk      |  4 ++--
 src/soc/mediatek/mt8188/Makefile.mk      |  4 ++--
 src/soc/mediatek/mt8189/Makefile.mk      |  4 ++--
 src/soc/mediatek/mt8192/Makefile.mk      |  4 ++--
 src/soc/mediatek/mt8195/Makefile.mk      |  4 ++--
 src/soc/mediatek/mt8196/Makefile.mk      |  4 ++--
 9 files changed, 14 insertions(+), 28 deletions(-)
 delete mode 100644 src/soc/mediatek/common/mmu_cmops.c

diff --git a/src/soc/mediatek/common/mmu_cmops.c b/src/soc/mediatek/common/mmu_cmops.c
deleted file mode 100644
index e102569745..0000000000
--- a/src/soc/mediatek/common/mmu_cmops.c
+++ /dev/null
@@ -1,11 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <soc/symbols.h>
-#include <soc/mmu_operations.h>
-
-/* mtk_soc_after_dram is called in romstage */
-void mtk_soc_after_dram(void)
-{
-	mmu_config_range(_dram_dma, REGION_SIZE(dram_dma),
-			 NONSECURE_UNCACHED_MEM);
-}
diff --git a/src/soc/mediatek/common/mmu_operations.c b/src/soc/mediatek/common/mmu_operations.c
index 5471af27e9..1bbe4dc319 100644
--- a/src/soc/mediatek/common/mmu_operations.c
+++ b/src/soc/mediatek/common/mmu_operations.c
@@ -49,6 +49,8 @@ void mtk_mmu_after_dram(void)
 	/* Map DRAM as cached now that it's up and running */
 	mmu_config_range(_dram, (uintptr_t)sdram_size(), NONSECURE_CACHED_MEM);
 
+	mmu_config_range(_dram_dma, REGION_SIZE(dram_dma), NONSECURE_UNCACHED_MEM);
+
 	mtk_soc_after_dram();
 }
 
diff --git a/src/soc/mediatek/mt8173/mmu_operations.c b/src/soc/mediatek/mt8173/mmu_operations.c
index 44e3ddf24e..7c03b1887c 100644
--- a/src/soc/mediatek/mt8173/mmu_operations.c
+++ b/src/soc/mediatek/mt8173/mmu_operations.c
@@ -1,17 +1,12 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
 #include <device/mmio.h>
-#include <arch/mmu.h>
-#include <symbols.h>
-#include <soc/symbols.h>
 #include <soc/infracfg.h>
 #include <soc/mcucfg.h>
 #include <soc/mmu_operations.h>
 
 void mtk_soc_after_dram(void)
 {
-	mmu_config_range(_dram_dma, REGION_SIZE(dram_dma),
-			 NONSECURE_UNCACHED_MEM);
 	mtk_mmu_disable_l2c_sram();
 }
 
diff --git a/src/soc/mediatek/mt8186/Makefile.mk b/src/soc/mediatek/mt8186/Makefile.mk
index e3592fc418..080cc1337f 100644
--- a/src/soc/mediatek/mt8186/Makefile.mk
+++ b/src/soc/mediatek/mt8186/Makefile.mk
@@ -26,7 +26,7 @@ romstage-y += ../common/emi.c
 romstage-y += ../common/l2c_ops.c
 romstage-y += ../common/memory.c
 romstage-y += ../common/memory_test.c
-romstage-y += ../common/mmu_operations.c ../common/mmu_cmops.c
+romstage-y += ../common/mmu_operations.c
 romstage-y += ../common/mt6315.c mt6315.c
 romstage-y += ../common/pmic_wrap.c pmic_wrap.c pmif.c mt6366.c
 romstage-y += ../common/pmif.c ../common/pmif_clk.c ../common/pmif_init.c pmif_clk.c
@@ -44,7 +44,7 @@ ramstage-y += ../common/dsi.c ../common/mtk_mipi_dphy.c
 ramstage-y += ../common/emi.c
 ramstage-y += ../common/l2c_ops.c
 ramstage-y += ../common/mcu.c
-ramstage-y += ../common/mmu_operations.c ../common/mmu_cmops.c
+ramstage-y += ../common/mmu_operations.c
 ramstage-$(CONFIG_COMMONLIB_STORAGE_MMC) += ../common/msdc.c msdc.c
 ramstage-y += ../common/mtcmos.c mtcmos.c
 ramstage-y += ../common/pmic_wrap.c pmic_wrap.c pmif.c mt6366.c
diff --git a/src/soc/mediatek/mt8188/Makefile.mk b/src/soc/mediatek/mt8188/Makefile.mk
index 0469738ff4..f8a7faa577 100644
--- a/src/soc/mediatek/mt8188/Makefile.mk
+++ b/src/soc/mediatek/mt8188/Makefile.mk
@@ -24,7 +24,7 @@ romstage-y += ../common/emi.c
 romstage-y += ../common/l2c_ops.c
 romstage-y += ../common/memory.c
 romstage-y += ../common/memory_test.c
-romstage-y += ../common/mmu_operations.c ../common/mmu_cmops.c
+romstage-y += ../common/mmu_operations.c
 romstage-y += ../common/mt6315.c mt6315.c
 romstage-y += ../common/mt6359p.c mt6359p.c
 romstage-y += ../common/pmif.c ../common/pmif_clk.c ../common/pmif_init.c pmif_clk.c
@@ -50,7 +50,7 @@ ramstage-y += ../common/emi.c
 ramstage-y += ../common/l2c_ops.c
 ramstage-y += ../common/mcu.c
 ramstage-y += ../common/mcupm.c
-ramstage-y += ../common/mmu_operations.c ../common/mmu_cmops.c
+ramstage-y += ../common/mmu_operations.c
 ramstage-$(CONFIG_COMMONLIB_STORAGE_MMC) += ../common/msdc.c msdc.c
 ramstage-y += ../common/mt6359p.c mt6359p.c
 ramstage-y += ../common/mtcmos.c mtcmos.c
diff --git a/src/soc/mediatek/mt8189/Makefile.mk b/src/soc/mediatek/mt8189/Makefile.mk
index 8eda710cc2..02e2847123 100644
--- a/src/soc/mediatek/mt8189/Makefile.mk
+++ b/src/soc/mediatek/mt8189/Makefile.mk
@@ -26,7 +26,7 @@ romstage-y += ../common/dramc_param.c
 romstage-y += dvfs.c
 romstage-y += ../common/emi.c
 romstage-y += ../common/memory.c ../common/memory_test.c ../common/memory_type.c
-romstage-y += ../common/mmu_operations.c ../common/mmu_cmops.c
+romstage-y += ../common/mmu_operations.c
 romstage-y += ../common/thermal.c thermal.c
 romstage-y += ../common/thermal_sram.c thermal_sram.c
 romstage-y += ../common/mt6315.c mt6315.c
@@ -49,7 +49,7 @@ ramstage-y += ../common/dramc_info.c
 ramstage-y += ../common/emi.c
 ramstage-y += ../common/mcu.c mcupm.c
 ramstage-y += ../common/memory.c
-ramstage-y += ../common/mmu_operations.c ../common/mmu_cmops.c
+ramstage-y += ../common/mmu_operations.c
 ramstage-$(CONFIG_COMMONLIB_STORAGE_MMC) += ../common/msdc.c msdc.c
 ramstage-y += ../common/mt6315.c mt6315.c
 ramstage-y += ../common/mt6359p.c mt6359p.c
diff --git a/src/soc/mediatek/mt8192/Makefile.mk b/src/soc/mediatek/mt8192/Makefile.mk
index 7b88100478..ae75f13eb2 100644
--- a/src/soc/mediatek/mt8192/Makefile.mk
+++ b/src/soc/mediatek/mt8192/Makefile.mk
@@ -23,7 +23,7 @@ romstage-y += ../common/dram_init.c
 romstage-y += ../common/dramc_param.c
 romstage-y += ../common/l2c_ops.c
 romstage-y += ../common/memory.c ../common/memory_test.c
-romstage-y += ../common/mmu_operations.c ../common/mmu_cmops.c
+romstage-y += ../common/mmu_operations.c
 romstage-y += ../common/pll.c pll.c
 romstage-y += ../common/pmif.c ../common/pmif_clk.c ../common/pmif_init.c pmif_clk.c
 romstage-y += ../common/pmif_spi.c pmif_spi.c
@@ -44,7 +44,7 @@ ramstage-y += ../common/dsi.c ../common/mtk_mipi_dphy.c
 ramstage-y += ../common/l2c_ops.c
 ramstage-y += ../common/mcu.c
 ramstage-y += ../common/mcupm.c
-ramstage-y += ../common/mmu_operations.c ../common/mmu_cmops.c
+ramstage-y += ../common/mmu_operations.c
 ramstage-$(CONFIG_COMMONLIB_STORAGE_MMC) += ../common/msdc.c msdc.c
 ramstage-y += ../common/mtcmos.c mtcmos.c
 ramstage-y += ../common/pmif.c ../common/pmif_init.c
diff --git a/src/soc/mediatek/mt8195/Makefile.mk b/src/soc/mediatek/mt8195/Makefile.mk
index 35c6c63385..6a9534436d 100644
--- a/src/soc/mediatek/mt8195/Makefile.mk
+++ b/src/soc/mediatek/mt8195/Makefile.mk
@@ -26,7 +26,7 @@ romstage-y += emi.c
 romstage-y += ../common/l2c_ops.c
 romstage-y += ../common/memory.c
 romstage-y += ../common/memory_test.c
-romstage-y += ../common/mmu_operations.c ../common/mmu_cmops.c
+romstage-y += ../common/mmu_operations.c
 romstage-y += ../common/pll.c pll.c
 romstage-y += scp.c
 romstage-y += ../common/pmif.c ../common/pmif_clk.c ../common/pmif_init.c pmif_clk.c
@@ -59,7 +59,7 @@ ramstage-y += hdmi.c
 ramstage-y += ../common/l2c_ops.c
 ramstage-y += ../common/mcu.c
 ramstage-y += ../common/mcupm.c
-ramstage-y += ../common/mmu_operations.c ../common/mmu_cmops.c
+ramstage-y += ../common/mmu_operations.c
 ramstage-$(CONFIG_COMMONLIB_STORAGE_MMC) += ../common/msdc.c msdc.c
 ramstage-y += mt6360.c
 ramstage-y += ../common/mtcmos.c mtcmos.c
diff --git a/src/soc/mediatek/mt8196/Makefile.mk b/src/soc/mediatek/mt8196/Makefile.mk
index 5517b092e4..e4bb1bd523 100644
--- a/src/soc/mediatek/mt8196/Makefile.mk
+++ b/src/soc/mediatek/mt8196/Makefile.mk
@@ -37,7 +37,7 @@ romstage-y += l2c_ops.c
 romstage-y += modem_power_ctrl.c
 romstage-y += ../common/memory.c ../common/memory_type.c
 romstage-y += ../common/memory_test.c
-romstage-y += ../common/mmu_operations.c ../common/mmu_cmops.c
+romstage-y += ../common/mmu_operations.c
 romstage-y += ../common/mt6316.c mt6316.c
 romstage-y += ../common/mt6363.c mt6363.c
 romstage-y += ../common/mt6373.c mt6373.c
@@ -68,7 +68,7 @@ ramstage-y += ../common/emi.c
 ramstage-y += gpueb.c
 ramstage-y += l2c_ops.c
 ramstage-y += ../common/mcu.c mcupm.c
-ramstage-y += ../common/mmu_operations.c ../common/mmu_cmops.c
+ramstage-y += ../common/mmu_operations.c
 ramstage-$(CONFIG_PCI) += ../common/pcie.c pcie.c
 ramstage-$(CONFIG_COMMONLIB_STORAGE_MMC) += msdc.c
 ramstage-y += ../common/mt6363.c mt6363.c

From 2e92833172a94684217ea30c78d21ac32ae74a03 Mon Sep 17 00:00:00 2001
From: Paul Menzel <pmenzel@molgen.mpg.de>
Date: Wed, 8 Oct 2025 06:12:09 +0200
Subject: [PATCH 2183/3886] soc/qualcomm/common/usb/qmpv4_usb_phy: Fix delay
 value in comment to 10 ms
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

`wait_us(10000, …)` is 10 ms and not 1 ms.

Change-Id: I8b44e96f9611f081287413151c4294bcadf1ce5c
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89455
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
---
 src/soc/qualcomm/common/usb/qmpv4_usb_phy.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/soc/qualcomm/common/usb/qmpv4_usb_phy.c b/src/soc/qualcomm/common/usb/qmpv4_usb_phy.c
index 6a5d7abcb0..14a8187c01 100644
--- a/src/soc/qualcomm/common/usb/qmpv4_usb_phy.c
+++ b/src/soc/qualcomm/common/usb/qmpv4_usb_phy.c
@@ -398,7 +398,7 @@ void ss_qmp_phy_init(void)
 
 	/*
 	 * Wait for PHY initialization to be done
-	 * PCS_STATUS: wait for 1ms for PHY STATUS;
+	 * PCS_STATUS: wait for 10ms for PHY STATUS;
 	 * SW can continuously check for PHYSTATUS = 1.b0.
 	 */
 	long lock_us = wait_us(10000,

From 414f1a61dd3f4f996d4f880acf69973e53f664d5 Mon Sep 17 00:00:00 2001
From: Jeremy Compostella <jeremy.compostella@intel.com>
Date: Tue, 10 Jun 2025 17:56:23 -0700
Subject: [PATCH 2184/3886] vc/intel/fsp/fsp2_0/pantherlake: Expose Thermal
 current thresholds and mode

The changes focus on offering power state current thresholds and Thermal
Design Current (TDC) mode settings.

The Ps1Threshold, Ps2Threshold, and Ps3Threshold new fields configure
current thresholds for different power states. This allows for
fine-tuned power management by specifying current thresholds in 1/4 A
increments. These configurations can help optimize performance based on
specific current requirements for different components like IA, GT, and
SA.

The TdcMode parameter configures TDC mode based on the IRMS supported
bit from Mailbox, offering the option between iPL2 and Irms modes.

BUG=b:449662274

Change-Id: I25b6b9d2bf19ade51e39db06298ffaef98a7897e
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88043
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 .../intel/fsp/fsp2_0/pantherlake/FspmUpd.h    | 111 +++++++++++++-----
 1 file changed, 80 insertions(+), 31 deletions(-)

diff --git a/src/vendorcode/intel/fsp/fsp2_0/pantherlake/FspmUpd.h b/src/vendorcode/intel/fsp/fsp2_0/pantherlake/FspmUpd.h
index a2f8ce7572..827eec302d 100644
--- a/src/vendorcode/intel/fsp/fsp2_0/pantherlake/FspmUpd.h
+++ b/src/vendorcode/intel/fsp/fsp2_0/pantherlake/FspmUpd.h
@@ -2370,9 +2370,42 @@ typedef struct {
 **/
   UINT16                      DcLoadline[6];
 
-/** Offset 0x0896 - Reserved
+/** Offset 0x0896 - Power State 1 Threshold current
+  PS Current Threshold1, defined in 1/4 A increments. A value of 400 = 100A. Range
+  0-152, which translates to 0-38A. 0 = AUTO. [0] for IA, [1] for GT, [2] for SA,
+  [3] through [5] are Reserved.
 **/
-  UINT8                      Reserved66[116];
+  UINT16                      Ps1Threshold[6];
+
+/** Offset 0x08A2 - Power State 2 Threshold current
+  PS Current Threshold2, defined in 1/4 A increments. A value of 400 = 100A. Range
+  0-48, which translates to 0-12A. 0 = AUTO. [0] for IA, [1] for GT, [2] for SA,
+  [3] through [5] are Reserved.
+**/
+  UINT16                      Ps2Threshold[6];
+
+/** Offset 0x08AE - Power State 3 Threshold current
+  PS Current Threshold3, defined in 1/4 A increments. A value of 400 = 100A. Range
+  0-16, which translates to 0-4A. 0 = AUTO. [0] for IA, [1] for GT, [2] for SA, [3]
+  through [5] are Reserved.
+**/
+  UINT16                      Ps3Threshold[6];
+
+/** Offset 0x08BA - Reserved
+**/
+  UINT8                       Reserved66[26];
+
+/** Offset 0x08D4 - Icc Max limit
+  Voltage Regulator Current Limit (Icc Max). This value represents the Maximum instantaneous
+  current allowed at any given time. The value is represented in 1/4 A increments.
+  A value of 400 = 100A. 0 means AUTO. IA and GT, range 0-2047. SA range 0-1023.
+  [0] for IA, [1] for GT, [2] for SA, [3] through [5] are Reserved.
+**/
+  UINT16                      IccMax[6];
+
+/** Offset 0x08E0 - Reserved
+**/
+  UINT8                      Reserved67[42];
 
 /** Offset 0x090A - Thermal Design Current enable/disable
   Thermal Design Current enable/disable; <b>0: Disable</b>; 1: Enable. [0] for IA,
@@ -2382,7 +2415,7 @@ typedef struct {
 
 /** Offset 0x0910 - Reserved
 **/
-  UINT8                       Reserved67[6];
+  UINT8                       Reserved68[6];
 
 /** Offset 0x0916 - Disable Fast Slew Rate for Deep Package C States for VR domains
   This option needs to be configured to reduce acoustic noise during deeper C states.
@@ -2404,7 +2437,7 @@ typedef struct {
 
 /** Offset 0x0922 - Reserved
 **/
-  UINT8                       Reserved68[6];
+  UINT8                       Reserved69[6];
 
 /** Offset 0x0928 - Thermal Design Current time window
   Auto = 0 is default. Range is from 1ms to 448s. <b>0: Auto</b>. [0] for IA, [1]
@@ -2412,9 +2445,15 @@ typedef struct {
 **/
   UINT32                      TdcTimeWindow[6];
 
-/** Offset 0x0940 - Reserved
+/** Offset 0x0940 - TDC Mode
+  TDC Mode based on IRMS supported bit from Mailbox. <b>0: iPL2</b>; 1: Irms. [0]
+  for IA, [1] for GT, [2] for SA, [3] for atom [4]-[5] are Reserved.
 **/
-  UINT8                       Reserved69[8];
+  UINT8                       TdcMode[6];
+
+/** Offset 0x0946 - Reserved
+**/
+  UINT8                       Reserved70[2];
 
 /** Offset 0x0948 - DLVR RFI Enable
   Enable/Disable DLVR RFI frequency hopping. 0: Disable; <b>1: Enable</b>.
@@ -2422,9 +2461,19 @@ typedef struct {
 **/
   UINT8                       DlvrRfiEnable;
 
-/** Offset 0x0949 - Reserved
+/** Offset 0x0949 - Pcore VR Hysteresis time window
+  0 is default. Range of PcoreHysteresisWindow from 1ms to 50ms.
 **/
-  UINT8                       Reserved70[13];
+  UINT8                       PcoreHysteresisWindow;
+
+/** Offset 0x094A - Ecore VR Hysteresis time window
+  0 is default. Range of EcoreHysteresisWindow from 1ms to 50ms.
+**/
+  UINT8                       EcoreHysteresisWindow;
+
+/** Offset 0x094B - Reserved
+**/
+  UINT8                       Reserved71[11];
 
 /** Offset 0x0956 - VR Fast Vmode ICC Limit support
   Voltage Regulator Fast Vmode ICC Limit. A value of 400 = 100A. A value of 0 corresponds
@@ -2449,7 +2498,7 @@ typedef struct {
 
 /** Offset 0x096E - Reserved
 **/
-  UINT8                       Reserved71[28];
+  UINT8                       Reserved72[28];
 
 /** Offset 0x098A - PCH Port80 Route
   Control where the Port 80h cycles are sent, 0: LPC; 1: PCI.
@@ -2466,7 +2515,7 @@ typedef struct {
 
 /** Offset 0x098C - Reserved
 **/
-  UINT8                       Reserved72[4];
+  UINT8                       Reserved73[4];
 
 /** Offset 0x0990 - PMR Size
   Size of PMR memory buffer. 0x400000 for normal boot and 0x200000 for S3 boot
@@ -2492,7 +2541,7 @@ typedef struct {
 
 /** Offset 0x0997 - Reserved
 **/
-  UINT8                       Reserved73;
+  UINT8                       Reserved74;
 
 /** Offset 0x0998 - Base addresses for VT-d function MMIO access
   Base addresses for VT-d MMIO access per VT-d engine
@@ -2501,7 +2550,7 @@ typedef struct {
 
 /** Offset 0x09BC - Reserved
 **/
-  UINT8                       Reserved74[20];
+  UINT8                       Reserved75[20];
 
 /** Offset 0x09D0 - MMIO Size
   Size of MMIO space reserved for devices. 0(Default)=Auto, non-Zero=size in MB
@@ -2516,7 +2565,7 @@ typedef struct {
 
 /** Offset 0x09D4 - Reserved
 **/
-  UINT8                      Reserved75[36];
+  UINT8                      Reserved76[36];
 
 /** Offset 0x09F8 - Enable above 4GB MMIO resource support
   Enable/disable above 4GB MMIO resource support
@@ -2532,7 +2581,7 @@ typedef struct {
 
 /** Offset 0x09FA - Reserved
 **/
-  UINT8                       Reserved76[10];
+  UINT8                       Reserved77[10];
 
 /** Offset 0x0A04 - Enable/Disable CrashLog Device
   Enable or Disable CrashLog/Telemetry Device  0- Disable, <b>1- Enable</b>
@@ -2542,7 +2591,7 @@ typedef struct {
 
 /** Offset 0x0A08 - Reserved
 **/
-  UINT8                      Reserved77[20];
+  UINT8                      Reserved78[20];
 
 /** Offset 0x0A1C - Platform Debug Option
   Enabled Trace active: TraceHub is enabled and trace is active, blocks s0ix.\n
@@ -2559,7 +2608,7 @@ typedef struct {
 
 /** Offset 0x0A1D - Reserved
 **/
-  UINT8                       Reserved78[14];
+  UINT8                       Reserved79[14];
 
 /** Offset 0x0A2B - Program GPIOs for LFP on DDI port-A device
   0=Disabled,1(Default)=eDP, 2=MIPI DSI
@@ -2569,7 +2618,7 @@ typedef struct {
 
 /** Offset 0x0A2C - Reserved
 **/
-  UINT8                      Reserved79[2];
+  UINT8                      Reserved80[2];
 
 /** Offset 0x0A2E - Program GPIOs for LFP on DDI port-B device
   0(Default)=Disabled,1=eDP, 2=MIPI DSI
@@ -2663,7 +2712,7 @@ typedef struct {
 
 /** Offset 0x0A3D - Reserved
 **/
-  UINT8                       Reserved80[3];
+  UINT8                       Reserved81[3];
 
 /** Offset 0x0A40 - Temporary MMIO address for GMADR
   The reference code will use this as Temporary MMIO address space to access GMADR
@@ -2682,7 +2731,7 @@ typedef struct {
 
 /** Offset 0x0A50 - Reserved
 **/
-  UINT8                      Reserved81[2];
+  UINT8                      Reserved82[2];
 
 /** Offset 0x0A52 - Enable/Disable Memory Bandwidth Compression
   0=Disable, 1(Default)=Enable
@@ -2712,7 +2761,7 @@ typedef struct {
 
 /** Offset 0x0A56 - Reserved
 **/
-  UINT8                       Reserved82[2];
+  UINT8                       Reserved83[2];
 
 /** Offset 0x0A58 - Intel Graphics VBT (Video BIOS Table) Size
   Size of Internal Graphics VBT Image
@@ -2721,7 +2770,7 @@ typedef struct {
 
 /** Offset 0x0A5C - Reserved
 **/
-  UINT8                       Reserved83[4];
+  UINT8                       Reserved84[4];
 
 /** Offset 0x0A60 - Graphics Configuration Ptr
   Points to VBT
@@ -2782,7 +2831,7 @@ typedef struct {
 
 /** Offset 0x0A83 - Reserved
 **/
-  UINT8                       Reserved84[4];
+  UINT8                       Reserved85[4];
 
 /** Offset 0x0A87 - TCSS Type C Port 0
   Set TCSS Type C Port 0 Type, Options are 0=DISABLE, 1=DP_ONLY, 2=NO_TBT, 3=NO_PCIE,
@@ -2814,7 +2863,7 @@ typedef struct {
 
 /** Offset 0x0A8B - Reserved
 **/
-  UINT8                       Reserved85;
+  UINT8                       Reserved86;
 
 /** Offset 0x0A8C - TypeC port GPIO setting
   GPIO Pin number for Type C Aux orientation setting, use the GpioPad that is defined
@@ -2882,7 +2931,7 @@ typedef struct {
 
 /** Offset 0x0AC9 - Reserved
 **/
-  UINT8                       Reserved86;
+  UINT8                       Reserved87;
 
 /** Offset 0x0ACA - DLL Weak Lock Support
   Enables/Disable DLL Weak Lock Support
@@ -2892,7 +2941,7 @@ typedef struct {
 
 /** Offset 0x0ACB - Reserved
 **/
-  UINT8                       Reserved87;
+  UINT8                       Reserved88;
 
 /** Offset 0x0ACC - Rx DQS Delay Comp Support
   Enables/Disable Rx DQS Delay Comp Support
@@ -2902,7 +2951,7 @@ typedef struct {
 
 /** Offset 0x0ACD - Reserved
 **/
-  UINT8                       Reserved88[2];
+  UINT8                       Reserved89[2];
 
 /** Offset 0x0ACF - Mrc Failure On Unsupported Dimm
   Enables/Disable Mrc Failure On Unsupported Dimm
@@ -2912,7 +2961,7 @@ typedef struct {
 
 /** Offset 0x0AD0 - Reserved
 **/
-  UINT8                      Reserved89[4];
+  UINT8                      Reserved90[4];
 
 /** Offset 0x0AD4 - DynamicMemoryBoost
   Enable/Disable Dynamic Memory Boost Feature. Only valid if SpdProfileSelected is
@@ -2930,7 +2979,7 @@ typedef struct {
 
 /** Offset 0x0ADC - Reserved
 **/
-  UINT8                      Reserved90[9];
+  UINT8                      Reserved91[9];
 
 /** Offset 0x0AE5 - Vref Offset
   Offset to be applied to DDRDATACH0_CR_DDRCRDATAOFFSETTRAIN.VrefOffset
@@ -2941,7 +2990,7 @@ typedef struct {
 
 /** Offset 0x0AE6 - Reserved
 **/
-  UINT8                       Reserved91[2];
+  UINT8                       Reserved92[2];
 
 /** Offset 0x0AE8 - tRRSG Delta
   Delay between Read-to-Read commands in the same Bank Group. 0 - Auto. Signed TAT
@@ -3057,7 +3106,7 @@ typedef struct {
 
 /** Offset 0x0AF8 - Reserved
 **/
-  UINT8                       Reserved92[41];
+  UINT8                       Reserved93[41];
 
 /** Offset 0x0B21 - Channel to CKD QCK Mapping
   Specify Channel to CKD QCK Mapping for CH0D0/CH0D1/CH1D0&CH1D1
@@ -3071,7 +3120,7 @@ typedef struct {
 
 /** Offset 0x0B31 - Reserved
 **/
-  UINT8                       Reserved93[55];
+  UINT8                       Reserved94[55];
 } FSP_M_CONFIG;
 
 /** Fsp M UPD Configuration

From 341b108a71dd1089f33187ec1615d80f270a6a86 Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Tue, 7 Oct 2025 09:00:28 +0100
Subject: [PATCH 2185/3886] mb/starlabs/starfighter: Add missing GPP_A5
 definition

Change-Id: I1969bb993ac7af16054b6b1cc4f1d22d7036d184
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89441
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/starlabs/starfighter/variants/rpl/gpio.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/src/mainboard/starlabs/starfighter/variants/rpl/gpio.c b/src/mainboard/starlabs/starfighter/variants/rpl/gpio.c
index 0195ac9033..1b66c49515 100644
--- a/src/mainboard/starlabs/starfighter/variants/rpl/gpio.c
+++ b/src/mainboard/starlabs/starfighter/variants/rpl/gpio.c
@@ -116,6 +116,7 @@ const struct pad_config gpio_table[] = {
 	PAD_NC(GPD10, NONE),
 	PAD_NC(GPD11, NONE),
 
+	PAD_NC(GPP_A5, NONE),
 	PAD_NC(GPP_A6, NONE),
 	PAD_NC(GPP_A7, NONE),
 	PAD_NC(GPP_A8, NONE),

From e59c5abd13e6be052281a77c076037bc85de7084 Mon Sep 17 00:00:00 2001
From: Yu-Ping Wu <yupingso@chromium.org>
Date: Fri, 3 Oct 2025 09:04:30 +0800
Subject: [PATCH 2186/3886] ec/google/chromeec: Add
 EC_GOOGLE_CHROMEEC_FW_CONFIG_FROM_UFSC

Introduce a Kconfig option EC_GOOGLE_CHROMEEC_FW_CONFIG_FROM_UFSC for
reading firmware configuration from Unified Firmware and Second-source
Config (UFSC) [1] from EC CBI. As the UFSC already includes both the
32-bit FW_CONFIG and 32-bit SSFC, this option is incompatible with
EC_GOOGLE_CHROMEEC_INCLUDE_SSFC_IN_FW_CONFIG.

Also check the size of the data read from CBI.

[1] https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/6974727

BUG=b:448300592
TEST=emerge=skywalker coreboot
BRANCH=none

Change-Id: I2f686838d2f7a6f3eec3bd5224f89389340f7471
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89404
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
---
 src/ec/google/chromeec/Kconfig |  8 +++++
 src/ec/google/chromeec/ec.c    | 60 ++++++++++++++++++++--------------
 2 files changed, 44 insertions(+), 24 deletions(-)

diff --git a/src/ec/google/chromeec/Kconfig b/src/ec/google/chromeec/Kconfig
index fbd4758e71..9213e24302 100644
--- a/src/ec/google/chromeec/Kconfig
+++ b/src/ec/google/chromeec/Kconfig
@@ -185,8 +185,16 @@ config EC_GOOGLE_CHROMEEC_SWITCHES
 	  Enable support for ChromeOS mode switches provided by the ChromeOS
 	  EC.
 
+config EC_GOOGLE_CHROMEEC_FW_CONFIG_FROM_UFSC
+	depends on FW_CONFIG_SOURCE_CHROMEEC_CBI
+	bool
+	help
+	  Get firmware configuration from Unified Firmware and Second-source
+	  Config (UFSC) in CBI.
+
 config EC_GOOGLE_CHROMEEC_INCLUDE_SSFC_IN_FW_CONFIG
 	depends on FW_CONFIG_SOURCE_CHROMEEC_CBI
+	depends on !EC_GOOGLE_CHROMEEC_FW_CONFIG_FROM_UFSC
 	bool
 	help
 	  Fetch Second Source Factory Cache from CBI EEPROM and add it in the most significant
diff --git a/src/ec/google/chromeec/ec.c b/src/ec/google/chromeec/ec.c
index eeef4341f3..acba0dfefb 100644
--- a/src/ec/google/chromeec/ec.c
+++ b/src/ec/google/chromeec/ec.c
@@ -1,5 +1,6 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
+#include <stdbool.h>
 #include <stdint.h>
 #include <string.h>
 #include <assert.h>
@@ -666,31 +667,38 @@ void google_chromeec_ap_poweroff(void)
 	halt();
 }
 
-static int cbi_get_uint32(uint32_t *id, uint32_t tag)
+static int cbi_read(void *buf, size_t bufsize, uint32_t tag, bool check_size)
 {
 	struct ec_params_get_cbi params = {
 		.tag = tag,
 	};
-	uint32_t r = 0;
 	struct chromeec_command cmd = {
 		.cmd_code = EC_CMD_GET_CROS_BOARD_INFO,
 		.cmd_version = 0,
 		.cmd_data_in = &params,
-		.cmd_data_out = &r,
+		.cmd_data_out = buf,
 		.cmd_size_in = sizeof(params),
-		.cmd_size_out = sizeof(r),
-		.cmd_dev_index = 0,
+		.cmd_size_out = bufsize,
 	};
-	int rv;
 
-	rv = google_chromeec_command(&cmd);
-	if (rv != 0)
+	int rv = google_chromeec_command(&cmd);
+	if (rv)
 		return rv;
 
-	*id = r;
+	if (check_size && cmd.cmd_size_out != bufsize) {
+		printk(BIOS_ERR, "Wrong out size for CBI tag %d: expected %zu, got %u\n",
+		       tag, bufsize, cmd.cmd_size_out);
+		return -1;
+	}
+
 	return 0;
 }
 
+static int cbi_get_uint32(uint32_t *id, uint32_t tag)
+{
+	return cbi_read(id, sizeof(*id), tag, true);
+}
+
 int google_chromeec_cbi_get_sku_id(uint32_t *id)
 {
 	return cbi_get_uint32(id, CBI_TAG_SKU_ID);
@@ -711,8 +719,25 @@ uint32_t google_chromeec_get_board_sku(void)
 
 int google_chromeec_cbi_get_fw_config(uint64_t *fw_config)
 {
+	int rv;
 	uint32_t config;
 
+	_Static_assert(!CONFIG(EC_GOOGLE_CHROMEEC_FW_CONFIG_FROM_UFSC) ||
+		       !CONFIG(EC_GOOGLE_CHROMEEC_INCLUDE_SSFC_IN_FW_CONFIG),
+		       "EC_GOOGLE_CHROMEEC_FW_CONFIG_FROM_UFSC and "
+		       "EC_GOOGLE_CHROMEEC_INCLUDE_SSFC_IN_FW_CONFIG are conflicting");
+
+	if (CONFIG(EC_GOOGLE_CHROMEEC_FW_CONFIG_FROM_UFSC)) {
+		struct cbi_ufsc ufsc;
+		rv = cbi_read(&ufsc, sizeof(ufsc), CBI_TAG_UFSC, true);
+		if (rv)
+			return rv;
+		_Static_assert(sizeof(*fw_config) == sizeof(ufsc.data[0]) * 2,
+			       "Wrong UFSC size");
+		*fw_config = ufsc.data[0] | ((uint64_t)ufsc.data[1] << 32);
+		return 0;
+	}
+
 	if (cbi_get_uint32(&config, CBI_TAG_FW_CONFIG))
 		return -1;
 
@@ -760,27 +785,14 @@ bool google_chromeec_get_ucsi_enabled(void)
 
 static int cbi_get_string(char *buf, size_t bufsize, uint32_t tag)
 {
-	struct ec_params_get_cbi params = {
-		.tag = tag,
-	};
-	struct chromeec_command cmd = {
-		.cmd_code = EC_CMD_GET_CROS_BOARD_INFO,
-		.cmd_version = 0,
-		.cmd_data_in = &params,
-		.cmd_data_out = buf,
-		.cmd_size_in = sizeof(params),
-		.cmd_size_out = bufsize,
-	};
 	int rv;
 
-	rv = google_chromeec_command(&cmd);
-	if (rv != 0)
-		return rv;
+	rv = cbi_read(buf, bufsize, tag, false);
 
 	/* Ensure NUL termination. */
 	buf[bufsize - 1] = '\0';
 
-	return 0;
+	return rv;
 }
 
 int google_chromeec_cbi_get_dram_part_num(char *buf, size_t bufsize)

From 738fd2efc9345a498cd701d89495822fada906e6 Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Sun, 5 Oct 2025 15:08:17 -0500
Subject: [PATCH 2187/3886] util/chromeos/extract_blobs: Add support for
 command line params

Add support for taking the ifdtool platform parameter via the cmd
line, as well as the output directory. Add double quotes around
variables as needed. Add help output describing new parameter options.

TEST=run script against images from skl, adl, and mtl platforms.
Verify no warning from ifdtool that platform is unknown.

Change-Id: I4a27c9876bf639579b791c894b2cbfdae7ab63c1
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89452
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
---
 util/chromeos/extract_blobs.sh | 135 ++++++++++++++++++++++++++-------
 1 file changed, 106 insertions(+), 29 deletions(-)

diff --git a/util/chromeos/extract_blobs.sh b/util/chromeos/extract_blobs.sh
index ca0bdeeee6..253b6eefdb 100755
--- a/util/chromeos/extract_blobs.sh
+++ b/util/chromeos/extract_blobs.sh
@@ -2,21 +2,89 @@
 #
 # SPDX-License-Identifier: GPL-2.0-only
 
-if [ ! -f "$1" ]; then
-	echo "Error: You must provide a valid filename"
+# Default values
+DIR=""
+PLATFORM=""
+
+# Parse command line arguments
+while [[ $# -gt 0 ]]; do
+	case $1 in
+		-o|--output)
+			DIR="$2"
+			shift 2
+			;;
+		-p|--platform)
+			PLATFORM="$2"
+			shift 2
+			;;
+		-h|--help)
+			echo "Usage: $0 [OPTIONS] IMAGE_FILE"
+			echo ""
+			echo "Extract blobs from a coreboot image"
+			echo ""
+			echo "OPTIONS:"
+			echo "  -o, --output DIR     Output directory (default: $IMAGE-blobs)"
+			echo "  -p, --platform PLAT  Platform for ifdtool (see platforms below)"
+			echo "  -h, --help          Show this help message"
+			echo ""
+			echo "AVAILABLE PLATFORMS:"
+			echo "  adl     - Alder Lake"
+			echo "  aplk    - Apollo Lake"
+			echo "  cnl     - Cannon Lake"
+			echo "  lbg     - Lewisburg PCH"
+			echo "  dnv     - Denverton"
+			echo "  ehl     - Elkhart Lake"
+			echo "  glk     - Gemini Lake"
+			echo "  icl     - Ice Lake"
+			echo "  ifd2    - IFDv2 Platform"
+			echo "  jsl     - Jasper Lake"
+			echo "  mtl     - Meteor Lake"
+			echo "  sklkbl  - Sky Lake/Kaby Lake"
+			echo "  tgl     - Tiger Lake"
+			echo "  wbg     - Wellsburg"
+			echo ""
+			echo "EXAMPLES:"
+			echo "  $0 -o ./blobs -p mtl bios.bin"
+			echo "  $0 -p tgl image.bin"
+			echo "  $0 -o custom-dir image.bin"
+			exit 0
+			;;
+		-*)
+			echo "Error: Unknown option $1"
+			echo "Use -h or --help for usage information"
+			exit 1
+			;;
+		*)
+			if [ -z "$IMAGE" ]; then
+				IMAGE="$1"
+			else
+				echo "Error: Multiple image files specified"
+				exit 1
+			fi
+			shift
+			;;
+	esac
+done
+
+# Check if image file is provided
+if [ -z "$IMAGE" ]; then
+	echo "Error: You must provide an image file"
+	echo "Use -h or --help for usage information"
 	exit 1
 fi
 
-IMAGE=$1
-
-if [[ "$2" = "" ]]; then
-	# create new dir '$IMAGE-blobs' (less file extension)
-	DIR=$(basename $IMAGE)
-	DIR="${DIR%.*}-blobs"
-else
-	DIR=$2
+if [ ! -f "$IMAGE" ]; then
+	echo "Error: Image file '$IMAGE' does not exist"
+	exit 1
 fi
-mkdir -p $DIR
+
+# Set default output directory if not specified
+if [[ "$DIR" = "" ]]; then
+	# create new dir '$IMAGE-blobs' (less file extension)
+	DIR=$(basename "$IMAGE")
+	DIR="${DIR%.*}-blobs"
+fi
+mkdir -p "$DIR"
 
 if [ -f ./cbfstool ]; then
 	CBFSTOOL="./cbfstool"
@@ -41,12 +109,12 @@ fi
 # ensure valid coreboot image / get list of CBFS contents
 # try using RW_MAIN_A region first as it may contain newer
 # files / files not present in the COREBOOT region
-if $CBFSTOOL $IMAGE print -r FW_MAIN_A >$DIR/cbfs.txt 2>/dev/null; then
+if $CBFSTOOL "$IMAGE" print -r FW_MAIN_A >"$DIR"/cbfs.txt 2>/dev/null; then
 	REGION="FW_MAIN_A"
-elif $CBFSTOOL $IMAGE print -r COREBOOT >$DIR/cbfs.txt; then
+elif $CBFSTOOL "$IMAGE" print -r COREBOOT >"$DIR"/cbfs.txt 2>/dev/null; then
 	# use COREBOOT region
 	REGION="COREBOOT"
-elif $CBFSTOOL $IMAGE print -r BOOT_STUB >$DIR/cbfs.txt; then
+elif $CBFSTOOL "$IMAGE" print -r BOOT_STUB >"$DIR"/cbfs.txt 2>/dev/null; then
 	# use BOOT_STUB region
 	REGION="BOOT_STUB"
 else
@@ -59,68 +127,77 @@ echo "Extracting blobs from region $REGION..."
 echo ""
 
 # extract flash regions
-if ! $IFDTOOL -x $IMAGE >/dev/null; then
+IFDTOOL_ARGS="-x $IMAGE"
+if [ -n "$PLATFORM" ]; then
+	IFDTOOL_ARGS="-p $PLATFORM $IFDTOOL_ARGS"
+fi
+
+if ! $IFDTOOL $IFDTOOL_ARGS >/dev/null; then
 	echo "Error reading flash descriptor/extracting flash regions"
 	exit 1
 fi
 # rename to normal convention; drop unused regions
-mv flashregion_0_flashdescriptor.bin $DIR/flashdescriptor.bin
-[ -f flashregion_2_intel_me.bin ] && mv flashregion_2_intel_me.bin $DIR/me.bin
+mv flashregion_0_flashdescriptor.bin "$DIR"/flashdescriptor.bin
+[ -f flashregion_2_intel_me.bin ] && mv flashregion_2_intel_me.bin "$DIR"/me.bin
 rm flashregion_*.bin
 
 # extract microcode
-$CBFSTOOL $IMAGE extract -r $REGION -n cpu_microcode_blob.bin -f $DIR/cpu_microcode_blob.bin
+if grep -q "cpu_microcode_blob.bin" "$DIR"/cbfs.txt; then
+	$CBFSTOOL "$IMAGE" extract -r $REGION -n cpu_microcode_blob.bin -f "$DIR"/cpu_microcode_blob.bin
+else
+	echo "Note: cpu_microcode_blob.bin not found in CBFS, skipping..."
+fi
 
 # extract VGA BIOS
 VGA=$(grep pci $DIR/cbfs.txt | cut -f1 -d\ )
 if [ "$VGA" != "" ]; then
-	$CBFSTOOL $IMAGE extract -r $REGION -n $VGA -f $DIR/vgabios.bin
+	$CBFSTOOL "$IMAGE" extract -r $REGION -n "$VGA" -f "$DIR/vgabios.bin"
 fi
 
 # extract MRC.bin
 MRC=$(grep mrc.bin $DIR/cbfs.txt | cut -f1 -d\ )
 if [ "$MRC" != "" ]; then
-	$CBFSTOOL $IMAGE extract -r $REGION -n "$MRC" -f "$DIR/$MRC"
+	$CBFSTOOL "$IMAGE" extract -r $REGION -n "$MRC" -f "$DIR/$MRC"
 fi
 
 # extract refcode
 REF=$(grep refcode $DIR/cbfs.txt | cut -f1 -d\ )
 if [ "$REF" != "" ]; then
-	$CBFSTOOL $IMAGE extract -r $REGION -n fallback/refcode -f "$DIR/refcode.elf" -m x86
+	$CBFSTOOL "$IMAGE" extract -r $REGION -n fallback/refcode -f "$DIR/refcode.elf" -m x86
 fi
 
 # extract FSP blobs
 for FSP in $(grep fsp $DIR/cbfs.txt | cut -f1 -d\ ); do
-	$CBFSTOOL $IMAGE extract -r $REGION -n $FSP -f $DIR/$FSP
+	$CBFSTOOL "$IMAGE" extract -r $REGION -n $FSP -f "$DIR/$FSP"
 done
 
 # extract audio blobs
 for AUD in $(grep -e "-2ch-" -e "-4ch-" $DIR/cbfs.txt | cut -f1 -d\ ); do
-	$CBFSTOOL $IMAGE extract -r $REGION -n $AUD -f $DIR/$AUD
+	$CBFSTOOL "$IMAGE" extract -r $REGION -n $AUD -f "$DIR"/"$AUD"
 done
 
 # extract VBTs
 for VBT in $(grep vbt $DIR/cbfs.txt | cut -f1 -d\ ); do
-	$CBFSTOOL $IMAGE extract -r $REGION -n $VBT -f $DIR/$VBT
+	$CBFSTOOL "$IMAGE" extract -r $REGION -n "$VBT" -f "$DIR"/"$VBT"
 done
 
 # extract IFWI
-IFWI=$(cbfstool $IMAGE layout -w | grep IFWI)
+IFWI=$(cbfstool "$IMAGE" layout -w | grep IFWI)
 if [ "$IFWI" != "" ]; then
-	$CBFSTOOL $IMAGE read -r IFWI -f $DIR/ifwi.bin
+	$CBFSTOOL "$IMAGE" read -r IFWI -f "$DIR"/ifwi.bin
 fi
 
 # generate hashes
 (
-	cd $DIR
+	cd "$DIR"
 	: >hashes.txt
 	for FILE in $(ls *.{bin,elf} 2>/dev/null); do
-		sha256sum $FILE >>hashes.txt
+		sha256sum "$FILE" >>hashes.txt
 	done
 )
 
 # a little housekeeping
-rm $DIR/cbfs.txt
+rm "$DIR"/cbfs.txt
 
 echo ""
 echo "All done"

From b4b6c3aa5565d9144534241aa67adb530099d392 Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Sun, 5 Oct 2025 18:53:57 -0500
Subject: [PATCH 2188/3886] mb/google/brya/var/{marasov,mithrax,omnigul}: Add
 SOF chip driver entries

These boards all use PDM1 for the microphone topology, and so need to
override the baseboard default.

TEST=boot Win11 on omnigul, verify speakers/microphone work with
Coolstar's drivers.

Change-Id: I55a5886fc02a83640392854cd7132aa811dac6f3
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89454
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 .../google/brya/variants/marasov/overridetree.cb          | 8 ++++++++
 .../google/brya/variants/mithrax/overridetree.cb          | 6 ++++++
 .../google/brya/variants/omnigul/overridetree.cb          | 8 ++++++++
 3 files changed, 22 insertions(+)

diff --git a/src/mainboard/google/brya/variants/marasov/overridetree.cb b/src/mainboard/google/brya/variants/marasov/overridetree.cb
index 392fbdd715..0718ef49ff 100644
--- a/src/mainboard/google/brya/variants/marasov/overridetree.cb
+++ b/src/mainboard/google/brya/variants/marasov/overridetree.cb
@@ -474,5 +474,13 @@ chip soc/intel/alderlake
 				end
 			end
 		end
+		device ref hda on
+			chip drivers/sof
+				register "spkr_tplg" = "rt1019"
+				register "jack_tplg" = "rt5682"
+				register "mic_tplg" = "_2ch_pdm1"
+				device generic 0 on end
+			end
+		end
 	end
 end
diff --git a/src/mainboard/google/brya/variants/mithrax/overridetree.cb b/src/mainboard/google/brya/variants/mithrax/overridetree.cb
index 4c1a359161..f455ce740d 100644
--- a/src/mainboard/google/brya/variants/mithrax/overridetree.cb
+++ b/src/mainboard/google/brya/variants/mithrax/overridetree.cb
@@ -304,6 +304,12 @@ chip soc/intel/alderlake
 				register "sdmode_delay" = "5"
 				device generic 0 on end
 			end
+			chip drivers/sof
+				register "spkr_tplg" = "rt1019"
+				register "jack_tplg" = "rt5682"
+				register "mic_tplg" = "_2ch_pdm1"
+				device generic 0 on end
+			end
 		end
 		device ref pch_espi on
 			chip ec/google/chromeec
diff --git a/src/mainboard/google/brya/variants/omnigul/overridetree.cb b/src/mainboard/google/brya/variants/omnigul/overridetree.cb
index 20e3d41064..cd580f2a09 100644
--- a/src/mainboard/google/brya/variants/omnigul/overridetree.cb
+++ b/src/mainboard/google/brya/variants/omnigul/overridetree.cb
@@ -465,5 +465,13 @@ chip soc/intel/alderlake
 				end
 			end
 		end
+		device ref hda on
+			chip drivers/sof
+				register "spkr_tplg" = "max98360a"
+				register "jack_tplg" = "rt5682"
+				register "mic_tplg" = "_2ch_pdm1"
+				device generic 0 on end
+			end
+		end
 	end
 end

From 1af0497c123a29eafc447c70fb09e5ac9b3a1a58 Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Sun, 5 Oct 2025 18:51:09 -0500
Subject: [PATCH 2189/3886] mb/google/dedede: Fix MAINBOARD_FAMILY conditional

Mainboard family is set based on the baseboard.

TEST=build/boot google/galtic, verify mainboard family set correctly
in SMBIOS.

Change-Id: Ifb5335c7dad43e8a75dd462a121d2eb711c51ccc
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89453
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/google/dedede/Kconfig | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/mainboard/google/dedede/Kconfig b/src/mainboard/google/dedede/Kconfig
index 19dd260f4b..57b7c05720 100644
--- a/src/mainboard/google/dedede/Kconfig
+++ b/src/mainboard/google/dedede/Kconfig
@@ -313,7 +313,7 @@ config MAINBOARD_DIR
 
 config MAINBOARD_FAMILY
 	string
-	default "Google_Dedede" if BOARD_GOOGLE_DEDEDE
+	default "Google_Dedede" if BOARD_GOOGLE_BASEBOARD_DEDEDE
 
 config MAINBOARD_PART_NUMBER
 	default "Beadrix" if BOARD_GOOGLE_BEADRIX

From f47e6c39050b40bcfc4e4e51ec0073a73d1b484b Mon Sep 17 00:00:00 2001
From: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Date: Fri, 10 Oct 2025 08:56:01 +0900
Subject: [PATCH 2190/3886] MAINTAINERS: Fix typo "copperlake_sp" to
 "cooperlake_sp"

Change-Id: I020878dc8bfbec3a3bacabc1070b119f7a61ab0e
Signed-off-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89507
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
---
 MAINTAINERS | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/MAINTAINERS b/MAINTAINERS
index dddfa099a8..e87b4cd683 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -968,7 +968,7 @@ M:	Lean Sheng Tan <sheng.tan@9elements.com>
 S:	Supported
 F:	src/soc/intel/xeon_sp/
 F:	src/vendorcode/intel/fsp/fsp2_0/skylake_sp/
-F:	src/vendorcode/intel/fsp/fsp2_0/copperlake_sp/
+F:	src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/
 F:	src/vendorcode/intel/fsp/fsp2_0/sapphirerapids_sp/
 F:	src/vendorcode/intel/fsp/fsp2_0/graniterapids/
 

From ffa262db5942e72e91d1e73efc96e6d839576467 Mon Sep 17 00:00:00 2001
From: Daniel Maslowski <info@orangecms.org>
Date: Wed, 8 Oct 2025 20:41:03 +0200
Subject: [PATCH 2191/3886] Documentation/FIT: reference archived copy of Intel
 TXT lab handout

The document is no longer accessible at the original URL.

Change-Id: I9601b3fb9a86796dafd742961d3d130fb735804e
Signed-off-by: Daniel Maslowski <info@orangecms.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89463
Reviewed-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 Documentation/soc/intel/fit.md | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/Documentation/soc/intel/fit.md b/Documentation/soc/intel/fit.md
index b7dbc5f8bc..5e91df566e 100644
--- a/Documentation/soc/intel/fit.md
+++ b/Documentation/soc/intel/fit.md
@@ -56,5 +56,5 @@ execution of the IA32 reset vector happens.
 
 ## References
 
-* [Intel TXT LAB handout](https://downloadmirror.intel.com/18931/eng/Intel%20TXT%20LAB%20Handout.pdf)
+* [Intel TXT LAB handout](https://web.archive.org/web/20170830010916/http://downloadmirror.intel.com/18931/eng/Intel%20TXT%20LAB%20Handout.pdf)
 * [FIT BIOS specification](https://www.intel.com/content/dam/www/public/us/en/documents/guides/fit-bios-specification.pdf)

From 150647a2fb7e20bc767019ae0e1492d54e2de121 Mon Sep 17 00:00:00 2001
From: Varun Upadhyay <varun.upadhyay@intel.com>
Date: Mon, 6 Oct 2025 00:05:38 +0530
Subject: [PATCH 2192/3886] ec/google/chromeec: Fix ACPI _CRS method generation
 for LPC memory range

Enable _CRS method when EC_GOOGLE_CHROMEEC_LPC_GENERIC_MEMORY_RANGE is
configured, even without EC sync IRQ support.

Previously, the _CRS method was only generated if EC_ENABLE_SYNC_IRQ or
EC_ENABLE_SYNC_IRQ_GPIO was defined, causing LPC generic memory range
configuration to be skipped on boards that don't use EC sync IRQ which
will results in no communication between kernel and EC.

This change ensures LPC memory range resources are properly exposed
in ACPI considering the hardware limitations where the EC sync IRQ GPIO
is not available for boards using LPC_GENERIC_MEMORY_RANGE.

BUG=437459757
TEST=Build and verify EC LPC memory range is configured in ACPI tables
on boards with EC_GOOGLE_CHROMEEC_LPC_GENERIC_MEMORY_RANGE enabled
by dumping ssdt tables and also verify 'ectool version' cmd.

ectool version
RO version:    ojal-0.0.0-2db24f9+
RW version:    ojal-0.0.0-2db24f9+

Change-Id: If63dd631029d2756451fad71a5556bc0b23f507d
Signed-off-by: Varun Upadhyay <varun.upadhyay@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89420
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/ec/google/chromeec/acpi/cros_ec.asl | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/src/ec/google/chromeec/acpi/cros_ec.asl b/src/ec/google/chromeec/acpi/cros_ec.asl
index 9cf1f66fb2..f29ca14efc 100644
--- a/src/ec/google/chromeec/acpi/cros_ec.asl
+++ b/src/ec/google/chromeec/acpi/cros_ec.asl
@@ -23,7 +23,8 @@ Device (CREC)
 	#define EC_SYNC_SHARE_TYPE Exclusive
 #endif
 
-#if defined(EC_ENABLE_SYNC_IRQ) || defined(EC_ENABLE_SYNC_IRQ_GPIO)
+#if defined(EC_ENABLE_SYNC_IRQ) || defined(EC_ENABLE_SYNC_IRQ_GPIO) || \
+CONFIG(EC_GOOGLE_CHROMEEC_LPC_GENERIC_MEMORY_RANGE)
 	Method (_CRS, 0x0, NotSerialized)
 	{
 		Name (RBUF, ResourceTemplate()

From 1580346fa764afa6d6d030b9af2c6d62827a5cb1 Mon Sep 17 00:00:00 2001
From: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
Date: Thu, 9 Oct 2025 09:26:43 +0800
Subject: [PATCH 2193/3886] mb/google/fatcat/var/moonstone: correct the Kconfig
 settting

Correct the Kconfig setting to moonstone, and the compiler condition
in baseboard/gpio.h

BUG=none
TEST=emerge-fatcat coreboot chromeos-bootimage

Change-Id: I7cb794912001bf4fe0d35900fe843bf275fb77e7
Signed-off-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89466
Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
---
 src/mainboard/google/fatcat/Kconfig                         | 6 +++++-
 .../variants/baseboard/fatcat/include/baseboard/gpio.h      | 5 +++++
 2 files changed, 10 insertions(+), 1 deletion(-)

diff --git a/src/mainboard/google/fatcat/Kconfig b/src/mainboard/google/fatcat/Kconfig
index f02925916d..01a1c7a767 100644
--- a/src/mainboard/google/fatcat/Kconfig
+++ b/src/mainboard/google/fatcat/Kconfig
@@ -143,7 +143,11 @@ config BOARD_GOOGLE_LAPIS
 	select MAINBOARD_HAS_GOOGLE_STRAUSS_KEYBOARD
 
 config BOARD_GOOGLE_MOONSTONE
-	select BOARD_GOOGLE_MODEL_KINMEN
+	select BOARD_GOOGLE_BASEBOARD_FATCAT
+	select DRIVERS_SOUNDWIRE_ALC1320
+	select FSP_UGOP_EARLY_SIGN_OF_LIFE
+	select HAVE_SLP_S0_GATE
+	select MAINBOARD_HAS_GOOGLE_STRAUSS_KEYBOARD
 
 if BOARD_GOOGLE_FATCAT_COMMON
 
diff --git a/src/mainboard/google/fatcat/variants/baseboard/fatcat/include/baseboard/gpio.h b/src/mainboard/google/fatcat/variants/baseboard/fatcat/include/baseboard/gpio.h
index beffed62a1..d3ec2fdb6f 100644
--- a/src/mainboard/google/fatcat/variants/baseboard/fatcat/include/baseboard/gpio.h
+++ b/src/mainboard/google/fatcat/variants/baseboard/fatcat/include/baseboard/gpio.h
@@ -42,6 +42,11 @@
  #define GPIO_PCH_WP	GPP_D02
 /* Used to gate SoC's SLP_S0# signal */
 #define GPIO_SLP_S0_GATE	GPP_V17
+#elif CONFIG(BOARD_GOOGLE_MOONSTONE)
+ #define EC_SYNC_IRQ	GPP_E07_IRQ
+ #define GPIO_PCH_WP	GPP_D02
+/* Used to gate SoC's SLP_S0# signal */
+#define GPIO_SLP_S0_GATE	GPP_V17
 #endif
 
 #endif /* __BASEBOARD_GPIO_H__ */

From 24bfeb154e701ae71831f9e31b5fe19a675b5865 Mon Sep 17 00:00:00 2001
From: David Wu <david_wu@quanta.corp-partner.google.com>
Date: Thu, 9 Oct 2025 08:58:16 +0800
Subject: [PATCH 2194/3886] mb/google/fatcat/var/moonstone: Add focaltech
 touchscreen support

This change adds the necessary configuration for the focaltech
touchscreen (FTSC1000) device, connected to I2C bus 38.

It includes settings for:
* HID descriptor
* Device description
* IRQ configuration
* Detection
* Reset and enable GPIOs with their respective delays
* Power resource handling
* HID descriptor register offset

BUG=b:442964901
TEST=emerge-fatcat coreboot and focaltech touchscreen can work well.

Change-Id: I7fb2f8b3c4ceb9d4bc7471d7eef23b0a18dca78a
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89465
Reviewed-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 .../fatcat/variants/moonstone/overridetree.cb      | 14 ++++++++++++++
 1 file changed, 14 insertions(+)

diff --git a/src/mainboard/google/fatcat/variants/moonstone/overridetree.cb b/src/mainboard/google/fatcat/variants/moonstone/overridetree.cb
index c1ed2a9400..9c7320018e 100644
--- a/src/mainboard/google/fatcat/variants/moonstone/overridetree.cb
+++ b/src/mainboard/google/fatcat/variants/moonstone/overridetree.cb
@@ -351,6 +351,20 @@ chip soc/intel/pantherlake
 				register "hid_desc_reg_offset" = "0x01"
 				device i2c 0x10 on end
 			end
+			chip drivers/i2c/hid
+				register "generic.hid" = ""FTSC1000""
+				register "generic.desc" = ""Focal Touchscreen""
+				register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_F18_IRQ)"
+				register "generic.detect" = "1"
+				register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_F16)"
+				register "generic.reset_delay_ms" = "20"
+				register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_F08)"
+				register "generic.enable_delay_ms" = "6"
+				register "generic.has_power_resource" = "1"
+				register "generic.use_gpio_for_status" = "true"
+				register "hid_desc_reg_offset" = "0x01"
+				device i2c 0x38 on end
+			end
 		end # I2C5
 		device ref gspi0 on
 			probe FPMCU FP_SPI

From f5d1505c6baef640b28ef2ac69de2c5c1e833e0d Mon Sep 17 00:00:00 2001
From: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
Date: Thu, 9 Oct 2025 11:16:04 +0800
Subject: [PATCH 2195/3886] mb/google/fatcat/var/moonstone: Add Elan touchpad
 support

Add the Elan touchpad configuration for moonstone AVL.

BUG=b:442964901
TEST=build firwmare and check the touchpad can work well in ALOS.
     cat /sys/bus/i2c/devices/i2c-12/i2c-ELAN0000\:00/name
     i2cdetect -y -r 12 -> 0x15 = UU

Change-Id: Ie105906fb54383dbf91513f81ab933653162ad4e
Signed-off-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89467
Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-by: Pranava Y N <pranavayn@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 .../google/fatcat/variants/moonstone/overridetree.cb      | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/src/mainboard/google/fatcat/variants/moonstone/overridetree.cb b/src/mainboard/google/fatcat/variants/moonstone/overridetree.cb
index 9c7320018e..535d0a902b 100644
--- a/src/mainboard/google/fatcat/variants/moonstone/overridetree.cb
+++ b/src/mainboard/google/fatcat/variants/moonstone/overridetree.cb
@@ -312,6 +312,14 @@ chip soc/intel/pantherlake
 			end
 		end # I2C3
 		device ref i2c4 on
+			chip drivers/i2c/generic
+				register "hid" = ""ELAN0000""
+				register "desc" = ""ELAN Touchpad""
+				register "irq" = "ACPI_IRQ_WAKE_EDGE_LOW(GPP_E18_IRQ)"
+				register "wake" = "GPE0_DW2_18"
+				register "detect" = "1"
+				device i2c 15 on end
+			end
 			chip drivers/i2c/hid
 				register "generic.hid" = ""PIXA2305""
 				register "generic.desc" = ""PIXA Touchpad""

From 0965bb9f68bc95309a6cfd9a42f8ed1d19fe6805 Mon Sep 17 00:00:00 2001
From: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Date: Fri, 10 Oct 2025 08:39:31 +0900
Subject: [PATCH 2196/3886] MAINTAINERS: Remove non-existant mainboards

These mainboards were removed in the following commits:
  - e56f0c7cab77 ("mb/*/*: Remove AMD FAMILY15TN boards")
  - 6baee3d28729 ("mb/*/*: Remove AMD agesa family16 boards")

Change-Id: I41c386a6f61efd20cfd52ce5b71412b1f9e9181f
Signed-off-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89504
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 MAINTAINERS | 15 ---------------
 1 file changed, 15 deletions(-)

diff --git a/MAINTAINERS b/MAINTAINERS
index e87b4cd683..54a315796b 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -200,16 +200,6 @@ F:	src/mainboard/asrock/z97_extreme6/
 
 
 
-ASUS A88XM-E MAINBOARD
-M:	Mike Banon <mikebdp2@gmail.com>
-S:	Maintained
-F:	src/mainboard/asus/a88xm-e/
-
-ASUS AM1I-A MAINBOARD
-M:	Mike Banon <mikebdp2@gmail.com>
-S:	Maintained
-F:	src/mainboard/asus/am1i-a/
-
 ASUS H61 SERIES MAINBOARDS
 M:	Angel Pons <th3fanbus@gmail.com>
 S:	Maintained
@@ -475,11 +465,6 @@ M:	Alexander Couzens <lynxis@fe80.eu>
 S:	Maintained
 F:	src/mainboard/lenovo/
 
-LENOVO G505S MAINBOARD
-M:	Mike Banon <mikebdp2@gmail.com>
-S:	Maintained
-F:	src/mainboard/lenovo/g505s/
-
 LENOVO X200 MAINBOARD
 R:	Stefan Ott <coreboot@desire.ch>
 S:	Maintained

From ef8eb796365ccc34a22267dddbb7e89c57c787a8 Mon Sep 17 00:00:00 2001
From: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Date: Fri, 10 Oct 2025 08:59:19 +0900
Subject: [PATCH 2197/3886] MAINTAINERS: Rename util/ipqheader to util/qualcomm

This was renamed to util/qualcomm in commit 101098c41a04
("sdm845: Combine BB with QC-Sec for ROM boot").

Change-Id: I14c9b6d918d30e1d156559d110ad47e556645d84
Signed-off-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89508
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
---
 MAINTAINERS | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/MAINTAINERS b/MAINTAINERS
index 54a315796b..485683455c 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -981,7 +981,7 @@ F:	src/cpu/armltd/
 F:	src/soc/ti/
 F:	src/soc/samsung/
 F:	util/exynos/
-F:	util/ipqheader/
+F:	util/qualcomm/
 
 ################################################################################
 # Payloads

From d7ae81132b2ec61c2938f8cdef35143d44742d7b Mon Sep 17 00:00:00 2001
From: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Date: Fri, 10 Oct 2025 08:47:00 +0900
Subject: [PATCH 2198/3886] MAINTAINERS: Correct asus/p8z77-series to
 asus/p8x7x-series

This was renamed in commit 3201ec343afc ("mb/asus: Rename p8z77-series
to p8x7x-series").

Change-Id: Ia536a5306866c3f1dccab56f1e0a7474cf1842fd
Signed-off-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89505
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
---
 MAINTAINERS | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/MAINTAINERS b/MAINTAINERS
index 485683455c..1601251a87 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -216,11 +216,11 @@ M:	Angel Pons <th3fanbus@gmail.com>
 S:	Maintained
 F:	src/mainboard/asus/p5qpl-am/
 
-ASUS P8Z77 SERIES MAINBOARDS
+ASUS P8X7X SERIES MAINBOARDS
 M:	Angel Pons <th3fanbus@gmail.com>
 M:	Vlado Cibic <vladocb@protonmail.com>
 S:	Maintained
-F:	src/mainboard/asus/p8z77-series/
+F:	src/mainboard/asus/p8x7x-series/
 
 
 

From 6bfa257eefb24b79be840b88779c5ee721edf324 Mon Sep 17 00:00:00 2001
From: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Date: Fri, 10 Oct 2025 09:12:22 +0900
Subject: [PATCH 2199/3886] MAINTAINERS: Correct the path of cbmem_id.h

This was moved to commonlib in commit dc9f5cd54661 ("coreboot: introduce
commonlib"), then subsequently moved into commonlib/bsd in
commit ea619425eebd ("commonlib: Move commonlib/cbmem_id.h to commonlib/bsd/").

Change-Id: Ib92c89cd090e78c76931000925ea6292e1783e28
Signed-off-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89510
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 MAINTAINERS | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/MAINTAINERS b/MAINTAINERS
index 1601251a87..1c6e0a79f5 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1155,7 +1155,7 @@ F:	util/cbfstool/
 
 CBMEM
 F:	src/include/cbmem.h
-F:	src/include/cbmem_id.h
+F:	src/commonlib/bsd/include/commonlib/bsd/cbmem_id.h
 F:	util/cbmem/
 
 CONSOLE

From ff5daa0581cfc2407856c4633b612041f9d86c27 Mon Sep 17 00:00:00 2001
From: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Date: Fri, 10 Oct 2025 08:52:16 +0900
Subject: [PATCH 2200/3886] MAINTAINERS: Remove '/' from the beginning of paths

This also adds a missing trailing '/' to util/gitconfig, as this is a
directory.

Change-Id: Ib45dbf161b773cd89ad5acee183aeceac4d29584
Signed-off-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89506
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 MAINTAINERS | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/MAINTAINERS b/MAINTAINERS
index 1c6e0a79f5..ff6e32b626 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -889,8 +889,8 @@ M:	Piotr Król <piotr.krol@3mdeb.com>
 M:	Michał Żygowski <michal.zygowski@3mdeb.com>
 M:	Frans Hendriks <fhendriks@eltan.com>
 S:	Maintained
-F:	/src/soc/intel/braswell/
-F:	/src/vendorcode/intel/fsp/fsp1_1/braswell/
+F:	src/soc/intel/braswell/
+F:	src/vendorcode/intel/fsp/fsp1_1/braswell/
 
 INTEL CANNONLAKE SOC
 S:	Orphan
@@ -1058,7 +1058,7 @@ F:	util/docker/
 
 GIT
 F:	.git*
-F:	/util/gitconfig
+F:	util/gitconfig/
 
 HDA DECODER
 M:	Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>

From bf677716564c9cf74a939ccb11aa6053bab09b08 Mon Sep 17 00:00:00 2001
From: Hualin Wei <weihualin@huaqin.corp-partner.google.com>
Date: Sun, 28 Sep 2025 10:49:46 +0800
Subject: [PATCH 2201/3886] mb/google/fatcat/var/lapis: Update gpio GPP_E07
 configuration

The IRQ97 will continue to be triggered, and cros_ec_irq_thread()
will be called all the time, even if GPP_E07 is high.
The following information will be continuously printed on the EC
console:
25-09-20 15:25:53.945[148.780609 HC 0x0067 err 9]
...

According to NB7835CAA_SCH_MB_V1_A.pdf,
change
PAD_CFG_GPI_SCI_LOW(GPP_E07, NONE, DEEP, LEVEL),
->
PAD_CFG_GPI_APIC_LOCK(GPP_E07, NONE, LEVEL, INVERT, LOCK_CONFIG),
can fix the interrupt exception.

BUG=b:445883867
TEST=emerge-fatcat coreboot and there is no HC error storm.

Change-Id: Ic151dce7881a6730a347eeae8f2e029fdc60bbd0
Signed-off-by: Hualin Wei <weihualin@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89362
Reviewed-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Pranava Y N <pranavayn@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/google/fatcat/variants/lapis/gpio.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/mainboard/google/fatcat/variants/lapis/gpio.c b/src/mainboard/google/fatcat/variants/lapis/gpio.c
index b288420cda..aeb554c4a2 100644
--- a/src/mainboard/google/fatcat/variants/lapis/gpio.c
+++ b/src/mainboard/google/fatcat/variants/lapis/gpio.c
@@ -211,7 +211,7 @@ static const struct pad_config gpio_table[] = {
 	/* GPP_E06:     Not used */
 	PAD_NC(GPP_E06, NONE),
 	/* GPP_E07:     EC_SOC_INT_ODL */
-	PAD_CFG_GPI_SCI_LOW(GPP_E07, NONE, DEEP, LEVEL),
+	PAD_CFG_GPI_APIC_LOCK(GPP_E07, NONE, LEVEL, INVERT, LOCK_CONFIG),
 	/* GPP_E08:     Not used */
 	PAD_NC(GPP_E08, NONE),
 	/* GPP_E09:     USBA0_OC_ODL ==> USB_OC0# */

From f7512c8647f30863ac4ee5e69c5904e6ade83c20 Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Thu, 2 Oct 2025 14:52:34 +0100
Subject: [PATCH 2202/3886] mb/starlabs/starbook/{adl,rpl}: Remove USB
 OverCurrent Configuration

This isn't supported so remove it.

Change-Id: I8e8a87f1394199d3288ae27601069ad88e2fa74f
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89512
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
---
 .../starlabs/starbook/variants/adl/devicetree.cb          | 4 ++--
 .../starlabs/starbook/variants/rpl/devicetree.cb          | 8 ++++----
 src/mainboard/starlabs/starbook/variants/rpl/gpio.c       | 4 ++--
 3 files changed, 8 insertions(+), 8 deletions(-)

diff --git a/src/mainboard/starlabs/starbook/variants/adl/devicetree.cb b/src/mainboard/starlabs/starbook/variants/adl/devicetree.cb
index 63d8e6a4d7..675cc27d3b 100644
--- a/src/mainboard/starlabs/starbook/variants/adl/devicetree.cb
+++ b/src/mainboard/starlabs/starbook/variants/adl/devicetree.cb
@@ -65,14 +65,14 @@ chip soc/intel/alderlake
 			register "usb3_ports[0]"		= "USB3_PORT_DEFAULT(OC_SKIP)"
 
 			# Daughterboard USB 3.0 Type-A
-			register "usb2_ports[6]"		= "USB2_PORT_MID(OC0)"
+			register "usb2_ports[6]"		= "USB2_PORT_MID(OC_SKIP)"
 			register "usb3_ports[1]"		= "USB3_PORT_DEFAULT(OC_SKIP)"
 
 			# Internal Webcam
 			register "usb2_ports[CONFIG_CCD_PORT]"	= "USB2_PORT_MID(OC_SKIP)"
 
 			# Fingerprint Reader
-			register "usb2_ports[5]"		= "USB2_PORT_MID(OC0)"
+			register "usb2_ports[5]"		= "USB2_PORT_MID(OC_SKIP)"
 
 			# Daughterboard USB 2.0 Type-A + SD Card Reader
 			register "usb2_ports[3]"		= "USB2_PORT_MID(OC_SKIP)"
diff --git a/src/mainboard/starlabs/starbook/variants/rpl/devicetree.cb b/src/mainboard/starlabs/starbook/variants/rpl/devicetree.cb
index 8a7652f278..1862070935 100644
--- a/src/mainboard/starlabs/starbook/variants/rpl/devicetree.cb
+++ b/src/mainboard/starlabs/starbook/variants/rpl/devicetree.cb
@@ -106,22 +106,22 @@ chip soc/intel/alderlake
 		device ref gna		on  end
 		device ref xhci		on
 			# Motherboard USB TBT Type-C
-			register "usb2_ports[0]"		= "USB2_PORT_MID(OC5)"
+			register "usb2_ports[0]"		= "USB2_PORT_MID(OC_SKIP)"
 			register "tcss_ports[0]"		= "TCSS_PORT_DEFAULT(OC_SKIP)"
 
 			# Motherboard USB 3.0 Type-A
 			register "usb2_ports[2]"		= "USB2_PORT_MID(OC_SKIP)"
-			register "usb3_ports[0]"		= "USB3_PORT_DEFAULT(OC5)"
+			register "usb3_ports[0]"		= "USB3_PORT_DEFAULT(OC_SKIP)"
 
 			# Daughterboard USB 3.0 Type-A
-			register "usb2_ports[6]"		= "USB2_PORT_MID(OC0)"
+			register "usb2_ports[6]"		= "USB2_PORT_MID(OC_SKIP)"
 			register "usb3_ports[1]"		= "USB3_PORT_DEFAULT(OC_SKIP)"
 
 			# Internal Webcam
 			register "usb2_ports[CONFIG_CCD_PORT]"	= "USB2_PORT_MID(OC_SKIP)"
 
 			# Fingerprint Reader
-			register "usb2_ports[5]"		= "USB2_PORT_MID(OC0)"
+			register "usb2_ports[5]"		= "USB2_PORT_MID(OC_SKIP)"
 
 			# Daughterboard USB 2.0 Type-A + SD Card Reader
 			register "usb2_ports[3]"		= "USB2_PORT_MID(OC_SKIP)"
diff --git a/src/mainboard/starlabs/starbook/variants/rpl/gpio.c b/src/mainboard/starlabs/starbook/variants/rpl/gpio.c
index 56ab332835..2fd683a8eb 100644
--- a/src/mainboard/starlabs/starbook/variants/rpl/gpio.c
+++ b/src/mainboard/starlabs/starbook/variants/rpl/gpio.c
@@ -112,7 +112,7 @@ const struct pad_config gpio_table[] = {
 	/* A15:		Test Point 52					*/
 	PAD_NC(GPP_A15, NONE),
 	/* A16:		USB OverCurrent 3				*/
-	PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1),
+	PAD_NC(GPP_A16, NONE),
 	/* A17:		Not Connected					*/
 	PAD_NC(GPP_A17, NONE),
 	/* A19:		Not Connected					*/
@@ -272,7 +272,7 @@ const struct pad_config gpio_table[] = {
 	/* E7:		Embedded Controller SMI				*/
 	PAD_NC(GPP_E7, NONE),
 	/* E9:		USB OverCurrent 0				*/
-	PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1),
+	PAD_NC(GPP_E9, NONE),
 	/* E10:		PWD Amplifier Input				*/
 	PAD_NC(GPP_E10, NONE),
 	/* E13:		Not connected					*/

From ac8765c88a37bc94fcc96dc2bd77eb8e60e735a1 Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Thu, 2 Oct 2025 14:50:12 +0100
Subject: [PATCH 2203/3886] mb/starlabs/*: Correct USB Type-C Port
 Configuration

The macro USB2_PORTS_MID vs USB2_PORTS_TYPE_C essentially enables
or disables the PortResetMessage. This is only relevant to TCSS
ports.

Correct the macros accordingly.

Change-Id: I18a078c7f6fb937293e6159f05587b7e1f881512
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89513
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/starlabs/byte_adl/variants/mk_ii/devicetree.cb  | 2 +-
 src/mainboard/starlabs/starbook/variants/cml/devicetree.cb    | 2 +-
 src/mainboard/starlabs/starbook/variants/kbl/devicetree.cb    | 2 +-
 src/mainboard/starlabs/starbook/variants/rpl/devicetree.cb    | 2 +-
 src/mainboard/starlabs/starfighter/variants/rpl/devicetree.cb | 4 ++--
 5 files changed, 6 insertions(+), 6 deletions(-)

diff --git a/src/mainboard/starlabs/byte_adl/variants/mk_ii/devicetree.cb b/src/mainboard/starlabs/byte_adl/variants/mk_ii/devicetree.cb
index a85936813c..6cb92be551 100644
--- a/src/mainboard/starlabs/byte_adl/variants/mk_ii/devicetree.cb
+++ b/src/mainboard/starlabs/byte_adl/variants/mk_ii/devicetree.cb
@@ -39,7 +39,7 @@ chip soc/intel/alderlake
 		device ref gna		on  end
 		device ref xhci		on
 			# Front USB 3.0 Type-C
-			register "usb2_ports[0]"		= "USB2_PORT_MID(OC_SKIP)"
+			register "usb2_ports[0]"		= "USB2_PORT_TYPE_C(OC_SKIP)"
 			register "tcss_ports[0]"		= "TCSS_PORT_DEFAULT(OC_SKIP)"
 
 			# Back Top USB 3.0 Type-A
diff --git a/src/mainboard/starlabs/starbook/variants/cml/devicetree.cb b/src/mainboard/starlabs/starbook/variants/cml/devicetree.cb
index 900c504e3d..c9595dc6fd 100644
--- a/src/mainboard/starlabs/starbook/variants/cml/devicetree.cb
+++ b/src/mainboard/starlabs/starbook/variants/cml/devicetree.cb
@@ -53,7 +53,7 @@ chip soc/intel/cannonlake
 		end
 		device ref xhci on
 			# Motherboard USB 3.0 Type-C
-			register "usb2_ports[0]"		= "USB2_PORT_TYPE_C(OC_SKIP)"
+			register "usb2_ports[0]"		= "USB2_PORT_MID(OC_SKIP)"
 			register "usb3_ports[0]"		= "USB3_PORT_DEFAULT(OC_SKIP)"
 
 			# Motherboard USB 3.0 Type-A
diff --git a/src/mainboard/starlabs/starbook/variants/kbl/devicetree.cb b/src/mainboard/starlabs/starbook/variants/kbl/devicetree.cb
index 213cf56960..f2e9376bd0 100644
--- a/src/mainboard/starlabs/starbook/variants/kbl/devicetree.cb
+++ b/src/mainboard/starlabs/starbook/variants/kbl/devicetree.cb
@@ -49,7 +49,7 @@ chip soc/intel/skylake
 		end
 		device ref south_xhci	on
 			# Motherboard USB Type C
-			register "usb2_ports[0]"		= "USB2_PORT_TYPE_C(OC_SKIP)"
+			register "usb2_ports[0]"		= "USB2_PORT_MID(OC_SKIP)"
 			register "usb3_ports[0]"		= "USB3_PORT_DEFAULT(OC_SKIP)"
 
 			# Motherboard USB 3.0
diff --git a/src/mainboard/starlabs/starbook/variants/rpl/devicetree.cb b/src/mainboard/starlabs/starbook/variants/rpl/devicetree.cb
index 1862070935..e838c79256 100644
--- a/src/mainboard/starlabs/starbook/variants/rpl/devicetree.cb
+++ b/src/mainboard/starlabs/starbook/variants/rpl/devicetree.cb
@@ -106,7 +106,7 @@ chip soc/intel/alderlake
 		device ref gna		on  end
 		device ref xhci		on
 			# Motherboard USB TBT Type-C
-			register "usb2_ports[0]"		= "USB2_PORT_MID(OC_SKIP)"
+			register "usb2_ports[0]"		= "USB2_PORT_TYPE_C(OC_SKIP)"
 			register "tcss_ports[0]"		= "TCSS_PORT_DEFAULT(OC_SKIP)"
 
 			# Motherboard USB 3.0 Type-A
diff --git a/src/mainboard/starlabs/starfighter/variants/rpl/devicetree.cb b/src/mainboard/starlabs/starfighter/variants/rpl/devicetree.cb
index c82bc9aaf0..c911b05a4b 100644
--- a/src/mainboard/starlabs/starfighter/variants/rpl/devicetree.cb
+++ b/src/mainboard/starlabs/starfighter/variants/rpl/devicetree.cb
@@ -121,11 +121,11 @@ chip soc/intel/alderlake
 		device ref gna		on  end
 		device ref xhci		on
 			# Motherboard USB TBT Type-C #0
-			register "usb2_ports[0]"		= "USB2_PORT_MID(OC_SKIP)"
+			register "usb2_ports[0]"		= "USB2_PORT_TYPE_C(OC_SKIP)"
 			register "tcss_ports[0]"		= "TCSS_PORT_DEFAULT(OC_SKIP)"
 
 			# Motherboard USB TBT Type-C #1
-			register "usb2_ports[1]"		= "USB2_PORT_MID(OC_SKIP)"
+			register "usb2_ports[1]"		= "USB2_PORT_TYPE_C(OC_SKIP)"
 			register "tcss_ports[1]"		= "TCSS_PORT_DEFAULT(OC_SKIP)"
 
 			# Motherboard USB 3.0 Type-A

From b37821ac25bf7520d3002a3c51efb71965c913b2 Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Thu, 11 Sep 2025 14:14:24 +0100
Subject: [PATCH 2204/3886] mb/starlabs/*: Unify settings across device VBTs

The common settings are:
* Reorder Child Device mappings to prioritise EFP displays.
* Disable EFPx that are not present.
* eDP panel colour depth is 24-bit (8 bpc).
* POST brightness of 100.
* Minimum brightness of 0.
* DPST level of 2.
* PSR Enabled.
* DDRS Enabled.

Test=Boot all boards, check brightness levels are consistant, the
kernel recognises that PSR and DDRS are enabled, check all outputs
work.

Change-Id: I7eb6a110d25d4bcfd26ffdddd9ec666fc90a04b0
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89515
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 .../starlabs/byte_adl/variants/mk_ii/data.vbt | Bin 9216 -> 9216 bytes
 .../starlabs/starbook/variants/adl/data.vbt   | Bin 8704 -> 8704 bytes
 .../starlabs/starbook/variants/adl_n/data.vbt | Bin 9216 -> 9216 bytes
 .../variants/adl_n/data_native_res.vbt        | Bin 9216 -> 9216 bytes
 .../starlabs/starbook/variants/rpl/data.vbt   | Bin 9216 -> 9216 bytes
 .../starlabs/starbook/variants/tgl/data.vbt   | Bin 8704 -> 8704 bytes
 .../starfighter/variants/rpl/data.vbt         | Bin 9216 -> 9216 bytes
 .../variants/rpl/data_native_res.vbt          | Bin 9216 -> 9216 bytes
 .../starlite_adl/variants/mk_v/data.vbt       | Bin 9216 -> 9216 bytes
 .../variants/mk_v/data_native_res.vbt         | Bin 9216 -> 9216 bytes
 10 files changed, 0 insertions(+), 0 deletions(-)

diff --git a/src/mainboard/starlabs/byte_adl/variants/mk_ii/data.vbt b/src/mainboard/starlabs/byte_adl/variants/mk_ii/data.vbt
index 5c9db50c93300f512c58a713d068ecc6f6e605cf..bfb1495a8dc46a360340603580c39e1c5bcd9871 100644
GIT binary patch
delta 93
zcmZqhXz-XI#k`QgU~(d(@J0h^Mt(*H76uSzU~m9p#>t6n+LK!u3mF+Ee`mB{VqlnT
o$W*3qErCHmfZ?p708j}70~b&okUGHNz^DLXFfeRB&Sa?w09B?CmH+?%

delta 83
zcmZqhXz-XI#Vo>LFgcM?c%y+dBfkOz3j+u<FgO6Q!sJ9Y?a8f-g^U7|zcX4e9m|+(
c$W$f-lo1eMIIAcCWI(`VM<$WYXPJx@0k<3w9RL6T

diff --git a/src/mainboard/starlabs/starbook/variants/adl/data.vbt b/src/mainboard/starlabs/starbook/variants/adl/data.vbt
index 2c7db18510f074164a5f49ab607ca2dfcbcd864c..711e5311d306afdd0daa636ef0f8ad2c607ae226 100644
GIT binary patch
delta 245
zcmZp0X>ge!#q7plF!>{s@J0h+Mqw5P4h9DX79i$eU;xq#3=WeM*|aA&GQMGCn4HI?
z1|+94{Z40OVqjumpc(le2)Ir&a7|`pIWXCtg=_OcmNZ620iaVfHwUu$Gc)pRUdSoK
l%9t{FAD=zYN&ono<Uo4<|7T!;&_ZZnvOk-|=5735LI7&vE{*^I

delta 288
zcmZp0X>ge!#r&SZU~(d(@J0h+Mw<o(4h9w=b^u}pAQk{(CLm@6Vg^Pa2Ffx3Wf_37
z3_w{1pe#@Vh#43s*E7CjWS*SIqy{9XGW|{m%7J8QMXmw@uG0)$lNnhKOtxp?+I)~D
zjd5}!o7Uz)Hh*SDh0O~&WmqSl<kOjamXBvLBfrUHUVfg*ru^P=zyE^(0|S`)FNOvt
N`?E=G-p21G1ONqEF8=@k

diff --git a/src/mainboard/starlabs/starbook/variants/adl_n/data.vbt b/src/mainboard/starlabs/starbook/variants/adl_n/data.vbt
index 1e9e797faec9ba9bed5f962b2cf0c3505be043e4..70c3e07ea6ca12b647ed82e96d25eb46fd38ebe6 100644
GIT binary patch
delta 25
gcmZqhXz-XI#oWwbFgcM?c%#7)Mn;CsUm3ZT0A?r$b^rhX

delta 25
gcmZqhXz-XI#azr_FgcM?c%#7)Mn-|nUm3ZT0A*+gb^rhX

diff --git a/src/mainboard/starlabs/starbook/variants/adl_n/data_native_res.vbt b/src/mainboard/starlabs/starbook/variants/adl_n/data_native_res.vbt
index f82018ef8b785284d4b305e438de3a665e4dede3..0cd0ec4b7773a3710b525f434dbf9050e4800bb7 100644
GIT binary patch
delta 25
gcmZqhXz-XI#oWSRFgcM?c%#7)Mn;CsUm3ZT0A@M|cK`qY

delta 25
gcmZqhXz-XI#azN*FgcM?c%#7)Mn-|nUm3ZT0A+dycK`qY

diff --git a/src/mainboard/starlabs/starbook/variants/rpl/data.vbt b/src/mainboard/starlabs/starbook/variants/rpl/data.vbt
index f299aa546da06e224fb252815dab1a8fa93adb84..32a044ccf76a1983a4ad1e4909487aef4bccb312 100644
GIT binary patch
delta 256
zcmZqhXz-XI#ca=DF!>{s@J0i1Mqw5P4h9DX79i$eU;xq#3=WeM*|aCOGA?6cV3@4S
z<if}>xrj*(NX}&XozBR_02HPf`5y?lPBU;#c4TSUT+gzGkx>BX8qLk2Y<V1vDU%QI
pnRBuMoe07VllaXiTl0G>f%N?U&%gkoh0p*<9Ozk*&3pJ=L;$Z9FR=gs

delta 288
zcmZqhXz-XI#k`2YU~(d(@J0i1Mw<o(4h9w=b^u}pAQk{(CLm@6Vg^Pa2Ffx3Wf_37
z3_w{1pe#@Vh#43sH#4qax|T3mm&t{Zd2$hx8jzgH^gA7>1f+;o<SHQGI?cc}*^#AX
zb3Mx%#>t6nTAM@J@;D}6=Tn({pHF16Fu%rRd47q>*8JW|zyE^(0|S`)FNOv{;=sTV
K*}R9}MFarW!!XJK

diff --git a/src/mainboard/starlabs/starbook/variants/tgl/data.vbt b/src/mainboard/starlabs/starbook/variants/tgl/data.vbt
index 992a864623a6e92e61ab81204e437c5c4ab5ed1b..ca57e717f303b0d00a9038814afb2d62b2f74fd4 100644
GIT binary patch
delta 535
zcmbW!Jxjw-6b9gPZkjeNHBB`Zb*T732E`ITpo`Qf3NDHYI*BM02XW{uf)&I`r1dP$
z>LPRy3W8hRL>%nuV*f$+g2XqvSlvAEoRj-rxLj_E^Tqj6kN!4bk}EshRdy}CMJc*1
zFEpJPC2GX<RUdO?kwGEw&^=7TB=Tf7JSxXL!x4GpG`FO|j!F%Pq531(w=9~FjB<Dx
zJsnlSX~_2E5ZS3*qhHChnmp=eFW76V8||rW9W18w80BCQ)?gEMp#TSP0_SiES5Sd_
zsKGNt^F*u&7isG&f202=P2czBMSJIUsf1poq!;8)w`G+_l<!yT_O_BU!%-W$ti&C8
zGqyCmr6l7+)vahrlS0ST4}Egekq`U+=s1VPHK$=%_RTKtl%i>KUdm=xUQB~Y>iCK$
m#_`s<MDHLjfg<{zoxdu`@yl&3<MM?yCXK`rWUFJ=L-G^5^lHQa

delta 582
zcmbWzJ%|%Q6bJA(v)R4P$8IJH@wg(cSFCXOvGG!+$)eF{6IO_jYeXf*73mJtE_;P=
zTw}tMD?@DVf`y2w1dG^+l>`e*4Ps#-+5{Vw^`BsZdY%8__x8<W7}yERVY$7m4^O-x
zk8g^j9Z%^K%F_ML#jiPo(nAtNKhKjQlZayAg9D25##z26O3pFtkRc8^vu;`(9DZ|y
zl%g?z6t4W?a7rFudOI5}^M=fEAWcy~=Zb(s)FvOG?(l25-pUAnan-!(X|Lw(;_K-N
zDnc2mP={O4gxe6pE<AuP^x-KyhnEm<;3|prcMT4Y{(tfa;gR-U+~p^+k(>zb=?%!?
z1=kW$l=+=O-l$7%o32sQLpc`g$5;8Cd7W!1m%k-5gROW=v#R-mclko)bmi(fBHp%6
zvTtp|3iquB+x8tx{u%Dt1%7O&_=D~77hCa>biP!i&zJDWS13W(D4+(N5_|MXqbT~0
e6-9(@n(RNB&d+#)AEx(NspO!do@LlKR(=7a8FA+T

diff --git a/src/mainboard/starlabs/starfighter/variants/rpl/data.vbt b/src/mainboard/starlabs/starfighter/variants/rpl/data.vbt
index b788ede142beaa8e642d4adea8cb6f014477da36..9377482170c89d789297f36e23526eae38141a2c 100644
GIT binary patch
delta 265
zcmZqhXz-XI#mvZHF!>{s@J0i1Mr9TT4h9DxR$yQO(hgu+0mx?n@)>}91_lM7TItEH
zjBgkjCKoZO0m+$6ztb6+7?>CsXh!}A0<O~xT$3GHS~l0StYKsnn4HL_xjB?AkApE~
s@&P_`PBx(1K$u|?zxiZqes3j^p8x+D7$CF|8UTp{eIl}X55J2D03J;+2><{9

delta 281
zcmZqhXz-XI#oWbUFu9OXc%y+hqfG+?2LlTbI{>i)5DNe?6A&{3F#{tI17#V2vJ603
z2B0hhP!=cw#0-p+n;G9RGEXjIQUj7RnSQ4O<v_BuB3A(c*J%c>$&M^7o9kKDFiuWn
z)7l)$md7#qI-knq`+Opkh50om%kxW2w&wR%`u!gS7#P6Re=#%w5(kEY$mTu#E+PN{
CsV>?8

diff --git a/src/mainboard/starlabs/starfighter/variants/rpl/data_native_res.vbt b/src/mainboard/starlabs/starfighter/variants/rpl/data_native_res.vbt
index 9020e8740d6c5e194e749680361434ccf102137a..b0222677f63a502e639ba65c929273bee5409d70 100644
GIT binary patch
delta 265
zcmZqhXz-XI#mvNDF!>{s@J0i1Mr9TT4h9DxR$yQO(hgu+0mx?n@)>}91_lM7TItEH
zjBgkjCKoZO0m+$6ztb6+7?>CsXh!}A0<O~xT$3GHS~l0StYKsnn4HL_xjB?AkApE~
s@&P_`PBx(1K$u|?zxiZqes3j^p8x+D7$CF|8UTp{eIl}X55J2D03S~<3IG5A

delta 281
zcmZqhXz-XI#oWzcFu9OXc%y+hqfG+?2LlTbI{>i)5DNe?6A&{3F#{tI17#V2vJ603
z2B0hhP!=cw#0-p+n;G9RGEXjIQUj7RnSQ4O<v_BuB3A(c*J%c>$&M^7o9kKDFiuWn
z)7l)$md7#qI-knq`+Opkh50om%kxW2w&wR%`u!gS7#P6Re=#%w5(kEY$mTu#E+PN|
CyDr-R

diff --git a/src/mainboard/starlabs/starlite_adl/variants/mk_v/data.vbt b/src/mainboard/starlabs/starlite_adl/variants/mk_v/data.vbt
index a985a4b18a819d4122a5aecef554467f36113e3f..3b0236d896639cc33734710dc8a4527cc631e290 100644
GIT binary patch
delta 518
zcmcIgJxc>Y5S`ikFu6$X@KChyxTHxAoA`kdM7V%Lda<w&5=mj<7g%YNAhv=!<TqG{
zvlO%vL6jg^TU%)_T%0+tkn|4B%)Vvcn>X93cj_0DMxl5F6>6e;S#b=&3Ha)*DIC`!
z10kmmI`=T?KCNPqQC(CzK$*_5gfZP<X)e~`wE>O;wSof@BLIrqJplU1hcx049(Ls2
z7Uk6RJj8yAk5irvJWhCrDNjq7aiYq+E^R8$ibY#wdejk^Okns-*8)K>!w-5<9y@HB
zWpcH^ebXKjwLgW{wUvW!!-8y!ttv77Z*{<7J%L3v{VZzhMWj1pmp%;-9kv)m8|Hon
zTh!0b(0hI~YqCvAxU#FXY|r90?b%aBQ5g&Xe*4%^$i3_v-P%>mE%9IWd8LI#jT-LB
Ka7GRH)cFCknP6c6

delta 469
zcmcJLu}i~H5XSG`OG;9ud8Q@CA*Cu9gbpnf6-4S%sf)NcNWnT3-K2ux+Np~O%0Xx6
z4iyRRx(Nk`4judpGKek?LWg(>U3B+5IPQ1c-FtkUdZ&Kl>T+olN_39d+mg~J;K1mi
zCXkxALhY1mh$|EtfKS)x(<AzG8jOxXDOg@q5DV!89djGTNw-QF;gw}!ijC=z1;9t(
z3EEh|cuOWJxxlwB=}6>F5%-vgx=hI!(>)ECAV#JkjYXbLQa*Wdb$%#c;+<b==xI8X
zTc>7=+k)f&a-S8T)<+Rade$%KQ_oQ)=dy8j&`g~f*rV4>l@_cbdDbk|tn$VlyzlUr
zb|DQ1un#RLVh=(IQ8eL*BH${P^G7tW+~Cbx$C*2wjb#5SYcf!Fh@|YV;5%z5em4ID
DjkQ)c

diff --git a/src/mainboard/starlabs/starlite_adl/variants/mk_v/data_native_res.vbt b/src/mainboard/starlabs/starlite_adl/variants/mk_v/data_native_res.vbt
index 4f5a52e969536baa2f61403f78f0ab79a19a7abb..13c5b92d61f599b4168691619efc28a28e05e7f4 100644
GIT binary patch
delta 51
zcmZqhXz-XI#oWYTFu9OXc%#8FMn;Cs-x;O&xf!6q#Ef~ffY1xZ$pS)OHvbUj5C8yM
C*bO=W

delta 51
zcmZqhXz-XI#hk)mFu9OXc%#8FMn-|n-x;O&xh+^27%ng|FqoJzZx#@G!8ln!=*#9G
H!W;qsZ@>;Z


From ac7bb7694d7ee99206edc2d863d1509bdf290a25 Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Fri, 10 Oct 2025 20:49:13 +0100
Subject: [PATCH 2205/3886] mb/starlabs/starbook/mtl: Configure eSPI GPIO Mux

Configure Pin Mix for Cs, Clk, Miso and Mosi to get the eSPI
GPIOs working as they should be.

Change-Id: I798f1e98f611a53e9c87f15e1e0f1679b9933bee
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89520
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/starlabs/starbook/variants/mtl/ramstage.c | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/src/mainboard/starlabs/starbook/variants/mtl/ramstage.c b/src/mainboard/starlabs/starbook/variants/mtl/ramstage.c
index 0d400f3977..e602932bfe 100644
--- a/src/mainboard/starlabs/starbook/variants/mtl/ramstage.c
+++ b/src/mainboard/starlabs/starbook/variants/mtl/ramstage.c
@@ -6,4 +6,9 @@
 void mainboard_silicon_init_params(FSP_S_CONFIG *supd)
 {
 	supd->TcNotifyIgd = 2; // Auto
+	/* eSPI GPIOs */
+	supd->SerialIoSpiCsPinMux[0] = 0x14a48a;
+	supd->SerialIoSpiClkPinMux[0] = 0x14a48b;
+	supd->SerialIoSpiMisoPinMux[0] = 0x14a48c;
+	supd->SerialIoSpiMosiPinMux[0] = 0x14a48d;
 }

From 0c73e45493f871755e5a17fe5848b12dc4341e7c Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Thu, 9 Oct 2025 20:15:27 +0100
Subject: [PATCH 2206/3886] ec/starlabs/merlin: Add disabled option for lid
 switch

There are three options for the LID switch:
    SWITCH_NORMAL        0x00
    SWITCH_SLEEP_ONLY    0x01
    SWITCH_DISABLED      0x02

Add these to coreboot to ensure they are set correctly.

Change-Id: I159111438eabd4abeb654be75fd80f29bd835055
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89502
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
---
 src/ec/starlabs/merlin/ec.h  | 5 +++--
 src/ec/starlabs/merlin/ite.c | 3 ++-
 2 files changed, 5 insertions(+), 3 deletions(-)

diff --git a/src/ec/starlabs/merlin/ec.h b/src/ec/starlabs/merlin/ec.h
index 4b6b791771..b22b27917a 100644
--- a/src/ec/starlabs/merlin/ec.h
+++ b/src/ec/starlabs/merlin/ec.h
@@ -105,8 +105,9 @@
 #define SPEED_0_2C		0x02
 
 /* Lid Switch */
-#define SWITCH_ENABLED		0x00
-#define SWITCH_DISABLED		0x01
+#define SWITCH_NORMAL		0x00
+#define SWITCH_SLEEP_ONLY	0x01
+#define SWITCH_DISABLED		0x02
 
 /* Power LED Brightness */
 #define LED_NORMAL		0x00
diff --git a/src/ec/starlabs/merlin/ite.c b/src/ec/starlabs/merlin/ite.c
index f034a0505a..f0566a9bd2 100644
--- a/src/ec/starlabs/merlin/ite.c
+++ b/src/ec/starlabs/merlin/ite.c
@@ -319,7 +319,8 @@ static void merlin_init(struct device *dev)
 	 *
 	 */
 	const uint8_t lid_switch[] = {
-		SWITCH_ENABLED,
+		SWITCH_NORMAL,
+		SWITCH_SLEEP_ONLY,
 		SWITCH_DISABLED
 	};
 

From c7e4ef822d149c0f5cec6d1fa7251e054c5467e6 Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Fri, 10 Oct 2025 10:27:53 +0100
Subject: [PATCH 2207/3886] mb/starlabs/{starbook,starfighter}: Remove
 DRIVER_TPM_SPI_CHIP

This doesn't do anything, so remove it.

Change-Id: Ic753d0f08bdc0e9dd839357eb73c9771d94e5c83
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89517
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
---
 src/mainboard/starlabs/starbook/Kconfig    | 3 ---
 src/mainboard/starlabs/starfighter/Kconfig | 3 ---
 2 files changed, 6 deletions(-)

diff --git a/src/mainboard/starlabs/starbook/Kconfig b/src/mainboard/starlabs/starbook/Kconfig
index d0180d9cd6..ac265a92fc 100644
--- a/src/mainboard/starlabs/starbook/Kconfig
+++ b/src/mainboard/starlabs/starbook/Kconfig
@@ -146,9 +146,6 @@ config DEVICETREE
 config DIMM_SPD_SIZE
 	default 512
 
-config DRIVER_TPM_SPI_CHIP
-	default 2
-
 config EC_GPE_SCI
 	default 0x50 if BOARD_STARLABS_LABTOP_KBL || BOARD_STARLABS_LABTOP_CML
 	default 0x6e
diff --git a/src/mainboard/starlabs/starfighter/Kconfig b/src/mainboard/starlabs/starfighter/Kconfig
index 06aee60633..4b08a351cf 100644
--- a/src/mainboard/starlabs/starfighter/Kconfig
+++ b/src/mainboard/starlabs/starfighter/Kconfig
@@ -63,9 +63,6 @@ config DEVICETREE
 config DIMM_SPD_SIZE
 	default 512
 
-config DRIVER_TPM_SPI_CHIP
-	default 2
-
 config EC_GPE_SCI
 	default 0x6e
 

From b18dfde22a73f27a4618a5ecba4f4a637d6a7502 Mon Sep 17 00:00:00 2001
From: Hari L <haril@qualcomm.corp-partner.google.com>
Date: Thu, 25 Sep 2025 19:33:20 +0530
Subject: [PATCH 2208/3886] soc/qualcomm/x1p42100: Add Clock support for USB
 Type-C ports

Enable clocks for Type-C ports C0 and C1.
The register details are part of HRD-X1P42100-S1 document.
https://docs.qualcomm.com/bundle/resource/topics/HRD-X1P42100-S1/

BUG=b:448107633
TEST = Verified that all the clocks added are ON during usb init.
BIT31[CLK OFF] of CBCR register of respective clock indicates
clock status.

Clock Configuration Status:

Clock Name                          State  Register    Value
----------------------------------------------------------------
gcc_usb30_mp_master_clk             ON     0x00117018  0x00000001
gcc_usb30_mp_sleep_clk              ON     0x00117024  0x00000001
gcc_usb30_mp_mock_utmi_clk          ON     0x00117028  0x00000001
gcc_usb3_mp_phy_aux_clk             ON     0x00117288  0x00000001
gcc_usb3_mp_phy_com_aux_clk         ON     0x0011728C  0x00000001
gcc_usb3_mp_phy_pipe_0_clk          ON     0x00117290  0x00000001
gcc_usb3_mp_phy_pipe_1_clk          ON     0x00117298  0x00000001
gcc_cfg_noc_usb3_mp_axi_clk         ON     0x001173CC  0x00000001
gcc_aggre_usb3_mp_axi_clk           ON     0x001173D0  0x00000001
gcc_sys_noc_usb_axi_clk             ON     0x0012D014  0x00000001
gcc_cfg_noc_usb_anoc_north_ahb_clk  ON     0x0012D028  0x00000000
gcc_cfg_noc_usb_anoc_south_ahb_clk  ON     0x0012D02C  0x00000000
gcc_aggre_usb_noc_axi_clk           ON     0x0012D034  0x00000001
gcc_cfg_noc_usb_anoc_ahb_clk        ON     0x0012D024  0x00000000
gcc_usb30_prim_master_clk           ON     0x00139018  0x00000001
gcc_usb30_prim_sleep_clk            ON     0x00139024  0x00000001
gcc_usb30_prim_mock_utmi_clk        ON     0x00139028  0x00000001
gcc_usb3_prim_phy_com_aux_clk       ON     0x00139064  0x00000001
gcc_usb3_prim_phy_pipe_clk          ON     0x00139068  0x00000001
gcc_cfg_noc_usb3_prim_axi_clk       ON     0x0013908C  0x00000001
gcc_aggre_usb3_prim_axi_clk         ON     0x00139090  0x00000001
gcc_cfg_noc_usb3_sec_axi_clk        ON     0x001A108C  0x00000001
gcc_aggre_usb3_sec_axi_clk          ON     0x001A1090  0x00000001
gcc_usb30_sec_master_clk            ON     0x001A1018  0x00000001
gcc_usb30_sec_sleep_clk             ON     0x001A1024  0x00000001
gcc_usb30_sec_mock_utmi_clk         ON     0x001A1028  0x00000001
gcc_usb3_sec_phy_aux_clk            ON     0x001A1060  0x00000001
gcc_usb3_sec_phy_com_aux_clk        ON     0x001A1064  0x00000001
gcc_usb3_sec_phy_pipe_clk           ON     0x001A1068  0x00000001

Change-Id: I86cd84f515a22a080fe39687c8b7b8c01cb9c001
Signed-off-by: Hari L <haril@qualcomm.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89350
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
---
 src/soc/qualcomm/x1p42100/clock.c             |  84 +++++++-
 .../x1p42100/include/soc/addressmap.h         |  26 +++
 src/soc/qualcomm/x1p42100/include/soc/clock.h | 197 +++++++++++++++---
 3 files changed, 274 insertions(+), 33 deletions(-)

diff --git a/src/soc/qualcomm/x1p42100/clock.c b/src/soc/qualcomm/x1p42100/clock.c
index 81c406282d..614490104a 100644
--- a/src/soc/qualcomm/x1p42100/clock.c
+++ b/src/soc/qualcomm/x1p42100/clock.c
@@ -239,9 +239,11 @@ static u32 *usb_gdsc[MAX_USB_GDSC] = {
 	[USB30_MP_GDSC] = &gcc->gcc_usb30_mp_gdscr,
 	[USB3_SS0_PHY_GDSC] = &gcc->gcc_usb3_mp_ss0_phy_gdscr,
 	[USB3_SS1_PHY_GDSC] = &gcc->gcc_usb3_mp_ss1_phy_gdscr,
+	[USB30_PRIM_GDSC] = &gcc->gcc_usb30_prim_gdscr,
+	[USB30_SEC_GDSC] = &gcc->gcc_usb30_sec_gdscr,
 };
 
-static u32 *usb_cbcr[USB_CLK_COUNT] = {
+static u32 *usb_mp_cbcr[USB_CLK_COUNT] = {
 	[USB30_MP_MASTER_CBCR] = &gcc->gcc_usb30_mp_master_cbcr,
 	[USB30_MP_SLEEP_CBCR] = &gcc->gcc_usb30_mp_sleep_cbcr,
 	[USB30_MP_MOCK_UTMI_CBCR] = &gcc->gcc_usb30_mp_mock_utmi_cbcr,
@@ -259,6 +261,39 @@ static u32 *usb_cbcr[USB_CLK_COUNT] = {
 	[AGGRE_NOC_USB_NORTH_AXI_CBCR] = &gcc->gcc_aggre_noc_usb_north_axi_cbcr,
 };
 
+static u32 *usb_prim_cbcr[USB_PRIM_CLK_COUNT] = {
+	[USB_PRIM_SYS_NOC_USB_AXI_CBCR] = &gcc->gcc_sys_noc_usb_axi_cbcr,
+	[USB_PRIM_CFG_NOC_USB_ANOC_AHB_CBCR] = &gcc->gcc_cfg_noc_usb_anoc_ahb_cbcr,
+	[USB_PRIM_CFG_NOC_USB_ANOC_NORTH_AHB_CBCR] = &gcc->gcc_cfg_noc_usb_anoc_north_ahb_cbcr,
+	[USB_PRIM_CFG_NOC_USB_ANOC_SOUTH_AHB_CBCR] = &gcc->gcc_cfg_noc_usb_anoc_south_ahb_cbcr,
+	[USB_PRIM_AGGRE_USB_NOC_AXI_CBCR] = &gcc->gcc_aggre_usb_noc_axi_cbcr,
+	[USB_PRIM_AGGRE_NOC_USB_SOUTH_AXI_CBCR] = &gcc->gcc_aggre_noc_usb_south_axi_cbcr,
+	[USB_PRIM_AGGRE_NOC_USB_NORTH_AXI_CBCR] = &gcc->gcc_aggre_noc_usb_north_axi_cbcr,
+	[USB_PRIM_USB30_PRIM_MASTER_CBCR] = &gcc->gcc_usb30_prim_master_cbcr,
+	[USB_PRIM_USB30_PRIM_SLEEP_CBCR] = &gcc->gcc_usb30_prim_sleep_cbcr,
+	[USB_PRIM_USB30_PRIM_MOCK_UTMI_CBCR] = &gcc->gcc_usb30_prim_mock_utmi_cbcr,
+	[USB_PRIM_USB3_PRIM_PHY_AUX_CBCR] = &gcc->gcc_usb3_prim_phy_aux_cbcr,
+	[USB_PRIM_USB3_PRIM_PHY_COM_AUX_CBCR] = &gcc->gcc_usb3_prim_phy_com_aux_cbcr,
+	[USB_PRIM_USB3_PRIM_PHY_PIPE_CBCR] = &gcc->gcc_usb3_prim_phy_pipe_cbcr,
+	[USB_PRIM_CFG_NOC_USB3_PRIM_AXI_CBCR] = &gcc->gcc_cfg_noc_usb3_prim_axi_cbcr,
+	[USB_PRIM_AGGRE_USB3_PRIM_AXI_CBCR] = &gcc->gcc_aggre_usb3_prim_axi_cbcr,
+};
+
+static u32 *usb_sec_cbcr[USB_SEC_CLK_COUNT] = {
+	[USB_SEC_CFG_NOC_USB3_SEC_AXI_CBCR] = &gcc->gcc_cfg_noc_usb3_sec_axi_cbcr,
+	[USB_SEC_AGGRE_USB3_SEC_AXI_CBCR] = &gcc->gcc_aggre_usb3_sec_axi_cbcr,
+	[USB_SEC_USB30_SEC_MASTER_CBCR] = &gcc->gcc_usb30_sec_master_cbcr,
+	[USB_SEC_USB30_SEC_SLEEP_CBCR] = &gcc->gcc_usb30_sec_sleep_cbcr,
+	[USB_SEC_USB30_SEC_MOCK_UTMI_CBCR] = &gcc->gcc_usb30_sec_mock_utmi_cbcr,
+	[USB_SEC_USB3_SEC_PHY_AUX_CBCR] = &gcc->gcc_usb3_sec_phy_aux_cbcr,
+	[USB_SEC_USB3_SEC_PHY_COM_AUX_CBCR] = &gcc->gcc_usb3_sec_phy_com_aux_cbcr,
+	[USB_SEC_USB3_SEC_PHY_PIPE_CBCR] = &gcc->gcc_usb3_sec_phy_pipe_cbcr,
+	[USB_SEC_AGGRE_USB_NOC_AXI_CBCR] = &gcc->gcc_aggre_usb_noc_axi_cbcr,
+	[USB_SEC_AGGRE_NOC_USB_NORTH_AXI_CBCR] = &gcc->gcc_aggre_noc_usb_north_axi_cbcr,
+	[USB_SEC_AGGRE_NOC_USB_SOUTH_AXI_CBCR] = &gcc->gcc_aggre_noc_usb_south_axi_cbcr,
+	[USB_SEC_SYS_NOC_USB_AXI_CBCR] = &gcc->gcc_sys_noc_usb_axi_cbcr,
+};
+
 static struct clock_freq_config pcie_core_cfg[] = {
 	{
 		.hz = 100 * MHz,
@@ -385,18 +420,54 @@ enum cb_err usb_clock_enable(enum clk_usb clk_type)
 	if (clk_type >= USB_CLK_COUNT)
 		return CB_ERR;
 
-	return clock_enable(usb_cbcr[clk_type]);
+	return clock_enable(usb_mp_cbcr[clk_type]);
 }
 
 void usb_clock_reset(enum clk_usb clk_type, bool assert)
 {
-	clock_reset(usb_cbcr[clk_type], assert);
+	clock_reset(usb_mp_cbcr[clk_type], assert);
+}
+
+enum cb_err usb_prim_clock_enable(enum clk_usb_prim clk_type)
+{
+	if (clk_type >= USB_PRIM_CLK_COUNT) {
+		printk(BIOS_ERR, "USB C0 clock enable failed: "
+			"clock type %d out of range\n", clk_type);
+		return CB_ERR;
+	}
+
+	return clock_enable(usb_prim_cbcr[clk_type]);
+}
+
+void usb_prim_clock_reset(enum clk_usb_prim clk_type, bool assert)
+{
+	clock_reset(usb_prim_cbcr[clk_type], assert);
+}
+
+enum cb_err usb_sec_clock_enable(enum clk_usb_sec clk_type)
+{
+	if (clk_type >= USB_SEC_CLK_COUNT) {
+		printk(BIOS_ERR, "USB C1 clock enable failed: "
+			"clock type %d out of range\n", clk_type);
+		return CB_ERR;
+	}
+
+	return clock_enable(usb_sec_cbcr[clk_type]);
+}
+
+void usb_sec_clock_reset(enum clk_usb_sec clk_type, bool assert)
+{
+	clock_reset(usb_sec_cbcr[clk_type], assert);
 }
 
 void clock_configure_usb(void)
 {
 	clock_configure(&gcc->usb30_mp_master_rcg,
 		usb_core_cfg, USB3_MASTER_CLK_MIN_FREQ_HZ, ARRAY_SIZE(usb_core_cfg));
+	clock_configure(&gcc->usb30_prim_master_rcg,
+		usb_core_cfg, USB3_MASTER_CLK_MIN_FREQ_HZ, ARRAY_SIZE(usb_core_cfg));
+	clock_configure(&gcc->usb30_sec_master_rcg,
+		usb_core_cfg, USB3_MASTER_CLK_MIN_FREQ_HZ, ARRAY_SIZE(usb_core_cfg));
 }
 
 enum cb_err usb_clock_configure_mux(enum clk_pipe_usb clk_type, u32 src_type)
@@ -408,6 +479,13 @@ enum cb_err usb_clock_configure_mux(enum clk_pipe_usb clk_type, u32 src_type)
 	case USB3_PHY_PIPE_1:
 		write32(&gcc->gcc_usb3_mp_phy_pipe_1_muxr, src_type);
 		break;
+	case USB3_PRIM_PHY_PIPE:
+		write32(&gcc->gcc_usb3_prim_phy_pipe_muxr, src_type);
+		break;
+	case USB3_SEC_PHY_PIPE:
+		write32(&gcc->gcc_usb3_sec_phy_pipe_muxr, src_type);
+		break;
+
 	default:
 		printk(BIOS_ERR, "Unhandled clk_type: %d, src_type: %u\n", clk_type, src_type);
 		return CB_ERR;
diff --git a/src/soc/qualcomm/x1p42100/include/soc/addressmap.h b/src/soc/qualcomm/x1p42100/include/soc/addressmap.h
index cbb6aa33cd..8643f49b9b 100644
--- a/src/soc/qualcomm/x1p42100/include/soc/addressmap.h
+++ b/src/soc/qualcomm/x1p42100/include/soc/addressmap.h
@@ -70,6 +70,10 @@
 #define QUP_2_GSI_BASE			0x00804000
 
 /* USB BASE ADDRESSES */
+#define HS_USB_SS0_PHY_BASE		0x00FD3000
+#define HS_USB_SS1_PHY_BASE		0x00FD9000
+#define HS_USB_SS2_PHY_BASE		0x00FDE000
+
 #define HS_USB_MP0_PHY_BASE		0x088e1000
 #define HS_USB_MP1_PHY_BASE		0x088E2000
 #define QMP_PHY_MP0_QSERDES_COM_REG_BASE	0x088E3000
@@ -85,6 +89,26 @@
 #define QMP_PHY_MP1_PCS_REG_BASE			0x088E5200
 #define QMP_PHY_MP1_PCS_USB3_REG_BASE		0x088E6200
 
+/* USB SS0 PHY BASE ADDRESSES - AHB2PHY_1_QUSB4PHY_SS_0 */
+#define QMP_PHY_SS0_COM_REG_BASE		0xFD5000  // USB43DP_COM
+#define QMP_PHY_SS0_TXA_REG_BASE		0xFD5400  // USB43DP_QSERDES_TXA
+#define QMP_PHY_SS0_TXB_REG_BASE		0xFD5A00  // USB43DP_QSERDES_TXB
+#define QMP_PHY_SS0_RXA_REG_BASE		0xFD5600  // USB43DP_QSERDES_RXA
+#define QMP_PHY_SS0_RXB_REG_BASE		0xFD5C00  // USB43DP_QSERDES_RXB
+#define QMP_PHY_SS0_QSERDES_PLL_REG_BASE	0x00FD6000  // USB3_QSERDES_PLL
+#define QMP_PHY_SS0_PCS_REG_BASE		0xFD6400  // USB3_PCS
+#define QMP_PHY_SS0_PCS_USB3_REG_BASE		0xFD6700  // USB3_PCS_USB3
+
+/* USB SS1 PHY BASE ADDRESSES - AHB2PHY_1_QUSB4PHY_SS_1 */
+#define QMP_PHY_SS1_COM_REG_BASE		0xFDA000  // USB43DP_COM
+#define QMP_PHY_SS1_TXA_REG_BASE		0xFDA400  // USB43DP_QSERDES_TXA
+#define QMP_PHY_SS1_TXB_REG_BASE		0xFDAA00  // USB43DP_QSERDES_TXB
+#define QMP_PHY_SS1_RXA_REG_BASE		0xFDA600  // USB43DP_QSERDES_RXA
+#define QMP_PHY_SS1_RXB_REG_BASE		0xFDAC00  // USB43DP_QSERDES_RXB
+#define QMP_PHY_SS1_QSERDES_PLL_REG_BASE	0xFDB000  // USB3_QSERDES_PLL
+#define QMP_PHY_SS1_PCS_REG_BASE		0xFDB400  // USB3_PCS
+#define QMP_PHY_SS1_PCS_USB3_REG_BASE		0xFDB700  // USB3_PCS_USB3
+
 /* PCIE 6A */
 #define PCIE6A_PCIE_PARF		0x01BF8000
 #define PCIE6A_GEN1X4_PCIE_DBI		0x70000000
@@ -141,6 +165,8 @@
 
 #define TCSR_GCC_USB3_MP0_CLKREF_EN_ADDR	((void *)0x1FD510C)
 #define TCSR_GCC_USB3_MP1_CLKREF_EN_ADDR	((void *)0x1FD5110)
+#define TCSR_GCC_USB4_1_CLKREF_EN_ADDR		((void *)0x1FD5120)
+#define TCSR_GCC_USB4_2_CLKREF_EN_ADDR		((void *)0x1FD5124)
 #define USB3_CLKREF_ENABLE_VALUE			0x1
 
 /* SPMI PMIC ARB */
diff --git a/src/soc/qualcomm/x1p42100/include/soc/clock.h b/src/soc/qualcomm/x1p42100/include/soc/clock.h
index 2076699769..988bba9eea 100644
--- a/src/soc/qualcomm/x1p42100/include/soc/clock.h
+++ b/src/soc/qualcomm/x1p42100/include/soc/clock.h
@@ -217,7 +217,10 @@ struct x1p42100_gcc {
 	struct x1p42100_gpll gpll0;
 	u8 _res0[0x10004 - 0x0002c];
 	struct x1p42100_pcie_noc pcie_noc;
-	u8 _res1[0x1200C - 0x10054];
+	u8 _res1[0x12000 - 0x10054];
+	u32 gcc_qusb2phy_prim_bcr;
+	u32 gcc_qusb2phy_sec_bcr;
+	u32 gcc_qusb2phy_tert_bcr;
 	u32 qusb2phy_hs0_mp_bcr;
 	u32 qusb2phy_hs1_mp_bcr;
 	u8 _res2[0x17000 - 0x12014];
@@ -225,7 +228,7 @@ struct x1p42100_gcc {
 	u32 gcc_usb30_mp_gdscr;
 	u8 _res3[0x17018 - 0x17008];
 	u32 gcc_usb30_mp_master_cbcr;
-	u8 _res4[0x17024 - 0x1701C];
+	u8 _res4[0x17024 - 0x1701c];
 	u32 gcc_usb30_mp_sleep_cbcr;
 	u32 gcc_usb30_mp_mock_utmi_cbcr;
 	struct clock_rcg usb30_mp_master_rcg;
@@ -236,10 +239,10 @@ struct x1p42100_gcc {
 	u32 gcc_usb3_mp_phy_pipe_0_muxr;
 	u32 gcc_usb3_mp_phy_pipe_1_cbcr;
 	u32 gcc_usb3_mp_phy_pipe_1_muxr;
-	u8 _res6[0x173CC - 0x172A0];
+	u8 _res6[0x173cc - 0x172a0];
 	u32 gcc_cfg_noc_usb3_mp_axi_cbcr;
 	u32 gcc_aggre_usb3_mp_axi_cbcr;
-	u8 _res7[0x18004 - 0x173D4];
+	u8 _res7[0x18004 - 0x173d4];
 	struct qupv3_clock qup_wrap1_s[8];
 	u8 _res8[0x19000 - 0x189c4];
 	u32 usb3_uniphy_mp0_bcr;
@@ -275,59 +278,148 @@ struct x1p42100_gcc {
 	u32 qup_wrap2_core_2x_cbcr;
 	u8 _res19[0x232c4 - 0x232bc];
 	struct clock_rcg qup_wrap2_core_2x;
-	u8 _res20[0x2D014 - 0x232cc];
+	u8 _res20[0x2a000 - 0x232cc];
+	u32 gcc_usb3_phy_sec_bcr;
+	u32 gcc_usb3phy_phy_sec_bcr;
+	u8 _res21[0x2a010 - 0x2a008];
+	u32 gcc_usb4_1_dp0_phy_sec_bcr;
+	u8 _res22[0x2d014 - 0x2a014];
 	u32 gcc_sys_noc_usb_axi_cbcr;
-	u8 _res21[0x2D028 - 0x2D018];
+	u8 _res23[0x2d024 - 0x2d018];
+	u32 gcc_cfg_noc_usb_anoc_ahb_cbcr;
 	u32 gcc_cfg_noc_usb_anoc_north_ahb_cbcr;
 	u32 gcc_cfg_noc_usb_anoc_south_ahb_cbcr;
-	u8 _res22[0x2D034 - 0x2D030];
+	u8 _res24[0x2d034 - 0x2d030];
 	u32 gcc_aggre_usb_noc_axi_cbcr;
-	u8 _res23[0x2D174 - 0x2D038];
+	u8 _res25[0x2d174 - 0x2d038];
 	u32 gcc_aggre_noc_usb_south_axi_cbcr;
-	u8 _res24[0x2D17C - 0x2D178];
+	u8 _res26[0x2d17c - 0x2d178];
 	u32 gcc_aggre_noc_usb_north_axi_cbcr;
-	u8 _res25[0x31000 - 0x2D180];
+	u8 _res27[0x31000 - 0x2d180];
 	struct x1p42100_pcie pcie_6a;
-	u8  res26[0x39000-0x3108c];
-	u32 usb30_prim_bcr;
-	u8  res27[0x42004-0x39004];
+	u8  _res28[0x39000 - 0x3108c];
+	u32 gcc_usb30_prim_bcr;
+	u32 gcc_usb30_prim_gdscr;
+	u8  _res29[0x39018 - 0x39008];
+	u32 gcc_usb30_prim_master_cbcr;
+	u8  _res30[0x39024 - 0x3901c];
+	u32 gcc_usb30_prim_sleep_cbcr;
+	u32 gcc_usb30_prim_mock_utmi_cbcr;
+	struct clock_rcg usb30_prim_master_rcg;
+	u8  _res31[0x39060 - 0x39034];
+	u32 gcc_usb3_prim_phy_aux_cbcr;
+	u32 gcc_usb3_prim_phy_com_aux_cbcr;
+	u32 gcc_usb3_prim_phy_pipe_cbcr;
+	u32 gcc_usb3_prim_phy_pipe_muxr;
+	u32 gcc_usb4_mode_prim_phy_pipe_muxr;
+	u8  _res32[0x3908c - 0x39074];
+	u32 gcc_cfg_noc_usb3_prim_axi_cbcr;
+	u32 gcc_aggre_usb3_prim_axi_cbcr;
+	u8  _res33[0x42004 - 0x39094];
 	struct qupv3_clock qup_wrap0_s[8];
-	u8 _res28[0x4b000 - 0x429c4];
+	u8 _res34[0x4b000 - 0x429c4];
 	u32 qspi_bcr;
 	u32 qspi_cnoc_ahb_cbcr;
 	u32 qspi_core_cbcr;
 	struct clock_rcg qspi_core;
-	u8 _res29[0x52000 - 0x4b014];
+	u8 _res35[0x50000 - 0x4b014];
+	u32 gcc_usb3_phy_prim_bcr;
+	u32 gcc_usb3phy_phy_prim_bcr;
+	u8 _res36[0x50010 - 0x50008];
+	u32 gcc_usb4_0_dp0_phy_prim_bcr;
+	u8 _res37[0x52000 - 0x50014];
 	u32 apcs_clk_br_en;
-	u8 _res30[0x52008 - 0x52004];
+	u8 _res38[0x52008 - 0x52004];
 	u32 apcs_clk_br_en1;
-	u8 _res31[0x52010 - 0x5200c];
+	u8 _res39[0x52010 - 0x5200c];
 	u32 apcs_clk_br_en2;
-	u8 _res32[0x52018 - 0x52014];
+	u8 _res40[0x52018 - 0x52014];
 	u32 apcs_clk_br_en3;
-	u8 _res33[0x52020 - 0x5201c];
+	u8 _res41[0x52020 - 0x5201c];
 	u32 apcs_clk_br_en4;
-	u8 _res34[0x52028 - 0x52024];
+	u8 _res42[0x52028 - 0x52024];
 	u32 apcs_clk_br_en5;
-	u8 _res35[0x52030 - 0x5202c];
+	u8 _res43[0x52030 - 0x5202c];
 	u32 apcs_pll_br_en;
-	u8 _res36[0x54000 - 0x52034];
+	u8 _res44[0x54000 - 0x52034];
 	u32 usb3_uniphy_mp1_bcr;
 	u32 usb3uniphy_phy_mp1_bcr;
 	u32 gcc_usb3_mp_ss1_phy_bcr;
 	u32 gcc_usb3_mp_ss1_phy_gdscr;
-	u8 _res37[0x8e000 - 0x54010];
+	u8 _res45[0x8e000 - 0x54010];
 	u32 pcie_6_phy_gdscr;
-	u8 _res38[0xac01c - 0x8e004];
+	u8 _res46[0xa1000 - 0x8e004];
+	u32 gcc_usb30_sec_bcr;
+	u32 gcc_usb30_sec_gdscr;
+	u8 _res47[0xa1018 - 0xa1008];
+	u32 gcc_usb30_sec_master_cbcr;
+	u8 _res48[0xa1024 - 0xa101c];
+	u32 gcc_usb30_sec_sleep_cbcr;
+	u32 gcc_usb30_sec_mock_utmi_cbcr;
+	struct clock_rcg usb30_sec_master_rcg;
+	u8 _res49[0xa1060 - 0xa1034];
+	u32 gcc_usb3_sec_phy_aux_cbcr;
+	u32 gcc_usb3_sec_phy_com_aux_cbcr;
+	u32 gcc_usb3_sec_phy_pipe_cbcr;
+	u32 gcc_usb3_sec_phy_pipe_muxr;
+	u8 _res50[0xa108c - 0xa1070];
+	u32 gcc_cfg_noc_usb3_sec_axi_cbcr;
+	u32 gcc_aggre_usb3_sec_axi_cbcr;
+	u8 _res51[0xa2000 - 0xa1094];
+	u32 gcc_usb30_tert_bcr;
+	u32 gcc_usb30_tert_gdscr;
+	u8 _res52[0xa2018 - 0xa2008];
+	u32 gcc_usb30_tert_master_cbcr;
+	u8 _res53[0xa2024 - 0xa201c];
+	u32 gcc_usb30_tert_sleep_cbcr;
+	u32 gcc_usb30_tert_mock_utmi_cbcr;
+	u8 _res54[0xa2034 - 0xa202c];
+	u32 gcc_usb30_tert_master_m;
+	u32 gcc_usb30_tert_master_n;
+	u32 gcc_usb30_tert_master_d;
+	u8 _res55[0xa2060 - 0xa2040];
+	u32 gcc_usb3_tert_phy_aux_cbcr;
+	u32 gcc_usb3_tert_phy_com_aux_cbcr;
+	u32 gcc_usb3_tert_phy_pipe_cbcr;
+	u32 gcc_usb3_tert_phy_pipe_muxr;
+	u8 _res56[0xa208c - 0xa2070];
+	u32 gcc_cfg_noc_usb3_tert_axi_cbcr;
+	u32 gcc_aggre_usb3_tert_axi_cbcr;
+	u8 _res57[0xa3000 - 0xa2094];
+	u32 gcc_usb3_phy_tert_bcr;
+	u32 gcc_usb3phy_phy_tert_bcr;
+	u8 _res58[0xa3010 - 0xa3008];
+	u32 gcc_usb4_2_dp0_phy_tert_bcr;
+	u8 _res59[0xac01c - 0xa3014];
 	u32 pcie_6a_phy_bcr;
 };
+
+check_member(x1p42100_gcc, gcc_usb30_prim_bcr, 0x39000);
+check_member(x1p42100_gcc, gcc_usb30_prim_master_cbcr, 0x39018);
+check_member(x1p42100_gcc, gcc_cfg_noc_usb3_prim_axi_cbcr, 0x3908c);
+check_member(x1p42100_gcc, gcc_usb30_sec_bcr, 0xa1000);
+check_member(x1p42100_gcc, gcc_usb30_sec_master_cbcr, 0xa1018);
+check_member(x1p42100_gcc, gcc_usb3_sec_phy_aux_cbcr, 0xa1060);
+check_member(x1p42100_gcc, gcc_usb30_tert_bcr, 0xa2000);
+check_member(x1p42100_gcc, gcc_qusb2phy_prim_bcr, 0x12000);
+check_member(x1p42100_gcc, gcc_qusb2phy_sec_bcr, 0x12004);
+check_member(x1p42100_gcc, gcc_qusb2phy_tert_bcr, 0x12008);
 check_member(x1p42100_gcc, qusb2phy_hs1_mp_bcr, 0x12010);
+check_member(x1p42100_gcc, gcc_usb3_phy_sec_bcr, 0x2a000);
+check_member(x1p42100_gcc, gcc_usb3phy_phy_sec_bcr, 0x2a004);
+check_member(x1p42100_gcc, gcc_usb4_1_dp0_phy_sec_bcr, 0x2a010);
+check_member(x1p42100_gcc, gcc_usb3_phy_prim_bcr, 0x50000);
+check_member(x1p42100_gcc, gcc_usb3phy_phy_prim_bcr, 0x50004);
+check_member(x1p42100_gcc, gcc_usb4_0_dp0_phy_prim_bcr, 0x50010);
+check_member(x1p42100_gcc, gcc_usb3_phy_tert_bcr, 0xa3000);
+check_member(x1p42100_gcc, gcc_usb3phy_phy_tert_bcr, 0xa3004);
+check_member(x1p42100_gcc, gcc_usb4_2_dp0_phy_tert_bcr, 0xa3010);
 check_member(x1p42100_gcc, gcc_usb30_mp_bcr, 0x17000);
 check_member(x1p42100_gcc, qup_wrap1_s, 0x18004);
 check_member(x1p42100_gcc, gcc_usb30_mp_master_cbcr, 0x17018);
 check_member(x1p42100_gcc, gcc_usb30_mp_sleep_cbcr, 0x17024);
 check_member(x1p42100_gcc, gcc_usb3_mp_phy_aux_cbcr, 0x17288);
-check_member(x1p42100_gcc, gcc_cfg_noc_usb3_mp_axi_cbcr, 0x173CC);
+check_member(x1p42100_gcc, gcc_cfg_noc_usb3_mp_axi_cbcr, 0x173cc);
 check_member(x1p42100_gcc, qup_wrap2_s, 0x1e004);
 check_member(x1p42100_gcc, qup_wrap0_m_ahb_cbcr, 0x23000);
 check_member(x1p42100_gcc, qup_wrap0_core_cdivr, 0x23014);
@@ -338,11 +430,11 @@ check_member(x1p42100_gcc, qup_wrap1_core_2x, 0x23174);
 check_member(x1p42100_gcc, qup_wrap2_m_ahb_cbcr, 0x232a0);
 check_member(x1p42100_gcc, qup_wrap2_core_cdivr, 0x232b4);
 check_member(x1p42100_gcc, qup_wrap2_core_2x, 0x232c4);
-check_member(x1p42100_gcc, gcc_sys_noc_usb_axi_cbcr, 0x2D014);
-check_member(x1p42100_gcc, gcc_cfg_noc_usb_anoc_north_ahb_cbcr, 0x2D028);
-check_member(x1p42100_gcc, gcc_aggre_usb_noc_axi_cbcr, 0x2D034);
-check_member(x1p42100_gcc, gcc_aggre_noc_usb_south_axi_cbcr, 0x2D174);
-check_member(x1p42100_gcc, gcc_aggre_noc_usb_north_axi_cbcr, 0x2D17C);
+check_member(x1p42100_gcc, gcc_sys_noc_usb_axi_cbcr, 0x2d014);
+check_member(x1p42100_gcc, gcc_cfg_noc_usb_anoc_north_ahb_cbcr, 0x2d028);
+check_member(x1p42100_gcc, gcc_aggre_usb_noc_axi_cbcr, 0x2d034);
+check_member(x1p42100_gcc, gcc_aggre_noc_usb_south_axi_cbcr, 0x2d174);
+check_member(x1p42100_gcc, gcc_aggre_noc_usb_north_axi_cbcr, 0x2d17c);
 check_member(x1p42100_gcc, qup_wrap0_s, 0x42004);
 check_member(x1p42100_gcc, qspi_bcr, 0x4b000);
 check_member(x1p42100_gcc, apcs_clk_br_en, 0x52000);
@@ -437,6 +529,8 @@ enum clk_usb_gdsc {
 	USB30_MP_GDSC,
 	USB3_SS0_PHY_GDSC,
 	USB3_SS1_PHY_GDSC,
+	USB30_PRIM_GDSC,
+	USB30_SEC_GDSC,
 	MAX_USB_GDSC,
 };
 enum clk_usb {
@@ -458,9 +552,46 @@ enum clk_usb {
 	USB_CLK_COUNT,
 };
 
+enum clk_usb_prim {
+	USB_PRIM_SYS_NOC_USB_AXI_CBCR,
+	USB_PRIM_CFG_NOC_USB_ANOC_AHB_CBCR,
+	USB_PRIM_CFG_NOC_USB_ANOC_NORTH_AHB_CBCR,
+	USB_PRIM_CFG_NOC_USB_ANOC_SOUTH_AHB_CBCR,
+	USB_PRIM_AGGRE_USB_NOC_AXI_CBCR,
+	USB_PRIM_AGGRE_NOC_USB_SOUTH_AXI_CBCR,
+	USB_PRIM_AGGRE_NOC_USB_NORTH_AXI_CBCR,
+	USB_PRIM_USB30_PRIM_MASTER_CBCR,
+	USB_PRIM_USB30_PRIM_SLEEP_CBCR,
+	USB_PRIM_USB30_PRIM_MOCK_UTMI_CBCR,
+	USB_PRIM_USB3_PRIM_PHY_AUX_CBCR,
+	USB_PRIM_USB3_PRIM_PHY_COM_AUX_CBCR,
+	USB_PRIM_USB3_PRIM_PHY_PIPE_CBCR,
+	USB_PRIM_CFG_NOC_USB3_PRIM_AXI_CBCR,
+	USB_PRIM_AGGRE_USB3_PRIM_AXI_CBCR,
+	USB_PRIM_CLK_COUNT,
+};
+
+enum clk_usb_sec {
+	USB_SEC_CFG_NOC_USB3_SEC_AXI_CBCR,
+	USB_SEC_AGGRE_USB3_SEC_AXI_CBCR,
+	USB_SEC_USB30_SEC_MASTER_CBCR,
+	USB_SEC_USB30_SEC_SLEEP_CBCR,
+	USB_SEC_USB30_SEC_MOCK_UTMI_CBCR,
+	USB_SEC_USB3_SEC_PHY_AUX_CBCR,
+	USB_SEC_USB3_SEC_PHY_COM_AUX_CBCR,
+	USB_SEC_USB3_SEC_PHY_PIPE_CBCR,
+	USB_SEC_AGGRE_USB_NOC_AXI_CBCR,
+	USB_SEC_AGGRE_NOC_USB_NORTH_AXI_CBCR,
+	USB_SEC_AGGRE_NOC_USB_SOUTH_AXI_CBCR,
+	USB_SEC_SYS_NOC_USB_AXI_CBCR,
+	USB_SEC_CLK_COUNT,
+};
+
 enum clk_pipe_usb {
 	USB3_PHY_PIPE_0,
 	USB3_PHY_PIPE_1,
+	USB3_PRIM_PHY_PIPE,
+	USB3_SEC_PHY_PIPE,
 	USB3_PIPE_CLK_COUNT
 };
 
@@ -486,7 +617,13 @@ enum cb_err clock_configure_mux(enum clk_pcie clk_type, u32 src_type);
 enum cb_err usb_clock_configure_mux(enum clk_pipe_usb clk_type, u32 src_type);
 enum cb_err usb_clock_enable(enum clk_usb clk_type);
 enum cb_err clock_enable_usb_gdsc(enum clk_usb_gdsc gdsc_type);
+enum cb_err usb_prim_clock_enable(enum clk_usb_prim clk_type);
+enum cb_err usb_sec_clock_enable(enum clk_usb_sec clk_type);
+
 void usb_clock_reset(enum clk_usb clk_type, bool assert);
+void usb_prim_clock_reset(enum clk_usb_prim clk_type, bool assert);
+void usb_sec_clock_reset(enum clk_usb_sec clk_type, bool assert);
+
 /* Subsystem Reset */
 static struct aoss *const aoss = (void *)AOSS_CC_BASE;
 static struct x1p42100_gcc *const gcc = (void *)GCC_BASE;

From 45cedbb9922e18533ba292e3dc65cee16d07d640 Mon Sep 17 00:00:00 2001
From: Hari L <haril@qualcomm.corp-partner.google.com>
Date: Mon, 29 Sep 2025 21:27:20 +0530
Subject: [PATCH 2209/3886] soc/qualcomm/x1p42100: Add HS/SS PHY support for
 USB Type-C ports

Add HS/SS Phy for USB Type-C primary and secondary USB Type-C ports.
The register details are part of HRD-X1P42100-S1 document.
https://docs.qualcomm.com/bundle/resource/topics/HRD-X1P42100-S1/

TEST=Boot from USB-C key on Google/Quenbi.

SS PHY used for Type-A and Type-C ports have different register layout.
[register address may vary for a similar register name]
USB4_USB3_EDP_DP_Con PHY Configuration - Type-C
USB3 Gen2 UNI PHY Configuration - Type-A
Hence it cannot be shared

Console logs:
[INFO ]  Setting up USB HOST controller.
[DEBUG]  USB HS PHY initialized for index 0
[DEBUG]  USB HS PHY initialized for index 1
[DEBUG]  QMP PHY MP0 init
[DEBUG]  QMP PHY MP0 initialized and locked in 1674us
[DEBUG]  QMP PHY MP1 init
[DEBUG]  QMP PHY MP1 initialized and locked in 1674us
[DEBUG]  USB HS PHY initialized for index 2
[DEBUG]  QMP-1x16 USB4 DP PHY SS0 init
[DEBUG]  QMP PHY SS0 initialized and locked in 1672us, phy_status: 0x86868686
[INFO ]  Enabling SMB1 VBUS SuperSpeed
[DEBUG]  SMB1 OTG Status: 0x00, State: 0x00
[ERROR]  SMB1 OTG enable timeout after 100 ms, final state: 0x00
[ERROR]  SMB1 OTG enable failed
[INFO ]  SMB1 Type-C Status:
[INFO ]    Misc Status (0x2B0B): 0x3b
[INFO ]    Src Status (0x2B08): 0x00
[INFO ]    Mode Config (0x2B44): 0x00
[DEBUG]  USB HS PHY initialized for index 3
[DEBUG]  QMP-1x16 USB4 DP PHY SS1 init
[DEBUG]  QMP PHY SS1 initialized and locked in 1672us, phy_status: 0x86868686
[INFO ]  Enabling SMB2 VBUS SuperSpeed
[DEBUG]  SMB2 OTG Status: 0x03, State: 0x03
[DEBUG]  SMB2 OTG Status: 0x02, State: 0x02
[INFO ]  SMB2 OTG block enabled successfully
[INFO ]  SMB2 Type-C Status:
[INFO ]    Misc Status (0x2B0B): 0x49, VBUS Status (bit 5): 0
[INFO ]    Src Status (0x2B08): 0x08
[INFO ]    Mode Config (0x2B44): 0x00
[SPEW ]  Configure USB in Host mode
[SPEW ]  Configure USB Primary in Host mode
[SPEW ]  Configure USB Secondary in Host mode
[INFO ]  DWC3 and PHY setup finished

Change-Id: Icfec6f00ea41032e4fd17a5d99dea7529ef347fc
Signed-off-by: Hari L <haril@qualcomm.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89372
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
---
 src/soc/qualcomm/x1p42100/Makefile.mk         |   1 +
 .../x1p42100/include/soc/usb/qmp_usb_phy.h    |  17 +
 .../qualcomm/x1p42100/usb/qmpv4_usb4_dp_phy.c | 630 ++++++++++++++++++
 src/soc/qualcomm/x1p42100/usb/snps_usb_phy.c  |  20 +-
 4 files changed, 666 insertions(+), 2 deletions(-)
 create mode 100644 src/soc/qualcomm/x1p42100/usb/qmpv4_usb4_dp_phy.c

diff --git a/src/soc/qualcomm/x1p42100/Makefile.mk b/src/soc/qualcomm/x1p42100/Makefile.mk
index c7e39a8a12..7325d9bf7a 100644
--- a/src/soc/qualcomm/x1p42100/Makefile.mk
+++ b/src/soc/qualcomm/x1p42100/Makefile.mk
@@ -46,6 +46,7 @@ ramstage-$(CONFIG_DRIVERS_UART) += ../common/qupv3_uart.c
 ramstage-y += usb/usb.c
 ramstage-y += usb/snps_usb_phy.c
 ramstage-y += usb/qmpv4_usb_phy.c
+ramstage-y += usb/qmpv4_usb4_dp_phy.c
 ramstage-$(CONFIG_PCI) += ../common/pcie_common.c
 ramstage-y += ../common/spmi.c
 ramstage-$(CONFIG_PCI) += pcie.c
diff --git a/src/soc/qualcomm/x1p42100/include/soc/usb/qmp_usb_phy.h b/src/soc/qualcomm/x1p42100/include/soc/usb/qmp_usb_phy.h
index e463c61b82..6a5069844f 100644
--- a/src/soc/qualcomm/x1p42100/include/soc/usb/qmp_usb_phy.h
+++ b/src/soc/qualcomm/x1p42100/include/soc/usb/qmp_usb_phy.h
@@ -5,6 +5,17 @@
 /* USB3PHY_PCIE_USB3_PCS_PCS_STATUS bit */
 #define USB3_PCS_PHYSTATUS		BIT(6)
 
+/* PCS Control Register Values */
+#define PCS_SW_RESET_DEASSERT		0x00
+#define QPHY_PCS_START			BIT(0)
+#define QPHY_SERDES_START			BIT(1)
+
+/* USB43DP_COM_TYPEC_CTRL register bit definitions */
+#define SW_PORTSELECT_SHIFT     0
+#define SW_PORTSELECT_MUX_SHIFT 1
+#define SW_PORTSELECT_MASK      BIT(SW_PORTSELECT_SHIFT)
+#define SW_PORTSELECT_MUX_MASK  BIT(SW_PORTSELECT_MUX_SHIFT)
+
 /* Define qmp_phy_init_tbl to use offsets instead of absolute addresses.
 This makes the tables generic and reusable */
 typedef struct qmp_phy_init_tbl {
@@ -15,8 +26,11 @@ typedef struct qmp_phy_init_tbl {
 /* Structure to encapsulate base addresses and configuration tables for a specific PHY instance */
 struct ss_usb_phy_reg {
 	void *com_base;
+	void *qserdes_pll_base;
 	void *tx_base;
 	void *rx_base;
+	void *txb_base;
+	void *rxb_base;
 	void *pcs_base;
 	void *pcs_usb3_base;
 	const char *name;
@@ -34,3 +48,6 @@ struct ss_usb_phy_reg {
 };
 /* Initialize a specific QMP USB3 PHY instance */
 bool ss_qmp_phy_init(u32 phy_idx);
+
+/* Initialize SS0/SS1 QMP PHY - pass 0 for SS0, 1 for SS1 */
+enum cb_err qmp_usb4_dp_phy_ss_init(int phy_instance);
diff --git a/src/soc/qualcomm/x1p42100/usb/qmpv4_usb4_dp_phy.c b/src/soc/qualcomm/x1p42100/usb/qmpv4_usb4_dp_phy.c
new file mode 100644
index 0000000000..6da080be6e
--- /dev/null
+++ b/src/soc/qualcomm/x1p42100/usb/qmpv4_usb4_dp_phy.c
@@ -0,0 +1,630 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+#include <console/console.h>
+#include <timer.h>
+#include <delay.h>
+#include <soc/usb/qmp_usb_phy.h>
+#include <soc/addressmap.h>
+
+/* Only for QMP V4 PHY - TX registers */
+struct usb3_phy_qserdes_tx_reg_layout {
+	u8 _reserved1[48];			/* 0x00-0x2F */
+	u32 tx_res_code_lane_offset_tx;		/* 0x30 */
+	u32 tx_res_code_lane_offset_rx;		/* 0x34 */
+	u8 _reserved2[64];			/* 0x38-0x77 */
+	u32 tx_lane_mode_1;			/* 0x78 */
+	u32 tx_lane_mode_2;			/* 0x7C */
+	u32 tx_lane_mode_3;			/* 0x80 */
+	u8 _reserved3[184];			/* 0x84-0x13B (rest of registers) */
+} __packed;
+
+check_member(usb3_phy_qserdes_tx_reg_layout, tx_res_code_lane_offset_tx, 0x30);
+check_member(usb3_phy_qserdes_tx_reg_layout, tx_res_code_lane_offset_rx, 0x34);
+check_member(usb3_phy_qserdes_tx_reg_layout, tx_lane_mode_1, 0x78);
+check_member(usb3_phy_qserdes_tx_reg_layout, tx_lane_mode_2, 0x7C);
+check_member(usb3_phy_qserdes_tx_reg_layout, tx_lane_mode_3, 0x80);
+
+/* Only for QMP V4 PHY - RX registers */
+struct usb3_phy_qserdes_rx_reg_layout {
+	u8 _reserved1[8];			/* 0x00-0x07 */
+	u32 rx_ucdr_fo_gain_rate2;		/* 0x08 */
+	u8 _reserved2[12];			/* 0x0C-0x17 */
+	u32 rx_ucdr_so_gain_rate2;		/* 0x18 */
+	u8 _reserved3[4];			/* 0x1C-0x1F */
+	u32 rx_ucdr_pi_controls;		/* 0x20 */
+	u8 _reserved4[112];			/* 0x24-0x93 */
+	u32 rx_ivcm_cal_code_override;		/* 0x94 */
+	u8 _reserved5[4];			/* 0x98-0x9B */
+	u32 rx_ivcm_cal_ctrl2;			/* 0x9C */
+	u32 rx_ivcm_postcal_offset;		/* 0xA0 */
+	u8 _reserved6[16];			/* 0xA4-0xB3 */
+	u32 rx_dfe_3;				/* 0xB4 */
+	u8 _reserved7[40];			/* 0xB8-0xDF */
+	u32 rx_vga_cal_cntrl1;			/* 0xE0 */
+	u8 _reserved8[4];			/* 0xE4-0xE7 */
+	u32 rx_vga_cal_man_val;			/* 0xE8 */
+	u8 _reserved9[32];			/* 0xEC-0x10B */
+	u32 rx_gm_cal;				/* 0x10C */
+	u8 _reserved10[56];			/* 0x110-0x147 */
+	u32 rx_sigdet_enables;			/* 0x148 */
+	u32 rx_sigdet_cntrl;			/* 0x14C */
+	u8 _reserved11[4];			/* 0x150-0x153 */
+	u32 rx_sigdet_deglitch_cntrl;		/* 0x154 */
+	u8 _reserved12[60];			/* 0x158-0x193 */
+	u32 rx_dfe_ctle_post_cal_offset;	/* 0x194 */
+	u8 _reserved13[68];			/* 0x198-0x1DB */
+	u32 rx_q_pi_intrinsic_bias_rate32;	/* 0x1DC */
+	u8 _reserved14[92];			/* 0x1E0-0x23B */
+	u32 rx_ucdr_pi_ctrl1;			/* 0x23C */
+	u32 rx_ucdr_pi_ctrl2;			/* 0x240 */
+	u8 _reserved15[56];			/* 0x244-0x27B */
+	u32 rx_ucdr_sb2_gain2_rate2;		/* 0x27C */
+	u8 _reserved16[24];			/* 0x280-0x297 */
+	u32 rx_dfe_dac_enable1;			/* 0x298 */
+	u8 _reserved17[28];			/* 0x29C-0x2B7 */
+	u32 rx_mode_rate_0_1_b0;		/* 0x2B8 */
+	u32 rx_mode_rate_0_1_b1;		/* 0x2BC */
+	u32 rx_mode_rate_0_1_b2;		/* 0x2C0 */
+	u32 rx_mode_rate_0_1_b3;		/* 0x2C4 */
+	u32 rx_mode_rate_0_1_b4;		/* 0x2C8 */
+	u32 rx_mode_rate_0_1_b5;		/* 0x2CC */
+	u32 rx_mode_rate_0_1_b6;		/* 0x2D0 */
+	u32 rx_mode_rate2_b0;			/* 0x2D4 */
+	u32 rx_mode_rate2_b1;			/* 0x2D8 */
+	u32 rx_mode_rate2_b2;			/* 0x2DC */
+	u32 rx_mode_rate2_b3;			/* 0x2E0 */
+	u32 rx_mode_rate2_b4;			/* 0x2E4 */
+	u32 rx_mode_rate2_b5;			/* 0x2E8 */
+	u32 rx_mode_rate2_b6;			/* 0x2EC */
+	u8 _reserved18[28];			/* 0x2F0-0x30B */
+	u32 rx_summer_cal_spd_mode;		/* 0x30C */
+	u32 rx_bkup_ctrl1;			/* 0x310 */
+	u8 _reserved19[812];			/* 0x314-0x63F (remaining space) */
+} __packed;
+
+check_member(usb3_phy_qserdes_rx_reg_layout, rx_ucdr_fo_gain_rate2, 0x08);
+check_member(usb3_phy_qserdes_rx_reg_layout, rx_ucdr_so_gain_rate2, 0x18);
+check_member(usb3_phy_qserdes_rx_reg_layout, rx_ucdr_pi_controls, 0x20);
+check_member(usb3_phy_qserdes_rx_reg_layout, rx_ivcm_cal_code_override, 0x94);
+check_member(usb3_phy_qserdes_rx_reg_layout, rx_ivcm_cal_ctrl2, 0x9C);
+check_member(usb3_phy_qserdes_rx_reg_layout, rx_ivcm_postcal_offset, 0xA0);
+check_member(usb3_phy_qserdes_rx_reg_layout, rx_dfe_3, 0xB4);
+check_member(usb3_phy_qserdes_rx_reg_layout, rx_vga_cal_cntrl1, 0xE0);
+check_member(usb3_phy_qserdes_rx_reg_layout, rx_vga_cal_man_val, 0xE8);
+check_member(usb3_phy_qserdes_rx_reg_layout, rx_gm_cal, 0x10C);
+check_member(usb3_phy_qserdes_rx_reg_layout, rx_sigdet_enables, 0x148);
+check_member(usb3_phy_qserdes_rx_reg_layout, rx_sigdet_cntrl, 0x14C);
+check_member(usb3_phy_qserdes_rx_reg_layout, rx_sigdet_deglitch_cntrl, 0x154);
+check_member(usb3_phy_qserdes_rx_reg_layout, rx_dfe_ctle_post_cal_offset, 0x194);
+check_member(usb3_phy_qserdes_rx_reg_layout, rx_q_pi_intrinsic_bias_rate32, 0x1DC);
+check_member(usb3_phy_qserdes_rx_reg_layout, rx_ucdr_pi_ctrl1, 0x23C);
+check_member(usb3_phy_qserdes_rx_reg_layout, rx_ucdr_pi_ctrl2, 0x240);
+check_member(usb3_phy_qserdes_rx_reg_layout, rx_ucdr_sb2_gain2_rate2, 0x27C);
+check_member(usb3_phy_qserdes_rx_reg_layout, rx_dfe_dac_enable1, 0x298);
+check_member(usb3_phy_qserdes_rx_reg_layout, rx_mode_rate_0_1_b0, 0x2B8);
+check_member(usb3_phy_qserdes_rx_reg_layout, rx_mode_rate_0_1_b1, 0x2BC);
+check_member(usb3_phy_qserdes_rx_reg_layout, rx_mode_rate_0_1_b2, 0x2C0);
+check_member(usb3_phy_qserdes_rx_reg_layout, rx_mode_rate_0_1_b3, 0x2C4);
+check_member(usb3_phy_qserdes_rx_reg_layout, rx_mode_rate_0_1_b4, 0x2C8);
+check_member(usb3_phy_qserdes_rx_reg_layout, rx_mode_rate_0_1_b5, 0x2CC);
+check_member(usb3_phy_qserdes_rx_reg_layout, rx_mode_rate_0_1_b6, 0x2D0);
+check_member(usb3_phy_qserdes_rx_reg_layout, rx_mode_rate2_b0, 0x2D4);
+check_member(usb3_phy_qserdes_rx_reg_layout, rx_mode_rate2_b1, 0x2D8);
+check_member(usb3_phy_qserdes_rx_reg_layout, rx_mode_rate2_b2, 0x2DC);
+check_member(usb3_phy_qserdes_rx_reg_layout, rx_mode_rate2_b3, 0x2E0);
+check_member(usb3_phy_qserdes_rx_reg_layout, rx_mode_rate2_b4, 0x2E4);
+check_member(usb3_phy_qserdes_rx_reg_layout, rx_mode_rate2_b5, 0x2E8);
+check_member(usb3_phy_qserdes_rx_reg_layout, rx_mode_rate2_b6, 0x2EC);
+check_member(usb3_phy_qserdes_rx_reg_layout, rx_summer_cal_spd_mode, 0x30C);
+check_member(usb3_phy_qserdes_rx_reg_layout, rx_bkup_ctrl1, 0x310);
+
+/* Only for QMP V4 PHY - PCS registers */
+struct usb3_phy_pcs_reg_layout {
+	u32 pcs_sw_reset;			/* 0x00 */
+	u8 _reserved1[16];			/* 0x04-0x13 */
+	u32 pcs_pcs_status1;			/* 0x14 */
+	u8 _reserved2[40];			/* 0x18-0x3F */
+	u32 pcs_power_down_control;		/* 0x40 */
+	u32 pcs_start_control;			/* 0x44 */
+	u8 _reserved3[124];			/* 0x48-0xC3 */
+	u32 pcs_lock_detect_config1;		/* 0xC4 */
+	u32 pcs_lock_detect_config2;		/* 0xC8 */
+	u32 pcs_lock_detect_config3;		/* 0xCC */
+	u8 _reserved4[8];			/* 0xD0-0xD7 */
+	u32 pcs_lock_detect_config6;		/* 0xD8 */
+	u32 pcs_refgen_req_config1;		/* 0xDC */
+	u8 _reserved5[168];			/* 0xE0-0x187 */
+	u32 pcs_rx_sigdet_lvl;			/* 0x188 */
+	u8 _reserved6[4];			/* 0x18C-0x18F */
+	u32 pcs_rcvr_dtct_dly_p1u2_l;		/* 0x190 */
+	u32 pcs_rcvr_dtct_dly_p1u2_h;		/* 0x194 */
+	u8 _reserved7[24];			/* 0x198-0x1AF */
+	u32 pcs_rx_config;			/* 0x1B0 */
+	u8 _reserved8[12];			/* 0x1B4-0x1BF */
+	u32 pcs_align_detect_config1;		/* 0x1C0 */
+	u32 pcs_align_detect_config2;		/* 0x1C4 */
+	u8 _reserved9[8];			/* 0x1C8-0x1CF */
+	u32 pcs_pcs_tx_rx_config;		/* 0x1D0 */
+	u8 _reserved10[8];			/* 0x1D4-0x1DB */
+	u32 pcs_eq_config1;			/* 0x1DC */
+	u8 _reserved11[12];			/* 0x1E0-0x1EB */
+	u32 pcs_eq_config5;			/* 0x1EC */
+	u8 _reserved12[20];			/* 0x1F0-0x203 (remaining space) */
+} __packed;
+
+check_member(usb3_phy_pcs_reg_layout, pcs_sw_reset, 0x00);
+check_member(usb3_phy_pcs_reg_layout, pcs_pcs_status1, 0x14);
+check_member(usb3_phy_pcs_reg_layout, pcs_power_down_control, 0x40);
+check_member(usb3_phy_pcs_reg_layout, pcs_start_control, 0x44);
+check_member(usb3_phy_pcs_reg_layout, pcs_lock_detect_config1, 0xC4);
+check_member(usb3_phy_pcs_reg_layout, pcs_lock_detect_config2, 0xC8);
+check_member(usb3_phy_pcs_reg_layout, pcs_lock_detect_config3, 0xCC);
+check_member(usb3_phy_pcs_reg_layout, pcs_lock_detect_config6, 0xD8);
+check_member(usb3_phy_pcs_reg_layout, pcs_refgen_req_config1, 0xDC);
+check_member(usb3_phy_pcs_reg_layout, pcs_rx_sigdet_lvl, 0x188);
+check_member(usb3_phy_pcs_reg_layout, pcs_rcvr_dtct_dly_p1u2_l, 0x190);
+check_member(usb3_phy_pcs_reg_layout, pcs_rcvr_dtct_dly_p1u2_h, 0x194);
+check_member(usb3_phy_pcs_reg_layout, pcs_rx_config, 0x1B0);
+check_member(usb3_phy_pcs_reg_layout, pcs_align_detect_config1, 0x1C0);
+check_member(usb3_phy_pcs_reg_layout, pcs_align_detect_config2, 0x1C4);
+check_member(usb3_phy_pcs_reg_layout, pcs_pcs_tx_rx_config, 0x1D0);
+check_member(usb3_phy_pcs_reg_layout, pcs_eq_config1, 0x1DC);
+check_member(usb3_phy_pcs_reg_layout, pcs_eq_config5, 0x1EC);
+
+/* Only for QMP V4 PHY - PCS USB3 registers */
+struct usb3_phy_pcs_usb3_reg_layout {
+	u8 _reserved1[24];			/* 0x00-0x17 */
+	u32 pcs_usb3_lfps_det_high_count_val;	/* 0x18 */
+	u8 _reserved2[32];			/* 0x1C-0x3B */
+	u32 pcs_usb3_rxeqtraining_dfe_time_s2;	/* 0x3C */
+	u32 pcs_usb3_rcvr_dtct_dly_u3_l;	/* 0x40 */
+	u32 pcs_usb3_rcvr_dtct_dly_u3_h;	/* 0x44 */
+	u8 _reserved3[184];			/* 0x48-0xFF (remaining space) */
+} __packed;
+
+check_member(usb3_phy_pcs_usb3_reg_layout, pcs_usb3_lfps_det_high_count_val, 0x18);
+check_member(usb3_phy_pcs_usb3_reg_layout, pcs_usb3_rxeqtraining_dfe_time_s2, 0x3C);
+check_member(usb3_phy_pcs_usb3_reg_layout, pcs_usb3_rcvr_dtct_dly_u3_l, 0x40);
+check_member(usb3_phy_pcs_usb3_reg_layout, pcs_usb3_rcvr_dtct_dly_u3_h, 0x44);
+
+/* USB43DP_COM registers */
+struct usb43dp_com_reg_layout {
+	u32 phy_mode_ctrl;			/* 0x00 */
+	u32 sw_reset;				/* 0x04 */
+	u32 power_down_ctrl;			/* 0x08 */
+	u32 swi_ctrl;				/* 0x0C */
+	u32 typec_ctrl;				/* 0x10 */
+	u32 typec_pwrdn_ctrl;			/* 0x14 */
+	u32 dp_bist_cfg_0;			/* 0x18 */
+	u32 reset_ovrd_ctrl1;			/* 0x1C */
+	u32 reset_ovrd_ctrl2;			/* 0x20 */
+	u32 dbg_clk_mux_ctrl;			/* 0x24 */
+	u32 typec_status;			/* 0x28 */
+	u32 placeholder_status;			/* 0x2C */
+	u32 revision_id0;			/* 0x30 */
+	u32 revision_id1;			/* 0x34 */
+	u32 revision_id2;			/* 0x38 */
+	u32 revision_id3;			/* 0x3C */
+} __packed;
+
+check_member(usb43dp_com_reg_layout, phy_mode_ctrl, 0x00);
+check_member(usb43dp_com_reg_layout, sw_reset, 0x04);
+check_member(usb43dp_com_reg_layout, power_down_ctrl, 0x08);
+check_member(usb43dp_com_reg_layout, swi_ctrl, 0x0C);
+check_member(usb43dp_com_reg_layout, typec_ctrl, 0x10);
+check_member(usb43dp_com_reg_layout, typec_pwrdn_ctrl, 0x14);
+check_member(usb43dp_com_reg_layout, dp_bist_cfg_0, 0x18);
+check_member(usb43dp_com_reg_layout, reset_ovrd_ctrl1, 0x1C);
+check_member(usb43dp_com_reg_layout, reset_ovrd_ctrl2, 0x20);
+check_member(usb43dp_com_reg_layout, dbg_clk_mux_ctrl, 0x24);
+check_member(usb43dp_com_reg_layout, typec_status, 0x28);
+check_member(usb43dp_com_reg_layout, placeholder_status, 0x2C);
+check_member(usb43dp_com_reg_layout, revision_id0, 0x30);
+check_member(usb43dp_com_reg_layout, revision_id1, 0x34);
+check_member(usb43dp_com_reg_layout, revision_id2, 0x38);
+check_member(usb43dp_com_reg_layout, revision_id3, 0x3C);
+
+static const qmp_phy_init_tbl_t qmp_v4_usb3_ss0_com_tbl[] = {
+	{offsetof(struct usb43dp_com_reg_layout, power_down_ctrl), 0x01},
+	{offsetof(struct usb43dp_com_reg_layout, reset_ovrd_ctrl1), 0x15},
+};
+
+/* USB3_QSERDES_PLL table */
+struct usb3_qserdes_pll_reg_layout {
+	u32 ssc_step_size1_mode1;		/* 0x00 */
+	u32 ssc_step_size2_mode1;		/* 0x04 */
+	u8 _reserved1[8];			/* 0x08-0x0F */
+	u32 cp_ctrl_mode1;			/* 0x10 */
+	u32 pll_rctrl_mode1;			/* 0x14 */
+	u32 pll_cctrl_mode1;			/* 0x18 */
+	u32 coreclk_div_mode1;			/* 0x1C */
+	u32 lock_cmp1_mode1;			/* 0x20 */
+	u32 lock_cmp2_mode1;			/* 0x24 */
+	u32 dec_start_mode1;			/* 0x28 */
+	u32 dec_start_msb_mode1;		/* 0x2C */
+	u32 div_frac_start1_mode1;		/* 0x30 */
+	u32 div_frac_start2_mode1;		/* 0x34 */
+	u32 div_frac_start3_mode1;		/* 0x38 */
+	u32 hsclk_sel_1;			/* 0x3C */
+	u32 integloop_gain0_mode1;		/* 0x40 */
+	u8 _reserved3[4];			/* 0x44-0x47 */
+	u32 vco_tune1_mode1;			/* 0x48 */
+	u32 vco_tune2_mode1;			/* 0x4C */
+	u8 _reserved4[16];			/* 0x50-0x5F */
+	u32 ssc_step_size1_mode0;		/* 0x60 */
+	u32 ssc_step_size2_mode0;		/* 0x64 */
+	u8 _reserved5[8];			/* 0x68-0x6F */
+	u32 cp_ctrl_mode0;			/* 0x70 */
+	u32 pll_rctrl_mode0;			/* 0x74 */
+	u32 pll_cctrl_mode0;			/* 0x78 */
+	u32 coreclk_div_mode0;			/* 0x7C */
+	u32 lock_cmp1_mode0;			/* 0x80 */
+	u32 lock_cmp2_mode0;			/* 0x84 */
+	u32 dec_start_mode0;			/* 0x88 */
+	u32 dec_start_msb_mode0;		/* 0x8C */
+	u32 div_frac_start1_mode0;		/* 0x90 */
+	u32 div_frac_start2_mode0;		/* 0x94 */
+	u32 div_frac_start3_mode0;		/* 0x98 */
+	u32 hsclk_hs_switch_sel_1;		/* 0x9C */
+	u32 integloop_gain0_mode0;		/* 0xA0 */
+	u8 _reserved6[4];			/* 0xA4-0xA7 */
+	u32 vco_tune1_mode0;			/* 0xA8 */
+	u32 vco_tune2_mode0;			/* 0xAC */
+	u8 _reserved7[12];			/* 0xB0-0xBB */
+	u32 bg_timer;				/* 0xBC */
+	u32 ssc_en_center;			/* 0xC0 */
+	u8 _reserved8[8];			/* 0xC4-0xCB */
+	u32 ssc_per1;				/* 0xCC */
+	u32 ssc_per2;				/* 0xD0 */
+	u8 _reserved9[20];			/* 0xD4-0xE7 */
+	u32 sysclk_buf_enable;			/* 0xE8 */
+	u8 _reserved10[4];			/* 0xEC-0xEF */
+	u8 _reserved11[4];			/* 0xF0-0xF3 */
+	u32 pll_ivco;				/* 0xF4 */
+	u32 pll_ivco_mode1;			/* 0xF8 */
+	u8 _reserved12[16];			/* 0xFC-0x10B */
+	u8 _reserved13[4];			/* 0x10C-0x10F */
+	u32 sysclk_en_sel;			/* 0x110 */
+	u8 _reserved14[8];			/* 0x114-0x11B */
+	u8 _reserved15[4];			/* 0x11C-0x11F */
+	u32 lock_cmp_en;			/* 0x120 */
+	u32 lock_cmp_cfg;			/* 0x124 */
+	u8 _reserved16[24];			/* 0x128-0x13F */
+	u32 vco_tune_map;			/* 0x140 */
+	u8 _reserved17[4];			/* 0x144-0x147 */
+	u32 vco_tune_initval2;			/* 0x148 */
+	u8 _reserved18[12];			/* 0x14C-0x157 */
+	u32 vco_tune_maxval2;			/* 0x158 */
+	u8 _reserved19[20];			/* 0x15C-0x16F */
+	u32 core_clk_en;			/* 0x170 */
+	u32 cmn_config_1;			/* 0x174 */
+	u8 _reserved20[4];			/* 0x178-0x17B */
+	u32 svs_mode_clk_sel;			/* 0x17C */
+	u8 _reserved21[128];			/* 0x180-0x1FF (remaining space) */
+} __packed;
+
+check_member(usb3_qserdes_pll_reg_layout, ssc_step_size1_mode1, 0x00);
+check_member(usb3_qserdes_pll_reg_layout, ssc_step_size2_mode1, 0x04);
+check_member(usb3_qserdes_pll_reg_layout, cp_ctrl_mode1, 0x10);
+check_member(usb3_qserdes_pll_reg_layout, pll_rctrl_mode1, 0x14);
+check_member(usb3_qserdes_pll_reg_layout, pll_cctrl_mode1, 0x18);
+check_member(usb3_qserdes_pll_reg_layout, coreclk_div_mode1, 0x1C);
+check_member(usb3_qserdes_pll_reg_layout, lock_cmp1_mode1, 0x20);
+check_member(usb3_qserdes_pll_reg_layout, lock_cmp2_mode1, 0x24);
+check_member(usb3_qserdes_pll_reg_layout, dec_start_mode1, 0x28);
+check_member(usb3_qserdes_pll_reg_layout, dec_start_msb_mode1, 0x2C);
+check_member(usb3_qserdes_pll_reg_layout, div_frac_start1_mode1, 0x30);
+check_member(usb3_qserdes_pll_reg_layout, div_frac_start2_mode1, 0x34);
+check_member(usb3_qserdes_pll_reg_layout, div_frac_start3_mode1, 0x38);
+check_member(usb3_qserdes_pll_reg_layout, hsclk_sel_1, 0x3C);
+check_member(usb3_qserdes_pll_reg_layout, integloop_gain0_mode1, 0x40);
+check_member(usb3_qserdes_pll_reg_layout, vco_tune1_mode1, 0x48);
+check_member(usb3_qserdes_pll_reg_layout, vco_tune2_mode1, 0x4C);
+check_member(usb3_qserdes_pll_reg_layout, ssc_step_size1_mode0, 0x60);
+check_member(usb3_qserdes_pll_reg_layout, ssc_step_size2_mode0, 0x64);
+check_member(usb3_qserdes_pll_reg_layout, cp_ctrl_mode0, 0x70);
+check_member(usb3_qserdes_pll_reg_layout, pll_rctrl_mode0, 0x74);
+check_member(usb3_qserdes_pll_reg_layout, pll_cctrl_mode0, 0x78);
+check_member(usb3_qserdes_pll_reg_layout, coreclk_div_mode0, 0x7C);
+check_member(usb3_qserdes_pll_reg_layout, lock_cmp1_mode0, 0x80);
+check_member(usb3_qserdes_pll_reg_layout, lock_cmp2_mode0, 0x84);
+check_member(usb3_qserdes_pll_reg_layout, dec_start_mode0, 0x88);
+check_member(usb3_qserdes_pll_reg_layout, dec_start_msb_mode0, 0x8C);
+check_member(usb3_qserdes_pll_reg_layout, div_frac_start1_mode0, 0x90);
+check_member(usb3_qserdes_pll_reg_layout, div_frac_start2_mode0, 0x94);
+check_member(usb3_qserdes_pll_reg_layout, div_frac_start3_mode0, 0x98);
+check_member(usb3_qserdes_pll_reg_layout, hsclk_hs_switch_sel_1, 0x9C);
+check_member(usb3_qserdes_pll_reg_layout, integloop_gain0_mode0, 0xA0);
+check_member(usb3_qserdes_pll_reg_layout, vco_tune1_mode0, 0xA8);
+check_member(usb3_qserdes_pll_reg_layout, vco_tune2_mode0, 0xAC);
+check_member(usb3_qserdes_pll_reg_layout, bg_timer, 0xBC);
+check_member(usb3_qserdes_pll_reg_layout, ssc_en_center, 0xC0);
+check_member(usb3_qserdes_pll_reg_layout, ssc_per1, 0xCC);
+check_member(usb3_qserdes_pll_reg_layout, ssc_per2, 0xD0);
+check_member(usb3_qserdes_pll_reg_layout, sysclk_buf_enable, 0xE8);
+check_member(usb3_qserdes_pll_reg_layout, pll_ivco, 0xF4);
+check_member(usb3_qserdes_pll_reg_layout, pll_ivco_mode1, 0xF8);
+check_member(usb3_qserdes_pll_reg_layout, sysclk_en_sel, 0x110);
+check_member(usb3_qserdes_pll_reg_layout, lock_cmp_en, 0x120);
+check_member(usb3_qserdes_pll_reg_layout, lock_cmp_cfg, 0x124);
+check_member(usb3_qserdes_pll_reg_layout, vco_tune_map, 0x140);
+check_member(usb3_qserdes_pll_reg_layout, vco_tune_initval2, 0x148);
+check_member(usb3_qserdes_pll_reg_layout, vco_tune_maxval2, 0x158);
+check_member(usb3_qserdes_pll_reg_layout, core_clk_en, 0x170);
+check_member(usb3_qserdes_pll_reg_layout, cmn_config_1, 0x174);
+check_member(usb3_qserdes_pll_reg_layout, svs_mode_clk_sel, 0x17C);
+
+/* QSERDES PLL table */
+static const qmp_phy_init_tbl_t qmp_v4_usb3_ss0_serdes_tbl[] = {
+	{offsetof(struct usb3_qserdes_pll_reg_layout, ssc_en_center), 0x01},
+	{offsetof(struct usb3_qserdes_pll_reg_layout, ssc_per1), 0x62},
+	{offsetof(struct usb3_qserdes_pll_reg_layout, ssc_per2), 0x02},
+	{offsetof(struct usb3_qserdes_pll_reg_layout, ssc_step_size1_mode0), 0xC2},
+	{offsetof(struct usb3_qserdes_pll_reg_layout, ssc_step_size2_mode0), 0x03},
+	{offsetof(struct usb3_qserdes_pll_reg_layout, ssc_step_size1_mode1), 0xC2},
+	{offsetof(struct usb3_qserdes_pll_reg_layout, ssc_step_size2_mode1), 0x03},
+	{offsetof(struct usb3_qserdes_pll_reg_layout, sysclk_buf_enable), 0x0A},
+	{offsetof(struct usb3_qserdes_pll_reg_layout, cp_ctrl_mode0), 0x02},
+	{offsetof(struct usb3_qserdes_pll_reg_layout, cp_ctrl_mode1), 0x02},
+	{offsetof(struct usb3_qserdes_pll_reg_layout, pll_rctrl_mode0), 0x16},
+	{offsetof(struct usb3_qserdes_pll_reg_layout, pll_rctrl_mode1), 0x16},
+	{offsetof(struct usb3_qserdes_pll_reg_layout, pll_cctrl_mode0), 0x36},
+	{offsetof(struct usb3_qserdes_pll_reg_layout, pll_cctrl_mode1), 0x36},
+	{offsetof(struct usb3_qserdes_pll_reg_layout, sysclk_en_sel), 0x1A},
+	{offsetof(struct usb3_qserdes_pll_reg_layout, lock_cmp_en), 0x04},
+	{offsetof(struct usb3_qserdes_pll_reg_layout, lock_cmp_cfg), 0x04},
+	{offsetof(struct usb3_qserdes_pll_reg_layout, lock_cmp1_mode0), 0x08},
+	{offsetof(struct usb3_qserdes_pll_reg_layout, lock_cmp2_mode0), 0x1A},
+	{offsetof(struct usb3_qserdes_pll_reg_layout, lock_cmp1_mode1), 0x16},
+	{offsetof(struct usb3_qserdes_pll_reg_layout, lock_cmp2_mode1), 0x41},
+	{offsetof(struct usb3_qserdes_pll_reg_layout, dec_start_mode0), 0x82},
+	{offsetof(struct usb3_qserdes_pll_reg_layout, dec_start_msb_mode0), 0x00},
+	{offsetof(struct usb3_qserdes_pll_reg_layout, dec_start_mode1), 0x82},
+	{offsetof(struct usb3_qserdes_pll_reg_layout, dec_start_msb_mode1), 0x00},
+	{offsetof(struct usb3_qserdes_pll_reg_layout, div_frac_start1_mode0), 0x55},
+	{offsetof(struct usb3_qserdes_pll_reg_layout, div_frac_start2_mode0), 0x55},
+	{offsetof(struct usb3_qserdes_pll_reg_layout, div_frac_start3_mode0), 0x03},
+	{offsetof(struct usb3_qserdes_pll_reg_layout, div_frac_start1_mode1), 0x55},
+	{offsetof(struct usb3_qserdes_pll_reg_layout, div_frac_start2_mode1), 0x55},
+	{offsetof(struct usb3_qserdes_pll_reg_layout, div_frac_start3_mode1), 0x03},
+	{offsetof(struct usb3_qserdes_pll_reg_layout, vco_tune_map), 0x14},
+	{offsetof(struct usb3_qserdes_pll_reg_layout, vco_tune1_mode0), 0xBA},
+	{offsetof(struct usb3_qserdes_pll_reg_layout, vco_tune2_mode0), 0x00},
+	{offsetof(struct usb3_qserdes_pll_reg_layout, vco_tune1_mode1), 0xBA},
+	{offsetof(struct usb3_qserdes_pll_reg_layout, vco_tune2_mode1), 0x00},
+	{offsetof(struct usb3_qserdes_pll_reg_layout, hsclk_sel_1), 0x13},
+	{offsetof(struct usb3_qserdes_pll_reg_layout, hsclk_hs_switch_sel_1), 0x00},
+	{offsetof(struct usb3_qserdes_pll_reg_layout, coreclk_div_mode0), 0x0A},
+	{offsetof(struct usb3_qserdes_pll_reg_layout, coreclk_div_mode1), 0x04},
+	{offsetof(struct usb3_qserdes_pll_reg_layout, core_clk_en), 0xA0},
+	{offsetof(struct usb3_qserdes_pll_reg_layout, cmn_config_1), 0x76},
+	{offsetof(struct usb3_qserdes_pll_reg_layout, pll_ivco), 0x0F},
+	{offsetof(struct usb3_qserdes_pll_reg_layout, pll_ivco_mode1), 0x0F},
+	{offsetof(struct usb3_qserdes_pll_reg_layout, integloop_gain0_mode0), 0x20},
+	{offsetof(struct usb3_qserdes_pll_reg_layout, integloop_gain0_mode1), 0x20},
+	{offsetof(struct usb3_qserdes_pll_reg_layout, vco_tune_initval2), 0x00},
+	{offsetof(struct usb3_qserdes_pll_reg_layout, vco_tune_maxval2), 0x01},
+	{offsetof(struct usb3_qserdes_pll_reg_layout, svs_mode_clk_sel), 0x0A},
+	{offsetof(struct usb3_qserdes_pll_reg_layout, bg_timer), 0x0A},
+};
+
+/* TX table - single set of registers (will be applied to both TXA and TXB via different base addresses) */
+static const qmp_phy_init_tbl_t qmp_v4_usb3_ss0_tx_tbl[] = {
+	{(u32)offsetof(struct usb3_phy_qserdes_tx_reg_layout, tx_lane_mode_1), 0x05},
+	{(u32)offsetof(struct usb3_phy_qserdes_tx_reg_layout, tx_lane_mode_2), 0x50},
+	{(u32)offsetof(struct usb3_phy_qserdes_tx_reg_layout, tx_lane_mode_3), 0x40},
+	{(u32)offsetof(struct usb3_phy_qserdes_tx_reg_layout, tx_res_code_lane_offset_tx), 0x1F},
+	{(u32)offsetof(struct usb3_phy_qserdes_tx_reg_layout, tx_res_code_lane_offset_rx), 0x0A},
+};
+
+/* RX table - single set of registers (will be applied to both RXA and RXB via different base addresses) */
+static const qmp_phy_init_tbl_t qmp_v4_usb3_ss0_rx_tbl[] = {
+	{(u32)offsetof(struct usb3_phy_qserdes_rx_reg_layout, rx_sigdet_cntrl), 0x04},
+	{(u32)offsetof(struct usb3_phy_qserdes_rx_reg_layout, rx_sigdet_deglitch_cntrl), 0x0E},
+	{(u32)offsetof(struct usb3_phy_qserdes_rx_reg_layout, rx_sigdet_enables), 0x00},
+	{(u32)offsetof(struct usb3_phy_qserdes_rx_reg_layout, rx_mode_rate_0_1_b0), 0xC3},
+	{(u32)offsetof(struct usb3_phy_qserdes_rx_reg_layout, rx_mode_rate_0_1_b1), 0xC3},
+	{(u32)offsetof(struct usb3_phy_qserdes_rx_reg_layout, rx_mode_rate_0_1_b2), 0xD8},
+	{(u32)offsetof(struct usb3_phy_qserdes_rx_reg_layout, rx_mode_rate_0_1_b3), 0x9E},
+	{(u32)offsetof(struct usb3_phy_qserdes_rx_reg_layout, rx_mode_rate_0_1_b4), 0x36},
+	{(u32)offsetof(struct usb3_phy_qserdes_rx_reg_layout, rx_mode_rate_0_1_b5), 0xB6},
+	{(u32)offsetof(struct usb3_phy_qserdes_rx_reg_layout, rx_mode_rate_0_1_b6), 0x64},
+	{(u32)offsetof(struct usb3_phy_qserdes_rx_reg_layout, rx_mode_rate2_b0), 0xD3},
+	{(u32)offsetof(struct usb3_phy_qserdes_rx_reg_layout, rx_mode_rate2_b1), 0xEE},
+	{(u32)offsetof(struct usb3_phy_qserdes_rx_reg_layout, rx_mode_rate2_b2), 0x58},
+	{(u32)offsetof(struct usb3_phy_qserdes_rx_reg_layout, rx_mode_rate2_b3), 0x9A},
+	{(u32)offsetof(struct usb3_phy_qserdes_rx_reg_layout, rx_mode_rate2_b4), 0x24},
+	{(u32)offsetof(struct usb3_phy_qserdes_rx_reg_layout, rx_mode_rate2_b5), 0x76},
+	{(u32)offsetof(struct usb3_phy_qserdes_rx_reg_layout, rx_mode_rate2_b6), 0xEF},
+	{(u32)offsetof(struct usb3_phy_qserdes_rx_reg_layout, rx_ivcm_cal_code_override), 0x00},
+	{(u32)offsetof(struct usb3_phy_qserdes_rx_reg_layout, rx_ivcm_cal_ctrl2), 0x80},
+	{(u32)offsetof(struct usb3_phy_qserdes_rx_reg_layout, rx_summer_cal_spd_mode), 0x2F},
+	{(u32)offsetof(struct usb3_phy_qserdes_rx_reg_layout, rx_dfe_ctle_post_cal_offset), 0x08},
+	{(u32)offsetof(struct usb3_phy_qserdes_rx_reg_layout, rx_ucdr_pi_controls), 0x15},
+	{(u32)offsetof(struct usb3_phy_qserdes_rx_reg_layout, rx_ucdr_pi_ctrl1), 0xD0},
+	{(u32)offsetof(struct usb3_phy_qserdes_rx_reg_layout, rx_ucdr_pi_ctrl2), 0x48},
+	{(u32)offsetof(struct usb3_phy_qserdes_rx_reg_layout, rx_ucdr_sb2_gain2_rate2), 0x0A},
+	{(u32)offsetof(struct usb3_phy_qserdes_rx_reg_layout, rx_ivcm_postcal_offset), 0x00},
+	{(u32)offsetof(struct usb3_phy_qserdes_rx_reg_layout, rx_vga_cal_cntrl1), 0x00},
+	{(u32)offsetof(struct usb3_phy_qserdes_rx_reg_layout, rx_vga_cal_man_val), 0x04},
+	{(u32)offsetof(struct usb3_phy_qserdes_rx_reg_layout, rx_dfe_dac_enable1), 0x88},
+	{(u32)offsetof(struct usb3_phy_qserdes_rx_reg_layout, rx_dfe_3), 0x45},
+	{(u32)offsetof(struct usb3_phy_qserdes_rx_reg_layout, rx_gm_cal), 0x0D},
+	{(u32)offsetof(struct usb3_phy_qserdes_rx_reg_layout, rx_ucdr_fo_gain_rate2), 0x09},
+	{(u32)offsetof(struct usb3_phy_qserdes_rx_reg_layout, rx_ucdr_so_gain_rate2), 0x05},
+	{(u32)offsetof(struct usb3_phy_qserdes_rx_reg_layout, rx_q_pi_intrinsic_bias_rate32), 0x2F},
+	{(u32)offsetof(struct usb3_phy_qserdes_rx_reg_layout, rx_bkup_ctrl1), 0x14},
+};
+
+/* PCS table */
+static const qmp_phy_init_tbl_t qmp_v4_usb3_ss0_pcs_tbl[] = {
+	{(u32)offsetof(struct usb3_phy_pcs_reg_layout, pcs_rcvr_dtct_dly_p1u2_l), 0xE7},
+	{(u32)offsetof(struct usb3_phy_pcs_reg_layout, pcs_rcvr_dtct_dly_p1u2_h), 0x03},
+	{(u32)offsetof(struct usb3_phy_pcs_reg_layout, pcs_lock_detect_config1), 0xC4},
+	{(u32)offsetof(struct usb3_phy_pcs_reg_layout, pcs_lock_detect_config2), 0x89},
+	{(u32)offsetof(struct usb3_phy_pcs_reg_layout, pcs_lock_detect_config3), 0x20},
+	{(u32)offsetof(struct usb3_phy_pcs_reg_layout, pcs_lock_detect_config6), 0x13},
+	{(u32)offsetof(struct usb3_phy_pcs_reg_layout, pcs_refgen_req_config1), 0x21},
+	{(u32)offsetof(struct usb3_phy_pcs_reg_layout, pcs_rx_sigdet_lvl), 0x55},
+	{(u32)offsetof(struct usb3_phy_pcs_reg_layout, pcs_rx_config), 0x0A},
+	{(u32)offsetof(struct usb3_phy_pcs_reg_layout, pcs_align_detect_config1), 0xD4},
+	{(u32)offsetof(struct usb3_phy_pcs_reg_layout, pcs_align_detect_config2), 0x30},
+	{(u32)offsetof(struct usb3_phy_pcs_reg_layout, pcs_pcs_tx_rx_config), 0x0C},
+	{(u32)offsetof(struct usb3_phy_pcs_reg_layout, pcs_eq_config1), 0x4B},
+	{(u32)offsetof(struct usb3_phy_pcs_reg_layout, pcs_eq_config5), 0x10},
+};
+
+/* PCS USB3 table */
+static const qmp_phy_init_tbl_t qmp_v4_usb3_ss0_pcs_usb3_tbl[] = {
+	{(u32)offsetof(struct usb3_phy_pcs_usb3_reg_layout, pcs_usb3_lfps_det_high_count_val), 0xF8},
+	{(u32)offsetof(struct usb3_phy_pcs_usb3_reg_layout, pcs_usb3_rxeqtraining_dfe_time_s2), 0x07},
+};
+
+const struct ss_usb_phy_reg qmp_phy_ss_instance[] = {
+	[0] = { /* SS0 PHY */
+		.com_base = (void *)QMP_PHY_SS0_COM_REG_BASE,
+		.qserdes_pll_base = (void *)QMP_PHY_SS0_QSERDES_PLL_REG_BASE,
+		.tx_base = (void *)QMP_PHY_SS0_TXA_REG_BASE,
+		.rx_base = (void *)QMP_PHY_SS0_RXA_REG_BASE,
+		.txb_base = (void *)QMP_PHY_SS0_TXB_REG_BASE,
+		.rxb_base = (void *)QMP_PHY_SS0_RXB_REG_BASE,
+		.pcs_base = (void *)QMP_PHY_SS0_PCS_REG_BASE,
+		.pcs_usb3_base = (void *)QMP_PHY_SS0_PCS_USB3_REG_BASE,
+		.name = "SS0",
+		.serdes_tbl = qmp_v4_usb3_ss0_serdes_tbl,
+		.serdes_tbl_num = ARRAY_SIZE(qmp_v4_usb3_ss0_serdes_tbl),
+		.tx_tbl = qmp_v4_usb3_ss0_tx_tbl,
+		.tx_tbl_num = ARRAY_SIZE(qmp_v4_usb3_ss0_tx_tbl),
+		.rx_tbl = qmp_v4_usb3_ss0_rx_tbl,
+		.rx_tbl_num = ARRAY_SIZE(qmp_v4_usb3_ss0_rx_tbl),
+		.pcs_tbl = qmp_v4_usb3_ss0_pcs_tbl,
+		.pcs_tbl_num = ARRAY_SIZE(qmp_v4_usb3_ss0_pcs_tbl),
+		.pcs_usb3_tbl = qmp_v4_usb3_ss0_pcs_usb3_tbl,
+		.pcs_usb3_tbl_num = ARRAY_SIZE(qmp_v4_usb3_ss0_pcs_usb3_tbl),
+	},
+	[1] = { /* SS1 PHY */
+		.com_base = (void *)QMP_PHY_SS1_COM_REG_BASE,
+		.qserdes_pll_base = (void *)QMP_PHY_SS1_QSERDES_PLL_REG_BASE,
+		.tx_base = (void *)QMP_PHY_SS1_TXA_REG_BASE,
+		.rx_base = (void *)QMP_PHY_SS1_RXA_REG_BASE,
+		.txb_base = (void *)QMP_PHY_SS1_TXB_REG_BASE,
+		.rxb_base = (void *)QMP_PHY_SS1_RXB_REG_BASE,
+		.pcs_base = (void *)QMP_PHY_SS1_PCS_REG_BASE,
+		.pcs_usb3_base = (void *)QMP_PHY_SS1_PCS_USB3_REG_BASE,
+		.name = "SS1",
+		.serdes_tbl = qmp_v4_usb3_ss0_serdes_tbl,
+		.serdes_tbl_num = ARRAY_SIZE(qmp_v4_usb3_ss0_serdes_tbl),
+		.tx_tbl = qmp_v4_usb3_ss0_tx_tbl,
+		.tx_tbl_num = ARRAY_SIZE(qmp_v4_usb3_ss0_tx_tbl),
+		.rx_tbl = qmp_v4_usb3_ss0_rx_tbl,
+		.rx_tbl_num = ARRAY_SIZE(qmp_v4_usb3_ss0_rx_tbl),
+		.pcs_tbl = qmp_v4_usb3_ss0_pcs_tbl,
+		.pcs_tbl_num = ARRAY_SIZE(qmp_v4_usb3_ss0_pcs_tbl),
+		.pcs_usb3_tbl = qmp_v4_usb3_ss0_pcs_usb3_tbl,
+		.pcs_usb3_tbl_num = ARRAY_SIZE(qmp_v4_usb3_ss0_pcs_usb3_tbl),
+	},
+};
+
+/* Helper function to write register table */
+static void qcom_qmp_phy_configure(void *base_addr, const qmp_phy_init_tbl_t tbl[], unsigned int num)
+{
+	int i;
+	const qmp_phy_init_tbl_t *t = tbl;
+
+	if (!t)
+		return;
+
+	for (i = 0; i < num; i++, t++)
+		write32((void *)((uintptr_t)base_addr + t->offset), t->val);
+}
+
+/* SS QMP PHY initialization function - supports both SS0 and SS1 */
+enum cb_err qmp_usb4_dp_phy_ss_init(int phy_instance)
+{
+	if (phy_instance < 0 || phy_instance >= ARRAY_SIZE(qmp_phy_ss_instance)) {
+		printk(BIOS_ERR, "Invalid PHY instance %d\n", phy_instance);
+		return CB_ERR;
+	}
+
+	const struct ss_usb_phy_reg *ss_phy_reg = &qmp_phy_ss_instance[phy_instance];
+	struct usb3_phy_pcs_reg_layout *current_pcs_reg = (struct usb3_phy_pcs_reg_layout *)ss_phy_reg->pcs_base;
+
+	printk(BIOS_DEBUG, "QMP-1x16 USB4 DP PHY %s init\n", ss_phy_reg->name);
+
+	/* Configure TYPEC_CTRL register for lane selection */
+	struct usb43dp_com_reg_layout *current_com_reg = (struct usb43dp_com_reg_layout *)ss_phy_reg->com_base;
+
+	/* Configure SW_PORTSELECT and SW_PORTSELECT_MUX using coreboot style */
+	clrsetbits32(&current_com_reg->typec_ctrl,
+				SW_PORTSELECT_MASK | SW_PORTSELECT_MUX_MASK,
+				(0 << SW_PORTSELECT_SHIFT) | SW_PORTSELECT_MUX_MASK);
+
+	/* Step 1: COM registers */
+	qcom_qmp_phy_configure(ss_phy_reg->com_base,
+						qmp_v4_usb3_ss0_com_tbl,
+						ARRAY_SIZE(qmp_v4_usb3_ss0_com_tbl));
+
+	/* Step 2: power up USB3 PHY */
+	write32(&current_pcs_reg->pcs_power_down_control, 0x01);
+
+	/* Step 3: PLL/Serdes registers */
+	qcom_qmp_phy_configure(ss_phy_reg->qserdes_pll_base,
+						ss_phy_reg->serdes_tbl,
+						ss_phy_reg->serdes_tbl_num);
+
+	/* Step 4: TXA registers */
+	qcom_qmp_phy_configure(ss_phy_reg->tx_base,
+						ss_phy_reg->tx_tbl,
+						ss_phy_reg->tx_tbl_num);
+
+	/* Step 5: RXA registers */
+	qcom_qmp_phy_configure(ss_phy_reg->rx_base,
+						ss_phy_reg->rx_tbl,
+						ss_phy_reg->rx_tbl_num);
+
+	/* Step 6: TXB registers */
+	qcom_qmp_phy_configure(ss_phy_reg->txb_base,
+						ss_phy_reg->tx_tbl,
+						ss_phy_reg->tx_tbl_num);
+
+	/* Step 7: RXB registers */
+	qcom_qmp_phy_configure(ss_phy_reg->rxb_base,
+						ss_phy_reg->rx_tbl,
+						ss_phy_reg->rx_tbl_num);
+
+	/* Step 8: PCS registers */
+	qcom_qmp_phy_configure(ss_phy_reg->pcs_base,
+						ss_phy_reg->pcs_tbl,
+						ss_phy_reg->pcs_tbl_num);
+
+	/* Step 9: PCS USB3 registers */
+	qcom_qmp_phy_configure(ss_phy_reg->pcs_usb3_base,
+						ss_phy_reg->pcs_usb3_tbl,
+						ss_phy_reg->pcs_usb3_tbl_num);
+
+	udelay(100);
+
+	/* perform software reset of USB43DP_COM */
+	write32(&current_com_reg->sw_reset, PCS_SW_RESET_DEASSERT);
+
+	write32(&current_pcs_reg->pcs_sw_reset, PCS_SW_RESET_DEASSERT);
+	write32(&current_pcs_reg->pcs_start_control, QPHY_PCS_START | QPHY_SERDES_START);
+
+	udelay(100);
+
+	long lock_us = wait_us(10000,
+			!(read32(&current_pcs_reg->pcs_pcs_status1) &
+			USB3_PCS_PHYSTATUS));
+
+	uint32_t phy_status = read32(&current_pcs_reg->pcs_pcs_status1);
+
+	if (!lock_us) {
+		printk(BIOS_ERR, "QMP PHY %s PLL LOCK failed after 10ms, phy_status: 0x%x\n",
+				ss_phy_reg->name, phy_status);
+		return CB_ERR;
+	}
+
+	printk(BIOS_DEBUG, "QMP PHY %s initialized and locked in %ldus, phy_status: 0x%x\n",
+			ss_phy_reg->name, lock_us, phy_status);
+
+	return CB_SUCCESS;
+}
diff --git a/src/soc/qualcomm/x1p42100/usb/snps_usb_phy.c b/src/soc/qualcomm/x1p42100/usb/snps_usb_phy.c
index 2fc35ad077..a33cf71d2e 100644
--- a/src/soc/qualcomm/x1p42100/usb/snps_usb_phy.c
+++ b/src/soc/qualcomm/x1p42100/usb/snps_usb_phy.c
@@ -95,10 +95,26 @@
 struct hs_usb_phy_reg *hs_phy_reg = NULL;
 void hs_usb_phy_init(int index)
 {
-	if (index == 0)
+	switch (index) {
+	case 0:
 		hs_phy_reg = (void *)HS_USB_MP0_PHY_BASE;
-	else
+		break;
+	case 1:
 		hs_phy_reg = (void *)HS_USB_MP1_PHY_BASE;
+		break;
+	case 2:
+		hs_phy_reg = (void *)HS_USB_SS0_PHY_BASE;
+		break;
+	case 3:
+		hs_phy_reg = (void *)HS_USB_SS1_PHY_BASE;
+		break;
+	case 4:
+		hs_phy_reg = (void *)HS_USB_SS2_PHY_BASE;
+		break;
+	default:
+		printk(BIOS_ERR, "Invalid USB PHY index: %d\n", index);
+		return;
+	}
 
 	/*
 	 * This sequence initializes the USB HS PHY.

From 8ffa58723a2893c8dbabde0fe17ee1a3192431cd Mon Sep 17 00:00:00 2001
From: Hari L <haril@qualcomm.corp-partner.google.com>
Date: Tue, 7 Oct 2025 19:20:26 +0530
Subject: [PATCH 2210/3886] soc/qualcomm/x1p42100: Add USB Type-C support

Add USB DWC3 controller, VBUS support and Integrate Clock and PHY
for Type C ports C0, C1.
The register details are part of HRD-X1P42100-S1 document.
https://docs.qualcomm.com/bundle/resource/topics/HRD-X1P42100-S1/

BUG=b:448107633
TEST=Create an image.serial.bin, ensure it boots on X1P42100
and check USB port link status.

firmware-shell: md 0x0a800420 8
0a800420: 000002a0 00000000 00000000 00000000    ................
0a800430: 00001203 00000000 00000000 00000000    ................

firmware-shell: md 0x0a600420 8
0a600420: 00000e03 00000000 00000000 00000000    ................
0a600430: 00001203 00000000 00000000 00000000    ..........

Console logs:
[INFO ]  Setting up USB HOST controller.
[DEBUG]  USB HS PHY initialized for index 0
[DEBUG]  USB HS PHY initialized for index 1
[DEBUG]  QMP PHY MP0 init
[DEBUG]  QMP PHY MP0 initialized and locked in 1674us
[DEBUG]  QMP PHY MP1 init
[DEBUG]  QMP PHY MP1 initialized and locked in 1674us
[DEBUG]  USB HS PHY initialized for index 2
[DEBUG]  QMP-1x16 USB4 DP PHY SS0 init
[DEBUG]  QMP PHY SS0 initialized and locked in 1671us
[INFO ]  Enabling SMB1 VBUS SuperSpeed
[DEBUG]  SMB1 OTG Status: 0x00, State: 0x00
[ERROR]  SMB1 OTG enable timeout after 100 ms, final state: 0x00
[ERROR]  SMB1 OTG enable failed
[INFO ]  SMB1 Type-C Status:
[INFO ]    Misc Status (0x2B0B): 0x3b
[INFO ]    Src Status (0x2B08): 0x00
[INFO ]    Mode Config (0x2B44): 0x00
[DEBUG]  USB HS PHY initialized for index 3
[DEBUG]  QMP-1x16 USB4 DP PHY SS1 init
[DEBUG]  QMP PHY SS1 initialized and locked in 1672us
[INFO ]  Enabling SMB2 VBUS SuperSpeed
[DEBUG]  SMB2 OTG Status: 0x03, State: 0x03
[DEBUG]  SMB2 OTG Status: 0x02, State: 0x02
[INFO ]  SMB2 OTG block enabled successfully
[INFO ]  SMB2 Type-C Status:
[INFO ]    Misc Status (0x2B0B): 0x49, VBUS Status (bit 5): 0
[INFO ]    Src Status (0x2B08): 0x08
[INFO ]    Mode Config (0x2B44): 0x00
[SPEW ]  Configure USB in Host mode
[SPEW ]  Configure USB Primary in Host mode
[SPEW ]  Configure USB Secondary in Host mode
[INFO ]  DWC3 and PHY setup finished

Change-Id: I9f5e9ef910844358308a16b31de6da58d5da7f3a
Signed-off-by: Hari L <haril@qualcomm.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89447
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
---
 .../qualcomm/common/include/soc/qcom_spmi.h   |   3 +
 .../x1p42100/include/soc/addressmap.h         |  50 ++-
 .../qualcomm/x1p42100/include/soc/usb/usb.h   |  72 +++-
 src/soc/qualcomm/x1p42100/usb/usb.c           | 402 +++++++++++++++++-
 4 files changed, 489 insertions(+), 38 deletions(-)

diff --git a/src/soc/qualcomm/common/include/soc/qcom_spmi.h b/src/soc/qualcomm/common/include/soc/qcom_spmi.h
index 1c0ae6121f..533486cb84 100644
--- a/src/soc/qualcomm/common/include/soc/qcom_spmi.h
+++ b/src/soc/qualcomm/common/include/soc/qcom_spmi.h
@@ -6,6 +6,9 @@
 #include <stddef.h>
 #include <stdint.h>
 
+/* Macro to construct SPMI address from slave ID and register offset */
+#define SPMI_ADDR(slave, reg) ((slave << 16) | reg)
+
 int spmi_read8(uint32_t addr);
 int spmi_write8(uint32_t addr, uint8_t data);
 
diff --git a/src/soc/qualcomm/x1p42100/include/soc/addressmap.h b/src/soc/qualcomm/x1p42100/include/soc/addressmap.h
index 8643f49b9b..90c85bff59 100644
--- a/src/soc/qualcomm/x1p42100/include/soc/addressmap.h
+++ b/src/soc/qualcomm/x1p42100/include/soc/addressmap.h
@@ -18,8 +18,8 @@
 
 /* CPUCP */
 #define APSS_HM_BASE						0x17000000
-#define APSS_CPUCP_LPM_BFSM_REG_BASE				(APSS_HM_BASE + 0x019d0000)
-#define HWIO_APSS_CPUCP_CPUCP_LPM_SEQ_WAIT_EVT_CTRL_MASK_ADDR	(APSS_CPUCP_LPM_BFSM_REG_BASE + 0x161c)
+#define APSS_CPUCP_LPM_BFSM_REG_BASE				(APSS_HM_BASE + 0x019D0000)
+#define HWIO_APSS_CPUCP_CPUCP_LPM_SEQ_WAIT_EVT_CTRL_MASK_ADDR	(APSS_CPUCP_LPM_BFSM_REG_BASE + 0x161C)
 #define HWIO_APSS_CPUCP_CPUCP_SW_WAKEUP_REQ_ADDR		(APSS_CPUCP_LPM_BFSM_REG_BASE + 0x1688)
 
 /* X1P42100 QSPI GPIO PINS */
@@ -74,40 +74,42 @@
 #define HS_USB_SS1_PHY_BASE		0x00FD9000
 #define HS_USB_SS2_PHY_BASE		0x00FDE000
 
-#define HS_USB_MP0_PHY_BASE		0x088e1000
+#define HS_USB_MP0_PHY_BASE		0x088E1000
 #define HS_USB_MP1_PHY_BASE		0x088E2000
 #define QMP_PHY_MP0_QSERDES_COM_REG_BASE	0x088E3000
 #define QMP_PHY_MP0_QSERDES_TX_REG_BASE		0x088E3E00
 #define QMP_PHY_MP0_QSERDES_RX_REG_BASE		0x088E4000
-#define QMP_PHY_MP0_PCS_REG_BASE			0x088E3200
+#define QMP_PHY_MP0_PCS_REG_BASE		0x088E3200
 #define QMP_PHY_MP0_PCS_USB3_REG_BASE		0x088E4200
-#define USB_HOST_DWC3_BASE					0x0a40c100
+#define USB_HOST_DWC3_MP_BASE			0x0A40C100
 
 #define QMP_PHY_MP1_QSERDES_COM_REG_BASE	0x088E5000
 #define QMP_PHY_MP1_QSERDES_TX_REG_BASE		0x088E5E00
 #define QMP_PHY_MP1_QSERDES_RX_REG_BASE		0x088E6000
-#define QMP_PHY_MP1_PCS_REG_BASE			0x088E5200
+#define QMP_PHY_MP1_PCS_REG_BASE		0x088E5200
 #define QMP_PHY_MP1_PCS_USB3_REG_BASE		0x088E6200
 
 /* USB SS0 PHY BASE ADDRESSES - AHB2PHY_1_QUSB4PHY_SS_0 */
-#define QMP_PHY_SS0_COM_REG_BASE		0xFD5000  // USB43DP_COM
-#define QMP_PHY_SS0_TXA_REG_BASE		0xFD5400  // USB43DP_QSERDES_TXA
-#define QMP_PHY_SS0_TXB_REG_BASE		0xFD5A00  // USB43DP_QSERDES_TXB
-#define QMP_PHY_SS0_RXA_REG_BASE		0xFD5600  // USB43DP_QSERDES_RXA
-#define QMP_PHY_SS0_RXB_REG_BASE		0xFD5C00  // USB43DP_QSERDES_RXB
-#define QMP_PHY_SS0_QSERDES_PLL_REG_BASE	0x00FD6000  // USB3_QSERDES_PLL
-#define QMP_PHY_SS0_PCS_REG_BASE		0xFD6400  // USB3_PCS
-#define QMP_PHY_SS0_PCS_USB3_REG_BASE		0xFD6700  // USB3_PCS_USB3
+#define QMP_PHY_SS0_COM_REG_BASE		0x00FD5000	/* USB43DP_COM */
+#define QMP_PHY_SS0_TXA_REG_BASE		0x00FD5400	/* USB43DP_QSERDES_TXA */
+#define QMP_PHY_SS0_TXB_REG_BASE		0x00FD5A00	/* USB43DP_QSERDES_TXB */
+#define QMP_PHY_SS0_RXA_REG_BASE		0x00FD5600	/* USB43DP_QSERDES_RXA */
+#define QMP_PHY_SS0_RXB_REG_BASE		0x00FD5C00	/* USB43DP_QSERDES_RXB */
+#define QMP_PHY_SS0_QSERDES_PLL_REG_BASE	0x00FD6000	/* USB3_QSERDES_PLL */
+#define QMP_PHY_SS0_PCS_REG_BASE		0x00FD6400	/* USB3_PCS */
+#define QMP_PHY_SS0_PCS_USB3_REG_BASE		0x00FD6700	/* USB3_PCS_USB3 */
+#define USB_HOST_DWC3_PRIM_BASE			0x0A60C100
 
 /* USB SS1 PHY BASE ADDRESSES - AHB2PHY_1_QUSB4PHY_SS_1 */
-#define QMP_PHY_SS1_COM_REG_BASE		0xFDA000  // USB43DP_COM
-#define QMP_PHY_SS1_TXA_REG_BASE		0xFDA400  // USB43DP_QSERDES_TXA
-#define QMP_PHY_SS1_TXB_REG_BASE		0xFDAA00  // USB43DP_QSERDES_TXB
-#define QMP_PHY_SS1_RXA_REG_BASE		0xFDA600  // USB43DP_QSERDES_RXA
-#define QMP_PHY_SS1_RXB_REG_BASE		0xFDAC00  // USB43DP_QSERDES_RXB
-#define QMP_PHY_SS1_QSERDES_PLL_REG_BASE	0xFDB000  // USB3_QSERDES_PLL
-#define QMP_PHY_SS1_PCS_REG_BASE		0xFDB400  // USB3_PCS
-#define QMP_PHY_SS1_PCS_USB3_REG_BASE		0xFDB700  // USB3_PCS_USB3
+#define QMP_PHY_SS1_COM_REG_BASE		0x00FDA000	/* USB43DP_COM */
+#define QMP_PHY_SS1_TXA_REG_BASE		0x00FDA400	/* USB43DP_QSERDES_TXA */
+#define QMP_PHY_SS1_TXB_REG_BASE		0x00FDAA00	/* USB43DP_QSERDES_TXB */
+#define QMP_PHY_SS1_RXA_REG_BASE		0x00FDA600	/* USB43DP_QSERDES_RXA */
+#define QMP_PHY_SS1_RXB_REG_BASE		0x00FDAC00	/* USB43DP_QSERDES_RXB */
+#define QMP_PHY_SS1_QSERDES_PLL_REG_BASE	0xFDB000	/* USB3_QSERDES_PLL */
+#define QMP_PHY_SS1_PCS_REG_BASE		0xFDB400	/* USB3_PCS */
+#define QMP_PHY_SS1_PCS_USB3_REG_BASE		0xFDB700	/* USB3_PCS_USB3 */
+#define USB_HOST_DWC3_SEC_BASE				0x0A80C100
 
 /* PCIE 6A */
 #define PCIE6A_PCIE_PARF		0x01BF8000
@@ -166,8 +168,10 @@
 #define TCSR_GCC_USB3_MP0_CLKREF_EN_ADDR	((void *)0x1FD510C)
 #define TCSR_GCC_USB3_MP1_CLKREF_EN_ADDR	((void *)0x1FD5110)
 #define TCSR_GCC_USB4_1_CLKREF_EN_ADDR		((void *)0x1FD5120)
+#define TCSR_GCC_USB2_1_CLKREF_EN_ADDR		((void *)0x1FD5114)
 #define TCSR_GCC_USB4_2_CLKREF_EN_ADDR		((void *)0x1FD5124)
-#define USB3_CLKREF_ENABLE_VALUE			0x1
+#define TCSR_GCC_USB2_2_CLKREF_EN_ADDR		((void *)0x1FD5118)
+#define USB_CLKREF_ENABLE_VALUE			0x1
 
 /* SPMI PMIC ARB */
 #define SPMI_PMIC_ARB_CORE_BASE		0x0C400000
diff --git a/src/soc/qualcomm/x1p42100/include/soc/usb/usb.h b/src/soc/qualcomm/x1p42100/include/soc/usb/usb.h
index 4b62392d2f..360e319939 100644
--- a/src/soc/qualcomm/x1p42100/include/soc/usb/usb.h
+++ b/src/soc/qualcomm/x1p42100/include/soc/usb/usb.h
@@ -29,12 +29,29 @@
 #define DWC3_GCTL_DISSCRAMBLE			(1 << 3)
 #define DWC3_GCTL_U2EXIT_LFPS			(1 << 2)
 #define DWC3_GCTL_DSBLCLKGTNG			(1 << 0)
+
+/* Global RX Threshold Configuration Register */
+#define DWC3_GRXTHRCFG_USBMAXRXBURSTSIZE_SHFT	19
+#define DWC3_GRXTHRCFG_USBRXPKTCNT_SHFT		24
+#define DWC3_GRXTHRCFG_USBRXPKTCNTSEL		BIT(29)
+#define DWC3_GRXTHRCFG_USBMAXRXBURSTSIZE(n)	((n) << DWC3_GRXTHRCFG_USBMAXRXBURSTSIZE_SHFT)
+#define DWC3_GRXTHRCFG_USBRXPKTCNT(n)		((n) << DWC3_GRXTHRCFG_USBRXPKTCNT_SHFT)
+
+/* Global SBus Configuration 1 Register */
+#define DWC3_GSBUSCFG1_PIPETRANSLIMIT_SHFT	8
+#define DWC3_GSBUSCFG1_EN1KPAGE			BIT(12)
+#define DWC3_GSBUSCFG1_PIPETRANSLIMIT(n)	((n) << DWC3_GSBUSCFG1_PIPETRANSLIMIT_SHFT)
+
+/* Global User Control Register */
+#define DWC3_GUCTL_SPRSCTRLTRANSEN		BIT(17)
+
 #define UTMI_CLK_DIS_0					(1 << 8)
 #define UTMI_CLK_SEL_0					(1 << 0)
 #define PIPE3_PHYSTATUS_SW_0			(1 << 3)
 #define PIPE3_SET_PHYSTATUS_SW_0		(1 << 9)
 #define USB3_MP_CGCTL_REG_ADDR			((void *)0x0A4F8828)
-#define USB3_MP_DBM_FSM_EN_BIT			(1 << 1)
+
+#define USB3_CGCTL_DBM_FSM_EN_BIT		(1 << 1)
 #define USB3_MP_LINK_REGS_1_LU3LFPSRXTIM_ADDR	((void *)0X0A40D090)
 #define USB3_MP_LINK_REGS_0_LU3LFPSRXTIM_ADDR	((void *)0X0A40D010)
 
@@ -56,7 +73,7 @@
 								DWC3_GUCTL1_IP_GAP_ADD_ON(0x3) | \
 								DWC3_GUCTL1_DEV_DECOUPLE_L1L2_EVT)
 
-#define USB_HOST_DWC3_GENERAL_CFG_ADDR		0X0A4F8808
+#define USB_HOST_DWC3_MP_GENERAL_CFG_ADDR		0X0A4F8808
 #define USB3_MP_GUSB2PHYCFG_REGS_1_ADDR		((void *)0x0A40C204)
 #define GUSB2PHYCFG_ENBLSLPM_BIT		BIT(8)
 #define USB3_MP_GUSB2PHYCFG_REGS_0_ADDR		((void *)0x0A40C200)
@@ -66,6 +83,51 @@
 #define USB3_MP_PORTSC_30_REGS_1_ADDR	((void *)0x0A400450)
 #define USB3_PORTSC_WCE_BIT				BIT(25)
 
+/* USB4 SS USB3 DRD SP 0 (Primary) Register Addresses */
+#define USB4_SS_USB3_DRD_SP_0_USB31_PRIMCGCTL_REG	((void *)0x0A6F8828)
+#define USB4_SS_USB3_DRD_SP_0_USB31_PRIMLINK_REGS_0_LU3LFPSRXTIM_ADDR	((void *)0x0A61D010)
+#define USB4_SS_USB3_DRD_SP_0_USB31_PRIMGUSB2PHYCFG_REGS_0_GUSB2PHYCFG_ADDR	((void *)0x0A60C200)
+#define USB4_SS_USB3_DRD_SP_0_USB31_PRIMPORTSC_20_REGS_0_PORTSC_20_ADDR	((void *)0x0A600420)
+#define USB4_SS_USB3_DRD_SP_0_USB31_PRIMPORTSC_30_REGS_0_PORTSC_30_ADDR	((void *)0x0A600430)
+#define USB4_SS_USB3_DRD_SP_0_USB31_PRIMGENERAL_CFG 0xA6F8808
+/* USB4 SS USB3 DRD SP 1 (Secondary) Register Addresses */
+#define USB4_SS_USB3_DRD_SP_1_USB31_SECCGCTL_REG	((void *)0x0A8F8828)
+#define USB4_SS_USB3_DRD_SP_1_USB31_SECLINK_REGS_0_LU3LFPSRXTIM_ADDR	((void *)0x0A81D010)
+#define USB4_SS_USB3_DRD_SP_1_USB31_SECGUSB2PHYCFG_REGS_0_GUSB2PHYCFG_ADDR	((void *)0x0A80C200)
+#define USB4_SS_USB3_DRD_SP_1_USB31_SECPORTSC_20_REGS_0_PORTSC_20_ADDR	((void *)0x0A800420)
+#define USB4_SS_USB3_DRD_SP_1_USB31_SECPORTSC_30_REGS_0_PORTSC_30_ADDR	((void *)0x0A800430)
+#define USB4_SS_USB3_DRD_SP_1_USB31_SECGENERAL_CFG 0xA8F8808
+
+/* VBUS SS Enable definitions - using same slave IDs as battery charging */
+#define SMB1_SLAVE_ID 0x07
+#define SMB2_SLAVE_ID 0x0A
+
+/* SCHG DCDC register offsets */
+#define SCHG_DCDC_CMD_OTG 0x2740
+#define SCHG_DCDC_OTG_CFG 0x2753
+#define SCHG_DCDC_OTG_STATUS 0x270D
+
+/* OTG Status register bit definitions */
+#define OTG_STATE_MASK 0x07
+#define OTG_STATE_DISABLED 0x00
+#define OTG_STATE_ENABLING 0x01
+#define OTG_STATE_ENABLED 0x02
+#define OTG_STATE_DISABLING 0x03
+#define OTG_STATE_ERROR 0x04
+
+/* OTG Status check timeout and polling interval */
+#define OTG_STATUS_TIMEOUT_MS 100
+#define OTG_STATUS_POLL_INTERVAL_MS 2
+
+/* Type-C register offsets */
+#define SCHG_TYPE_C_TYPE_C_MISC_STATUS 0x2B0B
+#define SCHG_TYPE_C_TYPE_C_SRC_STATUS 0x2B08
+#define SCHG_TYPE_C_TYPE_C_MODE_CFG 0x2B44
+#define TYPEC_VBUS_STATUS_MASK BIT(5)
+
+/* Forward declaration */
+struct dwc3_controller_config;
+
 /* Initializes a specific HS PHY instance */
 void hs_usb_phy_init(int index);
 /* Initializes and configures the USB HOST0 controller */
@@ -74,3 +136,9 @@ void setup_usb_host0(void);
 int qcom_enable_usb_clk(void);
 /* Enable TCSR REFGEN */
 void enable_clock_tcsr(void);
+/* Enable TCSR CLKREF */
+void usb_update_refclk_for_core(u32 core_num, bool enable);
+/* Enables VBUS SuperSpeed for specified USB core */
+void enable_vbus_ss(const struct dwc3_controller_config *config);
+/* Reads comprehensive Type-C status from PMIC */
+void usb_typec_status_check(const struct dwc3_controller_config *config);
diff --git a/src/soc/qualcomm/x1p42100/usb/usb.c b/src/soc/qualcomm/x1p42100/usb/usb.c
index c969693c4f..5916bcef81 100644
--- a/src/soc/qualcomm/x1p42100/usb/usb.c
+++ b/src/soc/qualcomm/x1p42100/usb/usb.c
@@ -5,6 +5,7 @@
 #include <soc/usb/usb.h>
 #include <soc/addressmap.h>
 #include <soc/clock.h>
+#include <soc/qcom_spmi.h>
 #include <delay.h>
 #include <gpio.h>
 
@@ -49,20 +50,29 @@ check_member(usb_dwc3, usb3pipectl_mp1, 0x1c4);
 
 struct usb_dwc3_cfg {
 	struct usb_dwc3 *usb_host_dwc3;
+	struct usb_dwc3 *usb_host_dwc3_prim;
+	struct usb_dwc3 *usb_host_dwc3_sec;
 	u32 *usb3_bcr;
 	u32 *qusb2phy_bcr;
 	u32 *qusb2phy1_bcr;
+	u32 *gcc_qusb2phy_prim_bcr;
+	u32 *gcc_qusb2phy_sec_bcr;
 	u32 *gcc_usb3phy_bcr_reg;
 	u32 *gcc_qmpphy_bcr_reg;
 	u32 *gcc_usb3phy1_bcr_reg;
 	u32 *gcc_qmpphy1_bcr_reg;
-	u32 *qusb2secphy_bcr;
-	u32 *gcc_usb3secphy_bcr_reg;
-	u32 *gcc_qmpsecphy_bcr_reg;
+	u32 *gcc_usb4_0_dp0_phy_prim_bcr;
+	u32 *gcc_usb4_1_dp0_phy_sec_bcr;
+	u32 *gcc_usb3_phy_prim_bcr;
+	u32 *gcc_usb3_phy_sec_bcr;
+	u32 *gcc_usb3phy_phy_prim_bcr;
+	u32 *gcc_usb3phy_phy_sec_bcr;
 };
 
-static struct usb_dwc3_cfg usb_port0 = {
-	.usb_host_dwc3 =	(void *)USB_HOST_DWC3_BASE,
+static struct usb_dwc3_cfg usb_ports = {
+	.usb_host_dwc3 =	(void *)USB_HOST_DWC3_MP_BASE,
+	.usb_host_dwc3_prim =	(void *)USB_HOST_DWC3_PRIM_BASE,
+	.usb_host_dwc3_sec =	(void *)USB_HOST_DWC3_SEC_BASE,
 	.usb3_bcr =		&gcc->gcc_usb30_mp_bcr,
 	.qusb2phy_bcr =		&gcc->qusb2phy_hs0_mp_bcr,
 	.gcc_usb3phy_bcr_reg =	&gcc->usb3uniphy_phy_mp0_bcr,
@@ -70,10 +80,18 @@ static struct usb_dwc3_cfg usb_port0 = {
 	.qusb2phy1_bcr =		&gcc->qusb2phy_hs1_mp_bcr,
 	.gcc_usb3phy1_bcr_reg =	&gcc->usb3uniphy_phy_mp1_bcr,
 	.gcc_qmpphy1_bcr_reg =	&gcc->usb3_uniphy_mp1_bcr,
+	.gcc_qusb2phy_prim_bcr =	&gcc->gcc_qusb2phy_prim_bcr,
+	.gcc_qusb2phy_sec_bcr =		&gcc->gcc_qusb2phy_sec_bcr,
+	.gcc_usb4_0_dp0_phy_prim_bcr =	&gcc->gcc_usb4_0_dp0_phy_prim_bcr,
+	.gcc_usb4_1_dp0_phy_sec_bcr =	&gcc->gcc_usb4_1_dp0_phy_sec_bcr,
+	.gcc_usb3_phy_prim_bcr =	&gcc->gcc_usb3_phy_prim_bcr,
+	.gcc_usb3_phy_sec_bcr =		&gcc->gcc_usb3_phy_sec_bcr,
+	.gcc_usb3phy_phy_prim_bcr =	&gcc->gcc_usb3phy_phy_prim_bcr,
+	.gcc_usb3phy_phy_sec_bcr =	&gcc->gcc_usb3phy_phy_sec_bcr,
 };
 
-bool hs_speed_only = false;
-u32 *usb3_general_cfg_addr = (void *)USB_HOST_DWC3_GENERAL_CFG_ADDR;
+static bool hs_speed_only;
+static u32 *usb3_general_cfg_addr = (void *)USB_HOST_DWC3_MP_GENERAL_CFG_ADDR;
 
 /* Enables Repeaters /Refgen blocks for USB */
 void enable_clock_tcsr(void)
@@ -107,7 +125,7 @@ int32_t qcom_enable_usb_clk(void)
 	}
 
 	clock_configure_usb();
-	/* Set USB3 PHY PIPE 0 clock source to X0  */
+
 	if (usb_clock_configure_mux(USB3_PHY_PIPE_0, USB_PHY_XO_SRC_SEL)) {
 		printk(BIOS_ERR, "%s(): USB3 PHY PIPE 0 clock enable failed\n", __func__);
 		return -1;
@@ -125,8 +143,7 @@ int32_t qcom_enable_usb_clk(void)
 		}
 	}
 
-	write32(TCSR_GCC_USB3_MP0_CLKREF_EN_ADDR, USB3_CLKREF_ENABLE_VALUE);
-	write32(TCSR_GCC_USB3_MP1_CLKREF_EN_ADDR, USB3_CLKREF_ENABLE_VALUE);
+	usb_update_refclk_for_core(3, true);
 	/* Set USB3 PHY PIPE 1 clock source to USB PHY */
 
 	if (usb_clock_configure_mux(USB3_PHY_PIPE_0, USB_PHY_PIPE_SRC_SEL)) {
@@ -139,6 +156,48 @@ int32_t qcom_enable_usb_clk(void)
 		return -1;
 	}
 
+	if (usb_clock_configure_mux(USB3_PRIM_PHY_PIPE, USB_PHY_XO_SRC_SEL)) {
+		printk(BIOS_ERR, "%s(): USB3 PRIM PHY PIPE clock XO config failed\n", __func__);
+		return -1;
+	}
+
+	/* Enable USB0 PRIM clocks */
+	for (clk = USB_PRIM_SYS_NOC_USB_AXI_CBCR; clk < USB_PRIM_CLK_COUNT; clk++) {
+		ret = usb_prim_clock_enable(clk);
+		if (ret) {
+			printk(BIOS_ERR, "Failed to enable USB0 clock %d\n", clk);
+			return ret;
+		}
+	}
+
+	if (usb_clock_configure_mux(USB3_PRIM_PHY_PIPE, USB_PHY_PIPE_SRC_SEL)) {
+		printk(BIOS_ERR, "%s(): USB3 PRIM PHY PIPE clock PHY config failed\n", __func__);
+		return -1;
+	}
+
+	usb_update_refclk_for_core(0, true);
+
+	if (usb_clock_configure_mux(USB3_SEC_PHY_PIPE, USB_PHY_XO_SRC_SEL)) {
+		printk(BIOS_ERR, "%s(): USB3 SEC PHY PIPE clock XO config failed\n", __func__);
+		return -1;
+	}
+
+	/* Enable USB SEC clocks */
+	for (clk = USB_SEC_CFG_NOC_USB3_SEC_AXI_CBCR; clk < USB_SEC_CLK_COUNT; clk++) {
+		ret = usb_sec_clock_enable(clk);
+		if (ret) {
+			printk(BIOS_ERR, "Failed to enable USB SEC clock %d\n", clk);
+			return ret;
+		}
+	}
+
+	if (usb_clock_configure_mux(USB3_SEC_PHY_PIPE, USB_PHY_PIPE_SRC_SEL)) {
+		printk(BIOS_ERR, "%s(): USB3 SEC PHY PIPE clock PHY config failed\n", __func__);
+		return -1;
+	}
+
+	usb_update_refclk_for_core(1, true);
+
 	return ret;
 }
 
@@ -201,7 +260,7 @@ static void setup_dwc3(struct usb_dwc3 *dwc3)
 	To save power, enable the hardware-based clock gating (not relevant for PBL):
 	a. usb30_reg_cgctl[DBM_FSM_EN] = 0x1
 	*/
-	setbits32(USB3_MP_CGCTL_REG_ADDR, USB3_MP_DBM_FSM_EN_BIT);
+	setbits32(USB3_MP_CGCTL_REG_ADDR, USB3_CGCTL_DBM_FSM_EN_BIT);
 	//Disable clock gating: DWC_USB3_GCTL.DSBLCLKGTNG = 1
 	clrsetbits32(&dwc3->ctl, (DWC3_GCTL_SCALEDOWN_MASK |
 			DWC3_GCTL_DISSCRAMBLE),
@@ -246,9 +305,151 @@ static void setup_dwc3(struct usb_dwc3 *dwc3)
 
 }
 
+/*
+ * setup_dwc3 - Configures the DWC3 USB controller.
+ * @dwc3: Pointer to the USB DWC3 configuration structure.
+ * Handles high-speed operation, power management, and sets to host mode.
+ */
+
+/* DWC3 Controller Configuration Structure */
+struct dwc3_controller_config {
+	const char *name;
+	u32 *general_cfg_addr;
+	u32 *cgctl_reg_addr;
+	u32 *link_regs_lu3lfpsrxtim_addr;
+	u32 *gusb2phycfg_regs_addr;
+	u32 *portsc_20_regs_addr;
+	u32 *portsc_30_regs_addr;
+	u8 smb_slave_addr;
+};
+
+/*
+ * setup_dwc3_controller - Configure DWC3 USB controller
+ * @dwc3: Pointer to the USB DWC3 structure
+ * @config: Controller-specific configuration
+ * @hs_only: true for high-speed only mode, false for super-speed mode
+ *
+ * Handles both high-speed and super-speed operation, power management,
+ * and sets controller to host mode.
+ */
+static void setup_dwc3_controller(struct usb_dwc3 *dwc3,
+				  const struct dwc3_controller_config *config,
+				  bool hs_only)
+{
+	u32 *reg = config->general_cfg_addr;
+
+	/* Configure speed mode */
+	if (hs_only) {
+		/* High-speed only mode configuration */
+		setbits32(reg, UTMI_CLK_DIS_0);
+		udelay(10);
+		setbits32(reg, UTMI_CLK_SEL_0);
+		setbits32(reg, PIPE3_PHYSTATUS_SW_0);
+		clrbits32(reg, PIPE3_SET_PHYSTATUS_SW_0);
+		udelay(10);
+		clrbits32(reg, UTMI_CLK_DIS_0);
+	} else {
+		/* Super-speed mode: core exits U1/U2/U3 only in PHY power state P1/P2/P3 */
+		clrsetbits32(&dwc3->usb3pipectl,
+			DWC3_GUSB3PIPECTL_DELAYP1TRANS,
+			DWC3_GUSB3PIPECTL_UX_EXIT_IN_PX);
+	}
+
+	/* Configure USB2 PHY interface: Select UTMI+ PHY with 8-bit interface */
+	clrsetbits32(&dwc3->usb2phycfg,
+		(DWC3_GUSB2PHYCFG_USB2TRDTIM_MASK |
+		 DWC3_GUSB2PHYCFG_PHYIF_MASK |
+		 DWC3_GUSB2PHYCFG_ENBLSLPM_MASK),
+		(DWC3_GUSB2PHYCFG_PHYIF(UTMI_PHYIF_8_BIT) |
+		 DWC3_GUSB2PHYCFG_USBTRDTIM(USBTRDTIM_UTMI_8_BIT)));
+
+	/* Enable hardware-based clock gating */
+	setbits32(config->cgctl_reg_addr, USB3_CGCTL_DBM_FSM_EN_BIT);
+
+	/* Disable clock gating: DWC_USB3_GCTL.DSBLCLKGTNG = 1 */
+	clrsetbits32(&dwc3->ctl,
+		(DWC3_GCTL_SCALEDOWN_MASK | DWC3_GCTL_DISSCRAMBLE),
+		DWC3_GCTL_U2EXIT_LFPS | DWC3_GCTL_DSBLCLKGTNG);
+
+	/* Allow PHY to transition to P2 from suspend (P3) state */
+	setbits32(&dwc3->usb3pipectl,
+		(DWC3_GUSB3PIPECTL_P3EXSIGP2 |
+		 DWC3_GUSB3PIPECTL_UX_EXIT_IN_PX));
+
+	/* Reduce U3 exit handshake timer to 300ns */
+	clrsetbits32(config->link_regs_lu3lfpsrxtim_addr,
+		LFPS_RSP_RX_CLK_CLR_MASK, LFPS_RSP_RX_CLK_SET_MASK);
+
+	/* Configure L1 exit and IP gap settings */
+	clrsetbits32(&dwc3->uctl1,
+		DWC3_GUCTL1_CLR_MASK,
+		DWC3_GUCTL1_SET_MASK);
+
+	/* Set GRXTHRCFG based on case 8000615753 values */
+	setbits32(&dwc3->rxthrcfg,
+		DWC3_GRXTHRCFG_USBMAXRXBURSTSIZE(3) |
+		DWC3_GRXTHRCFG_USBRXPKTCNT(3) |
+		DWC3_GRXTHRCFG_USBRXPKTCNTSEL);
+
+	/* Set the bus configuration 1K page pipe limit */
+	setbits32(&dwc3->sbuscfg1,
+		DWC3_GSBUSCFG1_PIPETRANSLIMIT(0xE) |
+		DWC3_GSBUSCFG1_EN1KPAGE);
+
+	/* Set Sparse Control Transaction Enable */
+	setbits32(&dwc3->uctl, DWC3_GUCTL_SPRSCTRLTRANSEN);
+
+	/* Disable sleep mode */
+	clrbits32(config->gusb2phycfg_regs_addr, GUSB2PHYCFG_ENBLSLPM_BIT);
+
+	/* Configure controller in Host mode */
+	clrsetbits32(&dwc3->ctl,
+		DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_OTG),
+		DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_HOST));
+
+	printk(BIOS_SPEW, "Configure USB %s in Host mode\n", config->name);
+
+	/* Enable wake on connect/disconnect/overcurrent */
+	setbits32(config->portsc_20_regs_addr, USB3_PORTSC_WCE_BIT);
+	setbits32(config->portsc_30_regs_addr, USB3_PORTSC_WCE_BIT);
+}
+
+static const struct dwc3_controller_config prim_config = {
+	.name = "Primary",
+	.general_cfg_addr = (u32 *)USB4_SS_USB3_DRD_SP_0_USB31_PRIMGENERAL_CFG,
+	.cgctl_reg_addr = USB4_SS_USB3_DRD_SP_0_USB31_PRIMCGCTL_REG,
+	.link_regs_lu3lfpsrxtim_addr =
+		USB4_SS_USB3_DRD_SP_0_USB31_PRIMLINK_REGS_0_LU3LFPSRXTIM_ADDR,
+	.gusb2phycfg_regs_addr =
+		USB4_SS_USB3_DRD_SP_0_USB31_PRIMGUSB2PHYCFG_REGS_0_GUSB2PHYCFG_ADDR,
+	.portsc_20_regs_addr =
+		USB4_SS_USB3_DRD_SP_0_USB31_PRIMPORTSC_20_REGS_0_PORTSC_20_ADDR,
+	.portsc_30_regs_addr =
+		USB4_SS_USB3_DRD_SP_0_USB31_PRIMPORTSC_30_REGS_0_PORTSC_30_ADDR,
+	.smb_slave_addr = SMB1_SLAVE_ID,
+};
+
+static const struct dwc3_controller_config sec_config = {
+	.name = "Secondary",
+	.general_cfg_addr = (u32 *)USB4_SS_USB3_DRD_SP_1_USB31_SECGENERAL_CFG,
+	.cgctl_reg_addr = USB4_SS_USB3_DRD_SP_1_USB31_SECCGCTL_REG,
+	.link_regs_lu3lfpsrxtim_addr =
+		USB4_SS_USB3_DRD_SP_1_USB31_SECLINK_REGS_0_LU3LFPSRXTIM_ADDR,
+	.gusb2phycfg_regs_addr =
+		USB4_SS_USB3_DRD_SP_1_USB31_SECGUSB2PHYCFG_REGS_0_GUSB2PHYCFG_ADDR,
+	.portsc_20_regs_addr =
+		USB4_SS_USB3_DRD_SP_1_USB31_SECPORTSC_20_REGS_0_PORTSC_20_ADDR,
+	.portsc_30_regs_addr =
+		USB4_SS_USB3_DRD_SP_1_USB31_SECPORTSC_30_REGS_0_PORTSC_30_ADDR,
+	.smb_slave_addr = SMB2_SLAVE_ID,
+};
+
 /* Initialization of DWC3 Core and PHY */
 static void setup_usb_host(struct usb_dwc3_cfg *dwc3)
 {
+	bool high_speed_only_primary = false;
+	bool high_speed_only_secondary = false;
+
 	/* Call Clock Enable */
 	qcom_enable_usb_clk();
 
@@ -311,7 +512,69 @@ static void setup_usb_host(struct usb_dwc3_cfg *dwc3)
 	if (!ret0 || !ret1)
 		hs_speed_only = true;
 
+	/* Type C port 0 - C0 */
+	clock_reset_bcr(dwc3->gcc_qusb2phy_prim_bcr, 1);
+	udelay(10);
+	clock_reset_bcr(dwc3->gcc_qusb2phy_prim_bcr, 0);
+	/* TBD:usb_shared_repeater_reset,usb_shared_repeater_init */
+	/* Initialize secondary HS PHY */
+	hs_usb_phy_init(2);
+
+	/* Reset USB4.0 DP0 PHY, USB3 PHY, and USB3PHY PHY PRIM BCRs */
+	clock_reset_bcr(dwc3->gcc_usb4_0_dp0_phy_prim_bcr, 1);
+	clock_reset_bcr(dwc3->gcc_usb3_phy_prim_bcr, 1);
+	clock_reset_bcr(dwc3->gcc_usb3phy_phy_prim_bcr, 1);
+	udelay(10);
+	clock_reset_bcr(dwc3->gcc_usb3phy_phy_prim_bcr, 0);
+	clock_reset_bcr(dwc3->gcc_usb3_phy_prim_bcr, 0);
+	clock_reset_bcr(dwc3->gcc_usb4_0_dp0_phy_prim_bcr, 0);
+	udelay(10);
+	/* Initialize USB4/USB3 EDP_DP_Con PHY Configuration */
+	int ss0_ret = qmp_usb4_dp_phy_ss_init(0);
+	if (ss0_ret != CB_SUCCESS) {
+		printk(BIOS_ERR, "SS0 QMP PHY initialization failed\n");
+		high_speed_only_primary = true;
+	}
+	/* Enable VBUS for C0 */
+	enable_vbus_ss(&prim_config);
+	udelay(50);
+	usb_typec_status_check(&prim_config);
+
+	/* Type C port 1 - C1 */
+	/* Reset USB secondary[C1] PHY BCRs */
+	clock_reset_bcr(dwc3->gcc_qusb2phy_sec_bcr, 1);
+	udelay(10);
+	clock_reset_bcr(dwc3->gcc_qusb2phy_sec_bcr, 0);
+	/* TBD:usb_shared_repeater_reset,usb_shared_repeater_init for secondary */
+	/* Initialize secondary HS PHY */
+	hs_usb_phy_init(3);
+
+	/* Reset USB4.1 DP0 PHY, USB3 PHY, and USB3PHY PHY SEC BCRs */
+	clock_reset_bcr(dwc3->gcc_usb4_1_dp0_phy_sec_bcr, 1);
+	clock_reset_bcr(dwc3->gcc_usb3_phy_sec_bcr, 1);
+	clock_reset_bcr(dwc3->gcc_usb3phy_phy_sec_bcr, 1);
+	udelay(10);
+	clock_reset_bcr(dwc3->gcc_usb3phy_phy_sec_bcr, 0);
+	clock_reset_bcr(dwc3->gcc_usb3_phy_sec_bcr, 0);
+	clock_reset_bcr(dwc3->gcc_usb4_1_dp0_phy_sec_bcr, 0);
+	udelay(10);
+	/* Initialize USB4/USB3 EDP_DP_Con PHY Configuration (secondary) */
+	int ss1_ret = qmp_usb4_dp_phy_ss_init(1);
+	if (ss1_ret != CB_SUCCESS) {
+		printk(BIOS_ERR, "SS1 QMP PHY initialization failed\n");
+		high_speed_only_secondary = true;
+	}
+	/* Enable VBUS for C1 */
+	enable_vbus_ss(&sec_config);
+	udelay(50);
+	usb_typec_status_check(&sec_config);
+
+	/* Initialize USB Controller for Type A */
 	setup_dwc3(dwc3->usb_host_dwc3);
+	/* Initialize USB Controller for Type C port 0(C0) */
+	setup_dwc3_controller(dwc3->usb_host_dwc3_prim, &prim_config, high_speed_only_primary);
+	/* Initialize USB Controller for Type C port 1(C1) */
+	setup_dwc3_controller(dwc3->usb_host_dwc3_sec, &sec_config, high_speed_only_secondary);
 
 	printk(BIOS_INFO, "DWC3 and PHY setup finished\n");
 }
@@ -322,6 +585,119 @@ static void setup_usb_host(struct usb_dwc3_cfg *dwc3)
 */
 void setup_usb_host0(void)
 {
-	printk(BIOS_INFO, "Setting up USB HOST0 controller.\n");
-	setup_usb_host(&usb_port0);
+	printk(BIOS_INFO, "Setting up USB HOST controller.\n");
+	setup_usb_host(&usb_ports);
+}
+
+/*
+ * usb_update_refclk_for_core - Updates USB reference clock for specified core
+ * @core_num: USB core number (0-4)
+ * @enable: true to enable, false to disable reference clock
+ */
+void usb_update_refclk_for_core(u32 core_num, bool enable)
+{
+	u32 value = enable ? USB_CLKREF_ENABLE_VALUE : 0;
+
+	switch (core_num) {
+	case 1:
+		clrsetbits32(TCSR_GCC_USB4_1_CLKREF_EN_ADDR, 0x1, value);
+		clrsetbits32(TCSR_GCC_USB2_1_CLKREF_EN_ADDR, 0x1, value);
+		break;
+	case 2:
+		clrsetbits32(TCSR_GCC_USB4_2_CLKREF_EN_ADDR, 0x1, value);
+		clrsetbits32(TCSR_GCC_USB2_2_CLKREF_EN_ADDR, 0x1, value);
+		break;
+	case 3:
+		clrsetbits32(TCSR_GCC_USB3_MP0_CLKREF_EN_ADDR, 0x1, value);
+		clrsetbits32(TCSR_GCC_USB3_MP1_CLKREF_EN_ADDR, 0x1, value);
+		break;
+	default:
+		/* No clkref */
+		break;
+	}
+}
+
+/*
+ * wait_for_otg_enabled - Waits for OTG block to reach enabled state
+ * @status_reg_addr: SPMI address of the OTG status register
+ * @core_name: Name of the core for logging (e.g., "SMB1", "SMB2")
+ * @return: true if OTG enabled successfully, false if timeout or error
+ */
+static bool wait_for_otg_enabled(u32 status_reg_addr, const char *core_name)
+{
+	u32 timeout_ms = 0;
+	u8 otg_status;
+	u8 otg_state;
+
+	while (timeout_ms < OTG_STATUS_TIMEOUT_MS) {
+		otg_status = spmi_read8(status_reg_addr);
+		otg_state = otg_status & OTG_STATE_MASK;
+
+		printk(BIOS_DEBUG, "%s OTG Status: 0x%02x, State: 0x%02x\n",
+		       core_name, otg_status, otg_state);
+
+		switch (otg_state) {
+		case OTG_STATE_ENABLED:
+			printk(BIOS_INFO, "%s OTG block enabled successfully\n", core_name);
+			return true;
+		case OTG_STATE_ERROR:
+			printk(BIOS_ERR, "%s OTG block in ERROR state (0x%02x)\n",
+			       core_name, otg_status);
+			return false;
+		case OTG_STATE_DISABLED:
+		case OTG_STATE_ENABLING:
+		case OTG_STATE_DISABLING:
+			/* Continue polling */
+			break;
+		default:
+			printk(BIOS_WARNING, "%s OTG block in unknown state: 0x%02x\n",
+			       core_name, otg_state);
+			break;
+		}
+
+		mdelay(OTG_STATUS_POLL_INTERVAL_MS);
+		timeout_ms += OTG_STATUS_POLL_INTERVAL_MS;
+	}
+
+	printk(BIOS_ERR, "%s OTG enable timeout after %d ms, final state: 0x%02x\n",
+	       core_name, timeout_ms, otg_state);
+	return false;
+}
+
+/*
+ * enable_vbus_ss - Enables VBUS SuperSpeed for specified USB core
+ * @config: Controller configuration containing SMB slave address
+ */
+void enable_vbus_ss(const struct dwc3_controller_config *config)
+{
+	u8 slave = config->smb_slave_addr;
+
+	printk(BIOS_INFO, "Enabling %s VBUS SuperSpeed\n", config->name);
+
+	spmi_write8(SPMI_ADDR(slave, SCHG_DCDC_OTG_CFG), 0x20);
+	spmi_write8(SPMI_ADDR(slave, SCHG_DCDC_CMD_OTG), 0x1);
+
+	/* Wait for OTG block to reach enabled state */
+	if (!wait_for_otg_enabled(SPMI_ADDR(slave, SCHG_DCDC_OTG_STATUS), config->name))
+		printk(BIOS_ERR, "%s OTG enable failed\n", config->name);
+}
+
+/*
+ * usb_typec_status_check - Reads comprehensive Type-C status from PMIC
+ * @config: Controller configuration containing SMB slave address
+ */
+void usb_typec_status_check(const struct dwc3_controller_config *config)
+{
+	u8 slave = config->smb_slave_addr;
+	u8 misc_status, src_status, mode_cfg;
+
+	misc_status = spmi_read8(SPMI_ADDR(slave, SCHG_TYPE_C_TYPE_C_MISC_STATUS));
+	src_status = spmi_read8(SPMI_ADDR(slave, SCHG_TYPE_C_TYPE_C_SRC_STATUS));
+	mode_cfg = spmi_read8(SPMI_ADDR(slave, SCHG_TYPE_C_TYPE_C_MODE_CFG));
+
+	printk(BIOS_INFO, "%s Type-C Status:\n", config->name);
+	printk(BIOS_INFO, "  Misc Status (0x2B0B): 0x%02x, VBUS Status (bit 5): %d\n",
+	       misc_status, (misc_status & TYPEC_VBUS_STATUS_MASK) ? 1 : 0);
+	printk(BIOS_INFO, "  Src Status (0x2B08): 0x%02x\n", src_status);
+	printk(BIOS_INFO, "  Mode Config (0x2B44): 0x%02x\n", mode_cfg);
 }

From 88439b4cd39fee9b5299b56856d3633b01a7d098 Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Fri, 10 Oct 2025 11:31:14 +0100
Subject: [PATCH 2211/3886] mb/starlabs/starbook/mtl: Set the VPU default to
 disabled

Change-Id: I7e1b6c752e440a9fff271a7775f4ffe9879bb8c4
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89518
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
---
 src/mainboard/starlabs/starbook/cfr.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/mainboard/starlabs/starbook/cfr.h b/src/mainboard/starlabs/starbook/cfr.h
index ddf1d15e1b..7062fd436e 100644
--- a/src/mainboard/starlabs/starbook/cfr.h
+++ b/src/mainboard/starlabs/starbook/cfr.h
@@ -73,7 +73,7 @@ static const struct sm_object vpu = SM_DECLARE_BOOL({
 	.opt_name	= "vpu",
 	.ui_name	= "VPU",
 	.ui_helptext	= "Enable or disable VPU",
-	.default_value	= true,
+	.default_value	= false,
 });
 
 static const struct sm_object webcam = SM_DECLARE_BOOL({

From 1f328351e6d179bfc1f6deaaf23771280ed65b74 Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Sat, 11 Oct 2025 20:40:04 +0100
Subject: [PATCH 2212/3886] mb/starlabs/*: Select SPD_READ_BY_WORD

This saves boot time (approx 82ms).

Change-Id: Ib6c07d941c634d3be7449740f48b2a012a9e8cc6
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89526
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
---
 src/mainboard/starlabs/byte_adl/Kconfig     | 1 +
 src/mainboard/starlabs/lite/Kconfig         | 1 +
 src/mainboard/starlabs/starbook/Kconfig     | 1 +
 src/mainboard/starlabs/starfighter/Kconfig  | 1 +
 src/mainboard/starlabs/starlite_adl/Kconfig | 1 +
 5 files changed, 5 insertions(+)

diff --git a/src/mainboard/starlabs/byte_adl/Kconfig b/src/mainboard/starlabs/byte_adl/Kconfig
index eb9280edc9..234d59b43f 100644
--- a/src/mainboard/starlabs/byte_adl/Kconfig
+++ b/src/mainboard/starlabs/byte_adl/Kconfig
@@ -21,6 +21,7 @@ config BOARD_STARLABS_BYTE_SERIES
 	select SOC_INTEL_COMMON_BLOCK_HDA_VERB
 	select SOC_INTEL_COMMON_BLOCK_TCSS
 	select SOC_INTEL_CRASHLOG
+	select SPD_READ_BY_WORD
 	select SPI_FLASH_WINBOND
 	select SYSTEM_TYPE_MINIPC
 	select TPM2
diff --git a/src/mainboard/starlabs/lite/Kconfig b/src/mainboard/starlabs/lite/Kconfig
index fa82f5eba2..2218b4e051 100644
--- a/src/mainboard/starlabs/lite/Kconfig
+++ b/src/mainboard/starlabs/lite/Kconfig
@@ -19,6 +19,7 @@ config BOARD_STARLABS_LITE_SERIES
 	select ONBOARD_VGA_IS_PRIMARY
 	select SOC_INTEL_COMMON_BLOCK_HDA
 	select SOC_INTEL_COMMON_BLOCK_HDA_VERB
+	select SPD_READ_BY_WORD
 	select SPI_FLASH_GIGADEVICE
 	select SYSTEM_TYPE_LAPTOP
 	select TPM2
diff --git a/src/mainboard/starlabs/starbook/Kconfig b/src/mainboard/starlabs/starbook/Kconfig
index ac265a92fc..fd93a9b070 100644
--- a/src/mainboard/starlabs/starbook/Kconfig
+++ b/src/mainboard/starlabs/starbook/Kconfig
@@ -16,6 +16,7 @@ config BOARD_STARLABS_STARBOOK_SERIES
 	select INTEL_GMA_HAVE_VBT
 	select INTEL_LPSS_UART_FOR_CONSOLE
 	select NO_UART_ON_SUPERIO
+	select SPD_READ_BY_WORD
 	select SOC_INTEL_COMMON_BLOCK_HDA_VERB
 	select SYSTEM_TYPE_LAPTOP
 	select VALIDATE_INTEL_DESCRIPTOR
diff --git a/src/mainboard/starlabs/starfighter/Kconfig b/src/mainboard/starlabs/starfighter/Kconfig
index 4b08a351cf..8dfbf1b101 100644
--- a/src/mainboard/starlabs/starfighter/Kconfig
+++ b/src/mainboard/starlabs/starfighter/Kconfig
@@ -37,6 +37,7 @@ config BOARD_STARLABS_STARFIGHTER_SERIES
 	select SOC_INTEL_CRASHLOG
 	select SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES
 	select SOC_INTEL_RAPTORLAKE
+	select SPD_READ_BY_WORD
 	select SPI_FLASH_WINBOND
 	select SYSTEM_TYPE_LAPTOP
 	select TPM_MEASURED_BOOT
diff --git a/src/mainboard/starlabs/starlite_adl/Kconfig b/src/mainboard/starlabs/starlite_adl/Kconfig
index d67a42a4f5..36b61a71f5 100644
--- a/src/mainboard/starlabs/starlite_adl/Kconfig
+++ b/src/mainboard/starlabs/starlite_adl/Kconfig
@@ -30,6 +30,7 @@ config BOARD_STARLABS_STARLITE_SERIES
 	select SOC_INTEL_COMMON_BLOCK_HDA_VERB
 	select SOC_INTEL_COMMON_BLOCK_TCSS
 	select SOC_INTEL_CRASHLOG
+	select SPD_READ_BY_WORD
 	select SPI_FLASH_WINBOND
 	select SYSTEM_TYPE_DETACHABLE
 	select TPM2

From 23419df34cf447d94994ae74b241ab0b40216140 Mon Sep 17 00:00:00 2001
From: Subrata Banik <subratabanik@google.com>
Date: Thu, 9 Oct 2025 16:28:08 +0530
Subject: [PATCH 2213/3886] drivers/intel/fsp2_0: Implement API to retrieve
 DIMM info

This patch extracts the implementation responsible for retrieving DIMM
information from the FSP HOBs and centralizes it within the common FSP
driver code.

This ensures that each SoC layer does not duplicate the logic for
parsing memory-related data. The primary goal is to rely on the
common FSP driver code for retrieving memory information.

The only SoC-specific implementation that remains is limited to
handling dependencies related to FSP UPD or header differences across
SoC generations.

TEST=Able to build and boot google/kinmen. Verify the memory related
information is proper as part of the SMBIOS table.

Change-Id: Ic3741a248bb1fe9420c784d51fbf459a30f8c42f
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89494
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/drivers/intel/fsp2_0/Kconfig           |   7 ++
 src/drivers/intel/fsp2_0/Makefile.mk       |   1 +
 src/drivers/intel/fsp2_0/fsp_dimm_info.c   | 139 +++++++++++++++++++++
 src/drivers/intel/fsp2_0/include/fsp/api.h |  15 +++
 4 files changed, 162 insertions(+)
 create mode 100644 src/drivers/intel/fsp2_0/fsp_dimm_info.c

diff --git a/src/drivers/intel/fsp2_0/Kconfig b/src/drivers/intel/fsp2_0/Kconfig
index 715ec2a759..ed599d5e72 100644
--- a/src/drivers/intel/fsp2_0/Kconfig
+++ b/src/drivers/intel/fsp2_0/Kconfig
@@ -493,4 +493,11 @@ config USE_COREBOOT_FOR_BMP_RENDERING
 	  Platforms can choose to override this Kconfig option based on their
 	  specific graphics requirements and FSP capabilities.
 
+config FSP_DIMM_INFO
+	bool
+	default n
+	help
+	  Select this option to retrieve DIMM (Memory) related information by relying on
+	  the Intel FSP. coreboot relies on this information to prepare SMBIOS table 17.
+
 endif
diff --git a/src/drivers/intel/fsp2_0/Makefile.mk b/src/drivers/intel/fsp2_0/Makefile.mk
index 16905ca373..a7dd80a1ed 100644
--- a/src/drivers/intel/fsp2_0/Makefile.mk
+++ b/src/drivers/intel/fsp2_0/Makefile.mk
@@ -17,6 +17,7 @@ romstage-$(CONFIG_MMA) += mma_core.c
 romstage-y += cbmem.c
 romstage-$(CONFIG_ENABLE_FSP_ERROR_INFO) += fsp_error_info_hob.c
 romstage-$(CONFIG_CACHE_MRC_SETTINGS) += save_mrc_data.c
+romstage-$(CONFIG_FSP_DIMM_INFO) += fsp_dimm_info.c
 
 ramstage-y += debug.c
 ramstage-$(CONFIG_FSP_USES_CB_DEBUG_EVENT_HANDLER) += fsp_debug_event.c
diff --git a/src/drivers/intel/fsp2_0/fsp_dimm_info.c b/src/drivers/intel/fsp2_0/fsp_dimm_info.c
new file mode 100644
index 0000000000..82e1fa157b
--- /dev/null
+++ b/src/drivers/intel/fsp2_0/fsp_dimm_info.c
@@ -0,0 +1,139 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <cbmem.h>
+#include <console/console.h>
+#include <fsp/api.h>
+#include <fsp/util.h>
+#include <memory_info.h>
+#include <soc/intel/common/smbios.h>
+#include <string.h>
+
+/*
+ * Processes a single DIMM slot, checks for presence, fills in the
+ * dimm_info structure, and prepares for SMBIOS table creation.
+ *
+ * @param src_dimm: Source DIMM info from FSP HOB.
+ * @param dest_dimm: Destination DIMM info in CBMEM.
+ * @param channel_info: Channel info from FSP HOB.
+ * @param meminfo_hob: Overall memory info HOB.
+ * @param node: Memory controller node index.
+ * @param dram_part_num_ptr: Pointer to the current DRAM part number string.
+ * @param dram_part_num_len_ptr: Pointer to the current DRAM part number length.
+ * @return 1 if a DIMM was processed (index incremented), 0 otherwise.
+ */
+static int fsp_process_dimm_slot(const DIMM_INFO *src_dimm,
+				 struct dimm_info *dest_dimm,
+				 const CHANNEL_INFO *channel_info,
+				 const MEMORY_INFO_DATA_HOB *meminfo_hob,
+				 int node,
+				 const char **dram_part_num_ptr,
+				 size_t *dram_part_num_len_ptr)
+{
+	const char *dram_part_num = *dram_part_num_ptr;
+	size_t dram_part_num_len = *dram_part_num_len_ptr;
+	const uint8_t *serial_num;
+	uint8_t mem_profile_number;
+	struct dimm_fill_args fill_args;
+
+	if (src_dimm->Status != DIMM_PRESENT)
+		return 0;
+
+	/* If there is no DRAM part number overridden by
+	 * mainboard then use original one. */
+	if (!dram_part_num) {
+		dram_part_num_len = sizeof(src_dimm->ModulePartNum);
+		dram_part_num = (const char *)&src_dimm->ModulePartNum[0];
+	}
+
+	mem_profile_number = meminfo_hob->MemoryProfile;
+	serial_num = src_dimm->SpdSave + SPD_SAVE_OFFSET_SERIAL;
+
+	platform_fill_dimm_info_args(src_dimm, meminfo_hob, &fill_args);
+
+	/* Populate the DIMM information */
+	dimm_info_fill(dest_dimm,
+		src_dimm->DimmCapacity,
+		meminfo_hob->MemoryType,
+		meminfo_hob->ConfiguredMemoryClockSpeed,
+		src_dimm->RankInDimm,
+		channel_info->ChannelId,
+		src_dimm->DimmId,
+		dram_part_num,
+		dram_part_num_len,
+		serial_num,
+		fill_args.data_width,
+		meminfo_hob->VddVoltage[mem_profile_number],
+		meminfo_hob->EccSupport,
+		fill_args.mfg_id_arg,
+		src_dimm->SpdModuleType,
+		node,
+		meminfo_hob->MaximumMemoryClockSpeed);
+
+	/* Update the pointers in case the DRAM part number was set here */
+	*dram_part_num_ptr = dram_part_num;
+	*dram_part_num_len_ptr = dram_part_num_len;
+
+	return 1;
+}
+
+void fsp_save_dimm_info(void)
+{
+	int node, channel, dimm_max;
+	size_t hob_size;
+	const CONTROLLER_INFO *ctrlr_info;
+	const CHANNEL_INFO *channel_info;
+	struct memory_info *mem_info;
+	const MEMORY_INFO_DATA_HOB *meminfo_hob;
+	const uint8_t smbios_memory_info_guid[] = {
+		0xd4, 0x71, 0x20, 0x9b, 0x54, 0xb0, 0x0c, 0x4e,
+		0x8d, 0x09, 0x11, 0xcf, 0x8b, 0x9f, 0x03, 0x23
+	};
+	const char *dram_part_num = NULL;
+	size_t dram_part_num_len = 0;
+
+	/* Locate the memory info HOB, presence validated by raminit */
+	meminfo_hob = fsp_find_extension_hob_by_guid(smbios_memory_info_guid, &hob_size);
+
+	if (!meminfo_hob || hob_size == 0) {
+		printk(BIOS_ERR, "SMBIOS MEMORY_INFO_DATA_HOB not found\n");
+		return;
+	}
+
+	/* Allocate CBMEM area for DIMM information... */
+	mem_info = cbmem_add(CBMEM_ID_MEMINFO, sizeof(*mem_info));
+	if (!mem_info) {
+		printk(BIOS_ERR, "CBMEM entry for DIMM info missing\n");
+		return;
+	}
+
+	memset(mem_info, 0, sizeof(*mem_info));
+
+	/* Allow mainboard to override DRAM part number. */
+	dram_part_num = mainboard_get_dram_part_num();
+	if (dram_part_num)
+		dram_part_num_len = strlen(dram_part_num);
+
+	/* Save available DIMM information */
+	size_t dimm = 0;
+	dimm_max = ARRAY_SIZE(mem_info->dimm);
+	for (node = 0; node < MAX_NODE; node++) {
+		ctrlr_info = &meminfo_hob->Controller[node];
+		for (channel = 0; channel < MAX_CH && dimm < dimm_max; channel++) {
+			channel_info = &ctrlr_info->ChannelInfo[channel];
+			if (channel_info->Status != CHANNEL_PRESENT)
+				continue;
+			for (size_t index = 0; index < MAX_DIMM && dimm < dimm_max; index++)
+				dimm += fsp_process_dimm_slot(&channel_info->DimmInfo[index],
+							&mem_info->dimm[dimm],
+							channel_info, meminfo_hob,
+							node, &dram_part_num,
+							&dram_part_num_len);
+		}
+	}
+
+	mem_info->dimm_cnt = dimm;
+	if (mem_info->dimm_cnt == 0)
+		printk(BIOS_ERR, "No DIMMs found\n");
+	else
+		printk(BIOS_DEBUG, "%d DIMMs found\n", mem_info->dimm_cnt);
+}
diff --git a/src/drivers/intel/fsp2_0/include/fsp/api.h b/src/drivers/intel/fsp2_0/include/fsp/api.h
index 84edb640b2..b9a58dbaa0 100644
--- a/src/drivers/intel/fsp2_0/include/fsp/api.h
+++ b/src/drivers/intel/fsp2_0/include/fsp/api.h
@@ -50,6 +50,21 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd);
 /* Callbacks for SoC/Mainboard specific overrides */
 void platform_fsp_memory_multi_phase_init_cb(uint32_t phase_index);
 void platform_fsp_silicon_multi_phase_init_cb(uint32_t phase_index);
+
+#if CONFIG(FSP_DIMM_INFO)
+struct dimm_fill_args {
+	uint16_t data_width;
+	uint16_t mfg_id_arg;
+};
+
+/* Retrieve DIMM Information by relying on the FSP */
+void fsp_save_dimm_info(void);
+/* Callbacks for SoC/Mainboard specific overrides */
+void platform_fill_dimm_info_args(const DIMM_INFO *src_dimm,
+	    const MEMORY_INFO_DATA_HOB *meminfo_hob,
+	    struct dimm_fill_args *args);
+#endif
+
 /*
  * Displays an early shutdown notification to the user.
  *

From e168a516e4545fb6cf0e064d22c0af569ec6e22e Mon Sep 17 00:00:00 2001
From: Subrata Banik <subratabanik@google.com>
Date: Thu, 9 Oct 2025 17:06:20 +0530
Subject: [PATCH 2214/3886] soc/intel/pantherlake: Rely on FSP_DIMM_INFO

This patch updates the Panther Lake SoC configuration to select the
`FSP_DIMM_INFO` Kconfig option. This change instructs the build system
to use the common FSP driver implementation for retrieving and storing
DIMM information.

As a result, the duplicated, SoC-specific DIMM information retrieval
logic is dropped from the Panther Lake SoC code base, centralizing
the memory parsing mechanism.

TEST=Able to build and boot google/kinmen. Verify the memory
related information is proper as part of the SMBIOS table.

Change-Id: I3323d3add9213cc384b9a2ca978681287d0e1822
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89495
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
---
 src/soc/intel/pantherlake/Kconfig             |   1 +
 src/soc/intel/pantherlake/romstage/romstage.c | 111 ++----------------
 2 files changed, 8 insertions(+), 104 deletions(-)

diff --git a/src/soc/intel/pantherlake/Kconfig b/src/soc/intel/pantherlake/Kconfig
index 60dc9e3390..7d6e9f7248 100644
--- a/src/soc/intel/pantherlake/Kconfig
+++ b/src/soc/intel/pantherlake/Kconfig
@@ -19,6 +19,7 @@ config SOC_INTEL_PANTHERLAKE_BASE
 	select DISPLAY_FSP_VERSION_INFO_2
 	select DRAM_SUPPORT_DDR5
 	select DRIVERS_USB_ACPI
+	select FSP_DIMM_INFO
 	select FAST_SPI_DMA
 	select FAST_SPI_SUPPORTS_EXT_BIOS_WINDOW
 	select FSP_COMPRESS_FSP_S_LZ4
diff --git a/src/soc/intel/pantherlake/romstage/romstage.c b/src/soc/intel/pantherlake/romstage/romstage.c
index a6fd887123..fa4d941b2d 100644
--- a/src/soc/intel/pantherlake/romstage/romstage.c
+++ b/src/soc/intel/pantherlake/romstage/romstage.c
@@ -3,14 +3,12 @@
 #include <arch/romstage.h>
 #include <cbmem.h>
 #include <console/console.h>
-#include <fsp/util.h>
+#include <fsp/api.h>
 #include <intelblocks/cfg.h>
 #include <intelblocks/cse.h>
 #include <intelblocks/pmclib.h>
 #include <intelblocks/smbus.h>
 #include <intelblocks/thermal.h>
-#include <memory_info.h>
-#include <soc/intel/common/smbios.h>
 #include <soc/iomap.h>
 #include <soc/pm.h>
 #include <soc/romstage.h>
@@ -18,107 +16,12 @@
 #include <string.h>
 #include <timestamp.h>
 
-#define FSP_SMBIOS_MEMORY_INFO_GUID	\
-{	\
-	0xd4, 0x71, 0x20, 0x9b, 0x54, 0xb0, 0x0c, 0x4e,	\
-	0x8d, 0x09, 0x11, 0xcf, 0x8b, 0x9f, 0x03, 0x23	\
-}
-
-/* Save the DIMM information for SMBIOS table 17 */
-static void save_dimm_info(void)
+void platform_fill_dimm_info_args(const DIMM_INFO *src_dimm,
+	    const MEMORY_INFO_DATA_HOB *meminfo_hob,
+	    struct dimm_fill_args *args)
 {
-	int node, channel, dimm, dimm_max, index;
-	size_t hob_size;
-	const CONTROLLER_INFO *ctrlr_info;
-	const CHANNEL_INFO *channel_info;
-	const DIMM_INFO *src_dimm;
-	struct dimm_info *dest_dimm;
-	struct memory_info *mem_info;
-	const MEMORY_INFO_DATA_HOB *meminfo_hob;
-	const uint8_t smbios_memory_info_guid[sizeof(EFI_GUID)] = FSP_SMBIOS_MEMORY_INFO_GUID;
-	const uint8_t *serial_num;
-	const char *dram_part_num = NULL;
-	size_t dram_part_num_len = 0;
-
-	/* Locate the memory info HOB, presence validated by raminit */
-	meminfo_hob = fsp_find_extension_hob_by_guid(
-						smbios_memory_info_guid,
-						&hob_size);
-	if (!meminfo_hob || hob_size == 0) {
-		printk(BIOS_ERR, "SMBIOS MEMORY_INFO_DATA_HOB not found\n");
-		return;
-	}
-
-	/*
-	 * Allocate CBMEM area for DIMM information used to populate SMBIOS
-	 * table 17
-	 */
-	mem_info = cbmem_add(CBMEM_ID_MEMINFO, sizeof(*mem_info));
-	if (!mem_info) {
-		printk(BIOS_ERR, "CBMEM entry for DIMM info missing\n");
-		return;
-	}
-	memset(mem_info, 0, sizeof(*mem_info));
-
-	/* Allow mainboard to override DRAM part number. */
-	dram_part_num = mainboard_get_dram_part_num();
-	if (dram_part_num)
-		dram_part_num_len = strlen(dram_part_num);
-
-	/* Save available DIMM information */
-	index = 0;
-	dimm_max = ARRAY_SIZE(mem_info->dimm);
-	for (node = 0; node < MAX_NODE; node++) {
-		ctrlr_info = &meminfo_hob->Controller[node];
-		for (channel = 0; channel < MAX_CH && index < dimm_max; channel++) {
-			channel_info = &ctrlr_info->ChannelInfo[channel];
-			if (channel_info->Status != CHANNEL_PRESENT)
-				continue;
-
-			for (dimm = 0; dimm < MAX_DIMM && index < dimm_max; dimm++) {
-				src_dimm = &channel_info->DimmInfo[dimm];
-				dest_dimm = &mem_info->dimm[index];
-				if (src_dimm->Status != DIMM_PRESENT)
-					continue;
-
-				/* If there is no DRAM part number overridden by
-				 * mainboard then use original one. */
-				if (!dram_part_num) {
-					dram_part_num_len = sizeof(src_dimm->ModulePartNum);
-					dram_part_num = (const char *)
-							&src_dimm->ModulePartNum[0];
-				}
-
-				uint8_t memProfNum = meminfo_hob->MemoryProfile;
-				serial_num = src_dimm->SpdSave + SPD_SAVE_OFFSET_SERIAL;
-
-				/* Populate the DIMM information */
-				dimm_info_fill(dest_dimm,
-					src_dimm->DimmCapacity,
-						meminfo_hob->MemoryType,
-						meminfo_hob->ConfiguredMemoryClockSpeed,
-					src_dimm->RankInDimm,
-					channel_info->ChannelId,
-					src_dimm->DimmId,
-						dram_part_num,
-						dram_part_num_len,
-						serial_num,
-						src_dimm->DataWidth,
-						meminfo_hob->VddVoltage[memProfNum],
-						meminfo_hob->EccSupport,
-					src_dimm->MfgId.Data,
-					src_dimm->SpdModuleType,
-					node,
-					meminfo_hob->MaximumMemoryClockSpeed);
-				index++;
-			}
-		}
-	}
-	mem_info->dimm_cnt = index;
-	if (mem_info->dimm_cnt == 0)
-		printk(BIOS_ERR, "No DIMMs found\n");
-	else
-		printk(BIOS_DEBUG, "%d DIMMs found\n", mem_info->dimm_cnt);
+	args->data_width = src_dimm->DataWidth;
+	args->mfg_id_arg = src_dimm->MfgId.Data;
 }
 
 void mainboard_romstage_entry(void)
@@ -155,5 +58,5 @@ void mainboard_romstage_entry(void)
 	fsp_memory_init(s3wake);
 	pmc_set_disb();
 	if (!s3wake)
-		save_dimm_info();
+		fsp_save_dimm_info();
 }

From d5a8cec7487b037fea07b49caac16f08fd0b6415 Mon Sep 17 00:00:00 2001
From: Subrata Banik <subratabanik@google.com>
Date: Thu, 9 Oct 2025 17:27:42 +0530
Subject: [PATCH 2215/3886] soc/intel/meteorlake: Rely on FSP_DIMM_INFO

This patch updates the Meteor Lake SoC configuration to select the
`FSP_DIMM_INFO` Kconfig option. This change instructs the build system
to use the common FSP driver implementation for retrieving and storing
DIMM information.

As a result, the duplicated, SoC-specific DIMM information retrieval
logic is dropped from the Panther Lake SoC code base, centralizing
the memory parsing mechanism.

TEST=Able to build and boot google/screebo. Verify the memory related
information is proper as part of the SMBIOS table.

Change-Id: I88fe72b558d2f9af55b585fd20f5f55e15eb465f
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89496
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/soc/intel/meteorlake/Kconfig             |   1 +
 src/soc/intel/meteorlake/romstage/romstage.c | 111 ++-----------------
 2 files changed, 8 insertions(+), 104 deletions(-)

diff --git a/src/soc/intel/meteorlake/Kconfig b/src/soc/intel/meteorlake/Kconfig
index c1c2266973..a0e648a856 100644
--- a/src/soc/intel/meteorlake/Kconfig
+++ b/src/soc/intel/meteorlake/Kconfig
@@ -18,6 +18,7 @@ config SOC_INTEL_METEORLAKE
 	select DRIVERS_USB_ACPI
 	select EDK2_CPU_TIMER_LIB if PAYLOAD_EDK2
 	select FSP_COMPRESS_FSP_S_LZ4
+	select FSP_DIMM_INFO
 	select FAST_SPI_SUPPORTS_EXT_BIOS_WINDOW
 	select FSP_M_XIP
 	select FSP_UGOP_EARLY_SIGN_OF_LIFE if !SOC_INTEL_METEORLAKE_PRE_PRODUCTION_SILICON && !BOARD_GOOGLE_BASEBOARD_OVIS
diff --git a/src/soc/intel/meteorlake/romstage/romstage.c b/src/soc/intel/meteorlake/romstage/romstage.c
index 5ceb6d5577..d509ae5147 100644
--- a/src/soc/intel/meteorlake/romstage/romstage.c
+++ b/src/soc/intel/meteorlake/romstage/romstage.c
@@ -3,121 +3,24 @@
 #include <arch/romstage.h>
 #include <cbmem.h>
 #include <console/console.h>
-#include <fsp/util.h>
+#include <fsp/api.h>
 #include <intelblocks/cfg.h>
 #include <intelblocks/cse.h>
 #include <intelblocks/pmclib.h>
 #include <intelblocks/smbus.h>
 #include <intelblocks/thermal.h>
-#include <memory_info.h>
-#include <soc/intel/common/smbios.h>
 #include <soc/iomap.h>
 #include <soc/pm.h>
 #include <soc/romstage.h>
 #include <soc/soc_chip.h>
 #include <string.h>
 
-#define FSP_SMBIOS_MEMORY_INFO_GUID	\
-{	\
-	0xd4, 0x71, 0x20, 0x9b, 0x54, 0xb0, 0x0c, 0x4e,	\
-	0x8d, 0x09, 0x11, 0xcf, 0x8b, 0x9f, 0x03, 0x23	\
-}
-
-/* Save the DIMM information for SMBIOS table 17 */
-static void save_dimm_info(void)
+void platform_fill_dimm_info_args(const DIMM_INFO *src_dimm,
+	    const MEMORY_INFO_DATA_HOB *meminfo_hob,
+	    struct dimm_fill_args *args)
 {
-	int node, channel, dimm, dimm_max, index;
-	size_t hob_size;
-	const CONTROLLER_INFO *ctrlr_info;
-	const CHANNEL_INFO *channel_info;
-	const DIMM_INFO *src_dimm;
-	struct dimm_info *dest_dimm;
-	struct memory_info *mem_info;
-	const MEMORY_INFO_DATA_HOB *meminfo_hob;
-	const uint8_t smbios_memory_info_guid[sizeof(EFI_GUID)] = FSP_SMBIOS_MEMORY_INFO_GUID;
-	const uint8_t *serial_num;
-	const char *dram_part_num = NULL;
-	size_t dram_part_num_len = 0;
-
-	/* Locate the memory info HOB, presence validated by raminit */
-	meminfo_hob = fsp_find_extension_hob_by_guid(
-						smbios_memory_info_guid,
-						&hob_size);
-	if (!meminfo_hob || hob_size == 0) {
-		printk(BIOS_ERR, "SMBIOS MEMORY_INFO_DATA_HOB not found\n");
-		return;
-	}
-
-	/*
-	 * Allocate CBMEM area for DIMM information used to populate SMBIOS
-	 * table 17
-	 */
-	mem_info = cbmem_add(CBMEM_ID_MEMINFO, sizeof(*mem_info));
-	if (!mem_info) {
-		printk(BIOS_ERR, "CBMEM entry for DIMM info missing\n");
-		return;
-	}
-	memset(mem_info, 0, sizeof(*mem_info));
-
-	/* Allow mainboard to override DRAM part number. */
-	dram_part_num = mainboard_get_dram_part_num();
-	if (dram_part_num)
-		dram_part_num_len = strlen(dram_part_num);
-
-	/* Save available DIMM information */
-	index = 0;
-	dimm_max = ARRAY_SIZE(mem_info->dimm);
-	for (node = 0; node < MAX_NODE; node++) {
-		ctrlr_info = &meminfo_hob->Controller[node];
-		for (channel = 0; channel < MAX_CH && index < dimm_max; channel++) {
-			channel_info = &ctrlr_info->ChannelInfo[channel];
-			if (channel_info->Status != CHANNEL_PRESENT)
-				continue;
-
-			for (dimm = 0; dimm < MAX_DIMM && index < dimm_max; dimm++) {
-				src_dimm = &channel_info->DimmInfo[dimm];
-				dest_dimm = &mem_info->dimm[index];
-				if (src_dimm->Status != DIMM_PRESENT)
-					continue;
-
-				/* If there is no DRAM part number overridden by
-				 * mainboard then use original one. */
-				if (!dram_part_num) {
-					dram_part_num_len = sizeof(src_dimm->ModulePartNum);
-					dram_part_num = (const char *)
-							&src_dimm->ModulePartNum[0];
-				}
-
-				uint8_t memProfNum = meminfo_hob->MemoryProfile;
-				serial_num = src_dimm->SpdSave + SPD_SAVE_OFFSET_SERIAL;
-
-				/* Populate the DIMM information */
-				dimm_info_fill(dest_dimm,
-					src_dimm->DimmCapacity,
-						meminfo_hob->MemoryType,
-						meminfo_hob->ConfiguredMemoryClockSpeed,
-					src_dimm->RankInDimm,
-					channel_info->ChannelId,
-					src_dimm->DimmId,
-						dram_part_num,
-						dram_part_num_len,
-						serial_num,
-						meminfo_hob->DataWidth,
-						meminfo_hob->VddVoltage[memProfNum],
-						meminfo_hob->EccSupport,
-					src_dimm->MfgId,
-					src_dimm->SpdModuleType,
-					node,
-					meminfo_hob->MaximumMemoryClockSpeed);
-				index++;
-			}
-		}
-	}
-	mem_info->dimm_cnt = index;
-	if (mem_info->dimm_cnt == 0)
-		printk(BIOS_ERR, "No DIMMs found\n");
-	else
-		printk(BIOS_DEBUG, "%d DIMMs found\n", mem_info->dimm_cnt);
+	args->data_width = meminfo_hob->DataWidth;
+	args->mfg_id_arg = src_dimm->MfgId;
 }
 
 void mainboard_romstage_entry(void)
@@ -154,5 +57,5 @@ void mainboard_romstage_entry(void)
 	fsp_memory_init(s3wake);
 	pmc_set_disb();
 	if (!s3wake)
-		save_dimm_info();
+		fsp_save_dimm_info();
 }

From 60ef877d9387382eb45c6436a3d92f7b799a49c2 Mon Sep 17 00:00:00 2001
From: Youwen Huang <huangyouwen5@huaqin.corp-partner.google.com>
Date: Thu, 9 Oct 2025 17:48:18 +0800
Subject: [PATCH 2216/3886] mb/google/skywalker: Modify the RST pin naming

Modify the RST pin naming to keep the code consistent.

BUG=b:422688421
TEST=emerge-jedi coreboot chromeos-bootimage
BRANCH=Skywalker

Change-Id: Icf39bf77d24fd423309aa7f451c1fc07b5bfd057
Signed-off-by: Youwen Huang <huangyouwen5@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89491
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/google/skywalker/chromeos.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/mainboard/google/skywalker/chromeos.c b/src/mainboard/google/skywalker/chromeos.c
index b364282dcb..d7494bb1bc 100644
--- a/src/mainboard/google/skywalker/chromeos.c
+++ b/src/mainboard/google/skywalker/chromeos.c
@@ -84,7 +84,7 @@ void fill_lb_gpios(struct lb_gpios *gpios)
 		lb_add_gpios(gpios, alc5645_gpios, ARRAY_SIZE(alc5645_gpios));
 	} else if (fw_config_probe(FW_CONFIG(AUDIO_AMP, AMP_CS35L51))) {
 		struct lb_gpio cs35l51_gpios[] = {
-			{GPIO_RST_SPKR_L.id, ACTIVE_LOW, -1, "speaker reset"},
+			{GPIO_RST_SPKR_L.id, ACTIVE_LOW, -1, "cs35l51_spk_rst"},
 		};
 		lb_add_gpios(gpios, cs35l51_gpios, ARRAY_SIZE(cs35l51_gpios));
 	}

From 3e0457e087ec38aeb3ba18b2704e1c5abe502f4b Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Micha=C5=82=20=C5=BBygowski?= <michal.zygowski@3mdeb.com>
Date: Tue, 9 Sep 2025 10:20:58 +0200
Subject: [PATCH 2217/3886] security/vboot/Makefile.mk: Fix building vboot lib
 with OpenSIL
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

When the board uses OpenSIL, the OpenSIL include paths already include
the $(top). Vboot patches the paths so that all of them include $(top)
at the beginning. This however would result in the include paths from
OpenSIL to include $(top) twice. Filter the paths that already contain
the $(top) and strip the prefix. Then add the $(top) prefix again to
all include paths to fix the problem.

TEST=Build vboot lib selected by enabled measured boot on Gigabyte MZ33-AR1.

Change-Id: Id67ea760f7b1ee2212f19a875c905771cdecdfa5
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89114
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/security/vboot/Makefile.mk | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/src/security/vboot/Makefile.mk b/src/security/vboot/Makefile.mk
index e9b3eb69f1..eb75975d04 100644
--- a/src/security/vboot/Makefile.mk
+++ b/src/security/vboot/Makefile.mk
@@ -9,8 +9,9 @@ ramstage-y += vboot_lib.c
 postcar-y += vboot_lib.c
 
 vboot-fixup-includes = $(patsubst -I%,-I$(top)/%,\
+		       $(patsubst -I$(top)/%,-I%,\
 		       $(patsubst $(src)/%.h,$(top)/$(src)/%.h,\
-		       $(filter-out -I$(obj),$(1))))
+		       $(filter-out -I$(obj),$(1)))))
 
 # call with $1 = stage name to create rules for building the library
 # for the stage and adding it to the stage's set of object files.

From 9e4a0a60264c82d51bf8de450b7d9ac4ec7fcad5 Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Wed, 8 Oct 2025 14:02:51 +0100
Subject: [PATCH 2218/3886] mb/starlabs/starbook/mtl: Don't configure eSPI
 GPIOs

Now that the PinMux is configured correctly, these no longer
need to be set, as they're configured automatically on reset.

Change-Id: I03c6431f6ce7118444ef3672de32c5afa2e36441
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89514
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
---
 .../starlabs/starbook/variants/mtl/gpio.c          | 14 +++++++-------
 1 file changed, 7 insertions(+), 7 deletions(-)

diff --git a/src/mainboard/starlabs/starbook/variants/mtl/gpio.c b/src/mainboard/starlabs/starbook/variants/mtl/gpio.c
index 435840cf8e..6b05026e1b 100644
--- a/src/mainboard/starlabs/starbook/variants/mtl/gpio.c
+++ b/src/mainboard/starlabs/starbook/variants/mtl/gpio.c
@@ -30,13 +30,13 @@ const struct pad_config gpio_table[] = {
 	PAD_CFG_NF(GPP_V08, NONE, DEEP, NF1),				/* Bluetooth Suspend */
 
 	/* eSPI */
-	PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_A00, UP_20K, DEEP, NF1),	/* eSPI IO 0 */
-	PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_A01, UP_20K, DEEP, NF1),	/* eSPI IO 1 */
-	PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_A02, UP_20K, DEEP, NF1),	/* eSPI IO 2 */
-	PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_A03, UP_20K, DEEP, NF1),	/* eSPI IO 3 */
-	PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_A04, UP_20K, DEEP, NF1),	/* eSPI CS 0 */
-	PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_A05, UP_20K, DEEP, NF1),	/* eSPI Clk */
-	PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_A06, NONE, DEEP, NF1),		/* eSPI Reset */
+	// PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_A00, UP_20K, DEEP, NF1),	/* eSPI IO 0 */
+	// PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_A01, UP_20K, DEEP, NF1),	/* eSPI IO 1 */
+	// PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_A02, UP_20K, DEEP, NF1),	/* eSPI IO 2 */
+	// PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_A03, UP_20K, DEEP, NF1),	/* eSPI IO 3 */
+	// PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_A04, UP_20K, DEEP, NF1),	/* eSPI CS 0 */
+	// PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_A05, UP_20K, DEEP, NF1),	/* eSPI Clk */
+	// PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_A06, NONE, DEEP, NF1),	/* eSPI Reset */
 
 	/* Touchpad */
 	PAD_CFG_NF(GPP_H19, NONE, DEEP, NF1),				/* Data */

From 0c97aed8acbaea97feab865f2634cc87cefc043f Mon Sep 17 00:00:00 2001
From: Hualin Wei <weihualin@huaqin.corp-partner.google.com>
Date: Tue, 30 Sep 2025 17:15:54 +0800
Subject: [PATCH 2219/3886] mb/google/fatcat/var/lapis: Modify touchpad and
 touchpanel configuration

When configuring the touch_thc_i2c controlled touchpad and touchscreen
for the first time, referring to the fatcat code. The touchpad and
touchscreen could not be successfully bringup, since the touchpad and
touchscreen configured in the code are opposite to those in the fatcat
schematic diagram. According to the circuit schematic
NB7835CAA_SCH_MB_V1_A.pdf, modify the GPIO configuration and devicetree.

1. Configure GPIO as THC-I2C function.
2. Modify devicetree
        touchpad    ==> THC0
        touchpanel  ==> THC1

BUG=b:448030832 b:445817408
TEST=emerge-fatcat coerboot chromeos-bootimage
flash to DUT, touchpad and touchpanel can be found by `getevent`

Change-Id: I6826145f58d437e03683a4459ded3b7657cf616a
Signed-off-by: Hualin Wei <weihualin@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89383
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 .../google/fatcat/variants/lapis/gpio.c       | 26 +++++++++----------
 .../fatcat/variants/lapis/overridetree.cb     | 16 +++++++-----
 2 files changed, 22 insertions(+), 20 deletions(-)

diff --git a/src/mainboard/google/fatcat/variants/lapis/gpio.c b/src/mainboard/google/fatcat/variants/lapis/gpio.c
index aeb554c4a2..92d63a9e90 100644
--- a/src/mainboard/google/fatcat/variants/lapis/gpio.c
+++ b/src/mainboard/google/fatcat/variants/lapis/gpio.c
@@ -220,9 +220,9 @@ static const struct pad_config gpio_table[] = {
 	PAD_NC(GPP_E10, NONE),
 	/* GPP_E11:     EN_TCHSCR_PWR ==> TOUCH_ENABLE */
 	PAD_CFG_GPO(GPP_E11, 1, PLTRST),
-	/* GPP_E12:     SOC_I2C_TCHPAD_SCL ==> THC_I2C0_SCL_TOUCH_EDP */
+	/* GPP_E12:     SOC_I2C_TCHPAD_SCL ==> THC_I2C1_SCL_TOUCH_EDP */
 	PAD_CFG_NF(GPP_E12, NONE, DEEP, NF1),
-	/* GPP_E13:     SOC_I2C_TCHPAD_SDA ==> THC_I2C0_SDA_TOUCH_EDP*/
+	/* GPP_E13:     SOC_I2C_TCHPAD_SDA ==> THC_I2C1_SDA_TOUCH_EDP*/
 	PAD_CFG_NF(GPP_E13, NONE, DEEP, NF1),
 	/* GPP_E14:     Not used */
 	PAD_NC(GPP_E14, NONE),
@@ -230,10 +230,10 @@ static const struct pad_config gpio_table[] = {
 	PAD_NC(GPP_E15, NONE),
 	/* GPP_E16:     Not used */
 	PAD_NC(GPP_E16, NONE),
-	/* GPP_E17:     Not used ==> TOUCHPAD_INTR */
-	PAD_CFG_GPI_APIC(GPP_E17, NONE, PLTRST, LEVEL, NONE),
-	/* GPP_E18:     TCHPAD_INT_ODL_LS ==> Not used */
-	PAD_NC(GPP_E18, NONE),
+	/* GPP_E17:     Not used  */
+	PAD_NC(GPP_E17, NONE),
+	/* GPP_E18:     TCHPAD_INT_ODL_LS */
+	PAD_CFG_NF(GPP_E18, NONE, DEEP, NF3),
 	/* GPP_E20:     Not used ==> PANEL_ID1 */
 	PAD_NC(GPP_E20, NONE),
 	/* GPP_E21:     PMC_I2C_PD_INT_ODL ==> PD_SMB1_INT# */
@@ -263,18 +263,18 @@ static const struct pad_config gpio_table[] = {
 	PAD_NC(GPP_F06, NONE),
 	/* GPP_F07:     Not used */
 	PAD_NC(GPP_F07, NONE),
-	/* GPP_F08:     Not used */
-	PAD_NC(GPP_F08, NONE),
+	/* GPP_F08:     TCHSCR_PWR_EN */
+	PAD_CFG_GPO(GPP_F08, 1, DEEP),
 	/* GPP_F09:     NC */
 	PAD_NC(GPP_F09, NONE),
 	/* GPP_F10:     NC */
 	PAD_NC(GPP_F10, NONE),
 	/* GPP_F11:     NC */
 	PAD_NC(GPP_F11, NONE),
-	/* GPP_F12:     THC_I2C1_SCL_TCH_PAD */
-	PAD_CFG_NF(GPP_F12, NONE, DEEP, NF8),
-	/* GPP_F13:     THC_I2C1_SDA_TCH_PAD */
-	PAD_CFG_NF(GPP_F13, NONE, DEEP, NF8),
+	/* GPP_F12:     THC_I2C0_SCL_TCH_PAD */
+	PAD_CFG_NF(GPP_F12, NONE, DEEP, NF1),
+	/* GPP_F13:     THC_I2C0_SDA_TCH_PAD */
+	PAD_CFG_NF(GPP_F13, NONE, DEEP, NF1),
 	/* GPP_F14:     NC */
 	PAD_NC(GPP_F14, NONE),
 	/* GPP_F15:     NC */
@@ -285,7 +285,7 @@ static const struct pad_config gpio_table[] = {
 	/* GPP_F17:     CODEC_INT_N ==> NC */
 	PAD_NC(GPP_F17, NONE),
 	/* GPP_F18:     SOC_TCHSCR_INT */
-	PAD_CFG_GPI_APIC(GPP_F18, NONE, PLTRST, LEVEL, INVERT),
+	PAD_CFG_NF(GPP_F18, NONE, DEEP, NF3),
 	/* GPP_F19:     NC */
 	PAD_NC(GPP_F19, NONE),
 	/* GPP_F20:     NC */
diff --git a/src/mainboard/google/fatcat/variants/lapis/overridetree.cb b/src/mainboard/google/fatcat/variants/lapis/overridetree.cb
index 4d40ef9f7a..f206e272ab 100644
--- a/src/mainboard/google/fatcat/variants/lapis/overridetree.cb
+++ b/src/mainboard/google/fatcat/variants/lapis/overridetree.cb
@@ -406,11 +406,8 @@ chip soc/intel/pantherlake
 			chip drivers/intel/touch
 				register "name" = "INTEL_THC0_NAME"
 				register "mode" = "THC_HID_I2C_MODE"
-				register "dev_hidi2c.hid" = ""RAYD0001""
-				register "dev_hidi2c.cid" = ""PNP0C50""
-				register "dev_hidi2c.intf.hidi2c.addr" = "0x39"
-				register "dev_hidi2c.intf.hidi2c.descriptor_address" = "0x1"
-				register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E11)"
+				register "dev_hidi2c.intf.hidi2c.addr" = "0x15"
+				register "dev_hidi2c.intf.hidi2c.descriptor_address" = "0x01"
 				register "wake_on_touch" = "true"
 				# NOTE: Use GpioInt() in _CRS and does not use GPE.
 				register "wake_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW_WAKE(GPP_VGPIO3_THC0)"
@@ -420,12 +417,17 @@ chip soc/intel/pantherlake
 				register "add_acpi_dma_property" = "true"
 				device generic 0 on end
 			end
-		end #Touchpenal
+		end #Touchpad
 		device ref thc1 on
 			register "thc_wake_on_touch[1]" = "true"
 			chip drivers/intel/touch
 				register "name" = "INTEL_THC1_NAME"
 				register "mode" = "THC_HID_I2C_MODE"
+				register "dev_hidi2c.hid" = ""RAYD0001""
+				register "dev_hidi2c.cid" = ""PNP0C50""
+				register "dev_hidi2c.intf.hidi2c.addr" = "0x39"
+				register "dev_hidi2c.intf.hidi2c.descriptor_address" = "0"
+				register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_F08)"
 				register "wake_on_touch" = "true"
 				# NOTE: Use GpioInt() in _CRS and does not use GPE.
 				register "wake_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW_WAKE(GPP_VGPIO3_THC1)"
@@ -435,7 +437,7 @@ chip soc/intel/pantherlake
 				register "add_acpi_dma_property" = "true"
 				device generic 0 on end
 			end
-		end #Touchpad
+		end #Touchpenal
 
 		device ref i2c0 on end
 		device ref i2c3 on

From 55bf4ea07e81ec4e45c364bd7d732f0ba4bb54d2 Mon Sep 17 00:00:00 2001
From: Jeremy Compostella <jeremy.compostella@intel.com>
Date: Wed, 8 Oct 2025 09:04:56 -0700
Subject: [PATCH 2220/3886] cpu/x86/topology: Add tile and die ID CPU topology
 fields

This commit makes the tile and die ID CPU topology parameters
information available to support the implementation of
EFI_MP_SERVICES_PROTOCOL.GetProcessorInfo() in accordance with the
Platform Initialization Specification 1.7.

TEST=Instrumentation shows that the tile_id and die_id apic_path fields
     are properly populated.

Change-Id: If4d473901c8de02b3d6cef44f5481a1864f14d64
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89461
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/cpu/x86/topology.c    | 2 ++
 src/include/device/path.h | 2 ++
 2 files changed, 4 insertions(+)

diff --git a/src/cpu/x86/topology.c b/src/cpu/x86/topology.c
index 70bdf47c4a..eda599e23e 100644
--- a/src/cpu/x86/topology.c
+++ b/src/cpu/x86/topology.c
@@ -118,6 +118,8 @@ void set_cpu_topology(struct device *cpu)
 		{ LEVEL_TYPE_SMT, &cpu->path.apic.thread_id },
 		{ LEVEL_TYPE_CORE, &cpu->path.apic.core_id },
 		{ LEVEL_TYPE_MODULE, &cpu->path.apic.module_id },
+		{ LEVEL_TYPE_TILE, &cpu->path.apic.tile_id },
+		{ LEVEL_TYPE_DIE, &cpu->path.apic.die_id },
 		{ LEVEL_TYPE_PACKAGE, &cpu->path.apic.package_id },
 		{ LEVEL_TYPE_PACKAGE, &cpu->path.apic.node_id }
 	};
diff --git a/src/include/device/path.h b/src/include/device/path.h
index 03aa909d88..9b6e1ef717 100644
--- a/src/include/device/path.h
+++ b/src/include/device/path.h
@@ -82,6 +82,8 @@ struct apic_path {
 	unsigned int core_id;
 	unsigned int thread_id;
 	unsigned int module_id;
+	unsigned int tile_id;
+	unsigned int die_id;
 	/*
 	 * Core identifier within the package, including the die group, die, tile, module, and
 	 * specific core.

From f1708cf21a295f7317567dc5bf65e71c0188dc17 Mon Sep 17 00:00:00 2001
From: Cliff Huang <cliff.huang@intel.com>
Date: Sun, 14 Sep 2025 23:01:22 -0700
Subject: [PATCH 2221/3886] drivers/intel/touch: Enhance Intel touch driver for
 new devices
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Enhancements have been made to the Intel touch driver, including support
for Google touchscreen devices, ELAN9006 and ELAN6918. The update
also includes device-specific configuration changes for both I2C and SPI
interfaces.

Key improvements include:
- Google Touchscreen support integration for ELAN9006 (SPI) and ELAN6918
  (I2C).
- Specification of recommended connection speeds for supported devices.
- Removal of an unnecessary 100ms delay in the SPI _RST method.
- Addition of a function to map the System on Chip's (SoC) I2C speed
  frequency.
- Improved device-specific connection speed settings for both I2C and
  SPI interfaces.

These changes aim to improve the driver’s compatibility and efficiency
when interacting with the newly supported devices.

BUG=none

TEST=Test the updated driver on devices using ELAN9006 and ELAN6918 to
verify improved responsiveness and correct device initialization.
Confirm that connection speeds are set as recommended and check the
absence of the previously unnecessary delay in SPI operations from the
SSDT.

Change-Id: Ie35de90ece44101aea008d13d19e12873cdc09bf
Signed-off-by: Cliff Huang <cliff.huang@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89180
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
---
 src/drivers/intel/touch/chip.h     | 22 ++++++++++++++--
 src/drivers/intel/touch/elan.h     | 29 ++++++++++++++++++++-
 src/drivers/intel/touch/hynitron.h |  3 ++-
 src/drivers/intel/touch/touch.c    | 41 +++++++++++++++++++++++-------
 4 files changed, 82 insertions(+), 13 deletions(-)

diff --git a/src/drivers/intel/touch/chip.h b/src/drivers/intel/touch/chip.h
index e0c78648ba..90bee4a814 100644
--- a/src/drivers/intel/touch/chip.h
+++ b/src/drivers/intel/touch/chip.h
@@ -4,6 +4,8 @@
 #define __DRIVERS_INTEL_TOUCH_CHIP_H__
 
 #include <acpi/acpi_device.h>
+#include <commonlib/bsd/helpers.h>
+#include <device/i2c.h>
 
 #define INTEL_THC0_NAME "THC0"
 #define INTEL_THC1_NAME "THC1"
@@ -13,6 +15,11 @@ struct intel_thc_hidi2c_dev_info {
 	uint64_t addr;
 	/* Used in THC_HID_I2C mode */
 	uint32_t descriptor_address;
+	/*
+	 * connection_speed: Indicates a recommended speed for this device;
+	 * Otherwise, if not specified, use the speed setting from the platform.
+	 */
+	enum i2c_speed connection_speed;
 };
 
 struct intel_thc_hidspi_dev_info {
@@ -31,6 +38,11 @@ struct intel_thc_hidspi_dev_info {
 	/* Touch Host Controller HID Over SPI Write Opcode */
 	uint32_t write_opcode;
 
+	/*
+	 * connection_speed: indicates a recommended speed for this device;
+	 * otherwise 0 = use speed setting from the platform. unit = Hz.
+	 */
+	uint64_t connection_speed;
 };
 
 union intel_thc_dev_intf_info {
@@ -48,7 +60,12 @@ struct intel_thc_dev_info {
 
 struct intel_thc_hidi2c_info {
 	/* Device connection speed in Hz */
-	uint64_t connection_speed;
+	enum i2c_speed connection_speed;
+	/*
+	 * This maps SoC specific function for converting speed in Hz to the actual
+	 * value for the configuration register.
+	 */
+	uint64_t (*get_soc_i2c_bus_speed_val_func)(uint32_t speed);
 	/* Device address mode */
 	uint64_t addr_mode;
 	/* Standard Mode (100 kbit/s) Serial Clock Line HIGH Period */
@@ -97,7 +114,7 @@ struct intel_thc_hidspi_info {
 	/*
 	 * Touch Host Controller HID Over SPI Connection Speed
 	 *
-	 * HID Over SPI Connection Speed - SPI Frequency
+	 * HID Over SPI Connection Speed - SPI Frequency; unit = Hz
 	 */
 	uint32_t connection_speed;
 
@@ -158,6 +175,7 @@ enum intel_touch_device {
 	TH_SENSOR_NONE,
 	TH_SENSOR_WACOM,    /* BOM22 for SPI only */
 	TH_SENSOR_ELAN,     /* BOM36 for SPI and BOM37 for I2C */
+	TH_SENSOR_GOOGLE,   /* ELAN9006 for SPI and ELAN6918 for I2C */
 	TH_SENSOR_HYNITRON, /* NYITRON for I2C only  */
 	TH_SENSOR_GENERIC,  /* for device properity thru devicetree */
 	TH_SENSOR_MAX
diff --git a/src/drivers/intel/touch/elan.h b/src/drivers/intel/touch/elan.h
index b1f3ea615d..4f7b2a1ee0 100644
--- a/src/drivers/intel/touch/elan.h
+++ b/src/drivers/intel/touch/elan.h
@@ -16,7 +16,8 @@ static const struct drivers_intel_touch_config elan_touch_config = {
 		.hid				= "ELAN9048",
 		.cid				= "PNP0C50",
 		.intf.hidi2c.addr		= 0x16,
-		.intf.hidi2c.descriptor_address	= 0x1
+		.intf.hidi2c.descriptor_address	= 0x1,
+		.intf.hidi2c.connection_speed	= I2C_SPEED_FAST, /* fast mode */
 	},
 	.dev_hidspi = { /* BOM36 */
 		.hid						= "ELAN904A",
@@ -29,4 +30,30 @@ static const struct drivers_intel_touch_config elan_touch_config = {
 	},
 };
 
+/*
+ * ELAN9006 is used for HID-SPI interface, while ELAN6918 is used for HID-I2C
+ * interface.
+ */
+
+static const struct drivers_intel_touch_config google_touch_config = {
+	.sensor_dev_name = "ELAN Touch Sensor Device",
+	.dev_hidi2c = {	/* Google's I2C-based touch */
+		.hid				= "ELAN6918",
+		.cid				= "PNP0C50",
+		.intf.hidi2c.addr		= 0x10,
+		.intf.hidi2c.descriptor_address	= 0x1,
+		.intf.hidi2c.connection_speed	= I2C_SPEED_FAST, /* fast mode */
+	},
+	.dev_hidspi = { /* Google's SPI-based touch */
+		.hid						= "ELAN9006",
+		.cid						= "PNP0C51",
+		.intf.hidspi.connection_speed			= (32 * MHz), /* unit: Hz */
+		.intf.hidspi.input_report_header_address	= 0x1000,
+		.intf.hidspi.input_report_body_address		= 0x1100,
+		.intf.hidspi.output_report_address		= 0x2000,
+		.intf.hidspi.read_opcode			= 0xb,
+		.intf.hidspi.write_opcode			= 0x2,
+	},
+};
+
 #endif /* __DRIVERS_TOUCH_DEV_ELAN_H__ */
diff --git a/src/drivers/intel/touch/hynitron.h b/src/drivers/intel/touch/hynitron.h
index 6e34d712f2..9932bbeb65 100644
--- a/src/drivers/intel/touch/hynitron.h
+++ b/src/drivers/intel/touch/hynitron.h
@@ -11,7 +11,8 @@ static const struct drivers_intel_touch_config hynitron_touch_config = {
 		.hid					= "HFW68H",
 		.cid					= "PNP0C50",
 		.intf.hidi2c.addr			= 0x2c,
-		.intf.hidi2c.descriptor_address		=  0x20
+		.intf.hidi2c.descriptor_address		= 0x20,
+		.intf.hidi2c.connection_speed		= I2C_SPEED_FAST, /* fast mode */
 	},
 };
 
diff --git a/src/drivers/intel/touch/touch.c b/src/drivers/intel/touch/touch.c
index d0723d5dce..2310773dd3 100644
--- a/src/drivers/intel/touch/touch.c
+++ b/src/drivers/intel/touch/touch.c
@@ -45,6 +45,7 @@ static const struct drivers_intel_touch_config *get_driver_config(const struct d
 		[TH_SENSOR_NONE] = &none_driver_config,
 		[TH_SENSOR_WACOM] = &wacom_touch_config,
 		[TH_SENSOR_ELAN] = &elan_touch_config,
+		[TH_SENSOR_GOOGLE] = &google_touch_config,
 		[TH_SENSOR_HYNITRON] = &hynitron_touch_config,
 		[TH_SENSOR_GENERIC] = config
 	};
@@ -67,6 +68,16 @@ static const struct drivers_intel_touch_config *get_driver_config(const struct d
 	 (((const struct drivers_intel_touch_config *)(device)->chip_info)->soc_## intf .field) :	\
 	 (_soc_## intf ##_info->field))
 
+/*
+ * Device-tree definition takes precedence over static drivers device-specific over static
+ * drivers SoC-specific definition.
+ */
+#define touch_dev_soc_get(device, interface, field)  \
+	((((const struct drivers_intel_touch_config *)(device)->chip_info)->dev_## interface .intf.interface.field) ? :  \
+	(get_driver_config(device)->dev_## interface .intf.interface.field) ? :  \
+	((((const struct drivers_intel_touch_config *)(device)->chip_info)->soc_## interface .field) ? :  \
+	(_soc_## interface ##_info->field)))
+
 static const char *touch_acpi_name(const struct device *dev)
 {
 	return touch_get(dev, name) ? : INTEL_THC0_NAME;
@@ -104,7 +115,16 @@ static const char *touch_acpi_name(const struct device *dev)
 		acpigen_write_return_ ## type(value);				\
 	}
 
-touch_soc_acpigen(connection_speed, hidspi, integer, "%s: connection speed = %d\n");
+#define touch_dev_soc_acpigen(field, intf, type, fmt)				\
+	static void touch_acpigen_## intf ## _ ## field(void *arg)		\
+	{									\
+		const struct device *dev = (const struct device *)arg;		\
+		uint32_t value = touch_dev_soc_get(dev, intf, field);		\
+		acpigen_write_debug_sprintf(fmt, touch_acpi_name(dev), value);	\
+		acpigen_write_return_ ## type(value);				\
+	}
+
+touch_dev_soc_acpigen(connection_speed, hidspi, integer, "%s: connection speed = %d\n");
 touch_soc_acpigen(limit_packet_size, hidspi, integer, "%s: limit packet size = %d\n");
 touch_soc_acpigen(performance_limit, hidspi, integer, "%s: performance limit = %d\n");
 
@@ -212,11 +232,12 @@ static void touch_generate_acpi_crs(const struct drivers_intel_touch_config *con
 static void touch_generate_acpi_i2cdev_dsd(const struct device *dev)
 {
 	int dsd_pkg_cnt;
+	uint64_t connection_speed_val;
 
 	acpigen_write_name("ICRS");
 	acpigen_emit_byte(BUFFER_OP);
 	acpigen_write_len_f();
-	acpigen_write_integer(12);
+	acpigen_write_integer(12); /* total size of ICRS + 1 */
 	acpigen_pop_len(); /* Name */
 	acpigen_write_create_buffer_word_field("ICRS", 0x00, "DADR");
 	acpigen_write_create_buffer_qword_field("ICRS", 0x02, "DSPD");
@@ -225,7 +246,7 @@ static void touch_generate_acpi_i2cdev_dsd(const struct device *dev)
 	acpigen_write_name("ISUB");
 	acpigen_emit_byte(BUFFER_OP);
 	acpigen_write_len_f();
-	acpigen_write_integer(145);
+	acpigen_write_integer(145); /* total size of ISUB + 1 */
 	acpigen_pop_len();
 	acpigen_write_create_buffer_qword_field("ISUB", 0x00, "SMHX");
 	acpigen_write_create_buffer_qword_field("ISUB", 0x08, "SMLX");
@@ -247,7 +268,9 @@ static void touch_generate_acpi_i2cdev_dsd(const struct device *dev)
 	acpigen_write_create_buffer_qword_field("ISUB", 0x88, "HMSL");
 
 	acpigen_write_store_int_to_namestr(touch_get(dev, dev_hidi2c.intf.hidi2c.addr), "DADR");
-	acpigen_write_store_int_to_namestr(touch_soc_get(dev, hidi2c, connection_speed), "DSPD");
+	connection_speed_val = _soc_hidi2c_info->get_soc_i2c_bus_speed_val_func(
+		touch_dev_soc_get(dev, hidi2c, connection_speed));
+	acpigen_write_store_int_to_namestr(connection_speed_val, "DSPD");
 	acpigen_write_store_int_to_namestr(touch_soc_get(dev, hidi2c, addr_mode), "DADM");
 	acpigen_write_store_int_to_namestr(touch_soc_get(dev, hidi2c, sm_scl_high_period), "SMHX");
 	acpigen_write_store_int_to_namestr(touch_soc_get(dev, hidi2c, sm_scl_low_period), "SMLX");
@@ -451,7 +474,6 @@ static void touch_generate_acpi_spidev_rst(const struct drivers_intel_touch_conf
 			acpigen_write_sleep(touch_soc_get(dev, hidspi, reset_sequencing_delay));
 			/* De-assert RESET# GPIO. */
 			acpigen_disable_tx_gpio(&config->soc_hidspi.reset_gpio);
-			acpigen_write_sleep(100); /* Note: use 100 for now */
 			acpigen_write_release(TOUCH_MUTEX);
 		} else
 			acpigen_write_debug_sprintf("%s: _RST() empty method\n",
@@ -510,10 +532,11 @@ static void touch_dev_fill_ssdt_generator(const struct device *dev)
 			touch_generate_acpi_ini(dev);
 			touch_generate_acpi_dsm(config, dev);
 			/* When only THC1 is used, both THC0/1 need to be enabled since THC0's
-			   device function is '0'. In this case, THC0 should set
-			   connected_device to TH_SENSOR_NONE so that when the driver detects
-			   THC0, the _DSM will be available for it to check and exit without
-			   error. */
+			 * device function is '0'. In this case, THC0 should set
+			 * connected_device to TH_SENSOR_NONE so that when the driver detects
+			 * THC0, the _DSM will be available for it to check and exit without
+			 * error.
+			 */
 			if (config->connected_device == TH_SENSOR_NONE)
 				return;
 

From 7ebcd6763f6bec9bb8b3af3383b50b309f353453 Mon Sep 17 00:00:00 2001
From: Kapil Porwal <kapilporwal@google.com>
Date: Thu, 9 Oct 2025 11:29:15 +0530
Subject: [PATCH 2222/3886] soc/qualcomm/x1p42100: Handle Type-C polarity for
 USB4/DP PHY init

This commit introduces necessary changes to correctly initialize the
Qualcomm X1p42100 USB4/DP PHY based on the USB Type-C CC polarity
detection.

When a Type-C cable is connected, the CC lines determine the
connector orientation (polarity). The USB PHY lanes must be swapped
accordingly to ensure the SuperSpeed signals are routed correctly.

Key changes:
- Adds 'get_usb_typec_polarity()' to read the CC polarity state from
the PMIC (SMB1/SMB2) via the 'SCHG_TYPE_C_MISC_STATUS' register.
- Extends 'qmp_usb4_dp_phy_ss_init()' to accept a 'polarity_inverse'
boolean.
- Uses the polarity state to set the 'SW_PORTSELECT' register in the
USB4/DP common configuration, effectively swapping the lanes when
needed.
- Calls the updated PHY initialization function with the appropriate
polarity for both primary (SS0) and secondary (SS1) USB instances.

This ensures robust USB functionality regardless of the cable insertion
orientation.

BUG=b:448107633
TEST=Verify USB-C works in both polarities on Google/Quenbi.

Without this CL -
USB3 key doesn't work in inverted polarity.

With this CL -
USB3 key works in both polarities.

Change-Id: I1855a12e32a76032d4c1b57770143c152b806008
Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89468
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
---
 .../x1p42100/include/soc/usb/qmp_usb_phy.h     |  2 +-
 .../qualcomm/x1p42100/include/soc/usb/usb.h    |  1 +
 .../qualcomm/x1p42100/usb/qmpv4_usb4_dp_phy.c  |  8 ++++++--
 src/soc/qualcomm/x1p42100/usb/usb.c            | 18 ++++++++++++++++--
 4 files changed, 24 insertions(+), 5 deletions(-)

diff --git a/src/soc/qualcomm/x1p42100/include/soc/usb/qmp_usb_phy.h b/src/soc/qualcomm/x1p42100/include/soc/usb/qmp_usb_phy.h
index 6a5069844f..220f155fe2 100644
--- a/src/soc/qualcomm/x1p42100/include/soc/usb/qmp_usb_phy.h
+++ b/src/soc/qualcomm/x1p42100/include/soc/usb/qmp_usb_phy.h
@@ -50,4 +50,4 @@ struct ss_usb_phy_reg {
 bool ss_qmp_phy_init(u32 phy_idx);
 
 /* Initialize SS0/SS1 QMP PHY - pass 0 for SS0, 1 for SS1 */
-enum cb_err qmp_usb4_dp_phy_ss_init(int phy_instance);
+enum cb_err qmp_usb4_dp_phy_ss_init(int phy_instance, bool polarity_inverse);
diff --git a/src/soc/qualcomm/x1p42100/include/soc/usb/usb.h b/src/soc/qualcomm/x1p42100/include/soc/usb/usb.h
index 360e319939..4ac6dad763 100644
--- a/src/soc/qualcomm/x1p42100/include/soc/usb/usb.h
+++ b/src/soc/qualcomm/x1p42100/include/soc/usb/usb.h
@@ -124,6 +124,7 @@
 #define SCHG_TYPE_C_TYPE_C_SRC_STATUS 0x2B08
 #define SCHG_TYPE_C_TYPE_C_MODE_CFG 0x2B44
 #define TYPEC_VBUS_STATUS_MASK BIT(5)
+#define CCOUT_INVERT_POLARITY 0x03
 
 /* Forward declaration */
 struct dwc3_controller_config;
diff --git a/src/soc/qualcomm/x1p42100/usb/qmpv4_usb4_dp_phy.c b/src/soc/qualcomm/x1p42100/usb/qmpv4_usb4_dp_phy.c
index 6da080be6e..9a500b8e29 100644
--- a/src/soc/qualcomm/x1p42100/usb/qmpv4_usb4_dp_phy.c
+++ b/src/soc/qualcomm/x1p42100/usb/qmpv4_usb4_dp_phy.c
@@ -538,8 +538,9 @@ static void qcom_qmp_phy_configure(void *base_addr, const qmp_phy_init_tbl_t tbl
 }
 
 /* SS QMP PHY initialization function - supports both SS0 and SS1 */
-enum cb_err qmp_usb4_dp_phy_ss_init(int phy_instance)
+enum cb_err qmp_usb4_dp_phy_ss_init(int phy_instance, bool polarity_inverse)
 {
+	unsigned int lane_num = 0;
 	if (phy_instance < 0 || phy_instance >= ARRAY_SIZE(qmp_phy_ss_instance)) {
 		printk(BIOS_ERR, "Invalid PHY instance %d\n", phy_instance);
 		return CB_ERR;
@@ -553,10 +554,13 @@ enum cb_err qmp_usb4_dp_phy_ss_init(int phy_instance)
 	/* Configure TYPEC_CTRL register for lane selection */
 	struct usb43dp_com_reg_layout *current_com_reg = (struct usb43dp_com_reg_layout *)ss_phy_reg->com_base;
 
+	/* Swap lanes based on polarity */
+	if (polarity_inverse)
+		lane_num = 1;
 	/* Configure SW_PORTSELECT and SW_PORTSELECT_MUX using coreboot style */
 	clrsetbits32(&current_com_reg->typec_ctrl,
 				SW_PORTSELECT_MASK | SW_PORTSELECT_MUX_MASK,
-				(0 << SW_PORTSELECT_SHIFT) | SW_PORTSELECT_MUX_MASK);
+				(lane_num << SW_PORTSELECT_SHIFT) | SW_PORTSELECT_MUX_MASK);
 
 	/* Step 1: COM registers */
 	qcom_qmp_phy_configure(ss_phy_reg->com_base,
diff --git a/src/soc/qualcomm/x1p42100/usb/usb.c b/src/soc/qualcomm/x1p42100/usb/usb.c
index 5916bcef81..9e91391d06 100644
--- a/src/soc/qualcomm/x1p42100/usb/usb.c
+++ b/src/soc/qualcomm/x1p42100/usb/usb.c
@@ -444,6 +444,20 @@ static const struct dwc3_controller_config sec_config = {
 	.smb_slave_addr = SMB2_SLAVE_ID,
 };
 
+/*
+ * get_usb_typec_polarity - Reads Type-C polarity from PMIC
+ * @config: Controller configuration containing SMB slave address
+ *
+ * @return TRUE if polarify is inverse
+ * @return FALSE if polarify is normal
+ */
+static bool get_usb_typec_polarity(const struct dwc3_controller_config *config)
+{
+	u8 slave = config->smb_slave_addr;
+	u8 misc_status = spmi_read8(SPMI_ADDR(slave, SCHG_TYPE_C_TYPE_C_MISC_STATUS));
+	return (misc_status & CCOUT_INVERT_POLARITY) == CCOUT_INVERT_POLARITY;
+}
+
 /* Initialization of DWC3 Core and PHY */
 static void setup_usb_host(struct usb_dwc3_cfg *dwc3)
 {
@@ -530,7 +544,7 @@ static void setup_usb_host(struct usb_dwc3_cfg *dwc3)
 	clock_reset_bcr(dwc3->gcc_usb4_0_dp0_phy_prim_bcr, 0);
 	udelay(10);
 	/* Initialize USB4/USB3 EDP_DP_Con PHY Configuration */
-	int ss0_ret = qmp_usb4_dp_phy_ss_init(0);
+	int ss0_ret = qmp_usb4_dp_phy_ss_init(0, get_usb_typec_polarity(&prim_config));
 	if (ss0_ret != CB_SUCCESS) {
 		printk(BIOS_ERR, "SS0 QMP PHY initialization failed\n");
 		high_speed_only_primary = true;
@@ -559,7 +573,7 @@ static void setup_usb_host(struct usb_dwc3_cfg *dwc3)
 	clock_reset_bcr(dwc3->gcc_usb4_1_dp0_phy_sec_bcr, 0);
 	udelay(10);
 	/* Initialize USB4/USB3 EDP_DP_Con PHY Configuration (secondary) */
-	int ss1_ret = qmp_usb4_dp_phy_ss_init(1);
+	int ss1_ret = qmp_usb4_dp_phy_ss_init(1, get_usb_typec_polarity(&sec_config));
 	if (ss1_ret != CB_SUCCESS) {
 		printk(BIOS_ERR, "SS1 QMP PHY initialization failed\n");
 		high_speed_only_secondary = true;

From 990ad929a08fb8ba94c69a062b2bfb9342faa9d8 Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Sat, 11 Oct 2025 19:31:35 +0100
Subject: [PATCH 2223/3886] mb/starlabs/starbook/tgl: Don't configure eSPI
 GPIOs

These do not need to be configured, as they're configured
automatically on reset.

Change-Id: I26c9a42fa44b55208583859895f9a39016e76eac
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89523
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 .../starlabs/starbook/variants/tgl/gpio.c          | 14 +++++++-------
 1 file changed, 7 insertions(+), 7 deletions(-)

diff --git a/src/mainboard/starlabs/starbook/variants/tgl/gpio.c b/src/mainboard/starlabs/starbook/variants/tgl/gpio.c
index f36b9a3ba3..45ebd3d9b1 100644
--- a/src/mainboard/starlabs/starbook/variants/tgl/gpio.c
+++ b/src/mainboard/starlabs/starbook/variants/tgl/gpio.c
@@ -26,13 +26,13 @@ const struct pad_config gpio_table[] = {
 	PAD_CFG_NF(GPD8, NONE, DEEP, NF1),				/* Bluetooth Suspend */
 
 	/* eSPI */
-	PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_A0, UP_20K, DEEP, NF1),		/* eSPI IO 0 */
-	PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_A1, UP_20K, DEEP, NF1),		/* eSPI IO 1 */
-	PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_A2, UP_20K, DEEP, NF1),		/* eSPI IO 2 */
-	PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_A3, UP_20K, DEEP, NF1),		/* eSPI IO 3 */
-	PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_A4, UP_20K, DEEP, NF1),		/* eSPI CS 0 */
-	PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_A5, UP_20K, DEEP, NF1),		/* eSPI Clk */
-	PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_A6, NONE, DEEP, NF1),		/* eSPI Reset */
+	// PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_A0, UP_20K, DEEP, NF1),	/* eSPI IO 0 */
+	// PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_A1, UP_20K, DEEP, NF1),	/* eSPI IO 1 */
+	// PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_A2, UP_20K, DEEP, NF1),	/* eSPI IO 2 */
+	// PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_A3, UP_20K, DEEP, NF1),	/* eSPI IO 3 */
+	// PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_A4, UP_20K, DEEP, NF1),	/* eSPI CS 0 */
+	// PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_A5, UP_20K, DEEP, NF1),	/* eSPI Clk */
+	// PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_A6, NONE, DEEP, NF1),	/* eSPI Reset */
 
 	/* Touchpad */
 	PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1),				/* Data */

From db0faffdb8667bf7a81a224a8bc5a78f8a35f1ac Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Sat, 11 Oct 2025 19:35:17 +0100
Subject: [PATCH 2224/3886] mb/starlabs/*: Add comment about not configuring
 eSPI GPIOs

Change-Id: If733599ff699ffa31db95384857540694050d6bd
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89524
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/starlabs/byte_adl/variants/mk_ii/gpio.c    | 2 +-
 src/mainboard/starlabs/starbook/variants/adl/gpio.c      | 2 +-
 src/mainboard/starlabs/starbook/variants/adl_n/gpio.c    | 2 +-
 src/mainboard/starlabs/starbook/variants/mtl/gpio.c      | 2 +-
 src/mainboard/starlabs/starbook/variants/rpl/gpio.c      | 2 +-
 src/mainboard/starlabs/starbook/variants/tgl/gpio.c      | 2 +-
 src/mainboard/starlabs/starfighter/variants/rpl/gpio.c   | 2 +-
 src/mainboard/starlabs/starlite_adl/variants/mk_v/gpio.c | 2 +-
 8 files changed, 8 insertions(+), 8 deletions(-)

diff --git a/src/mainboard/starlabs/byte_adl/variants/mk_ii/gpio.c b/src/mainboard/starlabs/byte_adl/variants/mk_ii/gpio.c
index 01a4d5dcd0..28dd5486de 100644
--- a/src/mainboard/starlabs/byte_adl/variants/mk_ii/gpio.c
+++ b/src/mainboard/starlabs/byte_adl/variants/mk_ii/gpio.c
@@ -25,7 +25,7 @@ const struct pad_config gpio_table[] = {
 	PAD_CFG_NF(GPD5, NONE, DEEP, NF1),				/* Sleep S4 */
 	PAD_CFG_NF(GPD8, NONE, DEEP, NF1),				/* Bluetooth Suspend */
 
-	/* eSPI */
+	/* eSPI - Configure automatically on reset */
 	// PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_A0, UP_20K, DEEP, NF1),	/* eSPI IO 0 */
 	// PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_A1, UP_20K, DEEP, NF1),	/* eSPI IO 1 */
 	// PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_A2, UP_20K, DEEP, NF1),	/* eSPI IO 2 */
diff --git a/src/mainboard/starlabs/starbook/variants/adl/gpio.c b/src/mainboard/starlabs/starbook/variants/adl/gpio.c
index 7edf4ce7b9..2a90e4c103 100644
--- a/src/mainboard/starlabs/starbook/variants/adl/gpio.c
+++ b/src/mainboard/starlabs/starbook/variants/adl/gpio.c
@@ -25,7 +25,7 @@ const struct pad_config gpio_table[] = {
 	PAD_CFG_NF(GPD5, NONE, DEEP, NF1),				/* Sleep S4 */
 	PAD_CFG_NF(GPD8, NONE, DEEP, NF1),				/* Bluetooth Suspend */
 
-	/* eSPI */
+	/* eSPI - Configure automatically on reset */
 	// PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_A0, UP_20K, DEEP, NF1),	/* eSPI IO 0 */
 	// PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_A1, UP_20K, DEEP, NF1),	/* eSPI IO 1 */
 	// PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_A2, UP_20K, DEEP, NF1),	/* eSPI IO 2 */
diff --git a/src/mainboard/starlabs/starbook/variants/adl_n/gpio.c b/src/mainboard/starlabs/starbook/variants/adl_n/gpio.c
index fb82f3edf3..fc44208bac 100644
--- a/src/mainboard/starlabs/starbook/variants/adl_n/gpio.c
+++ b/src/mainboard/starlabs/starbook/variants/adl_n/gpio.c
@@ -25,7 +25,7 @@ const struct pad_config gpio_table[] = {
 	PAD_CFG_NF(GPD5, NONE, DEEP, NF1),				/* Sleep S4 */
 	PAD_CFG_NF(GPD8, NONE, DEEP, NF1),				/* Bluetooth Suspend */
 
-	/* eSPI */
+	/* eSPI - Configure automatically on reset */
 	// PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_A0, UP_20K, DEEP, NF1),	/* eSPI IO 0 */
 	// PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_A1, UP_20K, DEEP, NF1),	/* eSPI IO 1 */
 	// PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_A2, UP_20K, DEEP, NF1),	/* eSPI IO 2 */
diff --git a/src/mainboard/starlabs/starbook/variants/mtl/gpio.c b/src/mainboard/starlabs/starbook/variants/mtl/gpio.c
index 6b05026e1b..9f920dfcd5 100644
--- a/src/mainboard/starlabs/starbook/variants/mtl/gpio.c
+++ b/src/mainboard/starlabs/starbook/variants/mtl/gpio.c
@@ -29,7 +29,7 @@ const struct pad_config gpio_table[] = {
 	PAD_CFG_NF(GPP_V05, NONE, DEEP, NF1),				/* Sleep S4 */
 	PAD_CFG_NF(GPP_V08, NONE, DEEP, NF1),				/* Bluetooth Suspend */
 
-	/* eSPI */
+	/* eSPI - Configure automatically on reset */
 	// PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_A00, UP_20K, DEEP, NF1),	/* eSPI IO 0 */
 	// PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_A01, UP_20K, DEEP, NF1),	/* eSPI IO 1 */
 	// PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_A02, UP_20K, DEEP, NF1),	/* eSPI IO 2 */
diff --git a/src/mainboard/starlabs/starbook/variants/rpl/gpio.c b/src/mainboard/starlabs/starbook/variants/rpl/gpio.c
index 2fd683a8eb..bfcd0769c0 100644
--- a/src/mainboard/starlabs/starbook/variants/rpl/gpio.c
+++ b/src/mainboard/starlabs/starbook/variants/rpl/gpio.c
@@ -25,7 +25,7 @@ const struct pad_config gpio_table[] = {
 	PAD_CFG_NF(GPD5, NONE, DEEP, NF1),				/* Sleep S4 */
 	PAD_CFG_NF(GPD8, NONE, DEEP, NF1),				/* Bluetooth Suspend */
 
-	/* eSPI */
+	/* eSPI - Configure automatically on reset */
 	// PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_A0, UP_20K, DEEP, NF1),	/* eSPI IO 0 */
 	// PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_A1, UP_20K, DEEP, NF1),	/* eSPI IO 1 */
 	// PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_A2, UP_20K, DEEP, NF1),	/* eSPI IO 2 */
diff --git a/src/mainboard/starlabs/starbook/variants/tgl/gpio.c b/src/mainboard/starlabs/starbook/variants/tgl/gpio.c
index 45ebd3d9b1..4d66d40880 100644
--- a/src/mainboard/starlabs/starbook/variants/tgl/gpio.c
+++ b/src/mainboard/starlabs/starbook/variants/tgl/gpio.c
@@ -25,7 +25,7 @@ const struct pad_config gpio_table[] = {
 	PAD_CFG_NF(GPD5, NONE, DEEP, NF1),				/* Sleep S4 */
 	PAD_CFG_NF(GPD8, NONE, DEEP, NF1),				/* Bluetooth Suspend */
 
-	/* eSPI */
+	/* eSPI - Configure automatically on reset */
 	// PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_A0, UP_20K, DEEP, NF1),	/* eSPI IO 0 */
 	// PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_A1, UP_20K, DEEP, NF1),	/* eSPI IO 1 */
 	// PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_A2, UP_20K, DEEP, NF1),	/* eSPI IO 2 */
diff --git a/src/mainboard/starlabs/starfighter/variants/rpl/gpio.c b/src/mainboard/starlabs/starfighter/variants/rpl/gpio.c
index 1b66c49515..d58121e83a 100644
--- a/src/mainboard/starlabs/starfighter/variants/rpl/gpio.c
+++ b/src/mainboard/starlabs/starfighter/variants/rpl/gpio.c
@@ -31,7 +31,7 @@ const struct pad_config gpio_table[] = {
 	PAD_CFG_NF(GPD5, NONE, DEEP, NF1),				/* Sleep S4 */
 	PAD_CFG_NF(GPD8, NONE, DEEP, NF1),				/* Bluetooth Suspend */
 
-	/* eSPI */
+	/* eSPI - Configure automatically on reset */
 	// PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_A0, UP_20K, DEEP, NF1),	/* eSPI IO 0 */
 	// PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_A1, UP_20K, DEEP, NF1),	/* eSPI IO 1 */
 	// PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_A2, UP_20K, DEEP, NF1),	/* eSPI IO 2 */
diff --git a/src/mainboard/starlabs/starlite_adl/variants/mk_v/gpio.c b/src/mainboard/starlabs/starlite_adl/variants/mk_v/gpio.c
index 9cf3a3e2bd..8c1b7cf79f 100644
--- a/src/mainboard/starlabs/starlite_adl/variants/mk_v/gpio.c
+++ b/src/mainboard/starlabs/starlite_adl/variants/mk_v/gpio.c
@@ -25,7 +25,7 @@ const struct pad_config gpio_table[] = {
 	PAD_CFG_NF(GPD5, NONE, DEEP, NF1),				/* Sleep S4 */
 	PAD_CFG_NF(GPD8, NONE, DEEP, NF1),				/* Bluetooth Suspend */
 
-	/* eSPI */
+	/* eSPI - Configure automatically on reset */
 	// PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_A0, UP_20K, DEEP, NF1),	/* eSPI IO 0 */
 	// PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_A1, UP_20K, DEEP, NF1),	/* eSPI IO 1 */
 	// PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_A2, UP_20K, DEEP, NF1),	/* eSPI IO 2 */

From 375847acfe99fac54ee1d38798589ed1df0d286b Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Tue, 7 Oct 2025 15:55:48 +0100
Subject: [PATCH 2225/3886] soc/intel/meteorlake: Configure
 PmcPchLpmS0ixSubStateEnableMask
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Only PmcLpmS0ixSubStateEnableMask is currently configured, and
PmcPchLpmS0ixSubStateEnableMask is left with the default value.

These should be the same.

Change-Id: I71bebec251c5c336407c2c173af29ddbfde0691b
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89448
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
---
 src/soc/intel/meteorlake/fsp_params.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/src/soc/intel/meteorlake/fsp_params.c b/src/soc/intel/meteorlake/fsp_params.c
index 0ad32a3e5e..0502b757c5 100644
--- a/src/soc/intel/meteorlake/fsp_params.c
+++ b/src/soc/intel/meteorlake/fsp_params.c
@@ -659,6 +659,9 @@ static void fill_fsps_misc_power_params(FSP_S_CONFIG *s_cfg,
 	/* Enable the energy efficient turbo mode */
 	s_cfg->EnergyEfficientTurbo = 1;
 	s_cfg->PmcLpmS0ixSubStateEnableMask = get_supported_lpm_mask();
+#if CONFIG(PLATFORM_USES_FSP2_X86_32)
+	s_cfg->PmcPchLpmS0ixSubStateEnableMask = get_supported_lpm_mask();
+#endif
 
 	/* Apply minimum assertion width settings if non-zero */
 	if (config->pch_slp_s3_min_assertion_width)

From 5e64ae2554bf090dfc447c095cf6feeff6ff4ea4 Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Sat, 11 Oct 2025 20:41:47 +0100
Subject: [PATCH 2226/3886] mb/starlabs/starbook/mtl: Enable PCH Energy

ReportingPchPmDisableEnergyReport has been 0 by default in all
FSP versions up until Meteor Lake. Set this to unify the
configuration between boards.

No applicable tests.

Change-Id: If9cdbb466bf8e4efc7a1577b0a1fec6270550d05
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89527
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/starlabs/starbook/variants/mtl/devicetree.cb | 1 +
 1 file changed, 1 insertion(+)

diff --git a/src/mainboard/starlabs/starbook/variants/mtl/devicetree.cb b/src/mainboard/starlabs/starbook/variants/mtl/devicetree.cb
index 2865a3d4b1..f2851ee890 100644
--- a/src/mainboard/starlabs/starbook/variants/mtl/devicetree.cb
+++ b/src/mainboard/starlabs/starbook/variants/mtl/devicetree.cb
@@ -1,6 +1,7 @@
 chip soc/intel/meteorlake
 	# FSP UPDs
 	register "eist_enable"				= "true"
+	register "pch_pm_energy_report_enable"		= "true"
 	register "sagv"					= "SAGV_ENABLED"
 
 	# Serial I/O

From af8b15ae0489d390170ddbb585f049cccc0cb1d9 Mon Sep 17 00:00:00 2001
From: Yu-Ping Wu <yupingso@google.com>
Date: Thu, 9 Oct 2025 07:31:12 +0000
Subject: [PATCH 2227/3886] Revert "libpayload: Define
 UCHAR_MAX/CHAR_MIN/CHAR_MAX"

This reverts commit 4f13f72dbc40 ("libpayload: Define UCHAR_MAX/CHAR_MIN/CHAR_MAX").

Reason for revert: char can be either signed or unsigned. If it's
unsigned, then CHAR_MIN would be incorrectly defined as 128.

Change-Id: Id49ddfff2d91029dc191b8b64e8e3f325ad0a462
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89469
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 payloads/libpayload/include/limits.h | 4 ----
 1 file changed, 4 deletions(-)

diff --git a/payloads/libpayload/include/limits.h b/payloads/libpayload/include/limits.h
index c712b60bfd..53adfcb98c 100644
--- a/payloads/libpayload/include/limits.h
+++ b/payloads/libpayload/include/limits.h
@@ -41,10 +41,6 @@
 
 #define CHAR_BIT	8
 
-#define UCHAR_MAX	((unsigned char)~0U)
-#define CHAR_MIN	((char)(UCHAR_MAX & ~(UCHAR_MAX >> 1)))
-#define CHAR_MAX	((char)(UCHAR_MAX >> 1))
-
 #define USHRT_MAX	((unsigned short int)~0U)
 #define SHRT_MIN	((short int)(USHRT_MAX & ~(USHRT_MAX >> 1)))
 #define SHRT_MAX	((short int)(USHRT_MAX >> 1))

From 3ac1a2b124e482d11f6a75d600d2facbe7d157f5 Mon Sep 17 00:00:00 2001
From: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Date: Fri, 10 Oct 2025 09:09:53 +0900
Subject: [PATCH 2228/3886] MAINTAINERS: Drop non-existant TPM files from VBOOT

The TPM related files were moved into src/security/tpm in commit
64e2d1908263 ("security/tpm: Move tpm TSS and TSPI layer to security
section"), then further work was done on the coreboot TPM stack which
makes it difficult to find the equivalent area of code which these files
correspond to.

Therefore, we will drop these files for now and leave it up to the
maintainers of VBOOT to re-add any TPM related files (if they want to)
in a future change.

Change-Id: Ief7cfb81efc4c3daadc4b73af21bfdf0224b9005
Signed-off-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89509
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
---
 MAINTAINERS | 2 --
 1 file changed, 2 deletions(-)

diff --git a/MAINTAINERS b/MAINTAINERS
index ff6e32b626..7ad94bd567 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1132,8 +1132,6 @@ M:	Yu-Ping Wu <yupingso@google.com>
 S:	Supported
 F:	3rdparty/vboot/
 F:	src/security/vboot/
-F:	src/include/tpm.h
-F:	src/include/tpm_lite/
 
 RESOURCE ALLOCATOR
 F:	src/device/*

From 04affc3354bc7dff5cfd3b0e6ac36a170cdabdcc Mon Sep 17 00:00:00 2001
From: Varun Upadhyay <varun.upadhyay@intel.com>
Date: Mon, 15 Sep 2025 14:32:42 +0530
Subject: [PATCH 2229/3886] mb/google/ocelot: Update gpio's for ALC721 sndw

This commit updates sndw codec fwconfig for including dmic pins
necessary for microphone data.

Schematic version: schematic_1433518
Platform Mapping Document : Rev0p86

TEST=emerge-ocelot coreboot chromeos-bootimage and check microphone
functionality.

Change-Id: I8d271c7f11fa3fcf34105de7552e641c40463090
Signed-off-by: Varun Upadhyay <varun.upadhyay@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89175
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Usha P <usha.p@intel.com>
Reviewed-by: Pranava Y N <pranavayn@google.com>
---
 src/mainboard/google/ocelot/variants/ocelot/fw_config.c | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/src/mainboard/google/ocelot/variants/ocelot/fw_config.c b/src/mainboard/google/ocelot/variants/ocelot/fw_config.c
index 5e9559803b..b299a406f2 100644
--- a/src/mainboard/google/ocelot/variants/ocelot/fw_config.c
+++ b/src/mainboard/google/ocelot/variants/ocelot/fw_config.c
@@ -86,6 +86,10 @@ static const struct pad_config sndw_alc721_enable_pads[] = {
 	PAD_CFG_NF(GPP_S06, NONE, DEEP, NF5),
 	/* GPP_S07:     DMIC1_DATA (HDR) */
 	PAD_CFG_NF(GPP_S07, NONE, DEEP, NF5),
+	/* GPP_D16:	DMIC_CLK */
+	PAD_CFG_NF(GPP_D16, NONE, DEEP, NF3),
+	/* GPP_D17:	DMIC_DATA */
+	PAD_CFG_NF(GPP_D17, NONE, DEEP, NF3),
 };
 
 static const struct pad_config audio_disable_pads[] = {

From 8f24546fc4c0d08462eb16b4dcd7e5bb3a179325 Mon Sep 17 00:00:00 2001
From: Jeremy Compostella <jeremy.compostella@intel.com>
Date: Wed, 24 Sep 2025 09:52:13 -0700
Subject: [PATCH 2230/3886] vc/intel/fsp/fsp2_0/wildcatlake: Expose Thermal
 current thresholds and mode

The changes focus on offering power state current thresholds, Thermal
Design Current (TDC) mode settings, and P-core and E-core hysteresis time
windows to support acoustic noise mitigation.

The Ps1Threshold, Ps2Threshold, and Ps3Threshold new fields configure
current thresholds for different power states. This allows for
fine-tuned power management by specifying current thresholds in 1/4 A
increments. These configurations can help optimize performance based on
specific current requirements for different components like IA, GT, and
SA.

The TdcMode parameter configures TDC mode based on the IRMS supported
bit from Mailbox, offering the option between iPL2 and Irms modes.

BUG=b:449662274

Change-Id: I949dd6a5c6bf575415ee62dcd0d0eda369ef29fc
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89330
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-by: Zhixing Ma <zhixing.ma@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 .../intel/fsp/fsp2_0/wildcatlake/FspmUpd.h    | 113 +++++++++++++-----
 1 file changed, 81 insertions(+), 32 deletions(-)

diff --git a/src/vendorcode/intel/fsp/fsp2_0/wildcatlake/FspmUpd.h b/src/vendorcode/intel/fsp/fsp2_0/wildcatlake/FspmUpd.h
index 1d9868ca13..449a25447a 100644
--- a/src/vendorcode/intel/fsp/fsp2_0/wildcatlake/FspmUpd.h
+++ b/src/vendorcode/intel/fsp/fsp2_0/wildcatlake/FspmUpd.h
@@ -2364,9 +2364,42 @@ typedef struct {
 **/
   UINT16                      DcLoadline[6];
 
-/** Offset 0x0896 - Reserved
+/** Offset 0x0896 - Power State 1 Threshold current
+  PS Current Threshold1, defined in 1/4 A increments. A value of 400 = 100A. Range
+  0-152, which translates to 0-38A. 0 = AUTO. [0] for IA, [1] for GT, [2] for SA,
+  [3] through [5] are Reserved.
 **/
-  UINT8                      Reserved66[116];
+  UINT16                      Ps1Threshold[6];
+
+/** Offset 0x08A2 - Power State 2 Threshold current
+  PS Current Threshold2, defined in 1/4 A increments. A value of 400 = 100A. Range
+  0-48, which translates to 0-12A. 0 = AUTO. [0] for IA, [1] for GT, [2] for SA,
+  [3] through [5] are Reserved.
+**/
+  UINT16                      Ps2Threshold[6];
+
+/** Offset 0x08AE - Power State 3 Threshold current
+  PS Current Threshold3, defined in 1/4 A increments. A value of 400 = 100A. Range
+  0-16, which translates to 0-4A. 0 = AUTO. [0] for IA, [1] for GT, [2] for SA, [3]
+  through [5] are Reserved.
+**/
+  UINT16                      Ps3Threshold[6];
+
+/** Offset 0x08BA - Reserved
+**/
+  UINT8                       Reserved66[26];
+
+/** Offset 0x08D4 - Icc Max limit
+  Voltage Regulator Current Limit (Icc Max). This value represents the Maximum instantaneous
+  current allowed at any given time. The value is represented in 1/4 A increments.
+  A value of 400 = 100A. 0 means AUTO. IA and GT, range 0-2047. SA range 0-1023.
+  [0] for IA, [1] for GT, [2] for SA, [3] through [5] are Reserved.
+**/
+  UINT16                      IccMax[6];
+
+/** Offset 0x08E0 - Reserved
+**/
+  UINT8                      Reserved67[42];
 
 /** Offset 0x090A - Thermal Design Current enable/disable
   Thermal Design Current enable/disable; <b>0: Disable</b>; 1: Enable. [0] for IA,
@@ -2376,7 +2409,7 @@ typedef struct {
 
 /** Offset 0x0910 - Reserved
 **/
-  UINT8                       Reserved67[6];
+  UINT8                       Reserved68[6];
 
 /** Offset 0x0916 - Disable Fast Slew Rate for Deep Package C States for VR domains
   This option needs to be configured to reduce acoustic noise during deeper C states.
@@ -2398,7 +2431,7 @@ typedef struct {
 
 /** Offset 0x0922 - Reserved
 **/
-  UINT8                       Reserved68[6];
+  UINT8                       Reserved69[6];
 
 /** Offset 0x0928 - Thermal Design Current time window
   Auto = 0 is default. Range is from 1ms to 448s. <b>0: Auto</b>. [0] for IA, [1]
@@ -2406,9 +2439,15 @@ typedef struct {
 **/
   UINT32                      TdcTimeWindow[6];
 
-/** Offset 0x0940 - Reserved
+/** Offset 0x0940 - TDC Mode
+  TDC Mode based on IRMS supported bit from Mailbox. <b>0: iPL2</b>; 1: Irms. [0]
+  for IA, [1] for GT, [2] for SA, [3] for atom [4]-[5] are Reserved.
 **/
-  UINT8                       Reserved69[8];
+  UINT8                       TdcMode[6];
+
+/** Offset 0x0946 - Reserved
+**/
+  UINT8                       Reserved70[2];
 
 /** Offset 0x0948 - DLVR RFI Enable
   Enable/Disable DLVR RFI frequency hopping. 0: Disable; <b>1: Enable</b>.
@@ -2416,9 +2455,19 @@ typedef struct {
 **/
   UINT8                       DlvrRfiEnable;
 
-/** Offset 0x0949 - Reserved
+/** Offset 0x0949 - Pcore VR Hysteresis time window
+  0 is default. Range of PcoreHysteresisWindow from 1ms to 50ms.
 **/
-  UINT8                       Reserved70[13];
+  UINT8                       PcoreHysteresisWindow;
+
+/** Offset 0x094A - Ecore VR Hysteresis time window
+  0 is default. Range of EcoreHysteresisWindow from 1ms to 50ms.
+**/
+  UINT8                       EcoreHysteresisWindow;
+
+/** Offset 0x094B - Reserved
+**/
+  UINT8                       Reserved71[11];
 
 /** Offset 0x0956 - VR Fast Vmode ICC Limit support
   Voltage Regulator Fast Vmode ICC Limit. A value of 400 = 100A. A value of 0 corresponds
@@ -2443,7 +2492,7 @@ typedef struct {
 
 /** Offset 0x096E - Reserved
 **/
-  UINT8                       Reserved71[28];
+  UINT8                       Reserved72[28];
 
 /** Offset 0x098A - PCH Port80 Route
   Control where the Port 80h cycles are sent, 0: LPC; 1: PCI.
@@ -2460,7 +2509,7 @@ typedef struct {
 
 /** Offset 0x098C - Reserved
 **/
-  UINT8                       Reserved72[4];
+  UINT8                       Reserved73[4];
 
 /** Offset 0x0990 - PMR Size
   Size of PMR memory buffer. 0x400000 for normal boot and 0x200000 for S3 boot
@@ -2486,7 +2535,7 @@ typedef struct {
 
 /** Offset 0x0997 - Reserved
 **/
-  UINT8                       Reserved73;
+  UINT8                       Reserved74;
 
 /** Offset 0x0998 - Base addresses for VT-d function MMIO access
   Base addresses for VT-d MMIO access per VT-d engine
@@ -2495,7 +2544,7 @@ typedef struct {
 
 /** Offset 0x09BC - Reserved
 **/
-  UINT8                       Reserved74[20];
+  UINT8                       Reserved75[20];
 
 /** Offset 0x09D0 - MMIO Size
   Size of MMIO space reserved for devices. 0(Default)=Auto, non-Zero=size in MB
@@ -2510,7 +2559,7 @@ typedef struct {
 
 /** Offset 0x09D4 - Reserved
 **/
-  UINT8                      Reserved75[36];
+  UINT8                      Reserved76[36];
 
 /** Offset 0x09F8 - Enable above 4GB MMIO resource support
   Enable/disable above 4GB MMIO resource support
@@ -2526,7 +2575,7 @@ typedef struct {
 
 /** Offset 0x09FA - Reserved
 **/
-  UINT8                       Reserved76[10];
+  UINT8                       Reserved77[10];
 
 /** Offset 0x0A04 - Enable/Disable CrashLog Device
   Enable or Disable CrashLog/Telemetry Device  0- Disable, <b>1- Enable</b>
@@ -2536,7 +2585,7 @@ typedef struct {
 
 /** Offset 0x0A08 - Reserved
 **/
-  UINT8                      Reserved77[20];
+  UINT8                      Reserved78[20];
 
 /** Offset 0x0A1C - Platform Debug Option
   Enabled Trace active: TraceHub is enabled and trace is active, blocks s0ix.\n
@@ -2553,7 +2602,7 @@ typedef struct {
 
 /** Offset 0x0A1D - Reserved
 **/
-  UINT8                       Reserved78[14];
+  UINT8                       Reserved79[14];
 
 /** Offset 0x0A2B - Program GPIOs for LFP on DDI port-A device
   0=Disabled,1(Default)=eDP, 2=MIPI DSI
@@ -2563,7 +2612,7 @@ typedef struct {
 
 /** Offset 0x0A2C - Reserved
 **/
-  UINT8                      Reserved79[2];
+  UINT8                      Reserved80[2];
 
 /** Offset 0x0A2E - Program GPIOs for LFP on DDI port-B device
   0(Default)=Disabled,1=eDP, 2=MIPI DSI
@@ -2657,7 +2706,7 @@ typedef struct {
 
 /** Offset 0x0A3D - Reserved
 **/
-  UINT8                       Reserved80[3];
+  UINT8                       Reserved81[3];
 
 /** Offset 0x0A40 - Temporary MMIO address for GMADR
   The reference code will use this as Temporary MMIO address space to access GMADR
@@ -2676,7 +2725,7 @@ typedef struct {
 
 /** Offset 0x0A50 - Reserved
 **/
-  UINT8                      Reserved81[2];
+  UINT8                      Reserved82[2];
 
 /** Offset 0x0A52 - Enable/Disable Memory Bandwidth Compression
   0=Disable, 1(Default)=Enable
@@ -2706,7 +2755,7 @@ typedef struct {
 
 /** Offset 0x0A56 - Reserved
 **/
-  UINT8                       Reserved82[2];
+  UINT8                       Reserved83[2];
 
 /** Offset 0x0A58 - Intel Graphics VBT (Video BIOS Table) Size
   Size of Internal Graphics VBT Image
@@ -2715,7 +2764,7 @@ typedef struct {
 
 /** Offset 0x0A5C - Reserved
 **/
-  UINT8                       Reserved83[4];
+  UINT8                       Reserved84[4];
 
 /** Offset 0x0A60 - Graphics Configuration Ptr
   Points to VBT
@@ -2743,7 +2792,7 @@ typedef struct {
 
 /** Offset 0x0A72 - Reserved
 **/
-  UINT8                      Reserved84[16];
+  UINT8                      Reserved85[16];
 
 /** Offset 0x0A82 - TCSS USB HOST (xHCI) Enable
   Set TCSS XHCI. 0:Disabled  1:Enabled - Must be enabled if xDCI is enabled below
@@ -2753,7 +2802,7 @@ typedef struct {
 
 /** Offset 0x0A83 - Reserved
 **/
-  UINT8                       Reserved85[4];
+  UINT8                       Reserved86[4];
 
 /** Offset 0x0A87 - TCSS Type C Port 0
   Set TCSS Type C Port 0 Type, Options are 0=DISABLE, 1=DP_ONLY, 2=NO_TBT, 3=NO_PCIE,
@@ -2785,7 +2834,7 @@ typedef struct {
 
 /** Offset 0x0A8B - Reserved
 **/
-  UINT8                       Reserved86;
+  UINT8                       Reserved87;
 
 /** Offset 0x0A8C - TypeC port GPIO setting
   GPIO Pin number for Type C Aux orientation setting, use the GpioPad that is defined
@@ -2853,7 +2902,7 @@ typedef struct {
 
 /** Offset 0x0AC9 - Reserved
 **/
-  UINT8                       Reserved87;
+  UINT8                       Reserved88;
 
 /** Offset 0x0ACA - DLL Weak Lock Support
   Enables/Disable DLL Weak Lock Support
@@ -2863,7 +2912,7 @@ typedef struct {
 
 /** Offset 0x0ACB - Reserved
 **/
-  UINT8                       Reserved88;
+  UINT8                       Reserved89;
 
 /** Offset 0x0ACC - Rx DQS Delay Comp Support
   Enables/Disable Rx DQS Delay Comp Support
@@ -2873,7 +2922,7 @@ typedef struct {
 
 /** Offset 0x0ACD - Reserved
 **/
-  UINT8                       Reserved89[2];
+  UINT8                       Reserved90[2];
 
 /** Offset 0x0ACF - Mrc Failure On Unsupported Dimm
   Enables/Disable Mrc Failure On Unsupported Dimm
@@ -2883,7 +2932,7 @@ typedef struct {
 
 /** Offset 0x0AD0 - Reserved
 **/
-  UINT8                      Reserved90[4];
+  UINT8                      Reserved91[4];
 
 /** Offset 0x0AD4 - DynamicMemoryBoost
   Enable/Disable Dynamic Memory Boost Feature. Only valid if SpdProfileSelected is
@@ -2901,7 +2950,7 @@ typedef struct {
 
 /** Offset 0x0ADC - Reserved
 **/
-  UINT8                      Reserved91[9];
+  UINT8                      Reserved92[9];
 
 /** Offset 0x0AE5 - Vref Offset
   Offset to be applied to DDRDATACH0_CR_DDRCRDATAOFFSETTRAIN.VrefOffset
@@ -2912,7 +2961,7 @@ typedef struct {
 
 /** Offset 0x0AE6 - Reserved
 **/
-  UINT8                       Reserved92[2];
+  UINT8                       Reserved93[2];
 
 /** Offset 0x0AE8 - tRRSG Delta
   Delay between Read-to-Read commands in the same Bank Group. 0 - Auto. Signed TAT
@@ -3028,7 +3077,7 @@ typedef struct {
 
 /** Offset 0x0AF8 - Reserved
 **/
-  UINT8                       Reserved93[41];
+  UINT8                       Reserved94[41];
 
 /** Offset 0x0B21 - Channel to CKD QCK Mapping
   Specify Channel to CKD QCK Mapping for CH0D0/CH0D1/CH1D0&CH1D1
@@ -3042,7 +3091,7 @@ typedef struct {
 
 /** Offset 0x0B31 - Reserved
 **/
-  UINT8                       Reserved94[55];
+  UINT8                       Reserved95[55];
 } FSP_M_CONFIG;
 
 /** Fsp M UPD Configuration

From 0d1545ffacff4ba2016557766c9b2eb2fc7b6496 Mon Sep 17 00:00:00 2001
From: Jeremy Compostella <jeremy.compostella@intel.com>
Date: Wed, 24 Sep 2025 14:11:57 -0700
Subject: [PATCH 2231/3886] soc/intel/pantherlake: Add hysteresis window UPDs
 support

This commit introduces configuration options for P-core and E-core
hysteresis time windows to support acoustic noise mitigation on Intel
Panther Lake (PTL) System on Chips (SoCs).

Change-Id: Ic3bceda06adf4e0a81b0503e5fb65895bfad2c12
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89333
Reviewed-by: Jamie Ryu <jamie.m.ryu@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Cliff Huang <cliff.huang@intel.com>
---
 src/soc/intel/pantherlake/chip.h                | 4 ++++
 src/soc/intel/pantherlake/romstage/fsp_params.c | 2 ++
 2 files changed, 6 insertions(+)

diff --git a/src/soc/intel/pantherlake/chip.h b/src/soc/intel/pantherlake/chip.h
index cb37155adb..d9da2d1b26 100644
--- a/src/soc/intel/pantherlake/chip.h
+++ b/src/soc/intel/pantherlake/chip.h
@@ -651,6 +651,10 @@ struct soc_intel_pantherlake_config {
 	 * as per `enum slew_rate` data type.
 	 */
 	uint8_t slow_slew_rate_config[NUM_VR_DOMAINS];
+	/* P-cores Hysteresis time window ranges from 1 to 50 ms. */
+	uint8_t pcore_hysteresis_window_ms;
+	/* E-cores Hysteresis time window ranges from 1 to 50 ms. */
+	uint8_t ecore_hysteresis_window_ms;
 
 	uint16_t max_dram_speed_mts;
 
diff --git a/src/soc/intel/pantherlake/romstage/fsp_params.c b/src/soc/intel/pantherlake/romstage/fsp_params.c
index 30b4eac48a..2a30bd3599 100644
--- a/src/soc/intel/pantherlake/romstage/fsp_params.c
+++ b/src/soc/intel/pantherlake/romstage/fsp_params.c
@@ -363,6 +363,8 @@ static void fill_fspm_acoustic_params(FSP_M_CONFIG *m_cfg,
 		return;
 
 	m_cfg->AcousticNoiseMitigation = config->enable_acoustic_noise_mitigation;
+	m_cfg->PcoreHysteresisWindow = config->pcore_hysteresis_window_ms;
+	m_cfg->EcoreHysteresisWindow = config->ecore_hysteresis_window_ms;
 
 	for (size_t i = 0; i < ARRAY_SIZE(config->disable_fast_pkgc_ramp); i++) {
 		m_cfg->FastPkgCRampDisable[i] = config->disable_fast_pkgc_ramp[i];

From c54658d20067f4cbe5149b39ceda9010bc0c4cd7 Mon Sep 17 00:00:00 2001
From: Jeremy Compostella <jeremy.compostella@intel.com>
Date: Tue, 10 Jun 2025 18:00:55 -0700
Subject: [PATCH 2232/3886] soc/intel/pantherlake: Add ICC Max configuration
 support

Add configuration for Maximum Integrated Circuit Current (ICC) for
various SKUs and VR domains. The ICC values, defined in 1/4A increments,
specify the maximum allowable current for a given SKU and VR domain
configuration. This update enhances power management by allowing
tailored ICC settings.

Change-Id: I2c4712521da7b89cd4b2a6c499e11245b8eeb719
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88044
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/soc/intel/pantherlake/chip.h                | 12 ++++++++++++
 src/soc/intel/pantherlake/romstage/fsp_params.c |  6 ++++++
 2 files changed, 18 insertions(+)

diff --git a/src/soc/intel/pantherlake/chip.h b/src/soc/intel/pantherlake/chip.h
index d9da2d1b26..a6e794d08c 100644
--- a/src/soc/intel/pantherlake/chip.h
+++ b/src/soc/intel/pantherlake/chip.h
@@ -190,6 +190,7 @@ enum vr_domain {
 	VR_DOMAIN_IA,
 	VR_DOMAIN_GT,
 	VR_DOMAIN_SA,
+	VR_DOMAIN_ATOM,
 	NUM_VR_DOMAINS,
 };
 
@@ -416,6 +417,17 @@ struct soc_intel_pantherlake_config {
 	 */
 	uint16_t thermal_design_current[MAX_PTL_SKUS][NUM_VR_DOMAINS];
 
+	/*
+	 * Maximum Integrated Current Capability (ICC) settings for various SKUs.
+	 *
+	 * ICC values represent the maximum allowable current for a given SKU
+	 * and VR domain configuration.
+	 *
+	 * ICC unit is defined in 1/4A increments. For example, a value of 400
+	 * corresponds to 100A.
+	 */
+	uint16_t icc_max[MAX_PTL_SKUS][NUM_VR_DOMAINS];
+
 	/*
 	 * SerialIO device mode selection:
 	 * PchSerialIoDisabled,
diff --git a/src/soc/intel/pantherlake/romstage/fsp_params.c b/src/soc/intel/pantherlake/romstage/fsp_params.c
index 2a30bd3599..2498bec4e2 100644
--- a/src/soc/intel/pantherlake/romstage/fsp_params.c
+++ b/src/soc/intel/pantherlake/romstage/fsp_params.c
@@ -346,6 +346,12 @@ static void fill_fspm_vr_config_params(FSP_M_CONFIG *m_cfg,
 		m_cfg->TdcEnable[i] = 1;
 		m_cfg->TdcCurrentLimit[i] = config->thermal_design_current[map->sku][i];
 	}
+
+	for (size_t i = 0; i < ARRAY_SIZE(config->icc_max[0]); i++) {
+		if (!config->icc_max[map->sku][i])
+			continue;
+		m_cfg->IccMax[i] = config->icc_max[map->sku][i];
+	}
 }
 
 #if CONFIG(PLATFORM_HAS_EARLY_LOW_BATTERY_INDICATOR)

From 59ede353c5b0d0ad89c1cb07fb98c8a3add5e4b6 Mon Sep 17 00:00:00 2001
From: Jeremy Compostella <jeremy.compostella@intel.com>
Date: Tue, 23 Sep 2025 14:27:56 -0700
Subject: [PATCH 2233/3886] soc/intel/pantherlake: Add Thermal Design Current
 (TDC) configuration

This commit adds the capability to configure TDC mode and time window
for each Voltage Regulator (VR) domain, providing better control over
thermal constraints and power consumption.

The TDC mode specifies the method (iPL2 or Irms) used for thermal
management, while the time window determines the duration for current
averaging.

Change-Id: I2e11855c4f0533d826a25efead02ddcff9ab1f62
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89319
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Bora Guvendik <bora.guvendik@intel.corp-partner.google.com>
---
 src/soc/intel/pantherlake/chip.h              | 29 +++++++++++++++++++
 .../intel/pantherlake/romstage/fsp_params.c   |  5 ++++
 2 files changed, 34 insertions(+)

diff --git a/src/soc/intel/pantherlake/chip.h b/src/soc/intel/pantherlake/chip.h
index a6e794d08c..1b6b0aecb3 100644
--- a/src/soc/intel/pantherlake/chip.h
+++ b/src/soc/intel/pantherlake/chip.h
@@ -210,6 +210,11 @@ enum slew_rate {
 	SLEW_IGNORE = 0xff,
 };
 
+enum tdc_mode {
+	TDC_IPL2,
+	TDC_IRMS,
+};
+
 struct soc_intel_pantherlake_config {
 
 	/* Common struct containing soc config data required by common code */
@@ -417,6 +422,30 @@ struct soc_intel_pantherlake_config {
 	 */
 	uint16_t thermal_design_current[MAX_PTL_SKUS][NUM_VR_DOMAINS];
 
+	/*
+	 * Thermal Design Current (TDC) mode for each Voltage Regulator (VR) domain.
+	 *
+	 * The mode indicates the method used for managing thermal constraints and power
+	 * consumption based on current measurement techniques.
+	 *
+	 * Possible values:
+	 * - 0: iPL2
+	 * - 1: Irms
+	 */
+	uint8_t tdc_mode[NUM_VR_DOMAINS];
+
+	/*
+	 * Time Window for Thermal Design Current (TDC) for each Voltage Regulator (VR)
+	 * domain.
+	 *
+	 * This array specifies the time window for TDC measurement for each VR
+	 * domain. The TDC time window determines the duration over which the current is
+	 * averaged.
+	 *
+	 * Units are milliseconds.
+	 */
+	uint32_t tdc_time_window_ms[NUM_VR_DOMAINS];
+
 	/*
 	 * Maximum Integrated Current Capability (ICC) settings for various SKUs.
 	 *
diff --git a/src/soc/intel/pantherlake/romstage/fsp_params.c b/src/soc/intel/pantherlake/romstage/fsp_params.c
index 2498bec4e2..c0dd691836 100644
--- a/src/soc/intel/pantherlake/romstage/fsp_params.c
+++ b/src/soc/intel/pantherlake/romstage/fsp_params.c
@@ -352,6 +352,11 @@ static void fill_fspm_vr_config_params(FSP_M_CONFIG *m_cfg,
 			continue;
 		m_cfg->IccMax[i] = config->icc_max[map->sku][i];
 	}
+
+	for (size_t i = 0; i < ARRAY_SIZE(config->tdc_mode); i++) {
+		m_cfg->TdcMode[i] = config->tdc_mode[i];
+		m_cfg->TdcTimeWindow[i] = config->tdc_time_window_ms[i];
+	}
 }
 
 #if CONFIG(PLATFORM_HAS_EARLY_LOW_BATTERY_INDICATOR)

From 1fb4a7409b0288ce349e0c359783f24df269d36b Mon Sep 17 00:00:00 2001
From: Jeremy Compostella <jeremy.compostella@intel.com>
Date: Tue, 7 Oct 2025 10:29:09 -0700
Subject: [PATCH 2234/3886] soc/intel/pantherlake: Add VR power state current
 thresholds

This commit introduces support for configuring power state current
thresholds (PS1, PS2, PS3) for each Voltage Regulator (VR) domain in the
Panther Lake SoC.

The thresholds allow platform integrators to specify current thresholds
(in 1/4 A increments, 0-128 A) for each VR domain and power state. A
value of 0 indicates AUTO (use default).

Change-Id: If4d473901c8de02b3d6cef44f5481a1864f14d63
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89450
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Cliff Huang <cliff.huang@intel.com>
---
 src/soc/intel/pantherlake/chip.h                | 14 ++++++++++++++
 src/soc/intel/pantherlake/romstage/fsp_params.c |  9 +++++++++
 2 files changed, 23 insertions(+)

diff --git a/src/soc/intel/pantherlake/chip.h b/src/soc/intel/pantherlake/chip.h
index 1b6b0aecb3..bfd307553b 100644
--- a/src/soc/intel/pantherlake/chip.h
+++ b/src/soc/intel/pantherlake/chip.h
@@ -457,6 +457,20 @@ struct soc_intel_pantherlake_config {
 	 */
 	uint16_t icc_max[MAX_PTL_SKUS][NUM_VR_DOMAINS];
 
+	/*
+	 * Power State Current Thresholds for VR Domains.
+	 *
+	 * These arrays define the current thresholds for different power states (PS1,
+	 * PS2, PS3) for each Voltage Regulator (VR) domain.
+	 *
+	 * Each value is defined in 1/4 A increments.  For example, a value of 400
+	 * corresponds to 100A. The valid range is 0-512 (0-128A).  A value of 0
+	 * indicates AUTO (use default).
+	 */
+	uint16_t ps1_threshold[NUM_VR_DOMAINS];
+	uint16_t ps2_threshold[NUM_VR_DOMAINS];
+	uint16_t ps3_threshold[NUM_VR_DOMAINS];
+
 	/*
 	 * SerialIO device mode selection:
 	 * PchSerialIoDisabled,
diff --git a/src/soc/intel/pantherlake/romstage/fsp_params.c b/src/soc/intel/pantherlake/romstage/fsp_params.c
index c0dd691836..04cd86d7a1 100644
--- a/src/soc/intel/pantherlake/romstage/fsp_params.c
+++ b/src/soc/intel/pantherlake/romstage/fsp_params.c
@@ -357,6 +357,15 @@ static void fill_fspm_vr_config_params(FSP_M_CONFIG *m_cfg,
 		m_cfg->TdcMode[i] = config->tdc_mode[i];
 		m_cfg->TdcTimeWindow[i] = config->tdc_time_window_ms[i];
 	}
+
+	for (size_t i = 0; i < ARRAY_SIZE(config->ps1_threshold); i++) {
+		if (config->ps1_threshold[i])
+			m_cfg->Ps1Threshold[i] = config->ps1_threshold[i];
+		if (config->ps2_threshold[i])
+			m_cfg->Ps2Threshold[i] = config->ps2_threshold[i];
+		if (config->ps3_threshold[i])
+			m_cfg->Ps3Threshold[i] = config->ps3_threshold[i];
+	}
 }
 
 #if CONFIG(PLATFORM_HAS_EARLY_LOW_BATTERY_INDICATOR)

From fba8c14c27af88a6b66f638396cb325b34b7d58d Mon Sep 17 00:00:00 2001
From: Simon Yang <simon1.yang@intel.com>
Date: Tue, 30 Sep 2025 19:53:51 +0800
Subject: [PATCH 2235/3886] mb/google/brya: add cnvi BT recovery mechanism

Add BT _PRR related methods to mitigate BT lost issue.

Refer to Intel TA#837249, toggling BTEN, BT_IF_SELECT, and
BT_RESET_GPIO to recovery BT device when BT became a low-speed usb
device.

BUG=b:451095940
TEST=Run reboot stress and check kernel log, BT could be recovery.
usb 3-10: new full-speed USB device number 4 using xhci_hcd
usb 3-10: New USB device found, idVendor=8087, idProduct=0033,
bcdDevice= 0.00
usb 3-10: New USB device strings: Mfr=0, Product=0, SerialNumber=0
usb 3-10: using ACPI '\_SB.PCI0.XHCI.RHUB.HS10' for 'reset' GPIO lookup
usb 3-10: USB disconnect, device number 4
usb 3-10: new low-speed USB device number 5 using xhci_hcd
usb 3-10: device descriptor read/64, error -71
usb 3-10: device descriptor read/64, error -71
usb 3-10: new low-speed USB device number 6 using xhci_hcd
usb 3-10: device descriptor read/64, error -71
usb 3-10: device descriptor read/64, error -71
usb 3-10: new full-speed USB device number 7 using xhci_hcd
usb 3-10: New USB device found, idVendor=8087, idProduct=0033,
bcdDevice= 0.00

Change-Id: I0d485a9102676624da28d5d681ea4510444e17bd
Signed-off-by: Simon Yang <simon1.yang@intel.com>
Signed-off-by: Jamie Chen <jamie.chen@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89384
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
---
 .../google/brya/acpi/cnvi_bt_reset.asl        | 53 +++++++++++++++++++
 src/mainboard/google/brya/dsdt.asl            |  2 +
 2 files changed, 55 insertions(+)
 create mode 100644 src/mainboard/google/brya/acpi/cnvi_bt_reset.asl

diff --git a/src/mainboard/google/brya/acpi/cnvi_bt_reset.asl b/src/mainboard/google/brya/acpi/cnvi_bt_reset.asl
new file mode 100644
index 0000000000..e2a387aee1
--- /dev/null
+++ b/src/mainboard/google/brya/acpi/cnvi_bt_reset.asl
@@ -0,0 +1,53 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <variant/gpio.h>
+
+/* If variants use other GPIO for BT_RESET
+   Define it at variant/gpio.h */
+#ifndef BT_RESET_GPIO
+#define BT_RESET_GPIO	GPP_D4
+#endif
+
+#define CNV_BTEN		GPP_VGPIO_0
+#define CNV_BT_IF_SELECT	GPP_VGPIO_5
+
+External (\_SB.PCI0.CTXS, MethodObj)
+External (\_SB.PCI0.STXS, MethodObj)
+
+Scope (\_SB.PCI0.XHCI.RHUB.HS10)
+{
+	PowerResource (CTTR, 0x00, 0x0000)
+	{
+		Method (_STA, 0, NotSerialized)  // _STA: Status
+		{
+			Return (One)
+		}
+
+		Method (_ON, 0, NotSerialized)  // _ON_: Power On
+		{
+			\_SB.PCI0.STXS(CNV_BTEN);
+			\_SB.PCI0.STXS(CNV_BT_IF_SELECT);
+			\_SB.PCI0.STXS(BT_RESET_GPIO);
+			Sleep (105)
+		}
+
+		Method (_OFF, 0, NotSerialized)  // _OFF: Power Off
+		{
+			\_SB.PCI0.CTXS(CNV_BTEN);
+			\_SB.PCI0.CTXS(CNV_BT_IF_SELECT);
+			\_SB.PCI0.CTXS(BT_RESET_GPIO);
+			Sleep (105)
+		}
+
+	}
+
+	Name (_PRR, Package (0x01)  // _PRR: Power Resource for Reset
+	{
+		CTTR
+	})
+
+	Name (_PR0, Package (0x01)  // _PR0: Power Resources for D0
+	{
+		CTTR
+	})
+}
diff --git a/src/mainboard/google/brya/dsdt.asl b/src/mainboard/google/brya/dsdt.asl
index 4f82409565..cd571ab6a8 100644
--- a/src/mainboard/google/brya/dsdt.asl
+++ b/src/mainboard/google/brya/dsdt.asl
@@ -46,4 +46,6 @@ DefinitionBlock(
 #if CONFIG(INCLUDE_NVIDIA_GPU_ASL)
 	#include "acpi/gpu_top.asl"
 #endif
+
+	#include "acpi/cnvi_bt_reset.asl"
 }

From 5e36d9ba044f446417857fdf237c4252679dce05 Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Mon, 13 Oct 2025 09:40:26 +0100
Subject: [PATCH 2236/3886] mb/starlabs/starbook/mtl: Update the VBT from 256
 to 261

This is a non-functional change, as the settings remain the same, and
it's only done as a pre-caution as FSP has been funny with VBT versions
before.

Change-Id: Ie7978e76286b3e2ff21fd0a28bfe51bdfd32f381
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89547
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 .../starlabs/starbook/variants/mtl/data.vbt   | Bin 7680 -> 7680 bytes
 .../starbook/variants/mtl/data_native_res.vbt | Bin 7680 -> 7680 bytes
 2 files changed, 0 insertions(+), 0 deletions(-)

diff --git a/src/mainboard/starlabs/starbook/variants/mtl/data.vbt b/src/mainboard/starlabs/starbook/variants/mtl/data.vbt
index b9189a74b0c9f171e61e4d1fd3bd689d313c45fd..680f2cfe2397cedbc981e3f30c629e8559220d0a 100644
GIT binary patch
delta 167
zcmZp$X|S0f!8%*!7lXm%LPp_<1_HvYjA9H~GXGvNFr+XtO7a*Qm>Fygp2Wzwd-5|z
zb;j$H`IyuhKTkGeQfK0qnH<lg#-uGXxgAKk%S>L+q{f)M`5Mz+CZ-_f$ro8uCckI3
z*=)+z$27TsO=a_8j?HY09h1xXlYv|T$^ZWu7?RKc1B0Fc<K#pE-N_09c|a_-xlcfY
F7XbeEG3WpQ

delta 141
zcmV;80CN9;Jb*lq7zI%r2>>vYaRC#NFc1>}0Tuut9RBJ60Av9H84NKnFfp-Hk^up6
zljZ>@0gaOm0w)2flQse;0>vAXUjilq;Tw~O0wx0e8<VdBCIK0<)&ji(0xkoS(FJ6a
v?*%-wH3p6Xv*!r21_5G|n-60HE-(R;!4MadfDl-dfDl5n*bpcUlW+z~pnEBi

diff --git a/src/mainboard/starlabs/starbook/variants/mtl/data_native_res.vbt b/src/mainboard/starlabs/starbook/variants/mtl/data_native_res.vbt
index 6a5f830b12a6c6a1206faec687fb07163f76a06b..f855dabf240a70571e2c1c25eeae7efd490739cf 100644
GIT binary patch
delta 167
zcmZp$X|S0f!8%*!H-o|CLPp_<1_HvYjA9H~GXGvNFr+XtO7a*Qm>Fygp2Wzwd-5|z
zb;j$H`IyuhKTkGeQfK0qnH<lg#-uGXxgAKk%S>L+q{f)M`5Mz+CZ-_f$ro8uCckI3
z*=)+z$27TsO=a_8j?HY09h1xXlYv|T$^ZWu7?RKc1B0Fc<K#pE-N_09c|a_-xlcfY
F7Xbg2G3fvR

delta 141
zcmV;80CN9;Jb*lq7zI%r3IH&ZaRC#NFc1>}0Tuut9RBJ60Av9H84NKnFfp-Hk^up6
zljZ>@0gaOm0w)2flQse;0>vAXUjilq;Tw~O0wx0e8<VdBCIK0<)&ji(0xkoS(FJ6a
v?*%-wH3p6Xv*!r21_5G|n-60HE-(R;!4MadfDl-dfDl5n*bpcUlW+z~p#Le7


From 06de11693f15f60480c03cbe87bade8ac96cb6b5 Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Mon, 13 Oct 2025 16:06:30 +0100
Subject: [PATCH 2237/3886] mb/starlabs/starfighter: Fix Thunderbolt disabling
 code

When Thunderbolt was disabled in the option table, only
VtdBaseAddress[3] was zero'd, when it should be
VtdBaseAddress[4] as well.

Change-Id: I63e3cefcb74c2ef31b5b0180d13a4720a6d7d0c2
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89553
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/starlabs/starfighter/variants/rpl/romstage.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/src/mainboard/starlabs/starfighter/variants/rpl/romstage.c b/src/mainboard/starlabs/starfighter/variants/rpl/romstage.c
index 785a8d135b..6ec63a16d7 100644
--- a/src/mainboard/starlabs/starfighter/variants/rpl/romstage.c
+++ b/src/mainboard/starlabs/starfighter/variants/rpl/romstage.c
@@ -134,6 +134,7 @@ void mainboard_memory_init_params(FSPM_UPD *mupd)
 	if (get_uint_option("thunderbolt", 1) == 0) {
 		mupd->FspmConfig.VtdItbtEnable = 0;
 		mupd->FspmConfig.VtdBaseAddress[3] = 0;
+		mupd->FspmConfig.VtdBaseAddress[4] = 0;
 		mupd->FspmConfig.TcssDma0En = 0;
 		mupd->FspmConfig.TcssItbtPcie0En = 0;
 		mupd->FspmConfig.TcssXhciEn = 0;

From 1b5aaaefd91de61e0d307c46572cfa5741a052c0 Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Tue, 14 Oct 2025 09:38:25 +0100
Subject: [PATCH 2238/3886] soc/intel/meteorlake: Fix IGD IRQ
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

The wrong definition was used, so fix it.

Change-Id: I7ebbf0dcba4117ddeaa496b6faa83561d82c621d
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89561
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
---
 src/soc/intel/meteorlake/fsp_params.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/soc/intel/meteorlake/fsp_params.c b/src/soc/intel/meteorlake/fsp_params.c
index 0502b757c5..61be03ad47 100644
--- a/src/soc/intel/meteorlake/fsp_params.c
+++ b/src/soc/intel/meteorlake/fsp_params.c
@@ -62,7 +62,7 @@ static const struct slot_irq_constraints irq_constraints[] = {
 		.slot = PCI_DEV_SLOT_IGD,
 		.fns = {
 			/* INTERRUPT_PIN is RO/0x01 */
-			FIXED_INT_ANY_PIRQ(PCI_DEV_SLOT_IGD, PCI_INT_A),
+			FIXED_INT_ANY_PIRQ(PCI_DEVFN_IGD, PCI_INT_A),
 		},
 	},
 	{

From 115a6ce36a4e48e3790705a2911fc04b923f9a96 Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Tue, 14 Oct 2025 16:43:16 +0100
Subject: [PATCH 2239/3886] mb/starlabs/starbook/adl: Correct clock request
 number in comment

Change-Id: I36e5b57923f2205958545f86ebd350312b0dca0d
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89573
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
---
 src/mainboard/starlabs/starbook/variants/adl/gpio.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/mainboard/starlabs/starbook/variants/adl/gpio.c b/src/mainboard/starlabs/starbook/variants/adl/gpio.c
index 2a90e4c103..d8a1a2ce41 100644
--- a/src/mainboard/starlabs/starbook/variants/adl/gpio.c
+++ b/src/mainboard/starlabs/starbook/variants/adl/gpio.c
@@ -45,7 +45,7 @@ const struct pad_config gpio_table[] = {
 	PAD_CFG_GPO(GPP_H0, 1, PLTRST),					/* Reset */
 
 	/* Wireless */
-	PAD_CFG_NF(GPP_D7, NONE, DEEP, NF1),				/* Clock Request 1 */
+	PAD_CFG_NF(GPP_D7, NONE, DEEP, NF1),				/* Clock Request 2 */
 	PAD_CFG_GPO(GPP_H2, 1, PLTRST),					/* Reset */
 	PAD_CFG_GPO(GPP_E3, 1, DEEP),					/* WiFi RF Kill */
 	PAD_CFG_GPO(GPP_A13, 1, DEEP),					/* Bluetooth RF Kill */

From 2c465c0e216c230fe0692e84b3c5527e9fcbff8b Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Tue, 14 Oct 2025 16:44:58 +0100
Subject: [PATCH 2240/3886] mb/starlabs/starbook/adl: Re-order GPIOs to match
 other boards

Change-Id: Ibfacb4430e74f7cd9dfcac2c20fbb59635851979
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89574
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
---
 src/mainboard/starlabs/starbook/variants/adl/gpio.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/mainboard/starlabs/starbook/variants/adl/gpio.c b/src/mainboard/starlabs/starbook/variants/adl/gpio.c
index d8a1a2ce41..f541553361 100644
--- a/src/mainboard/starlabs/starbook/variants/adl/gpio.c
+++ b/src/mainboard/starlabs/starbook/variants/adl/gpio.c
@@ -41,8 +41,8 @@ const struct pad_config gpio_table[] = {
 
 	/* SSD */
 	PAD_CFG_NF(GPP_D6, NONE, DEEP, NF1),				/* Clock Request 1 */
-	PAD_CFG_GPO(GPP_D16, 1, DEEP),					/* Enable */
 	PAD_CFG_GPO(GPP_H0, 1, PLTRST),					/* Reset */
+	PAD_CFG_GPO(GPP_D16, 1, DEEP),					/* Enable */
 
 	/* Wireless */
 	PAD_CFG_NF(GPP_D7, NONE, DEEP, NF1),				/* Clock Request 2 */

From 38525716d8b51e9712ec8d1d6e0008d1e1e01605 Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Tue, 14 Oct 2025 16:54:06 +0100
Subject: [PATCH 2241/3886] mb/starlabs/starbook/adl: Re-order the config strap
 GPIOs

This is a non-functional change, it just puts them into a the same
format as the other Star Labs boards.

Change-Id: I849d0b50490eec6b6c58bd0fd29f57e434ba95c4
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89575
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 .../starlabs/starbook/variants/adl/gpio.c     | 55 ++++++++-----------
 1 file changed, 23 insertions(+), 32 deletions(-)

diff --git a/src/mainboard/starlabs/starbook/variants/adl/gpio.c b/src/mainboard/starlabs/starbook/variants/adl/gpio.c
index f541553361..bdc0e14212 100644
--- a/src/mainboard/starlabs/starbook/variants/adl/gpio.c
+++ b/src/mainboard/starlabs/starbook/variants/adl/gpio.c
@@ -79,12 +79,24 @@ const struct pad_config gpio_table[] = {
 	PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1),				/* Data */
 	PAD_CFG_GPO(GPP_E8, 1, DEEP),					/* DRAM Sleep */
 
+	/* Config Straps 									[ Low      / High     ] */
+	PAD_NC(GPP_B14, NONE),						/* Top Swap		[ Disabled / Enabled  ] */
+	PAD_NC(GPP_B18, NONE),						/* Reboot Support	[ Enabled  / Disabled ] */
+	PAD_CFG_GPO(GPP_C2, 1, PLTRST),					/* TLS Confidentiality	[ Disabled / Enabled  ] */
+	PAD_CFG_GPO(GPP_C5, 0, DEEP),					/* eSPI			[ Enabled  / Disabled ] */
+	PAD_CFG_GPO(GPP_E6, 0, DEEP),					/* JTAG ODT		[ Disabled / Enabled  ] */
+	PAD_CFG_GPO(GPP_H1, 0, DEEP),					/* BFX Strap 2 Bit 3	[ Disabled / Enabled  ] */
+	PAD_NC(GPP_F2, NONE),						/* M.2 CNVi		[ Enabled  / Disabled ] */
+	PAD_NC(GPP_E19, NONE),						/* TBT LSX #0		[ 1.8V     / 3.3V     ] */
+	PAD_CFG_GPO(GPP_F7, 0, DEEP),					/* MCRO LDO		[ Disabled / Bypass   ] */
+	PAD_CFG_GPO(GPD7, 0, PWROK),					/* RTC Clock Delay	[ Disabled / 95ms     ] */
+
+
 	/* GPD2:	LAN Wake					*/
 	PAD_NC(GPD2, NONE),
 	/* GPD6:	Sleep A						*/
 	PAD_NC(GPD6, NONE),
-	/* GPD7:	Power Adapter Disable				*/
-	PAD_CFG_GPO(GPD7, 0, PWROK),
+
 	/* GPD9:	Wireless LAN Sleep				*/
 	PAD_NC(GPD9, NONE),
 	/* GPD10:	Sleep S5					*/
@@ -141,20 +153,14 @@ const struct pad_config gpio_table[] = {
 	PAD_NC(GPP_B11, NONE),
 	/* B12:		PM SLP S0					*/
 	PAD_NC(GPP_B12, NONE),
-	/* B14:		Top Swap Override	Weak Internal PD 20K
-				High:	Enabled
-				Low:	Disabled			*/
-	PAD_NC(GPP_B14, NONE),
+
 	/* B15:		Not Connected					*/
 	PAD_NC(GPP_B15, NONE),
 	/* B16:		Not Connected					*/
 	PAD_NC(GPP_B16, NONE),
 	/* B17:		Not Connected					*/
 	PAD_NC(GPP_B17, NONE),
-	/* B18:		Reboot Support		Weak Internal PD 20K
-				High:	Disabled
-				Low:	Enabled				*/
-	PAD_NC(GPP_B18, NONE),
+
 	/* B19:		Not Connected					*/
 	PAD_NC(GPP_B19, NONE),
 	/* B20:		Not Connected					*/
@@ -170,18 +176,12 @@ const struct pad_config gpio_table[] = {
 	/* B25:		Not Connected					*/
 	PAD_NC(GPP_B25, NONE),
 
-	/* C2:		TLS Confidentiality	Weak Internal PD 20K
-				Low:	Disabled
-				High:	Enabled				*/
-	PAD_CFG_GPO(GPP_C2, 1, PLTRST),
+
 	/* C3:		SML 0 Clock					*/
 	PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1),
 	/* C4:		SML 0 Data					*/
 	PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1),
-	/* C5:		Boot Strap		Weak Internal PD 20K
-				Low:	ESPI
-				High:	Disabled			*/
-	PAD_CFG_GPO(GPP_C5, 0, DEEP),
+
 	/* C6:		SML 1 Clock					*/
 	PAD_CFG_NF(GPP_C6, NONE, DEEP, NF1),
 	/* C7:		SML 1 Data					*/
@@ -264,10 +264,7 @@ const struct pad_config gpio_table[] = {
 	PAD_NC(GPP_E4, NONE),
 	/* E5:		Not Connected					*/
 	PAD_NC(GPP_E5, NONE),
-	/* E6:		JTAG ODT		No internal PD
-				Low:	Disabled
-				High:	Enabled				*/
-	PAD_CFG_GPO(GPP_E6, 0, DEEP),
+
 	/* E7:		Embedded Controller SMI				*/
 	PAD_NC(GPP_E7, NONE),
 	/* E9:		USB OverCurrent 0				*/
@@ -284,8 +281,7 @@ const struct pad_config gpio_table[] = {
 	PAD_NC(GPP_E17, NONE),
 	/* E18:		Not Connected					*/
 	PAD_NC(GPP_E18, NONE),
-	/* E19:		Thunderbolt LSX RXD				*/
-	PAD_NC(GPP_E19, NONE),
+
 	/* E20:		Not Connected					*/
 	PAD_NC(GPP_E20, NONE),
 	/* E21:		Not Connected					*/
@@ -299,8 +295,7 @@ const struct pad_config gpio_table[] = {
 	PAD_NC(GPP_F0, NONE),
 	/* F1:		CNV BRI Response				*/
 	PAD_NC(GPP_F1, NONE),
-	/* F2:		CNV RGI Data					*/
-	PAD_NC(GPP_F2, NONE),
+
 	/* F3:		CNV RGI Response				*/
 	PAD_NC(GPP_F3, NONE),
 	/* F4:		CNV RF Reset					*/
@@ -309,10 +304,7 @@ const struct pad_config gpio_table[] = {
 	PAD_NC(GPP_F5, NONE),
 	/* F6:		CNV PA Blanking					*/
 	PAD_NC(GPP_F6, NONE),
-	/* F7:		TBT LSX VCCIO		Weak Internal PD 20K
-				Low:	1.8V
-				High:	3.3V				*/
-	PAD_CFG_GPO(GPP_F7, 0, DEEP),
+
 	/* F8:		Not Connected					*/
 	PAD_NC(GPP_F8, NONE),
 	/* F9:		EC Sleep S0					*/
@@ -346,8 +338,7 @@ const struct pad_config gpio_table[] = {
 	/* F23:		Not Connected					*/
 	PAD_NC(GPP_F23, NONE),
 
-	/* H1:		BFX Strap 2 Bit 3	Weak Internal PD 20K	*/
-	PAD_CFG_GPO(GPP_H1, 0, DEEP),
+
 	/* H3:		Not Connected					*/
 	PAD_NC(GPP_H3, NONE),
 	/* H6:		Not Connected					*/

From ed736a47d86b84fc0f3f8ebfd8fc41efa1c30aae Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Tue, 14 Oct 2025 20:07:40 +0100
Subject: [PATCH 2242/3886] mb/starlabs/byte_adl: Configure additional SSD
 GPIOs

SATA_DEVSLP1B and PEDET were simply missed, so configure them

Change-Id: Iface1f19c5a93f5a911861fbad7fa4b3f808bfef
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89577
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/starlabs/byte_adl/variants/mk_ii/gpio.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/mainboard/starlabs/byte_adl/variants/mk_ii/gpio.c b/src/mainboard/starlabs/byte_adl/variants/mk_ii/gpio.c
index 28dd5486de..bddabb14db 100644
--- a/src/mainboard/starlabs/byte_adl/variants/mk_ii/gpio.c
+++ b/src/mainboard/starlabs/byte_adl/variants/mk_ii/gpio.c
@@ -38,6 +38,8 @@ const struct pad_config gpio_table[] = {
 	PAD_CFG_NF(GPP_D5, NONE, DEEP, NF1),				/* Clock Request 0 */
 	PAD_CFG_GPO(GPP_H0, 1, PLTRST),					/* Reset */
 	PAD_CFG_GPO(GPP_D16, 1, DEEP),					/* Enable */
+	PAD_CFG_NF(GPP_H13, NONE, DEEP, NF5),				/* Device Sleep */
+	PAD_CFG_NF(GPP_A12, NONE, DEEP, NF1),				/* PEDET */
 
 	/* Wireless */
 	PAD_CFG_NF(GPP_F0, NONE, DEEP, NF1),				/* BRI Data */
@@ -107,7 +109,6 @@ const struct pad_config gpio_table[] = {
 	PAD_NC(GPP_A7, NONE),
 	PAD_NC(GPP_A8, NONE),
 	PAD_NC(GPP_A11, NONE),
-	PAD_NC(GPP_A12, NONE),
 	PAD_NC(GPP_A14, NONE),
 	PAD_NC(GPP_A15, NONE),
 	PAD_NC(GPP_A16, NONE),
@@ -220,7 +221,6 @@ const struct pad_config gpio_table[] = {
 	PAD_NC(GPP_H8, NONE),
 	PAD_NC(GPP_H9, NONE),
 	PAD_NC(GPP_H12, NONE),
-	PAD_NC(GPP_H13, NONE),
 	PAD_NC(GPP_H14, NONE),
 	PAD_NC(GPP_H16, NONE),
 	PAD_NC(GPP_H19, NONE),

From f4ecb693147c390e1c1b45cd2b63ce05b7b075f5 Mon Sep 17 00:00:00 2001
From: Dmytro Aleksandrov <alkersan@gmail.com>
Date: Sun, 12 Oct 2025 12:15:07 -0400
Subject: [PATCH 2243/3886] util/inteltool: Add Twin Lake UHD Graphics PCI IDs

Add PCI IDs and descriptor strings of the integrated GPU
for the Twin Lake CPU.
Reference document: #759603 Rev 002

---
CPU: ID 0xb06e0, Processor Type 0x0, Family 0x6, Model 0xbe, Stepping 0x0
Northbridge: 8086:4617 (12th generation (Alder Lake N family) Intel Processor)
Southbridge: 8086:5481 (Alder Lake-N)
IGD: 8086:46d3 (Intel(R) UHD Graphics)
---

TEST=build and run inteltool on N355 mini pc, verify GPU ID is not unknown.

Change-Id: I8921bd1e22690acbb71547590905f739485126fb
Signed-off-by: Dmytro Aleksandrov <alkersan@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89529
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 util/inteltool/inteltool.c | 4 ++++
 util/inteltool/inteltool.h | 2 ++
 2 files changed, 6 insertions(+)

diff --git a/util/inteltool/inteltool.c b/util/inteltool/inteltool.c
index b7dbd62223..e6f82371da 100644
--- a/util/inteltool/inteltool.c
+++ b/util/inteltool/inteltool.c
@@ -625,6 +625,10 @@ static const struct {
 	  "Intel(R) UHD Graphics" },
 	{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ADL_N_UHD_3,
 	  "Intel(R) UHD Graphics" },
+	{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ADL_N_UHD_4,
+	  "Intel(R) UHD Graphics" },
+	{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ADL_N_UHD_5,
+	  "Intel(R) UHD Graphics" },
 	{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_RPL_H_IRIS_XE,
 	  "Intel(R) Iris Xe Graphics [RPL-P]" },
 	{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_MTL_M_GT2,
diff --git a/util/inteltool/inteltool.h b/util/inteltool/inteltool.h
index f44c79c5fc..80d307cfe4 100644
--- a/util/inteltool/inteltool.h
+++ b/util/inteltool/inteltool.h
@@ -513,6 +513,8 @@ static inline uint32_t inl(unsigned port)
 #define PCI_DEVICE_ID_INTEL_ADL_N_UHD		0x46D0
 #define PCI_DEVICE_ID_INTEL_ADL_N_UHD_2		0x46D1
 #define PCI_DEVICE_ID_INTEL_ADL_N_UHD_3		0x46D2
+#define PCI_DEVICE_ID_INTEL_ADL_N_UHD_4		0x46D3
+#define PCI_DEVICE_ID_INTEL_ADL_N_UHD_5		0x46D4
 #define PCI_DEVICE_ID_INTEL_MTL_M_GT2		0x7d40
 #define PCI_DEVICE_ID_INTEL_MTL_P_GT2_1		0x7d45
 #define PCI_DEVICE_ID_INTEL_MTL_P_GT2_2		0x7d50

From 16feb1bb28025b4f1bc6e4286b6eecfeffccf067 Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Thu, 9 Oct 2025 10:49:50 -0500
Subject: [PATCH 2244/3886] mb/google/brya/var/nissa: Add missing device type
 to gfx device

Commit 743e3a07f529 ("mb/google/brya/var/nissa: Remove duplicate ACPI
device GFX0") removed the GMA default panel and replaced it with the
generic gfx device, but left out the device type field, which resulted
in changes to the _DOD and _ADR methods for the GFX0 ACPI device.

This change caused Windows to ignore the ACPI brightness controls,
leaving the display fixed at full brightness. Add the missing device
type entry to restore the brightness control functionality.

before (incorrect):
_DOD: 0x80010000
_ADR: Zero

after (correct):
_DOD: 0x80010400
_ADR: 0x00000400

TEST=build/boot Win11, Linux on craaskvin, verify brightness controls
functional under both OSes.

Change-Id: Ia0cfcec14963605ce874c6c7ed6b26c725cf74f0
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89498
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Simon Yang <simon1.yang@intel.com>
Reviewed-by: Eric Lai <ericllai@google.com>
---
 src/mainboard/google/brya/variants/baseboard/nissa/devicetree.cb | 1 +
 1 file changed, 1 insertion(+)

diff --git a/src/mainboard/google/brya/variants/baseboard/nissa/devicetree.cb b/src/mainboard/google/brya/variants/baseboard/nissa/devicetree.cb
index 2804818261..840c4e778f 100644
--- a/src/mainboard/google/brya/variants/baseboard/nissa/devicetree.cb
+++ b/src/mainboard/google/brya/variants/baseboard/nissa/devicetree.cb
@@ -192,6 +192,7 @@ chip soc/intel/alderlake
 			chip drivers/gfx/generic
 				register "device_count" = "1"
 				register "device[0].name" = ""LCD0""
+				register "device[0].type" = "panel"
 				device generic 0 on end
 			end
 		end

From 19feafc018f1b0f5184edd6bf4b4b068ef190dab Mon Sep 17 00:00:00 2001
From: Jeremy Compostella <jeremy.compostella@intel.com>
Date: Wed, 8 Oct 2025 09:57:01 -0700
Subject: [PATCH 2245/3886] drivers/intel/fsp2_0/ppi/mp_service_ppi: Support
 CPU_V2_EXTENDED_TOPOLOGY

Complies with the Multi-Processor (MP) service as defined by the
EFI_MP_SERVICES_PROTOCOL.GetProcessorInfo() in the Platform
Initialization Specification 1.7. If bit 24 (CPU_V2_EXTENDED_TOPOLOGY)
is set in ProcessorId, GetProcessorInfo() must populate the
EFI_CPU_PHYSICAL_LOCATION2 data structure.

TEST=FSP using PI 1.7 GetProcessorInfo() is able to retrieve the
     information instead of receiving an EFI_NOT_FOUND error.

Change-Id: If4d473901c8de02b3d6cef44f5481a1864f14d65
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89462
Reviewed-by: Zhixing Ma <zhixing.ma@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
---
 src/drivers/intel/fsp2_0/ppi/mp_service_ppi.c | 21 +++++++++++++++++++
 1 file changed, 21 insertions(+)

diff --git a/src/drivers/intel/fsp2_0/ppi/mp_service_ppi.c b/src/drivers/intel/fsp2_0/ppi/mp_service_ppi.c
index b697ccbf21..ccc6bdbf97 100644
--- a/src/drivers/intel/fsp2_0/ppi/mp_service_ppi.c
+++ b/src/drivers/intel/fsp2_0/ppi/mp_service_ppi.c
@@ -40,6 +40,14 @@ efi_return_status_t mp_get_number_of_processors(efi_uintn_t *number_of_processor
 efi_return_status_t mp_get_processor_info(efi_uintn_t processor_number,
 	efi_processor_information *processor_info_buffer)
 {
+#if CONFIG_UDK_VERSION >= CONFIG_UDK_202005_VERSION
+	bool location2_requested = false;
+	if (processor_number & CPU_V2_EXTENDED_TOPOLOGY) {
+		processor_number &= ~CPU_V2_EXTENDED_TOPOLOGY;
+		location2_requested = true;
+	}
+#endif
+
 	if (processor_number >= MIN(get_cpu_count(), CONFIG_MAX_CPUS))
 		return FSP_NOT_FOUND;
 
@@ -64,6 +72,19 @@ efi_return_status_t mp_get_processor_info(efi_uintn_t processor_number,
 	processor_info_buffer->Location.Core = dev->path.apic.core_id_within_package;
 	processor_info_buffer->Location.Thread = dev->path.apic.thread_id;
 
+#if CONFIG_UDK_VERSION >= CONFIG_UDK_202005_VERSION
+	if (location2_requested) {
+		EFI_CPU_PHYSICAL_LOCATION2 *location2 =
+			&processor_info_buffer->ExtendedInformation.Location2;
+		location2->Package = dev->path.apic.package_id;
+		location2->Die = dev->path.apic.die_id;
+		location2->Tile = dev->path.apic.tile_id;
+		location2->Module = dev->path.apic.module_id;
+		location2->Core = dev->path.apic.core_id_within_package;
+		location2->Thread = dev->path.apic.thread_id;
+	}
+#endif
+
 	return FSP_SUCCESS;
 }
 

From 5271ac7ac5acb21f286d01a436cabbcc6cf3da51 Mon Sep 17 00:00:00 2001
From: Swathi Tamilselvan <tswathi@qualcomm.corp-partner.google.com>
Date: Mon, 13 Oct 2025 16:30:16 +0530
Subject: [PATCH 2246/3886] soc/qualcomm/x1p42100: Reserve DDR carveout region

Reserve DDR region for HYP, QTEE SMMU buffers, Gunyah and ACDB. The
carveout is located at: 0xFF800000 - ((n*5.5)+1+32+3), where n is
the DRAM size. This region is protected by QTEE and must remain
reserved to prevent access by other components.

TEST=1. Create an image.serial.bin and ensure it boots on X1P42100.
2. Verified carveout region reservation via depthcharge serial log.
Prior to reservation, the memory wipeout range was [0x000000f61f7920,
0x000000ff800000). After reserving the carveout, the range is reduced
to [0x000000f61f7920, 0x000000f7c00000).
```
Wipe memory regions:
        [0x00000080000000, 0x00000080a00000)
        [0x000000815a0000, 0x00000081a00000)
        [0x00000081cf4000, 0x00000081e00000)
        [0x00000082800000, 0x00000085380000)
        [0x00000085f80000, 0x000000866c0000)
        [0x00000091380000, 0x000000c72c4000)
        [0x000000c7800000, 0x000000d8000000)
        [0x000000d9600000, 0x000000f1000000)
        [0x000000f61f7920, 0x000000f7c00000)
        [0x00000880000000, 0x00000c00000000)
```

Change-Id: I511452054dcf10f8a2254eafb2f127c05a3249e5
Signed-off-by: Swathi Tamilselvan <tswathi@qualcomm.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89552
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
---
 src/soc/qualcomm/x1p42100/memlayout.ld | 2 ++
 src/soc/qualcomm/x1p42100/soc.c        | 9 +++++++++
 2 files changed, 11 insertions(+)

diff --git a/src/soc/qualcomm/x1p42100/memlayout.ld b/src/soc/qualcomm/x1p42100/memlayout.ld
index 9996889cfd..b93a1e4c80 100644
--- a/src/soc/qualcomm/x1p42100/memlayout.ld
+++ b/src/soc/qualcomm/x1p42100/memlayout.ld
@@ -23,6 +23,8 @@
  * 0xFFE00000    +----------------------------------------------------------+      |        |
  *               |                     dram_llcc_lpi                        |      |        |
  * 0xFF800000    +----------------------------------------------------------+      |        |
+ *               |                       dram_acdb                          |      |        |
+ *               +----------------------------------------------------------+      |        |
  *               |                ... Usable memory ...                     |      |        |
  * 0xDF4C0000    +----------------------------------------------------------+      |        |
  *               |                       dram_ta                            |      |        |
diff --git a/src/soc/qualcomm/x1p42100/soc.c b/src/soc/qualcomm/x1p42100/soc.c
index f76ba44e24..ffa3a0e7d9 100644
--- a/src/soc/qualcomm/x1p42100/soc.c
+++ b/src/soc/qualcomm/x1p42100/soc.c
@@ -14,6 +14,11 @@ static struct device_operations pci_domain_ops = {
 	.enable = &qcom_setup_pcie_host,
 };
 
+static uint64_t calc_acdb_carveout_size(void)
+{
+	return ((((region_sz(ddr_region) / GiB) * 11) / 2 + 36) * MiB);
+}
+
 static void soc_read_resources(struct device *dev)
 {
 	int index = 0;
@@ -43,6 +48,10 @@ static void soc_read_resources(struct device *dev)
 	reserved_ram_range(dev, index++, (uintptr_t)_dram_wlan, REGION_SIZE(dram_wlan));
 	reserved_ram_range(dev, index++, (uintptr_t)_dram_pil, REGION_SIZE(dram_pil));
 	reserved_ram_range(dev, index++, (uintptr_t)_dram_ta, REGION_SIZE(dram_ta));
+
+	/* ACDB carveout region located at 0xFF800000 - (n*5.5 +1+32+3) where n is size of DDR */
+	reserved_ram_range(dev, index++, (uintptr_t)(_dram_llcc_lpi - calc_acdb_carveout_size()),
+			calc_acdb_carveout_size());
 	reserved_ram_range(dev, index++, (uintptr_t)_dram_llcc_lpi, REGION_SIZE(dram_llcc_lpi));
 	reserved_ram_range(dev, index++, (uintptr_t)_dram_smem, REGION_SIZE(dram_smem));
 }

From 0ff213d711f7bfb2b329a2fd7c291931e5c26f67 Mon Sep 17 00:00:00 2001
From: Yidi Lin <yidilin@google.com>
Date: Thu, 9 Oct 2025 00:38:12 +0800
Subject: [PATCH 2247/3886] soc/mediatek/common: Conditionally set up
 framebuffer

To save memory, only allocate and configure the framebuffer when display
output is required during boot.

This is achieved by:
1. Making the `framebuffer` memory region optional.
2. Guarding the framebuffer's uncached MMU configuration with a
   `display_init_required()` check.

This ensures the framebuffer is prepared only when needed, saving
memory on boot paths that do not require display.

BUG=b:319511268
BRANCH=none
TEST=emerge-rauru coreboot

Change-Id: I3808031160e421de7c21f585f4b79d42bfddccc4
Signed-off-by: Yidi Lin <yidilin@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89541
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/include/symbols.h                    | 2 +-
 src/soc/mediatek/common/display.c        | 7 ++++++-
 src/soc/mediatek/common/mmu_operations.c | 5 +++++
 3 files changed, 12 insertions(+), 2 deletions(-)

diff --git a/src/include/symbols.h b/src/include/symbols.h
index 48ff832afd..ad8231c089 100644
--- a/src/include/symbols.h
+++ b/src/include/symbols.h
@@ -75,7 +75,7 @@ DECLARE_REGION(ttb)
 DECLARE_OPTIONAL_REGION(ttb_subtables)
 DECLARE_REGION(dma_coherent)
 DECLARE_REGION(soc_registers)
-DECLARE_REGION(framebuffer)
+DECLARE_OPTIONAL_REGION(framebuffer)
 DECLARE_REGION(pdpt)
 DECLARE_OPTIONAL_REGION(opensbi)
 DECLARE_OPTIONAL_REGION(bl31)
diff --git a/src/soc/mediatek/common/display.c b/src/soc/mediatek/common/display.c
index 84981f059e..163b900769 100644
--- a/src/soc/mediatek/common/display.c
+++ b/src/soc/mediatek/common/display.c
@@ -11,6 +11,7 @@
 #include <soc/dsi.h>
 #include <soc/mtcmos.h>
 #include <stdio.h>
+#include <symbols.h>
 
 static struct panel_serializable_data *get_mipi_cmd_from_cbfs(struct panel_description *desc)
 {
@@ -70,6 +71,7 @@ int mtk_display_init(void)
 	struct fb_info *info;
 	const char *name;
 	struct panel_description *panel = get_active_panel();
+	uintptr_t fb_addr;
 
 	if (!panel || panel->disp_path == DISP_PATH_NONE) {
 		printk(BIOS_ERR, "%s: Failed to get the active panel\n", __func__);
@@ -143,7 +145,10 @@ int mtk_display_init(void)
 		}
 	}
 
-	info = fb_new_framebuffer_info_from_edid(&edid, (uintptr_t)0);
+	fb_addr = (REGION_SIZE(framebuffer)) ? (uintptr_t)_framebuffer : 0;
+
+	info = fb_new_framebuffer_info_from_edid(&edid, fb_addr);
+
 	if (info)
 		fb_set_orientation(info, panel->orientation);
 
diff --git a/src/soc/mediatek/common/mmu_operations.c b/src/soc/mediatek/common/mmu_operations.c
index 1bbe4dc319..68ac77d515 100644
--- a/src/soc/mediatek/common/mmu_operations.c
+++ b/src/soc/mediatek/common/mmu_operations.c
@@ -1,6 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
 #include <arch/mmu.h>
+#include <bootmode.h>
 #include <symbols.h>
 #include <soc/emi.h>
 #include <soc/mmu_operations.h>
@@ -51,6 +52,10 @@ void mtk_mmu_after_dram(void)
 
 	mmu_config_range(_dram_dma, REGION_SIZE(dram_dma), NONSECURE_UNCACHED_MEM);
 
+	if (display_init_required())
+		mmu_config_range(_framebuffer, REGION_SIZE(framebuffer),
+				 NONSECURE_UNCACHED_MEM);
+
 	mtk_soc_after_dram();
 }
 

From bdd4561536380b19880d48d9271ff4d831e36226 Mon Sep 17 00:00:00 2001
From: Yidi Lin <yidilin@google.com>
Date: Thu, 9 Oct 2025 13:48:38 +0800
Subject: [PATCH 2248/3886] soc/mediatek/mt8196: Add mtk_ddp_ovlsys_start for
 rendering framebuffer

Implement mtk_ddp_ovlsys_start in order to render the logo in coreboot.
The implementation is ported from depthcharge[1].

[1]: https://chromium.googlesource.com/chromiumos/platform/depthcharge/+/refs/heads/main/src/drivers/video/mtk_ddp.c

BUG=b:319511268
TEST=Draw the logo in ramstage

Change-Id: I37f929b85d4df818163e3af364038631f7b4623d
Signed-off-by: Yidi Lin <yidilin@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89542
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/soc/mediatek/common/include/soc/display.h | 1 +
 src/soc/mediatek/mt8196/ddp.c                 | 8 ++++++++
 2 files changed, 9 insertions(+)

diff --git a/src/soc/mediatek/common/include/soc/display.h b/src/soc/mediatek/common/include/soc/display.h
index a874412aff..fdcfcfdef2 100644
--- a/src/soc/mediatek/common/include/soc/display.h
+++ b/src/soc/mediatek/common/include/soc/display.h
@@ -33,5 +33,6 @@ int mtk_display_init(void);
 
 void mtk_ddp_init(void);
 void mtk_ddp_mode_set(const struct edid *edid, enum disp_path_sel path);
+void mtk_ddp_ovlsys_start(uintptr_t fb_addr);
 
 #endif
diff --git a/src/soc/mediatek/mt8196/ddp.c b/src/soc/mediatek/mt8196/ddp.c
index 9453622a6e..6e57e78301 100644
--- a/src/soc/mediatek/mt8196/ddp.c
+++ b/src/soc/mediatek/mt8196/ddp.c
@@ -310,3 +310,11 @@ void mtk_ddp_mode_set(const struct edid *edid, enum disp_path_sel path)
 	main_disp_path_setup(width, height, vrefresh, path);
 	ovlsys_layer_config(fmt, bpp, width, height);
 }
+
+void mtk_ddp_ovlsys_start(uintptr_t fb_addr)
+{
+	write32(&exdma2_reg->ovl_addr, fb_addr);
+	setbits32(&exdma2_reg->ovl_en, BIT(0));
+	setbits32(&exdma2_reg->ovl_l_en, BIT(0));
+	setbits32(&blenders[0]->bld_l_en, BIT(0));
+}

From 193420fe0b25f31527a7b26d41e7ec98c40293c2 Mon Sep 17 00:00:00 2001
From: Yidi Lin <yidilin@google.com>
Date: Mon, 13 Oct 2025 11:35:39 +0800
Subject: [PATCH 2249/3886] soc/mediatek/common: Add bootsplash support

This change introduces support for displaying a bootsplash logo during
boot on Mediatek platforms.

A new `display_logo` function is added to render a logo from the CBFS
into the framebuffer. This function is called from `mtk_display_init` if
`BMP_LOGO` is enabled in the board's Kconfig.

Additionally, this change refactors the backlight configuration logic
into a new `panel_configure_backlight` helper function for better
clarity.

BUG=b:319511268
TEST=Verified on Hylia that the bootsplash logo is displayed correctly
during ramstage. Boot time increased by 562ms due to display
initialization.

Change-Id: Ibcfaa7d309eb4a0b14244b98c78a0dc32e6836e5
Signed-off-by: Yidi Lin <yidilin@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89543
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/soc/mediatek/common/display.c | 38 +++++++++++++++++++++++++++++--
 1 file changed, 36 insertions(+), 2 deletions(-)

diff --git a/src/soc/mediatek/common/display.c b/src/soc/mediatek/common/display.c
index 163b900769..109da29d59 100644
--- a/src/soc/mediatek/common/display.c
+++ b/src/soc/mediatek/common/display.c
@@ -1,5 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
+#include <assert.h>
+#include <bootsplash.h>
 #include <cbfs.h>
 #include <console/console.h>
 #include <delay.h>
@@ -64,6 +66,35 @@ static void process_panel_quirks(struct mtk_dp *mtk_dp,
 		mtk_dp->force_max_swing = true;
 }
 
+static void panel_configure_backlight(struct panel_description *panel,
+				      bool enable)
+{
+	assert(panel);
+
+	if (!panel->configure_backlight)
+		return;
+	panel->configure_backlight(enable);
+}
+
+static void display_logo(struct panel_description *panel,
+			 uintptr_t fb_addr,
+			 const struct edid *edid)
+{
+	memset((void *)fb_addr, 0, edid->bytes_per_line * edid->y_resolution);
+
+	struct logo_config config = {
+		.panel_orientation = panel->orientation,
+		.halignment = FW_SPLASH_HALIGNMENT_CENTER,
+		.valignment = FW_SPLASH_VALIGNMENT_CENTER,
+		.logo_bottom_margin = 100,
+	};
+	render_logo_to_framebuffer(&config);
+
+	mtk_ddp_ovlsys_start(fb_addr);
+
+	panel_configure_backlight(panel, true);
+}
+
 int mtk_display_init(void)
 {
 	struct edid edid = {0};
@@ -84,8 +115,8 @@ int mtk_display_init(void)
 	mtcmos_protect_display_bus();
 
 	/* Set up backlight control pins as output pin and turn-off the backlight */
-	if (panel->configure_backlight)
-		panel->configure_backlight(false);
+	panel_configure_backlight(panel, false);
+
 	if (panel->power_on)
 		panel->power_on();
 
@@ -152,5 +183,8 @@ int mtk_display_init(void)
 	if (info)
 		fb_set_orientation(info, panel->orientation);
 
+	if (CONFIG(BMP_LOGO))
+		display_logo(panel, fb_addr, &edid);
+
 	return 0;
 }

From 815f3f7df294aa6a713371edfdbdc29febf47ae8 Mon Sep 17 00:00:00 2001
From: Yidi Lin <yidilin@google.com>
Date: Mon, 13 Oct 2025 10:59:03 +0800
Subject: [PATCH 2250/3886] mb/google/rauru: Increase RW firmware sections size
 to 1756KB

The RW_A and RW_B firmware sections are increased by 256KB, from 1500K
to 1756K, to support larger firmware images. With bootsplash enabled,
the remaining space in these sections is approximately 15KB, which is
insufficient to hold the bootsplash assets. This increase provides the
necessary space. Additionally, with more features anticipated from the
payload (depthcharge), this extra space serves as a reserve to prevent
future build failures due to insufficient space.

The RW_LEGACY section is also adjusted to fill the remaining space.

WARNING: Please do NOT cherry-pick to rauru firmware branch.

BUG=b:450510630,b:319511268
TEST=emerge-rauru coreboot chromeos-bootimage (with BMP_LOGO enabled)

Change-Id: I70aaa9e7011b7f2376b7bc28caac27c0a86aa20a
Signed-off-by: Yidi Lin <yidilin@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89545
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
---
 src/mainboard/google/rauru/chromeos.fmd | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/src/mainboard/google/rauru/chromeos.fmd b/src/mainboard/google/rauru/chromeos.fmd
index abf673fa03..b0f3191ab4 100644
--- a/src/mainboard/google/rauru/chromeos.fmd
+++ b/src/mainboard/google/rauru/chromeos.fmd
@@ -22,7 +22,7 @@ FLASH 8M {
 		RO_GSCVD 8K
 		RO_VPD(PRESERVE) 32K  # At least 16K.
 	}
-	RW_SECTION_A 1500K {
+	RW_SECTION_A 1756K {
 		VBLOCK_A 8K
 		FW_MAIN_A(CBFS)
 		RW_FWID_A 0x100
@@ -33,7 +33,7 @@ FLASH 8M {
 		RW_MRC_CACHE(PRESERVE) 16K
 		RW_ELOG(PRESERVE) 4K  # ELOG driver hard-coded size in 4K.
 	}
-	RW_SECTION_B 1500K {
+	RW_SECTION_B 1756K {
 		VBLOCK_B 8K
 		FW_MAIN_B(CBFS)
 		RW_FWID_B 0x100
@@ -42,5 +42,5 @@ FLASH 8M {
 		SHARED_DATA 4K  # 4K or less for netboot params.
 		RW_UNUSED
 	}
-	RW_LEGACY(CBFS) 1M  # Minimal 1M.
+	RW_LEGACY(CBFS) 512K
 }

From f6b5e26fe7c694977b1607be30c29389913ed735 Mon Sep 17 00:00:00 2001
From: Yidi Lin <yidilin@google.com>
Date: Mon, 13 Oct 2025 11:31:58 +0800
Subject: [PATCH 2251/3886] soc/mediatek/mt8196: Add 24MB framebuffer region

Add framebuffer region to reserve 24MB for the boot logo feature.

BUG=b:319511268
TEST=The logo is shown in the ramstage.

Change-Id: I183651f7bd28de5551a15bd335bc2eed5f0804eb
Signed-off-by: Yidi Lin <yidilin@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89544
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
---
 src/soc/mediatek/mt8196/include/soc/memlayout.ld | 1 +
 1 file changed, 1 insertion(+)

diff --git a/src/soc/mediatek/mt8196/include/soc/memlayout.ld b/src/soc/mediatek/mt8196/include/soc/memlayout.ld
index ef6a146aeb..8c64d661db 100644
--- a/src/soc/mediatek/mt8196/include/soc/memlayout.ld
+++ b/src/soc/mediatek/mt8196/include/soc/memlayout.ld
@@ -73,4 +73,5 @@ SECTIONS
 	RESV_MEMORY_GPUEB(0xA0000000, 2M)
 	/* Reserved memory for the dedicated secured memory allocator of GPU Mali firmware */
 	GPU_SEC_BUF(0xA2000000, 16M)
+	FRAMEBUFFER(0xBEC00000, 24M)
 }

From 90d87c59414bb2eeb3e880da35c1e719db2aee83 Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Tue, 14 Oct 2025 20:42:23 +0100
Subject: [PATCH 2252/3886] mb/starlabs/starbook/*: Remove comments for unused
 GPIOs

Non-functional change that makes it easier to see what is actually
configured.

Change-Id: I2ffb11ef73a0b2c9e5236b2edb9ec187a045374c
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89582
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 .../starlabs/starbook/variants/adl/gpio.c     | 156 ------------------
 .../starlabs/starbook/variants/cml/gpio.c     | 102 ------------
 .../starlabs/starbook/variants/kbl/gpio.c     | 123 +-------------
 .../starlabs/starbook/variants/rpl/gpio.c     | 153 +----------------
 .../starlabs/starbook/variants/tgl/gpio.c     |   1 -
 5 files changed, 8 insertions(+), 527 deletions(-)

diff --git a/src/mainboard/starlabs/starbook/variants/adl/gpio.c b/src/mainboard/starlabs/starbook/variants/adl/gpio.c
index bdc0e14212..012dc923cf 100644
--- a/src/mainboard/starlabs/starbook/variants/adl/gpio.c
+++ b/src/mainboard/starlabs/starbook/variants/adl/gpio.c
@@ -92,91 +92,49 @@ const struct pad_config gpio_table[] = {
 	PAD_CFG_GPO(GPD7, 0, PWROK),					/* RTC Clock Delay	[ Disabled / 95ms     ] */
 
 
-	/* GPD2:	LAN Wake					*/
 	PAD_NC(GPD2, NONE),
-	/* GPD6:	Sleep A						*/
 	PAD_NC(GPD6, NONE),
-
-	/* GPD9:	Wireless LAN Sleep				*/
 	PAD_NC(GPD9, NONE),
-	/* GPD10:	Sleep S5					*/
 	PAD_NC(GPD10, NONE),
-	/* GPD11:	LAN PHY Enable					*/
 	PAD_NC(GPD11, NONE),
 
-	/* A5:		Not Connected					*/
 	PAD_NC(GPP_A5, NONE),
-	/* A6:		Not Connected					*/
 	PAD_NC(GPP_A6, NONE),
-	/* A7:		Embedded Controller SCI				*/
 	PAD_NC(GPP_A7, NONE),
-	/* A8:		Not Connected					*/
 	PAD_NC(GPP_A8, NONE),
-	/* A11:		Not Connected					*/
 	PAD_NC(GPP_A11, NONE),
 	/* A12:		PCH M.2 SSD PEDET				*/
 	PAD_CFG_NF(GPP_A12, NONE, DEEP, NF1),
-	/* A14:		Test Point 45					*/
 	PAD_NC(GPP_A14, NONE),
-	/* A15:		Test Point 52					*/
 	PAD_NC(GPP_A15, NONE),
-	/* A16:		USB OverCurrent 3				*/
 	PAD_NC(GPP_A16, NONE),
-	/* A17:		Not Connected					*/
 	PAD_NC(GPP_A17, NONE),
-	/* A20:		Test Point 44					*/
 	PAD_NC(GPP_A20, NONE),
-	/* A21:		Fingerprint Reader Interrupt			*/
 	PAD_NC(GPP_A21, NONE),
-	/* A22:		Fingerprint Reader Reset			*/
 	PAD_NC(GPP_A22, NONE),
-	/* A23:		Not Connected					*/
 	PAD_NC(GPP_A23, NONE),
 
-	/* B3:		Not Connected					*/
 	PAD_NC(GPP_B3, NONE),
-	/* B4:		Not Connected					*/
 	PAD_NC(GPP_B4, NONE),
-	/* B5:		I2C 2 SDA		Touch Panel SDA		*/
 	PAD_NC(GPP_B5, NONE),
-	/* B6:		I2C 2 SCL		Touch Panel Clock	*/
 	PAD_NC(GPP_B6, NONE),
-	/* B7:		I2C 3 SDA		Test Point 15		*/
 	PAD_NC(GPP_B7, NONE),
-	/* B8:		I2C 3 SCL		Test Point 16		*/
 	PAD_NC(GPP_B8, NONE),
-	/* B9:		Not Connected					*/
 	PAD_NC(GPP_B9, NONE),
-	/* B10:		Not Connected					*/
 	PAD_NC(GPP_B10, NONE),
-	/* B11:		I2C PMC PD Interrupt	Test Point 28		*/
 	PAD_NC(GPP_B11, NONE),
-	/* B12:		PM SLP S0					*/
 	PAD_NC(GPP_B12, NONE),
-
-	/* B15:		Not Connected					*/
 	PAD_NC(GPP_B15, NONE),
-	/* B16:		Not Connected					*/
 	PAD_NC(GPP_B16, NONE),
-	/* B17:		Not Connected					*/
 	PAD_NC(GPP_B17, NONE),
-
-	/* B19:		Not Connected					*/
 	PAD_NC(GPP_B19, NONE),
-	/* B20:		Not Connected					*/
 	PAD_NC(GPP_B20, NONE),
-	/* B21:		Not Connected					*/
 	PAD_NC(GPP_B21, NONE),
-	/* B22:		Not Connected					*/
 	PAD_NC(GPP_B22, NONE),
-	/* B23:		Not used	MiPi Camera			*/
 	PAD_NC(GPP_B23, NONE),
-	/* B24:		Not Connected					*/
 	PAD_NC(GPP_B24, NONE),
-	/* B25:		Not Connected					*/
 	PAD_NC(GPP_B25, NONE),
 
-
 	/* C3:		SML 0 Clock					*/
 	PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1),
 	/* C4:		SML 0 Data					*/
@@ -186,243 +144,129 @@ const struct pad_config gpio_table[] = {
 	PAD_CFG_NF(GPP_C6, NONE, DEEP, NF1),
 	/* C7:		SML 1 Data					*/
 	PAD_CFG_NF(GPP_C7, NONE, DEEP, NF1),
-	/* C8:		Not Connected					*/
 	PAD_NC(GPP_C8, NONE),
-	/* C9:		Not Connected					*/
 	PAD_NC(GPP_C9, NONE),
-	/* C10:		Not Connected					*/
 	PAD_NC(GPP_C10, NONE),
-	/* C11:		Not Connected					*/
 	PAD_NC(GPP_C11, NONE),
-	/* C12:		Not Connected					*/
 	PAD_NC(GPP_C12, NONE),
-	/* C13:		Not Connected					*/
 	PAD_NC(GPP_C13, NONE),
-	/* C14:		Not Connected					*/
 	PAD_NC(GPP_C14, NONE),
-	/* C15:		Not Connected					*/
 	PAD_NC(GPP_C15, NONE),
-	/* C16:		Not Connected					*/
 	PAD_NC(GPP_C16, NONE),
-	/* C17:		Not Connected					*/
 	PAD_NC(GPP_C17, NONE),
-	/* C18:		Not Connected					*/
 	PAD_NC(GPP_C18, NONE),
-	/* C19:		Not Connected					*/
 	PAD_NC(GPP_C19, NONE),
-	/* C20:		Not Connected					*/
 	PAD_NC(GPP_C20, NONE),
-	/* C21:		Not Connected					*/
 	PAD_NC(GPP_C21, NONE),
-	/* C22:		Not Connected					*/
 	PAD_NC(GPP_C22, NONE),
-	/* C23:		Not Connected					*/
 	PAD_NC(GPP_C23, NONE),
 
-	/* D0:		Not used		Audio ID 0		*/
 	PAD_NC(GPP_D0, NONE),
-	/* D1:		Not used		Audio ID 1		*/
 	PAD_NC(GPP_D1, NONE),
-	/* D2:		Not used		Audio ID 2		*/
 	PAD_NC(GPP_D2, NONE),
-	/* D3:		Not Connected					*/
 	PAD_NC(GPP_D3, NONE),
-	/* D4:		Not Connected					*/
 	PAD_NC(GPP_D4, NONE),
-	/* D5:		Clock Request 0					*/
 	PAD_NC(GPP_D5, NONE),
-	/* D8:		Clock Request 3		LAN			*/
 	PAD_NC(GPP_D8, NONE),
-	/* D9:		GSPI 2 FPS					*/
 	PAD_NC(GPP_D9, NONE),
-	/* D10:		GSPI 2 Clock					*/
 	PAD_NC(GPP_D10, NONE),
-	/* D11:		GSPI 2 MISO FPS					*/
 	PAD_NC(GPP_D11, NONE),
-	/* D12:		GSPI 2 MOSI FPS					*/
 	PAD_NC(GPP_D12, NONE),
-	/* D13:		Wireless LAN Wake				*/
 	PAD_NC(GPP_D13, NONE),
-	/* D14:		CPU M.2 SSD Power Enable			*/
 	PAD_NC(GPP_D14, NONE),
-	/* D15:		Not Connected					*/
 	PAD_NC(GPP_D15, NONE),
-	/* D17:		Not used		Fingerprint ID		*/
 	PAD_NC(GPP_D17, NONE),
-	/* D18:		Not Connected					*/
 	PAD_NC(GPP_D18, NONE),
-	/* D19:		Test Point 21					*/
 	PAD_NC(GPP_D19, NONE),
 
-	/* E0:		SATA x PCIe					*/
 	PAD_NC(GPP_E0, NONE),
-	/* E1:		Not used		Accelerometer Interrupt	*/
 	PAD_NC(GPP_E1, NONE),
-	/* E2:		Not Connected					*/
 	PAD_NC(GPP_E2, NONE),
-	/* E4:		Test Point 14					*/
 	PAD_NC(GPP_E4, NONE),
-	/* E5:		Not Connected					*/
 	PAD_NC(GPP_E5, NONE),
-
-	/* E7:		Embedded Controller SMI				*/
 	PAD_NC(GPP_E7, NONE),
-	/* E9:		USB OverCurrent 0				*/
 	PAD_NC(GPP_E9, NONE),
-	/* E10:		PWD Amplifier Input				*/
 	PAD_NC(GPP_E10, NONE),
-	/* E13:		Not connected					*/
 	PAD_NC(GPP_E13, NONE),
-	/* E15:		Not Connected					*/
 	PAD_NC(GPP_E15, NONE),
-	/* E16:		Not Connected					*/
 	PAD_NC(GPP_E16, NONE),
-	/* E17:		Not Connected					*/
 	PAD_NC(GPP_E17, NONE),
-	/* E18:		Not Connected					*/
 	PAD_NC(GPP_E18, NONE),
-
-	/* E20:		Not Connected					*/
 	PAD_NC(GPP_E20, NONE),
-	/* E21:		Not Connected					*/
 	PAD_NC(GPP_E21, NONE),
-	/* E22:		Not Connected					*/
 	PAD_NC(GPP_E22, NONE),
-	/* E23:		Not Connected					*/
 	PAD_NC(GPP_E23, NONE),
 
-	/* F0:		CNV BRI Data					*/
 	PAD_NC(GPP_F0, NONE),
-	/* F1:		CNV BRI Response				*/
 	PAD_NC(GPP_F1, NONE),
-
-	/* F3:		CNV RGI Response				*/
 	PAD_NC(GPP_F3, NONE),
-	/* F4:		CNV RF Reset					*/
 	PAD_NC(GPP_F4, NONE),
-	/* F5:		Not used		MODEM_CLKREQ		*/
 	PAD_NC(GPP_F5, NONE),
-	/* F6:		CNV PA Blanking					*/
 	PAD_NC(GPP_F6, NONE),
 
-	/* F8:		Not Connected					*/
 	PAD_NC(GPP_F8, NONE),
-	/* F9:		EC Sleep S0					*/
 	PAD_NC(GPP_F9, NONE),
 	/* F10:		Weak Internal PD 20K				*/
 	PAD_CFG_GPO(GPP_F10, 0, DEEP),
-	/* F11:		TPM ID						*/
 	PAD_NC(GPP_F11, NONE),
-	/* F12:		Not Connected					*/
 	PAD_NC(GPP_F12, NONE),
-	/* F13:		Not Connected					*/
 	PAD_NC(GPP_F13, NONE),
-	/* F14:		Not Connected					*/
 	PAD_NC(GPP_F14, NONE),
-	/* F15:		Not used		Accelerometer Interrupt 2*/
 	PAD_NC(GPP_F15, NONE),
-	/* F16:		Not Connected					*/
 	PAD_NC(GPP_F16, NONE),
-	/* F17:		Not used		Touch Panel Reset	*/
 	PAD_NC(GPP_F17, NONE),
-	/* F18:		Not used		Touch Panel Interrupt	*/
 	PAD_NC(GPP_F18, NONE),
-	/* F19:		Not Connected					*/
 	PAD_NC(GPP_F19, NONE),
-	/* F20:		CPU M.2 SSD Reset				*/
 	PAD_NC(GPP_F20, NONE),
-	/* F21:		GPPC_F21					*/
 	PAD_NC(GPP_F21, NONE),
-	/* F22:		Not Connected					*/
 	PAD_NC(GPP_F22, NONE),
-	/* F23:		Not Connected					*/
 	PAD_NC(GPP_F23, NONE),
 
 
-	/* H3:		Not Connected					*/
 	PAD_NC(GPP_H3, NONE),
-	/* H6:		Not Connected					*/
 	PAD_NC(GPP_H6, NONE),
-	/* H7:		Not Connected					*/
 	PAD_NC(GPP_H7, NONE),
-	/* H8:		I2C 4 SDA		GSensor			*/
 	PAD_NC(GPP_H8, NONE),
-	/* H9:		I2C 4 SDL		GSensor			*/
 	PAD_NC(GPP_H9, NONE),
-	/* H12:		Not Connected					*/
 	PAD_NC(GPP_H12, NONE),
 	/* H13:		PCH M.2 SSD Device Sleep			*/
 	PAD_CFG_NF(GPP_H13, NONE, DEEP, NF5),
-	/* H14:		Not Connected					*/
 	PAD_NC(GPP_H14, NONE),
-	/* H16:		Not Connected					*/
 	PAD_NC(GPP_H16, NONE),
-	/* H19:		Clock Request 4		CPU M.2 SSD		*/
 	PAD_NC(GPP_H19, NONE),
-	/* H20:		Not Connected					*/
 	PAD_NC(GPP_H20, NONE),
-	/* H21:		Not Connected					*/
 	PAD_NC(GPP_H21, NONE),
-	/* H22:		Not Connected					*/
 	PAD_NC(GPP_H22, NONE),
-	/* H23:		Clock Request 5					*/
 	PAD_NC(GPP_H23, NONE),
 
-	/* S0:		Not Connected					*/
 	PAD_NC(GPP_S0, NONE),
-	/* S1:		Not Connected					*/
 	PAD_NC(GPP_S1, NONE),
-	/* S2:		DMIC Clock					*/
 	PAD_NC(GPP_S2, NONE),
-	/* S3:		DMIC Data					*/
 	PAD_NC(GPP_S3, NONE),
-	/* S4:		Not Connected					*/
 	PAD_NC(GPP_S4, NONE),
-	/* S5:		Not Connected					*/
 	PAD_NC(GPP_S5, NONE),
-	/* S6:		Not Connected					*/
 	PAD_NC(GPP_S6, NONE),
-	/* S7:		Not Connected					*/
 	PAD_NC(GPP_S7, NONE),
 
-	/* T0:		 Not Connected					*/
 	PAD_NC(GPP_T0, NONE),
-	/* T1:		 Not Connected					*/
 	PAD_NC(GPP_T1, NONE),
-	/* T2:		 Not Connected					*/
 	PAD_NC(GPP_T2, NONE),
-	/* T3:		 Not Connected					*/
 	PAD_NC(GPP_T3, NONE),
-	/* T4:		 Not Connected					*/
 	PAD_NC(GPP_T4, NONE),
-	/* T5:		 Not Connected					*/
 	PAD_NC(GPP_T5, NONE),
-	/* T6:		 Not Connected					*/
 	PAD_NC(GPP_T6, NONE),
-	/* T7:		 Not Connected					*/
 	PAD_NC(GPP_T7, NONE),
-	/* T8:		 Not Connected					*/
 	PAD_NC(GPP_T8, NONE),
-	/* T9:		 Not Connected					*/
 	PAD_NC(GPP_T9, NONE),
-	/* T10:		 Not Connected					*/
 	PAD_NC(GPP_T10, NONE),
-	/* T11:		 Not Connected					*/
 	PAD_NC(GPP_T11, NONE),
-	/* T12:		 Not Connected					*/
 	PAD_NC(GPP_T12, NONE),
-	/* T13:		 Not Connected					*/
 	PAD_NC(GPP_T13, NONE),
-	/* T14:		 Not Connected					*/
 	PAD_NC(GPP_T14, NONE),
-	/* T15:		 Not Connected					*/
 	PAD_NC(GPP_T15, NONE),
 
-	/* R5:		MiPi Cam Reset				*/
 	PAD_NC(GPP_R5, NONE),
-	/* R6:		Not Connected				*/
 	PAD_NC(GPP_R6, NONE),
-	/* R7:		Not Connected				*/
 	PAD_NC(GPP_R7, NONE),
 };
 
diff --git a/src/mainboard/starlabs/starbook/variants/cml/gpio.c b/src/mainboard/starlabs/starbook/variants/cml/gpio.c
index a844562817..601b273036 100644
--- a/src/mainboard/starlabs/starbook/variants/cml/gpio.c
+++ b/src/mainboard/starlabs/starbook/variants/cml/gpio.c
@@ -67,7 +67,6 @@ const struct pad_config gpio_table[] = {
 	PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1),				/* Clock */
 	PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1),				/* Data */
 
-	/* GPD2:	LAN_WAKE#		*/
 	PAD_NC(GPD2, NONE),
 	/* GPD6:	SIO_SLP_A#		*/
 	PAD_CFG_NF(GPD6, NONE, DEEP, NF1),
@@ -94,17 +93,13 @@ const struct pad_config gpio_table[] = {
 	PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1),
 	/* A6:	LPC_SERIRQ			*/
 	PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1),
-	/* A7:	Not Connected			*/
 	PAD_NC(GPP_A7, NONE),
 	/* A8:	 GPPC_A8_CLKRUN_N		*/
 	PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1),
 	/* A9:	 ESPI_CLK			*/
 	PAD_CFG_NF(GPP_A9, DN_20K, DEEP, NF1),
-	/* A10:	Not Connected			*/
 	PAD_NC(GPP_A10, NONE),
-	/* A11:	Not Connected			*/
 	PAD_NC(GPP_A11, NONE),
-	/* A12:	 TABLET_MODE_CTRL		*/
 	PAD_NC(GPP_A12, NONE),
 	/* A13:	 SUSPWRDNACK			*/
 	PAD_CFG_GPO(GPP_A13, 1, PLTRST),
@@ -112,38 +107,24 @@ const struct pad_config gpio_table[] = {
 	PAD_CFG_NF(GPP_A14, NONE, DEEP, NF1),
 	/* A15:	 SPK_PD_N			*/
 	PAD_CFG_GPO(GPP_A15, 1, PLTRST),
-	/* A16:	Not Connected			*/
 	PAD_NC(GPP_A16, NONE),
-	/* A17:	 SAR_DPR_PCH			*/
 	PAD_NC(GPP_A17, NONE),
-	/* A18:	 ACCEL1_INT1			*/
 	PAD_NC(GPP_A18, UP_20K),
-	/* A19:	 ACCEL2_INT1			*/
 	PAD_NC(GPP_A19, UP_20K),
-	/* A20:	 HUMAN_PRESENCE_INT_N		*/
 	PAD_NC(GPP_A20, UP_20K),
-	/* A21:	 HALL_SENSOR_INT		*/
 	PAD_NC(GPP_A21, UP_20K),
-	/* A22:	 SAR_NIRQ_PCH			*/
 	PAD_NC(GPP_A22, UP_20K),
-	/* A23:	 INT_SHARED			*/
 	PAD_NC(GPP_A23, UP_20K),
 
-	/* B0:	Not Connected			*/
 	PAD_NC(GPP_B0, NONE),
-	/* B1:	Not Connected			*/
 	PAD_NC(GPP_B1, NONE),
-	/* B2:	Not Connected			*/
 	PAD_NC(GPP_B2, NONE),
 	/* B5:	WLAN_CLKREQ#			*/
 	PAD_CFG_NF(GPP_B5, NONE, DEEP, NF1),
 	/* B7:	 LAN_CLKREQ#			*/
 	PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1),
-	/* B8:	Not Connected			*/
 	PAD_NC(GPP_B8, NONE),
-	/* B9:	Not Connected			*/
 	PAD_NC(GPP_B9, NONE),
-	/* B10:	Not Connected			*/
 	PAD_NC(GPP_B10, NONE),
 	/* B11:	 EXT_PWR_GATE_N			*/
 	PAD_CFG_GPO(GPP_B11, 1, PLTRST),
@@ -151,7 +132,6 @@ const struct pad_config gpio_table[] = {
 	PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1),
 	/* B14:	 TCH_PNL_PWR_EN			*/
 	PAD_CFG_GPO(GPP_B14, 1, PLTRST),
-	/* B15:	Not Connected			*/
 	PAD_NC(GPP_B15, NONE),
 	/* B16:	 FPS_INT			*/
 	PAD_CFG_GPI_APIC(GPP_B16, NONE, PLTRST, LEVEL, NONE),
@@ -159,75 +139,46 @@ const struct pad_config gpio_table[] = {
 	PAD_CFG_GPO(GPP_B17, 1, PLTRST),
 	/* B18:	 AR_CIO_PWR_EN			*/
 	PAD_CFG_GPO(GPP_B18, 0, DEEP),
-	/* B19:	 GSPI1_CS0_FPS_N		*/
 	PAD_NC(GPP_B19, NONE),
-	/* B20:	 GSPI1_CLK_FPS			*/
 	PAD_NC(GPP_B20, NONE),
-	/* B21:	 GSPI1_MISO_FPS			*/
 	PAD_NC(GPP_B21, NONE),
 	/* B22:	 GSPI1_MOSI_FPS			*/
 	PAD_CFG_GPO(GPP_B22, 0, DEEP),
-	/* B23:	 EC_SLP_S0IX_N			*/
 	PAD_NC(GPP_B23, NONE),
 
-	/* C3:	Not Connected			*/
 	PAD_NC(GPP_C3, NONE),
-	/* C4:	Not Connected			*/
 	PAD_NC(GPP_C4, NONE),
 	/* C5:	 SML0ALERT			*/
 	PAD_CFG_GPO(GPP_C5, 0, DEEP),
-	/* C6:	Not Connected			*/
 	PAD_NC(GPP_C6, NONE),
-	/* C7:	Not Connected			*/
 	PAD_NC(GPP_C7, NONE),
 	/* C8:	 CODEC_INT_N			*/
 	PAD_CFG_GPI_APIC_LOW(GPP_C8, UP_20K, PLTRST),
-	/* C9:	Not Connected			*/
 	PAD_NC(GPP_C9, NONE),
-	/* C10:	Not Connected			*/
 	PAD_NC(GPP_C10, NONE),
-	/* C11:	Not Connected			*/
 	PAD_NC(GPP_C11, NONE),
 	/* C12:	 PCIE_NAND_RST_R_N		*/
 	PAD_CFG_GPO(GPP_C12, 1, PLTRST),
-	/* C13:	 M2_SSD_PWREN			*/
 	PAD_NC(GPP_C13, NONE),
-	/* C14:	 TBT_WAKE_MUX_SEL_N		*/
 	PAD_NC(GPP_C14, NONE),
-	/* C15:	 TBT_RST_N			*/
 	PAD_NC(GPP_C15, NONE),
-	/* C18:	 TOUCH_I2C_SDA			*/
 	PAD_NC(GPP_C18, NONE),
-	/* C19:	 TOUCH_I2C_SDL			*/
 	PAD_NC(GPP_C19, NONE),
-	/* C22:	 AR1_USB_PWR_EN			*/
 	PAD_NC(GPP_C22, NONE),
-	/* C23:	Not Connected			*/
 	PAD_NC(GPP_C23, NONE),
 
-	/* D0:	 TPM_IRQ			*/
 	PAD_NC(GPP_D0, NONE),
-	/* D1:	Not Connected			*/
 	PAD_NC(GPP_D1, NONE),
-	/* D2:	Not Connected			*/
 	PAD_NC(GPP_D2, NONE),
-	/* D3:	Not Connected			*/
 	PAD_NC(GPP_D3, NONE),
-	/* D4:	Not Connected			*/
 	PAD_NC(GPP_D4, NONE),
-	/* D5:	Not Connected			*/
 	PAD_NC(GPP_D5, NONE),
-	/* D6:	Not Connected			*/
 	PAD_NC(GPP_D6, NONE),
-	/* D7:	 ISH_I2C1_SDA			*/
 	PAD_NC(GPP_D7, NONE),
-	/* D8:	 ISH_I2C1_SDL			*/
 	PAD_NC(GPP_D8, NONE),
 	/* D9:	 TCH_PNL2_RST_R_N		*/
 	PAD_CFG_GPO(GPP_D9, 1, PLTRST),
-	/* D10:	 TCH_PNL2_INT_R_N		*/
 	PAD_NC(GPP_D10, NATIVE),
-	/* D11:	Not Connected			*/
 	PAD_NC(GPP_D11, NATIVE),
 	/* D12:	 GPPC_D_12			*/
 	PAD_CFG_GPO(GPP_D12, 0, DEEP),
@@ -235,7 +186,6 @@ const struct pad_config gpio_table[] = {
 	PAD_NC(GPP_D13, NONE),
 	/* D14:	 TCH_PNL1_RST_N			*/
 	PAD_CFG_GPO(GPP_D14, 1, PLTRST),
-	/* D15:	Not Connected			*/
 	PAD_NC(GPP_D15, NONE),
 	/* D16:	 GPIO_2_EC			*/
 	PAD_CFG_GPO(GPP_D16, 0, PWROK),
@@ -247,30 +197,19 @@ const struct pad_config gpio_table[] = {
 	PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1),
 	/* D20:	 DMIC_DATA_0			*/
 	PAD_CFG_NF(GPP_D20, NONE, DEEP, NF1),
-	/* D21:	Not Connected			*/
 	PAD_NC(GPP_D21, NONE),
-	/* D22:	 TPM_RST			*/
 	PAD_NC(GPP_D22, NONE),
-	/* D23:	 TPM_IRQ			*/
 	PAD_NC(GPP_D23, NONE),
 
-	/* E0:	Not Connected			*/
 	PAD_NC(GPP_E0, NONE),
 	/* E1:	 GPPC_E1_SATAXPCIE_1_SATAGP_1	*/
 	PAD_CFG_NF(GPP_E1, UP_20K, DEEP, NF1),
-	/* E2:	Not Connected			*/
 	PAD_NC(GPP_E2, NONE),
-	/* E3:	Not Connected			*/
 	PAD_NC(GPP_E3, NONE),
-	/* E4:	Not Connected			*/
 	PAD_NC(GPP_E4, NONE),
-	/* E5:	 GPPC_E5_SATA_DEVSLP_1		*/
 	PAD_NC(GPP_E5, NONE),
-	/* E6:	Not Connected			*/
 	PAD_NC(GPP_E6, NONE),
-	/* E7:	Not Connected			*/
 	PAD_CFG_GPI(GPP_E7, NONE, PLTRST),
-	/* E8:	Not Connected			*/
 	PAD_NC(GPP_E8, NONE),
 	/* E9:	 GPPC_E9_USB2_OCB_0		*/
 	PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1),
@@ -289,99 +228,58 @@ const struct pad_config gpio_table[] = {
 	/* E21:	 DDI2_CTRL_DATA			*/
 	PAD_CFG_NF(GPP_E21, NONE, DEEP, NF1),
 
-	/* F0:	Not Connected			*/
 	PAD_NC(GPP_F0, NONE),
-	/* F1:	Not Connected			*/
 	PAD_NC(GPP_F1, NONE),
-	/* F2:	Not Connected			*/
 	PAD_NC(GPP_F2, NONE),
-	/* F3:	Not Connected			*/
 	PAD_NC(GPP_F3, NONE),
-	/* F8:	Not Connected			*/
 	PAD_NC(GPP_F8, NONE),
-	/* F9:	Not Connected			*/
 	PAD_NC(GPP_F9, NONE),
-	/* F10:	Not Connected			*/
 	PAD_NC(GPP_F10, NONE),
-	/* F11:	EMMC_CMD			*/
 	PAD_NC(GPP_F11, NONE),
-	/* F12:	EMMC_DATA_0			*/
 	PAD_NC(GPP_F12, NONE),
-	/* F13:	EMMC_DATA_1			*/
 	PAD_NC(GPP_F13, NONE),
-	/* F14:	EMMC_DATA_2			*/
 	PAD_NC(GPP_F14, NONE),
-	/* F15:	EMMC_DATA_3			*/
 	PAD_NC(GPP_F15, NONE),
-	/* F16:	EMMC_DATA_4			*/
 	PAD_NC(GPP_F16, NONE),
-	/* F17:	EMMC_DATA_5			*/
 	PAD_NC(GPP_F17, NONE),
-	/* F18:	EMMC_DATA_6			*/
 	PAD_NC(GPP_F18, NONE),
-	/* F19:	EMMC_DATA_7			*/
 	PAD_NC(GPP_F19, NONE),
-	/* F20:	EMMC_STROBE			*/
 	PAD_NC(GPP_F20, NONE),
-	/* F21:	EMMC_CLK			*/
 	PAD_NC(GPP_F21, NONE),
-	/* F22:	EMMC_RESETB			*/
 	PAD_NC(GPP_F22, NONE),
 	/* F23:	A4WP_PRESENT			*/
 	PAD_CFG_NF(GPP_F23, DN_20K, DEEP, NF1),
 
-	/* G0:	Not Connected			*/
 	PAD_NC(GPP_G0, NONE),
-	/* G1:	Not Connected			*/
 	PAD_NC(GPP_G1, NONE),
-	/* G2:	Not Connected			*/
 	PAD_NC(GPP_G2, NONE),
-	/* G3:	Not Connected			*/
 	PAD_NC(GPP_G3, NONE),
-	/* G4:	Not Connected			*/
 	PAD_NC(GPP_G4, NONE),
-	/* G5:	Not Connected			*/
 	PAD_NC(GPP_G5, UP_20K),
-	/* G6:	Not Connected			*/
 	PAD_NC(GPP_G6, NONE),
-	/* G7:	Not Connected			*/
 	PAD_NC(GPP_G7, DN_20K),
 
-	/* H0:	Not Connected			*/
 	PAD_NC(GPP_H0, NONE),
-	/* H3:	Not Connected			*/
 	PAD_NC(GPP_H3, UP_20K),
-	/* H4:	 GSENSOR_I2C_SDA		*/
 	PAD_NC(GPP_H4, NONE),
-	/* H5:	 GSENSOR_I2C_SCL		*/
 	PAD_NC(GPP_H5, NONE),
-	/* H8:	Not Connected			*/
 	PAD_NC(GPP_H8, NONE),
-	/* H9:	Not Connected			*/
 	PAD_NC(GPP_H9, NONE),
 	/* H10:	 ISH_I2C2_SDA			*/
 	PAD_CFG_GPO(GPP_H10, 1, PLTRST),
 	/* H11:	 ISH_I2C2_SCL			*/
 	PAD_CFG_GPO(GPP_H11, 1, PLTRST),
-	/* H12:	Not Connected			*/
 	PAD_NC(GPP_H12, NONE),
-	/* H13:	Not Connected			*/
 	PAD_NC(GPP_H13, NONE),
-	/* H14:	Not Connected			*/
 	PAD_NC(GPP_H14, NONE),
-	/* H15:	Not Connected			*/
 	PAD_NC(GPP_H15, NONE),
-	/* H16:	Not Connected			*/
 	PAD_NC(GPP_H16, NONE),
 	/* H17:	 GPPC_H_17_WWAN_DISABLE_N	*/
 	PAD_CFG_GPO(GPP_H17, 0, DEEP),
-	/* H19:	Not Connected			*/
 	PAD_NC(GPP_H19, NONE),
-	/* H20:	Not Connected			*/
 	PAD_NC(GPP_H20, NONE),
 	/* H21:	 GPPC_H21			*/
 	PAD_CFG_GPO(GPP_H21, 0, DEEP),
-	/* H22:	Not Connected			*/
 	PAD_NC(GPP_H22, NONE),
 	/* H23:	 GPPC_H23			*/
 	PAD_CFG_GPO(GPP_H23, 0, DEEP),
diff --git a/src/mainboard/starlabs/starbook/variants/kbl/gpio.c b/src/mainboard/starlabs/starbook/variants/kbl/gpio.c
index cdc34ae46f..03d8ffcc9b 100644
--- a/src/mainboard/starlabs/starbook/variants/kbl/gpio.c
+++ b/src/mainboard/starlabs/starbook/variants/kbl/gpio.c
@@ -51,19 +51,13 @@ const struct pad_config gpio_table[] = {
 	PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1),				/* Clock */
 	PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1),				/* Data */
 
-	/* GPD2:	Not Connected		*/
 	PAD_NC(GPD2, NONE),
-	/* GPD6:	Not Connected		*/
 	PAD_NC(GPD6, NONE),
-	/* GPD7:	Not Connected		*/
 	PAD_NC(GPD7, NONE),
-	/* GPD9:	Not Connected		*/
 	PAD_NC(GPD9, NONE),
-	/* GPD10:	Not Connected		*/
 	PAD_NC(GPD10, NONE),
-	/* GPD11:	Not Connected		*/
 	PAD_NC(GPD11, NONE),
-	/* GPP_A0:	KBRST_N			*/
+
 	PAD_NC(GPP_A0, NONE),
 	/* GPP_A1:	LDC_AD0			*/
 	PAD_CFG_NF(GPP_A1, NONE, DEEP, NF1),
@@ -77,47 +71,30 @@ const struct pad_config gpio_table[] = {
 	PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1),
 	/* GPP_A6:	LPC_SERIRQ		*/
 	PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1),
-	/* GPP_A7:	Not Connected		*/
 	PAD_NC(GPP_A7, NONE),
 	/* GPP_A8:	PM_CLKRUN_N		*/
 	PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1),
 	/* GPP_A9:	LPC_CLK_EC		*/
 	PAD_CFG_NF(GPP_A9, DN_20K, DEEP, NF1),
-	/* GPP_A10:	LPC_CLK_Debug		*/
 	PAD_NC(GPP_A10, DN_20K),
 	/* GPP_A11:	PME_N			*/
 	PAD_CFG_GPI(GPP_A11, DN_20K, DEEP),
-	/* GPP_A12:	Not Connected		*/
 	PAD_NC(GPP_A12, NONE),
-	/* GPP_A13:	SUSPWRDNACK		*/
 	PAD_NC(GPP_A13, DN_20K),
-	/* GPP_A14:	PM_SUS_STAT_N		*/
 	PAD_NC(GPP_A14, DN_20K),
-	/* GPP_A15:	SUSACK#			*/
 	PAD_NC(GPP_A15, DN_20K),
-	/* GPP_A16:	Not Connected		*/
 	PAD_NC(GPP_A16, DN_20K),
-	/* GPP_A17:	Not Connected		*/
 	PAD_NC(GPP_A17, DN_20K),
-	/* GPP_A18:	Not Connected		*/
 	PAD_NC(GPP_A18, DN_20K),
-	/* GPP_A19:	Not Connected		*/
 	PAD_NC(GPP_A19, DN_20K),
-	/* GPP_A20:	Not Connected		*/
 	PAD_NC(GPP_A20, NONE),
-	/* GPP_A21:	Not Connected		*/
 	PAD_NC(GPP_A21, DN_20K),
-	/* GPP_A22:	FP_SSP0_INT		*/
 	PAD_NC(GPP_A22, DN_20K),
-	/* GPP_A23:	FP_SSP0_RST		*/
 	PAD_NC(GPP_A23, DN_20K),
-	/* GPP_B0:	Not Connected		*/
+
 	PAD_NC(GPP_B0, DN_20K),
-	/* GPP_B1:	Not Connected		*/
 	PAD_NC(GPP_B1, DN_20K),
-	/* GPP_B2:	+V3P3A_PCH		*/
 	PAD_NC(GPP_B2, DN_20K),
-	/* GPP_B3:	Not Connected		*/
 	PAD_NC(GPP_B3, DN_20K),
 	/* GPP_B5:	SRCCLKREQ0#		*/
 	PAD_CFG_NF(GPP_B5, NONE, DEEP, NF1),
@@ -129,41 +106,24 @@ const struct pad_config gpio_table[] = {
 	PAD_CFG_NF(GPP_B8, DN_20K, DEEP, NF1),
 	/* GPP_B9:	WLAN_CLKREQ#		*/
 	PAD_CFG_NF(GPP_B9, NONE, DEEP, NF1),
-	/* GPP_B11:	Not Connected		*/
 	PAD_NC(GPP_B11, DN_20K),
-	/* GPP_B12	SLP_S0_N		*/
 	PAD_NC(GPP_B12, DN_20K),
-	/* GPP_B14:	HDA_SPKR		*/
 	PAD_NC(GPP_B14, DN_20K),
-	/* GPP_B15:	Not Connected		*/
 	PAD_NC(GPP_B15, DN_20K),
-	/* GPP_B16:	Not Connected		*/
 	PAD_NC(GPP_B16, DN_20K),
-	/* GPP_B17:	Not Connected		*/
 	PAD_NC(GPP_B17, DN_20K),
-	/* GPP_B18:	+V3P3A_PCH		*/
 	PAD_NC(GPP_B18, DN_20K),
-	/* GPP_B19:	FP_SSP0_CS		*/
 	PAD_NC(GPP_B19, DN_20K),
-	/* GPP_B20:	FP_SSP0_CLK		*/
 	PAD_NC(GPP_B20, DN_20K),
-	/* GPP_21:	FP_SSP0_MISO		*/
 	PAD_NC(GPP_B21, DN_20K),
-	/* GPP_22:	FP_SSP0_MOSI		*/
 	PAD_NC(GPP_B22, DN_20K),
-	/* GPP_B23:	SML1ALERT#/PCHHOT#	*/
 	PAD_NC(GPP_B23, DN_20K),
-	/* GPP_C2:	SMBALERT#		*/
+
 	PAD_NC(GPP_C2, DN_20K),
-	/* GPP_C3:	SML0CLK			*/
 	PAD_NC(GPP_C3, DN_20K),
-	/* GPP_C4:	SML0DATA		*/
 	PAD_NC(GPP_C4, DN_20K),
-	/* GPP_C5:	SML0ALERT#		*/
 	PAD_NC(GPP_C5, DN_20K),
-	/* GPP_C6:	SML1CLK			*/
 	PAD_NC(GPP_C6, DN_20K),
-	/* GPP_C7:	SML1DATA		*/
 	PAD_NC(GPP_C7, DN_20K),
 	/* GPP_C8:	UART0_RXD		*/
 	PAD_CFG_NF(GPP_C8, UP_20K, DEEP, NF1),
@@ -173,83 +133,49 @@ const struct pad_config gpio_table[] = {
 	PAD_CFG_NF(GPP_C10, NONE, DEEP, NF1),
 	/* GPP_C11:	UART0_CTS#		*/
 	PAD_CFG_NF(GPP_C11, UP_20K, DEEP, NF1),
-	/* GPP_C12:	Not Connected		*/
 	PAD_NC(GPP_C12, UP_20K),
-	/* GPP_C13:	Not Connected		*/
 	PAD_NC(GPP_C13, UP_20K),
-	/* GPP_C14:	Not Connected		*/
 	PAD_NC(GPP_C14, UP_20K),
-	/* GPP_C15:	Not Connected		*/
 	PAD_NC(GPP_C15, UP_20K),
 	/* GPP_C18:	TOUCH_I2C_SDA		*/
 	PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1),
 	/* GPP_C19:	TOUCH_I2C_CLK		*/
 	PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1),
-	/* GPP_C22:	Not Connected		*/
 	PAD_NC(GPP_C22, NONE),
-	/* GPP_D0:	Not Connected		*/
+
 	PAD_NC(GPP_D0, DN_20K),
-	/* GPP_D1:	Not Connected		*/
 	PAD_NC(GPP_D1, DN_20K),
-	/* GPP_D2:	Not Connected		*/
 	PAD_NC(GPP_D2, DN_20K),
-	/* GPP_D3:	Not Connected		*/
 	PAD_NC(GPP_D3, DN_20K),
-	/* GPP_D4:	Not Connected		*/
 	PAD_NC(GPP_D4, DN_20K),
-	/* GPP_D5:	Not Connected		*/
 	PAD_NC(GPP_D5, DN_20K),
-	/* GPP_D6:	Not Connected		*/
 	PAD_NC(GPP_D6, DN_20K),
-	/* GPP_D7:	Not Connected		*/
 	PAD_NC(GPP_D7, DN_20K),
-	/* GPP_D8:	Not Connected		*/
 	PAD_NC(GPP_D8, DN_20K),
-	/* GPP_D9:	VOLUME_UP		*/
 	PAD_NC(GPP_D9, DN_20K),
-	/* GPP_D10:	VOLUME_DOWN		*/
 	PAD_NC(GPP_D10, DN_20K),
-	/* GPP_D11:	Not Connected		*/
 	PAD_NC(GPP_D11, DN_20K),
-	/* GPP_D12:	Not Connected		*/
 	PAD_NC(GPP_D12, DN_20K),
-	/* GPP_D13:	Not Connected		*/
 	PAD_NC(GPP_D13, DN_20K),
-	/* GPP_D14:	GPP_D14			*/
 	PAD_NC(GPP_D14, DN_20K),
-	/* GPP_D15:	GPP_D15			*/
 	PAD_NC(GPP_D15, DN_20K),
-	/* GPP_D16:	GPP_D16			*/
 	PAD_NC(GPP_D16, DN_20K),
-	/* GPP_D17:	PCH_AUDIO_PWREN		*/
 	PAD_NC(GPP_D17, DN_20K),
-	/* GPP_D18:	Not Connected		*/
 	PAD_NC(GPP_D18, DN_20K),
-	/* GPP_D19:	Not Connected		*/
 	PAD_NC(GPP_D19, DN_20K),
-	/* GPP_D21:	Not Connected		*/
 	PAD_NC(GPP_D21, DN_20K),
-	/* GPP_D22:	Not Connected		*/
 	PAD_NC(GPP_D22, DN_20K),
-	/* GPP_D23:	Not Connected		*/
 	PAD_NC(GPP_D23, DN_20K),
-	/* GPP_E0:	Not Connected		*/
+
 	PAD_NC(GPP_E0, DN_20K),
-	/* GPP_E1:	Not Connected		*/
 	PAD_NC(GPP_E1, DN_20K),
-	/* GPP_E2:	SATA2_SSD_Type		*/
 	PAD_NC(GPP_E2, DN_20K),
-	/* GPP_E3:	Not Connected		*/
 	PAD_NC(GPP_E3, DN_20K),
-	/* GPP_E4:	Not Connected		*/
 	PAD_NC(GPP_E4, DN_20K),
-	/* GPP_E5:	Not Connected		*/
 	PAD_NC(GPP_E5, DN_20K),
 	/* GPP_E6:	SATA2_SSD_DEVSLP	*/
 	PAD_CFG_NF(GPP_E6, NONE, PWROK, NF1),
-	/* GPP_E7:	TOUCH_PANEL_INT_N	*/
 	PAD_NC(GPP_E7, DN_20K),
-	/* GPP_E8:	Not Connected		*/
 	PAD_NC(GPP_E8, DN_20K),
 	/* GPP_E9:	USB2_P1_WP1_OC_N	*/
 	PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1),
@@ -257,83 +183,48 @@ const struct pad_config gpio_table[] = {
 	PAD_CFG_NF(GPP_E10, NONE, DEEP, NF1),
 	/* GPP_E11:	USB2_P3_WP2_OC_N	*/
 	PAD_CFG_NF(GPP_E11, NONE, DEEP, NF1),
-	/* GPP_E12:	Not Connected		*/
 	PAD_NC(GPP_E12, DN_20K),
 	/* E15:  SMC_SMI_N                      */
 	PAD_CFG_GPI_SMI_LOW(GPP_E15, NONE, DEEP, EDGE_SINGLE),
 	/* E16:  SMC_SCI_N                      */
 	PAD_CFG_GPI_SCI_LOW(GPP_E16, NONE, PLTRST, LEVEL),
-	/* GPP_E20:	Not Connected		*/
 	PAD_NC(GPP_E20, DN_20K),
-	/* GPP_E21:	DDI2_DDC_SDA		*/
 	PAD_NC(GPP_E21, DN_20K),
-	/* GPP_E22:	Not Connected		*/
 	PAD_NC(GPP_E22, DN_20K),
-	/* GPP_E23:	TOUCH_PANEL_RESET_N	*/
 	PAD_NC(GPP_E23, DN_20K),
-	/* GPP_F0:	Not Connected		*/
+
 	PAD_NC(GPP_F0, DN_20K),
-	/* GPP_F1:	Not Connected		*/
 	PAD_NC(GPP_F1, DN_20K),
-	/* GPP_F2:	Not Connected		*/
 	PAD_NC(GPP_F2, DN_20K),
-	/* GPP_F3:	Not Connected		*/
 	PAD_NC(GPP_F3, DN_20K),
-	/* GPP_F4:	GSENSOR_I2C_SDA		*/
 	PAD_NC(GPP_F4, DN_20K),
-	/* GPP_F5:	GSENSOR_I2C_SCL		*/
 	PAD_NC(GPP_F5, DN_20K),
-	/* GPP_F6:	Not Connected		*/
 	PAD_NC(GPP_F6, DN_20K),
-	/* GPP_F7:	Not Connected		*/
 	PAD_NC(GPP_F7, DN_20K),
-	/* GPP_F8:	Not Connected		*/
 	PAD_NC(GPP_F8, NONE),
-	/* GPP_F9:	Not Connected		*/
 	PAD_NC(GPP_F9, NONE),
-	/* GPP_F10:	ACCEL2_INT		*/
 	PAD_NC(GPP_F10, DN_20K),
-	/* GPP_F11:	ACCEL1_INT		*/
 	PAD_NC(GPP_F11, DN_20K),
-	/* GPP_F12:	Not Connected		*/
 	PAD_NC(GPP_F12, DN_20K),
-	/* GPP_F13:	Not Connected		*/
 	PAD_NC(GPP_F13, DN_20K),
-	/* GPP_F14:	Not Connected		*/
 	PAD_NC(GPP_F14, DN_20K),
-	/* GPP_F15:	Not Connected		*/
 	PAD_NC(GPP_F15, DN_20K),
-	/* GPP_F16:	Not Connected		*/
 	PAD_NC(GPP_F16, DN_20K),
-	/* GPP_F17:	Not Connected		*/
 	PAD_NC(GPP_F17, DN_20K),
-	/* GPP_F18:	Not Connected		*/
 	PAD_NC(GPP_F18, DN_20K),
-	/* GPP_F19:	Not Connected		*/
 	PAD_NC(GPP_F19, DN_20K),
-	/* GPP_F20:	Not Connected		*/
 	PAD_NC(GPP_F20, DN_20K),
-	/* GPP_F21:	Not Connected		*/
 	PAD_NC(GPP_F21, DN_20K),
-	/* GPP_F22:	Not Connected		*/
 	PAD_NC(GPP_F22, DN_20K),
-	/* GPP_F23:	Not Connected		*/
 	PAD_NC(GPP_F23, DN_20K),
-	/* GPP_G0:	Not Connected		*/
+
 	PAD_NC(GPP_G0, NONE),
-	/* GPP_G1:	Not Connected		*/
 	PAD_NC(GPP_G1, NONE),
-	/* GPP_G2:	Not Connected		*/
 	PAD_NC(GPP_G2, NONE),
-	/* GPP_G3:	Not Connected		*/
 	PAD_NC(GPP_G3, NONE),
-	/* GPP_G4:	Not Connected		*/
 	PAD_NC(GPP_G4, NONE),
-	/* GPP_G5:	Not Connected		*/
 	PAD_NC(GPP_G5, NONE),
-	/* GPP_G6:	Not Connected		*/
 	PAD_NC(GPP_G6, NONE),
-	/* GPP_G7:	Not Connected		*/
 	PAD_NC(GPP_G7, NONE),
 };
 
diff --git a/src/mainboard/starlabs/starbook/variants/rpl/gpio.c b/src/mainboard/starlabs/starbook/variants/rpl/gpio.c
index bfcd0769c0..34b67af6a6 100644
--- a/src/mainboard/starlabs/starbook/variants/rpl/gpio.c
+++ b/src/mainboard/starlabs/starbook/variants/rpl/gpio.c
@@ -81,96 +81,58 @@ const struct pad_config gpio_table[] = {
 	PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1),				/* Data */
 	PAD_CFG_GPO(GPP_E8, 1, DEEP),					/* DRAM Sleep */
 
-	/* GPD2:	LAN Wake					*/
 	PAD_NC(GPD2, NONE),
-	/* GPD6:	Sleep A						*/
 	PAD_NC(GPD6, NONE),
 	/* GPD7:	Power Adapter Disable				*/
 	PAD_CFG_GPO(GPD7, 0, PWROK),
 	/* GPD9:	Wireless LAN Sleep				*/
 	PAD_CFG_NF(GPD9, NONE, DEEP, NF1),
 
-	/* GPD10:	Sleep S5					*/
 	PAD_NC(GPD10, NONE),
-	/* GPD11:	LAN PHY Enable					*/
 	PAD_NC(GPD11, NONE),
 
-	/* A5:		Not Connected					*/
 	PAD_NC(GPP_A5, NONE),
-	/* A6:		Not Connected					*/
 	PAD_NC(GPP_A6, NONE),
-	/* A7:		Embedded Controller SCI				*/
 	PAD_NC(GPP_A7, NONE),
-	/* A8:		Not Connected					*/
 	PAD_NC(GPP_A8, NONE),
-	/* A11:		Not Connected					*/
 	PAD_NC(GPP_A11, NONE),
-	/* A12:		PCH M.2 SSD PEDET				*/
 	PAD_NC(GPP_A12, NONE),
-	/* A14:		Test Point 45					*/
 	PAD_NC(GPP_A14, NONE),
-	/* A15:		Test Point 52					*/
 	PAD_NC(GPP_A15, NONE),
-	/* A16:		USB OverCurrent 3				*/
 	PAD_NC(GPP_A16, NONE),
-	/* A17:		Not Connected					*/
 	PAD_NC(GPP_A17, NONE),
-	/* A19:		Not Connected					*/
 	PAD_NC(GPP_A19, NONE),
-	/* A20:		Test Point 44					*/
 	PAD_NC(GPP_A20, NONE),
-	/* A21:		Fingerprint Reader Interrupt			*/
 	PAD_NC(GPP_A21, NONE),
-	/* A22:		Fingerprint Reader Reset			*/
 	PAD_NC(GPP_A22, NONE),
-	/* A23:		Not Connected					*/
 	PAD_NC(GPP_A23, NONE),
 
-	/* B3:		Not Connected					*/
 	PAD_NC(GPP_B3, NONE),
-	/* B4:		Not Connected					*/
 	PAD_NC(GPP_B4, NONE),
-	/* B5:		I2C 2 SDA		Touch Panel SDA		*/
 	PAD_NC(GPP_B5, NONE),
-	/* B6:		I2C 2 SCL		Touch Panel Clock	*/
 	PAD_NC(GPP_B6, NONE),
-	/* B7:		I2C 3 SDA		Test Point 15		*/
 	PAD_NC(GPP_B7, NONE),
-	/* B8:		I2C 3 SCL		Test Point 16		*/
 	PAD_NC(GPP_B8, NONE),
-	/* B9:		Not Connected					*/
 	PAD_NC(GPP_B9, NONE),
-	/* B10:		Not Connected					*/
 	PAD_NC(GPP_B10, NONE),
-	/* B12:		PM SLP S0					*/
 	PAD_NC(GPP_B12, NONE),
 	/* B14:		Top Swap Override	Weak Internal PD 20K
 				High:	Enabled
 				Low:	Disabled			*/
 	PAD_NC(GPP_B14, NONE),
-	/* B15:		Not Connected					*/
 	PAD_NC(GPP_B15, NONE),
-	/* B16:		Not Connected					*/
 	PAD_NC(GPP_B16, NONE),
-	/* B17:		Not Connected					*/
 	PAD_NC(GPP_B17, NONE),
 	/* B18:		Reboot Support		Weak Internal PD 20K
 				High:	Disabled
 				Low:	Enabled				*/
 	PAD_NC(GPP_B18, NONE),
-	/* B19:		Not Connected					*/
 	PAD_NC(GPP_B19, NONE),
-	/* B20:		Not Connected					*/
 	PAD_NC(GPP_B20, NONE),
-	/* B21:		Not Connected					*/
 	PAD_NC(GPP_B21, NONE),
-	/* B22:		Not Connected					*/
 	PAD_NC(GPP_B22, NONE),
-	/* B23:		Not used	MiPi Camera			*/
 	PAD_NC(GPP_B23, NONE),
-	/* B24:		Not Connected					*/
 	PAD_NC(GPP_B24, NONE),
-	/* B25:		Not Connected					*/
 	PAD_NC(GPP_B25, NONE),
 
 	/* C2:		TLS Confidentiality	Weak Internal PD 20K
@@ -185,252 +147,139 @@ const struct pad_config gpio_table[] = {
 				Low:	ESPI
 				High:	Disabled			*/
 	PAD_CFG_GPO(GPP_C5, 0, DEEP),
-	/* C8:		Not Connected					*/
 	PAD_NC(GPP_C8, NONE),
-	/* C9:		Not Connected					*/
 	PAD_NC(GPP_C9, NONE),
-	/* C10:		Not Connected					*/
 	PAD_NC(GPP_C10, NONE),
-	/* C11:		Not Connected					*/
 	PAD_NC(GPP_C11, NONE),
-	/* C12:		Not Connected					*/
 	PAD_NC(GPP_C12, NONE),
-	/* C13:		Not Connected					*/
 	PAD_NC(GPP_C13, NONE),
-	/* C14:		Not Connected					*/
 	PAD_NC(GPP_C14, NONE),
-	/* C15:		Not Connected					*/
 	PAD_NC(GPP_C15, NONE),
-	/* C16:		Not Connected					*/
 	PAD_NC(GPP_C16, NONE),
-	/* C17:		Not Connected					*/
 	PAD_NC(GPP_C17, NONE),
-	/* C18:		Not Connected					*/
 	PAD_NC(GPP_C18, NONE),
-	/* C19:		Not Connected					*/
 	PAD_NC(GPP_C19, NONE),
-	/* C20:		Not Connected					*/
 	PAD_NC(GPP_C20, NONE),
-	/* C21:		Not Connected					*/
 	PAD_NC(GPP_C21, NONE),
-	/* C22:		Not Connected					*/
 	PAD_NC(GPP_C22, NONE),
-	/* C23:		Not Connected					*/
 	PAD_NC(GPP_C23, NONE),
 
-	/* D0:		Not used		Audio ID 0		*/
 	PAD_NC(GPP_D0, NONE),
-	/* D1:		Not used		Audio ID 1		*/
 	PAD_NC(GPP_D1, NONE),
-	/* D2:		Not used		Audio ID 2		*/
 	PAD_NC(GPP_D2, NONE),
-	/* D3:		Not Connected					*/
 	PAD_NC(GPP_D3, NONE),
-	/* D4:		Not Connected					*/
 	PAD_NC(GPP_D4, NONE),
-	/* D5:		Clock Request 0					*/
-	PAD_NC(GPP_D5, NONE),
-	/* D6:		Clock Request 1		PCH M.2 SSD		*/
+	PAD_NC(GPP_D3, NONE),
 	PAD_NC(GPP_D6, NONE),
-	/* D8:		Clock Request 3		LAN			*/
 	PAD_NC(GPP_D8, NONE),
-	/* D9:		GSPI 2 FPS					*/
 	PAD_NC(GPP_D9, NONE),
-	/* D10:		GSPI 2 Clock					*/
 	PAD_NC(GPP_D10, NONE),
-	/* D11:		GSPI 2 MISO FPS					*/
 	PAD_NC(GPP_D11, NONE),
-	/* D12:		GSPI 2 MOSI FPS					*/
 	PAD_NC(GPP_D12, NONE),
-	/* D13:		Wireless LAN Wake				*/
 	PAD_NC(GPP_D13, NONE),
-	/* D15:		Not Connected					*/
 	PAD_NC(GPP_D15, NONE),
-	/* D16:		PCH M.2 SSD Power Enable			*/
 	PAD_NC(GPP_D16, NONE),
-	/* D17:		Not used		Fingerprint ID		*/
 	PAD_NC(GPP_D17, NONE),
-	/* D18:		Not Connected					*/
 	PAD_NC(GPP_D18, NONE),
-	/* D19:		Test Point 21					*/
 	PAD_NC(GPP_D19, NONE),
 
-	/* E0:		SATA x PCIe					*/
 	PAD_NC(GPP_E0, NONE),
-	/* E1:		Not used		Accelerometer Interrupt	*/
 	PAD_NC(GPP_E1, NONE),
-	/* E2:		Not Connected					*/
 	PAD_NC(GPP_E2, NONE),
 	/* E4:		Retimer Force Power				*/
 	PAD_CFG_GPO(GPP_E4, 0, DEEP),
-	/* E5:		Not Connected					*/
 	PAD_NC(GPP_E5, NONE),
 	/* E6:		JTAG ODT		No internal PD
 				Low:	Disabled
 				High:	Enabled				*/
 	PAD_CFG_GPO(GPP_E6, 0, DEEP),
-	/* E7:		Embedded Controller SMI				*/
 	PAD_NC(GPP_E7, NONE),
-	/* E9:		USB OverCurrent 0				*/
 	PAD_NC(GPP_E9, NONE),
-	/* E10:		PWD Amplifier Input				*/
 	PAD_NC(GPP_E10, NONE),
-	/* E13:		Not connected					*/
 	PAD_NC(GPP_E13, NONE),
-	/* E15:		Not Connected					*/
 	PAD_NC(GPP_E15, NONE),
-	/* E16:		Not Connected					*/
 	PAD_NC(GPP_E16, NONE),
-	/* E17:		Not Connected					*/
 	PAD_NC(GPP_E17, NONE),
-	/* E18:		Thunderbolt LSX TXD				*/
 	PAD_NC(GPP_E18, NONE),
-	/* E19:		Thunderbolt LSX RXD				*/
 	PAD_NC(GPP_E19, NONE),
-	/* E20:		Not Connected					*/
 	PAD_NC(GPP_E20, NONE),
-	/* E21:		Not Connected					*/
 	PAD_NC(GPP_E21, NONE),
-	/* E22:		Not Connected					*/
 	PAD_NC(GPP_E22, NONE),
-	/* E23:		Not Connected					*/
 	PAD_NC(GPP_E23, NONE),
 
-	/* F0:		CNV BRI Data					*/
 	PAD_NC(GPP_F0, NONE),
-	/* F1:		CNV BRI Response				*/
 	PAD_NC(GPP_F1, NONE),
-	/* F2:		CNV RGI Data					*/
 	PAD_NC(GPP_F2, NONE),
-	/* F3:		CNV RGI Response				*/
 	PAD_NC(GPP_F3, NONE),
-	/* F4:		CNV RF Reset					*/
 	PAD_NC(GPP_F4, NONE),
-	/* F5:		Not used		MODEM_CLKREQ		*/
 	PAD_NC(GPP_F5, NONE),
-	/* F6:		CNV PA Blanking					*/
 	PAD_NC(GPP_F6, NONE),
 	/* F7:		TBT LSX VCCIO		Weak Internal PD 20K
 				Low:	1.8V
 				High:	3.3V				*/
 	PAD_CFG_GPO(GPP_F7, 0, DEEP),
-	/* F8:		Not Connected					*/
 	PAD_NC(GPP_F8, NONE),
-	/* F9:		EC Sleep S0					*/
 	PAD_NC(GPP_F9, NONE),
 	/* F10:		Weak Internal PD 20K				*/
 	PAD_CFG_GPO(GPP_F10, 0, PLTRST),
-	/* F11:		TPM ID						*/
 	PAD_NC(GPP_F11, NONE),
-	/* F12:		Not Connected					*/
 	PAD_NC(GPP_F12, NONE),
-	/* F13:		Not Connected					*/
 	PAD_NC(GPP_F13, NONE),
-	/* F14:		Not Connected					*/
 	PAD_NC(GPP_F14, NONE),
-	/* F15:		Not used		Accelerometer Interrupt 2*/
 	PAD_NC(GPP_F15, NONE),
-	/* F16:		Not Connected					*/
 	PAD_NC(GPP_F16, NONE),
-	/* F17:		Not used		Touch Panel Reset	*/
 	PAD_NC(GPP_F17, NONE),
-	/* F18:		Not used		Touch Panel Interrupt	*/
 	PAD_NC(GPP_F18, NONE),
-	/* F19:		Not Connected					*/
 	PAD_NC(GPP_F19, NONE),
-	/* F21:		GPPC_F21					*/
 	PAD_NC(GPP_F21, NONE),
-	/* F22:		Not Connected					*/
 	PAD_NC(GPP_F22, NONE),
-	/* F23:		Not Connected					*/
 	PAD_NC(GPP_F23, NONE),
 
-	/* H0:		PCH M.2 SSD Reset				*/
 	PAD_NC(GPP_H0, NONE),
 	/* H1:		BFX Strap 2 Bit 3	Weak Internal PD 20K	*/
 	PAD_CFG_GPO(GPP_H1, 0, DEEP),
-	/* H3:		Not Connected					*/
 	PAD_NC(GPP_H3, NONE),
-	/* H6:		Not Connected					*/
 	PAD_NC(GPP_H6, NONE),
-	/* H7:		Not Connected					*/
 	PAD_NC(GPP_H7, NONE),
-	/* H8:		I2C 4 SDA		GSensor			*/
 	PAD_NC(GPP_H8, NONE),
-	/* H9:		I2C 4 SDL		GSensor			*/
 	PAD_NC(GPP_H9, NONE),
-	/* H12:		Not Connected					*/
 	PAD_NC(GPP_H12, NONE),
-	/* H13:		PCH M.2 SSD Device Sleep			*/
 	PAD_NC(GPP_H13, NONE),
-	/* H14:		Not Connected					*/
 	PAD_NC(GPP_H14, NONE),
-	/* H16:		Not Connected					*/
 	PAD_NC(GPP_H16, NONE),
-	/* H20:		Not Connected					*/
 	PAD_NC(GPP_H20, NONE),
-	/* H21:		Not Connected					*/
 	PAD_NC(GPP_H21, NONE),
-	/* H22:		Not Connected					*/
 	PAD_NC(GPP_H22, NONE),
-	/* H23:		Clock Request 5					*/
 	PAD_NC(GPP_H23, NONE),
 
-	/* S0:		Not Connected					*/
 	PAD_NC(GPP_S0, NONE),
-	/* S1:		Not Connected					*/
 	PAD_NC(GPP_S1, NONE),
-	/* S2:		DMIC Clock					*/
 	PAD_NC(GPP_S2, NONE),
-	/* S3:		DMIC Data					*/
 	PAD_NC(GPP_S3, NONE),
-	/* S4:		Not Connected					*/
 	PAD_NC(GPP_S4, NONE),
-	/* S5:		Not Connected					*/
 	PAD_NC(GPP_S5, NONE),
-	/* S6:		Not Connected					*/
 	PAD_NC(GPP_S6, NONE),
-	/* S7:		Not Connected					*/
 	PAD_NC(GPP_S7, NONE),
 
-	/* T0:		 Not Connected					*/
 	PAD_NC(GPP_T0, NONE),
-	/* T1:		 Not Connected					*/
 	PAD_NC(GPP_T1, NONE),
-	/* T2:		 Not Connected					*/
 	PAD_NC(GPP_T2, NONE),
-	/* T3:		 Not Connected					*/
 	PAD_NC(GPP_T3, NONE),
-	/* T4:		 Not Connected					*/
 	PAD_NC(GPP_T4, NONE),
-	/* T5:		 Not Connected					*/
 	PAD_NC(GPP_T5, NONE),
-	/* T6:		 Not Connected					*/
 	PAD_NC(GPP_T6, NONE),
-	/* T7:		 Not Connected					*/
 	PAD_NC(GPP_T7, NONE),
-	/* T8:		 Not Connected					*/
 	PAD_NC(GPP_T8, NONE),
-	/* T9:		 Not Connected					*/
 	PAD_NC(GPP_T9, NONE),
-	/* T10:		 Not Connected					*/
 	PAD_NC(GPP_T10, NONE),
-	/* T11:		 Not Connected					*/
 	PAD_NC(GPP_T11, NONE),
-	/* T12:		 Not Connected					*/
 	PAD_NC(GPP_T12, NONE),
-	/* T13:		 Not Connected					*/
 	PAD_NC(GPP_T13, NONE),
-	/* T14:		 Not Connected					*/
 	PAD_NC(GPP_T14, NONE),
-	/* T15:		 Not Connected					*/
 	PAD_NC(GPP_T15, NONE),
 
-	/* R5:		MiPi Cam Reset				*/
 	PAD_NC(GPP_R5, NONE),
-	/* R6:		Not Connected				*/
 	PAD_NC(GPP_R6, NONE),
-	/* R7:		Not Connected				*/
 	PAD_NC(GPP_R7, NONE),
 };
 
diff --git a/src/mainboard/starlabs/starbook/variants/tgl/gpio.c b/src/mainboard/starlabs/starbook/variants/tgl/gpio.c
index 4d66d40880..448683ce28 100644
--- a/src/mainboard/starlabs/starbook/variants/tgl/gpio.c
+++ b/src/mainboard/starlabs/starbook/variants/tgl/gpio.c
@@ -212,7 +212,6 @@ const struct pad_config gpio_table[] = {
 	PAD_NC(GPP_F22, NONE),
 	PAD_NC(GPP_F23, NONE),
 
-	/* H3:	Not Connected			*/
 	PAD_NC(GPP_H3, NONE),
 	PAD_NC(GPP_H4, NONE),
 	PAD_NC(GPP_H5, NONE),

From 711d49d4ec164a19ec80d7848ee517a921943439 Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Tue, 14 Oct 2025 20:24:04 +0100
Subject: [PATCH 2253/3886] mb/starlabs/starbook/adl: Configure additional SSD
 GPIOs

DEV_SLP and PEDET were simply missed, so configure them.

Change-Id: Ia0da7f30167a689bca1f4692ee154a364c5b949c
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89580
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
---
 src/mainboard/starlabs/starbook/variants/adl/gpio.c | 6 ++----
 1 file changed, 2 insertions(+), 4 deletions(-)

diff --git a/src/mainboard/starlabs/starbook/variants/adl/gpio.c b/src/mainboard/starlabs/starbook/variants/adl/gpio.c
index 012dc923cf..c33c57dec2 100644
--- a/src/mainboard/starlabs/starbook/variants/adl/gpio.c
+++ b/src/mainboard/starlabs/starbook/variants/adl/gpio.c
@@ -43,6 +43,8 @@ const struct pad_config gpio_table[] = {
 	PAD_CFG_NF(GPP_D6, NONE, DEEP, NF1),				/* Clock Request 1 */
 	PAD_CFG_GPO(GPP_H0, 1, PLTRST),					/* Reset */
 	PAD_CFG_GPO(GPP_D16, 1, DEEP),					/* Enable */
+	PAD_CFG_NF(GPP_H13, NONE, DEEP, NF5),				/* Device Sleep */
+	PAD_CFG_NF(GPP_A12, NONE, DEEP, NF1),				/* PEDET */
 
 	/* Wireless */
 	PAD_CFG_NF(GPP_D7, NONE, DEEP, NF1),				/* Clock Request 2 */
@@ -103,8 +105,6 @@ const struct pad_config gpio_table[] = {
 	PAD_NC(GPP_A7, NONE),
 	PAD_NC(GPP_A8, NONE),
 	PAD_NC(GPP_A11, NONE),
-	/* A12:		PCH M.2 SSD PEDET				*/
-	PAD_CFG_NF(GPP_A12, NONE, DEEP, NF1),
 	PAD_NC(GPP_A14, NONE),
 	PAD_NC(GPP_A15, NONE),
 	PAD_NC(GPP_A16, NONE),
@@ -229,8 +229,6 @@ const struct pad_config gpio_table[] = {
 	PAD_NC(GPP_H8, NONE),
 	PAD_NC(GPP_H9, NONE),
 	PAD_NC(GPP_H12, NONE),
-	/* H13:		PCH M.2 SSD Device Sleep			*/
-	PAD_CFG_NF(GPP_H13, NONE, DEEP, NF5),
 	PAD_NC(GPP_H14, NONE),
 	PAD_NC(GPP_H16, NONE),
 	PAD_NC(GPP_H19, NONE),

From d7627a39e86bd17030224b62bb6b0b0dc3a04fae Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Tue, 14 Oct 2025 20:11:34 +0100
Subject: [PATCH 2254/3886] mb/starlabs/starbook/adl: Tidy up GPIO config
 straps

Apply the standard format for configuring the config straps. The
configuration of the straps isn't changed, just written more clearly.

Change-Id: I2cf130fbf7572a4014e97c14885951e5f604cfa8
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89578
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 .../starlabs/starbook/variants/adl/gpio.c      | 18 +++++++++---------
 1 file changed, 9 insertions(+), 9 deletions(-)

diff --git a/src/mainboard/starlabs/starbook/variants/adl/gpio.c b/src/mainboard/starlabs/starbook/variants/adl/gpio.c
index c33c57dec2..dbf0e67c38 100644
--- a/src/mainboard/starlabs/starbook/variants/adl/gpio.c
+++ b/src/mainboard/starlabs/starbook/variants/adl/gpio.c
@@ -82,16 +82,16 @@ const struct pad_config gpio_table[] = {
 	PAD_CFG_GPO(GPP_E8, 1, DEEP),					/* DRAM Sleep */
 
 	/* Config Straps 									[ Low      / High     ] */
-	PAD_NC(GPP_B14, NONE),						/* Top Swap		[ Disabled / Enabled  ] */
-	PAD_NC(GPP_B18, NONE),						/* Reboot Support	[ Enabled  / Disabled ] */
+	PAD_CFG_GPO(GPP_B14, 0, PLTRST),				/* Top Swap		[ Disabled / Enabled  ] */
+	PAD_CFG_GPO(GPP_B18, 0, PLTRST),				/* Reboot Support	[ Enabled  / Disabled ] */
 	PAD_CFG_GPO(GPP_C2, 1, PLTRST),					/* TLS Confidentiality	[ Disabled / Enabled  ] */
-	PAD_CFG_GPO(GPP_C5, 0, DEEP),					/* eSPI			[ Enabled  / Disabled ] */
-	PAD_CFG_GPO(GPP_E6, 0, DEEP),					/* JTAG ODT		[ Disabled / Enabled  ] */
-	PAD_CFG_GPO(GPP_H1, 0, DEEP),					/* BFX Strap 2 Bit 3	[ Disabled / Enabled  ] */
-	PAD_NC(GPP_F2, NONE),						/* M.2 CNVi		[ Enabled  / Disabled ] */
-	PAD_NC(GPP_E19, NONE),						/* TBT LSX #0		[ 1.8V     / 3.3V     ] */
-	PAD_CFG_GPO(GPP_F7, 0, DEEP),					/* MCRO LDO		[ Disabled / Bypass   ] */
-	PAD_CFG_GPO(GPD7, 0, PWROK),					/* RTC Clock Delay	[ Disabled / 95ms     ] */
+	PAD_CFG_GPO(GPP_C5, 0, PLTRST),					/* eSPI			[ Enabled  / Disabled ] */
+	PAD_CFG_GPO(GPP_E6, 0, PLTRST),					/* JTAG ODT		[ Disabled / Enabled  ] */
+	PAD_CFG_GPO(GPP_H1, 0, PLTRST),					/* BFX Strap 2 Bit 3	[ Disabled / Enabled  ] */
+	PAD_CFG_GPO(GPP_F2, 0, PLTRST),					/* M.2 CNVi		[ Enabled  / Disabled ] */
+	PAD_CFG_GPO(GPP_E19, 0, PLTRST),				/* TBT LSX #0		[ 1.8V     / 3.3V     ] */
+	PAD_CFG_GPO(GPP_F7, 0, PLTRST),					/* MCRO LDO		[ Disabled / Bypass   ] */
+	PAD_CFG_GPO(GPD7, 0, PLTRST),					/* RTC Clock Delay	[ Disabled / 95ms     ] */
 
 
 	PAD_NC(GPD2, NONE),

From 7ad632cbc7476ac49756cf7b382388f78be7a3a9 Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Tue, 14 Oct 2025 20:27:15 +0100
Subject: [PATCH 2255/3886] mb/starlabs/starbook/adl: Disconnect unused GPIOs

Set pads that are not used to PAD_NC.

Change-Id: I3bf005b743fdcaf75c456c59354e7440ec0faefb
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89581
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
---
 .../starlabs/starbook/variants/adl/gpio.c        | 16 +++++-----------
 1 file changed, 5 insertions(+), 11 deletions(-)

diff --git a/src/mainboard/starlabs/starbook/variants/adl/gpio.c b/src/mainboard/starlabs/starbook/variants/adl/gpio.c
index dbf0e67c38..f2d33b6458 100644
--- a/src/mainboard/starlabs/starbook/variants/adl/gpio.c
+++ b/src/mainboard/starlabs/starbook/variants/adl/gpio.c
@@ -135,15 +135,10 @@ const struct pad_config gpio_table[] = {
 	PAD_NC(GPP_B24, NONE),
 	PAD_NC(GPP_B25, NONE),
 
-	/* C3:		SML 0 Clock					*/
-	PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1),
-	/* C4:		SML 0 Data					*/
-	PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1),
-
-	/* C6:		SML 1 Clock					*/
-	PAD_CFG_NF(GPP_C6, NONE, DEEP, NF1),
-	/* C7:		SML 1 Data					*/
-	PAD_CFG_NF(GPP_C7, NONE, DEEP, NF1),
+	PAD_NC(GPP_C3, NONE),
+	PAD_NC(GPP_C4, NONE),
+	PAD_NC(GPP_C6, NONE),
+	PAD_NC(GPP_C7, NONE),
 	PAD_NC(GPP_C8, NONE),
 	PAD_NC(GPP_C9, NONE),
 	PAD_NC(GPP_C10, NONE),
@@ -206,8 +201,7 @@ const struct pad_config gpio_table[] = {
 
 	PAD_NC(GPP_F8, NONE),
 	PAD_NC(GPP_F9, NONE),
-	/* F10:		Weak Internal PD 20K				*/
-	PAD_CFG_GPO(GPP_F10, 0, DEEP),
+	PAD_NC(GPP_F10, NONE),
 	PAD_NC(GPP_F11, NONE),
 	PAD_NC(GPP_F12, NONE),
 	PAD_NC(GPP_F13, NONE),

From 83aa4417cb64b3e2863728fed2b6600347670eea Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Tue, 14 Oct 2025 20:48:48 +0100
Subject: [PATCH 2256/3886] mb/starlabs/starbook/rpl: Tidy up GPIO config
 straps

Emply the standard Star Labs format for the config straps; this is
a non-functional change - just easier to read.

Change-Id: I04c7a8046c21577154593996866448fc4c05d03b
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89583
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
---
 .../starlabs/starbook/variants/rpl/gpio.c     | 40 +++++--------------
 1 file changed, 11 insertions(+), 29 deletions(-)

diff --git a/src/mainboard/starlabs/starbook/variants/rpl/gpio.c b/src/mainboard/starlabs/starbook/variants/rpl/gpio.c
index 34b67af6a6..f60e5e7caa 100644
--- a/src/mainboard/starlabs/starbook/variants/rpl/gpio.c
+++ b/src/mainboard/starlabs/starbook/variants/rpl/gpio.c
@@ -81,10 +81,19 @@ const struct pad_config gpio_table[] = {
 	PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1),				/* Data */
 	PAD_CFG_GPO(GPP_E8, 1, DEEP),					/* DRAM Sleep */
 
+	/* Config Straps 									[ Low      / High     ] */
+	PAD_CFG_GPO(GPP_B14, 0, PLTRST),				/* Top Swap		[ Disabled / Enabled  ] */
+	PAD_CFG_GPO(GPP_B18, 0, PLTRST),				/* Reboot Support	[ Enabled  / Disabled ] */
+	PAD_CFG_GPO(GPP_C2, 1, PLTRST),					/* TLS Confidentiality	[ Disabled / Enabled  ] */
+	PAD_CFG_GPO(GPP_C5, 0, PLTRST),					/* eSPI			[ Enabled  / Disabled ] */
+	PAD_CFG_GPO(GPP_E6, 0, PLTRST),					/* JTAG ODT		[ Disabled / Enabled  ] */
+	PAD_CFG_GPO(GPP_H1, 0, PLTRST),					/* BFX Strap 2 Bit 3	[ Disabled / Enabled  ] */
+	PAD_CFG_GPO(GPP_F2, 0, PLTRST),					/* M.2 CNVi		[ Enabled  / Disabled ] */
+	PAD_CFG_GPO(GPP_F7, 0, PLTRST),					/* MCRO LDO		[ Disabled / Bypass   ] */
+	PAD_CFG_GPO(GPD7, 0, PLTRST),					/* RTC Clock Delay	[ Disabled / 95ms     ] */
+
 	PAD_NC(GPD2, NONE),
 	PAD_NC(GPD6, NONE),
-	/* GPD7:	Power Adapter Disable				*/
-	PAD_CFG_GPO(GPD7, 0, PWROK),
 	/* GPD9:	Wireless LAN Sleep				*/
 	PAD_CFG_NF(GPD9, NONE, DEEP, NF1),
 
@@ -116,17 +125,9 @@ const struct pad_config gpio_table[] = {
 	PAD_NC(GPP_B9, NONE),
 	PAD_NC(GPP_B10, NONE),
 	PAD_NC(GPP_B12, NONE),
-	/* B14:		Top Swap Override	Weak Internal PD 20K
-				High:	Enabled
-				Low:	Disabled			*/
-	PAD_NC(GPP_B14, NONE),
 	PAD_NC(GPP_B15, NONE),
 	PAD_NC(GPP_B16, NONE),
 	PAD_NC(GPP_B17, NONE),
-	/* B18:		Reboot Support		Weak Internal PD 20K
-				High:	Disabled
-				Low:	Enabled				*/
-	PAD_NC(GPP_B18, NONE),
 	PAD_NC(GPP_B19, NONE),
 	PAD_NC(GPP_B20, NONE),
 	PAD_NC(GPP_B21, NONE),
@@ -135,18 +136,10 @@ const struct pad_config gpio_table[] = {
 	PAD_NC(GPP_B24, NONE),
 	PAD_NC(GPP_B25, NONE),
 
-	/* C2:		TLS Confidentiality	Weak Internal PD 20K
-				Low:	Disabled
-				High:	Enabled				*/
-	PAD_CFG_GPO(GPP_C2, 1, PLTRST),
 	/* C3:		SML 0 Clock					*/
 	PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1),
 	/* C4:		SML 0 Data					*/
 	PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1),
-	/* C5:		Boot Strap		Weak Internal PD 20K
-				Low:	ESPI
-				High:	Disabled			*/
-	PAD_CFG_GPO(GPP_C5, 0, DEEP),
 	PAD_NC(GPP_C8, NONE),
 	PAD_NC(GPP_C9, NONE),
 	PAD_NC(GPP_C10, NONE),
@@ -189,10 +182,6 @@ const struct pad_config gpio_table[] = {
 	/* E4:		Retimer Force Power				*/
 	PAD_CFG_GPO(GPP_E4, 0, DEEP),
 	PAD_NC(GPP_E5, NONE),
-	/* E6:		JTAG ODT		No internal PD
-				Low:	Disabled
-				High:	Enabled				*/
-	PAD_CFG_GPO(GPP_E6, 0, DEEP),
 	PAD_NC(GPP_E7, NONE),
 	PAD_NC(GPP_E9, NONE),
 	PAD_NC(GPP_E10, NONE),
@@ -209,15 +198,10 @@ const struct pad_config gpio_table[] = {
 
 	PAD_NC(GPP_F0, NONE),
 	PAD_NC(GPP_F1, NONE),
-	PAD_NC(GPP_F2, NONE),
 	PAD_NC(GPP_F3, NONE),
 	PAD_NC(GPP_F4, NONE),
 	PAD_NC(GPP_F5, NONE),
 	PAD_NC(GPP_F6, NONE),
-	/* F7:		TBT LSX VCCIO		Weak Internal PD 20K
-				Low:	1.8V
-				High:	3.3V				*/
-	PAD_CFG_GPO(GPP_F7, 0, DEEP),
 	PAD_NC(GPP_F8, NONE),
 	PAD_NC(GPP_F9, NONE),
 	/* F10:		Weak Internal PD 20K				*/
@@ -236,8 +220,6 @@ const struct pad_config gpio_table[] = {
 	PAD_NC(GPP_F23, NONE),
 
 	PAD_NC(GPP_H0, NONE),
-	/* H1:		BFX Strap 2 Bit 3	Weak Internal PD 20K	*/
-	PAD_CFG_GPO(GPP_H1, 0, DEEP),
 	PAD_NC(GPP_H3, NONE),
 	PAD_NC(GPP_H6, NONE),
 	PAD_NC(GPP_H7, NONE),

From a8c70f7578189eef520a745b13651a21747fd92f Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Tue, 14 Oct 2025 20:50:32 +0100
Subject: [PATCH 2257/3886] mb/starlabs/starbook/rpl: Reconfigure TBT GPIOs

It seems that FSP was fixing up the TBT0 TXD and RXD GPIOs;
add the missing GPIO configuration and group them.

Change-Id: I22af542fe008395a47c64396f481442ff3bcc9a7
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89584
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/starlabs/starbook/variants/rpl/gpio.c | 9 +++++----
 1 file changed, 5 insertions(+), 4 deletions(-)

diff --git a/src/mainboard/starlabs/starbook/variants/rpl/gpio.c b/src/mainboard/starlabs/starbook/variants/rpl/gpio.c
index f60e5e7caa..856a243baf 100644
--- a/src/mainboard/starlabs/starbook/variants/rpl/gpio.c
+++ b/src/mainboard/starlabs/starbook/variants/rpl/gpio.c
@@ -59,6 +59,11 @@ const struct pad_config gpio_table[] = {
 	PAD_CFG_NF(GPP_C6, NONE, DEEP, NF1),				/* SML Clock */
 	PAD_CFG_NF(GPP_C7, NONE, DEEP, NF1),				/* SML Data */
 
+	/* Retimer */
+	PAD_CFG_NF(GPP_E18, NONE, DEEP, NF2),				/* TBT0 TXD */
+	PAD_CFG_NF(GPP_E19, NONE, DEEP, NF2),				/* TBT0 RXD */
+	PAD_CFG_GPO(GPP_E4, 0, DEEP),					/* Force Power */
+
 	/* High-Definition Audio */
 	PAD_CFG_NF(GPP_R0, NATIVE, DEEP, NF1),				/* Clock */
 	PAD_CFG_NF(GPP_R1, NATIVE, DEEP, NF1),				/* Sync */
@@ -179,8 +184,6 @@ const struct pad_config gpio_table[] = {
 	PAD_NC(GPP_E0, NONE),
 	PAD_NC(GPP_E1, NONE),
 	PAD_NC(GPP_E2, NONE),
-	/* E4:		Retimer Force Power				*/
-	PAD_CFG_GPO(GPP_E4, 0, DEEP),
 	PAD_NC(GPP_E5, NONE),
 	PAD_NC(GPP_E7, NONE),
 	PAD_NC(GPP_E9, NONE),
@@ -189,8 +192,6 @@ const struct pad_config gpio_table[] = {
 	PAD_NC(GPP_E15, NONE),
 	PAD_NC(GPP_E16, NONE),
 	PAD_NC(GPP_E17, NONE),
-	PAD_NC(GPP_E18, NONE),
-	PAD_NC(GPP_E19, NONE),
 	PAD_NC(GPP_E20, NONE),
 	PAD_NC(GPP_E21, NONE),
 	PAD_NC(GPP_E22, NONE),

From f22bcc1d42366b8dd80fa41f59ac7f4a0d8f78a1 Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Tue, 14 Oct 2025 20:52:01 +0100
Subject: [PATCH 2258/3886] mb/starlabs/starbook/rpl: Disconnect unused GPIOs

Set pads that are not used to PAD_NC

Change-Id: I1a50bc8eab9d086b71cc33f56789bdd10f133864
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89585
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
---
 src/mainboard/starlabs/starbook/variants/rpl/gpio.c | 13 ++++---------
 1 file changed, 4 insertions(+), 9 deletions(-)

diff --git a/src/mainboard/starlabs/starbook/variants/rpl/gpio.c b/src/mainboard/starlabs/starbook/variants/rpl/gpio.c
index 856a243baf..0625675f10 100644
--- a/src/mainboard/starlabs/starbook/variants/rpl/gpio.c
+++ b/src/mainboard/starlabs/starbook/variants/rpl/gpio.c
@@ -99,9 +99,7 @@ const struct pad_config gpio_table[] = {
 
 	PAD_NC(GPD2, NONE),
 	PAD_NC(GPD6, NONE),
-	/* GPD9:	Wireless LAN Sleep				*/
-	PAD_CFG_NF(GPD9, NONE, DEEP, NF1),
-
+	PAD_NC(GPD9, NONE),
 	PAD_NC(GPD10, NONE),
 	PAD_NC(GPD11, NONE),
 
@@ -141,10 +139,8 @@ const struct pad_config gpio_table[] = {
 	PAD_NC(GPP_B24, NONE),
 	PAD_NC(GPP_B25, NONE),
 
-	/* C3:		SML 0 Clock					*/
-	PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1),
-	/* C4:		SML 0 Data					*/
-	PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1),
+	PAD_NC(GPP_C3, NONE),
+	PAD_NC(GPP_C4, NONE),
 	PAD_NC(GPP_C8, NONE),
 	PAD_NC(GPP_C9, NONE),
 	PAD_NC(GPP_C10, NONE),
@@ -205,8 +201,7 @@ const struct pad_config gpio_table[] = {
 	PAD_NC(GPP_F6, NONE),
 	PAD_NC(GPP_F8, NONE),
 	PAD_NC(GPP_F9, NONE),
-	/* F10:		Weak Internal PD 20K				*/
-	PAD_CFG_GPO(GPP_F10, 0, PLTRST),
+	PAD_NC(GPP_F10, NONE),
 	PAD_NC(GPP_F11, NONE),
 	PAD_NC(GPP_F12, NONE),
 	PAD_NC(GPP_F13, NONE),

From a7a49e5f74effaeab9808c70b4f72048b10d3dfb Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Wed, 15 Oct 2025 14:40:15 +0100
Subject: [PATCH 2259/3886] mb/starlabs/starfighter: Correct reference for
 second TBT port

The second port was set to 07.0, which is the first port. Correct
this.

Change-Id: I8d1a046ea863beb921c103cb2aa82b09d75f2be7
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89595
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/starlabs/starfighter/variants/rpl/devtree.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/mainboard/starlabs/starfighter/variants/rpl/devtree.c b/src/mainboard/starlabs/starfighter/variants/rpl/devtree.c
index 7a4111dddb..ae35ed5e4b 100644
--- a/src/mainboard/starlabs/starfighter/variants/rpl/devtree.c
+++ b/src/mainboard/starlabs/starfighter/variants/rpl/devtree.c
@@ -23,7 +23,7 @@ void devtree_update(void)
 		&cfg->power_limits_config[RPL_P_682_642_482_45W_CORE];
 
 	struct device *tbt_pci_dev_0 = pcidev_on_root(0x07, 0);
-	struct device *tbt_pci_dev_1 = pcidev_on_root(0x07, 0);
+	struct device *tbt_pci_dev_1 = pcidev_on_root(0x07, 1);
 	struct device *tbt_dma_dev = pcidev_on_root(0x0d, 2);
 	struct device *gna_dev = pcidev_on_root(0x08, 0);
 

From f665e189da5f19dbc303146c5eb6614b2974edf4 Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Wed, 15 Oct 2025 16:46:49 +0100
Subject: [PATCH 2260/3886] mb/starlabs/{starbook/mtl,byte_adl}: Select
 USB4_PCIE_RESOURCES

Both of these boards have 20Gbps TBT2 ports, capable of accessing
PCIe labels from the PCH. Therefore, select
SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES.

Change-Id: I4528f2748d1fa3988296f695dac045de536c43df
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89597
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
---
 src/mainboard/starlabs/byte_adl/Kconfig | 1 +
 src/mainboard/starlabs/starbook/Kconfig | 1 +
 2 files changed, 2 insertions(+)

diff --git a/src/mainboard/starlabs/byte_adl/Kconfig b/src/mainboard/starlabs/byte_adl/Kconfig
index 234d59b43f..8054269b48 100644
--- a/src/mainboard/starlabs/byte_adl/Kconfig
+++ b/src/mainboard/starlabs/byte_adl/Kconfig
@@ -21,6 +21,7 @@ config BOARD_STARLABS_BYTE_SERIES
 	select SOC_INTEL_COMMON_BLOCK_HDA_VERB
 	select SOC_INTEL_COMMON_BLOCK_TCSS
 	select SOC_INTEL_CRASHLOG
+	select SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES
 	select SPD_READ_BY_WORD
 	select SPI_FLASH_WINBOND
 	select SYSTEM_TYPE_MINIPC
diff --git a/src/mainboard/starlabs/starbook/Kconfig b/src/mainboard/starlabs/starbook/Kconfig
index fd93a9b070..b6bcc47f9b 100644
--- a/src/mainboard/starlabs/starbook/Kconfig
+++ b/src/mainboard/starlabs/starbook/Kconfig
@@ -120,6 +120,7 @@ config BOARD_STARLABS_STARBOOK_MTL
 	select PMC_IPC_ACPI_INTERFACE
 	select SKIP_SEND_CONNECT_TOPOLOGY_CMD
 	select SOC_INTEL_COMMON_BLOCK_VTD
+	select SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES
 	select SOC_INTEL_METEORLAKE
 	select SOC_INTEL_METEORLAKE_U_H
 	select SOC_INTEL_COMMON_BLOCK_TCSS

From 079c9c47aab6890994f3152b01f8d57a820e54a9 Mon Sep 17 00:00:00 2001
From: Anand Vaikar <a.vaikar2021@gmail.com>
Date: Tue, 14 Oct 2025 10:36:56 +0530
Subject: [PATCH 2261/3886] soc/amd/cezanne: Add config option to keep ACP
 running in ACPI S3 state

Issue=ACP is not running in S3 because the XTAL FCH CLK is turned off.
ACP needs to be running in S3 for one of our customers who needs audio
playback to work in S3.

Fix=Introduce a config option to control this setting.

TEST=Tested this in ACPI S3 state,by connecting an external CODEC and
transmitting a known pattern to the ACP via the I2S TDM controller RX
lines and ensuring that the sound is output to the speaker connected
to the CODEC via the TDM TX line.

Change-Id: Ie9c0e96f87050b542a1ddf3f59d6b67064ac8faf
Signed-off-by: Anand Vaikar <a.vaikar2021@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89556
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
---
 src/soc/amd/cezanne/Kconfig | 7 +++++++
 src/soc/amd/cezanne/fch.c   | 6 +++++-
 2 files changed, 12 insertions(+), 1 deletion(-)

diff --git a/src/soc/amd/cezanne/Kconfig b/src/soc/amd/cezanne/Kconfig
index 5588262119..db4dc10a97 100644
--- a/src/soc/amd/cezanne/Kconfig
+++ b/src/soc/amd/cezanne/Kconfig
@@ -93,6 +93,13 @@ config SOC_AMD_CEZANNE
 
 if SOC_AMD_CEZANNE
 
+config KEEP_ACP_RUNNING_IN_S3
+	bool
+	default n
+	help
+	  Enables AMD Audio Co-Processor (ACP) to remain operational in ACPI
+	  S3 (sleep) state for continued audio processing support.
+
 config CHIPSET_DEVICETREE
 	string
 	default "soc/amd/cezanne/chipset.cb"
diff --git a/src/soc/amd/cezanne/fch.c b/src/soc/amd/cezanne/fch.c
index 0690eb7a63..52bdbb03f1 100644
--- a/src/soc/amd/cezanne/fch.c
+++ b/src/soc/amd/cezanne/fch.c
@@ -152,7 +152,11 @@ static void cgpll_clock_gate_init(void)
 	t = misc_read32(MISC_CLKGATEDCNTL);
 	t |= ALINKCLK_GATEOFFEN;
 	t |= BLINKCLK_GATEOFFEN;
-	t |= XTAL_PAD_S3_TURNOFF_EN;
+
+	if (!CONFIG(KEEP_ACP_RUNNING_IN_S3)) {
+		t |= XTAL_PAD_S3_TURNOFF_EN;
+	}
+
 	t |= XTAL_PAD_S5_TURNOFF_EN;
 	misc_write32(MISC_CLKGATEDCNTL, t);
 

From d23eaa356f9ca0b4fec09b74229b29f8d061789a Mon Sep 17 00:00:00 2001
From: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Date: Fri, 10 Oct 2025 09:15:01 +0900
Subject: [PATCH 2262/3886] util/lint: maintainers-syntax: Add a check to
 ensure paths exist

The MAINTAINERS file is used to automatically assign reviewers on
Gerrit, however as the paths are not checked they can become out of
sync with the codebase. This is detrimental to both the uploader
and the maintainers, as the change may not get the appropriate
attention.

Fix this problem by adding a simple check for 'F' and 'X' entries.

Change-Id: I7755f6317edda0d8d976e138cfafcc3ef5850ead
Signed-off-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89511
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
---
 util/lint/lint-stable-027-maintainers-syntax | 19 ++++++++++++++++---
 1 file changed, 16 insertions(+), 3 deletions(-)

diff --git a/util/lint/lint-stable-027-maintainers-syntax b/util/lint/lint-stable-027-maintainers-syntax
index 85245d1247..d0753d7316 100755
--- a/util/lint/lint-stable-027-maintainers-syntax
+++ b/util/lint/lint-stable-027-maintainers-syntax
@@ -1,21 +1,34 @@
 #!/usr/bin/env perl
 # SPDX-License-Identifier: GPL-2.0-or-later
 #
-# DESCR: Check that path patterns in MAINTAINERS have trailing slash
+# DESCR: Check the syntax of the MAINTAINERS file
 
 use strict;
 use warnings;
 
+sub check_path {
+	my ($path) = @_;
+
+	if ( ! -e $path ) {
+		print "MAINTAINERS:$. No such file or directory exists ";
+		print "`$path`\n";
+	}
+}
+
 open( my $file, "<", "MAINTAINERS" ) or die "Error: could not open file 'MAINTAINERS'\n";
 
 while ( my $line = <$file> ) {
-	if ( $line =~ /^[FX]:\s+([^\s]*[^*\/\s])\s+$/ ) {  # path patterns not ending with / or *
+	if ( $line =~ /^[FX]:\s+([^\s]*)\s+$/ ) {
 		my $path = $1;
 
-		if ( -d $path ) {
+		# Match path patterns not ending with '/' or '*'. This cannot be done
+		# in check_path(), as it only works on pre-globbed paths.
+		if ( $path =~ /[^*\/\s]$/ && -d $path ) {
 			print "MAINTAINERS:$. missing trailing slash for directory match ";
 			print "`$path`\n";
 		}
+
+		check_path($_) foreach ( glob $path );
 	}
 }
 

From 3747b47df1152b55d27f5ae587c91ac03b0628e0 Mon Sep 17 00:00:00 2001
From: "Johann C. Rode" <jcrode@gmx.net>
Date: Thu, 9 Oct 2025 11:07:11 -0700
Subject: [PATCH 2263/3886] mb/lenovo/sklkbl_thinkpad: Add Lenovo Thinkpad T580
 as a variant

The hardware is mostly identical to the well supported Thinkpad T480
aside from some swapped PCIe clock lines. Consequently, coreboot will
boot to the OS in combination with a properly deguarded Intel ME.

The VBT was obtained from the latest stock BIOS (1.43, N27ET57W) with
intelvbttool. GPIO assignments have been cross-checked against publicly
available schematics (Tachi-2).

The patches have been validated on a Thinkpad T580 P/N 20L9-001NUS. With
SeaBIOS rel-1.17.0-4 as payload, the system boots into Linux (debian 13)
and Windows 10 22H2 with the hardware working as expected.

Change-Id: Iaa8368aeda11560bc0c1c77e7611ed9879d038da
Signed-off-by: Johann C. Rode <jcrode@gmx.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89499
Reviewed-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/lenovo/sklkbl_thinkpad/Kconfig  |  11 +-
 .../lenovo/sklkbl_thinkpad/Kconfig.name       |   3 +
 .../sklkbl_thinkpad/variants/t580/data.vbt    | Bin 0 -> 4106 bytes
 .../variants/t580/gma-mainboard.ads           |  19 ++
 .../sklkbl_thinkpad/variants/t580/gpio.c      | 203 ++++++++++++++++++
 .../sklkbl_thinkpad/variants/t580/hda_verb.c  |  89 ++++++++
 .../variants/t580/include/variant/dgpu.h      |  15 ++
 .../variants/t580/memory_init_params.c        |  20 ++
 .../variants/t580/overridetree.cb             |  96 +++++++++
 9 files changed, 455 insertions(+), 1 deletion(-)
 create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t580/data.vbt
 create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t580/gma-mainboard.ads
 create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t580/gpio.c
 create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t580/hda_verb.c
 create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t580/include/variant/dgpu.h
 create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t580/memory_init_params.c
 create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t580/overridetree.cb

diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/Kconfig b/src/mainboard/lenovo/sklkbl_thinkpad/Kconfig
index 9c454e6f7f..bd84488762 100644
--- a/src/mainboard/lenovo/sklkbl_thinkpad/Kconfig
+++ b/src/mainboard/lenovo/sklkbl_thinkpad/Kconfig
@@ -35,6 +35,13 @@ config BOARD_LENOVO_T480S
 	select BOARD_LENOVO_SKLKBL_THINKPAD_COMMON
 	select VARIANT_HAS_DGPU
 
+config BOARD_LENOVO_T580
+	bool
+	select BOARD_LENOVO_SKLKBL_THINKPAD_COMMON
+	select MEC1653_HAS_DEBUG_UNLOCK
+	select VARIANT_HAS_DGPU
+
+
 if BOARD_LENOVO_SKLKBL_THINKPAD_COMMON
 
 config MAINBOARD_DIR
@@ -43,6 +50,7 @@ config MAINBOARD_DIR
 config VARIANT_DIR
 	default "t480" if BOARD_LENOVO_T480
 	default "t480s" if BOARD_LENOVO_T480S
+	default "t580" if BOARD_LENOVO_T580
 
 config OVERRIDE_DEVICETREE
 	default "variants/\$(CONFIG_VARIANT_DIR)/overridetree.cb"
@@ -50,6 +58,7 @@ config OVERRIDE_DEVICETREE
 config MAINBOARD_PART_NUMBER
 	default "T480" if BOARD_LENOVO_T480
 	default "T480s" if BOARD_LENOVO_T480S
+	default "T580" if BOARD_LENOVO_T580
 
 config CBFS_SIZE
 	default 0x900000
@@ -85,7 +94,7 @@ config THINKPADEC_HKEY_EISAID
 	default "LEN0268"
 
 config MEC1653_DEBUG_UNLOCK_KEY
-	default "7a41b149fe2101cf" if BOARD_LENOVO_T480
+	default "7a41b149fe2101cf" if BOARD_LENOVO_T480 || BOARD_LENOVO_T580
 
 config VARIANT_HAS_DGPU
 	bool
diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/Kconfig.name b/src/mainboard/lenovo/sklkbl_thinkpad/Kconfig.name
index abc273f387..21b9739e6f 100644
--- a/src/mainboard/lenovo/sklkbl_thinkpad/Kconfig.name
+++ b/src/mainboard/lenovo/sklkbl_thinkpad/Kconfig.name
@@ -5,3 +5,6 @@ config BOARD_LENOVO_T480
 
 config BOARD_LENOVO_T480S
 	bool "ThinkPad T480s"
+
+config BOARD_LENOVO_T580
+	bool "ThinkPad T580"
diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t580/data.vbt b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t580/data.vbt
new file mode 100644
index 0000000000000000000000000000000000000000..79b206a214f615f79ef35f8b09aca33e8da92d75
GIT binary patch
literal 4106
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zBE?|3Buzw3WKGn753&y?8eXhV#`qv=Vlceam_Xta`lQ6f7<n;@>zSYa&_cV>5aQ37
zJ@=k_?z!Kdd+y(<9SHSfU)NwP*wv0Ur9lIx3{ttALeY5Np-8YlcqkN$hr94AcmTdB
z|KkQgn&UP|el5@(JvNca`g-dKHrCh`iedN2k)dp+F_Ia7W@2O%6X7TZj~>lrGh>G*
zGHL7^*cU_tS7xE(L)kPQI6izNGuDa*7+Ir#S3~nIM9tsm4>UGu{zph|Zfyy)`X82A
zq&*z(PDEqD{%HIF#(Oam?F;txwReYNgP7=zcSb|e{`QE>jJbqIMo*3nJ^9oG`oeYC
zq-okt!t<l)GKNRSMjJ4g&0?=%GmgEP@yytBnRJ89jPaL16gU9R2`<n%->oK)M4?mE
zeIizgN<`3W1*{a5gs!A?)KG~D`VIlBMTO*~t|S#*0Y?kx5CFD{@Wtd@bP=>`1kW37
zhYm;;5fTe<H3f<yCM%4#cFhIgH2Pc$hvW$n(oeUop0=$-V<3?WIdm9;X=Mt8b;`6d
zTV-acacKVaVk>ynw(^)JRNyizy9e$1_G+niY1^`1s$JS%u;OXDzduiHs%^5QHJk?T
zh&6Lcvrh4sp+iI%5*0W_e3sblWKco8k$4-ipLh>(J8_(NkoYL^F!2fE)5Nb3zd?L~
z*qtJ12YvUhWLJRYgcM&a7C$K#!I^Z-NtfnyF5PMAbl0dY<y-|@0x>7pBg`-W5Xya%
zqzc$i`;ZsgrmG?6ni1Lne!3v@FbQleZBd(4Y0;7bRK5*mUaQMR1MW=sv&U=ffCqnc
z%(@uNx^8l3Di%w#uI0Kr+1-1cLT)Ond{%U6lPnyn`GCLdxI8caFZ{P7P~8bv-MKto
z->8VG%~mXG{+edf<FqFoB3%qRAc+!mf)A=70<};HDM*-EhiKljw*|d46(W=y2XqDU
zc?o=ck%9SE!bKv0y4Qg}>Bb9g^#eEi*p1)1)nDA~mK(P)wS}?03^PnU!Pser?=tlx
z#y)5G15<xv%;~}H9`#WV+vmYyk2>XHFM05NkNT;HUGd=09+j7vEMc>xwo5E7;c-cQ
zQDU!2_@ShJDY365{8dstGFvC(9$D>{*<&)kAggC(c3zh2RcFp|oy)CVW2On>m_&C^
z(jl4kO-`ZOS-y>~`{j!gnBuJCEg_$Dtd3A9NAM@B(U+^VVpJ2DvYtJVa<1KifzZZl
zaCaYS1G&QJ?oGOeEs*?-?x78VDc;I%$W5>jU<CxN9?tcErfZ{=g&0IW&_F|yCY|1r
z5GJw5O9|H^1TJspP9-9|*Eo5-$GcTeo?GyN%bOXKq?gT<;6vwLT{|+<r0bU!5XvZZ
zG-fg21b+3kc;cafi#<@Ib>!`}sG>;b&9{?WDJ2f48uEpdw}#dtVEnHcNg?kxBwEc<
zX5nk2)tuQv2=&G&Yc2AWt`b7QIbFgm-l{9i_DpZq66e<&qf7)I%*2u+Sqg$yuU}40
zr?sjc>#Q34fv2m3NHS84)gzhS0D2I%YE@?z;=qG!Avm!Fgd1KcByhbZX<=iOHH$o*
zM>CSvxiB{Q-Oq)iHCOfQ?wxva=VBkqO#~33%sN>sA=K%R%0Wd+QPvux>_{3fJxH;R
z#G%CDW0~xM!^4?>LBp8T%C!A7l<ilxLGt2$N>!-*PT=QdOY^tOV(}nl)C=TTLOa&M
eOC9896c`+&$14pxxHsW@zF`L7%sl-g#6JPZBg-fN

literal 0
HcmV?d00001

diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t580/gma-mainboard.ads b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t580/gma-mainboard.ads
new file mode 100644
index 0000000000..fcfbd75a92
--- /dev/null
+++ b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t580/gma-mainboard.ads
@@ -0,0 +1,19 @@
+-- SPDX-License-Identifier: GPL-2.0-or-later
+
+with HW.GFX.GMA;
+with HW.GFX.GMA.Display_Probing;
+
+use HW.GFX.GMA;
+use HW.GFX.GMA.Display_Probing;
+
+private package GMA.Mainboard is
+
+   ports : constant Port_List :=
+     (eDP,
+      DP1,
+      DP2,
+      HDMI1,
+      HDMI2,
+      others => Disabled);
+
+end GMA.Mainboard;
diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t580/gpio.c b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t580/gpio.c
new file mode 100644
index 0000000000..9c0da3c37e
--- /dev/null
+++ b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t580/gpio.c
@@ -0,0 +1,203 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <soc/gpio.h>
+#include "../../variant.h"
+
+/* FIXME: There are multiple GPIOs here that should be locked to prevent "TPM GPIO fail" style
+ * attacks. Unfortunately SKL/KBL GPIO locking *does not* work currently. */
+
+static const struct pad_config gpio_table[] = {
+
+	/* ------- GPIO Community 0 ------- */
+
+	/* ------- GPIO Group GPP_A ------- */
+	PAD_CFG_NF(GPP_A0, NONE, DEEP, NF1),				/* -KBRC */
+	PAD_CFG_NF(GPP_A1, NATIVE, DEEP, NF1),				/* LPC_AD0 */
+	PAD_CFG_NF(GPP_A2, NATIVE, DEEP, NF1),				/* LPC_AD1 */
+	PAD_CFG_NF(GPP_A3, NATIVE, DEEP, NF1),				/* LPC_AD2 */
+	PAD_CFG_NF(GPP_A4, NATIVE, DEEP, NF1),				/* LPC_AD3 */
+	PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1),				/* -LPC_FRAME */
+	PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1),				/* IRQSER */
+	PAD_CFG_NF(GPP_A7, NONE, DEEP, NF1),				/* -TPM_IRQ */
+	PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1),				/* -CLKRUN */
+	PAD_CFG_NF(GPP_A9, NATIVE, DEEP, NF1),				/* LPCCLK_EC_24M */
+	PAD_CFG_NF(GPP_A10, NATIVE, DEEP, NF1),				/* LPCCLK_DEBUG_24M */
+	PAD_NC(GPP_A11, NONE),
+	PAD_NC(GPP_A12, NONE),
+	PAD_CFG_NF(GPP_A13, NATIVE, DEEP, NF1),				/* -SUSWARN */
+	PAD_CFG_NF(GPP_A14, NATIVE, DEEP, NF1),				/* -SUS_STAT */
+	PAD_CFG_NF(GPP_A15, NATIVE, DEEP, NF1),				/* -SUSWARN */
+	PAD_NC(GPP_A16, NONE),
+	PAD_NC(GPP_A17, NONE),
+	PAD_NC(GPP_A18, NONE),
+	PAD_NC(GPP_A19, NONE),
+	PAD_NC(GPP_A20, NONE),
+	PAD_NC(GPP_A21, NONE),
+	PAD_NC(GPP_A22, NONE),
+	PAD_NC(GPP_A23, NONE),
+
+	/* ------- GPIO Group GPP_B ------- */
+	PAD_NC(GPP_B0, NONE),
+	PAD_NC(GPP_B1, NONE),
+	PAD_NC(GPP_B2, NONE),
+	PAD_NC(GPP_B3, NONE),
+	PAD_CFG_GPI_SCI(GPP_B4, NONE, DEEP, EDGE_SINGLE, INVERT),	/* -TBT_PLUG_EVENT */
+	PAD_CFG_NF(GPP_B5, NONE, DEEP, NF1),				/* -CLKREQ_PCIE0 */
+	PAD_CFG_NF(GPP_B6, NONE, DEEP, NF1),				/* -CLKREQ_PCIE4 */
+	PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1),				/* -CLKREQ_PCIE5 */
+	PAD_CFG_NF(GPP_B8, NONE, DEEP, NF1),				/* -CLKREQ_PCIE10 */
+	PAD_CFG_NF(GPP_B9, NONE, DEEP, NF1),				/* -CLKREQ_PCIE8 */
+	PAD_CFG_NF(GPP_B10, NONE, DEEP, NF1),				/* -CLKREQ_PCIE6 */
+	PAD_NC(GPP_B11, NONE),
+	PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1),				/* -PCH_SLP_S0 */
+	PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1),				/* -PLTRST */
+	PAD_CFG_NF(GPP_B14, NATIVE, DEEP, NF1),				/* PCH_SPKR */
+	PAD_CFG_GPO(GPP_B15, 1, DEEP),					/* NFC_DLREQ */
+	PAD_NC(GPP_B16, NONE),
+	PAD_NC(GPP_B17, NONE),
+	PAD_NC(GPP_B18, NONE),
+	PAD_NC(GPP_B19, NONE),
+	PAD_NC(GPP_B20, NONE),
+	PAD_NC(GPP_B21, NONE),
+	PAD_NC(GPP_B22, NONE),
+	PAD_NC(GPP_B23, NONE),
+
+	/* ------- GPIO Community 1 ------- */
+
+	/* ------- GPIO Group GPP_C ------- */
+	PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1),				/* SMB_CLK */
+	PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1),				/* SMB_DATA */
+	PAD_NC(GPP_C2, NONE),
+	PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1),				/* SML0_CLK */
+	PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1),				/* SML0_DATA */
+	PAD_NC(GPP_C5, NONE),
+	PAD_CFG_NF(GPP_C6, NONE, DEEP, NF1),				/* EC_SCL2 */
+	PAD_CFG_NF(GPP_C7, NONE, DEEP, NF1),				/* EC_SDA2 */
+	PAD_NC(GPP_C8, NONE),
+	PAD_NC(GPP_C9, NONE),
+	PAD_NC(GPP_C10, NONE),
+	PAD_NC(GPP_C11, NONE),
+	PAD_NC(GPP_C12, NONE),
+	PAD_NC(GPP_C13, NONE),
+	PAD_NC(GPP_C14, NONE),
+	PAD_NC(GPP_C15, NONE),
+	PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1),				/* I2C0_DATA */
+	PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1),				/* I2C0_CLK */
+	PAD_NC(GPP_C18, NONE),
+	PAD_NC(GPP_C19, NONE),
+	PAD_CFG_GPO(GPP_C20, 0, DEEP),					/* EPRIVACY_ON */
+	PAD_CFG_GPO(GPP_C21, 0, DEEP),					/* TBT_FORCE_PWR */
+	PAD_CFG_GPI_SCI(GPP_C22, NONE, DEEP, EDGE_SINGLE, INVERT),	/* -EC_SCI */
+	PAD_CFG_GPI_SCI(GPP_C23, NONE, DEEP, EDGE_SINGLE, INVERT),	/* -EC_WAKE */
+
+	/* ------- GPIO Group GPP_D ------- */
+	PAD_NC(GPP_D0, NONE),
+	PAD_NC(GPP_D1, NONE),
+	PAD_NC(GPP_D2, NONE),
+	PAD_NC(GPP_D3, NONE),
+	PAD_NC(GPP_D4, NONE),
+	PAD_NC(GPP_D5, NONE),
+	PAD_NC(GPP_D6, NONE),
+	PAD_NC(GPP_D7, NONE),
+	PAD_NC(GPP_D8, NONE),
+	PAD_CFG_GPI_TRIG_OWN(GPP_D9, UP_20K, DEEP, OFF, ACPI),		/* -DISCRETE_PRESENCE */
+	PAD_NC(GPP_D10, NONE),
+	PAD_CFG_GPI_TRIG_OWN(GPP_D11, UP_20K, DEEP, OFF, ACPI),		/* DGFX_VRAM_ID0 */
+	PAD_CFG_GPI_TRIG_OWN(GPP_D12, UP_20K, DEEP, OFF, ACPI),		/* DGFX_VRAM_ID1 */
+	PAD_NC(GPP_D13, NONE),
+	PAD_NC(GPP_D14, NONE),
+	PAD_NC(GPP_D15, NONE),
+	PAD_NC(GPP_D16, NONE),
+	PAD_CFG_GPO(GPP_D17, 0, DEEP),					/* DDI_PRIORITY1 */
+	PAD_NC(GPP_D18, NONE),
+	PAD_NC(GPP_D19, NONE),
+	PAD_NC(GPP_D20, NONE),
+	PAD_NC(GPP_D21, NONE),
+	PAD_CFG_GPI_TRIG_OWN(GPP_D22, UP_20K, DEEP, OFF, ACPI),		/* -NFC_DTCT */
+	PAD_NC(GPP_D23, NONE),
+
+	/* ------- GPIO Group GPP_E ------- */
+	PAD_NC(GPP_E0, NONE),
+	PAD_CFG_NF(GPP_E1, NONE, DEEP, NF1),				/* -WWAN_SATA_DTCT (always HIGH) */
+	PAD_CFG_NF(GPP_E2, NONE, DEEP, NF1),				/* -PE_DTCT */
+	PAD_CFG_GPI_TRIG_OWN(GPP_E3, NONE, DEEP, EDGE_SINGLE, ACPI),	/* -TBT_PLUG_EVENT */
+	PAD_CFG_GPO(GPP_E4, 1, DEEP),					/* NFC_ON */
+	PAD_NC(GPP_E5, NONE),
+	PAD_CFG_NF(GPP_E6, NONE, RSMRST, NF1),				/* SATA2_DEVSLP */
+	PAD_NC(GPP_E7, NONE),
+	PAD_NC(GPP_E8, NONE),
+	PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1),				/* -USB_PORT0_OC0 (AON port) */
+	PAD_CFG_NF(GPP_E10, NONE, DEEP, NF1),				/* -USB_PORT1_OC1 (regular port) */
+	PAD_NC(GPP_E11, NONE),
+	PAD_CFG_GPI_APIC_HIGH(GPP_E12, NONE, DEEP),			/* NFC_INT */
+	PAD_CFG_NF(GPP_E13, NONE, DEEP, NF1),				/* DDIP1_HPD */
+	PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1),				/* DDIP2_HPD */
+	PAD_NC(GPP_E15, NONE),
+	PAD_NC(GPP_E16, NONE),
+	PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1),				/* EDP_HPD */
+	PAD_NC(GPP_E18, NONE),
+	PAD_NC(GPP_E19, NONE),
+	PAD_CFG_NF(GPP_E20, NONE, DEEP, NF1),				/* DDIP2_CTRLCLK */
+	PAD_CFG_NF(GPP_E21, NONE, DEEP, NF1),				/* DDIP2_CTRLDATA */
+	PAD_CFG_TERM_GPO(GPP_E22, 0, UP_20K, RSMRST),			/* -GPU_RST */
+	PAD_CFG_TERM_GPO(GPP_E23, 0, UP_20K, RSMRST),			/* 1R8VIDEO_AON_ON */
+
+	/* ------- GPIO Community 2 ------- */
+
+	/* -------- GPIO Group GPD -------- */
+	PAD_CFG_NF(GPD0, NONE, PWROK, NF1),				/* -BATLOW */
+	PAD_CFG_NF(GPD1, NATIVE, PWROK, NF1),				/* AC_PRESENT */
+	PAD_CFG_NF(GPD2, NATIVE, PWROK, NF1),				/* -LANWAKE */
+	PAD_CFG_NF(GPD3, UP_20K, PWROK, NF1),				/* -PWRSW_EC */
+	PAD_CFG_NF(GPD4, NONE, PWROK, NF1),				/* -PCH_SLP_S3 */
+	PAD_CFG_NF(GPD5, NONE, PWROK, NF1),				/* -PCH_SLP_S4 */
+	PAD_CFG_NF(GPD6, NONE, PWROK, NF1),				/* -PCH_SLP_M */
+	PAD_NC(GPD7, NONE),
+	PAD_CFG_NF(GPD8, NONE, PWROK, NF1),				/* SUSCLK_32K */
+	PAD_CFG_NF(GPD9, NONE, PWROK, NF1),				/* -PCH_SLP_WLAN */
+	PAD_CFG_NF(GPD10, NONE, PWROK, NF1),				/* -PCH_SLP_S5 */
+	PAD_CFG_NF(GPD11, NONE, PWROK, NF1),				/* LANPHYPC */
+
+	/* ------- GPIO Community 3 ------- */
+
+	/* ------- GPIO Group GPP_F ------- */
+	PAD_NC(GPP_F0, NONE),
+	PAD_CFG_GPI_TRIG_OWN(GPP_F1, NONE, DEEP, OFF, ACPI),		/* GC6_FB_EN */
+	PAD_CFG_GPO(GPP_F2, 1, DEEP),					/* -GPU_EVENT */
+	PAD_CFG_GPI_TRIG_OWN(GPP_F3, NONE, DEEP, OFF, ACPI),		/* DGFX_PWRGD */
+	PAD_CFG_GPO(GPP_F4, 1, DEEP),					/* -WWAN_RESET */
+	PAD_NC(GPP_F5, NONE),
+	PAD_CFG_GPI_TRIG_OWN(GPP_F6, UP_20K, DEEP, OFF, ACPI),		/* -MIC_HW_EN (R961 to GND) */
+	PAD_CFG_GPI_TRIG_OWN(GPP_F7, UP_20K, DEEP, OFF, ACPI),		/* -INT_MIC_DTCT */
+	PAD_CFG_GPI_TRIG_OWN(GPP_F8, UP_20K, DEEP, OFF, ACPI),		/* WWAN_CFG0 */
+	PAD_CFG_GPI_TRIG_OWN(GPP_F9, UP_20K, DEEP, OFF, ACPI),		/* WWAN_CFG1 */
+	PAD_CFG_GPI_TRIG_OWN(GPP_F10, UP_20K, DEEP, OFF, ACPI),		/* WWAN_CFG2 */
+	PAD_CFG_GPI_TRIG_OWN(GPP_F11, UP_20K, DEEP, OFF, ACPI),		/* WWAN_CFG3 */
+	PAD_CFG_GPI_TRIG_OWN(GPP_F12, UP_20K, DEEP, OFF, ACPI),		/* PLANARID0 */
+	PAD_CFG_GPI_TRIG_OWN(GPP_F13, UP_20K, DEEP, OFF, ACPI),		/* PLANARID1 */
+	PAD_CFG_GPI_TRIG_OWN(GPP_F14, UP_20K, DEEP, OFF, ACPI),		/* PLANARID2 */
+	PAD_CFG_GPI_TRIG_OWN(GPP_F15, UP_20K, DEEP, OFF, ACPI),		/* PLANARID3 */
+	PAD_NC(GPP_F16, NONE),
+	PAD_NC(GPP_F17, NONE),
+	PAD_NC(GPP_F18, NONE),
+	PAD_NC(GPP_F19, NONE),
+	PAD_NC(GPP_F20, NONE),
+	PAD_NC(GPP_F21, NONE),
+	PAD_CFG_GPI_TRIG_OWN(GPP_F22, UP_20K, DEEP, OFF, ACPI),		/* -INTRUDER_PCH */
+	PAD_CFG_GPI_TRIG_OWN(GPP_F23, UP_20K, DEEP, OFF, ACPI),		/* -SC_DTCT */
+
+	/* ------- GPIO Group GPP_G ------- */
+	PAD_NC(GPP_G0, NONE),
+	PAD_NC(GPP_G1, NONE),
+	PAD_NC(GPP_G2, NONE),
+	PAD_NC(GPP_G3, NONE),
+	PAD_CFG_GPO(GPP_G4, 0, DEEP),					/* TBT_RTD3_PWR_EN */
+	PAD_CFG_GPO(GPP_G5, 0, DEEP),					/* TBT_FORCE_USB_PWR */
+	PAD_CFG_GPO(GPP_G6, 0, DEEP),					/* -TBT_PERST */
+	PAD_CFG_GPI_SCI(GPP_G7, NONE, DEEP, LEVEL, INVERT),		/* -TBT_PCIE_WAKE */
+};
+
+void variant_config_gpios(void)
+{
+	gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table));
+}
diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t580/hda_verb.c b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t580/hda_verb.c
new file mode 100644
index 0000000000..65245c8e21
--- /dev/null
+++ b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t580/hda_verb.c
@@ -0,0 +1,89 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <device/azalia_device.h>
+
+const u32 cim_verb_data[] = {
+	0x10ec0257, // Vendor/Device ID: Realtek ALC257
+	0x17aa225a, // Subsystem ID
+	11,
+	AZALIA_SUBVENDOR(0, 0x17aa225a),
+
+	AZALIA_PIN_CFG(0, 0x12, AZALIA_PIN_DESC(
+		AZALIA_INTEGRATED,
+		AZALIA_INTERNAL,
+		AZALIA_MIC_IN,
+		AZALIA_OTHER_DIGITAL,
+		AZALIA_COLOR_UNKNOWN,
+		AZALIA_NO_JACK_PRESENCE_DETECT,
+		2, 0
+	)),
+	AZALIA_PIN_CFG(0, 0x13, 0x40000000), // does not describe a jack or internal device
+	AZALIA_PIN_CFG(0, 0x14, AZALIA_PIN_DESC(
+		AZALIA_INTEGRATED,
+		AZALIA_INTERNAL,
+		AZALIA_SPEAKER,
+		AZALIA_OTHER_ANALOG,
+		AZALIA_COLOR_UNKNOWN,
+		AZALIA_NO_JACK_PRESENCE_DETECT,
+		1, 0
+	)),
+	AZALIA_PIN_CFG(0, 0x18, AZALIA_PIN_CFG_NC(0)),
+	AZALIA_PIN_CFG(0, 0x19, AZALIA_PIN_DESC(
+		AZALIA_JACK,
+		AZALIA_EXTERNAL_PRIMARY_CHASSIS | AZALIA_RIGHT,
+		AZALIA_MIC_IN,
+		AZALIA_STEREO_MONO_1_8,
+		AZALIA_BLACK,
+		AZALIA_JACK_PRESENCE_DETECT,
+		3, 0
+	)),
+	AZALIA_PIN_CFG(0, 0x1a, AZALIA_PIN_CFG_NC(0)),
+	AZALIA_PIN_CFG(0, 0x1b, AZALIA_PIN_CFG_NC(0)),
+	AZALIA_PIN_CFG(0, 0x1d, 0x40661b45), // does not describe a jack or internal device
+	AZALIA_PIN_CFG(0, 0x1e, AZALIA_PIN_CFG_NC(0)),
+	AZALIA_PIN_CFG(0, 0x21, AZALIA_PIN_DESC(
+		AZALIA_JACK,
+		AZALIA_EXTERNAL_PRIMARY_CHASSIS | AZALIA_RIGHT,
+		AZALIA_HP_OUT,
+		AZALIA_STEREO_MONO_1_8,
+		AZALIA_BLACK,
+		AZALIA_JACK_PRESENCE_DETECT,
+		1, 15
+	)),
+
+	0x8086280b, // Vendor/Device ID: Intel Kabylake HDMI
+	0x80860101, // Subsystem ID
+	4,
+	AZALIA_SUBVENDOR(2, 0x80860101),
+
+	AZALIA_PIN_CFG(2, 0x05, AZALIA_PIN_DESC(
+		AZALIA_JACK,
+		AZALIA_DIGITAL_DISPLAY,
+		AZALIA_DIGITAL_OTHER_OUT,
+		AZALIA_OTHER_DIGITAL,
+		AZALIA_COLOR_UNKNOWN,
+		AZALIA_JACK_PRESENCE_DETECT,
+		1, 0
+	)),
+	AZALIA_PIN_CFG(2, 0x06, AZALIA_PIN_DESC(
+		AZALIA_JACK,
+		AZALIA_DIGITAL_DISPLAY,
+		AZALIA_DIGITAL_OTHER_OUT,
+		AZALIA_OTHER_DIGITAL,
+		AZALIA_COLOR_UNKNOWN,
+		AZALIA_JACK_PRESENCE_DETECT,
+		1, 0
+	)),
+	AZALIA_PIN_CFG(2, 0x07, AZALIA_PIN_DESC(
+		AZALIA_JACK,
+		AZALIA_DIGITAL_DISPLAY,
+		AZALIA_DIGITAL_OTHER_OUT,
+		AZALIA_OTHER_DIGITAL,
+		AZALIA_COLOR_UNKNOWN,
+		AZALIA_JACK_PRESENCE_DETECT,
+		1, 0
+	)),
+};
+
+const u32 pc_beep_verbs[] = {};
+AZALIA_ARRAY_SIZES;
diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t580/include/variant/dgpu.h b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t580/include/variant/dgpu.h
new file mode 100644
index 0000000000..deb0cf4c1e
--- /dev/null
+++ b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t580/include/variant/dgpu.h
@@ -0,0 +1,15 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef _VARIANT_DGPU_H_
+#define _VARIANT_DGPU_H_
+
+#define GPIO_GPU_RST			GPP_E22 // active low
+#define GPIO_1R8VIDEO_AON_ON		GPP_E23
+
+#define GPIO_DGFX_PWRGD			GPP_F3
+
+#define GPIO_DISCRETE_PRESENCE		GPP_D9	// active low
+#define GPIO_DGFX_VRAM_ID0		GPP_D11
+#define GPIO_DGFX_VRAM_ID1		GPP_D12
+
+#endif
diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t580/memory_init_params.c b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t580/memory_init_params.c
new file mode 100644
index 0000000000..926cdf021a
--- /dev/null
+++ b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t580/memory_init_params.c
@@ -0,0 +1,20 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <soc/romstage.h>
+#include <spd_bin.h>
+
+void mainboard_memory_init_params(FSPM_UPD *mupd)
+{
+	FSP_M_CONFIG *mem_cfg = &mupd->FspmConfig;
+	mem_cfg->DqPinsInterleaved = false;			/* DDR_DQ in interleave mode */
+	mem_cfg->CaVrefConfig      = 2;				/* VREF_CA to CH_A and VREF_DQ_B to CH_B */
+	mem_cfg->MemorySpdDataLen  = CONFIG_DIMM_SPD_SIZE;
+
+	/* Get SPD for memory slots */
+	struct spd_block blk = { .addr_map = { 0x50, 0x51, } };
+	get_spd_smbus(&blk);
+	dump_spd_info(&blk);
+
+	mem_cfg->MemorySpdPtr00    = (uintptr_t)blk.spd_array[0];
+	mem_cfg->MemorySpdPtr10    = (uintptr_t)blk.spd_array[1];
+}
diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t580/overridetree.cb b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t580/overridetree.cb
new file mode 100644
index 0000000000..34320187ad
--- /dev/null
+++ b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t580/overridetree.cb
@@ -0,0 +1,96 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
+chip soc/intel/skylake
+	device domain 0 on
+		device ref south_xhci on
+			register "usb2_ports" = "{
+				[0] = USB2_PORT_MID(OC1),		// USB-A
+				[1] = USB2_PORT_MID(OC0),		// USB-A (always on)
+				[2] = USB2_PORT_MID(OC_SKIP),		// JSC-1 (smartcard slot)
+				[3] = USB2_PORT_MID(OC_SKIP),		// USB-C (charging port)
+				[4] = USB2_PORT_MID(OC_SKIP),		// JCAM1 (IR camera)
+				[5] = USB2_PORT_MID(OC_SKIP),		// JWWAN1 (M.2 WWAN USB)
+				[6] = USB2_PORT_MID(OC_SKIP),		// JWLAN1 (M.2 WLAN USB)
+				[7] = USB2_PORT_MID(OC_SKIP),		// JCAM1 (webcam)
+				[8] = USB2_PORT_MID(OC_SKIP),		// JFPR1 (fingerprint reader)
+				[9] = USB2_PORT_MID(OC_SKIP),		// JLCD1 (touch panel)
+			}"
+			register "usb3_ports" = "{
+				[0] = USB3_PORT_DEFAULT(OC1),		// USB-A
+				[1] = USB3_PORT_DEFAULT(OC0),		// USB-A (always on)
+				[2] = USB3_PORT_DEFAULT(OC_SKIP),	// RTS5344S (SD card reader)
+				[3] = USB3_PORT_DEFAULT(OC_SKIP),	// USB-C (charging port)
+			}"
+		end
+
+		# PCIe controller 1 - 1x4
+		#   PCIE 1-4   - RP1  - dGPU - CLKOUT0 - CLKREQ0
+		#
+		# PCIe controller 2 - 2x1+1x2 (lane reversal)
+		#   PCIE 5     - GBE  - GBE  - CLKOUT1 - CLKREQ1 (clobbers RP8)
+		#   PCIE 6     - RP7  - WLAN - CLKOUT2 - CLKREQ2
+		#   PCIE 7-8   - RP5  - WWAN - CLKOUT3 - CLKREQ3
+		#
+		# PCIe controller 3 - 2x2
+		#   PCIE 9-10  - RP9  - TB3  - CLKOUT4 - CLKREQ4
+		#   PCIE 11-12 - RP11 - SSD  - CLKOUT5 - CLKREQ5
+
+		# dGPU - x4
+		device ref pcie_rp1 on
+			register "PcieRpClkReqSupport[0]"		= "true"
+			register "PcieRpClkReqNumber[0]"		= "0"
+			register "PcieRpClkSrcNumber[0]"		= "0"
+			register "PcieRpAdvancedErrorReporting[0]"	= "true"
+			register "PcieRpLtrEnable[0]"			= "true"
+			device generic 0 alias dgpu on end
+		end
+
+		# Ethernet (clobbers RP8)
+		device ref gbe on
+			register "LanClkReqSupported"			= "true"
+			register "LanClkReqNumber"			= "1"
+			register "EnableLanLtr"				= "true"
+			register "EnableLanK1Off"			= "true"
+		end
+
+		# M.2 WLAN - x1
+		device ref pcie_rp7 on
+			register "PcieRpClkReqSupport[6]"		= "true"
+			register "PcieRpClkReqNumber[6]"		= "2"
+			register "PcieRpClkSrcNumber[6]"		= "2"
+			register "PcieRpAdvancedErrorReporting[6]"	= "true"
+			register "PcieRpLtrEnable[6]"			= "true"
+			smbios_slot_desc "SlotTypeM2Socket1_DP" "SlotLengthOther" "M.2/A 2230" "SlotDataBusWidth1X"
+		end
+
+		# M.2 WWAN - x2
+		device ref pcie_rp5 on
+			register "PcieRpClkReqSupport[4]"		= "true"
+			register "PcieRpClkReqNumber[4]"		= "5"
+			register "PcieRpClkSrcNumber[4]"		= "5"
+			register "PcieRpAdvancedErrorReporting[4]"	= "true"
+			register "PcieRpLtrEnable[4]"			= "true"
+			smbios_slot_desc "SlotTypeM2Socket2" "SlotLengthOther" "M.2/B 3042/2242" "SlotDataBusWidth2X"
+		end
+
+		# TB3 (Alpine Ridge LP) - x2
+		device ref pcie_rp9 on
+			register "PcieRpClkReqSupport[8]"		= "true"
+			register "PcieRpClkReqNumber[8]"		= "4"
+			register "PcieRpClkSrcNumber[8]"		= "4"
+			register "PcieRpAdvancedErrorReporting[8]"	= "true"
+			register "PcieRpLtrEnable[8]"			= "true"
+			register "PcieRpHotPlug[8]"			= "true"
+		end
+
+		# M.2 2280 caddy - x2
+		device ref pcie_rp11 on
+			register "PcieRpClkReqSupport[10]"		= "true"
+			register "PcieRpClkReqNumber[10]"		= "3"
+			register "PcieRpClkSrcNumber[10]"		= "3"
+			register "PcieRpAdvancedErrorReporting[10]"	= "true"
+			register "PcieRpLtrEnable[10]"			= "true"
+			smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M.2/M 2280 Sub Card" "SlotDataBusWidth2X"
+		end
+	end
+end

From 660f71e7046588d8a33d9bb58b146af5d4fe77a7 Mon Sep 17 00:00:00 2001
From: John Su <john_su@compal.corp-partner.google.com>
Date: Tue, 14 Oct 2025 17:45:07 +0800
Subject: [PATCH 2264/3886] mb/google/trulo/var/uldrenite: Set GPP_E16 to NC
 for non-WWAN SKU

For non-WWAN SKUs, the GPP_E16 (WWAN_PCIE_WAKE_ODL) pin is configured
as NC.

BUG=b:448550221
BRANCH=firmware-trulo-15217.771.B
TEST=emerge-nissa coreboot chromeos-bootimage

Change-Id: I85614b6ba25613efdbb1714d6e0a9653981be3e4
Signed-off-by: John Su <john_su@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89563
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/google/brya/variants/uldrenite/variant.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/src/mainboard/google/brya/variants/uldrenite/variant.c b/src/mainboard/google/brya/variants/uldrenite/variant.c
index 0cc6b3972f..c096e9fbbf 100644
--- a/src/mainboard/google/brya/variants/uldrenite/variant.c
+++ b/src/mainboard/google/brya/variants/uldrenite/variant.c
@@ -33,6 +33,8 @@ static const struct pad_config touchscreen_disable_pads[] = {
 static const struct pad_config lte_disable_pads[] = {
 	/* A8  : WWAN_RF_DISABLE_ODL */
 	PAD_NC(GPP_A8, NONE),
+	/* E16 : WWAN_PCIE_WAKE_ODL */
+	PAD_NC(GPP_E16, NONE),
 	/* F12 : WWAN_RST_L */
 	PAD_NC_LOCK(GPP_F12, NONE, LOCK_CONFIG),
 	/* F13 : PLTRST_WWAN# */

From fe26234cf2806d2be182282a469732da643e47cc Mon Sep 17 00:00:00 2001
From: John Su <john_su@compal.corp-partner.google.com>
Date: Tue, 14 Oct 2025 18:15:34 +0800
Subject: [PATCH 2265/3886] mb/google/trulo/var/uldrenite: Update DPTF
 parameters

Update the DPTF parameters as provided by thermal team.

1. Adjust the PSV threshold value of the Passive Policy.

BUG=b:449890912
BRANCH=firmware-trulo-15217.771.B
TEST=build test firmware and verified by thermal team

Change-Id: I8be7da7550994f6a408e2c5bbc6ae4d31fa22ada
Signed-off-by: John Su <john_su@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89564
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
---
 .../google/brya/variants/uldrenite/overridetree.cb          | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/src/mainboard/google/brya/variants/uldrenite/overridetree.cb b/src/mainboard/google/brya/variants/uldrenite/overridetree.cb
index be87bc8bb4..157e0fcc29 100644
--- a/src/mainboard/google/brya/variants/uldrenite/overridetree.cb
+++ b/src/mainboard/google/brya/variants/uldrenite/overridetree.cb
@@ -204,9 +204,9 @@ chip soc/intel/alderlake
 				## Passive Policy
 				register "policies.passive" = "{
 					[0] = DPTF_PASSIVE(CPU,         CPU,           95, 5000),
-					[1] = DPTF_PASSIVE(CPU,         TEMP_SENSOR_0, 85, 5000),
-					[2] = DPTF_PASSIVE(CPU,         TEMP_SENSOR_1, 85, 5000),
-					[3] = DPTF_PASSIVE(CPU,         TEMP_SENSOR_2, 85, 5000),
+					[1] = DPTF_PASSIVE(CPU,         TEMP_SENSOR_0, 90, 5000),
+					[2] = DPTF_PASSIVE(CPU,         TEMP_SENSOR_1, 90, 5000),
+					[3] = DPTF_PASSIVE(CPU,         TEMP_SENSOR_2, 90, 5000),
 				}"
 
 				## Critical Policy

From 85d7a1c85f1ed0fe2373ce7bee7a009c119b0d47 Mon Sep 17 00:00:00 2001
From: Sergii Dmytruk <sergii.dmytruk@3mdeb.com>
Date: Fri, 22 Oct 2021 01:04:49 +0300
Subject: [PATCH 2266/3886] drivers/ipmi: add Block Transfer (BT) interface

Unlike already implemented Keyboard Controller Style (KCS) interface
Block Transfer interface is not byte-oriented and implies that device is
capable of buffering a command before processing it.  Another difference
is that polling can be replaced with interrupts, though this isn't used
by this implementation.

More details can be found in "Intelligent Platform Management Interface
Specification", v2.0, Rev. 1.1:
https://www.intel.com/content/dam/www/public/us/en/documents/specification-updates/ipmi-intelligent-platform-mgt-interface-spec-2nd-gen-v2-0-spec-update.pdf

This was initially tested on Talos II (OpenPower platform) by Raptor
Computing Systems.  Later versions were tested using QEMU and ipmi_sim
from OpenIPMI project as well as QEMU's builtin BMC simulator.

Change-Id: Idb67972d1c38bbae04c7b4de3405350c229a05b9
Signed-off-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67057
Reviewed-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 Documentation/drivers/index.md     |   1 +
 Documentation/drivers/ipmi_bt.md   |  79 ++++++++++
 src/drivers/ipmi/Kconfig           |  28 ++++
 src/drivers/ipmi/Makefile.mk       |  10 ++
 src/drivers/ipmi/ipmi_bt.c         | 230 +++++++++++++++++++++++++++++
 src/drivers/ipmi/ipmi_bt.h         |  11 ++
 src/drivers/ipmi/ipmi_bt_ops.c     | 121 +++++++++++++++
 src/drivers/ipmi/ipmi_ops_premem.c |   7 +-
 8 files changed, 486 insertions(+), 1 deletion(-)
 create mode 100644 Documentation/drivers/ipmi_bt.md
 create mode 100644 src/drivers/ipmi/ipmi_bt.c
 create mode 100644 src/drivers/ipmi/ipmi_bt.h
 create mode 100644 src/drivers/ipmi/ipmi_bt_ops.c

diff --git a/Documentation/drivers/index.md b/Documentation/drivers/index.md
index 45c491bbaa..a797416008 100644
--- a/Documentation/drivers/index.md
+++ b/Documentation/drivers/index.md
@@ -21,6 +21,7 @@ Some of the drivers currently available include:
 CFR <cfr.md>
 CFR use within coreboot <cfr_internal.md>
 Intel DPTF <dptf.md>
+IPMI BT (Block Transfer) <ipmi_bt.md>
 IPMI KCS <ipmi_kcs.md>
 SMMSTORE <smmstore.md>
 SMMSTOREv2 <smmstorev2.md>
diff --git a/Documentation/drivers/ipmi_bt.md b/Documentation/drivers/ipmi_bt.md
new file mode 100644
index 0000000000..bcd68a02e8
--- /dev/null
+++ b/Documentation/drivers/ipmi_bt.md
@@ -0,0 +1,79 @@
+# IPMI Block Transfer (BT) driver
+
+The driver can be found in `src/drivers/ipmi/` (same as KCS). It works with BMC
+that provides a BT I/O interface as specified in the [IPMI] standard.  See
+"Intelligent Platform Management Interface Specification", v2.0, Rev. 1.1 for
+more details on the interface and IPMI in general.
+
+The driver detects the IPMI version and reserves the I/O space in coreboot's
+resource allocator.
+
+## For developers
+
+To use the driver, select the `IPMI_BT` Kconfig and add the following PNP
+device (in example for the BT at 0xe4):
+
+```
+chip drivers/ipmi
+    device pnp e4.0 on end        # IPMI BT
+end
+```
+
+**Note:** The I/O base address must be aligned to 4.
+
+The following settings can be set in a device tree:
+
+```{eval-rst}
++------------------+--------------+-------------------------------------------+
+|  Setting         | Type/Default | Description/Purpose                       |
++==================+==============+===========================================+
+| wait_for_bmc     | | Boolean    | Wait for BMC to boot. This can be used if |
+|                  | | false      | the BMC takes a long time to boot after   |
+|                  |              | PoR.                                      |
++------------------+--------------+-------------------------------------------+
+| bmc_boot_timeout | | Integer    | The timeout in seconds to wait for the    |
+|                  | | 0          | IPMI service to be loaded.  Will be used  |
+|                  |              | if wait_for_bmc is true.                  |
++------------------+--------------+-------------------------------------------+
+```
+
+## Debugging/testing the driver
+
+`ipmi_sim` from [OpenIPMI] project can be used by running `ipmi_sim -d` in one
+console to watch what's being sent/received and starting QEMU like this in
+another console:
+
+```
+qemu-system-x86_64 \
+    -M q35,smm=on \
+    -bios build/coreboot.rom \
+    -chardev socket,id=ipmichr0,host=localhost,port=9002,reconnect=10 \
+    -device ipmi-bmc-extern,chardev=ipmichr0,id=bmc0 \
+    -device isa-ipmi-bt,bmc=bmc0,irq=0 \
+    -serial stdio
+```
+
+A simpler alternative is to use QEMU's builtin BMC simulator:
+
+```
+qemu-system-x86_64 \
+    -M q35,smm=on \
+    -bios build/coreboot.rom \
+    -device ipmi-bmc-sim,id=bmc0 \
+    -device isa-ipmi-bt,bmc=bmc0,irq=0 \
+    -serial stdio
+```
+
+## References
+
+Useful links on the subject:
+ * README of `ipmi_sim`:
+   <https://github.com/wrouesnel/openipmi/blob/master/lanserv/README.ipmi_sim>
+ * slides about OpenIPMI:
+   <https://www.linux-kvm.org/images/7/76/03x08-Juniper-Corey_Minyard-UsingIPMIinQEMU.ods.pdf>
+ * a usage example: <https://github.com/dhilst/qemu-ipmi>
+ * old docs (the options are still there, but no longer have a dedicated page in
+   modern documentation): <https://hskinnemoen.github.io/qemu/specs/ipmi.html>
+
+[IPMI]: https://www.intel.com/content/dam/www/public/us/en/documents/specification-updates/ipmi-intelligent-platform-mgt-interface-spec-2nd-gen-v2-0-spec-update.pdf
+[OpenIPMI]: https://github.com/wrouesnel/openipmi
diff --git a/src/drivers/ipmi/Kconfig b/src/drivers/ipmi/Kconfig
index abfcade90a..101a781b55 100644
--- a/src/drivers/ipmi/Kconfig
+++ b/src/drivers/ipmi/Kconfig
@@ -55,3 +55,31 @@ config DRIVERS_IPMI_SUPERMICRO_OEM
 	  The following features are implemented:
 	  * Communicates the BIOS version to the BMC
 	  * Communicates the BIOS date to the BMC
+
+config IPMI_BT
+	bool
+	default n
+	depends on !IPMI_KCS
+
+config IPMI_BT_ROMSTAGE
+	bool
+	default n
+	depends on IPMI_BT
+	help
+	  IPMI BT support in romstage.
+
+config BMC_BT_BASE
+	hex
+	default 0xe4
+	depends on IPMI_BT
+	help
+	  The PNP base address of BMC BT. It must be equal to the
+	  pnp port value defined in devicetree for chip drivers/ipmi.
+
+config IPMI_TIMEOUT_MS
+	int
+	default 5000
+	depends on IPMI_BT || IPMI_KCS
+	help
+	  The time unit is millisecond for each IPMI transfer.
+	  The default is suitable for implementations using polling.
diff --git a/src/drivers/ipmi/Makefile.mk b/src/drivers/ipmi/Makefile.mk
index ade7147030..c1e2adae3e 100644
--- a/src/drivers/ipmi/Makefile.mk
+++ b/src/drivers/ipmi/Makefile.mk
@@ -11,3 +11,13 @@ romstage-$(CONFIG_IPMI_KCS_ROMSTAGE) += ipmi_ops_premem.c
 romstage-$(CONFIG_IPMI_KCS_ROMSTAGE) += ipmi_kcs.c
 romstage-$(CONFIG_IPMI_KCS_ROMSTAGE) += ipmi_ops.c
 smm-$(CONFIG_SOC_RAS_BMC_SEL) += ipmi_kcs.c
+
+ramstage-$(CONFIG_IPMI_BT) += ipmi_if.c
+ramstage-$(CONFIG_IPMI_BT) += ipmi_bt.c
+ramstage-$(CONFIG_IPMI_BT) += ipmi_bt_ops.c
+ramstage-$(CONFIG_IPMI_BT) += ipmi_ops.c
+ramstage-$(CONFIG_IPMI_BT) += ipmi_fru.c
+romstage-$(CONFIG_IPMI_BT_ROMSTAGE) += ipmi_if.c
+romstage-$(CONFIG_IPMI_BT_ROMSTAGE) += ipmi_ops_premem.c
+romstage-$(CONFIG_IPMI_BT_ROMSTAGE) += ipmi_bt.c
+romstage-$(CONFIG_IPMI_BT_ROMSTAGE) += ipmi_ops.c
diff --git a/src/drivers/ipmi/ipmi_bt.c b/src/drivers/ipmi/ipmi_bt.c
new file mode 100644
index 0000000000..511f664834
--- /dev/null
+++ b/src/drivers/ipmi/ipmi_bt.c
@@ -0,0 +1,230 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+/*
+ * IPMI specification:
+ * https://www.intel.com/content/dam/www/public/us/en/documents/specification-updates/ipmi-intelligent-platform-mgt-interface-spec-2nd-gen-v2-0-spec-update.pdf
+ *
+ * LUN seems to be always zero.
+ */
+
+#include "ipmi_bt.h"
+
+#include <arch/io.h>
+#include <console/console.h>
+#include <stdint.h>
+#include <string.h>
+#include <timer.h>
+
+#include "ipmi_if.h"
+
+/*
+ * 11.6.3 BT Host to BMC Buffer (HOST2BMC)
+ * "The buffer must be a minimum of 64-bytes deep."  This includes the length byte for
+ * convenience of the implementation.
+ */
+#define MAX_SEND_SIZE    64
+/*
+ * 11.1 BT Interface-BMC Request Message Format
+ * The length field is not considered part of the message on receiving (it's part of framing).
+ */
+#define MAX_RECEIVE_SIZE 255
+/*
+ * 11.1 BT Interface-BMC Request Message Format
+ * 4 leading bytes form a frame for the message.
+ */
+#define MAX_PAYLOAD_SIZE (MAX_SEND_SIZE - 4)
+
+#define BT_CTRL_REG  0 // Typical address of BT_CTRL is 0xE4
+#define HOST2BMC_REG 1 // Typical address of HOST2BMC is 0xE5
+#define BMC2HOST_REG 1 // Typical address of BMC2HOST is 0xE5
+
+/* Bits of BT_CTRL */
+#define B_BUSY     BIT(7)
+#define H_BUSY     BIT(6)
+#define OEM0       BIT(5)
+#define SMS_ATN    BIT(4)
+#define B2H_ATN    BIT(3)
+#define H2B_ATN    BIT(2)
+#define CLR_RD_PTR BIT(1)
+#define CLR_WR_PTR BIT(0)
+
+static enum cb_err wait_for_control_bits(uint16_t port, uint8_t mask, uint8_t expected)
+{
+	uint16_t bt_ctrl_port = port + BT_CTRL_REG;
+	if (!wait_ms(CONFIG_IPMI_TIMEOUT_MS, (inb(bt_ctrl_port) & mask) == expected)) {
+		printk(BIOS_ERR, "%s(0x%04x, 0x%02x, 0x%02x) timeout!\n",
+		       __func__, port, mask, expected);
+		return CB_ERR;
+	}
+
+	return CB_SUCCESS;
+}
+
+enum cb_err ipmi_bt_clear(uint16_t port)
+{
+	uint8_t bt_ctrl;
+
+	/*
+	 * First, make sure H_BUSY is set so BMC won't try to write new commands
+	 * while we're resetting pointers.
+	 */
+	outb(H_BUSY, port + BT_CTRL_REG);
+
+	/* If BMC is already in the process of writing, wait until it's done */
+	if (wait_for_control_bits(port, B_BUSY, 0) == CB_ERR)
+		return CB_ERR;
+
+	bt_ctrl = inb(port + BT_CTRL_REG);
+
+	printk(BIOS_SPEW, "%s(): BT_CTRL = 0x%02x\n", __func__, bt_ctrl);
+
+	/*
+	 * Clear all bits which are already set (they are either toggle bits or
+	 * write-1-to-clear) and reset buffer pointers. This also clears H_BUSY.
+	 */
+	outb(bt_ctrl | CLR_RD_PTR | CLR_WR_PTR, port + BT_CTRL_REG);
+
+	return CB_SUCCESS;
+}
+
+static enum cb_err ipmi_bt_send(uint16_t port, uint8_t addr, uint8_t cmd,
+				const uint8_t *payload, uint8_t payload_len,
+				uint8_t seq_num)
+{
+	uint16_t i;
+	uint16_t len;
+	uint8_t buf[MAX_SEND_SIZE];
+
+	len = 4 + payload_len;
+
+	/* The length doesn't include the length byte. */
+	buf[0] = len - 1;
+	buf[1] = addr;
+	buf[2] = seq_num;
+	buf[3] = cmd;
+	memcpy(&buf[4], payload, payload_len);
+
+	/* Wait for BMC to be available and ready for the next command */
+	if (wait_for_control_bits(port, B_BUSY | H2B_ATN, 0) == CB_ERR)
+		return CB_ERR;
+
+	/* Clear write pointer */
+	outb(CLR_WR_PTR, port + BT_CTRL_REG);
+
+	/* Send our message */
+	for (i = 0; i < len; ++i)
+		outb(buf[i], port + HOST2BMC_REG);
+
+	/* Tell BMC to process the data */
+	outb(H2B_ATN, port + BT_CTRL_REG);
+
+	return CB_SUCCESS;
+}
+
+static int ipmi_bt_recv(uint16_t port, uint8_t addr, uint8_t cmd,
+			uint8_t *response, uint8_t response_len,
+			uint8_t seq_num)
+{
+	uint16_t i;
+	uint16_t len;
+	uint16_t out_len;
+	uint8_t buf[MAX_RECEIVE_SIZE];
+
+	/* Wait for BMC's response */
+	if (wait_for_control_bits(port, B2H_ATN, B2H_ATN) == CB_ERR)
+		return -1;
+
+	/* Tell BMC that host is busy */
+	outb(H_BUSY, port + BT_CTRL_REG);
+
+	/* Acknowledge that response is being processed */
+	outb(B2H_ATN, port + BT_CTRL_REG);
+
+	/* Clear read pointer */
+	outb(CLR_RD_PTR, port + BT_CTRL_REG);
+
+	/* Receive response */
+	len = inb(port + BMC2HOST_REG);
+	for (i = 0; i < len; ++i)
+		buf[i] = inb(port + BMC2HOST_REG);
+
+	/* Indicate that the host is done working with the buffer */
+	outb(H_BUSY, port + BT_CTRL_REG);
+
+	if (len < 3) {
+		printk(BIOS_ERR, "IPMI BT response is shorter than 3 bytes: %d\n", len);
+		goto error;
+	}
+
+	if (buf[0] != addr) {
+		printk(BIOS_ERR,
+		       "NETFN/LUN field mismatch in IPMI BT response: 0x%02x instead of 0x%02x\n",
+		       buf[0], addr);
+		goto error;
+	}
+	if (buf[1] != seq_num) {
+		printk(BIOS_ERR,
+		       "SEQ field mismatch in IPMI BT response: 0x%02x instead of 0x%02x\n",
+		       buf[1], seq_num);
+		goto error;
+	}
+	if (buf[2] != cmd) {
+		printk(BIOS_ERR,
+		       "CMD field mismatch in IPMI BT response: 0x%02x instead of 0x%02x\n",
+		       buf[2], cmd);
+		goto error;
+	}
+
+	/*
+	 * Copy response skipping sequence number to match KCS messages.
+	 * Sequence number is really an implementation detail anyway.
+	 */
+	out_len = MIN(response_len, len - 1);
+	if (out_len > 0)
+		response[0] = buf[0];
+	if (out_len > 1)
+		memcpy(&response[1], &buf[2], out_len - 1);
+
+	return out_len;
+
+error:
+	printk(BIOS_DEBUG, "  IPMI response length field: 0x%02x\n", len);
+	printk(BIOS_DEBUG, "  IPMI NetFn/LUN: 0x%02x\n", addr);
+	printk(BIOS_DEBUG, "  IPMI SEQ: 0x%02x\n", seq_num);
+	printk(BIOS_DEBUG, "  IPMI command: 0x%02x\n", cmd);
+	return -1;
+}
+
+int ipmi_message(int port, int netfn, int lun, int cmd,
+		 const uint8_t *payload, int payload_len,
+		 uint8_t *response, int response_len)
+{
+	static uint8_t seq_num = 0xff;
+
+	uint8_t addr;
+
+	if (netfn < 0 || netfn > 0x3f) {
+		printk(BIOS_ERR, "%s(): NetFn (%d) is not within [0, %d] range\n",
+		       __func__, netfn, 0x3f);
+		return -1;
+	}
+	if (lun < 0 || lun > 0x3) {
+		printk(BIOS_ERR, "%s(): LUN (%d) is not within [0, %d] range\n",
+		       __func__, lun, 0x3);
+		return -1;
+	}
+	if (payload_len < 0 || payload_len > MAX_PAYLOAD_SIZE) {
+		printk(BIOS_ERR, "%s(): payload size (%d) is not within [0, %d] range\n",
+		       __func__, payload_len, MAX_PAYLOAD_SIZE);
+		return -1;
+	}
+
+	addr = (netfn << 2) | (lun & 0x3);
+	if (ipmi_bt_send(port, addr, cmd, payload, payload_len, ++seq_num) == CB_ERR) {
+		printk(BIOS_ERR, "Failed to send IPMI BT command 0x%02x\n", cmd);
+		return -1;
+	}
+
+	addr = ((netfn + 1) << 2) | (lun & 0x3);
+	return ipmi_bt_recv(port, addr, cmd, response, response_len, seq_num);
+}
diff --git a/src/drivers/ipmi/ipmi_bt.h b/src/drivers/ipmi/ipmi_bt.h
new file mode 100644
index 0000000000..23bfda1ad0
--- /dev/null
+++ b/src/drivers/ipmi/ipmi_bt.h
@@ -0,0 +1,11 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef __IPMI_BT_H
+#define __IPMI_BT_H
+
+#include <types.h>
+
+/* Drops events from BMC and resets state of the BT interface */
+enum cb_err ipmi_bt_clear(uint16_t port);
+
+#endif /* __IPMI_BT_H */
diff --git a/src/drivers/ipmi/ipmi_bt_ops.c b/src/drivers/ipmi/ipmi_bt_ops.c
new file mode 100644
index 0000000000..82bfc33f3b
--- /dev/null
+++ b/src/drivers/ipmi/ipmi_bt_ops.c
@@ -0,0 +1,121 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+/*
+ * Place in devicetree.cb:
+ *
+ * chip drivers/ipmi
+ *   device pnp e4.0 on end         # IPMI BT
+ * end
+ */
+
+#include <console/console.h>
+#include <commonlib/bsd/helpers.h>
+#include <device/device.h>
+#include <string.h>
+
+#include "ipmi_if.h"
+#include "ipmi_bt.h"
+
+static u8 bmc_revision_major = 0x0;
+static u8 bmc_revision_minor = 0x0;
+
+static void ipmi_bt_init(struct device *dev)
+{
+	struct ipmi_devid_rsp rsp;
+	struct drivers_ipmi_config *conf = dev->chip_info;
+
+	if (!conf) {
+		printk(BIOS_WARNING, "IPMI: chip_info is missing! Skip init.\n");
+		return;
+	}
+
+	printk(BIOS_DEBUG, "IPMI: PNP BT 0x%x\n", dev->path.pnp.port);
+
+	if (ipmi_process_self_test_result(dev)) {
+		dev->enabled = 0;
+		return;
+	}
+
+	if (!ipmi_get_device_id(dev, &rsp)) {
+		uint32_t man_id = 0;
+		uint32_t prod_id = 0;
+
+		/* 4 bit encoding */
+		u8 ipmi_revision_minor = IPMI_IPMI_VERSION_MINOR(rsp.ipmi_version);
+		u8 ipmi_revision_major = IPMI_IPMI_VERSION_MAJOR(rsp.ipmi_version);
+
+		bmc_revision_major = rsp.fw_rev1;
+		bmc_revision_minor = rsp.fw_rev2;
+
+		memcpy(&man_id, rsp.manufacturer_id, sizeof(rsp.manufacturer_id));
+
+		memcpy(&prod_id, rsp.product_id, sizeof(rsp.product_id));
+
+		printk(BIOS_INFO, "IPMI: Found man_id 0x%06x, prod_id 0x%04x\n",
+		       man_id, prod_id);
+
+		printk(BIOS_INFO, "IPMI: Version %01x.%01x\n",
+		       ipmi_revision_major, ipmi_revision_minor);
+	} else {
+		dev->enabled = 0;
+		return;
+	}
+
+	if (ipmi_bt_clear(dev->path.pnp.port) == CB_ERR)
+		dev->enabled = 0;
+}
+
+void ipmi_bmc_version(uint8_t *ipmi_bmc_major_revision, uint8_t *ipmi_bmc_minor_revision)
+{
+	if (bmc_revision_major == 0 && bmc_revision_minor == 0)
+		printk(BIOS_ERR, "IPMI: BMC revision missing\n");
+
+	*ipmi_bmc_major_revision = bmc_revision_major;
+	*ipmi_bmc_minor_revision = bmc_revision_minor;
+}
+
+static void ipmi_set_resources(struct device *dev)
+{
+	struct resource *res;
+
+	for (res = dev->resource_list; res; res = res->next) {
+		if (!(res->flags & IORESOURCE_ASSIGNED))
+			continue;
+
+		res->flags |= IORESOURCE_STORED;
+		report_resource_stored(dev, res, "");
+	}
+}
+
+static void ipmi_read_resources(struct device *dev)
+{
+	struct resource *res = new_resource(dev, 0);
+	res->base = dev->path.pnp.port;
+	res->size = 3;
+	res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
+}
+
+static struct device_operations ops = {
+	.read_resources = ipmi_read_resources,
+	.set_resources  = ipmi_set_resources,
+	.init           = ipmi_bt_init,
+};
+
+static void enable_dev(struct device *dev)
+{
+	if (dev->path.type != DEVICE_PATH_PNP)
+		printk(BIOS_ERR, "%s: Expected device type %s, got %s\n",
+		       dev_path(dev),
+		       dev_path_name(DEVICE_PATH_PNP),
+		       dev_path_name(dev->path.type));
+	else if (!IS_ALIGNED(dev->path.pnp.port, 4))
+		printk(BIOS_ERR, "%s: Base address %#x must be aligned to 4, but isn't\n",
+		       dev_path(dev), dev->path.pnp.port);
+	else
+		dev->ops = &ops;
+}
+
+struct chip_operations drivers_ipmi_ops = {
+	.name = "IPMI BT",
+	.enable_dev = enable_dev,
+};
diff --git a/src/drivers/ipmi/ipmi_ops_premem.c b/src/drivers/ipmi/ipmi_ops_premem.c
index 99c5842bb3..e65ab4ae95 100644
--- a/src/drivers/ipmi/ipmi_ops_premem.c
+++ b/src/drivers/ipmi/ipmi_ops_premem.c
@@ -6,6 +6,7 @@
 #include <delay.h>
 #include <timer.h>
 
+#include "ipmi_bt.h"
 #include "ipmi_if.h"
 #include "chip.h"
 
@@ -26,7 +27,8 @@ enum cb_err ipmi_premem_init(const u16 port, const u16 device)
 		printk(BIOS_ERR, "IPMI: device is not enabled\n");
 		return CB_ERR;
 	}
-	printk(BIOS_DEBUG, "IPMI: romstage PNP KCS 0x%x\n", dev->path.pnp.port);
+	printk(BIOS_DEBUG, "IPMI: romstage PNP %s 0x%x\n",
+	       CONFIG(IPMI_KCS) ? "KCS" : "BT", dev->path.pnp.port);
 	if (dev->chip_info)
 		conf = dev->chip_info;
 
@@ -49,5 +51,8 @@ enum cb_err ipmi_premem_init(const u16 port, const u16 device)
 	if (ipmi_process_self_test_result(dev))
 		return CB_ERR;
 
+	if (CONFIG(IPMI_BT) && ipmi_bt_clear(dev->path.pnp.port) == CB_ERR)
+		return CB_ERR;
+
 	return CB_SUCCESS;
 }

From e468e32dfb5c21f2ac8411c57b2854c0ecf35a76 Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Tue, 7 Oct 2025 15:04:51 -0500
Subject: [PATCH 2267/3886] mb/google/*: Update Kconfig.name with actual device
 names

Update Kconfig.name with device/product names where available. Names
were parsed from a ChromeOS Recovery image config file, and matched
to the appropriate board using a script generated by Cursor AI.
Output was spot checked for correctness and compared to other sources.
Development devices were dropped from the results.

Change-Id: I5ac1c153606b7d1f93ea5c72e5ff727bb1f38683
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89451
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
---
 src/mainboard/google/asurada/Kconfig.name |   2 +-
 src/mainboard/google/brox/Kconfig.name    |   8 +-
 src/mainboard/google/brya/Kconfig.name    | 126 +++++++++++++---------
 src/mainboard/google/cyan/Kconfig.name    |  22 +++-
 src/mainboard/google/dedede/Kconfig.name  |  31 +++---
 src/mainboard/google/fizz/Kconfig.name    |  13 ++-
 src/mainboard/google/gru/Kconfig.name     |   2 +-
 src/mainboard/google/kukui/Kconfig.name   |   4 +-
 src/mainboard/google/octopus/Kconfig.name |   6 +-
 src/mainboard/google/puff/Kconfig.name    |   8 +-
 src/mainboard/google/rambi/Kconfig.name   |  25 ++++-
 src/mainboard/google/rex/Kconfig.name     |   6 +-
 src/mainboard/google/skyrim/Kconfig.name  |   2 +-
 src/mainboard/google/trogdor/Kconfig.name |   6 +-
 14 files changed, 171 insertions(+), 90 deletions(-)

diff --git a/src/mainboard/google/asurada/Kconfig.name b/src/mainboard/google/asurada/Kconfig.name
index f72ac39139..278655180e 100644
--- a/src/mainboard/google/asurada/Kconfig.name
+++ b/src/mainboard/google/asurada/Kconfig.name
@@ -9,4 +9,4 @@ config BOARD_GOOGLE_HAYATO
 	bool "->  Hayato"
 
 config BOARD_GOOGLE_SPHERION
-	bool "->  Spherion"
+	bool "->  Spherion (Acer Chromebook 514 (CB514-2H, CB514-2HT))"
diff --git a/src/mainboard/google/brox/Kconfig.name b/src/mainboard/google/brox/Kconfig.name
index 2d67ec094d..ca231025fc 100644
--- a/src/mainboard/google/brox/Kconfig.name
+++ b/src/mainboard/google/brox/Kconfig.name
@@ -21,7 +21,11 @@ config BOARD_GOOGLE_GREENBAYUPOC
 	bool "->  Greenbayupoc"
 
 config BOARD_GOOGLE_JUBILANT
-	bool "->  Jubilant"
+	bool "->  Jubilant (Multiple devices - See help text)"
+	help
+	  The Jubilant board supports the following devices:
+	  - Acer Chromebook Plus 514
+	  - Acer Chromebook Plus 516 (CB516-1H,CB516-1HT)
 
 config BOARD_GOOGLE_LOTSO
-	bool "->  Lotso"
+	bool "->  Lotso (Lenovo Chromebook Plus 2-in-1)"
diff --git a/src/mainboard/google/brya/Kconfig.name b/src/mainboard/google/brya/Kconfig.name
index 58bcb74157..2565a426ef 100644
--- a/src/mainboard/google/brya/Kconfig.name
+++ b/src/mainboard/google/brya/Kconfig.name
@@ -6,19 +6,19 @@ config BOARD_GOOGLE_AGAH
 	bool "->  Agah"
 
 config BOARD_GOOGLE_ANAHERA
-	bool "->  Anahera"
+	bool "->  Anahera (HP Elite c640 14 inch G3 Chromebook)"
 
 config BOARD_GOOGLE_ANAHERA4ES
 	bool "->  Anahera4ES"
 
 config BOARD_GOOGLE_ANRAGGAR
-	bool "->  Anraggar"
+	bool "->  Anraggar (ASUS Chromebook CR12 CR1204C)"
 
 config BOARD_GOOGLE_AURASH
-	bool "->  Aurash"
+	bool "->  Aurash (AOpen Chromebox Commercial 3)"
 
 config BOARD_GOOGLE_BANSHEE
-	bool "->  Banshee"
+	bool "->  Banshee (Framework Laptop Chromebook Edition)"
 
 config BOARD_GOOGLE_BRASK
 	bool "->  Brask"
@@ -27,82 +27,96 @@ config BOARD_GOOGLE_BRYA0
 	bool "->  Brya 0"
 
 config BOARD_GOOGLE_CRAASK
-	bool "->  Craask"
+	bool "->  Craask (Acer Chromebook Spin 512)"
 
 config BOARD_GOOGLE_CRAASKOV
-	bool "->  Craaskov"
+	bool "->  Craaskov (Acer Chromebook Spin 312)"
 
 config BOARD_GOOGLE_CONSTITUTION
-	bool "->  Constitution"
+	bool "->  Constitution (Google Meet Series Two)"
 
 config BOARD_GOOGLE_CROTA
-	bool "->  Crota"
+	bool "->  Crota (Multiple devices - See help text)"
+	help
+	  The Crota board supports the following devices:
+	  - Dell Latitude 5430 Chromebook
+	  - Dell Latitude 5430 2-in-1 Chromebook
 
 config BOARD_GOOGLE_DIRKS
-	bool "->  Dirks"
+	bool "->  Dirks (Acer Chromebox Mini CXM2 (TWL))"
 
 config BOARD_GOOGLE_DOCHI
-	bool "->  Dochi"
+	bool "->  Dochi (Acer Chromebook Plus Spin 514)"
 
 config BOARD_GOOGLE_DOMIKA
-	bool "->  Domika"
+	bool "->  Domika (Multiple devices - See help text)"
+	help
+	  The Domika board supports the following devices:
+	  - HP Fortis G1i 11 Chromebook
+	  - HP Fortis Flip G1i 11 Chromebook
+	  - HP Fortis G1i 14 Chromebook
 
 config BOARD_GOOGLE_FELWINTER
-	bool "->  Felwinter"
+	bool "->  Felwinter (ASUS Chromebook Flip CX5(CX5601))"
 
 config BOARD_GOOGLE_GAELIN
 	bool "->  Gaelin"
 
 config BOARD_GOOGLE_GIMBLE
-	bool "->  Gimble"
+	bool "->  Gimble (HP Chromebook x360 14c-cd0)"
 
 config BOARD_GOOGLE_GIMBLE4ES
 	bool "->  Gimble4ES"
 
 config BOARD_GOOGLE_GLADIOS
-	bool "->  Gladios"
+	bool "->  Gladios (HP Chromebox Enterprise G4)"
 
 config BOARD_GOOGLE_GLASSWAY
-	bool "->  Glassway"
+	bool "->  Glassway (CTL Chromebook Plus PX141GX)"
 
 config BOARD_GOOGLE_GOTHRAX
-	bool "->  Gothrax"
+	bool "->  Gothrax (Multiple OEM Chromebooks)"
 
 config BOARD_GOOGLE_GUREN
-	bool "->  Guren"
+	bool "->  Guren (CTL Chromebook PX121E)"
 
 config BOARD_GOOGLE_HADES
 	bool "->  Hades"
 
 config BOARD_GOOGLE_KANO
-	bool "->  Kano"
+	bool "->  Kano (Acer Chromebook Spin 714)"
 
 config BOARD_GOOGLE_KALADIN
 	bool "->  Kaladin"
 
 config BOARD_GOOGLE_KINOX
-	bool "->  Kinox"
+	bool "->  Kinox (Lenovo ThinkCentre M60q Chromebox)"
 
 config BOARD_GOOGLE_KULDAX
-	bool "->  Kuldax"
+	bool "->  Kuldax (ASUS Chromebox 5/5a (CN67))"
 
 config BOARD_GOOGLE_JOXER
-	bool "->  Joxer"
+	bool "->  Joxer (HP Chromebook x360 14b)"
 
 config BOARD_GOOGLE_LISBON
-	bool "->  Lisbon"
+	bool "->  Lisbon (Multiple devices - See help text)"
+	help
+	  The Lisbon board supports the following devices:
+	  - CTL Chromebox CBx3 / CTL Chromebox Enterprise CBx3
+	  - Centerm Chromebox D661 / Centerm Chromebox Enterprise D661
+	  - Promethean Chromebox 3
 
 config BOARD_GOOGLE_MARASOV
-	bool "->  Marasov"
+	bool "->  Marasov (ASUS Chromebook Plus CX34 CX3402)"
 
 config BOARD_GOOGLE_MITHRAX
-	bool "->  Mithrax"
+	bool "->  Mithrax (ASUS Chromebook CX34 Flip (CX3401))"
 
 config BOARD_GOOGLE_MOLI
-	bool "->  Moli"
+	bool "->  Moli (Acer Chromebox CXI5)"
 
 config BOARD_GOOGLE_MOXIE
-	bool "->  Moxie"
+	bool "->  Moxie (Acer Chromebox CXI6)"
 
 config BOARD_GOOGLE_NIVVIKS
 	bool "->  Nivviks"
@@ -114,40 +128,44 @@ config BOARD_GOOGLE_NOKRIS
 	bool "->  Nokris"
 
 config BOARD_GOOGLE_OMNIGUL
-	bool "->  Omnigul"
+	bool "->  Omnigul (Multiple devices - See help text)"
+	help
+	  The Omnigul board supports the following devices:
+	  - Acer Chromebook Plus 515 (CB515-2H/2HT)
+	  - Acer Chromebook Plus Enterprise 515 (CBE595-2/2T)
 
 config BOARD_GOOGLE_OSIRIS
-	bool "->  Osiris"
+	bool "->  Osiris (Acer Chromebook 516 GE)"
 
 config BOARD_GOOGLE_PIRRHA
 	bool "->  Pirrha"
 
 config BOARD_GOOGLE_PRIMUS
-	bool "->  Primus"
+	bool "->  Primus (Lenovo ThinkPad C14 Gen 1 Chromebook)"
 
 config BOARD_GOOGLE_PUJJO
-	bool "->  Pujjo"
+	bool "->  Pujjo (Lenovo 500e Yoga/Flex 3i Chromebook)"
 
 config BOARD_GOOGLE_PUJJONIRU
-	bool "->  Pujjoniru"
+	bool "->  Pujjoniru (Lenovo Chromebook Plus 2-in-1 14ITN10)"
 
 config BOARD_GOOGLE_QUANDISO
-	bool "->  Quandiso"
+	bool "->  Quandiso (CTL Chromebook NL73)"
 
 config BOARD_GOOGLE_QUANDISO2
-	bool "->  Quandiso2"
+	bool "->  Quandiso2 (CTL Chromebook NL73 Gen 2)"
 
 config BOARD_GOOGLE_REDRIX
-	bool "->  Redrix"
+	bool "->  Redrix (HP Elite Dragonfly Chromebook)"
 
 config BOARD_GOOGLE_REDRIX4ES
 	bool "->  Redrix4ES"
 
 config BOARD_GOOGLE_RIVEN
-	bool "->  Riven"
+	bool "->  Riven (Acer Chromebook Spin 511)"
 
 config BOARD_GOOGLE_RULL
-	bool "->  Rull"
+	bool "->  Rull (Acer Chromebook 514 C937)"
 
 config BOARD_GOOGLE_SKOLAS
 	bool "->  Skolas"
@@ -156,16 +174,16 @@ config BOARD_GOOGLE_SKOLAS4ES
 	bool "->  Skolas4ES"
 
 config BOARD_GOOGLE_TAEKO
-	bool "->  Taeko"
+	bool "->  Taeko (Lenovo IdeaPad/Flex 5i Chromebook 14)"
 
 config BOARD_GOOGLE_TAEKO4ES
 	bool "->  Taeko4ES"
 
 config BOARD_GOOGLE_TANIKS
-	bool "->  Taniks"
+	bool "->  Taniks (Lenovo IdeaPad Gaming Chromebook 16)"
 
 config BOARD_GOOGLE_TELIKS
-	bool "->  Teliks"
+	bool "->  Teliks (ASUS Chromebook CR11 (CR1104CTA))"
 
 config BOARD_GOOGLE_TEREID
 	bool "->  Tereid"
@@ -177,49 +195,55 @@ config BOARD_GOOGLE_TRULO
 	bool "->  Trulo"
 
 config BOARD_GOOGLE_ULDREN
-	bool "->  Uldren"
+	bool "->  Uldren (Dell Chromebook 3120)"
 
 config BOARD_GOOGLE_ULDRENITE
 	bool "->  Uldrenite"
 
 config BOARD_GOOGLE_VELL
-	bool "->  Vell"
+	bool "->  Vell (HP Dragonfly Pro Chromebook)"
 
 config BOARD_GOOGLE_VOLMAR
-	bool "->  Volmar"
+	bool "->  Volmar (Acer Chromebook Vero 514)"
 
 config BOARD_GOOGLE_XIVU
-	bool "->  Xivu"
+	bool "->  Xivu (Asus Chromebook CR11 [CR1102C])"
 
 config BOARD_GOOGLE_YAVIKS
-	bool "->  Yaviks"
+	bool "->  Yaviks (HP Chromebook 15.6)"
 
 config BOARD_GOOGLE_YAVILLA
-	bool "->  Yavilla"
+	bool "->  Yavilla (HP Fortis 11 G10 Chromebook)"
 
 config BOARD_GOOGLE_ZYDRON
 	bool "->  Zydron"
 
 config BOARD_GOOGLE_XOL
-	bool "->  Xol"
+	bool "->  Xol (Galaxy Chromebook Plus)"
 
 config BOARD_GOOGLE_NOVA
 	bool "->  Nova"
 
 config BOARD_GOOGLE_BUJIA
-	bool "->  Bujia"
+	bool "->  Bujia (Multiple devices - See help text)"
+	help
+	  The Bujia board supports the following devices:
+	  - AOPEN Chromebox OPS / AOPEN Chromebox Enterprise OPS
+	  - IMAGO Chromebox OPS
+	  - Satsuki Chromebox OPS / Satsuki Chromebox Enterprise OPS
+	  - ViewSonic Bujia
 
 config BOARD_GOOGLE_YAVISTA
 	bool "->  Yavista"
 
 config BOARD_GOOGLE_SUNDANCE
-	bool "->  Sundance"
+	bool "->  Sundance (NEC Chromebook Y4)"
 
 config BOARD_GOOGLE_PUJJOGA
-	bool "->  Pujjoga"
+	bool "->  Pujjoga (Lenovo 500e Chromebook Gen 4s)"
 
 config BOARD_GOOGLE_PUJJOGATWIN
-	bool "->  Pujjogatwin"
+	bool "->  Pujjogatwin (Lenovo 500e Chromebook Gen 4s)"
 
 config BOARD_GOOGLE_PUJJOLO
 	bool "->  Pujjolo"
@@ -228,7 +252,7 @@ config BOARD_GOOGLE_ORISA
 	bool "->  Orisa"
 
 config BOARD_GOOGLE_TELITH
-	bool "->  Telith"
+	bool "->  Telith (ASUS Chromebook CX15 (CX1505CTA))"
 
 config BOARD_GOOGLE_MELIKS
 	bool "->  Meliks"
diff --git a/src/mainboard/google/cyan/Kconfig.name b/src/mainboard/google/cyan/Kconfig.name
index 6745aaa797..6edc464919 100644
--- a/src/mainboard/google/cyan/Kconfig.name
+++ b/src/mainboard/google/cyan/Kconfig.name
@@ -21,7 +21,16 @@ config BOARD_GOOGLE_REKS
 	bool "->  Reks (Lenovo N22/N42 Chromebook)"
 
 config BOARD_GOOGLE_RELM
-	bool "->  Relm"
+	bool "->  Relm (Multiple devices - See help text)"
+	help
+	  The Relm board supports the following devices:
+	  - Acer Chromebook 11 N7 (C731, C731T)
+	  - CTL NL61 Chromebook
+	  - EduGear Chromebook R
+	  - Edxis Education Chromebook (NL6D)
+	  - HP Chromebook 11 G5 EE
+	  - Mecer V2 Chromebook
+	  - Positivo Chromebook C216B
 
 config BOARD_GOOGLE_SETZER
 	bool "->  Setzer (HP Chromebook 11 G5)"
@@ -33,4 +42,13 @@ config BOARD_GOOGLE_ULTIMA
 	bool "->  Ultima (Lenovo Yoga 11e G3)"
 
 config BOARD_GOOGLE_WIZPIG
-	bool "->  Wizpig"
+	bool "->  Wizpig (Multiple devices - See help text)"
+	help
+	  The Wizpig board supports the following devices:
+	  - CTL J5 Chromebook
+	  - Edugear CMT Chromebook
+	  - Haier Chromebook 11 C
+	  - Multilaser Chromebook M11C
+	  - PCMerge Chromebook PCM-116T-432B
+	  - Prowise Chromebook Proline
+	  - Viglen Chromebook 360
diff --git a/src/mainboard/google/dedede/Kconfig.name b/src/mainboard/google/dedede/Kconfig.name
index b4708240b4..fd130ecb8d 100644
--- a/src/mainboard/google/dedede/Kconfig.name
+++ b/src/mainboard/google/dedede/Kconfig.name
@@ -6,16 +6,16 @@ config BOARD_GOOGLE_BEADRIX
 	bool "->  Beadrix"
 
 config BOARD_GOOGLE_BLIPPER
-	bool "->  Blipper"
+	bool "->  Blipper (Lenovo 3i-15 Chromebook)"
 
 config BOARD_GOOGLE_BOTEN
 	bool "->  Boten (Lenovo 500e Chromebook Gen 3)"
 
 config BOARD_GOOGLE_BOXY
-	bool "->  Boxy"
+	bool "->  Boxy (Lenovo Chromebox Micro)"
 
 config BOARD_GOOGLE_BUGZZY
-	bool "->  Bugzzy"
+	bool "->  Bugzzy (Samsung Galaxy Chromebook 2 360)"
 
 config BOARD_GOOGLE_CAPPY2
 	bool "->  Cappy2"
@@ -24,33 +24,34 @@ config BOARD_GOOGLE_CORORI
 	bool "->  Corori"
 
 config BOARD_GOOGLE_CRET
-	bool "->  Cret"
+	bool "->  Cret (Dell Chromebook 3110)"
 
 config BOARD_GOOGLE_DEDEDE
 	bool "->  Dedede"
 
 config BOARD_GOOGLE_DEXI
-	bool "->  Dexi"
+	bool "->  Dexi (AOPEN Chromebox Mini 2)"
 
 config BOARD_GOOGLE_DIBBI
 	bool "->  Dibbi"
 
 config BOARD_GOOGLE_DITA
-	bool "->  Dita"
+	bool "->  Dita (Acer Chromebox Mini CXM1)"
 
 config BOARD_GOOGLE_DRAWCIA
-	bool "->  Drawcia"
+	bool "->  Drawcia (Multiple devices - See help text)"
 	help
 	  The Drawcia board supports the following devices:
 	  - HP Chromebook x360 11 G4 EE (Drawcia)
 	  - HP Chromebook 11 G9 EE (Drawlat)
 	  - HP Chromebook 14 G7 (Drawman)
+	  - HP Fortis 14 G10 Chromebook (Drawper)
 
 config BOARD_GOOGLE_DRIBLEE
 	bool "->  Driblee"
 
 config BOARD_GOOGLE_GALTIC
-	bool "->  Galtic"
+	bool "->  Galtic (ASUS Chromebook CX1400CKA)"
 
 config BOARD_GOOGLE_GOOEY
 	bool "->  Gooey"
@@ -65,16 +66,16 @@ config BOARD_GOOGLE_LALALA
 	bool "->  Lalala"
 
 config BOARD_GOOGLE_LANTIS
-	bool "->  Lantis"
+	bool "->  Lantis (HP Chromebook 14a)"
 
 config BOARD_GOOGLE_MADOO
-	bool "->  Madoo"
+	bool "->  Madoo (HP Chromebook x360 14b)"
 
 config BOARD_GOOGLE_MAGOLOR
-	bool "->  Magolor"
+	bool "->  Magolor (Acer Chromebook Spin 511)"
 
 config BOARD_GOOGLE_METAKNIGHT
-	bool "->  Metaknight"
+	bool "->  Metaknight (NEC Chromebook Y3)"
 
 config BOARD_GOOGLE_PIRIKA
 	bool "->  Pirika"
@@ -83,10 +84,10 @@ config BOARD_GOOGLE_SASUKE
 	bool "->  Sasuke (Samsung Galaxy Chromebook Go)"
 
 config BOARD_GOOGLE_SASUKETTE
-	bool "->  Sasukette"
+	bool "->  Sasukette (Samsung Galaxy Chromebook Go 11)"
 
 config BOARD_GOOGLE_STORO
-	bool "->  Storo (Asus Chromebook CR1100)"
+	bool "->  Storo (ASUS Chromebook CR1100CKA)"
 
 config BOARD_GOOGLE_SHOTZO
 	bool "->  Shotzo"
@@ -101,4 +102,4 @@ config BOARD_GOOGLE_WADDLEDOO
 	bool "->  Waddledoo"
 
 config BOARD_GOOGLE_AWASUKI
-	bool "->  Awasuki"
+	bool "->  Awasuki (ASUS Chromebook CX1405CKA/CB1405CKA)"
diff --git a/src/mainboard/google/fizz/Kconfig.name b/src/mainboard/google/fizz/Kconfig.name
index 3f7f391159..928afd8122 100644
--- a/src/mainboard/google/fizz/Kconfig.name
+++ b/src/mainboard/google/fizz/Kconfig.name
@@ -3,10 +3,17 @@
 comment "Fizz"
 
 config BOARD_GOOGLE_FIZZ
-	bool "->  Fizz"
+	bool "->  Fizz (Multiple devices - See help text)"
+	help
+	  The Fizz board supports the following devices:
+	  - AOpen Chromebox Commercial 2 (Jax)
+	  - HP Chromebox G2 (Kench)
+	  - Acer Chromebox CXI3 (SION)
+	  - ASUS Chromebox 3 (CN65) (TEEMO)
+	  - CTL Chromebox CBx1 (WUKONG)
 
 config BOARD_GOOGLE_KARMA
-	bool "->  Karma"
+	bool "->  Karma (Acer Chromebase 24I2)"
 
 config BOARD_GOOGLE_ENDEAVOUR
-	bool "->  Endeavour"
+	bool "->  Endeavour (Google Meet Series One (Lenovo))"
diff --git a/src/mainboard/google/gru/Kconfig.name b/src/mainboard/google/gru/Kconfig.name
index 3f08947e41..f72a350816 100644
--- a/src/mainboard/google/gru/Kconfig.name
+++ b/src/mainboard/google/gru/Kconfig.name
@@ -12,7 +12,7 @@ config BOARD_GOOGLE_BOB
 	bool "->  Bob (Asus Chromebook Flip C101PA)"
 
 config BOARD_GOOGLE_SCARLET
-	bool "->  Scarlet"
+	bool "->  Scarlet (Acer Chromebook Tab 10)"
 
 config BOARD_GOOGLE_NEFARIO
 	bool "->  Nefario"
diff --git a/src/mainboard/google/kukui/Kconfig.name b/src/mainboard/google/kukui/Kconfig.name
index e29a912adc..d7f54f6d50 100644
--- a/src/mainboard/google/kukui/Kconfig.name
+++ b/src/mainboard/google/kukui/Kconfig.name
@@ -18,7 +18,7 @@ config BOARD_GOOGLE_FLAPJACK
 	bool "->  Flapjack"
 
 config BOARD_GOOGLE_KATSU
-	bool "->  Katsu"
+	bool "->  Katsu (ASUS Chromebook Detachable CZ1)"
 
 comment "Jacuzzi"
 
@@ -53,7 +53,7 @@ config BOARD_GOOGLE_FENNEL
 	bool "->  Fennel"
 
 config BOARD_GOOGLE_COZMO
-	bool "->  Cozmo"
+	bool "->  Cozmo (Acer Chromebook 314 (CB314-2H/CB314-2HT))"
 
 config BOARD_GOOGLE_MAKOMO
 	bool "->  Makomo"
diff --git a/src/mainboard/google/octopus/Kconfig.name b/src/mainboard/google/octopus/Kconfig.name
index b4ad2cd815..7519a2e7bf 100644
--- a/src/mainboard/google/octopus/Kconfig.name
+++ b/src/mainboard/google/octopus/Kconfig.name
@@ -15,16 +15,16 @@ config BOARD_GOOGLE_CASTA
 	bool "->  Bluebird/Casta (Samsung Chromebook 4, 4+)"
 
 config BOARD_GOOGLE_DOOD
-	bool "->  Dood"
+	bool "->  Dood (NEC Chromebook Y2)"
 
 config BOARD_GOOGLE_FLEEX
 	bool "->  Fleex (Dell Chromebook 3100)"
 
 config BOARD_GOOGLE_FOOB
-	bool "->  Foob"
+	bool "->  Foob (CTL Chromebook VX11/VT11T)"
 
 config BOARD_GOOGLE_GARG
-	bool "->  Garg"
+	bool "->  Garg (CTL Chromebook NL71/CT/LTE)"
 
 config BOARD_GOOGLE_LICK
 	bool "->  Lick (Ideapad 3 Chromebook)"
diff --git a/src/mainboard/google/puff/Kconfig.name b/src/mainboard/google/puff/Kconfig.name
index fa5b0f5ee6..d8a997e7fb 100644
--- a/src/mainboard/google/puff/Kconfig.name
+++ b/src/mainboard/google/puff/Kconfig.name
@@ -39,4 +39,10 @@ config BOARD_GOOGLE_SCOUT
 	bool "->  Scout (Series One Desk 27)"
 
 config BOARD_GOOGLE_WYVERN
-	bool "->  Wyvern (CTL Chromebox CBx2)"
+	bool "->  Wyvern (Multiple devices - See help text)"
+	help
+	  The Wyvern board supports the following devices:
+	  - CTL Chromebox CBx2/Enterprise CBx2
+	  - Promethean Chromebox 2
+	  - ViewSonic NMP760 Chromebox
+	  - Wyvern MobLab
diff --git a/src/mainboard/google/rambi/Kconfig.name b/src/mainboard/google/rambi/Kconfig.name
index 5e02ea01bc..cd63c425dc 100644
--- a/src/mainboard/google/rambi/Kconfig.name
+++ b/src/mainboard/google/rambi/Kconfig.name
@@ -12,10 +12,31 @@ config BOARD_GOOGLE_CLAPPER
 	bool "->  Clapper (Lenovo N20 Chromebook)"
 
 config BOARD_GOOGLE_ENGUARDE
-	bool "->  Enguarde"
+	bool "->  Enguarde (Multiple devices - See help text)"
+	help
+	  The Enguarde board supports the following devices:
+	  - ASI Chromebook
+	  - CTL N6 Education Chromebook
+	  - Crambo Chromebook
+	  - Education Chromebook
+	  - Edxis Education Chromebook (NL6)
+	  - JP Sa Couto Chromebook
+	  - Lenovo N21 Chromebook
+	  - M&A Chromebook
+	  - RGS Education Chromebook
+	  - Senkatel C1101 Chromebook
+	  - True IDC Chromebook
+	  - Videonet Chromebook
+	  - eduGear Chromebook R
 
 config BOARD_GOOGLE_EXPRESSO
-	bool "->  Expresso"
+	bool "->  Expresso (Multiple devices - See help text)"
+	help
+	  The Expresso board supports the following devices:
+	  - Bobicus Chromebook 11
+	  - Consumer Chromebook
+	  - Edxis Chromebook
+	  - HEXA Chromebook Pi
 
 config BOARD_GOOGLE_GLIMMER
 	bool "->  Glimmer (Lenovo ThinkPad 11e Chromebook)"
diff --git a/src/mainboard/google/rex/Kconfig.name b/src/mainboard/google/rex/Kconfig.name
index 1c68c89612..96aa4c63f1 100644
--- a/src/mainboard/google/rex/Kconfig.name
+++ b/src/mainboard/google/rex/Kconfig.name
@@ -9,7 +9,7 @@ config BOARD_GOOGLE_DEKU4ES
 	bool "-> Deku4ES"
 
 config BOARD_GOOGLE_KARIS
-	bool "->  Karis"
+	bool "->  Karis (Acer Chromebook Plus Spin 714)"
 
 config BOARD_GOOGLE_KARIS4ES
 	bool "->  Karis4ES"
@@ -36,10 +36,10 @@ config BOARD_GOOGLE_REX64
 	bool "-> Rex 64"
 
 config BOARD_GOOGLE_SCREEBO
-	bool "->  Screebo"
+	bool "->  Screebo (ASUS ExpertBook CX54 Chromebook Plus (CX5403))"
 
 config BOARD_GOOGLE_SCREEBO4ES
 	bool "->  Screebo4ES"
 
 config BOARD_GOOGLE_KANIX
-	bool "->  Kanix"
+	bool "->  Kanix (Acer Chromebook Plus 714)"
diff --git a/src/mainboard/google/skyrim/Kconfig.name b/src/mainboard/google/skyrim/Kconfig.name
index ad98886eea..5a9668c598 100644
--- a/src/mainboard/google/skyrim/Kconfig.name
+++ b/src/mainboard/google/skyrim/Kconfig.name
@@ -3,7 +3,7 @@
 comment "Skyrim"
 
 config BOARD_GOOGLE_CRYSTALDRIFT
-	bool "->  Crystaldrift"
+	bool "->  Crystaldrift (SPC Chromebook V1)"
 
 config BOARD_GOOGLE_FROSTFLOW
 	bool "->  Frostflow (ASUS Chromebook CM34 Flip)"
diff --git a/src/mainboard/google/trogdor/Kconfig.name b/src/mainboard/google/trogdor/Kconfig.name
index aec3e8ec6c..c3a00ab2aa 100644
--- a/src/mainboard/google/trogdor/Kconfig.name
+++ b/src/mainboard/google/trogdor/Kconfig.name
@@ -6,7 +6,7 @@ config BOARD_GOOGLE_BUBS
 	bool "->  Bubs"
 
 config BOARD_GOOGLE_COACHZ
-	bool "->  Coachz"
+	bool "->  Coachz (HP Chromebook x2 11-da0)"
 
 config BOARD_GOOGLE_GELARSHIE
 	bool "->  Gelarshie"
@@ -18,7 +18,7 @@ config BOARD_GOOGLE_KINGOFTOWN
 	bool "->  Kingoftown"
 
 config BOARD_GOOGLE_LAZOR
-	bool "->  Lazor"
+	bool "->  Lazor (Acer Chromebook Spin 513, CP513-1H/1HL, R841T/LT)"
 
 config BOARD_GOOGLE_MARZIPAN
 	bool "->  Marzipan"
@@ -33,7 +33,7 @@ config BOARD_GOOGLE_POMPOM
 	bool "->  Pompom"
 
 config BOARD_GOOGLE_QUACKINGSTICK
-	bool "->  Quackingstick"
+	bool "->  Quackingstick (Acer Chromebook Tab 510 / Enterprise Tab 510)"
 
 config BOARD_GOOGLE_WORMDINGLER
 	bool "->  Wormdingler"

From 114d24cd7a11e5cf6bb61a8add8d51c26ab65379 Mon Sep 17 00:00:00 2001
From: Yidi Lin <yidilin@google.com>
Date: Thu, 16 Oct 2025 16:26:31 +0800
Subject: [PATCH 2268/3886] lib: Generalize BMP_LOGO help text

The help description for `CONFIG_BMP_LOGO` in `src/lib/Kconfig` is
updated to be more generic.

Change-Id: Ic95aabe3fa3178ed5a8e4a2105364e8fb397d85f
Signed-off-by: Yidi Lin <yidilin@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89607
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
---
 src/lib/Kconfig | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/lib/Kconfig b/src/lib/Kconfig
index ea6852d601..6407c82cfa 100644
--- a/src/lib/Kconfig
+++ b/src/lib/Kconfig
@@ -162,7 +162,7 @@ config BMP_LOGO
 	bool "Enable logo"
 	default n
 	help
-	  Uses the FSP to display the boot logo. This method supports a
+	  Displays a BMP logo during boot. This method supports a
 	  BMP file only. The uncompressed size can be up to 1 MB. The logo can
 	  be compressed based on either `BMP_LOGO_COMPRESS_*` configs (default LZMA).
 

From 7e3883633a528f9bb3db3bf97864aee01c2de4a5 Mon Sep 17 00:00:00 2001
From: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
Date: Wed, 15 Oct 2025 14:45:44 +0800
Subject: [PATCH 2269/3886] mb/google/brox/var/jubilant: Apply fw_config to
 enable/disable I2C1

As a result of hardware BOM design, U51 (power gate for touchscreen)
would be required to remove on non-touch SKU. The change will cause
the I2C1 touchscreen devices probe ERROR of non-touch SKU since no
power for I2C bus pull-high resistors.The ERROR is waiting I2C stop
condition time out then bootperf test will get fail.

The CL apply fw_config field 19 - PANEL_PWR_SEQ_CTRL for I2C1:
0...disable (non-touch sku)
1...enable  (touch sku)
Turn off I2C1 for non-touch sku, and keep I2C1 is on for touch sku.
It will avoid the touchscreen probing error on I2c1.

BUG=b:447513390
TEST=Check boot to kernel time is 1,376 sec under spec and without
      I2C probe error in ap log of non-touch sku.
     Check touchscreen device works well of touch sku.

Change-Id: I72a68177a90cea88fe283d8499b8378c64206fa2
Signed-off-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89591
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com>
---
 src/mainboard/google/brox/variants/jubilant/overridetree.cb | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/src/mainboard/google/brox/variants/jubilant/overridetree.cb b/src/mainboard/google/brox/variants/jubilant/overridetree.cb
index 25bedf870e..1d667507a8 100644
--- a/src/mainboard/google/brox/variants/jubilant/overridetree.cb
+++ b/src/mainboard/google/brox/variants/jubilant/overridetree.cb
@@ -16,6 +16,10 @@ fw_config
 		option FPMCU_ABSENT			0
 		option FPMCU_NUVOTON			1
 	end
+	field PANEL_PWR 19
+		option DISABLE				0
+		option ENABLE				1
+	end
 end
 
 chip soc/intel/alderlake
@@ -402,6 +406,7 @@ chip soc/intel/alderlake
 				register "hid_desc_reg_offset" = "0x01"
 				device i2c 10 on end
 			end
+			probe PANEL_PWR ENABLE
 		end
 		device ref i2c2 on
 			chip drivers/i2c/generic

From cf97e1bc25d10ddc2b0bd20ed7fec9923ad64010 Mon Sep 17 00:00:00 2001
From: Bora Guvendik <bora.guvendik@intel.com>
Date: Wed, 25 Jun 2025 17:51:52 -0700
Subject: [PATCH 2270/3886] mb/intel/ptlrvp: Add power meter acpi changes

This commit introduces changes to the ACPI implementation for the
PTLRVP mainboard by adding power meter support. It defines how the
PAC194x series devices are connected to the I2C controller and details
their configuration. Each device under scope \_SB.PCI0.I2C3 is given
specific methods to indicate its status, resource settings, and device
specific configurations via _DSM. This includes functionality to return
monitored power rail names, resistor values, EMI configurations, sample
frequencies, and Vbus multiplication factors. These changes enhance
the power management capabilities of the mainboard, allowing precise
monitoring and control over various power rails.

BUG=none
TEST=Verify power meter ACPI changes in DSDT.

Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Change-Id: I6e5d38500cac46187283481ef6f84215b14e927b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88198
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Cliff Huang <cliff.huang@intel.com>
---
 .../intel/ptlrvp/acpi/power_meter.asl         | 1328 +++++++++++++++++
 src/mainboard/intel/ptlrvp/dsdt.asl           |    2 +
 2 files changed, 1330 insertions(+)
 create mode 100644 src/mainboard/intel/ptlrvp/acpi/power_meter.asl

diff --git a/src/mainboard/intel/ptlrvp/acpi/power_meter.asl b/src/mainboard/intel/ptlrvp/acpi/power_meter.asl
new file mode 100644
index 0000000000..99a41a638f
--- /dev/null
+++ b/src/mainboard/intel/ptlrvp/acpi/power_meter.asl
@@ -0,0 +1,1328 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+Scope(\_SB.PCI0.I2C3)
+{
+	/*
+	 * PA01 Device: Defines how the PAC194x is connected to the I2C Controller.
+	 */
+	Device(PA01)
+	{
+		Name(_HID, "MCHP1940")
+		Name(_UID, 1)
+
+		/* Lowest power D-State supported by the device is D3 */
+		Name (_S0W, 3)
+
+		/* Device Status: present, enabled, and functioning properly */
+		Method(_STA, 0x0, NotSerialized)
+		{
+			Return (0xf)
+		}
+
+		/*
+		 * Current Resources Settings
+		 */
+		Method(_CRS, 0x0, NotSerialized)
+		{
+			Name(RBUF, ResourceTemplate()
+			{
+				I2CSerialBusV2(0x18,    /* 7-bit Peripheral Address */
+				ControllerInitiated,    /* Peripheral or Controller? */
+				400000,                 /* Connection Speed in hz */
+				AddressingMode7Bit,     /* 7-bit or 10-bit addressing? */
+				"\\_SB.PCI0.I2C3",      /* I2C Controller to which PAC is connected */
+				0,                      /* Resource Index */
+				ResourceConsumer,       /* Consumer or Producer? */
+				DEV0,)
+			})
+			Return(RBUF)
+		}
+
+		/*
+		 * _DSM - Device Specific Method
+		 *
+		 * This method returns information that PAC194x/5x driver uses for the
+		 * device initial configuration.
+		 *
+		 * The DSM UUID for the Microchip PAC194x/5x: {721F1534-5D27-4B60-9DF4-41A3C4B7DA3A}.
+		 * This must match what the Windows PAC194x/5x driver expects.
+		 *
+		 * Returns:
+		 * Either: A Buffer (for supported Functions, or an error)
+		 * A Package containing PAC194x/5x resources (configuration values)
+		 *
+		 * Input Arguments (per _DSM standard):
+		 *
+		 *     Arg0: UUID - Function Identifier
+		 *     Arg1: Integer - Revision
+		 *     Arg2: Integer - Function Index
+		 *     Arg3: Package - Parameters (not used in our implementation)
+		 */
+		Function(_DSM, {BuffObj, PkgObj}, {BuffObj, IntObj, IntObj, PkgObj})
+		{
+			/*
+			 *  Is our UUID being invoked?
+			 */
+			if(LNotEqual(Arg0, ToUUID("721F1534-5D27-4B60-9DF4-41A3C4B7DA3A")))
+			{
+				return(Buffer() {0x0})  /* incorrect UUID, return NULL for error */
+			}
+
+			/*
+			 * Switch based on the function number requested...
+			 */
+			switch(ToInteger(Arg2))
+			{
+				/*
+				 * Function zero returns a bit-mask of supported functions
+				 */
+				case(0)
+				{
+
+					switch(ToInteger(Arg1)) /* revision check */
+					{
+						/* Revision 0: function 1->7 are supported */
+						case(0) {return (Buffer() {0xFF})}
+					}
+					break;
+				}
+
+				/* Function 1 - returns the names of the monitored power rails. */
+				/* The names should be compliant with Windows EMI power rail taxonomy. */
+				/* If the rail name is NULL ("") -> no EMI created for the channel ("private channel"). */
+				case(1)
+				{
+					Name(BUF1, Package()
+					{
+							/* Rail Name */
+							"SoC_VCCCORE_PH1", /* Channel 1 */
+							"SoC_VCCCORE_PH2", /* Channel 2 */
+							"SoC_VCCCORE_PH3", /* Channel 3 */
+							"SoC_VCCCORE_PH4"  /* Channel 4 */
+					})
+					return(BUF1)
+				}
+
+				/* Function 2 returns the Resistor values expressed in micro-Ohms. */
+				case(2)
+				{
+					/* Return enhanced precision resistor values. */
+					Name(BUF2, Package()
+					{
+							/* Value */
+							2000,   /* Channel 1 */
+							2000,   /* Channel 2 */
+							2000,   /* Channel 3 */
+							2000    /* Channel 4 */
+					})
+					return(BUF2)
+				}
+
+				/* Function 3 - returns the EMI enable/disable bit-mask */
+				case(3)
+				{
+					Name(BUF3, Package()
+					{
+						/* EMI bitmask - CH1:CH2:CH3:CH4 */
+						0xF	/* CHn = 1: EMI enable for channel 'n' */
+							/* CHn = 0: EMI disable for channel 'n' ("private channel") */
+					})
+					return(BUF3)
+				}
+
+				/* Function 4 - returns Vsense and Vbus polarity and full scale range configs */
+				case(4)
+				{
+					Name(BUF4, Package()
+					{
+						/* Vsense configs */
+						0x0, 0x0, 0x0, 0x0,	/* CFG_VS1, CFG_VS2, CFG_VS3, CFG_VS4 */
+									/* CFG_VSn: Vsense configuration for channel 'n' */
+									/* {0x0 = unipolar; 0x1 = bipolar; 0x2 = half scale bipolar} */
+									/* Vbus configs */
+						0x0, 0x0, 0x0, 0x0	/* CFG_VB1, CFG_VB2, CFG_VB3, CFG_VB4 */
+									/* CFG_VBn: Vbus configuration for channel 'n' */
+									/* {0x0 = unipolar; 0x1 = bipolar; 0x2 = half scale bipolar} */
+					})
+					return(BUF4)
+				}
+
+				/* Function 5 - returns the sample frequencies for ACTIVE and IDLE modes */
+				case(5)
+				{
+					Name(BUF5, Package()
+					 {
+						1024, /* ACTIVE sps - accepted values = {1024, 256, 64, 8} */
+						8     /* IDLE sps - accepted values = {1024, 256, 64, 8} */
+					 })
+					return(BUF5)
+				}
+
+				/* Function 6 - returns the REFRESH watchdog timer interval */
+				case(6)
+				{
+					Name(BUF6, Package()
+					{
+						900 /* seconds (min=60, max=60000) */
+					})
+					return(BUF6)
+				}
+
+				/* Function 7 - returns the Vbus multiplication factors for PAC194x/5x-2 */
+				/* PAC194x/5x-2 power meter VBUS+ pins may be connected to voltage dividers */
+				/* to measure rail voltage higher than device Vbus FSR. */
+				case(7)
+				{
+					Name(BUF7, Package()
+					{ /* K = 1000 * (Vrail / Vbus). Must be integer, positive value. */
+						1000, /* Channel 1 K-factor */
+						1000, /* Channel 2 K-factor */
+						1000, /* Channel 3 K-factor */
+						1000  /* Channel 4 K-factor */
+					})
+					return(BUF7)
+				}
+
+			} /* switch(Arg2) */
+			/*
+			 * Return an error (a buffer with a value of zero)
+			 * if we didn't return anything else above
+			 */
+			return(Buffer() {0x0})
+		} /* _DSM */
+	} /* PowerMeter Device PA01 Scope End */
+
+	/*
+	 * PA02 Device: Defines how the PAC194x is connected to the I2C Controller.
+	 */
+	Device(PA02)
+	{
+		Name(_HID, "MCHP1940")
+		Name(_UID, 2)
+
+		/* Lowest power D-State supported by the device is D3 */
+		Name (_S0W, 3)
+
+		/* Device Status: present, enabled, and functioning properly */
+		Method(_STA, 0x0, NotSerialized)
+		{
+			Return (0xf)
+		}
+
+		/*
+		 * Current Resources Settings
+		 */
+		Method(_CRS, 0x0, NotSerialized)
+		{
+			Name(RBUF, ResourceTemplate()
+			{
+				I2CSerialBusV2(0x1E,                    /* 7-bit Peripheral Address */
+						ControllerInitiated,    /* Peripheral or Controller? */
+						400000,                 /* Connection Speed in hz */
+						AddressingMode7Bit,     /* 7-bit or 10-bit addressing? */
+						"\\_SB.PCI0.I2C3",      /* I2C Controller to which PAC is connected */
+						0,                      /* Resource Index */
+						ResourceConsumer,       /* Consumer or Producer? */
+						DEV0,)
+			})
+			Return(RBUF)
+		}
+
+		/*
+		 * _DSM - Device Specific Method
+		 *
+		 * This method returns information that PAC194x/5x driver uses for the
+		 * device initial configuration.
+		 *
+		 * The DSM UUID for the Microchip PAC194x/5x: {721F1534-5D27-4B60-9DF4-41A3C4B7DA3A}.
+		 * This must match what the Windows PAC194x/5x driver expects.
+		 *
+		 * Returns:
+		 * Either: A Buffer (for supported Functions, or an error)
+		 * A Package containing PAC194x/5x resources (configuration values)
+		 *
+		 * Input Arguments (per _DSM standard):
+		 *
+		 *     Arg0: UUID - Function Identifier
+		 *     Arg1: Integer - Revision
+		 *     Arg2: Integer - Function Index
+		 *     Arg3: Package - Parameters (not used in our implementation)
+		 */
+		Function(_DSM, {BuffObj, PkgObj}, {BuffObj, IntObj, IntObj, PkgObj})
+		{
+			/*
+			 *  Is our UUID being invoked?
+			 */
+			if(LNotEqual(Arg0, ToUUID("721F1534-5D27-4B60-9DF4-41A3C4B7DA3A")))
+			{
+				return(Buffer() {0x0})  /* incorrect UUID, return NULL for error */
+			}
+
+			/*
+			 * Switch based on the function number requested...
+			 */
+			switch(ToInteger(Arg2))
+			{
+				/*
+				 * Function zero returns a bit-mask of supported functions
+				 */
+				case(0)
+				{
+					switch(ToInteger(Arg1)) /* revision check */
+					{
+						/* Revision 0: function 1->7 are supported */
+						case(0) {return (Buffer() {0xFF})}
+					}
+					break;
+				}
+
+				/* Function 1 - returns the names of the monitored power rails. */
+				/* The names should be compliant with Windows EMI power rail taxonomy. */
+				/* If the rail name is NULL ("") -> no EMI created for the channel ("private channel"). */
+				case(1)
+				{
+					Name(BUF1, Package()
+					{
+							/* Rail Name */
+							"SoC_VCCGT_PH1",  /* Channel 1 */
+							"SoC_VCCGT_PH2",  /* Channel 2 */
+							"SoC_VCCSA",      /* Channel 3 */
+							"SoC_VDDQ"        /* Channel 4 */
+					})
+					return(BUF1)
+				}
+
+				/* Function 2 returns the Resistor values expressed in micro-Ohms. */
+				case(2)
+				{
+					/* Return enhanced precision resistor values. */
+					Name(BUF2, Package()
+					{
+							/* Value */
+							2000,   /* Channel 1 */
+							2000,   /* Channel 2 */
+							2000,   /* Channel 3 */
+							2000    /* Channel 4 */
+					})
+					return(BUF2)
+				}
+
+				/* Function 3 - returns the EMI enable/disable bit-mask */
+				case(3)
+				{
+					Name(BUF3, Package()
+					{
+						/* EMI bitmask - CH1:CH2:CH3:CH4 */
+						0xF	/* CHn = 1: EMI enable for channel 'n' */
+							/* CHn = 0: EMI disable for channel 'n' ("private channel") */
+					})
+					return(BUF3)
+				}
+
+				/* Function 4 - returns Vsense and Vbus polarity and full scale range configs */
+				case(4)
+				{
+					Name(BUF4, Package()
+					{
+						/* Vsense configs */
+						0x0, 0x0, 0x0, 0x0,	/* CFG_VS1, CFG_VS2, CFG_VS3, CFG_VS4 */
+									/* CFG_VSn: Vsense configuration for channel 'n' */
+									/* {0x0 = unipolar; 0x1 = bipolar; 0x2 = half scale bipolar} */
+									/* Vbus configs */
+						0x0, 0x0, 0x0, 0x0	/* CFG_VB1, CFG_VB2, CFG_VB3, CFG_VB4 */
+									/* CFG_VBn: Vbus configuration for channel 'n' */
+									/* {0x0 = unipolar; 0x1 = bipolar; 0x2 = half scale bipolar} */
+					})
+					return(BUF4)
+				}
+
+				/* Function 5 - returns the sample frequencies for ACTIVE and IDLE modes */
+				case(5)
+				{
+					Name(BUF5, Package()
+					 {
+						1024, /* ACTIVE sps - accepted values = {1024, 256, 64, 8} */
+						8     /* IDLE sps - accepted values = {1024, 256, 64, 8} */
+					 })
+					return(BUF5)
+				}
+
+				/* Function 6 - returns the REFRESH watchdog timer interval */
+				case(6)
+				{
+					Name(BUF6, Package()
+					{
+						900 /* seconds (min=60, max=60000) */
+					})
+					return(BUF6)
+				}
+
+				/* Function 7 - returns the Vbus multiplication factors for PAC194x/5x-2 */
+				/* PAC194x/5x-2 power meter VBUS+ pins may be connected to voltage dividers */
+				/* to measure rail voltage higher than device Vbus FSR. */
+				case(7)
+				{
+					Name(BUF7, Package()
+					{ /* K = 1000 * (Vrail / Vbus). Must be integer, positive value. */
+						1000, /* Channel 1 K-factor */
+						1000, /* Channel 2 K-factor */
+						1000, /* Channel 3 K-factor */
+						1000  /* Channel 4 K-factor */
+					})
+					return(BUF7)
+				}
+
+			} /* switch(Arg2) */
+			/*
+			 * Return an error (a buffer with a value of zero)
+			 * if we didn't return anything else above
+			 */
+			return(Buffer() {0x0})
+		} /* _DSM */
+	} /* PowerMeter Device PA02 Scope End */
+
+	/*
+	 * PA03 Device: Defines how the PAC194x is connected to the I2C Controller.
+	 */
+	Device(PA03)
+	{
+		Name(_HID, "MCHP1940")
+		Name(_UID, 3)
+
+		/* Lowest power D-State supported by the device is D3 */
+		Name (_S0W, 3)
+
+		/* Device Status: present, enabled, and functioning properly */
+		Method(_STA, 0x0, NotSerialized)
+		{
+			Return (0xf)
+		}
+
+		/*
+		 * Current Resources Settings
+		 */
+		Method(_CRS, 0x0, NotSerialized)
+		{
+			Name(RBUF, ResourceTemplate()
+			{
+				I2CSerialBusV2(0x11,                    /* 7-bit Peripheral Address */
+						ControllerInitiated,    /* Peripheral or Controller? */
+						400000,                 /* Connection Speed in hz */
+						AddressingMode7Bit,     /* 7-bit or 10-bit addressing? */
+						"\\_SB.PCI0.I2C3",      /* I2C Controller to which PAC is connected */
+						0,                      /* Resource Index */
+						ResourceConsumer,       /* Consumer or Producer? */
+						DEV0,)
+			})
+			Return(RBUF)
+		}
+
+		/*
+		 * _DSM - Device Specific Method
+		 *
+		 * This method returns information that PAC194x/5x driver uses for the
+		 * device initial configuration.
+		 *
+		 * The DSM UUID for the Microchip PAC194x/5x: {721F1534-5D27-4B60-9DF4-41A3C4B7DA3A}.
+		 * This must match what the Windows PAC194x/5x driver expects.
+		 *
+		 * Returns:
+		 * Either: A Buffer (for supported Functions, or an error)
+		 * A Package containing PAC194x/5x resources (configuration values)
+		 *
+		 * Input Arguments (per _DSM standard):
+		 *
+		 *     Arg0: UUID - Function Identifier
+		 *     Arg1: Integer - Revision
+		 *     Arg2: Integer - Function Index
+		 *     Arg3: Package - Parameters (not used in our implementation)
+		 */
+		Function(_DSM, {BuffObj, PkgObj}, {BuffObj, IntObj, IntObj, PkgObj})
+		{
+			/*
+			 *  Is our UUID being invoked?
+			 */
+			if(LNotEqual(Arg0, ToUUID("721F1534-5D27-4B60-9DF4-41A3C4B7DA3A")))
+			{
+				return(Buffer() {0x0})  /* incorrect UUID, return NULL for error */
+			}
+
+			/*
+			 * Switch based on the function number requested...
+			 */
+			switch(ToInteger(Arg2))
+			{
+				/*
+				 * Function zero returns a bit-mask of supported functions
+				 */
+				case(0)
+				{
+					switch(ToInteger(Arg1)) /* revision check */
+					{
+						/* Revision 0: function 1->7 are supported */
+						case(0) {return (Buffer() {0xFF})}
+					}
+					break;
+				}
+
+				/* Function 1 - returns the names of the monitored power rails. */
+				/* The names should be compliant with Windows EMI power rail taxonomy. */
+				/* If the rail name is NULL ("") -> no EMI created for the channel ("private channel"). */
+				case(1)
+				{
+					Name(BUF1, Package()
+					{
+							/* Rail Name */
+							"SoC_VCCPRIM_VNNAON", /* Channel 1 */
+							"SoC_VCCPRIM_IO", /* Channel 2 */
+							"SoC_VCCPRIM3P3", /* Channel 3 */
+							"SoC_VCCPRIM1P8"  /* Channel 4 */
+					})
+					return(BUF1)
+				}
+
+				/* Function 2 returns the Resistor values expressed in micro-Ohms. */
+				case(2)
+				{
+					/* Return enhanced precision resistor values. */
+					Name(BUF2, Package()
+					{
+							/* Value */
+							1000,    /* Channel 1 */
+							4000,    /* Channel 2 */
+							22000,   /* Channel 3 */
+							10000    /* Channel 4 */
+					})
+					return(BUF2)
+				}
+
+				/* Function 3 - returns the EMI enable/disable bit-mask */
+				case(3)
+				{
+					Name(BUF3, Package()
+					{
+						/* EMI bitmask - CH1:CH2:CH3:CH4 */
+						0xF	/* CHn = 1: EMI enable for channel 'n' */
+							/* CHn = 0: EMI disable for channel 'n' ("private channel") */
+					})
+					return(BUF3)
+				}
+
+				/* Function 4 - returns Vsense and Vbus polarity and full scale range configs */
+				case(4)
+				{
+					Name(BUF4, Package()
+					{
+						/* Vsense configs */
+						0x0, 0x0, 0x0, 0x0,	/* CFG_VS1, CFG_VS2, CFG_VS3, CFG_VS4 */
+									/* CFG_VSn: Vsense configuration for channel 'n' */
+									/* {0x0 = unipolar; 0x1 = bipolar; 0x2 = half scale bipolar} */
+									/* Vbus configs */
+						0x0, 0x0, 0x0, 0x0	/* CFG_VB1, CFG_VB2, CFG_VB3, CFG_VB4 */
+									/* CFG_VBn: Vbus configuration for channel 'n' */
+									/* {0x0 = unipolar; 0x1 = bipolar; 0x2 = half scale bipolar} */
+					})
+					return(BUF4)
+				}
+
+				/* Function 5 - returns the sample frequencies for ACTIVE and IDLE modes */
+				case(5)
+				{
+					Name(BUF5, Package()
+					 {
+						1024, /* ACTIVE sps - accepted values = {1024, 256, 64, 8} */
+						8     /* IDLE sps - accepted values = {1024, 256, 64, 8} */
+					 })
+					return(BUF5)
+				}
+
+				/* Function 6 - returns the REFRESH watchdog timer interval */
+				case(6)
+				{
+					Name(BUF6, Package()
+					{
+						900 /* seconds (min=60, max=60000) */
+					})
+					return(BUF6)
+				}
+
+				/* Function 7 - returns the Vbus multiplication factors for PAC194x/5x-2 */
+				/* PAC194x/5x-2 power meter VBUS+ pins may be connected to voltage dividers */
+				/* to measure rail voltage higher than device Vbus FSR. */
+				case(7)
+				{
+					Name(BUF7, Package()
+					{ /* K = 1000 * (Vrail / Vbus). Must be integer, positive value. */
+						1000, /* Channel 1 K-factor */
+						1000, /* Channel 2 K-factor */
+						1000, /* Channel 3 K-factor */
+						1000  /* Channel 4 K-factor */
+					})
+					return(BUF7)
+				}
+
+			} /* switch(Arg2) */
+			/*
+			 * Return an error (a buffer with a value of zero)
+			 * if we didn't return anything else above
+			 */
+			return(Buffer() {0x0})
+		} /* _DSM */
+	} /* PowerMeter Device PA03 Scope End */
+
+	/*
+	 * PA04 Device: Defines how the PAC194x is connected to the I2C Controller.
+	 */
+	Device(PA04)
+	{
+		Name(_HID, "MCHP1940")
+		Name(_UID, 4)
+
+		/* Lowest power D-State supported by the device is D3 */
+		Name (_S0W, 3)
+
+		/* Device Status: present, enabled, and functioning properly */
+		Method(_STA, 0x0, NotSerialized)
+		{
+			Return (0xf)
+		}
+
+		/*
+		 * Current Resources Settings
+		 */
+		Method(_CRS, 0x0, NotSerialized)
+		{
+			Name(RBUF, ResourceTemplate()
+			{
+				I2CSerialBusV2(0x15,                    /* 7-bit Peripheral Address */
+						ControllerInitiated,    /* Peripheral or Controller? */
+						400000,                 /* Connection Speed in hz */
+						AddressingMode7Bit,     /* 7-bit or 10-bit addressing? */
+						"\\_SB.PCI0.I2C3",      /* I2C Controller to which PAC is connected */
+						0,                      /* Resource Index */
+						ResourceConsumer,       /* Consumer or Producer? */
+						DEV0,)
+			})
+			Return(RBUF)
+		}
+
+		/*
+		 * _DSM - Device Specific Method
+		 *
+		 * This method returns information that PAC194x/5x driver uses for the
+		 * device initial configuration.
+		 *
+		 * The DSM UUID for the Microchip PAC194x/5x: {721F1534-5D27-4B60-9DF4-41A3C4B7DA3A}.
+		 * This must match what the Windows PAC194x/5x driver expects.
+		 *
+		 * Returns:
+		 * Either: A Buffer (for supported Functions, or an error)
+		 * A Package containing PAC194x/5x resources (configuration values)
+		 *
+		 * Input Arguments (per _DSM standard):
+		 *
+		 *     Arg0: UUID - Function Identifier
+		 *     Arg1: Integer - Revision
+		 *     Arg2: Integer - Function Index
+		 *     Arg3: Package - Parameters (not used in our implementation)
+		 */
+		Function(_DSM, {BuffObj, PkgObj}, {BuffObj, IntObj, IntObj, PkgObj})
+		{
+			/*
+			 *  Is our UUID being invoked?
+			 */
+			if(LNotEqual(Arg0, ToUUID("721F1534-5D27-4B60-9DF4-41A3C4B7DA3A")))
+			{
+				return(Buffer() {0x0})  /* incorrect UUID, return NULL for error */
+			}
+
+			/*
+			 * Switch based on the function number requested...
+			 */
+			switch(ToInteger(Arg2))
+			{
+				/*
+				 * Function zero returns a bit-mask of supported functions
+				 */
+				case(0)
+				{
+					switch(ToInteger(Arg1)) /* revision check */
+					{
+						/* Revision 0: function 1->7 are supported */
+						case(0) {return (Buffer() {0xFF})}
+					}
+					break;
+				}
+
+				/* Function 1 - returns the names of the monitored power rails. */
+				/* The names should be compliant with Windows EMI power rail taxonomy. */
+				/* If the rail name is NULL ("") -> no EMI created for the channel ("private channel"). */
+				case(1)
+				{
+					Name(BUF1, Package()
+					{
+							/* Rail Name */
+							"SoC_VCCRTC",   /* Channel 1 */
+							"SoC_VCCST",    /* Channel 2 */
+							"SoC_VDD2_CPU", /* Channel 3 */
+							"SoC_VDDQ_CPU"  /* Channel 4 */
+					})
+					return(BUF1)
+				}
+
+				/* Function 2 returns the Resistor values expressed in micro-Ohms. */
+				case(2)
+				{
+					/* Return enhanced precision resistor values. */
+					Name(BUF2, Package()
+					{
+							/* Value */
+							22000,    /* Channel 1 */
+							2000,    /* Channel 2 */
+							2000,   /* Channel 3 */
+							5000    /* Channel 4 */
+					})
+					return(BUF2)
+				}
+
+				/* Function 3 - returns the EMI enable/disable bit-mask */
+				case(3)
+				{
+					Name(BUF3, Package()
+					{
+						/* EMI bitmask - CH1:CH2:CH3:CH4 */
+						0xF	/* CHn = 1: EMI enable for channel 'n' */
+							/* CHn = 0: EMI disable for channel 'n' ("private channel") */
+					})
+					return(BUF3)
+				}
+
+				/* Function 4 - returns Vsense and Vbus polarity and full scale range configs */
+				case(4)
+				{
+					Name(BUF4, Package()
+					{
+						/* Vsense configs */
+						0x0, 0x0, 0x0, 0x0,	/* CFG_VS1, CFG_VS2, CFG_VS3, CFG_VS4 */
+									/* CFG_VSn: Vsense configuration for channel 'n' */
+									/* {0x0 = unipolar; 0x1 = bipolar; 0x2 = half scale bipolar} */
+									/* Vbus configs */
+						0x0, 0x0, 0x0, 0x0	/* CFG_VB1, CFG_VB2, CFG_VB3, CFG_VB4 */
+									/* CFG_VBn: Vbus configuration for channel 'n' */
+									/* {0x0 = unipolar; 0x1 = bipolar; 0x2 = half scale bipolar} */
+					})
+					return(BUF4)
+				}
+
+				/* Function 5 - returns the sample frequencies for ACTIVE and IDLE modes */
+				case(5)
+				{
+					Name(BUF5, Package()
+					 {
+						1024, /* ACTIVE sps - accepted values = {1024, 256, 64, 8} */
+						8     /* IDLE sps - accepted values = {1024, 256, 64, 8} */
+					 })
+					return(BUF5)
+				}
+
+				/* Function 6 - returns the REFRESH watchdog timer interval */
+				case(6)
+				{
+					Name(BUF6, Package()
+					{
+						900 /* seconds (min=60, max=60000) */
+					})
+					return(BUF6)
+				}
+
+				/* Function 7 - returns the Vbus multiplication factors for PAC194x/5x-2 */
+				/* PAC194x/5x-2 power meter VBUS+ pins may be connected to voltage dividers */
+				/* to measure rail voltage higher than device Vbus FSR. */
+				case(7)
+				{
+					Name(BUF7, Package()
+					{ /* K = 1000 * (Vrail / Vbus). Must be integer, positive value. */
+						1000, /* Channel 1 K-factor */
+						1000, /* Channel 2 K-factor */
+						1000, /* Channel 3 K-factor */
+						1000  /* Channel 4 K-factor */
+					})
+					return(BUF7)
+				}
+
+			} /* switch(Arg2) */
+			/*
+			 * Return an error (a buffer with a value of zero)
+			 * if we didn't return anything else above
+			 */
+			return(Buffer() {0x0})
+		} /* _DSM */
+	} /* PowerMeter Device PA04 Scope End */
+
+	/*
+	 * PA05 Device: Defines how the PAC194x is connected to the I2C Controller.
+	 */
+	Device(PA05)
+	{
+		Name(_HID, "MCHP1940")
+		Name(_UID, 5)
+
+		/* Lowest power D-State supported by the device is D3 */
+		Name (_S0W, 3)
+
+		/* Device Status: present, enabled, and functioning properly */
+		Method(_STA, 0x0, NotSerialized)
+		{
+			Return (0xf)
+		}
+
+		/*
+		 * Current Resources Settings
+		 */
+		Method(_CRS, 0x0, NotSerialized)
+		{
+			Name(RBUF, ResourceTemplate()
+			{
+				I2CSerialBusV2(0x19,                    /* 7-bit Peripheral Address */
+						ControllerInitiated,    /* Peripheral or Controller? */
+						400000,                 /* Connection Speed in hz */
+						AddressingMode7Bit,     /* 7-bit or 10-bit addressing? */
+						"\\_SB.PCI0.I2C3",      /* I2C Controller to which PAC is connected */
+						0,                      /* Resource Index */
+						ResourceConsumer,       /* Consumer or Producer? */
+						DEV0,)
+			})
+			Return(RBUF)
+		}
+
+		/*
+		 * _DSM - Device Specific Method
+		 *
+		 * This method returns information that PAC194x/5x driver uses for the
+		 * device initial configuration.
+		 *
+		 * The DSM UUID for the Microchip PAC194x/5x: {721F1534-5D27-4B60-9DF4-41A3C4B7DA3A}.
+		 * This must match what the Windows PAC194x/5x driver expects.
+		 *
+		 * Returns:
+		 * Either: A Buffer (for supported Functions, or an error)
+		 * A Package containing PAC194x/5x resources (configuration values)
+		 *
+		 * Input Arguments (per _DSM standard):
+		 *
+		 *     Arg0: UUID - Function Identifier
+		 *     Arg1: Integer - Revision
+		 *     Arg2: Integer - Function Index
+		 *     Arg3: Package - Parameters (not used in our implementation)
+		 */
+		Function(_DSM, {BuffObj, PkgObj}, {BuffObj, IntObj, IntObj, PkgObj})
+		{
+			/*
+			 *  Is our UUID being invoked?
+			 */
+			if(LNotEqual(Arg0, ToUUID("721F1534-5D27-4B60-9DF4-41A3C4B7DA3A")))
+			{
+				return(Buffer() {0x0})  /* incorrect UUID, return NULL for error */
+			}
+
+			/*
+			 * Switch based on the function number requested...
+			 */
+			switch(ToInteger(Arg2))
+			{
+				/*
+				 * Function zero returns a bit-mask of supported functions
+				 */
+				case(0)
+				{
+					switch(ToInteger(Arg1)) /* revision check */
+					{
+						/* Revision 0: function 1->7 are supported */
+						case(0) {return (Buffer() {0xFF})}
+					}
+					break;
+				}
+
+				/* Function 1 - returns the names of the monitored power rails. */
+				/* The names should be compliant with Windows EMI power rail taxonomy. */
+				/* If the rail name is NULL ("") -> no EMI created for the channel ("private channel"). */
+				case(1)
+				{
+					Name(BUF1, Package()
+					{
+							/* Rail Name */
+							"DRAM_VDD2H",   /* Channel 1 */
+							"DRAM_VDD2L",   /* Channel 2 */
+							"DRAM_VDDQ",    /* Channel 3 */
+							"DRAM_VDD1"     /* Channel 4 */
+					})
+					return(BUF1)
+				}
+
+				/* Function 2 returns the Resistor values expressed in micro-Ohms. */
+				case(2)
+				{
+					/* Return enhanced precision resistor values. */
+					Name(BUF2, Package()
+					{
+							/* Value */
+							2000,    /* Channel 1 */
+							5000,    /* Channel 2 */
+							5000,    /* Channel 3 */
+							5000     /* Channel 4 */
+					})
+					return(BUF2)
+				}
+
+				/* Function 3 - returns the EMI enable/disable bit-mask */
+				case(3)
+				{
+					Name(BUF3, Package()
+					{
+						/* EMI bitmask - CH1:CH2:CH3:CH4 */
+						0xF	/* CHn = 1: EMI enable for channel 'n' */
+							/* CHn = 0: EMI disable for channel 'n' ("private channel") */
+					})
+					return(BUF3)
+				}
+
+				/* Function 4 - returns Vsense and Vbus polarity and full scale range configs */
+				case(4)
+				{
+					Name(BUF4, Package()
+					{
+						/* Vsense configs */
+						0x0, 0x0, 0x0, 0x0,	/* CFG_VS1, CFG_VS2, CFG_VS3, CFG_VS4 */
+									/* CFG_VSn: Vsense configuration for channel 'n' */
+									/* {0x0 = unipolar; 0x1 = bipolar; 0x2 = half scale bipolar} */
+									/* Vbus configs */
+						0x0, 0x0, 0x0, 0x0	/* CFG_VB1, CFG_VB2, CFG_VB3, CFG_VB4 */
+									/* CFG_VBn: Vbus configuration for channel 'n' */
+									/* {0x0 = unipolar; 0x1 = bipolar; 0x2 = half scale bipolar} */
+					})
+					return(BUF4)
+				}
+
+				/* Function 5 - returns the sample frequencies for ACTIVE and IDLE modes */
+				case(5)
+				{
+					Name(BUF5, Package()
+					 {
+						1024, /* ACTIVE sps - accepted values = {1024, 256, 64, 8} */
+						8     /* IDLE sps - accepted values = {1024, 256, 64, 8} */
+					 })
+					return(BUF5)
+				}
+
+				/* Function 6 - returns the REFRESH watchdog timer interval */
+				case(6)
+				{
+					Name(BUF6, Package()
+					{
+						900 /* seconds (min=60, max=60000) */
+					})
+					return(BUF6)
+				}
+
+				/* Function 7 - returns the Vbus multiplication factors for PAC194x/5x-2 */
+				/* PAC194x/5x-2 power meter VBUS+ pins may be connected to voltage dividers */
+				/* to measure rail voltage higher than device Vbus FSR. */
+				case(7)
+				{
+					Name(BUF7, Package()
+					{ /* K = 1000 * (Vrail / Vbus). Must be integer, positive value. */
+						1000, /* Channel 1 K-factor */
+						1000, /* Channel 2 K-factor */
+						1000, /* Channel 3 K-factor */
+						1000  /* Channel 4 K-factor */
+					})
+					return(BUF7)
+				}
+
+			} /* switch(Arg2) */
+			/*
+			 * Return an error (a buffer with a value of zero)
+			 * if we didn't return anything else above
+			 */
+			return(Buffer() {0x0})
+		} /* _DSM */
+	} /* PowerMeter Device PA05 Scope End */
+
+	/*
+	 * PA06 Device: Defines how the PAC194x is connected to the I2C Controller.
+	 */
+	Device(PA06)
+	{
+		Name(_HID, "MCHP1940")
+		Name(_UID, 6)
+
+		/* Lowest power D-State supported by the device is D3 */
+		Name (_S0W, 3)
+
+		/* Device Status: present, enabled, and functioning properly */
+		Method(_STA, 0x0, NotSerialized)
+		{
+			Return (0xf)
+		}
+
+		/*
+		 * Current Resources Settings
+		 */
+		Method(_CRS, 0x0, NotSerialized)
+		{
+			Name(RBUF, ResourceTemplate()
+			{
+				I2CSerialBusV2(0x14,                    /* 7-bit Peripheral Address */
+						ControllerInitiated,    /* Peripheral or Controller? */
+						400000,                 /* Connection Speed in hz */
+						AddressingMode7Bit,     /* 7-bit or 10-bit addressing? */
+						"\\_SB.PCI0.I2C3",      /* I2C Controller to which PAC is connected */
+						0,                      /* Resource Index */
+						ResourceConsumer,       /* Consumer or Producer? */
+						DEV0,)
+			})
+			Return(RBUF)
+		}
+
+		/*
+		 * _DSM - Device Specific Method
+		 *
+		 * This method returns information that PAC194x/5x driver uses for the
+		 * device initial configuration.
+		 *
+		 * The DSM UUID for the Microchip PAC194x/5x: {721F1534-5D27-4B60-9DF4-41A3C4B7DA3A}.
+		 * This must match what the Windows PAC194x/5x driver expects.
+		 *
+		 * Returns:
+		 * Either: A Buffer (for supported Functions, or an error)
+		 * A Package containing PAC194x/5x resources (configuration values)
+		 *
+		 * Input Arguments (per _DSM standard):
+		 *
+		 *     Arg0: UUID - Function Identifier
+		 *     Arg1: Integer - Revision
+		 *     Arg2: Integer - Function Index
+		 *     Arg3: Package - Parameters (not used in our implementation)
+		 */
+		Function(_DSM, {BuffObj, PkgObj}, {BuffObj, IntObj, IntObj, PkgObj})
+		{
+			/*
+			 *  Is our UUID being invoked?
+			 */
+			if(LNotEqual(Arg0, ToUUID("721F1534-5D27-4B60-9DF4-41A3C4B7DA3A")))
+			{
+				return(Buffer() {0x0})  /* incorrect UUID, return NULL for error */
+			}
+
+			/*
+			 * Switch based on the function number requested...
+			 */
+			switch(ToInteger(Arg2))
+			{
+				/*
+				 * Function zero returns a bit-mask of supported functions
+				 */
+				case(0)
+				{
+					switch(ToInteger(Arg1)) /* revision check */
+					{
+						/* Revision 0: function 1->7 are supported */
+						case(0) {return (Buffer() {0xFF})}
+					}
+					break;
+				}
+
+				/* Function 1 - returns the names of the monitored power rails. */
+				/* The names should be compliant with Windows EMI power rail taxonomy. */
+				/* If the rail name is NULL ("") -> no EMI created for the channel ("private channel"). */
+				case(1)
+				{
+					Name(BUF1, Package()
+					{
+							/* Rail Name */
+							"DISPLAY_BKLIGHT",    /* Channel 1 */
+							"DISPLAY_VDD",        /* Channel 2 */
+							"CONNECTIVITY_WLAN",  /* Channel 3 */
+							"STORAGE_V3P3A"       /* Channel 4 */
+					})
+					return(BUF1)
+				}
+
+				/* Function 2 returns the Resistor values expressed in micro-Ohms. */
+				case(2)
+				{
+					/* Return enhanced precision resistor values. */
+					Name(BUF2, Package()
+					{
+							/* Value */
+							10000,    /* Channel 1 */
+							10000,    /* Channel 2 */
+							5000,    /* Channel 3 */
+							5000     /* Channel 4 */
+					})
+					return(BUF2)
+				}
+
+				/* Function 3 - returns the EMI enable/disable bit-mask */
+				case(3)
+				{
+					Name(BUF3, Package()
+					{
+						/* EMI bitmask - CH1:CH2:CH3:CH4 */
+						0xF	/* CHn = 1: EMI enable for channel 'n' */
+							/* CHn = 0: EMI disable for channel 'n' ("private channel") */
+					})
+					return(BUF3)
+				}
+
+				/* Function 4 - returns Vsense and Vbus polarity and full scale range configs */
+				case(4)
+				{
+					Name(BUF4, Package()
+					{
+						/* Vsense configs */
+						0x0, 0x0, 0x0, 0x0,	/* CFG_VS1, CFG_VS2, CFG_VS3, CFG_VS4 */
+									/* CFG_VSn: Vsense configuration for channel 'n' */
+									/* {0x0 = unipolar; 0x1 = bipolar; 0x2 = half scale bipolar} */
+									/* Vbus configs */
+						0x0, 0x0, 0x0, 0x0	/* CFG_VB1, CFG_VB2, CFG_VB3, CFG_VB4 */
+									/* CFG_VBn: Vbus configuration for channel 'n' */
+									/* {0x0 = unipolar; 0x1 = bipolar; 0x2 = half scale bipolar} */
+					})
+					return(BUF4)
+				}
+
+				/* Function 5 - returns the sample frequencies for ACTIVE and IDLE modes */
+				case(5)
+				{
+					Name(BUF5, Package()
+					 {
+						1024, /* ACTIVE sps - accepted values = {1024, 256, 64, 8} */
+						8     /* IDLE sps - accepted values = {1024, 256, 64, 8} */
+					 })
+					return(BUF5)
+				}
+
+				/* Function 6 - returns the REFRESH watchdog timer interval */
+				case(6)
+				{
+					Name(BUF6, Package()
+					{
+						900 /* seconds (min=60, max=60000) */
+					})
+					return(BUF6)
+				}
+
+				/* Function 7 - returns the Vbus multiplication factors for PAC194x/5x-2 */
+				/* PAC194x/5x-2 power meter VBUS+ pins may be connected to voltage dividers */
+				/* to measure rail voltage higher than device Vbus FSR. */
+				case(7)
+				{
+					Name(BUF7, Package()
+					{ /* K = 1000 * (Vrail / Vbus). Must be integer, positive value. */
+						1000, /* Channel 1 K-factor */
+						1000, /* Channel 2 K-factor */
+						1000, /* Channel 3 K-factor */
+						1000  /* Channel 4 K-factor */
+					})
+					return(BUF7)
+				}
+
+			} /* switch(Arg2) */
+			/*
+			 * Return an error (a buffer with a value of zero)
+			 * if we didn't return anything else above
+			 */
+			return(Buffer() {0x0})
+		} /* _DSM */
+	} /* PowerMeter Device PA06 Scope End */
+
+	/*
+	 * PA07 Device: Defines how the PAC194x is connected to the I2C Controller.
+	 */
+	Device(PA07)
+	{
+		Name(_HID, "MCHP1940")
+		Name(_UID, 7)
+
+		/* Lowest power D-State supported by the device is D3 */
+		Name (_S0W, 3)
+
+		/* Device Status: present, enabled, and functioning properly */
+		Method(_STA, 0x0, NotSerialized)
+		{
+			Return (0xf)
+		}
+
+		/*
+		 * Current Resources Settings
+		 */
+		Method(_CRS, 0x0, NotSerialized)
+		{
+			Name(RBUF, ResourceTemplate()
+			{
+				I2CSerialBusV2(0x17,                    /* 7-bit Peripheral Address */
+						ControllerInitiated,    /* Peripheral or Controller? */
+						400000,                 /* Connection Speed in hz */
+						AddressingMode7Bit,     /* 7-bit or 10-bit addressing? */
+						"\\_SB.PCI0.I2C3",      /* I2C Controller to which PAC is connected */
+						0,                      /* Resource Index */
+						ResourceConsumer,       /* Consumer or Producer? */
+						DEV0,)
+			})
+			Return(RBUF)
+		}
+
+		/*
+		 * _DSM - Device Specific Method
+		 *
+		 * This method returns information that PAC194x/5x driver uses for the
+		 * device initial configuration.
+		 *
+		 * The DSM UUID for the Microchip PAC194x/5x: {721F1534-5D27-4B60-9DF4-41A3C4B7DA3A}.
+		 * This must match what the Windows PAC194x/5x driver expects.
+		 *
+		 * Returns:
+		 * Either: A Buffer (for supported Functions, or an error)
+		 * A Package containing PAC194x/5x resources (configuration values)
+		 *
+		 * Input Arguments (per _DSM standard):
+		 *
+		 *     Arg0: UUID - Function Identifier
+		 *     Arg1: Integer - Revision
+		 *     Arg2: Integer - Function Index
+		 *     Arg3: Package - Parameters (not used in our implementation)
+		 */
+		Function(_DSM, {BuffObj, PkgObj}, {BuffObj, IntObj, IntObj, PkgObj})
+		{
+			/*
+			 *  Is our UUID being invoked?
+			 */
+			if(LNotEqual(Arg0, ToUUID("721F1534-5D27-4B60-9DF4-41A3C4B7DA3A")))
+			{
+				return(Buffer() {0x0})  /* incorrect UUID, return NULL for error */
+			}
+
+			/*
+			 * Switch based on the function number requested...
+			 */
+			switch(ToInteger(Arg2))
+			{
+				/*
+				 * Function zero returns a bit-mask of supported functions
+				 */
+				case(0)
+				{
+					switch(ToInteger(Arg1)) /* revision check */
+					{
+						/* Revision 0: function 1->7 are supported */
+						case(0) {return (Buffer() {0xFF})}
+					}
+					break;
+				}
+
+				/* Function 1 - returns the names of the monitored power rails. */
+				/* The names should be compliant with Windows EMI power rail taxonomy. */
+				/* If the rail name is NULL ("") -> no EMI created for the channel ("private channel"). */
+				case(1)
+				{
+					Name(BUF1, Package()
+					{
+							/* Rail Name */
+							"SYSTEM_VBATA1",    /* Channel 1 */
+							"SYSTEM_VBATA2",    /* Channel 2 */
+							"CAMERA_V1P8S",     /* Channel 3 */
+							"CAMERA_V3P3S"      /* Channel 4 */
+					})
+					return(BUF1)
+				}
+
+				/* Function 2 returns the Resistor values expressed in micro-Ohms. */
+				case(2)
+				{
+					/* Return enhanced precision resistor values. */
+					Name(BUF2, Package()
+					{
+							/* Value */
+							2000,    /* Channel 1 */
+							2000,    /* Channel 2 */
+							10000,   /* Channel 3 */
+							10000    /* Channel 4 */
+					})
+					return(BUF2)
+				}
+
+				/* Function 3 - returns the EMI enable/disable bit-mask */
+				case(3)
+				{
+					Name(BUF3, Package()
+					{
+						/* EMI bitmask - CH1:CH2:CH3:CH4 */
+						0xF	/* CHn = 1: EMI enable for channel 'n' */
+							/* CHn = 0: EMI disable for channel 'n' ("private channel") */
+					})
+					return(BUF3)
+				}
+
+				/* Function 4 - returns Vsense and Vbus polarity and full scale range configs */
+				case(4)
+				{
+					Name(BUF4, Package()
+					{
+						/* Vsense configs */
+						0x0, 0x0, 0x0, 0x0,	/* CFG_VS1, CFG_VS2, CFG_VS3, CFG_VS4 */
+									/* CFG_VSn: Vsense configuration for channel 'n' */
+									/* {0x0 = unipolar; 0x1 = bipolar; 0x2 = half scale bipolar} */
+									/* Vbus configs */
+						0x0, 0x0, 0x0, 0x0	/* CFG_VB1, CFG_VB2, CFG_VB3, CFG_VB4 */
+									/* CFG_VBn: Vbus configuration for channel 'n' */
+									/* {0x0 = unipolar; 0x1 = bipolar; 0x2 = half scale bipolar} */
+					})
+					return(BUF4)
+				}
+
+				/* Function 5 - returns the sample frequencies for ACTIVE and IDLE modes */
+				case(5)
+				{
+					Name(BUF5, Package()
+					 {
+						1024, /* ACTIVE sps - accepted values = {1024, 256, 64, 8} */
+						8     /* IDLE sps - accepted values = {1024, 256, 64, 8} */
+					 })
+					return(BUF5)
+				}
+
+				/* Function 6 - returns the REFRESH watchdog timer interval */
+				case(6)
+				{
+					Name(BUF6, Package()
+					{
+						900 /* seconds (min=60, max=60000) */
+					})
+					return(BUF6)
+				}
+
+				/* Function 7 - returns the Vbus multiplication factors for PAC194x/5x-2 */
+				/* PAC194x/5x-2 power meter VBUS+ pins may be connected to voltage dividers */
+				/* to measure rail voltage higher than device Vbus FSR. */
+				case(7)
+				{
+					Name(BUF7, Package()
+					{ /* K = 1000 * (Vrail / Vbus). Must be integer, positive value. */
+						1000, /* Channel 1 K-factor */
+						1000, /* Channel 2 K-factor */
+						1000, /* Channel 3 K-factor */
+						1000  /* Channel 4 K-factor */
+					})
+					return(BUF7)
+				}
+
+			} /* switch(Arg2) */
+			/*
+			 * Return an error (a buffer with a value of zero)
+			 * if we didn't return anything else above
+			 */
+			return(Buffer() {0x0})
+		} /* _DSM */
+	} /* PowerMeter Device PA07 Scope End */
+} /* Scope I2C3 */
diff --git a/src/mainboard/intel/ptlrvp/dsdt.asl b/src/mainboard/intel/ptlrvp/dsdt.asl
index 03882c6327..ec2a104319 100644
--- a/src/mainboard/intel/ptlrvp/dsdt.asl
+++ b/src/mainboard/intel/ptlrvp/dsdt.asl
@@ -39,4 +39,6 @@ DefinitionBlock(
 #endif
 
 	#include <southbridge/intel/common/acpi/sleepstates.asl>
+
+	#include <acpi/power_meter.asl>
 }

From 1d02f139d3988e0b9e8ada928992a03cb5d4ef5b Mon Sep 17 00:00:00 2001
From: Jeremy Compostella <jeremy.compostella@intel.com>
Date: Thu, 4 Sep 2025 14:46:47 -0700
Subject: [PATCH 2271/3886] mb/google/fatcat: Add wake configuration to
 cnvi_bluetooth

This commit adds a wake configuration to the cnvi_bluetooth device for
all the Fatcat board variants. The "wake" setting is now registered to
"GPE0_PME_B0" using the common CNVi block. This enhancement ensures that
the cnvi_bluetooth device can properly wake the system.

TEST=Able to wake up the device from a low power state using a keyboard
     Bluetooth device.

Change-Id: Id0ef732d45b46a3f59456860d9070fffdab05509
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89058
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
---
 .../google/fatcat/variants/fatcat/overridetree.cb          | 4 ++++
 .../google/fatcat/variants/felino/overridetree.cb          | 4 ++++
 .../google/fatcat/variants/francka/overridetree.cb         | 7 ++++++-
 .../google/fatcat/variants/kinmen/overridetree.cb          | 7 ++++++-
 src/mainboard/google/fatcat/variants/lapis/overridetree.cb | 4 ++++
 .../google/fatcat/variants/moonstone/overridetree.cb       | 7 ++++++-
 6 files changed, 30 insertions(+), 3 deletions(-)

diff --git a/src/mainboard/google/fatcat/variants/fatcat/overridetree.cb b/src/mainboard/google/fatcat/variants/fatcat/overridetree.cb
index 4c75c332ca..f98fb46d53 100644
--- a/src/mainboard/google/fatcat/variants/fatcat/overridetree.cb
+++ b/src/mainboard/google/fatcat/variants/fatcat/overridetree.cb
@@ -641,6 +641,10 @@ chip soc/intel/pantherlake
 		device ref cnvi_bluetooth on
 			probe WIFI WIFI_CNVI_6
 			probe WIFI WIFI_CNVI_7
+			chip soc/intel/common/block/cnvi
+				register "wake" = "GPE0_PME_B0"
+				device generic 0 on end
+			end
 		end
 
 		# NOTE: i2c0 is function 0; hence it needs to be enabled when any of i2c1-5 is enabled.
diff --git a/src/mainboard/google/fatcat/variants/felino/overridetree.cb b/src/mainboard/google/fatcat/variants/felino/overridetree.cb
index 7d80164942..b4869ead78 100644
--- a/src/mainboard/google/fatcat/variants/felino/overridetree.cb
+++ b/src/mainboard/google/fatcat/variants/felino/overridetree.cb
@@ -331,6 +331,10 @@ device ref tbt_pcie_rp0 on end
 		device ref cnvi_bluetooth on
 			probe WIFI WIFI_CNVI_6
 			probe WIFI WIFI_CNVI_7
+			chip soc/intel/common/block/cnvi
+				register "wake" = "GPE0_PME_B0"
+				device generic 0 on end
+			end
 		end
 
 		device ref i2c0 on end
diff --git a/src/mainboard/google/fatcat/variants/francka/overridetree.cb b/src/mainboard/google/fatcat/variants/francka/overridetree.cb
index 68e3b6635a..4b758ea293 100644
--- a/src/mainboard/google/fatcat/variants/francka/overridetree.cb
+++ b/src/mainboard/google/fatcat/variants/francka/overridetree.cb
@@ -190,7 +190,12 @@ chip soc/intel/pantherlake
 			end
 		end # CNVi
 
-		device ref cnvi_bluetooth on end
+		device ref cnvi_bluetooth on
+			chip soc/intel/common/block/cnvi
+				register "wake" = "GPE0_PME_B0"
+				device generic 0 on end
+			end
+		end
 
 		# NOTE: i2c0 is function 0; hence it needs to be enabled when any of i2c1-5 is enabled.
 		# TPM device is under i2c1. Therefore, i2c0 needs to be enabled anyways.
diff --git a/src/mainboard/google/fatcat/variants/kinmen/overridetree.cb b/src/mainboard/google/fatcat/variants/kinmen/overridetree.cb
index e710082746..2a9b91b05a 100644
--- a/src/mainboard/google/fatcat/variants/kinmen/overridetree.cb
+++ b/src/mainboard/google/fatcat/variants/kinmen/overridetree.cb
@@ -392,7 +392,12 @@ chip soc/intel/pantherlake
 			end
 		end # CNVi
 
-		device ref cnvi_bluetooth on end
+		device ref cnvi_bluetooth on
+			chip soc/intel/common/block/cnvi
+				register "wake" = "GPE0_PME_B0"
+				device generic 0 on end
+			end
+		end
 
 		# NOTE: i2c0 is function 0; hence it needs to be enabled when any of i2c1-5 is enabled.
 		# TPM device is under i2c3. Therefore, i2c0 needs to be enabled anyways.
diff --git a/src/mainboard/google/fatcat/variants/lapis/overridetree.cb b/src/mainboard/google/fatcat/variants/lapis/overridetree.cb
index f206e272ab..39da99b14c 100644
--- a/src/mainboard/google/fatcat/variants/lapis/overridetree.cb
+++ b/src/mainboard/google/fatcat/variants/lapis/overridetree.cb
@@ -398,6 +398,10 @@ chip soc/intel/pantherlake
 		device ref cnvi_bluetooth on
 			probe WIFI WIFI_CNVI_7
 			probe WIFI WIFI_CNVI_7E
+			chip soc/intel/common/block/cnvi
+				register "wake" = "GPE0_PME_B0"
+				device generic 0 on end
+			end
 		end
 
 		device ref thc0 on
diff --git a/src/mainboard/google/fatcat/variants/moonstone/overridetree.cb b/src/mainboard/google/fatcat/variants/moonstone/overridetree.cb
index 535d0a902b..be75530d76 100644
--- a/src/mainboard/google/fatcat/variants/moonstone/overridetree.cb
+++ b/src/mainboard/google/fatcat/variants/moonstone/overridetree.cb
@@ -299,7 +299,12 @@ chip soc/intel/pantherlake
 			end
 		end # CNVi
 
-		device ref cnvi_bluetooth on end
+		device ref cnvi_bluetooth on
+			chip soc/intel/common/block/cnvi
+				register "wake" = "GPE0_PME_B0"
+				device generic 0 on end
+			end
+		end
 
 		# NOTE: i2c0 is function 0; hence it needs to be enabled when any of i2c1-5 is enabled.
 		# TPM device is under i2c3. Therefore, i2c0 needs to be enabled anyways.

From 08efea5141f4b77525a3dfde23d5176cd52e710a Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Fri, 10 Oct 2025 13:33:37 -0500
Subject: [PATCH 2272/3886] mb/purism/librem_cnl: Add CFR option menu support

Add CFR option menu support when using edk2 payload and SMMSTORE.
Drop the Intel ME-related options since these boards ship with the
ME disabled via HAP. Restrict the power-on-after-fail settings to
the Mini boards since it doesn't really make sense for a laptop.

TEST=build/boot purism librem_mini_v2, verify CFR option functionality.

Change-Id: I0945ad7ddcafc6970a69777ace53d09bb37c749f
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89532
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
---
 src/mainboard/purism/librem_cnl/Kconfig     |  1 +
 src/mainboard/purism/librem_cnl/Makefile.mk |  1 +
 src/mainboard/purism/librem_cnl/cfr.c       | 46 +++++++++++++++++++++
 3 files changed, 48 insertions(+)
 create mode 100644 src/mainboard/purism/librem_cnl/cfr.c

diff --git a/src/mainboard/purism/librem_cnl/Kconfig b/src/mainboard/purism/librem_cnl/Kconfig
index a718678605..6bbd9c2c11 100644
--- a/src/mainboard/purism/librem_cnl/Kconfig
+++ b/src/mainboard/purism/librem_cnl/Kconfig
@@ -4,6 +4,7 @@ config BOARD_PURISM_BASEBOARD_LIBREM_CNL
 	def_bool n
 	select BOARD_ROMSIZE_KB_16384
 	select DRIVERS_GENERIC_CBFS_SERIAL
+	select DRIVERS_OPTION_CFR_ENABLED if PAYLOAD_EDK2 && SMMSTORE
 	select DRIVERS_USB_ACPI
 	select HAVE_ACPI_RESUME
 	select HAVE_ACPI_TABLES
diff --git a/src/mainboard/purism/librem_cnl/Makefile.mk b/src/mainboard/purism/librem_cnl/Makefile.mk
index 131385e255..e4144c9649 100644
--- a/src/mainboard/purism/librem_cnl/Makefile.mk
+++ b/src/mainboard/purism/librem_cnl/Makefile.mk
@@ -6,6 +6,7 @@ ramstage-y += variants/$(VARIANT_DIR)/gpio.c
 ramstage-y += variants/$(VARIANT_DIR)/hda_verb.c
 ramstage-y += ramstage.c
 ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += variants/$(VARIANT_DIR)/gma-mainboard.ads
+ramstage-$(CONFIG_DRIVERS_OPTION_CFR_ENABLED) += cfr.c
 
 CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/include
 
diff --git a/src/mainboard/purism/librem_cnl/cfr.c b/src/mainboard/purism/librem_cnl/cfr.c
new file mode 100644
index 0000000000..90184388f5
--- /dev/null
+++ b/src/mainboard/purism/librem_cnl/cfr.c
@@ -0,0 +1,46 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <boot/coreboot_tables.h>
+#include <drivers/option/cfr_frontend.h>
+#include <intelblocks/cfr.h>
+#include <soc/cfr.h>
+
+static struct sm_obj_form system = {
+	.ui_name = "System",
+	.obj_list = (const struct sm_object *[]) {
+		&hyper_threading,
+		&igd_dvmt,
+		&igd_aperture,
+		&legacy_8254_timer,
+		&pciexp_aspm,
+		&pciexp_clk_pm,
+		&pciexp_l1ss,
+		&pciexp_speed,
+		&s0ix_enable,
+		&vtd,
+		NULL
+	},
+};
+
+#if !CONFIG(BOARD_PURISM_LIBREM_14)
+static struct sm_obj_form power = {
+	.ui_name = "Power",
+	.obj_list = (const struct sm_object *[]) {
+		&power_on_after_fail,
+		NULL
+	},
+};
+#endif
+
+static struct sm_obj_form *sm_root[] = {
+	&system,
+#if !CONFIG(BOARD_PURISM_LIBREM_14)
+	&power,
+#endif
+	NULL
+};
+
+void mb_cfr_setup_menu(struct lb_cfr *cfr_root)
+{
+	cfr_write_setup_menu(cfr_root, sm_root);
+}

From e9a01dea32131fb1eec9a7727b1951f75cd17a57 Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Fri, 10 Oct 2025 13:53:23 -0500
Subject: [PATCH 2273/3886] mb/purism/librem_jsl: Add CFR option menu support

Add CFR option menu support when using edk2 payload and SMMSTORE.
Drop the Intel ME-related options since these boards ship with the
ME disabled via HAP.

Change-Id: I09be7910a62441df95b186c8554bc2fe3bf8c92f
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89533
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
---
 src/mainboard/purism/librem_jsl/Kconfig     |  1 +
 src/mainboard/purism/librem_jsl/Makefile.mk |  1 +
 src/mainboard/purism/librem_jsl/cfr.c       | 32 +++++++++++++++++++++
 3 files changed, 34 insertions(+)
 create mode 100644 src/mainboard/purism/librem_jsl/cfr.c

diff --git a/src/mainboard/purism/librem_jsl/Kconfig b/src/mainboard/purism/librem_jsl/Kconfig
index 2198dd60f8..d87a1580bf 100644
--- a/src/mainboard/purism/librem_jsl/Kconfig
+++ b/src/mainboard/purism/librem_jsl/Kconfig
@@ -4,6 +4,7 @@ config BOARD_PURISM_BASEBOARD_LIBREM_JSL
 	def_bool n
 	select BOARD_ROMSIZE_KB_16384
 	select DRIVERS_GENERIC_CBFS_SERIAL
+	select DRIVERS_OPTION_CFR_ENABLED if PAYLOAD_EDK2 && SMMSTORE
 	select DRIVERS_USB_ACPI
 	select DRIVERS_I2C_GENERIC
 	select DRIVERS_I2C_HID
diff --git a/src/mainboard/purism/librem_jsl/Makefile.mk b/src/mainboard/purism/librem_jsl/Makefile.mk
index 7fd4d59f90..65226dfb3d 100644
--- a/src/mainboard/purism/librem_jsl/Makefile.mk
+++ b/src/mainboard/purism/librem_jsl/Makefile.mk
@@ -3,4 +3,5 @@
 bootblock-y += bootblock.c
 ramstage-y += ramstage.c
 ramstage-y += hda_verb.c
+ramstage-$(CONFIG_DRIVERS_OPTION_CFR_ENABLED) += cfr.c
 SPD_SOURCES += isocon8gb
diff --git a/src/mainboard/purism/librem_jsl/cfr.c b/src/mainboard/purism/librem_jsl/cfr.c
new file mode 100644
index 0000000000..2fd5e3565d
--- /dev/null
+++ b/src/mainboard/purism/librem_jsl/cfr.c
@@ -0,0 +1,32 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <boot/coreboot_tables.h>
+#include <drivers/option/cfr_frontend.h>
+#include <intelblocks/cfr.h>
+#include <soc/cfr.h>
+
+static struct sm_obj_form system = {
+	.ui_name = "System",
+	.obj_list = (const struct sm_object *[]) {
+		&igd_dvmt,
+		&igd_aperture,
+		&legacy_8254_timer,
+		&pciexp_aspm,
+		&pciexp_clk_pm,
+		&pciexp_l1ss,
+		&pciexp_speed,
+		&s0ix_enable,
+		&vtd,
+		NULL
+	},
+};
+
+static struct sm_obj_form *sm_root[] = {
+	&system,
+	NULL
+};
+
+void mb_cfr_setup_menu(struct lb_cfr *cfr_root)
+{
+	cfr_write_setup_menu(cfr_root, sm_root);
+}

From 0d50fdf0352cd444baf0826628cf8b0e77f4c6cf Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Fri, 10 Oct 2025 13:53:55 -0500
Subject: [PATCH 2274/3886] mb/purism/librem_l1um_v2: Add CFR option menu
 support

Add CFR option menu support when using edk2 payload and SMMSTORE.
Drop the Intel ME-related options since these boards ship with the
ME disabled via HAP.

Change-Id: I203b46320660d326db0cb2733b998003fc12e905
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89534
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
---
 src/mainboard/purism/librem_l1um_v2/Kconfig   |  1 +
 .../purism/librem_l1um_v2/Makefile.mk         |  1 +
 src/mainboard/purism/librem_l1um_v2/cfr.c     | 42 +++++++++++++++++++
 3 files changed, 44 insertions(+)
 create mode 100644 src/mainboard/purism/librem_l1um_v2/cfr.c

diff --git a/src/mainboard/purism/librem_l1um_v2/Kconfig b/src/mainboard/purism/librem_l1um_v2/Kconfig
index 946e5a40bb..03d151f621 100644
--- a/src/mainboard/purism/librem_l1um_v2/Kconfig
+++ b/src/mainboard/purism/librem_l1um_v2/Kconfig
@@ -6,6 +6,7 @@ config BOARD_PURISM_BASEBOARD_LIBREM_L1UM_V2
 	select DRIVERS_ASPEED_AST2050
 	select DRIVERS_ASPEED_AST_COMMON
 	select DRIVERS_GENERIC_CBFS_SERIAL
+	select DRIVERS_OPTION_CFR_ENABLED if PAYLOAD_EDK2 && SMMSTORE
 	select DRIVERS_UART_8250IO
 	select DRIVERS_USB_ACPI
 	select GENERATE_SMBIOS_TABLES
diff --git a/src/mainboard/purism/librem_l1um_v2/Makefile.mk b/src/mainboard/purism/librem_l1um_v2/Makefile.mk
index 836733c867..991a9a5cdd 100644
--- a/src/mainboard/purism/librem_l1um_v2/Makefile.mk
+++ b/src/mainboard/purism/librem_l1um_v2/Makefile.mk
@@ -2,3 +2,4 @@
 
 bootblock-y += bootblock.c
 ramstage-y += ramstage.c
+ramstage-$(CONFIG_DRIVERS_OPTION_CFR_ENABLED) += cfr.c
diff --git a/src/mainboard/purism/librem_l1um_v2/cfr.c b/src/mainboard/purism/librem_l1um_v2/cfr.c
new file mode 100644
index 0000000000..d3dd4de3b7
--- /dev/null
+++ b/src/mainboard/purism/librem_l1um_v2/cfr.c
@@ -0,0 +1,42 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <boot/coreboot_tables.h>
+#include <drivers/option/cfr_frontend.h>
+#include <intelblocks/cfr.h>
+#include <soc/cfr.h>
+
+static struct sm_obj_form system = {
+	.ui_name = "System",
+	.obj_list = (const struct sm_object *[]) {
+		&hyper_threading,
+		&igd_dvmt,
+		&igd_aperture,
+		&legacy_8254_timer,
+		&pciexp_aspm,
+		&pciexp_clk_pm,
+		&pciexp_l1ss,
+		&pciexp_speed,
+		&s0ix_enable,
+		&vtd,
+		NULL
+	},
+};
+
+static struct sm_obj_form power = {
+	.ui_name = "Power",
+	.obj_list = (const struct sm_object *[]) {
+		&power_on_after_fail,
+		NULL
+	},
+};
+
+static struct sm_obj_form *sm_root[] = {
+	&system,
+	&power,
+	NULL
+};
+
+void mb_cfr_setup_menu(struct lb_cfr *cfr_root)
+{
+	cfr_write_setup_menu(cfr_root, sm_root);
+}

From dd3d7dcdfab9acbc021aa5439c5c838bddfa8997 Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Fri, 10 Oct 2025 13:54:46 -0500
Subject: [PATCH 2275/3886] mb/purism/librem_skl: Add CFR option menu support

Add CFR option menu support when using edk2 payload and SMMSTORE.
Drop the Intel ME-related options since these boards ship with the
ME disabled via HAP.

Change-Id: I9b1a272cababc6852b4c2f9c03cc417c1b1d12be
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89535
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/purism/librem_skl/Kconfig     |  1 +
 src/mainboard/purism/librem_skl/Makefile.mk |  1 +
 src/mainboard/purism/librem_skl/cfr.c       | 33 +++++++++++++++++++++
 3 files changed, 35 insertions(+)
 create mode 100644 src/mainboard/purism/librem_skl/cfr.c

diff --git a/src/mainboard/purism/librem_skl/Kconfig b/src/mainboard/purism/librem_skl/Kconfig
index 5f3ed06cd4..a4ef4f3ffe 100644
--- a/src/mainboard/purism/librem_skl/Kconfig
+++ b/src/mainboard/purism/librem_skl/Kconfig
@@ -4,6 +4,7 @@ config BOARD_PURISM_BASEBOARD_LIBREM_SKL
 	def_bool n
 	select BOARD_ROMSIZE_KB_16384
 	select DRIVERS_GENERIC_CBFS_SERIAL
+	select DRIVERS_OPTION_CFR_ENABLED if PAYLOAD_EDK2 && SMMSTORE
 	select GFX_GMA_IGNORE_PRESENCE_STRAPS
 	select HAVE_ACPI_RESUME
 	select HAVE_ACPI_TABLES
diff --git a/src/mainboard/purism/librem_skl/Makefile.mk b/src/mainboard/purism/librem_skl/Makefile.mk
index 5983578bb6..0163e52c0b 100644
--- a/src/mainboard/purism/librem_skl/Makefile.mk
+++ b/src/mainboard/purism/librem_skl/Makefile.mk
@@ -4,3 +4,4 @@ ramstage-y += ramstage.c
 ramstage-y += hda_verb.c
 
 ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads
+ramstage-$(CONFIG_DRIVERS_OPTION_CFR_ENABLED) += cfr.c
diff --git a/src/mainboard/purism/librem_skl/cfr.c b/src/mainboard/purism/librem_skl/cfr.c
new file mode 100644
index 0000000000..2ddc7402c8
--- /dev/null
+++ b/src/mainboard/purism/librem_skl/cfr.c
@@ -0,0 +1,33 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <boot/coreboot_tables.h>
+#include <drivers/option/cfr_frontend.h>
+#include <intelblocks/cfr.h>
+#include <soc/cfr.h>
+
+static struct sm_obj_form system = {
+	.ui_name = "System",
+	.obj_list = (const struct sm_object *[]) {
+		&hyper_threading,
+		&igd_dvmt,
+		&igd_aperture,
+		&legacy_8254_timer,
+		&pciexp_aspm,
+		&pciexp_clk_pm,
+		&pciexp_l1ss,
+		&pciexp_speed,
+		&s0ix_enable,
+		&vtd,
+		NULL
+	},
+};
+
+static struct sm_obj_form *sm_root[] = {
+	&system,
+	NULL
+};
+
+void mb_cfr_setup_menu(struct lb_cfr *cfr_root)
+{
+	cfr_write_setup_menu(cfr_root, sm_root);
+}

From e7dd184e5f0949e042e2ae56787c0495ac85df48 Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Sun, 12 Oct 2025 20:18:09 +0100
Subject: [PATCH 2276/3886] Makefile.mk: Add support for mainboard vendor
 common code

Allow mainboard vendors to have common code, controlled by a new
Kconfig option MB_COMMON_CODE.

Change-Id: I5b97b26a70fbbe2e3f659f01aa00b16b76167f88
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89531
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 Makefile.mk | 6 +++++-
 1 file changed, 5 insertions(+), 1 deletion(-)

diff --git a/Makefile.mk b/Makefile.mk
index 1c5b8f05d5..e28e4f800d 100644
--- a/Makefile.mk
+++ b/Makefile.mk
@@ -35,8 +35,9 @@ COREBOOT_EXPORTS += KERNELVERSION
 # Basic component discovery
 MAINBOARDDIR=$(call strip_quotes,$(CONFIG_MAINBOARD_DIR))
 VARIANT_DIR:=$(call strip_quotes,$(CONFIG_VARIANT_DIR))
+MB_COMMON_DIR := $(call strip_quotes,$(CONFIG_MB_COMMON_DIR))
 CARRIER_DIR:=$(call strip_quotes,$(CONFIG_CARRIER_DIR))
-COREBOOT_EXPORTS += MAINBOARDDIR VARIANT_DIR CARRIER_DIR
+COREBOOT_EXPORTS += MAINBOARDDIR VARIANT_DIR MB_COMMON_DIR CARRIER_DIR
 
 ## Final build results, which CBFSTOOL uses to create the final
 ## rom image file, are placed under $(objcbfs).
@@ -119,6 +120,9 @@ subdirs-y += util/futility util/marvell util/bincfg util/supermicro util/qemu
 subdirs-y += util/ifdtool
 subdirs-y += $(wildcard src/arch/*)
 subdirs-y += src/mainboard/$(MAINBOARDDIR)
+ifneq ($(MB_COMMON_DIR),)
+subdirs-y += src/mainboard/$(MB_COMMON_DIR)
+endif
 subdirs-y += src/security
 subdirs-y += payloads payloads/external
 subdirs-$(CONFIG_SBOM) += src/sbom

From 7622a57771e6222ce3bb75a38e886fd41376a2cf Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Mon, 25 Aug 2025 20:51:41 +0100
Subject: [PATCH 2277/3886] mb/starlabs/common: Move the SMBIOS code to common
 directory

This avoids storing the same files in 5 different places in the tree.

Change-Id: I84bd5705613947444f48331d1a2d06b1ab71b2f3
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88943
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
---
 src/mainboard/starlabs/byte_adl/Makefile.mk   |  1 -
 src/mainboard/starlabs/common/Kconfig         | 13 +++++++
 src/mainboard/starlabs/common/Makefile.mk     |  3 ++
 .../starlabs/common/smbios/Makefile.mk        |  3 ++
 .../{byte_adl => common/smbios}/smbios.c      |  2 +-
 src/mainboard/starlabs/lite/Makefile.mk       |  1 -
 src/mainboard/starlabs/lite/smbios.c          | 38 ------------------
 src/mainboard/starlabs/starbook/Makefile.mk   |  1 -
 src/mainboard/starlabs/starbook/smbios.c      | 39 -------------------
 .../starlabs/starfighter/Makefile.mk          |  1 -
 src/mainboard/starlabs/starfighter/smbios.c   | 39 -------------------
 .../starlabs/starlite_adl/Makefile.mk         |  1 -
 src/mainboard/starlabs/starlite_adl/smbios.c  | 39 -------------------
 13 files changed, 20 insertions(+), 161 deletions(-)
 create mode 100644 src/mainboard/starlabs/common/Kconfig
 create mode 100644 src/mainboard/starlabs/common/Makefile.mk
 create mode 100644 src/mainboard/starlabs/common/smbios/Makefile.mk
 rename src/mainboard/starlabs/{byte_adl => common/smbios}/smbios.c (97%)
 delete mode 100644 src/mainboard/starlabs/lite/smbios.c
 delete mode 100644 src/mainboard/starlabs/starbook/smbios.c
 delete mode 100644 src/mainboard/starlabs/starfighter/smbios.c
 delete mode 100644 src/mainboard/starlabs/starlite_adl/smbios.c

diff --git a/src/mainboard/starlabs/byte_adl/Makefile.mk b/src/mainboard/starlabs/byte_adl/Makefile.mk
index 677db61b19..678662b55d 100644
--- a/src/mainboard/starlabs/byte_adl/Makefile.mk
+++ b/src/mainboard/starlabs/byte_adl/Makefile.mk
@@ -11,4 +11,3 @@ romstage-$(CONFIG_VBOOT) += vboot.c
 
 ramstage-$(CONFIG_DRIVERS_OPTION_CFR) += cfr.c
 ramstage-y += mainboard.c
-ramstage-y += smbios.c
diff --git a/src/mainboard/starlabs/common/Kconfig b/src/mainboard/starlabs/common/Kconfig
new file mode 100644
index 0000000000..4670672cb7
--- /dev/null
+++ b/src/mainboard/starlabs/common/Kconfig
@@ -0,0 +1,13 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
+if VENDOR_STARLABS
+
+menu "Star Labs Settings"
+
+config MB_COMMON_DIR
+	string
+	default "starlabs/common"
+
+endmenu
+
+endif
diff --git a/src/mainboard/starlabs/common/Makefile.mk b/src/mainboard/starlabs/common/Makefile.mk
new file mode 100644
index 0000000000..3979986e57
--- /dev/null
+++ b/src/mainboard/starlabs/common/Makefile.mk
@@ -0,0 +1,3 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
+subdirs-$(CONFIG_VENDOR_STARLABS) += smbios
diff --git a/src/mainboard/starlabs/common/smbios/Makefile.mk b/src/mainboard/starlabs/common/smbios/Makefile.mk
new file mode 100644
index 0000000000..ae6163b99a
--- /dev/null
+++ b/src/mainboard/starlabs/common/smbios/Makefile.mk
@@ -0,0 +1,3 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
+ramstage-y += smbios.c
diff --git a/src/mainboard/starlabs/byte_adl/smbios.c b/src/mainboard/starlabs/common/smbios/smbios.c
similarity index 97%
rename from src/mainboard/starlabs/byte_adl/smbios.c
rename to src/mainboard/starlabs/common/smbios/smbios.c
index ab2c211a99..00e6f249c7 100644
--- a/src/mainboard/starlabs/byte_adl/smbios.c
+++ b/src/mainboard/starlabs/common/smbios/smbios.c
@@ -1,6 +1,6 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
-#include <chip.h>
+#include <soc/soc_chip.h>
 #include <device/device.h>
 #include <device/pci_def.h>
 #include <ec/starlabs/merlin/ec.h>
diff --git a/src/mainboard/starlabs/lite/Makefile.mk b/src/mainboard/starlabs/lite/Makefile.mk
index 65a5241f39..acf62c2753 100644
--- a/src/mainboard/starlabs/lite/Makefile.mk
+++ b/src/mainboard/starlabs/lite/Makefile.mk
@@ -12,5 +12,4 @@ romstage-$(CONFIG_VBOOT) += vboot.c
 ramstage-$(CONFIG_DRIVERS_OPTION_CFR) += cfr.c
 ramstage-y += devtree.c
 ramstage-y += mainboard.c
-ramstage-y += smbios.c
 ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads
diff --git a/src/mainboard/starlabs/lite/smbios.c b/src/mainboard/starlabs/lite/smbios.c
deleted file mode 100644
index 5b85f501fd..0000000000
--- a/src/mainboard/starlabs/lite/smbios.c
+++ /dev/null
@@ -1,38 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <device/device.h>
-#include <device/pci_def.h>
-#include <ec/starlabs/merlin/ec.h>
-#include <smbios.h>
-#include <types.h>
-#include <uuid.h>
-#include <variants.h>
-
-/* Get the Embedded Controller firmware version */
-void smbios_ec_revision(uint8_t *ec_major_revision, uint8_t *ec_minor_revision)
-{
-	u16 ec_version = ec_get_version();
-
-	*ec_major_revision = ec_version >> 8;
-	*ec_minor_revision = ec_version & 0xff;
-}
-
-const char *smbios_system_sku(void)
-{
-	return CONFIG_MAINBOARD_FAMILY;
-}
-
-u8 smbios_mainboard_feature_flags(void)
-{
-	return SMBIOS_FEATURE_FLAGS_HOSTING_BOARD | SMBIOS_FEATURE_FLAGS_REPLACEABLE;
-}
-
-const char *smbios_chassis_version(void)
-{
-	return smbios_mainboard_version();
-}
-
-const char *smbios_chassis_serial_number(void)
-{
-	return smbios_mainboard_serial_number();
-}
diff --git a/src/mainboard/starlabs/starbook/Makefile.mk b/src/mainboard/starlabs/starbook/Makefile.mk
index 581c8613f6..1a8996f1b2 100644
--- a/src/mainboard/starlabs/starbook/Makefile.mk
+++ b/src/mainboard/starlabs/starbook/Makefile.mk
@@ -13,5 +13,4 @@ romstage-$(CONFIG_VBOOT) += vboot.c
 ramstage-$(CONFIG_DRIVERS_OPTION_CFR) += cfr.c
 ramstage-y += hda_verb.c
 ramstage-y += mainboard.c
-ramstage-y += smbios.c
 ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += variants/$(VARIANT_DIR)/gma-mainboard.ads
diff --git a/src/mainboard/starlabs/starbook/smbios.c b/src/mainboard/starlabs/starbook/smbios.c
deleted file mode 100644
index ab2c211a99..0000000000
--- a/src/mainboard/starlabs/starbook/smbios.c
+++ /dev/null
@@ -1,39 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <chip.h>
-#include <device/device.h>
-#include <device/pci_def.h>
-#include <ec/starlabs/merlin/ec.h>
-#include <smbios.h>
-#include <types.h>
-#include <uuid.h>
-#include <variants.h>
-
-/* Get the Embedded Controller firmware version */
-void smbios_ec_revision(uint8_t *ec_major_revision, uint8_t *ec_minor_revision)
-{
-	u16 ec_version = ec_get_version();
-
-	*ec_major_revision = ec_version >> 8;
-	*ec_minor_revision = ec_version & 0xff;
-}
-
-const char *smbios_system_sku(void)
-{
-	return CONFIG_MAINBOARD_FAMILY;
-}
-
-u8 smbios_mainboard_feature_flags(void)
-{
-	return SMBIOS_FEATURE_FLAGS_HOSTING_BOARD | SMBIOS_FEATURE_FLAGS_REPLACEABLE;
-}
-
-const char *smbios_chassis_version(void)
-{
-	return smbios_mainboard_version();
-}
-
-const char *smbios_chassis_serial_number(void)
-{
-	return smbios_mainboard_serial_number();
-}
diff --git a/src/mainboard/starlabs/starfighter/Makefile.mk b/src/mainboard/starlabs/starfighter/Makefile.mk
index f35c14f0b3..59e8f76e8f 100644
--- a/src/mainboard/starlabs/starfighter/Makefile.mk
+++ b/src/mainboard/starlabs/starfighter/Makefile.mk
@@ -9,5 +9,4 @@ bootblock-y += bootblock.c
 ramstage-$(CONFIG_DRIVERS_OPTION_CFR) += cfr.c
 ramstage-y += hda_verb.c
 ramstage-y += mainboard.c
-ramstage-y += smbios.c
 ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += variants/$(VARIANT_DIR)/gma-mainboard.ads
diff --git a/src/mainboard/starlabs/starfighter/smbios.c b/src/mainboard/starlabs/starfighter/smbios.c
deleted file mode 100644
index ab2c211a99..0000000000
--- a/src/mainboard/starlabs/starfighter/smbios.c
+++ /dev/null
@@ -1,39 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <chip.h>
-#include <device/device.h>
-#include <device/pci_def.h>
-#include <ec/starlabs/merlin/ec.h>
-#include <smbios.h>
-#include <types.h>
-#include <uuid.h>
-#include <variants.h>
-
-/* Get the Embedded Controller firmware version */
-void smbios_ec_revision(uint8_t *ec_major_revision, uint8_t *ec_minor_revision)
-{
-	u16 ec_version = ec_get_version();
-
-	*ec_major_revision = ec_version >> 8;
-	*ec_minor_revision = ec_version & 0xff;
-}
-
-const char *smbios_system_sku(void)
-{
-	return CONFIG_MAINBOARD_FAMILY;
-}
-
-u8 smbios_mainboard_feature_flags(void)
-{
-	return SMBIOS_FEATURE_FLAGS_HOSTING_BOARD | SMBIOS_FEATURE_FLAGS_REPLACEABLE;
-}
-
-const char *smbios_chassis_version(void)
-{
-	return smbios_mainboard_version();
-}
-
-const char *smbios_chassis_serial_number(void)
-{
-	return smbios_mainboard_serial_number();
-}
diff --git a/src/mainboard/starlabs/starlite_adl/Makefile.mk b/src/mainboard/starlabs/starlite_adl/Makefile.mk
index aab03f5d03..17c1dc2f4d 100644
--- a/src/mainboard/starlabs/starlite_adl/Makefile.mk
+++ b/src/mainboard/starlabs/starlite_adl/Makefile.mk
@@ -13,4 +13,3 @@ romstage-$(CONFIG_VBOOT) += vboot.c
 ramstage-$(CONFIG_DRIVERS_OPTION_CFR) += cfr.c
 ramstage-y += hda_verb.c
 ramstage-y += mainboard.c
-ramstage-y += smbios.c
diff --git a/src/mainboard/starlabs/starlite_adl/smbios.c b/src/mainboard/starlabs/starlite_adl/smbios.c
deleted file mode 100644
index ab2c211a99..0000000000
--- a/src/mainboard/starlabs/starlite_adl/smbios.c
+++ /dev/null
@@ -1,39 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <chip.h>
-#include <device/device.h>
-#include <device/pci_def.h>
-#include <ec/starlabs/merlin/ec.h>
-#include <smbios.h>
-#include <types.h>
-#include <uuid.h>
-#include <variants.h>
-
-/* Get the Embedded Controller firmware version */
-void smbios_ec_revision(uint8_t *ec_major_revision, uint8_t *ec_minor_revision)
-{
-	u16 ec_version = ec_get_version();
-
-	*ec_major_revision = ec_version >> 8;
-	*ec_minor_revision = ec_version & 0xff;
-}
-
-const char *smbios_system_sku(void)
-{
-	return CONFIG_MAINBOARD_FAMILY;
-}
-
-u8 smbios_mainboard_feature_flags(void)
-{
-	return SMBIOS_FEATURE_FLAGS_HOSTING_BOARD | SMBIOS_FEATURE_FLAGS_REPLACEABLE;
-}
-
-const char *smbios_chassis_version(void)
-{
-	return smbios_mainboard_version();
-}
-
-const char *smbios_chassis_serial_number(void)
-{
-	return smbios_mainboard_serial_number();
-}

From 163e6a502c849529a5e3d11f605fbfc1d6a7f495 Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Sat, 11 Oct 2025 20:18:41 +0100
Subject: [PATCH 2278/3886] mb/starlabs/common: Deduplicate Pin Mix

Rather than boards configuring a handful, have common code
configure all relevant ones for the SOC.

Change-Id: I06f202378dd26d99a4fb17f6195dd3fb4df61430
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89525
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 .../byte_adl/variants/mk_ii/ramstage.c        |  9 +----
 src/mainboard/starlabs/common/Makefile.mk     |  1 +
 .../starlabs/common/pin_mux/Makefile.mk       |  7 ++++
 .../starlabs/common/pin_mux/alderlake.c       | 24 ++++++++++++
 .../starlabs/common/pin_mux/meteorlake.c      | 39 +++++++++++++++++++
 .../starlabs/common/pin_mux/pin_mux.h         |  8 ++++
 .../starlabs/common/pin_mux/tigerlake.c       | 16 ++++++++
 .../starlabs/starbook/variants/adl/ramstage.c |  9 +----
 .../starbook/variants/adl_n/ramstage.c        |  8 +---
 .../starlabs/starbook/variants/mtl/ramstage.c |  8 +---
 .../starlabs/starbook/variants/rpl/ramstage.c |  8 +---
 .../starbook/variants/tgl/Makefile.mk         |  1 +
 .../starlabs/starbook/variants/tgl/ramstage.c |  9 +++++
 .../starfighter/variants/rpl/ramstage.c       |  8 +---
 .../starlite_adl/variants/mk_v/ramstage.c     | 10 +----
 15 files changed, 119 insertions(+), 46 deletions(-)
 create mode 100644 src/mainboard/starlabs/common/pin_mux/Makefile.mk
 create mode 100644 src/mainboard/starlabs/common/pin_mux/alderlake.c
 create mode 100644 src/mainboard/starlabs/common/pin_mux/meteorlake.c
 create mode 100644 src/mainboard/starlabs/common/pin_mux/pin_mux.h
 create mode 100644 src/mainboard/starlabs/common/pin_mux/tigerlake.c
 create mode 100644 src/mainboard/starlabs/starbook/variants/tgl/ramstage.c

diff --git a/src/mainboard/starlabs/byte_adl/variants/mk_ii/ramstage.c b/src/mainboard/starlabs/byte_adl/variants/mk_ii/ramstage.c
index 80f186ed03..e70ba50498 100644
--- a/src/mainboard/starlabs/byte_adl/variants/mk_ii/ramstage.c
+++ b/src/mainboard/starlabs/byte_adl/variants/mk_ii/ramstage.c
@@ -1,14 +1,9 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
 #include <soc/ramstage.h>
+#include "pin_mux.h"
 
 void mainboard_silicon_init_params(FSP_S_CONFIG *supd)
 {
-	/*
-	 * FSP defaults to pins that are used for LPC; given that
-	 * coreboot only supports eSPI, set these pins accordingly.
-	 */
-	supd->CnviRfResetPinMux			= 0x194ce404;	// GPP_F4
-	supd->CnviClkreqPinMux			= 0x294ce605;	// GPP_F5
-	supd->SataPortDevSlpPinMux[1]		= 0x5967400d;	// GPP_H13
+	configure_pin_mux(supd);
 }
diff --git a/src/mainboard/starlabs/common/Makefile.mk b/src/mainboard/starlabs/common/Makefile.mk
index 3979986e57..3329eb0554 100644
--- a/src/mainboard/starlabs/common/Makefile.mk
+++ b/src/mainboard/starlabs/common/Makefile.mk
@@ -1,3 +1,4 @@
 # SPDX-License-Identifier: GPL-2.0-only
 
 subdirs-$(CONFIG_VENDOR_STARLABS) += smbios
+subdirs-$(CONFIG_VENDOR_STARLABS) += pin_mux
diff --git a/src/mainboard/starlabs/common/pin_mux/Makefile.mk b/src/mainboard/starlabs/common/pin_mux/Makefile.mk
new file mode 100644
index 0000000000..2249df0b3c
--- /dev/null
+++ b/src/mainboard/starlabs/common/pin_mux/Makefile.mk
@@ -0,0 +1,7 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
+ramstage-$(CONFIG_SOC_INTEL_TIGERLAKE) += tigerlake.c
+ramstage-$(CONFIG_SOC_INTEL_ALDERLAKE) += alderlake.c
+ramstage-$(CONFIG_SOC_INTEL_METEORLAKE) += meteorlake.c
+
+CPPFLAGS_common += -I$(src)/mainboard/starlabs/common/pin_mux
diff --git a/src/mainboard/starlabs/common/pin_mux/alderlake.c b/src/mainboard/starlabs/common/pin_mux/alderlake.c
new file mode 100644
index 0000000000..1869b631e0
--- /dev/null
+++ b/src/mainboard/starlabs/common/pin_mux/alderlake.c
@@ -0,0 +1,24 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <fsp/api.h>
+#include "pin_mux.h"
+
+void configure_pin_mux(FSP_S_CONFIG *supd)
+{
+	supd->SataPortDevSlpPinMux[0] = 0x59673e0c;
+	supd->SataPortDevSlpPinMux[1] = 0x5967400d;
+	supd->PchSerialIoI2cSdaPinMux[0] = 0x1947c404;
+	supd->PchSerialIoI2cSdaPinMux[1] = 0x1947c606;
+	supd->PchSerialIoI2cSdaPinMux[4] = 0;
+	supd->PchSerialIoI2cSdaPinMux[7] = 0x1947d20c;
+	supd->PchSerialIoI2cSclPinMux[0] = 0x1947a405;
+	supd->PchSerialIoI2cSclPinMux[1] = 0x1947a607;
+	supd->PchSerialIoI2cSclPinMux[4] = 0;
+	supd->PchSerialIoI2cSclPinMux[7] = 0x1947b20d;
+	supd->IshGpGpioPinMuxing[4] = 0x290ea809;
+	supd->IshGpGpioPinMuxing[5] = 0x4900aa04;
+	supd->IshGpGpioPinMuxing[6] = 0x4907ac0c;
+	supd->IshGpGpioPinMuxing[7] = 0x5900ae0f;
+	supd->CnviRfResetPinMux = 0x194ce404;
+	supd->CnviClkreqPinMux = 0x294ce605;
+}
diff --git a/src/mainboard/starlabs/common/pin_mux/meteorlake.c b/src/mainboard/starlabs/common/pin_mux/meteorlake.c
new file mode 100644
index 0000000000..37d1f4aa1a
--- /dev/null
+++ b/src/mainboard/starlabs/common/pin_mux/meteorlake.c
@@ -0,0 +1,39 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <fsp/api.h>
+#include "pin_mux.h"
+
+void configure_pin_mux(FSP_S_CONFIG *supd)
+{
+	supd->IshUartRxPinMuxing[1] = 0x146806;
+	supd->IshUartTxPinMuxing[1] = 0x146807;
+	supd->IshI2cSdaPinMuxing[2] = 0x143012;
+	supd->IshI2cSclPinMuxing[2] = 0x143013;
+	supd->IshSpiMosiPinMuxing[0] = 0x147088;
+	supd->IshSpiMisoPinMuxing[0] = 0x147087;
+	supd->IshSpiClkPinMuxing[0] = 0x147086;
+	supd->IshSpiCsPinMuxing[0] = 0x147085;
+	supd->SerialIoUartRxPinMuxPolicy[1] = 0x144806;
+	supd->SerialIoUartTxPinMuxPolicy[1] = 0x144807;
+	supd->PchSerialIoI2cSdaPinMux[2] = 0x142804;
+	supd->PchSerialIoI2cSdaPinMux[3] = 0x142806;
+	supd->PchSerialIoI2cSdaPinMux[4] = 0x15048c;
+	supd->PchSerialIoI2cSdaPinMux[5] = 0x15088d;
+	supd->PchSerialIoI2cSclPinMux[2] = 0x142805;
+	supd->PchSerialIoI2cSclPinMux[3] = 0x142807;
+	supd->PchSerialIoI2cSclPinMux[4] = 0x15048d;
+	supd->PchSerialIoI2cSclPinMux[5] = 0x15088c;
+	supd->SerialIoI3cSdaPinMux[1] = 0x144815;
+	supd->SerialIoI3cSclPinMux[1] = 0x144816;
+	supd->SerialIoI3cSclFbPinMux[1] = 0x144818;
+	supd->IshGpGpioPinMuxing[5] = 0x149016;
+	supd->IshGpGpioPinMuxing[6] = 0x149017;
+	supd->IshGpGpioPinMuxing[8] = 0x149014;
+	supd->IshGpGpioPinMuxing[9] = 0x150897;
+	supd->IshGpGpioPinMuxing[10] = 0x150490;
+	supd->IshGpGpioPinMuxing[11] = 0x150889;
+	supd->SerialIoSpiCsPinMux[0] = 0x14a48a;
+	supd->SerialIoSpiClkPinMux[0] = 0x14a48b;
+	supd->SerialIoSpiMisoPinMux[0] = 0x14a48c;
+	supd->SerialIoSpiMosiPinMux[0] = 0x14a48d;
+}
diff --git a/src/mainboard/starlabs/common/pin_mux/pin_mux.h b/src/mainboard/starlabs/common/pin_mux/pin_mux.h
new file mode 100644
index 0000000000..38c77f4032
--- /dev/null
+++ b/src/mainboard/starlabs/common/pin_mux/pin_mux.h
@@ -0,0 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef PIN_MUX
+#define PIN_MUX
+
+void configure_pin_mux(FSP_S_CONFIG *supd);
+
+#endif
diff --git a/src/mainboard/starlabs/common/pin_mux/tigerlake.c b/src/mainboard/starlabs/common/pin_mux/tigerlake.c
new file mode 100644
index 0000000000..34c1a05b90
--- /dev/null
+++ b/src/mainboard/starlabs/common/pin_mux/tigerlake.c
@@ -0,0 +1,16 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <fsp/api.h>
+#include "pin_mux.h"
+
+void configure_pin_mux(FSP_S_CONFIG *supd)
+{
+	supd->SerialIoUartRxPinMuxPolicy[0] = 0x190B0208;
+	supd->SerialIoUartTxPinMuxPolicy[0] = 0x190B1209;
+	supd->SerialIoUartRtsPinMuxPolicy[0] = 0x190B220a;
+	supd->SerialIoUartCtsPinMuxPolicy[0] = 0x190B320b;
+	supd->SerialIoUartRxPinMuxPolicy[0] = 0x18050208;
+	supd->SerialIoUartTxPinMuxPolicy[0] = 0x18051209;
+	supd->SerialIoUartRtsPinMuxPolicy[0] = 0x1805220c;
+	supd->SerialIoUartCtsPinMuxPolicy[0] = 0x1805320b;
+}
diff --git a/src/mainboard/starlabs/starbook/variants/adl/ramstage.c b/src/mainboard/starlabs/starbook/variants/adl/ramstage.c
index 9e678def77..e6828e23ca 100644
--- a/src/mainboard/starlabs/starbook/variants/adl/ramstage.c
+++ b/src/mainboard/starlabs/starbook/variants/adl/ramstage.c
@@ -2,16 +2,11 @@
 
 #include <option.h>
 #include <soc/ramstage.h>
+#include "pin_mux.h"
 
 void mainboard_silicon_init_params(FSP_S_CONFIG *supd)
 {
-	/*
-	 * FSP defaults to pins that are used for LPC; given that
-	 * coreboot only supports eSPI, set these pins accordingly.
-	 */
-	supd->PchSerialIoI2cSdaPinMux[0]	= 0x1947c404;	// GPP_H4
-	supd->PchSerialIoI2cSclPinMux[0]	= 0x1947a405;	// GPP_H5
-	supd->SataPortDevSlpPinMux[1]		= 0x5967400d;	// GPP_H13
+	configure_pin_mux(supd);
 
 	/*
 	 * Enable Hot Plug on RP5 to slow down coreboot so that
diff --git a/src/mainboard/starlabs/starbook/variants/adl_n/ramstage.c b/src/mainboard/starlabs/starbook/variants/adl_n/ramstage.c
index 76bbbaeca8..e70ba50498 100644
--- a/src/mainboard/starlabs/starbook/variants/adl_n/ramstage.c
+++ b/src/mainboard/starlabs/starbook/variants/adl_n/ramstage.c
@@ -1,13 +1,9 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
 #include <soc/ramstage.h>
+#include "pin_mux.h"
 
 void mainboard_silicon_init_params(FSP_S_CONFIG *supd)
 {
-	/*
-	 * FSP defaults to pins that are used for LPC; given that
-	 * coreboot only supports eSPI, set these pins accordingly.
-	 */
-	supd->PchSerialIoI2cSdaPinMux[0]	= 0x1947c404;	// GPP_H4
-	supd->PchSerialIoI2cSclPinMux[0]	= 0x1947a405;	// GPP_H5
+	configure_pin_mux(supd);
 }
diff --git a/src/mainboard/starlabs/starbook/variants/mtl/ramstage.c b/src/mainboard/starlabs/starbook/variants/mtl/ramstage.c
index e602932bfe..423716531a 100644
--- a/src/mainboard/starlabs/starbook/variants/mtl/ramstage.c
+++ b/src/mainboard/starlabs/starbook/variants/mtl/ramstage.c
@@ -1,14 +1,10 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
-#include <option.h>
 #include <soc/ramstage.h>
+#include "pin_mux.h"
 
 void mainboard_silicon_init_params(FSP_S_CONFIG *supd)
 {
+	configure_pin_mux(supd);
 	supd->TcNotifyIgd = 2; // Auto
-	/* eSPI GPIOs */
-	supd->SerialIoSpiCsPinMux[0] = 0x14a48a;
-	supd->SerialIoSpiClkPinMux[0] = 0x14a48b;
-	supd->SerialIoSpiMisoPinMux[0] = 0x14a48c;
-	supd->SerialIoSpiMosiPinMux[0] = 0x14a48d;
 }
diff --git a/src/mainboard/starlabs/starbook/variants/rpl/ramstage.c b/src/mainboard/starlabs/starbook/variants/rpl/ramstage.c
index f62c0698f0..e30afaa5ca 100644
--- a/src/mainboard/starlabs/starbook/variants/rpl/ramstage.c
+++ b/src/mainboard/starlabs/starbook/variants/rpl/ramstage.c
@@ -2,15 +2,11 @@
 
 #include <option.h>
 #include <soc/ramstage.h>
+#include "pin_mux.h"
 
 void mainboard_silicon_init_params(FSP_S_CONFIG *supd)
 {
-	/*
-	 * FSP defaults to pins that are used for LPC; given that
-	 * coreboot only supports eSPI, set these pins accordingly.
-	 */
-	supd->PchSerialIoI2cSdaPinMux[0]	= 0x1947c404;	// GPP_H4
-	supd->PchSerialIoI2cSclPinMux[0]	= 0x1947a405;	// GPP_H5
+	configure_pin_mux(supd);
 
 	if (get_uint_option("thunderbolt", 1) == 0)
 		supd->UsbTcPortEn = 0;
diff --git a/src/mainboard/starlabs/starbook/variants/tgl/Makefile.mk b/src/mainboard/starlabs/starbook/variants/tgl/Makefile.mk
index 2a505c35c7..9abc069b38 100644
--- a/src/mainboard/starlabs/starbook/variants/tgl/Makefile.mk
+++ b/src/mainboard/starlabs/starbook/variants/tgl/Makefile.mk
@@ -7,3 +7,4 @@ romstage-y += romstage.c
 ramstage-y += devtree.c
 ramstage-y += gpio.c
 ramstage-y += hda_verb.c
+ramstage-y += ramstage.c
diff --git a/src/mainboard/starlabs/starbook/variants/tgl/ramstage.c b/src/mainboard/starlabs/starbook/variants/tgl/ramstage.c
new file mode 100644
index 0000000000..e70ba50498
--- /dev/null
+++ b/src/mainboard/starlabs/starbook/variants/tgl/ramstage.c
@@ -0,0 +1,9 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <soc/ramstage.h>
+#include "pin_mux.h"
+
+void mainboard_silicon_init_params(FSP_S_CONFIG *supd)
+{
+	configure_pin_mux(supd);
+}
diff --git a/src/mainboard/starlabs/starfighter/variants/rpl/ramstage.c b/src/mainboard/starlabs/starfighter/variants/rpl/ramstage.c
index f62c0698f0..e30afaa5ca 100644
--- a/src/mainboard/starlabs/starfighter/variants/rpl/ramstage.c
+++ b/src/mainboard/starlabs/starfighter/variants/rpl/ramstage.c
@@ -2,15 +2,11 @@
 
 #include <option.h>
 #include <soc/ramstage.h>
+#include "pin_mux.h"
 
 void mainboard_silicon_init_params(FSP_S_CONFIG *supd)
 {
-	/*
-	 * FSP defaults to pins that are used for LPC; given that
-	 * coreboot only supports eSPI, set these pins accordingly.
-	 */
-	supd->PchSerialIoI2cSdaPinMux[0]	= 0x1947c404;	// GPP_H4
-	supd->PchSerialIoI2cSclPinMux[0]	= 0x1947a405;	// GPP_H5
+	configure_pin_mux(supd);
 
 	if (get_uint_option("thunderbolt", 1) == 0)
 		supd->UsbTcPortEn = 0;
diff --git a/src/mainboard/starlabs/starlite_adl/variants/mk_v/ramstage.c b/src/mainboard/starlabs/starlite_adl/variants/mk_v/ramstage.c
index 140101fb14..211384c1ef 100644
--- a/src/mainboard/starlabs/starlite_adl/variants/mk_v/ramstage.c
+++ b/src/mainboard/starlabs/starlite_adl/variants/mk_v/ramstage.c
@@ -3,17 +3,11 @@
 #include <drivers/intel/gma/opregion.h>
 #include <soc/ramstage.h>
 #include <option.h>
+#include "pin_mux.h"
 
 void mainboard_silicon_init_params(FSP_S_CONFIG *supd)
 {
-	/*
-	 * FSP defaults to pins that are used for LPC; given that
-	 * coreboot only supports eSPI, set these pins accordingly.
-	 */
-	supd->CnviRfResetPinMux			= 0x194ce404;	// GPP_F4
-	supd->CnviClkreqPinMux			= 0x294ce605;	// GPP_F5
-	supd->PchSerialIoI2cSdaPinMux[0]	= 0x1947c404;	// GPP_H4
-	supd->PchSerialIoI2cSclPinMux[0]	= 0x1947a405;	// GPP_H5
+	configure_pin_mux(supd);
 }
 
 const char *mainboard_vbt_filename(void)

From 10b0697dc3b4330b0d481e01a89fe825ba780f51 Mon Sep 17 00:00:00 2001
From: Shaik Sameeruddin <shaik.sameeruddin@intel.com>
Date: Tue, 23 Sep 2025 14:24:01 -0700
Subject: [PATCH 2279/3886] soc/intel/pantherlake: Update power limits and
 voltage regulator parameters

This commit updates the power limit and voltage regulator parameters for
the Panther Lake SoC to align with the recommendations from the Power
Map 2.0 document (#813278). The update addresses discrepancies between
the previous configuration and the optimal settings specified in the
Power Map 2.0 document, ensuring better performance and efficiency.

TEST=Power and Performance team verified that Fatcat devices meet
     requirements with these settings.

Change-Id: I2e11855c4f0533d826a25efead02ddcff9ab1f61
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Signed-off-by: Shaik Sameeruddin <shaik.sameeruddin@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89318
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
---
 src/soc/intel/pantherlake/chip.h         | 11 ++--
 src/soc/intel/pantherlake/chipset_ptl.cb | 77 ++++++++++++++++++++----
 2 files changed, 71 insertions(+), 17 deletions(-)

diff --git a/src/soc/intel/pantherlake/chip.h b/src/soc/intel/pantherlake/chip.h
index bfd307553b..b1bd1a50a7 100644
--- a/src/soc/intel/pantherlake/chip.h
+++ b/src/soc/intel/pantherlake/chip.h
@@ -75,6 +75,7 @@ enum soc_intel_pantherlake_sku {
 	PTL_SKU_3,
 	PTL_SKU_4,
 	PTL_SKU_5,
+	PTL_SKU_6,
 	WCL_SKU_1,
 	WCL_SKU_2,
 	WCL_SKU_3,
@@ -94,16 +95,16 @@ static const struct soc_intel_pantherlake_power_map {
 	{ PCI_DID_INTEL_PTL_U_ID_1, PTL_CORE_1, TDP_25W, PTL_SKU_1 },
 	{ PCI_DID_INTEL_PTL_U_ID_2, PTL_CORE_2, TDP_15W, PTL_SKU_5 },
 	{ PCI_DID_INTEL_PTL_U_ID_2, PTL_CORE_2, TDP_25W, PTL_SKU_5 },
-	{ PCI_DID_INTEL_PTL_U_ID_3, PTL_CORE_2, TDP_15W, PTL_SKU_1 },
-	{ PCI_DID_INTEL_PTL_U_ID_3, PTL_CORE_2, TDP_25W, PTL_SKU_1 },
+	{ PCI_DID_INTEL_PTL_U_ID_3, PTL_CORE_1, TDP_15W, PTL_SKU_1 },
+	{ PCI_DID_INTEL_PTL_U_ID_3, PTL_CORE_1, TDP_25W, PTL_SKU_1 },
 	{ PCI_DID_INTEL_PTL_H_ID_1, PTL_CORE_3, TDP_25W, PTL_SKU_2 },
 	{ PCI_DID_INTEL_PTL_H_ID_2, PTL_CORE_3, TDP_25W, PTL_SKU_3 },
-	{ PCI_DID_INTEL_PTL_H_ID_3, PTL_CORE_4, TDP_25W, PTL_SKU_2 },
-	{ PCI_DID_INTEL_PTL_H_ID_4, PTL_CORE_4, TDP_25W, PTL_SKU_2 },
+	{ PCI_DID_INTEL_PTL_H_ID_3, PTL_CORE_4, TDP_25W, PTL_SKU_6 },
+	{ PCI_DID_INTEL_PTL_H_ID_4, PTL_CORE_4, TDP_25W, PTL_SKU_6 },
 	{ PCI_DID_INTEL_PTL_H_ID_5, PTL_CORE_4, TDP_25W, PTL_SKU_4 },
 	{ PCI_DID_INTEL_PTL_H_ID_6, PTL_CORE_4, TDP_25W, PTL_SKU_4 },
 	{ PCI_DID_INTEL_PTL_H_ID_7, PTL_CORE_4, TDP_25W, PTL_SKU_4 },
-	{ PCI_DID_INTEL_PTL_H_ID_8, PTL_CORE_4, TDP_25W, PTL_SKU_2 },
+	{ PCI_DID_INTEL_PTL_H_ID_8, PTL_CORE_3, TDP_25W, PTL_SKU_2 },
 	{ PCI_DID_INTEL_WCL_ID_1, WCL_CORE, TDP_15W, WCL_SKU_1},
 	{ PCI_DID_INTEL_WCL_ID_2, WCL_CORE, TDP_15W, WCL_SKU_2},
 	{ PCI_DID_INTEL_WCL_ID_3, WCL_CORE, TDP_15W, WCL_SKU_3},
diff --git a/src/soc/intel/pantherlake/chipset_ptl.cb b/src/soc/intel/pantherlake/chipset_ptl.cb
index 3ab98a260c..1c6075aff9 100644
--- a/src/soc/intel/pantherlake/chipset_ptl.cb
+++ b/src/soc/intel/pantherlake/chipset_ptl.cb
@@ -9,40 +9,93 @@ chip soc/intel/pantherlake
 		.tdp_pl4_fastvmode = 150,
 	}"
 	register "thermal_design_current[PTL_SKU_1]" = "{
-		[VR_DOMAIN_IA] = 34 * 8,
-		[VR_DOMAIN_GT] = 23 * 8
+		[VR_DOMAIN_IA] = 23 * 8,
+		[VR_DOMAIN_GT] = 15 * 8
+	}"
+	register "icc_max[PTL_SKU_1]" = "{
+		[VR_DOMAIN_IA] = 80 * 4,
+		[VR_DOMAIN_GT] = 56 * 4,
+		[VR_DOMAIN_SA] = 56 * 4,
+		[VR_DOMAIN_ATOM] = 30 * 4
 	}"
 
 	register "power_limits_config[PTL_CORE_2]" = "{
 		.tdp_pl1_override = 15,
-		.tdp_pl2_override = 45,
-		.tdp_pl4 = 105,
-		.tdp_pl4_fastvmode = 95,
+		.tdp_pl2_override = 55,
+		.tdp_pl4 = 163,
+		.tdp_pl4_fastvmode = 150,
 	}"
 	register "thermal_design_current[PTL_SKU_5]" = "{
 		[VR_DOMAIN_IA] = 23 * 8,
-		[VR_DOMAIN_GT] = 23 * 8
+		[VR_DOMAIN_GT] = 15 * 8
+	}"
+	register "icc_max[PTL_SKU_5]" = "{
+		[VR_DOMAIN_IA] = 80 * 4,
+		[VR_DOMAIN_GT] = 56 * 4,
+		[VR_DOMAIN_SA] = 56 * 4,
+		[VR_DOMAIN_ATOM] = 30 * 4
 	}"
 
 	register "power_limits_config[PTL_CORE_3]" = "{
 		.tdp_pl1_override = 25,
-		.tdp_pl2_override = 64,
+		.tdp_pl2_override = 65,
 		.tdp_pl4 = 175,
 		.tdp_pl4_fastvmode = 160,
 	}"
 	register "thermal_design_current[PTL_SKU_2]" = "{
-		[VR_DOMAIN_IA] = 39 * 8,
-		[VR_DOMAIN_GT] = 44 * 8
+		[VR_DOMAIN_IA] = 31 * 8,
+		[VR_DOMAIN_GT] = 25 * 8
+	}"
+	register "icc_max[PTL_SKU_2]" = "{
+		[VR_DOMAIN_IA] = 107 * 4,
+		[VR_DOMAIN_GT] = 124 * 4,
+		[VR_DOMAIN_SA] = 56 * 4,
+		[VR_DOMAIN_ATOM] = 30 * 4
 	}"
 	register "thermal_design_current[PTL_SKU_3]" = "{
-		[VR_DOMAIN_IA] = 39 * 8,
+		[VR_DOMAIN_IA] = 31 * 8,
 		[VR_DOMAIN_GT] = 23 * 8
 	}"
 
 	register "power_limits_config[PTL_CORE_4]" = "{
 		.tdp_pl1_override = 25,
-		.tdp_pl2_override = 64,
-		.tdp_pl4 = 154,
+		.tdp_pl2_override = 65,
+		.tdp_pl4 = 160,
+		.tdp_pl4_fastvmode = 140
+	}"
+
+
+	register "thermal_design_current[PTL_SKU_6]" = "{
+		[VR_DOMAIN_IA] = 31 * 8,
+		[VR_DOMAIN_GT] = 25 * 8
+	}"
+	register "icc_max[PTL_SKU_6]" = "{
+		[VR_DOMAIN_IA] = 90 * 4,
+		[VR_DOMAIN_GT] = 124 * 4,
+		[VR_DOMAIN_SA] = 56 * 4,
+		[VR_DOMAIN_ATOM] = 30 * 4
+	}"
+
+	register "tdc_mode[VR_DOMAIN_IA]" = "TDC_IRMS"
+	register "tdc_mode[VR_DOMAIN_GT]" = "TDC_IRMS"
+	register "tdc_time_window_ms[VR_DOMAIN_IA]" = "28000"
+
+	# Set the power state thresholds according to document 813278
+	# Panther Lake H Platform - Design Guide - Rev 2.0
+	register "ps1_threshold" = "{
+		[VR_DOMAIN_IA] = 20 * 4,
+		[VR_DOMAIN_GT] = 20 * 4,
+		[VR_DOMAIN_SA] = 20 * 4
+	}"
+	register "ps2_threshold" = "{
+		[VR_DOMAIN_IA] = 5 * 4,
+		[VR_DOMAIN_GT] = 5 * 4,
+		[VR_DOMAIN_SA] = 5 * 4
+	}"
+	register "ps3_threshold" = "{
+		[VR_DOMAIN_IA] = 1 * 4,
+		[VR_DOMAIN_GT] = 1 * 4,
+		[VR_DOMAIN_SA] = 1 * 4
 	}"
 
 	# Reduce the size of BasicMemoryTests to speed up the boot time.

From 07f25bef86394bee8273279101f09dc0df0c4e4b Mon Sep 17 00:00:00 2001
From: Nick Vaccaro <nvaccaro@google.com>
Date: Fri, 17 Oct 2025 13:55:45 -0700
Subject: [PATCH 2280/3886] mb/google/ocelot/var/ocelot: fix gpio settings

Configure the GPP_E16 reset line for the touch panel as a GPO.
Configure GPP_E17 to a no-connect by default.

BUG=b:452845001
TEST=`emerge-ocelot coreboot chromeos-bootimage`, flash an ocelotite4es
and verify it can boot to kernel without crashing.

Change-Id: I9ba2009252b84fb85356ef65e7b37017f9d2af43
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89630
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/google/ocelot/variants/ocelot/gpio.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/mainboard/google/ocelot/variants/ocelot/gpio.c b/src/mainboard/google/ocelot/variants/ocelot/gpio.c
index e4592c7201..32e1ae11fb 100644
--- a/src/mainboard/google/ocelot/variants/ocelot/gpio.c
+++ b/src/mainboard/google/ocelot/variants/ocelot/gpio.c
@@ -188,9 +188,9 @@ static const struct pad_config gpio_table[] = {
 	/* GPP_E15:     THC0_SPI1_IO_3_TCH_PNL1 */
 	PAD_CFG_NF(GPP_E15, NONE, DEEP, NF3),
 	/* GPP_E16:     THC0_SPI1_RST_N_TCH_PNL1 */
-	PAD_CFG_NF(GPP_E16, NONE, PLTRST, NF1),
+	PAD_CFG_GPO(GPP_E16, 1, DEEP),
 	/* GPP_E17:     GPP_E17_GSPI0A_CS0 */
-	PAD_CFG_NF(GPP_E17, NONE, DEEP, NF5),
+	PAD_NC(GPP_E17, NONE),
 	/* GPP_E18:     THC0_SPI1_INT_N_TCH_PNL1 */
 	PAD_CFG_NF(GPP_E18, NONE, DEEP, NF3),
 	/* GPP_E19:     FPS_INT_N */

From 74d7a213823eca265733630e2656ce502a3b5bfd Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Wed, 15 Oct 2025 09:12:05 -0500
Subject: [PATCH 2281/3886] nb/intel/haswell/acpi: Add missing MMIO window
 below 4GB

For Broadwell SoC boards (which use Haswell's northbridge ACPI),
coreboot's resource allocator identifies and uses two MMIO windows
below 4GB, but currently only one is declared in the ACPI _CRS.
Normally this isn't a problem, as coreboot is usually able to allocate
resources entirely in the (declared) lower MMIO window. But, this is
problematic when using top-down allocation, since coreboot assigns
resources to devices starting in the (undeclared) upper MMIO window,
which the OS does not consider a valid space.

Linux will mostly handle this gracefully, and reassign BARs in the
lower MMIO address space. Windows does not, and will simply mark any
devices in the upper window as invalid or malfunctioning.

To resolve this, add the dynamically-sized PM02 PCI MMIO window above
MMCONF to match the region used by coreboot's allocator.

With this change, both MMIO windows are properly reported via _CRS,
allowing the OS to use coreboot's resource allocations properly.

coreboot allocator:
[INFO ]   * Base: 80000000, Size: 70000000, Tag: 200  [Window 1: 1.75GB]
[INFO ]   * Base: f4000000, Size:  a000000, Tag: 200  [Window 2:  160MB]

kernel before:
[mem 0x80000000-0xefffffff window]  [PM01: 1.75GB]
[mem 0xf4000000-0xfed44fff window]  [TPM]

kernel after:
[mem 0x80000000-0xefffffff window]  [PM01: 1.75GB]
[mem 0xf4000000-0xfebfffff window]  [PM02:  172MB]
[mem 0xfed40000-0xfed44fff window]  [TPM]

BUG=https://ticket.coreboot.org/issues/611

TEST=Build/boot google/lulu with top-down allocation enabled.
Verify kernel sees both MMIO windows and devices keep their coreboot-
assigned BARs. Verify Windows boots with functional i2c devices.

Change-Id: I83fa8ca7f9edfd7d185895f8bbff15ee9895d1ff
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89588
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
---
 .../intel/haswell/acpi/hostbridge.asl         | 46 ++++++++++++++++++-
 1 file changed, 44 insertions(+), 2 deletions(-)

diff --git a/src/northbridge/intel/haswell/acpi/hostbridge.asl b/src/northbridge/intel/haswell/acpi/hostbridge.asl
index 3ecc5b3b36..509595b3b1 100644
--- a/src/northbridge/intel/haswell/acpi/hostbridge.asl
+++ b/src/northbridge/intel/haswell/acpi/hostbridge.asl
@@ -14,6 +14,12 @@ Device (MCHC)
 	OperationRegion (MCHP, PCI_Config, 0x00, 0x100)
 	Field (MCHP, DWordAcc, NoLock, Preserve)
 	{
+		Offset (0x60),	// PCIEXBAR
+		PXEN,	 1,	// Enable
+		PXSZ,	 2,	// PCIEXBAR size
+		,	23,
+		PXBR,	10,	// PCIEXBAR base
+
 		Offset (0x70),	// ME Base Address
 		MEBA,	 64,
 		Offset (0xa0),	// Top of Used Memory
@@ -125,12 +131,18 @@ Name (MCRS, ResourceTemplate()
 			0x00000000, 0x000f0000, 0x000fffff, 0x00000000,
 			0x00010000,,, FSEG)
 
-	// PCI Memory Region (Top of memory-CONFIG_ECAM_MMCONF_BASE_ADDRESS)
+	// PCI Memory Region below MMCONF (TOLUD)
 	DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
 			Cacheable, ReadWrite,
 			0x00000000, 0x00000000, 0x00000000, 0x00000000,
 			0x00000000,,, PM01)
-
+#if CONFIG(SOC_INTEL_BROADWELL)
+	// PCI Memory Region above MMCONF (dynamic, based on ECAM size)
+	DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
+			Cacheable, ReadWrite,
+			0x00000000, 0x00000000, 0x00000000, 0x00000000,
+			0x00000000,,, PM02)
+#endif
 	// TPM Area (0xfed40000-0xfed44fff)
 	DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
 			Cacheable, ReadWrite,
@@ -164,6 +176,36 @@ Method (_CRS, 0, Serialized)
 	PMAX = CONFIG_ECAM_MMCONF_BASE_ADDRESS - 1
 	PLEN = (PMAX - PMIN) + 1
 
+#if CONFIG(SOC_INTEL_BROADWELL)
+	// Set up PM02 region (MMCONF end to 0xFEBFFFFF)
+	CreateDwordField (MCRS, ^PM02._MIN, PM2B)
+	CreateDwordField (MCRS, ^PM02._MAX, PM2M)
+	CreateDwordField (MCRS, ^PM02._LEN, PM2L)
+
+	// Calculate ECAM/MMCONF end address based on size bits in PCIEXBAR
+	// Bits [2:1] encode size: 00=256MB, 01=128MB, 10=64MB, 11=reserved
+	Local2 = ^MCHC.PXSZ
+
+	// Populate based on ECAM size
+	If (Local2 == 0) {
+		// 256MB ECAM - no space for PM02 (would extend to 4GB boundary)
+		PM2L = 0
+	} Else {
+		// 128MB or 64MB ECAM - there's space for PM02
+		Local3 = CONFIG_ECAM_MMCONF_BASE_ADDRESS
+		If (Local2 == 1) {
+			// 128MB ECAM - ends at base + 0x08000000
+			Local3 += 0x08000000
+		} Else {
+			// 64MB ECAM (or reserved=3) - ends at base + 0x04000000
+			Local3 += 0x04000000
+		}
+
+		PM2B = Local3
+		PM2M = 0xFEBFFFFF  // Just before chipset reserved (IOAPIC at 0xFEC00000)
+		PM2L = PM2M - PM2B + 1
+	}
+#endif
 	Return (MCRS)
 }
 

From 321d8c5b219f8b84ad1e29e641064b9369ac0753 Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Tue, 14 Oct 2025 16:48:57 -0500
Subject: [PATCH 2282/3886] soc/intel/braswell/acpi: Add missing MMIO window
 below 4GB
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

coreboot's resource allocator identifies and uses two MMIO windows
below 4GB, but currently only one is declared in the ACPI _CRS.
Normally this isn't a problem, as coreboot is usually able to allocate
resources entirely in the (declared) lower MMIO window. But, this is
problematic when using top-down allocation, since coreboot assigns
resources to devices starting in the (undeclared) upper MMIO window,
which the OS does not consider a valid space.

Linux will mostly handle this gracefully, and reassign BARs in the
lower MMIO address space. Windows does not, and will simply mark any
devices in the upper window as invalid or malfunctioning.

To resolve this, add the fixed-sized PM02 PCI MMIO window above MMCONF
to match the region used by coreboot's allocator.

With this change, both MMIO windows are properly reported via _CRS,
allowing the OS to use coreboot's resource allocations properly.

coreboot allocator:
[INFO ]   * Base: 80000000, Size: 60000000, Tag: 200  [Window 1: 1.50GB]
[INFO ]   * Base: f0000000, Size:  e000000, Tag: 200  [Window 2:  224MB]

kernel before:
[mem 0x80000000-0xdfffffff window]  [PM01: 1.50GB]
[mem 0xf4000000-0xfed44fff window]  [TPM]

kernel after:
[mem 0x80000000-0xdfffffff window]  [PM01: 1.50GB]
[mem 0xf0000000-0xfdffffff window]  [PM02:  224MB]
[mem 0xfed40000-0xfed44fff window]  [TPM]

BUG=https://ticket.coreboot.org/issues/611

TEST=Build/boot google/edgar with top-down allocation enabled.
Verify kernel sees both MMIO windows and devices keep their coreboot-
assigned BARs. Verify Windows boots with functional i2c devices.

Change-Id: I86c38b6f0d3e31affb578dc7a1bf5c8109714bf5
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89590
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/soc/intel/braswell/acpi/southcluster.asl | 8 +++++++-
 1 file changed, 7 insertions(+), 1 deletion(-)

diff --git a/src/soc/intel/braswell/acpi/southcluster.asl b/src/soc/intel/braswell/acpi/southcluster.asl
index 7329096cf0..a094c16dbd 100644
--- a/src/soc/intel/braswell/acpi/southcluster.asl
+++ b/src/soc/intel/braswell/acpi/southcluster.asl
@@ -137,12 +137,18 @@ Method (_CRS, 0, Serialized)
 				0x00000000, 0x20000000, 0x201FFFFF, 0x00000000,
 				0x00200000,,, LMEM)
 
-		/* PCI Memory Region (Top of memory-CONFIG_ECAM_MMCONF_BASE_ADDRESS) */
+		/* PCI Memory Region (TOLM - CONFIG_ECAM_MMCONF_BASE_ADDRESS) */
 		DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
 				Cacheable, ReadWrite,
 				0x00000000, 0x00000000, 0x00000000, 0x00000000,
 				0x00000000,,, PMEM)
 
+		/* PCI Memory Region above MMCONF (0xf0000000 - 0xfdffffff) */
+		DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
+				Cacheable, ReadWrite,
+				0x00000000, 0xf0000000, 0xfdffffff, 0x00000000,
+				0x0e000000,,, PM02)
+
 		/* TPM Area (0xfed40000-0xfed44fff) */
 		DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
 				Cacheable, ReadWrite,

From 6b93516e021845d47f44d44fd0afbdfaa86cc8e4 Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Tue, 14 Oct 2025 16:30:12 -0500
Subject: [PATCH 2283/3886] soc/intel/baytrail/acpi: Add missing MMIO window
 below 4GB

coreboot's resource allocator identifies and uses two MMIO windows
below 4GB, but currently only one is declared in the ACPI _CRS.
Normally this isn't a problem, as coreboot is usually able to allocate
resources entirely in the (declared) lower MMIO window. But, this is
problematic when using top-down allocation, since coreboot assigns
resources to devices starting in the (undeclared) upper MMIO window,
which the OS does not consider a valid space.

Linux will mostly handle this gracefully, and reassign BARs in the
lower MMIO address space. Windows does not, and will simply mark any
devices in the upper window as invalid or malfunctioning.

To resolve this, add the fixed-sized PM02 PCI MMIO window above MMCONF
to match the region used by coreboot's allocator.

With this change, both MMIO windows are properly reported via _CRS,
allowing the OS to use coreboot's resource allocations properly.

coreboot allocator:
[INFO ]   * Base: 80000000, Size: 60000000, Tag: 200  [Window 1: 1.50GB]
[INFO ]   * Base: f0000000, Size:  e000000, Tag: 200  [Window 2:  224MB]

kernel before:
[mem 0x80000000-0xdfffffff window]  [PM01: 1.50GB]
[mem 0xf4000000-0xfed44fff window]  [TPM]

kernel after:
[mem 0x80000000-0xdfffffff window]  [PM01: 1.50GB]
[mem 0xf0000000-0xfdffffff window]  [PM02:  224MB]
[mem 0xfed40000-0xfed44fff window]  [TPM]

BUG=https://ticket.coreboot.org/issues/611

TEST=Build/boot google/swanky with top-down allocation enabled.
Verify kernel sees both MMIO windows and devices keep their coreboot-
assigned BARs. Verify Windows boots with functional i2c devices.

Change-Id: Ibb61d3188f75a963e9417685c2808b27055b46d1
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89589
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Walter Sonius <walterav1984@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
---
 src/soc/intel/baytrail/acpi/southcluster.asl | 10 ++++++++--
 1 file changed, 8 insertions(+), 2 deletions(-)

diff --git a/src/soc/intel/baytrail/acpi/southcluster.asl b/src/soc/intel/baytrail/acpi/southcluster.asl
index 9f3c76fff1..48fe9668a7 100644
--- a/src/soc/intel/baytrail/acpi/southcluster.asl
+++ b/src/soc/intel/baytrail/acpi/southcluster.asl
@@ -135,11 +135,17 @@ Name (MCRS, ResourceTemplate()
 			0x00000000, 0x00000000, 0x00000000, 0x00000000,
 			0x00000000,,, LMEM)
 
-	/* PCI Memory Region (Top of memory-CONFIG_ECAM_MMCONF_BASE_ADDRESS) */
+	/* PCI Memory Region (TOLM - CONFIG_ECAM_MMCONF_BASE_ADDRESS) */
 	DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
 			Cacheable, ReadWrite,
 			0x00000000, 0x00000000, 0x00000000, 0x00000000,
-                        0x00000000,,, PMEM)
+			0x00000000,,, PMEM)
+
+	/* PCI Memory Region above MMCONF (0xf0000000 - 0xfdffffff) */
+	DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
+			Cacheable, ReadWrite,
+			0x00000000, 0xf0000000, 0xfdffffff, 0x00000000,
+			0x0e000000,,, PM02)
 
 	/* TPM Area (0xfed40000-0xfed44fff) */
 	DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,

From 3aa312e4c976ffca506d9b580ecce443a8a330b5 Mon Sep 17 00:00:00 2001
From: Xiandong Wang <xiandong.wang@mediatek.corp-partner.google.com>
Date: Fri, 10 Oct 2025 11:16:24 +0800
Subject: [PATCH 2284/3886] soc/mediatek/mt8189: Add DSI path support and
 update mutex

Previously, only the EDP display path was supported due to incorrect
mutex bitfield assignments and incomplete main path setup logic. This
commit corrects the mutex bitfield assignments after reviewing the
datasheet, and updates the main path setup logic to enable support for
both EDP and DSI display paths, improving overall compatibility.

BUG=b:433422905,b:428854543
BRANCH=skywalker
TEST=Check log on padme
mtk_display_init: 'TM TL121BVMS07' 1600x2560@60Hz

Signed-off-by: Xiandong Wang <xiandong.wang@mediatek.corp-partner.google.com>
Change-Id: Ic3f901b9dff0a7ec9188212d2311b8394cf5c0e7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89566
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
---
 src/soc/mediatek/mt8189/ddp.c             | 14 ++++++++++----
 src/soc/mediatek/mt8189/include/soc/ddp.h | 16 ++++++++++------
 2 files changed, 20 insertions(+), 10 deletions(-)

diff --git a/src/soc/mediatek/mt8189/ddp.c b/src/soc/mediatek/mt8189/ddp.c
index f7bdc7f835..1d5630736c 100644
--- a/src/soc/mediatek/mt8189/ddp.c
+++ b/src/soc/mediatek/mt8189/ddp.c
@@ -14,7 +14,8 @@ static void disp_config_main_path_connection(enum disp_path_sel path)
 	write32(&mmsys_cfg->disp_rdma0_sel_in, 0x1);
 	write32(&mmsys_cfg->disp_rdma0_rsz0_sout_sel, 0x0);
 	write32(&mmsys_cfg->ovl_pq_out_cross1_mout_en, 0x10);
-	write32(&mmsys_cfg->comp_out_cross4_mout_en, 0x02);
+	write32(&mmsys_cfg->comp_out_cross4_mout_en,
+		path == DISP_PATH_EDP ? 0x02 : 0x01);
 	printk(BIOS_DEBUG,
 	       "%s: bgclr_mout_en: %#x ovl0_mout_en: %#x sel_in: %#x sout_sel: %#x"
 	       "cross1_mout_en: %#x cross4_mout_en: %#x\n",
@@ -28,11 +29,16 @@ static void disp_config_main_path_connection(enum disp_path_sel path)
 
 static void disp_config_main_path_mutex(enum disp_path_sel path)
 {
-	write32(&disp_mutex->mutex[0].mod, MUTEX_MOD_MAIN_PATH);
+	u32 val;
+
+	val = path == DISP_PATH_EDP ? MUTEX_MOD_MAIN_PATH : MUTEX_MOD_MAIN_DSI_PATH;
+	write32(&disp_mutex->mutex[0].mod, val);
 
 	/* Clock source from DVO0 */
-	write32(&disp_mutex->mutex[0].ctl,
-		MUTEX_SOF_DVO | (MUTEX_SOF_DVO << 7));
+	val = path == DISP_PATH_EDP ? (MUTEX_SOF_DVO | (MUTEX_SOF_DVO << 7)) :
+		(MUTEX_SOF_DSI0 | (MUTEX_SOF_DSI0 << 7));
+	write32(&disp_mutex->mutex[0].ctl, val);
+
 	write32(&disp_mutex->mutex[0].en, BIT(0));
 	printk(BIOS_DEBUG, "%s: mutex_mod: %#x ctl %#x\n",
 	       __func__, read32(&disp_mutex->mutex[0].mod), read32(&disp_mutex->mutex[0].ctl));
diff --git a/src/soc/mediatek/mt8189/include/soc/ddp.h b/src/soc/mediatek/mt8189/include/soc/ddp.h
index feb975af8b..a9d02f75d9 100644
--- a/src/soc/mediatek/mt8189/include/soc/ddp.h
+++ b/src/soc/mediatek/mt8189/include/soc/ddp.h
@@ -268,15 +268,19 @@ DEFINE_BIT(PQ_CFG_ENGINE_EN, 1)
 enum {
 	MUTEX_MOD_DISP_OVL0		= BIT(0),
 	MUTEX_MOD_DISP_RDMA0		= BIT(4),
-	MUTEX_MOD_DISP_COLOR0		= BIT(4),
-	MUTEX_MOD_DISP_CCORR0		= BIT(5),
-	MUTEX_MOD_DISP_CCORR2		= BIT(6),
-	MUTEX_MOD_DISP_AAL0		= BIT(7),
-	MUTEX_MOD_DISP_GAMMA0		= BIT(8),
-	MUTEX_MOD_DISP_DITHER0		= BIT(10),
+	MUTEX_MOD_DISP_COLOR0		= BIT(6),
+	MUTEX_MOD_DISP_CCORR0		= BIT(8),
+	MUTEX_MOD_DISP_CCORR2		= BIT(10),
+	MUTEX_MOD_DISP_AAL0		= BIT(12),
+	MUTEX_MOD_DISP_GAMMA0		= BIT(14),
+	MUTEX_MOD_DISP_DITHER0		= BIT(16),
+	MUTEX_MOD_DISP_DSI0		= BIT(22),
 
 	MUTEX_MOD_MAIN_PATH		= MUTEX_MOD_DISP_OVL0 |
 					  MUTEX_MOD_DISP_RDMA0,
+	MUTEX_MOD_MAIN_DSI_PATH		= MUTEX_MOD_DISP_OVL0 |
+					  MUTEX_MOD_DISP_RDMA0 |
+					  MUTEX_MOD_DISP_DSI0,
 };
 
 enum {

From 402ac7cd8126a0710acc2c99dd79d39e9722555e Mon Sep 17 00:00:00 2001
From: Elyes Haouas <ehaouas@noos.fr>
Date: Tue, 23 Sep 2025 07:59:30 +0200
Subject: [PATCH 2285/3886] crossgcc: Upgrade acpica from 20250404 to 20250807

Change-Id: I6584128af65e1dc5e0d3db5d4fae8ac68eeca036
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89306
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 util/crossgcc/buildgcc                                        | 4 ++--
 ...ix-20250404_iasl.patch => acpica-unix-20250807_iasl.patch} | 0
 util/crossgcc/sum/acpica-unix-20250404.tar.gz.cksum           | 1 -
 util/crossgcc/sum/acpica-unix-20250807.tar.gz.cksum           | 1 +
 4 files changed, 3 insertions(+), 3 deletions(-)
 rename util/crossgcc/patches/{acpica-unix-20250404_iasl.patch => acpica-unix-20250807_iasl.patch} (100%)
 delete mode 100644 util/crossgcc/sum/acpica-unix-20250404.tar.gz.cksum
 create mode 100644 util/crossgcc/sum/acpica-unix-20250807.tar.gz.cksum

diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc
index 1984054fa9..832ee2ce28 100755
--- a/util/crossgcc/buildgcc
+++ b/util/crossgcc/buildgcc
@@ -46,7 +46,7 @@ LIBSTDCXX_VERSION="${GCC_VERSION}"	# GCC-specific C++ library
 
 # Low-level Tools (built after GCC)
 NASM_VERSION=2.16.03	# x86 assembly
-IASL_VERSION=20250404	# ACPI compiler
+IASL_VERSION=20250807	# ACPI compiler
 
 # Clang/LLVM Toolchain (alternative to GCC, built separately)
 CLANG_VERSION=18.1.8
@@ -86,7 +86,7 @@ MPC_BASE_URL="https://ftpmirror.gnu.org/mpc"
 GCC_BASE_URL="https://ftpmirror.gnu.org/gcc/gcc-${GCC_VERSION}"
 LIBSTDCXX_BASE_URL="${GCC_BASE_URL}"
 BINUTILS_BASE_URL="https://ftpmirror.gnu.org/binutils"
-IASL_BASE_URL="https://downloadmirror.intel.com/852044"
+IASL_BASE_URL="https://downloadmirror.intel.com/864114"
 # CLANG toolchain archive locations
 LLVM_BASE_URL="https://github.com/llvm/llvm-project/releases/download/llvmorg-${CLANG_VERSION}"
 CLANG_BASE_URL="https://github.com/llvm/llvm-project/releases/download/llvmorg-${CLANG_VERSION}"
diff --git a/util/crossgcc/patches/acpica-unix-20250404_iasl.patch b/util/crossgcc/patches/acpica-unix-20250807_iasl.patch
similarity index 100%
rename from util/crossgcc/patches/acpica-unix-20250404_iasl.patch
rename to util/crossgcc/patches/acpica-unix-20250807_iasl.patch
diff --git a/util/crossgcc/sum/acpica-unix-20250404.tar.gz.cksum b/util/crossgcc/sum/acpica-unix-20250404.tar.gz.cksum
deleted file mode 100644
index 83d38deb24..0000000000
--- a/util/crossgcc/sum/acpica-unix-20250404.tar.gz.cksum
+++ /dev/null
@@ -1 +0,0 @@
-aeff4d1254e73263b4f2c6f7d1e96af47fa219e0  tarballs/acpica-unix-20250404.tar.gz
diff --git a/util/crossgcc/sum/acpica-unix-20250807.tar.gz.cksum b/util/crossgcc/sum/acpica-unix-20250807.tar.gz.cksum
new file mode 100644
index 0000000000..188ab9995b
--- /dev/null
+++ b/util/crossgcc/sum/acpica-unix-20250807.tar.gz.cksum
@@ -0,0 +1 @@
+76f0529964955679178714bc580eb560e52fab12  tarballs/acpica-unix-20250807.tar.gz

From 35970abcdfe127cfe2cf08cf766b574b733242db Mon Sep 17 00:00:00 2001
From: David Wu <david_wu@quanta.corp-partner.google.com>
Date: Fri, 17 Oct 2025 11:49:14 +0800
Subject: [PATCH 2286/3886] mb/google/nissa/var/dirks: Add H58G56CK8BX146 to
 RAM ID table

Add the new memory support: Hynix H58G56CK8BX146

BUG=b:442335706
BRANCH=firmware-nissa-15217.B
TEST=Run part_id_gen tool and check the generated files.

Change-Id: I48d1ac1b04c83a05859f2aaa17218d997cb5a3ac
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89618
Reviewed-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
---
 src/mainboard/google/brya/variants/dirks/memory/Makefile.mk     | 2 +-
 .../google/brya/variants/dirks/memory/dram_id.generated.txt     | 1 +
 .../google/brya/variants/dirks/memory/mem_parts_used.txt        | 1 +
 3 files changed, 3 insertions(+), 1 deletion(-)

diff --git a/src/mainboard/google/brya/variants/dirks/memory/Makefile.mk b/src/mainboard/google/brya/variants/dirks/memory/Makefile.mk
index 67b6ac1b88..769b2f33fe 100644
--- a/src/mainboard/google/brya/variants/dirks/memory/Makefile.mk
+++ b/src/mainboard/google/brya/variants/dirks/memory/Makefile.mk
@@ -9,6 +9,6 @@ SPD_SOURCES += spd/lp5/set-0/spd-1.hex      # ID = 1(0b0001)  Parts = MT62F512M3
 SPD_SOURCES += spd/lp5/set-0/spd-5.hex      # ID = 2(0b0010)  Parts = K3LKLKL0EM-MGCN
 SPD_SOURCES += spd/lp5/set-0/spd-3.hex      # ID = 3(0b0011)  Parts = K3LKBKB0BM-MGCP
 SPD_SOURCES += spd/lp5/set-0/spd-7.hex      # ID = 4(0b0100)  Parts = K3KL8L80CM-MGCT
-SPD_SOURCES += spd/lp5/set-0/spd-11.hex      # ID = 5(0b0101)  Parts = H58G56BK8BX068
+SPD_SOURCES += spd/lp5/set-0/spd-11.hex      # ID = 5(0b0101)  Parts = H58G56BK8BX068, H58G56CK8BX146
 SPD_SOURCES += spd/lp5/set-0/spd-8.hex      # ID = 6(0b0110)  Parts = K3KL9L90CM-MGCT
 SPD_SOURCES += spd/lp5/set-0/spd-10.hex      # ID = 7(0b0111)  Parts = H58G66BK8BX067
diff --git a/src/mainboard/google/brya/variants/dirks/memory/dram_id.generated.txt b/src/mainboard/google/brya/variants/dirks/memory/dram_id.generated.txt
index 059f1e69be..d9264d743b 100644
--- a/src/mainboard/google/brya/variants/dirks/memory/dram_id.generated.txt
+++ b/src/mainboard/google/brya/variants/dirks/memory/dram_id.generated.txt
@@ -14,3 +14,4 @@ K3KL8L80CM-MGCT                4 (0100)
 H58G56BK8BX068                 5 (0101)
 K3KL9L90CM-MGCT                6 (0110)
 H58G66BK8BX067                 7 (0111)
+H58G56CK8BX146                 5 (0101)
diff --git a/src/mainboard/google/brya/variants/dirks/memory/mem_parts_used.txt b/src/mainboard/google/brya/variants/dirks/memory/mem_parts_used.txt
index 61be3e79aa..f2459f39fa 100644
--- a/src/mainboard/google/brya/variants/dirks/memory/mem_parts_used.txt
+++ b/src/mainboard/google/brya/variants/dirks/memory/mem_parts_used.txt
@@ -19,3 +19,4 @@ K3KL8L80CM-MGCT
 H58G56BK8BX068
 K3KL9L90CM-MGCT
 H58G66BK8BX067
+H58G56CK8BX146

From f1c973bbff56e067cd248ff22770fc47c933d31f Mon Sep 17 00:00:00 2001
From: Maciej Strozek <mstrozek@opensource.cirrus.com>
Date: Tue, 16 Sep 2025 12:39:08 +0100
Subject: [PATCH 2287/3886] drivers/soundwire/cs42l43: Support Cirrus Logic
 CS42L43 codec

CS42L43 is a PC Codec with headphone and class D speaker drivers.

The driver was written based on the datasheet for CS42L43 part and
generates the audio SSDT information.

CS42L43 supports DisCo Version v2.1, but coreboot currently only
supports DisCo v1.0, so ACPI is only generated based on DisCo v1.0.

CS42L43 also supports the SDCA v1.0 Specification (from DisCo v2.1)
is also not currently supported by coreboot, therefore SDCA ACPI
properties are also not generated.

This is currently only tested using QEMU using example configuration:

chip drivers/soundwire/cs42l43
	# SoundWire Link 0 ID 1
	register "desc" = ""CODEC""
	register "sub" = ""1337""
	device generic 0.1 on end
end

Which produces the ACPI:

Device (SW01)
{
    Name (_ADR, 0x00003101FA424301)  // _ADR: Address
    Name (_DDN, "CODEC")  // _DDN: DOS Device Name
    Name (_SUB, "1337")  // _SUB: Subsystem ID
    Method (_STA, 0, NotSerialized)  // _STA: Status
    {
        Return (0x0F)
    }

    Name (_DSD, Package (0x04)  // _DSD: Device-Specific Data
    {
        ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301") /* Device Properties for _DSD */,
        Package (0x0F)
        {
            Package (0x02)
            {
                "mipi-sdw-sw-interface-revision",
                0x00010000
            },

            Package (0x02)
            {
                "mipi-sdw-wake-up-unavailable",
                Zero
            },

            Package (0x02)
            {
                "mipi-sdw-test-mode-supported",
                Zero
            },

            Package (0x02)
            {
                "mipi-sdw-clock-stop-mode1-supported",
                Zero
            },

            Package (0x02)
            {
                "mipi-sdw-simplified-clockstopprepare-sm-supported",
                Zero
            },

            Package (0x02)
            {
                "mipi-sdw-clockstopprepare-timeout",
                Zero
            },

            Package (0x02)
            {
                "mipi-sdw-clockstopprepare-hard-reset-behavior",
                Zero
            },

            Package (0x02)
            {
                "mipi-sdw-slave-channelprepare-timeout",
                Zero
            },

            Package (0x02)
            {
                "mipi-sdw-highPHY-capable",
                Zero
            },

            Package (0x02)
            {
                "mipi-sdw-paging-supported",
                One
            },

            Package (0x02)
            {
                "mipi-sdw-bank-delay-supported",
                Zero
            },

            Package (0x02)
            {
                "mipi-sdw-port15-read-behavior",
                Zero
            },

            Package (0x02)
            {
                "mipi-sdw-master-count",
                Zero
            },

            Package (0x02)
            {
                "mipi-sdw-source-port-list",
                0x06
            },

            Package (0x02)
            {
                "mipi-sdw-sink-port-list",
                0x60
            }
        },

        ToUUID ("dbb8e3e6-5886-4ba6-8795-1319f52a966b") /* Hierarchical Data Extension */,
        Package (0x06)
        {
            Package (0x02)
            {
                "mipi-sdw-port-bra-mode-0",
                "BRA0"
            },

            Package (0x02)
            {
                "mipi-sdw-dp-0-subproperties",
                "DP0"
            },

            Package (0x02)
            {
                "mipi-sdw-dp-2-source-subproperties",
                "SRC2"
            },

            Package (0x02)
            {
                "mipi-sdw-dp-5-sink-subproperties",
                "SNK5"
            },

            Package (0x02)
            {
                "mipi-sdw-dp-1-sink-subproperties",
                "SNK1"
            },

            Package (0x02)
            {
                "mipi-sdw-dp-6-source-subproperties",
                "SRC6"
            }
        }
    })
    Name (BRA0, Package (0x02)
    {
        ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301") /* Device Properties for _DSD */,
        Package (0x04)
        {
            Package (0x02)
            {
                "mipi-sdw-bra-mode-min-bus-frequency",
                Zero
            },

            Package (0x02)
            {
                "mipi-sdw-bra-mode-max-bus-frequency",
                Zero
            },

            Package (0x02)
            {
                "mipi-sdw-bra-mode-max-data-per-frame",
                0x01D6
            },

            Package (0x02)
            {
                "mipi-sdw-bra-mode-min-us-between-transactions",
                Zero
            }
        }
    })
    Name (DP0, Package (0x04)
    {
        ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301") /* Device Properties for _DSD */,
        Package (0x07)
        {
            Package (0x02)
            {
                "mipi-sdw-port-wordlength-configs",
                Package (0x03)
                {
                    0x08,
                    0x10,
                    0x18
                }
            },

            Package (0x02)
            {
                "mipi-sdw-bra-flow-controlled",
                One
            },

            Package (0x02)
            {
                "mipi-sdw-bra-imp-def-response-supported",
                One
            },

            Package (0x02)
            {
                "mipi-sdw-bra-role-supported",
                One
            },

            Package (0x02)
            {
                "mipi-sdw-simplified-channel-prepare-sm",
                Zero
            },

            Package (0x02)
            {
                "mipi-sdw-imp-def-dp0-interrupts-supported",
                Zero
            },

            Package (0x02)
            {
                "mipi-sdw-imp-def-bpt-supported",
                Zero
            }
        },

        ToUUID ("dbb8e3e6-5886-4ba6-8795-1319f52a966b") /* Hierarchical Data Extension */,
        Package (0x01)
        {
            Package (0x02)
            {
                "mipi-sdw-port-bra-mode-0",
                "BRA0"
            }
        }
    })
    Name (SRC2, Package (0x02)
    {
        ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301") /* Device Properties for _DSD */,
        Package (0x0C)
        {
            Package (0x02)
            {
                "mipi-sdw-data-port-type",
                Zero
            },

            Package (0x02)
            {
                "mipi-sdw-max-grouping-supported",
                Zero
            },

            Package (0x02)
            {
                "mipi-sdw-imp-def-dpn-interrupts-supported",
                Zero
            },

            Package (0x02)
            {
                "mipi-sdw-modes-supported",
                One
            },

            Package (0x02)
            {
                "mipi-sdw-max-async-buffer",
                Zero
            },

            Package (0x02)
            {
                "mipi-sdw-block-packing-mode",
                One
            },

            Package (0x02)
            {
                "mipi-sdw-port-encoding-type",
                One
            },

            Package (0x02)
            {
                "mipi-sdw-port-wordlength-configs",
                Package (0x03)
                {
                    0x08,
                    0x10,
                    0x18
                }
            },

            Package (0x02)
            {
                "mipi-sdw-simplified-channelprepare-sm",
                Zero
            },

            Package (0x02)
            {
                "mipi-sdw-port-channelprepare-timeout",
                Zero
            },

            Package (0x02)
            {
                "mipi-sdw-channel-number-list",
                Package (0x02)
                {
                    Zero,
                    One
                }
            },

            Package (0x02)
            {
                "mipi-sdw-channel-combination-list",
                Package (0x03)
                {
                    0x03,
                    0x02,
                    One
                }
            }
        }
    })
    Name (SNK5, Package (0x02)
    {
        [... Same as SRC2 ...]
    })
    Name (SNK1, Package (0x02)
    {
        [... Same as SRC2 except:]

	Package (0x02)
	{
	    "mipi-sdw-channel-number-list",
	    Package (0x04)
	    {
	        Zero,
	        One,
	        0x02,
	        0x03
	    }
	},

	Package (0x02)
	{
	    "mipi-sdw-channel-combination-list",
	    Package (0x04)
	    {
	        One,
	        0x03,
	        0x07,
	        0x0F
	    }
	}

        [ Same as SRC2 ...]

        }
    })
    Name (SRC6, Package (0x02)
    {
        [... Same as SRC2 ...]
    })
}

Change-Id: I38f40d29945b22f9c308ea4b7ed6157ccadb3c7c
Signed-off-by: Maciej Strozek <mstrozek@opensource.cirrus.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89230
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
---
 src/drivers/soundwire/cs42l43/Kconfig     |   8 ++
 src/drivers/soundwire/cs42l43/Makefile.mk |   3 +
 src/drivers/soundwire/cs42l43/chip.h      |  17 +++
 src/drivers/soundwire/cs42l43/cs42l43.c   | 166 ++++++++++++++++++++++
 src/include/mipi/ids.h                    |   1 +
 5 files changed, 195 insertions(+)
 create mode 100644 src/drivers/soundwire/cs42l43/Kconfig
 create mode 100644 src/drivers/soundwire/cs42l43/Makefile.mk
 create mode 100644 src/drivers/soundwire/cs42l43/chip.h
 create mode 100644 src/drivers/soundwire/cs42l43/cs42l43.c

diff --git a/src/drivers/soundwire/cs42l43/Kconfig b/src/drivers/soundwire/cs42l43/Kconfig
new file mode 100644
index 0000000000..d21ede7e0e
--- /dev/null
+++ b/src/drivers/soundwire/cs42l43/Kconfig
@@ -0,0 +1,8 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
+config DRIVERS_SOUNDWIRE_CS42L43
+	bool
+	depends on HAVE_ACPI_TABLES
+	default n
+	help
+	  SoundWire CS42L43 CODEC SSDT generator.
diff --git a/src/drivers/soundwire/cs42l43/Makefile.mk b/src/drivers/soundwire/cs42l43/Makefile.mk
new file mode 100644
index 0000000000..8c68a106cb
--- /dev/null
+++ b/src/drivers/soundwire/cs42l43/Makefile.mk
@@ -0,0 +1,3 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
+ramstage-$(CONFIG_DRIVERS_SOUNDWIRE_CS42L43) += cs42l43.c
diff --git a/src/drivers/soundwire/cs42l43/chip.h b/src/drivers/soundwire/cs42l43/chip.h
new file mode 100644
index 0000000000..35fdc93e14
--- /dev/null
+++ b/src/drivers/soundwire/cs42l43/chip.h
@@ -0,0 +1,17 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef __DRIVERS_SOUNDWIRE_CS42L43_CHIP_H__
+#define __DRIVERS_SOUNDWIRE_CS42L43_CHIP_H__
+
+#include <acpi/acpi.h>
+#include <acpi/acpi_device.h>
+#include <mipi/ids.h>
+
+struct drivers_soundwire_cs42l43_config {
+	char acpi_name[ACPI_NAME_BUFFER_SIZE]; /* Set by the acpi_name ops */
+	const char *desc;
+
+	const char *sub; /* SUB ID to uniquely identify system */
+};
+
+#endif /* __DRIVERS_SOUNDWIRE_CS42L43_CHIP_H__ */
diff --git a/src/drivers/soundwire/cs42l43/cs42l43.c b/src/drivers/soundwire/cs42l43/cs42l43.c
new file mode 100644
index 0000000000..e39176e7b2
--- /dev/null
+++ b/src/drivers/soundwire/cs42l43/cs42l43.c
@@ -0,0 +1,166 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <acpi/acpigen.h>
+#include <acpi/acpi_device.h>
+#include <acpi/acpi_soundwire.h>
+#include <device/device.h>
+#include <device/soundwire.h>
+#include <mipi/ids.h>
+#include <stdio.h>
+
+#include "chip.h"
+
+static struct soundwire_address cs42l43_address = {
+	.version = SOUNDWIRE_VERSION_1_2,
+	.manufacturer_id = MIPI_MFG_ID_CIRRUS,
+	.part_id = MIPI_DEV_ID_CIRRUS_CS42L43,
+	.class = MIPI_CLASS_SDCA
+};
+
+static struct soundwire_slave cs42l43_slave = {
+	.wake_up_unavailable = false,
+	.test_mode_supported = false,
+	.clock_stop_mode1_supported = false,
+	.simplified_clockstopprepare_sm_supported = false,
+	.paging_supported = true,
+	.source_port_list = SOUNDWIRE_PORT(1) | SOUNDWIRE_PORT(2),
+	.sink_port_list = SOUNDWIRE_PORT(5) | SOUNDWIRE_PORT(6)
+};
+
+static struct soundwire_dp0 cs42l43_dp0 = {
+	.port_wordlength_configs_count = 3,
+	.port_wordlength_configs = {8, 16, 24},
+	.bra_flow_controlled = true,
+	.bra_imp_def_response_supported = true,
+	.bra_role_supported = true,
+	.imp_def_dp0_interrupts_supported = 0,
+	.imp_def_bpt_supported = false,
+	.bra_mode_count = 1,
+	.bra_mode_list = { 0 },
+	.simplified_channel_prepare_sm = false
+};
+
+static struct soundwire_bra_mode cs42l43_dp0_bra_mode = {
+	.max_data_per_frame = 470,
+	.block_alignment = 4
+};
+
+static struct soundwire_dpn cs42l43_dp1 = {
+	.data_port_type = FULL_DATA_PORT,
+	.max_grouping_supported = BLOCK_GROUP_COUNT_1,
+	.modes_supported = MODE_ISOCHRONOUS,
+	.max_async_buffer = 0,
+	.block_packing_mode = true,
+	.port_encoding_type = ENCODE_TWOS_COMPLEMENT,
+	.port_wordlength_configs_count = 3,
+	.port_wordlength_configs = {8, 16, 24},
+	.simplified_channelprepare_sm = false,
+	.channel_number_list_count = 4,
+	.channel_number_list = {0, 1, 2, 3},
+	.channel_combination_list_count = 4,
+	.channel_combination_list = {0x1, 0x3, 0x7, 0xF},
+	.port_audio_mode_count = 0
+};
+
+static struct soundwire_dpn cs42l43_dpn = {
+	.data_port_type = FULL_DATA_PORT,
+	.max_grouping_supported = BLOCK_GROUP_COUNT_1,
+	.modes_supported = MODE_ISOCHRONOUS,
+	.max_async_buffer = 0,
+	.block_packing_mode = true,
+	.port_encoding_type = ENCODE_TWOS_COMPLEMENT,
+	.port_wordlength_configs_count = 3,
+	.port_wordlength_configs = {8, 16, 24},
+	.simplified_channelprepare_sm = false,
+	.channel_number_list_count = 2,
+	.channel_number_list = {0, 1},
+	.channel_combination_list_count = 3,
+	.channel_combination_list = {0x3, 0x2, 0x1},
+	.port_audio_mode_count = 0
+};
+
+static const struct soundwire_codec cs42l43_codec = {
+	.slave = &cs42l43_slave,
+	.dp0 = &cs42l43_dp0,
+	.dp0_bra_mode = { &cs42l43_dp0_bra_mode },
+	.dpn = {
+		{
+			/* UAJ_MIC */
+			.port = 2,
+			.source = &cs42l43_dpn
+		},
+		{
+			/* UAJ_SPK */
+			.port = 5,
+			.sink = &cs42l43_dpn
+		},
+		{
+			/* MIC */
+			.port = 1,
+			.sink = &cs42l43_dp1
+		},
+		{
+			/* SPK */
+			.port = 6,
+			.source = &cs42l43_dpn
+		}
+	}
+};
+
+static void soundwire_cs42l43_fill_ssdt(const struct device *dev)
+{
+	struct drivers_soundwire_cs42l43_config *config = dev->chip_info;
+	const char *scope = acpi_device_scope(dev);
+	struct acpi_dp *dsd;
+
+	if (!scope)
+		return;
+
+	acpigen_write_scope(scope);
+	acpigen_write_device(acpi_device_name(dev));
+
+	/* Set codec address IDs. */
+	cs42l43_address.link_id = dev->path.generic.id;
+	cs42l43_address.unique_id = dev->path.generic.subid;
+
+	acpigen_write_ADR_soundwire_device(&cs42l43_address);
+	acpigen_write_name_string("_DDN", config->desc ? : dev->chip_ops->name);
+	acpigen_write_name_string("_SUB", config->sub);
+	acpigen_write_STA(acpi_device_status(dev));
+
+	dsd = acpi_dp_new_table("_DSD");
+
+	soundwire_gen_codec(dsd, &cs42l43_codec, NULL);
+
+	acpi_dp_write(dsd);
+
+	acpigen_pop_len(); /* Device */
+	acpigen_pop_len(); /* Scope */
+}
+
+static const char *soundwire_cs42l43_acpi_name(const struct device *dev)
+{
+	struct drivers_soundwire_cs42l43_config *config = dev->chip_info;
+	if (config->acpi_name[0] != 0)
+		return config->acpi_name;
+	snprintf(config->acpi_name, sizeof(config->acpi_name), "SW%1X%1X",
+		 dev->path.generic.id, dev->path.generic.subid);
+	return config->acpi_name;
+}
+
+static struct device_operations soundwire_cs42l43_ops = {
+	.read_resources		= noop_read_resources,
+	.set_resources		= noop_set_resources,
+	.acpi_name		= soundwire_cs42l43_acpi_name,
+	.acpi_fill_ssdt		= soundwire_cs42l43_fill_ssdt,
+};
+
+static void soundwire_cs42l43_enable(struct device *dev)
+{
+	dev->ops = &soundwire_cs42l43_ops;
+}
+
+struct chip_operations drivers_soundwire_cs42l43_ops = {
+	.name = "Cirrus CS42L43 SoundWire Codec",
+	.enable_dev = soundwire_cs42l43_enable
+};
diff --git a/src/include/mipi/ids.h b/src/include/mipi/ids.h
index 3bab96cffb..7ae96c15b2 100644
--- a/src/include/mipi/ids.h
+++ b/src/include/mipi/ids.h
@@ -34,6 +34,7 @@
 
 #define MIPI_MFG_ID_CIRRUS			0x01fa
 #define MIPI_DEV_ID_CIRRUS_CS42L42		0x4242
+#define MIPI_DEV_ID_CIRRUS_CS42L43		0x4243
 #define MIPI_DEV_ID_CIRRUS_CS35L56		0x3556
 #define MIPI_DEV_ID_CIRRUS_CS35L57		0x3557
 #define MIPI_DEV_ID_CIRRUS_CS35L63		0x3563

From 78e7dcb152982a5789b40c46ebdc06c20329d539 Mon Sep 17 00:00:00 2001
From: Maciej Strozek <mstrozek@opensource.cirrus.com>
Date: Tue, 16 Sep 2025 14:01:12 +0100
Subject: [PATCH 2288/3886] drivers/soundwire/cs42l43: Add optional properties
 for controlling jack and accessory detect

CS42L43 contains a range of optional properties which control the
behaviour of jack and accessory detect, and are added here.

These properties are documented in the Linux kernel source code, in the
file:
linux/Documentation/devicetree/bindings/sound/cirrus,cs42l43.yaml
which contains names, descriptions, valid and default values.

Being optional, these properties will be ignored if not specified.

Change-Id: I53fbed81df9157022384d5879c9d9ed351641ab5
Signed-off-by: Maciej Strozek <mstrozek@opensource.cirrus.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89231
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
---
 src/drivers/soundwire/cs42l43/chip.h    | 138 ++++++++++++++++++++++++
 src/drivers/soundwire/cs42l43/cs42l43.c |  61 +++++++++++
 2 files changed, 199 insertions(+)

diff --git a/src/drivers/soundwire/cs42l43/chip.h b/src/drivers/soundwire/cs42l43/chip.h
index 35fdc93e14..3498733724 100644
--- a/src/drivers/soundwire/cs42l43/chip.h
+++ b/src/drivers/soundwire/cs42l43/chip.h
@@ -6,12 +6,150 @@
 #include <acpi/acpi.h>
 #include <acpi/acpi_device.h>
 #include <mipi/ids.h>
+#include <stdbool.h>
+
+enum cs42l43_detect_us {
+	DET_20_US = 20,
+	DET_100_US = 100,
+	DET_1_MS = 1000,
+	DET_10_MS = 10000,
+	DET_50_MS = 50000,
+	DET_75_MS = 75000,
+	DET_100_MS = 100000,
+	DET_200_MS = 200000,
+};
+
+enum cs42l43_db_ms {
+	DB_0_MS = -1, // To be handled as "0" in fill_ssdt function
+	DB_125_MS = 125,
+	DB_250_MS = 250,
+	DB_500_MS = 500,
+	DB_750_MS = 750,
+	DB_1000_MS = 1000,
+	DB_1250_MS = 1250,
+	DB_1500_MS = 1500,
+};
+
+enum cs42l43_bias_ramp_ms {
+	RAMP_10_MS = 10,
+	RAMP_40_MS = 40,
+	RAMP_90_MS = 90,
+	RAMP_170_MS = 170,
+};
+
+enum cs42l43_bias_sense {
+	BIAS_SENSE_OFF = -1,	// To be handled as "0" in fill_ssdt function
+	BIAS_SENSE_14_UA = 14,
+	BIAS_SENSE_24_UA = 24,
+	BIAS_SENSE_43_UA = 43,
+	BIAS_SENSE_52_UA = 52,
+	BIAS_SENSE_61_UA = 61,
+	BIAS_SENSE_71_UA = 71,
+	BIAS_SENSE_90_UA = 90,
+	BIAS_SENSE_99_UA = 99,
+};
 
 struct drivers_soundwire_cs42l43_config {
 	char acpi_name[ACPI_NAME_BUFFER_SIZE]; /* Set by the acpi_name ops */
 	const char *desc;
 
 	const char *sub; /* SUB ID to uniquely identify system */
+
+	/* Optional jack / accessory detect properties (from cirrus,cs42l43.yaml) */
+	/*
+	 * cirrus,bias-low: Select a 1.8V headset mic bias rather than 2.8V.
+	 * false: 2.8V, true: 1.8V
+	 * Default: false
+	 */
+	bool bias_low;
+	/*
+	 * cirrus,bias-sense-microamp: Current at which the headset micbias sense clamp will engage
+	 * 0 disables it.
+	 * Valid values: {0,14,24,43,52,61,71,90,99} (microamps)
+	 * Default: 14
+	 */
+	enum cs42l43_bias_sense bias_sense_microamp;
+	/*
+	 * cirrus,bias-ramp-ms: Time in milliseconds the hardware allows for the headset micbias to
+	 * ramp up.
+	 * Valid values: {10,40,90,170} (ms)
+	 * Default: 170
+	 */
+	enum cs42l43_bias_ramp_ms bias_ramp_ms;
+	/*
+	 * cirrus,detect-us: Time in microseconds the type detection will run for. Long values will
+	 * cause more audible effects, but give more accurate detection.
+	 * Valid values: {20,100,1000,10000,50000,75000,100000,200000} (us)
+	 * Default: 1000
+	 */
+	enum cs42l43_detect_us detect_us;
+	/*
+	 * cirrus,button-automute: Enable the hardware automuting of decimator 1 when a headset button is
+	 * pressed.
+	 */
+	bool button_automute;
+	/*
+	 * cirrus,buttons-ohms: Impedance in Ohms for each headset button, these should be listed in
+	 * ascending order.
+	 * Valid count: 1..6 entries each > 0 (Ohms)
+	 */
+	uint64_t buttons_ohms[6];
+	int buttons_ohms_count;
+	/*
+	 * cirrus,tip-debounce-ms: Software debounce on tip sense triggering in milliseconds.
+	 * Default: 0
+	 */
+	int tip_debounce_ms;
+	/*
+	 * cirrus,tip-invert: Indicates tip detect polarity, inverted implies open-circuit whilst the
+	 * jack is inserted.
+	 */
+	bool tip_invert;
+	/*
+	 * cirrus,tip-disable-pullup: Indicates if the internal pullup on the tip detect should be disabled.
+	 */
+	bool tip_disable_pullup;
+	/*
+	 * cirrus,tip-fall-db-ms: Time in milliseconds a falling edge on the tip detect should be hardware
+	 * debounced for. Note the falling edge is considered after the invert.
+	 * Valid values: {0,125,250,500,750,1000,1250,1500} (ms)
+	 * Default: 500
+	 */
+	enum cs42l43_db_ms tip_fall_db_ms;
+	/*
+	 * cirrus,tip-rise-db-ms: Time in milliseconds a rising edge on the tip detect should be hardware
+	 * debounced for. Note the rising edge is considered after the invert.
+	 * Valid values: {0,125,250,500,750,1000,1250,1500} (ms)
+	 * Default: 500
+	 */
+	enum cs42l43_db_ms tip_rise_db_ms;
+	/*
+	 * cirrus,use-ring-sense: Indicates if the ring sense should be used.
+	 */
+	bool use_ring_sense;
+	/*
+	 * cirrus,ring-invert: Indicates ring detect polarity, inverted implies open-circuit whilst the
+	 * jack is inserted.
+	 */
+	bool ring_invert;
+	/*
+	 * cirrus,ring-disable-pullup: Indicates if the internal pullup on the ring detect should be disabled.
+	 */
+	bool ring_disable_pullup;
+	/*
+	 * cirrus,ring-fall-db-ms: Time in milliseconds a falling edge on the ring detect should be hardware
+	 * debounced for. Note the falling edge is considered after the invert.
+	 * Valid values: {0,125,250,500,750,1000,1250,1500} (ms)
+	 * Default: 500
+	 */
+	enum cs42l43_db_ms ring_fall_db_ms;
+	/*
+	 * cirrus,ring-rise-db-ms: Time in milliseconds a rising edge on the ring detect should be hardware
+	 * debounced for. Note the rising edge is considered after the invert.
+	 * Valid values: {0,125,250,500,750,1000,1250,1500} (ms)
+	 * Default: 500
+	 */
+	enum cs42l43_db_ms ring_rise_db_ms;
 };
 
 #endif /* __DRIVERS_SOUNDWIRE_CS42L43_CHIP_H__ */
diff --git a/src/drivers/soundwire/cs42l43/cs42l43.c b/src/drivers/soundwire/cs42l43/cs42l43.c
index e39176e7b2..d6226d6fb9 100644
--- a/src/drivers/soundwire/cs42l43/cs42l43.c
+++ b/src/drivers/soundwire/cs42l43/cs42l43.c
@@ -7,6 +7,8 @@
 #include <device/soundwire.h>
 #include <mipi/ids.h>
 #include <stdio.h>
+#include <stdbool.h>
+#include <stddef.h>
 
 #include "chip.h"
 
@@ -130,6 +132,65 @@ static void soundwire_cs42l43_fill_ssdt(const struct device *dev)
 
 	dsd = acpi_dp_new_table("_DSD");
 
+	if (config->bias_low)
+		acpi_dp_add_integer(dsd, "cirrus,bias-low", 1);
+
+	if (config->bias_sense_microamp) {
+		if (config->bias_sense_microamp == BIAS_SENSE_OFF)
+			config->bias_sense_microamp = 0;
+		acpi_dp_add_integer(dsd, "cirrus,bias-sense-microamp", config->bias_sense_microamp);
+	}
+
+	if (config->bias_ramp_ms)
+		acpi_dp_add_integer(dsd, "cirrus,bias-ramp-ms", config->bias_ramp_ms);
+
+	if (config->detect_us)
+		acpi_dp_add_integer(dsd, "cirrus,detect-us", config->detect_us);
+
+	if (config->button_automute)
+		acpi_dp_add_integer(dsd, "cirrus,button-automute", 1);
+
+	if (config->buttons_ohms_count > 0)
+		acpi_dp_add_integer_array(dsd, "cirrus,buttons-ohms", config->buttons_ohms,
+					  config->buttons_ohms_count);
+
+	if (config->tip_debounce_ms)
+		acpi_dp_add_integer(dsd, "cirrus,tip-debounce-ms", config->tip_debounce_ms);
+
+	if (config->tip_invert)
+		acpi_dp_add_integer(dsd, "cirrus,tip-invert", 1);
+	if (config->tip_disable_pullup)
+		acpi_dp_add_integer(dsd, "cirrus,tip-disable-pullup", 1);
+
+	if (config->tip_fall_db_ms) {
+		if (config->tip_fall_db_ms == DB_0_MS)
+			config->tip_fall_db_ms = 0;
+		acpi_dp_add_integer(dsd, "cirrus,tip-fall-db-ms", config->tip_fall_db_ms);
+	}
+	if (config->tip_rise_db_ms) {
+		if (config->tip_rise_db_ms == DB_0_MS)
+			config->tip_rise_db_ms = 0;
+		acpi_dp_add_integer(dsd, "cirrus,tip-rise-db-ms", config->tip_rise_db_ms);
+	}
+
+	if (config->use_ring_sense)
+		acpi_dp_add_integer(dsd, "cirrus,use-ring-sense", 1);
+	if (config->ring_invert)
+		acpi_dp_add_integer(dsd, "cirrus,ring-invert", 1);
+	if (config->ring_disable_pullup)
+		acpi_dp_add_integer(dsd, "cirrus,ring-disable-pullup", 1);
+
+	if (config->ring_fall_db_ms) {
+		if (config->ring_fall_db_ms == DB_0_MS)
+			config->ring_fall_db_ms = 0;
+		acpi_dp_add_integer(dsd, "cirrus,ring-fall-db-ms", config->ring_fall_db_ms);
+	}
+	if (config->ring_rise_db_ms) {
+		if (config->ring_rise_db_ms == DB_0_MS)
+			config->ring_rise_db_ms = 0;
+		acpi_dp_add_integer(dsd, "cirrus,ring-rise-db-ms", config->ring_rise_db_ms);
+	}
+
 	soundwire_gen_codec(dsd, &cs42l43_codec, NULL);
 
 	acpi_dp_write(dsd);

From f04c45acee4a140463b657a451b74ff8f1343a87 Mon Sep 17 00:00:00 2001
From: Tongtong Pan <pantongtong@huaqin.corp-partner.google.com>
Date: Wed, 15 Oct 2025 21:15:18 +0800
Subject: [PATCH 2289/3886] mb/google/fatcat/var/lapis: enable CS35L56_FAMILY
 and CS42L43 driver options

Select the CS35L56_FAMILY and CS42L43 SoundWire driver configs in
Kconfig to ensure support amp cs35l56 and codec cs42l43 on lapis.

Scope (\_SB.PCI0.HDAS.SNDW)
    {
        Device (SW30)
        {
            Name (_ADR, 0x00033001FA424301)  // _ADR: Address
            Name (_DDN, "Headset Codec")  // _DDN: DOS Device Name
            Name (_SUB, "1337")  // _SUB: Subsystem ID
...
    {
        Device (SW20)
        {
            Name (_ADR, 0x00023001FA355601)  // _ADR: Address
            Name (_DDN, "Left Speaker Amp")  // _DDN: DOS Device Name
            Name (_SUB, "12345678")  // _SUB: Subsystem ID
...
        Device (SW21)
        {
            Name (_ADR, 0x00023101FA355601)  // _ADR: Address
            Name (_DDN, "Right Speaker Amp")  // _DDN: DOS Device Name
            Name (_SUB, "12345678")  // _SUB: Subsystem ID
...

BUG=b:444122406
TEST=emerge-fatcat coreboot and dump ssdt.asl

Change-Id: Icab7e38bb5c2733f1bd2a7ddd21b56ace01e64af
Signed-off-by: Tongtong Pan <pantongtong@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89593
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
---
 src/mainboard/google/fatcat/Kconfig | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/src/mainboard/google/fatcat/Kconfig b/src/mainboard/google/fatcat/Kconfig
index 01a1c7a767..3a54cc29e4 100644
--- a/src/mainboard/google/fatcat/Kconfig
+++ b/src/mainboard/google/fatcat/Kconfig
@@ -136,6 +136,8 @@ config BOARD_GOOGLE_KINMEN
 config BOARD_GOOGLE_LAPIS
 	select BOARD_GOOGLE_BASEBOARD_FATCAT
 	select DRIVERS_INTEL_TOUCH
+	select DRIVERS_SOUNDWIRE_CS35L56_FAMILY
+	select DRIVERS_SOUNDWIRE_CS42L43
 	select EC_GOOGLE_CHROMEEC_RTK
 	select EC_GOOGLE_CHROMEEC_LPC_GENERIC_MEMORY_RANGE
 	select FSP_UGOP_EARLY_SIGN_OF_LIFE

From 9f0f373ff90de012a272432ccfcd46c3272be35e Mon Sep 17 00:00:00 2001
From: Anand Vaikar <a.vaikar2021@gmail.com>
Date: Thu, 16 Oct 2025 16:21:52 +0530
Subject: [PATCH 2290/3886] mainboard/amd/crater: Select the option to keep the
 AMD ACP active in S3

Issue=ACP is not active in S3 state and audio playback doesnt work

Fix=Introduce a config option to control this setting.

TEST=Tested this in ACPI S3 state,by connecting an external CODEC and
transmitting a known pattern to the ACP via the I2S TDM controller RX
lines and ensuring that the sound is output to the speaker connected
to the CODEC via the TDM TX line.

Change-Id: Ifbd3e72a4d018e4a14d9459dd3a6804dd27050e4
Signed-off-by: Anand Vaikar <a.vaikar2021@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89610
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/amd/crater/Kconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/src/mainboard/amd/crater/Kconfig b/src/mainboard/amd/crater/Kconfig
index 136d1b834c..3312988926 100644
--- a/src/mainboard/amd/crater/Kconfig
+++ b/src/mainboard/amd/crater/Kconfig
@@ -18,6 +18,7 @@ config BOARD_AMD_CRATER_COMMON
 	select SPI_FLASH_EXIT_4_BYTE_ADDR_MODE
 	select SOC_AMD_COMMON_BLOCK_PSP_RPMC
 	select SOC_AMD_COMMON_BLOCK_PSP_SMI
+	select KEEP_ACP_RUNNING_IN_S3
 
 config BOARD_AMD_CRATER_RENOIR
 	select BOARD_AMD_CRATER_COMMON

From 1a0b7195f9c7c77f6cdf905a526c3c9e5f6dfe75 Mon Sep 17 00:00:00 2001
From: Daniel Peng <Daniel_Peng@pegatron.corp-partner.google.com>
Date: Mon, 13 Oct 2025 14:19:40 +0800
Subject: [PATCH 2291/3886] mb/google/nissa/var/glassway: Removed the flag of
 DB_1A for pmc_mux

Due to only 1A on DB, the test item of FAFT EC
firmware.DevInsertUSBScreen.insert_usb would be captured much error
message to detect C1 if set the flag.
And then missed to capture the correct message when running the test.
Therefore, removed the DB_1A for pmc_mux on daughter board to fix
the issue.

BUG=b:451436640
TEST=USE="${USE} -project_all project_craaskyu2" emerge-nirva \
     coreboot chromeos-zephyr chromeos-bootimage
     Confirm firmware.DevInsertUSBScreen.insert_usb PASS.

Change-Id: I6b1a3c99d422c99103818556365b0e5929a18dbf
Signed-off-by: Daniel Peng <Daniel_Peng@pegatron.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89538
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
---
 src/mainboard/google/brya/variants/glassway/overridetree.cb | 1 -
 1 file changed, 1 deletion(-)

diff --git a/src/mainboard/google/brya/variants/glassway/overridetree.cb b/src/mainboard/google/brya/variants/glassway/overridetree.cb
index 9d84273eac..f2662ebae2 100644
--- a/src/mainboard/google/brya/variants/glassway/overridetree.cb
+++ b/src/mainboard/google/brya/variants/glassway/overridetree.cb
@@ -623,7 +623,6 @@ chip soc/intel/alderlake
 						use tcss_usb3_port2 as usb3_port
 						device generic 1 alias conn1 on
 							probe DB_USB DB_1C
-							probe DB_USB DB_1A
 							probe DB_USB DB_1C_1A
 							probe DB_USB DB_1C_LTE
 						end

From 43df7b14ae760542ae6e85ab574c7ebd890927b2 Mon Sep 17 00:00:00 2001
From: John Su <john_su@compal.corp-partner.google.com>
Date: Wed, 8 Oct 2025 17:48:20 +0800
Subject: [PATCH 2292/3886] mb/var/uldrenite: Fix ISH UART port and VR
 configuration mismatch

During Uldrenite development, the ISH UART port design and VR settings
were changed, so the switching mechanism was implemented based on the
board ID. Uldrino adopts the latest Uldrenite design; however, its
board ID starts from 0. To resolve this issue, an additional FW_CONFIG
field is added to further distinguish between Uldrenite and Uldrino.

BUG=b:450182476
TEST=Verified the ISH log and used the servod board to dump the CPU
log for checking PMC Descriptor Record 7 at offset 0xC33.

Change-Id: Id24659d6f910de1d3da36c5da808fd768dbdbc37
Signed-off-by: John Su <john_su@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89457
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
---
 src/mainboard/google/brya/variants/uldrenite/variant.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/mainboard/google/brya/variants/uldrenite/variant.c b/src/mainboard/google/brya/variants/uldrenite/variant.c
index c096e9fbbf..6cbd2d2657 100644
--- a/src/mainboard/google/brya/variants/uldrenite/variant.c
+++ b/src/mainboard/google/brya/variants/uldrenite/variant.c
@@ -136,7 +136,7 @@ void fw_config_gpio_padbased_override(struct pad_config *padbased_table)
 	}
 
 	/* b/415605630: Support different ISH UART mappings according the board id */
-	if (board_version < 2) {
+	if (fw_config_probe(FW_CONFIG(SERIES, SERIES_ULDRENITE)) && board_version < 2) {
 		/* Override ISH UART0 to ISH UART1 */
 		gpio_padbased_override(padbased_table, switch_ish_uart1_pads,
 			ARRAY_SIZE(switch_ish_uart1_pads));
@@ -184,7 +184,7 @@ void variant_update_descriptor(void)
 	uint32_t board_version = board_id();
 
 	/* b/404126972: Only this phase has M/B with both FIVR and MBVR. */
-	if (board_version != 1)
+	if (fw_config_probe(FW_CONFIG(SERIES, SERIES_ULDRENITE)) && board_version != 1)
 		return;
 
 	/* VccanaVrLocation = "VCCANA is CPU FIVR" */

From 5c1a9fa809480215b792c67eb519dad1fafa56d5 Mon Sep 17 00:00:00 2001
From: Luca Lai <luca.lai@lcfc.corp-partner.google.com>
Date: Wed, 24 Sep 2025 20:33:09 +0800
Subject: [PATCH 2293/3886] mb/google/fatcat: Create ruby variant

Create the ruby variant of the fatcat reference board by copying
the fatcat files to a new directory named for the variant.

BUG=b:446771934
TEST=1. util/abuild/abuild -p none -t google/fatcat -x -a
        make sure the build includes GOOGLE_RUBY
     2. Run part_id_gen tool without any errors

Change-Id: Ie5f4a152d792f241a0044f18653b5363e1637b49
Signed-off-by: Luca Lai <luca.lai@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89327
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Bob Moragues <moragues@google.com>
Reviewed-by: Derek Huang <derekhuang@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/google/fatcat/Kconfig           |  14 +
 src/mainboard/google/fatcat/Kconfig.name      |   3 +
 .../baseboard/fatcat/include/baseboard/gpio.h |   5 +
 .../google/fatcat/variants/ruby/Makefile.mk   |   8 +
 .../google/fatcat/variants/ruby/fw_config.c   |  28 ++
 .../google/fatcat/variants/ruby/gpio.c        | 440 ++++++++++++++++++
 .../google/fatcat/variants/ruby/hda_verb.c    | 126 +++++
 .../fatcat/variants/ruby/include/variant/ec.h |   8 +
 .../variants/ruby/include/variant/gpio.h      |  11 +
 .../google/fatcat/variants/ruby/memory.c      | 100 ++++
 .../fatcat/variants/ruby/memory/Makefile.mk   |   7 +
 .../ruby/memory/dram_id.generated.txt         |   7 +
 .../variants/ruby/memory/mem_parts_used.txt   |  12 +
 .../fatcat/variants/ruby/overridetree.cb      | 302 ++++++++++++
 14 files changed, 1071 insertions(+)
 create mode 100644 src/mainboard/google/fatcat/variants/ruby/Makefile.mk
 create mode 100644 src/mainboard/google/fatcat/variants/ruby/fw_config.c
 create mode 100644 src/mainboard/google/fatcat/variants/ruby/gpio.c
 create mode 100644 src/mainboard/google/fatcat/variants/ruby/hda_verb.c
 create mode 100644 src/mainboard/google/fatcat/variants/ruby/include/variant/ec.h
 create mode 100644 src/mainboard/google/fatcat/variants/ruby/include/variant/gpio.h
 create mode 100644 src/mainboard/google/fatcat/variants/ruby/memory.c
 create mode 100644 src/mainboard/google/fatcat/variants/ruby/memory/Makefile.mk
 create mode 100644 src/mainboard/google/fatcat/variants/ruby/memory/dram_id.generated.txt
 create mode 100644 src/mainboard/google/fatcat/variants/ruby/memory/mem_parts_used.txt
 create mode 100644 src/mainboard/google/fatcat/variants/ruby/overridetree.cb

diff --git a/src/mainboard/google/fatcat/Kconfig b/src/mainboard/google/fatcat/Kconfig
index 3a54cc29e4..6d9c72a167 100644
--- a/src/mainboard/google/fatcat/Kconfig
+++ b/src/mainboard/google/fatcat/Kconfig
@@ -151,6 +151,16 @@ config BOARD_GOOGLE_MOONSTONE
 	select HAVE_SLP_S0_GATE
 	select MAINBOARD_HAS_GOOGLE_STRAUSS_KEYBOARD
 
+config BOARD_GOOGLE_MODEL_RUBY
+	def_bool n
+	select BOARD_GOOGLE_BASEBOARD_FATCAT
+	select FSP_UGOP_EARLY_SIGN_OF_LIFE
+	select HAVE_SLP_S0_GATE
+	select MAINBOARD_HAS_GOOGLE_STRAUSS_KEYBOARD
+
+config BOARD_GOOGLE_RUBY
+	select BOARD_GOOGLE_MODEL_RUBY
+
 if BOARD_GOOGLE_FATCAT_COMMON
 
 config BASEBOARD_DIR
@@ -190,6 +200,7 @@ config DRIVER_TPM_I2C_BUS
 	default 0x03 if BOARD_GOOGLE_MODEL_KINMEN
 	default 0x03 if BOARD_GOOGLE_LAPIS
 	default 0x03 if BOARD_GOOGLE_MOONSTONE
+	default 0x03 if BOARD_GOOGLE_MODEL_RUBY
 
 config HAVE_SLP_S0_GATE
 	def_bool n
@@ -208,6 +219,7 @@ config MAINBOARD_PART_NUMBER
 	default "Kinmen" if BOARD_GOOGLE_MODEL_KINMEN
 	default "Lapis" if BOARD_GOOGLE_LAPIS
 	default "Moonstone" if BOARD_GOOGLE_MOONSTONE
+	default "Ruby" if BOARD_GOOGLE_MODEL_RUBY
 
 config MEMORY_SOLDERDOWN
 	def_bool n
@@ -222,6 +234,7 @@ config TPM_TIS_ACPI_INTERRUPT
 	default 66 if BOARD_GOOGLE_MODEL_KINMEN # GPE0_DW2_02 (GPP_E02)
 	default 66 if BOARD_GOOGLE_LAPIS # GPE0_DW2_02 (GPP_E02)
 	default 66 if BOARD_GOOGLE_MOONSTONE # GPE0_DW2_02 (GPP_E02)
+	default 66 if BOARD_GOOGLE_MODEL_RUBY # GPE0_DW2_02 (GPP_E02)
 
 # FIXME: update as per board schematics
 config UART_FOR_CONSOLE
@@ -239,6 +252,7 @@ config VARIANT_DIR
 	default "kinmen" if BOARD_GOOGLE_MODEL_KINMEN
 	default "lapis" if BOARD_GOOGLE_LAPIS
 	default "moonstone" if BOARD_GOOGLE_MOONSTONE
+	default "ruby" if BOARD_GOOGLE_MODEL_RUBY
 
 config OVERRIDE_DEVICETREE
 	default "variants/\$(CONFIG_VARIANT_DIR)/overridetree.cb"
diff --git a/src/mainboard/google/fatcat/Kconfig.name b/src/mainboard/google/fatcat/Kconfig.name
index 46b7158971..61582c5102 100644
--- a/src/mainboard/google/fatcat/Kconfig.name
+++ b/src/mainboard/google/fatcat/Kconfig.name
@@ -43,3 +43,6 @@ config BOARD_GOOGLE_LAPIS
 
 config BOARD_GOOGLE_MOONSTONE
 	bool "-> Moonstone"
+
+config BOARD_GOOGLE_RUBY
+	bool "-> Ruby"
diff --git a/src/mainboard/google/fatcat/variants/baseboard/fatcat/include/baseboard/gpio.h b/src/mainboard/google/fatcat/variants/baseboard/fatcat/include/baseboard/gpio.h
index d3ec2fdb6f..88c8e0047d 100644
--- a/src/mainboard/google/fatcat/variants/baseboard/fatcat/include/baseboard/gpio.h
+++ b/src/mainboard/google/fatcat/variants/baseboard/fatcat/include/baseboard/gpio.h
@@ -47,6 +47,11 @@
  #define GPIO_PCH_WP	GPP_D02
 /* Used to gate SoC's SLP_S0# signal */
 #define GPIO_SLP_S0_GATE	GPP_V17
+#elif CONFIG(BOARD_GOOGLE_RUBY)
+ #define EC_SYNC_IRQ	GPP_E07_IRQ
+ #define GPIO_PCH_WP	GPP_D02
+/* Used to gate SoC's SLP_S0# signal */
+#define GPIO_SLP_S0_GATE	GPP_V17
 #endif
 
 #endif /* __BASEBOARD_GPIO_H__ */
diff --git a/src/mainboard/google/fatcat/variants/ruby/Makefile.mk b/src/mainboard/google/fatcat/variants/ruby/Makefile.mk
new file mode 100644
index 0000000000..6c0a1ae6fb
--- /dev/null
+++ b/src/mainboard/google/fatcat/variants/ruby/Makefile.mk
@@ -0,0 +1,8 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
+bootblock-y += gpio.c
+romstage-y += gpio.c
+romstage-y += memory.c
+romstage-$(CONFIG_FW_CONFIG) += fw_config.c
+ramstage-y += gpio.c
+ramstage-$(CONFIG_FW_CONFIG) += fw_config.c
diff --git a/src/mainboard/google/fatcat/variants/ruby/fw_config.c b/src/mainboard/google/fatcat/variants/ruby/fw_config.c
new file mode 100644
index 0000000000..8c207ed5e2
--- /dev/null
+++ b/src/mainboard/google/fatcat/variants/ruby/fw_config.c
@@ -0,0 +1,28 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <baseboard/variants.h>
+#include <console/console.h>
+#include <fw_config.h>
+#include <gpio.h>
+#include <inttypes.h>
+
+/* t: base table; o: override table */
+#define GPIO_PADBASED_OVERRIDE(t, o) gpio_padbased_override(t, o, ARRAY_SIZE(o))
+/* t: table */
+#define GPIO_CONFIGURE_PADS(t) gpio_configure_pads(t, ARRAY_SIZE(t))
+
+void fw_config_configure_pre_mem_gpio(void)
+{
+	if (!fw_config_is_provisioned()) {
+		printk(BIOS_WARNING, "FW_CONFIG is not provisioned, Exiting\n");
+		return;
+	}
+}
+
+void fw_config_gpio_padbased_override(struct pad_config *padbased_table)
+{
+	if (!fw_config_is_provisioned()) {
+		printk(BIOS_WARNING, "FW_CONFIG is not provisioned, Exiting\n");
+		return;
+	}
+}
diff --git a/src/mainboard/google/fatcat/variants/ruby/gpio.c b/src/mainboard/google/fatcat/variants/ruby/gpio.c
new file mode 100644
index 0000000000..f17fc8a883
--- /dev/null
+++ b/src/mainboard/google/fatcat/variants/ruby/gpio.c
@@ -0,0 +1,440 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <baseboard/gpio.h>
+#include <baseboard/variants.h>
+#include <boardid.h>
+#include <soc/gpio.h>
+
+/* Pad configuration in ramstage*/
+static const struct pad_config gpio_table[] = {
+	/* GPP_A00:     ESPI_IO0_EC_R */
+	/*  GPP_A00 : GPP_A00 ==> ESPI_IO0_EC_R configured on reset, do not touch */
+
+	/* GPP_A01:     ESPI_IO1_EC_R */
+	/*  GPP_A01 : GPP_A01 ==> ESPI_IO1_EC_R configured on reset, do not touch */
+
+	/* GPP_A02:     ESPI_IO2_EC_R */
+	/*  GPP_A02 : GPP_A02 ==> ESPI_IO2_EC_R configured on reset, do not touch */
+
+	/* GPP_A03:     ESPI_IO3_EC_R */
+	/*  GPP_A03 : GPP_A03 ==> ESPI_IO3_EC_R configured on reset, do not touch */
+
+	/* GPP_A04:     ESPI_CS0_EC_R_N */
+	/*  GPP_A04 : GPP_A04 ==> ESPI_CS0_HDR_L configured on reset, do not touch */
+
+	/* GPP_A05:     ESPI_CLK_EC_R */
+	/*  GPP_A05 : GPP_A05 ==> ESPI_CLK_HDR configured on reset, do not touch */
+
+	/* GPP_A06:     ESPI_RST_EC_R_N */
+	/*  GPP_A06 : GPP_A06 ==> ESPI_RST_HDR configured on reset, do not touch */
+
+	/* GPP_A08:     NC */
+	PAD_NC(GPP_A08, NONE),
+	/* GPP_A09:     NC */
+	PAD_NC(GPP_A09, NONE),
+	/* GPP_A10:     NC */
+	PAD_NC(GPP_A10, NONE),
+	/* GPP_A11:     TP */
+	PAD_NC(GPP_A11, NONE),
+	/* GPP_A12:     NC */
+	PAD_NC(GPP_A12, NONE),
+	/* GPP_A13:     MEM_STRAP_0 */
+	PAD_CFG_GPI(GPP_A13, NONE, DEEP),
+	/* GPP_A15:     SOC_GPP_A15 */
+	PAD_CFG_GPI(GPP_A15, NONE, DEEP),
+	/* GPP_A16:     BT_RF_KILL_N */
+	PAD_CFG_GPO(GPP_A16, 1, DEEP),
+	/* GPP_A17:     WIFI_RF_KILL_N */
+	PAD_CFG_GPO(GPP_A17, 1, DEEP),
+
+	/* GPP_B00:     USBC_SML_CLK_PD */
+	PAD_CFG_NF(GPP_B00, NONE, DEEP, NF1),
+	/* GPP_B01:     USBC_SML_DATA_PD */
+	PAD_CFG_NF(GPP_B01, NONE, DEEP, NF1),
+	/* GPP_B02:     NC */
+	PAD_NC(GPP_B02, NONE),
+	/* GPP_B03:     NC */
+	PAD_NC(GPP_B03, NONE),
+
+	/* GPP_B06:     NC */
+	PAD_NC(GPP_B06, NONE),
+	/* GPP_B07:     NC */
+	PAD_NC(GPP_B07, NONE),
+	/* GPP_B08:     NC */
+	PAD_NC(GPP_B08, NONE),
+	/* GPP_B09:     M2_GEN4_SSD_RESET_N */
+	PAD_CFG_GPO(GPP_B09, 1, PLTRST),
+	/* GPP_B10:     NC */
+	PAD_NC(GPP_B10, NONE),
+	/* GPP_B1:     NC */
+	PAD_NC(GPP_B11, NONE),
+	/* GPP_B12:     PM_SLP_S0_N */
+	PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1),
+	/* GPP_B13:     PLT_RST_N */
+	PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1),
+	/* GPP_B14:     MOD_TCSS2_DISP_HPD4 */
+	PAD_CFG_NF(GPP_B14, NONE, DEEP, NF2),
+	/* GPP_B15:     NC */
+	PAD_NC(GPP_B15, NONE),
+	/* GPP_B16:     GEN5_SSD_PWREN */
+	PAD_CFG_GPO(GPP_B16, 1, PLTRST),
+	/* GPP_B17:     NC */
+	PAD_NC(GPP_B17, NONE),
+	/* GPP_B18:     ISH_I2C2_SDA_SNSR_HDR */
+	/* NOTE: IOSSTAGE: 'Ignore' for S0ix */
+	PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_B18, NONE, DEEP, NF1),
+	/* GPP_B19:     ISH_I2C2_SCL_SNSR_HDR */
+	/* NOTE: IOSSTAGE: 'Ignore' for S0ix */
+	PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_B19, NONE, DEEP, NF1),
+	/* GPP_B20:     NC */
+	PAD_NC(GPP_B20, NONE),
+	/* GPP_B21:     TCP_RETIMER_FORCE_PWR */
+	PAD_CFG_GPO(GPP_B21, 0, DEEP),
+	/* GPP_B22:     NC */
+	PAD_NC(GPP_B22, NONE),
+	/* GPP_B24:     MEM_STRAP_3 */
+	PAD_CFG_GPI(GPP_B24, NONE, DEEP),
+	/* GPP_B25:     MEM_STRAP_2 */
+	PAD_CFG_GPI(GPP_B25, NONE, DEEP),
+
+	/* GPP_C00:     NC */
+	PAD_NC(GPP_C00, NONE),
+	/* GPP_C01:     NC */
+	PAD_NC(GPP_C01, NONE),
+	/* GPP_C02:     GPP_C2_STRAP */
+	PAD_CFG_GPI(GPP_C02, NONE, DEEP),
+	/* GPP_C03:     NC */
+	PAD_NC(GPP_C03, NONE),
+	/* GPP_C04:     NC */
+	PAD_NC(GPP_C04, NONE),
+	PAD_CFG_GPO(GPP_C05, 1, DEEP),
+	/* GPP_C06:     NC */
+	PAD_NC(GPP_C06, NONE),
+
+	/* GPP_C07:     MEM_CH_SEL */
+	PAD_CFG_GPI(GPP_C07, NONE, DEEP),
+	/* GPP_C08:     NC */
+	PAD_NC(GPP_C08, NONE),
+	/* GPP_C09:     NC */
+	PAD_NC(GPP_C09, NONE),
+	/* GPP_C10:     NC */
+	PAD_NC(GPP_C10, NONE),
+	/* GPP_C11:     NC */
+	PAD_NC(GPP_C11, NONE),
+	/* GPP_C12:     NC */
+	PAD_NC(GPP_C12, NONE),
+	/* GPP_C13:     NC */
+	PAD_NC(GPP_C13, NONE),
+	/* GPP_C14:     NC */
+	PAD_NC(GPP_C14, NONE),
+	/* GPP_C16:     TBT_LSX0_TXD  */
+	PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1),
+	/* GPP_C17:     TBT_LSX0_RXD  */
+	PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1),
+	/* GPP_C18:     NC */
+	PAD_NC(GPP_C18, NONE),
+	/* GPP_C19:     NC */
+	PAD_NC(GPP_C19, NONE),
+	/* GPP_C20:     MOD_TCSS1_LS_TX_DDC_SCL */
+	PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1),
+	/* GPP_C21:     MOD_TCSS1_LS_RX_DDC_SDA */
+	PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1),
+	/* GPP_C22:     MOD_TCSS2_LS_TX_DDC_SCL */
+	PAD_CFG_NF(GPP_C22, NONE, DEEP, NF2),
+	/* GPP_C23:     MOD_TCSS2_LS_RX_DDC_SDA */
+	PAD_CFG_NF(GPP_C23, NONE, DEEP, NF2),
+	/* GPP_D00:     TP */
+	PAD_NC(GPP_D00, NONE),
+	/* GPP_D02:     SOC_WP_OD */
+	PAD_CFG_GPI(GPP_D02, NONE, DEEP),
+	/* GPP_D03:     NC */
+	PAD_NC(GPP_D03, NONE),
+	/* GPP_D04:     TP */
+	PAD_NC(GPP_D04, NONE),
+	/* GPP_D07:     NC */
+	PAD_NC(GPP_D07, NONE),
+	/* GPP_D08:     NC */
+	PAD_NC(GPP_D08, NONE),
+	/* GPP_D09:     I2S_MCLK1_OUT */
+	PAD_CFG_NF(GPP_D09, NONE, DEEP, NF2),
+	/* GPP_D10:     HDA_BCLK */
+	PAD_CFG_NF(GPP_D10, NONE, DEEP, NF1),
+	/* GPP_D11:     HDA_SYNC */
+	PAD_CFG_NF(GPP_D11, NONE, DEEP, NF1),
+	/* GPP_D12:     HDA_SDO */
+	PAD_CFG_NF(GPP_D12, NONE, DEEP, NF1),
+	/* GPP_D13:     HDA_SDI0 */
+	PAD_CFG_NF(GPP_D13, NONE, DEEP, NF1),
+	/* GPP_D14:     NC */
+	PAD_NC(GPP_D14, NONE),
+	/* GPP_D15:     NC */
+	PAD_NC(GPP_D15, NONE),
+	/* GPP_D16:	TP*/
+	PAD_NC(GPP_D16, NONE),
+	/* GPP_D17:	TP*/
+	PAD_NC(GPP_D17, NONE),
+	/* GPP_D18:     CLKREQ6_X4_GEN4_M2_SSD_N */
+	PAD_CFG_NF(GPP_D18, NONE, DEEP, NF1),
+	/* GPP_D19:     NC */
+	PAD_NC(GPP_D19, NONE),
+	/* GPP_D20:     CSE_EARLY_SW */
+	PAD_CFG_GPI_SCI_HIGH(GPP_D20, NONE, DEEP, LEVEL),
+	/* GPP_D21:     NC */
+	PAD_NC(GPP_D21, NONE),
+	/* GPP_D22:     NC */
+	PAD_NC(GPP_D22, NONE),
+	/* GPP_D23:     NC */
+	PAD_NC(GPP_D23, NONE),
+	/* GPP_D24:     MEM_STRAP_1 */
+	PAD_CFG_GPI(GPP_D24, NONE, DEEP),
+	/* GPP_D25:     NC */
+	PAD_NC(GPP_D25, NONE),
+
+	/* GPP_E01:     NC */
+	PAD_NC(GPP_E01, NONE),
+	/* GPP_E02:     GSC_SOC_INT_ODL */
+	PAD_CFG_GPI_APIC_LOCK(GPP_E02, NONE, LEVEL, INVERT, LOCK_CONFIG),
+	/* GPP_E03:     NC */
+	PAD_NC(GPP_E03, NONE),
+	/* GPP_E05:     TCHSCR_RPT_EN */
+	PAD_CFG_GPO(GPP_E05, 1, DEEP),
+	/* GPP_E06:     SECURE_CAM_SW */
+	PAD_CFG_GPI_TRIG_OWN(GPP_E06, NONE, PLTRST, LEVEL, ACPI),
+	/* GPP_E07 : [] ==> EC_SOC_INT_ODL */
+	PAD_CFG_GPI_APIC_LOCK(GPP_E07, NONE, LEVEL, INVERT, LOCK_CONFIG),
+	/* GPP_E08:     NC */
+	PAD_NC(GPP_E08, NONE),
+	/* GPP_E10:     TP */
+	PAD_NC(GPP_E10, NONE),
+	/* GPP_E11:     NC */
+	PAD_NC(GPP_E11, NONE),
+	/* GPP_E12:     THC0_SPI1_IO_0_I2C4_SCL_TCH_PAD1*/
+	PAD_CFG_NF(GPP_E12, NONE, DEEP, NF3),
+	/* GPP_E13:     THC0_SPI1_IO_1_I2C4_SDA_TCH_PAD1 */
+	PAD_CFG_NF(GPP_E13, NONE, DEEP, NF3),
+	/* GPP_E14:     NC */
+	PAD_NC(GPP_E14, NONE),
+	/* GPP_E15:     NC */
+	PAD_NC(GPP_E15, NONE),
+	/* GPP_E16:     NC */
+	PAD_NC(GPP_E16, NONE),
+	/* GPP_E17:     NC */
+	PAD_NC(GPP_E17, NONE),
+	/* GPP_E18:     TCHPAD_INT# */
+	PAD_CFG_GPI_APIC(GPP_E18, NONE, PLTRST, LEVEL, INVERT),
+	/* GPP_E19:     FPMCU_PWREN */
+	PAD_CFG_GPO(GPP_E19, 1, DEEP),
+	/* GPP_E20:     NC */
+	PAD_NC(GPP_E20, NONE),
+	/* GPP_E21:     I2C_PMC_PD_INT_N */
+	PAD_CFG_NF(GPP_E21, NONE, DEEP, NF1),
+	/* GPP_E22:     NC */
+	PAD_NC(GPP_E22, NONE),
+
+	/* GPP_F00:     M.2_CNV_BRI_DT_BT_UART2_RTS_N */
+	/* NOTE: IOSSTAGE: 'Ignore' for S0ix */
+	PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_F00, NONE, DEEP, NF1),
+	/* GPP_F01:     M.2_CNV_BRI_RSP_BT_UART2_RXD */
+	/* NOTE: IOSSTAGE: 'Ignore' for S0ix */
+	PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_F01, NONE, DEEP, NF1),
+	/* GPP_F02:     M.2_CNV_RGI_DT_BT_UART2_TXD */
+	/* NOTE: IOSSTAGE: 'Ignore' for S0ix */
+	PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_F02, NONE, DEEP, NF1),
+	/* GPP_F03:     M.2_CNV_RGI_RSP_BT_UART2_CTS_N */
+	/* NOTE: IOSSTAGE: 'Ignore' for S0ix */
+	PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_F03, NONE, DEEP, NF1),
+	/* GPP_F04:     CNV_RF_RESET_R_N */
+	/* NOTE: IOSSTAGE: 'Ignore' for S0ix */
+	PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_F04, NONE, DEEP, NF1),
+	/* GPP_F05:     CRF_CLKREQ_R */
+	/* NOTE: IOSSTAGE: 'Ignore' for S0ix */
+	PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_F05, NONE, DEEP, NF3),
+	/* GPP_F06:     NC */
+	PAD_NC(GPP_F06, NONE),
+	/* GPP_F07:     NC */
+	PAD_NC(GPP_F07, NONE),
+	/* GPP_F08:     EN_TCHSCR_PWR */
+	PAD_CFG_GPO(GPP_F08, 1, DEEP),
+	/* GPP_F09:     NC */
+	PAD_NC(GPP_F09, NONE),
+	/* GPP_F10:     ISH_GP_6_SNSR_HDR */
+	PAD_CFG_NF(GPP_F10, NONE, DEEP, NF8),
+	/* GPP_F11:     NC */
+	PAD_NC(GPP_F11, NONE),
+	/* GPP_F12:     TCHSCR_I2C5_SCL */
+	PAD_CFG_NF(GPP_F12, NONE, DEEP, NF8),
+	/* GPP_F13:     TCHSCR_I2C5_SDA */
+	PAD_CFG_NF(GPP_F13, NONE, DEEP, NF8),
+	/* GPP_F14:     NC */
+	PAD_NC(GPP_F14, NONE),
+	/* GPP_F15:     NC */
+	PAD_NC(GPP_F15, NONE),
+	/* GPP_F16:     TCHSCR_RST_L */
+	PAD_CFG_GPO(GPP_F16, 1, DEEP),
+	/* GPP_F17:     NC */
+	PAD_NC(GPP_F17, NONE),
+	/* GPP_F18:     TCHSCR_INT_L */
+	PAD_CFG_GPI_APIC(GPP_F18, NONE, PLTRST, LEVEL, NONE),
+	/* GPP_F19:     EN_UCAM_SENR_PWR */
+	PAD_CFG_GPO(GPP_F19, 0, PLTRST),
+	/* GPP_F20:     NC */
+	PAD_NC(GPP_F20, NONE),
+	/* GPP_F22:     NC */
+	PAD_NC(GPP_F22, NONE),
+	/* GPP_F23:     NC */
+	PAD_NC(GPP_F23, NONE),
+
+	/* GPP_H00:     GPP_H0_STRAP */
+	PAD_CFG_GPO(GPP_H00, 1, PLTRST),
+	/* GPP_H01:     GPP_H1_STRAP */
+	PAD_CFG_GPO(GPP_H01, 0, PLTRST),
+	/* GPP_H02:     GPP_H2_STRAP */
+	PAD_CFG_GPO(GPP_H02, 1, PLTRST),
+	/* GPP_H03:     SOC_SPKR_INT_ODL */
+	PAD_CFG_GPI(GPP_H03, NONE, DEEP),
+	/* GPP_H04:     NC */
+	PAD_NC(GPP_H04, NONE),
+	/* GPP_H05:     NC */
+	PAD_NC(GPP_H05, NONE),
+	/* GPP_H06:     I2C3_SDA_PSS */
+	PAD_CFG_NF(GPP_H06, NONE, DEEP, NF1),
+	/* GPP_H07:     I2C3_SCL_PSS */
+	PAD_CFG_NF(GPP_H07, NONE, DEEP, NF1),
+	/* GPP_H08:     UART0_BUF_RXD */
+	PAD_CFG_NF(GPP_H08, NONE, DEEP, NF1),
+	/* GPP_H09:     UART0_BUF_TXD */
+	PAD_CFG_NF(GPP_H09, NONE, DEEP, NF1),
+	/* GPP_H10:     NC */
+	PAD_NC(GPP_H10, NONE),
+	/* GPP_H11:     NC */
+	PAD_NC(GPP_H11, NONE),
+	/* GPP_H13:     CPU_C10_GATE_N_R */
+	PAD_CFG_NF(GPP_H13, NONE, DEEP, NF1),
+	/* GPP_H14:     NC */
+	PAD_NC(GPP_H14, NONE),
+	/* GPP_H15:     NC */
+	PAD_NC(GPP_H15, NONE),
+	/* GPP_H16:     NC */
+	PAD_NC(GPP_H16, NONE),
+	/* GPP_H17:     SOC_HP_INT_L */
+	PAD_CFG_GPI(GPP_H17, NONE, DEEP),
+	/* GPP_H19:     I3C0_SDA_HDR */
+	PAD_CFG_NF(GPP_H19, NONE, DEEP, NF2),
+	/* GPP_H20:     I3C0_SCL_HDR */
+	PAD_CFG_NF(GPP_H20, NONE, DEEP, NF2),
+	/* GPP_H21:     CAL_SDA_IN */
+	PAD_CFG_NF(GPP_H21, NONE, DEEP, NF1),
+	/* GPP_H22:     CAL_SCL_IN */
+	PAD_CFG_NF(GPP_H22, NONE, DEEP, NF1),
+
+	/* GPP_S00:     I2S_SPK_AUDIO_R_TX */
+	PAD_CFG_NF(GPP_S00, NONE, DEEP, NF6),
+	/* GPP_S01:     I2S_SPK_AUDIO_R_RX */
+	PAD_CFG_NF(GPP_S01, NONE, DEEP, NF6),
+	/* GPP_S02:     I2S_SPK_BCLK*/
+	PAD_CFG_NF(GPP_S02, NONE, DEEP, NF6),
+	/* GPP_S03:     I2S_SPK_LRCK */
+	PAD_CFG_NF(GPP_S03, NONE, DEEP, NF6),
+	/* GPP_S04:	DMIC_CLK_A0 */
+	PAD_CFG_NF(GPP_S04, NONE, DEEP, NF5),
+	/* GPP_S05:	DMIC_DATA_0 */
+	PAD_CFG_NF(GPP_S05, NONE, DEEP, NF5),
+	/* GPP_S06:     NC */
+	PAD_NC(GPP_S06, NONE),
+	/* GPP_S07:     NC */
+	PAD_NC(GPP_S07, NONE),
+
+	/* GPP_V00:     PM_BATLOW_N */
+	PAD_CFG_NF(GPP_V00, NONE, DEEP, NF1),
+	/* GPP_V01:     BC_ACOK_MCP */
+	PAD_CFG_NF(GPP_V01, NONE, DEEP, NF1),
+	/* GPP_V02:     LANWAKE_N_R */
+	PAD_CFG_NF(GPP_V02, NONE, DEEP, NF1),
+	/* GPP_V03:     PWRBTN_MCP_N */
+	PAD_CFG_NF(GPP_V03, NONE, DEEP, NF1),
+	/* GPP_V04:     PM_SLP_S3_N */
+	PAD_CFG_NF(GPP_V04, NONE, DEEP, NF1),
+	/* GPP_V05:     PM_SLP_S4_N */
+	PAD_CFG_NF(GPP_V05, NONE, DEEP, NF1),
+	/* GPP_V06:     PM_SLP_A_N */
+	PAD_CFG_NF(GPP_V06, NONE, DEEP, NF1),
+	/* GPP_V07:     SUSCLK */
+	PAD_CFG_NF(GPP_V07, NONE, DEEP, NF1),
+	/* GPP_V08:     SLP_WLAN_N */
+	PAD_CFG_NF(GPP_V08, NONE, DEEP, NF1),
+	/* GPP_V09:     PM_SLP_S5_N */
+	PAD_CFG_NF(GPP_V09, NONE, DEEP, NF1),
+	/* GPP_V10:     LANPHYPC_R_N */
+	PAD_CFG_NF(GPP_V10, NONE, DEEP, NF1),
+	/* GPP_V11:     PM_SLP_LAN_N */
+	PAD_CFG_NF(GPP_V11, NONE, DEEP, NF1),
+	/* GPP_V12:     WAKE_N */
+	PAD_CFG_NF(GPP_V12, NONE, DEEP, NF1),
+	/* GPP_V13:     GPP_V13_CATERR_N */
+	PAD_CFG_NF(GPP_V13, NONE, DEEP, NF1),
+	/* GPP_V14:     GPP_V14_FORCEPR_N */
+	PAD_CFG_NF(GPP_V14, NONE, DEEP, NF1),
+	/* GPP_V15:     GPP_V15_THERMTRIP_N */
+	PAD_CFG_NF(GPP_V15, NONE, DEEP, NF1),
+	/* GPP_V16:     GPP_V16_VCCST_EN */
+	PAD_CFG_NF(GPP_V16, NONE, DEEP, NF1),
+	/* GPP_V17:     SLP_S0_GATE_R */
+	PAD_CFG_GPO(GPP_V17, 1, PLTRST),
+};
+
+/* Early pad configuration in bootblock */
+static const struct pad_config early_gpio_table[] = {
+	/* GPP_B14:     MOD_TCSS2_DISP_HPD4 */
+	PAD_CFG_NF(GPP_B14, NONE, DEEP, NF2),
+	/* GPP_C22:     MOD_TCSS2_LS_TX_DDC_SCL */
+	PAD_CFG_NF(GPP_C22, NONE, DEEP, NF2),
+	/* GPP_C23:     MOD_TCSS2_LS_RX_DDC_SDA */
+	PAD_CFG_NF(GPP_C23, NONE, DEEP, NF2),
+	/* GPP_H08:     UART0_BUF_RXD */
+	PAD_CFG_NF(GPP_H08, NONE, DEEP, NF1),
+	/* GPP_H09:     UART0_BUF_TXD */
+	PAD_CFG_NF(GPP_H09, NONE, DEEP, NF1),
+	/* GPP_H06: I2C3_SDA_PSS */
+	PAD_CFG_NF(GPP_H06, NONE, DEEP, NF1),
+	/* GPP_H07: I2C3_SCL_PSS */
+	PAD_CFG_NF(GPP_H07, NONE, DEEP, NF1),
+	/* GPP_E02: GSC_SOC_INT_ODL */
+	PAD_CFG_GPI_APIC(GPP_E02, NONE, PLTRST, LEVEL, INVERT),
+};
+
+/* Pad configuration in romstage */
+static const struct pad_config romstage_gpio_table[] = {
+	/* GPP_B16:     EN_PP3300_SSD */
+	PAD_CFG_GPO(GPP_B16, 1, PLTRST),
+	/* GPP_B09:     SSD_GEN4_PERST_L */
+	PAD_CFG_GPO(GPP_B09, 1, PLTRST),
+};
+
+const struct pad_config *variant_gpio_table(size_t *num)
+{
+	*num = ARRAY_SIZE(gpio_table);
+	return gpio_table;
+}
+
+const struct pad_config *variant_early_gpio_table(size_t *num)
+{
+	*num = ARRAY_SIZE(early_gpio_table);
+	return early_gpio_table;
+}
+
+/* Create the stub for romstage gpio, typically use for power sequence */
+const struct pad_config *variant_romstage_gpio_table(size_t *num)
+{
+	*num = ARRAY_SIZE(romstage_gpio_table);
+	return romstage_gpio_table;
+}
+
+static const struct cros_gpio cros_gpios[] = {
+	CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE0_NAME),
+	CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE1_NAME),
+	CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE2_NAME),
+	CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE3_NAME),
+	CROS_GPIO_WP_AH(GPIO_PCH_WP, CROS_GPIO_DEVICE4_NAME),
+};
+
+DECLARE_CROS_GPIOS(cros_gpios);
diff --git a/src/mainboard/google/fatcat/variants/ruby/hda_verb.c b/src/mainboard/google/fatcat/variants/ruby/hda_verb.c
new file mode 100644
index 0000000000..2f703b78ee
--- /dev/null
+++ b/src/mainboard/google/fatcat/variants/ruby/hda_verb.c
@@ -0,0 +1,126 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <device/azalia_device.h>
+
+const u32 cim_verb_data[] = {
+	/* coreboot specific header */
+	0x10ec0256,	/* Codec Vendor / Device ID: Realtek ALC256 */
+	0x10ec12ac,	/* Subsystem ID */
+	0x00000013,	/* Number of jacks (NID entries) */
+
+	AZALIA_RESET(0x1),
+	/* NID 0x01, HDA Codec Subsystem ID Verb Table */
+	AZALIA_SUBVENDOR(0, 0x10ec12ac),
+
+	/* Pin Widget Verb Table */
+	/*
+	 * DMIC
+	 * Requirement is to use PCH DMIC. Hence,
+	 * commented out codec's Internal DMIC.
+	 * AZALIA_PIN_CFG(0, 0x12, 0x90A60130),
+	 * AZALIA_PIN_CFG(0, 0x13, 0x40000000),
+	 */
+	/* Pin widget 0x14 - Front (Port-D) */
+	AZALIA_PIN_CFG(0, 0x14, 0x90170110),
+	/* Pin widget 0x18 - NPC */
+	AZALIA_PIN_CFG(0, 0x18, 0x411111F0),
+	/* Pin widget 0x19 - MIC2 (Port-F) */
+	AZALIA_PIN_CFG(0, 0x19, 0x04A11040),
+	/* Pin widget 0x1A - LINE1 (Port-C) */
+	AZALIA_PIN_CFG(0, 0x1a, 0x411111F0),
+	/* Pin widget 0x1B - NPC */
+	AZALIA_PIN_CFG(0, 0x1b, 0x411111F0),
+	/* Pin widget 0x1D - BEEP-IN */
+	AZALIA_PIN_CFG(0, 0x1d, 0x40610041),
+	/* Pin widget 0x1E - NPC */
+	AZALIA_PIN_CFG(0, 0x1e, 0x411111F0),
+	/* Pin widget 0x21 - HP1-OUT (Port-I) */
+	AZALIA_PIN_CFG(0, 0x21, 0x04211020),
+	/*
+	 * Widget node 0x20 - 1
+	 * Codec hidden reset and speaker power 2W/4ohm
+	 */
+	0x0205001A,
+	0x0204C003,
+	0x02050038,
+	0x02047901,
+	/*
+	 * Widget node 0x20 - 2
+	 * Class D power on Reset
+	 */
+	0x0205003C,
+	0x02040354,
+	0x0205003C,
+	0x02040314,
+	/*
+	 * Widget node 0x20 - 3
+	 * Disable AGC and set AGC limit to -1.5dB
+	 */
+	0x02050016,
+	0x02040C50,
+	0x02050012,
+	0x0204EBC1,
+	/*
+	 * Widget node 0x20 - 4
+	 * Set AGC Post gain +1.5dB then Enable AGC
+	 */
+	0x02050013,
+	0x02044023,
+	0x02050016,
+	0x02040E50,
+	/*
+	 * Widget node 0x20 - 5
+	 * Silence detector enabling + Set EAPD to verb control
+	 */
+	0x02050037,
+	0x0204FE15,
+	0x02050010,
+	0x02040020,
+	/*
+	 * Widget node 0x20 - 6
+	 * Silence data mode Threshold (-90dB)
+	 */
+	0x02050030,
+	0x0204A000,
+	0x0205001B,
+	0x02040A4B,
+	/*
+	 * Widget node 0x20 - 7
+	 * Default setting-1
+	 */
+	0x05750003,
+	0x05740DA3,
+	0x02050046,
+	0x02040004,
+	/*
+	 * Widget node 0x20 - 8
+	 * support 1 pin detect two port
+	 */
+	0x02050009,
+	0x0204E003,
+	0x0205000A,
+	0x02047770,
+	/*
+	 * Widget node 0x20 - 9
+	 * To set LDO1/LDO2 as default
+	 */
+	0x02050008,
+	0x02046A0C,
+	0x02050008,
+	0x02046A0C,
+};
+
+const u32 pc_beep_verbs[] = {
+	/* Dos beep path - 1 */
+	0x01470C00,
+	0x02050036,
+	0x02047151,
+	0x01470740,
+	/* Dos beep path - 2 */
+	0x0143b000,
+	0x01470C02,
+	0x01470C02,
+	0x01470C02,
+};
+
+AZALIA_ARRAY_SIZES;
diff --git a/src/mainboard/google/fatcat/variants/ruby/include/variant/ec.h b/src/mainboard/google/fatcat/variants/ruby/include/variant/ec.h
new file mode 100644
index 0000000000..4fc0622f15
--- /dev/null
+++ b/src/mainboard/google/fatcat/variants/ruby/include/variant/ec.h
@@ -0,0 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#ifndef MAINBOARD_EC_H
+#define MAINBOARD_EC_H
+
+#include <baseboard/ec.h>
+
+#endif /* MAINBOARD_GPIO_H */
diff --git a/src/mainboard/google/fatcat/variants/ruby/include/variant/gpio.h b/src/mainboard/google/fatcat/variants/ruby/include/variant/gpio.h
new file mode 100644
index 0000000000..cced66807a
--- /dev/null
+++ b/src/mainboard/google/fatcat/variants/ruby/include/variant/gpio.h
@@ -0,0 +1,11 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#ifndef __MAINBOARD_GPIO_H__
+#define __MAINBOARD_GPIO_H__
+
+#include <baseboard/gpio.h>
+
+/* EC wake is LAN_WAKE# which is a special DeepSX wake pin */
+#define GPE_EC_WAKE	GPE0_LAN_WAK
+
+#endif /* __MAINBOARD_GPIO_H__ */
diff --git a/src/mainboard/google/fatcat/variants/ruby/memory.c b/src/mainboard/google/fatcat/variants/ruby/memory.c
new file mode 100644
index 0000000000..b8b00f7f51
--- /dev/null
+++ b/src/mainboard/google/fatcat/variants/ruby/memory.c
@@ -0,0 +1,100 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <baseboard/variants.h>
+#include <soc/romstage.h>
+#include <soc/meminit.h>
+
+static const struct mb_cfg lp5_mem_config = {
+	.type = MEM_TYPE_LP5X,
+
+	.lpx_dq_map = {
+		.ddr0 = {
+			.dq0 = {  13,  14,  12,  15, 11,  10,  8,  9, },
+			.dq1 = {  7,  5,  4,  6,  0,  3,  1,  2 },
+		},
+		.ddr1 = {
+			.dq0 = {  1,  3,  0,  2,  7,  4,  6,  5, },
+			.dq1 = {  12,  13,  14,  15,  11,  10,  9,  8 },
+		},
+		.ddr2 = {
+			.dq0 = {  0,  2,  1,  3,  6,  4,  7,  5 },
+			.dq1 = {  14,  13,  15,  12,  8,  11,  10,  9, },
+		},
+		.ddr3 = {
+			.dq0 = {  6,  5,  7,  4,  2,  3,  1,  0, },
+			.dq1 = {  10,  8,  11,  9,  12,  15,  13,  14 },
+		},
+		.ddr4 = {
+			.dq0 = {  2,  1,  3,  0,  4,  7,  5,  6 },
+			.dq1 = {  15,  14,  12,  13,  9,  11,  10,  8, },
+		},
+		.ddr5 = {
+			.dq0 = {  6,  5,  7,  4,  3,  1,  0,  2, },
+			.dq1 = {  10,  9,  11,  8,  13,  14,  12,  15 },
+		},
+		.ddr6 = {
+			.dq0 = {  9,  10,  11,  8,  14,  12,  13, 15, },
+			.dq1 = {  0,  1,  2,  3,  5,  7,  4,  6 },
+		},
+		.ddr7 = {
+			.dq0 = {  0,  1,  2,  3,  7,  5,  6,  4, },
+			.dq1 = {  14,  13,  15,  12,  10,  8,  11,  9 },
+		},
+	},
+
+	.lpx_dqs_map = {
+		.ddr0 = { .dqs0 = 1, .dqs1 = 0 },
+		.ddr1 = { .dqs0 = 0, .dqs1 = 1 },
+		.ddr2 = { .dqs0 = 0, .dqs1 = 1 },
+		.ddr3 = { .dqs0 = 0, .dqs1 = 1 },
+		.ddr4 = { .dqs0 = 0, .dqs1 = 1 },
+		.ddr5 = { .dqs0 = 0, .dqs1 = 1 },
+		.ddr6 = { .dqs0 = 1, .dqs1 = 0 },
+		.ddr7 = { .dqs0 = 0, .dqs1 = 1 }
+	},
+
+	.ect = true, /* Early Command Training */
+
+	.user_bd = BOARD_TYPE_ULT_ULX,
+
+	.lp5x_config = {
+		.ccc_config = 0xFF,
+	},
+};
+
+const struct mb_cfg *variant_memory_params(void)
+{
+	return &lp5_mem_config;
+}
+
+void variant_get_spd_info(struct mem_spd *spd_info)
+{
+	spd_info->topo = MEM_TOPO_MEMORY_DOWN;
+	spd_info->cbfs_index = variant_memory_sku();
+
+}
+
+int variant_memory_sku(void)
+{
+	/*
+	 * Memory configuration board straps
+	 * GPIO_MEM_CONFIG_0	GPP_A13
+	 * GPIO_MEM_CONFIG_1	GPP_D24
+	 * GPIO_MEM_CONFIG_2	GPP_B25
+	 * GPIO_MEM_CONFIG_3    GPP_B24
+	 */
+	gpio_t spd_gpios[] = {
+		GPP_A13,
+		GPP_D24,
+		GPP_B25,
+		GPP_B24,
+	};
+
+	return gpio_base2_value(spd_gpios, ARRAY_SIZE(spd_gpios));
+}
+
+bool variant_is_half_populated(void)
+{
+	/* GPIO_MEM_CH_SEL GPP_C07 */
+	return gpio_get(GPP_C07);
+}
diff --git a/src/mainboard/google/fatcat/variants/ruby/memory/Makefile.mk b/src/mainboard/google/fatcat/variants/ruby/memory/Makefile.mk
new file mode 100644
index 0000000000..e58d787420
--- /dev/null
+++ b/src/mainboard/google/fatcat/variants/ruby/memory/Makefile.mk
@@ -0,0 +1,7 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+# This is an auto-generated file. Do not edit!!
+# Generated by:
+# /tmp/go-build4042912853/b001/exe/part_id_gen PTL lp5 src/mainboard/google/fatcat/variants/ruby/memory/ src/mainboard/google/fatcat/variants/ruby/memory/mem_parts_used.txt
+
+SPD_SOURCES =
+SPD_SOURCES += spd/lp5/set-0/spd-11.hex      # ID = 0(0b0000)  Parts = H58G56CK8BX146
diff --git a/src/mainboard/google/fatcat/variants/ruby/memory/dram_id.generated.txt b/src/mainboard/google/fatcat/variants/ruby/memory/dram_id.generated.txt
new file mode 100644
index 0000000000..4248666b32
--- /dev/null
+++ b/src/mainboard/google/fatcat/variants/ruby/memory/dram_id.generated.txt
@@ -0,0 +1,7 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+# This is an auto-generated file. Do not edit!!
+# Generated by:
+# /tmp/go-build4042912853/b001/exe/part_id_gen PTL lp5 src/mainboard/google/fatcat/variants/ruby/memory/ src/mainboard/google/fatcat/variants/ruby/memory/mem_parts_used.txt
+
+DRAM Part Name                 ID to assign
+H58G56CK8BX146                 0 (0000)
diff --git a/src/mainboard/google/fatcat/variants/ruby/memory/mem_parts_used.txt b/src/mainboard/google/fatcat/variants/ruby/memory/mem_parts_used.txt
new file mode 100644
index 0000000000..49d566c412
--- /dev/null
+++ b/src/mainboard/google/fatcat/variants/ruby/memory/mem_parts_used.txt
@@ -0,0 +1,12 @@
+# This is a CSV file containing a list of memory parts used by this variant.
+# One part per line with an optional fixed ID in column 2.
+# Only include a fixed ID if it is required for legacy reasons!
+# Generated IDs are dependent on the order of parts in this file,
+# so new parts must always be added at the end of the file!
+#
+# Generate an updated Makefile.mk and dram_id.generated.txt by running the
+# part_id_gen tool from util/spd_tools.
+# See util/spd_tools/README.md for more details and instructions.
+
+# Part Name
+H58G56CK8BX146
diff --git a/src/mainboard/google/fatcat/variants/ruby/overridetree.cb b/src/mainboard/google/fatcat/variants/ruby/overridetree.cb
new file mode 100644
index 0000000000..fe8c7eaadc
--- /dev/null
+++ b/src/mainboard/google/fatcat/variants/ruby/overridetree.cb
@@ -0,0 +1,302 @@
+chip soc/intel/pantherlake
+
+	# The initial version temporarily uses the PTL-H,
+	# but the thermal design is based on the PTL-U.
+	# Apply PTL-U's thermal settings here to avoid thermal issues.
+	register "power_limits_config[PTL_CORE_1]" = "{
+		.tdp_pl1_override = 15,
+		.tdp_pl2_override = 55,
+		.tdp_pl4 = 152,
+	}"
+
+	register "power_limits_config[PTL_CORE_2]" = "{
+		.tdp_pl1_override = 15,
+		.tdp_pl2_override = 55,
+		.tdp_pl4 = 152,
+	}"
+
+	register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC_SKIP)"	# USB2_C0
+	register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC_SKIP)"	# USB2_C1
+	register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # USB HUB (USB2 Camera)
+	register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)" # Type-A Port A1 (DB)
+	register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" # Fingerprint
+
+	register "usb3_ports[0]" = "USB3_PORT_EMPTY" # no use
+	register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB3.2 Type-A (DB)
+
+	register "tcss_ports[0]" = "TCSS_PORT_DEFAULT(OC_SKIP)" # USB3_C0
+	register "tcss_ports[2]" = "TCSS_PORT_DEFAULT(OC_SKIP)" # USB3_C1
+
+	register "tcss_cap_policy[0]" = "TCSS_TYPE_C_PORT_FULL_FUN"
+	register "tcss_cap_policy[2]" = "TCSS_TYPE_C_PORT_FULL_FUN"
+
+	# Enable EDP in PortA
+	register "ddi_port_A_config" = "1"
+	register "ddi_ports_config" = "{
+                [DDI_PORT_A] = DDI_ENABLE_HPD,
+	}"
+
+	# Enable CNVi Wi-Fi and Bluetooth
+	register "cnvi_wifi_core" = "true"
+	register "cnvi_bt_core" = "true"
+
+	register "serial_io_i2c_mode" = "{
+		[PchSerialIoIndexI2C0]  = PchSerialIoPci,
+		[PchSerialIoIndexI2C1] = PchSerialIoDisabled,
+		[PchSerialIoIndexI2C2] = PchSerialIoDisabled,
+		[PchSerialIoIndexI2C3]  = PchSerialIoPci,
+		[PchSerialIoIndexI2C4]  = PchSerialIoPci,
+		[PchSerialIoIndexI2C5]  = PchSerialIoPci,
+	}"
+
+	register "serial_io_gspi_mode" = "{
+		[PchSerialIoIndexGSPI0] = PchSerialIoPci,
+		[PchSerialIoIndexGSPI1] = PchSerialIoDisabled,
+		[PchSerialIoIndexGSPI0A] = PchSerialIoDisabled,
+	}"
+
+	# Intel Common SoC Config
+	#+-------------------+---------------------------+
+	#| Field             |  Value                    |
+	#+-------------------+---------------------------+
+	#| I2C0              | Audio ALC5682             |
+	#| I2C1              | PMIC                      |
+	#| I2C2              | ISH_I2C SENSOR            |
+	#| I2C3              | TPM(cr50)                 |
+	#| I2C4              | Touchpad                  |
+	#| I2C5              | Touchscreen               |
+	#+-------------------+---------------------------+
+	register "common_soc_config" = "{
+		/* Render OEM footer logo 100px above from the edge */
+		.logo_bottom_margin = 100,
+		.chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT,
+		.i2c[0] = {
+			.speed = I2C_SPEED_FAST,
+		},
+		.i2c[1] = {
+			.speed = I2C_SPEED_FAST,
+		},
+		.i2c[2] = {
+			.speed = I2C_SPEED_FAST,
+		},
+		.i2c[3] = {
+			.early_init = 1,
+			.speed = I2C_SPEED_FAST,
+		},
+		.i2c[4] = {
+			.speed = I2C_SPEED_FAST,
+		},
+		.i2c[5] = {
+			.speed = I2C_SPEED_FAST,
+		},
+	}"
+
+	device domain 0 on
+		device ref igpu on
+			chip drivers/gfx/generic
+				register "device_count" = "4"
+				# DDIA for eDP
+				register "device[0].name" = ""LCD0""
+				register "device[0].type" = "panel"
+				# DDIB for HDMI
+				# If HDMI is not enumerated in the kernel, then no GFX device should be added for DDIB
+				register "device[1].name" = ""DD01""
+				# TCP0 (DP-1) for port C0
+				register "device[2].name" = ""DD02""
+				register "device[2].use_pld" = "true"
+				register "device[2].pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(2, 1))"
+				# TCP1 (DP-2) for port C1
+				register "device[3].name" = ""DD03""
+				# TCP2 (DP-3) for port C2
+				register "device[4].name" = ""DD04""
+				register "device[4].use_pld" = "true"
+				register "device[4].pld" = "ACPI_PLD_TYPE_C(RIGHT, LEFT, ACPI_PLD_GROUP(3, 1))"
+			    device generic 0 on end
+			end
+		end
+
+		device ref iaa off end
+		device ref tbt_pcie_rp0 on end
+		device ref tbt_pcie_rp1 on end
+		device ref tbt_pcie_rp2 on end
+		device ref tbt_pcie_rp3 on end
+		device ref tcss_xhci on
+			chip drivers/usb/acpi
+				device ref tcss_root_hub on
+					chip drivers/usb/acpi
+						register "desc" = ""USB3 Type-C Port C0""
+						register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
+						register "group" = "ACPI_PLD_GROUP(1, 2)"
+						device ref tcss_usb3_port0 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB3 Type-C Port C2""
+						register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
+						register "group" = "ACPI_PLD_GROUP(3, 2)"
+						device ref tcss_usb3_port2 on end
+					end
+
+				end
+			end
+		end
+
+		device ref tcss_dma0 on
+			chip drivers/intel/usb4/retimer
+				register "dfp[0].power_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B21)"
+				use tcss_usb3_port0 as dfp[0].typec_port
+				device generic 0 on end
+			end
+		end
+		device ref tcss_dma1 on
+			chip drivers/intel/usb4/retimer
+				register "dfp[0].power_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B21)"
+				use tcss_usb3_port2 as dfp[0].typec_port
+				device generic 0 on	end
+			end
+		end
+
+		device ref ish on
+			chip drivers/intel/ish
+				register "add_acpi_dma_property" = "true"
+				device generic 0 on end
+			end
+		end
+
+		device ref xhci on
+			chip drivers/usb/acpi
+				device ref xhci_root_hub on
+					chip drivers/usb/acpi
+						register "desc" = ""USB2 Type-C Port C0""
+						register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
+						register "group" = "ACPI_PLD_GROUP(1, 1)"
+						device ref usb2_port1 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB2 Type-C Port C1""
+						register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
+						register "group" = "ACPI_PLD_GROUP(2, 1)"
+						device ref usb2_port2 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB2 Camera""
+						register "type" = "UPC_TYPE_INTERNAL"
+						register "has_power_resource" = "true"
+						register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C06)"
+						device ref usb2_port3 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB2 Type-A Port 0""
+						register "type" = "UPC_TYPE_A"
+						register "group" = "ACPI_PLD_GROUP(6, 1)"
+						device ref usb2_port6 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB2 FPMCU""
+						register "type" = "UPC_TYPE_INTERNAL"
+						register "has_power_resource" = "true"
+						register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E19)"
+						device ref usb2_port7 on end
+					end
+				end
+			end
+		end
+
+		device ref pcie_rp5 on
+			register "pcie_rp[PCIE_RP(5)]" = "{
+			.clk_src = 6,
+			.clk_req = 6,
+			.flags = PCIE_RP_CLK_REQ_DETECT | PCIE_RP_LTR | PCIE_RP_AER,
+			}"
+			chip soc/intel/common/block/pcie/rtd3
+				register "is_storage" = "true"
+				register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B16)"
+				register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B09)"
+				register "srcclk_pin" = "6"
+				device generic 0 on end
+			end
+		end # Gen4 M.2 SSD
+
+		device ref cnvi_wifi on
+			chip drivers/wifi/generic
+				register "wake" = "GPE0_PME_B0"
+				register "add_acpi_dma_property" = "true"
+				register "enable_cnvi_ddr_rfim" = "true"
+				use cnvi_bluetooth as bluetooth_companion
+				device generic 0 on end
+			end
+		end # CNVi
+
+		device ref cnvi_bluetooth on end
+
+		# NOTE: i2c0 is function 0; hence it needs to be enabled when any of i2c1-5 is enabled.
+		# TPM device is under i2c3. Therefore, i2c0 needs to be enabled anyways.
+		device ref i2c0 on
+			chip drivers/i2c/generic
+				register "hid" = ""RTL5682""
+				register "name" = ""RT58""
+				register "desc" = ""Headset Codec""
+				register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_H17)"
+				# Set the jd_src to RT5668_JD1 for jack detection
+				register "property_count" = "1"
+				register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER"
+				register "property_list[0].name" = ""realtek,jd-src""
+				register "property_list[0].integer" = "1"
+				device i2c 1a on
+					#probe AUDIO ALC5682I_I2S
+				end
+			end
+		end
+		device ref i2c1 on end
+		device ref i2c2 on end
+		device ref i2c3 on
+			chip drivers/i2c/tpm
+				register "hid" = ""GOOG0005""
+				register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_E02_IRQ)"
+				device i2c 50 on end
+			end
+		end # I2C3
+		device ref i2c4 on
+			chip drivers/i2c/hid
+				register "generic.hid" = ""PIXA2305""
+				register "generic.desc" = ""PIXA Touchpad""
+				register "generic.irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_E18_IRQ)"
+				# NOTE: pmc_gpe0_dw2 is GPP_E in baseboard devicetree.cb.
+				register "generic.wake" = "GPE0_DW2_18"
+				register "generic.detect" = "1"
+				register "hid_desc_reg_offset" = "0x20"
+				device i2c 68 on end
+			end
+			chip drivers/i2c/hid
+				register "generic.hid" = ""PNP0C50""
+				register "generic.desc" = ""ELAN Touchpad""
+				register "generic.irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_E18_IRQ)"
+				register "generic.wake" = "GPE0_DW2_18"
+				register "generic.detect" = "1"
+				register "hid_desc_reg_offset" = "0x20"
+				device i2c 2c on end
+			end
+		end # I2C4
+		device ref i2c5 on
+			chip drivers/i2c/hid
+				register "generic.hid" = ""ELAN9004""
+				register "generic.desc" = ""ELAN Touchscreen""
+				register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_F18_IRQ)"
+				register "generic.detect" = "1"
+				register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_F16)"
+				register "generic.reset_delay_ms" = "150"
+				register "generic.reset_off_delay_ms" = "1"
+				register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_F08)"
+				register "generic.enable_delay_ms" = "6"
+				register "generic.enable_off_delay_ms" = "30"
+				register "generic.stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_E05)"
+				register "generic.stop_off_delay_ms" = "1"
+				register "generic.has_power_resource" = "1"
+				register "generic.use_gpio_for_status" = "true"
+				register "hid_desc_reg_offset" = "0x01"
+				device i2c 0x10 on end
+			end
+		end # I2C5
+		device ref gspi0 on end
+		device ref smbus on end
+	end
+end

From 80861a9f69998c1d760cef536a9b078cf82bdd99 Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Fri, 17 Oct 2025 11:07:28 -0500
Subject: [PATCH 2294/3886] mb/starlabs/starlite_adl: Add CFR option for USB
 card reader

Add a CFR setup menu option to enable/disable the USB micro-SD card
reader, but restrict it to newer boards which use the MXC
accelerometer, as those boards have the card reader on USB2 port 4,
rather than shared with the detachable keyboard on port 3.

TEST=build/boot on starlite_adl boards with and without the MXC
accelerometer, verify only boards with it have the CFR option
to disable the card reader shown, and that the option works
as expected.

Change-Id: I9255d008c6f322d01390ed9f19e4e963cf04eeb6
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89626
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
---
 src/mainboard/starlabs/starlite_adl/cfr.c     | 19 +++++++++++++++++++
 .../starlite_adl/variants/mk_v/devicetree.cb  |  4 +++-
 .../starlite_adl/variants/mk_v/devtree.c      |  4 ++++
 3 files changed, 26 insertions(+), 1 deletion(-)

diff --git a/src/mainboard/starlabs/starlite_adl/cfr.c b/src/mainboard/starlabs/starlite_adl/cfr.c
index 2e36e99b6f..a7ebe498aa 100644
--- a/src/mainboard/starlabs/starlite_adl/cfr.c
+++ b/src/mainboard/starlabs/starlite_adl/cfr.c
@@ -5,6 +5,9 @@
 #include <drivers/option/cfr_frontend.h>
 #include <ec/starlabs/merlin/cfr.h>
 #include <intelblocks/cfr.h>
+#include <device/i2c_bus.h>
+#include <device/i2c_simple.h>
+#include <static.h>
 #include <variants.h>
 
 static const struct sm_object accelerometer = SM_DECLARE_BOOL({
@@ -14,6 +17,21 @@ static const struct sm_object accelerometer = SM_DECLARE_BOOL({
 	.default_value	= true,
 });
 
+static void update_card_reader(const struct sm_object *obj, struct sm_object *new)
+{
+	struct device *mxc_accel = DEV_PTR(mxc6655);
+
+	if (!i2c_dev_detect(i2c_busdev(mxc_accel), mxc_accel->path.i2c.device))
+		new->sm_bool.flags = CFR_OPTFLAG_SUPPRESS;
+}
+
+static const struct sm_object card_reader = SM_DECLARE_BOOL({
+	.opt_name	= "card_reader",
+	.ui_name	= "Card Reader",
+	.ui_helptext	= "Enable or disable the built-in card reader",
+	.default_value	= true,
+}, WITH_CALLBACK(update_card_reader));
+
 #if CONFIG(SOC_INTEL_TIGERLAKE) || CONFIG(SOC_INTEL_ALDERLAKE) || CONFIG(SOC_INTEL_RAPTORLAKE)
 static const struct sm_object gna = SM_DECLARE_BOOL({
 	.opt_name	= "gna",
@@ -147,6 +165,7 @@ static struct sm_obj_form devices = {
 	.ui_name = "Devices",
 	.obj_list = (const struct sm_object *[]) {
 		&accelerometer,
+		&card_reader,
 		&display_native_res,
 		#if CONFIG(SOC_INTEL_TIGERLAKE) || CONFIG(SOC_INTEL_ALDERLAKE) || CONFIG(SOC_INTEL_RAPTORLAKE)
 		&gna,
diff --git a/src/mainboard/starlabs/starlite_adl/variants/mk_v/devicetree.cb b/src/mainboard/starlabs/starlite_adl/variants/mk_v/devicetree.cb
index 598e2724d0..857d626197 100644
--- a/src/mainboard/starlabs/starlite_adl/variants/mk_v/devicetree.cb
+++ b/src/mainboard/starlabs/starlite_adl/variants/mk_v/devicetree.cb
@@ -85,6 +85,8 @@ chip soc/intel/alderlake
 			# Internal Bluetooth			1874 mil
 			register "usb2_ports[9]"		= "USB2_PORT_SHORT(OC_SKIP)"
 
+			register "usb2_ports[3]"		= "USB2_PORT_MID(OC_SKIP)"
+
 			chip drivers/usb/acpi
 				device ref xhci_root_hub on
 					chip drivers/usb/acpi
@@ -167,7 +169,7 @@ chip soc/intel/alderlake
 				register "has_rotation_matrix"		= "1"
 				register "rotation_matrix"		= "{1, 0, 0, 0, -1, 0, 0, 0, 1}"
 				register "detect"			= "1"
-				device i2c 15 on end
+				device i2c 15 alias mxc6655 on end
 			end
 		end
 		device ref i2c2		on				# Touchscreen
diff --git a/src/mainboard/starlabs/starlite_adl/variants/mk_v/devtree.c b/src/mainboard/starlabs/starlite_adl/variants/mk_v/devtree.c
index 08359ee7b1..8252d61756 100644
--- a/src/mainboard/starlabs/starlite_adl/variants/mk_v/devtree.c
+++ b/src/mainboard/starlabs/starlite_adl/variants/mk_v/devtree.c
@@ -72,4 +72,8 @@ void devtree_update(void)
 	/* Enable/Disable GNA based on CMOS settings */
 	if (get_uint_option("gna", 0) == 0)
 		gna_dev->enabled = 0;
+
+	/* Enable/Disable Card Reader based on CMOS Settings */
+	if (get_uint_option("card_reader", 1) == 0)
+		cfg->usb2_ports[3].enable = 0;
 }

From 249883d5bf851ae36f1729a67c2af9a97d8026ad Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Fri, 17 Oct 2025 11:14:27 -0500
Subject: [PATCH 2295/3886] mb/starlabs/starlite_adl: Squash SB and non-SB
 board variants

Originally, there were separate EC firmware builds for the smart
battery (SB) and non-SB versions of the starlite_adl board, but those
have long since been unified. Squash the board variants into a single
board which supports both SB and non-SB boards.

Adjust the board description to reflect that it will support both the
existing N200 and upcoming N355 flavors.

TEST=build/boot starlite_adl on both SB and non-SB boards, verify
battery and all other features function normally.

Change-Id: I2461a094f2455ce333132ffa9f2f83967ae0e927
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89627
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
---
 src/mainboard/starlabs/starlite_adl/Kconfig      | 5 -----
 src/mainboard/starlabs/starlite_adl/Kconfig.name | 5 +----
 2 files changed, 1 insertion(+), 9 deletions(-)

diff --git a/src/mainboard/starlabs/starlite_adl/Kconfig b/src/mainboard/starlabs/starlite_adl/Kconfig
index 36b61a71f5..ae86ef63dc 100644
--- a/src/mainboard/starlabs/starlite_adl/Kconfig
+++ b/src/mainboard/starlabs/starlite_adl/Kconfig
@@ -39,9 +39,6 @@ config BOARD_STARLABS_STARLITE_SERIES
 config BOARD_STARLABS_LITE_ADL
 	select BOARD_STARLABS_STARLITE_SERIES
 
-config BOARD_STARLABS_LITE_ADL_SB
-	select BOARD_STARLABS_STARLITE_SERIES
-
 if BOARD_STARLABS_STARLITE_SERIES
 
 config CCD_PORT
@@ -75,7 +72,6 @@ config EC_STARLABS_BATTERY_OEM
 config EC_STARLABS_ITE_BIN_PATH
 	string
 	depends on EC_STARLABS_NEED_ITE_BIN
-	default "3rdparty/blobs/mainboard/\$(MAINBOARDDIR)/mk_v_sb/ec.bin" if BOARD_STARLABS_LITE_ADL_SB
 	default "3rdparty/blobs/mainboard/\$(MAINBOARDDIR)/\$(CONFIG_VARIANT_DIR)/ec.bin"
 
 config EC_VARIANT_DIR
@@ -94,7 +90,6 @@ config MAINBOARD_DIR
 
 config MAINBOARD_FAMILY
 	string
-	default "I5-SB" if BOARD_STARLABS_LITE_ADL_SB
 	default "I5"
 
 config MAINBOARD_PART_NUMBER
diff --git a/src/mainboard/starlabs/starlite_adl/Kconfig.name b/src/mainboard/starlabs/starlite_adl/Kconfig.name
index 5d66e61934..071490084b 100644
--- a/src/mainboard/starlabs/starlite_adl/Kconfig.name
+++ b/src/mainboard/starlabs/starlite_adl/Kconfig.name
@@ -1,7 +1,4 @@
 comment "Star Labs StarLite Series"
 
 config BOARD_STARLABS_LITE_ADL
-	bool "Star Labs Lite Mk V (N200)"
-
-config BOARD_STARLABS_LITE_ADL_SB
-	bool "Star Labs Lite Mk V Smart Battery (N200)"
+	bool "Star Labs Lite Mk V (N200/N355)"

From fce489e9e5c306f78819535faf0df3f696aa2d2e Mon Sep 17 00:00:00 2001
From: Cliff Huang <cliff.huang@intel.com>
Date: Fri, 17 Oct 2025 11:03:54 -0700
Subject: [PATCH 2296/3886] drivers/intel/touch: Check SoC I2C speed function
 exists before calling
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

This change adds a null pointer check to ensure that the SoC-specific
function to retrieve I2C bus speed is properly mapped before attempting
to call it. Without this check, systems may crash during boot when the
function pointer is not initialized. The issue occurs when the
touchscreen or touchpad is configured to use THC-I2C via CBI fw_config,
but the underlying SoC doesn't provide the required I2C speed function
implementation.

BUG=none
TEST=Boot Fatcat board to OS with CBI fw_config selecting touchscreen or
touchpad using THC-I2C. Verify no crash occurs during boot and touch
devices function properly.

Change-Id: Ib982f4435aa506f2b9203f81140366addc6559f3
Signed-off-by: Cliff Huang <cliff.huang@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89628
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-by: Jamie Ryu <jamie.m.ryu@intel.com>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
---
 src/drivers/intel/touch/touch.c | 9 +++++++--
 1 file changed, 7 insertions(+), 2 deletions(-)

diff --git a/src/drivers/intel/touch/touch.c b/src/drivers/intel/touch/touch.c
index 2310773dd3..7697ffb149 100644
--- a/src/drivers/intel/touch/touch.c
+++ b/src/drivers/intel/touch/touch.c
@@ -268,8 +268,13 @@ static void touch_generate_acpi_i2cdev_dsd(const struct device *dev)
 	acpigen_write_create_buffer_qword_field("ISUB", 0x88, "HMSL");
 
 	acpigen_write_store_int_to_namestr(touch_get(dev, dev_hidi2c.intf.hidi2c.addr), "DADR");
-	connection_speed_val = _soc_hidi2c_info->get_soc_i2c_bus_speed_val_func(
-		touch_dev_soc_get(dev, hidi2c, connection_speed));
+
+	if (_soc_hidi2c_info->get_soc_i2c_bus_speed_val_func) {
+		connection_speed_val = _soc_hidi2c_info->get_soc_i2c_bus_speed_val_func(
+			touch_dev_soc_get(dev, hidi2c, connection_speed));
+	} else {
+		die("Missing SoC function to map I2C speed to its register value!\n");
+	}
 	acpigen_write_store_int_to_namestr(connection_speed_val, "DSPD");
 	acpigen_write_store_int_to_namestr(touch_soc_get(dev, hidi2c, addr_mode), "DADM");
 	acpigen_write_store_int_to_namestr(touch_soc_get(dev, hidi2c, sm_scl_high_period), "SMHX");

From 14fc6c3469076e3ba245011da5263268033c7ae9 Mon Sep 17 00:00:00 2001
From: Felix Singer <felix.singer@secunet.com>
Date: Tue, 23 Sep 2025 14:53:54 +0200
Subject: [PATCH 2297/3886] crossgcc: Drop nds32le-elf toolchain from default
 builds

coreboot does not use the nds32le-elf toolchain at all, but it causes
build issues in the CI. So drop it from the default builds. It can
still be built by using buildgcc.

Change-Id: I5e5e5b6914265d6aff14c011062db268db4acf6b
Signed-off-by: Felix Singer <felix.singer@secunet.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89317
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Reviewed-by: Jon Murphy <jpmurphy@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 util/crossgcc/Makefile | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/util/crossgcc/Makefile b/util/crossgcc/Makefile
index 06ec91c493..3be816e9d8 100644
--- a/util/crossgcc/Makefile
+++ b/util/crossgcc/Makefile
@@ -10,7 +10,7 @@ DEST ?= $(CURDIR)/xgcc
 
 all:
 	$(MAKE) build-i386 build-x64 build-arm \
-		build-riscv build-aarch64 build-ppc64 build-nds32le \
+		build-riscv build-aarch64 build-ppc64 \
 		build_clang build_iasl build_nasm
 
 ###########################################################

From 5c85793d260c812ec041fa833de00f61d1f62748 Mon Sep 17 00:00:00 2001
From: Mac Chiang <mac.chiang@intel.com>
Date: Wed, 17 Sep 2025 13:30:21 +0800
Subject: [PATCH 2298/3886] mb/google/fatcat/var/lapis: Add cs42l43 and cs35l56
 Soundwire links

Enable the CS42L43 codec on SoundWire link 3 and the CS35L56
amplifiers on SoundWire link 2.

Scope (\_SB.PCI0.HDAS.SNDW)
    {
        Device (SW30)
        {
            Name (_ADR, 0x00033001FA424301)  // _ADR: Address
            Name (_DDN, "Headset Codec")  // _DDN: DOS Device Name
            Name (_SUB, "1337")  // _SUB: Subsystem ID
...
    {
        Device (SW20)
        {
            Name (_ADR, 0x00023001FA355601)  // _ADR: Address
            Name (_DDN, "Left Speaker Amp")  // _DDN: DOS Device Name
            Name (_SUB, "12345678")  // _SUB: Subsystem ID
...
        Device (SW21)
        {
            Name (_ADR, 0x00023101FA355601)  // _ADR: Address
            Name (_DDN, "Right Speaker Amp")  // _DDN: DOS Device Name
            Name (_SUB, "12345678")  // _SUB: Subsystem ID
...

BUG=b:444122406, b:444302600
TES=emerge-lapis coreboot

Change-Id: Ic73d705655bdc0a4a8140feafa28aceb2fc25ad3
Signed-off-by: Mac Chiang <mac.chiang@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89345
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 .../fatcat/variants/lapis/overridetree.cb     | 26 +++++++++++++++++++
 1 file changed, 26 insertions(+)

diff --git a/src/mainboard/google/fatcat/variants/lapis/overridetree.cb b/src/mainboard/google/fatcat/variants/lapis/overridetree.cb
index 39da99b14c..8c98633a79 100644
--- a/src/mainboard/google/fatcat/variants/lapis/overridetree.cb
+++ b/src/mainboard/google/fatcat/variants/lapis/overridetree.cb
@@ -443,6 +443,32 @@ chip soc/intel/pantherlake
 			end
 		end #Touchpenal
 
+		device ref hda on
+			chip drivers/intel/soundwire
+				device generic 0 on
+					chip drivers/soundwire/cs42l43
+						# SoundWire Link 3 ID 0
+						register "desc" = ""Headset Codec""
+						register "sub" = ""1337""
+						device generic 3.0 on end
+					end
+					chip drivers/soundwire/cs35l56
+						# SoundWire Link 2 ID 0
+						register "desc" = ""Left Speaker Amp""
+						register "part_id" = "MIPI_DEV_ID_CIRRUS_CS35L56"
+						register "sub" = ""12345678""
+						device generic 2.0 on end
+					end
+					chip drivers/soundwire/cs35l56
+						# SoundWire Link 2 ID 1
+						register "desc" = ""Right Speaker Amp""
+						register "part_id" = "MIPI_DEV_ID_CIRRUS_CS35L56"
+						register "sub" = ""12345678""
+						device generic 2.1 on end
+					end
+				end
+			end
+		end # SNDW
 		device ref i2c0 on end
 		device ref i2c3 on
 			chip drivers/i2c/tpm

From 5daf497df4972c973b6a25602c5bea31b1988763 Mon Sep 17 00:00:00 2001
From: Ziang Wang <wangziang.ok@bytedance.com>
Date: Tue, 14 Oct 2025 15:14:26 +0800
Subject: [PATCH 2299/3886] arch/riscv: Add ACPI support for riscv

Add ACPI table creation routine for riscv. An empty header 'pci_ops.h'
is added to pass build.

TEST=Build and run successfully on QEMU rvvirt machine. Using command
"qemu-system-riscv64 -machine virt,aia=aplic-imsic,acpi=on -bios
build/coreboot.rom -nographic -pflash build/coreboot.rom".

Change-Id: Ifa57bd8511e73c3406bcf2672fed90c1e86a4ffd
Signed-off-by: Ziang Wang <wangziang.ok@bytedance.com>
Signed-off-by: Dong Wei <weidong.wd@bytedance.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89558
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
---
 src/arch/riscv/include/arch/pci_ops.h |  9 +++++++++
 src/arch/riscv/tables.c               | 21 +++++++++++++++++++++
 2 files changed, 30 insertions(+)
 create mode 100644 src/arch/riscv/include/arch/pci_ops.h

diff --git a/src/arch/riscv/include/arch/pci_ops.h b/src/arch/riscv/include/arch/pci_ops.h
new file mode 100644
index 0000000000..25c4f82a72
--- /dev/null
+++ b/src/arch/riscv/include/arch/pci_ops.h
@@ -0,0 +1,9 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef ARCH_RISCV_PCI_OPS_H
+#define ARCH_RISCV_PCI_OPS_H
+
+#include <device/pci_def.h>
+#include <device/pci_mmio_cfg.h>
+
+#endif
diff --git a/src/arch/riscv/tables.c b/src/arch/riscv/tables.c
index 9fc75f455c..0ff238c59e 100644
--- a/src/arch/riscv/tables.c
+++ b/src/arch/riscv/tables.c
@@ -4,9 +4,30 @@
 #include <boot/tables.h>
 #include <boot/coreboot_tables.h>
 #include <symbols.h>
+#include <assert.h>
+#include <acpi/acpi.h>
+#include <cbmem.h>
+#include <console/console.h>
+
+unsigned long acpi_arch_fill_madt(acpi_madt_t *madt, unsigned long current)
+{
+	return current;
+}
+
+static void write_acpi_table(void)
+{
+	const size_t max_acpi_size = CONFIG_MAX_ACPI_TABLE_SIZE_KB * KiB;
+	const uintptr_t acpi_start = (uintptr_t)cbmem_add(CBMEM_ID_ACPI, max_acpi_size);
+	assert(IS_ALIGNED(acpi_start, 16));
+	const uintptr_t acpi_end = write_acpi_tables(acpi_start);
+	assert(acpi_end < acpi_start + max_acpi_size);
+	printk(BIOS_DEBUG, "ACPI tables: %ld bytes.\n", acpi_end - acpi_start);
+}
 
 void arch_write_tables(uintptr_t coreboot_table)
 {
+	if (CONFIG(HAVE_ACPI_TABLES))
+		write_acpi_table();
 }
 
 void bootmem_arch_add_ranges(void)

From c1c83df3b5451bf15a677e546e5b4c644fc67089 Mon Sep 17 00:00:00 2001
From: Ziang Wang <wangziang.ok@bytedance.com>
Date: Tue, 14 Oct 2025 16:45:10 +0800
Subject: [PATCH 2300/3886] mb/emulation/qemu-riscv: Enable ACPI by default

Select HAVE_ACPI_TABLES & PCI for QEMU riscv virt machine mainboard. Add
an empty dsdt.asl to fit current build process, but it will not actually
be used since QEMU has its own method of providing DSDT blob.

TEST=build and run successfully on QEMU rvvirt machine. Using command
"qemu-system-riscv64 -machine virt,aia=aplic-imsic,acpi=on -bios
build/coreboot.rom -nographic -pflash build/coreboot.rom".

Change-Id: If8c9b5d86adb69afdcb4bf320d6353b2b2acfb31
Signed-off-by: Ziang Wang <wangziang.ok@bytedance.com>
Signed-off-by: Dong Wei <weidong.wd@bytedance.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89562
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/emulation/qemu-riscv/Kconfig    |  8 ++++++++
 .../emulation/qemu-riscv/Makefile.mk          |  1 +
 src/mainboard/emulation/qemu-riscv/acpi.c     | 18 ++++++++++++++++++
 src/mainboard/emulation/qemu-riscv/dsdt.asl   | 19 +++++++++++++++++++
 4 files changed, 46 insertions(+)
 create mode 100644 src/mainboard/emulation/qemu-riscv/acpi.c
 create mode 100644 src/mainboard/emulation/qemu-riscv/dsdt.asl

diff --git a/src/mainboard/emulation/qemu-riscv/Kconfig b/src/mainboard/emulation/qemu-riscv/Kconfig
index c6ff42bdb2..a8972260b5 100644
--- a/src/mainboard/emulation/qemu-riscv/Kconfig
+++ b/src/mainboard/emulation/qemu-riscv/Kconfig
@@ -38,6 +38,8 @@ config BOARD_SPECIFIC_OPTIONS
 	select RISCV_USE_ARCH_TIMER
 	select FLATTENED_DEVICE_TREE
 	select DRIVERS_EMULATION_QEMU_FW_CFG
+	select PCI
+	select HAVE_ACPI_TABLES
 
 config MEMLAYOUT_LD_FILE
 	string
@@ -49,6 +51,12 @@ config MAINBOARD_DIR
 config MAINBOARD_PART_NUMBER
 	default "QEMU RISCV"
 
+config ECAM_MMCONF_BASE_ADDRESS
+	default 0x30000000
+
+config ECAM_MMCONF_BUS_NUMBER
+	default 256
+
 config MAX_CPUS
 	int
 	default 512 # QEMUs current limit for the virt target
diff --git a/src/mainboard/emulation/qemu-riscv/Makefile.mk b/src/mainboard/emulation/qemu-riscv/Makefile.mk
index 90e5023feb..deaec5e44f 100644
--- a/src/mainboard/emulation/qemu-riscv/Makefile.mk
+++ b/src/mainboard/emulation/qemu-riscv/Makefile.mk
@@ -23,5 +23,6 @@ ramstage-y += cbmem.c
 ramstage-y += chip.c
 ramstage-y += smp.c
 ramstage-y += mmio.c
+ramstage-$(CONFIG_HAVE_ACPI_TABLES) += acpi.c
 
 CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/include
diff --git a/src/mainboard/emulation/qemu-riscv/acpi.c b/src/mainboard/emulation/qemu-riscv/acpi.c
new file mode 100644
index 0000000000..687fe20361
--- /dev/null
+++ b/src/mainboard/emulation/qemu-riscv/acpi.c
@@ -0,0 +1,18 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <acpi/acpi.h>
+#include <smbios.h>
+
+smbios_enclosure_type smbios_mainboard_enclosure_type(void)
+{
+	return SMBIOS_ENCLOSURE_MAIN_SERVER_CHASSIS;
+}
+
+void acpi_fill_fadt(acpi_fadt_t *fadt)
+{
+}
+
+unsigned long acpi_fill_madt(unsigned long current)
+{
+	return current;
+}
diff --git a/src/mainboard/emulation/qemu-riscv/dsdt.asl b/src/mainboard/emulation/qemu-riscv/dsdt.asl
new file mode 100644
index 0000000000..4e992f5ed3
--- /dev/null
+++ b/src/mainboard/emulation/qemu-riscv/dsdt.asl
@@ -0,0 +1,19 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+/*
+ * This DSDT source is meant to be empty since riscv qemu has its own
+ * method to retrieve DSDT blob via fw_cfg.
+ */
+
+#include <acpi/acpi.h>
+
+DefinitionBlock(
+	"dsdt.aml",
+	"DSDT",
+	ACPI_DSDT_REV_2,
+	OEM_ID,
+	ACPI_TABLE_CREATOR,
+	0x20110725	// OEM revision
+)
+{
+}

From e38056bef8f7afc3502ca02a9cf84692e4d42b19 Mon Sep 17 00:00:00 2001
From: Zheng Bao <fishbaozi@gmail.com>
Date: Sat, 21 Sep 2024 13:51:23 +0800
Subject: [PATCH 2301/3886] amdfwtool: Move ISH before PSP L2

The amdfw.rom will be divided into 3 parts:
PSP Level 1, PSP Level 2A, PSP Level 2B.

The two ISHs are close to L1 and can be combined as a CBFS module.
To do that, move the new_psp_dir for L1 and L2 to separated branches.
The final sequence is EFS, PSP L1, ISH A, ISH B, PSP L2A, BIOS L2A,
PSP L2B, BIOS L2B.

TEST=Google/Skyrim

Change-Id: Id69268619893d78d9b5330052a4fd5b501263f75
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84533
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
---
 util/amdfwtool/amdfwtool.c | 39 +++++++++++++++++++++++---------------
 1 file changed, 24 insertions(+), 15 deletions(-)

diff --git a/util/amdfwtool/amdfwtool.c b/util/amdfwtool/amdfwtool.c
index d071a5be7c..07736dd595 100644
--- a/util/amdfwtool/amdfwtool.c
+++ b/util/amdfwtool/amdfwtool.c
@@ -967,11 +967,6 @@ static void integrate_psp_levels(context *ctx,
 	current_table_save = ctx->current_table;
 	ctx->current_table = BUFF_TO_RUN_MODE(*ctx, pspdir, AMD_ADDR_REL_BIOS);
 	if (recovery_ab && (pspdir2 != NULL)) {
-		if (cb_config->need_ish) {	/* Need ISH */
-			ctx->ish_a_dir = new_ish_dir(ctx);
-			if (pspdir2_b != NULL)
-				ctx->ish_b_dir = new_ish_dir(ctx);
-		}
 		integrate_psp_ab(ctx, pspdir, pspdir2, ctx->ish_a_dir,
 			AMD_FW_RECOVERYAB_A, cb_config->soc_id);
 		if (pspdir2_b != NULL)
@@ -1012,7 +1007,7 @@ static void integrate_psp_firmwares(context *ctx,
 	unsigned int i, count;
 	int level;
 	uint32_t size;
-	psp_directory_table *pspdir;
+	psp_directory_table *pspdir = NULL;
 	uint64_t addr;
 	uint32_t current_table_save;
 	bool recovery_ab = cb_config->recovery_ab;
@@ -1023,17 +1018,31 @@ static void integrate_psp_firmwares(context *ctx,
 	 * is passed, clearly a 2nd-level table is intended.  However, a
 	 * 1st-level cookie may indicate level 1 or flattened.
 	 */
-	pspdir = new_psp_dir(ctx, cb_config->multi_level, cookie);
+	current_table_save = ctx->current_table;
 
 	if (cookie == PSP_COOKIE) {
-		ctx->pspdir = pspdir;
-		if (recovery_ab)
-			ctx->pspdir_bak = new_psp_dir(ctx, cb_config->multi_level, cookie);
+		if (!cb_config->combo_new_rab || ctx->combo_index == 0) {
+			pspdir = new_psp_dir(ctx, cb_config->multi_level, cookie);
+			ctx->pspdir = pspdir;
+			if (recovery_ab)
+				ctx->pspdir_bak = new_psp_dir(ctx, cb_config->multi_level, cookie);
+		}
+		/* The ISH tables are with PSP L1. */
+		if (cb_config->need_ish && ctx->ish_a_dir == NULL)	/* Need ISH */
+			ctx->ish_a_dir = new_ish_dir(ctx);
+		if (cb_config->need_ish && ctx->ish_b_dir == NULL)	/* Need ISH */
+			ctx->ish_b_dir = new_ish_dir(ctx);
 	} else if (cookie == PSPL2_COOKIE) {
-		if (ctx->pspdir2 == NULL)
+		if (ctx->pspdir2 == NULL) {
+			pspdir = new_psp_dir(ctx, cb_config->multi_level, cookie);
 			ctx->pspdir2 = pspdir;
-		else if (ctx->pspdir2_b == NULL)
+		} else if (ctx->pspdir2_b == NULL) {
+			pspdir = new_psp_dir(ctx, cb_config->multi_level, cookie);
 			ctx->pspdir2_b = pspdir;
+		}
+	}
+	if (pspdir == NULL) {
+		goto out;
 	}
 
 	if (!cb_config->multi_level)
@@ -1053,7 +1062,7 @@ static void integrate_psp_firmwares(context *ctx,
 		else
 			level = PSP_BOTH_AB;
 	}
-	current_table_save = ctx->current_table;
+
 	ctx->current_table = BUFF_TO_RUN_MODE(*ctx, pspdir, AMD_ADDR_REL_BIOS);
 	adjust_current_pointer(ctx, 0, TABLE_ALIGNMENT);
 
@@ -1153,6 +1162,7 @@ static void integrate_psp_firmwares(context *ctx,
 	}
 
 	fill_dir_header(pspdir, count, ctx);
+out:
 	ctx->current_table = current_table_save;
 }
 
@@ -1824,8 +1834,7 @@ int main(int argc, char **argv)
 
 		if (cb_config.multi_level) {
 			/* PSP L1 */
-			if (!cb_config.combo_new_rab || ctx.combo_index == 0)
-				integrate_psp_firmwares(&ctx,
+			integrate_psp_firmwares(&ctx,
 					amd_psp_fw_table, PSP_COOKIE, &cb_config);
 			/* PSP L2 & BIOS L2 (if AB recovery) */
 			integrate_psp_firmwares(&ctx,

From 35d4b3f2f48bc032579c15439b5cb29a5d254ce3 Mon Sep 17 00:00:00 2001
From: Venkateshwar S <vens@qualcomm.corp-partner.google.com>
Date: Sun, 12 Oct 2025 23:04:15 -0700
Subject: [PATCH 2302/3886] arch/arm64: Support to load QTEE firmware in
 x1P42100

This patch adds support to load QTEE firmware in X1P42100. A new
Kconfig 'ARM64_HAS_SECURE_OS_PAYLOAD' has been introduced to support
packing the QTEE firmware as a CBFS payload type. Based on this
configuration, the QTEE firmware is packed either as a stage or payload
type in CBFS.

In X1P42100, the QTEE FW is packed as a CBFS payload type, as its
memory regions are non-contiguous across system IMEM and DDR.

TEST=Create an image.serial.bin and ensure it boots on X1P42100.
Ensure loading of the QTEE firmware in the appropriate regions.

[INFO ]  CBFS: Found 'fallback/secure_os' @0xff1c0 size 0x2ac188
[DEBUG]  read SPI 0xd2f218 0x2ac188: 225876 us, 12405 KB/s, 99.240 Mbps
[INFO ]  VB2:vb2_secdata_kernel_get() VB2_SECDATA_KERNEL_FLAGS not
                supported for secdata_kernel v0, return 0
[INFO ]  VB2:vb2_digest_init() 2802056 bytes, hash algo 2, HW
                acceleration forbidden
[DEBUG]  Loading segment from ROM address 0x9f8040f8
[DEBUG]    code (compression=0)
[DEBUG]    New segment dstaddr 0x1468f000 memsize 0x2000 srcaddr
                0x9f804280 filesize 0x2000
[DEBUG]  Loading Segment: addr: 0x1468f000 memsz: 0x0000000000002000
                filesz: 0x0000000000002000
[DEBUG]  it's not compressed!
[SPEW ]  [ 0x1468f000, 14691000, 0x14691000) &amp;lt;- 9f804280
[DEBUG]  Loading segment from ROM address 0x9f804114
[DEBUG]    data (compression=0)
[DEBUG]    New segment dstaddr 0x14691000 memsize 0x2000 srcaddr
                0x9f806280 filesize 0x2000
[DEBUG]  Loading Segment: addr: 0x14691000 memsz: 0x0000000000002000
                filesz: 0x0000000000002000
[DEBUG]  it's not compressed!
[SPEW ]  [ 0x14691000, 14693000, 0x14693000) &amp;lt;- 9f806280
[DEBUG]  Loading segment from ROM address 0x9f804130
[DEBUG]    code (compression=0)
[DEBUG]    New segment dstaddr 0xd8087000 memsize 0x12b000 srcaddr
                0x9f808280 filesize 0x12b000
[DEBUG]  Loading Segment: addr: 0xd8087000 memsz: 0x000000000012b000
                filesz: 0x000000000012b000
[DEBUG]  it's not compressed!
[SPEW ]  [ 0xd8087000, d81b2000, 0xd81b2000) &amp;lt;- 9f808280
[DEBUG]  Loading segment from ROM address 0x9f80414c
[DEBUG]    data (compression=0)
[DEBUG]    New segment dstaddr 0xd81b2000 memsize 0x14000 srcaddr
                0x9f933280 filesize 0x14000
[DEBUG]  Loading Segment: addr: 0xd81b2000 memsz: 0x0000000000014000
                filesz: 0x0000000000014000
[DEBUG]  it's not compressed!
[SPEW ]  [ 0xd81b2000, d81c6000, 0xd81c6000) &amp;lt;- 9f933280
[DEBUG]  Loading segment from ROM address 0x9f804168
[DEBUG]    data (compression=0)
[DEBUG]    New segment dstaddr 0xd81c6000 memsize 0xb3000 srcaddr
                0x9f947280 filesize 0xb3000
[DEBUG]  Loading Segment: addr: 0xd81c6000 memsz: 0x00000000000b3000
                filesz: 0x00000000000b3000
[DEBUG]  it's not compressed!
[SPEW ]  [ 0xd81c6000, d8279000, 0xd8279000) &amp;lt;- 9f947280
[DEBUG]  Loading segment from ROM address 0x9f804184
[DEBUG]    BSS 0xd8279000 (4096 byte)
[DEBUG]  Loading Segment: addr: 0xd8279000 memsz: 0x0000000000001000
                filesz: 0x0000000000000000
[DEBUG]  it's not compressed!
[SPEW ]  [ 0xd8279000, d8279000, 0xd827a000) &amp;lt;- 9f9fa280
[DEBUG]  Clearing Segment: addr: 0x00000000d8279000 memsz:
                0x0000000000001000
[DEBUG]  Loading segment from ROM address 0x9f8041a0
[DEBUG]    data (compression=0)
[DEBUG]    New segment dstaddr 0xd82e6000 memsize 0x5d000 srcaddr
                0x9f9fa280 filesize 0xe000
[DEBUG]  Loading Segment: addr: 0xd82e6000 memsz: 0x000000000005d000
                filesz: 0x000000000000e000
[DEBUG]  it's not compressed!
[SPEW ]  [ 0xd82e6000, d82f4000, 0xd8343000) &amp;lt;- 9f9fa280
[DEBUG]  Clearing Segment: addr: 0x00000000d82f4000 memsz:
                0x000000000004f000
[DEBUG]  Loading segment from ROM address 0x9f8041bc
[DEBUG]    BSS 0xd8343000 (65536 byte)
[DEBUG]  Loading Segment: addr: 0xd8343000 memsz: 0x0000000000010000
[DEBUG]  Loading Segment: addr: 0xd8279000 memsz: 0x0000000000001000
                filesz: 0x0000000000000000
[DEBUG]  it's not compressed!
[SPEW ]  [ 0xd8279000, d8279000, 0xd827a000) &amp;lt;- 9f9fa280
[DEBUG]  Clearing Segment: addr: 0x00000000d8279000 memsz:
                0x0000000000001000
[DEBUG]  Loading segment from ROM address 0x9f8041a0
[DEBUG]    data (compression=0)
[DEBUG]    New segment dstaddr 0xd82e6000 memsize 0x5d000 srcaddr
                0x9f9fa280 filesize 0xe000
[DEBUG]  Loading Segment: addr: 0xd82e6000 memsz: 0x000000000005d000
                filesz: 0x000000000000e000
[DEBUG]  it's not compressed!
[SPEW ]  [ 0xd82e6000, d82f4000, 0xd8343000) &amp;lt;- 9f9fa280
[DEBUG]  Clearing Segment: addr: 0x00000000d82f4000 memsz:
                0x000000000004f000
[DEBUG]  Loading segment from ROM address 0x9f8041bc
[DEBUG]    BSS 0xd8343000 (65536 byte)
[DEBUG]  Loading Segment: addr: 0xd8343000 memsz: 0x0000000000010000
                filesz: 0x0000000000000000
[DEBUG]  it's not compressed!
[SPEW ]  [ 0xd8343000, d8343000, 0xd8353000) &amp;lt;- 9fa08280
[DEBUG]  Clearing Segment: addr: 0x00000000d8343000 memsz:
                0x0000000000010000
[DEBUG]  Loading segment from ROM address 0x9f8041d8
[DEBUG]    BSS 0xd8353000 (65536 byte)
[DEBUG]  Loading Segment: addr: 0xd8353000 memsz: 0x0000000000010000
                filesz: 0x0000000000000000
[DEBUG]  it's not compressed!
[SPEW ]  [ 0xd8353000, d8353000, 0xd8363000) &amp;lt;- 9fa08280
[DEBUG]  Clearing Segment: addr: 0x00000000d8353000 memsz:
                0x0000000000010000
[DEBUG]  Loading segment from ROM address 0x9f8041f4
[DEBUG]    data (compression=0)
[DEBUG]    New segment dstaddr 0xd836a000 memsize 0x1000 srcaddr
                0x9fa08280 filesize 0x1000
[DEBUG]  Loading Segment: addr: 0xd836a000 memsz: 0x0000000000001000
                filesz: 0x0000000000001000
[DEBUG]  it's not compressed!
[SPEW ]  [ 0xd836a000, d836b000, 0xd836b000) &amp;lt;- 9fa08280
[DEBUG]  Loading segment from ROM address 0x9f804210
[DEBUG]    code (compression=0)
[DEBUG]    New segment dstaddr 0xd836b000 memsize 0x99000 srcaddr
                0x9fa09280 filesize 0x99000
[DEBUG]  Loading Segment: addr: 0xd836b000 memsz: 0x0000000000099000
                filesz: 0x0000000000099000
[DEBUG]  it's not compressed!
[SPEW ]  [ 0xd836b000, d8404000, 0xd8404000) &amp;lt;- 9fa09280
[DEBUG]  Loading segment from ROM address 0x9f80422c
[DEBUG]    data (compression=0)
[DEBUG]    New segment dstaddr 0xd8404000 memsize 0x3000 srcaddr
                0x9faa2280 filesize 0x3000
[DEBUG]  Loading Segment: addr: 0xd8404000 memsz: 0x0000000000003000
                filesz: 0x0000000000003000
[DEBUG]  it's not compressed!
[SPEW ]  [ 0xd8404000, d8407000, 0xd8407000) &amp;lt;- 9faa2280
[DEBUG]  Loading segment from ROM address 0x9f804248
[DEBUG]    data (compression=0)
[DEBUG]    New segment dstaddr 0xd8407000 memsize 0xb000 srcaddr
                0x9faa5280 filesize 0xb000
[DEBUG]  Loading Segment: addr: 0xd8407000 memsz: 0x000000000000b000
                filesz: 0x000000000000b000
[DEBUG]  it's not compressed!
[SPEW ]  [ 0xd8407000, d8412000, 0xd8412000) &amp;lt;- 9faa5280
[DEBUG]  Loading segment from ROM address 0x9f804264
[DEBUG]    Entry Point 0x1468f000
[SPEW ]  Loaded segments

Change-Id: I5498f418ae7ccc4a8ad2ca05698da3e0a3ec5609
Signed-off-by: Venkateshwar S <vens@qualcomm.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89548
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/arch/arm64/Kconfig     | 8 ++++++++
 src/arch/arm64/Makefile.mk | 4 ++++
 src/arch/arm64/bl31.c      | 9 +++++++--
 3 files changed, 19 insertions(+), 2 deletions(-)

diff --git a/src/arch/arm64/Kconfig b/src/arch/arm64/Kconfig
index af5050b21b..9853ceddc0 100644
--- a/src/arch/arm64/Kconfig
+++ b/src/arch/arm64/Kconfig
@@ -68,6 +68,14 @@ config ARM64_USE_SECURE_OS
 	default n
 	depends on ARM64_USE_ARM_TRUSTED_FIRMWARE
 
+config ARM64_USE_SECURE_OS_PAYLOAD
+	bool
+	default n
+	depends on ARM64_USE_SECURE_OS
+	help
+	  This option adds support for packing the SECURE_OS image as a CBFS
+	  payload type when it spans non-contiguous memory regions.
+
 config ARM64_SECURE_OS_FILE
 	string "Secure OS binary file"
 	depends on ARM64_USE_SECURE_OS
diff --git a/src/arch/arm64/Makefile.mk b/src/arch/arm64/Makefile.mk
index f54c6d22fc..279d31fb47 100644
--- a/src/arch/arm64/Makefile.mk
+++ b/src/arch/arm64/Makefile.mk
@@ -219,7 +219,11 @@ ifeq ($(CONFIG_ARM64_USE_SECURE_OS),y)
 SECURE_OS_FILE := $(CONFIG_ARM64_SECURE_OS_FILE)
 SECURE_OS_FILE_CBFS := $(CONFIG_CBFS_PREFIX)/secure_os
 $(SECURE_OS_FILE_CBFS)-file := $(SECURE_OS_FILE)
+ifeq ($(CONFIG_ARM64_USE_SECURE_OS_PAYLOAD),y)
+$(SECURE_OS_FILE_CBFS)-type := payload
+else
 $(SECURE_OS_FILE_CBFS)-type := stage
+endif # CONFIG_ARM64_USE_SECURE_OS_PAYLOAD
 cbfs-files-y += $(SECURE_OS_FILE_CBFS)
 
 check-ramstage-overlap-files += $(SECURE_OS_FILE_CBFS)
diff --git a/src/arch/arm64/bl31.c b/src/arch/arm64/bl31.c
index 06676bcab8..a0402d7351 100644
--- a/src/arch/arm64/bl31.c
+++ b/src/arch/arm64/bl31.c
@@ -84,8 +84,13 @@ void run_bl31(u64 payload_entry, u64 payload_arg0, u64 payload_spsr)
 		struct prog bl32 = PROG_INIT(PROG_BL32,
 					     CONFIG_CBFS_PREFIX"/secure_os");
 
-		if (cbfs_prog_stage_load(&bl32))
-			die("BL32 load failed");
+		if (CONFIG(ARM64_USE_SECURE_OS_PAYLOAD)) {
+			if (!selfload(&bl32))
+				die("BL32 load failed");
+		} else {
+			if (cbfs_prog_stage_load(&bl32))
+				die("BL32 load failed");
+		}
 
 		bl32_ep_info.pc = (uintptr_t)prog_entry(&bl32);
 		bl32_ep_info.spsr = SPSR_EXCEPTION_MASK |

From 4a3cc37cbd64bff7e128326a220bd818989ee1b7 Mon Sep 17 00:00:00 2001
From: Elyes Haouas <ehaouas@noos.fr>
Date: Mon, 28 Jul 2025 17:55:43 +0200
Subject: [PATCH 2303/3886] crossgcc: Upgrade binutils from version 2.44 to
 2.45

Change-Id: I050cbe134fa7fd653a87234398d7be0d71c0bc3c
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88593
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
---
 util/crossgcc/buildgcc                                          | 2 +-
 ...{binutils-2.44_as-ipxe.patch => binutils-2.45_as-ipxe.patch} | 0
 ...s-2.44_no-makeinfo.patch => binutils-2.45_no-makeinfo.patch} | 0
 util/crossgcc/sum/binutils-2.44.tar.xz.cksum                    | 1 -
 util/crossgcc/sum/binutils-2.45.tar.xz.cksum                    | 1 +
 5 files changed, 2 insertions(+), 2 deletions(-)
 rename util/crossgcc/patches/{binutils-2.44_as-ipxe.patch => binutils-2.45_as-ipxe.patch} (100%)
 rename util/crossgcc/patches/{binutils-2.44_no-makeinfo.patch => binutils-2.45_no-makeinfo.patch} (100%)
 delete mode 100644 util/crossgcc/sum/binutils-2.44.tar.xz.cksum
 create mode 100644 util/crossgcc/sum/binutils-2.45.tar.xz.cksum

diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc
index 832ee2ce28..cf4a8d6bce 100755
--- a/util/crossgcc/buildgcc
+++ b/util/crossgcc/buildgcc
@@ -41,7 +41,7 @@ MPFR_VERSION=4.2.2
 MPC_VERSION=1.3.1
 # Core GCC components
 GCC_VERSION=14.2.0
-BINUTILS_VERSION=2.44
+BINUTILS_VERSION=2.45
 LIBSTDCXX_VERSION="${GCC_VERSION}"	# GCC-specific C++ library
 
 # Low-level Tools (built after GCC)
diff --git a/util/crossgcc/patches/binutils-2.44_as-ipxe.patch b/util/crossgcc/patches/binutils-2.45_as-ipxe.patch
similarity index 100%
rename from util/crossgcc/patches/binutils-2.44_as-ipxe.patch
rename to util/crossgcc/patches/binutils-2.45_as-ipxe.patch
diff --git a/util/crossgcc/patches/binutils-2.44_no-makeinfo.patch b/util/crossgcc/patches/binutils-2.45_no-makeinfo.patch
similarity index 100%
rename from util/crossgcc/patches/binutils-2.44_no-makeinfo.patch
rename to util/crossgcc/patches/binutils-2.45_no-makeinfo.patch
diff --git a/util/crossgcc/sum/binutils-2.44.tar.xz.cksum b/util/crossgcc/sum/binutils-2.44.tar.xz.cksum
deleted file mode 100644
index fd3669abff..0000000000
--- a/util/crossgcc/sum/binutils-2.44.tar.xz.cksum
+++ /dev/null
@@ -1 +0,0 @@
-c8c9f5ae46ab9e3722c71821982d2c270e267748  tarballs/binutils-2.44.tar.xz
diff --git a/util/crossgcc/sum/binutils-2.45.tar.xz.cksum b/util/crossgcc/sum/binutils-2.45.tar.xz.cksum
new file mode 100644
index 0000000000..05d55b3fc5
--- /dev/null
+++ b/util/crossgcc/sum/binutils-2.45.tar.xz.cksum
@@ -0,0 +1 @@
+09fd8a50a95be4a94412fe3847d16280996679c5  tarballs/binutils-2.45.tar.xz

From 668ea970757c1191f408a32fc47be7684dea2e30 Mon Sep 17 00:00:00 2001
From: Elyes Haouas <ehaouas@noos.fr>
Date: Wed, 24 Sep 2025 16:57:57 +0200
Subject: [PATCH 2304/3886] commonlib/endian: Silence GCC -Warray-bounds false
 positives

Recent GCC versions (>=12) warn about out-of-bounds accesses when
writing through *(volatile uint8_t *)dest in endian.h.
This is a false positive since these pointers intentionally alias
hardware/physical memory.

Change-Id: Ia47aa1214998dbc17bd4a58f7d996bcc6fff7b6a
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89328
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
---
 src/commonlib/include/commonlib/endian.h | 7 ++++++-
 1 file changed, 6 insertions(+), 1 deletion(-)

diff --git a/src/commonlib/include/commonlib/endian.h b/src/commonlib/include/commonlib/endian.h
index 971854c2b3..24b10826f4 100644
--- a/src/commonlib/include/commonlib/endian.h
+++ b/src/commonlib/include/commonlib/endian.h
@@ -7,6 +7,11 @@
 #include <stdint.h>
 #include <string.h>
 
+/* GCC >= 12 triggers false positives (-Warray-bounds) on
+ * deliberate low-level memory accesses here. */
+#pragma GCC diagnostic push
+#pragma GCC diagnostic ignored "-Warray-bounds"
+
 /* Endian agnostic functions working on single byte. */
 
 static inline uint8_t read_ble8(const void *src)
@@ -247,4 +252,4 @@ static inline void zero_n(void *dest, size_t n)
 	memset(dest, 0, n);
 }
 
-#endif
+#endif /* _COMMONLIB_ENDIAN_H_ */

From 6ffbc9a929550d7861d0f5aa4f9b9734c1f7b1df Mon Sep 17 00:00:00 2001
From: Vince Liu <vince-wl.liu@mediatek.corp-partner.google.com>
Date: Fri, 17 Oct 2025 11:03:56 +0800
Subject: [PATCH 2305/3886] soc/mediatek: Move mtk_dsi_reset() to
 mtk_dsi_common.c for reuse

Move mtk_dsi_reset() from mtk_mipi_dphy.c to mtk_dsi_common.c so that it
can also be used when using the C-PHY interface, improving code reuse.

BUG=b:433422905,b:428854543
BRANCH=skywaler
TEST=build passed

Signed-off-by: Vince Liu <vince-wl.liu@mediatek.corp-partner.google.com>
Change-Id: I3f080127af4411584f66e307f7d2b13abbb051bf
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89619
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
---
 src/soc/mediatek/common/mtk_dsi_common.c | 12 ++++++++++++
 src/soc/mediatek/common/mtk_mipi_dphy.c  |  8 --------
 src/soc/mediatek/mt8183/Makefile.mk      |  1 +
 src/soc/mediatek/mt8186/Makefile.mk      |  1 +
 src/soc/mediatek/mt8188/Makefile.mk      |  1 +
 src/soc/mediatek/mt8192/Makefile.mk      |  1 +
 6 files changed, 16 insertions(+), 8 deletions(-)
 create mode 100644 src/soc/mediatek/common/mtk_dsi_common.c

diff --git a/src/soc/mediatek/common/mtk_dsi_common.c b/src/soc/mediatek/common/mtk_dsi_common.c
new file mode 100644
index 0000000000..67654b1630
--- /dev/null
+++ b/src/soc/mediatek/common/mtk_dsi_common.c
@@ -0,0 +1,12 @@
+/* SPDX-License-Identifier: GPL-2.0-only OR MIT */
+
+#include <device/mmio.h>
+#include <soc/dsi.h>
+
+void mtk_dsi_reset(void)
+{
+	write32(&dsi0->dsi_force_commit,
+		DSI_FORCE_COMMIT_USE_MMSYS | DSI_FORCE_COMMIT_ALWAYS);
+	write32(&dsi0->dsi_con_ctrl, 1);
+	write32(&dsi0->dsi_con_ctrl, 0);
+}
diff --git a/src/soc/mediatek/common/mtk_mipi_dphy.c b/src/soc/mediatek/common/mtk_mipi_dphy.c
index fa73ddb4e6..d50a7898be 100644
--- a/src/soc/mediatek/common/mtk_mipi_dphy.c
+++ b/src/soc/mediatek/common/mtk_mipi_dphy.c
@@ -61,11 +61,3 @@ void mtk_dsi_configure_mipi_tx(u32 data_rate, u32 lanes)
 
 	setbits32(&mipi_tx->ck_ckmode_en, DSI_CK_CKMODE_EN);
 }
-
-void mtk_dsi_reset(void)
-{
-	write32(&dsi0->dsi_force_commit,
-		DSI_FORCE_COMMIT_USE_MMSYS | DSI_FORCE_COMMIT_ALWAYS);
-	write32(&dsi0->dsi_con_ctrl, 1);
-	write32(&dsi0->dsi_con_ctrl, 0);
-}
diff --git a/src/soc/mediatek/mt8183/Makefile.mk b/src/soc/mediatek/mt8183/Makefile.mk
index c1fd3b8a7a..a4aa9db0ea 100644
--- a/src/soc/mediatek/mt8183/Makefile.mk
+++ b/src/soc/mediatek/mt8183/Makefile.mk
@@ -55,6 +55,7 @@ ramstage-y += ../common/i2c.c i2c.c
 ramstage-y += ../common/mcu.c
 ramstage-y += ../common/mmu_operations.c mmu_operations.c
 ramstage-y += ../common/mtcmos.c mtcmos.c
+ramstage-y += ../common/mtk_dsi_common.c
 ramstage-y += ../common/pmic_wrap.c
 ramstage-y += ../common/rtc.c ../common/rtc_pwrap_ops.c ../common/rtc_osc_init.c rtc.c
 ramstage-y += soc.c
diff --git a/src/soc/mediatek/mt8186/Makefile.mk b/src/soc/mediatek/mt8186/Makefile.mk
index 080cc1337f..6625988edd 100644
--- a/src/soc/mediatek/mt8186/Makefile.mk
+++ b/src/soc/mediatek/mt8186/Makefile.mk
@@ -47,6 +47,7 @@ ramstage-y += ../common/mcu.c
 ramstage-y += ../common/mmu_operations.c
 ramstage-$(CONFIG_COMMONLIB_STORAGE_MMC) += ../common/msdc.c msdc.c
 ramstage-y += ../common/mtcmos.c mtcmos.c
+ramstage-y += ../common/mtk_dsi_common.c
 ramstage-y += ../common/pmic_wrap.c pmic_wrap.c pmif.c mt6366.c
 ramstage-y += ../common/rtc.c ../common/rtc_pwrap_ops.c ../common/rtc_osc_init.c rtc.c
 ramstage-y += soc.c
diff --git a/src/soc/mediatek/mt8188/Makefile.mk b/src/soc/mediatek/mt8188/Makefile.mk
index f8a7faa577..fa9a8f119a 100644
--- a/src/soc/mediatek/mt8188/Makefile.mk
+++ b/src/soc/mediatek/mt8188/Makefile.mk
@@ -54,6 +54,7 @@ ramstage-y += ../common/mmu_operations.c
 ramstage-$(CONFIG_COMMONLIB_STORAGE_MMC) += ../common/msdc.c msdc.c
 ramstage-y += ../common/mt6359p.c mt6359p.c
 ramstage-y += ../common/mtcmos.c mtcmos.c
+ramstage-y += ../common/mtk_dsi_common.c
 ramstage-y += ../common/pmif.c ../common/pmif_clk.c ../common/pmif_init.c pmif_clk.c
 ramstage-y += ../common/pmif_spi.c pmif_spi.c
 ramstage-y += ../common/pmif_spmi.c ../common/pmif_spmi_v1.c pmif_spmi.c
diff --git a/src/soc/mediatek/mt8192/Makefile.mk b/src/soc/mediatek/mt8192/Makefile.mk
index ae75f13eb2..eaf7bc1856 100644
--- a/src/soc/mediatek/mt8192/Makefile.mk
+++ b/src/soc/mediatek/mt8192/Makefile.mk
@@ -47,6 +47,7 @@ ramstage-y += ../common/mcupm.c
 ramstage-y += ../common/mmu_operations.c
 ramstage-$(CONFIG_COMMONLIB_STORAGE_MMC) += ../common/msdc.c msdc.c
 ramstage-y += ../common/mtcmos.c mtcmos.c
+ramstage-y += ../common/mtk_dsi_common.c
 ramstage-y += ../common/pmif.c ../common/pmif_init.c
 ramstage-y += ../common/rtc.c ../common/rtc_mt6359p.c
 ramstage-y += soc.c

From 7376761bdf94fe6ca6bdca8908a45037a9d7ba2b Mon Sep 17 00:00:00 2001
From: Luca Lai <luca.lai@lcfc.corp-partner.google.com>
Date: Mon, 20 Oct 2025 16:40:49 +0800
Subject: [PATCH 2306/3886] mb/nissa/var/pujjoquince: Modify fingerprint
 configuration

Adjust fingerprint power sequence to let the time interval between PP3300_MCU and MCU_RST_ODL H(GPP_E7) is 5.1ms(before is 1.1s), meet spec 5.95ms.

BUG=b:411558536
BRANCH=none
TEST=Build and boot to OS. Verify fingerprint power sequence by
EE colleagues.

Change-Id: Ic93af108144a3f227024a8749e0cf88b2f2d90ff
Signed-off-by: Luca Lai <luca.lai@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89644
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Derek Huang <derekhuang@google.com>
---
 .../google/brya/variants/pujjolo/gpio.c       | 28 +++++--------------
 .../brya/variants/pujjolo/overridetree.cb     |  2 +-
 2 files changed, 8 insertions(+), 22 deletions(-)

diff --git a/src/mainboard/google/brya/variants/pujjolo/gpio.c b/src/mainboard/google/brya/variants/pujjolo/gpio.c
index 427a1701b9..15590d9479 100644
--- a/src/mainboard/google/brya/variants/pujjolo/gpio.c
+++ b/src/mainboard/google/brya/variants/pujjolo/gpio.c
@@ -169,7 +169,7 @@ static const struct pad_config override_gpio_table[] = {
 	/* E6  : THC0_SPI1_RST# ==> GPP_E6_STRAP */
 	PAD_NC_LOCK(GPP_E6, NONE, LOCK_CONFIG),
 	/* E7  : NC ==> FP_RST_ODL */
-	PAD_CFG_GPO_LOCK(GPP_E7, 1, LOCK_CONFIG),
+	PAD_CFG_GPO_LOCK(GPP_E7, 0, LOCK_CONFIG),
 	/* E8  : GPP_E8 ==> WLAN_DISABLE_L */
 	PAD_CFG_GPO(GPP_E8, 1, DEEP),
 	/* E9  : NC ==> DIMM_CHANNEL_SELECT */
@@ -428,17 +428,10 @@ static const struct pad_config early_gpio_table[] = {
 	PAD_CFG_GPO(GPP_D6, 0, DEEP),
 	/* E12 : THC0_SPI1_IO1 ==> SOC_WP_OD */
 	PAD_CFG_GPI_GPIO_DRIVER(GPP_E12, NONE, DEEP),
-	/*
-	 * E7 ==> FP_RST_ODL
-	 * FP_RST_ODL comes out of reset as hi-z and does not have an external pull-down.
-	 * To ensure proper power sequencing for the FPMCU device, reset signal is driven low
-	 * early on in bootblock, followed by enabling of power. Reset signal is deasserted
-	 * later on in ramstage. Since reset signal is asserted in bootblock, it results in
-	 * FPMCU not working after a S3 resume. This is a known issue.
-	 */
+	/* E7 ==> FP_RST_ODL */
 	PAD_CFG_GPO(GPP_E7, 0, DEEP),
 	/* D2  : ISH_GP2 ==> EN_FP_PWR */
-	PAD_CFG_GPO(GPP_D2, 1, DEEP),
+	PAD_CFG_GPO(GPP_D2, 0, DEEP),
 	/* E9  : DIMM_CHANNEL_SELECT */
 	PAD_CFG_GPI_LOCK(GPP_E9, DN_20K, LOCK_CONFIG),
 	/* E17 : WWAN_RST_L */
@@ -466,17 +459,10 @@ static const struct pad_config romstage_gpio_table[] = {
 	PAD_CFG_GPO(GPP_C0, 1, DEEP),
 	/* C1  : SMBDATA ==> USI_RST_L */
 	PAD_CFG_TERM_GPO(GPP_C1, 0, UP_20K, DEEP),
-	/*
-	 * E7 ==> FP_RST_ODL
-	 * FP_RST_ODL comes out of reset as hi-z and does not have an external pull-down.
-	 * To ensure proper power sequencing for the FPMCU device, reset signal is driven low
-	 * early on in bootblock, followed by enabling of power. Reset signal is deasserted
-	 * later on in ramstage. Since reset signal is asserted in bootblock, it results in
-	 * FPMCU not working after a S3 resume. This is a known issue.
-	 */
-	 PAD_CFG_GPO(GPP_E7, 0, DEEP),
-	 /* D2  : ISH_GP2 ==> EN_FP_PWR */
-	 PAD_CFG_GPO(GPP_D2, 0, DEEP),
+	/* E7 ==> FP_RST_ODL */
+	PAD_CFG_GPO(GPP_E7, 0, DEEP),
+	/* D2  : ISH_GP2 ==> EN_FP_PWR */
+	PAD_CFG_GPO(GPP_D2, 0, DEEP),
 	/* H12 : UART0_RTS# ==> SD_PERST_L */
 	PAD_CFG_GPO(GPP_H12, 1, DEEP),
 };
diff --git a/src/mainboard/google/brya/variants/pujjolo/overridetree.cb b/src/mainboard/google/brya/variants/pujjolo/overridetree.cb
index 60f6393c48..7fa77801b2 100644
--- a/src/mainboard/google/brya/variants/pujjolo/overridetree.cb
+++ b/src/mainboard/google/brya/variants/pujjolo/overridetree.cb
@@ -733,7 +733,7 @@ chip soc/intel/alderlake
 				register "has_power_resource" = "1"
 				register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_E7)"
 				register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D2)"
-				register "enable_delay_ms" = "3"
+				register "enable_delay_ms" = "10"
 				device spi 0 on
 					probe FP FP_PRESENT
 				end

From 3dee4cd0c08ede0391d861a03c3e1e54bd460ad3 Mon Sep 17 00:00:00 2001
From: Cliff Huang <cliff.huang@intel.com>
Date: Wed, 1 Oct 2025 11:09:29 -0700
Subject: [PATCH 2307/3886] soc/intel/pantherlake: Correct Touch Controller
 Speed Configuration
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

The touch controller's I2C bus speed configuration was previously set
directly through register values. This update introduces the use of the
I2C speed enum type to specify the desired connection speed, improving
clarity and reducing the risk of errors. A mapping function has been
added to convert the I2C speed enum into the appropriate register
value, factoring in the SoC's specific divider configuration. This
change ensures that the speed assignment aligns with the expected
operational parameters of the Panther Lake SoC touch controller.

BUG=none
TEST=Boot Fatcat board to OS and verify that the I2C speed assignments
are correct for the register value in SSDT.

Signed-off-by: Cliff Huang <cliff.huang@intel.com>
Change-Id: I32e71ddcab77af2119c012bd3276f83c1bcea954
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89396
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Reviewed-by: Jamie Ryu <jamie.m.ryu@intel.com>
---
 src/soc/intel/pantherlake/include/soc/touch.h |  6 +++--
 src/soc/intel/pantherlake/touch.c             | 22 +++++++++++++++++--
 2 files changed, 24 insertions(+), 4 deletions(-)

diff --git a/src/soc/intel/pantherlake/include/soc/touch.h b/src/soc/intel/pantherlake/include/soc/touch.h
index 33b3d1db2e..c954437fa8 100644
--- a/src/soc/intel/pantherlake/include/soc/touch.h
+++ b/src/soc/intel/pantherlake/include/soc/touch.h
@@ -3,6 +3,8 @@
 #ifndef _SOC_PANTHERLAKE_TOUCH_H_
 #define _SOC_PANTHERLAKE_TOUCH_H_
 
+#include <commonlib/bsd/helpers.h>
+
 /* For THC-I2C: */
 
 /*
@@ -54,8 +56,8 @@
 /* unit: ms */
 #define SOC_PTL_THC_RST_SEQ_DLY                   300
 
-/* The initial default speed is 17000000 Hz. */
-#define SOC_PTL_THC_CONNECTION_SPEED         17000000
+/* The initial default speed is 17 MHz. */
+#define SOC_PTL_THC_SPI_CONNECTION_SPEED         (17 * MHz)
 
 /* 0 = no limit */
 #define SOC_PTL_THC_HIDSPI_LIMIT_PKT_SZ             0
diff --git a/src/soc/intel/pantherlake/touch.c b/src/soc/intel/pantherlake/touch.c
index ed475fe837..f09bd43187 100644
--- a/src/soc/intel/pantherlake/touch.c
+++ b/src/soc/intel/pantherlake/touch.c
@@ -3,11 +3,29 @@
 #include <drivers/intel/touch/chip.h>
 #include <soc/touch.h>
 
+/* Convert I2C speed into value for the register in SoC */
+static uint64_t get_soc_thc_i2c_bus_freq_val(uint32_t speed)
+{
+	switch (speed) {
+	case I2C_SPEED_FAST_PLUS:
+		return SOC_PTL_THC_I2C_CONNECTION_SPEED_FMP;
+	case I2C_SPEED_FAST:
+		return SOC_PTL_THC_I2C_CONNECTION_SPEED_FM;
+	case I2C_SPEED_STANDARD:
+		return SOC_PTL_THC_I2C_CONNECTION_SPEED_SM;
+	case 0: /* If not specified in the device tree, SoC, and device, standard speed is used */
+		return SOC_PTL_THC_I2C_CONNECTION_SPEED_SM;
+	default:
+		die("Fail to map %d Hz to proper I2C speed.\n", speed);
+	}
+}
+
 /* SoC-specific THC-I2C config */
 const struct intel_thc_hidi2c_info *soc_get_thc_hidi2c_info(void)
 {
 	static const struct intel_thc_hidi2c_info soc_thc_hidi2c_info = {
-		.connection_speed		= SOC_PTL_THC_I2C_CONNECTION_SPEED_FM,
+		.connection_speed		= I2C_SPEED_FAST, /* 400KHz */
+		.get_soc_i2c_bus_speed_val_func	= get_soc_thc_i2c_bus_freq_val,
 		.addr_mode			= SOC_PTL_THC_I2C_ADDR_MODE,
 		.sm_scl_high_period		= SOC_PTL_THC_I2C_SM_SCL_HIGH_PERIOD,
 		.sm_scl_low_period		= SOC_PTL_THC_I2C_SM_SCL_LOW_PERIOD,
@@ -35,7 +53,7 @@ const struct intel_thc_hidi2c_info *soc_get_thc_hidi2c_info(void)
 const struct intel_thc_hidspi_info *soc_get_thc_hidspi_info(void)
 {
 	static const struct intel_thc_hidspi_info soc_thc_hidspi_info = {
-		.connection_speed	= SOC_PTL_THC_CONNECTION_SPEED,
+		.connection_speed	= SOC_PTL_THC_SPI_CONNECTION_SPEED,
 		.write_mode		= HIDSPI_WRITE_MODE_MULTI_SINGLE_SPI,
 		.limit_packet_size	= SOC_PTL_THC_HIDSPI_LIMIT_PKT_SZ,
 		.performance_limit	= SOC_PTL_THC_PERFORMANCE_LIMIT,

From fc736de10e621a447218c5dc30d4668aacd1e836 Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Mon, 20 Oct 2025 10:26:31 +0100
Subject: [PATCH 2308/3886] ec/starlabs/merlin: Remove the
 EC_STARLABS_NEED_ITE_BIN option

None of these boards strictly "need" an ITE binary, so remove the
Kconfig option. This leaves the logic to add a binary untouched,
so it can be added if desired.

Change-Id: I6cd674a794cac51900b9a11c434b25e28a052b6a
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89645
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/ec/starlabs/merlin/Kconfig              | 7 -------
 src/ec/starlabs/merlin/Makefile.mk          | 2 --
 src/mainboard/starlabs/byte_adl/Kconfig     | 2 --
 src/mainboard/starlabs/starbook/Kconfig     | 5 -----
 src/mainboard/starlabs/starfighter/Kconfig  | 2 --
 src/mainboard/starlabs/starlite_adl/Kconfig | 2 --
 6 files changed, 20 deletions(-)

diff --git a/src/ec/starlabs/merlin/Kconfig b/src/ec/starlabs/merlin/Kconfig
index 52690e33dc..d2f59a64fb 100644
--- a/src/ec/starlabs/merlin/Kconfig
+++ b/src/ec/starlabs/merlin/Kconfig
@@ -17,16 +17,9 @@ config EC_STARLABS_ITE
 	  KBL - 3.12 or later
 	  And open-source Merlin firmware version 1.00 or later
 
-config EC_STARLABS_NEED_ITE_BIN
-	bool
-	depends on EC_STARLABS_ITE
-	help
-	  Select if the mainboard requires EC firmware in the main flash chip.
-
 config EC_STARLABS_ADD_ITE_BIN
 	bool "Add Star Labs EC binary file"
 	default n
-	depends on EC_STARLABS_NEED_ITE_BIN
 	help
 	  Select to add an EC firmware binary into the coreboot image. EC firmware
 	  is necessary, flashing a coreboot image without EC firmware will render
diff --git a/src/ec/starlabs/merlin/Makefile.mk b/src/ec/starlabs/merlin/Makefile.mk
index 841b65959a..e1163c9f66 100644
--- a/src/ec/starlabs/merlin/Makefile.mk
+++ b/src/ec/starlabs/merlin/Makefile.mk
@@ -10,7 +10,6 @@ CPPFLAGS_common += -I$(src)/ec/starlabs/merlin/variants/$(EC_VARIANT_DIR)
 
 all-y += ite.c
 
-ifeq ($(CONFIG_EC_STARLABS_NEED_ITE_BIN),y)
 ifeq ($(CONFIG_EC_STARLABS_ADD_ITE_BIN),y)
 add_ite_fw: $(obj)/coreboot.pre
 	$(CBFSTOOL) $(obj)/coreboot.pre write -r EC -f $(CONFIG_EC_STARLABS_ITE_BIN_PATH) -u
@@ -25,7 +24,6 @@ warn_no_ite_fw:
 	printf "may not respond when you press it.\n\n"
 endif
 endif
-endif
 
 ifeq ($(CONFIG_EC_STARLABS_NUVOTON),y)
 
diff --git a/src/mainboard/starlabs/byte_adl/Kconfig b/src/mainboard/starlabs/byte_adl/Kconfig
index 8054269b48..f3cc349142 100644
--- a/src/mainboard/starlabs/byte_adl/Kconfig
+++ b/src/mainboard/starlabs/byte_adl/Kconfig
@@ -9,7 +9,6 @@ config BOARD_STARLABS_BYTE_SERIES
 	select DRIVERS_OPTION_CFR_ENABLED
 	select EC_STARLABS_ITE
 	select EC_STARLABS_MERLIN
-	select EC_STARLABS_NEED_ITE_BIN
 	select HAVE_ACPI_RESUME
 	select HAVE_ACPI_TABLES
 	select HAVE_INTEL_PTT
@@ -57,7 +56,6 @@ config EC_GPE_SCI
 
 config EC_STARLABS_ITE_BIN_PATH
 	string
-	depends on EC_STARLABS_NEED_ITE_BIN
 	default "3rdparty/blobs/mainboard/\$(MAINBOARDDIR)/\$(CONFIG_VARIANT_DIR)/ec.bin"
 
 config EC_VARIANT_DIR
diff --git a/src/mainboard/starlabs/starbook/Kconfig b/src/mainboard/starlabs/starbook/Kconfig
index b6bcc47f9b..0853c1873d 100644
--- a/src/mainboard/starlabs/starbook/Kconfig
+++ b/src/mainboard/starlabs/starbook/Kconfig
@@ -39,7 +39,6 @@ config BOARD_STARLABS_LABTOP_CML
 	select EC_STARLABS_LID_SWITCH
 	select EC_STARLABS_MAX_CHARGE
 	select EC_STARLABS_MERLIN
-	select EC_STARLABS_NEED_ITE_BIN
 	select HAVE_INTEL_PTT
 	select HAVE_SPD_IN_CBFS
 	select CRB_TPM
@@ -57,7 +56,6 @@ config BOARD_STARLABS_STARBOOK_TGL
 	select EC_STARLABS_LID_SWITCH
 	select EC_STARLABS_MAX_CHARGE
 	select EC_STARLABS_MERLIN
-	select EC_STARLABS_NEED_ITE_BIN
 	select MAINBOARD_HAS_TPM2
 	select MEMORY_MAPPED_TPM
 	select SOC_INTEL_COMMON_BLOCK_TCSS
@@ -75,7 +73,6 @@ config BOARD_STARLABS_STARBOOK_ADL_COMMON
 	select EC_STARLABS_LID_SWITCH
 	select EC_STARLABS_MAX_CHARGE
 	select EC_STARLABS_MERLIN
-	select EC_STARLABS_NEED_ITE_BIN
 	select DRIVERS_GFX_GENERIC
 	select MAINBOARD_HAS_TPM2
 	select MEMORY_MAPPED_TPM
@@ -114,7 +111,6 @@ config BOARD_STARLABS_STARBOOK_MTL
 	select EC_STARLABS_LID_SWITCH
 	select EC_STARLABS_MAX_CHARGE
 	select EC_STARLABS_MERLIN
-	select EC_STARLABS_NEED_ITE_BIN
 	select MAINBOARD_HAS_TPM2
 	select MEMORY_MAPPED_TPM
 	select PMC_IPC_ACPI_INTERFACE
@@ -165,7 +161,6 @@ config EC_STARLABS_BATTERY_OEM
 
 config EC_STARLABS_ITE_BIN_PATH
 	string
-	depends on EC_STARLABS_NEED_ITE_BIN
 	default "3rdparty/blobs/mainboard/\$(MAINBOARDDIR)/\$(CONFIG_VARIANT_DIR)/ec.bin"
 
 config EC_VARIANT_DIR
diff --git a/src/mainboard/starlabs/starfighter/Kconfig b/src/mainboard/starlabs/starfighter/Kconfig
index 8dfbf1b101..d29427f373 100644
--- a/src/mainboard/starlabs/starfighter/Kconfig
+++ b/src/mainboard/starlabs/starfighter/Kconfig
@@ -18,7 +18,6 @@ config BOARD_STARLABS_STARFIGHTER_SERIES
 	select EC_STARLABS_LID_SWITCH
 	select EC_STARLABS_MAX_CHARGE
 	select EC_STARLABS_MERLIN
-	select EC_STARLABS_NEED_ITE_BIN
 	select HAVE_ACPI_RESUME
 	select HAVE_ACPI_TABLES
 	select HAVE_CMOS_DEFAULT
@@ -78,7 +77,6 @@ config EC_STARLABS_BATTERY_OEM
 
 config EC_STARLABS_ITE_BIN_PATH
 	string
-	depends on EC_STARLABS_NEED_ITE_BIN
 	default "3rdparty/blobs/mainboard/\$(MAINBOARDDIR)/\$(CONFIG_VARIANT_DIR)/ec.bin"
 
 config EC_VARIANT_DIR
diff --git a/src/mainboard/starlabs/starlite_adl/Kconfig b/src/mainboard/starlabs/starlite_adl/Kconfig
index ae86ef63dc..638fe72d0e 100644
--- a/src/mainboard/starlabs/starlite_adl/Kconfig
+++ b/src/mainboard/starlabs/starlite_adl/Kconfig
@@ -14,7 +14,6 @@ config BOARD_STARLABS_STARLITE_SERIES
 	select EC_STARLABS_LID_SWITCH
 	select EC_STARLABS_MAX_CHARGE
 	select EC_STARLABS_MERLIN
-	select EC_STARLABS_NEED_ITE_BIN
 	select EC_STARLABS_POWER_LED
 	select HAVE_ACPI_RESUME
 	select HAVE_ACPI_TABLES
@@ -71,7 +70,6 @@ config EC_STARLABS_BATTERY_OEM
 
 config EC_STARLABS_ITE_BIN_PATH
 	string
-	depends on EC_STARLABS_NEED_ITE_BIN
 	default "3rdparty/blobs/mainboard/\$(MAINBOARDDIR)/\$(CONFIG_VARIANT_DIR)/ec.bin"
 
 config EC_VARIANT_DIR

From f6743fba2995a6f106c324aa857182bfceff2558 Mon Sep 17 00:00:00 2001
From: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
Date: Thu, 16 Oct 2025 18:43:15 +0800
Subject: [PATCH 2309/3886] mb/google/fatcat/var/moonstone: Enable Intel DPTF
 support

Add initial thermal settings
- Remove fan control (handled by EC)
- Apply PL1/PL2 min & max values per thermal design

BUG=b:446813859
TEST=emerge-fatcat coreboot

Change-Id: I193951036abb9a37af6583de0b1401501524b2d8
Signed-off-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89609
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Pranava Y N <pranavayn@google.com>
Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com>
---
 .../fatcat/variants/moonstone/overridetree.cb | 93 +++++++++++++++++++
 1 file changed, 93 insertions(+)

diff --git a/src/mainboard/google/fatcat/variants/moonstone/overridetree.cb b/src/mainboard/google/fatcat/variants/moonstone/overridetree.cb
index be75530d76..b006a20f7a 100644
--- a/src/mainboard/google/fatcat/variants/moonstone/overridetree.cb
+++ b/src/mainboard/google/fatcat/variants/moonstone/overridetree.cb
@@ -123,6 +123,99 @@ chip soc/intel/pantherlake
 			end
 		end
 
+		device ref dtt on
+			chip drivers/intel/dptf
+				## sensor information
+				register "options.tsr[0].desc" = ""DDR_SOC""
+				register "options.tsr[1].desc" = ""Ambient""
+				register "options.tsr[2].desc" = ""Charger""
+
+				## Active Policy
+				# FIXME: below values are initial reference values only
+				register "policies.active" = "{
+						[0] = {
+							.target = DPTF_TEMP_SENSOR_0,
+							.thresholds = {
+									TEMP_PCT(70, 97),
+									TEMP_PCT(65, 90),
+									TEMP_PCT(60, 80),
+									TEMP_PCT(55, 75),
+									TEMP_PCT(50, 65),
+									TEMP_PCT(45, 45),
+									TEMP_PCT(43, 30),
+								}
+							},
+						[1] = {
+							.target = DPTF_TEMP_SENSOR_1,
+							.thresholds = {
+									TEMP_PCT(70, 97),
+									TEMP_PCT(65, 90),
+									TEMP_PCT(60, 80),
+									TEMP_PCT(55, 75),
+									TEMP_PCT(50, 65),
+									TEMP_PCT(45, 45),
+									TEMP_PCT(43, 30),
+								}
+							},
+						[2] = {
+							.target = DPTF_TEMP_SENSOR_2,
+							.thresholds = {
+									TEMP_PCT(75, 90),
+									TEMP_PCT(70, 80),
+									TEMP_PCT(65, 70),
+									TEMP_PCT(60, 50),
+								}
+							}
+				}"
+
+				## Passive Policy
+				# TODO: below values are initial reference values only
+				register "policies.passive" = "{
+						[0] = DPTF_PASSIVE(CPU,         CPU,           95, 5000),
+						[1] = DPTF_PASSIVE(CPU,         TEMP_SENSOR_0, 80, 5000),
+						[2] = DPTF_PASSIVE(CPU,         TEMP_SENSOR_1, 80, 5000),
+						[3] = DPTF_PASSIVE(CHARGER,     TEMP_SENSOR_2, 75, 5000),
+				}"
+
+				## Critical Policy
+				# TODO: below values are initial reference values only
+				register "policies.critical" = "{
+						[0] = DPTF_CRITICAL(CPU,          105, SHUTDOWN),
+						[1] = DPTF_CRITICAL(TEMP_SENSOR_0, 85, SHUTDOWN),
+						[2] = DPTF_CRITICAL(TEMP_SENSOR_1, 85, SHUTDOWN),
+						[3] = DPTF_CRITICAL(TEMP_SENSOR_2, 85, SHUTDOWN),
+				}"
+
+				## Power Limits Control
+				register "controls.power_limits" = "{
+						.pl1 = {
+							.min_power = 12000,
+							.max_power = 15000,
+							.time_window_min = 28 * MSECS_PER_SEC,
+							.time_window_max = 32 * MSECS_PER_SEC,
+							.granularity = 200,
+						},
+						.pl2 = {
+							.min_power = 55000,
+							.max_power = 55000,
+							.time_window_min = 28 * MSECS_PER_SEC,
+							.time_window_max = 32 * MSECS_PER_SEC,
+							.granularity = 1000,
+						}
+				}"
+
+				## Charger Performance Control (Control, mA)
+				register "controls.charger_perf" = "{
+						[0] = { 255, 3000 },
+						[1] = {  24, 1500 },
+						[2] = {  16, 1000 },
+						[3] = {   8,  500 }
+				}"
+
+				device generic 0 alias dptf_policy on end
+			end
+		end
+
 		device ref iaa off end
 		device ref tbt_pcie_rp0 on end
 		device ref tbt_pcie_rp1 on

From 9ff9f2904be69ba91ef1d63f5d2856b40ebe9a20 Mon Sep 17 00:00:00 2001
From: Kun Liu <liukun11@huaqin.corp-partner.google.com>
Date: Mon, 20 Oct 2025 09:58:29 +0800
Subject: [PATCH 2310/3886] mb/google/bluey/var/quartz: Enable all spi flash
 drivers

We use winbond, gigadevice spi flash, and will use spi flash from other vendors in the future, so we have enable all SPI Flash drivers.

BUG=b:442967024
BRANCH=None
TEST=emerge-bluey coreboot chromeos-bootimage

Change-Id: Icb9eeea90e924d412ad782ccf1ac390707f27314
Signed-off-by: Kun Liu <liukun11@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89641
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/google/bluey/Kconfig | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/mainboard/google/bluey/Kconfig b/src/mainboard/google/bluey/Kconfig
index 0decb59ef2..14c6bdf1c6 100644
--- a/src/mainboard/google/bluey/Kconfig
+++ b/src/mainboard/google/bluey/Kconfig
@@ -43,7 +43,7 @@ config BOARD_GOOGLE_MODEL_QUARTZ
 	select MAINBOARD_HAS_CHROME_EC
 	select MAINBOARD_HAS_FINGERPRINT_VIA_SPI
 	select MAINBOARD_HAS_GOOGLE_TPM
-	select SPI_FLASH_WINBOND
+	select SPI_FLASH_INCLUDE_ALL_DRIVERS
 
 config BOARD_GOOGLE_QUENBI
 	select BOARD_GOOGLE_MODEL_QUENBI

From 8a2c04e04db7b2db5ced00df3bbd6c81778cdbbe Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Mon, 20 Oct 2025 13:56:09 +0100
Subject: [PATCH 2311/3886] mb/starlabs/*/rpl: Re-enable GpioOverride

Now that the PinMux is correctly configured, everything works
as it should without having FSP touch the GPIOs.

Change-Id: Ieec678594f49f3aa003ade29aad85b24ec03f1ad
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89647
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
---
 src/mainboard/starlabs/starbook/variants/rpl/romstage.c    | 1 -
 src/mainboard/starlabs/starfighter/variants/rpl/romstage.c | 1 -
 2 files changed, 2 deletions(-)

diff --git a/src/mainboard/starlabs/starbook/variants/rpl/romstage.c b/src/mainboard/starlabs/starbook/variants/rpl/romstage.c
index 5038a526b7..20d518c5c3 100644
--- a/src/mainboard/starlabs/starbook/variants/rpl/romstage.c
+++ b/src/mainboard/starlabs/starbook/variants/rpl/romstage.c
@@ -46,5 +46,4 @@ void mainboard_memory_init_params(FSPM_UPD *mupd)
 	}
 
 	mupd->FspmConfig.DmiMaxLinkSpeed = 4;
-	mupd->FspmConfig.GpioOverride = 0;
 };
diff --git a/src/mainboard/starlabs/starfighter/variants/rpl/romstage.c b/src/mainboard/starlabs/starfighter/variants/rpl/romstage.c
index 6ec63a16d7..e382582de6 100644
--- a/src/mainboard/starlabs/starfighter/variants/rpl/romstage.c
+++ b/src/mainboard/starlabs/starfighter/variants/rpl/romstage.c
@@ -141,5 +141,4 @@ void mainboard_memory_init_params(FSPM_UPD *mupd)
 	}
 
 	mupd->FspmConfig.DmiMaxLinkSpeed = 4;
-	mupd->FspmConfig.GpioOverride = 0;
 };

From bbdf2eab6ac83b61012cb732fe5dbe2b13d90357 Mon Sep 17 00:00:00 2001
From: Vince Liu <vince-wl.liu@mediatek.corp-partner.google.com>
Date: Tue, 21 Oct 2025 15:48:21 +0800
Subject: [PATCH 2312/3886] soc/mediatek: Rename DSI common files for improved
 readability

Rename `common/dsi.c` to `common/dsi_common.c` since this file is used
by all SoCs. Rename `common/mtk_dsi_common.c` to `common/dsi_v1.c`, as
this file serves as the v1 implementation for all SoCs except mt8173.
These changes help clarify file usage and improve code readability.

BUG=b:433422905,b:428854543
BRANCH=skywaler
TEST=build passed

Signed-off-by: Vince Liu <vince-wl.liu@mediatek.corp-partner.google.com>
Change-Id: Ie711175434febce149a22742d78132842a6ec329
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89655
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
---
 src/soc/mediatek/common/{dsi.c => dsi_common.c}        | 0
 src/soc/mediatek/common/{mtk_dsi_common.c => dsi_v1.c} | 0
 src/soc/mediatek/common/include/soc/dsi_common.h       | 2 +-
 src/soc/mediatek/mt8173/Makefile.mk                    | 2 +-
 src/soc/mediatek/mt8183/Makefile.mk                    | 3 +--
 src/soc/mediatek/mt8186/Makefile.mk                    | 3 +--
 src/soc/mediatek/mt8188/Makefile.mk                    | 3 +--
 src/soc/mediatek/mt8192/Makefile.mk                    | 3 +--
 8 files changed, 6 insertions(+), 10 deletions(-)
 rename src/soc/mediatek/common/{dsi.c => dsi_common.c} (100%)
 rename src/soc/mediatek/common/{mtk_dsi_common.c => dsi_v1.c} (100%)

diff --git a/src/soc/mediatek/common/dsi.c b/src/soc/mediatek/common/dsi_common.c
similarity index 100%
rename from src/soc/mediatek/common/dsi.c
rename to src/soc/mediatek/common/dsi_common.c
diff --git a/src/soc/mediatek/common/mtk_dsi_common.c b/src/soc/mediatek/common/dsi_v1.c
similarity index 100%
rename from src/soc/mediatek/common/mtk_dsi_common.c
rename to src/soc/mediatek/common/dsi_v1.c
diff --git a/src/soc/mediatek/common/include/soc/dsi_common.h b/src/soc/mediatek/common/include/soc/dsi_common.h
index a0acce829b..f5fc70c1c6 100644
--- a/src/soc/mediatek/common/include/soc/dsi_common.h
+++ b/src/soc/mediatek/common/include/soc/dsi_common.h
@@ -197,7 +197,7 @@ void mtk_dsi_configure_mipi_tx(u32 data_rate, u32 lanes);
 /* Functions as weak no-ops that can be overridden. */
 void mtk_dsi_override_phy_timing(struct mtk_phy_timing *timing);
 
-/* Public API provided in common/dsi.c */
+/* Public API provided in common/dsi_common.c */
 int mtk_dsi_bpp_from_format(u32 format);
 int mtk_dsi_init(u32 mode_flags, u32 format, u32 lanes, const struct edid *edid,
 		 const u8 *init_commands);
diff --git a/src/soc/mediatek/mt8173/Makefile.mk b/src/soc/mediatek/mt8173/Makefile.mk
index 49861a71ac..ef969ab24d 100644
--- a/src/soc/mediatek/mt8173/Makefile.mk
+++ b/src/soc/mediatek/mt8173/Makefile.mk
@@ -71,7 +71,7 @@ ramstage-y += ../common/rtc.c ../common/rtc_pwrap_ops.c rtc.c
 ramstage-y += ../common/usb.c usb.c
 
 ramstage-y += ../common/ddp.c ddp.c
-ramstage-y += ../common/dsi.c dsi.c
+ramstage-y += ../common/dsi_common.c dsi.c
 
 BL31_MAKEARGS += PLAT=mt8173
 
diff --git a/src/soc/mediatek/mt8183/Makefile.mk b/src/soc/mediatek/mt8183/Makefile.mk
index a4aa9db0ea..70f1b2a664 100644
--- a/src/soc/mediatek/mt8183/Makefile.mk
+++ b/src/soc/mediatek/mt8183/Makefile.mk
@@ -49,13 +49,12 @@ ramstage-$(CONFIG_ARM64_USE_ARM_TRUSTED_FIRMWARE) += ../common/bl31.c
 ramstage-y += emi.c
 ramstage-y += ../common/auxadc.c
 ramstage-y += ../common/ddp.c ddp.c
-ramstage-y += ../common/dsi.c ../common/mtk_mipi_dphy.c
+ramstage-y += ../common/dsi_common.c ../common/dsi_v1.c ../common/mtk_mipi_dphy.c
 ramstage-y += ../common/gpio_eint_v1.c ../common/gpio.c gpio.c
 ramstage-y += ../common/i2c.c i2c.c
 ramstage-y += ../common/mcu.c
 ramstage-y += ../common/mmu_operations.c mmu_operations.c
 ramstage-y += ../common/mtcmos.c mtcmos.c
-ramstage-y += ../common/mtk_dsi_common.c
 ramstage-y += ../common/pmic_wrap.c
 ramstage-y += ../common/rtc.c ../common/rtc_pwrap_ops.c ../common/rtc_osc_init.c rtc.c
 ramstage-y += soc.c
diff --git a/src/soc/mediatek/mt8186/Makefile.mk b/src/soc/mediatek/mt8186/Makefile.mk
index 6625988edd..f066b4bb3a 100644
--- a/src/soc/mediatek/mt8186/Makefile.mk
+++ b/src/soc/mediatek/mt8186/Makefile.mk
@@ -40,14 +40,13 @@ ramstage-y += ../common/ddp.c ddp.c
 ramstage-y += ../common/devapc.c devapc.c
 ramstage-y += ../common/dfd.c
 ramstage-y += ../common/display.c
-ramstage-y += ../common/dsi.c ../common/mtk_mipi_dphy.c
+ramstage-y += ../common/dsi_common.c ../common/dsi_v1.c ../common/mtk_mipi_dphy.c
 ramstage-y += ../common/emi.c
 ramstage-y += ../common/l2c_ops.c
 ramstage-y += ../common/mcu.c
 ramstage-y += ../common/mmu_operations.c
 ramstage-$(CONFIG_COMMONLIB_STORAGE_MMC) += ../common/msdc.c msdc.c
 ramstage-y += ../common/mtcmos.c mtcmos.c
-ramstage-y += ../common/mtk_dsi_common.c
 ramstage-y += ../common/pmic_wrap.c pmic_wrap.c pmif.c mt6366.c
 ramstage-y += ../common/rtc.c ../common/rtc_pwrap_ops.c ../common/rtc_osc_init.c rtc.c
 ramstage-y += soc.c
diff --git a/src/soc/mediatek/mt8188/Makefile.mk b/src/soc/mediatek/mt8188/Makefile.mk
index fa9a8f119a..74ccbbdfac 100644
--- a/src/soc/mediatek/mt8188/Makefile.mk
+++ b/src/soc/mediatek/mt8188/Makefile.mk
@@ -45,7 +45,7 @@ ramstage-y += ../common/dp/dptx_hal_common.c ../common/dp/dptx_hal_v1.c
 ramstage-y += ../common/dpm.c
 ramstage-y += ../common/dpm_v1.c
 ramstage-$(CONFIG_DPM_FOUR_CHANNEL) += ../common/dpm_4ch.c
-ramstage-y += ../common/dsi.c ../common/mtk_mipi_dphy.c
+ramstage-y += ../common/dsi_common.c ../common/dsi_v1.c ../common/mtk_mipi_dphy.c
 ramstage-y += ../common/emi.c
 ramstage-y += ../common/l2c_ops.c
 ramstage-y += ../common/mcu.c
@@ -54,7 +54,6 @@ ramstage-y += ../common/mmu_operations.c
 ramstage-$(CONFIG_COMMONLIB_STORAGE_MMC) += ../common/msdc.c msdc.c
 ramstage-y += ../common/mt6359p.c mt6359p.c
 ramstage-y += ../common/mtcmos.c mtcmos.c
-ramstage-y += ../common/mtk_dsi_common.c
 ramstage-y += ../common/pmif.c ../common/pmif_clk.c ../common/pmif_init.c pmif_clk.c
 ramstage-y += ../common/pmif_spi.c pmif_spi.c
 ramstage-y += ../common/pmif_spmi.c ../common/pmif_spmi_v1.c pmif_spmi.c
diff --git a/src/soc/mediatek/mt8192/Makefile.mk b/src/soc/mediatek/mt8192/Makefile.mk
index eaf7bc1856..8bbc8215b9 100644
--- a/src/soc/mediatek/mt8192/Makefile.mk
+++ b/src/soc/mediatek/mt8192/Makefile.mk
@@ -40,14 +40,13 @@ ramstage-y += devapc.c
 ramstage-y += ../common/dfd.c
 ramstage-y += ../common/dpm.c
 ramstage-y += ../common/dpm_v1.c
-ramstage-y += ../common/dsi.c ../common/mtk_mipi_dphy.c
+ramstage-y += ../common/dsi_common.c ../common/dsi_v1.c ../common/mtk_mipi_dphy.c
 ramstage-y += ../common/l2c_ops.c
 ramstage-y += ../common/mcu.c
 ramstage-y += ../common/mcupm.c
 ramstage-y += ../common/mmu_operations.c
 ramstage-$(CONFIG_COMMONLIB_STORAGE_MMC) += ../common/msdc.c msdc.c
 ramstage-y += ../common/mtcmos.c mtcmos.c
-ramstage-y += ../common/mtk_dsi_common.c
 ramstage-y += ../common/pmif.c ../common/pmif_init.c
 ramstage-y += ../common/rtc.c ../common/rtc_mt6359p.c
 ramstage-y += soc.c

From 50adb3f23c75208f3bb69159fa001adf0fc2f05b Mon Sep 17 00:00:00 2001
From: Venkateshwar S <vens@qualcomm.corp-partner.google.com>
Date: Mon, 13 Oct 2025 01:21:42 -0700
Subject: [PATCH 2313/3886] mb/google/bluey: Increase FW_MAIN_A/B slot size to
 4.5MB

This patch increases the size of the FW_MAIN_A and FW_MAIN_B slots to
4608KB (4.5MB) to incorporate the QTEE FW and its config files.

TEST =Create an image.serial.bin and ensure it boots on X1P42100.

Change-Id: I69ce0f3cff2cae110a21417245c425ee8bcf1e6c
Signed-off-by: Venkateshwar S <vens@qualcomm.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89549
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
---
 src/mainboard/google/bluey/chromeos.fmd | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/mainboard/google/bluey/chromeos.fmd b/src/mainboard/google/bluey/chromeos.fmd
index f29de156d0..98f03b5851 100644
--- a/src/mainboard/google/bluey/chromeos.fmd
+++ b/src/mainboard/google/bluey/chromeos.fmd
@@ -26,13 +26,13 @@ FLASH@0x0 CONFIG_ROM_SIZE {
 		RW_NVRAM(PRESERVE) 16K
 	}
 
-	RW_SECTION_A 1984K {
+	RW_SECTION_A 4608K {
 		VBLOCK_A 8K
 		FW_MAIN_A(CBFS)
 		RW_FWID_A 256
 	}
 
-	RW_SECTION_B 1984K {
+	RW_SECTION_B 4608K {
 		VBLOCK_B 8K
 		FW_MAIN_B(CBFS)
 		RW_FWID_B 256

From 03524780fff3433966d0e6235bb96cecad88af0e Mon Sep 17 00:00:00 2001
From: Venkateshwar S <vens@qualcomm.corp-partner.google.com>
Date: Sun, 12 Oct 2025 23:12:02 -0700
Subject: [PATCH 2314/3886] soc/qualcomm/x1p42100: Support loading QTEE FW
 config files

This patch adds support to load the config files associated with
the QTEE firmware in X1P42100.

TEST=Create an image.serial.bin and ensure it boots on X1P42100.
Ensure config files are loaded into the appropriate regions.

[INFO ]  CBFS: Found 'fallback/tzoem_cfg' @0x3ab3c0 size 0x3900
[DEBUG]  read SPI 0xfdb418 0x3900: 1200 us, 12160 KB/s, 97.280 Mbps
[INFO ]  VB2:vb2_secdata_kernel_get() VB2_SECDATA_KERNEL_FLAGS not
                supported for secdata_kernel v0, return 0
[INFO ]  VB2:vb2_digest_init() 14592 bytes, hash algo 2, HW acceleration
                forbidden
[DEBUG]  Loading segment from ROM address 0x9f8040f8
[DEBUG]    data (compression=1)
[DEBUG]    New segment dstaddr 0xd802a000 memsize 0x1d0 srcaddr
                0x9f80414c filesize 0xd2
[DEBUG]  Loading Segment: addr: 0xd802a000 memsz: 0x00000000000001d0
                filesz: 0x00000000000000d2
[DEBUG]  using LZMA
[SPEW ]  [ 0xd802a000, d802a1d0, 0xd802a1d0) &amp;lt;- 9f80414c
[DEBUG]  Loading segment from ROM address 0x9f804114
[DEBUG]    data (compression=1)
[DEBUG]    New segment dstaddr 0xd802f000 memsize 0x9000 srcaddr
                0x9f80421e filesize 0x37da
[DEBUG]  Loading Segment: addr: 0xd802f000 memsz: 0x0000000000009000
                filesz: 0x00000000000037da
[DEBUG]  using LZMA
[SPEW ]  [ 0xd802f000, d8038000, 0xd8038000) &amp;lt;- 9f80421e
[DEBUG]  Loading segment from ROM address 0x9f804130
[DEBUG]    Entry Point 0xd802f000
[SPEW ]  Loaded segments
[INFO ]  CBFS: Found 'fallback/tzqti_cfg' @0x3aed40 size 0x19c3
[DEBUG]  read SPI 0xfded98 0x19c3: 562 us, 11734 KB/s, 93.872 Mbps
[INFO ]  VB2:vb2_secdata_kernel_get() VB2_SECDATA_KERNEL_FLAGS not
                supported for secdata_kernel v0, return 0
[INFO ]  VB2:vb2_digest_init() 6595 bytes, hash algo 2, HW acceleration
                forbidden
[DEBUG]  Loading segment from ROM address 0x9f8040f8
[DEBUG]    data (compression=1)
[DEBUG]    New segment dstaddr 0xd803b000 memsize 0x1d0 srcaddr
                0x9f80414c filesize 0xd2
[DEBUG]  Loading Segment: addr: 0xd803b000 memsz: 0x00000000000001d0
                filesz: 0x00000000000000d2
[DEBUG]  using LZMA
[SPEW ]  [ 0xd803b000, d803b1d0, 0xd803b1d0) &amp;lt;- 9f80414c
[DEBUG]  Loading segment from ROM address 0x9f804114
[DEBUG]    data (compression=1)
[DEBUG]    New segment dstaddr 0xd8040000 memsize 0xe000 srcaddr
                0x9f80421e filesize 0x189d
[DEBUG]  Loading Segment: addr: 0xd8040000 memsz: 0x000000000000e000
                filesz: 0x000000000000189d
[DEBUG]  using LZMA
[SPEW ]  [ 0xd8040000, d804e000, 0xd804e000) &amp;lt;- 9f80421e
[DEBUG]  Loading segment from ROM address 0x9f804130
[DEBUG]    Entry Point 0xd8040000
[SPEW ]  Loaded segments
[INFO ]  CBFS: Found 'fallback/tzac_cfg' @0x3b0780 size 0x1f0d
[DEBUG]  read SPI 0xfe07d8 0x1f0d: 670 us, 11864 KB/s, 94.912 Mbps
[INFO ]  VB2:vb2_secdata_kernel_get() VB2_SECDATA_KERNEL_FLAGS not
                supported for secdata_kernel v0, return 0
[INFO ]  VB2:vb2_digest_init() 7949 bytes, hash algo 2, HW acceleration
                forbidden
[DEBUG]  Loading segment from ROM address 0x9f8040f8
[DEBUG]    data (compression=1)
[DEBUG]    New segment dstaddr 0xd8019000 memsize 0xb800 srcaddr
                0x9f804130 filesize 0x1ed5
[DEBUG]  Loading Segment: addr: 0xd8019000 memsz: 0x000000000000b800
                filesz: 0x0000000000001ed5
[DEBUG]  using LZMA
[SPEW ]  [ 0xd8019000, d8024800, 0xd8024800) &amp;lt;- 9f804130
[DEBUG]  Loading segment from ROM address 0x9f804114
[DEBUG]    Entry Point 0xd8019000
[SPEW ]  Loaded segments
[INFO ]  CBFS: Found 'fallback/hypac_cfg' @0x3b2700 size 0x11f2
[DEBUG]  read SPI 0xfe2758 0x11f2: 400 us, 11485 KB/s, 91.880 Mbps
[INFO ]  VB2:vb2_secdata_kernel_get() VB2_SECDATA_KERNEL_FLAGS not
                supported for secdata_kernel v0, return 0
[INFO ]  VB2:vb2_digest_init() 4594 bytes, hash algo 2, HW acceleration
                forbidden
[DEBUG]  Loading segment from ROM address 0x9f8040f8
[DEBUG]    data (compression=1)
[DEBUG]    New segment dstaddr 0xd8000000 memsize 0xc8f4 srcaddr
                0x9f804130 filesize 0x11ba
[DEBUG]  Loading Segment: addr: 0xd8000000 memsz: 0x000000000000c8f4
                filesz: 0x00000000000011ba
[DEBUG]  using LZMA
[SPEW ]  [ 0xd8000000, d800c8f4, 0xd800c8f4) &amp;lt;- 9f804130
[DEBUG]  Loading segment from ROM address 0x9f804114
[DEBUG]    Entry Point 0xd8000000
[SPEW ]  Loaded segments

Change-Id: If07840fca327e51c385dbe3f33b9f775bbee7654
Signed-off-by: Venkateshwar S <vens@qualcomm.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89550
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/soc/qualcomm/x1p42100/Makefile.mk | 32 +++++++++++++++++++++++++++
 src/soc/qualcomm/x1p42100/soc.c       | 28 +++++++++++++++++++++++
 2 files changed, 60 insertions(+)

diff --git a/src/soc/qualcomm/x1p42100/Makefile.mk b/src/soc/qualcomm/x1p42100/Makefile.mk
index 7325d9bf7a..ab23dde75d 100644
--- a/src/soc/qualcomm/x1p42100/Makefile.mk
+++ b/src/soc/qualcomm/x1p42100/Makefile.mk
@@ -262,6 +262,38 @@ $(GSI_FW_CBFS)-type := raw
 $(GSI_FW_CBFS)-compression := $(CBFS_COMPRESS_FLAG)
 cbfs-files-y += $(GSI_FW_CBFS)
 
+################################################################################
+DEVCFG_TZ_FILE := $(X1P42100_BLOB)/qtee/tz_oem_config.mbn
+DEVCFG_TZ_FILE_CBFS := $(CONFIG_CBFS_PREFIX)/tzoem_cfg
+$(DEVCFG_TZ_FILE_CBFS)-file := $(DEVCFG_TZ_FILE)
+$(DEVCFG_TZ_FILE_CBFS)-type := payload
+$(DEVCFG_TZ_FILE_CBFS)-compression := $(CBFS_COMPRESS_FLAG)
+cbfs-files-y += $(DEVCFG_TZ_FILE_CBFS)
+
+################################################################################
+TZQTI_CFG_FILE := $(X1P42100_BLOB)/qtee/tz_qti_config.mbn
+TZQTI_CFG_FILE_CBFS := $(CONFIG_CBFS_PREFIX)/tzqti_cfg
+$(TZQTI_CFG_FILE_CBFS)-file := $(TZQTI_CFG_FILE)
+$(TZQTI_CFG_FILE_CBFS)-type := payload
+$(TZQTI_CFG_FILE_CBFS)-compression := $(CBFS_COMPRESS_FLAG)
+cbfs-files-y += $(TZQTI_CFG_FILE_CBFS)
+
+################################################################################
+TZAC_CFG_FILE := $(X1P42100_BLOB)/ac_policy/tz_ac_config.elf
+TZAC_CFG_FILE_CBFS := $(CONFIG_CBFS_PREFIX)/tzac_cfg
+$(TZAC_CFG_FILE_CBFS)-file := $(TZAC_CFG_FILE)
+$(TZAC_CFG_FILE_CBFS)-type := payload
+$(TZAC_CFG_FILE_CBFS)-compression := $(CBFS_COMPRESS_FLAG)
+cbfs-files-y += $(TZAC_CFG_FILE_CBFS)
+
+################################################################################
+HYPAC_CFG_FILE := $(X1P42100_BLOB)/ac_policy/hyp_ac_config.elf
+HYPAC_CFG_FILE_CBFS := $(CONFIG_CBFS_PREFIX)/hypac_cfg
+$(HYPAC_CFG_FILE_CBFS)-file := $(HYPAC_CFG_FILE)
+$(HYPAC_CFG_FILE_CBFS)-type := payload
+$(HYPAC_CFG_FILE_CBFS)-compression := $(CBFS_COMPRESS_FLAG)
+cbfs-files-y += $(HYPAC_CFG_FILE_CBFS)
+
 endif # ifeq ($(CONFIG_USE_QC_BLOBS),y)
 
 endif # ifeq ($(CONFIG_QC_BLOBS_UPSTREAM),y)
diff --git a/src/soc/qualcomm/x1p42100/soc.c b/src/soc/qualcomm/x1p42100/soc.c
index ffa3a0e7d9..d4fdb87396 100644
--- a/src/soc/qualcomm/x1p42100/soc.c
+++ b/src/soc/qualcomm/x1p42100/soc.c
@@ -6,6 +6,7 @@
 #include <soc/symbols_common.h>
 #include <soc/pcie.h>
 #include <soc/cpucp.h>
+#include <program_loading.h>
 
 static struct device_operations pci_domain_ops = {
 	.read_resources = &qcom_pci_domain_read_resources,
@@ -56,9 +57,36 @@ static void soc_read_resources(struct device *dev)
 	reserved_ram_range(dev, index++, (uintptr_t)_dram_smem, REGION_SIZE(dram_smem));
 }
 
+static void qtee_fw_config_load(void)
+{
+	if (!CONFIG(ARM64_USE_SECURE_OS))
+		return;
+
+	struct prog devcfg_tz = PROG_INIT(PROG_PAYLOAD,
+					CONFIG_CBFS_PREFIX"/tzoem_cfg");
+	if (!selfload(&devcfg_tz))
+		die("devcfg_tz load failed");
+
+	struct prog tzqti_cfg = PROG_INIT(PROG_PAYLOAD,
+					CONFIG_CBFS_PREFIX"/tzqti_cfg");
+	if (!selfload(&tzqti_cfg))
+		die("tzqti_cfg load failed");
+
+	struct prog tzac_cfg = PROG_INIT(PROG_PAYLOAD,
+					CONFIG_CBFS_PREFIX"/tzac_cfg");
+	if (!selfload(&tzac_cfg))
+		die("tzac_cfg load failed");
+
+	struct prog hypac_cfg = PROG_INIT(PROG_PAYLOAD,
+					CONFIG_CBFS_PREFIX"/hypac_cfg");
+	if (!selfload(&hypac_cfg))
+		die("hypac_cfg load failed");
+}
+
 static void soc_init(struct device *dev)
 {
 	cpucp_fw_load_reset();
+	qtee_fw_config_load();
 }
 
 static struct device_operations soc_ops = {

From ab4b82fb3c33ff89f16f68b4b0f5975ed75cc495 Mon Sep 17 00:00:00 2001
From: Martin Roth <gaumless@gmail.com>
Date: Sun, 19 Oct 2025 17:25:47 -0600
Subject: [PATCH 2315/3886] util/lint: Add a license check exception for
 .gitkeep files

A .gitkeep file is an unofficial convention used in Git to keep and
track empty directories, as Git does not track empty folders by default.

This could be needed when one mainboard variant has an include directory
but another doesn't. If the directory is added to the include, it could
be easier to just create an empty include directory with a .gitkeep file
in it to keep things from failing.

Change-Id: I34b2ffa4d748d82e26867ecd5b9149301300e6a1
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89640
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
---
 util/lint/lint-000-license-headers | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/util/lint/lint-000-license-headers b/util/lint/lint-000-license-headers
index bff8bb48d0..3a28d104b1 100755
--- a/util/lint/lint-000-license-headers
+++ b/util/lint/lint-000-license-headers
@@ -69,7 +69,8 @@ _shipped$|\
 config|\
 cmos\.layout|\
 cmos\.default|\
-\.apcb$\
+\.apcb$|\
+\.gitkeep$\
 "
 
 #space separated list of directories to test

From f4271cad0ad2900753c72aa1a4f3cb494223264a Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Filip=20Go=C5=82a=C5=9B?= <filip.golas@3mdeb.com>
Date: Mon, 6 Oct 2025 18:43:12 +0200
Subject: [PATCH 2316/3886] ifdtool: Add set top swap size PCH strap subcommand
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Top-Block Swap mode of Intel PCH allows to swap the boot block with
another location placed directly below it by redirecting the memory
accesses.

The range of the addresses to be redirected is configured using the Top
Swap Block Size (or BOOT_BLOCK_SIZE) PCH strap using 3 bits to encode
one of 8 sizes:
    64 KB, 128 KB, 256 KB, 512 KB, 1 MB, 2 MB, 4 MB or 8 MB.

The source and target ranges depend on the configured size, eg:
- 64 KB  - FFFF_0000h - FFFF_FFFFh -> FFFE_0000h - FFFE_FFFFh
- 128 KB - FFFE_0000h - FFFF_FFFFh -> FFFC_0000h - FFFD_FFFFh
- 8 MB   - FF80_0000h - FFFF_FFFFh -> FF00_0000h - FF7F_FFFFh

Only supporting Alder Lake-P and Alder Lake-N for now.

Needed for the bootblock redundancy feature suggested at
https://mail.coreboot.org/archives/list/coreboot@coreboot.org/thread/C6JN2PB7K7D67EG7OIKB6BBERZU5YV35/

TEST=check using xxd, MFIT tool, ensure VP6670 boots
Test details:
xxd:
  ./util/ifdtool/ifdtool -p adl -T 0x10000 vp66xx_fd.bin && \
  xxd vp66xx_fd.bin > vp66xx.hex && \
  xxd vp66xx_fd.bin.new > vp66xx_fd.new.hex && \
  diff -au vp66xx_fd.hex vp66xx_fd.new.hex

File vp66xx_fd.bin is 4096 bytes
Writing new image to vp66xx_fd.bin.new

--- vp66xx_fd.hex       2025-10-08 12:03:09.527193533 +0200
+++ vp66xx_fd.new.hex   2025-10-08 12:05:08.717108142 +0200
@@ -18,7 +18,7 @@
 00000110: 7f78 0700 0000 0000 1800 0000 0000 1f00  .x..............
 00000120: 0808 1170 0000 0000 0000 7f06 80f8 8107  ...p............
 00000130: 0000 0000 0f00 0000 2222 2222 2202 2222  ........""""".""
-00000140: 0000 0000 0000 0000 0000 ff00 6000 80c8  ............`...
+00000140: 0000 0000 0000 0000 0000 ff00 0000 80c8  ................
 00000150: 4586 0036 0000 0000 0002 5800 0000 4000  E..6......X...@.
 00000160: 0018 0000 0000 0000 0000 0000 0000 0000  ................
 00000170: 0000 0000 0000 0000 54b3 04a0 3000 0140  ........T...0..@

mfittool:
./mfit --gui -decompose protectli_vp66xx_v0.9.2.rom
In the UI:
Flash Settings > BIOS Configuration > Top Swap Block Size
shows the value changing to the expected one, ie.
    -T 0x10000 results in 64kB
    -T 0x20000 results in 128kB
    -T 0x400000 results in 4MB
    etc.

Change-Id: I50e9d4160ee4b60e83567bcd33c9d80d428cf2bb
Signed-off-by: Filip Gołaś <filip.golas@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89438
Reviewed-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 util/ifdtool/ifdtool.c | 80 +++++++++++++++++++++++++++++++++++++++---
 1 file changed, 76 insertions(+), 4 deletions(-)

diff --git a/util/ifdtool/ifdtool.c b/util/ifdtool/ifdtool.c
index b21a89c0e1..fc0cb5fa4e 100644
--- a/util/ifdtool/ifdtool.c
+++ b/util/ifdtool/ifdtool.c
@@ -2173,6 +2173,16 @@ static void new_layout(const char *filename, char *image, int size,
 	free(new_image);
 }
 
+static uint32_t uint_log2(uint32_t n)
+{
+	int log = -1;
+	while (n) {
+		n >>= 1;
+		++log;
+	}
+	return log;
+}
+
 static void print_version(void)
 {
 	printf("ifdtool v%s -- ", IFDTOOL_VERSION);
@@ -2231,6 +2241,9 @@ static void print_usage(const char *name)
 	       "                                         wbg    - Wellsburg\n"
 	       "   -S | --setpchstrap                    Write a PCH strap\n"
 	       "   -V | --newvalue                       The new value to write into PCH strap specified by -S\n"
+	       "   -T | --topswapsize                    Set the Top Swap Block Size PCH strap value\n"
+	       "                                         Possible values: 0x10000, 0x20000, 0x40000, 0x80000,\n"
+	       "                                         0x100000, 0x200000, 0x400000, 0x800000\n"
 	       "   -v | --version:                       print the version\n"
 	       "   -h | --help:                          print this help\n\n"
 	       "<region> is one of Descriptor, BIOS, ME, GbE, Platform Data, Secondary BIOS, "
@@ -2246,8 +2259,9 @@ int main(int argc, char *argv[])
 	int mode_layout = 0, mode_newlayout = 0, mode_density = 0, mode_setstrap = 0;
 	int mode_read = 0, mode_altmedisable = 0, altmedisable = 0, mode_fmap_template = 0;
 	int mode_gpr0_disable = 0, mode_gpr0_enable = 0, mode_gpr0_status = 0;
+	int mode_settopswapsize = 0;
 	char *region_type_string = NULL, *region_fname = NULL, *layout_fname = NULL;
-	char *new_filename = NULL;
+	char *new_filename = NULL, *top_swap_size_arg = NULL;
 	int region_type = -1, inputfreq = 0;
 	unsigned int value = 0;
 	unsigned int pchstrap = 0;
@@ -2279,10 +2293,11 @@ int main(int argc, char *argv[])
 		{"validate", 0, NULL, 't'},
 		{"setpchstrap", 1, NULL, 'S'},
 		{"newvalue", 1, NULL, 'V'},
+		{"topswapsize", 1, NULL, 'T'},
 		{0, 0, 0, 0}
 	};
 
-	while ((opt = getopt_long(argc, argv, "S:V:df:F:D:C:M:xi:n:O:s:p:elrugEcvth?",
+	while ((opt = getopt_long(argc, argv, "S:V:df:F:D:C:M:xi:n:O:s:p:T:elrugEcvth?",
 					long_options, &option_index)) != EOF) {
 		switch (opt) {
 		case 'd':
@@ -2533,6 +2548,10 @@ int main(int argc, char *argv[])
 		case 't':
 			mode_validate = 1;
 			break;
+		case 'T':
+			mode_settopswapsize = 1;
+			top_swap_size_arg = optarg;
+			break;
 		case 'v':
 			print_version();
 			exit(EXIT_SUCCESS);
@@ -2550,7 +2569,7 @@ int main(int argc, char *argv[])
 	}
 
 	if ((mode_dump + mode_layout + mode_fmap_template + mode_extract + mode_inject +
-			mode_setstrap + mode_newlayout + (mode_spifreq | mode_em100 |
+			mode_setstrap + mode_settopswapsize + mode_newlayout + (mode_spifreq | mode_em100 |
 			mode_unlocked | mode_locked) + mode_altmedisable + mode_validate +
 			(mode_gpr0_disable | mode_gpr0_enable) + mode_gpr0_status) > 1) {
 		fprintf(stderr, "You may not specify more than one mode.\n\n");
@@ -2559,7 +2578,7 @@ int main(int argc, char *argv[])
 	}
 
 	if ((mode_dump + mode_layout + mode_fmap_template + mode_extract + mode_inject +
-			mode_setstrap + mode_newlayout + mode_spifreq + mode_em100 +
+			mode_setstrap + mode_settopswapsize + mode_newlayout + mode_spifreq + mode_em100 +
 			mode_locked + mode_unlocked + mode_density + mode_altmedisable +
 			mode_validate + (mode_gpr0_disable | mode_gpr0_enable) + mode_gpr0_status) == 0) {
 		fprintf(stderr, "You need to specify a mode.\n\n");
@@ -2667,6 +2686,59 @@ int main(int argc, char *argv[])
 	if (mode_gpr0_status)
 		is_gpr0_protected(image, size);
 
+	if (mode_settopswapsize) {
+		if (platform == -1) {
+			fprintf(stderr, "Error: No platform specified.\n");
+			exit(EXIT_FAILURE);
+		}
+		struct fpsba *fpsba = find_fpsba(image, size);
+		uint32_t top_swap_size_offset = 0;
+		switch (platform) {
+		case PLATFORM_ADL:
+			// fixed bits for ADL-P / ADL-N
+			if (fpsba->pchstrp[0xd0 / 4] == 0x00000300) {
+				// fixed bits for ADL-P
+				if (((fpsba->pchstrp[0x7c / 4] >> 1) & 0xff) == 0x18) {
+					printf("Detected ADL-P flash descriptor\n");
+					pchstrap = 0x4C / 4;
+					top_swap_size_offset = 4;
+					// fixed bits for ADL-N
+				} else if (((fpsba->pchstrp[0x7c / 4] >> 1) & 0xff) == 0x51) {
+					printf("Detected ADL-N flash descriptor\n");
+					pchstrap = 0x4C / 4;
+					top_swap_size_offset = 4;
+				}
+			}
+			break;
+		default:
+			break;
+		}
+		if (pchstrap == 0) {
+			fprintf(stderr, "Setting top swap size not supported on selected platform.\n");
+			exit(EXIT_FAILURE);
+		}
+
+		uint32_t top_swap_size = strtoul(top_swap_size_arg, NULL, 0);
+		if (top_swap_size < 0x10000 || !IS_POWER_OF_2(top_swap_size) || top_swap_size > 0x800000) {
+			fprintf(stderr,
+				"Unsupported top swap size: %s\n"
+				"Supported top swap sizes:\n"
+				"\t0x10000, 0x20000, 0x40000, 0x80000, 0x100000,\n"
+				"\t0x200000, 0x400000, 0x800000\n",
+				top_swap_size_arg);
+			exit(EXIT_FAILURE);
+		}
+		// convert to 0x00-0x07
+		top_swap_size = uint_log2(top_swap_size / 0x10000);
+		const struct fdbar *fdb = find_fd(image, size);
+		value = fpsba->pchstrp[pchstrap];
+		value &= ~(0x7 << top_swap_size_offset);
+		value |= (top_swap_size << top_swap_size_offset);
+
+		set_pchstrap(fpsba, fdb, pchstrap, value);
+		write_image(new_filename, image, size);
+	}
+
 	if (mode_setstrap) {
 		struct fpsba *fpsba = find_fpsba(image, size);
 		const struct fdbar *fdb = find_fd(image, size);

From 6e4501661095af7857a8784c708b02135aff2e21 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Filip=20Go=C5=82a=C5=9B?= <filip.golas@3mdeb.com>
Date: Thu, 9 Oct 2025 12:34:45 +0200
Subject: [PATCH 2317/3886] intel soc,southbridge: Add Kconfig to set TSBS in
 IFD during build
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

To modify the Top Swap Block Size in the FD (if provided and
CONFIG_HAVE_IFD_BIN=y), set the following Kconfig variables:
- CONFIG_INTEL_HAS_TOP_SWAP
- CONFIG_INTEL_ADD_TOP_SWAP_BOOTBLOCK
- CONFIG_INTEL_TOP_SWAP_BOOTBLOCK_SIZE
- CONFIG_INTEL_IFD_SET_TOP_SWAP_BOOTBLOCK_SIZE

Needed for the bootblock redundancy feature suggested at
https://mail.coreboot.org/archives/list/coreboot@coreboot.org/thread/C6JN2PB7K7D67EG7OIKB6BBERZU5YV35/

TEST=build VP66xx with custom Kconfig, check if TSBS is modified in FD

Change-Id: I94d3d3e2511a7e56392a9e34f845ae91602ce7f1
Signed-off-by: Filip Gołaś <filip.golas@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89493
Reviewed-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/soc/intel/common/Kconfig.common               | 14 +++++++++++++-
 src/southbridge/intel/common/firmware/Makefile.mk | 13 +++++++++++++
 2 files changed, 26 insertions(+), 1 deletion(-)

diff --git a/src/soc/intel/common/Kconfig.common b/src/soc/intel/common/Kconfig.common
index 7cd57438be..d52bc1a0fa 100644
--- a/src/soc/intel/common/Kconfig.common
+++ b/src/soc/intel/common/Kconfig.common
@@ -23,7 +23,19 @@ config INTEL_TOP_SWAP_BOOTBLOCK_SIZE
 	default 0x10000
 	help
 	  Set this config to a supported topswap size.
-	  Valid sizes: 0x10000 0x20000 0x40000 0x80000 0x100000
+	  Valid sizes: 0x10000/0x20000/0x40000/0x80000/0x100000/
+	  0x200000/0x400000/0x800000. The maximum size
+	  varies depending on the platform.
+
+config INTEL_IFD_SET_TOP_SWAP_BOOTBLOCK_SIZE
+	bool "Replace the TSBS value with INTEL_TOP_SWAP_BOOTBLOCK_SIZE"
+	default n
+	depends on HAVE_IFD_BIN
+	help
+	  Set to use ifdtool to replace the Top Swap Block Size
+	  PCH strap value in the Intel Firmware Descriptor
+	  with INTEL_TOP_SWAP_BOOTBLOCK_SIZE
+
 
 config INTEL_TOP_SWAP_FIT_ENTRY_FMAP_REG
 	string
diff --git a/src/southbridge/intel/common/firmware/Makefile.mk b/src/southbridge/intel/common/firmware/Makefile.mk
index a4f0e2e1a9..41ccca41d9 100644
--- a/src/southbridge/intel/common/firmware/Makefile.mk
+++ b/src/southbridge/intel/common/firmware/Makefile.mk
@@ -47,9 +47,22 @@ ifeq ($(CONFIG_HAVE_EC_BIN),y)
 add_intel_firmware: $(call strip_quotes,$(CONFIG_EC_BIN_PATH))
 endif
 add_intel_firmware: $(obj)/coreboot.pre $(IFDTOOL)
+ifeq ($(INTEL_IFD_SET_TOP_SWAP_BOOTBLOCK_SIZE),y)
+	printf "    IFDTOOL    Modifying top swap PCH strap in IFD\n"
+	printf "     $(IFDTOOL_USE_CHIPSET)"
+	$(objutil)/ifdtool/ifdtool \
+		$(IFDTOOL_USE_CHIPSET) \
+		-T $(CONFIG_INTEL_TOP_SWAP_BOOTBLOCK_SIZE) \
+		-O $(obj)/ifd_custom_tsbs \
+		$(IFD_BIN_PATH)
+	printf "    DD         Adding Intel Firmware Descriptor\n"
+	dd if=$(obj)/ifd_custom_tsbs\
+		of=$(obj)/coreboot.pre conv=notrunc >/dev/null 2>&1
+else
 	printf "    DD         Adding Intel Firmware Descriptor\n"
 	dd if=$(IFD_BIN_PATH) \
 		of=$(obj)/coreboot.pre conv=notrunc >/dev/null 2>&1
+endif
 ifeq ($(CONFIG_VALIDATE_INTEL_DESCRIPTOR),y)
 	printf "    IFDTOOL    validate IFD against FMAP\n"
 	$(objutil)/ifdtool/ifdtool \

From 155041ad4cf85e4b4a4778c06259476b47276290 Mon Sep 17 00:00:00 2001
From: Hari L <haril@qualcomm.corp-partner.google.com>
Date: Thu, 16 Oct 2025 17:24:09 +0530
Subject: [PATCH 2318/3886] soc/qualcomm/x1p42100: Add EUSB2 HS repeater
 support for USB Type-C

Add usb_repeater_spmi_init() and usb_repeater_spmi_tune() functions
for USB repeater internal to SMB2360 via SPMI configuration
during HS PHY initialization.

The usb_repeater_spmi_init() function enables Embedded USB2 control for
both SMB1 and SMB2 cores, while usb_repeater_spmi_tune() configures
optimal signal integrity parameters (IUSB2, USB2_SLEW, USB2_PREEM)
for reliable Type-C connectivity.

BUG=b:451814646
TEST=Verify USB2.0 (HS) works for C1 on Google/Bluey.

Without this CL -
USB2 key doesn't work for C1.

Verified HS1 functionality by turning on L14B from coreboot.

Before USB insertion:
firmware-shell:  md 0x0a800420 8
0a800420: 000002a0 00000000 00000000 00000000    ................
0a800430: 000002a0 00000000 00000000 00000000    ................

firmware-shell: Added USB disk 2.
firmware-shell:  md 0x0a800420 8
0a800420: 00000e03 00000000 00000000 00000000    ................
0a800430: 000002a0 00000000 00000000 00000000    ................

firmware-shell: Removed USB disk 2.
firmware-shell:  md 0x0a800420 8
0a800420: 000002a0 00000000 00000000 00000000    ................
0a800430: 000002a0 00000000 00000000 00000000    ................

Change-Id: I24e0af062fc7a6b5effd9317ec5c0b2d89fe288e
Signed-off-by: Hari L <haril@qualcomm.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89613
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
---
 .../qualcomm/x1p42100/include/soc/usb/usb.h   | 15 +++++++
 src/soc/qualcomm/x1p42100/usb/usb.c           | 40 ++++++++++++++++++-
 2 files changed, 53 insertions(+), 2 deletions(-)

diff --git a/src/soc/qualcomm/x1p42100/include/soc/usb/usb.h b/src/soc/qualcomm/x1p42100/include/soc/usb/usb.h
index 4ac6dad763..f8aa9e9ccc 100644
--- a/src/soc/qualcomm/x1p42100/include/soc/usb/usb.h
+++ b/src/soc/qualcomm/x1p42100/include/soc/usb/usb.h
@@ -126,6 +126,21 @@
 #define TYPEC_VBUS_STATUS_MASK BIT(5)
 #define CCOUT_INVERT_POLARITY 0x03
 
+/* USB Repeater SPMI Tune register offsets */
+#define EUSB2_TUNE_IUSB2 0xFD51
+#define EUSB2_TUNE_USB2_SLEW 0xFD55
+#define EUSB2_TUNE_USB2_PREEM 0xFD57
+
+/* USB 2.0 tuning parameter values */
+#define EUSB2_TUNE_IUSB2_DEFAULT	0x06	/* +11.1% HS transmit amplitude (default) */
+#define EUSB2_TUNE_USB2_SLEW_FAST	0x02	/* +14.9% faster slew rate */
+#define EUSB2_TUNE_USB2_PREEM_25PCT	0x02	/* +25% pre-emphasis current */
+
+/* USB Shared SPMI Init register offsets */
+#define EUSB2_EN_CTL1 0xFD46
+#define EUSB2_EN_CTL1_ENABLE BIT(7)
+#define EUSB2_EN_CTL1_DISABLE 0x00
+
 /* Forward declaration */
 struct dwc3_controller_config;
 
diff --git a/src/soc/qualcomm/x1p42100/usb/usb.c b/src/soc/qualcomm/x1p42100/usb/usb.c
index 9e91391d06..e97650773d 100644
--- a/src/soc/qualcomm/x1p42100/usb/usb.c
+++ b/src/soc/qualcomm/x1p42100/usb/usb.c
@@ -444,6 +444,42 @@ static const struct dwc3_controller_config sec_config = {
 	.smb_slave_addr = SMB2_SLAVE_ID,
 };
 
+/*
+ * usb_repeater_spmi_tune - Configures USB repeater SPMI tuning parameters
+ * @config: Controller configuration containing SMB slave address
+ */
+static void usb_repeater_spmi_tune(const struct dwc3_controller_config *config)
+{
+	u8 slave = config->smb_slave_addr;
+
+	/* Configure USB 2.0 output current tuning - default +11.1% amplitude */
+	spmi_write8(SPMI_ADDR(slave, EUSB2_TUNE_IUSB2), EUSB2_TUNE_IUSB2_DEFAULT);
+
+	/* Configure USB 2.0 HS TX slew rate - +14.9% faster than default */
+	spmi_write8(SPMI_ADDR(slave, EUSB2_TUNE_USB2_SLEW), EUSB2_TUNE_USB2_SLEW_FAST);
+
+	/* Configure USB 2.0 HS TX pre-emphasis - +25% current boost */
+	spmi_write8(SPMI_ADDR(slave, EUSB2_TUNE_USB2_PREEM), EUSB2_TUNE_USB2_PREEM_25PCT);
+}
+
+/*
+ * usb_repeater_spmi_init - Initializes USB repeater SPMI with enable-delay-disable sequence
+ * @config: Controller configuration containing SMB slave address
+ */
+static void usb_repeater_spmi_init(const struct dwc3_controller_config *config)
+{
+	u8 slave = config->smb_slave_addr;
+
+	spmi_write8(SPMI_ADDR(slave, EUSB2_EN_CTL1), EUSB2_EN_CTL1_DISABLE);
+	udelay(50);
+	spmi_write8(SPMI_ADDR(slave, EUSB2_EN_CTL1), EUSB2_EN_CTL1_ENABLE);
+
+	printk(BIOS_INFO, "Enabling %s EUSB2_EN_CTL1\n", config->name);
+
+	/* Call tune API after initialization */
+	usb_repeater_spmi_tune(config);
+}
+
 /*
  * get_usb_typec_polarity - Reads Type-C polarity from PMIC
  * @config: Controller configuration containing SMB slave address
@@ -530,7 +566,7 @@ static void setup_usb_host(struct usb_dwc3_cfg *dwc3)
 	clock_reset_bcr(dwc3->gcc_qusb2phy_prim_bcr, 1);
 	udelay(10);
 	clock_reset_bcr(dwc3->gcc_qusb2phy_prim_bcr, 0);
-	/* TBD:usb_shared_repeater_reset,usb_shared_repeater_init */
+	usb_repeater_spmi_init(&prim_config);
 	/* Initialize secondary HS PHY */
 	hs_usb_phy_init(2);
 
@@ -559,7 +595,7 @@ static void setup_usb_host(struct usb_dwc3_cfg *dwc3)
 	clock_reset_bcr(dwc3->gcc_qusb2phy_sec_bcr, 1);
 	udelay(10);
 	clock_reset_bcr(dwc3->gcc_qusb2phy_sec_bcr, 0);
-	/* TBD:usb_shared_repeater_reset,usb_shared_repeater_init for secondary */
+	usb_repeater_spmi_init(&sec_config);
 	/* Initialize secondary HS PHY */
 	hs_usb_phy_init(3);
 

From 752d49a4ffe98b731eb5a7c1beccff49f0418faa Mon Sep 17 00:00:00 2001
From: Mac Chiang <mac.chiang@intel.corp-partner.google.com>
Date: Thu, 16 Oct 2025 13:31:10 +0800
Subject: [PATCH 2319/3886] mb/google/fatcat/var/moonstone: Disable RT721 clock
 stop support

RT721 headset jack detection fails because the wakeup event is not
triggered during runtime suspend in D3 state. Disable the clock stop
to allow the bus driver to handle the wakeup process properly. The MIPI
Disco property is "mipi-sdw-simplified-clockstopprepare-sm-supported".

BUG= b:435094908
TEST= verify headset jack works properly.

Change-Id: Ibd5271e496a9ca841498b17a5746e300f9557078
Signed-off-by: Mac Chiang <mac.chiang@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89605
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/google/fatcat/variants/moonstone/overridetree.cb | 1 +
 1 file changed, 1 insertion(+)

diff --git a/src/mainboard/google/fatcat/variants/moonstone/overridetree.cb b/src/mainboard/google/fatcat/variants/moonstone/overridetree.cb
index b006a20f7a..d2487ac9a9 100644
--- a/src/mainboard/google/fatcat/variants/moonstone/overridetree.cb
+++ b/src/mainboard/google/fatcat/variants/moonstone/overridetree.cb
@@ -503,6 +503,7 @@ chip soc/intel/pantherlake
 						register "alc711_address.version" = "SOUNDWIRE_VERSION_1_2"
 						register "alc711_address.class" = "MIPI_CLASS_SDCA"
 						register "alc711_address.part_id" = "MIPI_DEV_ID_REALTEK_ALC721"
+						register "disable_clkstop_sm_support" = "true"
 						# SoundWire Link 3 ID 1
 						device generic 3.1 on
 							probe AUDIO AUDIO_ALC721_SNDW

From ec1068883fcbc9997a9fba4615c5eb8a4793b4b4 Mon Sep 17 00:00:00 2001
From: Brian Hsu <Brian_Hsu@pegatron.corp-partner.google.com>
Date: Wed, 24 Sep 2025 15:13:03 +0800
Subject: [PATCH 2320/3886] mb/google/nissa/var/guren: Add initial WWAN related
 settings

1. Add DB_1C_5G 8 on DB_USB overridetree.
2. Also disable LTE-related GPIOs based on fw_config when system
   was DB_1C_5G.

BUG=b:445338278
BRANCH=firmware-nissa-15217.B
TEST=emerge-nissa coreboot chromeos-bootimage
     Check 5G LTE module detectable by command # mmcli -m a.

Change-Id: I3d525d9de151427d38485882117b59939b9da5c7
Signed-off-by: Joyce Ciou <Joyce_Ciou@pegatron.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89606
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/google/brya/variants/guren/fw_config.c     | 7 ++++---
 src/mainboard/google/brya/variants/guren/overridetree.cb | 4 ++++
 2 files changed, 8 insertions(+), 3 deletions(-)

diff --git a/src/mainboard/google/brya/variants/guren/fw_config.c b/src/mainboard/google/brya/variants/guren/fw_config.c
index 63e55a3b40..8d4c1b5e2b 100644
--- a/src/mainboard/google/brya/variants/guren/fw_config.c
+++ b/src/mainboard/google/brya/variants/guren/fw_config.c
@@ -44,10 +44,11 @@ void fw_config_gpio_padbased_override(struct pad_config *padbased_table)
 						ARRAY_SIZE(hdmi_disable_pads));
 	}
 
-	/* Set to Disable LTE-related GPIO pins when field DB_USB is not DB_1C_LTE and DB_HDMI_LTE. */
+	/* Set to Disable LTE-related GPIO pins when field DB_USB is not DB_1C_LTE, DB_HDMI_LTE and DB_1C_5G. */
 	if (!fw_config_probe(FW_CONFIG(DB_USB, DB_1C_LTE))
-		&& !fw_config_probe(FW_CONFIG(DB_USB, DB_HDMI_LTE))) {
-		printk(BIOS_INFO, "Disable LTE GPIO pins.\n");
+		&& !fw_config_probe(FW_CONFIG(DB_USB, DB_HDMI_LTE))
+		&& !fw_config_probe(FW_CONFIG(DB_USB, DB_1C_5G))) {
+		printk(BIOS_INFO, "Disable LTE/5G GPIO pins.\n");
 		gpio_padbased_override(padbased_table, lte_disable_pads,
 						ARRAY_SIZE(lte_disable_pads));
 	}
diff --git a/src/mainboard/google/brya/variants/guren/overridetree.cb b/src/mainboard/google/brya/variants/guren/overridetree.cb
index 8c50fd76d8..f74a20e562 100644
--- a/src/mainboard/google/brya/variants/guren/overridetree.cb
+++ b/src/mainboard/google/brya/variants/guren/overridetree.cb
@@ -12,6 +12,7 @@ fw_config
 		option DB_HDMI_LTE		5
 		option DB_HDMI			6
 		option DB_HDMI_1A		7
+		option DB_1C_5G			8
 	end
 	field SD_CARD 9
 		option SD_ABSENT		 0
@@ -479,6 +480,7 @@ chip soc/intel/alderlake
 				device i2c 28 on
 					probe DB_USB DB_1C_LTE
 					probe DB_USB DB_HDMI_LTE
+					probe DB_USB DB_1C_5G
 				end
 			end
 		end #I2C2
@@ -651,6 +653,7 @@ chip soc/intel/alderlake
 						device ref usb2_port4 on
 							probe DB_USB DB_1C_LTE
 							probe DB_USB DB_HDMI_LTE
+							probe DB_USB DB_1C_5G
 						end
 					end
 					chip drivers/usb/acpi
@@ -696,6 +699,7 @@ chip soc/intel/alderlake
 						device ref usb3_port2 on
 							probe DB_USB DB_1C_LTE
 							probe DB_USB DB_HDMI_LTE
+							probe DB_USB DB_1C_5G
 						end
 					end
 				end

From b87a9795de20d2906c440174f28e4de172fe127e Mon Sep 17 00:00:00 2001
From: Elyes Haouas <ehaouas@noos.fr>
Date: Sat, 8 Feb 2025 12:19:28 +0100
Subject: [PATCH 2321/3886] tree: Use boolean for s3resume

Change-Id: I3e23134f879fcaf817cf62b641e9b59563eb643b
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86331
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
---
 src/arch/arm64/include/arch/acpi.h                        | 6 +++---
 src/drivers/amd/agesa/mtrr_fixme.c                        | 4 ++--
 src/drivers/tpm/tpm.c                                     | 2 +-
 src/include/acpi/acpi.h                                   | 4 ++--
 src/include/cbmem.h                                       | 3 ++-
 src/include/romstage_handoff.h                            | 5 +++--
 src/include/stage_cache.h                                 | 4 ++--
 src/lib/bootblock.c                                       | 2 +-
 src/lib/imd_cbmem.c                                       | 2 +-
 src/lib/romstage_handoff.c                                | 8 ++++----
 src/mainboard/dell/snb_ivb_workstations/romstage.c        | 2 +-
 src/mainboard/emulation/qemu-i440fx/romstage.c            | 2 +-
 src/mainboard/emulation/qemu-q35/romstage.c               | 2 +-
 src/mainboard/google/auron/ec.c                           | 2 +-
 src/mainboard/google/auron/variants/gandof/variant.c      | 2 +-
 src/mainboard/google/auron/variants/lulu/variant.c        | 2 +-
 src/mainboard/google/auron/variants/samus/variant.c       | 2 +-
 src/mainboard/google/link/early_init.c                    | 2 +-
 src/mainboard/google/slippy/ec.c                          | 2 +-
 src/mainboard/google/stout/early_init.c                   | 2 +-
 src/mainboard/kontron/ktqm77/early_init.c                 | 2 +-
 src/mainboard/lenovo/t420/early_init.c                    | 2 +-
 src/mainboard/lenovo/t420s/early_init.c                   | 2 +-
 src/mainboard/lenovo/t430/early_init.c                    | 2 +-
 src/mainboard/lenovo/t430s/variants/t430s/romstage.c      | 2 +-
 src/mainboard/lenovo/t520/early_init.c                    | 2 +-
 src/mainboard/lenovo/t530/early_init.c                    | 2 +-
 src/mainboard/supermicro/x9scl/early_init.c               | 2 +-
 src/northbridge/amd/agesa/agesa_helper.h                  | 2 +-
 src/northbridge/amd/agesa/state_machine.h                 | 3 ++-
 src/northbridge/intel/e7505/romstage.c                    | 2 +-
 src/northbridge/intel/gm45/gm45.h                         | 6 +++---
 src/northbridge/intel/gm45/raminit.c                      | 2 +-
 src/northbridge/intel/gm45/raminit_read_write_training.c  | 4 ++--
 src/northbridge/intel/gm45/romstage.c                     | 2 +-
 src/northbridge/intel/haswell/broadwell_mrc/raminit.c     | 4 ++--
 src/northbridge/intel/haswell/haswell_mrc/raminit.c       | 2 +-
 .../intel/haswell/native_raminit/raminit_native.c         | 2 +-
 src/northbridge/intel/haswell/raminit.h                   | 2 +-
 src/northbridge/intel/haswell/romstage.c                  | 2 +-
 src/northbridge/intel/i440bx/raminit.c                    | 2 +-
 src/northbridge/intel/i440bx/raminit.h                    | 4 +++-
 src/northbridge/intel/i945/early_init.c                   | 6 +++---
 src/northbridge/intel/i945/i945.h                         | 2 +-
 src/northbridge/intel/i945/romstage.c                     | 2 +-
 src/northbridge/intel/ironlake/quickpath.c                | 4 ++--
 src/northbridge/intel/ironlake/raminit.c                  | 8 ++++----
 src/northbridge/intel/ironlake/raminit.h                  | 6 +++---
 src/northbridge/intel/ironlake/romstage.c                 | 4 ++--
 src/northbridge/intel/pineview/romstage.c                 | 5 +++--
 src/northbridge/intel/sandybridge/raminit.c               | 7 ++++---
 src/northbridge/intel/sandybridge/raminit_common.h        | 2 +-
 src/northbridge/intel/sandybridge/raminit_mrc.c           | 4 ++--
 src/northbridge/intel/sandybridge/raminit_native.c        | 2 +-
 src/northbridge/intel/sandybridge/romstage.c              | 4 ++--
 src/northbridge/intel/sandybridge/sandybridge.h           | 4 ++--
 src/northbridge/intel/x4x/raminit.c                       | 5 +++--
 src/northbridge/via/cx700/romstage.c                      | 2 +-
 src/security/intel/txt/ramstage.c                         | 2 +-
 src/soc/amd/stoneyridge/romstage.c                        | 2 +-
 src/soc/intel/baytrail/romstage/raminit.c                 | 4 ++--
 src/soc/intel/baytrail/romstage/romstage.c                | 2 +-
 src/soc/intel/broadwell/include/soc/romstage.h            | 2 +-
 src/soc/intel/broadwell/raminit.c                         | 4 ++--
 src/soc/intel/broadwell/romstage.c                        | 2 +-
 src/southbridge/intel/lynxpoint/early_pch_native.c        | 2 +-
 src/southbridge/intel/lynxpoint/pch.h                     | 2 +-
 67 files changed, 106 insertions(+), 98 deletions(-)

diff --git a/src/arch/arm64/include/arch/acpi.h b/src/arch/arm64/include/arch/acpi.h
index 396cdfd27f..1b88fe56bf 100644
--- a/src/arch/arm64/include/arch/acpi.h
+++ b/src/arch/arm64/include/arch/acpi.h
@@ -5,8 +5,8 @@
 
 /* STUB */
 
-static inline int acpi_is_wakeup(void) { return 0; }
-static inline int acpi_is_wakeup_s3(void) { return 0; }
-static inline int acpi_is_wakeup_s4(void) { return 0; }
+static inline bool acpi_is_wakeup(void) { return false; }
+static inline bool acpi_is_wakeup_s3(void) { return false; }
+static inline bool acpi_is_wakeup_s4(void) { return false; }
 
 #endif  /* __ARCH_ACPI_H_ */
diff --git a/src/drivers/amd/agesa/mtrr_fixme.c b/src/drivers/amd/agesa/mtrr_fixme.c
index 9db1fe5a1f..5b1294ecc4 100644
--- a/src/drivers/amd/agesa/mtrr_fixme.c
+++ b/src/drivers/amd/agesa/mtrr_fixme.c
@@ -33,7 +33,7 @@ static void set_range_uc(u32 base, u32 size)
 	wrmsr(MTRR_PHYS_MASK(i), msr);
 }
 
-void fixup_cbmem_to_UC(int s3resume)
+void fixup_cbmem_to_UC(bool s3resume)
 {
 	if (s3resume)
 		return;
@@ -54,7 +54,7 @@ static void recover_postcar_frame(struct postcar_frame *pcf)
 {
 	msr_t base, mask;
 	int i;
-	int s3resume = romstage_handoff_is_resume();
+	bool s3resume = romstage_handoff_is_resume();
 
 	/* Replicate non-UC MTRRs as left behind by AGESA.
 	 */
diff --git a/src/drivers/tpm/tpm.c b/src/drivers/tpm/tpm.c
index 3b582c84ab..f284146b9e 100644
--- a/src/drivers/tpm/tpm.c
+++ b/src/drivers/tpm/tpm.c
@@ -6,7 +6,7 @@
 
 static void init_tpm_dev(void *unused)
 {
-	int s3resume = acpi_is_wakeup_s3();
+	bool s3resume = acpi_is_wakeup_s3();
 	tpm_setup(s3resume);
 }
 
diff --git a/src/include/acpi/acpi.h b/src/include/acpi/acpi.h
index 1acdd7f7e7..b704255c46 100644
--- a/src/include/acpi/acpi.h
+++ b/src/include/acpi/acpi.h
@@ -1975,10 +1975,10 @@ static inline bool acpi_s3_resume_allowed(void)
 	return CONFIG(HAVE_ACPI_RESUME);
 }
 
-static inline int acpi_is_wakeup_s3(void)
+static inline bool acpi_is_wakeup_s3(void)
 {
 	if (!acpi_s3_resume_allowed())
-		return 0;
+		return false;
 
 	if (ENV_ROMSTAGE_OR_BEFORE)
 		return (acpi_get_sleep_type() == ACPI_S3);
diff --git a/src/include/cbmem.h b/src/include/cbmem.h
index fd258cda4e..13d3295f93 100644
--- a/src/include/cbmem.h
+++ b/src/include/cbmem.h
@@ -6,6 +6,7 @@
 #include <commonlib/bsd/cbmem_id.h> /* IWYU pragma: export */
 #include <stddef.h>
 #include <stdint.h>
+#include <stdbool.h>
 #include <boot/coreboot_tables.h>
 
 #define CBMEM_FSP_HOB_PTR	0x614
@@ -86,7 +87,7 @@ u64 cbmem_entry_size(const struct cbmem_entry *entry);
 
 /* Returns 0 if old cbmem was recovered. Recovery is only attempted if
  * s3resume is non-zero. */
-int cbmem_recovery(int s3resume);
+int cbmem_recovery(bool s3resume);
 /* Add a cbmem entry of a given size and id. These return NULL on failure. The
  * add function performs a find first and do not check against the original
  * size. */
diff --git a/src/include/romstage_handoff.h b/src/include/romstage_handoff.h
index d0e30b49cc..a9af518642 100644
--- a/src/include/romstage_handoff.h
+++ b/src/include/romstage_handoff.h
@@ -2,10 +2,11 @@
 #ifndef ROMSTAGE_HANDOFF_H
 #define ROMSTAGE_HANDOFF_H
 
+#include <stdbool.h>
+
 /* Returns 0 if initialized. Else < 0 if handoff structure not added. */
 int romstage_handoff_init(int is_s3_resume);
 
-/* Return 1 if resuming or 0 if not. */
-int romstage_handoff_is_resume(void);
+bool romstage_handoff_is_resume(void);
 
 #endif /* ROMSTAGE_HANDOFF_H */
diff --git a/src/include/stage_cache.h b/src/include/stage_cache.h
index 1e46b5cfe2..1a3811bc5c 100644
--- a/src/include/stage_cache.h
+++ b/src/include/stage_cache.h
@@ -39,10 +39,10 @@ static inline void stage_cache_get_raw(int stage_id, void **base, size_t *size)
 
 #endif
 
-static inline int resume_from_stage_cache(void)
+static inline bool resume_from_stage_cache(void)
 {
 	if (CONFIG(NO_STAGE_CACHE))
-		return 0;
+		return false;
 
 	/* TBD: Replace this with acpi_is_wakeup_s3(). */
 	return romstage_handoff_is_resume();
diff --git a/src/lib/bootblock.c b/src/lib/bootblock.c
index 5c202baa43..21b5d1eb31 100644
--- a/src/lib/bootblock.c
+++ b/src/lib/bootblock.c
@@ -59,7 +59,7 @@ void bootblock_main_with_timestamp(uint64_t base_timestamp,
 	bootblock_mainboard_init();
 
 	if (CONFIG(TPM_MEASURED_BOOT_INIT_BOOTBLOCK)) {
-		int s3resume = acpi_is_wakeup_s3();
+		bool s3resume = acpi_is_wakeup_s3();
 		tpm_setup(s3resume);
 	}
 
diff --git a/src/lib/imd_cbmem.c b/src/lib/imd_cbmem.c
index 2fc54bfff7..234e761177 100644
--- a/src/lib/imd_cbmem.c
+++ b/src/lib/imd_cbmem.c
@@ -121,7 +121,7 @@ int cbmem_initialize_id_size(u32 id, u64 size)
 	return 0;
 }
 
-int cbmem_recovery(int is_wakeup)
+int cbmem_recovery(bool is_wakeup)
 {
 	int rv = 0;
 	if (!is_wakeup)
diff --git a/src/lib/romstage_handoff.c b/src/lib/romstage_handoff.c
index faa2bc9f04..0296f8fa3e 100644
--- a/src/lib/romstage_handoff.c
+++ b/src/lib/romstage_handoff.c
@@ -53,19 +53,19 @@ int romstage_handoff_init(int is_s3_resume)
 	return 0;
 }
 
-int romstage_handoff_is_resume(void)
+bool romstage_handoff_is_resume(void)
 {
-	static int once, s3_resume;
+	static bool once, s3_resume;
 	struct romstage_handoff *handoff;
 
 	if (once)
 		return s3_resume;
 
 	/* Only try evaluate handoff once for s3 resume state. */
-	once = 1;
+	once = true;
 	handoff = cbmem_find(CBMEM_ID_ROMSTAGE_INFO);
 	if (handoff == NULL)
-		return 0;
+		return false;
 
 	s3_resume = handoff->s3_resume;
 	if (s3_resume)
diff --git a/src/mainboard/dell/snb_ivb_workstations/romstage.c b/src/mainboard/dell/snb_ivb_workstations/romstage.c
index d2a6b11848..54e1dd4659 100644
--- a/src/mainboard/dell/snb_ivb_workstations/romstage.c
+++ b/src/mainboard/dell/snb_ivb_workstations/romstage.c
@@ -23,7 +23,7 @@ void mainboard_late_rcba_config(void)
 	DIR_ROUTE(D20IR, PIRQA, PIRQB, PIRQC, PIRQD);
 }
 
-void mainboard_early_init(int s3resume)
+void mainboard_early_init(bool s3resume)
 {
 	uint16_t ec_fw_version;
 
diff --git a/src/mainboard/emulation/qemu-i440fx/romstage.c b/src/mainboard/emulation/qemu-i440fx/romstage.c
index f1c91762ff..db2c12eaeb 100644
--- a/src/mainboard/emulation/qemu-i440fx/romstage.c
+++ b/src/mainboard/emulation/qemu-i440fx/romstage.c
@@ -5,5 +5,5 @@
 
 void mainboard_romstage_entry(void)
 {
-	cbmem_recovery(0);
+	cbmem_recovery(false);
 }
diff --git a/src/mainboard/emulation/qemu-q35/romstage.c b/src/mainboard/emulation/qemu-q35/romstage.c
index c64321f665..fe5f7f922c 100644
--- a/src/mainboard/emulation/qemu-q35/romstage.c
+++ b/src/mainboard/emulation/qemu-q35/romstage.c
@@ -29,5 +29,5 @@ void mainboard_romstage_entry(void)
 		printk(BIOS_WARNING, "%s: Unsupported TSEG size: 0x%x\n", __func__, CONFIG_SMM_TSEG_SIZE);
 	}
 
-	cbmem_recovery(0);
+	cbmem_recovery(false);
 }
diff --git a/src/mainboard/google/auron/ec.c b/src/mainboard/google/auron/ec.c
index 2334cb61a4..09d0fe7efb 100644
--- a/src/mainboard/google/auron/ec.c
+++ b/src/mainboard/google/auron/ec.c
@@ -14,7 +14,7 @@ void mainboard_ec_init(void)
 		.s5_wake_events = MAINBOARD_EC_S5_WAKE_EVENTS,
 	};
 
-	int s3_wakeup = acpi_is_wakeup_s3();
+	bool s3_wakeup = acpi_is_wakeup_s3();
 
 	printk(BIOS_DEBUG, "%s\n", __func__);
 	post_code(0xf0);
diff --git a/src/mainboard/google/auron/variants/gandof/variant.c b/src/mainboard/google/auron/variants/gandof/variant.c
index b93e2c1472..b26300a9a8 100644
--- a/src/mainboard/google/auron/variants/gandof/variant.c
+++ b/src/mainboard/google/auron/variants/gandof/variant.c
@@ -24,7 +24,7 @@ int variant_smbios_data(struct device *dev, int *handle, unsigned long *current)
 	return len;
 }
 
-void mainboard_post_raminit(const int s3resume)
+void mainboard_post_raminit(const bool s3resume)
 {
 	if (!s3resume)
 		google_chromeec_kbbacklight(75);
diff --git a/src/mainboard/google/auron/variants/lulu/variant.c b/src/mainboard/google/auron/variants/lulu/variant.c
index 8349acaeff..0d42d4f8b5 100644
--- a/src/mainboard/google/auron/variants/lulu/variant.c
+++ b/src/mainboard/google/auron/variants/lulu/variant.c
@@ -34,7 +34,7 @@ int variant_smbios_data(struct device *dev, int *handle, unsigned long *current)
 	return len;
 }
 
-void mainboard_post_raminit(const int s3resume)
+void mainboard_post_raminit(const bool s3resume)
 {
 	if (!s3resume)
 		google_chromeec_kbbacklight(75);
diff --git a/src/mainboard/google/auron/variants/samus/variant.c b/src/mainboard/google/auron/variants/samus/variant.c
index 23468aba1e..a10e52c3fc 100644
--- a/src/mainboard/google/auron/variants/samus/variant.c
+++ b/src/mainboard/google/auron/variants/samus/variant.c
@@ -21,7 +21,7 @@ int variant_smbios_data(struct device *dev, int *handle, unsigned long *current)
 	return 0;
 }
 
-void mainboard_post_raminit(const int s3resume)
+void mainboard_post_raminit(const bool s3resume)
 {
 	if (!s3resume)
 		google_chromeec_kbbacklight(100);
diff --git a/src/mainboard/google/link/early_init.c b/src/mainboard/google/link/early_init.c
index 9d43da5a62..90f06d7f06 100644
--- a/src/mainboard/google/link/early_init.c
+++ b/src/mainboard/google/link/early_init.c
@@ -71,7 +71,7 @@ void mb_get_spd_map(struct spd_info *spdi)
 	spdi->spd_index = get_spd_index();
 }
 
-void mainboard_early_init(int s3resume)
+void mainboard_early_init(bool s3resume)
 {
 	if (!s3resume) {
 		/* This is the fastest way to let users know
diff --git a/src/mainboard/google/slippy/ec.c b/src/mainboard/google/slippy/ec.c
index 2334cb61a4..09d0fe7efb 100644
--- a/src/mainboard/google/slippy/ec.c
+++ b/src/mainboard/google/slippy/ec.c
@@ -14,7 +14,7 @@ void mainboard_ec_init(void)
 		.s5_wake_events = MAINBOARD_EC_S5_WAKE_EVENTS,
 	};
 
-	int s3_wakeup = acpi_is_wakeup_s3();
+	bool s3_wakeup = acpi_is_wakeup_s3();
 
 	printk(BIOS_DEBUG, "%s\n", __func__);
 	post_code(0xf0);
diff --git a/src/mainboard/google/stout/early_init.c b/src/mainboard/google/stout/early_init.c
index 178d270da7..4b29c591bd 100644
--- a/src/mainboard/google/stout/early_init.c
+++ b/src/mainboard/google/stout/early_init.c
@@ -83,7 +83,7 @@ void mainboard_fill_pei_data(struct pei_data *pei_data)
 	/* TODO: Confirm if nortbridge_fill_pei_data() gets .system_type right (should be 0) */
 }
 
-void mainboard_early_init(int s3resume)
+void mainboard_early_init(bool s3resume)
 {
 	/* Do ec reset as early as possible, but skip it on S3 resume */
 	if (!s3resume) {
diff --git a/src/mainboard/kontron/ktqm77/early_init.c b/src/mainboard/kontron/ktqm77/early_init.c
index 7a2376508f..1d2503a746 100644
--- a/src/mainboard/kontron/ktqm77/early_init.c
+++ b/src/mainboard/kontron/ktqm77/early_init.c
@@ -54,7 +54,7 @@ void mainboard_fill_pei_data(struct pei_data *pei_data)
 {
 }
 
-void mainboard_early_init(int s3resume)
+void mainboard_early_init(bool s3resume)
 {
 	/* Enable PEG10 (1x16) */
 	pci_write_config32(PCI_DEV(0, 0, 0), DEVEN,
diff --git a/src/mainboard/lenovo/t420/early_init.c b/src/mainboard/lenovo/t420/early_init.c
index 514e5677c2..b14fea93a6 100644
--- a/src/mainboard/lenovo/t420/early_init.c
+++ b/src/mainboard/lenovo/t420/early_init.c
@@ -30,7 +30,7 @@ static void hybrid_graphics_init(void)
 	pci_write_config32(PCI_DEV(0, 0, 0), DEVEN, reg32);
 }
 
-void mainboard_early_init(int s3resume)
+void mainboard_early_init(bool s3resume)
 {
 	hybrid_graphics_init();
 }
diff --git a/src/mainboard/lenovo/t420s/early_init.c b/src/mainboard/lenovo/t420s/early_init.c
index 514e5677c2..b14fea93a6 100644
--- a/src/mainboard/lenovo/t420s/early_init.c
+++ b/src/mainboard/lenovo/t420s/early_init.c
@@ -30,7 +30,7 @@ static void hybrid_graphics_init(void)
 	pci_write_config32(PCI_DEV(0, 0, 0), DEVEN, reg32);
 }
 
-void mainboard_early_init(int s3resume)
+void mainboard_early_init(bool s3resume)
 {
 	hybrid_graphics_init();
 }
diff --git a/src/mainboard/lenovo/t430/early_init.c b/src/mainboard/lenovo/t430/early_init.c
index ed1f59b888..8306e0e720 100644
--- a/src/mainboard/lenovo/t430/early_init.c
+++ b/src/mainboard/lenovo/t430/early_init.c
@@ -32,7 +32,7 @@ static void hybrid_graphics_init(void)
 	pci_write_config32(PCI_DEV(0, 0, 0), DEVEN, reg32);
 }
 
-void mainboard_early_init(int s3resume)
+void mainboard_early_init(bool s3resume)
 {
 	hybrid_graphics_init();
 }
diff --git a/src/mainboard/lenovo/t430s/variants/t430s/romstage.c b/src/mainboard/lenovo/t430s/variants/t430s/romstage.c
index b69c71d288..211ec2d345 100644
--- a/src/mainboard/lenovo/t430s/variants/t430s/romstage.c
+++ b/src/mainboard/lenovo/t430s/variants/t430s/romstage.c
@@ -7,7 +7,7 @@
 #include <ec/lenovo/pmh7/pmh7.h>
 #include <types.h>
 
-void mainboard_early_init(int s3resume)
+void mainboard_early_init(bool s3resume)
 {
 	u8 enable_peg = get_uint_option("enable_dual_graphics", 0);
 
diff --git a/src/mainboard/lenovo/t520/early_init.c b/src/mainboard/lenovo/t520/early_init.c
index 0b0a57639c..ba98ec700f 100644
--- a/src/mainboard/lenovo/t520/early_init.c
+++ b/src/mainboard/lenovo/t520/early_init.c
@@ -34,7 +34,7 @@ static void hybrid_graphics_init(void)
 	pci_write_config32(PCI_DEV(0, 0, 0), DEVEN, reg32);
 }
 
-void mainboard_early_init(int s3resume)
+void mainboard_early_init(bool s3resume)
 {
 	hybrid_graphics_init();
 }
diff --git a/src/mainboard/lenovo/t530/early_init.c b/src/mainboard/lenovo/t530/early_init.c
index b6bfa5ffe5..429ab2857a 100644
--- a/src/mainboard/lenovo/t530/early_init.c
+++ b/src/mainboard/lenovo/t530/early_init.c
@@ -33,7 +33,7 @@ static void hybrid_graphics_init(void)
 	pci_write_config32(PCI_DEV(0, 0, 0), DEVEN, reg32);
 }
 
-void mainboard_early_init(int s3resume)
+void mainboard_early_init(bool s3resume)
 {
 	hybrid_graphics_init();
 }
diff --git a/src/mainboard/supermicro/x9scl/early_init.c b/src/mainboard/supermicro/x9scl/early_init.c
index c284240f8a..c8a3e6ed5f 100644
--- a/src/mainboard/supermicro/x9scl/early_init.c
+++ b/src/mainboard/supermicro/x9scl/early_init.c
@@ -83,7 +83,7 @@ void bootblock_mainboard_early_init(void)
 	bmc_init();
 }
 
-void mainboard_early_init(int s3resume)
+void mainboard_early_init(bool s3resume)
 {
 	/* Disable IGD VGA decode, no GTT or GFX stolen */
 	pci_write_config16(PCI_DEV(0, 0, 0), GGC, 2);
diff --git a/src/northbridge/amd/agesa/agesa_helper.h b/src/northbridge/amd/agesa/agesa_helper.h
index e8a1323619..d64c7f59a8 100644
--- a/src/northbridge/amd/agesa/agesa_helper.h
+++ b/src/northbridge/amd/agesa/agesa_helper.h
@@ -34,7 +34,7 @@ void EmptyHeap(void);
 
 #define HIGH_MEMORY_SCRATCH		0x30000
 
-void fixup_cbmem_to_UC(int s3resume);
+void fixup_cbmem_to_UC(bool s3resume);
 
 void restore_mtrr(void);
 void backup_mtrr(void);
diff --git a/src/northbridge/amd/agesa/state_machine.h b/src/northbridge/amd/agesa/state_machine.h
index 6c77d21cf2..f1d3c66346 100644
--- a/src/northbridge/amd/agesa/state_machine.h
+++ b/src/northbridge/amd/agesa/state_machine.h
@@ -3,6 +3,7 @@
 #ifndef _STATE_MACHINE_H_
 #define _STATE_MACHINE_H_
 
+#include <stdbool.h>
 #include <stdint.h>
 #include <AGESA.h>
 #include <AMD.h>
@@ -28,7 +29,7 @@ struct sysinfo
 {
 	AMD_CONFIG_PARAMS StdHeader;
 
-	int s3resume;
+	bool s3resume;
 };
 
 void board_BeforeAgesa(struct sysinfo *cb);
diff --git a/src/northbridge/intel/e7505/romstage.c b/src/northbridge/intel/e7505/romstage.c
index d997ee19a8..77cdf9c7e9 100644
--- a/src/northbridge/intel/e7505/romstage.c
+++ b/src/northbridge/intel/e7505/romstage.c
@@ -14,5 +14,5 @@ void mainboard_romstage_entry(void)
 
 	sdram_initialize();
 
-	cbmem_recovery(0);
+	cbmem_recovery(false);
 }
diff --git a/src/northbridge/intel/gm45/gm45.h b/src/northbridge/intel/gm45/gm45.h
index 5d9ac56606..f68bfdee7a 100644
--- a/src/northbridge/intel/gm45/gm45.h
+++ b/src/northbridge/intel/gm45/gm45.h
@@ -410,7 +410,7 @@ void gm45_early_reset(void);
 
 void enter_raminit_or_reset(void);
 void get_gmch_info(sysinfo_t *);
-void raminit(sysinfo_t *, int s3resume);
+void raminit(sysinfo_t *, bool s3resume);
 void raminit_thermal(const sysinfo_t *);
 void setup_sdram_meminfo(const sysinfo_t *);
 void init_igd(const sysinfo_t *const);
@@ -423,8 +423,8 @@ u32 raminit_get_rank_addr(unsigned int channel, unsigned int rank);
 void raminit_rcomp_calibration(stepping_t stepping);
 void raminit_reset_readwrite_pointers(void);
 void raminit_receive_enable_calibration(int ddr_type, const timings_t *, const dimminfo_t *);
-void raminit_write_training(const mem_clock_t, const dimminfo_t *, int s3resume);
-void raminit_read_training(const dimminfo_t *, int s3resume);
+void raminit_write_training(const mem_clock_t, const dimminfo_t *, bool s3resume);
+void raminit_read_training(const dimminfo_t *, bool s3resume);
 
 void gm45_late_init(stepping_t);
 
diff --git a/src/northbridge/intel/gm45/raminit.c b/src/northbridge/intel/gm45/raminit.c
index b7e013959a..def9e1e331 100644
--- a/src/northbridge/intel/gm45/raminit.c
+++ b/src/northbridge/intel/gm45/raminit.c
@@ -2100,7 +2100,7 @@ void raminit_reset_readwrite_pointers(void)
 	mchbar_setbits32(0x15f0, 1 << 10);
 }
 
-void raminit(sysinfo_t *const sysinfo, const int s3resume)
+void raminit(sysinfo_t *const sysinfo, const bool s3resume)
 {
 	const dimminfo_t *const dimms = sysinfo->dimms;
 	const timings_t *const timings = &sysinfo->selected_timings;
diff --git a/src/northbridge/intel/gm45/raminit_read_write_training.c b/src/northbridge/intel/gm45/raminit_read_write_training.c
index d3571dfbd4..f2308abd10 100644
--- a/src/northbridge/intel/gm45/raminit_read_write_training.c
+++ b/src/northbridge/intel/gm45/raminit_read_write_training.c
@@ -262,7 +262,7 @@ static void read_training_restore_results(void)
 		}
 	}
 }
-void raminit_read_training(const dimminfo_t *const dimms, const int s3resume)
+void raminit_read_training(const dimminfo_t *const dimms, const bool s3resume)
 {
 	if (!s3resume) {
 		perform_read_training(dimms);
@@ -633,7 +633,7 @@ static void write_training_restore_results(const int memclk1067)
 }
 void raminit_write_training(const mem_clock_t ddr3clock,
 			    const dimminfo_t *const dimms,
-			    const int s3resume)
+			    const bool s3resume)
 {
 	const int memclk1067 = ddr3clock == MEM_CLOCK_1067MT;
 
diff --git a/src/northbridge/intel/gm45/romstage.c b/src/northbridge/intel/gm45/romstage.c
index bc17618b03..b44bee73d3 100644
--- a/src/northbridge/intel/gm45/romstage.c
+++ b/src/northbridge/intel/gm45/romstage.c
@@ -33,7 +33,7 @@ void __weak mb_post_raminit_setup(void)
 void mainboard_romstage_entry(void)
 {
 	sysinfo_t sysinfo;
-	int s3resume = 0;
+	bool s3resume = false;
 	int cbmem_initted;
 	u16 reg16;
 
diff --git a/src/northbridge/intel/haswell/broadwell_mrc/raminit.c b/src/northbridge/intel/haswell/broadwell_mrc/raminit.c
index e96f1a3adf..9114c26783 100644
--- a/src/northbridge/intel/haswell/broadwell_mrc/raminit.c
+++ b/src/northbridge/intel/haswell/broadwell_mrc/raminit.c
@@ -310,7 +310,7 @@ static uint8_t map_to_pei_oc_pin(const uint8_t oc_pin)
 	return oc_pin >= USB_OC_PIN_SKIP ? PEI_USB_OC_PIN_SKIP : oc_pin;
 }
 
-static bool early_init_native(int s3resume)
+static bool early_init_native(bool s3resume)
 {
 	printk(BIOS_DEBUG, "Starting native platform initialisation\n");
 
@@ -326,7 +326,7 @@ static bool early_init_native(int s3resume)
 	return cpu_replaced;
 }
 
-void perform_raminit(const int s3resume)
+void perform_raminit(const bool s3resume)
 {
 	const struct northbridge_intel_haswell_config *cfg = config_of_soc();
 
diff --git a/src/northbridge/intel/haswell/haswell_mrc/raminit.c b/src/northbridge/intel/haswell/haswell_mrc/raminit.c
index 62aa89ca79..edd9b049d4 100644
--- a/src/northbridge/intel/haswell/haswell_mrc/raminit.c
+++ b/src/northbridge/intel/haswell/haswell_mrc/raminit.c
@@ -340,7 +340,7 @@ static uint8_t map_to_pei_oc_pin(const uint8_t oc_pin)
 	return oc_pin >= USB_OC_PIN_SKIP ? PEI_USB_OC_PIN_SKIP : oc_pin;
 }
 
-void perform_raminit(const int s3resume)
+void perform_raminit(const bool s3resume)
 {
 	const struct device *gbe = pcidev_on_root(0x19, 0);
 
diff --git a/src/northbridge/intel/haswell/native_raminit/raminit_native.c b/src/northbridge/intel/haswell/native_raminit/raminit_native.c
index 3ad8ce29e7..4ac220cb22 100644
--- a/src/northbridge/intel/haswell/native_raminit/raminit_native.c
+++ b/src/northbridge/intel/haswell/native_raminit/raminit_native.c
@@ -163,7 +163,7 @@ static enum raminit_boot_mode do_actual_raminit(
 	return bootmode;
 }
 
-void perform_raminit(const int s3resume)
+void perform_raminit(const bool s3resume)
 {
 	/*
 	 * See, this function's name is a lie. There are more things to
diff --git a/src/northbridge/intel/haswell/raminit.h b/src/northbridge/intel/haswell/raminit.h
index 6c76739e77..3f13a03db5 100644
--- a/src/northbridge/intel/haswell/raminit.h
+++ b/src/northbridge/intel/haswell/raminit.h
@@ -17,6 +17,6 @@ struct spd_info {
 void mb_get_spd_map(struct spd_info *spdi);
 
 void get_spd_info(struct spd_info *spdi, const struct northbridge_intel_haswell_config *cfg);
-void perform_raminit(const int s3resume);
+void perform_raminit(const bool s3resume);
 
 #endif	/* NORTHBRIDGE_INTEL_HASWELL_RAMINIT_H */
diff --git a/src/northbridge/intel/haswell/romstage.c b/src/northbridge/intel/haswell/romstage.c
index ce14915b2b..85fe967c7d 100644
--- a/src/northbridge/intel/haswell/romstage.c
+++ b/src/northbridge/intel/haswell/romstage.c
@@ -27,7 +27,7 @@ void mainboard_romstage_entry(void)
 	haswell_early_initialization();
 	printk(BIOS_DEBUG, "Back from haswell_early_initialization()\n");
 
-	const int s3resume = southbridge_detect_s3_resume();
+	const bool s3resume = southbridge_detect_s3_resume();
 
 	elog_boot_notify(s3resume);
 
diff --git a/src/northbridge/intel/i440bx/raminit.c b/src/northbridge/intel/i440bx/raminit.c
index f82d54c821..e940b8d6f4 100644
--- a/src/northbridge/intel/i440bx/raminit.c
+++ b/src/northbridge/intel/i440bx/raminit.c
@@ -989,7 +989,7 @@ static void sdram_enable(void)
 /* Implemented under mainboard. */
 void __weak enable_spd(void) { }
 
-void sdram_initialize(int s3resume)
+void sdram_initialize(bool s3resume)
 {
 	timestamp_add_now(TS_INITRAM_START);
 	enable_spd();
diff --git a/src/northbridge/intel/i440bx/raminit.h b/src/northbridge/intel/i440bx/raminit.h
index b35554f2e4..0b6eb10623 100644
--- a/src/northbridge/intel/i440bx/raminit.h
+++ b/src/northbridge/intel/i440bx/raminit.h
@@ -3,6 +3,8 @@
 #ifndef RAMINIT_H
 #define RAMINIT_H
 
+#include <stdbool.h>
+
 /* The 440BX supports up to four (single- or double-sided) DIMMs. */
 #define DIMM_SOCKETS	4
 
@@ -13,7 +15,7 @@
 #define DIMM3		0x53
 
 void enable_spd(void);
-void sdram_initialize(int s3resume);
+void sdram_initialize(bool s3resume);
 
 /* Debug */
 #if CONFIG(DEBUG_RAM_SETUP)
diff --git a/src/northbridge/intel/i945/early_init.c b/src/northbridge/intel/i945/early_init.c
index eea20282cd..ac36f0810b 100644
--- a/src/northbridge/intel/i945/early_init.c
+++ b/src/northbridge/intel/i945/early_init.c
@@ -793,16 +793,16 @@ void i945_early_initialization(void)
 	RCBA32(0x2010) |= (1 << 10);
 }
 
-static void i945_prepare_resume(int s3resume)
+static void i945_prepare_resume(bool s3resume)
 {
-	int cbmem_was_initted;
+	bool cbmem_was_initted;
 
 	cbmem_was_initted = !cbmem_recovery(s3resume);
 
 	romstage_handoff_init(cbmem_was_initted && s3resume);
 }
 
-void i945_late_initialization(int s3resume)
+void i945_late_initialization(bool s3resume)
 {
 	i945_setup_egress_port();
 
diff --git a/src/northbridge/intel/i945/i945.h b/src/northbridge/intel/i945/i945.h
index 4818a730ab..a9f956a82e 100644
--- a/src/northbridge/intel/i945/i945.h
+++ b/src/northbridge/intel/i945/i945.h
@@ -323,7 +323,7 @@
 
 int i945_silicon_revision(void);
 void i945_early_initialization(void);
-void i945_late_initialization(int s3resume);
+void i945_late_initialization(bool s3resume);
 
 /* debugging functions */
 void print_pci_devices(void);
diff --git a/src/northbridge/intel/i945/romstage.c b/src/northbridge/intel/i945/romstage.c
index 61b9bcff43..5607f78b8c 100644
--- a/src/northbridge/intel/i945/romstage.c
+++ b/src/northbridge/intel/i945/romstage.c
@@ -26,7 +26,7 @@ __weak void mainboard_get_spd_map(u8 spd_map[4])
 
 void mainboard_romstage_entry(void)
 {
-	int s3resume = 0;
+	bool s3resume = false;
 	u8 spd_map[4] = {};
 
 	mainboard_lpc_decode();
diff --git a/src/northbridge/intel/ironlake/quickpath.c b/src/northbridge/intel/ironlake/quickpath.c
index aac852ab11..839b7846c4 100644
--- a/src/northbridge/intel/ironlake/quickpath.c
+++ b/src/northbridge/intel/ironlake/quickpath.c
@@ -353,7 +353,7 @@ set_2dx8_reg(struct raminfo *info, u16 reg, u8 mode, u16 freq1, u16 freq2,
 	}
 }
 
-static void set_2dxx_series(struct raminfo *info, int s3resume)
+static void set_2dxx_series(struct raminfo *info, bool s3resume)
 {
 	set_2dx8_reg(info, 0x2d00, 0, 0x78, frequency_11(info) / 2, 1359, 1005,
 		     0, 1);
@@ -573,7 +573,7 @@ void early_quickpath_init(struct raminfo *info, const u8 x2ca8)
 	mchbar_write32(0x18ac, 0x22222);
 }
 
-void late_quickpath_init(struct raminfo *info, const int s3resume)
+void late_quickpath_init(struct raminfo *info, const bool s3resume)
 {
 	const u16 deven = pci_read_config16(NORTHBRIDGE, DEVEN);
 
diff --git a/src/northbridge/intel/ironlake/raminit.c b/src/northbridge/intel/ironlake/raminit.c
index b2620975a7..f4f41e5640 100644
--- a/src/northbridge/intel/ironlake/raminit.c
+++ b/src/northbridge/intel/ironlake/raminit.c
@@ -333,7 +333,7 @@ static int count_ranks_in_channel(struct raminfo *info, int channel)
 }
 
 static void
-config_rank(struct raminfo *info, int s3resume, int channel, int slot, int rank)
+config_rank(struct raminfo *info, bool s3resume, int channel, int slot, int rank)
 {
 	int add;
 
@@ -2856,7 +2856,7 @@ static void dmi_setup(void)
 	gav(inb(DEFAULT_GPIOBASE | 0xe));	// = 0xfdcaff6e
 }
 
-void chipset_init(const int s3resume)
+void chipset_init(const bool s3resume)
 {
 	u8 x2ca8;
 	u16 ggc;
@@ -2915,12 +2915,12 @@ static u8 get_bits_420(const u32 reg32)
 	return val;
 }
 
-void raminit(const int s3resume, const u8 *spd_addrmap)
+void raminit(const bool s3resume, const u8 *spd_addrmap)
 {
 	unsigned int channel, slot, lane, rank;
 	struct raminfo info;
 	u8 x2ca8;
-	int cbmem_wasnot_inited;
+	bool cbmem_wasnot_inited;
 
 	x2ca8 = mchbar_read8(0x2ca8);
 
diff --git a/src/northbridge/intel/ironlake/raminit.h b/src/northbridge/intel/ironlake/raminit.h
index edfce51125..377864a10f 100644
--- a/src/northbridge/intel/ironlake/raminit.h
+++ b/src/northbridge/intel/ironlake/raminit.h
@@ -92,7 +92,7 @@ static inline unsigned int frequency_11(struct raminfo *info)
 	return (info->clock_speed_index + 3) * 120;
 }
 
-void chipset_init(const int s3resume);
+void chipset_init(const bool s3resume);
 /* spd_addrmap is array of 4 elements:
    Channel 0 Slot 0
    Channel 0 Slot 1
@@ -100,10 +100,10 @@ void chipset_init(const int s3resume);
    Channel 1 Slot 1
    0 means "not present"
 */
-void raminit(const int s3resume, const u8 *spd_addrmap);
+void raminit(const bool s3resume, const u8 *spd_addrmap);
 
 u16 get_max_timing(struct raminfo *info, int channel);
 void early_quickpath_init(struct raminfo *info, const u8 x2ca8);
-void late_quickpath_init(struct raminfo *info, const int s3resume);
+void late_quickpath_init(struct raminfo *info, const bool s3resume);
 
 #endif				/* RAMINIT_H */
diff --git a/src/northbridge/intel/ironlake/romstage.c b/src/northbridge/intel/ironlake/romstage.c
index 1e6bf67e3e..aea1cc5e1e 100644
--- a/src/northbridge/intel/ironlake/romstage.c
+++ b/src/northbridge/intel/ironlake/romstage.c
@@ -22,7 +22,7 @@
  */
 void mainboard_romstage_entry(void)
 {
-	int s3resume = 0;
+	bool s3resume = false;
 	u8 spd_addrmap[4] = {};
 
 	/* TODO, make this configurable */
@@ -34,7 +34,7 @@ void mainboard_romstage_entry(void)
 	if (s3resume) {
 		u8 reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa2);
 		if (!(reg8 & 0x20)) {
-			s3resume = 0;
+			s3resume = false;
 			printk(BIOS_DEBUG, "Bad resume from S3 detected.\n");
 		}
 	}
diff --git a/src/northbridge/intel/pineview/romstage.c b/src/northbridge/intel/pineview/romstage.c
index 03058ec2b5..5755eaaf7d 100644
--- a/src/northbridge/intel/pineview/romstage.c
+++ b/src/northbridge/intel/pineview/romstage.c
@@ -27,8 +27,9 @@ __weak void mb_pirq_setup(void)
 void mainboard_romstage_entry(void)
 {
 	u8 spd_addrmap[4] = {};
-	int boot_path, cbmem_was_initted;
-	int s3resume = 0;
+	int boot_path;
+	bool cbmem_was_initted;
+	bool s3resume = false;
 
 	/* Do some early chipset init, necessary for RAM init to work */
 	i82801gx_early_init();
diff --git a/src/northbridge/intel/sandybridge/raminit.c b/src/northbridge/intel/sandybridge/raminit.c
index dd6b36b25b..439221f84b 100644
--- a/src/northbridge/intel/sandybridge/raminit.c
+++ b/src/northbridge/intel/sandybridge/raminit.c
@@ -341,9 +341,10 @@ static void reinit_ctrl(ramctr_timing *ctrl, const u32 cpuid)
 			ctrl->ecc_forced ? "yes" : "no");
 }
 
-static void init_dram_ddr3(int s3resume, const u32 cpuid)
+static void init_dram_ddr3(bool s3resume, const u32 cpuid)
 {
-	int me_uma_size, cbmem_was_inited, fast_boot, err;
+	int me_uma_size, fast_boot, err;
+	bool cbmem_was_inited;
 	ramctr_timing ctrl;
 	spd_ddr3_raw_data spds[4];
 	size_t mrc_size = 0;
@@ -527,7 +528,7 @@ static void init_dram_ddr3(int s3resume, const u32 cpuid)
 		setup_sdram_meminfo(&ctrl);
 }
 
-void perform_raminit(int s3resume)
+void perform_raminit(bool s3resume)
 {
 	post_code(0x3a);
 	init_dram_ddr3(s3resume, cpu_get_cpuid());
diff --git a/src/northbridge/intel/sandybridge/raminit_common.h b/src/northbridge/intel/sandybridge/raminit_common.h
index ee7c525cad..202f67a78a 100644
--- a/src/northbridge/intel/sandybridge/raminit_common.h
+++ b/src/northbridge/intel/sandybridge/raminit_common.h
@@ -468,7 +468,7 @@ void set_read_write_timings(ramctr_timing *ctrl);
 void set_normal_operation(ramctr_timing *ctrl);
 void final_registers(ramctr_timing *ctrl);
 void restore_timings(ramctr_timing *ctrl);
-int try_init_dram_ddr3(ramctr_timing *ctrl, int fast_boot, int s3resume, int me_uma_size);
+int try_init_dram_ddr3(ramctr_timing *ctrl, int fast_boot, bool s3resume, int me_uma_size);
 
 void channel_scrub(ramctr_timing *ctrl);
 bool get_host_ecc_cap(void);
diff --git a/src/northbridge/intel/sandybridge/raminit_mrc.c b/src/northbridge/intel/sandybridge/raminit_mrc.c
index b81716aff0..146ec24fcf 100644
--- a/src/northbridge/intel/sandybridge/raminit_mrc.c
+++ b/src/northbridge/intel/sandybridge/raminit_mrc.c
@@ -340,7 +340,7 @@ static void disable_p2p(void)
 
 static void setup_sdram_meminfo(struct pei_data *pei_data);
 
-void perform_raminit(int s3resume)
+void perform_raminit(bool s3resume)
 {
 	const struct northbridge_intel_sandybridge_config *cfg = config_of_soc();
 	struct pei_data pei_data = {
@@ -412,7 +412,7 @@ void perform_raminit(int s3resume)
 		hexdump(mrc_var, sizeof(*mrc_var));
 	}
 
-	const int cbmem_was_initted = !cbmem_recovery(s3resume);
+	const bool cbmem_was_initted = !cbmem_recovery(s3resume);
 	if (!s3resume)
 		save_mrc_data(&pei_data);
 
diff --git a/src/northbridge/intel/sandybridge/raminit_native.c b/src/northbridge/intel/sandybridge/raminit_native.c
index ed11945ebf..282058b0d9 100644
--- a/src/northbridge/intel/sandybridge/raminit_native.c
+++ b/src/northbridge/intel/sandybridge/raminit_native.c
@@ -630,7 +630,7 @@ static void dram_ioregs(ramctr_timing *ctrl)
 	printram("done\n");
 }
 
-int try_init_dram_ddr3(ramctr_timing *ctrl, int fast_boot, int s3resume, int me_uma_size)
+int try_init_dram_ddr3(ramctr_timing *ctrl, int fast_boot, bool s3resume, int me_uma_size)
 {
 	int err;
 
diff --git a/src/northbridge/intel/sandybridge/romstage.c b/src/northbridge/intel/sandybridge/romstage.c
index 86569c1cb4..06380725f6 100644
--- a/src/northbridge/intel/sandybridge/romstage.c
+++ b/src/northbridge/intel/sandybridge/romstage.c
@@ -16,7 +16,7 @@
 #include <southbridge/intel/common/pmclib.h>
 #include <elog.h>
 
-__weak void mainboard_early_init(int s3resume)
+__weak void mainboard_early_init(bool s3resume)
 {
 }
 
@@ -48,7 +48,7 @@ static void early_pch_reset_pmcon(void)
 /* The romstage entry point for this platform is not mainboard-specific, hence the name */
 void mainboard_romstage_entry(void)
 {
-	int s3resume = 0;
+	bool s3resume = false;
 
 	if (mchbar_read16(SSKPD_HI) == 0xcafe)
 		system_reset();
diff --git a/src/northbridge/intel/sandybridge/sandybridge.h b/src/northbridge/intel/sandybridge/sandybridge.h
index 0eaa4ec340..2b07c495a3 100644
--- a/src/northbridge/intel/sandybridge/sandybridge.h
+++ b/src/northbridge/intel/sandybridge/sandybridge.h
@@ -64,8 +64,8 @@ void northbridge_romstage_finalize(void);
 void early_init_dmi(void);
 
 /* mainboard_early_init: Optional callback, run after console init but before raminit. */
-void mainboard_early_init(int s3resume);
-void perform_raminit(int s3resume);
+void mainboard_early_init(bool s3resume);
+void perform_raminit(bool s3resume);
 void report_memory_config(void);
 enum platform_type get_platform_type(void);
 
diff --git a/src/northbridge/intel/x4x/raminit.c b/src/northbridge/intel/x4x/raminit.c
index 3149074e19..6b0f3588e0 100644
--- a/src/northbridge/intel/x4x/raminit.c
+++ b/src/northbridge/intel/x4x/raminit.c
@@ -561,7 +561,8 @@ void sdram_initialize(int boot_path, const u8 *spd_map)
 {
 	struct sysinfo s, *ctrl_cached;
 	u8 reg8;
-	int fast_boot, cbmem_was_inited;
+	int fast_boot;
+	bool cbmem_was_inited;
 	size_t mrc_size;
 
 	timestamp_add_now(TS_INITRAM_START);
@@ -640,7 +641,7 @@ void sdram_initialize(int boot_path, const u8 *spd_map)
 
 	printk(BIOS_DEBUG, "RAM initialization finished.\n");
 
-	int s3resume = boot_path == BOOT_PATH_RESUME;
+	bool s3resume = boot_path == BOOT_PATH_RESUME;
 
 	cbmem_was_inited = !cbmem_recovery(s3resume);
 	if (!fast_boot)
diff --git a/src/northbridge/via/cx700/romstage.c b/src/northbridge/via/cx700/romstage.c
index d554b7656f..9294da8ff4 100644
--- a/src/northbridge/via/cx700/romstage.c
+++ b/src/northbridge/via/cx700/romstage.c
@@ -57,7 +57,7 @@ void mainboard_romstage_entry(void)
 
 	sdram_enable(&config->dram_cfg);
 
-	cbmem_recovery(/* s3resume => */0);
+	cbmem_recovery(/* s3resume => */false);
 
 	prepare_and_run_postcar();
 }
diff --git a/src/security/intel/txt/ramstage.c b/src/security/intel/txt/ramstage.c
index 5c03da909a..85606d4ec8 100644
--- a/src/security/intel/txt/ramstage.c
+++ b/src/security/intel/txt/ramstage.c
@@ -173,7 +173,7 @@ static void init_intel_txt(void *unused)
 		log_ibb_measurements();
 	}
 
-	int s3resume = acpi_is_wakeup_s3();
+	bool s3resume = acpi_is_wakeup_s3();
 	if (!s3resume && !CONFIG(INTEL_CBNT_SUPPORT)) {
 		printk(BIOS_INFO, "TEE-TXT: Scheck...\n");
 		if (intel_txt_run_bios_acm(ACMINPUT_SCHECK) < 0) {
diff --git a/src/soc/amd/stoneyridge/romstage.c b/src/soc/amd/stoneyridge/romstage.c
index 900d1a668a..8e2ebae756 100644
--- a/src/soc/amd/stoneyridge/romstage.c
+++ b/src/soc/amd/stoneyridge/romstage.c
@@ -55,7 +55,7 @@ void __noreturn romstage_main(void)
 	msr_t base, mask;
 	msr_t mtrr_cap = rdmsr(MTRR_CAP_MSR);
 	int vmtrrs = mtrr_cap.lo & MTRR_CAP_VCNT;
-	int s3_resume = acpi_is_wakeup_s3();
+	bool s3_resume = acpi_is_wakeup_s3();
 	int i;
 
 	soc_enable_psp_early();
diff --git a/src/soc/intel/baytrail/romstage/raminit.c b/src/soc/intel/baytrail/romstage/raminit.c
index 6244072c55..82e98f75d6 100644
--- a/src/soc/intel/baytrail/romstage/raminit.c
+++ b/src/soc/intel/baytrail/romstage/raminit.c
@@ -129,7 +129,7 @@ void raminit(struct mrc_params *mp, int prev_sleep_state)
 	mp->prev_sleep_state = prev_sleep_state;
 	mp->rmt_enabled = CONFIG(MRC_RMT);
 
-	int s3resume = prev_sleep_state == ACPI_S3;
+	bool s3resume = prev_sleep_state == ACPI_S3;
 
 	/* Default to 2GiB IO hole. */
 	if (!mp->io_hole_mb)
@@ -182,7 +182,7 @@ void raminit(struct mrc_params *mp, int prev_sleep_state)
 
 	ret = mrc_entry(mp);
 
-	int cbmem_was_initted = !cbmem_recovery(s3resume);
+	bool cbmem_was_initted = !cbmem_recovery(s3resume);
 	if (s3resume && !cbmem_was_initted) {
 		/* Failed S3 resume, reset to come up cleanly */
 		printk(BIOS_CRIT, "Failed to recover CBMEM in S3 resume.\n");
diff --git a/src/soc/intel/baytrail/romstage/romstage.c b/src/soc/intel/baytrail/romstage/romstage.c
index 658da2c44b..572f03e33e 100644
--- a/src/soc/intel/baytrail/romstage/romstage.c
+++ b/src/soc/intel/baytrail/romstage/romstage.c
@@ -108,7 +108,7 @@ void mainboard_romstage_entry(void)
 
 	printk(BIOS_DEBUG, "prev_sleep_state = S%d\n", prev_sleep_state);
 
-	int s3resume = prev_sleep_state == ACPI_S3;
+	bool s3resume = prev_sleep_state == ACPI_S3;
 
 	elog_boot_notify(s3resume);
 
diff --git a/src/soc/intel/broadwell/include/soc/romstage.h b/src/soc/intel/broadwell/include/soc/romstage.h
index d878e7a9c2..5b2e3b0ef1 100644
--- a/src/soc/intel/broadwell/include/soc/romstage.h
+++ b/src/soc/intel/broadwell/include/soc/romstage.h
@@ -3,7 +3,7 @@
 #ifndef _BROADWELL_ROMSTAGE_H_
 #define _BROADWELL_ROMSTAGE_H_
 
-void mainboard_post_raminit(const int s3resume);
+void mainboard_post_raminit(const bool s3resume);
 
 struct chipset_power_state;
 struct chipset_power_state *fill_power_state(void);
diff --git a/src/soc/intel/broadwell/raminit.c b/src/soc/intel/broadwell/raminit.c
index cacf8ecc89..9dc7973ec1 100644
--- a/src/soc/intel/broadwell/raminit.c
+++ b/src/soc/intel/broadwell/raminit.c
@@ -191,7 +191,7 @@ static int make_channel_disabled_mask(const struct spd_info *spdi, int ch)
 
 void perform_raminit(const struct chipset_power_state *const power_state)
 {
-	const int s3resume = power_state->prev_sleep_state == ACPI_S3;
+	const bool s3resume = power_state->prev_sleep_state == ACPI_S3;
 
 	struct pei_data pei_data = { 0 };
 
@@ -232,7 +232,7 @@ void perform_raminit(const struct chipset_power_state *const power_state)
 
 	timestamp_add_now(TS_INITRAM_END);
 
-	int cbmem_was_initted = !cbmem_recovery(s3resume);
+	bool cbmem_was_initted = !cbmem_recovery(s3resume);
 	if (s3resume && !cbmem_was_initted) {
 		/* Failed S3 resume, reset to come up cleanly */
 		printk(BIOS_CRIT, "Failed to recover CBMEM in S3 resume.\n");
diff --git a/src/soc/intel/broadwell/romstage.c b/src/soc/intel/broadwell/romstage.c
index 5c172ed2eb..4e2cb6a403 100644
--- a/src/soc/intel/broadwell/romstage.c
+++ b/src/soc/intel/broadwell/romstage.c
@@ -12,7 +12,7 @@
 #include <southbridge/intel/lynxpoint/lp_gpio.h>
 #include <stdint.h>
 
-__weak void mainboard_post_raminit(const int s3resume)
+__weak void mainboard_post_raminit(const bool s3resume)
 {
 }
 
diff --git a/src/southbridge/intel/lynxpoint/early_pch_native.c b/src/southbridge/intel/lynxpoint/early_pch_native.c
index d866182e61..452c8a5c0e 100644
--- a/src/southbridge/intel/lynxpoint/early_pch_native.c
+++ b/src/southbridge/intel/lynxpoint/early_pch_native.c
@@ -83,7 +83,7 @@ static void early_sata_init(const uint8_t pch_revision)
 	pci_or_config8(PCH_SATA_DEV, SATA_PCS, sata_pcs);
 }
 
-void early_pch_init_native(int s3resume)
+void early_pch_init_native(bool s3resume)
 {
 	const uint8_t pch_revision = pci_read_config8(PCH_LPC_DEV, PCI_REVISION_ID);
 
diff --git a/src/southbridge/intel/lynxpoint/pch.h b/src/southbridge/intel/lynxpoint/pch.h
index 3abca6ec9d..a5601ff929 100644
--- a/src/southbridge/intel/lynxpoint/pch.h
+++ b/src/southbridge/intel/lynxpoint/pch.h
@@ -116,7 +116,7 @@ void pch_dmi_setup_physical_layer(void);
 void pch_dmi_tc_vc_mapping(u32 vc0, u32 vc1, u32 vcp, u32 vcm);
 void early_usb_init(void);
 void early_thermal_init(void);
-void early_pch_init_native(int s3resume);
+void early_pch_init_native(bool s3resume);
 
 void usb_ehci_sleep_prepare(pci_devfn_t dev, u8 slp_typ);
 void usb_ehci_disable(pci_devfn_t dev);

From 1699d455e70d5662cb10a67f1a6ae5052174f0b0 Mon Sep 17 00:00:00 2001
From: Alok Agarwal <alok.agarwal@intel.com>
Date: Tue, 7 Oct 2025 13:52:50 +0530
Subject: [PATCH 2322/3886] vc/intel/fsp: Update PTL FSP headers to FSP 3373_03

Update header files for FSP for Panther Lake platform to FSP 3373_03
from FSP 3272_04

Details:
- Update FspmUpd.h: Add below variable
  - WREQT
- Update FspsUpd.h: Add below variable
  - PchHdaMicPrivacyMode
- Update MemInfoHob.h:
  - Add variable PprTargetedStatus and definition of PPR_REQUEST_MAX.

BUG=b:449580146
TEST=Able to build google/fatcat with the partial header changes

Change-Id: I6842fa4642ca994cd10f96efb7d4bc044cccacd2
Signed-off-by: Alok Agarwal <alok.agarwal@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89442
Reviewed-by: <srinivas.kulkarni@intel.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Pranava Y N <pranavayn@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 .../intel/fsp/fsp2_0/pantherlake/FspmUpd.h    | 155 +++++++++---------
 .../intel/fsp/fsp2_0/pantherlake/FspsUpd.h    |  12 +-
 .../intel/fsp/fsp2_0/pantherlake/MemInfoHob.h |   5 +-
 3 files changed, 92 insertions(+), 80 deletions(-)

diff --git a/src/vendorcode/intel/fsp/fsp2_0/pantherlake/FspmUpd.h b/src/vendorcode/intel/fsp/fsp2_0/pantherlake/FspmUpd.h
index 827eec302d..5c26bcd685 100644
--- a/src/vendorcode/intel/fsp/fsp2_0/pantherlake/FspmUpd.h
+++ b/src/vendorcode/intel/fsp/fsp2_0/pantherlake/FspmUpd.h
@@ -57,8 +57,7 @@ typedef struct {
 
 /** Offset 0x0060 - Serial Io Uart Debug Mode
   Select SerialIo Uart Controller mode
-  0:SerialIoUartDisabled, 1:SerialIoUartPci, 2:SerialIoUartHidden, 3:SerialIoUartCom,
-  4:SerialIoUartSkipInit
+  1:SerialIoUartPci, 4:SerialIoUartSkipInit
 **/
   UINT8                       SerialIoUartDebugMode;
 
@@ -941,8 +940,8 @@ typedef struct {
 **/
   UINT8                       DIMMRONT;
 
-/** Offset 0x0260 - Write Drive Strength/Equalization 2D
-  Enables/Disable Write Drive Strength/Equalization 2D
+/** Offset 0x0260 - Write Drive Strength Training
+  Enables/Disable Write Drive Strength Training
   $EN_DIS
 **/
   UINT8                       WRDSEQT;
@@ -1241,9 +1240,11 @@ typedef struct {
 **/
   UINT8                       ChHashInterleaveBit;
 
-/** Offset 0x02BB - Reserved
+/** Offset 0x02BB - Write Equalization Training
+  Enables/Disables Write Equalization Training
+  $EN_DIS
 **/
-  UINT8                       Reserved25;
+  UINT8                       WREQT;
 
 /** Offset 0x02BC - Ch Hash Mask
   Set the BIT(s) to be included in the XOR function. NOTE BIT mask corresponds to
@@ -1253,7 +1254,7 @@ typedef struct {
 
 /** Offset 0x02BE - Reserved
 **/
-  UINT8                       Reserved26;
+  UINT8                       Reserved25;
 
 /** Offset 0x02BF - Throttler CKEMin Timer
   Timer value for CKEMin, range[255;0]. Req'd min of SC_ROUND_T + BYTE_LENGTH (4).
@@ -1332,7 +1333,7 @@ typedef struct {
 
 /** Offset 0x02CB - Reserved
 **/
-  UINT8                       Reserved27[5];
+  UINT8                       Reserved26[5];
 
 /** Offset 0x02D0 - DDR Phy Safe Mode Support
   DdrSafeMode[0]: Basic PM Features, DdrSafeMode[1]: Spine Gating, DdrSafeMode[2]:
@@ -1354,7 +1355,7 @@ typedef struct {
 
 /** Offset 0x02D6 - Reserved
 **/
-  UINT8                       Reserved28[8];
+  UINT8                       Reserved27[8];
 
 /** Offset 0x02DE - RMTLoopCount
   Specifies the Loop Count to be used during Rank Margin Tool Testing. 0 - AUTO
@@ -1390,7 +1391,7 @@ typedef struct {
 
 /** Offset 0x02E7 - Reserved
 **/
-  UINT8                       Reserved29;
+  UINT8                       Reserved28;
 
 /** Offset 0x02E8 - Margin limit check L2
   Margin limit check L2 threshold: <b>100=Default</b>
@@ -1405,7 +1406,7 @@ typedef struct {
 
 /** Offset 0x02EB - Reserved
 **/
-  UINT8                       Reserved30;
+  UINT8                       Reserved29;
 
 /** Offset 0x02EC - LP5 Command Pins Mapping
   BitMask where bits [3:0] are Controller 0 Channel [3:0] and bits [7:4] are Controller
@@ -1427,7 +1428,7 @@ typedef struct {
 
 /** Offset 0x02EF - Reserved
 **/
-  UINT8                       Reserved31[43];
+  UINT8                       Reserved30[43];
 
 /** Offset 0x031A - Read Vref Decap Training*
   Enable/Disable Read Timing Centering Training with SR stress*
@@ -1455,7 +1456,7 @@ typedef struct {
 
 /** Offset 0x031E - Reserved
 **/
-  UINT8                       Reserved32[17];
+  UINT8                       Reserved31[17];
 
 /** Offset 0x032F - Board Type
   MrcBoardType, Options are 0=Mobile/Mobile Halo, 1=Desktop/DT Halo, 5=ULT/ULX/Mobile
@@ -1479,7 +1480,7 @@ typedef struct {
 
 /** Offset 0x0341 - Reserved
 **/
-  UINT8                       Reserved33;
+  UINT8                       Reserved32;
 
 /** Offset 0x0342 - Skip external display device scanning
   Enable: Do not scan for external display device, Disable (Default): Scan external
@@ -1607,7 +1608,7 @@ typedef struct {
 
 /** Offset 0x04D6 - Reserved
 **/
-  UINT8                       Reserved34[2];
+  UINT8                       Reserved33[2];
 
 /** Offset 0x04D8 - DMIC<N> ClkA Pin Muxing (N - DMIC number)
   Determines DMIC<N> ClkA Pin muxing. See  GPIO_*_MUXING_DMIC<N>_CLKA_*
@@ -1622,7 +1623,7 @@ typedef struct {
 
 /** Offset 0x04E1 - Reserved
 **/
-  UINT8                       Reserved35[3];
+  UINT8                       Reserved34[3];
 
 /** Offset 0x04E4 - DMIC<N> Data Pin Muxing
   Determines DMIC<N> Data Pin muxing. See GPIO_*_MUXING_DMIC<N>_DATA_*
@@ -1636,7 +1637,7 @@ typedef struct {
 
 /** Offset 0x04F3 - Reserved
 **/
-  UINT8                       Reserved36[117];
+  UINT8                       Reserved35[117];
 
 /** Offset 0x0568 - Enable HD Audio SoundWire#N Link
   Enable/disable HD Audio SNDW#N link. Muxed with HDA.
@@ -1657,7 +1658,7 @@ typedef struct {
 
 /** Offset 0x056F - Reserved
 **/
-  UINT8                       Reserved37[45];
+  UINT8                       Reserved36[45];
 
 /** Offset 0x059C - iDisplay Audio Codec disconnection
   0: Not disconnected, enumerable, 1: Disconnected SDI, not enumerable.
@@ -1667,7 +1668,7 @@ typedef struct {
 
 /** Offset 0x059D - Reserved
 **/
-  UINT8                       Reserved38[5];
+  UINT8                       Reserved37[5];
 
 /** Offset 0x05A2 - HDA Power/Clock Gating (PGD/CGD)
   Enable/Disable HD Audio Power and Clock Gating(POR: Enable). 0: PLATFORM_POR, 1:
@@ -1678,7 +1679,7 @@ typedef struct {
 
 /** Offset 0x05A3 - Reserved
 **/
-  UINT8                       Reserved39;
+  UINT8                       Reserved38;
 
 /** Offset 0x05A4 - Audio Sub System IDs
   Set default Audio Sub System IDs. If its set to 0 then value from Strap is used.
@@ -1687,7 +1688,7 @@ typedef struct {
 
 /** Offset 0x05A8 - Reserved
 **/
-  UINT8                       Reserved40;
+  UINT8                       Reserved39;
 
 /** Offset 0x05A9 - PCH LPC Enhance the port 8xh decoding
   Original LPC only decodes one byte of port 80h.
@@ -1707,7 +1708,7 @@ typedef struct {
 
 /** Offset 0x05CE - Reserved
 **/
-  UINT8                       Reserved41[46];
+  UINT8                       Reserved40[46];
 
 /** Offset 0x05FC - Enable PCIE RP Mask
   Enable/disable PCIE Root Ports. 0: disable, 1: enable. One bit for each port, bit0
@@ -1723,7 +1724,7 @@ typedef struct {
 
 /** Offset 0x0601 - Reserved
 **/
-  UINT8                       Reserved42[3];
+  UINT8                       Reserved41[3];
 
 /** Offset 0x0604 - Serial Io Uart Debug Mmio Base
   Select SerialIo Uart default MMIO resource in SEC/PEI phase when PcdLpssUartMode
@@ -1800,7 +1801,7 @@ typedef struct {
 
 /** Offset 0x061A - Reserved
 **/
-  UINT8                       Reserved43[2];
+  UINT8                       Reserved42[2];
 
 /** Offset 0x061C - HECI Timeouts
   0: Disable, 1: Enable (Default) timeout check for HECI
@@ -1853,7 +1854,7 @@ typedef struct {
 
 /** Offset 0x0624 - Reserved
 **/
-  UINT8                       Reserved44[2];
+  UINT8                       Reserved43[2];
 
 /** Offset 0x0626 - ISA Serial Base selection
   Select ISA Serial Base address. Default is 0x3F8.
@@ -1874,7 +1875,7 @@ typedef struct {
 
 /** Offset 0x062A - Reserved
 **/
-  UINT8                       Reserved45[26];
+  UINT8                       Reserved44[26];
 
 /** Offset 0x0644 - Enable SMBus
   Enable/disable SMBus controller.
@@ -1895,7 +1896,7 @@ typedef struct {
 
 /** Offset 0x0647 - Reserved
 **/
-  UINT8                       Reserved46;
+  UINT8                       Reserved45;
 
 /** Offset 0x0648 - SMBUS Base Address
   SMBUS Base Address (IO space).
@@ -1910,7 +1911,7 @@ typedef struct {
 
 /** Offset 0x064B - Reserved
 **/
-  UINT8                       Reserved47[13];
+  UINT8                       Reserved46[13];
 
 /** Offset 0x0658 - Smbus dynamic power gating
   Disable or Enable Smbus dynamic power gating.
@@ -1933,7 +1934,7 @@ typedef struct {
 
 /** Offset 0x065B - Reserved
 **/
-  UINT8                       Reserved48[18];
+  UINT8                       Reserved47[18];
 
 /** Offset 0x066D - Over clocking support
   Over clocking support; <b>0: Disable</b>; 1: Enable
@@ -1943,7 +1944,7 @@ typedef struct {
 
 /** Offset 0x066E - Reserved
 **/
-  UINT8                       Reserved49;
+  UINT8                       Reserved48;
 
 /** Offset 0x066F - Realtime Memory Timing
   0(Default): Disabled, 1: Enabled. When enabled, it will allow the system to perform
@@ -2006,7 +2007,7 @@ typedef struct {
 
 /** Offset 0x067B - Reserved
 **/
-  UINT8                       Reserved50[2];
+  UINT8                       Reserved49[2];
 
 /** Offset 0x067D - TjMax Offset
   TjMax offset.Specified value here is clipped by pCode (125 - TjMax Offset) to support
@@ -2016,7 +2017,7 @@ typedef struct {
 
 /** Offset 0x067E - Reserved
 **/
-  UINT8                      Reserved51[48];
+  UINT8                      Reserved50[48];
 
 /** Offset 0x06AE - Core VF Point Offset
   Array used to specifies the Core Voltage Offset applied to the each selected VF
@@ -2038,7 +2039,7 @@ typedef struct {
 
 /** Offset 0x06EA - Reserved
 **/
-  UINT8                       Reserved52[26];
+  UINT8                       Reserved51[26];
 
 /** Offset 0x0704 - Per Core Max Ratio override
   Enable or disable Per Core PState OC supported by writing OCMB 0x1D to program new
@@ -2049,7 +2050,7 @@ typedef struct {
 
 /** Offset 0x0705 - Reserved
 **/
-  UINT8                       Reserved53[25];
+  UINT8                       Reserved52[25];
 
 /** Offset 0x071E - Per Core Current Max Ratio
   Array for the Per Core Max Ratio
@@ -2058,7 +2059,7 @@ typedef struct {
 
 /** Offset 0x0726 - Reserved
 **/
-  UINT8                       Reserved54[8];
+  UINT8                       Reserved53[8];
 
 /** Offset 0x072E - Pvd Ratio Threshold for SOC/CPU die
   Array of Pvd Ratio Threshold for SOC/CPU die is the threshold value for input ratio
@@ -2071,7 +2072,7 @@ typedef struct {
 
 /** Offset 0x072F - Reserved
 **/
-  UINT8                       Reserved55[65];
+  UINT8                       Reserved54[65];
 
 /** Offset 0x0770 - CPU BCLK OC Frequency
   CPU BCLK OC Frequency in KHz units. 98000000Hz = 98MHz <b>0 - Auto</b>. Range is
@@ -2081,7 +2082,7 @@ typedef struct {
 
 /** Offset 0x0774 - Reserved
 **/
-  UINT8                      Reserved56[13];
+  UINT8                      Reserved55[13];
 
 /** Offset 0x0781 - Avx2 Voltage Guardband Scaling Factor
   AVX2 Voltage Guardband Scale factor applied to AVX2 workloads. Range is 0-200 in
@@ -2096,7 +2097,7 @@ typedef struct {
 
 /** Offset 0x0783 - Reserved
 **/
-  UINT8                       Reserved57[5];
+  UINT8                       Reserved56[5];
 
 /** Offset 0x0788 - Enable PCH ISH Controller
   0: Disable, 1: Enable (Default) ISH Controller
@@ -2106,7 +2107,7 @@ typedef struct {
 
 /** Offset 0x0789 - Reserved
 **/
-  UINT8                       Reserved58;
+  UINT8                       Reserved57;
 
 /** Offset 0x078A - BiosSize
   The size of the BIOS region of the IFWI. Used if FspmUpd->FspmConfig.BiosGuard !=
@@ -2141,7 +2142,7 @@ typedef struct {
 
 /** Offset 0x0790 - Reserved
 **/
-  UINT8                       Reserved59[3];
+  UINT8                       Reserved58[3];
 
 /** Offset 0x0793 - MKTME Key-Id Bits Override Enable
   Configure Trust Domain Extension (TDX) to isolate VMs from Virtual-Machine Manager
@@ -2152,7 +2153,7 @@ typedef struct {
 
 /** Offset 0x0794 - Reserved
 **/
-  UINT8                       Reserved60[4];
+  UINT8                       Reserved59[4];
 
 /** Offset 0x0798 - TME Exclude Base Address
   TME Exclude Base Address.
@@ -2166,7 +2167,7 @@ typedef struct {
 
 /** Offset 0x07A8 - Reserved
 **/
-  UINT8                      Reserved61[14];
+  UINT8                      Reserved60[14];
 
 /** Offset 0x07B6 - BIST on Reset
   Enable/Disable BIST (Built-In Self Test) on reset. <b>0: Disable</b>; 1: Enable.
@@ -2176,7 +2177,7 @@ typedef struct {
 
 /** Offset 0x07B7 - Reserved
 **/
-  UINT8                       Reserved62;
+  UINT8                       Reserved61;
 
 /** Offset 0x07B8 - Enable or Disable VMX
   Enable or Disable VMX, When enabled, a VMM can utilize the additional hardware capabilities
@@ -2246,7 +2247,7 @@ typedef struct {
 
 /** Offset 0x07C2 - Reserved
 **/
-  UINT8                       Reserved63[6];
+  UINT8                       Reserved62[6];
 
 /** Offset 0x07C8 - PrmrrSize
   Enable/Disable. 0: Disable, define default value of PrmrrSize , 1: enable
@@ -2274,7 +2275,7 @@ typedef struct {
 
 /** Offset 0x07D2 - Reserved
 **/
-  UINT8                       Reserved64[98];
+  UINT8                       Reserved63[98];
 
 /** Offset 0x0834 - SinitMemorySize
   Enable/Disable. 0: Disable, define default value of SinitMemorySize , 1: enable
@@ -2341,7 +2342,7 @@ typedef struct {
 
 /** Offset 0x086E - Reserved
 **/
-  UINT8                       Reserved65[2];
+  UINT8                       Reserved64[2];
 
 /** Offset 0x0870 - Platform Power Pmax
   PSYS PMax power, defined in 1/8 Watt increments. <b>0 - Auto</b> Specified in 1/8
@@ -2393,7 +2394,7 @@ typedef struct {
 
 /** Offset 0x08BA - Reserved
 **/
-  UINT8                       Reserved66[26];
+  UINT8                       Reserved65[26];
 
 /** Offset 0x08D4 - Icc Max limit
   Voltage Regulator Current Limit (Icc Max). This value represents the Maximum instantaneous
@@ -2405,7 +2406,7 @@ typedef struct {
 
 /** Offset 0x08E0 - Reserved
 **/
-  UINT8                      Reserved67[42];
+  UINT8                      Reserved66[42];
 
 /** Offset 0x090A - Thermal Design Current enable/disable
   Thermal Design Current enable/disable; <b>0: Disable</b>; 1: Enable. [0] for IA,
@@ -2415,7 +2416,7 @@ typedef struct {
 
 /** Offset 0x0910 - Reserved
 **/
-  UINT8                       Reserved68[6];
+  UINT8                       Reserved67[6];
 
 /** Offset 0x0916 - Disable Fast Slew Rate for Deep Package C States for VR domains
   This option needs to be configured to reduce acoustic noise during deeper C states.
@@ -2437,7 +2438,7 @@ typedef struct {
 
 /** Offset 0x0922 - Reserved
 **/
-  UINT8                       Reserved69[6];
+  UINT8                       Reserved68[6];
 
 /** Offset 0x0928 - Thermal Design Current time window
   Auto = 0 is default. Range is from 1ms to 448s. <b>0: Auto</b>. [0] for IA, [1]
@@ -2453,7 +2454,7 @@ typedef struct {
 
 /** Offset 0x0946 - Reserved
 **/
-  UINT8                       Reserved70[2];
+  UINT8                       Reserved69[2];
 
 /** Offset 0x0948 - DLVR RFI Enable
   Enable/Disable DLVR RFI frequency hopping. 0: Disable; <b>1: Enable</b>.
@@ -2462,18 +2463,18 @@ typedef struct {
   UINT8                       DlvrRfiEnable;
 
 /** Offset 0x0949 - Pcore VR Hysteresis time window
-  0 is default. Range of PcoreHysteresisWindow from 1ms to 50ms.
+  Enable/Disable DLVR RFI frequency hopping. 0: Disable; <b>1: Enable</b>.
 **/
   UINT8                       PcoreHysteresisWindow;
 
 /** Offset 0x094A - Ecore VR Hysteresis time window
-  0 is default. Range of EcoreHysteresisWindow from 1ms to 50ms.
+  Enable/Disable DLVR RFI frequency hopping. 0: Disable; <b>1: Enable</b>.
 **/
   UINT8                       EcoreHysteresisWindow;
 
 /** Offset 0x094B - Reserved
 **/
-  UINT8                       Reserved71[11];
+  UINT8                       Reserved70[11];
 
 /** Offset 0x0956 - VR Fast Vmode ICC Limit support
   Voltage Regulator Fast Vmode ICC Limit. A value of 400 = 100A. A value of 0 corresponds
@@ -2498,7 +2499,7 @@ typedef struct {
 
 /** Offset 0x096E - Reserved
 **/
-  UINT8                       Reserved72[28];
+  UINT8                       Reserved71[28];
 
 /** Offset 0x098A - PCH Port80 Route
   Control where the Port 80h cycles are sent, 0: LPC; 1: PCI.
@@ -2515,7 +2516,7 @@ typedef struct {
 
 /** Offset 0x098C - Reserved
 **/
-  UINT8                       Reserved73[4];
+  UINT8                       Reserved72[4];
 
 /** Offset 0x0990 - PMR Size
   Size of PMR memory buffer. 0x400000 for normal boot and 0x200000 for S3 boot
@@ -2541,7 +2542,7 @@ typedef struct {
 
 /** Offset 0x0997 - Reserved
 **/
-  UINT8                       Reserved74;
+  UINT8                       Reserved73;
 
 /** Offset 0x0998 - Base addresses for VT-d function MMIO access
   Base addresses for VT-d MMIO access per VT-d engine
@@ -2550,7 +2551,7 @@ typedef struct {
 
 /** Offset 0x09BC - Reserved
 **/
-  UINT8                       Reserved75[20];
+  UINT8                       Reserved74[20];
 
 /** Offset 0x09D0 - MMIO Size
   Size of MMIO space reserved for devices. 0(Default)=Auto, non-Zero=size in MB
@@ -2565,7 +2566,7 @@ typedef struct {
 
 /** Offset 0x09D4 - Reserved
 **/
-  UINT8                      Reserved76[36];
+  UINT8                      Reserved75[36];
 
 /** Offset 0x09F8 - Enable above 4GB MMIO resource support
   Enable/disable above 4GB MMIO resource support
@@ -2581,7 +2582,7 @@ typedef struct {
 
 /** Offset 0x09FA - Reserved
 **/
-  UINT8                       Reserved77[10];
+  UINT8                       Reserved76[10];
 
 /** Offset 0x0A04 - Enable/Disable CrashLog Device
   Enable or Disable CrashLog/Telemetry Device  0- Disable, <b>1- Enable</b>
@@ -2591,7 +2592,7 @@ typedef struct {
 
 /** Offset 0x0A08 - Reserved
 **/
-  UINT8                      Reserved78[20];
+  UINT8                      Reserved77[20];
 
 /** Offset 0x0A1C - Platform Debug Option
   Enabled Trace active: TraceHub is enabled and trace is active, blocks s0ix.\n
@@ -2608,7 +2609,7 @@ typedef struct {
 
 /** Offset 0x0A1D - Reserved
 **/
-  UINT8                       Reserved79[14];
+  UINT8                       Reserved78[14];
 
 /** Offset 0x0A2B - Program GPIOs for LFP on DDI port-A device
   0=Disabled,1(Default)=eDP, 2=MIPI DSI
@@ -2618,7 +2619,7 @@ typedef struct {
 
 /** Offset 0x0A2C - Reserved
 **/
-  UINT8                      Reserved80[2];
+  UINT8                      Reserved79[2];
 
 /** Offset 0x0A2E - Program GPIOs for LFP on DDI port-B device
   0(Default)=Disabled,1=eDP, 2=MIPI DSI
@@ -2712,7 +2713,7 @@ typedef struct {
 
 /** Offset 0x0A3D - Reserved
 **/
-  UINT8                       Reserved81[3];
+  UINT8                       Reserved80[3];
 
 /** Offset 0x0A40 - Temporary MMIO address for GMADR
   The reference code will use this as Temporary MMIO address space to access GMADR
@@ -2731,7 +2732,7 @@ typedef struct {
 
 /** Offset 0x0A50 - Reserved
 **/
-  UINT8                      Reserved82[2];
+  UINT8                      Reserved81[2];
 
 /** Offset 0x0A52 - Enable/Disable Memory Bandwidth Compression
   0=Disable, 1(Default)=Enable
@@ -2761,7 +2762,7 @@ typedef struct {
 
 /** Offset 0x0A56 - Reserved
 **/
-  UINT8                       Reserved83[2];
+  UINT8                       Reserved82[2];
 
 /** Offset 0x0A58 - Intel Graphics VBT (Video BIOS Table) Size
   Size of Internal Graphics VBT Image
@@ -2770,7 +2771,7 @@ typedef struct {
 
 /** Offset 0x0A5C - Reserved
 **/
-  UINT8                       Reserved84[4];
+  UINT8                       Reserved83[4];
 
 /** Offset 0x0A60 - Graphics Configuration Ptr
   Points to VBT
@@ -2831,7 +2832,7 @@ typedef struct {
 
 /** Offset 0x0A83 - Reserved
 **/
-  UINT8                       Reserved85[4];
+  UINT8                       Reserved84[4];
 
 /** Offset 0x0A87 - TCSS Type C Port 0
   Set TCSS Type C Port 0 Type, Options are 0=DISABLE, 1=DP_ONLY, 2=NO_TBT, 3=NO_PCIE,
@@ -2863,7 +2864,7 @@ typedef struct {
 
 /** Offset 0x0A8B - Reserved
 **/
-  UINT8                       Reserved86;
+  UINT8                       Reserved85;
 
 /** Offset 0x0A8C - TypeC port GPIO setting
   GPIO Pin number for Type C Aux orientation setting, use the GpioPad that is defined
@@ -2931,7 +2932,7 @@ typedef struct {
 
 /** Offset 0x0AC9 - Reserved
 **/
-  UINT8                       Reserved87;
+  UINT8                       Reserved86;
 
 /** Offset 0x0ACA - DLL Weak Lock Support
   Enables/Disable DLL Weak Lock Support
@@ -2941,7 +2942,7 @@ typedef struct {
 
 /** Offset 0x0ACB - Reserved
 **/
-  UINT8                       Reserved88;
+  UINT8                       Reserved87;
 
 /** Offset 0x0ACC - Rx DQS Delay Comp Support
   Enables/Disable Rx DQS Delay Comp Support
@@ -2951,7 +2952,7 @@ typedef struct {
 
 /** Offset 0x0ACD - Reserved
 **/
-  UINT8                       Reserved89[2];
+  UINT8                       Reserved88[2];
 
 /** Offset 0x0ACF - Mrc Failure On Unsupported Dimm
   Enables/Disable Mrc Failure On Unsupported Dimm
@@ -2961,7 +2962,7 @@ typedef struct {
 
 /** Offset 0x0AD0 - Reserved
 **/
-  UINT8                      Reserved90[4];
+  UINT8                      Reserved89[4];
 
 /** Offset 0x0AD4 - DynamicMemoryBoost
   Enable/Disable Dynamic Memory Boost Feature. Only valid if SpdProfileSelected is
@@ -2979,7 +2980,7 @@ typedef struct {
 
 /** Offset 0x0ADC - Reserved
 **/
-  UINT8                      Reserved91[9];
+  UINT8                      Reserved90[9];
 
 /** Offset 0x0AE5 - Vref Offset
   Offset to be applied to DDRDATACH0_CR_DDRCRDATAOFFSETTRAIN.VrefOffset
@@ -2990,7 +2991,7 @@ typedef struct {
 
 /** Offset 0x0AE6 - Reserved
 **/
-  UINT8                       Reserved92[2];
+  UINT8                       Reserved91[2];
 
 /** Offset 0x0AE8 - tRRSG Delta
   Delay between Read-to-Read commands in the same Bank Group. 0 - Auto. Signed TAT
@@ -3106,7 +3107,7 @@ typedef struct {
 
 /** Offset 0x0AF8 - Reserved
 **/
-  UINT8                       Reserved93[41];
+  UINT8                       Reserved92[41];
 
 /** Offset 0x0B21 - Channel to CKD QCK Mapping
   Specify Channel to CKD QCK Mapping for CH0D0/CH0D1/CH1D0&CH1D1
@@ -3120,7 +3121,7 @@ typedef struct {
 
 /** Offset 0x0B31 - Reserved
 **/
-  UINT8                       Reserved94[55];
+  UINT8                       Reserved93[55];
 } FSP_M_CONFIG;
 
 /** Fsp M UPD Configuration
diff --git a/src/vendorcode/intel/fsp/fsp2_0/pantherlake/FspsUpd.h b/src/vendorcode/intel/fsp/fsp2_0/pantherlake/FspsUpd.h
index 0b540c7e14..b5194418b1 100644
--- a/src/vendorcode/intel/fsp/fsp2_0/pantherlake/FspsUpd.h
+++ b/src/vendorcode/intel/fsp/fsp2_0/pantherlake/FspsUpd.h
@@ -2337,9 +2337,17 @@ typedef struct {
 **/
   UINT8                       PchHdaLinkFrequency;
 
-/** Offset 0x149B - Reserved
+/** Offset 0x149B - HD Audio Microphone Privacy Mode
+  HD Audio Microphone Privacy Mode: 0: No Microphone Privacy Support; 1: HW Managed
+  Microphone Privacy; 2: FW Managed Microphone Privacy; 3: Force Microphone Mute
+  0: No Microphone Privacy Support, 1: HW Managed Microphone Privacy, 2: FW Managed
+  Microphone Privacy, 3: Force Microphone Mute
 **/
-  UINT8                       Reserved59[2];
+  UINT8                       PchHdaMicPrivacyMode;
+
+/** Offset 0x149C - Reserved
+**/
+  UINT8                       Reserved59;
 
 /** Offset 0x149D - HD Audio Microphone Privacy applied for SoundWire Link number 0 in HW Mode
   HD Audio Microphone Privacy applied for SoundWire Link number 0 in HW Mode: 0: Disable, 1: Enable
diff --git a/src/vendorcode/intel/fsp/fsp2_0/pantherlake/MemInfoHob.h b/src/vendorcode/intel/fsp/fsp2_0/pantherlake/MemInfoHob.h
index 4171f4a1da..c89cf2cab1 100644
--- a/src/vendorcode/intel/fsp/fsp2_0/pantherlake/MemInfoHob.h
+++ b/src/vendorcode/intel/fsp/fsp2_0/pantherlake/MemInfoHob.h
@@ -15,7 +15,6 @@
 
 @par Specification Reference:
 **/
-
 #ifndef _MEM_INFO_HOB_H_
 #define _MEM_INFO_HOB_H_
 
@@ -36,6 +35,9 @@ extern EFI_GUID gSiMemoryPlatformDataGuid;
 #define _MAX_RANK_IN_CHANNEL       (4)       ///< The maximum number of ranks per channel.
 #define _MAX_SDRAM_IN_DIMM         (5)       ///< The maximum number of SDRAMs per DIMM.
 
+// Must match the corresponding definition in CMrcExtTypes.h
+#define PPR_REQUEST_MAX           (2)
+
 // Must match definitions in
 // Intel\OneSiliconPkg\IpBlock\MemoryInit\Mtl\Include\MrcInterface.h
 #define HOB_MAX_SAGV_POINTS 4
@@ -360,6 +362,7 @@ typedef struct {
   BOOLEAN           MixedEccDimms;                     ///< TRUE if both ECC and nonECC Dimms were detected in the system
   UINT8             MaxRankCapacity;                   ///< Maximum possible rank capacity in [GB]
   UINT16            PprFailingChannelBitMask;          ///< PPR failing channel mask
+  BOOLEAN           PprTargetedStatus[PPR_REQUEST_MAX]; ///< PPR status of each Targeted PPR request (0 = Targeted PPR was successful, 1 = PPR failed)
 } MEMORY_INFO_DATA_HOB;
 
 /**

From 84a348f4bff39cd4cf96c1f3c7a7cc6650093529 Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Thu, 23 Oct 2025 20:33:32 +0100
Subject: [PATCH 2323/3886] ec/starlabs/merlin: Remove the fast charge option

This is a legacy option that changed the charging frequency. It
is no longer needed as the "normal" frequency is faster and more
stable so remove it.

Change-Id: I73cf439d96d65f0be26595e42a4aedbc4388b850
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89694
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
---
 src/ec/starlabs/merlin/Kconfig                |  7 ------
 src/ec/starlabs/merlin/nuvoton.c              | 23 -------------------
 src/ec/starlabs/merlin/variants/glk/ecdefs.h  |  1 -
 src/ec/starlabs/merlin/variants/glkr/ecdefs.h |  1 -
 src/ec/starlabs/merlin/variants/kbl/ecdefs.h  |  1 -
 .../starlabs/merlin/variants/merlin/ecdefs.h  |  1 -
 src/mainboard/starlabs/lite/Kconfig           |  1 -
 src/mainboard/starlabs/lite/cfr.c             | 12 ----------
 8 files changed, 47 deletions(-)

diff --git a/src/ec/starlabs/merlin/Kconfig b/src/ec/starlabs/merlin/Kconfig
index d2f59a64fb..4758d44de1 100644
--- a/src/ec/starlabs/merlin/Kconfig
+++ b/src/ec/starlabs/merlin/Kconfig
@@ -43,13 +43,6 @@ config EC_STARLABS_FAN
 	help
 	  Select if the mainboard has a fan.
 
-config EC_STARLABS_FAST_CHARGE
-	bool
-	default n
-	depends on EC_STARLABS_NUVOTON
-	help
-	  Select if the mainboard supports fast charging.
-
 config EC_STARLABS_MAX_CHARGE
 	bool
 	default n
diff --git a/src/ec/starlabs/merlin/nuvoton.c b/src/ec/starlabs/merlin/nuvoton.c
index f62bcdf3ae..6b39fe0ebf 100644
--- a/src/ec/starlabs/merlin/nuvoton.c
+++ b/src/ec/starlabs/merlin/nuvoton.c
@@ -165,29 +165,6 @@ static void merlin_init(struct device *dev)
 						 UINT_MAX,
 						 UINT_MAX));
 
-	/*
-	 * Fast Charge
-	 *
-	 * Setting:	fast_charge
-	 *
-	 * Values:	Normal, Fast
-	 * Default:	Normal
-	 *
-	 */
-	const uint8_t fast_charge[] = {
-		CHARGE_RATE_NORMAL,
-		CHARGE_RATE_FAST
-	};
-
-	if (CONFIG(EC_STARLABS_FAST_CHARGE))
-		ec_write(ECRAM_FAST_CHARGE,
-			get_ec_value_from_option("fast_charge",
-						 0,
-						 fast_charge,
-						 ARRAY_SIZE(fast_charge),
-						 UINT_MAX,
-						 UINT_MAX));
-
 	/*
 	 * Fan Mode
 	 *
diff --git a/src/ec/starlabs/merlin/variants/glk/ecdefs.h b/src/ec/starlabs/merlin/variants/glk/ecdefs.h
index b9b4305f49..a9b3025148 100644
--- a/src/ec/starlabs/merlin/variants/glk/ecdefs.h
+++ b/src/ec/starlabs/merlin/variants/glk/ecdefs.h
@@ -19,7 +19,6 @@
 #define ECRAM_FN_CTRL_REVERSE	0x2d
 #define ECRAM_MAX_CHARGE	dead_code_t(uint8_t)
 #define ECRAM_FAN_MODE		dead_code_t(uint8_t)
-#define ECRAM_FAST_CHARGE	dead_code_t(uint8_t)
 #define ECRAM_CHARGING_SPEED	dead_code_t(uint8_t)
 #define ECRAM_LID_SWITCH	dead_code_t(uint8_t)
 #define ECRAM_POWER_LED		0x1f
diff --git a/src/ec/starlabs/merlin/variants/glkr/ecdefs.h b/src/ec/starlabs/merlin/variants/glkr/ecdefs.h
index 3e63bcba2e..028dd5f047 100644
--- a/src/ec/starlabs/merlin/variants/glkr/ecdefs.h
+++ b/src/ec/starlabs/merlin/variants/glkr/ecdefs.h
@@ -22,7 +22,6 @@
 #define ECRAM_FN_CTRL_REVERSE	0x13
 #define ECRAM_MAX_CHARGE	dead_code_t(uint8_t)
 #define ECRAM_FAN_MODE		dead_code_t(uint8_t)
-#define ECRAM_FAST_CHARGE       0x18
 #define ECRAM_CHARGING_SPEED	dead_code_t(uint8_t)
 #define ECRAM_LID_SWITCH	dead_code_t(uint8_t)
 #define ECRAM_POWER_LED		0x1f
diff --git a/src/ec/starlabs/merlin/variants/kbl/ecdefs.h b/src/ec/starlabs/merlin/variants/kbl/ecdefs.h
index 82384dd778..75b83c9bf5 100644
--- a/src/ec/starlabs/merlin/variants/kbl/ecdefs.h
+++ b/src/ec/starlabs/merlin/variants/kbl/ecdefs.h
@@ -19,7 +19,6 @@
 #define ECRAM_FAN_MODE		0x42
 #define ECRAM_FN_CTRL_REVERSE	0x43
 #define ECRAM_MAX_CHARGE	dead_code_t(uint8_t)
-#define ECRAM_FAST_CHARGE	dead_code_t(uint8_t)
 #define ECRAM_CHARGING_SPEED	dead_code_t(uint8_t)
 #define ECRAM_LID_SWITCH	dead_code_t(uint8_t)
 #define ECRAM_POWER_LED		0x1f
diff --git a/src/ec/starlabs/merlin/variants/merlin/ecdefs.h b/src/ec/starlabs/merlin/variants/merlin/ecdefs.h
index 17de22c6ae..b712baaf6a 100644
--- a/src/ec/starlabs/merlin/variants/merlin/ecdefs.h
+++ b/src/ec/starlabs/merlin/variants/merlin/ecdefs.h
@@ -19,7 +19,6 @@
 #define ECRAM_FN_CTRL_REVERSE	0x17
 #define ECRAM_MAX_CHARGE	0x1a
 #define ECRAM_FAN_MODE		0x1b
-#define ECRAM_FAST_CHARGE	dead_code_t(uint8_t)
 #define ECRAM_CHARGING_SPEED	0x1d
 #define ECRAM_LID_SWITCH	0x1e
 #define ECRAM_POWER_LED		0x1f
diff --git a/src/mainboard/starlabs/lite/Kconfig b/src/mainboard/starlabs/lite/Kconfig
index 2218b4e051..8ea2101f69 100644
--- a/src/mainboard/starlabs/lite/Kconfig
+++ b/src/mainboard/starlabs/lite/Kconfig
@@ -32,7 +32,6 @@ config BOARD_STARLABS_LITE_GLK
 
 config BOARD_STARLABS_LITE_GLKR
 	select BOARD_STARLABS_LITE_SERIES
-	select EC_STARLABS_FAST_CHARGE
 	select EC_STARLABS_NUVOTON
 	select EC_STARLABS_KBL_LEVELS
 	select SOC_INTEL_GEMINILAKE
diff --git a/src/mainboard/starlabs/lite/cfr.c b/src/mainboard/starlabs/lite/cfr.c
index 8423a04afa..4049531081 100644
--- a/src/mainboard/starlabs/lite/cfr.c
+++ b/src/mainboard/starlabs/lite/cfr.c
@@ -14,15 +14,6 @@ static const struct sm_object card_reader = SM_DECLARE_BOOL({
 	.default_value	= true,
 });
 
-#if CONFIG(EC_STARLABS_FAST_CHARGE)
-static const struct sm_object fast_charge = SM_DECLARE_BOOL({
-	.opt_name	= "fast_charge",
-	.ui_name	= "Fast Charge",
-	.ui_helptext	= "Charge the battery faster at the cost of heat and battery wear.",
-	.default_value	= false,
-});
-#endif
-
 static const struct sm_object power_profile = SM_DECLARE_ENUM({
 	.opt_name	= "power_profile",
 	.ui_name	= "Power Profile",
@@ -93,9 +84,6 @@ static struct sm_obj_form processor = {
 static struct sm_obj_form power = {
 	.ui_name = "Power",
 	.obj_list = (const struct sm_object *[]) {
-		#if CONFIG(EC_STARLABS_FAST_CHARGE)
-		&fast_charge,
-		#endif
 		&power_on_after_fail_bool,
 		NULL
 	},

From 1af54d9784bcd5aacbd81fce0ca1c62a8a74a871 Mon Sep 17 00:00:00 2001
From: Cliff Huang <cliff.huang@intel.com>
Date: Mon, 20 Oct 2025 10:56:37 -0700
Subject: [PATCH 2324/3886] drivers/intel/touch: Change I2C speed type to
 i2c_speed enum
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Change the I2C connection speed type from uint32_t to the i2c_speed
enum type for better type safety and code consistency. While the
i2c_speed enum values correspond to actual speed values in Hz, using the
enum provides clearer intent and prevents invalid speed values.
Additionally, add logic to use standard I2C speed (100 kHz) when no
recommended or required speed is specified in the device tree, SoC
configuration, or device settings.

BUG=none
TEST=Boot Fatcat board to OS and verify correct I2C speed assignments in
'DSPD' Name object under THC device from SSDT. Confirm touch devices
operate at expected speeds.

Signed-off-by: Cliff Huang <cliff.huang@intel.com>
Change-Id: Ie01693544bebf9f748d16606fc13f39fe4069b03
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89649
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Kyoung Il Kim <kyoung.il.kim@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Pranava Y N <pranavayn@google.com>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
---
 src/drivers/intel/touch/chip.h    |  4 ++--
 src/drivers/intel/touch/touch.c   | 11 ++++++++++-
 src/soc/intel/pantherlake/touch.c |  4 +---
 3 files changed, 13 insertions(+), 6 deletions(-)

diff --git a/src/drivers/intel/touch/chip.h b/src/drivers/intel/touch/chip.h
index 90bee4a814..9f3ad3f525 100644
--- a/src/drivers/intel/touch/chip.h
+++ b/src/drivers/intel/touch/chip.h
@@ -62,10 +62,10 @@ struct intel_thc_hidi2c_info {
 	/* Device connection speed in Hz */
 	enum i2c_speed connection_speed;
 	/*
-	 * This maps SoC specific function for converting speed in Hz to the actual
+	 * This maps SoC specific function for converting speed enum to the actual
 	 * value for the configuration register.
 	 */
-	uint64_t (*get_soc_i2c_bus_speed_val_func)(uint32_t speed);
+	uint64_t (*get_soc_i2c_bus_speed_val_func)(enum i2c_speed speed);
 	/* Device address mode */
 	uint64_t addr_mode;
 	/* Standard Mode (100 kbit/s) Serial Clock Line HIGH Period */
diff --git a/src/drivers/intel/touch/touch.c b/src/drivers/intel/touch/touch.c
index 7697ffb149..b070c47d7f 100644
--- a/src/drivers/intel/touch/touch.c
+++ b/src/drivers/intel/touch/touch.c
@@ -270,8 +270,17 @@ static void touch_generate_acpi_i2cdev_dsd(const struct device *dev)
 	acpigen_write_store_int_to_namestr(touch_get(dev, dev_hidi2c.intf.hidi2c.addr), "DADR");
 
 	if (_soc_hidi2c_info->get_soc_i2c_bus_speed_val_func) {
+		enum i2c_speed connection_speed;
+
+		connection_speed = touch_dev_soc_get(dev, hidi2c, connection_speed);
+		/*
+		 * If the recommended speed is not specified in the device tree, SoC, and device,
+		 * standard speed is used.
+		 */
+		if (!connection_speed)
+			connection_speed = I2C_SPEED_STANDARD;
 		connection_speed_val = _soc_hidi2c_info->get_soc_i2c_bus_speed_val_func(
-			touch_dev_soc_get(dev, hidi2c, connection_speed));
+			connection_speed);
 	} else {
 		die("Missing SoC function to map I2C speed to its register value!\n");
 	}
diff --git a/src/soc/intel/pantherlake/touch.c b/src/soc/intel/pantherlake/touch.c
index f09bd43187..1dab19cabb 100644
--- a/src/soc/intel/pantherlake/touch.c
+++ b/src/soc/intel/pantherlake/touch.c
@@ -4,7 +4,7 @@
 #include <soc/touch.h>
 
 /* Convert I2C speed into value for the register in SoC */
-static uint64_t get_soc_thc_i2c_bus_freq_val(uint32_t speed)
+static uint64_t get_soc_thc_i2c_bus_freq_val(enum i2c_speed speed)
 {
 	switch (speed) {
 	case I2C_SPEED_FAST_PLUS:
@@ -13,8 +13,6 @@ static uint64_t get_soc_thc_i2c_bus_freq_val(uint32_t speed)
 		return SOC_PTL_THC_I2C_CONNECTION_SPEED_FM;
 	case I2C_SPEED_STANDARD:
 		return SOC_PTL_THC_I2C_CONNECTION_SPEED_SM;
-	case 0: /* If not specified in the device tree, SoC, and device, standard speed is used */
-		return SOC_PTL_THC_I2C_CONNECTION_SPEED_SM;
 	default:
 		die("Fail to map %d Hz to proper I2C speed.\n", speed);
 	}

From cd4af952e7e453a26979a05627db55bfec20cff4 Mon Sep 17 00:00:00 2001
From: Varun Upadhyay <varun.upadhyay@intel.com>
Date: Fri, 10 Oct 2025 12:55:27 +0530
Subject: [PATCH 2325/3886] mb/google/ocelot/var/ocelot: Update DDR5 memory
 configs

This change updates memory configuration for DDR5 boards based
on board ID.
1. Set SaGv frequencies
2. Configure gear settings
3. Map Channel/PHY clock

TEST: Build ocelot image and boot board with DDR5 memory config.

Change-Id: Iffff1f1ac9b886f58304c002defbc008d3c6bbb8
Signed-off-by: Varun Upadhyay <varun.upadhyay@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89519
Reviewed-by: Usha P <usha.p@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 .../baseboard/include/baseboard/variants.h    |  2 ++
 .../google/ocelot/variants/ocelot/memory.c    |  7 ++--
 .../google/ocelot/variants/ocelot/variant.c   | 36 +++++++++++++++++++
 3 files changed, 43 insertions(+), 2 deletions(-)

diff --git a/src/mainboard/google/ocelot/variants/baseboard/include/baseboard/variants.h b/src/mainboard/google/ocelot/variants/baseboard/include/baseboard/variants.h
index d82877fe06..23ac848457 100644
--- a/src/mainboard/google/ocelot/variants/baseboard/include/baseboard/variants.h
+++ b/src/mainboard/google/ocelot/variants/baseboard/include/baseboard/variants.h
@@ -10,6 +10,8 @@
 #include <stdint.h>
 #include <vendorcode/google/chromeos/chromeos.h>
 
+#define BOARD_ID_MASK   0x3f
+
 /* The next set of functions return the gpio table and fill in the number of entries for
  * each table.
  */
diff --git a/src/mainboard/google/ocelot/variants/ocelot/memory.c b/src/mainboard/google/ocelot/variants/ocelot/memory.c
index 4f0a78a088..e15aa9fcb2 100644
--- a/src/mainboard/google/ocelot/variants/ocelot/memory.c
+++ b/src/mainboard/google/ocelot/variants/ocelot/memory.c
@@ -5,7 +5,6 @@
 #include <soc/meminit.h>
 #include <soc/romstage.h>
 
-#define BOARD_ID_MASK	0x3f
 #define SMBUS_ADDR_DIMM	0x50
 
 static const struct mb_cfg lp5_mem_config = {
@@ -56,6 +55,10 @@ static const struct mb_cfg ddr5_mem_config = {
 	.ddr_config = {
 		.dq_pins_interleaved = false,
 	},
+
+	.rcomp = {
+		.resistor = 100,
+	},
 };
 
 const struct mb_cfg *variant_memory_params(void)
@@ -78,7 +81,6 @@ const struct mb_cfg *variant_memory_params(void)
 void variant_get_spd_info(struct mem_spd *spd_info)
 {
 	uint32_t id = board_id() & BOARD_ID_MASK;
-	spd_info->cbfs_index = variant_memory_sku();
 
 	switch (id) {
 	case BOARD_ID_DDR5:
@@ -87,6 +89,7 @@ void variant_get_spd_info(struct mem_spd *spd_info)
 		spd_info->smbus[1].addr_dimm[0] = SMBUS_ADDR_DIMM;
 		break;
 	case BOARD_ID_LP5X:
+		spd_info->cbfs_index = variant_memory_sku();
 		spd_info->topo = MEM_TOPO_MEMORY_DOWN;
 		break;
 	default:
diff --git a/src/mainboard/google/ocelot/variants/ocelot/variant.c b/src/mainboard/google/ocelot/variants/ocelot/variant.c
index 5765b29c4a..92cce1450f 100644
--- a/src/mainboard/google/ocelot/variants/ocelot/variant.c
+++ b/src/mainboard/google/ocelot/variants/ocelot/variant.c
@@ -1,6 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
 #include <baseboard/variants.h>
+#include <boardid.h>
 #include <ec/google/chromeec/ec.h>
 #include <fsp/api.h>
 #include <fw_config.h>
@@ -56,6 +57,7 @@ void variant_update_soc_chip_config(struct soc_intel_pantherlake_config *config)
 void variant_update_soc_memory_init_params(FSPM_UPD *memupd)
 {
 	FSP_M_CONFIG *m_cfg = &memupd->FspmConfig;
+	uint32_t id = board_id() & BOARD_ID_MASK;
 
 	/* HDA Audio */
 	if (fw_config_probe(FW_CONFIG(AUDIO, AUDIO_ALC256_HDA))) {
@@ -63,6 +65,40 @@ void variant_update_soc_memory_init_params(FSPM_UPD *memupd)
 		m_cfg->PchHdaSdiEnable[0] = true;
 		m_cfg->PchHdaSdiEnable[1] = false;
 	}
+
+	if (id == BOARD_ID_DDR5) {
+		/* Override FSP-M SaGv frequency and gear for DDR5 boards */
+		m_cfg->SaGvFreq[0] = 3200;
+		m_cfg->SaGvGear[0] = GEAR_4;
+
+		m_cfg->SaGvFreq[1] = 4800;
+		m_cfg->SaGvGear[1] = GEAR_4;
+
+		m_cfg->SaGvFreq[2] = 5600;
+		m_cfg->SaGvGear[2] = GEAR_4;
+
+		m_cfg->SaGvFreq[3] = 6400;
+		m_cfg->SaGvGear[3] = GEAR_4;
+
+		/*
+		 * Override FSP-M ChannelToCkdQckMapping to map memory channels
+		 * to Clock Driver (CKD) and Query Clock (QCK) signals.
+		 */
+
+		const uint8_t channel_to_ckd_qck[] = { 1, 0, 0, 0,
+			0, 0, 0, 0 };
+		memcpy(m_cfg->ChannelToCkdQckMapping, channel_to_ckd_qck
+			, sizeof(channel_to_ckd_qck));
+
+		/*
+		 * Override FSP-M PhyClockToCkdDimm to map PHY clocks
+		 * to Clock Driver DIMM connections.
+		 */
+		const uint8_t phy_clock_to_ckd_dimm[] = { 4, 0, 4, 0,
+			0, 0, 0, 0 };
+		memcpy(m_cfg->PhyClockToCkdDimm, phy_clock_to_ckd_dimm,
+			sizeof(phy_clock_to_ckd_dimm));
+	}
 }
 
 bool variant_is_barrel_charger_present(void)

From 2279ba80e183822d93fb7bdf132afd3bddc5ac47 Mon Sep 17 00:00:00 2001
From: Dodoid <git-noreply@dodoid.com>
Date: Wed, 22 Oct 2025 00:11:37 -0400
Subject: [PATCH 2326/3886] .gitignore: Add .clangd as a "Development friendly
 file"

If using clangd for development, your .clangd file is almost
certainly specific to your environment, and should be gitignored,
same as e.g. .vscode/

Change-Id: I3388d14f381aa9f68be9806652514a741fad49c9
Signed-off-by: Dodoid <git-noreply@dodoid.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89680
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nicholas <nic.c3.14@gmail.com>
---
 .gitignore | 1 +
 1 file changed, 1 insertion(+)

diff --git a/.gitignore b/.gitignore
index e813493526..5a429b5e3c 100644
--- a/.gitignore
+++ b/.gitignore
@@ -35,6 +35,7 @@ tags
 .cache
 compile_commands.json
 .vscode/
+.clangd
 
 # Cross-compile toolkits
 xgcc/

From aab8ad98b66c1dacbf08a559b4e0349d297c4eac Mon Sep 17 00:00:00 2001
From: Ian Feng <ian_feng@compal.corp-partner.google.com>
Date: Wed, 22 Oct 2025 12:00:32 +0800
Subject: [PATCH 2327/3886] mb/google/ocelot: Create kodkod variant

Create the kodkod variant of the ocelot reference board by copying
the ocelot files to a new directory named for the variant.

BUG=b:451760650
TEST=util/abuild/abuild -p none -t google/ocelot -x -a
make sure the build includes GOOGLE_KODKOD

Change-Id: I8bbea4444d65e57b98bf9c8a621ff548abb8aece
Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89679
Reviewed-by: Pranava Y N <pranavayn@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/google/ocelot/Kconfig           |  20 +-
 src/mainboard/google/ocelot/Kconfig.name      |   3 +
 .../baseboard/ocelot/include/baseboard/gpio.h |   2 +
 .../google/ocelot/variants/kodkod/Makefile.mk |   6 +
 .../google/ocelot/variants/kodkod/gpio.c      | 393 ++++++++++++++++++
 .../google/ocelot/variants/kodkod/hda_verb.c  | 126 ++++++
 .../variants/kodkod/include/variant/ec.h      |   8 +
 .../variants/kodkod/include/variant/gpio.h    |  11 +
 .../google/ocelot/variants/kodkod/memory.c    |  31 ++
 .../ocelot/variants/kodkod/overridetree.cb    |   5 +
 10 files changed, 603 insertions(+), 2 deletions(-)
 create mode 100644 src/mainboard/google/ocelot/variants/kodkod/Makefile.mk
 create mode 100644 src/mainboard/google/ocelot/variants/kodkod/gpio.c
 create mode 100644 src/mainboard/google/ocelot/variants/kodkod/hda_verb.c
 create mode 100644 src/mainboard/google/ocelot/variants/kodkod/include/variant/ec.h
 create mode 100644 src/mainboard/google/ocelot/variants/kodkod/include/variant/gpio.h
 create mode 100644 src/mainboard/google/ocelot/variants/kodkod/memory.c
 create mode 100644 src/mainboard/google/ocelot/variants/kodkod/overridetree.cb

diff --git a/src/mainboard/google/ocelot/Kconfig b/src/mainboard/google/ocelot/Kconfig
index be6a8a6ace..f979addcbd 100644
--- a/src/mainboard/google/ocelot/Kconfig
+++ b/src/mainboard/google/ocelot/Kconfig
@@ -28,7 +28,7 @@ config BOARD_GOOGLE_OCELOT_COMMON
 	select GOOGLE_SMBIOS_MAINBOARD_VERSION
 	select HAVE_ACPI_RESUME
 	select HAVE_ACPI_TABLES
-	select HAVE_SPD_IN_CBFS
+	select HAVE_SPD_IN_CBFS if !BOARD_GOOGLE_MODEL_KODKOD
 	select I2C_TPM
 	select INTEL_LPSS_UART_FOR_CONSOLE
 	select MAINBOARD_DISABLE_STAGE_CACHE
@@ -50,13 +50,22 @@ config BOARD_GOOGLE_BASEBOARD_OCELOT
 	select DRIVERS_INTEL_USB4_RETIMER
 	select HAVE_SLP_S0_GATE
 	select MAINBOARD_HAS_CHROMEOS
-	select MEMORY_SOLDERDOWN
+	select MEMORY_SOLDERDOWN  if !BOARD_GOOGLE_MODEL_KODKOD
 	select SOC_INTEL_COMMON_BLOCK_HDA_VERB
 	select SOC_INTEL_IOE_DIE_SUPPORT
 	select SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES
 	select SYSTEM_TYPE_LAPTOP
 	select TPM_GOOGLE_TI50
 
+config BOARD_GOOGLE_MODEL_KODKOD
+	def_bool n
+	select BOARD_GOOGLE_BASEBOARD_OCELOT
+	select FSP_UGOP_EARLY_SIGN_OF_LIFE
+	select EC_GOOGLE_CHROMEEC_RTK
+	select EC_GOOGLE_CHROMEEC_LPC_GENERIC_MEMORY_RANGE
+	select SPD_CACHE_ENABLE
+	select SPD_CACHE_IN_FMAP
+
 config BOARD_GOOGLE_MODEL_MATSU
 	def_bool n
 	select BOARD_GOOGLE_BASEBOARD_OCELOT
@@ -81,6 +90,9 @@ config BOARD_GOOGLE_MODEL_OJAL
 	select EC_GOOGLE_CHROMEEC_RTK
 	select EC_GOOGLE_CHROMEEC_LPC_GENERIC_MEMORY_RANGE
 
+config BOARD_GOOGLE_KODKOD
+	select BOARD_GOOGLE_MODEL_KODKOD
+
 config BOARD_GOOGLE_MATSU
 	select BOARD_GOOGLE_MODEL_MATSU
 
@@ -140,6 +152,7 @@ config DRIVER_TPM_I2C_ADDR
 
 config DRIVER_TPM_I2C_BUS
 	hex
+	default 0x01 if BOARD_GOOGLE_MODEL_KODKOD
 	default 0x01 if BOARD_GOOGLE_MODEL_MATSU
 	default 0x01 if BOARD_GOOGLE_MODEL_OCELOT
 	default 0x01 if BOARD_GOOGLE_MODEL_OJAL
@@ -155,6 +168,7 @@ config MAINBOARD_FAMILY
 	default "Google_Ocelot"
 
 config MAINBOARD_PART_NUMBER
+	default "Kodkod" if BOARD_GOOGLE_MODEL_KODKOD
 	default "Matsu" if BOARD_GOOGLE_MODEL_MATSU
 	default "Ocelot" if BOARD_GOOGLE_MODEL_OCELOT
 	default "Ojal" if BOARD_GOOGLE_OJAL
@@ -166,6 +180,7 @@ config MEMORY_SOLDERDOWN
 
 config TPM_TIS_ACPI_INTERRUPT
 	int
+	default 49 if BOARD_GOOGLE_MODEL_KODKOD # GPE0_DW1_17 (GPP_B17)
 	default 78 if BOARD_GOOGLE_MODEL_MATSU # GPE0_DW2_14 (GPP_E14)
 	default 49 if BOARD_GOOGLE_MODEL_OCELOT # GPE0_DW1_17 (GPP_B17)
 	default 49 if BOARD_GOOGLE_MODEL_OJAL # GPE0_DW1_17 (GPP_B17)
@@ -179,6 +194,7 @@ config USE_PM_ACPI_TIMER
 
 config VARIANT_DIR
 	string
+	default "kodkod" if BOARD_GOOGLE_MODEL_KODKOD
 	default "matsu" if BOARD_GOOGLE_MODEL_MATSU
 	default "ocelot" if BOARD_GOOGLE_MODEL_OCELOT
 	default "ojal" if BOARD_GOOGLE_MODEL_OJAL
diff --git a/src/mainboard/google/ocelot/Kconfig.name b/src/mainboard/google/ocelot/Kconfig.name
index 6f6f45fb6e..e6713f98cb 100644
--- a/src/mainboard/google/ocelot/Kconfig.name
+++ b/src/mainboard/google/ocelot/Kconfig.name
@@ -2,6 +2,9 @@
 
 comment "Ocelot"
 
+config BOARD_GOOGLE_KODKOD
+	bool "-> Kodkod"
+
 config BOARD_GOOGLE_MATSU
 	bool "-> Matsu"
 
diff --git a/src/mainboard/google/ocelot/variants/baseboard/ocelot/include/baseboard/gpio.h b/src/mainboard/google/ocelot/variants/baseboard/ocelot/include/baseboard/gpio.h
index 48dbafc8d3..a0983a543a 100644
--- a/src/mainboard/google/ocelot/variants/baseboard/ocelot/include/baseboard/gpio.h
+++ b/src/mainboard/google/ocelot/variants/baseboard/ocelot/include/baseboard/gpio.h
@@ -15,6 +15,8 @@
 //TODO for Nuvo: #define EC_SYNC_IRQ	GPP_E07_IRQ
 #if CONFIG(BOARD_GOOGLE_MODEL_OCELOT) || CONFIG(BOARD_GOOGLE_MODEL_OJAL)
  #define EC_SYNC_IRQ	0 /* Not Connected */
+#elif CONFIG(BOARD_GOOGLE_MODEL_KODKOD)
+ #define EC_SYNC_IRQ	GPP_F10_IRQ
 #elif CONFIG(BOARD_GOOGLE_MODEL_MATSU)
  #define EC_SYNC_IRQ	GPP_E08_IRQ
 #endif
diff --git a/src/mainboard/google/ocelot/variants/kodkod/Makefile.mk b/src/mainboard/google/ocelot/variants/kodkod/Makefile.mk
new file mode 100644
index 0000000000..4c33dad4db
--- /dev/null
+++ b/src/mainboard/google/ocelot/variants/kodkod/Makefile.mk
@@ -0,0 +1,6 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
+bootblock-y += gpio.c
+romstage-y += gpio.c
+romstage-y += memory.c
+ramstage-y += gpio.c
diff --git a/src/mainboard/google/ocelot/variants/kodkod/gpio.c b/src/mainboard/google/ocelot/variants/kodkod/gpio.c
new file mode 100644
index 0000000000..8c9686ea2d
--- /dev/null
+++ b/src/mainboard/google/ocelot/variants/kodkod/gpio.c
@@ -0,0 +1,393 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <baseboard/gpio.h>
+#include <baseboard/variants.h>
+#include <boardid.h>
+#include <soc/gpio.h>
+
+/* Pad configuration in ramstage*/
+static const struct pad_config gpio_table[] = {
+	/* GPP_A */
+	/* GPP_A00:     ESPI_IO0_AIC */
+	/*  GPP_A00 : GPP_A00 ==> ESPI_IO0_EC_R configured on reset, do not touch */
+
+	/* GPP_A01:     ESPI_IO1_AIC */
+	/*  GPP_A01 : GPP_A01 ==> ESPI_IO1_EC_R configured on reset, do not touch */
+
+	/* GPP_A02:     ESPI_IO2_AIC */
+	/*  GPP_A02 : GPP_A02 ==> ESPI_IO2_EC_R configured on reset, do not touch */
+
+	/* GPP_A03:     ESPI_IO3_AIC */
+	/*  GPP_A03 : GPP_A03 ==> ESPI_IO3_EC_R configured on reset, do not touch */
+
+	/* GPP_A04:     ESPI_CS0_AIC_N */
+	/*  GPP_A04 : GPP_A04 ==> ESPI_CS0_HDR_L configured on reset, do not touch */
+
+	/* GPP_A05:     ESPI_CLK_AIC */
+	/*  GPP_A05 : GPP_A05 ==> ESPI_CLK_HDR configured on reset, do not touch */
+
+	/* GPP_A06:     ESPI_RST_AIC_N */
+	/*  GPP_A06 : GPP_A06 ==> ESPI_RST_HDR configured on reset, do not touch */
+
+	/* GPP_A08:     M2_GEN4_SSD_RESET_N */
+	PAD_CFG_GPO(GPP_A08, 1, PLTRST),
+	/* GPP_A09:     NC */
+	PAD_NC(GPP_A09, NONE),
+	/* GPP_A10:     NC */
+	PAD_NC(GPP_A10, NONE),
+	/* GPP_A11:     NC */
+	PAD_NC(GPP_A11, NONE),
+	/* GPP_A12:     NC */
+	PAD_NC(GPP_A12, NONE),
+	/* GPP_A13:     TCH_PAD_INT_N */
+	PAD_CFG_GPI_APIC_DRIVER(GPP_A13, NONE, PLTRST, EDGE_SINGLE, INVERT),
+	/* GPP_A15:     NC */
+	PAD_NC(GPP_A15, NONE),
+
+	/* GPP_B */
+	/* GPP_B00:     USBC_SML_CLK_PD */
+	PAD_CFG_NF(GPP_B00, NONE, DEEP, NF1),
+	/* GPP_B01:     USBC_SML_DATA_PD */
+	PAD_CFG_NF(GPP_B01, NONE, DEEP, NF1),
+	/* GPP_B02:     ISH_I2C0_SDA_SNSR_HDR */
+	PAD_NC(GPP_B02, NONE),
+	/* GPP_B03:     ISH_I2C0_SCL_SNSR_HDR */
+	PAD_NC(GPP_B03, NONE),
+	/* GPP_B04:     ISH_GP_0_SNSR_HDR */
+	PAD_NC(GPP_B04, NONE),
+	/* GPP_B06:     SOC_PDB_CTRL */
+	PAD_CFG_GPO(GPP_B06, 0, DEEP),
+	/* GPP_B08:     NC */
+	PAD_NC(GPP_B08, NONE),
+	/* GPP_B09:     BT_RF_KILL_N */
+	PAD_CFG_GPO(GPP_B09, 1, DEEP),
+	/* GPP_B10:     NC */
+	PAD_NC(GPP_B10, NONE),
+	/* GPP_B12:     PM_SLP_S0_N */
+	PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1),
+	/* GPP_B13:     PLT_RST_N */
+	PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1),
+	/* GPP_B14:     GPP_B14_DDSP_HPDB */
+	PAD_CFG_NF(GPP_B14, NONE, DEEP, NF2),
+	/* GPP_B16:     NC */
+	PAD_NC(GPP_B16, NONE),
+	/* GPP_B17:     SPI_TPM_INT_N */
+	PAD_CFG_GPI_APIC_LOCK(GPP_B17, NONE, LEVEL, INVERT, LOCK_CONFIG),
+	/* GPP_B20:     SOC_KB_MATRIX */
+	PAD_CFG_GPO(GPP_B20, 1, PLTRST),
+	/* GPP_B21:     TCP_RETIMER_FORCE_PWR */
+	PAD_CFG_GPO(GPP_B21, 0, DEEP),
+	/* GPP_B22:     SOC_CAM_WP */
+	PAD_CFG_GPO(GPP_B22, 0, DEEP),
+	/* GPP_B24:     ESPI_ALERT0_EC_R_N */
+	PAD_NC(GPP_B24, NONE),
+	/* GPP_B25:     None */
+	PAD_NC(GPP_B25, NONE),
+
+	/* GPP_C */
+	/* GPP_C00:     SPD_SMB_CLK */
+	PAD_CFG_NF(GPP_C00, NONE, DEEP, NF1),
+	/* GPP_C01:     SPD_SMB_DATA */
+	PAD_CFG_NF(GPP_C01, NONE, DEEP, NF1),
+	/* GPP_C02:     NC */
+	PAD_NC(GPP_C02, NONE),
+	/* GPP_C03:     TCP_LAN_SML0_SCL_R */
+	PAD_CFG_NF(GPP_C03, NONE, DEEP, NF1),
+	/* GPP_C04:     TCP_LAN_SML0_SDA_R */
+	PAD_CFG_NF(GPP_C04, NONE, DEEP, NF1),
+	/* GPP_C05:     NC */
+	PAD_NC(GPP_C05, NONE),
+	/* GPP_C06:     NC */
+	PAD_NC(GPP_C06, NONE),
+	/* GPP_C07:     NC */
+	PAD_NC(GPP_C07, NONE),
+	/* GPP_C08:     PM_SLP_S0_N_GPP_CNTRL */
+	PAD_CFG_GPO(GPP_C08, 1, PLTRST),
+	/* GPP_C09:     NC */
+	PAD_NC(GPP_C09, NONE),
+	/* GPP_C10:     WIFI_RF_KILL_N */
+	PAD_CFG_GPO(GPP_C10, 1, DEEP),
+	/* GPP_C11:     NC */
+	PAD_NC(GPP_C11, NONE),
+	/* GPP_C12:     CLKREQ3_X4_GEN4_M2_SSD_N */
+	PAD_CFG_NF(GPP_C12, NONE, DEEP, NF1),
+	/* GPP_C13:     NC */
+	PAD_NC(GPP_C13, NONE),
+	/* GPP_C14:     NC */
+	PAD_NC(GPP_C14, NONE),
+	/* GPP_C15:     FPS_RST_N */
+	PAD_CFG_GPO_LOCK(GPP_C15, 1, LOCK_CONFIG),
+	/* GPP_C16:     MOD_TCSS1_LS_TX_DDC_SCL */
+	PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1),
+	/* GPP_C17:     MOD_TCSS1_LS_RX_DDC_SDA */
+	PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1),
+	/* GPP_C18:     MOD_TCSS2_LS_TX_DDC_SCL */
+	PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1),
+	/* GPP_C19:     MOD_TCSS2_LS_RX_DDC_SDA */
+	PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1),
+	/* GPP_C22:     DDPB_HDMI_CTRLCLK */
+	PAD_CFG_NF(GPP_C22, NONE, DEEP, NF2),
+	/* GPP_C23:     DDPB_HDMI_CTRLDATA */
+	PAD_CFG_NF(GPP_C23, NONE, DEEP, NF2),
+
+	/* GPP_D */
+	/* GPP_D01:     NC */
+	PAD_NC(GPP_D01, NONE),
+	/* GPP_D02:     SOC_WP_OD */
+	PAD_CFG_GPO(GPP_D02, 0, DEEP),
+	/* GPP_D03:     NC */
+	PAD_NC(GPP_D03, NONE),
+	/* GPP_D07:     NC */
+	PAD_NC(GPP_D07, NONE),
+	/* GPP_D08:     NC */
+	PAD_NC(GPP_D08, NONE),
+	/* GPP_D09:     NC */
+	PAD_NC(GPP_D09, NONE),
+	/* GPP_D10:     NC */
+	PAD_NC(GPP_D10, NONE),
+	/* GPP_D11:     NC */
+	PAD_NC(GPP_D11, NONE),
+	/* GPP_D12:     NONE */
+	PAD_NC(GPP_D12, NONE),
+	/* GPP_D13:     NC */
+	PAD_NC(GPP_D13, NONE),
+	/* GPP_D16:     NC */
+	PAD_NC(GPP_D16, NONE),
+	/* GPP_D17:     NC */
+	PAD_NC(GPP_D17, NONE),
+	/* GPP_D19:     NC */
+	PAD_NC(GPP_D19, NONE),
+	/* GPP_D21:     GPP_D21_UFS_REFCLK_R */
+	PAD_CFG_NF(GPP_D21, NONE, DEEP, NF1),
+
+	/* GPP_E */
+	/* GPP_E01:     PM_SLP_DRAM_N */
+	PAD_CFG_NF(GPP_E01, NONE, DEEP, NF2),
+	/* GPP_E02:     VR_ALERT#_R */
+	PAD_NC(GPP_E02, NONE),
+	/* GPP_E03:     NC */
+	PAD_NC(GPP_E03, NONE),
+	/* GPP_E05:     NC */
+	PAD_NC(GPP_E05, NONE),
+	/* GPP_E06:     CAM_PRIVACY */
+	PAD_CFG_GPO(GPP_E06, 1, DEEP),
+	/* GPP_E07:     NC */
+	PAD_NC(GPP_E07, NONE),
+	/* GPP_E08:     NC */
+	PAD_NC(GPP_E08, NONE),
+	/* GPP_E09:     USB_FP_CONN_1_CONN_2_OC0_N */
+	PAD_CFG_NF(GPP_E09, NONE, DEEP, NF1),
+	/* GPP_E10:     NONE */
+	PAD_NC(GPP_E10, NONE),
+	/* GPP_E11:     NC */
+	PAD_NC(GPP_E11, NONE),
+	/* GPP_E12:     THC_I2C0_SCL_TCH_PNL1 */
+	PAD_CFG_NF(GPP_E12, NONE, DEEP, NF3),
+	/* GPP_E13:     THC_I2C0_SDA_TCH_PNL1 */
+	PAD_CFG_NF(GPP_E13, NONE, DEEP, NF3),
+	/* GPP_E14:     NC */
+	PAD_NC(GPP_E14, NONE),
+	/* GPP_E15:     NC */
+	PAD_NC(GPP_E15, NONE),
+	/* GPP_E16:     THC0_SPI1_RST_N_TCH_PNL1 */
+	PAD_CFG_NF(GPP_E16, NONE, PLTRST, NF1),
+	/* GPP_E17:     NC */
+	PAD_NC(GPP_E17, NONE),
+	/* GPP_E18:     THC0_SPI1_INT_N_TCH_PNL1 */
+	PAD_CFG_NF(GPP_E18, NONE, DEEP, NF3),
+	/* GPP_E19:     FPS_INT_N */
+	PAD_CFG_GPI_IRQ_WAKE(GPP_E19, NONE, PWROK, LEVEL, INVERT),
+	/* GPP_E20:     FPS_FW_UPDATE */
+	PAD_CFG_GPO_LOCK(GPP_E20, 0, LOCK_CONFIG),
+	/* GPP_E21:     I2C_PMC_PD_INT_N */
+	PAD_CFG_NF(GPP_E21, NONE, DEEP, NF1),
+	/* GPP_E22:     NC */
+	PAD_NC(GPP_E22, NONE),
+
+	/* GPP_F */
+	/* GPP_F00:     M.2_CNV_BRI_DT_BT_UART2_RTS_N */
+	PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_F00, NONE, DEEP, NF1),
+	/* GPP_F01:     M.2_CNV_BRI_RSP_BT_UART2_RXD */
+	PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_F01, NONE, DEEP, NF1),
+	/* GPP_F02:     M.2_CNV_RGI_DT_BT_UART2_TXD */
+	PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_F02, NONE, DEEP, NF1),
+	/* GPP_F03:     M.2_CNV_RGI_RSP_BT_UART2_CTS_N */
+	PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_F03, NONE, DEEP, NF1),
+	/* GPP_F04:     CNV_RF_RESET_R_N */
+	PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_F04, NONE, DEEP, NF1),
+	/* GPP_F05:     CRF_CLKREQ_R */
+	PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_F05, NONE, DEEP, NF3),
+	/* GPP_F06:     NC */
+	PAD_NC(GPP_F06, NONE),
+	/* GPP_F07:     NC */
+	PAD_NC(GPP_F07, NONE),
+	/* GPP_F08:     TCH_PNL1_PWR_EN */
+	PAD_CFG_GPO(GPP_F08, 1, PLTRST),
+	/* GPP_F09:     M2_UFS_RST_N */
+	PAD_CFG_GPO(GPP_F09, 1, DEEP),
+	/* GPP_F10:     SOC_EC_INT */
+	PAD_CFG_GPI_APIC(GPP_F10, NONE, PLTRST, LEVEL, INVERT),
+	/* GPP_F11:     NC */
+	PAD_NC(GPP_F11, NONE),
+	/* GPP_F12:     THC_I2C1_SCL_TCH_PAD */
+	PAD_CFG_NF(GPP_F12, NONE, DEEP, NF8),
+	/* GPP_F13:     THC_I2C1_SDA_TCH_PAD */
+	PAD_CFG_NF(GPP_F13, NONE, DEEP, NF8),
+	/* GPP_F14:     GPP_F14_GPSI0A_MOSI */
+	PAD_CFG_NF(GPP_F14, NONE, DEEP, NF8),
+	/* GPP_F15:     GPP_F15_GSPI0A_MISO */
+	PAD_CFG_NF(GPP_F15, NONE, DEEP, NF8),
+	/* GPP_F16:     GPP_F16_GSPI0A_CLK */
+	PAD_CFG_NF(GPP_F16, NONE, DEEP, NF8),
+	/* GPP_F17:     NC */
+	PAD_NC(GPP_F17, NONE),
+	/* GPP_F18:     GPP_F18_GSPI0A_CS0 */
+	PAD_CFG_NF(GPP_F18, NONE, DEEP, NF8),
+	/* GPP_F19:     NC */
+	PAD_NC(GPP_F19, NONE),
+	/* GPP_F20:     CSE_EARLY_SW */
+	PAD_CFG_GPI(GPP_F20, NONE, DEEP),
+	/* GPP_F22:     THC1_SPI2_DSYNC */
+	PAD_CFG_NF(GPP_F22, NONE, DEEP, NF3),
+
+	/* GPP_H */
+	/* GPP_H00:     NC */
+	PAD_NC(GPP_H00, NONE),
+	/* GPP_H01:     M2_UFS_SLP_N */
+	PAD_CFG_GPO(GPP_H01, 1, DEEP),
+	/* GPP_H02:     DEBUG_TRACE_PNP */
+	PAD_CFG_GPO(GPP_H02, 1, PLTRST),
+	/* GPP_H03:     MIC MUTE */
+	PAD_CFG_NF(GPP_H03, NONE, DEEP, NF1),
+	/* GPP_H04:     NC */
+	PAD_NC(GPP_H04, NONE),
+	/* GPP_H05:     NC */
+	PAD_NC(GPP_H05, NONE),
+	/* GPP_H06:     I2C3_SCL_AUDIO_HDR */
+	PAD_CFG_NF(GPP_H06, NONE, DEEP, NF1),
+	/* GPP_H07:     I2C3_SDA_AUDIO_HDR */
+	PAD_CFG_NF(GPP_H07, NONE, DEEP, NF1),
+	/* GPP_H08:     SOC_BIOS_LOG_TTK_UART_RX */
+	PAD_CFG_NF(GPP_H08, NONE, DEEP, NF1),
+	/* GPP_H09:     SOC_BIOS_LOG_TTK_UART_TX */
+	PAD_CFG_NF(GPP_H09, NONE, DEEP, NF1),
+	/* GPP_H10:     NC */
+	PAD_NC(GPP_H10, NONE),
+	/* GPP_H11:     NC */
+	PAD_NC(GPP_H11, NONE),
+	/* GPP_H13:     CPU_C10_GATE_N_R */
+	PAD_CFG_NF(GPP_H13, NONE, DEEP, NF1),
+	/* GPP_H14:     ISH_I3C1_SDA_SNSR_HDR */
+	PAD_NC(GPP_H14, NONE),
+	/* GPP_H15:     ISH_I3C1_SCL_SNSR_HDR */
+	PAD_NC(GPP_H15, NONE),
+	/* GPP_H17:     MIC MUTE LED */
+	PAD_CFG_NF(GPP_H17, NONE, DEEP, NF1),
+	/* GPP_H18:     GEN4_SSD_PWREN */
+	PAD_CFG_GPO(GPP_H18, 1, DEEP),
+	/* GPP_H19:     I3C0_SDA_HDR */
+	PAD_CFG_NF(GPP_H19, NONE, DEEP, NF2),
+	/* GPP_H20:     I3C0_SCL_HDR */
+	PAD_CFG_NF(GPP_H20, NONE, DEEP, NF2),
+	/* GPP_H21:     I2C1_SDA_TTK_CHROME */
+	PAD_CFG_NF(GPP_H21, NONE, DEEP, NF1),
+	/* GPP_H22:     I2C1_SCL_TTK_CHROME */
+	PAD_CFG_NF(GPP_H22, NONE, DEEP, NF1),
+	/* GPP_H23:     NC */
+	PAD_NC(GPP_H23, NONE),
+	/* GPP_H24:     NC */
+	PAD_NC(GPP_H24, NONE),
+
+	/* GPP_V */
+	/* GPP_V00:     PM_BATLOW_N */
+	PAD_CFG_NF(GPP_V00, NONE, DEEP, NF1),
+	/* GPP_V01:     BC_ACOK_MCP */
+	PAD_CFG_NF(GPP_V01, NONE, DEEP, NF1),
+	/* GPP_V02:     LANWAKE_N_R */
+	PAD_CFG_NF(GPP_V02, NONE, DEEP, NF1),
+	/* GPP_V03:     PWRBTN_MCP_N */
+	PAD_CFG_NF(GPP_V03, UP_20K, DEEP, NF1),
+	/* GPP_V04:     PM_SLP_S3_N */
+	PAD_CFG_NF(GPP_V04, NONE, DEEP, NF1),
+	/* GPP_V05:     PM_SLP_S4_N */
+	PAD_CFG_NF(GPP_V05, NONE, DEEP, NF1),
+	/* GPP_V06:     PM_SLP_A_N */
+	PAD_CFG_NF(GPP_V06, NONE, DEEP, NF1),
+	/* GPP_V07:     M.2_BTWIFI_SUS_CLK_LS */
+	PAD_CFG_NF(GPP_V07, NONE, DEEP, NF1),
+	/* GPP_V08:     SLP_WLAN_N */
+	PAD_CFG_NF(GPP_V08, NONE, DEEP, NF1),
+	/* GPP_V09:     PM_SLP_S5_N */
+	PAD_CFG_NF(GPP_V09, NONE, DEEP, NF1),
+	/* GPP_V10:     NC */
+	PAD_NC(GPP_V10, NONE),
+	/* GPP_V11:     PM_SLP_LAN_N */
+	PAD_CFG_NF(GPP_V11, NONE, DEEP, NF1),
+	/* GPP_V12:     WAKE_N */
+	PAD_CFG_NF(GPP_V12, NONE, DEEP, NF1),
+	/* GPP_V13:     GPP_V13_CATERR_N */
+	PAD_CFG_NF(GPP_V13, NONE, DEEP, NF1),
+	/* GPP_V14:     GPP_V14_FORCEPR_N */
+	PAD_CFG_NF(GPP_V14, NONE, DEEP, NF1),
+	/* GPP_V15:     GPP_V15_THERMTRIP_N */
+	PAD_CFG_NF(GPP_V15, NONE, DEEP, NF1),
+	/* GPP_V16:     GPP_V16_VCCST_EN */
+	PAD_CFG_NF(GPP_V16, NONE, DEEP, NF1),
+};
+
+/* Early pad configuration in bootblock */
+static const struct pad_config early_gpio_table[] = {
+	/* GPP_B17:     SPI_TPM_INT_N */
+	PAD_CFG_GPI_APIC(GPP_B17, NONE, DEEP, LEVEL, INVERT),
+	/* GPP_H06: I2C3_SDA_PSS */
+	PAD_CFG_NF(GPP_H06, NONE, DEEP, NF1),
+	/* GPP_H07: I2C3_SCL_PSS */
+	PAD_CFG_NF(GPP_H07, NONE, DEEP, NF1),
+	/* GPP_H08:     SOC_BIOS_LOG_TTK_UART_RX */
+	PAD_CFG_NF(GPP_H08, NONE, DEEP, NF1),
+	/* GPP_H09:     SOC_BIOS_LOG_TTK_UART_TX */
+	PAD_CFG_NF(GPP_H09, NONE, DEEP, NF1),
+	/* GPP_H21:     I2C1_SDA_TTK_CHROME */
+	PAD_CFG_NF(GPP_H21, NONE, DEEP, NF1),
+	/* GPP_H22:     I2C1_SCL_TTK_CHROME */
+	PAD_CFG_NF(GPP_H22, NONE, DEEP, NF1),
+};
+
+/* Pad configuration in romstage */
+static const struct pad_config romstage_gpio_table[] = {
+	/* GPP_C00:     SPD_SMB_CLK */
+	PAD_CFG_NF(GPP_C00, NONE, DEEP, NF1),
+	/* GPP_C01:     SPD_SMB_DATA */
+	PAD_CFG_NF(GPP_C01, NONE, DEEP, NF1),
+	/* GPP_C15:     FPS_RST_N */
+	PAD_CFG_GPO(GPP_C15, 0, PLTRST),
+};
+
+const struct pad_config *variant_gpio_table(size_t *num)
+{
+	*num = ARRAY_SIZE(gpio_table);
+	return gpio_table;
+}
+
+const struct pad_config *variant_early_gpio_table(size_t *num)
+{
+	*num = ARRAY_SIZE(early_gpio_table);
+	return early_gpio_table;
+}
+
+/* Create the stub for romstage gpio, typically use for power sequence */
+const struct pad_config *variant_romstage_gpio_table(size_t *num)
+{
+	*num = ARRAY_SIZE(romstage_gpio_table);
+	return romstage_gpio_table;
+}
+
+static const struct cros_gpio cros_gpios[] = {
+	CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE0_NAME),
+	CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE1_NAME),
+	CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE2_NAME),
+	CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE3_NAME),
+	CROS_GPIO_WP_AH(GPIO_PCH_WP, CROS_GPIO_DEVICE4_NAME),
+};
+
+DECLARE_CROS_GPIOS(cros_gpios);
diff --git a/src/mainboard/google/ocelot/variants/kodkod/hda_verb.c b/src/mainboard/google/ocelot/variants/kodkod/hda_verb.c
new file mode 100644
index 0000000000..2f703b78ee
--- /dev/null
+++ b/src/mainboard/google/ocelot/variants/kodkod/hda_verb.c
@@ -0,0 +1,126 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <device/azalia_device.h>
+
+const u32 cim_verb_data[] = {
+	/* coreboot specific header */
+	0x10ec0256,	/* Codec Vendor / Device ID: Realtek ALC256 */
+	0x10ec12ac,	/* Subsystem ID */
+	0x00000013,	/* Number of jacks (NID entries) */
+
+	AZALIA_RESET(0x1),
+	/* NID 0x01, HDA Codec Subsystem ID Verb Table */
+	AZALIA_SUBVENDOR(0, 0x10ec12ac),
+
+	/* Pin Widget Verb Table */
+	/*
+	 * DMIC
+	 * Requirement is to use PCH DMIC. Hence,
+	 * commented out codec's Internal DMIC.
+	 * AZALIA_PIN_CFG(0, 0x12, 0x90A60130),
+	 * AZALIA_PIN_CFG(0, 0x13, 0x40000000),
+	 */
+	/* Pin widget 0x14 - Front (Port-D) */
+	AZALIA_PIN_CFG(0, 0x14, 0x90170110),
+	/* Pin widget 0x18 - NPC */
+	AZALIA_PIN_CFG(0, 0x18, 0x411111F0),
+	/* Pin widget 0x19 - MIC2 (Port-F) */
+	AZALIA_PIN_CFG(0, 0x19, 0x04A11040),
+	/* Pin widget 0x1A - LINE1 (Port-C) */
+	AZALIA_PIN_CFG(0, 0x1a, 0x411111F0),
+	/* Pin widget 0x1B - NPC */
+	AZALIA_PIN_CFG(0, 0x1b, 0x411111F0),
+	/* Pin widget 0x1D - BEEP-IN */
+	AZALIA_PIN_CFG(0, 0x1d, 0x40610041),
+	/* Pin widget 0x1E - NPC */
+	AZALIA_PIN_CFG(0, 0x1e, 0x411111F0),
+	/* Pin widget 0x21 - HP1-OUT (Port-I) */
+	AZALIA_PIN_CFG(0, 0x21, 0x04211020),
+	/*
+	 * Widget node 0x20 - 1
+	 * Codec hidden reset and speaker power 2W/4ohm
+	 */
+	0x0205001A,
+	0x0204C003,
+	0x02050038,
+	0x02047901,
+	/*
+	 * Widget node 0x20 - 2
+	 * Class D power on Reset
+	 */
+	0x0205003C,
+	0x02040354,
+	0x0205003C,
+	0x02040314,
+	/*
+	 * Widget node 0x20 - 3
+	 * Disable AGC and set AGC limit to -1.5dB
+	 */
+	0x02050016,
+	0x02040C50,
+	0x02050012,
+	0x0204EBC1,
+	/*
+	 * Widget node 0x20 - 4
+	 * Set AGC Post gain +1.5dB then Enable AGC
+	 */
+	0x02050013,
+	0x02044023,
+	0x02050016,
+	0x02040E50,
+	/*
+	 * Widget node 0x20 - 5
+	 * Silence detector enabling + Set EAPD to verb control
+	 */
+	0x02050037,
+	0x0204FE15,
+	0x02050010,
+	0x02040020,
+	/*
+	 * Widget node 0x20 - 6
+	 * Silence data mode Threshold (-90dB)
+	 */
+	0x02050030,
+	0x0204A000,
+	0x0205001B,
+	0x02040A4B,
+	/*
+	 * Widget node 0x20 - 7
+	 * Default setting-1
+	 */
+	0x05750003,
+	0x05740DA3,
+	0x02050046,
+	0x02040004,
+	/*
+	 * Widget node 0x20 - 8
+	 * support 1 pin detect two port
+	 */
+	0x02050009,
+	0x0204E003,
+	0x0205000A,
+	0x02047770,
+	/*
+	 * Widget node 0x20 - 9
+	 * To set LDO1/LDO2 as default
+	 */
+	0x02050008,
+	0x02046A0C,
+	0x02050008,
+	0x02046A0C,
+};
+
+const u32 pc_beep_verbs[] = {
+	/* Dos beep path - 1 */
+	0x01470C00,
+	0x02050036,
+	0x02047151,
+	0x01470740,
+	/* Dos beep path - 2 */
+	0x0143b000,
+	0x01470C02,
+	0x01470C02,
+	0x01470C02,
+};
+
+AZALIA_ARRAY_SIZES;
diff --git a/src/mainboard/google/ocelot/variants/kodkod/include/variant/ec.h b/src/mainboard/google/ocelot/variants/kodkod/include/variant/ec.h
new file mode 100644
index 0000000000..4fc0622f15
--- /dev/null
+++ b/src/mainboard/google/ocelot/variants/kodkod/include/variant/ec.h
@@ -0,0 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#ifndef MAINBOARD_EC_H
+#define MAINBOARD_EC_H
+
+#include <baseboard/ec.h>
+
+#endif /* MAINBOARD_GPIO_H */
diff --git a/src/mainboard/google/ocelot/variants/kodkod/include/variant/gpio.h b/src/mainboard/google/ocelot/variants/kodkod/include/variant/gpio.h
new file mode 100644
index 0000000000..cced66807a
--- /dev/null
+++ b/src/mainboard/google/ocelot/variants/kodkod/include/variant/gpio.h
@@ -0,0 +1,11 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#ifndef __MAINBOARD_GPIO_H__
+#define __MAINBOARD_GPIO_H__
+
+#include <baseboard/gpio.h>
+
+/* EC wake is LAN_WAKE# which is a special DeepSX wake pin */
+#define GPE_EC_WAKE	GPE0_LAN_WAK
+
+#endif /* __MAINBOARD_GPIO_H__ */
diff --git a/src/mainboard/google/ocelot/variants/kodkod/memory.c b/src/mainboard/google/ocelot/variants/kodkod/memory.c
new file mode 100644
index 0000000000..f9e6fedfe4
--- /dev/null
+++ b/src/mainboard/google/ocelot/variants/kodkod/memory.c
@@ -0,0 +1,31 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <baseboard/variants.h>
+#include <boardid.h>
+#include <soc/meminit.h>
+#include <soc/romstage.h>
+
+#define SMBUS_ADDR_DIMM	0x50
+
+static const struct mb_cfg ddr5_mem_config = {
+	.type = MEM_TYPE_DDR5,
+
+	.ect = true, /* Early Command Training */
+
+	.user_bd = BOARD_TYPE_ULT_ULX,
+
+	.ddr_config = {
+		.dq_pins_interleaved = false,
+	},
+};
+const struct mb_cfg *variant_memory_params(void)
+{
+	return &ddr5_mem_config;
+}
+
+void variant_get_spd_info(struct mem_spd *spd_info)
+{
+	spd_info->topo = MEM_TOPO_DIMM_MODULE;
+	spd_info->smbus[0].addr_dimm[0] = SMBUS_ADDR_DIMM;
+	spd_info->smbus[1].addr_dimm[0] = SMBUS_ADDR_DIMM;
+}
diff --git a/src/mainboard/google/ocelot/variants/kodkod/overridetree.cb b/src/mainboard/google/ocelot/variants/kodkod/overridetree.cb
new file mode 100644
index 0000000000..bfd637ae50
--- /dev/null
+++ b/src/mainboard/google/ocelot/variants/kodkod/overridetree.cb
@@ -0,0 +1,5 @@
+chip soc/intel/pantherlake
+
+	device domain 0 on
+	end
+end

From 745f1312aa7505913897e5e36484e890f111414e Mon Sep 17 00:00:00 2001
From: Maximilian Brune <maximilian.brune@9elements.com>
Date: Wed, 22 Oct 2025 01:55:56 +0200
Subject: [PATCH 2328/3886] include/cper.h: Update comments to UEFI spec
 version 2.10

note: The entire patch was created using AI (besides commit-msg)

Change-Id: I0f80d1d8cd67b26a4ec1014584b5486254115839
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Co-authored-by: aider (openrouter/anthropic/claude-sonnet-4) <aider@aider.chat>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89677
Reviewed-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/include/cper.h | 52 +++++++++++++++++++++++-----------------------
 1 file changed, 26 insertions(+), 26 deletions(-)

diff --git a/src/include/cper.h b/src/include/cper.h
index af1778534a..4af8a7b3bf 100644
--- a/src/include/cper.h
+++ b/src/include/cper.h
@@ -13,11 +13,11 @@
  * is not a complete definition, but contains enough to generate a BERT ACPI
  * table.
  *
- * All table numbers and references correspond with UEFI spec version 2.7,
- * errata A, available at uefi.org.
+ * All table numbers and references correspond with UEFI spec version 2.10,
+ * Appendix N, available at uefi.org.
  */
 
-/* Error Record Header, Timestamp field (Table 251) */
+/* Error Record Header, Timestamp field (Table N.1) */
 typedef struct cper_timestamp { /* BCD values */
 	u8 sec;
 	u8 min;
@@ -31,7 +31,7 @@ typedef struct cper_timestamp { /* BCD values */
 
 #define CPER_TIMESTAMP_PRECISE			BIT(0)
 
-/* Section Descriptor, Flags field (Table 253) */
+/* Section Descriptor, Flags field (Table N.5) */
 #define CPER_SEC_PRIMARY			BIT(0)
 #define CPER_SEC_CONTAINMENT_WARNING		BIT(1)
 #define CPER_SEC_RESET				BIT(2)
@@ -41,7 +41,7 @@ typedef struct cper_timestamp { /* BCD values */
 #define CPER_SEC_PROPAGATED			BIT(6)
 #define CPER_SEC_OVERFLOW			BIT(7)
 
-/* Section Descriptor, Section Types values (Table 253) */
+/* Section Descriptor, Section Types values (Table N.5) */
 #define CPER_SEC_PROC_GENERIC_GUID			\
 		GUID_INIT(0x9876ccad, 0x47b4, 0x4bdb,	\
 		0xb6, 0x5e, 0x16, 0xf1, 0x93, 0xc4, 0xf3, 0xdb)
@@ -80,7 +80,7 @@ typedef struct cper_timestamp { /* BCD values */
 		0xa7, 0x9e, 0x57, 0x5f, 0xdf, 0xaa, 0x84, 0xec)
 
 /*
- * Processor Generic Error Section (Table 254)
+ * Processor Generic Error Section (Table N.6)
  */
 typedef struct cper_proc_generic_error_section {
 	u64 validation;
@@ -100,7 +100,7 @@ typedef struct cper_proc_generic_error_section {
 	u64 instruction_ip;
 } __packed cper_proc_generic_error_section_t;
 
-/* Processor Generic Error Section, Validation Bits field (Table 254) */
+/* Processor Generic Error Section, Validation Bits field (Table N.6) */
 #define GENPROC_VALID_PROC_TYPE			BIT(0)
 #define GENPROC_VALID_PROC_ISA			BIT(1)
 #define GENPROC_VALID_PROC_ERR_TYPE		BIT(2)
@@ -115,12 +115,12 @@ typedef struct cper_proc_generic_error_section {
 #define GENPROC_VALID_RSPR_ID			BIT(11)
 #define GENPROC_VALID_INSTR_IP			BIT(12)
 
-/* Processor Generic Error Section, Processor Type field (Table 254) */
+/* Processor Generic Error Section, Processor Type field (Table N.6) */
 #define GENPROC_PROCTYPE_IA32X64		0x0
 #define GENPROC_PROCTYPE_IA64			0x1
 #define GENPROC_PROCTYPE_ARM			0x2
 
-/* Processor Generic Error Section, Processor ISA (@time of fail) (Table 254) */
+/* Processor Generic Error Section, Processor ISA (@time of fail) (Table N.6) */
 #define GENPROC_ISA_IA32			0x0
 #define GENPROC_ISA_IA64			0x1
 #define GENPROC_ISA_X64				0x2
@@ -128,27 +128,27 @@ typedef struct cper_proc_generic_error_section {
 #define GENPROC_ISA_ARM64			0x4
 
 /* error_type definitions */
-/* Processor Generic Error Section, Processor Error Type field (Table 254) */
+/* Processor Generic Error Section, Processor Error Type field (Table N.6) */
 #define GENPROC_ERRTYPE_UNKNOWN			0x0
 #define GENPROC_ERRTYPE_CACHE			0x1
 #define GENPROC_ERRTYPE_TLB			0x2
 #define GENPROC_ERRTYPE_BUS			0x4
 #define GENPROC_ERRTYPE_UARCH			0x8
 
-/* Processor Generic Error Section, Operation field (Table 254) */
+/* Processor Generic Error Section, Operation field (Table N.6) */
 #define GENPROC_ERROP_UNKNOWN			0x0
 #define GENPROC_ERROP_READ			0x1
 #define GENPROC_ERROP_WRITE			0x2
 #define GENPROC_ERROP_EXECUTION			0x3
 
-/* Processor Generic Error Section, Flags field (Table 254) */
+/* Processor Generic Error Section, Flags field (Table N.6) */
 #define GENPROC_FLAG_RESTARTABLE		0x0
 #define GENPROC_FLAG_PRECISE_IP			0x1
 #define GENPROC_FLAG_OVERFLOW			0x2
 #define GENPROC_FLAG_CORRECTED			0x3
 
 /*
- * IA32/X64 Processor Error Section (Table 255)
+ * IA32/X64 Processor Error Section (Table N.7)
  */
 typedef struct cper_ia32x64_proc_error_section {
 	u64 validation;
@@ -158,7 +158,7 @@ typedef struct cper_ia32x64_proc_error_section {
 	/* PROC_CONTEXT_INFO_NUM x context structures */
 } __packed cper_ia32x64_proc_error_section_t;
 
-/* IA32/X64 Processor Error, Validation Bits field (Table 255) */
+/* IA32/X64 Processor Error, Validation Bits field (Table N.7) */
 #define I32X64SEC_VALID_LAPIC			BIT(0)
 #define I32X64SEC_VALID_CPUID			BIT(1)
 #define I32X64SEC_VALID_ERRNUM_SH		2
@@ -172,7 +172,7 @@ typedef struct cper_ia32x64_proc_error_section {
 					(I32X64SEC_VALID_CTXNUM_MAX \
 					<< I32X64SEC_VALID_CTXNUM_SH)
 
-/* IA32/X64 Processor Error Information Structure (Table 256) */
+/* IA32/X64 Processor Error Information Structure (Table N.8) */
 typedef struct cper_ia32x64_proc_error_info {
 	guid_t type; /* cache, tlb, bus, micro-architecture specific */
 	u64 validation;
@@ -183,7 +183,7 @@ typedef struct cper_ia32x64_proc_error_info {
 	u64 instruction_ip;
 } cper_ia32x64_proc_error_info_t;
 
-/* IA32/X64 Processor Error Information Structs, Err Struct Types (Table 256) */
+/* IA32/X64 Processor Error Information Structs, Err Struct Types (Table N.8) */
 #define X86_PROCESSOR_CACHE_CHK_ERROR_GUID		\
 		GUID_INIT(0xa55701f5, 0xe3ef, 0x43de,	\
 		0xac, 0x72, 0x24, 0x9b, 0x57, 0x3f, 0xad, 0x2c)
@@ -205,14 +205,14 @@ enum cper_x86_check_type {
 };
 #define X86_PROCESSOR_CHK_MAX X86_PROCESSOR_MS_CHK
 
-/* IA32/X64 Processor Error Information Structure, Validation Bits (Tbl 256) */
+/* IA32/X64 Processor Error Information Structure, Validation Bits (Table N.8) */
 #define I32X64ERRINFO_VALID_CHECK		BIT(0)
 #define I32X64ERRINFO_VALID_TGT_ADDR		BIT(1)
 #define I32X64ERRINFO_VALID_RQST_ID		BIT(2)
 #define I32X64ERRINFO_VALID_RSPD_ID		BIT(3)
 #define I32X64ERRINFO_VALID_IPPTR		BIT(4)
 
-/* IA32/X64 Proc. Error Info: Cache/TLB/Check defs (Tables 257, 258, 259) */
+/* IA32/X64 Proc. Error Info: Cache/TLB/Check defs (Tables N.9, N.10, N.11) */
 #define X86_PROC_CHK_XACT_TYPE_VALID		BIT(0)  /* CACHE|TLB|BUS */
 #define X86_PROC_CHK_OPERATION_VALID		BIT(1)  /* CACHE|TLB|BUS */
 #define X86_PROC_CHK_LEVEL_VALID		BIT(2)  /* CACHE|TLB|BUS */
@@ -262,7 +262,7 @@ enum cper_x86_check_type {
 #define X86_PROC_CHK_SPACE_MEM			(0 << X86_PROC_CHK_SPACE_SH)
 #define X86_PROC_CHK_SPACE_IO			(2 << X86_PROC_CHK_SPACE_SH)
 #define X86_PROC_CHK_SPACE_OTHER		(3 << X86_PROC_CHK_SPACE_SH)
-/* MS check defines & aligns (Table 260 */
+/* MS check defines & aligns (Table N.12) */
 #define X86_PROC_MS_ERROR_TYPE_VALID		BIT(0)
 #define X86_PROC_MS_CONTEXT_CORPT_VALID		BIT(1)
 #define X86_PROC_MS_UNCORRECTED_VALID		BIT(2)
@@ -283,7 +283,7 @@ enum cper_x86_check_type {
 #define X86_PROC_MS_CHK_RESTARTABLE_IP		(1 << 22)
 #define X86_PROC_MS_CHK_OVERFLOW		(1 << 23)
 
-/* IA32/X64 Processor Context Information (Table 261) */
+/* IA32/X64 Processor Context Information (Table N.13) */
 typedef struct cper_ia32x64_context {
 	u16 type;
 	u16 array_size;
@@ -292,7 +292,7 @@ typedef struct cper_ia32x64_context {
 	/* N bytes of register array */
 } cper_ia32x64_context_t;
 
-/* IA32/X64 Processor Context Information, Types field (Table 261) */
+/* IA32/X64 Processor Context Information, Types field (Table N.13) */
 #define CPER_IA32X64_CTX_UNCL			0
 #define CPER_IA32X64_CTX_MSR			1
 #define CPER_IA32X64_CTX_32BIT_EX		2
@@ -302,7 +302,7 @@ typedef struct cper_ia32x64_context {
 #define CPER_IA32X64_CTX_64BIT_DBG		6
 #define CPER_IA32X64_CTX_MEMMAPPED		7
 
-/* IA32/X64 Processor Context IA32 Register State (Table 262) */
+/* IA32/X64 Processor Context IA32 Register State (Table N.14) */
 typedef struct cper_ia32x64_ctx_ia32state {
 	u32 eax;
 	u32 ebx;
@@ -331,7 +331,7 @@ typedef struct cper_ia32x64_ctx_ia32state {
 	u16 tr;
 } cper_ia32x64_ctx_ia32state_t;
 
-/* IA32/X64 Processor Context X64 Register state (Table 263) */
+/* IA32/X64 Processor Context X64 Register state (Table N.15) */
 typedef struct cper_ia32x64_ctx_x64state {
 	u64 rax;
 	u64 rbx;
@@ -406,7 +406,7 @@ struct cper_memory_section {
 	GUID_INIT(0x8f87f311, 0xc998, 0x4d9e,			\
 		0xa0, 0xc4, 0x60, 0x65, 0x51, 0x8c, 0x4f, 0x6d)
 
-/* Firmware Error Record Reference, UEFI v2.8 sec N.2.10  */
+/* Firmware Error Record Reference, UEFI v2.10 sec N.2.10  */
 typedef struct cper_fw_err_rec_section {
 	u8 record_type;
 	u8 revision;
@@ -446,7 +446,7 @@ static inline cper_timestamp_t cper_timestamp(int precise)
 /* Calculate the size of an IA32/X64 context by its type.  Some types have a
  * predetermined size, and others are variable size.  All sizes are rounded up
  * to the nearest multiple of 16 bytes (See Processor Context field of
- * Table 255).
+ * Table N.7).
  *
  * type is one of:
  *   CPER_IA32X64_CTX_UNCL
@@ -475,7 +475,7 @@ static inline size_t cper_ia32x64_ctx_sz_bytype(int type, int arr_num)
 	case CPER_IA32X64_CTX_64BIT_DBG:
 	case CPER_IA32X64_CTX_MEMMAPPED:
 	default:
-		/* Table 261: "size ... is determined by (Array Size / 8)" */
+		/* Table N.13: "size ... is determined by (Array Size / 8)" */
 		return ALIGN_UP(sz + arr_num * 8, 16);
 	}
 }

From 8a6f9bf731323f7b54047bb1930ecd97d32f743a Mon Sep 17 00:00:00 2001
From: Yu-Ping Wu <yupingso@chromium.org>
Date: Tue, 21 Oct 2025 15:50:51 +0800
Subject: [PATCH 2329/3886] ec/google/chromeec: Update EC headers

Generated using update_ec_headers.sh from EC repo commit:

  a74136aff032 ("driver/cps8601: Add the driver for CPS8601")

BUG=b:448300592
TEST=emerge-skywalker coreboot
BRANCH=none

Change-Id: I069e12e0bacdf243648b98c6d3c0c4db12e0f4f7
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89654
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
---
 src/ec/google/chromeec/ec_commands.h | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/ec/google/chromeec/ec_commands.h b/src/ec/google/chromeec/ec_commands.h
index 073ae597cf..8de9362540 100644
--- a/src/ec/google/chromeec/ec_commands.h
+++ b/src/ec/google/chromeec/ec_commands.h
@@ -6653,7 +6653,7 @@ enum cbi_data_tag {
 	CBI_TAG_PROVISION_MATRIX_VERSION = 28, /* uint32_t bit field */
 
 	/* Unified Firmware and Second-source Config:
-	 * A fixed-size array of 5 uint32_t values.
+	 * A fixed-size array of 4 uint32_t values.
 	 */
 	CBI_TAG_UFSC = 29,
 
@@ -6661,7 +6661,7 @@ enum cbi_data_tag {
 	CBI_TAG_COUNT,
 };
 
-#define CBI_UFSC_DATA_COUNT 5
+#define CBI_UFSC_DATA_COUNT 4
 
 /* Unified Firmware and Second-source Config (UFSC) data structure */
 struct cbi_ufsc {

From 668d643e5cdef22e5a01a5562227e573ec8c9951 Mon Sep 17 00:00:00 2001
From: "Johann C. Rode" <jcrode@gmx.net>
Date: Sat, 18 Oct 2025 09:13:13 -0700
Subject: [PATCH 2330/3886] mb/lenovo/sklkbl_thinkpad: Add Lenovo Thinkpad
 T470s as a variant

The hardware is mostly identical to the already supported Thinkpad
T480s. Aside from the CPU (KBL vs SKL), major hardware differences are
GPIO pins routed out to a classical docking station connector, and the
lack of support for dedicated GPUs.

A tricky aspect of this machine is that it fails to enumerate PCIe
devices when using a truncated Intel ME firmware even when retaining
the MFS partition [1]. I suspect that the PCIe clock generators are set
up in some other part of the ME firmware.

The VBT (intelvbttool) as well as GPIO register dumps (inteltool) was
obtained from the latest stock BIOS 1.55/N1WET76W. GPIO, USB and PCIe
port assignments have been cross-checked against the publicly available
schematics (Thorpe-2).

The patches were validated on a laptop with part number 20JT-S16E00 in
conjunction with a non-truncated deguarded Intel ME firmware [2].
A cursory hardware test (video, wifi, audio, network, reboot, etc.) has
everything working as expected (debian 13).

[1] https://puri.sm/posts/deep-dive-into-intel-me-disablement/
[2] deguard commit 497732f8b2e3bdc699c0fbc6713b6afbaef7506a

Change-Id: I113b31484a634b7c1acdba5f74e5eef050d4ede6
Signed-off-by: Johann C. Rode <jcrode@gmx.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89638
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
---
 src/mainboard/lenovo/sklkbl_thinkpad/Kconfig  |   9 +-
 .../lenovo/sklkbl_thinkpad/Kconfig.name       |   3 +
 .../lenovo/sklkbl_thinkpad/Makefile.mk        |   2 +
 .../variants/t470s/Makefile.mk                |  10 +
 .../sklkbl_thinkpad/variants/t470s/data.vbt   | Bin 0 -> 4300 bytes
 .../variants/t470s/gma-mainboard.ads          |  19 ++
 .../sklkbl_thinkpad/variants/t470s/gpio.c     | 199 ++++++++++++++++++
 .../sklkbl_thinkpad/variants/t470s/hda_verb.c |  90 ++++++++
 .../variants/t470s/memory_init_params.c       |  44 ++++
 .../variants/t470s/overridetree.cb            |  86 ++++++++
 .../variants/t470s/spd/spd_0.bin              | Bin 0 -> 512 bytes
 .../variants/t470s/spd/spd_1.bin              | Bin 0 -> 512 bytes
 .../variants/t470s/spd/spd_10.bin             | Bin 0 -> 512 bytes
 .../variants/t470s/spd/spd_11.bin             | Bin 0 -> 512 bytes
 .../variants/t470s/spd/spd_12.bin             | Bin 0 -> 512 bytes
 .../variants/t470s/spd/spd_13.bin             | Bin 0 -> 512 bytes
 .../variants/t470s/spd/spd_14.bin             | Bin 0 -> 512 bytes
 .../variants/t470s/spd/spd_15.bin             | Bin 0 -> 512 bytes
 .../variants/t470s/spd/spd_16.bin             | Bin 0 -> 512 bytes
 .../variants/t470s/spd/spd_17.bin             | Bin 0 -> 512 bytes
 .../variants/t470s/spd/spd_18.bin             | Bin 0 -> 512 bytes
 .../variants/t470s/spd/spd_19.bin             | Bin 0 -> 512 bytes
 .../variants/t470s/spd/spd_2.bin              | Bin 0 -> 512 bytes
 .../variants/t470s/spd/spd_20.bin             | Bin 0 -> 512 bytes
 .../variants/t470s/spd/spd_3.bin              | Bin 0 -> 512 bytes
 .../variants/t470s/spd/spd_4.bin              | Bin 0 -> 512 bytes
 .../variants/t470s/spd/spd_5.bin              | Bin 0 -> 512 bytes
 .../variants/t470s/spd/spd_6.bin              | Bin 0 -> 512 bytes
 .../variants/t470s/spd/spd_7.bin              | Bin 0 -> 512 bytes
 .../variants/t470s/spd/spd_8.bin              | Bin 0 -> 512 bytes
 .../variants/t470s/spd/spd_9.bin              | Bin 0 -> 512 bytes
 31 files changed, 461 insertions(+), 1 deletion(-)
 create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t470s/Makefile.mk
 create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t470s/data.vbt
 create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t470s/gma-mainboard.ads
 create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t470s/gpio.c
 create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t470s/hda_verb.c
 create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t470s/memory_init_params.c
 create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t470s/overridetree.cb
 create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t470s/spd/spd_0.bin
 create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t470s/spd/spd_1.bin
 create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t470s/spd/spd_10.bin
 create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t470s/spd/spd_11.bin
 create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t470s/spd/spd_12.bin
 create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t470s/spd/spd_13.bin
 create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t470s/spd/spd_14.bin
 create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t470s/spd/spd_15.bin
 create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t470s/spd/spd_16.bin
 create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t470s/spd/spd_17.bin
 create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t470s/spd/spd_18.bin
 create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t470s/spd/spd_19.bin
 create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t470s/spd/spd_2.bin
 create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t470s/spd/spd_20.bin
 create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t470s/spd/spd_3.bin
 create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t470s/spd/spd_4.bin
 create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t470s/spd/spd_5.bin
 create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t470s/spd/spd_6.bin
 create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t470s/spd/spd_7.bin
 create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t470s/spd/spd_8.bin
 create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t470s/spd/spd_9.bin

diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/Kconfig b/src/mainboard/lenovo/sklkbl_thinkpad/Kconfig
index bd84488762..c9b3bcbf0a 100644
--- a/src/mainboard/lenovo/sklkbl_thinkpad/Kconfig
+++ b/src/mainboard/lenovo/sklkbl_thinkpad/Kconfig
@@ -20,10 +20,15 @@ config BOARD_LENOVO_SKLKBL_THINKPAD_COMMON
 	select MAINBOARD_USES_IFD_GBE_REGION
 	select MEMORY_MAPPED_TPM
 	select SOC_INTEL_COMMON_BLOCK_HDA_VERB
-	select SOC_INTEL_KABYLAKE
+	select SOC_INTEL_KABYLAKE if BOARD_LENOVO_T480 || BOARD_LENOVO_T480S || BOARD_LENOVO_T580
+	select SOC_INTEL_SKYLAKE if BOARD_LENOVO_T470S
 	select SPD_READ_BY_WORD
 	select SYSTEM_TYPE_LAPTOP
 
+config BOARD_LENOVO_T470S
+	bool
+	select BOARD_LENOVO_SKLKBL_THINKPAD_COMMON
+
 config BOARD_LENOVO_T480
 	bool
 	select BOARD_LENOVO_SKLKBL_THINKPAD_COMMON
@@ -48,6 +53,7 @@ config MAINBOARD_DIR
 	default "lenovo/sklkbl_thinkpad"
 
 config VARIANT_DIR
+	default "t470s" if BOARD_LENOVO_T470S
 	default "t480" if BOARD_LENOVO_T480
 	default "t480s" if BOARD_LENOVO_T480S
 	default "t580" if BOARD_LENOVO_T580
@@ -56,6 +62,7 @@ config OVERRIDE_DEVICETREE
 	default "variants/\$(CONFIG_VARIANT_DIR)/overridetree.cb"
 
 config MAINBOARD_PART_NUMBER
+	default "T470s" if BOARD_LENOVO_T470S
 	default "T480" if BOARD_LENOVO_T480
 	default "T480s" if BOARD_LENOVO_T480S
 	default "T580" if BOARD_LENOVO_T580
diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/Kconfig.name b/src/mainboard/lenovo/sklkbl_thinkpad/Kconfig.name
index 21b9739e6f..26c4a3c65b 100644
--- a/src/mainboard/lenovo/sklkbl_thinkpad/Kconfig.name
+++ b/src/mainboard/lenovo/sklkbl_thinkpad/Kconfig.name
@@ -1,5 +1,8 @@
 # SPDX-License-Identifier: GPL-2.0-only
 
+config BOARD_LENOVO_T470S
+	bool "ThinkPad T470s"
+
 config BOARD_LENOVO_T480
 	bool "ThinkPad T480"
 
diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/Makefile.mk b/src/mainboard/lenovo/sklkbl_thinkpad/Makefile.mk
index bf88dd3cd7..3049190948 100644
--- a/src/mainboard/lenovo/sklkbl_thinkpad/Makefile.mk
+++ b/src/mainboard/lenovo/sklkbl_thinkpad/Makefile.mk
@@ -13,4 +13,6 @@ ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += variants/$(VARIANT_DIR)/gma-mainb
 
 subdirs-y += variants/$(VARIANT_DIR)
 
+ifeq ($(CONFIG_VARIANT_HAS_DGPU),y)
 CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/include
+endif
diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t470s/Makefile.mk b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t470s/Makefile.mk
new file mode 100644
index 0000000000..a6b399f161
--- /dev/null
+++ b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t470s/Makefile.mk
@@ -0,0 +1,10 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
+# Add files spd_0.bin to spd_20.bin to the cbfs image
+SPD_BINS := $(shell seq 0 20)
+define SPD_template
+cbfs-files-y += spd_$(1).bin
+spd_$(1).bin-file := spd/spd_$(1).bin
+spd_$(1).bin-type := raw
+endef
+$(foreach n,$(SPD_BINS),$(eval $(call SPD_template,$(n))))
diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t470s/data.vbt b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t470s/data.vbt
new file mode 100644
index 0000000000000000000000000000000000000000..049f56ec22aac7649b3eb60aa86f0f17f944badf
GIT binary patch
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zq9RU(gYGKW#rt5Kx51NqBdoKZ1D6|NlUs&+iQ~lQ9SpuC{)YH_;$Mib5DQKQCB$oq
z?;@@vZXym5cM;!5JV5L`3YT-X3{VM(GMpt#ObN0bUaW@9Da(G!vb%paDgn%r9!oBo
z!VNmPoFKr}+-F|M<y`mZ5om-!IpD$;QoALihUEE})$b#z=PF_Kb2)dCx;A>|TT=4+
zwf39W*?C|Ydy>!Pa%XZma3pN=+Sz%VpgByNCX85GMwqfRGa{hL{v9;26gp@p@vfH1
zO2`N^_B{YUy)N-E0jz{JnMI1YXi=7(24{u&N@$t)St|d^Hx>E{So?!*R$wqIT;fiY
zF4lZ(x$Sy>f3{7}nM{x0XmxG*W9F5X%hF@Pc#$wqKhx>|_CK6~%66D@XR>(VHrbV2
zXC|WR<}9~AK<m)vqJu#LBvpiV@PQY?upY`l|6J?$CYN!}F3NaeCPXM+W!d^F2z<=I
zHoq?B-%Jw$RKEoL-3$kqGRD{w4BuqRdyJi7_$^a@V~q3QMvv0uVIdC=dX&dJ>=_Tf
z?NL7Pu#Y|Xqesbkm|Mg;Q3;5wQ^X^p^0dfa5b<46`A}q^i}<Uk2ofuiaEGKsB-Sh8
zF-dt&VlPYhzNCCAv9Bb&A}Pg1th@+!7Af%}c7Ksnqc}3Q3tXn8$hhdZMnyV%5;oD0
zmpGZEqj)17{L72daGW!@w}^bgwmQO8F@ir)iM|ZoVRWi$IBtH@K+Fh@b{(OGS7GHC
z8XGcGBaNte)fU+Pjto%VaGW>qXA~w_2vp=1XQ9@>$vCK*I#OzcpvOQ1bzPirR1}0T
zf$<8uGG2qgWsTckfe3HaO<agqY|s)X7h>SDP9p}*Ia5Fk?K?Gf|4hB6on1h1nl~V^
z-vRvUwK#Z3|8yLx)V8cu3om6dYkWH?ltS|Gcx`qnSy82_*pSbpJ?l1Rp?{OjYTl?8
zz80$H%$<Z#lSgo5>B3F5m~u=OFpJl!r)J}m>(tn*Yw`#@cnk#1SqOq!qn%4mrc`g-
z+Of1Acse@t81yT~>X}THgBE}ds`tb~9(a&U1P2y?aIpfWVz@>X)sQ~Q*cW`3_9MkG
zzc2JfzVfQJHD|m>8n<YPE!W0SY#`8y=UlxO)fyx-P@0tG5`B~z10AA7Vze!`FE(&E
zJ+yn^Q2Jlc(I<6d+Vm7SJLHX!nC>`7H}&a`uYu3&rsWT}x!fMQZ!eH-32nXwo^7Kr
aBfww}eY{eznR^Ak<7;OCPUPtyq5ckd<>xB^

literal 0
HcmV?d00001

diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t470s/gma-mainboard.ads b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t470s/gma-mainboard.ads
new file mode 100644
index 0000000000..fcfbd75a92
--- /dev/null
+++ b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t470s/gma-mainboard.ads
@@ -0,0 +1,19 @@
+-- SPDX-License-Identifier: GPL-2.0-or-later
+
+with HW.GFX.GMA;
+with HW.GFX.GMA.Display_Probing;
+
+use HW.GFX.GMA;
+use HW.GFX.GMA.Display_Probing;
+
+private package GMA.Mainboard is
+
+   ports : constant Port_List :=
+     (eDP,
+      DP1,
+      DP2,
+      HDMI1,
+      HDMI2,
+      others => Disabled);
+
+end GMA.Mainboard;
diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t470s/gpio.c b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t470s/gpio.c
new file mode 100644
index 0000000000..277b27c838
--- /dev/null
+++ b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t470s/gpio.c
@@ -0,0 +1,199 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <soc/gpio.h>
+#include "../../variant.h"
+
+static const struct pad_config gpio_table[] = {
+	/* ------- GPIO Community 0 ------- */
+
+	/* ------- GPIO Group GPP_A ------- */
+	PAD_CFG_NF(GPP_A0, NONE, DEEP, NF1),				/* -KBRC */
+	PAD_CFG_NF(GPP_A1, NATIVE, DEEP, NF1),				/* LPC_AD0 */
+	PAD_CFG_NF(GPP_A2, NATIVE, DEEP, NF1),				/* LPC_AD1 */
+	PAD_CFG_NF(GPP_A3, NATIVE, DEEP, NF1),				/* LPC_AD2 */
+	PAD_CFG_NF(GPP_A4, NATIVE, DEEP, NF1),				/* LPC_AD3 */
+	PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1),				/* -LPC_FRAME */
+	PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1),				/* IRQSER */
+	PAD_CFG_NF(GPP_A7, NONE, DEEP, NF1),				/* -TPM_IRQ */
+	PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1),				/* -CLKRUN */
+	PAD_CFG_NF(GPP_A9, DN_20K, DEEP, NF1),				/* LPCCLK_EC_24M */
+	PAD_CFG_NF(GPP_A10, DN_20K, DEEP, NF1),				/* LPCCLK_DEBUG_24M */
+	PAD_CFG_NF(GPP_A11, NONE, DEEP, NF1),				/* LPCCLK_DEBUG_24M */
+	PAD_NC(GPP_A12, NONE),
+	PAD_CFG_NF(GPP_A13, NATIVE, DEEP, NF1),				/* -SUSWARN */
+	PAD_CFG_NF(GPP_A14, NATIVE, DEEP, NF1),				/* -SUS_STAT */
+	PAD_CFG_NF(GPP_A15, NATIVE, DEEP, NF1),				/* -SUSACK*/
+	PAD_NC(GPP_A16, NONE),
+	PAD_NC(GPP_A17, NONE),
+	PAD_NC(GPP_A18, NONE),
+	PAD_NC(GPP_A19, NONE),
+	PAD_NC(GPP_A20, NONE),
+	PAD_NC(GPP_A21, NONE),
+	PAD_NC(GPP_A22, NONE),
+	PAD_NC(GPP_A23, NONE),
+
+	/* ------- GPIO Group GPP_B ------- */
+	PAD_CFG_NF(GPP_B0, NONE, DEEP, NF1),				/* CORE_VID0 */
+	PAD_CFG_NF(GPP_B1, NONE, DEEP, NF1),				/* CORE_VID1 */
+	PAD_NC(GPP_B2, NONE),
+	PAD_NC(GPP_B3, NONE),
+	PAD_NC(GPP_B4, NONE),
+	PAD_CFG_NF(GPP_B5, NONE, DEEP, NF1),				/* -CLKREQ_PCIE0 (TB) */
+	PAD_CFG_NF(GPP_B6, NONE, DEEP, NF1),				/* -CLKREQ_PCIE1 (WLAN1) */
+	PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1),				/* -CLKREQ_PCIE2 (GBE) */
+	PAD_CFG_NF(GPP_B8, NONE, DEEP, NF1),				/* -CLKREQ_PCIE3 (WLAN2) */
+	PAD_CFG_NF(GPP_B9, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_B10, NONE, DEEP, NF1),				/* -CLKREQ_PCIE5 (SSD) */
+	PAD_CFG_NF(GPP_B11, NONE, DEEP, NF1),				/* -EXT_PWR_GATE */
+	PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1),				/* -PCH_SLP_S0 */
+	PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1),				/* -PLTRST */
+	PAD_CFG_NF(GPP_B14, NATIVE, DEEP, NF1),				/* PCH_SPKR */
+	PAD_CFG_GPO(GPP_B15, 0, DEEP),					/* NFC_DLREQ */
+	PAD_NC(GPP_B16, NONE),
+	PAD_NC(GPP_B17, NONE),
+	PAD_NC(GPP_B18, NONE),
+	PAD_NC(GPP_B19, NONE),
+	PAD_NC(GPP_B20, NONE),
+	PAD_NC(GPP_B21, NONE),
+	PAD_NC(GPP_B22, NONE),
+	PAD_NC(GPP_B23, NONE),
+
+	/* ------- GPIO Community 1 ------- */
+
+	/* ------- GPIO Group GPP_C ------- */
+	PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1),				/* SMB_CLK */
+	PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1),				/* SMB_DATA */
+	PAD_NC(GPP_C2, NONE),
+	PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1),				/* SML0_CLK */
+	PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1),				/* SML0_DATA */
+	PAD_NC(GPP_C5, NONE),
+	PAD_CFG_NF(GPP_C6, NONE, DEEP, NF1),				/* EC_SCL2 */
+	PAD_CFG_NF(GPP_C7, NONE, DEEP, NF1),				/* EC_SDA2 */
+	PAD_NC(GPP_C8, NONE),
+	PAD_NC(GPP_C9, NONE),
+	PAD_NC(GPP_C10, NONE),
+	PAD_NC(GPP_C11, NONE),
+	PAD_NC(GPP_C12, NONE),
+	PAD_NC(GPP_C13, NONE),
+	PAD_NC(GPP_C14, NONE),
+	PAD_NC(GPP_C15, NONE),
+	PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1),				/* I2C0_DATA */
+	PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1),				/* I2C0_CLK */
+	PAD_NC(GPP_C18, NONE),
+	PAD_NC(GPP_C19, NONE),
+	PAD_CFG_GPI_SCI(GPP_C20, NONE, DEEP, EDGE_SINGLE, INVERT),	/* -TBT_PLUG_EVENT */
+	PAD_CFG_GPO(GPP_C21, 0, DEEP),					/* TBT_FORCE_PWR */
+	PAD_CFG_GPI_SCI(GPP_C22, NONE, DEEP, EDGE_SINGLE, INVERT),	/* -EC_SCI */
+	PAD_CFG_GPI_SCI(GPP_C23, NONE, DEEP, EDGE_SINGLE, INVERT),	/* -EC_WAKE */
+
+	/* ------- GPIO Group GPP_D ------- */
+	PAD_CFG_GPI_TRIG_OWN(GPP_D0, UP_20K, DEEP, OFF, ACPI),		/* DOCKID0 */
+	PAD_CFG_GPI_TRIG_OWN(GPP_D1, UP_20K, DEEP, OFF, ACPI),		/* DOCKID1 */
+	PAD_CFG_GPI_TRIG_OWN(GPP_D2, UP_20K, DEEP, OFF, ACPI),		/* DOCKID2 */
+	PAD_CFG_GPI_TRIG_OWN(GPP_D3, UP_20K, DEEP, OFF, ACPI),		/* DOCKID3 */
+	PAD_NC(GPP_D4, NONE),
+	PAD_NC(GPP_D5, NONE),
+	PAD_NC(GPP_D6, NONE),
+	PAD_NC(GPP_D7, NONE),
+	PAD_NC(GPP_D8, NONE),
+	PAD_NC(GPP_D9, UP_20K),
+	PAD_NC(GPP_D10, NONE),
+	PAD_NC(GPP_D11, UP_20K),
+	PAD_NC(GPP_D12, UP_20K),
+	PAD_NC(GPP_D13, NONE),
+	PAD_NC(GPP_D14, NONE),
+	PAD_NC(GPP_D15, NONE),
+	PAD_NC(GPP_D16, NONE),
+	PAD_NC(GPP_D17, NONE),						/* DDI_PRIORITY1 */
+	PAD_CFG_GPO(GPP_D18, 0, DEEP),					/* DDI_PRIORITY2 */
+	PAD_NC(GPP_D19, NONE),
+	PAD_NC(GPP_D20, NONE),
+	PAD_CFG_GPI_TRIG_OWN(GPP_D21, UP_20K, DEEP, OFF, ACPI),		/* -DOCK_CAP_ID */
+	PAD_CFG_GPI_TRIG_OWN(GPP_D22, UP_20K, DEEP, OFF, ACPI),		/* -NFC_DTCT */
+	PAD_NC(GPP_D23, NONE),
+
+	/* ------- GPIO Group GPP_E ------- */
+	PAD_NC(GPP_E0, NONE),
+	PAD_CFG_GPI_TRIG_OWN(GPP_E1, NONE, DEEP, OFF, ACPI),
+	PAD_CFG_NF(GPP_E2, NONE, DEEP, NF1),				/* -PE_DTCT */
+	PAD_NC(GPP_E3, NONE),
+	PAD_CFG_GPO(GPP_E4, 1, DEEP),					/* NFC_ON */
+	PAD_CFG_NF(GPP_E5, NONE, RSMRST, NF1),
+	PAD_CFG_NF(GPP_E6, NONE, RSMRST, NF1),				/* SATA2_DEVSLP */
+	PAD_NC(GPP_E7, NONE),
+	PAD_NC(GPP_E8, NONE),
+	PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1),				/* -USB_PORT0_OC0 */
+	PAD_CFG_NF(GPP_E10, NONE, DEEP, NF1),				/* -USB_PORT1_OC1 */
+	PAD_CFG_NF(GPP_E11, NONE, DEEP, NF1),				/* -USB_PORT2_OC2 */
+	PAD_CFG_GPI_APIC_HIGH(GPP_E12, NONE, DEEP),			/* NFC_INT */
+	PAD_CFG_NF(GPP_E13, NONE, DEEP, NF1),				/* DDIP1_HPD */
+	PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1),				/* DDIP2_HPD */
+	PAD_NC(GPP_E15, NONE),
+	PAD_NC(GPP_E16, NONE),
+	PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1),				/* EDP_HPD */
+	PAD_NC(GPP_E18, NONE),
+	PAD_CFG_NF(GPP_E19, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_E20, NONE, DEEP, NF1),				/* DDIP2_CTRLCLK */
+	PAD_CFG_NF(GPP_E21, NONE, DEEP, NF1),				/* DDIP2_CTRLDATA */
+	PAD_NC(GPP_E22, NONE),
+	PAD_NC(GPP_E23, NONE),
+
+	/* ------- GPIO Community 2 ------- */
+
+	/* -------- GPIO Group GPD -------- */
+	PAD_CFG_NF(GPD0, NONE, PWROK, NF1),				/* -BATLOW */
+	PAD_CFG_NF(GPD1, NATIVE, PWROK, NF1),				/* AC_PRESENT */
+	PAD_CFG_NF(GPD2, NATIVE, PWROK, NF1),				/* -LANWAKE */
+	PAD_CFG_NF(GPD3, UP_20K, PWROK, NF1),				/* -PWRSW_EC */
+	PAD_CFG_NF(GPD4, NONE, PWROK, NF1),				/* -PCH_SLP_S3 */
+	PAD_CFG_NF(GPD5, NONE, PWROK, NF1),				/* -PCH_SLP_S4 */
+	PAD_CFG_NF(GPD6, NONE, PWROK, NF1),				/* -PCH_SLP_M */
+	PAD_NC(GPD7, NONE),
+	PAD_CFG_NF(GPD8, NONE, PWROK, NF1),				/* SUSCLK_32K */
+	PAD_CFG_NF(GPD9, NONE, PWROK, NF1),				/* -PCH_SLP_WLAN */
+	PAD_CFG_NF(GPD10, NONE, PWROK, NF1),				/* -PCH_SLP_S5 */
+	PAD_CFG_NF(GPD11, NONE, PWROK, NF1),				/* LANPHYPC */
+
+	/* ------- GPIO Community 3 ------- */
+
+	/* ------- GPIO Group GPP_F ------- */
+	PAD_NC(GPP_F0, NONE),					/* NFC_ACTIVE */
+	PAD_NC(GPP_F1, NONE),
+	PAD_NC(GPP_F2, NONE),
+	PAD_NC(GPP_F3, NONE),
+	PAD_NC(GPP_F4, NONE),					/* -WWAN_RESET */
+	PAD_NC(GPP_F5, UP_20K),
+	PAD_CFG_GPI_TRIG_OWN(GPP_F6, UP_20K, RSMRST, OFF, ACPI),		/* -MIC_HW_EN (R961 to GND) */
+	PAD_CFG_GPI_TRIG_OWN(GPP_F7, UP_20K, RSMRST, OFF, ACPI),		/* -INT_MIC_DTCT */
+	PAD_CFG_GPI_TRIG_OWN(GPP_F8, UP_20K, RSMRST, OFF, ACPI),		/* WWAN_CFG0 */
+	PAD_CFG_GPI_TRIG_OWN(GPP_F9, UP_20K, RSMRST, OFF, ACPI),		/* WWAN_CFG1 */
+	PAD_CFG_GPI_TRIG_OWN(GPP_F10, UP_20K, RSMRST, OFF, ACPI),		/* WWAN_CFG2 */
+	PAD_CFG_GPI_TRIG_OWN(GPP_F11, UP_20K, RSMRST, OFF, ACPI),		/* WWAN_CFG3 */
+	PAD_CFG_GPI_TRIG_OWN(GPP_F12, UP_20K, RSMRST, OFF, ACPI),		/* PLANARID0 */
+	PAD_CFG_GPI_TRIG_OWN(GPP_F13, UP_20K, RSMRST, OFF, ACPI),		/* PLANARID1 */
+	PAD_CFG_GPI_TRIG_OWN(GPP_F14, UP_20K, RSMRST, OFF, ACPI),		/* PLANARID2 */
+	PAD_CFG_GPI_TRIG_OWN(GPP_F15, UP_20K, RSMRST, OFF, ACPI),		/* PLANARID3 */
+	PAD_CFG_GPI_TRIG_OWN(GPP_F16, UP_20K, RSMRST, OFF, ACPI),		/* MEMORYID0 */
+	PAD_CFG_GPI_TRIG_OWN(GPP_F17, UP_20K, RSMRST, OFF, ACPI),		/* MEMORYID1 */
+	PAD_CFG_GPI_TRIG_OWN(GPP_F18, UP_20K, RSMRST, OFF, ACPI),		/* MEMORYID2 */
+	PAD_CFG_GPI_TRIG_OWN(GPP_F19, UP_20K, RSMRST, OFF, ACPI),		/* MEMORYID3 */
+	PAD_CFG_GPI_TRIG_OWN(GPP_F20, UP_20K, RSMRST, OFF, ACPI),		/* MEMORYID4 */
+	PAD_NC(GPP_F21, UP_20K),
+	PAD_CFG_GPI_TRIG_OWN(GPP_F22, UP_20K, RSMRST, OFF, ACPI),		/* -TAMPER_SW_DTCT */
+	PAD_CFG_GPI_TRIG_OWN(GPP_F23, UP_20K, RSMRST, OFF, ACPI),		/* -SC_DTCT */
+
+	/* ------- GPIO Group GPP_G ------- */
+	PAD_NC(GPP_G0, NONE),
+	PAD_NC(GPP_G1, NONE),
+	PAD_NC(GPP_G2, NONE),
+	PAD_NC(GPP_G3, NONE),
+	PAD_NC(GPP_G4, NONE),
+	PAD_NC(GPP_G5, NONE),
+	PAD_NC(GPP_G6, NONE),
+	PAD_NC(GPP_G7, NONE),
+};
+
+void variant_config_gpios(void)
+{
+	gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table));
+}
diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t470s/hda_verb.c b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t470s/hda_verb.c
new file mode 100644
index 0000000000..1901127390
--- /dev/null
+++ b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t470s/hda_verb.c
@@ -0,0 +1,90 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <device/azalia_device.h>
+
+const u32 cim_verb_data[] = {
+	0x10ec0298, // Vendor/Device ID: Realtek ALC298
+	0x17aa224b, // Subsystem ID
+	12,
+	AZALIA_SUBVENDOR(0, 0x17aa224b),
+
+	AZALIA_PIN_CFG(0, 0x12, AZALIA_PIN_DESC(
+		AZALIA_INTEGRATED,
+		AZALIA_INTERNAL,
+		AZALIA_MIC_IN,
+		AZALIA_OTHER_DIGITAL,
+		AZALIA_COLOR_UNKNOWN,
+		AZALIA_NO_JACK_PRESENCE_DETECT,
+		4, 0
+	)),
+	AZALIA_PIN_CFG(0, 0x13, 0x40000000), // does not describe a jack or internal device
+	AZALIA_PIN_CFG(0, 0x14, AZALIA_PIN_DESC(
+		AZALIA_INTEGRATED,
+		AZALIA_INTERNAL,
+		AZALIA_SPEAKER,
+		AZALIA_OTHER_ANALOG,
+		AZALIA_COLOR_UNKNOWN,
+		AZALIA_NO_JACK_PRESENCE_DETECT,
+		1, 0
+	)),
+	AZALIA_PIN_CFG(0, 0x17, AZALIA_PIN_CFG_NC(0)),
+	AZALIA_PIN_CFG(0, 0x18, AZALIA_PIN_DESC(
+		AZALIA_JACK,
+		AZALIA_EXTERNAL_PRIMARY_CHASSIS | AZALIA_LEFT,
+		AZALIA_MIC_IN,
+		AZALIA_STEREO_MONO_1_8,
+		AZALIA_BLACK,
+		AZALIA_JACK_PRESENCE_DETECT,
+		3, 0
+	)),
+	AZALIA_PIN_CFG(0, 0x19, AZALIA_PIN_CFG_NC(0)),
+	AZALIA_PIN_CFG(0, 0x1a, AZALIA_PIN_CFG_NC(0)),
+	AZALIA_PIN_CFG(0, 0x1d, 0x40648605), // does not describe a jack or internal device
+	AZALIA_PIN_CFG(0, 0x1e, AZALIA_PIN_CFG_NC(0)),
+	AZALIA_PIN_CFG(0, 0x1f, AZALIA_PIN_CFG_NC(0)),
+	AZALIA_PIN_CFG(0, 0x21, AZALIA_PIN_DESC(
+		AZALIA_JACK,
+		AZALIA_EXTERNAL_PRIMARY_CHASSIS | AZALIA_LEFT,
+		AZALIA_HP_OUT,
+		AZALIA_STEREO_MONO_1_8,
+		AZALIA_BLACK,
+		AZALIA_JACK_PRESENCE_DETECT,
+		2, 0
+	)),
+
+	0x80862809, // Vendor/Device ID: Intel Skylake HDMI
+	0x80860101, // Subsystem ID
+	4,
+	AZALIA_SUBVENDOR(2, 0x80860101),
+
+	AZALIA_PIN_CFG(2, 0x05, AZALIA_PIN_DESC(
+		AZALIA_JACK,
+		AZALIA_DIGITAL_DISPLAY,
+		AZALIA_DIGITAL_OTHER_OUT,
+		AZALIA_OTHER_DIGITAL,
+		AZALIA_COLOR_UNKNOWN,
+		AZALIA_JACK_PRESENCE_DETECT,
+		1, 0
+	)),
+	AZALIA_PIN_CFG(2, 0x06, AZALIA_PIN_DESC(
+		AZALIA_JACK,
+		AZALIA_DIGITAL_DISPLAY,
+		AZALIA_DIGITAL_OTHER_OUT,
+		AZALIA_OTHER_DIGITAL,
+		AZALIA_COLOR_UNKNOWN,
+		AZALIA_JACK_PRESENCE_DETECT,
+		1, 0
+	)),
+	AZALIA_PIN_CFG(2, 0x07, AZALIA_PIN_DESC(
+		AZALIA_JACK,
+		AZALIA_DIGITAL_DISPLAY,
+		AZALIA_DIGITAL_OTHER_OUT,
+		AZALIA_OTHER_DIGITAL,
+		AZALIA_COLOR_UNKNOWN,
+		AZALIA_JACK_PRESENCE_DETECT,
+		1, 0
+	)),
+};
+
+const u32 pc_beep_verbs[] = {};
+AZALIA_ARRAY_SIZES;
diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t470s/memory_init_params.c b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t470s/memory_init_params.c
new file mode 100644
index 0000000000..001e934b3a
--- /dev/null
+++ b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t470s/memory_init_params.c
@@ -0,0 +1,44 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <cbfs.h>
+#include <gpio.h>
+#include <soc/gpio.h>
+#include <soc/romstage.h>
+#include <spd_bin.h>
+#include <stdio.h>
+
+static const struct pad_config memory_id_gpio_table[] = {
+	PAD_CFG_GPI_TRIG_OWN(GPP_F16, UP_20K, DEEP, OFF, ACPI),		/* MEMORYID0 */
+	PAD_CFG_GPI_TRIG_OWN(GPP_F17, UP_20K, DEEP, OFF, ACPI),		/* MEMORYID1 */
+	PAD_CFG_GPI_TRIG_OWN(GPP_F18, UP_20K, DEEP, OFF, ACPI),		/* MEMORYID2 */
+	PAD_CFG_GPI_TRIG_OWN(GPP_F19, UP_20K, DEEP, OFF, ACPI),		/* MEMORYID3 */
+	PAD_CFG_GPI_TRIG_OWN(GPP_F20, UP_20K, DEEP, OFF, ACPI),		/* MEMORYID4 */
+};
+
+void mainboard_memory_init_params(FSPM_UPD *mupd)
+{
+	int spd_idx;
+	char spd_name[20];
+	size_t spd_size;
+
+	FSP_M_CONFIG *mem_cfg = &mupd->FspmConfig;
+	mem_cfg->DqPinsInterleaved = true;			/* DDR_DQ in interleave mode */
+	mem_cfg->CaVrefConfig      = 2;				/* VREF_CA to CH_A and VREF_DQ_B to CH_B */
+	mem_cfg->MemorySpdDataLen  = CONFIG_DIMM_SPD_SIZE;
+
+	/* Get SPD for soldered RAM SPD (CH A) */
+	gpio_configure_pads(memory_id_gpio_table, ARRAY_SIZE(memory_id_gpio_table));
+
+	spd_idx = gpio_get(GPP_F16) | gpio_get(GPP_F17) << 1 | gpio_get(GPP_F18) << 2 |
+		  gpio_get(GPP_F19) << 3 | gpio_get(GPP_F20) << 4;
+	printk(BIOS_DEBUG, "Detected MEMORY_ID = %d\n", spd_idx);
+	snprintf(spd_name, sizeof(spd_name), "spd_%d.bin", spd_idx);
+	mem_cfg->MemorySpdPtr00    = (uintptr_t)cbfs_map(spd_name, &spd_size);
+
+	/* Get SPD for memory slot (CH B) */
+	struct spd_block blk = { .addr_map = { [1] = 0x51, } };
+	get_spd_smbus(&blk);
+	dump_spd_info(&blk);
+
+	mem_cfg->MemorySpdPtr10    = (uintptr_t)blk.spd_array[1];
+}
diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t470s/overridetree.cb b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t470s/overridetree.cb
new file mode 100644
index 0000000000..dc2143d3eb
--- /dev/null
+++ b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t470s/overridetree.cb
@@ -0,0 +1,86 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
+chip soc/intel/skylake
+	device domain 0 on
+		device ref south_xhci on
+			register "usb2_ports" = "{
+				[0] = USB2_PORT_MID(OC0),		// JUSB1 (USB-A always on)
+				[1] = USB2_PORT_MID(OC1),		// JUSB2 (USB-A)
+				[2] = USB2_PORT_MID(OC_SKIP),		// N/C
+				[3] = USB2_PORT_MID(OC_SKIP),		// JUSBC (USB docking station)
+				[4] = USB2_PORT_MID(OC_SKIP),		// JFPR (smartcard slot)
+				[5] = USB2_PORT_MID(OC_SKIP),		// JWWAN (M.2 WWAN USB)
+				[6] = USB2_PORT_MID(OC_SKIP),		// JWLAN (M.2 WLAN USB)
+				[7] = USB2_PORT_MID(OC_SKIP),		// JCAM (webcam)
+				[8] = USB2_PORT_MID(OC_SKIP),		// JFPR (fingerprint reader)
+				[9] = USB2_PORT_MID(OC_SKIP),		// JLCD (touch panel)
+			}"
+			register "usb3_ports" = "{
+				[0] = USB3_PORT_DEFAULT(OC0),		// JUSB1 (USB-A always on)
+				[1] = USB3_PORT_DEFAULT(OC1),		// JUSB2 (USB-A)
+				[2] = USB3_PORT_DEFAULT(OC_SKIP),	// JSD (SD card reader)
+				[3] = USB3_PORT_DEFAULT(OC_SKIP),	// JUSB3 (USB docking station)
+			}"
+		end
+
+		# PCIe
+		#   PCIe Controller 1 - 1x2 + 2x1
+		#   PCIE 1-2   - RP1  - TB - CLKOUT0 - CLKREQ0
+		#   PCIE 3     - RP3  - WLAN#1 - CLKOUT1 - CLKREQ1
+		#   PCIE 4     - GBE  - GBE  - CLKOUT2 - CLKREQ2
+		#   PCIe Controller 2 - 4x1
+		#   PCIE 5     - RP5  - WLAN#2 - CLKOUT3 - CLKREQ3
+		#   PCIE 6-8   - n/c
+		#   PCIe Controller 3 - 1x4 (lane reversal)
+		#   PCIE 9-12  - RP9  - SSD  - CLKOUT5 - CLKREQ5
+
+		# TB - x2
+		device ref pcie_rp1 on
+			register "PcieRpClkReqSupport[0]"		= "true"
+			register "PcieRpClkReqNumber[0]"		= "0"
+			register "PcieRpClkSrcNumber[0]"		= "0"
+			register "PcieRpAdvancedErrorReporting[0]"	= "true"
+			register "PcieRpHotPlug[0]"			= "true"
+		end
+
+		# M.2 WLAN#1 - x1
+		device ref pcie_rp3 on
+			register "PcieRpClkReqSupport[2]"		= "true"
+			register "PcieRpClkReqNumber[2]"		= "1"
+			register "PcieRpClkSrcNumber[2]"		= "1"
+			register "PcieRpAdvancedErrorReporting[2]"	= "true"
+			register "PcieRpLtrEnable[2]"			= "true"
+			smbios_slot_desc "SlotTypeM2Socket1_DP" "SlotLengthOther" "M.2/A 2230" "SlotDataBusWidth1X"
+		end
+
+		# Ethernet (clobbers RP4)
+                device ref gbe on
+                        register "LanClkReqSupported"                   = "true"
+                        register "LanClkReqNumber"                      = "2"
+			register "PcieRpClkReqNumber[3]"		= "2"
+			register "PcieRpClkSrcNumber[3]"		= "2"
+                        register "EnableLanLtr"                         = "true"
+                        register "EnableLanK1Off"                       = "true"
+                end
+
+		# M.2 WLAN#2 - x1
+		device ref pcie_rp5 on
+			register "PcieRpClkReqSupport[4]"		= "true"
+			register "PcieRpClkReqNumber[4]"		= "3"
+			register "PcieRpClkSrcNumber[4]"		= "3"
+			register "PcieRpAdvancedErrorReporting[4]"	= "true"
+			register "PcieRpLtrEnable[4]"			= "true"
+			smbios_slot_desc "SlotTypeM2Socket1_DP" "SlotLengthOther" "M.2/A 2230" "SlotDataBusWidth1X"
+		end
+
+		# M.2 2280 SSD - x4 (RP9)
+		device ref pcie_rp9 on
+			register "PcieRpClkReqSupport[8]"		= "true"
+			register "PcieRpClkReqNumber[8]"		= "5"
+			register "PcieRpClkSrcNumber[8]"		= "5"
+			register "PcieRpAdvancedErrorReporting[8]"	= "true"
+			register "PcieRpLtrEnable[8]"			= "true"
+			smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M.2/M 2280" "SlotDataBusWidth4X"
+		end
+	end
+end
diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t470s/spd/spd_0.bin b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t470s/spd/spd_0.bin
new file mode 100644
index 0000000000000000000000000000000000000000..86f39ddb55ea9fb58d5e5699637636ef597c734e
GIT binary patch
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literal 0
HcmV?d00001

diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t470s/spd/spd_1.bin b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t470s/spd/spd_1.bin
new file mode 100644
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GIT binary patch
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diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t470s/spd/spd_10.bin b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t470s/spd/spd_10.bin
new file mode 100644
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GIT binary patch
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diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t470s/spd/spd_11.bin b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t470s/spd/spd_11.bin
new file mode 100644
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GIT binary patch
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diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t470s/spd/spd_12.bin b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t470s/spd/spd_12.bin
new file mode 100644
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GIT binary patch
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diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t470s/spd/spd_13.bin b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t470s/spd/spd_13.bin
new file mode 100644
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GIT binary patch
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diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t470s/spd/spd_14.bin b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t470s/spd/spd_14.bin
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diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t470s/spd/spd_15.bin b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t470s/spd/spd_15.bin
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diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t470s/spd/spd_16.bin b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t470s/spd/spd_16.bin
new file mode 100644
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GIT binary patch
literal 512
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literal 0
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diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t470s/spd/spd_17.bin b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t470s/spd/spd_17.bin
new file mode 100644
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GIT binary patch
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diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t470s/spd/spd_18.bin b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t470s/spd/spd_18.bin
new file mode 100644
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diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t470s/spd/spd_19.bin b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t470s/spd/spd_19.bin
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diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t470s/spd/spd_2.bin b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t470s/spd/spd_2.bin
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diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t470s/spd/spd_20.bin b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t470s/spd/spd_20.bin
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diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t470s/spd/spd_3.bin b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t470s/spd/spd_3.bin
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diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t470s/spd/spd_4.bin b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t470s/spd/spd_4.bin
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diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t470s/spd/spd_5.bin b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t470s/spd/spd_5.bin
new file mode 100644
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GIT binary patch
literal 512
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diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t470s/spd/spd_6.bin b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t470s/spd/spd_6.bin
new file mode 100644
index 0000000000000000000000000000000000000000..a64a5a93fb4aef4d5f63d79cb2582731b9ac5063
GIT binary patch
literal 512
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literal 0
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diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t470s/spd/spd_7.bin b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t470s/spd/spd_7.bin
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diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t470s/spd/spd_8.bin b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t470s/spd/spd_8.bin
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diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t470s/spd/spd_9.bin b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t470s/spd/spd_9.bin
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literal 0
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From 3ef1cf9f84e8c0f8cc5caf40718c8d5d4a0d9fc1 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Micha=C5=82=20=C5=BBygowski?= <michal.zygowski@3mdeb.com>
Date: Tue, 8 Jul 2025 16:22:59 +0200
Subject: [PATCH 2331/3886] soc/amd/turin_poc: Add Turin SoC structure as a
 copy of genoa_poc
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Copied genoa_poc directory with Genoa occurrences renamed to Turin,
case sensitive.

Change-Id: I860f35a8b08dae1b3b18c65c96b0136f7b95913c
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88707
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com>
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
---
 src/soc/amd/turin_poc/Kconfig                 | 211 +++++++++
 src/soc/amd/turin_poc/Makefile.mk             | 160 +++++++
 src/soc/amd/turin_poc/acpi.c                  |  66 +++
 src/soc/amd/turin_poc/acpi/globalnvs.asl      |  13 +
 src/soc/amd/turin_poc/acpi/mmio.asl           | 414 ++++++++++++++++++
 src/soc/amd/turin_poc/acpi/pci_int_defs.asl   |  98 +++++
 src/soc/amd/turin_poc/acpi/soc.asl            |  39 ++
 src/soc/amd/turin_poc/aoac.c                  |  32 ++
 src/soc/amd/turin_poc/chip.c                  |  28 ++
 src/soc/amd/turin_poc/chip.h                  |  71 +++
 src/soc/amd/turin_poc/chipset.cb              | 394 +++++++++++++++++
 src/soc/amd/turin_poc/config.c                |  12 +
 src/soc/amd/turin_poc/cpu.c                   |  21 +
 src/soc/amd/turin_poc/domain.c                |  71 +++
 src/soc/amd/turin_poc/early_fch.c             |  33 ++
 src/soc/amd/turin_poc/fch.c                   |  86 ++++
 src/soc/amd/turin_poc/fw.cfg                  |  54 +++
 src/soc/amd/turin_poc/gpio.c                  |  38 ++
 src/soc/amd/turin_poc/i2c.c                   |  57 +++
 src/soc/amd/turin_poc/i3c.c                   |  18 +
 .../turin_poc/include/soc/amd_pci_int_defs.h  |  56 +++
 src/soc/amd/turin_poc/include/soc/aoac_defs.h |  24 +
 src/soc/amd/turin_poc/include/soc/cpu.h       |   9 +
 .../amd/turin_poc/include/soc/data_fabric.h   | 138 ++++++
 src/soc/amd/turin_poc/include/soc/gpio.h      | 270 ++++++++++++
 src/soc/amd/turin_poc/include/soc/i2c.h       |  36 ++
 src/soc/amd/turin_poc/include/soc/iomap.h     |  38 ++
 src/soc/amd/turin_poc/include/soc/lpc.h       |  16 +
 src/soc/amd/turin_poc/include/soc/msr.h       |  23 +
 src/soc/amd/turin_poc/include/soc/nvs.h       |  22 +
 src/soc/amd/turin_poc/include/soc/pci_devs.h  |  54 +++
 src/soc/amd/turin_poc/include/soc/smi.h       | 182 ++++++++
 src/soc/amd/turin_poc/include/soc/smu.h       |  23 +
 src/soc/amd/turin_poc/include/soc/soc_chip.h  |   8 +
 .../amd/turin_poc/include/soc/southbridge.h   | 122 ++++++
 src/soc/amd/turin_poc/include/soc/uart.h      |  10 +
 src/soc/amd/turin_poc/mca.c                   |  59 +++
 src/soc/amd/turin_poc/reset.c                 |  27 ++
 src/soc/amd/turin_poc/root_complex.c          |  51 +++
 src/soc/amd/turin_poc/smihandler.c            |  96 ++++
 src/soc/amd/turin_poc/uart.c                  |  38 ++
 41 files changed, 3218 insertions(+)
 create mode 100644 src/soc/amd/turin_poc/Kconfig
 create mode 100644 src/soc/amd/turin_poc/Makefile.mk
 create mode 100644 src/soc/amd/turin_poc/acpi.c
 create mode 100644 src/soc/amd/turin_poc/acpi/globalnvs.asl
 create mode 100644 src/soc/amd/turin_poc/acpi/mmio.asl
 create mode 100644 src/soc/amd/turin_poc/acpi/pci_int_defs.asl
 create mode 100644 src/soc/amd/turin_poc/acpi/soc.asl
 create mode 100644 src/soc/amd/turin_poc/aoac.c
 create mode 100644 src/soc/amd/turin_poc/chip.c
 create mode 100644 src/soc/amd/turin_poc/chip.h
 create mode 100644 src/soc/amd/turin_poc/chipset.cb
 create mode 100644 src/soc/amd/turin_poc/config.c
 create mode 100644 src/soc/amd/turin_poc/cpu.c
 create mode 100644 src/soc/amd/turin_poc/domain.c
 create mode 100644 src/soc/amd/turin_poc/early_fch.c
 create mode 100644 src/soc/amd/turin_poc/fch.c
 create mode 100644 src/soc/amd/turin_poc/fw.cfg
 create mode 100644 src/soc/amd/turin_poc/gpio.c
 create mode 100644 src/soc/amd/turin_poc/i2c.c
 create mode 100644 src/soc/amd/turin_poc/i3c.c
 create mode 100644 src/soc/amd/turin_poc/include/soc/amd_pci_int_defs.h
 create mode 100644 src/soc/amd/turin_poc/include/soc/aoac_defs.h
 create mode 100644 src/soc/amd/turin_poc/include/soc/cpu.h
 create mode 100644 src/soc/amd/turin_poc/include/soc/data_fabric.h
 create mode 100644 src/soc/amd/turin_poc/include/soc/gpio.h
 create mode 100644 src/soc/amd/turin_poc/include/soc/i2c.h
 create mode 100644 src/soc/amd/turin_poc/include/soc/iomap.h
 create mode 100644 src/soc/amd/turin_poc/include/soc/lpc.h
 create mode 100644 src/soc/amd/turin_poc/include/soc/msr.h
 create mode 100644 src/soc/amd/turin_poc/include/soc/nvs.h
 create mode 100644 src/soc/amd/turin_poc/include/soc/pci_devs.h
 create mode 100644 src/soc/amd/turin_poc/include/soc/smi.h
 create mode 100644 src/soc/amd/turin_poc/include/soc/smu.h
 create mode 100644 src/soc/amd/turin_poc/include/soc/soc_chip.h
 create mode 100644 src/soc/amd/turin_poc/include/soc/southbridge.h
 create mode 100644 src/soc/amd/turin_poc/include/soc/uart.h
 create mode 100644 src/soc/amd/turin_poc/mca.c
 create mode 100644 src/soc/amd/turin_poc/reset.c
 create mode 100644 src/soc/amd/turin_poc/root_complex.c
 create mode 100644 src/soc/amd/turin_poc/smihandler.c
 create mode 100644 src/soc/amd/turin_poc/uart.c

diff --git a/src/soc/amd/turin_poc/Kconfig b/src/soc/amd/turin_poc/Kconfig
new file mode 100644
index 0000000000..55af8c71e6
--- /dev/null
+++ b/src/soc/amd/turin_poc/Kconfig
@@ -0,0 +1,211 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
+config SOC_AMD_TURIN_POC
+	bool
+
+if SOC_AMD_TURIN_POC
+
+config SOC_SPECIFIC_OPTIONS
+	def_bool y
+	select ACPI_SOC_NVS
+	select ARCH_X86
+	select DEFAULT_X2APIC
+	select HAVE_ACPI_TABLES
+	select HAVE_X86_64_SUPPORT
+	select HAVE_SMI_HANDLER
+	select SOC_AMD_COMMON
+	select SOC_AMD_COMMON_BLOCK_ACPI
+	select SOC_AMD_COMMON_BLOCK_ACPIMMIO
+	select SOC_AMD_COMMON_BLOCK_ACPI_CPU_POWER_STATE
+	select SOC_AMD_COMMON_BLOCK_ACPI_IVRS
+	select SOC_AMD_COMMON_BLOCK_ACPI_MADT
+	select SOC_AMD_COMMON_BLOCK_AOAC
+	select SOC_AMD_COMMON_BLOCK_BANKED_GPIOS
+	select SOC_AMD_COMMON_BLOCK_CPUFREQ_FAM17H_19H
+	select SOC_AMD_COMMON_BLOCK_DATA_FABRIC
+	select SOC_AMD_COMMON_BLOCK_DATA_FABRIC_DOMAIN
+	select SOC_AMD_COMMON_BLOCK_DATA_FABRIC_MULTI_PCI_SEGMENT
+	select SOC_AMD_COMMON_BLOCK_DATA_FABRIC_EXTENDED_MMIO
+	select SOC_AMD_COMMON_BLOCK_HAS_ESPI
+	select SOC_AMD_COMMON_BLOCK_I2C
+	select SOC_AMD_COMMON_BLOCK_I3C
+	select SOC_AMD_COMMON_BLOCK_IOMMU
+	select SOC_AMD_COMMON_BLOCK_LPC
+	select SOC_AMD_COMMON_BLOCK_MCAX
+	select SOC_AMD_COMMON_BLOCK_NONCAR
+	select SOC_AMD_COMMON_BLOCK_PCI
+	select SOC_AMD_COMMON_BLOCK_PCI_MMCONF
+	select SOC_AMD_COMMON_BLOCK_PSP_GEN2
+	select SOC_AMD_COMMON_BLOCK_PSP_SPL
+	select SOC_AMD_COMMON_BLOCK_SMI
+	select SOC_AMD_COMMON_BLOCK_SMM
+	select SOC_AMD_COMMON_BLOCK_SMU
+	select SOC_AMD_COMMON_BLOCK_SMU_SX_ENTRY
+	select SOC_AMD_COMMON_BLOCK_SPI
+	select SOC_AMD_COMMON_BLOCK_SVI3
+	select SOC_AMD_COMMON_BLOCK_TSC
+	select SOC_AMD_COMMON_BLOCK_UART
+	select SOC_AMD_COMMON_BLOCK_UCODE
+	select SOC_AMD_COMMON_BLOCK_USE_ESPI
+	select SOC_AMD_OPENSIL
+	select OPENSIL_DRIVER
+
+config USE_X86_64_SUPPORT
+	default y
+
+config CHIPSET_DEVICETREE
+	string
+	default "soc/amd/turin_poc/chipset.cb"
+
+config DRIVERS_I2C_DESIGNWARE_CLOCK_MHZ
+	int
+	default 150
+
+config EARLY_RESERVED_DRAM_BASE
+	hex
+	default 0x7000000
+	help
+	  This variable defines the base address of the DRAM which is reserved
+	  for usage by coreboot in early stages (i.e. before ramstage is up).
+	  This memory gets reserved in BIOS tables to ensure that the OS does
+	  not use it, thus preventing corruption of OS memory in case of S3
+	  resume.
+
+config EARLYRAM_BSP_STACK_SIZE
+	hex
+	default 0x1000
+
+config MAX_CPUS
+	int
+	default 384
+
+config PSP_APOB_DRAM_ADDRESS
+	hex
+	default 0x7001000
+	help
+	  Location in DRAM where the PSP will copy the AGESA PSP Output
+	  Block.
+
+config PSP_APOB_DRAM_SIZE
+	hex
+	default 0x20000
+
+config PRERAM_CBMEM_CONSOLE_SIZE
+	hex
+	default 0x1600
+	help
+	  Increase this value if preram cbmem console is getting truncated
+
+config C_ENV_BOOTBLOCK_SIZE
+	hex
+	default 0x20000
+	help
+	  Sets the size of the bootblock stage that should be loaded in DRAM.
+	  This variable controls the DRAM allocation size in linker script
+	  for bootblock stage.
+
+config ROMSTAGE_ADDR
+	hex
+	default 0x7050000
+	help
+	  Sets the address in DRAM where romstage should be loaded.
+
+config ROMSTAGE_SIZE
+	hex
+	default 0x70000
+	help
+	  Sets the size of DRAM allocation for romstage in linker script.
+
+config ECAM_MMCONF_BASE_ADDRESS
+	hex
+	default 0xE0000000
+
+config ECAM_MMCONF_BUS_NUMBER
+	int
+	default 256
+
+menu "PSP Configuration Options"
+
+config AMDFW_CONFIG_FILE
+	string
+	default "src/soc/amd/turin_poc/fw.cfg"
+
+config PSP_DISABLE_POSTCODES
+	bool "Disable PSP post codes"
+	help
+	  Disables the output of port80 post codes from PSP.
+
+config PSP_INIT_ESPI
+	bool "Initialize eSPI in PSP Stage 2 Boot Loader"
+	help
+	  Select to initialize the eSPI controller in the PSP Stage 2 Boot
+	  Loader.
+
+config	PSP_UNLOCK_SECURE_DEBUG
+	bool
+	default y
+
+config HAVE_PSP_WHITELIST_FILE
+	bool "Include a debug whitelist file in PSP build"
+	default n
+	help
+	  Support secured unlock prior to reset using a whitelisted
+	  serial number. This feature requires a signed whitelist image
+	  and bootloader from AMD.
+
+	  If unsure, answer 'n'
+
+config PSP_WHITELIST_FILE
+	string "Debug whitelist file path"
+	depends on HAVE_PSP_WHITELIST_FILE
+
+config PSP_SOFTFUSE_BITS
+	string "PSP Soft Fuse bits to enable"
+	default ""
+	help
+	  Space separated list of Soft Fuse bits to enable.
+	  Bit 0:  Enable secure debug (Set by PSP_UNLOCK_SECURE_DEBUG)
+	  Bit 7:  Disable PSP postcodes on Renoir and newer chips only
+	          (Set by PSP_DISABLE_PORT80)
+	  Bit 15: PSP debug output destination:
+	          0=SoC MMIO UART, 1=IO port 0x3F8
+
+	  See #57299 (NDA) for additional bit definitions.
+endmenu
+
+config CONSOLE_UART_BASE_ADDRESS
+	depends on CONSOLE_SERIAL && AMD_SOC_CONSOLE_UART
+	hex
+	default 0xfedc9000 if UART_FOR_CONSOLE = 0
+	default 0xfedca000 if UART_FOR_CONSOLE = 1
+	default 0xfedce000 if UART_FOR_CONSOLE = 2
+
+config SMM_TSEG_SIZE
+	hex
+	default 0x800000
+
+config ACPI_SSDT_PSD_INDEPENDENT
+	bool "Allow core p-state independent transitions"
+	default y
+	help
+	  AMD recommends the ACPI _PSD object to be configured to cause
+	  cores to transition between p-states independently. A vendor may
+	  choose to generate _PSD object to allow cores to transition together.
+
+config ACPI_BERT
+	bool "Build ACPI BERT Table"
+	default y
+	depends on HAVE_ACPI_TABLES
+	help
+	  Report Machine Check errors identified in POST to the OS in an
+	  ACPI Boot Error Record Table.
+
+config ACPI_BERT_SIZE
+	hex
+	default 0x4000 if ACPI_BERT
+	default 0x0
+	help
+	  Specify the amount of DRAM reserved for gathering the data used to
+	  generate the ACPI table.
+
+endif # SOC_AMD_TURIN_POC
diff --git a/src/soc/amd/turin_poc/Makefile.mk b/src/soc/amd/turin_poc/Makefile.mk
new file mode 100644
index 0000000000..ab4d40f257
--- /dev/null
+++ b/src/soc/amd/turin_poc/Makefile.mk
@@ -0,0 +1,160 @@
+## SPDX-License-Identifier: GPL-2.0-only
+ifeq ($(CONFIG_SOC_AMD_TURIN_POC),y)
+
+all-y		+= reset.c
+all-y		+= config.c
+all-y		+= gpio.c
+all-y		+= i2c.c
+all-y		+= i3c.c
+all-y		+= uart.c
+
+bootblock-y	+= early_fch.c
+bootblock-y	+= aoac.c
+
+ramstage-y	+= acpi.c
+ramstage-y	+= aoac.c
+ramstage-y	+= chip.c
+ramstage-y	+= cpu.c
+ramstage-y	+= domain.c
+ramstage-y	+= fch.c
+ramstage-y	+= root_complex.c
+ramstage-y	+= smihandler.c
+ramstage-y	+= mca.c
+
+smm-y		+= root_complex.c
+smm-y		+= smihandler.c
+smm-$(CONFIG_DEBUG_SMI) += uart.c
+
+CPPFLAGS_common += -I$(src)/soc/amd/turin_poc/acpi
+CPPFLAGS_common += -I$(src)/soc/amd/turin_poc/include
+
+ifeq ($(call int-gt, $(CONFIG_ROM_SIZE) 0x1000000), 1)
+CBFSTOOL_ADD_CMD_OPTIONS+= --mmap 0:0xff000000:0x1000000
+endif
+
+#
+# PSP Directory Table items
+#
+# Certain ordering requirements apply, however these are ensured by amdfwtool.
+# For more information see "AMD Platform Security Processor BIOS Implementation
+# Guide for Server EPYC Processors" #57299
+#
+
+FIRMWARE_LOCATION=$(shell grep -e FIRMWARE_LOCATION $(CONFIG_AMDFW_CONFIG_FILE) | awk '{print $$2}')
+
+ifeq ($(CONFIG_PSP_DISABLE_POSTCODES),y)
+PSP_SOFTFUSE_BITS += 7
+endif
+
+ifeq ($(CONFIG_PSP_UNLOCK_SECURE_DEBUG),y)
+# Enable secure debug unlock
+PSP_SOFTFUSE_BITS += 0
+OPT_TOKEN_UNLOCK="--token-unlock"
+endif
+
+# Use additional Soft Fuse bits specified in Kconfig
+PSP_SOFTFUSE_BITS += $(call strip_quotes, $(CONFIG_PSP_SOFTFUSE_BITS))
+
+# type = 0x3a
+ifeq ($(CONFIG_HAVE_PSP_WHITELIST_FILE),y)
+PSP_WHITELIST_FILE=$(CONFIG_PSP_WHITELIST_FILE)
+endif
+
+# type = 0x55
+SPL_TABLE_FILE=$(CONFIG_SPL_TABLE_FILE)
+
+#
+# BIOS Directory Table items - proper ordering is managed by amdfwtool
+#
+
+# type = 0x60
+PSP_APCB_FILES=$(APCB_SOURCES) $(APCB1_SOURCES) $(APCB_SOURCES_RECOVERY) $(APCB_SOURCES_RECOVERY1) $(APCB_SOURCES_RECOVERY2)
+
+# type = 0x61
+PSP_APOB_BASE=$(CONFIG_PSP_APOB_DRAM_ADDRESS)
+
+# type = 0x62
+PSP_BIOSBIN_FILE=$(obj)/amd_biospsp.img
+PSP_ELF_FILE=$(objcbfs)/bootblock_fixed_data.elf
+PSP_BIOSBIN_SIZE=$(shell $(READELF_bootblock) -Wl $(PSP_ELF_FILE) | grep LOAD | awk '{print $$5}')
+PSP_BIOSBIN_DEST=$(shell $(READELF_bootblock) -Wl $(PSP_ELF_FILE) | grep LOAD | awk '{print $$3}')
+
+# Helper function to return a value with given bit set
+# Soft Fuse type = 0xb - See #57299 (NDA) for bit definitions.
+set-bit=$(call int-shift-left, 1 $(call _toint,$1))
+PSP_SOFTFUSE=$(shell A=$(call int-add, \
+		$(foreach bit,$(sort $(PSP_SOFTFUSE_BITS)),$(call set-bit,$(bit)))); printf "0x%x" $$A)
+
+#
+# Build the arguments to amdfwtool (order is unimportant).  Missing file names
+# result in empty OPT_ variables, i.e. the argument is not passed to amdfwtool.
+#
+
+add_opt_prefix=$(if $(call strip_quotes, $(1)), $(2) $(call strip_quotes, $(1)), )
+
+OPT_PSP_APCB_FILES= $(if $(APCB_SOURCES), --instance 0 --apcb $(APCB_SOURCES)) \
+                    $(if $(APCB_SOURCES1), --instance 1 --apcb $(APCB_SOURCES1)) \
+                    $(if $(APCB_SOURCES_RECOVERY), --instance 10 --apcb $(APCB_SOURCES_RECOVERY)) \
+                    $(if $(APCB_SOURCES_RECOVERY1), --instance 18 --apcb $(APCB_SOURCES_RECOVERY1)) \
+                    $(if $(APCB_SOURCES_RECOVERY2), --instance 19 --apcb $(APCB_SOURCES_RECOVERY2)) \
+                    $(if $(APCB_SOURCES_68), --instance 18 --apcb $(APCB_SOURCES_68))
+
+OPT_APOB_ADDR=$(call add_opt_prefix, $(PSP_APOB_BASE), --apob-base)
+OPT_PSP_BIOSBIN_FILE=$(call add_opt_prefix, $(PSP_BIOSBIN_FILE), --bios-bin)
+OPT_PSP_BIOSBIN_DEST=$(call add_opt_prefix, $(PSP_BIOSBIN_DEST), --bios-bin-dest)
+OPT_PSP_BIOSBIN_SIZE=$(call add_opt_prefix, $(PSP_BIOSBIN_SIZE), --bios-uncomp-size)
+
+OPT_EFS_SPI_READ_MODE=$(call add_opt_prefix, $(CONFIG_EFS_SPI_READ_MODE), --spi-read-mode)
+OPT_EFS_SPI_SPEED=$(call add_opt_prefix, $(CONFIG_EFS_SPI_SPEED), --spi-speed)
+OPT_EFS_SPI_MICRON_FLAG=$(call add_opt_prefix, $(CONFIG_EFS_SPI_MICRON_FLAG), --spi-micron-flag)
+OPT_PSP_SOFTFUSE=$(call add_opt_prefix, $(PSP_SOFTFUSE), --soft-fuse)
+
+OPT_WHITELIST_FILE=$(call add_opt_prefix, $(PSP_WHITELIST_FILE), --whitelist)
+OPT_SPL_TABLE_FILE=$(call add_opt_prefix, $(SPL_TABLE_FILE), --spl-table)
+
+AMDFW_COMMON_ARGS=$(OPT_PSP_APCB_FILES) \
+		$(OPT_APOB_ADDR) \
+		$(OPT_DEBUG_AMDFWTOOL) \
+		$(OPT_PSP_BIOSBIN_FILE) \
+		$(OPT_PSP_BIOSBIN_DEST) \
+		$(OPT_PSP_BIOSBIN_SIZE) \
+		$(OPT_PSP_SOFTFUSE) \
+		--use-pspsecureos \
+		$(OPT_TOKEN_UNLOCK) \
+		$(OPT_WHITELIST_FILE) \
+		$(OPT_SPL_TABLE_FILE) \
+		$(OPT_EFS_SPI_READ_MODE) \
+		$(OPT_EFS_SPI_SPEED) \
+		$(OPT_EFS_SPI_MICRON_FLAG) \
+		--config $(CONFIG_AMDFW_CONFIG_FILE) \
+		--flashsize 0x1000000
+
+$(obj)/amdfw.rom:	$(call strip_quotes, $(PSP_BIOSBIN_FILE)) \
+			$$(PSP_APCB_FILES) \
+			$(DEP_FILES) \
+			$(AMDFWTOOL) \
+			$(obj)/fmap_config.h \
+			$(objcbfs)/bootblock_fixed_data.elf # this target also creates the .map file
+	$(if $(PSP_APCB_FILES), ,$(error APCB_SOURCES is not set))
+	rm -f $@
+	@printf "    AMDFWTOOL  $(subst $(obj)/,,$(@))\n"
+	$(AMDFWTOOL) \
+		$(AMDFW_COMMON_ARGS) \
+		--location $(CONFIG_AMD_FWM_POSITION) \
+		--multilevel \
+		--output $@
+
+#
+# Extracts everything from the ELF's first PT_LOAD area and compresses it.
+# This discards everything before PT_LOAD, every symbol, debug information
+# and relocations. The generated binary is expected to run at PSP_BIOSBIN_DEST
+# with a maximum size of PSP_BIOSBIN_SIZE. The entrypoint is fixed at
+# PSP_BIOSBIN_DEST + PSP_BIOSBIN_SIZE - 0x10.
+#
+$(PSP_BIOSBIN_FILE): $(PSP_ELF_FILE) $(AMDCOMPRESS)
+	rm -f $@
+	@printf "    AMDCOMPRS  $(subst $(obj)/,,$(@))\n"
+	$(AMDCOMPRESS) --infile $(PSP_ELF_FILE) --outfile $@ --compress \
+		--maxsize $(PSP_BIOSBIN_SIZE)
+
+endif
diff --git a/src/soc/amd/turin_poc/acpi.c b/src/soc/amd/turin_poc/acpi.c
new file mode 100644
index 0000000000..9091050ba5
--- /dev/null
+++ b/src/soc/amd/turin_poc/acpi.c
@@ -0,0 +1,66 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+/* ACPI - create the Fixed ACPI Description Tables (FADT) */
+
+#include <acpi/acpi.h>
+#include <amdblocks/acpi.h>
+#include <amdblocks/acpimmio.h>
+#include <amdblocks/cpu.h>
+#include <arch/ioapic.h>
+#include <device/device.h>
+#include <drivers/amd/opensil/opensil.h>
+
+void acpi_fill_fadt(acpi_fadt_t *fadt)
+{
+	/* Fill in pm1_evt, pm1_cnt, pm_tmr, gpe0_blk from openSIL input structure */
+	amd_opensil_fill_fadt_io_ports(fadt);
+
+	fadt->pm1_evt_len = 4;	/* 32 bits */
+	fadt->pm1_cnt_len = 2;	/* 16 bits */
+	fadt->pm_tmr_len = 4;	/* 32 bits */
+	fadt->gpe0_blk_len = 8;	/* 64 bits */
+
+	fill_fadt_extended_pm_io(fadt);
+
+	fadt->iapc_boot_arch = ACPI_FADT_LEGACY_FREE; /* legacy free default */
+	fadt->flags |=	ACPI_FADT_WBINVD | /* See table 5-34 ACPI 6.3 spec */
+			ACPI_FADT_C1_SUPPORTED |
+			ACPI_FADT_S4_RTC_WAKE |
+			ACPI_FADT_32BIT_TIMER |
+			ACPI_FADT_PCI_EXPRESS_WAKE |
+			ACPI_FADT_PLATFORM_CLOCK |
+			ACPI_FADT_S4_RTC_VALID |
+			ACPI_FADT_REMOTE_POWER_ON;
+
+	fadt->x_firmware_ctl_l = 0;	/* set to 0 if firmware_ctrl is used */
+	fadt->x_firmware_ctl_h = 0;
+}
+
+unsigned long soc_acpi_write_tables(const struct device *device, unsigned long current,
+				    struct acpi_rsdp *rsdp)
+{
+	/* IVRS */
+	current = acpi_add_ivrs_table(current, rsdp);
+
+	return current;
+}
+
+/* There are only the following 2 C-states reported by the reference firmware */
+const acpi_cstate_t cstate_cfg_table[] = {
+	[0] = {
+		.ctype = 1,
+		.latency = 1,
+		.power = 0,
+	},
+	[1] = {
+		.ctype = 2,
+		.latency = 0x12,
+		.power = 0,
+	},
+};
+
+const acpi_cstate_t *get_cstate_config_data(size_t *size)
+{
+	*size = ARRAY_SIZE(cstate_cfg_table);
+	return cstate_cfg_table;
+}
diff --git a/src/soc/amd/turin_poc/acpi/globalnvs.asl b/src/soc/amd/turin_poc/acpi/globalnvs.asl
new file mode 100644
index 0000000000..4526204df8
--- /dev/null
+++ b/src/soc/amd/turin_poc/acpi/globalnvs.asl
@@ -0,0 +1,13 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+/*
+ * NOTE: The layout of the GNVS structure below must match the layout in
+ * soc/amd/turin_poc/include/soc/nvs.h !!!
+ */
+
+Field (GNVS, ByteAcc, NoLock, Preserve)
+{
+	/* Miscellaneous */
+	PM1I,	64,	// 0x00 - 0x07 - System Wake Source - PM1 Index
+	GPEI,	64,	// 0x08 - 0x0f - GPE Wake Source
+}
diff --git a/src/soc/amd/turin_poc/acpi/mmio.asl b/src/soc/amd/turin_poc/acpi/mmio.asl
new file mode 100644
index 0000000000..9b5e1d2d2b
--- /dev/null
+++ b/src/soc/amd/turin_poc/acpi/mmio.asl
@@ -0,0 +1,414 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <soc/amd/common/acpi/aoac.asl>
+#include <soc/aoac_defs.h>
+#include <soc/gpio.h>
+#include <soc/iomap.h>
+#include <amdblocks/acpimmio_map.h>
+
+Device (AAHB)
+{
+	Name (_HID, "AAHB0000")
+	Name (_UID, 0x0)
+	Name (_CRS, ResourceTemplate()
+	{
+		Memory32Fixed (ReadWrite, ALINK_AHB_ADDRESS, 0x2000)
+	})
+	Name (_STA, 0xb)
+}
+
+Device (GPIO)
+{
+	Name (_HID, GPIO_DEVICE_NAME)
+	Name (_CID, GPIO_DEVICE_NAME)
+	Name (_UID, 0)
+	Name (_DDN, GPIO_DEVICE_DESC)
+
+	Method (_CRS, 0) {
+		Local0 = ResourceTemplate() {
+			Interrupt (
+				ResourceConsumer,
+				Level,
+				ActiveLow,
+				Shared, , , IRQR)
+			{ 0 }
+			Memory32Fixed (ReadWrite, ACPIMMIO_GPIO0_BASE, 0x400)
+		}
+		CreateDWordField (Local0, IRQR._INT, IRQN)
+		If (PICM) {
+			IRQN = IGPI
+		} Else {
+			IRQN = PGPI
+		}
+		If (IRQN == 0x1f || IRQN == 0) {
+			Return (ResourceTemplate() {
+				Memory32Fixed (ReadWrite, ACPIMMIO_GPIO0_BASE, 0x400)
+			})
+		} Else {
+			Return (Local0)
+		}
+	}
+
+	Method (_STA, 0x0, NotSerialized)
+	{
+		Return (0x0F)
+	}
+}
+
+Device (FUR0)
+{
+	Name (_HID, "AMDI0020")
+	Name (_UID, 0x0)
+	Method (_CRS, 0) {
+		Local0 = ResourceTemplate() {
+			Interrupt (
+				ResourceConsumer,
+				Edge,
+				ActiveHigh,
+				Exclusive, , , IRQR)
+			{ 0 }
+			Memory32Fixed (ReadWrite, APU_UART0_BASE, 0x1000)
+		}
+		CreateDWordField (Local0, IRQR._INT, IRQN)
+		If (PICM) {
+			IRQN = IUA0
+		} Else {
+			IRQN = PUA0
+		}
+		If (IRQN == 0x1f) {
+			Return (ResourceTemplate() {
+				Memory32Fixed (ReadWrite, APU_UART0_BASE, 0x1000)
+			})
+		} Else {
+			Return (Local0)
+		}
+	}
+
+	Name (STAT, 0x0)
+	Method (_STA, 0x0, NotSerialized)
+	{
+		Return (STAT)
+	}
+
+	AOAC_DEVICE(FCH_AOAC_DEV_UART0, 0)
+}
+
+Device (FUR1) {
+	Name (_HID, "AMDI0020")
+	Name (_UID, 0x1)
+	Method (_CRS, 0) {
+		Local0 = ResourceTemplate() {
+			Interrupt (
+				ResourceConsumer,
+				Edge,
+				ActiveHigh,
+				Exclusive, , , IRQR)
+			{ 0 }
+			Memory32Fixed (ReadWrite, APU_UART1_BASE, 0x1000)
+		}
+		CreateDWordField (Local0, IRQR._INT, IRQN)
+		If (PICM) {
+			IRQN = IUA1
+		} Else {
+			IRQN = PUA1
+		}
+		If (IRQN == 0x1f) {
+			Return (ResourceTemplate() {
+				Memory32Fixed (ReadWrite, APU_UART1_BASE, 0x1000)
+			})
+		} Else {
+			Return (Local0)
+		}
+	}
+
+	Name (STAT, 0x0)
+	Method (_STA, 0x0, NotSerialized)
+	{
+		Return (STAT)
+	}
+
+	AOAC_DEVICE(FCH_AOAC_DEV_UART1, 0)
+}
+
+Device (FUR2) {
+	Name (_HID, "AMDI0020")
+	Name (_UID, 0x2)
+	Method (_CRS, 0) {
+		Local0 = ResourceTemplate() {
+			Interrupt (
+				ResourceConsumer,
+				Edge,
+				ActiveHigh,
+				Exclusive, , , IRQR)
+			{ 0 }
+			Memory32Fixed (ReadWrite, APU_UART2_BASE, 0x1000)
+		}
+		CreateDWordField (Local0, IRQR._INT, IRQN)
+		If (PICM) {
+			IRQN = IUA2
+		} Else {
+			IRQN = PUA2
+		}
+		If (IRQN == 0x1f) {
+			Return (ResourceTemplate() {
+				Memory32Fixed (ReadWrite, APU_UART2_BASE, 0x1000)
+			})
+		} Else {
+			Return (Local0)
+		}
+	}
+
+	Name (STAT, 0x0)
+	Method (_STA, 0x0, NotSerialized)
+	{
+		Return (STAT)
+	}
+
+	AOAC_DEVICE(FCH_AOAC_DEV_UART2, 0)
+}
+
+Device (I2C0) {
+	Name (_HID, "AMDI0010")
+	Name (_UID, 0x0)
+	Method (_CRS, 0) {
+		Local0 = ResourceTemplate() {
+			Interrupt (
+				ResourceConsumer,
+				Edge,
+				ActiveHigh,
+				Exclusive, , , IRQR)
+			{ 0 }
+			Memory32Fixed (ReadWrite, APU_I2C0_BASE, 0x1000)
+		}
+		CreateDWordField (Local0, IRQR._INT, IRQN)
+		If (PICM) {
+			IRQN = II20
+		} Else {
+			IRQN = PI20
+		}
+		If (IRQN == 0x1f) {
+			Return (ResourceTemplate() {
+				Memory32Fixed (ReadWrite, APU_I2C0_BASE, 0x1000)
+			})
+		} Else {
+			Return (Local0)
+		}
+	}
+
+	Name (STAT, 0x0)
+	Method (_STA, 0x0, NotSerialized)
+	{
+		Return (STAT)
+	}
+
+	AOAC_DEVICE(FCH_AOAC_DEV_I2C0, 0)
+}
+
+Device (I2C1) {
+	Name (_HID, "AMDI0010")
+	Name (_UID, 0x1)
+	Method (_CRS, 0) {
+		Local0 = ResourceTemplate() {
+			Interrupt (
+				ResourceConsumer,
+				Edge,
+				ActiveHigh,
+				Exclusive, , , IRQR)
+			{ 0 }
+			Memory32Fixed (ReadWrite, APU_I2C1_BASE, 0x1000)
+		}
+		CreateDWordField (Local0, IRQR._INT, IRQN)
+		If (PICM) {
+			IRQN = II21
+		} Else {
+			IRQN = PI21
+		}
+		If (IRQN == 0x1f) {
+			Return (ResourceTemplate() {
+				Memory32Fixed (ReadWrite, APU_I2C1_BASE, 0x1000)
+			})
+		} Else {
+			Return (Local0)
+		}
+	}
+
+	Name (STAT, 0x0)
+	Method (_STA, 0x0, NotSerialized)
+	{
+		Return (STAT)
+	}
+
+	AOAC_DEVICE(FCH_AOAC_DEV_I2C1, 0)
+}
+
+Device (I2C2) {
+	Name (_HID, "AMDI0010")
+	Name (_UID, 0x2)
+	Method (_CRS, 0) {
+		Local0 = ResourceTemplate() {
+			Interrupt (
+				ResourceConsumer,
+				Edge,
+				ActiveHigh,
+				Exclusive, , , IRQR)
+			{ 0 }
+			Memory32Fixed (ReadWrite, APU_I2C2_BASE, 0x1000)
+		}
+		CreateDWordField (Local0, IRQR._INT, IRQN)
+		If (PICM) {
+			IRQN = II22
+		} Else {
+			IRQN = PI22
+		}
+		If (IRQN == 0x1f) {
+			Return (ResourceTemplate() {
+				Memory32Fixed (ReadWrite, APU_I2C2_BASE, 0x1000)
+			})
+		} Else {
+			Return (Local0)
+		}
+	}
+
+	Name (STAT, 0x0)
+	Method (_STA, 0x0, NotSerialized)
+	{
+		Return (STAT)
+	}
+
+	AOAC_DEVICE(FCH_AOAC_DEV_I2C2, 0)
+}
+
+Device (I2C3)
+{
+	Name (_HID, "AMDI0010")
+	Name (_UID, 0x3)
+	Method (_CRS, 0) {
+		Local0 = ResourceTemplate() {
+			Interrupt (
+				ResourceConsumer,
+				Edge,
+				ActiveHigh,
+				Exclusive, , , IRQR)
+			{ 0 }
+			Memory32Fixed (ReadWrite, APU_I2C3_BASE, 0x1000)
+		}
+		CreateDWordField (Local0, IRQR._INT, IRQN)
+		If (PICM) {
+			IRQN = II23
+		} Else {
+			IRQN = PI23
+		}
+		If (IRQN == 0x1f) {
+			Return (ResourceTemplate() {
+				Memory32Fixed (ReadWrite, APU_I2C3_BASE, 0x1000)
+			})
+		} Else {
+			Return (Local0)
+		}
+	}
+
+	Name (STAT, 0x0)
+	Method (_STA, 0x0, NotSerialized)
+	{
+		Return (STAT)
+	}
+
+	AOAC_DEVICE(FCH_AOAC_DEV_I2C3, 0)
+}
+
+Device (I2C4)
+{
+	Name (_HID, "AMDI0010")
+	Name (_UID, 0x4)
+	Method (_CRS, 0) {
+		Local0 = ResourceTemplate() {
+			Interrupt (
+				ResourceConsumer,
+				Edge,
+				ActiveHigh,
+				Exclusive, , , IRQR)
+			{ 0 }
+			Memory32Fixed (ReadWrite, APU_I2C4_BASE, 0x1000)
+		}
+		CreateDWordField (Local0, IRQR._INT, IRQN)
+		If (PICM) {
+			IRQN = II24
+		} Else {
+			IRQN = PI24
+		}
+		If (IRQN == 0x1f) {
+			Return (ResourceTemplate() {
+				Memory32Fixed (ReadWrite, APU_I2C4_BASE, 0x1000)
+			})
+		} Else {
+			Return (Local0)
+		}
+	}
+
+	Name (STAT, 0x0)
+	Method (_STA, 0x0, NotSerialized)
+	{
+		Return (STAT)
+	}
+
+	AOAC_DEVICE(FCH_AOAC_DEV_I2C4, 0)
+}
+
+Device (I2C5)
+{
+	Name (_HID, "AMDI0010")
+	Name (_UID, 0x5)
+	Method (_CRS, 0) {
+		Local0 = ResourceTemplate() {
+			Interrupt (
+				ResourceConsumer,
+				Edge,
+				ActiveHigh,
+				Exclusive, , , IRQR)
+			{ 0 }
+			Memory32Fixed (ReadWrite, APU_I2C5_BASE, 0x1000)
+		}
+		CreateDWordField (Local0, IRQR._INT, IRQN)
+		If (PICM) {
+			IRQN = II25
+		} Else {
+			IRQN = PI25
+		}
+		If (IRQN == 0x1f) {
+			Return (ResourceTemplate() {
+				Memory32Fixed (ReadWrite, APU_I2C5_BASE, 0x1000)
+			})
+		} Else {
+			Return (Local0)
+		}
+	}
+
+	Name (STAT, 0x0)
+	Method (_STA, 0x0, NotSerialized)
+	{
+		Return (STAT)
+	}
+
+	AOAC_DEVICE(FCH_AOAC_DEV_I2C5, 0)
+}
+
+Device (MISC)
+{
+	Name (_HID, "AMD0040")
+	Name (_UID, 0x3)
+	Name (_CRS, ResourceTemplate() {
+		Memory32Fixed (ReadWrite, ACPIMMIO_MISC_BASE, 0x100)
+	})
+	Name (_DSD, Package ()
+	{
+		ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+		Package ()
+		{
+			Package () { "is-rv", 1 },
+		},
+	})
+	Method (_STA, 0x0, NotSerialized)
+	{
+		Return (0x0B)
+	}
+}
diff --git a/src/soc/amd/turin_poc/acpi/pci_int_defs.asl b/src/soc/amd/turin_poc/acpi/pci_int_defs.asl
new file mode 100644
index 0000000000..22455c5cae
--- /dev/null
+++ b/src/soc/amd/turin_poc/acpi/pci_int_defs.asl
@@ -0,0 +1,98 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+/* PCI IRQ mapping registers, C00h-C01h. */
+OperationRegion(PRQM, SystemIO, 0x00000c00, 0x00000002)
+	Field(PRQM, ByteAcc, NoLock, Preserve) {
+	PRQI, 0x00000008,
+	PRQD, 0x00000008,  /* Offset: 1h */
+}
+
+/*
+ * All PIC indexes are prefixed with P.
+ * All IO-APIC indexes are prefixed with I.
+ */
+IndexField(PRQI, PRQD, ByteAcc, NoLock, Preserve) {
+	PIRA, 0x00000008,	/* Index 0: INTA */
+	PIRB, 0x00000008,	/* Index 1: INTB */
+	PIRC, 0x00000008,	/* Index 2: INTC */
+	PIRD, 0x00000008,	/* Index 3: INTD */
+	PIRE, 0x00000008,	/* Index 4: INTE */
+	PIRF, 0x00000008,	/* Index 5: INTF */
+	PIRG, 0x00000008,	/* Index 6: INTG */
+	PIRH, 0x00000008,	/* Index 7: INTH */
+
+	Offset (0x10),
+	PSCI, 0x00000008,	/* Index 0x10: SCI */
+	PSB0, 0x00000008,	/* Index 0x11: SMBUS0 */
+	PASF, 0x00000008,	/* Index 0x12: ASF */
+
+	Offset (0x16),
+	PPMN, 0x00000008,	/* Index 0x16: PerMon */
+
+	Offset (0x1a),
+	PSIO, 0x00000008,	/* Index 0x1A: SDIO */
+
+	Offset (0x50),
+	PGP0, 0x00000008,	/* Index 0x50: GPP0 */
+	PGP1, 0x00000008,	/* Index 0x51: GPP1 */
+	PGP2, 0x00000008,	/* Index 0x52: GPP2 */
+	PGP3, 0x00000008,	/* Index 0x53: GPP3 */
+
+	Offset (0x62),
+	PGPI, 0x00000008,	/* Index 0x62: GPIO */
+
+	Offset (0x70),
+	PI20, 0x00000008,	/* Index 0x70: I2C0/I3C0 */
+	PI21, 0x00000008,	/* Index 0x71: I2C1/I3C1 */
+	PI22, 0x00000008,	/* Index 0x72: I2C2/I3C2 */
+	PI23, 0x00000008,	/* Index 0x73: I2C3/I3C3 */
+	PUA0, 0x00000008,	/* Index 0x74: UART0 */
+	PUA1, 0x00000008,	/* Index 0x75: UART1 */
+	PI24, 0x00000008,	/* Index 0x76: I2C4 */
+	PI25, 0x00000008,	/* Index 0x77: I2C5 */
+	PUA2, 0x00000008,	/* Index 0x78: UART2 */
+	PUA3, 0x00000008,	/* Index 0x79: UART3 */
+
+	/* IO-APIC IRQs */
+	Offset (0x80),
+	IORA, 0x00000008,	/* Index 0x80: INTA */
+	IORB, 0x00000008,	/* Index 0x81: INTB */
+	IORC, 0x00000008,	/* Index 0x82: INTC */
+	IORD, 0x00000008,	/* Index 0x83: INTD */
+	IORE, 0x00000008,	/* Index 0x84: INTE */
+	IORF, 0x00000008,	/* Index 0x85: INTF */
+	IORG, 0x00000008,	/* Index 0x86: INTG */
+	IORH, 0x00000008,	/* Index 0x87: INTH */
+
+	Offset (0x90),
+	ISCI, 0x00000008,	/* Index 0x90: SCI */
+	ISB0, 0x00000008,	/* Index 0x91: SMBUS0 */
+	IASF, 0x00000008,	/* Index 0x92: ASF */
+
+	Offset (0x96),
+	IPMN, 0x00000008,	/* Index 0x96: PerMon */
+
+	Offset (0x9a),
+	ISIO, 0x00000008,	/* Index 0x9A: SDIO */
+
+	Offset (0xD0),
+	IGP0, 0x00000008,	/* Index 0xD0: GPP0 */
+	IGP1, 0x00000008,	/* Index 0xD1: GPP1 */
+	IGP2, 0x00000008,	/* Index 0xD2: GPP2 */
+	IGP3, 0x00000008,	/* Index 0xD3: GPP3 */
+
+	Offset (0xE2),
+	IGPI, 0x00000008,	/* Index 0xE2: GPIO */
+
+	Offset (0xF0),
+	II20, 0x00000008,	/* Index 0xF0: I2C0/I3C0 */
+	II21, 0x00000008,	/* Index 0xF1: I2C1/I3C1 */
+	II22, 0x00000008,	/* Index 0xF2: I2C2/I3C2 */
+	II23, 0x00000008,	/* Index 0xF3: I2C3/I3C3 */
+	IUA0, 0x00000008,	/* Index 0xF4: UART0 */
+	IUA1, 0x00000008,	/* Index 0xF5: UART1 */
+	II24, 0x00000008,	/* Index 0xF6: I2C4 */
+	II25, 0x00000008,	/* Index 0xF7: I2C5 */
+	IUA2, 0x00000008,	/* Index 0xF8: UART2 */
+	IUA3, 0x00000008,	/* Index 0xF9: UART3 */
+}
diff --git a/src/soc/amd/turin_poc/acpi/soc.asl b/src/soc/amd/turin_poc/acpi/soc.asl
new file mode 100644
index 0000000000..75344dc325
--- /dev/null
+++ b/src/soc/amd/turin_poc/acpi/soc.asl
@@ -0,0 +1,39 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <soc/amd/common/acpi/pci_root.asl>
+#include "globalnvs.asl"
+
+Scope(\_SB) {
+	/* global utility methods expected within the \_SB scope */
+	#include <arch/x86/acpi/globutil.asl>
+
+	#include <soc/amd/common/acpi/gpio_bank_lib.asl>
+
+	#include <soc/amd/common/acpi/osc.asl>
+
+	#include "pci_int_defs.asl"
+
+	#include "mmio.asl"
+
+	ROOT_BRIDGE(S0B0)
+	ROOT_BRIDGE(S0B1)
+	ROOT_BRIDGE(S0B2)
+	ROOT_BRIDGE(S0B3)
+} /* End \_SB scope */
+
+#include <soc/amd/common/acpi/alib.asl>
+
+#include <soc/amd/common/acpi/platform.asl>
+
+#include <soc/amd/common/acpi/sleepstates.asl>
+
+/*
+ * Platform Notify
+ *
+ * This is called by soc/amd/common/acpi/platform.asl.
+ */
+Method (PNOT)
+{
+	/* Report AC/DC state to ALIB using WAL1() */
+	\WAL1 ()
+}
diff --git a/src/soc/amd/turin_poc/aoac.c b/src/soc/amd/turin_poc/aoac.c
new file mode 100644
index 0000000000..53ba88f1b9
--- /dev/null
+++ b/src/soc/amd/turin_poc/aoac.c
@@ -0,0 +1,32 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <stdint.h>
+#include <amdblocks/acpimmio.h>
+#include <amdblocks/aoac.h>
+#include <soc/aoac_defs.h>
+#include <soc/southbridge.h>
+#include <delay.h>
+
+#define FCH_AOAC_UART_FOR_CONSOLE \
+		(CONFIG_UART_FOR_CONSOLE == 0 ? FCH_AOAC_DEV_UART0 \
+		: CONFIG_UART_FOR_CONSOLE == 1 ? FCH_AOAC_DEV_UART1 \
+		: CONFIG_UART_FOR_CONSOLE == 2 ? FCH_AOAC_DEV_UART2 \
+		: -1)
+#if CONFIG(AMD_SOC_CONSOLE_UART) && FCH_AOAC_UART_FOR_CONSOLE == -1
+# error Unsupported UART_FOR_CONSOLE chosen
+#endif
+
+void wait_for_aoac_enabled(unsigned int dev)
+{
+	while (!is_aoac_device_enabled(dev))
+		udelay(100);
+}
+
+void enable_aoac_devices(void)
+{
+	if (CONFIG(AMD_SOC_CONSOLE_UART))
+		power_on_aoac_device(FCH_AOAC_UART_FOR_CONSOLE);
+
+	if (CONFIG(AMD_SOC_CONSOLE_UART))
+		wait_for_aoac_enabled(FCH_AOAC_UART_FOR_CONSOLE);
+}
diff --git a/src/soc/amd/turin_poc/chip.c b/src/soc/amd/turin_poc/chip.c
new file mode 100644
index 0000000000..344617d52e
--- /dev/null
+++ b/src/soc/amd/turin_poc/chip.c
@@ -0,0 +1,28 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <amdblocks/acpi.h>
+#include <amdblocks/data_fabric.h>
+#include <device/device.h>
+#include <drivers/amd/opensil/opensil.h>
+#include <soc/southbridge.h>
+
+static void soc_init(void *chip_info)
+{
+	default_dev_ops_root.write_acpi_tables = soc_acpi_write_tables;
+
+	amd_opensil_silicon_init();
+
+	data_fabric_print_mmio_conf();
+
+	fch_init(chip_info);
+}
+
+static void soc_final(void *chip_info)
+{
+}
+
+struct chip_operations soc_amd_turin_poc_ops = {
+	.name = "AMD Turin SoC Proof of Concept",
+	.init = soc_init,
+	.final = soc_final,
+};
diff --git a/src/soc/amd/turin_poc/chip.h b/src/soc/amd/turin_poc/chip.h
new file mode 100644
index 0000000000..f08f348f15
--- /dev/null
+++ b/src/soc/amd/turin_poc/chip.h
@@ -0,0 +1,71 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef __TURIN_POC_CHIP_H__
+#define __TURIN_POC_CHIP_H__
+
+#include <amdblocks/chip.h>
+#include <amdblocks/i2c.h>
+#include <drivers/i2c/designware/dw_i2c.h>
+#include <soc/iomap.h>
+#include <types.h>
+
+struct usb31_phy_settings {
+	uint8_t rx_ana_iq_phase_adjust;
+	uint8_t rx_eq_delta_iq_ovrd_en;
+	uint8_t rx_eq_delta_iq_ovrd_val;
+	uint8_t rx_iq_phase_adjust;
+	uint8_t tx_vboost_lvl_en;
+	uint8_t tx_vboost_lvl;
+	uint8_t rx_vref_ctrl_en;
+	uint8_t rx_vref_ctrl;
+	uint8_t tx_vboost_lvl_en_x;
+	uint8_t tx_vboost_lvl_x;
+	uint8_t rx_vref_ctrl_en_x;
+	uint8_t rx_vref_ctrl_x;
+};
+
+struct soc_usb_config {
+	uint8_t xhci0_enable : 1;
+	uint8_t xhci1_enable : 1;
+	struct {
+		uint8_t port0 : 4;
+		uint8_t port1 : 4;
+		uint8_t port2 : 4;
+		uint8_t port3 : 4;
+		uint8_t port4 : 4;
+		uint8_t port5 : 4;
+		uint8_t port6 : 4;
+		uint8_t port7 : 4;
+	} usb2_oc_pins[2];
+	struct {
+		uint8_t port0 : 4;
+		uint8_t port1 : 4;
+		uint8_t port2 : 4;
+		uint8_t port3 : 4;
+	}  usb3_oc_pins[2];
+	bool polarity_cfg_low;
+	union {
+		struct {
+			uint8_t port0 : 2;
+			uint8_t port1 : 2;
+			uint8_t port2 : 2; /* Broken in OpenSIL */
+			uint8_t port3 : 2; /* Broken in OpenSIL */
+		};
+		uint8_t raw;
+	} usb3_force_gen1;
+	bool usb31_phy_enable;
+	struct usb31_phy_settings usb31_phy[8];
+	bool s1_usb31_phy_enable;
+	struct usb31_phy_settings s1_usb31_phy[8];
+};
+
+struct soc_amd_turin_poc_config {
+	struct soc_amd_common_config common_config;
+
+	u8 i2c_scl_reset;
+	struct dw_i2c_bus_config i2c[I2C_CTRLR_COUNT];
+
+	struct soc_usb_config usb;
+};
+
+#endif /* __TURIN_POC_CHIP_H__ */
diff --git a/src/soc/amd/turin_poc/chipset.cb b/src/soc/amd/turin_poc/chipset.cb
new file mode 100644
index 0000000000..399d3530fc
--- /dev/null
+++ b/src/soc/amd/turin_poc/chipset.cb
@@ -0,0 +1,394 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
+chip soc/amd/turin_poc
+	device cpu_cluster 0 on ops amd_cpu_bus_ops end
+
+	# OC pins
+	register "usb.usb2_oc_pins[0]" = "{ 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf }"
+	register "usb.usb2_oc_pins[1]" = "{ 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf }"
+	register "usb.usb3_oc_pins[0]" = "{ 0xf, 0xf, 0xf, 0xf }"
+	register "usb.usb3_oc_pins[1]" = "{ 0xf, 0xf, 0xf, 0xf }"
+
+	device domain 0 on
+		ops turin_pci_domain_ops
+		device pci 00.0 alias gnb_0 on end
+		device pci 00.2 alias iommu_0 off ops amd_iommu_ops end
+		device pci 00.3 alias rcec_0 off end
+
+		device pci 01.0 on end # Dummy device function, do not disable
+		chip drivers/amd/opensil/mpio
+			device pci 01.1 alias gpp_bridge_0_0_a off end
+		end
+		chip drivers/amd/opensil/mpio
+			device pci 01.2 alias gpp_bridge_0_1_a off end
+		end
+		chip drivers/amd/opensil/mpio
+			device pci 01.3 alias gpp_bridge_0_2_a off end
+		end
+		chip drivers/amd/opensil/mpio
+			device pci 01.4 alias gpp_bridge_0_3_a off end
+		end
+		chip drivers/amd/opensil/mpio
+			device pci 01.5 alias gpp_bridge_0_4_a off end
+		end
+		chip drivers/amd/opensil/mpio
+			device pci 01.6 alias gpp_bridge_0_5_a off end
+		end
+		chip drivers/amd/opensil/mpio
+			device pci 01.7 alias gpp_bridge_0_6_a off end
+		end
+
+		device pci 02.0 on end # Dummy device function, do not disable
+		chip drivers/amd/opensil/mpio
+			device pci 02.1 alias gpp_bridge_0_7_a off end
+		end
+		chip drivers/amd/opensil/mpio
+			device pci 02.2 alias gpp_bridge_0_8_a off end
+		end
+
+		device pci 03.0 on end # Dummy device function, do not disable
+		chip drivers/amd/opensil/mpio
+			device pci 03.1 alias gpp_bridge_0_0_b off end
+		end
+		chip drivers/amd/opensil/mpio
+			device pci 03.2 alias gpp_bridge_0_1_b off end
+		end
+		chip drivers/amd/opensil/mpio
+			device pci 03.3 alias gpp_bridge_0_2_b off end
+		end
+		chip drivers/amd/opensil/mpio
+			device pci 03.4 alias gpp_bridge_0_3_b off end
+		end
+		chip drivers/amd/opensil/mpio
+			device pci 03.5 alias gpp_bridge_0_4_b off end
+		end
+		chip drivers/amd/opensil/mpio
+			device pci 03.6 alias gpp_bridge_0_5_b off end
+		end
+		chip drivers/amd/opensil/mpio
+			device pci 03.7 alias gpp_bridge_0_6_b off end
+		end
+
+		device pci 04.0 on end # Dummy device function, do not disable
+		chip drivers/amd/opensil/mpio
+			device pci 04.1 alias gpp_bridge_0_7_b off end
+		end
+		chip drivers/amd/opensil/mpio
+			device pci 04.2 alias gpp_bridge_0_8_b off end
+		end
+
+		device pci 05.0 on end # Dummy device function, do not disable
+		chip drivers/amd/opensil/mpio
+			device pci 05.1 alias gpp_bridge_0_0_c off end
+		end
+		chip drivers/amd/opensil/mpio
+			device pci 05.2 alias gpp_bridge_0_1_c off end
+		end
+		chip drivers/amd/opensil/mpio
+			device pci 05.3 alias gpp_bridge_0_2_c off end
+		end
+		chip drivers/amd/opensil/mpio
+			device pci 05.4 alias gpp_bridge_0_3_c off end
+		end
+
+		device pci 07.0 on end # Dummy device function, do not disable
+		device pci 07.1 alias gpp_bridge_0_a off # Internal GPP Bridge 0 to Bus B0
+			device pci 0.0 on end # Dummy PCIe function
+			device pci 0.1 off end
+			device pci 0.2 alias primary_NTB_0 off end # Primary PCIe Non-TransparentBridge
+			device pci 0.3 alias secondry_NTB_0 off end # Secondary vNTB
+			device pci 0.4 alias xhci_0 off end # USB
+			device pci 0.5 alias mp0_0 off end # PSP (MP0)
+			device pci 0.6 alias acp_0 off end # Audio Processor (ACP)
+			device pci 0.7 alias hda_0 off end # Audio Processor HD Audio Controller (main AZ)
+		end
+		device pci 07.2 alias gpp_bridge_0_b off # Internal GPP Bridge 1 to Bus C0
+			device pci 0.0 alias sata_0_0 off end # first SATA controller; AHCI mode
+			device pci 0.1 alias sata_0_1 off end # second SATA controller; AHCI mode
+		end
+
+		device pci 14.0 alias smbus on end # primary FCH function
+		device pci 14.3 alias lpc_bridge on ops amd_lpc_ops end
+		device pci 14.6 alias sdhci off end
+
+		device pci 18.0 alias data_fabric_0 on end
+		device pci 18.1 alias data_fabric_1 on end
+		device pci 18.2 alias data_fabric_2 on end
+		device pci 18.3 alias data_fabric_3 on end
+		device pci 18.4 alias data_fabric_4 on end
+		device pci 18.5 alias data_fabric_5 on end
+		device pci 18.6 alias data_fabric_6 on end
+		device pci 18.7 alias data_fabric_7 on end
+	end
+
+	device domain 1 on
+		ops turin_pci_domain_ops
+		device pci 00.0 alias gnb_1 on end
+		device pci 00.2 alias iommu_1 off ops amd_iommu_ops end
+		device pci 00.3 alias rcec_1 off end
+
+		device pci 01.0 on end # Dummy device function, do not disable
+		chip drivers/amd/opensil/mpio
+			device pci 01.1 alias gpp_bridge_1_0_a off end
+		end
+		chip drivers/amd/opensil/mpio
+			device pci 01.2 alias gpp_bridge_1_1_a off end
+		end
+		chip drivers/amd/opensil/mpio
+			device pci 01.3 alias gpp_bridge_1_2_a off end
+		end
+		chip drivers/amd/opensil/mpio
+			device pci 01.4 alias gpp_bridge_1_3_a off end
+		end
+		chip drivers/amd/opensil/mpio
+			device pci 01.5 alias gpp_bridge_1_4_a off end
+		end
+		chip drivers/amd/opensil/mpio
+			device pci 01.6 alias gpp_bridge_1_5_a off end
+		end
+		chip drivers/amd/opensil/mpio
+			device pci 01.7 alias gpp_bridge_1_6_a off end
+		end
+
+		device pci 02.0 on end # Dummy device function, do not disable
+		chip drivers/amd/opensil/mpio
+			device pci 02.1 alias gpp_bridge_1_7_a off end
+		end
+		chip drivers/amd/opensil/mpio
+			device pci 02.2 alias gpp_bridge_1_8_a off end
+		end
+
+		device pci 03.0 on end # Dummy device function, do not disable
+		chip drivers/amd/opensil/mpio
+			device pci 03.1 alias gpp_bridge_1_0_b off end
+		end
+		chip drivers/amd/opensil/mpio
+			device pci 03.2 alias gpp_bridge_1_1_b off end
+		end
+		chip drivers/amd/opensil/mpio
+			device pci 03.3 alias gpp_bridge_1_2_b off end
+		end
+		chip drivers/amd/opensil/mpio
+			device pci 03.4 alias gpp_bridge_1_3_b off end
+		end
+		chip drivers/amd/opensil/mpio
+			device pci 03.5 alias gpp_bridge_1_4_b off end
+		end
+		chip drivers/amd/opensil/mpio
+			device pci 03.6 alias gpp_bridge_1_5_b off end
+		end
+		chip drivers/amd/opensil/mpio
+			device pci 03.7 alias gpp_bridge_1_6_b off end
+		end
+
+		device pci 04.0 on end # Dummy device function, do not disable
+		chip drivers/amd/opensil/mpio
+			device pci 04.1 alias gpp_bridge_1_7_b off end
+		end
+		chip drivers/amd/opensil/mpio
+			device pci 04.2 alias gpp_bridge_1_8_b off end
+		end
+
+		device pci 05.0 on end # Dummy device function, do not disable
+
+		device pci 07.0 on end # Dummy device function, do not disable
+		device pci 07.1 alias gpp_bridge_1_a off
+			device pci 0.0 on end # Dummy PCIe function
+			device pci 0.1 off end #SDXI
+			device pci 0.2 alias primary_NTB_1 off end # Primary PCIe Non-TransparentBridge
+			device pci 0.3 alias secondry_NTB_1 off end # Secondary vNTB
+		end
+	end
+
+	device domain 2 on
+		ops turin_pci_domain_ops
+		device pci 00.0 alias gnb_2 on end
+		device pci 00.2 alias iommu_2 off ops amd_iommu_ops end
+		device pci 00.3 alias rcec_2 off end
+
+		device pci 01.0 on end # Dummy device function, do not disable
+		chip drivers/amd/opensil/mpio
+			device pci 01.1 alias gpp_bridge_2_0_a off end
+		end
+		chip drivers/amd/opensil/mpio
+			device pci 01.2 alias gpp_bridge_2_1_a off end
+		end
+		chip drivers/amd/opensil/mpio
+			device pci 01.3 alias gpp_bridge_2_2_a off end
+		end
+		chip drivers/amd/opensil/mpio
+			device pci 01.4 alias gpp_bridge_2_3_a off end
+		end
+		chip drivers/amd/opensil/mpio
+			device pci 01.5 alias gpp_bridge_2_4_a off end
+		end
+		chip drivers/amd/opensil/mpio
+			device pci 01.6 alias gpp_bridge_2_5_a off end
+		end
+		chip drivers/amd/opensil/mpio
+			device pci 01.7 alias gpp_bridge_2_6_a off end
+		end
+
+		device pci 02.0 on end # Dummy device function, do not disable
+		chip drivers/amd/opensil/mpio
+			device pci 02.1 alias gpp_bridge_2_7_a off end
+		end
+		chip drivers/amd/opensil/mpio
+			device pci 02.2 alias gpp_bridge_2_8_a off end
+		end
+
+		device pci 03.0 on end # Dummy device function, do not disable
+		chip drivers/amd/opensil/mpio
+			device pci 03.1 alias gpp_bridge_2_0_b off end
+		end
+		chip drivers/amd/opensil/mpio
+			device pci 03.2 alias gpp_bridge_2_1_b off end
+		end
+		chip drivers/amd/opensil/mpio
+			device pci 03.3 alias gpp_bridge_2_2_b off end
+		end
+		chip drivers/amd/opensil/mpio
+			device pci 03.4 alias gpp_bridge_2_3_b off end
+		end
+		chip drivers/amd/opensil/mpio
+			device pci 03.5 alias gpp_bridge_2_4_b off end
+		end
+		chip drivers/amd/opensil/mpio
+			device pci 03.6 alias gpp_bridge_2_5_b off end
+		end
+		chip drivers/amd/opensil/mpio
+			device pci 03.7 alias gpp_bridge_2_6_b off end
+		end
+
+		device pci 04.0 on end # Dummy device function, do not disable
+		chip drivers/amd/opensil/mpio
+			device pci 04.1 alias gpp_bridge_2_7_b off end
+		end
+		chip drivers/amd/opensil/mpio
+			device pci 04.2 alias gpp_bridge_2_8_b off end
+		end
+
+		device pci 05.0 on end # Dummy device function, do not disable
+
+		device pci 07.0 on end # Dummy device function, do not disable
+		device pci 07.1 alias gpp_bridge_2_a off
+			device pci 0.0 on end # Dummy PCIe function
+			device pci 0.1 off end
+			device pci 0.2 alias primary_NTB_2 off end # Primary PCIe Non-TransparentBridge
+			device pci 0.3 alias secondry_NTB_2 off end # Secondary vNTB
+		end
+	end
+
+	device domain 3 on
+		ops turin_pci_domain_ops
+		device pci 00.0 alias gnb_3 on end
+		device pci 00.2 alias iommu_3 off ops amd_iommu_ops end
+		device pci 00.3 alias rcec_3 off end
+
+		device pci 01.0 on end # Dummy device function, do not disable
+		chip drivers/amd/opensil/mpio
+			device pci 01.1 alias gpp_bridge_3_0_a off end
+		end
+		chip drivers/amd/opensil/mpio
+			device pci 01.2 alias gpp_bridge_3_1_a off end
+		end
+		chip drivers/amd/opensil/mpio
+			device pci 01.3 alias gpp_bridge_3_2_a off end
+		end
+		chip drivers/amd/opensil/mpio
+			device pci 01.4 alias gpp_bridge_3_3_a off end
+		end
+		chip drivers/amd/opensil/mpio
+			device pci 01.5 alias gpp_bridge_3_4_a off end
+		end
+		chip drivers/amd/opensil/mpio
+			device pci 01.6 alias gpp_bridge_3_5_a off end
+		end
+		chip drivers/amd/opensil/mpio
+			device pci 01.7 alias gpp_bridge_3_6_a off end
+		end
+
+		device pci 02.0 on end # Dummy device function, do not disable
+		chip drivers/amd/opensil/mpio
+			device pci 02.1 alias gpp_bridge_3_7_a off end
+		end
+		chip drivers/amd/opensil/mpio
+			device pci 02.2 alias gpp_bridge_3_8_a off end
+		end
+
+		device pci 03.0 on end # Dummy device function, do not disable
+		chip drivers/amd/opensil/mpio
+			device pci 03.1 alias gpp_bridge_3_0_b off end
+		end
+		chip drivers/amd/opensil/mpio
+			device pci 03.2 alias gpp_bridge_3_1_b off end
+		end
+		chip drivers/amd/opensil/mpio
+			device pci 03.3 alias gpp_bridge_3_2_b off end
+		end
+		chip drivers/amd/opensil/mpio
+			device pci 03.4 alias gpp_bridge_3_3_b off end
+		end
+		chip drivers/amd/opensil/mpio
+			device pci 03.5 alias gpp_bridge_3_4_b off end
+		end
+		chip drivers/amd/opensil/mpio
+			device pci 03.6 alias gpp_bridge_3_5_b off end
+		end
+		chip drivers/amd/opensil/mpio
+			device pci 03.7 alias gpp_bridge_3_6_b off end
+		end
+
+		device pci 04.0 on end # Dummy device function, do not disable
+		chip drivers/amd/opensil/mpio
+			device pci 04.1 alias gpp_bridge_3_7_b off end
+		end
+		chip drivers/amd/opensil/mpio
+			device pci 04.2 alias gpp_bridge_3_8_b off end
+		end
+
+		device pci 05.0 on end # Dummy device function, do not disable
+		chip drivers/amd/opensil/mpio
+			device pci 05.1 alias gpp_bridge_3_0_c off end
+		end
+		chip drivers/amd/opensil/mpio
+			device pci 05.2 alias gpp_bridge_3_1_c off end
+		end
+		chip drivers/amd/opensil/mpio
+			device pci 05.3 alias gpp_bridge_3_2_c off end
+		end
+		chip drivers/amd/opensil/mpio
+			device pci 05.4 alias gpp_bridge_3_3_c off end
+		end
+
+		device pci 07.0 on end # Dummy device function, do not disable
+		device pci 07.1 alias gpp_bridge_3_a off
+			device pci 0.0 on end # Dummy PCIe function
+			device pci 0.1 off end #SDXI
+			device pci 0.2 alias primary_NTB_3 off end # Primary PCIe Non-TransparentBridge
+			device pci 0.3 alias secondry_NTB_3 off end # Secondary vNTB
+			device pci 0.4 alias xhci_3 off end # USB
+			device pci 0.5 alias mp0_3 off end # PSP (MP0)
+		end
+
+		device pci 07.2 alias gpp_bridge_3_b off
+			device pci 0.0 alias sata_3_0 off end # first SATA controller; AHCI mode
+			device pci 0.1 alias sata_3_1 off end # second SATA controller; AHCI mode
+		end
+	end
+
+	device mmio 0xfedc2000 alias i2c_0 off ops soc_amd_i2c_mmio_ops end
+	device mmio 0xfedc3000 alias i2c_1 off ops soc_amd_i2c_mmio_ops end
+	device mmio 0xfedc4000 alias i2c_2 off ops soc_amd_i2c_mmio_ops end
+	device mmio 0xfedc5000 alias i2c_3 off ops soc_amd_i2c_mmio_ops end
+	device mmio 0xfedc6000 alias i2c_4 off ops soc_amd_i2c_mmio_ops end
+	device mmio 0xfedcb000 alias i2c_5 off ops soc_amd_i2c_mmio_ops end
+	device mmio 0xfedc9000 alias uart_0 off ops amd_uart_mmio_ops end
+	device mmio 0xfedca000 alias uart_1 off ops amd_uart_mmio_ops end
+	device mmio 0xfedce000 alias uart_2 off ops amd_uart_mmio_ops end
+	device mmio 0xfedd2000 alias i3c_0 off ops soc_amd_i3c_mmio_ops end
+	device mmio 0xfedd3000 alias i3c_1 off ops soc_amd_i3c_mmio_ops end
+	device mmio 0xfedd4000 alias i3c_2 off ops soc_amd_i3c_mmio_ops end
+	device mmio 0xfedd6000 alias i3c_3 off ops soc_amd_i3c_mmio_ops end
+
+end
diff --git a/src/soc/amd/turin_poc/config.c b/src/soc/amd/turin_poc/config.c
new file mode 100644
index 0000000000..08b35af4d7
--- /dev/null
+++ b/src/soc/amd/turin_poc/config.c
@@ -0,0 +1,12 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <amdblocks/chip.h>
+#include <device/device.h>
+#include <static.h>
+#include "chip.h"
+
+const struct soc_amd_common_config *soc_get_common_config(void)
+{
+	const struct soc_amd_turin_poc_config *cfg = config_of_soc();
+	return &cfg->common_config;
+}
diff --git a/src/soc/amd/turin_poc/cpu.c b/src/soc/amd/turin_poc/cpu.c
new file mode 100644
index 0000000000..aedd0ac6cf
--- /dev/null
+++ b/src/soc/amd/turin_poc/cpu.c
@@ -0,0 +1,21 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <amdblocks/cpu.h>
+#include <cpu/cpu.h>
+#include <device/device.h>
+#include <soc/cpu.h>
+
+static struct device_operations cpu_dev_ops = {
+	.init = amd_cpu_init,
+};
+
+static struct cpu_device_id cpu_table[] = {
+	{ X86_VENDOR_AMD, TURIN_A0_CPUID, CPUID_ALL_STEPPINGS_MASK },
+	{ X86_VENDOR_AMD, TURIN_B0_CPUID, CPUID_ALL_STEPPINGS_MASK },
+	CPU_TABLE_END
+};
+
+static const struct cpu_driver model_19 __cpu_driver = {
+	.ops      = &cpu_dev_ops,
+	.id_table = cpu_table,
+};
diff --git a/src/soc/amd/turin_poc/domain.c b/src/soc/amd/turin_poc/domain.c
new file mode 100644
index 0000000000..40177d7dcc
--- /dev/null
+++ b/src/soc/amd/turin_poc/domain.c
@@ -0,0 +1,71 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <acpi/acpigen_pci.h>
+#include <amdblocks/ioapic.h>
+#include <amdblocks/data_fabric.h>
+#include <amdblocks/memmap.h>
+#include <amdblocks/root_complex.h>
+#include <amdblocks/smn.h>
+#include <arch/ioapic.h>
+#include <console/console.h>
+#include <device/device.h>
+#include <drivers/amd/opensil/opensil.h>
+#include <types.h>
+
+#define IOHC_IOAPIC_BASE_ADDR_LO 0x2f0
+
+void read_soc_memmap_resources(struct device *domain, unsigned long *idx)
+{
+	read_lower_soc_memmap_resources(domain, idx);
+
+	amd_opensil_add_memmap(domain, idx);
+}
+
+static void turin_domain_set_resources(struct device *domain)
+{
+	if (domain->downstream->bridge_ctrl & PCI_BRIDGE_CTL_VGA) {
+		printk(BIOS_DEBUG, "Setting VGA decoding for domain 0x%x\n",
+		       dev_get_domain_id(domain));
+		const union df_vga_en vga_en = {
+			.ve = 1,
+			.dst_fabric_id = get_iohc_fabric_id(domain),
+		};
+		data_fabric_broadcast_write32(DF_VGA_EN, vga_en.raw);
+	}
+
+	pci_domain_set_resources(domain);
+
+	/* Enable IOAPIC memory decoding */
+	struct resource *res = probe_resource(domain, IOMMU_IOAPIC_IDX);
+	if (res) {
+		const uint32_t iohc_misc_base = get_iohc_misc_smn_base(domain);
+		uint32_t ioapic_base = smn_read32(iohc_misc_base | IOHC_IOAPIC_BASE_ADDR_LO);
+		ioapic_base |= (1 << 0);
+		smn_write32(iohc_misc_base | IOHC_IOAPIC_BASE_ADDR_LO, ioapic_base);
+	}
+}
+
+static const char *turin_domain_acpi_name(const struct device *domain)
+{
+	const unsigned int domain_id = dev_get_domain_id(domain);
+	const char *domain_acpi_names[4] = {
+		"S0B0",
+		"S0B1",
+		"S0B2",
+		"S0B3",
+	};
+
+	if (domain_id < ARRAY_SIZE(domain_acpi_names))
+		return domain_acpi_names[domain_id];
+
+	return NULL;
+}
+
+struct device_operations turin_pci_domain_ops = {
+	.read_resources	= amd_pci_domain_read_resources,
+	.set_resources	= turin_domain_set_resources,
+	.scan_bus	= amd_pci_domain_scan_bus,
+	.init		= amd_pci_domain_init,
+	.acpi_name	= turin_domain_acpi_name,
+	.acpi_fill_ssdt	= pci_domain_fill_ssdt,
+};
diff --git a/src/soc/amd/turin_poc/early_fch.c b/src/soc/amd/turin_poc/early_fch.c
new file mode 100644
index 0000000000..d82ebcbcf8
--- /dev/null
+++ b/src/soc/amd/turin_poc/early_fch.c
@@ -0,0 +1,33 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <amdblocks/espi.h>
+#include <amdblocks/lpc.h>
+#include <amdblocks/acpimmio.h>
+#include <amdblocks/aoac.h>
+#include <amdblocks/pmlib.h>
+#include <amdblocks/uart.h>
+#include <soc/southbridge.h>
+#include <soc/uart.h>
+
+/* Before console init */
+void fch_pre_init(void)
+{
+	fch_enable_cf9_io();
+
+	enable_aoac_devices();
+	/*
+	 * On reset Range_0 defaults to enabled. We want to start with a clean
+	 * slate to not have things unexpectedly enabled.
+	 */
+	clear_uart_legacy_config();
+
+	if (CONFIG(AMD_SOC_CONSOLE_UART))
+		set_uart_config(CONFIG_UART_FOR_CONSOLE);
+
+	configure_espi_with_mb_hook();
+}
+
+/* After console init */
+void fch_early_init(void)
+{
+}
diff --git a/src/soc/amd/turin_poc/fch.c b/src/soc/amd/turin_poc/fch.c
new file mode 100644
index 0000000000..46f97db8ea
--- /dev/null
+++ b/src/soc/amd/turin_poc/fch.c
@@ -0,0 +1,86 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <amdblocks/acpi.h>
+#include <amdblocks/acpimmio.h>
+#include <amdblocks/amd_pci_util.h>
+#include <amdblocks/gpio.h>
+#include <amdblocks/smi.h>
+#include <cpu/x86/smm.h>
+#include <soc/amd_pci_int_defs.h>
+#include <soc/smi.h>
+#include <soc/southbridge.h>
+
+/*
+ * Table of APIC register index and associated IRQ name. Using IDX_XXX_NAME
+ * provides a visible association with the index, therefore helping
+ * maintainability of table. If a new index/name is defined in
+ * amd_pci_int_defs.h, just add the pair at the end of this table.
+ * Order is not important.
+ */
+static const struct irq_idx_name irq_association[] = {
+	{ PIRQ_A,	"INTA#" },
+	{ PIRQ_B,	"INTB#" },
+	{ PIRQ_C,	"INTC#" },
+	{ PIRQ_D,	"INTD#" },
+	{ PIRQ_E,	"INTE#" },
+	{ PIRQ_F,	"INTF#/GENINT2" },
+	{ PIRQ_G,	"INTG#" },
+	{ PIRQ_H,	"INTH#" },
+	{ PIRQ_MISC,	"Misc" },
+	{ PIRQ_MISC0,	"Misc0" },
+	{ PIRQ_HPET_L,	"HPET_L" },
+	{ PIRQ_HPET_H,	"HPET_H" },
+	{ PIRQ_SIRQA,	"Ser IRQ INTA" },
+	{ PIRQ_SIRQB,	"Ser IRQ INTB" },
+	{ PIRQ_SIRQC,	"Ser IRQ INTC" },
+	{ PIRQ_SIRQD,	"Ser IRQ INTD" },
+	{ PIRQ_SCI,	"SCI" },
+	{ PIRQ_SMBUS,	"SMBUS" },
+	{ PIRQ_ASF,	"ASF" },
+	{ PIRQ_PMON,	"PerMon" },
+	{ PIRQ_SDIO,	"SDIO" },
+	{ PIRQ_GPP0,	"GPP0" },
+	{ PIRQ_GPP1,	"GPP1" },
+	{ PIRQ_GPP2,	"GPP2" },
+	{ PIRQ_GPP3,	"GPP3" },
+	{ PIRQ_GSCI,	"GEvent SCI" },
+	{ PIRQ_GSMI,	"GEvent SMI" },
+	{ PIRQ_GPIO,	"GPIO" },
+	{ PIRQ_I2C0,	"I2C0" },
+	{ PIRQ_I2C1,	"I2C1" },
+	{ PIRQ_I2C2,	"I2C2" },
+	{ PIRQ_I2C3,	"I2C3" },
+	{ PIRQ_UART0,	"UART0" },
+	{ PIRQ_UART1,	"UART1" },
+	{ PIRQ_I2C4,	"I2C4" },
+	{ PIRQ_I2C5,	"I2C5" },
+	{ PIRQ_UART2,	"UART2" },
+	{ PIRQ_UART3,	"UART3" },
+};
+
+const struct irq_idx_name *sb_get_apic_reg_association(size_t *size)
+{
+	*size = ARRAY_SIZE(irq_association);
+	return irq_association;
+}
+
+static void set_pci_irqs(void)
+{
+	/* Write PCI_INTR regs 0xC00/0xC01 */
+	write_pci_int_table();
+
+	/* TODO: PIRQ configuration */
+}
+
+static void fch_init_acpi_ports(void)
+{
+	/* Configure and enable APMC SMI Command Port */
+	pm_write16(PM_ACPI_SMI_CMD, APM_CNT);
+	configure_smi(SMITYPE_SMI_CMD_PORT, SMI_MODE_SMI);
+}
+
+void fch_init(void *chip_info)
+{
+	set_pci_irqs();
+	fch_init_acpi_ports();
+}
diff --git a/src/soc/amd/turin_poc/fw.cfg b/src/soc/amd/turin_poc/fw.cfg
new file mode 100644
index 0000000000..11b1ee638e
--- /dev/null
+++ b/src/soc/amd/turin_poc/fw.cfg
@@ -0,0 +1,54 @@
+# PSP fw config file
+FIRMWARE_LOCATION     3rdparty/amd_blobs/turin/PSP
+SOC_NAME              Turin
+
+# type                file
+# PSP
+AMD_PUBKEY_FILE       Typex0_0_0_0_AmdPubKey.bin
+PSPBTLDR_FILE         Typex1_0_0_0_PspBootLoader.bin Lbb
+PSPRCVR_FILE          Typex3_0_0_0_PspRecBL.bin
+PSP_SMUFW1_SUB0_FILE  Typex8_0_0_0_Smu.bin
+PSP_SMUFW1_SUB1_FILE  Typex8_0_0_1_Smu.bin
+PSP_SMUFW1_SUB2_FILE  Typex8_0_0_2_Smu.bin
+PSPSECUREDEBUG_FILE   Typex9_0_0_0_DbgKey.bin
+PSP_OEM_ABL_KEY_FILE  Typexa_0_0_0_OemAblKey.bin
+PSP_SMUFW2_SUB0_FILE  Typex12_0_0_0_Smu2.bin
+PSP_SMUFW2_SUB1_FILE  Typex12_0_0_1_Smu2.bin
+PSP_SMUFW2_SUB2_FILE  Typex12_0_0_2_Smu2.bin Lbb
+PSP_SEC_DEBUG_FILE    Typex13_0_0_0_PspEarlyUnlock.bin Lbb
+PSP_IKEK_FILE         Typex21_0_0_0_ikek.bin
+PSP_TOKEN_UNLOCK_FILE Typex22_0_0_0_PspTokenUnlockData.bin
+PSP_SECG0_FILE        Typex24_0_0_0_SecureGasket.bin
+PSP_SECG1_FILE        Typex24_0_0_1_SecureGasket.bin
+PSP_SECG2_FILE        Typex24_0_0_2_SecureGasket.bin
+PSP_MP5FW_SUB0_FILE   Typex2a_0_0_0_Mp5Fw.bin
+PSP_MP5FW_SUB1_FILE   Typex2a_0_0_1_Mp5Fw.bin
+PSP_MP5FW_SUB2_FILE   Typex2a_0_0_2_Mp5Fw.bin
+PSP_ABL0_FILE         Typex30_0_0_0_PspAgesaBL0.bin
+SEV_CODE_FILE         Typex39_0_0_0_SevCode.bin
+SEV_DATA_FILE         Typex38_0_0_0_SevData.bin
+PSP_DXIOFW_FILE       Typex42_0_0_0_DxioFw.bin
+UNIFIEDUSB_FILE       Typex44_0_0_0_UsbPhyFw.bin
+DRTMTA_FILE           Typex47_0_0_0_DrtmTa.bin
+KEYDBBL_FILE          Typex50_0_0_0_PspBlPubKey.bin
+SPL_TABLE_FILE        Typex55_0_0_0_BLAntiRB.bin Lbb
+PSP_MPIOFW_FILE       Typex5d_0_0_0_MPIOOffchipFW.bin
+PSP_RIB_FILE_SUB0     Typex76_0_0_0_RIB.bin
+PSP_MPDMATFFW_FILE    Typex8c_0_0_0_MpdmaTfFw.bin
+PSP_GMI3PHYFW_FILE    Typex91_0_0_0_Gmi3PhyFw.bin
+PSP_MPDMAPMFW_FILE    Typex92_0_0_0_MpdmaPmFw.bin
+AMD_FUSE_CHAIN        Dummy Lbb
+
+# BDT
+PSP_PMUI_FILE_SUB0_INS3 Typex64_0_3_0_PmuCode.bin
+PSP_PMUI_FILE_SUB0_INS4 Typex64_0_4_0_PmuCode.bin
+PSP_PMUI_FILE_SUB0_INS9 Typex64_0_9_0_PmuCode.bin
+PSP_PMUI_FILE_SUB0_INSA Typex64_0_a_0_PmuCode.bin
+PSP_PMUI_FILE_SUB0_INSB Typex64_0_b_0_PmuCode.bin
+PSP_PMUD_FILE_SUB0_INS3 Typex65_0_3_0_PmuData.bin
+PSP_PMUD_FILE_SUB0_INS4 Typex65_0_4_0_PmuData.bin
+PSP_PMUD_FILE_SUB0_INS9 Typex65_0_9_0_PmuData.bin
+PSP_PMUD_FILE_SUB0_INSA Typex65_0_a_0_PmuData.bin
+PSP_PMUD_FILE_SUB0_INSB Typex65_0_b_0_PmuData.bin
+PSP_PMUD_FILE_SUB0_INSC Typex65_0_c_0_PmuData.bin
+# TODO: Typex69_0_0_0_EarlyVgaImage.bin
diff --git a/src/soc/amd/turin_poc/gpio.c b/src/soc/amd/turin_poc/gpio.c
new file mode 100644
index 0000000000..c38719bf3f
--- /dev/null
+++ b/src/soc/amd/turin_poc/gpio.c
@@ -0,0 +1,38 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <amdblocks/gpio.h>
+#include <gpio.h>
+#include <types.h>
+
+/* see the IOMUX function table for the mapping from GPIO number to GEVENT number */
+static const struct soc_amd_event gpio_event_table[] = {
+	{ GPIO_0, GEVENT_21 }, /* GPIO0 may only be used as PWR_BTN_L in ACPI */
+	{ GPIO_1, GEVENT_19 },
+	{ GPIO_2, GEVENT_8 },
+	{ GPIO_3, GEVENT_2 },
+	{ GPIO_4, GEVENT_4 },
+	{ GPIO_5, GEVENT_7 },
+	{ GPIO_6, GEVENT_10 },
+	{ GPIO_16, GEVENT_12 },
+	{ GPIO_17, GEVENT_13 },
+	{ GPIO_21, GEVENT_5 },
+	{ GPIO_22, GEVENT_3 },
+	{ GPIO_23, GEVENT_16 },
+	{ GPIO_24, GEVENT_14 },
+	{ GPIO_26, GEVENT_15 },
+	{ GPIO_76, GEVENT_11 },
+	{ GPIO_86, GEVENT_9 },
+	{ GPIO_89, GEVENT_0 },
+	{ GPIO_104, GEVENT_20 },
+	{ GPIO_105, GEVENT_22 },
+	{ GPIO_106, GEVENT_23 },
+	{ GPIO_115, GEVENT_1 },
+	{ GPIO_116, GEVENT_6 },
+	{ GPIO_129, GEVENT_17 },
+};
+
+void soc_get_gpio_event_table(const struct soc_amd_event **table, size_t *items)
+{
+	*table = gpio_event_table;
+	*items = ARRAY_SIZE(gpio_event_table);
+}
diff --git a/src/soc/amd/turin_poc/i2c.c b/src/soc/amd/turin_poc/i2c.c
new file mode 100644
index 0000000000..76aa1aa591
--- /dev/null
+++ b/src/soc/amd/turin_poc/i2c.c
@@ -0,0 +1,57 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <amdblocks/i2c.h>
+#include <soc/i2c.h>
+#include <soc/iomap.h>
+#include <soc/southbridge.h>
+#include <static.h>
+#include "chip.h"
+
+/* Table to switch SCL pins to outputs to initially reset the I2C peripherals */
+static const struct soc_i2c_scl_pin i2c_scl_pins[] = {
+	I2C_RESET_SCL_PIN(I2C0_SCL_PIN, GPIO_I2C0_SCL),
+	I2C_RESET_SCL_PIN(I2C1_SCL_PIN, GPIO_I2C1_SCL),
+	I2C_RESET_SCL_PIN(I2C2_SCL_PIN, GPIO_I2C2_SCL),
+	I2C_RESET_SCL_PIN(I2C3_SCL_PIN, GPIO_I2C3_SCL),
+	I2C_RESET_SCL_PIN(I2C4_SCL_PIN, GPIO_I2C4_SCL),
+	I2C_RESET_SCL_PIN(I2C5_SCL_PIN, GPIO_I2C5_SCL),
+};
+
+static const struct soc_i2c_ctrlr_info i2c_ctrlr[I2C_CTRLR_COUNT] = {
+	{ I2C_MASTER_MODE, APU_I2C0_BASE, "I2C0" },
+	{ I2C_MASTER_MODE, APU_I2C1_BASE, "I2C1" },
+	{ I2C_MASTER_MODE, APU_I2C2_BASE, "I2C2" },
+	{ I2C_MASTER_MODE, APU_I2C3_BASE, "I2C3" },
+	{ I2C_MASTER_MODE, APU_I2C4_BASE, "I2C4" },
+	{ I2C_MASTER_MODE, APU_I2C5_BASE, "I2C5" }
+};
+
+void reset_i2c_peripherals(void)
+{
+	const struct soc_amd_turin_poc_config *cfg = config_of_soc();
+	struct soc_i2c_peripheral_reset_info reset_info;
+
+	reset_info.i2c_scl_reset_mask = cfg->i2c_scl_reset & GPIO_I2C_MASK;
+	reset_info.i2c_scl = i2c_scl_pins;
+	reset_info.num_pins = ARRAY_SIZE(i2c_scl_pins);
+	sb_reset_i2c_peripherals(&reset_info);
+}
+
+void soc_i2c_misc_init(unsigned int bus, const struct dw_i2c_bus_config *cfg)
+{
+	/* TODO: write I2C pad control registers */
+}
+
+const struct soc_i2c_ctrlr_info *soc_get_i2c_ctrlr_info(size_t *num_ctrlrs)
+{
+	*num_ctrlrs = ARRAY_SIZE(i2c_ctrlr);
+	return i2c_ctrlr;
+}
+
+const struct dw_i2c_bus_config *soc_get_i2c_bus_config(size_t *num_buses)
+{
+	const struct soc_amd_turin_poc_config *config = config_of_soc();
+
+	*num_buses = ARRAY_SIZE(config->i2c);
+	return config->i2c;
+}
diff --git a/src/soc/amd/turin_poc/i3c.c b/src/soc/amd/turin_poc/i3c.c
new file mode 100644
index 0000000000..e694623177
--- /dev/null
+++ b/src/soc/amd/turin_poc/i3c.c
@@ -0,0 +1,18 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <amdblocks/i2c.h>
+#include <soc/iomap.h>
+#include <types.h>
+
+static const struct soc_i3c_ctrlr_info i3c_ctrlr[I3C_CTRLR_COUNT] = {
+	{ APU_I3C0_BASE, "I3C0" },
+	{ APU_I3C1_BASE, "I3C1" },
+	{ APU_I3C2_BASE, "I3C2" },
+	{ APU_I3C3_BASE, "I3C3" }
+};
+
+const struct soc_i3c_ctrlr_info *soc_get_i3c_ctrlr_info(size_t *num_ctrlrs)
+{
+	*num_ctrlrs = ARRAY_SIZE(i3c_ctrlr);
+	return i3c_ctrlr;
+}
diff --git a/src/soc/amd/turin_poc/include/soc/amd_pci_int_defs.h b/src/soc/amd/turin_poc/include/soc/amd_pci_int_defs.h
new file mode 100644
index 0000000000..f093247735
--- /dev/null
+++ b/src/soc/amd/turin_poc/include/soc/amd_pci_int_defs.h
@@ -0,0 +1,56 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef AMD_TURIN_POC_AMD_PCI_INT_DEFS_H
+#define AMD_TURIN_POC_AMD_PCI_INT_DEFS_H
+
+/*
+ *  * PIRQ and device routing - these define the index into the
+ *   * FCH PCI_INTR 0xC00/0xC01 interrupt routing table.
+ *    */
+
+#define PIRQ_NC		0x1f	/* Not Used */
+#define PIRQ_A		0x00	/* INT A */
+#define PIRQ_B		0x01	/* INT B */
+#define PIRQ_C		0x02	/* INT C */
+#define PIRQ_D		0x03	/* INT D */
+#define PIRQ_E		0x04	/* INT E */
+#define PIRQ_F		0x05	/* INT F */
+#define PIRQ_G		0x06	/* INT G */
+#define PIRQ_H		0x07	/* INT H */
+#define PIRQ_MISC	0x08	/* Miscellaneous IRQ Settings */
+#define PIRQ_MISC0	0x09	/* Miscellaneous0 IRQ Settings */
+#define PIRQ_HPET_L	0x0a	/* Miscellaneous1 IRQ Settings */
+#define PIRQ_HPET_H	0x0b	/* Miscellaneous2 IRQ Settings */
+#define PIRQ_SIRQA	0x0c	/* Serial IRQ INTA */
+#define PIRQ_SIRQB	0x0d	/* Serial IRQ INTB */
+#define PIRQ_SIRQC	0x0e	/* Serial IRQ INTC */
+#define PIRQ_SIRQD	0x0f	/* Serial IRQ INTD */
+#define PIRQ_SCI	0x10	/* SCI IRQ */
+#define PIRQ_SMBUS	0x11	/* SMBUS0 */
+#define PIRQ_ASF	0x12	/* ASF */
+/* 0x13-0x15 reserved */
+#define PIRQ_PMON	0x16	/* Performance Monitor */
+/* 0x17-0x19 reserved */
+#define PIRQ_SDIO	0x1a	/* SDIO */
+/* 0x1b-0x49 reserved */
+#define PIRQ_GPP0	0x50	/* GPPInt0 */
+#define PIRQ_GPP1	0x51	/* GPPInt1 */
+#define PIRQ_GPP2	0x52	/* GPPInt2 */
+#define PIRQ_GPP3	0x53	/* GPPInt3 */
+/* 0x54-0x59 reserved */
+#define PIRQ_GSCI	0x60	/* SCI Interrupt */
+#define PIRQ_GSMI	0x61	/* SMI Interrupt */
+#define PIRQ_GPIO	0x62	/* GPIO Interrupt */
+/* 0x63-0x6f reserved */
+#define PIRQ_I2C0	0x70	/* I2C0/I3C0 */
+#define PIRQ_I2C1	0x71	/* I2C1/I3C1 */
+#define PIRQ_I2C2	0x72	/* I2C2/I3C2 */
+#define PIRQ_I2C3	0x73	/* I2C3/I3C3 */
+#define PIRQ_UART0	0x74	/* UART0 */
+#define PIRQ_UART1	0x75	/* UART1 */
+#define PIRQ_I2C4	0x76	/* I2C4 */
+#define PIRQ_I2C5	0x77	/* I2C5 */
+#define PIRQ_UART2	0x78	/* UART2 */
+#define PIRQ_UART3	0x79	/* UART3 */
+
+#endif /* AMD_TURIN_POC_AMD_PCI_INT_DEFS_H */
diff --git a/src/soc/amd/turin_poc/include/soc/aoac_defs.h b/src/soc/amd/turin_poc/include/soc/aoac_defs.h
new file mode 100644
index 0000000000..156ee34962
--- /dev/null
+++ b/src/soc/amd/turin_poc/include/soc/aoac_defs.h
@@ -0,0 +1,24 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef AMD_TURIN_POC_AOAC_DEFS_H
+#define AMD_TURIN_POC_AOAC_DEFS_H
+
+/* FCH AOAC device offsets for AOAC_DEV_D3_CTL/AOAC_DEV_D3_STATE */
+#define FCH_AOAC_DEV_CLK_GEN		0
+#define FCH_AOAC_DEV_I2C0		5
+#define FCH_AOAC_DEV_I2C1		6
+#define FCH_AOAC_DEV_I2C2		7
+#define FCH_AOAC_DEV_I2C3		8
+#define FCH_AOAC_DEV_I2C4		9
+#define FCH_AOAC_DEV_I2C5		10
+#define FCH_AOAC_DEV_UART0		11
+#define FCH_AOAC_DEV_UART1		12
+#define FCH_AOAC_DEV_I3C1		13
+#define FCH_AOAC_DEV_I3C2		14
+#define FCH_AOAC_DEV_I3C3		15
+#define FCH_AOAC_DEV_UART2		16
+#define FCH_AOAC_DEV_AMBA		17
+#define FCH_AOAC_DEV_I3C0		21
+#define FCH_AOAC_DEV_ESPI		27
+
+#endif /* AMD_TURIN_POC_AOAC_DEFS_H */
diff --git a/src/soc/amd/turin_poc/include/soc/cpu.h b/src/soc/amd/turin_poc/include/soc/cpu.h
new file mode 100644
index 0000000000..eada9233fa
--- /dev/null
+++ b/src/soc/amd/turin_poc/include/soc/cpu.h
@@ -0,0 +1,9 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef AMD_TURIN_POC_CPU_H
+#define AMD_TURIN_POC_CPU_H
+
+#define TURIN_A0_CPUID		CPUID_FROM_FMS(0x19, 0x10, 0)
+#define TURIN_B0_CPUID		CPUID_FROM_FMS(0x19, 0x11, 0)
+
+#endif /* AMD_TURIN_POC_CPU_H */
diff --git a/src/soc/amd/turin_poc/include/soc/data_fabric.h b/src/soc/amd/turin_poc/include/soc/data_fabric.h
new file mode 100644
index 0000000000..503dc39afb
--- /dev/null
+++ b/src/soc/amd/turin_poc/include/soc/data_fabric.h
@@ -0,0 +1,138 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef AMD_TURIN_POC_DATA_FABRIC_H
+#define AMD_TURIN_POC_DATA_FABRIC_H
+
+#include <amdblocks/data_fabric_defs.h>
+#include <types.h>
+
+#define DF_VGA_EN			DF_REG_ID(0, 0xc08)
+
+union df_vga_en {
+	struct {
+		uint32_t ve		:  1; /* [ 0.. 0] */
+		uint32_t np		:  1; /* [ 1.. 1] */
+		uint32_t cpu_dis	:  1; /* [ 2.. 2] */
+		uint32_t		:  1; /* [ 3.. 3] */
+		uint32_t dst_fabric_id	: 12; /* [ 4..15] */
+		uint32_t		: 16; /* [16..31] */
+	};
+	uint32_t raw;
+};
+
+#define DF_PCI_CFG_BASE0		DF_REG_ID(0, 0xc80)
+#define DF_PCI_CFG_LIMIT0		DF_REG_ID(0, 0xc84)
+
+#define DF_PCI_CFG_MAP_COUNT		8
+
+#define DF_PCI_CFG_REG_OFFSET(instance)	((instance) * 2 * sizeof(uint32_t))
+#define DF_PCI_CFG_BASE(reg)		(DF_PCI_CFG_BASE0 + DF_PCI_CFG_REG_OFFSET(reg))
+#define DF_PCI_CFG_LIMIT(reg)		(DF_PCI_CFG_LIMIT0 + DF_PCI_CFG_REG_OFFSET(reg))
+
+union df_pci_cfg_base {
+	struct {
+		uint32_t re		: 1; /* [ 0.. 0] */
+		uint32_t we		: 1; /* [ 1.. 1] */
+		uint32_t		: 6; /* [ 2.. 7] */
+		uint32_t segment_num	: 8; /* [ 8..15] */
+		uint32_t bus_num_base	: 8; /* [16..23] */
+		uint32_t		: 8; /* [24..31] */
+	};
+	uint32_t raw;
+};
+
+union df_pci_cfg_limit {
+	struct {
+		uint32_t dst_fabric_id	: 12; /* [ 0..11] */
+		uint32_t		:  4; /* [12..15] */
+		uint32_t bus_num_limit	:  8; /* [16..23] */
+		uint32_t		:  8; /* [24..31] */
+	};
+	uint32_t raw;
+};
+
+#define DF_IO_BASE0			DF_REG_ID(0, 0xd00)
+#define DF_IO_LIMIT0			DF_REG_ID(0, 0xd04)
+
+#define DF_IO_REG_COUNT			8
+
+#define DF_IO_REG_OFFSET(instance)	((instance) * 2 * sizeof(uint32_t))
+#define DF_IO_BASE(reg)			(DF_IO_BASE0 + DF_IO_REG_OFFSET(reg))
+#define DF_IO_LIMIT(reg)		(DF_IO_LIMIT0 + DF_IO_REG_OFFSET(reg))
+
+union df_io_base {
+	struct {
+		uint32_t re		:  1; /* [ 0.. 0] */
+		uint32_t we		:  1; /* [ 1.. 1] */
+		uint32_t		:  3; /* [ 2.. 4] */
+		uint32_t ie		:  1; /* [ 5.. 5] */
+		uint32_t		: 10; /* [ 6..15] */
+		uint32_t io_base	: 13; /* [16..28] */
+		uint32_t		:  3; /* [29..31] */
+	};
+	uint32_t raw;
+};
+
+union df_io_limit {
+	struct {
+		uint32_t dst_fabric_id	: 12; /* [ 0..11] */
+		uint32_t		:  4; /* [12..15] */
+		uint32_t io_limit	: 13; /* [16..28] */
+		uint32_t		:  3; /* [29..31] */
+	};
+	uint32_t raw;
+};
+
+#define DF_IO_ADDR_SHIFT		12
+
+#define DF_MMIO_BASE0			DF_REG_ID(0, 0xd80)
+#define DF_MMIO_LIMIT0			DF_REG_ID(0, 0xd84)
+#define   DF_MMIO_SHIFT			16
+#define DF_MMIO_CTRL0			DF_REG_ID(0, 0xd88)
+#define DF_MMIO_ADDR_EXT0		DF_REG_ID(0, 0xd8c)
+#define   DF_MMIO_EXT_ADDR_SHIFT	48
+
+#define DF_MMIO_REG_SET_SIZE		4
+#define DF_MMIO_REG_SET_COUNT		16
+
+union df_mmio_control {
+	struct {
+		uint32_t re		:  1; /* [ 0.. 0] */
+		uint32_t we		:  1; /* [ 1.. 1] */
+		uint32_t		:  1; /* [ 2.. 2] */
+		uint32_t np		:  1; /* [ 3.. 3] */
+		uint32_t		: 12; /* [ 4..15] */
+		uint32_t dst_fabric_id	: 12; /* [16..27] */
+		uint32_t		:  4; /* [28..31] */
+	};
+	uint32_t raw;
+};
+
+union df_mmio_addr_ext {
+	struct {
+		uint32_t base_ext	: 8; /* [ 0.. 7] */
+		uint32_t		: 8; /* [ 8..15] */
+		uint32_t limit_ext	: 8; /* [16..23] */
+		uint32_t		: 8; /* [24..31] */
+	};
+	uint32_t raw;
+};
+
+#define DF_FICAA_BIOS			DF_REG_ID(4, 0x8C)
+#define DF_FICAD_LO			DF_REG_ID(4, 0xB8)
+#define DF_FICAD_HI			DF_REG_ID(4, 0xBC)
+
+union df_ficaa {
+	struct {
+		uint32_t cfg_inst_acc_en :  1; /* [ 0.. 0] */
+		uint32_t reg_num         : 10; /* [10.. 1] */
+		uint32_t func_num        :  3; /* [13..11] */
+		uint32_t b64_en          :  1; /* [14..14] */
+		uint32_t                 :  1; /* [15..15] */
+		uint32_t inst_id         :  8; /* [23..16] */
+		uint32_t                 :  8; /* [31..24] */
+	};
+	uint32_t raw;
+};
+
+#endif /* AMD_TURIN_POC_DATA_FABRIC_H */
diff --git a/src/soc/amd/turin_poc/include/soc/gpio.h b/src/soc/amd/turin_poc/include/soc/gpio.h
new file mode 100644
index 0000000000..613fea7f25
--- /dev/null
+++ b/src/soc/amd/turin_poc/include/soc/gpio.h
@@ -0,0 +1,270 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef AMD_TURIN_POC_GPIO_H
+#define AMD_TURIN_POC_GPIO_H
+
+#define GPIO_DEVICE_NAME	"AMDI0030"
+#define GPIO_DEVICE_DESC	"GPIO Controller"
+
+#ifndef __ACPI__
+#include <soc/iomap.h>
+#include <amdblocks/gpio.h>
+#endif /* !__ACPI__ */
+
+#include <amdblocks/gpio_defs.h>
+
+/* The following sections describe only the GPIOs defined for this SOC */
+
+#define SOC_GPIO_TOTAL_PINS		267
+
+/* Bank 0: GPIO_0 - GPIO_63 */
+#define GPIO_0				0
+#define GPIO_1				1
+#define GPIO_2				2
+#define GPIO_3				3
+#define GPIO_4				4
+#define GPIO_5				5
+#define GPIO_6				6
+#define GPIO_7				7
+#define GPIO_12				12
+#define GPIO_13				13
+#define GPIO_14				14
+#define GPIO_16				16
+#define GPIO_17				17
+#define GPIO_19				19
+#define GPIO_20				20
+#define GPIO_21				21
+#define GPIO_22				22
+#define GPIO_23				23
+#define GPIO_24				24
+#define GPIO_26				26
+
+/* Bank 1: GPIO_64 - GPIO_127 */
+#define GPIO_74				74
+#define GPIO_75				75
+#define GPIO_76				76
+#define GPIO_86				86
+#define GPIO_87				87
+#define GPIO_88				88
+#define GPIO_89				89
+#define GPIO_104			104
+#define GPIO_105			105
+#define GPIO_106			106
+#define GPIO_107			107
+#define GPIO_108			108
+#define GPIO_109			109
+#define GPIO_110			110
+#define GPIO_115			115
+#define GPIO_116			116
+#define GPIO_117			117
+#define GPIO_118			118
+#define GPIO_119			119
+#define GPIO_120			120
+#define GPIO_121			121
+#define GPIO_122			122
+#define GPIO_123			123
+#define GPIO_124			124
+#define GPIO_125			125
+#define GPIO_126			126
+
+/* Bank 2: GPIO_128 - GPIO_191 */
+#define GPIO_129			129
+#define GPIO_131			131
+#define GPIO_132			132
+#define GPIO_133			133
+#define GPIO_134			134
+#define GPIO_135			135
+#define GPIO_136			136
+#define GPIO_137			137
+#define GPIO_138			138
+#define GPIO_139			139
+#define GPIO_141			141
+#define GPIO_142			142
+#define GPIO_145			145
+#define GPIO_146			146
+#define GPIO_147			147
+#define GPIO_148			148
+#define GPIO_149			149
+#define GPIO_150			150
+#define GPIO_151			151
+#define GPIO_152			152
+
+/* remote GPIO bank: GPIO_256 - GPIO_271 */
+#define GPIO_256			256
+#define GPIO_257			257
+#define GPIO_258			258
+#define GPIO_259			259
+#define GPIO_260			260
+#define GPIO_261			261
+#define GPIO_262			262
+#define GPIO_263			263
+#define GPIO_264			264
+#define GPIO_265			265
+#define GPIO_266			266
+
+/* IOMUX function names and values */
+#define GPIO_0_IOMUX_PWR_BTN_L 0
+#define GPIO_0_IOMUX_GPIO_PU1PD0 1
+#define GPIO_0_IOMUX_GPIOxx 2
+#define GPIO_1_IOMUX_SYS_RESET_L 0
+#define GPIO_1_IOMUX_GPIOxx 1
+#define GPIO_2_IOMUX_WAKE_L 0
+#define GPIO_2_IOMUX_GPIOxx 1
+#define GPIO_3_IOMUX_GPIOxx 0
+#define GPIO_4_IOMUX_GPIOxx 0
+#define GPIO_4_IOMUX_SATA_ACT_L 1
+#define GPIO_5_IOMUX_GPIOxx 0
+#define GPIO_5_IOMUX_DEVSLP0 1
+#define GPIO_6_IOMUX_GPIOxx 0
+#define GPIO_6_IOMUX_DEVSLP1 1
+#define GPIO_7_IOMUX_GPIOxx 0
+#define GPIO_12_IOMUX_PWRGD_OUT 0
+#define GPIO_12_IOMUX_GPIOxx 1
+#define GPIO_13_IOMUX_I2C4_SCL 0
+#define GPIO_13_IOMUX_CLK_48_24_0 1
+#define GPIO_13_IOMUX_GPIOxx 2
+#define GPIO_14_IOMUX_I2C4_SDA 0
+#define GPIO_14_IOMUX_S0A3 1
+#define GPIO_14_IOMUX_GPIOxx 2
+#define GPIO_16_IOMUX_USB_1O_OC_L 0
+#define GPIO_16_IOMUX_GPIOxx 1
+#define GPIO_17_IOMUX_USB11_OC_L 0
+#define GPIO_17_IOMUX_GPIOxx 1
+#define GPIO_19_IOMUX_I2C5_SCL 0
+#define GPIO_19_IOMUX_SMBUS1_SCL 1
+#define GPIO_19_IOMUX_GPIOxx 2
+#define GPIO_20_IOMUX_I2C5_SDA 0
+#define GPIO_20_IOMUX_SMBUS1_SDA 1
+#define GPIO_20_IOMUX_GPIOxx 2
+#define GPIO_21_IOMUX_GPIOxx 0
+#define GPIO_22_IOMUX_GPIOxx 0
+#define GPIO_23_IOMUX_ESPI_RST_OUT_L 0
+#define GPIO_23_IOMUX_GPIOxx 1
+#define GPIO_24_IOMUX_SMERR_L 0
+#define GPIO_24_IOMUX_GPIOxx 1
+#define GPIO_26_IOMUX_PCIE_RST1_L 0
+#define GPIO_26_IOMUX_GPIOxx 1
+#define GPIO_74_IOMUX_ESPI_CLK2 0
+#define GPIO_74_IOMUX_GPIOxx 1
+#define GPIO_75_IOMUX_ESPI_CLK1 0
+#define GPIO_75_IOMUX_GPIOxx 1
+#define GPIO_76_IOMUX_GPIOxx 0
+#define GPIO_76_IOMUX_SPI_TPM_CS_L 1
+#define GPIO_86_IOMUX_NMI_SYNC_FLOOD_L 0
+#define GPIO_87_IOMUX_GPIOxx 0
+#define GPIO_88_IOMUX_GPIOxx 0
+#define GPIO_89_IOMUX_GENINT_L 0
+#define GPIO_89_IOMUX_PM_INTR_L 1
+#define GPIO_89_IOMUX_GPIOxx 2
+#define GPIO_104_IOMUX_GPIOxx 0
+#define GPIO_105_IOMUX_GPIOxx 0
+#define GPIO_106_IOMUX_GPIOxx 0
+#define GPIO_107_IOMUX_GPIOxx 0
+#define GPIO_108_IOMUX_ESPI0_ALERT_D1 0
+#define GPIO_108_IOMUX_GPIOxx 1
+#define GPIO_109_IOMUX_GPIOxx 0
+#define GPIO_110_IOMUX_ESPI1_ALERT_D1 0
+#define GPIO_110_IOMUX_GPIOxx 1
+#define GPIO_115_IOMUX_GPIOxx 0
+#define GPIO_115_IOMUX_CLK_REQ11_L 1
+#define GPIO_116_IOMUX_GPIOxx 0
+#define GPIO_116_IOMUX_CLK_REQ12_L 1
+#define GPIO_117_IOMUX_ESPI_CLK0 0
+#define GPIO_117_IOMUX_GPIOxx 1
+#define GPIO_118_IOMUX_SPI_CS0_L 0
+#define GPIO_118_IOMUX_GPIOxx 1
+#define GPIO_119_IOMUX_SPI_CS1_L 0
+#define GPIO_119_IOMUX_GPIOxx 1
+#define GPIO_120_IOMUX_ESPI0_DATA0 0
+#define GPIO_120_IOMUX_GPIOxx 1
+#define GPIO_121_IOMUX_ESPI0_DATA1 0
+#define GPIO_121_IOMUX_GPIOxx 1
+#define GPIO_122_IOMUX_ESPI0_DATA2 0
+#define GPIO_122_IOMUX_GPIOxx 1
+#define GPIO_123_IOMUX_ESPI0_DATA3 0
+#define GPIO_123_IOMUX_GPIOxx 1
+#define GPIO_124_IOMUX_ESPI_CS0_L 0
+#define GPIO_124_IOMUX_GPIOxx 1
+#define GPIO_125_IOMUX_ESPI_CS1_L 0
+#define GPIO_125_IOMUX_GPIOxx 1
+#define GPIO_126_IOMUX_SPI_CS2_L 0
+#define GPIO_126_IOMUX_GPIOxx 1
+#define GPIO_129_IOMUX_ESPI_RSTIN_L 0
+#define GPIO_129_IOMUX_KBRST_L 1
+#define GPIO_129_IOMUX_GPIOxx 2
+#define GPIO_131_IOMUX_ESPI1_DATA0 0
+#define GPIO_131_IOMUX_GPIOxx 1
+#define GPIO_132_IOMUX_ESPI1_DATA1 0
+#define GPIO_132_IOMUX_GPIOxx 1
+#define GPIO_133_IOMUX_ESPI1_DATA2 0
+#define GPIO_133_IOMUX_GPIOxx 1
+#define GPIO_134_IOMUX_ESPI1_DATA3 0
+#define GPIO_134_IOMUX_GPIOxx 1
+#define GPIO_135_IOMUX_UART0_CTS_L 0
+#define GPIO_135_IOMUX_UART2_TXD 1
+#define GPIO_135_IOMUX_GPIOxx 2
+#define GPIO_136_IOMUX_UART0_RXD 0
+#define GPIO_136_IOMUX_GPIOxx 1
+#define GPIO_137_IOMUX_UART0_RTS_L 0
+#define GPIO_137_IOMUX_UART2_RXD 1
+#define GPIO_137_IOMUX_GPIOxx 2
+#define GPIO_138_IOMUX_UART0_TXD 0
+#define GPIO_138_IOMUX_GPIOxx 1
+#define GPIO_139_IOMUX_UART0_INTR 0
+#define GPIO_139_IOMUX_GPIOxx 1
+#define GPIO_141_IOMUX_UART1_RXD 0
+#define GPIO_141_IOMUX_GPIOxx 1
+#define GPIO_142_IOMUX_UART1_TXD 0
+#define GPIO_142_IOMUX_GPIOxx 1
+#define GPIO_145_IOMUX_I3C0_SCL_SPD0_SCL 0
+#define GPIO_145_IOMUX_I2C0_SCL_SPD0_SCL 1
+#define GPIO_145_IOMUX_SMBUS0_SCL 2
+#define GPIO_145_IOMUX_GPIOxx 3
+#define GPIO_146_IOMUX_I3C0_SDA_SPD0_SDA 0
+#define GPIO_146_IOMUX_I2C0_SDA_SPD0_SDA 1
+#define GPIO_146_IOMUX_SMBUS0_SDA 2
+#define GPIO_146_IOMUX_GPIOxx 3
+#define GPIO_147_IOMUX_I3C1_SCL_SPD1_SCL 0
+#define GPIO_147_IOMUX_I2C1_SCL_SPD1_SCL 1
+#define GPIO_147_IOMUX_GPIOxx 2
+#define GPIO_148_IOMUX_I3C1_SDA_SPD1_SDA 0
+#define GPIO_148_IOMUX_I2C1_SDA_SPD1_SDA 1
+#define GPIO_148_IOMUX_GPIOxx 2
+#define GPIO_149_IOMUX_I3C2_SCL_SPD2_SCL 0
+#define GPIO_149_IOMUX_I2C2_SCL_SPD2_SCL 1
+#define GPIO_149_IOMUX_GPIOxx 2
+#define GPIO_150_IOMUX_I3C2_SDA_SPD2_SDA 0
+#define GPIO_150_IOMUX_I2C2_SDA_SPD2_SDA 1
+#define GPIO_150_IOMUX_GPIOxx 2
+#define GPIO_151_IOMUX_I3C3_SCL_SPD3_SCL 0
+#define GPIO_151_IOMUX_I2C3_SCL_SPD3_SCL 1
+#define GPIO_151_IOMUX_GPIOxx 2
+#define GPIO_152_IOMUX_I3C3_SDA_SPD3_SDA 0
+#define GPIO_152_IOMUX_I2C3_SDA_SPD3_SDA 1
+#define GPIO_152_IOMUX_GPIOxx 2
+
+/* Remote GPIOs */
+#define GPIO_256_IOMUX_GPIOxx 0
+#define GPIO_256_IOMUX_SGPIO0_CLK 1
+#define GPIO_257_IOMUX_GPIOxx 0
+#define GPIO_257_IOMUX_SGPIO1_CLK 1
+#define GPIO_257_IOMUX_CLK_REQ01_L 2
+#define GPIO_258_IOMUX_GPIOxx 0
+#define GPIO_258_IOMUX_SGPIO2_CLK 1
+#define GPIO_258_IOMUX_CLK_REQ02_L 2
+#define GPIO_259_IOMUX_GPIOxx 0
+#define GPIO_259_IOMUX_SGPIO3_CLK 1
+#define GPIO_260_IOMUX_SGPIO_DATAOUT 0
+#define GPIO_260_IOMUX_GPIOxx 1
+#define GPIO_261_IOMUX_SGPIO_LOAD 0
+#define GPIO_261_IOMUX_GPIOxx 1
+#define GPIO_262_IOMUX_GPIOxx 0
+#define GPIO_263_IOMUX_GPIOxx 0
+#define GPIO_264_IOMUX_USB00_OC_L 0
+#define GPIO_264_IOMUX_GPIOxx 1
+#define GPIO_265_IOMUX_USB01_OC_L 0
+#define GPIO_265_IOMUX_GPIOxx 1
+#define GPIO_266_IOMUX_PCIE_RST0_L 0
+#define GPIO_266_IOMUX_GPIOxx 1
+
+#endif /* AMD_TURIN_POC_GPIO_H */
diff --git a/src/soc/amd/turin_poc/include/soc/i2c.h b/src/soc/amd/turin_poc/include/soc/i2c.h
new file mode 100644
index 0000000000..de6a07f899
--- /dev/null
+++ b/src/soc/amd/turin_poc/include/soc/i2c.h
@@ -0,0 +1,36 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef AMD_TURIN_POC_I2C_H
+#define AMD_TURIN_POC_I2C_H
+
+#include <gpio.h>
+#include <types.h>
+
+#define GPIO_I2C0_SCL		BIT(0)
+#define GPIO_I2C1_SCL		BIT(1)
+#define GPIO_I2C2_SCL		BIT(2)
+#define GPIO_I2C3_SCL		BIT(3)
+#define GPIO_I2C4_SCL		BIT(4)
+#define GPIO_I2C5_SCL		BIT(5)
+#define GPIO_I2C_MASK		(GPIO_I2C0_SCL | GPIO_I2C1_SCL | \
+				 GPIO_I2C2_SCL | GPIO_I2C3_SCL | \
+				 GPIO_I2C4_SCL | GPIO_I2C5_SCL)
+
+
+#define I2C0_SCL_PIN			GPIO_145
+#define I2C1_SCL_PIN			GPIO_147
+#define I2C2_SCL_PIN			GPIO_149
+#define I2C3_SCL_PIN			GPIO_151
+#define I2C4_SCL_PIN			GPIO_13
+#define I2C5_SCL_PIN			GPIO_19
+
+#define I2C0_SCL_PIN_IOMUX_GPIOxx	GPIO_145_IOMUX_GPIOxx
+#define I2C1_SCL_PIN_IOMUX_GPIOxx	GPIO_147_IOMUX_GPIOxx
+#define I2C2_SCL_PIN_IOMUX_GPIOxx	GPIO_149_IOMUX_GPIOxx
+#define I2C3_SCL_PIN_IOMUX_GPIOxx	GPIO_151_IOMUX_GPIOxx
+#define I2C4_SCL_PIN_IOMUX_GPIOxx	GPIO_13_IOMUX_GPIOxx
+#define I2C5_SCL_PIN_IOMUX_GPIOxx	GPIO_19_IOMUX_GPIOxx
+
+void reset_i2c_peripherals(void);
+
+#endif /* AMD_TURIN_POC_I2C_H */
diff --git a/src/soc/amd/turin_poc/include/soc/iomap.h b/src/soc/amd/turin_poc/include/soc/iomap.h
new file mode 100644
index 0000000000..f1d692121f
--- /dev/null
+++ b/src/soc/amd/turin_poc/include/soc/iomap.h
@@ -0,0 +1,38 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef AMD_TURIN_POC_IOMAP_H
+#define AMD_TURIN_POC_IOMAP_H
+
+#define I2C_MASTER_DEV_COUNT		6
+#define I2C_PERIPHERAL_DEV_COUNT	0
+#define I2C_CTRLR_COUNT			(I2C_MASTER_DEV_COUNT + I2C_PERIPHERAL_DEV_COUNT)
+#define I3C_CTRLR_COUNT			4
+
+#define SPI_BASE_ADDRESS		0xfec10000
+
+/* @Todo : Check these values for Turin */
+
+/* I/O Ranges */
+#define ACPI_IO_BASE			0x0400
+#define  ACPI_CSTATE_CONTROL		(ACPI_IO_BASE + 0x10)
+
+/* FCH AL2AHB Registers */
+#define ALINK_AHB_ADDRESS		0xfedc0000
+
+#define APU_I2C0_BASE			0xfedc2000
+#define APU_I2C1_BASE			0xfedc3000
+#define APU_I2C2_BASE			0xfedc4000
+#define APU_I2C3_BASE			0xfedc5000
+#define APU_I2C4_BASE			0xfedc6000
+#define APU_I2C5_BASE			0xfedcb000
+
+#define APU_UART0_BASE			0xfedc9000
+#define APU_UART1_BASE			0xfedca000
+#define APU_UART2_BASE			0xfedce000
+
+#define APU_I3C0_BASE			0xfedd2000
+#define APU_I3C1_BASE			0xfedd3000
+#define APU_I3C2_BASE			0xfedd4000
+#define APU_I3C3_BASE			0xfedd6000
+
+#endif /* AMD_TURIN_POC_IOMAP_H */
diff --git a/src/soc/amd/turin_poc/include/soc/lpc.h b/src/soc/amd/turin_poc/include/soc/lpc.h
new file mode 100644
index 0000000000..d460701c9e
--- /dev/null
+++ b/src/soc/amd/turin_poc/include/soc/lpc.h
@@ -0,0 +1,16 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef AMD_TURIN_POC_LPC_H
+#define AMD_TURIN_POC_LPC_H
+
+#define SPI_BASE_ADDRESS_REGISTER	0xa0
+#define   SPI_BASE_ALIGNMENT		BIT(8)
+#define   SPI_BASE_RESERVED		(BIT(5) | BIT(6) | BIT(7))
+#define   PSP_SPI_MMIO_SEL		BIT(4)
+#define   ROUTE_TPM_2_SPI		BIT(3)
+#define   SPI_ABORT_ENABLE		BIT(2)
+#define   SPI_ROM_ENABLE		BIT(1)
+#define   SPI_ROM_ALT_ENABLE		BIT(0)
+#define   SPI_PRESERVE_BITS		(BIT(0) | BIT(1) | BIT(2) | BIT(3) | BIT(4))
+
+#endif /* AMD_TURIN_POC_LPC_H */
diff --git a/src/soc/amd/turin_poc/include/soc/msr.h b/src/soc/amd/turin_poc/include/soc/msr.h
new file mode 100644
index 0000000000..ba2c25f997
--- /dev/null
+++ b/src/soc/amd/turin_poc/include/soc/msr.h
@@ -0,0 +1,23 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef AMD_TURIN_POC_MSR_H
+#define AMD_TURIN_POC_MSR_H
+
+#include <cpu/amd/msr.h>
+
+/* MSRC001_00[6B:64] P-state [7:0] bit definitions */
+union pstate_msr {
+	struct {
+		uint64_t cpu_fid_0_7	:  8; /* [ 0.. 7] */
+		uint64_t cpu_dfs_id	:  6; /* [ 8..13] */
+		uint64_t cpu_vid_0_7	:  8; /* [14..21] */
+		uint64_t idd_value	:  8; /* [22..29] */
+		uint64_t idd_div	:  2; /* [30..31] */
+		uint64_t cpu_vid_8	:  1; /* [32..32] */
+		uint64_t		: 30; /* [33..62] */
+		uint64_t pstate_en	:  1; /* [63..63] */
+	};
+	uint64_t raw;
+};
+
+#endif /* AMD_TURIN_POC_MSR_H */
diff --git a/src/soc/amd/turin_poc/include/soc/nvs.h b/src/soc/amd/turin_poc/include/soc/nvs.h
new file mode 100644
index 0000000000..3bbab86cad
--- /dev/null
+++ b/src/soc/amd/turin_poc/include/soc/nvs.h
@@ -0,0 +1,22 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+/* TODO: Check if this is still correct */
+
+/*
+ * NOTE: The layout of the global_nvs structure below must match the layout
+ * in soc/soc/amd/turin_poc/acpi/globalnvs.asl !!!
+ *
+ */
+
+#ifndef AMD_TURIN_POC_NVS_H
+#define AMD_TURIN_POC_NVS_H
+
+#include <stdint.h>
+
+struct __packed global_nvs {
+	/* Miscellaneous */
+	uint64_t	pm1i; /* 0x00 - 0x07 - System Wake Source - PM1 Index */
+	uint64_t	gpei; /* 0x08 - 0x0f - GPE Wake Source */
+};
+
+#endif /* AMD_TURIN_POC_NVS_H */
diff --git a/src/soc/amd/turin_poc/include/soc/pci_devs.h b/src/soc/amd/turin_poc/include/soc/pci_devs.h
new file mode 100644
index 0000000000..a903a4a807
--- /dev/null
+++ b/src/soc/amd/turin_poc/include/soc/pci_devs.h
@@ -0,0 +1,54 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef AMD_TURIN_POC_PCI_DEVS_H
+#define AMD_TURIN_POC_PCI_DEVS_H
+
+#include <device/pci_def.h>
+#include <amdblocks/pci_devs.h>
+
+/* GNB Root Complex */
+#define GNB_DEV			0x0
+#define GNB_FUNC		0
+#define GNB_DEVFN		PCI_DEVFN(GNB_DEV, GNB_FUNC)
+#define SOC_GNB_DEV		_SOC_DEV(GNB_DEV, GNB_FUNC)
+
+/* SMBUS */
+#define SMBUS_DEV		0x14
+#define SMBUS_FUNC		0
+#define SMBUS_DEVFN		PCI_DEVFN(SMBUS_DEV, SMBUS_FUNC)
+#define SOC_SMBUS_DEV		_SOC_DEV(SMBUS_DEV, SMBUS_FUNC)
+
+/* LPC BUS */
+#define PCU_DEV			0x14
+#define LPC_FUNC		3
+#define LPC_DEVFN		PCI_DEVFN(PCU_DEV, LPC_FUNC)
+#define SOC_LPC_DEV		_SOC_DEV(PCU_DEV, LPC_FUNC)
+
+/* Data Fabric functions */
+#define DF_DEV			0x18
+
+#define DF_F0_DEVFN		PCI_DEVFN(DF_DEV, 0)
+#define SOC_DF_F0_DEV		_SOC_DEV(DF_DEV, 0)
+
+#define DF_F1_DEVFN		PCI_DEVFN(DF_DEV, 1)
+#define SOC_DF_F1_DEV		_SOC_DEV(DF_DEV, 1)
+
+#define DF_F2_DEVFN		PCI_DEVFN(DF_DEV, 2)
+#define SOC_DF_F2_DEV		_SOC_DEV(DF_DEV, 2)
+
+#define DF_F3_DEVFN		PCI_DEVFN(DF_DEV, 3)
+#define SOC_DF_F3_DEV		_SOC_DEV(DF_DEV, 3)
+
+#define DF_F4_DEVFN		PCI_DEVFN(DF_DEV, 4)
+#define SOC_DF_F4_DEV		_SOC_DEV(DF_DEV, 4)
+
+#define DF_F5_DEVFN		PCI_DEVFN(DF_DEV, 5)
+#define SOC_DF_F5_DEV		_SOC_DEV(DF_DEV, 5)
+
+#define DF_F6_DEVFN		PCI_DEVFN(DF_DEV, 6)
+#define SOC_DF_F6_DEV		_SOC_DEV(DF_DEV, 6)
+
+#define DF_F7_DEVFN		PCI_DEVFN(DF_DEV, 7)
+#define SOC_DF_F7_DEV		_SOC_DEV(DF_DEV, 7)
+
+#endif /* AMD_TURIN_POC_PCI_DEVS_H */
diff --git a/src/soc/amd/turin_poc/include/soc/smi.h b/src/soc/amd/turin_poc/include/soc/smi.h
new file mode 100644
index 0000000000..df56b6750f
--- /dev/null
+++ b/src/soc/amd/turin_poc/include/soc/smi.h
@@ -0,0 +1,182 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#ifndef AMD_TURIN_POC_SMI_H
+#define AMD_TURIN_POC_SMI_H
+
+#include <types.h>
+
+#define SMI_GEVENTS			24
+#define SCIMAPS				64 /* 0..63 */
+#define SCI_GPES			32
+#define NUMBER_SMITYPES			157
+
+#define SMI_EVENT_STATUS		0x0
+#define SMI_EVENT_ENABLE		0x04
+#define SMI_SCI_TRIG			0x08
+#define SMI_SCI_LEVEL			0x0c
+#define SMI_SCI_STATUS			0x10
+#define SMI_SCI_EN			0x14
+#define SMI_SCI_MAP0			0x40
+# define SMI_SCI_MAP(X)			(SMI_SCI_MAP0 + (X))
+
+/* SMI source and status */
+#define SMITYPE_G_GENINT1_L		0
+#define SMITYPE_G_AGPIO115		1
+#define SMITYPE_G_AGPIO3		2
+#define SMITYPE_G_AGPIO22		3
+#define SMITYPE_G_AGPIO4		4
+#define SMITYPE_G_AGPIO21		5
+#define SMITYPE_G_AGPIO116		6
+#define SMITYPE_G_AGPIO5		7
+#define SMITYPE_G_WAKE_L		8
+#define SMITYPE_G_NMI_SYNC_FLOOD	9
+#define SMITYPE_G_AGPIO6		10
+#define SMITYPE_G_AGPIO76		11
+#define SMITYPE_G_USBOC0_L		12
+#define SMITYPE_G_USBOC1_L		13
+#define SMITYPE_G_SMERR_L		14
+#define SMITYPE_G_PCIE_RST1_L		15
+#define SMITYPE_G_ESPI_RSTOUT_L		16
+#define SMITYPE_G_ESPI_RSTIN_L		17
+#define SMITYPE_G_X48M_OUT		18
+#define SMITYPE_G_SYSRESET_L		19
+#define SMITYPE_G_AGPIO104		20
+#define SMITYPE_G_PWR_BTN_L		21
+#define SMITYPE_G_AGPI105		22
+#define SMITYPE_G_AGPI106		23
+#define GEVENT_MASK ((1 << SMITYPE_G_GENINT1_L)		\
+		   | (1 << SMITYPE_G_AGPIO115)		\
+		   | (1 << SMITYPE_G_AGPIO3)		\
+		   | (1 << SMITYPE_G_AGPIO22)		\
+		   | (1 << SMITYPE_G_AGPIO4)		\
+		   | (1 << SMITYPE_G_AGPIO21)		\
+		   | (1 << SMITYPE_G_AGPIO116)		\
+		   | (1 << SMITYPE_G_AGPIO5)		\
+		   | (1 << SMITYPE_G_WAKE_L)		\
+		   | (1 << SMITYPE_G_NMI_SYNC_FLOOD)	\
+		   | (1 << SMITYPE_G_AGPIO6)		\
+		   | (1 << SMITYPE_G_AGPIO76)		\
+		   | (1 << SMITYPE_G_USBOC0_L)		\
+		   | (1 << SMITYPE_G_USBOC1_L)		\
+		   | (1 << SMITYPE_G_SMERR_L)		\
+		   | (1 << SMITYPE_G_PCIE_RST1_L)	\
+		   | (1 << SMITYPE_G_ESPI_RSTOUT_L)	\
+		   | (1 << SMITYPE_G_ESPI_RSTIN_L)	\
+		   | (1 << SMITYPE_G_X48M_OUT)		\
+		   | (1 << SMITYPE_G_SYSRESET_L)	\
+		   | (1 << SMITYPE_G_AGPIO104)		\
+		   | (1 << SMITYPE_G_PWR_BTN_L)		\
+		   | (1 << SMITYPE_G_AGPI105)		\
+		   | (1 << SMITYPE_G_AGPI106))
+#define SMITYPE_MP2_WAKE		24
+#define SMITYPE_MP2_GPIO0		25
+#define SMITYPE_ESPI_SYS		26
+#define SMITYPE_ESPI_WAKE_PME		27
+#define SMITYPE_MP2_GPIO1		28
+#define SMITYPE_GPP_PME			29
+#define SMITYPE_NB_GPP_HOT_PLUG		30
+/* 31 Reserved */
+#define SMITYPE_WAKE_L2			32
+#define SMITYPE_PSP			33
+/* 34-35 Reserved */
+#define SMITYPE_ESPI_SCI_B		36
+#define SMITYPE_ESPI1_SYS_EVT_B		37
+#define SMITYPE_ESPI1_WAKE_PME		38
+#define SMITYPE_AZPME			39
+#define SMITYPE_USB_PD_I2C4		40
+#define SMITYPE_GPIO_CTL		41
+#define SMITYPE_ESPI1_SCI_B		42
+#define SMITYPE_ALT_HPET_ALARM		43
+#define SMITYPE_FAN_THERMAL		44
+#define SMITYPE_ASF_MASTER_SLAVE	45
+#define SMITYPE_I2S_WAKE		46
+#define SMITYPE_SMBUS0_MASTER		47
+#define SMITYPE_TWARN			48
+#define SMITYPE_TRAFFIC_MON		49
+#define SMITYPE_ILLB			50
+#define SMITYPE_PWRBUTTON_UP		51
+#define SMITYPE_PROCHOT			52
+#define SMITYPE_APU_HW			53
+#define SMITYPE_NB_SCI			54
+#define SMITYPE_RAS_SERR		55
+#define SMITYPE_XHC0_PME		56
+#define SMITYPE_XHC1_PME		57
+#define SMITYPE_ACDC_TIMER		58
+/* 59-63 Reserved */
+#define SMITYPE_KB_RESET		64
+#define SMITYPE_SLP_TYP			65
+#define SMITYPE_AL2H_ACPI		66
+/* 67-71 Reserved */
+#define SMITYPE_GBL_RLS			72
+#define SMITYPE_BIOS_RLS		73
+#define SMITYPE_PWRBUTTON_DOWN		74
+#define SMITYPE_SMI_CMD_PORT		75
+#define SMITYPE_USB_SMI			76
+#define SMITYPE_SERIRQ			77
+#define SMITYPE_SMBUS0_INTR		78
+/* 79-80 Reserved */
+#define SMITYPE_INTRUDER		81
+#define SMITYPE_VBAT_LOW		82
+#define SMITYPE_PROTHOT			83
+#define SMITYPE_PCI_SERR		84
+/* 85-89 Reserved */
+#define SMITYPE_EMUL60_64		90
+/* 91-132 Reserved */
+#define SMITYPE_FANIN0			133
+/* 134-140 Reserved */
+#define SMITYPE_CF9_WRITE		141
+#define SMITYPE_SHORT_TIMER		142
+#define SMITYPE_LONG_TIMER		143
+#define SMITYPE_AB_SMI			144
+/* 145 Reserved */
+#define SMITYPE_ESPI_SMI		146
+#define SMITYPE_ESPI1_SMI		147
+#define SMITYPE_IOTRAP0			148
+#define SMITYPE_IOTRAP1			149
+#define SMITYPE_IOTRAP2			150
+#define SMITYPE_IOTRAP3			151
+#define SMITYPE_MEMTRAP0		152
+/* 153-155 Reserved */
+#define SMITYPE_CFGTRAP0		156
+/* 157-159 Reserved */
+
+#define TYPE_TO_MASK(X)				(1 << (X) % 32)
+
+#define SMI_REG_SMISTS0			0x80
+#define SMI_REG_SMISTS1			0x84
+#define SMI_REG_SMISTS2			0x88
+#define SMI_REG_SMISTS3			0x8c
+#define SMI_REG_SMISTS4			0x90
+
+#define SMI_REG_POINTER			0x94
+# define SMI_STATUS_SRC_SCI			(1 << 0)
+# define SMI_STATUS_SRC_0			(1 << 1) /* SMIx80 */
+# define SMI_STATUS_SRC_1			(1 << 2) /* SMIx84... */
+# define SMI_STATUS_SRC_2			(1 << 3)
+# define SMI_STATUS_SRC_3			(1 << 4)
+# define SMI_STATUS_SRC_4			(1 << 5)
+
+#define SMI_TIMER			0x96
+#define SMI_TIMER_MASK				0x7fff
+#define SMI_TIMER_EN				(1 << 15)
+
+#define SMI_REG_SMITRIG0		0x98
+# define SMITRIG0_PSP				(1 << 25)
+# define SMITRG0_EOS				(1 << 28)
+# define SMI_TIMER_SEL				(1 << 29)
+# define SMITRG0_SMIENB				(1 << 31)
+
+#define SMI_REG_CONTROL0		0xa0
+#define SMI_REG_CONTROL1		0xa4
+#define SMI_REG_CONTROL2		0xa8
+#define SMI_REG_CONTROL3		0xac
+#define SMI_REG_CONTROL4		0xb0
+#define SMI_REG_CONTROL5		0xb4
+#define SMI_REG_CONTROL6		0xb8
+#define SMI_REG_CONTROL7		0xbc
+#define SMI_REG_CONTROL8		0xc0
+#define SMI_REG_CONTROL9		0xc4
+
+#define SMI_MODE_MASK			0x03
+
+#endif /* AMD_TURIN_POC_SMI_H */
diff --git a/src/soc/amd/turin_poc/include/soc/smu.h b/src/soc/amd/turin_poc/include/soc/smu.h
new file mode 100644
index 0000000000..dd34044264
--- /dev/null
+++ b/src/soc/amd/turin_poc/include/soc/smu.h
@@ -0,0 +1,23 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef AMD_GENOA_POC_SMU_H
+#define AMD_GENOA_POC_SMU_H
+
+/* SMU mailbox register offsets in SMN */
+#define SMN_SMU_MESG_ID		0x3b10530
+#define SMN_SMU_MESG_RESP	0x3b1057c
+#define SMN_SMU_MESG_ARGS_BASE	0x3b109c4
+
+#define SMU_NUM_ARGS		6
+
+enum smu_message_id {
+	SMC_MSG_S3ENTRY = 0x0b,
+};
+
+/*
+ * Request the SMU put system into S3, S4, or S5. On entry, SlpTyp determines S-State and
+ * SlpTypeEn gets set by the SMU. Function does not return if successful.
+ */
+void smu_sx_entry(void);
+
+#endif /* AMD_GENOA_POC_SMU_H */
diff --git a/src/soc/amd/turin_poc/include/soc/soc_chip.h b/src/soc/amd/turin_poc/include/soc/soc_chip.h
new file mode 100644
index 0000000000..ab0a094413
--- /dev/null
+++ b/src/soc/amd/turin_poc/include/soc/soc_chip.h
@@ -0,0 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef _SOC_TURIN_POC_SOC_CHIP_H_
+#define _SOC_TURIN_POC_SOC_CHIP_H_
+
+#include "../../chip.h"
+
+#endif /* _SOC_TURIN_POC_SOC_CHIP_H_ */
diff --git a/src/soc/amd/turin_poc/include/soc/southbridge.h b/src/soc/amd/turin_poc/include/soc/southbridge.h
new file mode 100644
index 0000000000..1027a58455
--- /dev/null
+++ b/src/soc/amd/turin_poc/include/soc/southbridge.h
@@ -0,0 +1,122 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef AMD_GENOA_POC_SOUTHBRIDGE_H
+#define AMD_GENOA_POC_SOUTHBRIDGE_H
+
+#include <soc/iomap.h>
+
+/* Power management registers:  0xfed80300 or index/data at IO 0xcd6/cd7 */
+#define PM_ISACONTROL			0x04
+#define   ABCLKGATEEN			BIT(16)
+#define PM_PCI_CTRL			0x08
+#define   FORCE_SLPSTATE_RETRY		BIT(25)
+#define PWR_RESET_CFG			0x10
+#define   TOGGLE_ALL_PWR_GOOD		(1 << 1)
+#define PM_SERIRQ_CONF			0x54
+#define   PM_SERIRQ_NUM_BITS_17		0x0000
+#define   PM_SERIRQ_NUM_BITS_18		0x0004
+#define   PM_SERIRQ_NUM_BITS_19		0x0008
+#define   PM_SERIRQ_NUM_BITS_20		0x000c
+#define   PM_SERIRQ_NUM_BITS_21		0x0010
+#define   PM_SERIRQ_NUM_BITS_22		0x0014
+#define   PM_SERIRQ_NUM_BITS_23		0x0018
+#define   PM_SERIRQ_NUM_BITS_24		0x001c
+#define   PM_SERIRQ_MODE		BIT(6)
+#define   PM_SERIRQ_ENABLE		BIT(7)
+#define PM_EVT_BLK			0x60
+#define   WAK_STS			BIT(15) /*AcpiPmEvtBlkx00 Pm1Status */
+#define   PCIEXPWAK_STS			BIT(14)
+#define   RTC_STS			BIT(10)
+#define   PWRBTN_STS			BIT(8)
+#define   GBL_STS			BIT(5)
+#define   BM_STS			BIT(4)
+#define   TIMER_STS			BIT(0)
+#define   PCIEXPWAK_DIS			BIT(14) /*AcpiPmEvtBlkx02 Pm1Enable */
+#define   RTC_EN			BIT(10)
+#define   PWRBTN_EN			BIT(8)
+#define   GBL_EN			BIT(5)
+#define   TIMER_STS			BIT(0)
+#define PM1_CNT_BLK			0x62
+#define PM_TMR_BLK			0x64
+#define PM_GPE0_BLK			0x68
+#define PM_ACPI_SMI_CMD			0x6a
+#define PM_ACPI_CONF			0x74
+#define   PM_ACPI_DECODE_STD		BIT(0)
+#define   PM_ACPI_GLOBAL_EN		BIT(1)
+#define   PM_ACPI_RTC_EN_EN		BIT(2)
+#define   PM_ACPI_SLPBTN_EN_EN		BIT(3)
+#define   PM_ACPI_TIMER_EN_EN		BIT(4)
+#define   PM_ACPI_MASK_ARB_DIS		BIT(6)
+#define   PM_ACPI_BIOS_RLS		BIT(7)
+#define   PM_ACPI_PWRBTNEN_EN		BIT(8)
+#define   PM_ACPI_REDUCED_HW_EN		BIT(9)
+#define   PM_ACPI_S5_LPC_PIN_MODE_SEL	BIT(10)
+#define   PM_ACPI_S5_LPC_PIN_MODE	BIT(11)
+#define   PM_ACPI_LPC_RST_DIS		BIT(12)
+#define   PM_ACPI_SEL_PWRGD_PAD		BIT(13)
+#define   PM_ACPI_SEL_SMU_THERMTRIP	BIT(14)
+#define   PM_ACPI_SW_S5PWRMUX_OVRD_N	BIT(15)
+#define   PM_ACPI_SW_S5PWRMUX		BIT(16)
+#define   PM_ACPI_EN_SHUTDOWN_MSG	BIT(17)
+#define   PM_ACPI_EN_SYNC_FLOOD		BIT(18)
+#define   PM_ACPI_FORCE_SPIUSEPIN_0	BIT(19)
+#define   PM_ACPI_EN_DF_INTRWAKE	BIT(20)
+#define   PM_ACPI_MASK_USB_S5_RST	BIT(21)
+#define   PM_ACPI_USE_RSMU_RESET	BIT(22)
+#define   PM_ACPI_RST_USB_S5		BIT(23)
+#define   PM_ACPI_BLOCK_PCIE_PME	BIT(24)
+#define   PM_ACPI_PCIE_WAK_MASK		BIT(25)
+#define   PM_ACPI_PCIE_WAK_INTR_DIS	BIT(26)
+#define   PM_ACPI_WAKE_AS_GEVENT	BIT(27)
+#define   PM_ACPI_NB_PME_GEVENT		BIT(28)
+#define   PM_ACPI_RTC_WAKE_EN		BIT(29)
+#define   PM_ACPI_USE_GATED_ALINK_CLK	BIT(30)
+#define   PM_ACPI_DELAY_GPP_OFF_TIME	BIT(31)
+#define PM_SPI_PAD_PU_PD		0x90
+#define   PM_ESPI_CS_USE_DATA2		BIT(16)
+#define PM_LPC_GATING			0xec
+#define   PM_LPC_AB_NO_BYPASS_EN	BIT(2)
+#define   PM_LPC_A20_EN			BIT(1)
+#define   PM_LPC_ENABLE			BIT(0)
+
+#define PM1_LIMIT			16
+#define GPE0_LIMIT			32
+#define TOTAL_BITS(a)			(8 * sizeof(a))
+
+#define FCH_LEGACY_UART_DECODE		(ALINK_AHB_ADDRESS + 0x20) /* 0xfedc0020 */
+
+/* FCH MISC Registers 0xfed80e00 */
+#define GPP_CLK_CNTRL			0x00
+#define   GPP_CLK0_REQ_SHIFT		0
+#define   GPP_CLK1_REQ_SHIFT		2
+#define   GPP_CLK4_REQ_SHIFT		4
+#define   GPP_CLK2_REQ_SHIFT		6
+#define   GPP_CLK3_REQ_SHIFT		8
+#define   GPP_CLK5_REQ_SHIFT		10
+#define   GPP_CLK6_REQ_SHIFT		12
+#define     GPP_CLK_OUTPUT_COUNT	7
+#define     GPP_CLK_OUTPUT_AVAILABLE	4
+#define   GPP_CLK_REQ_MASK(clk_shift)	(0x3 << (clk_shift))
+#define   GPP_CLK_REQ_ON(clk_shift)	(0x3 << (clk_shift))
+#define   GPP_CLK_REQ_EXT(clk_shift)	(0x1 << (clk_shift))
+#define   GPP_CLK_REQ_OFF(clk_shift)	(0x0 << (clk_shift))
+
+#define MISC_CLKGATEDCNTL		0x2c
+#define   ALINKCLK_GATEOFFEN		BIT(16)
+#define   BLINKCLK_GATEOFFEN		BIT(17)
+#define   XTAL_PAD_S0I3_TURNOFF_EN	BIT(19)
+#define   XTAL_PAD_S3_TURNOFF_EN	BIT(20)
+#define   XTAL_PAD_S5_TURNOFF_EN	BIT(21)
+#define MISC_CGPLL_CONFIGURATION0	0x30
+#define   USB_PHY_CMCLK_S3_DIS		BIT(8)
+#define   USB_PHY_CMCLK_S0I3_DIS	BIT(9)
+#define   USB_PHY_CMCLK_S5_DIS		BIT(10)
+#define MISC_CLK_CNTL0			0x40 /* named MISC_CLK_CNTL1 on Picasso */
+#define   BP_X48M0_S0I3_DIS		BIT(4)
+#define   BP_X48M0_OUTPUT_EN		BIT(2) /* 1=En, unlike Hudson, Kern */
+
+void fch_pre_init(void);
+void fch_early_init(void);
+void fch_init(void *chip_info);
+
+#endif /* AMD_GENOA_POC_SOUTHBRIDGE_H */
diff --git a/src/soc/amd/turin_poc/include/soc/uart.h b/src/soc/amd/turin_poc/include/soc/uart.h
new file mode 100644
index 0000000000..a8e18ca918
--- /dev/null
+++ b/src/soc/amd/turin_poc/include/soc/uart.h
@@ -0,0 +1,10 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef AMD_TURIN_POC_UART_H
+#define AMD_TURIN_POC_UART_H
+
+#include <types.h>
+
+void clear_uart_legacy_config(void); /* disable legacy I/O decode for FCH UART */
+
+#endif /* AMD_TURIN_POC_UART_H */
diff --git a/src/soc/amd/turin_poc/mca.c b/src/soc/amd/turin_poc/mca.c
new file mode 100644
index 0000000000..9a6df2b53e
--- /dev/null
+++ b/src/soc/amd/turin_poc/mca.c
@@ -0,0 +1,59 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <amdblocks/mca.h>
+#include <cpu/x86/msr.h>
+#include <types.h>
+
+/* TODO: Check if non-core MCA banks are same for all cores */
+static const char *const mca_bank_name[] = {
+	[0]  = "Load-store unit",
+	[1]  = "Instruction fetch unit",
+	[2]  = "L2 cache unit",
+	[3]  = "Decode unit",
+	[4]  = "",
+	[5]  = "Execution unit",
+	[6]  = "Floating point unit",
+	[7]  = "L3 cache unit",
+	[8]  = "L3 cache unit",
+	[9]  = "L3 cache unit",
+	[10] = "L3 cache unit",
+	[11] = "L3 cache unit",
+	[12] = "L3 cache unit",
+	[13] = "L3 cache unit",
+	[14] = "L3 cache unit",
+	[15] = "Microprocessor5 Management Controller",
+	[16] = "Parameter Block",
+	[17] = "GMI Controller",
+	[18] = "GMI Controller",
+	[19] = "High Speed Interface Unit (GMI)",
+	[20] = "High Speed Interface Unit (GMI)",
+	[21] = "Unified Memory Controller",
+	[22] = "Unified Memory Controller",
+	[23] = "Coherent Station",
+	[24] = "Coherent Station",
+	[25] = "Northbridge IO Unit",
+	[26] = "PCIe Root Port",
+	[27] = "PCIe Root Port",
+	[28] = "Power Management, Interrupts, Etc.",
+	[29] = "SMU",
+	[30] = "XGMI Controller",
+	[31] = "High Speed Interface Unit (XGMI)",
+};
+
+bool mca_has_expected_bank_count(void)
+{
+	return ARRAY_SIZE(mca_bank_name) == mca_get_bank_count();
+}
+
+bool mca_is_valid_bank(unsigned int bank)
+{
+	return (bank < ARRAY_SIZE(mca_bank_name) && mca_bank_name[bank] != NULL);
+}
+
+const char *mca_get_bank_name(unsigned int bank)
+{
+	if (mca_is_valid_bank(bank))
+		return mca_bank_name[bank];
+	else
+		return "";
+}
diff --git a/src/soc/amd/turin_poc/reset.c b/src/soc/amd/turin_poc/reset.c
new file mode 100644
index 0000000000..ac0c981718
--- /dev/null
+++ b/src/soc/amd/turin_poc/reset.c
@@ -0,0 +1,27 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <arch/io.h>
+#include <cf9_reset.h>
+#include <reset.h>
+#include <soc/southbridge.h>
+#include <amdblocks/acpimmio.h>
+#include <amdblocks/reset.h>
+
+void do_cold_reset(void)
+{
+	/* De-assert and then assert all PwrGood signals on CF9 reset. */
+	pm_write16(PWR_RESET_CFG, pm_read16(PWR_RESET_CFG) |
+		TOGGLE_ALL_PWR_GOOD);
+	outb(RST_CPU | SYS_RST, RST_CNT);
+}
+
+void do_warm_reset(void)
+{
+	/* Warm resets are not supported and must be executed as cold */
+	do_cold_reset();
+}
+
+void do_board_reset(void)
+{
+	do_cold_reset();
+}
diff --git a/src/soc/amd/turin_poc/root_complex.c b/src/soc/amd/turin_poc/root_complex.c
new file mode 100644
index 0000000000..3171febe9f
--- /dev/null
+++ b/src/soc/amd/turin_poc/root_complex.c
@@ -0,0 +1,51 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <amdblocks/ioapic.h>
+#include <amdblocks/root_complex.h>
+#include <types.h>
+
+static const struct domain_iohc_info iohc_info[] = {
+	[0] = {
+		.fabric_id = 0x22,
+		.misc_smn_base = SMN_IOHC_MISC_BASE_13C1,
+	},
+	[1] = {
+		.fabric_id = 0x23,
+		.misc_smn_base = SMN_IOHC_MISC_BASE_13B1,
+	},
+	[2] = {
+		.fabric_id = 0x21,
+		.misc_smn_base = SMN_IOHC_MISC_BASE_13E1,
+	},
+	[3] = {
+		.fabric_id = 0x20,
+		.misc_smn_base = SMN_IOHC_MISC_BASE_13D1,
+	},
+};
+
+const struct domain_iohc_info *get_iohc_info(size_t *count)
+{
+	*count = ARRAY_SIZE(iohc_info);
+	return iohc_info;
+}
+
+static const struct non_pci_mmio_reg non_pci_mmio[] = {
+	{ 0x2d8, 0xfffffff00000ull,   1 * MiB, NON_PCI_RES_IDX_AUTO },
+	{ 0x2e0, 0xfffffff00000ull,   1 * MiB, NON_PCI_RES_IDX_AUTO },
+	{ 0x2e8, 0xfffffff00000ull,   1 * MiB, NON_PCI_RES_IDX_AUTO },
+	/* The hardware has a 256 byte alignment requirement for the IOAPIC MMIO base, but we
+	   tell the FSP to configure a 4k-aligned base address and this is reported as 4 KiB
+	   resource. */
+	{ 0x2f0, 0xffffffffff00ull,   4 * KiB, IOMMU_IOAPIC_IDX },
+	{ 0x2f8, 0xfffffff00000ull,   1 * MiB, NON_PCI_RES_IDX_AUTO },
+	{ 0x300, 0xfffffff00000ull,   1 * MiB, NON_PCI_RES_IDX_AUTO },
+	{ 0x308, 0xfffffffff000ull,   4 * KiB, NON_PCI_RES_IDX_AUTO },
+	{ 0x310, 0xfffffff00000ull,   1 * MiB, NON_PCI_RES_IDX_AUTO },
+	{ 0x318, 0xfffffff80000ull, 512 * KiB, NON_PCI_RES_IDX_AUTO },
+};
+
+const struct non_pci_mmio_reg *get_iohc_non_pci_mmio_regs(size_t *count)
+{
+	*count = ARRAY_SIZE(non_pci_mmio);
+	return non_pci_mmio;
+}
diff --git a/src/soc/amd/turin_poc/smihandler.c b/src/soc/amd/turin_poc/smihandler.c
new file mode 100644
index 0000000000..1eb051317b
--- /dev/null
+++ b/src/soc/amd/turin_poc/smihandler.c
@@ -0,0 +1,96 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <acpi/acpi.h>
+#include <amdblocks/acpi.h>
+#include <amdblocks/acpimmio.h>
+#include <amdblocks/psp.h>
+#include <amdblocks/smi.h>
+#include <amdblocks/smm.h>
+#include <arch/hlt.h>
+#include <arch/io.h>
+#include <console/console.h>
+#include <cpu/x86/cache.h>
+#include <cpu/x86/smm.h>
+#include <soc/smi.h>
+#include <soc/smu.h>
+#include <soc/southbridge.h>
+#include <types.h>
+
+/*
+ * Both the psp_notify_sx_info and the smu_sx_entry call will clobber the SMN index register
+ * during the SMN accesses. Since the SMI handler is the last thing that gets called before
+ * entering S3, this won't interfere with any indirect SMN accesses via the same register pair.
+ */
+static void fch_slp_typ_handler(void)
+{
+	uint32_t pci_ctrl;
+	uint16_t pm1cnt;
+	uint8_t slp_typ, rst_ctrl;
+
+	/* Figure out SLP_TYP */
+	pm1cnt = acpi_read16(MMIO_ACPI_PM1_CNT_BLK);
+	printk(BIOS_SPEW, "SMI#: SLP = 0x%04x\n", pm1cnt);
+	slp_typ = acpi_sleep_from_pm1(pm1cnt);
+
+	/* Do any mainboard sleep handling */
+	mainboard_smi_sleep(slp_typ);
+
+	switch (slp_typ) {
+	case ACPI_S0:
+		printk(BIOS_DEBUG, "SMI#: Entering S0 (On)\n");
+		break;
+	case ACPI_S3:
+		printk(BIOS_DEBUG, "SMI#: Entering S3 (Suspend-To-RAM)\n");
+		break;
+	case ACPI_S4:
+		printk(BIOS_DEBUG, "SMI#: Entering S4 (Suspend-To-Disk)\n");
+		break;
+	case ACPI_S5:
+		printk(BIOS_DEBUG, "SMI#: Entering S5 (Soft Power off)\n");
+		break;
+	default:
+		printk(BIOS_DEBUG, "SMI#: ERROR: SLP_TYP reserved\n");
+		break;
+	}
+
+	if (slp_typ >= ACPI_S3) {
+		wbinvd();
+
+		clear_all_smi_status();
+
+		/* Do not send SMI before AcpiPm1CntBlkx00[SlpTyp] */
+		pci_ctrl = pm_read32(PM_PCI_CTRL);
+		pci_ctrl &= ~FORCE_SLPSTATE_RETRY;
+		pm_write32(PM_PCI_CTRL, pci_ctrl);
+
+		/* Enable SlpTyp */
+		rst_ctrl = pm_read8(PM_RST_CTRL1);
+		rst_ctrl |= SLPTYPE_CONTROL_EN;
+		pm_write8(PM_RST_CTRL1, rst_ctrl);
+
+		smu_sx_entry(); /* Leave SlpTypeEn clear, SMU will set */
+		printk(BIOS_ERR, "System did not go to sleep\n");
+		hlt();
+	}
+}
+
+/*
+ * Table of functions supported in the SMI handler.  Note that SMI source setup
+ * in fch.c is unrelated to this list.
+ */
+static const struct smi_sources_t smi_sources[] = {
+	{ .type = SMITYPE_SMI_CMD_PORT, .handler = fch_apmc_smi_handler },
+	{ .type = SMITYPE_SLP_TYP, .handler = fch_slp_typ_handler},
+	{ .type = SMITYPE_PSP, .handler = psp_smi_handler },
+};
+
+void *get_smi_source_handler(int source)
+{
+	size_t i;
+
+	for (i = 0 ; i < ARRAY_SIZE(smi_sources) ; i++)
+		if (smi_sources[i].type == source)
+			return smi_sources[i].handler;
+
+	return NULL;
+}
diff --git a/src/soc/amd/turin_poc/uart.c b/src/soc/amd/turin_poc/uart.c
new file mode 100644
index 0000000000..19f7746bc8
--- /dev/null
+++ b/src/soc/amd/turin_poc/uart.c
@@ -0,0 +1,38 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <device/mmio.h>
+#include <amdblocks/gpio.h>
+#include <amdblocks/uart.h>
+#include <commonlib/helpers.h>
+#include <soc/aoac_defs.h>
+#include <gpio.h>
+#include <soc/iomap.h>
+#include <soc/southbridge.h>
+#include <soc/uart.h>
+#include <types.h>
+
+static const struct soc_uart_ctrlr_info uart_info[] = {
+	[0] =	{ APU_UART0_BASE, FCH_AOAC_DEV_UART0, "FUR0", {
+			PAD_NF(GPIO_136, UART0_RXD, PULL_NONE),
+			PAD_NF(GPIO_138, UART0_TXD, PULL_NONE),
+		} },
+	[1] =	{ APU_UART1_BASE, FCH_AOAC_DEV_UART1, "FUR1", {
+			PAD_NF(GPIO_141, UART1_RXD, PULL_NONE),
+			PAD_NF(GPIO_142, UART1_TXD, PULL_NONE),
+		} },
+	[2] =	{ APU_UART2_BASE, FCH_AOAC_DEV_UART2, "FUR2", {
+			PAD_NF(GPIO_137, UART2_RXD, PULL_NONE),
+			PAD_NF(GPIO_135, UART2_TXD, PULL_NONE),
+		} },
+};
+
+const struct soc_uart_ctrlr_info *soc_get_uart_ctrlr_info(size_t *num_ctrlrs)
+{
+	*num_ctrlrs = ARRAY_SIZE(uart_info);
+	return uart_info;
+}
+
+void clear_uart_legacy_config(void)
+{
+	write16((void *)FCH_LEGACY_UART_DECODE, 0);
+}

From a73db6d45112976d8d5066841aa9f17bc1a77c00 Mon Sep 17 00:00:00 2001
From: Bora Guvendik <bora.guvendik@intel.com>
Date: Mon, 30 Jun 2025 19:53:21 -0700
Subject: [PATCH 2332/3886] mb/intel/ptlrvp: Add fw_config support for SPD
 selection
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Add firmware configuration support for SPD (Serial Presence Detect)
selection on Intel PTLRVP boards. This change allows dynamic memory
configuration based on fw_config fields instead of relying solely on
board ID detection.

BUG=None
TEST=Build and verify SPD selection works correctly on PTLRVP boards
with different memory configurations.

Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Change-Id: I3cc45ad9813bef09718fe679bfafb700024586f9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88255
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 .../intel/ptlrvp/variants/baseboard/ptlrvp/memory.c       | 8 +++++++-
 .../intel/ptlrvp/variants/ptlrvp/overridetree.cb          | 6 ++++++
 .../intel/ptlrvp/variants/ptlrvp_chromeec/overridetree.cb | 6 ++++++
 3 files changed, 19 insertions(+), 1 deletion(-)

diff --git a/src/mainboard/intel/ptlrvp/variants/baseboard/ptlrvp/memory.c b/src/mainboard/intel/ptlrvp/variants/baseboard/ptlrvp/memory.c
index 757aafd46e..3a79429f03 100644
--- a/src/mainboard/intel/ptlrvp/variants/baseboard/ptlrvp/memory.c
+++ b/src/mainboard/intel/ptlrvp/variants/baseboard/ptlrvp/memory.c
@@ -2,6 +2,7 @@
 
 #include <baseboard/variants.h>
 #include <ec/intel/board_id.h>
+#include <fw_config.h>
 
 static const struct mb_cfg baseboard_memcfg = {
 	.type = MEM_TYPE_LP5X,
@@ -22,7 +23,12 @@ int __weak variant_memory_sku(void)
 
 	printk(BIOS_INFO, "Board ID is 0x%x\n", board_id);
 
-	spd_index = (board_id == GCS_32GB || board_id == GCS_64GB) ? 1 : 0;
+	if (board_id == GCS_32GB || board_id == GCS_64GB)
+		spd_index = 1;
+	else
+		spd_index = fw_config_get_field(FW_CONFIG_FIELD(SPD));
+
+	printk(BIOS_INFO, "SPD index: %zu\n", spd_index);
 
 	return spd_index;
 }
diff --git a/src/mainboard/intel/ptlrvp/variants/ptlrvp/overridetree.cb b/src/mainboard/intel/ptlrvp/variants/ptlrvp/overridetree.cb
index f88f10f522..4cb063bab7 100644
--- a/src/mainboard/intel/ptlrvp/variants/ptlrvp/overridetree.cb
+++ b/src/mainboard/intel/ptlrvp/variants/ptlrvp/overridetree.cb
@@ -67,6 +67,12 @@ fw_config
 		option ISH_DISABLE		0
 		option ISH_ENABLE		1
 	end
+	field SPD 25 26
+		option MEM_H58G56BK7BX068	0
+		option MEM_H58G66BK8BX067	1
+		option MEM_H58G56BK8BX068	2
+		option MEM_H58G66BK7BX067       3
+	end
 end
 
 chip soc/intel/pantherlake
diff --git a/src/mainboard/intel/ptlrvp/variants/ptlrvp_chromeec/overridetree.cb b/src/mainboard/intel/ptlrvp/variants/ptlrvp_chromeec/overridetree.cb
index a3f2eaf5eb..19785ecc7c 100644
--- a/src/mainboard/intel/ptlrvp/variants/ptlrvp_chromeec/overridetree.cb
+++ b/src/mainboard/intel/ptlrvp/variants/ptlrvp_chromeec/overridetree.cb
@@ -67,6 +67,12 @@ fw_config
 		option ISH_DISABLE		0
 		option ISH_ENABLE		1
 	end
+	field SPD 25 26
+		option MEM_H58G56BK7BX068       0
+		option MEM_H58G66BK8BX067       1
+		option MEM_H58G56BK8BX068       2
+		option MEM_H58G66BK7BX067       3
+        end
 end
 
 chip soc/intel/pantherlake

From d97644dd3fe7e830db95b95e00bb5274e4b72fc7 Mon Sep 17 00:00:00 2001
From: Riku Viitanen <riku.viitanen@protonmail.com>
Date: Wed, 25 Dec 2024 23:38:42 +0200
Subject: [PATCH 2333/3886] mb/asrock: Add Z77 Extreme4

New port based on logs extracted from a board running OEM firmware.
VBT extracted from a running system with "intelvbttool --inlegacy".

Internal flashing of the entire chip is possible from vendor firmware
by overriding the Flash Descriptor. Conveniently, the HDA_SDO pin is
connected to one of the unused pins of the PCIE1 slot.

Tested:
- i7-3770K CPU (native raminit)
- 2x8GB: G.skill F3-1600C9-8GAR (@1600MHz)
- 4x8GB: Corsair CMY16GX3M2A2400C (@1333MHz)
- libgfxinit txtmode with onboard HDMI, DVI and VGA
- Gigabit Ethernet
- CPU fan
- PS/2 keyboard or mouse (but not at the same time)
- SeaBIOS 1.17.0 booting to Devuan and Void Linux
- All internal SATA ports
- Rear USB ports
- Line out
- me_cleaner
- PCIE2 (x16/x8), PCIE3 (x8) and PCIE4 (x1) slots
- PCI slots
- Suspend and resume (S3)
- Serial port header COM1 (including coreboot output)

Untested:
- Intel VBIOS
- Front USB headers
- Other fans
- LED headers
- eSATA, Toslink
- PCIE1 (x1) slot

Change-Id: Idf028c6d411bd501b73a3c526240d0b1d6ecaa0c
Signed-off-by: Riku Viitanen <riku.viitanen@protonmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85772
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
---
 src/mainboard/asrock/z77_extreme4/Kconfig     |  32 ++++
 .../asrock/z77_extreme4/Kconfig.name          |   4 +
 src/mainboard/asrock/z77_extreme4/Makefile.mk |   8 +
 src/mainboard/asrock/z77_extreme4/acpi/ec.asl |   3 +
 .../asrock/z77_extreme4/acpi/platform.asl     |  10 +
 .../asrock/z77_extreme4/acpi/superio.asl      |  11 ++
 .../asrock/z77_extreme4/board_info.txt        |   7 +
 .../asrock/z77_extreme4/cmos.default          |   8 +
 src/mainboard/asrock/z77_extreme4/cmos.layout |  86 +++++++++
 src/mainboard/asrock/z77_extreme4/data.vbt    | Bin 0 -> 3902 bytes
 .../asrock/z77_extreme4/devicetree.cb         | 168 ++++++++++++++++
 src/mainboard/asrock/z77_extreme4/dsdt.asl    |  28 +++
 .../asrock/z77_extreme4/early_init.c          |  12 ++
 .../asrock/z77_extreme4/gma-mainboard.ads     |  17 ++
 src/mainboard/asrock/z77_extreme4/gpio.c      | 179 ++++++++++++++++++
 src/mainboard/asrock/z77_extreme4/hda_verb.c  |  52 +++++
 src/mainboard/asrock/z77_extreme4/mainboard.c |  15 ++
 17 files changed, 640 insertions(+)
 create mode 100644 src/mainboard/asrock/z77_extreme4/Kconfig
 create mode 100644 src/mainboard/asrock/z77_extreme4/Kconfig.name
 create mode 100644 src/mainboard/asrock/z77_extreme4/Makefile.mk
 create mode 100644 src/mainboard/asrock/z77_extreme4/acpi/ec.asl
 create mode 100644 src/mainboard/asrock/z77_extreme4/acpi/platform.asl
 create mode 100644 src/mainboard/asrock/z77_extreme4/acpi/superio.asl
 create mode 100644 src/mainboard/asrock/z77_extreme4/board_info.txt
 create mode 100644 src/mainboard/asrock/z77_extreme4/cmos.default
 create mode 100644 src/mainboard/asrock/z77_extreme4/cmos.layout
 create mode 100644 src/mainboard/asrock/z77_extreme4/data.vbt
 create mode 100644 src/mainboard/asrock/z77_extreme4/devicetree.cb
 create mode 100644 src/mainboard/asrock/z77_extreme4/dsdt.asl
 create mode 100644 src/mainboard/asrock/z77_extreme4/early_init.c
 create mode 100644 src/mainboard/asrock/z77_extreme4/gma-mainboard.ads
 create mode 100644 src/mainboard/asrock/z77_extreme4/gpio.c
 create mode 100644 src/mainboard/asrock/z77_extreme4/hda_verb.c
 create mode 100644 src/mainboard/asrock/z77_extreme4/mainboard.c

diff --git a/src/mainboard/asrock/z77_extreme4/Kconfig b/src/mainboard/asrock/z77_extreme4/Kconfig
new file mode 100644
index 0000000000..0bc40152fa
--- /dev/null
+++ b/src/mainboard/asrock/z77_extreme4/Kconfig
@@ -0,0 +1,32 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
+if BOARD_ASROCK_Z77_EXTREME4
+
+config BOARD_SPECIFIC_OPTIONS
+	def_bool y
+	select BOARD_ROMSIZE_KB_8192
+	select DRIVERS_ASMEDIA_ASM1061
+	select HAVE_ACPI_RESUME
+	select HAVE_ACPI_TABLES
+	select HAVE_CMOS_DEFAULT
+	select HAVE_OPTION_TABLE
+	select INTEL_GMA_HAVE_VBT
+	select INTEL_INT15
+	select MAINBOARD_HAS_LIBGFXINIT
+	select NORTHBRIDGE_INTEL_SANDYBRIDGE
+	select SERIRQ_CONTINUOUS_MODE
+	select SOUTHBRIDGE_INTEL_C216
+	select SUPERIO_NUVOTON_COMMON_COM_A
+	select SUPERIO_NUVOTON_NCT6776
+	select USE_NATIVE_RAMINIT
+
+config CBFS_SIZE
+	default 0x600000
+
+config MAINBOARD_DIR
+	default "asrock/z77_extreme4"
+
+config MAINBOARD_PART_NUMBER
+	default "Z77 Extreme4"
+
+endif
diff --git a/src/mainboard/asrock/z77_extreme4/Kconfig.name b/src/mainboard/asrock/z77_extreme4/Kconfig.name
new file mode 100644
index 0000000000..e057b6e67d
--- /dev/null
+++ b/src/mainboard/asrock/z77_extreme4/Kconfig.name
@@ -0,0 +1,4 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
+config BOARD_ASROCK_Z77_EXTREME4
+	bool "Z77 Extreme4"
diff --git a/src/mainboard/asrock/z77_extreme4/Makefile.mk b/src/mainboard/asrock/z77_extreme4/Makefile.mk
new file mode 100644
index 0000000000..e4b6fbf0f0
--- /dev/null
+++ b/src/mainboard/asrock/z77_extreme4/Makefile.mk
@@ -0,0 +1,8 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
+bootblock-y += gpio.c
+romstage-y += gpio.c
+
+ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads
+bootblock-y += early_init.c
+romstage-y += early_init.c
diff --git a/src/mainboard/asrock/z77_extreme4/acpi/ec.asl b/src/mainboard/asrock/z77_extreme4/acpi/ec.asl
new file mode 100644
index 0000000000..16990d45f4
--- /dev/null
+++ b/src/mainboard/asrock/z77_extreme4/acpi/ec.asl
@@ -0,0 +1,3 @@
+/* SPDX-License-Identifier: CC-PDDC */
+
+/* Please update the license if adding licensable material. */
diff --git a/src/mainboard/asrock/z77_extreme4/acpi/platform.asl b/src/mainboard/asrock/z77_extreme4/acpi/platform.asl
new file mode 100644
index 0000000000..a56d3190bd
--- /dev/null
+++ b/src/mainboard/asrock/z77_extreme4/acpi/platform.asl
@@ -0,0 +1,10 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+Method(_WAK,1)
+{
+	Return(Package(){0,0})
+}
+
+Method(_PTS,1)
+{
+}
diff --git a/src/mainboard/asrock/z77_extreme4/acpi/superio.asl b/src/mainboard/asrock/z77_extreme4/acpi/superio.asl
new file mode 100644
index 0000000000..1eae4b21da
--- /dev/null
+++ b/src/mainboard/asrock/z77_extreme4/acpi/superio.asl
@@ -0,0 +1,11 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#undef SUPERIO_DEV
+#undef SUPERIO_PNP_BASE
+#define SUPERIO_DEV		SIO0
+#define SUPERIO_PNP_BASE	0x2e
+
+#define NCT6776_SHOW_SP1	1
+#define NCT6776_SHOW_KBC	1
+
+#include "superio/nuvoton/nct6776/acpi/superio.asl"
diff --git a/src/mainboard/asrock/z77_extreme4/board_info.txt b/src/mainboard/asrock/z77_extreme4/board_info.txt
new file mode 100644
index 0000000000..3819c563b2
--- /dev/null
+++ b/src/mainboard/asrock/z77_extreme4/board_info.txt
@@ -0,0 +1,7 @@
+Category: desktop
+Board URL: https://www.asrock.com/mb/Intel/Z77%20Extreme4/
+ROM protocol: SPI
+Flashrom support: y
+ROM package: DIP-8
+ROM socketed: y
+Release year: 2012
diff --git a/src/mainboard/asrock/z77_extreme4/cmos.default b/src/mainboard/asrock/z77_extreme4/cmos.default
new file mode 100644
index 0000000000..4501aa4904
--- /dev/null
+++ b/src/mainboard/asrock/z77_extreme4/cmos.default
@@ -0,0 +1,8 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
+boot_option=Fallback
+debug_level=Debug
+nmi=Disable
+power_on_after_fail=Disable
+sata_mode=AHCI
+gfx_uma_size=64M
diff --git a/src/mainboard/asrock/z77_extreme4/cmos.layout b/src/mainboard/asrock/z77_extreme4/cmos.layout
new file mode 100644
index 0000000000..0f9de5ed18
--- /dev/null
+++ b/src/mainboard/asrock/z77_extreme4/cmos.layout
@@ -0,0 +1,86 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
+# -----------------------------------------------------------------
+entries
+
+# -----------------------------------------------------------------
+0	120	r	0	reserved_memory
+
+# -----------------------------------------------------------------
+# RTC_BOOT_BYTE (coreboot hardcoded)
+384	1	e	2	boot_option
+388	4	h	0	reboot_counter
+
+# -----------------------------------------------------------------
+# coreboot config options: console
+395	4	e	3	debug_level
+
+# coreboot config options: southbridge
+408	1	e	1	nmi
+
+409	2	e	4	power_on_after_fail
+411	2	e	5	sata_mode
+
+# coreboot config options: northbridge
+416	5	e	6	gfx_uma_size
+
+# coreboot config options: check sums
+984	16	h	0	check_sum
+
+# -----------------------------------------------------------------
+
+enumerations
+#ID	value	text
+
+# Generic on/off enum
+1	0	Disable
+1	1	Enable
+
+# boot_option
+2	0	Fallback
+2	1	Normal
+
+# debug_level
+3	0	Emergency
+3	1	Alert
+3	2	Critical
+3	3	Error
+3	4	Warning
+3	5	Notice
+3	6	Info
+3	7	Debug
+3	8	Spew
+
+# power_on_after_fail
+4	0	Disable
+4	1	Enable
+4	2	Keep
+
+# sata_mode
+5	0	AHCI
+5	1	Compatible
+5	2	Legacy
+
+# gfx_uma_size (Intel IGP Video RAM size)
+6	0	32M
+6	1	64M
+6	2	96M
+6	3	128M
+6	4	160M
+6	5	192M
+6	6	224M
+6	7	256M
+6	8	288M
+6	9	320M
+6	10	352M
+6	11	384M
+6	12	416M
+6	13	448M
+6	14	480M
+6	15	512M
+6	16	1024M
+
+# -----------------------------------------------------------------
+checksums
+
+checksum 392 423 984
diff --git a/src/mainboard/asrock/z77_extreme4/data.vbt b/src/mainboard/asrock/z77_extreme4/data.vbt
new file mode 100644
index 0000000000000000000000000000000000000000..7c43dcf8fece1203883fd8aa78cc0de1ae6e9125
GIT binary patch
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diff --git a/src/mainboard/asrock/z77_extreme4/devicetree.cb b/src/mainboard/asrock/z77_extreme4/devicetree.cb
new file mode 100644
index 0000000000..17b2195743
--- /dev/null
+++ b/src/mainboard/asrock/z77_extreme4/devicetree.cb
@@ -0,0 +1,168 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+chip northbridge/intel/sandybridge
+	register "spd_addresses" = "{0x50, 0x51, 0x52, 0x53}"
+	device domain 0 on
+		device ref host_bridge on
+			subsystemid 0x1849 0x0150
+		end
+		device ref peg10 on
+			subsystemid 0x1849 0x0151
+			smbios_slot_desc "SlotTypePciExpressGen3X16" "SlotLengthLong"
+			                 "PCIE2" "SlotDataBusWidth16X"
+		end
+		device ref peg11 on
+			subsystemid 0x1849 0x0155
+			smbios_slot_desc "SlotTypePciExpressGen3X16" "SlotLengthLong"
+			                 "PCIE3" "SlotDataBusWidth8X"
+		end
+		device ref igd on
+			subsystemid 0x1849 0x0162
+			register "gpu_dp_b_hotplug" = "4"
+			register "gpu_dp_c_hotplug" = "4"
+			register "gpu_dp_d_hotplug" = "4"
+		end
+		chip southbridge/intel/bd82x6x # Intel Series 7 Panther Point PCH
+			register "pcie_port_coalesce" = "1"
+			register "spi_lvscc" = "0x2005"
+			register "spi_uvscc" = "0x2005"
+			register "usb_port_config" = "{
+				{1, 6, 0},
+				{1, 6, 0},
+				{1, 1, 1},
+				{1, 1, 1},
+				{1, 1, 2},
+				{1, 1, 2},
+				{1, 6, 3},
+				{1, 6, 3},
+				{1, 6, 4},
+				{1, 6, 4},
+				{1, 6, 6},
+				{1, 1, 5},
+				{1, 1, 5},
+				{1, 6, 6},
+			}"
+			device ref xhci on
+				subsystemid 0x1849 0x1e31
+				register "superspeed_capable_ports" = "0x0000000f"
+				register "xhci_switchable_ports" = "0x0000000f"
+			end
+			device ref mei1 on
+				subsystemid 0x1849 0x1e3a
+			end
+			device ref ehci2 on
+				subsystemid 0x1849 0x1e2d
+			end
+			device ref hda on
+				subsystemid 0x1849 0x1898
+			end
+			device ref pcie_rp1 on  # PCIe x1 slot, "PCIE4"
+				subsystemid 0x1849 0x1e10
+				smbios_slot_desc "SlotTypePciExpressGen2X1" "SlotLengthShort"
+				                 "PCIE4" "SlotDataBusWidth1X"
+			end
+			device ref pcie_rp4 on  # ASM1061 SATA Controller
+				subsystemid 0x1849 0x1e16
+				device pci 00.0 on end
+			end
+			device ref pcie_rp5 on  # BCM57781 GbE NIC
+				subsystemid 0x1849 0x1e18
+				device pci 00.0 on end
+			end
+			device ref pcie_rp6 on  # ASM1083 PCI bridge
+				subsystemid 0x1849 0x1e1a
+				device pci 00.0 on end
+			end
+			device ref pcie_rp7 on  # PCIe x1 slot, "PCIE1"
+				smbios_slot_desc "SlotTypePciExpressGen2X1" "SlotLengthShort"
+				                 "PCIE1" "SlotDataBusWidth16X"
+			end
+			device ref pcie_rp8 on  # ASM1042 USB 3.0 Controller
+				subsystemid 0x1849 0x1e1e
+				device pci 00.0 on end
+			end
+			device ref ehci1 on
+				subsystemid 0x1849 0x1e26
+			end
+			device ref lpc on
+				subsystemid 0x1849 0x1e44
+				register "gen1_dec" = "0x000c0291"
+				register "gen2_dec" = "0x000c0241"
+				register "gen3_dec" = "0x000c0251"
+				chip superio/nuvoton/nct6776
+					device pnp 2e.0 off end	 # Floppy
+					device pnp 2e.1 off end  # Parallel port
+					device pnp 2e.2 on  # COM1
+						# global
+						irq 0x13 = 0xff
+						irq 0x14 = 0xff
+						irq 0x1a = 0xf8
+						irq 0x1b = 0x0e
+						irq 0x24 = 0x5c
+						irq 0x27 = 0xd8
+						irq 0x2a = 0x62
+						irq 0x2c = 0x80
+						# COM1
+						io 0x60 = 0x3f8
+					end
+					device pnp 2e.3 on  # COM2, IR
+						io 0x60 = 0x2f8
+						irq 0xf1 = 0x5c
+					end
+					device pnp 2e.5 on
+						io 0x60 = 0x60
+						io 0x62 = 0x64
+						irq 0x70 = 0x01
+						irq 0x72 = 0x0c
+					end
+					device pnp 2e.6 off end  # CIR
+					device pnp 2e.7 on  # GPIO 6-9
+						irq 0x30 = 0x00
+						irq 0xe8 = 0xff
+						irq 0xea = 0xff
+						irq 0xf6 = 0xff
+						irq 0xf8 = 0xff
+					end
+					device pnp 2e.8 on  # WDT1, GPIO0-1, GPIOA
+						irq 0x30 = 0x00
+						irq 0xe2 = 0xff
+						irq 0xf0 = 0xb0
+						irq 0xf1 = 0x01
+					end
+					device pnp 2e.9 on  # GPIO2-5
+						irq 0x30 = 0xb6
+						irq 0xe0 = 0xff
+						irq 0xe6 = 0xff
+						irq 0xea = 0xff
+					end
+					device pnp 2e.a on  # ACPI
+						irq 0xe3 = 0x01
+						irq 0xe4 = 0x10
+						irq 0xe6 = 0x4c
+						irq 0xf0 = 0x20
+					end
+					device pnp 2e.b on  # HWM, front panel LED
+						irq 0x30 = 0xe1
+						io 0x60 = 0x290
+					end
+					device pnp 2e.d on end  # VID
+					device pnp 2e.e off end  # CIR wake-up
+					device pnp 2e.f on end   # GPIO push-pull or open drain
+					device pnp 2e.14 on end  # SVID
+					device pnp 2e.16 off  # Deep Sleep
+						irq 0x30 = 0x68
+					end
+					device pnp 2e.17 off end  # GPIOA
+				end
+			end
+			device ref sata1 on
+				subsystemid 0x1849 0x1e02
+				register "sata_interface_speed_support" = "0x3"
+				register "sata_port_map" = "0x3f"
+			end
+			device ref smbus on
+				subsystemid 0x1849 0x1e22
+			end
+		end
+	end
+end
diff --git a/src/mainboard/asrock/z77_extreme4/dsdt.asl b/src/mainboard/asrock/z77_extreme4/dsdt.asl
new file mode 100644
index 0000000000..e69210a83f
--- /dev/null
+++ b/src/mainboard/asrock/z77_extreme4/dsdt.asl
@@ -0,0 +1,28 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <acpi/acpi.h>
+DefinitionBlock(
+	"dsdt.aml",
+	"DSDT",
+	ACPI_DSDT_REV_2,
+	OEM_ID,
+	ACPI_TABLE_CREATOR,
+	0x20141018
+)
+{
+	#include <acpi/dsdt_top.asl>
+	#include "acpi/platform.asl"
+	#include <cpu/intel/common/acpi/cpu.asl>
+	#include <southbridge/intel/common/acpi/platform.asl>
+	#include <southbridge/intel/bd82x6x/acpi/globalnvs.asl>
+	#include <southbridge/intel/common/acpi/sleepstates.asl>
+
+	Scope (\_SB)
+	{
+		Device (PCI0)
+		{
+			#include <northbridge/intel/sandybridge/acpi/sandybridge.asl>
+			#include <southbridge/intel/bd82x6x/acpi/pch.asl>
+		}
+	}
+}
diff --git a/src/mainboard/asrock/z77_extreme4/early_init.c b/src/mainboard/asrock/z77_extreme4/early_init.c
new file mode 100644
index 0000000000..ed381c0e7c
--- /dev/null
+++ b/src/mainboard/asrock/z77_extreme4/early_init.c
@@ -0,0 +1,12 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <bootblock_common.h>
+#include <superio/nuvoton/nct6776/nct6776.h>
+#include <superio/nuvoton/common/nuvoton.h>
+
+void bootblock_mainboard_early_init(void)
+{
+	/* Enable early serial */
+	if (CONFIG(CONSOLE_SERIAL))
+		nuvoton_enable_serial(NCT6776_SP1, CONFIG_TTYS0_BASE);
+}
diff --git a/src/mainboard/asrock/z77_extreme4/gma-mainboard.ads b/src/mainboard/asrock/z77_extreme4/gma-mainboard.ads
new file mode 100644
index 0000000000..3f217ca730
--- /dev/null
+++ b/src/mainboard/asrock/z77_extreme4/gma-mainboard.ads
@@ -0,0 +1,17 @@
+-- SPDX-License-Identifier: GPL-2.0-or-later
+
+with HW.GFX.GMA;
+with HW.GFX.GMA.Display_Probing;
+
+use HW.GFX.GMA;
+use HW.GFX.GMA.Display_Probing;
+
+private package GMA.Mainboard is
+
+   ports : constant Port_List :=
+     (HDMI1, -- mainboard DVI port
+      HDMI3, -- mainboard HDMI port
+      Analog,
+      others => Disabled);
+
+end GMA.Mainboard;
diff --git a/src/mainboard/asrock/z77_extreme4/gpio.c b/src/mainboard/asrock/z77_extreme4/gpio.c
new file mode 100644
index 0000000000..7dae62c27b
--- /dev/null
+++ b/src/mainboard/asrock/z77_extreme4/gpio.c
@@ -0,0 +1,179 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <southbridge/intel/common/gpio.h>
+
+static const struct pch_gpio_set1 pch_gpio_set1_mode = {
+	.gpio0 = GPIO_MODE_GPIO,
+	.gpio1 = GPIO_MODE_GPIO,
+	.gpio2 = GPIO_MODE_NATIVE,
+	.gpio3 = GPIO_MODE_NATIVE,
+	.gpio4 = GPIO_MODE_NATIVE,
+	.gpio5 = GPIO_MODE_NATIVE,
+	.gpio6 = GPIO_MODE_GPIO,
+	.gpio7 = GPIO_MODE_GPIO,
+	.gpio8 = GPIO_MODE_GPIO,
+	.gpio9 = GPIO_MODE_NATIVE,
+	.gpio10 = GPIO_MODE_NATIVE,
+	.gpio11 = GPIO_MODE_NATIVE,
+	.gpio12 = GPIO_MODE_GPIO,
+	.gpio13 = GPIO_MODE_GPIO,
+	.gpio14 = GPIO_MODE_GPIO,
+	.gpio15 = GPIO_MODE_GPIO,
+	.gpio16 = GPIO_MODE_GPIO,
+	.gpio17 = GPIO_MODE_GPIO,
+	.gpio18 = GPIO_MODE_NATIVE,
+	.gpio19 = GPIO_MODE_NATIVE,
+	.gpio20 = GPIO_MODE_NATIVE,
+	.gpio21 = GPIO_MODE_NATIVE,
+	.gpio22 = GPIO_MODE_NATIVE,
+	.gpio23 = GPIO_MODE_NATIVE,
+	.gpio24 = GPIO_MODE_GPIO,
+	.gpio25 = GPIO_MODE_NATIVE,
+	.gpio26 = GPIO_MODE_NATIVE,
+	.gpio27 = GPIO_MODE_GPIO,
+	.gpio28 = GPIO_MODE_GPIO,
+	.gpio29 = GPIO_MODE_GPIO,
+	.gpio30 = GPIO_MODE_NATIVE,
+	.gpio31 = GPIO_MODE_GPIO,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_direction = {
+	.gpio0 = GPIO_DIR_INPUT,
+	.gpio1 = GPIO_DIR_INPUT,
+	.gpio6 = GPIO_DIR_INPUT,
+	.gpio7 = GPIO_DIR_INPUT,
+	.gpio8 = GPIO_DIR_OUTPUT,
+	.gpio12 = GPIO_DIR_INPUT,
+	.gpio13 = GPIO_DIR_INPUT,
+	.gpio14 = GPIO_DIR_OUTPUT,
+	.gpio15 = GPIO_DIR_OUTPUT,
+	.gpio16 = GPIO_DIR_INPUT,
+	.gpio17 = GPIO_DIR_INPUT,
+	.gpio24 = GPIO_DIR_OUTPUT,
+	.gpio27 = GPIO_DIR_INPUT,
+	.gpio28 = GPIO_DIR_OUTPUT,
+	.gpio29 = GPIO_DIR_OUTPUT,
+	.gpio31 = GPIO_DIR_INPUT,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_level = {
+	.gpio8 = GPIO_LEVEL_HIGH,
+	.gpio14 = GPIO_LEVEL_HIGH,
+	.gpio15 = GPIO_LEVEL_LOW,
+	.gpio24 = GPIO_LEVEL_LOW,
+	.gpio28 = GPIO_LEVEL_LOW,
+	.gpio29 = GPIO_LEVEL_HIGH,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_reset = {
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_invert = {
+	.gpio12 = GPIO_INVERT,
+	.gpio13 = GPIO_INVERT,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_blink = {
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_mode = {
+	.gpio32 = GPIO_MODE_GPIO,
+	.gpio33 = GPIO_MODE_GPIO,
+	.gpio34 = GPIO_MODE_GPIO,
+	.gpio35 = GPIO_MODE_NATIVE,
+	.gpio36 = GPIO_MODE_NATIVE,
+	.gpio37 = GPIO_MODE_NATIVE,
+	.gpio38 = GPIO_MODE_NATIVE,
+	.gpio39 = GPIO_MODE_NATIVE,
+	.gpio40 = GPIO_MODE_NATIVE,
+	.gpio41 = GPIO_MODE_NATIVE,
+	.gpio42 = GPIO_MODE_NATIVE,
+	.gpio43 = GPIO_MODE_NATIVE,
+	.gpio44 = GPIO_MODE_NATIVE,
+	.gpio45 = GPIO_MODE_NATIVE,
+	.gpio46 = GPIO_MODE_NATIVE,
+	.gpio47 = GPIO_MODE_NATIVE,
+	.gpio48 = GPIO_MODE_NATIVE,
+	.gpio49 = GPIO_MODE_GPIO,
+	.gpio50 = GPIO_MODE_NATIVE,
+	.gpio51 = GPIO_MODE_NATIVE,
+	.gpio52 = GPIO_MODE_NATIVE,
+	.gpio53 = GPIO_MODE_NATIVE,
+	.gpio54 = GPIO_MODE_NATIVE,
+	.gpio55 = GPIO_MODE_NATIVE,
+	.gpio56 = GPIO_MODE_NATIVE,
+	.gpio57 = GPIO_MODE_GPIO,
+	.gpio58 = GPIO_MODE_NATIVE,
+	.gpio59 = GPIO_MODE_NATIVE,
+	.gpio60 = GPIO_MODE_NATIVE,
+	.gpio61 = GPIO_MODE_NATIVE,
+	.gpio62 = GPIO_MODE_NATIVE,
+	.gpio63 = GPIO_MODE_NATIVE,
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_direction = {
+	.gpio32 = GPIO_DIR_OUTPUT,
+	.gpio33 = GPIO_DIR_OUTPUT,
+	.gpio34 = GPIO_DIR_INPUT,
+	.gpio49 = GPIO_DIR_INPUT,
+	.gpio57 = GPIO_DIR_INPUT,
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_level = {
+	.gpio32 = GPIO_LEVEL_HIGH,
+	.gpio33 = GPIO_LEVEL_HIGH,
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_reset = {
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_mode = {
+	.gpio64 = GPIO_MODE_NATIVE,
+	.gpio65 = GPIO_MODE_NATIVE,
+	.gpio66 = GPIO_MODE_NATIVE,
+	.gpio67 = GPIO_MODE_NATIVE,
+	.gpio68 = GPIO_MODE_GPIO,
+	.gpio69 = GPIO_MODE_GPIO,
+	.gpio70 = GPIO_MODE_NATIVE,
+	.gpio71 = GPIO_MODE_NATIVE,
+	.gpio72 = GPIO_MODE_GPIO,
+	.gpio73 = GPIO_MODE_NATIVE,
+	.gpio74 = GPIO_MODE_NATIVE,
+	.gpio75 = GPIO_MODE_NATIVE,
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_direction = {
+	.gpio68 = GPIO_DIR_INPUT,
+	.gpio69 = GPIO_DIR_INPUT,
+	.gpio72 = GPIO_DIR_OUTPUT,
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_level = {
+	.gpio72 = GPIO_LEVEL_LOW,
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_reset = {
+};
+
+const struct pch_gpio_map mainboard_gpio_map = {
+	.set1 = {
+		.mode		= &pch_gpio_set1_mode,
+		.direction	= &pch_gpio_set1_direction,
+		.level		= &pch_gpio_set1_level,
+		.blink		= &pch_gpio_set1_blink,
+		.invert		= &pch_gpio_set1_invert,
+		.reset		= &pch_gpio_set1_reset,
+	},
+	.set2 = {
+		.mode		= &pch_gpio_set2_mode,
+		.direction	= &pch_gpio_set2_direction,
+		.level		= &pch_gpio_set2_level,
+		.reset		= &pch_gpio_set2_reset,
+	},
+	.set3 = {
+		.mode		= &pch_gpio_set3_mode,
+		.direction	= &pch_gpio_set3_direction,
+		.level		= &pch_gpio_set3_level,
+		.reset		= &pch_gpio_set3_reset,
+	},
+};
diff --git a/src/mainboard/asrock/z77_extreme4/hda_verb.c b/src/mainboard/asrock/z77_extreme4/hda_verb.c
new file mode 100644
index 0000000000..276145f912
--- /dev/null
+++ b/src/mainboard/asrock/z77_extreme4/hda_verb.c
@@ -0,0 +1,52 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <device/azalia_device.h>
+
+static const u32 realtek_alc898_verbs[] = {
+	AZALIA_SUBVENDOR(0, 0x18491898),
+	AZALIA_PIN_CFG(0, 0x11, AZALIA_PIN_CFG_NC(0)),
+	AZALIA_PIN_CFG(0, 0x12, AZALIA_PIN_CFG_NC(0)),
+	AZALIA_PIN_CFG(0, 0x14, 0x01014010),
+	AZALIA_PIN_CFG(0, 0x15, 0x01011012),
+	AZALIA_PIN_CFG(0, 0x16, 0x01016011),
+	AZALIA_PIN_CFG(0, 0x17, AZALIA_PIN_CFG_NC(0)),
+	AZALIA_PIN_CFG(0, 0x18, 0x01a19840),
+	AZALIA_PIN_CFG(0, 0x19, 0x02a19950),
+	AZALIA_PIN_CFG(0, 0x1a, 0x0181304f),
+	AZALIA_PIN_CFG(0, 0x1b, 0x02214120),
+	AZALIA_PIN_CFG(0, 0x1c, AZALIA_PIN_CFG_NC(0)),
+	AZALIA_PIN_CFG(0, 0x1d, 0x4015e601),
+	AZALIA_PIN_CFG(0, 0x1e, 0x01451130),
+	AZALIA_PIN_CFG(0, 0x1f, AZALIA_PIN_CFG_NC(0)),
+};
+
+static const u32 intel_display_audio_verbs[] = {
+	AZALIA_SUBVENDOR(3, 0x80860101),
+	AZALIA_PIN_CFG(3, 0x05, 0x18560010),
+	AZALIA_PIN_CFG(3, 0x06, 0x58560020),
+	AZALIA_PIN_CFG(3, 0x07, 0x18560030),
+};
+
+const u32 pc_beep_verbs[0] = {};
+
+struct azalia_codec mainboard_azalia_codecs[] = {
+	{
+		.name           = "Realtek ALC898",
+		.vendor_id      = 0x10ec0899,
+		.subsystem_id   = 0x18491898,
+		.address        = 0,
+		.verbs          = realtek_alc898_verbs,
+		.verb_count     = ARRAY_SIZE(realtek_alc898_verbs),
+	},
+	{
+		.name           = "Intel Display Audio (HDMI)",
+		.vendor_id      = 0x80862806,
+		.subsystem_id   = 0x80860101,
+		.address        = 3,
+		.verbs          = intel_display_audio_verbs,
+		.verb_count     = ARRAY_SIZE(intel_display_audio_verbs),
+	},
+	{ /* terminator */ }
+};
+
+AZALIA_ARRAY_SIZES;
diff --git a/src/mainboard/asrock/z77_extreme4/mainboard.c b/src/mainboard/asrock/z77_extreme4/mainboard.c
new file mode 100644
index 0000000000..c11607a3e1
--- /dev/null
+++ b/src/mainboard/asrock/z77_extreme4/mainboard.c
@@ -0,0 +1,15 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <device/device.h>
+#include <drivers/intel/gma/int15.h>
+
+static void mainboard_enable(struct device *dev)
+{
+	install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_NONE,
+			GMA_INT15_PANEL_FIT_DEFAULT,
+			GMA_INT15_BOOT_DISPLAY_CRT, 0);
+}
+
+struct chip_operations mainboard_ops = {
+	.enable_dev = mainboard_enable,
+};

From 2c6cf2c2a8c142331166431df34b7e1f2ecc79b0 Mon Sep 17 00:00:00 2001
From: Maximilian Brune <maximilian.brune@9elements.com>
Date: Wed, 22 Oct 2025 02:11:52 +0200
Subject: [PATCH 2334/3886] include/cper.h: Update CPER structures with
 __packed attribute

Change-Id: I79945d40d68d2de93e8745425a046e700be97182
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89678
Reviewed-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/include/cper.h | 12 ++++++------
 1 file changed, 6 insertions(+), 6 deletions(-)

diff --git a/src/include/cper.h b/src/include/cper.h
index 4af8a7b3bf..50e858a219 100644
--- a/src/include/cper.h
+++ b/src/include/cper.h
@@ -181,7 +181,7 @@ typedef struct cper_ia32x64_proc_error_info {
 	u64 requestor_id;
 	u64 responder_id;
 	u64 instruction_ip;
-} cper_ia32x64_proc_error_info_t;
+} __packed cper_ia32x64_proc_error_info_t;
 
 /* IA32/X64 Processor Error Information Structs, Err Struct Types (Table N.8) */
 #define X86_PROCESSOR_CACHE_CHK_ERROR_GUID		\
@@ -290,7 +290,7 @@ typedef struct cper_ia32x64_context {
 	u32 msr_addr;
 	u64 mmap_addr;
 	/* N bytes of register array */
-} cper_ia32x64_context_t;
+} __packed cper_ia32x64_context_t;
 
 /* IA32/X64 Processor Context Information, Types field (Table N.13) */
 #define CPER_IA32X64_CTX_UNCL			0
@@ -329,7 +329,7 @@ typedef struct cper_ia32x64_ctx_ia32state {
 	u64 idtr;
 	u16 ldtr;
 	u16 tr;
-} cper_ia32x64_ctx_ia32state_t;
+} __packed cper_ia32x64_ctx_ia32state_t;
 
 /* IA32/X64 Processor Context X64 Register state (Table N.15) */
 typedef struct cper_ia32x64_ctx_x64state {
@@ -368,7 +368,7 @@ typedef struct cper_ia32x64_ctx_x64state {
 	u8 idtr[16];
 	u16 ldtr;
 	u16 tr;
-} cper_ia32x64_ctx_x64state_t;
+} __packed cper_ia32x64_ctx_x64state_t;
 
 /* UEFI Spec 2.10, Appendix N.2.5 Memory Error Types (Table N.31) */
 #define CPER_UNDEFINED			0
@@ -379,7 +379,7 @@ typedef struct cper_ia32x64_ctx_x64state {
 #define CPER_ERR_MEM_SCRUB_UCE_ERR	14
 
 /* UEFI Spec 2.10, Appendix N.2.5 Memory Error Section (Table N.31) */
-struct cper_memory_section {
+struct __packed cper_memory_section {
 	u64	valid_bits;
 	u64	err_sts;
 	u64	phys_addr;
@@ -413,7 +413,7 @@ typedef struct cper_fw_err_rec_section {
 	u8 reserved[6];
 	u64 record_id;
 	guid_t record_guid;
-} cper_fw_err_rec_section_t;
+} __packed cper_fw_err_rec_section_t;
 
 static inline cper_timestamp_t cper_timestamp(int precise)
 {

From 385ae6669b478149ee4f1e37dfd02f027d32ab86 Mon Sep 17 00:00:00 2001
From: Dodoid <git-noreply@dodoid.com>
Date: Wed, 22 Oct 2025 00:42:46 -0400
Subject: [PATCH 2335/3886] mb/gigabyte/ga-h77m-d3h/devicetree.cb: Re-enable
 IGD and PCIe VGA

Commit 7d8e105420c3 ("mb/gigabyte/ga-h77m-d3h: Add Sandy/Ivy Bridge
board GA-H77M-D3H"), adding this board, initially enabled igd and
peg10 in the device tree, but later, during review, Patchset 10
removed those lines of the device tree entirely, disabling onboard
and PCIe graphics in the port as ultimately submitted.

This commit re-adds these lines to the device tree, enabling both -
thanks to nic3-14159 for spotting the issue. I have confirmed both
now work on my GA-H77M-D3H.

TEST=Confirm IGD outputs as configured in SeaBIOS and Linux (with
CONFIG_ONBOARD_VGA_IS_PRIMARY), same for PCIe GPU (running option
ROMs).

$ lspci
00:00.0 Host bridge: Intel Corporation Xeon E3-1200 v2/3rd Gen Core
processor DRAM Controller (rev 09)
00:02.0 VGA compatible controller: Intel Corporation Xeon E3-1200
v2/3rd Gen Core processor Graphics Controller (rev 09)
...

With a monitor connected to the onboard DVI:

$ cat /sys/class/graphics/fb0/virtual_size
1920,1080

Change-Id: I248827b92d9f14cedbbd666d533764b5f152cf29
Signed-off-by: Dodoid <git-noreply@dodoid.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89681
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nicholas Chin <nic.c3.14@gmail.com>
---
 src/mainboard/gigabyte/ga-h77m-d3h/devicetree.cb | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/src/mainboard/gigabyte/ga-h77m-d3h/devicetree.cb b/src/mainboard/gigabyte/ga-h77m-d3h/devicetree.cb
index ce643241b6..3febdebd55 100644
--- a/src/mainboard/gigabyte/ga-h77m-d3h/devicetree.cb
+++ b/src/mainboard/gigabyte/ga-h77m-d3h/devicetree.cb
@@ -3,6 +3,11 @@
 chip northbridge/intel/sandybridge
 	register "spd_addresses" = "{0x50, 0x51, 0x52, 0x53}"
 	device domain 0 on
+		device ref peg10 on end
+		device ref igd on
+			subsystemid 0x1458 0xd000
+		end
+
 		chip southbridge/intel/bd82x6x	# Intel Series 7 Panther Point PCH
 			register "gen1_dec" = "0x003c0a01"
 

From c63e901b992b1bb62e31ef39bfc3e2c6b963601f Mon Sep 17 00:00:00 2001
From: Vince Liu <vince-wl.liu@mediatek.corp-partner.google.com>
Date: Mon, 27 Oct 2025 09:17:40 +0800
Subject: [PATCH 2336/3886] mipi: Add panel flags to support C-PHY interface

Add a new member 'flags' to the panel structure in panel.h, and define
`PANEL_FLAG_CPHY` to indicate C-PHY interface support. This change
enables panel drivers to check and handle C-PHY panels.

BUG=b:433422905,b:428854543
BRANCH=skywalker
TEST=build passed

Signed-off-by: Bincai Liu bincai.liu@mediatek.corp-partner.google.com
Signed-off-by: Vince Liu vince-wl.liu@mediatek.corp-partner.google.com
Change-Id: I4c35ad2cb6fc2289598ae47b3abf1c6c706dad42
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89760
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/include/mipi/panel.h | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/src/include/mipi/panel.h b/src/include/mipi/panel.h
index ca06897c98..cc5a065d02 100644
--- a/src/include/mipi/panel.h
+++ b/src/include/mipi/panel.h
@@ -15,6 +15,11 @@ enum panel_init_cmd {
 	PANEL_CMD_DCS = 3,
 };
 
+/* Definitions for flags in panel_serializable_data */
+enum panel_flag {
+	PANEL_FLAG_CPHY = BIT(0),
+};
+
 struct panel_init_command {
 	u8 cmd;
 	u8 len;
@@ -27,6 +32,7 @@ struct panel_init_command {
  * cannot be really serialized.
  */
 struct panel_serializable_data {
+	u32 flags; /* flags of panel_flag */
 	struct edid edid;  /* edid info of this panel */
 	u8 init[]; /* A packed array of panel_init_command */
 };

From 44635f328c1f3d7ddbcbb06dbf6bc15b21a4e98b Mon Sep 17 00:00:00 2001
From: Vince Liu <vince-wl.liu@mediatek.corp-partner.google.com>
Date: Mon, 27 Oct 2025 09:16:49 +0800
Subject: [PATCH 2337/3886] soc/mediatek/common: Add C-PHY support for MIPI DSI

Introduce C-PHY support by adding PANEL_FLAG_CPHY flag, updating data
rate calculations, timing configurations, and register settings for
C-PHY operation.

To improve code reusability, the D-PHY and C-PHY specific
implementations are moved to `mtk_mipi_dphy.c` and `mtk_mipi_cphy.c`,
respectively.

BUG=b:433422905,b:428854543
BRANCH=skywalker
TEST=check log on padme
mtk_display_init: 'TM TL121BVMS07' 1600x2560@60Hz

Change-Id: I9e81551484e605e1d74b9983fe00b5d0eba69358
Signed-off-by: Bincai Liu <bincai.liu@mediatek.corp-partner.google.com>
Signed-off-by: Vince Liu <vince-wl.liu@mediatek.corp-partner.google.com>
(cherry picked from commit 22a499836eeb6904e114023da6222b29da10f62f)
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89567
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
---
 src/soc/mediatek/common/Kconfig               |   6 +
 src/soc/mediatek/common/display.c             |  10 +-
 src/soc/mediatek/common/dsi_common.c          | 161 +++++++++++-------
 src/soc/mediatek/common/dsi_v1.c              |  62 +++++++
 .../mediatek/common/include/soc/dsi_common.h  |  26 ++-
 .../common/include/soc/dsi_register_v2.h      |  15 +-
 src/soc/mediatek/common/mtk_mipi_cphy.c       | 112 ++++++++++++
 src/soc/mediatek/common/mtk_mipi_dphy.c       |  56 +-----
 src/soc/mediatek/mt8173/dsi.c                 |   2 +-
 9 files changed, 323 insertions(+), 127 deletions(-)
 create mode 100644 src/soc/mediatek/common/mtk_mipi_cphy.c

diff --git a/src/soc/mediatek/common/Kconfig b/src/soc/mediatek/common/Kconfig
index 63a11d0ca8..1f0f54ea7a 100644
--- a/src/soc/mediatek/common/Kconfig
+++ b/src/soc/mediatek/common/Kconfig
@@ -54,6 +54,12 @@ config MEDIATEK_DRAM_SCRAMBLE
 	  This option enables DRAM data scramble, which can prevent DRAM data from
 	  being hacked.
 
+config MEDIATEK_DSI_CPHY
+	bool
+	default n
+	help
+	  The configuration to support DSI C-PHY.
+
 config MEMORY_TEST
 	bool
 	default y
diff --git a/src/soc/mediatek/common/display.c b/src/soc/mediatek/common/display.c
index 109da29d59..8e3979df26 100644
--- a/src/soc/mediatek/common/display.c
+++ b/src/soc/mediatek/common/display.c
@@ -103,6 +103,7 @@ int mtk_display_init(void)
 	const char *name;
 	struct panel_description *panel = get_active_panel();
 	uintptr_t fb_addr;
+	u32 lanes;
 
 	if (!panel || panel->disp_path == DISP_PATH_NONE) {
 		printk(BIOS_ERR, "%s: Failed to get the active panel\n", __func__);
@@ -146,7 +147,14 @@ int mtk_display_init(void)
 				      MIPI_DSI_MODE_LPM |
 				      MIPI_DSI_MODE_EOT_PACKET);
 
-		if (mtk_dsi_init(mipi_dsi_flags, MIPI_DSI_FMT_RGB888, 4, &edid,
+		if (mipi_data->flags & PANEL_FLAG_CPHY) {
+			mipi_dsi_flags |= MIPI_DSI_MODE_CPHY;
+			lanes = 3;
+		} else {
+			lanes = 4;
+		}
+
+		if (mtk_dsi_init(mipi_dsi_flags, MIPI_DSI_FMT_RGB888, lanes, &edid,
 				 mipi_data ? mipi_data->init : NULL) < 0) {
 			printk(BIOS_ERR, "%s: Failed in DSI init\n", __func__);
 			return -1;
diff --git a/src/soc/mediatek/common/dsi_common.c b/src/soc/mediatek/common/dsi_common.c
index 696f849a6a..027c748d0b 100644
--- a/src/soc/mediatek/common/dsi_common.c
+++ b/src/soc/mediatek/common/dsi_common.c
@@ -12,6 +12,9 @@
 #define MIN_HFP_BYTE	2
 #define MIN_HBP_BYTE	2
 
+#define CPHY_SYMBOL_RATE		7
+#define CPHY_SYMBOL_RATE_DIVISOR	16
+
 static unsigned int mtk_dsi_get_bits_per_pixel(u32 format)
 {
 	switch (format) {
@@ -29,7 +32,7 @@ static unsigned int mtk_dsi_get_bits_per_pixel(u32 format)
 }
 
 static u32 mtk_dsi_get_data_rate(u32 bits_per_pixel, u32 lanes,
-				 const struct edid *edid)
+				 const struct edid *edid, bool is_cphy)
 {
 	/* data_rate = pixel_clock * bits_per_pixel * mipi_ratio / lanes
 	 * Note pixel_clock comes in kHz and returned data_rate is in bps.
@@ -37,11 +40,16 @@ static u32 mtk_dsi_get_data_rate(u32 bits_per_pixel, u32 lanes,
 	 * for older platforms which do not have complete implementation in HFP.
 	 * Newer platforms should just set that to 1.0 (100 / 100).
 	 */
-	u32 data_rate = DIV_ROUND_UP((u64)edid->mode.pixel_clock *
-				     bits_per_pixel * 1000 *
-				     MTK_DSI_MIPI_RATIO_NUMERATOR,
-				     (u64)lanes *
-				     MTK_DSI_MIPI_RATIO_DENOMINATOR);
+	u32 data_rate;
+	u64 dividend = (u64)edid->mode.pixel_clock * bits_per_pixel * 1000 *
+			MTK_DSI_MIPI_RATIO_NUMERATOR;
+	u64 divisor = (u64)lanes * MTK_DSI_MIPI_RATIO_DENOMINATOR;
+
+	if (is_cphy) {
+		dividend *= CPHY_SYMBOL_RATE;
+		divisor *= CPHY_SYMBOL_RATE_DIVISOR;
+	}
+	data_rate = DIV_ROUND_UP(dividend, divisor);
 	printk(BIOS_INFO, "DSI data_rate: %u bps\n", data_rate);
 
 	if (data_rate < MTK_DSI_DATA_RATE_MIN_MHZ * MHz) {
@@ -63,13 +71,11 @@ __weak void mtk_dsi_override_phy_timing(struct mtk_phy_timing *timing)
 	/* Do nothing. */
 }
 
-static void mtk_dsi_phy_timing(u32 data_rate, struct mtk_phy_timing *timing)
+static void mtk_dsi_dphy_timing(u32 data_rate, struct mtk_phy_timing *timing)
 {
 	u32 timcon0, timcon1, timcon2, timcon3;
 	u32 data_rate_mhz = DIV_ROUND_UP(data_rate, MHz);
 
-	memset(timing, 0, sizeof(*timing));
-
 	timing->lpx = (60 * data_rate_mhz / (8 * 1000)) + 1;
 	timing->da_hs_prepare = (80 * data_rate_mhz + 4 * 1000) / 8000;
 	timing->da_hs_zero = (170 * data_rate_mhz + 10 * 1000) / 8000 + 1 -
@@ -163,46 +169,19 @@ static void mtk_dsi_rxtx_control(u32 mode_flags, u32 lanes)
 	write32(&dsi0->dsi_txrx_ctrl, tmp_reg);
 }
 
-static void mtk_dsi_config_vdo_timing(u32 mode_flags, u32 format, u32 lanes,
-				      const struct edid *edid,
-				      const struct mtk_phy_timing *phy_timing)
+static void mtk_dsi_dphy_vdo_timing(const u32 mode_flags,
+				    const u32 lanes,
+				    const struct edid *edid,
+				    const struct mtk_phy_timing *phy_timing,
+				    const u32 bytes_per_pixel,
+				    const u32 hbp,
+				    const u32 hfp,
+				    s32 *hbp_byte,
+				    s32 *hfp_byte,
+				    u32 *hsync_active_byte)
 {
-	u32 hsync_active_byte;
-	u32 hbp;
-	u32 hfp;
-	s32 hbp_byte;
-	s32 hfp_byte;
-	u32 vbp_byte;
-	u32 vfp_byte;
-	u32 bytes_per_pixel;
-	u32 packet_fmt;
-	u32 hactive;
-	u32 data_phy_cycles;
-
-	bytes_per_pixel = DIV_ROUND_UP(mtk_dsi_get_bits_per_pixel(format), 8);
-	vbp_byte = edid->mode.vbl - edid->mode.vso - edid->mode.vspw -
-		   edid->mode.vborder;
-	vfp_byte = edid->mode.vso - edid->mode.vborder;
-
-	write32(&dsi0->dsi_vsa_nl, edid->mode.vspw);
-	write32(&dsi0->dsi_vbp_nl, vbp_byte);
-	write32(&dsi0->dsi_vfp_nl, vfp_byte);
-	write32(&dsi0->dsi_vact_nl, edid->mode.va);
-
-	hsync_active_byte = edid->mode.hspw * bytes_per_pixel - 10;
-
-	hbp = edid->mode.hbl - edid->mode.hso - edid->mode.hspw -
-	      edid->mode.hborder;
-	hfp = edid->mode.hso - edid->mode.hborder;
-
-	if (mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE)
-		hbp_byte = hbp * bytes_per_pixel - 10;
-	else
-		hbp_byte = (hbp + edid->mode.hspw) * bytes_per_pixel - 10;
-	hfp_byte = hfp * bytes_per_pixel;
-
-	data_phy_cycles = phy_timing->lpx + phy_timing->da_hs_prepare +
-			  phy_timing->da_hs_zero + phy_timing->da_hs_exit + 3;
+	u32 data_phy_cycles = phy_timing->lpx + phy_timing->da_hs_prepare +
+				phy_timing->da_hs_zero + phy_timing->da_hs_exit + 3;
 
 	u32 delta = 10;
 
@@ -217,20 +196,65 @@ static void mtk_dsi_config_vdo_timing(u32 mode_flags, u32 format, u32 lanes,
 		d_phy = data_phy_cycles * lanes + delta;
 
 	if ((hfp + hbp) * bytes_per_pixel > d_phy) {
-		hfp_byte -= d_phy * hfp / (hfp + hbp);
-		hbp_byte -= d_phy * hbp / (hfp + hbp);
+		*hfp_byte -= d_phy * hfp / (hfp + hbp);
+		*hbp_byte -= d_phy * hbp / (hfp + hbp);
 	} else {
 		printk(BIOS_ERR, "HFP %u plus HBP %u is not greater than d_phy %u, "
-		       "the panel may not work properly.\n", hfp * bytes_per_pixel,
-		       hbp * bytes_per_pixel, d_phy);
+			"the panel may not work properly.\n", hfp * bytes_per_pixel,
+			hbp * bytes_per_pixel, d_phy);
 	}
 
+	*hsync_active_byte = edid->mode.hspw * bytes_per_pixel - 10;
 	if (mode_flags & MIPI_DSI_MODE_LINE_END) {
-		hsync_active_byte = DIV_ROUND_UP(hsync_active_byte, lanes) * lanes - 2;
-		hbp_byte = DIV_ROUND_UP(hbp_byte, lanes) * lanes - 2;
-		hfp_byte = DIV_ROUND_UP(hfp_byte, lanes) * lanes - 2;
-		hbp_byte -= (edid->mode.ha * bytes_per_pixel + 2) % lanes;
+		*hsync_active_byte = DIV_ROUND_UP(*hsync_active_byte, lanes) * lanes - 2;
+		*hbp_byte = DIV_ROUND_UP(*hbp_byte, lanes) * lanes - 2;
+		*hfp_byte = DIV_ROUND_UP(*hfp_byte, lanes) * lanes - 2;
+		*hbp_byte -= (edid->mode.ha * bytes_per_pixel + 2) % lanes;
 	}
+}
+
+static void mtk_dsi_config_vdo_timing(u32 mode_flags, u32 format, u32 lanes,
+				      const struct edid *edid,
+				      const struct mtk_phy_timing *phy_timing)
+{
+	u32 hsync_active_byte;
+	u32 hbp;
+	u32 hfp;
+	s32 hbp_byte;
+	s32 hfp_byte;
+	u32 vbp_byte;
+	u32 vfp_byte;
+	u32 bytes_per_pixel;
+	u32 packet_fmt;
+	u32 hactive;
+	bool is_cphy = !!(mode_flags & MIPI_DSI_MODE_CPHY);
+
+	bytes_per_pixel = DIV_ROUND_UP(mtk_dsi_get_bits_per_pixel(format), 8);
+	vbp_byte = edid->mode.vbl - edid->mode.vso - edid->mode.vspw -
+		   edid->mode.vborder;
+	vfp_byte = edid->mode.vso - edid->mode.vborder;
+
+	write32(&dsi0->dsi_vsa_nl, edid->mode.vspw);
+	write32(&dsi0->dsi_vbp_nl, vbp_byte);
+	write32(&dsi0->dsi_vfp_nl, vfp_byte);
+	write32(&dsi0->dsi_vact_nl, edid->mode.va);
+
+	hbp = edid->mode.hbl - edid->mode.hso - edid->mode.hspw -
+	      edid->mode.hborder;
+	hfp = edid->mode.hso - edid->mode.hborder;
+
+	if (mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE)
+		hbp_byte = hbp * bytes_per_pixel - 10;
+	else
+		hbp_byte = (hbp + edid->mode.hspw) * bytes_per_pixel - 10;
+	hfp_byte = hfp * bytes_per_pixel;
+
+	if (CONFIG(MEDIATEK_DSI_CPHY) && is_cphy)
+		mtk_dsi_cphy_vdo_timing(lanes, edid, phy_timing, bytes_per_pixel, hbp, hfp,
+					&hbp_byte, &hfp_byte, &hsync_active_byte);
+	else
+		mtk_dsi_dphy_vdo_timing(mode_flags, lanes, edid, phy_timing, bytes_per_pixel,
+					hbp, hfp, &hbp_byte, &hfp_byte, &hsync_active_byte);
 
 	if (hfp_byte + hbp_byte < MIN_HFP_BYTE + MIN_HBP_BYTE) {
 		printk(BIOS_ERR, "Calculated hfp_byte %d and hbp_byte %d are too small, "
@@ -281,6 +305,8 @@ static void mtk_dsi_config_vdo_timing(u32 mode_flags, u32 format, u32 lanes,
 		write32(&dsi0->dsi_size_con,
 			edid->mode.va << DSI_SIZE_CON_HEIGHT_SHIFT |
 			hactive << DSI_SIZE_CON_WIDTH_SHIFT);
+	if (CONFIG(MEDIATEK_DSI_CPHY) && is_cphy)
+		mtk_dsi_cphy_enable_cmdq_6byte();
 }
 
 static void mtk_dsi_start(void)
@@ -339,6 +365,7 @@ static enum cb_err mtk_dsi_cmdq(enum mipi_dsi_transaction type, const u8 *data,
 		}
 		write32(&dsi0->dsi_cmdq_size, 1 + DIV_ROUND_UP(len, 4));
 	}
+	setbits32(&dsi0->dsi_cmdq_size, CMDQ_SIZE_SEL);
 
 	mtk_dsi_start();
 
@@ -351,7 +378,7 @@ static enum cb_err mtk_dsi_cmdq(enum mipi_dsi_transaction type, const u8 *data,
 	return CB_SUCCESS;
 }
 
-static void mtk_dsi_reset_dphy(void)
+static void mtk_dsi_reset_phy(void)
 {
 	setbits32(&dsi0->dsi_con_ctrl, DPHY_RESET);
 	clrbits32(&dsi0->dsi_con_ctrl, DPHY_RESET);
@@ -362,18 +389,28 @@ int mtk_dsi_init(u32 mode_flags, u32 format, u32 lanes, const struct edid *edid,
 {
 	u32 data_rate;
 	u32 bits_per_pixel = mtk_dsi_get_bits_per_pixel(format);
+	bool is_cphy = !!(mode_flags & MIPI_DSI_MODE_CPHY);
 
-	data_rate = mtk_dsi_get_data_rate(bits_per_pixel, lanes, edid);
+	if (!CONFIG(MEDIATEK_DSI_CPHY) && is_cphy) {
+		printk(BIOS_ERR, "%s: Board is built without C-PHY interface support. "
+		       "Please check Kconfig MEDIATEK_DSI_CPHY.\n", __func__);
+		return -1;
+	}
+
+	data_rate = mtk_dsi_get_data_rate(bits_per_pixel, lanes, edid, is_cphy);
 	if (!data_rate)
 		return -1;
 
-	mtk_dsi_configure_mipi_tx(data_rate, lanes);
+	mtk_dsi_configure_mipi_tx(data_rate, lanes, is_cphy);
 	mtk_dsi_reset();
-	struct mtk_phy_timing phy_timing;
-	mtk_dsi_phy_timing(data_rate, &phy_timing);
+	struct mtk_phy_timing phy_timing = {};
+	if (CONFIG(MEDIATEK_DSI_CPHY) && is_cphy)
+		mtk_dsi_cphy_timing(data_rate, &phy_timing);
+	else
+		mtk_dsi_dphy_timing(data_rate, &phy_timing);
 	mtk_dsi_rxtx_control(mode_flags, lanes);
 	mdelay(1);
-	mtk_dsi_reset_dphy();
+	mtk_dsi_reset_phy();
 	mtk_dsi_clk_hs_mode_disable();
 	mtk_dsi_config_vdo_timing(mode_flags, format, lanes, edid, &phy_timing);
 	mtk_dsi_clk_hs_mode_enable();
diff --git a/src/soc/mediatek/common/dsi_v1.c b/src/soc/mediatek/common/dsi_v1.c
index 67654b1630..6177bc35ad 100644
--- a/src/soc/mediatek/common/dsi_v1.c
+++ b/src/soc/mediatek/common/dsi_v1.c
@@ -1,7 +1,69 @@
 /* SPDX-License-Identifier: GPL-2.0-only OR MIT */
 
+#include <assert.h>
+#include <delay.h>
 #include <device/mmio.h>
 #include <soc/dsi.h>
+#include <soc/pll.h>
+
+void mtk_dsi_configure_mipi_tx(u32 data_rate, u32 lanes, bool is_cphy)
+{
+	unsigned int txdiv0;
+	u64 pcw;
+
+	if (data_rate >= 2000 * MHz) {
+		txdiv0 = 0;
+	} else if (data_rate >= 1000 * MHz) {
+		txdiv0 = 1;
+	} else if (data_rate >= 500 * MHz) {
+		txdiv0 = 2;
+	} else if (data_rate > 250 * MHz) {
+		/* (data_rate == 250MHz) is a special case that should go to the
+		   else-block below (txdiv0 = 4) */
+		txdiv0 = 3;
+	} else {
+		/* MIN = 125 */
+		assert(data_rate >= MTK_DSI_DATA_RATE_MIN_MHZ * MHz);
+		txdiv0 = 4;
+	}
+
+	if (CONFIG(MEDIATEK_DSI_CPHY) && is_cphy)
+		mtk_dsi_cphy_lane_sel_setting();
+
+	clrbits32(&mipi_tx->pll_con4, BIT(11) | BIT(10));
+	setbits32(&mipi_tx->pll_pwr, AD_DSI_PLL_SDM_PWR_ON);
+	udelay(30);
+	clrbits32(&mipi_tx->pll_pwr, AD_DSI_PLL_SDM_ISO_EN);
+
+	pcw = (u64)data_rate * (1 << txdiv0);
+	pcw <<= 24;
+	pcw /= CLK26M_HZ;
+
+	write32(&mipi_tx->pll_con0, pcw);
+	clrsetbits32(&mipi_tx->pll_con1, RG_DSI_PLL_POSDIV, txdiv0 << 8);
+	udelay(30);
+	setbits32(&mipi_tx->pll_con1, RG_DSI_PLL_EN);
+
+	/* BG_LPF_EN / BG_CORE_EN */
+	write32(&mipi_tx->lane_con, 0x3FFF0180);
+	udelay(40);
+	write32(&mipi_tx->lane_con, 0x3FFF00C0);
+
+	if (CONFIG(MEDIATEK_DSI_CPHY) && is_cphy)
+		mtk_dsi_cphy_enable();
+
+	/* Switch OFF each Lane */
+	clrbits32(&mipi_tx->d0_sw_ctl_en, DSI_SW_CTL_EN);
+	clrbits32(&mipi_tx->d1_sw_ctl_en, DSI_SW_CTL_EN);
+	clrbits32(&mipi_tx->d2_sw_ctl_en, DSI_SW_CTL_EN);
+	clrbits32(&mipi_tx->d3_sw_ctl_en, DSI_SW_CTL_EN);
+	clrbits32(&mipi_tx->ck_sw_ctl_en, DSI_SW_CTL_EN);
+
+	if (CONFIG(MEDIATEK_DSI_CPHY) && is_cphy)
+		mtk_dsi_cphy_disable_ck_mode();
+	else
+		mtk_dsi_dphy_disable_ck_mode();
+}
 
 void mtk_dsi_reset(void)
 {
diff --git a/src/soc/mediatek/common/include/soc/dsi_common.h b/src/soc/mediatek/common/include/soc/dsi_common.h
index f5fc70c1c6..d741db0f1d 100644
--- a/src/soc/mediatek/common/include/soc/dsi_common.h
+++ b/src/soc/mediatek/common/include/soc/dsi_common.h
@@ -43,6 +43,8 @@ enum {
 	MIPI_DSI_MODE_LPM = BIT(11),
 	/* dsi per line's data end same time on all lanes */
 	MIPI_DSI_MODE_LINE_END = BIT(12),
+	/* mipi is in CPHY mode */
+	MIPI_DSI_MODE_CPHY = BIT(13),
 };
 
 static struct dsi_regs *const dsi0 = (void *)DSI0_BASE;
@@ -57,6 +59,11 @@ enum {
 	DSI_BUSY             = BIT(31),
 };
 
+/* DSI_CMD_TYPE1_HS */
+enum {
+	CMD_CPHY_6BYTE_EN = BIT(18),
+};
+
 /* DSI_CON_CTRL */
 enum {
 	DSI_RESET = BIT(0),
@@ -103,6 +110,7 @@ enum {
 /* DSI_CMDQ_SIZE */
 enum {
 	CMDQ_SIZE = 0x3f,
+	CMDQ_SIZE_SEL = BIT(15),
 };
 
 /* DSI_PHY_LCCON */
@@ -192,13 +200,25 @@ struct mtk_phy_timing {
 
 /* Functions that each SOC should provide. */
 void mtk_dsi_reset(void);
-void mtk_dsi_configure_mipi_tx(u32 data_rate, u32 lanes);
 
 /* Functions as weak no-ops that can be overridden. */
 void mtk_dsi_override_phy_timing(struct mtk_phy_timing *timing);
 
-/* Public API provided in common/dsi_common.c */
-int mtk_dsi_bpp_from_format(u32 format);
+/*
+ * Public API provided in common/dsi_common.c, common/dsi_v1.c, and
+ * common/mtk_mipi_{c/d}phy.c
+ */
+void mtk_dsi_cphy_enable(void);
+void mtk_dsi_cphy_enable_cmdq_6byte(void);
+void mtk_dsi_cphy_lane_sel_setting(void);
+void mtk_dsi_cphy_timing(u32 data_rate, struct mtk_phy_timing *timing);
+void mtk_dsi_cphy_vdo_timing(const u32 lanes, const struct edid *edid,
+			     const struct mtk_phy_timing *phy_timing,
+			     const u32 bytes_per_pixel, const u32 hbp, const u32 hfp,
+			     s32 *hbp_byte, s32 *hfp_byte, u32 *hsync_active_byte);
+void mtk_dsi_cphy_disable_ck_mode(void);
+void mtk_dsi_dphy_disable_ck_mode(void);
+void mtk_dsi_configure_mipi_tx(u32 data_rate, u32 lanes, bool is_cphy);
 int mtk_dsi_init(u32 mode_flags, u32 format, u32 lanes, const struct edid *edid,
 		 const u8 *init_commands);
 
diff --git a/src/soc/mediatek/common/include/soc/dsi_register_v2.h b/src/soc/mediatek/common/include/soc/dsi_register_v2.h
index 17809c79ef..5c26ba51af 100644
--- a/src/soc/mediatek/common/include/soc/dsi_register_v2.h
+++ b/src/soc/mediatek/common/include/soc/dsi_register_v2.h
@@ -31,24 +31,29 @@ struct dsi_regs {
 	u32 dsi_bllp_wc;
 	u32 dsi_cmdq_size;
 	u32 dsi_hstx_cklp_wc;
-	u8 reserved2[156];
+	u8 reserved2[4];
+	u32 dsi_cmd_type1_hs;
+	u8 reserved3[148];
 	u32 dsi_phy_lccon;
 	u32 dsi_phy_ld0con;
-	u8 reserved3[4];
+	u8 reserved4[4];
 	u32 dsi_phy_timecon0;
 	u32 dsi_phy_timecon1;
 	u32 dsi_phy_timecon2;
 	u32 dsi_phy_timecon3;
-	u8 reserved4[16];
+	u32 dsi_cphy_con0;
+	u8 reserved5[12];
 	u32 dsi_vm_cmd_con;
-	u8 reserved5[92];
+	u8 reserved6[92];
 	u32 dsi_force_commit;  /* Available since MT8183 */
-	u8 reserved6[2924];
+	u8 reserved7[2924];
 	u32 dsi_cmdq[128];
 };
 
+check_member(dsi_regs, dsi_cmd_type1_hs, 0x6c);
 check_member(dsi_regs, dsi_phy_lccon, 0x104);
 check_member(dsi_regs, dsi_phy_timecon3, 0x11c);
+check_member(dsi_regs, dsi_cphy_con0, 0x120);
 check_member(dsi_regs, dsi_vm_cmd_con, 0x130);
 check_member(dsi_regs, dsi_force_commit, 0x190);
 check_member(dsi_regs, dsi_cmdq, 0xd00);
diff --git a/src/soc/mediatek/common/mtk_mipi_cphy.c b/src/soc/mediatek/common/mtk_mipi_cphy.c
new file mode 100644
index 0000000000..9ff62240fc
--- /dev/null
+++ b/src/soc/mediatek/common/mtk_mipi_cphy.c
@@ -0,0 +1,112 @@
+/* SPDX-License-Identifier: GPL-2.0-only OR MIT */
+
+#include <assert.h>
+#include <device/mmio.h>
+#include <delay.h>
+#include <soc/dsi.h>
+#include <soc/pll.h>
+#include <types.h>
+
+#define DE_EMPHASIS_EN		BIT(9)
+#define DSI_CPHY_EN		BIT(3)
+#define DSI_HSTX_LDO_REF_SEL	GENMASK(9, 6)
+#define HFP_HS_EN		BIT(31)
+
+#define MIPITX_CPHY_LANE_SEL0_SETTING	0x65432101
+#define MIPITX_CPHY_LANE_SEL1_SETTING	0x24210987
+#define MIPITX_CPHY_LANE_SEL2_SETTING	0x68543102
+#define MIPITX_CPHY_LANE_SEL3_SETTING	0x00000007
+
+void mtk_dsi_cphy_lane_sel_setting(void)
+{
+	write32(&mipi_tx->phy_sel[0], MIPITX_CPHY_LANE_SEL0_SETTING);
+	write32(&mipi_tx->phy_sel[1], MIPITX_CPHY_LANE_SEL1_SETTING);
+	write32(&mipi_tx->phy_sel[2], MIPITX_CPHY_LANE_SEL2_SETTING);
+	write32(&mipi_tx->phy_sel[3], MIPITX_CPHY_LANE_SEL3_SETTING);
+}
+
+void mtk_dsi_cphy_enable(void)
+{
+	setbits32(&mipi_tx->lane_con, DSI_CPHY_EN);
+}
+
+void mtk_dsi_cphy_disable_ck_mode(void)
+{
+	clrsetbits32(&mipi_tx->voltage_sel, DSI_HSTX_LDO_REF_SEL, 0xF << 6);
+	clrbits32(&mipi_tx->ck_ckmode_en, DSI_CK_CKMODE_EN);
+	setbits32(&mipi_tx->lane_con, DE_EMPHASIS_EN);
+}
+
+void mtk_dsi_cphy_enable_cmdq_6byte(void)
+{
+	clrbits32(&dsi0->dsi_cmd_type1_hs, CMD_CPHY_6BYTE_EN);
+}
+
+void mtk_dsi_cphy_timing(u32 data_rate, struct mtk_phy_timing *timing)
+{
+	u32 cycle_time, value;
+
+	data_rate = data_rate / MHz;
+	cycle_time = 7000 / data_rate;
+	printk(BIOS_INFO, "cycle_time = %d data_rate= %d\n", cycle_time, data_rate);
+	/* spec. lpx > 50ns */
+	timing->lpx = DIV_ROUND_UP(75, cycle_time);
+	/* spec.  38ns < hs_prpr < 95ns */
+	timing->da_hs_prepare = DIV_ROUND_UP(64, cycle_time);
+	/* spec.  7ui < hs_zero(prebegin) < 448ui */
+	timing->da_hs_zero = 48;
+	/* spec.  7ui < hs_trail(post) < 224ui */
+	timing->da_hs_trail = 32;
+
+	/* spec. ta_get = 5*lpx */
+	timing->ta_get = 5 * timing->lpx;
+	/* spec. ta_sure = 1.5*lpx */
+	timing->ta_sure = 3 * timing->lpx / 2;
+	/* spec. ta_go = 4*lpx */
+	timing->ta_go = 4 * timing->lpx;
+	/* spec. da_hs_exit > 100ns */
+	timing->da_hs_exit = DIV_ROUND_UP(125, cycle_time);
+
+	/* Allow board-specific tuning. */
+	mtk_dsi_override_phy_timing(timing);
+
+	value = timing->lpx | timing->da_hs_prepare << 8 |
+		  timing->da_hs_zero << 16 | timing->da_hs_trail << 24;
+	write32(&dsi0->dsi_phy_timecon0, value);
+
+	value = timing->ta_go | timing->ta_sure << 8 |
+		  timing->ta_get << 16 | timing->da_hs_exit << 24;
+	write32(&dsi0->dsi_phy_timecon1, value);
+
+	write32(&dsi0->dsi_cphy_con0, 0x012C0003);
+	write32(&dsi0->dsi_bllp_wc, 16 * 3);
+}
+
+void mtk_dsi_cphy_vdo_timing(const u32 lanes,
+			     const struct edid *edid,
+			     const struct mtk_phy_timing *phy_timing,
+			     const u32 bytes_per_pixel,
+			     const u32 hbp,
+			     const u32 hfp,
+			     s32 *hbp_byte,
+			     s32 *hfp_byte,
+			     u32 *hsync_active_byte)
+{
+	s32 active_byte, phy_cycle, phy_trail, tmp;
+	u32 hs_vb_ps_wc, ps_wc, data_phy_cycles;
+
+	active_byte = edid->mode.hspw * bytes_per_pixel - 10 * lanes - 26;
+	*hsync_active_byte = MAX(4, active_byte);
+	active_byte =  hbp * bytes_per_pixel - 12 * lanes - 26;
+	*hbp_byte = MAX(4, active_byte);
+	data_phy_cycles = phy_timing->lpx + phy_timing->da_hs_prepare +
+				phy_timing->da_hs_zero + phy_timing->da_hs_exit + 5;
+	phy_cycle = 8 * lanes + 28 + 2 * data_phy_cycles * lanes;
+	phy_trail = 2 * (phy_timing->da_hs_trail + 1) * lanes - 6 * lanes - 14;
+	tmp = hfp * bytes_per_pixel - phy_cycle;
+	*hfp_byte = MIN(MAX(8, tmp), phy_trail);
+	ps_wc = edid->mode.ha * bytes_per_pixel;
+	hs_vb_ps_wc = ps_wc - (phy_timing->lpx + phy_timing->da_hs_exit +
+		phy_timing->da_hs_prepare + phy_timing->da_hs_zero + 2) * lanes;
+	*hfp_byte |= hs_vb_ps_wc << 16 | HFP_HS_EN;
+}
diff --git a/src/soc/mediatek/common/mtk_mipi_dphy.c b/src/soc/mediatek/common/mtk_mipi_dphy.c
index d50a7898be..278f578cf2 100644
--- a/src/soc/mediatek/common/mtk_mipi_dphy.c
+++ b/src/soc/mediatek/common/mtk_mipi_dphy.c
@@ -1,63 +1,9 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
-#include <assert.h>
 #include <device/mmio.h>
-#include <delay.h>
 #include <soc/dsi.h>
-#include <soc/pll.h>
-#include <types.h>
 
-void mtk_dsi_configure_mipi_tx(u32 data_rate, u32 lanes)
+void mtk_dsi_dphy_disable_ck_mode(void)
 {
-	unsigned int txdiv0, txdiv1;
-	u64 pcw;
-
-	if (data_rate >= 2000 * MHz) {
-		txdiv0 = 0;
-		txdiv1 = 0;
-	} else if (data_rate >= 1000 * MHz) {
-		txdiv0 = 1;
-		txdiv1 = 0;
-	} else if (data_rate >= 500 * MHz) {
-		txdiv0 = 2;
-		txdiv1 = 0;
-	} else if (data_rate > 250 * MHz) {
-		/* (data_rate == 250MHz) is a special case that should go to the
-		   else-block below (txdiv0 = 4) */
-		txdiv0 = 3;
-		txdiv1 = 0;
-	} else {
-		/* MIN = 125 */
-		assert(data_rate >= MTK_DSI_DATA_RATE_MIN_MHZ * MHz);
-		txdiv0 = 4;
-		txdiv1 = 0;
-	}
-
-	clrbits32(&mipi_tx->pll_con4, BIT(11) | BIT(10));
-	setbits32(&mipi_tx->pll_pwr, AD_DSI_PLL_SDM_PWR_ON);
-	udelay(30);
-	clrbits32(&mipi_tx->pll_pwr, AD_DSI_PLL_SDM_ISO_EN);
-
-	pcw = (u64)data_rate * (1 << txdiv0) * (1 << txdiv1);
-	pcw <<= 24;
-	pcw /= CLK26M_HZ;
-
-	write32(&mipi_tx->pll_con0, pcw);
-	clrsetbits32(&mipi_tx->pll_con1, RG_DSI_PLL_POSDIV, txdiv0 << 8);
-	udelay(30);
-	setbits32(&mipi_tx->pll_con1, RG_DSI_PLL_EN);
-
-	/* BG_LPF_EN / BG_CORE_EN */
-	write32(&mipi_tx->lane_con, 0x3fff0180);
-	udelay(40);
-	write32(&mipi_tx->lane_con, 0x3fff00c0);
-
-	/* Switch OFF each Lane */
-	clrbits32(&mipi_tx->d0_sw_ctl_en, DSI_SW_CTL_EN);
-	clrbits32(&mipi_tx->d1_sw_ctl_en, DSI_SW_CTL_EN);
-	clrbits32(&mipi_tx->d2_sw_ctl_en, DSI_SW_CTL_EN);
-	clrbits32(&mipi_tx->d3_sw_ctl_en, DSI_SW_CTL_EN);
-	clrbits32(&mipi_tx->ck_sw_ctl_en, DSI_SW_CTL_EN);
-
 	setbits32(&mipi_tx->ck_ckmode_en, DSI_CK_CKMODE_EN);
 }
diff --git a/src/soc/mediatek/mt8173/dsi.c b/src/soc/mediatek/mt8173/dsi.c
index ad379aecf5..c47634ef4e 100644
--- a/src/soc/mediatek/mt8173/dsi.c
+++ b/src/soc/mediatek/mt8173/dsi.c
@@ -7,7 +7,7 @@
 #include <soc/dsi.h>
 #include <timer.h>
 
-void mtk_dsi_configure_mipi_tx(u32 data_rate, u32 lanes)
+void mtk_dsi_configure_mipi_tx(u32 data_rate, u32 lanes, bool is_cphy)
 {
 	u32 txdiv0, txdiv1;
 	u64 pcw;

From 979fdee1d9be2ff3d52e94a2cce607ec23b873f7 Mon Sep 17 00:00:00 2001
From: Vince Liu <vince-wl.liu@mediatek.corp-partner.google.com>
Date: Fri, 17 Oct 2025 13:33:13 +0800
Subject: [PATCH 2338/3886] soc/mediatek/mt8189: Support MIPI C-PHY interface

Add config `MEDIATEK_DSI_CPHY` to enable the MIPI C-PHY interface on
mt8189, including necessary register definitions and integrating with
the common MIPI driver, dsi_register_v2.

BUG=b:433422905,b:428854543
TEST=Check display initialization log on padme
mtk_display_init: 'TM TL121BVMS07' 1600x2560@60Hz

Signed-off-by: Vince Liu <vince-wl.liu@mediatek.corp-partner.google.com>
Change-Id: Iac6c1b6d47331b63e7b45157bd60da93f104b0ee
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89620
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
---
 src/soc/mediatek/mt8189/Kconfig           |  1 +
 src/soc/mediatek/mt8189/Makefile.mk       |  2 +
 src/soc/mediatek/mt8189/include/soc/dsi.h | 54 +++++++++++++++++++++++
 3 files changed, 57 insertions(+)

diff --git a/src/soc/mediatek/mt8189/Kconfig b/src/soc/mediatek/mt8189/Kconfig
index ea3c7d2ece..786236478c 100644
--- a/src/soc/mediatek/mt8189/Kconfig
+++ b/src/soc/mediatek/mt8189/Kconfig
@@ -16,6 +16,7 @@ config SOC_MEDIATEK_MT8189
 	select SOC_MEDIATEK_COMMON
 	select FLASH_DUAL_IO_READ
 	select ARM64_USE_ARCH_TIMER
+	select MEDIATEK_DSI_CPHY
 
 if SOC_MEDIATEK_MT8189
 
diff --git a/src/soc/mediatek/mt8189/Makefile.mk b/src/soc/mediatek/mt8189/Makefile.mk
index 02e2847123..351c94190b 100644
--- a/src/soc/mediatek/mt8189/Makefile.mk
+++ b/src/soc/mediatek/mt8189/Makefile.mk
@@ -46,6 +46,7 @@ ramstage-y += ../common/dp/dp_intf_v2.c
 ramstage-y += ../common/dp/dptx_common.c ../common/dp/dptx_v2.c dptx.c
 ramstage-y += ../common/dp/dptx_hal_common.c ../common/dp/dptx_hal_v2.c  dptx_hal.c
 ramstage-y += ../common/dramc_info.c
+ramstage-y += ../common/dsi_common.c ../common/dsi_v1.c
 ramstage-y += ../common/emi.c
 ramstage-y += ../common/mcu.c mcupm.c
 ramstage-y += ../common/memory.c
@@ -55,6 +56,7 @@ ramstage-y += ../common/mt6315.c mt6315.c
 ramstage-y += ../common/mt6359p.c mt6359p.c
 ramstage-y += ../common/mtcmos.c mtcmos.c
 ramstage-y += ../common/mtk_fsp.c
+ramstage-y += ../common/mtk_mipi_cphy.c ../common/mtk_mipi_dphy.c
 ramstage-y += ../common/pi_image.c
 ramstage-y += ../common/pmif.c ../common/pmif_clk.c ../common/pmif_init.c pmif_clk.c
 ramstage-y += ../common/pmif_spi.c pmif_spi.c
diff --git a/src/soc/mediatek/mt8189/include/soc/dsi.h b/src/soc/mediatek/mt8189/include/soc/dsi.h
index 443e743b87..ad3a04d721 100644
--- a/src/soc/mediatek/mt8189/include/soc/dsi.h
+++ b/src/soc/mediatek/mt8189/include/soc/dsi.h
@@ -4,5 +4,59 @@
 #define SOC_MEDIATEK_MT8189_DSI_H
 
 #include <soc/dsi_common.h>
+#include <soc/dsi_register_v2.h>
+#include <types.h>
+
+/* DSI features */
+#define MTK_DSI_MIPI_RATIO_NUMERATOR 100
+#define MTK_DSI_MIPI_RATIO_DENOMINATOR 100
+#define MTK_DSI_DATA_RATE_MIN_MHZ 125
+#define MTK_DSI_HAVE_SIZE_CON 1
+#define PIXEL_STREAM_CUSTOM_HEADER 0xb
+
+/* MIPITX is SOC specific and cannot live in common. */
+
+/* MIPITX_REG */
+struct mipi_tx_regs {
+	u32 reserved0[3];
+	u32 lane_con;
+	u32 voltage_sel;
+	u32 reserved1[5];
+	u32 pll_pwr;
+	u32 pll_con0;
+	u32 pll_con1;
+	u32 pll_con2;
+	u32 pll_con3;
+	u32 pll_con4;
+	u32 phy_sel[4];
+	u32 reserved2[61];
+	u32 d2_sw_ctl_en;
+	u32 reserved3[63];
+	u32 d0_sw_ctl_en;
+	u32 reserved4[56];
+	u32 ck_ckmode_en;
+	u32 reserved5[6];
+	u32 ck_sw_ctl_en;
+	u32 reserved6[63];
+	u32 d1_sw_ctl_en;
+	u32 reserved7[63];
+	u32 d3_sw_ctl_en;
+};
+
+check_member(mipi_tx_regs, voltage_sel, 0x10);
+check_member(mipi_tx_regs, pll_con4, 0x3C);
+check_member(mipi_tx_regs, phy_sel[0], 0x40);
+check_member(mipi_tx_regs, phy_sel[3], 0x4C);
+check_member(mipi_tx_regs, d3_sw_ctl_en, 0x544);
+static struct mipi_tx_regs *const mipi_tx = (void *)MIPITX0_BASE;
+
+/* Register values */
+#define DSI_CK_CKMODE_EN	BIT(0)
+#define DSI_SW_CTL_EN		BIT(0)
+#define AD_DSI_PLL_SDM_PWR_ON	BIT(0)
+#define AD_DSI_PLL_SDM_ISO_EN	BIT(1)
+
+#define RG_DSI_PLL_EN		BIT(4)
+#define RG_DSI_PLL_POSDIV	(0x7 << 8)
 
 #endif

From 8f1c54685ae9b8f928e910f4d3fa06bb34cc4e2b Mon Sep 17 00:00:00 2001
From: Yang Wu <wuyang5@huaqin.corp-partner.google.com>
Date: Tue, 14 Oct 2025 19:49:36 +0800
Subject: [PATCH 2339/3886] drivers/mipi: Fix pixel clock and enable C-PHY for
 TM_TL121BVMS07_00C

Commit ddf5987c1e ("drivers/mipi: Add support for
TM_TL121BVMS07_00C panel") (CB:89216) added support for the
TM_TL121BVMS07_00C panel, but the screen was not functional.

Decrease the pixel clock from 4,400,560 Hz to 264,355 Hz to match the
actual panel timing specification. Also, the panel uses C-PHY interface,
so enable the `PANEL_FLAG_CPHY` flag accordingly.

Datasheet: Preliminary+specification+TL121BVMS07+-00+V01+20250721.pdf

BUG=b:428854543
TEST=build and check firmware screen.
BRANCH=skywalker

Change-Id: I88fa5215d7596926aa95a58ae91dd6ade793388b
Signed-off-by: Yang Wu <wuyang5@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89568
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/drivers/mipi/panel-TM_TL121BVMS07_00C.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/src/drivers/mipi/panel-TM_TL121BVMS07_00C.c b/src/drivers/mipi/panel-TM_TL121BVMS07_00C.c
index 22f6d87a42..e69d8ebc54 100644
--- a/src/drivers/mipi/panel-TM_TL121BVMS07_00C.c
+++ b/src/drivers/mipi/panel-TM_TL121BVMS07_00C.c
@@ -9,7 +9,7 @@ struct panel_serializable_data TM_TL121BVMS07_00C = {
 		.panel_bits_per_color = 8,
 		.panel_bits_per_pixel = 24,
 		.mode = {
-			.pixel_clock = 4400560,
+			.pixel_clock = 264355,
 			.lvds_dual_channel = 0,
 			.refresh = 60,
 			.ha = 1600, .hbl = 44, .hso = 20, .hspw = 4,
@@ -35,4 +35,5 @@ struct panel_serializable_data TM_TL121BVMS07_00C = {
 		PANEL_DELAY(20),
 		PANEL_END,
 	},
+	.flags = PANEL_FLAG_CPHY,
 };

From fea1b2abbe43c50ffd80877eb66b7759b1c57e3d Mon Sep 17 00:00:00 2001
From: Zheng Li <lizheng@huaqin.corp-partner.google.com>
Date: Sat, 25 Oct 2025 18:28:54 +0800
Subject: [PATCH 2340/3886] mb/google/nissa/var/pujjocento: Adjust touch panel
 timing for stability

Reduce reset delay from 20ms to 0ms to shorten total tp_rst time from
350ms to 330ms. Validation on Prade shows the controller initializes
reliably within the reduced timing. It will be able to complete the
following steps before vccs on.

1. TP Reset
2. Get HID Description
3. HID Reset/HID Power On
4. Get Report Descriptor/Get Feature Report

Verification results are in b/455053468 comment#3

BUG=b:455053468
BRANCH=none
TEST=Build and boot to pujjocento. Verify touchpanel sequence

Change-Id: I4efa4e927e78d3200b357f5f5b41c3d2aef12f8b
Signed-off-by: Zheng Li <lizheng@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89748
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
---
 src/mainboard/google/brya/variants/pujjocento/overridetree.cb | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/mainboard/google/brya/variants/pujjocento/overridetree.cb b/src/mainboard/google/brya/variants/pujjocento/overridetree.cb
index 8b7382c8a0..469a880cd6 100644
--- a/src/mainboard/google/brya/variants/pujjocento/overridetree.cb
+++ b/src/mainboard/google/brya/variants/pujjocento/overridetree.cb
@@ -547,7 +547,7 @@ chip soc/intel/alderlake
 				register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_E11_IRQ)"
 				register "generic.detect" = "1"
 				register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C1)"
-				register "generic.reset_delay_ms" = "20"
+				register "generic.reset_delay_ms" = "0"
 				register "generic.reset_off_delay_ms" = "2"
 				register "generic.stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C4)"
 				register "generic.stop_off_delay_ms" = "2"

From b1ed60b910a770ffccd5b5e97b0629b8a93149d1 Mon Sep 17 00:00:00 2001
From: Luca Lai <luca.lai@lcfc.corp-partner.google.com>
Date: Thu, 23 Oct 2025 14:17:09 +0800
Subject: [PATCH 2341/3886] mb/google/fatcat/var/ruby: Disable
 FSP_UGOP_EARLY_SIGN_OF_LIFE temporarily

Disable FSP_UGOP_EARLY_SIGN_OF_LIFE temporarily to workaround
memory training issue.

BUG=b:452180266
TEST=Build and boot to OS.

Change-Id: I9a928319fae7d5340848412f5af83e6294681933
Signed-off-by: Luca Lai <luca.lai@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89688
Reviewed-by: Derek Huang <derekhuang@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/google/fatcat/Kconfig | 1 -
 1 file changed, 1 deletion(-)

diff --git a/src/mainboard/google/fatcat/Kconfig b/src/mainboard/google/fatcat/Kconfig
index 6d9c72a167..394bf4f515 100644
--- a/src/mainboard/google/fatcat/Kconfig
+++ b/src/mainboard/google/fatcat/Kconfig
@@ -154,7 +154,6 @@ config BOARD_GOOGLE_MOONSTONE
 config BOARD_GOOGLE_MODEL_RUBY
 	def_bool n
 	select BOARD_GOOGLE_BASEBOARD_FATCAT
-	select FSP_UGOP_EARLY_SIGN_OF_LIFE
 	select HAVE_SLP_S0_GATE
 	select MAINBOARD_HAS_GOOGLE_STRAUSS_KEYBOARD
 

From 7484a887b855bfbb33d1648042e7bbc022cc88cb Mon Sep 17 00:00:00 2001
From: Appukuttan V K <appukuttan.vk@intel.com>
Date: Wed, 8 Oct 2025 16:41:20 +0530
Subject: [PATCH 2342/3886] mb/google/ocelot: Fix EC sync IRQ configuration for
 board variants

This patch corrects the EC sync IRQ configuration logic to properly
handle different ocelot board variants:

1. Update conditional compilation in ec.h to exclude OCELOTMCHP and
   OCELOTMCHP4ES variants from EC_ENABLE_SYNC_IRQ, as these boards do
   not have the EC sync IRQ connected.
2. Restructure GPIO definitions in gpio.h to:
 - Set EC_SYNC_IRQ to 0 (not connected) for OCELOTMCHP, OCELOTMCHP4ES,
   variants.
 - Enable EC_SYNC_IRQ on GPP_E08_IRQ for OCELOT, OCELOT4ES, OCELOTITE,
   and OCELOTITE4ES variants.
3. Configure GPP_E08 pad appropriately in gpio.c:
 - Set as NC (not connected) for OCELOTMCHP variants.
 - Configure as APIC interrupt for other variants that support EC sync
   IRQ functionality.

BUG=NONE
TEST=Build and boot on Ocelot variants.

Change-Id: I96e92ed9d6fa5b586ab9c0faf73d08b55abe4795
Signed-off-by: Appukuttan V K <appukuttan.vk@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89459
Reviewed-by: Usha P <usha.p@intel.com>
Reviewed-by: Krishna P Bhat D <krishna.p.bhat.d@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 .../variants/baseboard/ocelot/include/baseboard/ec.h       | 2 +-
 .../variants/baseboard/ocelot/include/baseboard/gpio.h     | 7 +++++--
 src/mainboard/google/ocelot/variants/ocelot/gpio.c         | 7 ++++++-
 3 files changed, 12 insertions(+), 4 deletions(-)

diff --git a/src/mainboard/google/ocelot/variants/baseboard/ocelot/include/baseboard/ec.h b/src/mainboard/google/ocelot/variants/baseboard/ocelot/include/baseboard/ec.h
index aa8f052b47..e4edd51378 100644
--- a/src/mainboard/google/ocelot/variants/baseboard/ocelot/include/baseboard/ec.h
+++ b/src/mainboard/google/ocelot/variants/baseboard/ocelot/include/baseboard/ec.h
@@ -75,7 +75,7 @@
 /* Enable EC backed PD MCU device in ACPI */
 #define EC_ENABLE_PD_MCU_DEVICE
 
-#if !CONFIG(BOARD_GOOGLE_OCELOT) && !CONFIG(BOARD_GOOGLE_OCELOT4ES) && \
+#if !CONFIG(BOARD_GOOGLE_OCELOTMCHP) && !CONFIG(BOARD_GOOGLE_OCELOTMCHP4ES) && \
 !CONFIG(BOARD_GOOGLE_OJAL)
  #define EC_ENABLE_SYNC_IRQ      /* Enable tight timestamp / wake support */
  #define EC_SYNC_IRQ_WAKE_CAPABLE /* Let the OS know ec_sync is wake capable */
diff --git a/src/mainboard/google/ocelot/variants/baseboard/ocelot/include/baseboard/gpio.h b/src/mainboard/google/ocelot/variants/baseboard/ocelot/include/baseboard/gpio.h
index a0983a543a..409c4d58e0 100644
--- a/src/mainboard/google/ocelot/variants/baseboard/ocelot/include/baseboard/gpio.h
+++ b/src/mainboard/google/ocelot/variants/baseboard/ocelot/include/baseboard/gpio.h
@@ -12,11 +12,14 @@
  * EC_SYNC_IRQ - GPIO IRQ for tight timestamps / wake support
  * GPIO_PCH_WP - WP signal to PCH
  */
-//TODO for Nuvo: #define EC_SYNC_IRQ	GPP_E07_IRQ
-#if CONFIG(BOARD_GOOGLE_MODEL_OCELOT) || CONFIG(BOARD_GOOGLE_MODEL_OJAL)
+#if (CONFIG(BOARD_GOOGLE_OCELOTMCHP) || CONFIG(BOARD_GOOGLE_OCELOTMCHP4ES) \
+	|| CONFIG(BOARD_GOOGLE_MODEL_OJAL))
  #define EC_SYNC_IRQ	0 /* Not Connected */
 #elif CONFIG(BOARD_GOOGLE_MODEL_KODKOD)
  #define EC_SYNC_IRQ	GPP_F10_IRQ
+#elif (CONFIG(BOARD_GOOGLE_OCELOT) || CONFIG(BOARD_GOOGLE_OCELOT4ES) \
+	|| CONFIG(BOARD_GOOGLE_OCELOTITE) || CONFIG(BOARD_GOOGLE_OCELOTITE4ES))
+ #define EC_SYNC_IRQ	GPP_E08_IRQ
 #elif CONFIG(BOARD_GOOGLE_MODEL_MATSU)
  #define EC_SYNC_IRQ	GPP_E08_IRQ
 #endif
diff --git a/src/mainboard/google/ocelot/variants/ocelot/gpio.c b/src/mainboard/google/ocelot/variants/ocelot/gpio.c
index 32e1ae11fb..405a424600 100644
--- a/src/mainboard/google/ocelot/variants/ocelot/gpio.c
+++ b/src/mainboard/google/ocelot/variants/ocelot/gpio.c
@@ -171,8 +171,13 @@ static const struct pad_config gpio_table[] = {
 	PAD_CFG_GPI_TRIG_OWN(GPP_E06, NONE, DEEP, LEVEL, ACPI),
 	/* GPP_E07:     LAN_GPIO_RST_N */
 	PAD_CFG_GPO(GPP_E07, 1, PLTRST),
+#if CONFIG(BOARD_GOOGLE_OCELOTMCHP) || CONFIG(BOARD_GOOGLE_OCELOTMCHP4ES)
+	/* GPP_E08:     Not used */
+	PAD_NC(GPP_E08, NONE),
+#else
 	/* GPP_E08:     EC_SOC_INT_ODL */
-	PAD_CFG_GPI(GPP_E08, NONE, DEEP),
+	PAD_CFG_GPI_APIC_LOCK(GPP_E08, NONE, LEVEL, INVERT, LOCK_CONFIG),
+#endif
 	/* GPP_E09:     USB_FP_CONN_1_CONN_2_OC0_N */
 	PAD_CFG_NF(GPP_E09, NONE, DEEP, NF1),
 	/* GPP_E10:     M2_UFS_DET_SEL_N */

From a5ddfa963f48f22f08f088147a03eed0615ab092 Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Mon, 27 Oct 2025 08:09:18 +0000
Subject: [PATCH 2343/3886] mb/starlabs/starlite_adl: Increase ME region size
 to match IFD

Increase the ME region by 4KiB to match the IFD that is used for
both the Alder Lake and Twin Lake versions.

Change-Id: I22fa2388ed5660b959815be00029c07cac2b5244
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89761
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/starlabs/starlite_adl/variants/mk_v/board.fmd | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/mainboard/starlabs/starlite_adl/variants/mk_v/board.fmd b/src/mainboard/starlabs/starlite_adl/variants/mk_v/board.fmd
index 3c64b27134..bc72a6098d 100644
--- a/src/mainboard/starlabs/starlite_adl/variants/mk_v/board.fmd
+++ b/src/mainboard/starlabs/starlite_adl/variants/mk_v/board.fmd
@@ -1,7 +1,7 @@
 FLASH	0x1000000 {
 	SI_ALL	0x600000 {
 		SI_DESC			0x1000
-		SI_ME			0x411000
+		SI_ME			0x412000
 	}
 	SI_BIOS 0xa00000 {
 		EC@0x0			0x20000

From e2cf7f7dc7fa1dc46f629e5835d9b16888f17e2a Mon Sep 17 00:00:00 2001
From: Yidi Lin <yidilin@google.com>
Date: Mon, 27 Oct 2025 12:03:39 +0800
Subject: [PATCH 2344/3886] soc/mediatek/common: Fix MMU assertion for
 framebuffer region

Configure MMU for framebuffer region only when framebuffer region
exists (i.e., REGION_SIZE(framebuffer) > 0). Otherwise, the MMU would
raise assertion.

[INFO ]  Mapping address range [0x0000040000000:0x0000240000000) as cacheable | read-write | non-secure | normal
[INFO ]  Mapping address range [0x0000040000000:0x0000040100000) as non-cacheable | read-write | non-secure | normal
[DEBUG]  Backing address range [0x0000040000000:0x0000080000000) with new L2 table @0x020da000
[DEBUG]  Backing address range [0x0000040000000:0x0000040200000) with new L3 table @0x020db000
[INFO ]  Mapping address range [0x0000000000000:0x0000000000000) as non-cacheable | read-write | non-secure | normal
[EMERG]  ASSERTION ERROR: file 'src/arch/arm64/armv8/mmu.c', line 194

BUG=b:454457496
TEST=The assertion does not occur.

Change-Id: I8ab17bd289cd41a4568fddff2e556e5e49b1e6a4
Signed-off-by: Yidi Lin <yidilin@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89759
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
---
 src/soc/mediatek/common/mmu_operations.c | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/src/soc/mediatek/common/mmu_operations.c b/src/soc/mediatek/common/mmu_operations.c
index 68ac77d515..738bcba6fc 100644
--- a/src/soc/mediatek/common/mmu_operations.c
+++ b/src/soc/mediatek/common/mmu_operations.c
@@ -1,7 +1,6 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
 #include <arch/mmu.h>
-#include <bootmode.h>
 #include <symbols.h>
 #include <soc/emi.h>
 #include <soc/mmu_operations.h>
@@ -52,7 +51,7 @@ void mtk_mmu_after_dram(void)
 
 	mmu_config_range(_dram_dma, REGION_SIZE(dram_dma), NONSECURE_UNCACHED_MEM);
 
-	if (display_init_required())
+	if (REGION_SIZE(framebuffer))
 		mmu_config_range(_framebuffer, REGION_SIZE(framebuffer),
 				 NONSECURE_UNCACHED_MEM);
 

From bbb895436ff222a1a78b7f7cee79ab81c95faec2 Mon Sep 17 00:00:00 2001
From: Luca Lai <luca.lai@lcfc.corp-partner.google.com>
Date: Wed, 17 Sep 2025 20:49:34 +0800
Subject: [PATCH 2345/3886] mb/nissa/var/pujjoga: Add single ram configuration

Pujjoga and pujjogatwin projects are both going to be single RAM device, so add single ram configuration.

Schematic version: 500E_GEN4S_ADL_N_MB_250920

Below log show the device can recognize the single dram.
[INFO ]  SPD: module type is LPDDR5X
[INFO ]  SPD: module part number is H9JCNNNBK3MLYR-N6E
[INFO ]  SPD: banks 8, ranks 1, rows 16, columns 11, density 16384 Mb
[INFO ]  SPD: device width 16 bits, bus width 16 bits
[INFO ]  SPD: module size is 2048 MB (per channel)
[INFO ]  Device only supports one DIMM. Disable all other memory
channels except first two on each memory controller.
[DEBUG]  CBMEM:
[DEBUG]  IMD: root @ 0x76fff000 254 entries.
[DEBUG]  IMD: root @ 0x76ffec00 62 entries.

BUG=b:445629015
BRANCH=none
TEST=Build and boot to OS. Verify functions work.

Change-Id: I22e8335432e6e65bd1640bf6a6dec03691e3462e
Signed-off-by: Luca Lai <luca.lai@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89221
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/google/brya/Kconfig             |  2 ++
 .../google/brya/variants/pujjoga/Makefile.mk  |  1 +
 .../google/brya/variants/pujjoga/gpio.c       |  4 ++++
 .../google/brya/variants/pujjoga/memory.c     | 21 +++++++++++++++++++
 4 files changed, 28 insertions(+)
 create mode 100644 src/mainboard/google/brya/variants/pujjoga/memory.c

diff --git a/src/mainboard/google/brya/Kconfig b/src/mainboard/google/brya/Kconfig
index 156a9e4a45..e1524bd206 100644
--- a/src/mainboard/google/brya/Kconfig
+++ b/src/mainboard/google/brya/Kconfig
@@ -491,6 +491,7 @@ config BOARD_GOOGLE_PUJJOGA
 	select CHROMEOS_WIFI_SAR if CHROMEOS
 	select DRIVERS_I2C_SX9324
 	select DRIVERS_I2C_SX9324_SUPPORT_LEGACY_LINUX_DRIVER
+	select ENFORCE_MEM_CHANNEL_DISABLE
 	select HAVE_WWAN_POWER_SEQUENCE
 	select INTEL_GMA_HAVE_VBT
 
@@ -500,6 +501,7 @@ config BOARD_GOOGLE_PUJJOGATWIN
 	select CHROMEOS_WIFI_SAR if CHROMEOS
 	select DRIVERS_I2C_SX9324
 	select DRIVERS_I2C_SX9324_SUPPORT_LEGACY_LINUX_DRIVER
+	select ENFORCE_MEM_CHANNEL_DISABLE
 	select HAVE_WWAN_POWER_SEQUENCE
 	select INTEL_GMA_HAVE_VBT
 	select SOC_INTEL_TWINLAKE
diff --git a/src/mainboard/google/brya/variants/pujjoga/Makefile.mk b/src/mainboard/google/brya/variants/pujjoga/Makefile.mk
index e04a887191..42b4080783 100644
--- a/src/mainboard/google/brya/variants/pujjoga/Makefile.mk
+++ b/src/mainboard/google/brya/variants/pujjoga/Makefile.mk
@@ -2,6 +2,7 @@
 bootblock-y += gpio.c
 
 romstage-y += gpio.c
+romstage-y += memory.c
 
 ramstage-$(CONFIG_FW_CONFIG) += fw_config.c
 ramstage-y += variant.c
diff --git a/src/mainboard/google/brya/variants/pujjoga/gpio.c b/src/mainboard/google/brya/variants/pujjoga/gpio.c
index 6098db9345..39a405a87a 100644
--- a/src/mainboard/google/brya/variants/pujjoga/gpio.c
+++ b/src/mainboard/google/brya/variants/pujjoga/gpio.c
@@ -32,6 +32,8 @@ static const struct pad_config override_gpio_table[] = {
 	PAD_NC_LOCK(GPP_D16, NONE, LOCK_CONFIG),
 	/* D17 : NC ==> SD_WAKE_N */
 	PAD_CFG_GPI_LOCK(GPP_D17, NONE, LOCK_CONFIG),
+	/* E9  : NC ==> DIMM_CHANNEL_SELECT */
+	PAD_CFG_GPI_LOCK(GPP_E9, DN_20K, LOCK_CONFIG),
 	/* E20  : NC */
 	PAD_NC_LOCK(GPP_E20, NONE, LOCK_CONFIG),
 	/* E21  : NC */
@@ -66,6 +68,8 @@ static const struct pad_config early_gpio_table[] = {
 	*/
 	/* D6  : SRCCLKREQ1# ==> WWAN_EN */
 	PAD_CFG_GPO(GPP_D6, 0, DEEP),
+	/* E9  : NC ==> DIMM_CHANNEL_SELECT */
+	PAD_CFG_GPI_LOCK(GPP_E9, DN_20K, LOCK_CONFIG),
 	/* E12 : THC0_SPI1_IO1 ==> SOC_WP_OD */
 	PAD_CFG_GPI_GPIO_DRIVER(GPP_E12, NONE, DEEP),
 	/* F12 : WWAN_RST_L */
diff --git a/src/mainboard/google/brya/variants/pujjoga/memory.c b/src/mainboard/google/brya/variants/pujjoga/memory.c
new file mode 100644
index 0000000000..3ff8a24998
--- /dev/null
+++ b/src/mainboard/google/brya/variants/pujjoga/memory.c
@@ -0,0 +1,21 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <baseboard/variants.h>
+#include <gpio.h>
+#include <soc/romstage.h>
+
+uint8_t mb_get_channel_disable_mask(void)
+{
+	/*
+	 * GPP_E9 High -> Single RAM Chip
+	 * GPP_E9 Low  -> Dual RAM Chip
+	 */
+	if (gpio_get(GPP_E9)) {
+		/* Disable all other channels except first two on each controller */
+		printk(BIOS_INFO, "Device only supports one DIMM. Disable all other memory"
+		"channels except first two on each memory controller.\n");
+		return (BIT(2) | BIT(3));
+	}
+	return 0;
+
+}

From a92a2ee5d6ccae25ad8119ab172da33561c638e9 Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Tue, 28 Oct 2025 09:05:53 +0000
Subject: [PATCH 2346/3886] mb/starlabs/byte_adl: Expose fan control option in
 CFR

Test=Change fan mode on byte_adl in edk2 and verify correct value
is written to the EC memory using `ectool -d`

Change-Id: I93d4be663a059abb973ad6abf2e60d40f56ed6c7
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89782
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
---
 src/mainboard/starlabs/byte_adl/cfr.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/src/mainboard/starlabs/byte_adl/cfr.c b/src/mainboard/starlabs/byte_adl/cfr.c
index 3e22595079..530821bd34 100644
--- a/src/mainboard/starlabs/byte_adl/cfr.c
+++ b/src/mainboard/starlabs/byte_adl/cfr.c
@@ -3,6 +3,7 @@
 #include <boot/coreboot_tables.h>
 #include <console/cfr.h>
 #include <drivers/option/cfr_frontend.h>
+#include <ec/starlabs/merlin/cfr.h>
 #include <intelblocks/cfr.h>
 #include <variants.h>
 
@@ -54,6 +55,7 @@ static struct sm_obj_form performance = {
 	.ui_name = "Performance",
 	.obj_list = (const struct sm_object *[]) {
 		&bluetooth_rtd3,
+		&fan_mode,
 		&power_profile,
 		NULL
 	},

From a748e8b82bc644e2e2f6fe1e2a2a8e3f701bf9c7 Mon Sep 17 00:00:00 2001
From: Luca Lai <luca.lai@lcfc.corp-partner.google.com>
Date: Mon, 27 Oct 2025 10:50:19 +0800
Subject: [PATCH 2347/3886] mb/google/fatcat/var/ruby: Enable touchpad function
 using I2C interface

Modify gpio setting to redundant enable the touchpad.

schematics: RUBY_EVT_0902_2112.pdf

Device i2c log:
[INFO ]  \_SB.PCI0.CNVW: WIFI Device GENERIC: 0.0
[INFO ]  \_SB.PCI0.I2C0.RT58: Headset Codec at I2C: 00:1a
[INFO ]  \_SB.PCI0.I2C0.D04B: TI SPK AMP L at I2C: 00:4b
[INFO ]  \_SB.PCI0.I2C0.D04C: TI SPK AMP R at I2C: 00:4c
[INFO ]  \_SB.PCI0.I2C0.D04D: 	TI SPK AMP TL at I2C: 00:4d
[INFO ]  \_SB.PCI0.I2C0.D04F: T1 SPK AMP TR at I2C: 00:4f
[INFO ]  \_SB.PCI0.I2C3.TPMI: I2C TPM at I2C: 00:50
[INFO ]  \_SB.PCI0.I2C4.H015: ELAN Touchpad at I2C: 00:15
[INFO ]  \_SB.PCI0.I2C5.H014: Goodix Touchscreen at I2C: 00:14
[INFO ]  \_SB.PCI0.RP01: Enable RTD3 for PCI: 00:00:1c.0 (Intel PCIe Runtime D3)

BUG=b:449901218
TEST=Build and boot to OS and use Elan touchpad module to verify the cursor works.

Change-Id: Id84f96eb07c97dddd5cd1498a18317f9a1676b55
Signed-off-by: Luca Lai <luca.lai@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89758
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: YH Lin <yueherngl@google.com>
---
 src/mainboard/google/fatcat/variants/ruby/gpio.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/mainboard/google/fatcat/variants/ruby/gpio.c b/src/mainboard/google/fatcat/variants/ruby/gpio.c
index f17fc8a883..ebaad6f95f 100644
--- a/src/mainboard/google/fatcat/variants/ruby/gpio.c
+++ b/src/mainboard/google/fatcat/variants/ruby/gpio.c
@@ -209,9 +209,9 @@ static const struct pad_config gpio_table[] = {
 	/* GPP_E11:     NC */
 	PAD_NC(GPP_E11, NONE),
 	/* GPP_E12:     THC0_SPI1_IO_0_I2C4_SCL_TCH_PAD1*/
-	PAD_CFG_NF(GPP_E12, NONE, DEEP, NF3),
+	PAD_CFG_NF(GPP_E12, NONE, DEEP, NF8),
 	/* GPP_E13:     THC0_SPI1_IO_1_I2C4_SDA_TCH_PAD1 */
-	PAD_CFG_NF(GPP_E13, NONE, DEEP, NF3),
+	PAD_CFG_NF(GPP_E13, NONE, DEEP, NF8),
 	/* GPP_E14:     NC */
 	PAD_NC(GPP_E14, NONE),
 	/* GPP_E15:     NC */

From 4563db28071e918f0394011d021ae6acd46625c8 Mon Sep 17 00:00:00 2001
From: David Wu <david_wu@quanta.corp-partner.google.com>
Date: Tue, 28 Oct 2025 15:02:13 +0800
Subject: [PATCH 2348/3886] mb/google/nissa/var/riven: Add H58G66CK8BX147 to
 RAM ID table

Add the new memory support: Hynix H58G66CK8BX147

BUG=b:455729238
TEST=Run part_id_gen tool and check the generated files.

Change-Id: Ieed017b6910313f28367c4e1923c403b305f5bde
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89781
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
---
 src/mainboard/google/brya/variants/riven/memory/Makefile.mk      | 1 +
 .../google/brya/variants/riven/memory/dram_id.generated.txt      | 1 +
 .../google/brya/variants/riven/memory/mem_parts_used.txt         | 1 +
 3 files changed, 3 insertions(+)

diff --git a/src/mainboard/google/brya/variants/riven/memory/Makefile.mk b/src/mainboard/google/brya/variants/riven/memory/Makefile.mk
index 47474d7f79..736e72c2c9 100644
--- a/src/mainboard/google/brya/variants/riven/memory/Makefile.mk
+++ b/src/mainboard/google/brya/variants/riven/memory/Makefile.mk
@@ -10,3 +10,4 @@ SPD_SOURCES += spd/lp5/set-0/spd-5.hex      # ID = 2(0b0010)  Parts = K3LKLKL0EM
 SPD_SOURCES += spd/lp5/set-0/spd-3.hex      # ID = 3(0b0011)  Parts = K3LKBKB0BM-MGCP
 SPD_SOURCES += spd/lp5/set-0/spd-7.hex      # ID = 4(0b0100)  Parts = K3KL8L80CM-MGCT
 SPD_SOURCES += spd/lp5/set-0/spd-11.hex      # ID = 5(0b0101)  Parts = H58G56BK8BX068, H58G56CK8BX146
+SPD_SOURCES += spd/lp5/set-0/spd-10.hex      # ID = 6(0b0110)  Parts = H58G66CK8BX147
diff --git a/src/mainboard/google/brya/variants/riven/memory/dram_id.generated.txt b/src/mainboard/google/brya/variants/riven/memory/dram_id.generated.txt
index 0832ee921f..305df54708 100644
--- a/src/mainboard/google/brya/variants/riven/memory/dram_id.generated.txt
+++ b/src/mainboard/google/brya/variants/riven/memory/dram_id.generated.txt
@@ -13,3 +13,4 @@ H9JCNNNCP3MLYR-N6E             0 (0000)
 K3KL8L80CM-MGCT                4 (0100)
 H58G56BK8BX068                 5 (0101)
 H58G56CK8BX146                 5 (0101)
+H58G66CK8BX147                 6 (0110)
diff --git a/src/mainboard/google/brya/variants/riven/memory/mem_parts_used.txt b/src/mainboard/google/brya/variants/riven/memory/mem_parts_used.txt
index 96ddbf738d..9f1f37de6d 100644
--- a/src/mainboard/google/brya/variants/riven/memory/mem_parts_used.txt
+++ b/src/mainboard/google/brya/variants/riven/memory/mem_parts_used.txt
@@ -18,3 +18,4 @@ H9JCNNNCP3MLYR-N6E
 K3KL8L80CM-MGCT
 H58G56BK8BX068
 H58G56CK8BX146
+H58G66CK8BX147

From 3ffb01e9cba9d0351b116fbf6ceb116dd6ac9644 Mon Sep 17 00:00:00 2001
From: Kilian Krause <kilian.krause@siemens.com>
Date: Thu, 23 Oct 2025 13:16:51 +0200
Subject: [PATCH 2349/3886] mb/siemens/mc_rpl1: Disable I2C1 and enable I2C6

Reconfigure I2C controller settings to disable I2C1 and enable I2C6
for the mc_rpl1 mainboard. This change reflects the updated hardware
configuration requirements.

Changes:
- Disable I2C controller 1
- Enable I2C controller 6

TEST=Build and boot tested on mc_rpl1 mainboard.
     Verified I2C6 functionality and confirmed I2C1 is disabled with
     `lspci -v | grep -A 5 "Serial bus controller"`. The output
     confirms that I2C6 (PCI 00:10.0) is enabled and I2C1 (PCI 00:15.1)
     is disabled because it is absent.

     ```
     00:10.0 Serial bus controller: Intel Corporation Alder Lake-P Serial IO I2C Controller #2 (rev 01)
        Subsystem: Intel Corporation Alder Lake-P Serial IO I2C Controller
        Flags: bus master, fast devsel, latency 0, IRQ 24, IOMMU group 4
        Memory at 80a12000 (64-bit, non-prefetchable) [size=4K]
        Capabilities: [80] Power Management version 3
        Capabilities: [90] Vendor Specific Information: Len=14 <?>
     ```

Change-Id: I4867062743ee10b34f94a1e588a10115b553a16e
Signed-off-by: Kilian Krause <kilian.krause@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89690
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Uwe Poeche <uwe.poeche@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/siemens/mc_rpl/variants/mc_rpl1/gpio.c       | 4 ++--
 .../siemens/mc_rpl/variants/mc_rpl1/overridetree.cb        | 7 ++++---
 2 files changed, 6 insertions(+), 5 deletions(-)

diff --git a/src/mainboard/siemens/mc_rpl/variants/mc_rpl1/gpio.c b/src/mainboard/siemens/mc_rpl/variants/mc_rpl1/gpio.c
index 8b10b57040..ca79d04251 100644
--- a/src/mainboard/siemens/mc_rpl/variants/mc_rpl1/gpio.c
+++ b/src/mainboard/siemens/mc_rpl/variants/mc_rpl1/gpio.c
@@ -30,8 +30,6 @@ static const struct pad_config gpio_table[] = {
 	PAD_CFG_GPI(GPP_H1, NONE, PLTRST),
 	PAD_CFG_GPI(GPP_H2, NONE, PLTRST),
 	PAD_CFG_NF(GPP_H3, NONE, DEEP, NF1),
-	PAD_CFG_NF(GPP_H6, NONE, DEEP, NF1),	/* I2C1_SDA */
-	PAD_CFG_NF(GPP_H7, NONE, DEEP, NF1),	/* I2C1_SCL */
 	PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2),	/* UART0_RXD */
 	PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2),	/* UART0_TXD */
 	PAD_CFG_NF(GPP_H19, NONE, DEEP, NF1),	/* PCIE_XCLKREQ4 */
@@ -44,6 +42,8 @@ static const struct pad_config gpio_table[] = {
 	PAD_CFG_NF(GPP_D8, NONE, DEEP, NF1),	/* PCIE_XCLKREQ3 */
 	PAD_CFG_GPI(GPP_D10, NONE, PLTRST),
 	PAD_CFG_GPI(GPP_D12, NONE, PLTRST),
+	PAD_CFG_NF(GPP_D13, NONE, DEEP, NF3),	/* I2C6_SDA */
+	PAD_CFG_NF(GPP_D14, NONE, DEEP, NF3),	/* I2C6_SCL */
 	PAD_CFG_NF(GPP_D17, NONE, DEEP, NF1),	/* UART1_RXD */
 	PAD_CFG_NF(GPP_D18, NONE, DEEP, NF1),	/* UART1_TXD */
 
diff --git a/src/mainboard/siemens/mc_rpl/variants/mc_rpl1/overridetree.cb b/src/mainboard/siemens/mc_rpl/variants/mc_rpl1/overridetree.cb
index c57481fb41..4c2350b779 100644
--- a/src/mainboard/siemens/mc_rpl/variants/mc_rpl1/overridetree.cb
+++ b/src/mainboard/siemens/mc_rpl/variants/mc_rpl1/overridetree.cb
@@ -42,11 +42,12 @@ chip soc/intel/alderlake
 
 	register "serial_io_i2c_mode" = "{
 		[PchSerialIoIndexI2C0] = PchSerialIoPci,
-		[PchSerialIoIndexI2C1] = PchSerialIoPci,
+		[PchSerialIoIndexI2C1] = PchSerialIoDisabled,
 		[PchSerialIoIndexI2C2] = PchSerialIoDisabled,
 		[PchSerialIoIndexI2C3] = PchSerialIoDisabled,
 		[PchSerialIoIndexI2C4] = PchSerialIoDisabled,
 		[PchSerialIoIndexI2C5] = PchSerialIoDisabled,
+		[PchSerialIoIndexI2C6] = PchSerialIoPci,
 	}"
 
 	register "serial_io_uart_mode" = "{
@@ -60,7 +61,7 @@ chip soc/intel/alderlake
 		.i2c[0] = {
 			.speed = I2C_SPEED_FAST,
 		},
-		.i2c[1] = {
+		.i2c[6] = {
 			.speed = I2C_SPEED_FAST,
 		},
 	}"
@@ -119,7 +120,7 @@ chip soc/intel/alderlake
 			}"
 		end
 		device ref i2c0 on end
-		device ref i2c1 on end
+		device ref i2c6 on end
 		device ref xhci on
 			chip drivers/usb/acpi
 				register "desc" = ""Root Hub""

From 3bbfbd37e14edeef66cc875080624554a5ed8448 Mon Sep 17 00:00:00 2001
From: Angel Pons <th3fanbus@gmail.com>
Date: Wed, 15 Oct 2025 16:52:32 +0200
Subject: [PATCH 2350/3886] nb/intel/haswell: Factor out
 `setup_sdram_meminfo()`

Move the `setup_sdram_meminfo()` function to shared raminit code
to deduplicate it as well as to allow native raminit to make use
of it, which will be done in a follow-up.

When consolidating the functions, the only functional difference
is that the Broadwell MRC.bin path reports memory frequencies in
MHz whereas the Haswell MRC.bin path reports them in MT/s. Since
this data is used to populate SMBIOS tables, which expect memory
frequencies in MT/s, using MT/s is the right choice.

Given that SPD data is handled differently in the three RAM init
implementations (Haswell MRC, Broadwell MRC, native raminit), we
have to abstract the SPD data pointers a bit. This is done using
an array of pointers.

While we're at it, add some TODO comments to note limitations of
the code. The idea is to fix those in follow-up commits.

Change-Id: I1f81bf18a9e856d80f8e4d7bda65089e999957f6
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89598
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 .../intel/haswell/broadwell_mrc/raminit.c     | 102 ++-------------
 .../intel/haswell/haswell_mrc/raminit.c       | 116 +++---------------
 src/northbridge/intel/haswell/raminit.h       |   4 +
 .../intel/haswell/raminit_shared.c            |  97 +++++++++++++++
 4 files changed, 131 insertions(+), 188 deletions(-)

diff --git a/src/northbridge/intel/haswell/broadwell_mrc/raminit.c b/src/northbridge/intel/haswell/broadwell_mrc/raminit.c
index 9114c26783..98cfdcf412 100644
--- a/src/northbridge/intel/haswell/broadwell_mrc/raminit.c
+++ b/src/northbridge/intel/haswell/broadwell_mrc/raminit.c
@@ -155,96 +155,6 @@ static void sdram_initialize(struct pei_data *pei_data)
 	report_memory_config();
 }
 
-static uint8_t nb_get_ecc_type(const uint32_t capid0_a)
-{
-	return capid0_a & CAPID_ECCDIS ? MEMORY_ARRAY_ECC_NONE : MEMORY_ARRAY_ECC_SINGLE_BIT;
-}
-
-static uint16_t nb_slots_per_channel(const uint32_t capid0_a)
-{
-	return !(capid0_a & CAPID_DDPCD) + 1;
-}
-
-static uint16_t nb_number_of_channels(const uint32_t capid0_a)
-{
-	return !(capid0_a & CAPID_PDCD) + 1;
-}
-
-static uint32_t nb_max_chan_capacity_mib(const uint32_t capid0_a)
-{
-	uint32_t ddrsz;
-
-	/* Values from documentation, which assume two DIMMs per channel */
-	switch (CAPID_DDRSZ(capid0_a)) {
-	case 1:
-		ddrsz = 8192;
-		break;
-	case 2:
-		ddrsz = 2048;
-		break;
-	case 3:
-		ddrsz = 512;
-		break;
-	default:
-		ddrsz = 16384;
-		break;
-	}
-
-	/* Account for the maximum number of DIMMs per channel */
-	return (ddrsz / 2) * nb_slots_per_channel(capid0_a);
-}
-
-static void setup_sdram_meminfo(struct pei_data *pei_data)
-{
-	unsigned int dimm_cnt = 0;
-
-	struct memory_info *mem_info = cbmem_add(CBMEM_ID_MEMINFO, sizeof(*mem_info));
-	if (!mem_info)
-		die("Failed to add memory info to CBMEM.\n");
-
-	memset(mem_info, 0, sizeof(struct memory_info));
-
-	const u32 ddr_frequency = (mchbar_read32(MC_BIOS_DATA) * 13333 * 2 + 50) / 100;
-
-	for (unsigned int ch = 0; ch < NUM_CHANNELS; ch++) {
-		const u32 ch_conf = mchbar_read32(MAD_DIMM(ch));
-		for (unsigned int slot = 0; slot < NUM_SLOTS; slot++) {
-			const u32 dimm_size = ((ch_conf >> (slot * 8)) & 0xff) * 256;
-			if (dimm_size) {
-				struct dimm_info *dimm = &mem_info->dimm[dimm_cnt];
-				dimm->dimm_size = dimm_size;
-				dimm->ddr_type = MEMORY_TYPE_DDR3;
-				dimm->ddr_frequency = ddr_frequency;
-				dimm->rank_per_dimm = 1 + ((ch_conf >> (17 + slot)) & 1);
-				dimm->channel_num = ch;
-				dimm->dimm_num = slot;
-				dimm->bank_locator = ch * 2;
-				memcpy(dimm->serial,
-					&pei_data->spd_data[ch][slot][SPD_DDR3_SERIAL_NUM],
-					SPD_DDR3_SERIAL_LEN);
-				memcpy(dimm->module_part_number,
-					&pei_data->spd_data[ch][slot][SPD_DDR3_PART_NUM],
-					SPD_DDR3_PART_LEN);
-				dimm->mod_id =
-					(pei_data->spd_data[ch][slot][SPD_DDR3_MOD_ID2] << 8) |
-					(pei_data->spd_data[ch][slot][SPD_DDR3_MOD_ID1] & 0xff);
-				dimm->mod_type = SPD_DDR3_DIMM_TYPE_SO_DIMM;
-				dimm->bus_width = MEMORY_BUS_WIDTH_64;
-				dimm_cnt++;
-			}
-		}
-	}
-	mem_info->dimm_cnt = dimm_cnt;
-
-	const uint32_t capid0_a = pci_read_config32(HOST_BRIDGE, CAPID0_A);
-
-	const uint16_t channels = nb_number_of_channels(capid0_a);
-
-	mem_info->ecc_type = nb_get_ecc_type(capid0_a);
-	mem_info->max_capacity_mib = channels * nb_max_chan_capacity_mib(capid0_a);
-	mem_info->number_of_devices = channels * nb_slots_per_channel(capid0_a);
-}
-
 #include <device/smbus_host.h>
 
 /* Copy SPD data for on-board memory */
@@ -433,5 +343,15 @@ void perform_raminit(const bool s3resume)
 	if (!s3resume)
 		save_mrc_data(&pei_data);
 
-	setup_sdram_meminfo(&pei_data);
+	const uint8_t *spd_data[NUM_CHANNELS][NUM_SLOTS] = {
+		[0] = {
+			[0] = pei_data.spd_data[0][0],
+			[1] = pei_data.spd_data[0][1],
+		},
+		[1] = {
+			[0] = pei_data.spd_data[1][0],
+			[1] = pei_data.spd_data[1][1],
+		},
+	};
+	setup_sdram_meminfo(spd_data);
 }
diff --git a/src/northbridge/intel/haswell/haswell_mrc/raminit.c b/src/northbridge/intel/haswell/haswell_mrc/raminit.c
index edd9b049d4..7db6a1397f 100644
--- a/src/northbridge/intel/haswell/haswell_mrc/raminit.c
+++ b/src/northbridge/intel/haswell/haswell_mrc/raminit.c
@@ -4,7 +4,6 @@
 #include <console/console.h>
 #include <console/usb.h>
 #include <string.h>
-#include <cbmem.h>
 #include <cbfs.h>
 #include <cf9_reset.h>
 #include <memory_info.h>
@@ -183,101 +182,6 @@ static void sdram_initialize(struct pei_data *pei_data)
 	report_memory_config();
 }
 
-static uint8_t nb_get_ecc_type(const uint32_t capid0_a)
-{
-	return capid0_a & CAPID_ECCDIS ? MEMORY_ARRAY_ECC_NONE : MEMORY_ARRAY_ECC_SINGLE_BIT;
-}
-
-static uint16_t nb_slots_per_channel(const uint32_t capid0_a)
-{
-	return !(capid0_a & CAPID_DDPCD) + 1;
-}
-
-static uint16_t nb_number_of_channels(const uint32_t capid0_a)
-{
-	return !(capid0_a & CAPID_PDCD) + 1;
-}
-
-static uint32_t nb_max_chan_capacity_mib(const uint32_t capid0_a)
-{
-	uint32_t ddrsz;
-
-	/* Values from documentation, which assume two DIMMs per channel */
-	switch (CAPID_DDRSZ(capid0_a)) {
-	case 1:
-		ddrsz = 8192;
-		break;
-	case 2:
-		ddrsz = 2048;
-		break;
-	case 3:
-		ddrsz = 512;
-		break;
-	default:
-		ddrsz = 16384;
-		break;
-	}
-
-	/* Account for the maximum number of DIMMs per channel */
-	return (ddrsz / 2) * nb_slots_per_channel(capid0_a);
-}
-
-static void setup_sdram_meminfo(struct pei_data *pei_data)
-{
-	struct memory_info *mem_info;
-	struct dimm_info *dimm;
-	int ch, d_num;
-	int dimm_cnt = 0;
-
-	mem_info = cbmem_add(CBMEM_ID_MEMINFO, sizeof(struct memory_info));
-	if (!mem_info)
-		die("Failed to add memory info to CBMEM.\n");
-
-	memset(mem_info, 0, sizeof(struct memory_info));
-
-	const u32 ddr_freq_mhz = (mchbar_read32(MC_BIOS_DATA) * 13333 * 2 + 50) / 100;
-
-	for (ch = 0; ch < NUM_CHANNELS; ch++) {
-		const u32 ch_conf = mchbar_read32(MAD_DIMM(ch));
-		/* DIMMs A/B */
-		for (d_num = 0; d_num < NUM_SLOTS; d_num++) {
-			const u32 dimm_size = ((ch_conf >> (d_num * 8)) & 0xff) * 256;
-			if (dimm_size) {
-				const int index = ch * NUM_SLOTS + d_num;
-				dimm = &mem_info->dimm[dimm_cnt];
-				dimm->dimm_size = dimm_size;
-				dimm->ddr_type = MEMORY_TYPE_DDR3;
-				dimm->ddr_frequency = ddr_freq_mhz * 2; /* In MT/s */
-				dimm->rank_per_dimm = 1 + ((ch_conf >> (17 + d_num)) & 1);
-				dimm->channel_num = ch;
-				dimm->dimm_num = d_num;
-				dimm->bank_locator = ch * 2;
-				memcpy(dimm->serial,
-					&pei_data->spd_data[index][SPD_DDR3_SERIAL_NUM],
-					SPD_DDR3_SERIAL_LEN);
-				memcpy(dimm->module_part_number,
-					&pei_data->spd_data[index][SPD_DDR3_PART_NUM],
-					SPD_DDR3_PART_LEN);
-				dimm->mod_id =
-					(pei_data->spd_data[index][SPD_DDR3_MOD_ID2] << 8) |
-					(pei_data->spd_data[index][SPD_DDR3_MOD_ID1] & 0xff);
-				dimm->mod_type = SPD_DDR3_DIMM_TYPE_SO_DIMM;
-				dimm->bus_width = MEMORY_BUS_WIDTH_64;
-				dimm_cnt++;
-			}
-		}
-	}
-	mem_info->dimm_cnt = dimm_cnt;
-
-	const uint32_t capid0_a = pci_read_config32(HOST_BRIDGE, CAPID0_A);
-
-	const uint16_t channels = nb_number_of_channels(capid0_a);
-
-	mem_info->ecc_type = nb_get_ecc_type(capid0_a);
-	mem_info->max_capacity_mib = channels * nb_max_chan_capacity_mib(capid0_a);
-	mem_info->number_of_devices = channels * nb_slots_per_channel(capid0_a);
-}
-
 /* Copy SPD data for on-board memory */
 static void copy_spd(struct pei_data *pei_data, struct spd_info *spdi)
 {
@@ -428,5 +332,23 @@ void perform_raminit(const bool s3resume)
 	if (!s3resume)
 		save_mrc_data(&pei_data);
 
-	setup_sdram_meminfo(&pei_data);
+	/*
+	 * TODO: `setup_sdram_info()` uses SPD data to fill in various fields. However,
+	 * even though Haswell MRC reads SPD data over SMBus, it does not pass the data
+	 * back to coreboot. So, we currently only have SPD data for memory-down slots.
+	 *
+	 * We have to read the SPD data over SMBus again for coreboot to use it. But we
+	 * can be smart and only read the bytes that `setup_sdram_meminfo()` needs.
+	 */
+	const uint8_t *spd_data[NUM_CHANNELS][NUM_SLOTS] = {
+		[0] = {
+			[0] = pei_data.spd_data[0],
+			[1] = pei_data.spd_data[1],
+		},
+		[1] = {
+			[0] = pei_data.spd_data[2],
+			[1] = pei_data.spd_data[3],
+		},
+	};
+	setup_sdram_meminfo(spd_data);
 }
diff --git a/src/northbridge/intel/haswell/raminit.h b/src/northbridge/intel/haswell/raminit.h
index 3f13a03db5..2b80c24aba 100644
--- a/src/northbridge/intel/haswell/raminit.h
+++ b/src/northbridge/intel/haswell/raminit.h
@@ -4,7 +4,9 @@
 #define NORTHBRIDGE_INTEL_HASWELL_RAMINIT_H
 
 #include <types.h>
+
 #include "chip.h"
+#include "haswell.h"
 
 #define SPD_MEMORY_DOWN	0xff
 
@@ -17,6 +19,8 @@ struct spd_info {
 void mb_get_spd_map(struct spd_info *spdi);
 
 void get_spd_info(struct spd_info *spdi, const struct northbridge_intel_haswell_config *cfg);
+void setup_sdram_meminfo(const uint8_t *spd_data[NUM_CHANNELS][NUM_SLOTS]);
+
 void perform_raminit(const bool s3resume);
 
 #endif	/* NORTHBRIDGE_INTEL_HASWELL_RAMINIT_H */
diff --git a/src/northbridge/intel/haswell/raminit_shared.c b/src/northbridge/intel/haswell/raminit_shared.c
index 90fe1145cc..7a87359b63 100644
--- a/src/northbridge/intel/haswell/raminit_shared.c
+++ b/src/northbridge/intel/haswell/raminit_shared.c
@@ -1,7 +1,13 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
+#include <cbmem.h>
+#include <device/dram/ddr3.h>
+#include <device/pci_ops.h>
 #include <string.h>
+#include <types.h>
+
 #include "chip.h"
+#include "haswell.h"
 #include "raminit.h"
 
 void get_spd_info(struct spd_info *spdi, const struct northbridge_intel_haswell_config *cfg)
@@ -14,3 +20,94 @@ void get_spd_info(struct spd_info *spdi, const struct northbridge_intel_haswell_
 		memcpy(spdi->addresses, cfg->spd_addresses, ARRAY_SIZE(spdi->addresses));
 	}
 }
+
+static uint8_t nb_get_ecc_type(const uint32_t capid0_a)
+{
+	return capid0_a & CAPID_ECCDIS ? MEMORY_ARRAY_ECC_NONE : MEMORY_ARRAY_ECC_SINGLE_BIT;
+}
+
+static uint16_t nb_slots_per_channel(const uint32_t capid0_a)
+{
+	return !(capid0_a & CAPID_DDPCD) + 1;
+}
+
+static uint16_t nb_number_of_channels(const uint32_t capid0_a)
+{
+	return !(capid0_a & CAPID_PDCD) + 1;
+}
+
+static uint32_t nb_max_chan_capacity_mib(const uint32_t capid0_a)
+{
+	uint32_t ddrsz;
+
+	/* Values from documentation, which assume two DIMMs per channel */
+	switch (CAPID_DDRSZ(capid0_a)) {
+	case 1:
+		ddrsz = 8192;
+		break;
+	case 2:
+		ddrsz = 2048;
+		break;
+	case 3:
+		ddrsz = 512;
+		break;
+	default:
+		ddrsz = 16384;
+		break;
+	}
+
+	/* Account for the maximum number of DIMMs per channel */
+	return (ddrsz / 2) * nb_slots_per_channel(capid0_a);
+}
+
+void setup_sdram_meminfo(const uint8_t *spd_data[NUM_CHANNELS][NUM_SLOTS])
+{
+	struct memory_info *mem_info = cbmem_add(CBMEM_ID_MEMINFO, sizeof(*mem_info));
+	if (!mem_info)
+		die("Failed to add memory info to CBMEM.\n");
+
+	memset(mem_info, 0, sizeof(struct memory_info));
+
+	/* TODO: This looks like an open-coded DIV_ROUND_CLOSEST() */
+	const uint32_t ddr_freq_mhz = (mchbar_read32(MC_BIOS_DATA) * 13333 * 2 + 50) / 100;
+
+	unsigned int dimm_cnt = 0;
+	for (unsigned int channel = 0; channel < NUM_CHANNELS; channel++) {
+		const uint32_t ch_conf = mchbar_read32(MAD_DIMM(channel));
+		for (unsigned int slot = 0; slot < NUM_SLOTS; slot++) {
+			const uint32_t dimm_size = ((ch_conf >> (slot * 8)) & 0xff) * 256;
+			if (dimm_size) {
+				struct dimm_info *dimm = &mem_info->dimm[dimm_cnt];
+				dimm->dimm_size = dimm_size;
+				/* TODO: Hardcoded, could also be LPDDR3 */
+				dimm->ddr_type = MEMORY_TYPE_DDR3;
+				dimm->ddr_frequency = ddr_freq_mhz * 2; /* In MT/s */
+				dimm->rank_per_dimm = 1 + ((ch_conf >> (17 + slot)) & 1);
+				dimm->channel_num = channel;
+				dimm->dimm_num = slot;
+				dimm->bank_locator = channel * 2;
+				memcpy(dimm->serial,
+					&spd_data[channel][slot][SPD_DDR3_SERIAL_NUM],
+					SPD_DDR3_SERIAL_LEN);
+				memcpy(dimm->module_part_number,
+					&spd_data[channel][slot][SPD_DDR3_PART_NUM],
+					SPD_DDR3_PART_LEN);
+				dimm->mod_id =
+					(spd_data[channel][slot][SPD_DDR3_MOD_ID2] << 8) |
+					(spd_data[channel][slot][SPD_DDR3_MOD_ID1] & 0xff);
+				/* TODO: Should be taken from SPD instead */
+				dimm->mod_type = SPD_DDR3_DIMM_TYPE_SO_DIMM;
+				dimm->bus_width = MEMORY_BUS_WIDTH_64;
+				dimm_cnt++;
+			}
+		}
+	}
+	mem_info->dimm_cnt = dimm_cnt;
+
+	const uint32_t capid0_a = pci_read_config32(HOST_BRIDGE, CAPID0_A);
+	const uint16_t num_channels = nb_number_of_channels(capid0_a);
+
+	mem_info->ecc_type = nb_get_ecc_type(capid0_a);
+	mem_info->max_capacity_mib = num_channels * nb_max_chan_capacity_mib(capid0_a);
+	mem_info->number_of_devices = num_channels * nb_slots_per_channel(capid0_a);
+}

From 1730d05ec3ede0e878029cef82049d1d073db543 Mon Sep 17 00:00:00 2001
From: Angel Pons <th3fanbus@gmail.com>
Date: Wed, 15 Oct 2025 17:10:30 +0200
Subject: [PATCH 2351/3886] nb/intel/haswell: Factor out
 `report_memory_config()`

Move the `report_memory_config()` function to shared raminit code, both
to deduplicate the code and to allow native raminit to make use of it.

Change-Id: I8b3c695c0a266634a42b0303e4f1ea699301c26b
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89599
Reviewed-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 .../intel/haswell/broadwell_mrc/raminit.c     | 50 -------------------
 .../intel/haswell/haswell_mrc/raminit.c       | 47 -----------------
 src/northbridge/intel/haswell/raminit.h       |  1 +
 .../intel/haswell/raminit_shared.c            | 45 +++++++++++++++++
 4 files changed, 46 insertions(+), 97 deletions(-)

diff --git a/src/northbridge/intel/haswell/broadwell_mrc/raminit.c b/src/northbridge/intel/haswell/broadwell_mrc/raminit.c
index 98cfdcf412..8c0f5422df 100644
--- a/src/northbridge/intel/haswell/broadwell_mrc/raminit.c
+++ b/src/northbridge/intel/haswell/broadwell_mrc/raminit.c
@@ -40,56 +40,6 @@ static void save_mrc_data(struct pei_data *pei_data)
 					pei_data->data_to_save_size);
 }
 
-static const char *const ecc_decoder[] = {
-	"inactive",
-	"active on IO",
-	"disabled on IO",
-	"active",
-};
-
-/*
- * Dump in the log memory controller configuration as read from the memory
- * controller registers.
- */
-static void report_memory_config(void)
-{
-	int i;
-
-	const u32 addr_decoder_common = mchbar_read32(MAD_CHNL);
-
-	printk(BIOS_DEBUG, "memcfg DDR3 clock %d MHz\n",
-	       (mchbar_read32(MC_BIOS_DATA) * 13333 * 2 + 50) / 100);
-
-	printk(BIOS_DEBUG, "memcfg channel assignment: A: %d, B % d, C % d\n",
-	       (addr_decoder_common >> 0) & 3,
-	       (addr_decoder_common >> 2) & 3,
-	       (addr_decoder_common >> 4) & 3);
-
-	for (i = 0; i < NUM_CHANNELS; i++) {
-		const u32 ch_conf = mchbar_read32(MAD_DIMM(i));
-
-		printk(BIOS_DEBUG, "memcfg channel[%d] config (%8.8x):\n", i, ch_conf);
-		printk(BIOS_DEBUG, "   ECC %s\n", ecc_decoder[(ch_conf >> 24) & 3]);
-		printk(BIOS_DEBUG, "   enhanced interleave mode %s\n",
-		       ((ch_conf >> 22) & 1) ? "on" : "off");
-
-		printk(BIOS_DEBUG, "   rank interleave %s\n",
-		       ((ch_conf >> 21) & 1) ? "on" : "off");
-
-		printk(BIOS_DEBUG, "   DIMMA %d MB width %s %s rank%s\n",
-		       ((ch_conf >> 0) & 0xff) * 256,
-		       ((ch_conf >> 19) & 1) ? "x16" : "x8 or x32",
-		       ((ch_conf >> 17) & 1) ? "dual" : "single",
-		       ((ch_conf >> 16) & 1) ? "" : ", selected");
-
-		printk(BIOS_DEBUG, "   DIMMB %d MB width %s %s rank%s\n",
-		       ((ch_conf >> 8) & 0xff) * 256,
-		       ((ch_conf >> 20) & 1) ? "x16" : "x8 or x32",
-		       ((ch_conf >> 18) & 1) ? "dual" : "single",
-		       ((ch_conf >> 16) & 1) ? ", selected" : "");
-	}
-}
-
 typedef int ABI_X86(*pei_wrapper_entry_t)(struct pei_data *pei_data);
 
 static void ABI_X86 send_to_console(unsigned char b)
diff --git a/src/northbridge/intel/haswell/haswell_mrc/raminit.c b/src/northbridge/intel/haswell/haswell_mrc/raminit.c
index 7db6a1397f..d7439ca7b1 100644
--- a/src/northbridge/intel/haswell/haswell_mrc/raminit.c
+++ b/src/northbridge/intel/haswell/haswell_mrc/raminit.c
@@ -58,53 +58,6 @@ static void prepare_mrc_cache(struct pei_data *pei_data)
 	       pei_data->mrc_input, mrc_size);
 }
 
-static const char *const ecc_decoder[] = {
-	"inactive",
-	"active on IO",
-	"disabled on IO",
-	"active",
-};
-
-/* Print out the memory controller configuration, as per the values in its registers. */
-static void report_memory_config(void)
-{
-	int i;
-
-	const u32 addr_decoder_common = mchbar_read32(MAD_CHNL);
-
-	printk(BIOS_DEBUG, "memcfg DDR3 clock %d MHz\n",
-	       DIV_ROUND_CLOSEST(mchbar_read32(MC_BIOS_DATA) * 13333 * 2, 100));
-
-	printk(BIOS_DEBUG, "memcfg channel assignment: A: %d, B % d, C % d\n",
-	       (addr_decoder_common >> 0) & 3,
-	       (addr_decoder_common >> 2) & 3,
-	       (addr_decoder_common >> 4) & 3);
-
-	for (i = 0; i < NUM_CHANNELS; i++) {
-		const u32 ch_conf = mchbar_read32(MAD_DIMM(i));
-
-		printk(BIOS_DEBUG, "memcfg channel[%d] config (%8.8x):\n", i, ch_conf);
-		printk(BIOS_DEBUG, "   ECC %s\n", ecc_decoder[(ch_conf >> 24) & 3]);
-		printk(BIOS_DEBUG, "   enhanced interleave mode %s\n",
-		       ((ch_conf >> 22) & 1) ? "on" : "off");
-
-		printk(BIOS_DEBUG, "   rank interleave %s\n",
-		       ((ch_conf >> 21) & 1) ? "on" : "off");
-
-		printk(BIOS_DEBUG, "   DIMMA %d MB width %s %s rank%s\n",
-		       ((ch_conf >> 0) & 0xff) * 256,
-		       ((ch_conf >> 19) & 1) ? "x16" : "x8 or x32",
-		       ((ch_conf >> 17) & 1) ? "dual" : "single",
-		       ((ch_conf >> 16) & 1) ? "" : ", selected");
-
-		printk(BIOS_DEBUG, "   DIMMB %d MB width %s %s rank%s\n",
-		       ((ch_conf >> 8) & 0xff) * 256,
-		       ((ch_conf >> 20) & 1) ? "x16" : "x8 or x32",
-		       ((ch_conf >> 18) & 1) ? "dual" : "single",
-		       ((ch_conf >> 16) & 1) ? ", selected" : "");
-	}
-}
-
 /**
  * Find PEI executable in coreboot filesystem and execute it.
  *
diff --git a/src/northbridge/intel/haswell/raminit.h b/src/northbridge/intel/haswell/raminit.h
index 2b80c24aba..e1b67e71d7 100644
--- a/src/northbridge/intel/haswell/raminit.h
+++ b/src/northbridge/intel/haswell/raminit.h
@@ -19,6 +19,7 @@ struct spd_info {
 void mb_get_spd_map(struct spd_info *spdi);
 
 void get_spd_info(struct spd_info *spdi, const struct northbridge_intel_haswell_config *cfg);
+void report_memory_config(void);
 void setup_sdram_meminfo(const uint8_t *spd_data[NUM_CHANNELS][NUM_SLOTS]);
 
 void perform_raminit(const bool s3resume);
diff --git a/src/northbridge/intel/haswell/raminit_shared.c b/src/northbridge/intel/haswell/raminit_shared.c
index 7a87359b63..6fcb0ec98a 100644
--- a/src/northbridge/intel/haswell/raminit_shared.c
+++ b/src/northbridge/intel/haswell/raminit_shared.c
@@ -21,6 +21,51 @@ void get_spd_info(struct spd_info *spdi, const struct northbridge_intel_haswell_
 	}
 }
 
+static const char *const ecc_decoder[] = {
+	"inactive",
+	"active on IO",
+	"disabled on IO",
+	"active",
+};
+
+/* Print out the memory controller configuration, as per the values in its registers. */
+void report_memory_config(void)
+{
+	const uint32_t addr_decoder_common = mchbar_read32(MAD_CHNL);
+
+	printk(BIOS_DEBUG, "memcfg DDR3 clock %d MHz\n",
+	       DIV_ROUND_CLOSEST(mchbar_read32(MC_BIOS_DATA) * 13333 * 2, 100));
+
+	printk(BIOS_DEBUG, "memcfg channel assignment: A: %d, B % d, C % d\n",
+	       (addr_decoder_common >> 0) & 3,
+	       (addr_decoder_common >> 2) & 3,
+	       (addr_decoder_common >> 4) & 3);
+
+	for (unsigned int i = 0; i < NUM_CHANNELS; i++) {
+		const uint32_t ch_conf = mchbar_read32(MAD_DIMM(i));
+
+		printk(BIOS_DEBUG, "memcfg channel[%d] config (%8.8x):\n", i, ch_conf);
+		printk(BIOS_DEBUG, "   ECC %s\n", ecc_decoder[(ch_conf >> 24) & 3]);
+		printk(BIOS_DEBUG, "   enhanced interleave mode %s\n",
+		       ((ch_conf >> 22) & 1) ? "on" : "off");
+
+		printk(BIOS_DEBUG, "   rank interleave %s\n",
+		       ((ch_conf >> 21) & 1) ? "on" : "off");
+
+		printk(BIOS_DEBUG, "   DIMMA %d MB width %s %s rank%s\n",
+		       ((ch_conf >> 0) & 0xff) * 256,
+		       ((ch_conf >> 19) & 1) ? "x16" : "x8 or x32",
+		       ((ch_conf >> 17) & 1) ? "dual" : "single",
+		       ((ch_conf >> 16) & 1) ? "" : ", selected");
+
+		printk(BIOS_DEBUG, "   DIMMB %d MB width %s %s rank%s\n",
+		       ((ch_conf >> 8) & 0xff) * 256,
+		       ((ch_conf >> 20) & 1) ? "x16" : "x8 or x32",
+		       ((ch_conf >> 18) & 1) ? "dual" : "single",
+		       ((ch_conf >> 16) & 1) ? ", selected" : "");
+	}
+}
+
 static uint8_t nb_get_ecc_type(const uint32_t capid0_a)
 {
 	return capid0_a & CAPID_ECCDIS ? MEMORY_ARRAY_ECC_NONE : MEMORY_ARRAY_ECC_SINGLE_BIT;

From 70e79f43b17b0646ac71d0ff28bc8a6a932bd2d2 Mon Sep 17 00:00:00 2001
From: Angel Pons <th3fanbus@gmail.com>
Date: Wed, 15 Oct 2025 17:47:50 +0200
Subject: [PATCH 2352/3886] Haswell NRI: Print and fill in memory-related info

Call the `report_memory_config()` and `setup_sdram_meminfo()` functions,
which were factored out into shared raminit code in previous patches. As
the SPD data is not readily available where `setup_sdram_meminfo()` gets
called, add a function to get it from the saved data, as it is available
in a global context. Technically speaking, the "mighty ctrl" variable is
also static (thus global), but it is only meant to be used within native
raminit code and is only static to avoid nuking the stack (it is huge).

Change-Id: Ia2c0946f55748e38bb5ccb5cb06721aeb77527e7
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89600
Reviewed-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 .../intel/haswell/native_raminit/raminit_native.c    | 12 ++++++++++--
 .../intel/haswell/native_raminit/raminit_native.h    |  1 +
 .../intel/haswell/native_raminit/save_restore.c      | 10 ++++++++++
 3 files changed, 21 insertions(+), 2 deletions(-)

diff --git a/src/northbridge/intel/haswell/native_raminit/raminit_native.c b/src/northbridge/intel/haswell/native_raminit/raminit_native.c
index 4ac220cb22..d5b5c117d6 100644
--- a/src/northbridge/intel/haswell/native_raminit/raminit_native.c
+++ b/src/northbridge/intel/haswell/native_raminit/raminit_native.c
@@ -179,7 +179,7 @@ void perform_raminit(const bool s3resume)
 	const enum raminit_boot_mode bootmode =
 			do_actual_raminit(s3resume, cpu_replaced, orig_bootmode);
 
-	/** TODO: report_memory_config **/
+	report_memory_config();
 
 	if (intel_early_me_uma_size() > 0) {
 		/*
@@ -208,5 +208,13 @@ void perform_raminit(const bool s3resume)
 	if (!s3resume)
 		save_mrc_data();
 
-	/** TODO: setup_sdram_meminfo **/
+	/*
+	 * To avoid passing pointers around too much, get the SPD data
+	 * from the saved data. It will always be present: a cold boot
+	 * populates saved data from training results, and a fast boot
+	 * or a S3 resume reads the saved data from the MRC cache.
+	 */
+	const uint8_t *spd_data[NUM_CHANNELS][NUM_SLOTS] = { 0 };
+	reg_frame_get_spd_data(spd_data);
+	setup_sdram_meminfo(spd_data);
 }
diff --git a/src/northbridge/intel/haswell/native_raminit/raminit_native.h b/src/northbridge/intel/haswell/native_raminit/raminit_native.h
index b9e84a11df..53dbe4df28 100644
--- a/src/northbridge/intel/haswell/native_raminit/raminit_native.h
+++ b/src/northbridge/intel/haswell/native_raminit/raminit_native.h
@@ -504,6 +504,7 @@ void configure_refresh(struct sysinfo *ctrl);
 struct register_save_frame *reg_frame_ptr(void);
 size_t reg_frame_size(void);
 uint32_t reg_frame_rev(void);
+void reg_frame_get_spd_data(const uint8_t *out_spd_data[NUM_CHANNELS][NUM_SLOTS]);
 
 uint32_t get_tCKE(uint32_t mem_clock_mhz, bool lpddr);
 uint32_t get_tXPDLL(uint32_t mem_clock_mhz);
diff --git a/src/northbridge/intel/haswell/native_raminit/save_restore.c b/src/northbridge/intel/haswell/native_raminit/save_restore.c
index f1f50e3ff8..5be68808d8 100644
--- a/src/northbridge/intel/haswell/native_raminit/save_restore.c
+++ b/src/northbridge/intel/haswell/native_raminit/save_restore.c
@@ -179,6 +179,16 @@ size_t reg_frame_size(void)
 	return sizeof(struct register_save_frame);
 }
 
+void reg_frame_get_spd_data(const uint8_t *out_spd_data[NUM_CHANNELS][NUM_SLOTS])
+{
+	const struct save_params *params = &reg_frame_ptr()->params;
+	for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
+		for (uint8_t slot = 0; slot < NUM_SLOTS; slot++) {
+			out_spd_data[channel][slot] = params->dimms[channel][slot].raw_spd;
+		}
+	}
+}
+
 typedef void (*reg_func_t)(const uint16_t offset, uint32_t *const value);
 
 static void save_value(const uint16_t offset, uint32_t *const value)

From b42f74122c1d0e451a45f8e0b0cbc9740c25f7d0 Mon Sep 17 00:00:00 2001
From: "Johann C. Rode" <jcrode@gmx.net>
Date: Sun, 26 Oct 2025 11:21:38 -0700
Subject: [PATCH 2353/3886] Documentation/mb/lenovo: Adjust docs for Thinkpad
 T470s/T580

The documentation has been adjusted to include additional variants,
and brushed up a bit for clarity.

Change-Id: Ia7711d5105e568113de219b1aa43e3a5d50aaf9c
Signed-off-by: Johann C. Rode <jcrode@gmx.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89750
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nicholas <nic.c3.14@gmail.com>
---
 Documentation/mainboard/index.md              |  2 +-
 .../mainboard/lenovo/{t480.md => skylake.md}  | 70 +++++++++++--------
 2 files changed, 42 insertions(+), 30 deletions(-)
 rename Documentation/mainboard/lenovo/{t480.md => skylake.md} (71%)

diff --git a/Documentation/mainboard/index.md b/Documentation/mainboard/index.md
index d4fbddace5..1b2697c9c0 100644
--- a/Documentation/mainboard/index.md
+++ b/Documentation/mainboard/index.md
@@ -248,7 +248,7 @@ T440p <lenovo/t440p.md>
 ```{toctree}
 :maxdepth: 1
 
-T480/T480s <lenovo/t480.md>
+T470s/T480/T480s/T580 <lenovo/skylake.md>
 ```
 ## Libretrend
 
diff --git a/Documentation/mainboard/lenovo/t480.md b/Documentation/mainboard/lenovo/skylake.md
similarity index 71%
rename from Documentation/mainboard/lenovo/t480.md
rename to Documentation/mainboard/lenovo/skylake.md
index 9ebce8ff7d..18e741daa0 100644
--- a/Documentation/mainboard/lenovo/t480.md
+++ b/Documentation/mainboard/lenovo/skylake.md
@@ -1,6 +1,7 @@
-# Lenovo ThinkPad T480/T480s
+# Lenovo ThinkPad T470s/T480/T480s/T580
 
-This page describes how to run coreboot on the [Lenovo ThinkPad T480/T480s].
+This page describes how to run coreboot on the Lenovo [Thinkpad T470s], [ThinkPad T480],
+[Thinkpad T480s], and [Thinkpad T580].
 
 ## Important Notes
 
@@ -12,11 +13,13 @@ feature, you need to downgrade the vendor firmware to a version with a compatibl
 
 The mapping can be seen here [on Lenovo's site].
 
-### Bootguard
-The T480/T480s both have Intel Bootguard enabled, which prevents the device from running
-firmware which is not cryptographically signed using the manufacturer's key.
+### Boot Guard
+Most Thinkpads newer than the xx30 models except machines with swappable CPUs (T440p, W541) and
+some models in the E series (E460, E470) have Intel Boot Guard enabled. This prevents these
+laptops from running custom firmware which is not cryptographically signed with the manufacturer's
+key.
 
-The [deguard utility](../../soc/intel/deguard) will need to be used in order to bypass Bootguard
+The [deguard utility](../../soc/intel/deguard) will need to be used in order to bypass Boot Guard
 on these devices.
 
 ### Thunderbolt
@@ -46,12 +49,12 @@ Follow the coreboot [tutorial](../../tutorial/part1) to:
 * clone the coreboot repo
 * build the coreboot toolchain
 
-You will also need to clone the [deguard](https://review.coreboot.org/deguard) repository, in
-order to bypass BootGuard.
+You will also need to clone the [deguard](https://review.coreboot.org/deguard) repository in
+order to bypass Boot Guard.
 
 ## Required proprietary blobs
 
-When flashing the T480/T480s for the first time, the following blobs are required for a full
+When flashing the laptop for the first time, the following blobs are required for a full
 flash image:
  * Flash Descriptor (IFD)
  * Management Engine (ME)
@@ -59,31 +62,32 @@ flash image:
 
 These will either be extracted from the vendor firmware on the device or downloaded as needed.
 
-Additionally, the T480/T480s make use of Intel's Firmware Support Package (FSP) for memory and
-silicon init. FSP is provided by default as part of the coreboot build, no user intervention is
-required.
+Additionally, all Skylake/Kabylake machines require Intel's Firmware Support Package (FSP) for
+hardware initialization. FSP is provided by default as part of the coreboot build, no user
+intervention is required.
 
 ## Reading the vendor firmware
 
-The T480/T480s have a single flash chip, a 16 MiB W25Q128 in a SOIC-8 package. The flash chip
-uses the following layout:
+The Skylake Thinkpads have a single BIOS flash chip (16 MiB serial flash in a SOIC-8 package).
+The flash chip uses the following layout:
 
     00000000:00000fff flash descriptor (fd)
-    00fff000:00000fff platform data (unused)
     00001000:00002fff gbe
     00003000:006fffff me
     00700000:00ffffff bios
 
-
 To read the vendor firmware, disconnect external power and remove the back of the laptop
-according to the T480 [Hardware Maintenance Manual].
-Disconnect/remove the battery (and CMOS battery if equipped). Attach a chip clip to the flash.
-Use an external programmer (ch341a, raspberry Pi, etc) and flashrom to read the chip.
+as described in the [hardware maintenance manual](thinkpad_hmm).
+Disconnect/remove all batteries (and CMOS battery if equipped). Attach a chip clip to the flash.
+Use an external SPI programmer (ch341a, raspberry Pi, etc) to read the chip `bios.bin`.
 
 ## Preparing the binaries
 
 The IFD and GBE need to be extracted from the vendor firmware backup read from the flash chip.
 See [Extract IFD binaries](../../util/ifdtool/binary_extraction).
+
+    ifdtool -x -p sklkbl bios.bin
+
 Rename the extracted files to `ifd.bin` and `gbe.bin` and move them to the `binaries` folder
 you created per the instructions.
 
@@ -91,8 +95,9 @@ you created per the instructions.
 
 Please review the documentation on the use of the [deguard utility](../../soc/intel/deguard).
 
-Since the T480/T480s is already a supported target, we simply need to download/extract the donor
-image, then generate the "deguarded" ME firmware image
+All Skylake/Kabylake Thinkpads supported by coreboot are also supported in deguard. Hence, we
+simply need to download/extract the donor image, then generate the "deguarded" ME firmware
+image.
 
 The donor ME binary required for use with the deguard utility can be downloaded as part of the
 [Dell firmware updater]. After downloading, use [Dell_PFS_Extract.py] to extract the required ME
@@ -101,9 +106,9 @@ firmware image from the updater:
     python Dell_PFS_Extract.py Inspiron_5468_1.3.0.exe
 
 The resulting binary should be renamed `me_donor.bin` and moved to the `binaries` folder with
-the IFD and GBE.
+the IFD and GBE binaries.
 
-Then, generate the deguarded ME firmware image:
+Then, generate the deguarded ME firmware image adjusting the `--delta` argument accordingly:
 
     ./finalimage.py --delta data/delta/thinkpad_t480 --version 11.6.0.1126 --pch LP --sku 2M --fake-fpfs data/fpfs/zero --input ../coreboot/binaries/me_donor.bin --output ../coreboot/binaries/me_deguarded.bin
 
@@ -112,6 +117,10 @@ deguard and coreboot repos are checked out under the same parent directory, and
 donor firmware is in the `binaries` subdirectory of coreboot (along with the IFD/GBE binaries).
 Adjust the paths as necessary if that is not the case.
 
+Please be careful with [me_cleaner](../../northbridge/intel/sandybridge/me_cleaner). While
+me_cleaner is generally expected to work, truncating the ME binary can have unintended side
+effects like disabling PCIe devices on Thinkpad T470s (NVMe, WLAN, WWAN, etc.).
+
 ### Preparing the IFD
 
 In order to use the modified ME firmware binary generated by deguard above, we need to set the
@@ -124,16 +133,17 @@ the HAP-enabled one to `ifd.bin`
 
 ## Building coreboot
 
-You can use `make menuconfig` or `make nconfig` to select the mainboard (Lenovo T480 or T480s),
+You can use `make menuconfig` or `make nconfig` to select the mainboard matching your machine,
 enable the inclusion of the IFD/ME/GBE binaries, and select your payload and options.
-You can also just use the following defconfig:
+For example, you can also just use the following defconfig for a Thinkpad T480 with EDK2/UEFI
+as a payload:
 
     CONFIG_VENDOR_LENOVO=y
+    CONFIG_BOARD_LENOVO_T480=y
     CONFIG_IFD_BIN_PATH="binaries/ifd.bin"
     CONFIG_ME_BIN_PATH="binaries/me_deguarded.bin"
     CONFIG_GBE_BIN_PATH="binaries/gbe.bin"
     CONFIG_HAVE_IFD_BIN=y
-    CONFIG_BOARD_LENOVO_T480=y
     CONFIG_HAVE_ME_BIN=y
     CONFIG_HAVE_GBE_BIN=y
     CONFIG_PAYLOAD_EDK2=y
@@ -190,10 +200,12 @@ binaries if only flashing the `bios` region.
 - Virtualization: VT-x and VT-d
 - Internal flashing (after initial flash with unlocked IFD)
 
-[Lenovo ThinkPad T480/T480s]: https://pcsupport.lenovo.com/us/en/products/laptops-and-netbooks/thinkpad-t-series-laptops/thinkpad-t480-type-20l5-20l6/
-[Hardware Maintenance Manual]: https://download.lenovo.com/pccbbs/mobiles_pdf/t480_hmm_en.pdf
+[Thinkpad T470s]: https://pcsupport.lenovo.com/us/en/products/laptops-and-netbooks/thinkpad-t-series-laptops/thinkpad-t470s/
+[ThinkPad T480]: https://pcsupport.lenovo.com/us/en/products/laptops-and-netbooks/thinkpad-t-series-laptops/thinkpad-t480-type-20l5-20l6/
+[ThinkPad T480s]: https://pcsupport.lenovo.com/us/en/products/laptops-and-netbooks/thinkpad-t-series-laptops/thinkpad-t480s-type-20l7-20l8/
+[Thinkpad T580]: https://pcsupport.lenovo.com/us/en/products/laptops-and-netbooks/thinkpad-t-series-laptops/thinkpad-t580-type-20l9-20la/
 [on Lenovo's site]: https://support.lenovo.com/us/en/downloads/ds502355-bios-update-utility-bootable-cd-for-windows-10-64-bit-linux-thinkpad-t480
 [from Lenovo's site]: https://pcsupport.lenovo.com/gb/en/products/laptops-and-netbooks/thinkpad-t-series-laptops/thinkpad-t480s-type-20l7-20l8/solutions/ht508988-critical-intel-thunderbolt-software-and-firmware-updates-thinkpad
 [how to externally flash the TB3 firmware]: https://libreboot.org/docs/install/t480.html#thunderbolt-issue-read-this-before-flashing
 [Dell firmware updater]: https://web.archive.org/web/20241110222323/https://dl.dell.com/FOLDER04573471M/1/Inspiron_5468_1.3.0.exe
-[Dell_PFS_Extract.py]: https://github.com/vuquangtrong/Dell-PFS-BIOS-Assembler/blob/master/Dell_PFS_Extract.py
\ No newline at end of file
+[Dell_PFS_Extract.py]: https://github.com/vuquangtrong/Dell-PFS-BIOS-Assembler/blob/master/Dell_PFS_Extract.py

From 3a1d6d5dede1fe8ac2fe860c4b02ee185ed3a699 Mon Sep 17 00:00:00 2001
From: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Date: Mon, 20 Oct 2025 11:34:15 +0800
Subject: [PATCH 2354/3886] mb/google/brox/var/caboc: Adjust WWAN power off
 sequence

Currently wwan_power.asl clears gpio WWAN (PERST) during power-off.

Caboc project uses a MOS reverse pin to connect GPP_A21
(WWAN_ASPM_EXIT) to WWAN (PERST). Based on this design, uses STXS to
keep GPP_A21 high to meet power-off sequence.

Set T1_OFF_MS to 20ms and T2_OFF_MS to 10ms as HW engineer requested.

BUG=b:453512678
TEST=emerge-brox coreboot
     HW enginer has measured and confirms WWAN power-off sequence.

Change-Id: I202a370dba2ba1dec61b1ad44140674bd470ba6e
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89642
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
---
 src/mainboard/google/brox/Kconfig                             | 1 -
 .../google/brox/variants/caboc/include/variant/gpio.h         | 4 ++--
 src/mainboard/google/brox/wwan_power.asl                      | 4 ++++
 3 files changed, 6 insertions(+), 3 deletions(-)

diff --git a/src/mainboard/google/brox/Kconfig b/src/mainboard/google/brox/Kconfig
index da73be5642..23cd594e20 100644
--- a/src/mainboard/google/brox/Kconfig
+++ b/src/mainboard/google/brox/Kconfig
@@ -100,7 +100,6 @@ config BOARD_GOOGLE_CABOC
 	select BOARD_GOOGLE_BASEBOARD_BROX
 	select CHROMEOS_WIFI_SAR if CHROMEOS
 	select DRIVERS_WWAN_FM350GL
-	select HAVE_PCIE_WWAN
 	select HAVE_WWAN_POWER_SEQUENCE
 	select MAINBOARD_HAS_GOOGLE_STRAUSS_KEYBOARD
 	select RT8168_GEN_ACPI_POWER_RESOURCE
diff --git a/src/mainboard/google/brox/variants/caboc/include/variant/gpio.h b/src/mainboard/google/brox/variants/caboc/include/variant/gpio.h
index 8fbc069648..d347707456 100644
--- a/src/mainboard/google/brox/variants/caboc/include/variant/gpio.h
+++ b/src/mainboard/google/brox/variants/caboc/include/variant/gpio.h
@@ -5,8 +5,8 @@
 
 #include <baseboard/gpio.h>
 
-#define T1_OFF_MS	16
-#define T2_OFF_MS	2
+#define T1_OFF_MS	20
+#define T2_OFF_MS	10
 #define WWAN_FCPO	GPP_F21
 #define WWAN_RST	GPP_D19
 #define WWAN_PERST	GPP_A21
diff --git a/src/mainboard/google/brox/wwan_power.asl b/src/mainboard/google/brox/wwan_power.asl
index f19a5ef4e9..2855e3cfbe 100644
--- a/src/mainboard/google/brox/wwan_power.asl
+++ b/src/mainboard/google/brox/wwan_power.asl
@@ -7,6 +7,10 @@ Method (MPTS, 1)
 #if CONFIG(HAVE_PCIE_WWAN)
 	\_SB.PCI0.CTXS(WWAN_PERST);
 	Sleep(T1_OFF_MS)
+#endif
+#if CONFIG(BOARD_GOOGLE_CABOC)
+	\_SB.PCI0.STXS(WWAN_PERST);
+	Sleep(T1_OFF_MS)
 #endif
 	\_SB.PCI0.CTXS(WWAN_RST);
 	Sleep(T2_OFF_MS)

From 4047a44b682e9f84eec63fb3b66ad3288e18b26a Mon Sep 17 00:00:00 2001
From: Keith Hui <buurin@gmail.com>
Date: Tue, 21 Oct 2025 21:39:21 -0400
Subject: [PATCH 2355/3886] sio/nuvoton/common/nuvoton.h: Add common Nuvoton
 SIO LDNs

Put the most commonly shared Nuvoton SIO logical device numbers into
one central header. It will be handy when they start sharing per-LDN
setup code.

Block iasl from seeing anything other than the LDNs.

Rename the re-inclusion guard symbol as its use is no longer limited to
pre-RAM stages.

It references NCT677x because that reference is hidden in every single
Nuvoton SIO chip datasheet in my possession.

Change-Id: Ibf01c0e0ffdecbedc34df62b582e3be0c5c0a852
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89739
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
---
 src/superio/nuvoton/common/nuvoton.h | 21 ++++++++++++++++++---
 1 file changed, 18 insertions(+), 3 deletions(-)

diff --git a/src/superio/nuvoton/common/nuvoton.h b/src/superio/nuvoton/common/nuvoton.h
index eb5bc759f3..0243c69b3e 100644
--- a/src/superio/nuvoton/common/nuvoton.h
+++ b/src/superio/nuvoton/common/nuvoton.h
@@ -1,13 +1,28 @@
 /* SPDX-License-Identifier: GPL-2.0-or-later */
 
-#ifndef SUPERIO_NUVOTON_COMMON_PRE_RAM_H
-#define SUPERIO_NUVOTON_COMMON_PRE_RAM_H
+#ifndef SUPERIO_NUVOTON_COMMON_H
+#define SUPERIO_NUVOTON_COMMON_H
 
+#ifndef __ACPI__
 #include <device/pnp_type.h>
 #include <stdint.h>
 
 void nuvoton_pnp_enter_conf_state(pnp_devfn_t dev);
 void nuvoton_pnp_exit_conf_state(pnp_devfn_t dev);
 void nuvoton_enable_serial(pnp_devfn_t dev, u16 iobase);
+#endif
 
-#endif /* SUPERIO_NUVOTON_COMMON_PRE_RAM_H */
+/*
+ * Logical Device Numbers (LDN) common to all Nuvoton SIOs.
+ * Because they will be incorporated into ACPI device IDs,
+ * they must be written as decimal.
+ */
+#define NCT677X_PP		1 /* Parallel port */
+#define NCT677X_SP1		2 /* COM1 */
+#define NCT677X_SP2		3 /* COM2 & IR */
+#define NCT677X_KBC		5 /* PS/2 keyboard and mouse */
+#define NCT677X_ACPI		10 /* ACPI */
+#define NCT677X_HWM_FPLED	11 /* Hardware monitor & front LED */
+#define NCT677X_MAXLDN		22 /* The highest known LDN of these chips (0x16) */
+
+#endif /* SUPERIO_NUVOTON_COMMON_H */

From 56a8c40efa1875a0c2d9cd719fe65b8111c2a6ff Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Mon, 27 Oct 2025 15:42:55 +0000
Subject: [PATCH 2356/3886] mb/starlabs/starlite_adl: Add missing ACPI entry
 for USB card reader

commit 80861a9f6999 ("mb/starlabs/starlite_adl: Add CFR option for
USB card reader") added support for the USB card reader, but did
not add the corresponding ACPI entries.

Change-Id: Ibef1b8412d5f51ffbfa715bb1ee80f73411dd3b3
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89772
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 .../starlabs/starlite_adl/variants/mk_v/devicetree.cb      | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/src/mainboard/starlabs/starlite_adl/variants/mk_v/devicetree.cb b/src/mainboard/starlabs/starlite_adl/variants/mk_v/devicetree.cb
index 857d626197..10680827c6 100644
--- a/src/mainboard/starlabs/starlite_adl/variants/mk_v/devicetree.cb
+++ b/src/mainboard/starlabs/starlite_adl/variants/mk_v/devicetree.cb
@@ -85,6 +85,7 @@ chip soc/intel/alderlake
 			# Internal Bluetooth			1874 mil
 			register "usb2_ports[9]"		= "USB2_PORT_SHORT(OC_SKIP)"
 
+			# Card Reader
 			register "usb2_ports[3]"		= "USB2_PORT_MID(OC_SKIP)"
 
 			chip drivers/usb/acpi
@@ -124,6 +125,12 @@ chip soc/intel/alderlake
 						register "group"		= "ACPI_PLD_GROUP(0, 2)"
 						device ref usb2_port3 on end
 					end
+					chip drivers/usb/acpi
+						register "desc"			= ""Card Reader""
+						register "type"			= "UPC_TYPE_INTERNAL"
+						register "group"		= "ACPI_PLD_GROUP(0, 6)"
+						device usb 2.3 alias card_reader on end
+					end
 					chip drivers/usb/acpi
 						register "desc"			= ""USB 2.0 Hub""
 						register "type"			= "UPC_TYPE_HUB"

From 784d8f25f90cce36a737c0d249ea1277e23d9911 Mon Sep 17 00:00:00 2001
From: Luca Lai <luca.lai@lcfc.corp-partner.google.com>
Date: Mon, 27 Oct 2025 10:32:40 +0800
Subject: [PATCH 2357/3886] mb/google/fatcat/var/ruby: Enable panel touch
 function

Modify gpio and device tree setting to to make the touchscreen
function work.

schematics: RUBY_EVT_0902_2112.pdf

Device i2c log:
[INFO ]  \_SB.PCI0.CNVW: WIFI Device GENERIC: 0.0
[INFO ]  \_SB.PCI0.I2C0.RT58: Headset Codec at I2C: 00:1a
[INFO ]  \_SB.PCI0.I2C0.D04B: TI SPK AMP L at I2C: 00:4b
[INFO ]  \_SB.PCI0.I2C0.D04C: TI SPK AMP R at I2C: 00:4c
[INFO ]  \_SB.PCI0.I2C0.D04D: 	TI SPK AMP TL at I2C: 00:4d
[INFO ]  \_SB.PCI0.I2C0.D04F: T1 SPK AMP TR at I2C: 00:4f
[INFO ]  \_SB.PCI0.I2C3.TPMI: I2C TPM at I2C: 00:50
[INFO ]  \_SB.PCI0.I2C4.H015: ELAN Touchpad at I2C: 00:15
[INFO ]  \_SB.PCI0.I2C5.H014: Goodix Touchscreen at I2C: 00:14
[INFO ]  \_SB.PCI0.RP01: Enable RTD3 for PCI: 00:00:1c.0 (Intel PCIe Runtime D3)

BUG=b:451935490
TEST=Build and boot to OS and check touch function work.

Change-Id: I867e10d34e4bed5a5db242a74e8c9ac04657feb9
Signed-off-by: Luca Lai <luca.lai@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89757
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
---
 src/mainboard/google/fatcat/variants/ruby/gpio.c          | 4 ++--
 src/mainboard/google/fatcat/variants/ruby/overridetree.cb | 8 ++++----
 2 files changed, 6 insertions(+), 6 deletions(-)

diff --git a/src/mainboard/google/fatcat/variants/ruby/gpio.c b/src/mainboard/google/fatcat/variants/ruby/gpio.c
index ebaad6f95f..9eb0fbe80e 100644
--- a/src/mainboard/google/fatcat/variants/ruby/gpio.c
+++ b/src/mainboard/google/fatcat/variants/ruby/gpio.c
@@ -197,7 +197,7 @@ static const struct pad_config gpio_table[] = {
 	/* GPP_E03:     NC */
 	PAD_NC(GPP_E03, NONE),
 	/* GPP_E05:     TCHSCR_RPT_EN */
-	PAD_CFG_GPO(GPP_E05, 1, DEEP),
+	PAD_CFG_GPO(GPP_E05, 0, PLTRST),
 	/* GPP_E06:     SECURE_CAM_SW */
 	PAD_CFG_GPI_TRIG_OWN(GPP_E06, NONE, PLTRST, LEVEL, ACPI),
 	/* GPP_E07 : [] ==> EC_SOC_INT_ODL */
@@ -254,7 +254,7 @@ static const struct pad_config gpio_table[] = {
 	/* GPP_F07:     NC */
 	PAD_NC(GPP_F07, NONE),
 	/* GPP_F08:     EN_TCHSCR_PWR */
-	PAD_CFG_GPO(GPP_F08, 1, DEEP),
+	PAD_CFG_GPO(GPP_F08, 1, PLTRST),
 	/* GPP_F09:     NC */
 	PAD_NC(GPP_F09, NONE),
 	/* GPP_F10:     ISH_GP_6_SNSR_HDR */
diff --git a/src/mainboard/google/fatcat/variants/ruby/overridetree.cb b/src/mainboard/google/fatcat/variants/ruby/overridetree.cb
index fe8c7eaadc..e9efe66691 100644
--- a/src/mainboard/google/fatcat/variants/ruby/overridetree.cb
+++ b/src/mainboard/google/fatcat/variants/ruby/overridetree.cb
@@ -278,8 +278,8 @@ chip soc/intel/pantherlake
 		end # I2C4
 		device ref i2c5 on
 			chip drivers/i2c/hid
-				register "generic.hid" = ""ELAN9004""
-				register "generic.desc" = ""ELAN Touchscreen""
+				register "generic.hid" = ""GT7936L""
+				register "generic.desc" = ""Goodix Touchscreen""
 				register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_F18_IRQ)"
 				register "generic.detect" = "1"
 				register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_F16)"
@@ -289,11 +289,11 @@ chip soc/intel/pantherlake
 				register "generic.enable_delay_ms" = "6"
 				register "generic.enable_off_delay_ms" = "30"
 				register "generic.stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_E05)"
-				register "generic.stop_off_delay_ms" = "1"
+				register "generic.stop_delay_ms" = "1"
 				register "generic.has_power_resource" = "1"
 				register "generic.use_gpio_for_status" = "true"
 				register "hid_desc_reg_offset" = "0x01"
-				device i2c 0x10 on end
+				device i2c 0x14 on end
 			end
 		end # I2C5
 		device ref gspi0 on end

From 82d90b1f2132c644bf831d7459562607b78ca6cb Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Wed, 29 Oct 2025 11:59:13 +0000
Subject: [PATCH 2358/3886] Revert "mb/starlabs/*/rpl: Re-enable GpioOverride"

This reverts commit 8a2c04e04db7b2db5ced00df3bbd6c81778cdbbe.

Reason for revert: The hang is still present

Change-Id: Iba3c2b684cce3adefecd175d0ef09a5d051410ae
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89805
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/starlabs/starbook/variants/rpl/romstage.c    | 1 +
 src/mainboard/starlabs/starfighter/variants/rpl/romstage.c | 1 +
 2 files changed, 2 insertions(+)

diff --git a/src/mainboard/starlabs/starbook/variants/rpl/romstage.c b/src/mainboard/starlabs/starbook/variants/rpl/romstage.c
index 20d518c5c3..5038a526b7 100644
--- a/src/mainboard/starlabs/starbook/variants/rpl/romstage.c
+++ b/src/mainboard/starlabs/starbook/variants/rpl/romstage.c
@@ -46,4 +46,5 @@ void mainboard_memory_init_params(FSPM_UPD *mupd)
 	}
 
 	mupd->FspmConfig.DmiMaxLinkSpeed = 4;
+	mupd->FspmConfig.GpioOverride = 0;
 };
diff --git a/src/mainboard/starlabs/starfighter/variants/rpl/romstage.c b/src/mainboard/starlabs/starfighter/variants/rpl/romstage.c
index e382582de6..6ec63a16d7 100644
--- a/src/mainboard/starlabs/starfighter/variants/rpl/romstage.c
+++ b/src/mainboard/starlabs/starfighter/variants/rpl/romstage.c
@@ -141,4 +141,5 @@ void mainboard_memory_init_params(FSPM_UPD *mupd)
 	}
 
 	mupd->FspmConfig.DmiMaxLinkSpeed = 4;
+	mupd->FspmConfig.GpioOverride = 0;
 };

From d7f427a7d23ab6fe7ab5a990b9704346f86d7a25 Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Mon, 20 Oct 2025 10:19:01 +0100
Subject: [PATCH 2359/3886] util/xcompile: Fix compiler detection on newer
 Linux distros
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Switch to using `objdump -f`, which consistently prints the line
"file format <format>" across modern binutils versions, and extract
the architecture format from that output. This restores correct
toolchain detection on Ubuntu 25.10 and other systems with binutils
≥ 2.43, without breakng older versions.

Before:
    DEBUG: obj_type:
    /tmp/temp.rrDQ8i.o:     file format elf64-x86-64
    DEBUG: obj_arch:

After:
    DEBUG: obj_type:
    /tmp/temp.8GsK08.o:     file format elf64-x86-64
    architecture: i386:x86-64, flags 0x00000000:

    start address 0x0000000000000000
    DEBUG: obj_arch: elf64-x86-64

Change-Id: Ic09304f9e81580bbe1c0bb4910c0cc534d3d2816
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89643
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
---
 util/xcompile/xcompile | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/util/xcompile/xcompile b/util/xcompile/xcompile
index 6443dd2a90..8f0d19a6a6 100755
--- a/util/xcompile/xcompile
+++ b/util/xcompile/xcompile
@@ -155,8 +155,8 @@ testas() {
 		2>/dev/null || return 1
 
 	# Check output content type.
-	local obj_type="$(LANG=C LC_ALL='' "${gccprefix}"objdump -p "$obj_file" 2>/dev/null)"
-	local obj_arch="$(expr "$obj_type" : '.*format \(.[a-z0-9-]*\)')"
+	local obj_type="$(LANG=C LC_ALL='' "${gccprefix}"objdump -f "$obj_file" 2>/dev/null)"
+	local obj_arch="$(printf '%s\n' "$obj_type" | sed -n 's/.*file format \([a-z0-9-]*\).*/\1/p')"
 	[ "$obj_arch" = "$full_arch" ] || return 1
 
 	unset ASFLAGS LDFLAGS

From a5b51ab2850c7c4e5249ae7cf0da7cdf30d1a877 Mon Sep 17 00:00:00 2001
From: David Wu <david_wu@quanta.corp-partner.google.com>
Date: Tue, 28 Oct 2025 10:26:37 +0800
Subject: [PATCH 2360/3886] mb/google/rex/var/kanix: Add H58G66CK8BX147 to RAM
 ID table

Add the new memory support: Hynix H58G66CK8BX147

BUG=b:441882141
TEST=Run part_id_gen tool and check the generated files.

Change-Id: Iebdb05d134ee0719257a9d16121b5bf3977f06ed
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89780
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
---
 src/mainboard/google/rex/variants/kanix/memory/Makefile.mk       | 1 +
 .../google/rex/variants/kanix/memory/dram_id.generated.txt       | 1 +
 .../google/rex/variants/kanix/memory/mem_parts_used.txt          | 1 +
 3 files changed, 3 insertions(+)

diff --git a/src/mainboard/google/rex/variants/kanix/memory/Makefile.mk b/src/mainboard/google/rex/variants/kanix/memory/Makefile.mk
index f818a38d02..59d88581ed 100644
--- a/src/mainboard/google/rex/variants/kanix/memory/Makefile.mk
+++ b/src/mainboard/google/rex/variants/kanix/memory/Makefile.mk
@@ -7,3 +7,4 @@ SPD_SOURCES =
 SPD_SOURCES += spd/lp5/set-0/spd-11.hex      # ID = 0(0b0000)  Parts = MT62F1G32D2DS-023 WT:B, H58G56BK8BX068, H58G56CK8BX146, K3KL8L80EM-MGCU
 SPD_SOURCES += spd/lp5/set-0/spd-1.hex      # ID = 1(0b0001)  Parts = H9JCNNNBK3MLYR-N6E, MT62F512M32D2DR-031 WT:B
 SPD_SOURCES += spd/lp5/set-0/spd-7.hex      # ID = 2(0b0010)  Parts = K3KL8L80CM-MGCT
+SPD_SOURCES += spd/lp5/set-0/spd-10.hex      # ID = 3(0b0011)  Parts = H58G66CK8BX147
diff --git a/src/mainboard/google/rex/variants/kanix/memory/dram_id.generated.txt b/src/mainboard/google/rex/variants/kanix/memory/dram_id.generated.txt
index 74e7f23d8b..896ca7ede5 100644
--- a/src/mainboard/google/rex/variants/kanix/memory/dram_id.generated.txt
+++ b/src/mainboard/google/rex/variants/kanix/memory/dram_id.generated.txt
@@ -11,3 +11,4 @@ K3KL8L80CM-MGCT                2 (0010)
 MT62F512M32D2DR-031 WT:B       1 (0001)
 H58G56CK8BX146                 0 (0000)
 K3KL8L80EM-MGCU                0 (0000)
+H58G66CK8BX147                 3 (0011)
diff --git a/src/mainboard/google/rex/variants/kanix/memory/mem_parts_used.txt b/src/mainboard/google/rex/variants/kanix/memory/mem_parts_used.txt
index 3fa9bc7335..8aec4b9616 100644
--- a/src/mainboard/google/rex/variants/kanix/memory/mem_parts_used.txt
+++ b/src/mainboard/google/rex/variants/kanix/memory/mem_parts_used.txt
@@ -16,3 +16,4 @@ K3KL8L80CM-MGCT
 MT62F512M32D2DR-031 WT:B
 H58G56CK8BX146
 K3KL8L80EM-MGCU
+H58G66CK8BX147

From 105598545e4bfab6d53b3d2d1cc21b1281a5e1ab Mon Sep 17 00:00:00 2001
From: Bora Guvendik <bora.guvendik@intel.com>
Date: Thu, 23 Oct 2025 13:30:39 -0700
Subject: [PATCH 2361/3886] soc/intel/pantherlake: Update thermal design
 current parameters
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Update thermal design current (TDC) values for GT domain across
multiple PTL SKUs based on input from Power and Performance team.

BUG=none
TEST=Boot to OS on fatcat device and check performance.

Change-Id: I6333f8b5db8c7fc1739d0772d83bfe602a837a53
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89697
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Reviewed-by: Ma, Zhixing <zhixing.ma@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/soc/intel/pantherlake/chipset_ptl.cb | 9 ++++-----
 1 file changed, 4 insertions(+), 5 deletions(-)

diff --git a/src/soc/intel/pantherlake/chipset_ptl.cb b/src/soc/intel/pantherlake/chipset_ptl.cb
index 1c6075aff9..676a309f2e 100644
--- a/src/soc/intel/pantherlake/chipset_ptl.cb
+++ b/src/soc/intel/pantherlake/chipset_ptl.cb
@@ -10,7 +10,7 @@ chip soc/intel/pantherlake
 	}"
 	register "thermal_design_current[PTL_SKU_1]" = "{
 		[VR_DOMAIN_IA] = 23 * 8,
-		[VR_DOMAIN_GT] = 15 * 8
+		[VR_DOMAIN_GT] = 23 * 8
 	}"
 	register "icc_max[PTL_SKU_1]" = "{
 		[VR_DOMAIN_IA] = 80 * 4,
@@ -27,7 +27,7 @@ chip soc/intel/pantherlake
 	}"
 	register "thermal_design_current[PTL_SKU_5]" = "{
 		[VR_DOMAIN_IA] = 23 * 8,
-		[VR_DOMAIN_GT] = 15 * 8
+		[VR_DOMAIN_GT] = 23 * 8
 	}"
 	register "icc_max[PTL_SKU_5]" = "{
 		[VR_DOMAIN_IA] = 80 * 4,
@@ -44,7 +44,7 @@ chip soc/intel/pantherlake
 	}"
 	register "thermal_design_current[PTL_SKU_2]" = "{
 		[VR_DOMAIN_IA] = 31 * 8,
-		[VR_DOMAIN_GT] = 25 * 8
+		[VR_DOMAIN_GT] = 44 * 8
 	}"
 	register "icc_max[PTL_SKU_2]" = "{
 		[VR_DOMAIN_IA] = 107 * 4,
@@ -67,7 +67,7 @@ chip soc/intel/pantherlake
 
 	register "thermal_design_current[PTL_SKU_6]" = "{
 		[VR_DOMAIN_IA] = 31 * 8,
-		[VR_DOMAIN_GT] = 25 * 8
+		[VR_DOMAIN_GT] = 44 * 8
 	}"
 	register "icc_max[PTL_SKU_6]" = "{
 		[VR_DOMAIN_IA] = 90 * 4,
@@ -77,7 +77,6 @@ chip soc/intel/pantherlake
 	}"
 
 	register "tdc_mode[VR_DOMAIN_IA]" = "TDC_IRMS"
-	register "tdc_mode[VR_DOMAIN_GT]" = "TDC_IRMS"
 	register "tdc_time_window_ms[VR_DOMAIN_IA]" = "28000"
 
 	# Set the power state thresholds according to document 813278

From da204a92c1f23dcced1dc1cbb657b4985a56dc20 Mon Sep 17 00:00:00 2001
From: Zhixing Ma <zhixing.ma@intel.corp-partner.google.com>
Date: Mon, 27 Oct 2025 13:29:08 -0700
Subject: [PATCH 2362/3886] vc/intel/fsp/wildcatlake: Expose
 PchHdaMicPrivacyMode
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Expose the PchHdaMicPrivacyMode UPD parameter in the FSP-S
configuration structure for WildcatLake. This parameter controls
the HD Audio microphone privacy mode, allowing mainboards to
configure whether microphone privacy is hardware-managed,
firmware-managed, forced to mute, or disabled entirely.

TEST=Built WCL FSP successfully with this change.

Change-Id: If48c684aea09291715718a6e8fb400b9550aab61
Signed-off-by: Zhixing Ma <zhixing.ma@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89779
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
---
 .../intel/fsp/fsp2_0/wildcatlake/FspsUpd.h           | 12 ++++++++++--
 1 file changed, 10 insertions(+), 2 deletions(-)

diff --git a/src/vendorcode/intel/fsp/fsp2_0/wildcatlake/FspsUpd.h b/src/vendorcode/intel/fsp/fsp2_0/wildcatlake/FspsUpd.h
index 0b540c7e14..b5194418b1 100644
--- a/src/vendorcode/intel/fsp/fsp2_0/wildcatlake/FspsUpd.h
+++ b/src/vendorcode/intel/fsp/fsp2_0/wildcatlake/FspsUpd.h
@@ -2337,9 +2337,17 @@ typedef struct {
 **/
   UINT8                       PchHdaLinkFrequency;
 
-/** Offset 0x149B - Reserved
+/** Offset 0x149B - HD Audio Microphone Privacy Mode
+  HD Audio Microphone Privacy Mode: 0: No Microphone Privacy Support; 1: HW Managed
+  Microphone Privacy; 2: FW Managed Microphone Privacy; 3: Force Microphone Mute
+  0: No Microphone Privacy Support, 1: HW Managed Microphone Privacy, 2: FW Managed
+  Microphone Privacy, 3: Force Microphone Mute
 **/
-  UINT8                       Reserved59[2];
+  UINT8                       PchHdaMicPrivacyMode;
+
+/** Offset 0x149C - Reserved
+**/
+  UINT8                       Reserved59;
 
 /** Offset 0x149D - HD Audio Microphone Privacy applied for SoundWire Link number 0 in HW Mode
   HD Audio Microphone Privacy applied for SoundWire Link number 0 in HW Mode: 0: Disable, 1: Enable

From 1815a204b4cb814f2b219b2baace1879ab37850b Mon Sep 17 00:00:00 2001
From: "Johann C. Rode" <jcrode@gmx.net>
Date: Mon, 20 Oct 2025 09:48:01 -0700
Subject: [PATCH 2363/3886] src/mainboard/lenovo: Add smbios_slot_desc, fix
 register types

Mostly cosmetic fixes.

Change-Id: I701b32de78f74bfd9ad3a82096f7ad92ffbb46e1
Signed-off-by: Johann C. Rode <jcrode@gmx.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89648
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 .../variants/t480/overridetree.cb             | 21 +++++++++++--------
 .../variants/t480s/overridetree.cb            | 21 +++++++++++--------
 2 files changed, 24 insertions(+), 18 deletions(-)

diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480/overridetree.cb b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480/overridetree.cb
index 3b05ae9fdc..d052b48e0e 100644
--- a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480/overridetree.cb
+++ b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480/overridetree.cb
@@ -40,17 +40,17 @@ chip soc/intel/skylake
 			register "PcieRpClkReqSupport[0]"		= "true"
 			register "PcieRpClkReqNumber[0]"		= "0"
 			register "PcieRpClkSrcNumber[0]"		= "0"
-			register "PcieRpAdvancedErrorReporting[0]"	= "1"
+			register "PcieRpAdvancedErrorReporting[0]"	= "true"
 			register "PcieRpLtrEnable[0]"			= "true"
 			device generic 0 alias dgpu on end
 		end
 
 		# Ethernet (clobbers RP8)
 		device ref gbe on
-			register "LanClkReqSupported"			= "1"
+			register "LanClkReqSupported"			= "true"
 			register "LanClkReqNumber"			= "1"
-			register "EnableLanLtr"				= "1"
-			register "EnableLanK1Off"			= "1"
+			register "EnableLanLtr"				= "true"
+			register "EnableLanK1Off"			= "true"
 		end
 
 		# M.2 WLAN - x1
@@ -58,8 +58,9 @@ chip soc/intel/skylake
 			register "PcieRpClkReqSupport[6]"		= "true"
 			register "PcieRpClkReqNumber[6]"		= "2"
 			register "PcieRpClkSrcNumber[6]"		= "2"
-			register "PcieRpAdvancedErrorReporting[6]"	= "1"
+			register "PcieRpAdvancedErrorReporting[6]"	= "true"
 			register "PcieRpLtrEnable[6]"			= "true"
+                        smbios_slot_desc "SlotTypeM2Socket1_DP" "SlotLengthOther" "M.2/A 2230" "SlotDataBusWidth1X"
 		end
 
 		# M.2 WWAN - x2
@@ -67,8 +68,9 @@ chip soc/intel/skylake
 			register "PcieRpClkReqSupport[4]"		= "true"
 			register "PcieRpClkReqNumber[4]"		= "3"
 			register "PcieRpClkSrcNumber[4]"		= "3"
-			register "PcieRpAdvancedErrorReporting[4]"	= "1"
+			register "PcieRpAdvancedErrorReporting[4]"	= "true"
 			register "PcieRpLtrEnable[4]"			= "true"
+                        smbios_slot_desc "SlotTypeM2Socket1_DP" "SlotLengthOther" "M.2/A 2230" "SlotDataBusWidth1X"
 		end
 
 		# TB3 (Alpine Ridge LP) - x2
@@ -76,9 +78,9 @@ chip soc/intel/skylake
 			register "PcieRpClkReqSupport[8]"		= "true"
 			register "PcieRpClkReqNumber[8]"		= "4"
 			register "PcieRpClkSrcNumber[8]"		= "4"
-			register "PcieRpAdvancedErrorReporting[8]"	= "1"
+			register "PcieRpAdvancedErrorReporting[8]"	= "true"
 			register "PcieRpLtrEnable[8]"			= "true"
-			register "PcieRpHotPlug[8]"			= "1"
+			register "PcieRpHotPlug[8]"			= "true"
 		end
 
 		# M.2 2280 caddy - x2
@@ -86,8 +88,9 @@ chip soc/intel/skylake
 			register "PcieRpClkReqSupport[10]"		= "true"
 			register "PcieRpClkReqNumber[10]"		= "5"
 			register "PcieRpClkSrcNumber[10]"		= "5"
-			register "PcieRpAdvancedErrorReporting[10]"	= "1"
+			register "PcieRpAdvancedErrorReporting[10]"	= "true"
 			register "PcieRpLtrEnable[10]"			= "true"
+                        smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M.2/M 2280 Sub Card" "SlotDataBusWidth2X"
 		end
 	end
 end
diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/overridetree.cb b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/overridetree.cb
index 6a933c42c8..78a1a22eef 100644
--- a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/overridetree.cb
+++ b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/overridetree.cb
@@ -40,7 +40,7 @@ chip soc/intel/skylake
 			register "PcieRpClkReqSupport[0]"		= "true"
 			register "PcieRpClkReqNumber[0]"		= "0"
 			register "PcieRpClkSrcNumber[0]"		= "0"
-			register "PcieRpAdvancedErrorReporting[0]"	= "1"
+			register "PcieRpAdvancedErrorReporting[0]"	= "true"
 			register "PcieRpLtrEnable[0]"			= "true"
 			device generic 0 alias dgpu on end
 		end
@@ -50,16 +50,17 @@ chip soc/intel/skylake
 			register "PcieRpClkReqSupport[3]"		= "true"
 			register "PcieRpClkReqNumber[3]"		= "1"
 			register "PcieRpClkSrcNumber[3]"		= "1"
-			register "PcieRpAdvancedErrorReporting[3]"	= "1"
+			register "PcieRpAdvancedErrorReporting[3]"	= "true"
 			register "PcieRpLtrEnable[3]"			= "true"
+                        smbios_slot_desc "SlotTypeM2Socket2" "SlotLengthOther" "M.2/B 3042/2242" "SlotDataBusWidth2X"
 		end
 
 		# Ethernet (clobbers RP8)
 		device ref gbe on
-			register "LanClkReqSupported"			= "1"
+			register "LanClkReqSupported"			= "true"
 			register "LanClkReqNumber"			= "2"
-			register "EnableLanLtr"				= "1"
-			register "EnableLanK1Off"			= "1"
+			register "EnableLanLtr"				= "true"
+			register "EnableLanK1Off"			= "true"
 		end
 
 		# M.2 WLAN - x1
@@ -67,8 +68,9 @@ chip soc/intel/skylake
 			register "PcieRpClkReqSupport[6]"		= "true"
 			register "PcieRpClkReqNumber[6]"		= "3"
 			register "PcieRpClkSrcNumber[6]"		= "3"
-			register "PcieRpAdvancedErrorReporting[6]"	= "1"
+			register "PcieRpAdvancedErrorReporting[6]"	= "true"
 			register "PcieRpLtrEnable[6]"			= "true"
+                        smbios_slot_desc "SlotTypeM2Socket1_DP" "SlotLengthOther" "M.2/A 2230" "SlotDataBusWidth1X"
 		end
 
 		# TB3 (Alpine Ridge LP) - x2
@@ -76,9 +78,9 @@ chip soc/intel/skylake
 			register "PcieRpClkReqSupport[4]"		= "true"
 			register "PcieRpClkReqNumber[4]"		= "4"
 			register "PcieRpClkSrcNumber[4]"		= "4"
-			register "PcieRpAdvancedErrorReporting[4]"	= "1"
+			register "PcieRpAdvancedErrorReporting[4]"	= "true"
 			register "PcieRpLtrEnable[4]"			= "true"
-			register "PcieRpHotPlug[4]"			= "1"
+			register "PcieRpHotPlug[4]"			= "true"
 		end
 
 		# M.2 2280 SSD - x2
@@ -86,8 +88,9 @@ chip soc/intel/skylake
 			register "PcieRpClkReqSupport[8]"		= "true"
 			register "PcieRpClkReqNumber[8]"		= "5"
 			register "PcieRpClkSrcNumber[8]"		= "5"
-			register "PcieRpAdvancedErrorReporting[8]"	= "1"
+			register "PcieRpAdvancedErrorReporting[8]"	= "true"
 			register "PcieRpLtrEnable[8]"			= "true"
+                        smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M.2/M 2280" "SlotDataBusWidth2X"
 		end
 	end
 end

From 1eda98a16eae648a14023f900c50e837f74c4e0b Mon Sep 17 00:00:00 2001
From: Kilian Krause <kilian.krause@siemens.com>
Date: Tue, 28 Oct 2025 15:04:39 +0100
Subject: [PATCH 2364/3886] mb/siemens/mc_rpl1: Document CLKSRC 2 usage for
 PCIe RP5

PCIe Root Port 5 uses both CLKSRC 1 and CLKSRC 2, but coreboot's
devicetree only allows configuring a single clock source per port. Add
a comment to document that CLKSRC 2 is implicitly used by the hardware.

Change-Id: I9b54d97fa5e4e4e80a58392a7592bab91e00824d
Signed-off-by: Kilian Krause <kilian.krause@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89791
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
---
 src/mainboard/siemens/mc_rpl/variants/mc_rpl1/overridetree.cb | 1 +
 1 file changed, 1 insertion(+)

diff --git a/src/mainboard/siemens/mc_rpl/variants/mc_rpl1/overridetree.cb b/src/mainboard/siemens/mc_rpl/variants/mc_rpl1/overridetree.cb
index 4c2350b779..3c26345eae 100644
--- a/src/mainboard/siemens/mc_rpl/variants/mc_rpl1/overridetree.cb
+++ b/src/mainboard/siemens/mc_rpl/variants/mc_rpl1/overridetree.cb
@@ -96,6 +96,7 @@ chip soc/intel/alderlake
 			}"
 		end
 		device ref pcie_rp5 on
+			# Uses CLKSRC 1 + 2 (only 1 configurable)
 			register "pch_pcie_rp[PCH_RP(5)]" = "{
 				.clk_src = 1,
 				.flags = PCIE_RP_CLK_REQ_UNUSED,

From 04d9a0d0f0f589e86d4143938105a8e904af460e Mon Sep 17 00:00:00 2001
From: Angel Pons <th3fanbus@gmail.com>
Date: Thu, 30 Oct 2025 15:07:31 +0100
Subject: [PATCH 2365/3886] ec/starlabs/merlin/Kconfig: Fix typo in
 description/help text

Selec ---> Select

Change-Id: I53936c72ec0fb0227fb733dc07e2c3268a5c72d2
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89832
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
---
 src/ec/starlabs/merlin/Kconfig | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/ec/starlabs/merlin/Kconfig b/src/ec/starlabs/merlin/Kconfig
index 4758d44de1..5e22cb00d1 100644
--- a/src/ec/starlabs/merlin/Kconfig
+++ b/src/ec/starlabs/merlin/Kconfig
@@ -66,7 +66,7 @@ config EC_STARLABS_POWER_LED
 	bool "Enable lowering the brightess of the Power LED"
 	depends on EC_STARLABS_ITE
 	help
-	  Selec the in the mainboard supports reducing the LED brightness
+	  Select the in the mainboard supports reducing the LED brightness
 
 config EC_STARLABS_MERLIN
 	bool "Use open-source Merlin EC Firmware"

From 4a806a68651e9242a11ea06a6bc5e8cd7b9cefaa Mon Sep 17 00:00:00 2001
From: Angel Pons <th3fanbus@gmail.com>
Date: Thu, 30 Oct 2025 15:18:03 +0100
Subject: [PATCH 2366/3886] ec/starlabs/merlin: Only show EC FW options for ITE
 EC

The `EC_STARLABS_ADD_ITE_BIN` Kconfig option is only meaningful on
Star Labs boards with an ITE EC, i.e. those with `EC_STARLABS_ITE`
selected. So, add a "depends on" line so that the former option is
only visible on applicable boards.

TEST=`EC_STARLABS_ADD_ITE_BIN` no longer shows up for qemu-q35.

Change-Id: Ifb40d8b432d2abeadba2a970010dac126e4b7418
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89833
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
---
 src/ec/starlabs/merlin/Kconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/src/ec/starlabs/merlin/Kconfig b/src/ec/starlabs/merlin/Kconfig
index 5e22cb00d1..12c4600b42 100644
--- a/src/ec/starlabs/merlin/Kconfig
+++ b/src/ec/starlabs/merlin/Kconfig
@@ -20,6 +20,7 @@ config EC_STARLABS_ITE
 config EC_STARLABS_ADD_ITE_BIN
 	bool "Add Star Labs EC binary file"
 	default n
+	depends on EC_STARLABS_ITE
 	help
 	  Select to add an EC firmware binary into the coreboot image. EC firmware
 	  is necessary, flashing a coreboot image without EC firmware will render

From c189604f4335624967d32b59b72cdbd418e34a97 Mon Sep 17 00:00:00 2001
From: Nick Vaccaro <nvaccaro@google.com>
Date: Thu, 30 Oct 2025 14:54:04 -0700
Subject: [PATCH 2367/3886] mb/goog/ocelot/var/ocelot: Enable rp5 if PCIE WiFi
 detected

Enable rp5 if the FW_CONFIG bits for WIFI are set to WIFI_PCIE_6 or
WIFI_PCIE_7.

BUG=b:444509417
TEST=emerge-ocelot coreboot chromeos-bootimage', flash ocelot and
verify CNVI and PCIe WiFi solutions are detected correctly.

Change-Id: I077bfc48a82c354d1011ef756aa6aa55bf6951cd
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89838
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Appukuttan V K <appukuttan.vk@intel.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
---
 .../google/ocelot/variants/ocelot/overridetree.cb      | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/src/mainboard/google/ocelot/variants/ocelot/overridetree.cb b/src/mainboard/google/ocelot/variants/ocelot/overridetree.cb
index 7a06471ea3..3b0c1b49c7 100644
--- a/src/mainboard/google/ocelot/variants/ocelot/overridetree.cb
+++ b/src/mainboard/google/ocelot/variants/ocelot/overridetree.cb
@@ -473,6 +473,16 @@ chip soc/intel/pantherlake
 			end
 		end # Gen4 M.2 SSD
 
+		device ref pcie_rp5 on
+			probe WIFI WIFI_PCIE_6
+			probe WIFI WIFI_PCIE_7
+			register "pcie_rp[PCIE_RP(5)]" = "{
+			.clk_src = 0,
+			.clk_req = 0,
+			.flags = PCIE_RP_CLK_REQ_DETECT | PCIE_RP_LTR | PCIE_RP_AER,
+			}"
+		end # M.2 WLAN KEY-E
+
 		device ref pcie_rp6 on
 			probe SD SD_GENSYS
 			probe SD SD_BAYHUB

From 410506b47cda79f2e4ad7307d5d31d43a2ae2d16 Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Thu, 30 Oct 2025 11:59:09 -0500
Subject: [PATCH 2368/3886] Makefile.mk: Print all FMAP region sizes in
 hexadecimal format

The generated build/fmap.fmd file was displaying region sizes and
offsets in a mix of decimal and hexadecimal formats, making it harder
to read and compare values. This change ensures all numeric values are
consistently printed in hexadecimal.

The conversion to hex is done in two places:

1. For conditional FMAP entries (MRC_CACHE, SMMSTORE, SPD_CACHE, VPD,
   HSPHY_FW, CONSOLE), the _tohex conversion is applied at entry
   definition time. This is necessary because these entries may be
   empty when their respective CONFIG options are disabled, and the
   conditional logic happens before the sed substitution.

2. For unconditional values (ROM_SIZE, BIOS_BASE, BIOS_SIZE,
   FMAP_BASE, CBFS_BASE, CBFS_SIZE), the _tohex conversion is applied
   directly in the sed command when generating fmap.fmd. This keeps
   the base variables in decimal form for continued use in arithmetic
   operations.

All internal calculations continue to use decimal values. Only the
final output strings that are written to fmap.fmd are converted to hex
format.

Before:
  SI_BIOS@29032448 4521984 {
    SMMSTORE@65536 0x40000
    RW_SPD_CACHE@327680 4096

After:
  SI_BIOS@0x1bb0000 0x450000 {
    SMMSTORE@0x10000 0x40000
    RW_SPD_CACHE@0x50000 0x1000

Change-Id: I48cc39b430943cb4923955b5e3d64ad6dd24a6cf
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89836
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
---
 Makefile.mk | 28 ++++++++++++++--------------
 1 file changed, 14 insertions(+), 14 deletions(-)

diff --git a/Makefile.mk b/Makefile.mk
index e28e4f800d..abc804e99a 100644
--- a/Makefile.mk
+++ b/Makefile.mk
@@ -1112,7 +1112,7 @@ FMAP_CURRENT_BASE := 0
 ifeq ($(CONFIG_CONSOLE_SPI_FLASH),y)
 FMAP_CONSOLE_BASE := $(FMAP_CURRENT_BASE)
 FMAP_CONSOLE_SIZE := $(CONFIG_CONSOLE_SPI_FLASH_BUFFER_SIZE)
-FMAP_CONSOLE_ENTRY := CONSOLE@$(FMAP_CONSOLE_BASE) $(FMAP_CONSOLE_SIZE)
+FMAP_CONSOLE_ENTRY := CONSOLE@$(call _tohex,$(FMAP_CONSOLE_BASE)) $(call _tohex,$(FMAP_CONSOLE_SIZE))
 FMAP_CURRENT_BASE := $(call int-add, $(FMAP_CONSOLE_BASE) $(FMAP_CONSOLE_SIZE))
 else
 FMAP_CONSOLE_ENTRY :=
@@ -1121,7 +1121,7 @@ endif
 ifeq ($(CONFIG_CACHE_MRC_SETTINGS),y)
 FMAP_MRC_CACHE_BASE := $(call int-align, $(FMAP_CURRENT_BASE), 0x10000)
 FMAP_MRC_CACHE_SIZE := $(CONFIG_MRC_SETTINGS_CACHE_SIZE)
-FMAP_MRC_CACHE_ENTRY := RW_MRC_CACHE@$(FMAP_MRC_CACHE_BASE) $(FMAP_MRC_CACHE_SIZE)
+FMAP_MRC_CACHE_ENTRY := RW_MRC_CACHE@$(call _tohex,$(FMAP_MRC_CACHE_BASE)) $(call _tohex,$(FMAP_MRC_CACHE_SIZE))
 FMAP_CURRENT_BASE := $(call int-add, $(FMAP_MRC_CACHE_BASE) $(FMAP_MRC_CACHE_SIZE))
 else
 FMAP_MRC_CACHE_ENTRY :=
@@ -1130,7 +1130,7 @@ endif
 ifeq ($(CONFIG_SMMSTORE),y)
 FMAP_SMMSTORE_BASE := $(call int-align, $(FMAP_CURRENT_BASE), 0x10000)
 FMAP_SMMSTORE_SIZE := $(CONFIG_SMMSTORE_SIZE)
-FMAP_SMMSTORE_ENTRY := SMMSTORE@$(FMAP_SMMSTORE_BASE) $(FMAP_SMMSTORE_SIZE)
+FMAP_SMMSTORE_ENTRY := SMMSTORE@$(call _tohex,$(FMAP_SMMSTORE_BASE)) $(call _tohex,$(FMAP_SMMSTORE_SIZE))
 FMAP_CURRENT_BASE := $(call int-add, $(FMAP_SMMSTORE_BASE) $(FMAP_SMMSTORE_SIZE))
 else
 FMAP_SMMSTORE_ENTRY :=
@@ -1140,7 +1140,7 @@ ifeq ($(CONFIG_SPD_CACHE_IN_FMAP),y)
 FMAP_SPD_CACHE_BASE := $(call int-align, $(FMAP_CURRENT_BASE), 0x4000)
 FMAP_SPD_CACHE_SIZE := $(call int-multiply, $(CONFIG_DIMM_MAX) $(CONFIG_DIMM_SPD_SIZE))
 FMAP_SPD_CACHE_SIZE := $(call int-align, $(FMAP_SPD_CACHE_SIZE), 0x1000)
-FMAP_SPD_CACHE_ENTRY := $(CONFIG_SPD_CACHE_FMAP_NAME)@$(FMAP_SPD_CACHE_BASE) $(FMAP_SPD_CACHE_SIZE)
+FMAP_SPD_CACHE_ENTRY := $(CONFIG_SPD_CACHE_FMAP_NAME)@$(call _tohex,$(FMAP_SPD_CACHE_BASE)) $(call _tohex,$(FMAP_SPD_CACHE_SIZE))
 FMAP_CURRENT_BASE := $(call int-add, $(FMAP_SPD_CACHE_BASE) $(FMAP_SPD_CACHE_SIZE))
 else
 FMAP_SPD_CACHE_ENTRY :=
@@ -1149,7 +1149,7 @@ endif
 ifeq ($(CONFIG_VPD),y)
 FMAP_VPD_BASE := $(call int-align, $(FMAP_CURRENT_BASE), 0x4000)
 FMAP_VPD_SIZE := $(CONFIG_VPD_FMAP_SIZE)
-FMAP_VPD_ENTRY := $(CONFIG_VPD_FMAP_NAME)@$(FMAP_VPD_BASE) $(FMAP_VPD_SIZE)
+FMAP_VPD_ENTRY := $(CONFIG_VPD_FMAP_NAME)@$(call _tohex,$(FMAP_VPD_BASE)) $(call _tohex,$(FMAP_VPD_SIZE))
 FMAP_CURRENT_BASE := $(call int-add, $(FMAP_VPD_BASE) $(FMAP_VPD_SIZE))
 else
 FMAP_VPD_ENTRY :=
@@ -1158,7 +1158,7 @@ endif
 ifeq ($(CONFIG_INCLUDE_HSPHY_IN_FMAP),y)
 FMAP_HSPHY_FW_BASE := $(call int-align, $(FMAP_CURRENT_BASE), 0x1000)
 FMAP_HSPHY_FW_SIZE := $(CONFIG_HSPHY_FW_MAX_SIZE)
-FMAP_HSPHY_FW_ENTRY := HSPHY_FW@$(FMAP_HSPHY_FW_BASE) $(FMAP_HSPHY_FW_SIZE)
+FMAP_HSPHY_FW_ENTRY := HSPHY_FW@$(call _tohex,$(FMAP_HSPHY_FW_BASE)) $(call _tohex,$(FMAP_HSPHY_FW_SIZE))
 FMAP_CURRENT_BASE := $(call int-add, $(FMAP_HSPHY_FW_BASE) $(FMAP_HSPHY_FW_SIZE))
 else
 FMAP_HSPHY_FW_ENTRY :=
@@ -1200,7 +1200,7 @@ FMAP_CURRENT_BASE := $(call int-add, $(FMAP_FMAP_BASE) $(FMAP_FMAP_SIZE))
 ifeq ($(CONFIG_CONSOLE_SPI_FLASH),y)
 FMAP_CONSOLE_BASE := $(FMAP_CURRENT_BASE)
 FMAP_CONSOLE_SIZE := $(CONFIG_CONSOLE_SPI_FLASH_BUFFER_SIZE)
-FMAP_CONSOLE_ENTRY := CONSOLE@$(FMAP_CONSOLE_BASE) $(FMAP_CONSOLE_SIZE)
+FMAP_CONSOLE_ENTRY := CONSOLE@$(call _tohex,$(FMAP_CONSOLE_BASE)) $(call _tohex,$(FMAP_CONSOLE_SIZE))
 FMAP_CURRENT_BASE := $(call int-add, $(FMAP_CONSOLE_BASE) $(FMAP_CONSOLE_SIZE))
 else
 FMAP_CONSOLE_ENTRY :=
@@ -1213,7 +1213,7 @@ endif
 ifeq ($(CONFIG_CACHE_MRC_SETTINGS),y)
 FMAP_MRC_CACHE_BASE := $(call int-align, $(FMAP_CURRENT_BASE), 0x10000)
 FMAP_MRC_CACHE_SIZE := $(CONFIG_MRC_SETTINGS_CACHE_SIZE)
-FMAP_MRC_CACHE_ENTRY := RW_MRC_CACHE@$(FMAP_MRC_CACHE_BASE) $(FMAP_MRC_CACHE_SIZE)
+FMAP_MRC_CACHE_ENTRY := RW_MRC_CACHE@$(call _tohex,$(FMAP_MRC_CACHE_BASE)) $(call _tohex,$(FMAP_MRC_CACHE_SIZE))
 FMAP_CURRENT_BASE := $(call int-add, $(FMAP_MRC_CACHE_BASE) $(FMAP_MRC_CACHE_SIZE))
 else
 FMAP_MRC_CACHE_ENTRY :=
@@ -1229,10 +1229,10 @@ FMAP_CBFS_SIZE := $(call int-subtract,$(FMAP_BIOS_SIZE) $(FMAP_CBFS_BASE))
 endif # ifeq ($(CONFIG_ARCH_X86),y)
 
 $(obj)/fmap.fmd: $(top)/Makefile.mk $(DEFAULT_FLASHMAP) $(obj)/config.h
-	sed -e "s,##ROM_SIZE##,$(FMAP_ROM_SIZE)," \
-	    -e "s,##BIOS_BASE##,$(FMAP_BIOS_BASE)," \
-	    -e "s,##BIOS_SIZE##,$(FMAP_BIOS_SIZE)," \
-	    -e "s,##FMAP_BASE##,$(FMAP_FMAP_BASE)," \
+	sed -e "s,##ROM_SIZE##,$(call _tohex,$(FMAP_ROM_SIZE))," \
+	    -e "s,##BIOS_BASE##,$(call _tohex,$(FMAP_BIOS_BASE))," \
+	    -e "s,##BIOS_SIZE##,$(call _tohex,$(FMAP_BIOS_SIZE))," \
+	    -e "s,##FMAP_BASE##,$(call _tohex,$(FMAP_FMAP_BASE))," \
 	    -e "s,##FMAP_SIZE##,$(FMAP_FMAP_SIZE)," \
 	    -e "s,##CONSOLE_ENTRY##,$(FMAP_CONSOLE_ENTRY)," \
 	    -e "s,##MRC_CACHE_ENTRY##,$(FMAP_MRC_CACHE_ENTRY)," \
@@ -1240,8 +1240,8 @@ $(obj)/fmap.fmd: $(top)/Makefile.mk $(DEFAULT_FLASHMAP) $(obj)/config.h
 	    -e "s,##SPD_CACHE_ENTRY##,$(FMAP_SPD_CACHE_ENTRY)," \
 	    -e "s,##VPD_ENTRY##,$(FMAP_VPD_ENTRY)," \
 	    -e "s,##HSPHY_FW_ENTRY##,$(FMAP_HSPHY_FW_ENTRY)," \
-	    -e "s,##CBFS_BASE##,$(FMAP_CBFS_BASE)," \
-	    -e "s,##CBFS_SIZE##,$(FMAP_CBFS_SIZE)," \
+	    -e "s,##CBFS_BASE##,$(call _tohex,$(FMAP_CBFS_BASE))," \
+	    -e "s,##CBFS_SIZE##,$(call _tohex,$(FMAP_CBFS_SIZE))," \
 		$(DEFAULT_FLASHMAP) > $@.tmp
 	mv $@.tmp $@
 else # ifeq ($(CONFIG_FMDFILE),)

From a4f067c058982ec8fad4af4189b9d05bf0d4b119 Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Sun, 26 Oct 2025 18:29:40 -0500
Subject: [PATCH 2369/3886] Makefile.mk: Align FMAP COREBOOT region to 4k
 boundary

Ensure FMAP_CBFS_BASE is aligned to 4k (0x1000) to match typical flash
sector boundaries. This allows flashrom to read/write only the COREBOOT
region using the --fmap layout option without extending the boundaries.

Previously, the COREBOOT region would start immediately after the FMAP
region (at FMAP_BASE + 0x200), which is not sector-aligned. Most flash
chips support a minimum 4k sector size, so flashrom would automatically
extend the region boundaries and emit a warning.

This eliminates warnings from flashrom such as:

  Region [0x00c54000 - 0x00c541ff] is not sector aligned!
  Extending end boundaries by 0x00000e00 bytes,
  from 0x00c541ff -> 0x00c54fff

TEST=build/boot google/gladios, update using --fmap and verify no
warnings regarding region alignment.

Change-Id: Ie4963bbef546aa23364bb9c1c347c5eb5bfeaf8e
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89811
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
---
 Makefile.mk | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/Makefile.mk b/Makefile.mk
index abc804e99a..62bce6f91c 100644
--- a/Makefile.mk
+++ b/Makefile.mk
@@ -1176,7 +1176,7 @@ FMAP_FMAP_SIZE := 0x200
 # X86 COREBOOT default cbfs FMAP region
 #
 # position and size of CBFS, relative to BIOS_BASE
-FMAP_CBFS_BASE := $(call int-add, $(FMAP_FMAP_BASE) $(FMAP_FMAP_SIZE))
+FMAP_CBFS_BASE := $(call int-align, $(call int-add, $(FMAP_FMAP_BASE) $(FMAP_FMAP_SIZE)), 0x1000)
 FMAP_CBFS_SIZE := $(call int-subtract, $(FMAP_BIOS_SIZE) $(FMAP_CBFS_BASE))
 
 else # ifeq ($(CONFIG_ARCH_X86),y)

From 641eeca835eb69e3c4eb1df61fa6f1b4ab46ae7a Mon Sep 17 00:00:00 2001
From: Kapil Porwal <kapilporwal@google.com>
Date: Thu, 30 Oct 2025 21:37:59 +0530
Subject: [PATCH 2370/3886] lib/vga_gfx: Fix left-up and right-up orientations

The left-up and right-up orientations were swapped. Fix it to align
with boot logo and depthcharge screen.

BUG=b:406725440
TEST=Verify all 4 panel orientation on Google/Felino.

Change-Id: Ib0d08d4b2aa697129d854c15e081c7765e542060
Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89834
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
---
 src/lib/vga_gfx.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/lib/vga_gfx.c b/src/lib/vga_gfx.c
index 9badc1bf8f..a4d8f62ef4 100644
--- a/src/lib/vga_gfx.c
+++ b/src/lib/vga_gfx.c
@@ -37,7 +37,7 @@ static void set_pixel(int x_logical, int y_logical, int value)
 	 * The physical buffer is always buffer_width x buffer_height.
 	 */
 	switch (current_orientation) {
-	case LB_FB_ORIENTATION_LEFT_UP:
+	case LB_FB_ORIENTATION_RIGHT_UP:
 		/* Logical (x,y) -> Physical (buffer_width-1-y, x) */
 		buffer_x = buffer_width - 1 - y_logical;
 		buffer_y = x_logical;
@@ -50,7 +50,7 @@ static void set_pixel(int x_logical, int y_logical, int value)
 		buffer_x = buffer_width - 1 - x_logical;
 		buffer_y = buffer_height - 1 - y_logical;
 		break;
-	case LB_FB_ORIENTATION_RIGHT_UP:
+	case LB_FB_ORIENTATION_LEFT_UP:
 		/* Logical (x,y) -> Physical (y, buffer_height-1-x) */
 		buffer_x = y_logical;
 		buffer_y = buffer_height - 1 - x_logical;

From 5eafe672e322614dad27153761443ee5836cbd41 Mon Sep 17 00:00:00 2001
From: Alok Agarwal <alok.agarwal@intel.com>
Date: Tue, 23 Sep 2025 13:16:00 +0530
Subject: [PATCH 2371/3886] vc/intel/fsp: Update WCL FSP headers to 3344_03

Update header files for FSP for wildcatlake platform from FSP 3266_02
to FSP 3344_03

Details:
-Update FspmUpd.h: Add below variable
   -Update definition of SerialIoUartDebugAutoFlow
   -Add WREQT, IsWckIdleExitEnabled, LogoPixelHeight , LogoPixelWidth,
    LogoXPosition, LogoYPosition ,VgaGraphicsMode12ImagePtr
-Update FspsUpd.h:
   - Add PchHdaMicPrivacyMode

BUG=b:447530895
TEST=Able to build google/ocelot with the partial header changes

Change-Id: Id5b37434396d4d70f4269a1bf82aa3d6935a9d41
Signed-off-by: Alok Agarwal <alok.agarwal@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89311
Reviewed-by: Pranava Y N <pranavayn@google.com>
Reviewed-by: Avi Uday <aviuday@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 .../intel/fsp/fsp2_0/wildcatlake/FspmUpd.h    | 188 ++++++++++--------
 1 file changed, 109 insertions(+), 79 deletions(-)

diff --git a/src/vendorcode/intel/fsp/fsp2_0/wildcatlake/FspmUpd.h b/src/vendorcode/intel/fsp/fsp2_0/wildcatlake/FspmUpd.h
index 449a25447a..dace75895d 100644
--- a/src/vendorcode/intel/fsp/fsp2_0/wildcatlake/FspmUpd.h
+++ b/src/vendorcode/intel/fsp/fsp2_0/wildcatlake/FspmUpd.h
@@ -57,8 +57,7 @@ typedef struct {
 
 /** Offset 0x0060 - Serial Io Uart Debug Mode
   Select SerialIo Uart Controller mode
-  0:SerialIoUartDisabled, 1:SerialIoUartPci, 2:SerialIoUartHidden, 3:SerialIoUartCom,
-  4:SerialIoUartSkipInit
+  1:SerialIoUartPci, 4:SerialIoUartSkipInit
 **/
   UINT8                       SerialIoUartDebugMode;
 
@@ -941,8 +940,8 @@ typedef struct {
 **/
   UINT8                       DIMMRONT;
 
-/** Offset 0x0260 - Write Drive Strength/Equalization 2D
-  Enables/Disable Write Drive Strength/Equalization 2D
+/** Offset 0x0260 - Write Drive Strength Training
+  Enables/Disable Write Drive Strength Training
   $EN_DIS
 **/
   UINT8                       WRDSEQT;
@@ -1241,9 +1240,11 @@ typedef struct {
 **/
   UINT8                       ChHashInterleaveBit;
 
-/** Offset 0x02BB - Reserved
+/** Offset 0x02BB - Write Equalization Training
+  Enables/Disables Write Equalization Training
+  $EN_DIS
 **/
-  UINT8                       Reserved25;
+  UINT8                       WREQT;
 
 /** Offset 0x02BC - Ch Hash Mask
   Set the BIT(s) to be included in the XOR function. NOTE BIT mask corresponds to
@@ -1253,7 +1254,7 @@ typedef struct {
 
 /** Offset 0x02BE - Reserved
 **/
-  UINT8                       Reserved26;
+  UINT8                       Reserved25;
 
 /** Offset 0x02BF - Throttler CKEMin Timer
   Timer value for CKEMin, range[255;0]. Req'd min of SC_ROUND_T + BYTE_LENGTH (4).
@@ -1332,7 +1333,7 @@ typedef struct {
 
 /** Offset 0x02CB - Reserved
 **/
-  UINT8                       Reserved27[5];
+  UINT8                       Reserved26[5];
 
 /** Offset 0x02D0 - DDR Phy Safe Mode Support
   DdrSafeMode[0]: Basic PM Features, DdrSafeMode[1]: Spine Gating, DdrSafeMode[2]:
@@ -1354,7 +1355,7 @@ typedef struct {
 
 /** Offset 0x02D6 - Reserved
 **/
-  UINT8                       Reserved28[8];
+  UINT8                       Reserved27[8];
 
 /** Offset 0x02DE - RMTLoopCount
   Specifies the Loop Count to be used during Rank Margin Tool Testing. 0 - AUTO
@@ -1390,7 +1391,7 @@ typedef struct {
 
 /** Offset 0x02E7 - Reserved
 **/
-  UINT8                       Reserved29;
+  UINT8                       Reserved28;
 
 /** Offset 0x02E8 - Margin limit check L2
   Margin limit check L2 threshold: <b>100=Default</b>
@@ -1405,7 +1406,7 @@ typedef struct {
 
 /** Offset 0x02EB - Reserved
 **/
-  UINT8                       Reserved30;
+  UINT8                       Reserved29;
 
 /** Offset 0x02EC - LP5 Command Pins Mapping
   BitMask where bits [3:0] are Controller 0 Channel [3:0] and bits [7:4] are Controller
@@ -1427,7 +1428,7 @@ typedef struct {
 
 /** Offset 0x02EF - Reserved
 **/
-  UINT8                       Reserved31[43];
+  UINT8                       Reserved30[43];
 
 /** Offset 0x031A - Read Vref Decap Training*
   Enable/Disable Read Timing Centering Training with SR stress*
@@ -1447,9 +1448,15 @@ typedef struct {
 **/
   UINT8                       Use1p5ReadPostamble;
 
-/** Offset 0x031D - Reserved
+/** Offset 0x031D - IsWckIdleExitEnabled
+  Enables/Disables WCK Idle Exit
+  $EN_DIS
 **/
-  UINT8                       Reserved32[18];
+  UINT8                       IsWckIdleExitEnabled;
+
+/** Offset 0x031E - Reserved
+**/
+  UINT8                       Reserved31[17];
 
 /** Offset 0x032F - Board Type
   MrcBoardType, Options are 0=Mobile/Mobile Halo, 1=Desktop/DT Halo, 5=ULT/ULX/Mobile
@@ -1473,7 +1480,7 @@ typedef struct {
 
 /** Offset 0x0341 - Reserved
 **/
-  UINT8                       Reserved33;
+  UINT8                       Reserved32;
 
 /** Offset 0x0342 - Skip external display device scanning
   Enable: Do not scan for external display device, Disable (Default): Scan external
@@ -1601,7 +1608,7 @@ typedef struct {
 
 /** Offset 0x04D6 - Reserved
 **/
-  UINT8                       Reserved34[2];
+  UINT8                       Reserved33[2];
 
 /** Offset 0x04D8 - DMIC<N> ClkA Pin Muxing (N - DMIC number)
   Determines DMIC<N> ClkA Pin muxing. See  GPIO_*_MUXING_DMIC<N>_CLKA_*
@@ -1616,7 +1623,7 @@ typedef struct {
 
 /** Offset 0x04E1 - Reserved
 **/
-  UINT8                       Reserved35[3];
+  UINT8                       Reserved34[3];
 
 /** Offset 0x04E4 - DMIC<N> Data Pin Muxing
   Determines DMIC<N> Data Pin muxing. See GPIO_*_MUXING_DMIC<N>_DATA_*
@@ -1630,7 +1637,7 @@ typedef struct {
 
 /** Offset 0x04F3 - Reserved
 **/
-  UINT8                       Reserved36[117];
+  UINT8                       Reserved35[117];
 
 /** Offset 0x0568 - Enable HD Audio SoundWire#N Link
   Enable/disable HD Audio SNDW#N link. Muxed with HDA.
@@ -1651,7 +1658,7 @@ typedef struct {
 
 /** Offset 0x056F - Reserved
 **/
-  UINT8                       Reserved37[45];
+  UINT8                       Reserved36[45];
 
 /** Offset 0x059C - iDisplay Audio Codec disconnection
   0: Not disconnected, enumerable, 1: Disconnected SDI, not enumerable.
@@ -1661,7 +1668,7 @@ typedef struct {
 
 /** Offset 0x059D - Reserved
 **/
-  UINT8                       Reserved38[5];
+  UINT8                       Reserved37[5];
 
 /** Offset 0x05A2 - HDA Power/Clock Gating (PGD/CGD)
   Enable/Disable HD Audio Power and Clock Gating(POR: Enable). 0: PLATFORM_POR, 1:
@@ -1672,7 +1679,7 @@ typedef struct {
 
 /** Offset 0x05A3 - Reserved
 **/
-  UINT8                       Reserved39;
+  UINT8                       Reserved38;
 
 /** Offset 0x05A4 - Audio Sub System IDs
   Set default Audio Sub System IDs. If its set to 0 then value from Strap is used.
@@ -1681,7 +1688,7 @@ typedef struct {
 
 /** Offset 0x05A8 - Reserved
 **/
-  UINT8                       Reserved40;
+  UINT8                       Reserved39;
 
 /** Offset 0x05A9 - PCH LPC Enhance the port 8xh decoding
   Original LPC only decodes one byte of port 80h.
@@ -1701,7 +1708,7 @@ typedef struct {
 
 /** Offset 0x05CE - Reserved
 **/
-  UINT8                       Reserved41[46];
+  UINT8                       Reserved40[46];
 
 /** Offset 0x05FC - Enable PCIE RP Mask
   Enable/disable PCIE Root Ports. 0: disable, 1: enable. One bit for each port, bit0
@@ -1717,7 +1724,7 @@ typedef struct {
 
 /** Offset 0x0601 - Reserved
 **/
-  UINT8                       Reserved42[3];
+  UINT8                       Reserved41[3];
 
 /** Offset 0x0604 - Serial Io Uart Debug Mmio Base
   Select SerialIo Uart default MMIO resource in SEC/PEI phase when PcdLpssUartMode
@@ -1794,7 +1801,7 @@ typedef struct {
 
 /** Offset 0x061A - Reserved
 **/
-  UINT8                       Reserved43[2];
+  UINT8                       Reserved42[2];
 
 /** Offset 0x061C - HECI Timeouts
   0: Disable, 1: Enable (Default) timeout check for HECI
@@ -1847,7 +1854,7 @@ typedef struct {
 
 /** Offset 0x0624 - Reserved
 **/
-  UINT8                       Reserved44[2];
+  UINT8                       Reserved43[2];
 
 /** Offset 0x0626 - ISA Serial Base selection
   Select ISA Serial Base address. Default is 0x3F8.
@@ -1868,7 +1875,7 @@ typedef struct {
 
 /** Offset 0x062A - Reserved
 **/
-  UINT8                       Reserved45[26];
+  UINT8                       Reserved44[26];
 
 /** Offset 0x0644 - Enable SMBus
   Enable/disable SMBus controller.
@@ -1889,7 +1896,7 @@ typedef struct {
 
 /** Offset 0x0647 - Reserved
 **/
-  UINT8                       Reserved46;
+  UINT8                       Reserved45;
 
 /** Offset 0x0648 - SMBUS Base Address
   SMBUS Base Address (IO space).
@@ -1904,7 +1911,7 @@ typedef struct {
 
 /** Offset 0x064B - Reserved
 **/
-  UINT8                       Reserved47[13];
+  UINT8                       Reserved46[13];
 
 /** Offset 0x0658 - Smbus dynamic power gating
   Disable or Enable Smbus dynamic power gating.
@@ -1927,7 +1934,7 @@ typedef struct {
 
 /** Offset 0x065B - Reserved
 **/
-  UINT8                       Reserved48[18];
+  UINT8                       Reserved47[18];
 
 /** Offset 0x066D - Over clocking support
   Over clocking support; <b>0: Disable</b>; 1: Enable
@@ -1937,7 +1944,7 @@ typedef struct {
 
 /** Offset 0x066E - Reserved
 **/
-  UINT8                       Reserved49;
+  UINT8                       Reserved48;
 
 /** Offset 0x066F - Realtime Memory Timing
   0(Default): Disabled, 1: Enabled. When enabled, it will allow the system to perform
@@ -2000,7 +2007,7 @@ typedef struct {
 
 /** Offset 0x067B - Reserved
 **/
-  UINT8                       Reserved50[2];
+  UINT8                       Reserved49[2];
 
 /** Offset 0x067D - TjMax Offset
   TjMax offset.Specified value here is clipped by pCode (125 - TjMax Offset) to support
@@ -2010,7 +2017,7 @@ typedef struct {
 
 /** Offset 0x067E - Reserved
 **/
-  UINT8                      Reserved51[48];
+  UINT8                      Reserved50[48];
 
 /** Offset 0x06AE - Core VF Point Offset
   Array used to specifies the Core Voltage Offset applied to the each selected VF
@@ -2032,7 +2039,7 @@ typedef struct {
 
 /** Offset 0x06EA - Reserved
 **/
-  UINT8                       Reserved52[26];
+  UINT8                       Reserved51[26];
 
 /** Offset 0x0704 - Per Core Max Ratio override
   Enable or disable Per Core PState OC supported by writing OCMB 0x1D to program new
@@ -2043,7 +2050,7 @@ typedef struct {
 
 /** Offset 0x0705 - Reserved
 **/
-  UINT8                       Reserved53[25];
+  UINT8                       Reserved52[25];
 
 /** Offset 0x071E - Per Core Current Max Ratio
   Array for the Per Core Max Ratio
@@ -2052,7 +2059,7 @@ typedef struct {
 
 /** Offset 0x0726 - Reserved
 **/
-  UINT8                       Reserved54[8];
+  UINT8                       Reserved53[8];
 
 /** Offset 0x072E - Pvd Ratio Threshold for SOC/CPU die
   Array of Pvd Ratio Threshold for SOC/CPU die is the threshold value for input ratio
@@ -2065,7 +2072,7 @@ typedef struct {
 
 /** Offset 0x072F - Reserved
 **/
-  UINT8                       Reserved55[65];
+  UINT8                       Reserved54[65];
 
 /** Offset 0x0770 - CPU BCLK OC Frequency
   CPU BCLK OC Frequency in KHz units. 98000000Hz = 98MHz <b>0 - Auto</b>. Range is
@@ -2075,7 +2082,7 @@ typedef struct {
 
 /** Offset 0x0774 - Reserved
 **/
-  UINT8                      Reserved56[13];
+  UINT8                      Reserved55[13];
 
 /** Offset 0x0781 - Avx2 Voltage Guardband Scaling Factor
   AVX2 Voltage Guardband Scale factor applied to AVX2 workloads. Range is 0-200 in
@@ -2090,7 +2097,7 @@ typedef struct {
 
 /** Offset 0x0783 - Reserved
 **/
-  UINT8                       Reserved57[5];
+  UINT8                       Reserved56[5];
 
 /** Offset 0x0788 - Enable PCH ISH Controller
   0: Disable, 1: Enable (Default) ISH Controller
@@ -2100,7 +2107,7 @@ typedef struct {
 
 /** Offset 0x0789 - Reserved
 **/
-  UINT8                       Reserved58;
+  UINT8                       Reserved57;
 
 /** Offset 0x078A - BiosSize
   The size of the BIOS region of the IFWI. Used if FspmUpd->FspmConfig.BiosGuard !=
@@ -2135,7 +2142,7 @@ typedef struct {
 
 /** Offset 0x0790 - Reserved
 **/
-  UINT8                       Reserved59[3];
+  UINT8                       Reserved58[3];
 
 /** Offset 0x0793 - MKTME Key-Id Bits Override Enable
   Configure Trust Domain Extension (TDX) to isolate VMs from Virtual-Machine Manager
@@ -2146,7 +2153,7 @@ typedef struct {
 
 /** Offset 0x0794 - Reserved
 **/
-  UINT8                       Reserved60[4];
+  UINT8                       Reserved59[4];
 
 /** Offset 0x0798 - TME Exclude Base Address
   TME Exclude Base Address.
@@ -2160,7 +2167,7 @@ typedef struct {
 
 /** Offset 0x07A8 - Reserved
 **/
-  UINT8                      Reserved61[14];
+  UINT8                      Reserved60[14];
 
 /** Offset 0x07B6 - BIST on Reset
   Enable/Disable BIST (Built-In Self Test) on reset. <b>0: Disable</b>; 1: Enable.
@@ -2170,7 +2177,7 @@ typedef struct {
 
 /** Offset 0x07B7 - Reserved
 **/
-  UINT8                       Reserved62;
+  UINT8                       Reserved61;
 
 /** Offset 0x07B8 - Enable or Disable VMX
   Enable or Disable VMX, When enabled, a VMM can utilize the additional hardware capabilities
@@ -2240,7 +2247,7 @@ typedef struct {
 
 /** Offset 0x07C2 - Reserved
 **/
-  UINT8                       Reserved63[6];
+  UINT8                       Reserved62[6];
 
 /** Offset 0x07C8 - PrmrrSize
   Enable/Disable. 0: Disable, define default value of PrmrrSize , 1: enable
@@ -2268,7 +2275,7 @@ typedef struct {
 
 /** Offset 0x07D2 - Reserved
 **/
-  UINT8                       Reserved64[98];
+  UINT8                       Reserved63[98];
 
 /** Offset 0x0834 - SinitMemorySize
   Enable/Disable. 0: Disable, define default value of SinitMemorySize , 1: enable
@@ -2335,7 +2342,7 @@ typedef struct {
 
 /** Offset 0x086E - Reserved
 **/
-  UINT8                       Reserved65[2];
+  UINT8                       Reserved64[2];
 
 /** Offset 0x0870 - Platform Power Pmax
   PSYS PMax power, defined in 1/8 Watt increments. <b>0 - Auto</b> Specified in 1/8
@@ -2387,7 +2394,7 @@ typedef struct {
 
 /** Offset 0x08BA - Reserved
 **/
-  UINT8                       Reserved66[26];
+  UINT8                       Reserved65[26];
 
 /** Offset 0x08D4 - Icc Max limit
   Voltage Regulator Current Limit (Icc Max). This value represents the Maximum instantaneous
@@ -2399,7 +2406,7 @@ typedef struct {
 
 /** Offset 0x08E0 - Reserved
 **/
-  UINT8                      Reserved67[42];
+  UINT8                      Reserved66[42];
 
 /** Offset 0x090A - Thermal Design Current enable/disable
   Thermal Design Current enable/disable; <b>0: Disable</b>; 1: Enable. [0] for IA,
@@ -2409,7 +2416,7 @@ typedef struct {
 
 /** Offset 0x0910 - Reserved
 **/
-  UINT8                       Reserved68[6];
+  UINT8                       Reserved67[6];
 
 /** Offset 0x0916 - Disable Fast Slew Rate for Deep Package C States for VR domains
   This option needs to be configured to reduce acoustic noise during deeper C states.
@@ -2431,7 +2438,7 @@ typedef struct {
 
 /** Offset 0x0922 - Reserved
 **/
-  UINT8                       Reserved69[6];
+  UINT8                       Reserved68[6];
 
 /** Offset 0x0928 - Thermal Design Current time window
   Auto = 0 is default. Range is from 1ms to 448s. <b>0: Auto</b>. [0] for IA, [1]
@@ -2447,7 +2454,7 @@ typedef struct {
 
 /** Offset 0x0946 - Reserved
 **/
-  UINT8                       Reserved70[2];
+  UINT8                       Reserved69[2];
 
 /** Offset 0x0948 - DLVR RFI Enable
   Enable/Disable DLVR RFI frequency hopping. 0: Disable; <b>1: Enable</b>.
@@ -2467,7 +2474,7 @@ typedef struct {
 
 /** Offset 0x094B - Reserved
 **/
-  UINT8                       Reserved71[11];
+  UINT8                       Reserved70[11];
 
 /** Offset 0x0956 - VR Fast Vmode ICC Limit support
   Voltage Regulator Fast Vmode ICC Limit. A value of 400 = 100A. A value of 0 corresponds
@@ -2492,7 +2499,7 @@ typedef struct {
 
 /** Offset 0x096E - Reserved
 **/
-  UINT8                       Reserved72[28];
+  UINT8                       Reserved71[28];
 
 /** Offset 0x098A - PCH Port80 Route
   Control where the Port 80h cycles are sent, 0: LPC; 1: PCI.
@@ -2509,7 +2516,7 @@ typedef struct {
 
 /** Offset 0x098C - Reserved
 **/
-  UINT8                       Reserved73[4];
+  UINT8                       Reserved72[4];
 
 /** Offset 0x0990 - PMR Size
   Size of PMR memory buffer. 0x400000 for normal boot and 0x200000 for S3 boot
@@ -2535,7 +2542,7 @@ typedef struct {
 
 /** Offset 0x0997 - Reserved
 **/
-  UINT8                       Reserved74;
+  UINT8                       Reserved73;
 
 /** Offset 0x0998 - Base addresses for VT-d function MMIO access
   Base addresses for VT-d MMIO access per VT-d engine
@@ -2544,7 +2551,7 @@ typedef struct {
 
 /** Offset 0x09BC - Reserved
 **/
-  UINT8                       Reserved75[20];
+  UINT8                       Reserved74[20];
 
 /** Offset 0x09D0 - MMIO Size
   Size of MMIO space reserved for devices. 0(Default)=Auto, non-Zero=size in MB
@@ -2559,7 +2566,7 @@ typedef struct {
 
 /** Offset 0x09D4 - Reserved
 **/
-  UINT8                      Reserved76[36];
+  UINT8                      Reserved75[36];
 
 /** Offset 0x09F8 - Enable above 4GB MMIO resource support
   Enable/disable above 4GB MMIO resource support
@@ -2575,7 +2582,7 @@ typedef struct {
 
 /** Offset 0x09FA - Reserved
 **/
-  UINT8                       Reserved77[10];
+  UINT8                       Reserved76[10];
 
 /** Offset 0x0A04 - Enable/Disable CrashLog Device
   Enable or Disable CrashLog/Telemetry Device  0- Disable, <b>1- Enable</b>
@@ -2585,7 +2592,7 @@ typedef struct {
 
 /** Offset 0x0A08 - Reserved
 **/
-  UINT8                      Reserved78[20];
+  UINT8                      Reserved77[20];
 
 /** Offset 0x0A1C - Platform Debug Option
   Enabled Trace active: TraceHub is enabled and trace is active, blocks s0ix.\n
@@ -2602,7 +2609,7 @@ typedef struct {
 
 /** Offset 0x0A1D - Reserved
 **/
-  UINT8                       Reserved79[14];
+  UINT8                       Reserved78[14];
 
 /** Offset 0x0A2B - Program GPIOs for LFP on DDI port-A device
   0=Disabled,1(Default)=eDP, 2=MIPI DSI
@@ -2612,7 +2619,7 @@ typedef struct {
 
 /** Offset 0x0A2C - Reserved
 **/
-  UINT8                      Reserved80[2];
+  UINT8                      Reserved79[2];
 
 /** Offset 0x0A2E - Program GPIOs for LFP on DDI port-B device
   0(Default)=Disabled,1=eDP, 2=MIPI DSI
@@ -2706,7 +2713,7 @@ typedef struct {
 
 /** Offset 0x0A3D - Reserved
 **/
-  UINT8                       Reserved81[3];
+  UINT8                       Reserved80[3];
 
 /** Offset 0x0A40 - Temporary MMIO address for GMADR
   The reference code will use this as Temporary MMIO address space to access GMADR
@@ -2725,7 +2732,7 @@ typedef struct {
 
 /** Offset 0x0A50 - Reserved
 **/
-  UINT8                      Reserved82[2];
+  UINT8                      Reserved81[2];
 
 /** Offset 0x0A52 - Enable/Disable Memory Bandwidth Compression
   0=Disable, 1(Default)=Enable
@@ -2755,7 +2762,7 @@ typedef struct {
 
 /** Offset 0x0A56 - Reserved
 **/
-  UINT8                       Reserved83[2];
+  UINT8                       Reserved82[2];
 
 /** Offset 0x0A58 - Intel Graphics VBT (Video BIOS Table) Size
   Size of Internal Graphics VBT Image
@@ -2764,7 +2771,7 @@ typedef struct {
 
 /** Offset 0x0A5C - Reserved
 **/
-  UINT8                       Reserved84[4];
+  UINT8                       Reserved83[4];
 
 /** Offset 0x0A60 - Graphics Configuration Ptr
   Points to VBT
@@ -2785,14 +2792,37 @@ typedef struct {
 /** Offset 0x0A71 - Control SOL VGA Initialition sequence
   Initialise SOL Init, BIT0 - (0 : Disable VGA Support, 1 : Enable VGA Support),,
   BIT1 - (0 : VGA Text Mode 3, 1 : VGA Graphics Mode 12), BIT2 - (0 : VGA Exit Supported,
-  1: NO VGA Exit)
+  1: NO VGA Exit), BIT3 - (0 : VGA Init During Display Init, 1 - VGA Init During
+  MRC Cold Boot), BIT4 - (0 : Enable Progress Bar, 1 : Disable Progress Bar)
   0:VGA Disable, 1:Mode 3 VGA, 2:Mode 12 VGA
 **/
   UINT8                       VgaInitControl;
 
-/** Offset 0x0A72 - Reserved
+/** Offset 0x0A72 - SOL VGA Graphics Mode 12 LogoPixelHeight
+  Heigh of VGA Graphics Mode 12 Logo
 **/
-  UINT8                      Reserved85[16];
+  UINT16                      LogoPixelHeight;
+
+/** Offset 0x0A74 - SOL VGA Graphics Mode 12 LogoPixelWidth
+  Width of VGA Graphics Mode 12 Logo
+**/
+  UINT16                      LogoPixelWidth;
+
+/** Offset 0x0A76 - SOL VGA Graphics Mode 12 Image X Position
+  X position of Image on Display
+**/
+  UINT16                      LogoXPosition;
+
+/** Offset 0x0A78 - SOL VGA Graphics Mode 12 Image Pointer
+  Points to SOL VGA Graphics Graphics 12 Image, VgaPlanarImage200x58[4][58][25] for
+  58Hx200W as example,
+**/
+  UINT64                      VgaGraphicsMode12ImagePtr;
+
+/** Offset 0x0A80 - SOL VGA Graphics Mode 12 Image Y Position
+  Y position of Image on Display
+**/
+  UINT16                      LogoYPosition;
 
 /** Offset 0x0A82 - TCSS USB HOST (xHCI) Enable
   Set TCSS XHCI. 0:Disabled  1:Enabled - Must be enabled if xDCI is enabled below
@@ -2802,7 +2832,7 @@ typedef struct {
 
 /** Offset 0x0A83 - Reserved
 **/
-  UINT8                       Reserved86[4];
+  UINT8                       Reserved84[4];
 
 /** Offset 0x0A87 - TCSS Type C Port 0
   Set TCSS Type C Port 0 Type, Options are 0=DISABLE, 1=DP_ONLY, 2=NO_TBT, 3=NO_PCIE,
@@ -2834,7 +2864,7 @@ typedef struct {
 
 /** Offset 0x0A8B - Reserved
 **/
-  UINT8                       Reserved87;
+  UINT8                       Reserved85;
 
 /** Offset 0x0A8C - TypeC port GPIO setting
   GPIO Pin number for Type C Aux orientation setting, use the GpioPad that is defined
@@ -2902,7 +2932,7 @@ typedef struct {
 
 /** Offset 0x0AC9 - Reserved
 **/
-  UINT8                       Reserved88;
+  UINT8                       Reserved86;
 
 /** Offset 0x0ACA - DLL Weak Lock Support
   Enables/Disable DLL Weak Lock Support
@@ -2912,7 +2942,7 @@ typedef struct {
 
 /** Offset 0x0ACB - Reserved
 **/
-  UINT8                       Reserved89;
+  UINT8                       Reserved87;
 
 /** Offset 0x0ACC - Rx DQS Delay Comp Support
   Enables/Disable Rx DQS Delay Comp Support
@@ -2922,7 +2952,7 @@ typedef struct {
 
 /** Offset 0x0ACD - Reserved
 **/
-  UINT8                       Reserved90[2];
+  UINT8                       Reserved88[2];
 
 /** Offset 0x0ACF - Mrc Failure On Unsupported Dimm
   Enables/Disable Mrc Failure On Unsupported Dimm
@@ -2932,7 +2962,7 @@ typedef struct {
 
 /** Offset 0x0AD0 - Reserved
 **/
-  UINT8                      Reserved91[4];
+  UINT8                      Reserved89[4];
 
 /** Offset 0x0AD4 - DynamicMemoryBoost
   Enable/Disable Dynamic Memory Boost Feature. Only valid if SpdProfileSelected is
@@ -2950,7 +2980,7 @@ typedef struct {
 
 /** Offset 0x0ADC - Reserved
 **/
-  UINT8                      Reserved92[9];
+  UINT8                      Reserved90[9];
 
 /** Offset 0x0AE5 - Vref Offset
   Offset to be applied to DDRDATACH0_CR_DDRCRDATAOFFSETTRAIN.VrefOffset
@@ -2961,7 +2991,7 @@ typedef struct {
 
 /** Offset 0x0AE6 - Reserved
 **/
-  UINT8                       Reserved93[2];
+  UINT8                       Reserved91[2];
 
 /** Offset 0x0AE8 - tRRSG Delta
   Delay between Read-to-Read commands in the same Bank Group. 0 - Auto. Signed TAT
@@ -3077,7 +3107,7 @@ typedef struct {
 
 /** Offset 0x0AF8 - Reserved
 **/
-  UINT8                       Reserved94[41];
+  UINT8                       Reserved92[41];
 
 /** Offset 0x0B21 - Channel to CKD QCK Mapping
   Specify Channel to CKD QCK Mapping for CH0D0/CH0D1/CH1D0&CH1D1
@@ -3091,7 +3121,7 @@ typedef struct {
 
 /** Offset 0x0B31 - Reserved
 **/
-  UINT8                       Reserved95[55];
+  UINT8                       Reserved93[55];
 } FSP_M_CONFIG;
 
 /** Fsp M UPD Configuration

From 98c7be30ad36994aaa81f36d0217b35903d8d48e Mon Sep 17 00:00:00 2001
From: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
Date: Thu, 30 Oct 2025 11:30:35 +0800
Subject: [PATCH 2372/3886] mb/google/fatcat/var/moonstone: Support new
 schematic changes
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Based on the Moonstone Schematic Proto 2.0 design, disable
Thunderbolt support for TCSS_PORT0 on the MB and TCSS_PORT1
on the DB.

Schematic: Kinmen(ZDQ)_Proto2.0_Moonstone_1014.pdf

BUG＝none
TEST=emerge-fatcat coreboot

Change-Id: Ie9acb9d68234b2d8bfc9392cf89d581de8c54a08
Signed-off-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89819
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 .../google/fatcat/variants/moonstone/overridetree.cb  | 11 -----------
 1 file changed, 11 deletions(-)

diff --git a/src/mainboard/google/fatcat/variants/moonstone/overridetree.cb b/src/mainboard/google/fatcat/variants/moonstone/overridetree.cb
index d2487ac9a9..2e8e44e6c3 100644
--- a/src/mainboard/google/fatcat/variants/moonstone/overridetree.cb
+++ b/src/mainboard/google/fatcat/variants/moonstone/overridetree.cb
@@ -217,10 +217,6 @@ chip soc/intel/pantherlake
 		end
 
 		device ref iaa off end
-		device ref tbt_pcie_rp0 on end
-		device ref tbt_pcie_rp1 on
-			probe IO_PORT USB3C
-		end
 		device ref tbt_pcie_rp2 on
 			probe IO_PORT USB2A2C_HDMI
 		end
@@ -262,13 +258,6 @@ chip soc/intel/pantherlake
 			end
 		end
 
-		device ref tcss_dma0 on
-			chip drivers/intel/usb4/retimer
-				register "dfp[0].power_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B21)"
-				use tcss_usb3_port0 as dfp[0].typec_port
-				device generic 0 on end
-			end
-		end
 		device ref tcss_dma1 on
 			chip drivers/intel/usb4/retimer
 				register "dfp[0].power_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B21)"

From 05c0e165930e98e534e210c22570247e19edc6db Mon Sep 17 00:00:00 2001
From: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Date: Thu, 30 Oct 2025 12:26:53 +0800
Subject: [PATCH 2373/3886] mb/google/ocelot/var/matsu: Update GPIO table

Configure GPIOs and related settings per schematic_20251028.

BUG=b:443612246
TEST=emerge-ocelot coreboot

Change-Id: I59227e435448eb6e362ab45d443fdea2f64a4233
Signed-off-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89815
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Pranava Y N <pranavayn@google.com>
---
 .../google/ocelot/variants/matsu/gpio.c       | 403 ++++++++++--------
 1 file changed, 216 insertions(+), 187 deletions(-)

diff --git a/src/mainboard/google/ocelot/variants/matsu/gpio.c b/src/mainboard/google/ocelot/variants/matsu/gpio.c
index 41c21a1b39..abbf708ffd 100644
--- a/src/mainboard/google/ocelot/variants/matsu/gpio.c
+++ b/src/mainboard/google/ocelot/variants/matsu/gpio.c
@@ -31,34 +31,38 @@ static const struct pad_config gpio_table[] = {
 
 	/* GPP_A08:     M2_GEN4_SSD_RESET_N */
 	PAD_CFG_GPO(GPP_A08, 1, PLTRST),
-	/* GPP_A09:     M.2_WWAN_FCP_OFF_N */
-	PAD_CFG_GPO(GPP_A09, 1, PLTRST),
-	/* GPP_A10:     WWAN_DISABLE_N */
-	PAD_CFG_GPO(GPP_A10, 1, PLTRST),
-	/* GPP_A11:     WLAN_RST_N */
-	PAD_CFG_GPO(GPP_A11, 1, PLTRST),
-	/* GPP_A12:     WIFI_WAKE_N */
-	PAD_CFG_GPI_SCI_LOW(GPP_A12, NONE, DEEP, LEVEL),
-	/* GPP_A13:     PCIE_LNK_DOWN */
-	PAD_CFG_NF_OWNERSHIP(GPP_A13, NONE, DEEP, NF2, ACPI),
-	/* GPP_A15:     CODEC_GPIO_EN */
-	PAD_CFG_GPO(GPP_A15, 1, DEEP),
+	/* GPP_A09:     NC */
+	PAD_NC(GPP_A09, NONE),
+	/* GPP_A10:     NC */
+	PAD_NC(GPP_A10, NONE),
+	/* GPP_A11:     NC */
+	PAD_NC(GPP_A11, NONE),
+	/* GPP_A12:     NC */
+	PAD_NC(GPP_A12, NONE),
+	/* GPP_A13:     NC */
+	PAD_NC(GPP_A13, NONE),
+	/* GPP_A15:     NC */
+	PAD_NC(GPP_A15, NONE),
 
 	/* GPP_B */
 	/* GPP_B00:     USBC_SML_CLK_PD */
 	PAD_CFG_NF(GPP_B00, NONE, DEEP, NF1),
 	/* GPP_B01:     USBC_SML_DATA_PD */
 	PAD_CFG_NF(GPP_B01, NONE, DEEP, NF1),
-	/* GPP_B02:     ISH_I2C0_SDA_SNSR_HDR */
+	/* GPP_B02:     NC */
 	PAD_NC(GPP_B02, NONE),
-	/* GPP_B03:     ISH_I2C0_SCL_SNSR_HDR */
+	/* GPP_B03:     NC */
 	PAD_NC(GPP_B03, NONE),
-	/* GPP_B04:     ISH_GP_0_SNSR_HDR */
+	/* GPP_B04:     NC */
 	PAD_NC(GPP_B04, NONE),
-	/* GPP_B06:     SOC_PDB_CTRL */
-	PAD_CFG_GPO(GPP_B06, 0, DEEP),
-	/* GPP_B08:     ISH_GP_4_SNSR_HDR */
-	PAD_NC(GPP_B08, NONE),
+	/* GPP_B05:     EC_ISH_INT_ODL */
+	PAD_CFG_NF(GPP_B05, NONE, DEEP, NF4),
+	/* GPP_B06:     MEM_STRAP_2 */
+	PAD_CFG_GPI(GPP_B06, NONE, DEEP),
+	/* GPP_B07:     NC */
+	PAD_NC(GPP_B07, NONE),
+	/* GPP_B08:     MEM_STRAP_3 */
+	PAD_CFG_GPI(GPP_B08, NONE, DEEP),
 	/* GPP_B09:     BT_RF_KILL_N */
 	PAD_CFG_GPO(GPP_B09, 1, DEEP),
 	/* GPP_B10:     NC */
@@ -69,30 +73,38 @@ static const struct pad_config gpio_table[] = {
 	PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1),
 	/* GPP_B14:     GPP_B14_DDSP_HPDB */
 	PAD_CFG_NF(GPP_B14, NONE, DEEP, NF2),
-	/* GPP_B16:     COINLESS_MODE_SELECT */
-	PAD_CFG_GPI(GPP_B16, NONE, DEEP),
-	/* GPP_B17:     SPI_TPM_INT_N */
-	PAD_CFG_GPI_APIC_LOCK(GPP_B17, NONE, LEVEL, INVERT, LOCK_CONFIG),
-	/* GPP_B20:     WWAN_RST_N */
-	PAD_CFG_GPO(GPP_B20, 1, PLTRST),
-	/* GPP_B21:     TCP_RETIMER_FORCE_PWR */
-	PAD_CFG_GPO(GPP_B21, 0, DEEP),
-	/* GPP_B24:     ESPI_ALERT0_EC_R_N */
+	/* GPP_B16:     NC */
+	PAD_NC(GPP_B16, NONE),
+	/* GPP_B17:     NC */
+	PAD_NC(GPP_B17, NONE),
+	/* GPP_B18:     ISH_I2C2_SDA_SNSR_HDR */
+	PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_B18, NONE, DEEP, NF1),
+	/* GPP_B19:     ISH_I2C2_SCL_SNSR_HDR */
+	PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_B19, NONE, DEEP, NF1),
+	/* GPP_B20:     NC */
+	PAD_NC(GPP_B20, NONE),
+	/* GPP_B21:     NC */
+	PAD_NC(GPP_B21, NONE),
+	/* GPP_B22:     ISH_GP_5_SNSR_HDR */
+	PAD_CFG_NF(GPP_B22, NONE, DEEP, NF4),
+	/* GPP_B23:     NC */
+	PAD_NC(GPP_B23, NONE),
+	/* GPP_B24:     NC */
 	PAD_NC(GPP_B24, NONE),
-	/* GPP_B25:     None */
+	/* GPP_B25:     NC */
 	PAD_NC(GPP_B25, NONE),
 
 	/* GPP_C */
-	/* GPP_C00:     SPD_SMB_CLK */
-	PAD_CFG_NF(GPP_C00, NONE, DEEP, NF1),
-	/* GPP_C01:     SPD_SMB_DATA */
-	PAD_CFG_NF(GPP_C01, NONE, DEEP, NF1),
+	/* GPP_C00:     MIC_PWR_EN */
+	PAD_CFG_GPO(GPP_C00, 1, DEEP),
+	/* GPP_C01:     EN_FCAM_PWR */
+	PAD_CFG_GPO(GPP_C01, 1, DEEP),
 	/* GPP_C02:     NC */
 	PAD_NC(GPP_C02, NONE),
-	/* GPP_C03:     TCP_LAN_SML0_SCL_R */
-	PAD_CFG_NF(GPP_C03, NONE, DEEP, NF1),
-	/* GPP_C04:     TCP_LAN_SML0_SDA_R */
-	PAD_CFG_NF(GPP_C04, NONE, DEEP, NF1),
+	/* GPP_C03:     NC */
+	PAD_NC(GPP_C03, NONE),
+	/* GPP_C04:     NC */
+	PAD_NC(GPP_C04, NONE),
 	/* GPP_C05:     NC */
 	PAD_NC(GPP_C05, NONE),
 	/* GPP_C06:     NC */
@@ -101,102 +113,106 @@ static const struct pad_config gpio_table[] = {
 	PAD_NC(GPP_C07, NONE),
 	/* GPP_C08:     PM_SLP_S0_N_GPP_CNTRL */
 	PAD_CFG_GPO(GPP_C08, 1, PLTRST),
-	/* GPP_C09:     CLKREQ0_X1_GEN4_M2_WLAN_N */
-	PAD_CFG_NF(GPP_C09, NONE, DEEP, NF1),
+	/* GPP_C09:     NC */
+	PAD_NC(GPP_C09, NONE),
 	/* GPP_C10:     WIFI_RF_KILL_N */
 	PAD_CFG_GPO(GPP_C10, 1, DEEP),
-	/* GPP_C11:     CLKREQ2_X4_GEN4_DT_CEM_SLOT1_N */
-	PAD_CFG_NF(GPP_C11, NONE, DEEP, NF1),
+	/* GPP_C11:     NC */
+	PAD_NC(GPP_C11, NONE),
 	/* GPP_C12:     CLKREQ3_X4_GEN4_M2_SSD_N */
 	PAD_CFG_NF(GPP_C12, NONE, DEEP, NF1),
-	/* GPP_C13:     CLKREQ4_X4_GEN4_DT_CEM_SLOT2_N */
-	PAD_CFG_NF(GPP_C13, NONE, DEEP, NF1),
-	/* GPP_C14:     CLKREQ5_X1_GEN1_GBE_LAN_N */
-	PAD_CFG_NF(GPP_C14, NONE, DEEP, NF1),
-	/* GPP_C15:     FPS_RST_N */
-	PAD_CFG_GPO_LOCK(GPP_C15, 1, LOCK_CONFIG),
-	/* GPP_C16:     MOD_TCSS1_LS_TX_DDC_SCL */
-	PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1),
-	/* GPP_C17:     MOD_TCSS1_LS_RX_DDC_SDA */
-	PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1),
-	/* GPP_C18:     MOD_TCSS2_LS_TX_DDC_SCL */
-	PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1),
-	/* GPP_C19:     MOD_TCSS2_LS_RX_DDC_SDA */
-	PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1),
+	/* GPP_C13:     NC */
+	PAD_NC(GPP_C13, NONE),
+	/* GPP_C14:     NC */
+	PAD_NC(GPP_C14, NONE),
+	/* GPP_C15:     NC */
+	PAD_NC(GPP_C15, NONE),
+	/* GPP_C16:     NC */
+	PAD_NC(GPP_C16, NONE),
+	/* GPP_C17:     NC */
+	PAD_NC(GPP_C17, NONE),
+	/* GPP_C18:     NC */
+	PAD_NC(GPP_C18, NONE),
+	/* GPP_C19:     NC */
+	PAD_NC(GPP_C19, NONE),
 	/* GPP_C22:     DDPB_HDMI_CTRLCLK */
 	PAD_CFG_NF(GPP_C22, NONE, DEEP, NF2),
 	/* GPP_C23:     DDPB_HDMI_CTRLDATA */
 	PAD_CFG_NF(GPP_C23, NONE, DEEP, NF2),
 
 	/* GPP_D */
-	/* GPP_D01:     MOD_TCSS1_TYP_A_VBUS_EN */
-	PAD_CFG_GPO(GPP_D01, 1, DEEP),
+	/* GPP_D01:     NC */
+	PAD_NC(GPP_D01, NONE),
 	/* GPP_D02:     SOC_WP_OD */
-	PAD_CFG_GPO(GPP_D02, 0, DEEP),
-	/* GPP_D03:     X4_SLOT_WAKE_N */
-	PAD_CFG_GPI_SCI_LOW(GPP_D03, NONE, DEEP, LEVEL),
-	/* GPP_D07:     ISH_UART0_RTS_N_SNSR_HDR */
+	PAD_CFG_GPI(GPP_D02, NONE, DEEP),
+	/* GPP_D03:     NC */
+	PAD_NC(GPP_D03, NONE),
+	/* GPP_D05:     ISH_UART0_ECAIC_RXD */
+	PAD_CFG_NF(GPP_D05, NONE, DEEP, NF2),
+	/* GPP_D06:     ISH_UART0_ECAIC_TXD */
+	PAD_CFG_NF(GPP_D06, NONE, DEEP, NF2),
+	/* GPP_D07:     NC */
 	PAD_NC(GPP_D07, NONE),
-	/* GPP_D08:     ISH_UART0_CTS_N_SNSR_HDR */
+	/* GPP_D08:     NC */
 	PAD_NC(GPP_D08, NONE),
-	/* GPP_D09:     I2S_MCLK_HDR */
-	PAD_CFG_NF(GPP_D09, NONE, DEEP, NF1),
-	/* GPP_D10:     HDA_BCLK (HDR) */
-	PAD_CFG_NF(GPP_D10, NONE, DEEP, NF1),
-	/* GPP_D11:     HDA_SYNC (HDR) */
-	PAD_CFG_NF(GPP_D11, NONE, DEEP, NF1),
-	/* GPP_D12:     HDA_SDO (HDR) */
-	PAD_CFG_NF(GPP_D12, NONE, DEEP, NF1),
-	/* GPP_D13:     HDA_SDI0 (HDR) */
-	PAD_CFG_NF(GPP_D13, NONE, DEEP, NF1),
-	/* GPP_D16:     HDA_RST_N (HDR) */
-	PAD_CFG_NF(GPP_D16, NONE, DEEP, NF1),
-	/* GPP_D17:     HDA_SDI1 (HDR) */
-	PAD_CFG_NF(GPP_D17, NONE, DEEP, NF1),
-	/* GPP_D19:     NC */
-	PAD_NC(GPP_D19, NONE),
-	/* GPP_D21:     GPP_D21_UFS_REFCLK_R */
+	/* GPP_D09:     NC */
+	PAD_NC(GPP_D09, NONE),
+	/* GPP_D10:     NC */
+	PAD_NC(GPP_D10, NONE),
+	/* GPP_D11:     NC */
+	PAD_NC(GPP_D11, NONE),
+	/* GPP_D12:     NC */
+	PAD_NC(GPP_D12, NONE),
+	/* GPP_D13:     NC */
+	PAD_NC(GPP_D13, NONE),
+	/* GPP_D16:     DMIC_CLK_A1 */
+	PAD_CFG_NF(GPP_D16, NONE, DEEP, NF3),
+	/* GPP_D17:     DMIC_DATA_1 */
+	PAD_CFG_NF(GPP_D17, NONE, DEEP, NF3),
+	/* GPP_D19:     TCHSCR_RPT_EN */
+	PAD_CFG_GPO(GPP_D19, 0, PLTRST),
+	/* GPP_D21:     GPP_D21_UFS_REFCLK */
 	PAD_CFG_NF(GPP_D21, NONE, DEEP, NF1),
 
 	/* GPP_E */
-	/* GPP_E01:     PM_SLP_DRAM_N */
-	PAD_CFG_NF(GPP_E01, NONE, DEEP, NF2),
+	/* GPP_E01:     NC */
+	PAD_NC(GPP_E01, NONE),
 	/* GPP_E02:     NC */
 	PAD_NC(GPP_E02, NONE),
-	/* GPP_E03:     X4_DT_PCIE_RST_N */
-	PAD_CFG_GPO(GPP_E03, 1, PLTRST),
+	/* GPP_E03:     NC */
+	PAD_NC(GPP_E03, NONE),
 	/* GPP_E05:     GPP_E5_FPS_PWREN */
 	PAD_CFG_GPO(GPP_E05, 1, DEEP),
-	/* GPP_E06:     GPP_E6_PEN_DETECT */
-	PAD_CFG_GPI_TRIG_OWN(GPP_E06, NONE, DEEP, LEVEL, ACPI),
-	/* GPP_E07:     LAN_GPIO_RST_N */
-	PAD_CFG_GPO(GPP_E07, 1, PLTRST),
+	/* GPP_E06:     NC */
+	PAD_NC(GPP_E06, NONE),
+	/* GPP_E07:     NC */
+	PAD_NC(GPP_E07, NONE),
 	/* GPP_E08:     EC_SOC_INT_ODL */
-	PAD_CFG_GPI(GPP_E08, NONE, DEEP),
-	/* GPP_E09:     USB_FP_CONN_1_CONN_2_OC0_N */
+	PAD_CFG_GPI_APIC_LOCK(GPP_E08, NONE, LEVEL, INVERT, LOCK_CONFIG),
+	/* GPP_E09:     USB_A_OC_ODL */
 	PAD_CFG_NF(GPP_E09, NONE, DEEP, NF1),
-	/* GPP_E10:     M2_UFS_DET_SEL_N */
-	PAD_CFG_GPI(GPP_E10, NONE, DEEP),
-	/* GPP_E11:     THC0_SPI1_CLK_TCH_PNL1 */
-	PAD_CFG_NF(GPP_E11, NONE, DEEP, NF3),
-	/* GPP_E12:     THC_I2C0_SCL_TCH_PNL1 */
-	PAD_CFG_NF(GPP_E12, NONE, DEEP, NF3),
-	/* GPP_E13:     THC_I2C0_SDA_TCH_PNL1 */
-	PAD_CFG_NF(GPP_E13, NONE, DEEP, NF3),
-	/* GPP_E14:     THC0_SPI1_IO_2_TCH_PNL1 */
-	PAD_CFG_NF(GPP_E14, NONE, DEEP, NF3),
-	/* GPP_E15:     THC0_SPI1_IO_3_TCH_PNL1 */
-	PAD_CFG_NF(GPP_E15, NONE, DEEP, NF3),
-	/* GPP_E16:     THC0_SPI1_RST_N_TCH_PNL1 */
-	PAD_CFG_NF(GPP_E16, NONE, PLTRST, NF1),
-	/* GPP_E17:     GPP_E17_GSPI0A_CS0 */
-	PAD_CFG_NF(GPP_E17, NONE, DEEP, NF5),
-	/* GPP_E18:     THC0_SPI1_INT_N_TCH_PNL1 */
-	PAD_CFG_NF(GPP_E18, NONE, DEEP, NF3),
-	/* GPP_E19:     FPS_INT_N */
-	PAD_CFG_GPI_IRQ_WAKE(GPP_E19, NONE, PWROK, LEVEL, INVERT),
-	/* GPP_E20:     FPS_FW_UPDATE */
-	PAD_CFG_GPO_LOCK(GPP_E20, 0, LOCK_CONFIG),
+	/* GPP_E10:     NC */
+	PAD_NC(GPP_E10, NONE),
+	/* GPP_E11:     NC */
+	PAD_NC(GPP_E11, NONE),
+	/* GPP_E12:     I2C_TCHPAD_SCL */
+	PAD_CFG_NF(GPP_E12, NONE, DEEP, NF8),
+	/* GPP_E13:     I2C_TCHPAD_SDA */
+	PAD_CFG_NF(GPP_E13, NONE, DEEP, NF8),
+	/* GPP_E14: GSC_SOC_INT_ODL */
+	PAD_CFG_GPI_APIC_LOCK(GPP_E14, NONE, LEVEL, INVERT, LOCK_CONFIG),
+	/* GPP_E15:     NC */
+	PAD_NC(GPP_E15, NONE),
+	/* GPP_E16:     NC */
+	PAD_NC(GPP_E16, NONE),
+	/* GPP_E17:     NC */
+	PAD_NC(GPP_E17, NONE),
+	/* GPP_E18:     TCHPAD_INT_ODL */
+	PAD_CFG_GPI_APIC(GPP_E18, NONE, PLTRST, LEVEL, INVERT),
+	/* GPP_E19:     NC */
+	PAD_NC(GPP_E19, NONE),
+	/* GPP_E20:     NC */
+	PAD_NC(GPP_E20, NONE),
 	/* GPP_E21:     I2C_PMC_PD_INT_N */
 	PAD_CFG_NF(GPP_E21, NONE, DEEP, NF1),
 	/* GPP_E22:     NC */
@@ -215,86 +231,105 @@ static const struct pad_config gpio_table[] = {
 	PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_F04, NONE, DEEP, NF1),
 	/* GPP_F05:     CRF_CLKREQ_R */
 	PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_F05, NONE, DEEP, NF3),
-	/* GPP_F06:     DISC_WLAN_WWAN_COEX3 */
-	PAD_CFG_NF(GPP_F06, NONE, DEEP, NF1),
-	/* GPP_F07:     FUSA_DIAGTEST_EN_HDR */
-	PAD_CFG_NF(GPP_F07, NONE, DEEP, NF2),
-	/* GPP_F08:     TCH_PNL1_PWR_EN */
+	/* GPP_F06:     NC */
+	PAD_NC(GPP_F06, NONE),
+	/* GPP_F07:     NC */
+	PAD_NC(GPP_F07, NONE),
+	/* GPP_F08:     TCHSCR_PNL1_PWR_EN */
 	PAD_CFG_GPO(GPP_F08, 1, PLTRST),
 	/* GPP_F09:     M2_UFS_RST_N */
 	PAD_CFG_GPO(GPP_F09, 1, DEEP),
-	/* GPP_F10:     X4_PCIE_SLOT1_PWR_EN */
-	PAD_CFG_GPO(GPP_F10, 1, PLTRST),
-	/* GPP_F11:     THC1_SPI2_CLK_TCH_PNL2 */
-	PAD_CFG_NF(GPP_F11, NONE, DEEP, NF11),
-	/* GPP_F12:     THC_I2C1_SCL_TCH_PAD */
+	/* GPP_F10:     ISH_ACCEL_MB_INT_L*/
+	PAD_CFG_NF(GPP_F10, NONE, DEEP, NF8),
+	/* GPP_F11:     NC */
+	PAD_NC(GPP_F11, NONE),
+	/* GPP_F12:     TCHSCR_I2C5_SCL */
 	PAD_CFG_NF(GPP_F12, NONE, DEEP, NF8),
-	/* GPP_F13:     THC_I2C1_SDA_TCH_PAD */
+	/* GPP_F13:     TCHSCR_I2C5_SDA */
 	PAD_CFG_NF(GPP_F13, NONE, DEEP, NF8),
-	/* GPP_F14:     GPP_F14_GPSI0A_MOSI */
-	PAD_CFG_NF(GPP_F14, NONE, DEEP, NF8),
-	/* GPP_F15:     GPP_F15_GSPI0A_MISO */
-	PAD_CFG_NF(GPP_F15, NONE, DEEP, NF8),
-	/* GPP_F16:     GPP_F16_GSPI0A_CLK */
-	PAD_CFG_NF(GPP_F16, NONE, DEEP, NF8),
-	/* GPP_F17:     CODEC_IRQ_HDR */
-	PAD_CFG_GPI(GPP_F17, NONE, DEEP),
-	/* GPP_F18:     TCH_PAD_INT_N */
-	PAD_CFG_GPI_APIC_DRIVER(GPP_F18, NONE, PLTRST, EDGE_SINGLE, INVERT),
+	/* GPP_F14:     NC */
+	PAD_NC(GPP_F14, NONE),
+	/* GPP_F15:     NC */
+	PAD_NC(GPP_F15, NONE),
+	/* GPP_F16:     SOC_TCHSCR_INT */
+	PAD_CFG_GPI_APIC(GPP_F16, NONE, PLTRST, LEVEL, NONE),
+	/* GPP_F17:     NC */
+	PAD_NC(GPP_F17, NONE),
+	/* GPP_F18:     TCHSCR_RST_L */
+	PAD_CFG_GPO(GPP_F18, 1, DEEP),
 	/* GPP_F19:     NC */
 	PAD_NC(GPP_F19, NONE),
 	/* GPP_F20:     CSE_EARLY_SW */
 	PAD_CFG_GPI(GPP_F20, NONE, DEEP),
-	/* GPP_F22:     THC1_SPI2_DSYNC */
-	PAD_CFG_NF(GPP_F22, NONE, DEEP, NF3),
+	/* GPP_F22:     NC */
+	PAD_NC(GPP_F22, NONE),
+	/* GPP_F23:     NC */
+	PAD_NC(GPP_F23, NONE),
 
 	/* GPP_H */
 	/* GPP_H00:     NC */
 	PAD_NC(GPP_H00, NONE),
-	/* GPP_H01:     M2_UFS_SLP_N */
-	PAD_CFG_GPO(GPP_H01, 1, DEEP),
-	/* GPP_H02:     DEBUG_TRACE_PNP */
-	PAD_CFG_GPO(GPP_H02, 1, PLTRST),
-	/* GPP_H03:     MIC MUTE */
-	PAD_CFG_NF(GPP_H03, NONE, DEEP, NF1),
-	/* GPP_H04:     CNV_MFUART2_RXD */
-	PAD_CFG_NF(GPP_H04, NONE, DEEP, NF1),
-	/* GPP_H05:     CNV_MFUART2_TXD */
-	PAD_CFG_NF(GPP_H05, NONE, DEEP, NF1),
-	/* GPP_H06:     I2C3_SCL_AUDIO_HDR */
-	PAD_CFG_NF(GPP_H06, NONE, DEEP, NF1),
-	/* GPP_H07:     I2C3_SDA_AUDIO_HDR */
-	PAD_CFG_NF(GPP_H07, NONE, DEEP, NF1),
+	/* GPP_H01:     NC */
+	PAD_NC(GPP_H01, NONE),
+	/* GPP_H02:     NC */
+	PAD_NC(GPP_H02, NONE),
+	/* GPP_H03:     NC */
+	PAD_NC(GPP_H03, NONE),
+	/* GPP_H04:     NC */
+	PAD_NC(GPP_H04, NONE),
+	/* GPP_H05:     NC */
+	PAD_NC(GPP_H05, NONE),
+	/* GPP_H06:     NC */
+	PAD_NC(GPP_H06, NONE),
+	/* GPP_H07:     NC */
+	PAD_NC(GPP_H07, NONE),
 	/* GPP_H08:     SOC_BIOS_LOG_TTK_UART_RX */
 	PAD_CFG_NF(GPP_H08, NONE, DEEP, NF1),
 	/* GPP_H09:     SOC_BIOS_LOG_TTK_UART_TX */
 	PAD_CFG_NF(GPP_H09, NONE, DEEP, NF1),
-	/* GPP_H10:     UART0_BUF_RTS */
-	PAD_CFG_NF(GPP_H10, NONE, DEEP, NF1),
-	/* GPP_H11:     UART0_BUF_CTS */
-	PAD_CFG_NF(GPP_H11, NONE, DEEP, NF1),
-	/* GPP_H13:     CPU_C10_GATE_N_R */
-	PAD_CFG_NF(GPP_H13, NONE, DEEP, NF1),
-	/* GPP_H14:     ISH_I3C1_SDA_SNSR_HDR */
+	/* GPP_H10:     NC */
+	PAD_NC(GPP_H10, NONE),
+	/* GPP_H11:     NC */
+	PAD_NC(GPP_H11, NONE),
+	/* GPP_H13:     NC */
+	PAD_NC(GPP_H13, NONE),
+	/* GPP_H14:     NC */
 	PAD_NC(GPP_H14, NONE),
-	/* GPP_H15:     ISH_I3C1_SCL_SNSR_HDR */
+	/* GPP_H15:     NC */
 	PAD_NC(GPP_H15, NONE),
-	/* GPP_H17:     MIC MUTE LED */
-	PAD_CFG_NF(GPP_H17, NONE, DEEP, NF1),
+	/* GPP_H17:     NC */
+	PAD_NC(GPP_H17, NONE),
 	/* GPP_H18:     GEN4_SSD_PWREN */
 	PAD_CFG_GPO(GPP_H18, 1, DEEP),
-	/* GPP_H19:     I3C0_SDA_HDR */
-	PAD_CFG_NF(GPP_H19, NONE, DEEP, NF2),
-	/* GPP_H20:     I3C0_SCL_HDR */
-	PAD_CFG_NF(GPP_H20, NONE, DEEP, NF2),
-	/* GPP_H21:     I2C1_SDA_TTK_CHROME */
+	/* GPP_H19:     NC */
+	PAD_NC(GPP_H19, NONE),
+	/* GPP_H20:     NC */
+	PAD_NC(GPP_H20, NONE),
+	/* GPP_H21:     SOC_I2C_GSC_SDA */
 	PAD_CFG_NF(GPP_H21, NONE, DEEP, NF1),
-	/* GPP_H22:     I2C1_SCL_TTK_CHROME */
+	/* GPP_H22:     SOC_I2C_GSC_SCL */
 	PAD_CFG_NF(GPP_H22, NONE, DEEP, NF1),
-	/* GPP_H23:     TP */
-	PAD_CFG_NF(GPP_H23, NONE, DEEP, NF1),
-	/* GPP_H24:     TP */
-	PAD_CFG_NF(GPP_H24, NONE, DEEP, NF1),
+	/* GPP_H23:     MEM_STRAP_0 */
+	PAD_CFG_GPI(GPP_H23, NONE, DEEP),
+	/* GPP_H24:     MEM_STRAP_1 */
+	PAD_CFG_GPI(GPP_H24, NONE, DEEP),
+
+	/* GPP_S00:     SNDW3_CLK_CODEC */
+	PAD_CFG_NF(GPP_S00, NONE, DEEP, NF1),
+	/* GPP_S01:     SNDW3_DATA0_CODEC */
+	PAD_CFG_NF(GPP_S01, NONE, DEEP, NF1),
+	/* GPP_S02:     SNDW3_DATA1_CODEC */
+	PAD_CFG_NF(GPP_S02, NONE, DEEP, NF1),
+	/* GPP_S03:     SNDW3_DATA2_CODEC */
+	PAD_CFG_NF(GPP_S03, NONE, DEEP, NF1),
+	/* GPP_S04:	DMIC_CLK_A0 */
+	PAD_CFG_NF(GPP_S04, NONE, DEEP, NF5),
+	/* GPP_S05:	DMIC_DATA_0 */
+	PAD_CFG_NF(GPP_S05, NONE, DEEP, NF5),
+	/* GPP_S06:     NC */
+	PAD_NC(GPP_S06, NONE),
+	/* GPP_S07:     NC */
+	PAD_NC(GPP_S07, NONE),
 
 	/* GPP_V */
 	/* GPP_V00:     PM_BATLOW_N */
@@ -313,14 +348,14 @@ static const struct pad_config gpio_table[] = {
 	PAD_CFG_NF(GPP_V06, NONE, DEEP, NF1),
 	/* GPP_V07:     M.2_BTWIFI_SUS_CLK_LS */
 	PAD_CFG_NF(GPP_V07, NONE, DEEP, NF1),
-	/* GPP_V08:     SLP_WLAN_N */
+	/* GPP_V08:     RSVD */
 	PAD_CFG_NF(GPP_V08, NONE, DEEP, NF1),
 	/* GPP_V09:     PM_SLP_S5_N */
 	PAD_CFG_NF(GPP_V09, NONE, DEEP, NF1),
-	/* GPP_V10:     LANPHYPC_R_N */
-	PAD_CFG_NF(GPP_V10, NONE, DEEP, NF1),
-	/* GPP_V11:     PM_SLP_LAN_N */
-	PAD_CFG_NF(GPP_V11, NONE, DEEP, NF1),
+	/* GPP_V10:     NC */
+	PAD_NC(GPP_V10, NONE),
+	/* GPP_V11:     NC */
+	PAD_NC(GPP_V11, NONE),
 	/* GPP_V12:     WAKE_N */
 	PAD_CFG_NF(GPP_V12, NONE, DEEP, NF1),
 	/* GPP_V13:     GPP_V13_CATERR_N */
@@ -335,30 +370,24 @@ static const struct pad_config gpio_table[] = {
 
 /* Early pad configuration in bootblock */
 static const struct pad_config early_gpio_table[] = {
-	/* GPP_B17:     SPI_TPM_INT_N */
-	PAD_CFG_GPI_APIC(GPP_B17, NONE, DEEP, LEVEL, INVERT),
-	/* GPP_H06: I2C3_SDA_PSS */
-	PAD_CFG_NF(GPP_H06, NONE, DEEP, NF1),
-	/* GPP_H07: I2C3_SCL_PSS */
-	PAD_CFG_NF(GPP_H07, NONE, DEEP, NF1),
+	/* GPP_E14:     GSC_SOC_INT_ODL */
+	PAD_CFG_GPI_APIC(GPP_E14, NONE, PLTRST, LEVEL, INVERT),
 	/* GPP_H08:     SOC_BIOS_LOG_TTK_UART_RX */
 	PAD_CFG_NF(GPP_H08, NONE, DEEP, NF1),
 	/* GPP_H09:     SOC_BIOS_LOG_TTK_UART_TX */
 	PAD_CFG_NF(GPP_H09, NONE, DEEP, NF1),
-	/* GPP_H21:     I2C1_SDA_TTK_CHROME */
+	/* GPP_H21:     SOC_I2C_GSC_SDA */
 	PAD_CFG_NF(GPP_H21, NONE, DEEP, NF1),
-	/* GPP_H22:     I2C1_SCL_TTK_CHROME */
+	/* GPP_H22:     SOC_I2C_GSC_SCL */
 	PAD_CFG_NF(GPP_H22, NONE, DEEP, NF1),
 };
 
 /* Pad configuration in romstage */
 static const struct pad_config romstage_gpio_table[] = {
-	/* GPP_C00:     SPD_SMB_CLK */
-	PAD_CFG_NF(GPP_C00, NONE, DEEP, NF1),
-	/* GPP_C01:     SPD_SMB_DATA */
-	PAD_CFG_NF(GPP_C01, NONE, DEEP, NF1),
-	/* GPP_C15:     FPS_RST_N */
-	PAD_CFG_GPO(GPP_C15, 0, PLTRST),
+	/* GPP_H18:     GEN4_SSD_PWREN */
+	PAD_CFG_GPO(GPP_H18, 1, PLTRST),
+	/* GPP_A08:     M2_GEN4_SSD_RESET_N */
+	PAD_CFG_GPO(GPP_A08, 1, PLTRST),
 };
 
 const struct pad_config *variant_gpio_table(size_t *num)

From 82367b82050ef2bb6539d17a57d704011794a8a9 Mon Sep 17 00:00:00 2001
From: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Date: Thu, 30 Oct 2025 12:28:09 +0800
Subject: [PATCH 2374/3886] mb/google/ocelot/var/matsu: Add overridetree

Add override devicetree per schematic_20251028.

BUG=b:443612246
TEST=emerge-ocelot coreboot

Change-Id: I0b527846ed455f46b9de1cd4bb4987aae85e0456
Signed-off-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89816
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Pranava Y N <pranavayn@google.com>
---
 .../ocelot/variants/matsu/overridetree.cb     | 377 ++++++++++++++++++
 1 file changed, 377 insertions(+)

diff --git a/src/mainboard/google/ocelot/variants/matsu/overridetree.cb b/src/mainboard/google/ocelot/variants/matsu/overridetree.cb
index bfd637ae50..ded15fb279 100644
--- a/src/mainboard/google/ocelot/variants/matsu/overridetree.cb
+++ b/src/mainboard/google/ocelot/variants/matsu/overridetree.cb
@@ -1,5 +1,382 @@
 chip soc/intel/pantherlake
 
+	register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Type C port - various configurations - TCP0
+	register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Type C port - various configurations - TCP1
+	register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # USB Camera
+	register "usb2_ports[3]" = "USB2_PORT_MID(OC0)" # USB3.2 Gen1 x1 Type-A Port
+	register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)" # USB FPS
+	register "usb2_ports[6]" = "USB2_PORT_MID(OC0)" # USB3.2 Gen1 x1 Type-A Port
+
+	register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)" # USB 3.2 Gen1 x1 Type-A Con - # 1
+	register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC0)" # USB 3.2 Gen1 x1 Type-A Con - # 2
+
+	register "tcss_ports[0]" = "TCSS_PORT_DEFAULT(OC_SKIP)"
+	register "tcss_ports[1]" = "TCSS_PORT_DEFAULT(OC_SKIP)"
+
+	register "tcss_cap_policy[0]" = "TCSS_TYPE_C_PORT_FULL_FUN"
+	register "tcss_cap_policy[1]" = "TCSS_TYPE_C_PORT_FULL_FUN"
+
+	# Enable EDP in PortA & HDMI in Port B
+	register "ddi_port_A_config" = "1"
+	register "ddi_port_B_config" = "1"
+	register "ddi_ports_config" = "{
+		[DDI_PORT_A] = DDI_ENABLE_HPD,
+		[DDI_PORT_B] = DDI_ENABLE_HPD | DDI_ENABLE_DDC,
+	}"
+
+	register "serial_io_i2c_mode" = "{
+		[PchSerialIoIndexI2C0]  = PchSerialIoPci,
+		[PchSerialIoIndexI2C1]  = PchSerialIoPci,
+		[PchSerialIoIndexI2C2]  = PchSerialIoDisabled,
+		[PchSerialIoIndexI2C3]  = PchSerialIoDisabled,
+		[PchSerialIoIndexI2C4]  = PchSerialIoPci,
+		[PchSerialIoIndexI2C5]  = PchSerialIoPci,
+	}"
+
+	register "serial_io_gspi_mode" = "{
+		[PchSerialIoIndexGSPI0] = PchSerialIoDisabled,
+		[PchSerialIoIndexGSPI1] = PchSerialIoDisabled,
+		[PchSerialIoIndexGSPI0A] = PchSerialIoDisabled,
+	}"
+
+	# Intel Common SoC Config
+	#+-------------------+---------------------------+
+	#| Field             |  Value                    |
+	#+-------------------+---------------------------+
+	#| I2C1              | TPM(cr50)                 |
+	#| I2C4              | Touchpad                  |
+	#| I2C5              | TouchScreen               |
+	#+-------------------+---------------------------+
+	register "common_soc_config" = "{
+		/* Render OEM footer logo 100px above from the edge */
+		.logo_bottom_margin = 100,
+		.chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT,
+		.i2c[1] = {
+			.speed = I2C_SPEED_FAST,
+			.early_init = 1,
+		},
+		.i2c[4] = {
+			.speed = I2C_SPEED_FAST,
+		},
+		.i2c[5] = {
+			.speed = I2C_SPEED_FAST,
+		},
+	}"
+
 	device domain 0 on
+		device ref igpu on
+			chip drivers/gfx/generic
+				register "device_count" = "4"
+				# DDIA for eDP
+				register "device[0].name" = ""LCD0""
+				register "device[0].type" = "panel"
+				# DDIB for HDMI
+				# If HDMI is not enumerated in the kernel, then no GFX device should be added for DDIB
+				register "device[1].name" = ""DD01""
+				# TCP0 (DP-1) for port C0
+				register "device[2].name" = ""DD02""
+				register "device[2].use_pld" = "true"
+				register "device[2].pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(1, 1))"
+				# TCP1 (DP-2) for port C1
+				register "device[3].name" = ""DD03""
+				register "device[3].use_pld" = "true"
+				register "device[3].pld" = "ACPI_PLD_TYPE_C(LEFT, RIGHT, ACPI_PLD_GROUP(2, 1))"
+				device generic 0 on end
+			end
+		end
+
+		device ref dtt on
+			chip drivers/intel/dptf
+				## sensor information
+				register "options.tsr[0].desc" = ""DDR_SOC""
+				register "options.tsr[1].desc" = ""Ambient""
+				register "options.tsr[2].desc" = ""Charger""
+
+				## Active Policy
+				# FIXME: below values are initial reference values only
+				register "policies.active" = "{
+						[0] = {
+							.target = DPTF_TEMP_SENSOR_0,
+							.thresholds = {
+									TEMP_PCT(70, 97),
+									TEMP_PCT(65, 90),
+									TEMP_PCT(60, 80),
+									TEMP_PCT(55, 75),
+									TEMP_PCT(50, 65),
+									TEMP_PCT(45, 45),
+									TEMP_PCT(43, 30),
+								}
+							},
+						[1] = {
+							.target = DPTF_TEMP_SENSOR_1,
+							.thresholds = {
+									TEMP_PCT(70, 97),
+									TEMP_PCT(65, 90),
+									TEMP_PCT(60, 80),
+									TEMP_PCT(55, 75),
+									TEMP_PCT(50, 65),
+									TEMP_PCT(45, 45),
+									TEMP_PCT(43, 30),
+								}
+							},
+						[2] = {
+							.target = DPTF_TEMP_SENSOR_2,
+							.thresholds = {
+									TEMP_PCT(75, 90),
+									TEMP_PCT(70, 80),
+									TEMP_PCT(65, 70),
+									TEMP_PCT(60, 50),
+								}
+							}
+				}"
+
+				## Passive Policy
+				# TODO: below values are initial reference values only
+				register "policies.passive" = "{
+						[0] = DPTF_PASSIVE(CPU,         CPU,           95, 5000),
+						[1] = DPTF_PASSIVE(CPU,         TEMP_SENSOR_0, 80, 5000),
+						[2] = DPTF_PASSIVE(CPU,         TEMP_SENSOR_1, 80, 5000),
+						[3] = DPTF_PASSIVE(CHARGER,     TEMP_SENSOR_2, 75, 5000),
+				}"
+
+				## Critical Policy
+				# TODO: below values are initial reference values only
+				register "policies.critical" = "{
+						[0] = DPTF_CRITICAL(CPU,          105, SHUTDOWN),
+						[1] = DPTF_CRITICAL(TEMP_SENSOR_0, 85, SHUTDOWN),
+						[2] = DPTF_CRITICAL(TEMP_SENSOR_1, 85, SHUTDOWN),
+						[3] = DPTF_CRITICAL(TEMP_SENSOR_2, 85, SHUTDOWN),
+				}"
+
+				## Power Limits Control
+				register "controls.power_limits" = "{
+						.pl1 = {
+							.min_power = 12000,
+							.max_power = 15000,
+							.time_window_min = 28 * MSECS_PER_SEC,
+							.time_window_max = 32 * MSECS_PER_SEC,
+							.granularity = 200,
+						},
+						.pl2 = {
+							.min_power = 55000,
+							.max_power = 55000,
+							.time_window_min = 28 * MSECS_PER_SEC,
+							.time_window_max = 32 * MSECS_PER_SEC,
+							.granularity = 1000,
+						}
+				}"
+
+				## Charger Performance Control (Control, mA)
+				register "controls.charger_perf" = "{
+						[0] = { 255, 3000 },
+						[1] = {  24, 1500 },
+						[2] = {  16, 1000 },
+						[3] = {   8,  500 }
+				}"
+
+				## Fan Performance Control (Percent, Speed, Noise, Power)
+				register "controls.fan_perf" = "{
+						[0] = {  90, 6700, 220, 2200, },
+						[1] = {  80, 5800, 180, 1800, },
+						[2] = {  70, 5000, 145, 1450, },
+						[3] = {  60, 4900, 115, 1150, },
+						[4] = {  50, 3838,  90,  900, },
+						[5] = {  40, 2904,  55,  550, },
+						[6] = {  30, 2337,  30,  300, },
+						[7] = {  20, 1608,  15,  150, },
+						[8] = {  10,  800,  10,  100, },
+						[9] = {   0,    0,   0,   50, }
+				}"
+
+				## Fan options
+				register "options.fan.fine_grained_control" = "true"
+				register "options.fan.step_size" = "2"
+
+				device generic 0 alias dptf_policy on end
+			end
+		end
+
+		device ref iaa off end
+		device ref tbt_pcie_rp0 on end
+		device ref tbt_pcie_rp1 on end
+		device ref tcss_xhci on
+			chip drivers/usb/acpi
+				device ref tcss_root_hub on
+					chip drivers/usb/acpi
+						register "desc" = ""USB3 Type-C Port C0""
+						register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
+						register "group" = "ACPI_PLD_GROUP(4, 2)"
+						device ref tcss_usb3_port0 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB3 Type-C Port C1""
+						register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
+						register "group" = "ACPI_PLD_GROUP(3, 2)"
+						device ref tcss_usb3_port1 on end
+					end
+				end
+			end
+		end
+
+		device ref ish on
+			chip drivers/intel/ish
+				register "add_acpi_dma_property" = "true"
+				device generic 0 on end
+			end
+		end
+
+		device ref xhci on
+			chip drivers/usb/acpi
+				device ref xhci_root_hub on
+					chip drivers/usb/acpi
+						register "desc" = ""USB2 Type-C Port C0""
+						register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
+						register "group" = "ACPI_PLD_GROUP(1, 1)"
+						device ref usb2_port1 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB2 Type-C Port C1""
+						register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
+						register "group" = "ACPI_PLD_GROUP(2, 1)"
+						device ref usb2_port2 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB2 Camera""
+						register "type" = "UPC_TYPE_INTERNAL"
+						register "has_power_resource" = "true"
+						register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C01)"
+						device ref usb2_port3 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB2 Type-A Port 2""
+						register "type" = "UPC_TYPE_A"
+						register "group" = "ACPI_PLD_GROUP(4, 1)"
+						device ref usb2_port4 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB2 FPMCU""
+						register "type" = "UPC_TYPE_INTERNAL"
+						register "has_power_resource" = "true"
+						register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E05)"
+						device ref usb2_port6 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB2 Type-A Port 1""
+						register "type" = "UPC_TYPE_A"
+						register "group" = "ACPI_PLD_GROUP(3, 1)"
+						device ref usb2_port7 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB3 Type-A Port 1""
+						register "type" = "UPC_TYPE_USB3_A"
+						register "group" = "ACPI_PLD_GROUP(3, 2)"
+						device ref usb3_port1 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB3 Type-A Port 2""
+						register "type" = "UPC_TYPE_USB3_A"
+						register "group" = "ACPI_PLD_GROUP(4, 2)"
+						device ref usb3_port2 on end
+					end
+				end
+			end
+		end
+		#ToDo: Probe using fw_config after decision.
+		device ref ufs on end
+		#ToDo: Probe using fw_config after decision.
+		device ref pcie_rp1 on
+			register "pcie_rp[PCIE_RP(1)]" = "{
+			.clk_src = 3,
+			.clk_req = 3,
+			.flags = PCIE_RP_CLK_REQ_DETECT | PCIE_RP_LTR | PCIE_RP_AER,
+			}"
+			chip soc/intel/common/block/pcie/rtd3
+				register "is_storage" = "true"
+				register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_H18)"
+				register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A08)"
+				register "srcclk_pin" = "3"
+				device generic 0 on end
+			end
+		end # Gen4 M.2 SSD
+
+		device ref cnvi_wifi on
+			chip drivers/wifi/generic
+				register "wake" = "GPE0_PME_B0"
+				register "add_acpi_dma_property" = "true"
+				register "enable_cnvi_ddr_rfim" = "true"
+				use cnvi_bluetooth as bluetooth_companion
+				device generic 0 on end
+			end
+		end # CNVi
+
+		device ref cnvi_bluetooth on end
+
+		# NOTE: i2c0 is function 0; hence it needs to be enabled when any of i2c1-5 is enabled.
+		# TPM device is under i2c1. Therefore, i2c0 needs to be enabled anyways.
+		device ref i2c0 on end
+		device ref i2c1 on
+			chip drivers/i2c/tpm
+				register "hid" = ""GOOG0005""
+				register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_E14_IRQ)"
+				device i2c 50 on end
+			end
+		end
+		device ref i2c4 on
+			chip drivers/i2c/hid
+				register "generic.hid" = ""PIXA2305""
+				register "generic.desc" = ""PIXA Touchpad""
+				register "generic.irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_E18_IRQ)"
+				# NOTE: pmc_gpe0_dw2 is GPP_E in baseboard devicetree.cb.
+				register "generic.wake" = "GPE0_DW2_18"
+				register "generic.detect" = "1"
+				register "hid_desc_reg_offset" = "0x20"
+				device i2c 68 on end
+			end
+			chip drivers/i2c/hid
+				register "generic.hid" = ""PNP0C50""
+				register "generic.desc" = ""Synaptics Touchpad""
+				register "generic.irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_E18_IRQ)"
+				register "generic.wake" = "GPE0_DW2_18"
+				register "generic.detect" = "1"
+				register "hid_desc_reg_offset" = "0x20"
+				device i2c 2c on end
+			end
+		end # I2C4
+		device ref i2c5 on
+			chip drivers/i2c/hid
+				register "generic.hid" = ""ELAN9004""
+				register "generic.desc" = ""ELAN Touchscreen""
+				register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_F16_IRQ)"
+				register "generic.detect" = "1"
+				register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_F18)"
+				register "generic.reset_delay_ms" = "150"
+				register "generic.reset_off_delay_ms" = "2"
+				register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_F08)"
+				register "generic.enable_delay_ms" = "6"
+				register "generic.enable_off_delay_ms" = "1"
+				register "generic.stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D19)"
+				register "generic.stop_off_delay_ms" = "2"
+				register "generic.has_power_resource" = "1"
+				register "generic.use_gpio_for_status" = "true"
+				register "hid_desc_reg_offset" = "0x01"
+				device i2c 0x10 on end
+			end
+		end # I2C5
+		#ToDo: Probe using fw_config after decision.
+		device ref hda on
+			chip drivers/intel/soundwire
+				device generic 0 on
+					chip drivers/soundwire/alc711
+						register "desc" = ""Headset Codec""
+						register "alc711_address.version" = "SOUNDWIRE_VERSION_1_2"
+						register "alc711_address.class" = "MIPI_CLASS_SDCA"
+						register "alc711_address.part_id" = "MIPI_DEV_ID_REALTEK_ALC721"
+						register "disable_clkstop_sm_support" = "true"
+						# SoundWire Link 3 ID 1
+						device generic 3.1 on end
+					end
+				end
+			end
+		end
 	end
 end

From 66f40a86de21a0470f78c69ac6e01051673eb55d Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Thu, 23 Oct 2025 20:36:01 +0100
Subject: [PATCH 2375/3886] ec/starlabs/merlin: Move version offsets to ECDEFs

This is a more suitable place for these definitions as
it contains all other ECRAM offsets.

Change-Id: I12f52b7b27b24c49b6dfc3d4b8fa0718605d2d5f
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89695
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/ec/starlabs/merlin/ec.h                     | 4 ----
 src/ec/starlabs/merlin/variants/glk/ecdefs.h    | 2 ++
 src/ec/starlabs/merlin/variants/glkr/ecdefs.h   | 2 ++
 src/ec/starlabs/merlin/variants/kbl/ecdefs.h    | 2 ++
 src/ec/starlabs/merlin/variants/merlin/ecdefs.h | 2 ++
 5 files changed, 8 insertions(+), 4 deletions(-)

diff --git a/src/ec/starlabs/merlin/ec.h b/src/ec/starlabs/merlin/ec.h
index b22b27917a..39c805cb48 100644
--- a/src/ec/starlabs/merlin/ec.h
+++ b/src/ec/starlabs/merlin/ec.h
@@ -47,10 +47,6 @@
 #define ITE_CHIPID2		0x21	/* Device ID register 2 */
 #define NUVOTON_CHIPID		0x27	/* Device ID register */
 
-/* EC RAM common offsets */
-#define ECRAM_MAJOR_VERSION	0x00
-#define ECRAM_MINOR_VERSION	0x01
-
 /*
  * CMOS Settings
  */
diff --git a/src/ec/starlabs/merlin/variants/glk/ecdefs.h b/src/ec/starlabs/merlin/variants/glk/ecdefs.h
index a9b3025148..ecdff4a5aa 100644
--- a/src/ec/starlabs/merlin/variants/glk/ecdefs.h
+++ b/src/ec/starlabs/merlin/variants/glk/ecdefs.h
@@ -11,6 +11,8 @@
 #define _EC_STARLABS_GLK_EC_DEFS_H
 
 /* EC RAM offsets. */
+#define ECRAM_MAJOR_VERSION	0x00
+#define ECRAM_MINOR_VERSION	0x01
 #define ECRAM_TRACKPAD_STATE	0x14
 #define ECRAM_KBL_STATE		0x19
 #define ECRAM_KBL_BRIGHTNESS	0x18
diff --git a/src/ec/starlabs/merlin/variants/glkr/ecdefs.h b/src/ec/starlabs/merlin/variants/glkr/ecdefs.h
index 028dd5f047..e6dbc2f25e 100644
--- a/src/ec/starlabs/merlin/variants/glkr/ecdefs.h
+++ b/src/ec/starlabs/merlin/variants/glkr/ecdefs.h
@@ -14,6 +14,8 @@
 #define NUVOTON_CHIPID_VAL	0x0004
 
 /* EC RAM offsets. */
+#define ECRAM_MAJOR_VERSION	0x00
+#define ECRAM_MINOR_VERSION	0x01
 #define ECRAM_TRACKPAD_STATE	0x14
 #define ECRAM_KBL_STATE		0x16
 #define ECRAM_KBL_BRIGHTNESS	0x17
diff --git a/src/ec/starlabs/merlin/variants/kbl/ecdefs.h b/src/ec/starlabs/merlin/variants/kbl/ecdefs.h
index 75b83c9bf5..d5dd307eb3 100644
--- a/src/ec/starlabs/merlin/variants/kbl/ecdefs.h
+++ b/src/ec/starlabs/merlin/variants/kbl/ecdefs.h
@@ -11,6 +11,8 @@
 #define _EC_STARLABS_KBL_EC_DEFS_H
 
 /* EC RAM offsets */
+#define ECRAM_MAJOR_VERSION	0x00
+#define ECRAM_MINOR_VERSION	0x01
 #define ECRAM_TRACKPAD_STATE	0x14
 #define ECRAM_KBL_STATE		0x18
 #define ECRAM_KBL_BRIGHTNESS	0x19
diff --git a/src/ec/starlabs/merlin/variants/merlin/ecdefs.h b/src/ec/starlabs/merlin/variants/merlin/ecdefs.h
index b712baaf6a..75c2c62ce3 100644
--- a/src/ec/starlabs/merlin/variants/merlin/ecdefs.h
+++ b/src/ec/starlabs/merlin/variants/merlin/ecdefs.h
@@ -11,6 +11,8 @@
 #define _EC_STARLABS_MERLIN_EC_DEFS_H
 
 /* EC RAM offsets */
+#define ECRAM_MAJOR_VERSION	0x00
+#define ECRAM_MINOR_VERSION	0x01
 #define ECRAM_KBL_BRIGHTNESS	0x09
 #define ECRAM_KBL_TIMEOUT	0x10
 #define ECRAM_KBL_STATE		0x0a

From 1fa24898e2cb98cf2a4ce8e36b70e215043d70c4 Mon Sep 17 00:00:00 2001
From: Kilian Krause <kilian.krause@siemens.com>
Date: Fri, 24 Oct 2025 15:49:35 +0200
Subject: [PATCH 2376/3886] soc/intel/common/block/pcie: Move speed helper to
 pcie_helpers.c

The pcie_speed_control_to_upd() helper function was only available in
aspm.c for PCH root port configuration. However, CPU root ports in
romstage also need to convert PCIE_SPEED_control enum values to FSP
UPD indices.

Move pcie_speed_control_to_upd() from aspm.c to pcie_helpers.c to
make it available in both romstage and ramstage. This allows both
PCH and CPU root port code to use the same conversion logic without
code duplication.

The helper handles the mapping between devicetree enum values and FSP
UPD values using the UPD_INDEX() macro (which subtracts 1):
- SPEED_DEFAULT (0) -> SPEED_AUTO (1) -> UPD_INDEX = 0
- SPEED_AUTO (1) -> UPD_INDEX = 0
- SPEED_GEN1 (2) -> UPD_INDEX = 1
- SPEED_GEN2 (3) -> UPD_INDEX = 2
- SPEED_GEN3 (4) -> UPD_INDEX = 3
- SPEED_GEN4 (5) -> UPD_INDEX = 4

This accounts for the fact that FSP expects 0-based indexing where
0 = Auto, 1 = Gen1, 2 = Gen2, etc.

TEST=Configured PCIE_SPEED_GEN2 for root port on mc_rpl1, booted and
verified with lspci -vv that device is limited to Gen2 speed

Change-Id: I0f70ad4da6f9f9e73b1c05648f0b206d5d61e07d
Signed-off-by: Kilian Krause <kilian.krause@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89763
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
---
 src/soc/intel/common/block/aspm/aspm.c              |  9 ---------
 .../common/block/include/intelblocks/pcie_rp.h      | 13 +++++++++++++
 src/soc/intel/common/block/pcie/pcie_helpers.c      |  9 +++++++++
 3 files changed, 22 insertions(+), 9 deletions(-)

diff --git a/src/soc/intel/common/block/aspm/aspm.c b/src/soc/intel/common/block/aspm/aspm.c
index 595de84d0d..56da3cb91e 100644
--- a/src/soc/intel/common/block/aspm/aspm.c
+++ b/src/soc/intel/common/block/aspm/aspm.c
@@ -74,15 +74,6 @@ static unsigned int l1ss_control_to_upd(enum L1_substates_control l1_substates_c
 	return UPD_INDEX(l1_substates_control);
 }
 
-static unsigned int pcie_speed_control_to_upd(enum PCIE_SPEED_control pcie_speed_control)
-{
-	/* Use auto unless overwritten */
-	if (!pcie_speed_control)
-		return UPD_INDEX(SPEED_AUTO);
-
-	return UPD_INDEX(pcie_speed_control);
-}
-
 void configure_pch_rp_power_management(FSP_S_CONFIG *s_cfg,
 					      const struct pcie_rp_config *rp_cfg,
 					      unsigned int index)
diff --git a/src/soc/intel/common/block/include/intelblocks/pcie_rp.h b/src/soc/intel/common/block/include/intelblocks/pcie_rp.h
index 6ff07cf3b2..68137490b9 100644
--- a/src/soc/intel/common/block/include/intelblocks/pcie_rp.h
+++ b/src/soc/intel/common/block/include/intelblocks/pcie_rp.h
@@ -149,6 +149,19 @@ void pcie_rp_update_devicetree(const struct pcie_rp_group *groups);
  */
 uint32_t pcie_rp_enable_mask(const struct pcie_rp_group *groups);
 
+/*
+ * Convert PCIe speed control setting to UPD index format.
+ *
+ * Takes a PCIE_SPEED_control enum value and converts it to the corresponding
+ * UPD (Unit Parameter Data) index required by the firmware interface.
+ *
+ * If pcie_speed_control is 0 (uninitialized/default), the function returns
+ * the UPD index for SPEED_AUTO, enabling automatic speed negotiation.
+ * Otherwise, it returns the UPD index corresponding to the specified speed
+ * control value.
+ */
+unsigned int pcie_speed_control_to_upd(enum PCIE_SPEED_control pcie_speed_control);
+
 /* Get PCH root port groups */
 const struct pcie_rp_group *soc_get_pch_rp_groups(void);
 
diff --git a/src/soc/intel/common/block/pcie/pcie_helpers.c b/src/soc/intel/common/block/pcie/pcie_helpers.c
index 00bef42a79..697d1c7520 100644
--- a/src/soc/intel/common/block/pcie/pcie_helpers.c
+++ b/src/soc/intel/common/block/pcie/pcie_helpers.c
@@ -39,3 +39,12 @@ uint32_t pcie_rp_enable_mask(const struct pcie_rp_group *const groups)
 
 	return mask;
 }
+
+unsigned int pcie_speed_control_to_upd(enum PCIE_SPEED_control pcie_speed_control)
+{
+	/* Use auto unless overwritten */
+	if (!pcie_speed_control)
+		return UPD_INDEX(SPEED_AUTO);
+
+	return UPD_INDEX(pcie_speed_control);
+}

From e167e568832304ef44eab37bb281f5f3c5ecb28f Mon Sep 17 00:00:00 2001
From: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Date: Thu, 30 Oct 2025 10:51:54 +0800
Subject: [PATCH 2377/3886] mb/google/nissa/var/yavilla: Add stop pin for G2
 touchscreen

Add stop pin control for G2 touchscreen.

BUG=b:456578327
TEST=build and verified Touchscreen work normally.

Change-Id: I0581fffdc2ec16a1c36b2e716b0fae27bad465ee
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89813
Reviewed-by: Derek Huang <derekhuang@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
---
 src/mainboard/google/brya/variants/yavilla/overridetree.cb | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/src/mainboard/google/brya/variants/yavilla/overridetree.cb b/src/mainboard/google/brya/variants/yavilla/overridetree.cb
index 4935a3a65d..b57ff9abd6 100644
--- a/src/mainboard/google/brya/variants/yavilla/overridetree.cb
+++ b/src/mainboard/google/brya/variants/yavilla/overridetree.cb
@@ -330,6 +330,9 @@ chip soc/intel/alderlake
 				register "generic.detect" = "1"
 				register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C1)"
 				register "generic.reset_delay_ms" = "50"
+				register "generic.stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C6)"
+				register "generic.stop_delay_ms" = "55"
+				register "generic.stop_off_delay_ms" = "5"
 				register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C0)"
 				register "generic.enable_delay_ms" = "1"
 				register "generic.has_power_resource" = "1"

From 111da2557adcc65b74ad47a820cde84651a3aebb Mon Sep 17 00:00:00 2001
From: Subrata Banik <subratabanik@google.com>
Date: Thu, 30 Oct 2025 11:40:45 +0530
Subject: [PATCH 2378/3886] mb/google/fatcat: Preserve VGPIO GPE for THC wake
 on touch

The Touch Host Controller (THC) requires its dedicated VGPIO pins to
remain enabled as a General Purpose Event (GPE) source for the system
to wake up on touch events.

This change introduces override_tier_1_gpio_chip_config to explicitly
check the thc_wake_on_touch status for each enabled THC interface.
If any wake-on-touch functionality is active, the Tier-1 GPE
configuration (pmc_gpe0_dw0) is overridden to ensure the GPP_VGPIO
bank is included.

This guarantees that the VGPIO pins dedicated to THC are always
monitored as a wake source when required by the platform
configuration.

BUG=b:414614106
TEST=Able to build and boot google/fatcat.

Change-Id: Ia1165c167850f5d66a8c5a85e3ec64f80e7a40da
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89817
Reviewed-by: Huang, Cliff <cliff.huang@intel.com>
Reviewed-by: Pranava Y N <pranavayn@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/google/fatcat/mainboard.c | 14 ++++++++++++++
 1 file changed, 14 insertions(+)

diff --git a/src/mainboard/google/fatcat/mainboard.c b/src/mainboard/google/fatcat/mainboard.c
index 5bd9892480..1ea606a6f1 100644
--- a/src/mainboard/google/fatcat/mainboard.c
+++ b/src/mainboard/google/fatcat/mainboard.c
@@ -16,9 +16,23 @@ void __weak fw_config_gpio_padbased_override(struct pad_config *padbased_table)
 	/* default implementation does nothing */
 }
 
+static void override_tier_1_gpio_chip_config(struct soc_intel_pantherlake_config *config)
+{
+	/* Override the Tier-1 GPIO to ensure VGPIO dedicated for THC remains as wake source */
+	for (size_t i = 0; i < NUM_THC; i++) {
+		if (is_devfn_enabled(_PCI_DEVFN(THC, i)) && config->thc_wake_on_touch[i]) {
+			/* Atleast one THC interface is enabled, hence, skip checking further */
+			config->pmc_gpe0_dw0 = GPP_VGPIO;
+			break;
+		}
+	}
+}
+
 void mainboard_update_soc_chip_config(struct soc_intel_pantherlake_config *config)
 {
 	variant_update_soc_chip_config(config);
+
+	override_tier_1_gpio_chip_config(config);
 }
 
 void __weak variant_update_soc_chip_config(struct soc_intel_pantherlake_config *config)

From 4ea33e5ffa82e23849e6f5d7c5462e5aad7f7fd3 Mon Sep 17 00:00:00 2001
From: Subrata Banik <subratabanik@google.com>
Date: Thu, 30 Oct 2025 11:43:53 +0530
Subject: [PATCH 2379/3886] mb/google/fatcat/var/lapis: Enable THC HID over I2C
 mode

Configure the Touch Host Controller (THC) devices 0 and 1 on the
Fatcat/Lapis variant to use HID over I2C mode.

This change explicitly sets the thc_mode[0] and thc_mode[1] registers
to THC_HID_I2C_MODE in overridetree.cb. This is necessary to correctly
initialize the THC for devices like touchpads or touchscreens that
communicate using this protocol.

BUG=b:455442712
TEST=Able to build and boot google/lapis with functional touchpad.

Change-Id: I7c9a62afab396cb38775eaa5e96f2dc7ed773216
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89818
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Pranava Y N <pranavayn@google.com>
Reviewed-by: Huang, Cliff <cliff.huang@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/google/fatcat/variants/lapis/overridetree.cb | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/src/mainboard/google/fatcat/variants/lapis/overridetree.cb b/src/mainboard/google/fatcat/variants/lapis/overridetree.cb
index 8c98633a79..d9ce5bc352 100644
--- a/src/mainboard/google/fatcat/variants/lapis/overridetree.cb
+++ b/src/mainboard/google/fatcat/variants/lapis/overridetree.cb
@@ -406,6 +406,7 @@ chip soc/intel/pantherlake
 
 		device ref thc0 on
 			register "thc_wake_on_touch[0]" = "true"
+			register "thc_mode[0]" = "THC_HID_I2C_MODE"
 			# THC0 is function 0; hence it needs to be enabled when THC1 is to be enabled.
 			chip drivers/intel/touch
 				register "name" = "INTEL_THC0_NAME"
@@ -424,6 +425,7 @@ chip soc/intel/pantherlake
 		end #Touchpad
 		device ref thc1 on
 			register "thc_wake_on_touch[1]" = "true"
+			register "thc_mode[1]" = "THC_HID_I2C_MODE"
 			chip drivers/intel/touch
 				register "name" = "INTEL_THC1_NAME"
 				register "mode" = "THC_HID_I2C_MODE"

From 65dc0bdd7eb98ba0fab90dc6a04f9574ec07b999 Mon Sep 17 00:00:00 2001
From: Subrata Banik <subratabanik@google.com>
Date: Thu, 30 Oct 2025 22:43:27 +0530
Subject: [PATCH 2380/3886] mainboard/fatcat/lapis: Override PMC GPE
 configuration

Set the GPE0 registers (DW0, DW1, and DW2) to configure General
Purpose Events (GPEs) for the Lapis variant. This configures
GPP_VGPIO, GPP_F, and GPP_E as the Tier-1 PMC GPIO groups.

This patch ensures the variant can override the default baseboard
(fatcat) GPE settings, which may not align with the variant's
(aka lapis) hardware.

BUG=b:414614106
TEST=Able to override PMC GPEs as per google/lapis configuration.

Change-Id: Icd191d5265619ebfbf7f8dabb39a91a6517dfbd8
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89835
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Pranava Y N <pranavayn@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: hualin wei <weihualin@huaqin.corp-partner.google.com>
---
 src/mainboard/google/fatcat/variants/lapis/overridetree.cb | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/src/mainboard/google/fatcat/variants/lapis/overridetree.cb b/src/mainboard/google/fatcat/variants/lapis/overridetree.cb
index d9ce5bc352..c686dd4da2 100644
--- a/src/mainboard/google/fatcat/variants/lapis/overridetree.cb
+++ b/src/mainboard/google/fatcat/variants/lapis/overridetree.cb
@@ -37,6 +37,10 @@ fw_config
 end
 
 chip soc/intel/pantherlake
+	# GPE configuration override
+	register "pmc_gpe0_dw0" = "GPP_VGPIO"
+	register "pmc_gpe0_dw1" = "GPP_F"
+	register "pmc_gpe0_dw2" = "GPP_E"
 
 	register "power_limits_config[PTL_CORE_1]" = "{
 		.tdp_pl1_override = 15,

From bc475414c7c268be28e2dd3507a78345414a764f Mon Sep 17 00:00:00 2001
From: Yidi Lin <yidilin@google.com>
Date: Thu, 30 Oct 2025 10:47:54 +0800
Subject: [PATCH 2381/3886] MAINTAINERS: Add Chen-Tsung Hsieh for MediaTek
 platforms

Change-Id: I16993969b0d17fe4957cb00ff2f3e7e6fa2e8f49
Signed-off-by: Yidi Lin <yidilin@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89812
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Chen-Tsung Hsieh <chentsung@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
---
 MAINTAINERS | 1 +
 1 file changed, 1 insertion(+)

diff --git a/MAINTAINERS b/MAINTAINERS
index 7ad94bd567..a676f72b99 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -395,6 +395,7 @@ F:	src/mainboard/google/guybrush/
 F:	src/mainboard/google/skyrim/
 
 GOOGLE MEDIATEK-BASED MAINBOARDS
+M:	Chen-Tsung Hsieh <chentsung@google.com>
 M:	Hung-Te Lin <hungte@chromium.org>
 M:	Yu-Ping Wu <yupingso@google.com>
 M:	Yidi Lin <yidilin@google.com>

From 7afd7318493032a3c1cb8116f5ec231d364a68fb Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Wed, 15 Oct 2025 16:22:44 -0500
Subject: [PATCH 2382/3886] ec/google/chromeec/acpi: Fix long battery string
 reporting for Windows

`ToString(byte x)` is undefined behavior per the ACPI spec, which
causes Windows to discard the battery device status entirely.

Fix this and improve performance of the BRSX method by using an array
to store the characters read, calling ToString() only once at the end.

TEST=build/boot Win11 and Linux on google/rex, verify battery status
reported properly under both OSes.

Change-Id: I4e5aea3b2763a3c4433abe95c3a41d218fcd06c1
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89602
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Reviewed-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
---
 src/ec/google/chromeec/acpi/battery.asl | 14 ++++++++++----
 1 file changed, 10 insertions(+), 4 deletions(-)

diff --git a/src/ec/google/chromeec/acpi/battery.asl b/src/ec/google/chromeec/acpi/battery.asl
index 7d5208835a..41b77861a5 100644
--- a/src/ec/google/chromeec/acpi/battery.asl
+++ b/src/ec/google/chromeec/acpi/battery.asl
@@ -152,13 +152,19 @@ Method(BRSX, 1, Serialized)
 		// Read to end of string, or up to a reasonable maximum length. Reads of
 		// BSRF consume bytes from the FIFO, so take care to read it only once
 		// per byte of data.
-		Local0 = ""
-		Local1 = BSRF
-		While (Local1 != 0 && SizeOf (Local0) < 32)
+		Local0 = Buffer (33){}
+		For (Local2 = 0, Local2 < SizeOf(Local0) - 1, Local2++)
 		{
-			Local0 = Concatenate (Local0, ToString (Local1))
 			Local1 = BSRF
+			If (Local1 == 0)
+			{
+				Break
+			}
+			Local0[Local2] = Local1
 		}
+
+		Local0[Local2] = 0
+		Local0 = ToString(Local0)
 	}
 
 	// Store the result in the cache

From c3b5c8723ed6af01db333c70f810c87817e67f9f Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Sun, 19 Oct 2025 17:26:07 -0500
Subject: [PATCH 2383/3886] ec/google/chromeec: Add function to determine
 keyboard backlight presence

Add a new function google_chromeec_has_kbbacklight() to check if the EC
has keyboard backlight capability. The function first tries the EC
feature flag (EC_FEATURE_PWM_KEYB), falling back to a read test if
unavailable. The EC command ec_cmd_pwm_get_keyboard_backlight() returns
-1 if the device does not have a keyboard backlight.

This function will be used in subsequent commits to guard setting the
keyboard backlight at boot and the visiblity of a CFR option setting.

TEST=tested hooked up to a CFR option to set the keyboard backlight
at boot, with visibility controlled by backlight presence, on a
range of Chromebooks with and without keyboard backlight support.

Change-Id: I74daf7a63f06239d2ba3915221555af494a9340f
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89827
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/ec/google/chromeec/ec.c | 25 +++++++++++++++++++++++++
 src/ec/google/chromeec/ec.h |  1 +
 2 files changed, 26 insertions(+)

diff --git a/src/ec/google/chromeec/ec.c b/src/ec/google/chromeec/ec.c
index acba0dfefb..fb8a014d0a 100644
--- a/src/ec/google/chromeec/ec.c
+++ b/src/ec/google/chromeec/ec.c
@@ -107,6 +107,31 @@ int google_chromeec_kbbacklight(int percent)
 	return 0;
 }
 
+bool google_chromeec_has_kbbacklight(void)
+{
+	/* Try the feature flag (most reliable for modern ECs) */
+	int feature_check = google_chromeec_check_feature(EC_FEATURE_PWM_KEYB);
+
+	if (feature_check > 0) {
+		printk(BIOS_DEBUG, "Chrome EC: Keyboard backlight detected (feature flag)\n");
+		return true;
+	} else if (feature_check == 0) {
+		printk(BIOS_DEBUG, "Chrome EC: No keyboard backlight (feature flag)\n");
+		return false;
+	}
+
+	printk(BIOS_DEBUG, "Chrome EC: Feature flag unavailable, testing backlight read\n");
+	struct ec_response_pwm_get_keyboard_backlight resp = {};
+
+	if (ec_cmd_pwm_get_keyboard_backlight(PLAT_EC, &resp) == 0) {
+		printk(BIOS_DEBUG, "Chrome EC: Keyboard backlight detected (read test)\n");
+		return true;
+	} else {
+		printk(BIOS_DEBUG, "Chrome EC: No keyboard backlight (read test)\n");
+		return false;
+	}
+}
+
 void google_chromeec_post(uint8_t postcode)
 {
 	/* backlight is a percent. postcode is a uint8_t.
diff --git a/src/ec/google/chromeec/ec.h b/src/ec/google/chromeec/ec.h
index febef6c1ab..3c77eeb459 100644
--- a/src/ec/google/chromeec/ec.h
+++ b/src/ec/google/chromeec/ec.h
@@ -80,6 +80,7 @@ int google_chromeec_set_sku_id(uint32_t skuid);
 uint64_t  google_chromeec_get_events_b(void);
 int google_chromeec_clear_events_b(uint64_t mask);
 int google_chromeec_kbbacklight(int percent);
+bool google_chromeec_has_kbbacklight(void);
 void google_chromeec_post(uint8_t postcode);
 uint8_t google_chromeec_get_switches(void);
 bool google_chromeec_get_ap_watchdog_flag(void);

From 3d41ac370d5e869bbd984ad2104a1de448df76ed Mon Sep 17 00:00:00 2001
From: Maximilian Brune <maximilian.brune@9elements.com>
Date: Fri, 17 Oct 2025 00:35:15 +0200
Subject: [PATCH 2384/3886] payloads/external/U-Boot/Makefile: Remove
 conditional

Apparently no one ever build this using UBOOT_MASTER, because it is
missing the "cd $(project_dir)" before git fetch.

I have also no idea what the git show was originally supposed to do.
So just remove them both and move on.

Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: I2f26660131ce91420a951fb33ac0eef89371745d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89615
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
---
 payloads/external/U-Boot/Makefile | 11 +----------
 1 file changed, 1 insertion(+), 10 deletions(-)

diff --git a/payloads/external/U-Boot/Makefile b/payloads/external/U-Boot/Makefile
index ea850b31ee..c588025616 100644
--- a/payloads/external/U-Boot/Makefile
+++ b/payloads/external/U-Boot/Makefile
@@ -26,17 +26,8 @@ $(project_dir):
 	git clone $(project_git_repo) -b $(TAG-y) $(project_dir)
 
 fetch: $(project_dir)
-ifeq ($(CONFIG_UBOOT_MASTER),y)
 	echo "    Fetching new commits from the $(project_name) git repo"
-	git fetch
-
-	#master doesn't get a file, so it's continuously updated
-	rm -f $(STABLE_COMMIT_ID)
-else
-	cd $(project_dir); git show $(TAG-y) >/dev/null 2>&1 ;	if [ $$? -ne 0 ]; \
-	then echo "    Fetching new commits from the $(project_name) git repo"; git fetch; fi
-	touch $(STABLE_COMMIT_ID)
-endif
+	cd $(project_dir) && git fetch
 
 checkout: fetch
 	echo "    Checking out $(project_name) revision $(TAG-y)"

From 4b50bc9e5fd7c8ccca6ea8111846eff0db43bf57 Mon Sep 17 00:00:00 2001
From: Maximilian Brune <maximilian.brune@9elements.com>
Date: Fri, 17 Oct 2025 00:35:15 +0200
Subject: [PATCH 2385/3886] payloads/external/U-Boot/Makefile: Add custom repo
 and tag

Adds the abillity to use a custom u-boot repo and a custom branch.

Change-Id: I15df8a41d3d94ca0559abc964792035651b3d8b2
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89616
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 payloads/external/Makefile.mk     |  5 +++--
 payloads/external/U-Boot/Kconfig  | 20 +++++++-------------
 payloads/external/U-Boot/Makefile | 14 +++++---------
 3 files changed, 15 insertions(+), 24 deletions(-)

diff --git a/payloads/external/Makefile.mk b/payloads/external/Makefile.mk
index 4c93298fac..0ba9a02c27 100644
--- a/payloads/external/Makefile.mk
+++ b/payloads/external/Makefile.mk
@@ -298,8 +298,9 @@ $(GRUB_TARGET_PATH): grub2
 payloads/external/U-Boot/build/u-boot.bin u-boot: $(DOTCONFIG)
 	$(MAKE) -C payloads/external/U-Boot \
 			STABLE_COMMIT_ID=$(CONFIG_UBOOT_STABLE_COMMIT_ID) \
-			CONFIG_UBOOT_MASTER=$(CONFIG_UBOOT_MASTER) \
-			CONFIG_UBOOT_STABLE=$(CONFIG_UBOOT_STABLE)
+			CONFIG_UBOOT_STABLE=$(CONFIG_UBOOT_STABLE) \
+			CONFIG_UBOOT_BRANCH_OR_TAG=$(CONFIG_UBOOT_BRANCH_OR_TAG) \
+			CONFIG_UBOOT_REPO_URL=$(CONFIG_UBOOT_REPO_URL)
 
 # TINT
 
diff --git a/payloads/external/U-Boot/Kconfig b/payloads/external/U-Boot/Kconfig
index 28bc72765d..3f4122b39e 100644
--- a/payloads/external/U-Boot/Kconfig
+++ b/payloads/external/U-Boot/Kconfig
@@ -7,25 +7,19 @@ config PAYLOAD_SPECIFIC_OPTIONS
 	select PAYLOAD_IS_FLAT_BINARY
 	select WANT_LINEAR_FRAMEBUFFER
 
-config UBOOT_STABLE_COMMIT_ID
-	string
-	default "v2025.07"
-
-choice
-	prompt "U-Boot version"
-	default UBOOT_STABLE
-
 config UBOOT_STABLE
 	bool "v2025.07"
 	help
 	  Stable U-Boot version
 
-config UBOOT_MASTER
-	bool "master"
-	help
-	  Newest U-Boot version
+config UBOOT_BRANCH_OR_TAG
+	string "branch/tag to use for u-boot payload"
+	default "v2025.07" if UBOOT_STABLE
+	default "master"
 
-endchoice
+config UBOOT_REPO_URL
+	string "URL to uboot repository"
+	default "http://github.com/u-boot/u-boot/"
 
 config PAYLOAD_CONFIGFILE
 	string "U-Boot config file"
diff --git a/payloads/external/U-Boot/Makefile b/payloads/external/U-Boot/Makefile
index c588025616..9652838849 100644
--- a/payloads/external/U-Boot/Makefile
+++ b/payloads/external/U-Boot/Makefile
@@ -1,11 +1,7 @@
 ## SPDX-License-Identifier: GPL-2.0-only
 
-TAG-$(CONFIG_UBOOT_MASTER)=master
-TAG-$(CONFIG_UBOOT_STABLE)=$(STABLE_COMMIT_ID)
-
 project_name=U-Boot
 project_dir=u-boot
-project_git_repo=http://github.com/u-boot/u-boot/
 project_build_dir=build
 project_config_file=$(project_build_dir)/.config
 
@@ -23,15 +19,15 @@ all: build
 
 $(project_dir):
 	echo "    Cloning $(project_name) from Git"
-	git clone $(project_git_repo) -b $(TAG-y) $(project_dir)
+	git clone $(CONFIG_UBOOT_REPO_URL) -b $(CONFIG_UBOOT_BRANCH_OR_TAG) $(project_dir)
 
 fetch: $(project_dir)
 	echo "    Fetching new commits from the $(project_name) git repo"
 	cd $(project_dir) && git fetch
 
 checkout: fetch
-	echo "    Checking out $(project_name) revision $(TAG-y)"
-	cd $(project_dir); git checkout master; git branch -D coreboot 2>/dev/null; git checkout -b coreboot $(TAG-y)
+	echo "    Checking out $(project_name) revision $(CONFIG_UBOOT_BRANCH_OR_TAG)"
+	cd $(project_dir); git checkout $(CONFIG_UBOOT_BRANCH_OR_TAG); git branch -D coreboot 2>/dev/null; git checkout -b coreboot $(CONFIG_UBOOT_BRANCH_OR_TAG)
 
 config: checkout
 	mkdir -p $(project_build_dir)
@@ -49,7 +45,7 @@ else
 endif
 
 build: config
-	echo "    MAKE       $(project_name) $(TAG-y)"
+	echo "    MAKE       $(project_name) $(CONFIG_UBOOT_BRANCH_OR_TAG)"
 	$(MAKE) $(make_args)
 
 clean:
@@ -59,6 +55,6 @@ distclean:
 	rm -rf $(project_dir)
 
 print-repo-info:
-	echo "$(project_git_repo) $(project_dir)"
+	echo "$(CONFIG_UBOOT_REPO_URL) $(project_dir)"
 
 .PHONY: checkout config build clean distclean fetch print-repo-info

From 32ec29a51e9cfd6e07c793e867a59ab455081cd4 Mon Sep 17 00:00:00 2001
From: Norman Bintang <normanbt@chromium.org>
Date: Tue, 28 Oct 2025 18:34:14 +0800
Subject: [PATCH 2386/3886] mb/google/fatcat/var/kinmen: Disable RT721 clock
 stop support

This change applies the same fix as coreboot change CB:89605 to the
kinmen variant. Without this change, headset jack detection won't work.

The original change 752d49a4ffe98b731eb5a7c1beccff49f0418faa was:
  "mb/google/fatcat/var/moonstone: Disable RT721 clock stop support"

RT721 headset jack detection fails because the wakeup event is not
triggered during runtime suspend in D3 state. Disable the clock stop
to allow the bus driver to handle the wakeup process properly. The MIPI
Disco property is "mipi-sdw-simplified-clockstopprepare-sm-supported".

BUG=b:435094908
TEST=After plugging a headset, audio output is switched to it.
Change-Id: I468d949e1249548348493c070b4955c012ef7b4e
Signed-off-by: Norman Bintang <normanbt@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89784
Reviewed-by: Pranava Y N <pranavayn@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
---
 src/mainboard/google/fatcat/variants/kinmen/overridetree.cb | 1 +
 1 file changed, 1 insertion(+)

diff --git a/src/mainboard/google/fatcat/variants/kinmen/overridetree.cb b/src/mainboard/google/fatcat/variants/kinmen/overridetree.cb
index 2a9b91b05a..36a7c30d09 100644
--- a/src/mainboard/google/fatcat/variants/kinmen/overridetree.cb
+++ b/src/mainboard/google/fatcat/variants/kinmen/overridetree.cb
@@ -481,6 +481,7 @@ chip soc/intel/pantherlake
 						register "alc711_address.version" = "SOUNDWIRE_VERSION_1_2"
 						register "alc711_address.class" = "MIPI_CLASS_SDCA"
 						register "alc711_address.part_id" = "MIPI_DEV_ID_REALTEK_ALC721"
+						register "disable_clkstop_sm_support" = "true"
 						# SoundWire Link 3 ID 1
 						device generic 3.1 on
 							probe AUDIO AUDIO_ALC721_SNDW

From cfdaff3f7083a2d9ba7c9d7325232074746719a8 Mon Sep 17 00:00:00 2001
From: Elyes Haouas <ehaouas@noos.fr>
Date: Sun, 2 Nov 2025 07:59:25 +0100
Subject: [PATCH 2387/3886] commonlib/endian: Restore -Warray-bounds at the end
 of file

commit 668ea970 ("commonlib/endian: Silence GCC -Warray-bounds false
positives") added `#pragma GCC diagnostic ignored "-Warray-bounds"` but
forgot to restore the diagnostic state at the end of the file.

Change-Id: I41b38758ce862490777ede63ff92d95d6ba21521
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89867
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/commonlib/include/commonlib/endian.h | 1 +
 1 file changed, 1 insertion(+)

diff --git a/src/commonlib/include/commonlib/endian.h b/src/commonlib/include/commonlib/endian.h
index 24b10826f4..114d1bd469 100644
--- a/src/commonlib/include/commonlib/endian.h
+++ b/src/commonlib/include/commonlib/endian.h
@@ -252,4 +252,5 @@ static inline void zero_n(void *dest, size_t n)
 	memset(dest, 0, n);
 }
 
+#pragma GCC diagnostic pop /* restore -Warray-bounds */
 #endif /* _COMMONLIB_ENDIAN_H_ */

From fe7b75d79203d6b6f7f6cab82f8dfeaee4407ade Mon Sep 17 00:00:00 2001
From: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
Date: Fri, 31 Oct 2025 19:23:33 +0800
Subject: [PATCH 2388/3886] mb/google/fatcat/var/moonstone: Add fw_config
 touchscreen setting

Add a fw_config for touchscreen and non-touchscreen sku.
Based on the field to differentiat the touchscreen I2C port on/off
and GPIOs configuration.

BUG=none
TEST=Update the fw_config field and check the ap log:
     ABSENCE = 0 ... without touchscreen i2c probing messages.
     PRESENCE = 1 ... with touchscreen i2c probing messages.

Change-Id: I5f2cc0b0c37986240fbbeae3668ccc250748295d
Signed-off-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89851
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kenneth Chan <kenneth.chan@quanta.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
---
 .../google/fatcat/variants/moonstone/fw_config.c   | 14 ++++++++++++++
 .../fatcat/variants/moonstone/overridetree.cb      |  5 +++++
 2 files changed, 19 insertions(+)

diff --git a/src/mainboard/google/fatcat/variants/moonstone/fw_config.c b/src/mainboard/google/fatcat/variants/moonstone/fw_config.c
index 02fc5c82e2..22168413ba 100644
--- a/src/mainboard/google/fatcat/variants/moonstone/fw_config.c
+++ b/src/mainboard/google/fatcat/variants/moonstone/fw_config.c
@@ -77,6 +77,17 @@ static const struct pad_config pre_mem_fp_spi_enable_pads[] = {
 	PAD_CFG_GPO(GPP_C15, 0, DEEP),
 };
 
+static const struct pad_config touchscreen_disable_pads[] = {
+	/* GPP_F08:     EN_TCHSCR_PWR => NC */
+	PAD_NC(GPP_F08, NONE),
+	/* GPP_F16:     TCHSCR_RST_L => NC */
+	PAD_NC(GPP_F16, NONE),
+	/* GPP_F18:     TCHSCR_INT_L => NC */
+	PAD_NC(GPP_F18, NONE),
+	/* GPP_E05:     TCHSCR_RPT_EN => NC */
+	PAD_NC(GPP_E05, NONE),
+};
+
 void fw_config_configure_pre_mem_gpio(void)
 {
 	if (!fw_config_is_provisioned()) {
@@ -134,4 +145,7 @@ void fw_config_gpio_padbased_override(struct pad_config *padbased_table)
 		GPIO_PADBASED_OVERRIDE(padbased_table, use_usb3c_enable_pads);
 	else
 		GPIO_PADBASED_OVERRIDE(padbased_table, use_usb2a2c_hdmi_enable_pads);
+
+	if (fw_config_probe(FW_CONFIG(TOUCH_SCREEN, ABSENCE)))
+		GPIO_PADBASED_OVERRIDE(padbased_table, touchscreen_disable_pads);
 }
diff --git a/src/mainboard/google/fatcat/variants/moonstone/overridetree.cb b/src/mainboard/google/fatcat/variants/moonstone/overridetree.cb
index 2e8e44e6c3..8f02787cb2 100644
--- a/src/mainboard/google/fatcat/variants/moonstone/overridetree.cb
+++ b/src/mainboard/google/fatcat/variants/moonstone/overridetree.cb
@@ -16,6 +16,10 @@ fw_config
 		option USB2A2C_HDMI		0
 		option USB3C			1
 	end
+	field TOUCH_SCREEN 13 13
+		option ABSENCE			0
+		option PRESENCE			1
+	end
 end
 
 chip soc/intel/pantherlake
@@ -428,6 +432,7 @@ chip soc/intel/pantherlake
 			end
 		end # I2C4
 		device ref i2c5 on
+			probe TOUCH_SCREEN PRESENCE
 			chip drivers/i2c/hid
 				register "generic.hid" = ""ELAN9004""
 				register "generic.desc" = ""ELAN Touchscreen""

From ca5b51ef9c953dd74ac921e51ff2d19dc5f4d9fa Mon Sep 17 00:00:00 2001
From: Venkateshwar S <vens@qualcomm.corp-partner.google.com>
Date: Mon, 13 Oct 2025 21:03:33 -0700
Subject: [PATCH 2389/3886] mb/google/bluey: Select QTEE firmware dependent
 Kconfig

When the mainboard is Bluey, the Kconfig options 'ARM64_HAS_SECURE_OS'
and 'ARM64_HAS_SECURE_OS_PAYLOAD' are selected to pack and load the
QTEE firmware as a CBFS payload type, since its memory regions are non-
contiguous across system IMEM and DDR.

TEST = Create an image.serial.bin incorporating QTEE firmware and
ensure it boots to OS on X1P42100.

Change-Id: Iaedfa25d574af8451a7bb9a4a35c557f4e09eee2
Signed-off-by: Venkateshwar S <vens@qualcomm.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89554
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/google/bluey/Kconfig | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/src/mainboard/google/bluey/Kconfig b/src/mainboard/google/bluey/Kconfig
index 14c6bdf1c6..ffe06eb433 100644
--- a/src/mainboard/google/bluey/Kconfig
+++ b/src/mainboard/google/bluey/Kconfig
@@ -2,6 +2,8 @@
 
 config BOARD_GOOGLE_BLUEY_COMMON
 	def_bool n
+	select ARM64_USE_SECURE_OS
+	select ARM64_USE_SECURE_OS_PAYLOAD
 	select COMMON_CBFS_SPI_WRAPPER
 	select MAINBOARD_HAS_CHROMEOS
 	select SPI_FLASH

From 0c3f304d5af1be1d3931e22faf4c47f2387bf4c2 Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Tue, 28 Oct 2025 09:28:16 +0000
Subject: [PATCH 2390/3886] mb/starlabs/byte_adl: Enable Wake On Lan

Change-Id: I61e6e2b54fb41d610598af08b3f86009a5d539e5
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89783
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/starlabs/byte_adl/Kconfig                   | 1 +
 .../starlabs/byte_adl/variants/mk_ii/devicetree.cb        | 8 ++++++++
 2 files changed, 9 insertions(+)

diff --git a/src/mainboard/starlabs/byte_adl/Kconfig b/src/mainboard/starlabs/byte_adl/Kconfig
index f3cc349142..d3df0e0c44 100644
--- a/src/mainboard/starlabs/byte_adl/Kconfig
+++ b/src/mainboard/starlabs/byte_adl/Kconfig
@@ -7,6 +7,7 @@ config BOARD_STARLABS_BYTE_SERIES
 	select DRIVERS_EFI_VARIABLE_STORE
 	select DRIVERS_INTEL_PMC
 	select DRIVERS_OPTION_CFR_ENABLED
+	select DRIVERS_PCIE_GENERIC
 	select EC_STARLABS_ITE
 	select EC_STARLABS_MERLIN
 	select HAVE_ACPI_RESUME
diff --git a/src/mainboard/starlabs/byte_adl/variants/mk_ii/devicetree.cb b/src/mainboard/starlabs/byte_adl/variants/mk_ii/devicetree.cb
index 6cb92be551..40635bde30 100644
--- a/src/mainboard/starlabs/byte_adl/variants/mk_ii/devicetree.cb
+++ b/src/mainboard/starlabs/byte_adl/variants/mk_ii/devicetree.cb
@@ -154,6 +154,10 @@ chip soc/intel/alderlake
 				.PcieRpL1Substates			= L1_SS_L1_2,
 
 			}"
+			chip drivers/pcie/generic
+				register "wake_gpe" = "GPE0_PME_B0"
+				device generic 0 on end
+			end
 			smbios_slot_desc				"SlotTypePciExpressGen4x1"
 									"SlotLengthShort"
 									"SlotTypePci"
@@ -167,6 +171,10 @@ chip soc/intel/alderlake
 				.pcie_rp_aspm				= ASPM_L0S_L1,
 				.PcieRpL1Substates			= L1_SS_L1_2,
 			}"
+			chip drivers/pcie/generic
+				register "wake_gpe" = "GPE0_PME_B0"
+				device generic 0 on end
+			end
 			smbios_slot_desc				"SlotTypePciExpressGen3X4"
 									"SlotLengthShort"
 									"SlotTypePci"

From 2c9596555be54761d2708c4a2a1100335e99a825 Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Tue, 5 Sep 2023 11:27:46 -0500
Subject: [PATCH 2391/3886] mb/google/skyrim: Use edge (vs level) triggering
 for PS2K

For reasons currently unknown, using a level triggered interrupt for the
PS2 keyboard causes an IRQ storm under Windows when any key is pressed,
leading to audio distortion/dropouts. Work around this by using an edge
triggered interrupt instead.

BUG=none
TEST=build/boot Win11, Linux on google/skyrim (frostflow), verify kb
functionality, verify no IRQ storm or audio stutter/distortion under
Windows.

Change-Id: I6de426c5780b2f05571415e8e411e379de45b5bf
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77679
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
---
 .../skyrim/variants/baseboard/include/baseboard/ec.h       | 7 ++++++-
 1 file changed, 6 insertions(+), 1 deletion(-)

diff --git a/src/mainboard/google/skyrim/variants/baseboard/include/baseboard/ec.h b/src/mainboard/google/skyrim/variants/baseboard/include/baseboard/ec.h
index b7269f64cb..aeff2459b8 100644
--- a/src/mainboard/google/skyrim/variants/baseboard/include/baseboard/ec.h
+++ b/src/mainboard/google/skyrim/variants/baseboard/include/baseboard/ec.h
@@ -69,7 +69,12 @@
 #define SIO_EC_MEMMAP_ENABLE /* EC Memory Map Resources */
 #define SIO_EC_HOST_ENABLE   /* EC Host Interface Resources */
 #define SIO_EC_ENABLE_PS2K   /* Enable PS/2 Keyboard */
-#define SIO_EC_PS2K_IRQ Interrupt(ResourceConsumer, Level, ActiveLow, Shared) {1}
+/*
+ * This interrupt should technically be level, since that is the contract between the EC
+ * and the AP, but under Windows it produces an IRQ storm so Edge needs to be used instead.
+ * Both Windows and Linux are happy with Edge, so we'll use it for now.
+ */
+#define SIO_EC_PS2K_IRQ Interrupt(ResourceConsumer, Edge, ActiveLow, Shared) {1}
 
 /* Enable EC sync interrupt */
 #define EC_ENABLE_SYNC_IRQ_GPIO

From 2bbc0f1ad3b99816be599e163d9f00fd1496d61e Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Tue, 28 Oct 2025 20:05:18 +0000
Subject: [PATCH 2392/3886] mb/starlabs/starbook/{kbl,cml,tgl}: Control USB
 Bluetooth with wireless

Make the "wireless" option enable or disable the USB Bluetooth along
with the wireless card.

Change-Id: I253b83ac3efb768e91dba424be4cec6a56bf53f8
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89798
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/starlabs/starbook/variants/cml/devtree.c | 4 +++-
 src/mainboard/starlabs/starbook/variants/kbl/devtree.c | 4 +++-
 src/mainboard/starlabs/starbook/variants/tgl/devtree.c | 4 +++-
 3 files changed, 9 insertions(+), 3 deletions(-)

diff --git a/src/mainboard/starlabs/starbook/variants/cml/devtree.c b/src/mainboard/starlabs/starbook/variants/cml/devtree.c
index 85b5174392..f9d201078c 100644
--- a/src/mainboard/starlabs/starbook/variants/cml/devtree.c
+++ b/src/mainboard/starlabs/starbook/variants/cml/devtree.c
@@ -48,8 +48,10 @@ void devtree_update(void)
 	soc_conf->tdp_pl2_override = (soc_conf->tdp_pl2_override * performance_scale) / 100;
 
 	/* Enable/Disable Wireless based on CMOS settings */
-	if (get_uint_option("wireless", 1) == 0)
+	if (get_uint_option("wireless", 1) == 0) {
 		nic_dev->enabled = 0;
+		cfg->usb2_ports[9].enable = 0;
+	}
 
 	/* Enable/Disable Webcam based on CMOS settings */
 	cfg->usb2_ports[CONFIG_CCD_PORT].enable = get_uint_option("webcam", 1);
diff --git a/src/mainboard/starlabs/starbook/variants/kbl/devtree.c b/src/mainboard/starlabs/starbook/variants/kbl/devtree.c
index 4c7394515f..3cda4ce455 100644
--- a/src/mainboard/starlabs/starbook/variants/kbl/devtree.c
+++ b/src/mainboard/starlabs/starbook/variants/kbl/devtree.c
@@ -48,8 +48,10 @@ void devtree_update(void)
 	soc_conf->tdp_pl2_override = (soc_conf->tdp_pl2_override * performance_scale) / 100;
 
 	/* Enable/Disable Wireless based on CMOS settings */
-	if (get_uint_option("wireless", 1) == 0)
+	if (get_uint_option("wireless", 1) == 0) {
 		nic_dev->enabled = 0;
+		cfg->usb2_ports[9].enable = 0;
+	}
 
 	/* Enable/Disable Webcam based on CMOS settings */
 	cfg->usb2_ports[CONFIG_CCD_PORT].enable = get_uint_option("webcam", 1);
diff --git a/src/mainboard/starlabs/starbook/variants/tgl/devtree.c b/src/mainboard/starlabs/starbook/variants/tgl/devtree.c
index 8f6e39b066..3988cf2cde 100644
--- a/src/mainboard/starlabs/starbook/variants/tgl/devtree.c
+++ b/src/mainboard/starlabs/starbook/variants/tgl/devtree.c
@@ -60,8 +60,10 @@ void devtree_update(void)
 	soc_conf_4core->tdp_pl2_override = (soc_conf_4core->tdp_pl2_override * performance_scale) / 100;
 
 	/* Enable/Disable Wireless based on CMOS settings */
-	if (get_uint_option("wireless", 1) == 0)
+	if (get_uint_option("wireless", 1) == 0) {
 		nic_dev->enabled = 0;
+		cfg->usb2_ports[9].enable = 0;
+	}
 
 	/* Enable/Disable Webcam based on CMOS settings */
 	cfg->usb2_ports[CONFIG_CCD_PORT].enable = get_uint_option("webcam", 1);

From eadf2ee4a3a64c61a8a5e8e7a457a1205f50e28b Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Mon, 3 Nov 2025 10:13:54 -0600
Subject: [PATCH 2393/3886] ec/starlabs/merlin/cfr: Replace integer literals
 with named constants

Use defined constants from ec.h instead of hardcoded integer values
in all CFR enum definitions for improved readability and
maintainability.

Change-Id: I13b313d0c7a177fc689c3022256eb17125354599
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89881
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/ec/starlabs/merlin/cfr.h | 69 ++++++++++++++++++------------------
 1 file changed, 34 insertions(+), 35 deletions(-)

diff --git a/src/ec/starlabs/merlin/cfr.h b/src/ec/starlabs/merlin/cfr.h
index f53ec5fa4c..51b3adad1a 100644
--- a/src/ec/starlabs/merlin/cfr.h
+++ b/src/ec/starlabs/merlin/cfr.h
@@ -15,14 +15,14 @@ static const struct sm_object kbl_timeout = SM_DECLARE_ENUM({
 	.ui_name	= "Keyboard Backlight Timeout",
 	.ui_helptext	= "Set the amount of time before the keyboard backlight turns off"
 			  " when un-used",
-	.default_value	= 0,
+	.default_value	= SEC_30,
 	.values		= (struct sm_enum_value[]) {
-				{ "30 seconds",		0	},
-				{ "1 minute",		1	},
-				{ "3 minutes",		2	},
-				{ "5 minutes",		3	},
-				{ "Never",		4	},
-				SM_ENUM_VALUE_END		},
+			{ "30 seconds",		SEC_30	},
+			{ "1 minute",		MIN_1	},
+			{ "3 minutes",		MIN_3	},
+			{ "5 minutes",		MIN_5	},
+			{ "Never",		NEVER	},
+			SM_ENUM_VALUE_END		},
 });
 
 
@@ -43,12 +43,12 @@ static const struct sm_object max_charge = SM_DECLARE_ENUM({
 	.opt_name	= "max_charge",
 	.ui_name	= "Maximum Charge Level",
 	.ui_helptext	= "Set the maximum level the battery will charge to.",
-	.default_value	= 0,
+	.default_value	= CHARGE_100,
 	.values		= (const struct sm_enum_value[]) {
-				{ "100%",		0	},
-				{ "80%",		1	},
-				{ "60%",		2	},
-				SM_ENUM_VALUE_END		},
+			{ "100%",		CHARGE_100	},
+			{ "80%",		CHARGE_80	},
+			{ "60%",		CHARGE_60	},
+			SM_ENUM_VALUE_END			},
 });
 
 /*
@@ -58,13 +58,13 @@ static const struct sm_object fan_mode = SM_DECLARE_ENUM({
 	.opt_name	= "fan_mode",
 	.ui_name	= "Fan Mode",
 	.ui_helptext	= "Adjust the fan curve to prioritize performance or noise levels.",
-	.default_value	= 0,
+	.default_value	= FAN_NORMAL,
 	.values		= (const struct sm_enum_value[]) {
-				{ "Normal",		0		},
-				{ "Aggressive",		1		},
-				{ "Quiet",		2		},
-				{ "Disabled",		3		},
-				SM_ENUM_VALUE_END			},
+			{ "Normal",		FAN_NORMAL	},
+			{ "Aggressive",		FAN_AGGRESSIVE	},
+			{ "Quiet",		FAN_QUIET	},
+			{ "Disabled",		FAN_DISABLED	},
+			SM_ENUM_VALUE_END			},
 });
 
 /*
@@ -74,13 +74,13 @@ static const struct sm_object charging_speed = SM_DECLARE_ENUM({
 	.opt_name	= "charging_speed",
 	.ui_name	= "Charging Speed",
 	.ui_helptext	= "Set the maximum speed to charge the battery. Charging faster"
-			  " will increase heat and battery wear.",
-	.default_value	= 1,
+		  " will increase heat and battery wear.",
+	.default_value	= SPEED_0_5C,
 	.values		= (const struct sm_enum_value[]) {
-				{ "1.0C",		0	},
-				{ "0.5C",		1	},
-				{ "0.2C",		2	},
-				SM_ENUM_VALUE_END		},
+			{ "1.0C",		SPEED_1_0C	},
+			{ "0.5C",		SPEED_0_5C	},
+			{ "0.2C",		SPEED_0_2C	},
+			SM_ENUM_VALUE_END			},
 });
 
 /*
@@ -90,12 +90,12 @@ static const struct sm_object lid_switch = SM_DECLARE_ENUM({
 	.opt_name	= "lid_switch",
 	.ui_name	= "Lid Switch",
 	.ui_helptext	= "Configure what opening or closing the lid will do.",
-	.default_value	= 0,
+	.default_value	= SWITCH_NORMAL,
 	.values		= (const struct sm_enum_value[]) {
-				{ "Normal",		0	},
-				{ "Sleep Only",		1	},
-				{ "Disabled",		2	},
-				SM_ENUM_VALUE_END		},
+			{ "Normal",		SWITCH_NORMAL		},
+			{ "Sleep Only",		SWITCH_SLEEP_ONLY	},
+			{ "Disabled",		SWITCH_DISABLED		},
+			SM_ENUM_VALUE_END				},
 });
 
 /*
@@ -105,11 +105,10 @@ static const struct sm_object power_led = SM_DECLARE_ENUM({
 	.opt_name	= "power_led",
 	.ui_name	= "Power LED Brightness",
 	.ui_helptext	= "Control the maximum brightness of the power LED",
-	.default_value	= 0,
+	.default_value	= LED_NORMAL,
 	.values		= (const struct sm_enum_value[]) {
-				{ "Normal",		0		},
-				{ "Reduced",		1		},
-				{ "Off",		2		},
-				SM_ENUM_VALUE_END,
-	},
+			{ "Normal",		LED_NORMAL	},
+			{ "Reduced",		LED_REDUCED	},
+			{ "Off",		LED_OFF		},
+			SM_ENUM_VALUE_END			},
 });

From 2821e8e2aee534d8e42fc133d910e4efc625264d Mon Sep 17 00:00:00 2001
From: Subrata Banik <subratabanik@google.com>
Date: Mon, 3 Nov 2025 19:15:08 +0530
Subject: [PATCH 2394/3886] soc/intel/ptl: Remove redundant
 HAVE_BMP_LOGO_COMPRESS_LZMA Kconfig
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

This commit removes the explicit CONFIG_HAVE_BMP_LOGO_COMPRESS_LZMA
definition from the Panther Lake Kconfig.

This local Kconfig setting, previously defaulted to 'n', is redundant
because the Panther Lake build now correctly inherits the intended
system-wide default, which is to use LZMA compression for the BMP
splash screen.

Removing this unnecessary Kconfig option simplifies the configuration
and results in a measured ~3ms reduction in boot time during the
firmware splash screen rendering phase on Panther Lake platforms.

w/o this patch:

```
 963:returning from FspMultiPhaseSiInit          1,096,797 (102,937)
  17:starting LZ4 decompress (ignore for x86)    1,111,606 (14,808)
  18:finished LZ4 decompress (ignore for x86)    1,111,641 (34)
  17:starting LZ4 decompress (ignore for x86)    1,119,857 (8,216)
  18:finished LZ4 decompress (ignore for x86)    1,119,879 (21)
```

w/ this patch

```
 963:returning from FspMultiPhaseSiInit          1,097,817 (103,211)
  15:starting LZMA decompress (ignore for x86)   1,110,058 (12,241)
  16:finished LZMA decompress (ignore for x86)   1,111,096 (1,037)
  15:starting LZMA decompress (ignore for x86)   1,117,554 (6,458)
  16:finished LZMA decompress (ignore for x86)   1,117,906 (352)
```

Change-Id: I64579e53c7f307d1430767da04a413f80016487f
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89876
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
---
 src/soc/intel/pantherlake/Kconfig | 3 ---
 1 file changed, 3 deletions(-)

diff --git a/src/soc/intel/pantherlake/Kconfig b/src/soc/intel/pantherlake/Kconfig
index 7d6e9f7248..a0a39bc765 100644
--- a/src/soc/intel/pantherlake/Kconfig
+++ b/src/soc/intel/pantherlake/Kconfig
@@ -430,9 +430,6 @@ config PCIE_LTR_MAX_NO_SNOOP_LATENCY
 	help
 	  Latency tolerance reporting, max non-snoop latency value defaults to 15.73 ms.
 
-config HAVE_BMP_LOGO_COMPRESS_LZMA
-	default n
-
 # The default offset to store CSE RW FW version information is at 68.
 # However, in Intel Panther Lake based systems that use PSR, the additional
 # size required to keep CSE RW FW version information and PSR back-up status

From 4d9dacae165b219061f7fc80c2651504f8a71b51 Mon Sep 17 00:00:00 2001
From: Luca Lai <luca.lai@lcfc.corp-partner.google.com>
Date: Mon, 3 Nov 2025 19:51:40 +0800
Subject: [PATCH 2395/3886] mb/google/fatcat/var/ruby: Modify touchpad device
 setting to enable function

Modify touchpad device setting to enable the ELAN touchpad.

schematics: RUBY_EVT_0902_2112.pdf

Device i2c log:
[INFO ]  \_SB.PCI0.CNVW: WIFI Device GENERIC: 0.0
[INFO ]  \_SB.PCI0.I2C0.RT58: Headset Codec at I2C: 00:1a
[INFO ]  \_SB.PCI0.I2C0.D04B: TI SPK AMP L at I2C: 00:4b
[INFO ]  \_SB.PCI0.I2C0.D04C: TI SPK AMP R at I2C: 00:4c
[INFO ]  \_SB.PCI0.I2C0.D04D: TI SPK AMP TL at I2C: 00:4d
[INFO ]  \_SB.PCI0.I2C0.D04F: T1 SPK AMP TR at I2C: 00:4f
[INFO ]  \_SB.PCI0.I2C3.TPMI: I2C TPM at I2C: 00:50
[INFO ]  \_SB.PCI0.I2C4.H015: ELAN Touchpad at I2C: 00:15
[INFO ]  \_SB.PCI0.I2C5.H014: Goodix Touchscreen at I2C: 00:14
[INFO ]  \_SB.PCI0.RP01: Enable RTD3 for PCI: 00:00:1c.0 (Intel PCIe Runtime D3)

Changes:
hid : From PIXA2305 to ELAN2705
hid_desc_reg_offset : From 0x20 to 0x01
address : From 0x2C to 0x15

BUG=b:449901218
TEST=Build and boot to OS and use Elan touchpad module to verify the cursor works.

Change-Id: I11dcca5db5558af4cdd4b87a9b42519615839fef
Signed-off-by: Luca Lai <luca.lai@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89873
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: YH Lin <yueherngl@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
---
 .../google/fatcat/variants/ruby/overridetree.cb  | 16 +++-------------
 1 file changed, 3 insertions(+), 13 deletions(-)

diff --git a/src/mainboard/google/fatcat/variants/ruby/overridetree.cb b/src/mainboard/google/fatcat/variants/ruby/overridetree.cb
index e9efe66691..7abb6c6a8f 100644
--- a/src/mainboard/google/fatcat/variants/ruby/overridetree.cb
+++ b/src/mainboard/google/fatcat/variants/ruby/overridetree.cb
@@ -257,23 +257,13 @@ chip soc/intel/pantherlake
 		end # I2C3
 		device ref i2c4 on
 			chip drivers/i2c/hid
-				register "generic.hid" = ""PIXA2305""
-				register "generic.desc" = ""PIXA Touchpad""
-				register "generic.irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_E18_IRQ)"
-				# NOTE: pmc_gpe0_dw2 is GPP_E in baseboard devicetree.cb.
-				register "generic.wake" = "GPE0_DW2_18"
-				register "generic.detect" = "1"
-				register "hid_desc_reg_offset" = "0x20"
-				device i2c 68 on end
-			end
-			chip drivers/i2c/hid
-				register "generic.hid" = ""PNP0C50""
+				register "generic.hid" = ""ELAN2705""
 				register "generic.desc" = ""ELAN Touchpad""
 				register "generic.irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_E18_IRQ)"
 				register "generic.wake" = "GPE0_DW2_18"
 				register "generic.detect" = "1"
-				register "hid_desc_reg_offset" = "0x20"
-				device i2c 2c on end
+				register "hid_desc_reg_offset" = "0x01"
+				device i2c 15 on end
 			end
 		end # I2C4
 		device ref i2c5 on

From ebc2030ff78363507e8f5a8dfda42c7b62130dfe Mon Sep 17 00:00:00 2001
From: Zhixing Ma <zhixing.ma@intel.com>
Date: Wed, 16 Jul 2025 09:32:44 -0700
Subject: [PATCH 2396/3886] soc/intel/pantherlake: Enable HW managed microphone
 privacy
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Enable hardware-managed microphone privacy by setting the
PchHdaMicPrivacyMode FSP UPD to 1. This feature was enabled by
default in FSP previously but has since changed to disabled by
default, so now coreboot explicitly enables this as it is a desired
feature for Chrome platforms.

The hardware-managed microphone privacy feature allows the platform
to control the microphone mute state at the hardware level for
enhanced privacy.

TEST=Verify UPD value is set correctly and HW managed mic privacy is
working as expected.

Change-Id: I9a20bd129103aae35550104f6a7025484ef5e9c1
Signed-off-by: Zhixing Ma <zhixing.ma@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88451
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: <srinivas.kulkarni@intel.com>
---
 src/soc/intel/pantherlake/fsp_params.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/src/soc/intel/pantherlake/fsp_params.c b/src/soc/intel/pantherlake/fsp_params.c
index e423986d53..0976d3bb77 100644
--- a/src/soc/intel/pantherlake/fsp_params.c
+++ b/src/soc/intel/pantherlake/fsp_params.c
@@ -730,6 +730,7 @@ static void fill_fsps_audio_params(FSP_S_CONFIG *s_cfg,
 	s_cfg->PchHdaMicPrivacyHwModeSoundWire3 = 1;
 	s_cfg->PchHdaMicPrivacyHwModeSoundWire4 = 1;
 	s_cfg->PchHdaMicPrivacyHwModeDmic = 1;
+	s_cfg->PchHdaMicPrivacyMode = 1;
 }
 
 static void fill_fsps_iax_params(FSP_S_CONFIG *s_cfg,

From 9c0a9141921edc5a6b1dde0c43f02a8da8e0a050 Mon Sep 17 00:00:00 2001
From: Julius Werner <jwerner@chromium.org>
Date: Thu, 30 Oct 2025 14:02:25 -0700
Subject: [PATCH 2397/3886] libpayload: Fix printf edge cases for precision

This patch fixes a number of rare edge cases in handling the precision
argument in printf. The existing printf implementation used 0 as the
sentinel value for "no precision provided", which makes sense for
integers (where 0 precision has the same effect as no precision, since
in both cases no extra zeroes will be added to the front). However, for
strings it can make an important difference, since callers may expect
that they can use `printf("%.*s", len, str)` to guarantee that `str`
doesn't get dereferenced when `len` is 0. Therefore, change the
implementation so that negative values are used to represent "no
precision provided", and 0 is a legitimate value.

print_string() also had the problem that it called strlen() on the
string before even evaluating the precision. That of course defeats the
purpose of the common "%.*s" pattern to access unterminated strings.
This patch fixes the problem.

Finally, this patch slightly modifies the behavior when printing a NULL
pointer as a string, to make sure width and precision values are still
taken into account in that case, and to change from `(NULL)` to `(null)`
to match the behavior in glibc.

Change-Id: I787c18e1d33006842cf758aeb87710f80f0e5a40
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89837
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 payloads/libpayload/libc/printf.c | 36 ++++++++++---------------------
 1 file changed, 11 insertions(+), 25 deletions(-)

diff --git a/payloads/libpayload/libc/printf.c b/payloads/libpayload/libc/printf.c
index 3edf166b98..a071f0d59f 100644
--- a/payloads/libpayload/libc/printf.c
+++ b/payloads/libpayload/libc/printf.c
@@ -100,18 +100,6 @@ static int printf_putnchars(const char *buf, size_t count,
 	return ps->write(buf, count, ps->data);
 }
 
-/**
- * Print a string without adding a newline.
- *
- * @param str	String to print.
- * @param ps	Write function specification and support data.
- * @return	Number of characters printed.
- */
-static inline int printf_putstr(const char *str, struct printf_spec *ps)
-{
-	return printf_putnchars(str, strlen(str), ps);
-}
-
 /**
  * Print one character.
  *
@@ -191,19 +179,19 @@ static int print_char(char c, int width, uint64_t flags, struct printf_spec *ps)
  * @return		Number of characters printed, negative value on	failure.
  */
 /** Structure for specifying output methods for different printf clones. */
-static int print_string(char *s, int width, unsigned int precision,
+static int print_string(const char *s, int width, int precision,
 			uint64_t flags, struct printf_spec *ps)
 {
 	int counter = 0, retval;
 	size_t size;
 
 	if (s == NULL)
-		return printf_putstr("(NULL)", ps);
-	size = strlen(s);
-	/* Print leading spaces. */
-	if (precision == 0)
-		precision = size;
-	width -= precision;
+		s = "(null)";
+	if (precision >= 0)
+		size = strnlen(s, precision);
+	else
+		size = strlen(s);
+	width -= size;
 
 	if (!(flags & __PRINTF_FLAG_LEFTALIGNED)) {
 		if ((retval = print_spaces(width, ps)) < 0)
@@ -212,7 +200,7 @@ static int print_string(char *s, int width, unsigned int precision,
 			counter += retval;
 	}
 
-	if ((retval = printf_putnchars(s, MIN(size, precision), ps)) < 0)
+	if ((retval = printf_putnchars(s, size, ps)) < 0)
 		return retval;
 	counter += retval;
 
@@ -264,7 +252,7 @@ static int print_number(uint64_t num, int width, int precision, int base,
 	}
 
 	/* Both precision and LEFTALIGNED overrule ZEROPADDED. */
-	if ((flags & __PRINTF_FLAG_LEFTALIGNED) || precision)
+	if ((flags & __PRINTF_FLAG_LEFTALIGNED) || precision >= 0)
 		flags &= ~__PRINTF_FLAG_ZEROPADDED;
 
 	/* Fix precision now since it doesn't count prefixes/signs. */
@@ -517,9 +505,10 @@ static int printf_core(const char *fmt, struct printf_spec *ps, va_list ap)
 			}
 
 			/* Precision and '*' operator. */
-			precision = 0;
+			precision = -1;
 			if (fmt[i] == '.') {
 				++i;
+				precision = 0;
 				if (isdigit(fmt[i])) {
 					while (isdigit(fmt[i])) {
 						precision *= 10;
@@ -529,9 +518,6 @@ static int printf_core(const char *fmt, struct printf_spec *ps, va_list ap)
 					/* Get precision from argument list. */
 					i++;
 					precision = (int)va_arg(ap, int);
-					/* Ignore negative precision. */
-					if (precision < 0)
-						precision = 0;
 				}
 			}
 

From 1b2675e4f21c829ba820923a03aa00053f0c0d53 Mon Sep 17 00:00:00 2001
From: Yu-Ping Wu <yupingso@chromium.org>
Date: Mon, 3 Nov 2025 23:57:41 +0800
Subject: [PATCH 2398/3886] soc/mediatek/mt8189: Require libbl31.a to exist

The libbl31.a library is crucial to MT8189's UFS functionality. Modify
Makefile.mk to enforce the presence of the file.

BUG=b:453965141
TEST=emerge-skywalker coreboot
BRANCH=skywalker

Change-Id: I7af74936462a8f2f8c11782e33011686d00a6dea
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89880
Reviewed-by: Chen-Tsung Hsieh <chentsung@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
---
 src/soc/mediatek/mt8189/Makefile.mk | 3 ---
 1 file changed, 3 deletions(-)

diff --git a/src/soc/mediatek/mt8189/Makefile.mk b/src/soc/mediatek/mt8189/Makefile.mk
index 351c94190b..fe4c7d931b 100644
--- a/src/soc/mediatek/mt8189/Makefile.mk
+++ b/src/soc/mediatek/mt8189/Makefile.mk
@@ -76,10 +76,7 @@ CPPFLAGS_common += -Isrc/soc/mediatek/common/dp/include
 MT8189_BLOB_DIR := 3rdparty/blobs/soc/mediatek/mt8189
 
 BL31_LIB := $(top)/$(MT8189_BLOB_DIR)/libbl31.a
-
-ifneq ($(wildcard $(BL31_LIB)),)
 BL31_MAKEARGS += MTKLIB_PATH=$(BL31_LIB)
-endif
 
 firmware-files := \
 	$(CONFIG_DPM_DM_FIRMWARE) \

From 2646eeffb2adf9f2345972be3860f7eccafc1515 Mon Sep 17 00:00:00 2001
From: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Date: Tue, 4 Nov 2025 16:16:16 +0800
Subject: [PATCH 2399/3886] mb/google/skywalker: Create variant Dooku

BUG=b:457605256
TEST=emerge-skywalker coreboot
BRANCH=skywalker

Change-Id: I9c1d0f1655c986fbd096742b04a4b3efaf515ec0
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89888
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/google/skywalker/Kconfig      | 2 ++
 src/mainboard/google/skywalker/Kconfig.name | 3 +++
 2 files changed, 5 insertions(+)

diff --git a/src/mainboard/google/skywalker/Kconfig b/src/mainboard/google/skywalker/Kconfig
index c369c5b5c2..fe0c6a8edf 100644
--- a/src/mainboard/google/skywalker/Kconfig
+++ b/src/mainboard/google/skywalker/Kconfig
@@ -4,6 +4,7 @@
 config BOARD_GOOGLE_SKYWALKER_COMMON
 	def_bool BOARD_GOOGLE_ANAKIN || \
 		 BOARD_GOOGLE_BAZE || \
+		 BOARD_GOOGLE_DOOKU || \
 		 BOARD_GOOGLE_GROGU || \
 		 BOARD_GOOGLE_OBIWAN || \
 		 BOARD_GOOGLE_PADME || \
@@ -52,6 +53,7 @@ config MAINBOARD_PART_NUMBER
 	string
 	default "Anakin" if BOARD_GOOGLE_ANAKIN
 	default "Baze" if BOARD_GOOGLE_BAZE
+	default "Dooku" if BOARD_GOOGLE_DOOKU
 	default "Grogu" if BOARD_GOOGLE_GROGU
 	default "Obiwan" if BOARD_GOOGLE_OBIWAN
 	default "Padme" if BOARD_GOOGLE_PADME
diff --git a/src/mainboard/google/skywalker/Kconfig.name b/src/mainboard/google/skywalker/Kconfig.name
index abdaf64209..6c67574e94 100644
--- a/src/mainboard/google/skywalker/Kconfig.name
+++ b/src/mainboard/google/skywalker/Kconfig.name
@@ -8,6 +8,9 @@ config BOARD_GOOGLE_ANAKIN
 config BOARD_GOOGLE_BAZE
 	bool "->  Baze"
 
+config BOARD_GOOGLE_DOOKU
+	bool "->  Dooku"
+
 config BOARD_GOOGLE_GROGU
 	bool "->  Grogu"
 

From 75318743c3d6aba87bb72bb8796576e27add13d6 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Bart=C5=82omiej=20Grzesik?= <bgrzesik@google.com>
Date: Mon, 3 Nov 2025 11:01:54 +0100
Subject: [PATCH 2400/3886] commonlib: Add pKVM DRNG related timestamps
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Add 2 new timestamps for measuring the time to generate pKVM
deterministic random number generator seed in depthcharge.
First indicate when the generation has started and
a second when the setup is complete.

BUG=b:449097147
TEST=builds

Change-Id: I1bced5a331e4d10a1ec1c305b9b2a41d1e913579
Signed-off-by: Bartłomiej Grzesik <bgrzesik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89872
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
---
 src/commonlib/include/commonlib/timestamp_serialized.h | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/src/commonlib/include/commonlib/timestamp_serialized.h b/src/commonlib/include/commonlib/timestamp_serialized.h
index 022725af3e..db02ac7219 100644
--- a/src/commonlib/include/commonlib/timestamp_serialized.h
+++ b/src/commonlib/include/commonlib/timestamp_serialized.h
@@ -178,6 +178,9 @@ enum timestamp_id {
 	TS_PVMFW_GSC_NVRAM_DONE = 1111,
 	TS_PVMFW_SETUP_DONE = 1112,
 
+	TS_PKVM_DRNG_SEED_START = 1120,
+	TS_PKVM_DRNG_SEED_DONE = 1121,
+
 	/* 1200-1300: ChromeOS Hypervisor */
 	TS_CRHV_BOOT = 1200,
 	TS_CRHV_PLATFORM_INIT = 1201,
@@ -379,6 +382,9 @@ static const struct timestamp_id_to_name {
 	TS_NAME_DEF(TS_PVMFW_GSC_NVRAM_DONE, 0, "finished fetching boot params from GSC"),
 	TS_NAME_DEF(TS_PVMFW_SETUP_DONE, 0, "finished pvmfw setup"),
 
+	TS_NAME_DEF(TS_PKVM_DRNG_SEED_START, 0, "started generating pKVM DRNG seed"),
+	TS_NAME_DEF(TS_PKVM_DRNG_SEED_DONE, 0, "finished generating pKVM DRNG seed"),
+
 	/* ChromeOS hypervisor */
 	TS_NAME_DEF(TS_CRHV_BOOT, 0, "hypervisor boot finished"),
 	TS_NAME_DEF(TS_CRHV_PLATFORM_INIT, 0, "hypervisor platform initialized"),

From 74113f5d5e89f6cf81e077a2a4a1c9da66940f77 Mon Sep 17 00:00:00 2001
From: Kapil Porwal <kapilporwal@google.com>
Date: Sun, 7 Sep 2025 19:40:46 +0530
Subject: [PATCH 2401/3886] drivers/intel/fsp2_0: Add options to config VGA
 mode 12

This commit adds new Kconfig options and a code snippet to support
VGA mode 12 within the FSP (Firmware Support Package) 2.0. The
changes allow platforms to select VGA mode 12 and configure it.

The key features are:
- Introduces `FSP_VGA_MODE12` to enable VGA mode 12 support.
- A new `FSP_VGA_MODE12_BPP` option defines the bits per pixel,
  defaulting to 4 for color mode.
- A bitmap buffer is allocated on the stack and supplied to FSP
  based on the configured bits per pixel.

BUG=b:406725440
TEST=Verify VGA text rotation on Google/Felino.

Change-Id: Iaa3a64b7c8c735d8329b3596f4be315871bc7fa4
Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89090
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
---
 src/drivers/intel/fsp2_0/Kconfig           | 15 +++++++++++++++
 src/drivers/intel/fsp2_0/include/fsp/api.h |  6 ++++++
 src/drivers/intel/fsp2_0/memory_init.c     | 10 ++++++++++
 3 files changed, 31 insertions(+)

diff --git a/src/drivers/intel/fsp2_0/Kconfig b/src/drivers/intel/fsp2_0/Kconfig
index ed599d5e72..f864c344e7 100644
--- a/src/drivers/intel/fsp2_0/Kconfig
+++ b/src/drivers/intel/fsp2_0/Kconfig
@@ -500,4 +500,19 @@ config FSP_DIMM_INFO
 	  Select this option to retrieve DIMM (Memory) related information by relying on
 	  the Intel FSP. coreboot relies on this information to prepare SMBIOS table 17.
 
+config FSP_VGA_MODE12
+	bool
+	default n
+	depends on VGA || ROMSTAGE_VGA
+	help
+	  Select this if the FSP supports VGA mode 12.
+
+config FSP_VGA_MODE12_BPP
+	hex
+	default 0x4 if FSP_VGA_MODE12
+	default 0x0
+	help
+	  This is the number of bits per pixel used by FSP in VGA mode 12.
+	  A bitmap buffer is allocated based on this value and supplied to FSP.
+
 endif
diff --git a/src/drivers/intel/fsp2_0/include/fsp/api.h b/src/drivers/intel/fsp2_0/include/fsp/api.h
index b9a58dbaa0..fa3c42c94e 100644
--- a/src/drivers/intel/fsp2_0/include/fsp/api.h
+++ b/src/drivers/intel/fsp2_0/include/fsp/api.h
@@ -129,6 +129,12 @@ static inline void soc_load_logo_by_coreboot(void) { /* nop */ }
 static inline int soc_mark_gfx_memory(void) { return -1; }
 #endif
 
+#if CONFIG(FSP_VGA_MODE12)
+void soc_set_vga_mode12_buffer(FSPM_UPD *fspm_upd, uintptr_t buffer);
+#else
+static inline void soc_set_vga_mode12_buffer(FSPM_UPD *fspm_upd, uintptr_t buffer) { /* nop */ }
+#endif
+
 /* Update the SOC specific memory config param for mma. */
 void soc_update_memory_params_for_mma(FSP_M_CONFIG *memory_cfg,
 	struct mma_config_param *mma_cfg);
diff --git a/src/drivers/intel/fsp2_0/memory_init.c b/src/drivers/intel/fsp2_0/memory_init.c
index f6945a2313..f3cb529caa 100644
--- a/src/drivers/intel/fsp2_0/memory_init.c
+++ b/src/drivers/intel/fsp2_0/memory_init.c
@@ -405,6 +405,16 @@ static void do_fsp_memory_init(const struct fspm_context *context, bool s3wake)
 	/* Reserve enough memory under TOLUD to save CBMEM header */
 	arch_upd->BootLoaderTolumSize = cbmem_overhead_size();
 
+#if CONFIG_FSP_VGA_MODE12_BPP
+	/* Allocate a buffer for VGA mode 12 on the stack since we do not have
+	 * memory available yet. It is done here to avoid deallocation before
+	 * calling FSP-M.
+	 */
+	unsigned char temp_vga_buffer[CONFIG_FSP_VGA_MODE12_BPP * VGA12_BITMAP_BUFFER_SZ];
+	memset(temp_vga_buffer, 0, sizeof(temp_vga_buffer));
+	soc_set_vga_mode12_buffer(&fspm_upd, (uintptr_t)temp_vga_buffer);
+#endif
+
 	/* Fill common settings on behalf of chipset. */
 	if (fsp_fill_common_arch_params(arch_upd, s3wake, version,
 					memmap) != CB_SUCCESS)

From 824992ddef46381b73428ccd07ba0e4bb7571b5e Mon Sep 17 00:00:00 2001
From: Kapil Porwal <kapilporwal@google.com>
Date: Sun, 7 Sep 2025 19:46:07 +0530
Subject: [PATCH 2402/3886] soc/intel/pantherlake/romstage: Configure VGA mode
 12 planar buffer

This commit implements the configuration of VGA mode 12 in the
Intel Pantherlake SoC's romstage. It integrates the newly added
text rendering API to display user messages using a planar buffer
instead of the standard VGA message string.

The changes include:
- A call to `render_text_to_bitmap_buffer()` to draw the message
  on the bitmap buffer.
- Determining the display orientation from the common SoC
  configuration, with an override for a closed lid.
- Calculating and setting the correct position of the rendered
  text in the VGA buffer.
- Duplicating the single-plane bitmap data to all required planes
  for VGA mode 12.
- Setting the `VGA_INIT_CONTROL_MODE12` bit in the FSP-M UPD
  to inform FSP to use the new mode.
- Implementing the `soc_set_vga_mode12_buffer()` API to set the
  corresponding FSP-M UPD for VGA mode12 buffer address.

BUG=b:406725440
TEST=Verify VGA text rotation on Google/Felino.

Change-Id: Ic69fff0479020a31c7e6f0c52b4bdb25b1483bb9
Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89091
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
---
 src/soc/intel/pantherlake/romstage/ux.c | 41 +++++++++++++++++++++++++
 src/soc/intel/pantherlake/romstage/ux.h |  3 +-
 2 files changed, 43 insertions(+), 1 deletion(-)

diff --git a/src/soc/intel/pantherlake/romstage/ux.c b/src/soc/intel/pantherlake/romstage/ux.c
index 5f511a2827..4e346f439f 100644
--- a/src/soc/intel/pantherlake/romstage/ux.c
+++ b/src/soc/intel/pantherlake/romstage/ux.c
@@ -1,6 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
 #include <bootmode.h>
+#include <bootsplash.h>
 #include <console/console.h>
 #include <fsp/util.h>
 #include <timestamp.h>
@@ -10,6 +11,43 @@
 
 #include "ux.h"
 
+#if CONFIG(FSP_VGA_MODE12)
+void soc_set_vga_mode12_buffer(FSPM_UPD *fspm_upd, uintptr_t buffer)
+{
+	fspm_upd->FspmConfig.VgaGraphicsMode12ImagePtr = buffer;
+}
+#endif
+
+static void setup_vga_mode12_params(FSP_M_CONFIG *m_cfg, enum ux_locale_msg id)
+{
+	struct soc_intel_common_config *common_config = chip_get_common_soc_structure();
+	unsigned char *vga_bitmap_buffer = (unsigned char *)(uintptr_t)m_cfg->VgaGraphicsMode12ImagePtr;
+	enum lb_fb_orientation current_orientation = common_config->panel_orientation;
+	if (!vga_bitmap_buffer) {
+		return;
+	}
+	int img_width = VGA12_WIDTH;
+	int img_height = VGA12_HEIGHT;
+	if (!m_cfg->LidStatus)
+		current_orientation = LB_FB_ORIENTATION_NORMAL;
+	render_text_to_bitmap_buffer(vga_bitmap_buffer,
+				current_orientation,
+				ux_locales_get_text(id),
+				&img_width, &img_height);
+	int img_size = img_width * img_height / 8; // Image is a bitmap
+	// Duplicate the first plane data to all other planes
+	for (int i = 1; i < CONFIG_FSP_VGA_MODE12_BPP; i++)
+		memcpy(vga_bitmap_buffer + (i * img_size),
+			vga_bitmap_buffer,
+			img_size);
+
+	m_cfg->LogoPixelHeight = img_height;
+	m_cfg->LogoPixelWidth = img_width;
+	m_cfg->LogoXPosition = (VGA12_WIDTH - img_width) / 2;
+	m_cfg->LogoYPosition = (VGA12_HEIGHT - img_height) / 2;
+	m_cfg->VgaInitControl |= VGA_INIT_CONTROL_MODE12;
+}
+
 static bool ux_inform_user_of_operation(const char *name, enum ux_locale_msg id,
 		 FSPM_UPD *mupd)
 {
@@ -55,6 +93,9 @@ static bool ux_inform_user_of_operation(const char *name, enum ux_locale_msg id,
 	m_cfg->LidStatus = CONFIG(VBOOT_LID_SWITCH) ? get_lid_switch() : CONFIG(RUN_FSP_GOP);
 	m_cfg->VgaMessage = (efi_uintn_t)ux_locales_get_text(id);
 
+	if (CONFIG(FSP_VGA_MODE12))
+		setup_vga_mode12_params(m_cfg, id);
+
 	ux_done = true;
 
 	timestamp_add_now(TS_ESOL_END);
diff --git a/src/soc/intel/pantherlake/romstage/ux.h b/src/soc/intel/pantherlake/romstage/ux.h
index 85a641dec8..abdaa86eec 100644
--- a/src/soc/intel/pantherlake/romstage/ux.h
+++ b/src/soc/intel/pantherlake/romstage/ux.h
@@ -10,6 +10,7 @@ bool ux_inform_user_of_poweroff_operation(const char *name, FSPM_UPD *mupd);
 
 /* VGA initialization configuration */
 #define VGA_INIT_CONTROL_ENABLE		BIT(0)
-#define VGA_INIT_DISABLE_ANIMATION  BIT(4)
+#define VGA_INIT_CONTROL_MODE12		BIT(1)
+#define VGA_INIT_DISABLE_ANIMATION	BIT(4)
 
 #endif /* _SOC_INTEL_PANTHERLAKE_ROMSTAGE_UX_H_ */

From 40a8466655024234af887f14ae024a9200b3ffdb Mon Sep 17 00:00:00 2001
From: Kapil Porwal <kapilporwal@google.com>
Date: Sun, 7 Sep 2025 19:49:17 +0530
Subject: [PATCH 2403/3886] mb/google/fatcat: Add option to enable VGA mode 12

This commit adds a new Kconfig option to the `fatcat`
mainboard to enable VGA mode 12 support for early Sign of Life
(eSOL).

- This option, `FATCAT_VGA_MODE12_SUPPORT`, is dependent on
  `FSP_UGOP_EARLY_SIGN_OF_LIFE`.
- It selects `ROMSTAGE_VGA` and `FSP_VGA_MODE12` to enable the
  necessary VGA components.

BUG=b:406725440
TEST=Verify VGA text rotation on Google/Felino.

Change-Id: I3b9a433c7b3938b8cc17f44552b8463ee049e5c3
Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89092
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/google/fatcat/Kconfig | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/src/mainboard/google/fatcat/Kconfig b/src/mainboard/google/fatcat/Kconfig
index 394bf4f515..1d0f83f3ce 100644
--- a/src/mainboard/google/fatcat/Kconfig
+++ b/src/mainboard/google/fatcat/Kconfig
@@ -259,4 +259,13 @@ config OVERRIDE_DEVICETREE
 config VBOOT
 	select VBOOT_LID_SWITCH
 
+config FATCAT_VGA_MODE12_SUPPORT
+	bool "Enable VGA Mode 12 support for eSOL"
+	default n
+	depends on FSP_UGOP_EARLY_SIGN_OF_LIFE
+	select ROMSTAGE_VGA
+	select FSP_VGA_MODE12
+	help
+	  Select this if the FSP supports VGA mode 12 for eSOL.
+
 endif # BOARD_GOOGLE_FATCAT_COMMON

From a86a5ebf7c162c5cad93c2f21fc75b6763acfabd Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Thu, 30 Oct 2025 14:20:55 -0500
Subject: [PATCH 2404/3886] payloads/edk2: Update default MrChromebox branch
 from 2502 to 2508

Update the default MrChromebox branch to uefipayload_2508.
This branch is rebased on the latest upstream edk tag
'edk2-stable202508', and includes a number of other improvements,
including memory safety fixes, improved support for eMMC on AMD
Picasso-based devices, improved UFS support for Alderlake-N based
devices, and a new driver supporting devices which use a Genesys
Logic GL97xx PCIe eMMC or SD card controller.

Change-Id: Id5d02da6396ce7ec7bfb7aaa90ebb234ec05020b
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89856
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
---
 payloads/external/edk2/Kconfig | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/payloads/external/edk2/Kconfig b/payloads/external/edk2/Kconfig
index 08e48e53ff..a23400f752 100644
--- a/payloads/external/edk2/Kconfig
+++ b/payloads/external/edk2/Kconfig
@@ -86,7 +86,7 @@ config EDK2_REPOSITORY
 
 config EDK2_TAG_OR_REV
 	string "Insert a commit's SHA-1 or a branch name"
-	default "origin/uefipayload_2502" if EDK2_REPO_MRCHROMEBOX
+	default "origin/uefipayload_2508" if EDK2_REPO_MRCHROMEBOX
 	default "origin/universalpayload" if EDK2_UNIVERSAL_PAYLOAD
 	default "origin/master" if EDK2_REPO_OFFICIAL
 	default "" if EDK2_REPO_CUSTOM

From 4423a0b3908845f77324109d98b6336ff0d6f62a Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Thu, 30 Oct 2025 14:08:34 -0500
Subject: [PATCH 2405/3886] payloads/edk2: Drop EDK2_UFS_ENABLE Kconfig option

This option existed because the inclusion of the UFS driver in edk2
needed to be guarded due to some issues on non-UFS equipped devices.
Those issues have been resolved in edk2, so the UFS driver does not
need guarding anymore.

Remove the EDK2_UFS_ENABLE Kconfig symbol definition, associated build
logic, and selection from google/brya baseboard.

TEST=build/boot UFS and non-UFS ChromeOS boards with edk2 payload.

Change-Id: I3f20d503de4a642ee3fbb175c267e1f5f7328c8d
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89857
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 payloads/external/Makefile.mk     | 1 -
 payloads/external/edk2/Kconfig    | 9 ---------
 payloads/external/edk2/Makefile   | 4 ----
 src/mainboard/google/brya/Kconfig | 1 -
 4 files changed, 15 deletions(-)

diff --git a/payloads/external/Makefile.mk b/payloads/external/Makefile.mk
index 0ba9a02c27..b7d3516bfe 100644
--- a/payloads/external/Makefile.mk
+++ b/payloads/external/Makefile.mk
@@ -196,7 +196,6 @@ $(obj)/UEFIPAYLOAD.fd: $(DOTCONFIG)
 		CONFIG_EDK2_GOP_FILE=$(CONFIG_EDK2_GOP_FILE) \
 		CONFIG_INTEL_GMA_VBT_FILE=$(CONFIG_INTEL_GMA_VBT_FILE) \
 		CONFIG_EDK2_DISABLE_TPM=$(CONFIG_EDK2_DISABLE_TPM) \
-		CONFIG_EDK2_UFS_ENABLE=$(CONFIG_EDK2_UFS_ENABLE) \
 		CONFIG_EDK2_PCO_MMIO_EMMC=$(CONFIG_EDK2_PCO_MMIO_EMMC) \
 		CONFIG_EDK2_USE_LAPIC_TIMER=$(CONFIG_EDK2_USE_LAPIC_TIMER) \
 		CONFIG_SOC_AMD_COMMON_BLOCK_PSP_GEN2=$(CONFIG_SOC_AMD_COMMON_BLOCK_PSP_GEN2) \
diff --git a/payloads/external/edk2/Kconfig b/payloads/external/edk2/Kconfig
index a23400f752..f731bb1eda 100644
--- a/payloads/external/edk2/Kconfig
+++ b/payloads/external/edk2/Kconfig
@@ -298,15 +298,6 @@ config EDK2_DISABLE_TPM
 	  Select this option to disable TPM support in edk2. This is necessary to avoid boot
 	  hangs on some boards with a CR50 TPM, particularly those with an AMD Zen SoC.
 
-config EDK2_UFS_ENABLE
-	bool "Enable UFS DXE driver in edk2"
-	depends on EDK2_REPO_MRCHROMEBOX
-	default n
-	help
-	  Select this option to enable the UFS DXE driver in MrChromebox's fork of edk2.
-	  It is needed for boards with UFS storage, but can cause issues with other boards,
-	  so should only be enabled when needed.
-
 config EDK2_PCO_MMIO_EMMC
 	bool "Enable MMIO eMMC driver for AMD Picasso boards in edk2"
 	depends on EDK2_REPO_MRCHROMEBOX
diff --git a/payloads/external/edk2/Makefile b/payloads/external/edk2/Makefile
index 168c511562..e55b6b5354 100644
--- a/payloads/external/edk2/Makefile
+++ b/payloads/external/edk2/Makefile
@@ -150,10 +150,6 @@ endif
 ifeq ($(CONFIG_EDK2_DISABLE_TPM),y)
 BUILD_STR += -D TPM_ENABLE=FALSE
 endif
-# UFS_ENABLE			= FALSE
-ifeq ($(CONFIG_EDK2_UFS_ENABLE),y)
-BUILD_STR += -D UFS_ENABLE=TRUE
-endif
 # USE_PCO_MMIO_EMMC		= FALSE
 ifeq ($(CONFIG_EDK2_PCO_MMIO_EMMC),y)
 BUILD_STR += -D USE_PCO_MMIO_EMMC=TRUE
diff --git a/src/mainboard/google/brya/Kconfig b/src/mainboard/google/brya/Kconfig
index e1524bd206..a60dd5386a 100644
--- a/src/mainboard/google/brya/Kconfig
+++ b/src/mainboard/google/brya/Kconfig
@@ -25,7 +25,6 @@ config BOARD_GOOGLE_BRYA_COMMON
 	select EC_GOOGLE_CHROMEEC_ESPI
 	select EC_GOOGLE_CHROMEEC_SKUID
 	select EC_GOOGLE_CHROMEEC_SMBIOS
-	select EDK2_UFS_ENABLE if EDK2_REPO_MRCHROMEBOX
 	select ENABLE_TCSS_USB_DETECTION if !(SOC_INTEL_TCSS_USE_PDC_PMC_USBC_MUX_CONFIGURATION || CHROMEOS)
 	select FW_CONFIG
 	select FW_CONFIG_SOURCE_CHROMEEC_CBI

From 6d751ef9870255e316e422904fa85f67bb0d99bd Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Thu, 30 Oct 2025 14:19:35 -0500
Subject: [PATCH 2406/3886] payloads/edk2: Drop EDK2_PCO_MMIO_EMMC Kconfig
 option

This option existed to enable the MMIO eMMC DXE driver for AMD Picasso
boards with eMMC storage. The driver has been integrated into edk2 and
no longer requires guarding via a build-time option.

Remove the EDK2_PCO_MMIO_EMMC Kconfig symbol definition, associated
build logic, and the board-level select from google/zork.

TEST=build/boot AMD Picasso boards with edk2 payload.

Change-Id: I458a45ad752d88cc9252f2d8fe6b0e8ec054329d
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89858
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
---
 payloads/external/Makefile.mk     | 1 -
 payloads/external/edk2/Kconfig    | 9 ---------
 payloads/external/edk2/Makefile   | 4 ----
 src/mainboard/google/zork/Kconfig | 1 -
 4 files changed, 15 deletions(-)

diff --git a/payloads/external/Makefile.mk b/payloads/external/Makefile.mk
index b7d3516bfe..c0882c426d 100644
--- a/payloads/external/Makefile.mk
+++ b/payloads/external/Makefile.mk
@@ -196,7 +196,6 @@ $(obj)/UEFIPAYLOAD.fd: $(DOTCONFIG)
 		CONFIG_EDK2_GOP_FILE=$(CONFIG_EDK2_GOP_FILE) \
 		CONFIG_INTEL_GMA_VBT_FILE=$(CONFIG_INTEL_GMA_VBT_FILE) \
 		CONFIG_EDK2_DISABLE_TPM=$(CONFIG_EDK2_DISABLE_TPM) \
-		CONFIG_EDK2_PCO_MMIO_EMMC=$(CONFIG_EDK2_PCO_MMIO_EMMC) \
 		CONFIG_EDK2_USE_LAPIC_TIMER=$(CONFIG_EDK2_USE_LAPIC_TIMER) \
 		CONFIG_SOC_AMD_COMMON_BLOCK_PSP_GEN2=$(CONFIG_SOC_AMD_COMMON_BLOCK_PSP_GEN2) \
 		CONFIG_DRIVERS_EFI_UPDATE_CAPSULES=$(CONFIG_DRIVERS_EFI_UPDATE_CAPSULES) \
diff --git a/payloads/external/edk2/Kconfig b/payloads/external/edk2/Kconfig
index f731bb1eda..583de2dc1d 100644
--- a/payloads/external/edk2/Kconfig
+++ b/payloads/external/edk2/Kconfig
@@ -298,15 +298,6 @@ config EDK2_DISABLE_TPM
 	  Select this option to disable TPM support in edk2. This is necessary to avoid boot
 	  hangs on some boards with a CR50 TPM, particularly those with an AMD Zen SoC.
 
-config EDK2_PCO_MMIO_EMMC
-	bool "Enable MMIO eMMC driver for AMD Picasso boards in edk2"
-	depends on EDK2_REPO_MRCHROMEBOX
-	default n
-	help
-	  Select this option to enable the MMIO eMMC DXE driver in MrChromebox's fork of edk2.
-	  It is needed for AMD Picasso boards with eMMC storage, but will conflict with the
-	  PCI-based eMMC driver, so should only be enabled for AMD Picasso boards.
-
 config EDK2_USE_LAPIC_TIMER
 	bool "Use LAPIC timer instead of HPET"
 	default n
diff --git a/payloads/external/edk2/Makefile b/payloads/external/edk2/Makefile
index e55b6b5354..1b8ca2e67b 100644
--- a/payloads/external/edk2/Makefile
+++ b/payloads/external/edk2/Makefile
@@ -150,10 +150,6 @@ endif
 ifeq ($(CONFIG_EDK2_DISABLE_TPM),y)
 BUILD_STR += -D TPM_ENABLE=FALSE
 endif
-# USE_PCO_MMIO_EMMC		= FALSE
-ifeq ($(CONFIG_EDK2_PCO_MMIO_EMMC),y)
-BUILD_STR += -D USE_PCO_MMIO_EMMC=TRUE
-endif
 # TIMER_SUPPORT			= HPET
 ifeq ($(CONFIG_EDK2_USE_LAPIC_TIMER),y)
 BUILD_STR += -D TIMER_SUPPORT=LAPIC
diff --git a/src/mainboard/google/zork/Kconfig b/src/mainboard/google/zork/Kconfig
index 2cb296408c..b998de0f1c 100644
--- a/src/mainboard/google/zork/Kconfig
+++ b/src/mainboard/google/zork/Kconfig
@@ -63,7 +63,6 @@ config BOARD_SPECIFIC_OPTIONS
 	select EC_GOOGLE_CHROMEEC_INCLUDE_SSFC_IN_FW_CONFIG
 	select EC_GOOGLE_CHROMEEC_SKUID
 	select EC_GOOGLE_CHROMEEC_SMBIOS
-	select EDK2_PCO_MMIO_EMMC if EDK2_REPO_MRCHROMEBOX
 	select ELOG
 	select ELOG_BOOT_COUNT
 	select ELOG_GSMI

From 8a518b21344617d016efb835fa183670083104c5 Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Thu, 30 Oct 2025 15:00:55 -0500
Subject: [PATCH 2407/3886] mb/google/beltino: Fix ACPI fan control FNP4 power
 resource

The FNP4 power resource (minimum fan level) had both _ON and _OFF
methods setting the same state (\FLVL = 4), violating ACPI power
resource requirements where _OFF must transition to a state where
_STA eventually returns 0 (OFF).

This violation causes Windows to reject the thermal zone entirely due
to its stricter ACPI compliance checking, resulting in non-functional
fan control. Linux tolerates this bug, which is why it went unnoticed.

Since FAN4 represents the minimum cooling state with no lower state
to transition to, the correct implementation is to make _OFF a no-op.
This maintains proper ACPI state machine semantics: after _ON, _STA
returns 1; after _OFF, the system remains at minimum cooling (which
is already the lowest valid state).

This enables proper fan control operation on Windows while maintaining
Linux compatibility.

TEST=build/boot Win10/Linux on google/beltino, verify fan functional
under Windows 10, continues to work correctly under Linux.

Change-Id: Ie53ad9b547b2f2d522e2ed692f8db55aa9a6b8d3
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89839
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/google/beltino/acpi/thermal.asl | 8 +++-----
 1 file changed, 3 insertions(+), 5 deletions(-)

diff --git a/src/mainboard/google/beltino/acpi/thermal.asl b/src/mainboard/google/beltino/acpi/thermal.asl
index 3463028bbd..40564c3ad7 100644
--- a/src/mainboard/google/beltino/acpi/thermal.asl
+++ b/src/mainboard/google/beltino/acpi/thermal.asl
@@ -271,11 +271,9 @@ Scope (\_TZ)
 				}
 			}
 			Method (_OFF) {
-				If (_STA ()) {
-					\FLVL = 4
-					\_SB.PCI0.LPCB.SIO.ENVC.F2PS = FAN4_PWM
-					Notify (\_TZ.THRM, 0x81)
-				}
+				// FAN4 is the minimum cooling state (idle/lowest fan speed)
+				// There is no lower state to transition to, so _OFF is a no-op
+				// to maintain proper ACPI power resource state machine semantics
 			}
 		}
 

From b9b95c917adc5890cb6e47a0045d70e192fa32a0 Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Thu, 30 Oct 2025 15:04:23 -0500
Subject: [PATCH 2408/3886] mb/google/guado: Fix ACPI fan control FNP4 power
 resource

The FNP4 power resource (minimum fan level) had both _ON and _OFF
methods setting the same state (\FLVL = 4), violating ACPI power
resource requirements where _OFF must transition to a state where
_STA eventually returns 0 (OFF).

This violation causes Windows to reject the thermal zone entirely due
to its stricter ACPI compliance checking, resulting in non-functional
fan control. Linux tolerates this bug, which is why it went unnoticed.

Since FAN4 represents the minimum cooling state with no lower state
to transition to, the correct implementation is to make _OFF a no-op.
This maintains proper ACPI state machine semantics: after _ON, _STA
returns 1; after _OFF, the system remains at minimum cooling (which
is already the lowest valid state).

This enables proper fan control operation on Windows while maintaining
Linux compatibility.

TEST=build/boot Win10/Linux on google/jecht, verify fan functional
under Windows 10, continues to work correctly under Linux.

Change-Id: Iac60a18dd1e4b632d85384ddbbcfcddaf0b8d2cc
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89840
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
---
 .../jecht/variants/guado/include/variant/acpi/thermal.asl | 8 +++-----
 .../jecht/variants/jecht/include/variant/acpi/thermal.asl | 8 +++-----
 .../jecht/variants/rikku/include/variant/acpi/thermal.asl | 8 +++-----
 .../jecht/variants/tidus/include/variant/acpi/thermal.asl | 8 +++-----
 4 files changed, 12 insertions(+), 20 deletions(-)

diff --git a/src/mainboard/google/jecht/variants/guado/include/variant/acpi/thermal.asl b/src/mainboard/google/jecht/variants/guado/include/variant/acpi/thermal.asl
index d4957f44a4..ac9926562b 100644
--- a/src/mainboard/google/jecht/variants/guado/include/variant/acpi/thermal.asl
+++ b/src/mainboard/google/jecht/variants/guado/include/variant/acpi/thermal.asl
@@ -272,11 +272,9 @@ Scope (\_TZ)
 				}
 			}
 			Method (_OFF) {
-				If (_STA ()) {
-					\FLVL = 4
-					\_SB.PCI0.LPCB.SIO.ENVC.F2PS = FAN4_PWM
-					Notify (\_TZ.THRM, 0x81)
-				}
+				// FAN4 is the minimum cooling state (idle/lowest fan speed)
+				// There is no lower state to transition to, so _OFF is a no-op
+				// to maintain proper ACPI power resource state machine semantics
 			}
 		}
 
diff --git a/src/mainboard/google/jecht/variants/jecht/include/variant/acpi/thermal.asl b/src/mainboard/google/jecht/variants/jecht/include/variant/acpi/thermal.asl
index d4957f44a4..ac9926562b 100644
--- a/src/mainboard/google/jecht/variants/jecht/include/variant/acpi/thermal.asl
+++ b/src/mainboard/google/jecht/variants/jecht/include/variant/acpi/thermal.asl
@@ -272,11 +272,9 @@ Scope (\_TZ)
 				}
 			}
 			Method (_OFF) {
-				If (_STA ()) {
-					\FLVL = 4
-					\_SB.PCI0.LPCB.SIO.ENVC.F2PS = FAN4_PWM
-					Notify (\_TZ.THRM, 0x81)
-				}
+				// FAN4 is the minimum cooling state (idle/lowest fan speed)
+				// There is no lower state to transition to, so _OFF is a no-op
+				// to maintain proper ACPI power resource state machine semantics
 			}
 		}
 
diff --git a/src/mainboard/google/jecht/variants/rikku/include/variant/acpi/thermal.asl b/src/mainboard/google/jecht/variants/rikku/include/variant/acpi/thermal.asl
index d4957f44a4..ac9926562b 100644
--- a/src/mainboard/google/jecht/variants/rikku/include/variant/acpi/thermal.asl
+++ b/src/mainboard/google/jecht/variants/rikku/include/variant/acpi/thermal.asl
@@ -272,11 +272,9 @@ Scope (\_TZ)
 				}
 			}
 			Method (_OFF) {
-				If (_STA ()) {
-					\FLVL = 4
-					\_SB.PCI0.LPCB.SIO.ENVC.F2PS = FAN4_PWM
-					Notify (\_TZ.THRM, 0x81)
-				}
+				// FAN4 is the minimum cooling state (idle/lowest fan speed)
+				// There is no lower state to transition to, so _OFF is a no-op
+				// to maintain proper ACPI power resource state machine semantics
 			}
 		}
 
diff --git a/src/mainboard/google/jecht/variants/tidus/include/variant/acpi/thermal.asl b/src/mainboard/google/jecht/variants/tidus/include/variant/acpi/thermal.asl
index 6be0181578..749cd51208 100644
--- a/src/mainboard/google/jecht/variants/tidus/include/variant/acpi/thermal.asl
+++ b/src/mainboard/google/jecht/variants/tidus/include/variant/acpi/thermal.asl
@@ -380,11 +380,9 @@ Scope (\_TZ)
 				}
 			}
 			Method (_OFF) {
-				If (_STA ()) {
-					\FLVL = 4
-					\_SB.PCI0.LPCB.SIO.ENVC.F2PS = F4PW
-					Notify (\_TZ.THRM, 0x81)
-				}
+				// FAN4 is the minimum cooling state (idle/lowest fan speed)
+				// There is no lower state to transition to, so _OFF is a no-op
+				// to maintain proper ACPI power resource state machine semantics
 			}
 		}
 

From f12f292d91772bae72565dbb7224c04d403cdaa9 Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Thu, 30 Oct 2025 15:06:13 -0500
Subject: [PATCH 2409/3886] mb/google/intel/*: Fix ACPI fan control FNP4 power
 resource

The FNP4 power resource (minimum fan level) had both _ON and _OFF
methods setting the same state (\FLVL = 4), violating ACPI power
resource requirements where _OFF must transition to a state where
_STA eventually returns 0 (OFF).

This violation causes Windows to reject the thermal zone entirely due
to its stricter ACPI compliance checking, resulting in non-functional
fan control. Linux tolerates this bug, which is why it went unnoticed.

Since FAN4 represents the minimum cooling state with no lower state
to transition to, the correct implementation is to make _OFF a no-op.
This maintains proper ACPI state machine semantics: after _ON, _STA
returns 1; after _OFF, the system remains at minimum cooling (which
is already the lowest valid state).

This enables proper fan control operation on Windows while maintaining
Linux compatibility.

TEST=untested, but same as tested change on other mainboards in series.

Change-Id: I5d6c5f6cb8232b956bbd1be6220b8bb09c32b480
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89841
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
---
 src/mainboard/intel/baskingridge/acpi/thermal.asl | 6 +++---
 src/mainboard/intel/emeraldlake2/acpi/thermal.asl | 6 +++---
 src/mainboard/intel/wtm2/acpi/thermal.asl         | 5 +++--
 3 files changed, 9 insertions(+), 8 deletions(-)

diff --git a/src/mainboard/intel/baskingridge/acpi/thermal.asl b/src/mainboard/intel/baskingridge/acpi/thermal.asl
index 5649d87a2c..fb015d17ca 100644
--- a/src/mainboard/intel/baskingridge/acpi/thermal.asl
+++ b/src/mainboard/intel/baskingridge/acpi/thermal.asl
@@ -196,9 +196,9 @@ Scope (\_TZ)
 				Notify (\_TZ.THRM, 0x81)
 			}
 			Method (_OFF) {
-				\FLVL = 4
-				\_SB.PCI0.LPCB.SIO.ENVC.F3PS = \F4PW
-				Notify (\_TZ.THRM, 0x81)
+				// FAN4 is the minimum cooling state (idle/lowest fan speed)
+				// There is no lower state to transition to, so _OFF is a no-op
+				// to maintain proper ACPI power resource state machine semantics
 			}
 		}
 
diff --git a/src/mainboard/intel/emeraldlake2/acpi/thermal.asl b/src/mainboard/intel/emeraldlake2/acpi/thermal.asl
index af6c41e572..d5149da549 100644
--- a/src/mainboard/intel/emeraldlake2/acpi/thermal.asl
+++ b/src/mainboard/intel/emeraldlake2/acpi/thermal.asl
@@ -215,9 +215,9 @@ Scope (\_TZ)
 				Notify (\_TZ.THRM, 0x81)
 			}
 			Method (_OFF) {
-				\FLVL = 4
-				\_SB.PCI0.LPCB.SIO.ENVC.F3PS = \F4PW
-				Notify (\_TZ.THRM, 0x81)
+				// FAN4 is the minimum cooling state (idle/lowest fan speed)
+				// There is no lower state to transition to, so _OFF is a no-op
+				// to maintain proper ACPI power resource state machine semantics
 			}
 		}
 
diff --git a/src/mainboard/intel/wtm2/acpi/thermal.asl b/src/mainboard/intel/wtm2/acpi/thermal.asl
index cb0388f924..3604805245 100644
--- a/src/mainboard/intel/wtm2/acpi/thermal.asl
+++ b/src/mainboard/intel/wtm2/acpi/thermal.asl
@@ -189,8 +189,9 @@ Scope (\_TZ)
 				Notify (\_TZ.THRM, 0x81)
 			}
 			Method (_OFF) {
-				\FLVL = 4
-				Notify (\_TZ.THRM, 0x81)
+				// FAN4 is the minimum cooling state (idle/lowest fan speed)
+				// There is no lower state to transition to, so _OFF is a no-op
+				// to maintain proper ACPI power resource state machine semantics
 			}
 		}
 

From 8ce9255f8219320320e4a4aa8b78c4c7a9dc8c29 Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Thu, 30 Oct 2025 15:07:42 -0500
Subject: [PATCH 2410/3886] mb/samsung/stumpy: Fix ACPI fan control FNP4 power
 resource

The FNP4 power resource (minimum fan level) had both _ON and _OFF
methods setting the same state (\FLVL = 4), violating ACPI power
resource requirements where _OFF must transition to a state where
_STA eventually returns 0 (OFF).

This violation causes Windows to reject the thermal zone entirely due
to its stricter ACPI compliance checking, resulting in non-functional
fan control. Linux tolerates this bug, which is why it went unnoticed.

Since FAN4 represents the minimum cooling state with no lower state
to transition to, the correct implementation is to make _OFF a no-op.
This maintains proper ACPI state machine semantics: after _ON, _STA
returns 1; after _OFF, the system remains at minimum cooling (which
is already the lowest valid state).

This enables proper fan control operation on Windows while maintaining
Linux compatibility.

TEST=build/boot Win10/Linux on samsung/stumpy, verify fan functional
under Windows 10, continues to work correctly under Linux.

Change-Id: I00431490ae080226d526c1e217bb10e8ded64c3c
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89842
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/samsung/stumpy/acpi/thermal.asl | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/src/mainboard/samsung/stumpy/acpi/thermal.asl b/src/mainboard/samsung/stumpy/acpi/thermal.asl
index 1edaafd84e..2dcb13fabe 100644
--- a/src/mainboard/samsung/stumpy/acpi/thermal.asl
+++ b/src/mainboard/samsung/stumpy/acpi/thermal.asl
@@ -214,9 +214,9 @@ Scope (\_TZ)
 				Notify (\_TZ.THRM, 0x81)
 			}
 			Method (_OFF) {
-				\FLVL = 4
-				\_SB.PCI0.LPCB.SIO.ENVC.F3PS = \F4PW
-				Notify (\_TZ.THRM, 0x81)
+				// FAN4 is the minimum cooling state (idle/lowest fan speed)
+				// There is no lower state to transition to, so _OFF is a no-op
+				// to maintain proper ACPI power resource state machine semantics
 			}
 		}
 

From 534fceb36a203c10a1cd65d9461768e6fb4fef5b Mon Sep 17 00:00:00 2001
From: Kilian Krause <kilian.krause@siemens.com>
Date: Mon, 3 Nov 2025 17:38:22 +0100
Subject: [PATCH 2411/3886] mb/siemens/mc_rpl1: Set PCI bridge function for
 NC_FPGA

Update EARLY_PCI_BRIDGE_FUNCTION from 0x0 to 0x2 for NC FPGA POST
code communication. This matches the PCI bridge function where the
NC FPGA is connected on this hardware.

TEST=Built and booted on mc_rpl1. Verified that POST codes display
correctly on the 7-segment display.

Change-Id: I52c463036091ac42c6db415d1d3e582e561aff67
Signed-off-by: Kilian Krause <kilian.krause@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89882
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
---
 src/mainboard/siemens/mc_rpl/variants/mc_rpl1/Kconfig | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/mainboard/siemens/mc_rpl/variants/mc_rpl1/Kconfig b/src/mainboard/siemens/mc_rpl/variants/mc_rpl1/Kconfig
index 858cb3fce8..9bf0138051 100644
--- a/src/mainboard/siemens/mc_rpl/variants/mc_rpl1/Kconfig
+++ b/src/mainboard/siemens/mc_rpl/variants/mc_rpl1/Kconfig
@@ -24,7 +24,7 @@ config EARLY_PCI_BRIDGE_DEVICE
 config EARLY_PCI_BRIDGE_FUNCTION
 	hex
 	depends on NC_FPGA_POST_CODE
-	default 0x0
+	default 0x2
 
 config EARLY_PCI_MMIO_BASE
 	hex

From 8411fef90f5acaa5edddaf9834711349633ea108 Mon Sep 17 00:00:00 2001
From: Kilian Krause <kilian.krause@siemens.com>
Date: Tue, 4 Nov 2025 14:27:26 +0100
Subject: [PATCH 2412/3886] mb/siemens/mc_rpl1: Switch from LPSS UART to legacy
 8250 I/O UART

Replace the memory-mapped LPSS UART2 with I/O port-mapped legacy
8250 UART for the serial console.

- Replace INTEL_LPSS_UART_FOR_CONSOLE with DRIVERS_UART_8250IO
- Add SOC_INTEL_COMMON_BLOCK_LPC_COMB_ENABLE to enable COM2
- Change UART_FOR_CONSOLE from 2 to 0 (COM1 at 0x3F8)

DRIVERS_UART_8250IO enables COM1 (I/O port 0x3F8).
SOC_INTEL_COMMON_BLOCK_LPC_COMB_ENABLE enables COM2 (I/O port 0x2F8).

TEST=Build and boot on mc_rpl1. Verify console output on both COM1
and COM2.

Change-Id: I93deaba5fedf8c9aecff4a425e8cec406d2759c2
Signed-off-by: Kilian Krause <kilian.krause@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89892
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/siemens/mc_rpl/variants/mc_rpl1/Kconfig | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/src/mainboard/siemens/mc_rpl/variants/mc_rpl1/Kconfig b/src/mainboard/siemens/mc_rpl/variants/mc_rpl1/Kconfig
index 9bf0138051..47cceb0cc7 100644
--- a/src/mainboard/siemens/mc_rpl/variants/mc_rpl1/Kconfig
+++ b/src/mainboard/siemens/mc_rpl/variants/mc_rpl1/Kconfig
@@ -4,9 +4,10 @@ if BOARD_SIEMENS_MC_RPL1
 
 config BOARD_SPECIFIC_OPTIONS
 	def_bool y
-	select INTEL_LPSS_UART_FOR_CONSOLE
+	select DRIVERS_UART_8250IO
 	select MAINBOARD_HAS_TPM2
 	select MEMORY_MAPPED_TPM
+	select SOC_INTEL_COMMON_BLOCK_LPC_COMB_ENABLE
 	select TPM_MEASURED_BOOT
 	select TPM_MEASURED_BOOT_INIT_BOOTBLOCK
 	select DRIVER_INTEL_I210
@@ -14,7 +15,7 @@ config BOARD_SPECIFIC_OPTIONS
 
 config UART_FOR_CONSOLE
 	int
-	default 2
+	default 0
 
 config EARLY_PCI_BRIDGE_DEVICE
 	hex

From fa23504c59bc548928b281a970f762eb90926f95 Mon Sep 17 00:00:00 2001
From: Kilian Krause <kilian.krause@siemens.com>
Date: Tue, 4 Nov 2025 14:46:33 +0100
Subject: [PATCH 2413/3886] mb/siemens/mc_rpl: Alphabetize Kconfig options

Sort Kconfig select statements alphabetically for better readability
and maintainability.

No functional changes.

Change-Id: Id0c858de485dee6b8f950b7b60a469de9139d7b4
Signed-off-by: Kilian Krause <kilian.krause@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89893
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
---
 src/mainboard/siemens/mc_rpl/Kconfig                  | 6 +++---
 src/mainboard/siemens/mc_rpl/variants/mc_rpl1/Kconfig | 4 ++--
 2 files changed, 5 insertions(+), 5 deletions(-)

diff --git a/src/mainboard/siemens/mc_rpl/Kconfig b/src/mainboard/siemens/mc_rpl/Kconfig
index 76e2845420..cfb5712833 100644
--- a/src/mainboard/siemens/mc_rpl/Kconfig
+++ b/src/mainboard/siemens/mc_rpl/Kconfig
@@ -4,17 +4,17 @@ config BOARD_SIEMENS_BASEBOARD_MC_RPL
 	def_bool n
 	select BOARD_ROMSIZE_KB_16384
 	select CPU_INTEL_SOCKET_LGA1700
+	select DRIVER_SIEMENS_NC_FPGA
 	select DRIVERS_I2C_GENERIC
 	select DRIVERS_INTEL_DPTF
 	select DRIVERS_SPI_ACPI
 	select DRIVERS_USB_ACPI
+	select FSP_TYPE_IOT
 	select HAVE_ACPI_RESUME
 	select HAVE_ACPI_TABLES
-	select USE_SIEMENS_HWILIB
 	select SOC_INTEL_ALDERLAKE_PCH_P
 	select SOC_INTEL_RAPTORLAKE
-	select DRIVER_SIEMENS_NC_FPGA
-	select FSP_TYPE_IOT
+	select USE_SIEMENS_HWILIB
 
 config BOARD_SIEMENS_MC_RPL1
 	select BOARD_SIEMENS_BASEBOARD_MC_RPL
diff --git a/src/mainboard/siemens/mc_rpl/variants/mc_rpl1/Kconfig b/src/mainboard/siemens/mc_rpl/variants/mc_rpl1/Kconfig
index 47cceb0cc7..fdb35b66d5 100644
--- a/src/mainboard/siemens/mc_rpl/variants/mc_rpl1/Kconfig
+++ b/src/mainboard/siemens/mc_rpl/variants/mc_rpl1/Kconfig
@@ -4,14 +4,14 @@ if BOARD_SIEMENS_MC_RPL1
 
 config BOARD_SPECIFIC_OPTIONS
 	def_bool y
+	select DRIVER_INTEL_I210
 	select DRIVERS_UART_8250IO
 	select MAINBOARD_HAS_TPM2
 	select MEMORY_MAPPED_TPM
+	select NC_FPGA_POST_CODE
 	select SOC_INTEL_COMMON_BLOCK_LPC_COMB_ENABLE
 	select TPM_MEASURED_BOOT
 	select TPM_MEASURED_BOOT_INIT_BOOTBLOCK
-	select DRIVER_INTEL_I210
-	select NC_FPGA_POST_CODE
 
 config UART_FOR_CONSOLE
 	int

From 47c4da36c456dd0e7f4a5d8059882c71ad153570 Mon Sep 17 00:00:00 2001
From: Maximilian Brune <maximilian.brune@9elements.com>
Date: Thu, 25 Sep 2025 02:34:40 +0200
Subject: [PATCH 2414/3886] util/amdfwtool/data_parse.c: Remove duplicate
 MP2_CFG_FILE

It was accidently added and is just dead code.
It doesn't change any functionality.

Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: I868b8c8725fc2240543fb1e9e379ecb5e1471ef4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89898
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
---
 util/amdfwtool/data_parse.c | 3 ---
 1 file changed, 3 deletions(-)

diff --git a/util/amdfwtool/data_parse.c b/util/amdfwtool/data_parse.c
index e508e9147b..8e75d652fa 100644
--- a/util/amdfwtool/data_parse.c
+++ b/util/amdfwtool/data_parse.c
@@ -626,9 +626,6 @@ static uint8_t find_register_fw_filename_bios_dir(char *fw_name, char *filename,
 		} else {
 			fw_type = AMD_BIOS_SKIP;
 		}
-	} else if (strcmp(fw_name, "PSP_MP2CFG_FILE") == 0) {
-		fw_type = AMD_BIOS_MP2_CFG;
-		subprog = 0;
 	} else {
 		fw_type = AMD_BIOS_INVALID;
 	}

From 8cc8f219bf253696a6f79555d13f00825df197a0 Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Thu, 30 Oct 2025 15:22:11 -0500
Subject: [PATCH 2415/3886] Documentation/drivers: Add ACPI five-level fan
 control documentation

Document the ACPI thermal zone pattern used across multiple mainboards
that implement five-level fan control via power resource state machines.

This pattern is used by 9 mainboards including Google Chromebooks
(beltino, jecht variants), Samsung stumpy, and Intel reference boards
(wtm2, baskingridge, emeraldlake2).

The documentation covers:
- Power resource state machine implementation
- Temperature management via PECI/SuperIO
- Active and passive cooling policies
- Critical FNP4._OFF no-op requirement for Windows compatibility
- Implementation variations and checklist for new boards

Initial framework generated by Cursor AI, heavily edited thereafter.

Change-Id: I4174a4552c97fb85a894f5362948d57057cacb81
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89843
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
---
 Documentation/drivers/acpi_fan_control.md | 387 ++++++++++++++++++++++
 Documentation/drivers/index.md            |   1 +
 2 files changed, 388 insertions(+)
 create mode 100644 Documentation/drivers/acpi_fan_control.md

diff --git a/Documentation/drivers/acpi_fan_control.md b/Documentation/drivers/acpi_fan_control.md
new file mode 100644
index 0000000000..a38f270dcf
--- /dev/null
+++ b/Documentation/drivers/acpi_fan_control.md
@@ -0,0 +1,387 @@
+# ACPI Active Cooling with Five-Level Fan Control
+
+## Overview
+
+This document describes an ACPI-based thermal management pattern used across multiple coreboot mainboards. The implementation uses ACPI thermal zones with active cooling policies to control fan speed based on CPU temperature through a five-level power resource state machine.
+
+This pattern is particularly prevalent on Intel-based mainboards using SuperIO environmental controllers for fan PWM control.
+
+## Mainboards Using This Pattern
+
+The following mainboards implement this five-level ACPI fan control pattern:
+
+### Google Chromebooks
+- **google/beltino** - Haswell Chromebox
+  - All variants (mccloud, monroe, panther, tricky, zako) use a single implementation
+- **google/jecht** - Broadwell Chromebox
+  - Each variant (jecht, rikku, guado, tidus) has a unique implementation
+
+### Samsung
+- **samsung/stumpy** - Sandy Bridge Chromebox
+
+### Intel Reference Boards
+- **intel/wtm2** - Haswell ULT reference board
+- **intel/baskingridge** - Haswell desktop reference board
+- **intel/emeraldlake2** - Ivy Bridge reference board
+
+## Architecture
+
+### Hardware Components
+
+Common hardware elements across implementations:
+
+- **Temperature Sensor**: SuperIO TMPIN3 reads CPU temperature via PECI (Platform Environment Control Interface)
+- **Fan Controller**: SuperIO Environmental Controller (ENVC) with PWM output
+  - Fan2 (F2PS) on Google Chromebooks
+  - Fan3 (F3PS) on Intel/Samsung boards
+- **CPU**: Provides temperature data as an offset from Tj_max (maximum junction temperature)
+
+### ACPI Components
+
+- **Thermal Zone**: `\_TZ.THRM` - Main thermal management zone
+- **Fan Devices**: `FAN0` through `FAN4` - Five fan speed levels
+- **Power Resources**: `FNP0` through `FNP4` - Control fan state transitions
+- **Active Cooling Levels**: `_AC0` through `_AC4` - Temperature thresholds for each fan level
+
+## Fan Speed Levels
+
+The system implements **5 fan speed levels** (0-4), where:
+
+- **Level 0**: Maximum fan speed (highest cooling, activated at highest temperature)
+- **Level 1**: High fan speed
+- **Level 2**: Medium fan speed
+- **Level 3**: Low fan speed
+- **Level 4**: Minimum fan speed (idle/baseline cooling, default state)
+
+The system starts at **Level 4** (minimum speed) and increases to lower-numbered levels as temperature rises.
+
+## Temperature Management
+
+### Temperature Reading Process
+
+1. **Raw PECI Reading**: Read from `\_SB.PCI0.LPCB.SIO.ENVC.TIN3`
+   - Returns a value representing offset from Tj_max
+   - Value 0x80 indicates "no reading available"
+   - Values 0 or 255 are invalid
+
+2. **Temperature Calculation**:
+   ```
+   actual_temperature = Tj_max - (255 - raw_value)
+   ```
+
+3. **Conversion to ACPI Format**: Convert from Celsius to deci-Kelvin:
+   ```
+   deci_kelvin = (celsius * 10) + 2732
+   ```
+
+### Critical Temperature Handling
+
+Most implementations include safety logic in the `_TMP` method:
+- If temperature reaches `\TMAX` (Tj_max), logs a critical event
+- Waits 1 second for sensor re-poll
+- Re-reads temperature to confirm
+- Reports the current temperature to the OS
+
+### Temperature Thresholds
+
+Thresholds are defined in board-specific headers (typically `thermal.h`):
+
+- `FAN0_THRESHOLD_ON/OFF` - Trigger points for maximum fan speed
+- `FAN1_THRESHOLD_ON/OFF` - Trigger points for high fan speed
+- `FAN2_THRESHOLD_ON/OFF` - Trigger points for medium fan speed
+- `FAN3_THRESHOLD_ON/OFF` - Trigger points for low fan speed
+- `FAN4_PWM` - PWM value for minimum fan speed
+
+Each level has hysteresis (different ON/OFF thresholds) to prevent rapid cycling.
+
+## Active Cooling Implementation
+
+### Active Cooling Methods (`_ACx`)
+
+Each `_ACx` method returns a temperature threshold:
+- When system temperature **exceeds** the threshold, the OS activates the corresponding fan level
+- When temperature **falls below** the threshold, the OS may deactivate that level
+
+**Hysteresis Logic**:
+```
+Method (_AC0) {
+    If (\FLVL <= 0) {
+        Return (CTOK (FAN0_THRESHOLD_OFF))  // Higher temp to turn off
+    } Else {
+        Return (CTOK (FAN0_THRESHOLD_ON))   // Lower temp to turn on
+    }
+}
+```
+
+This prevents oscillation by requiring different temperatures to activate vs. deactivate a fan level.
+
+### Active Cooling Lists (`_ALx`)
+
+Each `_ALx` associates a cooling threshold with a fan device:
+```
+Name (_AL0, Package () { FAN0 })  // FAN0 activated at _AC0 threshold
+Name (_AL1, Package () { FAN1 })  // FAN1 activated at _AC1 threshold
+Name (_AL2, Package () { FAN2 })  // FAN2 activated at _AC2 threshold
+Name (_AL3, Package () { FAN3 })  // FAN3 activated at _AC3 threshold
+Name (_AL4, Package () { FAN4 })  // FAN4 activated at _AC4 threshold
+```
+
+## Power Resource State Machine
+
+Each fan level has an associated power resource (`FNP0` through `FNP4`) that manages state transitions.
+
+### State Transitions
+
+**FNP0-FNP3** (Levels 0-3):
+- `_STA`: Returns 1 (ON) if `\FLVL <= level`, else 0 (OFF)
+- `_ON`: Transitions **to** this level from a higher-numbered level
+- `_OFF`: Transitions **away** from this level to the next higher-numbered level
+
+Example for FNP0 (maximum cooling):
+```
+PowerResource (FNP0, 0, 0) {
+    Method (_STA) {
+        If (\FLVL <= 0) { Return (1) }  // Active if at max cooling
+        Else { Return (0) }
+    }
+    Method (_ON) {
+        If (!_STA ()) {                  // If not already active
+            \FLVL = 0                     // Set to max cooling
+            \_SB.PCI0.LPCB.SIO.ENVC.F2PS = FAN0_PWM  // Set fan PWM
+            Notify (\_TZ.THRM, 0x81)       // Notify thermal zone
+        }
+    }
+    Method (_OFF) {
+        If (_STA ()) {                   // If currently active
+            \FLVL = 1                     // Transition to level 1
+            \_SB.PCI0.LPCB.SIO.ENVC.F2PS = FAN1_PWM  // Set corresponding PWM
+            Notify (\_TZ.THRM, 0x81)       // Notify thermal zone
+        }
+    }
+}
+```
+
+**FNP4** (Minimum cooling - Level 4):
+- `_STA`: Returns 1 if `\FLVL <= 4` (always true in normal operation)
+- `_ON`: Transitions to minimum cooling state
+- `_OFF`: **No-op** - This is the minimum state, cannot transition lower
+
+### Critical: FNP4._OFF Must Be a No-Op
+
+This is **essential for Windows compatibility**:
+
+**Problem**: Early implementations had `_OFF` setting `\FLVL = 4` and PWM values, identical to `_ON`. This violated ACPI power resource requirements:
+- After `_ON` is called, `_STA` must eventually return 1 (ON)
+- After `_OFF` is called, `_STA` must eventually return 0 (OFF)
+
+Since both methods resulted in `\FLVL = 4`, and `_STA` returns 1 when `\FLVL <= 4`, the power resource could never properly transition to OFF state.
+
+**Solution**: Make `_OFF` a no-op since FAN4 is the minimum cooling state:
+```
+PowerResource (FNP4, 0, 0) {
+    Method (_STA) {
+        If (\FLVL <= 4) { Return (1) }
+        Else { Return (0) }
+    }
+    Method (_ON) {
+        If (!_STA ()) {
+            \FLVL = 4
+            \_SB.PCI0.LPCB.SIO.ENVC.F2PS = FAN4_PWM
+            Notify (\_TZ.THRM, 0x81)
+        }
+    }
+    Method (_OFF) {
+        // FAN4 is the minimum cooling state (idle/lowest fan speed)
+        // There is no lower state to transition to, so _OFF is a no-op
+        // to maintain proper ACPI power resource state machine semantics
+    }
+}
+```
+
+This maintains proper ACPI state machine semantics and ensures Windows compatibility while maintaining Linux compatibility.
+
+## Passive Cooling
+
+In addition to active (fan-based) cooling, most implementations support passive cooling:
+
+- `_PSV`: Returns passive cooling threshold temperature
+- `_PSL`: Returns list of processors to throttle
+- `_TC1`, `_TC2`: Thermal constants for passive cooling algorithm
+- `_TSP`: Thermal sampling period (typically 20 deciseconds = 2 seconds)
+
+When temperature exceeds `_PSV` threshold, the OS throttles CPUs listed in `_PSL` to reduce heat generation.
+
+## Polling and Notification
+
+- `_TZP`: Thermal zone polling period (typically 100 deciseconds = 10 seconds)
+  - OS polls `_TMP` at this interval to check temperature
+
+- `Notify (\_TZ.THRM, 0x81)`: Thermal zone change notification
+  - Sent whenever fan level changes
+  - Tells OS to re-evaluate thermal zone immediately
+
+## Initialization
+
+The `_INI` method runs when the thermal zone is initialized:
+
+```
+Method (_INI) {
+    \FLVL = 4                             // Start at minimum cooling
+    \_SB.PCI0.LPCB.SIO.ENVC.F2PS = FAN4_PWM  // Set initial fan PWM
+    Notify (\_TZ.THRM, 0x81)               // Initial notification
+}
+```
+
+## Operating System Interaction
+
+### Thermal Policy Flow
+
+1. **OS boots** → Executes `_INI` → Fan starts at Level 4
+2. **OS polls `_TMP`** periodically → Gets current temperature
+3. **Temperature rises** → Exceeds `_AC3` threshold
+4. **OS calls `FAN3._ON`** → Power resource FNP3 activated → `\FLVL = 3`
+5. **Temperature continues rising** → Exceeds `_AC2` threshold
+6. **OS calls `FAN2._ON`** → Power resource FNP2 activated → `\FLVL = 2`
+7. **Temperature drops** → Falls below `_AC2` threshold
+8. **OS calls `FAN2._OFF`** → `\FLVL = 3` → Returns to Level 3
+9. **Cycle continues** based on temperature changes
+
+### Critical Temperature
+
+If temperature reaches `_CRT` threshold:
+- OS initiates emergency shutdown
+- Prevents hardware damage from overheating
+
+## Global Variables
+
+Standard variables used across implementations:
+
+- `\FLVL`: Current fan level (0-4)
+- `\TMAX`: Maximum junction temperature (Tj_max)
+- `\TCRT`: Critical shutdown temperature
+- `\TPSV`: Passive cooling threshold temperature
+
+## Configuration
+
+Fan thresholds and PWM values are defined in board-specific headers, typically:
+```
+src/mainboard/<vendor>/<board>/include/thermal.h
+```
+or
+```
+src/mainboard/<vendor>/<board>/variants/<variant>/include/variant/thermal.h
+```
+
+Example configuration:
+```c
+#define FAN0_THRESHOLD_ON   75  // Temperature to activate max fan (°C)
+#define FAN0_THRESHOLD_OFF  65  // Temperature to deactivate max fan (°C)
+#define FAN0_PWM            0xFF // PWM duty cycle value (max)
+
+#define FAN1_THRESHOLD_ON   65
+#define FAN1_THRESHOLD_OFF  55
+#define FAN1_PWM            0xC0
+
+#define FAN2_THRESHOLD_ON   55
+#define FAN2_THRESHOLD_OFF  45
+#define FAN2_PWM            0x80
+
+#define FAN3_THRESHOLD_ON   45
+#define FAN3_THRESHOLD_OFF  35
+#define FAN3_PWM            0x40
+
+#define FAN4_PWM            0x20  // Idle fan speed
+```
+
+## Implementation Variations
+
+While the core pattern is consistent, there are some variations:
+
+### PWM Output Selection
+- **Google boards**: Use Fan2 PWM (`F2PS`)
+- **Intel/Samsung boards**: Use Fan3 PWM (`F3PS`)
+
+### Guard Checks
+Some implementations wrap state changes with `_STA()` checks:
+```
+Method (_ON) {
+    If (!_STA ()) {  // Only change state if not already active
+        // ... state change
+    }
+}
+```
+
+Others omit the guard and always perform the state change.
+
+### Temperature Reading
+- Most implementations read from SuperIO TMPIN3 via PECI
+- Some (like intel/wtm2) use simplified stub implementations for reference
+
+### Dynamic Thermal Tables
+The google/jecht/tidus variant includes multiple thermal tables that can be switched based on system temperature sensors, allowing more sophisticated thermal management.
+
+## Compatibility Notes
+
+### Linux
+- More lenient ACPI parser
+- Tolerates minor state machine violations
+- Worked with buggy FNP4._OFF implementations
+
+### Windows
+- Stricter ACPI compliance checking
+- Requires proper power resource state machine behavior
+- **Requires the FNP4._OFF no-op fix** to function correctly
+- May disable thermal zone entirely if ACPI violations detected
+
+## Debugging
+
+To debug fan control issues:
+
+1. **Check ACPI errors**: Look for thermal zone errors in OS logs
+   - Linux: `dmesg | grep -i acpi` or check `/sys/class/thermal/`
+   - Windows: Event Viewer → System → ACPI errors
+
+2. **Monitor temperature**: Use OS tools to check `_TMP` readings
+   - Linux: `/sys/class/thermal/thermal_zone*/temp`
+   - Windows: HWiNFO64, HWMonitor
+
+3. **Check fan level**: Monitor `\FLVL` value (ACPI debugger or custom logging)
+
+4. **Verify thresholds**: Ensure threshold values are appropriate for the hardware
+
+5. **Test state transitions**: Verify each fan level activates at correct temperature
+
+6. **ACPI table inspection**: Decompile DSDT/SSDT tables with `acpidump` and `iasl` to verify implementation
+
+## Implementation Checklist
+
+When implementing this pattern on a new board:
+
+- [ ] Define all 5 fan threshold pairs (ON/OFF) with appropriate hysteresis
+- [ ] Define PWM values for all 5 fan levels
+- [ ] Implement temperature sensor reading (typically PECI via SuperIO)
+- [ ] Implement CTOK conversion method (°C to deci-Kelvin)
+- [ ] Create all 5 PowerResource objects (FNP0-FNP4)
+- [ ] **Critical**: Ensure FNP4._OFF is a no-op (not setting state)
+- [ ] Create all 5 Fan Device objects (FAN0-FAN4) with correct `_PR0` references
+- [ ] Implement _ACx methods with hysteresis logic
+- [ ] Define _ALx packages linking to fan devices
+- [ ] Implement _INI to set initial state
+- [ ] Implement _TMP with error handling
+- [ ] Define _CRT, _PSV, _PSL for critical/passive cooling
+- [ ] Set appropriate _TZP polling interval
+- [ ] Test on both Linux and Windows
+
+## References
+
+- [ACPI Specification 6.5 - Thermal Management](https://uefi.org/specs/ACPI/6.5/)
+- [ACPI Specification - ThermalZone Objects](https://uefi.org/specs/ACPI/6.5/11_Thermal_Management.html)
+- [ACPI Specification - PowerResource Objects](https://uefi.org/specs/ACPI/6.5/07_Power_and_Performance_Mgmt.html#power-resources)
+- Intel PECI Specification
+- SuperIO vendor datasheets (ITE, Nuvoton, Winbond, etc.)
+
+## See Also
+
+- [Intel DPTF](dptf.md) - More sophisticated Intel Dynamic Platform and Thermal Framework
+- [ACPI GPIO Documentation](../acpi/gpio.md)
+
diff --git a/Documentation/drivers/index.md b/Documentation/drivers/index.md
index a797416008..381685e068 100644
--- a/Documentation/drivers/index.md
+++ b/Documentation/drivers/index.md
@@ -18,6 +18,7 @@ Some of the drivers currently available include:
 ```{toctree}
 :maxdepth: 1
 
+ACPI Five-Level Fan Control <acpi_fan_control.md>
 CFR <cfr.md>
 CFR use within coreboot <cfr_internal.md>
 Intel DPTF <dptf.md>

From 76a48b51581a3fede769947a1b7bf48389e58021 Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Thu, 30 Oct 2025 17:20:27 -0500
Subject: [PATCH 2416/3886] mb/google/beltino: Remove unused GNVS fan
 configuration

Remove unused GNVS fan thresholds, PWM assignments from acpi_tables.c.

The Beltino thermal.asl uses compile-time macros (FAN*_THRESHOLD_OFF,
FAN*_THRESHOLD_ON, FAN*_PWM) directly from variant/thermal.h, not
runtime GNVS variables. The GNVS assignments were never consumed by
the ACPI code and just wasted memory.

Retained GNVS values that ARE used:
- tpmp: TPM presence flag
- tcrt: Critical temperature (\TCRT)
- tpsv: Passive temperature (\TPSV)
- tmax: Tj_max (\TMAX)

Removed unused GNVS values:
- f{0-4}{of,on,pw}: Fan thresholds and PWM values (24 values total)
- flvl: Fan level (unused, ACPI uses \FLVL local variable)

This matches the google/jecht approach which also uses compile-time
macros and only sets the essential GNVS thermal values.

No functional change - the ACPI thermal zone behavior is identical.

Change-Id: I703b7d8e424d4451abf0781b4491b813be216bc7
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89844
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
---
 src/mainboard/google/beltino/acpi_tables.c | 21 ---------------------
 1 file changed, 21 deletions(-)

diff --git a/src/mainboard/google/beltino/acpi_tables.c b/src/mainboard/google/beltino/acpi_tables.c
index 83e3165eef..41dc54d642 100644
--- a/src/mainboard/google/beltino/acpi_tables.c
+++ b/src/mainboard/google/beltino/acpi_tables.c
@@ -11,28 +11,7 @@ void mainboard_fill_gnvs(struct global_nvs *gnvs)
 	/* TPM Present */
 	gnvs->tpmp = 1;
 
-	gnvs->f4of = FAN4_THRESHOLD_OFF;
-	gnvs->f4on = FAN4_THRESHOLD_ON;
-	gnvs->f4pw = FAN4_PWM;
-
-	gnvs->f3of = FAN3_THRESHOLD_OFF;
-	gnvs->f3on = FAN3_THRESHOLD_ON;
-	gnvs->f3pw = FAN3_PWM;
-
-	gnvs->f2of = FAN2_THRESHOLD_OFF;
-	gnvs->f2on = FAN2_THRESHOLD_ON;
-	gnvs->f2pw = FAN2_PWM;
-
-	gnvs->f1of = FAN1_THRESHOLD_OFF;
-	gnvs->f1on = FAN1_THRESHOLD_ON;
-	gnvs->f1pw = FAN1_PWM;
-
-	gnvs->f0of = FAN0_THRESHOLD_OFF;
-	gnvs->f0on = FAN0_THRESHOLD_ON;
-	gnvs->f0pw = FAN0_PWM;
-
 	gnvs->tcrt = CRITICAL_TEMPERATURE;
 	gnvs->tpsv = PASSIVE_TEMPERATURE;
 	gnvs->tmax = MAX_TEMPERATURE;
-	gnvs->flvl = 5;
 }

From 9fa2d55987131772a988c0f8ef8d38f0feccae7e Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Thu, 30 Oct 2025 16:02:02 -0500
Subject: [PATCH 2417/3886] mb/google/beltino: Fix thermal configuration issues
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Fix critical thermal management problems across all Beltino variants
while preserving the quiet-at-idle design intent:

- Overlapping temperature thresholds causing fan oscillations
- CRITICAL_TEMPERATURE equal to Tj_max (no safety margin)
- Poor threshold spacing creating thermal management gaps

Variant-specific fixes:

panther (CRITICAL SAFETY ISSUE):
- CRITICAL_TEMPERATURE: 100°C → 98°C
  * Was equal to Tj_max, leaving zero safety margin
  * System could reach thermal limits before clean shutdown
  * Risk of hardware damage
- Reorganize thresholds: eliminate 25°C gap between levels
  * Old: FAN3:40-50, FAN2:75-83 (25°C gap!), FAN1:86-90, FAN0:93-96
  * New: FAN3:40-50, FAN2:55-67, FAN1:67-75, FAN0:85-90
  * Progressive response instead of sudden jumps
- Adjust PWM values for smoother progression

zako (SEVERE OPERATIONAL ISSUE):
- Fix catastrophic overlapping thresholds
  * All 4 active fan levels tried to activate simultaneously (50-52°C)
  * Old: FAN3:48-52, FAN2:50-55, FAN1:52-58, FAN0:55-60
  * Fan would oscillate wildly between speeds
- New: FAN3:40-50, FAN2:55-67, FAN1:67-75, FAN0:85-90
  * Proper discrete levels with no overlaps
  * 8-12°C hysteresis prevents oscillation

monroe:
- Fix overlapping thresholds across all levels
  * Old: FAN3:45-58, FAN2:52-64, FAN1:59-68, FAN0:66-79
  * FAN2 started before FAN3 stopped, same for FAN1/FAN0
- New: Clean discrete levels with proper spacing

mccloud:
- Raise FAN3 start: 35-40°C → 40-50°C
  * 35°C is barely above ambient, causes unnecessary noise
- Standardize remaining thresholds to match other variants

tricky:
- Already had reasonable thresholds, no changes needed

Design philosophy:
- Keep FAN4_PWM = 0x00 (fan OFF at idle)
  * Chromeboxes are designed as quiet desktop devices
  * Passive cooling adequate below 50°C
  * Silent operation at idle/light loads
  * Fan only activates when thermal load requires it (>40-50°C)

All variants now follow proper thermal management:
- Silent at idle (fan OFF until >40-50°C)
- Progressive thresholds: 40-50, 55-67, 67-75, 85-90°C
- No overlapping ranges (discrete fan levels)
- 8-12°C hysteresis (prevents oscillation)
- 2°C safety margin below Tj_max for critical shutdown

These changes fix the actual bugs (overlaps and safety margins) while
respecting the original quiet-desktop design intent.

TEST=build/boot panther, verify fan remains silent at idle, activates
smoothly when needed, no oscillations, proper shutdown margin
maintained.

Change-Id: Ibcd138dfb16b13dfa2ef3a3fcac2556d7daaf0c2
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89845
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
---
 src/mainboard/google/beltino/acpi/thermal.asl |  6 +---
 .../mccloud/include/variant/thermal.h         | 26 ++++++++---------
 .../variants/monroe/include/variant/thermal.h | 28 +++++++++----------
 .../panther/include/variant/thermal.h         | 24 ++++++++--------
 .../variants/tricky/include/variant/thermal.h |  4 +--
 .../variants/zako/include/variant/thermal.h   | 24 ++++++++--------
 6 files changed, 49 insertions(+), 63 deletions(-)

diff --git a/src/mainboard/google/beltino/acpi/thermal.asl b/src/mainboard/google/beltino/acpi/thermal.asl
index 40564c3ad7..7e9d413c59 100644
--- a/src/mainboard/google/beltino/acpi/thermal.asl
+++ b/src/mainboard/google/beltino/acpi/thermal.asl
@@ -141,11 +141,7 @@ Scope (\_TZ)
 		}
 
 		Method (_AC4) {
-			If (\FLVL <= 4) {
-				Return (CTOK (FAN4_THRESHOLD_OFF))
-			} Else {
-				Return (CTOK (FAN4_THRESHOLD_ON))
-			}
+			Return (CTOK (0))
 		}
 
 		Name (_AL0, Package () { FAN0 })
diff --git a/src/mainboard/google/beltino/variants/mccloud/include/variant/thermal.h b/src/mainboard/google/beltino/variants/mccloud/include/variant/thermal.h
index f4c0474329..4a84032609 100644
--- a/src/mainboard/google/beltino/variants/mccloud/include/variant/thermal.h
+++ b/src/mainboard/google/beltino/variants/mccloud/include/variant/thermal.h
@@ -3,29 +3,27 @@
 #ifndef THERMAL_H
 #define THERMAL_H
 
-/* Fan is OFF */
-#define FAN4_THRESHOLD_OFF	0
-#define FAN4_THRESHOLD_ON	0
+/* Fan is OFF at idle (passive cooling) */
 #define FAN4_PWM		0x00
 
 /* Fan is at LOW speed */
-#define FAN3_THRESHOLD_OFF	35
-#define FAN3_THRESHOLD_ON	40
-#define FAN3_PWM		0x88
+#define FAN3_THRESHOLD_OFF	40
+#define FAN3_THRESHOLD_ON	50
+#define FAN3_PWM		0x68
 
 /* Fan is at MEDIUM speed */
-#define FAN2_THRESHOLD_OFF	44
-#define FAN2_THRESHOLD_ON	48
-#define FAN2_PWM		0x94
+#define FAN2_THRESHOLD_OFF	55
+#define FAN2_THRESHOLD_ON	67
+#define FAN2_PWM		0x84
 
 /* Fan is at HIGH speed */
-#define FAN1_THRESHOLD_OFF	53
-#define FAN1_THRESHOLD_ON	58
-#define FAN1_PWM		0xb5
+#define FAN1_THRESHOLD_OFF	67
+#define FAN1_THRESHOLD_ON	75
+#define FAN1_PWM		0xa5
 
 /* Fan is at FULL speed */
-#define FAN0_THRESHOLD_OFF	65
-#define FAN0_THRESHOLD_ON	70
+#define FAN0_THRESHOLD_OFF	85
+#define FAN0_THRESHOLD_ON	90
 #define FAN0_PWM		0xc4
 
 /* Temperature which OS will shutdown at */
diff --git a/src/mainboard/google/beltino/variants/monroe/include/variant/thermal.h b/src/mainboard/google/beltino/variants/monroe/include/variant/thermal.h
index c2a2ef09b8..0074f0dd91 100644
--- a/src/mainboard/google/beltino/variants/monroe/include/variant/thermal.h
+++ b/src/mainboard/google/beltino/variants/monroe/include/variant/thermal.h
@@ -3,30 +3,28 @@
 #ifndef THERMAL_H
 #define THERMAL_H
 
-/* Fan is OFF */
-#define FAN4_THRESHOLD_OFF	0
-#define FAN4_THRESHOLD_ON	0
+/* Fan is OFF at idle (passive cooling) */
 #define FAN4_PWM		0x00
 
 /* Fan is at LOW speed */
-#define FAN3_THRESHOLD_OFF	45
-#define FAN3_THRESHOLD_ON	58
-#define FAN3_PWM		0x40
+#define FAN3_THRESHOLD_OFF	40
+#define FAN3_THRESHOLD_ON	50
+#define FAN3_PWM		0x68
 
 /* Fan is at MEDIUM speed */
-#define FAN2_THRESHOLD_OFF	52
-#define FAN2_THRESHOLD_ON	64
-#define FAN2_PWM		0x80
+#define FAN2_THRESHOLD_OFF	55
+#define FAN2_THRESHOLD_ON	67
+#define FAN2_PWM		0x84
 
 /* Fan is at HIGH speed */
-#define FAN1_THRESHOLD_OFF	59
-#define FAN1_THRESHOLD_ON	68
-#define FAN1_PWM		0xb3
+#define FAN1_THRESHOLD_OFF	67
+#define FAN1_THRESHOLD_ON	75
+#define FAN1_PWM		0xa3
 
 /* Fan is at FULL speed */
-#define FAN0_THRESHOLD_OFF	66
-#define FAN0_THRESHOLD_ON	79
-#define FAN0_PWM		0xff
+#define FAN0_THRESHOLD_OFF	85
+#define FAN0_THRESHOLD_ON	90
+#define FAN0_PWM		0xc4
 
 /* Temperature which OS will shutdown at */
 #define CRITICAL_TEMPERATURE	98
diff --git a/src/mainboard/google/beltino/variants/panther/include/variant/thermal.h b/src/mainboard/google/beltino/variants/panther/include/variant/thermal.h
index 27c6c33756..07f7c9f075 100644
--- a/src/mainboard/google/beltino/variants/panther/include/variant/thermal.h
+++ b/src/mainboard/google/beltino/variants/panther/include/variant/thermal.h
@@ -3,9 +3,7 @@
 #ifndef THERMAL_H
 #define THERMAL_H
 
-/* Fan is OFF */
-#define FAN4_THRESHOLD_OFF	0
-#define FAN4_THRESHOLD_ON	0
+/* Fan is OFF at idle (passive cooling) */
 #define FAN4_PWM		0x00
 
 /* Fan is at LOW speed */
@@ -14,22 +12,22 @@
 #define FAN3_PWM		0x6b
 
 /* Fan is at MEDIUM speed */
-#define FAN2_THRESHOLD_OFF	75
-#define FAN2_THRESHOLD_ON	83
-#define FAN2_PWM		0xcc
+#define FAN2_THRESHOLD_OFF	55
+#define FAN2_THRESHOLD_ON	67
+#define FAN2_PWM		0x86
 
 /* Fan is at HIGH speed */
-#define FAN1_THRESHOLD_OFF	86
-#define FAN1_THRESHOLD_ON	90
-#define FAN1_PWM		0xe5
+#define FAN1_THRESHOLD_OFF	67
+#define FAN1_THRESHOLD_ON	75
+#define FAN1_PWM		0xa8
 
 /* Fan is at FULL speed */
-#define FAN0_THRESHOLD_OFF	93
-#define FAN0_THRESHOLD_ON	96
-#define FAN0_PWM		0xff
+#define FAN0_THRESHOLD_OFF	85
+#define FAN0_THRESHOLD_ON	90
+#define FAN0_PWM		0xdc
 
 /* Temperature which OS will shutdown at */
-#define CRITICAL_TEMPERATURE	100
+#define CRITICAL_TEMPERATURE	98
 
 /* Temperature which OS will throttle CPU */
 #define PASSIVE_TEMPERATURE	90
diff --git a/src/mainboard/google/beltino/variants/tricky/include/variant/thermal.h b/src/mainboard/google/beltino/variants/tricky/include/variant/thermal.h
index 68db6b89e6..791f2dd279 100644
--- a/src/mainboard/google/beltino/variants/tricky/include/variant/thermal.h
+++ b/src/mainboard/google/beltino/variants/tricky/include/variant/thermal.h
@@ -3,9 +3,7 @@
 #ifndef THERMAL_H
 #define THERMAL_H
 
-/* Fan is OFF */
-#define FAN4_THRESHOLD_OFF	0
-#define FAN4_THRESHOLD_ON	0
+/* Fan is OFF at idle (passive cooling) */
 #define FAN4_PWM		0x00
 
 /* Fan is at LOW speed */
diff --git a/src/mainboard/google/beltino/variants/zako/include/variant/thermal.h b/src/mainboard/google/beltino/variants/zako/include/variant/thermal.h
index 5006b64983..7a1cbc77ec 100644
--- a/src/mainboard/google/beltino/variants/zako/include/variant/thermal.h
+++ b/src/mainboard/google/beltino/variants/zako/include/variant/thermal.h
@@ -3,30 +3,28 @@
 #ifndef THERMAL_H
 #define THERMAL_H
 
-/* Fan is OFF */
-#define FAN4_THRESHOLD_OFF	0
-#define FAN4_THRESHOLD_ON	0
-#define FAN4_PWM		0x4c
+/* Fan is OFF at idle (passive cooling) */
+#define FAN4_PWM		0x00
 
 /* Fan is at LOW speed */
-#define FAN3_THRESHOLD_OFF	48
-#define FAN3_THRESHOLD_ON	52
+#define FAN3_THRESHOLD_OFF	40
+#define FAN3_THRESHOLD_ON	50
 #define FAN3_PWM		0x6d
 
 /* Fan is at MEDIUM speed */
-#define FAN2_THRESHOLD_OFF	50
-#define FAN2_THRESHOLD_ON	55
+#define FAN2_THRESHOLD_OFF	55
+#define FAN2_THRESHOLD_ON	67
 #define FAN2_PWM		0x7c
 
 /* Fan is at HIGH speed */
-#define FAN1_THRESHOLD_OFF	52
-#define FAN1_THRESHOLD_ON	58
+#define FAN1_THRESHOLD_OFF	67
+#define FAN1_THRESHOLD_ON	75
 #define FAN1_PWM		0xa3
 
 /* Fan is at FULL speed */
-#define FAN0_THRESHOLD_OFF	55
-#define FAN0_THRESHOLD_ON	60
-#define FAN0_PWM		0xba
+#define FAN0_THRESHOLD_OFF	85
+#define FAN0_THRESHOLD_ON	90
+#define FAN0_PWM		0xdc
 
 /* Temperature which OS will shutdown at */
 #define CRITICAL_TEMPERATURE	98

From 288889cd9827c1594da654d9493002c661575085 Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Thu, 30 Oct 2025 16:02:56 -0500
Subject: [PATCH 2418/3886] mb/google/jecht: Fix thermal configuration issues
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Fix thermal management issues across Jecht variants.

tidus (CRITICAL):
- PASSIVE_TEMPERATURE: 105°C → 95°C
  * Was higher than CRITICAL_TEMPERATURE (103°C)
  * OS would initiate emergency shutdown before CPU throttling
  * Passive CPU throttling would NEVER engage
  * Now activates at 95°C, well before critical shutdown at 103°C

guado:
- Fix threshold spacing and eliminate minor overlap
  * Old: FAN1:65-70, FAN0:90-100 (with FAN2 stopping at 67°C)
  * Had 2°C overlap between FAN1 and FAN2
- Standardize thresholds: FAN3:40-50, FAN2:55-67, FAN1:67-75, FAN0:85-90
- Adjust PWM values for consistent progression
  * FAN3: 0x55→0x62, FAN2: 0xa6→0x86, FAN1: 0xc0→0xa8, FAN0: 0xff→0xdc
  * More linear progression, better acoustic profile

rikku:
- Improve hysteresis (was only 5°C, can cause rapid switching)
  * Old: FAN3:42-47, FAN2:54-59, FAN1:66-71, FAN0:78-83
  * New: FAN3:40-50, FAN2:55-67, FAN1:67-75, FAN0:85-90
  * 8-12°C hysteresis prevents oscillation under varying loads
- Adjust PWM values for smoother progression
  * Old progression was too aggressive (0xa5, 0xb2, 0xc9, 0xd8)
  * New: 0x62, 0x86, 0xa8, 0xdc (more gradual)

All three variants now properly configured for Broadwell with
Tj_max=105°C:
- tidus: Critical passive cooling logic fixed
- guado/rikku: Aligned with jecht reference configuration
- No overlapping thresholds
- Proper hysteresis for stable operation
- Consistent PWM progression across variants

Note: jecht variant was already properly configured and serves as the
reference implementation for this thermal pattern.

TEST=build/boot Win10/Linux on google/guado, verify fan speeds work as
expected when varying the CPU load/temp.

Change-Id: I0502829665f373215e6be9aaf1c082abe0b613fe
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89846
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
---
 .../variants/guado/include/variant/thermal.h  | 16 ++++++-------
 .../variants/rikku/include/variant/thermal.h  | 24 +++++++++----------
 .../variants/tidus/include/variant/thermal.h  |  2 +-
 3 files changed, 21 insertions(+), 21 deletions(-)

diff --git a/src/mainboard/google/jecht/variants/guado/include/variant/thermal.h b/src/mainboard/google/jecht/variants/guado/include/variant/thermal.h
index 7dc4836982..7a98894663 100644
--- a/src/mainboard/google/jecht/variants/guado/include/variant/thermal.h
+++ b/src/mainboard/google/jecht/variants/guado/include/variant/thermal.h
@@ -11,22 +11,22 @@
 /* Fan is at LOW speed */
 #define FAN3_THRESHOLD_OFF	40
 #define FAN3_THRESHOLD_ON	50
-#define FAN3_PWM		0x55
+#define FAN3_PWM		0x62
 
 /* Fan is at MEDIUM speed */
 #define FAN2_THRESHOLD_OFF	55
 #define FAN2_THRESHOLD_ON	67
-#define FAN2_PWM		0xa6
+#define FAN2_PWM		0x86
 
 /* Fan is at HIGH speed */
-#define FAN1_THRESHOLD_OFF	65
-#define FAN1_THRESHOLD_ON	70
-#define FAN1_PWM		0xc0
+#define FAN1_THRESHOLD_OFF	67
+#define FAN1_THRESHOLD_ON	75
+#define FAN1_PWM		0xa8
 
 /* Fan is at FULL speed */
-#define FAN0_THRESHOLD_OFF	90
-#define FAN0_THRESHOLD_ON	100
-#define FAN0_PWM		0xff
+#define FAN0_THRESHOLD_OFF	85
+#define FAN0_THRESHOLD_ON	90
+#define FAN0_PWM		0xdc
 
 /* Temperature which OS will shutdown at */
 #define CRITICAL_TEMPERATURE	104
diff --git a/src/mainboard/google/jecht/variants/rikku/include/variant/thermal.h b/src/mainboard/google/jecht/variants/rikku/include/variant/thermal.h
index 58ca2f6d98..bc46ae39b3 100644
--- a/src/mainboard/google/jecht/variants/rikku/include/variant/thermal.h
+++ b/src/mainboard/google/jecht/variants/rikku/include/variant/thermal.h
@@ -9,24 +9,24 @@
 #define FAN4_PWM		0x4d
 
 /* Fan is at LOW speed */
-#define FAN3_THRESHOLD_OFF	42
-#define FAN3_THRESHOLD_ON	47
-#define FAN3_PWM		0xa5
+#define FAN3_THRESHOLD_OFF	40
+#define FAN3_THRESHOLD_ON	50
+#define FAN3_PWM		0x62
 
 /* Fan is at MEDIUM speed */
-#define FAN2_THRESHOLD_OFF	54
-#define FAN2_THRESHOLD_ON	59
-#define FAN2_PWM		0xb2
+#define FAN2_THRESHOLD_OFF	55
+#define FAN2_THRESHOLD_ON	67
+#define FAN2_PWM		0x86
 
 /* Fan is at HIGH speed */
-#define FAN1_THRESHOLD_OFF	66
-#define FAN1_THRESHOLD_ON	71
-#define FAN1_PWM		0xc9
+#define FAN1_THRESHOLD_OFF	67
+#define FAN1_THRESHOLD_ON	75
+#define FAN1_PWM		0xa8
 
 /* Fan is at FULL speed */
-#define FAN0_THRESHOLD_OFF	78
-#define FAN0_THRESHOLD_ON	83
-#define FAN0_PWM		0xd8
+#define FAN0_THRESHOLD_OFF	85
+#define FAN0_THRESHOLD_ON	90
+#define FAN0_PWM		0xdc
 
 /* Temperature which OS will shutdown at */
 #define CRITICAL_TEMPERATURE	100
diff --git a/src/mainboard/google/jecht/variants/tidus/include/variant/thermal.h b/src/mainboard/google/jecht/variants/tidus/include/variant/thermal.h
index 779b64049f..7d0597075e 100644
--- a/src/mainboard/google/jecht/variants/tidus/include/variant/thermal.h
+++ b/src/mainboard/google/jecht/variants/tidus/include/variant/thermal.h
@@ -88,7 +88,7 @@
 #define CRITICAL_TEMPERATURE		103
 
 /* Temperature which OS will throttle CPU */
-#define PASSIVE_TEMPERATURE		105
+#define PASSIVE_TEMPERATURE		95
 
 /* Tj_max value for calculating PECI CPU temperature */
 #define MAX_TEMPERATURE			105

From c27c9db51b3f6dc345df338187efb326b4a25649 Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Thu, 30 Oct 2025 16:04:52 -0500
Subject: [PATCH 2419/3886] mb/samsung/stumpy: Fix thermal configuration issues
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Fix multiple critical thermal management problems while preserving the
quiet-at-idle design:

- Overlapping temperature thresholds causing fan oscillations
- CRITICAL_TEMPERATURE equal to Tj_max (no safety margin)
- Multiple fan levels trying to activate simultaneously

Issues fixed:

1. CRITICAL_TEMPERATURE: 100°C → 98°C
   - Was equal to Tj_max, leaving zero safety margin
   - System could reach absolute thermal limits before shutdown
   - 2°C margin allows clean shutdown before CPU thermal protection

2. Fix overlapping temperature thresholds (PRIMARY BUG)
   - Previous config had all fan levels overlapping:
     * FAN3: 48-55°C
     * FAN2: 52-64°C (started at 52°C, before FAN3 stopped at 55°C)
     * FAN1: 60-68°C (started at 60°C, before FAN2 stopped at 64°C)
     * FAN0: 66-78°C (started at 66°C, before FAN1 stopped at 68°C)
   - Multiple fan levels would try to activate simultaneously
   - Caused rapid fan speed oscillations and unpredictable behavior

   New configuration with proper discrete levels:
     * FAN3: 45-55°C
     * FAN2: 55-65°C (starts when FAN3 stops)
     * FAN1: 65-72°C (starts when FAN2 stops)
     * FAN0: 72-80°C (starts when FAN1 stops)

3. Increase PWM values for better cooling at each level:
   - FAN3: 0x40 → 0xA0
   - FAN2: 0x80 → 0xB0
   - FAN1: 0xb0 → 0xC0
   - Provides more effective cooling progression

Design philosophy:
- Keep FAN4_PWM = 0x00 (fan OFF at idle)
  * Chromebox designed as quiet desktop device
  * Passive cooling adequate below 55°C
  * Silent operation at idle/light loads

Configuration now follows best practices:
- Silent at idle (fan OFF until >45-55°C)
- No overlapping thresholds (discrete fan levels)
- 8-10°C hysteresis (prevents oscillation)
- Proper safety margin below Tj_max
- Progressive PWM values for smooth transitions

These changes fix the actual bugs (overlaps and safety margins) while
maintaining the intended quiet operation at idle.

TEST=build/boot stumpy, verify fan remains silent at idle, activates
smoothly when needed, no oscillations, proper cooling maintained under
load.

Change-Id: I284cbe34348345589564ae77828b9beee0b0d9c0
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89847
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
---
 src/mainboard/samsung/stumpy/thermal.h | 24 ++++++++++++------------
 1 file changed, 12 insertions(+), 12 deletions(-)

diff --git a/src/mainboard/samsung/stumpy/thermal.h b/src/mainboard/samsung/stumpy/thermal.h
index fa8a08ed75..bfefc36d36 100644
--- a/src/mainboard/samsung/stumpy/thermal.h
+++ b/src/mainboard/samsung/stumpy/thermal.h
@@ -3,33 +3,33 @@
 #ifndef STUMPY_THERMAL_H
 #define STUMPY_THERMAL_H
 
-/* Fan is OFF */
+/* Fan is OFF at idle (passive cooling) */
 #define FAN4_THRESHOLD_OFF	0
 #define FAN4_THRESHOLD_ON	0
 #define FAN4_PWM		0x00
 
 /* Fan is at LOW speed */
-#define FAN3_THRESHOLD_OFF	48
+#define FAN3_THRESHOLD_OFF	45
 #define FAN3_THRESHOLD_ON	55
-#define FAN3_PWM		0x40
+#define FAN3_PWM		0xA0
 
 /* Fan is at MEDIUM speed */
-#define FAN2_THRESHOLD_OFF	52
-#define FAN2_THRESHOLD_ON	64
-#define FAN2_PWM		0x80
+#define FAN2_THRESHOLD_OFF	55
+#define FAN2_THRESHOLD_ON	65
+#define FAN2_PWM		0xB0
 
 /* Fan is at HIGH speed */
-#define FAN1_THRESHOLD_OFF	60
-#define FAN1_THRESHOLD_ON	68
-#define FAN1_PWM		0xb0
+#define FAN1_THRESHOLD_OFF	65
+#define FAN1_THRESHOLD_ON	72
+#define FAN1_PWM		0xC0
 
 /* Fan is at FULL speed */
-#define FAN0_THRESHOLD_OFF	66
-#define FAN0_THRESHOLD_ON	78
+#define FAN0_THRESHOLD_OFF	72
+#define FAN0_THRESHOLD_ON	80
 #define FAN0_PWM		0xff
 
 /* Temperature which OS will shutdown at */
-#define CRITICAL_TEMPERATURE	100
+#define CRITICAL_TEMPERATURE	98
 
 /* Temperature which OS will throttle CPU */
 #define PASSIVE_TEMPERATURE	90

From 66039a61f1e37252a43550b09e2ae04d3978538a Mon Sep 17 00:00:00 2001
From: Elyes Haouas <ehaouas@noos.fr>
Date: Wed, 5 Nov 2025 03:57:57 +0000
Subject: [PATCH 2420/3886] Revert "commonlib/endian: Restore -Warray-bounds at
 the end of file"

This reverts commit cfdaff3f7083a2d9ba7c9d7325232074746719a8.

Let's just keep using --param=min-pagesize=1024 in xcompile to sweep
the -Warray-bounds warnings under the rug in the coreboot tree.

Change-Id: I875cb140aacd44f1aaddd410de0f154af585b1c1
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89914
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
---
 src/commonlib/include/commonlib/endian.h | 1 -
 1 file changed, 1 deletion(-)

diff --git a/src/commonlib/include/commonlib/endian.h b/src/commonlib/include/commonlib/endian.h
index 114d1bd469..24b10826f4 100644
--- a/src/commonlib/include/commonlib/endian.h
+++ b/src/commonlib/include/commonlib/endian.h
@@ -252,5 +252,4 @@ static inline void zero_n(void *dest, size_t n)
 	memset(dest, 0, n);
 }
 
-#pragma GCC diagnostic pop /* restore -Warray-bounds */
 #endif /* _COMMONLIB_ENDIAN_H_ */

From d8bcf242c6f4170a40695e08bf88e51d49a2e435 Mon Sep 17 00:00:00 2001
From: Elyes Haouas <ehaouas@noos.fr>
Date: Wed, 5 Nov 2025 03:58:30 +0000
Subject: [PATCH 2421/3886] Revert "commonlib/endian: Silence GCC
 -Warray-bounds false positives"

This reverts commit 668ea970757c1191f408a32fc47be7684dea2e30.

Let's just keep using --param=min-pagesize=1024 in xcompile to sweep
the -Warray-bounds warnings under the rug in the coreboot tree.

Change-Id: I0f76c27bcbaac9d0927160fcab9cbf9aaefa9095
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89915
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/commonlib/include/commonlib/endian.h | 7 +------
 1 file changed, 1 insertion(+), 6 deletions(-)

diff --git a/src/commonlib/include/commonlib/endian.h b/src/commonlib/include/commonlib/endian.h
index 24b10826f4..971854c2b3 100644
--- a/src/commonlib/include/commonlib/endian.h
+++ b/src/commonlib/include/commonlib/endian.h
@@ -7,11 +7,6 @@
 #include <stdint.h>
 #include <string.h>
 
-/* GCC >= 12 triggers false positives (-Warray-bounds) on
- * deliberate low-level memory accesses here. */
-#pragma GCC diagnostic push
-#pragma GCC diagnostic ignored "-Warray-bounds"
-
 /* Endian agnostic functions working on single byte. */
 
 static inline uint8_t read_ble8(const void *src)
@@ -252,4 +247,4 @@ static inline void zero_n(void *dest, size_t n)
 	memset(dest, 0, n);
 }
 
-#endif /* _COMMONLIB_ENDIAN_H_ */
+#endif

From 9bea3130b5329d3de07a04066df5f0ec7ef2eb1c Mon Sep 17 00:00:00 2001
From: Cai Chen <chencai5@huaqin.corp-partner.google.com>
Date: Wed, 5 Nov 2025 10:42:13 +0800
Subject: [PATCH 2422/3886] mb/google/skywalker: Add AW88081 support for beep
 sound

Add the FW_CONFIG configuration for the audio amp.

BUG=b:426678967
TEST=emerge-skywalker coreboot chromeos-bootimage
BRANCH=Skywalker

Change-Id: Iaf461a26db92597883c8fa61f292bf14a145145c
Signed-off-by: Cai Chen <chencai5@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89913
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/google/skywalker/devicetree.cb |  1 +
 src/mainboard/google/skywalker/mainboard.c   | 13 +++++++++++++
 2 files changed, 14 insertions(+)

diff --git a/src/mainboard/google/skywalker/devicetree.cb b/src/mainboard/google/skywalker/devicetree.cb
index e2618d1f19..e02d63e686 100644
--- a/src/mainboard/google/skywalker/devicetree.cb
+++ b/src/mainboard/google/skywalker/devicetree.cb
@@ -8,6 +8,7 @@ fw_config
 	field AUDIO_AMP 25 27
 		option AMP_RT9123 0
 		option AMP_RT1019 1
+		option AMP_AW88081 2
 		option AMP_ALC5645 3
 		option AMP_CS35L51 4
 	end
diff --git a/src/mainboard/google/skywalker/mainboard.c b/src/mainboard/google/skywalker/mainboard.c
index 9a1b0adb89..e219861b63 100644
--- a/src/mainboard/google/skywalker/mainboard.c
+++ b/src/mainboard/google/skywalker/mainboard.c
@@ -50,6 +50,17 @@ static void configure_cs35l51(void)
 	printk(BIOS_INFO, "%s: AMP configuration done\n", __func__);
 }
 
+static void configure_aw88081(void)
+{
+	/* Set the SOC corresponding pin to I2S related function */
+	setup_i2s_speaker();
+
+	/* Init I2C bus timing register for audio codecs */
+	mtk_i2c_bus_init(I2C8, I2C_SPEED_STANDARD);
+
+	printk(BIOS_INFO, "%s: AMP configuration done\n", __func__);
+}
+
 static void configure_alc5645(void)
 {
 	/* SoC I2S */
@@ -75,6 +86,8 @@ static void configure_audio(void)
 	if (fw_config_probe(FW_CONFIG(AUDIO_AMP, AMP_RT9123)) ||
 	    fw_config_probe(FW_CONFIG(AUDIO_AMP, AMP_RT1019)))
 		configure_rt9123_rt1019();
+	else if (fw_config_probe(FW_CONFIG(AUDIO_AMP, AMP_AW88081)))
+		configure_aw88081();
 	else if (fw_config_probe(FW_CONFIG(AUDIO_AMP, AMP_ALC5645)))
 		configure_alc5645();
 	else if (fw_config_probe(FW_CONFIG(AUDIO_AMP, AMP_CS35L51)))

From f4af55a00853ff33bda36b3ddbabc38385cb0374 Mon Sep 17 00:00:00 2001
From: Luca Lai <luca.lai@lcfc.corp-partner.google.com>
Date: Mon, 3 Nov 2025 20:33:36 +0800
Subject: [PATCH 2423/3886] spd/lp5: Add SPD for MT62F1G32D2DS-020 WT:D and
 K3KL8L80EM-MGCV

Add  MT62F1G32D2DS-020 WT:D and K3KL8L80EM-MGCV in the
memory_parts.json and re-generate the SPD.

TEST=util/spd_tools/bin/spd_gen spd/lp5/memory_parts.json lp5

Change-Id: I014a847de2d5d53a7895460912c30b45959d3fbc
Signed-off-by: Luca Lai <luca.lai@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89874
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: YH Lin <yueherngl@google.com>
Reviewed-by: Derek Huang <derekhuang@google.com>
---
 spd/lp5/memory_parts.json                     | 22 +++++++++++++
 .../set-0/parts_spd_manifest.generated.txt    |  2 ++
 spd/lp5/set-0/spd-14.hex                      | 32 +++++++++++++++++++
 .../set-1/parts_spd_manifest.generated.txt    |  2 ++
 spd/lp5/set-1/spd-14.hex                      | 32 +++++++++++++++++++
 5 files changed, 90 insertions(+)
 create mode 100644 spd/lp5/set-0/spd-14.hex
 create mode 100644 spd/lp5/set-1/spd-14.hex

diff --git a/spd/lp5/memory_parts.json b/spd/lp5/memory_parts.json
index 31e6a6e723..d53a1c3cff 100644
--- a/spd/lp5/memory_parts.json
+++ b/spd/lp5/memory_parts.json
@@ -381,6 +381,28 @@
                 "speedMbps": 8533,
                 "lp5x": true
             }
+    },
+    {
+        "name":  "MT62F1G32D2DS-020 WT:D",
+        "attribs": {
+            "densityPerDieGb": 16,
+            "diesPerPackage": 2,
+            "bitWidthPerChannel": 16,
+            "ranksPerChannel": 2,
+            "speedMbps": 8533,
+            "lp5x": true
+        }
+    },
+    {
+        "name":  "K3KL8L80EM-MGCV",
+        "attribs": {
+            "densityPerDieGb": 16,
+            "diesPerPackage": 4,
+            "bitWidthPerChannel": 16,
+            "ranksPerChannel": 2,
+            "speedMbps": 8533,
+            "lp5x": true
+        }
     }
     ]
 }
diff --git a/spd/lp5/set-0/parts_spd_manifest.generated.txt b/spd/lp5/set-0/parts_spd_manifest.generated.txt
index 9ea9aca301..0d71bfb08a 100644
--- a/spd/lp5/set-0/parts_spd_manifest.generated.txt
+++ b/spd/lp5/set-0/parts_spd_manifest.generated.txt
@@ -37,3 +37,5 @@ MT62F1G32D2DS-031 WT:C,spd-3.hex
 MT62F2G32D4DS-031 WT:C,spd-6.hex
 H58GE6AK8BX104,spd-12.hex
 K3KLALA0EM-MGCU,spd-13.hex
+MT62F1G32D2DS-020 WT:D,spd-14.hex
+K3KL8L80EM-MGCV,spd-10.hex
diff --git a/spd/lp5/set-0/spd-14.hex b/spd/lp5/set-0/spd-14.hex
new file mode 100644
index 0000000000..fb1b5a43c4
--- /dev/null
+++ b/spd/lp5/set-0/spd-14.hex
@@ -0,0 +1,32 @@
+23 10 15 0E 16 22 91 08 00 00 00 00 0A 01 00 00
+00 00 08 00 00 00 00 00 AD 00 90 A8 90 C0 08 60
+04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 B6 00 C1 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 20 20 20 20 20 20 20
+20 20 20 20 20 20 20 20 20 20 20 20 20 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
diff --git a/spd/lp5/set-1/parts_spd_manifest.generated.txt b/spd/lp5/set-1/parts_spd_manifest.generated.txt
index 9ea9aca301..08d9e6ecee 100644
--- a/spd/lp5/set-1/parts_spd_manifest.generated.txt
+++ b/spd/lp5/set-1/parts_spd_manifest.generated.txt
@@ -37,3 +37,5 @@ MT62F1G32D2DS-031 WT:C,spd-3.hex
 MT62F2G32D4DS-031 WT:C,spd-6.hex
 H58GE6AK8BX104,spd-12.hex
 K3KLALA0EM-MGCU,spd-13.hex
++MT62F1G32D2DS-020 WT:D,spd-14.hex
++K3KL8L80EM-MGCV,spd-10.hex
diff --git a/spd/lp5/set-1/spd-14.hex b/spd/lp5/set-1/spd-14.hex
new file mode 100644
index 0000000000..37203cc057
--- /dev/null
+++ b/spd/lp5/set-1/spd-14.hex
@@ -0,0 +1,32 @@
+23 11 13 0E 86 21 91 18 00 40 00 00 0A 02 00 00
+00 00 02 00 00 00 00 00 2C 00 90 A8 90 C0 08 60
+04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 8A 00 F0 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 20 20 20 20 20 20 20
+20 20 20 20 20 20 20 20 20 20 20 20 20 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00

From 8449a15aedd13de7fbb85dfc51b0fde9d3649963 Mon Sep 17 00:00:00 2001
From: Hari L <haril@qualcomm.corp-partner.google.com>
Date: Tue, 28 Oct 2025 19:16:46 +0530
Subject: [PATCH 2424/3886] soc/qualcomm/x1p42100: Reduce USB OTG state enable
 timeout to 20ms

Reduce maximum timeout from 100ms to 20ms for OTG Enablement polling
for USB Type-C.

Avoid OTG enablement polling when in sink mode

BUG=b:455551151
TEST: Verify USB3.0 (SS) works for C0/C1 on Google/Bluey.

Background:
During USB Type-C port initialization, the OTG (On-The-Go) status must
be verified when the port operates in source mode to ensure proper VBUS
power delivery. The previous implementation polled the OTG status
register with a 100ms timeout on all ports regardless of their role.

Previous Implementation Issues:
1. Overly conservative timeout: The 100ms maximum wait significantly
   exceeded actual requirements, as OTG enablement consistently
   completes in approximately 14ms under normal conditions
2. Inefficient polling logic: OTG status was polled even when ports
   operated in sink mode, where OTG functionality is irrelevant since
   the port receives rather than provides power

Improvements:
1. Timeout reduction: Decreased maximum polling duration from 100ms to
   20ms, maintaining adequate margin (>40% headroom) while reducing boot
   time by up to 80ms per sink-mode port
2. Mode-aware polling: Added logic to detect port role and skip OTG
   status polling entirely for sink-mode ports, as demonstrated by the
   "Primary in SNK mode - skipping OTG status read" log entry

The changes maintain full USB3.0 SuperSpeed functionality while
improving initialization efficiency. The 20ms timeout remains
sufficiently conservative to accommodate normal timing variations.

Debug logs:
[DEBUG]  QMP PHY SS0 initialized and locked in 1671us,
	phy_status: 0x86868686
[INFO ]  Enabling Primary VBUS SuperSpeed
[INFO ]  Primary in SNK mode - skipping OTG status read
[INFO ]  Primary Type-C Status:
[INFO ]    Misc Status (0x2B0B): 0x1a
[INFO ]    Src Status (0x2B08): 0x00
[INFO ]    Mode Config (0x2B44): 0x00
[INFO ]    Interrupt En Cfg 1 (0x2B5E): 0xff
[INFO ]    State Machine Status (0x2B09): 0x02
[DEBUG]  USB HS PHY initialized for index 3
[DEBUG]  QMP-1x16 USB4 DP PHY SS1 init
[DEBUG]  QMP PHY SS1 initialized and locked in 1671us,
	phy_status: 0x86868686
[INFO ]  Enabling Secondary VBUS SuperSpeed
[INFO ]  Secondary in SRC mode - OTG Status: 0x02, State: 0x02
	(OTG Enabled) - Time: 14 ms
[INFO ]  Secondary Type-C Status:
[INFO ]    Misc Status (0x2B0B): 0x4b
[INFO ]    Src Status (0x2B08): 0x08
[INFO ]    Mode Config (0x2B44): 0x00
[INFO ]    Interrupt En Cfg 1 (0x2B5E): 0xff
[INFO ]    State Machine Status (0x2B09): 0xa6

confirmed that there are no otg polling for sink mode and
polling timeout is reduced to max of 20ms.

Change-Id: I7467248185c9d0526816ac62e1e1a1496440fddc
Signed-off-by: Hari L <haril@qualcomm.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89826
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
---
 .../qualcomm/x1p42100/include/soc/usb/usb.h   | 13 ++-
 src/soc/qualcomm/x1p42100/usb/usb.c           | 85 +++++++------------
 2 files changed, 38 insertions(+), 60 deletions(-)

diff --git a/src/soc/qualcomm/x1p42100/include/soc/usb/usb.h b/src/soc/qualcomm/x1p42100/include/soc/usb/usb.h
index f8aa9e9ccc..250ae55c70 100644
--- a/src/soc/qualcomm/x1p42100/include/soc/usb/usb.h
+++ b/src/soc/qualcomm/x1p42100/include/soc/usb/usb.h
@@ -106,24 +106,21 @@
 #define SCHG_DCDC_CMD_OTG 0x2740
 #define SCHG_DCDC_OTG_CFG 0x2753
 #define SCHG_DCDC_OTG_STATUS 0x270D
+#define SCHG_DCDC_ENG_SDCDC_CFG7 0x27C7
+#define SCHG_DCDC_ENG_SDCDC_GM_CLOOP_PD_OTG_BUCK_MASK 0x30
 
 /* OTG Status register bit definitions */
 #define OTG_STATE_MASK 0x07
-#define OTG_STATE_DISABLED 0x00
-#define OTG_STATE_ENABLING 0x01
 #define OTG_STATE_ENABLED 0x02
-#define OTG_STATE_DISABLING 0x03
-#define OTG_STATE_ERROR 0x04
-
-/* OTG Status check timeout and polling interval */
-#define OTG_STATUS_TIMEOUT_MS 100
-#define OTG_STATUS_POLL_INTERVAL_MS 2
+#define OTG_STATUS_TIMEOUT_MS 20
+#define OTG_STATUS_POLL_DELAY_MS 2
 
 /* Type-C register offsets */
 #define SCHG_TYPE_C_TYPE_C_MISC_STATUS 0x2B0B
 #define SCHG_TYPE_C_TYPE_C_SRC_STATUS 0x2B08
 #define SCHG_TYPE_C_TYPE_C_MODE_CFG 0x2B44
 #define TYPEC_VBUS_STATUS_MASK BIT(5)
+#define TYPEC_SNK_SRC_MODE BIT(6)
 #define CCOUT_INVERT_POLARITY 0x03
 
 /* USB Repeater SPMI Tune register offsets */
diff --git a/src/soc/qualcomm/x1p42100/usb/usb.c b/src/soc/qualcomm/x1p42100/usb/usb.c
index e97650773d..ec61ebd5be 100644
--- a/src/soc/qualcomm/x1p42100/usb/usb.c
+++ b/src/soc/qualcomm/x1p42100/usb/usb.c
@@ -8,6 +8,7 @@
 #include <soc/qcom_spmi.h>
 #include <delay.h>
 #include <gpio.h>
+#include <timer.h>
 
 struct usb_dwc3 {
 	u32 sbuscfg0;
@@ -667,53 +668,6 @@ void usb_update_refclk_for_core(u32 core_num, bool enable)
 	}
 }
 
-/*
- * wait_for_otg_enabled - Waits for OTG block to reach enabled state
- * @status_reg_addr: SPMI address of the OTG status register
- * @core_name: Name of the core for logging (e.g., "SMB1", "SMB2")
- * @return: true if OTG enabled successfully, false if timeout or error
- */
-static bool wait_for_otg_enabled(u32 status_reg_addr, const char *core_name)
-{
-	u32 timeout_ms = 0;
-	u8 otg_status;
-	u8 otg_state;
-
-	while (timeout_ms < OTG_STATUS_TIMEOUT_MS) {
-		otg_status = spmi_read8(status_reg_addr);
-		otg_state = otg_status & OTG_STATE_MASK;
-
-		printk(BIOS_DEBUG, "%s OTG Status: 0x%02x, State: 0x%02x\n",
-		       core_name, otg_status, otg_state);
-
-		switch (otg_state) {
-		case OTG_STATE_ENABLED:
-			printk(BIOS_INFO, "%s OTG block enabled successfully\n", core_name);
-			return true;
-		case OTG_STATE_ERROR:
-			printk(BIOS_ERR, "%s OTG block in ERROR state (0x%02x)\n",
-			       core_name, otg_status);
-			return false;
-		case OTG_STATE_DISABLED:
-		case OTG_STATE_ENABLING:
-		case OTG_STATE_DISABLING:
-			/* Continue polling */
-			break;
-		default:
-			printk(BIOS_WARNING, "%s OTG block in unknown state: 0x%02x\n",
-			       core_name, otg_state);
-			break;
-		}
-
-		mdelay(OTG_STATUS_POLL_INTERVAL_MS);
-		timeout_ms += OTG_STATUS_POLL_INTERVAL_MS;
-	}
-
-	printk(BIOS_ERR, "%s OTG enable timeout after %d ms, final state: 0x%02x\n",
-	       core_name, timeout_ms, otg_state);
-	return false;
-}
-
 /*
  * enable_vbus_ss - Enables VBUS SuperSpeed for specified USB core
  * @config: Controller configuration containing SMB slave address
@@ -721,15 +675,43 @@ static bool wait_for_otg_enabled(u32 status_reg_addr, const char *core_name)
 void enable_vbus_ss(const struct dwc3_controller_config *config)
 {
 	u8 slave = config->smb_slave_addr;
+	u8 misc_status, otg_status = 0, otg_state = 0;
+	struct stopwatch sw;
 
 	printk(BIOS_INFO, "Enabling %s VBUS SuperSpeed\n", config->name);
 
+	/* Configure SDCDC CFG7 register before enabling OTG */
+	spmi_write8(SPMI_ADDR(slave, SCHG_DCDC_ENG_SDCDC_CFG7),
+		    SCHG_DCDC_ENG_SDCDC_GM_CLOOP_PD_OTG_BUCK_MASK);
+
 	spmi_write8(SPMI_ADDR(slave, SCHG_DCDC_OTG_CFG), 0x20);
 	spmi_write8(SPMI_ADDR(slave, SCHG_DCDC_CMD_OTG), 0x1);
 
-	/* Wait for OTG block to reach enabled state */
-	if (!wait_for_otg_enabled(SPMI_ADDR(slave, SCHG_DCDC_OTG_STATUS), config->name))
-		printk(BIOS_ERR, "%s OTG enable failed\n", config->name);
+	/* Check Type-C mode */
+	misc_status = spmi_read8(SPMI_ADDR(slave, SCHG_TYPE_C_TYPE_C_MISC_STATUS));
+
+	/* Check SNK_SRC_MODE bit (bit 6): 0 = SNK, 1 = SRC */
+	if (misc_status & TYPEC_SNK_SRC_MODE) {
+		/* In SRC mode, poll OTG status until enabled */
+		stopwatch_init_msecs_expire(&sw, OTG_STATUS_TIMEOUT_MS);
+		while (!stopwatch_expired(&sw)) {
+			otg_status = spmi_read8(SPMI_ADDR(slave, SCHG_DCDC_OTG_STATUS));
+			otg_state = otg_status & OTG_STATE_MASK;
+
+			if (otg_state == OTG_STATE_ENABLED) {
+				printk(BIOS_INFO, "%s in SRC mode - OTG Status: 0x%02x, State: 0x%02x (OTG Enabled)\n",
+				       config->name, otg_status, otg_state);
+				return;
+			}
+			mdelay(OTG_STATUS_POLL_DELAY_MS);
+		}
+
+		/* Timeout - log final state */
+		printk(BIOS_INFO, "%s in SRC mode - OTG Status: 0x%02x, State: 0x%02x - Timeout after %d ms\n",
+		       config->name, otg_status, otg_state, OTG_STATUS_TIMEOUT_MS);
+	} else {
+		printk(BIOS_INFO, "%s in SNK mode - skipping OTG status read\n", config->name);
+	}
 }
 
 /*
@@ -746,8 +728,7 @@ void usb_typec_status_check(const struct dwc3_controller_config *config)
 	mode_cfg = spmi_read8(SPMI_ADDR(slave, SCHG_TYPE_C_TYPE_C_MODE_CFG));
 
 	printk(BIOS_INFO, "%s Type-C Status:\n", config->name);
-	printk(BIOS_INFO, "  Misc Status (0x2B0B): 0x%02x, VBUS Status (bit 5): %d\n",
-	       misc_status, (misc_status & TYPEC_VBUS_STATUS_MASK) ? 1 : 0);
+	printk(BIOS_INFO, "  Misc Status (0x2B0B): 0x%02x\n", misc_status);
 	printk(BIOS_INFO, "  Src Status (0x2B08): 0x%02x\n", src_status);
 	printk(BIOS_INFO, "  Mode Config (0x2B44): 0x%02x\n", mode_cfg);
 }

From 973d0faf65d7a756f6f1c61d6c7e03d2d2ad9a22 Mon Sep 17 00:00:00 2001
From: Maximilian Brune <maximilian.brune@9elements.com>
Date: Wed, 26 Mar 2025 17:23:15 +0100
Subject: [PATCH 2425/3886] util/amdfwtool: Move needs_ish and combo_new_rab to
 data_parse.c

Move these functions for better readability.

Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: Ib609d967e23b4ca1937e00ec72a669751ef09714
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87019
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-by: Ana Carolina Cabral <ana.cpmelo95@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 util/amdfwtool/amdfwtool.c  |  8 --------
 util/amdfwtool/amdfwtool.h  |  1 -
 util/amdfwtool/data_parse.c | 10 +++++++++-
 3 files changed, 9 insertions(+), 10 deletions(-)

diff --git a/util/amdfwtool/amdfwtool.c b/util/amdfwtool/amdfwtool.c
index 07736dd595..9e9ada79a7 100644
--- a/util/amdfwtool/amdfwtool.c
+++ b/util/amdfwtool/amdfwtool.c
@@ -1687,11 +1687,6 @@ static bool is_initial_alignment_required(enum platform soc_id)
 	}
 }
 
-static bool needs_new_combo_layout(enum platform soc_id)
-{
-	return needs_ish(soc_id);
-}
-
 int main(int argc, char **argv)
 {
 	int retval = 0;
@@ -1719,9 +1714,6 @@ int main(int argc, char **argv)
 
 	open_process_config(cb_config.config, &cb_config);
 
-	if (cb_config.use_combo && needs_new_combo_layout(cb_config.soc_id))
-		cb_config.combo_new_rab = true;
-
 	ctx.rom = malloc(ctx.rom_size);
 	if (!ctx.rom) {
 		fprintf(stderr, "Error: Failed to allocate memory\n");
diff --git a/util/amdfwtool/amdfwtool.h b/util/amdfwtool/amdfwtool.h
index 2327584813..dbc1c4adc0 100644
--- a/util/amdfwtool/amdfwtool.h
+++ b/util/amdfwtool/amdfwtool.h
@@ -500,7 +500,6 @@ void process_signed_psp_firmwares(const char *signed_rom,
 		uint64_t signed_start_addr,
 		enum platform soc_id);
 int find_bios_entry(amd_bios_type type);
-bool needs_ish(enum platform platform_type);
 
 #define EFS_FILE_SUFFIX ".efs"
 #define TMP_FILE_SUFFIX ".tmp"
diff --git a/util/amdfwtool/data_parse.c b/util/amdfwtool/data_parse.c
index 8e75d652fa..13922d63c9 100644
--- a/util/amdfwtool/data_parse.c
+++ b/util/amdfwtool/data_parse.c
@@ -792,7 +792,7 @@ static uint8_t process_one_line(char *oneline, regmatch_t *match, char *dir,
 	return 1;
 }
 
-bool needs_ish(enum platform platform_type)
+static bool needs_ish(enum platform platform_type)
 {
 	if (platform_type == PLATFORM_MENDOCINO || platform_type == PLATFORM_PHOENIX ||
 		platform_type == PLATFORM_GLINDA || platform_type == PLATFORM_FAEGAN)
@@ -801,6 +801,11 @@ bool needs_ish(enum platform platform_type)
 		return false;
 }
 
+static bool needs_new_combo_layout(enum platform soc_id)
+{
+	return needs_ish(soc_id);
+}
+
 static bool is_second_gen(enum platform platform_type)
 {
 	switch (platform_type) {
@@ -877,6 +882,9 @@ uint8_t process_config(FILE *config, amd_cb_config *cb_config)
 	if (cb_config->need_ish)
 		cb_config->recovery_ab = true;
 
+	if (cb_config->use_combo && needs_new_combo_layout(cb_config->soc_id))
+		cb_config->combo_new_rab = true;
+
 	if (cb_config->recovery_ab)
 		cb_config->multi_level = true;
 

From 8d7183a904e0d0a9fe271014db4cde642cf15e04 Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Sun, 19 Oct 2025 17:33:46 -0500
Subject: [PATCH 2426/3886] ec/google/chromeec: Add option to set keyboard
 backlight level at boot

Add the ability to set the keyboard backlight level at boot, controlled
by a setup option variable and restricted to devices which actually
have a backlit keyboard.

TEST=tested hooked up to a CFR option 'ec_kb_backlight' (added later in
the patch series) to set the keyboard backlight at boot, with
visibility controlled by backlight presence, on a range of Chromebooks
with and without keyboard backlight support.

Change-Id: I92eed62935d0333f548599860b7bbe22f6b9f2b4
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89828
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
---
 src/ec/google/chromeec/ec.c | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/src/ec/google/chromeec/ec.c b/src/ec/google/chromeec/ec.c
index fb8a014d0a..66cf54c4b0 100644
--- a/src/ec/google/chromeec/ec.c
+++ b/src/ec/google/chromeec/ec.c
@@ -3,6 +3,7 @@
 #include <stdbool.h>
 #include <stdint.h>
 #include <string.h>
+#include <acpi/acpi.h>
 #include <assert.h>
 #include <console/console.h>
 #include <delay.h>
@@ -10,6 +11,7 @@
 #include <device/path.h>
 #include <elog.h>
 #include <halt.h>
+#include <option.h>
 #include <reset.h>
 #include <rtc.h>
 #include <security/vboot/vboot_common.h>
@@ -1329,6 +1331,11 @@ void google_chromeec_init(void)
 	if (CONFIG(EC_GOOGLE_CHROMEEC_AUTO_FAN_CTRL)) {
 		ec_cmd_thermal_auto_fan_ctrl(PLAT_EC);
 	}
+
+	/* Set keyboard backlight */
+	int backlight_level = get_uint_option("ec_kb_backlight", -1);
+	if (backlight_level != -1 && !acpi_is_wakeup_s3() && google_chromeec_has_kbbacklight())
+		google_chromeec_kbbacklight(backlight_level);
 }
 
 int google_ec_running_ro(void)

From d4e8af407c21419864b5719511a8dbf8a75af3d0 Mon Sep 17 00:00:00 2001
From: Daniel Peng <Daniel_Peng@pegatron.corp-partner.google.com>
Date: Wed, 5 Nov 2025 20:12:55 +0800
Subject: [PATCH 2427/3886] spd/lp4x: Add CXMT CXDB5CBAM-MA-B memory

Generate initial SPD matched for CXMT CXDB5CBAM-MA-B.

BUG=b:451917928
TEST=1. make -C util/spd_tools
     2. util/spd_tools/bin/spd_gen spd/lp4x/memory_parts.json lp4x

Change-Id: Ib071aacd8aae0f22ee3d17544166b39d41f3f476
Signed-off-by: Daniel Peng <Daniel_Peng@pegatron.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89921
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 spd/lp4x/memory_parts.json                      | 12 ++++++++++++
 spd/lp4x/set-0/parts_spd_manifest.generated.txt |  1 +
 spd/lp4x/set-1/parts_spd_manifest.generated.txt |  1 +
 3 files changed, 14 insertions(+)

diff --git a/spd/lp4x/memory_parts.json b/spd/lp4x/memory_parts.json
index 094dcf3c96..70116be0f2 100644
--- a/spd/lp4x/memory_parts.json
+++ b/spd/lp4x/memory_parts.json
@@ -449,6 +449,18 @@
                 "ranksPerChannel": 1,
                 "speedMbps": 4267
             }
+        },
+        {
+            "name": "CXDB5CBAM-MA-B",
+            "attribs": {
+                "densityPerChannelGb": 16,
+                "banks": 8,
+                "channelsPerDie": 1,
+                "diesPerPackage": 2,
+                "bitWidthPerChannel": 16,
+                "ranksPerChannel": 1,
+                "speedMbps": 4267
+            }
         }
 
     ]
diff --git a/spd/lp4x/set-0/parts_spd_manifest.generated.txt b/spd/lp4x/set-0/parts_spd_manifest.generated.txt
index e60c68e5e7..6e2798c2b8 100644
--- a/spd/lp4x/set-0/parts_spd_manifest.generated.txt
+++ b/spd/lp4x/set-0/parts_spd_manifest.generated.txt
@@ -38,3 +38,4 @@ SDVB8D8A34XGCL3N3T,spd-1.hex
 NT6AP512T32BL-J1,spd-8.hex
 NT6AP1024F32BL-J1,spd-9.hex
 B3221XM3BDGVI,spd-10.hex
+CXDB5CBAM-MA-B,spd-10.hex
diff --git a/spd/lp4x/set-1/parts_spd_manifest.generated.txt b/spd/lp4x/set-1/parts_spd_manifest.generated.txt
index 0844ba9f58..d8b1606b6b 100644
--- a/spd/lp4x/set-1/parts_spd_manifest.generated.txt
+++ b/spd/lp4x/set-1/parts_spd_manifest.generated.txt
@@ -38,3 +38,4 @@ SDVB8D8A34XGCL3N3T,spd-5.hex
 NT6AP512T32BL-J1,spd-11.hex
 NT6AP1024F32BL-J1,spd-12.hex
 B3221XM3BDGVI,spd-13.hex
+CXDB5CBAM-MA-B,spd-13.hex

From 6b30e1f46bd6b197e2a34c487002f9c79cb2ba5f Mon Sep 17 00:00:00 2001
From: Daniel Peng <Daniel_Peng@pegatron.corp-partner.google.com>
Date: Wed, 5 Nov 2025 20:22:40 +0800
Subject: [PATCH 2428/3886] mb/google/dedede/var/pirika: Add support memory for
 CXMT CXDB5CBAM-MA-B

Add support for the new memory CXMT CXDB5CBAM-MA-B.

BUG=b:451917928
BRANCH=firmware-dedede-13606.B
TEST=Run command
     "go run ./util/spd_tools/src/part_id_gen/part_id_gen.go \
     JSL lp4x src/mainboard/google/dedede/variants/pirika/memory/ \
     src/mainboard/google/dedede/variants/pirika/memory/\
     mem_parts_used.txt"
     And confirm the mainboard boot normally with CXMT
     CXDB5CBAM-MA-B memory.

Change-Id: I8e1600ac191fd76b2226605e7a72497823a48105
Signed-off-by: Daniel Peng <Daniel_Peng@pegatron.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89922
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
---
 src/mainboard/google/dedede/variants/pirika/memory/Makefile.mk | 3 ++-
 .../google/dedede/variants/pirika/memory/dram_id.generated.txt | 3 ++-
 .../google/dedede/variants/pirika/memory/mem_parts_used.txt    | 1 +
 3 files changed, 5 insertions(+), 2 deletions(-)

diff --git a/src/mainboard/google/dedede/variants/pirika/memory/Makefile.mk b/src/mainboard/google/dedede/variants/pirika/memory/Makefile.mk
index 90505f8f5f..1e8ea64091 100644
--- a/src/mainboard/google/dedede/variants/pirika/memory/Makefile.mk
+++ b/src/mainboard/google/dedede/variants/pirika/memory/Makefile.mk
@@ -1,8 +1,9 @@
 # SPDX-License-Identifier: GPL-2.0-or-later
 # This is an auto-generated file. Do not edit!!
 # Generated by:
-# /tmp/go-build796126413/b001/exe/part_id_gen JSL lp4x src/mainboard/google/dedede/variants/pirika/memory/ src/mainboard/google/dedede/variants/pirika/memory/mem_parts_used.txt
+# /tmp/go-build2725596139/b001/exe/part_id_gen JSL lp4x src/mainboard/google/dedede/variants/pirika/memory/ src/mainboard/google/dedede/variants/pirika/memory/mem_parts_used.txt
 
 SPD_SOURCES =
 SPD_SOURCES += spd/lp4x/set-1/spd-1.hex      # ID = 0(0b0000)  Parts = H9HCNNNBKMMLXR-NEE, K4U6E3S4AA-MGCR, K4U6E3S4AB-MGCL, MT53E512M32D1NP-046 WT:B, H54G46CYRBX267
 SPD_SOURCES += spd/lp4x/set-1/spd-11.hex      # ID = 1(0b0001)  Parts = CXDB4CBAM-ML-A
+SPD_SOURCES += spd/lp4x/set-1/spd-13.hex      # ID = 2(0b0010)  Parts = CXDB5CBAM-MA-B
diff --git a/src/mainboard/google/dedede/variants/pirika/memory/dram_id.generated.txt b/src/mainboard/google/dedede/variants/pirika/memory/dram_id.generated.txt
index c62f08b15f..e2b72662ea 100644
--- a/src/mainboard/google/dedede/variants/pirika/memory/dram_id.generated.txt
+++ b/src/mainboard/google/dedede/variants/pirika/memory/dram_id.generated.txt
@@ -1,7 +1,7 @@
 # SPDX-License-Identifier: GPL-2.0-or-later
 # This is an auto-generated file. Do not edit!!
 # Generated by:
-# /tmp/go-build796126413/b001/exe/part_id_gen JSL lp4x src/mainboard/google/dedede/variants/pirika/memory/ src/mainboard/google/dedede/variants/pirika/memory/mem_parts_used.txt
+# /tmp/go-build2725596139/b001/exe/part_id_gen JSL lp4x src/mainboard/google/dedede/variants/pirika/memory/ src/mainboard/google/dedede/variants/pirika/memory/mem_parts_used.txt
 
 DRAM Part Name                 ID to assign
 H9HCNNNBKMMLXR-NEE             0 (0000)
@@ -10,3 +10,4 @@ K4U6E3S4AB-MGCL                0 (0000)
 CXDB4CBAM-ML-A                 1 (0001)
 MT53E512M32D1NP-046 WT:B       0 (0000)
 H54G46CYRBX267                 0 (0000)
+CXDB5CBAM-MA-B                 2 (0010)
diff --git a/src/mainboard/google/dedede/variants/pirika/memory/mem_parts_used.txt b/src/mainboard/google/dedede/variants/pirika/memory/mem_parts_used.txt
index c87f6c1ca2..a881f77e66 100644
--- a/src/mainboard/google/dedede/variants/pirika/memory/mem_parts_used.txt
+++ b/src/mainboard/google/dedede/variants/pirika/memory/mem_parts_used.txt
@@ -4,3 +4,4 @@ K4U6E3S4AB-MGCL
 CXDB4CBAM-ML-A
 MT53E512M32D1NP-046 WT:B
 H54G46CYRBX267
+CXDB5CBAM-MA-B

From 74dcb4c6795fa16d453fba415d7ff7d19d79bc23 Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Wed, 5 Nov 2025 08:52:00 +0000
Subject: [PATCH 2429/3886] mb/starlabs/common: Adjust the includes inline with
 coreboot

Adjust how the common headers are included, in a more "coreboot"
fashion.

Change-Id: Iaeb8e12272235a51c620656387838be8b0a0a098
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89917
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/starlabs/byte_adl/variants/mk_ii/ramstage.c     | 2 +-
 src/mainboard/starlabs/common/Makefile.mk                     | 2 ++
 .../starlabs/common/{pin_mux => include/common}/pin_mux.h     | 4 ++--
 src/mainboard/starlabs/common/pin_mux/Makefile.mk             | 2 --
 src/mainboard/starlabs/common/pin_mux/alderlake.c             | 2 +-
 src/mainboard/starlabs/common/pin_mux/meteorlake.c            | 2 +-
 src/mainboard/starlabs/common/pin_mux/tigerlake.c             | 2 +-
 src/mainboard/starlabs/starbook/variants/adl/ramstage.c       | 2 +-
 src/mainboard/starlabs/starbook/variants/adl_n/ramstage.c     | 2 +-
 src/mainboard/starlabs/starbook/variants/mtl/ramstage.c       | 2 +-
 src/mainboard/starlabs/starbook/variants/rpl/ramstage.c       | 2 +-
 src/mainboard/starlabs/starbook/variants/tgl/ramstage.c       | 2 +-
 src/mainboard/starlabs/starfighter/variants/rpl/ramstage.c    | 2 +-
 src/mainboard/starlabs/starlite_adl/variants/mk_v/ramstage.c  | 2 +-
 14 files changed, 15 insertions(+), 15 deletions(-)
 rename src/mainboard/starlabs/common/{pin_mux => include/common}/pin_mux.h (59%)

diff --git a/src/mainboard/starlabs/byte_adl/variants/mk_ii/ramstage.c b/src/mainboard/starlabs/byte_adl/variants/mk_ii/ramstage.c
index e70ba50498..3e9cfb13c4 100644
--- a/src/mainboard/starlabs/byte_adl/variants/mk_ii/ramstage.c
+++ b/src/mainboard/starlabs/byte_adl/variants/mk_ii/ramstage.c
@@ -1,7 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
 #include <soc/ramstage.h>
-#include "pin_mux.h"
+#include <common/pin_mux.h>
 
 void mainboard_silicon_init_params(FSP_S_CONFIG *supd)
 {
diff --git a/src/mainboard/starlabs/common/Makefile.mk b/src/mainboard/starlabs/common/Makefile.mk
index 3329eb0554..ba007bfa25 100644
--- a/src/mainboard/starlabs/common/Makefile.mk
+++ b/src/mainboard/starlabs/common/Makefile.mk
@@ -2,3 +2,5 @@
 
 subdirs-$(CONFIG_VENDOR_STARLABS) += smbios
 subdirs-$(CONFIG_VENDOR_STARLABS) += pin_mux
+
+CPPFLAGS_common += -I$(src)/mainboard/starlabs/common/include
diff --git a/src/mainboard/starlabs/common/pin_mux/pin_mux.h b/src/mainboard/starlabs/common/include/common/pin_mux.h
similarity index 59%
rename from src/mainboard/starlabs/common/pin_mux/pin_mux.h
rename to src/mainboard/starlabs/common/include/common/pin_mux.h
index 38c77f4032..7ecf11c80f 100644
--- a/src/mainboard/starlabs/common/pin_mux/pin_mux.h
+++ b/src/mainboard/starlabs/common/include/common/pin_mux.h
@@ -1,7 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
-#ifndef PIN_MUX
-#define PIN_MUX
+#ifndef _STARLABS_CMN_PIN_MUX_H_
+#define _STARLABS_CMN_PIN_MUX_H_
 
 void configure_pin_mux(FSP_S_CONFIG *supd);
 
diff --git a/src/mainboard/starlabs/common/pin_mux/Makefile.mk b/src/mainboard/starlabs/common/pin_mux/Makefile.mk
index 2249df0b3c..73374dac50 100644
--- a/src/mainboard/starlabs/common/pin_mux/Makefile.mk
+++ b/src/mainboard/starlabs/common/pin_mux/Makefile.mk
@@ -3,5 +3,3 @@
 ramstage-$(CONFIG_SOC_INTEL_TIGERLAKE) += tigerlake.c
 ramstage-$(CONFIG_SOC_INTEL_ALDERLAKE) += alderlake.c
 ramstage-$(CONFIG_SOC_INTEL_METEORLAKE) += meteorlake.c
-
-CPPFLAGS_common += -I$(src)/mainboard/starlabs/common/pin_mux
diff --git a/src/mainboard/starlabs/common/pin_mux/alderlake.c b/src/mainboard/starlabs/common/pin_mux/alderlake.c
index 1869b631e0..a0fac4d650 100644
--- a/src/mainboard/starlabs/common/pin_mux/alderlake.c
+++ b/src/mainboard/starlabs/common/pin_mux/alderlake.c
@@ -1,7 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
 #include <fsp/api.h>
-#include "pin_mux.h"
+#include <common/pin_mux.h>
 
 void configure_pin_mux(FSP_S_CONFIG *supd)
 {
diff --git a/src/mainboard/starlabs/common/pin_mux/meteorlake.c b/src/mainboard/starlabs/common/pin_mux/meteorlake.c
index 37d1f4aa1a..094f002fa4 100644
--- a/src/mainboard/starlabs/common/pin_mux/meteorlake.c
+++ b/src/mainboard/starlabs/common/pin_mux/meteorlake.c
@@ -1,7 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
 #include <fsp/api.h>
-#include "pin_mux.h"
+#include <common/pin_mux.h>
 
 void configure_pin_mux(FSP_S_CONFIG *supd)
 {
diff --git a/src/mainboard/starlabs/common/pin_mux/tigerlake.c b/src/mainboard/starlabs/common/pin_mux/tigerlake.c
index 34c1a05b90..1553ae55b4 100644
--- a/src/mainboard/starlabs/common/pin_mux/tigerlake.c
+++ b/src/mainboard/starlabs/common/pin_mux/tigerlake.c
@@ -1,7 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
 #include <fsp/api.h>
-#include "pin_mux.h"
+#include <common/pin_mux.h>
 
 void configure_pin_mux(FSP_S_CONFIG *supd)
 {
diff --git a/src/mainboard/starlabs/starbook/variants/adl/ramstage.c b/src/mainboard/starlabs/starbook/variants/adl/ramstage.c
index e6828e23ca..1dbad4fc98 100644
--- a/src/mainboard/starlabs/starbook/variants/adl/ramstage.c
+++ b/src/mainboard/starlabs/starbook/variants/adl/ramstage.c
@@ -2,7 +2,7 @@
 
 #include <option.h>
 #include <soc/ramstage.h>
-#include "pin_mux.h"
+#include <common/pin_mux.h>
 
 void mainboard_silicon_init_params(FSP_S_CONFIG *supd)
 {
diff --git a/src/mainboard/starlabs/starbook/variants/adl_n/ramstage.c b/src/mainboard/starlabs/starbook/variants/adl_n/ramstage.c
index e70ba50498..3e9cfb13c4 100644
--- a/src/mainboard/starlabs/starbook/variants/adl_n/ramstage.c
+++ b/src/mainboard/starlabs/starbook/variants/adl_n/ramstage.c
@@ -1,7 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
 #include <soc/ramstage.h>
-#include "pin_mux.h"
+#include <common/pin_mux.h>
 
 void mainboard_silicon_init_params(FSP_S_CONFIG *supd)
 {
diff --git a/src/mainboard/starlabs/starbook/variants/mtl/ramstage.c b/src/mainboard/starlabs/starbook/variants/mtl/ramstage.c
index 423716531a..bfac74f5ee 100644
--- a/src/mainboard/starlabs/starbook/variants/mtl/ramstage.c
+++ b/src/mainboard/starlabs/starbook/variants/mtl/ramstage.c
@@ -1,7 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
 #include <soc/ramstage.h>
-#include "pin_mux.h"
+#include <common/pin_mux.h>
 
 void mainboard_silicon_init_params(FSP_S_CONFIG *supd)
 {
diff --git a/src/mainboard/starlabs/starbook/variants/rpl/ramstage.c b/src/mainboard/starlabs/starbook/variants/rpl/ramstage.c
index e30afaa5ca..6ffe593f7f 100644
--- a/src/mainboard/starlabs/starbook/variants/rpl/ramstage.c
+++ b/src/mainboard/starlabs/starbook/variants/rpl/ramstage.c
@@ -2,7 +2,7 @@
 
 #include <option.h>
 #include <soc/ramstage.h>
-#include "pin_mux.h"
+#include <common/pin_mux.h>
 
 void mainboard_silicon_init_params(FSP_S_CONFIG *supd)
 {
diff --git a/src/mainboard/starlabs/starbook/variants/tgl/ramstage.c b/src/mainboard/starlabs/starbook/variants/tgl/ramstage.c
index e70ba50498..3e9cfb13c4 100644
--- a/src/mainboard/starlabs/starbook/variants/tgl/ramstage.c
+++ b/src/mainboard/starlabs/starbook/variants/tgl/ramstage.c
@@ -1,7 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
 #include <soc/ramstage.h>
-#include "pin_mux.h"
+#include <common/pin_mux.h>
 
 void mainboard_silicon_init_params(FSP_S_CONFIG *supd)
 {
diff --git a/src/mainboard/starlabs/starfighter/variants/rpl/ramstage.c b/src/mainboard/starlabs/starfighter/variants/rpl/ramstage.c
index e30afaa5ca..6ffe593f7f 100644
--- a/src/mainboard/starlabs/starfighter/variants/rpl/ramstage.c
+++ b/src/mainboard/starlabs/starfighter/variants/rpl/ramstage.c
@@ -2,7 +2,7 @@
 
 #include <option.h>
 #include <soc/ramstage.h>
-#include "pin_mux.h"
+#include <common/pin_mux.h>
 
 void mainboard_silicon_init_params(FSP_S_CONFIG *supd)
 {
diff --git a/src/mainboard/starlabs/starlite_adl/variants/mk_v/ramstage.c b/src/mainboard/starlabs/starlite_adl/variants/mk_v/ramstage.c
index 211384c1ef..370f5c8769 100644
--- a/src/mainboard/starlabs/starlite_adl/variants/mk_v/ramstage.c
+++ b/src/mainboard/starlabs/starlite_adl/variants/mk_v/ramstage.c
@@ -3,7 +3,7 @@
 #include <drivers/intel/gma/opregion.h>
 #include <soc/ramstage.h>
 #include <option.h>
-#include "pin_mux.h"
+#include <common/pin_mux.h>
 
 void mainboard_silicon_init_params(FSP_S_CONFIG *supd)
 {

From a58d99575e0791b665a190dba5f07ac2eed35b9f Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Wed, 29 Oct 2025 21:17:28 +0000
Subject: [PATCH 2430/3886] mb/starlabs/*: Move CFR object defs to common
 directory

Move all of the CFR object definitons to the common directory
to reduce duplicated code.

Change-Id: I02d486563a01738335a9f1a20b5fcad2b96d6498
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89809
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/starlabs/byte_adl/cfr.c         |  45 +------
 src/mainboard/starlabs/common/Makefile.mk     |   3 +-
 src/mainboard/starlabs/common/cfr/Makefile.mk |   4 +
 src/mainboard/starlabs/common/cfr/cfr.c       |  11 ++
 .../{starbook => common/include/common}/cfr.h | 120 +++++++++++-------
 src/mainboard/starlabs/lite/cfr.c             |  58 +--------
 src/mainboard/starlabs/starbook/cfr.c         |   2 +-
 src/mainboard/starlabs/starfighter/cfr.c      |  72 +----------
 src/mainboard/starlabs/starlite_adl/cfr.c     | 114 +----------------
 9 files changed, 99 insertions(+), 330 deletions(-)
 create mode 100644 src/mainboard/starlabs/common/cfr/Makefile.mk
 create mode 100644 src/mainboard/starlabs/common/cfr/cfr.c
 rename src/mainboard/starlabs/{starbook => common/include/common}/cfr.h (75%)

diff --git a/src/mainboard/starlabs/byte_adl/cfr.c b/src/mainboard/starlabs/byte_adl/cfr.c
index 530821bd34..30b44971e7 100644
--- a/src/mainboard/starlabs/byte_adl/cfr.c
+++ b/src/mainboard/starlabs/byte_adl/cfr.c
@@ -6,50 +6,7 @@
 #include <ec/starlabs/merlin/cfr.h>
 #include <intelblocks/cfr.h>
 #include <variants.h>
-
-static const struct sm_object gna = SM_DECLARE_BOOL({
-	.opt_name	= "gna",
-	.ui_name	= "Gaussian & Neural Accelerator",
-	.ui_helptext	= "Enable or Disable the Gaussian & Neural Accelerator",
-	.default_value	= false,
-});
-
-static const struct sm_object power_profile = SM_DECLARE_ENUM({
-	.opt_name	= "power_profile",
-	.ui_name	= "Power Profile",
-	.ui_helptext	= "Select whether to maximize performance, battery life or both.",
-	.default_value	= 1,
-	.values		= (const struct sm_enum_value[]) {
-				{ "Power Saver",	PP_POWER_SAVER	},
-				{ "Balanced",		PP_BALANCED	},
-				{ "Performance",	PP_PERFORMANCE	},
-				SM_ENUM_VALUE_END			},
-});
-
-static const struct sm_object vtd = SM_DECLARE_BOOL({
-	.opt_name	= "vtd",
-	.ui_name	= "VT-d",
-	.ui_helptext	= "Enable or disable Intel VT-d (virtualization)",
-	.default_value	= true,
-});
-
-static const struct sm_object bluetooth_rtd3 = SM_DECLARE_BOOL({
-	.opt_name	= "bluetooth_rtd3",
-	.ui_name	= "Bluetooth Runtime-D3",
-	.ui_helptext	= "Enable or disable Bluetooth power optimization.\n"
-			  "Recommended to disable when booting Windows.",
-	.default_value	= true,
-});
-
-static const struct sm_object s0ix_enable = SM_DECLARE_BOOL({
-	.opt_name	= "s0ix_enable",
-	.ui_name	= "Modern Standby (S0ix)",
-	.ui_helptext	= "Enabled: Use S0ix for device sleep.\n"
-			  "Disabled: Use ACPI S3 for device sleep.\n"
-			  "Requires Intel ME to be enabled.\n"
-			  "Recommended: Enabled when booting Windows, disabled otherwise.",
-	.default_value	= false,
-});
+#include <common/cfr.h>
 
 static struct sm_obj_form performance = {
 	.ui_name = "Performance",
diff --git a/src/mainboard/starlabs/common/Makefile.mk b/src/mainboard/starlabs/common/Makefile.mk
index ba007bfa25..966914673d 100644
--- a/src/mainboard/starlabs/common/Makefile.mk
+++ b/src/mainboard/starlabs/common/Makefile.mk
@@ -1,6 +1,7 @@
 # SPDX-License-Identifier: GPL-2.0-only
 
-subdirs-$(CONFIG_VENDOR_STARLABS) += smbios
+subdirs-$(CONFIG_VENDOR_STARLABS) += cfr
 subdirs-$(CONFIG_VENDOR_STARLABS) += pin_mux
+subdirs-$(CONFIG_VENDOR_STARLABS) += smbios
 
 CPPFLAGS_common += -I$(src)/mainboard/starlabs/common/include
diff --git a/src/mainboard/starlabs/common/cfr/Makefile.mk b/src/mainboard/starlabs/common/cfr/Makefile.mk
new file mode 100644
index 0000000000..00b8b806b3
--- /dev/null
+++ b/src/mainboard/starlabs/common/cfr/Makefile.mk
@@ -0,0 +1,4 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
+CPPFLAGS_common += -I$(src)/mainboard/starlabs/common/cfr
+ramstage-y += cfr.c
diff --git a/src/mainboard/starlabs/common/cfr/cfr.c b/src/mainboard/starlabs/common/cfr/cfr.c
new file mode 100644
index 0000000000..ebf5ffc7ce
--- /dev/null
+++ b/src/mainboard/starlabs/common/cfr/cfr.c
@@ -0,0 +1,11 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <drivers/option/cfr_frontend.h>
+#include <common/cfr.h>
+
+void __weak cfr_card_reader_update(const struct sm_object *obj,
+		struct sm_object *new_obj)
+{
+	(void)obj;
+	(void)new_obj;
+}
diff --git a/src/mainboard/starlabs/starbook/cfr.h b/src/mainboard/starlabs/common/include/common/cfr.h
similarity index 75%
rename from src/mainboard/starlabs/starbook/cfr.h
rename to src/mainboard/starlabs/common/include/common/cfr.h
index 7062fd436e..969efa2b19 100644
--- a/src/mainboard/starlabs/starbook/cfr.h
+++ b/src/mainboard/starlabs/common/include/common/cfr.h
@@ -1,17 +1,41 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
-
-#ifndef _STARBOOK_CFR_H_
-#define _STARBOOK_CFR_H_
+#ifndef _STARLABS_CMN_CFR_H_
+#define _STARLABS_CMN_CFR_H_
 
 #include <drivers/option/cfr_frontend.h>
 #include <variants.h>
 
+void cfr_card_reader_update(const struct sm_object *obj, struct sm_object *new_obj);
+
+static const struct sm_object accelerometer = SM_DECLARE_BOOL({
+	.opt_name	= "accelerometer",
+	.ui_name	= "Accelerometer",
+	.ui_helptext	= "Enable or disable the built-in accelerometer",
+	.default_value	= true,
+});
+
+static const struct sm_object bluetooth_rtd3 = SM_DECLARE_BOOL({
+	.opt_name	= "bluetooth_rtd3",
+	.ui_name	= "Bluetooth Runtime-D3",
+	.ui_helptext	= "Enable or disable Bluetooth power optimization.\n"
+			  "Recommended to disable when booting Windows.",
+	.default_value	= true,
+});
+
 static const struct sm_object card_reader = SM_DECLARE_BOOL({
 	.opt_name	= "card_reader",
 	.ui_name	= "Card Reader",
 	.ui_helptext	= "Enable or disable the built-in card reader",
 	.default_value	= true,
+}, WITH_CALLBACK(cfr_card_reader_update));
+
+static const struct sm_object display_native_res = SM_DECLARE_BOOL({
+	.opt_name	= "display_native_res",
+	.ui_name	= "Display: Use Native Resolution",
+	.ui_helptext	= "Enabled: use the native panel resolution at boot.\n"
+			  "Disabled: use a fixed/scaled video mode at boot.",
+	.default_value	= false,
 });
 
 static const struct sm_object fingerprint_reader = SM_DECLARE_BOOL({
@@ -35,16 +59,19 @@ static const struct sm_object hyper_threading = SM_DECLARE_BOOL({
 	.default_value	= true,
 });
 
-static const struct sm_object power_profile = SM_DECLARE_ENUM({
-	.opt_name	= "power_profile",
-	.ui_name	= "Power Profile",
-	.ui_helptext	= "Select whether to maximize performance, battery life or both.",
+static const struct sm_object memory_speed = SM_DECLARE_ENUM({
+	.opt_name	= "memory_speed",
+	.ui_name	= "Memory Speed",
+	.ui_helptext	= "Configure the speed that the memory will run at. "
+			  "Higher speeds produce more heat and consume more power "
+			  "but provide higher performance.",
 	.default_value	= 1,
 	.values		= (const struct sm_enum_value[]) {
-				{ "Power Saver",	PP_POWER_SAVER	},
-				{ "Balanced",		PP_BALANCED	},
-				{ "Performance",	PP_PERFORMANCE	},
-				SM_ENUM_VALUE_END			},
+		{ "5500MT/s", 0 },
+		{ "6400MT/s", 1 },
+		{ "7500MT/s", 2 },
+		SM_ENUM_VALUE_END,
+	},
 });
 
 static const struct sm_object microphone = SM_DECLARE_BOOL({
@@ -62,6 +89,28 @@ static const struct sm_object pci_hot_plug = SM_DECLARE_BOOL({
 	.default_value	= false,
 });
 
+static const struct sm_object power_profile = SM_DECLARE_ENUM({
+	.opt_name	= "power_profile",
+	.ui_name	= "Power Profile",
+	.ui_helptext	= "Select whether to maximize performance, battery life or both.",
+	.default_value	= 1,
+	.values		= (const struct sm_enum_value[]) {
+			{ "Power Saver",	PP_POWER_SAVER	},
+			{ "Balanced",		PP_BALANCED	},
+			{ "Performance",	PP_PERFORMANCE	},
+			SM_ENUM_VALUE_END			},
+});
+
+static const struct sm_object s0ix_enable = SM_DECLARE_BOOL({
+	.opt_name	= "s0ix_enable",
+	.ui_name	= "Modern Standby (S0ix)",
+	.ui_helptext	= "Enabled: Use S0ix for device sleep.\n"
+			  "Disabled: Use ACPI S3 for device sleep.\n"
+			  "Requires Intel ME to be enabled.\n"
+			  "Recommended: Enabled when booting Windows, disabled otherwise.",
+	.default_value	= false,
+});
+
 static const struct sm_object thunderbolt = SM_DECLARE_BOOL({
 	.opt_name	= "thunderbolt",
 	.ui_name	= "Thunderbolt",
@@ -69,6 +118,13 @@ static const struct sm_object thunderbolt = SM_DECLARE_BOOL({
 	.default_value	= true,
 });
 
+static const struct sm_object touchscreen = SM_DECLARE_BOOL({
+	.opt_name	= "touchscreen",
+	.ui_name	= "Touchscreen",
+	.ui_helptext	= "Enable or disable the built-in touch-screen",
+	.default_value	= true,
+});
+
 static const struct sm_object vpu = SM_DECLARE_BOOL({
 	.opt_name	= "vpu",
 	.ui_name	= "VPU",
@@ -76,6 +132,13 @@ static const struct sm_object vpu = SM_DECLARE_BOOL({
 	.default_value	= false,
 });
 
+static const struct sm_object vtd = SM_DECLARE_BOOL({
+	.opt_name	= "vtd",
+	.ui_name	= "VT-d",
+	.ui_helptext	= "Enable or disable Intel VT-d (virtualization)",
+	.default_value	= true,
+});
+
 static const struct sm_object webcam = SM_DECLARE_BOOL({
 	.opt_name	= "webcam",
 	.ui_name	= "Webcam",
@@ -90,37 +153,4 @@ static const struct sm_object wireless = SM_DECLARE_BOOL({
 	.default_value	= true,
 });
 
-static const struct sm_object vtd = SM_DECLARE_BOOL({
-	.opt_name	= "vtd",
-	.ui_name	= "VT-d",
-	.ui_helptext	= "Enable or disable Intel VT-d (virtualization)",
-	.default_value	= true,
-});
-
-static const struct sm_object bluetooth_rtd3 = SM_DECLARE_BOOL({
-	.opt_name	= "bluetooth_rtd3",
-	.ui_name	= "Bluetooth Runtime-D3",
-	.ui_helptext	= "Enable or disable Bluetooth power optimization.\n"
-			  "Recommended to disable when booting Windows.",
-	.default_value	= true,
-});
-
-static const struct sm_object display_native_res = SM_DECLARE_BOOL({
-	.opt_name	= "display_native_res",
-	.ui_name	= "Display: Use Native Resolution",
-	.ui_helptext	= "Enabled: use the native panel resolution at boot.\n"
-			  "Disabled: use a fixed/scaled video mode at boot.",
-	.default_value	= false,
-});
-
-static const struct sm_object s0ix_enable = SM_DECLARE_BOOL({
-	.opt_name	= "s0ix_enable",
-	.ui_name	= "Modern Standby (S0ix)",
-	.ui_helptext	= "Enabled: Use S0ix for device sleep.\n"
-			  "Disabled: Use ACPI S3 for device sleep.\n"
-			  "Requires Intel ME to be enabled.\n"
-			  "Recommended: Enabled when booting Windows, disabled otherwise.",
-	.default_value	= false,
-});
-
-#endif /* _STARBOOK_CFR_H_ */
+#endif /* _STARLABS_CMN_CFR_H_ */
diff --git a/src/mainboard/starlabs/lite/cfr.c b/src/mainboard/starlabs/lite/cfr.c
index 4049531081..3f17350189 100644
--- a/src/mainboard/starlabs/lite/cfr.c
+++ b/src/mainboard/starlabs/lite/cfr.c
@@ -6,63 +6,7 @@
 #include <ec/starlabs/merlin/cfr.h>
 #include <intelblocks/cfr.h>
 #include <variants.h>
-
-static const struct sm_object card_reader = SM_DECLARE_BOOL({
-	.opt_name	= "card_reader",
-	.ui_name	= "Card Reader",
-	.ui_helptext	= "Enable or disable the built-in card reader",
-	.default_value	= true,
-});
-
-static const struct sm_object power_profile = SM_DECLARE_ENUM({
-	.opt_name	= "power_profile",
-	.ui_name	= "Power Profile",
-	.ui_helptext	= "Select whether to maximize performance, battery life or both.",
-	.default_value	= 1,
-	.values		= (const struct sm_enum_value[]) {
-				{ "Power Saver",	PP_POWER_SAVER	},
-				{ "Balanced",		PP_BALANCED	},
-				{ "Performance",	PP_PERFORMANCE	},
-				SM_ENUM_VALUE_END			},
-});
-
-static const struct sm_object microphone = SM_DECLARE_BOOL({
-	.opt_name	= "microphone",
-	.ui_name	= "Microphone",
-	.ui_helptext	= "Enable or disable the built-in microphone",
-	.default_value	= true,
-});
-
-static const struct sm_object webcam = SM_DECLARE_BOOL({
-	.opt_name	= "webcam",
-	.ui_name	= "Webcam",
-	.ui_helptext	= "Enable or disable the built-in webcam",
-	.default_value	= true,
-});
-
-static const struct sm_object wireless = SM_DECLARE_BOOL({
-	.opt_name	= "wireless",
-	.ui_name	= "Wireless",
-	.ui_helptext	= "Enable or disable the built-in wireless card",
-	.default_value	= true,
-});
-
-static const struct sm_object vtd = SM_DECLARE_BOOL({
-	.opt_name	= "vtd",
-	.ui_name	= "VT-d",
-	.ui_helptext	= "Enable or disable Intel VT-d (virtualization)",
-	.default_value	= true,
-});
-
-static const struct sm_object s0ix_enable = SM_DECLARE_BOOL({
-	.opt_name	= "s0ix_enable",
-	.ui_name	= "Modern Standby (S0ix)",
-	.ui_helptext	= "Enabled: Use S0ix for device sleep.\n"
-			  "Disabled: Use ACPI S3 for device sleep.\n"
-			  "Requires Intel ME to be enabled.\n"
-			  "Recommended: Enabled when booting Windows, disabled otherwise.",
-	.default_value	= false,
-});
+#include <common/cfr.h>
 
 static struct sm_obj_form performance = {
 	.ui_name = "Performance",
diff --git a/src/mainboard/starlabs/starbook/cfr.c b/src/mainboard/starlabs/starbook/cfr.c
index fb3605cfdd..cf7f22170f 100644
--- a/src/mainboard/starlabs/starbook/cfr.c
+++ b/src/mainboard/starlabs/starbook/cfr.c
@@ -5,7 +5,7 @@
 #include <drivers/option/cfr_frontend.h>
 #include <ec/starlabs/merlin/cfr.h>
 #include <intelblocks/cfr.h>
-#include "cfr.h"
+#include <common/cfr.h>
 
 static struct sm_obj_form performance = {
 	.ui_name = "Performance",
diff --git a/src/mainboard/starlabs/starfighter/cfr.c b/src/mainboard/starlabs/starfighter/cfr.c
index d54ff0de07..89f8811bb0 100644
--- a/src/mainboard/starlabs/starfighter/cfr.c
+++ b/src/mainboard/starlabs/starfighter/cfr.c
@@ -6,77 +6,7 @@
 #include <ec/starlabs/merlin/cfr.h>
 #include <intelblocks/cfr.h>
 #include <variants.h>
-
-#if CONFIG(SOC_INTEL_TIGERLAKE) || CONFIG(SOC_INTEL_ALDERLAKE) || CONFIG(SOC_INTEL_RAPTORLAKE)
-static const struct sm_object gna = SM_DECLARE_BOOL({
-	.opt_name	= "gna",
-	.ui_name	= "Gaussian & Neural Accelerator",
-	.ui_helptext	= "Enable or Disable the Gaussian & Neural Accelerator",
-	.default_value	= false,
-});
-#endif
-
-static const struct sm_object hyper_threading = SM_DECLARE_BOOL({
-	.opt_name	= "hyper_threading",
-	.ui_name	= "Hyper-Threading",
-	.ui_helptext	= "Enable or disable Hyper-Threading",
-	.default_value	= true,
-});
-
-
-static const struct sm_object power_profile = SM_DECLARE_ENUM({
-	.opt_name	= "power_profile",
-	.ui_name	= "Power Profile",
-	.ui_helptext	= "Select whether to maximize performance, battery life or both.",
-	.default_value	= 1,
-	.values		= (const struct sm_enum_value[]) {
-				{ "Power Saver",	PP_POWER_SAVER	},
-				{ "Balanced",		PP_BALANCED	},
-				{ "Performance",	PP_PERFORMANCE	},
-				SM_ENUM_VALUE_END			},
-});
-
-#if CONFIG(DRIVERS_INTEL_USB4_RETIMER)
-static const struct sm_object thunderbolt = SM_DECLARE_BOOL({
-	.opt_name	= "thunderbolt",
-	.ui_name	= "Thunderbolt",
-	.ui_helptext	= "Enable or disable Thunderbolt support",
-	.default_value	= true,
-});
-#endif
-
-static const struct sm_object vtd = SM_DECLARE_BOOL({
-	.opt_name	= "vtd",
-	.ui_name	= "VT-d",
-	.ui_helptext	= "Enable or disable Intel VT-d (virtualization)",
-	.default_value	= true,
-});
-
-static const struct sm_object bluetooth_rtd3 = SM_DECLARE_BOOL({
-	.opt_name	= "bluetooth_rtd3",
-	.ui_name	= "Bluetooth Runtime-D3",
-	.ui_helptext	= "Enable or disable Bluetooth power optimization.\n"
-			  "Recommended to disable when booting Windows.",
-	.default_value	= true,
-});
-
-static const struct sm_object display_native_res = SM_DECLARE_BOOL({
-	.opt_name	= "display_native_res",
-	.ui_name	= "Display: Use Native Resolution",
-	.ui_helptext	= "Enabled: use the native panel resolution at boot.\n"
-			  "Disabled: use a fixed/scaled video mode at boot.",
-	.default_value	= false,
-});
-
-static const struct sm_object s0ix_enable = SM_DECLARE_BOOL({
-	.opt_name	= "s0ix_enable",
-	.ui_name	= "Modern Standby (S0ix)",
-	.ui_helptext	= "Enabled: Use S0ix for device sleep.\n"
-			  "Disabled: Use ACPI S3 for device sleep.\n"
-			  "Requires Intel ME to be enabled.\n"
-			  "Recommended: Enabled when booting Windows, disabled otherwise.",
-	.default_value	= false,
-});
+#include <common/cfr.h>
 
 static struct sm_obj_form performance = {
 	.ui_name = "Performance",
diff --git a/src/mainboard/starlabs/starlite_adl/cfr.c b/src/mainboard/starlabs/starlite_adl/cfr.c
index a7ebe498aa..defa0ec1b1 100644
--- a/src/mainboard/starlabs/starlite_adl/cfr.c
+++ b/src/mainboard/starlabs/starlite_adl/cfr.c
@@ -9,124 +9,16 @@
 #include <device/i2c_simple.h>
 #include <static.h>
 #include <variants.h>
+#include <common/cfr.h>
 
-static const struct sm_object accelerometer = SM_DECLARE_BOOL({
-	.opt_name	= "accelerometer",
-	.ui_name	= "Accelerometer",
-	.ui_helptext	= "Enable or disable the built-in accelerometer",
-	.default_value	= true,
-});
-
-static void update_card_reader(const struct sm_object *obj, struct sm_object *new)
+void cfr_card_reader_update(const struct sm_object *obj, struct sm_object *new_obj)
 {
 	struct device *mxc_accel = DEV_PTR(mxc6655);
 
 	if (!i2c_dev_detect(i2c_busdev(mxc_accel), mxc_accel->path.i2c.device))
-		new->sm_bool.flags = CFR_OPTFLAG_SUPPRESS;
+		new_obj->sm_bool.flags = CFR_OPTFLAG_SUPPRESS;
 }
 
-static const struct sm_object card_reader = SM_DECLARE_BOOL({
-	.opt_name	= "card_reader",
-	.ui_name	= "Card Reader",
-	.ui_helptext	= "Enable or disable the built-in card reader",
-	.default_value	= true,
-}, WITH_CALLBACK(update_card_reader));
-
-#if CONFIG(SOC_INTEL_TIGERLAKE) || CONFIG(SOC_INTEL_ALDERLAKE) || CONFIG(SOC_INTEL_RAPTORLAKE)
-static const struct sm_object gna = SM_DECLARE_BOOL({
-	.opt_name	= "gna",
-	.ui_name	= "Gaussian & Neural Accelerator",
-	.ui_helptext	= "Enable or Disable the Gaussian & Neural Accelerator",
-	.default_value	= false,
-});
-#endif
-
-static const struct sm_object memory_speed = SM_DECLARE_ENUM({
-	.opt_name	= "memory_speed",
-	.ui_name	= "Memory Speed",
-	.ui_helptext	= "Configure the speed that the memory will run at. Higher speeds produce more heat and consume more power but provide higher performance.",
-	.default_value	= 1,
-	.values		= (const struct sm_enum_value[]) {
-		{	"5500MT/s",	0		},
-		{	"6400MT/s",	1		},
-		{	"7500MT/s",	2		},
-		SM_ENUM_VALUE_END,
-	}
-});
-
-static const struct sm_object power_profile = SM_DECLARE_ENUM({
-	.opt_name	= "power_profile",
-	.ui_name	= "Power Profile",
-	.ui_helptext	= "Select whether to maximize performance, battery life or both.",
-	.default_value	= 1,
-	.values		= (const struct sm_enum_value[]) {
-				{ "Power Saver",	PP_POWER_SAVER	},
-				{ "Balanced",		PP_BALANCED	},
-				{ "Performance",	PP_PERFORMANCE	},
-				SM_ENUM_VALUE_END			},
-});
-
-static const struct sm_object microphone = SM_DECLARE_BOOL({
-	.opt_name	= "microphone",
-	.ui_name	= "Microphone",
-	.ui_helptext	= "Enable or disable the built-in microphone",
-	.default_value	= true,
-});
-
-static const struct sm_object touchscreen = SM_DECLARE_BOOL({
-	.opt_name	= "touchscreen",
-	.ui_name	= "Touchscreen",
-	.ui_helptext	= "Enable or disable the built-in touch-screen",
-	.default_value	= true,
-});
-
-static const struct sm_object webcam = SM_DECLARE_BOOL({
-	.opt_name	= "webcam",
-	.ui_name	= "Webcam",
-	.ui_helptext	= "Enable or disable the built-in webcam",
-	.default_value	= true,
-});
-
-static const struct sm_object wireless = SM_DECLARE_BOOL({
-	.opt_name	= "wireless",
-	.ui_name	= "Wireless",
-	.ui_helptext	= "Enable or disable the built-in wireless card",
-	.default_value	= true,
-});
-
-static const struct sm_object vtd = SM_DECLARE_BOOL({
-	.opt_name	= "vtd",
-	.ui_name	= "VT-d",
-	.ui_helptext	= "Enable or disable Intel VT-d (virtualization)",
-	.default_value	= true,
-});
-
-static const struct sm_object bluetooth_rtd3 = SM_DECLARE_BOOL({
-	.opt_name	= "bluetooth_rtd3",
-	.ui_name	= "Bluetooth Runtime-D3",
-	.ui_helptext	= "Enable or disable Bluetooth power optimization.\n"
-			  "Recommended to disable when booting Windows.",
-	.default_value	= true,
-});
-
-static const struct sm_object display_native_res = SM_DECLARE_BOOL({
-	.opt_name	= "display_native_res",
-	.ui_name	= "Display: Use Native Resolution",
-	.ui_helptext	= "Enabled: use the native panel resolution at boot.\n"
-			  "Disabled: use a fixed/scaled video mode at boot.",
-	.default_value	= false,
-});
-
-static const struct sm_object s0ix_enable = SM_DECLARE_BOOL({
-	.opt_name	= "s0ix_enable",
-	.ui_name	= "Modern Standby (S0ix)",
-	.ui_helptext	= "Enabled: Use S0ix for device sleep.\n"
-			  "Disabled: Use ACPI S3 for device sleep.\n"
-			  "Requires Intel ME to be enabled.\n"
-			  "Recommended: Enabled when booting Windows, disabled otherwise.",
-	.default_value	= false,
-});
-
 static struct sm_obj_form performance = {
 	.ui_name = "Performance",
 	.obj_list = (const struct sm_object *[]) {

From abf630c96bd644180625b8599ca125a91cf7448f Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Wed, 29 Oct 2025 21:26:46 +0000
Subject: [PATCH 2431/3886] mb/starlabs/byte_adl: Add wireless CFR object

Add the wireless CFR object to allow users to disable or
enable the built-in wireless.

Change-Id: I8f48bf30429d64980d15d33f9e26164e806c520c
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89810
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/starlabs/byte_adl/cfr.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/src/mainboard/starlabs/byte_adl/cfr.c b/src/mainboard/starlabs/byte_adl/cfr.c
index 30b44971e7..e3b37adf1d 100644
--- a/src/mainboard/starlabs/byte_adl/cfr.c
+++ b/src/mainboard/starlabs/byte_adl/cfr.c
@@ -41,6 +41,7 @@ static struct sm_obj_form devices = {
 	.ui_name = "Devices",
 	.obj_list = (const struct sm_object *[]) {
 		&gna,
+		&wireless,
 		NULL
 	},
 };

From 082ad480d925cc96d0e1218f2a99c0fb6fb23db0 Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Tue, 28 Oct 2025 20:03:01 +0000
Subject: [PATCH 2432/3886] mb/starlabs/*: Separate WiFi and Bluetooth controls

Split the "wireless" option into "WiFi" and "Bluetooth" in CFR
to allow more granular control.

Test=Disable WiFi and Bluetooth in turn and make sure the devices
are disabled independently.

Change-Id: I3f617486c78a89a60a1e8c7c8ab7d157dc20bf2e
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89797
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/starlabs/byte_adl/cfr.c             |  3 ++-
 .../starlabs/byte_adl/variants/mk_ii/devtree.c    | 11 +++++++----
 .../starlabs/common/include/common/cfr.h          | 15 +++++++++++----
 src/mainboard/starlabs/lite/cfr.c                 |  3 ++-
 src/mainboard/starlabs/lite/devtree.c             |  9 +++++----
 src/mainboard/starlabs/starbook/cfr.c             |  3 ++-
 .../starlabs/starbook/variants/adl/devtree.c      |  2 +-
 .../starlabs/starbook/variants/adl/romstage.c     |  4 ++--
 .../starlabs/starbook/variants/adl_n/devtree.c    |  2 +-
 .../starlabs/starbook/variants/adl_n/romstage.c   |  4 ++--
 .../starlabs/starbook/variants/cml/devtree.c      | 12 +++++++-----
 .../starlabs/starbook/variants/kbl/devtree.c      | 12 +++++++-----
 .../starlabs/starbook/variants/mtl/devtree.c      |  2 +-
 .../starlabs/starbook/variants/mtl/romstage.c     |  4 ++--
 .../starlabs/starbook/variants/rpl/devtree.c      |  2 +-
 .../starlabs/starbook/variants/rpl/romstage.c     |  4 ++--
 .../starlabs/starbook/variants/tgl/devtree.c      | 12 +++++++-----
 .../starlabs/starfighter/variants/rpl/devtree.c   |  2 +-
 .../starlabs/starfighter/variants/rpl/romstage.c  |  2 +-
 src/mainboard/starlabs/starlite_adl/cfr.c         |  3 ++-
 .../starlabs/starlite_adl/variants/mk_v/devtree.c | 11 +++++++----
 21 files changed, 73 insertions(+), 49 deletions(-)

diff --git a/src/mainboard/starlabs/byte_adl/cfr.c b/src/mainboard/starlabs/byte_adl/cfr.c
index e3b37adf1d..5a29170778 100644
--- a/src/mainboard/starlabs/byte_adl/cfr.c
+++ b/src/mainboard/starlabs/byte_adl/cfr.c
@@ -40,8 +40,9 @@ static struct sm_obj_form power = {
 static struct sm_obj_form devices = {
 	.ui_name = "Devices",
 	.obj_list = (const struct sm_object *[]) {
+		&bluetooth,
 		&gna,
-		&wireless,
+		&wifi,
 		NULL
 	},
 };
diff --git a/src/mainboard/starlabs/byte_adl/variants/mk_ii/devtree.c b/src/mainboard/starlabs/byte_adl/variants/mk_ii/devtree.c
index eb1710dc4a..2b273952ab 100644
--- a/src/mainboard/starlabs/byte_adl/variants/mk_ii/devtree.c
+++ b/src/mainboard/starlabs/byte_adl/variants/mk_ii/devtree.c
@@ -21,7 +21,7 @@ void devtree_update(void)
 	struct soc_power_limits_config *soc_conf_8core =
 		&cfg->power_limits_config[ADL_N_041_15W_CORE];
 
-	struct device *nic_dev = pcidev_on_root(0x14, 3);
+	struct device *wifi_dev = pcidev_on_root(0x14, 3);
 	struct device *gna_dev = pcidev_on_root(0x08, 0);
 
 	uint8_t performance_scale = 100;
@@ -55,11 +55,14 @@ void devtree_update(void)
 	soc_conf_8core->tdp_pl1_override = (soc_conf_8core->tdp_pl1_override * performance_scale) / 100;
 	soc_conf_8core->tdp_pl2_override = (soc_conf_8core->tdp_pl2_override * performance_scale) / 100;
 
+
+	/* Enable/Disable WiFi based on CMOS settings */
+	if (get_uint_option("wifi", 1) == 0)
+		wifi_dev->enabled = 0;
+
 	/* Enable/Disable Bluetooth based on CMOS settings */
-	if (get_uint_option("wireless", 1) == 0) {
+	if (get_uint_option("bluetooth", 1) == 0)
 		cfg->usb2_ports[9].enable = 0;
-		nic_dev->enabled = 0;
-	}
 
 	/* Enable/Disable GNA based on CMOS settings */
 	if (get_uint_option("gna", 0) == 0)
diff --git a/src/mainboard/starlabs/common/include/common/cfr.h b/src/mainboard/starlabs/common/include/common/cfr.h
index 969efa2b19..d6bb406a24 100644
--- a/src/mainboard/starlabs/common/include/common/cfr.h
+++ b/src/mainboard/starlabs/common/include/common/cfr.h
@@ -15,6 +15,13 @@ static const struct sm_object accelerometer = SM_DECLARE_BOOL({
 	.default_value	= true,
 });
 
+static const struct sm_object bluetooth = SM_DECLARE_BOOL({
+	.opt_name	= "bluetooth",
+	.ui_name	= "Bluetooth",
+	.ui_helptext	= "Enable or disable the built-in Bluetooth",
+	.default_value	= true,
+});
+
 static const struct sm_object bluetooth_rtd3 = SM_DECLARE_BOOL({
 	.opt_name	= "bluetooth_rtd3",
 	.ui_name	= "Bluetooth Runtime-D3",
@@ -146,10 +153,10 @@ static const struct sm_object webcam = SM_DECLARE_BOOL({
 	.default_value	= true,
 });
 
-static const struct sm_object wireless = SM_DECLARE_BOOL({
-	.opt_name	= "wireless",
-	.ui_name	= "Wireless",
-	.ui_helptext	= "Enable or disable the built-in wireless card",
+static const struct sm_object wifi = SM_DECLARE_BOOL({
+	.opt_name	= "wifi",
+	.ui_name	= "WiFi",
+	.ui_helptext	= "Enable or disable the built-in WiFi",
 	.default_value	= true,
 });
 
diff --git a/src/mainboard/starlabs/lite/cfr.c b/src/mainboard/starlabs/lite/cfr.c
index 3f17350189..f9e42146cf 100644
--- a/src/mainboard/starlabs/lite/cfr.c
+++ b/src/mainboard/starlabs/lite/cfr.c
@@ -45,10 +45,11 @@ static struct sm_obj_form keyboard = {
 static struct sm_obj_form devices = {
 	.ui_name = "Devices",
 	.obj_list = (const struct sm_object *[]) {
+		&bluetooth,
 		&card_reader,
 		&microphone,
 		&webcam,
-		&wireless,
+		&wifi,
 		NULL
 	},
 };
diff --git a/src/mainboard/starlabs/lite/devtree.c b/src/mainboard/starlabs/lite/devtree.c
index f25628b4e5..bd43b2154c 100644
--- a/src/mainboard/starlabs/lite/devtree.c
+++ b/src/mainboard/starlabs/lite/devtree.c
@@ -23,7 +23,7 @@ void devtree_update(void)
 	struct soc_power_limits_config *soc_conf =
 		&cfg->power_limits_config;
 
-	struct device *nic_dev = pcidev_on_root(0x0c, 0);
+	struct device *wifi_dev = pcidev_on_root(0x0c, 0);
 
 	uint8_t performance_scale = 100;
 
@@ -52,9 +52,10 @@ void devtree_update(void)
 	soc_conf->tdp_pl1_override = (soc_conf->tdp_pl1_override * performance_scale) / 100;
 	soc_conf->tdp_pl2_override = (soc_conf->tdp_pl2_override * performance_scale) / 100;
 
-	/* Enable/Disable Wireless based on CMOS settings */
-	if (get_uint_option("wireless", 1) == 0)
-		nic_dev->enabled = 0;
+
+	/* Enable/Disable WiFi based on CMOS settings */
+	if (get_uint_option("wifi", 1) == 0)
+		wifi_dev->enabled = 0;
 
 	/* Enable/Disable Webcam based on CMOS settings */
 	cfg->usb2_port[CONFIG_WEBCAM_USB_PORT].enable = get_uint_option("webcam", 1);
diff --git a/src/mainboard/starlabs/starbook/cfr.c b/src/mainboard/starlabs/starbook/cfr.c
index cf7f22170f..e1f3f6dd56 100644
--- a/src/mainboard/starlabs/starbook/cfr.c
+++ b/src/mainboard/starlabs/starbook/cfr.c
@@ -55,6 +55,7 @@ static struct sm_obj_form keyboard = {
 static struct sm_obj_form devices = {
 	.ui_name = "Devices",
 	.obj_list = (const struct sm_object *[]) {
+		&bluetooth,
 		&card_reader,
 		#if CONFIG(BOARD_USES_FIXED_MODE_VBT)
 		&display_native_res,
@@ -76,7 +77,7 @@ static struct sm_obj_form devices = {
 		&vpu,
 		#endif
 		&webcam,
-		&wireless,
+		&wifi,
 		NULL
 	},
 };
diff --git a/src/mainboard/starlabs/starbook/variants/adl/devtree.c b/src/mainboard/starlabs/starbook/variants/adl/devtree.c
index 5bbf8a3b40..01557f875f 100644
--- a/src/mainboard/starlabs/starbook/variants/adl/devtree.c
+++ b/src/mainboard/starlabs/starbook/variants/adl/devtree.c
@@ -57,7 +57,7 @@ void devtree_update(void)
 	soc_conf_12core->tdp_pl2_override = (soc_conf_12core->tdp_pl2_override * performance_scale) / 100;
 
 	/* Enable/Disable Bluetooth based on CMOS settings */
-	if (get_uint_option("wireless", 1) == 0)
+	if (get_uint_option("bluetooth", 1) == 0)
 		cfg->usb2_ports[9].enable = 0;
 
 	/* Enable/Disable Webcam based on CMOS settings */
diff --git a/src/mainboard/starlabs/starbook/variants/adl/romstage.c b/src/mainboard/starlabs/starbook/variants/adl/romstage.c
index 98683da2df..e57cc32a3d 100644
--- a/src/mainboard/starlabs/starbook/variants/adl/romstage.c
+++ b/src/mainboard/starlabs/starbook/variants/adl/romstage.c
@@ -32,8 +32,8 @@ void mainboard_memory_init_params(FSPM_UPD *mupd)
 	const uint8_t vtd = get_uint_option("vtd", 1);
 	mupd->FspmConfig.VtdDisable = !vtd;
 
-	/* Enable/Disable Wireless (RP05) based on CMOS settings */
-	if (get_uint_option("wireless", 1) == 0)
+	/* Enable/Disable WiFi (RP05) based on CMOS settings */
+	if (get_uint_option("wifi", 1) == 0)
 		mupd->FspmConfig.PcieRpEnableMask &= ~(1 << 4);
 
 	mupd->FspmConfig.DmiMaxLinkSpeed = 4;
diff --git a/src/mainboard/starlabs/starbook/variants/adl_n/devtree.c b/src/mainboard/starlabs/starbook/variants/adl_n/devtree.c
index 8ab1c92834..afea557b0b 100644
--- a/src/mainboard/starlabs/starbook/variants/adl_n/devtree.c
+++ b/src/mainboard/starlabs/starbook/variants/adl_n/devtree.c
@@ -49,7 +49,7 @@ void devtree_update(void)
 	soc_conf_4core->tdp_pl2_override = (soc_conf_4core->tdp_pl2_override * performance_scale) / 100;
 
 	/* Enable/Disable Bluetooth based on CMOS settings */
-	if (get_uint_option("wireless", 1) == 0)
+	if (get_uint_option("bluetooth", 1) == 0)
 		cfg->usb2_ports[9].enable = 0;
 
 	/* Enable/Disable Webcam based on CMOS settings */
diff --git a/src/mainboard/starlabs/starbook/variants/adl_n/romstage.c b/src/mainboard/starlabs/starbook/variants/adl_n/romstage.c
index 21000d1d33..7141d59301 100644
--- a/src/mainboard/starlabs/starbook/variants/adl_n/romstage.c
+++ b/src/mainboard/starlabs/starbook/variants/adl_n/romstage.c
@@ -29,7 +29,7 @@ void mainboard_memory_init_params(FSPM_UPD *mupd)
 	const uint8_t vtd = get_uint_option("vtd", 1);
 	mupd->FspmConfig.VtdDisable = !vtd;
 
-	/* Enable/Disable Wireless (RP07) based on CMOS settings */
-	if (get_uint_option("wireless", 1) == 0)
+	/* Enable/Disable WiFi (RP07) based on CMOS settings */
+	if (get_uint_option("wifi", 1) == 0)
 		mupd->FspmConfig.PcieRpEnableMask &= ~(1 << 6);
 };
diff --git a/src/mainboard/starlabs/starbook/variants/cml/devtree.c b/src/mainboard/starlabs/starbook/variants/cml/devtree.c
index f9d201078c..f5975dd9e0 100644
--- a/src/mainboard/starlabs/starbook/variants/cml/devtree.c
+++ b/src/mainboard/starlabs/starbook/variants/cml/devtree.c
@@ -18,7 +18,7 @@ void devtree_update(void)
 
 	struct soc_power_limits_config *soc_conf = &cfg->power_limits_config;
 
-	struct device *nic_dev = pcidev_on_root(0x14, 3);
+	struct device *wifi_dev = pcidev_on_root(0x14, 3);
 
 	uint8_t performance_scale = 100;
 
@@ -47,11 +47,13 @@ void devtree_update(void)
 	soc_conf->tdp_pl1_override = (soc_conf->tdp_pl1_override * performance_scale) / 100;
 	soc_conf->tdp_pl2_override = (soc_conf->tdp_pl2_override * performance_scale) / 100;
 
-	/* Enable/Disable Wireless based on CMOS settings */
-	if (get_uint_option("wireless", 1) == 0) {
-		nic_dev->enabled = 0;
+	/* Enable/Disable WiFi based on CMOS settings */
+	if (get_uint_option("wifi", 1) == 0)
+		wifi_dev->enabled = 0;
+
+	/* Enable/Disable Bluetooth based on CMOS settings */
+	if (get_uint_option("bluetooth", 1) == 0)
 		cfg->usb2_ports[9].enable = 0;
-	}
 
 	/* Enable/Disable Webcam based on CMOS settings */
 	cfg->usb2_ports[CONFIG_CCD_PORT].enable = get_uint_option("webcam", 1);
diff --git a/src/mainboard/starlabs/starbook/variants/kbl/devtree.c b/src/mainboard/starlabs/starbook/variants/kbl/devtree.c
index 3cda4ce455..16244ad047 100644
--- a/src/mainboard/starlabs/starbook/variants/kbl/devtree.c
+++ b/src/mainboard/starlabs/starbook/variants/kbl/devtree.c
@@ -18,7 +18,7 @@ void devtree_update(void)
 
 	struct soc_power_limits_config *soc_conf = &cfg->power_limits_config;
 
-	struct device *nic_dev = pcidev_on_root(0x1c, 5);
+	struct device *wifi_dev = pcidev_on_root(0x1c, 5);
 
 	uint8_t performance_scale = 100;
 
@@ -47,11 +47,13 @@ void devtree_update(void)
 	soc_conf->tdp_pl1_override = (soc_conf->tdp_pl1_override * performance_scale) / 100;
 	soc_conf->tdp_pl2_override = (soc_conf->tdp_pl2_override * performance_scale) / 100;
 
-	/* Enable/Disable Wireless based on CMOS settings */
-	if (get_uint_option("wireless", 1) == 0) {
-		nic_dev->enabled = 0;
+	/* Enable/Disable WiFi based on CMOS settings */
+	if (get_uint_option("wifi", 1) == 0)
+		wifi_dev->enabled = 0;
+
+	/* Enable/Disable Bluetooth based on CMOS settings */
+	if (get_uint_option("bluetooth", 1) == 0)
 		cfg->usb2_ports[9].enable = 0;
-	}
 
 	/* Enable/Disable Webcam based on CMOS settings */
 	cfg->usb2_ports[CONFIG_CCD_PORT].enable = get_uint_option("webcam", 1);
diff --git a/src/mainboard/starlabs/starbook/variants/mtl/devtree.c b/src/mainboard/starlabs/starbook/variants/mtl/devtree.c
index 69406c7e78..82c137b557 100644
--- a/src/mainboard/starlabs/starbook/variants/mtl/devtree.c
+++ b/src/mainboard/starlabs/starbook/variants/mtl/devtree.c
@@ -50,7 +50,7 @@ void devtree_update(void)
 	soc_conf_20core->tdp_pl2_override = (soc_conf_20core->tdp_pl2_override * performance_scale) / 100;
 
 	/* Enable/Disable Bluetooth based on CMOS settings */
-	if (get_uint_option("wireless", 1) == 0)
+	if (get_uint_option("bluetooth", 1) == 0)
 		cfg->usb2_ports[9].enable = 0;
 
 	/* Enable/Disable Webcam based on CMOS settings */
diff --git a/src/mainboard/starlabs/starbook/variants/mtl/romstage.c b/src/mainboard/starlabs/starbook/variants/mtl/romstage.c
index 6f553a2885..ceff083d00 100644
--- a/src/mainboard/starlabs/starbook/variants/mtl/romstage.c
+++ b/src/mainboard/starlabs/starbook/variants/mtl/romstage.c
@@ -32,8 +32,8 @@ void mainboard_memory_init_params(FSPM_UPD *mupd)
 	const uint8_t vtd = get_uint_option("vtd", 1);
 	mupd->FspmConfig.VtdDisable = !vtd;
 
-	/* Enable/Disable Wireless (RP09) based on CMOS settings */
-	if (get_uint_option("wireless", 1) == 0)
+	/* Enable/Disable WiFi (RP09) based on CMOS settings */
+	if (get_uint_option("wifi", 1) == 0)
 		mupd->FspmConfig.PcieRpEnableMask &= ~(1 << 8);
 
 	mupd->FspmConfig.PchHdaSubSystemIds = 0x70381e50;
diff --git a/src/mainboard/starlabs/starbook/variants/rpl/devtree.c b/src/mainboard/starlabs/starbook/variants/rpl/devtree.c
index 76031d0f1f..f9680fe3b0 100644
--- a/src/mainboard/starlabs/starbook/variants/rpl/devtree.c
+++ b/src/mainboard/starlabs/starbook/variants/rpl/devtree.c
@@ -59,7 +59,7 @@ void devtree_update(void)
 	soc_conf_12core->tdp_pl2_override = (soc_conf_12core->tdp_pl2_override * performance_scale) / 100;
 
 	/* Enable/Disable Bluetooth based on CMOS settings */
-	if (get_uint_option("wireless", 1) == 0)
+	if (get_uint_option("bluetooth", 1) == 0)
 		cfg->usb2_ports[9].enable = 0;
 
 	/* Enable/Disable Webcam based on CMOS settings */
diff --git a/src/mainboard/starlabs/starbook/variants/rpl/romstage.c b/src/mainboard/starlabs/starbook/variants/rpl/romstage.c
index 5038a526b7..c1d646f860 100644
--- a/src/mainboard/starlabs/starbook/variants/rpl/romstage.c
+++ b/src/mainboard/starlabs/starbook/variants/rpl/romstage.c
@@ -32,8 +32,8 @@ void mainboard_memory_init_params(FSPM_UPD *mupd)
 	const uint8_t vtd = get_uint_option("vtd", 1);
 	mupd->FspmConfig.VtdDisable = !vtd;
 
-	/* Enable/Disable Wireless (RP05) based on CMOS settings */
-	if (get_uint_option("wireless", 1) == 0)
+	/* Enable/Disable WiFi (RP05) based on CMOS settings */
+	if (get_uint_option("wifi", 1) == 0)
 		mupd->FspmConfig.PcieRpEnableMask &= ~(1 << 4);
 
 	/* Enable/Disable Thunderbolt based on CMOS settings */
diff --git a/src/mainboard/starlabs/starbook/variants/tgl/devtree.c b/src/mainboard/starlabs/starbook/variants/tgl/devtree.c
index 3988cf2cde..f507025487 100644
--- a/src/mainboard/starlabs/starbook/variants/tgl/devtree.c
+++ b/src/mainboard/starlabs/starbook/variants/tgl/devtree.c
@@ -22,7 +22,7 @@ void devtree_update(void)
 	struct soc_power_limits_config *soc_conf_4core =
 		&cfg->power_limits_config[POWER_LIMITS_U_4_CORE];
 
-	struct device *nic_dev = pcidev_on_root(0x14, 3);
+	struct device *wifi_dev = pcidev_on_root(0x14, 3);
 	struct device *tbt_pci_dev = pcidev_on_root(0x07, 0);
 	struct device *tbt_dma_dev = pcidev_on_root(0x0d, 2);
 	struct device *gna_dev = pcidev_on_root(0x08, 0);
@@ -59,11 +59,13 @@ void devtree_update(void)
 	soc_conf_4core->tdp_pl1_override = (soc_conf_4core->tdp_pl1_override * performance_scale) / 100;
 	soc_conf_4core->tdp_pl2_override = (soc_conf_4core->tdp_pl2_override * performance_scale) / 100;
 
-	/* Enable/Disable Wireless based on CMOS settings */
-	if (get_uint_option("wireless", 1) == 0) {
-		nic_dev->enabled = 0;
+	/* Enable/Disable WiFi based on CMOS settings */
+	if (get_uint_option("wifi", 1) == 0)
+		wifi_dev->enabled = 0;
+
+	/* Enable/Disable Bluetooth based on CMOS settings */
+	if (get_uint_option("bluetooth", 1) == 0)
 		cfg->usb2_ports[9].enable = 0;
-	}
 
 	/* Enable/Disable Webcam based on CMOS settings */
 	cfg->usb2_ports[CONFIG_CCD_PORT].enable = get_uint_option("webcam", 1);
diff --git a/src/mainboard/starlabs/starfighter/variants/rpl/devtree.c b/src/mainboard/starlabs/starfighter/variants/rpl/devtree.c
index ae35ed5e4b..5fb56c3f46 100644
--- a/src/mainboard/starlabs/starfighter/variants/rpl/devtree.c
+++ b/src/mainboard/starlabs/starfighter/variants/rpl/devtree.c
@@ -60,7 +60,7 @@ void devtree_update(void)
 	soc_conf_14core->tdp_pl2_override = (soc_conf_14core->tdp_pl2_override * performance_scale) / 100;
 
 	/* Enable/Disable Bluetooth based on CMOS settings */
-	if (get_uint_option("wireless", 1) == 0)
+	if (get_uint_option("bluetooth", 1) == 0)
 		cfg->usb2_ports[9].enable = 0;
 
 	/* Enable/Disable Webcam based on CMOS settings */
diff --git a/src/mainboard/starlabs/starfighter/variants/rpl/romstage.c b/src/mainboard/starlabs/starfighter/variants/rpl/romstage.c
index 6ec63a16d7..34e61728c4 100644
--- a/src/mainboard/starlabs/starfighter/variants/rpl/romstage.c
+++ b/src/mainboard/starlabs/starfighter/variants/rpl/romstage.c
@@ -127,7 +127,7 @@ void mainboard_memory_init_params(FSPM_UPD *mupd)
 	mupd->FspmConfig.VtdDisable = !vtd;
 
 	/* Enable/Disable Wireless (RP05) based on CMOS settings */
-	if (get_uint_option("wireless", 1) == 0)
+	if (get_uint_option("wifi", 1) == 0)
 		mupd->FspmConfig.PcieRpEnableMask &= ~(1 << 4);
 
 	/* Enable/Disable Thunderbolt based on CMOS settings */
diff --git a/src/mainboard/starlabs/starlite_adl/cfr.c b/src/mainboard/starlabs/starlite_adl/cfr.c
index defa0ec1b1..62dc785b6c 100644
--- a/src/mainboard/starlabs/starlite_adl/cfr.c
+++ b/src/mainboard/starlabs/starlite_adl/cfr.c
@@ -57,6 +57,7 @@ static struct sm_obj_form devices = {
 	.ui_name = "Devices",
 	.obj_list = (const struct sm_object *[]) {
 		&accelerometer,
+		&bluetooth,
 		&card_reader,
 		&display_native_res,
 		#if CONFIG(SOC_INTEL_TIGERLAKE) || CONFIG(SOC_INTEL_ALDERLAKE) || CONFIG(SOC_INTEL_RAPTORLAKE)
@@ -68,7 +69,7 @@ static struct sm_obj_form devices = {
 		&microphone,
 		&touchscreen,
 		&webcam,
-		&wireless,
+		&wifi,
 		NULL
 	},
 };
diff --git a/src/mainboard/starlabs/starlite_adl/variants/mk_v/devtree.c b/src/mainboard/starlabs/starlite_adl/variants/mk_v/devtree.c
index 8252d61756..31de19db97 100644
--- a/src/mainboard/starlabs/starlite_adl/variants/mk_v/devtree.c
+++ b/src/mainboard/starlabs/starlite_adl/variants/mk_v/devtree.c
@@ -19,7 +19,7 @@ void devtree_update(void)
 	struct soc_power_limits_config *soc_conf_4core =
 		&cfg->power_limits_config[ADL_N_041_6W_CORE];
 
-	struct device *nic_dev = pcidev_on_root(0x14, 3);
+	struct device *wifi_dev = pcidev_on_root(0x14, 3);
 	struct device *touchscreen_dev = pcidev_on_root(0x15, 2);
 	struct device *accelerometer_dev = pcidev_on_root(0x15, 0);
 	struct device *gna_dev = pcidev_on_root(0x08, 0);
@@ -51,11 +51,14 @@ void devtree_update(void)
 	soc_conf_4core->tdp_pl1_override = (soc_conf_4core->tdp_pl1_override * performance_scale) / 100;
 	soc_conf_4core->tdp_pl2_override = (soc_conf_4core->tdp_pl2_override * performance_scale) / 100;
 
+
+	/* Enable/Disable WiFi based on CMOS settings */
+	if (get_uint_option("wifi", 1) == 0)
+		wifi_dev->enabled = 0;
+
 	/* Enable/Disable Bluetooth based on CMOS settings */
-	if (get_uint_option("wireless", 1) == 0) {
+	if (get_uint_option("bluetooth", 1) == 0)
 		cfg->usb2_ports[9].enable = 0;
-		nic_dev->enabled = 0;
-	}
 
 	/* Enable/Disable Webcam/Camera based on CMOS settings */
 	if (get_uint_option("webcam", 1) == 0)

From 98e0ff1e4b94dbbd07049bbc50da2f4ce4b3603b Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Mon, 27 Oct 2025 20:07:32 +0000
Subject: [PATCH 2433/3886] mb/starlabs/*: Move DMIC disabling code to common
 dir

Move the code that disables the DMIC based on the option table
to the common directory, as it's pretty much the same for all
boards.

Drop the check for the codec ID, as it's pointless.

Change-Id: I55dd8f5f65908f5c4605001893003209f85cb139
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89777
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
---
 src/mainboard/starlabs/common/Kconfig         |  2 ++
 src/mainboard/starlabs/common/Makefile.mk     |  1 +
 src/mainboard/starlabs/common/hda/Kconfig     |  7 +++++
 src/mainboard/starlabs/common/hda/Makefile.mk |  3 +++
 src/mainboard/starlabs/common/hda/dmic.c      | 21 +++++++++++++++
 src/mainboard/starlabs/starbook/Kconfig       |  1 +
 src/mainboard/starlabs/starbook/Makefile.mk   |  1 -
 src/mainboard/starlabs/starbook/hda_verb.c    | 27 -------------------
 src/mainboard/starlabs/starfighter/Kconfig    |  1 +
 .../starlabs/starfighter/Makefile.mk          |  1 -
 src/mainboard/starlabs/starfighter/hda_verb.c | 26 ------------------
 src/mainboard/starlabs/starlite_adl/Kconfig   |  1 +
 .../starlabs/starlite_adl/Makefile.mk         |  1 -
 .../starlabs/starlite_adl/hda_verb.c          | 26 ------------------
 14 files changed, 37 insertions(+), 82 deletions(-)
 create mode 100644 src/mainboard/starlabs/common/hda/Kconfig
 create mode 100644 src/mainboard/starlabs/common/hda/Makefile.mk
 create mode 100644 src/mainboard/starlabs/common/hda/dmic.c
 delete mode 100644 src/mainboard/starlabs/starbook/hda_verb.c
 delete mode 100644 src/mainboard/starlabs/starfighter/hda_verb.c
 delete mode 100644 src/mainboard/starlabs/starlite_adl/hda_verb.c

diff --git a/src/mainboard/starlabs/common/Kconfig b/src/mainboard/starlabs/common/Kconfig
index 4670672cb7..07239c8904 100644
--- a/src/mainboard/starlabs/common/Kconfig
+++ b/src/mainboard/starlabs/common/Kconfig
@@ -8,6 +8,8 @@ config MB_COMMON_DIR
 	string
 	default "starlabs/common"
 
+source "src/mainboard/starlabs/common/hda/Kconfig"
+
 endmenu
 
 endif
diff --git a/src/mainboard/starlabs/common/Makefile.mk b/src/mainboard/starlabs/common/Makefile.mk
index 966914673d..07ac8e9640 100644
--- a/src/mainboard/starlabs/common/Makefile.mk
+++ b/src/mainboard/starlabs/common/Makefile.mk
@@ -1,6 +1,7 @@
 # SPDX-License-Identifier: GPL-2.0-only
 
 subdirs-$(CONFIG_VENDOR_STARLABS) += cfr
+subdirs-$(CONFIG_VENDOR_STARLABS) += hda
 subdirs-$(CONFIG_VENDOR_STARLABS) += pin_mux
 subdirs-$(CONFIG_VENDOR_STARLABS) += smbios
 
diff --git a/src/mainboard/starlabs/common/hda/Kconfig b/src/mainboard/starlabs/common/hda/Kconfig
new file mode 100644
index 0000000000..984616f94e
--- /dev/null
+++ b/src/mainboard/starlabs/common/hda/Kconfig
@@ -0,0 +1,7 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
+config HAVE_HDA_DMIC
+	bool
+	help
+	  Select if the board has a DMIC and to allow disabling it via
+	  the option API.
diff --git a/src/mainboard/starlabs/common/hda/Makefile.mk b/src/mainboard/starlabs/common/hda/Makefile.mk
new file mode 100644
index 0000000000..c6f53539f7
--- /dev/null
+++ b/src/mainboard/starlabs/common/hda/Makefile.mk
@@ -0,0 +1,3 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
+ramstage-$(CONFIG_HAVE_HDA_DMIC) += dmic.c
diff --git a/src/mainboard/starlabs/common/hda/dmic.c b/src/mainboard/starlabs/common/hda/dmic.c
new file mode 100644
index 0000000000..cf1b243866
--- /dev/null
+++ b/src/mainboard/starlabs/common/hda/dmic.c
@@ -0,0 +1,21 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <device/azalia_codec/realtek.h>
+#include <device/azalia_device.h>
+#include <option.h>
+#include <types.h>
+
+static const uint32_t override_verb[] = {
+	AZALIA_PIN_CFG(0, ALC269_DMIC12, AZALIA_PIN_CFG_NC(0)),
+};
+
+static void disable_microphone(uint8_t *base)
+{
+	azalia_program_verb_table(base, override_verb, ARRAY_SIZE(override_verb));
+}
+
+void mainboard_azalia_program_runtime_verbs(uint8_t *base, uint32_t viddid)
+{
+	if (get_uint_option("microphone", 1) == 0)
+		disable_microphone(base);
+}
diff --git a/src/mainboard/starlabs/starbook/Kconfig b/src/mainboard/starlabs/starbook/Kconfig
index 0853c1873d..244bcfb195 100644
--- a/src/mainboard/starlabs/starbook/Kconfig
+++ b/src/mainboard/starlabs/starbook/Kconfig
@@ -12,6 +12,7 @@ config BOARD_STARLABS_STARBOOK_SERIES
 	select HAVE_ACPI_RESUME
 	select HAVE_ACPI_TABLES
 	select HAVE_CMOS_DEFAULT
+	select HAVE_HDA_DMIC
 	select HAVE_OPTION_TABLE
 	select INTEL_GMA_HAVE_VBT
 	select INTEL_LPSS_UART_FOR_CONSOLE
diff --git a/src/mainboard/starlabs/starbook/Makefile.mk b/src/mainboard/starlabs/starbook/Makefile.mk
index 1a8996f1b2..a51e1d5128 100644
--- a/src/mainboard/starlabs/starbook/Makefile.mk
+++ b/src/mainboard/starlabs/starbook/Makefile.mk
@@ -11,6 +11,5 @@ verstage-$(CONFIG_VBOOT) += vboot.c
 romstage-$(CONFIG_VBOOT) += vboot.c
 
 ramstage-$(CONFIG_DRIVERS_OPTION_CFR) += cfr.c
-ramstage-y += hda_verb.c
 ramstage-y += mainboard.c
 ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += variants/$(VARIANT_DIR)/gma-mainboard.ads
diff --git a/src/mainboard/starlabs/starbook/hda_verb.c b/src/mainboard/starlabs/starbook/hda_verb.c
deleted file mode 100644
index 699ff34102..0000000000
--- a/src/mainboard/starlabs/starbook/hda_verb.c
+++ /dev/null
@@ -1,27 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <console/console.h>
-#include <device/azalia_device.h>
-#include <option.h>
-#include <types.h>
-
-#define AZALIA_CODEC_ALC256 0x10ec0256
-#define AZALIA_CODEC_ALC269 0x10ec0269
-
-static const u32 override_verb[] = {
-	AZALIA_PIN_CFG(0, 0x12, AZALIA_PIN_CFG_NC(0)),
-};
-
-static void disable_microphone(u8 *base)
-{
-	azalia_program_verb_table(base, override_verb, ARRAY_SIZE(override_verb));
-}
-
-void mainboard_azalia_program_runtime_verbs(u8 *base, u32 viddid)
-{
-	if (viddid == AZALIA_CODEC_ALC256 || viddid == AZALIA_CODEC_ALC269) {
-		printk(BIOS_DEBUG, "CMOS: viddid = %08x\n", viddid);
-		if (get_uint_option("microphone", 1) == 0)
-			disable_microphone(base);
-	}
-}
diff --git a/src/mainboard/starlabs/starfighter/Kconfig b/src/mainboard/starlabs/starfighter/Kconfig
index d29427f373..28838aacd4 100644
--- a/src/mainboard/starlabs/starfighter/Kconfig
+++ b/src/mainboard/starlabs/starfighter/Kconfig
@@ -21,6 +21,7 @@ config BOARD_STARLABS_STARFIGHTER_SERIES
 	select HAVE_ACPI_RESUME
 	select HAVE_ACPI_TABLES
 	select HAVE_CMOS_DEFAULT
+	select HAVE_HDA_DMIC
 	select HAVE_OPTION_TABLE
 	select HAVE_SPD_IN_CBFS
 	select INTEL_GMA_HAVE_VBT
diff --git a/src/mainboard/starlabs/starfighter/Makefile.mk b/src/mainboard/starlabs/starfighter/Makefile.mk
index 59e8f76e8f..535c3237a6 100644
--- a/src/mainboard/starlabs/starfighter/Makefile.mk
+++ b/src/mainboard/starlabs/starfighter/Makefile.mk
@@ -7,6 +7,5 @@ subdirs-y += variants/$(VARIANT_DIR)
 bootblock-y += bootblock.c
 
 ramstage-$(CONFIG_DRIVERS_OPTION_CFR) += cfr.c
-ramstage-y += hda_verb.c
 ramstage-y += mainboard.c
 ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += variants/$(VARIANT_DIR)/gma-mainboard.ads
diff --git a/src/mainboard/starlabs/starfighter/hda_verb.c b/src/mainboard/starlabs/starfighter/hda_verb.c
deleted file mode 100644
index 0aec559a03..0000000000
--- a/src/mainboard/starlabs/starfighter/hda_verb.c
+++ /dev/null
@@ -1,26 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <console/console.h>
-#include <device/azalia_device.h>
-#include <option.h>
-#include <types.h>
-
-#define AZALIA_CODEC_ALC256 0x10ec0256
-
-static const u32 override_verb[] = {
-	AZALIA_PIN_CFG(0, 0x12, 0x411111f0),
-};
-
-static void disable_microphone(u8 *base)
-{
-	azalia_program_verb_table(base, override_verb, ARRAY_SIZE(override_verb));
-}
-
-void mainboard_azalia_program_runtime_verbs(u8 *base, u32 viddid)
-{
-	if (viddid == AZALIA_CODEC_ALC256) {
-		printk(BIOS_DEBUG, "CMOS: viddid = %08x\n", viddid);
-		if (get_uint_option("microphone", 1) == 0)
-			disable_microphone(base);
-	}
-}
diff --git a/src/mainboard/starlabs/starlite_adl/Kconfig b/src/mainboard/starlabs/starlite_adl/Kconfig
index 638fe72d0e..d14b441be1 100644
--- a/src/mainboard/starlabs/starlite_adl/Kconfig
+++ b/src/mainboard/starlabs/starlite_adl/Kconfig
@@ -17,6 +17,7 @@ config BOARD_STARLABS_STARLITE_SERIES
 	select EC_STARLABS_POWER_LED
 	select HAVE_ACPI_RESUME
 	select HAVE_ACPI_TABLES
+	select HAVE_HDA_DMIC
 	select HAVE_INTEL_PTT
 	select HAVE_OPTION_TABLE
 	select HAVE_SPD_IN_CBFS
diff --git a/src/mainboard/starlabs/starlite_adl/Makefile.mk b/src/mainboard/starlabs/starlite_adl/Makefile.mk
index 17c1dc2f4d..14842f76e4 100644
--- a/src/mainboard/starlabs/starlite_adl/Makefile.mk
+++ b/src/mainboard/starlabs/starlite_adl/Makefile.mk
@@ -11,5 +11,4 @@ verstage-$(CONFIG_VBOOT) += vboot.c
 romstage-$(CONFIG_VBOOT) += vboot.c
 
 ramstage-$(CONFIG_DRIVERS_OPTION_CFR) += cfr.c
-ramstage-y += hda_verb.c
 ramstage-y += mainboard.c
diff --git a/src/mainboard/starlabs/starlite_adl/hda_verb.c b/src/mainboard/starlabs/starlite_adl/hda_verb.c
deleted file mode 100644
index 787e55a17b..0000000000
--- a/src/mainboard/starlabs/starlite_adl/hda_verb.c
+++ /dev/null
@@ -1,26 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <console/console.h>
-#include <device/azalia_device.h>
-#include <option.h>
-#include <types.h>
-
-#define AZALIA_CODEC_ALC269	0x10ec0269
-
-static const u32 override_verb[] = {
-	AZALIA_PIN_CFG(0, 0x12, 0x00000000),
-};
-
-static void disable_microphone(u8 *base)
-{
-	azalia_program_verb_table(base, override_verb, ARRAY_SIZE(override_verb));
-}
-
-void mainboard_azalia_program_runtime_verbs(u8 *base, u32 viddid)
-{
-	if (viddid == AZALIA_CODEC_ALC269) {
-		printk(BIOS_DEBUG, "CMOS: viddid = %08x\n", viddid);
-		if (get_uint_option("microphone", 1) == 0)
-			disable_microphone(base);
-	}
-}

From 87475ef37f57b89a9f1a441b39df8a43acc7f951 Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Mon, 27 Oct 2025 08:18:21 +0000
Subject: [PATCH 2434/3886] mb/starlabs/common: Move power profile enum to
 common code

This isn't a functional change, just reduces duplicated code.

Change-Id: I00b08a71d85be73fbadc25df685f7f9e04cc76c0
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89762
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
---
 .../starlabs/byte_adl/include/variants.h          |  9 ---------
 src/mainboard/starlabs/byte_adl/mainboard.c       |  6 ------
 .../starlabs/byte_adl/variants/mk_ii/devtree.c    |  1 +
 src/mainboard/starlabs/common/Makefile.mk         |  1 +
 .../starlabs/common/include/common/cfr.h          |  2 +-
 .../starlabs/common/include/common/powercap.h     | 15 +++++++++++++++
 .../starlabs/common/powercap/Makefile.mk          |  5 +++++
 src/mainboard/starlabs/common/powercap/powercap.c | 10 ++++++++++
 src/mainboard/starlabs/lite/devtree.c             |  7 +------
 src/mainboard/starlabs/lite/include/variants.h    |  9 ---------
 .../starlabs/starbook/include/variants.h          |  9 ---------
 src/mainboard/starlabs/starbook/mainboard.c       |  6 ------
 .../starlabs/starbook/variants/adl/devtree.c      |  1 +
 .../starlabs/starbook/variants/adl_n/devtree.c    |  1 +
 .../starlabs/starbook/variants/cml/devtree.c      |  1 +
 .../starlabs/starbook/variants/kbl/devtree.c      |  1 +
 .../starlabs/starbook/variants/mtl/devtree.c      |  1 +
 .../starlabs/starbook/variants/rpl/devtree.c      |  1 +
 .../starlabs/starbook/variants/tgl/devtree.c      |  1 +
 .../starlabs/starfighter/include/variants.h       |  9 ---------
 src/mainboard/starlabs/starfighter/mainboard.c    |  6 ------
 .../starlabs/starfighter/variants/rpl/devtree.c   |  1 +
 .../starlabs/starlite_adl/include/variants.h      |  9 ---------
 src/mainboard/starlabs/starlite_adl/mainboard.c   |  6 ------
 .../starlabs/starlite_adl/variants/mk_v/devtree.c |  1 +
 25 files changed, 43 insertions(+), 76 deletions(-)
 create mode 100644 src/mainboard/starlabs/common/include/common/powercap.h
 create mode 100644 src/mainboard/starlabs/common/powercap/Makefile.mk
 create mode 100644 src/mainboard/starlabs/common/powercap/powercap.c

diff --git a/src/mainboard/starlabs/byte_adl/include/variants.h b/src/mainboard/starlabs/byte_adl/include/variants.h
index 0dd41c062c..c95d15bd72 100644
--- a/src/mainboard/starlabs/byte_adl/include/variants.h
+++ b/src/mainboard/starlabs/byte_adl/include/variants.h
@@ -5,15 +5,6 @@
 
 #include <soc/gpio.h>
 
-enum cmos_power_profile {
-	PP_POWER_SAVER = 0,
-	PP_BALANCED    = 1,
-	PP_PERFORMANCE = 2,
-};
-#define NUM_POWER_PROFILES 3
-
-enum cmos_power_profile get_power_profile(enum cmos_power_profile fallback);
-
 /*
  * The next set of functions return the gpio table and fill in the number of
  * entries for each table.
diff --git a/src/mainboard/starlabs/byte_adl/mainboard.c b/src/mainboard/starlabs/byte_adl/mainboard.c
index d394f2579d..60e65ee8c4 100644
--- a/src/mainboard/starlabs/byte_adl/mainboard.c
+++ b/src/mainboard/starlabs/byte_adl/mainboard.c
@@ -5,12 +5,6 @@
 #include <option.h>
 #include <variants.h>
 
-enum cmos_power_profile get_power_profile(enum cmos_power_profile fallback)
-{
-	const unsigned int power_profile = get_uint_option("power_profile", fallback);
-	return power_profile < NUM_POWER_PROFILES ? power_profile : fallback;
-}
-
 static void init_mainboard(void *chip_info)
 {
 	const struct pad_config *pads;
diff --git a/src/mainboard/starlabs/byte_adl/variants/mk_ii/devtree.c b/src/mainboard/starlabs/byte_adl/variants/mk_ii/devtree.c
index 2b273952ab..b9746623fe 100644
--- a/src/mainboard/starlabs/byte_adl/variants/mk_ii/devtree.c
+++ b/src/mainboard/starlabs/byte_adl/variants/mk_ii/devtree.c
@@ -8,6 +8,7 @@
 #include <static.h>
 #include <types.h>
 #include <variants.h>
+#include <common/powercap.h>
 
 #define TJ_MAX		105
 #define TCC(temp)	(TJ_MAX - temp)
diff --git a/src/mainboard/starlabs/common/Makefile.mk b/src/mainboard/starlabs/common/Makefile.mk
index 07ac8e9640..90c0d94d5a 100644
--- a/src/mainboard/starlabs/common/Makefile.mk
+++ b/src/mainboard/starlabs/common/Makefile.mk
@@ -2,6 +2,7 @@
 
 subdirs-$(CONFIG_VENDOR_STARLABS) += cfr
 subdirs-$(CONFIG_VENDOR_STARLABS) += hda
+subdirs-$(CONFIG_VENDOR_STARLABS) += powercap
 subdirs-$(CONFIG_VENDOR_STARLABS) += pin_mux
 subdirs-$(CONFIG_VENDOR_STARLABS) += smbios
 
diff --git a/src/mainboard/starlabs/common/include/common/cfr.h b/src/mainboard/starlabs/common/include/common/cfr.h
index d6bb406a24..e71f1bafd3 100644
--- a/src/mainboard/starlabs/common/include/common/cfr.h
+++ b/src/mainboard/starlabs/common/include/common/cfr.h
@@ -4,7 +4,7 @@
 #define _STARLABS_CMN_CFR_H_
 
 #include <drivers/option/cfr_frontend.h>
-#include <variants.h>
+#include <common/powercap.h>
 
 void cfr_card_reader_update(const struct sm_object *obj, struct sm_object *new_obj);
 
diff --git a/src/mainboard/starlabs/common/include/common/powercap.h b/src/mainboard/starlabs/common/include/common/powercap.h
new file mode 100644
index 0000000000..aa1d68f418
--- /dev/null
+++ b/src/mainboard/starlabs/common/include/common/powercap.h
@@ -0,0 +1,15 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef _STARLABS_CMN_POWERCAP_H_
+#define _STARLABS_CMN_POWERCAP_H_
+
+enum cmos_power_profile {
+	PP_POWER_SAVER	= 0,
+	PP_BALANCED	= 1,
+	PP_PERFORMANCE	= 2,
+};
+#define NUM_POWER_PROFILES 3
+
+enum cmos_power_profile get_power_profile(enum cmos_power_profile fallback);
+
+#endif
diff --git a/src/mainboard/starlabs/common/powercap/Makefile.mk b/src/mainboard/starlabs/common/powercap/Makefile.mk
new file mode 100644
index 0000000000..1ff73ef3d0
--- /dev/null
+++ b/src/mainboard/starlabs/common/powercap/Makefile.mk
@@ -0,0 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
+ramstage-y += powercap.c
+
+CPPFLAGS_common += -I$(src)/mainboard/starlabs/common/powercap
diff --git a/src/mainboard/starlabs/common/powercap/powercap.c b/src/mainboard/starlabs/common/powercap/powercap.c
new file mode 100644
index 0000000000..e19e6ec403
--- /dev/null
+++ b/src/mainboard/starlabs/common/powercap/powercap.c
@@ -0,0 +1,10 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <option.h>
+#include <common/powercap.h>
+
+enum cmos_power_profile get_power_profile(enum cmos_power_profile fallback)
+{
+	const unsigned int power_profile = get_uint_option("power_profile", fallback);
+	return power_profile < NUM_POWER_PROFILES ? power_profile : fallback;
+}
diff --git a/src/mainboard/starlabs/lite/devtree.c b/src/mainboard/starlabs/lite/devtree.c
index bd43b2154c..b86c38b208 100644
--- a/src/mainboard/starlabs/lite/devtree.c
+++ b/src/mainboard/starlabs/lite/devtree.c
@@ -7,15 +7,10 @@
 #include <static.h>
 #include <types.h>
 #include <variants.h>
+#include <common/powercap.h>
 
 #include "soc/intel/apollolake/chip.h"
 
-enum cmos_power_profile get_power_profile(enum cmos_power_profile fallback)
-{
-	const unsigned int power_profile = get_uint_option("power_profile", fallback);
-	return power_profile < NUM_POWER_PROFILES ? power_profile : fallback;
-}
-
 void devtree_update(void)
 {
 	config_t *cfg = config_of_soc();
diff --git a/src/mainboard/starlabs/lite/include/variants.h b/src/mainboard/starlabs/lite/include/variants.h
index 5df05a3b62..781a8313f2 100644
--- a/src/mainboard/starlabs/lite/include/variants.h
+++ b/src/mainboard/starlabs/lite/include/variants.h
@@ -5,15 +5,6 @@
 
 #include <gpio.h>
 
-enum cmos_power_profile {
-	PP_POWER_SAVER = 0,
-	PP_BALANCED    = 1,
-	PP_PERFORMANCE = 2,
-};
-#define NUM_POWER_PROFILES 3
-
-enum cmos_power_profile get_power_profile(enum cmos_power_profile fallback);
-
 /*
  * The next set of functions return the gpio table and fill in the number of
  * entries for each table.
diff --git a/src/mainboard/starlabs/starbook/include/variants.h b/src/mainboard/starlabs/starbook/include/variants.h
index 5df05a3b62..781a8313f2 100644
--- a/src/mainboard/starlabs/starbook/include/variants.h
+++ b/src/mainboard/starlabs/starbook/include/variants.h
@@ -5,15 +5,6 @@
 
 #include <gpio.h>
 
-enum cmos_power_profile {
-	PP_POWER_SAVER = 0,
-	PP_BALANCED    = 1,
-	PP_PERFORMANCE = 2,
-};
-#define NUM_POWER_PROFILES 3
-
-enum cmos_power_profile get_power_profile(enum cmos_power_profile fallback);
-
 /*
  * The next set of functions return the gpio table and fill in the number of
  * entries for each table.
diff --git a/src/mainboard/starlabs/starbook/mainboard.c b/src/mainboard/starlabs/starbook/mainboard.c
index 4141475a5d..772e32cc1c 100644
--- a/src/mainboard/starlabs/starbook/mainboard.c
+++ b/src/mainboard/starlabs/starbook/mainboard.c
@@ -6,12 +6,6 @@
 #include <option.h>
 #include <variants.h>
 
-enum cmos_power_profile get_power_profile(enum cmos_power_profile fallback)
-{
-	const unsigned int power_profile = get_uint_option("power_profile", fallback);
-	return power_profile < NUM_POWER_PROFILES ? power_profile : fallback;
-}
-
 static void init_mainboard(void *chip_info)
 {
 	const struct pad_config *pads;
diff --git a/src/mainboard/starlabs/starbook/variants/adl/devtree.c b/src/mainboard/starlabs/starbook/variants/adl/devtree.c
index 01557f875f..22b66d0d9f 100644
--- a/src/mainboard/starlabs/starbook/variants/adl/devtree.c
+++ b/src/mainboard/starlabs/starbook/variants/adl/devtree.c
@@ -8,6 +8,7 @@
 #include <static.h>
 #include <types.h>
 #include <variants.h>
+#include <common/powercap.h>
 
 #define TJ_MAX		110
 #define TCC(temp)	(TJ_MAX - temp)
diff --git a/src/mainboard/starlabs/starbook/variants/adl_n/devtree.c b/src/mainboard/starlabs/starbook/variants/adl_n/devtree.c
index afea557b0b..437a73c1bb 100644
--- a/src/mainboard/starlabs/starbook/variants/adl_n/devtree.c
+++ b/src/mainboard/starlabs/starbook/variants/adl_n/devtree.c
@@ -8,6 +8,7 @@
 #include <static.h>
 #include <types.h>
 #include <variants.h>
+#include <common/powercap.h>
 
 #define TJ_MAX		105
 #define TCC(temp)	(TJ_MAX - temp)
diff --git a/src/mainboard/starlabs/starbook/variants/cml/devtree.c b/src/mainboard/starlabs/starbook/variants/cml/devtree.c
index f5975dd9e0..d9bafcabd5 100644
--- a/src/mainboard/starlabs/starbook/variants/cml/devtree.c
+++ b/src/mainboard/starlabs/starbook/variants/cml/devtree.c
@@ -8,6 +8,7 @@
 #include <static.h>
 #include <types.h>
 #include <variants.h>
+#include <common/powercap.h>
 
 #define TJ_MAX		100
 #define TCC(temp)	(TJ_MAX - temp)
diff --git a/src/mainboard/starlabs/starbook/variants/kbl/devtree.c b/src/mainboard/starlabs/starbook/variants/kbl/devtree.c
index 16244ad047..c648be9da7 100644
--- a/src/mainboard/starlabs/starbook/variants/kbl/devtree.c
+++ b/src/mainboard/starlabs/starbook/variants/kbl/devtree.c
@@ -8,6 +8,7 @@
 #include <static.h>
 #include <types.h>
 #include <variants.h>
+#include <common/powercap.h>
 
 #define TJ_MAX		100
 #define TCC(temp)	(TJ_MAX - temp)
diff --git a/src/mainboard/starlabs/starbook/variants/mtl/devtree.c b/src/mainboard/starlabs/starbook/variants/mtl/devtree.c
index 82c137b557..fdfec7468d 100644
--- a/src/mainboard/starlabs/starbook/variants/mtl/devtree.c
+++ b/src/mainboard/starlabs/starbook/variants/mtl/devtree.c
@@ -8,6 +8,7 @@
 #include <static.h>
 #include <types.h>
 #include <variants.h>
+#include <common/powercap.h>
 
 #define TJ_MAX		110
 #define TCC(temp)	(TJ_MAX - temp)
diff --git a/src/mainboard/starlabs/starbook/variants/rpl/devtree.c b/src/mainboard/starlabs/starbook/variants/rpl/devtree.c
index f9680fe3b0..32ba845ba8 100644
--- a/src/mainboard/starlabs/starbook/variants/rpl/devtree.c
+++ b/src/mainboard/starlabs/starbook/variants/rpl/devtree.c
@@ -8,6 +8,7 @@
 #include <static.h>
 #include <types.h>
 #include <variants.h>
+#include <common/powercap.h>
 
 #define TJ_MAX		110
 #define TCC(temp)	(TJ_MAX - temp)
diff --git a/src/mainboard/starlabs/starbook/variants/tgl/devtree.c b/src/mainboard/starlabs/starbook/variants/tgl/devtree.c
index f507025487..d83c2b55a7 100644
--- a/src/mainboard/starlabs/starbook/variants/tgl/devtree.c
+++ b/src/mainboard/starlabs/starbook/variants/tgl/devtree.c
@@ -8,6 +8,7 @@
 #include <static.h>
 #include <types.h>
 #include <variants.h>
+#include <common/powercap.h>
 
 #define TJ_MAX		100
 #define TCC(temp)	(TJ_MAX - temp)
diff --git a/src/mainboard/starlabs/starfighter/include/variants.h b/src/mainboard/starlabs/starfighter/include/variants.h
index 0dd41c062c..c95d15bd72 100644
--- a/src/mainboard/starlabs/starfighter/include/variants.h
+++ b/src/mainboard/starlabs/starfighter/include/variants.h
@@ -5,15 +5,6 @@
 
 #include <soc/gpio.h>
 
-enum cmos_power_profile {
-	PP_POWER_SAVER = 0,
-	PP_BALANCED    = 1,
-	PP_PERFORMANCE = 2,
-};
-#define NUM_POWER_PROFILES 3
-
-enum cmos_power_profile get_power_profile(enum cmos_power_profile fallback);
-
 /*
  * The next set of functions return the gpio table and fill in the number of
  * entries for each table.
diff --git a/src/mainboard/starlabs/starfighter/mainboard.c b/src/mainboard/starlabs/starfighter/mainboard.c
index e9c17e53ed..c474390e46 100644
--- a/src/mainboard/starlabs/starfighter/mainboard.c
+++ b/src/mainboard/starlabs/starfighter/mainboard.c
@@ -6,12 +6,6 @@
 #include <option.h>
 #include <variants.h>
 
-enum cmos_power_profile get_power_profile(enum cmos_power_profile fallback)
-{
-	const unsigned int power_profile = get_uint_option("power_profile", fallback);
-	return power_profile < NUM_POWER_PROFILES ? power_profile : fallback;
-}
-
 static void init_mainboard(void *chip_info)
 {
 	const struct pad_config *pads;
diff --git a/src/mainboard/starlabs/starfighter/variants/rpl/devtree.c b/src/mainboard/starlabs/starfighter/variants/rpl/devtree.c
index 5fb56c3f46..fe9d9117dc 100644
--- a/src/mainboard/starlabs/starfighter/variants/rpl/devtree.c
+++ b/src/mainboard/starlabs/starfighter/variants/rpl/devtree.c
@@ -8,6 +8,7 @@
 #include <static.h>
 #include <types.h>
 #include <variants.h>
+#include <common/powercap.h>
 
 #define TJ_MAX		110
 #define TCC(temp)	(TJ_MAX - temp)
diff --git a/src/mainboard/starlabs/starlite_adl/include/variants.h b/src/mainboard/starlabs/starlite_adl/include/variants.h
index 0dd41c062c..c95d15bd72 100644
--- a/src/mainboard/starlabs/starlite_adl/include/variants.h
+++ b/src/mainboard/starlabs/starlite_adl/include/variants.h
@@ -5,15 +5,6 @@
 
 #include <soc/gpio.h>
 
-enum cmos_power_profile {
-	PP_POWER_SAVER = 0,
-	PP_BALANCED    = 1,
-	PP_PERFORMANCE = 2,
-};
-#define NUM_POWER_PROFILES 3
-
-enum cmos_power_profile get_power_profile(enum cmos_power_profile fallback);
-
 /*
  * The next set of functions return the gpio table and fill in the number of
  * entries for each table.
diff --git a/src/mainboard/starlabs/starlite_adl/mainboard.c b/src/mainboard/starlabs/starlite_adl/mainboard.c
index 98a4ea0506..b82e2c0eba 100644
--- a/src/mainboard/starlabs/starlite_adl/mainboard.c
+++ b/src/mainboard/starlabs/starlite_adl/mainboard.c
@@ -6,12 +6,6 @@
 #include <option.h>
 #include <variants.h>
 
-enum cmos_power_profile get_power_profile(enum cmos_power_profile fallback)
-{
-	const unsigned int power_profile = get_uint_option("power_profile", fallback);
-	return power_profile < NUM_POWER_PROFILES ? power_profile : fallback;
-}
-
 static void init_mainboard(void *chip_info)
 {
 	const struct pad_config *pads;
diff --git a/src/mainboard/starlabs/starlite_adl/variants/mk_v/devtree.c b/src/mainboard/starlabs/starlite_adl/variants/mk_v/devtree.c
index 31de19db97..35d289c7ad 100644
--- a/src/mainboard/starlabs/starlite_adl/variants/mk_v/devtree.c
+++ b/src/mainboard/starlabs/starlite_adl/variants/mk_v/devtree.c
@@ -8,6 +8,7 @@
 #include <static.h>
 #include <types.h>
 #include <variants.h>
+#include <common/powercap.h>
 
 #define TJ_MAX		105
 #define TCC(temp)	(TJ_MAX - temp)

From 0d35c3fcc3e7cc52f7400a65b8a23b6da677e740 Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Tue, 4 Nov 2025 20:37:38 +0000
Subject: [PATCH 2435/3886] mb/starlabs/starbook: Fix inclusion of CPU RP ASPM
 option

The ASPM option for CPU root ports was guarded against the
SOC supporting CPU root ports. This meant that the option
was visible for boards that didn't utilise the CPU root
ports.

Adjust this to guard against BOARD_STARLABS_STARBOOK_RPL,
which is the only board to actually use the CPU root ports.

Change-Id: Id632a8279e8c1cb07536b4198c3752d57eee657a
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89908
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/starlabs/starbook/cfr.c | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/src/mainboard/starlabs/starbook/cfr.c b/src/mainboard/starlabs/starbook/cfr.c
index e1f3f6dd56..cddc9af16f 100644
--- a/src/mainboard/starlabs/starbook/cfr.c
+++ b/src/mainboard/starlabs/starbook/cfr.c
@@ -90,9 +90,10 @@ static struct sm_obj_form pci = {
 		#endif
 		#if CONFIG(SOC_INTEL_COMMON_BLOCK_ASPM)
 		&pciexp_clk_pm,
-		&pciexp_aspm,
-		#if CONFIG(HAS_INTEL_CPU_ROOT_PORTS)
+		#if CONFIG(BOARD_STARLABS_STARBOOK_RPL)
 		&pciexp_aspm_cpu,
+		#else
+		&pciexp_aspm,
 		#endif
 		&pciexp_l1ss,
 		#endif

From 649a6a591bcde3eccda6f718fa4f51587ef9af44 Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Tue, 4 Nov 2025 20:45:19 +0000
Subject: [PATCH 2436/3886] ec/starlabs/merlin: Correct Kconfig dependancies

MAX_CHARGE and FAN aren't available for the Nuvoton EC, so
remove the dependency.

Change-Id: Ie087b1c4503a397621b8fd714564cc082150d7a6
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89909
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/ec/starlabs/merlin/Kconfig | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/ec/starlabs/merlin/Kconfig b/src/ec/starlabs/merlin/Kconfig
index 12c4600b42..01a02eb958 100644
--- a/src/ec/starlabs/merlin/Kconfig
+++ b/src/ec/starlabs/merlin/Kconfig
@@ -40,14 +40,14 @@ config EC_STARLABS_KBL_LEVELS
 config EC_STARLABS_FAN
 	bool
 	default n
-	depends on EC_STARLABS_ITE || EC_STARLABS_NUVOTON
+	depends on EC_STARLABS_ITE
 	help
 	  Select if the mainboard has a fan.
 
 config EC_STARLABS_MAX_CHARGE
 	bool
 	default n
-	depends on EC_STARLABS_ITE || EC_STARLABS_NUVOTON
+	depends on EC_STARLABS_ITE
 	help
 	  Select if the mainboard supports limiting the maximum charge of the battery.
 

From 696344ac011ba0d8a6cd878e3d84e10c43ecbdff Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Tue, 4 Nov 2025 20:54:26 +0000
Subject: [PATCH 2437/3886] ec/starlabs/merlin: Optimise Kconfig defaults

The featureset of Merlin is common, so adjust the Kconfig options
to avoid having the boards select all of them.

This is not a functional change.

Change-Id: Ie8d7afed750055274cdfde3f2f4f9b70fa47a8b1
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89910
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
---
 src/ec/starlabs/merlin/Kconfig              | 81 +++++++++++----------
 src/mainboard/starlabs/byte_adl/Kconfig     |  5 +-
 src/mainboard/starlabs/starbook/Kconfig     | 21 +-----
 src/mainboard/starlabs/starfighter/Kconfig  |  8 --
 src/mainboard/starlabs/starlite_adl/Kconfig |  8 --
 5 files changed, 44 insertions(+), 79 deletions(-)

diff --git a/src/ec/starlabs/merlin/Kconfig b/src/ec/starlabs/merlin/Kconfig
index 01a02eb958..8599fa903c 100644
--- a/src/ec/starlabs/merlin/Kconfig
+++ b/src/ec/starlabs/merlin/Kconfig
@@ -8,6 +8,7 @@ config EC_STARLABS_NUVOTON
 
 config EC_STARLABS_ITE
 	bool
+	default y if EC_STARLABS_MERLIN
 	select EC_ACPI
 	help
 	  Interface to ITE embedded controller principally in Star Labs notebooks.
@@ -30,6 +31,11 @@ config EC_STARLABS_ITE_BIN_PATH
 	string "Star Labs EC binary file path"
 	depends on EC_STARLABS_ADD_ITE_BIN
 
+config EC_STARLABS_FAN
+	bool
+	help
+	  Select if the mainboard has a fan.
+
 config EC_STARLABS_KBL_LEVELS
 	bool
 	default n
@@ -37,46 +43,6 @@ config EC_STARLABS_KBL_LEVELS
 	help
 	  Select if the mainboard supports multiple levels of brightness for the keyboard.
 
-config EC_STARLABS_FAN
-	bool
-	default n
-	depends on EC_STARLABS_ITE
-	help
-	  Select if the mainboard has a fan.
-
-config EC_STARLABS_MAX_CHARGE
-	bool
-	default n
-	depends on EC_STARLABS_ITE
-	help
-	  Select if the mainboard supports limiting the maximum charge of the battery.
-
-config EC_STARLABS_CHARGING_SPEED
-	bool "Enable setting the charging speed"
-	depends on EC_STARLABS_MERLIN
-	help
-	  Select if the mainboard supports configuring the charging speed.
-
-config EC_STARLABS_LID_SWITCH
-	bool "Enable disabling the lid switch"
-	depends on EC_STARLABS_ITE
-	help
-	  Select if the mainboard supports disabling the lid switch
-
-config EC_STARLABS_POWER_LED
-	bool "Enable lowering the brightess of the Power LED"
-	depends on EC_STARLABS_ITE
-	help
-	  Select the in the mainboard supports reducing the LED brightness
-
-config EC_STARLABS_MERLIN
-	bool "Use open-source Merlin EC Firmware"
-	default n
-	depends on EC_STARLABS_ITE
-	help
-	  Use open source embedded controller firmware. Both firmwares have the
-	  same features but differ in licensing and compilers.
-
 config EC_VARIANT_DIR
 	string
 	default "merlin" if EC_STARLABS_MERLIN
@@ -96,3 +62,38 @@ config EC_STARLABS_BATTERY_TYPE
 config EC_STARLABS_BATTERY_OEM
 	string
 	default "Unknown"
+
+config EC_STARLABS_MERLIN
+	bool "Use open-source Merlin EC Firmware"
+	default n
+	help
+	  Use open source embedded controller firmware. Both firmwares have the
+	  same features but differ in licensing and compilers.
+
+if EC_STARLABS_MERLIN
+
+config EC_STARLABS_MAX_CHARGE
+	bool
+	default y
+	help
+	  Select if the mainboard supports limiting the maximum charge of the battery.
+
+config EC_STARLABS_CHARGING_SPEED
+	bool "Enable setting the charging speed"
+	default y
+	help
+	  Select if the mainboard supports configuring the charging speed.
+
+config EC_STARLABS_LID_SWITCH
+	bool "Enable disabling the lid switch"
+	default y
+	help
+	  Select if the mainboard supports disabling the lid switch
+
+config EC_STARLABS_POWER_LED
+	bool "Enable lowering the brightess of the Power LED"
+	default y
+	help
+	  Select the in the mainboard supports reducing the LED brightness
+
+endif
diff --git a/src/mainboard/starlabs/byte_adl/Kconfig b/src/mainboard/starlabs/byte_adl/Kconfig
index d3df0e0c44..e0e6de1267 100644
--- a/src/mainboard/starlabs/byte_adl/Kconfig
+++ b/src/mainboard/starlabs/byte_adl/Kconfig
@@ -8,7 +8,7 @@ config BOARD_STARLABS_BYTE_SERIES
 	select DRIVERS_INTEL_PMC
 	select DRIVERS_OPTION_CFR_ENABLED
 	select DRIVERS_PCIE_GENERIC
-	select EC_STARLABS_ITE
+	select EC_STARLABS_FAN
 	select EC_STARLABS_MERLIN
 	select HAVE_ACPI_RESUME
 	select HAVE_ACPI_TABLES
@@ -59,9 +59,6 @@ config EC_STARLABS_ITE_BIN_PATH
 	string
 	default "3rdparty/blobs/mainboard/\$(MAINBOARDDIR)/\$(CONFIG_VARIANT_DIR)/ec.bin"
 
-config EC_VARIANT_DIR
-	default "merlin"
-
 config FMDFILE
 	default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/variants/\$(CONFIG_VARIANT_DIR)/vboot.fmd" if VBOOT
 	default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/variants/\$(CONFIG_VARIANT_DIR)/board.fmd"
diff --git a/src/mainboard/starlabs/starbook/Kconfig b/src/mainboard/starlabs/starbook/Kconfig
index 244bcfb195..27761dc507 100644
--- a/src/mainboard/starlabs/starbook/Kconfig
+++ b/src/mainboard/starlabs/starbook/Kconfig
@@ -7,7 +7,6 @@ config BOARD_STARLABS_STARBOOK_SERIES
 	select DRIVERS_EFI_VARIABLE_STORE
 	select DRIVERS_OPTION_CFR_ENABLED
 	select DRIVERS_I2C_HID
-	select EC_STARLABS_ITE
 	select EC_STARLABS_FAN
 	select HAVE_ACPI_RESUME
 	select HAVE_ACPI_TABLES
@@ -26,6 +25,8 @@ config BOARD_STARLABS_LABTOP_KBL
 	select BOARD_ROMSIZE_KB_8192
 	select BOARD_STARLABS_STARBOOK_SERIES
 	select CRB_TPM
+	select EC_STARLABS_ITE
+	select EC_STARLABS_FAN
 	select HAVE_INTEL_PTT
 	select HAVE_SPD_IN_CBFS
 	select SOC_INTEL_KABYLAKE
@@ -35,10 +36,6 @@ config BOARD_STARLABS_LABTOP_KBL
 config BOARD_STARLABS_LABTOP_CML
 	select BOARD_ROMSIZE_KB_16384
 	select BOARD_STARLABS_STARBOOK_SERIES
-	select EC_STARLABS_CHARGING_SPEED
-	select EC_STARLABS_KBL_LEVELS
-	select EC_STARLABS_LID_SWITCH
-	select EC_STARLABS_MAX_CHARGE
 	select EC_STARLABS_MERLIN
 	select HAVE_INTEL_PTT
 	select HAVE_SPD_IN_CBFS
@@ -52,10 +49,6 @@ config BOARD_STARLABS_STARBOOK_TGL
 	select BOARD_STARLABS_STARBOOK_SERIES
 	select DRIVERS_INTEL_PMC
 	select DRIVERS_INTEL_USB4_RETIMER
-	select EC_STARLABS_CHARGING_SPEED
-	select EC_STARLABS_KBL_LEVELS
-	select EC_STARLABS_LID_SWITCH
-	select EC_STARLABS_MAX_CHARGE
 	select EC_STARLABS_MERLIN
 	select MAINBOARD_HAS_TPM2
 	select MEMORY_MAPPED_TPM
@@ -69,10 +62,6 @@ config BOARD_STARLABS_STARBOOK_ADL_COMMON
 	def_bool n
 	select BOARD_STARLABS_STARBOOK_SERIES
 	select DRIVERS_INTEL_PMC
-	select EC_STARLABS_CHARGING_SPEED
-	select EC_STARLABS_KBL_LEVELS
-	select EC_STARLABS_LID_SWITCH
-	select EC_STARLABS_MAX_CHARGE
 	select EC_STARLABS_MERLIN
 	select DRIVERS_GFX_GENERIC
 	select MAINBOARD_HAS_TPM2
@@ -107,10 +96,6 @@ config BOARD_STARLABS_STARBOOK_MTL
 	select BOARD_STARLABS_STARBOOK_SERIES
 	select DRIVERS_GFX_GENERIC
 	select DRIVERS_INTEL_PMC
-	select EC_STARLABS_CHARGING_SPEED
-	select EC_STARLABS_KBL_LEVELS
-	select EC_STARLABS_LID_SWITCH
-	select EC_STARLABS_MAX_CHARGE
 	select EC_STARLABS_MERLIN
 	select MAINBOARD_HAS_TPM2
 	select MEMORY_MAPPED_TPM
@@ -166,8 +151,6 @@ config EC_STARLABS_ITE_BIN_PATH
 
 config EC_VARIANT_DIR
 	default "kbl" if !EC_STARLABS_MERLIN && BOARD_STARLABS_LABTOP_KBL
-	default "cml" if !EC_STARLABS_MERLIN && BOARD_STARLABS_LABTOP_CML
-	default "merlin"
 
 config EDK2_BOOTSPLASH_FILE
 	string
diff --git a/src/mainboard/starlabs/starfighter/Kconfig b/src/mainboard/starlabs/starfighter/Kconfig
index 28838aacd4..a5dbe709c8 100644
--- a/src/mainboard/starlabs/starfighter/Kconfig
+++ b/src/mainboard/starlabs/starfighter/Kconfig
@@ -12,11 +12,6 @@ config BOARD_STARLABS_STARFIGHTER_SERIES
 	select DRIVERS_INTEL_USB4_RETIMER
 	select DRIVERS_I2C_HID
 	select EC_STARLABS_FAN
-	select EC_STARLABS_ITE
-	select EC_STARLABS_CHARGING_SPEED
-	select EC_STARLABS_KBL_LEVELS
-	select EC_STARLABS_LID_SWITCH
-	select EC_STARLABS_MAX_CHARGE
 	select EC_STARLABS_MERLIN
 	select HAVE_ACPI_RESUME
 	select HAVE_ACPI_TABLES
@@ -80,9 +75,6 @@ config EC_STARLABS_ITE_BIN_PATH
 	string
 	default "3rdparty/blobs/mainboard/\$(MAINBOARDDIR)/\$(CONFIG_VARIANT_DIR)/ec.bin"
 
-config EC_VARIANT_DIR
-	default "merlin"
-
 config EDK2_BOOTSPLASH_FILE
 	string
 	default "3rdparty/blobs/mainboard/starlabs/Logo.bmp"
diff --git a/src/mainboard/starlabs/starlite_adl/Kconfig b/src/mainboard/starlabs/starlite_adl/Kconfig
index d14b441be1..68e6df8a81 100644
--- a/src/mainboard/starlabs/starlite_adl/Kconfig
+++ b/src/mainboard/starlabs/starlite_adl/Kconfig
@@ -9,12 +9,7 @@ config BOARD_STARLABS_STARLITE_SERIES
 	select DRIVERS_I2C_HID
 	select DRIVERS_INTEL_PMC
 	select DRIVERS_OPTION_CFR_ENABLED
-	select EC_STARLABS_CHARGING_SPEED
-	select EC_STARLABS_ITE
-	select EC_STARLABS_LID_SWITCH
-	select EC_STARLABS_MAX_CHARGE
 	select EC_STARLABS_MERLIN
-	select EC_STARLABS_POWER_LED
 	select HAVE_ACPI_RESUME
 	select HAVE_ACPI_TABLES
 	select HAVE_HDA_DMIC
@@ -73,9 +68,6 @@ config EC_STARLABS_ITE_BIN_PATH
 	string
 	default "3rdparty/blobs/mainboard/\$(MAINBOARDDIR)/\$(CONFIG_VARIANT_DIR)/ec.bin"
 
-config EC_VARIANT_DIR
-	default "merlin"
-
 config FMDFILE
 	default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/variants/\$(CONFIG_VARIANT_DIR)/vboot.fmd" if VBOOT
 	default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/variants/\$(CONFIG_VARIANT_DIR)/board.fmd"

From 224ddb85e3ed0a49de71614a9c3612e822df314e Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Tue, 4 Nov 2025 20:56:43 +0000
Subject: [PATCH 2438/3886] ec/starlabs/merlin: Choose a better default for GPE
 SCI

This isn't a function change, it just reduces the number of
overrides.

Change-Id: I9178028b40c04fe52f4f549365828005cfe5f8be
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89911
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/ec/starlabs/merlin/Kconfig              | 2 +-
 src/mainboard/starlabs/byte_adl/Kconfig     | 3 ---
 src/mainboard/starlabs/starbook/Kconfig     | 1 -
 src/mainboard/starlabs/starfighter/Kconfig  | 3 ---
 src/mainboard/starlabs/starlite_adl/Kconfig | 3 ---
 5 files changed, 1 insertion(+), 11 deletions(-)

diff --git a/src/ec/starlabs/merlin/Kconfig b/src/ec/starlabs/merlin/Kconfig
index 8599fa903c..c21ac68a0a 100644
--- a/src/ec/starlabs/merlin/Kconfig
+++ b/src/ec/starlabs/merlin/Kconfig
@@ -49,7 +49,7 @@ config EC_VARIANT_DIR
 
 config EC_GPE_SCI
 	hex
-	default 0x50
+	default 0x6e
 
 config EC_STARLABS_BATTERY_MODEL
 	string
diff --git a/src/mainboard/starlabs/byte_adl/Kconfig b/src/mainboard/starlabs/byte_adl/Kconfig
index e0e6de1267..04bdcc8ee2 100644
--- a/src/mainboard/starlabs/byte_adl/Kconfig
+++ b/src/mainboard/starlabs/byte_adl/Kconfig
@@ -52,9 +52,6 @@ config DEVICETREE
 config DIMM_SPD_SIZE
 	default 512
 
-config EC_GPE_SCI
-	default 0x6e
-
 config EC_STARLABS_ITE_BIN_PATH
 	string
 	default "3rdparty/blobs/mainboard/\$(MAINBOARDDIR)/\$(CONFIG_VARIANT_DIR)/ec.bin"
diff --git a/src/mainboard/starlabs/starbook/Kconfig b/src/mainboard/starlabs/starbook/Kconfig
index 27761dc507..7a7ac3919e 100644
--- a/src/mainboard/starlabs/starbook/Kconfig
+++ b/src/mainboard/starlabs/starbook/Kconfig
@@ -132,7 +132,6 @@ config DIMM_SPD_SIZE
 
 config EC_GPE_SCI
 	default 0x50 if BOARD_STARLABS_LABTOP_KBL || BOARD_STARLABS_LABTOP_CML
-	default 0x6e
 
 config EC_STARLABS_BATTERY_MODEL
 	default "AEC3987118-2S1P" if BOARD_STARLABS_LABTOP_KBL || BOARD_STARLABS_LABTOP_CML
diff --git a/src/mainboard/starlabs/starfighter/Kconfig b/src/mainboard/starlabs/starfighter/Kconfig
index a5dbe709c8..cad5ac64a1 100644
--- a/src/mainboard/starlabs/starfighter/Kconfig
+++ b/src/mainboard/starlabs/starfighter/Kconfig
@@ -59,9 +59,6 @@ config DEVICETREE
 config DIMM_SPD_SIZE
 	default 512
 
-config EC_GPE_SCI
-	default 0x6e
-
 config EC_STARLABS_BATTERY_MODEL
 	default "AEC617573-4S1P"
 
diff --git a/src/mainboard/starlabs/starlite_adl/Kconfig b/src/mainboard/starlabs/starlite_adl/Kconfig
index 68e6df8a81..6e66d653b0 100644
--- a/src/mainboard/starlabs/starlite_adl/Kconfig
+++ b/src/mainboard/starlabs/starlite_adl/Kconfig
@@ -52,9 +52,6 @@ config DEVICETREE
 config DIMM_SPD_SIZE
 	default 512
 
-config EC_GPE_SCI
-	default 0x6e
-
 config EC_STARLABS_BATTERY_MODEL
 	default "AEC3756153-2S1P-N"
 

From bdcd65bd7fc78e0a5b1d9c77ec54731f0fba695d Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Wed, 5 Nov 2025 20:11:11 +0000
Subject: [PATCH 2439/3886] ec/starlabs/merlin: Add battery capacity offsets

Add the battery design capacity and voltage offsets to the EC
definitons; these will be used by coreboot to calculate the
wattage which it'll use to set PL4.

Change-Id: Id0600ddd8ffaecab6004549ab51b7c06305d3c09
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89925
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/ec/starlabs/merlin/variants/glk/ecdefs.h  | 28 ++++++++++---------
 src/ec/starlabs/merlin/variants/glkr/ecdefs.h | 28 ++++++++++---------
 src/ec/starlabs/merlin/variants/kbl/ecdefs.h  | 28 ++++++++++---------
 .../starlabs/merlin/variants/merlin/ecdefs.h  | 28 ++++++++++---------
 4 files changed, 60 insertions(+), 52 deletions(-)

diff --git a/src/ec/starlabs/merlin/variants/glk/ecdefs.h b/src/ec/starlabs/merlin/variants/glk/ecdefs.h
index ecdff4a5aa..ed518f400a 100644
--- a/src/ec/starlabs/merlin/variants/glk/ecdefs.h
+++ b/src/ec/starlabs/merlin/variants/glk/ecdefs.h
@@ -11,18 +11,20 @@
 #define _EC_STARLABS_GLK_EC_DEFS_H
 
 /* EC RAM offsets. */
-#define ECRAM_MAJOR_VERSION	0x00
-#define ECRAM_MINOR_VERSION	0x01
-#define ECRAM_TRACKPAD_STATE	0x14
-#define ECRAM_KBL_STATE		0x19
-#define ECRAM_KBL_BRIGHTNESS	0x18
-#define ECRAM_KBL_TIMEOUT	0x1a
-#define ECRAM_FN_LOCK_STATE	0x2c
-#define ECRAM_FN_CTRL_REVERSE	0x2d
-#define ECRAM_MAX_CHARGE	dead_code_t(uint8_t)
-#define ECRAM_FAN_MODE		dead_code_t(uint8_t)
-#define ECRAM_CHARGING_SPEED	dead_code_t(uint8_t)
-#define ECRAM_LID_SWITCH	dead_code_t(uint8_t)
-#define ECRAM_POWER_LED		0x1f
+#define ECRAM_MAJOR_VERSION		0x00
+#define ECRAM_MINOR_VERSION		0x01
+#define ECRAM_TRACKPAD_STATE		0x14
+#define ECRAM_KBL_STATE			0x19
+#define ECRAM_KBL_BRIGHTNESS		0x18
+#define ECRAM_KBL_TIMEOUT		0x1a
+#define ECRAM_FN_LOCK_STATE		0x2c
+#define ECRAM_FN_CTRL_REVERSE		0x2d
+#define ECRAM_MAX_CHARGE		dead_code_t(uint8_t)
+#define ECRAM_FAN_MODE			dead_code_t(uint8_t)
+#define ECRAM_CHARGING_SPEED		dead_code_t(uint8_t)
+#define ECRAM_LID_SWITCH		dead_code_t(uint8_t)
+#define ECRAM_POWER_LED			0x1f
+#define ECRAM_BATTERY_DESIGN_CAPACITY	0x84
+#define ECRAM_BATTERY_DESIGN_VOLTAGE	0x86
 
 #endif
diff --git a/src/ec/starlabs/merlin/variants/glkr/ecdefs.h b/src/ec/starlabs/merlin/variants/glkr/ecdefs.h
index e6dbc2f25e..6d469b2785 100644
--- a/src/ec/starlabs/merlin/variants/glkr/ecdefs.h
+++ b/src/ec/starlabs/merlin/variants/glkr/ecdefs.h
@@ -14,18 +14,20 @@
 #define NUVOTON_CHIPID_VAL	0x0004
 
 /* EC RAM offsets. */
-#define ECRAM_MAJOR_VERSION	0x00
-#define ECRAM_MINOR_VERSION	0x01
-#define ECRAM_TRACKPAD_STATE	0x14
-#define ECRAM_KBL_STATE		0x16
-#define ECRAM_KBL_BRIGHTNESS	0x17
-#define ECRAM_KBL_TIMEOUT	0x12
-#define ECRAM_FN_LOCK_STATE	0x15
-#define ECRAM_FN_CTRL_REVERSE	0x13
-#define ECRAM_MAX_CHARGE	dead_code_t(uint8_t)
-#define ECRAM_FAN_MODE		dead_code_t(uint8_t)
-#define ECRAM_CHARGING_SPEED	dead_code_t(uint8_t)
-#define ECRAM_LID_SWITCH	dead_code_t(uint8_t)
-#define ECRAM_POWER_LED		0x1f
+#define ECRAM_MAJOR_VERSION		0x00
+#define ECRAM_MINOR_VERSION		0x01
+#define ECRAM_TRACKPAD_STATE		0x14
+#define ECRAM_KBL_STATE			0x16
+#define ECRAM_KBL_BRIGHTNESS		0x17
+#define ECRAM_KBL_TIMEOUT		0x12
+#define ECRAM_FN_LOCK_STATE		0x15
+#define ECRAM_FN_CTRL_REVERSE		0x13
+#define ECRAM_MAX_CHARGE		dead_code_t(uint8_t)
+#define ECRAM_FAN_MODE			dead_code_t(uint8_t)
+#define ECRAM_CHARGING_SPEED		dead_code_t(uint8_t)
+#define ECRAM_LID_SWITCH		dead_code_t(uint8_t)
+#define ECRAM_POWER_LED			0x1f
+#define ECRAM_BATTERY_DESIGN_CAPACITY	0x84
+#define ECRAM_BATTERY_DESIGN_VOLTAGE	0x86
 
 #endif
diff --git a/src/ec/starlabs/merlin/variants/kbl/ecdefs.h b/src/ec/starlabs/merlin/variants/kbl/ecdefs.h
index d5dd307eb3..b0f743f711 100644
--- a/src/ec/starlabs/merlin/variants/kbl/ecdefs.h
+++ b/src/ec/starlabs/merlin/variants/kbl/ecdefs.h
@@ -11,18 +11,20 @@
 #define _EC_STARLABS_KBL_EC_DEFS_H
 
 /* EC RAM offsets */
-#define ECRAM_MAJOR_VERSION	0x00
-#define ECRAM_MINOR_VERSION	0x01
-#define ECRAM_TRACKPAD_STATE	0x14
-#define ECRAM_KBL_STATE		0x18
-#define ECRAM_KBL_BRIGHTNESS	0x19
-#define ECRAM_KBL_TIMEOUT	0x1a
-#define ECRAM_FN_LOCK_STATE	0x2c
-#define ECRAM_FAN_MODE		0x42
-#define ECRAM_FN_CTRL_REVERSE	0x43
-#define ECRAM_MAX_CHARGE	dead_code_t(uint8_t)
-#define ECRAM_CHARGING_SPEED	dead_code_t(uint8_t)
-#define ECRAM_LID_SWITCH	dead_code_t(uint8_t)
-#define ECRAM_POWER_LED		0x1f
+#define ECRAM_MAJOR_VERSION		0x00
+#define ECRAM_MINOR_VERSION		0x01
+#define ECRAM_TRACKPAD_STATE		0x14
+#define ECRAM_KBL_STATE			0x18
+#define ECRAM_KBL_BRIGHTNESS		0x19
+#define ECRAM_KBL_TIMEOUT		0x1a
+#define ECRAM_FN_LOCK_STATE		0x2c
+#define ECRAM_FAN_MODE			0x42
+#define ECRAM_FN_CTRL_REVERSE		0x43
+#define ECRAM_MAX_CHARGE		dead_code_t(uint8_t)
+#define ECRAM_CHARGING_SPEED		dead_code_t(uint8_t)
+#define ECRAM_LID_SWITCH		dead_code_t(uint8_t)
+#define ECRAM_POWER_LED			0x1f
+#define ECRAM_BATTERY_DESIGN_CAPACITY	0x84
+#define ECRAM_BATTERY_DESIGN_VOLTAGE	0x86
 
 #endif
diff --git a/src/ec/starlabs/merlin/variants/merlin/ecdefs.h b/src/ec/starlabs/merlin/variants/merlin/ecdefs.h
index 75c2c62ce3..4fab635f3d 100644
--- a/src/ec/starlabs/merlin/variants/merlin/ecdefs.h
+++ b/src/ec/starlabs/merlin/variants/merlin/ecdefs.h
@@ -11,18 +11,20 @@
 #define _EC_STARLABS_MERLIN_EC_DEFS_H
 
 /* EC RAM offsets */
-#define ECRAM_MAJOR_VERSION	0x00
-#define ECRAM_MINOR_VERSION	0x01
-#define ECRAM_KBL_BRIGHTNESS	0x09
-#define ECRAM_KBL_TIMEOUT	0x10
-#define ECRAM_KBL_STATE		0x0a
-#define ECRAM_TRACKPAD_STATE	0x0c
-#define ECRAM_FN_LOCK_STATE	0x0f
-#define ECRAM_FN_CTRL_REVERSE	0x17
-#define ECRAM_MAX_CHARGE	0x1a
-#define ECRAM_FAN_MODE		0x1b
-#define ECRAM_CHARGING_SPEED	0x1d
-#define ECRAM_LID_SWITCH	0x1e
-#define ECRAM_POWER_LED		0x1f
+#define ECRAM_MAJOR_VERSION		0x00
+#define ECRAM_MINOR_VERSION		0x01
+#define ECRAM_KBL_BRIGHTNESS		0x09
+#define ECRAM_KBL_TIMEOUT		0x10
+#define ECRAM_KBL_STATE			0x0a
+#define ECRAM_TRACKPAD_STATE		0x0c
+#define ECRAM_FN_LOCK_STATE		0x0f
+#define ECRAM_FN_CTRL_REVERSE		0x17
+#define ECRAM_MAX_CHARGE		0x1a
+#define ECRAM_FAN_MODE			0x1b
+#define ECRAM_CHARGING_SPEED		0x1d
+#define ECRAM_LID_SWITCH		0x1e
+#define ECRAM_POWER_LED			0x1f
+#define ECRAM_BATTERY_DESIGN_CAPACITY	0x84
+#define ECRAM_BATTERY_DESIGN_VOLTAGE	0x86
 
 #endif

From 45163509cf63dc4f513c9ee91edf4f5b7a6b46a0 Mon Sep 17 00:00:00 2001
From: Maximilian Brune <maximilian.brune@9elements.com>
Date: Tue, 23 Jul 2024 12:37:05 +0200
Subject: [PATCH 2440/3886] util/cbfstool/cbfs-payload-linux.c: Remove TODO

LZMA checks at util/cbfstool/lzma/lzma.c:Write() for the output
buffer/stream size and does not write beyond it.

LZ4 checks at src/commonlib/bsd/lz4.c.inc:LZ4_decompress_generic() for
the buffer/stream size and does not write beyond it.

Change-Id: I41298b509b3f5e775bb4000c82c539eefa80c885
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83618
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
---
 util/cbfstool/cbfs-payload-linux.c | 5 -----
 1 file changed, 5 deletions(-)

diff --git a/util/cbfstool/cbfs-payload-linux.c b/util/cbfstool/cbfs-payload-linux.c
index 0eb841df82..33f154f326 100644
--- a/util/cbfstool/cbfs-payload-linux.c
+++ b/util/cbfstool/cbfs-payload-linux.c
@@ -187,11 +187,6 @@ static int bzp_output_segment(struct bzpayload *bzp, struct buffer *b,
  *   add support for more parameters to trampoline:
  *     alt_mem_k, ext_mem_k (not strictly necessary since e820 takes precedence)
  *     framebuffer/console values
- *
- *  larger work:
- *     is compress() safe to use in a size constrained buffer? ie. do(es) the
- *     compression algorithm(s) stop once the compression result reaches input
- *     size (ie. incompressible data)?
  */
 int parse_bzImage_to_payload(const struct buffer *input,
 			     struct buffer *output, const char *initrd_name,

From f8da2bf9b2927959a29bd8c98a5da91e234b3a1b Mon Sep 17 00:00:00 2001
From: Luca Lai <luca.lai@lcfc.corp-partner.google.com>
Date: Wed, 5 Nov 2025 09:59:26 +0800
Subject: [PATCH 2441/3886] mb/google/fatcat/var/ruby: Modify camera enable
 gpio pin.

Modify camera enable gpio pin from C05 to C06 to enable function.

schematics: RUBY_EVT_0902_2112.pdf

BUG=b:457650397
TEST=Build and boot to OS and check camera function works.

Change-Id: Id4ef314d039298e9cadd69e2faa53e6b9bcf6143
Signed-off-by: Luca Lai <luca.lai@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89912
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Pranava Y N <pranavayn@google.com>
Reviewed-by: Derek Huang <derekhuang@google.com>
---
 src/mainboard/google/fatcat/variants/ruby/overridetree.cb | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/mainboard/google/fatcat/variants/ruby/overridetree.cb b/src/mainboard/google/fatcat/variants/ruby/overridetree.cb
index 7abb6c6a8f..d9552f834b 100644
--- a/src/mainboard/google/fatcat/variants/ruby/overridetree.cb
+++ b/src/mainboard/google/fatcat/variants/ruby/overridetree.cb
@@ -181,7 +181,7 @@ chip soc/intel/pantherlake
 						register "desc" = ""USB2 Camera""
 						register "type" = "UPC_TYPE_INTERNAL"
 						register "has_power_resource" = "true"
-						register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C06)"
+						register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C05)"
 						device ref usb2_port3 on end
 					end
 					chip drivers/usb/acpi

From 8e2567c7a95f11f159c90aa118f0fff096fcf3d3 Mon Sep 17 00:00:00 2001
From: Hualin Wei <weihualin@huaqin.corp-partner.google.com>
Date: Tue, 4 Nov 2025 16:23:52 +0800
Subject: [PATCH 2442/3886] mb/google/fatcat/var/lapis: Adjust touchpad I2C
 frequency

Adjust the touchpad I2C frequency to greater than 380 kHz
and less than 400 kHz.

Before:
THC0-I2C - 368KHz

After:
THC0-T2C - 388KHz

BUG=b:456906446
TEST=Rate of the actual measured machine is pass.

Change-Id: I389a1b0f56494694f1d96aa036fd41dff476c074
Signed-off-by: Hualin Wei <weihualin@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89889
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com>
Reviewed-by: Pranava Y N <pranavayn@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
---
 src/mainboard/google/fatcat/variants/lapis/overridetree.cb | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/src/mainboard/google/fatcat/variants/lapis/overridetree.cb b/src/mainboard/google/fatcat/variants/lapis/overridetree.cb
index c686dd4da2..3c47b7f597 100644
--- a/src/mainboard/google/fatcat/variants/lapis/overridetree.cb
+++ b/src/mainboard/google/fatcat/variants/lapis/overridetree.cb
@@ -417,6 +417,8 @@ chip soc/intel/pantherlake
 				register "mode" = "THC_HID_I2C_MODE"
 				register "dev_hidi2c.intf.hidi2c.addr" = "0x15"
 				register "dev_hidi2c.intf.hidi2c.descriptor_address" = "0x01"
+				register "soc_hidi2c.fm_scl_low_period" = "160"
+				register "soc_hidi2c.fm_scl_high_period" = "146"
 				register "wake_on_touch" = "true"
 				# NOTE: Use GpioInt() in _CRS and does not use GPE.
 				register "wake_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW_WAKE(GPP_VGPIO3_THC0)"

From 7946d2d65dba34f9e7bcf76e18b6e2193994c889 Mon Sep 17 00:00:00 2001
From: Tongtong Pan <pantongtong@huaqin.corp-partner.google.com>
Date: Thu, 6 Nov 2025 10:31:40 +0800
Subject: [PATCH 2443/3886] mb/google/fatcat/var/felino: Add reset_gpio for SSD
 RTD3 configuration

To resolve the issue of probabilistic inability to enter s0ix, We need to
1.Add reset_gpio for SSD RTD3 configuration
2.Disable card reader in coreboot

Regarding adding reset_gpio for SSD RTD3 configuration
The PCIE SSD PERST part is added in the schematic diagram of the V4 version,
So GPP_F20 needs to be configured on felino, and keeps NC on felino4es.

BUG=b:431653999
TEST=dut can successfully enter S0IX during stress test.

Change-Id: I7dbb8b167fd7d519cd8c148ff7ead328c8c11d81
Signed-off-by: Tongtong Pan <pantongtong@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89927
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Pranava Y N <pranavayn@google.com>
---
 src/mainboard/google/fatcat/variants/felino/gpio.c         | 7 ++++++-
 .../google/fatcat/variants/felino/overridetree.cb          | 1 +
 2 files changed, 7 insertions(+), 1 deletion(-)

diff --git a/src/mainboard/google/fatcat/variants/felino/gpio.c b/src/mainboard/google/fatcat/variants/felino/gpio.c
index 3a82f97155..45e2ad4670 100644
--- a/src/mainboard/google/fatcat/variants/felino/gpio.c
+++ b/src/mainboard/google/fatcat/variants/felino/gpio.c
@@ -288,8 +288,13 @@ static const struct pad_config gpio_table[] = {
 	PAD_NC(GPP_F18, NONE),
 	/* GPP_F19:     GPP_F19 */
 	PAD_NC(GPP_F19, NONE),
-	/* GPP_F20:     NC */
+#if CONFIG(BOARD_GOOGLE_FELINO4ES)
+	/* GPP_F20:     Not used */
 	PAD_NC(GPP_F20, NONE),
+#else
+	/* GPP_F20:     SOC_SSD1_RST# */
+	PAD_CFG_GPO(GPP_F20, 1, PLTRST),
+#endif
 	/* GPP_F22:     NC */
 	PAD_NC(GPP_F22, NONE),
 	/* GPP_F23:     NC */
diff --git a/src/mainboard/google/fatcat/variants/felino/overridetree.cb b/src/mainboard/google/fatcat/variants/felino/overridetree.cb
index b4869ead78..0d2b9c2da8 100644
--- a/src/mainboard/google/fatcat/variants/felino/overridetree.cb
+++ b/src/mainboard/google/fatcat/variants/felino/overridetree.cb
@@ -252,6 +252,7 @@ device ref tbt_pcie_rp0 on end
 			chip soc/intel/common/block/pcie/rtd3
 				register "is_storage" = "true"
 				register "srcclk_pin" = "0"
+				register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_F20)"
 				device generic 0 on end
 			end
 		end # Gen5 SSD

From 0f7c54d7d121397bd8f01ffe0ba18d4e086217d6 Mon Sep 17 00:00:00 2001
From: Tongtong Pan <pantongtong@huaqin.corp-partner.google.com>
Date: Thu, 6 Nov 2025 11:54:11 +0800
Subject: [PATCH 2444/3886] mb/google/fatcat/var/felino: Disable card reader in
 coreboot

To resolve the issue of probabilistic inability to enter s0ix, We need to
1.Add reset_gpio for SSD RTD3 configuration
2.Disable card reader in coreboot

BUG=b:431653999
TEST=dut can successfully enter S0IX during stress test.

Change-Id: I7f8b117f23ca5639a17f2bace634ee84fce08247
Signed-off-by: Tongtong Pan <pantongtong@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89929
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Pranava Y N <pranavayn@google.com>
---
 src/mainboard/google/fatcat/variants/felino/gpio.c     |  2 +-
 .../google/fatcat/variants/felino/overridetree.cb      | 10 ----------
 2 files changed, 1 insertion(+), 11 deletions(-)

diff --git a/src/mainboard/google/fatcat/variants/felino/gpio.c b/src/mainboard/google/fatcat/variants/felino/gpio.c
index 45e2ad4670..b430004257 100644
--- a/src/mainboard/google/fatcat/variants/felino/gpio.c
+++ b/src/mainboard/google/fatcat/variants/felino/gpio.c
@@ -187,7 +187,7 @@ static const struct pad_config gpio_table[] = {
 	/* GPP_D17:     PCH_DMIC_DATA1 */
 	PAD_CFG_NF(GPP_D17, NONE, DEEP, NF3),
 	/* GPP_D18:     PCIE_CLKREQ_SD_N */
-	PAD_CFG_NF(GPP_D18, NONE, DEEP, NF1),
+	PAD_NC(GPP_D18, NONE),
 	/* GPP_D19:     NC */
 	PAD_NC(GPP_D19, NONE),
 	/* GPP_D20:     NC */
diff --git a/src/mainboard/google/fatcat/variants/felino/overridetree.cb b/src/mainboard/google/fatcat/variants/felino/overridetree.cb
index 0d2b9c2da8..0be19ae39c 100644
--- a/src/mainboard/google/fatcat/variants/felino/overridetree.cb
+++ b/src/mainboard/google/fatcat/variants/felino/overridetree.cb
@@ -204,16 +204,6 @@ device ref tbt_pcie_rp0 on end
 			end
 		end
 
-		device ref pcie_rp2 on
-			# Enable PCH PCIE x1 slot using CLK 6
-			register "pcie_rp[PCIE_RP(2)]" = "{
-				.clk_src = 6,
-				.clk_req = 6,
-				.flags = PCIE_RP_HOTPLUG | PCIE_RP_CLK_REQ_DETECT | PCIE_RP_LTR | PCIE_RP_AER,
-				.pcie_rp_aspm = ASPM_L1,
-			}"
-		end # SD Card
-
 		device ref pcie_rp4 on
 			probe WIFI WIFI_PCIE_6
 			probe WIFI WIFI_PCIE_7

From bb3e59051a77abe95c3cde719633998a3bc6aba3 Mon Sep 17 00:00:00 2001
From: Simon Yang <simon1.yang@intel.com>
Date: Fri, 31 Oct 2025 13:31:32 +0800
Subject: [PATCH 2445/3886] mb/google/brya: Check power state before process
 _ON method for BT

According to ACPI spec, OSPM will not check _STA first and may run the
_ON method repeatedly, even if the resource is already on.

GPIO CNV_BTEN, CNV_BT_IF_SELECT and BT_RESRT_GPIO are already enabled
before entering OS, but OS still try to run method _ON during boot up
process.

Therefore, try to check the GPIO state first to avoid unnecessary
operation and interfere touch enabling sequence.

BUG=b:454848201
TEST="rebuild and dump dsdt to check asl code generate as expected"

Change-Id: I8bd517c3a5ca46c7c8b8ad436af5e4be2295b631
Signed-off-by: Simon Yang <simon1.yang@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89849
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 .../google/brya/acpi/cnvi_bt_reset.asl        | 25 +++++++++++++------
 1 file changed, 17 insertions(+), 8 deletions(-)

diff --git a/src/mainboard/google/brya/acpi/cnvi_bt_reset.asl b/src/mainboard/google/brya/acpi/cnvi_bt_reset.asl
index e2a387aee1..6e84522145 100644
--- a/src/mainboard/google/brya/acpi/cnvi_bt_reset.asl
+++ b/src/mainboard/google/brya/acpi/cnvi_bt_reset.asl
@@ -8,11 +8,17 @@
 #define BT_RESET_GPIO	GPP_D4
 #endif
 
+/* Delay in milliseconds for BT_RESET */
+#ifndef BT_RESET_DELAY_MS
+#define BT_RESET_DELAY_MS	105
+#endif
+
 #define CNV_BTEN		GPP_VGPIO_0
 #define CNV_BT_IF_SELECT	GPP_VGPIO_5
 
 External (\_SB.PCI0.CTXS, MethodObj)
 External (\_SB.PCI0.STXS, MethodObj)
+External (\_SB.PCI0.GTXS, MethodObj)
 
 Scope (\_SB.PCI0.XHCI.RHUB.HS10)
 {
@@ -25,18 +31,21 @@ Scope (\_SB.PCI0.XHCI.RHUB.HS10)
 
 		Method (_ON, 0, NotSerialized)  // _ON_: Power On
 		{
-			\_SB.PCI0.STXS(CNV_BTEN);
-			\_SB.PCI0.STXS(CNV_BT_IF_SELECT);
-			\_SB.PCI0.STXS(BT_RESET_GPIO);
-			Sleep (105)
+			If (LEqual (\_SB.PCI0.GTXS(BT_RESET_GPIO), 0)) {
+				\_SB.PCI0.STXS(CNV_BTEN)
+				\_SB.PCI0.STXS(CNV_BT_IF_SELECT)
+				\_SB.PCI0.STXS(BT_RESET_GPIO)
+			}
 		}
 
 		Method (_OFF, 0, NotSerialized)  // _OFF: Power Off
 		{
-			\_SB.PCI0.CTXS(CNV_BTEN);
-			\_SB.PCI0.CTXS(CNV_BT_IF_SELECT);
-			\_SB.PCI0.CTXS(BT_RESET_GPIO);
-			Sleep (105)
+			If (LEqual (\_SB.PCI0.GTXS(BT_RESET_GPIO), 1)) {
+				\_SB.PCI0.CTXS(CNV_BTEN)
+				\_SB.PCI0.CTXS(CNV_BT_IF_SELECT)
+				\_SB.PCI0.CTXS(BT_RESET_GPIO)
+				Sleep (BT_RESET_DELAY_MS)
+			}
 		}
 
 	}

From b3b7b7a027517aaf238be4b6cc1ebf24c2ed3beb Mon Sep 17 00:00:00 2001
From: Maximilian Brune <maximilian.brune@9elements.com>
Date: Sat, 12 Apr 2025 15:36:13 +0200
Subject: [PATCH 2446/3886] mb/emulation/qemu-q35/Makefile.mk: Use all-y for
 memmap.c

Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: I14cd19c6c0f458a8d9a4034bb6faff0b42577f54
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87290
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Naresh <naresh.solanki.2011@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
---
 src/mainboard/emulation/qemu-q35/Makefile.mk | 5 +----
 1 file changed, 1 insertion(+), 4 deletions(-)

diff --git a/src/mainboard/emulation/qemu-q35/Makefile.mk b/src/mainboard/emulation/qemu-q35/Makefile.mk
index 2ad19b92d6..cba6b4ebc5 100644
--- a/src/mainboard/emulation/qemu-q35/Makefile.mk
+++ b/src/mainboard/emulation/qemu-q35/Makefile.mk
@@ -1,22 +1,19 @@
 ## SPDX-License-Identifier: GPL-2.0-only
 
 bootblock-y += bootblock.c
-bootblock-y += memmap.c
 
 romstage-y += ../qemu-i440fx/memmap.c
-romstage-y += memmap.c
 
 postcar-y += ../qemu-i440fx/memmap.c
 postcar-y += ../qemu-i440fx/exit_car.S
-postcar-y += memmap.c
 
 ramstage-y += ../qemu-i440fx/memmap.c
 ramstage-y += ../qemu-i440fx/northbridge.c
 ramstage-y += ../qemu-i440fx/rom_media.c
-ramstage-y += memmap.c
 ramstage-y += cpu.c
 
 all-y += ../qemu-i440fx/bootmode.c
+all-y += memmap.c
 
 ramstage-$(CONFIG_CHROMEOS) += chromeos.c
 

From b933a554ba7367382e7aecad9e70c0b4920886bb Mon Sep 17 00:00:00 2001
From: Hualin Wei <weihualin@huaqin.corp-partner.google.com>
Date: Fri, 7 Nov 2025 21:56:06 +0800
Subject: [PATCH 2447/3886] mb/google/var/fatcat/lapis: Modify fw_config for
 audio and touch

Add FW_CONFIG probe based on lapis boxster of below devices:
touchpad, audio and touchscreen.

BUG=b:456579786
TEST=Boot to OS and verify the touch and audio device are set
     based on fw_config

Change-Id: I6943a0cd6304a6d92481d2904bfa5082944ffd70
Signed-off-by: Hualin Wei <weihualin@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89939
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 .../fatcat/variants/lapis/overridetree.cb      | 18 ++++++++++++++----
 1 file changed, 14 insertions(+), 4 deletions(-)

diff --git a/src/mainboard/google/fatcat/variants/lapis/overridetree.cb b/src/mainboard/google/fatcat/variants/lapis/overridetree.cb
index 3c47b7f597..50eeb0d564 100644
--- a/src/mainboard/google/fatcat/variants/lapis/overridetree.cb
+++ b/src/mainboard/google/fatcat/variants/lapis/overridetree.cb
@@ -1,16 +1,20 @@
 fw_config
+	field AUDIO 0 1
+		option AUDIO_NONE		0
+		option CS42L43_SNDW		1
+	end
 	field WIFI 2 3
 		option WIFI_CNVI_7		0
 		option WIFI_CNVI_7E		1
 	end
 	field TOUCHSCREEN 4 5
 		option NONE_TOUCH	0
-		option 14_TOUCH		1
+		option THC_RAYDIMU	1
+		option THC_ILITEK	2
 	end
 	field TOUCHPAD 6 7
 		option TOUCHPAD_UNKNOWN		0
-		option TOUCHPAD_LPSS_I2C	1
-		option TOUCHPAD_THC_I2C		2
+		option TOUCHPAD_PCT4802		1
 	end
 	field STORAGE 8 9
 		option STORAGE_UNKNOWN		0
@@ -411,6 +415,7 @@ chip soc/intel/pantherlake
 		device ref thc0 on
 			register "thc_wake_on_touch[0]" = "true"
 			register "thc_mode[0]" = "THC_HID_I2C_MODE"
+			probe TOUCHPAD TOUCHPAD_PCT4802
 			# THC0 is function 0; hence it needs to be enabled when THC1 is to be enabled.
 			chip drivers/intel/touch
 				register "name" = "INTEL_THC0_NAME"
@@ -432,6 +437,8 @@ chip soc/intel/pantherlake
 		device ref thc1 on
 			register "thc_wake_on_touch[1]" = "true"
 			register "thc_mode[1]" = "THC_HID_I2C_MODE"
+			probe TOUCHSCREEN THC_RAYDIMU
+			probe TOUCHSCREEN THC_ILITEK
 			chip drivers/intel/touch
 				register "name" = "INTEL_THC1_NAME"
 				register "mode" = "THC_HID_I2C_MODE"
@@ -447,11 +454,14 @@ chip soc/intel/pantherlake
 				register "idle_ltr" = "0"
 				register "connected_device" = "TH_SENSOR_GENERIC"
 				register "add_acpi_dma_property" = "true"
-				device generic 0 on end
+				device generic 0 on
+					probe TOUCHSCREEN THC_RAYDIMU
+				end
 			end
 		end #Touchpenal
 
 		device ref hda on
+			probe AUDIO CS42L43_SNDW
 			chip drivers/intel/soundwire
 				device generic 0 on
 					chip drivers/soundwire/cs42l43

From 9210f2fd1c0a3dc76eba08f1ee28984b8dfa5b8d Mon Sep 17 00:00:00 2001
From: Hualin Wei <weihualin@huaqin.corp-partner.google.com>
Date: Mon, 20 Oct 2025 16:22:37 +0800
Subject: [PATCH 2448/3886] mb/google/fatcat/var/lapis: add ILITEK touchscreen
 support

This chang adds the necessary configuration for ILITEK touchscreen
(ILIT2901) device. The relevant parameters are from the manufacturer's
email dated October 13th. Furthermore, adding fw_config THC_ILITEK
ensures that the touch functionality of both touchscreens is normal.

BUG=b:455442712
TEST=emerge-fatcat coreboot and chromeos-bootimage,
flash to DUT, ilitek touchscreen can be found by `getevent`,
and no wake-up functionality when the DUT is in sleep mode.

Change-Id: I7611c7b1e1364e48ae87a0d91ad3106130ccc586
Signed-off-by: Hualin Wei <weihualin@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89756
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
---
 .../fatcat/variants/lapis/overridetree.cb     | 19 +++++++++++++++++++
 1 file changed, 19 insertions(+)

diff --git a/src/mainboard/google/fatcat/variants/lapis/overridetree.cb b/src/mainboard/google/fatcat/variants/lapis/overridetree.cb
index 50eeb0d564..c772f46ac1 100644
--- a/src/mainboard/google/fatcat/variants/lapis/overridetree.cb
+++ b/src/mainboard/google/fatcat/variants/lapis/overridetree.cb
@@ -458,6 +458,25 @@ chip soc/intel/pantherlake
 					probe TOUCHSCREEN THC_RAYDIMU
 				end
 			end
+			chip drivers/intel/touch
+				register "name" = "INTEL_THC1_NAME"
+				register "mode" = "THC_HID_I2C_MODE"
+				register "dev_hidi2c.hid" = ""ILIT2901""
+				register "dev_hidi2c.cid" = ""PNP0C50""
+				register "dev_hidi2c.intf.hidi2c.addr" = "0x41"
+				register "dev_hidi2c.intf.hidi2c.descriptor_address" = "0x0001"
+				register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_F08)"
+				register "wake_on_touch" = "true"
+				# NOTE: Use GpioInt() in _CRS and does not use GPE.
+				register "wake_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW_WAKE(GPP_VGPIO3_THC1)"
+				register "active_ltr" = "1"
+				register "idle_ltr" = "0"
+				register "connected_device" = "TH_SENSOR_GENERIC"
+				register "add_acpi_dma_property" = "true"
+				device generic 0 on
+					probe TOUCHSCREEN THC_ILITEK
+				end
+			end
 		end #Touchpenal
 
 		device ref hda on

From 84e000b88e7fe8bec57201766fab496cbdb9ac24 Mon Sep 17 00:00:00 2001
From: Julius Werner <jwerner@chromium.org>
Date: Wed, 5 Nov 2025 16:53:30 -0800
Subject: [PATCH 2449/3886] libpayload: arm64: Fix alignment for
 exception_state

In the arm64 exception handler in libpayload, we use the banked
exception stack pointer (SP_EL2, as opposed to the normal SP_EL0) not as
a normal stack pointer, but simply as a pointer to the exception_state
struct. This makes it easy to dump all registers into that struct on
context switch. We then immediately switch back to SP_EL0.

Yet, even though it is not really a stack for us, the aarch64
architecture still requires that SP_EL2 is 16 byte aligned at function
boundaries. If the exception_state struct is not thus aligned,
exceptions are broken. (I don't know why nobody ever hit this before,
but I hit it now while trying to pull in zstd code. I guess we just
don't have unaligned BSS entries that often and simply got lucky for a
while. 3 hours wasted on debugging. :( )

Change-Id: Id19184656fb9da68fe4bfdbc240c0c25b9d24cd6
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89926
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
---
 payloads/libpayload/arch/arm64/exception.c | 7 +++++--
 payloads/libpayload/arch/arm64/gdb.c       | 2 +-
 2 files changed, 6 insertions(+), 3 deletions(-)

diff --git a/payloads/libpayload/arch/arm64/exception.c b/payloads/libpayload/arch/arm64/exception.c
index 21ed1c2661..3a9157f4f4 100644
--- a/payloads/libpayload/arch/arm64/exception.c
+++ b/payloads/libpayload/arch/arm64/exception.c
@@ -30,7 +30,7 @@
 #include <libpayload.h>
 #include <stdint.h>
 
-u64 exception_stack[2*KiB] __attribute__((aligned(16)));
+u64 exception_stack[2*KiB] __aligned(16);
 u64 *exception_stack_end = exception_stack + ARRAY_SIZE(exception_stack);
 
 struct exception_handler_info
@@ -39,7 +39,10 @@ struct exception_handler_info
 };
 
 static exception_hook hook;
-struct exception_state exception_state;
+
+/* To make the exception entry easier, we write this into SP_EL2. AArch64 demands
+   that stack pointers are always 16-byte aligned at function boundaries. */
+struct exception_state exception_state __aligned(16);
 
 static struct exception_handler_info exceptions[EXC_COUNT] = {
 	[EXC_SYNC_SP0] = { "_sync_sp_el0" },
diff --git a/payloads/libpayload/arch/arm64/gdb.c b/payloads/libpayload/arch/arm64/gdb.c
index 10ae675fe4..230f2a9e45 100644
--- a/payloads/libpayload/arch/arm64/gdb.c
+++ b/payloads/libpayload/arch/arm64/gdb.c
@@ -32,7 +32,7 @@ struct gdb_regs
 } __packed;
 
 /* Scratch value to write reentrant exception states to. We never read it. */
-static struct exception_state sentinel_exception_state;
+static struct exception_state sentinel_exception_state __aligned(16);
 
 static int gdb_exception_hook(u32 type)
 {

From ea84a29a2755c8ef733039cec5657d52f407dede Mon Sep 17 00:00:00 2001
From: Luca Lai <luca.lai@lcfc.corp-partner.google.com>
Date: Tue, 4 Nov 2025 20:22:58 +0800
Subject: [PATCH 2450/3886] mb/google/trulo/var/pujjoquince: Enable Bayhub LV2
 driver

Some SKUs of pujjoquince have a Bayhub LV2 card reader chip,
therefore enable the corresponding driver for the mainboard.

BUG=b:454252968
TEST=Build FW and checking SD card reader register is correct like
printk(BIOS_INFO, "Luca_0x%x: %x\n", ltr_cap + PCI_LTR_MAX_NOSNOOP,
pci_read_config16(dev, 0x236));.

Change-Id: Ib04a419b86213b6ffef25d7f6f64668abaf36801
Signed-off-by: Luca Lai <luca.lai@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89890
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
---
 src/mainboard/google/brya/Kconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/src/mainboard/google/brya/Kconfig b/src/mainboard/google/brya/Kconfig
index a60dd5386a..437632bfe6 100644
--- a/src/mainboard/google/brya/Kconfig
+++ b/src/mainboard/google/brya/Kconfig
@@ -511,6 +511,7 @@ config BOARD_GOOGLE_PUJJOLO
 	select DRIVERS_GENERIC_GPIO_KEYS
 	select DRIVERS_INTEL_MIPI_CAMERA
 	select DRIVERS_I2C_SX9324
+	select DRIVERS_GENERIC_BAYHUB_LV2
 	select DRIVERS_GFX_GENERIC
 	select DRIVERS_I2C_SX9324_SUPPORT_LEGACY_LINUX_DRIVER
 	select ENFORCE_MEM_CHANNEL_DISABLE

From 786ac14d48be280fea1a2cad18fdbf6781dcca94 Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Thu, 6 Nov 2025 14:41:05 -0600
Subject: [PATCH 2451/3886] drivers/option/cfr: Add optional override table for
 default values

Add a mechanism for mainboards to override default values of CFR
objects defined in SoC or common code without duplicating object
metadata.

Mainboards can now declare a simple override table mapping option
names to new default values:

  const struct cfr_default_override mb_cfr_overrides[] = {
      CFR_OVERRIDE_BOOL("s0ix_enable", false),
      CFR_OVERRIDE_ENUM("pciexp_aspm", ASPM_DISABLE),
      CFR_OVERRIDE_END
  };

The CFR backend checks this table when writing options and uses the
override value if one exists. All other metadata (name, help text,
enum values, flags) comes from the original object.

Change-Id: Ifb3da90d605f2799bf0207ff58d69bee3415ccc2
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89933
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 Documentation/drivers/cfr_internal.md | 46 ++++++++++++++++++++++++++-
 src/drivers/option/cfr.c              | 44 ++++++++++++++++++++++++-
 src/drivers/option/cfr_frontend.h     | 46 +++++++++++++++++++++++++++
 3 files changed, 134 insertions(+), 2 deletions(-)

diff --git a/Documentation/drivers/cfr_internal.md b/Documentation/drivers/cfr_internal.md
index b2355d7b62..6aa896ed68 100644
--- a/Documentation/drivers/cfr_internal.md
+++ b/Documentation/drivers/cfr_internal.md
@@ -23,6 +23,50 @@ In both cases you have to add `C` structs in ramstage to describe the
 option and group them together into a form. CFR objects should reside
 on the heap as they can be modified to match the current boot flow.
 
+### Overriding default values
+
+Mainboards often want to reuse CFR objects defined in SoC or common code
+but with different default values. Rather than duplicating the entire object
+definition, mainboards can declare an override table that maps option names
+to new default values.
+
+**Example:** Override defaults for several SoC-defined options:
+
+```
+#include <drivers/option/cfr_frontend.h>
+#include <intelblocks/pcie_rp.h>
+
+const struct cfr_default_override mb_cfr_overrides[] = {
+	CFR_OVERRIDE_BOOL("s0ix_enable", false),
+	CFR_OVERRIDE_ENUM("pciexp_aspm", ASPM_DISABLE),
+	CFR_OVERRIDE_NUMBER("igd_dvmt", 64),
+	CFR_OVERRIDE_END
+};
+
+void mb_cfr_setup_menu(struct lb_cfr *cfr_root)
+{
+	/* Register overrides before writing menu */
+	cfr_register_overrides(mb_cfr_overrides);
+	cfr_write_setup_menu(cfr_root, sm_root);
+}
+```
+
+When the CFR system writes the setup menu, it will check the override table
+for each option and use the override value if one exists. All other object
+metadata (name, help text, enum values, flags) comes from the original object.
+
+The following helper macros are available to populate the table:
+
+- `CFR_OVERRIDE_BOOL(name, value)`
+- `CFR_OVERRIDE_ENUM(name, value)`
+- `CFR_OVERRIDE_NUMBER(name, value)`
+- `CFR_OVERRIDE_VARCHAR(name, value)`
+- `CFR_OVERRIDE_END`
+
+Each macro encodes the override type, and the CFR backend validates that the
+override type matches the original object's type. If the types do not match,
+the override is ignored and a warning is printed.
+
 ### Updating CFR options
 
 The CFR options should be updated before tables are written.
@@ -143,4 +187,4 @@ static const  __cfr_form struct sm_obj_form southbridge = {
 		NULL
 	},
 };
-```
\ No newline at end of file
+```
diff --git a/src/drivers/option/cfr.c b/src/drivers/option/cfr.c
index 26bdd55f4d..a332d906d6 100644
--- a/src/drivers/option/cfr.c
+++ b/src/drivers/option/cfr.c
@@ -10,6 +10,27 @@
 #include <string.h>
 #include <types.h>
 
+/* Global override table registered by mainboard */
+static const struct cfr_default_override *mb_overrides = NULL;
+
+void cfr_register_overrides(const struct cfr_default_override *overrides)
+{
+	mb_overrides = overrides;
+}
+
+/* Look up override for a given option name */
+static const struct cfr_default_override *find_override(const char *opt_name)
+{
+	if (!mb_overrides || !opt_name)
+		return NULL;
+
+	for (const struct cfr_default_override *ovr = mb_overrides; ovr->opt_name; ovr++) {
+		if (strcmp(ovr->opt_name, opt_name) == 0)
+			return ovr;
+	}
+	return NULL;
+}
+
 static uint32_t cfr_record_size(const char *startp, const char *endp)
 {
 	const uintptr_t start = (uintptr_t)startp;
@@ -111,6 +132,17 @@ static uint32_t write_numeric_option(char *current, uint32_t tag, const uint64_t
 	struct lb_cfr_numeric_option *option = (struct lb_cfr_numeric_option *)current;
 	size_t len;
 
+	/* Check for mainboard override of default value */
+	const struct cfr_default_override *ovr = find_override(opt_name);
+	if (ovr) {
+		if (ovr->kind != tag)
+			printk(BIOS_WARNING, "CFR: override for option '%s' has mismatched type; skipping.\n", opt_name);
+		else if (tag == CFR_TAG_OPTION_BOOL)
+			default_value = ovr->bool_value;
+		else
+			default_value = ovr->uint_value;
+	}
+
 	option->tag = tag;
 	option->object_id = object_id;
 	option->dependency_id = dep_id;
@@ -187,6 +219,16 @@ static uint32_t sm_write_opt_varchar(char *current, const struct sm_obj_varchar
 {
 	struct lb_cfr_varchar_option *option = (struct lb_cfr_varchar_option *)current;
 	size_t len;
+	const char *default_value = sm_varchar->default_value;
+
+	/* Check for mainboard override of default value */
+	const struct cfr_default_override *ovr = find_override(sm_varchar->opt_name);
+	if (ovr) {
+		if (ovr->kind == SM_OBJ_VARCHAR)
+			default_value = ovr->str_value;
+		else
+			printk(BIOS_WARNING, "CFR: override for option '%s' has mismatched type (not varchar); skipping.\n", sm_varchar->opt_name);
+	}
 
 	option->tag = CFR_TAG_OPTION_VARCHAR;
 	option->object_id = object_id;
@@ -197,7 +239,7 @@ static uint32_t sm_write_opt_varchar(char *current, const struct sm_obj_varchar
 	option->size = sizeof(*option);
 
 	current += option->size;
-	current += sm_write_string_default_value(current, sm_varchar->default_value);
+	current += sm_write_string_default_value(current, default_value);
 	len = sm_write_opt_name(current, sm_varchar->opt_name);
 	if (!len)
 		return 0;
diff --git a/src/drivers/option/cfr_frontend.h b/src/drivers/option/cfr_frontend.h
index 17332bdca4..3beaaa7690 100644
--- a/src/drivers/option/cfr_frontend.h
+++ b/src/drivers/option/cfr_frontend.h
@@ -5,6 +5,7 @@
 
 #include <commonlib/coreboot_tables.h>
 #include <commonlib/cfr.h>
+#include <string.h>
 #include <types.h>
 
 /* Front-end */
@@ -119,6 +120,51 @@ struct sm_object {
 	.dep_values = ((const uint32_t[]) { __VA_ARGS__ }),			\
 	.num_dep_values = sizeof((uint32_t[]) { __VA_ARGS__ }) / sizeof(uint32_t)
 
+/*
+ * CFR Default Value Override System
+ *
+ * Mainboards can override default values of CFR objects defined in SoC/common
+ * code by declaring an override table. This avoids duplicating object metadata.
+ *
+ * Usage:
+ *   1. Declare overrides in mainboard cfr.c:
+ *
+ *      const struct cfr_default_override mb_cfr_overrides[] = {
+ *          CFR_OVERRIDE_BOOL("s0ix_enable", false),
+ *          CFR_OVERRIDE_ENUM("pciexp_aspm", ASPM_DISABLE),
+ *          CFR_OVERRIDE_END
+ *      };
+ *
+ *   2. Register the table in mb_cfr_setup_menu():
+ *
+ *      void mb_cfr_setup_menu(struct lb_cfr *cfr_root)
+ *      {
+ *          cfr_register_overrides(mb_cfr_overrides);
+ *          cfr_write_setup_menu(cfr_root, sm_root);
+ *      }
+ */
+
+/* Override table entry */
+struct cfr_default_override {
+	const char *opt_name;
+	enum sm_object_kind kind;
+	union {
+		bool bool_value;
+		uint32_t uint_value;
+		const char *str_value;
+	};
+};
+
+/* Helper macros for override table entries */
+#define CFR_OVERRIDE_BOOL(name, val)	{ .opt_name = (name), .kind = SM_OBJ_BOOL, .bool_value = (val) }
+#define CFR_OVERRIDE_ENUM(name, val)	{ .opt_name = (name), .kind = SM_OBJ_ENUM, .uint_value = (val) }
+#define CFR_OVERRIDE_NUMBER(name, val)	{ .opt_name = (name), .kind = SM_OBJ_NUMBER, .uint_value = (val) }
+#define CFR_OVERRIDE_VARCHAR(name, val)	{ .opt_name = (name), .kind = SM_OBJ_VARCHAR, .str_value = (val) }
+#define CFR_OVERRIDE_END			{ .opt_name = NULL }
+
+/* Register mainboard override table (call before cfr_write_setup_menu) */
+void cfr_register_overrides(const struct cfr_default_override *overrides);
+
 void cfr_write_setup_menu(struct lb_cfr *cfr_root, struct sm_obj_form *sm_root[]);
 
 #if ENV_RAMSTAGE

From 312d455a93ca6918c9127eb8e64c2e1d953d0e3a Mon Sep 17 00:00:00 2001
From: Angel Pons <th3fanbus@gmail.com>
Date: Tue, 28 Oct 2025 12:59:39 +0100
Subject: [PATCH 2452/3886] soc/intel/{adl,mtl}/romstage/fsp_params.c: Fix
 printf specifier

`cfg[i].clk_req` is a `uint8_t` so use `%u` instead of `%d`.

Change-Id: I6c7a6ecbd2f5b917d44923d0ad6cb331d9bb054c
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89789
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kilian Krause <kilian.krause@siemens.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
---
 src/soc/intel/alderlake/romstage/fsp_params.c  | 2 +-
 src/soc/intel/meteorlake/romstage/fsp_params.c | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/soc/intel/alderlake/romstage/fsp_params.c b/src/soc/intel/alderlake/romstage/fsp_params.c
index 6ab8bb3e50..30ec714b50 100644
--- a/src/soc/intel/alderlake/romstage/fsp_params.c
+++ b/src/soc/intel/alderlake/romstage/fsp_params.c
@@ -79,7 +79,7 @@ static void pcie_rp_init(FSP_M_CONFIG *m_cfg, uint32_t en_mask, enum pcie_rp_typ
 		if (!(cfg[i].flags & PCIE_RP_CLK_REQ_UNUSED)) {
 			if (clk_req_mapping & (1 << cfg[i].clk_req))
 				printk(BIOS_WARNING,
-				       "Found overlapped clkreq assignment on clk req %d\n",
+				       "Found overlapped clkreq assignment on clk req %u\n",
 				       cfg[i].clk_req);
 			m_cfg->PcieClkSrcClkReq[cfg[i].clk_src] = cfg[i].clk_req;
 			clk_req_mapping |= 1 << cfg[i].clk_req;
diff --git a/src/soc/intel/meteorlake/romstage/fsp_params.c b/src/soc/intel/meteorlake/romstage/fsp_params.c
index 414c270dcd..0543106442 100644
--- a/src/soc/intel/meteorlake/romstage/fsp_params.c
+++ b/src/soc/intel/meteorlake/romstage/fsp_params.c
@@ -59,7 +59,7 @@ static void pcie_rp_init(FSP_M_CONFIG *m_cfg, uint32_t en_mask,
 		if (!(cfg[i].flags & PCIE_RP_CLK_REQ_UNUSED)) {
 			if (clk_req_mapping & (1 << cfg[i].clk_req))
 				printk(BIOS_WARNING,
-				       "Found overlapped clkreq assignment on clk req %d\n",
+				       "Found overlapped clkreq assignment on clk req %u\n",
 				       cfg[i].clk_req);
 			m_cfg->PcieClkSrcClkReq[cfg[i].clk_src] = cfg[i].clk_req;
 			clk_req_mapping |= 1 << cfg[i].clk_req;

From c917ecf21e7d9885f46849c4fb164cc561307996 Mon Sep 17 00:00:00 2001
From: Angel Pons <th3fanbus@gmail.com>
Date: Tue, 28 Oct 2025 12:49:19 +0100
Subject: [PATCH 2453/3886] soc/intel/{adl,mtl}: Fix CLKSRC handling for
 compliance mode

The code was indexing an array of clock sources using an RP index which
is not correct. As the intent of compliance mode seems to be to set all
clock sources to be free-running, do the same from a different place in
order to avoid potential out-of-bounds accesses.

To preserve original behaviour, exit early from `pcie_rp_init()`. While
this is rather crude, subsequent commits will refactor said function.

Change-Id: I89e6e9f85b7b86b0a74ece88641a378f2c0b599f
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89788
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kilian Krause <kilian.krause@siemens.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
---
 src/soc/intel/alderlake/romstage/fsp_params.c  | 12 +++++++-----
 src/soc/intel/meteorlake/romstage/fsp_params.c | 12 +++++++-----
 2 files changed, 14 insertions(+), 10 deletions(-)

diff --git a/src/soc/intel/alderlake/romstage/fsp_params.c b/src/soc/intel/alderlake/romstage/fsp_params.c
index 30ec714b50..5be064e4dd 100644
--- a/src/soc/intel/alderlake/romstage/fsp_params.c
+++ b/src/soc/intel/alderlake/romstage/fsp_params.c
@@ -62,11 +62,11 @@ static void pcie_rp_init(FSP_M_CONFIG *m_cfg, uint32_t en_mask, enum pcie_rp_typ
 	/* bitmask to save the status of clkreq assignment */
 	static unsigned int clk_req_mapping = 0;
 
+	/* Will be refactored to only skip configuring CLKSRC and CLKREQ */
+	if (CONFIG(SOC_INTEL_COMPLIANCE_TEST_MODE))
+		return;
+
 	for (i = 0; i < cfg_count; i++) {
-		if (CONFIG(SOC_INTEL_COMPLIANCE_TEST_MODE)) {
-			m_cfg->PcieClkSrcUsage[i] = FSP_CLK_FREE_RUNNING;
-			continue;
-		}
 		if (!(en_mask & BIT(i)))
 			continue;
 		if (cfg[i].flags & PCIE_RP_CLK_SRC_UNUSED)
@@ -95,7 +95,9 @@ static void fill_fspm_pcie_rp_params(FSP_M_CONFIG *m_cfg,
 	unsigned int i;
 
 	for (i = 0; i < CONFIG_MAX_PCIE_CLOCK_SRC; i++) {
-		if (config->pcie_clk_config_flag[i] & PCIE_CLK_FREE_RUNNING)
+		if (CONFIG(SOC_INTEL_COMPLIANCE_TEST_MODE))
+			m_cfg->PcieClkSrcUsage[i] = FSP_CLK_FREE_RUNNING;
+		else if (config->pcie_clk_config_flag[i] & PCIE_CLK_FREE_RUNNING)
 			m_cfg->PcieClkSrcUsage[i] = FSP_CLK_FREE_RUNNING;
 		else if (config->pcie_clk_config_flag[i] & PCIE_CLK_LAN)
 			m_cfg->PcieClkSrcUsage[i] = FSP_CLK_LAN;
diff --git a/src/soc/intel/meteorlake/romstage/fsp_params.c b/src/soc/intel/meteorlake/romstage/fsp_params.c
index 0543106442..49e3b09ea2 100644
--- a/src/soc/intel/meteorlake/romstage/fsp_params.c
+++ b/src/soc/intel/meteorlake/romstage/fsp_params.c
@@ -42,11 +42,11 @@ static void pcie_rp_init(FSP_M_CONFIG *m_cfg, uint32_t en_mask,
 	size_t i;
 	static unsigned int clk_req_mapping = 0;
 
+	/* Will be refactored to only skip configuring CLKSRC and CLKREQ */
+	if (CONFIG(SOC_INTEL_COMPLIANCE_TEST_MODE))
+		return;
+
 	for (i = 0; i < cfg_count; i++) {
-		if (CONFIG(SOC_INTEL_COMPLIANCE_TEST_MODE)) {
-			m_cfg->PcieClkSrcUsage[i] = FSP_CLK_FREE_RUNNING;
-			continue;
-		}
 		if (!(en_mask & BIT(i)))
 			continue;
 		if (cfg[i].flags & PCIE_RP_CLK_SRC_UNUSED)
@@ -76,7 +76,9 @@ static void fill_fspm_pcie_rp_params(FSP_M_CONFIG *m_cfg,
 	uint8_t max_clock = get_max_pcie_clock();
 
 	for (i = 0; i < max_clock; i++) {
-		if (config->pcie_clk_config_flag[i] & PCIE_CLK_FREE_RUNNING)
+		if (CONFIG(SOC_INTEL_COMPLIANCE_TEST_MODE))
+			m_cfg->PcieClkSrcUsage[i] = FSP_CLK_FREE_RUNNING;
+		else if (config->pcie_clk_config_flag[i] & PCIE_CLK_FREE_RUNNING)
 			m_cfg->PcieClkSrcUsage[i] = FSP_CLK_FREE_RUNNING;
 		else if (config->pcie_clk_config_flag[i] & PCIE_CLK_LAN)
 			m_cfg->PcieClkSrcUsage[i] = FSP_CLK_LAN;

From 8851b5b0e72eb9823544a664b74205da31b60598 Mon Sep 17 00:00:00 2001
From: Simon Yang <simon1.yang@intel.com>
Date: Mon, 10 Nov 2025 19:36:07 +0800
Subject: [PATCH 2454/3886] soc/intel/pantherlake: Program HDA SVID/SSID

Retrieve SVID/SSID via devicetree and program to HDA device

BUG=b/458444964, b/454824561
TEST="lspci -s 00:1f.3 -x and check value in offset 0x2c-0x2f"

Change-Id: I6bf4b5f2cbce69429daabce83ab11c13272194f4
Signed-off-by: Simon Yang <simon1.yang@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89983
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Derek Huang <derekhuang@google.com>
---
 src/soc/intel/pantherlake/romstage/fsp_params.c | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/src/soc/intel/pantherlake/romstage/fsp_params.c b/src/soc/intel/pantherlake/romstage/fsp_params.c
index 04cd86d7a1..69f3ed4d9b 100644
--- a/src/soc/intel/pantherlake/romstage/fsp_params.c
+++ b/src/soc/intel/pantherlake/romstage/fsp_params.c
@@ -196,6 +196,15 @@ static void fill_fspm_audio_params(FSP_M_CONFIG *m_cfg,
 	memset(m_cfg->PchHdaAudioLinkDmicEnable, 0, sizeof(m_cfg->PchHdaAudioLinkDmicEnable));
 	memset(m_cfg->PchHdaAudioLinkSspEnable, 0, sizeof(m_cfg->PchHdaAudioLinkSspEnable));
 	memset(m_cfg->PchHdaAudioLinkSndwEnable, 0, sizeof(m_cfg->PchHdaAudioLinkSndwEnable));
+
+	/*
+	 * Get HDA Subsystem Vendor ID and Device ID from devicetree
+	 * and set it in FSPM UPD.
+	 */
+	const struct device_path path = { .type = DEVICE_PATH_PCI, .pci.devfn = PCI_DEVFN_HDA };
+	const struct device *dev = find_dev_path(pci_root_bus(), &path);
+	if (is_dev_enabled(dev) && dev->subsystem_vendor && dev->subsystem_device)
+		m_cfg->PchHdaSubSystemIds = dev->subsystem_vendor | (dev->subsystem_device << 16);
 }
 
 static void pcie_rp_init(FSP_M_CONFIG *m_cfg, uint32_t en_mask,

From d0c936eea17b257126379d13637d28cb644ffb53 Mon Sep 17 00:00:00 2001
From: Joyce Ciou <Joyce_Ciou@pegatron.corp-partner.google.com>
Date: Thu, 6 Nov 2025 11:18:01 +0800
Subject: [PATCH 2455/3886] mb/google/nissa/var/guren: Tune SX9324 register for
 5G LTE module

Update SX9324 register settings based on tuning values from SEMTECH to
adjust the proximity sensor sensing range to support 5G LTE module.

BUG=b:445338278
TEST=Confirm P sensor function can work and check i2c register settings
     on Guren by command # i2cwatch -f -y 14 0x28

Signed-off-by: Joyce Ciou <joyce_ciou@pegatron.corp-partner.google.com>
Change-Id: Ic5e8fe1c67dcdfcfc9a4657b9d859a3b71239858
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89930
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Derek Huang <derekhuang@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
---
 .../brya/variants/guren/overridetree.cb       | 68 +++++++++++++++++++
 1 file changed, 68 insertions(+)

diff --git a/src/mainboard/google/brya/variants/guren/overridetree.cb b/src/mainboard/google/brya/variants/guren/overridetree.cb
index f74a20e562..6c7ecd83e7 100644
--- a/src/mainboard/google/brya/variants/guren/overridetree.cb
+++ b/src/mainboard/google/brya/variants/guren/overridetree.cb
@@ -480,6 +480,74 @@ chip soc/intel/alderlake
 				device i2c 28 on
 					probe DB_USB DB_1C_LTE
 					probe DB_USB DB_HDMI_LTE
+				end
+			end
+			chip drivers/i2c/sx9324
+				register "desc" = ""SAR Proximity Sensor""
+				register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_H19_IRQ)"
+				register "speed" = "I2C_SPEED_FAST"
+				register "uid" = "1"
+				register "reg_gnrl_ctrl0" = "0x0A"
+				register "reg_afe_ctrl0" = "0x20"
+				register "reg_afe_ctrl3" = "0x00"
+				register "reg_afe_ctrl4" = "0x45"
+				register "reg_afe_ctrl6" = "0x00"
+				register "reg_afe_ctrl7" = "0x47"
+				register "reg_afe_ph0" = "0x3D"
+				register "reg_afe_ph1" = "0x1B"
+				register "reg_afe_ph2" = "0x1F"
+				register "reg_afe_ph3" = "0x3d"
+				register "reg_afe_ctrl8" = "0x12"
+				register "reg_afe_ctrl9" = "0x08"
+				register "reg_prox_ctrl0" = "0x0B"
+				register "reg_prox_ctrl1" = "0x0B"
+				register "reg_prox_ctrl2" = "0x20"
+				register "reg_prox_ctrl3" = "0x20"
+				register "reg_prox_ctrl4" = "0x0C"
+				register "reg_prox_ctrl5" = "0x00"
+				register "reg_prox_ctrl6" = "0x2d"
+				register "reg_prox_ctrl7" = "0x00"
+				register "reg_adv_ctrl0" = "0x00"
+				register "reg_adv_ctrl1" = "0x00"
+				register "reg_adv_ctrl2" = "0x00"
+				register "reg_adv_ctrl3" = "0x00"
+				register "reg_adv_ctrl4" = "0x00"
+				register "reg_adv_ctrl5" = "0x05"
+				register "reg_adv_ctrl6" = "0x00"
+				register "reg_adv_ctrl7" = "0x00"
+				register "reg_adv_ctrl8" = "0x00"
+				register "reg_adv_ctrl9" = "0x00"
+				register "reg_adv_ctrl10" = "0x00"
+				register "reg_adv_ctrl11" = "0x00"
+				register "reg_adv_ctrl12" = "0x00"
+				register "reg_adv_ctrl13" = "0x00"
+				register "reg_adv_ctrl14" = "0x80"
+				register "reg_adv_ctrl15" = "0x0C"
+				register "reg_adv_ctrl16" = "0x04"
+				register "reg_adv_ctrl17" = "0x70"
+				register "reg_adv_ctrl18" = "0x20"
+				register "reg_adv_ctrl19" = "0x00"
+				register "reg_adv_ctrl20" = "0x00"
+				register "reg_irq_msk" = "0x67"
+				register "reg_irq_cfg0" = "0x00"
+				register "reg_irq_cfg1" = "0x80"
+				register "reg_irq_cfg2" = "0x00"
+				register "reg_gnrl_ctrl1" = "0x21"
+
+				register "ph01_resolution" = "256"
+				register "ph23_resolution" = "1024"
+				register "ph0_pin" = "{1, 3, 3}"
+				register "ph1_pin" = "{3, 2, 1}"
+				register "ph2_pin" = "{3, 3, 1}"
+				register "ph3_pin" = "{1, 3, 3}"
+				register "input_precharge_resistor_ohms" = "4000"
+				register "input_analog_gain" = "1"
+				register "ph01_proxraw_strength" = "3"
+				register "ph23_proxraw_strength" = "3"
+				register "avg_pos_strength" = "256"
+				register "startup_sensor" = "1"
+				register "cs_idle_sleep" = ""gnd""
+				device i2c 28 on
 					probe DB_USB DB_1C_5G
 				end
 			end

From d18cc50e6ab25dca0e684589e09c729b17b2d94b Mon Sep 17 00:00:00 2001
From: Maximilian Brune <maximilian.brune@9elements.com>
Date: Sun, 2 Mar 2025 23:50:07 +0100
Subject: [PATCH 2456/3886] soc/intel/xeon_sp: Use common smm_relocate

Xeons implementation and the common intel implementation are identical
functionality wise so just use the common function.

Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: I0ed42a93444e7cc0d339cf63cec4c4411b5b4f73
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86682
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
---
 src/soc/intel/common/block/cpu/smmrelocate.c  |   1 -
 src/soc/intel/xeon_sp/Kconfig                 |   1 +
 src/soc/intel/xeon_sp/cpx/cpu.c               |   2 +-
 src/soc/intel/xeon_sp/gnr/cpu.c               |   2 +-
 .../intel/xeon_sp/include/soc/smmrelocate.h   |   3 -
 src/soc/intel/xeon_sp/skx/cpu.c               |   2 +-
 src/soc/intel/xeon_sp/smmrelocate.c           | 127 ------------------
 src/soc/intel/xeon_sp/spr/cpu.c               |   2 +-
 8 files changed, 5 insertions(+), 135 deletions(-)

diff --git a/src/soc/intel/common/block/cpu/smmrelocate.c b/src/soc/intel/common/block/cpu/smmrelocate.c
index 20697825cf..8c45c218b2 100644
--- a/src/soc/intel/common/block/cpu/smmrelocate.c
+++ b/src/soc/intel/common/block/cpu/smmrelocate.c
@@ -12,7 +12,6 @@
 #include <device/pci.h>
 #include <device/pci_ops.h>
 #include <smp/node.h>
-#include <soc/cpu.h>
 #include <soc/msr.h>
 #include <soc/pci_devs.h>
 #include <soc/soc_chip.h>
diff --git a/src/soc/intel/xeon_sp/Kconfig b/src/soc/intel/xeon_sp/Kconfig
index eed04fbc62..931c0c19f4 100644
--- a/src/soc/intel/xeon_sp/Kconfig
+++ b/src/soc/intel/xeon_sp/Kconfig
@@ -31,6 +31,7 @@ config XEON_SP_COMMON_BASE
 	select SOC_INTEL_COMMON_BLOCK
 	select SOC_INTEL_COMMON_BLOCK_ACPI
 	select SOC_INTEL_COMMON_BLOCK_CPU
+	select SOC_INTEL_COMMON_BLOCK_CPU_SMMRELOCATE
 	select SOC_INTEL_COMMON_BLOCK_GPIO_DUAL_ROUTE_SUPPORT
 	select SOC_INTEL_COMMON_BLOCK_GPIO_PADCFG_PADTOL
 	select SOC_INTEL_COMMON_BLOCK_PMC_DISCOVERABLE
diff --git a/src/soc/intel/xeon_sp/cpx/cpu.c b/src/soc/intel/xeon_sp/cpx/cpu.c
index ae3f0fb423..5df399a61b 100644
--- a/src/soc/intel/xeon_sp/cpx/cpu.c
+++ b/src/soc/intel/xeon_sp/cpx/cpu.c
@@ -186,7 +186,7 @@ static void post_mp_init(void)
 static const struct mp_ops mp_ops = {
 	.pre_mp_init = pre_mp_init,
 	.get_cpu_count = get_platform_thread_count,
-	.get_smm_info = get_smm_info,
+	.get_smm_info = smm_info,
 	.pre_mp_smm_init = smm_southbridge_clear_state,
 	.relocation_handler = smm_relocation_handler,
 	.get_microcode_info = get_microcode_info,
diff --git a/src/soc/intel/xeon_sp/gnr/cpu.c b/src/soc/intel/xeon_sp/gnr/cpu.c
index 71edd70e7c..44f466d2e5 100644
--- a/src/soc/intel/xeon_sp/gnr/cpu.c
+++ b/src/soc/intel/xeon_sp/gnr/cpu.c
@@ -73,7 +73,7 @@ static const struct mp_ops mp_ops = {
 	.pre_mp_init = pre_mp_init,
 	.get_cpu_count = get_platform_thread_count,
 #if CONFIG(HAVE_SMI_HANDLER)
-	.get_smm_info = get_smm_info,
+	.get_smm_info = smm_info,
 	.pre_mp_smm_init = smm_southbridge_clear_state,
 	.relocation_handler = smm_relocation_handler,
 #endif
diff --git a/src/soc/intel/xeon_sp/include/soc/smmrelocate.h b/src/soc/intel/xeon_sp/include/soc/smmrelocate.h
index b18d05703b..c3b179caa4 100644
--- a/src/soc/intel/xeon_sp/include/soc/smmrelocate.h
+++ b/src/soc/intel/xeon_sp/include/soc/smmrelocate.h
@@ -5,9 +5,6 @@
 
 #include <cpu/x86/smm.h>
 
-void get_smm_info(uintptr_t *perm_smbase, size_t *perm_smsize,
-		  size_t *smm_save_state_size);
-
 void soc_ubox_store_resources(struct smm_pci_resource_info *slots, size_t size);
 
 #endif
diff --git a/src/soc/intel/xeon_sp/skx/cpu.c b/src/soc/intel/xeon_sp/skx/cpu.c
index 1becda8f0a..e829aa988c 100644
--- a/src/soc/intel/xeon_sp/skx/cpu.c
+++ b/src/soc/intel/xeon_sp/skx/cpu.c
@@ -268,7 +268,7 @@ static void post_mp_init(void)
 static const struct mp_ops mp_ops = {
 	.pre_mp_init = pre_mp_init,
 	.get_cpu_count = get_platform_thread_count,
-	.get_smm_info = get_smm_info,
+	.get_smm_info = smm_info,
 	.pre_mp_smm_init = smm_southbridge_clear_state,
 	.relocation_handler = smm_relocation_handler,
 	.get_microcode_info = get_microcode_info,
diff --git a/src/soc/intel/xeon_sp/smmrelocate.c b/src/soc/intel/xeon_sp/smmrelocate.c
index c1079d31a6..28fe76e35b 100644
--- a/src/soc/intel/xeon_sp/smmrelocate.c
+++ b/src/soc/intel/xeon_sp/smmrelocate.c
@@ -14,133 +14,6 @@
 #include <soc/smmrelocate.h>
 #include <soc/pci_devs.h>
 
-static void fill_in_relocation_params(struct smm_relocation_params *params)
-{
-	uintptr_t tseg_base;
-	size_t tseg_size;
-
-	smm_region(&tseg_base, &tseg_size);
-
-	if (!IS_ALIGNED(tseg_base, tseg_size)) {
-		/*
-		 * Note SMRR2 is supported which might support base/size combinations.
-		 * For now it looks like FSP-M always uses aligned base/size, so let's
-		 * not care about that.
-		 */
-		printk(BIOS_WARNING,
-		       "TSEG base not aligned with TSEG SIZE! Not setting SMRR\n");
-		return;
-	}
-
-	/* SMRR has 32-bits of valid address aligned to 4KiB. */
-	if (!IS_ALIGNED(tseg_size, 4 * KiB)) {
-		printk(BIOS_WARNING,
-		       "TSEG size not aligned to the minimum 4KiB! Not setting SMRR\n");
-		return;
-	}
-
-	smm_subregion(SMM_SUBREGION_CHIPSET, &params->ied_base, &params->ied_size);
-
-	params->smrr_base.lo = tseg_base | MTRR_TYPE_WRBACK;
-	params->smrr_base.hi = 0;
-	params->smrr_mask.lo = ~(tseg_size - 1) | MTRR_PHYS_MASK_VALID;
-	params->smrr_mask.hi = 0;
-}
-
-static void setup_ied_area(struct smm_relocation_params *params)
-{
-	char *ied_base;
-
-	const struct ied_header ied = {
-		.signature = "INTEL RSVD",
-		.size = params->ied_size,
-		.reserved = {0},
-	};
-
-	ied_base = (void *)params->ied_base;
-
-	printk(BIOS_DEBUG, "IED base = 0x%08x\n", (u32)params->ied_base);
-	printk(BIOS_DEBUG, "IED size = 0x%08x\n", (u32)params->ied_size);
-
-	/* Place IED header at IEDBASE. */
-	memcpy(ied_base, &ied, sizeof(ied));
-
-	assert(params->ied_size > 1 * MiB + 32 * KiB);
-
-	/* Zero out 32KiB at IEDBASE + 1MiB */
-	memset(ied_base + 1 * MiB, 0, 32 * KiB);
-}
-
-void get_smm_info(uintptr_t *perm_smbase, size_t *perm_smsize,
-		  size_t *smm_save_state_size)
-{
-	fill_in_relocation_params(&smm_reloc_params);
-
-	smm_subregion(SMM_SUBREGION_HANDLER, perm_smbase, perm_smsize);
-
-	if (smm_reloc_params.ied_size)
-		setup_ied_area(&smm_reloc_params);
-
-	*smm_save_state_size = sizeof(em64t101_smm_state_save_area_t);
-}
-
-static void update_save_state(uintptr_t curr_smbase,
-			      uintptr_t staggered_smbase,
-			      struct smm_relocation_params *relo_params)
-{
-	u32 smbase;
-	u32 iedbase;
-	em64t101_smm_state_save_area_t *save_state;
-	/*
-	 * The relocated handler runs with all CPUs concurrently. Therefore
-	 * stagger the entry points adjusting SMBASE downwards by save state
-	 * size * CPU num.
-	 */
-	smbase = staggered_smbase;
-	iedbase = relo_params->ied_base;
-
-	printk(BIOS_DEBUG, "New SMBASE=0x%08x IEDBASE=0x%08x\n apic_id=0x%x\n",
-		smbase, iedbase, initial_lapicid());
-
-	save_state = (void *)(curr_smbase + SMM_DEFAULT_SIZE - sizeof(*save_state));
-
-	save_state->smbase = smbase;
-	save_state->iedbase = iedbase;
-}
-
-/*
- * The relocation work is actually performed in SMM context, but the code
- * resides in the ramstage module. This occurs by trampolining from the default
- * SMRAM entry point to here.
- */
-void smm_relocation_handler(int cpu, uintptr_t curr_smbase,
-				uintptr_t staggered_smbase)
-{
-	msr_t mtrr_cap, msr;
-	struct smm_relocation_params *relo_params = &smm_reloc_params;
-
-	printk(BIOS_DEBUG, "%s : CPU %d\n", __func__, cpu);
-
-	/* Make appropriate changes to the save state map. */
-	update_save_state(curr_smbase, staggered_smbase, relo_params);
-
-	/* Write SMRR MSRs based on indicated support. */
-	mtrr_cap = rdmsr(MTRR_CAP_MSR);
-
-	/* Set Lock bit if supported */
-	if (mtrr_cap.lo & SMRR_LOCK_SUPPORTED) {
-		msr = rdmsr(IA32_SMRR_PHYS_MASK);
-		/* Don't write the same core scope MSR if another thread has locked it,
-		   otherwise system would hang. */
-		if (msr.lo & SMRR_PHYS_MASK_LOCK)
-			return;
-		relo_params->smrr_mask.lo |= SMRR_PHYS_MASK_LOCK;
-	}
-
-	if (mtrr_cap.lo & SMRR_SUPPORTED)
-		write_smrr(relo_params);
-}
-
 void soc_ubox_store_resources(struct smm_pci_resource_info *slots, size_t size)
 {
 	struct device *devices[CONFIG_MAX_SOCKET] = {0};
diff --git a/src/soc/intel/xeon_sp/spr/cpu.c b/src/soc/intel/xeon_sp/spr/cpu.c
index ec369b2c5c..cafdc37970 100644
--- a/src/soc/intel/xeon_sp/spr/cpu.c
+++ b/src/soc/intel/xeon_sp/spr/cpu.c
@@ -239,7 +239,7 @@ static const struct mp_ops mp_ops = {
 	.pre_mp_init = pre_mp_init,
 	.get_cpu_count = get_platform_thread_count,
 #if CONFIG(HAVE_SMI_HANDLER)
-	.get_smm_info = get_smm_info,
+	.get_smm_info = smm_info,
 	.pre_mp_smm_init = smm_southbridge_clear_state,
 	.relocation_handler = smm_relocation_handler,
 #endif

From 3c69295ce4b138992fd3543c00f824bdeccba0a3 Mon Sep 17 00:00:00 2001
From: Luca Lai <luca.lai@lcfc.corp-partner.google.com>
Date: Tue, 4 Nov 2025 15:35:25 +0800
Subject: [PATCH 2457/3886] mb/google/fatcat/var/ruby: Add new supported memory
 part

Add ruby project new supported memory parts in mem_parts_used.txt.
Generate SPD id for this part.

Micron MT62F1G32D2DS-020 WT:D
Samsung K3KL8L80EM-MGCV

BUG=b:446771934
TEST=Use part_id_gen to generate related settings

Change-Id: Ic2710e9a5e59ffecb3fd696c15b944eb58e23f0b
Signed-off-by: Luca Lai <luca.lai@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89886
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: YH Lin <yueherngl@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
---
 src/mainboard/google/fatcat/variants/ruby/memory/Makefile.mk  | 4 +++-
 .../google/fatcat/variants/ruby/memory/dram_id.generated.txt  | 4 +++-
 .../google/fatcat/variants/ruby/memory/mem_parts_used.txt     | 2 ++
 3 files changed, 8 insertions(+), 2 deletions(-)

diff --git a/src/mainboard/google/fatcat/variants/ruby/memory/Makefile.mk b/src/mainboard/google/fatcat/variants/ruby/memory/Makefile.mk
index e58d787420..5bf822a1fa 100644
--- a/src/mainboard/google/fatcat/variants/ruby/memory/Makefile.mk
+++ b/src/mainboard/google/fatcat/variants/ruby/memory/Makefile.mk
@@ -1,7 +1,9 @@
 # SPDX-License-Identifier: GPL-2.0-or-later
 # This is an auto-generated file. Do not edit!!
 # Generated by:
-# /tmp/go-build4042912853/b001/exe/part_id_gen PTL lp5 src/mainboard/google/fatcat/variants/ruby/memory/ src/mainboard/google/fatcat/variants/ruby/memory/mem_parts_used.txt
+# ./util/spd_tools/bin/part_id_gen ADL lp5 src/mainboard/google/fatcat/variants/ruby/memory/ src/mainboard/google/fatcat/variants/ruby/memory/mem_parts_used.txt
 
 SPD_SOURCES =
 SPD_SOURCES += spd/lp5/set-0/spd-11.hex      # ID = 0(0b0000)  Parts = H58G56CK8BX146
+SPD_SOURCES += spd/lp5/set-0/spd-14.hex      # ID = 1(0b0001)  Parts = MT62F1G32D2DS-020 WT:D
+SPD_SOURCES += spd/lp5/set-0/spd-10.hex      # ID = 2(0b0010)  Parts = K3KL8L80EM-MGCV
diff --git a/src/mainboard/google/fatcat/variants/ruby/memory/dram_id.generated.txt b/src/mainboard/google/fatcat/variants/ruby/memory/dram_id.generated.txt
index 4248666b32..d37b6715e1 100644
--- a/src/mainboard/google/fatcat/variants/ruby/memory/dram_id.generated.txt
+++ b/src/mainboard/google/fatcat/variants/ruby/memory/dram_id.generated.txt
@@ -1,7 +1,9 @@
 # SPDX-License-Identifier: GPL-2.0-or-later
 # This is an auto-generated file. Do not edit!!
 # Generated by:
-# /tmp/go-build4042912853/b001/exe/part_id_gen PTL lp5 src/mainboard/google/fatcat/variants/ruby/memory/ src/mainboard/google/fatcat/variants/ruby/memory/mem_parts_used.txt
+# ./util/spd_tools/bin/part_id_gen ADL lp5 src/mainboard/google/fatcat/variants/ruby/memory/ src/mainboard/google/fatcat/variants/ruby/memory/mem_parts_used.txt
 
 DRAM Part Name                 ID to assign
 H58G56CK8BX146                 0 (0000)
+MT62F1G32D2DS-020 WT:D         1 (0001)
+K3KL8L80EM-MGCV                2 (0010)
diff --git a/src/mainboard/google/fatcat/variants/ruby/memory/mem_parts_used.txt b/src/mainboard/google/fatcat/variants/ruby/memory/mem_parts_used.txt
index 49d566c412..149a20f41f 100644
--- a/src/mainboard/google/fatcat/variants/ruby/memory/mem_parts_used.txt
+++ b/src/mainboard/google/fatcat/variants/ruby/memory/mem_parts_used.txt
@@ -10,3 +10,5 @@
 
 # Part Name
 H58G56CK8BX146
+MT62F1G32D2DS-020 WT:D
+K3KL8L80EM-MGCV

From 113cef70fd4139611842649410d86bc2a573ed94 Mon Sep 17 00:00:00 2001
From: Subrata Banik <subratabanik@google.com>
Date: Mon, 10 Nov 2025 23:15:02 +0530
Subject: [PATCH 2458/3886] soc/intel: Move USB port macros (2.0/3.0/TCSS) to
 IA common header
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

The USB port configuration macros (covering USB 2.0, 3.0, and TCSS) are
currently duplicated across multiple Intel SoC headers.

This patch refactors the definitions into a new, central IA common
header file. Moving these macros to a shared location eliminates
redundant code, simplifies maintenance, and ensures consistency across
platforms.

Specifically, this refactoring allows Intel Meteor Lake (MTL) and
Panther Lake (PTL) to immediately adopt the common definitions.

TEST=Able to build and boot google/kinmen.

Change-Id: I7fb1e4d100c6d72eba0e31f37aa58e6d741ceea6
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89984
Reviewed-by: Pranava Y N <pranavayn@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
---
 .../block/include/intelblocks}/usb.h          |   5 +-
 src/soc/intel/meteorlake/chip.h               |   2 +-
 src/soc/intel/pantherlake/chip.h              |   2 +-
 src/soc/intel/pantherlake/include/soc/usb.h   | 155 ------------------
 4 files changed, 4 insertions(+), 160 deletions(-)
 rename src/soc/intel/{meteorlake/include/soc => common/block/include/intelblocks}/usb.h (97%)
 delete mode 100644 src/soc/intel/pantherlake/include/soc/usb.h

diff --git a/src/soc/intel/meteorlake/include/soc/usb.h b/src/soc/intel/common/block/include/intelblocks/usb.h
similarity index 97%
rename from src/soc/intel/meteorlake/include/soc/usb.h
rename to src/soc/intel/common/block/include/intelblocks/usb.h
index 70a367ec59..44094d29fe 100644
--- a/src/soc/intel/meteorlake/include/soc/usb.h
+++ b/src/soc/intel/common/block/include/intelblocks/usb.h
@@ -1,7 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
-#ifndef _SOC_USB_H_
-#define _SOC_USB_H_
+#ifndef SOC_INTEL_COMMON_BLOCK_USB_H
+#define SOC_INTEL_COMMON_BLOCK_USB_H
 
 #include <stdint.h>
 
@@ -152,5 +152,4 @@ struct tcss_port_config {
 	.ocpin            = (pin), \
 }
 
-
 #endif
diff --git a/src/soc/intel/meteorlake/chip.h b/src/soc/intel/meteorlake/chip.h
index 88aaaf6435..7c4c954d26 100644
--- a/src/soc/intel/meteorlake/chip.h
+++ b/src/soc/intel/meteorlake/chip.h
@@ -12,11 +12,11 @@
 #include <intelblocks/power_limit.h>
 #include <intelblocks/pcie_rp.h>
 #include <intelblocks/tcss.h>
+#include <intelblocks/usb.h>
 #include <soc/gpe.h>
 #include <soc/pci_devs.h>
 #include <soc/pmc.h>
 #include <soc/serialio.h>
-#include <soc/usb.h>
 #include <stdbool.h>
 #include <stdint.h>
 
diff --git a/src/soc/intel/pantherlake/chip.h b/src/soc/intel/pantherlake/chip.h
index b1bd1a50a7..601c026c6f 100644
--- a/src/soc/intel/pantherlake/chip.h
+++ b/src/soc/intel/pantherlake/chip.h
@@ -12,12 +12,12 @@
 #include <intelblocks/power_limit.h>
 #include <intelblocks/pcie_rp.h>
 #include <intelblocks/tcss.h>
+#include <intelblocks/usb.h>
 #include <soc/gpe.h>
 #include <soc/pci_devs.h>
 #include <soc/pmc.h>
 #include <soc/serialio.h>
 #include <soc/tcss.h>
-#include <soc/usb.h>
 #include <stdint.h>
 
 /* Define config parameters for In-Band ECC (IBECC). */
diff --git a/src/soc/intel/pantherlake/include/soc/usb.h b/src/soc/intel/pantherlake/include/soc/usb.h
deleted file mode 100644
index 1e68d8d73f..0000000000
--- a/src/soc/intel/pantherlake/include/soc/usb.h
+++ /dev/null
@@ -1,155 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#ifndef _SOC_PANTHERLAKE_USB_H_
-#define _SOC_PANTHERLAKE_USB_H_
-
-#include <stdint.h>
-
-/* Per Port HS Transmitter Emphasis */
-#define USB2_EMP_OFF			0
-#define USB2_DE_EMP_ON			1
-#define USB2_PRE_EMP_ON			2
-#define USB2_DE_EMP_ON_PRE_EMP_ON	3
-
-/* Per Port Half Bit Pre-emphasis */
-#define USB2_FULL_BIT_PRE_EMP	0
-#define USB2_HALF_BIT_PRE_EMP	1
-
-/* Per Port HS Preemphasis Bias */
-#define USB2_BIAS_0MV		0
-#define USB2_BIAS_11P25MV	1
-#define USB2_BIAS_16P9MV	2
-#define USB2_BIAS_28P15MV	3
-#define USB2_BIAS_39P35MV	5
-#define USB2_BIAS_45MV		6
-#define USB2_BIAS_56P3MV	7
-
-struct usb2_port_config {
-	uint8_t enable;
-	uint8_t ocpin;
-	uint8_t tx_bias;
-	uint8_t tx_emp_enable;
-	uint8_t pre_emp_bias;
-	uint8_t pre_emp_bit;
-	uint8_t type_c;
-};
-
-/* USB Overcurrent pins definition */
-enum {
-	OC0 = 0,
-	OC1,
-	OC2,
-	OC3,
-	OC4,
-	OC5,
-	OC6,
-	OC7,
-	OCMAX,
-	OC_SKIP = 0xff, /* Skip OC programming */
-};
-
-/* Standard USB Port based on length:
- * - External
- * - Back Panel
- * - OTG
- * - M.2
- * - Internal device down */
-
-#define USB2_PORT_EMPTY { \
-	.enable        = 0, \
-	.ocpin         = OC_SKIP, \
-	.tx_bias       = USB2_BIAS_0MV, \
-	.tx_emp_enable = USB2_EMP_OFF, \
-	.pre_emp_bias  = USB2_BIAS_0MV, \
-	.pre_emp_bit   = USB2_HALF_BIT_PRE_EMP, \
-}
-
-/* Length = 11.5"-12" */
-#define USB2_PORT_LONG(pin) { \
-	.enable        = 1, \
-	.ocpin         = (pin), \
-	.tx_bias       = USB2_BIAS_39P35MV, \
-	.tx_emp_enable = USB2_PRE_EMP_ON, \
-	.pre_emp_bias  = USB2_BIAS_56P3MV, \
-	.pre_emp_bit   = USB2_HALF_BIT_PRE_EMP, \
-}
-
-/* Length  = 6"-11.49" */
-#define USB2_PORT_MID(pin) { \
-	.enable        = 1, \
-	.ocpin         = (pin), \
-	.tx_bias       = USB2_BIAS_0MV, \
-	.tx_emp_enable = USB2_DE_EMP_ON_PRE_EMP_ON, \
-	.pre_emp_bias  = USB2_BIAS_45MV, \
-	.pre_emp_bit   = USB2_FULL_BIT_PRE_EMP, \
-}
-
-/* Length = 3"-5.99" */
-#define USB2_PORT_SHORT(pin) { \
-	.enable        = 1, \
-	.ocpin         = (pin), \
-	.tx_bias       = USB2_BIAS_39P35MV, \
-	.tx_emp_enable = USB2_PRE_EMP_ON | USB2_DE_EMP_ON, \
-	.pre_emp_bias  = USB2_BIAS_39P35MV, \
-	.pre_emp_bit   = USB2_FULL_BIT_PRE_EMP, \
-}
-
-/* Max TX and Pre-emp settings */
-#define USB2_PORT_MAX(pin) { \
-	.enable        = 1, \
-	.ocpin         = (pin), \
-	.tx_bias       = USB2_BIAS_56P3MV, \
-	.tx_emp_enable = USB2_PRE_EMP_ON, \
-	.pre_emp_bias  = USB2_BIAS_56P3MV, \
-	.pre_emp_bit   = USB2_HALF_BIT_PRE_EMP, \
-}
-
-/* Type-C Port, no BC1.2 charge detect module / MUX
- * Length  = 3.0" - 9.00" */
-#define USB2_PORT_TYPE_C(pin) { \
-	.enable        = 1, \
-	.ocpin         = (pin), \
-	.tx_bias       = USB2_BIAS_0MV, \
-	.tx_emp_enable = USB2_PRE_EMP_ON, \
-	.pre_emp_bias  = USB2_BIAS_56P3MV, \
-	.pre_emp_bit   = USB2_HALF_BIT_PRE_EMP, \
-	.type_c	       = 1, \
-}
-
-struct usb3_port_config {
-	uint8_t enable;
-	uint8_t ocpin;
-	uint8_t tx_de_emp;
-	uint8_t tx_downscale_amp;
-};
-
-#define USB3_PORT_EMPTY { \
-	.enable           = 0, \
-	.ocpin            = OC_SKIP, \
-	.tx_de_emp        = 0x00, \
-	.tx_downscale_amp = 0x00, \
-}
-
-#define USB3_PORT_DEFAULT(pin) { \
-	.enable           = 1, \
-	.ocpin            = (pin), \
-	.tx_de_emp        = 0x0, \
-	.tx_downscale_amp = 0x00, \
-}
-
-struct tcss_port_config {
-	uint8_t enable;
-	uint8_t ocpin;
-};
-
-#define TCSS_PORT_EMPTY { \
-	.enable           = 0, \
-	.ocpin            = OC_SKIP, \
-}
-
-#define TCSS_PORT_DEFAULT(pin) { \
-	.enable           = 1, \
-	.ocpin            = (pin), \
-}
-
-#endif /* _SOC_PANTHERLAKE_USB_H_ */

From 0e1742a7e227a97b6f3370686792f2c4f2e3080d Mon Sep 17 00:00:00 2001
From: Subrata Banik <subratabanik@google.com>
Date: Tue, 11 Nov 2025 06:18:09 +0000
Subject: [PATCH 2459/3886] mb/google/bluey: Control slow battery charging via
 boot mode

The slow battery charging control was split across two locations:
1. Unconditionally enabled in `romstage.c`.
2. Conditionally disabled later in `mainboard.c` for normal boot mode.

This split logic is unnecessary and can be simplified. Battery charging
should only be enabled when the system determines it needs to enter a
low-battery boot mode (`LB_BOOT_MODE_LOW_BATTERY`).

This commit refactors the control flow by:
1. Removing the unconditional `enable_slow_battery_charging()` call from
   `romstage.c`.
2. Enabling `slow_battery_charging()` only within `lb_add_boot_mode()`
   when the determined boot mode is low-battery.

This ensures charging is managed solely based on the determined boot
mode, confining the control logic to a single location.

BUG=b:457566143
TEST=Able to build and boot google/quenbi. Ensure charging is only
enabled in AP firmware if booted in low-battery mode.

Change-Id: I906d555b9fa4ad2581f598621ea96bda891ff47e
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89990
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
---
 src/mainboard/google/bluey/mainboard.c | 6 +++---
 src/mainboard/google/bluey/romstage.c  | 2 --
 2 files changed, 3 insertions(+), 5 deletions(-)

diff --git a/src/mainboard/google/bluey/mainboard.c b/src/mainboard/google/bluey/mainboard.c
index 123e39854d..df2d3d33a7 100644
--- a/src/mainboard/google/bluey/mainboard.c
+++ b/src/mainboard/google/bluey/mainboard.c
@@ -32,9 +32,9 @@ void lb_add_boot_mode(struct lb_header *header)
 	if (google_chromeec_is_below_critical_threshold())
 		mode->boot_mode = LB_BOOT_MODE_LOW_BATTERY;
 
-	/* Booting into normal mode hence disable charging */
-	if (mode->boot_mode == LB_BOOT_MODE_NORMAL)
-		disable_slow_battery_charging();
+	/* Enable charging only during low-battery mode */
+	if (mode->boot_mode == LB_BOOT_MODE_LOW_BATTERY)
+		enable_slow_battery_charging();
 }
 
 bool mainboard_needs_pcie_init(void)
diff --git a/src/mainboard/google/bluey/romstage.c b/src/mainboard/google/bluey/romstage.c
index da87261fef..b76dfba1f2 100644
--- a/src/mainboard/google/bluey/romstage.c
+++ b/src/mainboard/google/bluey/romstage.c
@@ -18,8 +18,6 @@ void platform_romstage_main(void)
 	/* QCLib: DDR init & train */
 	qclib_load_and_run();
 
-	enable_slow_battery_charging();
-
 	aop_fw_load_reset();
 
 	qclib_rerun();

From 2804a0d7715515801da703dede847b188e6089d6 Mon Sep 17 00:00:00 2001
From: Yu-Ping Wu <yupingso@chromium.org>
Date: Thu, 30 Oct 2025 11:31:21 +0800
Subject: [PATCH 2460/3886] mb/google/fatcat/var/lapis: Update fw_config
 definitions with UFSC

The existing fw_config definitions are obsolete. Update overridetree.cb
with new definitions and enable EC_GOOGLE_CHROMEEC_FW_CONFIG_FROM_UFSC.

BUG=b:455768543
TEST=util/abuild/abuild -x -t GOOGLE_LAPIS -a
BRANCH=none

Change-Id: I73eb453cc7caad2445e43e0a61cdddc9123fe5f2
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89814
Reviewed-by: Aamir Bohra <aamirbohra@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/google/fatcat/Kconfig           |  1 +
 .../google/fatcat/variants/lapis/fw_config.c  |  2 +-
 .../fatcat/variants/lapis/overridetree.cb     | 96 ++++++++++---------
 3 files changed, 54 insertions(+), 45 deletions(-)

diff --git a/src/mainboard/google/fatcat/Kconfig b/src/mainboard/google/fatcat/Kconfig
index 1d0f83f3ce..c1e19b8b34 100644
--- a/src/mainboard/google/fatcat/Kconfig
+++ b/src/mainboard/google/fatcat/Kconfig
@@ -138,6 +138,7 @@ config BOARD_GOOGLE_LAPIS
 	select DRIVERS_INTEL_TOUCH
 	select DRIVERS_SOUNDWIRE_CS35L56_FAMILY
 	select DRIVERS_SOUNDWIRE_CS42L43
+	select EC_GOOGLE_CHROMEEC_FW_CONFIG_FROM_UFSC
 	select EC_GOOGLE_CHROMEEC_RTK
 	select EC_GOOGLE_CHROMEEC_LPC_GENERIC_MEMORY_RANGE
 	select FSP_UGOP_EARLY_SIGN_OF_LIFE
diff --git a/src/mainboard/google/fatcat/variants/lapis/fw_config.c b/src/mainboard/google/fatcat/variants/lapis/fw_config.c
index 4221a5bf8e..8690594f37 100644
--- a/src/mainboard/google/fatcat/variants/lapis/fw_config.c
+++ b/src/mainboard/google/fatcat/variants/lapis/fw_config.c
@@ -5,5 +5,5 @@
 
 const char *get_wifi_sar_cbfs_filename(void)
 {
-	return get_wifi_sar_fw_config_filename(FW_CONFIG_FIELD(WIFI));
+	return get_wifi_sar_fw_config_filename(FW_CONFIG_FIELD(WIFI_SAR));
 }
diff --git a/src/mainboard/google/fatcat/variants/lapis/overridetree.cb b/src/mainboard/google/fatcat/variants/lapis/overridetree.cb
index c772f46ac1..120935e90c 100644
--- a/src/mainboard/google/fatcat/variants/lapis/overridetree.cb
+++ b/src/mainboard/google/fatcat/variants/lapis/overridetree.cb
@@ -1,42 +1,52 @@
 fw_config
-	field AUDIO 0 1
-		option AUDIO_NONE		0
-		option CS42L43_SNDW		1
+	field AUDIO_CODEC 0 2
+		option AUDIO_CODEC_UNKNOWN	0
+		option AUDIO_CODEC_CS42L43	1
 	end
-	field WIFI 2 3
-		option WIFI_CNVI_7		0
-		option WIFI_CNVI_7E		1
+	field CAMERA_UFC_NAME 6 8
+		option CAMERA_UFC_NAME_UNKNOWN	0
+		option CAMERA_UFC_NAME_FL225F	1
 	end
-	field TOUCHSCREEN 4 5
-		option NONE_TOUCH	0
-		option THC_RAYDIMU	1
-		option THC_ILITEK	2
+	field STORAGE_TYPE 12 14
+		option STORAGE_TYPE_UNKNOWN	0
+		option STORAGE_TYPE_NVME_GEN4	1
+		option STORAGE_TYPE_NVME_GEN5	2
 	end
-	field TOUCHPAD 6 7
-		option TOUCHPAD_UNKNOWN		0
-		option TOUCHPAD_PCT4802		1
+	field TOUCHSCREEN 17 18
+		option TOUCHSCREEN_UNKNOWN	0
+		option TOUCHSCREEN_RAYDIUM	1
+		option TOUCHSCREEN_ILITEK	2
 	end
-	field STORAGE 8 9
-		option STORAGE_UNKNOWN		0
-		option STORAGE_NVME_GEN4	1
-		option STORAGE_NVME_GEN5	2
-		option STORAGE_UFS		3
+	field TOUCHSCREEN_SOC_INTERFACE 21 22
+		option TOUCHSCREEN_SOC_INTERFACE_UNKNOWN	0
+		option TOUCHSCREEN_SOC_INTERFACE_I2C_LPSS	1
+		option TOUCHSCREEN_SOC_INTERFACE_I2C_THC	2
 	end
-	field KB 10 11
-		option KB_UNKNOWN	0
-		option KB_BL		1
+	field FINGERPRINT_INTERFACE 24 25
+		option FINGERPRINT_INTERFACE_UNKNOWN	0
+		option FINGERPRINT_INTERFACE_SPI	1
+		option FINGERPRINT_INTERFACE_USB	2
 	end
-	field UFC 12 13
-		option UFC_UNKNOWN	0
-		option UFC_1080P	1
+	field WIFI_INTERFACE 26 27
+		option WIFI_INTERFACE_UNKNOWN	0
+		option WIFI_INTERFACE_CNVI	1
 	end
-	field FP 14 15
-		option FP_ABSENT	0
-		option FP_PRESENT	1
+	field TRACKPAD 32 34
+		option TRACKPAD_UNKNOWN		0
+		option TRACKPAD_PCT4802QR	1
 	end
-	field STYLUS 16 16
-		option STYLUS_ABSENT	0
-		option STYLUS_PRESENT	1
+	field TRACKPAD_SOC_INTERFACE 37 38
+		option TRACKPAD_SOC_INTERFACE_UNKNOWN	0
+		option TRACKPAD_SOC_INTERFACE_I2C_LPSS	1
+		option TRACKPAD_SOC_INTERFACE_I2C_THC	2
+	end
+	field KB_BACKLIGHT_PRESENT 43 43
+		option KB_BACKLIGHT_ABSENT	0
+		option KB_BACKLIGHT_PRESENT	1
+	end
+	field WIFI_SAR 56 58
+		option WIFI_SAR_ID0	0
+		option WIFI_SAR_ID1	1
 	end
 end
 
@@ -377,8 +387,8 @@ chip soc/intel/pantherlake
 		end
 
 		device ref pcie_rp9 on
-			probe STORAGE STORAGE_UNKNOWN
-			probe STORAGE STORAGE_NVME_GEN4
+			probe STORAGE_TYPE STORAGE_TYPE_UNKNOWN
+			probe STORAGE_TYPE STORAGE_TYPE_NVME_GEN4
 			register "pcie_rp[PCIE_RP(9)]" = "{
 			.clk_src = 0,
 			.clk_req = 0,
@@ -392,8 +402,7 @@ chip soc/intel/pantherlake
 		end # Gen4 SSD
 
 		device ref cnvi_wifi on
-			probe WIFI WIFI_CNVI_7
-			probe WIFI WIFI_CNVI_7E
+			probe WIFI_INTERFACE WIFI_INTERFACE_CNVI
 			chip drivers/wifi/generic
 				register "wake" = "GPE0_PME_B0"
 				register "add_acpi_dma_property" = "true"
@@ -404,8 +413,7 @@ chip soc/intel/pantherlake
 		end # CNVi
 
 		device ref cnvi_bluetooth on
-			probe WIFI WIFI_CNVI_7
-			probe WIFI WIFI_CNVI_7E
+			probe WIFI_INTERFACE WIFI_INTERFACE_CNVI
 			chip soc/intel/common/block/cnvi
 				register "wake" = "GPE0_PME_B0"
 				device generic 0 on end
@@ -415,7 +423,7 @@ chip soc/intel/pantherlake
 		device ref thc0 on
 			register "thc_wake_on_touch[0]" = "true"
 			register "thc_mode[0]" = "THC_HID_I2C_MODE"
-			probe TOUCHPAD TOUCHPAD_PCT4802
+			probe TRACKPAD TRACKPAD_PCT4802QR
 			# THC0 is function 0; hence it needs to be enabled when THC1 is to be enabled.
 			chip drivers/intel/touch
 				register "name" = "INTEL_THC0_NAME"
@@ -433,12 +441,12 @@ chip soc/intel/pantherlake
 				register "add_acpi_dma_property" = "true"
 				device generic 0 on end
 			end
-		end #Touchpad
+		end #Trackpad
 		device ref thc1 on
 			register "thc_wake_on_touch[1]" = "true"
 			register "thc_mode[1]" = "THC_HID_I2C_MODE"
-			probe TOUCHSCREEN THC_RAYDIMU
-			probe TOUCHSCREEN THC_ILITEK
+			probe TOUCHSCREEN TOUCHSCREEN_RAYDIUM
+			probe TOUCHSCREEN TOUCHSCREEN_ILITEK
 			chip drivers/intel/touch
 				register "name" = "INTEL_THC1_NAME"
 				register "mode" = "THC_HID_I2C_MODE"
@@ -455,7 +463,7 @@ chip soc/intel/pantherlake
 				register "connected_device" = "TH_SENSOR_GENERIC"
 				register "add_acpi_dma_property" = "true"
 				device generic 0 on
-					probe TOUCHSCREEN THC_RAYDIMU
+					probe TOUCHSCREEN TOUCHSCREEN_RAYDIUM
 				end
 			end
 			chip drivers/intel/touch
@@ -474,13 +482,13 @@ chip soc/intel/pantherlake
 				register "connected_device" = "TH_SENSOR_GENERIC"
 				register "add_acpi_dma_property" = "true"
 				device generic 0 on
-					probe TOUCHSCREEN THC_ILITEK
+					probe TOUCHSCREEN TOUCHSCREEN_ILITEK
 				end
 			end
-		end #Touchpenal
+		end #Touchscreen
 
 		device ref hda on
-			probe AUDIO CS42L43_SNDW
+			probe AUDIO_CODEC AUDIO_CODEC_CS42L43
 			chip drivers/intel/soundwire
 				device generic 0 on
 					chip drivers/soundwire/cs42l43

From 4c5c62bc8dcbcb6ac477df578f2ee4da82fc6983 Mon Sep 17 00:00:00 2001
From: "luca.lai" <luca.lai@lcfc.corp-partner.google.com>
Date: Tue, 11 Nov 2025 13:46:35 +0800
Subject: [PATCH 2461/3886] mb/google/fatcat/var/ruby: Modify gpio pin for
 enabling audio function

Correct gpio pin GPP_H17 to enable audio function.

schematics: RUBY_EVT_0902_2112.pdf

BUG=b:444302973
TEST=Use local test bios and kernel to test audio function works.

Change-Id: I2145349f23915b7fe7ba6002ef6b5cbdfea3e5bb
Signed-off-by: luca.lai <luca.lai@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89991
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Derek Huang <derekhuang@google.com>
---
 src/mainboard/google/fatcat/variants/ruby/gpio.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/mainboard/google/fatcat/variants/ruby/gpio.c b/src/mainboard/google/fatcat/variants/ruby/gpio.c
index 9eb0fbe80e..51355e7f45 100644
--- a/src/mainboard/google/fatcat/variants/ruby/gpio.c
+++ b/src/mainboard/google/fatcat/variants/ruby/gpio.c
@@ -317,7 +317,7 @@ static const struct pad_config gpio_table[] = {
 	/* GPP_H16:     NC */
 	PAD_NC(GPP_H16, NONE),
 	/* GPP_H17:     SOC_HP_INT_L */
-	PAD_CFG_GPI(GPP_H17, NONE, DEEP),
+	PAD_CFG_GPI_INT(GPP_H17, NONE, PLTRST, EDGE_BOTH),
 	/* GPP_H19:     I3C0_SDA_HDR */
 	PAD_CFG_NF(GPP_H19, NONE, DEEP, NF2),
 	/* GPP_H20:     I3C0_SCL_HDR */

From ec5b5386d4acd2de197b82d5bcff7c1539b47ced Mon Sep 17 00:00:00 2001
From: Angel Pons <th3fanbus@gmail.com>
Date: Tue, 28 Oct 2025 13:23:09 +0100
Subject: [PATCH 2462/3886] soc/intel/mtl/romstage/fsp_params.c: Refactor
 `pcie_rp_init()`

Extract the logic to configure PCIe RPs' clock source and clock request
signals to a separate function, so that the loop in `pcie_rp_init()` is
easier to reuse to program other PCIe-related settings.

While we're at it, make a few small improvements such as printing which
RP index is missing the clock structure definition as well as using the
`BIT()` macro (which is already used in `pcie_rp_init()`. Also retype a
few variables for the RP index, as it is never bigger than a `uint8_t`,
the type of the return value of the `get_max_pcie_port()` function.

Change-Id: I5583ef863630790cedd901e7bd30f4606f887a04
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89790
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
---
 .../intel/meteorlake/romstage/fsp_params.c    | 53 ++++++++++---------
 1 file changed, 29 insertions(+), 24 deletions(-)

diff --git a/src/soc/intel/meteorlake/romstage/fsp_params.c b/src/soc/intel/meteorlake/romstage/fsp_params.c
index 49e3b09ea2..f16def4aef 100644
--- a/src/soc/intel/meteorlake/romstage/fsp_params.c
+++ b/src/soc/intel/meteorlake/romstage/fsp_params.c
@@ -36,35 +36,40 @@
 #define FSP_CLK_LAN			0x70
 #define FSP_CLK_FREE_RUNNING		0x80
 
+static void configure_rp_clocks(FSP_M_CONFIG *m_cfg,
+				const struct pcie_rp_config *rp_cfg,
+				size_t index)
+{
+	static unsigned int clk_req_mapping = 0;
+
+	if (CONFIG(SOC_INTEL_COMPLIANCE_TEST_MODE))
+		return;
+	if (rp_cfg->flags & PCIE_RP_CLK_SRC_UNUSED)
+		return;
+	if (!rp_cfg->flags && rp_cfg->clk_src == 0 && rp_cfg->clk_req == 0) {
+		printk(BIOS_WARNING, "Missing root port %zu clock structure definition\n",
+			index + 1);
+		return;
+	}
+	if (!(rp_cfg->flags & PCIE_RP_CLK_REQ_UNUSED)) {
+		if (clk_req_mapping & BIT(rp_cfg->clk_req)) {
+			printk(BIOS_WARNING,
+			       "Found overlapped clkreq assignment on clk req %u\n",
+			       rp_cfg->clk_req);
+		}
+		m_cfg->PcieClkSrcClkReq[rp_cfg->clk_src] = rp_cfg->clk_req;
+		clk_req_mapping |= BIT(rp_cfg->clk_req);
+	}
+	m_cfg->PcieClkSrcUsage[rp_cfg->clk_src] = index;
+}
+
 static void pcie_rp_init(FSP_M_CONFIG *m_cfg, uint32_t en_mask,
 			const struct pcie_rp_config *cfg, size_t cfg_count)
 {
-	size_t i;
-	static unsigned int clk_req_mapping = 0;
-
-	/* Will be refactored to only skip configuring CLKSRC and CLKREQ */
-	if (CONFIG(SOC_INTEL_COMPLIANCE_TEST_MODE))
-		return;
-
-	for (i = 0; i < cfg_count; i++) {
+	for (size_t i = 0; i < cfg_count; i++) {
 		if (!(en_mask & BIT(i)))
 			continue;
-		if (cfg[i].flags & PCIE_RP_CLK_SRC_UNUSED)
-			continue;
-		if (!cfg[i].flags && cfg[i].clk_src == 0 && cfg[i].clk_req == 0) {
-			printk(BIOS_WARNING, "Missing root port clock structure definition\n");
-			continue;
-		}
-
-		if (!(cfg[i].flags & PCIE_RP_CLK_REQ_UNUSED)) {
-			if (clk_req_mapping & (1 << cfg[i].clk_req))
-				printk(BIOS_WARNING,
-				       "Found overlapped clkreq assignment on clk req %u\n",
-				       cfg[i].clk_req);
-			m_cfg->PcieClkSrcClkReq[cfg[i].clk_src] = cfg[i].clk_req;
-			clk_req_mapping |= 1 << cfg[i].clk_req;
-		}
-		m_cfg->PcieClkSrcUsage[cfg[i].clk_src] = i;
+		configure_rp_clocks(m_cfg, &cfg[i], i);
 	}
 }
 

From afa6c31ef57fc50f7b6fdc7c0da4af82094c6055 Mon Sep 17 00:00:00 2001
From: Kilian Krause <kilian.krause@siemens.com>
Date: Tue, 28 Oct 2025 17:20:10 +0100
Subject: [PATCH 2463/3886] soc/intel/alderlake/romstage/fsp_params.c: Refactor
 `pcie_rp_init()`

Extract PCIe RP clock configuration logic to a separate function,
following the same refactoring done for Meteor Lake in CB:89790.

Change-Id: I0abc48c066697199acfc7b77ee553e4e8c7b5119
Signed-off-by: Kilian Krause <kilian.krause@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89802
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
---
 src/soc/intel/alderlake/romstage/fsp_params.c | 46 ++++++++++---------
 1 file changed, 25 insertions(+), 21 deletions(-)

diff --git a/src/soc/intel/alderlake/romstage/fsp_params.c b/src/soc/intel/alderlake/romstage/fsp_params.c
index 5be064e4dd..22a37ea84b 100644
--- a/src/soc/intel/alderlake/romstage/fsp_params.c
+++ b/src/soc/intel/alderlake/romstage/fsp_params.c
@@ -55,36 +55,40 @@ static uint8_t clk_src_to_fsp(enum pcie_rp_type type, int rp_number)
 		return CPU_PCIE_BASE + rp_number;
 }
 
-static void pcie_rp_init(FSP_M_CONFIG *m_cfg, uint32_t en_mask, enum pcie_rp_type type,
-			const struct pcie_rp_config *cfg, size_t cfg_count)
+static void configure_rp_clocks(FSP_M_CONFIG *m_cfg, enum pcie_rp_type type,
+		const struct pcie_rp_config *rp_cfg, size_t index)
 {
-	size_t i;
 	/* bitmask to save the status of clkreq assignment */
 	static unsigned int clk_req_mapping = 0;
 
-	/* Will be refactored to only skip configuring CLKSRC and CLKREQ */
 	if (CONFIG(SOC_INTEL_COMPLIANCE_TEST_MODE))
 		return;
+	if (rp_cfg->flags & PCIE_RP_CLK_SRC_UNUSED)
+		return;
+	if (!rp_cfg->flags && rp_cfg->clk_src == 0 && rp_cfg->clk_req == 0) {
+		printk(BIOS_WARNING, "Missing %s root port %zu clock structure definition\n",
+			type == PCIE_RP_CPU ? "CPU" : "PCH", index + 1);
+		return;
+	}
+	if (!(rp_cfg->flags & PCIE_RP_CLK_REQ_UNUSED)) {
+		if (clk_req_mapping & (BIT(rp_cfg->clk_req))) {
+			printk(BIOS_WARNING,
+				"Found overlapped clkreq assignment on clk req %u\n",
+				rp_cfg->clk_req);
+		}
+		m_cfg->PcieClkSrcClkReq[rp_cfg->clk_src] = rp_cfg->clk_req;
+		clk_req_mapping |= BIT(rp_cfg->clk_req);
+	}
+	m_cfg->PcieClkSrcUsage[rp_cfg->clk_src] = clk_src_to_fsp(type, index);
+}
 
-	for (i = 0; i < cfg_count; i++) {
+static void pcie_rp_init(FSP_M_CONFIG *m_cfg, uint32_t en_mask, enum pcie_rp_type type,
+		const struct pcie_rp_config *cfg, size_t cfg_count)
+{
+	for (size_t i = 0; i < cfg_count; i++) {
 		if (!(en_mask & BIT(i)))
 			continue;
-		if (cfg[i].flags & PCIE_RP_CLK_SRC_UNUSED)
-			continue;
-		if (!cfg[i].flags && cfg[i].clk_src == 0 && cfg[i].clk_req == 0) {
-			printk(BIOS_WARNING, "Missing root port clock structure definition\n");
-			continue;
-		}
-
-		if (!(cfg[i].flags & PCIE_RP_CLK_REQ_UNUSED)) {
-			if (clk_req_mapping & (1 << cfg[i].clk_req))
-				printk(BIOS_WARNING,
-				       "Found overlapped clkreq assignment on clk req %u\n",
-				       cfg[i].clk_req);
-			m_cfg->PcieClkSrcClkReq[cfg[i].clk_src] = cfg[i].clk_req;
-			clk_req_mapping |= 1 << cfg[i].clk_req;
-		}
-		m_cfg->PcieClkSrcUsage[cfg[i].clk_src] = clk_src_to_fsp(type, i);
+		configure_rp_clocks(m_cfg, type, &cfg[i], i);
 	}
 }
 

From 240e17025c83c88467a2fcb2f46eb915e24ceb75 Mon Sep 17 00:00:00 2001
From: Alicja Michalska <alicja.michalska@9elements.com>
Date: Tue, 11 Nov 2025 00:04:55 +0100
Subject: [PATCH 2464/3886] src/soc/intel/ptl: Add LPSS UART DMA control

This patch implements passing a "SerialIoUartDmaEnable" pointer to
FSP-S by parsing the devicetree.

Default (0) means PIO, while 1 means DMA.

Change-Id: Id0acfe0b30899a3019ea7e54067fc06cbc56bab6
Signed-off-by: Alicja Michalska <alicja.michalska@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89989
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Pranava Y N <pranavayn@google.com>
---
 src/soc/intel/pantherlake/chip.h                 | 9 +++++++++
 src/soc/intel/pantherlake/fsp_params.c           | 2 ++
 src/soc/intel/pantherlake/include/soc/serialio.h | 5 +++++
 3 files changed, 16 insertions(+)

diff --git a/src/soc/intel/pantherlake/chip.h b/src/soc/intel/pantherlake/chip.h
index 601c026c6f..310e6d3bc2 100644
--- a/src/soc/intel/pantherlake/chip.h
+++ b/src/soc/intel/pantherlake/chip.h
@@ -483,12 +483,21 @@ struct soc_intel_pantherlake_config {
 	uint8_t serial_io_i2c_mode[CONFIG_SOC_INTEL_I2C_DEV_MAX];
 	uint8_t serial_io_gspi_mode[CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX];
 	uint8_t serial_io_uart_mode[CONFIG_SOC_INTEL_UART_DEV_MAX];
+
+	/*
+	 * SerialIO DMA/PIO mode:
+	 * 0: Disable (PIO)
+	 * 1: Enable (DMA)
+	 */
+	uint8_t serial_io_uart_dma_enable[CONFIG_SOC_INTEL_UART_DEV_MAX];
+
 	/*
 	 * GSPIn Default Chip Select Mode:
 	 * 0:Hardware Mode,
 	 * 1:Software Mode
 	 */
 	uint8_t serial_io_gspi_cs_mode[CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX];
+
 	/*
 	 * GSPIn Default Chip Select State:
 	 * 0: Low,
diff --git a/src/soc/intel/pantherlake/fsp_params.c b/src/soc/intel/pantherlake/fsp_params.c
index 0976d3bb77..0133e72c00 100644
--- a/src/soc/intel/pantherlake/fsp_params.c
+++ b/src/soc/intel/pantherlake/fsp_params.c
@@ -289,6 +289,8 @@ static void fill_fsps_lpss_params(FSP_S_CONFIG *s_cfg,
 			config->serial_io_uart_mode[i] : 0;
 		s_cfg->SerialIoUartPowerGating[i] = is_devfn_enabled(uart_dev[i]) ?
 			LPSS_UART_PG_ENABLED : LPSS_UART_PG_AUTO;
+		s_cfg->SerialIoUartDmaEnable[i] = is_devfn_enabled(uart_dev[i]) ?
+			config->serial_io_uart_dma_enable[i] : 0;
 	}
 }
 
diff --git a/src/soc/intel/pantherlake/include/soc/serialio.h b/src/soc/intel/pantherlake/include/soc/serialio.h
index 1c1500182b..c635086904 100644
--- a/src/soc/intel/pantherlake/include/soc/serialio.h
+++ b/src/soc/intel/pantherlake/include/soc/serialio.h
@@ -11,6 +11,11 @@ enum {
 	PchSerialIoSkipInit
 };
 
+enum {
+	PchSerialPio,
+	PchSerialDma
+};
+
 enum {
 	PchSerialIoIndexI2C0,
 	PchSerialIoIndexI2C1,

From a3ea128ecf334a646dc45222ac2f08c7aad19b0f Mon Sep 17 00:00:00 2001
From: David Lin <david.lin@intel.com>
Date: Mon, 27 Oct 2025 17:09:49 +0800
Subject: [PATCH 2465/3886] drivers/i2c/tas2563: Add driver for generating
 device in SSDT

This driver uses the ACPI Device Property interface to generate
the required parameters into the _DSD table format expected by
the kernel.

This was tested on the fatcat/variants/ruby mainboard to ensure
that the SSDT contained the equivalent parameters that are provided
by the current DSDT object.

BUG=b:451935496
TEST=Build and boot to Android16 with Linux 6.12.52 and check tas2563 audio driver was probed successful.

Change-Id: I801ef13937078ca9cfcd3610b1aa8aaedbaf1cf1
Signed-off-by: David Lin <david.lin@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89877
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Chiang, Mac <mac.chiang@intel.com>
---
 src/drivers/i2c/tas2563/Kconfig     |   7 ++
 src/drivers/i2c/tas2563/Makefile.mk |   3 +
 src/drivers/i2c/tas2563/chip.h      |  25 +++++++
 src/drivers/i2c/tas2563/tas2563.c   | 110 ++++++++++++++++++++++++++++
 4 files changed, 145 insertions(+)
 create mode 100644 src/drivers/i2c/tas2563/Kconfig
 create mode 100644 src/drivers/i2c/tas2563/Makefile.mk
 create mode 100644 src/drivers/i2c/tas2563/chip.h
 create mode 100644 src/drivers/i2c/tas2563/tas2563.c

diff --git a/src/drivers/i2c/tas2563/Kconfig b/src/drivers/i2c/tas2563/Kconfig
new file mode 100644
index 0000000000..8b42d816b9
--- /dev/null
+++ b/src/drivers/i2c/tas2563/Kconfig
@@ -0,0 +1,7 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
+config DRIVERS_I2C_TAS2563
+	bool
+	default n
+	help
+	  Enable support for TI TAS2563 Amplifier.
diff --git a/src/drivers/i2c/tas2563/Makefile.mk b/src/drivers/i2c/tas2563/Makefile.mk
new file mode 100644
index 0000000000..f90f11c06a
--- /dev/null
+++ b/src/drivers/i2c/tas2563/Makefile.mk
@@ -0,0 +1,3 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
+ramstage-$(CONFIG_DRIVERS_I2C_TAS2563) += tas2563.c
diff --git a/src/drivers/i2c/tas2563/chip.h b/src/drivers/i2c/tas2563/chip.h
new file mode 100644
index 0000000000..8fdf86a9cd
--- /dev/null
+++ b/src/drivers/i2c/tas2563/chip.h
@@ -0,0 +1,25 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef __DRIVERS_I2C_TAS2563_CHIP_H__
+#define __DRIVERS_I2C_TAS2563_CHIP_H__
+
+#include <acpi/acpi_device.h>
+
+#define TAS2563_MAX_AUDIO_SLOTS	8
+
+struct drivers_i2c_tas2563_config {
+	/* I2C Bus Speed */
+	enum i2c_speed bus_speed;
+
+	/* IRQ configuration */
+	struct acpi_irq irq;
+	struct acpi_gpio irq_gpio;
+
+	/* Reset GPIO configuration */
+	struct acpi_gpio reset_gpio;
+
+	/* Audio slots configuration */
+	uint64_t audio_slots[TAS2563_MAX_AUDIO_SLOTS];
+};
+
+#endif /* __DRIVERS_I2C_TAS2563_CHIP_H__ */
diff --git a/src/drivers/i2c/tas2563/tas2563.c b/src/drivers/i2c/tas2563/tas2563.c
new file mode 100644
index 0000000000..1e445910f2
--- /dev/null
+++ b/src/drivers/i2c/tas2563/tas2563.c
@@ -0,0 +1,110 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <acpi/acpi_device.h>
+#include <acpi/acpigen.h>
+#include <console/console.h>
+#include <device/i2c_simple.h>
+#include <device/device.h>
+#include <stdint.h>
+#include "chip.h"
+
+#if CONFIG(HAVE_ACPI_TABLES)
+
+#define TAS2563_ACPI_NAME	"TXNW"
+#define TAS2563_ACPI_HID	"TXNW2563"
+
+static unsigned int count_valid_audio_slots(struct drivers_i2c_tas2563_config *config)
+{
+	unsigned int count = 0;
+
+	for (unsigned int i = 0; i < TAS2563_MAX_AUDIO_SLOTS; i++) {
+		if (config->audio_slots[i] != 0)
+			count++;
+		else
+			break;
+	}
+
+	return count;
+}
+
+static void tas2563_fill_ssdt(const struct device *dev)
+{
+	struct drivers_i2c_tas2563_config *config = dev->chip_info;
+	const char *scope = acpi_device_scope(dev);
+	struct acpi_i2c i2c = {
+		.address = dev->path.i2c.device,
+		.mode_10bit = dev->path.i2c.mode_10bit,
+		.speed = config->bus_speed ? : I2C_SPEED_FAST,
+		.resource = scope,
+	};
+	struct acpi_dp *dp = NULL;
+	unsigned int slots_count = 0;
+
+	if (!scope)
+		return;
+
+	/* Device */
+	acpigen_write_scope(scope);
+	acpigen_write_device(acpi_device_name(dev));
+	acpigen_write_name_string("_HID", TAS2563_ACPI_HID);
+	acpigen_write_name_integer("_UID", 0);
+	acpigen_write_name_string("_DDN", dev->chip_ops->name);
+	acpigen_write_STA(acpi_device_status(dev));
+
+	/* Resources */
+	acpigen_write_name("_CRS");
+	acpigen_write_resourcetemplate_header();
+	acpi_device_write_i2c(&i2c);
+
+	/* Allow either GpioInt() or Interrupt() */
+	if (config->irq_gpio.pin_count)
+		acpi_device_write_gpio(&config->irq_gpio);
+	else
+		acpi_device_write_interrupt(&config->irq);
+
+	if (config->reset_gpio.pin_count)
+		acpi_device_write_gpio(&config->reset_gpio);
+
+	acpigen_write_resourcetemplate_footer();
+
+	slots_count = count_valid_audio_slots(config);
+
+	/* Device Properties */
+	if (slots_count > 0) {
+		dp = acpi_dp_new_table("_DSD");
+		acpi_dp_add_integer_array(dp, "ti,audio-slots",
+				  config->audio_slots, slots_count);
+		acpi_dp_write(dp);
+	}
+	acpigen_pop_len(); /* Device */
+	acpigen_pop_len(); /* Scope */
+
+	printk(BIOS_INFO, "%s: %s address 0%xh irq %d\n",
+	       acpi_device_path(dev), dev->chip_ops->name,
+	       dev->path.i2c.device, config->irq.pin);
+}
+
+static const char *tas2563_acpi_name(const struct device *dev)
+{
+	return TAS2563_ACPI_NAME;
+}
+#endif
+
+static struct device_operations tas2563_ops = {
+	.read_resources		= noop_read_resources,
+	.set_resources		= noop_set_resources,
+#if CONFIG(HAVE_ACPI_TABLES)
+	.acpi_name              = tas2563_acpi_name,
+	.acpi_fill_ssdt		= tas2563_fill_ssdt,
+#endif
+};
+
+static void tas2563_enable(struct device *dev)
+{
+	dev->ops = &tas2563_ops;
+}
+
+struct chip_operations drivers_i2c_tas2563_ops = {
+	.name = "TI TAS2563 Audio Amplifier",
+	.enable_dev = tas2563_enable
+};

From e08a35f806848b0db196fecbd962acb5301f6c15 Mon Sep 17 00:00:00 2001
From: David Lin <david.lin@intel.com>
Date: Tue, 28 Oct 2025 01:50:45 +0800
Subject: [PATCH 2466/3886] drivers/sof: Add support for tas2563 speaker
 topology

Enables correct identification of boards using tas2563 speaker amplifier
by SOF Windows drivers.

BUG=b:451935496
TEST=Build and boot to Android16 with Linux 6.12.52 and check tas2563 audio driver was probed successful.

Change-Id: I7dd0276a44ebb9b0712589c28ac017bff1ed5b1a
Signed-off-by: David Lin <david.lin@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89878
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
---
 src/drivers/sof/chip.h | 1 +
 src/drivers/sof/sof.c  | 1 +
 2 files changed, 2 insertions(+)

diff --git a/src/drivers/sof/chip.h b/src/drivers/sof/chip.h
index 9ac8ad8833..97e2a24ccd 100644
--- a/src/drivers/sof/chip.h
+++ b/src/drivers/sof/chip.h
@@ -18,6 +18,7 @@ enum _spkr_tplg {
 	rt1015,
 	rt1019,
 	rt5650_sp,
+	tas2563,
 };
 
 /* Jack topology */
diff --git a/src/drivers/sof/sof.c b/src/drivers/sof/sof.c
index 9f6391b214..d5eb466f5d 100644
--- a/src/drivers/sof/sof.c
+++ b/src/drivers/sof/sof.c
@@ -19,6 +19,7 @@ static const char *get_spkr_tplg_str(enum _spkr_tplg tplg)
 	case rt1015: return "rt1015";
 	case rt1019: return "rt1019";
 	case rt5650_sp: return "rt5650";
+	case tas2563: return "tas2563";
 	default: return "default";
 	}
 }

From 87c33739259e3496e0f3f51514d602a5e1b70a33 Mon Sep 17 00:00:00 2001
From: David Lin <david.lin@intel.com>
Date: Mon, 3 Nov 2025 22:27:00 +0800
Subject: [PATCH 2467/3886] mb/google/fatcat: Add FW_CONFIG Support for TAS2563

This change adds support for the TAS2563 codec in the device tree
and enables it based on the fw_config.

BUG=b:451935496
TEST=Build and boot to Android16 with Linux 6.12.52 and check tas2563 audio driver was probed successful.

Change-Id: I924518aab5463ed49bd2341cab0104e6ed3ed14b
Signed-off-by: David Lin <david.lin@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89879
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: YH Lin <yueherngl@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Chiang, Mac <mac.chiang@intel.com>
---
 src/mainboard/google/fatcat/Kconfig           |  1 +
 .../google/fatcat/variants/ruby/fw_config.c   | 97 +++++++++++++++++++
 .../fatcat/variants/ruby/overridetree.cb      | 27 +++++-
 3 files changed, 124 insertions(+), 1 deletion(-)

diff --git a/src/mainboard/google/fatcat/Kconfig b/src/mainboard/google/fatcat/Kconfig
index c1e19b8b34..f78f5e2c11 100644
--- a/src/mainboard/google/fatcat/Kconfig
+++ b/src/mainboard/google/fatcat/Kconfig
@@ -155,6 +155,7 @@ config BOARD_GOOGLE_MOONSTONE
 config BOARD_GOOGLE_MODEL_RUBY
 	def_bool n
 	select BOARD_GOOGLE_BASEBOARD_FATCAT
+	select DRIVERS_I2C_TAS2563
 	select HAVE_SLP_S0_GATE
 	select MAINBOARD_HAS_GOOGLE_STRAUSS_KEYBOARD
 
diff --git a/src/mainboard/google/fatcat/variants/ruby/fw_config.c b/src/mainboard/google/fatcat/variants/ruby/fw_config.c
index 8c207ed5e2..d02976e026 100644
--- a/src/mainboard/google/fatcat/variants/ruby/fw_config.c
+++ b/src/mainboard/google/fatcat/variants/ruby/fw_config.c
@@ -11,6 +11,93 @@
 /* t: table */
 #define GPIO_CONFIGURE_PADS(t) gpio_configure_pads(t, ARRAY_SIZE(t))
 
+static const struct pad_config i2s_enable_pads[] = {
+	/* I2S_MCLK1_OUT */
+	PAD_CFG_NF(GPP_D09, NONE, DEEP, NF2),
+	/* I2S0_SCLK_HDR */
+	PAD_CFG_NF(GPP_D10, NONE, DEEP, NF2),
+	/* I2S0_SFRM_HDR */
+	PAD_CFG_NF(GPP_D11, NONE, DEEP, NF2),
+	/* I2S0_TXD_HDR */
+	PAD_CFG_NF(GPP_D12, NONE, DEEP, NF2),
+	/* I2S0_RXD_HDR */
+	PAD_CFG_NF(GPP_D13, NONE, DEEP, NF2),
+
+	/* I2S1_TXD_HDR */
+	PAD_CFG_NF(GPP_S00, NONE, DEEP, NF6),
+	/* I2S1_RXD_HDR */
+	PAD_CFG_NF(GPP_S01, NONE, DEEP, NF6),
+	/* I2S1_SCLK_HDR */
+	PAD_CFG_NF(GPP_S02, NONE, DEEP, NF6),
+	/* I2S1_SFRM_HDR */
+	PAD_CFG_NF(GPP_S03, NONE, DEEP, NF6),
+
+	/* DMIC_CLK_A0 */
+	PAD_CFG_NF(GPP_S04, NONE, DEEP, NF5),
+	/* DMIC_CLK_A0 */
+	PAD_CFG_NF(GPP_S05, NONE, DEEP, NF5),
+	/* DMIC_CLK_A1 */
+	PAD_CFG_NF(GPP_D16, NONE, DEEP, NF3),
+	/* DMIC_DATA_A1 */
+	PAD_CFG_NF(GPP_D17, NONE, DEEP, NF3),
+};
+
+static const struct pad_config bt_i2s_enable_pads[] = {
+	/* GPP_V30 : [] ==> BT_I2S_BCLK - SSP2 */
+	PAD_CFG_NF(GPP_VGPIO30, NONE, DEEP, NF3),
+	/* GPP_V31 : [] ==> BT_I2S_SYNC - SSP2 */
+	PAD_CFG_NF(GPP_VGPIO31, NONE, DEEP, NF3),
+	/* GPP_V32 : [] ==> BT_I2S_SDO - SSP2 */
+	PAD_CFG_NF(GPP_VGPIO32, NONE, DEEP, NF3),
+	/* GPP_V33 : [] ==> BT_I2S_SDI - SSP2 */
+	PAD_CFG_NF(GPP_VGPIO33, NONE, DEEP, NF3),
+	/* GPP_V34 : [] ==> SSP_SCLK */
+	PAD_CFG_NF(GPP_VGPIO34, NONE, DEEP, NF1),
+	/* GPP_V35 : [] ==> SSP_SFRM */
+	PAD_CFG_NF(GPP_VGPIO35, NONE, DEEP, NF1),
+	/* GPP_V36 : [] ==> SSP_TXD */
+	PAD_CFG_NF(GPP_VGPIO36, NONE, DEEP, NF1),
+	/* GPP_V37 : [] ==> SSP_RXD */
+	PAD_CFG_NF(GPP_VGPIO37, NONE, DEEP, NF1),
+};
+
+static const struct pad_config bt_i2s_disable_pads[] = {
+	/* GPP_V30 : [] ==> BT_I2S_BCLK */
+	PAD_NC(GPP_VGPIO30, NONE),
+	/* GPP_V31 : [] ==> BT_I2S_SYNC */
+	PAD_NC(GPP_VGPIO31, NONE),
+	/* GPP_V32 : [] ==> BT_I2S_SDO */
+	PAD_NC(GPP_VGPIO32, NONE),
+	/* GPP_V33 : [] ==> BT_I2S_SDI */
+	PAD_NC(GPP_VGPIO33, NONE),
+	/* GPP_V34 : [] ==> SSP2_SCLK */
+	PAD_NC(GPP_VGPIO34, NONE),
+	/* GPP_V35 : [] ==> SSP2_SFRM */
+	PAD_NC(GPP_VGPIO35, NONE),
+	/* GPP_V36 : [] ==> SSP_TXD */
+	PAD_NC(GPP_VGPIO36, NONE),
+	/* GPP_V37 : [] ==> SSP_RXD */
+	PAD_NC(GPP_VGPIO37, NONE),
+};
+
+static const struct pad_config audio_disable_pads[] = {
+	PAD_NC(GPP_S00, NONE),
+	PAD_NC(GPP_S01, NONE),
+	PAD_NC(GPP_S02, NONE),
+	PAD_NC(GPP_S03, NONE),
+	PAD_NC(GPP_S04, NONE),
+	PAD_NC(GPP_S05, NONE),
+	PAD_NC(GPP_S06, NONE),
+	PAD_NC(GPP_S07, NONE),
+	PAD_NC(GPP_D09, NONE),
+	PAD_NC(GPP_D10, NONE),
+	PAD_NC(GPP_D11, NONE),
+	PAD_NC(GPP_D12, NONE),
+	PAD_NC(GPP_D13, NONE),
+	PAD_NC(GPP_D16, NONE),
+	PAD_NC(GPP_D17, NONE),
+};
+
 void fw_config_configure_pre_mem_gpio(void)
 {
 	if (!fw_config_is_provisioned()) {
@@ -25,4 +112,14 @@ void fw_config_gpio_padbased_override(struct pad_config *padbased_table)
 		printk(BIOS_WARNING, "FW_CONFIG is not provisioned, Exiting\n");
 		return;
 	}
+
+	if (fw_config_probe(FW_CONFIG(AUDIO, AUDIO_NONE))) {
+		GPIO_PADBASED_OVERRIDE(padbased_table, audio_disable_pads);
+		GPIO_PADBASED_OVERRIDE(padbased_table, bt_i2s_disable_pads);
+	} else if (fw_config_probe(FW_CONFIG(AUDIO, AUDIO_TAS2563_ALC5682I_I2S))) {
+		printk(BIOS_INFO, "Configure GPIOs for I2S TAS2563 ALC5682 audio.\n");
+		GPIO_PADBASED_OVERRIDE(padbased_table, i2s_enable_pads);
+		printk(BIOS_INFO, "Configure GPIOs for BT offload mode.\n");
+		GPIO_PADBASED_OVERRIDE(padbased_table, bt_i2s_enable_pads);
+	}
 }
diff --git a/src/mainboard/google/fatcat/variants/ruby/overridetree.cb b/src/mainboard/google/fatcat/variants/ruby/overridetree.cb
index d9552f834b..a7f37a8840 100644
--- a/src/mainboard/google/fatcat/variants/ruby/overridetree.cb
+++ b/src/mainboard/google/fatcat/variants/ruby/overridetree.cb
@@ -1,3 +1,10 @@
+fw_config
+	field AUDIO 0 1
+		option AUDIO_NONE			0
+		option AUDIO_TAS2563_ALC5682I_I2S	1
+	end
+end
+
 chip soc/intel/pantherlake
 
 	# The initial version temporarily uses the PTL-H,
@@ -242,7 +249,18 @@ chip soc/intel/pantherlake
 				register "property_list[0].name" = ""realtek,jd-src""
 				register "property_list[0].integer" = "1"
 				device i2c 1a on
-					#probe AUDIO ALC5682I_I2S
+					probe AUDIO AUDIO_TAS2563_ALC5682I_I2S
+				end
+			end
+			chip drivers/i2c/tas2563
+				register "irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPP_H03)"
+				register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D01)"
+				register "audio_slots[0]" = "0x4e"
+				register "audio_slots[1]" = "0x4f"
+				register "audio_slots[2]" = "0x4c"
+				register "audio_slots[3]" = "0x4d"
+				device i2c 4a on
+					probe AUDIO AUDIO_TAS2563_ALC5682I_I2S
 				end
 			end
 		end
@@ -288,5 +306,12 @@ chip soc/intel/pantherlake
 		end # I2C5
 		device ref gspi0 on end
 		device ref smbus on end
+		device ref hda on
+			chip drivers/sof
+				register "spkr_tplg" = "tas2563"
+				register "jack_tplg" = "rt5682"
+				device generic 0 on end
+			end
+		end
 	end
 end

From 0ba4505024290cb7c709adc45fb777a24941c559 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Micha=C5=82=20=C5=BBygowski?= <michal.zygowski@3mdeb.com>
Date: Tue, 16 Sep 2025 10:33:19 +0200
Subject: [PATCH 2468/3886] payloads/external/edk2/Makefile: Configure AP
 wakeup in UEFI payload
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

PcdFirstTimeWakeUpAPsBySipi controls the sequence of IPIs sent to APs
during AP wakeup in UefiCpuPkg. Since coreboot leaves APs parked in
halt loop, SIPI is not enough to wake them up. They need to go through
regular INIT-SIPI-SIPI sequence. Set PcdFirstTimeWakeUpAPsBySipi to
FALSE to cause the MP code in UEFI Payload to send INIT-SIPI-SIPI
sequence, otherwise the APs are not detected in UEFI Payload.

Additionally, after rebasing to the latest UefiCpuPkg, CpuDxe now calls
MpInitLibStartupAllCPUs() while setting up per-CPU exception stacks.
If we leave `PcdFirstTimeWakeUpAPsBySipi` at its default (TRUE), only a
SIPI is issued on the first wake attempt. The APs that coreboot parks in
an HLT loop never acknowledge that SIPI, the DXE driver trips
`ASSERT_EFI_ERROR()` and the UEFI payload reboots straight back into
coreboot. Explicitly set the PCD to FALSE so the INIT-SIPI-SIPI flow is
used and all cores report in.

before:
MpInitLib: Find 1 processors in system.

after:
MpInitLib: Find 4 processors in system.


TEST=edk2 boots cleanly on Star Labs Lite ADL (Intel N200) and
Gigabyte MZ33-AR1; DXE log shows all processors detected.

Change-Id: I299b74892a56894c3e15507b507a50bdf7e59860
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89210
Reviewed-by: Benjamin Doron <benjamin.doron00@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
---
 payloads/external/edk2/Makefile | 1 +
 1 file changed, 1 insertion(+)

diff --git a/payloads/external/edk2/Makefile b/payloads/external/edk2/Makefile
index 1b8ca2e67b..0b343b3d7a 100644
--- a/payloads/external/edk2/Makefile
+++ b/payloads/external/edk2/Makefile
@@ -178,6 +178,7 @@ BUILD_STR += --pcd gEfiMdeModulePkgTokenSpaceGuid.PcdSetupConOutColumn=128
 endif
 
 BUILD_STR += --pcd gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultOemId="COREv4"
+BUILD_STR += --pcd gUefiCpuPkgTokenSpaceGuid.PcdFirstTimeWakeUpAPsBySipi=FALSE
 
 bootloader = $(word 8,$(subst /, ,$(BUILD_STR)))
 

From 2a9deabc35f85e54a2778084ce3cfabc5cc6ffc7 Mon Sep 17 00:00:00 2001
From: Maximilian Brune <maximilian.brune@9elements.com>
Date: Tue, 5 Aug 2025 22:59:12 +0200
Subject: [PATCH 2469/3886] commonlib/coreboot_tables.h: Fix lb_smmstorev2
 alignment

We have a hard alignment to LB_ENTRY_ALIGN (4). We check for an
alignment of 4 bytes at the beginning of each lb_record. But since it
was 8 byte aligned, it was also automatically 4 byte aligned.
It therefore wasn't detected by coreboot.

This will break payload implementations that rely on the 8 byte
alignment for this specific struct. But since lb_smmstorev2 has only
been recently updated in commit 5bf88a44e960 ("drivers/smmstore:
Support 64-bit MMIO addresses"), one can only hope that no payloads
were updated to this yet.

Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: Ib6171b7d4bd08b8a1559833ddb048644ff082b73
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89902
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
---
 src/commonlib/include/commonlib/coreboot_tables.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/commonlib/include/commonlib/coreboot_tables.h b/src/commonlib/include/commonlib/coreboot_tables.h
index 20f192436e..d308cf0ebf 100644
--- a/src/commonlib/include/commonlib/coreboot_tables.h
+++ b/src/commonlib/include/commonlib/coreboot_tables.h
@@ -555,7 +555,7 @@ struct lb_smmstorev2 {
 	uint32_t com_buffer_size;	/* Size of the communication buffer in bytes */
 	uint8_t apm_cmd;		/* The command byte to write to the APM I/O port */
 	uint8_t unused[3];		/* Set to zero */
-	uint64_t mmap_addr;		/* 64-bit MMIO address of the store for read only access.
+	lb_uint64_t mmap_addr;		/* 64-bit MMIO address of the store for read only access.
 					   Introduced after the initial implementation. Users of
 					   this table must check the 'size' field to detect if its
 					   written out by coreboot. */

From d4bee96484dfe1fda8f983c0e088c29b4ad115c8 Mon Sep 17 00:00:00 2001
From: "Johann C. Rode" <jcrode@gmx.net>
Date: Sat, 1 Nov 2025 13:54:32 -0700
Subject: [PATCH 2470/3886] mb/lenovo/sklkbl: refactor memory_init_params to
 use gpio_base2_value()

Cosmetic fix validated on a Thinkpad T470s.

Change-Id: I7e2032a665933cb7e002a7202bcd4305dfcdbed4
Signed-off-by: Johann C. Rode <jcrode@gmx.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89864
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
---
 .../lenovo/sklkbl_thinkpad/variant.h          |  2 ++
 .../variants/t470s/memory_init_params.c       | 17 ++++++++++--
 .../variants/t480s/memory_init_params.c       | 27 ++++++++++++++-----
 3 files changed, 37 insertions(+), 9 deletions(-)

diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variant.h b/src/mainboard/lenovo/sklkbl_thinkpad/variant.h
index 66fdc0fa82..92255f2e0d 100644
--- a/src/mainboard/lenovo/sklkbl_thinkpad/variant.h
+++ b/src/mainboard/lenovo/sklkbl_thinkpad/variant.h
@@ -5,6 +5,8 @@
 
 void variant_config_gpios(void);
 
+int variant_memory_sku(void);
+
 void ssdt_add_dgpu(const struct device *dev);
 
 void dgpu_detect(void);
diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t470s/memory_init_params.c b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t470s/memory_init_params.c
index 001e934b3a..cc9375808a 100644
--- a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t470s/memory_init_params.c
+++ b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t470s/memory_init_params.c
@@ -6,6 +6,7 @@
 #include <soc/romstage.h>
 #include <spd_bin.h>
 #include <stdio.h>
+#include "../../variant.h"
 
 static const struct pad_config memory_id_gpio_table[] = {
 	PAD_CFG_GPI_TRIG_OWN(GPP_F16, UP_20K, DEEP, OFF, ACPI),		/* MEMORYID0 */
@@ -15,6 +16,19 @@ static const struct pad_config memory_id_gpio_table[] = {
 	PAD_CFG_GPI_TRIG_OWN(GPP_F20, UP_20K, DEEP, OFF, ACPI),		/* MEMORYID4 */
 };
 
+int variant_memory_sku(void)
+{
+        gpio_t spd_gpios[] = {
+                GPP_F16,
+                GPP_F17,
+                GPP_F18,
+                GPP_F19,
+                GPP_F20,
+        };
+
+        return gpio_base2_value(spd_gpios, ARRAY_SIZE(spd_gpios));
+}
+
 void mainboard_memory_init_params(FSPM_UPD *mupd)
 {
 	int spd_idx;
@@ -29,8 +43,7 @@ void mainboard_memory_init_params(FSPM_UPD *mupd)
 	/* Get SPD for soldered RAM SPD (CH A) */
 	gpio_configure_pads(memory_id_gpio_table, ARRAY_SIZE(memory_id_gpio_table));
 
-	spd_idx = gpio_get(GPP_F16) | gpio_get(GPP_F17) << 1 | gpio_get(GPP_F18) << 2 |
-		  gpio_get(GPP_F19) << 3 | gpio_get(GPP_F20) << 4;
+	spd_idx = variant_memory_sku();
 	printk(BIOS_DEBUG, "Detected MEMORY_ID = %d\n", spd_idx);
 	snprintf(spd_name, sizeof(spd_name), "spd_%d.bin", spd_idx);
 	mem_cfg->MemorySpdPtr00    = (uintptr_t)cbfs_map(spd_name, &spd_size);
diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/memory_init_params.c b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/memory_init_params.c
index 001e934b3a..3cbca9ae6c 100644
--- a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/memory_init_params.c
+++ b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/memory_init_params.c
@@ -6,15 +6,29 @@
 #include <soc/romstage.h>
 #include <spd_bin.h>
 #include <stdio.h>
+#include "../../variant.h"
 
 static const struct pad_config memory_id_gpio_table[] = {
-	PAD_CFG_GPI_TRIG_OWN(GPP_F16, UP_20K, DEEP, OFF, ACPI),		/* MEMORYID0 */
-	PAD_CFG_GPI_TRIG_OWN(GPP_F17, UP_20K, DEEP, OFF, ACPI),		/* MEMORYID1 */
-	PAD_CFG_GPI_TRIG_OWN(GPP_F18, UP_20K, DEEP, OFF, ACPI),		/* MEMORYID2 */
-	PAD_CFG_GPI_TRIG_OWN(GPP_F19, UP_20K, DEEP, OFF, ACPI),		/* MEMORYID3 */
-	PAD_CFG_GPI_TRIG_OWN(GPP_F20, UP_20K, DEEP, OFF, ACPI),		/* MEMORYID4 */
+       PAD_CFG_GPI_TRIG_OWN(GPP_F16, UP_20K, DEEP, OFF, ACPI),         /* MEMORYID0 */
+       PAD_CFG_GPI_TRIG_OWN(GPP_F17, UP_20K, DEEP, OFF, ACPI),         /* MEMORYID1 */
+       PAD_CFG_GPI_TRIG_OWN(GPP_F18, UP_20K, DEEP, OFF, ACPI),         /* MEMORYID2 */
+       PAD_CFG_GPI_TRIG_OWN(GPP_F19, UP_20K, DEEP, OFF, ACPI),         /* MEMORYID3 */
+       PAD_CFG_GPI_TRIG_OWN(GPP_F20, UP_20K, DEEP, OFF, ACPI),         /* MEMORYID4 */
 };
 
+int variant_memory_sku(void)
+{
+        gpio_t spd_gpios[] = {
+                GPP_F16,
+                GPP_F17,
+                GPP_F18,
+                GPP_F19,
+                GPP_F20,
+        };
+
+        return gpio_base2_value(spd_gpios, ARRAY_SIZE(spd_gpios));
+}
+
 void mainboard_memory_init_params(FSPM_UPD *mupd)
 {
 	int spd_idx;
@@ -29,8 +43,7 @@ void mainboard_memory_init_params(FSPM_UPD *mupd)
 	/* Get SPD for soldered RAM SPD (CH A) */
 	gpio_configure_pads(memory_id_gpio_table, ARRAY_SIZE(memory_id_gpio_table));
 
-	spd_idx = gpio_get(GPP_F16) | gpio_get(GPP_F17) << 1 | gpio_get(GPP_F18) << 2 |
-		  gpio_get(GPP_F19) << 3 | gpio_get(GPP_F20) << 4;
+	spd_idx = variant_memory_sku();
 	printk(BIOS_DEBUG, "Detected MEMORY_ID = %d\n", spd_idx);
 	snprintf(spd_name, sizeof(spd_name), "spd_%d.bin", spd_idx);
 	mem_cfg->MemorySpdPtr00    = (uintptr_t)cbfs_map(spd_name, &spd_size);

From 729918628de373aac155c49d0b5fc1201a9fbd33 Mon Sep 17 00:00:00 2001
From: Elyes Haouas <ehaouas@noos.fr>
Date: Sat, 1 Nov 2025 10:00:40 +0000
Subject: [PATCH 2471/3886] 3rdparty/blobs: Update to upstream main

Updating from commit id a0726508b86d:
2025-02-06 17:31:46 +0800 - (soc/mediatek/mt8196: Update SSPM firmware to v4.0)

to commit id 2aefd97c3e01:
2025-10-06 10:54:06 +0800 - (soc/mediatek/mt8196: Update PI_IMG firmware to v1.1)

This brings in 36 new commits.

Change-Id: I7c2ffc22d24f7e615ef081e439646578b4ab7b3a
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89861
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
---
 3rdparty/blobs | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/3rdparty/blobs b/3rdparty/blobs
index a0726508b8..2aefd97c3e 160000
--- a/3rdparty/blobs
+++ b/3rdparty/blobs
@@ -1 +1 @@
-Subproject commit a0726508b86dafe490ff9908274eff408298b15d
+Subproject commit 2aefd97c3e012c87a7dbfd5728c987fe51200b71

From a65d9fe589da92b7b7a65c65c947501768099967 Mon Sep 17 00:00:00 2001
From: Subrata Banik <subratabanik@google.com>
Date: Mon, 10 Nov 2025 13:11:52 +0530
Subject: [PATCH 2472/3886] mb/google/fatcat: Remove
 FSP_UGOP_EARLY_SIGN_OF_LIFE from Lapis

The option FSP_UGOP_EARLY_SIGN_OF_LIFE is not supported for the 'lapis'
and should be removed from its Kconfig selection.

BUG=b:459309919
TEST=Able to see firmware splash screen while booting google/lapis.

Change-Id: Ifcc7f4fe8658cf8d2fdada5a5de84c8ee352861a
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89980
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Derek Huang <derekhuang@google.com>
---
 src/mainboard/google/fatcat/Kconfig | 1 -
 1 file changed, 1 deletion(-)

diff --git a/src/mainboard/google/fatcat/Kconfig b/src/mainboard/google/fatcat/Kconfig
index f78f5e2c11..54ecd5c02c 100644
--- a/src/mainboard/google/fatcat/Kconfig
+++ b/src/mainboard/google/fatcat/Kconfig
@@ -141,7 +141,6 @@ config BOARD_GOOGLE_LAPIS
 	select EC_GOOGLE_CHROMEEC_FW_CONFIG_FROM_UFSC
 	select EC_GOOGLE_CHROMEEC_RTK
 	select EC_GOOGLE_CHROMEEC_LPC_GENERIC_MEMORY_RANGE
-	select FSP_UGOP_EARLY_SIGN_OF_LIFE
 	select HAVE_SLP_S0_GATE
 	select MAINBOARD_HAS_GOOGLE_STRAUSS_KEYBOARD
 

From ace2e540d00327fb9598dcf65551d18a1f07cffb Mon Sep 17 00:00:00 2001
From: Subrata Banik <subratabanik@google.com>
Date: Mon, 10 Nov 2025 13:15:26 +0530
Subject: [PATCH 2473/3886] soc/intel/pantherlake: Update
 CONSOLE_UART_BASE_ADDRESS Kconfig value

The console UART base address for Panther Lake is being updated from
0xfe036000 to 0xfe02c000 (as per FSP version 3272). This correction
ensures the console initializes with the correct UART base address.

TEST=Able to get FSP debug log while building google/fatcat.

Change-Id: Ic123189fb5689318a4940edcfcf206c32e3ccf26
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89981
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Derek Huang <derekhuang@google.com>
---
 src/soc/intel/pantherlake/Kconfig | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/soc/intel/pantherlake/Kconfig b/src/soc/intel/pantherlake/Kconfig
index a0a39bc765..365d8e2736 100644
--- a/src/soc/intel/pantherlake/Kconfig
+++ b/src/soc/intel/pantherlake/Kconfig
@@ -320,7 +320,7 @@ config SOC_INTEL_USB3_DEV_MAX
 
 config CONSOLE_UART_BASE_ADDRESS
 	hex
-	default 0xfe036000
+	default 0xfe02c000
 	depends on INTEL_LPSS_UART_FOR_CONSOLE
 
 # Clock divider parameters for 115200 baud rate

From 971f10d1d7b3d672a3cac641c5a7ffcea2771e33 Mon Sep 17 00:00:00 2001
From: Simon Yang <simon1.yang@intel.com>
Date: Mon, 10 Nov 2025 13:24:53 +0800
Subject: [PATCH 2474/3886] mb/google/var/fatcat/lapis: set custom SVID/SSID to
 load fw for CS35L56

The Lapis board has a Cirrus CS35L56 smart audio amplifier, which needs
board-specific firmware to work properly [1]. The OS uses the SVID/SSID
of the host PCI audio interface to know which firmware file to use.

Set the correct SVID/SSID for Lapis so that the OS can load the correct
firmware for the CS35L56.

[1]: https://www.kernel.org/doc/Documentation/sound/codecs/cs35l56.rst

BUG=b/458444964, b/454824561
TEST="lspci -s 00:1f.3 -x and check value in offset 0x2c-0x2f"

Change-Id: Ie726d3d1c1a42f1961a63d62f3bb8809f6a29d29
Signed-off-by: Simon Yang <simon1.yang@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89978
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
---
 src/mainboard/google/fatcat/variants/lapis/overridetree.cb | 1 +
 1 file changed, 1 insertion(+)

diff --git a/src/mainboard/google/fatcat/variants/lapis/overridetree.cb b/src/mainboard/google/fatcat/variants/lapis/overridetree.cb
index 120935e90c..299483d626 100644
--- a/src/mainboard/google/fatcat/variants/lapis/overridetree.cb
+++ b/src/mainboard/google/fatcat/variants/lapis/overridetree.cb
@@ -119,6 +119,7 @@ chip soc/intel/pantherlake
 	}"
 
 	device domain 0 on
+		subsystemid 0x1043 0x15e4 inherit
 		device ref dtt on
 			chip drivers/intel/dptf
 				## sensor information

From 04d52014262fbab22ca7d41193d7d7e00dc064bb Mon Sep 17 00:00:00 2001
From: Maximilian Brune <maximilian.brune@9elements.com>
Date: Sun, 2 Nov 2025 23:11:22 +0100
Subject: [PATCH 2475/3886] treewide: Fix include guards

Include guards should cover the whole file.

Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: Idbb7b26b31460ad5ac6b8a55a41eb274a8fcec92
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89871
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jakub "Kuba" Czapiga <czapiga@google.com>
---
 src/arch/riscv/include/arch/encoding.h          | 17 +++++++++--------
 src/include/console/cbmem_console.h             |  3 ++-
 src/include/cpu/amd/amd64_save_state.h          |  3 ++-
 src/mainboard/intel/harcuvar/hsio.h             |  3 +--
 src/soc/intel/meteorlake/include/soc/pci_devs.h |  4 ++--
 .../intel/pantherlake/include/soc/pci_devs.h    |  4 ++--
 6 files changed, 18 insertions(+), 16 deletions(-)

diff --git a/src/arch/riscv/include/arch/encoding.h b/src/arch/riscv/include/arch/encoding.h
index 6ab38bb9e7..28f89f87e8 100644
--- a/src/arch/riscv/include/arch/encoding.h
+++ b/src/arch/riscv/include/arch/encoding.h
@@ -214,13 +214,12 @@
 #define rdcycle() read_csr(cycle)
 #define rdinstret() read_csr(instret)
 
-#endif
+#endif // __GNUC__
 
-#endif
+#endif // __ASSEMBLER__
 
-#endif
+#endif // __riscv
 
-#endif
 /* Automatically generated by parse-opcodes.  */
 #ifndef RISCV_ENCODING_H
 #define RISCV_ENCODING_H
@@ -976,7 +975,7 @@
 #define CAUSE_FETCH_PAGE_FAULT 0xc
 #define CAUSE_LOAD_PAGE_FAULT 0xd
 #define CAUSE_STORE_PAGE_FAULT 0xf
-#endif
+#endif // RISCV_ENCODING_H
 #ifdef DECLARE_INSN
 DECLARE_INSN(beq, MATCH_BEQ, MASK_BEQ)
 DECLARE_INSN(bne, MATCH_BNE, MASK_BNE)
@@ -1240,7 +1239,7 @@ DECLARE_INSN(custom3_rs1_rs2, MATCH_CUSTOM3_RS1_RS2, MASK_CUSTOM3_RS1_RS2)
 DECLARE_INSN(custom3_rd, MATCH_CUSTOM3_RD, MASK_CUSTOM3_RD)
 DECLARE_INSN(custom3_rd_rs1, MATCH_CUSTOM3_RD_RS1, MASK_CUSTOM3_RD_RS1)
 DECLARE_INSN(custom3_rd_rs1_rs2, MATCH_CUSTOM3_RD_RS1_RS2, MASK_CUSTOM3_RD_RS1_RS2)
-#endif
+#endif // DECLARE_INSN
 #ifdef DECLARE_CSR
 DECLARE_CSR(fflags, CSR_FFLAGS)
 DECLARE_CSR(frm, CSR_FRM)
@@ -1455,7 +1454,7 @@ DECLARE_CSR(mhpmcounter28h, CSR_MHPMCOUNTER28H)
 DECLARE_CSR(mhpmcounter29h, CSR_MHPMCOUNTER29H)
 DECLARE_CSR(mhpmcounter30h, CSR_MHPMCOUNTER30H)
 DECLARE_CSR(mhpmcounter31h, CSR_MHPMCOUNTER31H)
-#endif
+#endif // DECLARE_CSR
 #ifdef DECLARE_CAUSE
 DECLARE_CAUSE("misaligned fetch", CAUSE_MISALIGNED_FETCH)
 DECLARE_CAUSE("fetch access", CAUSE_FETCH_ACCESS)
@@ -1472,4 +1471,6 @@ DECLARE_CAUSE("machine_ecall", CAUSE_MACHINE_ECALL)
 DECLARE_CAUSE("fetch page fault", CAUSE_FETCH_PAGE_FAULT)
 DECLARE_CAUSE("load page fault", CAUSE_LOAD_PAGE_FAULT)
 DECLARE_CAUSE("store page fault", CAUSE_STORE_PAGE_FAULT)
-#endif
+#endif // DECLARE_CAUSE
+
+#endif // RISCV_CSR_ENCODING_H
diff --git a/src/include/console/cbmem_console.h b/src/include/console/cbmem_console.h
index 84a95dd593..12c3fb83bf 100644
--- a/src/include/console/cbmem_console.h
+++ b/src/include/console/cbmem_console.h
@@ -28,7 +28,8 @@ void cbmemc_copy_in(void *buffer, size_t size);
 
 void cbmem_dump_console_to_uart(void);
 void cbmem_dump_console(void);
-#endif
 
 /* Retrieves the location of the CBMEM Console buffer in SMM mode */
 void smm_get_cbmemc_buffer(void **buffer_out, size_t *size_out);
+
+#endif // _CONSOLE_CBMEM_CONSOLE_H_
diff --git a/src/include/cpu/amd/amd64_save_state.h b/src/include/cpu/amd/amd64_save_state.h
index 08b700afaa..fd0331d919 100644
--- a/src/include/cpu/amd/amd64_save_state.h
+++ b/src/include/cpu/amd/amd64_save_state.h
@@ -2,7 +2,6 @@
 
 #ifndef __AMD64_SAVE_STATE_H__
 #define __AMD64_SAVE_STATE_H__
-#endif
 
 #include <types.h>
 #include <cpu/x86/smm.h>
@@ -111,3 +110,5 @@ typedef struct {
 	u64	rcx;
 	u64	rax;
 } __packed amd64_smm_state_save_area_t;
+
+#endif // __AMD64_SAVE_STATE_H__
diff --git a/src/mainboard/intel/harcuvar/hsio.h b/src/mainboard/intel/harcuvar/hsio.h
index a79decd591..8986024472 100644
--- a/src/mainboard/intel/harcuvar/hsio.h
+++ b/src/mainboard/intel/harcuvar/hsio.h
@@ -606,5 +606,4 @@ const BL_HSIO_INFORMATION harcuvar_hsio_config[] = {
 		   BL_FIA_PCIE_ROOT_PORT_7)} } }
 };
 #endif
-#endif
-/* _MAINBOARD_HSIO_H */
+#endif /* _MAINBOARD_HSIO_H */
diff --git a/src/soc/intel/meteorlake/include/soc/pci_devs.h b/src/soc/intel/meteorlake/include/soc/pci_devs.h
index f52ca6edaa..0e55da24bb 100644
--- a/src/soc/intel/meteorlake/include/soc/pci_devs.h
+++ b/src/soc/intel/meteorlake/include/soc/pci_devs.h
@@ -222,8 +222,6 @@
 #define  PCI_DEV_GBE		_PCI_DEV(ESPI, 6)
 #define  PCI_DEV_NPK		_PCI_DEV(ESPI, 7)
 
-#endif
-
 /* for common code */
 #define MIN_PCH_SLOT		PCI_DEV_SLOT_THC
 #define PCH_DEV_SLOT_CSE	PCI_DEV_SLOT_CSE
@@ -243,3 +241,5 @@
 #define SA_DEVFN_TCSS_DMA1	PCI_DEVFN_TCSS_DMA1
 #define SA_DEV_IGD		PCI_DEV_IGD
 #define SA_DEVFN_IGD		PCI_DEVFN_IGD
+
+#endif // _SOC_METEORLAKE_PCI_DEVS_H_
diff --git a/src/soc/intel/pantherlake/include/soc/pci_devs.h b/src/soc/intel/pantherlake/include/soc/pci_devs.h
index 4d7d2301b0..25468ab39a 100644
--- a/src/soc/intel/pantherlake/include/soc/pci_devs.h
+++ b/src/soc/intel/pantherlake/include/soc/pci_devs.h
@@ -237,8 +237,6 @@
 #define  PCI_DEV_GBE		_PCI_DEV(ESPI, 6)
 #define  PCI_DEV_NPK		_PCI_DEV(ESPI, 7)
 
-#endif
-
 /* for common code */
 #define MIN_PCH_SLOT		PCI_DEV_SLOT_THC
 #define PCH_DEV_SLOT_CSE	PCI_DEV_SLOT_CSE
@@ -258,3 +256,5 @@
 #define SA_DEVFN_TCSS_DMA1	PCI_DEVFN_TCSS_DMA1
 #define SA_DEV_IGD		PCI_DEV_IGD
 #define SA_DEVFN_IGD		PCI_DEVFN_IGD
+
+#endif // _SOC_PANTHERLAKE_PCI_DEVS_H_

From fad0908c5beca82f4a4f73d0e7e7a66c9cba8aa7 Mon Sep 17 00:00:00 2001
From: Kilian Krause <kilian.krause@siemens.com>
Date: Mon, 27 Oct 2025 10:04:56 +0100
Subject: [PATCH 2476/3886] soc/intel/alderlake: Make CPU RP PCIe speed
 configurable

Add PCIe speed configuration for CPU root ports in FSP-M. Previously,
only PCH root port speed could be configured via FSP-S. Since CPU root
ports are initialized in FSP-M, they require configuration during
romstage.

This change uses the pcie_speed_control_to_upd() helper (now available
in the shared header) to convert devicetree PCIE_SPEED_control values
to FSP UPD indices. The configuration respects the pciexp_speed CMOS
option override if present, otherwise uses the devicetree setting.

TEST=Booted on mc_rpl1. Configured CPU RP to different PCIe speeds
(Gen1/Gen2/Gen3) via devicetree and verified correct link speed
negotiation with lspci for each configuration.

Change-Id: If3d871f238e7f063fef01c68cc371ae72ec9642c
Signed-off-by: Kilian Krause <kilian.krause@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89764
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
---
 src/soc/intel/alderlake/romstage/fsp_params.c | 15 +++++++++++++++
 1 file changed, 15 insertions(+)

diff --git a/src/soc/intel/alderlake/romstage/fsp_params.c b/src/soc/intel/alderlake/romstage/fsp_params.c
index 22a37ea84b..041b0fb4e1 100644
--- a/src/soc/intel/alderlake/romstage/fsp_params.c
+++ b/src/soc/intel/alderlake/romstage/fsp_params.c
@@ -55,6 +55,19 @@ static uint8_t clk_src_to_fsp(enum pcie_rp_type type, int rp_number)
 		return CPU_PCIE_BASE + rp_number;
 }
 
+static void configure_cpu_rp_speed(FSP_M_CONFIG *m_cfg,
+			const struct pcie_rp_config *cfg,
+			size_t index)
+{
+	static const char *const speeds[] = {"AUTO", "GEN1", "GEN2", "GEN3", "GEN4"};
+
+	m_cfg->CpuPcieRpPcieSpeed[index] =
+		pcie_speed_control_to_upd(get_uint_option("pciexp_speed",
+			cfg->pcie_rp_pcie_speed));
+	printk(BIOS_DEBUG, "CPU PCIe RP%zu: speed set to %s\n",
+		index + 1, speeds[m_cfg->CpuPcieRpPcieSpeed[index]]);
+}
+
 static void configure_rp_clocks(FSP_M_CONFIG *m_cfg, enum pcie_rp_type type,
 		const struct pcie_rp_config *rp_cfg, size_t index)
 {
@@ -89,6 +102,8 @@ static void pcie_rp_init(FSP_M_CONFIG *m_cfg, uint32_t en_mask, enum pcie_rp_typ
 		if (!(en_mask & BIT(i)))
 			continue;
 		configure_rp_clocks(m_cfg, type, &cfg[i], i);
+		if (type == PCIE_RP_CPU)
+			configure_cpu_rp_speed(m_cfg, &cfg[i], i);
 	}
 }
 

From 29faf77d4a2d386bdc0ca92d61e5a23d8935dbad Mon Sep 17 00:00:00 2001
From: Kilian Krause <kilian.krause@siemens.com>
Date: Mon, 27 Oct 2025 10:13:47 +0100
Subject: [PATCH 2477/3886] mb/siemens/mc_rpl1: Limit CPU RP1 to PCIe Gen2
 speed

Configure CPU root port 1 to operate at PCIe Gen2 speed instead of
the default Gen3. This change addresses signal integrity issues on
the PCIe link that prevent reliable operation at Gen3 speeds.

TEST=Booted on mc_rpl1 and verified CPU RP1 operates at Gen2 speed
with `lspci -vv -s 01:00.0 | grep LnkSta`. Output shows
`LnkSta: Speed 5GT/s (downgraded), Width x2`

Change-Id: I35650d46d4c2ac6942b2e68a4fd23fe875bd0c10
Signed-off-by: Kilian Krause <kilian.krause@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89765
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
---
 src/mainboard/siemens/mc_rpl/variants/mc_rpl1/overridetree.cb | 1 +
 1 file changed, 1 insertion(+)

diff --git a/src/mainboard/siemens/mc_rpl/variants/mc_rpl1/overridetree.cb b/src/mainboard/siemens/mc_rpl/variants/mc_rpl1/overridetree.cb
index 3c26345eae..ae9f1c0ab4 100644
--- a/src/mainboard/siemens/mc_rpl/variants/mc_rpl1/overridetree.cb
+++ b/src/mainboard/siemens/mc_rpl/variants/mc_rpl1/overridetree.cb
@@ -75,6 +75,7 @@ chip soc/intel/alderlake
 			register "cpu_pcie_rp[CPU_RP(1)]" = "{
 				.clk_src = 0,
 				.flags = PCIE_RP_CLK_REQ_UNUSED,
+				.pcie_rp_pcie_speed = SPEED_GEN2,
 			}"
 		end
 		device ref pcie4_1 on

From d62653749cfa2ff4f13d93570363815fa8a3373b Mon Sep 17 00:00:00 2001
From: Karthikeyan Ramasubramanian <kramasub@google.com>
Date: Fri, 31 Oct 2025 14:06:10 -0600
Subject: [PATCH 2478/3886] payloads/libpayload: Support legacy LZ4 compression
 format

Linux kernel images from upstream tree are compressed using legacy LZ4
format and not the modern LZ4 format. Hence support legacy LZ4
compression format to decompress and boot upstream Linux kernel images.
Also add unit test case to verify the currently supported LZ4
compression format as well as legacy LZ4 compression format.

References:
* https://github.com/lz4/lz4

BUG=None
TEST=make tests/liblz4/lz4-test
[==========] tests_liblz4_lz4-test(tests): Running 4 test(s).
[ RUN      ] test_lz4
[       OK ] test_lz4
[ RUN      ] test_lz4_partial_decompression
[       OK ] test_lz4_partial_decompression
[ RUN      ] test_legacy_lz4
[       OK ] test_legacy_lz4
[ RUN      ] test_legacy_lz4_partial_decompression
[       OK ] test_legacy_lz4_partial_decompression
[==========] tests_liblz4_lz4-test(tests): 4 test(s) run.
[  PASSED  ] 4 test(s).

Change-Id: I7e3d407fc313e0937fd8d327840534de60d8c625
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89854
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
---
 payloads/libpayload/include/lz4.h            |   7 +
 payloads/libpayload/liblz4/lz4_wrapper.c     |  54 +++++-
 payloads/libpayload/tests/liblz4/Makefile.mk |   5 +
 payloads/libpayload/tests/liblz4/lz4-test.c  | 170 +++++++++++++++++++
 4 files changed, 230 insertions(+), 6 deletions(-)
 create mode 100644 payloads/libpayload/tests/liblz4/Makefile.mk
 create mode 100644 payloads/libpayload/tests/liblz4/lz4-test.c

diff --git a/payloads/libpayload/include/lz4.h b/payloads/libpayload/include/lz4.h
index d2120a48fc..249afb3a41 100644
--- a/payloads/libpayload/include/lz4.h
+++ b/payloads/libpayload/include/lz4.h
@@ -47,4 +47,11 @@ size_t ulz4fn(const void *src, size_t srcn, void *dst, size_t dstn);
 /* Same as ulz4fn() but does not perform any bounds checks. */
 size_t ulz4f(const void *src, void *dst);
 
+/* Decompresses an Legacy LZ4 image from src to dst, ensuring that it doesn't read
+ * more than srcn bytes and doesn't write more than dstn. Will reliably return an
+ * error if buffer was too small.
+ * Returns amount of decompressed bytes, or 0 on error.
+ */
+size_t ulz4ln(const void *src, size_t srcn, void *dst, size_t dstn);
+
 #endif /* __LZ4_H_ */
diff --git a/payloads/libpayload/liblz4/lz4_wrapper.c b/payloads/libpayload/liblz4/lz4_wrapper.c
index 3d17fe6742..160d5dcb74 100644
--- a/payloads/libpayload/liblz4/lz4_wrapper.c
+++ b/payloads/libpayload/liblz4/lz4_wrapper.c
@@ -74,6 +74,7 @@ typedef uint64_t U64;
 #include "lz4.c.inc"	/* #include for inlining, do not link! */
 
 #define LZ4F_MAGICNUMBER 0x184D2204
+#define LEGACY_MAGICNUMBER 0x184C2102
 
 struct lz4_frame_header {
 	uint32_t magic;
@@ -112,6 +113,14 @@ struct lz4_block_header {
 	/* + uint32_t block_checksum iff has_block_checksum is set */
 } __packed;
 
+/* A wrapper function used by ulz4fn and ulz4ln to inline LZ4_decompress_generic
+   which is critical for performance. */
+static int lz4_wrap(const void *in, void *out, int in_size, int out_size)
+{
+	return LZ4_decompress_generic(in, out, in_size, out_size, endOnInputSize,
+				      full, 0, noDict, out, NULL, 0);
+}
+
 size_t ulz4fn(const void *src, size_t srcn, void *dst, size_t dstn)
 {
 	const void *in = src;
@@ -163,14 +172,10 @@ size_t ulz4fn(const void *src, size_t srcn, void *dst, size_t dstn)
 			else
 				out += size;
 		} else {
-			/* constant folding essential, do not touch params! */
-			int ret = LZ4_decompress_generic(in, out, b.size,
-					dst + dstn - out, endOnInputSize,
-					full, 0, noDict, out, NULL, 0);
+			int ret = lz4_wrap(in, out, b.size, dst + dstn - out);
 			if (ret < 0)
 				break;		/* decompression error */
-			else
-				out += ret;
+			out += ret;
 		}
 
 		in += b.size;
@@ -186,3 +191,40 @@ size_t ulz4f(const void *src, void *dst)
 	/* LZ4 uses signed size parameters, so can't just use ((u32)-1) here. */
 	return ulz4fn(src, 1*GiB, dst, 1*GiB);
 }
+
+size_t ulz4ln(const void *src, size_t srcn, void *dst, size_t dstn)
+{
+	const void *in = src;
+	void *out = dst;
+	size_t out_size = 0;
+
+	if (le32toh(*((const uint32_t *)in)) != LEGACY_MAGICNUMBER)
+		return 0;
+
+	in += sizeof(uint32_t);
+	while (1) {
+		uint32_t block_size;
+
+		if ((size_t)(in - src) == srcn) {
+			out_size = out - dst;	/* decompression is complete */
+			break;
+		}
+
+		if ((size_t)(in - src) + sizeof(block_size) > srcn)
+			break;	/* input overrun */
+
+		block_size = le32toh(*(uint32_t *)in);
+		in += sizeof(block_size);
+
+		if ((size_t)(in - src) + block_size > srcn)
+			break;	/* input overrun */
+
+		int ret = lz4_wrap(in, out, block_size, dst + dstn - out);
+		if (ret < 0)
+			break;		/* decompression error */
+		out += ret;
+		in += block_size;
+	}
+
+	return out_size;
+}
diff --git a/payloads/libpayload/tests/liblz4/Makefile.mk b/payloads/libpayload/tests/liblz4/Makefile.mk
new file mode 100644
index 0000000000..fa5ca8d1b3
--- /dev/null
+++ b/payloads/libpayload/tests/liblz4/Makefile.mk
@@ -0,0 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
+tests-y += lz4-test
+
+lz4-test-srcs += tests/liblz4/lz4-test.c
diff --git a/payloads/libpayload/tests/liblz4/lz4-test.c b/payloads/libpayload/tests/liblz4/lz4-test.c
new file mode 100644
index 0000000000..bbdc0af47d
--- /dev/null
+++ b/payloads/libpayload/tests/liblz4/lz4-test.c
@@ -0,0 +1,170 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <libpayload.h>
+#include <tests/test.h>
+
+#include "../liblz4/lz4_wrapper.c"
+
+/* This macro basically does nothing but suppresses linter messages */
+#define EMPTY_WRAP(...) __VA_ARGS__
+
+#define TEST_RAW_DATA_SIZE sizeof((u8[]){TEST_RAW_DATA})
+/* TEST_RAW_DATA="LLLLLLLLLLLLLLLLZZZZZZZZZZZZZZZZ4444444444444444"
+   echo ${TEST_RAW_DATA} | hexdump -e '1/1 "0x%02x" ", "' -v */
+#define TEST_RAW_DATA EMPTY_WRAP( \
+	0x4c, 0x4c, 0x4c, 0x4c, 0x4c, 0x4c, 0x4c, 0x4c, 0x4c, 0x4c, 0x4c, 0x4c, 0x4c, 0x4c, \
+	0x4c, 0x4c, 0x5a, 0x5a, 0x5a, 0x5a, 0x5a, 0x5a, 0x5a, 0x5a, 0x5a, 0x5a, 0x5a, 0x5a, \
+	0x5a, 0x5a, 0x5a, 0x5a, 0x34, 0x34, 0x34, 0x34, 0x34, 0x34, 0x34, 0x34, 0x34, 0x34, \
+	0x34, 0x34, 0x34, 0x34, 0x34, 0x34, 0x0a)
+
+#define TEST_LZ4_DATA_SIZE sizeof((u8[]){TEST_LZ4_DATA})
+/* echo ${TEST_RAW_DATA} | lz4 -12 --favor-decSpeed -c | \
+   hexdump -e '1/1 "0x%02x" ", "' -v */
+#define TEST_LZ4_DATA EMPTY_WRAP( \
+	0x04, 0x22, 0x4d, 0x18, 0x64, 0x40, 0xa7, 0x15, 0x00, 0x00, 0x00, 0x2a, 0x4c, 0x4c, \
+	0x02, 0x00, 0x2a, 0x5a, 0x5a, 0x02, 0x00, 0x26, 0x34, 0x34, 0x02, 0x00, 0x50, 0x34, \
+	0x34, 0x34, 0x34, 0x0a, 0x00, 0x00, 0x00, 0x00, 0xe1, 0xea, 0x87, 0xfa)
+
+#define TEST_LEGACY_LZ4_DATA_SIZE sizeof((u8[]){TEST_LEGACY_LZ4_DATA})
+/* echo ${TEST_RAW_DATA} | lz4 -l -12 --favor-decSpeed -c | \
+   hexdump -e '1/1 "0x%02x" ", "' -v */
+#define TEST_LEGACY_LZ4_DATA EMPTY_WRAP( \
+	0x02, 0x21, 0x4c, 0x18, 0x12, 0x00, 0x00, 0x00, 0x1b, 0x4c, 0x01, 0x00, 0x1b, 0x5a, \
+	0x01, 0x00, 0x17, 0x34, 0x01, 0x00, 0x50, 0x34, 0x34, 0x34, 0x34, 0x0a)
+
+#define TEST_LARGE_RAW_DATA_SIZE sizeof((u8[]){TEST_LARGE_RAW_DATA})
+/*
+ * LINUX_IMG_PATH=<set to available uncompressed ARM Linux Image>;
+ * hexdump -e '1/1 "0x%02x" ", "' ${LINUX_IMG_PATH} -n 320 -v
+ * Arm Linux kernel image header is 64 bytes long. Size of scratch buffer in one of the
+ * payloads is 256 bytes + Arm Linux kernel image header. Hence 320 bytes.
+ */
+#define TEST_LARGE_RAW_DATA EMPTY_WRAP( \
+	0x4d, 0x5a, 0x40, 0xfa, 0x19, 0x00, 0x7f, 0x14, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+	0x00, 0x00, 0x00, 0x00, 0x72, 0x02, 0x00, 0x00, 0x00, 0x00, 0x0a, 0x00, 0x00, 0x00, \
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+	0x41, 0x52, 0x4d, 0x64, 0x40, 0x00, 0x00, 0x00, 0x50, 0x45, 0x00, 0x00, 0x64, 0xaa, \
+	0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+	0xa0, 0x00, 0x06, 0x02, 0x0b, 0x02, 0x02, 0x14, 0x00, 0x00, 0x3b, 0x02, 0x00, 0x00, \
+	0x36, 0x00, 0x00, 0x00, 0x00, 0x00, 0x04, 0x04, 0x03, 0x02, 0x00, 0x00, 0x01, 0x00, \
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x02, \
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x72, 0x02, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, \
+	0x00, 0x00, 0x0a, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+	0x06, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x2e, 0x74, 0x65, 0x78, \
+	0x74, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3b, 0x02, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, \
+	0x3b, 0x02, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+	0x00, 0x00, 0x00, 0x00, 0x20, 0x00, 0x00, 0x60, 0x2e, 0x64, 0x61, 0x74, 0x61, 0x00, \
+	0x00, 0x00, 0x00, 0x00, 0x36, 0x00, 0x00, 0x00, 0x3c, 0x02, 0x00, 0x0a, 0x2b, 0x00, \
+	0x00, 0x00, 0x3c, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00)
+
+#define TEST_LARGE_LZ4_DATA_SIZE sizeof((u8[]){TEST_LARGE_LZ4_DATA})
+/* head -c 320 ${LINUX_IMG_PATH} | lz4 -12 --favor-decSpeed -c | \
+   hexdump -e '1/1 "0x%02x" ", "' -v */
+#define TEST_LARGE_LZ4_DATA EMPTY_WRAP( \
+	0x04, 0x22, 0x4d, 0x18, 0x64, 0x40, 0xa7, 0x9a, 0x00, 0x00, 0x00, 0xa4, 0x4d, 0x5a, \
+	0x40, 0xfa, 0x19, 0x00, 0x7f, 0x14, 0x00, 0x00, 0x02, 0x00, 0x20, 0x72, 0x02, 0x0c, \
+	0x00, 0x3e, 0x0a, 0x00, 0x00, 0x02, 0x00, 0x07, 0x14, 0x00, 0xf9, 0x00, 0x41, 0x52, \
+	0x4d, 0x64, 0x40, 0x00, 0x00, 0x00, 0x50, 0x45, 0x00, 0x00, 0x64, 0xaa, 0x02, 0x1c, \
+	0x00, 0xf1, 0x00, 0xa0, 0x00, 0x06, 0x02, 0x0b, 0x02, 0x02, 0x14, 0x00, 0x00, 0x3b, \
+	0x02, 0x00, 0x00, 0x36, 0x14, 0x00, 0x77, 0x04, 0x04, 0x03, 0x02, 0x00, 0x00, 0x01, \
+	0x26, 0x00, 0x33, 0x01, 0x00, 0x00, 0x37, 0x00, 0x19, 0x03, 0x3e, 0x00, 0x15, 0x72, \
+	0x28, 0x00, 0x19, 0x0a, 0x31, 0x00, 0x0e, 0x0a, 0x00, 0x04, 0x1c, 0x00, 0x3f, 0x06, \
+	0x00, 0x00, 0x02, 0x00, 0x1e, 0x51, 0x2e, 0x74, 0x65, 0x78, 0x74, 0x0a, 0x00, 0x13, \
+	0x3b, 0x70, 0x00, 0x2c, 0x3b, 0x02, 0x6f, 0x00, 0x90, 0x20, 0x00, 0x00, 0x60, 0x2e, \
+	0x64, 0x61, 0x74, 0x61, 0x0e, 0x00, 0x01, 0xc8, 0x00, 0x52, 0x3c, 0x02, 0x00, 0x0a, \
+	0x2b, 0x08, 0x00, 0x70, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+	0x00, 0xf6, 0xb4, 0xb7, 0x4f)
+
+#define TEST_LARGE_LEGACY_LZ4_DATA_SIZE sizeof((u8[]){TEST_LARGE_LEGACY_LZ4_DATA})
+/* head -c 320 ${LINUX_IMG_PATH} | lz4 -l -12 --favor-decSpeed -c | \
+   hexdump -e '1/1 "0x%02x" ", "' -v */
+#define TEST_LARGE_LEGACY_LZ4_DATA EMPTY_WRAP( \
+	0x02, 0x21, 0x4c, 0x18, 0x93, 0x00, 0x00, 0x00, 0x95, 0x4d, 0x5a, 0x40, 0xfa, 0x19, \
+	0x00, 0x7f, 0x14, 0x00, 0x01, 0x00, 0x20, 0x72, 0x02, 0x06, 0x00, 0x2f, 0x0a, 0x00, \
+	0x01, 0x00, 0x0b, 0xf9, 0x00, 0x41, 0x52, 0x4d, 0x64, 0x40, 0x00, 0x00, 0x00, 0x50, \
+	0x45, 0x00, 0x00, 0x64, 0xaa, 0x02, 0x1c, 0x00, 0xf1, 0x00, 0xa0, 0x00, 0x06, 0x02, \
+	0x0b, 0x02, 0x02, 0x14, 0x00, 0x00, 0x3b, 0x02, 0x00, 0x00, 0x36, 0x14, 0x00, 0x76, \
+	0x04, 0x04, 0x03, 0x02, 0x00, 0x00, 0x01, 0x26, 0x00, 0x00, 0x0c, 0x00, 0x03, 0x37, \
+	0x00, 0x19, 0x03, 0x3e, 0x00, 0x15, 0x72, 0x28, 0x00, 0x1a, 0x0a, 0x31, 0x00, 0x0f, \
+	0x01, 0x00, 0x06, 0x2f, 0x06, 0x00, 0x01, 0x00, 0x1f, 0x51, 0x2e, 0x74, 0x65, 0x78, \
+	0x74, 0x0a, 0x00, 0x13, 0x3b, 0x70, 0x00, 0x2c, 0x3b, 0x02, 0x6f, 0x00, 0x91, 0x20, \
+	0x00, 0x00, 0x60, 0x2e, 0x64, 0x61, 0x74, 0x61, 0x0e, 0x00, 0x00, 0xc8, 0x00, 0x52, \
+	0x3c, 0x02, 0x00, 0x0a, 0x2b, 0x08, 0x00, 0x70, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+	0x00)
+
+static void test_lz4(void **state)
+{
+	const u8 test_src_data[TEST_LZ4_DATA_SIZE] = { TEST_LZ4_DATA };
+	u8 test_dst_data[TEST_RAW_DATA_SIZE] = {0};
+	u8 test_uncompressed_data[TEST_RAW_DATA_SIZE] = { TEST_RAW_DATA };
+	size_t dst_size;
+
+	dst_size = ulz4fn(test_src_data, sizeof(test_src_data),
+			  test_dst_data, sizeof(test_dst_data));
+	assert_int_equal(TEST_RAW_DATA_SIZE, dst_size);
+	assert_memory_equal(test_dst_data, test_uncompressed_data, TEST_RAW_DATA_SIZE);
+}
+
+static void test_lz4_partial_decompression(void **state)
+{
+	const u8 test_src_data[TEST_LARGE_LZ4_DATA_SIZE] = { TEST_LARGE_LZ4_DATA };
+	u8 test_dst_data[TEST_LARGE_RAW_DATA_SIZE / 2] = {0};
+	u8 test_uncompressed_data[TEST_LARGE_RAW_DATA_SIZE] = { TEST_LARGE_RAW_DATA };
+	size_t dst_size;
+
+	ulz4fn(test_src_data, sizeof(test_src_data),
+			  test_dst_data, sizeof(test_dst_data));
+	for (dst_size = 0; dst_size < sizeof(test_dst_data); dst_size++) {
+		if (test_dst_data[dst_size] != test_uncompressed_data[dst_size])
+			break;
+	}
+	assert_in_range(dst_size, TEST_LARGE_RAW_DATA_SIZE / 4, TEST_LARGE_RAW_DATA_SIZE);
+}
+
+static void test_legacy_lz4(void **state)
+{
+	const u8 test_src_data[TEST_LEGACY_LZ4_DATA_SIZE] = { TEST_LEGACY_LZ4_DATA };
+	u8 test_dst_data[TEST_RAW_DATA_SIZE] = {0};
+	u8 test_uncompressed_data[TEST_RAW_DATA_SIZE] = { TEST_RAW_DATA };
+	size_t dst_size;
+
+	dst_size = ulz4ln(test_src_data, sizeof(test_src_data),
+			  test_dst_data, sizeof(test_dst_data));
+	assert_int_equal(TEST_RAW_DATA_SIZE, dst_size);
+	assert_memory_equal(test_dst_data, test_uncompressed_data, TEST_RAW_DATA_SIZE);
+}
+
+static void test_legacy_lz4_partial_decompression(void **state)
+{
+	const u8 test_src_data[TEST_LARGE_LEGACY_LZ4_DATA_SIZE] = { TEST_LARGE_LEGACY_LZ4_DATA };
+	u8 test_dst_data[TEST_LARGE_RAW_DATA_SIZE / 2] = {0};
+	u8 test_uncompressed_data[TEST_LARGE_RAW_DATA_SIZE] = { TEST_LARGE_RAW_DATA };
+	size_t dst_size;
+
+	ulz4ln(test_src_data, sizeof(test_src_data),
+			  test_dst_data, sizeof(test_dst_data));
+	for (dst_size = 0; dst_size < sizeof(test_dst_data); dst_size++) {
+		if (test_dst_data[dst_size] != test_uncompressed_data[dst_size])
+			break;
+	}
+	assert_in_range(dst_size, TEST_LARGE_RAW_DATA_SIZE / 4, TEST_LARGE_RAW_DATA_SIZE);
+}
+
+int main(void)
+{
+	const struct CMUnitTest tests[] = {
+		cmocka_unit_test(test_lz4),
+		cmocka_unit_test(test_lz4_partial_decompression),
+		cmocka_unit_test(test_legacy_lz4),
+		cmocka_unit_test(test_legacy_lz4_partial_decompression),
+	};
+
+	return lp_run_group_tests(tests, NULL, NULL);
+}

From 9dc35142aceecb15eea1c0211d0d325a6c0ddff6 Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Fri, 31 Oct 2025 15:38:35 -0500
Subject: [PATCH 2479/3886] soc/amd/stoneyridge: Generate SATA ACPI registers
 at runtime

Convert SATA controller ACPI OperationRegion and Field definitions from
static ASL code to runtime-generated acpigen code. This allows the SATA
registers (STB5, SB5, and port fields P0ER-P3PR) to be conditionally
included in ACPI tables only when the SATA controller (device 00:11.0)
is enabled in the devicetree.

Including them unconditionally when the SATA PCI device is disabled
causes Windows to BSOD (ACPI BIOS ERROR), since the OpRegion references
a non-existent device.

Changes:
- Move SATA OperationRegion generation to sata.c using acpigen APIs
- Remove static SATA fields from acpi/pci_int.asl
- Add stoneyridge_sata_ops with acpi_fill_ssdt callback
- Update chipset_st.cb and chipset_cz.cb to use stoneyridge_sata_ops
- Remove Kconfig for SoC common SATA code, since no longer used

This reduces ACPI table size when SATA is disabled and properly scopes
SATA registers to the SATA device.

TEST=boot Win11 on google/liara without a BSOD

Change-Id: I6e7a9a60e3622368eac83c36efd384c8d92c2b05
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89855
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
---
 src/soc/amd/stoneyridge/Kconfig          |   1 -
 src/soc/amd/stoneyridge/acpi/pci_int.asl |  78 +-------
 src/soc/amd/stoneyridge/chipset_cz.cb    |   2 +-
 src/soc/amd/stoneyridge/chipset_st.cb    |   2 +-
 src/soc/amd/stoneyridge/sata.c           | 220 ++++++++++++++++++++++-
 5 files changed, 227 insertions(+), 76 deletions(-)

diff --git a/src/soc/amd/stoneyridge/Kconfig b/src/soc/amd/stoneyridge/Kconfig
index 1d236363a6..b8c04b59b6 100644
--- a/src/soc/amd/stoneyridge/Kconfig
+++ b/src/soc/amd/stoneyridge/Kconfig
@@ -36,7 +36,6 @@ config SOC_AMD_STONEYRIDGE
 	select SOC_AMD_COMMON_BLOCK_PCI
 	select SOC_AMD_COMMON_BLOCK_PM
 	select SOC_AMD_COMMON_BLOCK_PSP_GEN1
-	select SOC_AMD_COMMON_BLOCK_SATA
 	select SOC_AMD_COMMON_BLOCK_SMBUS
 	select SOC_AMD_COMMON_BLOCK_SMI
 	select SOC_AMD_COMMON_BLOCK_SMM
diff --git a/src/soc/amd/stoneyridge/acpi/pci_int.asl b/src/soc/amd/stoneyridge/acpi/pci_int.asl
index e905c9738c..8d76c58f9e 100644
--- a/src/soc/amd/stoneyridge/acpi/pci_int.asl
+++ b/src/soc/amd/stoneyridge/acpi/pci_int.asl
@@ -5,8 +5,6 @@
 		 * ((bus number + 1) * ((device number * 8) * 4096)) + register offset
 		 * The 8 comes from 8 functions per device, and 4096 bytes per function config space
 		*/
-		Offset(0x00088024),	/* Byte offset to SATA register 24h - Bus 0, Device 17, Function 0 */
-		STB5, 32,
 		Offset(0x00098042),	/* Byte offset to OHCI0 register 42h - Bus 0, Device 19, Function 0 */
 		PT0D, 1,
 		PT1D, 1,
@@ -30,76 +28,12 @@
 		P92E, 1,		/* Port92 decode enable */
 	}
 
-	OperationRegion(SB5, SystemMemory, STB5, 0x1000)
-		Field(SB5, AnyAcc, NoLock, Preserve){
-		/* Port 0 */
-		Offset(0x120),		/* Port 0 Task file status */
-		P0ER, 1,
-		, 2,
-		P0DQ, 1,
-		, 3,
-		P0BY, 1,
-		Offset(0x128),		/* Port 0 Serial ATA status */
-		P0DD, 4,
-		, 4,
-		P0IS, 4,
-		Offset(0x12c),		/* Port 0 Serial ATA control */
-		P0DI, 4,
-		Offset(0x130),		/* Port 0 Serial ATA error */
-		, 16,
-		P0PR, 1,
-
-		/* Port 1 */
-		offset(0x1a0),		/* Port 1 Task file status */
-		P1ER, 1,
-		, 2,
-		P1DQ, 1,
-		, 3,
-		P1BY, 1,
-		Offset(0x1a8),		/* Port 1 Serial ATA status */
-		P1DD, 4,
-		, 4,
-		P1IS, 4,
-		Offset(0x1ac),		/* Port 1 Serial ATA control */
-		P1DI, 4,
-		Offset(0x1b0),		/* Port 1 Serial ATA error */
-		, 16,
-		P1PR, 1,
-
-		/* Port 2 */
-		Offset(0x220),		/* Port 2 Task file status */
-		P2ER, 1,
-		, 2,
-		P2DQ, 1,
-		, 3,
-		P2BY, 1,
-		Offset(0x228),		/* Port 2 Serial ATA status */
-		P2DD, 4,
-		, 4,
-		P2IS, 4,
-		Offset(0x22c),		/* Port 2 Serial ATA control */
-		P2DI, 4,
-		Offset(0x230),		/* Port 2 Serial ATA error */
-		, 16,
-		P2PR, 1,
-
-		/* Port 3 */
-		Offset(0x2a0),		/* Port 3 Task file status */
-		P3ER, 1,
-		, 2,
-		P3DQ, 1,
-		, 3,
-		P3BY, 1,
-		Offset(0x2a8),		/* Port 3 Serial ATA status */
-		P3DD, 4,
-		, 4,
-		P3IS, 4,
-		Offset(0x2aC),		/* Port 3 Serial ATA control */
-		P3DI, 4,
-		Offset(0x2b0),		/* Port 3 Serial ATA error */
-		, 16,
-		P3PR, 1,
-	}
+	/*
+	* SATA OperationRegion (STB5, SB5) and port Fields (P0ER, P0DQ, etc.)
+	* are now generated at runtime via acpigen in acpi_sata.c
+	* This allows the SATA registers to only be included when the SATA
+	* controller (device 00:11.0) is enabled in the devicetree.
+	*/
 
 	Name(IRQB, ResourceTemplate(){
 		IRQ(Level,ActiveLow,Shared){15}
diff --git a/src/soc/amd/stoneyridge/chipset_cz.cb b/src/soc/amd/stoneyridge/chipset_cz.cb
index d45c6d7d56..3101114e8f 100644
--- a/src/soc/amd/stoneyridge/chipset_cz.cb
+++ b/src/soc/amd/stoneyridge/chipset_cz.cb
@@ -26,7 +26,7 @@ chip soc/amd/stoneyridge
 		device pci 09.0 alias hda_bridge off end # host audio bridge
 		device pci 09.2 alias hda off end # main HD Audio Controller
 		device pci 10.0 alias xhci off ops stoneyridge_usb_ops end
-		device pci 11.0 alias sata off ops amd_sata_ops end
+		device pci 11.0 alias sata off ops stoneyridge_sata_ops end
 		device pci 12.0 alias ehci off ops stoneyridge_usb_ops end
 		device pci 14.0 alias smbus on ops amd_smbus_ops end # primary FCH function
 		device pci 14.3 alias lpc_bridge on ops amd_lpc_ops end
diff --git a/src/soc/amd/stoneyridge/chipset_st.cb b/src/soc/amd/stoneyridge/chipset_st.cb
index 0039ed97a7..e404b655de 100644
--- a/src/soc/amd/stoneyridge/chipset_st.cb
+++ b/src/soc/amd/stoneyridge/chipset_st.cb
@@ -20,7 +20,7 @@ chip soc/amd/stoneyridge
 		device pci 09.0 alias hda_bridge off end # host audio bridge
 		device pci 09.2 alias hda off end # main HD Audio Controller
 		device pci 10.0 alias xhci off ops stoneyridge_usb_ops end
-		device pci 11.0 alias sata off ops amd_sata_ops end
+		device pci 11.0 alias sata off ops stoneyridge_sata_ops end
 		device pci 12.0 alias ehci off ops stoneyridge_usb_ops end
 		device pci 14.0 alias smbus on ops amd_smbus_ops end # primary FCH function
 		device pci 14.3 alias lpc_bridge on ops amd_lpc_ops end
diff --git a/src/soc/amd/stoneyridge/sata.c b/src/soc/amd/stoneyridge/sata.c
index fb2f7acd91..110b23b0f1 100644
--- a/src/soc/amd/stoneyridge/sata.c
+++ b/src/soc/amd/stoneyridge/sata.c
@@ -1,9 +1,12 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
+#include <acpi/acpi_device.h>
+#include <acpi/acpigen.h>
+#include <amdblocks/sata.h>
+#include <console/console.h>
 #include <device/device.h>
 #include <device/pci.h>
 #include <device/pci_ops.h>
-#include <amdblocks/sata.h>
 #include <soc/southbridge.h>
 
 void soc_enable_sata_features(struct device *dev)
@@ -30,4 +33,219 @@ void soc_enable_sata_features(struct device *dev)
 	temp = pci_read_config32(dev, SATA_MISC_CONTROL_REG);
 	temp &= ~SATA_MISC_SUBCLASS_WREN;
 	pci_write_config32(dev, SATA_MISC_CONTROL_REG, temp);
+}
+
+#if CONFIG(HAVE_ACPI_TABLES)
+
+/*
+ * Generate ACPI SATA OperationRegion and Fields for port status
+ * This is only generated if the SATA device (00:11.0) is enabled
+ */
+static void sata_acpi_fill_ssdt(const struct device *dev)
+{
+	const char *scope;
+
+	if (!dev->enabled)
+		return;
+
+	/* First generate the standard PCI device info */
+	acpi_device_write_pci_dev(dev);
+
+	/* Get the scope for the SATA device */
+	scope = acpi_device_path(dev);
+	if (!scope)
+		return;
+
+	acpigen_write_scope(scope);
+
+	/*
+	 * Generate Field in PCFG OperationRegion for SATA BAR5 register
+	 * PCFG is the PCI config space OperationRegion defined elsewhere
+	 *
+	 * Field(PCFG, ByteAcc, NoLock, Preserve) {
+	 *	Offset(0x00088024),
+	 *	STB5, 32,
+	 * }
+	 *
+	 */
+	struct fieldlist sata_pcfg_field[] = {
+		FIELDLIST_OFFSET(0x00088024),  /* SATA device register 24h */
+		FIELDLIST_NAMESTR("STB5", 32), /* SATA BAR5 (ABAR) */
+	};
+	acpigen_write_field("PCFG", sata_pcfg_field, ARRAY_SIZE(sata_pcfg_field),
+			    FIELD_BYTEACC | FIELD_NOLOCK | FIELD_PRESERVE);
+
+	/*
+	 * Generate OperationRegion for SATA AHCI memory space
+	 * This maps to the BAR5 (ABAR) memory region:
+	 *
+	 * OperationRegion(SB5, SystemMemory, STB5, 0x1000)
+	 *
+	 */
+	acpigen_emit_ext_op(OPREGION_OP);
+	acpigen_emit_namestring("SB5");
+	acpigen_emit_byte(SYSTEMMEMORY);
+	acpigen_emit_namestring("STB5");  /* Reference to the STB5 field defined above */
+	acpigen_write_integer(0x1000);
+
+	/*
+	 * Generate Field in SB5 OperationRegion for SATA port registers
+	 * These fields allow access to AHCI port status registers:
+	 *
+	 * Field(SB5, AnyAcc, NoLock, Preserve) {
+	 *	Offset(0x120),
+	 *	P0ER, 1,
+	 *	, 2,
+	 *	P0DQ, 1,
+	 *	, 3,
+	 *	P0BY, 1,
+	 *	Offset(0x128),
+	 *	P0DD, 4,
+	 *	, 4,
+	 *	P0IS, 4,
+	 *	Offset(0x12c),
+	 *	P0DI, 4,
+	 *	Offset(0x130),
+	 *	, 16,
+	 *	P0PR, 1,
+	 *	Offset(0x1a0),
+	 *	P1ER, 1,
+	 *	, 2,
+	 *	P1DQ, 1,
+	 *	, 3,
+	 *	P1BY, 1,
+	 *	Offset(0x1a8),
+	 *	P1DD, 4,
+	 *	, 4,
+	 *	P1IS, 4,
+	 *	Offset(0x1ac),
+	 *	P1DI, 4,
+	 *	Offset(0x1b0),
+	 *	, 16,
+	 *	P1PR, 1,
+	 *	Offset(0x220),
+	 *	P2ER, 1,
+	 *	, 2,
+	 *	P2DQ, 1,
+	 *	, 3,
+	 *	P2BY, 1,
+	 *	Offset(0x228),
+	 *	P2DD, 4,
+	 *	, 4,
+	 *	P2IS, 4,
+	 *	Offset(0x22c),
+	 *	P2DI, 4,
+	 *	Offset(0x230),
+	 *	, 16,
+	 *	P2PR, 1,
+	 *	Offset(0x2a0),
+	 *	P3ER, 1,
+	 *	, 2,
+	 *	P3DQ, 1,
+	 *	, 3,
+	 *	P3BY, 1,
+	 *	Offset(0x2a8),
+	 *	P3DD, 4,
+	 *	, 4,
+	 *	P3IS, 4,
+	 *	Offset(0x2ac),
+	 *	P3DI, 4,
+	 *	Offset(0x2b0),
+	 *	, 16,
+	 *	P3PR, 1,
+	 * }
+	 *
+	 */
+	struct fieldlist sata_port_fields[] = {
+		/* Port 0 - offset 0x120 */
+		FIELDLIST_OFFSET(0x120),
+		FIELDLIST_NAMESTR("P0ER", 1),  /* Error bit */
+		FIELDLIST_RESERVED(2),
+		FIELDLIST_NAMESTR("P0DQ", 1),  /* Data request */
+		FIELDLIST_RESERVED(3),
+		FIELDLIST_NAMESTR("P0BY", 1),  /* Busy */
+		FIELDLIST_OFFSET(0x128),
+		FIELDLIST_NAMESTR("P0DD", 4),  /* Device detection */
+		FIELDLIST_RESERVED(4),
+		FIELDLIST_NAMESTR("P0IS", 4),  /* Interface speed */
+		FIELDLIST_OFFSET(0x12c),
+		FIELDLIST_NAMESTR("P0DI", 4),  /* Device idle */
+		FIELDLIST_OFFSET(0x130),
+		FIELDLIST_RESERVED(16),
+		FIELDLIST_NAMESTR("P0PR", 1),  /* Port ready */
+
+		/* Port 1 - offset 0x1a0 */
+		FIELDLIST_OFFSET(0x1a0),
+		FIELDLIST_NAMESTR("P1ER", 1),
+		FIELDLIST_RESERVED(2),
+		FIELDLIST_NAMESTR("P1DQ", 1),
+		FIELDLIST_RESERVED(3),
+		FIELDLIST_NAMESTR("P1BY", 1),
+		FIELDLIST_OFFSET(0x1a8),
+		FIELDLIST_NAMESTR("P1DD", 4),
+		FIELDLIST_RESERVED(4),
+		FIELDLIST_NAMESTR("P1IS", 4),
+		FIELDLIST_OFFSET(0x1ac),
+		FIELDLIST_NAMESTR("P1DI", 4),
+		FIELDLIST_OFFSET(0x1b0),
+		FIELDLIST_RESERVED(16),
+		FIELDLIST_NAMESTR("P1PR", 1),
+
+		/* Port 2 - offset 0x220 */
+		FIELDLIST_OFFSET(0x220),
+		FIELDLIST_NAMESTR("P2ER", 1),
+		FIELDLIST_RESERVED(2),
+		FIELDLIST_NAMESTR("P2DQ", 1),
+		FIELDLIST_RESERVED(3),
+		FIELDLIST_NAMESTR("P2BY", 1),
+		FIELDLIST_OFFSET(0x228),
+		FIELDLIST_NAMESTR("P2DD", 4),
+		FIELDLIST_RESERVED(4),
+		FIELDLIST_NAMESTR("P2IS", 4),
+		FIELDLIST_OFFSET(0x22c),
+		FIELDLIST_NAMESTR("P2DI", 4),
+		FIELDLIST_OFFSET(0x230),
+		FIELDLIST_RESERVED(16),
+		FIELDLIST_NAMESTR("P2PR", 1),
+
+		/* Port 3 - offset 0x2a0 */
+		FIELDLIST_OFFSET(0x2a0),
+		FIELDLIST_NAMESTR("P3ER", 1),
+		FIELDLIST_RESERVED(2),
+		FIELDLIST_NAMESTR("P3DQ", 1),
+		FIELDLIST_RESERVED(3),
+		FIELDLIST_NAMESTR("P3BY", 1),
+		FIELDLIST_OFFSET(0x2a8),
+		FIELDLIST_NAMESTR("P3DD", 4),
+		FIELDLIST_RESERVED(4),
+		FIELDLIST_NAMESTR("P3IS", 4),
+		FIELDLIST_OFFSET(0x2ac),
+		FIELDLIST_NAMESTR("P3DI", 4),
+		FIELDLIST_OFFSET(0x2b0),
+		FIELDLIST_RESERVED(16),
+		FIELDLIST_NAMESTR("P3PR", 1),
+	};
+	acpigen_write_field("SB5", sata_port_fields, ARRAY_SIZE(sata_port_fields),
+			    FIELD_ANYACC | FIELD_NOLOCK | FIELD_PRESERVE);
+
+	acpigen_pop_len(); /* Scope */
+}
+
+static const char *sata_acpi_name(const struct device *dev)
+{
+	return "STCR";
+}
+
+#endif /* CONFIG(HAVE_ACPI_TABLES) */
+
+struct device_operations stoneyridge_sata_ops = {
+	.read_resources		= pci_dev_read_resources,
+	.set_resources		= pci_dev_set_resources,
+	.enable_resources	= pci_dev_enable_resources,
+	.init			= soc_enable_sata_features,
+	.ops_pci		= &pci_dev_ops_pci,
+#if CONFIG(HAVE_ACPI_TABLES)
+	.acpi_name		= sata_acpi_name,
+	.acpi_fill_ssdt		= sata_acpi_fill_ssdt,
+#endif
 };

From 773997c92d9680da272730e5028caa93d361fcfc Mon Sep 17 00:00:00 2001
From: Maximilian Brune <maximilian.brune@9elements.com>
Date: Fri, 7 Nov 2025 18:43:28 +0100
Subject: [PATCH 2480/3886] drivers/intel/touch: Avoid returning undefined
 pointer

Currently we may return an undefined pointer called
`none_driver_config` since stack variables are not by default
initialized to 0/NULL.
This also causes an issue when updating to a clang version 21.1.5 from
version 18.1.8, since it complains about this very issue.

returning NULL is fine, since the macros in this file actually depend on
it to figure out where to get the config from.

Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: I7b719ca9fd41409375f635b1dcddbc5796b48fe7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89940
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
---
 src/drivers/intel/touch/chip.h  |  1 -
 src/drivers/intel/touch/touch.c | 20 ++++++++++----------
 2 files changed, 10 insertions(+), 11 deletions(-)

diff --git a/src/drivers/intel/touch/chip.h b/src/drivers/intel/touch/chip.h
index 9f3ad3f525..69b58f83aa 100644
--- a/src/drivers/intel/touch/chip.h
+++ b/src/drivers/intel/touch/chip.h
@@ -178,7 +178,6 @@ enum intel_touch_device {
 	TH_SENSOR_GOOGLE,   /* ELAN9006 for SPI and ELAN6918 for I2C */
 	TH_SENSOR_HYNITRON, /* NYITRON for I2C only  */
 	TH_SENSOR_GENERIC,  /* for device properity thru devicetree */
-	TH_SENSOR_MAX
 };
 
 /*
diff --git a/src/drivers/intel/touch/touch.c b/src/drivers/intel/touch/touch.c
index b070c47d7f..5bca4173c6 100644
--- a/src/drivers/intel/touch/touch.c
+++ b/src/drivers/intel/touch/touch.c
@@ -39,17 +39,17 @@ __weak const struct intel_thc_hidspi_info *soc_get_thc_hidspi_info(void) { retur
 static const struct drivers_intel_touch_config *get_driver_config(const struct device *dev)
 
 {
-	const struct drivers_intel_touch_config none_driver_config;
 	const struct drivers_intel_touch_config *config = dev->chip_info;
-	const struct drivers_intel_touch_config *devices[TH_SENSOR_MAX] = {
-		[TH_SENSOR_NONE] = &none_driver_config,
-		[TH_SENSOR_WACOM] = &wacom_touch_config,
-		[TH_SENSOR_ELAN] = &elan_touch_config,
-		[TH_SENSOR_GOOGLE] = &google_touch_config,
-		[TH_SENSOR_HYNITRON] = &hynitron_touch_config,
-		[TH_SENSOR_GENERIC] = config
-	};
-	return devices[config->connected_device];
+	switch (config->connected_device) {
+	case TH_SENSOR_WACOM:    return &wacom_touch_config;
+	case TH_SENSOR_ELAN:     return &elan_touch_config;
+	case TH_SENSOR_GOOGLE:   return &google_touch_config;
+	case TH_SENSOR_HYNITRON: return &hynitron_touch_config;
+	case TH_SENSOR_GENERIC:  return config;
+	case TH_SENSOR_NONE:     return NULL;
+	/* no default so that we get an error in case someone forgets to add a case here */
+	}
+	return NULL;
 }
 
 /* Use only Device-tree definition. */

From c197643d44f36b6758811a7e0c7bc8dade33acdb Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Wed, 12 Nov 2025 14:18:48 -0600
Subject: [PATCH 2481/3886] drivers/intel/gma/acpi: Add power management
 methods for GFX0

Add ACPI power state methods (_PS0, _PS3, _S0W, _S3D) to the GFX0
device definition to fix VIDEO_TDR_FAILURE 0x116 errors when
resuming from S3 sleep under Windows on modern Intel platforms
(TGL and newer).

Windows requires these methods to properly manage GPU power states
during sleep/resume cycles. Without them, Windows cannot determine
the correct power state transitions, leading to display driver
timeouts on resume.

The methods are implemented as no-ops since integrated graphics
power is managed by the platform, but Windows needs the method
definitions to properly initialize and restore the GPU after S3
resume.

TEST=build/boot starlabs/starlite_adl, verify S3 resume from
Windows works properly without a VIDEO_TDR_FAILURE BSOD.

Change-Id: Ib3f8060dee3281c2281d4e719be9aff9e0239b49
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90013
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/drivers/intel/gma/acpi/gfx.asl | 30 ++++++++++++++++++++++++++++++
 1 file changed, 30 insertions(+)

diff --git a/src/drivers/intel/gma/acpi/gfx.asl b/src/drivers/intel/gma/acpi/gfx.asl
index 109543fd6f..b1f090cce5 100644
--- a/src/drivers/intel/gma/acpi/gfx.asl
+++ b/src/drivers/intel/gma/acpi/gfx.asl
@@ -3,4 +3,34 @@
 Device (GFX0)
 {
 	Name (_ADR, 0x00020000)
+
+	/*
+	 * Power state methods required for proper S3 resume support.
+	 * Windows needs these to properly manage GPU power states during
+	 * sleep/resume cycles.
+	 */
+
+	/* Power state D0 (fully on) - called when device is powered on */
+	Method (_PS0, 0, NotSerialized)
+	{
+		/* Integrated graphics power is managed by the platform */
+	}
+
+	/* Power state D3 (off) - called when device is powered off */
+	Method (_PS3, 0, NotSerialized)
+	{
+		/* Integrated graphics power is managed by the platform */
+	}
+
+	/* Deepest sleep state from S0 - D3hot */
+	Method (_S0W, 0x0, NotSerialized)
+	{
+		Return (0x03)  /* D3hot */
+	}
+
+	/* Deepest sleep state from S3 - D3hot */
+	Method (_S3D, 0x0, NotSerialized)
+	{
+		Return (0x03)  /* D3hot - device can enter D3hot during S3 */
+	}
 }

From b535db8f1e3ec4b0af26c0013bd0e7ada3e43e53 Mon Sep 17 00:00:00 2001
From: Subrata Banik <subratabanik@google.com>
Date: Thu, 13 Nov 2025 09:08:29 +0000
Subject: [PATCH 2482/3886] soc/intel/cmn/usb: Add helper macro for USB 3.0
 port TX configuration
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Introduce the `USB3_PORT_TX_CFG` macro to simplify the definition of
`usb3_port_config` structures.

This macro allows platform code to easily configure the Transmit
De-emphasis (`tx_de_emp`) value for a specific USB 3.0 port (identified
by `ocpin`).

This improves readability and reduces boilerplate when tuning signal
integrity settings for different USB ports on the board.

TEST=Able to build and boot google/kinmen.

Change-Id: I42565e2c573dfcff244a81bf7bcb9749eca52c05
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90021
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
---
 src/soc/intel/common/block/include/intelblocks/usb.h | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/src/soc/intel/common/block/include/intelblocks/usb.h b/src/soc/intel/common/block/include/intelblocks/usb.h
index 44094d29fe..e334cf5b8d 100644
--- a/src/soc/intel/common/block/include/intelblocks/usb.h
+++ b/src/soc/intel/common/block/include/intelblocks/usb.h
@@ -137,6 +137,13 @@ struct usb3_port_config {
 	.tx_downscale_amp = 0x00, \
 }
 
+#define USB3_PORT_TX_CFG(pin, de_emp) { \
+	.enable           = 1, \
+	.ocpin            = (pin), \
+	.tx_de_emp        = (de_emp), \
+	.tx_downscale_amp = 0x00, \
+}
+
 struct tcss_port_config {
 	uint8_t enable;
 	uint8_t ocpin;

From 04778ddd3814f8764eec8b0f43150a07d9356221 Mon Sep 17 00:00:00 2001
From: Maximilian Brune <maximilian.brune@9elements.com>
Date: Fri, 7 Nov 2025 21:41:12 +0100
Subject: [PATCH 2483/3886] drivers/option/cfr: Remove old sm_object from
 constructor

There is no reason I can think to also pass the old object into the
constructor considering that the new objects contains the exact same
contents during that call (it's copied over a few lines above).

Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: Idd5b34134b6064c19266448b551248eb29e097fe
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89957
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
---
 Documentation/drivers/cfr_internal.md            |  2 +-
 src/drivers/option/cfr.c                         |  2 +-
 src/drivers/option/cfr_frontend.h                |  2 +-
 src/mainboard/lenovo/sklkbl_thinkpad/cfr.c       |  2 +-
 src/mainboard/prodrive/atlas/cfr.c               | 16 ++++++++--------
 src/mainboard/starlabs/common/cfr/cfr.c          |  4 +---
 .../starlabs/common/include/common/cfr.h         |  2 +-
 src/mainboard/starlabs/starlite_adl/cfr.c        |  2 +-
 8 files changed, 15 insertions(+), 17 deletions(-)

diff --git a/Documentation/drivers/cfr_internal.md b/Documentation/drivers/cfr_internal.md
index 6aa896ed68..82f5bda04c 100644
--- a/Documentation/drivers/cfr_internal.md
+++ b/Documentation/drivers/cfr_internal.md
@@ -78,7 +78,7 @@ coreboot table.
 EMI eeprom.
 
 ```
-static void update_serial(const struct sm_object *obj, struct sm_object *new)
+static void update_serial(struct sm_object *new)
 {
 	new->sm_varchar.default_value = get_emi_eeprom_vpd()->serial_number;
 }
diff --git a/src/drivers/option/cfr.c b/src/drivers/option/cfr.c
index a332d906d6..d338648029 100644
--- a/src/drivers/option/cfr.c
+++ b/src/drivers/option/cfr.c
@@ -347,8 +347,8 @@ static uint32_t sm_write_object(char *current, const struct sm_object *sm_obj)
 	/* Invoke callback to update fields */
 	if (sm_obj->ctor) {
 		memcpy(&sm_obj_copy, sm_obj, sizeof(*sm_obj));
-		sm_obj->ctor(sm_obj, &sm_obj_copy);
 
+		sm_obj->ctor(&sm_obj_copy);
 		assert(sm_obj->kind == sm_obj_copy.kind);
 		sm_obj = (const struct sm_object *)&sm_obj_copy;
 	}
diff --git a/src/drivers/option/cfr_frontend.h b/src/drivers/option/cfr_frontend.h
index 3beaaa7690..4a154be985 100644
--- a/src/drivers/option/cfr_frontend.h
+++ b/src/drivers/option/cfr_frontend.h
@@ -82,7 +82,7 @@ struct sm_object {
 	const struct sm_object *dep;
 	const uint32_t *dep_values;
 	const uint32_t num_dep_values;
-	void (*ctor)(const struct sm_object *obj, struct sm_object *new);	/* Called on object creation */
+	void (*ctor)(struct sm_object *new);	/* Called on object creation */
 	union {
 		struct sm_obj_enum sm_enum;
 		struct sm_obj_number sm_number;
diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/cfr.c b/src/mainboard/lenovo/sklkbl_thinkpad/cfr.c
index 45f344b939..8f282facdd 100644
--- a/src/mainboard/lenovo/sklkbl_thinkpad/cfr.c
+++ b/src/mainboard/lenovo/sklkbl_thinkpad/cfr.c
@@ -9,7 +9,7 @@
 #include <static.h>
 
 /* Hide the dGPU CFR entry if dGPU not present */
-static void update_dgpu(const struct sm_object *obj, struct sm_object *new)
+static void update_dgpu(struct sm_object *new)
 {
 	struct device *dgpu = DEV_PTR(dgpu);
 	if (!dgpu || !dgpu->enabled) {
diff --git a/src/mainboard/prodrive/atlas/cfr.c b/src/mainboard/prodrive/atlas/cfr.c
index f5700e2ba0..b275bd23c8 100644
--- a/src/mainboard/prodrive/atlas/cfr.c
+++ b/src/mainboard/prodrive/atlas/cfr.c
@@ -12,23 +12,23 @@
 
 #include "vpd.h"
 
-static void update_rt_perf(const struct sm_object *obj, struct sm_object *new)
+static void update_rt_perf(struct sm_object *new)
 {
 	const bool rt_perf = get_emi_eeprom_vpd()->profile == ATLAS_PROF_REALTIME_PERFORMANCE;
 
 	if (!rt_perf)
 		return;
 
-	if (obj->kind == SM_OBJ_BOOL) {
+	if (new->kind == SM_OBJ_BOOL) {
 		new->sm_bool.flags = CFR_OPTFLAG_SUPPRESS;
 		new->sm_bool.default_value = false;
-	} else if (obj->kind == SM_OBJ_ENUM) {
+	} else if (new->kind == SM_OBJ_ENUM) {
 		new->sm_enum.flags = CFR_OPTFLAG_SUPPRESS;
 		new->sm_enum.default_value = 0;
 	}
 }
 
-static void update_bad_profile(const struct sm_object *obj, struct sm_object *new)
+static void update_bad_profile(struct sm_object *new)
 {
 	const bool pf_ok = get_emi_eeprom_vpd()->profile != 0;
 
@@ -37,17 +37,17 @@ static void update_bad_profile(const struct sm_object *obj, struct sm_object *ne
 	new->sm_comment.flags |= CFR_OPTFLAG_SUPPRESS;
 }
 
-static void update_serial(const struct sm_object *obj, struct sm_object *new)
+static void update_serial(struct sm_object *new)
 {
 	new->sm_varchar.default_value = get_emi_eeprom_vpd()->serial_number;
 }
 
-static void update_part_number(const struct sm_object *obj, struct sm_object *new)
+static void update_part_number(struct sm_object *new)
 {
 	new->sm_varchar.default_value = get_emi_eeprom_vpd()->part_number;
 }
 
-static void update_profile(const struct sm_object *obj, struct sm_object *new)
+static void update_profile(struct sm_object *new)
 {
 	new->sm_number.default_value = get_emi_eeprom_vpd()->profile;
 }
@@ -180,7 +180,7 @@ static struct sm_enum_value pch_pm_pcie_pll_ssc_values[] = {
 	SM_ENUM_VALUE_END,
 };
 
-static void update_pll_ssc_values(const struct sm_object *obj, struct sm_object *new)
+static void update_pll_ssc_values(struct sm_object *new)
 {
 	for (size_t i = 0; i < NUM_PCIE_SSC_SETTINGS; i++) {
 		char buffer[16];
diff --git a/src/mainboard/starlabs/common/cfr/cfr.c b/src/mainboard/starlabs/common/cfr/cfr.c
index ebf5ffc7ce..78a41814e5 100644
--- a/src/mainboard/starlabs/common/cfr/cfr.c
+++ b/src/mainboard/starlabs/common/cfr/cfr.c
@@ -3,9 +3,7 @@
 #include <drivers/option/cfr_frontend.h>
 #include <common/cfr.h>
 
-void __weak cfr_card_reader_update(const struct sm_object *obj,
-		struct sm_object *new_obj)
+void __weak cfr_card_reader_update(struct sm_object *new_obj)
 {
-	(void)obj;
 	(void)new_obj;
 }
diff --git a/src/mainboard/starlabs/common/include/common/cfr.h b/src/mainboard/starlabs/common/include/common/cfr.h
index e71f1bafd3..6566ce6e96 100644
--- a/src/mainboard/starlabs/common/include/common/cfr.h
+++ b/src/mainboard/starlabs/common/include/common/cfr.h
@@ -6,7 +6,7 @@
 #include <drivers/option/cfr_frontend.h>
 #include <common/powercap.h>
 
-void cfr_card_reader_update(const struct sm_object *obj, struct sm_object *new_obj);
+void cfr_card_reader_update(struct sm_object *new_obj);
 
 static const struct sm_object accelerometer = SM_DECLARE_BOOL({
 	.opt_name	= "accelerometer",
diff --git a/src/mainboard/starlabs/starlite_adl/cfr.c b/src/mainboard/starlabs/starlite_adl/cfr.c
index 62dc785b6c..2ed505a17f 100644
--- a/src/mainboard/starlabs/starlite_adl/cfr.c
+++ b/src/mainboard/starlabs/starlite_adl/cfr.c
@@ -11,7 +11,7 @@
 #include <variants.h>
 #include <common/cfr.h>
 
-void cfr_card_reader_update(const struct sm_object *obj, struct sm_object *new_obj)
+void cfr_card_reader_update(struct sm_object *new_obj)
 {
 	struct device *mxc_accel = DEV_PTR(mxc6655);
 

From a43498e193bb7cd5c1ea42d49c032871068a1a19 Mon Sep 17 00:00:00 2001
From: Ingo Reitz <9l@9lo.re>
Date: Fri, 14 Nov 2025 04:36:21 +0100
Subject: [PATCH 2484/3886] util/inteltool: Enable dumping GPIOs from Tiger
 Lake IoT PCH

Tested on Intel i5-1145GRE and it worked.

Change-Id: I0731e651eafe8635c50546eafdfccd00b74bcd2f
Signed-off-by: Ingo Reitz <9l@9lo.re>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90034
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 util/inteltool/gpio.c        | 1 +
 util/inteltool/gpio_groups.c | 1 +
 util/inteltool/inteltool.c   | 2 ++
 util/inteltool/inteltool.h   | 1 +
 util/inteltool/pcr.c         | 1 +
 5 files changed, 6 insertions(+)

diff --git a/util/inteltool/gpio.c b/util/inteltool/gpio.c
index cd6ce91185..ff21d2452b 100644
--- a/util/inteltool/gpio.c
+++ b/util/inteltool/gpio.c
@@ -1051,6 +1051,7 @@ int print_gpios(struct pci_dev *sb, int show_all, int show_diffs)
 	case PCI_DEVICE_ID_INTEL_TIGERPOINT_U_BASE:
 	case PCI_DEVICE_ID_INTEL_TIGERPOINT_Y_SUPER:
 	case PCI_DEVICE_ID_INTEL_TIGERPOINT_Y_PREM:
+	case PCI_DEVICE_ID_INTEL_TIGERPOINT_EMBEDDED_IOTG:
 	case PCI_DEVICE_ID_INTEL_C621:
 	case PCI_DEVICE_ID_INTEL_C622:
 	case PCI_DEVICE_ID_INTEL_C624:
diff --git a/util/inteltool/gpio_groups.c b/util/inteltool/gpio_groups.c
index 6efbfcb131..fb50905b25 100644
--- a/util/inteltool/gpio_groups.c
+++ b/util/inteltool/gpio_groups.c
@@ -198,6 +198,7 @@ const struct gpio_community *const *get_gpio_communities(struct pci_dev *const s
 	case PCI_DEVICE_ID_INTEL_TIGERPOINT_U_BASE:
 	case PCI_DEVICE_ID_INTEL_TIGERPOINT_Y_SUPER:
 	case PCI_DEVICE_ID_INTEL_TIGERPOINT_Y_PREM:
+	case PCI_DEVICE_ID_INTEL_TIGERPOINT_EMBEDDED_IOTG:
 		*community_count = ARRAY_SIZE(tigerlake_pch_lp_communities);
 		*pad_stepping = 16;
 		return tigerlake_pch_lp_communities;
diff --git a/util/inteltool/inteltool.c b/util/inteltool/inteltool.c
index e6f82371da..d58b850717 100644
--- a/util/inteltool/inteltool.c
+++ b/util/inteltool/inteltool.c
@@ -359,6 +359,8 @@ static const struct {
 	  "Tiger Point Y Engineering Sample" },
 	{ PCI_VENDOR_ID_INTEL,  PCI_DEVICE_ID_INTEL_TIGERPOINT_Y_PREM,
 	  "Tiger Point Y Premium/Tigerlake" },
+	{ PCI_VENDOR_ID_INTEL,  PCI_DEVICE_ID_INTEL_TIGERPOINT_EMBEDDED_IOTG,
+	  "Tiger Point Embedded IOTG" },
 	{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_H110, "H110" },
 	{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_H170, "H170" },
 	{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_Z170, "Z170" },
diff --git a/util/inteltool/inteltool.h b/util/inteltool/inteltool.h
index 80d307cfe4..f0ddef283d 100644
--- a/util/inteltool/inteltool.h
+++ b/util/inteltool/inteltool.h
@@ -158,6 +158,7 @@ static inline uint32_t inl(unsigned port)
 #define PCI_DEVICE_ID_INTEL_TIGERPOINT_U_BASE	0xa083
 #define PCI_DEVICE_ID_INTEL_TIGERPOINT_Y_SUPER	0xa086
 #define PCI_DEVICE_ID_INTEL_TIGERPOINT_Y_PREM	0xa087
+#define PCI_DEVICE_ID_INTEL_TIGERPOINT_EMBEDDED_IOTG	0xa088
 #define PCI_DEVICE_ID_INTEL_H110		0xa143
 #define PCI_DEVICE_ID_INTEL_H170		0xa144
 #define PCI_DEVICE_ID_INTEL_Z170		0xa145
diff --git a/util/inteltool/pcr.c b/util/inteltool/pcr.c
index 8bc6e1917b..6594561257 100644
--- a/util/inteltool/pcr.c
+++ b/util/inteltool/pcr.c
@@ -150,6 +150,7 @@ void pcr_init(struct pci_dev *const sb)
 	case PCI_DEVICE_ID_INTEL_TIGERPOINT_U_BASE:
 	case PCI_DEVICE_ID_INTEL_TIGERPOINT_Y_SUPER:
 	case PCI_DEVICE_ID_INTEL_TIGERPOINT_Y_PREM:
+	case PCI_DEVICE_ID_INTEL_TIGERPOINT_EMBEDDED_IOTG:
 	case PCI_DEVICE_ID_INTEL_ADL_P:
 	case PCI_DEVICE_ID_INTEL_ADL_M:
 	case PCI_DEVICE_ID_INTEL_RPL_P:

From 91073f37d76db19c7229c477837fb439f8d09753 Mon Sep 17 00:00:00 2001
From: Yu-Ping Wu <yupingso@chromium.org>
Date: Fri, 14 Nov 2025 01:59:11 +0000
Subject: [PATCH 2485/3886] mb/google/brya: Increase RW_SECTION_* by 256KB for
 16MiB boards

As the payload (depthcharge) is getting bigger for new features, the RW
CBFS sections for boards with 16MiB flash are not large enough.
Therefore, reduce RW_LEGACY from 1M to 512K, and increase each of
RW_SECTION_A and RW_SECTION_B by 256K.

NOTE: This is a RO/RW incompatible change, and should NEVER be
cherry-picked to firmware branches.

BUG=b:459853033
TEST=cq
BRANCH=none

Change-Id: If1b998e4ac8e5f00dee0b8afcf324c5f6bab697c
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90033
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
---
 src/mainboard/google/brya/chromeos-16MiB.fmd | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/src/mainboard/google/brya/chromeos-16MiB.fmd b/src/mainboard/google/brya/chromeos-16MiB.fmd
index 037812a83f..2ad5cc03d5 100644
--- a/src/mainboard/google/brya/chromeos-16MiB.fmd
+++ b/src/mainboard/google/brya/chromeos-16MiB.fmd
@@ -4,12 +4,12 @@ FLASH 16M {
 		SI_ME
 	}
 	SI_BIOS 12672K {
-		RW_SECTION_A 3700K {
+		RW_SECTION_A 3956K {
 			VBLOCK_A 8K
 			FW_MAIN_A(CBFS)
 			RW_FWID_A 64
 		}
-		RW_LEGACY(CBFS) 1M
+		RW_LEGACY(CBFS) 512K
 		RW_MISC 152K {
 			UNIFIED_MRC_CACHE(PRESERVE) 128K {
 				RECOVERY_MRC_CACHE 64K
@@ -22,7 +22,7 @@ FLASH 16M {
 			RW_VPD(PRESERVE) 8K
 			RW_NVRAM(PRESERVE) 8K
 		}
-		RW_SECTION_B 3700K {
+		RW_SECTION_B 3956K {
 			VBLOCK_B 8K
 			FW_MAIN_B(CBFS)
 			RW_FWID_B 64

From f164feba3ec2958564890fab71c04e1649285719 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Filip=20Lewi=C5=84ski?= <filip.lewinski@3mdeb.com>
Date: Thu, 16 Oct 2025 11:13:07 +0200
Subject: [PATCH 2486/3886] ifittool: allow adding files from a separate region
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Allows ifittool to add FIT entries for files that are located in a
different FMAP region than the FIT table.

The region from where to source the file can be specified with -R.
If not given it defaults to using the value of the mandatory -r,
for full backwards compatibility.

Example: Tested with a custom binary with the bootblock and
corresponding FIT table in a separate region, and the microcode still
in the COREBOOT region:

λ ./ifittool -f test_ts.rom -a -n cpu_microcode_blob.bin -t 1 \
	-r BOOTBLOCK \
	-R COREBOOT \
	-s 4

Change-Id: I7e49247f280ec118e09cf173795d7602a4c0d7f6
Signed-off-by: Filip Lewiński <filip.lewinski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89608
Reviewed-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 util/cbfstool/fit.c      |  6 +++---
 util/cbfstool/fit.h      |  2 +-
 util/cbfstool/ifittool.c | 46 +++++++++++++++++++++++++++++++++-------
 3 files changed, 42 insertions(+), 12 deletions(-)

diff --git a/util/cbfstool/fit.c b/util/cbfstool/fit.c
index 0d5d4c7847..87f9dd1895 100644
--- a/util/cbfstool/fit.c
+++ b/util/cbfstool/fit.c
@@ -492,7 +492,7 @@ static void update_fit_key_manifest_entry(struct fit_table *fit,
 
 /* Special case for ucode CBFS file, as it might contain more than one ucode */
 int fit_add_microcode_file(struct fit_table *fit,
-			   struct cbfs_image *image,
+			   struct cbfs_image *file_source_image,
 			   const char *blob_name,
 			   fit_offset_converter_t offset_helper,
 			   const size_t max_fit_entries)
@@ -508,7 +508,7 @@ int fit_add_microcode_file(struct fit_table *fit,
 		return 1;
 	}
 
-	if (parse_microcode_blob(image, blob_name, &mcus_found, mcus,
+	if (parse_microcode_blob(file_source_image, blob_name, &mcus_found, mcus,
 				 max_fit_entries)) {
 		free(mcus);
 		return 1;
@@ -516,7 +516,7 @@ int fit_add_microcode_file(struct fit_table *fit,
 
 	for (i = 0; i < mcus_found; i++) {
 		if (fit_add_entry(fit,
-				  offset_to_ptr(offset_helper, &image->buffer,
+				  offset_to_ptr(offset_helper, &file_source_image->buffer,
 						mcus[i].offset),
 				  0,
 				  FIT_TYPE_MICROCODE,
diff --git a/util/cbfstool/fit.h b/util/cbfstool/fit.h
index 6d7681f710..9df546ffa5 100644
--- a/util/cbfstool/fit.h
+++ b/util/cbfstool/fit.h
@@ -54,7 +54,7 @@ int fit_delete_entry(struct fit_table *fit,
 		     const size_t idx);
 
 int fit_add_microcode_file(struct fit_table *fit,
-			   struct cbfs_image *image,
+			   struct cbfs_image *file_source_image,
 			   const char *blob_name,
 			   fit_offset_converter_t offset_helper,
 			   const size_t max_fit_entries);
diff --git a/util/cbfstool/ifittool.c b/util/cbfstool/ifittool.c
index d0d9431804..d289ef746a 100644
--- a/util/cbfstool/ifittool.c
+++ b/util/cbfstool/ifittool.c
@@ -15,10 +15,11 @@
 /* Global variables */
 partitioned_file_t *image_file;
 
-static const char *optstring  = "H:j:f:r:d:t:n:s:cAaDvhF?";
+static const char *optstring  = "H:j:f:r:R:d:t:n:s:cAaDvhF?";
 static struct option long_options[] = {
 	{"file",            required_argument, 0, 'f' },
 	{"region",          required_argument, 0, 'r' },
+	{"file-region",     required_argument, 0, 'R' },
 	{"add-cbfs-entry",  no_argument,       0, 'a' },
 	{"add-region",      no_argument,       0, 'A' },
 	{"del-entry",       required_argument, 0, 'd' },
@@ -54,10 +55,12 @@ static void usage(const char *name)
 		"\t\t-D|--dump             :   Dump FIT table (at end of operation)\n"
 		"\t\t-c|--clear-table      :   Remove all existing entries (do not update)\n"
 		"\t\t-j|--topswap-size     :   Use second FIT table if non zero\n"
+		"\t\t-R|--file-region      :   The FMAP region of the added file,\n"
+		"\t\t                      :   defaults to the value of -r\n"
 		"\tREQUIRED ARGUMENTS:\n"
 		"\t\t-f|--file name        :   The file containing the CBFS\n"
 		"\t\t-s|--max-table-size   :   The number of possible FIT entries in table\n"
-		"\t\t-r|--region           :   The FMAP region to operate on\n"
+		"\t\t-r|--region           :   The FMAP region of the FIT table\n"
 	, name);
 }
 
@@ -139,6 +142,7 @@ int main(int argc, char *argv[])
 	const char *input_file = NULL;
 	const char *name = NULL;
 	const char *region_name = NULL;
+	const char *file_region_name = NULL;
 	enum fit_operation op = NO_OP;
 	bool dump = false, clear_table = false;
 	size_t max_table_size = 0;
@@ -228,6 +232,9 @@ int main(int argc, char *argv[])
 		case 'r':
 			region_name = optarg;
 			break;
+		case 'R':
+			file_region_name = optarg;
+			break;
 		case 's':
 			max_table_size = atoi(optarg);
 			break;
@@ -282,7 +289,9 @@ int main(int argc, char *argv[])
 					     op != NO_OP || clear_table);
 
 	struct buffer image_region;
+	struct buffer file_image_region;
 
+	// Open the FIT table's region
 	if (!partitioned_file_read_region(&image_region, image_file,
 					  region_name)) {
 		partitioned_file_close(image_file);
@@ -290,16 +299,37 @@ int main(int argc, char *argv[])
 		return 1;
 	}
 
+	// If the added file region is not specified, default to the FIT table's one.
+	if (!file_region_name) {
+		file_image_region = image_region;
+	} else {
+		// Open the -n file-to-add region
+		if (!partitioned_file_read_region(&file_image_region, image_file,
+						  file_region_name)) {
+			partitioned_file_close(image_file);
+			ERROR("The image will be left unmodified.\n");
+			return 1;
+		}
+	}
+
 	struct buffer bootblock;
 	// The bootblock is part of the CBFS on x86
 	buffer_clone(&bootblock, &image_region);
 
+	// Open the FIT table's CBFS
 	struct cbfs_image image;
 	if (cbfs_image_from_buffer(&image, &image_region, headeroffset)) {
 		partitioned_file_close(image_file);
 		return 1;
 	}
 
+	// Open the -n file-to-add CBFS
+	struct cbfs_image file_source_image;
+	if (cbfs_image_from_buffer(&file_source_image, &file_image_region, HEADER_OFFSET_UNKNOWN)) {
+		partitioned_file_close(image_file);
+		return 1;
+	}
+
 	struct fit_table *fit = NULL;
 	if (op != SET_FIT_PTR_OP) {
 		fit = fit_get_table(&bootblock, convert_to_from_top_aligned, topswap_size);
@@ -339,8 +369,8 @@ int main(int argc, char *argv[])
 	case ADD_CBFS_OP:
 	{
 		if (fit_type == FIT_TYPE_MICROCODE) {
-			if (fit_add_microcode_file(fit, &image, name,
-						   convert_to_from_top_aligned,
+			if (fit_add_microcode_file(fit, &file_source_image, name,
+						   convert_to_from_absolute_top_aligned,
 						   max_table_size)) {
 				return 1;
 			}
@@ -348,7 +378,7 @@ int main(int argc, char *argv[])
 			uint32_t offset, len;
 			struct cbfs_file *cbfs_file;
 
-			cbfs_file = cbfs_get_entry(&image, name);
+			cbfs_file = cbfs_get_entry(&file_source_image, name);
 			if (!cbfs_file) {
 				partitioned_file_close(image_file);
 				ERROR("%s not found in CBFS.\n", name);
@@ -356,9 +386,9 @@ int main(int argc, char *argv[])
 			}
 
 			len = be32toh(cbfs_file->len);
-			offset = offset_to_ptr(convert_to_from_top_aligned,
-					&image.buffer,
-					cbfs_get_entry_addr(&image, cbfs_file) +
+			offset = offset_to_ptr(convert_to_from_absolute_top_aligned,
+					&file_source_image.buffer,
+					cbfs_get_entry_addr(&file_source_image, cbfs_file) +
 					be32toh(cbfs_file->offset));
 
 

From 04ea4724e2d06498b463c32365306c5f2286affe Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Filip=20Lewi=C5=84ski?= <filip.lewinski@3mdeb.com>
Date: Fri, 17 Oct 2025 16:00:46 +0200
Subject: [PATCH 2487/3886] Makefile.mk: separate bootblocks into BOOTBLOCK and
 TOPSWAP
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Add Kconfig INTEL_TOP_SWAP_SEPARATE_REGIONS. When enabled, place the
regular bootblock in BOOTBLOCK and the Top Swap bootblock in TOPSWAP
to simplify A B updates. This lays groundwork for redundancy where one
bootblock remains a read only golden copy and the other is replaceable.

No swap control logic is added in this change. The option depends on
INTEL_ADD_TOP_SWAP_BOOTBLOCK and defaults to n so existing builds are
unchanged. A custom .fmd is required with BOOTBLOCK and TOPSWAP added
at the end of the image.

Background and update flow are described here:
Link: https://mail.coreboot.org/archives/list/coreboot@coreboot.org/thread/C6JN2PB7K7D67EG7OIKB6BBERZU5Y
V35/

TEST=Build and run Protectli VP6650 (ADL-P), boots successfully with
correct microcode

Change-Id: I489406dd8d08ad85bb46324d3d009acb49b6c52a
Signed-off-by: Filip Lewiński <filip.lewinski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89570
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com>
---
 Makefile.mk                         | 29 +++++++++++++++++++++++++++--
 src/cpu/intel/fit/Makefile.mk       | 16 +++++++++++-----
 src/soc/intel/common/Kconfig.common |  9 +++++++++
 3 files changed, 47 insertions(+), 7 deletions(-)

diff --git a/Makefile.mk b/Makefile.mk
index 62bce6f91c..93a26d0d95 100644
--- a/Makefile.mk
+++ b/Makefile.mk
@@ -1261,8 +1261,22 @@ $(obj)/fmap.fmap: $(obj)/fmap.fmd $(FMAPTOOL)
 	$(FMAPTOOL) -h $(obj)/fmap_config.h -R $(obj)/fmap.desc $< $@
 
 ifeq ($(CONFIG_INTEL_ADD_TOP_SWAP_BOOTBLOCK),y)
+ifneq ($(CONFIG_INTEL_TOP_SWAP_SEPARATE_REGIONS),y)
 TS_OPTIONS := -j $(CONFIG_INTEL_TOP_SWAP_BOOTBLOCK_SIZE)
 endif
+endif
+
+ifneq ($(CONFIG_INTEL_TOP_SWAP_SEPARATE_REGIONS),y)
+BB_FIT_REGION = COREBOOT
+TS_FIT_REGION = COREBOOT
+else
+BB_FIT_REGION = BOOTBLOCK
+TS_FIT_REGION = TOPSWAP
+bootblock_add_params = -f $(objcbfs)/bootblock.bin \
+	  -n bootblock -t bootblock \
+	  -b -$(call file-size,$(objcbfs)/bootblock.bin) \
+	  $(TXTIBB) $(cbfs-autogen-attributes) $(TS_OPTIONS) $(CBFSTOOL_ADD_CMD_OPTIONS)
+endif
 
 ifneq ($(CONFIG_ARCH_X86),y)
 add_bootblock = $(CBFSTOOL) $(1) write -u -r BOOTBLOCK -f $(2)
@@ -1276,7 +1290,9 @@ ifneq ($(CONFIG_UPDATE_IMAGE),y)
 $(obj)/coreboot.pre: $$(prebuilt-files) $(CBFSTOOL) $(obj)/fmap.fmap $(obj)/fmap.desc $(objcbfs)/bootblock.bin
 	$(CBFSTOOL) $@.tmp create -M $(obj)/fmap.fmap -r $(shell cat $(obj)/fmap.desc)
 	printf "    BOOTBLOCK\n"
+ifneq ($(CONFIG_INTEL_TOP_SWAP_SEPARATE_REGIONS),y)
 	$(call add_bootblock,$@.tmp,$(objcbfs)/bootblock.bin)
+endif # ifneq ($(CONFIG_INTEL_TOP_SWAP_SEPARATE_REGIONS),y)
 	$(prebuild-files) true
 	mv $@.tmp $@
 else # ifneq ($(CONFIG_UPDATE_IMAGE),y)
@@ -1306,6 +1322,15 @@ add_intermediate = \
 	$(1): $(obj)/coreboot.pre $(2) | $(INTERMEDIATE) \
 	$(eval INTERMEDIATE+=$(1)) $(eval PHONY+=$(1))
 
+ifeq ($(CONFIG_INTEL_TOP_SWAP_SEPARATE_REGIONS),y)
+$(call add_intermediate, prep_bb_regions, $(CBFSTOOL))
+	@printf "    PREP       place bootblocks in BOOTBLOCK and TOPSWAP\n"
+	@printf "    BOOTBLOCK\n"
+	$(CBFSTOOL) $< add -r $(BB_FIT_REGION) $(bootblock_add_params)
+	@printf "    TOPSWAP\n"
+	$(CBFSTOOL) $< add -r $(TS_FIT_REGION) $(bootblock_add_params)
+endif
+
 $(obj)/coreboot.rom: $(obj)/coreboot.pre $(CBFSTOOL) $(IFITTOOL) $$(INTERMEDIATE)
 	@printf "    CBFS       $(subst $(obj)/,,$(@))\n"
 # The full ROM may be larger than the CBFS part, so create an empty
@@ -1314,11 +1339,11 @@ $(obj)/coreboot.rom: $(obj)/coreboot.pre $(CBFSTOOL) $(IFITTOOL) $$(INTERMEDIATE
 	dd if=$(obj)/coreboot.pre of=$@.tmp bs=8192 conv=notrunc 2> /dev/null
 ifeq ($(CONFIG_CPU_INTEL_FIRMWARE_INTERFACE_TABLE),y)
 # Print final FIT table
-	$(IFITTOOL) -f $@.tmp -D -r COREBOOT
+	$(IFITTOOL) -f $@.tmp -D -r $(BB_FIT_REGION)
 # Print final TS BOOTBLOCK FIT table
 ifeq ($(CONFIG_INTEL_ADD_TOP_SWAP_BOOTBLOCK),y)
 	@printf "    TOP SWAP FIT table\n"
-	$(IFITTOOL) -f $@.tmp -D $(TS_OPTIONS) -r COREBOOT
+	$(IFITTOOL) -f $@.tmp -D $(TS_OPTIONS) -r $(TS_FIT_REGION)
 endif # CONFIG_INTEL_ADD_TOP_SWAP_BOOTBLOCK
 endif # CONFIG_CPU_INTEL_FIRMWARE_INTERFACE_TABLE
 	mv $@.tmp $@
diff --git a/src/cpu/intel/fit/Makefile.mk b/src/cpu/intel/fit/Makefile.mk
index f405c57744..c8bb5bd26f 100644
--- a/src/cpu/intel/fit/Makefile.mk
+++ b/src/cpu/intel/fit/Makefile.mk
@@ -13,9 +13,14 @@ intel_fit-file := fit_table.c:struct
 intel_fit-type := intel_fit
 intel_fit-align := 16
 
+ifeq ($(CONFIG_INTEL_TOP_SWAP_SEPARATE_REGIONS),y)
+regions-for-file-intel_fit = BOOTBLOCK
+regions-for-file-intel_fit_ts = TOPSWAP
+endif
+
 $(call add_intermediate, set_fit_ptr, $(IFITTOOL))
 	@printf "    UPDATE-FIT set FIT pointer to table\n"
-	$(IFITTOOL) -f $< -F -n intel_fit -r COREBOOT -c
+	$(IFITTOOL) -f $< -F -n intel_fit -r $(BB_FIT_REGION) -c
 
 FIT_ENTRY=$(call strip_quotes, $(CONFIG_INTEL_TOP_SWAP_FIT_ENTRY_FMAP_REG))
 
@@ -24,22 +29,23 @@ ifneq ($(CONFIG_UPDATE_IMAGE),y) # never update the bootblock
 ifneq ($(CONFIG_CPU_MICROCODE_CBFS_NONE)$(CONFIG_CPU_INTEL_MICROCODE_CBFS_SPLIT_BINS),y)
 
 $(call add_intermediate, add_mcu_fit, set_fit_ptr $(IFITTOOL))
+	@printf "$(call regions-for-file,$(cpu_microcode_blob.bin))"
 	@printf "    UPDATE-FIT Microcode\n"
-	$(IFITTOOL) -f $< -a -n cpu_microcode_blob.bin -t 1 -s $(CONFIG_CPU_INTEL_NUM_FIT_ENTRIES) -r COREBOOT
+	$(IFITTOOL) -f $< -a -n cpu_microcode_blob.bin -t 1 -s $(CONFIG_CPU_INTEL_NUM_FIT_ENTRIES) -r $(BB_FIT_REGION) -R COREBOOT
 
 # Second FIT in TOP_SWAP bootblock
 ifeq ($(CONFIG_INTEL_ADD_TOP_SWAP_BOOTBLOCK),y)
 
 $(call add_intermediate, set_ts_fit_ptr, $(IFITTOOL))
 	@printf "    UPDATE-FIT Top Swap: set FIT pointer to table\n"
-	$(IFITTOOL) -f $< -F -n intel_fit_ts -r COREBOOT $(TS_OPTIONS)
+	$(IFITTOOL) -f $< -F -n intel_fit_ts -r $(TS_FIT_REGION) $(TS_OPTIONS)
 
 $(call add_intermediate, add_ts_mcu_fit, set_ts_fit_ptr $(IFITTOOL))
 	@printf "    UPDATE-FIT Top Swap: Microcode\n"
 ifneq ($(FIT_ENTRY),)
-	$(IFITTOOL) -f $< -A -n $(FIT_ENTRY) -t 1 -s $(CONFIG_CPU_INTEL_NUM_FIT_ENTRIES) $(TS_OPTIONS) -r COREBOOT
+	$(IFITTOOL) -f $< -A -n $(FIT_ENTRY) -t 1 -s $(CONFIG_CPU_INTEL_NUM_FIT_ENTRIES) $(TS_OPTIONS) -r $(TS_FIT_REGION)
 endif # FIT_ENTRY
-	$(IFITTOOL) -f $< -a -n cpu_microcode_blob.bin -t 1 -s $(CONFIG_CPU_INTEL_NUM_FIT_ENTRIES) $(TS_OPTIONS) -r COREBOOT
+	$(IFITTOOL) -f $< -a -n cpu_microcode_blob.bin -t 1 -s $(CONFIG_CPU_INTEL_NUM_FIT_ENTRIES) $(TS_OPTIONS) -r $(TS_FIT_REGION) -R COREBOOT
 
 cbfs-files-y += intel_fit_ts
 intel_fit_ts-file := fit_table.c:struct
diff --git a/src/soc/intel/common/Kconfig.common b/src/soc/intel/common/Kconfig.common
index d52bc1a0fa..be05c65315 100644
--- a/src/soc/intel/common/Kconfig.common
+++ b/src/soc/intel/common/Kconfig.common
@@ -48,6 +48,15 @@ config INTEL_TOP_SWAP_FIT_ENTRY_FMAP_REG
 	  onto ifittool (-A -n option). ifittool will not parse the region for MCU
 	  entries, and only locate the region and insert its address into FIT.
 
+config INTEL_TOP_SWAP_SEPARATE_REGIONS
+	bool "Place the regular and Top Swap bootblocks in separate fmap regions"
+	depends on INTEL_ADD_TOP_SWAP_BOOTBLOCK && BOOTBLOCK_IN_CBFS
+	default n
+	help
+	  Place the bootblocks in BOOTBLOCK and TOPSWAP regions for easy access, to
+	  facilitate firmware updates using the Top Swap as Slot A/Slot B redundancy.
+	  Requires a custom .fmd with the regions added at the end.
+
 endif
 
 config SOC_INTEL_COMMON

From 91594f4894f041947b4cfdf0e76b5a9aeb3ac382 Mon Sep 17 00:00:00 2001
From: Maximilian Brune <maximilian.brune@9elements.com>
Date: Fri, 7 Nov 2025 23:02:16 +0100
Subject: [PATCH 2488/3886] drivers/option/cfr.c: Replace memcpy() to avoid
 uninitialized object

When updating clang to version 21.1.5, we now get the following error
when compiling the CFR code.
```
src/drivers/option/cfr.c:287:19: error: default initialization of an
      object of type 'struct sm_object' with const member leaves the object uninitialized
      [-Werror,-Wdefault-const-init-field-unsafe]
  287 |         struct sm_object sm_obj_copy;
```

In this specific case its actually not an issue, but initialize the
variable from the start to avoid the error and arguably make the code
easier to read.

Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: Ib0b22e20a7482ab29d997a3e3c3bec4a1db1a4f1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89958
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/drivers/option/cfr.c | 21 +++++++++------------
 1 file changed, 9 insertions(+), 12 deletions(-)

diff --git a/src/drivers/option/cfr.c b/src/drivers/option/cfr.c
index d338648029..d5390231d6 100644
--- a/src/drivers/option/cfr.c
+++ b/src/drivers/option/cfr.c
@@ -326,8 +326,8 @@ static uint32_t sm_write_object(char *current, const struct sm_object *sm_obj)
 	uint64_t dep_id, obj_id;
 	const uint32_t *dep_values;
 	uint32_t num_dep_values;
-	struct sm_object sm_obj_copy;
 	assert(sm_obj);
+	struct sm_object sm_obj_copy = *sm_obj;
 
 	/* Assign uniqueue ID */
 	obj_id = sm_gen_obj_id((void *)sm_obj);
@@ -346,37 +346,34 @@ static uint32_t sm_write_object(char *current, const struct sm_object *sm_obj)
 
 	/* Invoke callback to update fields */
 	if (sm_obj->ctor) {
-		memcpy(&sm_obj_copy, sm_obj, sizeof(*sm_obj));
-
 		sm_obj->ctor(&sm_obj_copy);
 		assert(sm_obj->kind == sm_obj_copy.kind);
-		sm_obj = (const struct sm_object *)&sm_obj_copy;
 	}
 
-	switch (sm_obj->kind) {
+	switch (sm_obj_copy.kind) {
 	case SM_OBJ_NONE:
 		return 0;
 	case SM_OBJ_ENUM:
-		return sm_write_opt_enum(current, &sm_obj->sm_enum, obj_id,
+		return sm_write_opt_enum(current, &sm_obj_copy.sm_enum, obj_id,
 					 dep_id, dep_values, num_dep_values);
 	case SM_OBJ_NUMBER:
-		return sm_write_opt_number(current, &sm_obj->sm_number, obj_id,
+		return sm_write_opt_number(current, &sm_obj_copy.sm_number, obj_id,
 					   dep_id, dep_values, num_dep_values);
 	case SM_OBJ_BOOL:
-		return sm_write_opt_bool(current, &sm_obj->sm_bool, obj_id,
+		return sm_write_opt_bool(current, &sm_obj_copy.sm_bool, obj_id,
 					 dep_id, dep_values, num_dep_values);
 	case SM_OBJ_VARCHAR:
-		return sm_write_opt_varchar(current, &sm_obj->sm_varchar, obj_id,
+		return sm_write_opt_varchar(current, &sm_obj_copy.sm_varchar, obj_id,
 					    dep_id, dep_values, num_dep_values);
 	case SM_OBJ_COMMENT:
-		return sm_write_opt_comment(current, &sm_obj->sm_comment, obj_id,
+		return sm_write_opt_comment(current, &sm_obj_copy.sm_comment, obj_id,
 					    dep_id, dep_values, num_dep_values);
 	case SM_OBJ_FORM:
-		return sm_write_form(current, (struct sm_obj_form *)&sm_obj->sm_form, obj_id,
+		return sm_write_form(current, (struct sm_obj_form *)&sm_obj_copy.sm_form, obj_id,
 				     dep_id, dep_values, num_dep_values);
 	default:
 		BUG();
-		printk(BIOS_ERR, "Unknown setup menu object kind %u, ignoring\n", sm_obj->kind);
+		printk(BIOS_ERR, "Unknown setup menu object kind %u, ignoring\n", sm_obj_copy.kind);
 		return 0;
 	}
 }

From 2b7b89ae316c021b5843f4a298e8994e08dca8c3 Mon Sep 17 00:00:00 2001
From: Hari L <haril@qualcomm.corp-partner.google.com>
Date: Fri, 14 Nov 2025 11:39:32 +0530
Subject: [PATCH 2489/3886] soc/qualcomm/x1p42100: Update PCIE PHY init
 sequence

Update PCIE PHY sequence as per hardware setting reference(HSR)
specifically, PCIE RC Config sequence(PCIE RC Cfg Seq).

Key changes:

- Add RX1-specific overrides applied after common RX settings
- Update TX lane mode register (LANE_MODE_3: 0x90 -> 0x51)
- Modify RX calibration and equalization parameters
- Adjust RX signal detection level (0xAA -> 0xCC)
- Add NVME_PLN_GPIO definition for Power Loss Notification

The changes ensure proper PHY initialization for PCIe Gen 4 link
establishment and improve signal integrity.

TEST=Boot the Google/Bluey board and check that the link is up

Debug logs:

[INFO ]  Enumerating buses...
[SPEW ]  Show all devs... Before device enumeration.
[SPEW ]  Root Device: enabled 1
[SPEW ]  CPU_CLUSTER: 0: enabled 1
[SPEW ]  DOMAIN: 00000000: enabled 1
[SPEW ]  PCI: 00:00:00.0: enabled 1
[SPEW ]  Compare with tree...
[SPEW ]  Root Device: enabled 1
[SPEW ]   CPU_CLUSTER: 0: enabled 1
[SPEW ]   DOMAIN: 00000000: enabled 1
[SPEW ]    PCI: 00:00:00.0: enabled 1
[DEBUG]  Root Device scanning...
[SPEW ]  scan_static_bus for Root Device
[DEBUG]  CPU_CLUSTER: 0 enabled
[INFO ]  Setup PCIe in RC mode
[DEBUG]  Skipping pipe
[DEBUG]  PCIe QPHY Initialized took 13us
[INFO ]  PCIe Link speed configured in Gen 4
[INFO ]  PCIe link is up
[NOTE ]  PCIe enumerated succussfully..
[DEBUG]  DOMAIN: 00000000 enabled
[DEBUG]  DOMAIN: 00000000 scanning...
[DEBUG]  PCI: pci_scan_bus for segment group 00 bus 00
[DEBUG]  PCI: 00:00:00.0 subordinate bus PCI Express
[DEBUG]  PCI: 00:00:00.0 [17cb/0111] enabled
[DEBUG]  PCI: 00:00:00.0 scanning...
[SPEW ]  do_pci_scan_bridge for PCI: 00:00:00.0
[DEBUG]  PCI: pci_scan_bus for segment group 00 bus 01
[DEBUG]  PCI: 00:01:00.0 [1e0f/000c] enabled
[INFO ]  PCI: 00:00:00.0: Setting Max_Payload_Size to 256
		for devices under this root port
[DEBUG]  scan_bus: bus PCI: 00:00:00.0 finished in 29 msecs
[DEBUG]  scan_bus: bus DOMAIN: 00000000 finished in 60 msecs
[SPEW ]  scan_static_bus for Root Device done
[DEBUG]  scan_bus: bus Root Device finished in 220 msecs
[INFO ]  done

Debug logs show successful PCIe enumeration with Gen 4 link up
and device [1e0f/000c] detected.

Change-Id: Ifb07839818e30622e35b6ee39af824fd5f19dec5
Signed-off-by: Hari L <haril@qualcomm.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90036
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
---
 src/soc/qualcomm/common/pcie_common.c |  2 ++
 src/soc/qualcomm/x1p42100/pcie.c      | 23 +++++++++++++++--------
 2 files changed, 17 insertions(+), 8 deletions(-)

diff --git a/src/soc/qualcomm/common/pcie_common.c b/src/soc/qualcomm/common/pcie_common.c
index 2ad32b02b2..ab8af642d1 100644
--- a/src/soc/qualcomm/common/pcie_common.c
+++ b/src/soc/qualcomm/common/pcie_common.c
@@ -379,6 +379,8 @@ static void configure_phy_port(pcie_qmp_phy_base_t *port, pcie_qmp_phy_cfg_t *qp
 	qcom_qmp_phy_config_lane(port->rx0, qphy->rx_tbl, qphy->rx_tbl_num, lane_base);
 	qcom_qmp_phy_config_lane(port->tx1, qphy->tx_tbl, qphy->tx_tbl_num, lane_base + 1);
 	qcom_qmp_phy_config_lane(port->rx1, qphy->rx_tbl, qphy->rx_tbl_num, lane_base + 1);
+	/* Apply RX1-specific overrides after common RX settings */
+	qcom_qmp_phy_config_lane(port->rx1, qphy->rx_tbl_sec, qphy->rx_tbl_num_sec, lane_base + 1);
 	qcom_qmp_phy_configure(port->ln_shrd, qphy->ln_shrd_tbl, qphy->ln_shrd_tbl_num);
 	qcom_qmp_phy_configure(port->serdes, qphy->serdes_tbl, qphy->serdes_tbl_num);
 	qcom_qmp_phy_configure(port->pcs, qphy->pcs_tbl, qphy->pcs_tbl_num);
diff --git a/src/soc/qualcomm/x1p42100/pcie.c b/src/soc/qualcomm/x1p42100/pcie.c
index a456e2805d..1e2c5e6e9f 100644
--- a/src/soc/qualcomm/x1p42100/pcie.c
+++ b/src/soc/qualcomm/x1p42100/pcie.c
@@ -64,7 +64,7 @@ static const struct qcom_qmp_phy_init_tbl x1p42100_qmp_pcie_tx_tbl[] = {
 	QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_RX, 0x03),
 	QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x01),
 	QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_2, 0x10),
-	QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_3, 0x90),
+	QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_3, 0x51),
 	QMP_PHY_INIT_CFG(QSERDES_V4_TX_TRAN_DRVR_EMP_EN, 0x34),
 };
 
@@ -72,12 +72,11 @@ static const struct qcom_qmp_phy_init_tbl x1p42100_qmp_pcie_rx_tbl[] = {
 	QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN_RATE2, 0x0C),
 	QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN_RATE2, 0x04),
 	QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN_RATE3, 0x0A),
-	QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN_RATE3, 0x05),
 	QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x16),
 	QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_ACC_DEFAULT_VAL_RATE3, 0x00),
-	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IVCM_CAL_CTRL2, 0x82),
+	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IVCM_CAL_CTRL2, 0x80),
 	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IVCM_POSTCAL_OFFSET, 0x00),
-	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_BKUP_CTRL1, 0x12),
+	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_BKUP_CTRL1, 0x15),
 	QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_1, 0x01),
 	QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_2, 0x01),
 	QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_3, 0x45),
@@ -87,13 +86,13 @@ static const struct qcom_qmp_phy_init_tbl x1p42100_qmp_pcie_rx_tbl[] = {
 	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0B),
 	QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_ENABLES, 0x1C),
 	QMP_PHY_INIT_CFG(QSERDES_V4_RX_PHPRE_CTRL, 0x20),
-	QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
-	QMP_PHY_INIT_CFG(QSERDES_V4_RX_Q_PI_INTRINSIC_BIAS_RATE32, 0x01),
+	QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x3A),
+	QMP_PHY_INIT_CFG(QSERDES_V4_RX_Q_PI_INTRINSIC_BIAS_RATE32, 0x39),
 	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_RATE2_B0, 0x14),
 	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_RATE2_B1, 0xB3),
 	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_RATE2_B2, 0x58),
 	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_RATE2_B3, 0x9A),
-	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_RATE2_B4, 0x28),
+	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_RATE2_B4, 0x26),
 	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_RATE2_B5, 0xB6),
 	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_RATE2_B6, 0xEE),
 	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_RATE3_B0, 0xE4),
@@ -106,6 +105,12 @@ static const struct qcom_qmp_phy_init_tbl x1p42100_qmp_pcie_rx_tbl[] = {
 	QMP_PHY_INIT_CFG(QSERDES_V4_RX_TX_ADPT_CTRL, 0x10),
 };
 
+/* RX1-specific overrides (applied after rx_tbl to RX1 lanes only) */
+static const struct qcom_qmp_phy_init_tbl x1p42100_qmp_pcie_rx_tbl_sec[] = {
+	QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_MAN_VAL, 0x0B),
+	QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
+};
+
 static const struct qcom_qmp_phy_init_tbl x1p42100_qmp_pcie_ln_shrd_tbl[] = {
 	QMP_PHY_INIT_CFG(QSERDES_V4_LN_SHRD_RXCLK_DIV2_CTRL, 0x01),
 	QMP_PHY_INIT_CFG(QSERDES_V4_LN_SHRD_DFE_DAC_ENABLE1, 0x88),
@@ -132,7 +137,7 @@ static const struct qcom_qmp_phy_init_tbl x1p42100_qmp_pcie_ln_shrd_tbl[] = {
 
 static const struct qcom_qmp_phy_init_tbl x1p42100_qmp_pcie_pcs_com_tbl[] = {
 	QMP_PHY_INIT_CFG(QPHY_PCIE4_PCS_COM_G3S2_PRE_GAIN, 0x2E),
-	QMP_PHY_INIT_CFG(QPHY_PCIE4_PCS_COM_RX_SIGDET_LVL, 0xAA),
+	QMP_PHY_INIT_CFG(QPHY_PCIE4_PCS_COM_RX_SIGDET_LVL, 0xCC),
 	QMP_PHY_INIT_CFG(QPHY_PCIE4_PCS_COM_EQ_CONFIG4, 0x00),
 	QMP_PHY_INIT_CFG(QPHY_PCIE4_PCS_COM_EQ_CONFIG5, 0x22),
 };
@@ -231,6 +236,8 @@ static pcie_qmp_phy_cfg_t pcie6a_qmp_phy_1x4 = {
 	.tx_tbl_num             = ARRAY_SIZE(x1p42100_qmp_pcie_tx_tbl),
 	.rx_tbl                 = x1p42100_qmp_pcie_rx_tbl,
 	.rx_tbl_num             = ARRAY_SIZE(x1p42100_qmp_pcie_rx_tbl),
+	.rx_tbl_sec             = x1p42100_qmp_pcie_rx_tbl_sec,
+	.rx_tbl_num_sec         = ARRAY_SIZE(x1p42100_qmp_pcie_rx_tbl_sec),
 	.pcs_tbl                = x1p42100_qmp_pcie_pcs_com_tbl,
 	.pcs_tbl_num            = ARRAY_SIZE(x1p42100_qmp_pcie_pcs_com_tbl),
 	.pcs_misc_tbl           = x1p42100_qmp_pcie_pcs_pcie_tbl,

From 62fc93de906780b7ca78cbf05c4d5f929699962b Mon Sep 17 00:00:00 2001
From: Hari L <haril@qualcomm.corp-partner.google.com>
Date: Fri, 14 Nov 2025 14:31:16 +0530
Subject: [PATCH 2490/3886] soc/qualcomm/x1p42100: Add NVMe Power Loss
 Notification GPIO configuration

Add support for configuring the NVMe Power Loss Notification (PLN)
GPIO before powering on the NVMe device.

The Hamoa target has the PLN signal wired to SoC GPIO 157. The voltage
level conversion circuitry between the SoC (1.2V) and NVMe (3.3V) causes
the PLN signal voltage level to vary depending on the NVMe part used.

This change configures GPIO 157 as an input with no pull resistors and
2mA drive strength to ensure proper PLN signal handling and allow the
GPIO to be used for other hardware configurations.

Changes:
- Add NVME_PLN_GPIO definition for GPIO(157)
- Add nvme_core_pln_gpio() function to configure PLN GPIO
- Update gcom_pcie_power_on_ep() to call nvme_core_pln_gpio() before
  enabling NVMe power regulator

TEST=Boot the Google/Bluey board and verify NVMe device is detected
and functional

Debug logs:

Initializing NVMe controller 1e0f:000c
nvme_ctrlr_init: PCI Command register = 0x2
nvme_ctrlr_init: PCI Status register = 0x10
nvme_ctrlr_init: PCI Command after bus master enable = 0x6
iosq_sz = 11, iocq_sz = 11
nvme_wait_status: Waiting for CSTS & 0x1 == 0x0, timeout=30000 ms
nvme_ctrlr_init: Waited 100ms after controller disable
nvme_enable_controller: CSTS before enable = 0x0
nvme_enable_controller: CAP register = 0x303c03ffff
nvme_enable_controller: CAP.TO timeout = 30000 ms
nvme_enable_controller: Writing CC register = 0x460001
nvme_enable_controller: CC register readback = 0x460001
nvme_wait_status: Waiting for CSTS & 0x1 == 0x1, timeout=30000 ms
nvme_enable_controller: CSTS after enable = 0x1 (status=0)
Identified NVMe model KBG50ZNS256G KIOXIA
Added NVMe drive "NVMe Namespace 1" lbasize:512, count:0x1dcf32b0

Change-Id: Icc22cfd397a0adbc051b2b1a2178aeedb7389ac0
Signed-off-by: Hari L <haril@qualcomm.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90037
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/soc/qualcomm/x1p42100/pcie.c | 23 +++++++++++++++++++++++
 1 file changed, 23 insertions(+)

diff --git a/src/soc/qualcomm/x1p42100/pcie.c b/src/soc/qualcomm/x1p42100/pcie.c
index 1e2c5e6e9f..1648bc6f2f 100644
--- a/src/soc/qualcomm/x1p42100/pcie.c
+++ b/src/soc/qualcomm/x1p42100/pcie.c
@@ -11,6 +11,7 @@
 #include <soc/pcie.h>
 
 #define NVME_REG_EN GPIO(18)
+#define NVME_PLN_GPIO GPIO(157)  /* Power Loss Notification */
 
 static const struct qcom_qmp_phy_init_tbl x1p42100_qmp_pcie_serdes_pll_tbl[] = {
 	QMP_PHY_INIT_CFG(QSERDES_V4_PLL_SSC_STEP_SIZE1_MODE1, 0x26),
@@ -301,9 +302,31 @@ int32_t qcom_dw_pcie_enable_clock(void)
 	return ret;
 }
 
+/*
+ * Configure NVMe Power Loss Notification GPIO
+ *
+ * Hamoa target wired the PLN signal to a SoC GPIO. The circuitry
+ * for connecting the PLN from the SoC (1.2volts) to the NVMe (3.3volts)
+ * caused the voltage level on the PLN signal on the NVMe side to be
+ * different depending on the NVMe part. This function will Configure PLN
+ * GPIO in software to make sure the PLN is high and this GPIO can be used
+ * for other HW configurations.
+ */
+static void nvme_core_pln_gpio(void)
+{
+	gpio_configure(NVME_PLN_GPIO,   /* GPIO 157 */
+		       GPIO_FUNC_GPIO,  /* Function, 0 for generic */
+		       GPIO_NO_PULL,    /* Pull */
+		       GPIO_2MA,        /* Drive strength */
+		       GPIO_INPUT);     /* Direction */
+}
+
 /* Turn on NVMe */
 void gcom_pcie_power_on_ep(void)
 {
+	/* Configure Power Loss Notification GPIO before powering on */
+	nvme_core_pln_gpio();
+
 	gpio_output(NVME_REG_EN, 1);
 }
 

From 493e3d182e82eb6ee0ea27e7d688337d79a0b5be Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Micha=C5=82=20=C5=BBygowski?= <michal.zygowski@3mdeb.com>
Date: Tue, 9 Apr 2024 14:00:50 +0200
Subject: [PATCH 2491/3886] payloads/external/iPXE: Allow building EFI target
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Add a Kconfig to enable building iPXE for EFI target, which can be
executed from EDK2. If not selected, iPXE will be built for use with
legacy BIOS. Add support to the Makefile to build the EFI target.

Change-Id: I7f247a59a65aeb18a67475d4d543f519af88aeb9
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83385
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 payloads/external/iPXE/Kconfig  |  8 ++++++++
 payloads/external/iPXE/Makefile | 14 +++++++++++---
 2 files changed, 19 insertions(+), 3 deletions(-)

diff --git a/payloads/external/iPXE/Kconfig b/payloads/external/iPXE/Kconfig
index ff25d81957..85e8c69296 100644
--- a/payloads/external/iPXE/Kconfig
+++ b/payloads/external/iPXE/Kconfig
@@ -116,6 +116,14 @@ config IPXE_TRUST_CMD
 	  digital signature of file prior loading it, and restrict to loading
 	  trusted files only.
 
+config IPXE_BUILD_EFI
+	bool "Build iPXE for EFI target"
+	depends on PAYLOAD_EDK2
+	default n
+	help
+	  Build iPXE for EFI target, enabling it to be executed from EDK2. If not
+	  selected, iPXE will be built for use with legacy BIOS.
+
 endif # BUILD_IPXE
 
 endmenu
diff --git a/payloads/external/iPXE/Makefile b/payloads/external/iPXE/Makefile
index 7ec8126c97..a58d5f79ce 100644
--- a/payloads/external/iPXE/Makefile
+++ b/payloads/external/iPXE/Makefile
@@ -11,6 +11,14 @@ project_name=iPXE
 project_dir=ipxe
 project_git_repo=https://git.ipxe.org/ipxe.git
 
+ifeq ($(CONFIG_IPXE_BUILD_EFI),y)
+IPXE_BUILD_TARGET := bin-x86_64-efi-sb/ipxe.efi
+# Workaround problems with unrecognized ipxe/util/elf2efi relocations
+PXE_MAKE_OPTS += EXTRA_CFLAGS="$(CFLAGS_x86_64) -fno-pic"
+else
+IPXE_BUILD_TARGET := bin/$(PXE_ROM_PCI_ID).rom
+endif
+
 all: build
 
 $(project_dir):
@@ -59,12 +67,12 @@ endif
 build: config $(CONFIG_SCRIPT)
 ifeq ($(CONFIG_HAS_SCRIPT),y)
 	echo "    MAKE       $(project_name) $(TAG-y) EMBED=$(CONFIG_SCRIPT)"
-	$(MAKE) -C $(project_dir)/src bin/$(PXE_ROM_PCI_ID).rom EMBED=$(CONFIG_SCRIPT)
+	$(MAKE) -C $(project_dir)/src $(IPXE_BUILD_TARGET) EMBED=$(CONFIG_SCRIPT) $(PXE_MAKE_OPTS)
 else
 	echo "    MAKE       $(project_name) $(TAG-y)"
-	$(MAKE) -C $(project_dir)/src bin/$(PXE_ROM_PCI_ID).rom
+	$(MAKE) -C $(project_dir)/src $(IPXE_BUILD_TARGET) $(PXE_MAKE_OPTS)
 endif
-	cp $(project_dir)/src/bin/$(PXE_ROM_PCI_ID).rom $(project_dir)/ipxe.rom
+	cp $(project_dir)/src/$(IPXE_BUILD_TARGET) $(project_dir)/ipxe.rom
 ifeq ($(CONSOLE_SERIAL),yy)
 	cp "$(project_dir)/src/config/console.h.cb" "$(project_dir)/src/config/console.h"
 	cp "$(project_dir)/src/config/serial.h.cb" "$(project_dir)/src/config/serial.h"

From dfe553aebb64782f363f9287d0c4374e147cb175 Mon Sep 17 00:00:00 2001
From: Riku Viitanen <riku.viitanen@protonmail.com>
Date: Wed, 12 Nov 2025 23:38:44 +0200
Subject: [PATCH 2492/3886] util/intelvbttool/Makefile: Add install target

Change-Id: Id69f8e4ea426bc60080cdfd004890a87b1720cd1
Signed-off-by: Riku Viitanen <riku.viitanen@protonmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90014
Reviewed-by: Nicholas <nic.c3.14@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 util/intelvbttool/Makefile | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/util/intelvbttool/Makefile b/util/intelvbttool/Makefile
index 86081e0f39..5c770dec9e 100644
--- a/util/intelvbttool/Makefile
+++ b/util/intelvbttool/Makefile
@@ -3,6 +3,8 @@
 
 PROGRAM = intelvbttool
 CC ?= gcc
+INSTALL ?= /usr/bin/env install
+PREFIX ?= /usr/local
 CFLAGS ?= -O2 -g
 CFLAGS += -Wall -Werror
 CFLAGS += -I../../src/commonlib/include -I ../../src/commonlib/bsd/include
@@ -17,4 +19,8 @@ clean:
 
 distclean: clean
 
+install: $(PROGRAM)
+	$(INSTALL) -d $(DESTDIR)$(PREFIX)/sbin
+	$(INSTALL) $(PROGRAM) $(DESTDIR)$(PREFIX)/sbin
+
 .PHONY: all clean distclean

From 0416ac98297b6850b41bbbe12a2bbfa41844490b Mon Sep 17 00:00:00 2001
From: Tongtong Pan <pantongtong@huaqin.corp-partner.google.com>
Date: Wed, 12 Nov 2025 14:56:20 +0800
Subject: [PATCH 2493/3886] mb/google/var/fatcat/lapis: Modify type-A USB3
 port0/1 tx_de_emp

Fix USB 3.2 Type-A port0/1 Tx compliance failures in EA test
- De-emphasis test failed: Actual value = 0.000000 dB,
requirement: -7.0 dB <= value <= -2.1 dB
- Preshoot test failed: Actual value = 0.000000 dB,
requirement: 1.2 dB <= value <= 3.2 dB
Set Type-A USB3 port0/1 tx_de_emp to 0x4 for signal integrity

BUG=b/451560515
TEST=build FW and check Type-A
USB3 port0/port1 RX pass in EA test

Change-Id: I1a563fbc27d2dac8b57a62b7bfded73e1a6732cf
Signed-off-by: Tongtong Pan <pantongtong@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90004
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/google/fatcat/variants/lapis/overridetree.cb | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/mainboard/google/fatcat/variants/lapis/overridetree.cb b/src/mainboard/google/fatcat/variants/lapis/overridetree.cb
index 299483d626..3d7e53aba5 100644
--- a/src/mainboard/google/fatcat/variants/lapis/overridetree.cb
+++ b/src/mainboard/google/fatcat/variants/lapis/overridetree.cb
@@ -80,8 +80,8 @@ chip soc/intel/pantherlake
 	register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" # Fingerprint
 	register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # Discrete Bluetooth
 
-	register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB3.2 x1 Type-A Con #1 (MB)/
-	register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB3.2 x1 Type-A Con #2 (DB)/
+	register "usb3_ports[0]" = "USB3_PORT_TX_CFG(OC_SKIP, 0x4)" # USB3.2 x1 Type-A Con #1 (MB)/
+	register "usb3_ports[1]" = "USB3_PORT_TX_CFG(OC_SKIP, 0x4)" # USB3.2 x1 Type-A Con #2 (DB)/
 
 	register "tcss_ports[0]" = "TCSS_PORT_DEFAULT(OC_SKIP)"
 	register "tcss_ports[2]" = "TCSS_PORT_DEFAULT(OC_SKIP)"

From ee59936e8333792316238caec43c7fa5d8ceb61a Mon Sep 17 00:00:00 2001
From: Karthikeyan Ramasubramanian <kramasub@google.com>
Date: Wed, 12 Nov 2025 22:07:31 -0700
Subject: [PATCH 2494/3886] commonlib/device_tree: Add an API to check if a DT
 is an overlay

Add dt_is_overlay() API to check whether the input devicetree is
actually an overlay DT. Payload will use this API when parsing an input
image which is a collection of base and overlay devicetree blobs.

BUG=b:394980221
TEST=Build firmware image for Rauru/Hylia and boot to OS. Ensure that
the API correctly identifies the base and overlay DTs.

Change-Id: I2fc54e3d9e63ebc993c8ce6a7d4a7224a9251497
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90028
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/commonlib/device_tree.c                   | 16 ++++++++++++++++
 src/commonlib/include/commonlib/device_tree.h |  3 +++
 2 files changed, 19 insertions(+)

diff --git a/src/commonlib/device_tree.c b/src/commonlib/device_tree.c
index d244ad9954..595c3cbb5d 100644
--- a/src/commonlib/device_tree.c
+++ b/src/commonlib/device_tree.c
@@ -2149,3 +2149,19 @@ int dt_apply_overlay(struct device_tree *tree, struct device_tree *overlay)
 
 	return 0;
 }
+
+bool dt_is_overlay(struct device_tree *tree)
+{
+	/* The actual overlaid nodes/props are in an __overlay__ child node. */
+	const char * const overlay_path[] = { "__overlay__", NULL };
+	struct device_tree_node *fragment;
+
+	if (!tree)
+		return false;
+
+	list_for_each(fragment, tree->root->children, list_node)
+		if (dt_find_node(fragment, overlay_path, NULL, NULL, 0))
+			return true;
+
+	return false;
+}
diff --git a/src/commonlib/include/commonlib/device_tree.h b/src/commonlib/include/commonlib/device_tree.h
index be945d93da..b6004fe8c4 100644
--- a/src/commonlib/include/commonlib/device_tree.h
+++ b/src/commonlib/include/commonlib/device_tree.h
@@ -234,4 +234,7 @@ int dt_apply_fixups(struct device_tree *tree);
  */
 struct device_tree_node *dt_init_reserved_memory_node(struct device_tree *tree);
 
+/* Check whether a devicetree is an overlay device tree */
+bool dt_is_overlay(struct device_tree *tree);
+
 #endif /* __COMMONLIB_DEVICE_TREE_H__ */

From f5f943c1c36f020f8e4dc608c4cc395bd1388f2f Mon Sep 17 00:00:00 2001
From: Subrata Banik <subratabanik@google.com>
Date: Sat, 15 Nov 2025 18:48:36 +0000
Subject: [PATCH 2495/3886] bluey/kconfig: Consolidate SPI flash driver
 selection

Simplify board-level Kconfig by consolidating the selection of SPI flash
drivers into the common configuration option.

Previously, individual board models explicitly selected their specific
SPI flash drivers (e.g., SPI_FLASH_MACRONIX, SPI_FLASH_WINBOND).

This patch standardizes the approach by:
1. Selecting `SPI_FLASH_INCLUDE_ALL_DRIVERS` in
   `BOARD_GOOGLE_BLUEY_COMMON`.
2. Removing the redundant vendor-specific selects from
   `BOARD_GOOGLE_MODEL_BLUEY`, `BOARD_GOOGLE_MODEL_QUENBI`, and
   `BOARD_GOOGLE_MODEL_QUARTZ`.

This change ensures all derived board models inherit the comprehensive
set of SPI flash drivers, simplifying maintenance and improving
flexibility for multi-vendor support.

BUG=b:456953373
TEST=Able to verify that the SPI flash getting correctly probed.

Change-Id: I3eb573d0069bfc1d7caab36c9a7a2a223d81c5df
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90051
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
---
 src/mainboard/google/bluey/Kconfig | 4 +---
 1 file changed, 1 insertion(+), 3 deletions(-)

diff --git a/src/mainboard/google/bluey/Kconfig b/src/mainboard/google/bluey/Kconfig
index ffe06eb433..a6ead70307 100644
--- a/src/mainboard/google/bluey/Kconfig
+++ b/src/mainboard/google/bluey/Kconfig
@@ -8,6 +8,7 @@ config BOARD_GOOGLE_BLUEY_COMMON
 	select MAINBOARD_HAS_CHROMEOS
 	select SPI_FLASH
 	select SPI_FLASH_FORCE_4_BYTE_ADDR_MODE
+	select SPI_FLASH_INCLUDE_ALL_DRIVERS
 
 config BOARD_GOOGLE_BASEBOARD_BLUEY
 	def_bool n
@@ -19,7 +20,6 @@ config BOARD_GOOGLE_MODEL_BLUEY
 	select BOARD_ROMSIZE_KB_65536
 	select MAINBOARD_HAS_FINGERPRINT_VIA_USB
 	select MISSING_BOARD_RESET
-	select SPI_FLASH_MACRONIX
 
 config BOARD_GOOGLE_BLUEY
 	select BOARD_GOOGLE_MODEL_BLUEY
@@ -36,7 +36,6 @@ config BOARD_GOOGLE_MODEL_QUENBI
 	select MAINBOARD_HAS_CHROME_EC
 	select MAINBOARD_HAS_FINGERPRINT_VIA_SPI
 	select MAINBOARD_HAS_GOOGLE_TPM
-	select SPI_FLASH_WINBOND
 
 config BOARD_GOOGLE_MODEL_QUARTZ
 	def_bool n
@@ -45,7 +44,6 @@ config BOARD_GOOGLE_MODEL_QUARTZ
 	select MAINBOARD_HAS_CHROME_EC
 	select MAINBOARD_HAS_FINGERPRINT_VIA_SPI
 	select MAINBOARD_HAS_GOOGLE_TPM
-	select SPI_FLASH_INCLUDE_ALL_DRIVERS
 
 config BOARD_GOOGLE_QUENBI
 	select BOARD_GOOGLE_MODEL_QUENBI

From 5bfc2d23bbb6bfd4543fb65ba5e747be03bce201 Mon Sep 17 00:00:00 2001
From: Subrata Banik <subratabanik@google.com>
Date: Wed, 12 Nov 2025 16:54:24 +0000
Subject: [PATCH 2496/3886] soc/qc/x1p42100:: Select Secure OS options in SoC
 Kconfig

Refactor Kconfig dependency by moving the selection of Secure OS
(TrustZone/TEE) features from the mainboard configuration to the
specific SoC configuration layer.

The selections for `ARM64_USE_SECURE_OS` and
`ARM64_USE_SECURE_OS_PAYLOAD` are moved from `BOARD_GOOGLE_BLUEY_COMMON`
to `SOC_QUALCOMM_HAMOA`.

This ensures that the Secure OS requirements are correctly associated
with the Hamoa chipset family itself, leading to better modularity and
future compatibility for Hamoa-based platforms.

Crucially, this change allows for precise control of the Secure OS
(BL32 firmware) applicability. By selecting the feature only within
`SOC_QUALCOMM_HAMOA`, we can ensure that platforms utilizing the
"Purwa SoC" family (which currently does not have a ready/available
SecureOS) automatically avoid the selection of these Kconfig options.

The change is verified by ensuring the QTEE (SecureOS) feature is
disabled for platforms using the Purwa SoC, specifically verified on the
google/quenbi mainboard.

BUG=b:459268465
TEST=Ensure disabling QTEE aka SecureOS feature for google/quenbi w/
Purwa SoC.

AP firmware log shows the expected path taken when SecureOS is disabled:

```
WARNING: No QTEE entry point provided by BL2 boot loader,
Booting device without QTEE initialization.
```

Change-Id: Ic82a29a4330cc6e5f99727fc40ec73b38cbbc72d
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90011
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/google/bluey/Kconfig | 2 --
 src/soc/qualcomm/x1p42100/Kconfig  | 2 ++
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/mainboard/google/bluey/Kconfig b/src/mainboard/google/bluey/Kconfig
index a6ead70307..0f5e8c3950 100644
--- a/src/mainboard/google/bluey/Kconfig
+++ b/src/mainboard/google/bluey/Kconfig
@@ -2,8 +2,6 @@
 
 config BOARD_GOOGLE_BLUEY_COMMON
 	def_bool n
-	select ARM64_USE_SECURE_OS
-	select ARM64_USE_SECURE_OS_PAYLOAD
 	select COMMON_CBFS_SPI_WRAPPER
 	select MAINBOARD_HAS_CHROMEOS
 	select SPI_FLASH
diff --git a/src/soc/qualcomm/x1p42100/Kconfig b/src/soc/qualcomm/x1p42100/Kconfig
index c02c2a649b..7107720391 100644
--- a/src/soc/qualcomm/x1p42100/Kconfig
+++ b/src/soc/qualcomm/x1p42100/Kconfig
@@ -39,6 +39,8 @@ config SOC_QUALCOMM_X1P42100
 
 config SOC_QUALCOMM_HAMOA
 	bool
+	select ARM64_USE_SECURE_OS
+	select ARM64_USE_SECURE_OS_PAYLOAD
 	select SOC_QUALCOMM_BASE
 	default n
 	help

From 33418b7e682f0352950579384f0cb824db741553 Mon Sep 17 00:00:00 2001
From: Subrata Banik <subratabanik@google.com>
Date: Fri, 14 Nov 2025 11:59:02 +0000
Subject: [PATCH 2497/3886] soc/qc/x1p42100: Disable compression for peripheral
 firmware binaries

The firmware binaries for UART, SPI, I2C, and GSI are loaded early in
the boot process. Disable CBFS compression for these files by explicitly
setting $(CBFS_..._compression) to 'none'.

This ensures the firmware is stored and loaded as a raw binary,
mitigating potential boot time impact with decompression.

BUG=b:449871690
TEST=Able to save ~10ms of the boot time while booting google/quenbi.

Change-Id: I0418aadeb860143e766b0fe1ba10a0316d4cc6a7
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90040
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/soc/qualcomm/x1p42100/Makefile.mk | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/src/soc/qualcomm/x1p42100/Makefile.mk b/src/soc/qualcomm/x1p42100/Makefile.mk
index ab23dde75d..0c6b9469f2 100644
--- a/src/soc/qualcomm/x1p42100/Makefile.mk
+++ b/src/soc/qualcomm/x1p42100/Makefile.mk
@@ -139,7 +139,7 @@ UART_FW_FILE := $(X1P42100_BLOB)/qup_fw/uart_fw.bin
 UART_FW_CBFS := $(CONFIG_CBFS_PREFIX)/uart_fw
 $(UART_FW_CBFS)-file := $(UART_FW_FILE)
 $(UART_FW_CBFS)-type := raw
-$(UART_FW_CBFS)-compression := $(CBFS_PRERAM_COMPRESS_FLAG)
+$(UART_FW_CBFS)-compression := none
 cbfs-files-y += $(UART_FW_CBFS)
 
 ################################################################################
@@ -147,7 +147,7 @@ SPI_FW_FILE := $(X1P42100_BLOB)/qup_fw/spi_fw.bin
 SPI_FW_CBFS := $(CONFIG_CBFS_PREFIX)/spi_fw
 $(SPI_FW_CBFS)-file := $(SPI_FW_FILE)
 $(SPI_FW_CBFS)-type := raw
-$(SPI_FW_CBFS)-compression := $(CBFS_PRERAM_COMPRESS_FLAG)
+$(SPI_FW_CBFS)-compression := none
 cbfs-files-y += $(SPI_FW_CBFS)
 
 ################################################################################
@@ -155,7 +155,7 @@ I2C_FW_FILE := $(X1P42100_BLOB)/qup_fw/i2c_fw.bin
 I2C_FW_CBFS := $(CONFIG_CBFS_PREFIX)/i2c_fw
 $(I2C_FW_CBFS)-file := $(I2C_FW_FILE)
 $(I2C_FW_CBFS)-type := raw
-$(I2C_FW_CBFS)-compression := $(CBFS_PRERAM_COMPRESS_FLAG)
+$(I2C_FW_CBFS)-compression := none
 cbfs-files-y += $(I2C_FW_CBFS)
 
 ################################################################################
@@ -259,7 +259,7 @@ GSI_FW_FILE := $(X1P42100_BLOB)/qup_fw/gsi_fw.bin
 GSI_FW_CBFS := $(CONFIG_CBFS_PREFIX)/gsi_fw
 $(GSI_FW_CBFS)-file := $(GSI_FW_FILE)
 $(GSI_FW_CBFS)-type := raw
-$(GSI_FW_CBFS)-compression := $(CBFS_COMPRESS_FLAG)
+$(GSI_FW_CBFS)-compression := none
 cbfs-files-y += $(GSI_FW_CBFS)
 
 ################################################################################

From 486b1b51af7fd814a5ec5b3131ec3fae60f30ad7 Mon Sep 17 00:00:00 2001
From: Subrata Banik <subratabanik@google.com>
Date: Thu, 13 Nov 2025 07:53:05 +0000
Subject: [PATCH 2498/3886] mb/google/bluey: Cache low battery mode check

The function `google_chromeec_is_below_critical_threshold()`
communicates with the Embedded Controller (EC) via the eSPI bus or
similar interface. Calling this function multiple times during boot is
inefficient, as the battery state is static for the duration of the
current boot stage.

Introduce a new static inline wrapper function, `is_low_battery_mode()`,
which ensures that the EC is queried only once. This is achieved by
using a function-scope static variable initialized by the EC function,
leveraging C's guarantee that static local variables are initialized
only upon first call.

Replace the direct calls to the EC function in:
1. `lb_add_boot_mode()`
2. `mainboard_needs_pcie_init()`
3. `mainboard_init()`

This change optimizes boot time by eliminating redundant EC
communication checks and ensures non-boot critical componts are not
getting initialized during the low-battery or off-mode charging boot

BUG=b:460299891
TEST=Ensures non-boot critical componts are not getting initialized
during the low-battery or off-mode charging boot.

Change-Id: I05fa17866c4952c3f3ad552b969dbe0d023b30a6
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90020
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
---
 src/mainboard/google/bluey/mainboard.c | 34 +++++++++++++++++++++++++-
 1 file changed, 33 insertions(+), 1 deletion(-)

diff --git a/src/mainboard/google/bluey/mainboard.c b/src/mainboard/google/bluey/mainboard.c
index df2d3d33a7..6517842b66 100644
--- a/src/mainboard/google/bluey/mainboard.c
+++ b/src/mainboard/google/bluey/mainboard.c
@@ -12,6 +12,30 @@
 #include "board.h"
 #include <soc/usb/usb.h>
 
+/*
+ * Check if the system is in low battery boot mode.
+ *
+ * This function calls the underlying EC function only once during the
+ * first execution and caches the result for all subsequent calls.
+ *
+ * Return `true` if system battery is below critical threshold, `false` otherwise.
+ */
+static inline bool is_low_battery_mode(void)
+{
+	if (!CONFIG(EC_GOOGLE_CHROMEEC))
+		return false;
+
+	static bool low_battery_mode_cached = false;
+	static bool cached_low_battery_result = false;
+
+	if (!low_battery_mode_cached) {
+		cached_low_battery_result = google_chromeec_is_below_critical_threshold();
+		low_battery_mode_cached = true;
+	}
+
+	return cached_low_battery_result;
+}
+
 static void setup_usb(void)
 {
 	setup_usb_host0();
@@ -29,7 +53,7 @@ void lb_add_boot_mode(struct lb_header *header)
 	mode->size = sizeof(*mode);
 	mode->boot_mode = LB_BOOT_MODE_NORMAL;
 
-	if (google_chromeec_is_below_critical_threshold())
+	if (is_low_battery_mode())
 		mode->boot_mode = LB_BOOT_MODE_LOW_BATTERY;
 
 	/* Enable charging only during low-battery mode */
@@ -39,6 +63,10 @@ void lb_add_boot_mode(struct lb_header *header)
 
 bool mainboard_needs_pcie_init(void)
 {
+	/* Skip PCIe initialization if boot mode is "low-battery" or "off-mode charging"*/
+	if (is_low_battery_mode())
+		return false;
+
 	return true;
 }
 
@@ -54,6 +82,10 @@ static void display_startup(void)
 
 static void mainboard_init(struct device *dev)
 {
+	/* Skip mainboard initialization if boot mode is "low-battery" or "off-mode charging"*/
+	if (is_low_battery_mode())
+		return;
+
 	gpi_firmware_load(QUP_0_GSI_BASE);
 	gpi_firmware_load(QUP_1_GSI_BASE);
 	gpi_firmware_load(QUP_2_GSI_BASE);

From 14595d64de17a39f946085620e2f221a6865443d Mon Sep 17 00:00:00 2001
From: Nancy Lin <nancy.lin@mediatek.corp-partner.google.com>
Date: Wed, 12 Nov 2025 13:34:08 +0800
Subject: [PATCH 2499/3886] lib/edid_fill_fb: Add dual pipe flag to
 lb_framebuffer_flags

Extend the lb_framebuffer_flags struct to include one more bitfield
'has_dual_pipe' to indicate dual pipe support.

TEST=firmware display ok, in depthcharge with https://crrev.com/c/7129839
BRANCH=none
BUG=b:424782827

Change-Id: I082be80b4606090ed219820a407d80d9f429ea7e
Signed-off-by: Nancy Lin <nancy.lin@mediatek.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90038
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
---
 payloads/libpayload/include/coreboot_tables.h     | 3 ++-
 src/commonlib/include/commonlib/coreboot_tables.h | 3 ++-
 src/include/framebuffer_info.h                    | 3 +++
 src/lib/edid_fill_fb.c                            | 8 ++++++++
 4 files changed, 15 insertions(+), 2 deletions(-)

diff --git a/payloads/libpayload/include/coreboot_tables.h b/payloads/libpayload/include/coreboot_tables.h
index 04d205c053..2f5b9be228 100644
--- a/payloads/libpayload/include/coreboot_tables.h
+++ b/payloads/libpayload/include/coreboot_tables.h
@@ -223,7 +223,8 @@ enum cb_fb_orientation {
 
 struct cb_framebuffer_flags {
 	u8 has_external_display : 1;
-	u8 reserved : 7;
+	u8 has_dual_pipe : 1;
+	u8 reserved : 6;
 };
 
 struct cb_framebuffer {
diff --git a/src/commonlib/include/commonlib/coreboot_tables.h b/src/commonlib/include/commonlib/coreboot_tables.h
index d308cf0ebf..fa966b5fef 100644
--- a/src/commonlib/include/commonlib/coreboot_tables.h
+++ b/src/commonlib/include/commonlib/coreboot_tables.h
@@ -281,7 +281,8 @@ enum lb_fb_orientation {
 
 struct lb_framebuffer_flags {
 	uint8_t has_external_display : 1;
-	uint8_t reserved : 7;
+	uint8_t has_dual_pipe : 1;
+	uint8_t reserved : 6;
 };
 
 struct lb_framebuffer {
diff --git a/src/include/framebuffer_info.h b/src/include/framebuffer_info.h
index 451d893e99..4bc7afea51 100644
--- a/src/include/framebuffer_info.h
+++ b/src/include/framebuffer_info.h
@@ -5,6 +5,7 @@
 
 #include <stdint.h>
 #include <commonlib/coreboot_tables.h>
+#include <types.h>
 
 struct fb_info;
 
@@ -20,6 +21,8 @@ int fb_add_framebuffer_info_simple(uintptr_t fb_addr, uint32_t x_res, uint32_t y
 void fb_set_orientation(struct fb_info *info,
 			enum lb_fb_orientation orientation);
 
+void fb_set_dual_pipe_flag(struct fb_info *info, bool dual_pipe);
+
 struct edid;
 struct fb_info *fb_new_framebuffer_info_from_edid(const struct edid *edid,
 						  uintptr_t fb_addr);
diff --git a/src/lib/edid_fill_fb.c b/src/lib/edid_fill_fb.c
index c72b70172c..a9ff31f5ca 100644
--- a/src/lib/edid_fill_fb.c
+++ b/src/lib/edid_fill_fb.c
@@ -163,6 +163,14 @@ void fb_set_orientation(struct fb_info *info, enum lb_fb_orientation orientation
 	info->fb.orientation = orientation;
 }
 
+void fb_set_dual_pipe_flag(struct fb_info *info, bool dual_pipe)
+{
+	if (!info)
+		return;
+
+	info->fb.flags.has_dual_pipe = dual_pipe;
+}
+
 /*
  * Take an edid, and create a framebuffer.
  */

From 3cf976e51a480ba19295c2aa04c548962a9d1ef4 Mon Sep 17 00:00:00 2001
From: Nancy Lin <nancy.lin@mediatek.corp-partner.google.com>
Date: Wed, 12 Nov 2025 13:39:17 +0800
Subject: [PATCH 2500/3886] soc/mediatek/mt8196: Add dual display pipe path

Add dual display pipe path. Also change the original single pipe path
with DSC engine configured in relay mode.

TEST=build pass and test display logo ok
BUG=b:424782827

Change-Id: I2373ea63a08bf25a7eef45b947d218b445b62130
Signed-off-by: Nancy Lin <nancy.lin@mediatek.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90039
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/soc/mediatek/common/display.c             |   3 +
 src/soc/mediatek/common/include/soc/display.h |   1 +
 src/soc/mediatek/mt8196/ddp.c                 | 263 ++++++++++++++----
 .../mediatek/mt8196/include/soc/addressmap.h  |  22 ++
 src/soc/mediatek/mt8196/include/soc/ddp.h     | 183 +++++++++---
 5 files changed, 377 insertions(+), 95 deletions(-)

diff --git a/src/soc/mediatek/common/display.c b/src/soc/mediatek/common/display.c
index 8e3979df26..f48cdaf215 100644
--- a/src/soc/mediatek/common/display.c
+++ b/src/soc/mediatek/common/display.c
@@ -191,6 +191,9 @@ int mtk_display_init(void)
 	if (info)
 		fb_set_orientation(info, panel->orientation);
 
+	if (panel->disp_path == DISP_PATH_DUAL_MIPI)
+		fb_set_dual_pipe_flag(info, true);
+
 	if (CONFIG(BMP_LOGO))
 		display_logo(panel, fb_addr, &edid);
 
diff --git a/src/soc/mediatek/common/include/soc/display.h b/src/soc/mediatek/common/include/soc/display.h
index fdcfcfdef2..f202c1d40e 100644
--- a/src/soc/mediatek/common/include/soc/display.h
+++ b/src/soc/mediatek/common/include/soc/display.h
@@ -11,6 +11,7 @@ enum disp_path_sel {
 	DISP_PATH_NONE = 0,
 	DISP_PATH_EDP,
 	DISP_PATH_MIPI,
+	DISP_PATH_DUAL_MIPI,
 };
 
 #define PANEL_QUIRK_FORCE_MAX_SWING	BIT(0)
diff --git a/src/soc/mediatek/mt8196/ddp.c b/src/soc/mediatek/mt8196/ddp.c
index 6e57e78301..6e63b376cd 100644
--- a/src/soc/mediatek/mt8196/ddp.c
+++ b/src/soc/mediatek/mt8196/ddp.c
@@ -1,5 +1,6 @@
 /* SPDX-License-Identifier: GPL-2.0-only OR MIT */
 
+#include <assert.h>
 #include <console/console.h>
 #include <device/mmio.h>
 #include <edid.h>
@@ -7,6 +8,40 @@
 #include <soc/ddp.h>
 
 #define SIZE(w, h) ((u32)(h) << 16 | (w))
+#define DUAL_PIPE(path) ((path) == DISP_PATH_DUAL_MIPI)
+
+struct disp_pipe_regs {
+	struct disp_mdp_rsz_regs *const mdp_rsz;
+	struct disp_tdshp_regs *const tdshp;
+	struct disp_ccorr_regs *const ccorr0;
+	struct disp_ccorr_regs *const ccorr1;
+	struct disp_gamma_regs *const gamma;
+	struct disp_postmask_regs *const postmask;
+	struct disp_dither_regs *const dither;
+	struct disp_dsc_regs *const dsc;
+};
+
+static const struct disp_pipe_regs disp_pipe0_regs = {
+	.mdp_rsz  = disp_mdp_rsz0_reg,
+	.tdshp    = disp_tdshp0_reg,
+	.ccorr0   = disp_ccorr0_reg,
+	.ccorr1   = disp_ccorr1_reg,
+	.gamma    = disp_gamma0_reg,
+	.postmask = disp_postmask0_reg,
+	.dither   = disp_dither0_reg,
+	.dsc      = disp_dsc2_reg,
+};
+
+static const struct disp_pipe_regs disp_pipe1_regs = {
+	.mdp_rsz  = disp_mdp_rsz1_reg,
+	.tdshp    = disp_tdshp1_reg,
+	.ccorr0   = disp_ccorr2_reg,
+	.ccorr1   = disp_ccorr3_reg,
+	.gamma    = disp_gamma1_reg,
+	.postmask = disp_postmask1_reg,
+	.dither   = disp_dither1_reg,
+	.dsc      = disp_dsc3_reg,
+};
 
 static void blender_config(struct blender *reg, u16 width, u16 height,
 			   enum mtk_disp_blender_layer type)
@@ -121,19 +156,37 @@ static void dither_start(struct disp_dither_regs *reg)
 	setbits32(&reg->en, BIT(0));
 }
 
+static void dsc_config(struct disp_dsc_regs *reg, u16 width, u16 height)
+{
+	write32(&reg->dsc_con, BIT(5));
+	write32(&reg->pic_w, width);
+	write32(&reg->pic_h, height);
+	write32(&reg->chunk_size, width << 16);
+}
+
+static void dsc_start(struct disp_dsc_regs *reg)
+{
+	setbits32(&reg->dsc_con, BIT(0));
+}
+
+static void ovlsys_path_connect(struct ovlsys_cfg *reg)
+{
+	setbits32(&reg->bypass_mux_shadow, BIT(0));
+	write32(&reg->cb_con, 0xFF << 16);
+	setbits32(&reg->rsz_in_cb2, BIT(1));
+	setbits32(&reg->exdma_out_cb3, BIT(2));
+	setbits32(&reg->blender_out_cb4, BIT(0));
+	setbits32(&reg->outproc_out_cb0, BIT(0));
+}
+
 static void disp_config_main_path_connection(enum disp_path_sel path)
 {
 	/* ovlsys */
-	setbits32(&ovlsys_cfg->bypass_mux_shadow, BIT(0));
-	write32(&ovlsys_cfg->cb_con, 0xFF << 16);
-	setbits32(&ovlsys_cfg->rsz_in_cb2, BIT(1));
-	setbits32(&ovlsys_cfg->exdma_out_cb3, BIT(2));
-	setbits32(&ovlsys_cfg->blender_out_cb4, BIT(0));
-	setbits32(&ovlsys_cfg->outproc_out_cb0, BIT(0));
+	ovlsys_path_connect(ovlsys_cfg);
 
 	/* dispsys */
 	write32(&mmsys_cfg->bypass_mux_shadow, 0xFF << 16 | BIT(0));
-	setbits32(&mmsys_cfg->pq_in_cb0, BIT(0));
+	setbits32(&mmsys_cfg->pq_in_cb[0], BIT(0));
 	setbits32(&mmsys_cfg->disp_mdp_rsz0_mout, BIT(0));
 	write32(&mmsys_cfg->disp_tdshp0_sout, 0x2);
 	write32(&mmsys_cfg->disp_ccorr0_sel, 0x2);
@@ -142,45 +195,95 @@ static void disp_config_main_path_connection(enum disp_path_sel path)
 	write32(&mmsys_cfg->disp_ccorr1_sout, 0x1);
 	write32(&mmsys_cfg->disp_gamma0_sel, 0x1);
 	write32(&mmsys_cfg->disp_postmask_sout, 0x0);
-	setbits32(&mmsys_cfg->pq_out_cb0, BIT(1));
+	setbits32(&mmsys_cfg->pq_out_cb[0], BIT(1));
 	setbits32(&mmsys_cfg->panel_comp_out_cb1, BIT(1));
 
 	/* dispsys1 */
 	write32(&mmsys1_cfg->bypass_mux_shadow, 0xFF << 16 | BIT(0));
 	setbits32(&mmsys1_cfg->splitter_in_cb1, BIT(5));
-	setbits32(&mmsys1_cfg->splitter_out_cb9, BIT(10));
-	setbits32(&mmsys1_cfg->comp_out_cb6, BIT(0));
-	if (path == DISP_PATH_EDP)
+	setbits32(&mmsys1_cfg->splitter_out_cb9, BIT(5));
+	setbits32(&mmsys1_cfg->comp_out_cb3, BIT(0));
+
+	if (DUAL_PIPE(path)) {
+		/* ovlsys1 */
+		ovlsys_path_connect(ovlsys1_cfg);
+		/* dispsys */
+		setbits32(&mmsys_cfg->pq_in_cb[8], BIT(1));
+		setbits32(&mmsys_cfg->disp_mdp_rsz1_mout, BIT(0));
+		write32(&mmsys_cfg->disp_tdshp1_sout, 0x2);
+		write32(&mmsys_cfg->disp_ccorr2_sel, 0x2);
+		write32(&mmsys_cfg->disp_ccorr2_sout, 0x1);
+		write32(&mmsys_cfg->disp_ccorr3_sel, 0x1);
+		write32(&mmsys_cfg->disp_ccorr3_sout, 0x1);
+		write32(&mmsys_cfg->disp_gamma1_sel, 0x1);
+		write32(&mmsys_cfg->disp_postmask1_sout, 0x0);
+		setbits32(&mmsys_cfg->pq_out_cb[3], BIT(2));
+		setbits32(&mmsys_cfg->panel_comp_out_cb2, BIT(2));
+
+		/* dispsys1 */
+		setbits32(&mmsys1_cfg->splitter_in_cb2, BIT(8));
+		setbits32(&mmsys1_cfg->splitter_out_cb12, BIT(7));
+		setbits32(&mmsys1_cfg->comp_out_cb4, BIT(3));
+	}
+
+	if (path == DISP_PATH_EDP) {
 		setbits32(&mmsys1_cfg->merge_out_cb0, BIT(9));
-	else
+	} else if (path == DISP_PATH_MIPI) {
 		setbits32(&mmsys1_cfg->merge_out_cb0, BIT(0));
+	} else {
+		setbits32(&mmsys1_cfg->merge_out_cb0, BIT(0));
+		setbits32(&mmsys1_cfg->merge_out_cb3, BIT(3));
+	}
 }
 
-static void async_config(u16 width, u16 height)
+static void async_config(u16 width, u16 height, enum disp_path_sel path)
 {
+	u32 relay = BIT(30) | SIZE(width, height);
+
 	write32(&ovlsys_cfg->relay5_size, SIZE(width, height));
-	write32(&mmsys_cfg->dl_in_relay0, BIT(30) | SIZE(width, height));
-	write32(&mmsys_cfg->dl_out_relay1, BIT(30) | SIZE(width, height));
-	write32(&mmsys1_cfg->dl_in_relay21, BIT(30) | SIZE(width, height));
+	write32(&mmsys_cfg->dl_in_relay[0], relay);
+	write32(&mmsys_cfg->dl_out_relay[1], relay);
+	write32(&mmsys1_cfg->dl_in_relay21, relay);
+
+	if (DUAL_PIPE(path)) {
+		write32(&ovlsys1_cfg->relay5_size, SIZE(width, height));
+		write32(&mmsys_cfg->dl_in_relay[8], relay);
+		write32(&mmsys_cfg->dl_out_relay[2], relay);
+		write32(&mmsys1_cfg->dl_in_relay22, relay);
+	}
 }
 
 static void disp_config_main_path_mutex(enum disp_path_sel path)
 {
-	u32 val;
+	u32 val, val1;
 
 	/* ovlsys mutex */
 	write32(&mmsys_mutex[OVL0]->mutex[0].mod, MUTEX_MOD_OVL_MAIN_PATH);
 	write32(&mmsys_mutex[OVL0]->mutex[0].mod1, MUTEX_MOD1_OVL_MAIN_PATH);
 
+	if (DUAL_PIPE(path)) {
+		write32(&mmsys_mutex[OVL1]->mutex[0].mod, MUTEX_MOD_OVL_MAIN_PATH_DUAL);
+		write32(&mmsys_mutex[OVL1]->mutex[0].mod1, MUTEX_MOD1_OVL_MAIN_PATH_DUAL);
+	}
+
 	/* dispsys mutex */
-	write32(&mmsys_mutex[DISP0]->mutex[0].mod, MUTEX_MOD_DISP_MAIN_PATH);
-	write32(&mmsys_mutex[DISP0]->mutex[0].mod1, MUTEX_MOD1_DISP_MAIN_PATH);
+	val = MUTEX_MOD_DISP_MAIN_PATH;
+	val1 = MUTEX_MOD1_DISP_MAIN_PATH;
+	if (DUAL_PIPE(path)) {
+		val |= MUTEX_MOD_DISP_MAIN_PATH_DUAL;
+		val1 |= MUTEX_MOD1_DISP_MAIN_PATH_DUAL;
+	}
+	write32(&mmsys_mutex[DISP0]->mutex[0].mod, val);
+	write32(&mmsys_mutex[DISP0]->mutex[0].mod1, val1);
 
 	/* dispsys1 mutex */
 	if (path == DISP_PATH_EDP)
-		write32(&mmsys_mutex[DISP1]->mutex[0].mod, MUTEX_MOD_DISP1_MAIN_PATH_EDP);
+		val = MUTEX_MOD_DISP1_MAIN_PATH_EDP;
+	else if (path == DISP_PATH_MIPI)
+		val = MUTEX_MOD_DISP1_MAIN_PATH_DSI0;
 	else
-		write32(&mmsys_mutex[DISP1]->mutex[0].mod, MUTEX_MOD_DISP1_MAIN_PATH_DSI0);
+		val = MUTEX_MOD_DISP1_MAIN_PATH_DUAL_DSI;
+	write32(&mmsys_mutex[DISP1]->mutex[0].mod, val);
 
 	/* mutex source from DVO */
 	if (path == DISP_PATH_EDP)
@@ -188,52 +291,81 @@ static void disp_config_main_path_mutex(enum disp_path_sel path)
 	else
 		val = MUTEX_SOF_DSI0 | (MUTEX_SOF_DSI0 << 7);
 	write32(&mmsys_mutex[OVL0]->mutex[0].ctl, val);
+	if (DUAL_PIPE(path))
+		write32(&mmsys_mutex[OVL1]->mutex[0].ctl, val);
 	write32(&mmsys_mutex[DISP0]->mutex[0].ctl, val);
 	write32(&mmsys_mutex[DISP1]->mutex[0].ctl, val);
 
 	/* mutex enable */
 	write32(&mmsys_mutex[OVL0]->mutex[0].en, BIT(0));
+	if (DUAL_PIPE(path))
+		write32(&mmsys_mutex[OVL1]->mutex[0].en, BIT(0));
 	write32(&mmsys_mutex[DISP0]->mutex[0].en, BIT(0));
 	write32(&mmsys_mutex[DISP1]->mutex[0].en, BIT(0));
 }
 
-static void main_disp_path_setup(u16 width, u16 height, u32 vrefresh, enum disp_path_sel path)
+static void disp_config_blender(struct blender *const blenders[], size_t size, u16 width,
+				u16 height)
 {
 	int i;
-	enum mtk_disp_blender_layer blender_type[ARRAY_SIZE(blenders)] = {
+	static const enum mtk_disp_blender_layer blender_type[] = {
 		FIRST_BLENDER,
 		OTHER_BLENDER,
 		OTHER_BLENDER,
 		LAST_BLENDER,
 	};
 
+	assert(size <= ARRAY_SIZE(blender_type));
+
 	/* ovlsys config */
-	for (i = 0; i < ARRAY_SIZE(blenders); i++) {
+	for (i = 0; i < size; i++) {
 		blender_config(blenders[i], width, height, blender_type[i]);
 		blender_start(blenders[i]);
 	}
+}
 
-	outproc_config(outproc0_reg, width, height);
-	outproc_start(outproc0_reg);
+static void main_disp_path_setup(u16 width, u16 height, u32 vrefresh, enum disp_path_sel path)
+{
+	u16 w = width;
+	size_t num_pipe = DUAL_PIPE(path) ? 2 : 1;
+	const struct disp_pipe_regs pipes[] = {disp_pipe0_regs, disp_pipe1_regs};
+
+	if (DUAL_PIPE(path))
+		w /= 2;
+
+	disp_config_blender(ovl_blenders, ARRAY_SIZE(ovl_blenders), w, height);
+	if (DUAL_PIPE(path))
+		disp_config_blender(ovl1_blenders, ARRAY_SIZE(ovl1_blenders), w, height);
+
+	outproc_config(ovl_outproc0_reg, w, height);
+	outproc_start(ovl_outproc0_reg);
+	if (DUAL_PIPE(path)) {
+		outproc_config(ovl1_outproc0_reg, w, height);
+		outproc_start(ovl1_outproc0_reg);
+	}
 
 	/* disp config */
-	mdp_rsz_config(disp_mdp_rsz0_reg, width, height);
-	mdp_rsz_start(disp_mdp_rsz0_reg);
-	tdshp_config(disp_tdshp0_reg, width, height);
-	tdshp_start(disp_tdshp0_reg);
-	ccorr_config(disp_ccorr0_reg, width, height);
-	ccorr_start(disp_ccorr0_reg);
-	ccorr_config(disp_ccorr1_reg, width, height);
-	ccorr_start(disp_ccorr1_reg);
-	gamma_config(disp_gamma0_reg, width, height);
-	gamma_start(disp_gamma0_reg);
-	postmask_config(disp_postmask0_reg, width, height);
-	postmask_start(disp_postmask0_reg);
-	dither_config(disp_dither0_reg, width, height);
-	dither_start(disp_dither0_reg);
+	for (int i = 0; i < num_pipe; i++) {
+		mdp_rsz_config(pipes[i].mdp_rsz, w, height);
+		mdp_rsz_start(pipes[i].mdp_rsz);
+		tdshp_config(pipes[i].tdshp, w, height);
+		tdshp_start(pipes[i].tdshp);
+		ccorr_config(pipes[i].ccorr0, w, height);
+		ccorr_start(pipes[i].ccorr0);
+		ccorr_config(pipes[i].ccorr1, w, height);
+		ccorr_start(pipes[i].ccorr1);
+		gamma_config(pipes[i].gamma, w, height);
+		gamma_start(pipes[i].gamma);
+		postmask_config(pipes[i].postmask, w, height);
+		postmask_start(pipes[i].postmask);
+		dither_config(pipes[i].dither, w, height);
+		dither_start(pipes[i].dither);
+		dsc_config(pipes[i].dsc, w, height);
+		dsc_start(pipes[i].dsc);
+	}
 
 	/* async config */
-	async_config(width, height);
+	async_config(w, height, path);
 
 	/* path connect */
 	disp_config_main_path_connection(path);
@@ -255,25 +387,40 @@ static void disp_clock_on(void)
 	clrbits32(&ovlsys_cfg->mmsys_cg_con2, CG_CON_ALL);
 }
 
-static void ovlsys_layer_config(u32 fmt, u32 bpp, u16 width, u16 height)
+static void ovlsys_layer_config_pipe(struct exdma *exdma, struct blender *blender,
+				     u32 fmt, u16 width, u16 height, u16 pitch)
 {
 	/* exdma config */
-	write32(&exdma2_reg->roi_size, SIZE(width, height));
-	write32(&exdma2_reg->ovl_l_size, SIZE(width, height));
-	write32(&exdma2_reg->pitch, (width * bpp) & 0xFFFF);
-	write32(&exdma2_reg->ovl_l_clrfmt, fmt);
+	write32(&exdma->roi_size, SIZE(width, height));
+	write32(&exdma->ovl_l_size, SIZE(width, height));
+	write32(&exdma->pitch, pitch & 0xFFFF);
+	write32(&exdma->ovl_l_clrfmt, fmt);
 
 	/* exdma start */
-	clrsetbits32(&exdma2_reg->rdma_burst_ctl, BIT(28) | BIT(30) | BIT(31),
+	clrsetbits32(&exdma->rdma_burst_ctl, BIT(28) | BIT(30) | BIT(31),
 		     BIT(28) | BIT(31));
-	setbits32(&exdma2_reg->dummy, BIT(2) | BIT(3));
-	setbits32(&exdma2_reg->datapath_con, BIT(0) | BIT(24) | BIT(25));
-	clrsetbits32(&exdma2_reg->ovl_mout, BIT(0) | BIT(1), BIT(1));
-	write32(&exdma2_reg->gdrdy_period, 0xFFFFFFFF);
+	setbits32(&exdma->dummy, BIT(2) | BIT(3));
+	setbits32(&exdma->datapath_con, BIT(0) | BIT(24) | BIT(25));
+	clrsetbits32(&exdma->ovl_mout, BIT(0) | BIT(1), BIT(1));
+	write32(&exdma->gdrdy_period, 0xFFFFFFFF);
 
 	/* Enable layer */
-	setbits32(&exdma2_reg->rdma0_ctl, BIT(0));
-	setbits32(&blenders[0]->bld_l_fmt, fmt);
+	setbits32(&exdma->rdma0_ctl, BIT(0));
+	setbits32(&blender->bld_l_fmt, fmt);
+}
+
+static void ovlsys_layer_config(u32 fmt, u32 bpp, u16 width, u16 height,
+				enum disp_path_sel path)
+{
+	u16 w = width;
+
+	if (DUAL_PIPE(path))
+		w /= 2;
+
+	ovlsys_layer_config_pipe(ovl_exdma2_reg, ovl_blenders[0], fmt, w, height, width * bpp);
+	if (DUAL_PIPE(path))
+		ovlsys_layer_config_pipe(ovl1_exdma2_reg, ovl1_blenders[0], fmt, w, height,
+					 width * bpp);
 }
 
 void mtk_ddp_init(void)
@@ -308,13 +455,13 @@ void mtk_ddp_mode_set(const struct edid *edid, enum disp_path_sel path)
 		       width, height, 0x1FFF);
 
 	main_disp_path_setup(width, height, vrefresh, path);
-	ovlsys_layer_config(fmt, bpp, width, height);
+	ovlsys_layer_config(fmt, bpp, width, height, path);
 }
 
 void mtk_ddp_ovlsys_start(uintptr_t fb_addr)
 {
-	write32(&exdma2_reg->ovl_addr, fb_addr);
-	setbits32(&exdma2_reg->ovl_en, BIT(0));
-	setbits32(&exdma2_reg->ovl_l_en, BIT(0));
-	setbits32(&blenders[0]->bld_l_en, BIT(0));
+	write32(&ovl_exdma2_reg->ovl_addr, fb_addr);
+	setbits32(&ovl_exdma2_reg->ovl_en, BIT(0));
+	setbits32(&ovl_exdma2_reg->ovl_l_en, BIT(0));
+	setbits32(&ovl_blenders[0]->bld_l_en, BIT(0));
 }
diff --git a/src/soc/mediatek/mt8196/include/soc/addressmap.h b/src/soc/mediatek/mt8196/include/soc/addressmap.h
index 65257eb769..dd16892646 100644
--- a/src/soc/mediatek/mt8196/include/soc/addressmap.h
+++ b/src/soc/mediatek/mt8196/include/soc/addressmap.h
@@ -196,25 +196,47 @@ enum {
 	MMSYS_MUTEX_BASE	= IO_PHYS + 0x22020000,
 	DISP_CCORR0_BASE	= IO_PHYS + 0x22090000,
 	DISP_CCORR1_BASE	= IO_PHYS + 0x220A0000,
+	DISP_CCORR2_BASE	= IO_PHYS + 0x220B0000,
+	DISP_CCORR3_BASE	= IO_PHYS + 0x220C0000,
 	DISP_COLOR0_BASE	= IO_PHYS + 0x220F0000,
 	DISP_DITHER0_BASE	= IO_PHYS + 0x22110000,
+	DISP_DITHER1_BASE	= IO_PHYS + 0x22120000,
 	DISP_GAMMA0_BASE	= IO_PHYS + 0x22130000,
+	DISP_GAMMA1_BASE	= IO_PHYS + 0x22140000,
 	DISP_POSTMASK0_BASE	= IO_PHYS + 0x22180000,
+	DISP_POSTMASK1_BASE	= IO_PHYS + 0x22190000,
 	DISP_MDP_RSZ0_BASE	= IO_PHYS + 0x221A0000,
+	DISP_MDP_RSZ1_BASE	= IO_PHYS + 0x221B0000,
 	DISP_TDSHP0_BASE	= IO_PHYS + 0x221E0000,
+	DISP_TDSHP1_BASE	= IO_PHYS + 0x221F0000,
 	MMSYS1_CONFIG_BASE	= IO_PHYS + 0x22400000,
 	MMSYS1_MUTEX_BASE	= IO_PHYS + 0x22420000,
+	DSC2_BASE		= IO_PHYS + 0x22470000,
+	DSC3_BASE		= IO_PHYS + 0x22480000,
 	DSI0_BASE		= IO_PHYS + 0x22490000,
 	DISP_DVO0		= IO_PHYS + 0x224C0000,
 	OVLSYS_CONFIG_BASE	= IO_PHYS + 0x22800000,
 	OVLSYS_MUTEX_BASE	= IO_PHYS + 0x22820000,
 	OVLSYS_EXDMA2_BASE	= IO_PHYS + 0x22850000,
+	OVLSYS_EXDMA6_BASE	= IO_PHYS + 0x22890000,
 	OVLSYS_BLENDER1_BASE	= IO_PHYS + 0x228E0000,
 	OVLSYS_BLENDER2_BASE	= IO_PHYS + 0x228F0000,
 	OVLSYS_BLENDER3_BASE	= IO_PHYS + 0x22900000,
 	OVLSYS_BLENDER4_BASE	= IO_PHYS + 0x22910000,
+	OVLSYS_BLENDER5_BASE	= IO_PHYS + 0x22920000,
+	OVLSYS_BLENDER6_BASE	= IO_PHYS + 0x22930000,
+	OVLSYS_BLENDER7_BASE	= IO_PHYS + 0x22940000,
+	OVLSYS_BLENDER8_BASE	= IO_PHYS + 0x22950000,
 	OVLSYS_OUTPROC0_BASE	= IO_PHYS + 0x22970000,
+	OVLSYS_OUTPROC1_BASE	= IO_PHYS + 0x22980000,
 	OVLSYS1_CONFIG_BASE	= IO_PHYS + 0x22C00000,
+	OVLSYS1_MUTEX_BASE	= IO_PHYS + 0x22C20000,
+	OVLSYS1_EXDMA2_BASE	= IO_PHYS + 0x22C50000,
+	OVLSYS1_BLENDER1_BASE	= IO_PHYS + 0x22CE0000,
+	OVLSYS1_BLENDER2_BASE	= IO_PHYS + 0x22CF0000,
+	OVLSYS1_BLENDER3_BASE	= IO_PHYS + 0x22D00000,
+	OVLSYS1_BLENDER4_BASE	= IO_PHYS + 0x22D10000,
+	OVLSYS1_OUTPROC0_BASE	= IO_PHYS + 0x22D70000,
 	DISP_VDISP_AO_CONFIG_BASE	= IO_PHYS + 0x2E800000,
 	EDP_CLK_BASE		= IO_PHYS + 0x21B50000,
 	EDP_BASE		= IO_PHYS + 0x2EC40000,
diff --git a/src/soc/mediatek/mt8196/include/soc/ddp.h b/src/soc/mediatek/mt8196/include/soc/ddp.h
index c2fbbb36ee..2c91747345 100644
--- a/src/soc/mediatek/mt8196/include/soc/ddp.h
+++ b/src/soc/mediatek/mt8196/include/soc/ddp.h
@@ -24,7 +24,8 @@ struct ovlsys_cfg {
 	u32 mmsys_cg_clr2;
 	u32 reserved_0x12c[92];
 	u32 relay5_size;
-	u32 reserved_0x2a0[640];
+	u32 relay6_size;
+	u32 reserved_0x2a4[639];
 	u32 bypass_mux_shadow;
 	u32 reserved_0xca4;
 	u32 reserved_0xca8;
@@ -33,13 +34,15 @@ struct ovlsys_cfg {
 	u32 blender_out_cb4;
 	u32 reserved_0xe14;
 	u32 reserved_0xe18;
-	u32 reserved_0xe1c[17];
-	u32 reserved_0xe60;
-	u32 reserved_0xe64;
+	u32 reserved_0xe1c;
+	u32 blender_out_cb8;
+	u32 reserved_0xe24[17];
 	u32 exdma_out_cb3;
-	u32 reserved_0xe6c[41];
+	u32 reserved_0xe6c[7];
+	u32 exdma_out_cb7;
+	u32 reserved_0xe8c[33];
 	u32 outproc_out_cb0;
-	u32 reserved_0xf14;
+	u32 outproc_out_cb1;
 	u32 reserved_0xf18[22];
 	u32 rsz_in_cb2;
 };
@@ -48,14 +51,19 @@ check_member(ovlsys_cfg, mmsys_cg_con0, 0x100);
 check_member(ovlsys_cfg, mmsys_cg_con1, 0x110);
 check_member(ovlsys_cfg, mmsys_cg_con2, 0x120);
 check_member(ovlsys_cfg, relay5_size, 0x29C);
+check_member(ovlsys_cfg, relay6_size, 0x2A0);
 check_member(ovlsys_cfg, bypass_mux_shadow, 0xCA0);
 check_member(ovlsys_cfg, cb_con, 0xCAC);
 check_member(ovlsys_cfg, blender_out_cb4, 0xE10);
+check_member(ovlsys_cfg, blender_out_cb8, 0xE20);
 check_member(ovlsys_cfg, exdma_out_cb3, 0xE68);
+check_member(ovlsys_cfg, exdma_out_cb7, 0xE88);
 check_member(ovlsys_cfg, outproc_out_cb0, 0xF10);
+check_member(ovlsys_cfg, outproc_out_cb1, 0xF14);
 check_member(ovlsys_cfg, rsz_in_cb2, 0xF70);
 
 static struct ovlsys_cfg *const ovlsys_cfg = (void *)OVLSYS_CONFIG_BASE;
+static struct ovlsys_cfg *const ovlsys1_cfg = (void *)OVLSYS1_CONFIG_BASE;
 
 struct dispsys_cfg {
 	u32 reserved_0x000[64];
@@ -71,50 +79,58 @@ struct dispsys_cfg {
 	u32 mmsys_cg_set2;
 	u32 mmsys_cg_clr2;
 	u32 reserved_0x12c[53];
-	u32 dl_in_relay0;
-	u32 reserved_0x204[25];
-	u32 dl_out_relay1;
-	u32 reserved_0x26c[625];
+	u32 dl_in_relay[9];
+	u32 reserved_0x224[16];
+	u32 dl_out_relay[9];
+	u32 reserved_0x288[618];
 	u32 bypass_mux_shadow;
 	u32 reserved_0xc34[61];
 	u32 disp_ccorr0_sel;
 	u32 disp_ccorr0_sout;
 	u32 disp_ccorr1_sel;
 	u32 disp_ccorr1_sout;
-	u32 reserved_0xd38[8];
+	u32 disp_ccorr2_sel;
+	u32 disp_ccorr2_sout;
+	u32 disp_ccorr3_sel;
+	u32 disp_ccorr3_sout;
+	u32 reserved_0xd48[4];
 	u32 disp_gamma0_sel;
-	u32 reserved_0xd5c[3];
+	u32 disp_gamma1_sel;
+	u32 reserved_0xd60[2];
 	u32 disp_postmask_sout;
-	u32 reserved_0xd6c;
+	u32 disp_postmask1_sout;
 	u32 disp_tdshp0_sout;
-	u32 reserved_0xd74;
+	u32 disp_tdshp1_sout;
 	u32 disp_mdp_rsz0_mout;
-	u32 reserved_0xd7c[2];
+	u32 disp_mdp_rsz1_mout;
+	u32 reserved_0xd80;
 	u32 panel_comp_out_cb1;
-	u32 reserved_0xd88[18];
-	u32 pq_in_cb0;
-	u32 reserved_0xdd4[26];
-	u32 pq_out_cb0;
-	u32 pq_out_cb1;
-	u32 pq_out_cb2;
-	u32 reserved_0xe40[3];
-	u32 pq_out_cb6;
+	u32 panel_comp_out_cb2;
+	u32 reserved_0xd8c[17];
+	u32 pq_in_cb[9];
+	u32 reserved_0xdf4[18];
+	u32 pq_out_cb[7];
 };
 
 check_member(dispsys_cfg, mmsys_cg_con0, 0x100);
 check_member(dispsys_cfg, mmsys_cg_con1, 0x110);
 check_member(dispsys_cfg, mmsys_cg_con2, 0x120);
-check_member(dispsys_cfg, dl_in_relay0, 0x200);
-check_member(dispsys_cfg, dl_out_relay1, 0x268);
+check_member(dispsys_cfg, dl_in_relay[0], 0x200);
+check_member(dispsys_cfg, dl_out_relay[0], 0x264);
 check_member(dispsys_cfg, bypass_mux_shadow, 0xC30);
 check_member(dispsys_cfg, disp_ccorr0_sel, 0xD28);
 check_member(dispsys_cfg, disp_gamma0_sel, 0xD58);
+check_member(dispsys_cfg, disp_gamma1_sel, 0xD5C);
 check_member(dispsys_cfg, disp_postmask_sout, 0xD68);
+check_member(dispsys_cfg, disp_postmask1_sout, 0xD6C);
 check_member(dispsys_cfg, disp_tdshp0_sout, 0xD70);
+check_member(dispsys_cfg, disp_tdshp1_sout, 0xD74);
+check_member(dispsys_cfg, disp_mdp_rsz0_mout, 0xD78);
+check_member(dispsys_cfg, disp_mdp_rsz1_mout, 0xD7C);
 check_member(dispsys_cfg, panel_comp_out_cb1, 0xD84);
-check_member(dispsys_cfg, pq_in_cb0, 0xDD0);
-check_member(dispsys_cfg, pq_out_cb0, 0xE3C);
-check_member(dispsys_cfg, pq_out_cb6, 0xE54);
+check_member(dispsys_cfg, panel_comp_out_cb2, 0xD88);
+check_member(dispsys_cfg, pq_in_cb[0], 0xDD0);
+check_member(dispsys_cfg, pq_out_cb[0], 0xE3C);
 
 static struct dispsys_cfg *const mmsys_cfg = (void *)MMSYS_CONFIG_BASE;
 
@@ -133,27 +149,47 @@ struct dispsys1_cfg {
 	u32 mmsys_cg_clr2;
 	u32 reserved_0x12c[54];
 	u32 dl_in_relay21;
-	u32 reserved_0x208[700];
+	u32 dl_in_relay22;
+	u32 reserved_0x20c[699];
 	u32 bypass_mux_shadow;
-	u32 reserved_0xcfc[13];
+	u32 reserved_0xcfc[7];
+	u32 comp_out_cb3;
+	u32 reserved_0xd1c;
+	u32 comp_out_cb4;
+	u32 reserved_0xd24[3];
 	u32 comp_out_cb6;
-	u32 reserved_0xd34[38];
+	u32 reserved_0xd34;
+	u32 comp_out_cb7;
+	u32 reserved_0xd3c[36];
 	u32 merge_out_cb0;
-	u32 reserved_0xdd0[55];
+	u32 reserved_0xdd0[5];
+	u32 merge_out_cb3;
+	u32 reserved_0xde8[49];
 	u32 splitter_in_cb1;
-	u32 reserved_0xeb0[45];
+	u32 reserved_0xeb0;
+	u32 splitter_in_cb2;
+	u32 reserved_0xeb8[43];
 	u32 splitter_out_cb9;
+	u32 reserved_0xf68[5];
+	u32 splitter_out_cb12;
 };
 
 check_member(dispsys1_cfg, mmsys_cg_con0, 0x100);
 check_member(dispsys1_cfg, mmsys_cg_con1, 0x110);
 check_member(dispsys1_cfg, mmsys_cg_con2, 0x120);
 check_member(dispsys1_cfg, dl_in_relay21, 0x204);
+check_member(dispsys1_cfg, dl_in_relay22, 0x208);
 check_member(dispsys1_cfg, bypass_mux_shadow, 0xCF8);
+check_member(dispsys1_cfg, comp_out_cb3, 0xD18);
+check_member(dispsys1_cfg, comp_out_cb4, 0xD20);
 check_member(dispsys1_cfg, comp_out_cb6, 0xD30);
+check_member(dispsys1_cfg, comp_out_cb7, 0xD38);
 check_member(dispsys1_cfg, merge_out_cb0, 0xDCC);
+check_member(dispsys1_cfg, merge_out_cb3, 0xDE4);
 check_member(dispsys1_cfg, splitter_in_cb1, 0xEAC);
+check_member(dispsys1_cfg, splitter_in_cb2, 0xEB4);
 check_member(dispsys1_cfg, splitter_out_cb9, 0xF64);
+check_member(dispsys1_cfg, splitter_out_cb12, 0xF7C);
 
 static struct dispsys1_cfg *const mmsys1_cfg = (void *)MMSYS1_CONFIG_BASE;
 
@@ -204,7 +240,8 @@ check_member(exdma, pitch, 0x2F4);
 check_member(exdma, ovl_addr, 0xF40);
 check_member(exdma, ovl_mout, 0xFF0);
 
-static struct exdma *const exdma2_reg = (void *)OVLSYS_EXDMA2_BASE;
+static struct exdma *const ovl_exdma2_reg = (void *)OVLSYS_EXDMA2_BASE;
+static struct exdma *const ovl1_exdma2_reg = (void *)OVLSYS1_EXDMA2_BASE;
 
 struct blender {
 	u32 reserved_0x000[4];
@@ -237,13 +274,20 @@ check_member(blender, bld_l_fmt, 0x050);
 check_member(blender, bg_clr, 0x104);
 check_member(blender, bld_l_con2, 0x200);
 
-static struct blender *const blenders[] = {
+static struct blender *const ovl_blenders[] = {
 	(void *)OVLSYS_BLENDER1_BASE,
 	(void *)OVLSYS_BLENDER2_BASE,
 	(void *)OVLSYS_BLENDER3_BASE,
 	(void *)OVLSYS_BLENDER4_BASE,
 };
 
+static struct blender *const ovl1_blenders[] = {
+	(void *)OVLSYS1_BLENDER1_BASE,
+	(void *)OVLSYS1_BLENDER2_BASE,
+	(void *)OVLSYS1_BLENDER3_BASE,
+	(void *)OVLSYS1_BLENDER4_BASE,
+};
+
 struct outproc {
 	u32 reserved_0x000[4];
 	u32 datapath_con;
@@ -260,7 +304,8 @@ check_member(outproc, outproc_en, 0x020);
 check_member(outproc, shadow_ctl, 0x028);
 check_member(outproc, roi_size, 0x030);
 
-static struct outproc *const outproc0_reg = (void *)OVLSYS_OUTPROC0_BASE;
+static struct outproc *const ovl_outproc0_reg = (void *)OVLSYS_OUTPROC0_BASE;
+static struct outproc *const ovl1_outproc0_reg = (void *)OVLSYS1_OUTPROC0_BASE;
 
 struct disp_mutex {
 	u32 inten;
@@ -282,12 +327,14 @@ enum mmsys {
 	DISP0,
 	DISP1,
 	OVL0,
+	OVL1,
 };
 
 static struct disp_mutex *const mmsys_mutex[] = {
 	[DISP0] = (void *)MMSYS_MUTEX_BASE,
 	[DISP1] = (void *)MMSYS1_MUTEX_BASE,
 	[OVL0] = (void *)OVLSYS_MUTEX_BASE,
+	[OVL1] = (void *)OVLSYS1_MUTEX_BASE,
 };
 
 enum {
@@ -303,59 +350,98 @@ enum {
 /* OVLSYS mutex module */
 enum {
 	MUTEX_MOD_OVL_EXDMA2		= BIT(2),
+	MUTEX_MOD_OVL_EXDMA6		= BIT(6),
 	MUTEX_MOD_OVL_BLENDER1		= BIT(11),
 	MUTEX_MOD_OVL_BLENDER2		= BIT(12),
 	MUTEX_MOD_OVL_BLENDER3		= BIT(13),
 	MUTEX_MOD_OVL_BLENDER4		= BIT(14),
+	MUTEX_MOD_OVL_BLENDER5		= BIT(15),
+	MUTEX_MOD_OVL_BLENDER6		= BIT(16),
+	MUTEX_MOD_OVL_BLENDER7		= BIT(17),
+	MUTEX_MOD_OVL_BLENDER8		= BIT(18),
 	MUTEX_MOD_OVL_OUTPROC0		= BIT(20),
+	MUTEX_MOD_OVL_OUTPROC1		= BIT(21),
 	MUTEX_MOD_OVL_MAIN_PATH		= MUTEX_MOD_OVL_EXDMA2 |
 					  MUTEX_MOD_OVL_BLENDER1 |
 					  MUTEX_MOD_OVL_BLENDER2 |
 					  MUTEX_MOD_OVL_BLENDER3 |
 					  MUTEX_MOD_OVL_BLENDER4 |
 					  MUTEX_MOD_OVL_OUTPROC0,
+	MUTEX_MOD_OVL_MAIN_PATH_DUAL	= MUTEX_MOD_OVL_MAIN_PATH,
 };
 
 enum {
 	MUTEX_MOD1_OVL_DLO_ASYNC5	= BIT(16),
+	MUTEX_MOD1_OVL_DLO_ASYNC6	= BIT(17),
 	MUTEX_MOD1_OVL_MAIN_PATH	= MUTEX_MOD1_OVL_DLO_ASYNC5,
+	MUTEX_MOD1_OVL_MAIN_PATH_DUAL	= MUTEX_MOD1_OVL_MAIN_PATH,
 };
 
 /* DISPSYS mutex module */
 enum {
 	MUTEX_MOD_DISP_CCORR0		= BIT(6),
 	MUTEX_MOD_DISP_CCORR1		= BIT(7),
+	MUTEX_MOD_DISP_CCORR2		= BIT(8),
+	MUTEX_MOD_DISP_CCORR3		= BIT(9),
 	MUTEX_MOD_DISP_DITHER0		= BIT(14),
+	MUTEX_MOD_DISP_DITHER1		= BIT(15),
 	MUTEX_MOD_DISP_DLI_ASYNC0	= BIT(16),
+	MUTEX_MOD_DISP_DLI_ASYNC1	= BIT(17),
+	MUTEX_MOD_DISP_DLI_ASYNC8	= BIT(24),
 	MUTEX_MOD_DISP_MAIN_PATH	= MUTEX_MOD_DISP_DLI_ASYNC0 |
 					  MUTEX_MOD_DISP_CCORR0 |
 					  MUTEX_MOD_DISP_CCORR1 |
 					  MUTEX_MOD_DISP_DITHER0,
-
+	MUTEX_MOD_DISP_MAIN_PATH_DUAL	= MUTEX_MOD_DISP_DLI_ASYNC8 |
+					  MUTEX_MOD_DISP_CCORR2 |
+					  MUTEX_MOD_DISP_CCORR3 |
+					  MUTEX_MOD_DISP_DITHER1,
 };
 
 enum {
 	MUTEX_MOD1_DISP_DLO_ASYNC1	= BIT(1),
+	MUTEX_MOD1_DISP_DLO_ASYNC2	= BIT(2),
 	MUTEX_MOD1_DISP_GAMMA0		= BIT(9),
+	MUTEX_MOD1_DISP_GAMMA1		= BIT(10),
 	MUTEX_MOD1_DISP_POSTMASK0	= BIT(14),
+	MUTEX_MOD1_DISP_POSTMASK1	= BIT(15),
 	MUTEX_MOD1_DISP_MDP_RSZ0	= BIT(18),
+	MUTEX_MOD1_DISP_MDP_RSZ1	= BIT(19),
 	MUTEX_MOD1_DISP_TDSHP0		= BIT(21),
+	MUTEX_MOD1_DISP_TDSHP1		= BIT(22),
 	MUTEX_MOD1_DISP_MAIN_PATH	= MUTEX_MOD1_DISP_MDP_RSZ0 |
 					  MUTEX_MOD1_DISP_TDSHP0 |
 					  MUTEX_MOD1_DISP_GAMMA0 |
 					  MUTEX_MOD1_DISP_POSTMASK0 |
 					  MUTEX_MOD1_DISP_DLO_ASYNC1,
+	MUTEX_MOD1_DISP_MAIN_PATH_DUAL	= MUTEX_MOD1_DISP_MDP_RSZ1 |
+					  MUTEX_MOD1_DISP_TDSHP1 |
+					  MUTEX_MOD1_DISP_GAMMA1 |
+					  MUTEX_MOD1_DISP_POSTMASK1 |
+					  MUTEX_MOD1_DISP_DLO_ASYNC2,
 };
 
 /* DISPSYS1 mutex module */
 enum {
 	MUTEX_MOD_DISP1_DLI_ASYNC21	= BIT(1),
+	MUTEX_MOD_DISP1_DLI_ASYNC22	= BIT(2),
+	MUTEX_MOD_DISP1_DSC2		= BIT(19),
+	MUTEX_MOD_DISP1_DSC3		= BIT(21),
 	MUTEX_MOD_DISP1_DSI0		= BIT(23),
+	MUTEX_MOD_DISP1_DSI1		= BIT(25),
 	MUTEX_MOD_DISP1_DVO		= BIT(29),
 	MUTEX_MOD_DISP1_MAIN_PATH_EDP	= MUTEX_MOD_DISP1_DLI_ASYNC21 |
+					  MUTEX_MOD_DISP1_DSC2 |
 					  MUTEX_MOD_DISP1_DVO,
 	MUTEX_MOD_DISP1_MAIN_PATH_DSI0	= MUTEX_MOD_DISP1_DLI_ASYNC21 |
 					  MUTEX_MOD_DISP1_DSI0,
+	MUTEX_MOD_DISP1_MAIN_PATH_DUAL_DSI
+					= MUTEX_MOD_DISP1_DLI_ASYNC21 |
+					  MUTEX_MOD_DISP1_DLI_ASYNC22 |
+					  MUTEX_MOD_DISP1_DSC2 |
+					  MUTEX_MOD_DISP1_DSC3 |
+					  MUTEX_MOD_DISP1_DSI0 |
+					  MUTEX_MOD_DISP1_DSI1,
 };
 
 enum {
@@ -451,12 +537,35 @@ struct disp_postmask_regs {
 
 check_member(disp_postmask_regs, size, 0x30);
 
+struct disp_dsc_regs {
+	u32 dsc_con;
+	u32 reserved0x4[5];
+	u32 pic_w;
+	u32 pic_h;
+	u32 reserved0x20;
+	u32 reserved0x24;
+	u32 chunk_size;
+};
+check_member(disp_dsc_regs, dsc_con, 0x0);
+check_member(disp_dsc_regs, pic_w, 0x18);
+check_member(disp_dsc_regs, pic_h, 0x1C);
+check_member(disp_dsc_regs, chunk_size, 0x28);
+
 static struct disp_mdp_rsz_regs *const disp_mdp_rsz0_reg	= (void *)DISP_MDP_RSZ0_BASE;
+static struct disp_mdp_rsz_regs *const disp_mdp_rsz1_reg	= (void *)DISP_MDP_RSZ1_BASE;
 static struct disp_postmask_regs *const disp_postmask0_reg	= (void *)DISP_POSTMASK0_BASE;
+static struct disp_postmask_regs *const disp_postmask1_reg	= (void *)DISP_POSTMASK1_BASE;
 static struct disp_tdshp_regs *const disp_tdshp0_reg		= (void *)DISP_TDSHP0_BASE;
+static struct disp_tdshp_regs *const disp_tdshp1_reg		= (void *)DISP_TDSHP1_BASE;
 static struct disp_ccorr_regs *const disp_ccorr0_reg		= (void *)DISP_CCORR0_BASE;
 static struct disp_ccorr_regs *const disp_ccorr1_reg		= (void *)DISP_CCORR1_BASE;
+static struct disp_ccorr_regs *const disp_ccorr2_reg		= (void *)DISP_CCORR2_BASE;
+static struct disp_ccorr_regs *const disp_ccorr3_reg		= (void *)DISP_CCORR3_BASE;
 static struct disp_gamma_regs *const disp_gamma0_reg		= (void *)DISP_GAMMA0_BASE;
+static struct disp_gamma_regs *const disp_gamma1_reg		= (void *)DISP_GAMMA1_BASE;
 static struct disp_dither_regs *const disp_dither0_reg		= (void *)DISP_DITHER0_BASE;
+static struct disp_dither_regs *const disp_dither1_reg		= (void *)DISP_DITHER1_BASE;
+static struct disp_dsc_regs *const disp_dsc2_reg		= (void *)DSC2_BASE;
+static struct disp_dsc_regs *const disp_dsc3_reg		= (void *)DSC3_BASE;
 
 #endif

From 8f3626c4b59a173647eaf70e46ff0feb75eb5d40 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Micha=C5=82=20=C5=BBygowski?= <michal.zygowski@3mdeb.com>
Date: Thu, 9 Oct 2025 12:23:40 +0200
Subject: [PATCH 2501/3886] util/amdtool: Add utility to dump useful
 information on AMD CPUs
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Add an utility similar to inteltool, which dumps useful information
for porting a board to coreboot.

TEST=Use amdtool on Gigabyte MZ33-AR1 with vendor BIOS and coreboot.

Change-Id: I34405897d0f5670038e7923f3680a28090d92821
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89492
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michał Kopeć <michal.kopec@3mdeb.com>
---
 util/amdtool/.gitignore     |   1 +
 util/amdtool/Makefile       |  85 ++++++
 util/amdtool/acpimmio.c     | 185 ++++++++++++
 util/amdtool/acpimmio.h     |  12 +
 util/amdtool/amdtool.8      |  63 ++++
 util/amdtool/amdtool.c      | 403 ++++++++++++++++++++++++++
 util/amdtool/amdtool.h      | 127 ++++++++
 util/amdtool/cpu.c          | 564 ++++++++++++++++++++++++++++++++++++
 util/amdtool/description.md |   2 +
 util/amdtool/espi.c         | 199 +++++++++++++
 util/amdtool/gpio.c         | 394 +++++++++++++++++++++++++
 util/amdtool/irq.c          | 180 ++++++++++++
 util/amdtool/lpc.c          | 126 ++++++++
 util/amdtool/psb.c          | 149 ++++++++++
 util/amdtool/smn.c          |  42 +++
 util/amdtool/smn.h          |  15 +
 util/amdtool/spi.c          | 405 ++++++++++++++++++++++++++
 17 files changed, 2952 insertions(+)
 create mode 100644 util/amdtool/.gitignore
 create mode 100644 util/amdtool/Makefile
 create mode 100644 util/amdtool/acpimmio.c
 create mode 100644 util/amdtool/acpimmio.h
 create mode 100644 util/amdtool/amdtool.8
 create mode 100644 util/amdtool/amdtool.c
 create mode 100644 util/amdtool/amdtool.h
 create mode 100644 util/amdtool/cpu.c
 create mode 100644 util/amdtool/description.md
 create mode 100644 util/amdtool/espi.c
 create mode 100644 util/amdtool/gpio.c
 create mode 100644 util/amdtool/irq.c
 create mode 100644 util/amdtool/lpc.c
 create mode 100644 util/amdtool/psb.c
 create mode 100644 util/amdtool/smn.c
 create mode 100644 util/amdtool/smn.h
 create mode 100644 util/amdtool/spi.c

diff --git a/util/amdtool/.gitignore b/util/amdtool/.gitignore
new file mode 100644
index 0000000000..2466c9f850
--- /dev/null
+++ b/util/amdtool/.gitignore
@@ -0,0 +1 @@
+amdtool
diff --git a/util/amdtool/Makefile b/util/amdtool/Makefile
new file mode 100644
index 0000000000..e2e15a030d
--- /dev/null
+++ b/util/amdtool/Makefile
@@ -0,0 +1,85 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+PROGRAM = amdtool
+
+top ?= $(abspath ../..)
+
+CC      ?= gcc
+INSTALL ?= /usr/bin/env install
+PREFIX  ?= /usr/local
+CFLAGS  ?= -O2 -g -Wall -Wextra -Wmissing-prototypes
+LDFLAGS += -lpci -lz
+
+CPPFLAGS += -I$(top)/util/amdtool
+CPPFLAGS += -I$(top)/src/commonlib/include -I$(top)/src/commonlib/bsd/include
+CPPFLAGS += -I$(top)/src/arch/x86/include
+
+OBJS = amdtool.o gpio.o acpimmio.o spi.o lpc.o psb.o smn.o cpu.o irq.o espi.o
+
+OS_ARCH	= $(shell uname)
+ifeq ($(OS_ARCH), Darwin)
+LDFLAGS += -framework DirectHW
+endif
+ifeq ($(OS_ARCH), FreeBSD)
+CPPFLAGS += -I/usr/local/include
+LDFLAGS += -L/usr/local/lib
+LIBS = -lz
+endif
+ifeq ($(OS_ARCH), NetBSD)
+CPPFLAGS += -I/usr/pkg/include
+LDFLAGS += -L/usr/pkg/lib -Wl,-rpath-link,/usr/pkg/lib -lz -lpciutils -lpci -l$(shell uname -p)
+endif
+
+all: pciutils dep $(PROGRAM)
+
+$(PROGRAM): $(OBJS)
+	$(CC) $(CFLAGS) $(CPPFLAGS) -o $(PROGRAM) $(OBJS) $(LDFLAGS)
+
+clean:
+	rm -f $(PROGRAM) *.o *~ junit.xml .dependencies
+
+distclean: clean
+	rm -f .dependencies
+
+dep:
+	@$(CC) $(CFLAGS) $(CPPFLAGS) -MM *.c > .dependencies
+
+define LIBPCI_TEST
+/* Avoid a failing test due to libpci header symbol shadowing breakage */
+#define index shadow_workaround_index
+#ifdef __NetBSD__
+#include <pciutils/pci.h>
+#else
+#include <pci/pci.h>
+#endif
+struct pci_access *pacc;
+int main(int argc, char **argv)
+{
+	(void) argc;
+	(void) argv;
+	pacc = pci_alloc();
+	return 0;
+}
+endef
+export LIBPCI_TEST
+
+pciutils:
+	@printf "\nChecking for pciutils and zlib... "
+	@echo "$$LIBPCI_TEST" > .test.c
+	@$(CC) $(CFLAGS) $(CPPFLAGS) .test.c -o .test $(LDFLAGS)	  \
+						>/dev/null 2>&1 &&	  \
+		printf "found.\n" || ( printf "not found.\n\n";		  \
+		printf "Please install pciutils-devel and zlib-devel.\n"; \
+		printf "See README for more information.\n\n";		  \
+		rm -f .test.c .test; exit 1)
+	@rm -rf .test.c .test .test.dSYM
+
+install: $(PROGRAM)
+	$(INSTALL) -d $(DESTDIR)$(PREFIX)/sbin
+	$(INSTALL) $(PROGRAM) $(DESTDIR)$(PREFIX)/sbin
+	$(INSTALL) -d $(DESTDIR)$(PREFIX)/share/man/man8
+	$(INSTALL) -p -m644 $(PROGRAM).8 $(DESTDIR)$(PREFIX)/share/man/man8
+
+.PHONY: all clean distclean dep pciutils
+
+-include .dependencies
diff --git a/util/amdtool/acpimmio.c b/util/amdtool/acpimmio.c
new file mode 100644
index 0000000000..f85565320e
--- /dev/null
+++ b/util/amdtool/acpimmio.c
@@ -0,0 +1,185 @@
+/* amdtool - dump all registers on an AMD CPU + chipset based system */
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <stdio.h>
+#include <stdlib.h>
+#include <stdint.h>
+#include <stdbool.h>
+#include <inttypes.h>
+#include <assert.h>
+#include "acpimmio.h"
+#include "amdtool.h"
+
+#define ACPIMMIO_REGION_SIZE 0x100
+
+const uint8_t *acpimmio_bar = NULL;
+size_t acpimmio_size = 0;
+
+static const io_register_t kunlun_acpi_mmio_regions[] = {
+	{ 0x0000, ACPIMMIO_REGION_SIZE, "SMB PCI" },
+	{ 0x0200, ACPIMMIO_REGION_SIZE, "SMI" },
+	{ 0x0300, ACPIMMIO_REGION_SIZE, "PMIO" },
+	{ 0x0400, ACPIMMIO_REGION_SIZE, "PMIO2" },
+	{ 0x0500, ACPIMMIO_REGION_SIZE, "BIOS RAM" },
+	{ 0x0600, ACPIMMIO_REGION_SIZE, "CMOS RAM" },
+	{ 0x0700, ACPIMMIO_REGION_SIZE, "CMOS" },
+	{ 0x0800, ACPIMMIO_REGION_SIZE, "ACPI" },
+	{ 0x0900, ACPIMMIO_REGION_SIZE, "ASF" },
+	{ 0x0a00, ACPIMMIO_REGION_SIZE, "SMB IO" },
+	{ 0x0b00, ACPIMMIO_REGION_SIZE, "WDT" },
+	{ 0x0c00, ACPIMMIO_REGION_SIZE, "HPET" },
+	{ 0x0d00, ACPIMMIO_REGION_SIZE, "IOMUX" },
+	{ 0x0e00, ACPIMMIO_REGION_SIZE, "MISC" },
+	{ 0x1000, ACPIMMIO_REGION_SIZE, "Serial debug" },
+	{ 0x1100, ACPIMMIO_REGION_SIZE, "Shadow timer" },
+	{ 0x1200, ACPIMMIO_REGION_SIZE, "Remote GPIO+IOMUX" },
+	{ 0x1300, ACPIMMIO_REGION_SIZE, "MISC2" },
+	{ 0x1400, ACPIMMIO_REGION_SIZE, "DP-VGA" },
+	{ 0x1500, ACPIMMIO_REGION_SIZE, "GPIO0" },
+	{ 0x1600, ACPIMMIO_REGION_SIZE, "GPIO1" },
+	{ 0x1700, ACPIMMIO_REGION_SIZE, "GPIO2" },
+	{ 0x1800, ACPIMMIO_REGION_SIZE, "GPIO3" },
+	{ 0x1900, ACPIMMIO_REGION_SIZE, "GPIO4" },
+	{ 0x1d00, ACPIMMIO_REGION_SIZE, "AC DC TIMER" },
+	{ 0x1e00, ACPIMMIO_REGION_SIZE, "AOAC" },
+};
+
+static uint8_t pmio_read8(uint8_t reg)
+{
+	outb(reg, 0xcd6);
+	return inb(0xcd7);
+}
+
+static void print_region(const uint32_t offset)
+{
+	unsigned int i, j;
+
+	printf("     0  1  2  3  4  5  6  7  8  9  a  b  c  d  e  f\n");
+
+	for (i = 0; i < 0x100; i += 16) {
+		printf("%02x: ", i);
+		for (j = 0; j < 16; j++) {
+			printf("%02"PRIx8, read8(acpimmio_bar + offset + i + j));
+			if (j < 15)
+				printf(" ");
+		}
+		printf("\n");
+	}
+}
+
+static void print_acpi_mmio_regions(const io_register_t *acpi_mmio_regions, size_t size)
+{
+	size_t i;
+
+	if (acpi_mmio_regions == NULL)
+		return;
+
+	for (i = 0; i < size; i++) {
+		printf("\n========== %s (offset 0x%04x) ==========\n",
+		       acpi_mmio_regions[i].name, acpi_mmio_regions[i].addr);
+		print_region(acpi_mmio_regions[i].addr);
+	}
+}
+
+static int init_acpimmio(struct pci_dev *sb)
+{
+	pciaddr_t acpimmio_phys;
+	bool acpimmio_enabled = false;
+	int smbus_rev = 0;
+
+	if (acpimmio_bar)
+		return 1;
+
+	switch (sb->device_id) {
+	case PCI_DEVICE_ID_AMD_FCH_LPC_2:
+		smbus_rev = find_smbus_dev_rev(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_FCH_SMB_2);
+		if (smbus_rev == -1)
+			return 1;
+
+		switch (smbus_rev) {
+		case 0x71:
+			acpimmio_phys = 0xfed80000;
+			acpimmio_size = 0x2000;
+			acpimmio_enabled = !!(pmio_read8(0x4) & 0x2);
+			break;
+		default:
+			printf("Error: Dumping ACPI MMIO on this southbridge is not (yet) supported.\n");
+			return 1;
+		}
+
+		break;
+	default:
+		perror("Error: Dumping ACPI MMIO on this southbridge is not (yet) supported.\n");
+		return 1;
+	}
+
+	if (!acpimmio_enabled) {
+		perror("ACPI MMIO not decoded by the soutbridge\n");
+		return 1;
+	}
+
+	if (acpimmio_phys == 0 || acpimmio_size == 0) {
+		perror("Error: Invalid ACPI MMIO address or size.\n");
+		return 1;
+	}
+
+	printf("ACPI MMIO = 0x%08"PRIx64" (size 0x%"PRIx64") (MEM)\n\n", (uint64_t)acpimmio_phys, acpimmio_size);
+	acpimmio_bar = map_physical(acpimmio_phys, acpimmio_size);
+	if (!acpimmio_bar) {
+		perror("Error mapping ACPI MMIO");
+		return 1;
+	}
+
+	return 0;
+}
+
+int print_acpimmio(struct pci_dev *sb)
+{
+	int smbus_rev = 0;
+	size_t acpimmio_regions_size = 0;
+	const io_register_t *acpi_mmio_regions = NULL;
+
+	printf("\n========== ACPI MMIO ==========\n\n");
+
+	if (init_acpimmio(sb))
+		return 1;
+
+	switch (sb->device_id) {
+	case PCI_DEVICE_ID_AMD_FCH_LPC_2:
+		smbus_rev = find_smbus_dev_rev(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_FCH_SMB_2);
+		if (smbus_rev == -1)
+			return 1;
+
+		switch (smbus_rev) {
+		case 0x71:
+			acpi_mmio_regions = kunlun_acpi_mmio_regions;
+			acpimmio_regions_size = ARRAY_SIZE(kunlun_acpi_mmio_regions);
+			break;
+		default:
+			printf("Error: Dumping ACPI MMIO on this southbridge is not (yet) supported.\n");
+			return 1;
+		}
+
+		break;
+	default:
+		perror("Error: Dumping ACPI MMIO on this southbridge is not (yet) supported.\n");
+		return 1;
+	}
+
+	print_acpi_mmio_regions(acpi_mmio_regions, acpimmio_regions_size);
+
+	return 0;
+}
+
+const uint8_t *get_acpi_mmio_bar(struct pci_dev *sb)
+{
+	init_acpimmio(sb);
+
+	return (const uint8_t *)acpimmio_bar;
+}
+
+void acpimmio_cleanup(void)
+{
+	if (acpimmio_bar)
+		unmap_physical((void *)acpimmio_bar, acpimmio_size);
+}
diff --git a/util/amdtool/acpimmio.h b/util/amdtool/acpimmio.h
new file mode 100644
index 0000000000..53582f60b6
--- /dev/null
+++ b/util/amdtool/acpimmio.h
@@ -0,0 +1,12 @@
+/* amdtool - dump all registers on an AMD CPU + chipset based system */
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef AMDTOOL_ACPIMMIO_H
+#define AMDTOOL_ACPIMMIO_H 1
+
+#include "amdtool.h"
+
+const uint8_t *get_acpi_mmio_bar(struct pci_dev *sb);
+void acpimmio_cleanup(void);
+
+#endif
diff --git a/util/amdtool/amdtool.8 b/util/amdtool/amdtool.8
new file mode 100644
index 0000000000..4595276088
--- /dev/null
+++ b/util/amdtool/amdtool.8
@@ -0,0 +1,63 @@
+.TH AMDTOOL 8
+.SH NAME
+amdtool \- a tool for dumping AMD CPU / chipset configuration parameters
+.SH SYNOPSIS
+.B amdtool \fR[\fB\-vh?gGlcMApsa\fR]
+.SH DESCRIPTION
+.B amdtool
+is a handy little tool for dumping the configuration space of AMD
+CPUs, northbridges and southbridges.
+.sp
+This tool has been developed for the coreboot project (see
+.B https://coreboot.org
+for details on coreboot).
+.SH OPTIONS
+.TP
+.B "\-h, \-\-help"
+Show a help text and exit.
+.TP
+.B "\-v, \-\-version"
+Show version information and exit.
+.TP
+.B "\-a, \-\-all"
+Dump all known information listed below.
+.TP
+.B "\-c, \-\-cpu"
+Dump CPU information and features.
+.TP
+.B "\-g, \-\-gpio"
+Dump Fusion Controller Hub (FCH) southbridge GPIO registers.
+.TP
+.B "\-G, \-\-gpio-diffs"
+Show only GPIO register differences from hardware defaults.
+.TP
+.B "\-i, \-\-irq-routing"
+Dump Fusion Controller Hub (FCH) southbridge IRQ routing registers.
+.TP
+.B "\-s, \-\-spi"
+Dump Fusion Controller Hub (FCH) southbridge SPI registers.
+.TP
+.B "\-l, \-\-lpc"
+Dump Fusion Controller Hub (FCH) southbridge LPC registers.
+.TP
+.B "\-M, \-\-msrs"
+Dump AMD CPU MSRs.
+.TP
+.B "\-A, \-\-acpimmio"
+Dump Fusion Controller Hub (FCH) southbridge ACPI MMIO registers.
+.TP
+.B "\-p, \-\-psb"
+Dump Platform Secure Boot State.
+.SH BUGS
+Please report any bugs on the coreboot mailing list
+.RB "(" https://coreboot.org/Mailinglist ")."
+.SH LICENCE
+.B amdtool
+is covered by the GNU General Public License (GPL), version 2.
+.SH COPYRIGHT
+Copyright (C) 2024 3mdeb
+.SH AUTHORS
+Michał Żygowski <michal.zygowski@3mdeb.com>
+.PP
+This manual page was written by Michał Żygowski <michal.zygowski@3mdeb.com>.
+It is licensed under the terms of the GNU GPL (version 2).
diff --git a/util/amdtool/amdtool.c b/util/amdtool/amdtool.c
new file mode 100644
index 0000000000..22306f78c0
--- /dev/null
+++ b/util/amdtool/amdtool.c
@@ -0,0 +1,403 @@
+/* amdtool - dump all registers on an AMD CPU + chipset based system */
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+#include <inttypes.h>
+#include <getopt.h>
+#include <fcntl.h>
+#include <sys/mman.h>
+#include <unistd.h>
+#include <errno.h>
+#include <limits.h>
+
+#include "acpimmio.h"
+#include "amdtool.h"
+#include "smn.h"
+
+#ifdef __NetBSD__
+#include <machine/sysarch.h>
+#endif
+
+static const struct {
+	uint16_t vendor_id, device_id;
+	char *name;
+} supported_chips_list[] = {
+	/* Host bridges/DRAM controllers (Northbridges) */
+	{ PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_BRH_ROOT_COMPLEX, "Turin Root Complex" },
+	{ PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_BRH_DATA_FABRIC_0, "Turin Data Fabric 0" },
+	{ PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_BRH_DATA_FABRIC_1, "Turin Data Fabric 1" },
+	{ PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_BRH_DATA_FABRIC_2, "Turin Data Fabric 2" },
+	{ PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_BRH_DATA_FABRIC_3, "Turin Data Fabric 3" },
+	{ PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_BRH_DATA_FABRIC_4, "Turin Data Fabric 4" },
+	{ PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_BRH_DATA_FABRIC_5, "Turin Data Fabric 5" },
+	{ PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_BRH_DATA_FABRIC_6, "Turin Data Fabric 6" },
+	{ PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_BRH_DATA_FABRIC_7, "Turin Data Fabric 7" },
+
+	/* FCHs (Southbridges) */
+	{ PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_FCH_SMB_1, "FCH SMBus Controller" },
+	{ PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_FCH_LPC_1, "FCH LPC Bridge" },
+	{ PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_FCH_SMB_2, "FCH SMBus Controller" },
+	{ PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_FCH_LPC_2, "FCH LPC Bridge" },
+};
+
+#ifndef __DARWIN__
+static int fd_mem;
+
+void *map_physical(uint64_t phys_addr, size_t len)
+{
+	void *virt_addr;
+
+	virt_addr = mmap(0, len, PROT_WRITE | PROT_READ, MAP_SHARED,
+		    fd_mem, (off_t) phys_addr);
+
+	if (virt_addr == MAP_FAILED) {
+		printf("Error mapping physical memory 0x%08" PRIx64 "[0x%zx]\n",
+			phys_addr, len);
+		return NULL;
+	}
+
+	return virt_addr;
+}
+
+void unmap_physical(void *virt_addr, size_t len)
+{
+	munmap(virt_addr, len);
+}
+#endif
+
+static struct pci_access *pacc;
+
+static struct pci_dev *pci_dev_find(uint16_t vendor, uint16_t device)
+{
+	struct pci_dev *temp;
+	struct pci_filter filter;
+
+	pci_filter_init(NULL, &filter);
+	filter.vendor = vendor;
+	filter.device = device;
+
+	for (temp = pacc->devices; temp; temp = temp->next)
+		if (pci_filter_match(&filter, temp))
+			return temp;
+
+	return NULL;
+}
+
+int find_smbus_dev_rev(uint16_t vendor, uint16_t device)
+{
+	struct pci_dev *smbus_dev = pci_dev_find(vendor, device);
+	if (!smbus_dev) {
+		printf("No SMBus device with ID %04X:%04X found.\n", vendor, device);
+		perror("ERROR: SMBus device not found.\n");
+		return -1;
+	}
+	return pci_read_byte(smbus_dev, PCI_REVISION_ID);
+}
+
+static void print_version(void)
+{
+	printf("amdtool v%s -- ", AMDTOOL_VERSION);
+	printf("Copyright (C) 2024 3mdeb\n\n");
+	printf("This program is free software: you can redistribute it and/or modify\n"
+	       "it under the terms of the GNU General Public License as published by\n"
+	       "the Free Software Foundation, version 2 of the License.\n\n"
+	       "This program is distributed in the hope that it will be useful,\n"
+	       "but WITHOUT ANY WARRANTY; without even the implied warranty of\n"
+	       "MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the\n"
+	       "GNU General Public License for more details.\n\n");
+}
+
+static void print_usage(const char *name)
+{
+	printf("usage: %s [-vh?gicspGlMAa]\n", name);
+	printf("\n"
+	     "   -v | --version:                   print the version\n"
+	     "   -h | --help:                      print this help\n\n"
+	     "   -s | --spi:                       dump southbridge spi and bios_cntrl registers\n"
+	     "   -g | --gpio:                      dump southbridge GPIO registers\n"
+	     "   -G | --gpio-diffs:                show GPIO differences from defaults\n"
+	     "   -i | --irq-routing                dump IRQ routing registers\n"
+	     "   -l | --lpc:                       dump southbridge LPC/eSPI Interface registers\n\n"
+	     "   -c | --cpu:                       dump CPU information and features\n\n"
+	     "   -M | --msrs:                      dump CPU MSRs\n"
+	     "   -A | --acpimmio:                  dump southbridge ACPI MMIO registers\n"
+	     "   -p | --psb:                       dump Platform Secure Boot state\n"
+	     "   -a | --all:                       dump all known (safe) registers\n"
+	     "\n");
+	exit(1);
+}
+
+static void print_system_info(struct pci_dev *nb, struct pci_dev *sb,
+			      struct pci_dev *smb, struct pci_dev *gfx)
+{
+	unsigned int id, i;
+	char *sbname = "unknown", *nbname = "unknown", *gfxname = "unknown", *smbname = "unknown";
+
+	id = cpuid(1);
+
+	/* Determine names */
+	for (i = 0; i < ARRAY_SIZE(supported_chips_list); i++) {
+		if (nb->device_id == supported_chips_list[i].device_id)
+			nbname = supported_chips_list[i].name;
+		if (sb->device_id == supported_chips_list[i].device_id)
+			sbname = supported_chips_list[i].name;
+		if (smb->device_id == supported_chips_list[i].device_id)
+			smbname = supported_chips_list[i].name;
+	}
+	if (gfx) {
+		for (i = 0; i < ARRAY_SIZE(supported_chips_list); i++)
+			if (gfx->device_id == supported_chips_list[i].device_id)
+				gfxname = supported_chips_list[i].name;
+	}
+	printf("CPU: ID 0x%x, Processor Type 0x%x, Family 0x%x, Model 0x%x, Stepping 0x%x\n",
+			id, (id >> 12) & 0x3, ((id >> 8) & 0xf) + ((id >> 20) & 0xff),
+			((id >> 12) & 0xf0) + ((id >> 4) & 0xf), (id & 0xf));
+
+	printf("Northbridge: %04x:%04x (%s)\n",
+		nb->vendor_id, nb->device_id, nbname);
+
+	printf("Southbridge SMBus: %04x:%04x rev %02x (%s)\n",
+		smb->vendor_id, smb->device_id, pci_read_byte(smb, PCI_REVISION_ID), smbname);
+
+	printf("Southbridge LPC: %04x:%04x rev %02x (%s)\n",
+		sb->vendor_id, sb->device_id, pci_read_byte(sb, PCI_REVISION_ID), sbname);
+
+	if (gfx)
+		printf("Integrated Graphics: %04x:%04x (%s)\n",
+		       gfx->vendor_id, gfx->device_id, gfxname);
+}
+
+int main(int argc, char *argv[])
+{
+	struct pci_dev *sb = NULL, *nb, *gfx = NULL, *smb = NULL, *dev;
+	int opt, option_index = 0;
+
+	int dump_gpios = 0, dump_coremsrs = 0, dump_acpimmio = 0, dump_cpu = 0;
+	int dump_spi = 0, dump_lpc = 0, show_gpio_diffs = 0, dump_psb = 0, dump_irq = 0;
+
+	static struct option long_options[] = {
+		{"version", 0, 0, 'v'},
+		{"help", 0, 0, 'h'},
+		{"gpios", 0, 0, 'g'},
+		{"gpio-diffs", 0, 0, 'G'},
+		{"irq-routing", 0, 0, 'i'},
+		{"lpc", 0, 0, 'l'},
+		{"cpu", 0, 0, 'c'},
+		{"msrs", 0, 0, 'M'},
+		{"acpimmio", 0, 0, 'A'},
+		{"psb", 0, 0, 'p'},
+		{"spi", 0, 0, 's'},
+		{"all", 0, 0, 'a'},
+		{0, 0, 0, 0}
+	};
+
+	while ((opt = getopt_long(argc, argv, "vh?gGilcMApsa",
+				  long_options, &option_index)) != EOF) {
+		switch (opt) {
+		case 'v':
+			print_version();
+			exit(0);
+			break;
+		case 'g':
+			dump_gpios = 1;
+			break;
+		case 'G':
+			show_gpio_diffs = 1;
+			break;
+		case 'i':
+			dump_irq = 1;
+			break;
+		case 'l':
+			dump_lpc = 1;
+			break;
+		case 'c':
+			dump_cpu = 1;
+			break;
+		case 'M':
+			dump_coremsrs = 1;
+			break;
+		case 'A':
+			dump_acpimmio = 1;
+			break;
+		case 'p':
+			dump_psb = 1;
+			break;
+		case 's':
+			dump_spi = 1;
+			break;
+		case 'a':
+			dump_gpios = 1;
+			show_gpio_diffs = 1;
+			dump_irq = 1;
+			dump_lpc = 1;
+			dump_cpu = 1;
+			dump_coremsrs = 1;
+			dump_acpimmio = 1;
+			dump_spi = 1;
+			dump_psb = 1;
+			break;
+		case 'h':
+		case '?':
+		default:
+			print_usage(argv[0]);
+			exit(0);
+			break;
+		}
+	}
+
+#if defined(__FreeBSD__)
+	if (open("/dev/io", O_RDWR) < 0) {
+		perror("/dev/io");
+#elif defined(__NetBSD__)
+# ifdef __i386__
+	if (i386_iopl(3)) {
+		perror("iopl");
+# else
+	if (x86_64_iopl(3)) {
+		perror("iopl");
+# endif
+#else
+	if (iopl(3)) {
+		perror("iopl");
+#endif
+		printf("You need to be root.\n");
+		exit(1);
+	}
+
+#ifndef __DARWIN__
+	if ((fd_mem = open("/dev/mem", O_RDWR)) < 0) {
+		perror("Can not open /dev/mem");
+		exit(1);
+	}
+#endif
+
+	pacc = pci_alloc();
+	pacc->method = PCI_ACCESS_I386_TYPE1;
+	pci_init(pacc);
+	pci_scan_bus(pacc);
+
+	/* Find the required devices */
+	for (dev = pacc->devices; dev; dev = dev->next) {
+		pci_fill_info(dev, PCI_FILL_CLASS);
+		/* The ISA/LPC bridge can be 0x1f, 0x07, or 0x04 so we probe. */
+		if (dev->device_class == 0x0601) { /* ISA/LPC bridge */
+			if (sb == NULL) {
+				sb = dev;
+			} else {
+				fprintf(stderr, "Multiple devices with class ID"
+					" 0x0601, using %02x%02x:%02x.%02x\n",
+					sb->domain, sb->bus, sb->dev, sb->func);
+				break;
+			}
+		}
+	}
+
+	if (!sb) {
+		printf("No southbridge found.\n");
+		exit(1);
+	}
+
+	pci_fill_info(sb, PCI_FILL_IDENT | PCI_FILL_BASES | PCI_FILL_CLASS);
+
+	if (sb->vendor_id != PCI_VENDOR_ID_AMD) {
+		printf("Not an AMD southbridge.\n");
+		exit(1);
+	}
+
+	nb = pci_get_dev(pacc, 0, 0, 0x00, 0);
+	if (!nb) {
+		printf("No northbridge found.\n");
+		exit(1);
+	}
+
+	pci_fill_info(nb, PCI_FILL_IDENT | PCI_FILL_BASES | PCI_FILL_CLASS);
+
+	if (nb->vendor_id != PCI_VENDOR_ID_AMD) {
+		printf("Not an AMD northbridge.\n");
+		exit(1);
+	}
+
+	smb = pci_get_dev(pacc, 0, 0, 0x14, 0);
+	if (!smb) {
+		printf("No SMBus Controller found.\n");
+		exit(1);
+	}
+
+	pci_fill_info(smb, PCI_FILL_IDENT | PCI_FILL_BASES | PCI_FILL_CLASS);
+
+	if (smb->vendor_id != PCI_VENDOR_ID_AMD) {
+		printf("Not an AMD southbridge.\n");
+		exit(1);
+	}
+
+	gfx = pci_get_dev(pacc, 0, 0, 0x02, 0);
+	if (gfx) {
+		pci_fill_info(gfx, PCI_FILL_IDENT | PCI_FILL_BASES |
+				   PCI_FILL_CLASS);
+		if ((gfx->device_class & 0xff00) != 0x0300)
+			gfx = NULL;
+		else if (gfx->vendor_id != PCI_VENDOR_ID_AMD)
+			gfx = NULL;
+	}
+
+	print_system_info(nb, sb, smb, gfx);
+
+	init_smn(nb);
+
+	/* Now do the deed */
+
+	if (dump_lpc) {
+		print_lpc(sb);
+		printf("\n\n");
+		print_espi(sb);
+		printf("\n\n");
+	}
+
+	if (dump_cpu) {
+		print_cpu_info();
+		printf("\n\n");
+	}
+
+	if (dump_coremsrs) {
+		print_amd_msrs();
+		printf("\n\n");
+	}
+
+	if (dump_acpimmio) {
+		print_acpimmio(sb);
+		printf("\n\n");
+	}
+
+	if (dump_gpios) {
+		print_gpios(sb, 1, show_gpio_diffs);
+		printf("\n\n");
+	} else if (show_gpio_diffs) {
+		print_gpios(sb, 0, show_gpio_diffs);
+		printf("\n\n");
+	}
+
+	if (dump_spi) {
+		print_spi(sb);
+		printf("\n\n");
+	}
+
+	if (dump_irq) {
+		print_irq_routing(sb);
+		printf("\n\n");
+	}
+
+	if (dump_psb) {
+		print_psb(nb);
+		printf("\n\n");
+	}
+
+	/* Clean up */
+	acpimmio_cleanup();
+	pci_free_dev(nb);
+	/* `sb` wasn't allocated by pci_get_dev() */
+	pci_cleanup(pacc);
+
+	return 0;
+}
diff --git a/util/amdtool/amdtool.h b/util/amdtool/amdtool.h
new file mode 100644
index 0000000000..524371235e
--- /dev/null
+++ b/util/amdtool/amdtool.h
@@ -0,0 +1,127 @@
+/* amdtool - dump all registers on an AMD CPU + chipset based system */
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef AMDTOOL_H
+#define AMDTOOL_H 1
+
+#if defined(__linux__)
+#include <linux/stddef.h>
+#endif
+#include <arch/mmio.h>
+#include <commonlib/helpers.h>
+
+#include <stdint.h>
+
+#if defined(__linux__)
+#include <sys/io.h>
+#endif
+#if (defined(__MACH__) && defined(__APPLE__))
+/* DirectHW is available here: https://www.coreboot.org/DirectHW */
+#define __DARWIN__
+#include <DirectHW/DirectHW.h>
+#endif
+
+#ifdef __NetBSD__
+#include <pciutils/pci.h>
+#else
+#include <pci/pci.h>
+#endif
+
+/* This #include is needed for freebsd_{rd,wr}msr. */
+#if defined(__FreeBSD__)
+#include <machine/cpufunc.h>
+#endif
+
+#ifdef __NetBSD__
+static inline uint8_t inb(unsigned port)
+{
+	uint8_t data;
+	__asm volatile("inb %w1,%0" : "=a" (data) : "d" (port));
+	return data;
+}
+static inline uint16_t inw(unsigned port)
+{
+	uint16_t data;
+	__asm volatile("inw %w1,%0": "=a" (data) : "d" (port));
+	return data;
+}
+static inline uint32_t inl(unsigned port)
+{
+	uint32_t data;
+	__asm volatile("inl %w1,%0": "=a" (data) : "d" (port));
+	return data;
+}
+
+static inline void outb(uint8_t value, uint16_t port)
+{
+	__asm__ __volatile__ ("outb %0, %w1" : : "a" (value), "d" (port));
+}
+
+static inline void outw(uint16_t value, uint16_t port)
+{
+	__asm__ __volatile__ ("outw %0, %w1" : : "a" (value), "d" (port));
+}
+
+static inline void outl(uint32_t value, uint16_t port)
+{
+	__asm__ __volatile__ ("outl %0, %w1" : : "a" (value), "d" (port));
+}
+#endif
+
+#define AMDTOOL_VERSION "0.1"
+
+#define PCI_VENDOR_ID_AMD			0x1022
+
+#define PCI_DEVICE_ID_AMD_FCH_SMB_1		0x780b
+#define PCI_DEVICE_ID_AMD_FCH_LPC_1		0x780e
+#define PCI_DEVICE_ID_AMD_FCH_SMB_2		0x790b
+#define PCI_DEVICE_ID_AMD_FCH_LPC_2		0x790e
+
+#define PCI_DEVICE_ID_AMD_BRH_ROOT_COMPLEX	0x153a
+#define PCI_DEVICE_ID_AMD_BRH_DATA_FABRIC_0	0x12c0
+#define PCI_DEVICE_ID_AMD_BRH_DATA_FABRIC_1	0x12c1
+#define PCI_DEVICE_ID_AMD_BRH_DATA_FABRIC_2	0x12c2
+#define PCI_DEVICE_ID_AMD_BRH_DATA_FABRIC_3	0x12c3
+#define PCI_DEVICE_ID_AMD_BRH_DATA_FABRIC_4	0x12c4
+#define PCI_DEVICE_ID_AMD_BRH_DATA_FABRIC_5	0x12c5
+#define PCI_DEVICE_ID_AMD_BRH_DATA_FABRIC_6	0x12c6
+#define PCI_DEVICE_ID_AMD_BRH_DATA_FABRIC_7	0x12c7
+
+#define CPUID_TURIN_C1				0x00b00f21
+
+#if !defined(__DARWIN__) && !defined(__FreeBSD__)
+typedef struct { uint32_t hi, lo; } msr_t;
+#endif
+#if defined (__FreeBSD__)
+/* FreeBSD already has conflicting definitions for wrmsr/rdmsr. */
+#undef rdmsr
+#undef wrmsr
+#define rdmsr freebsd_rdmsr
+#define wrmsr freebsd_wrmsr
+typedef struct { uint32_t hi, lo; } msr_t;
+#endif
+typedef struct { uint16_t addr; int size; char *name; } io_register_t;
+typedef struct {
+	uint32_t eax;
+	uint32_t ebx;
+	uint32_t ecx;
+	uint32_t edx;
+} cpuid_result_t;
+
+void *map_physical(uint64_t phys_addr, size_t len);
+void unmap_physical(void *virt_addr, size_t len);
+
+int find_smbus_dev_rev(uint16_t vendor, uint16_t device);
+
+uint32_t cpuid(uint32_t eax);
+int print_amd_msrs(void);
+int print_cpu_info(void);
+int print_lpc(struct pci_dev *sb);
+int print_espi(struct pci_dev *sb);
+int print_gpios(struct pci_dev *sb, int show_all, int show_diffs);
+int print_spi(struct pci_dev *sb);
+int print_acpimmio(struct pci_dev *sb);
+void print_psb(struct pci_dev *nb);
+int print_irq_routing(struct pci_dev *sb);
+
+#endif
diff --git a/util/amdtool/cpu.c b/util/amdtool/cpu.c
new file mode 100644
index 0000000000..73c5495e17
--- /dev/null
+++ b/util/amdtool/cpu.c
@@ -0,0 +1,564 @@
+/* amdtool - dump all registers on an AMD CPU + chipset based system */
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <fcntl.h>
+#include <unistd.h>
+#include <stdbool.h>
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+#include <errno.h>
+#include <limits.h>
+
+#include "amdtool.h"
+#include "smn.h"
+
+#ifdef __x86_64__
+# define BREG	"%%rbx"
+#else
+# define BREG	"%%ebx"
+#endif
+
+typedef struct {
+	uint32_t number;
+	char *name;
+} msr_entry_t;
+
+int fd_msr;
+
+uint32_t cpuid(uint32_t eax)
+{
+	uint32_t ret;
+
+#if defined(__PIC__) || defined(__DARWIN__) && !defined(__LP64__)
+	asm volatile (
+		"push " BREG "\n\t"
+		"cpuid\n\t"
+		"pop " BREG "\n\t"
+		: "=a" (ret) : "a" (eax) : "%ecx", "%edx"
+	);
+#else
+	asm ("cpuid" : "=a" (ret) : "a" (eax) : "%ebx", "%ecx", "%edx");
+#endif
+
+	return ret;
+}
+
+static inline cpuid_result_t cpuid_ext(uint32_t eax, unsigned int ecx)
+{
+	cpuid_result_t result;
+
+#ifndef __DARWIN__
+	asm volatile (
+			"mov %%ebx, %%edi;"
+			"cpuid;"
+			"mov %%ebx, %%esi;"
+			"mov %%edi, %%ebx;"
+			: "=a" (result.eax),
+			"=S" (result.ebx),
+			"=c" (result.ecx),
+			"=d" (result.edx)
+			: "0" (eax), "2" (ecx)
+			: "edi");
+#endif
+	return result;
+}
+
+#ifndef __DARWIN__
+int msr_readerror = 0;
+
+static msr_t rdmsr(unsigned int addr)
+{
+	uint32_t buf[2];
+	msr_t msr = { 0xffffffff, 0xffffffff };
+
+	if (lseek(fd_msr, (off_t) addr, SEEK_SET) == -1) {
+		perror("Could not lseek() to MSR");
+		close(fd_msr);
+		exit(1);
+	}
+
+	if (read(fd_msr, buf, 8) == 8) {
+		msr.lo = buf[0];
+		msr.hi = buf[1];
+		return msr;
+	}
+
+	if (errno == 5) {
+		printf(" (*)"); // Not all bits of the MSR could be read
+		msr_readerror = 1;
+	} else {
+		// A severe error.
+		perror("Could not read() MSR");
+		close(fd_msr);
+		exit(1);
+	}
+
+	return msr;
+}
+
+static int open_and_seek(int cpu, unsigned long msr, int mode, int *fd)
+{
+	char dev[32];
+	char temp_string[50];
+
+	snprintf(dev, sizeof(dev), "/dev/cpu/%d/msr", cpu);
+	*fd = open(dev, mode);
+
+	if (*fd < 0) {
+		snprintf(temp_string, sizeof(temp_string), "open(\"%s\")", dev);
+		perror(temp_string);
+		return -1;
+	}
+
+	if (lseek(*fd, msr, SEEK_SET) == (off_t)-1) {
+		snprintf(temp_string, sizeof(temp_string), "lseek(%lu)", msr);
+		perror(temp_string);
+		close(*fd);
+		return -1;
+	}
+
+	return 0;
+}
+
+static msr_t rdmsr_from_cpu(int cpu, unsigned long addr)
+{
+	int fd;
+	msr_t msr = { 0xffffffff, 0xffffffff };
+	uint32_t buf[2];
+	char temp_string[50];
+
+	if (open_and_seek(cpu, addr, O_RDONLY, &fd) < 0) {
+		snprintf(temp_string, sizeof(temp_string),
+			"Could not read MSR for CPU#%d", cpu);
+		perror(temp_string);
+	}
+
+	if (read(fd, buf, 8) == 8) {
+		msr.lo = buf[0];
+		msr.hi = buf[1];
+	}
+
+	close(fd);
+
+	return msr;
+}
+
+static int get_number_of_cpus(void)
+{
+	return sysconf(_SC_NPROCESSORS_ONLN);
+}
+
+static bool is_sme_supported(void)
+{
+	cpuid_result_t cpuid_regs;
+
+	if (cpuid(0x80000000) < 0x8000001f)
+		return false;
+
+	cpuid_regs = cpuid_ext(0x8000001f, 0x0);
+	return !!(cpuid_regs.eax & 1);
+}
+
+static bool is_sme_enabled(int cpunum)
+{
+	msr_t data;
+	data = rdmsr_from_cpu(cpunum, 0xC0010010);
+	return !!(data.lo & (1 << 23));
+}
+
+#endif
+
+static int print_sme(void)
+{
+	int error = -1;
+#ifndef __DARWIN__
+	int ncpus = get_number_of_cpus();
+	int i = 0;
+	bool sme_supported;
+
+	printf("\n============= Dumping AMD SME status =============\n");
+
+	if (ncpus < 1) {
+		perror("Failed to get number of CPUs");
+		error = -1;
+	} else {
+		sme_supported = is_sme_supported();
+		for (i = 0; i < ncpus ; i++) {
+
+			printf("------------- CPU %d ----------------\n", i);
+			printf("SME supported             : %s\n",
+					sme_supported ? "YES" : "NO");
+			if (sme_supported)
+				printf("SME enabled               : %s\n",
+					is_sme_enabled(i) ? "YES" : "NO");
+		}
+		error = 0;
+	}
+	printf("====================================================\n\n");
+#endif
+	return error;
+}
+
+static bool is_sev_supported(void)
+{
+	cpuid_result_t cpuid_regs;
+
+	if (cpuid(0x80000000) < 0x8000001f)
+		return false;
+
+	cpuid_regs = cpuid_ext(0x8000001f, 0x0);
+	return !!(cpuid_regs.eax & 2);
+}
+
+static bool is_sev_es_supported(void)
+{
+	cpuid_result_t cpuid_regs;
+
+	if (cpuid(0x80000000) < 0x8000001f)
+		return false;
+
+	cpuid_regs = cpuid_ext(0x8000001f, 0x0);
+	return !!(cpuid_regs.eax & 8);
+}
+
+static bool is_sev_snp_supported(void)
+{
+	cpuid_result_t cpuid_regs;
+
+	if (cpuid(0x80000000) < 0x8000001f)
+		return false;
+
+	cpuid_regs = cpuid_ext(0x8000001f, 0x0);
+	return !!(cpuid_regs.eax & 0x10);
+}
+
+static bool is_sev_enabled(int cpunum)
+{
+	msr_t data;
+
+	data = rdmsr_from_cpu(cpunum, 0xC0010131);
+	return !!(data.lo & 1);
+}
+
+static bool is_sev_es_enabled(int cpunum)
+{
+	msr_t data;
+
+	data = rdmsr_from_cpu(cpunum, 0xC0010131);
+	return !!(data.lo & 2);
+}
+
+static bool is_sev_snp_enabled(int cpunum)
+{
+	msr_t data;
+
+	data = rdmsr_from_cpu(cpunum, 0xC0010131);
+	return !!(data.lo & 4);
+}
+
+static unsigned int get_sev_max_guest_num(void)
+{
+	cpuid_result_t cpuid_regs;
+
+	cpuid_regs = cpuid_ext(0x8000001f, 0x0);
+	return cpuid_regs.ecx;
+}
+
+static unsigned int get_sev_min_asid(void)
+{
+	cpuid_result_t cpuid_regs;
+
+	cpuid_regs = cpuid_ext(0x8000001f, 0x0);
+	return cpuid_regs.edx;
+}
+
+static int print_sev(void)
+{
+	int error = -1;
+#ifndef __DARWIN__
+	int ncpus = get_number_of_cpus();
+	int i = 0;
+	bool sev_supported, sev_es_supported, sev_snp_supported;
+	unsigned int max_guest, min_asid;
+
+	printf("\n============= Dumping AMD SEV status =============\n");
+
+	if (ncpus < 1) {
+		perror("Failed to get number of CPUs");
+		error = -1;
+	} else {
+		/*
+		 * The following use CPUID, so should be the same for each core
+		 * in the scope of processor.
+		 */
+		sev_supported = is_sev_supported();
+		sev_es_supported = is_sev_es_supported();
+		sev_snp_supported = is_sev_snp_supported();
+		if (sev_supported) {
+			max_guest = get_sev_max_guest_num();
+			min_asid = get_sev_min_asid();
+		}
+
+		for (i = 0; i < ncpus ; i++) {
+			printf("------------- CPU %d ----------------\n", i);
+			printf("SEV supported             : %s\n",
+					sev_supported ? "YES" : "NO");
+			if (sev_supported) {
+				printf("Max SEV encrypted guests  : %u\n",
+					max_guest);
+				printf("Min SEV ASID              : %u\n",
+					min_asid);
+				printf("SEV enabled               : %s\n",
+					is_sev_enabled(i) ? "YES" : "NO");
+			}
+			printf("SEV-ES supported          : %s\n",
+					sev_es_supported ? "YES" : "NO");
+			if (sev_es_supported)
+				printf("SEV-ES enabled            : %s\n",
+					is_sev_es_enabled(i) ? "YES" : "NO");
+			printf("SEV-SNP supported         : %s\n",
+					sev_snp_supported ? "YES" : "NO");
+			if (sev_snp_supported)
+				printf("SEV-SNP enabled           : %s\n",
+					is_sev_snp_enabled(i) ? "YES" : "NO");
+		}
+		error = 0;
+	}
+	printf("====================================================");
+#endif
+	return error;
+}
+
+static void get_cpu_brand_string(char *cpu_string)
+{
+	u32 tmp[13];
+	cpuid_result_t res;
+	const char *str = "Unknown Processor Name";
+	int i, j;
+
+	if (cpuid(0x80000000) >= 0x80000004) {
+		j = 0;
+		for (i = 0; i < 3; i++) {
+			res = cpuid_ext(0x80000002 + i, 0x0);
+			tmp[j++] = res.eax;
+			tmp[j++] = res.ebx;
+			tmp[j++] = res.ecx;
+			tmp[j++] = res.edx;
+		}
+		tmp[12] = 0;
+		str = (const char *)tmp;
+	}
+
+	strcpy(cpu_string, str);
+}
+
+#define CPU_BRAND_STRING_LEN 48
+
+static int print_cpu_features(void)
+{
+	int error = -1;
+#ifndef __DARWIN__
+	cpuid_result_t cpuid_regs;
+
+	printf("\n============= AMD CPU features =============\n");
+
+	if (cpuid(0x80000000) >= 0x80000001) {
+		cpuid_regs = cpuid_ext(0x80000001, 0x0);
+		printf("SVM supported             : %s\n",
+			cpuid_regs.ecx & (1 << 2) ? "YES" : "NO");
+		printf("SKINIT supported          : %s\n",
+			cpuid_regs.ecx & (1 << 12) ? "YES" : "NO");
+	}
+
+	error = 0;
+
+	printf("====================================================\n");
+#endif
+	return error;
+}
+
+int print_cpu_info(void)
+{
+	int ret;
+	char brand_string[CPU_BRAND_STRING_LEN + 1];
+
+	get_cpu_brand_string(brand_string);
+	printf("CPU brand string: %s\n", brand_string);
+
+	ret = print_cpu_features();
+	ret += print_sme();
+	ret += print_sev();
+
+	return ret;
+}
+
+static const msr_entry_t common_msrs[] = {
+	{ 0x001b, "IA32_APIC_BASE" },
+	{ 0x008b, "MICROCODE_PATCH_LEVEL" },
+	{ 0x00fe, "IA32_MTRRCAP" },
+	{ 0x0179, "IA32_MCG_CAP" },
+	{ 0x017a, "IA32_MCG_STATUS" },
+	{ 0x017b, "IA32_MCG_CONTROL" },
+	{ 0x01d9, "IA32_DEBUGCTL" },
+	{ 0x0200, "IA32_MTRR_PHYSBASE0" },
+	{ 0x0201, "IA32_MTRR_PHYSMASK0" },
+	{ 0x0202, "IA32_MTRR_PHYSBASE1" },
+	{ 0x0203, "IA32_MTRR_PHYSMASK1" },
+	{ 0x0204, "IA32_MTRR_PHYSBASE2" },
+	{ 0x0205, "IA32_MTRR_PHYSMASK2" },
+	{ 0x0206, "IA32_MTRR_PHYSBASE3" },
+	{ 0x0207, "IA32_MTRR_PHYSMASK3" },
+	{ 0x0208, "IA32_MTRR_PHYSBASE4" },
+	{ 0x0209, "IA32_MTRR_PHYSMASK4" },
+	{ 0x020a, "IA32_MTRR_PHYSBASE5" },
+	{ 0x020b, "IA32_MTRR_PHYSMASK5" },
+	{ 0x020c, "IA32_MTRR_PHYSBASE6" },
+	{ 0x020d, "IA32_MTRR_PHYSMASK6" },
+	{ 0x020e, "IA32_MTRR_PHYSBASE7" },
+	{ 0x020f, "IA32_MTRR_PHYSMASK7" },
+	{ 0x0250, "IA32_MTRR_FIX64K_00000" },
+	{ 0x0258, "IA32_MTRR_FIX16K_80000" },
+	{ 0x0259, "IA32_MTRR_FIX16K_A0000" },
+	{ 0x0268, "IA32_MTRR_FIX4K_C0000" },
+	{ 0x0269, "IA32_MTRR_FIX4K_C8000" },
+	{ 0x026a, "IA32_MTRR_FIX4K_D0000" },
+	{ 0x026b, "IA32_MTRR_FIX4K_D8000" },
+	{ 0x026c, "IA32_MTRR_FIX4K_E0000" },
+	{ 0x026d, "IA32_MTRR_FIX4K_E8000" },
+	{ 0x026e, "IA32_MTRR_FIX4K_F0000" },
+	{ 0x026f, "IA32_MTRR_FIX4K_F8000" },
+	{ 0x0277, "IA32_PAT" },
+	{ 0x02ff, "IA32_MTRR_DEF_TYPE" },
+	{ 0xc0000080, "EFER" },
+	{ 0xc0010010, "SYS_CFG" },
+	{ 0xc0010015, "HWCR" },
+	{ 0xc0010016, "IORR_BASE0" },
+	{ 0xc0010017, "IORR_MASK0" },
+	{ 0xc0010018, "IORR_BASE1" },
+	{ 0xc0010019, "IORR_MASK1" },
+	{ 0xc001001a, "TOP_MEM" },
+	{ 0xc001001d, "TOM2" },
+	{ 0xc0010030, "PROCESSOR_NAME_STRING0" },
+	{ 0xc0010031, "PROCESSOR_NAME_STRING1" },
+	{ 0xc0010032, "PROCESSOR_NAME_STRING2" },
+	{ 0xc0010033, "PROCESSOR_NAME_STRING3" },
+	{ 0xc0010034, "PROCESSOR_NAME_STRING4" },
+	{ 0xc0010035, "PROCESSOR_NAME_STRING5" },
+	{ 0xc0010050, "SMI_ON_IO_TRAP0" },
+	{ 0xc0010051, "SMI_ON_IO_TRAP1" },
+	{ 0xc0010052, "SMI_ON_IO_TRAP2" },
+	{ 0xc0010053, "SMI_ON_IO_TRAP3" },
+	{ 0xc0010054, "SMI_ON_IO_TRAP_CTL_STS" },
+	{ 0xc0010056, "SMI_TRIGGER_IO_CYCLE" },
+	{ 0xc0010058, "MMCONF_BASE_ADDR" },
+	{ 0xc0010061, "PSTATE_CURRENT_LIMIT" },
+	{ 0xc0010062, "PSTATE_CNTRL" },
+	{ 0xc0010063, "PSTATE_STATUS" },
+	{ 0xc0010064, "PSTATE0_DEF" },
+	{ 0xc0010065, "PSTATE1_DEF" },
+	{ 0xc0010066, "PSTATE2_DEF" },
+	{ 0xc0010067, "PSTATE3_DEF" },
+	{ 0xc0010068, "PSTATE4_DEF" },
+	{ 0xc0010069, "PSTATE5_DEF" },
+	{ 0xc001006a, "PSTATE6_DEF" },
+	{ 0xc001006b, "PSTATE7_DEF" },
+	{ 0xc0010073, "CSTATE_BASE_ADDR" },
+	{ 0xc0010074, "CPU_WDT_CFG" },
+	{ 0xc0010111, "SMM_BASE" },
+	{ 0xc0010112, "SMM_TSEG_BASE" },
+	{ 0xc0010113, "SMM_TSEG_MASK" },
+	{ 0xc0010114, "VM_CR" },
+	{ 0xc0010118, "SVM_LOCK_KEY" },
+	{ 0xc0010119, "SMM_LOCK_KEY" },
+	{ 0xc0010131, "SEV_STATUS" },
+	{ 0xc0010140, "OSVW_ID_LENGTH" },
+	{ 0xc0010141, "OSVW_STATUS" },
+	{ 0xc0010292, "PWR_MNGMNT_MISC" },
+	{ 0xc0010293, "HW_PSTATE_STATUS" },
+	{ 0xc0010294, "CSTATE_POLICY" },
+	{ 0xc0010296, "CSTATE_CONFIG" },
+	{ 0xc0010297, "PWR_MNGMNT_DEFAULT" },
+	{ 0xc0010299, "RAPL_PWR_UNIT" },
+	{ 0xc001029a, "CORE_ENERGY_STS" },
+	{ 0xc001029b, "PKG_ENERGY_STS" },
+	{ 0xc00102b0, "CPPC_CAP1" },
+	{ 0xc00102b1, "CPPC_ENABLE" },
+	{ 0xc00102b2, "CPPC_CAP2" },
+	{ 0xc00102b3, "CPPC_REQUEST" },
+	{ 0xc00102b4, "CPPC_STATUS" },
+	{ 0xc0011002, "CPUID_7_FEATURES" },
+	{ 0xc0011003, "CPUID_PWR_THERM" },
+	{ 0xc0011004, "CPUID_FEATURES" },
+	{ 0xc0011005, "CPUID_EXT_FEATURES" },
+	{ 0xc001100c, "NODE_ID/SCRATCH" },
+	{ 0xC0011020, "LS_CFG" },
+	{ 0xC0011021, "IC_CFG" },
+	{ 0xc0011022, "DC_CFG" },
+	{ 0xc0011023, "TW_CFG" },
+	{ 0xc0011028, "FP_CFG" },
+	{ 0xc0011029, "ME_CFG" },
+	{ 0xc001102a, "BU_CFG2" },
+	{ 0xc001102b, "L2_PFCFG" },
+	{ 0xC001102d, "LS_CFG2" },
+	{ 0xc001102e, "BP_CFG" },
+	{ 0xc00110a2, "PSP_ADDR" },
+};
+
+int print_amd_msrs(void)
+{
+	unsigned int i, id;
+	msr_t msr;
+
+	typedef struct {
+		unsigned int model;
+		const msr_entry_t *global_msrs;
+		unsigned int num_global_msrs;
+	} cpu_t;
+
+	cpu_t cpulist[] = {
+		{ CPUID_TURIN_C1, common_msrs, ARRAY_SIZE(common_msrs) },
+	};
+
+	cpu_t *cpu = NULL;
+
+	/* Get CPU family, model and stepping */
+	id = cpuid(1);
+	for (i = 0; i < ARRAY_SIZE(cpulist); i++) {
+		if(cpulist[i].model == id) {
+			cpu = &cpulist[i];
+			break;
+		}
+	}
+
+	if (!cpu) {
+		printf("Error: Dumping MSRs on this CPU (0x%06x) is not (yet) supported.\n", id);
+		return -1;
+	}
+
+#ifndef __DARWIN__
+	fd_msr = open("/dev/cpu/0/msr", O_RDWR);
+	if (fd_msr < 0) {
+		perror("Error while opening /dev/cpu/0/msr");
+		printf("Did you run 'modprobe msr'?\n");
+		return -1;
+	}
+#endif
+
+	printf("\n===================== MSRs =====================\n");
+
+	for (i = 0; i < cpu->num_global_msrs; i++) {
+		msr = rdmsr(cpu->global_msrs[i].number);
+		printf(" MSR 0x%08X = 0x%08X:0x%08X (%s)\n",
+		       cpu->global_msrs[i].number, msr.hi, msr.lo,
+		       cpu->global_msrs[i].name);
+	}
+
+#ifndef __DARWIN__
+	close(fd_msr);
+
+	if (msr_readerror)
+		printf("\n(*) Some MSRs could not be read. The marked values are unreliable.\n");
+#endif
+	return 0;
+}
diff --git a/util/amdtool/description.md b/util/amdtool/description.md
new file mode 100644
index 0000000000..ad191e3afe
--- /dev/null
+++ b/util/amdtool/description.md
@@ -0,0 +1,2 @@
+Provides information about the AMD CPU/chipset hardware configuration
+(register contents, MSRs, etc). `C`
diff --git a/util/amdtool/espi.c b/util/amdtool/espi.c
new file mode 100644
index 0000000000..397f9fd343
--- /dev/null
+++ b/util/amdtool/espi.c
@@ -0,0 +1,199 @@
+/* amdtool - dump all registers on an AMD CPU + chipset based system */
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <stdbool.h>
+#include <stdio.h>
+#include <stdlib.h>
+#include <inttypes.h>
+#include <commonlib/helpers.h>
+#include "amdtool.h"
+#include "smn.h"
+
+#define AMD_FCH_SPIBAR_OFFSET	0xa0
+
+#define SPIBAR_ESPI_MMIO_OFFSET	0x10000
+#define SPI_MMIO_BASE		0xfec10000
+#define ESPI0_MMIO_BASE		0xfec20000
+#define ESPI1_MMIO_BASE		0xfec30000
+#define ESPI_MMIO_SIZE		0x10000
+
+#define BRH_ESPI0_SMN_BASE	0x02DC5000
+#define BRH_ESPI1_SMN_BASE	0x02DCA000
+
+static const io_register_t kunlun_espi_cfg_registers[] = {
+	{0x2C, 4, "MASTER_CAP"},
+	{0x30, 4, "GLBL_CTL0"},
+	{0x34, 4, "GLBL_CTL1"},
+	{0x40, 4, "SLAVE0_DECODE_EN"},
+	{0x44, 2, "IO_BASE[0]"},
+	{0x46, 2, "IO_BASE[1]"},
+	{0x48, 2, "IO_BASE[2]"},
+	{0x4A, 2, "IO_BASE[3]"},
+	{0x4C, 1, "IO_SIZE[0]"},
+	{0x4D, 1, "IO_SIZE[1]"},
+	{0x4E, 1, "IO_SIZE[2]"},
+	{0x4F, 1, "IO_SIZE[3]"},
+	{0x50, 4, "MMIO_BASE[0]"},
+	{0x54, 4, "MMIO_BASE[1]"},
+	{0x58, 4, "MMIO_BASE[2]"},
+	{0x5C, 4, "MMIO_BASE[3]"},
+	{0x60, 2, "MMIO_SIZE[0]"},
+	{0x62, 2, "MMIO_SIZE[1]"},
+	{0x64, 2, "MMIO_SIZE[2]"},
+	{0x66, 2, "MMIO_SIZE[3]"},
+	{0x68, 4, "SLAVE0_CFG"},
+	{0x6C, 4, "SLAVE0_INT_EN"},
+	{0x70, 4, "SLAVE0_INT_STS"},
+	{0x80, 2, "IO_BASE[4]"},
+	{0x82, 2, "IO_BASE[5]"},
+	{0x84, 2, "IO_BASE[6]"},
+	{0x86, 2, "IO_BASE[7]"},
+	{0x88, 1, "IO_SIZE[4]"},
+	{0x89, 1, "IO_SIZE[5]"},
+	{0x8A, 1, "IO_SIZE[6]"},
+	{0x8B, 1, "IO_SIZE[7]"},
+	{0x8C, 2, "IO_BASE[8]"},
+	{0x8E, 2, "IO_BASE[9]"},
+	{0x90, 2, "IO_BASE[10]"},
+	{0x92, 2, "IO_BASE[11]"},
+	{0x94, 1, "IO_SIZE[8]"},
+	{0x95, 1, "IO_SIZE[9]"},
+	{0x96, 1, "IO_SIZE[10]"},
+	{0x97, 1, "IO_SIZE[11]"},
+	{0xA8, 4, "SLAVE0_RXVW_MISC_CNTL"},
+	{0xAC, 4, "SLAVE0_RXVW_POLARITY"},
+	{0xB0, 2, "IO_BASE[12]"},
+	{0xB2, 2, "IO_BASE[13]"},
+	{0xB4, 2, "IO_BASE[14]"},
+	{0xB6, 2, "IO_BASE[15]"},
+	{0xB8, 1, "IO_SIZE[12]"},
+	{0xB9, 1, "IO_SIZE[13]"},
+	{0xBA, 1, "IO_SIZE[14]"},
+	{0xBB, 1, "IO_SIZE[15]"},
+	{0xBC, 4, "MMIO_BASE[4]"},
+	{0xC0, 4, "MMIO_SIZE[4]"},
+	{0xC4, 4, "MMIO_CPU_TEMP"},
+	{0xC8, 4, "MMIO_RTC_TIME"},
+	{0xCC, 4, "ESPI_MISC_CTL1"},
+};
+
+static bool use_smn = false;
+static uint32_t espi_smn_addr[2] = { 0, 0 };
+static volatile uint8_t *espibar;
+
+static uint32_t espi_read32(const io_register_t *reg, size_t espi_cntrlr)
+{
+	if (use_smn)
+		return smn_read32(espi_smn_addr[espi_cntrlr] + reg->addr);
+	else
+		return read32(espibar + (espi_cntrlr * ESPI_MMIO_SIZE) + reg->addr);
+}
+
+static uint32_t espi_read16(const io_register_t *reg, size_t espi_cntrlr)
+{
+	if (use_smn)
+		return smn_read16(espi_smn_addr[espi_cntrlr] + reg->addr);
+	else
+		return read16(espibar + (espi_cntrlr * ESPI_MMIO_SIZE) + reg->addr);
+}
+
+static uint32_t espi_read8(const io_register_t *reg, size_t espi_cntrlr)
+{
+	if (use_smn)
+		return smn_read8(espi_smn_addr[espi_cntrlr] + reg->addr);
+	else
+		return read8(espibar + (espi_cntrlr * ESPI_MMIO_SIZE) + reg->addr);
+}
+
+int print_espi(struct pci_dev *sb)
+{
+	size_t i, espi, num_espi, cfg_registers_size = 0;
+	uint32_t spibar_phys, spibar_mask;
+	const io_register_t *cfg_registers;
+	int smbus_rev = 0;
+
+	printf("\n========== eSPI ==========\n\n");
+
+	switch (sb->device_id) {
+	case PCI_DEVICE_ID_AMD_FCH_LPC_2:
+		smbus_rev = find_smbus_dev_rev(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_FCH_SMB_2);
+		if (smbus_rev == -1)
+			return 1;
+
+		switch (smbus_rev) {
+		case 0x71:
+			num_espi = 2;
+			cfg_registers = kunlun_espi_cfg_registers;
+			cfg_registers_size = ARRAY_SIZE(kunlun_espi_cfg_registers);
+			espi_smn_addr[0] = BRH_ESPI0_SMN_BASE;
+			espi_smn_addr[1] = BRH_ESPI1_SMN_BASE;
+			spibar_mask = 0xffffff00;
+			break;
+		default:
+			printf("Error: Dumping eSPI on this southbridge is not (yet) supported.\n");
+			return 1;
+		}
+
+		break;
+	default:
+		printf("Error: Dumping eSPI on this southbridge is not (yet) supported.\n");
+		return 1;
+	}
+
+	spibar_phys = pci_read_long(sb, AMD_FCH_SPIBAR_OFFSET);
+	if ((spibar_phys & spibar_mask) == 0) {
+		perror("Error SPIBAR not programmed");
+		return 1;
+	}
+
+	if (spibar_phys == UINT32_MAX) {
+		spibar_phys = SPI_MMIO_BASE;
+	}
+
+	spibar_phys &= spibar_mask;
+
+	espibar = map_physical(spibar_phys + SPIBAR_ESPI_MMIO_OFFSET,
+				ESPI_MMIO_SIZE * num_espi);
+	if (espibar == NULL) {
+		perror("Error mapping ESPI BAR, trying SMN");
+		use_smn = true;
+	}
+
+	for (espi = 0; espi < num_espi; espi++) {
+		printf("\n---------- eSPI %lu ----------\n\n", espi);
+		if (use_smn)
+			printf("ESPI%lu 0x%08x (SMN)\n\n", espi, espi_smn_addr[espi]);
+		else
+			printf("ESPI%lu 0x%08x (MEM)\n\n", espi,
+				(uint32_t)(spibar_phys + SPIBAR_ESPI_MMIO_OFFSET + (ESPI_MMIO_SIZE * espi)));
+
+		for (i = 0; i < cfg_registers_size; i++) {
+			switch (cfg_registers[i].size) {
+			case 4:
+				printf("0x%04x: 0x%08x (%s)\n",
+					cfg_registers[i].addr,
+					espi_read32(&cfg_registers[i], espi),
+					cfg_registers[i].name);
+				break;
+			case 2:
+				printf("0x%04x: 0x%04x     (%s)\n",
+					cfg_registers[i].addr,
+					espi_read16(&cfg_registers[i], espi),
+					cfg_registers[i].name);
+				break;
+			case 1:
+				printf("0x%04x: 0x%02x       (%s)\n",
+					cfg_registers[i].addr,
+					espi_read8(&cfg_registers[i], espi),
+					cfg_registers[i].name);
+				break;
+			default:
+				printf("Error: register size %d not implemented.\n",
+					cfg_registers[i].size);
+				break;
+			}
+		}
+	}
+
+	return 0;
+}
diff --git a/util/amdtool/gpio.c b/util/amdtool/gpio.c
new file mode 100644
index 0000000000..c2e038950a
--- /dev/null
+++ b/util/amdtool/gpio.c
@@ -0,0 +1,394 @@
+/* amdtool - dump all registers on an AMD CPU + chipset based system */
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <stdbool.h>
+#include <stdio.h>
+#include "acpimmio.h"
+#include "amdtool.h"
+#include "smn.h"
+
+#define AMD_IOMUX_MAX_FUNC_COUNT	4
+#define AMD_IOMUX_SIZE			0x100
+#define AMD_GPIO_BANK_SIZE		(0x100 / 4)
+
+#define AMD_BRH_IOMUX_SMN_BASE		0x02D01000
+
+static uint8_t *iomux_base;
+static uint32_t *gpio_base;
+
+struct gpio_group {
+	const uint8_t *iomux_defaults;
+	const char *const *gpio_names;
+	const unsigned int gpio_bank_count;
+	const uint32_t *gpio_defaults;
+	const uint16_t *special_gpio_regs;
+	const uint16_t special_gpio_regs_size;
+	const uint16_t acpimmio_gpio_offset;
+	const uint16_t acpimmio_iomux_offset;
+};
+
+/* For better readiability and less SLOC, we override the initialized values.
+ * Hide the warnings, as they will overflow the screen and make it harder to
+ * focus on real compielr errors and warnings.
+ */
+#pragma GCC diagnostic push
+#pragma GCC diagnostic ignored "-Woverride-init"
+
+const char *const kunlun_iomux_gpio_names[] = {
+	[0 ... AMD_IOMUX_MAX_FUNC_COUNT * AMD_IOMUX_SIZE - 1] = "",
+	[0x00 * 4] = "PWR_BTN_L",		"GPIO0",	"GPIO0",	"GPIO0",
+	[0x01 * 4] = "SYS_RESET_L",		"GPIO1",	"GPIO1",	"GPIO1",
+	[0x02 * 4] = "WAKE_L",			"GPIO2",	"GPIO2",	"GPIO2",
+	[0x03 * 4] = "GPIO3",			"GPIO3",	"GPIO3",	"GPIO3",
+	[0x04 * 4] = "GPIO4",			"SATA_ACT_L",	"GPIO4",	"GPIO4",
+	[0x05 * 4] = "GPIO5",			"DEVSLP0",	"GPIO5",	"GPIO5",
+	[0x06 * 4] = "GPIO6",			"DEVSLP1",	"GPIO6",	"GPIO6",
+	[0x07 * 4] = "GPIO7",			"GPIO7",	"GPIO7",	"GPIO7",
+	[0x0C * 4] = "PWRGD_OUT",		"GPIO12",	"GPIO12",	"GPIO12",
+	[0x0D * 4] = "I2C4_SCL",		"GPIO13",	"GPIO13",	"GPIO13",
+	[0x0E * 4] = "I2C4_SDA",		"GPIO14",	"GPIO14",	"GPIO14",
+	[0x10 * 4] = "USB10_OC0_L",		"GPIO16",	"GPIO16",	"GPIO16",
+	[0x11 * 4] = "USB11_OC1_L",		"GPIO17",	"GPIO17",	"GPIO17",
+	[0x13 * 4] = "I2C5_SCL",		"SMBUS1_SCL",	"GPIO19",	"GPIO19",
+	[0x14 * 4] = "I2C5_SDA",		"SMBUS1_SDA",	"GPIO20",	"GPIO20",
+	[0x15 * 4] = "GPIO21",			"GPIO21",	"GPIO21",	"n/a",
+	[0x16 * 4] = "GPIO22",			"n/a",		"GPIO22",	"GPIO22",
+	[0x17 * 4] = "ESPI_RSTOUT_L",		"GPIO23",	"GPIO23",	"GPIO23",
+	[0x18 * 4] = "SMERR_L",			"GPIO24",	"GPIO24",	"GPIO24",
+	[0x1A * 4] = "PCIE_RST_L",		"GPIO26",	"GPIO26",	"GPIO26",
+	[0x1C * 4] = "X48M_OUT",		"GPIO28",	"GPIO28",	"GPIO28",
+	[0x4A * 4] = "ESPI_CLK2",		"GPIO74",	"GPIO74"	"GPIO74",
+	[0x4B * 4] = "ESPI_CLK1",		"GPIO75",	"GPIO75",	"n/a",
+	[0x4C * 4] = "GPIO76",			"SPI_TPM_CS_L",	"GPIO76",	"GPIO76",
+	[0x56 * 4] = "GPIO86",			"GPIO86",	"LPC_SMI_L",	"GPIO86",
+	[0x57 * 4] = "GPIO87",			"n/a",		"GPIO87",	"GPIO87",
+	[0x58 * 4] = "GPIO88",			"n/a",		"GPIO88",	"GPIO88",
+	[0x59 * 4] = "GENINT1_L",		"PM_INTR_L",	"GPIO89",	"GPIO89",
+	[0x68 * 4] = "GPIO104",			"GPIO104",	"n/a",		"GPIO104",
+	[0x69 * 4] = "GPIO105",			"GPIO105",	"n/a",		"GPIO105",
+	[0x6A * 4] = "GPIO106",			"GPIO106",	"n/a",		"GPIO106",
+	[0x6B * 4] = "GPIO107",			"GPIO107",	"n/a",		"GPIO107",
+	[0x6C * 4] = "ESPI0_ALERT_D1",		"GPIO108",	"n/a",		"GPIO108",
+	[0x6D * 4] = "GPIO109",			"GPIO109",	"n/a",		"GPIO109",
+	[0x6E * 4] = "ESPI1_ALERT_D1",		"GPIO110",	"GPIO110",	"GPIO110",
+	[0x73 * 4] = "GPIO115",			"CLK_REQ1_L",	"GPIO115",	"GPIO115",
+	[0x74 * 4] = "GPIO116",			"CLK_REQ2_L",	"GPIO116",	"GPIO116",
+	[0x75 * 4] = "ESPI_CLK0",		"GPIO117",	"GPIO117",	"GPIO117",
+	[0x76 * 4] = "SPI_CS0_L",		"GPIO118",	"GPIO118",	"GPIO118",
+	[0x77 * 4] = "SPI_CS1_L",		"GPIO119",	"GPIO119",	"GPIO119",
+	[0x78 * 4] = "ESPI0_D0/SPI0_D0",	"GPIO120",	"GPIO120",	"GPIO120",
+	[0x79 * 4] = "ESPI0_D1/SPI0_D1",	"GPIO121",	"GPIO121",	"GPIO121",
+	[0x7A * 4] = "ESPI0_D2/SPI0_D2",	"GPIO122",	"GPIO122",	"GPIO122",
+	[0x7B * 4] = "ESPI0_D3/SPI0_D3",	"GPIO123",	"GPIO123",	"GPIO123",
+	[0x7C * 4] = "ESPI_CS0_L",		"GPIO124",	"GPIO124",	"GPIO124",
+	[0x7D * 4] = "ESPI_CS1_L",		"GPIO125",	"GPIO125",	"GPIO125",
+	[0x7E * 4] = "SPI_CS2_L",		"GPIO126",	"GPIO126",	"GPIO126",
+	[0x81 * 4] = "ESPI_RSTIN_L",		"KBRST_L",	"GPIO129",	"GPIO129",
+	[0x83 * 4] = "ESPI1_D0/SPI1_D0",	"GPIO131",	"GPIO131",	"GPIO131",
+	[0x84 * 4] = "ESPI1_D1/SPI1_D1",	"GPIO132",	"GPIO132",	"GPIO132",
+	[0x85 * 4] = "ESPI1_D2/SPI1_D2",	"GPIO133",	"GPIO133",	"GPIO133",
+	[0x86 * 4] = "ESPI1_D3/SPI1_D3",	"GPIO134",	"GPIO134",	"GPIO134",
+	[0x87 * 4] = "UART0_CTS_L",		"UART2_RXD",	"GPIO135",	"GPIO135",
+	[0x88 * 4] = "UART0_RXD",		"GPIO136",	"GPIO136",	"GPIO136",
+	[0x89 * 4] = "UART0_RTS_L",		"UART2_TXD",	"GPIO137",	"GPIO137",
+	[0x8A * 4] = "UART0_TXD",		"GPIO138",	"GPIO138",	"GPIO138",
+	[0x8B * 4] = "UART0_INTR",		"GPIO139",	"GPIO139",	"GPIO139",
+	[0x8D * 4] = "UART1_RXD",		"GPIO141",	"GPIO141",	"GPIO141",
+	[0x8E * 4] = "UART1_TXD",		"GPIO142",	"GPIO142",	"GPIO142",
+	[0x91 * 4] = "I3C0_SCL",		"I2C0_SCL",	"SMBUS0_SCL",	"GPIO145",
+	[0x92 * 4] = "I3C0_SDA",		"I2C0_SDA",	"SMBUS0_SDA",	"GPIO146",
+	[0x93 * 4] = "I3C1_SCL",		"I2C1_SCL",	"GPIO147",	"GPIO147",
+	[0x94 * 4] = "I3C1_SDA",		"I2C1_SDA",	"GPIO148",	"GPIO148",
+	[0x95 * 4] = "I3C2_SCL",		"I2C2_SCL",	"GPIO149",	"GPIO149",
+	[0x96 * 4] = "I3C2_SDA",		"I2C2_SDA",	"GPIO150",	"GPIO150",
+	[0x97 * 4] = "I3C3_SCL",		"I2C3_SCL",	"GPIO151",	"GPIO151",
+	[0x98 * 4] = "I3C3_SDA",		"I2C3_SDA",	"GPIO152",	"GPIO152",
+};
+
+const uint8_t kunlun_iomux_group_defaults[] = {
+	[0 ...  AMD_IOMUX_SIZE - 1] = 0x00,
+	[0x13] = 0x01,
+	[0x14] = 0x01,
+	[0x87] = 0x02,
+	[0x89] = 0x02,
+	[0x8A] = 0x01,
+	[0x8E] = 0x01,
+};
+
+const uint32_t kunlun_gpio_group_defaults[] = {
+	[0 ...  4 * AMD_GPIO_BANK_SIZE - 1] = 0,
+	[0x0000]     = 0x00140000, 0x00140000, 0x00140000, 0x00140000,
+	[0x0010 / 4] = 0x00140000, 0x00240000, 0x00240000, 0x00240000,
+	[0x0020 / 4] = 0x00240000, 0x00240000, 0x00140000, 0x00140000,
+	[0x0030 / 4] = 0x00040000, 0x00040000, 0x00040000, 0x00000000,
+	[0x0040 / 4] = 0x00140000, 0x00140000, 0x00140000, 0x00040000,
+	[0x0050 / 4] = 0x00040000, 0x00240000, 0x00240000, 0x00140000,
+	[0x0060 / 4] = 0x00140000, 0x00000000, 0x00040000, 0x00240000,
+	[0x0070 / 4] = 0x00240000, 0x00140000, 0x00140000, 0x00140000,
+	[0x0080 / 4] = 0x00240000, 0x00000000, 0x00000000, 0x00000000,
+	[0x00A0 / 4] = 0x00240000, 0x00000000, 0x00140000, 0x00000000,
+	[0x0120 / 4] = 0x00000000, 0x00000000, 0x00240000, 0x00240000,
+	[0x0130 / 4] = 0x00140000, 0x00000000, 0x00000000, 0x00000000,
+	[0x0150 / 4] = 0x00000000, 0x00000000, 0x00240000, 0x00240000,
+	[0x0160 / 4] = 0x00240000, 0x00140000, 0x00000001, 0x00000000,
+	[0x01A0 / 4] = 0x00240000, 0x00240000, 0x00240000, 0x00240000,
+	[0x01B0 / 4] = 0x00140000, 0x00240000, 0x00000000, 0x00000000,
+	[0x01C0 / 4] = 0x00000000, 0x00000000, 0x00000000, 0x00140000,
+	[0x01D0 / 4] = 0x00140000, 0x00240000, 0x00140000, 0x00140000,
+	[0x01E0 / 4] = 0x00140000, 0x00140000, 0x00140000, 0x00140000,
+	[0x01F0 / 4] = 0x00140000, 0x00140000, 0x00140000, 0x00000000,
+	[0x0200 / 4] = 0x00000000, 0x00140000, 0x00000000, 0x00140000,
+	[0x0210 / 4] = 0x00140000, 0x00140000, 0x00140000, 0x00240000,
+	[0x0220 / 4] = 0x00240000, 0x00140000, 0x00140000, 0x00240000,
+	[0x0230 / 4] = 0x00000000, 0x00240000, 0x00140000, 0x00000000,
+	[0x0240 / 4] = 0x00040000, 0x00040000, 0x00040000, 0x00040000,
+	[0x0250 / 4] = 0x00040000, 0x00040000, 0x00040000, 0x00040000,
+	[0x0260 / 4] = 0x00040000, 0x00000000, 0x00000000, 0x00000000,
+};
+
+
+#pragma GCC diagnostic pop
+
+const uint16_t kunlun_special_gpio_regs[] = {
+	0x0fc, 0x1fc, 0x2f0, 0x02f4, 0x2f8, 0x2fc
+};
+
+const struct gpio_group kunlun_gpio_group = {
+	.iomux_defaults		= kunlun_iomux_group_defaults,
+	.gpio_names		= kunlun_iomux_gpio_names,
+	.gpio_bank_count	= 4,
+	.gpio_defaults		= kunlun_gpio_group_defaults,
+	.special_gpio_regs	= kunlun_special_gpio_regs,
+	.special_gpio_regs_size = ARRAY_SIZE(kunlun_special_gpio_regs),
+	.acpimmio_gpio_offset	= 0x1500,
+	.acpimmio_iomux_offset	= 0x0d00,
+};
+
+static const io_register_t fch_gpio_reg_fields[] = {
+	{  0, 4, "DebounceTmrOut" },
+	{  4, 1, "DebounceTmrOutUnit" },
+	{  5, 2, "DebounceCntrl." },
+	{  7, 1, "DebounceTmrLarge." },
+	{  9, 3, "Trigger Type" },
+	{ 11, 1, "Enable interrupt status" },
+	{ 12, 1, "Enable interrupt delivery" },
+	{ 13, 3, "Wake Control" },
+	{ 16, 1, "Pin Status" },
+	{ 17, 2, "DrvStrengthSel" },
+	{ 19, 1, "Reserved" },
+	{ 20, 1, "Pull Up Enable" },
+	{ 21, 1, "Pull Down Enable" },
+	{ 22, 1, "Output Value" },
+	{ 23, 1, "Output Enable" },
+	{ 24, 1, "SW Control In" },
+	{ 25, 1, "SW Control Enable" },
+	{ 25, 1, "RX Disable" },
+	{ 27, 1, "Reserved" },
+	{ 28, 1, "Interrupt Status" },
+	{ 29, 1, "Wake Status" },
+	{ 30, 1, "Less2SecSts" },
+	{ 31, 1, "Less10SecSts" },
+};
+
+const char * const drive_strength[] = {
+	"Unsupported",
+	"60 Ohms",
+	"40 Ohms",
+	"80 Ohms"
+};
+
+const char * const wake_cntrl[] = {
+	"S0i3",
+	"S3",
+	"S4/S5"
+};
+
+const char * const debounce_cntrl[] = {
+	"No debounce",
+	"Preserve low glitch",
+	"Preserve high glitch",
+	"Remove glitch"
+};
+
+const char * const trigger_type[] = {
+	[0] = "High edge",
+	[1] = "High level",
+	[2] = "Low edge",
+	[3] = "Low level",
+	[4] = "Both edges",
+	[5 ... 8] = "Reserved",
+};
+
+static void print_iomux_reg(uint16_t addr, uint8_t reg, const char *const *gpio_names)
+{
+	printf("IOMUXx%02x: 0x%02x       (%s)\n",
+		addr, reg, gpio_names[addr * 4 + reg]);
+}
+
+static void print_iomux_diff(const uint8_t reg, const uint8_t def, const uint8_t diff,
+			     const char *const *gpio_names)
+{
+	printf("IOMUXx%02x: 0x%02x       (%s) DEFAULT\n",
+		reg, def, gpio_names[reg * 4 + def]);
+	printf("IOMUXx%02x: 0x%02x       DIFF\n", reg, diff);
+}
+
+static void print_gpio_reg(uint16_t addr, uint32_t reg, bool verbose)
+{
+	size_t i;
+	const char *attr;
+
+	printf("GPIOx%04x: 0x%08"PRIx32"\n", addr * 4, reg);
+
+	if (!verbose)
+		return;
+
+	for (i = 0; i < ARRAY_SIZE(fch_gpio_reg_fields); i++) {
+		uint32_t val = reg >> fch_gpio_reg_fields[i].addr;
+		val &= ((1 << fch_gpio_reg_fields[i].size) - 1);
+		switch(i) {
+		case 2: attr = debounce_cntrl[val]; break;
+		case 4: attr = trigger_type[val]; break;
+		case 7: attr = wake_cntrl[val]; break;
+		case 9: attr = drive_strength[val]; break;
+		default: attr = NULL; break;
+		}
+		if (attr)
+			printf("0x%04x = %s (%s)\n", val, fch_gpio_reg_fields[i].name, attr);
+		else
+			printf("0x%04x = %s\n", val, fch_gpio_reg_fields[i].name);
+	}
+}
+
+static void print_gpio_diff(const uint16_t reg, const uint32_t def, const uint32_t diff)
+{
+	printf("GPIOx%04x: 0x%08x       DEFAULT\n", reg * 4, def);
+	printf("GPIOx%04x: 0x%08x       DIFF\n", reg * 4, diff);
+}
+
+static bool is_special_gpio_register(uint16_t reg, const struct gpio_group *sb_gpio_group)
+{
+	size_t i;
+
+	for (i = 0; i < sb_gpio_group->special_gpio_regs_size; i++) {
+		if (reg == sb_gpio_group->special_gpio_regs[i])
+			return true;
+	}
+
+	return false;
+}
+
+int print_gpios(struct pci_dev *sb, int show_all, int show_diffs)
+{
+	size_t i;
+	const struct gpio_group *sb_gpio_group = NULL;
+	const uint8_t *acpi_mmio_bar;
+	uint32_t acpi_mmio_smn_bar;
+	uint32_t gpio_reg, gpio_diff;
+	uint8_t iomux_reg, iomux_diff;
+	int smbus_rev;
+	bool use_smn = false;
+
+	switch (sb->device_id) {
+	case PCI_DEVICE_ID_AMD_FCH_LPC_2:
+		smbus_rev = find_smbus_dev_rev(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_FCH_SMB_2);
+		if (smbus_rev == -1)
+			return 1;
+
+		switch (smbus_rev) {
+		case 0x71:
+			sb_gpio_group = &kunlun_gpio_group;
+			acpi_mmio_smn_bar = AMD_BRH_IOMUX_SMN_BASE;
+			use_smn = true;
+			break;
+		default:
+			printf("Error: Dumping GPIOs on this southbridge is not (yet) supported.\n");
+			return 1;
+		}
+
+		break;
+	default:
+		printf("Error: Dumping GPIOs on this southbridge is not (yet) supported.\n");
+		return 1;
+	}
+
+	if (show_diffs && !show_all)
+		printf("\n========== GPIO DIFFS ===========\n\n");
+	else
+		printf("\n============= GPIOS =============\n\n");
+
+	acpi_mmio_bar = get_acpi_mmio_bar(sb);
+
+	if (!acpi_mmio_bar && !use_smn)
+		return 1;
+
+	if (use_smn) {
+		iomux_base = (uint8_t *)(uintptr_t)(acpi_mmio_smn_bar + sb_gpio_group->acpimmio_iomux_offset);
+		gpio_base = (uint32_t *)(uintptr_t)(acpi_mmio_smn_bar + sb_gpio_group->acpimmio_gpio_offset);
+
+		printf("ACPI MMIO IOMUX 0x%08x (SMN)\n\n", acpi_mmio_smn_bar + sb_gpio_group->acpimmio_iomux_offset);
+		printf("ACPI MMIO GPIO 0x%08x (SMN)\n\n", acpi_mmio_smn_bar + sb_gpio_group->acpimmio_gpio_offset);
+	} else {
+		iomux_base = (uint8_t *)(acpi_mmio_bar + sb_gpio_group->acpimmio_iomux_offset);
+		gpio_base = (uint32_t *)(acpi_mmio_bar + sb_gpio_group->acpimmio_gpio_offset);
+
+		printf("ACPI MMIO IOMUX 0x%08lx (MEM)\n\n", (uintptr_t)acpi_mmio_bar + sb_gpio_group->acpimmio_iomux_offset);
+		printf("ACPI MMIO GPIO 0x%08lx (MEM)\n\n", (uintptr_t)acpi_mmio_bar + sb_gpio_group->acpimmio_gpio_offset);
+	}
+
+
+	for (i = 0; i < AMD_IOMUX_SIZE; i++) {
+		if (use_smn)
+			iomux_reg = smn_read8((uint32_t)(uintptr_t)(iomux_base + i)) & 3;
+		else
+			iomux_reg = read8(iomux_base + i) & 3;
+
+		if (show_all)
+			print_iomux_reg(i, iomux_reg, sb_gpio_group->gpio_names);
+
+		if (show_diffs) {
+			iomux_diff = iomux_reg ^ sb_gpio_group->iomux_defaults[i];
+			if (iomux_diff) {
+				if (!show_all)
+					print_iomux_reg(i, iomux_reg, sb_gpio_group->gpio_names);
+				print_iomux_diff(i, sb_gpio_group->iomux_defaults[i],
+						 iomux_diff, sb_gpio_group->gpio_names);
+				if (!show_all)
+					printf("\n");
+			}
+		}
+	}
+
+	for (i = 0; i < AMD_GPIO_BANK_SIZE * sb_gpio_group->gpio_bank_count; i++) {
+		if (use_smn)
+			gpio_reg = smn_read32((uint32_t)(uintptr_t)(gpio_base + i)) ;
+		else
+			gpio_reg = read32(gpio_base + i);
+
+		print_gpio_reg(i, gpio_reg, false);
+
+		if (show_diffs) {
+			gpio_diff = gpio_reg ^ sb_gpio_group->gpio_defaults[i];
+			if (gpio_diff)
+				print_gpio_diff(i, sb_gpio_group->gpio_defaults[i], gpio_diff);
+		}
+	}
+
+	if (show_all) {
+		printf("\n========== GPIO CONFIG ===========\n\n");
+
+		for (i = 0; i < AMD_GPIO_BANK_SIZE * sb_gpio_group->gpio_bank_count; i++) {
+			if (is_special_gpio_register(i * 4, sb_gpio_group))
+				continue;
+
+			if (use_smn)
+				gpio_reg = smn_read32((uint32_t)(uintptr_t)(gpio_base + i)) ;
+			else
+				gpio_reg = read32(gpio_base + i);
+
+			print_gpio_reg(i, gpio_reg, true);
+		}
+	}
+
+	return 0;
+}
diff --git a/util/amdtool/irq.c b/util/amdtool/irq.c
new file mode 100644
index 0000000000..c6d8e8c9c2
--- /dev/null
+++ b/util/amdtool/irq.c
@@ -0,0 +1,180 @@
+/* amdtool - dump all registers on an AMD CPU + chipset based system */
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <stdio.h>
+#include <stdlib.h>
+#include "amdtool.h"
+#include "smn.h"
+
+#define AMD_PCI_INTR_IDX	0xc00
+#define AMD_PCI_INTR_DATA	0xc01
+
+#define PCI_INTR_ROUTE_IOAPIC	0x80
+
+struct irq_routing_table {
+	const io_register_t irq_reg;
+	void (*print_irq_reg)(uint8_t val);
+};
+
+static void print_misc_irq(uint8_t val)
+{
+	static const char * const irq14_irq15_map[] = {
+		"legacy IDE",
+		"SATA_IDE",
+		"SATA2",
+		"SERIRQ/PCI",
+	};
+
+	printf("\tIRQ0 source: %s\n"
+	       "\tIRQ1 source: %s\n"
+	       "\tIRQ8 source: %s\n"
+	       "\tIRQ12 source: %s\n"
+	       "\tIRQ14 mapped to: %s\n"
+	       "\tIRQ15 mapped to: %s\n",
+	       val & 0x1 ? "SERIRQ/PCI" : "i8254",
+	       val & 0x2 ? "SERIRQ/PCI" : "IMC",
+	       val & 0x4 ? "SERIRQ/PCI" : "RTC",
+	       val & 0x8 ? "SERIRQ/PCI" : "IMC",
+	       irq14_irq15_map[(val >> 4) & 0x3],
+ 	       irq14_irq15_map[(val >> 6) & 0x3]);
+}
+
+static void print_misc0_irq(uint8_t val)
+{
+	printf("\t%s\n"
+	       "\tUSB IRQ1 source: %s\n"
+	       "\tUSB IRQ12 source: %s\n"
+	       "\tIRQ1/IRQ12 mask: %sabled\n"
+	       "\tIRQ input: %s\n"
+	       "\tIRQ1 filter: %sabled\n"
+	       "\tIRQ12 filter: %sabled\n"
+	       "\tINTR delay 600ns: %sabled\n",
+	       val & 0x1 ? "IOAPIC INT2 from PIC IRQ0, IOAPIC INT0 from PIC INTR"
+			 : "IOAPIC INT0 from PIC IRQ0, IOAPIC INT2 from PIC INTR",
+	       val & 0x2 ? "IMC IRQ1" : "serial IRQ1",
+	       val & 0x4 ? "IMC IRQ12" : "serial IRQ12",
+	       val & 0x8 ? "en" : "dis",
+	       val & 0x10 ? "enabled" : "masked off",
+	       val & 0x20 ? "en" : "dis",
+	       val & 0x40 ? "en" : "dis",
+	       val & 0x80 ? "en" : "dis");
+}
+
+static const struct irq_routing_table kunlun_irq_routing[] = {
+	{ { 0x00, 1, "INTA#" }, NULL },
+	{ { 0x01, 1, "INTB#" }, NULL },
+	{ { 0x02, 1, "INTC#" }, NULL },
+	{ { 0x03, 1, "INTD#" }, NULL },
+	{ { 0x04, 1, "INTE#" }, NULL },
+	{ { 0x05, 1, "INTF#/GENINT2" }, NULL },
+	{ { 0x06, 1, "INTG#" }, NULL },
+	{ { 0x07, 1, "INTH#" }, NULL },
+	{ { 0x08, 1, "Misc" }, print_misc_irq },
+	{ { 0x09, 1, "Misc0" }, print_misc0_irq },
+	{ { 0x0A, 1, "Misc1/HPET_L" }, NULL },
+	{ { 0x0B, 1, "Misc2/HPET_H" }, NULL },
+	{ { 0x0C, 1, "INTA from SERIRQ" }, NULL },
+	{ { 0x0D, 1, "INTB from SERIRQ" }, NULL },
+	{ { 0x0E, 1, "INTC from SERIRQ" }, NULL },
+	{ { 0x0F, 1, "INTD from SERIRQ" }, NULL },
+	{ { 0x10, 1, "SCI" }, NULL },
+	{ { 0x11, 1, "SMBUS0" }, NULL },
+	{ { 0x12, 1, "ASF" }, NULL },
+	{ { 0x13, 1, "HDA" }, NULL },
+	{ { 0x14, 1, "GBE0" }, NULL },
+	{ { 0x15, 1, "GBE1" }, NULL },
+	{ { 0x16, 1, "PerMon" }, NULL },
+	{ { 0x17, 1, "SD" }, NULL },
+	{ { 0x1A, 1, "SDIO" }, NULL },
+	{ { 0x20, 1, "CIR (no IRQ connected)" }, NULL },
+	{ { 0x21, 1, "GPIOa (from PAD_FANIN0)" }, NULL },
+	{ { 0x22, 1, "GPIOb (from PAD_FANOUT0)" }, NULL },
+	{ { 0x23, 1, "GPIOc (no IRQ connected)" }, NULL },
+	{ { 0x30, 1, "USB Emu" }, NULL },
+	{ { 0x31, 1, "USB Dual Role 1" }, NULL },
+	{ { 0x32, 1, "USB Dual Role 2" }, NULL },
+	{ { 0x34, 1, "XHCI0" }, NULL },
+	{ { 0x35, 1, "USB SSIC" }, NULL },
+	{ { 0x40, 1, "IDE" }, NULL },
+	{ { 0x41, 1, "SATA" }, NULL },
+	{ { 0x42, 1, "UFS" }, NULL },
+	{ { 0x43, 1, "EMMC" }, NULL },
+	{ { 0x50, 1, "GPPInt0" }, NULL },
+	{ { 0x51, 1, "GPPInt1" }, NULL },
+	{ { 0x52, 1, "GPPInt2" }, NULL },
+	{ { 0x53, 1, "GPPInt3" }, NULL },
+	{ { 0x60, 1, "Gevent SCI interrupt" }, NULL },
+	{ { 0x61, 1, "Gevent SMI interrupt" }, NULL },
+	{ { 0x62, 1, "GPIO controller interrupt" }, NULL },
+	{ { 0x70, 1, "I2C0/I3C0" }, NULL },
+	{ { 0x71, 1, "I2C1/I3C1" }, NULL },
+	{ { 0x72, 1, "I2C2/I3C2" }, NULL },
+	{ { 0x73, 1, "I2C3/I3C3" }, NULL },
+	{ { 0x74, 1, "UART0" }, NULL },
+	{ { 0x75, 1, "UART1" }, NULL },
+	{ { 0x76, 1, "I2C4" }, NULL },
+	{ { 0x77, 1, "I2C5" }, NULL },
+	{ { 0x78, 1, "UART2" }, NULL },
+	{ { 0x79, 1, "UART3" }, NULL },
+};
+
+static uint8_t read_irq_reg(uint8_t addr)
+{
+	outb(addr, AMD_PCI_INTR_IDX);
+	return inb(AMD_PCI_INTR_DATA);
+}
+
+int print_irq_routing(struct pci_dev *sb)
+{
+	int i, irq_table_size;
+	const struct irq_routing_table *irq_table = NULL;
+	int smbus_rev;
+	uint8_t reg;
+
+	printf("\n============= IRQ routing ==============\n");
+
+	switch (sb->device_id) {
+	case PCI_DEVICE_ID_AMD_FCH_LPC_2:
+		smbus_rev = find_smbus_dev_rev(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_FCH_SMB_2);
+		if (smbus_rev == -1)
+			return 1;
+
+		switch (smbus_rev) {
+		case 0x71:
+			irq_table_size = ARRAY_SIZE(kunlun_irq_routing);
+			irq_table = kunlun_irq_routing;
+			break;
+		default:
+			printf("Error: Dumping IRQ routing on this southbridge is not (yet) supported.\n");
+			return 1;
+		}
+
+		break;
+	default:
+		printf("Error: Dumping IRQ routing on this southbridge is not (yet) supported.\n");
+		return 1;
+	}
+
+	printf("PIC routing:\n\n");
+	for (i = 0; i < irq_table_size; i++) {
+		reg = read_irq_reg(irq_table[i].irq_reg.addr);
+		printf("IRQ REG 0x%02x = 0x%02x (%s)\n", irq_table[i].irq_reg.addr,
+							 reg, irq_table[i].irq_reg.name);
+		if (irq_table[i].print_irq_reg)
+			irq_table[i].print_irq_reg(reg);
+	}
+
+	printf("\nIOAPIC routing:\n\n");
+	for (i = 0; i < irq_table_size; i++) {
+		reg = read_irq_reg(irq_table[i].irq_reg.addr | PCI_INTR_ROUTE_IOAPIC);
+		printf("IRQ REG 0x%02x = 0x%02x (%s)\n",
+		       irq_table[i].irq_reg.addr | PCI_INTR_ROUTE_IOAPIC,
+		       reg, irq_table[i].irq_reg.name);
+		if (irq_table[i].print_irq_reg)
+			irq_table[i].print_irq_reg(reg);
+	}
+
+	printf("========================================\n");
+
+	return 0;
+}
diff --git a/util/amdtool/lpc.c b/util/amdtool/lpc.c
new file mode 100644
index 0000000000..2b8441f46c
--- /dev/null
+++ b/util/amdtool/lpc.c
@@ -0,0 +1,126 @@
+/* amdtool - dump all registers on an AMD CPU + chipset based system */
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <stdio.h>
+#include <stdlib.h>
+#include <inttypes.h>
+#include <commonlib/helpers.h>
+#include "amdtool.h"
+
+static const io_register_t kunlun_lpc_cfg_registers[] = {
+	{0x00, 4, "ID"},
+	{0x04, 2, "CMD"},
+	{0x06, 2, "STS"},
+	{0x08, 1, "RID"},
+	{0x09, 1, "CC[2]"},
+	{0x0A, 1, "CC[1]"},
+	{0x0B, 1, "CC[0]"},
+	{0x0C, 1, "CLSIZE"},
+	{0x0D, 1, "LATTMR"},
+	{0x0E, 1, "HTYPE"},
+	{0x2C, 4, "SS"},
+	{0x34, 1, "CAPP"},
+	{0x40, 1, "PCICTL"},
+	{0x44, 4, "IOPDE"},
+	{0x48, 4, "IOMPDE"},
+	{0x4C, 4, "MEMRNG"},
+	{0x50, 4, "ROMPROT[0]"},
+	{0x54, 4, "ROMPROT[1]"},
+	{0x58, 4, "ROMPROT[2]"},
+	{0x5C, 4, "ROMPROT[3]"},
+	{0x60, 2, "LPCMEMADDRSTART"},
+	{0x62, 2, "LPCMEMADDREND"},
+	{0x64, 2, "PCIWIDEIO[0]"},
+	{0x66, 2, "PCIWIDEIO[1]"},
+	{0x68, 2, "ROMADDRSTART[0]"},
+	{0x6A, 2, "ROMADDREND[0]"},
+	{0x6C, 2, "ROMADDRSTART[1]"},
+	{0x6E, 2, "ROMADDREND[1]"},
+	{0x70, 4, "FWHUBSEL"},
+	{0x74, 4, "ALTWIDEIO"},
+	{0x78, 4, "MISCCTL"},
+	{0x7C, 1, "TPM"},
+	{0x7D, 1, "LPCCLKCNTL"},
+	{0x84, 4, "TMKBCBASELO"},
+	{0x88, 4, "TMKBCBASEHI"},
+	{0x8C, 2, "TMKBCREMAP"},
+	{0x90, 2, "PCIWIDEIO[2]"},
+	{0x98, 4, "EC_LPC_CTL"},
+	{0x9C, 4, "GEC_SHDWROM_ADDR"},
+	{0xA0, 4, "SPIBASE"},
+	{0xA4, 2, "EC_PORT_ADDR"},
+	{0xA8, 4, "ROM3_LO"},
+	{0xAC, 4, "ROM3_HI"},
+	{0xB8, 4, "ROMDMACTL"},
+	{0xBA, 1, "EC_CTL"},
+	{0xBB, 1, "HOST_CTL"},
+	{0xC8, 4, "CLIENT_ROM_PROTECT"},
+	{0xCC, 4, "AUTO_ROM_CFG"},
+	{0xD0, 4, "CLKCTL"},
+	{0xD4, 4, "CLKRUNOPT"},
+	{0xDC, 4, "MISCCTL"},
+	{0xE0, 4, "ROMPROT[4]"},
+	{0xE4, 4, "ROMPROT[5]"},
+	{0xE8, 4, "ROMPROT[6]"},
+	{0xEC, 4, "ROMPROT[7]"},
+};
+
+int print_lpc(struct pci_dev *sb)
+{
+	size_t i, cfg_registers_size = 0;
+	const io_register_t *cfg_registers;
+	int smbus_rev = 0;
+
+	printf("\n========== LPC =========\n\n");
+
+	switch (sb->device_id) {
+	case PCI_DEVICE_ID_AMD_FCH_LPC_2:
+		smbus_rev = find_smbus_dev_rev(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_FCH_SMB_2);
+		if (smbus_rev == -1)
+			return 1;
+
+		switch (smbus_rev) {
+		case 0x71:
+			cfg_registers = kunlun_lpc_cfg_registers;
+			cfg_registers_size = ARRAY_SIZE(kunlun_lpc_cfg_registers);
+			break;
+		default:
+			printf("Error: Dumping LPC on this southbridge is not (yet) supported.\n");
+			return 1;
+		}
+
+		break;
+	default:
+		printf("Error: Dumping LPC on this southbridge is not (yet) supported.\n");
+		return 1;
+	}
+
+	for (i = 0; i < cfg_registers_size; i++) {
+		switch (cfg_registers[i].size) {
+		case 4:
+			printf("0x%04x: 0x%08x (%s)\n",
+				cfg_registers[i].addr,
+				pci_read_long(sb, cfg_registers[i].addr),
+				cfg_registers[i].name);
+			break;
+		case 2:
+			printf("0x%04x: 0x%04x     (%s)\n",
+				cfg_registers[i].addr,
+				pci_read_word(sb, cfg_registers[i].addr),
+				cfg_registers[i].name);
+			break;
+		case 1:
+			printf("0x%04x: 0x%02x       (%s)\n",
+				cfg_registers[i].addr,
+				pci_read_byte(sb, cfg_registers[i].addr),
+				cfg_registers[i].name);
+			break;
+		default:
+			printf("Error: register size %d not implemented.\n",
+				cfg_registers[i].size);
+			break;
+		}
+	}
+
+	return 0;
+}
diff --git a/util/amdtool/psb.c b/util/amdtool/psb.c
new file mode 100644
index 0000000000..a6f86b0f6c
--- /dev/null
+++ b/util/amdtool/psb.c
@@ -0,0 +1,149 @@
+/* amdtool - dump all registers on an AMD CPU + chipset based system */
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <stdio.h>
+#include <stdlib.h>
+#include "amdtool.h"
+#include "smn.h"
+
+#define SMN_PSP_PUBLIC_BASE		0x3800000
+
+#define MP0_C2P_MSG_BASE		0x10500
+#define MPASP_C2P_MSG_BASE		0x10900
+
+#define CORE_2_PSP_MSG_37_OFFSET	(MPASP_C2P_MSG_BASE + (37 * 4))
+#define CORE_2_PSP_MSG_38_OFFSET	(MPASP_C2P_MSG_BASE + (38 * 4))
+
+static const io_register_t breithorn_c2p_msg_37_fields[] = {
+	{0x00, 8, "PLATFORM_VENDOR_ID"},
+	{0x08, 4, "PLATFORM_MODEL_ID"},
+	{0x0c, 4, "BIOS_KEY_REVISION_ID"},
+	{0x10, 4, "ROOT_KEY_SELECT"},
+	{0x18, 1, "PLATFORM_SECURE_BOOT_EN"},
+	{0x19, 1, "DISABLE_BIOS_KEY_ANTIROLLBACK"},
+	{0x1a, 1, "DISABLE_AMD_KEY_USAGE"},
+	{0x1b, 1, "DISABLE_SECURE_DEBUG_UNLOCK"},
+	{0x1c, 1, "CUSTOMER_KEY_LOCK"},
+};
+
+static const io_register_t breithorn_c2p_msg_38_fields[] = {
+	{0x00, 8, "PSB Status/Error"},
+	{0x08, 1, "PSB Fusing Readiness"},
+	{0x0c, 1, "SPL Fuse Update Required"},
+	{0x0d, 1, "SPL Fuse Error"},
+	{0x0e, 1, "SPL Entry Error"},
+	{0x0f, 1, "SPL Table Missing"},
+	{0x1c, 1, "HSTISTATE_PSP_SECURE_EN"},
+	{0x1d, 1, "HSTISTATE_PSP_PLATFORM_SECURE_EN"},
+	{0x1e, 1, "HSTISTATE_PSP_DEBUG_LOCK_ON"},
+	{0x1f, 1, "HSTISTATE_PSP_CUSTOMER_KEY_LOCK_ON"},
+};
+/* For better readiability and less SLOC, we override the initialized values.
+ * Hide the warnings, as they will overflow the screen and make it harder to
+ * focus on real compiler errors and warnings.
+ */
+#pragma GCC diagnostic push
+#pragma GCC diagnostic ignored "-Woverride-init"
+
+const char *const c2p_msg_38_error_codes[] = {
+	[0 ... 0xff] = "Other",
+	[0x00] = "PSB passed/no error",
+	[0x22] = "BIOS signing key entry not found",
+	[0x3e] = "Error reading fuse info",
+	[0x64] = "Timeout error attempting to fuse",
+	[0x6c] = "Error in BIOS Directory Table - Reset image not found",
+	[0x6f] = "OEM BIOS signing key usage flag violation",
+	[0x78] = "BIOS RTM signature entry not found",
+	[0x79] = "BIOS copy to DRAM failed",
+	[0x7a] = "BIOS RTM signature verification failed",
+	[0x7b] = "OEM BIOS signing key failed signature verification",
+	[0x7c] = "Platform Vendor ID and/or Model ID binding violation",
+	[0x7d] = "BIOS Copy bit is unset for reset image",
+	[0x7e] = "Requested fuse is already blown",
+	[0x7f] = "Error with actual fusing operation",
+	[0x80] = "Processor1: Error reading fuse info",
+	[0x81] = "Processor1: Requested fuse is already blown",
+	[0x82] = "Processor1: Platform Vendor ID and/or Model ID binding violation",
+	[0x83] = "Processor1: Error with actual fusing operation",
+	[0x92] = "Error in BIOS Directory Table - Firmware type mismatch",
+};
+
+#pragma GCC diagnostic pop
+
+static void print_psb_status_v2(const char * const *psb_status_codes,
+				const io_register_t *status_fields, size_t status_size,
+				const io_register_t *hsti_fields, size_t hsti_size)
+{
+	uint32_t status, hsti;
+	uint8_t psb_state;
+	size_t i;
+
+	status = smn_read32(SMN_PSP_PUBLIC_BASE + CORE_2_PSP_MSG_37_OFFSET);
+	printf("PSB: STATUS = %08"PRIx32"\n", status);
+
+	if (status_fields) {
+		for (i = 0; i < status_size; i++) {
+			unsigned int val = status >> status_fields[i].addr;
+			val &= ((1 << status_fields[i].size) -1);
+			printf("0x%04x = %s\n", val, status_fields[i].name);
+		}
+	}
+
+	hsti = smn_read32(SMN_PSP_PUBLIC_BASE + CORE_2_PSP_MSG_38_OFFSET);
+	printf("PSB: HSTI = %08"PRIx32"\n", hsti);
+
+	if (hsti_fields) {
+		for (i = 0; i < hsti_size; i++) {
+			unsigned int val = hsti >> hsti_fields[i].addr;
+			val &= ((1 << hsti_fields[i].size) -1);
+			if (psb_status_codes && i == 0)
+				printf("0x%04x = %s (%s)\n", val, hsti_fields[i].name, psb_status_codes[val]);
+			else
+				printf("0x%04x = %s\n", val, hsti_fields[i].name);
+		}
+	}
+
+	printf("\n\n");
+
+	psb_state = ((status >> 23) & 2) | ((status >> 28) & 1);
+	switch (psb_state) {
+	case 0:
+		printf("PSB state: NOT ENABLED\n");
+		printf("You may flash other firmware!\n"
+		       "But the Platform Secure Boot state may still be changed to ENABLED or DISABLED!\n");
+		break;
+	case 1:
+		printf("PSB state: DISABLED\n");
+		printf("You may flash other firmware!\n"
+		       "Platform Secure Boot is permanently DISABLED!\n");
+		break;
+	case 2:
+		printf("PSB state: ENABLED\n");
+		printf("You may NOT flash other firmware!\n"
+		       "Platform Secure Boot is permanently ENABLED!\n");
+		break;
+	default:
+		printf("PSB state: UNKNOWN\n");
+		break;
+	}
+}
+
+void print_psb(struct pci_dev *nb)
+{
+	printf("============= Platform Secure Boot ==============\n\n");
+
+	switch (nb->device_id) {
+	case PCI_DEVICE_ID_AMD_BRH_ROOT_COMPLEX:
+		print_psb_status_v2(c2p_msg_38_error_codes,
+				    breithorn_c2p_msg_37_fields,
+				    ARRAY_SIZE(breithorn_c2p_msg_37_fields),
+				    breithorn_c2p_msg_38_fields,
+				    ARRAY_SIZE(breithorn_c2p_msg_38_fields));
+		break;
+	default:
+		printf("Error: Dumping PSB status on this northbridge is not (yet) supported.\n");
+		break;
+	}
+
+	printf("\n=================================================\n");
+}
diff --git a/util/amdtool/smn.c b/util/amdtool/smn.c
new file mode 100644
index 0000000000..76afb7f2a4
--- /dev/null
+++ b/util/amdtool/smn.c
@@ -0,0 +1,42 @@
+/* amdtool - dump all registers on an AMD CPU + chipset based system */
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include "smn.h"
+#include "amdtool.h"
+
+#define SMN_INDIRECT_INDEX		0xB8
+#define SMN_INDIRECT_DATA		0xBC
+
+static struct pci_dev *nb_dev = NULL;
+
+uint32_t smn_read32(uint32_t addr)
+{
+	if (!nb_dev)
+		return UINT32_MAX;
+
+	pci_write_long(nb_dev, SMN_INDIRECT_INDEX, addr & 0xfffffffc);
+	return pci_read_long(nb_dev, SMN_INDIRECT_DATA);
+}
+
+uint16_t smn_read16(uint32_t addr)
+{
+	if (!nb_dev)
+		return UINT8_MAX;
+
+	pci_write_long(nb_dev, SMN_INDIRECT_INDEX, addr & 0xfffffffc);
+	return pci_read_word(nb_dev, SMN_INDIRECT_DATA + (addr & 2));
+}
+
+uint8_t smn_read8(uint32_t addr)
+{
+	if (!nb_dev)
+		return UINT8_MAX;
+
+	pci_write_long(nb_dev, SMN_INDIRECT_INDEX, addr & 0xfffffffc);
+	return pci_read_byte(nb_dev, SMN_INDIRECT_DATA + (addr & 3));
+}
+
+void init_smn(struct pci_dev *nb)
+{
+	nb_dev = nb;
+}
diff --git a/util/amdtool/smn.h b/util/amdtool/smn.h
new file mode 100644
index 0000000000..ae23875f11
--- /dev/null
+++ b/util/amdtool/smn.h
@@ -0,0 +1,15 @@
+/* amdtool - dump all registers on an AMD CPU + chipset based system */
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef AMDTOOL_SMN_H
+#define AMDTOOL_SMN_H 1
+
+#include <stdint.h>
+#include "amdtool.h"
+
+uint32_t smn_read32(uint32_t addr);
+uint16_t smn_read16(uint32_t addr);
+uint8_t smn_read8(uint32_t addr);
+void init_smn(struct pci_dev *nb);
+
+#endif
diff --git a/util/amdtool/spi.c b/util/amdtool/spi.c
new file mode 100644
index 0000000000..ceed89380b
--- /dev/null
+++ b/util/amdtool/spi.c
@@ -0,0 +1,405 @@
+/* amdtool - dump all registers on an AMD CPU + chipset based system */
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <stdio.h>
+#include <stdlib.h>
+#include "amdtool.h"
+#include "smn.h"
+
+#define AMD_FCH_SPIBAR_OFFSET	0xa0
+
+#define BRH_SPI_SMN_BASE	0x2DC4000
+
+static const io_register_t spi100_speed_cfg_fields[] = {
+	{ 0x0, 4, "TPM Speed" },
+	{ 0x4, 4, "Alt Speed" },
+	{ 0x8, 4, "Fast Read Speed" },
+	{ 0xc, 4, "Normal Speed" },
+};
+
+static const io_register_t spi100_host_prefetch_cfg_fields[] = {
+	{ 0x0, 7, "Host Prefetch Size" },
+	{ 0x7, 1, "Host Prefetch on 64B Boudnary" },
+	{ 0x8, 4, "Host Hit Range" },
+	{ 0xc, 1, "Host Will Hit Enable" },
+	{ 0xd, 1, "Host Hit Soon Enable" },
+	{ 0xe, 1, "Host Burst Enable" },
+	{ 0xf, 1, "Host Burst to 4DW Enable" },
+};
+
+static const io_register_t kunlun_spi_cntl0_fields[] = {
+	{ 0x0, 8, "Spi OpCode (Reserved)" },
+	{ 0x8, 1, "Disable Index Retry" },
+	{ 0x9, 1, "Index Cacheline Stop" },
+	{ 0xA, 2, "ROM Protection Compare Range" },
+	{ 0x12, 1, "SPI Read Mode [0]" },
+	{ 0x15, 1, "Illegal Access" },
+	{ 0x16, 1, "SPI MAC Access ROM Enable" },
+	{ 0x17, 1, "SPI Host Access ROM Enable" },
+	{ 0x1c, 1, "SPI Clock Gate" },
+	{ 0x1d, 1, "SPI Read Mode [1]" },
+	{ 0x1e, 1, "SPI Read Mode [2]" },
+	{ 0x1f, 1, "SPI Busy" },
+};
+
+static const io_register_t kunlun_alt_spi_cs_fields[] = {
+	{ 0x0, 2, "Alt SPI CS Enable" },
+	{ 0x3, 1, "SPI Protect Enable 0" },
+	{ 0x5, 1, "SPI Protect Lock" },
+	{ 0x6, 1, "Lock SPI CS" },
+};
+
+static const char * const kunlun_spi100_speed_values[] = {
+	"66.66 MHz",
+	"33.33 MHz",
+	"22.22 MHz",
+	"16.66 Mhz",
+	"100 MHz",
+	"800 KHz",
+	"Defined in SPIx6C[5:0]",
+	"Defined in SPIx6C[13:8]"
+};
+
+static const io_register_t kunlun_spi_bar_registers[] = {
+	{ 0x00, 4, "SPI Control 0" },
+	{ 0x04, 4, "SPI Restricted Command" },
+	{ 0x08, 4, "SPI Restricted Command 2" },
+	{ 0x0C, 4, "SPI Control 1" },
+	{ 0x10, 4, "ESPI Control" },
+	{ 0x14, 4, "SPI Command Value 1" },
+	{ 0x18, 4, "SPI Command Value 2" },
+	{ 0x1C, 1, "ROMCP CS" },
+	{ 0x1D, 1, "SPI ALT CS" },
+	{ 0x20, 4, "SPI100 Enable" },
+	{ 0x24, 4, "SPI100 Precyc0" },
+	{ 0x28, 4, "SPI100 Precyc1" },
+	{ 0x2C, 2, "SPI100 Host Prefetch Config" },
+	{ 0x2E, 2, "TPM SPI DI Timeout" },
+	{ 0x30, 2, "ROM2 Address Override" },
+	{ 0x32, 2, "SPI100 Dummy Cycle Config" },
+	{ 0x32, 2, "SPI100 Rx Timing Config" },
+	{ 0x40, 1, "DDR Command Code" },
+	{ 0x41, 1, "QDR Command Code" },
+	{ 0x42, 1, "DPR Command Code" },
+	{ 0x43, 1, "QPR Command Code" },
+	{ 0x44, 1, "Mode Byte" },
+	{ 0x50, 4, "Addr32 Control 0" },
+	{ 0x54, 4, "Addr32 Control 1" },
+	{ 0x58, 4, "Addr32 Control 2" },
+	{ 0x5C, 4, "Addr32 Control 3" },
+	{ 0x60, 4, "BAR 64MB ROM3 Low" },
+	{ 0x64, 4, "BAR 64MB ROM3 High" },
+	{ 0x68, 4, "SPI Restricted Command 3" },
+	{ 0x6C, 4, "SPI Speed" },
+	{ 0x70, 4, "Host Interrupt" },
+	{ 0x74, 4, "LPC SPI Interrupt" },
+	{ 0x78, 4, "Flash Idle COunt" },
+	{ 0xFC, 2, "SPI Misc Control" },
+};
+
+
+int use_smn_access = 0;
+volatile uint8_t *spibar = NULL;
+uint32_t spi_smn_base = 0;
+
+static uint8_t spi_read8(uint32_t offset)
+{
+	if (use_smn_access)
+		return smn_read8(spi_smn_base + offset);
+	else
+		return read8(spibar + offset);
+}
+
+static uint16_t spi_read16(uint32_t offset)
+{
+	if (use_smn_access)
+		return smn_read16(spi_smn_base + offset);
+	else
+		return read16(spibar + offset);
+}
+
+static uint32_t spi_read32(uint32_t offset)
+{
+	if (use_smn_access)
+		return smn_read32(spi_smn_base + offset);
+	else
+		return read32(spibar + offset);
+}
+
+static int print_spi_cntrl0(struct pci_dev *sb)
+{
+	int i, size = 0;
+	int smbus_rev = 0;
+	uint32_t spi_cntrl0 = UINT32_MAX;
+	const io_register_t *spi_cntrl_register = NULL;
+
+	printf("\n");
+
+	switch (sb->device_id) {
+	case PCI_DEVICE_ID_AMD_FCH_LPC_2:
+		smbus_rev = find_smbus_dev_rev(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_FCH_SMB_2);
+		if (smbus_rev == -1)
+			return 1;
+
+		switch (smbus_rev) {
+		case 0x71:
+			spi_cntrl0 = spi_read32(0);
+			spi_cntrl_register = kunlun_spi_cntl0_fields;
+			size = ARRAY_SIZE(kunlun_spi_cntl0_fields);
+			break;
+		default:
+			printf("Error: Dumping SPI CNTRL on this southbridge is not (yet) supported.\n");
+			return 1;
+		}
+
+		break;
+	default:
+		printf("Error: Dumping SPI CNTRL on this southbridge is not (yet) supported.\n");
+		return 1;
+	}
+
+	printf("SPI_CNTRL0 = 0x%08x\n\n", spi_cntrl0);
+
+	if (spi_cntrl_register) {
+		for (i = 0; i < size; i++) {
+			unsigned int val = spi_cntrl0 >> spi_cntrl_register[i].addr;
+			val &= ((1 << spi_cntrl_register[i].size) -1);
+			printf("0x%04x = %s\n", val, spi_cntrl_register[i].name);
+		}
+	}
+
+	return 0;
+}
+
+static int print_spi_alt_cs(struct pci_dev *sb)
+{
+	int i, size = 0;
+	int smbus_rev = 0;
+	uint8_t spi_alt_cs = 0xff;
+	const io_register_t *spi_alt_cs_register = NULL;
+
+	printf("\n");
+
+	switch (sb->device_id) {
+	case PCI_DEVICE_ID_AMD_FCH_LPC_2:
+		smbus_rev = find_smbus_dev_rev(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_FCH_SMB_2);
+		if (smbus_rev == -1)
+			return 1;
+
+		switch (smbus_rev) {
+		case 0x71:
+			spi_alt_cs = spi_read8(0x1d);
+			spi_alt_cs_register = kunlun_alt_spi_cs_fields;
+			size = ARRAY_SIZE(kunlun_alt_spi_cs_fields);
+			break;
+		default:
+			printf("Error: Dumping SPI_ALT_CS on this southbridge is not (yet) supported.\n");
+			return 1;
+		}
+
+		break;
+	default:
+		printf("Error: Dumping SPI_ALT_CS on this southbridge is not (yet) supported.\n");
+		return 1;
+	}
+
+	printf("SPI_ALT_CS = 0x%02x\n\n", spi_alt_cs);
+
+	if (spi_alt_cs_register) {
+		for (i = 0; i < size; i++) {
+			unsigned int val = spi_alt_cs >> spi_alt_cs_register[i].addr;
+			val &= ((1 << spi_alt_cs_register[i].size) -1);
+			printf("0x%04x = %s\n", val, spi_alt_cs_register[i].name);
+		}
+	}
+
+	return 0;
+}
+
+static int print_spi_speed_config(struct pci_dev *sb)
+{
+	size_t i, size = 0, values_size = 0;
+	uint16_t spi_speed_cfg = UINT16_MAX;
+	const io_register_t *spi_speed_cfg_register = NULL;
+	const char * const *speed_values = NULL;
+	int smbus_rev = 0;
+
+	printf("\n");
+
+	switch (sb->device_id) {
+	case PCI_DEVICE_ID_AMD_FCH_LPC_2:
+		smbus_rev = find_smbus_dev_rev(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_FCH_SMB_2);
+		if (smbus_rev == -1)
+			return 1;
+
+		switch (smbus_rev) {
+		case 0x71:
+			spi_speed_cfg = spi_read16(0x22);
+			spi_speed_cfg_register = spi100_speed_cfg_fields;
+			size = ARRAY_SIZE(spi100_speed_cfg_fields);
+			speed_values = kunlun_spi100_speed_values;
+			values_size = ARRAY_SIZE(kunlun_spi100_speed_values);
+			break;
+		default:
+			printf("Error: Dumping SPI100_SPEED_CFG on this southbridge is not (yet) supported.\n");
+			return 1;
+		}
+
+		break;
+	default:
+		printf("Error: Dumping SPI100_SPEED_CFG on this southbridge is not (yet) supported.\n");
+		return 1;
+	}
+
+	printf("SPI100_SPEED_CFG = 0x%04x\n\n", spi_speed_cfg);
+
+	if (spi_speed_cfg_register && speed_values) {
+		for (i = 0; i < size; i++) {
+			unsigned int val = spi_speed_cfg >> spi_speed_cfg_register[i].addr;
+			val &= ((1 << spi_speed_cfg_register[i].size) -1);
+			if (val < values_size)
+				printf("0x%04x = %s (%s)\n", val, spi_speed_cfg_register[i].name,
+							     speed_values[val]);
+			else
+				printf("0x%04x = %s (Reserved)\n", val, spi_speed_cfg_register[i].name);
+		}
+	}
+
+	return 0;
+}
+
+static int print_spi_host_prefetch(struct pci_dev *sb)
+{
+	int i, size = 0;
+	uint16_t spi_host_prefetch = UINT16_MAX;
+	const io_register_t *spi_host_prefetch_register = NULL;
+	int smbus_rev = 0;
+
+	printf("\n");
+
+	switch (sb->device_id) {
+	case PCI_DEVICE_ID_AMD_FCH_LPC_2:
+		smbus_rev = find_smbus_dev_rev(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_FCH_SMB_2);
+		if (smbus_rev == -1)
+			return 1;
+
+		switch (smbus_rev) {
+		case 0x71:
+			spi_host_prefetch = spi_read16(0x2c);
+			spi_host_prefetch_register = spi100_host_prefetch_cfg_fields;
+			size = ARRAY_SIZE(spi100_host_prefetch_cfg_fields);
+			break;
+		default:
+			printf("Error: Dumping SPI100_HOST_PREFETCH_CFG on this southbridge is not (yet) supported.\n");
+			return 1;
+		}
+
+		break;
+	default:
+		printf("Error: Dumping SPI100_HOST_PREFETCH_CFG on this southbridge is not (yet) supported.\n");
+		return 1;
+	}
+
+	printf("SPI100_HOST_PREFETCH_CFG = 0x%04x\n\n", spi_host_prefetch);
+
+	if (spi_host_prefetch_register) {
+		for (i = 0; i < size; i++) {
+			unsigned int val = spi_host_prefetch >> spi_host_prefetch_register[i].addr;
+			val &= ((1 << spi_host_prefetch_register[i].size) - 1);
+			printf("0x%04x = %s\n", val, spi_host_prefetch_register[i].name);
+		}
+	}
+
+	return 0;
+}
+
+static int print_spibar(struct pci_dev *sb)
+{
+	int i, size = 0, spi_size = 0x1000;
+	uint32_t spibar_phys, spibar_mask;
+	const io_register_t *spi_register = NULL;
+	int smbus_rev;
+
+	printf("\n============= SPI Bar ==============\n\n");
+
+	switch (sb->device_id) {
+	case PCI_DEVICE_ID_AMD_FCH_LPC_2:
+		smbus_rev = find_smbus_dev_rev(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_FCH_SMB_2);
+		if (smbus_rev == -1)
+			return 1;
+
+		switch (smbus_rev) {
+		case 0x71:
+			size = ARRAY_SIZE(kunlun_spi_bar_registers);
+			spi_register = kunlun_spi_bar_registers;
+			spibar_mask = 0xffffff00;
+			spi_smn_base = BRH_SPI_SMN_BASE;
+			break;
+		default:
+			printf("Error: Dumping SPI on this southbridge is not (yet) supported.\n");
+			return 1;
+		}
+
+		break;
+	default:
+		printf("Error: Dumping SPI on this southbridge is not (yet) supported.\n");
+		return 1;
+	}
+
+	spibar_phys = pci_read_long(sb, AMD_FCH_SPIBAR_OFFSET);
+	if ((spibar_phys & spibar_mask) == 0 || (spibar_phys == 0xffffffff)) {
+		if (spi_smn_base != 0) {
+			use_smn_access = 1;
+		} else {
+			perror("Error SPIBAR not programmed");
+			return 1;
+		}
+	} else {
+		if (spibar_phys == UINT32_MAX) {
+			perror("Error SPIBAR invalid");
+			return 1;
+		}
+
+		spibar = map_physical(spibar_phys & spibar_mask, spi_size);
+		if (spibar == NULL) {
+			perror("Error mapping SPIBAR");
+			return 1;
+		}
+
+	}
+
+	for (i = 0; i < size; i++) {
+		switch(spi_register[i].size) {
+			case 1:
+				printf("0x%08x = %s\n", spi_read8(spi_register[i].addr), spi_register[i].name);
+				break;
+			case 2:
+				printf("0x%08x = %s\n", spi_read16(spi_register[i].addr), spi_register[i].name);
+				break;
+			case 4:
+				printf("0x%08x = %s\n", spi_read32(spi_register[i].addr), spi_register[i].name);
+				break;
+			case 8:
+				printf("0x%08x%08x = %s\n", spi_read32(spi_register[i].addr + 4),
+					spi_read32(spi_register[i].addr), spi_register[i].name);
+				break;
+		}
+	}
+
+	print_spi_cntrl0(sb);
+	print_spi_alt_cs(sb);
+	print_spi_speed_config(sb);
+	print_spi_host_prefetch(sb);
+
+	if (spibar)
+		unmap_physical((void *)spibar, spi_size);
+
+	printf("\n====================================\n");
+
+	return 0;
+}
+
+int print_spi(struct pci_dev *sb)
+{
+	return print_spibar(sb);
+}

From 7436c598753c016e46f59b834c4d8a4bb97a737b Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Micha=C5=82=20=C5=BBygowski?= <michal.zygowski@3mdeb.com>
Date: Wed, 12 Nov 2025 17:35:36 +0100
Subject: [PATCH 2502/3886] util/amdtool: Add support for Phoenix AM5 CPUs
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Add register tables and device IDs for Phoenix AM5 desktop CPUs.

TEST=Dump all data with amdtool on MSI PRO B650M-A.

Change-Id: Ia7af9194fb7516e98b7cddee2bfc65af12d56dc0
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90009
Reviewed-by: Michał Kopeć <michal.kopec@3mdeb.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 util/amdtool/amdtool.c |  20 +++--
 util/amdtool/amdtool.h |  22 +++++-
 util/amdtool/cpu.c     |   1 +
 util/amdtool/espi.c    |  23 +++---
 util/amdtool/gpio.c    | 166 ++++++++++++++++++++++++++++++++++++++---
 util/amdtool/irq.c     |  70 +++++++++++++++--
 util/amdtool/lpc.c     |   6 +-
 util/amdtool/psb.c     |   1 +
 util/amdtool/spi.c     |  65 ++++++++++------
 9 files changed, 311 insertions(+), 63 deletions(-)

diff --git a/util/amdtool/amdtool.c b/util/amdtool/amdtool.c
index 22306f78c0..401082b897 100644
--- a/util/amdtool/amdtool.c
+++ b/util/amdtool/amdtool.c
@@ -34,7 +34,15 @@ static const struct {
 	{ PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_BRH_DATA_FABRIC_5, "Turin Data Fabric 5" },
 	{ PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_BRH_DATA_FABRIC_6, "Turin Data Fabric 6" },
 	{ PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_BRH_DATA_FABRIC_7, "Turin Data Fabric 7" },
-
+	{ PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_PHX_ROOT_COMPLEX, "Phoenix Root Complex" },
+	{ PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_PHX_DATA_FABRIC_0, "Phoenix Data Fabric 0" },
+	{ PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_PHX_DATA_FABRIC_1, "Phoenix Data Fabric 1" },
+	{ PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_PHX_DATA_FABRIC_2, "Phoenix Data Fabric 2" },
+	{ PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_PHX_DATA_FABRIC_3, "Phoenix Data Fabric 3" },
+	{ PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_PHX_DATA_FABRIC_4, "Phoenix Data Fabric 4" },
+	{ PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_PHX_DATA_FABRIC_5, "Phoenix Data Fabric 5" },
+	{ PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_PHX_DATA_FABRIC_6, "Phoenix Data Fabric 6" },
+	{ PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_PHX_DATA_FABRIC_7, "Phoenix Data Fabric 7" },
 	/* FCHs (Southbridges) */
 	{ PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_FCH_SMB_1, "FCH SMBus Controller" },
 	{ PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_FCH_LPC_1, "FCH LPC Bridge" },
@@ -351,7 +359,7 @@ int main(int argc, char *argv[])
 	if (dump_lpc) {
 		print_lpc(sb);
 		printf("\n\n");
-		print_espi(sb);
+		print_espi(sb, nb);
 		printf("\n\n");
 	}
 
@@ -371,20 +379,20 @@ int main(int argc, char *argv[])
 	}
 
 	if (dump_gpios) {
-		print_gpios(sb, 1, show_gpio_diffs);
+		print_gpios(sb, nb, 1, show_gpio_diffs);
 		printf("\n\n");
 	} else if (show_gpio_diffs) {
-		print_gpios(sb, 0, show_gpio_diffs);
+		print_gpios(sb, nb, 0, show_gpio_diffs);
 		printf("\n\n");
 	}
 
 	if (dump_spi) {
-		print_spi(sb);
+		print_spi(sb, nb);
 		printf("\n\n");
 	}
 
 	if (dump_irq) {
-		print_irq_routing(sb);
+		print_irq_routing(sb, nb);
 		printf("\n\n");
 	}
 
diff --git a/util/amdtool/amdtool.h b/util/amdtool/amdtool.h
index 524371235e..ef0ca7ec01 100644
--- a/util/amdtool/amdtool.h
+++ b/util/amdtool/amdtool.h
@@ -87,7 +87,21 @@ static inline void outl(uint32_t value, uint16_t port)
 #define PCI_DEVICE_ID_AMD_BRH_DATA_FABRIC_6	0x12c6
 #define PCI_DEVICE_ID_AMD_BRH_DATA_FABRIC_7	0x12c7
 
+#define PCI_DEVICE_ID_AMD_PHX_ROOT_COMPLEX	0x14e8
+#define PCI_DEVICE_ID_AMD_PHX_DATA_FABRIC_0	0x14f0
+#define PCI_DEVICE_ID_AMD_PHX_DATA_FABRIC_1	0x14f1
+#define PCI_DEVICE_ID_AMD_PHX_DATA_FABRIC_2	0x14f2
+#define PCI_DEVICE_ID_AMD_PHX_DATA_FABRIC_3	0x14f3
+#define PCI_DEVICE_ID_AMD_PHX_DATA_FABRIC_4	0x14f4
+#define PCI_DEVICE_ID_AMD_PHX_DATA_FABRIC_5	0x14f5
+#define PCI_DEVICE_ID_AMD_PHX_DATA_FABRIC_6	0x14f6
+#define PCI_DEVICE_ID_AMD_PHX_DATA_FABRIC_7	0x14f7
+
 #define CPUID_TURIN_C1				0x00b00f21
+#define CPUID_PHOENIX_A1			0x00a70f41
+#define CPUID_PHOENIX_A2			0x00a70f52
+#define CPUID_PHOENIX2_A0			0x00a70f80
+#define CPUID_HAWKPOINT2_A0			0x00a70fc0
 
 #if !defined(__DARWIN__) && !defined(__FreeBSD__)
 typedef struct { uint32_t hi, lo; } msr_t;
@@ -117,11 +131,11 @@ uint32_t cpuid(uint32_t eax);
 int print_amd_msrs(void);
 int print_cpu_info(void);
 int print_lpc(struct pci_dev *sb);
-int print_espi(struct pci_dev *sb);
-int print_gpios(struct pci_dev *sb, int show_all, int show_diffs);
-int print_spi(struct pci_dev *sb);
+int print_espi(struct pci_dev *sb, struct pci_dev *nb);
+int print_gpios(struct pci_dev *sb, struct pci_dev *nb, int show_all, int show_diffs);
+int print_spi(struct pci_dev *sb, struct pci_dev *nb);
 int print_acpimmio(struct pci_dev *sb);
 void print_psb(struct pci_dev *nb);
-int print_irq_routing(struct pci_dev *sb);
+int print_irq_routing(struct pci_dev *sb, struct pci_dev *nb);
 
 #endif
diff --git a/util/amdtool/cpu.c b/util/amdtool/cpu.c
index 73c5495e17..abac90f478 100644
--- a/util/amdtool/cpu.c
+++ b/util/amdtool/cpu.c
@@ -518,6 +518,7 @@ int print_amd_msrs(void)
 
 	cpu_t cpulist[] = {
 		{ CPUID_TURIN_C1, common_msrs, ARRAY_SIZE(common_msrs) },
+		{ CPUID_PHOENIX_A2, common_msrs, ARRAY_SIZE(common_msrs) },
 	};
 
 	cpu_t *cpu = NULL;
diff --git a/util/amdtool/espi.c b/util/amdtool/espi.c
index 397f9fd343..29495dd01c 100644
--- a/util/amdtool/espi.c
+++ b/util/amdtool/espi.c
@@ -17,10 +17,10 @@
 #define ESPI1_MMIO_BASE		0xfec30000
 #define ESPI_MMIO_SIZE		0x10000
 
-#define BRH_ESPI0_SMN_BASE	0x02DC5000
-#define BRH_ESPI1_SMN_BASE	0x02DCA000
+#define ESPI0_SMN_BASE		0x02DC5000
+#define ESPI1_SMN_BASE		0x02DCA000
 
-static const io_register_t kunlun_espi_cfg_registers[] = {
+static const io_register_t espi_cfg_registers[] = {
 	{0x2C, 4, "MASTER_CAP"},
 	{0x30, 4, "GLBL_CTL0"},
 	{0x34, 4, "GLBL_CTL1"},
@@ -105,12 +105,13 @@ static uint32_t espi_read8(const io_register_t *reg, size_t espi_cntrlr)
 		return read8(espibar + (espi_cntrlr * ESPI_MMIO_SIZE) + reg->addr);
 }
 
-int print_espi(struct pci_dev *sb)
+int print_espi(struct pci_dev *sb, struct pci_dev *nb)
 {
-	size_t i, espi, num_espi, cfg_registers_size = 0;
+	size_t i, espi, cfg_registers_size = 0;
 	uint32_t spibar_phys, spibar_mask;
 	const io_register_t *cfg_registers;
 	int smbus_rev = 0;
+	size_t num_espi = 1;
 
 	printf("\n========== eSPI ==========\n\n");
 
@@ -122,11 +123,13 @@ int print_espi(struct pci_dev *sb)
 
 		switch (smbus_rev) {
 		case 0x71:
-			num_espi = 2;
-			cfg_registers = kunlun_espi_cfg_registers;
-			cfg_registers_size = ARRAY_SIZE(kunlun_espi_cfg_registers);
-			espi_smn_addr[0] = BRH_ESPI0_SMN_BASE;
-			espi_smn_addr[1] = BRH_ESPI1_SMN_BASE;
+			if (nb->device_id == PCI_DEVICE_ID_AMD_BRH_ROOT_COMPLEX)
+				num_espi = 2;
+
+			cfg_registers = espi_cfg_registers;
+			cfg_registers_size = ARRAY_SIZE(espi_cfg_registers);
+			espi_smn_addr[0] = ESPI0_SMN_BASE;
+			espi_smn_addr[1] = ESPI1_SMN_BASE;
 			spibar_mask = 0xffffff00;
 			break;
 		default:
diff --git a/util/amdtool/gpio.c b/util/amdtool/gpio.c
index c2e038950a..029d106ae6 100644
--- a/util/amdtool/gpio.c
+++ b/util/amdtool/gpio.c
@@ -11,7 +11,7 @@
 #define AMD_IOMUX_SIZE			0x100
 #define AMD_GPIO_BANK_SIZE		(0x100 / 4)
 
-#define AMD_BRH_IOMUX_SMN_BASE		0x02D01000
+#define AMD_FCH_ACPIMMIO_SMN_BASE	0x02D01000
 
 static uint8_t *iomux_base;
 static uint32_t *gpio_base;
@@ -105,6 +105,90 @@ const char *const kunlun_iomux_gpio_names[] = {
 	[0x98 * 4] = "I3C3_SDA",		"I2C3_SDA",	"GPIO152",	"GPIO152",
 };
 
+const char *const tacoma_iomux_gpio_names[] = {
+	[0 ... AMD_IOMUX_MAX_FUNC_COUNT * AMD_IOMUX_SIZE - 1] = "",
+	[  0 * 4] = "PWR_BTN_L",		"GPIO0",		"GPIO0",		"GPIO0",
+	[  1 * 4] = "SYS_RESET_L",		"GPIO1",		"GPIO1",		"GPIO1",
+	[  2 * 4] = "WAKE_L",			"GPIO2",		"GPIO2",		"GPIO2",
+	[  3 * 4] = "GPIO3",			"GPIO3",		"GPIO3",		"GPIO3",
+	[  4 * 4] = "GPIO4",			"GPIO4",		"GPIO4",		"GPIO4",
+	[  5 * 4] = "GPIO5",			"GPIO5",		"GPIO5",		"GPIO5",
+	[  6 * 4] = "GPIO6",			"GPIO6",		"GPIO6",		"GPIO6",
+	[  7 * 4] = "GPIO7",			"GPIO7",		"GPIO7",		"GPIO7",
+	[  8 * 4] = "GPIO8",			"TMU_CLK_OUT0",		"TMU_CLK_OUT1",		"GPIO8",
+	[  9 * 4] = "GPIO9",			"GPIO9",		"GPIO9",		"GPIO9",
+	[ 10 * 4] = "GPIO10",			"S0A3_GPIO",		"GPIO10",		"DF_VRCONTEXT_0",
+	[ 11 * 4] = "GPIO11",			"BLINK",		"GPIO11",		"GPIO11",
+	[ 12 * 4] = "LLB_L",			"GPIO12",		"GPIO12",		"GPIO12",
+	[ 16 * 4] = "USB_OC0_L",		"GPIO16",		"GPIO16",		"GPIO16",
+	[ 17 * 4] = "USB_OC1_L",		"GPIO17",		"GPIO17",		"GPIO17",
+	[ 18 * 4] = "USB_OC2_L",		"GPIO18",		"GPIO18",		"GPIO18",
+	[ 19 * 4] = "SMBUS1_SCL",		"I2C3_SCL",		"I3C3_SCL",		"GPIO19",
+	[ 20 * 4] = "SMBUS1_SDA",		"I2C3_SDA",		"I3C3_SDA",		"GPIO20",
+	[ 21 * 4] = "ESPI_RESET_L",		"KBRST_L",		"GPIO21",		"GPIO21",
+	[ 22 * 4] = "ESPI_ALERT_D1",		"GPIO22",		"GPIO22",		"SD0_CMD",
+	[ 23 * 4] = "AC_PRES",			"GPIO23",		"GPIO23",		"GPIO23",
+	[ 24 * 4] = "USB_OC3_L",		"GPIO24",		"GPIO24",		"GPIO24",
+	[ 26 * 4] = "PCIE_RST0_L",		"GPIO26",		"GPIO26",		"GPIO26",
+	[ 29 * 4] = "SPI_TPM_CS_L",		"GPIO29",		"GPIO29",		"GPIO29",
+	[ 30 * 4] = "SPI_CS2_L",		"ESPI_CS_L",		"GPIO30",		"GPIO30",
+	[ 31 * 4] = "SPI_CS3_L",		"GPIO31",		"GPIO31",		"GPIO31",
+	[ 32 * 4] = "GPIO32",			"LPC_RST_L",		"GPIO32",		"GPIO32",
+	[ 38 * 4] = "CLK_REQ5_L",		"GPIO38",		"GPIO38",		"GPIO38",
+	[ 39 * 4] = "CLK_REQ6_L",		"GPIO39",		"GPIO39",		"GPIO39",
+	[ 40 * 4] = "GPIO40",			"GPIO40",		"GPIO40",		"GPIO40",
+	[ 42 * 4] = "GPIO42",			"DF_VRCONTEXT_1",	"GPIO42",		"GPIO42",
+	[ 67 * 4] = "SPI_ROM_REQ",		"GPIO67",		"GPIO67",		"GPIO67",
+	[ 68 * 4] = "SPI1_DAT2",		"GPIO68",		"GPIO68",		"SD0_DATA3",
+	[ 69 * 4] = "SPI1_DAT3",		"GPIO69",		"SD0_CLK",		"GPIO69",
+	[ 70 * 4] = "SPI2_CLK",			"GPIO70",		"GPIO70",		"GPIO70",
+	[ 74 * 4] = "SPI1_CS1_L",		"GPIO74",		"GFX10_CAC_IPIO0",	"GPIO74",
+	[ 75 * 4] = "SPI2_CS1_L",		"GPIO75",		"GPIO75",		"GPIO75",
+	[ 76 * 4] = "SPI_ROM_GNT",		"GPIO76",		"GPIO76",		"GPIO76",
+	[ 77 * 4] = "SPI1_CLK",			"GPIO77",		"GPIO77",		"SD0_DATA0",
+	[ 78 * 4] = "SPI1_CS2_L",		"GPIO78",		"GFX10_CAC_IPIO1",	"GPIO78",
+	[ 79 * 4] = "SPI1_CS3_L",		"GPIO79",		"GPIO79",		"GPIO79",
+	[ 80 * 4] = "SPI1_DAT1",		"GPIO80",		"GPIO80",		"SD0_DATA2",
+	[ 81 * 4] = "SPI1_DAT0",		"GPIO81",		"GPIO81",		"GPIO81",
+	[ 84 * 4] = "FANIN0",			"GPIO84",		"GPIO84",		"GPIO84",
+	[ 85 * 4] = "FANOUT0",			"GPIO85",		"GPIO85",		"GPIO85",
+	[ 86 * 4] = "GPIO86",			"GPIO86",		"GPIO86",		"GPIO86",
+	[ 89 * 4] = "GENINT1_L",		"PSP_INTR0",		"GPIO89",		"GPIO89",
+	[ 90 * 4] = "GENINT2_L",		"PSP_INTR1",		"GPIO90",		"GPIO90",
+	[ 91 * 4] = "SPKR",			"GPIO91",		"GPIO91",		"GPIO91",
+	[ 92 * 4] = "CLK_REQ0_L",		"GPIO92",		"GPIO92",		"GPIO92",
+	[104 * 4] = "SPI2_DAT0",		"GPIO104",		"GPIO104",		"GPIO104",
+	[105 * 4] = "SPI2_DAT1",		"GPIO105",		"GPIO105",		"GPIO105",
+	[106 * 4] = "SPI2_DAT2",		"GPIO106",		"GPIO106",		"GPIO106",
+	[107 * 4] = "SPI2_DAT3",		"GPIO107",		"GPIO107",		"GPIO107",
+	[113 * 4] = "SMBUS0_SCL",		"I2C2_SCL",		"I3C2_SCL",		"GPIO113",
+	[114 * 4] = "SMBUS0_SDA",		"I2C2_SDA",		"I3C2_SDA",		"GPIO114",
+	[115 * 4] = "CLK_REQ1_L",		"GPIO115",		"GPIO115",		"GPIO115",
+	[116 * 4] = "CLK_REQ2_L",		"GPIO116",		"GPIO116",		"GPIO116",
+	[130 * 4] = "GPIO130",			"GPIO130",		"GPIO130",		"GPIO130",
+	[131 * 4] = "CLK_REQ3_L",		"GPIO131",		"GPIO131",		"GPIO131",
+	[132 * 4] = "CLK_REQ4_L",		"OSCIN",		"GPIO132",		"GPIO132",
+	[135 * 4] = "GPIO135",			"UART2_CTS_L",		"UART3_TXD",		"GPIO135",
+	[136 * 4] = "GPIO136",			"UART2_RXD",		"GPIO136",		"GPIO136",
+	[137 * 4] = "GPIO137",			"UART2_RTS_L",		"UART3_RXD",		"GPIO137",
+	[138 * 4] = "GPIO138",			"UART2_TXD",		"GPIO138",		"GPIO138",
+	[139 * 4] = "GPIO139",			"UART2_INTR",		"GPIO139",		"GPIO139",
+	[140 * 4] = "GPIO140",			"UART0_CTS_L",		"UART1_TXD",		"GPIO140",
+	[141 * 4] = "GPIO141",			"UART0_RXD",		"GPIO141",		"GPIO141",
+	[142 * 4] = "GPIO142",			"UART0_RTS_L",		"UART1_RXD",		"GPIO142",
+	[143 * 4] = "GPIO143",			"UART0_TXD",		"GPIO143",		"GPIO143",
+	[144 * 4] = "GPIO144",			"SHUTDOWN_L",		"UART0_INTR",		"GPIO144",
+	[145 * 4] = "I2C0_SCL",			"I3C0_SCL",		"GPIO145",		"GPIO145",
+	[146 * 4] = "I2C0_SDA",			"I3C0_SDA",		"GPIO146",		"GPIO146",
+	[147 * 4] = "I2C1_SCL",			"I3C1_SCL",		"GPIO147",		"GPIO147",
+	[148 * 4] = "I2C1_SDA",			"I3C1_SDA",		"GPIO148",		"GPIO148",
+	[153 * 4] = "GPIO153",			"UART4_CTS_L",		"GPIO153",		"GPIO153",
+	[154 * 4] = "GPIO154",			"UART4_RTS_L",		"GPIO154",		"GPIO154",
+	[155 * 4] = "GPIO155",			"UART4_RXD",		"GPIO155",		"GPIO155",
+	[156 * 4] = "GPIO156",			"UART4_TXD",		"GPIO156",		"GPIO156",
+	[157 * 4] = "GPIO157",			"UART4_INTR",		"GPIO157",		"GPIO157",
+};
+
 const uint8_t kunlun_iomux_group_defaults[] = {
 	[0 ...  AMD_IOMUX_SIZE - 1] = 0x00,
 	[0x13] = 0x01,
@@ -115,6 +199,10 @@ const uint8_t kunlun_iomux_group_defaults[] = {
 	[0x8E] = 0x01,
 };
 
+const uint8_t tacoma_iomux_group_defaults[] = {
+	[0 ...  AMD_IOMUX_SIZE - 1] = 0x00
+};
+
 const uint32_t kunlun_gpio_group_defaults[] = {
 	[0 ...  4 * AMD_GPIO_BANK_SIZE - 1] = 0,
 	[0x0000]     = 0x00140000, 0x00140000, 0x00140000, 0x00140000,
@@ -146,6 +234,39 @@ const uint32_t kunlun_gpio_group_defaults[] = {
 	[0x0260 / 4] = 0x00040000, 0x00000000, 0x00000000, 0x00000000,
 };
 
+const uint32_t tacoma_gpio_group_defaults[] = {
+	[0 ...  4 * AMD_GPIO_BANK_SIZE - 1] = 0,
+	[0x0000]     = 0x00140000, 0x00140000, 0x00140000, 0x00140000,
+	[0x0010 / 4] = 0x00240000, 0x00240000, 0x00240000, 0x00140000,
+	[0x0020 / 4] = 0x00240000, 0x00240000, 0x00140000, 0x00140000,
+	[0x0030 / 4] = 0x00140000, 0x00000000, 0x00000000, 0x00000000,
+	[0x0040 / 4] = 0x00140000, 0x00140000, 0x00140000, 0x00000000,
+	[0x0050 / 4] = 0x00060000, 0x00140000, 0x00240000, 0x00140000,
+	[0x0060 / 4] = 0x00140000, 0x00000000, 0x00240000, 0x00240000,
+	[0x0070 / 4] = 0x00000000, 0x00140000, 0x00140000, 0x00140000,
+	[0x0080 / 4] = 0x00240000, 0x00000000, 0x00000000, 0x00000000,
+	[0x0090 / 4] = 0x00000000, 0x00000000, 0x00140000, 0x00140000,
+	[0x00A0 / 4] = 0x00240000, 0x00000000, 0x00140000, 0x00000000,
+	[0x0100 / 4] = 0x00000000, 0x00000000, 0x00000000, 0x00240000,
+	[0x0110 / 4] = 0x00140000, 0x00140000, 0x00240000, 0x00000000,
+	[0x0120 / 4] = 0x00000000, 0x00000000, 0x00140000, 0x00140000,
+	[0x0130 / 4] = 0x00240000, 0x00240000, 0x00140000, 0x00140000,
+	[0x0140 / 4] = 0x00240000, 0x00240000, 0x00000000, 0x00000000,
+	[0x0150 / 4] = 0x00140000, 0x00140000, 0x00140000, 0x00000000,
+	[0x0160 / 4] = 0x00000000, 0x00140000, 0x00140000, 0x00240000,
+	[0x0170 / 4] = 0x00140000, 0x00000000, 0x00000000, 0x00000000,
+	[0x01A0 / 4] = 0x00240000, 0x00240000, 0x00140000, 0x00140000,
+	[0x01C0 / 4] = 0x00000000, 0x00100000, 0x00140000, 0x00160000,
+	[0x01D0 / 4] = 0x00140000, 0x00000000, 0x00000000, 0x00000000,
+	[0x0200 / 4] = 0x00000000, 0x00000000, 0x00140000, 0x00140000,
+	[0x0210 / 4] = 0x00140000, 0x00000000, 0x00000000, 0x00240000,
+	[0x0220 / 4] = 0x00240000, 0x00140000, 0x00140000, 0x00240000,
+	[0x0230 / 4] = 0x00240000, 0x00240000, 0x00140000, 0x00140000,
+	[0x0240 / 4] = 0x00240000, 0x00000000, 0x00060000, 0x00000000,
+	[0x0250 / 4] = 0x00060000, 0x00000000, 0x00000000, 0x00000000,
+	[0x0260 / 4] = 0x00000000, 0x00240000, 0x00140000, 0x00240000,
+	[0x0260 / 4] = 0x00140000, 0x00240000, 0x00000000, 0x00000000,
+};
 
 #pragma GCC diagnostic pop
 
@@ -153,6 +274,10 @@ const uint16_t kunlun_special_gpio_regs[] = {
 	0x0fc, 0x1fc, 0x2f0, 0x02f4, 0x2f8, 0x2fc
 };
 
+const uint16_t tacoma_special_gpio_regs[] = {
+	0x0fc, 0x2f0, 0x02f4, 0x2f8, 0x2fc
+};
+
 const struct gpio_group kunlun_gpio_group = {
 	.iomux_defaults		= kunlun_iomux_group_defaults,
 	.gpio_names		= kunlun_iomux_gpio_names,
@@ -164,6 +289,17 @@ const struct gpio_group kunlun_gpio_group = {
 	.acpimmio_iomux_offset	= 0x0d00,
 };
 
+const struct gpio_group tacoma_gpio_group = {
+	.iomux_defaults		= tacoma_iomux_group_defaults,
+	.gpio_names		= tacoma_iomux_gpio_names,
+	.gpio_bank_count	= 4,
+	.gpio_defaults		= tacoma_gpio_group_defaults,
+	.special_gpio_regs	= tacoma_special_gpio_regs,
+	.special_gpio_regs_size = ARRAY_SIZE(tacoma_special_gpio_regs),
+	.acpimmio_gpio_offset	= 0x1500,
+	.acpimmio_iomux_offset	= 0x0d00,
+};
+
 static const io_register_t fch_gpio_reg_fields[] = {
 	{  0, 4, "DebounceTmrOut" },
 	{  4, 1, "DebounceTmrOutUnit" },
@@ -278,7 +414,7 @@ static bool is_special_gpio_register(uint16_t reg, const struct gpio_group *sb_g
 	return false;
 }
 
-int print_gpios(struct pci_dev *sb, int show_all, int show_diffs)
+int print_gpios(struct pci_dev *sb, struct pci_dev *nb, int show_all, int show_diffs)
 {
 	size_t i;
 	const struct gpio_group *sb_gpio_group = NULL;
@@ -297,19 +433,28 @@ int print_gpios(struct pci_dev *sb, int show_all, int show_diffs)
 
 		switch (smbus_rev) {
 		case 0x71:
-			sb_gpio_group = &kunlun_gpio_group;
-			acpi_mmio_smn_bar = AMD_BRH_IOMUX_SMN_BASE;
-			use_smn = true;
+			switch (nb->device_id) {
+			case PCI_DEVICE_ID_AMD_BRH_ROOT_COMPLEX:
+				sb_gpio_group = &kunlun_gpio_group;
+				acpi_mmio_smn_bar = AMD_FCH_ACPIMMIO_SMN_BASE;
+				use_smn = true;
+				break;
+			case PCI_DEVICE_ID_AMD_PHX_ROOT_COMPLEX:
+				sb_gpio_group = &tacoma_gpio_group;
+				acpi_mmio_smn_bar = AMD_FCH_ACPIMMIO_SMN_BASE;
+				use_smn = true;
+				break;
+			default:
+				goto err_out;
+			}
 			break;
 		default:
-			printf("Error: Dumping GPIOs on this southbridge is not (yet) supported.\n");
-			return 1;
+			goto err_out;
 		}
 
 		break;
 	default:
-		printf("Error: Dumping GPIOs on this southbridge is not (yet) supported.\n");
-		return 1;
+		goto err_out;
 	}
 
 	if (show_diffs && !show_all)
@@ -391,4 +536,7 @@ int print_gpios(struct pci_dev *sb, int show_all, int show_diffs)
 	}
 
 	return 0;
+err_out:
+	printf("Error: Dumping GPIOs on this southbridge is not (yet) supported.\n");
+	return 1;
 }
diff --git a/util/amdtool/irq.c b/util/amdtool/irq.c
index c6d8e8c9c2..dbd8391ffa 100644
--- a/util/amdtool/irq.c
+++ b/util/amdtool/irq.c
@@ -118,13 +118,56 @@ static const struct irq_routing_table kunlun_irq_routing[] = {
 	{ { 0x79, 1, "UART3" }, NULL },
 };
 
+static const struct irq_routing_table tacoma_irq_routing[] = {
+	{ { 0x00, 1, "INTA#" }, NULL },
+	{ { 0x01, 1, "INTB#" }, NULL },
+	{ { 0x02, 1, "INTC#" }, NULL },
+	{ { 0x03, 1, "INTD#" }, NULL },
+	{ { 0x04, 1, "INTE#" }, NULL },
+	{ { 0x05, 1, "INTF#/GENINT2" }, NULL },
+	{ { 0x06, 1, "INTG#" }, NULL },
+	{ { 0x07, 1, "INTH#" }, NULL },
+	{ { 0x08, 1, "Misc" }, print_misc_irq },
+	{ { 0x09, 1, "Misc0" }, print_misc0_irq },
+	{ { 0x0A, 1, "Misc1/HPET_L" }, NULL },
+	{ { 0x0B, 1, "Misc2/HPET_H" }, NULL },
+	{ { 0x0C, 1, "INTA from SERIRQ" }, NULL },
+	{ { 0x0D, 1, "INTB from SERIRQ" }, NULL },
+	{ { 0x0E, 1, "INTC from SERIRQ" }, NULL },
+	{ { 0x0F, 1, "INTD from SERIRQ" }, NULL },
+	{ { 0x10, 1, "SCI" }, NULL },
+	{ { 0x11, 1, "SMBUS0" }, NULL },
+	{ { 0x12, 1, "ASF" }, NULL },
+	{ { 0x16, 1, "PerMon" }, NULL },
+	{ { 0x17, 1, "SD" }, NULL },
+	{ { 0x1A, 1, "SDIO" }, NULL },
+	{ { 0x20, 1, "CIR (no IRQ connected)" }, NULL },
+	{ { 0x21, 1, "GPIOa (from PAD_FANIN0)" }, NULL },
+	{ { 0x22, 1, "GPIOb (from PAD_FANOUT0)" }, NULL },
+	{ { 0x23, 1, "GPIOc (no IRQ connected)" }, NULL },
+	{ { 0x43, 1, "EMMC" }, NULL },
+	{ { 0x60, 1, "Gevent SCI interrupt" }, NULL },
+	{ { 0x61, 1, "Gevent SMI interrupt" }, NULL },
+	{ { 0x62, 1, "GPIO controller interrupt" }, NULL },
+	{ { 0x70, 1, "I2C0" }, NULL },
+	{ { 0x71, 1, "I2C1" }, NULL },
+	{ { 0x72, 1, "I2C2" }, NULL },
+	{ { 0x73, 1, "I2C3" }, NULL },
+	{ { 0x74, 1, "UART0" }, NULL },
+	{ { 0x75, 1, "UART1" }, NULL },
+	{ { 0x76, 1, "I2C4" }, NULL },
+	{ { 0x77, 1, "UART4" }, NULL },
+	{ { 0x78, 1, "UART2" }, NULL },
+	{ { 0x79, 1, "UART3" }, NULL },
+};
+
 static uint8_t read_irq_reg(uint8_t addr)
 {
 	outb(addr, AMD_PCI_INTR_IDX);
 	return inb(AMD_PCI_INTR_DATA);
 }
 
-int print_irq_routing(struct pci_dev *sb)
+int print_irq_routing(struct pci_dev *sb,struct pci_dev *nb)
 {
 	int i, irq_table_size;
 	const struct irq_routing_table *irq_table = NULL;
@@ -141,18 +184,25 @@ int print_irq_routing(struct pci_dev *sb)
 
 		switch (smbus_rev) {
 		case 0x71:
-			irq_table_size = ARRAY_SIZE(kunlun_irq_routing);
-			irq_table = kunlun_irq_routing;
+			switch (nb->device_id) {
+			case PCI_DEVICE_ID_AMD_BRH_ROOT_COMPLEX:
+				irq_table_size = ARRAY_SIZE(kunlun_irq_routing);
+				irq_table = kunlun_irq_routing;
+				break;
+			case PCI_DEVICE_ID_AMD_PHX_ROOT_COMPLEX:
+				irq_table_size = ARRAY_SIZE(tacoma_irq_routing);
+				irq_table = tacoma_irq_routing;
+				break;
+			default:
+				goto err_out;
+			}
 			break;
 		default:
-			printf("Error: Dumping IRQ routing on this southbridge is not (yet) supported.\n");
-			return 1;
+			goto err_out;
 		}
-
 		break;
 	default:
-		printf("Error: Dumping IRQ routing on this southbridge is not (yet) supported.\n");
-		return 1;
+		goto err_out;
 	}
 
 	printf("PIC routing:\n\n");
@@ -177,4 +227,8 @@ int print_irq_routing(struct pci_dev *sb)
 	printf("========================================\n");
 
 	return 0;
+
+err_out:
+	printf("Error: Dumping IRQ routing on this southbridge is not (yet) supported.\n");
+	return 1;
 }
diff --git a/util/amdtool/lpc.c b/util/amdtool/lpc.c
index 2b8441f46c..e2ace6b1fd 100644
--- a/util/amdtool/lpc.c
+++ b/util/amdtool/lpc.c
@@ -7,7 +7,7 @@
 #include <commonlib/helpers.h>
 #include "amdtool.h"
 
-static const io_register_t kunlun_lpc_cfg_registers[] = {
+static const io_register_t lpc_cfg_registers[] = {
 	{0x00, 4, "ID"},
 	{0x04, 2, "CMD"},
 	{0x06, 2, "STS"},
@@ -81,8 +81,8 @@ int print_lpc(struct pci_dev *sb)
 
 		switch (smbus_rev) {
 		case 0x71:
-			cfg_registers = kunlun_lpc_cfg_registers;
-			cfg_registers_size = ARRAY_SIZE(kunlun_lpc_cfg_registers);
+			cfg_registers = lpc_cfg_registers;
+			cfg_registers_size = ARRAY_SIZE(lpc_cfg_registers);
 			break;
 		default:
 			printf("Error: Dumping LPC on this southbridge is not (yet) supported.\n");
diff --git a/util/amdtool/psb.c b/util/amdtool/psb.c
index a6f86b0f6c..e1458bb888 100644
--- a/util/amdtool/psb.c
+++ b/util/amdtool/psb.c
@@ -134,6 +134,7 @@ void print_psb(struct pci_dev *nb)
 
 	switch (nb->device_id) {
 	case PCI_DEVICE_ID_AMD_BRH_ROOT_COMPLEX:
+	case PCI_DEVICE_ID_AMD_PHX_ROOT_COMPLEX:
 		print_psb_status_v2(c2p_msg_38_error_codes,
 				    breithorn_c2p_msg_37_fields,
 				    ARRAY_SIZE(breithorn_c2p_msg_37_fields),
diff --git a/util/amdtool/spi.c b/util/amdtool/spi.c
index ceed89380b..36f59f543b 100644
--- a/util/amdtool/spi.c
+++ b/util/amdtool/spi.c
@@ -8,7 +8,7 @@
 
 #define AMD_FCH_SPIBAR_OFFSET	0xa0
 
-#define BRH_SPI_SMN_BASE	0x2DC4000
+#define SPI_SMN_BASE	0x2DC4000
 
 static const io_register_t spi100_speed_cfg_fields[] = {
 	{ 0x0, 4, "TPM Speed" },
@@ -27,7 +27,7 @@ static const io_register_t spi100_host_prefetch_cfg_fields[] = {
 	{ 0xf, 1, "Host Burst to 4DW Enable" },
 };
 
-static const io_register_t kunlun_spi_cntl0_fields[] = {
+static const io_register_t spi_cntl0_fields[] = {
 	{ 0x0, 8, "Spi OpCode (Reserved)" },
 	{ 0x8, 1, "Disable Index Retry" },
 	{ 0x9, 1, "Index Cacheline Stop" },
@@ -49,7 +49,13 @@ static const io_register_t kunlun_alt_spi_cs_fields[] = {
 	{ 0x6, 1, "Lock SPI CS" },
 };
 
-static const char * const kunlun_spi100_speed_values[] = {
+static const io_register_t tacoma_alt_spi_cs_fields[] = {
+	{ 0x0, 2, "Alt SPI CS Enable" },
+	{ 0x3, 1, "SPI Protect Enable 0" },
+	{ 0x5, 1, "SPI Protect Lock" },
+};
+
+static const char * const spi100_speed_values[] = {
 	"66.66 MHz",
 	"33.33 MHz",
 	"22.22 MHz",
@@ -60,7 +66,7 @@ static const char * const kunlun_spi100_speed_values[] = {
 	"Defined in SPIx6C[13:8]"
 };
 
-static const io_register_t kunlun_spi_bar_registers[] = {
+static const io_register_t spi_bar_registers[] = {
 	{ 0x00, 4, "SPI Control 0" },
 	{ 0x04, 4, "SPI Restricted Command" },
 	{ 0x08, 4, "SPI Restricted Command 2" },
@@ -144,8 +150,8 @@ static int print_spi_cntrl0(struct pci_dev *sb)
 		switch (smbus_rev) {
 		case 0x71:
 			spi_cntrl0 = spi_read32(0);
-			spi_cntrl_register = kunlun_spi_cntl0_fields;
-			size = ARRAY_SIZE(kunlun_spi_cntl0_fields);
+			spi_cntrl_register = spi_cntl0_fields;
+			size = ARRAY_SIZE(spi_cntl0_fields);
 			break;
 		default:
 			printf("Error: Dumping SPI CNTRL on this southbridge is not (yet) supported.\n");
@@ -171,7 +177,7 @@ static int print_spi_cntrl0(struct pci_dev *sb)
 	return 0;
 }
 
-static int print_spi_alt_cs(struct pci_dev *sb)
+static int print_spi_alt_cs(struct pci_dev *sb, struct pci_dev *nb)
 {
 	int i, size = 0;
 	int smbus_rev = 0;
@@ -188,19 +194,28 @@ static int print_spi_alt_cs(struct pci_dev *sb)
 
 		switch (smbus_rev) {
 		case 0x71:
-			spi_alt_cs = spi_read8(0x1d);
-			spi_alt_cs_register = kunlun_alt_spi_cs_fields;
-			size = ARRAY_SIZE(kunlun_alt_spi_cs_fields);
+			switch (nb->device_id) {
+			case PCI_DEVICE_ID_AMD_BRH_ROOT_COMPLEX:
+				spi_alt_cs = spi_read8(0x1d);
+				spi_alt_cs_register = kunlun_alt_spi_cs_fields;
+				size = ARRAY_SIZE(kunlun_alt_spi_cs_fields);
+				break;
+			case PCI_DEVICE_ID_AMD_PHX_ROOT_COMPLEX:
+				spi_alt_cs = spi_read8(0x1d);
+				spi_alt_cs_register = tacoma_alt_spi_cs_fields;
+				size = ARRAY_SIZE(tacoma_alt_spi_cs_fields);
+				break;
+			default:
+				goto alt_cs_err;
+			}
 			break;
 		default:
-			printf("Error: Dumping SPI_ALT_CS on this southbridge is not (yet) supported.\n");
-			return 1;
+			goto alt_cs_err;
 		}
 
 		break;
 	default:
-		printf("Error: Dumping SPI_ALT_CS on this southbridge is not (yet) supported.\n");
-		return 1;
+		goto alt_cs_err;
 	}
 
 	printf("SPI_ALT_CS = 0x%02x\n\n", spi_alt_cs);
@@ -214,6 +229,10 @@ static int print_spi_alt_cs(struct pci_dev *sb)
 	}
 
 	return 0;
+
+alt_cs_err:
+	printf("Error: Dumping SPI_ALT_CS on this southbridge is not (yet) supported.\n");
+	return 1;
 }
 
 static int print_spi_speed_config(struct pci_dev *sb)
@@ -237,8 +256,8 @@ static int print_spi_speed_config(struct pci_dev *sb)
 			spi_speed_cfg = spi_read16(0x22);
 			spi_speed_cfg_register = spi100_speed_cfg_fields;
 			size = ARRAY_SIZE(spi100_speed_cfg_fields);
-			speed_values = kunlun_spi100_speed_values;
-			values_size = ARRAY_SIZE(kunlun_spi100_speed_values);
+			speed_values = spi100_speed_values;
+			values_size = ARRAY_SIZE(spi100_speed_values);
 			break;
 		default:
 			printf("Error: Dumping SPI100_SPEED_CFG on this southbridge is not (yet) supported.\n");
@@ -313,7 +332,7 @@ static int print_spi_host_prefetch(struct pci_dev *sb)
 	return 0;
 }
 
-static int print_spibar(struct pci_dev *sb)
+static int print_spibar(struct pci_dev *sb, struct pci_dev *nb)
 {
 	int i, size = 0, spi_size = 0x1000;
 	uint32_t spibar_phys, spibar_mask;
@@ -330,10 +349,10 @@ static int print_spibar(struct pci_dev *sb)
 
 		switch (smbus_rev) {
 		case 0x71:
-			size = ARRAY_SIZE(kunlun_spi_bar_registers);
-			spi_register = kunlun_spi_bar_registers;
+			size = ARRAY_SIZE(spi_bar_registers);
+			spi_register = spi_bar_registers;
 			spibar_mask = 0xffffff00;
-			spi_smn_base = BRH_SPI_SMN_BASE;
+			spi_smn_base = SPI_SMN_BASE;
 			break;
 		default:
 			printf("Error: Dumping SPI on this southbridge is not (yet) supported.\n");
@@ -387,7 +406,7 @@ static int print_spibar(struct pci_dev *sb)
 	}
 
 	print_spi_cntrl0(sb);
-	print_spi_alt_cs(sb);
+	print_spi_alt_cs(sb, nb);
 	print_spi_speed_config(sb);
 	print_spi_host_prefetch(sb);
 
@@ -399,7 +418,7 @@ static int print_spibar(struct pci_dev *sb)
 	return 0;
 }
 
-int print_spi(struct pci_dev *sb)
+int print_spi(struct pci_dev *sb, struct pci_dev *nb)
 {
-	return print_spibar(sb);
+	return print_spibar(sb, nb);
 }

From 10d606bfca0127c1acae8683b3ebe24dea1126aa Mon Sep 17 00:00:00 2001
From: Cliff Huang <cliff.huang@intel.com>
Date: Fri, 14 Nov 2025 14:22:12 -0800
Subject: [PATCH 2503/3886] soc/intel/common/acpi: Add P2SB write functions
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Add common PCR write functions to write values directly to PCR
registers. These functions complement the existing read and
write-OR functions and provide a complete PCR access interface
for ACPI code.
WPCR: Generic PCR write function in the ACPI library
PCRW: PCH-specific PCR write function that calls WPCR

BUG=none
TEST=Build test on platforms using PCR functions. Verify ACPI code can
successfully write to PCR registers using the new functions.

Signed-off-by: Cliff Huang <cliff.huang@intel.com>
Change-Id: I2c74dffda94a3ab34bd71177a3878b8d4c3119cd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90044
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Reviewed-by: Kim, Wonkyu <wonkyu.kim@intel.com>
---
 src/soc/intel/common/acpi/pch_pcr.asl | 11 +++++++++++
 src/soc/intel/common/acpi/pcrlib.asl  | 25 +++++++++++++++++++++++++
 2 files changed, 36 insertions(+)

diff --git a/src/soc/intel/common/acpi/pch_pcr.asl b/src/soc/intel/common/acpi/pch_pcr.asl
index d7991c4fd1..6a791c780f 100644
--- a/src/soc/intel/common/acpi/pch_pcr.asl
+++ b/src/soc/intel/common/acpi/pch_pcr.asl
@@ -44,3 +44,14 @@ Method (PCRO, 3, Serialized)
 {
 	OPCR(PCH_P2SB, Arg0, Arg1, Arg2)
 }
+
+/*
+ * Write a value with PCR register at specified PID and offset
+ * Arg0 - PCR Port ID
+ * Arg1 - Register Offset
+ * Arg2 - Value to Write
+ */
+Method (PCRW, 3, Serialized)
+{
+	WPCR(PCH_P2SB, Arg0, Arg1, Arg2)
+}
diff --git a/src/soc/intel/common/acpi/pcrlib.asl b/src/soc/intel/common/acpi/pcrlib.asl
index dd5fb9f254..65384c79d3 100644
--- a/src/soc/intel/common/acpi/pcrlib.asl
+++ b/src/soc/intel/common/acpi/pcrlib.asl
@@ -97,4 +97,29 @@ Method (OPCR, 4, Serialized)
 	RPCR (Arg0, Arg1, Arg2)
 }
 
+/*
+ * Perform PCR register write for specified Die at PID and offset
+ * Arg0 - Die Index
+ * Arg1 - PCR Port ID
+ * Arg2 - Register Offset
+ * Arg3 - Value to write
+ */
+Method (WPCR, 4, Serialized)
+{
+	OperationRegion (PCRD, SystemMemory, GPCR (Arg0, Arg1) + Arg2, 4)
+	Field (PCRD, DWordAcc, NoLock, Preserve)
+	{
+		DATA, 32
+	}
+	DATA = Arg3
+
+	/*
+	 * After every write one needs to read an innocuous register
+	 * to ensure the writes are completed for certain ports. This is done
+	 * for all ports so that the callers don't need the per-port knowledge
+	 * for each transaction.
+	 */
+	RPCR (Arg0, Arg1, Arg2)
+}
+
 #endif /* _SOC_INTEL_ACPI_PCR_LIB_ */

From 4081793ff2c8b813370d87d0ebbf8e8c945610cb Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Sun, 16 Nov 2025 15:42:36 -0600
Subject: [PATCH 2504/3886] payloads/external/edk2: Replace dependencies on
 EDK2_REPO_MRCHROMEBOX

Replace positive dependency on EDK2_REPO_MRCHROMEBOX with negative
dependency on EDK2_REPO_OFFICIAL for downstream-specific features.
This makes the logic more generic and allows other downstream repos
to use these features. Options which were selected by default when
EDK2_REPO_MRCHROMEBOX is used remain unchanged.

Change-Id: Ia31e48c5a04d8db8b0f5250a6302123361cc3660
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90057
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
---
 payloads/external/edk2/Kconfig  | 10 +++++-----
 payloads/external/edk2/Makefile |  6 +++---
 2 files changed, 8 insertions(+), 8 deletions(-)

diff --git a/payloads/external/edk2/Kconfig b/payloads/external/edk2/Kconfig
index 583de2dc1d..dc76251fb2 100644
--- a/payloads/external/edk2/Kconfig
+++ b/payloads/external/edk2/Kconfig
@@ -212,7 +212,7 @@ config EDK2_CPU_TIMER_LIB
 
 config EDK2_FOLLOW_BGRT_SPEC
 	bool "Center logo 38.2% from the top of screen"
-	depends on EDK2_REPO_MRCHROMEBOX
+	depends on !EDK2_REPO_OFFICIAL
 	default n
 	help
 	  Follow the BGRT Specification implemented by Microsoft and
@@ -235,14 +235,14 @@ config EDK2_HAVE_EFI_SHELL
 
 config EDK2_PRIORITIZE_INTERNAL
 	bool "Prioritize internal boot devices"
-	depends on EDK2_REPO_MRCHROMEBOX
+	depends on !EDK2_REPO_OFFICIAL
 	default y
 	help
 	  Prioritize internal boot devices over external devices
 
 config EDK2_LOAD_OPTION_ROMS
 	bool "Load and Execute OpROMs on PCIe devices"
-	depends on EDK2_REPO_MRCHROMEBOX
+	depends on !EDK2_REPO_OFFICIAL
 	default n
 	help
 	  Load and execute OpROMs on PCIe devices.
@@ -271,7 +271,7 @@ config EDK2_SERIAL_SUPPORT
 
 config EDK2_SECURE_BOOT_SUPPORT
 	bool "Enable UEFI Secure Boot support"
-	depends on EDK2_REPO_MRCHROMEBOX && SMMSTORE_V2
+	depends on !EDK2_REPO_OFFICIAL && SMMSTORE_V2
 	default y if EDK2_REPO_MRCHROMEBOX && SMMSTORE_V2
 	help
 	  Select this option to enable UEFI SecureBoot support in edk2.
@@ -279,7 +279,7 @@ config EDK2_SECURE_BOOT_SUPPORT
 
 config EDK2_GOP_DRIVER
 	bool "Add a GOP driver to the Tianocore build"
-	depends on INTEL_GMA_ADD_VBT && NO_GFX_INIT && EDK2_REPO_MRCHROMEBOX
+	depends on INTEL_GMA_ADD_VBT && NO_GFX_INIT && !EDK2_REPO_OFFICIAL
 	default y if INTEL_GMA_ADD_VBT && NO_GFX_INIT && EDK2_REPO_MRCHROMEBOX
 	help
 	  Select this option to have edk2 use an external GOP driver for display init.
diff --git a/payloads/external/edk2/Makefile b/payloads/external/edk2/Makefile
index 0b343b3d7a..4eaf80b50e 100644
--- a/payloads/external/edk2/Makefile
+++ b/payloads/external/edk2/Makefile
@@ -130,9 +130,9 @@ BUILD_STR += -D CAPSULE_MAIN_FW_GUID=$(CONFIG_DRIVERS_EFI_MAIN_FW_GUID)
 endif
 
 #
-# The MrChromebox repository has the following addition options:
+# One or more downstream edk2 repositories support the following additional options:
 #
-ifeq ($(CONFIG_EDK2_REPO_MRCHROMEBOX),y)
+ifeq ($(CONFIG_EDK2_REPO_OFFICIAL),)
 
 # FOLLOW_BGRT_SPEC		= FALSE
 ifeq ($(CONFIG_EDK2_FOLLOW_BGRT_SPEC),y)
@@ -159,7 +159,7 @@ ifeq ($(CONFIG_EDK2_LOAD_OPTION_ROMS),y)
 BUILD_STR += -D LOAD_OPTION_ROMS=TRUE
 endif
 
-endif
+endif # !CONFIG_EDK2_REPO_OFFICIAL
 
 #
 # EDKII has the below PCDs that are relevant to coreboot:

From a907c6fb8d16bf47844fd44e5894c36543fdaa9c Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Sun, 16 Nov 2025 16:34:45 -0600
Subject: [PATCH 2505/3886] payloads/ipxe: Default to building from master
 branch
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

per ipxe.org:
iPXE uses a rolling release model, in which every commit is intended
to be production-ready. You should always use the latest code.

TEST=build/boot ipxe.efi from master branch via EFI shell.

Change-Id: Iae03d94291a8c02c54eb77e61f878902fead27c2
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90059
Reviewed-by: Filip Lewiński <filip.lewinski@3mdeb.com>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-by: Walter Sonius <walterav1984@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 payloads/external/iPXE/Kconfig | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/payloads/external/iPXE/Kconfig b/payloads/external/iPXE/Kconfig
index 85e8c69296..738f49cc15 100644
--- a/payloads/external/iPXE/Kconfig
+++ b/payloads/external/iPXE/Kconfig
@@ -51,7 +51,7 @@ if BUILD_IPXE
 
 choice
 	prompt "iPXE version"
-	default IPXE_STABLE
+	default IPXE_MASTER
 
 config IPXE_STABLE
 	bool "2022.1"

From 962edb7e6dbf3cd2bade780ac5e1b3d691c66416 Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Sun, 16 Nov 2025 16:37:13 -0600
Subject: [PATCH 2506/3886] payloads/ipxe: Guard PXE_ROM_ID for non-EFI builds
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

This config has no use for EFI builds, so guard it as such.

Change-Id: I6a25533d716f8d46f69d9eb518e8a07f20050839
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90060
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-by: Filip Lewiński <filip.lewinski@3mdeb.com>
Reviewed-by: Walter Sonius <walterav1984@gmail.com>
---
 payloads/external/iPXE/Kconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/payloads/external/iPXE/Kconfig b/payloads/external/iPXE/Kconfig
index 738f49cc15..845a8a1652 100644
--- a/payloads/external/iPXE/Kconfig
+++ b/payloads/external/iPXE/Kconfig
@@ -34,6 +34,7 @@ config PXE_ROM_FILE
 
 config PXE_ROM_ID
 	string "network card PCI IDs"
+	depends on !IPXE_BUILD_EFI
 	default "10ec,8168"
 	help
 	  The comma-separated PCI vendor and device ID that would associate

From f40de4e1622fec2aa2bd7d9572aa7409330df271 Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Sun, 16 Nov 2025 16:38:31 -0600
Subject: [PATCH 2507/3886] payloads/ipxe: Default enable serial output only if
 CONSOLE_SERIAL
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

If coreboot serial output is not enabled, it is pointless to enable
iPXE serial console as there's nowhere for the outout to go.

Change-Id: I91e76f255a674f8bfb849310f791b57a8cbcfd09
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90061
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Walter Sonius <walterav1984@gmail.com>
Reviewed-by: Filip Lewiński <filip.lewinski@3mdeb.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
---
 payloads/external/iPXE/Kconfig | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/payloads/external/iPXE/Kconfig b/payloads/external/iPXE/Kconfig
index 845a8a1652..fd427e9754 100644
--- a/payloads/external/iPXE/Kconfig
+++ b/payloads/external/iPXE/Kconfig
@@ -71,7 +71,7 @@ endchoice
 
 config IPXE_SERIAL_CONSOLE
 	bool "Enable iPXE serial console"
-	def_bool y
+	def_bool y if CONSOLE_SERIAL
 	help
 	  Enable/disable iPXE serial console. Since SeaBIOS supports serial
 	  console this option might be helpful to avoid duplicated output.

From 567470cbb3e0fa74797ddf3561cece0ebd4b9ff3 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Micha=C5=82=20Kope=C4=87?= <michal.kopec@3mdeb.com>
Date: Wed, 3 Apr 2024 12:06:20 +0200
Subject: [PATCH 2508/3886] payloads/edk2: Add iPXE EFI support for EDK2
 payload
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Add support for building iPXE as an EFI target and including it in
the EDK2 payload as a boot option. This allows network booting
directly from the UEFI boot menu without requiring a separate iPXE
ROM file, as it is integrated into the payload.

As the required payload-side changes are not yet upstream, guard
the option on !EDK2_REPO_OFFICIAL.

Adjust PXE Kconfig defaults so that PXE is built from source as
ipxe.efi when EDK2_ENABLE_IPXE is selected.

TEST=build/boot iPXE from edk2 boot menu on google/fizz.

Change-Id: Ied61c7b8aa7a34261d6c6f7fd089b1affdc7d3f6
Signed-off-by: Michał Kopeć <michal.kopec@3mdeb.com>
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82721
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-by: Walter Sonius <walterav1984@gmail.com>
---
 payloads/external/Makefile.mk   | 21 +++++++++++++++++----
 payloads/external/edk2/Kconfig  | 18 ++++++++++++++++++
 payloads/external/edk2/Makefile | 15 ++++++++++++++-
 payloads/external/iPXE/Kconfig  |  2 ++
 4 files changed, 51 insertions(+), 5 deletions(-)

diff --git a/payloads/external/Makefile.mk b/payloads/external/Makefile.mk
index c0882c426d..1a494486db 100644
--- a/payloads/external/Makefile.mk
+++ b/payloads/external/Makefile.mk
@@ -156,7 +156,11 @@ payloads/external/depthcharge/depthcharge/build/depthcharge.elf depthcharge: $(D
 
 # edk2
 
-$(obj)/UEFIPAYLOAD.fd: $(DOTCONFIG)
+ifeq ($(CONFIG_EDK2_ENABLE_IPXE),y)
+IPXE_EFI := payloads/external/iPXE/ipxe/ipxe.rom
+endif
+
+$(obj)/UEFIPAYLOAD.fd: $(DOTCONFIG) $(IPXE_EFI)
 	$(MAKE) -C payloads/external/edk2 UefiPayloadPkg \
 		HOSTCC="$(HOSTCC)" \
 		CC="$(HOSTCC)" \
@@ -208,7 +212,9 @@ $(obj)/UEFIPAYLOAD.fd: $(DOTCONFIG)
 		OBJCOPY_x86_64=$(OBJCOPY_x86_64) \
 		OBJCOPY_arm=$(OBJCOPY_arm) \
 		OBJCOPY_arm64=$(OBJCOPY_arm64) \
-		MFLAGS= MAKEFLAGS=
+		MFLAGS= MAKEFLAGS= \
+		CONFIG_EDK2_IPXE=$(CONFIG_EDK2_ENABLE_IPXE) \
+		CONFIG_EDK2_IPXE_OPTION_NAME=$(CONFIG_EDK2_IPXE_OPTION_NAME)
 
 $(obj)/ShimmedUniversalPayload.elf: $(DOTCONFIG)
 	$(MAKE) -C payloads/external/edk2 UniversalPayload \
@@ -367,13 +373,18 @@ else
 IPXE_SERIAL_CONSOLE = n
 endif
 
+ifneq ($(CONFIG_EDK2_ENABLE_IPXE),y)
 cbfs-files-$(CONFIG_PXE_ROM)$(CONFIG_BUILD_IPXE) += pci$(CONFIG_PXE_ROM_ID).rom
 pci$(CONFIG_PXE_ROM_ID).rom-file := $(PXE_ROM_FILE)
 pci$(CONFIG_PXE_ROM_ID).rom-type := raw
+IPXE_CROSS_COMPILE:="$(CROSS_COMPILE_$(ARCH-ramstage-y))"
+else
+IPXE_CROSS_COMPILE:=$(CROSS_COMPILE_x86_64)
+endif
 
 payloads/external/iPXE/ipxe/ipxe.rom ipxe: $(DOTCONFIG) $(IPXE_CONFIG_SCRIPT)
 	$(MAKE) -C payloads/external/iPXE all \
-	CROSS_COMPILE="$(CROSS_COMPILE_$(ARCH-ramstage-y))" \
+	CROSS_COMPILE=$(IPXE_CROSS_COMPILE) \
 	PXE_ROM_PCI_ID=$(PXE_ROM_PCI_ID) \
 	CONFIG_IPXE_MASTER=$(CONFIG_IPXE_MASTER) \
 	CONFIG_IPXE_STABLE=$(CONFIG_IPXE_STABLE) \
@@ -384,7 +395,9 @@ payloads/external/iPXE/ipxe/ipxe.rom ipxe: $(DOTCONFIG) $(IPXE_CONFIG_SCRIPT)
 	CONFIG_HAS_SCRIPT=$(CONFIG_IPXE_ADD_SCRIPT) \
 	CONFIG_IPXE_NO_PROMPT=$(CONFIG_IPXE_NO_PROMPT) \
 	CONFIG_IPXE_HAS_HTTPS=$(CONFIG_IPXE_HAS_HTTPS) \
-	CONFIG_IPXE_TRUST_CMD=$(CONFIG_IPXE_TRUST_CMD)
+	CONFIG_IPXE_TRUST_CMD=$(CONFIG_IPXE_TRUST_CMD) \
+	CFLAGS_x86_64="$(CFLAGS_x86_64)" \
+	CONFIG_IPXE_BUILD_EFI=$(CONFIG_EDK2_ENABLE_IPXE) \
 
 # LinuxBoot
 LINUXBOOT_CROSS_COMPILE_ARCH-$(CONFIG_LINUXBOOT_X86)        = x86_32
diff --git a/payloads/external/edk2/Kconfig b/payloads/external/edk2/Kconfig
index dc76251fb2..7bfd486f7a 100644
--- a/payloads/external/edk2/Kconfig
+++ b/payloads/external/edk2/Kconfig
@@ -317,4 +317,22 @@ config EDK2_CUSTOM_BUILD_PARAMS
 
 	  This option can support both macros `-D` and Pcds `--pcd`.
 
+config EDK2_ENABLE_IPXE
+	bool "Include iPXE in edk2 payload"
+	depends on !EDK2_REPO_OFFICIAL
+	default n
+	select PXE
+	help
+	  Instructs coreboot build system to build iPXE EFI target and include
+	  it in the EDK2 payload.
+
+config EDK2_IPXE_OPTION_NAME
+	string "iPXE option name"
+	depends on EDK2_ENABLE_IPXE
+	default "iPXE Network Boot"
+	help
+	  Configures how the iPXE boot option should be displayed in boot menu
+	  of EDK2 Payload. This name will be passed as PCD to the EDK2 build
+	  system.
+
 endif
diff --git a/payloads/external/edk2/Makefile b/payloads/external/edk2/Makefile
index 4eaf80b50e..6122cd4d30 100644
--- a/payloads/external/edk2/Makefile
+++ b/payloads/external/edk2/Makefile
@@ -158,6 +158,11 @@ endif
 ifeq ($(CONFIG_EDK2_LOAD_OPTION_ROMS),y)
 BUILD_STR += -D LOAD_OPTION_ROMS=TRUE
 endif
+# NETWORK_IPXE                  = FALSE
+ifeq ($(CONFIG_EDK2_IPXE),y)
+BUILD_STR += -D NETWORK_IPXE=TRUE
+BUILD_STR += --pcd gUefiPayloadPkgTokenSpaceGuid.PcdiPXEOptionName=L"$(CONFIG_EDK2_IPXE_OPTION_NAME)"
+endif
 
 endif # !CONFIG_EDK2_REPO_OFFICIAL
 
@@ -248,6 +253,14 @@ gop_driver: $(EDK2_PATH)
 		cp $(top)/$(CONFIG_INTEL_GMA_VBT_FILE) $(EDK2_PATH)/UefiPayloadPkg/vbt.bin; \
 	fi; \
 
+ipxe_rom: $(EDK2_PATH)
+	if [ "$(CONFIG_EDK2_IPXE)" == "y" ]; then \
+		echo "    Including externally built iPXE"; \
+		mkdir -p $(EDK2_PATH)/UefiPayloadPkg/NetworkDrivers/; \
+		cp $(top)/payloads/external/iPXE/ipxe/ipxe.rom \
+			$(EDK2_PATH)/UefiPayloadPkg/NetworkDrivers/ipxe.efi; \
+	fi \
+
 checktools:
 	echo -n "EDK2: Checking uuid-dev:"
 	echo "#include <uuid/uuid.h>" > libtest.c
@@ -285,7 +298,7 @@ print:
 		-e 's/s /Build:          Silent/' \
 		-e 's/t /Toolchain:      /'
 
-prep: $(EDK2_PATH) $(EDK2_PLATFORMS_PATH) clean checktools logo gop_driver
+prep: $(EDK2_PATH) $(EDK2_PLATFORMS_PATH) clean checktools logo gop_driver ipxe_rom
 	cd $(WORKSPACE); \
 		source $(EDK2_PATH)/edksetup.sh; \
 		unset CC; $(MAKE) -C $(EDK2_PATH)/BaseTools 2>&1; \
diff --git a/payloads/external/iPXE/Kconfig b/payloads/external/iPXE/Kconfig
index fd427e9754..14f8898f4e 100644
--- a/payloads/external/iPXE/Kconfig
+++ b/payloads/external/iPXE/Kconfig
@@ -10,6 +10,7 @@ menu "PXE Options"
 
 choice
 	prompt "PXE ROM to use"
+	default BUILD_IPXE if EDK2_ENABLE_IPXE
 	default PXE_ROM
 
 config PXE_ROM
@@ -120,6 +121,7 @@ config IPXE_TRUST_CMD
 config IPXE_BUILD_EFI
 	bool "Build iPXE for EFI target"
 	depends on PAYLOAD_EDK2
+	default y if EDK2_ENABLE_IPXE
 	default n
 	help
 	  Build iPXE for EFI target, enabling it to be executed from EDK2. If not

From a4242e5c388b0d2014959a9ded6a3a61370795f7 Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Tue, 18 Nov 2025 12:03:42 -0600
Subject: [PATCH 2509/3886] ec/starlabs/merlin: Fix get_ec_value_from_option()
 value validation

The function incorrectly treated option values as array indices.
Update the function to search the LUT array for the value, and return
it if found, otherwise return the fallback value (not index).

Update call sites to pass EC value constants (SEC_30, FN_CTRL, etc.)
as the fallback values instead of numeric indices.

TEST=build/boot starlabs/starlite, verify charge limit and other EC
options work properly and values set properly in ECRAM using ectool.

Change-Id: Ie44d912932c8a3cec6ce0829c024788421cf89aa
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90100
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
---
 src/ec/starlabs/merlin/ite.c | 33 ++++++++++++++++++---------------
 1 file changed, 18 insertions(+), 15 deletions(-)

diff --git a/src/ec/starlabs/merlin/ite.c b/src/ec/starlabs/merlin/ite.c
index f0566a9bd2..c239b061ad 100644
--- a/src/ec/starlabs/merlin/ite.c
+++ b/src/ec/starlabs/merlin/ite.c
@@ -41,16 +41,19 @@ static uint8_t get_ec_value_from_option(const char *name,
 					uint32_t cmos_start_bit,
 					uint32_t cmos_length)
 {
-	unsigned int index;
+	uint8_t value;
 
 	if (cmos_start_bit != UINT_MAX)
-		index = get_cmos_value(cmos_start_bit, cmos_length);
+		value = get_cmos_value(cmos_start_bit, cmos_length);
 	else
-		index = get_uint_option(name, fallback);
+		value = get_uint_option(name, fallback);
 
-	if (index >= lut_size)
-		index = fallback;
-	return lut[index];
+	/* Check if the value exists in the LUT array */
+	for (int i = 0; i < lut_size; i++)
+		if (lut[i] == value)
+			return value;
+
+	return fallback;
 }
 
 static uint16_t ec_get_chip_id(unsigned int port)
@@ -118,7 +121,7 @@ static void merlin_init(struct device *dev)
 
 	ec_write(ECRAM_KBL_TIMEOUT,
 		get_ec_value_from_option("kbl_timeout",
-					 0,
+					 SEC_30,
 					 kbl_timeout,
 					 ARRAY_SIZE(kbl_timeout),
 					 UINT_MAX,
@@ -140,7 +143,7 @@ static void merlin_init(struct device *dev)
 
 	ec_write(ECRAM_FN_CTRL_REVERSE,
 		get_ec_value_from_option("fn_ctrl_swap",
-					 0,
+					 FN_CTRL,
 					 fn_ctrl_swap,
 					 ARRAY_SIZE(fn_ctrl_swap),
 					 UINT_MAX,
@@ -164,7 +167,7 @@ static void merlin_init(struct device *dev)
 	if (CONFIG(EC_STARLABS_MAX_CHARGE))
 		ec_write(ECRAM_MAX_CHARGE,
 			get_ec_value_from_option("max_charge",
-						 0,
+						 CHARGE_100,
 						 max_charge,
 						 ARRAY_SIZE(max_charge),
 						 UINT_MAX,
@@ -189,7 +192,7 @@ static void merlin_init(struct device *dev)
 	if (CONFIG(EC_STARLABS_FAN))
 		ec_write(ECRAM_FAN_MODE,
 			get_ec_value_from_option("fan_mode",
-						 0,
+						 FAN_NORMAL,
 						 fan_mode,
 						 ARRAY_SIZE(fan_mode),
 						 UINT_MAX,
@@ -212,7 +215,7 @@ static void merlin_init(struct device *dev)
 
 	ec_write(ECRAM_FN_LOCK_STATE,
 		get_ec_value_from_option("fn_lock_state",
-					 1,
+					 UNLOCKED,
 					 fn_lock_state,
 					 ARRAY_SIZE(fn_lock_state),
 					 CMOS_VSTART_fn_lock_state,
@@ -236,7 +239,7 @@ static void merlin_init(struct device *dev)
 
 	ec_write(ECRAM_TRACKPAD_STATE,
 		get_ec_value_from_option("trackpad_state",
-					 0,
+					 TRACKPAD_ENABLED,
 					 trackpad_state,
 					 ARRAY_SIZE(trackpad_state),
 					 CMOS_VSTART_trackpad_state,
@@ -262,7 +265,7 @@ static void merlin_init(struct device *dev)
 
 	ec_write(ECRAM_KBL_BRIGHTNESS,
 		get_ec_value_from_option("kbl_brightness",
-			CONFIG(EC_STARLABS_KBL_LEVELS) ? 2 : 0,
+			CONFIG(EC_STARLABS_KBL_LEVELS) ? KBL_LOW : KBL_ON,
 			kbl_brightness,
 			ARRAY_SIZE(kbl_brightness),
 			CMOS_VSTART_kbl_brightness,
@@ -327,7 +330,7 @@ static void merlin_init(struct device *dev)
 	if (CONFIG(EC_STARLABS_LID_SWITCH))
 		ec_write(ECRAM_LID_SWITCH,
 			get_ec_value_from_option("lid_switch",
-				0,
+				SWITCH_NORMAL,
 				lid_switch,
 				ARRAY_SIZE(lid_switch),
 				UINT_MAX,
@@ -351,7 +354,7 @@ static void merlin_init(struct device *dev)
 	if (CONFIG(EC_STARLABS_POWER_LED))
 		ec_write(ECRAM_POWER_LED,
 			get_ec_value_from_option("power_led",
-				0,
+				LED_NORMAL,
 				power_led,
 				ARRAY_SIZE(power_led),
 				UINT_MAX,

From 8401bbd2ff71a2fab6b5f73791e05ff0bc65ca50 Mon Sep 17 00:00:00 2001
From: Luca Lai <luca.lai@lcfc.corp-partner.google.com>
Date: Tue, 18 Nov 2025 20:45:33 +0800
Subject: [PATCH 2510/3886] mb/google/fatcat/var/ruby: Change touch panel
 address

Change touch panel address from 0x14 to 0x5d for EVT build.

BUG=b:452216678
TEST=Build FW and boot to OS, check touch function works.

Change-Id: Ic19ce19a7bc4c8e370b2f2078e8f457e4f275012
Signed-off-by: Luca Lai <luca.lai@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90092
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/google/fatcat/variants/ruby/overridetree.cb | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/mainboard/google/fatcat/variants/ruby/overridetree.cb b/src/mainboard/google/fatcat/variants/ruby/overridetree.cb
index a7f37a8840..76fce5287f 100644
--- a/src/mainboard/google/fatcat/variants/ruby/overridetree.cb
+++ b/src/mainboard/google/fatcat/variants/ruby/overridetree.cb
@@ -301,7 +301,7 @@ chip soc/intel/pantherlake
 				register "generic.has_power_resource" = "1"
 				register "generic.use_gpio_for_status" = "true"
 				register "hid_desc_reg_offset" = "0x01"
-				device i2c 0x14 on end
+				device i2c 0x5d on end
 			end
 		end # I2C5
 		device ref gspi0 on end

From 872e06d60c8761f1ea97deb38af4fb875a520e4f Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Wed, 12 Nov 2025 11:59:16 -0600
Subject: [PATCH 2511/3886] mb/samsung/stumpy: inline fan thresholds and drop
 GNVS programming
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

- mirror Beltino’s thermal AML pattern by including `thermal.h` and
  using the static macros directly
- add `_INI` and `_STA`-guarded power resources so FAN4 idle state is
  established without relying on preseeded GNVS values
- remove the now-unused GNVS fan table and temperature fields from
  `acpi_tables.c`, leaving only the USB suspend defaults

This simplifies Stumpy's fan control and unifies it with newer boards
like Beltino and Jecht, and fixes an issue where the fan was not
starting automatically under Windows.

TEST=build/boot Win11, Ubuntu 25.10 on Stumpy, verify fan starts and
adjusts automatically, CPU temps kept under control.

Change-Id: Ie9c8c46e4bf3412ea60d7fe8f2d97651bca266f1
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90056
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
---
 src/mainboard/samsung/stumpy/acpi/thermal.asl | 114 +++++++++++-------
 src/mainboard/samsung/stumpy/acpi_tables.c    |  27 -----
 2 files changed, 71 insertions(+), 70 deletions(-)

diff --git a/src/mainboard/samsung/stumpy/acpi/thermal.asl b/src/mainboard/samsung/stumpy/acpi/thermal.asl
index 2dcb13fabe..cc8a060443 100644
--- a/src/mainboard/samsung/stumpy/acpi/thermal.asl
+++ b/src/mainboard/samsung/stumpy/acpi/thermal.asl
@@ -2,6 +2,8 @@
 
 // Thermal Zone
 
+#include "../thermal.h"
+
 External (\PPKG, MethodObj)
 
 Scope (\_TZ)
@@ -31,13 +33,13 @@ Scope (\_TZ)
 		// Threshold for OS to shutdown
 		Method (_CRT, 0, Serialized)
 		{
-			Return (CTOK (\TCRT))
+			Return (CTOK (CRITICAL_TEMPERATURE))
 		}
 
 		// Threshold for passive cooling
 		Method (_PSV, 0, Serialized)
 		{
-			Return (CTOK (\TPSV))
+			Return (CTOK (PASSIVE_TEMPERATURE))
 		}
 
 		// Processors used for passive cooling
@@ -46,6 +48,14 @@ Scope (\_TZ)
 			Return (\PPKG ())
 		}
 
+		// Initialize to the lowest cooling state (fan idle)
+		Method (_INI)
+		{
+			\FLVL = 4
+			\_SB.PCI0.LPCB.SIO.ENVC.F3PS = FAN4_PWM
+			Notify (\_TZ.THRM, 0x81)
+		}
+
 		Method (_TMP, 0, Serialized)
 		{
 			// Get CPU Temperature from PECI via SuperIO TMPIN3
@@ -53,59 +63,59 @@ Scope (\_TZ)
 
 			// Check for invalid readings
 			If ((Local0 == 255) || (Local0 == 0)) {
-				Return (CTOK (\F2ON))
+				Return (CTOK (FAN2_THRESHOLD_ON))
 			}
 
 			// PECI raw value is an offset from Tj_max
 			Local1 = 255 - Local0
 
 			// Handle values greater than Tj_max
-			If (Local1 >= \TMAX) {
-				Return (CTOK (\TMAX))
+			If (Local1 >= MAX_TEMPERATURE) {
+				Return (CTOK (MAX_TEMPERATURE))
 			}
 
 			// Subtract from Tj_max to get temperature
-			Local0 = \TMAX - Local1
+			Local0 = MAX_TEMPERATURE - Local1
 			Return (CTOK (Local0))
 		}
 
 		Method (_AC0) {
 			If (\FLVL <= 0) {
-				Return (CTOK (\F0OF))
+				Return (CTOK (FAN0_THRESHOLD_OFF))
 			} Else {
-				Return (CTOK (\F0ON))
+				Return (CTOK (FAN0_THRESHOLD_ON))
 			}
 		}
 
 		Method (_AC1) {
 			If (\FLVL <= 1) {
-				Return (CTOK (\F1OF))
+				Return (CTOK (FAN1_THRESHOLD_OFF))
 			} Else {
-				Return (CTOK (\F1ON))
+				Return (CTOK (FAN1_THRESHOLD_ON))
 			}
 		}
 
 		Method (_AC2) {
 			If (\FLVL <= 2) {
-				Return (CTOK (\F2OF))
+				Return (CTOK (FAN2_THRESHOLD_OFF))
 			} Else {
-				Return (CTOK (\F2ON))
+				Return (CTOK (FAN2_THRESHOLD_ON))
 			}
 		}
 
 		Method (_AC3) {
 			If (\FLVL <= 3) {
-				Return (CTOK (\F3OF))
+				Return (CTOK (FAN3_THRESHOLD_OFF))
 			} Else {
-				Return (CTOK (\F3ON))
+				Return (CTOK (FAN3_THRESHOLD_ON))
 			}
 		}
 
 		Method (_AC4) {
 			If (\FLVL <= 4) {
-				Return (CTOK (\F4OF))
+				Return (CTOK (FAN4_THRESHOLD_OFF))
 			} Else {
-				Return (CTOK (\F4ON))
+				Return (CTOK (FAN4_THRESHOLD_ON))
 			}
 		}
 
@@ -125,14 +135,18 @@ Scope (\_TZ)
 				}
 			}
 			Method (_ON)  {
-				\FLVL = 0
-				\_SB.PCI0.LPCB.SIO.ENVC.F3PS = \F0PW
-				Notify (\_TZ.THRM, 0x81)
+				If (! _STA ()) {
+					\FLVL = 0
+					\_SB.PCI0.LPCB.SIO.ENVC.F3PS = FAN0_PWM
+					Notify (\_TZ.THRM, 0x81)
+				}
 			}
 			Method (_OFF) {
-				\FLVL = 1
-				\_SB.PCI0.LPCB.SIO.ENVC.F3PS = \F1PW
-				Notify (\_TZ.THRM, 0x81)
+				If (_STA ()) {
+					\FLVL = 1
+					\_SB.PCI0.LPCB.SIO.ENVC.F3PS = FAN1_PWM
+					Notify (\_TZ.THRM, 0x81)
+				}
 			}
 		}
 
@@ -146,14 +160,18 @@ Scope (\_TZ)
 				}
 			}
 			Method (_ON)  {
-				\FLVL = 1
-				\_SB.PCI0.LPCB.SIO.ENVC.F3PS = \F1PW
-				Notify (\_TZ.THRM, 0x81)
+				If (! _STA ()) {
+					\FLVL = 1
+					\_SB.PCI0.LPCB.SIO.ENVC.F3PS = FAN1_PWM
+					Notify (\_TZ.THRM, 0x81)
+				}
 			}
 			Method (_OFF) {
-				\FLVL = 2
-				\_SB.PCI0.LPCB.SIO.ENVC.F3PS = \F2PW
-				Notify (\_TZ.THRM, 0x81)
+				If (_STA ()) {
+					\FLVL = 2
+					\_SB.PCI0.LPCB.SIO.ENVC.F3PS = FAN2_PWM
+					Notify (\_TZ.THRM, 0x81)
+				}
 			}
 		}
 
@@ -167,14 +185,18 @@ Scope (\_TZ)
 				}
 			}
 			Method (_ON)  {
-				\FLVL = 2
-				\_SB.PCI0.LPCB.SIO.ENVC.F3PS = \F2PW
-				Notify (\_TZ.THRM, 0x81)
+				If (! _STA ()) {
+					\FLVL = 2
+					\_SB.PCI0.LPCB.SIO.ENVC.F3PS = FAN2_PWM
+					Notify (\_TZ.THRM, 0x81)
+				}
 			}
 			Method (_OFF) {
-				\FLVL = 3
-				\_SB.PCI0.LPCB.SIO.ENVC.F3PS = \F3PW
-				Notify (\_TZ.THRM, 0x81)
+				If (_STA ()) {
+					\FLVL = 3
+					\_SB.PCI0.LPCB.SIO.ENVC.F3PS = FAN3_PWM
+					Notify (\_TZ.THRM, 0x81)
+				}
 			}
 		}
 
@@ -188,14 +210,18 @@ Scope (\_TZ)
 				}
 			}
 			Method (_ON)  {
-				\FLVL = 3
-				\_SB.PCI0.LPCB.SIO.ENVC.F3PS = \F3PW
-				Notify (\_TZ.THRM, 0x81)
+				If (! _STA ()) {
+					\FLVL = 3
+					\_SB.PCI0.LPCB.SIO.ENVC.F3PS = FAN3_PWM
+					Notify (\_TZ.THRM, 0x81)
+				}
 			}
 			Method (_OFF) {
-				\FLVL = 4
-				\_SB.PCI0.LPCB.SIO.ENVC.F3PS = \F4PW
-				Notify (\_TZ.THRM, 0x81)
+				If (_STA ()) {
+					\FLVL = 4
+					\_SB.PCI0.LPCB.SIO.ENVC.F3PS = FAN4_PWM
+					Notify (\_TZ.THRM, 0x81)
+				}
 			}
 		}
 
@@ -209,9 +235,11 @@ Scope (\_TZ)
 				}
 			}
 			Method (_ON)  {
-				\FLVL = 4
-				\_SB.PCI0.LPCB.SIO.ENVC.F3PS = \F4PW
-				Notify (\_TZ.THRM, 0x81)
+				If (! _STA ()) {
+					\FLVL = 4
+					\_SB.PCI0.LPCB.SIO.ENVC.F3PS = FAN4_PWM
+					Notify (\_TZ.THRM, 0x81)
+				}
 			}
 			Method (_OFF) {
 				// FAN4 is the minimum cooling state (idle/lowest fan speed)
diff --git a/src/mainboard/samsung/stumpy/acpi_tables.c b/src/mainboard/samsung/stumpy/acpi_tables.c
index 6912ca1a76..9c8c690e93 100644
--- a/src/mainboard/samsung/stumpy/acpi_tables.c
+++ b/src/mainboard/samsung/stumpy/acpi_tables.c
@@ -4,8 +4,6 @@
 #include <device/device.h>
 #include <soc/nvs.h>
 
-#include "thermal.h"
-
 void mainboard_fill_gnvs(struct global_nvs *gnvs)
 {
 	/* Enable Front USB ports in S3 by default */
@@ -18,29 +16,4 @@ void mainboard_fill_gnvs(struct global_nvs *gnvs)
 	 */
 	gnvs->s5u0 = 1;
 	gnvs->s5u1 = 1;
-
-	gnvs->f4of = FAN4_THRESHOLD_OFF;
-	gnvs->f4on = FAN4_THRESHOLD_ON;
-	gnvs->f4pw = FAN4_PWM;
-
-	gnvs->f3of = FAN3_THRESHOLD_OFF;
-	gnvs->f3on = FAN3_THRESHOLD_ON;
-	gnvs->f3pw = FAN3_PWM;
-
-	gnvs->f2of = FAN2_THRESHOLD_OFF;
-	gnvs->f2on = FAN2_THRESHOLD_ON;
-	gnvs->f2pw = FAN2_PWM;
-
-	gnvs->f1of = FAN1_THRESHOLD_OFF;
-	gnvs->f1on = FAN1_THRESHOLD_ON;
-	gnvs->f1pw = FAN1_PWM;
-
-	gnvs->f0of = FAN0_THRESHOLD_OFF;
-	gnvs->f0on = FAN0_THRESHOLD_ON;
-	gnvs->f0pw = FAN0_PWM;
-
-	gnvs->tcrt = CRITICAL_TEMPERATURE;
-	gnvs->tpsv = PASSIVE_TEMPERATURE;
-	gnvs->tmax = MAX_TEMPERATURE;
-	gnvs->flvl = 5;
 }

From abc87d533d327cc23aafde79aefe1ebdd9c2d85b Mon Sep 17 00:00:00 2001
From: Kapil Porwal <kapilporwal@google.com>
Date: Mon, 17 Nov 2025 23:24:17 +0530
Subject: [PATCH 2512/3886] mb/google/bluey: Introduce config to specify
 absence of USB-A port

This commit introduces the MAINBOARD_NO_USB_A_PORT Kconfig option
to allow boards derived from the 'bluey' base to specify when they
do not include a physical USB Type-A receptacle.

For boards like 'Quartz' which are Type-C only, this configuration
prevents attempts to initialize the USB-A retimer (which connects
via QUPV3_0_SE1 I2C bus) during the mainboard initialization sequence.
Skipping this unnecessary initialization avoids potential bus errors
on Type-C-only devices.

Key changes:
- Define new Kconfig option MAINBOARD_NO_USB_A_PORT.
- Select MAINBOARD_NO_USB_A_PORT for BOARD_GOOGLE_QUARTZ.
- In mainboard.c, conditionally execute the USB-A retimer
initialization based on the new configuration option.

BUG=b:445441291
TEST=Build and boot to Google/Quenbi.

Change-Id: Ia02092100c4e8c46106aff30db21461781d66419
Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90075
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/google/bluey/Kconfig     | 7 +++++++
 src/mainboard/google/bluey/mainboard.c | 3 ++-
 2 files changed, 9 insertions(+), 1 deletion(-)

diff --git a/src/mainboard/google/bluey/Kconfig b/src/mainboard/google/bluey/Kconfig
index 0f5e8c3950..53f6de67d8 100644
--- a/src/mainboard/google/bluey/Kconfig
+++ b/src/mainboard/google/bluey/Kconfig
@@ -54,6 +54,7 @@ config BOARD_GOOGLE_QUENBIH
 config BOARD_GOOGLE_QUARTZ
 	select BOARD_GOOGLE_MODEL_QUARTZ
 	select SOC_QUALCOMM_HAMOA
+	select MAINBOARD_NO_USB_A_PORT
 
 if BOARD_GOOGLE_BLUEY_COMMON
 
@@ -87,6 +88,12 @@ config MAINBOARD_HAS_SD_CONTROLLER
 	help
 	  Enable this option if your mainboard is equipped with SD card controller.
 
+config MAINBOARD_NO_USB_A_PORT
+	bool
+	default n
+	help
+	  Enable this option if your mainboard is not equipped with USB-A port.
+
 config MAINBOARD_HAS_GOOGLE_TPM
 	bool
 	default n
diff --git a/src/mainboard/google/bluey/mainboard.c b/src/mainboard/google/bluey/mainboard.c
index 6517842b66..92115f5464 100644
--- a/src/mainboard/google/bluey/mainboard.c
+++ b/src/mainboard/google/bluey/mainboard.c
@@ -100,7 +100,8 @@ static void mainboard_init(struct device *dev)
 	qupv3_se_fw_load_and_init(QUPV3_1_SE0, SE_PROTOCOL_I2C, MIXED); /* Touch I2C */
 	qupv3_se_fw_load_and_init(QUPV3_1_SE6, SE_PROTOCOL_UART, FIFO); /* BT UART */
 	qupv3_se_fw_load_and_init(QUPV3_0_SE0, SE_PROTOCOL_I2C, MIXED); /* Trackpad I2C */
-	qupv3_se_fw_load_and_init(QUPV3_0_SE1, SE_PROTOCOL_I2C, MIXED); /* USB-A retimer */
+	if (!CONFIG(MAINBOARD_NO_USB_A_PORT))
+		qupv3_se_fw_load_and_init(QUPV3_0_SE1, SE_PROTOCOL_I2C, MIXED); /* USB-A retimer */
 	if (CONFIG(MAINBOARD_HAS_FINGERPRINT_VIA_SPI))
 		qupv3_se_fw_load_and_init(QUPV3_2_SE2, SE_PROTOCOL_SPI, MIXED); /* Fingerprint SPI */
 

From d3760cdfdf1daadecd7939bf8f311ce0bac84fe3 Mon Sep 17 00:00:00 2001
From: Kapil Porwal <kapilporwal@google.com>
Date: Thu, 6 Nov 2025 19:33:41 +0530
Subject: [PATCH 2513/3886] mb/google/bluey: Configure QUP0 SE5 as I2C

eUSB repeater, which is an I2C device, is connected to QUP0 SE5.

BUG=none
TEST=Build and boot to Google/Quenbi.

Firmware log:
```
[INFO ]  VB2:vb2_digest_init() 3872 bytes, hash algo 2, HW acceleration enabled
[INFO ]  CBFS: Found 'fallback/i2c_fw' @0xaa280 size 0x576 in mcache @0xc77dd470
```

OS:
```
/sys/devices/platform/soc/bc0000.qcom,qupv3_0_geni_se/b94000.i2c/i2c-5
```

Change-Id: Ia6a3e1f68b945f93e77b4370f81015fbc68d74d3
Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89931
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
---
 src/mainboard/google/bluey/mainboard.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/src/mainboard/google/bluey/mainboard.c b/src/mainboard/google/bluey/mainboard.c
index 92115f5464..c20d98bbf5 100644
--- a/src/mainboard/google/bluey/mainboard.c
+++ b/src/mainboard/google/bluey/mainboard.c
@@ -102,6 +102,7 @@ static void mainboard_init(struct device *dev)
 	qupv3_se_fw_load_and_init(QUPV3_0_SE0, SE_PROTOCOL_I2C, MIXED); /* Trackpad I2C */
 	if (!CONFIG(MAINBOARD_NO_USB_A_PORT))
 		qupv3_se_fw_load_and_init(QUPV3_0_SE1, SE_PROTOCOL_I2C, MIXED); /* USB-A retimer */
+	qupv3_se_fw_load_and_init(QUPV3_0_SE5, SE_PROTOCOL_I2C, MIXED); /* eUSB repeater */
 	if (CONFIG(MAINBOARD_HAS_FINGERPRINT_VIA_SPI))
 		qupv3_se_fw_load_and_init(QUPV3_2_SE2, SE_PROTOCOL_SPI, MIXED); /* Fingerprint SPI */
 

From e05492cfb4da46c4079b45ee0097e83180a5123d Mon Sep 17 00:00:00 2001
From: Kapil Porwal <kapilporwal@google.com>
Date: Mon, 17 Nov 2025 22:29:13 +0530
Subject: [PATCH 2514/3886] soc/intel/pantherlake/romstage: Configure VGA mode
 12 monochrome buffer
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

This commit implements support for the FSP_VGA_MODE12_MONOCHROME
Kconfig option within the Panther Lake romstage code.

By checking for the CONFIG_FSP_VGA_MODE12_MONOCHROME option, we
set the corresponding VGA_INIT_CONTROL_MODE12_MONOCHROME bit in
the FSP_M_CONFIG structure.

This ensures that when a 1-bit-per-pixel framebuffer is used, the
Intel FSP is correctly informed to replicate the data across the
remaining color planes for display, saving 75% of framebuffer memory
in romstage.

Key changes:
- Define the new VGA_INIT_CONTROL_MODE12_MONOCHROME control bit.
- Conditionally set this control bit in setup_vga_mode12_params()
when CONFIG_FSP_VGA_MODE12_MONOCHROME is enabled.

BUG=b:406725440
TEST=Verify VGA text rotation on Google/Felino.

Change-Id: I1dec24bb7ed44ca07babe0aa6886a50952d3faa2
Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90073
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
---
 src/soc/intel/pantherlake/romstage/ux.c | 2 ++
 src/soc/intel/pantherlake/romstage/ux.h | 1 +
 2 files changed, 3 insertions(+)

diff --git a/src/soc/intel/pantherlake/romstage/ux.c b/src/soc/intel/pantherlake/romstage/ux.c
index 4e346f439f..e0a84257dc 100644
--- a/src/soc/intel/pantherlake/romstage/ux.c
+++ b/src/soc/intel/pantherlake/romstage/ux.c
@@ -46,6 +46,8 @@ static void setup_vga_mode12_params(FSP_M_CONFIG *m_cfg, enum ux_locale_msg id)
 	m_cfg->LogoXPosition = (VGA12_WIDTH - img_width) / 2;
 	m_cfg->LogoYPosition = (VGA12_HEIGHT - img_height) / 2;
 	m_cfg->VgaInitControl |= VGA_INIT_CONTROL_MODE12;
+	if (CONFIG(FSP_VGA_MODE12_MONOCHROME))
+		m_cfg->VgaInitControl |= VGA_INIT_CONTROL_MODE12_MONOCHROME;
 }
 
 static bool ux_inform_user_of_operation(const char *name, enum ux_locale_msg id,
diff --git a/src/soc/intel/pantherlake/romstage/ux.h b/src/soc/intel/pantherlake/romstage/ux.h
index abdaa86eec..6359b5ea5e 100644
--- a/src/soc/intel/pantherlake/romstage/ux.h
+++ b/src/soc/intel/pantherlake/romstage/ux.h
@@ -12,5 +12,6 @@ bool ux_inform_user_of_poweroff_operation(const char *name, FSPM_UPD *mupd);
 #define VGA_INIT_CONTROL_ENABLE		BIT(0)
 #define VGA_INIT_CONTROL_MODE12		BIT(1)
 #define VGA_INIT_DISABLE_ANIMATION	BIT(4)
+#define VGA_INIT_CONTROL_MODE12_MONOCHROME	BIT(5)
 
 #endif /* _SOC_INTEL_PANTHERLAKE_ROMSTAGE_UX_H_ */

From f643141728a4aebd64e1bd35e941cd2447651821 Mon Sep 17 00:00:00 2001
From: Kapil Porwal <kapilporwal@google.com>
Date: Mon, 17 Nov 2025 22:40:05 +0530
Subject: [PATCH 2515/3886] mb/google/fatcat: Option to enable monochrome VGA
 mode 12

Update the Fatcat mainboard Kconfig to select
FSP_VGA_MODE12_MONOCHROME. The FSP_VGA_MODE12_MONOCHROME option enables
the use of a minimal 1-bit-per-pixel (1bpp) framebuffer for early
sign-of-life (eSOL) messages, which significantly reduces the DRAM size
required for the framebuffer in romstage.

Key changes:
- Deselect FSP_VGA_MODE12 for CONFIG_FATCAT_VGA_MODE12_SUPPORT.
- Select FSP_VGA_MODE12_MONOCHROME instead.

BUG=b:406725440
TEST=Verify VGA text rotation on Google/Felino.

Change-Id: I172f01b9766d2aa8e2f86c399ba46f6be008fed3
Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90074
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
---
 src/mainboard/google/fatcat/Kconfig | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/mainboard/google/fatcat/Kconfig b/src/mainboard/google/fatcat/Kconfig
index 54ecd5c02c..5def0388f4 100644
--- a/src/mainboard/google/fatcat/Kconfig
+++ b/src/mainboard/google/fatcat/Kconfig
@@ -265,7 +265,7 @@ config FATCAT_VGA_MODE12_SUPPORT
 	default n
 	depends on FSP_UGOP_EARLY_SIGN_OF_LIFE
 	select ROMSTAGE_VGA
-	select FSP_VGA_MODE12
+	select FSP_VGA_MODE12_MONOCHROME
 	help
 	  Select this if the FSP supports VGA mode 12 for eSOL.
 

From e9c47bf99e4fe177c3bdb1d0980fc6763d28ff4f Mon Sep 17 00:00:00 2001
From: Kapil Porwal <kapilporwal@google.com>
Date: Mon, 17 Nov 2025 22:11:35 +0530
Subject: [PATCH 2516/3886] drivers/intel/fsp2_0: Add 1-bpp monochrome option
 for VGA mode 12
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Add a new Kconfig option, FSP_VGA_MODE12_MONOCHROME, to allow the
system to use a 1-bit-per-pixel (1bpp) planar VGA buffer during FSP
initialization instead of the standard 4bpp buffer. This is useful
in romstage where every byte is critical.

When this option is enabled, the FSP is expected to handle the
internal replication of the 1bpp data across the other three
color planes to render the monochrome image.

Key changes:
- Introduce FSP_VGA_MODE12_MONOCHROME Kconfig option.
- Automatically select FSP_VGA_MODE12 when the monochrome option is
used.
- Set FSP_VGA_MODE12_BPP to 0x1 when FSP_VGA_MODE12_MONOCHROME is
selected.

BUG=b:406725440
TEST=Verify VGA text rotation on Google/Felino.

Change-Id: Ie77c40025c13e52188439fffedc834c26338bfe3
Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90072
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
---
 src/drivers/intel/fsp2_0/Kconfig | 12 ++++++++++++
 1 file changed, 12 insertions(+)

diff --git a/src/drivers/intel/fsp2_0/Kconfig b/src/drivers/intel/fsp2_0/Kconfig
index f864c344e7..3309f99907 100644
--- a/src/drivers/intel/fsp2_0/Kconfig
+++ b/src/drivers/intel/fsp2_0/Kconfig
@@ -507,8 +507,20 @@ config FSP_VGA_MODE12
 	help
 	  Select this if the FSP supports VGA mode 12.
 
+config FSP_VGA_MODE12_MONOCHROME
+	bool
+	default n
+	depends on VGA || ROMSTAGE_VGA
+	select FSP_VGA_MODE12
+	help
+	  Select this if the FSP supports monochrome VGA mode 12. This implies
+	  that FSP can accept 1 bit-per-pixel planar buffer instead of 4 to save
+	  the crucial space. The FSP internally replicates the pixel data to other
+	  3 planes.
+
 config FSP_VGA_MODE12_BPP
 	hex
+	default 0x1 if FSP_VGA_MODE12_MONOCHROME
 	default 0x4 if FSP_VGA_MODE12
 	default 0x0
 	help

From 18dbeca5f40826b2d54c3b018e9e7255cef7e5e3 Mon Sep 17 00:00:00 2001
From: Nicholas Chin <nic.c3.14@gmail.com>
Date: Sun, 16 Nov 2025 11:32:05 -0700
Subject: [PATCH 2517/3886] util/autoport/azalia.go: Select
 CONFIG_AZALIA_USE_LEGACY_VERB_TABLE

As of commit 31fc5b06a6be ("device: Introduce reworked azalia verb
table"), all boards using the old azalia verb table format must select
CONFIG_AZALIA_USE_LEGACY_VERB_TABLE. The generated output of autoport
uses the old format, so select the config.

This is only meant to be a temporary measure as opposed to reworking
autoport to produce the new format, as I would rather incorporate
hda-decoder's functionality to generate hda-verb.c instead of
duplicating efforts. Support for the new format in hda-decoder is
currently WIP on CB:84357.

Change-Id: I54c6a92a69039eb747ee8cc6d5186dc3a3c6acc8
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90055
Reviewed-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 util/autoport/azalia.go | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/util/autoport/azalia.go b/util/autoport/azalia.go
index 1540398281..a7c8b7253b 100644
--- a/util/autoport/azalia.go
+++ b/util/autoport/azalia.go
@@ -9,6 +9,10 @@ type azalia struct {
 }
 
 func (i azalia) Scan(ctx Context, addr PCIDevData) {
+	/* FIXME: Rework to output new verb table format, or better
+	   yet use hda-decoder to avoid duplicating functionality */
+	KconfigBool["AZALIA_USE_LEGACY_VERB_TABLE"] = true
+
 	az := Create(ctx, "hda_verb.c")
 	defer az.Close()
 

From a363007c3bb7df81d476968ea1ea6b816a858bc5 Mon Sep 17 00:00:00 2001
From: Nicholas Chin <nic.c3.14@gmail.com>
Date: Tue, 18 Jun 2024 21:31:08 -0600
Subject: [PATCH 2518/3886] ec/dell/mec5035: Route power button event to host

Currently, pressing the power button results in the EC powering off the
system without letting the OS cleanly execute its shutdown procedures.
Sending command 0x3e with an argument of 1 to the EC tells it to route
power button events to the host so that the OS can determine what to do.

This command was found in the ec/google/wilco code in coreboot, which is
used on Dell's Latitude Chromebooks. Based on the CONFIG_EC_GOOGLE_WILCO
help text, the "Wilco" ECs run a modified version of Dell's typical
Latitude EC firmware, so it is likely that the two implementations share
commands. Examining LPC traffic on the Latitude E6400 did show that
vendor firmware was sending a 0x3e command to the EC, and reimplementing
it in coreboot allowed power button events to be handled by the OS.

Change-Id: I5ded315270c0e1efbbc90cfa9d9d894b872e99a2
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84878
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
---
 src/ec/dell/mec5035/mec5035.c | 8 ++++++++
 src/ec/dell/mec5035/mec5035.h | 6 ++++++
 2 files changed, 14 insertions(+)

diff --git a/src/ec/dell/mec5035/mec5035.c b/src/ec/dell/mec5035/mec5035.c
index dffbb7960c..17ac2c1dab 100644
--- a/src/ec/dell/mec5035/mec5035.c
+++ b/src/ec/dell/mec5035/mec5035.c
@@ -94,6 +94,13 @@ void mec5035_control_radio(enum ec_radio_dev dev, enum ec_radio_state state)
 	ec_command(CMD_RADIO_CTRL);
 }
 
+static void mec5035_power_button_route(enum ec_power_button_route target)
+{
+	u8 buf = (u8)target;
+	write_mailbox_regs(&buf, 2, 1);
+	ec_command(CMD_POWER_BUTTON_TO_HOST);
+}
+
 void mec5035_early_init(void)
 {
 	/* If this isn't sent the EC shuts down the system after about 15
@@ -107,6 +114,7 @@ static void mec5035_init(struct device *dev)
 	/* Unconditionally use this argument for now as this setting
 	   is probably the most sensible default out of the 3 choices. */
 	mec5035_mouse_touchpad(TP_PS2_MOUSE);
+	mec5035_power_button_route(HOST);
 
 	pc_keyboard_init(NO_AUX_DEVICE);
 
diff --git a/src/ec/dell/mec5035/mec5035.h b/src/ec/dell/mec5035/mec5035.h
index 32f791cb01..5fdf56631b 100644
--- a/src/ec/dell/mec5035/mec5035.h
+++ b/src/ec/dell/mec5035/mec5035.h
@@ -10,6 +10,7 @@
 enum mec5035_cmd {
 	CMD_MOUSE_TP = 0x1a,
 	CMD_RADIO_CTRL = 0x2b,
+	CMD_POWER_BUTTON_TO_HOST = 0x3e,
 	CMD_CPU_OK = 0xc2,
 };
 
@@ -33,6 +34,11 @@ enum ec_radio_state {
 	RADIO_ON
 };
 
+enum ec_power_button_route {
+	EC = 0,
+	HOST
+};
+
 u8 mec5035_mouse_touchpad(enum ec_mouse_setting setting);
 void mec5035_cpu_ok(void);
 void mec5035_early_init(void);

From aa1d44b6446018fabe3cf8eac6662aaea4a1996c Mon Sep 17 00:00:00 2001
From: Ian Feng <ian_feng@compal.corp-partner.google.com>
Date: Mon, 17 Nov 2025 15:33:16 +0800
Subject: [PATCH 2519/3886] mb/google/ocelot/var/kodkod: Update gpio settings

Configure GPIOs according to schematics_20251112.

BUG=b:452542491
TEST=emerge-ocelot coreboot

Change-Id: I74890f5980d392fbee75559299fb56fca8ca996a
Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90068
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Pranava Y N <pranavayn@google.com>
---
 .../google/ocelot/variants/kodkod/gpio.c      | 345 ++++++++++--------
 1 file changed, 189 insertions(+), 156 deletions(-)

diff --git a/src/mainboard/google/ocelot/variants/kodkod/gpio.c b/src/mainboard/google/ocelot/variants/kodkod/gpio.c
index 8c9686ea2d..e8884d9c43 100644
--- a/src/mainboard/google/ocelot/variants/kodkod/gpio.c
+++ b/src/mainboard/google/ocelot/variants/kodkod/gpio.c
@@ -29,114 +29,128 @@ static const struct pad_config gpio_table[] = {
 	/* GPP_A06:     ESPI_RST_AIC_N */
 	/*  GPP_A06 : GPP_A06 ==> ESPI_RST_HDR configured on reset, do not touch */
 
-	/* GPP_A08:     M2_GEN4_SSD_RESET_N */
+	/* GPP_A08:     SOC_SSD_RST# */
 	PAD_CFG_GPO(GPP_A08, 1, PLTRST),
 	/* GPP_A09:     NC */
 	PAD_NC(GPP_A09, NONE),
 	/* GPP_A10:     NC */
 	PAD_NC(GPP_A10, NONE),
-	/* GPP_A11:     NC */
+	/* GPP_A11:     SOC_WLAN_RST# */
 	PAD_NC(GPP_A11, NONE),
-	/* GPP_A12:     NC */
+	/* GPP_A12:     NC*/
 	PAD_NC(GPP_A12, NONE),
-	/* GPP_A13:     TCH_PAD_INT_N */
-	PAD_CFG_GPI_APIC_DRIVER(GPP_A13, NONE, PLTRST, EDGE_SINGLE, INVERT),
+	/* GPP_A13:     NC */
+	PAD_NC(GPP_A13, NONE),
 	/* GPP_A15:     NC */
 	PAD_NC(GPP_A15, NONE),
 
 	/* GPP_B */
-	/* GPP_B00:     USBC_SML_CLK_PD */
+	/* GPP_B00:     SOC_USBC_SMLCLK */
 	PAD_CFG_NF(GPP_B00, NONE, DEEP, NF1),
-	/* GPP_B01:     USBC_SML_DATA_PD */
+	/* GPP_B01:     SOC_USBC_SMLDATA */
 	PAD_CFG_NF(GPP_B01, NONE, DEEP, NF1),
-	/* GPP_B02:     ISH_I2C0_SDA_SNSR_HDR */
+	/* GPP_B02:     NC */
 	PAD_NC(GPP_B02, NONE),
-	/* GPP_B03:     ISH_I2C0_SCL_SNSR_HDR */
+	/* GPP_B03:     NC */
 	PAD_NC(GPP_B03, NONE),
-	/* GPP_B04:     ISH_GP_0_SNSR_HDR */
+	/* GPP_B04:     NC */
 	PAD_NC(GPP_B04, NONE),
-	/* GPP_B06:     SOC_PDB_CTRL */
-	PAD_CFG_GPO(GPP_B06, 0, DEEP),
+	/* GPP_B05:     NC */
+	PAD_NC(GPP_B05, NONE),
+	/* GPP_B06:     NC */
+	PAD_NC(GPP_B06, NONE),
+	/* GPP_B07:     NC */
+	PAD_NC(GPP_B07, NONE),
 	/* GPP_B08:     NC */
 	PAD_NC(GPP_B08, NONE),
-	/* GPP_B09:     BT_RF_KILL_N */
-	PAD_CFG_GPO(GPP_B09, 1, DEEP),
+	/* GPP_B09:     NC */
+	PAD_NC(GPP_B09, NONE),
 	/* GPP_B10:     NC */
 	PAD_NC(GPP_B10, NONE),
-	/* GPP_B12:     PM_SLP_S0_N */
+	/* GPP_B12:     PM_SLP_S0# */
 	PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1),
-	/* GPP_B13:     PLT_RST_N */
+	/* GPP_B13:     SOC_PLTRST# */
 	PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1),
-	/* GPP_B14:     GPP_B14_DDSP_HPDB */
+	/* GPP_B14:     SOC_DP2_HPD# */
 	PAD_CFG_NF(GPP_B14, NONE, DEEP, NF2),
 	/* GPP_B16:     NC */
 	PAD_NC(GPP_B16, NONE),
-	/* GPP_B17:     SPI_TPM_INT_N */
+	/* GPP_B17:     SOC_SPI_TPM_INT# */
 	PAD_CFG_GPI_APIC_LOCK(GPP_B17, NONE, LEVEL, INVERT, LOCK_CONFIG),
-	/* GPP_B20:     SOC_KB_MATRIX */
-	PAD_CFG_GPO(GPP_B20, 1, PLTRST),
-	/* GPP_B21:     TCP_RETIMER_FORCE_PWR */
-	PAD_CFG_GPO(GPP_B21, 0, DEEP),
-	/* GPP_B22:     SOC_CAM_WP */
-	PAD_CFG_GPO(GPP_B22, 0, DEEP),
-	/* GPP_B24:     ESPI_ALERT0_EC_R_N */
+	/* GPP_B18:     NC */
+	PAD_NC(GPP_B18, NONE),
+	/* GPP_B19:     NC */
+	PAD_NC(GPP_B19, NONE),
+	/* GPP_B20:     NC */
+	PAD_NC(GPP_B20, NONE),
+	/* GPP_B21:     NC */
+	PAD_NC(GPP_B21, NONE),
+	/* GPP_B22:     NC */
+	PAD_NC(GPP_B22, NONE),
+	/* GPP_B23:     NC */
+	PAD_NC(GPP_B23, NONE),
+	/* GPP_B24:     NC */
 	PAD_NC(GPP_B24, NONE),
-	/* GPP_B25:     None */
+	/* GPP_B25:     NC */
 	PAD_NC(GPP_B25, NONE),
 
 	/* GPP_C */
-	/* GPP_C00:     SPD_SMB_CLK */
+	/* GPP_C00:     SPD_SOC_SMBCLK */
 	PAD_CFG_NF(GPP_C00, NONE, DEEP, NF1),
-	/* GPP_C01:     SPD_SMB_DATA */
+	/* GPP_C01:     SPD_SOC_SMBDATA */
 	PAD_CFG_NF(GPP_C01, NONE, DEEP, NF1),
 	/* GPP_C02:     NC */
 	PAD_NC(GPP_C02, NONE),
-	/* GPP_C03:     TCP_LAN_SML0_SCL_R */
-	PAD_CFG_NF(GPP_C03, NONE, DEEP, NF1),
-	/* GPP_C04:     TCP_LAN_SML0_SDA_R */
-	PAD_CFG_NF(GPP_C04, NONE, DEEP, NF1),
+	/* GPP_C03:     NC */
+	PAD_NC(GPP_C03, NONE),
+	/* GPP_C04:     NC */
+	PAD_NC(GPP_C04, NONE),
 	/* GPP_C05:     NC */
 	PAD_NC(GPP_C05, NONE),
 	/* GPP_C06:     NC */
 	PAD_NC(GPP_C06, NONE),
 	/* GPP_C07:     NC */
 	PAD_NC(GPP_C07, NONE),
-	/* GPP_C08:     PM_SLP_S0_N_GPP_CNTRL */
+	/* GPP_C08:     PM_SLP_S0#_GATE */
 	PAD_CFG_GPO(GPP_C08, 1, PLTRST),
-	/* GPP_C09:     NC */
-	PAD_NC(GPP_C09, NONE),
-	/* GPP_C10:     WIFI_RF_KILL_N */
+	/* GPP_C09:     CLKREQ_PCIE#0_WLAN */
+	PAD_CFG_NF(GPP_C09, NONE, DEEP, NF1),
+	/* GPP_C10:     SOC_WIFI_KILL# */
 	PAD_CFG_GPO(GPP_C10, 1, DEEP),
-	/* GPP_C11:     NC */
-	PAD_NC(GPP_C11, NONE),
-	/* GPP_C12:     CLKREQ3_X4_GEN4_M2_SSD_N */
+	/* GPP_C11:     CLKREQ_PCIE#2_LAN */
+	PAD_CFG_NF(GPP_C11, NONE, DEEP, NF1),
+	/* GPP_C12:     CLKREQ_PCIE#3_SSD */
 	PAD_CFG_NF(GPP_C12, NONE, DEEP, NF1),
 	/* GPP_C13:     NC */
 	PAD_NC(GPP_C13, NONE),
 	/* GPP_C14:     NC */
 	PAD_NC(GPP_C14, NONE),
-	/* GPP_C15:     FPS_RST_N */
+	/* GPP_C15:     SOC_FPS_RST# */
 	PAD_CFG_GPO_LOCK(GPP_C15, 1, LOCK_CONFIG),
-	/* GPP_C16:     MOD_TCSS1_LS_TX_DDC_SCL */
-	PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1),
-	/* GPP_C17:     MOD_TCSS1_LS_RX_DDC_SDA */
-	PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1),
-	/* GPP_C18:     MOD_TCSS2_LS_TX_DDC_SCL */
-	PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1),
-	/* GPP_C19:     MOD_TCSS2_LS_RX_DDC_SDA */
-	PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1),
-	/* GPP_C22:     DDPB_HDMI_CTRLCLK */
+	/* GPP_C16:     NC */
+	PAD_NC(GPP_C16, NONE),
+	/* GPP_C17:     NC */
+	PAD_NC(GPP_C17, NONE),
+	/* GPP_C18:     NC */
+	PAD_NC(GPP_C18, NONE),
+	/* GPP_C19:     NC */
+	PAD_NC(GPP_C19, NONE),
+	/* GPP_C22:     SOC_DP2_CTRL_CLK */
 	PAD_CFG_NF(GPP_C22, NONE, DEEP, NF2),
-	/* GPP_C23:     DDPB_HDMI_CTRLDATA */
+	/* GPP_C23:     SOC_DP2_CTRL_DATA */
 	PAD_CFG_NF(GPP_C23, NONE, DEEP, NF2),
 
 	/* GPP_D */
 	/* GPP_D01:     NC */
 	PAD_NC(GPP_D01, NONE),
-	/* GPP_D02:     SOC_WP_OD */
-	PAD_CFG_GPO(GPP_D02, 0, DEEP),
+	/* GPP_D02:     SOC_SPI_WP_H1 */
+	PAD_CFG_GPI(GPP_D02, NONE, DEEP),
 	/* GPP_D03:     NC */
 	PAD_NC(GPP_D03, NONE),
+	/* GPP_D05:     NC */
+	PAD_NC(GPP_D05, NONE),
+	/* GPP_D06:     NC */
+	PAD_NC(GPP_D06, NONE),
 	/* GPP_D07:     NC */
 	PAD_NC(GPP_D07, NONE),
 	/* GPP_D08:     NC */
@@ -147,151 +161,153 @@ static const struct pad_config gpio_table[] = {
 	PAD_NC(GPP_D10, NONE),
 	/* GPP_D11:     NC */
 	PAD_NC(GPP_D11, NONE),
-	/* GPP_D12:     NONE */
+	/* GPP_D12:     NC */
 	PAD_NC(GPP_D12, NONE),
 	/* GPP_D13:     NC */
 	PAD_NC(GPP_D13, NONE),
-	/* GPP_D16:     NC */
-	PAD_NC(GPP_D16, NONE),
-	/* GPP_D17:     NC */
-	PAD_NC(GPP_D17, NONE),
+	/* GPP_D16:     SOC_DMIC_CLK1 */
+	PAD_CFG_NF(GPP_D16, NONE, DEEP, NF3),
+	/* GPP_D17:     SOC_DMIC_DATA1 */
+	PAD_CFG_NF(GPP_D17, NONE, DEEP, NF3),
 	/* GPP_D19:     NC */
 	PAD_NC(GPP_D19, NONE),
-	/* GPP_D21:     GPP_D21_UFS_REFCLK_R */
-	PAD_CFG_NF(GPP_D21, NONE, DEEP, NF1),
+	/* GPP_D21:     NC */
+	PAD_NC(GPP_D21, NONE),
 
 	/* GPP_E */
-	/* GPP_E01:     PM_SLP_DRAM_N */
-	PAD_CFG_NF(GPP_E01, NONE, DEEP, NF2),
+	/* GPP_E01:     NC */
+	PAD_NC(GPP_E01, NONE),
 	/* GPP_E02:     VR_ALERT#_R */
-	PAD_NC(GPP_E02, NONE),
+	PAD_CFG_NF(GPP_E02, NONE, DEEP, NF2),
 	/* GPP_E03:     NC */
 	PAD_NC(GPP_E03, NONE),
 	/* GPP_E05:     NC */
 	PAD_NC(GPP_E05, NONE),
-	/* GPP_E06:     CAM_PRIVACY */
-	PAD_CFG_GPO(GPP_E06, 1, DEEP),
+	/* GPP_E06:     NC */
+	PAD_NC(GPP_E06, NONE),
 	/* GPP_E07:     NC */
 	PAD_NC(GPP_E07, NONE),
-	/* GPP_E08:     NC */
-	PAD_NC(GPP_E08, NONE),
-	/* GPP_E09:     USB_FP_CONN_1_CONN_2_OC0_N */
+	/* GPP_E08:     SOC_BT_KILL# */
+	PAD_CFG_GPO(GPP_E08, 1, DEEP),
+	/* GPP_E09:     SOC_USB_OC0# */
 	PAD_CFG_NF(GPP_E09, NONE, DEEP, NF1),
-	/* GPP_E10:     NONE */
+	/* GPP_E10:     NC */
 	PAD_NC(GPP_E10, NONE),
 	/* GPP_E11:     NC */
 	PAD_NC(GPP_E11, NONE),
-	/* GPP_E12:     THC_I2C0_SCL_TCH_PNL1 */
-	PAD_CFG_NF(GPP_E12, NONE, DEEP, NF3),
-	/* GPP_E13:     THC_I2C0_SDA_TCH_PNL1 */
-	PAD_CFG_NF(GPP_E13, NONE, DEEP, NF3),
+	/* GPP_E12:     SOC_THC_I2C_0_SCL */
+	PAD_NC(GPP_E12, NONE),
+	/* GPP_E13:     SOC_THC_I2C_0_SDA */
+	PAD_NC(GPP_E13, NONE),
 	/* GPP_E14:     NC */
 	PAD_NC(GPP_E14, NONE),
 	/* GPP_E15:     NC */
 	PAD_NC(GPP_E15, NONE),
-	/* GPP_E16:     THC0_SPI1_RST_N_TCH_PNL1 */
-	PAD_CFG_NF(GPP_E16, NONE, PLTRST, NF1),
+	/* GPP_E16:     SOC_TCHSCR_RST# */
+	PAD_NC(GPP_E16, NONE),
 	/* GPP_E17:     NC */
 	PAD_NC(GPP_E17, NONE),
-	/* GPP_E18:     THC0_SPI1_INT_N_TCH_PNL1 */
-	PAD_CFG_NF(GPP_E18, NONE, DEEP, NF3),
-	/* GPP_E19:     FPS_INT_N */
-	PAD_CFG_GPI_IRQ_WAKE(GPP_E19, NONE, PWROK, LEVEL, INVERT),
-	/* GPP_E20:     FPS_FW_UPDATE */
-	PAD_CFG_GPO_LOCK(GPP_E20, 0, LOCK_CONFIG),
-	/* GPP_E21:     I2C_PMC_PD_INT_N */
+	/* GPP_E18:     SOC_TCHSCR_INT# */
+	PAD_NC(GPP_E18, NONE),
+	/* GPP_E19:     SOC_WL_WAKE# */
+	PAD_NC(GPP_E19, NONE),
+	/* GPP_E20:     SOC_TP_INT# */
+	PAD_CFG_GPI_APIC_DRIVER(GPP_E20, NONE, PLTRST, EDGE_SINGLE, INVERT),
+	/* GPP_E21:     SOC_I2C_PD_INT# */
 	PAD_CFG_NF(GPP_E21, NONE, DEEP, NF1),
 	/* GPP_E22:     NC */
 	PAD_NC(GPP_E22, NONE),
 
 	/* GPP_F */
-	/* GPP_F00:     M.2_CNV_BRI_DT_BT_UART2_RTS_N */
+	/* GPP_F00:     CNV_BRI_CTX_DRX */
 	PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_F00, NONE, DEEP, NF1),
-	/* GPP_F01:     M.2_CNV_BRI_RSP_BT_UART2_RXD */
+	/* GPP_F01:     CNV_BRI_CRX_DTX */
 	PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_F01, NONE, DEEP, NF1),
-	/* GPP_F02:     M.2_CNV_RGI_DT_BT_UART2_TXD */
+	/* GPP_F02:     CNV_RGI_CTX_DRX */
 	PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_F02, NONE, DEEP, NF1),
-	/* GPP_F03:     M.2_CNV_RGI_RSP_BT_UART2_CTS_N */
+	/* GPP_F03:     CNV_RGI_CRX_DTX */
 	PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_F03, NONE, DEEP, NF1),
-	/* GPP_F04:     CNV_RF_RESET_R_N */
+	/* GPP_F04:     CNV_RF_RESET# */
 	PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_F04, NONE, DEEP, NF1),
-	/* GPP_F05:     CRF_CLKREQ_R */
+	/* GPP_F05:     CLKREQ_CNV# */
 	PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_F05, NONE, DEEP, NF3),
 	/* GPP_F06:     NC */
 	PAD_NC(GPP_F06, NONE),
 	/* GPP_F07:     NC */
 	PAD_NC(GPP_F07, NONE),
-	/* GPP_F08:     TCH_PNL1_PWR_EN */
-	PAD_CFG_GPO(GPP_F08, 1, PLTRST),
-	/* GPP_F09:     M2_UFS_RST_N */
-	PAD_CFG_GPO(GPP_F09, 1, DEEP),
-	/* GPP_F10:     SOC_EC_INT */
+	/* GPP_F08:     SOC_TCH_PWR_EN */
+	PAD_NC(GPP_F08, NONE),
+	/* GPP_F09:     NC */
+	PAD_NC(GPP_F09, NONE),
+	/* GPP_F10:     EC_SOC_INT_ODL */
 	PAD_CFG_GPI_APIC(GPP_F10, NONE, PLTRST, LEVEL, INVERT),
 	/* GPP_F11:     NC */
 	PAD_NC(GPP_F11, NONE),
-	/* GPP_F12:     THC_I2C1_SCL_TCH_PAD */
-	PAD_CFG_NF(GPP_F12, NONE, DEEP, NF8),
-	/* GPP_F13:     THC_I2C1_SDA_TCH_PAD */
-	PAD_CFG_NF(GPP_F13, NONE, DEEP, NF8),
-	/* GPP_F14:     GPP_F14_GPSI0A_MOSI */
-	PAD_CFG_NF(GPP_F14, NONE, DEEP, NF8),
-	/* GPP_F15:     GPP_F15_GSPI0A_MISO */
-	PAD_CFG_NF(GPP_F15, NONE, DEEP, NF8),
-	/* GPP_F16:     GPP_F16_GSPI0A_CLK */
-	PAD_CFG_NF(GPP_F16, NONE, DEEP, NF8),
+	/* GPP_F12:     NC */
+	PAD_NC(GPP_F12, NONE),
+	/* GPP_F13:     NC */
+	PAD_NC(GPP_F13, NONE),
+	/* GPP_F14:     NC */
+	PAD_NC(GPP_F14, NONE),
+	/* GPP_F15:     NC */
+	PAD_NC(GPP_F15, NONE),
+	/* GPP_F16:     NC */
+	PAD_NC(GPP_F16, NONE),
 	/* GPP_F17:     NC */
 	PAD_NC(GPP_F17, NONE),
-	/* GPP_F18:     GPP_F18_GSPI0A_CS0 */
-	PAD_CFG_NF(GPP_F18, NONE, DEEP, NF8),
+	/* GPP_F18:     NC */
+	PAD_NC(GPP_F18, NONE),
 	/* GPP_F19:     NC */
 	PAD_NC(GPP_F19, NONE),
 	/* GPP_F20:     CSE_EARLY_SW */
 	PAD_CFG_GPI(GPP_F20, NONE, DEEP),
-	/* GPP_F22:     THC1_SPI2_DSYNC */
-	PAD_CFG_NF(GPP_F22, NONE, DEEP, NF3),
+	/* GPP_F22:     NC */
+	PAD_NC(GPP_F22, NONE),
+	/* GPP_F23:     NC */
+	PAD_NC(GPP_F23, NONE),
 
 	/* GPP_H */
 	/* GPP_H00:     NC */
 	PAD_NC(GPP_H00, NONE),
-	/* GPP_H01:     M2_UFS_SLP_N */
-	PAD_CFG_GPO(GPP_H01, 1, DEEP),
-	/* GPP_H02:     DEBUG_TRACE_PNP */
-	PAD_CFG_GPO(GPP_H02, 1, PLTRST),
-	/* GPP_H03:     MIC MUTE */
-	PAD_CFG_NF(GPP_H03, NONE, DEEP, NF1),
+	/* GPP_H01:     NC */
+	PAD_NC(GPP_H01, NONE),
+	/* GPP_H02:     NC */
+	PAD_NC(GPP_H02, NONE),
+	/* GPP_H03:     NC */
+	PAD_NC(GPP_H03, NONE),
 	/* GPP_H04:     NC */
 	PAD_NC(GPP_H04, NONE),
 	/* GPP_H05:     NC */
 	PAD_NC(GPP_H05, NONE),
-	/* GPP_H06:     I2C3_SCL_AUDIO_HDR */
+	/* GPP_H06:     SOC_I2C_3_SDA_iPCM */
 	PAD_CFG_NF(GPP_H06, NONE, DEEP, NF1),
-	/* GPP_H07:     I2C3_SDA_AUDIO_HDR */
+	/* GPP_H07:     SOC_I2C_3_SCL_iPCM */
 	PAD_CFG_NF(GPP_H07, NONE, DEEP, NF1),
-	/* GPP_H08:     SOC_BIOS_LOG_TTK_UART_RX */
+	/* GPP_H08:     UART_0_CRXD_DTXD */
 	PAD_CFG_NF(GPP_H08, NONE, DEEP, NF1),
-	/* GPP_H09:     SOC_BIOS_LOG_TTK_UART_TX */
+	/* GPP_H09:     UART_0_CTXD_DRXD */
 	PAD_CFG_NF(GPP_H09, NONE, DEEP, NF1),
 	/* GPP_H10:     NC */
 	PAD_NC(GPP_H10, NONE),
 	/* GPP_H11:     NC */
 	PAD_NC(GPP_H11, NONE),
-	/* GPP_H13:     CPU_C10_GATE_N_R */
-	PAD_CFG_NF(GPP_H13, NONE, DEEP, NF1),
-	/* GPP_H14:     ISH_I3C1_SDA_SNSR_HDR */
+	/* GPP_H13:     NC */
+	PAD_NC(GPP_H13, NONE),
+	/* GPP_H14:     NC */
 	PAD_NC(GPP_H14, NONE),
-	/* GPP_H15:     ISH_I3C1_SCL_SNSR_HDR */
+	/* GPP_H15:     NC */
 	PAD_NC(GPP_H15, NONE),
-	/* GPP_H17:     MIC MUTE LED */
-	PAD_CFG_NF(GPP_H17, NONE, DEEP, NF1),
-	/* GPP_H18:     GEN4_SSD_PWREN */
-	PAD_CFG_GPO(GPP_H18, 1, DEEP),
-	/* GPP_H19:     I3C0_SDA_HDR */
-	PAD_CFG_NF(GPP_H19, NONE, DEEP, NF2),
-	/* GPP_H20:     I3C0_SCL_HDR */
-	PAD_CFG_NF(GPP_H20, NONE, DEEP, NF2),
-	/* GPP_H21:     I2C1_SDA_TTK_CHROME */
+	/* GPP_H17:     NC */
+	PAD_NC(GPP_H17, NONE),
+	/* GPP_H18:     NC */
+	PAD_NC(GPP_H18, NONE),
+	/* GPP_H19:     SOC_I2C_0_SDA */
+	PAD_CFG_NF(GPP_H19, NONE, DEEP, NF1),
+	/* GPP_H20:     SOC_I2C_0_SCL */
+	PAD_CFG_NF(GPP_H20, NONE, DEEP, NF1),
+	/* GPP_H21:     SOC_I2C_1_SDA */
 	PAD_CFG_NF(GPP_H21, NONE, DEEP, NF1),
-	/* GPP_H22:     I2C1_SCL_TTK_CHROME */
+	/* GPP_H22:     SOC_I2C_1_SCL */
 	PAD_CFG_NF(GPP_H22, NONE, DEEP, NF1),
 	/* GPP_H23:     NC */
 	PAD_NC(GPP_H23, NONE),
@@ -299,65 +315,82 @@ static const struct pad_config gpio_table[] = {
 	PAD_NC(GPP_H24, NONE),
 
 	/* GPP_V */
-	/* GPP_V00:     PM_BATLOW_N */
+	/* GPP_V00:     BATLOW# */
 	PAD_CFG_NF(GPP_V00, NONE, DEEP, NF1),
 	/* GPP_V01:     BC_ACOK_MCP */
 	PAD_CFG_NF(GPP_V01, NONE, DEEP, NF1),
-	/* GPP_V02:     LANWAKE_N_R */
+	/* GPP_V02:     WAKE# */
 	PAD_CFG_NF(GPP_V02, NONE, DEEP, NF1),
-	/* GPP_V03:     PWRBTN_MCP_N */
+	/* GPP_V03:     EC_PWRBTN#_OUT_R */
 	PAD_CFG_NF(GPP_V03, UP_20K, DEEP, NF1),
-	/* GPP_V04:     PM_SLP_S3_N */
+	/* GPP_V04:     PM_SLP_S3# */
 	PAD_CFG_NF(GPP_V04, NONE, DEEP, NF1),
-	/* GPP_V05:     PM_SLP_S4_N */
+	/* GPP_V05:     PM_SLP_S4# */
 	PAD_CFG_NF(GPP_V05, NONE, DEEP, NF1),
-	/* GPP_V06:     PM_SLP_A_N */
+	/* GPP_V06:     PM_SLP_A# */
 	PAD_CFG_NF(GPP_V06, NONE, DEEP, NF1),
-	/* GPP_V07:     M.2_BTWIFI_SUS_CLK_LS */
+	/* GPP_V07:     WLAN_SUSCLK */
 	PAD_CFG_NF(GPP_V07, NONE, DEEP, NF1),
-	/* GPP_V08:     SLP_WLAN_N */
-	PAD_CFG_NF(GPP_V08, NONE, DEEP, NF1),
-	/* GPP_V09:     PM_SLP_S5_N */
+	/* GPP_V08:     NC */
+	PAD_NC(GPP_V08, NONE),
+	/* GPP_V09:     PM_SLP_S5# */
 	PAD_CFG_NF(GPP_V09, NONE, DEEP, NF1),
-	/* GPP_V10:     NC */
-	PAD_NC(GPP_V10, NONE),
-	/* GPP_V11:     PM_SLP_LAN_N */
+	/* GPP_V10:     LAN_WAKE# */
+	PAD_CFG_GPI_IRQ_WAKE(GPP_V10, NONE, PWROK, LEVEL, INVERT),
+	/* GPP_V11:     PM_SLP_LAN# */
 	PAD_CFG_NF(GPP_V11, NONE, DEEP, NF1),
-	/* GPP_V12:     WAKE_N */
-	PAD_CFG_NF(GPP_V12, NONE, DEEP, NF1),
+	/* GPP_V12:     NC */
+	PAD_NC(GPP_V12, NONE),
 	/* GPP_V13:     GPP_V13_CATERR_N */
 	PAD_CFG_NF(GPP_V13, NONE, DEEP, NF1),
 	/* GPP_V14:     GPP_V14_FORCEPR_N */
 	PAD_CFG_NF(GPP_V14, NONE, DEEP, NF1),
 	/* GPP_V15:     GPP_V15_THERMTRIP_N */
 	PAD_CFG_NF(GPP_V15, NONE, DEEP, NF1),
-	/* GPP_V16:     GPP_V16_VCCST_EN */
+	/* GPP_V16:     SOC_VCCST_EN */
 	PAD_CFG_NF(GPP_V16, NONE, DEEP, NF1),
+
+	/* GPP_S00:     SNDW_3_SCL */
+	PAD_CFG_NF(GPP_S00, NONE, DEEP, NF1),
+	/* GPP_S01:     SNDW_3_SDA0 */
+	PAD_CFG_NF(GPP_S01, NONE, DEEP, NF1),
+	/* GPP_S02:     SNDW_3_SDA1 */
+	PAD_CFG_NF(GPP_S02, NONE, DEEP, NF1),
+	/* GPP_S03:     SNDW_3_SDA2 */
+	PAD_CFG_NF(GPP_S03, NONE, DEEP, NF1),
+	/* GPP_S04:     NC */
+	PAD_NC(GPP_S04, NONE),
+	/* GPP_S05:     NC */
+	PAD_NC(GPP_S05, NONE),
+	/* GPP_S06:     NC */
+	PAD_NC(GPP_S06, NONE),
+	/* GPP_S07:     NC */
+	PAD_NC(GPP_S07, NONE),
 };
 
 /* Early pad configuration in bootblock */
 static const struct pad_config early_gpio_table[] = {
-	/* GPP_B17:     SPI_TPM_INT_N */
-	PAD_CFG_GPI_APIC(GPP_B17, NONE, DEEP, LEVEL, INVERT),
-	/* GPP_H06: I2C3_SDA_PSS */
+	/* GPP_B17:     SOC_SPI_TPM_INT# */
+	PAD_CFG_GPI_APIC_LOCK(GPP_B17, NONE, LEVEL, INVERT, LOCK_CONFIG),
+	/* GPP_H06: SOC_I2C_3_SDA_iPCM */
 	PAD_CFG_NF(GPP_H06, NONE, DEEP, NF1),
-	/* GPP_H07: I2C3_SCL_PSS */
+	/* GPP_H07: SOC_I2C_3_SCL_iPCM */
 	PAD_CFG_NF(GPP_H07, NONE, DEEP, NF1),
-	/* GPP_H08:     SOC_BIOS_LOG_TTK_UART_RX */
+	/* GPP_H08:     UART_0_CRXD_DTXD */
 	PAD_CFG_NF(GPP_H08, NONE, DEEP, NF1),
-	/* GPP_H09:     SOC_BIOS_LOG_TTK_UART_TX */
+	/* GPP_H09:     UART_0_CTXD_DRXD */
 	PAD_CFG_NF(GPP_H09, NONE, DEEP, NF1),
-	/* GPP_H21:     I2C1_SDA_TTK_CHROME */
+	/* GPP_H21:     SOC_I2C_1_SDA */
 	PAD_CFG_NF(GPP_H21, NONE, DEEP, NF1),
-	/* GPP_H22:     I2C1_SCL_TTK_CHROME */
+	/* GPP_H22:     SOC_I2C_1_SCL */
 	PAD_CFG_NF(GPP_H22, NONE, DEEP, NF1),
 };
 
 /* Pad configuration in romstage */
 static const struct pad_config romstage_gpio_table[] = {
-	/* GPP_C00:     SPD_SMB_CLK */
+	/* GPP_C00:     SPD_SOC_SMBCLK */
 	PAD_CFG_NF(GPP_C00, NONE, DEEP, NF1),
-	/* GPP_C01:     SPD_SMB_DATA */
+	/* GPP_C01:     SPD_SOC_SMBDATA */
 	PAD_CFG_NF(GPP_C01, NONE, DEEP, NF1),
 	/* GPP_C15:     FPS_RST_N */
 	PAD_CFG_GPO(GPP_C15, 0, PLTRST),

From 7b11254d584a8fbec5b9c0b924d326bf21bc1ee0 Mon Sep 17 00:00:00 2001
From: Ian Feng <ian_feng@compal.corp-partner.google.com>
Date: Mon, 17 Nov 2025 15:49:38 +0800
Subject: [PATCH 2520/3886] mb/google/ocelot/var/kodkod: Add overridetree

Add override devicetree based on schematic_20251112.

BUG=b:452542491
TEST=emerge-ocelot coreboot

Change-Id: I3a0e914ac463258bc475ff94ec9ad574707cad4a
Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90069
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Pranava Y N <pranavayn@google.com>
---
 src/mainboard/google/ocelot/Kconfig           |   3 +
 .../ocelot/variants/kodkod/overridetree.cb    | 248 ++++++++++++++++++
 2 files changed, 251 insertions(+)

diff --git a/src/mainboard/google/ocelot/Kconfig b/src/mainboard/google/ocelot/Kconfig
index f979addcbd..8b3c377289 100644
--- a/src/mainboard/google/ocelot/Kconfig
+++ b/src/mainboard/google/ocelot/Kconfig
@@ -63,6 +63,9 @@ config BOARD_GOOGLE_MODEL_KODKOD
 	select FSP_UGOP_EARLY_SIGN_OF_LIFE
 	select EC_GOOGLE_CHROMEEC_RTK
 	select EC_GOOGLE_CHROMEEC_LPC_GENERIC_MEMORY_RANGE
+	select RT8168_GEN_ACPI_POWER_RESOURCE
+	select RT8168_GET_MAC_FROM_VPD
+	select RT8168_SET_LED_MODE
 	select SPD_CACHE_ENABLE
 	select SPD_CACHE_IN_FMAP
 
diff --git a/src/mainboard/google/ocelot/variants/kodkod/overridetree.cb b/src/mainboard/google/ocelot/variants/kodkod/overridetree.cb
index bfd637ae50..ceac680dcd 100644
--- a/src/mainboard/google/ocelot/variants/kodkod/overridetree.cb
+++ b/src/mainboard/google/ocelot/variants/kodkod/overridetree.cb
@@ -1,5 +1,253 @@
 chip soc/intel/pantherlake
 
+	register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Type C port - various configurations - TCP0
+	register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Type C port - various configurations - TCP1
+	register "usb2_ports[2]" = "USB2_PORT_MID(OC0)" # USB3.2 Gen2x1 Type-A Port
+	register "usb2_ports[3]" = "USB2_PORT_MID(OC0)" # USB3.2 Gen2x1 Type-A Port
+	register "usb2_ports[4]" = "USB2_PORT_MID(OC_SKIP)" # Camera
+	register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)" # Micro SD card
+	register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" # Finger Print
+
+	register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)" # USB 3.2 Gen2 x1 Type-A Con - # 1
+	register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC0)" # USB 3.2 Gen2 x1 Type-A Con - # 2
+
+	register "tcss_ports[0]" = "TCSS_PORT_DEFAULT(OC_SKIP)"
+	register "tcss_ports[1]" = "TCSS_PORT_DEFAULT(OC_SKIP)"
+
+	register "tcss_cap_policy[0]" = "TCSS_TYPE_C_PORT_FULL_FUN"
+	register "tcss_cap_policy[1]" = "TCSS_TYPE_C_PORT_FULL_FUN"
+
+	#gpe configuration
+	register "pmc_gpe0_dw0" = "GPP_V"
+	register "pmc_gpe0_dw1" = "GPP_B"
+	register "pmc_gpe0_dw2" = "GPP_E"
+
+	# Enable EDP in PortA & HDMI in Port B
+	register "ddi_port_A_config" = "1"
+	register "ddi_port_B_config" = "1"
+	register "ddi_ports_config" = "{
+		[DDI_PORT_A] = DDI_ENABLE_HPD,
+		[DDI_PORT_B] = DDI_ENABLE_HPD | DDI_ENABLE_DDC,
+	}"
+
+	register "serial_io_i2c_mode" = "{
+		[PchSerialIoIndexI2C0]  = PchSerialIoPci,
+		[PchSerialIoIndexI2C1]  = PchSerialIoPci,
+		[PchSerialIoIndexI2C2]  = PchSerialIoDisabled,
+		[PchSerialIoIndexI2C3]  = PchSerialIoDisabled,
+		[PchSerialIoIndexI2C4]  = PchSerialIoDisabled,
+		[PchSerialIoIndexI2C5]  = PchSerialIoDisabled,
+	}"
+
+	register "serial_io_gspi_mode" = "{
+		[PchSerialIoIndexGSPI0] = PchSerialIoDisabled,
+		[PchSerialIoIndexGSPI1] = PchSerialIoDisabled,
+		[PchSerialIoIndexGSPI0A] = PchSerialIoDisabled,
+	}"
+
+	# Intel Common SoC Config
+	#+-------------------+---------------------------+
+	#| Field             |  Value                    |
+	#+-------------------+---------------------------+
+	#| I2C0              | Touchpad                   |
+	#| I2C1              | TPM(TI50) Early init is   |
+	#|                   | required to set up a BAR  |
+	#|                   | for TPM communication     |
+	#+-------------------+---------------------------+
+	register "common_soc_config" = "{
+		/* Render OEM footer logo 100px above from the edge */
+		.logo_bottom_margin = 100,
+		.chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT,
+		.i2c[0] = {
+			.speed = I2C_SPEED_FAST,
+		},
+		.i2c[1] = {
+                        .speed = I2C_SPEED_FAST,
+                        .early_init = 1,
+                },
+	}"
+
 	device domain 0 on
+		device ref igpu on
+			chip drivers/gfx/generic
+				register "device_count" = "4"
+				# DDIA for eDP
+				register "device[0].name" = ""LCD0""
+				register "device[0].type" = "panel"
+				# DDIB for HDMI
+				# If HDMI is not enumerated in the kernel, then no GFX device should be added for DDIB
+				register "device[1].name" = ""DD01""
+				# TCP0 (DP-1) for port C0
+				register "device[2].name" = ""DD02""
+				register "device[2].use_pld" = "true"
+				register "device[2].pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(1, 1))"
+				# TCP1 (DP-2) for port C1
+				register "device[3].name" = ""DD03""
+				register "device[3].use_pld" = "true"
+				register "device[3].pld" = "ACPI_PLD_TYPE_C(LEFT, RIGHT, ACPI_PLD_GROUP(2, 1))"
+				device generic 0 on end
+			end
+		end
+
+		device ref iaa off end
+
+		device ref tcss_xhci on
+			chip drivers/usb/acpi
+				device ref tcss_root_hub on
+					chip drivers/usb/acpi
+						register "desc" = ""USB3 Type-C Port C0""
+						register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
+						register "group" = "ACPI_PLD_GROUP(4, 2)"
+						device ref tcss_usb3_port0 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB3 Type-C Port C1""
+						register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
+						register "group" = "ACPI_PLD_GROUP(3, 2)"
+						device ref tcss_usb3_port1 on end
+					end
+				end
+			end
+		end
+
+		device ref xhci on
+			chip drivers/usb/acpi
+				device ref xhci_root_hub on
+					chip drivers/usb/acpi
+						register "desc" = ""USB2 Type-C Port C0""
+						register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
+						register "group" = "ACPI_PLD_GROUP(1, 1)"
+						device ref usb2_port1 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB2 Type-C Port C1""
+						register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
+						register "group" = "ACPI_PLD_GROUP(2, 1)"
+						device ref usb2_port2 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB2 Type-A Port 1""
+						register "type" = "UPC_TYPE_A"
+						register "group" = "ACPI_PLD_GROUP(3, 1)"
+						device ref usb2_port3 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB2 Type-A Port 2""
+						register "type" = "UPC_TYPE_A"
+						register "group" = "ACPI_PLD_GROUP(4, 1)"
+						device ref usb2_port4 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB2 Camera""
+						register "type" = "UPC_TYPE_INTERNAL"
+						register "group" = "ACPI_PLD_GROUP(5, 1)"
+						device ref usb2_port5 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB2 Micro SD card""
+						register "type" = "UPC_TYPE_INTERNAL"
+						register "group" = "ACPI_PLD_GROUP(6, 1)"
+						device ref usb2_port6 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB2 FPMCU""
+						register "type" = "UPC_TYPE_INTERNAL"
+						register "has_power_resource" = "true"
+						device ref usb2_port7 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB3 Type-A Port 1""
+						register "type" = "UPC_TYPE_USB3_A"
+						register "group" = "ACPI_PLD_GROUP(1, 2)"
+						device ref usb3_port1 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB3 Type-A Port 2""
+						register "type" = "UPC_TYPE_USB3_A"
+						register "group" = "ACPI_PLD_GROUP(2, 2)"
+						device ref usb3_port2 on end
+					end
+				end
+			end
+		end
+
+		device ref pcie_rp1 on
+			register "pcie_rp[PCIE_RP(1)]" = "{
+				.clk_src = 3,
+				.clk_req = 3,
+				.flags = PCIE_RP_CLK_REQ_DETECT | PCIE_RP_LTR | PCIE_RP_AER,
+			}"
+			chip soc/intel/common/block/pcie/rtd3
+				register "is_storage" = "true"
+				register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A08)"
+				register "srcclk_pin" = "3"
+				device generic 0 on end
+			end
+		end # Gen4 M.2 SSD
+		device ref pcie_rp6 on
+			register "pcie_rp[PCIE_RP(6)]" = "{
+				.clk_src = 2,
+				.clk_req = 2,
+				.flags = PCIE_RP_LTR | PCIE_RP_AER,
+			}"
+			chip drivers/net
+				register "customized_leds" = "0x05af"
+				register "wake" = "GPE0_DW0_10"	# GPP_V10
+				register "device_index" = "0"
+				register "enable_aspm_l1_2" = "1"
+				register "add_acpi_dma_property" = "true"
+				device pci 00.0 on end
+			end
+		end # LAN RTL8111H
+
+		device ref cnvi_wifi on
+			chip drivers/wifi/generic
+				register "wake" = "GPE0_PME_B0"
+				register "add_acpi_dma_property" = "true"
+				register "enable_cnvi_ddr_rfim" = "true"
+				use cnvi_bluetooth as bluetooth_companion
+				device generic 0 on end
+			end
+		end # CNVi
+
+		device ref cnvi_bluetooth on
+		end
+
+		device ref i2c0 on
+			chip drivers/i2c/generic
+				register "hid" = ""ELAN0000""
+				register "desc" = ""ELAN Touchpad""
+				register "irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_E20_IRQ)"
+				register "wake" = "GPE0_DW2_20"
+				register "detect" = "1"
+				device i2c 15 on end
+			end
+		end
+
+		device ref i2c1 on
+			chip drivers/i2c/tpm
+				register "hid" = ""GOOG0005""
+				register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_B17_IRQ)"
+				device i2c 50 on end
+			end
+		end
+
+		device ref smbus on end
+
+		device ref hda on
+			chip drivers/intel/soundwire
+				device generic 0 on
+					chip drivers/soundwire/alc711
+						register "desc" = ""Headset Codec""
+						register "alc711_address.version" = "SOUNDWIRE_VERSION_1_2"
+						register "alc711_address.class" = "MIPI_CLASS_SDCA"
+						register "alc711_address.part_id" = "MIPI_DEV_ID_REALTEK_ALC721"
+						register "disable_clkstop_sm_support" = "true"
+						# SoundWire Link 3 ID 0
+						device generic 3.0 on end
+					end
+				end
+			end
+		end
 	end
 end

From 0ef4bd807cef488d5be236643af9ca07bfedb1d2 Mon Sep 17 00:00:00 2001
From: Ian Feng <ian_feng@compal.corp-partner.google.com>
Date: Mon, 17 Nov 2025 15:51:28 +0800
Subject: [PATCH 2521/3886] mb/google/ocelot/var/ocelot: Update DDR5 memory
 configs

This change updates memory configuration for DDR5.
1. Set SaGv frequencies
2. Configure gear settings
3. Map Channel/PHY clock

Bug=b:452542491
TEST=Build kodkod image.

Change-Id: I49939c8bde06b4a3148b48307b4ccbebf8ba560d
Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90070
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Pranava Y N <pranavayn@google.com>
---
 .../google/ocelot/variants/kodkod/Makefile.mk |  2 +
 .../google/ocelot/variants/kodkod/memory.c    |  4 ++
 .../google/ocelot/variants/kodkod/variant.c   | 41 +++++++++++++++++++
 3 files changed, 47 insertions(+)
 create mode 100644 src/mainboard/google/ocelot/variants/kodkod/variant.c

diff --git a/src/mainboard/google/ocelot/variants/kodkod/Makefile.mk b/src/mainboard/google/ocelot/variants/kodkod/Makefile.mk
index 4c33dad4db..1e3790a9f1 100644
--- a/src/mainboard/google/ocelot/variants/kodkod/Makefile.mk
+++ b/src/mainboard/google/ocelot/variants/kodkod/Makefile.mk
@@ -3,4 +3,6 @@
 bootblock-y += gpio.c
 romstage-y += gpio.c
 romstage-y += memory.c
+romstage-y += variant.c
 ramstage-y += gpio.c
+ramstage-y += variant.c
diff --git a/src/mainboard/google/ocelot/variants/kodkod/memory.c b/src/mainboard/google/ocelot/variants/kodkod/memory.c
index f9e6fedfe4..06a9858c4b 100644
--- a/src/mainboard/google/ocelot/variants/kodkod/memory.c
+++ b/src/mainboard/google/ocelot/variants/kodkod/memory.c
@@ -17,6 +17,10 @@ static const struct mb_cfg ddr5_mem_config = {
 	.ddr_config = {
 		.dq_pins_interleaved = false,
 	},
+
+	.rcomp = {
+		.resistor = 100,
+	},
 };
 const struct mb_cfg *variant_memory_params(void)
 {
diff --git a/src/mainboard/google/ocelot/variants/kodkod/variant.c b/src/mainboard/google/ocelot/variants/kodkod/variant.c
new file mode 100644
index 0000000000..c667edcccf
--- /dev/null
+++ b/src/mainboard/google/ocelot/variants/kodkod/variant.c
@@ -0,0 +1,41 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <baseboard/variants.h>
+#include <fsp/api.h>
+
+void variant_update_soc_memory_init_params(FSPM_UPD *memupd)
+{
+	FSP_M_CONFIG *m_cfg = &memupd->FspmConfig;
+
+	/* Override FSP-M SaGv frequency and gear for DDR5 boards */
+	m_cfg->SaGvFreq[0] = 3200;
+	m_cfg->SaGvGear[0] = GEAR_4;
+
+	m_cfg->SaGvFreq[1] = 4800;
+	m_cfg->SaGvGear[1] = GEAR_4;
+
+	m_cfg->SaGvFreq[2] = 5600;
+	m_cfg->SaGvGear[2] = GEAR_4;
+
+	m_cfg->SaGvFreq[3] = 6400;
+	m_cfg->SaGvGear[3] = GEAR_4;
+
+	/*
+	* Override FSP-M ChannelToCkdQckMapping to map memory channels
+	* to Clock Driver (CKD) and Query Clock (QCK) signals.
+	*/
+
+	const uint8_t channel_to_ckd_qck[] = { 1, 0, 0, 0,
+		0, 0, 0, 0 };
+	memcpy(m_cfg->ChannelToCkdQckMapping, channel_to_ckd_qck
+		, sizeof(channel_to_ckd_qck));
+
+	/*
+	* Override FSP-M PhyClockToCkdDimm to map PHY clocks
+	* to Clock Driver DIMM connections.
+	*/
+	const uint8_t phy_clock_to_ckd_dimm[] = { 4, 0, 4, 0,
+		0, 0, 0, 0 };
+	memcpy(m_cfg->PhyClockToCkdDimm, phy_clock_to_ckd_dimm,
+		sizeof(phy_clock_to_ckd_dimm));
+}

From 8a83b8625483403f3ca754e2f8bc82bb402bfbdc Mon Sep 17 00:00:00 2001
From: "Johann C. Rode" <jcrode@gmx.net>
Date: Thu, 13 Nov 2025 16:32:50 -0800
Subject: [PATCH 2522/3886] spd/ddr4: add parts

This patch adds parts used on Lenovo Thinkpads:

Micron MT40A512M16HA-083E:A
Micron MT40A1G16HBA-083E:A
Samsung K4A8G165WB-BCPB
Micron MT40A512M16JY-083E:B
Micron MT40A1G16WBU-083E:B
Samsung K4A8G165WC-BCRC
Samsung K4AAG165WB-MCRC
SKHynix H5AN8G6NAFR-UHC
SKHynix H5AN8G6NAMR-UHC
Micron MT40A512M6LY-075:E
Micron MT40A256M16GE-083E
Samsung K4A4G165WE-BCRC

The SPD data (timing, configuration, etc.) has been extracted from datasheets and laptop schematics. When there has been conflicting data between these data sources, slower (safer) values were picked.

Change-Id: Ied92619130feaa160d01f75bc38230ab6a024ace
Signed-off-by: Johann C. Rode <jcrode@gmx.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90032
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 spd/ddr4/memory_parts.json                    | 143 ++++++++++++++++++
 spd/ddr4/platforms_manifest.generated.txt     |   2 +-
 .../set-0/parts_spd_manifest.generated.txt    |  15 +-
 spd/ddr4/set-0/spd-10.hex                     |  32 ++++
 spd/ddr4/set-0/spd-11.hex                     |  32 ++++
 spd/ddr4/set-0/spd-12.hex                     |  32 ++++
 spd/ddr4/set-0/spd-13.hex                     |  32 ++++
 spd/ddr4/set-0/spd-14.hex                     |  32 ++++
 spd/ddr4/set-0/spd-15.hex                     |  32 ++++
 9 files changed, 350 insertions(+), 2 deletions(-)
 create mode 100644 spd/ddr4/set-0/spd-10.hex
 create mode 100644 spd/ddr4/set-0/spd-11.hex
 create mode 100644 spd/ddr4/set-0/spd-12.hex
 create mode 100644 spd/ddr4/set-0/spd-13.hex
 create mode 100644 spd/ddr4/set-0/spd-14.hex
 create mode 100644 spd/ddr4/set-0/spd-15.hex

diff --git a/spd/ddr4/memory_parts.json b/spd/ddr4/memory_parts.json
index aac5cc806b..7684401cdf 100644
--- a/spd/ddr4/memory_parts.json
+++ b/spd/ddr4/memory_parts.json
@@ -261,6 +261,149 @@
                 "packageBusWidth": 16,
                 "ranksPerPackage": 1
             }
+        },
+        {
+            "name": "MT40A512M16HA-083E:A",
+            "attribs": {
+                "speedMTps": 2133,
+                "CL_nRCD_nRP": 15,
+                "capacityPerDieGb": 8,
+                "diesPerPackage": 1,
+                "packageBusWidth": 16,
+                "ranksPerPackage": 1
+            }
+        },
+        {
+            "name": "MT40A1G16HBA-083E:A",
+            "attribs": {
+                "speedMTps": 2133,
+                "CL_nRCD_nRP": 15,
+                "capacityPerDieGb": 8,
+                "diesPerPackage": 2,
+                "packageBusWidth": 8,
+                "ranksPerPackage": 1
+            }
+        },
+        {
+            "name": "K4A8G165WB-BCPB",
+            "attribs": {
+                "speedMTps": 2133,
+                "CL_nRCD_nRP": 15,
+                "capacityPerDieGb": 8,
+                "diesPerPackage": 1,
+                "packageBusWidth": 16,
+                "ranksPerPackage": 1
+            }
+        },
+        {
+            "name": "MT40A512M16JY-083E:B",
+            "attribs": {
+                "speedMTps": 2400,
+                "CL_nRCD_nRP": 17,
+                "capacityPerDieGb": 8,
+                "diesPerPackage": 1,
+                "packageBusWidth": 16,
+                "ranksPerPackage": 1
+            }
+        },
+        {
+            "name": "MT40A1G16WBU-083E:B",
+            "attribs": {
+                "speedMTps": 2400,
+                "CL_nRCD_nRP": 17,
+                "capacityPerDieGb": 8,
+                "diesPerPackage": 2,
+                "packageBusWidth": 8,
+                "ranksPerPackage": 1
+            }
+        },
+        {
+            "name": "K4A8G165WB-BCRC",
+            "attribs": {
+                "speedMTps": 2400,
+                "CL_nRCD_nRP": 17,
+                "capacityPerDieGb": 8,
+                "diesPerPackage": 1,
+                "packageBusWidth": 16,
+                "ranksPerPackage": 1
+            }
+        },
+        {
+            "name": "K4A8G165WC-BCRC",
+            "attribs": {
+                "speedMTps": 2400,
+                "CL_nRCD_nRP": 17,
+                "capacityPerDieGb": 8,
+                "diesPerPackage": 1,
+                "packageBusWidth": 16,
+                "ranksPerPackage": 1
+            }
+        },
+        {
+            "name": "K4AAG165WB-MCRC",
+            "attribs": {
+                "speedMTps": 2400,
+                "CL_nRCD_nRP": 17,
+                "capacityPerDieGb": 8,
+                "diesPerPackage": 2,
+                "packageBusWidth": 8,
+                "ranksPerPackage": 1
+            }
+        },
+        {
+            "name": "H5AN8G6NAFR-UHC",
+            "attribs": {
+                "speedMTps": 2400,
+                "CL_nRCD_nRP": 17,
+                "capacityPerDieGb": 8,
+                "diesPerPackage": 1,
+                "packageBusWidth": 16,
+                "ranksPerPackage": 1
+            }
+        },
+        {
+            "name": "H5AN8G6NAMR-UHC",
+            "attribs": {
+                "speedMTps": 2400,
+                "CL_nRCD_nRP": 17,
+                "capacityPerDieGb": 8,
+                "diesPerPackage": 2,
+                "packageBusWidth": 8,
+                "ranksPerPackage": 1
+            }
+        },
+        {
+            "name": "MT40A512M16LY-075:E",
+            "attribs": {
+                "speedMTps": 2400,
+                "CL_nRCD_nRP": 17,
+                "capacityPerDieGb": 8,
+                "diesPerPackage": 1,
+                "packageBusWidth": 16,
+                "ranksPerPackage": 1
+            }
+        },
+        {
+            "name": "MT40A256M16GE-083E:B",
+            "attribs": {
+                "speedMTps": 2133,
+                "CL_nRCD_nRP": 15,
+                "capacityPerDieGb": 4,
+                "diesPerPackage": 1,
+                "packageBusWidth": 16,
+                "ranksPerPackage": 1
+            }
+        },
+        {
+            "name": "K4A4G165WE-BCRC",
+            "attribs": {
+                "speedMTps": 2400,
+                "CL_nRCD_nRP": 17,
+                "capacityPerDieGb": 4,
+                "diesPerPackage": 1,
+                "packageBusWidth": 16,
+                "ranksPerPackage": 1
+            }
         }
     ]
 }
diff --git a/spd/ddr4/platforms_manifest.generated.txt b/spd/ddr4/platforms_manifest.generated.txt
index 594f6c82f9..eedc5062c3 100644
--- a/spd/ddr4/platforms_manifest.generated.txt
+++ b/spd/ddr4/platforms_manifest.generated.txt
@@ -1,5 +1,5 @@
 # Generated by:
-# ../../util/spd_tools/bin/spd_gen memory_parts.json ddr4
+# util/spd_tools/bin/spd_gen spd/ddr4/memory_parts.json ddr4
 
 TGL,set-0
 PCO,set-0
diff --git a/spd/ddr4/set-0/parts_spd_manifest.generated.txt b/spd/ddr4/set-0/parts_spd_manifest.generated.txt
index 6eb5e25306..440d4c1dab 100644
--- a/spd/ddr4/set-0/parts_spd_manifest.generated.txt
+++ b/spd/ddr4/set-0/parts_spd_manifest.generated.txt
@@ -1,5 +1,5 @@
 # Generated by:
-# ../../util/spd_tools/bin/spd_gen memory_parts.json ddr4
+# util/spd_tools/bin/spd_gen spd/ddr4/memory_parts.json ddr4
 
 H5AN8G6NDJR-XNC,spd-1.hex
 MT40A512M16TB-062E:J,spd-1.hex
@@ -22,3 +22,16 @@ K4AAG165WB-BCWE,spd-9.hex
 MT40A1G16RC-062E:B,spd-9.hex
 MT40A512M16TB-062E:R,spd-1.hex
 4JQA-0622AD,spd-1.hex
+MT40A512M16HA-083E:A,spd-10.hex
+MT40A1G16HBA-083E:A,spd-11.hex
+K4A8G165WB-BCPB,spd-10.hex
+MT40A512M16JY-083E:B,spd-12.hex
+MT40A1G16WBU-083E:B,spd-13.hex
+K4A8G165WB-BCRC,spd-12.hex
+K4A8G165WC-BCRC,spd-12.hex
+K4AAG165WB-MCRC,spd-13.hex
+H5AN8G6NAFR-UHC,spd-12.hex
+H5AN8G6NAMR-UHC,spd-13.hex
+MT40A512M16LY-075:E,spd-12.hex
+MT40A256M16GE-083E:B,spd-14.hex
+K4A4G165WE-BCRC,spd-15.hex
diff --git a/spd/ddr4/set-0/spd-10.hex b/spd/ddr4/set-0/spd-10.hex
new file mode 100644
index 0000000000..dd497e639a
--- /dev/null
+++ b/spd/ddr4/set-0/spd-10.hex
@@ -0,0 +1,32 @@
+23 11 0C 03 45 21 00 08 00 00 00 00 02 03 00 00
+00 00 08 09 F4 03 00 00 71 71 71 11 08 79 F0 0A
+20 08 00 05 00 F0 2B 34 2B 00 78 00 14 3C 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 EC 9C B5 C3 C3 C3 C3 CA C1 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 20 20 20 20 20 20 20
+20 20 20 20 20 20 20 20 20 20 20 20 20 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
diff --git a/spd/ddr4/set-0/spd-11.hex b/spd/ddr4/set-0/spd-11.hex
new file mode 100644
index 0000000000..a29187c06a
--- /dev/null
+++ b/spd/ddr4/set-0/spd-11.hex
@@ -0,0 +1,32 @@
+23 11 0C 03 85 21 91 08 00 00 00 00 01 03 00 00
+00 00 08 09 F4 03 00 00 71 71 71 11 08 79 F0 0A
+20 08 00 05 00 A8 1E 2B 2B 00 78 00 14 3C 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 EC B5 FE C3 C3 C3 C3 CA C1 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 20 20 20 20 20 20 20
+20 20 20 20 20 20 20 20 20 20 20 20 20 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
diff --git a/spd/ddr4/set-0/spd-12.hex b/spd/ddr4/set-0/spd-12.hex
new file mode 100644
index 0000000000..24a6c01b58
--- /dev/null
+++ b/spd/ddr4/set-0/spd-12.hex
@@ -0,0 +1,32 @@
+23 11 0C 03 45 21 00 08 00 00 00 00 02 03 00 00
+00 00 07 08 F8 0F 00 00 72 72 72 11 00 72 F0 0A
+20 08 00 05 00 F0 2B 34 28 00 78 00 14 3C 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 9C B5 AC AC AC AC C1 D6 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 20 20 20 20 20 20 20
+20 20 20 20 20 20 20 20 20 20 20 20 20 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
diff --git a/spd/ddr4/set-0/spd-13.hex b/spd/ddr4/set-0/spd-13.hex
new file mode 100644
index 0000000000..4d300ee875
--- /dev/null
+++ b/spd/ddr4/set-0/spd-13.hex
@@ -0,0 +1,32 @@
+23 11 0C 03 85 21 91 08 00 00 00 00 01 03 00 00
+00 00 07 08 F8 0F 00 00 72 72 72 11 00 72 F0 0A
+20 08 00 05 00 A8 1B 2B 28 00 78 00 14 3C 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 B5 D5 AC AC AC AC C1 D6 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 20 20 20 20 20 20 20
+20 20 20 20 20 20 20 20 20 20 20 20 20 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
diff --git a/spd/ddr4/set-0/spd-14.hex b/spd/ddr4/set-0/spd-14.hex
new file mode 100644
index 0000000000..ad66842f5e
--- /dev/null
+++ b/spd/ddr4/set-0/spd-14.hex
@@ -0,0 +1,32 @@
+23 11 0C 03 44 19 00 08 00 00 00 00 02 03 00 00
+00 00 08 09 F4 03 00 00 71 71 71 11 08 79 20 08
+00 05 70 03 00 F0 2B 34 2B 00 78 00 14 3C 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 EC 9C B5 C3 C3 C3 C3 CA C1 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 20 20 20 20 20 20 20
+20 20 20 20 20 20 20 20 20 20 20 20 20 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
diff --git a/spd/ddr4/set-0/spd-15.hex b/spd/ddr4/set-0/spd-15.hex
new file mode 100644
index 0000000000..a29ce9fd6b
--- /dev/null
+++ b/spd/ddr4/set-0/spd-15.hex
@@ -0,0 +1,32 @@
+23 11 0C 03 44 19 00 08 00 00 00 00 02 03 00 00
+00 00 07 08 F8 0F 00 00 72 72 72 11 00 72 20 08
+00 05 70 03 00 F0 2B 34 28 00 78 00 14 3C 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 9C B5 AC AC AC AC C1 D6 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 20 20 20 20 20 20 20
+20 20 20 20 20 20 20 20 20 20 20 20 20 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00

From 760e19e18f22780a2d13b2f2621f0bea39d64cbe Mon Sep 17 00:00:00 2001
From: "Johann C. Rode" <jcrode@gmx.net>
Date: Thu, 13 Nov 2025 16:47:10 -0800
Subject: [PATCH 2523/3886] mb/lenovo/sklkbl: Use spd_tools infrastructure for
 SPD binaries

For the t470s variant, this patch replaces the vendor SPD binaries for
soldered-on RAM with ones generated from spd_tools. This is in
preparation for adding variants with more complex onboard RAM
configurations.

This patch has been successfully validated on hardware (Thinkpad T470s
20JT-S16E00 with 4GB soldered-on RAM and unpopulated DIMM slot).

Change-Id: I9cde4f05472105c238b3a8ee94cdedb89db08198
Depends-On: Ied92619130feaa160d01f75bc38230ab6a024ace
Signed-off-by: Johann C. Rode <jcrode@gmx.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90027
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/lenovo/sklkbl_thinkpad/Kconfig  |   2 +-
 .../lenovo/sklkbl_thinkpad/Makefile.mk        |   5 +++
 .../lenovo/sklkbl_thinkpad/spd/Makefile.mk    |   8 ++++
 .../lenovo/sklkbl_thinkpad/spd/spd.c          |  39 ++++++++++++++++++
 .../lenovo/sklkbl_thinkpad/spd/spd.h          |  10 +++++
 .../lenovo/sklkbl_thinkpad/variant.h          |   2 +-
 .../variants/t470s/Makefile.mk                |  10 -----
 .../variants/t470s/memory/Makefile.mk         |  19 +++++++++
 .../t470s/memory/dram_id.generated.txt        |  14 +++++++
 .../variants/t470s/memory/mem_parts_used.txt  |   8 ++++
 .../variants/t470s/memory_init_params.c       |  10 ++---
 .../variants/t470s/spd/spd_0.bin              | Bin 512 -> 0 bytes
 .../variants/t470s/spd/spd_1.bin              | Bin 512 -> 0 bytes
 .../variants/t470s/spd/spd_10.bin             | Bin 512 -> 0 bytes
 .../variants/t470s/spd/spd_11.bin             | Bin 512 -> 0 bytes
 .../variants/t470s/spd/spd_12.bin             | Bin 512 -> 0 bytes
 .../variants/t470s/spd/spd_13.bin             | Bin 512 -> 0 bytes
 .../variants/t470s/spd/spd_14.bin             | Bin 512 -> 0 bytes
 .../variants/t470s/spd/spd_15.bin             | Bin 512 -> 0 bytes
 .../variants/t470s/spd/spd_16.bin             | Bin 512 -> 0 bytes
 .../variants/t470s/spd/spd_17.bin             | Bin 512 -> 0 bytes
 .../variants/t470s/spd/spd_18.bin             | Bin 512 -> 0 bytes
 .../variants/t470s/spd/spd_19.bin             | Bin 512 -> 0 bytes
 .../variants/t470s/spd/spd_2.bin              | Bin 512 -> 0 bytes
 .../variants/t470s/spd/spd_20.bin             | Bin 512 -> 0 bytes
 .../variants/t470s/spd/spd_3.bin              | Bin 512 -> 0 bytes
 .../variants/t470s/spd/spd_4.bin              | Bin 512 -> 0 bytes
 .../variants/t470s/spd/spd_5.bin              | Bin 512 -> 0 bytes
 .../variants/t470s/spd/spd_6.bin              | Bin 512 -> 0 bytes
 .../variants/t470s/spd/spd_7.bin              | Bin 512 -> 0 bytes
 .../variants/t470s/spd/spd_8.bin              | Bin 512 -> 0 bytes
 .../variants/t470s/spd/spd_9.bin              | Bin 512 -> 0 bytes
 .../variants/t480s/memory_init_params.c       |   4 +-
 33 files changed, 111 insertions(+), 20 deletions(-)
 create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/spd/Makefile.mk
 create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/spd/spd.c
 create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/spd/spd.h
 delete mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t470s/Makefile.mk
 create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t470s/memory/Makefile.mk
 create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t470s/memory/dram_id.generated.txt
 create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t470s/memory/mem_parts_used.txt
 delete mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t470s/spd/spd_0.bin
 delete mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t470s/spd/spd_1.bin
 delete mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t470s/spd/spd_10.bin
 delete mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t470s/spd/spd_11.bin
 delete mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t470s/spd/spd_12.bin
 delete mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t470s/spd/spd_13.bin
 delete mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t470s/spd/spd_14.bin
 delete mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t470s/spd/spd_15.bin
 delete mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t470s/spd/spd_16.bin
 delete mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t470s/spd/spd_17.bin
 delete mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t470s/spd/spd_18.bin
 delete mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t470s/spd/spd_19.bin
 delete mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t470s/spd/spd_2.bin
 delete mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t470s/spd/spd_20.bin
 delete mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t470s/spd/spd_3.bin
 delete mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t470s/spd/spd_4.bin
 delete mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t470s/spd/spd_5.bin
 delete mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t470s/spd/spd_6.bin
 delete mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t470s/spd/spd_7.bin
 delete mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t470s/spd/spd_8.bin
 delete mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t470s/spd/spd_9.bin

diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/Kconfig b/src/mainboard/lenovo/sklkbl_thinkpad/Kconfig
index c9b3bcbf0a..8db4676391 100644
--- a/src/mainboard/lenovo/sklkbl_thinkpad/Kconfig
+++ b/src/mainboard/lenovo/sklkbl_thinkpad/Kconfig
@@ -28,6 +28,7 @@ config BOARD_LENOVO_SKLKBL_THINKPAD_COMMON
 config BOARD_LENOVO_T470S
 	bool
 	select BOARD_LENOVO_SKLKBL_THINKPAD_COMMON
+	select HAVE_SPD_IN_CBFS
 
 config BOARD_LENOVO_T480
 	bool
@@ -46,7 +47,6 @@ config BOARD_LENOVO_T580
 	select MEC1653_HAS_DEBUG_UNLOCK
 	select VARIANT_HAS_DGPU
 
-
 if BOARD_LENOVO_SKLKBL_THINKPAD_COMMON
 
 config MAINBOARD_DIR
diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/Makefile.mk b/src/mainboard/lenovo/sklkbl_thinkpad/Makefile.mk
index 3049190948..8d530b7416 100644
--- a/src/mainboard/lenovo/sklkbl_thinkpad/Makefile.mk
+++ b/src/mainboard/lenovo/sklkbl_thinkpad/Makefile.mk
@@ -13,6 +13,11 @@ ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += variants/$(VARIANT_DIR)/gma-mainb
 
 subdirs-y += variants/$(VARIANT_DIR)
 
+ifeq ($(CONFIG_BOARD_LENOVO_T470S),y)
+subdirs-y += variants/$(VARIANT_DIR)/memory
+subdirs-y += spd
+endif
+
 ifeq ($(CONFIG_VARIANT_HAS_DGPU),y)
 CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/include
 endif
diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/spd/Makefile.mk b/src/mainboard/lenovo/sklkbl_thinkpad/spd/Makefile.mk
new file mode 100644
index 0000000000..4024692461
--- /dev/null
+++ b/src/mainboard/lenovo/sklkbl_thinkpad/spd/Makefile.mk
@@ -0,0 +1,8 @@
+## SPDX-License-Identifier: GPL-2.0-or-later
+##
+
+romstage-y += spd.c
+
+ifneq ($(SPD_SOURCES),)
+LIB_SPD_DEPS := $(SPD_SOURCES)
+endif
diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/spd/spd.c b/src/mainboard/lenovo/sklkbl_thinkpad/spd/spd.c
new file mode 100644
index 0000000000..6ce18e5167
--- /dev/null
+++ b/src/mainboard/lenovo/sklkbl_thinkpad/spd/spd.c
@@ -0,0 +1,39 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <cbfs.h>
+#include <console/console.h>
+#include <device/dram/ddr4.h>
+#include <spd.h>
+
+#include "spd.h"
+
+/* Get SPD data for on-board memory */
+uint8_t *mainboard_find_spd_data(uint8_t spd_index)
+{
+	uint8_t *spd_data;
+	size_t spd_file_len;
+	char *spd_file;
+
+	spd_file = cbfs_map("spd.bin", &spd_file_len);
+	if (!spd_file)
+		die("SPD data not found.");
+
+	if (spd_file_len < ((spd_index + 1) * SPD_SIZE_MAX_DDR4)) {
+		printk(BIOS_ERR,
+		       "SPD index override to 0 due to incorrect SPD index.\n");
+		spd_index = 0;
+	}
+
+	if (spd_file_len < SPD_SIZE_MAX_DDR4)
+		die("Missing SPD data (spd.bin size %zu smaller than SPD size %u).", spd_file_len, SPD_SIZE_MAX_DDR4);
+
+	/* Assume same memory in both channels */
+	spd_index *= SPD_SIZE_MAX_DDR4;
+	spd_data = (uint8_t *)(spd_file + spd_index);
+
+	/* Make sure a valid SPD was found */
+	if (spd_data[0] == 0)
+		die("Invalid SPD data.");
+
+	return spd_data;
+}
diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/spd/spd.h b/src/mainboard/lenovo/sklkbl_thinkpad/spd/spd.h
new file mode 100644
index 0000000000..5ff716d86c
--- /dev/null
+++ b/src/mainboard/lenovo/sklkbl_thinkpad/spd/spd.h
@@ -0,0 +1,10 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef MAINBOARD_SPD_H
+#define MAINBOARD_SPD_H
+
+#include <stdint.h>
+
+uint8_t *mainboard_find_spd_data(uint8_t spd_index);
+
+#endif
diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variant.h b/src/mainboard/lenovo/sklkbl_thinkpad/variant.h
index 92255f2e0d..689e50f59b 100644
--- a/src/mainboard/lenovo/sklkbl_thinkpad/variant.h
+++ b/src/mainboard/lenovo/sklkbl_thinkpad/variant.h
@@ -5,7 +5,7 @@
 
 void variant_config_gpios(void);
 
-int variant_memory_sku(void);
+uint8_t variant_memory_sku(void);
 
 void ssdt_add_dgpu(const struct device *dev);
 
diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t470s/Makefile.mk b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t470s/Makefile.mk
deleted file mode 100644
index a6b399f161..0000000000
--- a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t470s/Makefile.mk
+++ /dev/null
@@ -1,10 +0,0 @@
-## SPDX-License-Identifier: GPL-2.0-only
-
-# Add files spd_0.bin to spd_20.bin to the cbfs image
-SPD_BINS := $(shell seq 0 20)
-define SPD_template
-cbfs-files-y += spd_$(1).bin
-spd_$(1).bin-file := spd/spd_$(1).bin
-spd_$(1).bin-type := raw
-endef
-$(foreach n,$(SPD_BINS),$(eval $(call SPD_template,$(n))))
diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t470s/memory/Makefile.mk b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t470s/memory/Makefile.mk
new file mode 100644
index 0000000000..310ad25e59
--- /dev/null
+++ b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t470s/memory/Makefile.mk
@@ -0,0 +1,19 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+# This is an auto-generated file. Do not edit!!
+# Generated by:
+# util/spd_tools/bin/part_id_gen TGL ddr4 src/mainboard/lenovo/sklkbl_thinkpad/variants/t470s/memory src/mainboard/lenovo/sklkbl_thinkpad/variants/t470s/memory/mem_parts_used.txt
+
+SPD_SOURCES =
+SPD_SOURCES += spd/ddr4/set-0/spd-10.hex      # ID = 0(0b0000)  Parts = MT40A512M16HA-083E:A
+SPD_SOURCES += spd/ddr4/set-0/spd-11.hex      # ID = 1(0b0001)  Parts = MT40A1G16HBA-083E:A
+SPD_SOURCES += spd/ddr4/set-0/spd-10.hex      # ID = 2(0b0010)  Parts = K4A8G165WB-BCPB
+SPD_SOURCES += spd/ddr4/set-0/spd-empty.hex      # ID = 3(0b0011)
+SPD_SOURCES += spd/ddr4/set-0/spd-empty.hex      # ID = 4(0b0100)
+SPD_SOURCES += spd/ddr4/set-0/spd-empty.hex      # ID = 5(0b0101)
+SPD_SOURCES += spd/ddr4/set-0/spd-empty.hex      # ID = 6(0b0110)
+SPD_SOURCES += spd/ddr4/set-0/spd-empty.hex      # ID = 7(0b0111)
+SPD_SOURCES += spd/ddr4/set-0/spd-12.hex      # ID = 8(0b1000)  Parts = MT40A512M16JY-083E:B
+SPD_SOURCES += spd/ddr4/set-0/spd-13.hex      # ID = 9(0b1001)  Parts = MT40A1G16WBU-083E:B
+SPD_SOURCES += spd/ddr4/set-0/spd-12.hex      # ID = 10(0b1010)  Parts = K4A8G165WB-BCRC
+SPD_SOURCES += spd/ddr4/set-0/spd-13.hex      # ID = 11(0b1011)  Parts = K4AAG165WB-MCRC
+SPD_SOURCES += spd/ddr4/set-0/spd-12.hex      # ID = 12(0b1100)  Parts = H5AN8G6NAFR-UHC
diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t470s/memory/dram_id.generated.txt b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t470s/memory/dram_id.generated.txt
new file mode 100644
index 0000000000..a531aa1925
--- /dev/null
+++ b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t470s/memory/dram_id.generated.txt
@@ -0,0 +1,14 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+# This is an auto-generated file. Do not edit!!
+# Generated by:
+# util/spd_tools/bin/part_id_gen TGL ddr4 src/mainboard/lenovo/sklkbl_thinkpad/variants/t470s/memory src/mainboard/lenovo/sklkbl_thinkpad/variants/t470s/memory/mem_parts_used.txt
+
+DRAM Part Name                 ID to assign
+MT40A512M16HA-083E:A           0 (0000)
+MT40A1G16HBA-083E:A            1 (0001)
+K4A8G165WB-BCPB                2 (0010)
+MT40A512M16JY-083E:B           8 (1000)
+MT40A1G16WBU-083E:B            9 (1001)
+K4A8G165WB-BCRC                10 (1010)
+K4AAG165WB-MCRC                11 (1011)
+H5AN8G6NAFR-UHC                12 (1100)
diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t470s/memory/mem_parts_used.txt b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t470s/memory/mem_parts_used.txt
new file mode 100644
index 0000000000..22f34363fd
--- /dev/null
+++ b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t470s/memory/mem_parts_used.txt
@@ -0,0 +1,8 @@
+MT40A512M16HA-083E:A,0
+MT40A1G16HBA-083E:A,1
+K4A8G165WB-BCPB,2
+MT40A512M16JY-083E:B,8
+MT40A1G16WBU-083E:B,9
+K4A8G165WB-BCRC,10
+K4AAG165WB-MCRC,11
+H5AN8G6NAFR-UHC,12
diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t470s/memory_init_params.c b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t470s/memory_init_params.c
index cc9375808a..6986607c4e 100644
--- a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t470s/memory_init_params.c
+++ b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t470s/memory_init_params.c
@@ -6,6 +6,7 @@
 #include <soc/romstage.h>
 #include <spd_bin.h>
 #include <stdio.h>
+#include "../../spd/spd.h"
 #include "../../variant.h"
 
 static const struct pad_config memory_id_gpio_table[] = {
@@ -16,7 +17,7 @@ static const struct pad_config memory_id_gpio_table[] = {
 	PAD_CFG_GPI_TRIG_OWN(GPP_F20, UP_20K, DEEP, OFF, ACPI),		/* MEMORYID4 */
 };
 
-int variant_memory_sku(void)
+uint8_t variant_memory_sku(void)
 {
         gpio_t spd_gpios[] = {
                 GPP_F16,
@@ -31,9 +32,7 @@ int variant_memory_sku(void)
 
 void mainboard_memory_init_params(FSPM_UPD *mupd)
 {
-	int spd_idx;
-	char spd_name[20];
-	size_t spd_size;
+	uint8_t spd_idx;
 
 	FSP_M_CONFIG *mem_cfg = &mupd->FspmConfig;
 	mem_cfg->DqPinsInterleaved = true;			/* DDR_DQ in interleave mode */
@@ -45,8 +44,7 @@ void mainboard_memory_init_params(FSPM_UPD *mupd)
 
 	spd_idx = variant_memory_sku();
 	printk(BIOS_DEBUG, "Detected MEMORY_ID = %d\n", spd_idx);
-	snprintf(spd_name, sizeof(spd_name), "spd_%d.bin", spd_idx);
-	mem_cfg->MemorySpdPtr00    = (uintptr_t)cbfs_map(spd_name, &spd_size);
+	mem_cfg->MemorySpdPtr00    = (uintptr_t)mainboard_find_spd_data(spd_idx);
 
 	/* Get SPD for memory slot (CH B) */
 	struct spd_block blk = { .addr_map = { [1] = 0x51, } };
diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t470s/spd/spd_0.bin b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t470s/spd/spd_0.bin
deleted file mode 100644
index 86f39ddb55ea9fb58d5e5699637636ef597c734e..0000000000000000000000000000000000000000
GIT binary patch
literal 0
HcmV?d00001

literal 512
zcmY!u;9+)EWZ+<6U|?oq29gXMJYRrxPEL*>N67~+1r7#Qh7a1t+8`-(puhlu3{YAD
YT>%dM8_BI;nL`dsaHtp+rc($20I8n}l>h($

diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t470s/spd/spd_1.bin b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t470s/spd/spd_1.bin
deleted file mode 100644
index df0f6e58b79286a4aeb690c5027adf7a1f5f668b..0000000000000000000000000000000000000000
GIT binary patch
literal 0
HcmV?d00001

literal 512
zcmY!u;9+i6oWQ}rz`)GN3?vyic)kGXoSYm%j*<^t3LFfq3@hZcwLwzoK!E`Q8KATR
Yx&j>hH(SqvWezd%<4`dwOs5b40B_I==>Px#

diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t470s/spd/spd_10.bin b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t470s/spd/spd_10.bin
deleted file mode 100644
index 24f0d8992bc5244c62488da9633e4885f52f3e22..0000000000000000000000000000000000000000
GIT binary patch
literal 0
HcmV?d00001

literal 512
zcmY!u<Y9JIWZ+;(U|?oqW&i?q-XHu740(BZf(&^dxD+@TSQ$QOn`kgpFo@WI<Pkv3
zjN25185j^Oge*SRoUI_)=hwI&^9wTJQ%GaE+Z>cy&~OfFg0G3Wp`)phiHWn5fv$6q
PvjPw>z-1}5hGzN!nb#F$

diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t470s/spd/spd_11.bin b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t470s/spd/spd_11.bin
deleted file mode 100644
index 59b6b9e78263c42aae367ab7d4a784d888f30efe..0000000000000000000000000000000000000000
GIT binary patch
literal 0
HcmV?d00001

literal 512
zcmY!u<Y8`AWZ+;(U|?osW&i?q-XHu740(BZf(&^dxD+@TSQ%DGYiKZ3Fo@WI<Pm^J
zTbD)5RGF87L5G`J#gvCx7a@nAHD@bG{`ob#fBb?9_?6OB_I)U&#y6aUn&4|<Zs=&}
YZDQ=?WT@*L<g5S$3~*UWt)ZEI0F{0fq5uE@

diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t470s/spd/spd_12.bin b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t470s/spd/spd_12.bin
deleted file mode 100644
index 93be0ac94fc57222cd29e34eee11042d7842ac25..0000000000000000000000000000000000000000
GIT binary patch
literal 0
HcmV?d00001

literal 512
zcmY!u<Y9JIWZ+;(U|?oqW&i?q-XHu740(BZf(&^dxD+@TSQ$QOn`kgpFo@WI<Pkv3
zjN25185j^Oge*SRoUI_)=hwI&^9wTJQ%GaE+Z>cy(6E*fVuXjUqlKwqu$iM<keQ!u
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diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t470s/spd/spd_13.bin b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t470s/spd/spd_13.bin
deleted file mode 100644
index 171a272bc734b72395622bf889d24972ef2d14f7..0000000000000000000000000000000000000000
GIT binary patch
literal 0
HcmV?d00001

literal 512
zcmY!u<Y8`AWZ+;(U|?osW&i?q-XHu740(BZf(&^dxD+@TSQ%DGYiKZ3Fo@WI<Pkv3
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diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t470s/spd/spd_14.bin b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t470s/spd/spd_14.bin
deleted file mode 100644
index a2a64a5e1adada3fc00b2e4edc60c77e610881a9..0000000000000000000000000000000000000000
GIT binary patch
literal 0
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literal 512
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diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t470s/spd/spd_15.bin b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t470s/spd/spd_15.bin
deleted file mode 100644
index a2a64a5e1adada3fc00b2e4edc60c77e610881a9..0000000000000000000000000000000000000000
GIT binary patch
literal 0
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literal 512
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GCj$V){1T)9

diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t470s/spd/spd_16.bin b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t470s/spd/spd_16.bin
deleted file mode 100644
index a64a5a93fb4aef4d5f63d79cb2582731b9ac5063..0000000000000000000000000000000000000000
GIT binary patch
literal 0
HcmV?d00001

literal 512
NcmZQz7zHCa1ONg600961

diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t470s/spd/spd_17.bin b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t470s/spd/spd_17.bin
deleted file mode 100644
index 5f23e86606094d3e5d2011db902ebd4a500bbffa..0000000000000000000000000000000000000000
GIT binary patch
literal 0
HcmV?d00001

literal 512
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zjN25185j^Oge*SRoUI_)=M3$7{ESTa6w+Akz#~d6Xjsb#F~Y;w(ZbX)*v#20$jnbS
V%v%8n7#i08$7jJ^e3JB$0{}ZV7fApB

diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t470s/spd/spd_18.bin b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t470s/spd/spd_18.bin
deleted file mode 100644
index 05633943eb5af166da66a2e1f4e74948f75782fb..0000000000000000000000000000000000000000
GIT binary patch
literal 0
HcmV?d00001

literal 512
zcmY!u<Y9JIoXEkDz`)GN%m4&zyg%$281nM+1R3%^a4B#wurhqmHql_HU=XnZ$s>T6
z8Mi42GcX`n2w8lrIa@)p&l&!{<7bq|r;x^SwThHl(6E*fVuXjUqobjFu$i-OkeQ!u
Vn70BDFf^?FkI#a;_$28g2LNS*7)Ag9

diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t470s/spd/spd_19.bin b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t470s/spd/spd_19.bin
deleted file mode 100644
index 857da9c9828cdac842329f6cef4539283777268b..0000000000000000000000000000000000000000
GIT binary patch
literal 0
HcmV?d00001

literal 512
zcmY!u<Y9JIWZ+;(U|?oqW&i?K-XH(98S?V-1R3%^a4B#wurhqmHql_HU=XnZ$x{Q&
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GP6hy+m=i1j

diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t470s/spd/spd_2.bin b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t470s/spd/spd_2.bin
deleted file mode 100644
index b5b14cf2dfa06ae183b0379da4dc825129e1589f..0000000000000000000000000000000000000000
GIT binary patch
literal 0
HcmV?d00001

literal 512
zcmY!u;9+)EWZ+<6U|?oq29gXMJU@VRUS6IcN7)B11r7#Qh7a1tdLSuupuhlu3{YAD
XT>%b$v*cE=%%S%6I8=-Z(<uZ1pPdSg

diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t470s/spd/spd_20.bin b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t470s/spd/spd_20.bin
deleted file mode 100644
index a64a5a93fb4aef4d5f63d79cb2582731b9ac5063..0000000000000000000000000000000000000000
GIT binary patch
literal 0
HcmV?d00001

literal 512
NcmZQz7zHCa1ONg600961

diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t470s/spd/spd_3.bin b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t470s/spd/spd_3.bin
deleted file mode 100644
index d73736008af1eb67456b2fd66f7dec3b6669a442..0000000000000000000000000000000000000000
GIT binary patch
literal 0
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literal 512
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diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t470s/spd/spd_4.bin b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t470s/spd/spd_4.bin
deleted file mode 100644
index 829f149547bc24859646c33d5926938d7a1b90cb..0000000000000000000000000000000000000000
GIT binary patch
literal 0
HcmV?d00001

literal 512
zcmY!u;9+)EWZ+<6U|?oq29gXMJYRrxPEL*>N67~+1r7#Qh7a1tdLSuupuhlu3{YAD
XT>%b$o8(ro%%OI594bbI=@bG0z{d&v

diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t470s/spd/spd_5.bin b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t470s/spd/spd_5.bin
deleted file mode 100644
index a64a5a93fb4aef4d5f63d79cb2582731b9ac5063..0000000000000000000000000000000000000000
GIT binary patch
literal 0
HcmV?d00001

literal 512
NcmZQz7zHCa1ONg600961

diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t470s/spd/spd_6.bin b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t470s/spd/spd_6.bin
deleted file mode 100644
index a64a5a93fb4aef4d5f63d79cb2582731b9ac5063..0000000000000000000000000000000000000000
GIT binary patch
literal 0
HcmV?d00001

literal 512
NcmZQz7zHCa1ONg600961

diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t470s/spd/spd_7.bin b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t470s/spd/spd_7.bin
deleted file mode 100644
index 940f1e3cd8e5bd9ea32a82a14edcdcbc8132d8c7..0000000000000000000000000000000000000000
GIT binary patch
literal 0
HcmV?d00001

literal 512
zcmY!u<Y8`AWZ+;(U|?osW&i><-XH%N8S?V-1R3%^a4B#wurjQW(9mG0U=XnZ$x{Q&
z0UPq1A)%L_QJxwGl4(Y*BAFWD+8T7AOcTeDU_*B^6OSleBX=`bLy)jxgN`d)<=|uh
E020*^DF6Tf

diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t470s/spd/spd_8.bin b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t470s/spd/spd_8.bin
deleted file mode 100644
index 30c84410d417ef7afa8705c93cdb64a9f4e915a0..0000000000000000000000000000000000000000
GIT binary patch
literal 0
HcmV?d00001

literal 512
zcmY!u<Y9JIWZ+;(U|?oqW&i?q-XHZ040(BZf(&^dxD+@TSQ$QOn`kgpFo@WI<f#GX
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H2PXpn6CD!Q

diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t470s/spd/spd_9.bin b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t470s/spd/spd_9.bin
deleted file mode 100644
index 7facef55b93fe1f67411c00bab84862769461f63..0000000000000000000000000000000000000000
GIT binary patch
literal 0
HcmV?d00001

literal 512
zcmY!u<Y8`AWZ+;(U|?osW&i?q-XHZ040(BZf(&^dxD+@TSQ%DGYiKZ3Fo@WI<f#GX
zYz3L}{F>W!enxp}7)YiWinU~FgllWifig`TLxK(6%}hL^bdB7N9Ss$Lz^FmT39fQ*
FG5`?&65ap+

diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/memory_init_params.c b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/memory_init_params.c
index 3cbca9ae6c..bb3152f62c 100644
--- a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/memory_init_params.c
+++ b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/memory_init_params.c
@@ -16,7 +16,7 @@ static const struct pad_config memory_id_gpio_table[] = {
        PAD_CFG_GPI_TRIG_OWN(GPP_F20, UP_20K, DEEP, OFF, ACPI),         /* MEMORYID4 */
 };
 
-int variant_memory_sku(void)
+uint8_t variant_memory_sku(void)
 {
         gpio_t spd_gpios[] = {
                 GPP_F16,
@@ -31,7 +31,7 @@ int variant_memory_sku(void)
 
 void mainboard_memory_init_params(FSPM_UPD *mupd)
 {
-	int spd_idx;
+	uint8_t spd_idx;
 	char spd_name[20];
 	size_t spd_size;
 

From a48fd9ed7f85009c4a717d5f44634f55fda70960 Mon Sep 17 00:00:00 2001
From: Ana Carolina Cabral <ana.cpmelo95@gmail.com>
Date: Fri, 28 Mar 2025 09:48:04 -0300
Subject: [PATCH 2524/3886] soc/amd/cezanne: Add SOC_AMD_RENOIR as a Cezanne
 variant

AMD Renoir soc is very similar to Cezanne and has been used without
differentiation until now. Create the separation between SOCs using
Kconfig option to facilitate the customization of different features.
Also update SOC_AMD_RENOIR use on the crater mainboard.

Change-Id: I4783c4e3b17032b6d26ef67ddf954df3ce68fdf0
Signed-off-by: Ana Carolina Cabral <ana.cpmelo95@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87215
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/amd/crater/Kconfig  |  2 +-
 src/soc/amd/cezanne/Kconfig       | 25 +++++++++++++++---
 src/soc/amd/cezanne/Makefile.mk   |  4 +--
 src/soc/amd/cezanne/chip.c        |  4 +++
 src/soc/amd/cezanne/fw_renoir.cfg | 44 +++++++++++++++++++++++++++++++
 5 files changed, 73 insertions(+), 6 deletions(-)
 create mode 100644 src/soc/amd/cezanne/fw_renoir.cfg

diff --git a/src/mainboard/amd/crater/Kconfig b/src/mainboard/amd/crater/Kconfig
index 3312988926..110ba14fa1 100644
--- a/src/mainboard/amd/crater/Kconfig
+++ b/src/mainboard/amd/crater/Kconfig
@@ -22,7 +22,7 @@ config BOARD_AMD_CRATER_COMMON
 
 config BOARD_AMD_CRATER_RENOIR
 	select BOARD_AMD_CRATER_COMMON
-	select SOC_AMD_CEZANNE
+	select SOC_AMD_RENOIR
 
 if BOARD_AMD_CRATER_RENOIR
 
diff --git a/src/soc/amd/cezanne/Kconfig b/src/soc/amd/cezanne/Kconfig
index db4dc10a97..2fe56c0c4b 100644
--- a/src/soc/amd/cezanne/Kconfig
+++ b/src/soc/amd/cezanne/Kconfig
@@ -1,6 +1,6 @@
 # SPDX-License-Identifier: GPL-2.0-only
 
-config SOC_AMD_CEZANNE
+config SOC_AMD_CEZANNE_BASE
 	bool
 	select ACPI_SOC_NVS
 	select ADD_FSP_BINARIES if USE_AMD_BLOBS
@@ -91,7 +91,19 @@ config SOC_AMD_CEZANNE
 	help
 	  AMD Cezanne support
 
-if SOC_AMD_CEZANNE
+config SOC_AMD_CEZANNE
+	bool
+	select SOC_AMD_CEZANNE_BASE
+	help
+		AMD Cezanne support
+
+config SOC_AMD_RENOIR
+	bool
+	select SOC_AMD_CEZANNE_BASE
+	help
+		AMD Renoir support
+
+if SOC_AMD_CEZANNE_BASE
 
 config KEEP_ACP_RUNNING_IN_S3
 	bool
@@ -107,6 +119,7 @@ config CHIPSET_DEVICETREE
 config FSP_M_FILE
 	string "FSP-M (memory init) binary path and filename"
 	depends on ADD_FSP_BINARIES
+	#default "3rdparty/amd_blobs/renoir/RENOIR_M.fd" if SOC_AMD_RENOIR
 	default "3rdparty/amd_blobs/cezanne/CEZANNE_M.fd"
 	help
 	  The path and filename of the FSP-M binary for this platform.
@@ -114,6 +127,7 @@ config FSP_M_FILE
 config FSP_S_FILE
 	string "FSP-S (silicon init) binary path and filename"
 	depends on ADD_FSP_BINARIES
+	#default "3rdparty/amd_blobs/renoir/RENOIR_S.fd" if SOC_AMD_RENOIR
 	default "3rdparty/amd_blobs/cezanne/CEZANNE_S.fd"
 	help
 	  The path and filename of the FSP-S binary for this platform.
@@ -256,6 +270,7 @@ config RO_REGION_ONLY
 	default "apu/amdfw"
 
 config ECAM_MMCONF_BASE_ADDRESS
+	default 0xE0000000 if SOC_AMD_RENOIR
 	default 0xF8000000
 
 config ECAM_MMCONF_BUS_NUMBER
@@ -269,6 +284,7 @@ config MAX_CPUS
 
 config VGA_BIOS_ID
 	string
+	default "1002,1636" if SOC_AMD_RENOIR
 	default "1002,1638"
 	help
 	  The default VGA BIOS PCI vendor/device ID should be set to the
@@ -276,6 +292,7 @@ config VGA_BIOS_ID
 
 config VGA_BIOS_FILE
 	string
+	#default "3rdparty/amd_blobs/renoir/RenoirGenericVbios.bin" if SOC_AMD_RENOIR
 	default "3rdparty/amd_blobs/cezanne/CezanneGenericVbios.bin"
 
 config CONSOLE_UART_BASE_ADDRESS
@@ -337,6 +354,7 @@ menu "PSP Configuration Options"
 
 config AMDFW_CONFIG_FILE
 	string
+	#default "src/soc/amd/cezanne/fw_renoir.cfg" if SOC_AMD_RENOIR
 	default "src/soc/amd/cezanne/fw.cfg"
 
 config PSP_DISABLE_POSTCODES
@@ -385,6 +403,7 @@ config HAVE_PSP_WHITELIST_FILE
 config PSP_WHITELIST_FILE
 	string "Debug whitelist file path"
 	depends on HAVE_PSP_WHITELIST_FILE
+	#default "3rdparty/amd_blobs/renoir/PSP/wtl-rn.sbin" if SOC_AMD_RENOIR
 	default "3rdparty/amd_blobs/cezanne/PSP/wtl-czn.sbin"
 
 config PSP_SOFTFUSE_BITS
@@ -492,4 +511,4 @@ config SERIRQ_CONTINUOUS_MODE
 	  Set this option to y for serial IRQ in continuous mode.
 	  Otherwise it is in quiet mode.
 
-endif # SOC_AMD_CEZANNE
+endif # SOC_AMD_CEZANNE_BASE
diff --git a/src/soc/amd/cezanne/Makefile.mk b/src/soc/amd/cezanne/Makefile.mk
index 80a877a978..d01fbf4006 100644
--- a/src/soc/amd/cezanne/Makefile.mk
+++ b/src/soc/amd/cezanne/Makefile.mk
@@ -1,6 +1,6 @@
 # SPDX-License-Identifier: BSD-3-Clause
 
-ifeq ($(CONFIG_SOC_AMD_CEZANNE),y)
+ifeq ($(CONFIG_SOC_AMD_CEZANNE_BASE),y)
 
 subdirs-$(CONFIG_VBOOT_STARTS_BEFORE_BOOTBLOCK) += psp_verstage
 
@@ -285,4 +285,4 @@ apu/amdfw_b-position := $(AMD_FW_AB_POSITION)
 apu/amdfw_b-type := raw
 endif
 
-endif # ($(CONFIG_SOC_AMD_CEZANNE),y)
+endif # ($(CONFIG_SOC_AMD_CEZANNE_BASE),y)
diff --git a/src/soc/amd/cezanne/chip.c b/src/soc/amd/cezanne/chip.c
index 7463352963..a4a80f4cb8 100644
--- a/src/soc/amd/cezanne/chip.c
+++ b/src/soc/amd/cezanne/chip.c
@@ -53,7 +53,11 @@ static void soc_final(void *chip_info)
 }
 
 struct chip_operations soc_amd_cezanne_ops = {
+#if CONFIG(SOC_AMD_CEZANNE)
 	.name = "AMD Cezanne SoC",
+#elif CONFIG(SOC_AMD_RENOIR)
+	.name = "AMD Renoir SoC",
+#endif
 	.init = soc_init,
 	.final = soc_final
 };
diff --git a/src/soc/amd/cezanne/fw_renoir.cfg b/src/soc/amd/cezanne/fw_renoir.cfg
new file mode 100644
index 0000000000..192ab44f22
--- /dev/null
+++ b/src/soc/amd/cezanne/fw_renoir.cfg
@@ -0,0 +1,44 @@
+#TODO update for renoir
+# PSP fw config file
+
+FIRMWARE_LOCATION       3rdparty/amd_blobs/cezanne/PSP
+SOC_NAME                Renoir
+
+# type                    file
+# PSP
+AMD_PUBKEY_FILE         TypeId0x00_CezannePublicKey.tkn Lxb
+PSPBTLDR_FILE           TypeId0x01_PspBootLoader_CZN.sbin
+PSPBTLDR_AB_STAGE1_FILE TypeId0x01_PspBootLoader_AB_Stage1_CZN.sbin Lx1
+PSPBTLDR_WL_FILE        TypeId0x01_PspBootLoader_WL_CZN.sbin
+PSPSECUREOS_FILE        TypeId0x02_PspOS_CZN.sbin
+PSPRCVR_FILE            TypeId0x03_PspRecoveryBootLoader_CZN.sbin
+PSP_SMUFW1_SUB0_FILE    TypeId0x08_SmuFirmware_CZN.csbin
+PSPSECUREDEBUG_FILE     TypeId0x09_SecureDebugUnlockKey_CZN.stkn
+PSPTRUSTLETS_FILE       TypeId0x0C_FtpmDrv_CZN.csbin
+PSP_SMUFW2_SUB0_FILE    TypeId0x12_SmuFirmware2_CZN.csbin
+PSP_SEC_DEBUG_FILE      TypeId0x13_PspEarlyUnlock_CZN.sbin
+PSP_HW_IPCFG_FILE_SUB0  TypeId0x20_HwIpCfg_CZN_A0.sbin
+PSP_IKEK_FILE           TypeId0x21_PspIkek_CZN.bin Lxb
+PSP_SECG0_FILE          TypeId0x24_SecurePolicyL0_CZN.sbin
+PSP_MP2FW0_FILE         TypeId0x25_Mp2Fw_CZN.sbin
+AMD_DRIVER_ENTRIES      TypeId0x28_PspSystemDriver_CZN.sbin
+PSP_KVM_ENGINE_DUMMY_FILE TypeId0x29_KvmEngineDummy.csbin
+PSP_S0I3_FILE           TypeId0x2D_AgesaRunTimeDrv_CZN.sbin
+PSP_ABL0_FILE           TypeId0x30_AgesaBootloaderU_CZN_LPDDR4.csbin
+VBIOS_BTLOADER_FILE       TypeId0x3C_VbiosBootLoader_CZN.sbin
+SECURE_POLICY_L1_FILE   TypeId0x45_SecurePolicyL1_CZN.sbin
+UNIFIEDUSB_FILE         TypeId0x44_UnifiedUsb_CZN.sbin
+DRTMTA_FILE             TypeId0x47_DrtmTA_CZN.sbin
+KEYDBBL_FILE            TypeId0x50_KeyDbBl_CZN.sbin
+KEYDB_TOS_FILE          TypeId0x51_KeyDbTos_CZN.sbin
+SPL_TABLE_FILE          TypeId0x55_SplTableBl_CZN.sbin
+DMCUERAMDCN21_FILE      TypeId0x58_DmcuEramDcn21.sbin
+DMCUINTVECTORSDCN21_FILE  TypeId0x59_DmcuIntvectorsDcn21.sbin
+PSPBTLDR_AB_FILE        TypeId0x73_PspBootLoader_AB_CZN.sbin
+
+# BDT
+PSP_PMUI_FILE_SUB0_INS1  TypeId0x64_Appb_CZN_1D_Lpddr4_Imem.csbin
+PSP_PMUD_FILE_SUB0_INS1  TypeId0x65_Appb_CZN_1D_Lpddr4_Dmem.csbin
+PSP_PMUI_FILE_SUB0_INS4  TypeId0x64_Appb_CZN_2D_Lpddr4_Imem.csbin
+PSP_PMUD_FILE_SUB0_INS4  TypeId0x65_Appb_CZN_2D_Lpddr4_Dmem.csbin
+PSP_MP2CFG_FILE MP2FWConfig.sbin

From 1e28ff69553fc5a1dcd3b62f09e1a9660cf57944 Mon Sep 17 00:00:00 2001
From: Maximilian Brune <maximilian.brune@9elements.com>
Date: Tue, 18 Nov 2025 23:38:40 +0100
Subject: [PATCH 2525/3886] src/mb/amd/crater/port_descriptors_renoir.c:
 Prettify code

Doesn't change anything functionality wise, but passes the extended linter.

Change-Id: Ic6f1b3d9fb3fee7dca2ac0ef8909d6567abfc99f
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90102
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
---
 src/mainboard/amd/crater/port_descriptors_renoir.c | 10 +++++-----
 1 file changed, 5 insertions(+), 5 deletions(-)

diff --git a/src/mainboard/amd/crater/port_descriptors_renoir.c b/src/mainboard/amd/crater/port_descriptors_renoir.c
index 7ecb797a28..a22bf94632 100644
--- a/src/mainboard/amd/crater/port_descriptors_renoir.c
+++ b/src/mainboard/amd/crater/port_descriptors_renoir.c
@@ -15,12 +15,12 @@
 
 #define ECRAM_BOARDID_OFFSET 0x93
 
-#define CRATER_EC_CMD	0x666
-#define CRATER_EC_DATA	0x662
+#define CRATER_EC_CMD   0x666
+#define CRATER_EC_DATA  0x662
 
-#define CRATER_REVB     0x42
+#define CRATER_REVB 0x42
 
-#define mxm_dxio_descriptor {	\
+#define mxm_dxio_descriptor { \
 	.engine_type = PCIE_ENGINE, \
 	.port_present = true, \
 	.start_logical_lane = 16, \
@@ -67,7 +67,7 @@
 	.port_params = {PP_PSPP_AC, 0x133, PP_PSPP_DC, 0x122},  \
 }
 
-#define wwan_dxio_descriptor {	\
+#define wwan_dxio_descriptor { \
 	.engine_type = PCIE_ENGINE,  \
 	.port_present = true,  \
 	.start_logical_lane = 2,  \

From 141fd11d79f5c05e4c4a9ec27c0fc8a6623121f3 Mon Sep 17 00:00:00 2001
From: Maximilian Brune <maximilian.brune@9elements.com>
Date: Tue, 18 Nov 2025 23:50:28 +0100
Subject: [PATCH 2526/3886] mb/amd/crater: Rename ETH_AIC_SLOT_ONLY ->
 PCIE_DT_SLOT

Also adds some help messages to make it more clearly on what this
Kconfig achives.

Change-Id: Ic74ea602c038f029a5b7b1edb256c23c6ad1ba9f
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90103
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
---
 src/mainboard/amd/crater/Kconfig                   | 11 +++++++----
 src/mainboard/amd/crater/port_descriptors_renoir.c |  5 ++---
 2 files changed, 9 insertions(+), 7 deletions(-)

diff --git a/src/mainboard/amd/crater/Kconfig b/src/mainboard/amd/crater/Kconfig
index 110ba14fa1..1560201ea3 100644
--- a/src/mainboard/amd/crater/Kconfig
+++ b/src/mainboard/amd/crater/Kconfig
@@ -101,12 +101,15 @@ choice
 config XGBE_WWAN_WLAN
 	bool "XGBE_WWAN_WLAN"
 	help
-	  Use GPP[0:1] for XGBE (ETH_AIC_SLOT), GPP[2] for WWAN slot and GPP[3] for WLAN slot.
+	  Use GPP[0:1] connected to ETH AIC  (PCIe x4 Slot)
+	  Use GPP[2]   connected to WWAN/GPS (M.2 B-Key)
+	  Use GPP[3]   connected to WiFi/BT  (M.2 E-Key)
 
-config ETH_AIC_SLOT_ONLY
-	bool "DT Enablement"
+config PCIE_DT_SLOT
+	bool "PCIe Slot"
 	help
-	  Use GPP[0:3] for as PCIE (ETH_AIC_SLOT) only
+	  Use GPP[0:3] connected to PCIe x4 Slot
+
 endchoice
 
 if !EM100	# EM100 defaults in soc/amd/common/blocks/spi/Kconfig
diff --git a/src/mainboard/amd/crater/port_descriptors_renoir.c b/src/mainboard/amd/crater/port_descriptors_renoir.c
index a22bf94632..cfc6e2f35c 100644
--- a/src/mainboard/amd/crater/port_descriptors_renoir.c
+++ b/src/mainboard/amd/crater/port_descriptors_renoir.c
@@ -185,10 +185,9 @@ void mainboard_get_dxio_ddi_descriptors(
 		mxm_dxio_descriptor,
 		ssd_dxio_descriptor,
 		tb_dxio_descriptor,
-#if CONFIG(ETH_AIC_SLOT_ONLY)
+#if CONFIG(PCIE_DT_SLOT)
 		dt_dxio_descriptor, // GPP 0~3
-#endif
-#if CONFIG(XGBE_WWAN_WLAN)
+#elif CONFIG(XGBE_WWAN_WLAN)
 		xgbe_port0_dxio_descriptor, // GPP 0
 		xgbe_port1_dxio_descriptor, // GPP 1
 		wwan_dxio_descriptor, // GPP 2

From 9d355a39aa36dee77a9b28985d93f91fe4bc88f7 Mon Sep 17 00:00:00 2001
From: Ana Carolina Cabral <ana.cpmelo95@gmail.com>
Date: Tue, 8 Apr 2025 09:52:45 -0300
Subject: [PATCH 2527/3886] mb/amd/crater/ec.c: Enable power/reset for PCIe
 lanes

The EC controls the power and reset to some of the PCIe devices.

Change-Id: Ic607978e32486ecd4563c32cd6a5ff1dfd125013
Signed-off-by: Ana Carolina Cabral <ana.cpmelo95@gmail.com>
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87221
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/amd/crater/ec.c | 30 +++++++++++++++++++++++++++---
 1 file changed, 27 insertions(+), 3 deletions(-)

diff --git a/src/mainboard/amd/crater/ec.c b/src/mainboard/amd/crater/ec.c
index fa7c21fa1b..e9a947523f 100644
--- a/src/mainboard/amd/crater/ec.c
+++ b/src/mainboard/amd/crater/ec.c
@@ -31,8 +31,10 @@
 #define   EC4_TBT_PWREN		BIT(0)
 
 #define EC_GPIO_7_ADDR		0xA7
+#define   EC7_DT_WLAN_EN	BIT(6)
 #define   EC7_SSD_HDD_SW	BIT(5)
 #define   EC7_ODD_SSD_SW	BIT(4)
+#define   EC7_DT_WLAN_SW	BIT(3)
 #define   EC7_CAM1_EN		BIT(0)
 
 #define EC_GPIO_8_ADDR		0xA8
@@ -110,7 +112,6 @@ static void configure_ec_gpio(void)
 	uint8_t tmp;
 
 	tmp = ec_read(EC_GPIO_2_ADDR);
-	printk(BIOS_SPEW, "A2: Write reg [0x%02x] = 0x%02x\n", EC_GPIO_2_ADDR, tmp);
 	if (CONFIG(ENABLE_EVAL_CARD)) {
 		tmp |= EC2_EVAL_SLOT_PWREN;
 		if (CONFIG(ENABLE_EVAL_19V)) {
@@ -122,21 +123,44 @@ static void configure_ec_gpio(void)
 		tmp &= ~EC2_EVAL_SLOT_PWREN;
 		tmp &= ~EC2_EVAL_19V_EN;
 	}
+
+	if (CONFIG(PCIE_DT_SLOT))
+		tmp |= EC2_DT_PWREN;
+
 	printk(BIOS_SPEW, "Write reg [0x%02x] = 0x%02x\n", EC_GPIO_2_ADDR, tmp);
 	ec_write(EC_GPIO_2_ADDR, tmp);
 
+	tmp = ec_read(EC_GPIO_3_ADDR);
+	tmp |= EC3_WLAN_RST_AUX | EC3_WWAN_RST_AUX | EC3_SD_RST_AUX;
+	tmp |= EC3_DT_RST | EC3_LOM_RST_AUX | EC3_EVAL_RST_AUX | EC3_TBT_RST;
+	printk(BIOS_SPEW, "Write reg [0x%02x] = 0x%02x\n", EC_GPIO_3_ADDR, tmp);
+	ec_write(EC_GPIO_3_ADDR, tmp);
+
+	//TBT pwr EN (GPP 4~7)
+	tmp = ec_read(EC_GPIO_4_ADDR);
+	tmp |= EC4_TBT_PWREN;
+	printk(BIOS_SPEW, "Write reg [0x%02x] = 0x%02x\n", EC_GPIO_4_ADDR, tmp);
+	ec_write(EC_GPIO_4_ADDR, tmp);
+
 	tmp = ec_read(EC_GPIO_7_ADDR);
-	printk(BIOS_SPEW, "A7: Write reg [0x%02x] = 0x%02x\n", EC_GPIO_7_ADDR, tmp);
 	if (CONFIG(ENABLE_M2_SSD1)) {
 		tmp |= (EC7_ODD_SSD_SW | EC7_SSD_HDD_SW);
 	} else {
 		tmp &= ~(EC7_ODD_SSD_SW | EC7_SSD_HDD_SW);
 	}
+
+	if (CONFIG(PCIE_DT_SLOT)) {
+		tmp &= ~(EC7_DT_WLAN_SW);
+		tmp |= EC7_DT_WLAN_EN;
+	} else { // XGBE_WWAN_WLAN
+		tmp &= ~(EC7_DT_WLAN_EN);
+		tmp |= EC7_DT_WLAN_SW;
+	}
+
 	printk(BIOS_SPEW, "Write reg [0x%02x] = 0x%02x\n", EC_GPIO_7_ADDR, tmp);
 	ec_write(EC_GPIO_7_ADDR, tmp);
 
 	tmp = ec_read(EC_GPIO_8_ADDR);
-	printk(BIOS_SPEW, "A8: Write reg [0x%02x] = 0x%02x\n", EC_GPIO_8_ADDR, tmp);
 	if (CONFIG(ENABLE_M2_SSD1)) {
 		tmp |= EC8_M2SSD_PWREN;
 	} else {

From 450389be05fd474eaa419e99f9297c6ac8d83592 Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Wed, 29 Oct 2025 18:52:39 -0500
Subject: [PATCH 2528/3886] ec/google/chromeec: Add fan presence helper
 function

Add google_chromeec_has_fan() to determine if a board has a fan or not.
The function first tries the EC feature flag (EC_FEATURE_PWM_FAN),
falling back to a RPM read test if the flag is unavailable.

TEST=tested hooked up to a CFR option to enable auto fan control at
boot, with option visibility controlled by fan presence, on a range
of Chromebooks with and without PWM-controlled fans.

Change-Id: I2a920709f0e6780c779a87568d6a8d18f817c76d
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89829
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
---
 src/ec/google/chromeec/ec.c | 38 +++++++++++++++++++++++++++++++++++++
 src/ec/google/chromeec/ec.h |  1 +
 2 files changed, 39 insertions(+)

diff --git a/src/ec/google/chromeec/ec.c b/src/ec/google/chromeec/ec.c
index 66cf54c4b0..27c752b196 100644
--- a/src/ec/google/chromeec/ec.c
+++ b/src/ec/google/chromeec/ec.c
@@ -134,6 +134,44 @@ bool google_chromeec_has_kbbacklight(void)
 	}
 }
 
+bool google_chromeec_has_fan(void)
+{
+	/* Try the PWM fan feature flag (most reliable for modern ECs) */
+	int feature_check = google_chromeec_check_feature(EC_FEATURE_PWM_FAN);
+
+	if (feature_check > 0) {
+		printk(BIOS_DEBUG, "Chrome EC: Fan detected (feature flag)\n");
+		return true;
+	} else if (feature_check == 0) {
+		printk(BIOS_DEBUG, "Chrome EC: No fan (feature flag)\n");
+		return false;
+	}
+
+	/* Feature flag unavailable, try reading fan duty as a fallback test */
+	printk(BIOS_DEBUG, "Chrome EC: Feature flag unavailable, testing fan read\n");
+	const struct ec_params_pwm_get_fan_duty params = {
+		.fan_idx = 0,
+	};
+	struct ec_response_pwm_get_fan_rpm resp = {};
+	struct chromeec_command cmd = {
+		.cmd_code = EC_CMD_PWM_GET_FAN_TARGET_RPM,
+		.cmd_version = 0,
+		.cmd_data_in = &params,
+		.cmd_size_in = sizeof(params),
+		.cmd_data_out = &resp,
+		.cmd_size_out = sizeof(resp),
+		.cmd_dev_index = 0,
+	};
+
+	if (google_chromeec_command(&cmd) == 0) {
+		printk(BIOS_DEBUG, "Chrome EC: Fan detected (read test)\n");
+		return true;
+	} else {
+		printk(BIOS_DEBUG, "Chrome EC: No fan (read test)\n");
+		return false;
+	}
+}
+
 void google_chromeec_post(uint8_t postcode)
 {
 	/* backlight is a percent. postcode is a uint8_t.
diff --git a/src/ec/google/chromeec/ec.h b/src/ec/google/chromeec/ec.h
index 3c77eeb459..04d5fba1c3 100644
--- a/src/ec/google/chromeec/ec.h
+++ b/src/ec/google/chromeec/ec.h
@@ -81,6 +81,7 @@ uint64_t  google_chromeec_get_events_b(void);
 int google_chromeec_clear_events_b(uint64_t mask);
 int google_chromeec_kbbacklight(int percent);
 bool google_chromeec_has_kbbacklight(void);
+bool google_chromeec_has_fan(void);
 void google_chromeec_post(uint8_t postcode);
 uint8_t google_chromeec_get_switches(void);
 bool google_chromeec_get_ap_watchdog_flag(void);

From 1ca1dc6c313a710ab1983b8d3b8011ae160e12d5 Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Wed, 29 Oct 2025 18:59:46 -0500
Subject: [PATCH 2529/3886] ec/google/chromeec: Add ability to enable auto fan
 control via setup option

Allow enabling of automatic fan control via a setup option, while
preserving the functionality of the existing Kconfig symbol.

TEST=tested hooked up to a CFR option to toggle automatic fan control
at boot, with visibility controlled by fan presence, on a range of
ChromeOS devices with and without a PWM-controlled fan.

Change-Id: I0510c0d0bd79106036f77d59e04d455ee904ce6e
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89830
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/ec/google/chromeec/ec.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/ec/google/chromeec/ec.c b/src/ec/google/chromeec/ec.c
index 27c752b196..662e83e4b2 100644
--- a/src/ec/google/chromeec/ec.c
+++ b/src/ec/google/chromeec/ec.c
@@ -1366,7 +1366,7 @@ void google_chromeec_init(void)
 	google_chromeec_log_uptimeinfo();
 
 	/* Enable automatic fan control */
-	if (CONFIG(EC_GOOGLE_CHROMEEC_AUTO_FAN_CTRL)) {
+	if (get_uint_option("auto_fan_control", CONFIG(EC_GOOGLE_CHROMEEC_AUTO_FAN_CTRL))) {
 		ec_cmd_thermal_auto_fan_ctrl(PLAT_EC);
 	}
 

From cae53bea52f794e7e4986f07e63066ed845cabee Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Sun, 19 Oct 2025 17:33:46 -0500
Subject: [PATCH 2530/3886] ec/google/chromeec: Add CFR options for keyboard
 backlight and fan control

Create a new header with CFR objects for keyboard backlight and
automatic fan control, which mainboards can include in their
setup menus in order to expose the options. The visibility of the
options are controlled by callbacks which test for device presence.

Change-Id: I2386b527f65b2e3b4ca43b9b65b69040abee00ad
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89831
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
---
 src/ec/google/chromeec/cfr.h | 58 ++++++++++++++++++++++++++++++++++++
 1 file changed, 58 insertions(+)
 create mode 100644 src/ec/google/chromeec/cfr.h

diff --git a/src/ec/google/chromeec/cfr.h b/src/ec/google/chromeec/cfr.h
new file mode 100644
index 0000000000..980ac120c4
--- /dev/null
+++ b/src/ec/google/chromeec/cfr.h
@@ -0,0 +1,58 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+/*
+ * CFR enums and structs which are used to control EC settings.
+ */
+
+#ifndef _CHROMEEC_CFR_H_
+#define _CHROMEEC_CFR_H_
+
+#include <drivers/option/cfr_frontend.h>
+#include "ec.h"
+
+static void update_fan_control(const struct sm_object *obj, struct sm_object *new)
+{
+	if (!CONFIG(EC_GOOGLE_CHROMEEC_AUTO_FAN_CTRL) && !google_chromeec_has_fan()) {
+		new->sm_bool.flags = CFR_OPTFLAG_SUPPRESS;
+		new->sm_bool.default_value = 0;
+	}
+}
+
+static const struct sm_object auto_fan_control = SM_DECLARE_ENUM({
+	.opt_name       = "auto_fan_control",
+	.ui_name        = "Automatic Fan Control",
+	.ui_helptext    = "Enable or disable automatic fan control.",
+	.default_value  = CONFIG(EC_GOOGLE_CHROMEEC_AUTO_FAN_CTRL),
+	.values         = (struct sm_enum_value[]) {
+		{ "Enabled", 1 },
+		{ "Disabled", 0 },
+		SM_ENUM_VALUE_END,
+	},
+}, WITH_CALLBACK(update_fan_control));
+
+static const struct sm_enum_value ec_backlight_values[] = {
+	{ "0%", 0 },
+	{ "25%", 25 },
+	{ "50%", 50 },
+	{ "100%", 100 },
+	SM_ENUM_VALUE_END,
+};
+
+static void update_kb_backlight(const struct sm_object *obj, struct sm_object *new)
+{
+	if (!google_chromeec_has_kbbacklight()) {
+		new->sm_bool.flags = CFR_OPTFLAG_SUPPRESS;
+		new->sm_bool.default_value = -1;
+	}
+}
+
+static const struct sm_object ec_kb_backlight = SM_DECLARE_ENUM({
+	.opt_name       = "ec_kb_backlight",
+	.ui_name        = "Keyboard Backlight Level At Boot",
+	.ui_helptext    = "Specify the level the keyboard backlight should be at boot."
+			" Set to 0% to disable the backlight.",
+	.default_value  = 50,
+	.values         = ec_backlight_values,
+}, WITH_CALLBACK(update_kb_backlight));
+
+#endif /* _CHROMEEC_CFR_H_ */

From 237944186ec362947a5161f260981f6eb8c86151 Mon Sep 17 00:00:00 2001
From: Terry Cheong <htcheong@chromium.org>
Date: Wed, 19 Nov 2025 17:43:40 +0800
Subject: [PATCH 2531/3886] mb/google/nissa/pujjolo: update verb table

Update the silence detection threshold based on the new verb table
provided by Realtek team.

BUG=b:446120613
TEST=reboot, open camera app, press shutter. There should be sound.

Change-Id: I7d27a38e4068a72f4fb04321e46f0266161572e1
Signed-off-by: Terry Cheong <htcheong@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90118
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 .../google/brya/variants/pujjolo/hda_verb.c   | 49 ++++++++++---------
 1 file changed, 27 insertions(+), 22 deletions(-)

diff --git a/src/mainboard/google/brya/variants/pujjolo/hda_verb.c b/src/mainboard/google/brya/variants/pujjolo/hda_verb.c
index ccbf6aacb4..ade39278b3 100644
--- a/src/mainboard/google/brya/variants/pujjolo/hda_verb.c
+++ b/src/mainboard/google/brya/variants/pujjolo/hda_verb.c
@@ -6,30 +6,35 @@ const u32 cim_verb_data[] = {
 	/* coreboot specific header */
 	0x10ec0257,	// Codec Vendor / Device ID: Realtek ALC257
 	0x10ec0257,	// Subsystem ID
-	0x00000012,	// Number of jacks (NID entries)
+	0x00000013,	// Number of jacks (NID entries)
 
-	AZALIA_RESET(0x1),
-	/* NID 0x01, HDA Codec Subsystem ID Verb table */
-	//AZALIA_SUBVENDOR(0, 0x10ec3a2c),
+	/* HDA Codec Subsystem ID Verb table */
+	AZALIA_SUBVENDOR(0, 0x00000000),
 
 	/* Pin Widget Verb Table */
-	/*
-	 * DMIC
-	 * Requirement is to use PCH DMIC. Hence,
-	 * commented out codec's Internal DMIC.
-	 * AZALIA_PIN_CFG(0, 0x12, 0x90A60130),
-	 * AZALIA_PIN_CFG(0, 0x13, 0x40000000),
-	 */
-	 AZALIA_PIN_CFG(0, 0x12, 0x40000000),
-	 AZALIA_PIN_CFG(0, 0x13, 0x411111F0),
-	 AZALIA_PIN_CFG(0, 0x14, 0x90170110),
-	 AZALIA_PIN_CFG(0, 0x18, 0x411111f0),
-	 AZALIA_PIN_CFG(0, 0x19, 0x04A11030),
-	 AZALIA_PIN_CFG(0, 0x1a, 0x411111f0),
-	 AZALIA_PIN_CFG(0, 0x1b, 0x411111f0),
-	 AZALIA_PIN_CFG(0, 0x1d, 0x40579A2D),
-	 AZALIA_PIN_CFG(0, 0x1e, 0x411111F0),
-	 AZALIA_PIN_CFG(0, 0x21, 0x04211020),
+	/* Widget node 0x01 */
+	AZALIA_RESET(0x1),
+	/* Pin widget 0x12 - DMIC */
+	AZALIA_PIN_CFG(0, 0x12, 0x40000000),
+	/* Pin widget 0x13 - DMIC */
+	AZALIA_PIN_CFG(0, 0x13, 0x411111F0),
+	/* Pin widget 0x14 - FRONT (Port-D) */
+	AZALIA_PIN_CFG(0, 0x14, 0x90170110),
+	/* Pin widget 0x18 - NPC */
+	AZALIA_PIN_CFG(0, 0x18, 0x411111F0),
+	/* Pin widget 0x19 - MIC2 (Port-F) */
+	AZALIA_PIN_CFG(0, 0x19, 0x04A11030),
+	/* Pin widget 0x1A - LINE1 (Port-C) */
+	AZALIA_PIN_CFG(0, 0x1a, 0x411111F0),
+	/* Pin widget 0x1B - LINE2 (Port-E) */
+	AZALIA_PIN_CFG(0, 0x1b, 0x411111F0),
+	/* Pin widget 0x1D - BEEP-IN */
+	AZALIA_PIN_CFG(0, 0x1d, 0x40579A2D),
+	/* Pin widget 0x1E - S/PDIF-OUT */
+	AZALIA_PIN_CFG(0, 0x1e, 0x411111F0),
+	/* Pin widget 0x21 - HP-OUT (Port-I) */
+	AZALIA_PIN_CFG(0, 0x21, 0x04211020),
+
 	//==========Widget node 0x20 - 0 :Hidden register SW reset
 	0x0205001A,
 	0x0204C003,
@@ -63,7 +68,7 @@ const u32 cim_verb_data[] = {
 	0x02050037,
 	0x0204FE15,
 	0x02050030,
-	0x02049004,
+	0x02041000,
 };
 
 const u32 pc_beep_verbs[] = {

From 0c18e7680ae83001b86039c6e6b82d8959d09aa5 Mon Sep 17 00:00:00 2001
From: Luca Lai <luca.lai@lcfc.corp-partner.google.com>
Date: Mon, 17 Nov 2025 20:33:09 +0800
Subject: [PATCH 2532/3886] mb/google/fatcat/var/ruby: Remove GPP_D16 and
 GPP_D17 in fw_config.c

Due to project requirements, GPP_D16 and GPP_D17 are not used. This has been confirmed by both the schematic and the LCFC hardware engineers. Therefore, they should be removed from the fw_config.

schematics: RUBY_EVT_0902_2112.pdf

BUG=b:452216678
TEST=Build FW and boot to OS, check DMIC function works.

Change-Id: I195ad082836d3b8a4fa79cbbc9e4bffaec745011
Signed-off-by: Luca Lai <luca.lai@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90071
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
---
 src/mainboard/google/fatcat/variants/ruby/fw_config.c | 6 ------
 1 file changed, 6 deletions(-)

diff --git a/src/mainboard/google/fatcat/variants/ruby/fw_config.c b/src/mainboard/google/fatcat/variants/ruby/fw_config.c
index d02976e026..396420fa6f 100644
--- a/src/mainboard/google/fatcat/variants/ruby/fw_config.c
+++ b/src/mainboard/google/fatcat/variants/ruby/fw_config.c
@@ -36,10 +36,6 @@ static const struct pad_config i2s_enable_pads[] = {
 	PAD_CFG_NF(GPP_S04, NONE, DEEP, NF5),
 	/* DMIC_CLK_A0 */
 	PAD_CFG_NF(GPP_S05, NONE, DEEP, NF5),
-	/* DMIC_CLK_A1 */
-	PAD_CFG_NF(GPP_D16, NONE, DEEP, NF3),
-	/* DMIC_DATA_A1 */
-	PAD_CFG_NF(GPP_D17, NONE, DEEP, NF3),
 };
 
 static const struct pad_config bt_i2s_enable_pads[] = {
@@ -94,8 +90,6 @@ static const struct pad_config audio_disable_pads[] = {
 	PAD_NC(GPP_D11, NONE),
 	PAD_NC(GPP_D12, NONE),
 	PAD_NC(GPP_D13, NONE),
-	PAD_NC(GPP_D16, NONE),
-	PAD_NC(GPP_D17, NONE),
 };
 
 void fw_config_configure_pre_mem_gpio(void)

From 541fd14fd95127072a7d5130a9ca404abf92fa9e Mon Sep 17 00:00:00 2001
From: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Date: Fri, 7 Nov 2025 10:25:55 +0800
Subject: [PATCH 2533/3886] mb/google/nissa/var/uldren: Increase Touch IC
 enable delay time
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

According to the datasheet and the LCD team’s response, increase Touch
IC enable delay time to resolve touch failure after resume.

BUG=b:458190286
TEST=1. Checked the touch screen power sequence waveform. The result is in b:458190286#comment4.
2. The touch feature works after resume.

Change-Id: Ia5a1d028721b1181d38730c23b27a80fa97e0dd7
Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89937
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
---
 src/mainboard/google/brya/variants/uldren/overridetree.cb | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/src/mainboard/google/brya/variants/uldren/overridetree.cb b/src/mainboard/google/brya/variants/uldren/overridetree.cb
index a2a0e26b81..d76c45404a 100644
--- a/src/mainboard/google/brya/variants/uldren/overridetree.cb
+++ b/src/mainboard/google/brya/variants/uldren/overridetree.cb
@@ -219,7 +219,7 @@ chip soc/intel/alderlake
 				register "generic.stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C6)"
 				register "generic.stop_delay_ms" = "130"
 				register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C0)"
-				register "generic.enable_delay_ms" = "1"
+				register "generic.enable_delay_ms" = "10"
 				register "generic.has_power_resource" = "1"
 				register "generic.use_gpio_for_status" = "true"
 				register "hid_desc_reg_offset" = "0x20"
@@ -239,7 +239,7 @@ chip soc/intel/alderlake
 				register "stop_delay_ms" = "280"
 				register "stop_off_delay_ms" = "2"
 				register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C0)"
-				register "enable_delay_ms" = "1"
+				register "enable_delay_ms" = "6"
 				register "has_power_resource" = "true"
 				register "use_gpio_for_status" = "true"
 				device i2c 10 on
@@ -311,7 +311,7 @@ chip soc/intel/alderlake
 				register "generic.stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C6)"
 				register "generic.stop_delay_ms" = "130"
 				register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C0)"
-				register "generic.enable_delay_ms" = "1"
+				register "generic.enable_delay_ms" = "10"
 				register "generic.has_power_resource" = "1"
 				register "generic.use_gpio_for_status" = "true"
 				register "hid_desc_reg_offset" = "0x20"

From a56a97d16707f2e00f6cf163c08053c0508d7d8a Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Wed, 19 Nov 2025 14:21:37 +0000
Subject: [PATCH 2534/3886] mb/starlabs/common/cfr: Adjust help text for S0IX

S3 now works on Windows, so don't recommend switching to S0IX.

Change-Id: I5f5dac0f2bf5eddbfef041b12a134bb70fdd7577
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90125
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/starlabs/common/include/common/cfr.h | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/src/mainboard/starlabs/common/include/common/cfr.h b/src/mainboard/starlabs/common/include/common/cfr.h
index 6566ce6e96..4a081c3c31 100644
--- a/src/mainboard/starlabs/common/include/common/cfr.h
+++ b/src/mainboard/starlabs/common/include/common/cfr.h
@@ -113,8 +113,7 @@ static const struct sm_object s0ix_enable = SM_DECLARE_BOOL({
 	.ui_name	= "Modern Standby (S0ix)",
 	.ui_helptext	= "Enabled: Use S0ix for device sleep.\n"
 			  "Disabled: Use ACPI S3 for device sleep.\n"
-			  "Requires Intel ME to be enabled.\n"
-			  "Recommended: Enabled when booting Windows, disabled otherwise.",
+			  "Requires Intel ME to be enabled.",
 	.default_value	= false,
 });
 

From cf2978f4b6c9372a37464e1c494ab3bb0100e6a7 Mon Sep 17 00:00:00 2001
From: Jian-Jia Su <jjsu@chromium.org>
Date: Wed, 16 Jul 2025 20:18:03 +0800
Subject: [PATCH 2535/3886] drivers/vpd: Search VPD info at 0x0 first

We used to put SMBIOS header and other data before VPD.  That is not the
case anymore. New device will write the VPD starting at 0 instead of
0x600.  Search VPD at 0x0 to support this.

TEST=build and boot google/geralt. VPD is found both at 0 and at 0x600.

Change-Id: I7072f7c646b6b55d11bc06dba5674828246fa1d0
Signed-off-by: Jian-Jia Su <jjsu@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88466
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
---
 src/drivers/vpd/vpd.c | 49 ++++++++++++++++++++-----------------------
 1 file changed, 23 insertions(+), 26 deletions(-)

diff --git a/src/drivers/vpd/vpd.c b/src/drivers/vpd/vpd.c
index 9e12967cf3..56b09263c3 100644
--- a/src/drivers/vpd/vpd.c
+++ b/src/drivers/vpd/vpd.c
@@ -43,6 +43,8 @@ static struct region_device ro_vpd, rw_vpd;
 /*
  * Initializes a region_device to represent the requested VPD 2.0 formatted
  * region on flash. On errors rdev->size will be set to 0.
+ * Check google_vpd_info at offset 0 first.  If not found, fall back to
+ * GOOGLE_VPD_2_0_OFFSET.
  */
 static void init_vpd_rdev(const char *fmap_name, struct region_device *rdev)
 {
@@ -57,36 +59,31 @@ static void init_vpd_rdev(const char *fmap_name, struct region_device *rdev)
 
 	size = region_device_sz(rdev);
 
-	if ((size < GOOGLE_VPD_2_0_OFFSET + sizeof(info)) ||
-	    rdev_chain(rdev, rdev, GOOGLE_VPD_2_0_OFFSET,
-			size - GOOGLE_VPD_2_0_OFFSET)) {
-		printk(BIOS_ERR, "%s: Too small (%d) for Google VPD 2.0.\n",
-		       __func__, size);
-		goto fail;
-	}
-
-	/* Try if we can find a google_vpd_info, otherwise read whole VPD. */
-	if (rdev_readat(rdev, &info, 0, sizeof(info)) != sizeof(info)) {
-		printk(BIOS_ERR, "Failed to read %s header.\n",
-		       fmap_name);
-		goto fail;
-	}
-
-	if (memcmp(info.header.magic, VPD_INFO_MAGIC, sizeof(info.header.magic))
-	    == 0) {
-		if (rdev_chain(rdev, rdev, sizeof(info), info.size)) {
-			printk(BIOS_ERR, "%s info size too large.\n",
+	size_t possible_offsets[] = {0x0, GOOGLE_VPD_2_0_OFFSET};
+	for (int i = 0; i < ARRAY_SIZE(possible_offsets); i++) {
+		size_t offset = possible_offsets[i];
+		if (size < offset + sizeof(info)) {
+			printk(BIOS_ERR,
+			       "%s: Too small (%d) for Google VPD 2.0.\n",
+			       __func__, size);
+			goto fail;
+		}
+		if (rdev_readat(rdev, &info, offset, sizeof(info)) != sizeof(info)) {
+			printk(BIOS_ERR, "Failed to read %s header.\n",
 			       fmap_name);
 			goto fail;
 		}
-	} else if (info.header.tlv.type == VPD_TYPE_TERMINATOR ||
-		   info.header.tlv.type == VPD_TYPE_IMPLICIT_TERMINATOR) {
-		printk(BIOS_WARNING, "%s is uninitialized or empty.\n",
-		       fmap_name);
-		goto fail;
+		if (memcmp(info.header.magic, VPD_INFO_MAGIC, sizeof(info.header.magic)) == 0) {
+			if (rdev_chain(rdev, rdev, offset + sizeof(info), info.size) == 0) {
+				return;
+			} else {
+				printk(BIOS_ERR, "%s info size too large.\n",
+				       fmap_name);
+				goto fail;
+			}
+		}
 	}
-
-	return;
+	printk(BIOS_WARNING, "%s is uninitialized.\n", fmap_name);
 
 fail:
 	memset(rdev, 0, sizeof(*rdev));

From 0145ebe847e6a3686b9b5f09ab3d5ee75555f93a Mon Sep 17 00:00:00 2001
From: Subrata Banik <subratabanik@google.com>
Date: Wed, 19 Nov 2025 12:36:43 +0530
Subject: [PATCH 2536/3886] commonlib: Add timestamps for Qualcomm QCLib and
 ARM TFA

This patch adds new timestamp IDs to track the execution flow within
the Qualcomm QCLib and the loading of the Secure OS (BL32) by the ARM
Trusted Firmware (TFA).

The following new IDs are introduced:
- TS_QUALCOMM_QCLIB_INIT_START (980)
- TS_QUALCOMM_QCLIB_INIT_END (981)
- TS_QUALCOMM_QCLIB_REINIT_START (982)
- TS_QUALCOMM_QCLIB_REINIT_END (983)
- TS_TFA_LOAD_BL32_START (998)
- TS_TFA_LOAD_BL32_END (999)

The reserved ID ranges are updated to accommodate these new vendor-
specific and architecture-specific timestamps:
- Intel/FSP range reduced from 950-989 to 950-980.
- A new range 980-990 is allocated for qualcomm/qclib.
- The Intel ME continued range is updated from 990-999 to 990-997.
- A new range 998-999 is allocated for ARM Trusted Firmware.

Change-Id: I904ac36862212a86961383dfe5e9b0f7ef0f02ea
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90111
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
---
 .../include/commonlib/timestamp_serialized.h  | 22 +++++++++++++++++--
 1 file changed, 20 insertions(+), 2 deletions(-)

diff --git a/src/commonlib/include/commonlib/timestamp_serialized.h b/src/commonlib/include/commonlib/timestamp_serialized.h
index db02ac7219..2a159f64b8 100644
--- a/src/commonlib/include/commonlib/timestamp_serialized.h
+++ b/src/commonlib/include/commonlib/timestamp_serialized.h
@@ -127,7 +127,7 @@ enum timestamp_id {
 	TS_CSE_FW_SYNC_START = 948,
 	TS_CSE_FW_SYNC_END = 949,
 
-	/* 950+ reserved for vendorcode extensions (950-989: intel/fsp) */
+	/* 950+ reserved for vendorcode extensions (950-980: intel/fsp) */
 	TS_FSP_MEMORY_INIT_START = 950,
 	TS_FSP_MEMORY_INIT_END = 951,
 	TS_FSP_TEMP_RAM_EXIT_START = 952,
@@ -147,11 +147,20 @@ enum timestamp_id {
 	TS_FSP_MEMORY_INIT_LOAD = 970,
 	TS_FSP_SILICON_INIT_LOAD = 971,
 
-	/* 990+ reserved for vendorcode extensions (990-999: Intel ME continued) */
+	/* 980+ reserved for vendorcode extensions (980-990: qualcomm/qclib) */
+	TS_QUALCOMM_QCLIB_INIT_START = 980,
+	TS_QUALCOMM_QCLIB_INIT_END = 981,
+	TS_QUALCOMM_QCLIB_REINIT_START = 982,
+	TS_QUALCOMM_QCLIB_REINIT_END = 983,
+
+	/* 990+ reserved for vendorcode extensions (990-997: Intel ME continued) */
 	TS_ME_ROM_START = 990,
 	TS_ISSE_DMU_LOAD_END = 991,
 	TS_ESE_LOAD_AUNIT_END = 992,
 
+	/* 998-999 reserved for ARM Trusted firmware) */
+	TS_TFA_LOAD_BL32_START = 998,
+	TS_TFA_LOAD_BL32_END = 999,
 	/* 1000+ reserved for payloads */
 
 	/* 1000-1200: Depthcharge */
@@ -353,11 +362,20 @@ static const struct timestamp_id_to_name {
 	TS_NAME_DEF(TS_FSP_MEMORY_INIT_LOAD, 0, "loading FSP-M"),
 	TS_NAME_DEF(TS_FSP_SILICON_INIT_LOAD, 0, "loading FSP-S"),
 
+	/* Qualcomm QCLib related timestamps */
+	TS_NAME_DEF(TS_QUALCOMM_QCLIB_INIT_START, 0, "Entering into QcLib"),
+	TS_NAME_DEF(TS_QUALCOMM_QCLIB_INIT_END, 0, "returning from QcLib"),
+	TS_NAME_DEF(TS_QUALCOMM_QCLIB_REINIT_START, 0, "Reentering from QcLib"),
+	TS_NAME_DEF(TS_QUALCOMM_QCLIB_REINIT_END, 0, "QcLib execution completed"),
+
 	/* Intel ME continued */
 	TS_NAME_DEF(TS_ME_ROM_START, 0, "CSME ROM started execution"),
 	TS_NAME_DEF(TS_ISSE_DMU_LOAD_END, 0, "Die Management Unit (DMU) load completed"),
 	TS_NAME_DEF(TS_ESE_LOAD_AUNIT_END, 0, "ESE completed AUnit loading"),
 
+	TS_NAME_DEF(TS_TFA_LOAD_BL32_START, 0, "BL32(secure_os) loading start"),
+	TS_NAME_DEF(TS_TFA_LOAD_BL32_END, 0, "BL32(secure_os) loading end"),
+
 	/* Depthcharge entry timestamp */
 	TS_NAME_DEF(TS_DC_START, 0, "depthcharge start"),
 

From d0177bd1024774e06c2bfc3420aab11f6ec621b2 Mon Sep 17 00:00:00 2001
From: Subrata Banik <subratabanik@google.com>
Date: Wed, 19 Nov 2025 12:40:00 +0530
Subject: [PATCH 2537/3886] soc/qualcomm: Add QCLib execution timestamps

Instrument the Qualcomm QCLib flow with timestamps to measure
execution time for both the initial loading/running phase and the
subsequent re-entry phase.

The timestamps are placed as follows:
- TS_QUALCOMM_QCLIB_INIT_START/END: Tracks the execution of
  `qclib_load_and_run()`.
- TS_QUALCOMM_QCLIB_REINIT_START/END: Tracks the execution of
  `qclib_rerun()`, which typically handles the AOP bring-up.

This instrumentation helps in profiling and optimizing the boot
performance on Qualcomm platforms.

Change-Id: I200ea5a78f4630000e80aed6dc38581af4d2e8aa
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90112
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
---
 src/soc/qualcomm/common/qclib.c | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/src/soc/qualcomm/common/qclib.c b/src/soc/qualcomm/common/qclib.c
index fa12ed9634..dd679964cd 100644
--- a/src/soc/qualcomm/common/qclib.c
+++ b/src/soc/qualcomm/common/qclib.c
@@ -17,6 +17,7 @@
 #include <soc/qclib_common.h>
 #include <soc/symbols_common.h>
 #include <string.h>
+#include <timestamp.h>
 #include <vb2_api.h>
 
 #define QCLIB_VERSION 0
@@ -247,6 +248,8 @@ void qclib_load_and_run(void)
 {
 	ssize_t data_size;
 
+	timestamp_add_now(TS_QUALCOMM_QCLIB_INIT_START);
+
 	/* zero ddr_information SRAM region, needs new data each boot */
 	memset(ddr_region, 0, sizeof(struct region));
 
@@ -328,6 +331,7 @@ void qclib_load_and_run(void)
 	assert((uintptr_t)_dram == region_offset(ddr_region) &&
 		region_sz(ddr_region) >= (u8 *)cbmem_top() - _dram);
 
+	timestamp_add_now(TS_QUALCOMM_QCLIB_INIT_END);
 	return;
 
 fail:
@@ -336,6 +340,8 @@ fail:
 
 void qclib_rerun(void)
 {
+	timestamp_add_now(TS_QUALCOMM_QCLIB_REINIT_START);
+
 	ssize_t data_size;
 
 	assert(prog_type(&qclib) == PROG_REFCODE)
@@ -372,6 +378,7 @@ void qclib_rerun(void)
 	printk(BIOS_DEBUG, "\n\n\nRe-enter QCLib to bring up AOP\n");
 	qclib_prepare_and_run();
 
+	timestamp_add_now(TS_QUALCOMM_QCLIB_REINIT_END);
 	return;
 
 fail:

From fec1032ee8589cb8e6bd666b2d8fbe8d5e3011d2 Mon Sep 17 00:00:00 2001
From: Subrata Banik <subratabanik@google.com>
Date: Wed, 19 Nov 2025 12:44:45 +0530
Subject: [PATCH 2538/3886] arch/arm64: Add timestamps for Secure OS (BL32)
 loading

Add boot timestamps to measure the duration of loading the Secure OS
(BL32) payload in the `run_bl31()` function.

The Secure OS is loaded if the Kconfig option
`CONFIG_ARM64_USE_SECURE_OS` is enabled. The new timestamps are:

- "TS_TFA_LOAD_BL32_START": Placed immediately before the Secure OS
   (BL32) loading process begins.
- "TS_TFA_LOAD_BL32_END": Placed after the BL32 entry point information
   is set up and before the BL33 parameters are finalized.

This instrumentation helps profile the boot time cost of the Trusted
Firmware-A (TFA) BL32 component loading.

Change-Id: I6ca74b8d4b11dfab4829f8bc5fbaa39ee5212137
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90113
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
---
 src/arch/arm64/bl31.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/src/arch/arm64/bl31.c b/src/arch/arm64/bl31.c
index a0402d7351..18f3eff056 100644
--- a/src/arch/arm64/bl31.c
+++ b/src/arch/arm64/bl31.c
@@ -9,7 +9,7 @@
 #include <cbmem.h>
 #include <console/console.h>
 #include <program_loading.h>
-
+#include <timestamp.h>
 #include <arm-trusted-firmware/include/export/common/bl_common_exp.h>
 
 static entry_point_info_t bl32_ep_info = {
@@ -81,6 +81,7 @@ void run_bl31(u64 payload_entry, u64 payload_arg0, u64 payload_spsr)
 	bl31_entry = prog_entry(&bl31);
 
 	if (CONFIG(ARM64_USE_SECURE_OS)) {
+		timestamp_add_now(TS_TFA_LOAD_BL32_START);
 		struct prog bl32 = PROG_INIT(PROG_BL32,
 					     CONFIG_CBFS_PREFIX"/secure_os");
 
@@ -96,6 +97,7 @@ void run_bl31(u64 payload_entry, u64 payload_arg0, u64 payload_spsr)
 		bl32_ep_info.spsr = SPSR_EXCEPTION_MASK |
 				get_eret_el(EL1, SPSR_USE_L);
 		bl33_params_node.next_params_info = &bl32_params_node;
+		timestamp_add_now(TS_TFA_LOAD_BL32_END);
 	}
 
 	bl33_ep_info.pc = payload_entry;

From af9d809823f3b6995e7610a6dda697e508c4f959 Mon Sep 17 00:00:00 2001
From: Subrata Banik <subratabanik@google.com>
Date: Thu, 20 Nov 2025 19:38:49 +0000
Subject: [PATCH 2539/3886] soc/qualcomm/x1p42100: Move coreboot stack to SSRAM

This patch relocates the coreboot stack from the BSRAM (Boot IMEM)
region to the SSRAM (Shared System RAM) region.

The 16K stack definition is moved from:

BSRAM region (0x14850000)

To:

SSRAM region (0x14680000)

This move is crucial because the BSRAM region is actively cleared during
the later stages of the IP loading process, which would wipe the stack
and lead to instability. Placing the stack in the persistent SSRAM
ensures it remains accessible throughout the early boot process.

BUG=BUG=b:456953373
TEST=Able to build google/quenbi w/ new stack region.

Change-Id: I59cd14fed2a5907bcbb8bed027dd5a55eb73e56d
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90137
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
---
 src/soc/qualcomm/x1p42100/memlayout.ld | 14 +++++++-------
 1 file changed, 7 insertions(+), 7 deletions(-)

diff --git a/src/soc/qualcomm/x1p42100/memlayout.ld b/src/soc/qualcomm/x1p42100/memlayout.ld
index b93a1e4c80..092bac0c9e 100644
--- a/src/soc/qualcomm/x1p42100/memlayout.ld
+++ b/src/soc/qualcomm/x1p42100/memlayout.ld
@@ -133,8 +133,6 @@
  * 0x14857000    +----------------------------------------------------------+      |
  *               |                    VBOOT2_WORK                           |      |
  * 0x14854000    +----------------------------------------------------------+      |
- *               |                       STACK                              |      |
- * 0x14850000    +----------------------------------------------------------+      |
  *               |             TTB (Translation Table Base)                 |      |
  * 0x14842000    +----------------------------------------------------------+      |
  *               |                     TIMESTAMP                            |      |
@@ -154,11 +152,13 @@
  *               |                ... Usable memory ...                     |      ^
  * 0x146AB000    +----------------------------------------------------------+      |
  *               |                     shared_imem                          |      |
- * 0x146AA000    +----------------------------------------------------------+    SSRAM
- *               |                ... Usable memory ...                     |      |
+ * 0x146AA000    +----------------------------------------------------------+      |
+ *               |                ... Usable memory ...                     |    SSRAM
  * 0x146A5000    +----------------------------------------------------------+      |
- *               |                       qcsdi                              |      v
- * 0x14699000    +----------------------------------------------------------+ <---------
+ *               |                       qcsdi                              |      |
+ * 0x14699000    +----------------------------------------------------------+      |
+ *               |                       STACK                              |      v
+ * 0x14680000    +----------------------------------------------------------+ <---------
  *               |         ... (Memory not mapped: Unavailable) ...         | XXXXXXXXX
  * 0x0B100000    +----------------------------------------------------------+ <---------
  *               |                ... Usable memory ...                     |      ^
@@ -180,6 +180,7 @@ SECTIONS
 	AOPSRAM_END(0x0B100000)
 
 	SSRAM_START(0x14680000)
+	STACK(0x14680000, 16K)
 	REGION(qcsdi, 0x14699000, 48K, 4K)
 	REGION(shared_imem, 0x146AA000, 0x1000, 4K)
 	SSRAM_END(0x146AC000)
@@ -191,7 +192,6 @@ SECTIONS
 	PRERAM_CBFS_CACHE(0x14828000, 103K)
 	TIMESTAMP(0x14841C00, 1K)
 	TTB(0x14842000, 56K)
-	STACK(0x14850000, 16K)
 	VBOOT2_WORK(0x14854000, 12K)
 	DMA_COHERENT(0x14857000, 8K)
 	REGION(qclib_serial_log, 0x1485B000, 4K, 4K)

From 931fa9c01d9fb191635f3b0435cb58b41f2e96f1 Mon Sep 17 00:00:00 2001
From: Subrata Banik <subratabanik@google.com>
Date: Tue, 18 Nov 2025 08:30:34 +0000
Subject: [PATCH 2540/3886] memlayout: Introduce PRERAM and POSTRAM DMA
 coherent regions

Refactor the DMA coherent memory region definition to support
stage-specific allocations.

In some boot flows, it is necessary to define separate DMA coherent
buffers for the early boot stage (e.g., romstage/bootblock) and the
later stage (ramstage). It allows the firmware to use only the memory
it needs, where it needs it, and prevents small-scale memory constraints
from crippling the overall boot flow.

The arch-specific, and now redundant, definitions of DMA_COHERENT are
removed from arm/memlayout.h and arm64/memlayout.h.

BUG=b:456953373
TEST=Able to build google/quenbi.

Change-Id: Ic32d14dda6cda0f731233dd3d86f3215c6af3637
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90049
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/arch/arm/include/arch/memlayout.h   |  5 -----
 src/arch/arm64/include/arch/memlayout.h |  5 -----
 src/include/memlayout.h                 | 26 +++++++++++++++++++++++++
 src/include/symbols.h                   |  2 ++
 4 files changed, 28 insertions(+), 10 deletions(-)

diff --git a/src/arch/arm/include/arch/memlayout.h b/src/arch/arm/include/arch/memlayout.h
index 408443f1ba..991cbb78c6 100644
--- a/src/arch/arm/include/arch/memlayout.h
+++ b/src/arch/arm/include/arch/memlayout.h
@@ -22,11 +22,6 @@
 	REGION(stack, addr, size, 8) \
 	_ = ASSERT(size >= 2K, "stack should be >= 2K, see toolchain.mk");
 
-#define DMA_COHERENT(addr, size) \
-	REGION(dma_coherent, addr, size, SUPERPAGE_SIZE) \
-	_ = ASSERT(size % SUPERPAGE_SIZE == 0, \
-		"DMA coherency buffer must fit exactly in full superpages!");
-
 #define FRAMEBUFFER(addr, size) \
 	REGION(framebuffer, addr, size, SUPERPAGE_SIZE) \
 	_ = ASSERT(size % SUPERPAGE_SIZE == 0, \
diff --git a/src/arch/arm64/include/arch/memlayout.h b/src/arch/arm64/include/arch/memlayout.h
index 69e4731a12..5c648b36f0 100644
--- a/src/arch/arm64/include/arch/memlayout.h
+++ b/src/arch/arm64/include/arch/memlayout.h
@@ -9,11 +9,6 @@
 	REGION(ttb, addr, size, 4K) \
 	_ = ASSERT(size % 4K == 0, "TTB size must be divisible by 4K!");
 
-#define DMA_COHERENT(addr, size) \
-	REGION(dma_coherent, addr, size, 4K) \
-	_ = ASSERT(size % 4K == 0, \
-		"DMA buffer should be multiple of smallest page size (4K)!");
-
 #define FRAMEBUFFER(addr, size) \
 	REGION(framebuffer, addr, size, 1M) \
 	_ = ASSERT(size % 1M == 0, \
diff --git a/src/include/memlayout.h b/src/include/memlayout.h
index 07addbbcde..85f2959434 100644
--- a/src/include/memlayout.h
+++ b/src/include/memlayout.h
@@ -101,6 +101,32 @@
 		ALIAS_REGION(postram_cbfs_cache, cbfs_cache)
 #endif
 
+/* Use either DMA_COHERENT (unified) or both (PRERAM|POSTRAM)_DMA_COHERENT */
+#define DMA_COHERENT(addr, size) \
+	REGION(dma_coherent, addr, size, 4K) \
+	_ = ASSERT(size % 4K == 0, \
+		"DMA buffer should be multiple of smallest page size (4K)!"); \
+	ALIAS_REGION(dma_coherent, preram_dma_coherent) \
+	ALIAS_REGION(dma_coherent, postram_dma_coherent)
+
+#if ENV_ROMSTAGE_OR_BEFORE
+	#define PRERAM_DMA_COHERENT(addr, size) \
+		REGION(preram_dma_coherent, addr, size, 4K) \
+		_ = ASSERT(size % 4K == 0, \
+		"Pre-RAM DMA buffer should be multiple of smallest page size (4K)!"); \
+		ALIAS_REGION(preram_dma_coherent, dma_coherent)
+	#define POSTRAM_DMA_COHERENT(addr, size) \
+		REGION(postram_dma_coherent, addr, size, 4K)
+#else
+	#define PRERAM_DMA_COHERENT(addr, size) \
+		REGION(preram_dma_coherent, addr, size, 4K)
+	#define POSTRAM_DMA_COHERENT(addr, size) \
+		REGION(postram_dma_coherent, addr, size, 4K) \
+		_ = ASSERT(size % 4K == 0, \
+		"Post-RAM DMA buffer should be multiple of smallest page size (4K)!"); \
+		ALIAS_REGION(postram_dma_coherent, dma_coherent)
+#endif
+
 /* Careful: 'INCLUDE <filename>' must always be at the end of the output line */
 #if ENV_DECOMPRESSOR
 	#define DECOMPRESSOR(addr, sz) \
diff --git a/src/include/symbols.h b/src/include/symbols.h
index ad8231c089..c46b6ff9ef 100644
--- a/src/include/symbols.h
+++ b/src/include/symbols.h
@@ -73,6 +73,8 @@ DECLARE_REGION(ramstage)
 DECLARE_REGION(pagetables)
 DECLARE_REGION(ttb)
 DECLARE_OPTIONAL_REGION(ttb_subtables)
+DECLARE_OPTIONAL_REGION(preram_dma_coherent)
+DECLARE_OPTIONAL_REGION(postram_dma_coherent)
 DECLARE_REGION(dma_coherent)
 DECLARE_REGION(soc_registers)
 DECLARE_OPTIONAL_REGION(framebuffer)

From 958099b11422caed6ccf4043bd57799b55ac480d Mon Sep 17 00:00:00 2001
From: Subrata Banik <subratabanik@google.com>
Date: Tue, 18 Nov 2025 16:49:37 +0000
Subject: [PATCH 2541/3886] soc/qualcomm: Map the post-RAM DMA coherent buffer

The MMU configuration in qc_mmu_dram_config_post_dram_init() needs to
include the memory region allocated for DMA coherent buffers.

Map the `postram_dma_coherent` region as UNCACHED_RAM to ensure memory
writes bypass the CPU cache hierarchy.

The mapping is only configured if the `_postram_dma_coherent` address
is different from `_preram_dma_coherent` address aka migration of the
region.

This is necessary for DMA operations that occur after DRAM is
initialized.

BUG=b:456953373
TEST=Able to build google/quenbi.

Change-Id: If5f625ad74f4f6ea244c8b377543be3666122cea
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90050
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
---
 src/soc/qualcomm/common/mmu.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/src/soc/qualcomm/common/mmu.c b/src/soc/qualcomm/common/mmu.c
index ff8d5dc98e..b589d966a9 100644
--- a/src/soc/qualcomm/common/mmu.c
+++ b/src/soc/qualcomm/common/mmu.c
@@ -73,4 +73,7 @@ void qc_mmu_dram_config_post_dram_init(size_t ddr_size)
 							CACHED_RAM);
 	mmu_config_range((void *)_aop_data_ram, REGION_SIZE(aop_data_ram),
 							CACHED_RAM);
+	if (_preram_dma_coherent != _postram_dma_coherent)
+		mmu_config_range((void *)_postram_dma_coherent, REGION_SIZE(postram_dma_coherent),
+							UNCACHED_RAM);
 }

From d277b353072bb71ad83103dc96cd58a7bbe39d67 Mon Sep 17 00:00:00 2001
From: Subrata Banik <subratabanik@google.com>
Date: Tue, 18 Nov 2025 17:06:49 +0000
Subject: [PATCH 2542/3886] soc/qualcomm/x1p42100: Relocate ddr_information and
 watchdog tombstone

This commit relocates the following two regions:
1. `ddr_information`
2. `WATCHDOG_TOMBSTONE`

Previously, these regions were allocated in a higher address range
(starting near 0x14800000).

The regions are now defined within SSRAM`:

- `ddr_information` is moved from `0x14860000` to `0x146ABFE8`.
- `WATCHDOG_TOMBSTONE` is moved from `0x14818FFC` to `0x146ABFFC`.

This memory map change updates the linker script's visual diagram and
section definitions to reflect the new memory layout.

BUG=b:456953373
TEST=Able to build google/quenbi.

Change-Id: I4545722a836ec472e8086d1a941515cb3956c763
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90052
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/soc/qualcomm/x1p42100/memlayout.ld | 16 ++++++++--------
 1 file changed, 8 insertions(+), 8 deletions(-)

diff --git a/src/soc/qualcomm/x1p42100/memlayout.ld b/src/soc/qualcomm/x1p42100/memlayout.ld
index 092bac0c9e..5bf877e616 100644
--- a/src/soc/qualcomm/x1p42100/memlayout.ld
+++ b/src/soc/qualcomm/x1p42100/memlayout.ld
@@ -120,8 +120,6 @@
  *               |                ... Usable memory ...                     |      |
  * 0x14860C00    +----------------------------------------------------------+      |
  *               |                     FMAP_CACHE                           |      |
- * 0x14860400    +----------------------------------------------------------+      |
- *               |                   ddr_information                        |      |
  * 0x14860000    +----------------------------------------------------------+    BSRAM
  *               |                    CBFS_MCACHE                           |      |
  * 0x1485C000    +----------------------------------------------------------+      |
@@ -141,16 +139,18 @@
  * 0x14828000    +----------------------------------------------------------+      |
  *               |                     BOOTBLOCK                            |      |
  * 0x14819000    +----------------------------------------------------------+      |
- *               |                 WATCHDOG_TOMBSTONE                       |      |
- * 0x14818FFC    +----------------------------------------------------------+      |
  *               |                ... Usable memory ...                     |      |
  * 0x14815000    +----------------------------------------------------------+      |
  *               |                   pbl_timestamps                         |      v
  * 0x14800000    +----------------------------------------------------------+ <---------
  *               |              ... (Large Address Gap) ...                 |
+ *               +----------------------------------------------------------+
+ *               |                ... Usable memory ...                     |
  * 0x146AC000    +----------------------------------------------------------+ <---------
- *               |                ... Usable memory ...                     |      ^
- * 0x146AB000    +----------------------------------------------------------+      |
+ *               |                 WATCHDOG_TOMBSTONE                       |      ^
+ * 0x146ABFFC    +----------------------------------------------------------+      |
+ *               |                   ddr_information                        |      |
+ * 0x146ABFE8    +----------------------------------------------------------+      |
  *               |                     shared_imem                          |      |
  * 0x146AA000    +----------------------------------------------------------+      |
  *               |                ... Usable memory ...                     |    SSRAM
@@ -183,11 +183,12 @@ SECTIONS
 	STACK(0x14680000, 16K)
 	REGION(qcsdi, 0x14699000, 48K, 4K)
 	REGION(shared_imem, 0x146AA000, 0x1000, 4K)
+	REGION(ddr_information, 0x146ABFE8, 16, 8)
+	WATCHDOG_TOMBSTONE(0x146ABFFC, 4)
 	SSRAM_END(0x146AC000)
 
 	BSRAM_START(0x14800000)
 	REGION(pbl_timestamps, 0x14800000, 84K, 4K)
-	WATCHDOG_TOMBSTONE(0x14818FFC, 4)
 	BOOTBLOCK(0x14819000, 60K)
 	PRERAM_CBFS_CACHE(0x14828000, 103K)
 	TIMESTAMP(0x14841C00, 1K)
@@ -196,7 +197,6 @@ SECTIONS
 	DMA_COHERENT(0x14857000, 8K)
 	REGION(qclib_serial_log, 0x1485B000, 4K, 4K)
 	CBFS_MCACHE(0x1485C000,16K)
-	REGION(ddr_information, 0x14860000, 1K, 1K)
 	FMAP_CACHE(0x14860400, 2K)
 	REGION(dcb, 0x14862000, 56K, 4K)
 	REGION(dtb, 0x14870000, 32K, 4K)

From 7521f3ea830d814bca062ac11037fbca47e9cc42 Mon Sep 17 00:00:00 2001
From: Subrata Banik <subratabanik@google.com>
Date: Tue, 18 Nov 2025 17:35:10 +0000
Subject: [PATCH 2543/3886] soc/qualcomm/x1p42100: Define pre and post-RAM DMA
 coherent regions

This commit updates the linker script to properly define and name the
DMA coherent memory regions used before and after DRAM initialization.

1. Rename Pre-RAM DMA Region:
The existing `DMA_COHERENT` region allocated in BSRAM at `0x14857000` is
renamed to `PRERAM_DMA_COHERENT`. This aligns the linker script with the
code changes (in `mmu.c`) which use the more specific name for the early
boot DMA buffer.

2. Add Post-RAM DMA Region:
A new region, `POSTRAM_DMA_COHERENT`, is defined at the very start of
DRAM (`0x80000000`) with an 8KB size. This region is intended for
general-purpose DMA operations that occur after DRAM is active,
ensuring a reserved, known, and uncached region for peripherals.

The memory map diagram comments are also updated to reflect these new
region names.

BUG=b:456953373
TEST=Able to build and boot google/quenbi.

Change-Id: I6fb4b9bf3425b311169ac43e1997f6574b571e00
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90098
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
---
 src/soc/qualcomm/x1p42100/memlayout.ld | 7 ++++---
 1 file changed, 4 insertions(+), 3 deletions(-)

diff --git a/src/soc/qualcomm/x1p42100/memlayout.ld b/src/soc/qualcomm/x1p42100/memlayout.ld
index 5bf877e616..c93ed62462 100644
--- a/src/soc/qualcomm/x1p42100/memlayout.ld
+++ b/src/soc/qualcomm/x1p42100/memlayout.ld
@@ -81,7 +81,7 @@
  * 0x80E00000    +----------------------------------------------------------+      |        |
  *               |                      dram_ncc                            |      |        |
  * 0x80A00000    +----------------------------------------------------------+      |        |
- *               |                ... Usable memory ...                     |      v        v
+ *               |              postram_dma_coherent_dram                   |      v        v
  * 0x80000000    +----------------------------------------------------------+ <--------------
  *               |         ... (Memory not mapped: Unavailable) ...         | XXXXXXXXX
  * 0x24060000    +----------------------------------------------------------+ <---------
@@ -127,7 +127,7 @@
  * 0x1485B000    +----------------------------------------------------------+      |
  *               |                ... Usable memory ...                     |      |
  * 0x14859000    +----------------------------------------------------------+      |
- *               |                    DMA_COHERENT                          |      |
+ *               |               preram_dma_coherent_dram                   |      |
  * 0x14857000    +----------------------------------------------------------+      |
  *               |                    VBOOT2_WORK                           |      |
  * 0x14854000    +----------------------------------------------------------+      |
@@ -194,7 +194,7 @@ SECTIONS
 	TIMESTAMP(0x14841C00, 1K)
 	TTB(0x14842000, 56K)
 	VBOOT2_WORK(0x14854000, 12K)
-	DMA_COHERENT(0x14857000, 8K)
+	PRERAM_DMA_COHERENT(0x14857000, 8K)
 	REGION(qclib_serial_log, 0x1485B000, 4K, 4K)
 	CBFS_MCACHE(0x1485C000,16K)
 	FMAP_CACHE(0x14860400, 2K)
@@ -214,6 +214,7 @@ SECTIONS
 	REGION(shrm, 0x24040000, 128K , 4K)
 
 	DRAM_START(0x80000000)
+	POSTRAM_DMA_COHERENT(0x80000000, 8K)
 	REGION(dram_ncc, 0x80A00000, 0x400000, 4K)
 	REGION(dram_cpucp, 0x80E00000, 0x7A0000, 4K)
 

From d03799ec3c3448bacd068ce9a2f8b2c524918595 Mon Sep 17 00:00:00 2001
From: Jeff Xu <jeffxu@google.com>
Date: Mon, 17 Nov 2025 20:26:05 +0000
Subject: [PATCH 2544/3886] soc/mediatek/mt8196: Configure registers and
 parameters required for MTE

To support Memory Tagging Extension (MTE), configure booker
(custom CI-700) registers related to MTE to set up MTE tag address.

According to CI-700 documentation, the por_mtu_tag_addr_base register is
only accessible by Secure accesses. Therefore these registers are now
configured in coreboot ramstage before passing to payloads.

BRANCH=rauru
BUG=b:438666196
TEST=manual test

Change-Id: I0d98cfee3e208a559116f84362528f005ea6f2c8
Signed-off-by: Jeff Xu <jeffxu@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90141
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
---
 src/soc/mediatek/mt8196/Makefile.mk          |  1 +
 src/soc/mediatek/mt8196/booker.c             | 45 ++++++++++++++++++++
 src/soc/mediatek/mt8196/include/soc/booker.h |  5 +++
 src/soc/mediatek/mt8196/soc.c                |  7 +++
 4 files changed, 58 insertions(+)

diff --git a/src/soc/mediatek/mt8196/Makefile.mk b/src/soc/mediatek/mt8196/Makefile.mk
index e4bb1bd523..a4926056aa 100644
--- a/src/soc/mediatek/mt8196/Makefile.mk
+++ b/src/soc/mediatek/mt8196/Makefile.mk
@@ -54,6 +54,7 @@ romstage-y += ../common/thermal.c thermal.c
 romstage-y += ../common/thermal_sram.c thermal_sram.c
 
 ramstage-$(CONFIG_ARM64_USE_ARM_TRUSTED_FIRMWARE) += ../common/bl31.c
+ramstage-y += booker.c
 ramstage-y += dcc.c
 ramstage-y += ddp.c
 ramstage-y += ../common/display.c
diff --git a/src/soc/mediatek/mt8196/booker.c b/src/soc/mediatek/mt8196/booker.c
index 020af9ad0b..c571734f62 100644
--- a/src/soc/mediatek/mt8196/booker.c
+++ b/src/soc/mediatek/mt8196/booker.c
@@ -13,8 +13,31 @@
 #define INSTANCE1_SBSX_POR_SBSX_CFG_CTL	(0x0A800000 + POR_SBSX_CFG_CTL_OFFSET)
 #define INSTANCE2_SBSX_POR_SBSX_CFG_CTL	(0x0B000000 + POR_SBSX_CFG_CTL_OFFSET)
 #define INSTANCE3_SBSX_POR_SBSX_CFG_CTL	(0x0B800000 + POR_SBSX_CFG_CTL_OFFSET)
+
+#define POR_MTU_BASE			0x790000
+#define POR_MTU_AUX_CTL_OFFSET		(POR_MTU_BASE + 0x0A08)
+#define POR_MTU_TAG_ADDR_CTL_OFFSET	(POR_MTU_BASE + 0x0A40)
+#define POR_MTU_TAG_ADDR_BASE_OFFSET	(POR_MTU_BASE + 0x0A48)
+#define POR_MTU_TAG_ADDR_SHUTTER0_OFFSET	(POR_MTU_BASE + 0x0A50)
+#define POR_MTU_TAG_ADDR_SHUTTER1_OFFSET	(POR_MTU_BASE + 0x0A58)
+#define POR_MTU_TAG_ADDR_SHUTTER2_OFFSET	(POR_MTU_BASE + 0x0A60)
+
+#define BIT_DISABLE_BOOKER_TAG		BIT(0)
 #define BIT_DISABLE_CMO_PROP		BIT(3)
 
+#define MTU_TYPE_MODE_0			0x5
+#define MTU_SHUTTER0_SETTING		0x2222222222222200ULL
+#define MTU_SHUTTER1_SETTING		0x2222222222222222ULL
+#define MTU_SHUTTER2_SETTING		0x0000000002222222ULL
+
+/* Booker instance base addresses */
+static const uint32_t booker_base[] = {
+	0x0A000000,
+	0x0A800000,
+	0x0B000000,
+	0x0B800000,
+};
+
 /*
  * Configure booker and disable HN-D coherence request to avoid
  * receiving NDE(Non-data Error) before MMU enabled.
@@ -36,3 +59,25 @@ void booker_init(void)
 	       __func__,
 	       read32p(REG_READ_ONLY_HASH_VALUE));
 }
+
+void booker_mte_init(uint64_t mte_tag_addr)
+{
+	int i;
+
+	printk(BIOS_DEBUG, "%s: MTE tag addr %#llx\n", __func__, mte_tag_addr);
+
+	/* Setting MTU TAG */
+	for (i = 0; i < ARRAY_SIZE(booker_base); i++) {
+		write64p(booker_base[i] + POR_MTU_TAG_ADDR_CTL_OFFSET, MTU_TYPE_MODE_0);
+		write64p(booker_base[i] + POR_MTU_TAG_ADDR_BASE_OFFSET, mte_tag_addr);
+		write64p(booker_base[i] + POR_MTU_TAG_ADDR_SHUTTER0_OFFSET,
+			 MTU_SHUTTER0_SETTING);
+		write64p(booker_base[i] + POR_MTU_TAG_ADDR_SHUTTER1_OFFSET,
+			 MTU_SHUTTER1_SETTING);
+		write64p(booker_base[i] + POR_MTU_TAG_ADDR_SHUTTER2_OFFSET,
+			 MTU_SHUTTER2_SETTING);
+		setbits64p(booker_base[i] + POR_MTU_AUX_CTL_OFFSET, BIT_DISABLE_BOOKER_TAG);
+	}
+	dsb();
+	isb();
+}
diff --git a/src/soc/mediatek/mt8196/include/soc/booker.h b/src/soc/mediatek/mt8196/include/soc/booker.h
index a9f8d6375c..25c2d140af 100644
--- a/src/soc/mediatek/mt8196/include/soc/booker.h
+++ b/src/soc/mediatek/mt8196/include/soc/booker.h
@@ -3,6 +3,11 @@
 #ifndef SOC_MEDIATEK_MT8196_BOOKER_H
 #define SOC_MEDIATEK_MT8196_BOOKER_H
 
+#include <stdint.h>
+
+#define MTE_TAG_ADDR 0x460E80000
+
 void booker_init(void);
+void booker_mte_init(uint64_t mte_tag_addr);
 
 #endif
diff --git a/src/soc/mediatek/mt8196/soc.c b/src/soc/mediatek/mt8196/soc.c
index 16271643ea..1fbe09025f 100644
--- a/src/soc/mediatek/mt8196/soc.c
+++ b/src/soc/mediatek/mt8196/soc.c
@@ -3,6 +3,7 @@
 #include <bootmem.h>
 #include <device/device.h>
 #include <device/pci.h>
+#include <soc/booker.h>
 #include <soc/dcc.h>
 #include <soc/dramc_info.h>
 #include <soc/emi.h>
@@ -51,6 +52,12 @@ static void soc_init(struct device *dev)
 	gpueb_init();
 	mcupm_init();
 	mt6685_init_pmif_arb();
+	/*
+	 * According to CI-700 documentation:
+	 * Registers are only accessible by Secure accesses. Writes to them must occur prior to
+	 * the first non-configuration access targeting the device.
+	 */
+	booker_mte_init(MTE_TAG_ADDR);
 }
 
 static struct device_operations soc_ops = {

From bae3e026627d4d9ca3daf27aae1a78fdd4f6e266 Mon Sep 17 00:00:00 2001
From: Jakub Czapiga <czapiga@google.com>
Date: Wed, 19 Nov 2025 10:00:01 +0000
Subject: [PATCH 2545/3886] include: commonlib: Move memory_info and dimm_info
 to commonlib

memory_info with dimm_info entries is available as CBMEM_ID_MEMINFO.
Moving the structures definitions to the commonlib allows the payloads
to easily access the memory information.

BUG=b:450374306
TEST=Build and boot Google/Brya

Change-Id: I25e788d5afd668e93f8ea60adaefb7b8b5d5ec28
Signed-off-by: Jakub Czapiga <czapiga@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90119
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
---
 src/commonlib/include/commonlib/memory_info.h | 126 ++++++++++++++++++
 src/include/memory_info.h                     | 120 +----------------
 2 files changed, 127 insertions(+), 119 deletions(-)
 create mode 100644 src/commonlib/include/commonlib/memory_info.h

diff --git a/src/commonlib/include/commonlib/memory_info.h b/src/commonlib/include/commonlib/memory_info.h
new file mode 100644
index 0000000000..5465b1bccf
--- /dev/null
+++ b/src/commonlib/include/commonlib/memory_info.h
@@ -0,0 +1,126 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef _COMMONLIB_MEMORY_INFO_H_
+#define _COMMONLIB_MEMORY_INFO_H_
+
+#include <stdint.h>
+
+#define DIMM_INFO_SERIAL_SIZE		4
+#define DIMM_INFO_PART_NUMBER_SIZE	33
+#define DIMM_INFO_TOTAL			64
+
+/**
+ * If this table is filled and put in CBMEM,
+ * then these info in CBMEM will be used to generate smbios type 17 table
+ *
+ * Values are specified according to the JEDEC SPD Standard.
+ */
+struct dimm_info {
+	/*
+	 * Size of the module in MiB.
+	 */
+	uint32_t dimm_size;
+	/*
+	 * SMBIOS (not SPD) device type.
+	 *
+	 * See the smbios.h smbios_memory_type enum.
+	 */
+	uint16_t ddr_type;
+	/*
+	 * ddr_frequency is deprecated.
+	 * Use max_speed_mts and configured_speed_mts instead.
+	 */
+	uint16_t ddr_frequency;
+	uint8_t rank_per_dimm;
+	/*
+	 * Socket-ID
+	 */
+	uint8_t soc_num;
+	/*
+	 * Memory-Controller-ID
+	 */
+	uint8_t ctrlr_num;
+	/*
+	 * Channel-ID
+	 */
+	uint8_t channel_num;
+	/*
+	 * DIMM-ID
+	 */
+	uint8_t dimm_num;
+	uint8_t bank_locator;
+	/*
+	 * SPD serial number.
+	 */
+	uint8_t serial[DIMM_INFO_SERIAL_SIZE];
+	/*
+	 * The last byte is '\0' for the end of string
+	 *
+	 * Must contain only printable ASCII.
+	 */
+	uint8_t module_part_number[DIMM_INFO_PART_NUMBER_SIZE];
+	/*
+	 * SPD Manufacturer ID
+	 */
+	uint16_t mod_id;
+	/*
+	 * SPD Module Type.
+	 *
+	 * See spd.h for valid values.
+	 *
+	 * e.g., SPD_RDIMM, SPD_SODIMM, SPD_MICRO_DIMM
+	 */
+	uint8_t mod_type;
+	/*
+	 * SPD bus width.
+	 *
+	 * Bits 0 - 2 encode the primary bus width:
+	 *   0b000 = 8 bit width
+	 *   0b001 = 16 bit width
+	 *   0b010 = 32 bit width
+	 *   0b011 = 64 bit width
+	 *
+	 * Bits 3 - 4 encode the extension bits (ECC):
+	 *   0b00 = 0 extension bits
+	 *   0b01 = 8 bit of ECC
+	 *
+	 * e.g.,
+	 *   64 bit bus with 8 bits of ECC (72 bits total): 0b1011
+	 *   64 bit bus with 0 bits of ECC (64 bits total): 0b0011
+	 *
+	 * See the smbios.h smbios_memory_bus_width enum.
+	 */
+	uint8_t bus_width;
+	/*
+	 * Voltage Level
+	 */
+	uint16_t vdd_voltage;
+	/*
+	 * Max speed in MT/s
+	 * If the value is 0, ddr_frequency should be used instead.
+	 */
+	uint16_t max_speed_mts;
+	/*
+	 * Configured speed in MT/s
+	 * If the value is 0, ddr_frequency should be used instead.
+	 */
+	uint16_t configured_speed_mts;
+} __packed;
+
+struct memory_info {
+	/*
+	 * SMBIOS error correction type.
+	 * See the smbios.h smbios_memory_array_ecc enum.
+	 */
+	uint8_t ecc_type;
+	/* Maximum capacity the DRAM controller/mainboard supports */
+	uint32_t max_capacity_mib;
+	/* Maximum number of DIMMs the DRAM controller/mainboard supports */
+	uint16_t number_of_devices;
+
+	/* active DIMM configuration */
+	uint8_t dimm_cnt;
+	struct dimm_info dimm[DIMM_INFO_TOTAL];
+} __packed;
+
+#endif /* _COMMONLIB_MEMORY_INFO_H_ */
diff --git a/src/include/memory_info.h b/src/include/memory_info.h
index 74aa2a7b88..e2c0b3ae97 100644
--- a/src/include/memory_info.h
+++ b/src/include/memory_info.h
@@ -4,125 +4,7 @@
 #ifndef _MEMORY_INFO_H_
 #define _MEMORY_INFO_H_
 
-#include <stdint.h>
-
-#define DIMM_INFO_SERIAL_SIZE		4
-#define DIMM_INFO_PART_NUMBER_SIZE	33
-#define DIMM_INFO_TOTAL			64
-
-/**
- * If this table is filled and put in CBMEM,
- * then these info in CBMEM will be used to generate smbios type 17 table
- *
- * Values are specified according to the JEDEC SPD Standard.
- */
-struct dimm_info {
-	/*
-	 * Size of the module in MiB.
-	 */
-	uint32_t dimm_size;
-	/*
-	 * SMBIOS (not SPD) device type.
-	 *
-	 * See the smbios.h smbios_memory_type enum.
-	 */
-	uint16_t ddr_type;
-	/*
-	 * ddr_frequency is deprecated.
-	 * Use max_speed_mts and configured_speed_mts instead.
-	 */
-	uint16_t ddr_frequency;
-	uint8_t rank_per_dimm;
-	/*
-	 * Socket-ID
-	 */
-	uint8_t soc_num;
-	/*
-	 * Memory-Controller-ID
-	 */
-	uint8_t ctrlr_num;
-	/*
-	 * Channel-ID
-	 */
-	uint8_t channel_num;
-	/*
-	 * DIMM-ID
-	 */
-	uint8_t dimm_num;
-	uint8_t bank_locator;
-	/*
-	 * SPD serial number.
-	 */
-	uint8_t serial[DIMM_INFO_SERIAL_SIZE];
-	/*
-	 * The last byte is '\0' for the end of string
-	 *
-	 * Must contain only printable ASCII.
-	 */
-	uint8_t module_part_number[DIMM_INFO_PART_NUMBER_SIZE];
-	/*
-	 * SPD Manufacturer ID
-	 */
-	uint16_t mod_id;
-	/*
-	 * SPD Module Type.
-	 *
-	 * See spd.h for valid values.
-	 *
-	 * e.g., SPD_RDIMM, SPD_SODIMM, SPD_MICRO_DIMM
-	 */
-	uint8_t mod_type;
-	/*
-	 * SPD bus width.
-	 *
-	 * Bits 0 - 2 encode the primary bus width:
-	 *   0b000 = 8 bit width
-	 *   0b001 = 16 bit width
-	 *   0b010 = 32 bit width
-	 *   0b011 = 64 bit width
-	 *
-	 * Bits 3 - 4 encode the extension bits (ECC):
-	 *   0b00 = 0 extension bits
-	 *   0b01 = 8 bit of ECC
-	 *
-	 * e.g.,
-	 *   64 bit bus with 8 bits of ECC (72 bits total): 0b1011
-	 *   64 bit bus with 0 bits of ECC (64 bits total): 0b0011
-	 *
-	 * See the smbios.h smbios_memory_bus_width enum.
-	 */
-	uint8_t bus_width;
-	/*
-	 * Voltage Level
-	 */
-	uint16_t vdd_voltage;
-	/*
-	 * Max speed in MT/s
-	 * If the value is 0, ddr_frequency should be used instead.
-	 */
-	uint16_t max_speed_mts;
-	/*
-	 * Configured speed in MT/s
-	 * If the value is 0, ddr_frequency should be used instead.
-	 */
-	uint16_t configured_speed_mts;
-} __packed;
-
-struct memory_info {
-	/*
-	 * SMBIOS error correction type.
-	 * See the smbios.h smbios_memory_array_ecc enum.
-	 */
-	uint8_t ecc_type;
-	/* Maximum capacity the DRAM controller/mainboard supports */
-	uint32_t max_capacity_mib;
-	/* Maximum number of DIMMs the DRAM controller/mainboard supports */
-	uint16_t number_of_devices;
-
-	/* active DIMM configuration */
-	uint8_t dimm_cnt;
-	struct dimm_info dimm[DIMM_INFO_TOTAL];
-} __packed;
+#include <commonlib/memory_info.h>
 
 /*
  * mainboard_get_dram_part_num returns a DRAM part number override string

From fd603e510256b93d3f9625f418d6303b3436d967 Mon Sep 17 00:00:00 2001
From: Jakub Czapiga <czapiga@google.com>
Date: Wed, 19 Nov 2025 10:10:13 +0000
Subject: [PATCH 2546/3886] libpayload: Add CBMEM_ID_MEMINFO to sysinfo

BUG=b:450374306
TEST=Build and boot Google/Brya

Change-Id: I16d51e9aab7ec3d7430a1e6b6467007a3669d083
Signed-off-by: Jakub Czapiga <czapiga@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90120
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
---
 payloads/libpayload/include/sysinfo.h | 6 ++++++
 payloads/libpayload/libc/coreboot.c   | 3 +++
 2 files changed, 9 insertions(+)

diff --git a/payloads/libpayload/include/sysinfo.h b/payloads/libpayload/include/sysinfo.h
index 7c47074aa1..f18ad62308 100644
--- a/payloads/libpayload/include/sysinfo.h
+++ b/payloads/libpayload/include/sysinfo.h
@@ -45,6 +45,10 @@
 
 #include <coreboot_tables.h>
 
+#if CONFIG(LP_GPL)
+#include <commonlib/memory_info.h>
+#endif
+
 /*
  * This is a collection of information and pointers gathered
  * mostly from the coreboot table.
@@ -174,6 +178,8 @@ struct sysinfo_t {
 	uintptr_t pvmfw;
 	uint32_t pvmfw_size;
 	enum boot_mode_t boot_mode;
+
+	uintptr_t memory_info;
 };
 
 extern struct sysinfo_t lib_sysinfo;
diff --git a/payloads/libpayload/libc/coreboot.c b/payloads/libpayload/libc/coreboot.c
index 11703ee178..b1be37c19e 100644
--- a/payloads/libpayload/libc/coreboot.c
+++ b/payloads/libpayload/libc/coreboot.c
@@ -273,6 +273,9 @@ static void cb_parse_cbmem_entry(void *ptr, struct sysinfo_t *info)
 		info->pvmfw = cbmem_entry->address;
 		info->pvmfw_size = cbmem_entry->entry_size;
 		break;
+	case CBMEM_ID_MEMINFO:
+		info->memory_info = cbmem_entry->address;
+		break;
 	default:
 		break;
 	}

From a7efa40e39e989e1c7bbb556d61274f443f7b5b3 Mon Sep 17 00:00:00 2001
From: Fabio Baltieri <fabiobaltieri@google.com>
Date: Wed, 5 Nov 2025 10:41:11 +0000
Subject: [PATCH 2547/3886] acpigen_ps2_keybd: map KEY_HOMEPAGE to 0xaa
 scancode and TK_HOME

Chromium OS EC has some specialized handling of chromebook specific
function keys on the keyboard top row, these have a function specific
action key code that is exposed to the OS and used to map their
position, and also a specific scancode that has to be mapped to a Linux
event code.

This adds the necessary mapping for KEY_HOMEPAGE, which is going to be
used in new devices.

The scancode picked is 0xe012, which maps to e02a or 0xaa, the
corresponding EC CL is:

https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/7118961

BUG=b:446007724
TEST=flashed and tested on a brox board with chromiumos, checked the
code with evtest

Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
Change-Id: I395721a342f507453dae19373df2f189ac1b5dac
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90024
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
---
 src/acpi/acpigen_ps2_keybd.c         | 1 +
 src/ec/google/chromeec/ec_acpi.c     | 1 +
 src/ec/google/chromeec/ec_commands.h | 1 +
 src/include/acpi/acpigen_ps2_keybd.h | 1 +
 4 files changed, 4 insertions(+)

diff --git a/src/acpi/acpigen_ps2_keybd.c b/src/acpi/acpigen_ps2_keybd.c
index 75e0b73bac..1059e9c69a 100644
--- a/src/acpi/acpigen_ps2_keybd.c
+++ b/src/acpi/acpigen_ps2_keybd.c
@@ -59,6 +59,7 @@ static const uint32_t action_keymaps[] = {
 	[PS2_KEY_DICTATE] = KEYMAP(0xa7, KEY_DICTATE),		/* e027*/
 	[PS2_KEY_ACCESSIBILITY] = KEYMAP(0xa9, KEY_ACCESSIBILITY),	/* e029 */
 	[PS2_KEY_DO_NOT_DISTURB] = KEYMAP(0xa8, KEY_DO_NOT_DISTURB),	/* e028 */
+	[PS2_KEY_HOMEPAGE] = KEYMAP(0xaa, KEY_HOMEPAGE),	/* e02a */
 };
 
 /* Keymap for numeric keypad keys */
diff --git a/src/ec/google/chromeec/ec_acpi.c b/src/ec/google/chromeec/ec_acpi.c
index 65a425b793..8e0e9fee34 100644
--- a/src/ec/google/chromeec/ec_acpi.c
+++ b/src/ec/google/chromeec/ec_acpi.c
@@ -247,6 +247,7 @@ static const enum ps2_action_key ps2_enum_val[] = {
 	[TK_DICTATE] = PS2_KEY_DICTATE,
 	[TK_ACCESSIBILITY] = PS2_KEY_ACCESSIBILITY,
 	[TK_DONOTDISTURB] = PS2_KEY_DO_NOT_DISTURB,
+	[TK_HOME] = PS2_KEY_HOMEPAGE,
 };
 
 static void fill_ssdt_ps2_keyboard(const struct device *dev)
diff --git a/src/ec/google/chromeec/ec_commands.h b/src/ec/google/chromeec/ec_commands.h
index 8de9362540..091a9fbabb 100644
--- a/src/ec/google/chromeec/ec_commands.h
+++ b/src/ec/google/chromeec/ec_commands.h
@@ -7138,6 +7138,7 @@ enum action_key {
 	TK_DICTATE = 21,
 	TK_ACCESSIBILITY = 22,
 	TK_DONOTDISTURB = 23,
+	TK_HOME = 24,
 
 	TK_COUNT
 };
diff --git a/src/include/acpi/acpigen_ps2_keybd.h b/src/include/acpi/acpigen_ps2_keybd.h
index deb755bbf8..b564e64817 100644
--- a/src/include/acpi/acpigen_ps2_keybd.h
+++ b/src/include/acpi/acpigen_ps2_keybd.h
@@ -30,6 +30,7 @@ enum ps2_action_key {
 	PS2_KEY_DICTATE,
 	PS2_KEY_ACCESSIBILITY,
 	PS2_KEY_DO_NOT_DISTURB,
+	PS2_KEY_HOMEPAGE,
 };
 
 #define PS2_MIN_TOP_ROW_KEYS		2

From 607740999da86d05165dd7788abe86f8452d6b0a Mon Sep 17 00:00:00 2001
From: Fabio Baltieri <fabiobaltieri@google.com>
Date: Wed, 5 Nov 2025 11:03:15 +0000
Subject: [PATCH 2548/3886] acpigen_ps2_keybd: map capslock

Looks like some devices may be using the capslock key, this a standard
code, just map it.

BUG=b:446677367
TEST=flashed and tested on a brox board, checked that the correct code
is generated with evtest

Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
Change-Id: Ieb0f55e7f25a1b34d226efe12ad9dc481a53a082
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90025
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
---
 src/acpi/acpigen_ps2_keybd.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/src/acpi/acpigen_ps2_keybd.c b/src/acpi/acpigen_ps2_keybd.c
index 1059e9c69a..6118669a8e 100644
--- a/src/acpi/acpigen_ps2_keybd.c
+++ b/src/acpi/acpigen_ps2_keybd.c
@@ -175,6 +175,8 @@ static uint32_t rest_of_keymaps[] = {
 	KEYMAP(0xc8, KEY_UP),
 	/* Power Key */
 	KEYMAP(0xde, KEY_POWER),
+	/* Caps Lock */
+	KEYMAP(0x3a, KEY_CAPSLOCK),
 };
 
 static void ssdt_generate_physmap(struct acpi_dp *dp, uint8_t num_top_row_keys,

From 7a1e63308a4294cb5c41f2236b85a33c234a7f2d Mon Sep 17 00:00:00 2001
From: Fabio Baltieri <fabiobaltieri@google.com>
Date: Fri, 7 Nov 2025 16:51:29 +0000
Subject: [PATCH 2549/3886] acpigen_ps2_keybd: map insert

This is going to be used in some devices in place of KEY_ASSISTANT, map
it.

BUG=b:446676921
TEST=flashed and tested on a brox board, checked that the correct code
is generated with evtest

Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
Change-Id: I006c232c2924e8b6dc06338b0282c76f1f529a9e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90026
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/acpi/acpigen_ps2_keybd.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/src/acpi/acpigen_ps2_keybd.c b/src/acpi/acpigen_ps2_keybd.c
index 6118669a8e..f8b58d739b 100644
--- a/src/acpi/acpigen_ps2_keybd.c
+++ b/src/acpi/acpigen_ps2_keybd.c
@@ -177,6 +177,8 @@ static uint32_t rest_of_keymaps[] = {
 	KEYMAP(0xde, KEY_POWER),
 	/* Caps Lock */
 	KEYMAP(0x3a, KEY_CAPSLOCK),
+	/* Insert Key */
+	KEYMAP(0xd2, KEY_INSERT),
 };
 
 static void ssdt_generate_physmap(struct acpi_dp *dp, uint8_t num_top_row_keys,

From ddb3f0b17fd4d3d7324322d69eb21ddb5646bec2 Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Sat, 1 Nov 2025 11:42:36 -0500
Subject: [PATCH 2550/3886] drivers/hwid_dmi: Populate SMBIOS product name from
 CBFS hwid file

Add driver to read 'hwid' file from CBFS and use it for SMBIOS product
name. Processes the ChromeOS-format HWID string by removing prefix
after colon, trimming whitespace, and extracting base name before
any hyphen/space. Returned string is normalized to have the first
character/letter capitalized, and the rest lower case. If no HWID file
is found in CBFS, the fallback is CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME.

This driver is intended to allow ChromeOS devices running upstream
coreboot to persist their board's unique HWID and use it as the SMBIOS
board name, but it is not limited to that function.

TEST=tested in MrChromebox downstream. Multiple devices which use the
same ChromeOS board but differ in HWID can use the same firmware image
and still be properly identified.

Change-Id: I1af1df4c79858d23ef71400abe72f41eec6c25c6
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90063
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
---
 src/drivers/hwid_dmi/Kconfig     | 12 ++++
 src/drivers/hwid_dmi/Makefile.mk |  3 +
 src/drivers/hwid_dmi/hwid_dmi.c  | 97 ++++++++++++++++++++++++++++++++
 3 files changed, 112 insertions(+)
 create mode 100644 src/drivers/hwid_dmi/Kconfig
 create mode 100644 src/drivers/hwid_dmi/Makefile.mk
 create mode 100644 src/drivers/hwid_dmi/hwid_dmi.c

diff --git a/src/drivers/hwid_dmi/Kconfig b/src/drivers/hwid_dmi/Kconfig
new file mode 100644
index 0000000000..27aeca38da
--- /dev/null
+++ b/src/drivers/hwid_dmi/Kconfig
@@ -0,0 +1,12 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
+config DRIVERS_HWID_DMI
+	bool "HWID from CBFS for SMBIOS product name"
+	default n
+	help
+	  Enable this option to read the hardware ID (HWID) from a
+	  file in CBFS and use it to populate the SMBIOS product name.
+	  The driver will read a file named 'hwid' from CBFS, process it
+	  to extract the base HWID (trimming whitespace, removing 'hwid:'
+	  prefix, and dropping everything after hyphen or space), and
+	  use it as the SMBIOS system product name.
diff --git a/src/drivers/hwid_dmi/Makefile.mk b/src/drivers/hwid_dmi/Makefile.mk
new file mode 100644
index 0000000000..3af79a0236
--- /dev/null
+++ b/src/drivers/hwid_dmi/Makefile.mk
@@ -0,0 +1,3 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
+ramstage-$(CONFIG_DRIVERS_HWID_DMI) += hwid_dmi.c
diff --git a/src/drivers/hwid_dmi/hwid_dmi.c b/src/drivers/hwid_dmi/hwid_dmi.c
new file mode 100644
index 0000000000..786f936253
--- /dev/null
+++ b/src/drivers/hwid_dmi/hwid_dmi.c
@@ -0,0 +1,97 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <cbfs.h>
+#include <console/console.h>
+#include <ctype.h>
+#include <smbios.h>
+#include <string.h>
+
+#define MAX_HWID_LENGTH 0x100
+
+/*
+ * Process the HWID string according to requirements:
+ * - If a colon is found, delete everything before it
+ * - Trim leading/trailing whitespace
+ * - Drop anything after hyphen or space
+ *
+ * Examples:
+ * - 'hardware_id: NOCTURNE D5B-A5F-B47-H6A-A5L' --> Nocturne
+ * - 'BANSHEE-UZTQ B4B-D3A-F3F-D8A-A7O' --> Banshee
+ */
+static void process_hwid(char *hwid)
+{
+	char *src = hwid;
+	char *dst = hwid;
+	char *colon;
+	char *end;
+
+	if (!hwid || !*hwid)
+		return;
+
+	/* Look for a colon and skip everything before it */
+	colon = strchr(hwid, ':');
+	if (colon) {
+		src = colon + 1;  /* Start after the colon */
+	}
+
+	/* Trim leading whitespace */
+	while (*src && isspace((unsigned char)*src))
+		src++;
+
+	/* Copy characters until we hit a hyphen, space, or end of string */
+	while (*src && *src != '-' && !isspace((unsigned char)*src)) {
+		*dst++ = *src++;
+	}
+
+	/* Null terminate */
+	*dst = '\0';
+
+	/* Trim trailing whitespace (shouldn't be any based on the logic above, but just in case) */
+	end = dst - 1;
+	while (end >= hwid && isspace((unsigned char)*end)) {
+		*end = '\0';
+		end--;
+	}
+
+	/* Normalize casing: capitalize first character, lowercase the rest */
+	if (*hwid) {
+		char *p = hwid;
+
+		*p = toupper((unsigned char)*p);
+		for (p = hwid + 1; *p; p++)
+			*p = tolower((unsigned char)*p);
+	}
+}
+
+const char *smbios_system_product_name(void)
+{
+	static char hwid_str[MAX_HWID_LENGTH + 1] = {0};
+
+	/* Return cached value if already loaded */
+	if (hwid_str[0] != '\0')
+		return hwid_str;
+
+	/* Try to load HWID from CBFS */
+	size_t hwid_len = cbfs_load("hwid", hwid_str, MAX_HWID_LENGTH);
+
+	if (hwid_len > 0) {
+		/* Ensure null termination */
+		hwid_str[hwid_len] = '\0';
+
+		/* Process the HWID string */
+		process_hwid(hwid_str);
+
+		/* Check if we have a valid string after processing */
+		if (hwid_str[0] != '\0') {
+			printk(BIOS_INFO, "HWID: Using '%s' as product name\n", hwid_str);
+			return hwid_str;
+		}
+	}
+
+	/* Fall back to default if file not found or processing resulted in empty string */
+	printk(BIOS_WARNING, "HWID: File not found or invalid, using default product name\n");
+	strncpy(hwid_str, CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME, MAX_HWID_LENGTH);
+	hwid_str[MAX_HWID_LENGTH] = '\0';
+
+	return hwid_str;
+}

From 1b0f9c5458608ae4bd0e3517d33e1775195f0b7d Mon Sep 17 00:00:00 2001
From: Kun Liu <liukun11@huaqin.corp-partner.google.com>
Date: Wed, 5 Nov 2025 20:07:21 +0800
Subject: [PATCH 2551/3886] mb/google/nissa/var/telith: Add parade touchscreen
 support

Add parade PRT3408 touchscreen support

BUG=b:461693725
TEST=emerge-nissa coreboot chromeos-bootimage

Change-Id: I7d320bcaf3554c9adde4813a366ee60c28b8cc13
Signed-off-by: Kun Liu <liukun11@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90093
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
---
 .../google/brya/variants/telith/gpio.c        |  2 +-
 .../brya/variants/telith/overridetree.cb      | 19 +++++++++++++++++++
 2 files changed, 20 insertions(+), 1 deletion(-)

diff --git a/src/mainboard/google/brya/variants/telith/gpio.c b/src/mainboard/google/brya/variants/telith/gpio.c
index 75f7617655..7b8d8344cc 100644
--- a/src/mainboard/google/brya/variants/telith/gpio.c
+++ b/src/mainboard/google/brya/variants/telith/gpio.c
@@ -96,7 +96,7 @@ static const struct pad_config early_gpio_table[] = {
 	/* C0  : SMBCLK ==> EN_PP3300_TCHSCR_X */
 	PAD_CFG_GPO(GPP_C0, 1, DEEP),
 	/* C1  : SMBDATA ==> TCHSCR_RST_L */
-	PAD_CFG_GPO(GPP_C1, 1, DEEP),
+	PAD_CFG_GPO(GPP_C1, 0, DEEP),
 
 	/* H20 : IMGCLKOUT1 ==> WLAN_PERST_L */
 	PAD_CFG_GPO(GPP_H20, 0, DEEP),
diff --git a/src/mainboard/google/brya/variants/telith/overridetree.cb b/src/mainboard/google/brya/variants/telith/overridetree.cb
index 86c4bc43e6..7c8706d8bf 100644
--- a/src/mainboard/google/brya/variants/telith/overridetree.cb
+++ b/src/mainboard/google/brya/variants/telith/overridetree.cb
@@ -372,6 +372,7 @@ chip soc/intel/alderlake
 				register "hid" = ""ELAN0001""
 				register "desc" = ""ELAN Touchscreen""
 				register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_C7_IRQ)"
+				register "detect" = "1"
 				register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C1)"
 				register "reset_delay_ms" = "20"
 				register "reset_off_delay_ms" = "4"
@@ -384,6 +385,24 @@ chip soc/intel/alderlake
 				register "use_gpio_for_status" = "true"
 				device i2c 10 on end
 			end
+			chip drivers/i2c/hid
+				register "generic.hid" = ""PRT3408""
+				register "generic.desc" = ""Parade Touchscreen""
+				register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_C7_IRQ)"
+				register "generic.detect" = "1"
+				register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C1)"
+				register "generic.reset_delay_ms" = "20"
+				register "generic.reset_off_delay_ms" = "2"
+				register "generic.stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C6)"
+				register "generic.stop_delay_ms" = "250"
+				register "generic.stop_off_delay_ms" = "25"
+				register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C0)"
+				register "generic.enable_delay_ms" = "1"
+				register "generic.has_power_resource" = "true"
+				register "generic.use_gpio_for_status" = "true"
+				register "hid_desc_reg_offset" = "0x01"
+				device i2c 24 on end
+			end
 		end
 		device ref i2c2 on
 			chip drivers/intel/mipi_camera

From 40b2a2b03c5c49795c343b8bfe5287fd866f93e0 Mon Sep 17 00:00:00 2001
From: Jarried Lin <jarried.lin@mediatek.corp-partner.google.com>
Date: Fri, 21 Nov 2025 14:40:18 +0800
Subject: [PATCH 2552/3886] soc/mediatek/mt8196/booker: Refactor CMO property
 clearing with loop

Replace multiple hardcoded clrbits64p calls with a loop over
booker_base. This improves readability and maintainability.

BRANCH=rauru
BUG=b:438666196
TEST=manual test

Change-Id: I4799bc3eff2ab24265bac093600948dccc4916de
Signed-off-by: Jarried Lin <jarried.lin@mediatek.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90143
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Chen-Tsung Hsieh <chentsung@google.com>
---
 src/soc/mediatek/mt8196/booker.c | 13 +++++--------
 1 file changed, 5 insertions(+), 8 deletions(-)

diff --git a/src/soc/mediatek/mt8196/booker.c b/src/soc/mediatek/mt8196/booker.c
index c571734f62..13a0248653 100644
--- a/src/soc/mediatek/mt8196/booker.c
+++ b/src/soc/mediatek/mt8196/booker.c
@@ -9,10 +9,6 @@
 #define REG_MCUSYS_RESERVED_REG2	(MCUCFG_BASE + 0xFFE8)
 
 #define POR_SBSX_CFG_CTL_OFFSET		(0x00450000 + 0x0A00)
-#define INSTANCE0_SBSX_POR_SBSX_CFG_CTL	(0x0A000000 + POR_SBSX_CFG_CTL_OFFSET)
-#define INSTANCE1_SBSX_POR_SBSX_CFG_CTL	(0x0A800000 + POR_SBSX_CFG_CTL_OFFSET)
-#define INSTANCE2_SBSX_POR_SBSX_CFG_CTL	(0x0B000000 + POR_SBSX_CFG_CTL_OFFSET)
-#define INSTANCE3_SBSX_POR_SBSX_CFG_CTL	(0x0B800000 + POR_SBSX_CFG_CTL_OFFSET)
 
 #define POR_MTU_BASE			0x790000
 #define POR_MTU_AUX_CTL_OFFSET		(POR_MTU_BASE + 0x0A08)
@@ -44,11 +40,12 @@ static const uint32_t booker_base[] = {
  */
 void booker_init(void)
 {
+	int i;
+
 	/* Enable CMO(cache maintenance operations) propagation */
-	clrbits64p(INSTANCE0_SBSX_POR_SBSX_CFG_CTL, BIT_DISABLE_CMO_PROP);
-	clrbits64p(INSTANCE1_SBSX_POR_SBSX_CFG_CTL, BIT_DISABLE_CMO_PROP);
-	clrbits64p(INSTANCE2_SBSX_POR_SBSX_CFG_CTL, BIT_DISABLE_CMO_PROP);
-	clrbits64p(INSTANCE3_SBSX_POR_SBSX_CFG_CTL, BIT_DISABLE_CMO_PROP);
+	for (i = 0; i < ARRAY_SIZE(booker_base); i++)
+		clrbits64p(booker_base[i] + POR_SBSX_CFG_CTL_OFFSET, BIT_DISABLE_CMO_PROP);
+
 	dsb();
 	isb();
 

From e5d10e5d23d362e994ac6066991049b50257f690 Mon Sep 17 00:00:00 2001
From: Arthur Heymans <arthur@aheymans.xyz>
Date: Thu, 13 Nov 2025 15:45:46 +0100
Subject: [PATCH 2553/3886] mb/lenovo/t480: Fix headphone jack

Add additional register configuration for the Realtek ALC257 audio
codec on the Lenovo ThinkPad T480. This includes:

- Hidden register SW reset sequence
- ClassD 2W amplifier configuration
- Jack detection (JD1) setup for headphone port
- Silence data mode threshold setting at -84dB

Shamelessly taken from google/brya/variants/pujjolo/hda_verb.c

Change-Id: Ib77138d782ceb9feeaef82935bc1c0d5c3066183
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90023
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
---
 .../sklkbl_thinkpad/variants/t480/hda_verb.c  | 37 ++++++++++++++++++-
 1 file changed, 36 insertions(+), 1 deletion(-)

diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480/hda_verb.c b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480/hda_verb.c
index 3a951ce0da..fc8cac8680 100644
--- a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480/hda_verb.c
+++ b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480/hda_verb.c
@@ -5,7 +5,7 @@
 const u32 cim_verb_data[] = {
 	0x10ec0257, // Vendor/Device ID: Realtek ALC257
 	0x17aa225d, // Subsystem ID
-	11,
+	18,
 	AZALIA_SUBVENDOR(0, 0x17aa225d),
 
 	AZALIA_PIN_CFG(0, 0x12, AZALIA_PIN_DESC(
@@ -51,6 +51,41 @@ const u32 cim_verb_data[] = {
 		1, 15
 	)),
 
+	//==========Widget node 0x20 - 0 :Hidden register SW reset
+	0x0205001A,
+	0x0204C003,
+	0x0205001A,
+	0x0204C003,
+	0x05850000,
+	0x0584F880,
+	0x05850000,
+	0x0584F880,
+	//==========Widget node 0x20 - 1 : ClassD 2W
+	0x02050038,
+	0x02048981,
+	0x0205001B,
+	0x02040A4B,
+	//==========Widget node 0x20 - 2
+	0x0205003C,
+	0x02043154,
+	0x0205003C,
+	0x02043114,
+	//==========Widget node 0x20 - 3 :
+	0x02050046,
+	0x02040004,
+	0x05750003,
+	0x057409A3,
+	//==========Widget node 0x20 - 4 :JD1 enable 1JD port for HP JD
+	0x02050009,
+	0x02046003,
+	0x0205000A,
+	0x02047770,
+	//==========Widget node 0x20 - 5 : Silence data mode Threshold (-84dB)
+	0x02050037,
+	0x0204FE15,
+	0x02050030,
+	0x02049004,
+
 	0x8086280b, // Vendor/Device ID: Intel Kabylake HDMI
 	0x80860101, // Subsystem ID
 	4,

From 10802bac163664de67474b8f6a92e728f39252db Mon Sep 17 00:00:00 2001
From: Luca Lai <luca.lai@lcfc.corp-partner.google.com>
Date: Wed, 19 Nov 2025 20:51:37 +0800
Subject: [PATCH 2554/3886] spd/lp5: Modify SPD for MT62F1G32D2DS-020 WT:D and
 K3KL8L80EM-MGCV

Modify ranksPerChannel and diesPerPackage attributes for
MT62F1G32D2DS-020 WT:D and K3KL8L80EM-MGCV.

TEST=util/spd_tools/bin/spd_gen spd/lp5/memory_parts.json lp5

Change-Id: I1069fac58d099d58f76fe268973081f49842f16d
Signed-off-by: Luca Lai <luca.lai@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90123
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Derek Huang <derekhuang@google.com>
---
 spd/lp5/memory_parts.json                      | 6 +++---
 spd/lp5/set-0/parts_spd_manifest.generated.txt | 4 ++--
 spd/lp5/set-1/parts_spd_manifest.generated.txt | 4 ++--
 3 files changed, 7 insertions(+), 7 deletions(-)

diff --git a/spd/lp5/memory_parts.json b/spd/lp5/memory_parts.json
index d53a1c3cff..1a29150bc0 100644
--- a/spd/lp5/memory_parts.json
+++ b/spd/lp5/memory_parts.json
@@ -388,7 +388,7 @@
             "densityPerDieGb": 16,
             "diesPerPackage": 2,
             "bitWidthPerChannel": 16,
-            "ranksPerChannel": 2,
+            "ranksPerChannel": 1,
             "speedMbps": 8533,
             "lp5x": true
         }
@@ -397,9 +397,9 @@
         "name":  "K3KL8L80EM-MGCV",
         "attribs": {
             "densityPerDieGb": 16,
-            "diesPerPackage": 4,
+            "diesPerPackage": 2,
             "bitWidthPerChannel": 16,
-            "ranksPerChannel": 2,
+            "ranksPerChannel": 1,
             "speedMbps": 8533,
             "lp5x": true
         }
diff --git a/spd/lp5/set-0/parts_spd_manifest.generated.txt b/spd/lp5/set-0/parts_spd_manifest.generated.txt
index 0d71bfb08a..b808e1941c 100644
--- a/spd/lp5/set-0/parts_spd_manifest.generated.txt
+++ b/spd/lp5/set-0/parts_spd_manifest.generated.txt
@@ -37,5 +37,5 @@ MT62F1G32D2DS-031 WT:C,spd-3.hex
 MT62F2G32D4DS-031 WT:C,spd-6.hex
 H58GE6AK8BX104,spd-12.hex
 K3KLALA0EM-MGCU,spd-13.hex
-MT62F1G32D2DS-020 WT:D,spd-14.hex
-K3KL8L80EM-MGCV,spd-10.hex
+MT62F1G32D2DS-020 WT:D,spd-11.hex
+K3KL8L80EM-MGCV,spd-11.hex
diff --git a/spd/lp5/set-1/parts_spd_manifest.generated.txt b/spd/lp5/set-1/parts_spd_manifest.generated.txt
index 08d9e6ecee..b808e1941c 100644
--- a/spd/lp5/set-1/parts_spd_manifest.generated.txt
+++ b/spd/lp5/set-1/parts_spd_manifest.generated.txt
@@ -37,5 +37,5 @@ MT62F1G32D2DS-031 WT:C,spd-3.hex
 MT62F2G32D4DS-031 WT:C,spd-6.hex
 H58GE6AK8BX104,spd-12.hex
 K3KLALA0EM-MGCU,spd-13.hex
-+MT62F1G32D2DS-020 WT:D,spd-14.hex
-+K3KL8L80EM-MGCV,spd-10.hex
+MT62F1G32D2DS-020 WT:D,spd-11.hex
+K3KL8L80EM-MGCV,spd-11.hex

From 56be23114e6dba7e9bc81f6e1387a532aa163844 Mon Sep 17 00:00:00 2001
From: Yidi Lin <yidilin@google.com>
Date: Mon, 24 Nov 2025 12:22:05 +0800
Subject: [PATCH 2555/3886] mb/google/rauru: Use chromeos-legacy.fmd for Hylia
 and Navi

The recent increase of the RW size to 1756KB (CB:89545) has led to an
FMAP incompatibility. This issue arises during testing when both the ToT
firmware (which utilizes a new FMAP layout) and the firmware
branch-built firmware (which relies on an older FMAP layout) are used on
the same device.

To address this testing failure and streamline the testing process, the
updated FMAP will be exclusively implemented for the new variant. The
Navi and Hylia devices will continue to use the legacy FMAP.

BUG=b:461559917,b:463050048
TEST=emerge-{rauru,tanjiro} coreboot chromeos-bootimage

Change-Id: Icb4a12030f7a2e05757c903b70899c07b92c9875
Signed-off-by: Yidi Lin <yidilin@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90168
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Chen-Tsung Hsieh <chentsung@google.com>
---
 src/mainboard/google/rauru/Kconfig            |  4 ++
 .../google/rauru/chromeos-legacy.fmd          | 46 +++++++++++++++++++
 2 files changed, 50 insertions(+)
 create mode 100644 src/mainboard/google/rauru/chromeos-legacy.fmd

diff --git a/src/mainboard/google/rauru/Kconfig b/src/mainboard/google/rauru/Kconfig
index 2e23681354..7acca4b9e5 100644
--- a/src/mainboard/google/rauru/Kconfig
+++ b/src/mainboard/google/rauru/Kconfig
@@ -72,4 +72,8 @@ config DRIVER_TPM_I2C_ADDR
 	hex
 	default 0x50
 
+config FMDFILE
+	default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/chromeos-legacy.fmd" if CHROMEOS && (BOARD_GOOGLE_HYLIA || BOARD_GOOGLE_NAVI)
+	default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/chromeos.fmd" if CHROMEOS
+
 endif
diff --git a/src/mainboard/google/rauru/chromeos-legacy.fmd b/src/mainboard/google/rauru/chromeos-legacy.fmd
new file mode 100644
index 0000000000..abf673fa03
--- /dev/null
+++ b/src/mainboard/google/rauru/chromeos-legacy.fmd
@@ -0,0 +1,46 @@
+# Firmware Layout Description for ChromeOS.
+#
+# The size and address of every section must be aligned to at least 4K, except:
+# RO_FRID, RW_FWID*, GBB, or any unused / padding / CBFS type sections.
+#
+# 'FMAP' may be found by binary search so its starting address should be better
+# aligned to larger values.
+#
+# For sections to be preserved on update, add (PRESERVE) to individual sections
+# instead of a group section; otherwise the preserved data may be wrong if you
+# resize or reorder sections inside a group.
+
+FLASH 8M {
+	WP_RO@0x0 4M {
+		RO_SECTION {
+			BOOTBLOCK 128K
+			FMAP 4K
+			COREBOOT(CBFS)
+			GBB 0x2f00
+			RO_FRID 0x100
+		}
+		RO_GSCVD 8K
+		RO_VPD(PRESERVE) 32K  # At least 16K.
+	}
+	RW_SECTION_A 1500K {
+		VBLOCK_A 8K
+		FW_MAIN_A(CBFS)
+		RW_FWID_A 0x100
+	}
+	RW_MISC 36K {
+		RW_VPD(PRESERVE) 8K  # At least 8K.
+		RW_NVRAM(PRESERVE) 8K
+		RW_MRC_CACHE(PRESERVE) 16K
+		RW_ELOG(PRESERVE) 4K  # ELOG driver hard-coded size in 4K.
+	}
+	RW_SECTION_B 1500K {
+		VBLOCK_B 8K
+		FW_MAIN_B(CBFS)
+		RW_FWID_B 0x100
+	}
+	RW_SHARED 36K {  # Will be force updated on recovery.
+		SHARED_DATA 4K  # 4K or less for netboot params.
+		RW_UNUSED
+	}
+	RW_LEGACY(CBFS) 1M  # Minimal 1M.
+}

From 51e99de558c9926f90cd211e3f5651f41392a2d2 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Filip=20Lewi=C5=84ski?= <filip.lewinski@3mdeb.com>
Date: Fri, 21 Nov 2025 12:18:58 +0100
Subject: [PATCH 2556/3886] soc/intel/common/block/rtc/rtc.c: control Top Swap
 via CMOS option
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Toggle the RTC BUC control bit for Top Swap bootblock selection based on
the "attempt_slot_b" flag CMOS option, allowing to select which of the
BOOTBLOCK or TOP_SWAP regions to boot from.

This means that after an update, the CMOS option can be set to boot from
the newer TOP_SWAP bootblock. In case of failure, CMOS can be cleared to
revert to the known-good base BOOTBLOCK.

This is part of ongoing implementation of a redundancy feature proposed
on the mailing list:
https://mail.coreboot.org/archives/list/coreboot@coreboot.org/thread/C6JN2PB7K7D67EG7OIKB6BBERZU5YV35/

Switching between identical bootblocks doesn't impact further boot flow,
i.e. selecting which FMAP region to load consecutive stages from.
That is to be enabled in following patches.

So far tested and enabled for the Alder Lake SoC.

TEST=Boot VP6650, setting the attempt_slot_b flag to different values,
observing that it resets/continues booting correctly.

Change-Id: Ib183a1f72ee8585b2c4ad4376344de33ff54cbb9
Signed-off-by: Filip Lewiński <filip.lewinski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90042
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com>
---
 src/soc/intel/alderlake/bootblock/bootblock.c  |  4 ++++
 src/soc/intel/common/Kconfig.common            |  9 +++++++++
 .../common/block/include/intelblocks/rtc.h     |  7 +++++++
 src/soc/intel/common/block/rtc/rtc.c           | 18 +++++++++++++++++-
 4 files changed, 37 insertions(+), 1 deletion(-)

diff --git a/src/soc/intel/alderlake/bootblock/bootblock.c b/src/soc/intel/alderlake/bootblock/bootblock.c
index b8086a42ab..df39c9db52 100644
--- a/src/soc/intel/alderlake/bootblock/bootblock.c
+++ b/src/soc/intel/alderlake/bootblock/bootblock.c
@@ -2,6 +2,7 @@
 
 #include <bootblock_common.h>
 #include <intelblocks/fast_spi.h>
+#include <intelblocks/rtc.h>
 #include <intelblocks/systemagent.h>
 #include <intelblocks/tco.h>
 #include <intelblocks/uart.h>
@@ -30,4 +31,7 @@ void bootblock_soc_init(void)
 
 	/* Programming TCO_BASE_ADDRESS and TCO Timer Halt */
 	tco_configure();
+
+	if (CONFIG(INTEL_TOP_SWAP_OPTION_CONTROL))
+		sync_rtc_buc_top_swap();
 }
diff --git a/src/soc/intel/common/Kconfig.common b/src/soc/intel/common/Kconfig.common
index be05c65315..964a564303 100644
--- a/src/soc/intel/common/Kconfig.common
+++ b/src/soc/intel/common/Kconfig.common
@@ -57,6 +57,15 @@ config INTEL_TOP_SWAP_SEPARATE_REGIONS
 	  facilitate firmware updates using the Top Swap as Slot A/Slot B redundancy.
 	  Requires a custom .fmd with the regions added at the end.
 
+config INTEL_TOP_SWAP_OPTION_CONTROL
+	bool "Toggle the Top Swap functionality using a CMOS option"
+	depends on INTEL_TOP_SWAP_SEPARATE_REGIONS && USE_OPTION_TABLE && SOC_INTEL_ALDERLAKE
+	default n
+	help
+	  Switch between the Top Swap bootblocks using the "attempt_slot_b" CMOS
+	  option. Note that the option must be present in the board's cmos.layout.
+	  file.
+
 endif
 
 config SOC_INTEL_COMMON
diff --git a/src/soc/intel/common/block/include/intelblocks/rtc.h b/src/soc/intel/common/block/include/intelblocks/rtc.h
index 0f09d7e0fb..ca53996c6b 100644
--- a/src/soc/intel/common/block/include/intelblocks/rtc.h
+++ b/src/soc/intel/common/block/include/intelblocks/rtc.h
@@ -3,6 +3,8 @@
 #ifndef SOC_INTEL_COMMON_BLOCK_RTC_H
 #define SOC_INTEL_COMMON_BLOCK_RTC_H
 
+#define TOP_SWAP_ENABLE_CMOS_OPTION "attempt_slot_b"
+
 /* Top swap feature enable/disable config */
 enum ts_config {
 	TS_DISABLE,
@@ -32,6 +34,11 @@ void configure_rtc_buc_top_swap(enum ts_config ts_state);
  */
 enum ts_config get_rtc_buc_top_swap_status(void);
 
+/*
+ * Set/unset the top swap bit based on TOP_SWAP_ENABLE_CMOS_OPTION state
+ */
+void sync_rtc_buc_top_swap(void);
+
 /* Set RTC Configuration BILD bit. */
 void rtc_conf_set_bios_interface_lockdown(void);
 #endif	/* SOC_INTEL_COMMON_BLOCK_RTC_H */
diff --git a/src/soc/intel/common/block/rtc/rtc.c b/src/soc/intel/common/block/rtc/rtc.c
index 5a5de912bb..fd8dc88755 100644
--- a/src/soc/intel/common/block/rtc/rtc.c
+++ b/src/soc/intel/common/block/rtc/rtc.c
@@ -2,8 +2,10 @@
 
 #include <intelblocks/pcr.h>
 #include <intelblocks/rtc.h>
-#include <soc/pcr_ids.h>
+#include <option.h>
 #include <pc80/mc146818rtc.h>
+#include <reset.h>
+#include <soc/pcr_ids.h>
 
 /* RTC PCR configuration */
 #define PCR_RTC_CONF		0x3400
@@ -53,4 +55,18 @@ enum ts_config get_rtc_buc_top_swap_status(void)
 	else
 		return TS_DISABLE;
 }
+
+void sync_rtc_buc_top_swap(void)
+{
+	uint8_t cmos_slotb_option, topswap_control_bit;
+	cmos_slotb_option = get_uint_option(TOP_SWAP_ENABLE_CMOS_OPTION, 0);
+	topswap_control_bit = get_rtc_buc_top_swap_status();
+	printk(BIOS_INFO, "Top Swap: CMOS option state: %d\n", cmos_slotb_option);
+	printk(BIOS_INFO, "Top Swap: RTC BUC control bit: %d\n", topswap_control_bit);
+	if (cmos_slotb_option != topswap_control_bit) {
+		configure_rtc_buc_top_swap(cmos_slotb_option);
+		printk(BIOS_INFO, "Top Swap: RTC BUC control bit set to: %d, platform reset is necessary\n", get_rtc_buc_top_swap_status());
+		board_reset();
+	}
+}
 #endif

From 2f9b4ad6a508628ce60973e649b036c099eda310 Mon Sep 17 00:00:00 2001
From: Swathi Tamilselvan <tswathi@qualcomm.corp-partner.google.com>
Date: Wed, 19 Nov 2025 19:48:19 +0530
Subject: [PATCH 2557/3886] soc/qualcomm/x1p42100: Add DFSR table configuration
 support

Add support to configure DFSR table, introduce qupv3_clock_v2
structure to calculate register addresses for serial engines 2
and 3. Update CBCR registers to use the new structure for QUPv3
clock enablement.

BUG=b:444617760
TEST=Create an image.serial.bin and ensure it boots on X1P42100.
Dump DFSR registers for corresponding QUP and check if values are
updated properly into correct register address.

Change-Id: Ibd7e4bf121bd99130336047a50ed70d4cbec2234
Signed-off-by: Swathi Tamilselvan <tswathi@qualcomm.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90145
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
---
 .../common/include/soc/clock_common.h         |   9 ++
 src/soc/qualcomm/x1p42100/clock.c             | 117 +++++++++++++++---
 .../x1p42100/include/soc/addressmap.h         |   3 +
 src/soc/qualcomm/x1p42100/include/soc/clock.h |  17 +++
 4 files changed, 130 insertions(+), 16 deletions(-)

diff --git a/src/soc/qualcomm/common/include/soc/clock_common.h b/src/soc/qualcomm/common/include/soc/clock_common.h
index 10ae134c70..f638ce00e6 100644
--- a/src/soc/qualcomm/common/include/soc/clock_common.h
+++ b/src/soc/qualcomm/common/include/soc/clock_common.h
@@ -52,6 +52,15 @@ struct qupv3_clock {
 	struct clock_rcg_dfsr dfsr_clk;
 };
 
+struct qupv3_clock_v2 {
+	u32 cbcr;
+#if CONFIG(QC_COMMON_QUPV3_2)
+	u8 reserved[0x10];
+#endif
+	struct clock_rcg_mnd clk;
+	struct clock_rcg_dfsr dfsr_clk;
+};
+
 /* PLL Configuration */
 struct alpha_pll_reg_val_config {
 	void *reg_mode;
diff --git a/src/soc/qualcomm/x1p42100/clock.c b/src/soc/qualcomm/x1p42100/clock.c
index 614490104a..377f529a08 100644
--- a/src/soc/qualcomm/x1p42100/clock.c
+++ b/src/soc/qualcomm/x1p42100/clock.c
@@ -317,37 +317,122 @@ void clock_configure_qspi(uint32_t hz)
 	clock_enable(&gcc->qspi_core_cbcr);
 }
 
+/* Helper function to get SE index within a wrap */
+static inline int get_qup_se_index(int qup)
+{
+	return qup % QUP_WRAP1_S0;
+}
+
+/* Helper function to get pointer to QUP SE clock structure */
+static void *get_qup_se_clk(int qup, int s)
+{
+	struct x1p42100_qupv3_wrap *wrap;
+	void *se_clk_array[8];
+
+	/* Determine which wrap based on qup value */
+	if (qup <= QUP_WRAP0_S7)
+		wrap = qup_wrap0_clk;
+	else if (qup <= QUP_WRAP1_S7)
+		wrap = qup_wrap1_clk;
+	else
+		wrap = qup_wrap2_clk;
+
+	/* Build array of pointers to SE clock structures */
+	se_clk_array[0] = &wrap->qupv3_s0;
+	se_clk_array[1] = &wrap->qupv3_s1;
+	se_clk_array[2] = &wrap->qupv3_s2;
+	se_clk_array[3] = &wrap->qupv3_s3;
+	se_clk_array[4] = &wrap->qupv3_s4;
+	se_clk_array[5] = &wrap->qupv3_s5;
+	se_clk_array[6] = &wrap->qupv3_s6;
+	se_clk_array[7] = &wrap->qupv3_s7;
+
+	return se_clk_array[s];
+}
+
 void clock_enable_qup(int qup)
 {
-	struct qupv3_clock *qup_clk;
-	int s = qup % QUP_WRAP1_S0, clk_en_off;
-	void *clk_br_en_ptr = NULL;	// Pointer to the correct apcs_clk_br_enX
-	qup_clk = qup < QUP_WRAP1_S0 ? &gcc->qup_wrap0_s[s] : qup < QUP_WRAP2_S0 ?
-		&gcc->qup_wrap1_s[s] : &gcc->qup_wrap2_s[s];
+	int s = get_qup_se_index(qup), clk_en_off;
+	void *clk_br_en_ptr = NULL;
+	u32 *cbcr;
 
 	if (qup <= QUP_WRAP0_S7) {
 		clk_en_off = QUPV3_WRAP0_CLK_ENA_S(s);
 		clk_br_en_ptr = &gcc->apcs_clk_br_en4;
-	} else if (qup >= QUP_WRAP1_S0 && qup <= QUP_WRAP1_S6) {
-		clk_en_off = QUPV3_WRAP1_CLK_ENA_S(s);
-		clk_br_en_ptr = &gcc->apcs_clk_br_en1;
-	} else if (qup >= QUP_WRAP2_S0 && qup <= QUP_WRAP2_S6) {
-		clk_en_off = QUPV3_WRAP2_CLK_ENA_S(s);
-		clk_br_en_ptr = &gcc->apcs_clk_br_en2;
-	} else if (qup == QUP_WRAP1_S7 || qup == QUP_WRAP2_S7) {
-		clk_en_off = qup == QUP_WRAP1_S7 ? QUPV3_WRAP1_SE7_CLK_ENA : QUPV3_WRAP2_SE7_CLK_ENA;
+	} else if (qup <= QUP_WRAP1_S7) {
+		clk_en_off = (qup == QUP_WRAP1_S7) ? QUPV3_WRAP1_SE7_CLK_ENA : QUPV3_WRAP1_CLK_ENA_S(s);
+		clk_br_en_ptr = (qup == QUP_WRAP1_S7) ? &gcc->apcs_clk_br_en2 : &gcc->apcs_clk_br_en1;
+	} else {
+		clk_en_off = (qup == QUP_WRAP2_S7) ? QUPV3_WRAP2_SE7_CLK_ENA : QUPV3_WRAP2_CLK_ENA_S(s);
 		clk_br_en_ptr = &gcc->apcs_clk_br_en2;
 	}
 
+	if (s == 2 || s == 3)
+		cbcr = &((struct qupv3_clock_v2 *)get_qup_se_clk(qup, s))->cbcr;
+	else
+		cbcr = &((struct qupv3_clock *)get_qup_se_clk(qup, s))->cbcr;
+
 	/* Only call if a valid pointer was assigned */
 	if (clk_br_en_ptr)
-		clock_enable_vote(&qup_clk->cbcr, clk_br_en_ptr, clk_en_off);
+		clock_enable_vote(cbcr, clk_br_en_ptr, clk_en_off);
+}
+
+/* Clock Root clock Generator with DFS Operations */
+void clock_configure_dfsr_table_x1p42100(int qup, struct clock_freq_config *clk_cfg,
+	uint32_t num_perfs)
+{
+	unsigned int idx;
+	int s = get_qup_se_index(qup);
+	uint32_t reg_val;
+	struct clock_rcg_dfsr *dfsr_clk;
+
+	/* Validate s value is within bounds */
+	if (s > 7) {
+		printk(BIOS_ERR, "Invalid QUP index: s=%d\n", s);
+		return;
+	}
+
+	/* Get DFSR clock pointer - cast based on SE type
+	 * (s2, s3 are qupv3_clock_v2, others are qupv3_clock)
+	 */
+	if (s == 2 || s == 3)
+		dfsr_clk = &((struct qupv3_clock_v2 *)get_qup_se_clk(qup, s))->dfsr_clk;
+	else
+		dfsr_clk = &((struct qupv3_clock *)get_qup_se_clk(qup, s))->dfsr_clk;
+
+	clrsetbits32(&dfsr_clk->cmd_dfsr,
+			BIT(CLK_CTL_CMD_RCG_SW_CTL_SHFT),
+			BIT(CLK_CTL_CMD_DFSR_SHFT));
+
+	for (idx = 0; idx < num_perfs; idx++) {
+		reg_val = (clk_cfg[idx].src << CLK_CTL_CFG_SRC_SEL_SHFT) |
+			(clk_cfg[idx].div << CLK_CTL_CFG_SRC_DIV_SHFT);
+
+		write32(&dfsr_clk->perf_dfsr[idx], reg_val);
+
+		if (clk_cfg[idx].m == 0)
+			continue;
+
+		setbits32(&dfsr_clk->perf_dfsr[idx], RCG_MODE_DUAL_EDGE << CLK_CTL_CFG_MODE_SHFT);
+
+		reg_val = clk_cfg[idx].m & CLK_CTL_RCG_MND_BMSK;
+		write32(&dfsr_clk->perf_m_dfsr[idx], reg_val);
+
+		reg_val = ~(clk_cfg[idx].n - clk_cfg[idx].m) & CLK_CTL_RCG_MND_BMSK;
+		write32(&dfsr_clk->perf_n_dfsr[idx], reg_val);
+
+		reg_val = ~(clk_cfg[idx].d_2) & CLK_CTL_RCG_MND_BMSK;
+		write32(&dfsr_clk->perf_d_dfsr[idx], reg_val);
+	}
 }
 
 void clock_configure_dfsr(int qup)
 {
-	clock_configure_dfsr_table(qup, qupv3_wrap_cfg,
-						ARRAY_SIZE(qupv3_wrap_cfg));
+	int s = get_qup_se_index(qup);
+	uint32_t qupv3_cfg_size = (s < 4) ? (ARRAY_SIZE(qupv3_wrap_cfg) - 1) :
+				ARRAY_SIZE(qupv3_wrap_cfg);
+
+	clock_configure_dfsr_table_x1p42100(qup, qupv3_wrap_cfg, qupv3_cfg_size);
 }
 static enum cb_err clock_configure_gpll0(void)
 {
diff --git a/src/soc/qualcomm/x1p42100/include/soc/addressmap.h b/src/soc/qualcomm/x1p42100/include/soc/addressmap.h
index 90c85bff59..4df4cc99eb 100644
--- a/src/soc/qualcomm/x1p42100/include/soc/addressmap.h
+++ b/src/soc/qualcomm/x1p42100/include/soc/addressmap.h
@@ -10,6 +10,9 @@
 #define TLMM_TILE_BASE			0x0F100000
 #define GCC_BASE			0x00100000
 #define NCC0_BASE			0x19A30000
+#define GCC_QUPV3_WRAP0_BASE		0x142004
+#define GCC_QUPV3_WRAP1_BASE		0x118004
+#define GCC_QUPV3_WRAP2_BASE		0x11e004
 
 #define CBMEM_TOP			0xC7800000
 /* X1P42100 NCC0 PLL CONFIG ADDRESSES */
diff --git a/src/soc/qualcomm/x1p42100/include/soc/clock.h b/src/soc/qualcomm/x1p42100/include/soc/clock.h
index 988bba9eea..a0a6eae8a0 100644
--- a/src/soc/qualcomm/x1p42100/include/soc/clock.h
+++ b/src/soc/qualcomm/x1p42100/include/soc/clock.h
@@ -447,6 +447,18 @@ check_member(x1p42100_gcc, apcs_pll_br_en, 0x52030);
 check_member(x1p42100_gcc, pcie_6_phy_gdscr, 0x8e000);
 check_member(x1p42100_gcc, pcie_6a_phy_bcr, 0xac01c);
 
+/* Generic QUPV3 wrapper structure - all wrappers have identical layout */
+struct x1p42100_qupv3_wrap {
+	struct qupv3_clock qupv3_s0;
+	struct qupv3_clock qupv3_s1;
+	struct qupv3_clock_v2 qupv3_s2;
+	struct qupv3_clock_v2 qupv3_s3;
+	struct qupv3_clock qupv3_s4;
+	struct qupv3_clock qupv3_s5;
+	struct qupv3_clock qupv3_s6;
+	struct qupv3_clock qupv3_s7;
+};
+
 enum clk_qup {
 	QUP_WRAP0_S0,
 	QUP_WRAP0_S1,
@@ -619,6 +631,8 @@ enum cb_err usb_clock_enable(enum clk_usb clk_type);
 enum cb_err clock_enable_usb_gdsc(enum clk_usb_gdsc gdsc_type);
 enum cb_err usb_prim_clock_enable(enum clk_usb_prim clk_type);
 enum cb_err usb_sec_clock_enable(enum clk_usb_sec clk_type);
+void clock_configure_dfsr_table_x1p42100(int qup, struct clock_freq_config *clk_cfg,
+		uint32_t num_perfs);
 
 void usb_clock_reset(enum clk_usb clk_type, bool assert);
 void usb_prim_clock_reset(enum clk_usb_prim clk_type, bool assert);
@@ -628,6 +642,9 @@ void usb_sec_clock_reset(enum clk_usb_sec clk_type, bool assert);
 static struct aoss *const aoss = (void *)AOSS_CC_BASE;
 static struct x1p42100_gcc *const gcc = (void *)GCC_BASE;
 static struct x1p42100_ncc0_clock *const apss_ncc0 = (void *)NCC0_BASE;
+static struct x1p42100_qupv3_wrap *const qup_wrap0_clk = (void *)GCC_QUPV3_WRAP0_BASE;
+static struct x1p42100_qupv3_wrap *const qup_wrap1_clk = (void *)GCC_QUPV3_WRAP1_BASE;
+static struct x1p42100_qupv3_wrap *const qup_wrap2_clk = (void *)GCC_QUPV3_WRAP2_BASE;
 
 /* Does nothing */
 #define clock_reset_aop() do {} while (0)

From a64dd410d82d81370a9d6734ed38e1d058d09339 Mon Sep 17 00:00:00 2001
From: Luca Lai <luca.lai@lcfc.corp-partner.google.com>
Date: Mon, 24 Nov 2025 14:01:13 +0800
Subject: [PATCH 2558/3886] mb/google/fatcat/var/ruby: Update EN_SPK_PA GPIO
 pin configuration

Update EN_SPK_PA pin configuration based on the schematic to enable speaker function.

schematics: RUBY_EVT_0902_2112.pdf

BUG=b:452216678
TEST=Build FW and boot to OS, verify that the speaker is functioning
by playing a YouTube video.

Change-Id: Iabb3e9d214841aaa155ce5b782740ad0722722fa
Signed-off-by: Luca Lai <luca.lai@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90169
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Derek Huang <derekhuang@google.com>
---
 src/mainboard/google/fatcat/variants/ruby/gpio.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/src/mainboard/google/fatcat/variants/ruby/gpio.c b/src/mainboard/google/fatcat/variants/ruby/gpio.c
index 51355e7f45..43449b778f 100644
--- a/src/mainboard/google/fatcat/variants/ruby/gpio.c
+++ b/src/mainboard/google/fatcat/variants/ruby/gpio.c
@@ -145,6 +145,8 @@ static const struct pad_config gpio_table[] = {
 	PAD_CFG_NF(GPP_C23, NONE, DEEP, NF2),
 	/* GPP_D00:     TP */
 	PAD_NC(GPP_D00, NONE),
+	/* GPP_D01:     EN_SPK_PA */
+	PAD_CFG_GPO(GPP_D01, 1, DEEP),
 	/* GPP_D02:     SOC_WP_OD */
 	PAD_CFG_GPI(GPP_D02, NONE, DEEP),
 	/* GPP_D03:     NC */

From 7d3bf767cc873bf8ef029e0e0a75dc2f9b2fb33a Mon Sep 17 00:00:00 2001
From: Yu-Ping Wu <yupingso@chromium.org>
Date: Fri, 31 Oct 2025 15:44:50 +0800
Subject: [PATCH 2559/3886] soc/mediatek/mt8189: Move WATCHDOG_TOMBSTONE from
 SRAM to SRAM_L2C

The purpose of the WATCHDOG_TOMBSTONE section is to temporarily record
the watchdog timeout event, before triggering the reboot. Then, in the
next boot, if WATCHDOG_TOMBSTONE contains the watchdog event magic, then
a watchdog event will be added to the event log.

The flow relies on the fact that the WATCHDOG_TOMBSTONE section can be
preserved across AP resets. However, for MT8189, the whole SRAM region
will be powered down during AP reset via GPIO AP_SYSRST_ODL (SYSRSTB).

Fortunately, the Kconfig option CHROMEOS_USE_EC_WATCHDOG_FLAG is also
enabled. Therefore, even if WATCHDOG_TOMBSTONE data is cleared, the
elog_handle_watchdog_tombstone() function can still obtain the correct
watchdog reset reason from EC.

On MT8189, L3C (used as SRAM_L2C) is powered on by default. Also, per
MT8189 PMIC configuration, a SYSRSTB reset will retain the L3C power.
Therefore, region data in SRAM_L2C can be preserved across AP resets.

Fix the WATCHDOG_TOMBSTONE preservation by moving it to SRAM_L2C.
Reduce PRERAM_CBMEM_CONSOLE by 1K for WATCHDOG_TOMBSTONE.

BUG=b:433636690, b:456672760
TEST=emerge-skywalker coreboot
TEST=watchdog event added to eventlog on WDT timeout
TEST=cbmem logs preserved on WDT timeout
BRANCH=skywalker

Change-Id: Id1cfc2700301ebb0b6399356b884b2473c883445
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90171
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Chen-Tsung Hsieh <chentsung@google.com>
---
 src/soc/mediatek/mt8189/include/soc/memlayout.ld | 10 +++++++---
 1 file changed, 7 insertions(+), 3 deletions(-)

diff --git a/src/soc/mediatek/mt8189/include/soc/memlayout.ld b/src/soc/mediatek/mt8189/include/soc/memlayout.ld
index 7e77a816ed..a9c867a58a 100644
--- a/src/soc/mediatek/mt8189/include/soc/memlayout.ld
+++ b/src/soc/mediatek/mt8189/include/soc/memlayout.ld
@@ -4,9 +4,12 @@
 
 SECTIONS
 {
-	/* MT8189 has 64KB SRAM. */
+	/*
+	 * MT8189 has 64KB SRAM. Per HW design, on SoC reset via GPIO
+	 * AP_SYSRST_ODL (SYSRSTB), SRAM will be powered down. That means
+	 * SRAM data will be lost across SoC resets.
+	 */
 	SRAM_START(0x00100000)
-	WATCHDOG_TOMBSTONE(0x00100030, 4)
 
 	/*
 	 * MCUPM uses the following regions to exchange data with kernel.
@@ -58,7 +61,8 @@ SECTIONS
 	DMA_COHERENT(0x020DC000, 4K)
 	STACK(0x020DD000, 15K)
 	TIMESTAMP(0x020E0C00, 1K)
-	PRERAM_CBMEM_CONSOLE(0x020E1000, 124K)
+	PRERAM_CBMEM_CONSOLE(0x020E1000, 123K)
+	WATCHDOG_TOMBSTONE(0x0020FFC00, 4)
 	SRAM_L2C_END(0x02100000)
 
 	DRAM_START(0x40000000)

From 1ae0cebff348b7cd23c1cf5a16ab87905cf201e7 Mon Sep 17 00:00:00 2001
From: Yu-Ping Wu <yupingso@chromium.org>
Date: Wed, 29 Oct 2025 15:15:28 +0800
Subject: [PATCH 2560/3886] soc/mediatek: Add Kconfig option
 MEDIATEK_WDT_RESET_BY_SW

When the watchdog timeout triggers a reset, the CPU will return to the
default frequency. If there is a mismatch between voltage and frequency,
the device will fail to reboot. Therefore, the kernel configuration
"mediatek,disable-extrst" is removed for MT8189, meaning the watchdog
timeout will trigger external reset, by notifying PMIC and EC via
AP_PMIC_WDTRST_L.

As we want to keep the watchdog status registers until coreboot runs,
the MT8189's EC simply ignores the external reset signal
AP_PMIC_WDTRST_L. Because EC ignores it, coreboot has to trigger the
secondary reset by another method other than watchdog hardware.

Therefore, introduce a Kconfig option MEDIATEK_WDT_RESET_BY_SW to
trigger the secondary reset by board_reset(), which is often implemented
by asserting a GPIO (for example GPIO_AP_EC_WARM_RST_REQ for MT8189).

BUG=b:433636690
TEST=emerge-skywalker coreboot
BRANCH=skywalker

Change-Id: Ib4c698bfd1b85705be05f40f385f4e252975c319
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90172
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Chen-Tsung Hsieh <chentsung@google.com>
---
 src/soc/mediatek/common/Kconfig |  9 +++++++++
 src/soc/mediatek/common/wdt.c   | 28 ++++++++++++++++++----------
 2 files changed, 27 insertions(+), 10 deletions(-)

diff --git a/src/soc/mediatek/common/Kconfig b/src/soc/mediatek/common/Kconfig
index 1f0f54ea7a..30cab53df6 100644
--- a/src/soc/mediatek/common/Kconfig
+++ b/src/soc/mediatek/common/Kconfig
@@ -60,6 +60,15 @@ config MEDIATEK_DSI_CPHY
 	help
 	  The configuration to support DSI C-PHY.
 
+config MEDIATEK_WDT_RESET_BY_SW
+	bool
+	default n
+	help
+	  This option allows triggering secondary watchdog (WDT) reset by the
+	  software driver, as opposed to by the watchdog hardware.
+	  If the kernel disables WDT external reset (mediatek,disable-extrst),
+	  then this option must be disabled to allow WDT hardware external reset.
+
 config MEMORY_TEST
 	bool
 	default y
diff --git a/src/soc/mediatek/common/wdt.c b/src/soc/mediatek/common/wdt.c
index e4038aae02..6c256366cf 100644
--- a/src/soc/mediatek/common/wdt.c
+++ b/src/soc/mediatek/common/wdt.c
@@ -5,6 +5,7 @@
 #include <device/mmio.h>
 #include <console/console.h>
 #include <halt.h>
+#include <reset.h>
 #include <soc/wdt.h>
 #include <vendorcode/google/chromeos/chromeos.h>
 
@@ -15,20 +16,27 @@ __weak void mtk_wdt_clear_efuse_ecc(void) { /* do nothing */ }
 static inline void mtk_wdt_swreset(void)
 {
 	/*
-	 * We trigger a secondary reset by triggering WDT hardware to send the
-	 * signal to EC.
-	 * We do not use do_board_reset() to send the signal to EC which is
-	 * controlled by software driver.
-	 * Before triggering the secondary reset, clean the data cache so the
-	 * logs in cbmem console (either in SRAM or DRAM) can be flushed.
+	 * We trigger a secondary reset by either do_board_reset() or WDT hardware,
+	 * both of which eventually send the signal to EC.
 	 */
 	printk(BIOS_INFO, "%s() called!\n", __func__);
 
-	dcache_clean_all();
+	/* Kick the watchdog to reset timer. */
 	write32(&mtk_wdt->wdt_restart, MTK_WDT_RESTART_KEY);
-	setbits32(&mtk_wdt->wdt_mode, MTK_WDT_MODE_EXTEN | MTK_WDT_MODE_KEY);
-	udelay(100);
-	write32(&mtk_wdt->wdt_swrst, MTK_WDT_SWRST_KEY);
+
+	if (CONFIG(MEDIATEK_WDT_RESET_BY_SW)) {
+		board_reset();
+	} else {
+		/*
+		 * Before triggering the secondary reset, clean the data cache so the
+		 * logs in cbmem console (either in SRAM or DRAM) can be flushed.
+		 */
+		dcache_clean_all();
+
+		setbits32(&mtk_wdt->wdt_mode, MTK_WDT_MODE_EXTEN | MTK_WDT_MODE_KEY);
+		udelay(100);
+		write32(&mtk_wdt->wdt_swrst, MTK_WDT_SWRST_KEY);
+	}
 
 	halt();
 }

From e4b0410946e9aee1036b85f3d1dbe2022570dcba Mon Sep 17 00:00:00 2001
From: Yu-Ping Wu <yupingso@chromium.org>
Date: Fri, 31 Oct 2025 15:41:14 +0800
Subject: [PATCH 2561/3886] soc/mediatek/mt8189: Enable
 MEDIATEK_WDT_RESET_BY_SW

For MT8189, watchdog external reset is enabled by kernel configuration,
and EC ignores the reset signal AP_PMIC_WDTRST_L. Therefore, enable
MEDIATEK_WDT_RESET_BY_SW to allow triggering the secondary watchdog
reset via software instead of watchdog hardware.

BUG=b:433636690
TEST=emerge-skywalker coreboot
TEST=watchdog event added to eventlog on WDT timeout
TEST=cbmem logs preserved on WDT timeout
BRANCH=skywalker

Change-Id: I5ab73a06dd1bd7848e2e166d4717a970043ea20a
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90173
Reviewed-by: Chen-Tsung Hsieh <chentsung@google.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/soc/mediatek/mt8189/Kconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/src/soc/mediatek/mt8189/Kconfig b/src/soc/mediatek/mt8189/Kconfig
index 786236478c..d4a0621a22 100644
--- a/src/soc/mediatek/mt8189/Kconfig
+++ b/src/soc/mediatek/mt8189/Kconfig
@@ -17,6 +17,7 @@ config SOC_MEDIATEK_MT8189
 	select FLASH_DUAL_IO_READ
 	select ARM64_USE_ARCH_TIMER
 	select MEDIATEK_DSI_CPHY
+	select MEDIATEK_WDT_RESET_BY_SW
 
 if SOC_MEDIATEK_MT8189
 

From f5f304a5f35c34801086048d4ece6e63131fc736 Mon Sep 17 00:00:00 2001
From: Yu-Ping Wu <yupingso@chromium.org>
Date: Tue, 4 Nov 2025 15:56:46 +0800
Subject: [PATCH 2562/3886] mb/google/skywalker: Disable
 CHROMEOS_USE_EC_WATCHDOG_FLAG

Now that we use the WATCHDOG_TOMBSTONE section to store the watchdog
event magic, there is no need to ask EC for the last reset reason. In
fact, with MEDIATEK_WDT_RESET_BY_SW enabled, EC doesn't even record the
watchdog reset reason.

Enable CHROMEOS_USE_EC_WATCHDOG_FLAG only if MEDIATEK_WDT_RESET_BY_SW is
disabled.

BUG=b:433636690
TEST=emerge-skywalker coreboot
TEST="elogtool list" contained "Hardware watchdog reset"
BRANCH=skywalker

Change-Id: Iac6ec72d5c148244ccbd7d1b02af78c359897d7d
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90174
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Chen-Tsung Hsieh <chentsung@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/google/skywalker/Kconfig | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/mainboard/google/skywalker/Kconfig b/src/mainboard/google/skywalker/Kconfig
index fe0c6a8edf..6e8848af94 100644
--- a/src/mainboard/google/skywalker/Kconfig
+++ b/src/mainboard/google/skywalker/Kconfig
@@ -26,7 +26,7 @@ config BOARD_SPECIFIC_OPTIONS
 	select SOC_MEDIATEK_MT8189
 	select BOARD_ROMSIZE_KB_8192
 	select MAINBOARD_HAS_CHROMEOS
-	select CHROMEOS_USE_EC_WATCHDOG_FLAG if CHROMEOS
+	select CHROMEOS_USE_EC_WATCHDOG_FLAG if CHROMEOS && !MEDIATEK_WDT_RESET_BY_SW
 	select COMMON_CBFS_SPI_WRAPPER
 	select SPI_FLASH
 	select SPI_FLASH_INCLUDE_ALL_DRIVERS

From 5a4c7495202a70b400ee626688c16279fd2180e2 Mon Sep 17 00:00:00 2001
From: Uwe Poeche <uwe.poeche@siemens.com>
Date: Fri, 4 Jul 2025 14:26:41 +0200
Subject: [PATCH 2563/3886] mb/siemens/mc_ehl6: Add new board variant based on
 mc_ehl2

This new mainboard variant for the Siemens mc_ehl6 is initially based on
a direct copy of the mc_ehl2 configuration. This commit contains the
basic board setup with only minimal changes to enable the new variant.

Further specific adaptations for the mc_ehl6 hardware will be handled
in subsequent commits.

Change-Id: Ifcc730da492edb084e67762ce643f27b1a2576b0
Signed-off-by: Uwe Poeche <uwe.poeche@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90081
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
---
 src/mainboard/siemens/mc_ehl/Kconfig          |   5 +
 src/mainboard/siemens/mc_ehl/Kconfig.name     |   3 +
 .../siemens/mc_ehl/variants/mc_ehl6/Kconfig   |  24 ++
 .../mc_ehl/variants/mc_ehl6/Makefile.mk       |   6 +
 .../mc_ehl/variants/mc_ehl6/devicetree.cb     | 250 ++++++++++++++++++
 .../siemens/mc_ehl/variants/mc_ehl6/gpio.c    | 157 +++++++++++
 .../mc_ehl/variants/mc_ehl6/mainboard.c       |  69 +++++
 .../siemens/mc_ehl/variants/mc_ehl6/memory.c  |  48 ++++
 8 files changed, 562 insertions(+)
 create mode 100644 src/mainboard/siemens/mc_ehl/variants/mc_ehl6/Kconfig
 create mode 100644 src/mainboard/siemens/mc_ehl/variants/mc_ehl6/Makefile.mk
 create mode 100644 src/mainboard/siemens/mc_ehl/variants/mc_ehl6/devicetree.cb
 create mode 100644 src/mainboard/siemens/mc_ehl/variants/mc_ehl6/gpio.c
 create mode 100644 src/mainboard/siemens/mc_ehl/variants/mc_ehl6/mainboard.c
 create mode 100644 src/mainboard/siemens/mc_ehl/variants/mc_ehl6/memory.c

diff --git a/src/mainboard/siemens/mc_ehl/Kconfig b/src/mainboard/siemens/mc_ehl/Kconfig
index 651cef7ce1..0841e1d486 100644
--- a/src/mainboard/siemens/mc_ehl/Kconfig
+++ b/src/mainboard/siemens/mc_ehl/Kconfig
@@ -26,6 +26,9 @@ config BOARD_SIEMENS_MC_EHL4
 config BOARD_SIEMENS_MC_EHL5
 	select BOARD_SIEMENS_BASEBOARD_MC_EHL
 
+config BOARD_SIEMENS_MC_EHL6
+	select BOARD_SIEMENS_BASEBOARD_MC_EHL
+
 source "src/mainboard/siemens/mc_ehl/variants/*/Kconfig"
 
 if BOARD_SIEMENS_BASEBOARD_MC_EHL
@@ -39,6 +42,7 @@ config VARIANT_DIR
 	default "mc_ehl3" if BOARD_SIEMENS_MC_EHL3
 	default "mc_ehl4" if BOARD_SIEMENS_MC_EHL4
 	default "mc_ehl5" if BOARD_SIEMENS_MC_EHL5
+	default "mc_ehl6" if BOARD_SIEMENS_MC_EHL6
 
 config MAINBOARD_PART_NUMBER
 	default "MC EHL1" if BOARD_SIEMENS_MC_EHL1
@@ -46,6 +50,7 @@ config MAINBOARD_PART_NUMBER
 	default "MC EHL3" if BOARD_SIEMENS_MC_EHL3
 	default "MC EHL4" if BOARD_SIEMENS_MC_EHL4
 	default "MC EHL5" if BOARD_SIEMENS_MC_EHL5
+	default "MC EHL6" if BOARD_SIEMENS_MC_EHL6
 
 config DEVICETREE
 	default "variants/\$(CONFIG_VARIANT_DIR)/devicetree.cb"
diff --git a/src/mainboard/siemens/mc_ehl/Kconfig.name b/src/mainboard/siemens/mc_ehl/Kconfig.name
index c419a0cd87..50233cea9c 100644
--- a/src/mainboard/siemens/mc_ehl/Kconfig.name
+++ b/src/mainboard/siemens/mc_ehl/Kconfig.name
@@ -16,3 +16,6 @@ config BOARD_SIEMENS_MC_EHL4
 
 config BOARD_SIEMENS_MC_EHL5
 	bool "-> MC EHL5"
+
+config BOARD_SIEMENS_MC_EHL6
+	bool "-> MC EHL6"
diff --git a/src/mainboard/siemens/mc_ehl/variants/mc_ehl6/Kconfig b/src/mainboard/siemens/mc_ehl/variants/mc_ehl6/Kconfig
new file mode 100644
index 0000000000..8ebeec9679
--- /dev/null
+++ b/src/mainboard/siemens/mc_ehl/variants/mc_ehl6/Kconfig
@@ -0,0 +1,24 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
+if BOARD_SIEMENS_MC_EHL6
+
+config BOARD_SPECIFIC_OPTIONS
+	def_bool y
+	select DRIVERS_I2C_RV3028C7
+	select DRIVER_INTEL_I210
+	select SOC_INTEL_COMMON_BLOCK_LPC_COMB_ENABLE
+	select EHL_TSN_DRIVER
+	select DRIVERS_ETH_PHY_M88E1512
+	select MAINBOARD_HAS_TPM2
+	select MEMORY_MAPPED_TPM
+	select TPM_MEASURED_BOOT
+	select TPM_MEASURED_BOOT_INIT_BOOTBLOCK
+
+config FMDFILE
+	default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/mc_ehl.fmd"
+
+config UART_FOR_CONSOLE
+	int
+	default 0
+
+endif # BOARD_SIEMENS_MC_EHL6
diff --git a/src/mainboard/siemens/mc_ehl/variants/mc_ehl6/Makefile.mk b/src/mainboard/siemens/mc_ehl/variants/mc_ehl6/Makefile.mk
new file mode 100644
index 0000000000..6e87f9fc1a
--- /dev/null
+++ b/src/mainboard/siemens/mc_ehl/variants/mc_ehl6/Makefile.mk
@@ -0,0 +1,6 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
+bootblock-y += gpio.c
+romstage-y += memory.c
+ramstage-y += gpio.c
+ramstage-y += mainboard.c
diff --git a/src/mainboard/siemens/mc_ehl/variants/mc_ehl6/devicetree.cb b/src/mainboard/siemens/mc_ehl/variants/mc_ehl6/devicetree.cb
new file mode 100644
index 0000000000..67ece6d158
--- /dev/null
+++ b/src/mainboard/siemens/mc_ehl/variants/mc_ehl6/devicetree.cb
@@ -0,0 +1,250 @@
+chip soc/intel/elkhartlake
+
+	device cpu_cluster 0 on end
+
+	# GPE configuration
+	# Note that GPE events called out in ASL code rely on this
+	# route. i.e. If this route changes then the affected GPE
+	# offset bits also need to be changed.
+	register "pmc_gpe0_dw0" = "GPP_B"
+	register "pmc_gpe0_dw1" = "GPP_F"
+	register "pmc_gpe0_dw2" = "GPP_E"
+
+	# FSP configuration
+	register "SaGv" = "SaGv_Disabled"
+
+	# Enable IBECC for the complete memory
+	register "ibecc" = "{
+		.enable = 1,
+		.mode = IBECC_ALL
+	}"
+
+	# USB related UPDs
+	register "usb2_ports[0]" = "USB2_PORT_MID(OC2)"	# X125/X135
+	register "usb2_ports[1]" = "USB2_PORT_MID(OC2)"	# X125/X135
+	register "usb2_ports[2]" = "USB2_PORT_MID(OC0)"	# X145/X155
+	register "usb2_ports[3]" = "USB2_PORT_MID(OC0)"	# X145/X155
+	register "usb2_ports[4]" = "USB2_PORT_MID(OC3)"	# USB Panel
+	register "usb2_ports[5]" = "USB2_PORT_MID(OC3)"	# USB Panel
+	register "usb2_ports[6]" = "USB2_PORT_EMPTY"
+	register "usb2_ports[7]" = "USB2_PORT_EMPTY"
+	register "usb2_ports[8]" = "USB2_PORT_EMPTY"
+	register "usb2_ports[9]" = "USB2_PORT_EMPTY"
+
+	register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)"	# USB3/2 Type A port1
+	register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)"	# USB3/2 Type A port2
+	register "usb3_ports[2]" = "USB3_PORT_EMPTY"	# UNUSED
+	register "usb3_ports[3]" = "USB3_PORT_EMPTY"	# UNUSED
+
+	# Skip the CPU replacement check
+	register "SkipCpuReplacementCheck" = "1"
+
+	# PCIe root ports related UPDs
+	register "PcieClkSrcUsage[0]" = "PCIE_CLK_NOTUSED"
+	register "PcieClkSrcUsage[1]" = "PCIE_CLK_FREE"
+	register "PcieClkSrcUsage[2]" = "PCIE_CLK_NOTUSED"
+	register "PcieClkSrcUsage[3]" = "PCIE_CLK_NOTUSED"
+	register "PcieClkSrcUsage[4]" = "PCIE_CLK_FREE"
+	register "PcieClkSrcUsage[5]" = "PCIE_CLK_NOTUSED"
+
+	register "PcieClkSrcClkReq[0]" = "PCIE_CLK_NOTUSED"
+	register "PcieClkSrcClkReq[1]" = "PCIE_CLK_NOTUSED"
+	register "PcieClkSrcClkReq[2]" = "PCIE_CLK_NOTUSED"
+	register "PcieClkSrcClkReq[3]" = "PCIE_CLK_NOTUSED"
+	register "PcieClkSrcClkReq[4]" = "PCIE_CLK_NOTUSED"
+	register "PcieClkSrcClkReq[5]" = "PCIE_CLK_NOTUSED"
+
+	# Disable all L1 substates for PCIe root ports
+	register "PcieRpL1Substates[1]" = "L1_SS_DISABLED"
+	register "PcieRpL1Substates[6]" = "L1_SS_DISABLED"
+
+	# Disable LTR for all PCIe root ports
+	register "PcieRpLtrDisable[1]" = "true"
+	register "PcieRpLtrDisable[6]" = "true"
+
+	# Storage (SDCARD/EMMC) related UPDs
+	register "ScsEmmcHs400Enabled" = "0"
+	register "ScsEmmcDdr50Enabled" = "1"
+	register "SdCardPowerEnableActiveHigh" = "1"
+
+	# GPIO for SD card detect
+	register "sdcard_cd_gpio" = "GPP_G5"
+
+	# LPSS Serial IO (I2C/UART/GSPI) related UPDs
+	register "SerialIoI2cMode" = "{
+		[PchSerialIoIndexI2C0] = PchSerialIoPci,
+		[PchSerialIoIndexI2C1] = PchSerialIoPci,
+		[PchSerialIoIndexI2C2] = PchSerialIoPci,
+		[PchSerialIoIndexI2C3] = PchSerialIoPci,
+		[PchSerialIoIndexI2C4] = PchSerialIoPci,
+		[PchSerialIoIndexI2C5] = PchSerialIoPci,
+		[PchSerialIoIndexI2C6] = PchSerialIoDisabled,
+		[PchSerialIoIndexI2C7] = PchSerialIoDisabled,
+	}"
+
+	register "SerialIoUartMode" = "{
+		[PchSerialIoIndexUART0] = PchSerialIoPci,
+		[PchSerialIoIndexUART1] = PchSerialIoPci,
+		[PchSerialIoIndexUART2] = PchSerialIoPci,
+	}"
+
+	register "SerialIoUartDmaEnable" = "{
+		[PchSerialIoIndexUART0] = 1,
+		[PchSerialIoIndexUART1] = 1,
+		[PchSerialIoIndexUART2] = 1,
+	}"
+
+	# TSN GBE related UPDs
+	register "PchTsnGbeLinkSpeed" = "Tsn_1_Gbps"
+	register "PchTsnGbeSgmiiEnable" = "1"
+	register "PseDmaOwn[0]" = "Host_Owned"
+	register "PseDmaOwn[1]" = "Host_Owned"
+	register "pch_tsn_phy_irq_edge" = "RISING_EDGE"
+	register "pse_tsn_phy_irq_edge[0]" = "RISING_EDGE"
+	register "pse_tsn_phy_irq_edge[1]" = "RISING_EDGE"
+
+	register "common_soc_config" = "{
+		.i2c[1] = {
+			.speed = I2C_SPEED_STANDARD,
+			.speed_config[0] = {
+				.speed = I2C_SPEED_STANDARD,
+				.scl_hcnt = 0x1e1,
+				.scl_lcnt = 0x1f4,
+				.sda_hold = 0x64
+			},
+		},
+		.i2c[2] = {
+			.speed = I2C_SPEED_STANDARD,
+			.speed_config[0] = {
+				.speed = I2C_SPEED_STANDARD,
+				.scl_hcnt = 0x1df,
+				.scl_lcnt = 0x1f4,
+				.sda_hold = 0x64
+			},
+		},
+	}"
+
+	# FIVR related settings
+	register "fivr" = "{
+		.fivr_config_en = true,
+		.vcc_low_high_us = 50,
+	}"
+
+	# Disable L1 prefetcher for real-time demands
+	register "L1_prefetcher_disable" = "true"
+
+	# Enable real-time tuning
+	register "realtime_tuning_enable" = "true"
+
+	device domain 0 on
+		device pci 00.0 on	end # Host Bridge
+		device pci 02.0 on	end # Integrated Graphics Device
+
+		device pci 14.0 on	end # USB3.1 xHCI
+
+		device pci 15.0 on	end # I2C0
+		device pci 15.1 on	    # I2C1
+			# Enable external RTC chip
+			chip drivers/i2c/rv3028c7
+				register "bus_speed" = "I2C_SPEED_STANDARD"
+				register "set_user_date" = "1"
+				register "user_year" = "04"
+				register "user_month" = "07"
+				register "user_day" = "01"
+				register "user_weekday" = "4"
+				register "bckup_sw_mode" = "BACKUP_SW_LEVEL"
+				register "cap_charge" = "CHARGE_OFF"
+				device i2c 0x52 on end  # RTC RV3028-C7
+			end
+		end
+		device pci 15.2 on	    # I2C2
+		# Add dummy I2C device to limit BUS speed to 100 kHz in OS
+			chip drivers/i2c/generic
+				register "hid" = ""PRP0001""
+				register "speed" = "I2C_SPEED_STANDARD"
+				device i2c 0x7f on end
+			end
+		end
+		device pci 15.3 on	end # I2C3
+
+		device pci 16.0 hidden	end # Management Engine Interface 1
+
+		device pci 19.0 on	end # I2C4
+		device pci 19.1 on	end # I2C5
+		device pci 19.2 on	end # UART2
+
+		device pci 1a.0 on	end # eMMC
+		device pci 1a.1 on	end # SD
+
+		device pci 1c.1 on	end # RP2 (pcie0 single VC)
+		device pci 1c.6 on	end # RP7 (pcie3 multi VC)
+
+		device pci 1d.0 off	end # Intel PSE IPC (local host to PSE)
+		device pci 1d.1 on	    # Intel PSE Time-Sensitive Networking GbE 0
+			# Enable external Marvell PHY 88E1512
+			chip drivers/net/phy/m88e1512
+				register "configure_leds" = "true"
+				# LED[0]: On - 1000 Mbps Link, Off - Else
+				register "led_0_ctrl" = "7"
+				# LED[1]: On - Link, Blink - Activity, Off - No Link
+				register "led_1_ctrl" = "1"
+				# INTn is routed to LED[2] pin
+				register "enable_int" = "true"
+				register "downshift_cnt" = "2"
+				register "force_mos" = "true"
+				register "pmos_val" = "0xF"
+				register "nmos_val" = "0xA"
+				device mdio 0 on    # PHY address
+					ops m88e1512_ops
+				end
+			end
+		end
+		device pci 1d.2 on	    # Intel PSE Time-Sensitive Networking GbE 1
+			# Enable external Marvell PHY 88E1512
+			chip drivers/net/phy/m88e1512
+				register "configure_leds" = "true"
+				# LED[0]: On - 1000 Mbps Link, Off - Else
+				register "led_0_ctrl" = "7"
+				# LED[1]: On - Link, Blink - Activity, Off - No Link
+				register "led_1_ctrl" = "1"
+				# INTn is routed to LED[2] pin
+				register "enable_int" = "true"
+				register "downshift_cnt" = "2"
+				register "force_mos" = "true"
+				register "pmos_val" = "0xF"
+				register "nmos_val" = "0xA"
+				device mdio 1 on    # PHY address
+					ops m88e1512_ops
+				end
+			end
+		end
+
+		device pci 1e.0 on	end # UART0
+		device pci 1e.1 on	end # UART1
+		device pci 1e.4 on	    # PCH Time-Sensitive Networking GbE
+			# Enable external Marvell PHY 88E1512
+			chip drivers/net/phy/m88e1512
+				register "configure_leds" = "true"
+				# LED[0]: On - 1000 Mbps Link, Off - Else
+				register "led_0_ctrl" = "7"
+				# LED[1]: On - Link, Blink - Activity, Off - No Link
+				register "led_1_ctrl" = "1"
+				# INTn is routed to LED[2] pin
+				register "enable_int" = "true"
+				register "downshift_cnt" = "2"
+				device mdio 1 on    # PHY address
+					ops m88e1512_ops
+				end
+			end
+		end
+
+		device pci 1f.0 on	    # eSPI Interface
+			chip drivers/pc80/tpm
+				device pnp 0c31.0 on end
+			end
+		end
+		device pci 1f.2 hidden	end # Power Management Controller
+		device pci 1f.4	on	end # SMBus
+		device pci 1f.5 on	end # PCH SPI (flash & TPM)
+	end
+end
diff --git a/src/mainboard/siemens/mc_ehl/variants/mc_ehl6/gpio.c b/src/mainboard/siemens/mc_ehl/variants/mc_ehl6/gpio.c
new file mode 100644
index 0000000000..63a13bba7b
--- /dev/null
+++ b/src/mainboard/siemens/mc_ehl/variants/mc_ehl6/gpio.c
@@ -0,0 +1,157 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <baseboard/variants.h>
+#include <commonlib/helpers.h>
+
+/* Pad configuration in ramstage */
+static const struct pad_config gpio_table[] = {
+	/* Community 0 - GpioGroup GPP_B */
+	PAD_CFG_NF(GPP_B2, NONE, PLTRST, NF1),		/* PMC_VRALERT_N */
+	PAD_CFG_NF(GPP_B3, NONE, PLTRST, NF4),		/* ESPI_ALERT0_N */
+	PAD_NC(GPP_B4, NONE),				/* Not connected */
+	PAD_NC(GPP_B9, NONE),				/* Not connected */
+	PAD_NC(GPP_B10, NONE),				/* Not connected */
+	PAD_CFG_NF(GPP_B11, NONE, PLTRST, NF1),		/* PMC_ALERT_N */
+	PAD_NC(GPP_B14, NONE),				/* Not connected */
+	PAD_NC(GPP_B15, NONE),				/* Not connected */
+	PAD_NC(GPP_B18, NONE),				/* Not connected */
+	PAD_NC(GPP_B19, NONE),				/* Not connected */
+	PAD_NC(GPP_B23, NONE),				/* Not connected */
+
+	/* Community 0 - GpioGroup GPP_T */
+	PAD_CFG_NF(GPP_T4, NONE, DEEP, NF1),		/* PSE_GBE0_INT */
+	PAD_CFG_GPO(GPP_T5, 1, DEEP),			/* PSE_GBE0_RST_N */
+	PAD_CFG_NF(GPP_T6, NONE, DEEP, NF1),		/* PSE_GBE0_AUXTS */
+	PAD_CFG_NF(GPP_T7, NONE, DEEP, NF1),		/* PSE_GBE0_PPS */
+	PAD_CFG_NF(GPP_T12, NONE, DEEP, NF2),		/* SIO_UART0_RXD */
+	PAD_CFG_NF(GPP_T13, NONE, DEEP, NF2),		/* SIO_UART0_TXD */
+
+	/* Community 0 - GpioGroup GPP_G */
+	PAD_NC(GPP_G8, NONE),				/* Not connected */
+	PAD_NC(GPP_G9, NONE),				/* Not connected */
+	PAD_CFG_GPI(GPP_G19, UP_20K, PLTRST),		/* TPM_IRQ_N */
+
+	/* Community 1 - GpioGroup GPP_V */
+	PAD_CFG_NF(GPP_V0, UP_20K, DEEP, NF1),		/* EMMC_CMD */
+	PAD_CFG_NF(GPP_V1, UP_20K, DEEP, NF1),		/* EMMC_DATA0 */
+	PAD_CFG_NF(GPP_V2, UP_20K, DEEP, NF1),		/* EMMC_DATA1 */
+	PAD_CFG_NF(GPP_V3, UP_20K, DEEP, NF1),		/* EMMC_DATA2 */
+	PAD_CFG_NF(GPP_V4, UP_20K, DEEP, NF1),		/* EMMC_DATA3 */
+	PAD_CFG_NF(GPP_V5, UP_20K, DEEP, NF1),		/* EMMC_DATA4 */
+	PAD_CFG_NF(GPP_V6, UP_20K, DEEP, NF1),		/* EMMC_DATA5 */
+	PAD_CFG_NF(GPP_V7, UP_20K, DEEP, NF1),		/* EMMC_DATA6 */
+	PAD_CFG_NF(GPP_V8, UP_20K, DEEP, NF1),		/* EMMC_DATA7 */
+	PAD_CFG_NF(GPP_V9, DN_20K, DEEP, NF1),		/* EMMC_RCLK */
+	PAD_CFG_NF(GPP_V10, DN_20K, DEEP, NF1),		/* EMMC_CLK */
+	PAD_CFG_NF(GPP_V11, NONE, DEEP, NF1),		/* EMMC_RESET */
+
+	/* Community 1 - GpioGroup GPP_H */
+	PAD_CFG_NF(GPP_H0, NONE, DEEP, NF1),		/* PSE_GBE1_INT */
+	PAD_CFG_GPO(GPP_H1, 1, DEEP),			/* PSE_GBE1_RST_N */
+	PAD_CFG_NF(GPP_H2, NONE, DEEP, NF1),		/* PSE_GBE1_AUXTS */
+	PAD_CFG_NF(GPP_H3, NONE, DEEP, NF1),		/* PSE_GBE1_PPS */
+	PAD_CFG_NF(GPP_H10, NONE, DEEP, NF1),		/* PCIE_CLKREQ4_N */
+	PAD_CFG_NF(GPP_H11, NONE, DEEP, NF1),		/* PCIE_CLKREQ5_N */
+
+	/* Community 1 - GpioGroup GPP_D */
+	PAD_CFG_NF(GPP_D5, NONE, DEEP, NF1),		/* PCIE_CLKREQ0_N */
+	PAD_CFG_NF(GPP_D6, NONE, DEEP, NF1),		/* PCIE_CLKREQ1_N */
+	PAD_CFG_NF(GPP_D7, NONE, DEEP, NF1),		/* PCIE_CLKREQ2_N */
+	PAD_CFG_NF(GPP_D8, NONE, DEEP, NF1),		/* PCIE_CLKREQ3_N */
+
+	/* Community 1 - GpioGroup GPP_U */
+	PAD_CFG_NF(GPP_U0, NONE, DEEP, NF1),		/* GBE_INT */
+	PAD_CFG_GPO(GPP_U1, 1, DEEP),			/* GBE_RST_N */
+	PAD_NC(GPP_U12, NONE),				/* Not connected */
+	PAD_NC(GPP_U13, NONE),				/* Not connected */
+	PAD_NC(GPP_U16, NONE),				/* Not connected */
+	PAD_NC(GPP_U17, NONE),				/* Not connected */
+	PAD_NC(GPP_U18, NONE),				/* Not connected */
+
+	/* Community 2 - GpioGroup DSW */
+	PAD_CFG_NF(GPD1, NONE, PLTRST, NF1),		/* ACPRESENT */
+	PAD_NC(GPD9, NONE),				/* Not connected */
+	PAD_NC(GPD11, NONE),				/* Not connected */
+
+	/* Community 3 - GpioGroup GPP_S */
+	PAD_NC(GPP_S0, NONE),				/* Not connected */
+	PAD_NC(GPP_S1, NONE),				/* Not connected */
+
+	/* Community 3 - GpioGroup GPP_A */
+	PAD_CFG_NF(GPP_A0, NONE, DEEP, NF1),		/* PSE_GBE0_RGMII_TXD3 */
+	PAD_CFG_NF(GPP_A1, NONE, DEEP, NF1),		/* PSE_GBE0_RGMII_TXD2 */
+	PAD_CFG_NF(GPP_A2, NONE, DEEP, NF1),		/* PSE_GBE0_RGMII_TXD1 */
+	PAD_CFG_NF(GPP_A3, NONE, DEEP, NF1),		/* PSE_GBE0_RGMII_TXD0 */
+	PAD_CFG_NF(GPP_A4, NONE, DEEP, NF1),		/* PSE_GBE0_RGMII_TXCLK */
+	PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1),		/* PSE_GBE0_RGMII_TXCTL */
+	PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1),		/* PSE_GBE0_RGMII_RXCLK */
+	PAD_CFG_NF(GPP_A7, NONE, DEEP, NF1),		/* PSE_GBE0_RGMII_RXD3 */
+	PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1),		/* PSE_GBE0_RGMII_RXD2 */
+	PAD_CFG_NF(GPP_A9, NONE, DEEP, NF1),		/* PSE_GBE0_RGMII_RXD1 */
+	PAD_CFG_NF(GPP_A10, NONE, DEEP, NF1),		/* PSE_GBE0_RGMII_RXD0 */
+	PAD_CFG_NF(GPP_A11, NONE, DEEP, NF1),		/* PSE_GBE1_RGMII_TXD3 */
+	PAD_CFG_NF(GPP_A12, NONE, DEEP, NF1),		/* PSE_GBE1_RGMII_TXD2 */
+	PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1),		/* PSE_GBE1_RGMII_TXD1 */
+	PAD_CFG_NF(GPP_A14, NONE, DEEP, NF1),		/* PSE_GBE1_RGMII_TXD0 */
+	PAD_CFG_NF(GPP_A15, NONE, DEEP, NF1),		/* PSE_GBE1_RGMII_TXCLK */
+	PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1),		/* PSE_GBE1_RGMII_TXCTL */
+	PAD_CFG_NF(GPP_A17, NONE, DEEP, NF1),		/* PSE_GBE1_RGMII_RXCLK */
+	PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1),		/* PSE_GBE1_RGMII_RXCTL */
+	PAD_CFG_NF(GPP_A19, NONE, DEEP, NF1),		/* PSE_GBE1_RGMII_RXD3 */
+	PAD_CFG_NF(GPP_A20, NONE, DEEP, NF1),		/* PSE_GBE1_RGMII_RXD2 */
+	PAD_CFG_NF(GPP_A21, NONE, DEEP, NF1),		/* PSE_GBE1_RGMII_RXD1 */
+	PAD_CFG_NF(GPP_A22, NONE, DEEP, NF1),		/* PSE_GBE1_RGMII_RXD0 */
+	PAD_CFG_NF(GPP_A23, NONE, DEEP, NF1),		/* PSE_GBE0_RGMII_RXCTL */
+
+	/* Community 4 - GpioGroup GPP_C */
+	PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1),		/* PSE_GBE0_MDC */
+	PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1),		/* PSE_GBE0_MDIO */
+	PAD_CFG_NF(GPP_C6, NONE, DEEP, NF1),		/* PSE_GBE1_MDC */
+	PAD_CFG_NF(GPP_C7, NONE, DEEP, NF1),		/* PSE_GBE1_MDIO */
+	PAD_NC(GPP_C8, NONE),				/* Not connected */
+	PAD_CFG_NF(GPP_C12, NONE, DEEP, NF4),		/* SIO_UART1_RXD */
+	PAD_CFG_NF(GPP_C13, NONE, DEEP, NF4),		/* SIO_UART1_TXD */
+	PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1),		/* GBE_MDIO */
+	PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1),		/* GBE_MDC */
+
+	/* Community 4 - GpioGroup GPP_F */
+	PAD_NC(GPP_F1, NONE),				/* Not connected */
+	PAD_NC(GPP_F3, NONE),				/* Not connected */
+	PAD_NC(GPP_F8, NONE),				/* Not connected */
+	PAD_NC(GPP_F11, NONE),				/* Not connected */
+	PAD_NC(GPP_F12, NONE),				/* Not connected */
+	PAD_NC(GPP_F13, NONE),				/* Not connected */
+	PAD_NC(GPP_F14, NONE),				/* Not connected */
+	PAD_NC(GPP_F15, NONE),				/* Not connected */
+	PAD_NC(GPP_F16, NONE),				/* Not connected */
+	PAD_NC(GPP_F17, NONE),				/* Not connected */
+	PAD_CFG_GPO(GPP_F20, 0, DEEP),			/* LED_BIOS_DONE */
+
+	/* Community 4 - GpioGroup GPP_E */
+	PAD_CFG_NF(GPP_E0, NONE, DEEP, NF1),		/* SATA_LED_N */
+	PAD_CFG_NF(GPP_E8, NONE, DEEP, NF2),		/* M.2_SSD_SATA_DEVSLP_1 */
+	PAD_NC(GPP_E15, NONE),				/* Not connected */
+	PAD_NC(GPP_E16, NONE),				/* Not connected */
+	PAD_NC(GPP_E18, NONE),				/* Not connected */
+	PAD_NC(GPP_E19, NONE),				/* Not connected */
+	PAD_NC(GPP_E23, NONE),				/* Not connected */
+
+	/* Community 5 - GpioGroup GPP_R */
+	PAD_NC(GPP_R1, NONE),				/* Not connected */
+	PAD_NC(GPP_R3, NONE),				/* Not connected */
+};
+
+/* Early pad configuration in bootblock */
+static const struct pad_config early_gpio_table[] = {};
+
+const struct pad_config *variant_gpio_table(size_t *num)
+{
+	*num = ARRAY_SIZE(gpio_table);
+	return gpio_table;
+}
+
+const struct pad_config *variant_early_gpio_table(size_t *num)
+{
+	*num = ARRAY_SIZE(early_gpio_table);
+	return early_gpio_table;
+}
diff --git a/src/mainboard/siemens/mc_ehl/variants/mc_ehl6/mainboard.c b/src/mainboard/siemens/mc_ehl/variants/mc_ehl6/mainboard.c
new file mode 100644
index 0000000000..b3846196fc
--- /dev/null
+++ b/src/mainboard/siemens/mc_ehl/variants/mc_ehl6/mainboard.c
@@ -0,0 +1,69 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <baseboard/variants.h>
+#include <bootstate.h>
+#include <device/pci_ids.h>
+#include <gpio.h>
+#include <intelblocks/pcr.h>
+#include <soc/pci_devs.h>
+#include <soc/pcr_ids.h>
+
+#define HOSTCTRL2		0x3E
+#define  HOSTCTRL2_PRESET	(1 << 15)
+#define MMC_CAP_BYP		0x810
+#define  MMC_CAP_BYP_EN		0x5A
+#define MMC_CAP_BYP_REG1	0x814
+#define  MMC_CAP_BYP_SDR50	(1 << 13)
+#define  MMC_CAP_BYP_SDR104	(1 << 14)
+#define  MMC_CAP_BYP_DDR50	(1 << 15)
+
+/* Disable SDR104 and SDR50 mode while keeping DDR50 mode enabled. */
+static void disable_sdr_modes(struct resource *res)
+{
+	write32(res2mmio(res, MMC_CAP_BYP, 0), MMC_CAP_BYP_EN);
+	clrsetbits32(res2mmio(res, MMC_CAP_BYP_REG1, 0),
+			MMC_CAP_BYP_SDR104 | MMC_CAP_BYP_SDR50,
+			MMC_CAP_BYP_DDR50);
+}
+
+void variant_mainboard_final(void)
+{
+	struct device *dev;
+
+	/* PIR8 register mapping for PCIe root ports
+	   INTA#->PIRQC#, INTB#->PIRQD#, INTC#->PIRQA#, INTD#-> PIRQB# */
+	pcr_write16(PID_ITSS, 0x3150, 0x1032);
+
+	/* Disable clock outputs 1-5 (CLKOUT) for XIO2001 PCIe to PCI Bridge. */
+	dev = dev_find_device(PCI_VID_TI, PCI_DID_TI_XIO2001, 0);
+	if (dev)
+		pci_write_config8(dev, 0xd8, 0x3e);
+
+	dev = pcidev_path_on_root(PCH_DEVFN_SDCARD);
+	if (dev) {
+		struct resource *res = probe_resource(dev, PCI_BASE_ADDRESS_0);
+		if (res) {
+			disable_sdr_modes(res);
+
+			/* Use preset driver strength from preset value
+			   registers. */
+			clrsetbits16(res2mmio(res, HOSTCTRL2, 0), 0,
+					HOSTCTRL2_PRESET);
+		}
+	}
+
+	dev = pcidev_path_on_root(PCH_DEVFN_EMMC);
+	if (dev) {
+		struct resource *res = probe_resource(dev, PCI_BASE_ADDRESS_0);
+		if (res)
+			disable_sdr_modes(res);
+	}
+}
+
+static void finalize_boot(void *unused)
+{
+	/* Set coreboot ready LED. */
+	gpio_output(GPP_F20, 1);
+}
+
+BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_BOOT, BS_ON_ENTRY, finalize_boot, NULL);
diff --git a/src/mainboard/siemens/mc_ehl/variants/mc_ehl6/memory.c b/src/mainboard/siemens/mc_ehl/variants/mc_ehl6/memory.c
new file mode 100644
index 0000000000..551583394b
--- /dev/null
+++ b/src/mainboard/siemens/mc_ehl/variants/mc_ehl6/memory.c
@@ -0,0 +1,48 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <baseboard/variants.h>
+#include <gpio.h>
+#include <soc/meminit.h>
+#include <soc/romstage.h>
+
+static const struct mb_cfg mc_ehl_lpddr4x_memcfg_cfg = {
+	.dq_map[DDR_CH0] = {
+		{0xf, 0xf0}, {0xf, 0xf0}, {0xff, 0x0}, {0x0, 0x0}, {0x0, 0x0}, {0x0, 0x0}
+	},
+
+	.dq_map[DDR_CH1] = {
+		{0xf, 0xf0}, {0xf, 0xf0}, {0xff, 0x0}, {0x0, 0x0}, {0x0, 0x0}, {0x0, 0x0}
+	},
+
+	/*
+	 * The dqs_map arrays map the ddr4 pins to the SoC pins
+	 * for both channels.
+	 *
+	 * the index = pin number on ddr4 part
+	 * the value = pin number on SoC
+	 */
+	.dqs_map[DDR_CH0] = {3, 0, 1, 2, 7, 4, 5, 6},
+	.dqs_map[DDR_CH1] = {3, 0, 1, 2, 7, 4, 5, 6},
+
+	/* Baseboard uses 100, 100 and 100 rcomp resistors */
+	.rcomp_resistor = {100, 100, 100},
+
+	.rcomp_targets = {60, 40, 30, 20, 30},
+
+	/* LPDDR4x does not allow interleaved memory */
+	.dq_pins_interleaved = 0,
+
+	/* Baseboard is using config 2 for vref_ca */
+	.vref_ca_config = 2,
+
+	/* Enable Early Command Training */
+	.ect = 1,
+
+	/* Set Board Type */
+	.UserBd = BOARD_TYPE_MOBILE,
+};
+
+const struct mb_cfg *variant_memcfg_config(void)
+{
+	return &mc_ehl_lpddr4x_memcfg_cfg;
+}

From fc88b6217433429ec93c7e0ca4b677669d2fd3a8 Mon Sep 17 00:00:00 2001
From: Uwe Poeche <uwe.poeche@siemens.com>
Date: Mon, 7 Jul 2025 16:21:33 +0200
Subject: [PATCH 2564/3886] mb/siemens/mc_ehl6: Enable PCIe root ports and
 clocks

Configure and enable the PCIe root ports and associated clocks for the
mc_ehl6 mainboard. This is necessary because the PCIe configuration
differs from the mc_ehl2 baseboard.

TEST=Boot into the OS and verify that all expected PCIe devices are
correctly detected.

Change-Id: Ie5ac3d437088d1db08f869317ef3e5712c3baa3e
Signed-off-by: Uwe Poeche <uwe.poeche@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90082
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
---
 .../siemens/mc_ehl/variants/mc_ehl6/devicetree.cb | 15 ++++++++++++---
 1 file changed, 12 insertions(+), 3 deletions(-)

diff --git a/src/mainboard/siemens/mc_ehl/variants/mc_ehl6/devicetree.cb b/src/mainboard/siemens/mc_ehl/variants/mc_ehl6/devicetree.cb
index 67ece6d158..1e5bd881c0 100644
--- a/src/mainboard/siemens/mc_ehl/variants/mc_ehl6/devicetree.cb
+++ b/src/mainboard/siemens/mc_ehl/variants/mc_ehl6/devicetree.cb
@@ -40,12 +40,12 @@ chip soc/intel/elkhartlake
 	register "SkipCpuReplacementCheck" = "1"
 
 	# PCIe root ports related UPDs
-	register "PcieClkSrcUsage[0]" = "PCIE_CLK_NOTUSED"
+	register "PcieClkSrcUsage[0]" = "PCIE_CLK_FREE"
 	register "PcieClkSrcUsage[1]" = "PCIE_CLK_FREE"
-	register "PcieClkSrcUsage[2]" = "PCIE_CLK_NOTUSED"
+	register "PcieClkSrcUsage[2]" = "PCIE_CLK_FREE"
 	register "PcieClkSrcUsage[3]" = "PCIE_CLK_NOTUSED"
 	register "PcieClkSrcUsage[4]" = "PCIE_CLK_FREE"
-	register "PcieClkSrcUsage[5]" = "PCIE_CLK_NOTUSED"
+	register "PcieClkSrcUsage[5]" = "PCIE_CLK_FREE"
 
 	register "PcieClkSrcClkReq[0]" = "PCIE_CLK_NOTUSED"
 	register "PcieClkSrcClkReq[1]" = "PCIE_CLK_NOTUSED"
@@ -55,11 +55,17 @@ chip soc/intel/elkhartlake
 	register "PcieClkSrcClkReq[5]" = "PCIE_CLK_NOTUSED"
 
 	# Disable all L1 substates for PCIe root ports
+	register "PcieRpL1Substates[0]" = "L1_SS_DISABLED"
 	register "PcieRpL1Substates[1]" = "L1_SS_DISABLED"
+	register "PcieRpL1Substates[2]" = "L1_SS_DISABLED"
+	register "PcieRpL1Substates[4]" = "L1_SS_DISABLED"
 	register "PcieRpL1Substates[6]" = "L1_SS_DISABLED"
 
 	# Disable LTR for all PCIe root ports
+	register "PcieRpLtrDisable[0]" = "true"
 	register "PcieRpLtrDisable[1]" = "true"
+	register "PcieRpLtrDisable[2]" = "true"
+	register "PcieRpLtrDisable[4]" = "true"
 	register "PcieRpLtrDisable[6]" = "true"
 
 	# Storage (SDCARD/EMMC) related UPDs
@@ -176,7 +182,10 @@ chip soc/intel/elkhartlake
 		device pci 1a.0 on	end # eMMC
 		device pci 1a.1 on	end # SD
 
+		device pci 1c.0 on	end # RP1 (pcie0 single VC)
 		device pci 1c.1 on	end # RP2 (pcie0 single VC)
+		device pci 1c.2 on	end # RP3 (pcie0 single VC)
+		device pci 1c.4 on	end # RP5 (pcie1 multi VC)
 		device pci 1c.6 on	end # RP7 (pcie3 multi VC)
 
 		device pci 1d.0 off	end # Intel PSE IPC (local host to PSE)

From b584967d0405bcf6632dfd99fbaa6236b47d7e0d Mon Sep 17 00:00:00 2001
From: Varun Upadhyay <varun.upadhyay@intel.com>
Date: Mon, 10 Nov 2025 15:17:17 +0530
Subject: [PATCH 2565/3886] mb/google/ocelot: Add wake configuration to
 cnvi_bluetooth

This commit adds wake functionality to the CNVi Bluetooth device by
registering to "GPE0_PME_B0" using the common CNVi block.

BUG=454341255
TEST=Able to wake up the device from a low power state using a keyboard
     Bluetooth device.

Change-Id: I4bcbb34e1d53b3438f9e9f2b39f09d91e8dc7110
Signed-off-by: Varun Upadhyay <varun.upadhyay@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89982
Reviewed-by: P, Usha <usha.p@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/google/ocelot/variants/matsu/overridetree.cb | 7 ++++++-
 .../google/ocelot/variants/ocelot/overridetree.cb          | 4 ++++
 src/mainboard/google/ocelot/variants/ojal/overridetree.cb  | 4 ++++
 3 files changed, 14 insertions(+), 1 deletion(-)

diff --git a/src/mainboard/google/ocelot/variants/matsu/overridetree.cb b/src/mainboard/google/ocelot/variants/matsu/overridetree.cb
index ded15fb279..196d47a358 100644
--- a/src/mainboard/google/ocelot/variants/matsu/overridetree.cb
+++ b/src/mainboard/google/ocelot/variants/matsu/overridetree.cb
@@ -309,7 +309,12 @@ chip soc/intel/pantherlake
 			end
 		end # CNVi
 
-		device ref cnvi_bluetooth on end
+		device ref cnvi_bluetooth on
+			chip soc/intel/common/block/cnvi
+				register "wake" = "GPE0_PME_B0"
+				device generic 0 on end
+			end
+		end
 
 		# NOTE: i2c0 is function 0; hence it needs to be enabled when any of i2c1-5 is enabled.
 		# TPM device is under i2c1. Therefore, i2c0 needs to be enabled anyways.
diff --git a/src/mainboard/google/ocelot/variants/ocelot/overridetree.cb b/src/mainboard/google/ocelot/variants/ocelot/overridetree.cb
index 3b0c1b49c7..117e7d8610 100644
--- a/src/mainboard/google/ocelot/variants/ocelot/overridetree.cb
+++ b/src/mainboard/google/ocelot/variants/ocelot/overridetree.cb
@@ -516,6 +516,10 @@ chip soc/intel/pantherlake
 		device ref cnvi_bluetooth on
 			probe WIFI WIFI_CNVI_6
 			probe WIFI WIFI_CNVI_7
+			chip soc/intel/common/block/cnvi
+				register "wake" = "GPE0_PME_B0"
+				device generic 0 on end
+			end
 		end
 
 		# NOTE: i2c0 is function 0; hence it needs to be enabled when any of i2c1-5 is enabled.
diff --git a/src/mainboard/google/ocelot/variants/ojal/overridetree.cb b/src/mainboard/google/ocelot/variants/ojal/overridetree.cb
index 641acbf9ea..c2977f6ac7 100644
--- a/src/mainboard/google/ocelot/variants/ojal/overridetree.cb
+++ b/src/mainboard/google/ocelot/variants/ojal/overridetree.cb
@@ -261,6 +261,10 @@ chip soc/intel/pantherlake
 		device ref cnvi_bluetooth on
 			probe WIFI WIFI_CNVI_6
 			probe WIFI WIFI_CNVI_7
+			chip soc/intel/common/block/cnvi
+				register "wake" = "GPE0_PME_B0"
+				device generic 0 on end
+			end
 		end
 
 		device ref i2c0 on

From 7fb0f14ebeaf93b71e4c337aae4d01d373dcd72d Mon Sep 17 00:00:00 2001
From: Julius Werner <jwerner@chromium.org>
Date: Wed, 19 Nov 2025 15:57:15 -0800
Subject: [PATCH 2566/3886] libpayload: arm64: Fix asynchronous exception
 routing in payload

Six years ago we had a problem with not getting SError exceptions in
coreboot, and we fixed it by setting the right SCR_EL3 bits to force
exception routing to EL3 (commit bb345abbfc99 ("arm64: Correctly unmask
asynchronous SError interrupts")). Turns out that we have the same
problem in the payload but we never fixed it there. EL2 exception
routing works differently, so in order to achieve the same effect here
we can either enable the HCR_EL2 AMO, FMO and IMO bits (respectively),
or we can just enable the TGE bit which traps everything. This patch
chooses the latter, and it also ensures that the PSTATE exception
masking (DAIF) bits are in the expected state (although they usually
already are).

This state will persist after handoff to the kernel or chained payload,
and will prevent transition into EL1 if not cleared first. This should
be fine since any code taking control in EL2 should be expected to
correctly reintialize HCR_EL2 before handing off into EL1 (the Linux
kernel has always reinitialized this very early after its entry point).
If any selfboot() payloads are broken after this change, the payload
should be fixed to reinitialize HCR_EL2 to 0 (or desired value).

Change-Id: I339eded5a5344b5753c94be82e4f1e52e00b39f4
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90127
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Chen-Tsung Hsieh <chentsung@google.com>
---
 payloads/libpayload/arch/arm64/head.S                | 7 +++++++
 payloads/libpayload/include/arm64/arch/lib_helpers.h | 2 ++
 2 files changed, 9 insertions(+)

diff --git a/payloads/libpayload/arch/arm64/head.S b/payloads/libpayload/arch/arm64/head.S
index 0ebadeae34..5fc7ef2967 100644
--- a/payloads/libpayload/arch/arm64/head.S
+++ b/payloads/libpayload/arch/arm64/head.S
@@ -37,6 +37,13 @@ ENTRY(_entry)
 	ldr w1, =(SCTLR_RES1 | SCTLR_I | SCTLR_SA)
 	msr sctlr_el2, x1
 
+	/* Initialize HCR to intended state (route all exceptions to EL2) */
+	mov x1, #HCR_TGE
+	msr hcr_el2, x1
+
+	/* Initialize PSTATE.DAIF to intended state (unmask all exceptions) */
+	msr DAIFClr, #0xf
+
 	/* Save off the location of the coreboot tables */
 	ldr x1, 1f
 	str x0, [x1]
diff --git a/payloads/libpayload/include/arm64/arch/lib_helpers.h b/payloads/libpayload/include/arm64/arch/lib_helpers.h
index c086098da0..fd4ff9e3fc 100644
--- a/payloads/libpayload/include/arm64/arch/lib_helpers.h
+++ b/payloads/libpayload/include/arm64/arch/lib_helpers.h
@@ -45,6 +45,8 @@
 #define SCTLR_RES1           ((0x3 << 4) | (0x1 << 11) | (0x1 << 16) |	\
 			      (0x1 << 18) | (0x3 << 22) | (0x3 << 28))
 
+#define HCR_TGE		(1 << 27)	/* Trap General Exception	*/
+
 #define DAIF_DBG_BIT      (1 << 3)
 #define DAIF_ABT_BIT      (1 << 2)
 #define DAIF_IRQ_BIT      (1 << 1)

From 87f8d15c872d87a12027adea8e41b6cef543f994 Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Sun, 23 Nov 2025 18:01:17 -0600
Subject: [PATCH 2567/3886] ec/google/chromeec/cfr: Fix CFR callback signatures

Commit 04778ddd3814 ("drivers/option/cfr: Remove old sm_object from
constructor") updated the function signature for CFR callbacks, but the
commits adding the fan and backlight controls were merged afterwards
without being adjusted accordingly. Do so here.

TEST=build/boot google/link with these CFR options enabled.

Change-Id: I9ea5224a820b014c4c8edb93e8a6b336ea6f58d0
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90158
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
---
 src/ec/google/chromeec/cfr.h | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/ec/google/chromeec/cfr.h b/src/ec/google/chromeec/cfr.h
index 980ac120c4..93b5bd0d78 100644
--- a/src/ec/google/chromeec/cfr.h
+++ b/src/ec/google/chromeec/cfr.h
@@ -10,7 +10,7 @@
 #include <drivers/option/cfr_frontend.h>
 #include "ec.h"
 
-static void update_fan_control(const struct sm_object *obj, struct sm_object *new)
+static void update_fan_control(struct sm_object *new)
 {
 	if (!CONFIG(EC_GOOGLE_CHROMEEC_AUTO_FAN_CTRL) && !google_chromeec_has_fan()) {
 		new->sm_bool.flags = CFR_OPTFLAG_SUPPRESS;
@@ -38,7 +38,7 @@ static const struct sm_enum_value ec_backlight_values[] = {
 	SM_ENUM_VALUE_END,
 };
 
-static void update_kb_backlight(const struct sm_object *obj, struct sm_object *new)
+static void update_kb_backlight(struct sm_object *new)
 {
 	if (!google_chromeec_has_kbbacklight()) {
 		new->sm_bool.flags = CFR_OPTFLAG_SUPPRESS;

From f61553c9fa743893cb5a301d76ec05234f5a3824 Mon Sep 17 00:00:00 2001
From: Ana Carolina Cabral <ana.cpmelo95@gmail.com>
Date: Thu, 17 Apr 2025 10:27:17 -0300
Subject: [PATCH 2568/3886] vc/amd/fsp/cezanne: Add Renoir FSP

Add FSP folder for Renoir and include it in the build from soc/cezanne
path. Cezanne and Renoir are very similar but there are still enough
changes to justify a separate vendorcode directory.

Change-Id: Id7f51a70c02ea632d87a635e92a6c422ac369bef
Signed-off-by: Ana Carolina Cabral <ana.cpmelo95@gmail.com>
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87216
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
---
 src/soc/amd/cezanne/Makefile.mk               |  11 +-
 src/soc/amd/cezanne/chip.h                    |   5 +
 src/soc/amd/cezanne/fsp_m_params.c            |  13 +-
 src/soc/amd/cezanne/fsp_m_params.h            |   7 +
 src/soc/amd/cezanne/fsp_m_params_cezanne.c    |  18 +
 src/soc/amd/cezanne/fsp_m_params_renoir.c     |   9 +
 src/vendorcode/amd/fsp/renoir/FspGuids.h      |  24 ++
 src/vendorcode/amd/fsp/renoir/FspUpd.h        |  20 ++
 src/vendorcode/amd/fsp/renoir/FspUsb.h        |  59 ++++
 src/vendorcode/amd/fsp/renoir/FspmUpd.h       | 124 +++++++
 src/vendorcode/amd/fsp/renoir/FspsUpd.h       |  26 ++
 src/vendorcode/amd/fsp/renoir/ccx_cppc_data.h |  17 +
 src/vendorcode/amd/fsp/renoir/fsp_h_c99.h     |  58 +++
 .../amd/fsp/renoir/platform_descriptors.h     | 333 ++++++++++++++++++
 src/vendorcode/amd/fsp/renoir/soc_dmi_info.h  |  17 +
 15 files changed, 730 insertions(+), 11 deletions(-)
 create mode 100644 src/soc/amd/cezanne/fsp_m_params.h
 create mode 100644 src/soc/amd/cezanne/fsp_m_params_cezanne.c
 create mode 100644 src/soc/amd/cezanne/fsp_m_params_renoir.c
 create mode 100644 src/vendorcode/amd/fsp/renoir/FspGuids.h
 create mode 100644 src/vendorcode/amd/fsp/renoir/FspUpd.h
 create mode 100644 src/vendorcode/amd/fsp/renoir/FspUsb.h
 create mode 100644 src/vendorcode/amd/fsp/renoir/FspmUpd.h
 create mode 100644 src/vendorcode/amd/fsp/renoir/FspsUpd.h
 create mode 100644 src/vendorcode/amd/fsp/renoir/ccx_cppc_data.h
 create mode 100644 src/vendorcode/amd/fsp/renoir/fsp_h_c99.h
 create mode 100644 src/vendorcode/amd/fsp/renoir/platform_descriptors.h
 create mode 100644 src/vendorcode/amd/fsp/renoir/soc_dmi_info.h

diff --git a/src/soc/amd/cezanne/Makefile.mk b/src/soc/amd/cezanne/Makefile.mk
index d01fbf4006..ff32b740fe 100644
--- a/src/soc/amd/cezanne/Makefile.mk
+++ b/src/soc/amd/cezanne/Makefile.mk
@@ -17,6 +17,8 @@ bootblock-y	+= early_fch.c
 bootblock-y	+= espi_util.c
 
 romstage-y	+= fsp_m_params.c
+romstage-$(CONFIG_SOC_AMD_CEZANNE) += fsp_m_params_cezanne.c
+romstage-$(CONFIG_SOC_AMD_RENOIR)  += fsp_m_params_renoir.c
 
 ramstage-y	+= acpi.c
 ramstage-y	+= chip.c
@@ -36,9 +38,16 @@ smm-$(CONFIG_DEBUG_SMI) += uart.c
 
 CPPFLAGS_common += -I$(src)/soc/amd/cezanne/include
 CPPFLAGS_common += -I$(src)/soc/amd/cezanne/acpi
-CPPFLAGS_common += -I$(src)/vendorcode/amd/fsp/cezanne
 CPPFLAGS_common += -I$(src)/vendorcode/amd/fsp/common
 
+ifeq ($(CONFIG_SOC_AMD_CEZANNE),y)
+CPPFLAGS_common += -I$(src)/vendorcode/amd/fsp/cezanne
+endif
+
+ifeq ($(CONFIG_SOC_AMD_RENOIR),y)
+CPPFLAGS_common += -I$(src)/vendorcode/amd/fsp/renoir
+endif
+
 # 0x40 accounts for the cbfs_file struct + filename + metadata structs, aligned to 64 bytes
 # Building the cbfs image will fail if the offset isn't large enough
 AMD_FW_AB_POSITION := 0x40
diff --git a/src/soc/amd/cezanne/chip.h b/src/soc/amd/cezanne/chip.h
index bdf6ba8ff1..9a1e1d7bab 100644
--- a/src/soc/amd/cezanne/chip.h
+++ b/src/soc/amd/cezanne/chip.h
@@ -11,7 +11,12 @@
 #include <soc/southbridge.h>
 #include <drivers/i2c/designware/dw_i2c.h>
 #include <types.h>
+
+#if CONFIG(SOC_AMD_CEZANNE)
 #include <vendorcode/amd/fsp/cezanne/FspUsb.h>
+#elif CONFIG(SOC_AMD_RENOIR)
+#include <vendorcode/amd/fsp/renoir/FspUsb.h>
+#endif
 
 struct soc_amd_cezanne_config {
 	struct soc_amd_common_config common_config;
diff --git a/src/soc/amd/cezanne/fsp_m_params.c b/src/soc/amd/cezanne/fsp_m_params.c
index 5b20439931..adfd579c83 100644
--- a/src/soc/amd/cezanne/fsp_m_params.c
+++ b/src/soc/amd/cezanne/fsp_m_params.c
@@ -13,8 +13,9 @@
 #include <static.h>
 #include <string.h>
 #include <types.h>
-#include <vendorcode/amd/fsp/cezanne/FspUsb.h>
+
 #include "chip.h"
+#include "fsp_m_params.h"
 
 __weak void mb_pre_fspm(FSP_M_CONFIG *mcfg)
 {
@@ -169,15 +170,7 @@ void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version)
 		mcfg->usb_phy_ptr = 0;
 	}
 
-	if (config->edp_phy_override) {
-		mcfg->edp_phy_override = config->edp_phy_override;
-		mcfg->edp_physel = config->edp_physel;
-		mcfg->dp_vs_pemph_level = config->edp_tuningset.dp_vs_pemph_level;
-		mcfg->tx_eq_main = config->edp_tuningset.tx_eq_main;
-		mcfg->tx_eq_pre = config->edp_tuningset.tx_eq_pre;
-		mcfg->tx_eq_post = config->edp_tuningset.tx_eq_post;
-		mcfg->tx_vboost_lvl = config->edp_tuningset.tx_vboost_lvl;
-	}
+	platform_fsp_memory_init_params_cb_sub(mcfg, config);
 
 	fsp_fill_pcie_ddi_descriptors(mcfg);
 	fsp_assign_ioapic_upds(mcfg);
diff --git a/src/soc/amd/cezanne/fsp_m_params.h b/src/soc/amd/cezanne/fsp_m_params.h
new file mode 100644
index 0000000000..ba601c470c
--- /dev/null
+++ b/src/soc/amd/cezanne/fsp_m_params.h
@@ -0,0 +1,7 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <fsp/api.h>
+#include "chip.h"
+
+void platform_fsp_memory_init_params_cb_sub(FSP_M_CONFIG *mcfg,
+					    const struct soc_amd_cezanne_config *config);
diff --git a/src/soc/amd/cezanne/fsp_m_params_cezanne.c b/src/soc/amd/cezanne/fsp_m_params_cezanne.c
new file mode 100644
index 0000000000..b18fcfc135
--- /dev/null
+++ b/src/soc/amd/cezanne/fsp_m_params_cezanne.c
@@ -0,0 +1,18 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include "chip.h"
+#include "fsp_m_params.h"
+
+void platform_fsp_memory_init_params_cb_sub(FSP_M_CONFIG *mcfg,
+					    const struct soc_amd_cezanne_config *config)
+{
+	if (config->edp_phy_override) {
+		mcfg->edp_phy_override = config->edp_phy_override;
+		mcfg->edp_physel = config->edp_physel;
+		mcfg->dp_vs_pemph_level = config->edp_tuningset.dp_vs_pemph_level;
+		mcfg->tx_eq_main = config->edp_tuningset.tx_eq_main;
+		mcfg->tx_eq_pre = config->edp_tuningset.tx_eq_pre;
+		mcfg->tx_eq_post = config->edp_tuningset.tx_eq_post;
+		mcfg->tx_vboost_lvl = config->edp_tuningset.tx_vboost_lvl;
+	}
+}
diff --git a/src/soc/amd/cezanne/fsp_m_params_renoir.c b/src/soc/amd/cezanne/fsp_m_params_renoir.c
new file mode 100644
index 0000000000..8b4dfd8042
--- /dev/null
+++ b/src/soc/amd/cezanne/fsp_m_params_renoir.c
@@ -0,0 +1,9 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include "chip.h"
+#include "fsp_m_params.h"
+
+void platform_fsp_memory_init_params_cb_sub(FSP_M_CONFIG *mcfg,
+					    const struct soc_amd_cezanne_config *config)
+{
+}
diff --git a/src/vendorcode/amd/fsp/renoir/FspGuids.h b/src/vendorcode/amd/fsp/renoir/FspGuids.h
new file mode 100644
index 0000000000..1bef794418
--- /dev/null
+++ b/src/vendorcode/amd/fsp/renoir/FspGuids.h
@@ -0,0 +1,24 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef __FSP_GUIDS__
+#define __FSP_GUIDS__
+
+#include <uuid.h>
+
+#define AMD_FSP_TSEG_HOB_GUID \
+		GUID_INIT(0x5fc7897a, 0x5aff, 0x4c61, \
+		0xaa, 0x7a, 0xdd, 0xcf, 0xa9, 0x18, 0x43, 0x0c)
+
+#define AMD_FSP_ACPI_ALIB_HOB_GUID \
+		GUID_INIT(0x42494c41, 0x4002, 0x403b, \
+		0x87, 0xE1, 0x3F, 0xEB, 0x13, 0xC5, 0x66, 0x9A)
+
+#define AMD_FSP_PCIE_DEVFUNC_REMAP_HOB_GUID \
+		GUID_INIT(0X6D5CD69D, 0XFB24, 0X4461, \
+		0XAA, 0X32, 0X8E, 0XE1, 0XB3, 0X3, 0X31, 0X9C )
+
+#define AMD_FSP_CCX_CPPC_DATA_HOB_GUID \
+		GUID_INIT(0x3060C5EC, 0x7399, 0x432D, \
+		0xBC, 0x97, 0xBF, 0x95, 0xE4, 0x3D, 0x53, 0x0C )
+
+#endif /* __FSP_GUIDS__ */
diff --git a/src/vendorcode/amd/fsp/renoir/FspUpd.h b/src/vendorcode/amd/fsp/renoir/FspUpd.h
new file mode 100644
index 0000000000..efd8bdd64e
--- /dev/null
+++ b/src/vendorcode/amd/fsp/renoir/FspUpd.h
@@ -0,0 +1,20 @@
+/** @file
+ *
+ * This file is automatically generated.
+ *
+ */
+
+#ifndef __FSPUPD_H__
+#define __FSPUPD_H__
+
+#ifdef EFI32
+# include <FspEas.h>
+# include <stdint.h>
+#else
+# include <fsp_h_c99.h>
+#endif
+
+#define FSPM_UPD_SIGNATURE               0x4D5F31305F444D41        /* 'RENOIR_M' */
+#define FSPS_UPD_SIGNATURE               0x535F31305F444D41        /* 'RENOIR_S' */
+
+#endif
diff --git a/src/vendorcode/amd/fsp/renoir/FspUsb.h b/src/vendorcode/amd/fsp/renoir/FspUsb.h
new file mode 100644
index 0000000000..fea1fee3bd
--- /dev/null
+++ b/src/vendorcode/amd/fsp/renoir/FspUsb.h
@@ -0,0 +1,59 @@
+#ifndef __FSPUSB_H__
+#define __FSPUSB_H__
+
+#include <FspUpd.h>
+
+#define FSP_USB_STRUCT_MAJOR_VERSION	0xd
+#define FSP_USB_STRUCT_MINOR_VERSION	0x6
+
+#define USB2_PORT_COUNT 8
+#define USB3_PORT_COUNT 4
+#define USBC_COMBO_PHY_COUNT 2
+
+struct fch_usb2_phy {
+	uint8_t			compdstune;                             ///< COMPDSTUNE
+	uint8_t			sqrxtune;                               ///< SQRXTUNE
+	uint8_t			txfslstune;                             ///< TXFSLSTUNE
+	uint8_t			txpreempamptune;                        ///< TXPREEMPAMPTUNE
+	uint8_t			txpreemppulsetune;                      ///< TXPREEMPPULSETUNE
+	uint8_t			txrisetune;                             ///< TXRISETUNE
+	uint8_t			txvreftune;                             ///< TXVREFTUNE
+	uint8_t			txhsxvtune;                             ///< TXHSXVTUNE
+	uint8_t			txrestune;                              ///< TXRESTUNE
+} __packed;
+
+struct fch_usb3_phy {
+	uint8_t			tx_term_ctrl;                           ///< tx_term_ctrl
+	uint8_t			rx_term_ctrl;                           ///< rx_term_ctrl
+	uint8_t			tx_vboost_lvl_en;                       ///< TX_VBOOST_LVL_EN
+	uint8_t			tx_vboost_lvl;                          ///< TX_VBOOST_LVL
+} __packed;
+
+#define USB0_PORT0	0
+#define USB0_PORT1	1
+#define USB0_PORT2	1
+#define USB0_PORT3	3
+#define USB1_PORT0	(0<<2)
+#define USB1_PORT1	(1<<2)
+#define USB1_PORT2	(1<<2)
+#define USB1_PORT3	(3<<2)
+
+#define USB_COMBO_PHY_MODE_USB_C	0
+#define USB_COMBO_PHY_MODE_USB_ONLY	1
+#define USB_COMBO_PHY_MODE_USB_DPM	2
+#define USB_COMBO_PHY_MODE_USB_DPP	3
+
+struct usb_phy_config {
+	uint8_t			Version_Major;                     ///< USB IP version
+	uint8_t			Version_Minor;                     ///< USB IP version
+	uint8_t			TableLength;                       ///< TableLength
+	uint8_t			Reserved0;
+	struct fch_usb2_phy	Usb2PhyPort[USB2_PORT_COUNT];      ///< USB 2.0 Driving Strength
+	struct fch_usb3_phy	Usb3PhyPort[USB3_PORT_COUNT];      ///< USB3 PHY Adjustment
+	uint8_t			BatteryChargerEnable;              ///< bit[1:0]-Usb0 Port[1:0], bit[3:2]-Usb1 Port[1:0]
+	uint8_t			PhyP3CpmP4Support;                 ///< bit[1:0]-Usb0 Port[1:0], bit[3:2]-Usb1 Port[1:0]
+	uint8_t			ComboPhyStaticConfig[USBC_COMBO_PHY_COUNT]; ///< 0-Type C, 1- USB only mode, 2- DP only mode, 3- USB + DP
+	uint8_t			Reserved2[4];
+} __packed;
+
+#endif
diff --git a/src/vendorcode/amd/fsp/renoir/FspmUpd.h b/src/vendorcode/amd/fsp/renoir/FspmUpd.h
new file mode 100644
index 0000000000..7e1d2f20cb
--- /dev/null
+++ b/src/vendorcode/amd/fsp/renoir/FspmUpd.h
@@ -0,0 +1,124 @@
+/** @file
+ *
+ * This file is _NOT_ automatically generated in coreboot!
+ *
+ */
+
+#ifndef __FSPMUPD_H__
+#define __FSPMUPD_H__
+
+#include <FspUpd.h>
+#include <FspUsb.h>
+
+#define FSPM_UPD_DXIO_DESCRIPTOR_COUNT	14
+#define FSPM_UPD_DDI_DESCRIPTOR_COUNT	5
+
+/** Fsp M Configuration
+**/
+typedef struct __packed {
+	/** Offset 0x0040**/	uint32_t                    bert_size;
+	/** Offset 0x0044**/	uint32_t                    tseg_size;
+	/** Offset 0x0048**/	uint32_t                    pci_express_base_addr;
+	/** Offset 0x004C**/	uint8_t                     misc_reserved[32];
+	/** Offset 0x006C**/	uint32_t                    serial_port_base;
+	/** Offset 0x0070**/	uint32_t                    serial_port_use_mmio;
+	/** Offset 0x0074**/	uint32_t                    serial_port_baudrate;
+	/** Offset 0x0078**/	uint32_t                    serial_port_refclk;
+	/** Offset 0x007C**/	uint32_t                    serial_reserved;
+	/** Offset 0x0080**/	uint8_t                     dxio_descriptor[FSPM_UPD_DXIO_DESCRIPTOR_COUNT][52];
+	/** Offset 0x0358**/	uint8_t                     fsp_owns_pcie_resets;
+	/** Offset 0x0359**/	uint8_t                     pcie_reserved[51];
+	/** Offset 0x038C**/	uint32_t                    ddi_descriptor[FSPM_UPD_DDI_DESCRIPTOR_COUNT];
+	/** Offset 0x03A0**/	uint8_t                     ddi_reserved[6];
+	/** Offset 0x03A6**/	uint8_t                     ccx_down_core_mode;
+	/** Offset 0x03A7**/	uint8_t                     ccx_disable_smt;
+	/** Offset 0x03A8**/	uint8_t                     ccx_reserved[32];
+	/** Offset 0x03C8**/	uint8_t                     stt_control;
+	/** Offset 0x03C9**/	uint8_t                     stt_pcb_sensor_count;
+	/** Offset 0x03CA**/	uint16_t                    stt_min_limit;
+	/** Offset 0x03CC**/	uint16_t                    stt_m1;
+	/** Offset 0x03CE**/	uint16_t                    stt_m2;
+	/** Offset 0x03D0**/	uint16_t                    stt_m3;
+	/** Offset 0x03D2**/	uint16_t                    stt_m4;
+	/** Offset 0x03D4**/	uint16_t                    stt_m5;
+	/** Offset 0x03D6**/	uint16_t                    stt_m6;
+	/** Offset 0x03D8**/	uint16_t                    stt_c_apu;
+	/** Offset 0x03DA**/	uint16_t                    stt_c_gpu;
+	/** Offset 0x03DC**/	uint16_t                    stt_c_hs2;
+	/** Offset 0x03DE**/	uint16_t                    stt_alpha_apu;
+	/** Offset 0x03E0**/	uint16_t                    stt_alpha_gpu;
+	/** Offset 0x03E2**/	uint16_t                    stt_alpha_hs2;
+	/** Offset 0x03E4**/	uint16_t                    stt_skin_temp_apu;
+	/** Offset 0x03E6**/	uint16_t                    stt_skin_temp_gpu;
+	/** Offset 0x03E8**/	uint16_t                    stt_skin_temp_hs2;
+	/** Offset 0x03EA**/	uint16_t                    stt_error_coeff;
+	/** Offset 0x03EC**/	uint16_t                    stt_error_rate_coefficient;
+	/** Offset 0x03EE**/	uint8_t                     smartshift_enable;
+	/** Offset 0x03EF**/	uint32_t                    apu_only_sppt_limit;
+	/** Offset 0x03F3**/	uint32_t                    sustained_power_limit;
+	/** Offset 0x03F7**/	uint32_t                    fast_ppt_limit;
+	/** Offset 0x03FB**/	uint32_t                    slow_ppt_limit;
+	/** Offset 0x03FF**/	uint8_t                     system_configuration;
+	/** Offset 0x0400**/	uint8_t                     cppc_ctrl;
+	/** Offset 0x0401**/	uint8_t                     cppc_perf_limit_max_range;
+	/** Offset 0x0402**/	uint8_t                     cppc_perf_limit_min_range;
+	/** Offset 0x0403**/	uint8_t                     cppc_epp_max_range;
+	/** Offset 0x0404**/	uint8_t                     cppc_epp_min_range;
+	/** Offset 0x0405**/	uint8_t                     cppc_preferred_cores;
+	/** Offset 0x0406**/	uint8_t                     stapm_boost;
+	/** Offset 0x0407**/	uint32_t                    stapm_time_constant;
+	/** Offset 0x040B**/	uint32_t                    slow_ppt_time_constant;
+	/** Offset 0x040F**/	uint32_t                    thermctl_limit;
+	/** Offset 0x0413**/	uint8_t                     smu_soc_tuning_reserved[9];
+	/** Offset 0x041C**/	uint8_t                     iommu_support;
+	/** Offset 0x041D**/	uint8_t                     pspp_policy;
+	/** Offset 0x041E**/	uint8_t                     enable_nb_azalia;
+	/** Offset 0x041F**/	uint8_t                     audio_io_ctl;
+	/** Offset 0x0420**/	uint8_t                     pdm_mic_selection;
+	/** Offset 0x0421**/	uint8_t                     hda_enable;
+	/** Offset 0x0422**/	uint8_t                     nbio_reserved[31];
+	/** Offset 0x0441**/	uint32_t                    emmc0_mode;
+	/** Offset 0x0445**/	uint16_t                    emmc0_init_khz_preset;
+	/** Offset 0x0447**/	uint8_t                     emmc0_sdr104_hs400_driver_strength;
+	/** Offset 0x0448**/	uint8_t                     emmc0_ddr50_driver_strength;
+	/** Offset 0x0449**/	uint8_t                     emmc0_sdr50_driver_strength;
+	/** Offset 0x044A**/	uint8_t                     UnusedUpdSpace0[85];
+	/** Offset 0x049F**/	uint32_t                    gnb_ioapic_base;
+	/** Offset 0x04A3**/	uint8_t                     gnb_ioapic_id;
+	/** Offset 0x04A4**/	uint8_t                     fch_ioapic_id;
+	/** Offset 0x04A5**/	uint8_t                     sata_enable;
+	/** Offset 0x04A6**/	uint8_t                     fch_reserved[32];
+	/** Offset 0x04C6**/	uint8_t                     s0i3_enable;
+	/** Offset 0x04C7**/	uint32_t                    telemetry_vddcrvddfull_scale_current;
+	/** Offset 0x04CB**/	uint32_t                    telemetry_vddcrvddoffset;
+	/** Offset 0x04CF**/	uint32_t                    telemetry_vddcrsocfull_scale_current;
+	/** Offset 0x04D3**/	uint32_t                    telemetry_vddcrsocOffset;
+	/** Offset 0x04D7**/	uint8_t                     UnusedUpdSpace1;
+	/* usb_phy_ptr is actually struct usb_phy_config *, but that won't work for 64bit coreboot */
+	/** Offset 0x04D8**/	uint32_t                    usb_phy_ptr;
+	/** Offset 0x04DC**/	uint64_t                    xgbe_port0_mac;
+	/** Offset 0x04E4**/	uint64_t                    xgbe_port1_mac;
+	/** offset 0x04EC**/	uint8_t                     xgbe_port0_config_en;
+	/** offset 0x04ED**/	uint8_t                     xgbe_port1_config_en;
+	/** offset 0x04EE**/	uint32_t                    xgbe_port0_table;
+	/** offset 0x04F2**/	uint32_t                    xgbe_port1_table;
+	/** offset 0x04F6**/	uint8_t                     nvme_rst_gpio;
+	/** Offset 0x04F7**/	uint8_t                     UnusedUpdSpace2[265];
+	/** Offset 0x0600**/	uint16_t                    UpdTerminator;
+} FSP_M_CONFIG;
+
+/** Fsp M UPD Configuration
+**/
+typedef struct __packed {
+	/** Offset 0x0000**/	FSP_UPD_HEADER              FspUpdHeader;
+	/** Offset 0x0020**/	FSPM_ARCH_UPD               FspmArchUpd;
+	/** Offset 0x0040**/	FSP_M_CONFIG                FspmConfig;
+} FSPM_UPD;
+
+#define IMAGE_REVISION_MAJOR_VERSION 0x01
+#define IMAGE_REVISION_MINOR_VERSION 0x00
+#define IMAGE_REVISION_REVISION 0x05
+#define IMAGE_REVISION_BUILD_NUMBER 0x00
+
+
+#endif
diff --git a/src/vendorcode/amd/fsp/renoir/FspsUpd.h b/src/vendorcode/amd/fsp/renoir/FspsUpd.h
new file mode 100644
index 0000000000..3ac52c097f
--- /dev/null
+++ b/src/vendorcode/amd/fsp/renoir/FspsUpd.h
@@ -0,0 +1,26 @@
+/** @file
+ *
+ * This file is automatically generated.
+ *
+ */
+
+#ifndef __FSPSUPD_H__
+#define __FSPSUPD_H__
+
+#include <FspUpd.h>
+
+typedef struct __packed {
+	/** Offset 0x0020**/	uint32_t                    vbios_buffer;
+	/** Offset 0x0024**/	uint64_t                    gop_reserved;
+	/** Offset 0x002C**/	uint32_t                    reserved1;
+	/** Offset 0x0030**/	uint16_t                    UpdTerminator;
+} FSP_S_CONFIG;
+
+/** Fsp S UPD Configuration
+**/
+typedef struct __packed {
+	/** Offset 0x0000**/	FSP_UPD_HEADER              FspUpdHeader;
+	/** Offset 0x0020**/	FSP_S_CONFIG                FspsConfig;
+} FSPS_UPD;
+
+#endif
diff --git a/src/vendorcode/amd/fsp/renoir/ccx_cppc_data.h b/src/vendorcode/amd/fsp/renoir/ccx_cppc_data.h
new file mode 100644
index 0000000000..a924eaa4d4
--- /dev/null
+++ b/src/vendorcode/amd/fsp/renoir/ccx_cppc_data.h
@@ -0,0 +1,17 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef CEZANNE_FSP_CCX_CPPC_DATA_H
+#define CEZANNE_FSP_CCX_CPPC_DATA_H
+
+#include <types.h>
+
+#define FSP_CCX_CPPC_DATA_VERSION	1
+
+struct fsp_ccx_cppc_data {
+	uint8_t version;
+	uint8_t unused[3];
+	uint32_t ccx_cppc_min_speed;
+	uint32_t ccx_cppc_nom_speed;
+} __packed;
+
+#endif /* CEZANNE_FSP_CCX_CPPC_DATA_H */
diff --git a/src/vendorcode/amd/fsp/renoir/fsp_h_c99.h b/src/vendorcode/amd/fsp/renoir/fsp_h_c99.h
new file mode 100644
index 0000000000..1a295f591a
--- /dev/null
+++ b/src/vendorcode/amd/fsp/renoir/fsp_h_c99.h
@@ -0,0 +1,58 @@
+/** @file
+ *
+ * C99 common FSP definitions from
+ * Intel Firmware Support Package External Architecture Specification v2.0
+ *
+ * These definitions come in a format that is usable outside an EFI environment.
+ **/
+#ifndef FSP_H_C99_H
+#define FSP_H_C99_H
+
+#include <stdint.h>
+
+enum {
+	FSP_STATUS_RESET_REQUIRED_COLD		= 0x40000001,
+	FSP_STATUS_RESET_REQUIRED_WARM		= 0x40000002,
+	FSP_STATUS_RESET_REQUIRED_3		= 0x40000003,
+	FSP_STATUS_RESET_REQUIRED_4		= 0x40000004,
+	FSP_STATUS_RESET_REQUIRED_5		= 0x40000005,
+	FSP_STATUS_RESET_REQUIRED_6		= 0x40000006,
+	FSP_STATUS_RESET_REQUIRED_7		= 0x40000007,
+	FSP_STATUS_RESET_REQUIRED_8		= 0x40000008,
+};
+
+typedef enum {
+	EnumInitPhaseAfterPciEnumeration	= 0x20,
+	EnumInitPhaseReadyToBoot		= 0x40,
+	EnumInitPhaseEndOfFirmware		= 0xF0
+} FSP_INIT_PHASE;
+
+typedef struct __packed {
+	uint64_t	Signature;
+	uint8_t		Revision;
+	uint8_t		Reserved[23];
+} FSP_UPD_HEADER;
+
+_Static_assert(sizeof(FSP_UPD_HEADER) == 32, "FSP_UPD_HEADER not packed");
+
+
+#if CONFIG(PLATFORM_USES_FSP2_X86_32)
+typedef struct __packed {
+	uint8_t		Revision;
+	uint8_t		Reserved[3];
+	/* Note: This ought to be void*, but that won't allow calling this binary on x86_64. */
+	uint32_t	NvsBufferPtr;
+	/* Note: This ought to be void*, but that won't allow calling this binary on x86_64. */
+	uint32_t	StackBase;
+	uint32_t	StackSize;
+	uint32_t	BootLoaderTolumSize;
+	uint32_t	BootMode;
+	uint8_t		Reserved1[8];
+} FSPM_ARCH_UPD;
+
+_Static_assert(sizeof(FSPM_ARCH_UPD) == 32, "FSPM_ARCH_UPD not packed");
+#else
+#error You need to implement this struct for x86_64 FSP
+#endif
+
+#endif /* FSP_H_C99_H */
diff --git a/src/vendorcode/amd/fsp/renoir/platform_descriptors.h b/src/vendorcode/amd/fsp/renoir/platform_descriptors.h
new file mode 100644
index 0000000000..3b1ff53d28
--- /dev/null
+++ b/src/vendorcode/amd/fsp/renoir/platform_descriptors.h
@@ -0,0 +1,333 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+/*
+ * These definitions are used to describe PCIe bifurcation and display physical
+ * connector types connected to the SOC.
+ */
+
+#ifndef PI_CEZANNE_PLATFORM_DESCRIPTORS_H
+#define PI_CEZANNE_PLATFORM_DESCRIPTORS_H
+
+#define NUM_DXIO_PHY_PARAMS	6
+#define NUM_DXIO_PORT_PARAMS	6
+
+/* Engine descriptor type */
+enum dxio_engine_type {
+	UNUSED_ENGINE	= 0x00,	// Unused descriptor
+	PCIE_ENGINE	= 0x01,	// PCIe port
+	USB_ENGINE	= 0x02,	// USB port
+	SATA_ENGINE	= 0x03,	// SATA
+	DP_ENGINE	= 0x08,	// Digital Display
+	ETHERNET_ENGINE	= 0x10,	// Ethernet (GBe, XGBe)
+	MAX_ENGINE		// Max engine type for boundary check.
+};
+
+/* PCIe link capability/speed */
+enum dxio_link_speed_cap {
+	GEN_MAX = 0,		// Maximum supported
+	GEN1,
+	GEN2,
+	GEN3,
+	GEN_INVALID		// Max Gen for boundary check
+};
+
+/* Upstream Auto Speed Change Allowed */
+enum dxio_upstream_auto_speed_change {
+	SPDC_DEFAULT = 0,      // Enabled for Gen2 and Gen3
+	SPDC_DISABLED,
+	SPDC_ENABLED,
+	SPDC_INVALID
+};
+
+/* SATA ChannelType initialization */
+enum dxio_sata_channel_type {
+	SATA_CHANNEL_OTHER = 0,	// Default Channel Type
+	SATA_CHANNEL_SHORT,	// Short Trace Channel Type
+	SATA_CHANNEL_LONG	// Long Trace Channel Type
+};
+
+/* CLKREQ for PCIe type descriptors */
+enum cpm_clk_req {
+	CLK_DISABLE = 0x00,
+	CLK_REQ0,
+	CLK_REQ1,
+	CLK_REQ2,
+	CLK_REQ3,
+	CLK_REQ4_GFX,
+	CLK_REQ5,
+	CLK_REQ6,
+	CLK_ENABLE = 0xff,
+};
+
+/* PCIe link ASPM initialization */
+enum dxio_aspm_type {
+	ASPM_DISABLED = 0,	// Disabled
+	ASPM_L0s,		// PCIe L0s link state
+	ASPM_L1,		// PCIe L1 link state
+	ASPM_L0sL1,		// PCIe L0s & L1 link state
+	ASPM_MAX		// Not valid value, used to verify input
+};
+
+/* PCIe link hotplug */
+enum dxio_link_hotplug_type {
+	HOTPLUG_DISABLED = 0,
+	HOTPLUG_BASIC,
+	HOTPLUG_SERVER,
+	HOTPLUG_ENHANCED,
+	HOTPLUG_INBOARD,
+	HOTPLUG_SERVER_SSD,
+};
+
+enum dxio_port_param_type {
+	PP_DEVICE = 1,
+	PP_FUNCTION,
+	PP_PORT_PRESENT,
+	PP_LINK_SPEED_CAP,
+	PP_LINK_ASPM,
+	PP_HOTPLUG_TYPE,
+	PP_CLKREQ,
+	PP_ASPM_L1_1,
+	PP_ASPM_L1_2,
+	PP_COMPLIANCE,
+	PP_SAFE_MODE,
+	PP_CHIPSET_LINK,
+	PP_CLOCK_PM,
+	PP_CHANNELTYPE,
+	PP_TURN_OFF_UNUSED_LANES,
+	PP_APIC_GROUPMAP,
+	PP_APIC_SWIZZLE,
+	PP_APIC_BRIDGEINT,
+	PP_MASTER_PLL,
+	PP_SLOT_NUM,
+	PP_PHY_PARAM,
+	PP_ESM,
+	PP_CCIX,
+	PP_GEN3_DS_TX_PRESET,
+	PP_GEN3_DS_RX_PRESET_HINT,
+	PP_GEN3_US_TX_PRESET,
+	PP_GEN3_US_RX_PRESET_HINT,
+	PP_GEN4_DS_TX_PRESET,
+	PP_GEN4_US_TX_PRESET,
+	PP_GEN3_FIXED_PRESET,
+	PP_GEN4_FIXED_PRESET,
+	PP_PSPP_DC,
+	PP_PSPP_AC,
+	PP_GEN2_DEEMPHASIS,
+	PP_INVERT_POLARITY,
+	PP_TARGET_LINK_SPEED,
+	PP_GEN4_DLF_CAP_DISABLE,
+	PP_GEN4_DLF_EXCHG_DISABLE
+};
+
+/* DDI Aux channel */
+enum ddi_aux_type {
+	DDI_AUX1 = 0,
+	DDI_AUX2,
+	DDI_AUX3,
+	DDI_AUX4,
+	DDI_AUX5,
+	DDI_AUX6,
+	DDI_AUX_MAX		// Not valid value, used to verify input
+};
+
+/* DDI Hdp Index */
+enum ddi_hdp_type {
+	DDI_HDP1 = 0,
+	DDI_HDP2,
+	DDI_HDP3,
+	DDI_HDP4,
+	DDI_HDP5,
+	DDI_HDP6,
+	DDI_HDP_MAX		// Not valid value, used to verify input
+};
+
+/* DDI display connector type */
+enum ddi_connector_type {
+	DDI_DP = 0,		// DP
+	DDI_EDP,		// eDP
+	DDI_SINGLE_LINK_DVI,	// Single Link DVI-D
+	DDI_DUAL_LINK_DVI,	// Dual Link DVI-D
+	DDI_HDMI,		// HDMI
+	DDI_DP_TO_VGA,		// DP-to-VGA
+	DDI_DP_TO_LVDS,		// DP-to-LVDS
+	DDI_NUTMEG_DP_TO_VGA,	// Hudson-2 NutMeg DP-to-VGA
+	DDI_SINGLE_LINK_DVI_I,	// Single Link DVI-I
+	DDI_CRT,		// CRT (VGA)
+	DDI_LVDS,		// LVDS
+	DDI_EDP_TO_LVDS,	// eDP-to-LVDS translator chip without AMD SW init
+	DDI_EDP_TO_LVDS_SW,	// eDP-to-LVDS translator which requires AMD SW init
+	DDI_AUTO_DETECT,	// VBIOS auto detect connector type
+	DDI_UNUSED_TYPE,	// UnusedType
+	DDI_MAX_CONNECTOR_TYPE	// Not valid value, used to verify input
+};
+
+/* DDI Descriptor: used for configuring display outputs */
+typedef struct __packed {
+	uint8_t		connector_type; // see ddi_connector_type
+	uint8_t		aux_index; // see ddi_aux_type
+	uint8_t		hdp_index; // see ddi_hdp_type
+	uint8_t		reserved;
+} fsp_ddi_descriptor;
+
+/*
+ * Cezanne DXIO Descriptor: Used for assigning lanes to PCIe/SATA/XGBE engines,
+ * configure bifurcation and other settings. Beware that the lane numbers in
+ * here are the logical and not the physical lane numbers!
+ *
+ * Cezanne DXIO logical lane to physical PCIe lane mapping:
+ *
+ * logical |   FT6      |   AM4
+ * --------|------------|----------------------
+ * [00:03] | GPP[00:03] | GPP[00:03]
+ * [04:07] | GPP[04:07] | GPP[04:07]/HUB[00:03]
+ * [08:11] | GPP[08:11] | GFX[15:12]
+ * [12:15] |        n/a | GFX[11:08]
+ * [16:23] | GFX[00:07] | GFX[07:0]
+ *
+ * Different ports mustn't overlap or be assigned to the same lane(s). Within
+ * ports with the same width the one with a higher start logical lane number
+ * needs to be assigned to a higher PCIe root port number; ports of the same
+ * size don't have to be assigned to consecutive PCIe root ports though.
+ *
+ * Lanes 2 and 3 can be mapped to the SATA controller on all packages; the FT6
+ * platform additionally supports mapping lanes 8 and 9 to a SATA controller.
+ * On embedded SKUs lanes 0 and 1 can be mapped to the Gigabit Ethernet
+ * controllers.
+ */
+typedef struct __packed {
+	uint8_t		engine_type;			// See dxio_engine_type
+	uint8_t		start_logical_lane;		// Start lane of the pci device
+	uint8_t		end_logical_lane;		// End lane of the pci device
+	uint8_t		gpio_group_id;			// GPIO number used as reset
+	uint32_t	port_present		:1;	// Should be TRUE if train link
+	uint32_t	reserved_3		:7;
+	uint32_t	device_number		:5;	// Desired root port device number
+	uint32_t	function_number		:3;	// Desired root port function number
+	uint32_t	link_speed_capability	:2;	// See dxio_link_speed_cap
+	uint32_t	auto_spd_change		:2;	// See dxio_upstream_auto_speed_change
+	uint32_t	eq_preset		:4;	// Gen3 equalization preset
+	uint32_t	link_aspm		:2;	// See dxio_aspm_type
+	uint32_t	link_aspm_L1_1		:1;	// En/Dis root port capabilities for L1.1
+	uint32_t	link_aspm_L1_2		:1;	// En/Dis root port capabilities for L1.2
+	uint32_t	clk_req			:4;	// See cpm_clk_req
+	uint8_t		link_hotplug;			// See dxio_link_hotplug_type
+	uint8_t		slot_power_limit;		// Currently unused by FSP
+	uint32_t	slot_power_limit_scale	:2;	// Currently unused by FSP
+	uint32_t	reserved_4		:6;
+	uint32_t	link_compliance_mode	:1;	// Currently unused by FSP
+	uint32_t	link_safe_mode		:1;	// Currently unused by FSP
+	uint32_t	sb_link			:1;	// Currently unused by FSP
+	uint32_t	clk_pm_support		:1;	// Currently unused by FSP
+	uint32_t	channel_type		:3;	// See dxio_sata_channel_type
+	uint32_t	turn_off_unused_lanes	:1;	// Power down lanes if device not present
+	uint8_t		reserved[4];
+	uint8_t		phy_params[NUM_DXIO_PHY_PARAMS*2];
+	uint16_t	port_params[NUM_DXIO_PORT_PARAMS*2];	// key-value parameters. see dxio_port_param_type
+} fsp_dxio_descriptor;
+
+typedef enum {
+	XGBE_PORT_DISABLE,
+	XGBE_PORT_ENABLE,
+} xgbe_port_enable;
+
+typedef enum {
+	XGBE_PHY_MODE_RJ45,
+	XGBE_PHY_MODE_SFP_PLUS,
+	XGBE_PHY_MODE_BACKPLANE
+} xgbe_port_phy_modes;
+
+typedef enum {
+	XGBE_RESERVED,
+	XGBE_10G_1G_BACKPLANE,
+	XGBE_2_5G_BACKPLANE,
+	XGBE_SOLDERED_DOWN_1000BASE_T,
+	XGBE_SOLDERED_DOWN_1000BASE_X,
+	XGBE_SOLDERED_DOWN_NBASE_T,
+	XGBE_SOLDERED_DOWN_10GBASE_T,
+	XGBE_SOLDERED_DOWN_10GBASE_R,
+	XGBE_SFP_PLUS_CONNECTOR,
+	BACKPLANE_AUTONEG_OFF
+} xgbe_port_platform_config;
+
+typedef enum {
+	XGBE_PORT_SPEED_10M = 0x1,
+	XGBE_PORT_SPEED_100M = 0x2,
+	XGBE_PORT_SPEED_1G = 0x4,
+	XGBE_PORT_SPEED_10_100_1000M = 0x7,
+} xgbe_port_speed_config;
+
+typedef enum {
+	XGBE_PORT_NOT_USED = 0x0,
+	XGBE_SFP_PLUS_CONNECTION = 0x1,
+	XGBE_CONNECTION_MDIO_PHY = 0x2,
+	XGBE_BACKPLANE_CONNECTION = 0x4,
+} xgbe_port_connection_type;
+
+struct __packed xgbe_port_table {
+	uint8_t xgbe_port_config;               ///< XGbE controller Port Config Enable/disable
+	uint8_t xgbe_port_platform_config;      ///< Platform Config
+	                                        ///  @li   <b>0000</b> - Reserved
+	                                        ///  @li   <b>0001</b> - 10G/1G Backplane
+	                                        ///  @li   <b>0010</b> - 2.5G Backplane
+	                                        ///  @li   <b>0011</b> - 1000Base-T
+	                                        ///  @li   <b>0100</b> - 1000Base-X
+	                                        ///  @li   <b>0101</b> - NBase-T
+	                                        ///  @li   <b>0110</b> - 10GBase-T
+	                                        ///  @li   <b>0111</b> - 10GBase-X
+	                                        ///  @li   <b>1000</b> - SFP+
+	uint8_t xgbe_port_supported_speed;      ///< Indicated Ethernet speeds supported on platform
+	                                        ///  @li   <b>x111</b> - 10/100/1000M
+	                                        ///  @li   <b>x1xx</b> - 1G
+	                                        ///  @li   <b>xx1x</b> - 100M
+	                                        ///  @li   <b>xxx1</b> - 10M
+	uint8_t xgbe_port_connected_type;       ///< PHY connected type
+	                                        ///  @li   <b>000</b> - Port not used
+	                                        ///  @li   <b>001</b> - SFP+
+	                                        ///  @li   <b>010</b> - MDIO
+	                                        ///  @li   <b>100</b> - Backplane connection
+	uint8_t xgbe_port_mdio_id;              ///< MDIO ID of the PHY associated with this port
+	uint8_t xgbe_port_mdio_reset_type;      ///< MDIO PHY reset type
+	                                        ///  @li   <b>00</b> - None
+	                                        ///  @li   <b>01</b> - I2C GPIO
+	                                        ///  @li   <b>10</b> - Integrated GPIO
+	                                        ///  @li   <b>11</b> - Reserved
+	uint8_t xgbe_port_reset_gpio_num;       ///< GPIO used to control the reset
+	uint8_t xgbe_port_mdio_reset_i2c_address; ///< I2C address of PCA9535 MDIO reset GPIO
+	uint8_t xgbe_port_sfp_i2c_address;      ///< I2C address of PCA9535 for SFP
+	uint8_t xgbe_port_sfp_tx_fault_gpio;    ///< GPIO number for SFP+ TX_FAULT
+	uint8_t xgbe_port_sfp_rs_gpio;          ///< GPIO number for SFP+ RS
+	uint8_t xgbe_port_sfp_mod_abs_gpio;     ///< GPIO number for SFP+ Mod_ABS
+	uint8_t xgbe_port_sfp_rx_los_gpio;      ///< GPIO number for SFP+ Rx_LOS
+	uint8_t xgbe_port_sfp_gpio_mask;        ///< GPIO Mask for SFP+
+	                                        ///  @li   <b>1xxx</b> - Rx_LOS not supported
+	                                        ///  @li   <b>x1xx</b> - Mod_ABS not supported
+	                                        ///  @li   <b>xx1x</b> - RS not supported
+	                                        ///  @li   <b>xxx1</b> - TX_FAULT not supported
+	uint8_t xgbe_port_sfp_twi_address;      ///< Address of PCA9545 I2C multiplexor
+	uint8_t xgbe_port_sfp_twi_bus;          ///< Downstream channel of PCA9545
+	uint8_t xgba_port_redriver_present;     ///< Redriver Present or not
+	uint8_t reserve0[3];                    ///< Reserved
+	uint8_t xgba_port_redriver_model;       ///< Redriver Model
+	                                        ///  @li   <b>00</b> - InPhi 4223
+	                                        ///  @li   <b>01</b> - InPhi 4227
+	uint8_t xgba_port_redriver_interface;   ///< Redriver Interface
+	                                        ///  @li   <b>00</b> - MDIO
+	                                        ///  @li   <b>01</b> - I2C
+	uint8_t xgba_port_redriver_address;     ///< Redriver Address
+	uint8_t xgba_port_redriver_lane;        ///< Redriver Lane
+	uint8_t xgba_port_pad_gpio;             ///< Portx_GPIO Pad selection
+	                                        ///  @li   <b>001</b> - MDIO0 pin
+	                                        ///  @li   <b>010</b> - MDIO1 pin
+	                                        ///  @li   <b>100</b> - SFP pin
+	uint8_t xgba_port_pad_mdio;             ///< Portx_Mdio Pad selection
+	                                        ///  @li   <b>001</b> - MDIO0 pin
+	                                        ///  @li   <b>010</b> - MDIO1 pin
+	                                        ///  @li   <b>100</b> - SFP pin
+	uint8_t xgba_port_pad_i2c;              ///< Portx_I2C Pad selection
+	                                        ///  @li   <b>001</b> - MDIO0 pin
+	                                        ///  @li   <b>010</b> - MDIO1 pin
+	                                        ///  @li   <b>100</b> - SFP pin
+	uint8_t reserve1;                       ///< Reserved
+};
+
+#endif /* PI_CEZANNE_PLATFORM_DESCRIPTORS_H */
diff --git a/src/vendorcode/amd/fsp/renoir/soc_dmi_info.h b/src/vendorcode/amd/fsp/renoir/soc_dmi_info.h
new file mode 100644
index 0000000000..5726dffa59
--- /dev/null
+++ b/src/vendorcode/amd/fsp/renoir/soc_dmi_info.h
@@ -0,0 +1,17 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+/*
+ * These definitions are used to describe memory modules physical layout
+ */
+
+#ifndef SOC_DMI_INFO_H
+#define SOC_DMI_INFO_H
+
+#define AGESA_STRUCT_SOCKET_COUNT         2   ///< Number of sockets in AGESA FSP DMI T17 table
+#define AGESA_STRUCT_CHANNELS_PER_SOCKET  8   ///< Channels per socket in AGESA FSP DMI T17 table
+#define AGESA_STRUCT_DIMMS_PER_CHANNEL    4   ///< DIMMs per channel in AGESA FSP DMI T17 table
+#define AGESA_STRUCT_PART_NUMBER_SIZE     21 //TODO check
+
+#define SMBIOS_3_2_3_3_SUPPORT            1
+
+#endif /* SOC_DMI_INFO_H */

From bd858faee8ef6d71a8742808167662ccca259933 Mon Sep 17 00:00:00 2001
From: Maximilian Brune <maximilian.brune@9elements.com>
Date: Tue, 18 Nov 2025 23:20:35 +0100
Subject: [PATCH 2569/3886] mb/amd/crater: Add XGBE support

If XGBE is used on the platform, it can be configured to match different
use cases.

Change-Id: Ia6f7c2b836050e52bfb1d9ff64745d83715c874b
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90104
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/amd/crater/Kconfig              |  52 ++++++
 src/mainboard/amd/crater/Makefile.mk          |   2 +
 src/mainboard/amd/crater/ec.c                 |  29 ++++
 src/mainboard/amd/crater/ec.h                 |   1 +
 .../amd/crater/port_descriptors_renoir.c      | 151 +++++++++++++++++-
 5 files changed, 233 insertions(+), 2 deletions(-)

diff --git a/src/mainboard/amd/crater/Kconfig b/src/mainboard/amd/crater/Kconfig
index 1560201ea3..cc15d467ab 100644
--- a/src/mainboard/amd/crater/Kconfig
+++ b/src/mainboard/amd/crater/Kconfig
@@ -112,6 +112,58 @@ config PCIE_DT_SLOT
 
 endchoice
 
+choice
+	prompt "SGMII lanes interface"
+	depends on XGBE_WWAN_WLAN
+	default GBE_PATH_SELECT_AIC2
+	help
+	  Option to select either AIC2 card (Marvell Phy), AIC3 card (Broadcom Phy) or
+	  Backplane mode for SGMII
+
+config GBE_PATH_SELECT_AIC2
+	bool "AIC2 PHY"
+	help
+	  Select to use AIC2 Marvell Phy card
+
+config GBE_PATH_SELECT_AIC3
+	bool "AIC3 PHY"
+	help
+	  Select to use AIC3 Boradcom Phy card
+
+config XGBE_PATH_SELECT_BACKPLANE
+	bool "BackPlane"
+	help
+	  Select to use BackPlane Mode
+
+endchoice # "SGMII lanes interface"
+
+choice
+	prompt "XGBE port speed"
+	depends on XGBE_WWAN_WLAN && !XGBE_PATH_SELECT_BACKPLANE
+	default XGBE_10_100_1000MB_SPEED
+
+config XGBE_10_100_1000MB_SPEED
+	bool "10/100/1000MB"
+	help
+	  Set XGBE port speed to support 10/100/1000MB.
+
+config XGBE_10MB_SPEED
+	bool "10MB Port Speed"
+	help
+	  Set XGBE port speed to support 10MBps.
+
+config XGBE_100MB_SPEED
+	bool "100 MBps port speed"
+	help
+	  Set XGBE port speed to support 1000MBps.
+
+config XGBE_1G_SPEED
+	bool "1G Port Speed"
+	help
+	  Set XGBE port speed to support 1GBps.
+
+endchoice # "XGBE port speed"
+
 if !EM100	# EM100 defaults in soc/amd/common/blocks/spi/Kconfig
 config EFS_SPI_READ_MODE
 	default 3	# Quad IO (1-1-4)
diff --git a/src/mainboard/amd/crater/Makefile.mk b/src/mainboard/amd/crater/Makefile.mk
index 3207c59c5c..8380fc6fef 100644
--- a/src/mainboard/amd/crater/Makefile.mk
+++ b/src/mainboard/amd/crater/Makefile.mk
@@ -4,10 +4,12 @@ bootblock-y += bootblock.c
 bootblock-y += early_gpio.c
 bootblock-y += ec.c
 
+romstage-y += ec.c
 romstage-$(CONFIG_BOARD_AMD_CRATER_RENOIR) += port_descriptors_renoir.c
 
 ramstage-y += chromeos.c
 ramstage-y += gpio.c
+ramstage-y += ec.c
 ramstage-$(CONFIG_BOARD_AMD_CRATER_RENOIR) += port_descriptors_renoir.c
 
 ifneq ($(wildcard $(MAINBOARD_BLOBS_DIR)/APCB_RN_D4_Updatable.bin),)
diff --git a/src/mainboard/amd/crater/ec.c b/src/mainboard/amd/crater/ec.c
index e9a947523f..533e32de25 100644
--- a/src/mainboard/amd/crater/ec.c
+++ b/src/mainboard/amd/crater/ec.c
@@ -106,6 +106,8 @@
 
 #define ECRAM_BOARDID_OFFSET 0x93
 #define CRATER_REVB    0x42
+#define ECRAM_MACID_OFFSET 0x54
+#define MACID_LEN 12
 
 static void configure_ec_gpio(void)
 {
@@ -211,3 +213,30 @@ void crater_ec_init(void)
 	crater_boardrevision();
 	configure_ec_gpio();
 }
+
+void crater_ec_get_mac_addresses(uint64_t *xgbe_port0_mac, uint64_t *xgbe_port1_mac)
+{
+	uint64_t port0_mac = 0;
+	uint64_t port1_mac = 0;
+	uint8_t value = 0;
+	uint8_t index = 0;
+	uint8_t offset = ECRAM_MACID_OFFSET;
+
+	ec_set_ports(CRATER_EC_CMD, CRATER_EC_DATA);
+	for (index = 0; index < MACID_LEN; index++) {
+		value = ec_read(offset + index);
+		printk(BIOS_SPEW, "READ MACID REG 0x%2x Value 0x%02x\n", offset - index, value);
+
+		if (index < 6) {
+			port0_mac = (port0_mac << 8) | value;
+		} else {
+			port1_mac = (port1_mac << 8) | value;
+		}
+	}
+
+	printk(BIOS_SPEW, "MAC Address XGBE port0: 0x%02llx\n", port0_mac);
+	printk(BIOS_SPEW, "MAC Address XGBE port1: 0x%02llx\n", port1_mac);
+
+	*xgbe_port0_mac = port0_mac;
+	*xgbe_port1_mac = port1_mac;
+}
diff --git a/src/mainboard/amd/crater/ec.h b/src/mainboard/amd/crater/ec.h
index 9dd5cbca1b..f9e90a5244 100644
--- a/src/mainboard/amd/crater/ec.h
+++ b/src/mainboard/amd/crater/ec.h
@@ -5,5 +5,6 @@
 
 void crater_ec_init(void);
 void crater_boardrevision(void);
+void crater_ec_get_mac_addresses(uint64_t *xgbe_port0_mac, uint64_t *xgbe_port1_mac);
 
 #endif /* CRATER_EC_H */
diff --git a/src/mainboard/amd/crater/port_descriptors_renoir.c b/src/mainboard/amd/crater/port_descriptors_renoir.c
index cfc6e2f35c..f24eb874a0 100644
--- a/src/mainboard/amd/crater/port_descriptors_renoir.c
+++ b/src/mainboard/amd/crater/port_descriptors_renoir.c
@@ -10,8 +10,8 @@
 #include <ec/acpi/ec.h>
 #include <stdint.h>
 
-#define ECRAM_MACID_OFFSET 0x54
-#define MACID_LEN 12
+#include <static.h>
+#include "ec.h"
 
 #define ECRAM_BOARDID_OFFSET 0x93
 
@@ -200,3 +200,150 @@ void mainboard_get_dxio_ddi_descriptors(
 	*ddi_descs = crater_ddi_descriptors;
 	*ddi_num = ARRAY_SIZE(crater_ddi_descriptors);
 }
+
+#if CONFIG(XGBE_PATH_SELECT_BACKPLANE)
+
+#define xgbe_port0_table_descriptor { \
+	.xgbe_port_config          = XGBE_PORT_DISABLE, \
+	.xgbe_port_connected_type  = XGBE_BACKPLANE_CONNECTION, \
+	.xgbe_port_platform_config = BACKPLANE_AUTONEG_OFF, \
+	.xgbe_port_supported_speed = XGBE_PORT_SPEED_1G, \
+	.xgba_port_pad_mdio           = 0x0, \
+	.xgba_port_pad_i2c            = 0x1, \
+	.xgbe_port_sfp_tx_fault_gpio  = 0xE, \
+	.xgbe_port_sfp_rx_los_gpio    = 0xD, \
+	.xgbe_port_sfp_mod_abs_gpio   = 0xC, \
+	.xgbe_port_sfp_twi_bus        = 0x1, \
+	.xgbe_port_mdio_reset_type    = 0x0, \
+	.xgbe_port_reset_gpio_num     = 0x0, \
+	.xgbe_port_mdio_reset_i2c_address = 0x0, \
+	.xgbe_port_sfp_i2c_address    = 0x1, \
+	.xgbe_port_sfp_gpio_mask      = 0x2, \
+	.xgbe_port_sfp_rs_gpio        = 0x0, \
+	.xgba_port_redriver_model     = 0x0, \
+	.xgba_port_redriver_interface = 0x1, \
+	.xgba_port_redriver_address   = 0x0, \
+	.xgba_port_redriver_lane      = 0x0, \
+	.xgbe_port_sfp_twi_address    = 0x1C, \
+	.xgba_port_pad_gpio           = 0x0, \
+	.reserve1                     = 0x0, \
+	.xgbe_port_mdio_id            = 0x0, \
+}
+#define xgbe_port1_table_descriptor { \
+	.xgbe_port_config          = XGBE_PORT_DISABLE, \
+	.xgbe_port_connected_type  = XGBE_BACKPLANE_CONNECTION, \
+	.xgbe_port_platform_config = BACKPLANE_AUTONEG_OFF, \
+	.xgbe_port_supported_speed = XGBE_PORT_SPEED_1G, \
+	.xgba_port_pad_mdio           = 0x0, \
+	.xgbe_port_mdio_id            = 0x0, \
+	.xgba_port_pad_i2c            = 0x1, \
+	.xgbe_port_sfp_tx_fault_gpio  = 0xA, \
+	.xgbe_port_sfp_rx_los_gpio    = 0x9, \
+	.xgbe_port_sfp_mod_abs_gpio   = 0x8, \
+	.xgbe_port_sfp_twi_bus        = 0x2, \
+	.xgbe_port_mdio_reset_type    = 0x0, \
+	.xgbe_port_reset_gpio_num     = 0x0, \
+	.xgbe_port_mdio_reset_i2c_address = 0x0, \
+	.xgbe_port_sfp_i2c_address    = 0x1, \
+	.xgbe_port_sfp_gpio_mask      = 0x2, \
+	.xgbe_port_sfp_rs_gpio        = 0x0, \
+	.xgba_port_redriver_model     = 0x0, \
+	.xgba_port_redriver_interface = 0x1, \
+	.xgba_port_redriver_address   = 0x0, \
+	.xgba_port_redriver_lane      = 0x0, \
+	.xgbe_port_sfp_twi_address    = 0x1C, \
+	.xgba_port_pad_gpio           = 0x0, \
+	.reserve1                     = 0x0, \
+}
+
+#else
+
+#define xgbe_port0_table_descriptor { \
+	.xgbe_port_config          = XGBE_PORT_DISABLE, \
+	.xgbe_port_connected_type  = XGBE_CONNECTION_MDIO_PHY, \
+	.xgbe_port_platform_config = XGBE_SOLDERED_DOWN_1000BASE_T, \
+	.xgbe_port_supported_speed = CONFIG(XGBE_1G_SPEED)    ? XGBE_PORT_SPEED_1G : \
+				     CONFIG(XGBE_100MB_SPEED) ? XGBE_PORT_SPEED_100M : \
+				     CONFIG(XGBE_10MB_SPEED)  ? XGBE_PORT_SPEED_10M : XGBE_PORT_SPEED_10_100_1000M, \
+	.xgba_port_pad_mdio           = 0x1, \
+	.xgba_port_pad_i2c            = 0x0, \
+	.xgbe_port_sfp_tx_fault_gpio  = 0xB, \
+	.xgbe_port_sfp_rx_los_gpio    = 0xD, \
+	.xgbe_port_sfp_mod_abs_gpio   = 0xC, \
+	.xgbe_port_sfp_twi_bus        = 0x0, \
+	.xgbe_port_mdio_reset_type    = 0x0, \
+	.xgbe_port_reset_gpio_num     = 0x0, \
+	.xgbe_port_mdio_reset_i2c_address = 0x0, \
+	.xgbe_port_sfp_i2c_address     = 0x1, \
+	.xgbe_port_sfp_gpio_mask       = 0x2, \
+	.xgbe_port_sfp_rs_gpio         = 0x0, \
+	.xgba_port_redriver_model      = 0x0, \
+	.xgba_port_redriver_interface  = 0x1, \
+	.xgba_port_redriver_address    = 0x0, \
+	.xgba_port_redriver_lane       = 0x0, \
+	.xgbe_port_sfp_twi_address     = 0x1C, \
+	.xgba_port_pad_gpio            = 0x0, \
+	.reserve1                      = 0x0, \
+	.xgbe_port_mdio_id             = 0x0, \
+}
+#define xgbe_port1_table_descriptor { \
+	.xgbe_port_config = XGBE_PORT_DISABLE, \
+	.xgbe_port_connected_type = XGBE_CONNECTION_MDIO_PHY, \
+	.xgbe_port_platform_config = XGBE_SOLDERED_DOWN_1000BASE_T, \
+	.xgbe_port_supported_speed = CONFIG(XGBE_1G_SPEED)    ? XGBE_PORT_SPEED_1G : \
+				     CONFIG(XGBE_100MB_SPEED) ? XGBE_PORT_SPEED_100M : \
+				     CONFIG(XGBE_10MB_SPEED)  ? XGBE_PORT_SPEED_10M : XGBE_PORT_SPEED_10_100_1000M, \
+	.xgba_port_pad_mdio          = CONFIG(GBE_PATH_SELECT_AIC3) ? 0x2 : CONFIG(GBE_PATH_SELECT_AIC3) ? 0x01 : 0x0, \
+	.xgbe_port_mdio_id           = CONFIG(GBE_PATH_SELECT_AIC3) ? 0x0 : CONFIG(GBE_PATH_SELECT_AIC3) ? 0x01 : 0x0, \
+	.xgba_port_pad_i2c            = 0x0, \
+	.xgbe_port_sfp_tx_fault_gpio  = 0xA, \
+	.xgbe_port_sfp_rx_los_gpio    = 0x9, \
+	.xgbe_port_sfp_mod_abs_gpio   = 0x8, \
+	.xgbe_port_sfp_twi_bus        = 0x1, \
+	.xgbe_port_mdio_reset_type    = 0x0, \
+	.xgbe_port_reset_gpio_num     = 0x0, \
+	.xgbe_port_mdio_reset_i2c_address = 0x0, \
+	.xgbe_port_sfp_i2c_address    = 0x1, \
+	.xgbe_port_sfp_gpio_mask      = 0x2, \
+	.xgbe_port_sfp_rs_gpio        = 0x0, \
+	.xgba_port_redriver_model     = 0x0, \
+	.xgba_port_redriver_interface = 0x1, \
+	.xgba_port_redriver_address   = 0x0, \
+	.xgba_port_redriver_lane      = 0x0, \
+	.xgbe_port_sfp_twi_address    = 0x1C, \
+	.xgba_port_pad_gpio           = 0x0, \
+	.reserve1                     = 0x0, \
+}
+
+#endif
+
+static void xgbe_init(FSP_M_CONFIG *mcfg)
+{
+	static struct xgbe_port_table xgbe_port[2] = {
+		xgbe_port0_table_descriptor,
+		xgbe_port1_table_descriptor
+	};
+
+	/* MAC can be updated here to pass the same to FSP */
+	crater_ec_get_mac_addresses(&mcfg->xgbe_port0_mac, &mcfg->xgbe_port1_mac);
+	printk(BIOS_SPEW, "MAC Address XGBE port0: 0x%02llx\n", mcfg->xgbe_port0_mac);
+	printk(BIOS_SPEW, "MAC Address XGBE port1: 0x%02llx\n", mcfg->xgbe_port1_mac);
+
+	mcfg->xgbe_port0_config_en = is_dev_enabled(DEV_PTR(xgbe_0));
+	mcfg->xgbe_port1_config_en = is_dev_enabled(DEV_PTR(xgbe_1));
+
+	if (mcfg->xgbe_port0_config_en) {
+		xgbe_port[0].xgbe_port_config = XGBE_PORT_ENABLE;
+		mcfg->xgbe_port0_table = (uint32_t)(uintptr_t)&xgbe_port[0];
+	}
+
+	if (mcfg->xgbe_port1_config_en) {
+		xgbe_port[1].xgbe_port_config = XGBE_PORT_ENABLE;
+		mcfg->xgbe_port1_table = (uint32_t)(uintptr_t)&xgbe_port[1];
+	}
+}
+
+void mb_pre_fspm(FSP_M_CONFIG *mcfg)
+{
+	xgbe_init(mcfg);
+}

From 14b5c004f566264a8c1753a32a1b17290490fca7 Mon Sep 17 00:00:00 2001
From: Ana Carolina Cabral <ana.cpmelo95@gmail.com>
Date: Thu, 24 Apr 2025 10:29:44 -0300
Subject: [PATCH 2570/3886] mb/amd/crater/ec: Create function to get board
 revision

Remove duplicate code and make it into a single function to
read the board revision from ec.

Change-Id: If7f3e7eda2c43417639494880a080fa472474cab
Signed-off-by: Ana Carolina Cabral <ana.cpmelo95@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87441
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/amd/crater/ec.c                      | 14 +++++++++++++-
 src/mainboard/amd/crater/ec.h                      |  3 +++
 src/mainboard/amd/crater/port_descriptors_renoir.c |  9 ++-------
 3 files changed, 18 insertions(+), 8 deletions(-)

diff --git a/src/mainboard/amd/crater/ec.c b/src/mainboard/amd/crater/ec.c
index 533e32de25..b74f72fb1e 100644
--- a/src/mainboard/amd/crater/ec.c
+++ b/src/mainboard/amd/crater/ec.c
@@ -105,7 +105,6 @@
 #define   ECG_WLAN_WWAN_MUX_OFF	BIT(4)
 
 #define ECRAM_BOARDID_OFFSET 0x93
-#define CRATER_REVB    0x42
 #define ECRAM_MACID_OFFSET 0x54
 #define MACID_LEN 12
 
@@ -214,6 +213,19 @@ void crater_ec_init(void)
 	configure_ec_gpio();
 }
 
+uint8_t crater_ec_get_board_revision(void)
+{
+	static uint8_t board_rev;
+
+	if (board_rev)
+		return board_rev;
+
+	ec_set_ports(CRATER_EC_CMD, CRATER_EC_DATA);
+	board_rev = ec_read(ECRAM_BOARDID_OFFSET + 0x3);
+
+	return board_rev;
+}
+
 void crater_ec_get_mac_addresses(uint64_t *xgbe_port0_mac, uint64_t *xgbe_port1_mac)
 {
 	uint64_t port0_mac = 0;
diff --git a/src/mainboard/amd/crater/ec.h b/src/mainboard/amd/crater/ec.h
index f9e90a5244..e47b7d9f2d 100644
--- a/src/mainboard/amd/crater/ec.h
+++ b/src/mainboard/amd/crater/ec.h
@@ -3,8 +3,11 @@
 #ifndef CRATER_EC_H
 #define CRATER_EC_H
 
+#define CRATER_REVB  0x42
+
 void crater_ec_init(void);
 void crater_boardrevision(void);
+uint8_t crater_ec_get_board_revision(void);
 void crater_ec_get_mac_addresses(uint64_t *xgbe_port0_mac, uint64_t *xgbe_port1_mac);
 
 #endif /* CRATER_EC_H */
diff --git a/src/mainboard/amd/crater/port_descriptors_renoir.c b/src/mainboard/amd/crater/port_descriptors_renoir.c
index f24eb874a0..5ac965f84a 100644
--- a/src/mainboard/amd/crater/port_descriptors_renoir.c
+++ b/src/mainboard/amd/crater/port_descriptors_renoir.c
@@ -18,8 +18,6 @@
 #define CRATER_EC_CMD   0x666
 #define CRATER_EC_DATA  0x662
 
-#define CRATER_REVB 0x42
-
 #define mxm_dxio_descriptor { \
 	.engine_type = PCIE_ENGINE, \
 	.port_present = true, \
@@ -164,18 +162,15 @@ void mainboard_get_dxio_ddi_descriptors(
 		const fsp_dxio_descriptor **dxio_descs, size_t *dxio_num,
 		const fsp_ddi_descriptor **ddi_descs, size_t *ddi_num)
 {
-	uint8_t BoardRev;
+	uint8_t board_rev = crater_ec_get_board_revision();
 
 	if ((get_cpu_count() == 4 && get_threads_per_core() == 2) || get_cpu_count() == 2)
 		crater_ddi_descriptors[1].connector_type = DDI_UNUSED_TYPE;
 
-	ec_set_ports(CRATER_EC_CMD, CRATER_EC_DATA);
-	BoardRev = ec_read(ECRAM_BOARDID_OFFSET + 0x3);
-
 	if (CONFIG(ENABLE_EDP)) {
 		crater_ddi_descriptors[1].connector_type = DDI_EDP;
 	} else {
-		if (BoardRev == CRATER_REVB)
+		if (board_rev == CRATER_REVB)
 			crater_ddi_descriptors[1].connector_type = DDI_DP;
 		else
 			crater_ddi_descriptors[1].connector_type = DDI_HDMI;

From 430e34cd0f5455b5f790124c15ab568c26c15423 Mon Sep 17 00:00:00 2001
From: Ana Carolina Cabral <ana.cpmelo95@gmail.com>
Date: Thu, 24 Apr 2025 10:32:21 -0300
Subject: [PATCH 2571/3886] mb/amd/crater: Move gpio configuration to
 early_gpio

Remove the gpio function calls from ec code and mode to early gpio file.

Change-Id: I941828808bdcdac00ab59d48907da1f70024d6e0
Signed-off-by: Ana Carolina Cabral <ana.cpmelo95@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87442
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/amd/crater/early_gpio.c | 18 ++++++++++++++++++
 src/mainboard/amd/crater/ec.c         | 22 ----------------------
 src/mainboard/amd/crater/ec.h         |  1 -
 3 files changed, 18 insertions(+), 23 deletions(-)

diff --git a/src/mainboard/amd/crater/early_gpio.c b/src/mainboard/amd/crater/early_gpio.c
index 097a61f0b8..28ca462a39 100644
--- a/src/mainboard/amd/crater/early_gpio.c
+++ b/src/mainboard/amd/crater/early_gpio.c
@@ -2,6 +2,7 @@
 
 #include <gpio.h>
 #include "gpio.h"
+#include "ec.h"
 
 /* GPIO pins used by coreboot should be initialized in bootblock */
 
@@ -69,7 +70,24 @@ static const struct soc_amd_gpio gpio_set_stage_reset[] = {
 	PAD_NF(GPIO_20, I2C3_SDA, PULL_NONE),
 };
 
+static const struct soc_amd_gpio RevA_gpio_set_stage_ram[] = {
+	/* PCIE x8 SLOT*/
+	PAD_GPO(GPIO_4, HIGH),
+};
+
+static const struct soc_amd_gpio RevB_gpio_set_stage_ram[] = {
+	PAD_GPI(GPIO_4, PULL_UP),
+	PAD_GPO(GPIO_12, LOW),
+};
+
 void mainboard_program_early_gpios(void)
 {
 	gpio_configure_pads(gpio_set_stage_reset, ARRAY_SIZE(gpio_set_stage_reset));
+
+	uint8_t board_rev = crater_ec_get_board_revision();
+	if (board_rev == CRATER_REVB)
+		gpio_configure_pads(RevB_gpio_set_stage_ram, ARRAY_SIZE(RevB_gpio_set_stage_ram));
+	else
+		gpio_configure_pads(RevA_gpio_set_stage_ram, ARRAY_SIZE(RevA_gpio_set_stage_ram));
+
 }
diff --git a/src/mainboard/amd/crater/ec.c b/src/mainboard/amd/crater/ec.c
index b74f72fb1e..b97b1100c4 100644
--- a/src/mainboard/amd/crater/ec.c
+++ b/src/mainboard/amd/crater/ec.c
@@ -185,31 +185,9 @@ static void configure_ec_gpio(void)
 	}
 }
 
-static const struct soc_amd_gpio RevA_gpio_set_stage_ram[] = {
-	/* PCIE x8 SLOT*/
-	PAD_GPO(GPIO_4, HIGH),
-};
-
-static const struct soc_amd_gpio RevB_gpio_set_stage_ram[] = {
-	PAD_GPI(GPIO_4, PULL_UP),
-	PAD_GPO(GPIO_12, LOW),
-};
-
-void crater_boardrevision(void)
-{
-	uint8_t BoardRev;
-	BoardRev = ec_read(ECRAM_BOARDID_OFFSET + 0x3);
-
-	if (BoardRev == CRATER_REVB)
-		gpio_configure_pads(RevB_gpio_set_stage_ram, ARRAY_SIZE(RevB_gpio_set_stage_ram));
-	else
-		gpio_configure_pads(RevA_gpio_set_stage_ram, ARRAY_SIZE(RevA_gpio_set_stage_ram));
-}
-
 void crater_ec_init(void)
 {
 	ec_set_ports(CRATER_EC_CMD, CRATER_EC_DATA);
-	crater_boardrevision();
 	configure_ec_gpio();
 }
 
diff --git a/src/mainboard/amd/crater/ec.h b/src/mainboard/amd/crater/ec.h
index e47b7d9f2d..20303cc94c 100644
--- a/src/mainboard/amd/crater/ec.h
+++ b/src/mainboard/amd/crater/ec.h
@@ -6,7 +6,6 @@
 #define CRATER_REVB  0x42
 
 void crater_ec_init(void);
-void crater_boardrevision(void);
 uint8_t crater_ec_get_board_revision(void);
 void crater_ec_get_mac_addresses(uint64_t *xgbe_port0_mac, uint64_t *xgbe_port1_mac);
 

From c9f124a8fbe3b01ebf7619957e459f543de87536 Mon Sep 17 00:00:00 2001
From: Ana Carolina Cabral <ana.cpmelo95@gmail.com>
Date: Thu, 24 Apr 2025 11:12:49 -0300
Subject: [PATCH 2572/3886] mb/amd/crater/ec: Make macro ENABLE_M2_SSD1 a
 Kconfig option

Move the option to enable M.2 SDD slot to Kconfig file instead of using
a macro. Its already used like a Kconfig option later on, so the if
condition actually works now.

Change-Id: I104eae5501da6ed1fe43039f88d6722c1e54e82d
Signed-off-by: Ana Carolina Cabral <ana.cpmelo95@gmail.com>
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87443
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
---
 src/mainboard/amd/crater/Kconfig | 6 ++++++
 src/mainboard/amd/crater/ec.c    | 5 ++---
 2 files changed, 8 insertions(+), 3 deletions(-)

diff --git a/src/mainboard/amd/crater/Kconfig b/src/mainboard/amd/crater/Kconfig
index cc15d467ab..729e1d6fd8 100644
--- a/src/mainboard/amd/crater/Kconfig
+++ b/src/mainboard/amd/crater/Kconfig
@@ -92,6 +92,12 @@ config ENABLE_EVAL_19V
 	help
 	  Enable the 19V rail for Eval Card PCIe slot
 
+config ENABLE_M2_SSD
+	bool "Enable M.2 SSD Slot"
+	default y
+	help
+	  Use GPP[8:11] connected to M.2 SSD
+
 choice
 	prompt "XGBE/WWAN/WLAN/DT Selection"
 	default XGBE_WWAN_WLAN
diff --git a/src/mainboard/amd/crater/ec.c b/src/mainboard/amd/crater/ec.c
index b97b1100c4..442782e1d4 100644
--- a/src/mainboard/amd/crater/ec.c
+++ b/src/mainboard/amd/crater/ec.c
@@ -9,7 +9,6 @@
 #define CRATER_EC_CMD	0x666
 #define CRATER_EC_DATA	0x662
 
-#define ENABLE_M2_SSD1  1
 #define EC_GPIO_0_ADDR		0xA0
 #define   EC_EVAL_PWREN	BIT(0)
 
@@ -144,7 +143,7 @@ static void configure_ec_gpio(void)
 	ec_write(EC_GPIO_4_ADDR, tmp);
 
 	tmp = ec_read(EC_GPIO_7_ADDR);
-	if (CONFIG(ENABLE_M2_SSD1)) {
+	if (CONFIG(ENABLE_M2_SSD)) {
 		tmp |= (EC7_ODD_SSD_SW | EC7_SSD_HDD_SW);
 	} else {
 		tmp &= ~(EC7_ODD_SSD_SW | EC7_SSD_HDD_SW);
@@ -162,7 +161,7 @@ static void configure_ec_gpio(void)
 	ec_write(EC_GPIO_7_ADDR, tmp);
 
 	tmp = ec_read(EC_GPIO_8_ADDR);
-	if (CONFIG(ENABLE_M2_SSD1)) {
+	if (CONFIG(ENABLE_M2_SSD)) {
 		tmp |= EC8_M2SSD_PWREN;
 	} else {
 		tmp &= ~EC8_M2SSD_PWREN;

From 47101fc224f66353a5ab5dc0bdd96c56d91ef470 Mon Sep 17 00:00:00 2001
From: Maximilian Brune <maximilian.brune@9elements.com>
Date: Tue, 11 Nov 2025 22:01:03 +0100
Subject: [PATCH 2573/3886] soc/amd/cezanne/Kconfig: Make AMDFW_CONFIG_FILE
 configurable

Its useful if you have some binaries downstream which are not published
yet.

Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: I00f67e6eb93af095e3ae1f4851d13cd7666a9851
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90180
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/soc/amd/cezanne/Kconfig | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/src/soc/amd/cezanne/Kconfig b/src/soc/amd/cezanne/Kconfig
index 2fe56c0c4b..955e1fa3bc 100644
--- a/src/soc/amd/cezanne/Kconfig
+++ b/src/soc/amd/cezanne/Kconfig
@@ -353,9 +353,11 @@ config DISABLE_KEYBOARD_RESET_PIN
 menu "PSP Configuration Options"
 
 config AMDFW_CONFIG_FILE
-	string
+	string "AMD PSP Firmware config file"
 	#default "src/soc/amd/cezanne/fw_renoir.cfg" if SOC_AMD_RENOIR
 	default "src/soc/amd/cezanne/fw.cfg"
+	help
+	  Specify the path/location of AMD PSP Firmware config file.
 
 config PSP_DISABLE_POSTCODES
 	bool "Disable PSP post codes"

From 85752323173fe756b76f0426b6672c6331b1506e Mon Sep 17 00:00:00 2001
From: Aamir Bohra <aamirbohra@google.com>
Date: Mon, 24 Nov 2025 09:50:20 +0000
Subject: [PATCH 2574/3886] mb/google/ruby: Migrate to UFSC

Enable Unified Firmware and Secondary Source Configuration (UFSC)
support for Ruby.
UFSC standardizes the bitfields and bitmap definitions for firmware
configuration. Update overridetree.cb with new UFSC definitions and
enable EC_GOOGLE_CHROMEEC_FW_CONFIG_FROM_UFSC.

BUG=b:460231264
TEST=util/abuild/abuild -x -t GOOGLE_RUBY -a
BRANCH=none

Change-Id: If992b89e1c6563404c71af2f77b6170d15c92d61
Signed-off-by: Aamir Bohra <aamirbohra@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90177
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: YH Lin <yueherngl@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
---
 src/mainboard/google/fatcat/Kconfig                |  1 +
 .../google/fatcat/variants/ruby/fw_config.c        |  6 +++---
 .../google/fatcat/variants/ruby/overridetree.cb    | 14 +++++++++-----
 3 files changed, 13 insertions(+), 8 deletions(-)

diff --git a/src/mainboard/google/fatcat/Kconfig b/src/mainboard/google/fatcat/Kconfig
index 5def0388f4..d66905ab67 100644
--- a/src/mainboard/google/fatcat/Kconfig
+++ b/src/mainboard/google/fatcat/Kconfig
@@ -155,6 +155,7 @@ config BOARD_GOOGLE_MODEL_RUBY
 	def_bool n
 	select BOARD_GOOGLE_BASEBOARD_FATCAT
 	select DRIVERS_I2C_TAS2563
+	select EC_GOOGLE_CHROMEEC_FW_CONFIG_FROM_UFSC
 	select HAVE_SLP_S0_GATE
 	select MAINBOARD_HAS_GOOGLE_STRAUSS_KEYBOARD
 
diff --git a/src/mainboard/google/fatcat/variants/ruby/fw_config.c b/src/mainboard/google/fatcat/variants/ruby/fw_config.c
index 396420fa6f..e216523900 100644
--- a/src/mainboard/google/fatcat/variants/ruby/fw_config.c
+++ b/src/mainboard/google/fatcat/variants/ruby/fw_config.c
@@ -107,11 +107,11 @@ void fw_config_gpio_padbased_override(struct pad_config *padbased_table)
 		return;
 	}
 
-	if (fw_config_probe(FW_CONFIG(AUDIO, AUDIO_NONE))) {
+	if (fw_config_probe(FW_CONFIG(AUDIO_CODEC, AUDIO_CODEC_UNKNOWN))) {
 		GPIO_PADBASED_OVERRIDE(padbased_table, audio_disable_pads);
 		GPIO_PADBASED_OVERRIDE(padbased_table, bt_i2s_disable_pads);
-	} else if (fw_config_probe(FW_CONFIG(AUDIO, AUDIO_TAS2563_ALC5682I_I2S))) {
-		printk(BIOS_INFO, "Configure GPIOs for I2S TAS2563 ALC5682 audio.\n");
+	} else if (fw_config_probe(FW_CONFIG(AUDIO_CODEC, AUDIO_CODEC_ALC5682IVS))) {
+		printk(BIOS_INFO, "Configure GPIOs for I2S ALC5682IVS audio.\n");
 		GPIO_PADBASED_OVERRIDE(padbased_table, i2s_enable_pads);
 		printk(BIOS_INFO, "Configure GPIOs for BT offload mode.\n");
 		GPIO_PADBASED_OVERRIDE(padbased_table, bt_i2s_enable_pads);
diff --git a/src/mainboard/google/fatcat/variants/ruby/overridetree.cb b/src/mainboard/google/fatcat/variants/ruby/overridetree.cb
index 76fce5287f..98dae87dc4 100644
--- a/src/mainboard/google/fatcat/variants/ruby/overridetree.cb
+++ b/src/mainboard/google/fatcat/variants/ruby/overridetree.cb
@@ -1,7 +1,11 @@
 fw_config
-	field AUDIO 0 1
-		option AUDIO_NONE			0
-		option AUDIO_TAS2563_ALC5682I_I2S	1
+	field AUDIO_CODEC 0 2
+		option AUDIO_CODEC_UNKNOWN	0
+		option AUDIO_CODEC_ALC5682IVS	1
+	end
+	field AUDIO_AMPLIFIER 3 5
+		option AUDIO_AMPLIFIER_UNKNOWN	0
+		option AUDIO_AMPLIFIER_TAS2563	1
 	end
 end
 
@@ -249,7 +253,7 @@ chip soc/intel/pantherlake
 				register "property_list[0].name" = ""realtek,jd-src""
 				register "property_list[0].integer" = "1"
 				device i2c 1a on
-					probe AUDIO AUDIO_TAS2563_ALC5682I_I2S
+					probe AUDIO_CODEC AUDIO_CODEC_ALC5682IVS
 				end
 			end
 			chip drivers/i2c/tas2563
@@ -260,7 +264,7 @@ chip soc/intel/pantherlake
 				register "audio_slots[2]" = "0x4c"
 				register "audio_slots[3]" = "0x4d"
 				device i2c 4a on
-					probe AUDIO AUDIO_TAS2563_ALC5682I_I2S
+					probe AUDIO_AMPLIFIER AUDIO_AMPLIFIER_TAS2563
 				end
 			end
 		end

From c7273c8ddc16a957146a4dd51af1ee602985be7b Mon Sep 17 00:00:00 2001
From: Luca Lai <luca.lai@lcfc.corp-partner.google.com>
Date: Tue, 25 Nov 2025 18:48:04 +0800
Subject: [PATCH 2575/3886] mb/google/fatcat/var/ruby: Add proto touch panel
 address

Because the proto and evt build use the same panel but different
controllers, so add proto touch panel address to fit two controllers.

BUG=b:452216678
TEST=Build FW and boot to OS, check touch function works.

Change-Id: Ia9a3764ffe85aa69ba1c4c3f4ae8fd2717e1e570
Signed-off-by: Luca Lai <luca.lai@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90200
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: YH Lin <yueherngl@google.com>
---
 .../fatcat/variants/ruby/overridetree.cb       | 18 ++++++++++++++++++
 1 file changed, 18 insertions(+)

diff --git a/src/mainboard/google/fatcat/variants/ruby/overridetree.cb b/src/mainboard/google/fatcat/variants/ruby/overridetree.cb
index 98dae87dc4..2e5f29faa6 100644
--- a/src/mainboard/google/fatcat/variants/ruby/overridetree.cb
+++ b/src/mainboard/google/fatcat/variants/ruby/overridetree.cb
@@ -289,6 +289,24 @@ chip soc/intel/pantherlake
 			end
 		end # I2C4
 		device ref i2c5 on
+			chip drivers/i2c/hid
+				register "generic.hid" = ""GT7936L""
+				register "generic.desc" = ""Goodix Touchscreen""
+				register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_F18_IRQ)"
+				register "generic.detect" = "1"
+				register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_F16)"
+				register "generic.reset_delay_ms" = "150"
+				register "generic.reset_off_delay_ms" = "1"
+				register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_F08)"
+				register "generic.enable_delay_ms" = "6"
+				register "generic.enable_off_delay_ms" = "30"
+				register "generic.stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_E05)"
+				register "generic.stop_delay_ms" = "1"
+				register "generic.has_power_resource" = "1"
+				register "generic.use_gpio_for_status" = "true"
+				register "hid_desc_reg_offset" = "0x01"
+				device i2c 0x14 on end
+			end
 			chip drivers/i2c/hid
 				register "generic.hid" = ""GT7936L""
 				register "generic.desc" = ""Goodix Touchscreen""

From 2148143ae9f1a68beeb406ba383e78ec0322b63b Mon Sep 17 00:00:00 2001
From: Jeremy Compostella <jeremy.compostella@intel.com>
Date: Thu, 6 Nov 2025 09:10:53 -0800
Subject: [PATCH 2576/3886] soc/intel/pantherlake: Separate TDC configuration
 for different TDPs

This commit refactors the Panther Lake SoC power mapping and
configuration to support distinct Thermal Design Current (TDC) settings
for each TDP variant and SKU. Previously, TDC values were mapped
directly to SKUs, which limited flexibility and could lead to incorrect
current settings for CPUs with the same SKU but different TDP
requirements.

TEST=On a Fatcat device with a 25W TDP, the FSP logs show that the
     appropriate TDC settings were applied.

Change-Id: Ie645110e9ff200ecb601faf427958ded731fb22b
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89932
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Guvendik, Bora <bora.guvendik@intel.com>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
---
 src/soc/intel/pantherlake/chip.h              | 50 ++++++++++++-------
 src/soc/intel/pantherlake/chipset_ptl.cb      | 19 +++----
 .../intel/pantherlake/romstage/fsp_params.c   |  4 +-
 3 files changed, 40 insertions(+), 33 deletions(-)

diff --git a/src/soc/intel/pantherlake/chip.h b/src/soc/intel/pantherlake/chip.h
index 310e6d3bc2..d6b3aff027 100644
--- a/src/soc/intel/pantherlake/chip.h
+++ b/src/soc/intel/pantherlake/chip.h
@@ -84,32 +84,44 @@ enum soc_intel_pantherlake_sku {
 	MAX_PTL_SKUS,
 };
 
+/* Thermal Design Current for different SKUs */
+enum soc_intel_pantherlake_tdc {
+	PTL_TDC_1,
+	PTL_TDC_2,
+	PTL_TDC_3,
+	PTL_TDC_4,
+	PTL_TDC_5,
+	WCL_TDC_1,
+	MAX_PTL_TDC
+};
+
 /* Mapping of different SKUs based on CPU ID and TDP values */
 static const struct soc_intel_pantherlake_power_map {
 	unsigned int cpu_id;
 	enum soc_intel_pantherlake_power_limits limits;
 	enum soc_intel_pantherlake_cpu_tdps cpu_tdp;
 	enum soc_intel_pantherlake_sku sku;
+	enum soc_intel_pantherlake_tdc tdc;
 } cpuid_to_ptl[] = {
-	{ PCI_DID_INTEL_PTL_U_ID_1, PTL_CORE_1, TDP_15W, PTL_SKU_1 },
-	{ PCI_DID_INTEL_PTL_U_ID_1, PTL_CORE_1, TDP_25W, PTL_SKU_1 },
-	{ PCI_DID_INTEL_PTL_U_ID_2, PTL_CORE_2, TDP_15W, PTL_SKU_5 },
-	{ PCI_DID_INTEL_PTL_U_ID_2, PTL_CORE_2, TDP_25W, PTL_SKU_5 },
-	{ PCI_DID_INTEL_PTL_U_ID_3, PTL_CORE_1, TDP_15W, PTL_SKU_1 },
-	{ PCI_DID_INTEL_PTL_U_ID_3, PTL_CORE_1, TDP_25W, PTL_SKU_1 },
-	{ PCI_DID_INTEL_PTL_H_ID_1, PTL_CORE_3, TDP_25W, PTL_SKU_2 },
-	{ PCI_DID_INTEL_PTL_H_ID_2, PTL_CORE_3, TDP_25W, PTL_SKU_3 },
-	{ PCI_DID_INTEL_PTL_H_ID_3, PTL_CORE_4, TDP_25W, PTL_SKU_6 },
-	{ PCI_DID_INTEL_PTL_H_ID_4, PTL_CORE_4, TDP_25W, PTL_SKU_6 },
-	{ PCI_DID_INTEL_PTL_H_ID_5, PTL_CORE_4, TDP_25W, PTL_SKU_4 },
-	{ PCI_DID_INTEL_PTL_H_ID_6, PTL_CORE_4, TDP_25W, PTL_SKU_4 },
-	{ PCI_DID_INTEL_PTL_H_ID_7, PTL_CORE_4, TDP_25W, PTL_SKU_4 },
-	{ PCI_DID_INTEL_PTL_H_ID_8, PTL_CORE_3, TDP_25W, PTL_SKU_2 },
-	{ PCI_DID_INTEL_WCL_ID_1, WCL_CORE, TDP_15W, WCL_SKU_1},
-	{ PCI_DID_INTEL_WCL_ID_2, WCL_CORE, TDP_15W, WCL_SKU_2},
-	{ PCI_DID_INTEL_WCL_ID_3, WCL_CORE, TDP_15W, WCL_SKU_3},
-	{ PCI_DID_INTEL_WCL_ID_4, WCL_CORE, TDP_15W, WCL_SKU_4},
-	{ PCI_DID_INTEL_WCL_ID_5, WCL_CORE, TDP_15W, WCL_SKU_5},
+	{ PCI_DID_INTEL_PTL_U_ID_1, PTL_CORE_1, TDP_15W, PTL_SKU_1, PTL_TDC_1 },
+	{ PCI_DID_INTEL_PTL_U_ID_1, PTL_CORE_1, TDP_25W, PTL_SKU_1, PTL_TDC_2 },
+	{ PCI_DID_INTEL_PTL_U_ID_2, PTL_CORE_2, TDP_15W, PTL_SKU_5, PTL_TDC_1 },
+	{ PCI_DID_INTEL_PTL_U_ID_2, PTL_CORE_2, TDP_25W, PTL_SKU_5, PTL_TDC_2 },
+	{ PCI_DID_INTEL_PTL_U_ID_3, PTL_CORE_1, TDP_15W, PTL_SKU_1, PTL_TDC_1 },
+	{ PCI_DID_INTEL_PTL_U_ID_3, PTL_CORE_1, TDP_25W, PTL_SKU_1, PTL_TDC_2 },
+	{ PCI_DID_INTEL_PTL_H_ID_1, PTL_CORE_3, TDP_25W, PTL_SKU_2, PTL_TDC_3 },
+	{ PCI_DID_INTEL_PTL_H_ID_2, PTL_CORE_3, TDP_25W, PTL_SKU_3, PTL_TDC_4 },
+	{ PCI_DID_INTEL_PTL_H_ID_3, PTL_CORE_4, TDP_25W, PTL_SKU_6, PTL_TDC_3 },
+	{ PCI_DID_INTEL_PTL_H_ID_4, PTL_CORE_4, TDP_25W, PTL_SKU_6, PTL_TDC_3 },
+	{ PCI_DID_INTEL_PTL_H_ID_5, PTL_CORE_4, TDP_25W, PTL_SKU_4, PTL_TDC_5 },
+	{ PCI_DID_INTEL_PTL_H_ID_6, PTL_CORE_4, TDP_25W, PTL_SKU_4, PTL_TDC_5 },
+	{ PCI_DID_INTEL_PTL_H_ID_7, PTL_CORE_4, TDP_25W, PTL_SKU_4, PTL_TDC_5 },
+	{ PCI_DID_INTEL_PTL_H_ID_8, PTL_CORE_3, TDP_25W, PTL_SKU_2, PTL_TDC_3 },
+	{ PCI_DID_INTEL_WCL_ID_1, WCL_CORE, TDP_15W, WCL_SKU_1, WCL_TDC_1 },
+	{ PCI_DID_INTEL_WCL_ID_2, WCL_CORE, TDP_15W, WCL_SKU_2, WCL_TDC_1 },
+	{ PCI_DID_INTEL_WCL_ID_3, WCL_CORE, TDP_15W, WCL_SKU_3, WCL_TDC_1 },
+	{ PCI_DID_INTEL_WCL_ID_4, WCL_CORE, TDP_15W, WCL_SKU_4, WCL_TDC_1 },
+	{ PCI_DID_INTEL_WCL_ID_5, WCL_CORE, TDP_15W, WCL_SKU_5, WCL_TDC_1 },
 };
 
 /* Types of display ports */
diff --git a/src/soc/intel/pantherlake/chipset_ptl.cb b/src/soc/intel/pantherlake/chipset_ptl.cb
index 676a309f2e..a310a1be3f 100644
--- a/src/soc/intel/pantherlake/chipset_ptl.cb
+++ b/src/soc/intel/pantherlake/chipset_ptl.cb
@@ -8,7 +8,11 @@ chip soc/intel/pantherlake
 		.tdp_pl4 = 163,
 		.tdp_pl4_fastvmode = 150,
 	}"
-	register "thermal_design_current[PTL_SKU_1]" = "{
+	register "thermal_design_current[PTL_TDC_1]" = "{
+		[VR_DOMAIN_IA] = 23 * 8,
+		[VR_DOMAIN_GT] = 15 * 8
+	}"
+	register "thermal_design_current[PTL_TDC_2]" = "{
 		[VR_DOMAIN_IA] = 23 * 8,
 		[VR_DOMAIN_GT] = 23 * 8
 	}"
@@ -25,10 +29,6 @@ chip soc/intel/pantherlake
 		.tdp_pl4 = 163,
 		.tdp_pl4_fastvmode = 150,
 	}"
-	register "thermal_design_current[PTL_SKU_5]" = "{
-		[VR_DOMAIN_IA] = 23 * 8,
-		[VR_DOMAIN_GT] = 23 * 8
-	}"
 	register "icc_max[PTL_SKU_5]" = "{
 		[VR_DOMAIN_IA] = 80 * 4,
 		[VR_DOMAIN_GT] = 56 * 4,
@@ -42,7 +42,7 @@ chip soc/intel/pantherlake
 		.tdp_pl4 = 175,
 		.tdp_pl4_fastvmode = 160,
 	}"
-	register "thermal_design_current[PTL_SKU_2]" = "{
+	register "thermal_design_current[PTL_TDC_3]" = "{
 		[VR_DOMAIN_IA] = 31 * 8,
 		[VR_DOMAIN_GT] = 44 * 8
 	}"
@@ -52,7 +52,7 @@ chip soc/intel/pantherlake
 		[VR_DOMAIN_SA] = 56 * 4,
 		[VR_DOMAIN_ATOM] = 30 * 4
 	}"
-	register "thermal_design_current[PTL_SKU_3]" = "{
+	register "thermal_design_current[PTL_TDC_4]" = "{
 		[VR_DOMAIN_IA] = 31 * 8,
 		[VR_DOMAIN_GT] = 23 * 8
 	}"
@@ -64,11 +64,6 @@ chip soc/intel/pantherlake
 		.tdp_pl4_fastvmode = 140
 	}"
 
-
-	register "thermal_design_current[PTL_SKU_6]" = "{
-		[VR_DOMAIN_IA] = 31 * 8,
-		[VR_DOMAIN_GT] = 44 * 8
-	}"
 	register "icc_max[PTL_SKU_6]" = "{
 		[VR_DOMAIN_IA] = 90 * 4,
 		[VR_DOMAIN_GT] = 124 * 4,
diff --git a/src/soc/intel/pantherlake/romstage/fsp_params.c b/src/soc/intel/pantherlake/romstage/fsp_params.c
index 69f3ed4d9b..63a3f3b013 100644
--- a/src/soc/intel/pantherlake/romstage/fsp_params.c
+++ b/src/soc/intel/pantherlake/romstage/fsp_params.c
@@ -350,10 +350,10 @@ static void fill_fspm_vr_config_params(FSP_M_CONFIG *m_cfg,
 	}
 
 	for (size_t i = 0; i < ARRAY_SIZE(config->thermal_design_current[0]); i++) {
-		if (!config->thermal_design_current[map->sku][i])
+		if (!config->thermal_design_current[map->tdc][i])
 			continue;
 		m_cfg->TdcEnable[i] = 1;
-		m_cfg->TdcCurrentLimit[i] = config->thermal_design_current[map->sku][i];
+		m_cfg->TdcCurrentLimit[i] = config->thermal_design_current[map->tdc][i];
 	}
 
 	for (size_t i = 0; i < ARRAY_SIZE(config->icc_max[0]); i++) {

From 6dbcf903a599923bb8eff573fc10d26d3e4cfe77 Mon Sep 17 00:00:00 2001
From: Jeremy Compostella <jeremy.compostella@intel.com>
Date: Tue, 18 Nov 2025 09:21:30 -0800
Subject: [PATCH 2577/3886] soc/intel/pantherlake: Add ICC Max and TDC settings
 for SKU_7

SKU_7 ICC Max and TDC were not accurate. This commit aligns SKU_7
settings with document #813278 - Panther Lake H Platform Power Map
2.1.1.

Change-Id: Ia66ca5c0d2dc1ba0f0cf3b21476e83923e49969e
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90096
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
---
 src/soc/intel/pantherlake/chip.h         | 3 ++-
 src/soc/intel/pantherlake/chipset_ptl.cb | 7 +++++++
 2 files changed, 9 insertions(+), 1 deletion(-)

diff --git a/src/soc/intel/pantherlake/chip.h b/src/soc/intel/pantherlake/chip.h
index d6b3aff027..d383d63fa5 100644
--- a/src/soc/intel/pantherlake/chip.h
+++ b/src/soc/intel/pantherlake/chip.h
@@ -76,6 +76,7 @@ enum soc_intel_pantherlake_sku {
 	PTL_SKU_4,
 	PTL_SKU_5,
 	PTL_SKU_6,
+	PTL_SKU_7,
 	WCL_SKU_1,
 	WCL_SKU_2,
 	WCL_SKU_3,
@@ -115,7 +116,7 @@ static const struct soc_intel_pantherlake_power_map {
 	{ PCI_DID_INTEL_PTL_H_ID_4, PTL_CORE_4, TDP_25W, PTL_SKU_6, PTL_TDC_3 },
 	{ PCI_DID_INTEL_PTL_H_ID_5, PTL_CORE_4, TDP_25W, PTL_SKU_4, PTL_TDC_5 },
 	{ PCI_DID_INTEL_PTL_H_ID_6, PTL_CORE_4, TDP_25W, PTL_SKU_4, PTL_TDC_5 },
-	{ PCI_DID_INTEL_PTL_H_ID_7, PTL_CORE_4, TDP_25W, PTL_SKU_4, PTL_TDC_5 },
+	{ PCI_DID_INTEL_PTL_H_ID_7, PTL_CORE_4, TDP_25W, PTL_SKU_7, PTL_TDC_4 },
 	{ PCI_DID_INTEL_PTL_H_ID_8, PTL_CORE_3, TDP_25W, PTL_SKU_2, PTL_TDC_3 },
 	{ PCI_DID_INTEL_WCL_ID_1, WCL_CORE, TDP_15W, WCL_SKU_1, WCL_TDC_1 },
 	{ PCI_DID_INTEL_WCL_ID_2, WCL_CORE, TDP_15W, WCL_SKU_2, WCL_TDC_1 },
diff --git a/src/soc/intel/pantherlake/chipset_ptl.cb b/src/soc/intel/pantherlake/chipset_ptl.cb
index a310a1be3f..e19ca02080 100644
--- a/src/soc/intel/pantherlake/chipset_ptl.cb
+++ b/src/soc/intel/pantherlake/chipset_ptl.cb
@@ -71,6 +71,13 @@ chip soc/intel/pantherlake
 		[VR_DOMAIN_ATOM] = 30 * 4
 	}"
 
+	register "icc_max[PTL_SKU_7]" = "{
+		[VR_DOMAIN_IA] = 90 * 4,
+		[VR_DOMAIN_GT] = 56 * 4,
+		[VR_DOMAIN_SA] = 56 * 4,
+		[VR_DOMAIN_ATOM] = 30 * 4
+	}"
+
 	register "tdc_mode[VR_DOMAIN_IA]" = "TDC_IRMS"
 	register "tdc_time_window_ms[VR_DOMAIN_IA]" = "28000"
 

From b0ee0c462051c0f2d03749ecdb8146a61bb69875 Mon Sep 17 00:00:00 2001
From: Jeremy Compostella <jeremy.compostella@intel.com>
Date: Thu, 6 Nov 2025 12:52:22 -0800
Subject: [PATCH 2578/3886] soc/intel/pantherlake: Fix IA domain TDC value for
 PTL_TDC_2 SKU

Align the IA domain Thermal Design Current (TDC) value for PTL_TDC_2
with Document #813289 power map revision 2.1. The previous value 23A did
not match the updated specification, which now requires 28A. This change
ensures that the firmware correctly reflects the hardware power limits
for this SKU, preventing potential power delivery issues and improving
system stability.

Change-Id: I16bb510b8ec2ad1ffdeba20bfe26d0cbad209088
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89935
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/soc/intel/pantherlake/chipset_ptl.cb | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/soc/intel/pantherlake/chipset_ptl.cb b/src/soc/intel/pantherlake/chipset_ptl.cb
index e19ca02080..72907656ef 100644
--- a/src/soc/intel/pantherlake/chipset_ptl.cb
+++ b/src/soc/intel/pantherlake/chipset_ptl.cb
@@ -13,7 +13,7 @@ chip soc/intel/pantherlake
 		[VR_DOMAIN_GT] = 15 * 8
 	}"
 	register "thermal_design_current[PTL_TDC_2]" = "{
-		[VR_DOMAIN_IA] = 23 * 8,
+		[VR_DOMAIN_IA] = 28 * 8,
 		[VR_DOMAIN_GT] = 23 * 8
 	}"
 	register "icc_max[PTL_SKU_1]" = "{

From cb1045a8b8030ddb8a5f6c388da8a63cd4050be3 Mon Sep 17 00:00:00 2001
From: Jeremy Compostella <jeremy.compostella@intel.com>
Date: Thu, 20 Nov 2025 10:03:37 -0800
Subject: [PATCH 2579/3886] soc/intel/pantherlake: Update GT domain TDC value
 for PTL_TDC_1 SKU

Update the GT domain Thermal Design Current (TDC) value for the
PTL_TDC_1 SKU from 15A to 23A to align with the latest hardware
specifications. The previous value was inconsistent with the intended
power map, which could lead to incorrect power delivery settings and
potential system instability. This change ensures compliance with
Document #813289, revision 2.1.

Change-Id: Ib6b4ddc422de62585658b5e8464d598762b947ee
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90136
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Guvendik, Bora <bora.guvendik@intel.com>
---
 src/soc/intel/pantherlake/chipset_ptl.cb | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/soc/intel/pantherlake/chipset_ptl.cb b/src/soc/intel/pantherlake/chipset_ptl.cb
index 72907656ef..e646c5dc4e 100644
--- a/src/soc/intel/pantherlake/chipset_ptl.cb
+++ b/src/soc/intel/pantherlake/chipset_ptl.cb
@@ -10,7 +10,7 @@ chip soc/intel/pantherlake
 	}"
 	register "thermal_design_current[PTL_TDC_1]" = "{
 		[VR_DOMAIN_IA] = 23 * 8,
-		[VR_DOMAIN_GT] = 15 * 8
+		[VR_DOMAIN_GT] = 23 * 8
 	}"
 	register "thermal_design_current[PTL_TDC_2]" = "{
 		[VR_DOMAIN_IA] = 28 * 8,

From 9f675eb96ba1457682c2321e7b2c0bab74511837 Mon Sep 17 00:00:00 2001
From: Kapil Porwal <kapilporwal@google.com>
Date: Tue, 25 Nov 2025 11:31:02 +0530
Subject: [PATCH 2580/3886] soc/qc/common: Update SPMI_ADDR macro for better
 type safety

Update the SPMI_ADDR macro to wrap both the slave and reg
arguments in parentheses.

The previous definition, ((slave << 16) | reg), led to incorrect
address calculation when the slave argument was an arithmetic or
logical expression (e.g., (a | b)), as the bit-shift operator (<<)
has higher precedence than the logical OR (|).

The revised macro guarantees that the full slave expression is
evaluated before the bit shift, ensuring correct SPMI register
address construction.

Key changes:
- Wrap slave and reg arguments in parentheses within
  SPMI_ADDR definition.

BUG=b:439819922
TEST=Verify that the SPMI_ADDR output is correct.

e.g. SPMI_ADDR(0x02 | 0x01, 0x200)
Output before this change:
```
((0x02 | 0x01 << 16) | 0x200)
(0x02 | 0x010000 | 0x200)
(0x010202)
```
Output after this change:
```
(((0x02 | 0x01) << 16) | 0x200)
(((0x03) << 16) | 0x200)
((0x030000) | 0x200)
(0x030200)
```

Change-Id: I58b36b62f0b5a59c03a1c1d08640fe9086d81d7a
Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90198
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/soc/qualcomm/common/include/soc/qcom_spmi.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/soc/qualcomm/common/include/soc/qcom_spmi.h b/src/soc/qualcomm/common/include/soc/qcom_spmi.h
index 533486cb84..2c0d9416ab 100644
--- a/src/soc/qualcomm/common/include/soc/qcom_spmi.h
+++ b/src/soc/qualcomm/common/include/soc/qcom_spmi.h
@@ -7,7 +7,7 @@
 #include <stdint.h>
 
 /* Macro to construct SPMI address from slave ID and register offset */
-#define SPMI_ADDR(slave, reg) ((slave << 16) | reg)
+#define SPMI_ADDR(slave, reg) (((slave) << 16) | (reg))
 
 int spmi_read8(uint32_t addr);
 int spmi_write8(uint32_t addr, uint8_t data);

From 293f3a7f5c0bbc2bcf0c09db337a11897cf40d5b Mon Sep 17 00:00:00 2001
From: Kapil Porwal <kapilporwal@google.com>
Date: Mon, 24 Nov 2025 22:02:16 +0530
Subject: [PATCH 2581/3886] soc/qc/spmi: Add API to read byte array

Introduce a new API, spmi_read_bytes(), to allow reading a
sequence of registers from a Qualcomm PMIC using the SPMI bus.

While the existing spmi_read8() is suitable for single-byte
access, reading large log areas (like the PON history log)
requires iterating over a contiguous block of addresses. This
new function encapsulates the required loop, calling spmi_read8()
sequentially for each address in the range.

This abstraction improves code cleanliness and makes high-level PMIC
log parsing much simpler.

Key changes:
- Define spmi_read_bytes() prototype in qcom_spmi.h.
- Implement spmi_read_bytes() in spmi.c to perform sequential
  reads using spmi_read8().

BUG=b:439819922
TEST=Verify off-mode charging behavior on Google/Quenbi.

Change-Id: I6017336a882a8fa8d771b0127e78dd4f0fdbdd0e
Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90191
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
---
 src/soc/qualcomm/common/include/soc/qcom_spmi.h |  1 +
 src/soc/qualcomm/common/spmi.c                  | 16 ++++++++++++++++
 2 files changed, 17 insertions(+)

diff --git a/src/soc/qualcomm/common/include/soc/qcom_spmi.h b/src/soc/qualcomm/common/include/soc/qcom_spmi.h
index 2c0d9416ab..65d2e17bba 100644
--- a/src/soc/qualcomm/common/include/soc/qcom_spmi.h
+++ b/src/soc/qualcomm/common/include/soc/qcom_spmi.h
@@ -11,5 +11,6 @@
 
 int spmi_read8(uint32_t addr);
 int spmi_write8(uint32_t addr, uint8_t data);
+int spmi_read_bytes(uint32_t addr, uint8_t *data, uint32_t num_bytes);
 
 #endif	// __SOC_QCOM_SPMI_H__
diff --git a/src/soc/qualcomm/common/spmi.c b/src/soc/qualcomm/common/spmi.c
index 51a37058b0..2409cbbf23 100644
--- a/src/soc/qualcomm/common/spmi.c
+++ b/src/soc/qualcomm/common/spmi.c
@@ -125,3 +125,19 @@ int spmi_write8(uint32_t addr, uint8_t data)
 
 	return ret;
 }
+
+int spmi_read_bytes(uint32_t addr, uint8_t *data, uint32_t num_bytes)
+{
+	int spmi_result;
+	if (!data)
+		return -1;
+
+	for (uint32_t i = 0; i < num_bytes; i++) {
+		spmi_result = spmi_read8(addr + i);
+		if (spmi_result < 0)
+			return -1;
+		*data = spmi_result & 0xff;
+		data++;
+	}
+	return 0;
+}

From 201ebd48ee2dca15025eb5607f7da08d8c4a5452 Mon Sep 17 00:00:00 2001
From: Kapil Porwal <kapilporwal@google.com>
Date: Mon, 24 Nov 2025 22:03:50 +0530
Subject: [PATCH 2582/3886] soc/qc/x1p42100: Add APIs to read PON reason from
 PMIC

Add the Power-On (PON) history log parsing and status API to the
SOC layer (soc/qualcomm/x1p42100/pmic.c).

This code is specific to the Qualcomm PMIC architecture (reading
registers for PON events and reasons), making it an SOC-specific
utility rather than a board-level policy. Moving it here improves
modularization and allows other X1p42100-based boards to reuse this
critical power management logic.

Key APIs introduced:
- pm_pon_read_pon_hist(): Reads the raw circular PON event log
  from the PMIC, reverses the buffer to put the latest entry first.
- is_pon_on_ac(): Interprets the log to detect if the power-on
  reason was due to AC/Cable Power (PON_CBLPWR_RSN).

Key changes:
- Create src/soc/qualcomm/x1p42100/include/soc/pmic.h with PON
  definitions and API prototypes.
- Create src/soc/qualcomm/x1p42100/pmic.c containing the PON
  log reading and parsing logic.
- Add pmic.c to the SOC's romstage build via Makefile.mk.

BUG=b:439819922
TEST=Verify off-mode charging behavior on Google/Quenbi.

Change-Id: I8cd1478b9f8d53519f603e8f5168d0a51fa54971
Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90192
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/soc/qualcomm/x1p42100/Makefile.mk        |   1 +
 src/soc/qualcomm/x1p42100/include/soc/pmic.h |  53 ++++++
 src/soc/qualcomm/x1p42100/pmic.c             | 175 +++++++++++++++++++
 3 files changed, 229 insertions(+)
 create mode 100644 src/soc/qualcomm/x1p42100/include/soc/pmic.h
 create mode 100644 src/soc/qualcomm/x1p42100/pmic.c

diff --git a/src/soc/qualcomm/x1p42100/Makefile.mk b/src/soc/qualcomm/x1p42100/Makefile.mk
index 0c6b9469f2..85191ea52c 100644
--- a/src/soc/qualcomm/x1p42100/Makefile.mk
+++ b/src/soc/qualcomm/x1p42100/Makefile.mk
@@ -37,6 +37,7 @@ romstage-y += mmu.c
 romstage-y += ../common/aop_load_reset.c
 romstage-$(CONFIG_DRIVERS_UART) += ../common/qupv3_uart.c
 romstage-y += ../common/spmi.c
+romstage-y += pmic.c
 
 ################################################################################
 ramstage-y += soc.c
diff --git a/src/soc/qualcomm/x1p42100/include/soc/pmic.h b/src/soc/qualcomm/x1p42100/include/soc/pmic.h
new file mode 100644
index 0000000000..db798d6b75
--- /dev/null
+++ b/src/soc/qualcomm/x1p42100/include/soc/pmic.h
@@ -0,0 +1,53 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef _SOC_QUALCOMM_X1P42100_PMIC_H__
+#define _SOC_QUALCOMM_X1P42100_PMIC_H__
+
+#include <types.h>
+
+#define PMIC_SLAVE_ID				0x00
+#define SDAM05_BASE_ADDR			0x7400
+#define MEM_OFFSET_START			0x40
+#define PON_EVENT_LOG_AREA_SIZE			(127 - 11 + 1)
+#define PON_EVENT_TOTAL_LOG_AREA_SIZE		(PON_EVENT_LOG_AREA_SIZE * 2)
+
+#define PM_PON_SDAM_COUNT_ADDR			(SDAM05_BASE_ADDR + MEM_OFFSET_START + 5)
+#define PM_PON_ENQUEUE_ADDR			(SDAM05_BASE_ADDR + MEM_OFFSET_START + 6)
+#define PM_PON_ENQUEUE_SDAM_NUM			(SDAM05_BASE_ADDR + MEM_OFFSET_START + 7)
+#define PM_PON_LOGGING_AREA_START		(SDAM05_BASE_ADDR + MEM_OFFSET_START + 11)
+#define PM_PON_LOGGING_AREA_END			(SDAM05_BASE_ADDR + MEM_OFFSET_START + 127)
+#define PM_PON_PUSH_PTR_INDEX(x)		(x - (MEM_OFFSET_START + 11))
+
+#define PM_PON_EVENT_PON_TRIGGER		0x1
+#define PM_PON_EVENT_RESET_TYPE			0x7
+#define PM_PON_EVENT_FUNDAMENTAL_RESET		0xC
+#define PM_PON_EVENT_RESET_TRIGGER		0x6
+#define BEGIN_PON				0XD
+#define PON_EVENT_PARSE_LIMIT			2
+
+#define PON_KEYPD_PWR_N_S2_RSN			0x0080
+#define PON_RESIN_N_S2_RSN			0x0081
+#define PON_KPDPWR_AND_RESIN_RSN		0x0082
+#define PON_PMIC_WD_RSN				0x0083
+#define PON_PS_HOLD_RSN				0x0084
+#define PON_SW_RST_RSN				0x0085
+#define PON_RESIN_N_DEB_RSN			0x0086
+#define PON_KEYPD_PWR_N_RSN			0x0087
+#define PON_SMPL_RSN				0x0640
+#define PON_PON1_RSN				0x18C1
+#define PON_CBLPWR_RSN				0x18C0
+#define PON_SYS_OK_RSN				0x71C2
+#define PON_RTC_ALARM_RSN			0x0621
+
+#define PON_RAW_XVDD_RB_MASK			0x8000
+#define PON_RAW_DVDD_RB_MASK			0x4000
+#define PON_S3_RESET_MASK			0xF0
+
+#define PON_HARDRESET				0x7
+#define PON_SHUTDOWN				0x4
+#define PON_WARMRESET				0x1
+
+int pm_pon_read_pon_hist(uint8_t *pon_hist_raw);
+bool is_pon_on_ac(void);
+
+#endif  // _SOC_QUALCOMM_X1P42100_PMIC_H__
diff --git a/src/soc/qualcomm/x1p42100/pmic.c b/src/soc/qualcomm/x1p42100/pmic.c
new file mode 100644
index 0000000000..db2ff3890d
--- /dev/null
+++ b/src/soc/qualcomm/x1p42100/pmic.c
@@ -0,0 +1,175 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <console/console.h>
+#include <soc/pmic.h>
+#include <soc/qcom_spmi.h>
+#include <types.h>
+
+/*
+ * pm_pon_get_pon_event - Search for a specific event type in the PON log.
+ * @event: The event type to search for.
+ * @pon_hist_log: Pointer to the PON history log buffer.
+ * @pon_hist_raw_size: Total size of the raw log buffer.
+ * @return_data: Pointer to store the associated event data.
+ *
+ * This helper function iterates through the PON log buffer and searches for an
+ * entry matching the specified event type (e.g., PM_PON_EVENT_PON_TRIGGER).
+ * If found, it extracts the associated 16-bit data field (which usually contains
+ * the power-on reason or status) and returns it via return_data.
+ *
+ * @return 0 on success, -1 on error.
+ */
+static int pm_pon_get_pon_event(uint8_t event, uint8_t *pon_hist_log, uint32_t pon_hist_raw_size, uint16_t *return_data)
+{
+	bool event_found = false;
+	uint8_t data0;
+	uint8_t data1;
+	uint32_t i;
+
+	if (!pon_hist_log || !return_data)
+		return -1;
+
+	for (i = 0; i < pon_hist_raw_size; i += 4) {
+		if (event == *(pon_hist_log + 2)) {
+			data0 = *pon_hist_log;
+			data1 = *(pon_hist_log + 1);
+			event_found = true;
+			break;
+		}
+		pon_hist_log += 4;
+	}
+
+	if (event_found == false)
+		*return_data = 0;
+	else
+		*return_data = ((uint16_t) data1 << 8) | data0;
+
+	return 0;
+}
+
+/*
+ * pm_pon_read_pon_hist - Read, reorder, and prepare the PMIC Power-On history log.
+ * @pon_hist_raw: Buffer to store the resulting PON history log. The buffer size
+ * must be at least PON_EVENT_TOTAL_LOG_AREA_SIZE bytes.
+ *
+ * This function handles the low-level logic to read the PON event data from
+ * the PMIC's SDAM registers (which function as a circular buffer) and reorders
+ * the data in the output buffer (pon_hist_raw) so that the most recent event
+ * entry is placed at the beginning (index 0).
+ *
+ * @return 0 on success, -1 on failure (e.g., if pon_hist_raw is NULL or SPMI read fails).
+ */
+int pm_pon_read_pon_hist(uint8_t *pon_hist_raw)
+{
+	int status;
+	uint8_t sdam_count;
+	uint8_t enqueue_sdam_num;
+	uint32_t i;
+	uint32_t read_size;
+	uint32_t push_ptr;
+	uint8_t enqueue_addr;
+	uint8_t temp;
+
+	if (!pon_hist_raw)
+		return -1;
+
+	enqueue_addr = spmi_read8(SPMI_ADDR(PMIC_SLAVE_ID, PM_PON_ENQUEUE_ADDR));
+	sdam_count = spmi_read8(SPMI_ADDR(PMIC_SLAVE_ID, PM_PON_SDAM_COUNT_ADDR));
+	enqueue_sdam_num = spmi_read8(SPMI_ADDR(PMIC_SLAVE_ID, PM_PON_ENQUEUE_SDAM_NUM));
+
+	/* if sdam_count == 1, each SDAM contains half of the total size
+	 * otherwise, the SDAM stores the whole size
+	 */
+	status = spmi_read_bytes(SPMI_ADDR(PMIC_SLAVE_ID, PM_PON_LOGGING_AREA_START), pon_hist_raw, PON_EVENT_LOG_AREA_SIZE);
+
+	if (sdam_count != 0) {
+		/* 0: Only used 1 SDAM
+		 * 1: Used 2 SDAM
+		 * Currently only extend to 2 continuous SDAM.
+		 */
+		status |= spmi_read_bytes(SPMI_ADDR(PMIC_SLAVE_ID, (PM_PON_LOGGING_AREA_START + 0x100)), pon_hist_raw + PON_EVENT_LOG_AREA_SIZE, PON_EVENT_LOG_AREA_SIZE);
+	}
+
+	push_ptr = enqueue_addr;
+	push_ptr = PM_PON_PUSH_PTR_INDEX(push_ptr) + (enqueue_sdam_num * PON_EVENT_LOG_AREA_SIZE);
+
+	if (status != 0 || push_ptr >= PON_EVENT_TOTAL_LOG_AREA_SIZE)
+		return -1;
+
+	read_size = push_ptr/2;
+
+	/* Reverse the Buffer to start from latest event */
+	for (i = 0; i < read_size; i++) {
+		temp = pon_hist_raw[push_ptr - i - 1];
+		pon_hist_raw[push_ptr - i - 1] = pon_hist_raw[i];
+		pon_hist_raw[i] = temp;
+	}
+
+	read_size = (PON_EVENT_TOTAL_LOG_AREA_SIZE - push_ptr) / 2;
+
+	for (i = 0; i < read_size; i++) {
+		temp = pon_hist_raw[PON_EVENT_TOTAL_LOG_AREA_SIZE - i - 1];
+		if (push_ptr + i < PON_EVENT_TOTAL_LOG_AREA_SIZE) {
+			pon_hist_raw[PON_EVENT_TOTAL_LOG_AREA_SIZE - i - 1] =  pon_hist_raw[push_ptr + i];
+			pon_hist_raw[push_ptr + i] = temp;
+		}
+	}
+
+	return status;
+}
+
+/*
+ * is_pon_on_ac - Checks if the system was powered on by an AC/cable insertion event.
+ *
+ * This function reads and parses the PMIC Power-On (PON) history log to determine
+ * the specific cause of the system power-up. It specifically looks for the
+ * PON_CBLPWR_RSN trigger, which indicates that external power (AC/charging cable)
+ * was the reason for the boot sequence initiation.
+ *
+ * @return true if AC/Cable Power was the PON reason, false otherwise.
+ */
+bool is_pon_on_ac(void)
+{
+	uint16_t data, data2;
+	uint32_t i;
+	int8_t current_index = -1;
+	uint8_t *pon_hist_curr_addr;
+	uint8_t pon_hist_raw[PON_EVENT_TOTAL_LOG_AREA_SIZE] = {0};
+
+	printk(BIOS_INFO, "PON: Show power on reason -\n");
+	if (pm_pon_read_pon_hist(pon_hist_raw))
+		return false;
+
+	pon_hist_curr_addr = pon_hist_raw;
+
+	for (i = 0; i < PON_EVENT_LOG_AREA_SIZE - 2; i += 4) {
+		if (current_index >= PON_EVENT_PARSE_LIMIT) {
+			pon_hist_curr_addr += 4;
+			continue;
+		}
+		data = ((uint16_t)(*(pon_hist_curr_addr + 1)) << 8) | *pon_hist_curr_addr;
+
+		if (BEGIN_PON  == *(pon_hist_curr_addr + 2)) {
+			pm_pon_get_pon_event(BEGIN_PON, pon_hist_curr_addr, (PON_EVENT_LOG_AREA_SIZE - 2) - (uint8_t)(pon_hist_curr_addr - pon_hist_raw), &data2);
+			current_index += 1;
+		} else if (PM_PON_EVENT_PON_TRIGGER == *(pon_hist_curr_addr + 2)) {
+			switch (data) { /* SID<<12|PID<<4|IRQ */
+			case PON_CBLPWR_RSN:
+				printk(BIOS_INFO, " PON Reason : cblpwr\n");
+				return true;
+			default:
+				printk(BIOS_INFO, " PON Reason : %d\n", data);
+				return false;
+			}
+		} else if (PM_PON_EVENT_RESET_TYPE == *(pon_hist_curr_addr + 2)) {
+			printk(BIOS_INFO, " Reset Reason : %d\n", data & 0xFF);
+			return false;
+		} else if (PM_PON_EVENT_FUNDAMENTAL_RESET == *(pon_hist_curr_addr + 2)) {
+			printk(BIOS_INFO, " POFF Reason : %d\n", data & PON_RAW_XVDD_RB_MASK);
+			return false;
+		}
+		pon_hist_curr_addr += 4;
+	}
+	printk(BIOS_INFO, " Unable to detect PON reason.\n");
+	return false;
+}

From d6132c4c03a51a650fd8afaf0d734305b0191418 Mon Sep 17 00:00:00 2001
From: Kapil Porwal <kapilporwal@google.com>
Date: Tue, 9 Sep 2025 22:16:16 +0530
Subject: [PATCH 2583/3886] mb/google/bluey: Use SOC PMIC API to detect
 off-mode charging event

Refactor the is_off_mode() detection API on the Bluey mainboard
to call the newly introduced SOC-specific PMIC function,
is_pon_on_ac().

This change delegates the complex Power-On (PON) log parsing and
PMIC register checking to the SOC layer, simplifying the mainboard
code base. The board layer now contains only the high-level policy
wrapper for detecting cable-power-on events.

This improves modularity and ensures the board code relies on the
correct hardware abstraction.

Key changes:
- Implement is_off_mode() as a simple wrapper around is_pon_on_ac()
  (from the SOC PMIC library).
- Include soc/pmic.h to access the SOC's PMIC APIs.
- Expose is_off_mode() in board.h.

BUG=b:439819922
TEST=Verify boot mode on Google/Quenbi.

Change-Id: Ibc13c3ad96846cf5b3fb9bcf461e3f338ac9b8bd
Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89122
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
---
 src/mainboard/google/bluey/board.h    |  1 +
 src/mainboard/google/bluey/charging.c | 18 ++++++++++++++++++
 2 files changed, 19 insertions(+)

diff --git a/src/mainboard/google/bluey/board.h b/src/mainboard/google/bluey/board.h
index 4a84e6333d..af2715b898 100644
--- a/src/mainboard/google/bluey/board.h
+++ b/src/mainboard/google/bluey/board.h
@@ -41,6 +41,7 @@
 #endif
 
 void setup_chromeos_gpios(void);
+bool is_off_mode(void);
 void enable_slow_battery_charging(void);
 void disable_slow_battery_charging(void);
 
diff --git a/src/mainboard/google/bluey/charging.c b/src/mainboard/google/bluey/charging.c
index 2c1e447585..56deedcdb9 100644
--- a/src/mainboard/google/bluey/charging.c
+++ b/src/mainboard/google/bluey/charging.c
@@ -1,7 +1,9 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
 #include "board.h"
+#include <soc/pmic.h>
 #include <soc/qcom_spmi.h>
+#include <types.h>
 
 #define SMB1_SLAVE_ID 0x07
 #define SMB2_SLAVE_ID 0x0A
@@ -41,3 +43,19 @@ void disable_slow_battery_charging(void)
 	spmi_write8(SMB1_CHGR_CHRG_EN_CMD, CHRG_DISABLE);
 	spmi_write8(SMB2_CHGR_CHRG_EN_CMD, CHRG_DISABLE);
 }
+
+/*
+ * is_off_mode - Check if the system is booting due to an off-mode power event.
+ *
+ * This function provides the board-level policy wrapper for detecting if the
+ * system power-on was triggered by an external charging event (e.g., cable
+ * insertion). This is typically used to enter LB_BOOT_MODE_OFFMODE_CHARGING.
+ *
+ * @return true if the system was triggered by a specific off-mode reason
+ * (e.g., charging cable insertion).
+ * @return false otherwise.
+ */
+bool is_off_mode(void)
+{
+	return is_pon_on_ac();
+}

From 27fcb8617dc1f1dedb9711b5fa1c01045f3e566a Mon Sep 17 00:00:00 2001
From: Kapil Porwal <kapilporwal@google.com>
Date: Mon, 24 Nov 2025 13:15:36 +0530
Subject: [PATCH 2584/3886] commonlib: Add CBMEM ID to store boot mode

Introduce a new CBMEM ID, CBMEM_ID_BOOT_MODE (0x444D5442, "BTMD"),
to provide a dedicated storage location for the system's detected
boot mode (e.g., normal boot, low-battery, off-mode boot etc).

Storing the boot mode in CBMEM ensures that the initial detection
performed early in the boot process (e.g., in romstage by reading
PMIC logs) is securely passed to subsequent stages like ramstage,
where different boot modes require distinct logic paths.

Key changes:
- Define CBMEM_ID_BOOT_MODE in cbmem_id.h.
- Add "BOOT MODE" entry to the CBMEM_ID_TO_NAME_TABLE.

BUG=b:439819922
TEST=Verify boot mode stored in CBMEM.

Change-Id: I7ebf29385a99ac1be491bfefe1c74c8c9e58b55d
Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90175
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/commonlib/bsd/include/commonlib/bsd/cbmem_id.h | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/src/commonlib/bsd/include/commonlib/bsd/cbmem_id.h b/src/commonlib/bsd/include/commonlib/bsd/cbmem_id.h
index 4cf1f09a84..20a1099f0a 100644
--- a/src/commonlib/bsd/include/commonlib/bsd/cbmem_id.h
+++ b/src/commonlib/bsd/include/commonlib/bsd/cbmem_id.h
@@ -91,6 +91,7 @@
 #define CBMEM_ID_CSE_BP_INFO	0x42455343
 #define CBMEM_ID_AMD_OPENSIL	0x4153494C
 #define CBMEM_ID_PVMFW		0x666d7670
+#define CBMEM_ID_BOOT_MODE	0x444D5442
 
 #define CBMEM_ID_TO_NAME_TABLE				 \
 	{ CBMEM_ID_ACPI,		"ACPI       " }, \
@@ -174,5 +175,6 @@
 	{ CBMEM_ID_CSE_INFO,		"CSE SPECIFIC INFO"},\
 	{ CBMEM_ID_CSE_BP_INFO,		"CSE BP INFO"}, \
 	{ CBMEM_ID_AMD_OPENSIL,		"OPENSIL DATA"}, \
-	{ CBMEM_ID_PVMFW,		"PVMFW      "}
+	{ CBMEM_ID_PVMFW,		"PVMFW      "}, \
+	{ CBMEM_ID_BOOT_MODE,		"BOOT MODE  "}
 #endif /* _CBMEM_ID_H_ */

From 567186a0003b37d956045b3da3c19f292d7c9d4c Mon Sep 17 00:00:00 2001
From: Kapil Porwal <kapilporwal@google.com>
Date: Mon, 24 Nov 2025 13:18:05 +0530
Subject: [PATCH 2585/3886] mb/google/bluey: Add support for off-mode charging

Implement full support for the LB_BOOT_MODE_OFFMODE_CHARGING
state. This mode is detected when the system powers on due to an
external charging event (cable insertion) while the system was
previously fully powered off.

This boot mode is critical for systems that need to maintain a light
footprint to quickly start charging without performing a full boot.
It combines with the existing low-battery mode to define a unified
"low power boot" state.

In romstage, the boot mode is detected using is_off_mode() and
the EC's low battery status, and the result is saved to CBMEM. In
ramstage, this mode is read to determine if heavy, resource-intensive
initializations should be skipped to conserve time and power.

Key changes:
- In romstage.c, implement set_boot_mode() to determine the
  mode (NORMAL, OFFMODE_CHARGING, or LOW_BATTERY) and save it to
  CBMEM_ID_BOOT_MODE.
- In mainboard.c, introduce get_boot_mode() and
  is_low_power_boot() to retrieve and check the CBMEM value.
- Skip heavy ramstage initializations (mainboard_init and
  mainboard_needs_pcie_init) when in a low-power boot mode.
- Update lb_add_boot_mode to report the mode stored in CBMEM
  to the coreboot table.

BUG=b:439819922
TEST=Verify off-mode charging behavior on Google/Quenbi.

Change-Id: I57d25deb6b2b1f9ff199cea5ca2953f10ffb4746
Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90176
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/google/bluey/mainboard.c | 51 ++++++++++++++------------
 src/mainboard/google/bluey/romstage.c  | 29 +++++++++++++++
 2 files changed, 56 insertions(+), 24 deletions(-)

diff --git a/src/mainboard/google/bluey/mainboard.c b/src/mainboard/google/bluey/mainboard.c
index c20d98bbf5..07b50352c6 100644
--- a/src/mainboard/google/bluey/mainboard.c
+++ b/src/mainboard/google/bluey/mainboard.c
@@ -2,6 +2,9 @@
 
 #include <boot/coreboot_tables.h>
 #include <bootmode.h>
+#include <cbmem.h>
+#include <commonlib/bsd/cbmem_id.h>
+#include <commonlib/coreboot_tables.h>
 #include <console/console.h>
 #include <device/device.h>
 #include <ec/google/chromeec/ec.h>
@@ -13,27 +16,30 @@
 #include <soc/usb/usb.h>
 
 /*
- * Check if the system is in low battery boot mode.
- *
- * This function calls the underlying EC function only once during the
+ * This function calls the underlying PMIC/EC function only once during the
  * first execution and caches the result for all subsequent calls.
- *
- * Return `true` if system battery is below critical threshold, `false` otherwise.
  */
-static inline bool is_low_battery_mode(void)
+static enum boot_mode_t get_boot_mode(void)
 {
-	if (!CONFIG(EC_GOOGLE_CHROMEEC))
-		return false;
-
-	static bool low_battery_mode_cached = false;
-	static bool cached_low_battery_result = false;
-
-	if (!low_battery_mode_cached) {
-		cached_low_battery_result = google_chromeec_is_below_critical_threshold();
-		low_battery_mode_cached = true;
+	static bool initialized = false;
+	static enum boot_mode_t boot_mode = LB_BOOT_MODE_NORMAL;
+	if (!initialized) {
+		enum boot_mode_t *boot_mode_ptr = cbmem_find(CBMEM_ID_BOOT_MODE);
+		if (boot_mode_ptr)
+			boot_mode = *boot_mode_ptr;
+		printk(BIOS_INFO, "Boot mode is %d\n", boot_mode);
+		initialized = true;
 	}
+	return boot_mode;
+}
 
-	return cached_low_battery_result;
+static bool is_low_power_boot(void)
+{
+	enum boot_mode_t boot_mode = get_boot_mode();
+	if ((boot_mode == LB_BOOT_MODE_LOW_BATTERY) ||
+	    (boot_mode == LB_BOOT_MODE_OFFMODE_CHARGING))
+		return true;
+	return false;
 }
 
 static void setup_usb(void)
@@ -51,20 +57,17 @@ void lb_add_boot_mode(struct lb_header *header)
 
 	mode->tag = LB_TAG_BOOT_MODE;
 	mode->size = sizeof(*mode);
-	mode->boot_mode = LB_BOOT_MODE_NORMAL;
+	mode->boot_mode = get_boot_mode();
 
-	if (is_low_battery_mode())
-		mode->boot_mode = LB_BOOT_MODE_LOW_BATTERY;
-
-	/* Enable charging only during low-battery mode */
-	if (mode->boot_mode == LB_BOOT_MODE_LOW_BATTERY)
+	/* Enable charging only during off-mode or low-battery mode */
+	if (is_low_power_boot())
 		enable_slow_battery_charging();
 }
 
 bool mainboard_needs_pcie_init(void)
 {
 	/* Skip PCIe initialization if boot mode is "low-battery" or "off-mode charging"*/
-	if (is_low_battery_mode())
+	if (is_low_power_boot())
 		return false;
 
 	return true;
@@ -83,7 +86,7 @@ static void display_startup(void)
 static void mainboard_init(struct device *dev)
 {
 	/* Skip mainboard initialization if boot mode is "low-battery" or "off-mode charging"*/
-	if (is_low_battery_mode())
+	if (is_low_power_boot())
 		return;
 
 	gpi_firmware_load(QUP_0_GSI_BASE);
diff --git a/src/mainboard/google/bluey/romstage.c b/src/mainboard/google/bluey/romstage.c
index b76dfba1f2..c2cbf5b7c4 100644
--- a/src/mainboard/google/bluey/romstage.c
+++ b/src/mainboard/google/bluey/romstage.c
@@ -2,12 +2,29 @@
 
 #include <arch/stages.h>
 #include "board.h"
+#include <cbmem.h>
+#include <commonlib/bsd/cbmem_id.h>
+#include <commonlib/coreboot_tables.h>
+#include <ec/google/chromeec/ec.h>
 #include <gpio.h>
 #include <soc/aop_common.h>
 #include <soc/qclib_common.h>
 #include <soc/shrm.h>
 #include <soc/watchdog.h>
 
+static enum boot_mode_t boot_mode = LB_BOOT_MODE_NORMAL;
+
+static void set_boot_mode(void)
+{
+	if (!CONFIG(EC_GOOGLE_CHROMEEC))
+		return;
+
+	if (is_off_mode())
+		boot_mode = LB_BOOT_MODE_OFFMODE_CHARGING;
+	else if (google_chromeec_is_below_critical_threshold())
+		boot_mode = LB_BOOT_MODE_LOW_BATTERY;
+}
+
 void platform_romstage_main(void)
 {
 	/* Watchdog must be checked first to avoid erasing watchdog info later. */
@@ -18,6 +35,9 @@ void platform_romstage_main(void)
 	/* QCLib: DDR init & train */
 	qclib_load_and_run();
 
+	/* Underlying PMIC registers are accessible only at this point */
+	set_boot_mode();
+
 	aop_fw_load_reset();
 
 	qclib_rerun();
@@ -31,3 +51,12 @@ void platform_romstage_main(void)
 	if (CONFIG(MAINBOARD_HAS_FINGERPRINT_VIA_SPI))
 		gpio_output(GPIO_EN_FP_RAILS, 1);
 }
+
+void platform_romstage_postram(void)
+{
+	enum boot_mode_t *boot_mode_ptr = cbmem_add(CBMEM_ID_BOOT_MODE, sizeof(*boot_mode_ptr));
+	if (boot_mode_ptr) {
+		*boot_mode_ptr = boot_mode;
+		printk(BIOS_INFO, "Boot mode is %d\n", *boot_mode_ptr);
+	}
+}

From 14e96b4ef1f76926a3d9c1c4821266f3f81e6c14 Mon Sep 17 00:00:00 2001
From: Terry Cheong <htcheong@chromium.org>
Date: Tue, 25 Nov 2025 16:29:56 +0800
Subject: [PATCH 2586/3886] mb/google/brox/caboc: Mute speaker amp to prevent
 pop noise on reboot

A pop noise is heard from the speakers on caboc devices when rebooting
while audio is playing.

This is caused by the speaker amplifier (class-D) being active during
the reboot process.

This change mutes the amplifier by updating the HDA verb table, which
is configured at boot time. The amplifier will be unmuted when
generating a dev beep to preserve that functionality.

BUG=b:439638686
TEST=Play audio in the OS and reboot the device. Verify that no pop
noise is heard from the speakers.

Change-Id: Ic9980d31097d60ede879c8d6dcdd541580765795
Signed-off-by: Terry Cheong <htcheong@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90199
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 .../google/brox/variants/caboc/include/variant/hda_verb.h       | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/mainboard/google/brox/variants/caboc/include/variant/hda_verb.h b/src/mainboard/google/brox/variants/caboc/include/variant/hda_verb.h
index e6b4d057bf..3edbe5e39e 100644
--- a/src/mainboard/google/brox/variants/caboc/include/variant/hda_verb.h
+++ b/src/mainboard/google/brox/variants/caboc/include/variant/hda_verb.h
@@ -128,7 +128,7 @@ const u32 pc_beep_verbs[] = {
 	0x02050010,
 	0x02040320,
 	/* Dos beep path - 2 */
-	0x0143B000,
+	0x0143B080,
 	0x01470740,
 	0x01470C02,
 	0x01470C02,

From 01540f036ed4245671ddfcadf79c12f78675d6ef Mon Sep 17 00:00:00 2001
From: Luca Lai <luca.lai@lcfc.corp-partner.google.com>
Date: Wed, 19 Nov 2025 21:05:41 +0800
Subject: [PATCH 2587/3886] mb/google/fatcat/var/ruby: Use spd-11 for
 MT62F1G32D2DS-020 WT:D and K3KL8L80EM-MGCV

Because there are some attributes of MT62F1G32D2DS-020 WT:D and
K3KL8L80EM-MGCV when review the specification again,
so modify the memory_parts.json attributes and re-generate SPD id
for MT62F1G32D2DS-020 WT:D and K3KL8L80EM-MGCV.

BUG=b:446771934
TEST=Use part_id_gen to generate related settings

Change-Id: Ic38286f38c4c6572cf2e22c78f5f202cc0a152cc
Signed-off-by: Luca Lai <luca.lai@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90124
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
---
 src/mainboard/google/fatcat/variants/ruby/memory/Makefile.mk  | 4 +---
 .../google/fatcat/variants/ruby/memory/dram_id.generated.txt  | 4 ++--
 2 files changed, 3 insertions(+), 5 deletions(-)

diff --git a/src/mainboard/google/fatcat/variants/ruby/memory/Makefile.mk b/src/mainboard/google/fatcat/variants/ruby/memory/Makefile.mk
index 5bf822a1fa..cc8e0af2ea 100644
--- a/src/mainboard/google/fatcat/variants/ruby/memory/Makefile.mk
+++ b/src/mainboard/google/fatcat/variants/ruby/memory/Makefile.mk
@@ -4,6 +4,4 @@
 # ./util/spd_tools/bin/part_id_gen ADL lp5 src/mainboard/google/fatcat/variants/ruby/memory/ src/mainboard/google/fatcat/variants/ruby/memory/mem_parts_used.txt
 
 SPD_SOURCES =
-SPD_SOURCES += spd/lp5/set-0/spd-11.hex      # ID = 0(0b0000)  Parts = H58G56CK8BX146
-SPD_SOURCES += spd/lp5/set-0/spd-14.hex      # ID = 1(0b0001)  Parts = MT62F1G32D2DS-020 WT:D
-SPD_SOURCES += spd/lp5/set-0/spd-10.hex      # ID = 2(0b0010)  Parts = K3KL8L80EM-MGCV
+SPD_SOURCES += spd/lp5/set-0/spd-11.hex      # ID = 0(0b0000)  Parts = H58G56CK8BX146, MT62F1G32D2DS-020 WT:D, K3KL8L80EM-MGCV
diff --git a/src/mainboard/google/fatcat/variants/ruby/memory/dram_id.generated.txt b/src/mainboard/google/fatcat/variants/ruby/memory/dram_id.generated.txt
index d37b6715e1..de8e5b3344 100644
--- a/src/mainboard/google/fatcat/variants/ruby/memory/dram_id.generated.txt
+++ b/src/mainboard/google/fatcat/variants/ruby/memory/dram_id.generated.txt
@@ -5,5 +5,5 @@
 
 DRAM Part Name                 ID to assign
 H58G56CK8BX146                 0 (0000)
-MT62F1G32D2DS-020 WT:D         1 (0001)
-K3KL8L80EM-MGCV                2 (0010)
+MT62F1G32D2DS-020 WT:D         0 (0000)
+K3KL8L80EM-MGCV                0 (0000)

From 12e763eece263f7251a5d409e282777653156602 Mon Sep 17 00:00:00 2001
From: Erik van den Bogaert <ebogaert@eltan.com>
Date: Mon, 24 Nov 2025 13:38:19 +0100
Subject: [PATCH 2588/3886] device/pci_ids: Add DIDs for TGL-H (GT1 and RM590E)
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

This commit adds the relevant DIDs to support Tiger Lake H (TGL-H) systems based on the Xeon W-11865MRE (GPU) and RM590E chipset (PCH).

TEST=A platform with Xeon W-11865MRE and RM590E booted
     the relevant information printed in coreboot log.
     [DEBUG]  CPU: ID 806d1, Tigerlake R0, ucode: 00000056
     [DEBUG]  MCH: device id 9a36 (rev 05) is Tigerlake-H-8-1
     [DEBUG]  PCH: device id 4390 (rev 11) is Tigerlake-H RM590E
     [DEBUG]  IGD: device id 9a70 (rev 01) is Tigerlake H GT1 32EU

Change-Id: I2bff2551b9f194e169c0edd080e9c869bcc9c60f
Signed-off-by: Erik van den Bogaert <ebogaert@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90179
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
---
 src/include/device/pci_ids.h                        | 2 ++
 src/soc/intel/tigerlake/bootblock/report_platform.c | 2 ++
 2 files changed, 4 insertions(+)

diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h
index 2c3723afa6..a3c3e58056 100644
--- a/src/include/device/pci_ids.h
+++ b/src/include/device/pci_ids.h
@@ -3029,6 +3029,7 @@
 #define PCI_DID_INTEL_TGP_H_ESPI_HM570		0x438B
 #define PCI_DID_INTEL_TGP_H_ESPI_QM580		0x438A
 #define PCI_DID_INTEL_TGP_H_ESPI_WM590		0x4389
+#define PCI_DID_INTEL_TGP_H_ESPI_RM590E		0x4390
 #define PCI_DID_INTEL_MCC_ESPI_0			0x4b00
 #define PCI_DID_INTEL_MCC_ESPI_1			0x4b04
 #define PCI_DID_INTEL_MCC_BASE_ESPI			0x4b03
@@ -4434,6 +4435,7 @@
 #define PCI_DID_INTEL_TGL_GT0				0x9A7F
 #define PCI_DID_INTEL_TGL_GT1_H_32				0x9A60
 #define PCI_DID_INTEL_TGL_GT1_H_16				0x9A68
+#define PCI_DID_INTEL_TGL_GT1_H_32_1			0x9A70
 #define PCI_DID_INTEL_TGL_GT2_ULT			0x9A49
 #define PCI_DID_INTEL_TGL_GT3_ULT			0x9A52
 #define PCI_DID_INTEL_TGL_GT2_ULX			0x9A40
diff --git a/src/soc/intel/tigerlake/bootblock/report_platform.c b/src/soc/intel/tigerlake/bootblock/report_platform.c
index 8f90b3c6a3..9667f1b13b 100644
--- a/src/soc/intel/tigerlake/bootblock/report_platform.c
+++ b/src/soc/intel/tigerlake/bootblock/report_platform.c
@@ -86,6 +86,7 @@ static struct {
 	{ PCI_DID_INTEL_TGP_H_ESPI_HM570, "Tigerlake-H HM570" },
 	{ PCI_DID_INTEL_TGP_H_ESPI_QM580, "Tigerlake-H QM580" },
 	{ PCI_DID_INTEL_TGP_H_ESPI_WM590, "Tigerlake-H WM590" },
+	{ PCI_DID_INTEL_TGP_H_ESPI_RM590E, "Tigerlake-H RM590E" },
 };
 
 static struct {
@@ -93,6 +94,7 @@ static struct {
 	const char *name;
 } igd_table[] = {
 	{ PCI_DID_INTEL_TGL_GT0, "Tigerlake U GT0" },
+	{ PCI_DID_INTEL_TGL_GT1_H_32_1, "Tigerlake H GT1 32EU" },
 	{ PCI_DID_INTEL_TGL_GT1_H_32, "Tigerlake H GT1 32EU" },
 	{ PCI_DID_INTEL_TGL_GT1_H_16, "Tigerlake H GT1 16EU" },
 	{ PCI_DID_INTEL_TGL_GT2_ULT, "Tigerlake U GT2" },

From 3dabe4f857aa2a1cc1dc199ea75ca14d4d45ea31 Mon Sep 17 00:00:00 2001
From: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Date: Wed, 19 Nov 2025 16:15:58 +0800
Subject: [PATCH 2589/3886] mb/google/brox/var/caboc: Increase I2C0 touchpad
 tHD to 0.53 us

Increase I2C0 touchpad tHD to 0.53 us by adjusting data_hold_time_ns in
I2C0 from 50 to 250, the new tHD meets SPEC between 0.3 us and 0.9 us.

The setting format is copied from baseboard/brox and modify I2C0.

BUG=b:461977573
TEST=emerge-brox coreboot
     checked TP function work
     measure the wave form meets SPEC
     Before: tHD  ~0.072 us
     After:  tHD  ~0.53 us

Change-Id: I2841107a9165fc0eacc465fe5013d23856a3f755
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90114
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com>
---
 .../brox/variants/caboc/overridetree.cb       | 39 +++++++++++++++++++
 1 file changed, 39 insertions(+)

diff --git a/src/mainboard/google/brox/variants/caboc/overridetree.cb b/src/mainboard/google/brox/variants/caboc/overridetree.cb
index 575b865205..6cf5defcdc 100644
--- a/src/mainboard/google/brox/variants/caboc/overridetree.cb
+++ b/src/mainboard/google/brox/variants/caboc/overridetree.cb
@@ -45,6 +45,45 @@ chip soc/intel/alderlake
 
 	register "platform_pmax" = "208"
 
+	# Intel Common SoC Config
+	#+-------------------+---------------------------+
+	#| Field             |  Value                    |
+	#+-------------------+---------------------------+
+	#| I2C0              | Trackpad                  |
+	#| I2C1              | Touchscreen               |
+	#| I2C2              | ISH Sensor                |
+	#| I2C4              | cr50 TPM. Early init is   |
+	#|                   | required to set up a BAR  |
+	#|                   | for TPM communication     |
+	#+-------------------+---------------------------+
+	register "common_soc_config" = "{
+		.i2c[0] = {
+			.speed = I2C_SPEED_FAST,
+			.rise_time_ns = 650,
+			.fall_time_ns = 330,
+			.data_hold_time_ns = 250,
+		},
+		.i2c[1] = {
+			.speed = I2C_SPEED_FAST,
+			.rise_time_ns = 600,
+			.fall_time_ns = 350,
+			.data_hold_time_ns = 50,
+		},
+		.i2c[2] = {
+			.speed = I2C_SPEED_FAST,
+			.rise_time_ns = 600,
+			.fall_time_ns = 400,
+			.data_hold_time_ns = 50,
+		},
+		.i2c[4] = {
+			.early_init = 1,
+			.speed = I2C_SPEED_FAST,
+			.rise_time_ns = 650,
+			.fall_time_ns = 400,
+			.data_hold_time_ns = 50,
+		},
+	}"
+
 	device domain 0 on
 		device ref dtt on
 			chip drivers/intel/dptf

From 67bf203e52ed7eebedc4d48fa6f7b07f87ad6bfd Mon Sep 17 00:00:00 2001
From: Joyce Ciou <joyce_ciou@pegatron.corp-partner.google.com>
Date: Mon, 24 Nov 2025 11:00:34 +0800
Subject: [PATCH 2590/3886] mb/google/nissa/var/guren: Add missing settings for
 WWAN

Due to "firmware.PDProtocol" item of FAFT PD test result has failed
and the HDMI function can't work on USB type C of the daughter board
side when the DUT with 1C+5G of daughter board config.
Add missing settings for WWAN to pass the test.

BUG=b:463200834
TEST=emerge-nissa coreboot chromeos-bootimage
     Check 5G LTE module detectable by command # mmcli -m a.
     Confirm firmware.PDProtocol PASS.

Change-Id: I8657e383ed376c4a3af328f7593d5503babe2e3d
Signed-off-by: Joyce Ciou <joyce_ciou@pegatron.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90170
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/google/brya/variants/guren/overridetree.cb | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/src/mainboard/google/brya/variants/guren/overridetree.cb b/src/mainboard/google/brya/variants/guren/overridetree.cb
index 6c7ecd83e7..f18fc8837c 100644
--- a/src/mainboard/google/brya/variants/guren/overridetree.cb
+++ b/src/mainboard/google/brya/variants/guren/overridetree.cb
@@ -647,6 +647,7 @@ chip soc/intel/alderlake
 							probe DB_USB DB_1A
 							probe DB_USB DB_1C_1A
 							probe DB_USB DB_1C_LTE
+							probe DB_USB DB_1C_5G
 						end
 					end
 				end
@@ -671,6 +672,7 @@ chip soc/intel/alderlake
 							probe DB_USB DB_1C
 							probe DB_USB DB_1C_1A
 							probe DB_USB DB_1C_LTE
+							probe DB_USB DB_1C_5G
 						end
 					end
 				end
@@ -695,6 +697,7 @@ chip soc/intel/alderlake
 							probe DB_USB DB_1C
 							probe DB_USB DB_1C_1A
 							probe DB_USB DB_1C_LTE
+							probe DB_USB DB_1C_5G
 						end
 					end
 					chip drivers/usb/acpi

From e8599956dc87e72e7c318b789defead594061abf Mon Sep 17 00:00:00 2001
From: Maximilian Brune <maximilian.brune@9elements.com>
Date: Tue, 25 Nov 2025 20:45:44 +0100
Subject: [PATCH 2591/3886] mb/amd/crater: Make NVMe reset GPIO configurable

If you reworked the board its possible NVME reset is attached to GPIO 40
instead of 24.

Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: Ib2a10701ed2c3e677419f700a69277c2cde588f5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90206
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
---
 src/mainboard/amd/crater/Kconfig                   | 6 ++++++
 src/mainboard/amd/crater/early_gpio.c              | 4 ++++
 src/mainboard/amd/crater/gpio.c                    | 4 ++++
 src/mainboard/amd/crater/port_descriptors_renoir.c | 2 ++
 4 files changed, 16 insertions(+)

diff --git a/src/mainboard/amd/crater/Kconfig b/src/mainboard/amd/crater/Kconfig
index 729e1d6fd8..e8feffc94c 100644
--- a/src/mainboard/amd/crater/Kconfig
+++ b/src/mainboard/amd/crater/Kconfig
@@ -98,6 +98,12 @@ config ENABLE_M2_SSD
 	help
 	  Use GPP[8:11] connected to M.2 SSD
 
+config NVME_RST_GPIO40
+	bool "NVMe Reset on GPIO40"
+	help
+	  Select if the NVMe reset pin is connected to GPIO40.
+	  Otherwise its assumed to be connected to GPIO24.
+
 choice
 	prompt "XGBE/WWAN/WLAN/DT Selection"
 	default XGBE_WWAN_WLAN
diff --git a/src/mainboard/amd/crater/early_gpio.c b/src/mainboard/amd/crater/early_gpio.c
index 28ca462a39..de490b3ee1 100644
--- a/src/mainboard/amd/crater/early_gpio.c
+++ b/src/mainboard/amd/crater/early_gpio.c
@@ -26,7 +26,11 @@ static const struct soc_amd_gpio gpio_set_stage_reset[] = {
 	/* PCIE_RST1_L */
 	PAD_NFO(GPIO_27, PCIE_RST1_L, HIGH),
 	/* M2_SSD0_RST */
+#if CONFIG(NVME_RST_GPIO40)
+	PAD_GPO(GPIO_40, HIGH),
+#else
 	PAD_GPO(GPIO_24, HIGH),
+#endif
 	/* DEVSLP1 */
 	PAD_NFO(GPIO_6, DEVSLP1, LOW),
 
diff --git a/src/mainboard/amd/crater/gpio.c b/src/mainboard/amd/crater/gpio.c
index 27b045c245..b1da83e8db 100644
--- a/src/mainboard/amd/crater/gpio.c
+++ b/src/mainboard/amd/crater/gpio.c
@@ -28,7 +28,11 @@ static const struct soc_amd_gpio gpio_set_stage_ram[] = {
 	/* PCIE_RST1_L */
 	PAD_NFO(GPIO_27, PCIE_RST1_L, HIGH),
 	/* M2_SSD0_RST */
+#if CONFIG(NVME_RST_GPIO40)
+	PAD_GPO(GPIO_40, HIGH),
+#else
 	PAD_GPO(GPIO_24, HIGH),
+#endif
 	/* DEVSLP1 */
 	PAD_NFO(GPIO_6, DEVSLP1, LOW),
 
diff --git a/src/mainboard/amd/crater/port_descriptors_renoir.c b/src/mainboard/amd/crater/port_descriptors_renoir.c
index 5ac965f84a..83e861d0ab 100644
--- a/src/mainboard/amd/crater/port_descriptors_renoir.c
+++ b/src/mainboard/amd/crater/port_descriptors_renoir.c
@@ -341,4 +341,6 @@ static void xgbe_init(FSP_M_CONFIG *mcfg)
 void mb_pre_fspm(FSP_M_CONFIG *mcfg)
 {
 	xgbe_init(mcfg);
+
+	mcfg->nvme_rst_gpio = CONFIG(NVME_RST_GPIO40) ? 40 : 24;
 }

From 0ed1529ce3739c61609d4682a2c126a4cad32289 Mon Sep 17 00:00:00 2001
From: Felix Held <felix-coreboot@felixheld.de>
Date: Tue, 11 Mar 2025 21:59:22 +0100
Subject: [PATCH 2592/3886] src/vc/amd/fsp: fix type 17 DMI info

The TYPE17_DMI_INFO struct in renoir FSP has the SMBIOS 3.2 layout, not
the SMBIOS 3.3 layout. The struct definition in the coreboot code needs
to match the one that the FSP uses when creating the DMI into HOB.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: Icd45d4e25dcc4a5977deaeba2b178e0b9dd1e453
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90207
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
---
 src/vendorcode/amd/fsp/cezanne/soc_dmi_info.h   | 3 ++-
 src/vendorcode/amd/fsp/common/dmi_info.h        | 4 +++-
 src/vendorcode/amd/fsp/glinda/soc_dmi_info.h    | 3 ++-
 src/vendorcode/amd/fsp/mendocino/soc_dmi_info.h | 3 ++-
 src/vendorcode/amd/fsp/phoenix/soc_dmi_info.h   | 3 ++-
 src/vendorcode/amd/fsp/renoir/soc_dmi_info.h    | 2 +-
 6 files changed, 12 insertions(+), 6 deletions(-)

diff --git a/src/vendorcode/amd/fsp/cezanne/soc_dmi_info.h b/src/vendorcode/amd/fsp/cezanne/soc_dmi_info.h
index 76f165d061..47500defa3 100644
--- a/src/vendorcode/amd/fsp/cezanne/soc_dmi_info.h
+++ b/src/vendorcode/amd/fsp/cezanne/soc_dmi_info.h
@@ -12,6 +12,7 @@
 #define AGESA_STRUCT_DIMMS_PER_CHANNEL    4   ///< DIMMs per channel in AGESA FSP DMI T17 table
 #define AGESA_STRUCT_PART_NUMBER_SIZE     21
 
-#define SMBIOS_3_2_3_3_SUPPORT            1
+#define SMBIOS_3_2_SUPPORT                1
+#define SMBIOS_3_3_SUPPORT                1
 
 #endif /* SOC_DMI_INFO_H */
diff --git a/src/vendorcode/amd/fsp/common/dmi_info.h b/src/vendorcode/amd/fsp/common/dmi_info.h
index 5593d760f5..e38a44ed94 100644
--- a/src/vendorcode/amd/fsp/common/dmi_info.h
+++ b/src/vendorcode/amd/fsp/common/dmi_info.h
@@ -165,7 +165,7 @@ typedef struct {
   OUT UINT16                    MaximumVoltage;         ///< Maximum operating voltage for this device, in millivolts
   OUT UINT16                    ConfiguredVoltage;      ///< Configured voltage for this device, in millivolts
   // SMBIOS 3.2
-#ifdef SMBIOS_3_2_3_3_SUPPORT
+#ifdef SMBIOS_3_2_SUPPORT
   OUT UINT8                     MemoryTechnology;       ///< Memory technology type for this memory device
   OUT DMI_T17_MEMORY_OPERATING_MODE_CAPABILITY_VAR   MemoryOperatingModeCapability; ///< The operating modes supported by this memory device
   OUT CHAR8                     FirmwareVersion[10];    ///< String number for the firmware version of this memory device
@@ -178,9 +178,11 @@ typedef struct {
   OUT UINT64                    CacheSize;              ///< Size of the Cache portion of the memory device in Bytes, if any.
   OUT UINT64                    LogicalSize;            ///< Size of the Logical memory device in Bytes.
   // SMBIOS 3.3
+#ifdef SMBIOS_3_3_SUPPORT
   OUT UINT32                    ExtendedSpeed;          ///< Extended Speed
   OUT UINT32                    ExtendedConfiguredMemorySpeed; ///< Extended Configured memory speed
 #endif
+#endif
 } __packed TYPE17_DMI_INFO;
 
 /// Collection of pointers to the DMI records
diff --git a/src/vendorcode/amd/fsp/glinda/soc_dmi_info.h b/src/vendorcode/amd/fsp/glinda/soc_dmi_info.h
index 3f24fe9b16..15c7b63a71 100644
--- a/src/vendorcode/amd/fsp/glinda/soc_dmi_info.h
+++ b/src/vendorcode/amd/fsp/glinda/soc_dmi_info.h
@@ -13,6 +13,7 @@
 #define AGESA_STRUCT_DIMMS_PER_CHANNEL    2   ///< DIMMs per channel in AGESA FSP DMI T17 table
 #define AGESA_STRUCT_PART_NUMBER_SIZE     31
 
-#define SMBIOS_3_2_3_3_SUPPORT            1
+#define SMBIOS_3_2_SUPPORT                1
+#define SMBIOS_3_3_SUPPORT                1
 
 #endif /* SOC_DMI_INFO_H */
diff --git a/src/vendorcode/amd/fsp/mendocino/soc_dmi_info.h b/src/vendorcode/amd/fsp/mendocino/soc_dmi_info.h
index 1c3cb1a0b1..bf35aea3e5 100644
--- a/src/vendorcode/amd/fsp/mendocino/soc_dmi_info.h
+++ b/src/vendorcode/amd/fsp/mendocino/soc_dmi_info.h
@@ -12,6 +12,7 @@
 #define AGESA_STRUCT_DIMMS_PER_CHANNEL    2   ///< DIMMs per channel in AGESA FSP DMI T17 table
 #define AGESA_STRUCT_PART_NUMBER_SIZE     21
 
-#define SMBIOS_3_2_3_3_SUPPORT            1
+#define SMBIOS_3_2_SUPPORT                1
+#define SMBIOS_3_3_SUPPORT                1
 
 #endif /* SOC_DMI_INFO_H */
diff --git a/src/vendorcode/amd/fsp/phoenix/soc_dmi_info.h b/src/vendorcode/amd/fsp/phoenix/soc_dmi_info.h
index 1c3cb1a0b1..bf35aea3e5 100644
--- a/src/vendorcode/amd/fsp/phoenix/soc_dmi_info.h
+++ b/src/vendorcode/amd/fsp/phoenix/soc_dmi_info.h
@@ -12,6 +12,7 @@
 #define AGESA_STRUCT_DIMMS_PER_CHANNEL    2   ///< DIMMs per channel in AGESA FSP DMI T17 table
 #define AGESA_STRUCT_PART_NUMBER_SIZE     21
 
-#define SMBIOS_3_2_3_3_SUPPORT            1
+#define SMBIOS_3_2_SUPPORT                1
+#define SMBIOS_3_3_SUPPORT                1
 
 #endif /* SOC_DMI_INFO_H */
diff --git a/src/vendorcode/amd/fsp/renoir/soc_dmi_info.h b/src/vendorcode/amd/fsp/renoir/soc_dmi_info.h
index 5726dffa59..762320cdc3 100644
--- a/src/vendorcode/amd/fsp/renoir/soc_dmi_info.h
+++ b/src/vendorcode/amd/fsp/renoir/soc_dmi_info.h
@@ -12,6 +12,6 @@
 #define AGESA_STRUCT_DIMMS_PER_CHANNEL    4   ///< DIMMs per channel in AGESA FSP DMI T17 table
 #define AGESA_STRUCT_PART_NUMBER_SIZE     21 //TODO check
 
-#define SMBIOS_3_2_3_3_SUPPORT            1
+#define SMBIOS_3_2_SUPPORT                1
 
 #endif /* SOC_DMI_INFO_H */

From 520bc70b573443d437a3b430c07ebbd55c396159 Mon Sep 17 00:00:00 2001
From: Anand Vaikar <a.vaikar2021@gmail.com>
Date: Tue, 12 Aug 2025 16:48:05 +0530
Subject: [PATCH 2593/3886] mb/amd/crater: Configure UART1 GPIOs

Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: I9b04479d2e1508d767cfc4dc94d2ac55163cc369
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90208
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/amd/crater/early_gpio.c | 5 +++++
 src/mainboard/amd/crater/gpio.c       | 6 ++++++
 2 files changed, 11 insertions(+)

diff --git a/src/mainboard/amd/crater/early_gpio.c b/src/mainboard/amd/crater/early_gpio.c
index de490b3ee1..bb378a0c73 100644
--- a/src/mainboard/amd/crater/early_gpio.c
+++ b/src/mainboard/amd/crater/early_gpio.c
@@ -47,6 +47,11 @@ static const struct soc_amd_gpio gpio_set_stage_reset[] = {
 	/*MDIO1_SDA*/
 	PAD_NF(GPIO_23, MDIO1_SDA, PULL_DOWN),
 
+	/* Enable UART 1 */
+	/* UART1_TXD */
+	PAD_NF(GPIO_140, UART1_TXD, PULL_NONE),
+	/* UART1_RXD */
+	PAD_NF(GPIO_142, UART1_RXD, PULL_NONE),
 
 	/* Enable UART 0 */
 	/* UART0_RXD */
diff --git a/src/mainboard/amd/crater/gpio.c b/src/mainboard/amd/crater/gpio.c
index b1da83e8db..72131baacc 100644
--- a/src/mainboard/amd/crater/gpio.c
+++ b/src/mainboard/amd/crater/gpio.c
@@ -49,6 +49,12 @@ static const struct soc_amd_gpio gpio_set_stage_ram[] = {
 	/*MDIO1_SDA*/
 	PAD_NF(GPIO_23, MDIO1_SDA, PULL_DOWN),
 
+	/* Enable UART 1 */
+	/* UART1_TXD */
+	PAD_NF(GPIO_140, UART1_TXD, PULL_NONE),
+	/* UART1_RXD */
+	PAD_NF(GPIO_142, UART1_RXD, PULL_NONE),
+
 	/* Enable UART 0 */
 	/* UART0_RXD */
 	PAD_NF(GPIO_141, UART0_RXD, PULL_NONE),

From 149d11d1d8762c912d986986a4ec4aedf6055841 Mon Sep 17 00:00:00 2001
From: Maximilian Brune <maximilian.brune@9elements.com>
Date: Wed, 5 Nov 2025 16:22:58 +0100
Subject: [PATCH 2594/3886] soc/amd/cezanne/Kconfig: Select Kconfig to program
 the PSP_ADDR MSR

The PSP_ADDR_MSR is programmed into the BSP by FSP, but not always
propagated to the other cores/APs. Add a hook to run a function
which will read the MSR value from the BSP, and program it into the
APs, guarded by a Kconfig.

It only writes the MSRs of the APs if they are not initialized yet.

Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: I45771e596ac4354dd233a47fcae33012d9c0a6c9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90209
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
---
 src/soc/amd/cezanne/Kconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/src/soc/amd/cezanne/Kconfig b/src/soc/amd/cezanne/Kconfig
index 955e1fa3bc..e7767f36f4 100644
--- a/src/soc/amd/cezanne/Kconfig
+++ b/src/soc/amd/cezanne/Kconfig
@@ -100,6 +100,7 @@ config SOC_AMD_CEZANNE
 config SOC_AMD_RENOIR
 	bool
 	select SOC_AMD_CEZANNE_BASE
+	select SOC_AMD_COMMON_BLOCK_CPU_SYNC_PSP_ADDR_MSR
 	help
 		AMD Renoir support
 

From 97291b5838358df157e134d5764f457ed59ecf2f Mon Sep 17 00:00:00 2001
From: Maximilian Brune <maximilian.brune@9elements.com>
Date: Mon, 10 Nov 2025 13:17:29 +0100
Subject: [PATCH 2595/3886] soc/amd/cezanne: Optionally propagate UART0 through
 ACPI

Unable to passthrough the UART0 in domU when UART1 enabled in dom0

Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: I7ccf366dbac556f68096382644f3e72b13e2dbf9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90210
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/soc/amd/cezanne/Kconfig       | 8 ++++++++
 src/soc/amd/cezanne/acpi/mmio.asl | 2 ++
 2 files changed, 10 insertions(+)

diff --git a/src/soc/amd/cezanne/Kconfig b/src/soc/amd/cezanne/Kconfig
index e7767f36f4..eeb4266c84 100644
--- a/src/soc/amd/cezanne/Kconfig
+++ b/src/soc/amd/cezanne/Kconfig
@@ -351,6 +351,14 @@ config DISABLE_KEYBOARD_RESET_PIN
 	  functionality isn't disabled, configuring it as an output and driving
 	  it as 0 will cause a reset.
 
+config UART0_REMOVE_FROM_DSDT
+	bool "Do not add UART0 to ACPI DSDT"
+	default n
+	help
+	  Select this option to remove the UART0 device from the ACPI DSDT, so that the UART
+	  can be passed through to domU instead of being used by dom0 in the virtualization
+	  case.
+
 menu "PSP Configuration Options"
 
 config AMDFW_CONFIG_FILE
diff --git a/src/soc/amd/cezanne/acpi/mmio.asl b/src/soc/amd/cezanne/acpi/mmio.asl
index c138cbcb03..647ab748f2 100644
--- a/src/soc/amd/cezanne/acpi/mmio.asl
+++ b/src/soc/amd/cezanne/acpi/mmio.asl
@@ -94,6 +94,7 @@ Device (MMC0)
 	}
 }
 
+#if !CONFIG(UART0_REMOVE_FROM_DSDT)
 Device (FUR0)
 {
 	Name (_HID, "AMDI0020")
@@ -131,6 +132,7 @@ Device (FUR0)
 
 	AOAC_DEVICE(FCH_AOAC_DEV_UART0, 0)
 }
+#endif
 
 Device (FUR1) {
 	Name (_HID, "AMDI0020")

From 384e6e1c375a5c58aef92d9f8942d8218e6ef252 Mon Sep 17 00:00:00 2001
From: Maximilian Brune <maximilian.brune@9elements.com>
Date: Tue, 25 Nov 2025 20:45:19 +0100
Subject: [PATCH 2596/3886] soc/amd/cezanne: Remove set_resets_to_cold

Renoir actually supports warm reset, so we don't need to toggle the
PwrGood for all resets.

Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: I45d6b559874d67b886c65f7ad722f96eba415399
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90211
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/soc/amd/cezanne/Kconfig | 1 +
 src/soc/amd/cezanne/fch.c   | 4 +++-
 2 files changed, 4 insertions(+), 1 deletion(-)

diff --git a/src/soc/amd/cezanne/Kconfig b/src/soc/amd/cezanne/Kconfig
index eeb4266c84..d02339e400 100644
--- a/src/soc/amd/cezanne/Kconfig
+++ b/src/soc/amd/cezanne/Kconfig
@@ -100,6 +100,7 @@ config SOC_AMD_CEZANNE
 config SOC_AMD_RENOIR
 	bool
 	select SOC_AMD_CEZANNE_BASE
+	select SOC_AMD_SUPPORTS_WARM_RESET
 	select SOC_AMD_COMMON_BLOCK_CPU_SYNC_PSP_ADDR_MSR
 	help
 		AMD Renoir support
diff --git a/src/soc/amd/cezanne/fch.c b/src/soc/amd/cezanne/fch.c
index 52bdbb03f1..1fabe3a864 100644
--- a/src/soc/amd/cezanne/fch.c
+++ b/src/soc/amd/cezanne/fch.c
@@ -173,7 +173,9 @@ static void cgpll_clock_gate_init(void)
 
 void fch_init(void *chip_info)
 {
-	set_resets_to_cold();
+	if (!CONFIG(SOC_AMD_RENOIR))
+		set_resets_to_cold();
+
 	i2c_soc_init();
 	fch_init_acpi_ports();
 

From f35cb39de583a05a21d1a92a61cd8598c2950b06 Mon Sep 17 00:00:00 2001
From: Maximilian Brune <maximilian.brune@9elements.com>
Date: Mon, 10 Nov 2025 17:24:41 +0100
Subject: [PATCH 2597/3886] soc/amd/cezanne: Increase APOB DRAM size for Renoir

The renoir variant has larger APOB data.

Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: I7b7da3b35f2795deb785f82326f3e6c640f6e9ca
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90213
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
---
 src/mainboard/amd/crater/board_renoir.fmd    | 2 +-
 src/mainboard/amd/crater/chromeos_renoir.fmd | 2 +-
 src/soc/amd/cezanne/Kconfig                  | 2 ++
 src/soc/amd/cezanne/memmap.c                 | 4 ++--
 4 files changed, 6 insertions(+), 4 deletions(-)

diff --git a/src/mainboard/amd/crater/board_renoir.fmd b/src/mainboard/amd/crater/board_renoir.fmd
index b5a4e73a00..f3606246d2 100644
--- a/src/mainboard/amd/crater/board_renoir.fmd
+++ b/src/mainboard/amd/crater/board_renoir.fmd
@@ -6,6 +6,6 @@ FLASH 16M {
 		PSP_NVRAM(PRESERVE) 128K
 		PSP_RPMC_NVRAM(PRESERVE) 256K
 		EC_BODY@15872K 256K
-		RW_MRC_CACHE 64K
+		RW_MRC_CACHE 120K
 	}
 }
diff --git a/src/mainboard/amd/crater/chromeos_renoir.fmd b/src/mainboard/amd/crater/chromeos_renoir.fmd
index 12b472774e..71b8827ced 100644
--- a/src/mainboard/amd/crater/chromeos_renoir.fmd
+++ b/src/mainboard/amd/crater/chromeos_renoir.fmd
@@ -30,6 +30,6 @@ FLASH 16M {
 		SMMSTORE(PRESERVE) 256K
 		RW_LEGACY(CBFS)
 		EC_BODY@15872K 256K
-		RW_MRC_CACHE(PRESERVE) 64K
+		RW_MRC_CACHE(PRESERVE) 120K
 	}
 }
diff --git a/src/soc/amd/cezanne/Kconfig b/src/soc/amd/cezanne/Kconfig
index d02339e400..26d3f3e4a8 100644
--- a/src/soc/amd/cezanne/Kconfig
+++ b/src/soc/amd/cezanne/Kconfig
@@ -157,10 +157,12 @@ config PSP_APOB_DRAM_ADDRESS
 
 config PSP_APOB_DRAM_SIZE
 	hex
+	default 0x1E000 if SOC_AMD_RENOIR
 	default 0x10000
 
 config PSP_SHAREDMEM_BASE
 	hex
+	default 0x201F000 if VBOOT && SOC_AMD_RENOIR
 	default 0x2011000 if VBOOT
 	default 0x0
 	help
diff --git a/src/soc/amd/cezanne/memmap.c b/src/soc/amd/cezanne/memmap.c
index bb1eca24e6..feecdd7b13 100644
--- a/src/soc/amd/cezanne/memmap.c
+++ b/src/soc/amd/cezanne/memmap.c
@@ -32,7 +32,7 @@
  *                     |     (C_ENV_BOOTBLOCK_SIZE)     |
  *                     +--------------------------------+ BOOTBLOCK_ADDR = BOOTBLOCK_END - C_ENV_BOOTBLOCK_SIZE
  *                     |          Unused hole           |
- *                     |            (86KiB)             |
+ *                     |            (30KiB)             |
  *                     +--------------------------------+
  *                     |     FMAP cache (FMAP_SIZE)     |
  *                     +--------------------------------+ PSP_SHAREDMEM_BASE + PSP_SHAREDMEM_SIZE + PRERAM_CBMEM_CONSOLE_SIZE + 0x200
@@ -44,7 +44,7 @@
  *                     |   PSP shared (vboot workbuf)   |
  *                     |      (PSP_SHAREDMEM_SIZE)      |
  *                     +--------------------------------+ PSP_SHAREDMEM_BASE
- *                     |          APOB (64KiB)          |
+ *                     |          APOB (120KiB)         |
  *                     +--------------------------------+ PSP_APOB_DRAM_ADDRESS
  *                     |        Early BSP stack         |
  *                     |   (EARLYRAM_BSP_STACK_SIZE)    |

From fecf05c4f26a7500a19d34b21ab2e0b6b089535e Mon Sep 17 00:00:00 2001
From: Terry Cheong <htcheong@chromium.org>
Date: Wed, 26 Nov 2025 16:50:22 +0800
Subject: [PATCH 2598/3886] mb/google/trulo/var/kaladin: Mute speaker amp to
 prevent pop noise on reboot

This change mutes the amplifier by updating the HDA verb table boot beep
section, which is configured at boot time. The amplifier will be unmuted when
generating a dev beep to preserve that functionality.

After entering OS, the kernel will reset the drivers and re-enable the
speaker.

BUG=b:457933720
TEST=Play audio in the OS and reboot the device. Verify that no pop
noise is heard from the speakers.
TEST=Verify devbeep function

Change-Id: I19ef19533d8ed7522e638787c8179ae0fdbf1ebb
Signed-off-by: Terry Cheong <htcheong@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90238
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/google/brya/variants/kaladin/hda_verb.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/mainboard/google/brya/variants/kaladin/hda_verb.c b/src/mainboard/google/brya/variants/kaladin/hda_verb.c
index bb978b8120..91c4e6d785 100644
--- a/src/mainboard/google/brya/variants/kaladin/hda_verb.c
+++ b/src/mainboard/google/brya/variants/kaladin/hda_verb.c
@@ -114,7 +114,7 @@ const u32 pc_beep_verbs[] = {
 	0x02050010,
 	0x02040020,
 	/* Dos beep path - 2 */
-	0x0143B000,
+	0x0143B080,
 	0x01470740,
 	0x01470C02,
 	0x01470C02,

From 804aab3abb9ac5ad0b7123af4c558ccaa88316df Mon Sep 17 00:00:00 2001
From: Luca Lai <luca.lai@lcfc.corp-partner.google.com>
Date: Tue, 4 Nov 2025 11:01:41 +0800
Subject: [PATCH 2599/3886] mb/google/fatcat/var/ruby: Modify usb3 port setting

Modify usb3 port 0 and 1 settings by vendor's advices.

BUG=b:446771934
TEST=Build and boot to OS, check usb3 functions work by lsusb -t.

Change-Id: I9ed47ead1b2ef0b007897513ceb99e9460875bdc
Signed-off-by: Luca Lai <luca.lai@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89883
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
---
 src/mainboard/google/fatcat/variants/ruby/overridetree.cb | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/mainboard/google/fatcat/variants/ruby/overridetree.cb b/src/mainboard/google/fatcat/variants/ruby/overridetree.cb
index 2e5f29faa6..2de2dc082b 100644
--- a/src/mainboard/google/fatcat/variants/ruby/overridetree.cb
+++ b/src/mainboard/google/fatcat/variants/ruby/overridetree.cb
@@ -32,8 +32,8 @@ chip soc/intel/pantherlake
 	register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)" # Type-A Port A1 (DB)
 	register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" # Fingerprint
 
-	register "usb3_ports[0]" = "USB3_PORT_EMPTY" # no use
-	register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB3.2 Type-A (DB)
+	register "usb3_ports[0]" = "USB3_PORT_TX_CFG(OC_SKIP, 0x4)" # USB3.2 x1 Type-A Con #1 (MB)
+	register "usb3_ports[1]" = "USB3_PORT_TX_CFG(OC_SKIP, 0x4)" # USB3.2 x1 Type-A Con #2 (DB)
 
 	register "tcss_ports[0]" = "TCSS_PORT_DEFAULT(OC_SKIP)" # USB3_C0
 	register "tcss_ports[2]" = "TCSS_PORT_DEFAULT(OC_SKIP)" # USB3_C1

From 2462e3a027a90c3ea79d2a4f46731b7dcbc4bfae Mon Sep 17 00:00:00 2001
From: Yidi Lin <yidilin@google.com>
Date: Thu, 27 Nov 2025 20:32:09 +0800
Subject: [PATCH 2600/3886] soc/mediatek/mt8188: Adjust memlayout for bootblock
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Increase the bootblock size to 70K to accommodate its growth, e.g.,
CB:90147 and CB:89157.

This commit also conditionally includes the DRAM_INIT_CODE section when
ENV_ROMSTAGE is enabled, and the BOOTBLOCK section otherwise. This
allows increased BOOTBLOCK overlapping with DRAM_INIT_CODE as these two
sections won't be utilized in the same boot stage.

TEST=emerge-geralt coreboot

Change-Id: Ib7b930fbb1815d2f24b9618d94a38d02c66eab97
Signed-off-by: Yidi Lin <yidilin@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90251
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Filip Lewiński <filip.lewinski@3mdeb.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Chen-Tsung Hsieh <chentsung@google.com>
---
 src/soc/mediatek/mt8188/include/soc/memlayout.ld | 15 +++++++++------
 1 file changed, 9 insertions(+), 6 deletions(-)

diff --git a/src/soc/mediatek/mt8188/include/soc/memlayout.ld b/src/soc/mediatek/mt8188/include/soc/memlayout.ld
index 732b5baeb6..c2fafe7f22 100644
--- a/src/soc/mediatek/mt8188/include/soc/memlayout.ld
+++ b/src/soc/mediatek/mt8188/include/soc/memlayout.ld
@@ -33,18 +33,21 @@ SECTIONS
 	 * can't reconfigure whole L3 as SRAM).
 	 */
 	SRAM_L2C_START(0x00200000)
-	/*
-	 * The bootROM needs 4K starting from SRAM_L2C_START so the bootblock starting address
-	 * is fixed at SRAM_L2C_START + 4K, and the 4K can be reused after bootblock is started.
-	 * To move the address, gen-bl-img.py also needs to be modified accordingly.
-	 */
-	BOOTBLOCK(0x00201000, 60K)
+	#if ENV_ROMSTAGE
 	/*
 	 * The needed size can be obtained by:
 	 *  aarch64-cros-linux-gnu-objdump -x dram.elf | grep memsz
 	 * To move the address, dram.elf also needs to be modified accordingly.
 	 */
 	DRAM_INIT_CODE(0x00210000, 300K)
+	#else
+	/*
+	 * The bootROM needs 4K starting from SRAM_L2C_START so the bootblock starting address
+	 * is fixed at SRAM_L2C_START + 4K, and the 4K can be reused after bootblock is started.
+	 * To move the address, gen-bl-img.py also needs to be modified accordingly.
+	 */
+	BOOTBLOCK(0x00201000, 70K)
+	#endif
 	OVERLAP_DECOMPRESSOR_VERSTAGE_ROMSTAGE(0x0025b000, 272K)
 	PRERAM_CBFS_CACHE(0x0029f000, 48K)
 	PRERAM_CBMEM_CONSOLE(0x002ab000, 340K)

From cc542c15f4272b189135bb403a65845f6e529c17 Mon Sep 17 00:00:00 2001
From: Maximilian Brune <maximilian.brune@9elements.com>
Date: Tue, 10 Jun 2025 20:03:55 +0200
Subject: [PATCH 2601/3886] include/acpi: Move Error definitions/declarations
 into acpi_apei.h
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

This moves all the definitions and declarations that are part of the
ACPI Platform Error Interface (APEI) into the corresponding header file.

Change-Id: Ied3915e4f598cd393f396de26b07ade7ce3a7ab1
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88036
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Benjamin Doron <benjamin.doron00@gmail.com>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
---
 src/arch/x86/acpi_bert_storage.c         |   1 +
 src/arch/x86/include/arch/bert_storage.h |   1 +
 src/include/acpi/acpi.h                  | 248 +----------------------
 src/include/acpi/acpi_apei.h             | 234 +++++++++++++++++++++
 4 files changed, 244 insertions(+), 240 deletions(-)

diff --git a/src/arch/x86/acpi_bert_storage.c b/src/arch/x86/acpi_bert_storage.c
index 62c044137d..2d5a055ec6 100644
--- a/src/arch/x86/acpi_bert_storage.c
+++ b/src/arch/x86/acpi_bert_storage.c
@@ -1,5 +1,6 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
+#include <acpi/acpi_apei.h>
 #include <bootstate.h>
 #include <cbmem.h>
 #include <console/console.h>
diff --git a/src/arch/x86/include/arch/bert_storage.h b/src/arch/x86/include/arch/bert_storage.h
index ab44c9c32c..d979d64000 100644
--- a/src/arch/x86/include/arch/bert_storage.h
+++ b/src/arch/x86/include/arch/bert_storage.h
@@ -4,6 +4,7 @@
 #define _BERT_STORAGE_H_
 
 #include <acpi/acpi.h>
+#include <acpi/acpi_apei.h>
 #include <types.h>
 
 /* Items in the BERT region
diff --git a/src/include/acpi/acpi.h b/src/include/acpi/acpi.h
index b704255c46..ca1ec7d894 100644
--- a/src/include/acpi/acpi.h
+++ b/src/include/acpi/acpi.h
@@ -135,6 +135,14 @@ typedef struct acpi_gen_regaddr {
 	u32 addrh;		/* Register address, high 32 bits */
 } __packed acpi_addr_t;
 
+typedef struct acpi_gen_regaddr1 {
+	u8  space_id;		/* Address space ID */
+	u8  bit_width;		/* Register size in bits */
+	u8  bit_offset;		/* Register bit offset */
+	u8  access_size;	/* Access size since ACPI 2.0c */
+	u64 addr;		/* Register address */
+} __packed acpi_addr64_t;
+
 #define ACPI_ADDRESS_SPACE_MEMORY		0	/* System memory */
 #define ACPI_ADDRESS_SPACE_IO			1	/* System I/O */
 #define ACPI_ADDRESS_SPACE_PCI			2	/* PCI config space */
@@ -1085,114 +1093,6 @@ typedef struct acpi_ecdt {
 	u8 ec_id[];				/* EC ID  */
 } __packed acpi_ecdt_t;
 
-/* HEST (Hardware Error Source Table) */
-typedef struct acpi_hest {
-	acpi_header_t header;
-	u32 error_source_count;
-	/* error_source_struct(s) */
-} __packed acpi_hest_t;
-
-/* Error Source Descriptors */
-typedef struct acpi_hest_esd {
-	u16 type;
-	u16 source_id;
-	u16 resv;
-	u8 flags;
-	u8 enabled;
-	u32 prealloc_erecords;		/* The number of error records to
-					 * pre-allocate for this error source.
-					 */
-	u32 max_section_per_record;
-} __packed acpi_hest_esd_t;
-
-/* Hardware Error Notification */
-typedef struct acpi_hest_hen {
-	u8 type;
-	u8 length;
-	u16 conf_we;		/* Configuration Write Enable */
-	u32 poll_interval;
-	u32 vector;
-	u32 sw2poll_threshold_val;
-	u32 sw2poll_threshold_win;
-	u32 error_threshold_val;
-	u32 error_threshold_win;
-} __packed acpi_hest_hen_t;
-
-/* BERT (Boot Error Record Table) */
-typedef struct acpi_bert {
-	acpi_header_t header;
-	u32 region_length;
-	u64 error_region;
-} __packed acpi_bert_t;
-
-/* Generic Error Data Entry */
-typedef struct acpi_hest_generic_data {
-	guid_t section_type;
-	u32 error_severity;
-	u16 revision;
-	u8 validation_bits;
-	u8 flags;
-	u32 data_length;
-	guid_t fru_id;
-	u8 fru_text[20];
-	/* error data */
-} __packed acpi_hest_generic_data_t;
-
-/* Generic Error Data Entry v300 */
-typedef struct acpi_hest_generic_data_v300 {
-	guid_t section_type;
-	u32 error_severity;
-	u16 revision;
-	u8 validation_bits;
-	u8 flags;		/* see CPER Section Descriptor, Flags field */
-	u32 data_length;
-	guid_t fru_id;
-	u8 fru_text[20];
-	cper_timestamp_t timestamp;
-	/* error data */
-} __packed acpi_hest_generic_data_v300_t;
-#define HEST_GENERIC_ENTRY_V300			0x300
-
-/* Both Generic Error Status & Generic Error Data Entry, Error Severity field */
-#define ACPI_GENERROR_SEV_RECOVERABLE		0
-#define ACPI_GENERROR_SEV_FATAL			1
-#define ACPI_GENERROR_SEV_CORRECTED		2
-#define ACPI_GENERROR_SEV_NONE			3
-
-/* Generic Error Data Entry, Validation Bits field */
-#define ACPI_GENERROR_VALID_FRUID		BIT(0)
-#define ACPI_GENERROR_VALID_FRUID_TEXT		BIT(1)
-#define ACPI_GENERROR_VALID_TIMESTAMP		BIT(2)
-
-/*
- * Generic Error Status Block
- *
- * If there is a raw data section at the end of the generic error status block after the
- * zero or more generic error data entries, raw_data_length indicates the length of the raw
- * section and raw_data_offset is the offset of the beginning of the raw data section from
- * the start of the acpi_generic_error_status block it is contained in. So if raw_data_length
- * is non-zero, raw_data_offset must be at least sizeof(acpi_generic_error_status_t).
- */
-typedef struct acpi_generic_error_status {
-	u32 block_status;
-	u32 raw_data_offset;	/* must follow any generic entries */
-	u32 raw_data_length;
-	u32 data_length;	/* generic data */
-	u32 error_severity;
-	/* Generic Error Data structures, zero or more entries */
-} __packed acpi_generic_error_status_t;
-
-/* Generic Status Block, Block Status values */
-#define GENERIC_ERR_STS_UNCORRECTABLE_VALID	BIT(0)
-#define GENERIC_ERR_STS_CORRECTABLE_VALID	BIT(1)
-#define GENERIC_ERR_STS_MULT_UNCORRECTABLE	BIT(2)
-#define GENERIC_ERR_STS_MULT_CORRECTABLE	BIT(3)
-#define GENERIC_ERR_STS_ENTRY_COUNT_SHIFT	4
-#define GENERIC_ERR_STS_ENTRY_COUNT_MAX		0x3ff
-#define GENERIC_ERR_STS_ENTRY_COUNT_MASK	\
-					(GENERIC_ERR_STS_ENTRY_COUNT_MAX \
-					<< GENERIC_ERR_STS_ENTRY_COUNT_SHIFT)
-
 typedef struct acpi_cstate {
 	u8  ctype;
 	u16 latency;
@@ -1307,131 +1207,6 @@ struct acpi_spmi {
 	u8 reserved3;
 } __packed;
 
-/* EINJ APEI Standard Definitions */
-/* EINJ Error Types
-   Refer to the ACPI spec, EINJ section, for more info on bit definitions
-*/
-#define ACPI_EINJ_CPU_CE		(1 << 0)
-#define ACPI_EINJ_CPU_UCE		(1 << 1)
-#define ACPI_EINJ_CPU_UCE_FATAL		(1 << 2)
-#define ACPI_EINJ_MEM_CE		(1 << 3)
-#define ACPI_EINJ_MEM_UCE		(1 << 4)
-#define ACPI_EINJ_MEM_UCE_FATAL		(1 << 5)
-#define ACPI_EINJ_PCIE_CE		(1 << 6)
-#define ACPI_EINJ_PCIE_UCE_NON_FATAL	(1 << 7)
-#define ACPI_EINJ_PCIE_UCE_FATAL	(1 << 8)
-#define ACPI_EINJ_PLATFORM_CE		(1 << 9)
-#define ACPI_EINJ_PLATFORM_UCE		(1 << 10)
-#define ACPI_EINJ_PLATFORM_UCE_FATAL	(1 << 11)
-#define ACPI_EINJ_VENDOR_DEFINED	(1 << 31)
-#define ACPI_EINJ_DEFAULT_CAP		(ACPI_EINJ_MEM_CE | ACPI_EINJ_MEM_UCE | \
-					ACPI_EINJ_PCIE_CE | ACPI_EINJ_PCIE_UCE_FATAL)
-
-/* EINJ actions */
-#define ACTION_COUNT			9
-#define BEGIN_INJECT_OP			0x00
-#define GET_TRIGGER_ACTION_TABLE	0x01
-#define SET_ERROR_TYPE			0x02
-#define GET_ERROR_TYPE			0x03
-#define END_INJECT_OP			0x04
-#define EXECUTE_INJECT_OP		0x05
-#define CHECK_BUSY_STATUS		0x06
-#define GET_CMD_STATUS			0x07
-#define SET_ERROR_TYPE_WITH_ADDRESS	0x08
-#define TRIGGER_ERROR			0xFF
-
-/* EINJ Instructions */
-#define READ_REGISTER			0x00
-#define READ_REGISTER_VALUE		0x01
-#define WRITE_REGISTER			0x02
-#define WRITE_REGISTER_VALUE		0x03
-#define NO_OP				0x04
-
-/* EINJ (Error Injection Table) */
-typedef struct acpi_gen_regaddr1 {
-	u8  space_id;		/* Address space ID */
-	u8  bit_width;		/* Register size in bits */
-	u8  bit_offset;		/* Register bit offset */
-	u8  access_size;	/* Access size since ACPI 2.0c */
-	u64 addr;		/* Register address */
-} __packed acpi_addr64_t;
-
-/* Instruction entry */
-typedef struct acpi_einj_action_table {
-	u8 action;
-	u8 instruction;
-	u16 flags;
-	acpi_addr64_t reg;
-	u64 value;
-	u64 mask;
-} __packed acpi_einj_action_table_t;
-
-typedef struct acpi_injection_header {
-	u32 einj_header_size;
-	u32 flags;
-	u32 entry_count;
-} __packed acpi_injection_header_t;
-
-typedef struct acpi_einj_trigger_table {
-	u32 header_size;
-	u32 revision;
-	u32 table_size;
-	u32 entry_count;
-	acpi_einj_action_table_t trigger_action[];
-} __packed acpi_einj_trigger_table_t;
-
-typedef struct set_error_type {
-	u32 errtype;
-	u32 vendorerrortype;
-	u32 flags;
-	u32 apicid;
-	u64 memaddr;
-	u64 memrange;
-	u32 pciesbdf;
-} __packed set_error_type_t;
-
-#define EINJ_PARAM_NUM 6
-typedef struct acpi_einj_smi {
-	u64 op_state;
-	u64 err_inject[EINJ_PARAM_NUM];
-	u64 trigger_action_table;
-	u64 err_inj_cap;
-	u64 op_status;
-	u64 cmd_sts;
-	u64 einj_addr;
-	u64 einj_addr_msk;
-	set_error_type_t setaddrtable;
-	u64 reserved[50];
-} __packed acpi_einj_smi_t;
-
-/* EINJ Flags */
-#define EINJ_DEF_TRIGGER_PORT	0xb2
-#define FLAG_PRESERVE		0x01
-#define FLAG_IGNORE		0x00
-
-/* EINJ Registers */
-#define EINJ_REG_MEMORY(address) \
-	{ \
-	.space_id = ACPI_ADDRESS_SPACE_MEMORY, \
-	.bit_width = 64, \
-	.bit_offset = 0, \
-	.access_size = ACPI_ACCESS_SIZE_QWORD_ACCESS, \
-	.addr = address}
-
-#define EINJ_REG_IO() \
-	{ \
-	.space_id = ACPI_ADDRESS_SPACE_IO, \
-	.bit_width = 0x10, \
-	.bit_offset = 0, \
-	.access_size = ACPI_ACCESS_SIZE_WORD_ACCESS, \
-	.addr = EINJ_DEF_TRIGGER_PORT} /* HW dependent code can override this also */
-
-typedef struct acpi_einj {
-	acpi_header_t header;
-	acpi_injection_header_t inj_header;
-	acpi_einj_action_table_t action_table[ACTION_COUNT];
-} __packed acpi_einj_t;
-
 /* PPTT definitions */
 
 #define PPTT_NODE_TYPE_CPU   0
@@ -1734,7 +1509,6 @@ typedef struct acpi_table_wdat {
 } __packed acpi_wdat_t;
 
 uintptr_t get_coreboot_rsdp(void);
-void acpi_create_einj(acpi_einj_t *einj, uintptr_t addr, u8 actions);
 
 unsigned long fw_cfg_acpi_tables(unsigned long start);
 
@@ -1880,14 +1654,8 @@ unsigned long acpi_create_dmar_ds_msi_hpet(unsigned long current,
 						u8 enumeration_id,
 						u8 bus, u8 dev, u8 fn);
 
-unsigned long acpi_create_hest_error_source(acpi_hest_t *hest, acpi_hest_esd_t *esd, u16 type,
-					    void *data, u16 len);
-
 unsigned long acpi_create_lpi_desc_ncst(acpi_lpi_desc_ncst_t *lpi_desc, uint16_t uid);
 
-/* chipsets that select ACPI_BERT must implement this function */
-enum cb_err acpi_soc_get_bert_region(void **region, size_t *length);
-
 void acpi_soc_fill_gtdt(acpi_gtdt_t *gtdt);
 unsigned long acpi_soc_gtdt_add_timers(uint32_t *count, unsigned long current);
 unsigned long acpi_gtdt_add_timer_block(unsigned long current, const uint64_t address,
diff --git a/src/include/acpi/acpi_apei.h b/src/include/acpi/acpi_apei.h
index b2edc2dea3..8c3e77e5a3 100644
--- a/src/include/acpi/acpi_apei.h
+++ b/src/include/acpi/acpi_apei.h
@@ -5,6 +5,7 @@
  * These are mostly used by:
  * - BERT (Boot Error Record Table) ACPI Table.
  * - HEST (Hardware Error Source Table) ACPI Table.
+ * - EINJ (Error Injection Table)
  */
 
 #ifndef _ACPI_APEI_H_
@@ -12,6 +13,39 @@
 
 #include <acpi/acpi.h>
 
+/* HEST (Hardware Error Source Table) */
+typedef struct acpi_hest {
+	acpi_header_t header;
+	u32 error_source_count;
+	/* error_source_struct(s) */
+} __packed acpi_hest_t;
+
+/* Error Source Descriptors */
+typedef struct acpi_hest_esd {
+	u16 type;
+	u16 source_id;
+	u16 resv;
+	u8 flags;
+	u8 enabled;
+	u32 prealloc_erecords;		/* The number of error records to
+					 * pre-allocate for this error source.
+					 */
+	u32 max_section_per_record;
+} __packed acpi_hest_esd_t;
+
+/* Hardware Error Notification */
+typedef struct acpi_hest_hen {
+	u8 type;
+	u8 length;
+	u16 conf_we;		/* Configuration Write Enable */
+	u32 poll_interval;
+	u32 vector;
+	u32 sw2poll_threshold_val;
+	u32 sw2poll_threshold_win;
+	u32 error_threshold_val;
+	u32 error_threshold_win;
+} __packed acpi_hest_hen_t;
+
 /* Generic Hardware Error Source Descriptor */
 typedef struct acpi_ghes_esd {
 	u16 type;
@@ -31,6 +65,206 @@ typedef struct ghes_record {
 	u32 err_sts_blk_len;
 } __packed ghes_record_t;
 
+/* BERT (Boot Error Record Table) */
+typedef struct acpi_bert {
+	acpi_header_t header;
+	u32 region_length;
+	u64 error_region;
+} __packed acpi_bert_t;
+
+/* Generic Error Data Entry */
+typedef struct acpi_hest_generic_data {
+	guid_t section_type;
+	u32 error_severity;
+	u16 revision;
+	u8 validation_bits;
+	u8 flags;
+	u32 data_length;
+	guid_t fru_id;
+	u8 fru_text[20];
+	/* error data */
+} __packed acpi_hest_generic_data_t;
+
+/* Generic Error Data Entry v300 */
+typedef struct acpi_hest_generic_data_v300 {
+	guid_t section_type;
+	u32 error_severity;
+	u16 revision;
+	u8 validation_bits;
+	u8 flags;		/* see CPER Section Descriptor, Flags field */
+	u32 data_length;
+	guid_t fru_id;
+	u8 fru_text[20];
+	cper_timestamp_t timestamp;
+	/* error data */
+} __packed acpi_hest_generic_data_v300_t;
+#define HEST_GENERIC_ENTRY_V300			0x300
+
+/* Both Generic Error Status & Generic Error Data Entry, Error Severity field */
+#define ACPI_GENERROR_SEV_RECOVERABLE		0
+#define ACPI_GENERROR_SEV_FATAL			1
+#define ACPI_GENERROR_SEV_CORRECTED		2
+#define ACPI_GENERROR_SEV_NONE			3
+
+/* Generic Error Data Entry, Validation Bits field */
+#define ACPI_GENERROR_VALID_FRUID		BIT(0)
+#define ACPI_GENERROR_VALID_FRUID_TEXT		BIT(1)
+#define ACPI_GENERROR_VALID_TIMESTAMP		BIT(2)
+
+/*
+ * Generic Error Status Block
+ *
+ * If there is a raw data section at the end of the generic error status block after the
+ * zero or more generic error data entries, raw_data_length indicates the length of the raw
+ * section and raw_data_offset is the offset of the beginning of the raw data section from
+ * the start of the acpi_generic_error_status block it is contained in. So if raw_data_length
+ * is non-zero, raw_data_offset must be at least sizeof(acpi_generic_error_status_t).
+ */
+typedef struct acpi_generic_error_status {
+	u32 block_status;
+	u32 raw_data_offset;	/* must follow any generic entries */
+	u32 raw_data_length;
+	u32 data_length;	/* generic data */
+	u32 error_severity;
+	/* Generic Error Data structures, zero or more entries */
+} __packed acpi_generic_error_status_t;
+
+/* Generic Status Block, Block Status values */
+#define GENERIC_ERR_STS_UNCORRECTABLE_VALID	BIT(0)
+#define GENERIC_ERR_STS_CORRECTABLE_VALID	BIT(1)
+#define GENERIC_ERR_STS_MULT_UNCORRECTABLE	BIT(2)
+#define GENERIC_ERR_STS_MULT_CORRECTABLE	BIT(3)
+#define GENERIC_ERR_STS_ENTRY_COUNT_SHIFT	4
+#define GENERIC_ERR_STS_ENTRY_COUNT_MAX		0x3ff
+#define GENERIC_ERR_STS_ENTRY_COUNT_MASK	\
+					(GENERIC_ERR_STS_ENTRY_COUNT_MAX \
+					<< GENERIC_ERR_STS_ENTRY_COUNT_SHIFT)
+
+/* chipsets that select ACPI_BERT must implement this function */
+enum cb_err acpi_soc_get_bert_region(void **region, size_t *length);
+
 uintptr_t acpi_soc_fill_hest(acpi_hest_t *hest, uintptr_t current, void *log_mem);
+unsigned long acpi_create_hest_error_source(acpi_hest_t *hest, acpi_hest_esd_t *esd, u16 type,
+					    void *data, u16 len);
+
+/* EINJ APEI Standard Definitions */
+/* EINJ Error Types
+   Refer to the ACPI spec, EINJ section, for more info on bit definitions
+*/
+#define ACPI_EINJ_CPU_CE		(1 << 0)
+#define ACPI_EINJ_CPU_UCE		(1 << 1)
+#define ACPI_EINJ_CPU_UCE_FATAL		(1 << 2)
+#define ACPI_EINJ_MEM_CE		(1 << 3)
+#define ACPI_EINJ_MEM_UCE		(1 << 4)
+#define ACPI_EINJ_MEM_UCE_FATAL		(1 << 5)
+#define ACPI_EINJ_PCIE_CE		(1 << 6)
+#define ACPI_EINJ_PCIE_UCE_NON_FATAL	(1 << 7)
+#define ACPI_EINJ_PCIE_UCE_FATAL	(1 << 8)
+#define ACPI_EINJ_PLATFORM_CE		(1 << 9)
+#define ACPI_EINJ_PLATFORM_UCE		(1 << 10)
+#define ACPI_EINJ_PLATFORM_UCE_FATAL	(1 << 11)
+#define ACPI_EINJ_VENDOR_DEFINED	(1 << 31)
+#define ACPI_EINJ_DEFAULT_CAP		(ACPI_EINJ_MEM_CE | ACPI_EINJ_MEM_UCE | \
+					ACPI_EINJ_PCIE_CE | ACPI_EINJ_PCIE_UCE_FATAL)
+
+/* EINJ actions */
+#define ACTION_COUNT			9
+#define BEGIN_INJECT_OP			0x00
+#define GET_TRIGGER_ACTION_TABLE	0x01
+#define SET_ERROR_TYPE			0x02
+#define GET_ERROR_TYPE			0x03
+#define END_INJECT_OP			0x04
+#define EXECUTE_INJECT_OP		0x05
+#define CHECK_BUSY_STATUS		0x06
+#define GET_CMD_STATUS			0x07
+#define SET_ERROR_TYPE_WITH_ADDRESS	0x08
+#define TRIGGER_ERROR			0xFF
+
+/* EINJ Instructions */
+#define READ_REGISTER			0x00
+#define READ_REGISTER_VALUE		0x01
+#define WRITE_REGISTER			0x02
+#define WRITE_REGISTER_VALUE		0x03
+#define NO_OP				0x04
+
+/* EINJ (Error Injection Table) */
+
+/* Instruction entry */
+typedef struct acpi_einj_action_table {
+	u8 action;
+	u8 instruction;
+	u16 flags;
+	acpi_addr64_t reg;
+	u64 value;
+	u64 mask;
+} __packed acpi_einj_action_table_t;
+
+typedef struct acpi_injection_header {
+	u32 einj_header_size;
+	u32 flags;
+	u32 entry_count;
+} __packed acpi_injection_header_t;
+
+typedef struct acpi_einj_trigger_table {
+	u32 header_size;
+	u32 revision;
+	u32 table_size;
+	u32 entry_count;
+	acpi_einj_action_table_t trigger_action[];
+} __packed acpi_einj_trigger_table_t;
+
+typedef struct set_error_type {
+	u32 errtype;
+	u32 vendorerrortype;
+	u32 flags;
+	u32 apicid;
+	u64 memaddr;
+	u64 memrange;
+	u32 pciesbdf;
+} __packed set_error_type_t;
+
+#define EINJ_PARAM_NUM 6
+typedef struct acpi_einj_smi {
+	u64 op_state;
+	u64 err_inject[EINJ_PARAM_NUM];
+	u64 trigger_action_table;
+	u64 err_inj_cap;
+	u64 op_status;
+	u64 cmd_sts;
+	u64 einj_addr;
+	u64 einj_addr_msk;
+	set_error_type_t setaddrtable;
+	u64 reserved[50];
+} __packed acpi_einj_smi_t;
+
+/* EINJ Flags */
+#define EINJ_DEF_TRIGGER_PORT	0xb2
+#define FLAG_PRESERVE		0x01
+#define FLAG_IGNORE		0x00
+
+/* EINJ Registers */
+#define EINJ_REG_MEMORY(address) \
+	{ \
+	.space_id = ACPI_ADDRESS_SPACE_MEMORY, \
+	.bit_width = 64, \
+	.bit_offset = 0, \
+	.access_size = ACPI_ACCESS_SIZE_QWORD_ACCESS, \
+	.addr = address}
+
+#define EINJ_REG_IO() \
+	{ \
+	.space_id = ACPI_ADDRESS_SPACE_IO, \
+	.bit_width = 0x10, \
+	.bit_offset = 0, \
+	.access_size = ACPI_ACCESS_SIZE_WORD_ACCESS, \
+	.addr = EINJ_DEF_TRIGGER_PORT} /* HW dependent code can override this also */
+
+typedef struct acpi_einj {
+	acpi_header_t header;
+	acpi_injection_header_t inj_header;
+	acpi_einj_action_table_t action_table[ACTION_COUNT];
+} __packed acpi_einj_t;
+
+void acpi_create_einj(acpi_einj_t *einj, uintptr_t addr, u8 actions);
 
 #endif

From 2aadfc2b5e14b618624d1a2986a5d2475dd7f8c3 Mon Sep 17 00:00:00 2001
From: Maximilian Brune <maximilian.brune@9elements.com>
Date: Mon, 16 Jun 2025 12:36:19 +0200
Subject: [PATCH 2602/3886] soc/amd/common/block/acpi: Add ACPI HEST table

Adds skeleton code so that the HEST ACPI table is included as part of
the ACPI tables propagated to the OS.

The ACPI table can be included by mainboards by selecting
SOC_AMD_COMMON_BLOCK_ACPI_HEST.

TEST=Select the option, build the mainboard and see the output in Linux:
[    0.282277] HEST: Table parsing has been initialized.

Change-Id: I69886a19764d6974cbe129a8a6bf717f7808fb08
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88113
Reviewed-by: Benjamin Doron <benjamin.doron00@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Anand Vaikar <a.vaikar2021@gmail.com>
---
 src/soc/amd/common/block/acpi/Kconfig     |  4 ++++
 src/soc/amd/common/block/acpi/Makefile.mk |  1 +
 src/soc/amd/common/block/acpi/hest.c      | 12 ++++++++++++
 3 files changed, 17 insertions(+)
 create mode 100644 src/soc/amd/common/block/acpi/hest.c

diff --git a/src/soc/amd/common/block/acpi/Kconfig b/src/soc/amd/common/block/acpi/Kconfig
index 90e66b2ca7..7f121b5fba 100644
--- a/src/soc/amd/common/block/acpi/Kconfig
+++ b/src/soc/amd/common/block/acpi/Kconfig
@@ -29,6 +29,10 @@ config SOC_AMD_COMMON_BLOCK_ACPI_CPU_POWER_STATE
 config SOC_AMD_COMMON_BLOCK_ACPI_GPIO
 	bool
 
+config SOC_AMD_COMMON_BLOCK_ACPI_HEST
+	bool
+	select ACPI_HEST
+
 config SOC_AMD_COMMON_BLOCK_ACPI_IVRS
 	bool
 
diff --git a/src/soc/amd/common/block/acpi/Makefile.mk b/src/soc/amd/common/block/acpi/Makefile.mk
index 763a3bc61a..50de3459d4 100644
--- a/src/soc/amd/common/block/acpi/Makefile.mk
+++ b/src/soc/amd/common/block/acpi/Makefile.mk
@@ -7,6 +7,7 @@ smm-y += acpi.c
 ramstage-y += pm_state.c
 ramstage-y += tables.c
 ramstage-$(CONFIG_ACPI_BERT) += bert.c
+ramstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_ACPI_HEST) += hest.c
 ramstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_ACPI_ALIB) += alib.c
 ramstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_ACPI_CPPC) += cppc.c
 ramstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_ACPI_CPU_POWER_STATE) += cpu_power_state.c
diff --git a/src/soc/amd/common/block/acpi/hest.c b/src/soc/amd/common/block/acpi/hest.c
new file mode 100644
index 0000000000..c6d6ec1ebb
--- /dev/null
+++ b/src/soc/amd/common/block/acpi/hest.c
@@ -0,0 +1,12 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <acpi/acpi_apei.h>
+#include <acpi/acpi_gnvs.h>
+#include <cbmem.h>
+#include <console/console.h>
+
+uintptr_t acpi_soc_fill_hest(acpi_hest_t *hest, uintptr_t current, void *log_mem)
+{
+	hest->error_source_count = 0;
+	return current;
+}

From 743e31939c8716eccb6fb6a2445a0406476ebc98 Mon Sep 17 00:00:00 2001
From: Maximilian Brune <maximilian.brune@9elements.com>
Date: Sun, 2 Nov 2025 23:11:16 +0100
Subject: [PATCH 2603/3886] drivers/intel/fsp2_0/.../fsp/upd.h: Fix excess
 endif

There is one too many `endif` in this file. The only reason why jenkins
never complained is because this is apparently never included (and
therefore never compiled) by any code/mainboard in our tree.

Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: Id68d91d5c5365000fc97815d184d48f4b71bcb35
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89869
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
---
 src/drivers/intel/fsp2_0/include/fsp/upd.h | 1 -
 1 file changed, 1 deletion(-)

diff --git a/src/drivers/intel/fsp2_0/include/fsp/upd.h b/src/drivers/intel/fsp2_0/include/fsp/upd.h
index 827c95d980..153b174cc3 100644
--- a/src/drivers/intel/fsp2_0/include/fsp/upd.h
+++ b/src/drivers/intel/fsp2_0/include/fsp/upd.h
@@ -58,7 +58,6 @@ struct FSPM_ARCH_UPD {
 #error You need to implement this struct for x86_64 FSP
 #endif
 
-#endif
 struct FSPS_ARCH_UPD {
 	///
 	/// Revision of the structure. For FSP v2.2 value is 1.

From 31f44f55211b3ca7607b4d8b6b1acd96b074a058 Mon Sep 17 00:00:00 2001
From: Payne Lin <payne.lin@mediatek.corp-partner.google.com>
Date: Mon, 17 Nov 2025 21:48:34 +0800
Subject: [PATCH 2604/3886] mipi: Add DSC configuration and rate control
 parameters to panel header

This patch adds the Display Stream Compression (DSC) related structures
to the panel header. These structures define the rate control parameters
and configuration options required by the DSC engine for frame
compression, such as quantization parameter ranges, bits per group
offset, compression enable flag, dual DSC support, and line buffer
depth.

BUG=b:424782827
TEST=Build pass, boot ok, display ok

Change-Id: Icec24f55b962cd2794a79a68fc8fecec43300103
Signed-off-by: Payne Lin <payne.lin@mediatek.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90129
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/include/mipi/panel.h | 186 +++++++++++++++++++++++++++++++++++++++
 1 file changed, 186 insertions(+)

diff --git a/src/include/mipi/panel.h b/src/include/mipi/panel.h
index cc5a065d02..938f87dc3b 100644
--- a/src/include/mipi/panel.h
+++ b/src/include/mipi/panel.h
@@ -26,6 +26,191 @@ struct panel_init_command {
 	u8 data[];
 };
 
+/* VESA Display Stream Compression DSC 1.2 constants */
+#define DSC_NUM_BUF_RANGES			15
+
+/*
+ * struct dsc_rc_range_parameters - DSC Rate Control range parameters
+ *
+ * This defines different rate control parameters used by the DSC engine
+ * to compress the frame.
+ */
+struct dsc_rc_range_parameters {
+	/*
+	 * @range_min_qp: Min Quantization Parameters allowed for this range
+	 */
+	u8 range_min_qp;
+	/*
+	 * @range_max_qp: Max Quantization Parameters allowed for this range
+	 */
+	u8 range_max_qp;
+	/*
+	 * @range_bpg_offset:
+	 * Bits/group offset to apply to target for this group
+	 */
+	u8 range_bpg_offset;
+};
+
+struct dsc_config {
+	/*
+	 * @convert_rgb:
+	 * Flag to indicate if RGB - YCoCg conversion is needed
+	 * True if RGB input, False if YCoCg input
+	 */
+	u8 convert_rgb : 1;
+		/*
+	 * @simple_422: True if simple 4_2_2 mode is enabled else False
+	 */
+	u8 simple_422 : 1;
+	/*
+	 * @block_pred_enable:
+	 * True if block prediction is used to code any groups within the
+	 * picture. False if BP not used
+	 */
+	u8 block_pred_enable : 1;
+	/*
+	 * @line_buf_depth:
+	 * Bits per component for previous reconstructed line buffer
+	 */
+	u8 line_buf_depth;
+	/*
+	 * @bits_per_component: Bits per component to code (8/10/12)
+	 */
+	u8 bits_per_component;
+	/*
+	 *  @slice_width: Width of each slice in pixels
+	 */
+	u16 slice_width;
+	/*
+	 * @slice_height: Slice height in pixels
+	 */
+	u16 slice_height;
+	/*
+	 * @pic_width: Width of the input display frame in pixels
+	 */
+	u16 pic_width;
+	/*
+	 * @pic_height: Vertical height of the input display frame
+	 */
+	u16 pic_height;
+	/*
+	 * @rc_tgt_offset_high:
+	 * Offset to bits/group used by RC to determine QP adjustment
+	 */
+	u8 rc_tgt_offset_high;
+	/*
+	 * @rc_tgt_offset_low:
+	 * Offset to bits/group used by RC to determine QP adjustment
+	 */
+	u8 rc_tgt_offset_low;
+	/*
+	 * @bits_per_pixel:
+	 * Target bits per pixel with 4 fractional bits, bits_per_pixel << 4
+	 */
+	u16 bits_per_pixel;
+	/*
+	 * @rc_edge_factor:
+	 * Factor to determine if an edge is present based on the bits produced
+	 */
+	u8 rc_edge_factor;
+	/*
+	 * @rc_quant_incr_limit1:
+	 * Slow down incrementing once the range reaches this value
+	 */
+	u8 rc_quant_incr_limit1;
+	/*
+	 * @rc_quant_incr_limit0:
+	 * Slow down incrementing once the range reaches this value
+	 */
+	u8 rc_quant_incr_limit0;
+	/*
+	 * @initial_xmit_delay:
+	 * Number of pixels to delay the initial transmission
+	 */
+	u16 initial_xmit_delay;
+	/*
+	 * @initial_dec_delay:
+	 * Initial decoder delay, number of pixel times that the decoder
+	 * accumulates data in its rate buffer before starting to decode
+	 * and output pixels.
+	 */
+	u16 initial_dec_delay;
+	/*
+	 * @first_line_bpg_offset:
+	 * Number of additional bits allocated for each group on the first
+	 * line of slice.
+	 */
+	u8 first_line_bpg_offset;
+	/*
+	 * @initial_offset: Value to use for RC model offset at slice start
+	 */
+	u16 initial_offset;
+	/*
+	 * @rc_buf_thresh: Thresholds defining each of the buffer ranges
+	 */
+	u16 rc_buf_thresh[DSC_NUM_BUF_RANGES - 1];
+	/*
+	 * @rc_range_params:
+	 * Parameters for each of the RC ranges defined in
+	 * &struct dsc_rc_range_parameters
+	 */
+	struct dsc_rc_range_parameters rc_range_params[DSC_NUM_BUF_RANGES];
+	/*
+	 * @rc_model_size: Total size of RC model
+	 */
+	u16 rc_model_size;
+	/*
+	 * @flatness_min_qp: Minimum QP where flatness information is sent
+	 */
+	u8 flatness_min_qp;
+	/*
+	 * @flatness_max_qp: Maximum QP where flatness information is sent
+	 */
+	u8 flatness_max_qp;
+	/*
+	 * @initial_scale_value: Initial value for the scale factor
+	 */
+	u8 initial_scale_value;
+	/*
+	 * @scale_decrement_interval:
+	 * Specifies number of group times between decrementing the scale factor
+	 * at beginning of a slice.
+	 */
+	u16 scale_decrement_interval;
+	/*
+	 * @scale_increment_interval:
+	 * Number of group times between incrementing the scale factor value
+	 * used at the beginning of a slice.
+	 */
+	u16 scale_increment_interval;
+	/*
+	 * @nfl_bpg_offset: Non first line BPG offset to be used
+	 */
+	u16 nfl_bpg_offset;
+	/*
+	 * @slice_bpg_offset: BPG offset used to enforce slice bit
+	 */
+	u16 slice_bpg_offset;
+	/*
+	 * @final_offset: Final RC linear transformation offset value
+	 */
+	u16 final_offset;
+	/*
+	 * @slice_chunk_size:
+	 * The (max) size in bytes of the "chunks" that are used in slice
+	 * multiplexing.
+	 */
+	u16 slice_chunk_size;
+	/*
+	 * @dsc_version_minor: DSC minor version
+	 */
+	u8 dsc_version_minor;
+	/*
+	 * @dsc_version_major: DSC major version
+	 */
+	u8 dsc_version_major;
+};
+
 /*
  * The data to be serialized and put into CBFS.
  * Note some fields, for example edid.mode.name, were actually pointers and
@@ -34,6 +219,7 @@ struct panel_init_command {
 struct panel_serializable_data {
 	u32 flags; /* flags of panel_flag */
 	struct edid edid;  /* edid info of this panel */
+	struct dsc_config dsc_config; /* dsc config of this panel */
 	u8 init[]; /* A packed array of panel_init_command */
 };
 

From 864e3ca66145e91fdab77378cd1f011c44ba5954 Mon Sep 17 00:00:00 2001
From: Uwe Poeche <uwe.poeche@siemens.com>
Date: Wed, 9 Jul 2025 11:49:11 +0200
Subject: [PATCH 2605/3886] mb/siemens/mc_ehl6: Adjust I2C setup

Adapt I2C controller configuration for mc_ehl6 board. This involves
changes to the coreboot I2C setup. To prevent higher I2C speeds from
being used by the OS, dummy devices are installed on the I2C bus.

TEST=Check if drivers for the I2C devices started correctly during
coreboot execution and verify that all I2C devices are detected in the
OS.

Change-Id: I6de578f969456a15807a1380209ea18e01f522bd
Signed-off-by: Uwe Poeche <uwe.poeche@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90083
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
---
 .../mc_ehl/variants/mc_ehl6/devicetree.cb     | 68 ++++++++++---------
 1 file changed, 37 insertions(+), 31 deletions(-)

diff --git a/src/mainboard/siemens/mc_ehl/variants/mc_ehl6/devicetree.cb b/src/mainboard/siemens/mc_ehl/variants/mc_ehl6/devicetree.cb
index 1e5bd881c0..2e7f0c0a72 100644
--- a/src/mainboard/siemens/mc_ehl/variants/mc_ehl6/devicetree.cb
+++ b/src/mainboard/siemens/mc_ehl/variants/mc_ehl6/devicetree.cb
@@ -78,16 +78,23 @@ chip soc/intel/elkhartlake
 
 	# LPSS Serial IO (I2C/UART/GSPI) related UPDs
 	register "SerialIoI2cMode" = "{
-		[PchSerialIoIndexI2C0] = PchSerialIoPci,
+		[PchSerialIoIndexI2C0] = PchSerialIoDisabled,
 		[PchSerialIoIndexI2C1] = PchSerialIoPci,
 		[PchSerialIoIndexI2C2] = PchSerialIoPci,
-		[PchSerialIoIndexI2C3] = PchSerialIoPci,
+		[PchSerialIoIndexI2C3] = PchSerialIoDisabled,
 		[PchSerialIoIndexI2C4] = PchSerialIoPci,
-		[PchSerialIoIndexI2C5] = PchSerialIoPci,
-		[PchSerialIoIndexI2C6] = PchSerialIoDisabled,
+		[PchSerialIoIndexI2C5] = PchSerialIoDisabled,
+		[PchSerialIoIndexI2C6] = PchSerialIoPci,
 		[PchSerialIoIndexI2C7] = PchSerialIoDisabled,
 	}"
 
+	register "SerialIoI2cPadsTermination" = "{
+		[PchSerialIoIndexI2C1] = 1,
+		[PchSerialIoIndexI2C2] = 1,
+		[PchSerialIoIndexI2C4] = 1,
+		[PchSerialIoIndexI2C6] = 1,
+        }"
+
 	register "SerialIoUartMode" = "{
 		[PchSerialIoIndexUART0] = PchSerialIoPci,
 		[PchSerialIoIndexUART1] = PchSerialIoPci,
@@ -109,26 +116,6 @@ chip soc/intel/elkhartlake
 	register "pse_tsn_phy_irq_edge[0]" = "RISING_EDGE"
 	register "pse_tsn_phy_irq_edge[1]" = "RISING_EDGE"
 
-	register "common_soc_config" = "{
-		.i2c[1] = {
-			.speed = I2C_SPEED_STANDARD,
-			.speed_config[0] = {
-				.speed = I2C_SPEED_STANDARD,
-				.scl_hcnt = 0x1e1,
-				.scl_lcnt = 0x1f4,
-				.sda_hold = 0x64
-			},
-		},
-		.i2c[2] = {
-			.speed = I2C_SPEED_STANDARD,
-			.speed_config[0] = {
-				.speed = I2C_SPEED_STANDARD,
-				.scl_hcnt = 0x1df,
-				.scl_lcnt = 0x1f4,
-				.sda_hold = 0x64
-			},
-		},
-	}"
 
 	# FIVR related settings
 	register "fivr" = "{
@@ -146,9 +133,17 @@ chip soc/intel/elkhartlake
 		device pci 00.0 on	end # Host Bridge
 		device pci 02.0 on	end # Integrated Graphics Device
 
+		device pci 10.0 on	    # I2C6
+			# Add dummy I2C device to limit BUS speed to 100 kHz in OS
+			chip drivers/i2c/generic
+				register "hid" = ""PRP0001""
+				register "speed" = "I2C_SPEED_STANDARD"
+				device i2c 0x7f on end
+			end
+		end
+
 		device pci 14.0 on	end # USB3.1 xHCI
 
-		device pci 15.0 on	end # I2C0
 		device pci 15.1 on	    # I2C1
 			# Enable external RTC chip
 			chip drivers/i2c/rv3028c7
@@ -162,21 +157,32 @@ chip soc/intel/elkhartlake
 				register "cap_charge" = "CHARGE_OFF"
 				device i2c 0x52 on end  # RTC RV3028-C7
 			end
-		end
-		device pci 15.2 on	    # I2C2
-		# Add dummy I2C device to limit BUS speed to 100 kHz in OS
+			# Add dummy I2C device to limit BUS speed to 100 kHz in OS
+			chip drivers/i2c/generic
+				register "hid" = ""PRP0001""
+				register "speed" = "I2C_SPEED_STANDARD"
+				device i2c 0x7f on end
+			end
+		end
+		device pci 15.2 on	    # I2C2
+			# Add dummy I2C device to limit BUS speed to 100 kHz in OS
 			chip drivers/i2c/generic
 				register "hid" = ""PRP0001""
 				register "speed" = "I2C_SPEED_STANDARD"
 				device i2c 0x7f on end
 			end
 		end
-		device pci 15.3 on	end # I2C3
 
 		device pci 16.0 hidden	end # Management Engine Interface 1
 
-		device pci 19.0 on	end # I2C4
-		device pci 19.1 on	end # I2C5
+		device pci 19.0 on	    # I2C4
+			# Add dummy I2C device to limit BUS speed to 100 kHz in OS
+			chip drivers/i2c/generic
+				register "hid" = ""PRP0001""
+				register "speed" = "I2C_SPEED_STANDARD"
+				device i2c 0x7f on end
+			end
+		end
 		device pci 19.2 on	end # UART2
 
 		device pci 1a.0 on	end # eMMC

From 43d5f7057632346b3a5956866c94b6d5e49a1d89 Mon Sep 17 00:00:00 2001
From: Uwe Poeche <uwe.poeche@siemens.com>
Date: Thu, 10 Jul 2025 13:08:19 +0200
Subject: [PATCH 2606/3886] mb/siemens/mc_ehl6: Enable PTM for all enabled PCIe
 RPs

Enable PCIe PTM (Precision Time Measurement) for all enabled PCIe root
ports. The time synchronization is mainly necessary for stable timing to
PLC.

TEST
Boot in a standard linux OS and check if PTM ist enabled for active RPs
via lspci -vv -s 00:1c.0..6 | grep PTM

Change-Id: I965ab349c07158d0c69b9112571aa98575eada77
Signed-off-by: Uwe Poeche <uwe.poeche@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90084
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kilian Krause <kilian.krause@siemens.com>
---
 .../siemens/mc_ehl/variants/mc_ehl6/devicetree.cb          | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/src/mainboard/siemens/mc_ehl/variants/mc_ehl6/devicetree.cb b/src/mainboard/siemens/mc_ehl/variants/mc_ehl6/devicetree.cb
index 2e7f0c0a72..9b21d381e0 100644
--- a/src/mainboard/siemens/mc_ehl/variants/mc_ehl6/devicetree.cb
+++ b/src/mainboard/siemens/mc_ehl/variants/mc_ehl6/devicetree.cb
@@ -68,6 +68,13 @@ chip soc/intel/elkhartlake
 	register "PcieRpLtrDisable[4]" = "true"
 	register "PcieRpLtrDisable[6]" = "true"
 
+	# Enable PCIe PTM (Precision Time Measurement) for all PCIe root ports
+	register "PciePtm[0]" = "true"
+	register "PciePtm[1]" = "true"
+	register "PciePtm[2]" = "true"
+	register "PciePtm[4]" = "true"
+	register "PciePtm[6]" = "true"
+
 	# Storage (SDCARD/EMMC) related UPDs
 	register "ScsEmmcHs400Enabled" = "0"
 	register "ScsEmmcDdr50Enabled" = "1"

From e19f2b313e2dfb155b48d25af3c8b9e73e7216b9 Mon Sep 17 00:00:00 2001
From: Uwe Poeche <uwe.poeche@siemens.com>
Date: Mon, 14 Jul 2025 15:43:37 +0200
Subject: [PATCH 2607/3886] mb/siemens/mc_ehl6: Enable PCHHOT_N via GPIO

This mainboard uses native function two of GPIO B23 (PCHHOT_N) to
realise overtemperature behaviour of the mainboard.

TEST=Check the signal during HW commissioning and influence of heat to
the CPU.

Change-Id: I4caa88316d5027f7b9d74293a74377915f274766
Signed-off-by: Uwe Poeche <uwe.poeche@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90085
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-by: Kilian Krause <kilian.krause@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/siemens/mc_ehl/variants/mc_ehl6/gpio.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/mainboard/siemens/mc_ehl/variants/mc_ehl6/gpio.c b/src/mainboard/siemens/mc_ehl/variants/mc_ehl6/gpio.c
index 63a13bba7b..7e68cf9a6b 100644
--- a/src/mainboard/siemens/mc_ehl/variants/mc_ehl6/gpio.c
+++ b/src/mainboard/siemens/mc_ehl/variants/mc_ehl6/gpio.c
@@ -16,7 +16,7 @@ static const struct pad_config gpio_table[] = {
 	PAD_NC(GPP_B15, NONE),				/* Not connected */
 	PAD_NC(GPP_B18, NONE),				/* Not connected */
 	PAD_NC(GPP_B19, NONE),				/* Not connected */
-	PAD_NC(GPP_B23, NONE),				/* Not connected */
+	PAD_CFG_NF(GPP_B23, NONE, PLTRST, NF2),		/* PCHHOT_N */
 
 	/* Community 0 - GpioGroup GPP_T */
 	PAD_CFG_NF(GPP_T4, NONE, DEEP, NF1),		/* PSE_GBE0_INT */

From aad2b715ea75ea937172314933433336cc151f51 Mon Sep 17 00:00:00 2001
From: Uwe Poeche <uwe.poeche@siemens.com>
Date: Tue, 15 Jul 2025 08:18:45 +0200
Subject: [PATCH 2608/3886] mb/siemens/mc_ehl6: Remove PSE GbE 1

Remove the unused PSE TSN GbE device #1. This device is not
required for the current board functionality and removing it
simplifies the configuration.

TEST=Check if all other GbE ports of mainboard still work.

Change-Id: I8b23064ecff5fe67da3d847bb769784f8b3a15cc
Signed-off-by: Uwe Poeche <uwe.poeche@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90086
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-by: Kilian Krause <kilian.krause@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 .../mc_ehl/variants/mc_ehl6/devicetree.cb     | 21 -------------------
 .../siemens/mc_ehl/variants/mc_ehl6/gpio.c    | 18 ----------------
 2 files changed, 39 deletions(-)

diff --git a/src/mainboard/siemens/mc_ehl/variants/mc_ehl6/devicetree.cb b/src/mainboard/siemens/mc_ehl/variants/mc_ehl6/devicetree.cb
index 9b21d381e0..b549276b35 100644
--- a/src/mainboard/siemens/mc_ehl/variants/mc_ehl6/devicetree.cb
+++ b/src/mainboard/siemens/mc_ehl/variants/mc_ehl6/devicetree.cb
@@ -118,10 +118,8 @@ chip soc/intel/elkhartlake
 	register "PchTsnGbeLinkSpeed" = "Tsn_1_Gbps"
 	register "PchTsnGbeSgmiiEnable" = "1"
 	register "PseDmaOwn[0]" = "Host_Owned"
-	register "PseDmaOwn[1]" = "Host_Owned"
 	register "pch_tsn_phy_irq_edge" = "RISING_EDGE"
 	register "pse_tsn_phy_irq_edge[0]" = "RISING_EDGE"
-	register "pse_tsn_phy_irq_edge[1]" = "RISING_EDGE"
 
 
 	# FIVR related settings
@@ -221,25 +219,6 @@ chip soc/intel/elkhartlake
 				end
 			end
 		end
-		device pci 1d.2 on	    # Intel PSE Time-Sensitive Networking GbE 1
-			# Enable external Marvell PHY 88E1512
-			chip drivers/net/phy/m88e1512
-				register "configure_leds" = "true"
-				# LED[0]: On - 1000 Mbps Link, Off - Else
-				register "led_0_ctrl" = "7"
-				# LED[1]: On - Link, Blink - Activity, Off - No Link
-				register "led_1_ctrl" = "1"
-				# INTn is routed to LED[2] pin
-				register "enable_int" = "true"
-				register "downshift_cnt" = "2"
-				register "force_mos" = "true"
-				register "pmos_val" = "0xF"
-				register "nmos_val" = "0xA"
-				device mdio 1 on    # PHY address
-					ops m88e1512_ops
-				end
-			end
-		end
 
 		device pci 1e.0 on	end # UART0
 		device pci 1e.1 on	end # UART1
diff --git a/src/mainboard/siemens/mc_ehl/variants/mc_ehl6/gpio.c b/src/mainboard/siemens/mc_ehl/variants/mc_ehl6/gpio.c
index 7e68cf9a6b..f23ac25ce3 100644
--- a/src/mainboard/siemens/mc_ehl/variants/mc_ehl6/gpio.c
+++ b/src/mainboard/siemens/mc_ehl/variants/mc_ehl6/gpio.c
@@ -46,10 +46,6 @@ static const struct pad_config gpio_table[] = {
 	PAD_CFG_NF(GPP_V11, NONE, DEEP, NF1),		/* EMMC_RESET */
 
 	/* Community 1 - GpioGroup GPP_H */
-	PAD_CFG_NF(GPP_H0, NONE, DEEP, NF1),		/* PSE_GBE1_INT */
-	PAD_CFG_GPO(GPP_H1, 1, DEEP),			/* PSE_GBE1_RST_N */
-	PAD_CFG_NF(GPP_H2, NONE, DEEP, NF1),		/* PSE_GBE1_AUXTS */
-	PAD_CFG_NF(GPP_H3, NONE, DEEP, NF1),		/* PSE_GBE1_PPS */
 	PAD_CFG_NF(GPP_H10, NONE, DEEP, NF1),		/* PCIE_CLKREQ4_N */
 	PAD_CFG_NF(GPP_H11, NONE, DEEP, NF1),		/* PCIE_CLKREQ5_N */
 
@@ -89,25 +85,11 @@ static const struct pad_config gpio_table[] = {
 	PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1),		/* PSE_GBE0_RGMII_RXD2 */
 	PAD_CFG_NF(GPP_A9, NONE, DEEP, NF1),		/* PSE_GBE0_RGMII_RXD1 */
 	PAD_CFG_NF(GPP_A10, NONE, DEEP, NF1),		/* PSE_GBE0_RGMII_RXD0 */
-	PAD_CFG_NF(GPP_A11, NONE, DEEP, NF1),		/* PSE_GBE1_RGMII_TXD3 */
-	PAD_CFG_NF(GPP_A12, NONE, DEEP, NF1),		/* PSE_GBE1_RGMII_TXD2 */
-	PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1),		/* PSE_GBE1_RGMII_TXD1 */
-	PAD_CFG_NF(GPP_A14, NONE, DEEP, NF1),		/* PSE_GBE1_RGMII_TXD0 */
-	PAD_CFG_NF(GPP_A15, NONE, DEEP, NF1),		/* PSE_GBE1_RGMII_TXCLK */
-	PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1),		/* PSE_GBE1_RGMII_TXCTL */
-	PAD_CFG_NF(GPP_A17, NONE, DEEP, NF1),		/* PSE_GBE1_RGMII_RXCLK */
-	PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1),		/* PSE_GBE1_RGMII_RXCTL */
-	PAD_CFG_NF(GPP_A19, NONE, DEEP, NF1),		/* PSE_GBE1_RGMII_RXD3 */
-	PAD_CFG_NF(GPP_A20, NONE, DEEP, NF1),		/* PSE_GBE1_RGMII_RXD2 */
-	PAD_CFG_NF(GPP_A21, NONE, DEEP, NF1),		/* PSE_GBE1_RGMII_RXD1 */
-	PAD_CFG_NF(GPP_A22, NONE, DEEP, NF1),		/* PSE_GBE1_RGMII_RXD0 */
 	PAD_CFG_NF(GPP_A23, NONE, DEEP, NF1),		/* PSE_GBE0_RGMII_RXCTL */
 
 	/* Community 4 - GpioGroup GPP_C */
 	PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1),		/* PSE_GBE0_MDC */
 	PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1),		/* PSE_GBE0_MDIO */
-	PAD_CFG_NF(GPP_C6, NONE, DEEP, NF1),		/* PSE_GBE1_MDC */
-	PAD_CFG_NF(GPP_C7, NONE, DEEP, NF1),		/* PSE_GBE1_MDIO */
 	PAD_NC(GPP_C8, NONE),				/* Not connected */
 	PAD_CFG_NF(GPP_C12, NONE, DEEP, NF4),		/* SIO_UART1_RXD */
 	PAD_CFG_NF(GPP_C13, NONE, DEEP, NF4),		/* SIO_UART1_TXD */

From b6e7f3e005cba2cd3775d32e228997f53abe52f6 Mon Sep 17 00:00:00 2001
From: Uwe Poeche <uwe.poeche@siemens.com>
Date: Tue, 15 Jul 2025 10:29:46 +0200
Subject: [PATCH 2609/3886] mb/siemens/mc_ehl6: Change GbE LED settings

This patch changes the LED settings for used Marvell PHY 88E1512 driver
of PSE GbE 0 and PCH GbE on mc_ehl6 mainboard.
The interrupt functionality on Marvell PHY 88E1512 is not used in the
OS for this board. In this Phy the interrupt is multiplexed with LED[2]
Pin.

On mc_ehl6 mainboard LED Pins [0/1/2] are used.
- LED Pins [0/1] for two color LINK LED at the interface
- LED[2] for ACT LED
Driver parameters are set accordingly.

TEST=Boot into OS and check LINK and ACT LED at the related plugs at
100 and 1000 Mbit mode.

Change-Id: If7fd314034b35de67fc0b10e6be9b7578807cbff
Signed-off-by: Uwe Poeche <uwe.poeche@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90087
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
---
 .../mc_ehl/variants/mc_ehl6/devicetree.cb     | 22 ++++++++++---------
 1 file changed, 12 insertions(+), 10 deletions(-)

diff --git a/src/mainboard/siemens/mc_ehl/variants/mc_ehl6/devicetree.cb b/src/mainboard/siemens/mc_ehl/variants/mc_ehl6/devicetree.cb
index b549276b35..d1e5debf4f 100644
--- a/src/mainboard/siemens/mc_ehl/variants/mc_ehl6/devicetree.cb
+++ b/src/mainboard/siemens/mc_ehl/variants/mc_ehl6/devicetree.cb
@@ -118,8 +118,6 @@ chip soc/intel/elkhartlake
 	register "PchTsnGbeLinkSpeed" = "Tsn_1_Gbps"
 	register "PchTsnGbeSgmiiEnable" = "1"
 	register "PseDmaOwn[0]" = "Host_Owned"
-	register "pch_tsn_phy_irq_edge" = "RISING_EDGE"
-	register "pse_tsn_phy_irq_edge[0]" = "RISING_EDGE"
 
 
 	# FIVR related settings
@@ -206,10 +204,12 @@ chip soc/intel/elkhartlake
 				register "configure_leds" = "true"
 				# LED[0]: On - 1000 Mbps Link, Off - Else
 				register "led_0_ctrl" = "7"
-				# LED[1]: On - Link, Blink - Activity, Off - No Link
-				register "led_1_ctrl" = "1"
-				# INTn is routed to LED[2] pin
-				register "enable_int" = "true"
+				# LED[1]: On - 100 Mbps Link, Off - Else
+				register "led_1_ctrl" = "7"
+				# LED[2]: Blink - Activity, Off - No Activity
+				register "led_2_ctrl" = "4"
+				# INTn is not routed to LED[2] pin
+				register "enable_int" = "false"
 				register "downshift_cnt" = "2"
 				register "force_mos" = "true"
 				register "pmos_val" = "0xF"
@@ -228,10 +228,12 @@ chip soc/intel/elkhartlake
 				register "configure_leds" = "true"
 				# LED[0]: On - 1000 Mbps Link, Off - Else
 				register "led_0_ctrl" = "7"
-				# LED[1]: On - Link, Blink - Activity, Off - No Link
-				register "led_1_ctrl" = "1"
-				# INTn is routed to LED[2] pin
-				register "enable_int" = "true"
+				# LED[1]: On - 100 Mbps Link, Off - Else
+				register "led_1_ctrl" = "7"
+				# LED[2]: Blink - Activity, Off - No Activity
+				register "led_2_ctrl" = "4"
+				# INTn is not routed to LED[2] pin
+				register "enable_int" = "false"
 				register "downshift_cnt" = "2"
 				device mdio 1 on    # PHY address
 					ops m88e1512_ops

From 54f2652bde037b111e146818f4cf07f3e60e9048 Mon Sep 17 00:00:00 2001
From: Uwe Poeche <uwe.poeche@siemens.com>
Date: Tue, 15 Jul 2025 10:47:10 +0200
Subject: [PATCH 2610/3886] mb/siemens/mc_ehl6: Enable auto impedance
 calibration on GbE 0

Use the default automatic RGMII Output Impedance Calibration on Marvell
PHY 88E1512 by using default coreboot driver parameters.

TEST=Check signal integrity on RGMII interface on mc_ehl6 mainboard.

Change-Id: I6b6d7aeb8ddc4ef4ed297f4147b87d3e81c8a37e
Signed-off-by: Uwe Poeche <uwe.poeche@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90088
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kilian Krause <kilian.krause@siemens.com>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
---
 src/mainboard/siemens/mc_ehl/variants/mc_ehl6/devicetree.cb | 3 ---
 1 file changed, 3 deletions(-)

diff --git a/src/mainboard/siemens/mc_ehl/variants/mc_ehl6/devicetree.cb b/src/mainboard/siemens/mc_ehl/variants/mc_ehl6/devicetree.cb
index d1e5debf4f..f035c4adfd 100644
--- a/src/mainboard/siemens/mc_ehl/variants/mc_ehl6/devicetree.cb
+++ b/src/mainboard/siemens/mc_ehl/variants/mc_ehl6/devicetree.cb
@@ -211,9 +211,6 @@ chip soc/intel/elkhartlake
 				# INTn is not routed to LED[2] pin
 				register "enable_int" = "false"
 				register "downshift_cnt" = "2"
-				register "force_mos" = "true"
-				register "pmos_val" = "0xF"
-				register "nmos_val" = "0xA"
 				device mdio 0 on    # PHY address
 					ops m88e1512_ops
 				end

From 760c3f6abc9bcb6c3b8897a3184933900e131bd6 Mon Sep 17 00:00:00 2001
From: Uwe Poeche <uwe.poeche@siemens.com>
Date: Tue, 15 Jul 2025 13:23:32 +0200
Subject: [PATCH 2611/3886] mb/siemens/mc_ehl6: Activate SATA interface port 1

Activate SATA interface port 1 for mass storage connection on mc_ehl6
mainboard.
Function of SATA_LED_N and M.2_SSD_SATA_DEVSLP_1 are not used.

TEST=Check mass storage in running OS.

Change-Id: I34ca0d71a04c4338e35bcf9ede4ccef41efab01e
Signed-off-by: Uwe Poeche <uwe.poeche@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90089
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
---
 .../siemens/mc_ehl/variants/mc_ehl6/devicetree.cb     | 11 +++++++++--
 src/mainboard/siemens/mc_ehl/variants/mc_ehl6/gpio.c  |  2 --
 2 files changed, 9 insertions(+), 4 deletions(-)

diff --git a/src/mainboard/siemens/mc_ehl/variants/mc_ehl6/devicetree.cb b/src/mainboard/siemens/mc_ehl/variants/mc_ehl6/devicetree.cb
index f035c4adfd..c6861401c0 100644
--- a/src/mainboard/siemens/mc_ehl/variants/mc_ehl6/devicetree.cb
+++ b/src/mainboard/siemens/mc_ehl/variants/mc_ehl6/devicetree.cb
@@ -75,7 +75,13 @@ chip soc/intel/elkhartlake
 	register "PciePtm[4]" = "true"
 	register "PciePtm[6]" = "true"
 
-	# Storage (SDCARD/EMMC) related UPDs
+	# Storage (SATA/SDCARD/EMMC) related UPDs
+	register "SataSalpSupport" = "0"
+	register "SataPortsEnable[1]" = "1"
+	register "SataPortsDevSlp[1]" = "0"
+	register "SataPortsSSD[1]" = "1"
+	register "SataSpeed" = "SATA_GEN2"
+
 	register "ScsEmmcHs400Enabled" = "0"
 	register "ScsEmmcDdr50Enabled" = "1"
 	register "SdCardPowerEnableActiveHigh" = "1"
@@ -119,7 +125,6 @@ chip soc/intel/elkhartlake
 	register "PchTsnGbeSgmiiEnable" = "1"
 	register "PseDmaOwn[0]" = "Host_Owned"
 
-
 	# FIVR related settings
 	register "fivr" = "{
 		.fivr_config_en = true,
@@ -178,6 +183,8 @@ chip soc/intel/elkhartlake
 
 		device pci 16.0 hidden	end # Management Engine Interface 1
 
+		device pci 17.0 on      end # SATA
+
 		device pci 19.0 on	    # I2C4
 			# Add dummy I2C device to limit BUS speed to 100 kHz in OS
 			chip drivers/i2c/generic
diff --git a/src/mainboard/siemens/mc_ehl/variants/mc_ehl6/gpio.c b/src/mainboard/siemens/mc_ehl/variants/mc_ehl6/gpio.c
index f23ac25ce3..49f737b868 100644
--- a/src/mainboard/siemens/mc_ehl/variants/mc_ehl6/gpio.c
+++ b/src/mainboard/siemens/mc_ehl/variants/mc_ehl6/gpio.c
@@ -110,8 +110,6 @@ static const struct pad_config gpio_table[] = {
 	PAD_CFG_GPO(GPP_F20, 0, DEEP),			/* LED_BIOS_DONE */
 
 	/* Community 4 - GpioGroup GPP_E */
-	PAD_CFG_NF(GPP_E0, NONE, DEEP, NF1),		/* SATA_LED_N */
-	PAD_CFG_NF(GPP_E8, NONE, DEEP, NF2),		/* M.2_SSD_SATA_DEVSLP_1 */
 	PAD_NC(GPP_E15, NONE),				/* Not connected */
 	PAD_NC(GPP_E16, NONE),				/* Not connected */
 	PAD_NC(GPP_E18, NONE),				/* Not connected */

From fceb03337284c84fa14b7423dd9e2386dd9d07d1 Mon Sep 17 00:00:00 2001
From: Uwe Poeche <uwe.poeche@siemens.com>
Date: Mon, 29 Sep 2025 06:47:09 +0200
Subject: [PATCH 2612/3886] mb/siemens/mc_ehl6: Limit PCIe RP7 speed to Gen2

Configure PCIe root port 7 to operate at PCIe Gen2 speed to fulfill
mainboard constraints regarding signal integrity.

TEST=Check resulting transfer rate in OS via
`lspci -vv -s 06:00.0 | grep LnkSta`.
Output shows `LnkSta: Speed 5GT/s (downgraded), Width x2`

Change-Id: I7cb86f04675a850bf3c0a3e8af2436d929d5768b
Signed-off-by: Uwe Poeche <uwe.poeche@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90090
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-by: Kilian Krause <kilian.krause@siemens.com>
---
 src/mainboard/siemens/mc_ehl/variants/mc_ehl6/devicetree.cb | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/src/mainboard/siemens/mc_ehl/variants/mc_ehl6/devicetree.cb b/src/mainboard/siemens/mc_ehl/variants/mc_ehl6/devicetree.cb
index c6861401c0..5180770908 100644
--- a/src/mainboard/siemens/mc_ehl/variants/mc_ehl6/devicetree.cb
+++ b/src/mainboard/siemens/mc_ehl/variants/mc_ehl6/devicetree.cb
@@ -75,6 +75,9 @@ chip soc/intel/elkhartlake
 	register "PciePtm[4]" = "true"
 	register "PciePtm[6]" = "true"
 
+	# Determine PCIe root port speed
+	register "PcieRpPcieSpeed[6]" = "2"
+
 	# Storage (SATA/SDCARD/EMMC) related UPDs
 	register "SataSalpSupport" = "0"
 	register "SataPortsEnable[1]" = "1"

From 1a11dca12dffa6ce34915b8db2e18ec7862c10f1 Mon Sep 17 00:00:00 2001
From: Uwe Poeche <uwe.poeche@siemens.com>
Date: Tue, 11 Nov 2025 09:47:34 +0100
Subject: [PATCH 2613/3886] mb/siemens/mc_ehl6: Send POST codes to NC FPGA via
 PCI

Enable the feature to send POST codes to the NC FPGA via PCI. This
allows the POST codes to be visible on the embedded 7-segment display
during coreboot runtime.
Further sort switches in alphabetical order.

TEST=Build and boot mc_ehl6. Verify that the POST Codes are
correctly displayed on the embedded 7-segment display.

Change-Id: Ie7e4961c0345312126eb2000c2934e33fce3b584
Signed-off-by: Uwe Poeche <uwe.poeche@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90091
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
---
 .../siemens/mc_ehl/variants/mc_ehl6/Kconfig      | 16 ++++++++++++++++
 .../siemens/mc_ehl/variants/mc_ehl6/Makefile.mk  |  2 ++
 .../siemens/mc_ehl/variants/mc_ehl6/post.c       | 10 ++++++++++
 3 files changed, 28 insertions(+)
 create mode 100644 src/mainboard/siemens/mc_ehl/variants/mc_ehl6/post.c

diff --git a/src/mainboard/siemens/mc_ehl/variants/mc_ehl6/Kconfig b/src/mainboard/siemens/mc_ehl/variants/mc_ehl6/Kconfig
index 8ebeec9679..c8cd345d7a 100644
--- a/src/mainboard/siemens/mc_ehl/variants/mc_ehl6/Kconfig
+++ b/src/mainboard/siemens/mc_ehl/variants/mc_ehl6/Kconfig
@@ -11,6 +11,7 @@ config BOARD_SPECIFIC_OPTIONS
 	select DRIVERS_ETH_PHY_M88E1512
 	select MAINBOARD_HAS_TPM2
 	select MEMORY_MAPPED_TPM
+	select NC_FPGA_POST_CODE
 	select TPM_MEASURED_BOOT
 	select TPM_MEASURED_BOOT_INIT_BOOTBLOCK
 
@@ -21,4 +22,19 @@ config UART_FOR_CONSOLE
 	int
 	default 0
 
+config EARLY_PCI_BRIDGE_DEVICE
+	hex
+	depends on NC_FPGA_POST_CODE
+	default 0x1c
+
+config EARLY_PCI_BRIDGE_FUNCTION
+	hex
+	depends on NC_FPGA_POST_CODE
+	default 0x0
+
+config EARLY_PCI_MMIO_BASE
+	hex
+	depends on NC_FPGA_POST_CODE
+	default 0xfe800000
+
 endif # BOARD_SIEMENS_MC_EHL6
diff --git a/src/mainboard/siemens/mc_ehl/variants/mc_ehl6/Makefile.mk b/src/mainboard/siemens/mc_ehl/variants/mc_ehl6/Makefile.mk
index 6e87f9fc1a..d9050f098d 100644
--- a/src/mainboard/siemens/mc_ehl/variants/mc_ehl6/Makefile.mk
+++ b/src/mainboard/siemens/mc_ehl/variants/mc_ehl6/Makefile.mk
@@ -4,3 +4,5 @@ bootblock-y += gpio.c
 romstage-y += memory.c
 ramstage-y += gpio.c
 ramstage-y += mainboard.c
+
+all-$(CONFIG_NC_FPGA_POST_CODE) += post.c
diff --git a/src/mainboard/siemens/mc_ehl/variants/mc_ehl6/post.c b/src/mainboard/siemens/mc_ehl/variants/mc_ehl6/post.c
new file mode 100644
index 0000000000..c34e2539bc
--- /dev/null
+++ b/src/mainboard/siemens/mc_ehl/variants/mc_ehl6/post.c
@@ -0,0 +1,10 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <console/console.h>
+#include <nc_fpga.h>
+#include <types.h>
+
+void mainboard_post(uint8_t value)
+{
+	nc_fpga_post(value);
+}

From 801795d4ddf23096c482dcb8b92a40cf68677a78 Mon Sep 17 00:00:00 2001
From: Uwe Poeche <uwe.poeche@siemens.com>
Date: Fri, 21 Nov 2025 13:48:45 +0100
Subject: [PATCH 2614/3886] mb/siemens/mc_ehl6: Alphabetize Kconfig options

Sort Kconfig select statements alphabetically for better readability
and maintainability.

No functional changes.

Change-Id: Iaa04c2666e16a2fc442a34d2be37ca3b0c567168
Signed-off-by: Uwe Poeche <uwe.poeche@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90146
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
---
 src/mainboard/siemens/mc_ehl/variants/mc_ehl6/Kconfig | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/src/mainboard/siemens/mc_ehl/variants/mc_ehl6/Kconfig b/src/mainboard/siemens/mc_ehl/variants/mc_ehl6/Kconfig
index c8cd345d7a..936a452065 100644
--- a/src/mainboard/siemens/mc_ehl/variants/mc_ehl6/Kconfig
+++ b/src/mainboard/siemens/mc_ehl/variants/mc_ehl6/Kconfig
@@ -4,14 +4,14 @@ if BOARD_SIEMENS_MC_EHL6
 
 config BOARD_SPECIFIC_OPTIONS
 	def_bool y
-	select DRIVERS_I2C_RV3028C7
 	select DRIVER_INTEL_I210
-	select SOC_INTEL_COMMON_BLOCK_LPC_COMB_ENABLE
-	select EHL_TSN_DRIVER
 	select DRIVERS_ETH_PHY_M88E1512
+	select DRIVERS_I2C_RV3028C7
+	select EHL_TSN_DRIVER
 	select MAINBOARD_HAS_TPM2
 	select MEMORY_MAPPED_TPM
 	select NC_FPGA_POST_CODE
+	select SOC_INTEL_COMMON_BLOCK_LPC_COMB_ENABLE
 	select TPM_MEASURED_BOOT
 	select TPM_MEASURED_BOOT_INIT_BOOTBLOCK
 

From 866a0591f71d6b8bb275b2372f5e495308b19610 Mon Sep 17 00:00:00 2001
From: Kilian Krause <kilian.krause@siemens.com>
Date: Tue, 25 Nov 2025 12:56:14 +0100
Subject: [PATCH 2615/3886] mb/siemens/mc_rpl1: Set coreboot ready LED

This mainboard has an LED that shows when coreboot has finished. The LED
is switched on via GPIO GPP_F4.

TEST=LED turns on when booting to Payload.

Change-Id: Ia292b10573d67df3f288b97fa2e92ae85ba7f27b
Signed-off-by: Kilian Krause <kilian.krause@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90201
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 .../siemens/mc_rpl/variants/mc_rpl1/Makefile.mk      |  1 +
 .../siemens/mc_rpl/variants/mc_rpl1/ramstage.c       | 12 ++++++++++++
 2 files changed, 13 insertions(+)
 create mode 100644 src/mainboard/siemens/mc_rpl/variants/mc_rpl1/ramstage.c

diff --git a/src/mainboard/siemens/mc_rpl/variants/mc_rpl1/Makefile.mk b/src/mainboard/siemens/mc_rpl/variants/mc_rpl1/Makefile.mk
index 03a936c199..2aa4fa9f80 100644
--- a/src/mainboard/siemens/mc_rpl/variants/mc_rpl1/Makefile.mk
+++ b/src/mainboard/siemens/mc_rpl/variants/mc_rpl1/Makefile.mk
@@ -3,5 +3,6 @@
 bootblock-y += early_gpio.c
 ramstage-y += gpio.c
 romstage-y += variant.c
+ramstage-y += ramstage.c
 
 all-$(CONFIG_NC_FPGA_POST_CODE) += post.c
diff --git a/src/mainboard/siemens/mc_rpl/variants/mc_rpl1/ramstage.c b/src/mainboard/siemens/mc_rpl/variants/mc_rpl1/ramstage.c
new file mode 100644
index 0000000000..b49ab1d0f9
--- /dev/null
+++ b/src/mainboard/siemens/mc_rpl/variants/mc_rpl1/ramstage.c
@@ -0,0 +1,12 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <bootstate.h>
+#include <gpio.h>
+
+static void finalize_boot(void *unused)
+{
+	/* Set coreboot ready LED. */
+	gpio_output(GPP_F4, 1);
+}
+
+BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_BOOT, BS_ON_ENTRY, finalize_boot, NULL);

From f1d1c825dcbd6ad277e2dae883734eb2064b00b8 Mon Sep 17 00:00:00 2001
From: Kilian Krause <kilian.krause@siemens.com>
Date: Fri, 21 Nov 2025 10:41:07 +0100
Subject: [PATCH 2616/3886] mb/siemens/mc_rpl1: Enable IBECC

Enable In-band ECC (IBECC) for mc_rpl1. IBECC provides memory error
detection and correction capabilities without requiring ECC memory
modules.

TEST=Inject correctable Error and verify IBECC detection and correction
through system logs. Testing based on Intel Doc. #751401

Change-Id: Ibf2a61bf425a51762fa8bb1cfe7b6f57edd3cfb5
Signed-off-by: Kilian Krause <kilian.krause@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90202
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-by: Uwe Poeche <uwe.poeche@siemens.com>
---
 .../siemens/mc_rpl/variants/mc_rpl1/overridetree.cb         | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/src/mainboard/siemens/mc_rpl/variants/mc_rpl1/overridetree.cb b/src/mainboard/siemens/mc_rpl/variants/mc_rpl1/overridetree.cb
index ae9f1c0ab4..ae514c2f3e 100644
--- a/src/mainboard/siemens/mc_rpl/variants/mc_rpl1/overridetree.cb
+++ b/src/mainboard/siemens/mc_rpl/variants/mc_rpl1/overridetree.cb
@@ -17,6 +17,12 @@ chip soc/intel/alderlake
 		[1] = 1,
 	}"
 
+	# Enable IBECC for the complete memory
+	register "ibecc" = "{
+		.enable = 1,
+		.mode = IBECC_MODE_ALL
+	}"
+
 	register "usb2_ports[0]" = "USB2_PORT_MID(OC_SKIP)"	# Port1
 	register "usb2_ports[1]" = "USB2_PORT_MID(OC_SKIP)"	# Port2
 	register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)"	# Onboard USB

From 80cf2008a9ffa26bd8521bdeb9b4fe5fc42a5b47 Mon Sep 17 00:00:00 2001
From: John Su <john_su@compal.corp-partner.google.com>
Date: Thu, 13 Nov 2025 15:33:39 +0800
Subject: [PATCH 2617/3886] spd/lp5: Add SPD for MT62F1G32D2DS-031RF WT:C

Add MT62F1G32D2DS-031RF WT:C in the memory_parts.json and re-generate
the SPD.

BUG=b:459934066
TEST=util/spd_tools/bin/spd_gen spd/lp5/memory_parts.json lp5

Change-Id: Ib65f24347ddae2808720f8e3c73652a82de94311
Signed-off-by: John Su <john_su@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90019
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 spd/lp5/memory_parts.json                      | 10 ++++++++++
 spd/lp5/set-0/parts_spd_manifest.generated.txt |  1 +
 spd/lp5/set-1/parts_spd_manifest.generated.txt |  1 +
 3 files changed, 12 insertions(+)

diff --git a/spd/lp5/memory_parts.json b/spd/lp5/memory_parts.json
index 1a29150bc0..c012c2eb50 100644
--- a/spd/lp5/memory_parts.json
+++ b/spd/lp5/memory_parts.json
@@ -403,6 +403,16 @@
             "speedMbps": 8533,
             "lp5x": true
         }
+    },
+    {
+        "name":  "MT62F1G32D2DS-031RF WT:C",
+        "attribs": {
+            "densityPerDieGb": 16,
+            "diesPerPackage": 2,
+            "bitWidthPerChannel": 16,
+            "ranksPerChannel": 1,
+            "speedMbps": 6400
+       }
     }
     ]
 }
diff --git a/spd/lp5/set-0/parts_spd_manifest.generated.txt b/spd/lp5/set-0/parts_spd_manifest.generated.txt
index b808e1941c..9566fc2752 100644
--- a/spd/lp5/set-0/parts_spd_manifest.generated.txt
+++ b/spd/lp5/set-0/parts_spd_manifest.generated.txt
@@ -39,3 +39,4 @@ H58GE6AK8BX104,spd-12.hex
 K3KLALA0EM-MGCU,spd-13.hex
 MT62F1G32D2DS-020 WT:D,spd-11.hex
 K3KL8L80EM-MGCV,spd-11.hex
+MT62F1G32D2DS-031RF WT:C,spd-3.hex
diff --git a/spd/lp5/set-1/parts_spd_manifest.generated.txt b/spd/lp5/set-1/parts_spd_manifest.generated.txt
index b808e1941c..9566fc2752 100644
--- a/spd/lp5/set-1/parts_spd_manifest.generated.txt
+++ b/spd/lp5/set-1/parts_spd_manifest.generated.txt
@@ -39,3 +39,4 @@ H58GE6AK8BX104,spd-12.hex
 K3KLALA0EM-MGCU,spd-13.hex
 MT62F1G32D2DS-020 WT:D,spd-11.hex
 K3KL8L80EM-MGCV,spd-11.hex
+MT62F1G32D2DS-031RF WT:C,spd-3.hex

From 36f4341533dac0867ed43685bdd82734050053fc Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Wed, 15 Oct 2025 09:01:17 +0100
Subject: [PATCH 2618/3886] mb/starlabs/starfighter: Add Arrow Lake (285H)
 variant

Tested using `edk2` from
`https://github.com/starlabsltd/edk2/tree/uefipayload_vs`:
* Ubuntu 24.04
* Manjaro 24

No known issues.

https://starlabs.systems/pages/starfighter-specification

Change-Id: I75f92cd957c72077460ab4b7ed6b08453f5058d4
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89592
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/starlabs/starfighter/Kconfig    |  27 +-
 .../starlabs/starfighter/Kconfig.name         |   3 +
 src/mainboard/starlabs/starfighter/cfr.c      |   3 +
 src/mainboard/starlabs/starfighter/dsdt.asl   |   6 +-
 .../starlabs/starfighter/include/variants.h   |   2 +
 .../starlabs/starfighter/mainboard.c          |   9 -
 .../starlabs/starfighter/spd/32gb-mtl.spd.hex |  32 ++
 .../starlabs/starfighter/spd/64gb-mtl.spd.hex |  23 ++
 .../starlabs/starfighter/spd/Makefile.mk      |  11 +-
 .../starfighter/variants/mtl/Makefile.mk      |  15 +
 .../starfighter/variants/mtl/board.fmd        |  14 +
 .../starfighter/variants/mtl/board_id.c       |  34 ++
 .../starfighter/variants/mtl/data.vbt         | Bin 0 -> 7680 bytes
 .../variants/mtl/data_native_res.vbt          | Bin 0 -> 7680 bytes
 .../starfighter/variants/mtl/data_qhd.vbt     | Bin 0 -> 7680 bytes
 .../starfighter/variants/mtl/devicetree.cb    | 322 ++++++++++++++++++
 .../starfighter/variants/mtl/devtree.c        |  68 ++++
 .../starlabs/starfighter/variants/mtl/gpio.c  | 260 ++++++++++++++
 .../starfighter/variants/mtl/hda_verb.c       | 105 ++++++
 .../starfighter/variants/mtl/ramstage.c       |  24 ++
 .../starfighter/variants/mtl/romstage.c       | 106 ++++++
 .../starfighter/variants/rpl/ramstage.c       |   9 +
 22 files changed, 1055 insertions(+), 18 deletions(-)
 create mode 100644 src/mainboard/starlabs/starfighter/spd/32gb-mtl.spd.hex
 create mode 100644 src/mainboard/starlabs/starfighter/spd/64gb-mtl.spd.hex
 create mode 100644 src/mainboard/starlabs/starfighter/variants/mtl/Makefile.mk
 create mode 100644 src/mainboard/starlabs/starfighter/variants/mtl/board.fmd
 create mode 100644 src/mainboard/starlabs/starfighter/variants/mtl/board_id.c
 create mode 100644 src/mainboard/starlabs/starfighter/variants/mtl/data.vbt
 create mode 100644 src/mainboard/starlabs/starfighter/variants/mtl/data_native_res.vbt
 create mode 100644 src/mainboard/starlabs/starfighter/variants/mtl/data_qhd.vbt
 create mode 100644 src/mainboard/starlabs/starfighter/variants/mtl/devicetree.cb
 create mode 100644 src/mainboard/starlabs/starfighter/variants/mtl/devtree.c
 create mode 100644 src/mainboard/starlabs/starfighter/variants/mtl/gpio.c
 create mode 100644 src/mainboard/starlabs/starfighter/variants/mtl/hda_verb.c
 create mode 100644 src/mainboard/starlabs/starfighter/variants/mtl/ramstage.c
 create mode 100644 src/mainboard/starlabs/starfighter/variants/mtl/romstage.c

diff --git a/src/mainboard/starlabs/starfighter/Kconfig b/src/mainboard/starlabs/starfighter/Kconfig
index cad5ac64a1..1e12366501 100644
--- a/src/mainboard/starlabs/starfighter/Kconfig
+++ b/src/mainboard/starlabs/starfighter/Kconfig
@@ -25,13 +25,10 @@ config BOARD_STARLABS_STARFIGHTER_SERIES
 	select MEMORY_MAPPED_TPM
 	select NO_UART_ON_SUPERIO
 	select PMC_IPC_ACPI_INTERFACE
-	select SOC_INTEL_ALDERLAKE
-	select SOC_INTEL_ALDERLAKE_PCH_P
 	select SOC_INTEL_COMMON_BLOCK_HDA_VERB
 	select SOC_INTEL_COMMON_BLOCK_TCSS
 	select SOC_INTEL_CRASHLOG
 	select SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES
-	select SOC_INTEL_RAPTORLAKE
 	select SPD_READ_BY_WORD
 	select SPI_FLASH_WINBOND
 	select SYSTEM_TYPE_LAPTOP
@@ -40,12 +37,25 @@ config BOARD_STARLABS_STARFIGHTER_SERIES
 
 config BOARD_STARLABS_STARFIGHTER_RPL
 	select BOARD_STARLABS_STARFIGHTER_SERIES
+	select SOC_INTEL_ALDERLAKE
+	select SOC_INTEL_ALDERLAKE_PCH_P
+	select SOC_INTEL_RAPTORLAKE
+
+config BOARD_STARLABS_STARFIGHTER_MTL
+	select BOARD_STARLABS_STARFIGHTER_SERIES
+	select SOC_INTEL_COMMON_BLOCK_VTD
+	select SOC_INTEL_METEORLAKE
+	select SOC_INTEL_METEORLAKE_U_H
 
 if BOARD_STARLABS_STARFIGHTER_SERIES
 
+config BOARD_USES_FIXED_MODE_VBT
+	bool
+	default y
+
 config CCD_PORT
 	int
-	default 3 # TODO
+	default 4
 
 config CONSOLE_SERIAL
 	default n if !EDK2_DEBUG
@@ -89,16 +99,18 @@ config MAINBOARD_DIR
 
 config MAINBOARD_FAMILY
 	string
+	default "F2" if BOARD_STARLABS_STARFIGHTER_MTL
 	default "F1"
 
 config MAINBOARD_PART_NUMBER
+	default "StarFighter Mk II" if BOARD_STARLABS_STARFIGHTER_MTL
 	default "StarFighter Mk I"
 
 config MAINBOARD_SMBIOS_PRODUCT_NAME
 	default "StarFighter"
 
 config ME_BIN_PATH
-	# string
+	string
 	default "3rdparty/blobs/mainboard/\$(MAINBOARDDIR)/\$(CONFIG_VARIANT_DIR)/intel_me.bin"
 
 config POWER_STATE_DEFAULT_ON_AFTER_FAILURE
@@ -107,8 +119,12 @@ config POWER_STATE_DEFAULT_ON_AFTER_FAILURE
 config SOC_INTEL_CSE_SEND_EOP_EARLY
 	default n
 
+config TME_KEY_REGENERATION_ON_WARM_BOOT
+	default n
+
 config TPM_PIRQ
 	depends on MAINBOARD_HAS_TPM2
+	default 0x3d if BOARD_STARLABS_STARFIGHTER_MTL
 	default 0x37
 
 config UART_FOR_CONSOLE
@@ -121,6 +137,7 @@ config VBOOT
 	select VBOOT_VBNV_FLASH
 
 config VARIANT_DIR
+	default "mtl" if BOARD_STARLABS_STARFIGHTER_MTL
 	default "rpl"
 
 endif
diff --git a/src/mainboard/starlabs/starfighter/Kconfig.name b/src/mainboard/starlabs/starfighter/Kconfig.name
index 0106256552..4f530fa699 100644
--- a/src/mainboard/starlabs/starfighter/Kconfig.name
+++ b/src/mainboard/starlabs/starfighter/Kconfig.name
@@ -4,3 +4,6 @@ comment "Star Labs StarFighter Series"
 
 config BOARD_STARLABS_STARFIGHTER_RPL
 	bool "Star Labs StarFighter Mk I (i3-1315U, i7-13700H and i9-13900H)"
+
+config BOARD_STARLABS_STARFIGHTER_MTL
+	bool "Star Labs StarFighter Mk II (125H and 285H)"
diff --git a/src/mainboard/starlabs/starfighter/cfr.c b/src/mainboard/starlabs/starfighter/cfr.c
index 89f8811bb0..166a9dbb81 100644
--- a/src/mainboard/starlabs/starfighter/cfr.c
+++ b/src/mainboard/starlabs/starfighter/cfr.c
@@ -64,6 +64,9 @@ static struct sm_obj_form devices = {
 		#if CONFIG(DRIVERS_INTEL_USB4_RETIMER)
 		&thunderbolt,
 		#endif
+		#if CONFIG(SOC_INTEL_METEORLAKE)
+		&vpu,
+		#endif
 		NULL
 	},
 };
diff --git a/src/mainboard/starlabs/starfighter/dsdt.asl b/src/mainboard/starlabs/starfighter/dsdt.asl
index b7783eae63..a2b00e54ea 100644
--- a/src/mainboard/starlabs/starfighter/dsdt.asl
+++ b/src/mainboard/starlabs/starfighter/dsdt.asl
@@ -18,9 +18,13 @@ DefinitionBlock(
 	Device (\_SB.PCI0)
 	{
 		#include <soc/intel/common/block/acpi/acpi/northbridge.asl>
+#if CONFIG(SOC_INTEL_ALDERLAKE)
 		#include <soc/intel/alderlake/acpi/southbridge.asl>
 		#include <soc/intel/alderlake/acpi/tcss.asl>
-
+#elif CONFIG(SOC_INTEL_METEORLAKE)
+		#include <soc/intel/meteorlake/acpi/southbridge.asl>
+		#include <soc/intel/meteorlake/acpi/tcss.asl>
+#endif
 		#include <drivers/intel/gma/acpi/default_brightness_levels.asl>
 
 		#include <soc/intel/common/block/acpi/acpi/gna.asl>
diff --git a/src/mainboard/starlabs/starfighter/include/variants.h b/src/mainboard/starlabs/starfighter/include/variants.h
index c95d15bd72..b3334870b1 100644
--- a/src/mainboard/starlabs/starfighter/include/variants.h
+++ b/src/mainboard/starlabs/starfighter/include/variants.h
@@ -5,6 +5,8 @@
 
 #include <soc/gpio.h>
 
+uint8_t get_memory_config_straps(void);
+
 /*
  * The next set of functions return the gpio table and fill in the number of
  * entries for each table.
diff --git a/src/mainboard/starlabs/starfighter/mainboard.c b/src/mainboard/starlabs/starfighter/mainboard.c
index c474390e46..60e65ee8c4 100644
--- a/src/mainboard/starlabs/starfighter/mainboard.c
+++ b/src/mainboard/starlabs/starfighter/mainboard.c
@@ -1,7 +1,6 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
 #include <device/device.h>
-#include <drivers/intel/gma/opregion.h>
 #include <soc/ramstage.h>
 #include <option.h>
 #include <variants.h>
@@ -20,11 +19,3 @@ static void init_mainboard(void *chip_info)
 struct chip_operations mainboard_ops = {
 	.init = init_mainboard,
 };
-
-const char *mainboard_vbt_filename(void)
-{
-	if (get_uint_option("display_native_res", 0) == 1)
-		return "vbt_native_res.bin";
-
-	return "vbt.bin";
-}
diff --git a/src/mainboard/starlabs/starfighter/spd/32gb-mtl.spd.hex b/src/mainboard/starlabs/starfighter/spd/32gb-mtl.spd.hex
new file mode 100644
index 0000000000..d38329a777
--- /dev/null
+++ b/src/mainboard/starlabs/starfighter/spd/32gb-mtl.spd.hex
@@ -0,0 +1,32 @@
+23 10 13 0E 16 22 B5 08 00 40 00 00 0A 01 00 00
+48 00 0A FF 92 55 05 00 AA 00 90 A8 90 C0 08 60
+04 08 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 7F 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 20 00 00 00 20 20 20 20 20 20 20
+20 20 20 20 20 20 20 20 20 20 20 20 20 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
diff --git a/src/mainboard/starlabs/starfighter/spd/64gb-mtl.spd.hex b/src/mainboard/starlabs/starfighter/spd/64gb-mtl.spd.hex
new file mode 100644
index 0000000000..d8a75d2182
--- /dev/null
+++ b/src/mainboard/starlabs/starfighter/spd/64gb-mtl.spd.hex
@@ -0,0 +1,23 @@
+23 10 15 0E 16 2A F9 08 00 40 00 00 09 01 00 00
+48 00 08 FF 92 55 05 00 AA 00 90 A8 90 C0 08 60
+04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 20 00 00 00
+20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20
+20 20 20 20 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
diff --git a/src/mainboard/starlabs/starfighter/spd/Makefile.mk b/src/mainboard/starlabs/starfighter/spd/Makefile.mk
index 2f4598ee8e..ee9a117ed2 100644
--- a/src/mainboard/starlabs/starfighter/spd/Makefile.mk
+++ b/src/mainboard/starlabs/starfighter/spd/Makefile.mk
@@ -1,5 +1,10 @@
 ## SPDX-License-Identifier: GPL-2.0-only
 
-SPD_SOURCES = 16gb	# 13
-SPD_SOURCES += 32gb	# 0
-SPD_SOURCES += 64gb	# 8
+ifeq ($(CONFIG_BOARD_STARLABS_STARFIGHTER_RPL),y)
+SPD_SOURCES = 16gb # 13
+SPD_SOURCES += 32gb # 0
+SPD_SOURCES += 64gb # 8
+else
+SPD_SOURCES = 32gb-mtl # 13
+SPD_SOURCES += 64gb-mtl # 0
+endif
diff --git a/src/mainboard/starlabs/starfighter/variants/mtl/Makefile.mk b/src/mainboard/starlabs/starfighter/variants/mtl/Makefile.mk
new file mode 100644
index 0000000000..c32caa48e9
--- /dev/null
+++ b/src/mainboard/starlabs/starfighter/variants/mtl/Makefile.mk
@@ -0,0 +1,15 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
+bootblock-y += gpio.c
+
+romstage-y += board_id.c
+romstage-y += romstage.c
+
+ramstage-y += board_id.c
+ramstage-y += devtree.c
+ramstage-y += gpio.c
+ramstage-y += hda_verb.c
+ramstage-y += ramstage.c
+
+$(call add_vbt_to_cbfs, vbt_native_res.bin, data_native_res.vbt)
+$(call add_vbt_to_cbfs, vbt_qhd.bin, data_qhd.vbt)
diff --git a/src/mainboard/starlabs/starfighter/variants/mtl/board.fmd b/src/mainboard/starlabs/starfighter/variants/mtl/board.fmd
new file mode 100644
index 0000000000..1c11c433a2
--- /dev/null
+++ b/src/mainboard/starlabs/starfighter/variants/mtl/board.fmd
@@ -0,0 +1,14 @@
+FLASH	0x2000000 {
+	SI_ALL	0x1000000 {
+		SI_DESC			0x4000
+		SI_ME			0x80f000
+	}
+	SI_BIOS 0x1000000 {
+		EC@0x0			0x20000
+		RW_MRC_CACHE@0x20000	0x10000
+		SMMSTORE@0x30000	0x40000
+		CONSOLE@0x70000		0x20000
+		FMAP@0x90000		0x1000
+		COREBOOT(CBFS)
+	}
+}
diff --git a/src/mainboard/starlabs/starfighter/variants/mtl/board_id.c b/src/mainboard/starlabs/starfighter/variants/mtl/board_id.c
new file mode 100644
index 0000000000..83e12b4d91
--- /dev/null
+++ b/src/mainboard/starlabs/starfighter/variants/mtl/board_id.c
@@ -0,0 +1,34 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <gpio.h>
+#include <variants.h>
+
+uint8_t get_memory_config_straps(void)
+{
+	/*
+	 * The hardware supports a number of different memory configurations
+	 * which are selected using four ID bits ID3 (GPP_B05), ID2 (GPP_B06),
+	 * ID1 (GPP_B07) and ID0 (GPP_B08).
+	 *
+	 * +------+-----+-----+-----+-----+
+	 * |      | ID3 | ID2 | ID1 | ID0 |
+	 * +------+-----+-----+-----+-----+
+	 * | 32GB |  1  |  0  |  0  |  0  |
+	 * +------+-----+-----+-----+-----+
+	 * | 64GB |  1  |  1  |  0  |  1  |
+	 * +------+-----+-----+-----+-----+
+	 *
+	 * We return the value of these bits so that the index into the SPD
+	 * table can be .spd[] values can be configured correctly in the
+	 * memory configuration structure.
+	 */
+
+	gpio_t spd_id[] = {
+		GPP_B05,
+		GPP_B06,
+		GPP_B07,
+		GPP_B08,
+	};
+
+	return (uint8_t)gpio_base2_value(spd_id, ARRAY_SIZE(spd_id));
+}
diff --git a/src/mainboard/starlabs/starfighter/variants/mtl/data.vbt b/src/mainboard/starlabs/starfighter/variants/mtl/data.vbt
new file mode 100644
index 0000000000000000000000000000000000000000..af525583dddaf60d143a663e70787402123461a5
GIT binary patch
literal 7680
zcmeHMO>7%Q6n?X7JC1RP+XU*SX&BNfIBAn?oHnFUq^|SVx=kAAr;#fm#Z7H!AZ<dL
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qzSmQ$tv<)j>u+ODocI$5KXR187WtJ)j<?zTJqa>|tw38HfxiJxxrr_S

literal 0
HcmV?d00001

diff --git a/src/mainboard/starlabs/starfighter/variants/mtl/data_native_res.vbt b/src/mainboard/starlabs/starfighter/variants/mtl/data_native_res.vbt
new file mode 100644
index 0000000000000000000000000000000000000000..cd70aad5d9189f370421e197dac094e155763603
GIT binary patch
literal 7680
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literal 0
HcmV?d00001

diff --git a/src/mainboard/starlabs/starfighter/variants/mtl/data_qhd.vbt b/src/mainboard/starlabs/starfighter/variants/mtl/data_qhd.vbt
new file mode 100644
index 0000000000000000000000000000000000000000..2235579a167aa29251b0c71b8e85c02945ea756c
GIT binary patch
literal 7680
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literal 0
HcmV?d00001

diff --git a/src/mainboard/starlabs/starfighter/variants/mtl/devicetree.cb b/src/mainboard/starlabs/starfighter/variants/mtl/devicetree.cb
new file mode 100644
index 0000000000..ff211fd173
--- /dev/null
+++ b/src/mainboard/starlabs/starfighter/variants/mtl/devicetree.cb
@@ -0,0 +1,322 @@
+chip soc/intel/meteorlake
+	# FSP UPDs
+	register "eist_enable"				= "true"
+	register "pch_pm_energy_report_enable"		= "true"
+	register "sagv"					= "SAGV_ENABLED"
+
+	# Serial I/O
+	register "serial_io_i2c_mode" = "{
+		[PchSerialIoIndexI2C0]			= PchSerialIoPci,
+	}"
+
+	register "common_soc_config" = "{
+		.i2c[0] = {
+			.speed				= I2C_SPEED_FAST,
+		},
+	}"
+
+	register "serial_io_uart_mode" = "{
+		[PchSerialIoIndexUART0]			= PchSerialIoSkipInit,
+	}"
+
+	# Power
+	register "pch_slp_s3_min_assertion_width"	= "SLP_S3_ASSERTION_1_MS"
+	register "pch_slp_s4_min_assertion_width"	= "SLP_S4_ASSERTION_3S"
+	register "pch_slp_sus_min_assertion_width"	= "SLP_SUS_ASSERTION_1_S"
+	register "pch_slp_a_min_assertion_width"	= "SLP_A_ASSERTION_98_MS"
+
+	device domain 0 on
+		device ref igpu		on
+			chip drivers/gfx/generic
+				register "device_count"		= "6"
+				# [DDIA] eDP
+				register "device[0].name"	= ""LCD0""
+				register "device[0].type"	= "panel"
+				# [DDIB] HDMI
+				register "device[1].name"	= ""DD01""
+				# [TCP0] Type-C
+				register "device[2].name"	= ""DD02""
+				register "device[2].use_pld"	= "true"
+				register "device[2].pld"	= "ACPI_PLD_TYPE_C(LEFT, CENTER, ACPI_PLD_GROUP(0, 0))"
+				# [TCP1] Type-C
+				register "device[3].name"	= ""DD03""
+				register "device[3].use_pld"	= "true"
+				register "device[3].pld"	= "ACPI_PLD_TYPE_C(LEFT, CENTER, ACPI_PLD_GROUP(0, 1))"
+				# [TCP2] N/A
+				register "device[4].name"	= ""DD04""
+				# [TCP3] N/A
+				register "device[5].name"	= ""DD05""
+				device generic 0 on end
+			end
+
+			register "ddi_port_A_config"		= "1"
+			register "ddi_ports_config" = "{
+				[DDI_PORT_A]			= DDI_ENABLE_HPD | DDI_ENABLE_DDC,
+				[DDI_PORT_B]			= DDI_ENABLE_HPD | DDI_ENABLE_DDC,
+			}"
+		end
+		device ref pcie_rp9	on				# WiFi
+			register "pcie_rp[PCH_RP(9)]" = "{
+				.clk_src				= 5,
+				.clk_req				= 5,
+				.flags					= PCIE_RP_LTR | PCIE_RP_AER,
+				.pcie_rp_aspm				= ASPM_L0S_L1,
+				.PcieRpL1Substates			= L1_SS_L1_2,
+			}"
+
+			smbios_slot_desc				"SlotTypePciExpressGen3X1"
+									"SlotLengthShort"
+									"M.2/M 2230"
+									"SlotDataBusWidth1X"
+
+			chip soc/intel/common/block/pcie/rtd3
+				register "enable_gpio"			= "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B19)"
+				register "reset_gpio"			= "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_H02)"
+				register "srcclk_pin"			= "5"
+				register "add_acpi_dma_property"	= "true"
+				register "skip_on_off_support"		= "true"
+				register "ext_pm_support"		= "ACPI_PCIE_RP_EMIT_ALL"
+				register "use_rp_mutex"			= "true"
+				device generic 0 on end
+			end
+		end
+		device ref pcie_rp10	on				# SSD x4
+			register "pcie_rp[PCH_RP(10)]" = "{
+				.clk_src				= 8,
+				.clk_req				= 8,
+				.flags					= PCIE_RP_LTR | PCIE_RP_AER,
+				.pcie_rp_aspm				= ASPM_L0S_L1,
+				.PcieRpL1Substates			= L1_SS_L1_2,
+			}"
+
+			smbios_slot_desc				"SlotTypeM2Socket3"
+									"SlotLengthLong"
+									"M.2/M 2280"
+									"SlotDataBusWidth4X"
+
+			chip soc/intel/common/block/pcie/rtd3
+				register "enable_gpio"			= "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_H07)"
+				register "reset_gpio"			= "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A20)"
+				register "srcclk_pin"			= "8"
+				register "is_storage"			= "true"
+				register "add_acpi_dma_property"	= "true"
+				register "skip_on_off_support"		= "true"
+				register "ext_pm_support"		= "ACPI_PCIE_RP_EMIT_ALL"
+				register "use_rp_mutex"			= "true"
+				device generic 0 on end
+			end
+		end
+		device ref tbt_pcie_rp0	on  end
+		device ref tbt_pcie_rp1	on  end
+		device ref gna		on  end
+		device ref vpu		on  end
+		device ref tcss_xhci	on
+			chip drivers/usb/acpi
+				device ref tcss_root_hub on
+					chip drivers/usb/acpi
+						register "desc"			= ""Back USB Type-C""
+						register "type"			= "UPC_TYPE_C_USB2_SS_SWITCH"
+						register "use_custom_pld"	= "true"
+						register "custom_pld"		= "ACPI_PLD_TYPE_C(LEFT, CENTER, ACPI_PLD_GROUP(0, 0))"
+						device ref tcss_usb3_port0 on end
+					end
+					chip drivers/usb/acpi
+						register "desc"			= ""Front USB Type-C""
+						register "type"			= "UPC_TYPE_C_USB2_SS_SWITCH"
+						register "use_custom_pld"	= "true"
+						register "custom_pld"		= "ACPI_PLD_TYPE_C(LEFT, CENTER, ACPI_PLD_GROUP(0, 1))"
+						device ref tcss_usb3_port1 on end
+					end
+				end
+			end
+		end
+		device ref tcss_dma0	on
+			chip drivers/intel/usb4/retimer
+				register "dfp[0].power_gpio"	= "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B21)"
+				use tcss_usb3_port1 as dfp[0].typec_port
+				device generic 0 on end
+			end
+			chip drivers/intel/usb4/retimer
+				register "dfp[0].power_gpio"	= "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B21)"
+				use tcss_usb3_port2 as dfp[0].typec_port
+				device generic 0 on end
+			end
+		end
+		device ref ioe_shared_sram	on  end
+		device ref xhci		on
+			# Motherboard USB 3.0 Type-C Back	7893 mil
+			register "usb2_ports[0]"		= "USB2_PORT_TYPE_C(OC_SKIP)"
+			register "tcss_ports[0]"		= "TCSS_PORT_DEFAULT(OC_SKIP)"
+
+			# Motherboard USB 3.0 Type-C Front	9557 mil
+			register "usb2_ports[2]"		= "USB2_PORT_TYPE_C(OC_SKIP)"
+			register "tcss_ports[1]"		= "TCSS_PORT_DEFAULT(OC_SKIP)"
+
+			# Motherboard USB 3.0 Type-A		8916 mil
+			register "usb2_ports[1]"		= "USB2_PORT_MID(OC_SKIP)"
+			register "usb3_ports[0]"		= "USB3_PORT_DEFAULT(OC_SKIP)"
+
+			# Daughterboard USB 3.0 Type-A		2229 mil
+			register "usb2_ports[6]"		= "USB2_PORT_SHORT(OC_SKIP)"
+			register "usb3_ports[1]"		= "USB3_PORT_DEFAULT(OC_SKIP)"
+
+			# Internal Webcam			9070 mil
+			register "usb2_ports[CONFIG_CCD_PORT]"	= "USB2_PORT_MID(OC_SKIP)"
+
+			# Internal Bluetooth			723 mil
+			register "usb2_ports[9]"		= "USB2_PORT_SHORT(OC_SKIP)"
+
+			chip drivers/usb/acpi
+				device ref xhci_root_hub on
+					chip drivers/usb/acpi
+						register "desc"			= ""Back USB Type-C""
+						register "type"			= "UPC_TYPE_C_USB2_SS_SWITCH"
+						register "use_custom_pld"	= "true"
+						register "custom_pld"		= "ACPI_PLD_TYPE_C(LEFT, CENTER, ACPI_PLD_GROUP(0, 0))"
+						device ref usb2_port1 on end
+					end
+					chip drivers/usb/acpi
+						register "desc"			= ""Front USB Type-C""
+						register "type"			= "UPC_TYPE_C_USB2_SS_SWITCH"
+						register "use_custom_pld"	= "true"
+						register "custom_pld"		= "ACPI_PLD_TYPE_C(LEFT, CENTER, ACPI_PLD_GROUP(0, 1))"
+						device ref usb2_port3 on end
+					end
+					chip drivers/usb/acpi
+						register "desc"			= ""Left USB Type-A""
+						register "type"			= "UPC_TYPE_USB3_A"
+						register "group"		= "ACPI_PLD_GROUP(0, 2)"
+						device ref usb2_port2 on end
+					end
+					chip drivers/usb/acpi
+						register "desc"			= ""Left USB Type-A""
+						register "type"			= "UPC_TYPE_USB3_A"
+						register "group"		= "ACPI_PLD_GROUP(0, 2)"
+						device ref usb3_port1 on end
+					end
+					chip drivers/usb/acpi
+						register "desc"			= ""Right Rear USB Type-A""
+						register "type"			= "UPC_TYPE_USB3_A"
+						register "group"		= "ACPI_PLD_GROUP(0, 3)"
+						device ref usb2_port7 on end
+					end
+					chip drivers/usb/acpi
+						register "desc"			= ""Right Rear USB Type-A""
+						register "type"			= "UPC_TYPE_USB3_A"
+						register "group"		= "ACPI_PLD_GROUP(0, 3)"
+						device ref usb3_port2 on end
+					end
+					chip drivers/usb/acpi
+						register "desc"			= ""Internal Webcam""
+						register "type"			= "UPC_TYPE_INTERNAL"
+						register "group"		= "ACPI_PLD_GROUP(0, 4)"
+						device ref usb2_port5 on end
+					end
+					chip drivers/usb/acpi
+						register "desc"			= ""Internal Bluetooth""
+						register "type"			= "UPC_TYPE_INTERNAL"
+						register "is_intel_bluetooth"	= "true"
+						register "enable_gpio"		= "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B18)"
+						register "reset_gpio"		= "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B18)"
+						register "group"		= "ACPI_PLD_GROUP(0, 6)"
+						device ref usb2_port10 on end
+					end
+				end
+			end
+		end
+		device ref i2c0		on
+			chip drivers/i2c/hid
+				register "generic.hid"		= ""STAR0001""
+				register "generic.desc"		= ""Touchpad""
+				register "generic.irq"		= "ACPI_IRQ_LEVEL_LOW(GPP_B00_IRQ)"
+				register "hid_desc_reg_offset"	= "0x20"
+				device i2c 2c on end
+			end
+		end
+		device ref pcie_rp1	on				# SSD x4
+			register "pcie_rp[PCH_RP(1)]" = "{
+				.clk_src				= 1,
+				.clk_req				= 1,
+				.flags					= PCIE_RP_LTR | PCIE_RP_AER,
+				.pcie_rp_aspm				= ASPM_L0S_L1,
+				.PcieRpL1Substates			= L1_SS_L1_2,
+			}"
+
+			smbios_slot_desc				"SlotTypeM2Socket3"
+									"SlotLengthLong"
+									"M.2/M 2280"
+									"SlotDataBusWidth4X"
+
+			chip soc/intel/common/block/pcie/rtd3
+				register "enable_gpio"			= "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D22)"
+				register "reset_gpio"			= "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_H00)"
+				register "srcclk_pin"			= "1"
+				register "is_storage"			= "true"
+				register "add_acpi_dma_property"	= "true"
+				register "skip_on_off_support"		= "true"
+				register "ext_pm_support"		= "ACPI_PCIE_RP_EMIT_ALL"
+				register "use_rp_mutex"			= "true"
+				device generic 0 on end
+			end
+		end
+		device ref uart0	on  end
+		device ref soc_espi	on
+			register "gen1_dec"			= "0x00040069"
+			register "gen2_dec"			= "0x00fc0201"
+			register "gen3_dec"			= "0x000c0081"
+
+			chip drivers/pc80/tpm
+				device pnp 0c31.0 on end
+			end
+
+			chip ec/starlabs/merlin
+				# Port pair 4Eh/4Fh
+				device pnp 4e.01 off end			# Com 1
+				device pnp 4e.02 off end			# Com 2
+				device pnp 4e.04 off end			# System Wake-Up
+				device pnp 4e.05 off end			# PS/2 Mouse
+				device pnp 4e.06 on				# PS/2 Keyboard
+					io 0x60			= 0x0060
+					io 0x62			= 0x0064
+					irq 0x70		= 1
+				end
+				device pnp 4e.0a off end			# Consumer IR
+				device pnp 4e.0f off end			# Shared Memory/Flash Interface
+				device pnp 4e.10 off end			# RTC-like Timer
+				device pnp 4e.11 off end			# Power Management Channel 1
+				device pnp 4e.12 off end			# Power Management Channel 2
+				device pnp 4e.13 off end			# Serial Peripheral Interface
+				device pnp 4e.14 off end			# Platform EC Interface
+				device pnp 4e.17 off end			# Power Management Channel 3
+				device pnp 4e.18 off end			# Power Management Channel 4
+				device pnp 4e.19 off end			# Power Management Channel 5
+			end
+		end
+		device ref pmc		hidden
+			chip drivers/intel/pmc_mux
+				device generic 0 on
+					chip drivers/intel/pmc_mux/conn
+						use usb2_port1 as usb2_port
+						use tcss_usb3_port0 as usb3_port
+						device generic 0 alias conn0 on end
+					end
+					chip drivers/intel/pmc_mux/conn
+						use usb2_port3 as usb2_port
+						use tcss_usb3_port1 as usb3_port
+						device generic 1 alias conn1 on end
+					end
+				end
+			end
+		end
+		device ref hda		on
+			subsystemid 0x2014 0x7017
+			register "pch_hda_sdi_enable[0]"		= "true"
+			register "pch_hda_dsp_enable"			= "true"
+			register "pch_hda_audio_link_hda_enable"	= "true"
+			register "pch_hda_idisp_codec_enable"		= "true"
+			register "pch_hda_idisp_link_frequency"		= "HDA_LINKFREQ_96MHZ"
+			register "pch_hda_idisp_link_tmode"		= "HDA_TMODE_8T"
+		end
+		device ref smbus	on  end
+	end
+end
diff --git a/src/mainboard/starlabs/starfighter/variants/mtl/devtree.c b/src/mainboard/starlabs/starfighter/variants/mtl/devtree.c
new file mode 100644
index 0000000000..a983bba747
--- /dev/null
+++ b/src/mainboard/starlabs/starfighter/variants/mtl/devtree.c
@@ -0,0 +1,68 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <chip.h>
+#include <cpu/intel/turbo.h>
+#include <device/device.h>
+#include <device/pci_def.h>
+#include <option.h>
+#include <static.h>
+#include <types.h>
+#include <variants.h>
+#include <common/powercap.h>
+
+#define TJ_MAX		110
+#define TCC(temp)	(TJ_MAX - temp)
+
+void devtree_update(void)
+{
+	config_t *cfg = config_of_soc();
+
+	struct soc_power_limits_config *soc_conf_20core =
+		&cfg->power_limits_config[MTL_P_682_482_CORE];
+
+	uint8_t performance_scale = 100;
+
+	/* Set PL4 to 1.0C */
+	soc_conf_20core->tdp_pl4			= 65;
+
+	/* Set PL1 to 50% of PL2 */
+	soc_conf_20core->tdp_pl1_override = (soc_conf_20core->tdp_pl2_override / 2) & ~1;
+
+	/* Scale PL1 & PL2 based on CMOS settings */
+	switch (get_power_profile(PP_POWER_SAVER)) {
+	case PP_POWER_SAVER:
+		performance_scale			-= 50;
+		cfg->tcc_offset				= TCC(80);
+		break;
+	case PP_BALANCED:
+		performance_scale			-= 25;
+		cfg->tcc_offset				= TCC(90);
+		break;
+	case PP_PERFORMANCE:
+		/* Use the Intel defaults */
+		cfg->tcc_offset				= TCC(100);
+		break;
+	}
+
+	soc_conf_20core->tdp_pl1_override = (soc_conf_20core->tdp_pl1_override * performance_scale) / 100;
+	soc_conf_20core->tdp_pl2_override = (soc_conf_20core->tdp_pl2_override * performance_scale) / 100;
+
+	/* Enable/Disable Webcam based on CMOS settings */
+	if (get_uint_option("webcam", 1) == 0)
+		cfg->usb2_ports[CONFIG_CCD_PORT].enable = 0;
+
+	/* Enable/Disable Thunderbolt based on CMOS settings */
+	if (get_uint_option("thunderbolt", 1) == 0) {
+		DEV_PTR(tbt_pcie_rp0)->enabled = 0;
+		DEV_PTR(tbt_pcie_rp1)->enabled = 0;
+		DEV_PTR(tcss_dma0)->enabled = 0;
+	}
+
+	/* Enable/Disable GNA based on CMOS settings */
+	if (get_uint_option("gna", 0) == 0)
+		DEV_PTR(gna)->enabled = 0;
+
+	/* Enable/Disable VPU based on CMOS settings */
+	if (get_uint_option("vpu", 0) == 0)
+		DEV_PTR(vpu)->enabled = 0;
+}
diff --git a/src/mainboard/starlabs/starfighter/variants/mtl/gpio.c b/src/mainboard/starlabs/starfighter/variants/mtl/gpio.c
new file mode 100644
index 0000000000..63d8218f80
--- /dev/null
+++ b/src/mainboard/starlabs/starfighter/variants/mtl/gpio.c
@@ -0,0 +1,260 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <variants.h>
+
+/* Early pad configuration in bootblock */
+const struct pad_config early_gpio_table[] = {
+	/* Debug Connector */
+	PAD_CFG_NF(GPP_H08, NONE, DEEP, NF1),				/* RXD */
+	PAD_CFG_NF(GPP_H09, NONE, DEEP, NF1),				/* TXD */
+
+	/* SMBus */
+	PAD_CFG_NF(GPP_C00, NONE, DEEP, NF1),				/* Clock */
+	PAD_CFG_NF(GPP_C01, NONE, DEEP, NF1),				/* Data */
+
+	/* Board ID */
+	PAD_CFG_GPI_LOCK(GPP_B05, NONE, LOCK_CONFIG),
+	PAD_CFG_GPI_LOCK(GPP_B06, NONE, LOCK_CONFIG),
+	PAD_CFG_GPI_LOCK(GPP_B07, NONE, LOCK_CONFIG),
+	PAD_CFG_GPI_LOCK(GPP_B08, NONE, LOCK_CONFIG),
+};
+
+const struct pad_config *variant_early_gpio_table(size_t *num)
+{
+	*num = ARRAY_SIZE(early_gpio_table);
+	return early_gpio_table;
+}
+
+/* Pad configuration in ramstage. */
+const struct pad_config gpio_table[] = {
+	/* General Purpose I/O Deep */
+	PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_V00, NONE, DEEP, NF1),		/* Battery Low */
+	PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_V01, NONE, DEEP, NF1),		/* Charger Connected */
+	PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_V03, UP_20K, DEEP, NF1),	/* Power Button */
+	PAD_CFG_NF(GPP_V04, NONE, DEEP, NF1),				/* Sleep S3 */
+	PAD_CFG_NF(GPP_V05, NONE, DEEP, NF1),				/* Sleep S4 */
+	PAD_CFG_NF(GPP_V08, NONE, DEEP, NF1),				/* Bluetooth Suspend */
+
+	/* eSPI  */
+	PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_A00, UP_20K, DEEP, NF1),	/* eSPI IO 0 */
+	PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_A01, UP_20K, DEEP, NF1),	/* eSPI IO 1 */
+	PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_A02, UP_20K, DEEP, NF1),	/* eSPI IO 2 */
+	PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_A03, UP_20K, DEEP, NF1),	/* eSPI IO 3 */
+	PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_A04, UP_20K, DEEP, NF1),	/* eSPI CS 0 */
+	PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_A05, UP_20K, DEEP, NF1),	/* eSPI Clk */
+	PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_A06, NONE, DEEP, NF1),		/* eSPI Reset */
+
+	/* Touchpad */
+	PAD_CFG_NF(GPP_H19, NONE, DEEP, NF1),				/* Data */
+	PAD_CFG_NF(GPP_H20, NONE, DEEP, NF1),				/* Clock */
+	PAD_CFG_GPI_APIC(GPP_B00, NONE, DEEP, LEVEL, INVERT),		/* Interrupt */
+
+	/* SSD (CPU)*/
+	PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_D20, NONE, PLTRST, NF1),	/* Clock Request 8 */
+	PAD_CFG_GPO(GPP_A20, 1, PLTRST),				/* Reset */
+	PAD_CFG_GPO(GPP_H07, 1, DEEP),					/* Enable */
+
+	/* SSD (PCH) */
+	PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_C10, NONE, PLTRST, NF1),	/* Clock Request 1 */
+	PAD_CFG_GPO(GPP_H00, 1, PLTRST),				/* Reset */
+	PAD_CFG_GPO(GPP_D22, 1, DEEP),					/* Enable */
+
+	/* Wireless */
+	PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_D21, NONE, PLTRST, NF2),	/* Clock Request 5 */
+	PAD_CFG_GPO(GPP_H02, 1, PLTRST),				/* Reset */
+	PAD_CFG_GPO(GPP_B19, 1, DEEP),					/* WiFi RF Kill */
+	PAD_CFG_GPO(GPP_B18, 1, DEEP),					/* Bluetooth RF Kill */
+
+	/* Display */
+	PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1),				/* eDP Hot Plug */
+	PAD_CFG_NF(GPP_B16, NONE, DEEP, NF2),				/* HDMI Hot Plug */
+	PAD_CFG_NF(GPP_H16, NONE, DEEP, NF1),				/* HDMI Clock */
+	PAD_CFG_NF(GPP_H17, NONE, DEEP, NF1),				/* HDMI Data */
+	PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_A21, NONE, DEEP, NF1),		/* PMC Interrupt */
+	PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_C06, NONE, DEEP, NF1),		/* SML Clock */
+	PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_C07, NONE, DEEP, NF1),		/* SML Data */
+
+	/* Retimer */
+	PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1),				/* TBT0 TXD */
+	PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1),				/* TBT0 RXD */
+	PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1),				/* TBT1 TXD */
+	PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1),				/* TBT1 RXD */
+	PAD_CFG_GPO(GPP_B21, 0, DEEP),					/* Force Power */
+
+	/* High-Definition Audio */
+	PAD_CFG_NF(GPP_D10, NATIVE, DEEP, NF1),				/* Clock */
+	PAD_CFG_NF(GPP_D11, NATIVE, DEEP, NF1),				/* Sync */
+	PAD_CFG_NF(GPP_D12, NATIVE, DEEP, NF1),				/* Data Output */
+	PAD_CFG_NF(GPP_D13, NATIVE, DEEP, NF1),				/* Data Input */
+	PAD_CFG_NF(GPP_D17, NATIVE, DEEP, NF1),				/* Reset */
+
+	/* PCH */
+	PAD_CFG_NF(GPP_H13, NONE, DEEP, NF1),				/* C10 Gate */
+	PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1),				/* Platform Reset */
+	PAD_CFG_GPI_SCI(GPP_E16, NONE, PLTRST, EDGE_SINGLE, INVERT),	/* Processor Hot */
+
+	/* TPM */
+	PAD_CFG_GPI_APIC_LOW(GPP_F13, NONE, PLTRST),			/* Interrupt */
+
+	/* Config Straps									[ Low      / High     ] */
+	PAD_CFG_GPO(GPP_B14, 0, PLTRST),				/* Top Swap		[ Disabled / Enabled  ] */
+	PAD_CFG_GPO(GPP_B04, 0, PLTRST),				/* Reboot Support	[ Enabled  / Disabled ] */
+	PAD_CFG_GPO(GPP_C02, 1, PLTRST),				/* TLS Confidentiality	[ Disabled / Enabled  ] */
+	PAD_CFG_GPO(GPP_C05, 0, PLTRST),				/* eSPI			[ Enabled  / Disabled ] */
+	PAD_CFG_GPO(GPP_E06, 0, PLTRST),				/* JTAG ODT		[ Disabled / Enabled  ] */
+	PAD_CFG_GPO(GPP_F02, 0, PLTRST),				/* M.2 CNVi		[ Enabled  / Disabled ] */
+	PAD_CFG_GPO(GPP_H01, 0, PLTRST),				/* Flash Recovery	[ Disabled / Enabled  ] */
+	PAD_CFG_GPO(GPP_F20, 0, PLTRST),				/* SVID			[ Present  / Disabled ] */
+	PAD_CFG_GPO(GPP_F21, 0, PLTRST),				/* CCD			[ BSSB-LS  / BALTIC   ] */
+
+	PAD_NC(GPP_V02, NONE),
+	PAD_NC(GPP_V06, NONE),
+	PAD_NC(GPP_V07, NONE),
+	PAD_NC(GPP_V09, NONE),
+	PAD_NC(GPP_V10, NONE),
+	PAD_NC(GPP_V11, NONE),
+	PAD_NC(GPP_V12, NONE),
+	PAD_NC(GPP_V13, NONE),
+	PAD_NC(GPP_V14, NONE),
+	PAD_NC(GPP_V15, NONE),
+	PAD_NC(GPP_V16, NONE),
+	PAD_NC(GPP_V17, NONE),
+	PAD_NC(GPP_V18, NONE),
+	PAD_NC(GPP_V19, NONE),
+	PAD_NC(GPP_V20, NONE),
+	PAD_NC(GPP_V21, NONE),
+	PAD_NC(GPP_V22, NONE),
+	PAD_NC(GPP_V23, NONE),
+
+	PAD_NC(GPP_C03, NONE),
+	PAD_NC(GPP_C04, NONE),
+	PAD_NC(GPP_C08, NONE),
+	PAD_NC(GPP_C09, NONE),
+	PAD_NC(GPP_C11, NONE),
+	PAD_NC(GPP_C12, NONE),
+	PAD_NC(GPP_C13, NONE),
+	PAD_NC(GPP_C14, NONE),
+	PAD_NC(GPP_C15, NONE),
+	PAD_NC(GPP_C20, NONE),
+	PAD_NC(GPP_C21, NONE),
+	PAD_NC(GPP_C22, NONE),
+	PAD_NC(GPP_C23, NONE),
+
+	PAD_NC(GPP_A07, NONE),
+	PAD_NC(GPP_A08, NONE),
+	PAD_NC(GPP_A09, NONE),
+	PAD_NC(GPP_A10, NONE),
+	PAD_NC(GPP_A11, NONE),
+	PAD_NC(GPP_A12, NONE),
+	PAD_NC(GPP_A13, NONE),
+	PAD_NC(GPP_A14, NONE),
+	PAD_NC(GPP_A15, NONE),
+	PAD_NC(GPP_A16, NONE),
+	PAD_NC(GPP_A17, NONE),
+	PAD_NC(GPP_A18, NONE),
+	PAD_NC(GPP_A19, NONE),
+	PAD_NC(GPP_A22, NONE),
+	PAD_NC(GPP_A23, NONE),
+
+	PAD_NC(GPP_E00, NONE),
+	PAD_NC(GPP_E01, NONE),
+	PAD_NC(GPP_E02, NONE),
+	PAD_NC(GPP_E03, NONE),
+	PAD_NC(GPP_E04, NONE),
+	PAD_NC(GPP_E05, NONE),
+	PAD_NC(GPP_E07, NONE),
+	PAD_NC(GPP_E08, NONE),
+	PAD_NC(GPP_E09, NONE),
+	PAD_NC(GPP_E10, NONE),
+	PAD_NC(GPP_E11, NONE),
+	PAD_NC(GPP_E12, NONE),
+	PAD_NC(GPP_E13, NONE),
+	PAD_NC(GPP_E15, NONE),
+	PAD_NC(GPP_E17, NONE),
+	PAD_NC(GPP_E18, NONE),
+	PAD_NC(GPP_E19, NONE),
+	PAD_NC(GPP_E20, NONE),
+	PAD_NC(GPP_E21, NONE),
+	PAD_NC(GPP_E22, NONE),
+	PAD_NC(GPP_E23, NONE),
+
+	PAD_NC(GPP_H03, NONE),
+	PAD_NC(GPP_H04, NONE),
+	PAD_NC(GPP_H05, NONE),
+	PAD_NC(GPP_H06, NONE),
+	PAD_NC(GPP_H10, NONE),
+	PAD_NC(GPP_H11, NONE),
+	PAD_NC(GPP_H12, NONE),
+	PAD_NC(GPP_H14, NONE),
+	PAD_NC(GPP_H15, NONE),
+	PAD_NC(GPP_H18, NONE),
+	PAD_NC(GPP_H21, NONE),
+	PAD_NC(GPP_H22, NONE),
+	PAD_NC(GPP_H23, NONE),
+
+	PAD_NC(GPP_F00, NONE),
+	PAD_NC(GPP_F01, NONE),
+	PAD_NC(GPP_F03, NONE),
+	PAD_NC(GPP_F04, NONE),
+	PAD_NC(GPP_F05, NONE),
+	PAD_NC(GPP_F06, NONE),
+	PAD_NC(GPP_F07, NONE),
+	PAD_NC(GPP_F08, NONE),
+	PAD_NC(GPP_F09, NONE),
+	PAD_NC(GPP_F10, NONE),
+	PAD_NC(GPP_F11, NONE),
+	PAD_NC(GPP_F12, NONE),
+	PAD_NC(GPP_F14, NONE),
+	PAD_NC(GPP_F15, NONE),
+	PAD_NC(GPP_F16, NONE),
+	PAD_NC(GPP_F17, NONE),
+	PAD_NC(GPP_F18, NONE),
+	PAD_NC(GPP_F19, NONE),
+	PAD_NC(GPP_F22, NONE),
+	PAD_NC(GPP_F23, NONE),
+
+	PAD_NC(GPP_S00, NONE),
+	PAD_NC(GPP_S01, NONE),
+	PAD_NC(GPP_S02, NONE),
+	PAD_NC(GPP_S03, NONE),
+	PAD_NC(GPP_S04, NONE),
+	PAD_NC(GPP_S05, NONE),
+	PAD_NC(GPP_S06, NONE),
+	PAD_NC(GPP_S07, NONE),
+
+	PAD_NC(GPP_B01, NONE),
+	PAD_NC(GPP_B02, NONE),
+	PAD_NC(GPP_B03, NONE),
+	PAD_NC(GPP_B09, NONE),
+	PAD_NC(GPP_B10, NONE),
+	PAD_NC(GPP_B11, NONE),
+	PAD_NC(GPP_B12, NONE),
+	PAD_NC(GPP_B15, NONE),
+	PAD_NC(GPP_B17, NONE),
+	PAD_NC(GPP_B20, NONE),
+	PAD_NC(GPP_B22, NONE),
+	PAD_NC(GPP_B23, NONE),
+
+	PAD_NC(GPP_D00, NONE),
+	PAD_NC(GPP_D01, NONE),
+	PAD_NC(GPP_D02, NONE),
+	PAD_NC(GPP_D03, NONE),
+	PAD_NC(GPP_D04, NONE),
+	PAD_NC(GPP_D05, NONE),
+	PAD_NC(GPP_D06, NONE),
+	PAD_NC(GPP_D07, NONE),
+	PAD_NC(GPP_D08, NONE),
+	PAD_NC(GPP_D09, NONE),
+	PAD_NC(GPP_D14, NONE),
+	PAD_NC(GPP_D15, NONE),
+	PAD_NC(GPP_D16, NONE),
+	PAD_NC(GPP_D18, NONE),
+	PAD_NC(GPP_D19, NONE),
+	PAD_NC(GPP_D23, NONE),
+};
+
+const struct pad_config *variant_gpio_table(size_t *num)
+{
+	*num = ARRAY_SIZE(gpio_table);
+	return gpio_table;
+}
diff --git a/src/mainboard/starlabs/starfighter/variants/mtl/hda_verb.c b/src/mainboard/starlabs/starfighter/variants/mtl/hda_verb.c
new file mode 100644
index 0000000000..9c73edc6ab
--- /dev/null
+++ b/src/mainboard/starlabs/starfighter/variants/mtl/hda_verb.c
@@ -0,0 +1,105 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <device/azalia_device.h>
+#include <device/azalia_codec/realtek.h>
+
+const u32 cim_verb_data[] = {
+	/* coreboot specific header */
+	0x10ec0235,	/* Codec Vendor / Device ID: Realtek ALC235 */
+	0x20147017,	/* Subsystem ID */
+	18,		/* Number of verb entries */
+
+	/* Reset Codec First */
+	AZALIA_RESET(0x1),
+
+	/* HDA Codec Subsystem ID */
+	AZALIA_SUBVENDOR(0, 0x20147017),
+
+	/* Pin Widget Verb-table */
+	AZALIA_PIN_CFG(0, ALC269_DMIC12,	AZALIA_PIN_DESC(
+							AZALIA_INTEGRATED,
+							AZALIA_MOBILE_LID_INSIDE,
+							AZALIA_MIC_IN,
+							AZALIA_OTHER_DIGITAL,
+							AZALIA_COLOR_UNKNOWN,
+							AZALIA_NO_JACK_PRESENCE_DETECT,
+							3,
+							0
+						)),
+	AZALIA_PIN_CFG(0, ALC269_MIC2,		AZALIA_PIN_DESC(
+							AZALIA_JACK,
+							AZALIA_EXTERNAL_PRIMARY_CHASSIS | AZALIA_RIGHT,
+							AZALIA_MIC_IN,
+							AZALIA_STEREO_MONO_1_8,
+							AZALIA_BLACK,
+							AZALIA_JACK_PRESENCE_DETECT,
+							4,
+							0
+						)),
+	/* Internal speakers are connected to LINE2 and external amps */
+	AZALIA_PIN_CFG(0, ALC269_LINE2,		AZALIA_PIN_DESC(
+							AZALIA_INTEGRATED,
+							AZALIA_INTERNAL | AZALIA_FRONT,
+							AZALIA_SPEAKER,
+							AZALIA_OTHER_ANALOG,
+							AZALIA_COLOR_UNKNOWN,
+							AZALIA_NO_JACK_PRESENCE_DETECT,
+							1,
+							0
+						)),
+	AZALIA_PIN_CFG(0, ALC269_VB_HP_OUT,	AZALIA_PIN_DESC(
+							AZALIA_JACK,
+							AZALIA_EXTERNAL_PRIMARY_CHASSIS | AZALIA_RIGHT,
+							AZALIA_HP_OUT,
+							AZALIA_STEREO_MONO_1_8,
+							AZALIA_BLACK,
+							AZALIA_JACK_PRESENCE_DETECT,
+							2,
+							0
+						)),
+	AZALIA_PIN_CFG(0, ALC269_PC_BEEP,    AZALIA_PIN_DESC(
+							AZALIA_NC,
+							AZALIA_EXTERNAL_PRIMARY_CHASSIS | AZALIA_GEOLOCATION_NA,
+							AZALIA_LINE_IN,
+							AZALIA_OTHER_DIGITAL,
+							AZALIA_PINK,
+							0xa,
+							4,
+							5
+						)),
+	AZALIA_PIN_CFG(0, 0x20,			AZALIA_PIN_CFG_NC(0)),
+	AZALIA_PIN_CFG(0, ALC269_MONO,		AZALIA_PIN_CFG_NC(0)),
+	AZALIA_PIN_CFG(0, ALC269_MIC1,		AZALIA_PIN_CFG_NC(0)),
+	AZALIA_PIN_CFG(0, ALC269_SPEAKERS,	AZALIA_PIN_CFG_NC(0)),
+	AZALIA_PIN_CFG(0, ALC269_LINE1,		AZALIA_PIN_CFG_NC(0)),
+	AZALIA_PIN_CFG(0, ALC269_SPDIF_OUT,	AZALIA_PIN_CFG_NC(0)),
+
+	0x05750003,
+	0x057486a6,
+	0x02050034,
+	0x02048204,
+
+	0x0205001b,
+	0x02040a0b,
+	0x02050046,
+	0x02040004,
+
+	0x02050008,
+	0x02046a0c,
+	0x02050040,
+	0x02041800,
+
+	0x02050037,
+	0x02044a06,
+	0x0205004c,
+	0x02044803,
+
+	0x02050019,
+	0x02040a10,
+	0x02050035,
+	0x020488aa,
+};
+
+const u32 pc_beep_verbs[] = {};
+
+AZALIA_ARRAY_SIZES;
diff --git a/src/mainboard/starlabs/starfighter/variants/mtl/ramstage.c b/src/mainboard/starlabs/starfighter/variants/mtl/ramstage.c
new file mode 100644
index 0000000000..b58fda0204
--- /dev/null
+++ b/src/mainboard/starlabs/starfighter/variants/mtl/ramstage.c
@@ -0,0 +1,24 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <option.h>
+#include <drivers/intel/gma/opregion.h>
+#include <soc/ramstage.h>
+#include <variants.h>
+#include <common/pin_mux.h>
+
+void mainboard_silicon_init_params(FSP_S_CONFIG *supd)
+{
+	configure_pin_mux(supd);
+	supd->TcNotifyIgd = 2; // Auto
+}
+
+const char *mainboard_vbt_filename(void)
+{
+	if (get_uint_option("display_native_res", 0) == 1)
+		return "vbt_native_res.bin";
+
+
+	if (get_memory_config_straps() == 13)
+		return "vbt_qhd.bin";
+	return "vbt.bin";
+}
diff --git a/src/mainboard/starlabs/starfighter/variants/mtl/romstage.c b/src/mainboard/starlabs/starfighter/variants/mtl/romstage.c
new file mode 100644
index 0000000000..8281dd0ebb
--- /dev/null
+++ b/src/mainboard/starlabs/starfighter/variants/mtl/romstage.c
@@ -0,0 +1,106 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <option.h>
+#include <soc/meminit.h>
+#include <soc/romstage.h>
+#include <types.h>
+#include <variants.h>
+
+static uint8_t strap_to_cbfs_index(uint8_t strap)
+{
+	switch (strap) {
+	case 13:	// 32GB
+		return 0;
+	default:	// 64GB
+		return 1;
+	}
+}
+
+void mainboard_memory_init_params(FSPM_UPD *mupd)
+{
+	const struct mb_cfg mem_config = {
+		.type = MEM_TYPE_LP5X,
+
+		.lpx_dq_map = {
+			.ddr0 = {
+				.dq0 = {  8, 11, 10,  9, 15, 12, 13, 14 },
+				.dq1 = {  4,  7,  5,  6,  3,  1,  2,  0 },
+			},
+			.ddr1 = {
+				.dq0 = {  2,  0,  3,  1,  4,  6,  7,  5 },
+				.dq1 = { 13, 10, 12, 15, 11,  8,  9, 14 },
+			},
+			.ddr2 = {
+				.dq0 = {  0,  3,  1,  2,  4,  7,  6,  5 },
+				.dq1 = {  8, 15,  9, 12, 10, 11, 14, 13 },
+			},
+			.ddr3 = {
+				.dq0 = { 13, 10,  8,  9, 14, 11, 15, 12 },
+				.dq1 = {  1,  6,  4,  7,  0,  5,  2,  3 },
+			},
+			.ddr4 = {
+				.dq0 = { 10, 11,  9, 12, 13, 14, 15,  8 },
+				.dq1 = {  6,  7,  4,  5,  1,  0,  3,  2 },
+			},
+			.ddr5 = {
+				.dq0 = {  0,  5,  3,  6,  1,  4,  2,  7 },
+				.dq1 = {  8, 11, 10,  9, 15, 14, 13, 12 },
+			},
+			.ddr6 = {
+				.dq0 = {  1,  3,  0,  2,  6,  5,  7,  4 },
+				.dq1 = { 13, 15, 14, 12, 11, 10,  8,  9 },
+			},
+			.ddr7 = {
+				.dq0 = { 10,  9, 11,  8, 12, 15, 14, 13 },
+				.dq1 = {  6,  4,  7,  5,  2,  1,  0,  3 },
+			},
+		},
+
+		/* DQS CPU<>DRAM map */
+		.lpx_dqs_map = {
+			.ddr0 = { .dqs0 = 1, .dqs1 = 0 },
+			.ddr1 = { .dqs0 = 0, .dqs1 = 1 },
+			.ddr2 = { .dqs0 = 0, .dqs1 = 1 },
+			.ddr3 = { .dqs0 = 1, .dqs1 = 0 },
+			.ddr4 = { .dqs0 = 1, .dqs1 = 0 },
+			.ddr5 = { .dqs0 = 0, .dqs1 = 1 },
+			.ddr6 = { .dqs0 = 0, .dqs1 = 1 },
+			.ddr7 = { .dqs0 = 1, .dqs1 = 0 },
+		},
+
+		.ect			= true,
+
+		.LpDdrDqDqsReTraining	= 1,
+
+		.UserBd			= BOARD_TYPE_ULT_ULX,
+		.lp5x_config = {
+			.ccc_config	= 0x66,
+		}
+	};
+
+	const bool half_populated = false;
+
+	const struct mem_spd lpddr5_spd_info = {
+		.topo = MEM_TOPO_MEMORY_DOWN,
+		.cbfs_index = strap_to_cbfs_index(get_memory_config_straps()),
+	};
+
+	memcfg_init(mupd, &mem_config, &lpddr5_spd_info, half_populated);
+
+	const uint8_t vtd = get_uint_option("vtd", 1);
+	mupd->FspmConfig.VtdDisable = !vtd;
+
+	/* Enable/Disable Wireless (RP09) based on CMOS settings */
+	if (get_uint_option("wireless", 1) == 0)
+		mupd->FspmConfig.PcieRpEnableMask &= ~(1 << 8);
+
+	/* Enable/Disable Thunderbolt based on CMOS settings */
+	if (get_uint_option("thunderbolt", 1) == 0) {
+		mupd->FspmConfig.TcssDma0En = 0;
+		mupd->FspmConfig.TcssItbtPcie0En = 0;
+		mupd->FspmConfig.TcssXhciEn = 0;
+	}
+
+	mupd->FspmConfig.PchHdaSubSystemIds = 0x20147017;
+	mupd->FspmConfig.PsysPmax = 0;
+};
diff --git a/src/mainboard/starlabs/starfighter/variants/rpl/ramstage.c b/src/mainboard/starlabs/starfighter/variants/rpl/ramstage.c
index 6ffe593f7f..d17549ec3a 100644
--- a/src/mainboard/starlabs/starfighter/variants/rpl/ramstage.c
+++ b/src/mainboard/starlabs/starfighter/variants/rpl/ramstage.c
@@ -1,6 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
 #include <option.h>
+#include <drivers/intel/gma/opregion.h>
 #include <soc/ramstage.h>
 #include <common/pin_mux.h>
 
@@ -11,3 +12,11 @@ void mainboard_silicon_init_params(FSP_S_CONFIG *supd)
 	if (get_uint_option("thunderbolt", 1) == 0)
 		supd->UsbTcPortEn = 0;
 }
+
+const char *mainboard_vbt_filename(void)
+{
+	if (get_uint_option("display_native_res", 0) == 1)
+		return "vbt_native_res.bin";
+
+	return "vbt.bin";
+}

From 7afe1e9f9d7224d39313ed5edf38ac5c1119a8dd Mon Sep 17 00:00:00 2001
From: Hualin Wei <weihualin@huaqin.corp-partner.google.com>
Date: Thu, 27 Nov 2025 10:45:36 +0800
Subject: [PATCH 2619/3886] mb/google/fatcat/var/lapis: Adjust touchpanel power
 on timing

GPP_F08 -> EN_TCHSCR_PWR
GPP_F16 -> TOUCHPANEL_RESET#

Adjust touchpanel's power on timings:
1. EN_TCHSCR_PWR go high before L_VDDEN_PCH during power on
2. TOUCHPANEL_RESET# high after EN_TCHSCR_PWR high when power on

BUG=b:462913972
TEST=emerge-fatcat coreboot
the EE measured the power-on timing of the touchscreen, and it met the requirements.

Change-Id: I4e50223477003ff93d4751527196894cc0a3e781
Signed-off-by: Hualin Wei <weihualin@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90243
Reviewed-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
---
 src/mainboard/google/fatcat/variants/lapis/gpio.c | 8 ++++++--
 1 file changed, 6 insertions(+), 2 deletions(-)

diff --git a/src/mainboard/google/fatcat/variants/lapis/gpio.c b/src/mainboard/google/fatcat/variants/lapis/gpio.c
index 92d63a9e90..1f3e25dcc6 100644
--- a/src/mainboard/google/fatcat/variants/lapis/gpio.c
+++ b/src/mainboard/google/fatcat/variants/lapis/gpio.c
@@ -263,8 +263,6 @@ static const struct pad_config gpio_table[] = {
 	PAD_NC(GPP_F06, NONE),
 	/* GPP_F07:     Not used */
 	PAD_NC(GPP_F07, NONE),
-	/* GPP_F08:     TCHSCR_PWR_EN */
-	PAD_CFG_GPO(GPP_F08, 1, DEEP),
 	/* GPP_F09:     NC */
 	PAD_NC(GPP_F09, NONE),
 	/* GPP_F10:     NC */
@@ -398,6 +396,9 @@ static const struct pad_config early_gpio_table[] = {
 	/* GPP_E19:     FP_PWR_EN */
 	PAD_CFG_GPO(GPP_E19, 1, PLTRST),
 
+	/* GPP_F16:     THC0_SPI1_RST_N_TCH_PNL1 */
+	PAD_CFG_GPO(GPP_F16, 0, DEEP),
+
 	/* GPP_H08:     UART0_BUF_RXD */
 	PAD_CFG_NF(GPP_H08, NONE, DEEP, NF1),
 	/* GPP_H09:     UART0_BUF_TXD */
@@ -409,6 +410,9 @@ static const struct pad_config early_gpio_table[] = {
 	PAD_CFG_NF(GPP_H07, NONE, DEEP, NF1),
 	/* GPP_E02:     GSC_SOC_INT_ODL  */
 	PAD_CFG_GPI_APIC_LOCK(GPP_E02, NONE, LEVEL, INVERT, LOCK_CONFIG),
+
+	/* GPP_F08:     TCHSCR_PWR_EN */
+	PAD_CFG_GPO(GPP_F08, 1, DEEP),
 };
 
 /* Pad configuration in romstage */

From 2ce4e09469040effc6bb87a787dcb718440858b6 Mon Sep 17 00:00:00 2001
From: Maximilian Brune <maximilian.brune@9elements.com>
Date: Tue, 4 Nov 2025 17:00:21 +0100
Subject: [PATCH 2620/3886] drivers/intel/fsp2_0: Add typedef FSP_UPD_HEADER

The FSP structs are usually typedefs and are also used like that across
the tree.

In order to make this file usable for code inside our tree
(specifically AMD) change it to typedefs.

Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: Ie799e0116997ba559b990a9b3a2038fea852d8ba
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89901
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
---
 src/drivers/intel/fsp2_0/include/fsp/upd.h | 13 +++++++------
 1 file changed, 7 insertions(+), 6 deletions(-)

diff --git a/src/drivers/intel/fsp2_0/include/fsp/upd.h b/src/drivers/intel/fsp2_0/include/fsp/upd.h
index 153b174cc3..8c307c5748 100644
--- a/src/drivers/intel/fsp2_0/include/fsp/upd.h
+++ b/src/drivers/intel/fsp2_0/include/fsp/upd.h
@@ -5,7 +5,8 @@
 
 #include <stdint.h>
 
-struct FSP_UPD_HEADER {
+
+typedef struct {
 	///
 	/// UPD Region Signature. This signature will be
 	/// "XXXXXX_T" for FSP-T
@@ -19,10 +20,10 @@ struct FSP_UPD_HEADER {
 	///
 	uint8_t                       Revision;
 	uint8_t                       Reserved[23];
-} __packed;
+} __packed FSP_UPD_HEADER;
 
 #if CONFIG(PLATFORM_USES_FSP2_X86_32)
-struct FSPM_ARCH_UPD {
+typedef struct {
 	///
 	/// Revision of the structure. For FSP v2.0 value is 1.
 	///
@@ -53,12 +54,12 @@ struct FSPM_ARCH_UPD {
 	///
 	uint32_t                      BootMode;
 	uint8_t                       Reserved1[8];
-} __packed;
+} __packed FSPM_ARCH_UPD;
 #else
 #error You need to implement this struct for x86_64 FSP
 #endif
 
-struct FSPS_ARCH_UPD {
+typedef struct {
 	///
 	/// Revision of the structure. For FSP v2.2 value is 1.
 	///
@@ -74,6 +75,6 @@ struct FSPS_ARCH_UPD {
 	///
 	uint8_t                       EnableMultiPhaseSiliconInit;
 	uint8_t                       Reserved2[19];
-} __packed;
+} __packed FSPS_ARCH_UPD;
 
 #endif /* _FSP2_0_UPD_H_ */

From 796d3b37aa3dddf2a6ae4bc2bdfd3cb8d24cffd1 Mon Sep 17 00:00:00 2001
From: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
Date: Wed, 26 Nov 2025 13:31:46 +0800
Subject: [PATCH 2621/3886] mb/google/fatcat/var/moonstone: Update fw_config
 definitions with UFSC

Enable Unified Firmware and Secondary Source Configuration (UFSC)
support for moonstone.
UFSC standardizes the bitfields and bitmap definitions for firmware
configuration. Update coreboot code with new UFSC definitions and
enable EC_GOOGLE_CHROMEEC_FW_CONFIG_FROM_UFSC.

BUG=b:464077440
TEST=emerge-fatcat coreboot depthcharge chromeos-bootimage
BRANCH=none

Change-Id: I8ecd9accb4ad09aae3a6fb9e3f92d8d0a3c9bb9c
Signed-off-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90258
Reviewed-by: Bob Moragues <moragues@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/google/fatcat/Kconfig           |  1 +
 .../fatcat/variants/moonstone/fw_config.c     | 24 +----
 .../fatcat/variants/moonstone/overridetree.cb | 96 ++++++++++++-------
 .../fatcat/variants/moonstone/variant.c       | 10 +-
 4 files changed, 70 insertions(+), 61 deletions(-)

diff --git a/src/mainboard/google/fatcat/Kconfig b/src/mainboard/google/fatcat/Kconfig
index d66905ab67..b38a4e90b9 100644
--- a/src/mainboard/google/fatcat/Kconfig
+++ b/src/mainboard/google/fatcat/Kconfig
@@ -147,6 +147,7 @@ config BOARD_GOOGLE_LAPIS
 config BOARD_GOOGLE_MOONSTONE
 	select BOARD_GOOGLE_BASEBOARD_FATCAT
 	select DRIVERS_SOUNDWIRE_ALC1320
+	select EC_GOOGLE_CHROMEEC_FW_CONFIG_FROM_UFSC
 	select FSP_UGOP_EARLY_SIGN_OF_LIFE
 	select HAVE_SLP_S0_GATE
 	select MAINBOARD_HAS_GOOGLE_STRAUSS_KEYBOARD
diff --git a/src/mainboard/google/fatcat/variants/moonstone/fw_config.c b/src/mainboard/google/fatcat/variants/moonstone/fw_config.c
index 22168413ba..baff0bd640 100644
--- a/src/mainboard/google/fatcat/variants/moonstone/fw_config.c
+++ b/src/mainboard/google/fatcat/variants/moonstone/fw_config.c
@@ -77,17 +77,6 @@ static const struct pad_config pre_mem_fp_spi_enable_pads[] = {
 	PAD_CFG_GPO(GPP_C15, 0, DEEP),
 };
 
-static const struct pad_config touchscreen_disable_pads[] = {
-	/* GPP_F08:     EN_TCHSCR_PWR => NC */
-	PAD_NC(GPP_F08, NONE),
-	/* GPP_F16:     TCHSCR_RST_L => NC */
-	PAD_NC(GPP_F16, NONE),
-	/* GPP_F18:     TCHSCR_INT_L => NC */
-	PAD_NC(GPP_F18, NONE),
-	/* GPP_E05:     TCHSCR_RPT_EN => NC */
-	PAD_NC(GPP_E05, NONE),
-};
-
 void fw_config_configure_pre_mem_gpio(void)
 {
 	if (!fw_config_is_provisioned()) {
@@ -95,7 +84,7 @@ void fw_config_configure_pre_mem_gpio(void)
 		return;
 	}
 
-	if (fw_config_probe(FW_CONFIG(FPMCU, FP_SPI)))
+	if (fw_config_probe(FW_CONFIG(FINGERPRINT_INTERFACE, FINGERPRINT_INTERFACE_SPI)))
 		GPIO_CONFIGURE_PADS(pre_mem_fp_spi_enable_pads);
 
 }
@@ -113,7 +102,7 @@ void fw_config_gpio_padbased_override(struct pad_config *padbased_table)
 	 *| FPMCU | GSPI0  | usb2_port6  |
 	 *+-------+--------+-------------+
 	 */
-	if (fw_config_probe(FW_CONFIG(FPMCU, FP_SPI))) {
+	if (fw_config_probe(FW_CONFIG(FINGERPRINT_INTERFACE, FINGERPRINT_INTERFACE_SPI))) {
 		GPIO_PADBASED_OVERRIDE(padbased_table, fp_spi_enable_pads);
 	} else {
 		GPIO_PADBASED_OVERRIDE(padbased_table, fp_spi_disable_pads);
@@ -121,10 +110,10 @@ void fw_config_gpio_padbased_override(struct pad_config *padbased_table)
 	/* Probe fw_config : "IO_PORT" to reconfigure port settings accordingly.
 	 * proto0  : IO_PORT => "USB2A2C_HDMI:0"
 	 * porot1.5: IO_PORT => "USB3C:1"
-	 * +-----------------+------------------+------------------+
+	 *+-----------------+------------------+------------------+
 	 *| IO_PORT         | USB2A2C_HDMI     |  USB3C           |
 	 *+-----------------+------------------+------------------+
-	 *| tcss_usb3_port0 | USB4_C0 (MB-TBT) | USB4_C0 (MB-TBT) |
+	 *| tcss_usb3_port0 | USB4_C0 (MB-TBT) | USB4_C0 (MB)     |
 	 *+-----------------+------------------+------------------+
 	 *| tcss_usb3_port1 | N/A              | USB3.2 C2 (DB)   |
 	 *+-----------------+------------------+------------------+
@@ -141,11 +130,8 @@ void fw_config_gpio_padbased_override(struct pad_config *padbased_table)
 	 *| usb2_port6      | USB2_A1          | USB_FP           |
 	 *+-----------------+------------------+------------------+
 	 */
-	if (fw_config_probe(FW_CONFIG(IO_PORT, USB3C)))
+	if (fw_config_probe(FW_CONFIG(AP_OEM_2BIT_FIELD0, IO_BOARD_USB3C)))
 		GPIO_PADBASED_OVERRIDE(padbased_table, use_usb3c_enable_pads);
 	else
 		GPIO_PADBASED_OVERRIDE(padbased_table, use_usb2a2c_hdmi_enable_pads);
-
-	if (fw_config_probe(FW_CONFIG(TOUCH_SCREEN, ABSENCE)))
-		GPIO_PADBASED_OVERRIDE(padbased_table, touchscreen_disable_pads);
 }
diff --git a/src/mainboard/google/fatcat/variants/moonstone/overridetree.cb b/src/mainboard/google/fatcat/variants/moonstone/overridetree.cb
index 8f02787cb2..17d461248c 100644
--- a/src/mainboard/google/fatcat/variants/moonstone/overridetree.cb
+++ b/src/mainboard/google/fatcat/variants/moonstone/overridetree.cb
@@ -1,24 +1,45 @@
 fw_config
-	field WIFI 2 2
-		option WIFI_CNVI_7		0
+	field AUDIO_CODEC 0 2
+		option AUDIO_CODEC_UNKNOWN	0
+		option AUDIO_CODEC_ALC721	1
 	end
-	field AUDIO 3 5
-		option AUDIO_UNKNOWN				0
-		option AUDIO_ALC721_SNDW			1
-		option AUDIO_ALC1320_ALC721_SNDW	2
+	field AUDIO_AMPLIFIER 3 5
+		option AUDIO_AMPLIFIER_UNKNOWN	0
+		option AUDIO_AMPLIFIER_ALC1320	1
 	end
-	field FPMCU 6 7
-		option FP_ABSENT		0
-		option FP_SPI			1
-		option FP_USB			2
+	field STORAGE_TYPE 12 14
+		option STORAGE_TYPE_UNKNOWN	0
+		option STORAGE_TYPE_NVME_GEN4	1
 	end
-	field IO_PORT 12 12
-		option USB2A2C_HDMI		0
-		option USB3C			1
+	field SENSOR_HUB_PRESENT 23 23
+		option ISH_ABSENT	0
+		option ISH_PRESENT	1
 	end
-	field TOUCH_SCREEN 13 13
-		option ABSENCE			0
-		option PRESENCE			1
+	field FINGERPRINT_INTERFACE 24 25
+		option FINGERPRINT_INTERFACE_UNKNOWN	0
+		option FINGERPRINT_INTERFACE_SPI	1
+		option FINGERPRINT_INTERFACE_USB	2
+	end
+	field WIFI_INTERFACE 26 27
+		option WIFI_INTERFACE_UNKNOWN	0
+		option WIFI_INTERFACE_CNVI	1
+	end
+	field FORM_FACTOR 30 31
+		option FORM_FACTOR_UNKNOWN	0
+		option FORM_FACTOR_CLAMSHELL	1
+		option FORM_FACTOR_CONVERTIBLE	2
+	end
+	field KB_BACKLIGHT_PRESENT 43 43
+		option KB_BACKLIGHT_ABSENT	0
+		option KB_BACKLIGHT_PRESENT	1
+	end
+	field KEYBOARD_LAYOUT 45 47
+		option KEYBOARD_LAYOUT_DEFAULT	0
+		option KEYBOARD_LAYOUT_CA_FR	1
+	end
+	field AP_OEM_2BIT_FIELD0 59 60
+		option IO_BOARD_USB2A2C_HDMI	0
+		option IO_BOARD_USB3C	1
 	end
 end
 
@@ -222,9 +243,11 @@ chip soc/intel/pantherlake
 
 		device ref iaa off end
 		device ref tbt_pcie_rp2 on
-			probe IO_PORT USB2A2C_HDMI
+			probe AP_OEM_2BIT_FIELD0 IO_BOARD_USB2A2C_HDMI
+		end
+		device ref tbt_pcie_rp3 on
+			probe AP_OEM_2BIT_FIELD0 IO_BOARD_USB3C
 		end
-		device ref tbt_pcie_rp3 on end
 		device ref tcss_xhci on
 			chip drivers/usb/acpi
 				device ref tcss_root_hub on
@@ -239,7 +262,7 @@ chip soc/intel/pantherlake
 						register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
 						register "group" = "ACPI_PLD_GROUP(3, 2)"
 						device ref tcss_usb3_port1 on
-							probe IO_PORT USB3C
+							probe AP_OEM_2BIT_FIELD0 IO_BOARD_USB3C
 						end
 					end
 					chip drivers/usb/acpi
@@ -247,7 +270,7 @@ chip soc/intel/pantherlake
 						register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
 						register "group" = "ACPI_PLD_GROUP(2, 2)"
 						device ref tcss_usb3_port2 on
-							probe IO_PORT USB2A2C_HDMI
+							probe AP_OEM_2BIT_FIELD0 IO_BOARD_USB2A2C_HDMI
 						end
 					end
 					chip drivers/usb/acpi
@@ -255,7 +278,7 @@ chip soc/intel/pantherlake
 						register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
 						register "group" = "ACPI_PLD_GROUP(2, 2)"
 						device ref tcss_usb3_port3 on
-							probe IO_PORT USB3C
+							probe AP_OEM_2BIT_FIELD0 IO_BOARD_USB3C
 						end
 					end
 				end
@@ -267,14 +290,14 @@ chip soc/intel/pantherlake
 				register "dfp[0].power_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B21)"
 				use tcss_usb3_port2 as dfp[0].typec_port
 				device generic 0 on
-					probe IO_PORT USB2A2C_HDMI
+					probe AP_OEM_2BIT_FIELD0 IO_BOARD_USB2A2C_HDMI
 				end
 			end
 			chip drivers/intel/usb4/retimer
 				register "dfp[0].power_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B21)"
 				use tcss_usb3_port3 as dfp[0].typec_port
 				device generic 0 on
-					probe IO_PORT USB3C
+					probe AP_OEM_2BIT_FIELD0 IO_BOARD_USB3C
 				end
 			end
 		end
@@ -306,7 +329,7 @@ chip soc/intel/pantherlake
 						register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
 						register "group" = "ACPI_PLD_GROUP(3, 1)"
 						device ref usb2_port5 on
-							probe IO_PORT USB3C
+							probe AP_OEM_2BIT_FIELD0 IO_BOARD_USB3C
 						end
 					end
 					chip drivers/usb/acpi
@@ -321,7 +344,7 @@ chip soc/intel/pantherlake
 						register "type" = "UPC_TYPE_A"
 						register "group" = "ACPI_PLD_GROUP(3, 1)"
 						device ref usb2_port5 on
-							probe IO_PORT USB2A2C_HDMI
+							probe AP_OEM_2BIT_FIELD0 IO_BOARD_USB2A2C_HDMI
 						end
 					end
 					chip drivers/usb/acpi
@@ -329,7 +352,7 @@ chip soc/intel/pantherlake
 						register "type" = "UPC_TYPE_A"
 						register "group" = "ACPI_PLD_GROUP(4, 1)"
 						device ref usb2_port6 on
-							probe IO_PORT USB2A2C_HDMI
+							probe AP_OEM_2BIT_FIELD0 IO_BOARD_USB2A2C_HDMI
 						end
 					end
 					chip drivers/usb/acpi
@@ -338,7 +361,7 @@ chip soc/intel/pantherlake
 						register "has_power_resource" = "true"
 						register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E19)"
 						device ref usb2_port6 on
-							probe FPMCU FP_USB
+							probe FINGERPRINT_INTERFACE FINGERPRINT_INTERFACE_USB
 						end
 					end
 					chip drivers/usb/acpi
@@ -346,7 +369,7 @@ chip soc/intel/pantherlake
 						register "type" = "UPC_TYPE_USB3_A"
 						register "group" = "ACPI_PLD_GROUP(3, 2)"
 						device ref usb3_port1 on
-							probe IO_PORT USB2A2C_HDMI
+							probe AP_OEM_2BIT_FIELD0 IO_BOARD_USB2A2C_HDMI
 						end
 					end
 					chip drivers/usb/acpi
@@ -354,7 +377,7 @@ chip soc/intel/pantherlake
 						register "type" = "UPC_TYPE_USB3_A"
 						register "group" = "ACPI_PLD_GROUP(4, 2)"
 						device ref usb3_port2 on
-							probe IO_PORT USB2A2C_HDMI
+							probe AP_OEM_2BIT_FIELD0 IO_BOARD_USB2A2C_HDMI
 						end
 					end
 				end
@@ -432,7 +455,6 @@ chip soc/intel/pantherlake
 			end
 		end # I2C4
 		device ref i2c5 on
-			probe TOUCH_SCREEN PRESENCE
 			chip drivers/i2c/hid
 				register "generic.hid" = ""ELAN9004""
 				register "generic.desc" = ""ELAN Touchscreen""
@@ -467,7 +489,7 @@ chip soc/intel/pantherlake
 			end
 		end # I2C5
 		device ref gspi0 on
-			probe FPMCU FP_SPI
+			probe FINGERPRINT_INTERFACE FINGERPRINT_INTERFACE_SPI
 			chip drivers/spi/acpi
 				register "name" = ""CRFP""
 				register "hid" = "ACPI_DT_NAMESPACE_HID"
@@ -481,15 +503,15 @@ chip soc/intel/pantherlake
 				register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E19)"
 				register "enable_delay_ms" = "3"
 				device spi 0 on
-					probe FPMCU FP_SPI
+					probe FINGERPRINT_INTERFACE FINGERPRINT_INTERFACE_SPI
 				end
 			end
 		end
 
 		device ref smbus on end
 		device ref hda on
-			probe AUDIO AUDIO_ALC721_SNDW
-			probe AUDIO AUDIO_ALC1320_ALC721_SNDW
+			probe AUDIO_CODEC AUDIO_CODEC_ALC721
+			probe AUDIO_AMPLIFIER AUDIO_AMPLIFIER_ALC1320
 			chip drivers/intel/soundwire
 				device generic 0 on
 					chip drivers/soundwire/alc711
@@ -500,8 +522,8 @@ chip soc/intel/pantherlake
 						register "disable_clkstop_sm_support" = "true"
 						# SoundWire Link 3 ID 1
 						device generic 3.1 on
-							probe AUDIO AUDIO_ALC721_SNDW
-							probe AUDIO AUDIO_ALC1320_ALC721_SNDW
+							probe AUDIO_CODEC AUDIO_CODEC_ALC721
+							probe AUDIO_AMPLIFIER AUDIO_AMPLIFIER_ALC1320
 						end
 					end
 					chip drivers/soundwire/alc1320
@@ -511,7 +533,7 @@ chip soc/intel/pantherlake
 						register "alc1320_address.part_id" = "MIPI_DEV_ID_REALTEK_ALC1320"
 						# SoundWire Link 3 ID 2
 						device generic 3.2 on
-							probe AUDIO AUDIO_ALC1320_ALC721_SNDW
+							probe AUDIO_AMPLIFIER AUDIO_AMPLIFIER_ALC1320
 						end # ALC1320 Smart Amp
 					end
 				end
diff --git a/src/mainboard/google/fatcat/variants/moonstone/variant.c b/src/mainboard/google/fatcat/variants/moonstone/variant.c
index bf159c7e76..17ce4d2c2f 100644
--- a/src/mainboard/google/fatcat/variants/moonstone/variant.c
+++ b/src/mainboard/google/fatcat/variants/moonstone/variant.c
@@ -8,7 +8,7 @@
 
 const char *get_wifi_sar_cbfs_filename(void)
 {
-	return get_wifi_sar_fw_config_filename(FW_CONFIG_FIELD(WIFI));
+	return get_wifi_sar_fw_config_filename(FW_CONFIG_FIELD(WIFI_INTERFACE));
 }
 
 void variant_update_soc_chip_config(struct soc_intel_pantherlake_config *config)
@@ -20,7 +20,7 @@ void variant_update_soc_chip_config(struct soc_intel_pantherlake_config *config)
 	 *| FPMCU | GSPI0  | usb2_port6  |
 	 *+-------+--------+-------------+
 	 */
-	if (fw_config_probe(FW_CONFIG(FPMCU, FP_USB))) {
+	if (fw_config_probe(FW_CONFIG(FINGERPRINT_INTERFACE, FINGERPRINT_INTERFACE_USB))) {
 		printk(BIOS_INFO, "Disable GSPI\n");
 		config->serial_io_gspi_mode[PchSerialIoIndexGSPI0] = PchSerialIoDisabled;
 		printk(BIOS_INFO, "usb2_port6 to FP\n");
@@ -29,10 +29,10 @@ void variant_update_soc_chip_config(struct soc_intel_pantherlake_config *config)
 	/* Probe fw_config : "IO_PORT" to reconfigure port settings accordingly.
 	 * proto0  : IO_PORT => "USB2A2C_HDMI:0"
 	 * porot1.5: IO_PORT => "USB3C:1"
-	 * +-----------------+------------------+------------------+
+	 *+-----------------+------------------+------------------+
 	 *| IO_PORT         | USB2A2C_HDMI     |  USB3C           |
 	 *+-----------------+------------------+------------------+
-	 *| tcss_usb3_port0 | USB4_C0 (MB-TBT) | USB4_C0 (MB-TBT) |
+	 *| tcss_usb3_port0 | USB4_C0 (MB-TBT) | USB4_C0 (MB)     |
 	 *+-----------------+------------------+------------------+
 	 *| tcss_usb3_port1 | N/A              | USB3.2 C2 (DB)   |
 	 *+-----------------+------------------+------------------+
@@ -50,7 +50,7 @@ void variant_update_soc_chip_config(struct soc_intel_pantherlake_config *config)
 	 *+-----------------+------------------+------------------+
 	 */
 
-	if (fw_config_probe(FW_CONFIG(IO_PORT, USB3C))) {
+	if (fw_config_probe(FW_CONFIG(AP_OEM_2BIT_FIELD0, IO_BOARD_USB3C))) {
 		printk(BIOS_INFO, "Disable Type-A Port A0/A1\n");
 		config->usb3_ports[0] = (struct usb3_port_config) USB3_PORT_EMPTY;
 		config->usb3_ports[1] = (struct usb3_port_config) USB3_PORT_EMPTY;

From 908c2b54c63b9de5581503b2bcb97db8f84502af Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Sat, 29 Nov 2025 20:50:14 +0000
Subject: [PATCH 2622/3886] mb/starlabs/starbook/mtl: Fix Card Reader USB Port

The devtree.c was trying to disable the incorrect USB port, 3.
Correct this to 7.

Change-Id: Ibae3d104d2887706dbe2e1c13e817eeee644b5ad
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90275
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
---
 src/mainboard/starlabs/starbook/variants/mtl/devtree.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/mainboard/starlabs/starbook/variants/mtl/devtree.c b/src/mainboard/starlabs/starbook/variants/mtl/devtree.c
index fdfec7468d..296027e9e8 100644
--- a/src/mainboard/starlabs/starbook/variants/mtl/devtree.c
+++ b/src/mainboard/starlabs/starbook/variants/mtl/devtree.c
@@ -60,7 +60,7 @@ void devtree_update(void)
 
 	/* Enable/Disable Card Reader based on CMOS Settings */
 	if (get_uint_option("card_reader", 1) == 0)
-		cfg->usb2_ports[3].enable = 0;
+		cfg->usb2_ports[7].enable = 0;
 
 	/* Enable/Disable GNA based on CMOS settings */
 	if (get_uint_option("gna", 0) == 0)

From 109672a9a9ef55c511025fb26da2d884e034e16f Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Mon, 10 Nov 2025 21:32:38 +0000
Subject: [PATCH 2623/3886] drivers/intel/gma: Guard legacy brightness fallback

When BOX3.XBCM fails we currently fall back to LEGA.XBCM, which writes
directly to the IGD PWM registers. During S3 resume those registers are
still reset by the graphics driver, so AML stores a zero duty cycle and
the panel stays dark. This leads to having some other event needed to
wake the panel (i.e. key press).

Only invoke the legacy path after BCLM is initialized, matching when the
driver has reprogrammed the PWM registers and preventing firmware from
touching them while the driver is still restoring them.

Test=Enter and exit S3 on starbook_mtl, verify that the display turns on and stays on, instead of on -> off -> on.

Change-Id: I664d296372feef9de5c4f57428422328c4e33110
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89985
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
---
 .../intel/gma/acpi/configure_brightness_levels.asl       | 9 ++++++++-
 1 file changed, 8 insertions(+), 1 deletion(-)

diff --git a/src/drivers/intel/gma/acpi/configure_brightness_levels.asl b/src/drivers/intel/gma/acpi/configure_brightness_levels.asl
index a35ffe3863..b6c27fbe92 100644
--- a/src/drivers/intel/gma/acpi/configure_brightness_levels.asl
+++ b/src/drivers/intel/gma/acpi/configure_brightness_levels.asl
@@ -149,7 +149,14 @@
 	{
 		If (^BOX3.XBCM (Arg0) == Ones)
 		{
-			^LEGA.XBCM (Arg0)
+			/*
+			 * Only touch the legacy PWM registers after the graphics driver
+			 * reprograms them during boot/resume (BCLM stays zero until then).
+			 */
+			If (BCLM != 0)
+			{
+				^LEGA.XBCM (Arg0)
+			}
 		}
 	}
 

From afd5e5d4440f9829716b2a07f3a1ecbbf95255c4 Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Tue, 25 Nov 2025 11:06:06 -0600
Subject: [PATCH 2624/3886] mb/samsung/lumpy: Convert HDA verbs to use
 AZALIA_PIN_DESC macros

Convert raw hexadecimal pin configuration values to use the
AZALIA_PIN_DESC macro for improved readability and maintainability.

All pin configurations have been verified to generate identical
binary output to the original raw verbs:
  - NID 0x05: Headphone Jack (0x022110f0)
  - NID 0x06: Internal Speaker (0x901700f0)
  - NID 0x07: Microphone Jack (0x02a110f0)
  - NID 0x08: Unused/NC (0x77a70037)
  - NID 0x09: Unused/NC (0xb7a6003e)
  - NID 0x0a: SPDIF Out/NC (0x434510f0)

No functional changes.

Change-Id: Ib2f531575dd0e3cccf41b74e861394f21ce237af
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90215
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
---
 src/mainboard/samsung/lumpy/hda_verb.c | 85 +++++++++++++++++++++-----
 1 file changed, 70 insertions(+), 15 deletions(-)

diff --git a/src/mainboard/samsung/lumpy/hda_verb.c b/src/mainboard/samsung/lumpy/hda_verb.c
index b3350a1300..8c538d6853 100644
--- a/src/mainboard/samsung/lumpy/hda_verb.c
+++ b/src/mainboard/samsung/lumpy/hda_verb.c
@@ -11,30 +11,85 @@ const u32 cim_verb_data[] = {
 	/* NID 0x01, HDA Codec Subsystem ID Verb Table: 0x152D0924 */
 	AZALIA_SUBVENDOR(0, 0x152D0924),
 
+	/* Padding - Power up sequence */
+	0x00170500,
+	0x00170500,
+	0x00170500,
 	0x00170500,
-	0x00170500,	/* Padding */
-	0x00170500,	/* Padding */
-	0x00170500,	/* Padding */
 
 	/* Pin Widget Verb Table */
 
-	/* Pin Complex (NID 0x05) */
-	AZALIA_PIN_CFG(0, 0x05, 0x022110f0),
+	/* Pin Complex (NID 0x05) - Headphone Jack */
+	AZALIA_PIN_CFG(0, 0x05, AZALIA_PIN_DESC(
+						AZALIA_JACK,
+						AZALIA_EXTERNAL_PRIMARY_CHASSIS | AZALIA_FRONT,
+						AZALIA_HP_OUT,
+						AZALIA_STEREO_MONO_1_8,
+						AZALIA_BLACK,
+						AZALIA_JACK_PRESENCE_DETECT,
+						15,
+						0
+					)),
 
-	/* Pin Complex (NID 0x06) */
-	AZALIA_PIN_CFG(0, 0x06, 0x901700f0),
+	/* Pin Complex (NID 0x06) - Internal Speaker */
+	AZALIA_PIN_CFG(0, 0x06, AZALIA_PIN_DESC(
+						AZALIA_INTEGRATED,
+						AZALIA_INTERNAL,
+						AZALIA_SPEAKER,
+						AZALIA_OTHER_ANALOG,
+						AZALIA_COLOR_UNKNOWN,
+						AZALIA_JACK_PRESENCE_DETECT,
+						15,
+						0
+					)),
 
-	/* Pin Complex (NID 0x07) */
-	AZALIA_PIN_CFG(0, 0x07, 0x02a110f0),
+	/* Pin Complex (NID 0x07) - Microphone Jack */
+	AZALIA_PIN_CFG(0, 0x07, AZALIA_PIN_DESC(
+						AZALIA_JACK,
+						AZALIA_EXTERNAL_PRIMARY_CHASSIS | AZALIA_FRONT,
+						AZALIA_MIC_IN,
+						AZALIA_STEREO_MONO_1_8,
+						AZALIA_BLACK,
+						AZALIA_JACK_PRESENCE_DETECT,
+						15,
+						0
+					)),
 
-	/* Pin Complex (NID 0x08) */
-	AZALIA_PIN_CFG(0, 0x08, 0x77a70037),
+	/* Pin Complex (NID 0x08) - Unused (NC) */
+	AZALIA_PIN_CFG(0, 0x08, AZALIA_PIN_DESC(
+					AZALIA_NC,
+					AZALIA_MOBILE_LID_INSIDE,
+					AZALIA_MIC_IN,
+					AZALIA_OTHER_ANALOG,
+					AZALIA_COLOR_UNKNOWN,
+					AZALIA_JACK_PRESENCE_DETECT,
+					3,
+					7
+				)),
 
-	/* Pin Complex (NID 0x09) */
-	AZALIA_PIN_CFG(0, 0x09, 0xb7a6003e),
+	/* Pin Complex (NID 0x09) - Internal Digital Mic */
+	AZALIA_PIN_CFG(0, 0x09, AZALIA_PIN_DESC(
+					AZALIA_INTEGRATED,
+					AZALIA_MOBILE_LID_INSIDE,
+					AZALIA_MIC_IN,
+					AZALIA_OTHER_DIGITAL,
+					AZALIA_COLOR_UNKNOWN,
+					AZALIA_JACK_PRESENCE_DETECT,
+					3,
+					14
+				)),
 
-	/* Pin Complex (NID 0x0a) */
-	AZALIA_PIN_CFG(0, 0x0a, 0x434510f0),
+	/* Pin Complex (NID 0x0a) - SPDIF Out (NC) */
+	AZALIA_PIN_CFG(0, 0x0a, AZALIA_PIN_DESC(
+					AZALIA_NC,
+					AZALIA_EXTERNAL_PRIMARY_CHASSIS | AZALIA_LEFT,
+					AZALIA_SPDIF_OUT,
+					AZALIA_OPTICAL,
+					AZALIA_BLACK,
+					AZALIA_JACK_PRESENCE_DETECT,
+					15,
+					0
+				)),
 };
 
 const u32 pc_beep_verbs[] = {

From eb504eb49ab7af390f5ca903573ee318fdfc06a2 Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Tue, 25 Nov 2025 11:15:08 -0600
Subject: [PATCH 2625/3886] mb/samsung/lumpy: Fix HDA pin configuration issues

Fix several HDA pin configuration issues:

- NID 0x06 (Internal Speaker): Disable jack presence detection.

- NID 0x08 (Unused): Standardize to AZALIA_PIN_CFG_NC(0) which
  generates the canonical NC value 0x411111f0 instead of the
  non-standard 0x77a70037.

- NID 0x09 (Internal Digital Mic): Disable jack presence detection.

This resolves an issue under Linux where the speakers would keep
outputting audio when the headphones were plugged in.

Change-Id: If9f5781200e2d2dc6c90713caf999868f7b993a0
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90216
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
---
 src/mainboard/samsung/lumpy/hda_verb.c | 15 +++------------
 1 file changed, 3 insertions(+), 12 deletions(-)

diff --git a/src/mainboard/samsung/lumpy/hda_verb.c b/src/mainboard/samsung/lumpy/hda_verb.c
index 8c538d6853..aedd7b6ce2 100644
--- a/src/mainboard/samsung/lumpy/hda_verb.c
+++ b/src/mainboard/samsung/lumpy/hda_verb.c
@@ -38,7 +38,7 @@ const u32 cim_verb_data[] = {
 						AZALIA_SPEAKER,
 						AZALIA_OTHER_ANALOG,
 						AZALIA_COLOR_UNKNOWN,
-						AZALIA_JACK_PRESENCE_DETECT,
+						AZALIA_NO_JACK_PRESENCE_DETECT,
 						15,
 						0
 					)),
@@ -56,16 +56,7 @@ const u32 cim_verb_data[] = {
 					)),
 
 	/* Pin Complex (NID 0x08) - Unused (NC) */
-	AZALIA_PIN_CFG(0, 0x08, AZALIA_PIN_DESC(
-					AZALIA_NC,
-					AZALIA_MOBILE_LID_INSIDE,
-					AZALIA_MIC_IN,
-					AZALIA_OTHER_ANALOG,
-					AZALIA_COLOR_UNKNOWN,
-					AZALIA_JACK_PRESENCE_DETECT,
-					3,
-					7
-				)),
+	AZALIA_PIN_CFG_NC(0),
 
 	/* Pin Complex (NID 0x09) - Internal Digital Mic */
 	AZALIA_PIN_CFG(0, 0x09, AZALIA_PIN_DESC(
@@ -74,7 +65,7 @@ const u32 cim_verb_data[] = {
 					AZALIA_MIC_IN,
 					AZALIA_OTHER_DIGITAL,
 					AZALIA_COLOR_UNKNOWN,
-					AZALIA_JACK_PRESENCE_DETECT,
+					AZALIA_NO_JACK_PRESENCE_DETECT,
 					3,
 					14
 				)),

From 5078d32cccf82d31e81bd41de62c483128f440e9 Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Thu, 27 Nov 2025 11:14:08 -0600
Subject: [PATCH 2626/3886] mb/google/brya: Enable ACPI S3 sleep state support

Add missing HAVE_ACPI_RESUME Kconfig selection to enable S3
(suspend-to-RAM) sleep state support on Brya-based boards.

Without this option, the ACPI sleepstates.asl initializes SSFG to
0x09 (supporting only S0 and S4) instead of 0x0D (supporting S0, S3,
and S4). This prevents the _S3 ACPI object from being created in the
DSDT, causing the operating system to not recognize S3 as an
available sleep state.

With this change:
- SSFG is initialized to 0x0D
- _S3 ACPI object is created in DSDT
- Linux recognizes S3 as supported (dmesg shows "ACPI: PM: (supports
  S0 S3 S4 S5)")
- Both s2idle and deep sleep options become available

Tested on Yaviks (Nissa/PCH-N variant).

Change-Id: I07cfe9327b73d28ba7f7abc7755f3b870be5be00
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90252
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/google/brya/Kconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/src/mainboard/google/brya/Kconfig b/src/mainboard/google/brya/Kconfig
index 437632bfe6..e5f5dc991d 100644
--- a/src/mainboard/google/brya/Kconfig
+++ b/src/mainboard/google/brya/Kconfig
@@ -29,6 +29,7 @@ config BOARD_GOOGLE_BRYA_COMMON
 	select FW_CONFIG
 	select FW_CONFIG_SOURCE_CHROMEEC_CBI
 	select GOOGLE_SMBIOS_MAINBOARD_VERSION
+	select HAVE_ACPI_RESUME
 	select HAVE_ACPI_TABLES
 	select I2C_TPM
 	select INTEL_LPSS_UART_FOR_CONSOLE

From 02342b31dfd3aa9d81b7f71fc1dec990019f5b41 Mon Sep 17 00:00:00 2001
From: Maximilian Brune <maximilian.brune@9elements.com>
Date: Mon, 10 Nov 2025 16:46:23 +0100
Subject: [PATCH 2627/3886] soc/amd/*/memmap.c: Report FCH MMIO regions as
 reserved

The following error is observed in Linux:
[   30.255680] ACPI Error: Aborting method \_SB.FUR4.AOAC._OFF due to previous error (AE_AML_LOOP_TIMEOUT)
It caused a boot delay issue in the virtualization case above due to
some mmio regions not being passed through and the acpi interpreter
waiting.

reserve MMIO regions which are used by ACPI code in order to fix this
issue.

source: "Address Space Mapping" Table in relevant PPRs.

Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: Ia12a3dea0e24ae24fa1f7db7c7f2bd9f7dd6a591
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90212
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
---
 src/soc/amd/cezanne/memmap.c   | 5 +++++
 src/soc/amd/glinda/memmap.c    | 5 +++++
 src/soc/amd/mendocino/memmap.c | 5 +++++
 src/soc/amd/phoenix/memmap.c   | 5 +++++
 src/soc/amd/picasso/memmap.c   | 5 +++++
 5 files changed, 25 insertions(+)

diff --git a/src/soc/amd/cezanne/memmap.c b/src/soc/amd/cezanne/memmap.c
index feecdd7b13..a3f1c864a2 100644
--- a/src/soc/amd/cezanne/memmap.c
+++ b/src/soc/amd/cezanne/memmap.c
@@ -1,9 +1,11 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
+#include <amdblocks/acpimmio_map.h>
 #include <amdblocks/iomap.h>
 #include <amdblocks/memmap.h>
 #include <amdblocks/root_complex.h>
 #include <device/device.h>
+#include <soc/iomap.h>
 #include <stdint.h>
 
 /*
@@ -65,5 +67,8 @@ void read_soc_memmap_resources(struct device *dev, unsigned long *idx)
 	/* Reserve fixed IOMMU MMIO region */
 	mmio_range(dev, (*idx)++, IOMMU_RESERVED_MMIO_BASE, IOMMU_RESERVED_MMIO_SIZE);
 
+	mmio_range(dev, (*idx)++, AMD_SB_ACPI_MMIO_ADDR, 0x2000);
+	mmio_range(dev, (*idx)++, ALINK_AHB_ADDRESS, 0x20000);
+
 	read_fsp_resources(dev, idx);
 }
diff --git a/src/soc/amd/glinda/memmap.c b/src/soc/amd/glinda/memmap.c
index feecdd7b13..a3f1c864a2 100644
--- a/src/soc/amd/glinda/memmap.c
+++ b/src/soc/amd/glinda/memmap.c
@@ -1,9 +1,11 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
+#include <amdblocks/acpimmio_map.h>
 #include <amdblocks/iomap.h>
 #include <amdblocks/memmap.h>
 #include <amdblocks/root_complex.h>
 #include <device/device.h>
+#include <soc/iomap.h>
 #include <stdint.h>
 
 /*
@@ -65,5 +67,8 @@ void read_soc_memmap_resources(struct device *dev, unsigned long *idx)
 	/* Reserve fixed IOMMU MMIO region */
 	mmio_range(dev, (*idx)++, IOMMU_RESERVED_MMIO_BASE, IOMMU_RESERVED_MMIO_SIZE);
 
+	mmio_range(dev, (*idx)++, AMD_SB_ACPI_MMIO_ADDR, 0x2000);
+	mmio_range(dev, (*idx)++, ALINK_AHB_ADDRESS, 0x20000);
+
 	read_fsp_resources(dev, idx);
 }
diff --git a/src/soc/amd/mendocino/memmap.c b/src/soc/amd/mendocino/memmap.c
index feecdd7b13..a3f1c864a2 100644
--- a/src/soc/amd/mendocino/memmap.c
+++ b/src/soc/amd/mendocino/memmap.c
@@ -1,9 +1,11 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
+#include <amdblocks/acpimmio_map.h>
 #include <amdblocks/iomap.h>
 #include <amdblocks/memmap.h>
 #include <amdblocks/root_complex.h>
 #include <device/device.h>
+#include <soc/iomap.h>
 #include <stdint.h>
 
 /*
@@ -65,5 +67,8 @@ void read_soc_memmap_resources(struct device *dev, unsigned long *idx)
 	/* Reserve fixed IOMMU MMIO region */
 	mmio_range(dev, (*idx)++, IOMMU_RESERVED_MMIO_BASE, IOMMU_RESERVED_MMIO_SIZE);
 
+	mmio_range(dev, (*idx)++, AMD_SB_ACPI_MMIO_ADDR, 0x2000);
+	mmio_range(dev, (*idx)++, ALINK_AHB_ADDRESS, 0x20000);
+
 	read_fsp_resources(dev, idx);
 }
diff --git a/src/soc/amd/phoenix/memmap.c b/src/soc/amd/phoenix/memmap.c
index 1b45b9c93c..063c100bc9 100644
--- a/src/soc/amd/phoenix/memmap.c
+++ b/src/soc/amd/phoenix/memmap.c
@@ -1,10 +1,12 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
+#include <amdblocks/acpimmio_map.h>
 #include <amdblocks/iomap.h>
 #include <amdblocks/memmap.h>
 #include <amdblocks/root_complex.h>
 #include <device/device.h>
 #include <drivers/amd/opensil/opensil.h>
+#include <soc/iomap.h>
 #include <stdint.h>
 
 /*
@@ -66,6 +68,9 @@ void read_soc_memmap_resources(struct device *dev, unsigned long *idx)
 	/* Reserve fixed IOMMU MMIO region */
 	mmio_range(dev, (*idx)++, IOMMU_RESERVED_MMIO_BASE, IOMMU_RESERVED_MMIO_SIZE);
 
+	mmio_range(dev, (*idx)++, AMD_SB_ACPI_MMIO_ADDR, 0x2000);
+	mmio_range(dev, (*idx)++, ALINK_AHB_ADDRESS, 0x20000);
+
 	if (CONFIG(PLATFORM_USES_FSP2_0))
 		read_fsp_resources(dev, idx);
 	else
diff --git a/src/soc/amd/picasso/memmap.c b/src/soc/amd/picasso/memmap.c
index 2bbf28589a..bdbfb426e5 100644
--- a/src/soc/amd/picasso/memmap.c
+++ b/src/soc/amd/picasso/memmap.c
@@ -1,9 +1,11 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
+#include <amdblocks/acpimmio_map.h>
 #include <amdblocks/memmap.h>
 #include <amdblocks/iomap.h>
 #include <amdblocks/root_complex.h>
 #include <device/device.h>
+#include <soc/iomap.h>
 #include <stdint.h>
 
 /*
@@ -65,5 +67,8 @@ void read_soc_memmap_resources(struct device *dev, unsigned long *idx)
 	/* Reserve fixed IOMMU MMIO region */
 	mmio_range(dev, (*idx)++, IOMMU_RESERVED_MMIO_BASE, IOMMU_RESERVED_MMIO_SIZE);
 
+	mmio_range(dev, (*idx)++, AMD_SB_ACPI_MMIO_ADDR, 0x2000);
+	mmio_range(dev, (*idx)++, ALINK_AHB_ADDRESS, 0x20000);
+
 	read_fsp_resources(dev, idx);
 }

From c19585974876b5e8769c16e7ff67443faceb5227 Mon Sep 17 00:00:00 2001
From: Felix Held <felix-coreboot@felixheld.de>
Date: Fri, 11 Apr 2025 18:06:02 +0200
Subject: [PATCH 2628/3886] soc/amd: add ACPI code for I3C controller

Add the I3C controllers to the ACPI tables. Most of the ACPI code needed
for that is added to the DSDT, since everything, but the enable status
of the I3C MMIO devices is known at build-time. To handle the I3C
controller enable status, each ACPI device contains the STAT name with
the value of 0 in the DSDT and when the device is enabled this STAT name
will be overridden in the SSDT.

TEST=OS loads the I3C kernel modules on amd/birman_plus.

Change-Id: I309d54c81056486573c32d4da54de61b36b5c378
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87282
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
---
 src/soc/amd/common/block/i2c/i3c.c  |  36 ++++
 src/soc/amd/genoa_poc/acpi/mmio.asl | 181 +++++++++++++++++++
 src/soc/amd/glinda/acpi/mmio.asl    | 269 ++++++++++++++++++++++++++++
 src/soc/amd/mendocino/acpi/mmio.asl | 181 +++++++++++++++++++
 src/soc/amd/phoenix/acpi/mmio.asl   | 181 +++++++++++++++++++
 5 files changed, 848 insertions(+)

diff --git a/src/soc/amd/common/block/i2c/i3c.c b/src/soc/amd/common/block/i2c/i3c.c
index 9fb75d9e10..43eae71b67 100644
--- a/src/soc/amd/common/block/i2c/i3c.c
+++ b/src/soc/amd/common/block/i2c/i3c.c
@@ -1,6 +1,38 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
+#include <acpi/acpigen.h>
+#include <amdblocks/i2c.h>
+#include <console/console.h>
 #include <device/device.h>
+#include <types.h>
+
+#if CONFIG(HAVE_ACPI_TABLES)
+static const char *i3c_acpi_name(const struct device *dev)
+{
+	size_t i;
+	size_t num_ctrlrs;
+	const struct soc_i3c_ctrlr_info *ctrlr = soc_get_i3c_ctrlr_info(&num_ctrlrs);
+
+	if (!(uintptr_t)dev->path.mmio.addr) {
+		printk(BIOS_ERR, "NULL MMIO address at %s\n", __func__);
+		return NULL;
+	}
+
+	for (i = 0; i < num_ctrlrs; i++) {
+		if ((uintptr_t)dev->path.mmio.addr == ctrlr[i].bar)
+			return ctrlr[i].acpi_name;
+	}
+	printk(BIOS_ERR, "%s: Could not find %lu\n", __func__, (uintptr_t)dev->path.mmio.addr);
+	return NULL;
+}
+
+static void i3c_acpi_fill_ssdt(const struct device *dev)
+{
+	acpigen_write_scope(acpi_device_path(dev));
+	acpigen_write_store_int_to_namestr(acpi_device_status(dev), "STAT");
+	acpigen_pop_len(); /* Scope */
+}
+#endif
 
 static void i3c_read_resources(struct device *dev)
 {
@@ -10,4 +42,8 @@ static void i3c_read_resources(struct device *dev)
 struct device_operations soc_amd_i3c_mmio_ops = {
 	.read_resources = i3c_read_resources,
 	.set_resources = noop_set_resources,
+#if CONFIG(HAVE_ACPI_TABLES)
+	.acpi_name = i3c_acpi_name,
+	.acpi_fill_ssdt = i3c_acpi_fill_ssdt,
+#endif
 };
diff --git a/src/soc/amd/genoa_poc/acpi/mmio.asl b/src/soc/amd/genoa_poc/acpi/mmio.asl
index 9b5e1d2d2b..85bb12b021 100644
--- a/src/soc/amd/genoa_poc/acpi/mmio.asl
+++ b/src/soc/amd/genoa_poc/acpi/mmio.asl
@@ -392,6 +392,187 @@ Device (I2C5)
 	AOAC_DEVICE(FCH_AOAC_DEV_I2C5, 0)
 }
 
+Device (I3C0) {
+	Name (STAT, 0x0)
+
+	/* Only return I3C controller HID "AMDI0015" when device is enabled in devicetree */
+	Method (_HID, 0x0) {
+		If (STAT) {
+			Return ("AMDI0015")
+		} Else {
+			Return ("AMDI0016")
+		}
+	}
+	Name (_UID, 0x0)
+	Method (_CRS, 0) {
+		Local0 = ResourceTemplate() {
+			Interrupt (
+				ResourceConsumer,
+				Edge,
+				ActiveHigh,
+				Exclusive, , , IRQR)
+			{ 0 }
+			Memory32Fixed (ReadWrite, APU_I3C0_BASE, 0x1000)
+		}
+		CreateDWordField (Local0, IRQR._INT, IRQN)
+		If (PICM) {
+			IRQN = II20
+		} Else {
+			IRQN = PI20
+		}
+		If (IRQN == 0x1f) {
+			Return (ResourceTemplate() {
+				Memory32Fixed (ReadWrite, APU_I3C0_BASE, 0x1000)
+			})
+		} Else {
+			Return (Local0)
+		}
+	}
+
+	Method (_STA, 0x0, NotSerialized)
+	{
+		Return (STAT)
+	}
+
+	AOAC_DEVICE(FCH_AOAC_DEV_I3C0, 0)
+}
+
+Device (I3C1) {
+	Name (STAT, 0x0)
+
+	/* Only return I3C controller HID "AMDI0015" when device is enabled in devicetree */
+	Method (_HID, 0x0) {
+		If (STAT) {
+			Return ("AMDI0015")
+		} Else {
+			Return ("AMDI0016")
+		}
+	}
+	Name (_UID, 0x1)
+	Method (_CRS, 0) {
+		Local0 = ResourceTemplate() {
+			Interrupt (
+				ResourceConsumer,
+				Edge,
+				ActiveHigh,
+				Exclusive, , , IRQR)
+			{ 0 }
+			Memory32Fixed (ReadWrite, APU_I3C1_BASE, 0x1000)
+		}
+		CreateDWordField (Local0, IRQR._INT, IRQN)
+		If (PICM) {
+			IRQN = II21
+		} Else {
+			IRQN = PI21
+		}
+		If (IRQN == 0x1f) {
+			Return (ResourceTemplate() {
+				Memory32Fixed (ReadWrite, APU_I3C1_BASE, 0x1000)
+			})
+		} Else {
+			Return (Local0)
+		}
+	}
+
+	Method (_STA, 0x0, NotSerialized)
+	{
+		Return (STAT)
+	}
+
+	AOAC_DEVICE(FCH_AOAC_DEV_I3C1, 0)
+}
+
+Device (I3C2) {
+	Name (STAT, 0x0)
+
+	/* Only return I3C controller HID "AMDI0015" when device is enabled in devicetree */
+	Method (_HID, 0x0) {
+		If (STAT) {
+			Return ("AMDI0015")
+		} Else {
+			Return ("AMDI0016")
+		}
+	}
+	Name (_UID, 0x2)
+	Method (_CRS, 0) {
+		Local0 = ResourceTemplate() {
+			Interrupt (
+				ResourceConsumer,
+				Edge,
+				ActiveHigh,
+				Exclusive, , , IRQR)
+			{ 0 }
+			Memory32Fixed (ReadWrite, APU_I3C2_BASE, 0x1000)
+		}
+		CreateDWordField (Local0, IRQR._INT, IRQN)
+		If (PICM) {
+			IRQN = II22
+		} Else {
+			IRQN = PI22
+		}
+		If (IRQN == 0x1f) {
+			Return (ResourceTemplate() {
+				Memory32Fixed (ReadWrite, APU_I3C2_BASE, 0x1000)
+			})
+		} Else {
+			Return (Local0)
+		}
+	}
+
+	Method (_STA, 0x0, NotSerialized)
+	{
+		Return (STAT)
+	}
+
+	AOAC_DEVICE(FCH_AOAC_DEV_I3C2, 0)
+}
+
+Device (I3C3)
+{
+	Name (STAT, 0x0)
+
+	/* Only return I3C controller HID "AMDI0015" when device is enabled in devicetree */
+	Method (_HID, 0x0) {
+		If (STAT) {
+			Return ("AMDI0015")
+		} Else {
+			Return ("AMDI0016")
+		}
+	}
+	Name (_UID, 0x3)
+	Method (_CRS, 0) {
+		Local0 = ResourceTemplate() {
+			Interrupt (
+				ResourceConsumer,
+				Edge,
+				ActiveHigh,
+				Exclusive, , , IRQR)
+			{ 0 }
+			Memory32Fixed (ReadWrite, APU_I3C3_BASE, 0x1000)
+		}
+		CreateDWordField (Local0, IRQR._INT, IRQN)
+		If (PICM) {
+			IRQN = II23
+		} Else {
+			IRQN = PI23
+		}
+		If (IRQN == 0x1f) {
+			Return (ResourceTemplate() {
+				Memory32Fixed (ReadWrite, APU_I3C3_BASE, 0x1000)
+			})
+		} Else {
+			Return (Local0)
+		}
+	}
+
+	Method (_STA, 0x0, NotSerialized)
+	{
+		Return (STAT)
+	}
+
+	AOAC_DEVICE(FCH_AOAC_DEV_I3C3, 0)
+}
+
 Device (MISC)
 {
 	Name (_HID, "AMD0040")
diff --git a/src/soc/amd/glinda/acpi/mmio.asl b/src/soc/amd/glinda/acpi/mmio.asl
index 7323427b08..75b99703ec 100644
--- a/src/soc/amd/glinda/acpi/mmio.asl
+++ b/src/soc/amd/glinda/acpi/mmio.asl
@@ -3,6 +3,7 @@
 /* TODO: Update for Glinda */
 
 #include <soc/amd/common/acpi/aoac.asl>
+#include <soc/amd_pci_int_defs.h>
 #include <soc/aoac_defs.h>
 #include <soc/gpio.h>
 #include <soc/iomap.h>
@@ -405,6 +406,274 @@ Device (I2C3)
 #endif
 }
 
+Device (I3C0) {
+	Name (STAT, 0x0)
+
+	/* Only return I3C controller HID "AMDI5017" when device is enabled in devicetree */
+	Method (_HID, 0x0) {
+		If (STAT) {
+			Return ("AMDI5017")
+		} Else {
+			Return ("AMDI0016")
+		}
+	}
+	Name (_CID, "MIPI0100")
+	Name (_UID, 0x0)
+	Method (_CRS, 0) {
+		Local0 = ResourceTemplate() {
+			Interrupt (
+				ResourceConsumer,
+				Edge,
+				ActiveHigh,
+				Exclusive, , , IRQR)
+			{ 0 }
+			Memory32Fixed (ReadWrite, APU_I3C0_BASE, 0x1000)
+		}
+		CreateDWordField (Local0, IRQR._INT, IRQN)
+		If (PICM) {
+			IRQN = II20
+		} Else {
+			IRQN = PI20
+		}
+		If (IRQN == PIRQ_NC) {
+			Return (ResourceTemplate() {
+				Memory32Fixed (ReadWrite, APU_I3C0_BASE, 0x1000)
+			})
+		} Else {
+			Return (Local0)
+		}
+	}
+	Method(_DSD, 0, Serialized){
+		Return(Package() {
+			ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+			Package () {
+				"mipi-i3c-sw-interface-revision", 0x10000, // 1.0
+			},
+			ToUUID("dbb8e3e6-5886-4ba6-8795-1319f52a966b"), // Hierarchical Extension
+			Package () {
+				"mipi-i3c-ctrlr-0-subproperties", CTR0,
+			}
+		})
+	}
+
+	Method(CTR0, 0, Serialized){
+		Return(Package() {
+			ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+			Package () {
+			"mipi-i3c-sw-interface-revision", 0x10000, // 1.0
+			}
+		})
+	}
+	Method (_STA, 0x0, NotSerialized)
+	{
+		Return (STAT)
+	}
+
+	AOAC_DEVICE(FCH_AOAC_DEV_I3C0, 0)
+}
+
+Device (I3C1) {
+	Name (STAT, 0x0)
+
+	/* Only return I3C controller HID "AMDI5017" when device is enabled in devicetree */
+	Method (_HID, 0x0) {
+		If (STAT) {
+			Return ("AMDI5017")
+		} Else {
+			Return ("AMDI0016")
+		}
+	}
+	Name (_CID, "MIPI0100")
+	Name (_UID, 0x1)
+	Method (_CRS, 0) {
+		Local0 = ResourceTemplate() {
+			Interrupt (
+				ResourceConsumer,
+				Edge,
+				ActiveHigh,
+				Exclusive, , , IRQR)
+			{ 0 }
+			Memory32Fixed (ReadWrite, APU_I3C1_BASE, 0x1000)
+		}
+		CreateDWordField (Local0, IRQR._INT, IRQN)
+		If (PICM) {
+			IRQN = II21
+		} Else {
+			IRQN = PI21
+		}
+		If (IRQN == PIRQ_NC) {
+			Return (ResourceTemplate() {
+				Memory32Fixed (ReadWrite, APU_I3C1_BASE, 0x1000)
+			})
+		} Else {
+			Return (Local0)
+		}
+	}
+	Method(_DSD, 0, Serialized){
+		Return(Package() {
+			ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+			Package () {
+				"mipi-i3c-sw-interface-revision", 0x10000, // 1.0
+			},
+			ToUUID("dbb8e3e6-5886-4ba6-8795-1319f52a966b"), // Hierarchical Extension
+			Package () {
+				"mipi-i3c-ctrlr-0-subproperties", CTR0,
+			}
+		})
+	}
+
+	Method(CTR0, 0, Serialized){
+		Return(Package() {
+			ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+			Package () {
+			"mipi-i3c-sw-interface-revision", 0x10000, // 1.0
+			}
+		})
+	}
+	Method (_STA, 0x0, NotSerialized)
+	{
+		Return (STAT)
+	}
+
+	AOAC_DEVICE(FCH_AOAC_DEV_I3C1, 0)
+}
+
+Device (I3C2) {
+	Name (STAT, 0x0)
+
+	/* Only return I3C controller HID "AMDI5017" when device is enabled in devicetree */
+	Method (_HID, 0x0) {
+		If (STAT) {
+			Return ("AMDI5017")
+		} Else {
+			Return ("AMDI0016")
+		}
+	}
+	Name (_CID, "MIPI0100")
+	Name (_UID, 0x2)
+	Method (_CRS, 0) {
+		Local0 = ResourceTemplate() {
+			Interrupt (
+				ResourceConsumer,
+				Edge,
+				ActiveHigh,
+				Exclusive, , , IRQR)
+			{ 0 }
+			Memory32Fixed (ReadWrite, APU_I3C2_BASE, 0x1000)
+		}
+		CreateDWordField (Local0, IRQR._INT, IRQN)
+		If (PICM) {
+			IRQN = II22
+		} Else {
+			IRQN = PI22
+		}
+		If (IRQN == PIRQ_NC) {
+			Return (ResourceTemplate() {
+				Memory32Fixed (ReadWrite, APU_I3C2_BASE, 0x1000)
+			})
+		} Else {
+			Return (Local0)
+		}
+	}
+
+	Method(_DSD, 0, Serialized){
+		Return(Package() {
+			ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+			Package () {
+				"mipi-i3c-sw-interface-revision", 0x10000, // 1.0
+			},
+			ToUUID("dbb8e3e6-5886-4ba6-8795-1319f52a966b"), // Hierarchical Extension
+			Package () {
+				"mipi-i3c-ctrlr-0-subproperties", CTR0,
+			}
+		})
+	}
+
+	Method(CTR0, 0, Serialized){
+		Return(Package() {
+			ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+			Package () {
+			"mipi-i3c-sw-interface-revision", 0x10000, // 1.0
+			}
+		})
+	}
+	Method (_STA, 0x0, NotSerialized)
+	{
+		Return (STAT)
+	}
+
+	AOAC_DEVICE(FCH_AOAC_DEV_I3C2, 0)
+}
+
+Device (I3C3)
+{
+	Name (STAT, 0x0)
+
+	/* Only return I3C controller HID "AMDI5017" when device is enabled in devicetree */
+	Method (_HID, 0x0) {
+		If (STAT) {
+			Return ("AMDI5017")
+		} Else {
+			Return ("AMDI0016")
+		}
+	}
+	Name (_CID, "MIPI0100")
+	Name (_UID, 0x3)
+	Method (_CRS, 0) {
+		Local0 = ResourceTemplate() {
+			Interrupt (
+				ResourceConsumer,
+				Edge,
+				ActiveHigh,
+				Exclusive, , , IRQR)
+			{ 0 }
+			Memory32Fixed (ReadWrite, APU_I3C3_BASE, 0x1000)
+		}
+		CreateDWordField (Local0, IRQR._INT, IRQN)
+		If (PICM) {
+			IRQN = II23
+		} Else {
+			IRQN = PI23
+		}
+		If (IRQN == PIRQ_NC) {
+			Return (ResourceTemplate() {
+				Memory32Fixed (ReadWrite, APU_I3C3_BASE, 0x1000)
+			})
+		} Else {
+			Return (Local0)
+		}
+	}
+
+	Method (_STA, 0x0, NotSerialized)
+	{
+		Return (STAT)
+	}
+
+	Method(_DSD, 0, Serialized){
+		Return(Package() {
+			ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+			Package () {
+				"mipi-i3c-sw-interface-revision", 0x10000, // 1.0
+			},
+			ToUUID("dbb8e3e6-5886-4ba6-8795-1319f52a966b"), // Hierarchical Extension
+			Package () {
+				"mipi-i3c-ctrlr-0-subproperties", CTR0,
+			}
+		})
+	}
+
+	Method(CTR0, 0, Serialized){
+		Return(Package() {
+			ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+			Package () {
+			"mipi-i3c-sw-interface-revision", 0x10000, // 1.0
+			}
+		})
+	}
+
+	AOAC_DEVICE(FCH_AOAC_DEV_I3C3, 0)
+}
+
 Device (MISC)
 {
 	Name (_HID, "AMD0040")
diff --git a/src/soc/amd/mendocino/acpi/mmio.asl b/src/soc/amd/mendocino/acpi/mmio.asl
index d4459d66db..21237a781a 100644
--- a/src/soc/amd/mendocino/acpi/mmio.asl
+++ b/src/soc/amd/mendocino/acpi/mmio.asl
@@ -402,6 +402,187 @@ Device (I2C3)
 #endif
 }
 
+Device (I3C0) {
+	Name (STAT, 0x0)
+
+	/* Only return I3C controller HID "AMDI0015" when device is enabled in devicetree */
+	Method (_HID, 0x0) {
+		If (STAT) {
+			Return ("AMDI0015")
+		} Else {
+			Return ("AMDI0016")
+		}
+	}
+	Name (_UID, 0x0)
+	Method (_CRS, 0) {
+		Local0 = ResourceTemplate() {
+			Interrupt (
+				ResourceConsumer,
+				Edge,
+				ActiveHigh,
+				Exclusive, , , IRQR)
+			{ 0 }
+			Memory32Fixed (ReadWrite, APU_I3C0_BASE, 0x1000)
+		}
+		CreateDWordField (Local0, IRQR._INT, IRQN)
+		If (PICM) {
+			IRQN = II20
+		} Else {
+			IRQN = PI20
+		}
+		If (IRQN == 0x1f) {
+			Return (ResourceTemplate() {
+				Memory32Fixed (ReadWrite, APU_I3C0_BASE, 0x1000)
+			})
+		} Else {
+			Return (Local0)
+		}
+	}
+
+	Method (_STA, 0x0, NotSerialized)
+	{
+		Return (STAT)
+	}
+
+	AOAC_DEVICE(FCH_AOAC_DEV_I3C0, 0)
+}
+
+Device (I3C1) {
+	Name (STAT, 0x0)
+
+	/* Only return I3C controller HID "AMDI0015" when device is enabled in devicetree */
+	Method (_HID, 0x0) {
+		If (STAT) {
+			Return ("AMDI0015")
+		} Else {
+			Return ("AMDI0016")
+		}
+	}
+	Name (_UID, 0x1)
+	Method (_CRS, 0) {
+		Local0 = ResourceTemplate() {
+			Interrupt (
+				ResourceConsumer,
+				Edge,
+				ActiveHigh,
+				Exclusive, , , IRQR)
+			{ 0 }
+			Memory32Fixed (ReadWrite, APU_I3C1_BASE, 0x1000)
+		}
+		CreateDWordField (Local0, IRQR._INT, IRQN)
+		If (PICM) {
+			IRQN = II21
+		} Else {
+			IRQN = PI21
+		}
+		If (IRQN == 0x1f) {
+			Return (ResourceTemplate() {
+				Memory32Fixed (ReadWrite, APU_I3C1_BASE, 0x1000)
+			})
+		} Else {
+			Return (Local0)
+		}
+	}
+
+	Method (_STA, 0x0, NotSerialized)
+	{
+		Return (STAT)
+	}
+
+	AOAC_DEVICE(FCH_AOAC_DEV_I3C1, 0)
+}
+
+Device (I3C2) {
+	Name (STAT, 0x0)
+
+	/* Only return I3C controller HID "AMDI0015" when device is enabled in devicetree */
+	Method (_HID, 0x0) {
+		If (STAT) {
+			Return ("AMDI0015")
+		} Else {
+			Return ("AMDI0016")
+		}
+	}
+	Name (_UID, 0x2)
+	Method (_CRS, 0) {
+		Local0 = ResourceTemplate() {
+			Interrupt (
+				ResourceConsumer,
+				Edge,
+				ActiveHigh,
+				Exclusive, , , IRQR)
+			{ 0 }
+			Memory32Fixed (ReadWrite, APU_I3C2_BASE, 0x1000)
+		}
+		CreateDWordField (Local0, IRQR._INT, IRQN)
+		If (PICM) {
+			IRQN = II22
+		} Else {
+			IRQN = PI22
+		}
+		If (IRQN == 0x1f) {
+			Return (ResourceTemplate() {
+				Memory32Fixed (ReadWrite, APU_I3C2_BASE, 0x1000)
+			})
+		} Else {
+			Return (Local0)
+		}
+	}
+
+	Method (_STA, 0x0, NotSerialized)
+	{
+		Return (STAT)
+	}
+
+	AOAC_DEVICE(FCH_AOAC_DEV_I3C2, 0)
+}
+
+Device (I3C3)
+{
+	Name (STAT, 0x0)
+
+	/* Only return I3C controller HID "AMDI0015" when device is enabled in devicetree */
+	Method (_HID, 0x0) {
+		If (STAT) {
+			Return ("AMDI0015")
+		} Else {
+			Return ("AMDI0016")
+		}
+	}
+	Name (_UID, 0x3)
+	Method (_CRS, 0) {
+		Local0 = ResourceTemplate() {
+			Interrupt (
+				ResourceConsumer,
+				Edge,
+				ActiveHigh,
+				Exclusive, , , IRQR)
+			{ 0 }
+			Memory32Fixed (ReadWrite, APU_I3C3_BASE, 0x1000)
+		}
+		CreateDWordField (Local0, IRQR._INT, IRQN)
+		If (PICM) {
+			IRQN = II23
+		} Else {
+			IRQN = PI23
+		}
+		If (IRQN == 0x1f) {
+			Return (ResourceTemplate() {
+				Memory32Fixed (ReadWrite, APU_I3C3_BASE, 0x1000)
+			})
+		} Else {
+			Return (Local0)
+		}
+	}
+
+	Method (_STA, 0x0, NotSerialized)
+	{
+		Return (STAT)
+	}
+
+	AOAC_DEVICE(FCH_AOAC_DEV_I3C3, 0)
+}
+
 Device (MISC)
 {
 	Name (_HID, "AMD0040")
diff --git a/src/soc/amd/phoenix/acpi/mmio.asl b/src/soc/amd/phoenix/acpi/mmio.asl
index b0253b5ec9..e393574332 100644
--- a/src/soc/amd/phoenix/acpi/mmio.asl
+++ b/src/soc/amd/phoenix/acpi/mmio.asl
@@ -402,6 +402,187 @@ Device (I2C3)
 #endif
 }
 
+Device (I3C0) {
+	Name (STAT, 0x0)
+
+	/* Only return I3C controller HID "AMDI0015" when device is enabled in devicetree */
+	Method (_HID, 0x0) {
+		If (STAT) {
+			Return ("AMDI0015")
+		} Else {
+			Return ("AMDI0016")
+		}
+	}
+	Name (_UID, 0x0)
+	Method (_CRS, 0) {
+		Local0 = ResourceTemplate() {
+			Interrupt (
+				ResourceConsumer,
+				Edge,
+				ActiveHigh,
+				Exclusive, , , IRQR)
+			{ 0 }
+			Memory32Fixed (ReadWrite, APU_I3C0_BASE, 0x1000)
+		}
+		CreateDWordField (Local0, IRQR._INT, IRQN)
+		If (PICM) {
+			IRQN = II20
+		} Else {
+			IRQN = PI20
+		}
+		If (IRQN == 0x1f) {
+			Return (ResourceTemplate() {
+				Memory32Fixed (ReadWrite, APU_I3C0_BASE, 0x1000)
+			})
+		} Else {
+			Return (Local0)
+		}
+	}
+
+	Method (_STA, 0x0, NotSerialized)
+	{
+		Return (STAT)
+	}
+
+	AOAC_DEVICE(FCH_AOAC_DEV_I3C0, 0)
+}
+
+Device (I3C1) {
+	Name (STAT, 0x0)
+
+	/* Only return I3C controller HID "AMDI0015" when device is enabled in devicetree */
+	Method (_HID, 0x0) {
+		If (STAT) {
+			Return ("AMDI0015")
+		} Else {
+			Return ("AMDI0016")
+		}
+	}
+	Name (_UID, 0x1)
+	Method (_CRS, 0) {
+		Local0 = ResourceTemplate() {
+			Interrupt (
+				ResourceConsumer,
+				Edge,
+				ActiveHigh,
+				Exclusive, , , IRQR)
+			{ 0 }
+			Memory32Fixed (ReadWrite, APU_I3C1_BASE, 0x1000)
+		}
+		CreateDWordField (Local0, IRQR._INT, IRQN)
+		If (PICM) {
+			IRQN = II21
+		} Else {
+			IRQN = PI21
+		}
+		If (IRQN == 0x1f) {
+			Return (ResourceTemplate() {
+				Memory32Fixed (ReadWrite, APU_I3C1_BASE, 0x1000)
+			})
+		} Else {
+			Return (Local0)
+		}
+	}
+
+	Method (_STA, 0x0, NotSerialized)
+	{
+		Return (STAT)
+	}
+
+	AOAC_DEVICE(FCH_AOAC_DEV_I3C1, 0)
+}
+
+Device (I3C2) {
+	Name (STAT, 0x0)
+
+	/* Only return I3C controller HID "AMDI0015" when device is enabled in devicetree */
+	Method (_HID, 0x0) {
+		If (STAT) {
+			Return ("AMDI0015")
+		} Else {
+			Return ("AMDI0016")
+		}
+	}
+	Name (_UID, 0x2)
+	Method (_CRS, 0) {
+		Local0 = ResourceTemplate() {
+			Interrupt (
+				ResourceConsumer,
+				Edge,
+				ActiveHigh,
+				Exclusive, , , IRQR)
+			{ 0 }
+			Memory32Fixed (ReadWrite, APU_I3C2_BASE, 0x1000)
+		}
+		CreateDWordField (Local0, IRQR._INT, IRQN)
+		If (PICM) {
+			IRQN = II22
+		} Else {
+			IRQN = PI22
+		}
+		If (IRQN == 0x1f) {
+			Return (ResourceTemplate() {
+				Memory32Fixed (ReadWrite, APU_I3C2_BASE, 0x1000)
+			})
+		} Else {
+			Return (Local0)
+		}
+	}
+
+	Method (_STA, 0x0, NotSerialized)
+	{
+		Return (STAT)
+	}
+
+	AOAC_DEVICE(FCH_AOAC_DEV_I3C2, 0)
+}
+
+Device (I3C3)
+{
+	Name (STAT, 0x0)
+
+	/* Only return I3C controller HID "AMDI0015" when device is enabled in devicetree */
+	Method (_HID, 0x0) {
+		If (STAT) {
+			Return ("AMDI0015")
+		} Else {
+			Return ("AMDI0016")
+		}
+	}
+	Name (_UID, 0x3)
+	Method (_CRS, 0) {
+		Local0 = ResourceTemplate() {
+			Interrupt (
+				ResourceConsumer,
+				Edge,
+				ActiveHigh,
+				Exclusive, , , IRQR)
+			{ 0 }
+			Memory32Fixed (ReadWrite, APU_I3C3_BASE, 0x1000)
+		}
+		CreateDWordField (Local0, IRQR._INT, IRQN)
+		If (PICM) {
+			IRQN = II23
+		} Else {
+			IRQN = PI23
+		}
+		If (IRQN == 0x1f) {
+			Return (ResourceTemplate() {
+				Memory32Fixed (ReadWrite, APU_I3C3_BASE, 0x1000)
+			})
+		} Else {
+			Return (Local0)
+		}
+	}
+
+	Method (_STA, 0x0, NotSerialized)
+	{
+		Return (STAT)
+	}
+
+	AOAC_DEVICE(FCH_AOAC_DEV_I3C3, 0)
+}
+
 Device (MISC)
 {
 	Name (_HID, "AMD0040")

From 1cfe413f954bfe34c7b7b399e0a2a950cd1a377c Mon Sep 17 00:00:00 2001
From: Erik van den Bogaert <ebogaert@eltan.com>
Date: Thu, 27 Nov 2025 11:26:15 +0100
Subject: [PATCH 2629/3886] soc/intel/common/block/lpc: Support RM590E eSPI
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

RM590E eSPI should be correctly configured by LPC driver

TEST=Debug log shows initialization messages (eg IOAPIC)at PCI:
00:00:1f.0

Change-Id: I1ee9861c5d8a5e6eeb3ebe6041a9f141d051995a
Signed-off-by: Erik van den Bogaert <ebogaert@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90247
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
---
 src/soc/intel/common/block/lpc/lpc.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/src/soc/intel/common/block/lpc/lpc.c b/src/soc/intel/common/block/lpc/lpc.c
index 118adea1f0..391a0182f2 100644
--- a/src/soc/intel/common/block/lpc/lpc.c
+++ b/src/soc/intel/common/block/lpc/lpc.c
@@ -483,6 +483,7 @@ static const unsigned short pci_device_ids[] = {
 	PCI_DID_INTEL_TGP_H_ESPI_HM570,
 	PCI_DID_INTEL_TGP_H_ESPI_QM580,
 	PCI_DID_INTEL_TGP_H_ESPI_WM590,
+	PCI_DID_INTEL_TGP_H_ESPI_RM590E,
 	PCI_DID_INTEL_MCC_ESPI_0,
 	PCI_DID_INTEL_MCC_ESPI_1,
 	PCI_DID_INTEL_MCC_BASE_ESPI,

From d3d4571411b7a9bace4e0a80ec84b73089abac28 Mon Sep 17 00:00:00 2001
From: Erik van den Bogaert <ebogaert@eltan.com>
Date: Thu, 27 Nov 2025 11:44:53 +0100
Subject: [PATCH 2630/3886] soc/intel/common/block/graphics: Use Xeon
 W-11865MRE IGD PCI ID
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Add IGD PCI ID of Xeon W-11865MRE to graphics driver so coreboot can use
GOP-provided framebuffer.

TEST=Debug log shows framebuffer info at PCI: 00:00:02.0 init

Change-Id: Ifd76707d2ad61e11028cd0e19cf06857c597d514
Signed-off-by: Erik van den Bogaert <ebogaert@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90248
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
---
 src/soc/intel/common/block/graphics/graphics.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/src/soc/intel/common/block/graphics/graphics.c b/src/soc/intel/common/block/graphics/graphics.c
index 251483d18d..12f29b567b 100644
--- a/src/soc/intel/common/block/graphics/graphics.c
+++ b/src/soc/intel/common/block/graphics/graphics.c
@@ -435,6 +435,7 @@ static const unsigned short pci_device_ids[] = {
 	PCI_DID_INTEL_CML_GT2_H_R1,
 	PCI_DID_INTEL_TGL_GT0,
 	PCI_DID_INTEL_TGL_GT1_H_32,
+	PCI_DID_INTEL_TGL_GT1_H_32_1,
 	PCI_DID_INTEL_TGL_GT1_H_16,
 	PCI_DID_INTEL_TGL_GT2_ULT,
 	PCI_DID_INTEL_TGL_GT2_ULX,

From 9b0af4860442782d5ebe4cb4e32828d09c0923d2 Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Mon, 13 Oct 2025 16:15:27 +0100
Subject: [PATCH 2631/3886] mb/starlabs/starbook/mtl: Update GPIO config

The GPIO config in the tree does not allow for S3 resume to work, as
the eSPI Virtual Wires stop reponding when the system enters S3.

Through setting the GpioOverride UPD to 0, the configuration in this
patch was discovered. This configuration keeps the virtual wires
working, and in turn, S3 resume works.

Change-Id: I5f73f74970d70f7736aa019a8e37e898921ae740
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90281
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
---
 .../starlabs/starbook/variants/mtl/gpio.c     | 32 +++++++++----------
 1 file changed, 16 insertions(+), 16 deletions(-)

diff --git a/src/mainboard/starlabs/starbook/variants/mtl/gpio.c b/src/mainboard/starlabs/starbook/variants/mtl/gpio.c
index 9f920dfcd5..944c1452f8 100644
--- a/src/mainboard/starlabs/starbook/variants/mtl/gpio.c
+++ b/src/mainboard/starlabs/starbook/variants/mtl/gpio.c
@@ -22,21 +22,21 @@ const struct pad_config *variant_early_gpio_table(size_t *num)
 /* Pad configuration in ramstage. */
 const struct pad_config gpio_table[] = {
 	/* General Purpose I/O Deep */
-	PAD_CFG_NF(GPP_V00, NONE, DEEP, NF1),				/* Battery Low */
-	PAD_CFG_NF(GPP_V01, NONE, DEEP, NF1),				/* Charger Connected */
-	PAD_CFG_NF(GPP_V03, UP_20K, DEEP, NF1),				/* Power Button */
+	PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_V00, NONE, DEEP, NF1),		/* Battery Low */
+	PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_V01, NONE, DEEP, NF1),		/* Charger Connected */
+	PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_V03, UP_20K, DEEP, NF1),	/* Power Button */
 	PAD_CFG_NF(GPP_V04, NONE, DEEP, NF1),				/* Sleep S3 */
 	PAD_CFG_NF(GPP_V05, NONE, DEEP, NF1),				/* Sleep S4 */
 	PAD_CFG_NF(GPP_V08, NONE, DEEP, NF1),				/* Bluetooth Suspend */
 
-	/* eSPI - Configure automatically on reset */
-	// PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_A00, UP_20K, DEEP, NF1),	/* eSPI IO 0 */
-	// PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_A01, UP_20K, DEEP, NF1),	/* eSPI IO 1 */
-	// PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_A02, UP_20K, DEEP, NF1),	/* eSPI IO 2 */
-	// PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_A03, UP_20K, DEEP, NF1),	/* eSPI IO 3 */
-	// PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_A04, UP_20K, DEEP, NF1),	/* eSPI CS 0 */
-	// PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_A05, UP_20K, DEEP, NF1),	/* eSPI Clk */
-	// PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_A06, NONE, DEEP, NF1),	/* eSPI Reset */
+	/* eSPI */
+	PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_A00, UP_20K, DEEP, NF1),	/* eSPI IO 0 */
+	PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_A01, UP_20K, DEEP, NF1),	/* eSPI IO 1 */
+	PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_A02, UP_20K, DEEP, NF1),	/* eSPI IO 2 */
+	PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_A03, UP_20K, DEEP, NF1),	/* eSPI IO 3 */
+	PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_A04, UP_20K, DEEP, NF1),	/* eSPI CS 0 */
+	PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_A05, UP_20K, DEEP, NF1),	/* eSPI Clk */
+	PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_A06, NONE, DEEP, NF1),		/* eSPI Reset */
 
 	/* Touchpad */
 	PAD_CFG_NF(GPP_H19, NONE, DEEP, NF1),				/* Data */
@@ -44,12 +44,12 @@ const struct pad_config gpio_table[] = {
 	PAD_CFG_GPI_APIC(GPP_B00, NONE, DEEP, LEVEL, INVERT),		/* Interrupt */
 
 	/* SSD */
-	PAD_CFG_NF(GPP_D20, NONE, DEEP, NF1),				/* Clock Request 8 */
+	PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_D20, NONE, PLTRST, NF1),	/* Clock Request 8 */
 	PAD_CFG_GPO(GPP_A20, 1, PLTRST),				/* Reset */
 	PAD_CFG_GPO(GPP_H07, 1, DEEP),					/* Enable */
 
 	/* Wireless */
-	PAD_CFG_NF(GPP_D21, NONE, DEEP, NF2),				/* Clock Request 5 */
+	PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_D21, NONE, PLTRST, NF2),	/* Clock Request 5 */
 	PAD_CFG_GPO(GPP_H02, 1, PLTRST),				/* Reset */
 	PAD_CFG_GPO(GPP_B19, 1, DEEP),					/* WiFi RF Kill */
 	PAD_CFG_GPO(GPP_B18, 1, DEEP),					/* Bluetooth RF Kill */
@@ -59,9 +59,9 @@ const struct pad_config gpio_table[] = {
 	PAD_CFG_NF(GPP_B16, NONE, DEEP, NF2),				/* HDMI Hot Plug */
 	PAD_CFG_NF(GPP_H16, NONE, DEEP, NF1),				/* HDMI Clock */
 	PAD_CFG_NF(GPP_H17, NONE, DEEP, NF1),				/* HDMI Data */
-	PAD_CFG_NF(GPP_A21, NONE, DEEP, NF1),				/* PMC Interrupt */
-	PAD_CFG_NF(GPP_C06, NONE, DEEP, NF1),				/* SML Clock */
-	PAD_CFG_NF(GPP_C07, NONE, DEEP, NF1),				/* SML Data */
+	PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_A21, NONE, DEEP, NF1),		/* PMC Interrupt */
+	PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_C06, NONE, DEEP, NF1),		/* SML Clock */
+	PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_C07, NONE, DEEP, NF1),		/* SML Data */
 
 	/* High-Definition Audio */
 	PAD_CFG_NF(GPP_D10, NATIVE, DEEP, NF1),				/* Clock */

From 3459502e0c5dae6e41881e4c55585c6f1f7d257f Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Sat, 29 Nov 2025 14:48:02 -0600
Subject: [PATCH 2632/3886] mb/starlabs/starfighter: Enable pmc_shared_sram
 device

Eliminates errors in cbmem

Change-Id: I1e9b02a0391b952eb461f174b3dc73783eed2853
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90282
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/starlabs/starfighter/variants/mtl/devicetree.cb | 1 +
 1 file changed, 1 insertion(+)

diff --git a/src/mainboard/starlabs/starfighter/variants/mtl/devicetree.cb b/src/mainboard/starlabs/starfighter/variants/mtl/devicetree.cb
index ff211fd173..f83df3e27a 100644
--- a/src/mainboard/starlabs/starfighter/variants/mtl/devicetree.cb
+++ b/src/mainboard/starlabs/starfighter/variants/mtl/devicetree.cb
@@ -224,6 +224,7 @@ chip soc/intel/meteorlake
 				end
 			end
 		end
+		device ref pmc_shared_sram on  end
 		device ref i2c0		on
 			chip drivers/i2c/hid
 				register "generic.hid"		= ""STAR0001""

From e85a0b7ff1fa2e7c97211324957dc162b0b8baa0 Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Sun, 23 Nov 2025 17:37:45 -0600
Subject: [PATCH 2633/3886] mb/google/puff: Remove unsupported EC features

Remove EC feature definitions that are not supported by the
puff EC firmware:
- LID switch (CONFIG_LID_SWITCH is undefined)
- PS/2 keyboard (CONFIG_CMD_KEYBOARD is undefined)
- Keyboard backlight (not configured)

Also remove corresponding host event masks from SCI, SMI, and
wake event definitions.

All of these were remnants from puff originally being part of the
hatch mainboard, from which it was split off.

TEST=build/boot google/puff/var/wyvern

Change-Id: Idd86d4f342d29a25bd640d480cd5834e6250bcf0
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90155
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
---
 .../variants/baseboard/include/baseboard/ec.h | 25 ++++---------------
 1 file changed, 5 insertions(+), 20 deletions(-)

diff --git a/src/mainboard/google/puff/variants/baseboard/include/baseboard/ec.h b/src/mainboard/google/puff/variants/baseboard/include/baseboard/ec.h
index a1a71c0fd0..451db39faa 100644
--- a/src/mainboard/google/puff/variants/baseboard/include/baseboard/ec.h
+++ b/src/mainboard/google/puff/variants/baseboard/include/baseboard/ec.h
@@ -7,9 +7,7 @@
 #include <variant/gpio.h>
 
 #define MAINBOARD_EC_SCI_EVENTS \
-	(EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED)        |\
-	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN)          |\
-	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_CONNECTED)      |\
+	(EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_CONNECTED)      |\
 	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_DISCONNECTED)   |\
 	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_LOW)       |\
 	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_CRITICAL)  |\
@@ -21,21 +19,17 @@
 	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_PD_MCU)            |\
 	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_MODE_CHANGE))
 
-#define MAINBOARD_EC_SMI_EVENTS \
-	(EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED))
+#define MAINBOARD_EC_SMI_EVENTS
 
-/* EC can wake from S5 with lid or power button */
+/* EC can wake from S5 with power button */
 #define MAINBOARD_EC_S5_WAKE_EVENTS \
-	(EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) |\
-	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_POWER_BUTTON))
+	(EC_HOST_EVENT_MASK(EC_HOST_EVENT_POWER_BUTTON))
 
 /*
- * EC can wake from S3 with lid or power button or key press or
- * mode change event.
+ * EC can wake from S3 with power button or mode change event.
  */
 #define MAINBOARD_EC_S3_WAKE_EVENTS \
 	(MAINBOARD_EC_S5_WAKE_EVENTS |\
-	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEY_PRESSED) |\
 	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_MKBP)        |\
 	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_MODE_CHANGE))
 
@@ -56,21 +50,12 @@
 /* Enable EC backed PD MCU device in ACPI */
 #define EC_ENABLE_PD_MCU_DEVICE
 
-/* Enable LID switch and provide wake pin for EC */
-#define EC_ENABLE_LID_SWITCH
 #define EC_ENABLE_WAKE_PIN	GPE_EC_WAKE
 
-/* Enable Tablet switch */
-#define EC_ENABLE_TBMC_DEVICE
-
 #define SIO_EC_MEMMAP_ENABLE	/* EC Memory Map Resources */
 #define SIO_EC_HOST_ENABLE	/* EC Host Interface Resources */
-#define SIO_EC_ENABLE_PS2K      /* Enable PS/2 Keyboard */
 
 /* Enable EC sync interrupt, EC_SYNC_IRQ is defined in baseboard/gpio.h */
 #define EC_ENABLE_SYNC_IRQ
 
-/* Enable EC backed Keyboard Backlight in ACPI */
-#define EC_ENABLE_KEYBOARD_BACKLIGHT
-
 #endif /* __BASEBOARD_EC_H__ */

From 4dc03c54fccfbe841c0d27a7d9bac6df6e76867c Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Mon, 17 Nov 2025 15:13:54 -0600
Subject: [PATCH 2634/3886] mb/google/poppy/var/nocturne: Hide FPR device in
 ACPI

Set FPR (Fingerprint Reader) device status to hidden to prevent
Windows from enumerating it, as Windows does not support the FPR
on this platform. Linux ignores ACPI device status and continues
to work correctly via direct SPI access.

TEST=build/boot Win11, Linux on Nocturne.

Change-Id: I8806cbef3acbab45ddd03e9fa80f79625c84bcb4
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90156
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/google/poppy/variants/nocturne/devicetree.cb | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/mainboard/google/poppy/variants/nocturne/devicetree.cb b/src/mainboard/google/poppy/variants/nocturne/devicetree.cb
index d5149d85a1..8cdfc2b756 100644
--- a/src/mainboard/google/poppy/variants/nocturne/devicetree.cb
+++ b/src/mainboard/google/poppy/variants/nocturne/devicetree.cb
@@ -359,7 +359,7 @@ chip soc/intel/skylake
 				register "compat_string" = ""google,cros-ec-spi""
 				register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_C11_IRQ)"
 				register "wake" = "GPE0_DW0_09" # GPP_C9
-				device spi 0 on end
+				device spi 0 hidden end
 			end # FPMCU
 		end
 		device ref emmc 		on  end

From e15895b5c4566ddcd7ee1f1e10a4b92e2d95465a Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Mon, 17 Nov 2025 15:16:16 -0600
Subject: [PATCH 2635/3886] mb/google/poppy/var/nautilus/acpi: Fix CI02 comment

The camera ACPI code was likely copy/pasted from another board, and
while the ACPI itself is correct, the comment is not. Fix the comment
to match the code / actual board config.

TEST=n/a; this change is non-functional.

Change-Id: I10eb20d9f51e1bc0cd4589c11ac39d23ed836bf4
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90157
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
---
 .../nautilus/include/variant/acpi/ipu_mainboard.asl         | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/src/mainboard/google/poppy/variants/nautilus/include/variant/acpi/ipu_mainboard.asl b/src/mainboard/google/poppy/variants/nautilus/include/variant/acpi/ipu_mainboard.asl
index 453b7d333e..0a81bc45bc 100644
--- a/src/mainboard/google/poppy/variants/nautilus/include/variant/acpi/ipu_mainboard.asl
+++ b/src/mainboard/google/poppy/variants/nautilus/include/variant/acpi/ipu_mainboard.asl
@@ -2,9 +2,9 @@
 
 Scope (\_SB.PCI0.CIO2)
 {
-        /* Define two ports for CIO2 device where endpoint of port0
-	is connected to CAM0 and endpoint of port1 is connected to CAM1
-	Endpoints can be customized by the variants of the based board */
+	/* Define the port for CIO2 device where endpoint of port0
+	 * is connected to CAM0.
+	 * Endpoints can be customized by the variants of the based board */
 
 	Name (_DSD, Package () {
 		ToUUID ("dbb8e3e6-5886-4ba6-8795-1319f52a966b"),

From 7ed515d1c3a264c3d3fc79683ab0c59f0705c467 Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Sun, 31 Aug 2025 15:40:55 -0500
Subject: [PATCH 2636/3886] mb/google/auron/Makefile: Organize and group
 entries by stage

Tidy up before adding a new entry.

Change-Id: I33b0b4cf99534eb9dbc28d43286656488d1f498c
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90164
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/google/auron/Makefile.mk | 20 ++++++++------------
 1 file changed, 8 insertions(+), 12 deletions(-)

diff --git a/src/mainboard/google/auron/Makefile.mk b/src/mainboard/google/auron/Makefile.mk
index f642243667..d77f85a85b 100644
--- a/src/mainboard/google/auron/Makefile.mk
+++ b/src/mainboard/google/auron/Makefile.mk
@@ -1,26 +1,22 @@
 ## SPDX-License-Identifier: GPL-2.0-only
 
-ramstage-$(CONFIG_EC_GOOGLE_CHROMEEC) += ec.c
-
-romstage-$(CONFIG_CHROMEOS) += chromeos.c
-ramstage-$(CONFIG_CHROMEOS) += chromeos.c
 bootblock-$(CONFIG_CHROMEOS) += chromeos.c
 
-romstage-$(CONFIG_HAVE_SPD_IN_CBFS) += spd.c
-
+romstage-$(CONFIG_CHROMEOS) += chromeos.c
+romstage-y += variants/$(VARIANT_DIR)/gpio.c
 romstage-y += variants/$(VARIANT_DIR)/pei_data.c
-ramstage-y += variants/$(VARIANT_DIR)/pei_data.c
-
+romstage-$(CONFIG_HAVE_SPD_IN_CBFS) += spd.c
 ifneq ($(CONFIG_BOARD_GOOGLE_BUDDY),y)
 romstage-y += variants/$(VARIANT_DIR)/variant.c
 endif
+
+ramstage-$(CONFIG_CHROMEOS) += chromeos.c
+ramstage-$(CONFIG_EC_GOOGLE_CHROMEEC) += ec.c
+ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads
+ramstage-y += variants/$(VARIANT_DIR)/pei_data.c
 ramstage-y += variants/$(VARIANT_DIR)/variant.c
 
 subdirs-y += variants/$(VARIANT_DIR)
 subdirs-y += variants/$(VARIANT_DIR)/spd
 
 CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/include
-
-romstage-y += variants/$(VARIANT_DIR)/gpio.c
-
-ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads

From 88d3f563b3ef5739cfa8777a719a992dcbb1eeab Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Sun, 31 Aug 2025 15:46:57 -0500
Subject: [PATCH 2637/3886] mb/google/auron: Add CFR option menu support

Add CFR option menu support when using edk2 payload and SMMSTORE.
Include relevant items from Broadwell Soc and ChromeEC.

TEST=build/boot google/lulu, verify CFR option functionality.

Change-Id: I9a5d61464cbf88b621c38a3779a7409977f20bed
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90165
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/google/auron/Kconfig     |  1 +
 src/mainboard/google/auron/Makefile.mk |  1 +
 src/mainboard/google/auron/cfr.c       | 33 ++++++++++++++++++++++++++
 3 files changed, 35 insertions(+)
 create mode 100644 src/mainboard/google/auron/cfr.c

diff --git a/src/mainboard/google/auron/Kconfig b/src/mainboard/google/auron/Kconfig
index ac77e1a523..b84708f657 100644
--- a/src/mainboard/google/auron/Kconfig
+++ b/src/mainboard/google/auron/Kconfig
@@ -6,6 +6,7 @@ config BOARD_GOOGLE_BASEBOARD_AURON
 	select ACPI_GNVS_USB_CHARGECTL
 	select BOARD_ROMSIZE_KB_8192
 	select BROADWELL_LPDDR3 if BOARD_GOOGLE_SAMUS
+	select DRIVERS_OPTION_CFR_ENABLED if PAYLOAD_EDK2 && SMMSTORE
 	select EC_GOOGLE_CHROMEEC
 	select EC_GOOGLE_CHROMEEC_LPC
 	select HAVE_ACPI_RESUME
diff --git a/src/mainboard/google/auron/Makefile.mk b/src/mainboard/google/auron/Makefile.mk
index d77f85a85b..59118d76a6 100644
--- a/src/mainboard/google/auron/Makefile.mk
+++ b/src/mainboard/google/auron/Makefile.mk
@@ -10,6 +10,7 @@ ifneq ($(CONFIG_BOARD_GOOGLE_BUDDY),y)
 romstage-y += variants/$(VARIANT_DIR)/variant.c
 endif
 
+ramstage-$(CONFIG_DRIVERS_OPTION_CFR) += cfr.c
 ramstage-$(CONFIG_CHROMEOS) += chromeos.c
 ramstage-$(CONFIG_EC_GOOGLE_CHROMEEC) += ec.c
 ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads
diff --git a/src/mainboard/google/auron/cfr.c b/src/mainboard/google/auron/cfr.c
new file mode 100644
index 0000000000..e1d352665b
--- /dev/null
+++ b/src/mainboard/google/auron/cfr.c
@@ -0,0 +1,33 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <boot/coreboot_tables.h>
+#include <drivers/option/cfr_frontend.h>
+#include <ec/google/chromeec/cfr.h>
+#include <soc/cfr.h>
+
+static struct sm_obj_form system = {
+	.ui_name = "System",
+	.obj_list = (const struct sm_object *[]) {
+		&me_disable,
+		NULL
+	},
+};
+
+static struct sm_obj_form ec = {
+	.ui_name = "ChromeEC Embedded Controller",
+	.obj_list = (const struct sm_object *[]) {
+		&auto_fan_control,
+		&ec_kb_backlight,
+		NULL
+	},
+};
+static struct sm_obj_form *sm_root[] = {
+	&system,
+	&ec,
+	NULL
+};
+
+void mb_cfr_setup_menu(struct lb_cfr *cfr_root)
+{
+	cfr_write_setup_menu(cfr_root, sm_root);
+}

From 6be83443e5abf6ed07b0beda1fdaef077b986c72 Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Wed, 15 Oct 2025 10:57:00 -0500
Subject: [PATCH 2638/3886] mb/google/auron/var/lulu: Add CFR option to
 enable/disable touchscreen

Some LULU boards are equipped with a touchscreen, others are not. Since
Broadwell doesn't support the use of the i2c generic driver and runtime
detection, add a CFR menu option to allow selective disabling of the
touchscreen ACPI device by users whose boards do not have one.
This prevents a malfunctioning touchscreen device from appearing in
Device Manager under Windows.

TEST=build/boot lulu, boot Win11, verify no malfunctoning touchscreen
device shown in Device Manager when disabled in CFR option menu.

Change-Id: I423ef1cf085bc488b4740092b992a245e3fd7e7e
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90166
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/google/auron/cfr.c       | 24 ++++++++++++++++++++++++
 src/mainboard/google/auron/mainboard.c | 15 +++++++++++++++
 2 files changed, 39 insertions(+)

diff --git a/src/mainboard/google/auron/cfr.c b/src/mainboard/google/auron/cfr.c
index e1d352665b..90106a5586 100644
--- a/src/mainboard/google/auron/cfr.c
+++ b/src/mainboard/google/auron/cfr.c
@@ -5,6 +5,20 @@
 #include <ec/google/chromeec/cfr.h>
 #include <soc/cfr.h>
 
+static const struct sm_object touchscreen = SM_DECLARE_ENUM({
+	.opt_name	= "touchscreen",
+	.ui_name	= "Touchscreen",
+	.ui_helptext	= "Enable or disable the integrated touchscreen device",
+	.default_value	= 1,
+	.values		= (const struct sm_enum_value[]) {
+		{ "Disabled",		0		},
+		{ "Enabled",		1		},
+		SM_ENUM_VALUE_END			},
+#if !CONFIG(BOARD_GOOGLE_LULU)
+	.flags		= CFR_OPTFLAG_SUPPRESS,
+#endif
+});
+
 static struct sm_obj_form system = {
 	.ui_name = "System",
 	.obj_list = (const struct sm_object *[]) {
@@ -21,8 +35,18 @@ static struct sm_obj_form ec = {
 		NULL
 	},
 };
+
+static struct sm_obj_form devices = {
+	.ui_name = "Devices",
+	.obj_list = (const struct sm_object *[]) {
+		&touchscreen,
+		NULL
+	},
+};
+
 static struct sm_obj_form *sm_root[] = {
 	&system,
+	&devices,
 	&ec,
 	NULL
 };
diff --git a/src/mainboard/google/auron/mainboard.c b/src/mainboard/google/auron/mainboard.c
index ed2e7b889c..14c8f67642 100644
--- a/src/mainboard/google/auron/mainboard.c
+++ b/src/mainboard/google/auron/mainboard.c
@@ -1,7 +1,9 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
+#include <acpi/acpigen.h>
 #include <device/device.h>
 #include <drivers/intel/gma/int15.h>
+#include <option.h>
 #include "ec.h"
 #include "variant.h"
 
@@ -15,6 +17,18 @@ static void mainboard_init(struct device *dev)
 	lan_init();
 }
 
+static void mainboard_fill_ssdt(const struct device *dev)
+{
+	if (CONFIG(BOARD_GOOGLE_LULU)) {
+		/* Get touchscreen enable option from CFR */
+		unsigned int touchscreen_enabled = get_uint_option("touchscreen", 1);
+
+		acpigen_write_scope("\\_SB.PCI0.I2C1");
+		acpigen_write_store_int_to_namestr(touchscreen_enabled ? 1 : 0, "S2EN");
+		acpigen_pop_len(); /* Scope */
+	}
+}
+
 static int mainboard_smbios_data(struct device *dev, int *handle,
 				 unsigned long *current)
 {
@@ -25,6 +39,7 @@ static void mainboard_enable(struct device *dev)
 {
 	dev->ops->init = mainboard_init;
 	dev->ops->get_smbios_data = mainboard_smbios_data;
+	dev->ops->acpi_fill_ssdt = mainboard_fill_ssdt;
 	install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_EDP, GMA_INT15_PANEL_FIT_CENTERING, GMA_INT15_BOOT_DISPLAY_DEFAULT, 0);
 }
 

From e366e0ba7d2caf986bb7a80959373ba5717bd385 Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Sun, 31 Aug 2025 15:32:11 -0500
Subject: [PATCH 2639/3886] mb/google/slippy/Makefile: Organize and group
 entries by stage

Tidy up before adding a new entry.

Change-Id: Ib37c9b4b73819b1309a7c2405830f1524e3d3f74
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90161
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
---
 src/mainboard/google/slippy/Makefile.mk | 10 ++++------
 1 file changed, 4 insertions(+), 6 deletions(-)

diff --git a/src/mainboard/google/slippy/Makefile.mk b/src/mainboard/google/slippy/Makefile.mk
index 2a2541d477..990819e16d 100644
--- a/src/mainboard/google/slippy/Makefile.mk
+++ b/src/mainboard/google/slippy/Makefile.mk
@@ -1,15 +1,13 @@
 ## SPDX-License-Identifier: GPL-2.0-only
 
-ramstage-$(CONFIG_EC_GOOGLE_CHROMEEC) += ec.c
-
 romstage-$(CONFIG_CHROMEOS) += chromeos.c
-ramstage-$(CONFIG_CHROMEOS) += chromeos.c
-
 romstage-y += variants/$(VARIANT_DIR)/gpio.c
 romstage-y += variants/$(VARIANT_DIR)/romstage.c
 
-subdirs-y += variants/$(VARIANT_DIR)
-
+ramstage-$(CONFIG_CHROMEOS) += chromeos.c
+ramstage-$(CONFIG_EC_GOOGLE_CHROMEEC) += ec.c
 ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads
 
+subdirs-y += variants/$(VARIANT_DIR)
+
 CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/include

From 6f6a10df88710d2b5da41e9c8a74e6393bdb8aeb Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Sun, 31 Aug 2025 15:37:00 -0500
Subject: [PATCH 2640/3886] mb/google/slippy: Add CFR option menu support

Add CFR option menu support when using edk2 payload and SMMSTORE.
Include relevant items from Haswell/Lynxpoint/ChromeEC.

TEST=build/boot google/wolf, verify CFR option functionality.

Change-Id: Ife64d46a9866c67fbb941cc83428f7728c6f7f95
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90162
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
---
 src/mainboard/google/slippy/Kconfig     |  1 +
 src/mainboard/google/slippy/Makefile.mk |  1 +
 src/mainboard/google/slippy/cfr.c       | 33 +++++++++++++++++++++++++
 3 files changed, 35 insertions(+)
 create mode 100644 src/mainboard/google/slippy/cfr.c

diff --git a/src/mainboard/google/slippy/Kconfig b/src/mainboard/google/slippy/Kconfig
index 08239eb72f..d9684d34b3 100644
--- a/src/mainboard/google/slippy/Kconfig
+++ b/src/mainboard/google/slippy/Kconfig
@@ -5,6 +5,7 @@ config BOARD_GOOGLE_BASEBOARD_SLIPPY
 	select AZALIA_USE_LEGACY_VERB_TABLE
 	select ACPI_GNVS_USB_CHARGECTL
 	select BOARD_ROMSIZE_KB_8192
+	select DRIVERS_OPTION_CFR_ENABLED if PAYLOAD_EDK2 && SMMSTORE
 	select EC_GOOGLE_CHROMEEC
 	select EC_GOOGLE_CHROMEEC_LPC
 	select HAVE_ACPI_RESUME
diff --git a/src/mainboard/google/slippy/Makefile.mk b/src/mainboard/google/slippy/Makefile.mk
index 990819e16d..7954d5c8bd 100644
--- a/src/mainboard/google/slippy/Makefile.mk
+++ b/src/mainboard/google/slippy/Makefile.mk
@@ -4,6 +4,7 @@ romstage-$(CONFIG_CHROMEOS) += chromeos.c
 romstage-y += variants/$(VARIANT_DIR)/gpio.c
 romstage-y += variants/$(VARIANT_DIR)/romstage.c
 
+ramstage-$(CONFIG_DRIVERS_OPTION_CFR) += cfr.c
 ramstage-$(CONFIG_CHROMEOS) += chromeos.c
 ramstage-$(CONFIG_EC_GOOGLE_CHROMEEC) += ec.c
 ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads
diff --git a/src/mainboard/google/slippy/cfr.c b/src/mainboard/google/slippy/cfr.c
new file mode 100644
index 0000000000..a9801ed578
--- /dev/null
+++ b/src/mainboard/google/slippy/cfr.c
@@ -0,0 +1,33 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <boot/coreboot_tables.h>
+#include <drivers/option/cfr_frontend.h>
+#include <ec/google/chromeec/cfr.h>
+#include <southbridge/intel/lynxpoint/cfr.h>
+
+static struct sm_obj_form system = {
+	.ui_name = "System",
+	.obj_list = (const struct sm_object *[]) {
+		&me_disable,
+		&nmi,
+		NULL
+	},
+};
+
+static struct sm_obj_form ec = {
+	.ui_name = "ChromeEC Embedded Controller",
+	.obj_list = (const struct sm_object *[]) {
+		&auto_fan_control,
+		NULL
+	},
+};
+static struct sm_obj_form *sm_root[] = {
+	&system,
+	&ec,
+	NULL
+};
+
+void mb_cfr_setup_menu(struct lb_cfr *cfr_root)
+{
+	cfr_write_setup_menu(cfr_root, sm_root);
+}

From 8753155f713b9f775c79168c773311c07cd06944 Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Wed, 15 Oct 2025 13:27:42 -0500
Subject: [PATCH 2641/3886] mb/google/slippy/var/peppy: Add CFR menu option for
 touchpad type

Peppy has two touchpad options, and having the ACPI device for both
enabled under Windows causes issues, as they use the same resources.
Since Peppy can't use the runtime detection feature supported by
newer platforms, add a CFR menu option to select between the two.
Default to both touchpad devices being enabled, so that there
is no change in behavior until the user changes the option.

TEST=build/boot Win11/Linux on google/peppy, verify touchpad
functional under both OSes when correct touchpad type selected,
and functional under Linux when Auto-detect is selected.

Change-Id: I0e63a252cd5bbc04244c9999b7586480891013a5
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90163
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
---
 src/mainboard/google/slippy/cfr.c             | 25 +++++++++++++++++++
 src/mainboard/google/slippy/mainboard.c       | 25 +++++++++++++++++--
 .../peppy/include/variant/acpi/mainboard.asl  |  6 +++--
 3 files changed, 52 insertions(+), 4 deletions(-)

diff --git a/src/mainboard/google/slippy/cfr.c b/src/mainboard/google/slippy/cfr.c
index a9801ed578..07ff82c029 100644
--- a/src/mainboard/google/slippy/cfr.c
+++ b/src/mainboard/google/slippy/cfr.c
@@ -5,6 +5,21 @@
 #include <ec/google/chromeec/cfr.h>
 #include <southbridge/intel/lynxpoint/cfr.h>
 
+static const struct sm_object touchpad_type = SM_DECLARE_ENUM({
+	.opt_name	= "touchpad_type",
+	.ui_name	= "Touchpad Type",
+	.ui_helptext	= "Select the installed touchpad type",
+	.default_value	= 0,
+	.values		= (const struct sm_enum_value[]) {
+		{ "Auto-detect",	0	},
+		{ "Elan",		1	},
+		{ "Cypress",		2	},
+		SM_ENUM_VALUE_END		},
+#if !CONFIG(BOARD_GOOGLE_PEPPY)
+	.flags		= CFR_OPTFLAG_SUPPRESS,
+#endif
+});
+
 static struct sm_obj_form system = {
 	.ui_name = "System",
 	.obj_list = (const struct sm_object *[]) {
@@ -21,8 +36,18 @@ static struct sm_obj_form ec = {
 		NULL
 	},
 };
+
+static struct sm_obj_form devices = {
+	.ui_name = "Devices",
+	.obj_list = (const struct sm_object *[]) {
+		&touchpad_type,
+		NULL
+	},
+};
+
 static struct sm_obj_form *sm_root[] = {
 	&system,
+	&devices,
 	&ec,
 	NULL
 };
diff --git a/src/mainboard/google/slippy/mainboard.c b/src/mainboard/google/slippy/mainboard.c
index 8d470f4ba6..00bc1c7f94 100644
--- a/src/mainboard/google/slippy/mainboard.c
+++ b/src/mainboard/google/slippy/mainboard.c
@@ -1,14 +1,20 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
-#include <smbios.h>
+#include <acpi/acpi.h>
+#include <acpi/acpigen.h>
 #include <cpu/x86/smm.h>
 #include <device/device.h>
 #include <drivers/intel/gma/int15.h>
-#include <acpi/acpi.h>
+#include <option.h>
+#include <smbios.h>
 #include <southbridge/intel/lynxpoint/pch.h>
 #include "ec.h"
 #include "onboard.h"
 
+#define TP_TYPE_AUTO	0
+#define TP_TYPE_ELAN	1
+#define TP_TYPE_CYPRESS	2
+
 void mainboard_suspend_resume(void)
 {
 	/* Call SMM finalize() handlers before resume */
@@ -20,6 +26,20 @@ static void mainboard_init(struct device *dev)
 	mainboard_ec_init();
 }
 
+static void mainboard_fill_ssdt(const struct device *dev)
+{
+	if (CONFIG(BOARD_GOOGLE_PEPPY)) {
+		/* Get touchpad type option from CFR; enable both if not specified */
+		unsigned int touchpad_type = get_uint_option("touchpad_type", TP_TYPE_AUTO);
+
+		acpigen_write_scope("\\_SB.PCI0.I2C0");
+		/* 0 = Enalble both, 1 = Elan, 2 = Cypress */
+		acpigen_write_name_integer("ETPD", touchpad_type != TP_TYPE_CYPRESS ? 1 : 0);
+		acpigen_write_name_integer("CTPD", touchpad_type != TP_TYPE_ELAN ? 1 : 0);
+		acpigen_pop_len(); /* Scope */
+	}
+}
+
 static int mainboard_smbios_data(struct device *dev, int *handle,
 				 unsigned long *current)
 {
@@ -62,6 +82,7 @@ static void mainboard_enable(struct device *dev)
 {
 	dev->ops->init = mainboard_init;
 	dev->ops->get_smbios_data = mainboard_smbios_data;
+	dev->ops->acpi_fill_ssdt = mainboard_fill_ssdt;
 	install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_EDP, GMA_INT15_PANEL_FIT_CENTERING, GMA_INT15_BOOT_DISPLAY_DEFAULT, 0);
 }
 
diff --git a/src/mainboard/google/slippy/variants/peppy/include/variant/acpi/mainboard.asl b/src/mainboard/google/slippy/variants/peppy/include/variant/acpi/mainboard.asl
index a96ec197dd..7e7c6ab414 100644
--- a/src/mainboard/google/slippy/variants/peppy/include/variant/acpi/mainboard.asl
+++ b/src/mainboard/google/slippy/variants/peppy/include/variant/acpi/mainboard.asl
@@ -8,6 +8,7 @@ Scope (\_SB.PCI0.I2C0)
 		Name (_DDN, "Elan Touchpad")
 		Name (_UID, 1)
                 Name (ISTP, 1) // Touchpad
+		External (ETPD, IntObj)
 
                 Name (_CRS, ResourceTemplate()
 		{
@@ -26,7 +27,7 @@ Scope (\_SB.PCI0.I2C0)
 
 		Method (_STA)
 		{
-			If (\S1EN == 1) {
+			If (ETPD == 1) {
 				Return (0xF)
 			} Else {
 				Return (0x0)
@@ -50,6 +51,7 @@ Scope (\_SB.PCI0.I2C0)
 		Name (_DDN, "Cypress Touchpad")
 		Name (_UID, 3)
 		Name (ISTP, 1) // Touchpad
+		External (CTPD, IntObj)
 
 		Name (_CRS, ResourceTemplate()
 		{
@@ -68,7 +70,7 @@ Scope (\_SB.PCI0.I2C0)
 
 		Method (_STA)
 		{
-			If (\S1EN == 1) {
+			If (CTPD == 1) {
 				Return (0xF)
 			} Else {
 				Return (0x0)

From e4a809d441550913f5ffaecea861a29a7661e3d8 Mon Sep 17 00:00:00 2001
From: "Johann C. Rode" <jcrode@gmx.net>
Date: Fri, 28 Nov 2025 10:13:10 -0800
Subject: [PATCH 2642/3886] spd/ddr4: Double packageBusWidth of dual die
 package parts to 16

This fixes an error I made in my previous commit 8a83b8625483 (spd/ddr4:
add parts), CB:90032. The package bus width for all the dual die parts
is indeed 16 rather than 8. This has been validated when porting
coreboot to the Lenovo Thinkpad X280 that uses soldered-on DDP RAM
(Samsung K4AAG165WB-MCRC).

Change-Id: I8baa7c979074584e65772315e66e787cef3202e4
Signed-off-by: Johann C. Rode <jcrode@gmx.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90263
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
---
 spd/ddr4/memory_parts.json | 8 ++++----
 spd/ddr4/set-0/spd-11.hex  | 4 ++--
 spd/ddr4/set-0/spd-13.hex  | 4 ++--
 3 files changed, 8 insertions(+), 8 deletions(-)

diff --git a/spd/ddr4/memory_parts.json b/spd/ddr4/memory_parts.json
index 7684401cdf..0d416f89fa 100644
--- a/spd/ddr4/memory_parts.json
+++ b/spd/ddr4/memory_parts.json
@@ -280,7 +280,7 @@
                 "CL_nRCD_nRP": 15,
                 "capacityPerDieGb": 8,
                 "diesPerPackage": 2,
-                "packageBusWidth": 8,
+                "packageBusWidth": 16,
                 "ranksPerPackage": 1
             }
         },
@@ -313,7 +313,7 @@
                 "CL_nRCD_nRP": 17,
                 "capacityPerDieGb": 8,
                 "diesPerPackage": 2,
-                "packageBusWidth": 8,
+                "packageBusWidth": 16,
                 "ranksPerPackage": 1
             }
         },
@@ -346,7 +346,7 @@
                 "CL_nRCD_nRP": 17,
                 "capacityPerDieGb": 8,
                 "diesPerPackage": 2,
-                "packageBusWidth": 8,
+                "packageBusWidth": 16,
                 "ranksPerPackage": 1
             }
         },
@@ -368,7 +368,7 @@
                 "CL_nRCD_nRP": 17,
                 "capacityPerDieGb": 8,
                 "diesPerPackage": 2,
-                "packageBusWidth": 8,
+                "packageBusWidth": 16,
                 "ranksPerPackage": 1
             }
         },
diff --git a/spd/ddr4/set-0/spd-11.hex b/spd/ddr4/set-0/spd-11.hex
index a29187c06a..9b760a7db7 100644
--- a/spd/ddr4/set-0/spd-11.hex
+++ b/spd/ddr4/set-0/spd-11.hex
@@ -1,11 +1,11 @@
 23 11 0C 03 85 21 91 08 00 00 00 00 01 03 00 00
 00 00 08 09 F4 03 00 00 71 71 71 11 08 79 F0 0A
-20 08 00 05 00 A8 1E 2B 2B 00 78 00 14 3C 00 00
+20 08 00 05 00 F0 2B 34 2B 00 78 00 14 3C 00 00
 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 EC B5 FE C3 C3 C3 C3 CA C1 00 00
+00 00 00 00 00 EC 9C B5 C3 C3 C3 C3 CA C1 00 00
 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
diff --git a/spd/ddr4/set-0/spd-13.hex b/spd/ddr4/set-0/spd-13.hex
index 4d300ee875..324eecb43f 100644
--- a/spd/ddr4/set-0/spd-13.hex
+++ b/spd/ddr4/set-0/spd-13.hex
@@ -1,11 +1,11 @@
 23 11 0C 03 85 21 91 08 00 00 00 00 01 03 00 00
 00 00 07 08 F8 0F 00 00 72 72 72 11 00 72 F0 0A
-20 08 00 05 00 A8 1B 2B 28 00 78 00 14 3C 00 00
+20 08 00 05 00 F0 2B 34 28 00 78 00 14 3C 00 00
 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 B5 D5 AC AC AC AC C1 D6 00 00
+00 00 00 00 00 00 9C B5 AC AC AC AC C1 D6 00 00
 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00

From 4eb524ee9d174e8fe68ceb5d697456d08e555c3b Mon Sep 17 00:00:00 2001
From: "Johann C. Rode" <jcrode@gmx.net>
Date: Fri, 28 Nov 2025 10:19:18 -0800
Subject: [PATCH 2643/3886] spd/ddr4: Add three more parts

This patch adds three more parts that are used in Lenovo Thinkpads:

SKHynix H5AN4G6NAFR-UHC
SKHynix H5ANAG6NAMR-UHC
Micron MT40A512M16LY-075:H

The settings (MT/s, timing, organization, etc.) have been obtained from
schematics and datasheets.

Change-Id: Ie0958a4a845f072daee3379731f558584dca5da6
Signed-off-by: Johann C. Rode <jcrode@gmx.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90253
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
---
 spd/ddr4/memory_parts.json                    | 33 +++++++++++++++++++
 .../set-0/parts_spd_manifest.generated.txt    |  3 ++
 spd/ddr4/set-0/spd-16.hex                     | 32 ++++++++++++++++++
 3 files changed, 68 insertions(+)
 create mode 100644 spd/ddr4/set-0/spd-16.hex

diff --git a/spd/ddr4/memory_parts.json b/spd/ddr4/memory_parts.json
index 0d416f89fa..8a863efec0 100644
--- a/spd/ddr4/memory_parts.json
+++ b/spd/ddr4/memory_parts.json
@@ -404,6 +404,39 @@
                 "packageBusWidth": 16,
                 "ranksPerPackage": 1
             }
+        },
+        {
+            "name": "H5AN4G6NAFR-UHC",
+            "attribs": {
+                "speedMTps": 2400,
+                "CL_nRCD_nRP": 17,
+                "capacityPerDieGb": 4,
+                "diesPerPackage": 1,
+                "packageBusWidth": 16,
+                "ranksPerPackage": 1
+            }
+        },
+        {
+            "name": "H5ANAG6NAMR-UHC",
+            "attribs": {
+                "speedMTps": 2400,
+                "CL_nRCD_nRP": 17,
+                "capacityPerDieGb": 4,
+                "diesPerPackage": 2,
+                "packageBusWidth": 16,
+                "ranksPerPackage": 1
+            }
+        },
+        {
+            "name": "MT40A512M16LY-075:H",
+            "attribs": {
+                "speedMTps": 2400,
+                "CL_nRCD_nRP": 17,
+                "capacityPerDieGb": 8,
+                "diesPerPackage": 1,
+                "packageBusWidth": 16,
+                "ranksPerPackage": 1
+            }
         }
     ]
 }
diff --git a/spd/ddr4/set-0/parts_spd_manifest.generated.txt b/spd/ddr4/set-0/parts_spd_manifest.generated.txt
index 440d4c1dab..37b9b53f0c 100644
--- a/spd/ddr4/set-0/parts_spd_manifest.generated.txt
+++ b/spd/ddr4/set-0/parts_spd_manifest.generated.txt
@@ -35,3 +35,6 @@ H5AN8G6NAMR-UHC,spd-13.hex
 MT40A512M16LY-075:E,spd-12.hex
 MT40A256M16GE-083E:B,spd-14.hex
 K4A4G165WE-BCRC,spd-15.hex
+H5AN4G6NAFR-UHC,spd-15.hex
+H5ANAG6NAMR-UHC,spd-16.hex
+MT40A512M16LY-075:H,spd-12.hex
diff --git a/spd/ddr4/set-0/spd-16.hex b/spd/ddr4/set-0/spd-16.hex
new file mode 100644
index 0000000000..937e0cc335
--- /dev/null
+++ b/spd/ddr4/set-0/spd-16.hex
@@ -0,0 +1,32 @@
+23 11 0C 03 84 19 91 08 00 00 00 00 01 03 00 00
+00 00 07 08 F8 0F 00 00 72 72 72 11 00 72 20 08
+00 05 70 03 00 F0 2B 34 28 00 78 00 14 3C 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 9C B5 AC AC AC AC C1 D6 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 20 20 20 20 20 20 20
+20 20 20 20 20 20 20 20 20 20 20 20 20 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00

From e695731399ddbeddfde3422c1258a2af93bd5fab Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Wed, 12 Nov 2025 08:50:25 -0600
Subject: [PATCH 2644/3886] ec/google/chromeec: Add RGB keyboard helper
 functions and enum

Add enum google_chromeec_rgbkbd_color with predefined color values
(OFF, RED, GREEN, BLUE, YELLOW, WHITE) and helper functions to
detect RGB keyboard support and set keyboard color. The color enum
is converted to RGB struct values internally for EC communication.

These will be used in a subsequent change adding support for setting
the RGB keyboard color at boot via CFR.

TEST=tested with rest of patch train.

Change-Id: I9afcbd8359e0fdc7c89e653165499f693367f5db
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90159
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
---
 src/ec/google/chromeec/ec.c | 80 +++++++++++++++++++++++++++++++++++++
 src/ec/google/chromeec/ec.h | 12 ++++++
 2 files changed, 92 insertions(+)

diff --git a/src/ec/google/chromeec/ec.c b/src/ec/google/chromeec/ec.c
index 662e83e4b2..daf39975dd 100644
--- a/src/ec/google/chromeec/ec.c
+++ b/src/ec/google/chromeec/ec.c
@@ -134,6 +134,86 @@ bool google_chromeec_has_kbbacklight(void)
 	}
 }
 
+static bool google_chromeec_rgb_color_to_struct(enum google_chromeec_rgbkbd_color color,
+						struct rgb_s *rgb)
+{
+	switch (color) {
+	case GOOGLE_CHROMEEC_RGBKBD_COLOR_OFF:
+		*rgb = (struct rgb_s){ .r = 0x00, .g = 0x00, .b = 0x00 };
+		return true;
+	case GOOGLE_CHROMEEC_RGBKBD_COLOR_RED:
+		*rgb = (struct rgb_s){ .r = 0xFF, .g = 0x00, .b = 0x00 };
+		return true;
+	case GOOGLE_CHROMEEC_RGBKBD_COLOR_GREEN:
+		*rgb = (struct rgb_s){ .r = 0x00, .g = 0xFF, .b = 0x00 };
+		return true;
+	case GOOGLE_CHROMEEC_RGBKBD_COLOR_BLUE:
+		*rgb = (struct rgb_s){ .r = 0x00, .g = 0x00, .b = 0xFF };
+		return true;
+	case GOOGLE_CHROMEEC_RGBKBD_COLOR_YELLOW:
+		*rgb = (struct rgb_s){ .r = 0xFF, .g = 0xFF, .b = 0x00 };
+		return true;
+	case GOOGLE_CHROMEEC_RGBKBD_COLOR_WHITE:
+		*rgb = (struct rgb_s){ .r = 0xFF, .g = 0xFF, .b = 0xFF };
+		return true;
+	default:
+		printk(BIOS_DEBUG, "Chrome EC: Invalid RGB keyboard color: %d\n", color);
+		return false;
+	}
+}
+
+bool google_chromeec_has_rgbkbd(void)
+{
+	struct ec_params_rgbkbd params = {
+		.subcmd = EC_RGBKBD_SUBCMD_GET_CONFIG,
+	};
+	struct ec_response_rgbkbd resp = {};
+
+	/* Query the EC to determine if RGB keyboard is supported. */
+	if (ec_cmd_rgbkbd(PLAT_EC, &params, &resp) == 0 &&
+			resp.rgbkbd_type != EC_RGBKBD_TYPE_UNKNOWN) {
+		printk(BIOS_DEBUG, "ChromeEC: RGB keyboard detected (type: %d)\n", resp.rgbkbd_type);
+		return true;
+	}
+
+	printk(BIOS_DEBUG, "Chrome EC: No RGB keyboard\n");
+	return false;
+}
+
+int google_chromeec_rgbkbd_set_color(enum google_chromeec_rgbkbd_color color)
+{
+	struct rgb_s target_rgb;
+
+	if (!google_chromeec_rgb_color_to_struct(color, &target_rgb))
+		return -1;
+
+	/*
+	 * Disable any demo mode so the keyboard will honour the static color
+	 * we are about to set. Ignore failures in case older firmware doesn't
+	 * implement the subcommand.
+	 */
+	struct ec_params_rgbkbd params = {
+		.subcmd = EC_RGBKBD_SUBCMD_DEMO,
+		.demo = EC_RGBKBD_DEMO_OFF,
+	};
+	struct ec_response_rgbkbd resp = {};
+
+	(void)ec_cmd_rgbkbd(PLAT_EC, &params, &resp);
+
+	params = (struct ec_params_rgbkbd){
+		.subcmd = EC_RGBKBD_SUBCMD_CLEAR,
+		.color = target_rgb,
+	};
+
+	if (ec_cmd_rgbkbd(PLAT_EC, &params, &resp) != 0)
+		return -1;
+
+	printk(BIOS_DEBUG, "Chrome EC: RGB keyboard color set to RGB %02x,%02x,%02x\n",
+			target_rgb.r, target_rgb.g, target_rgb.b);
+
+	return 0;
+}
+
 bool google_chromeec_has_fan(void)
 {
 	/* Try the PWM fan feature flag (most reliable for modern ECs) */
diff --git a/src/ec/google/chromeec/ec.h b/src/ec/google/chromeec/ec.h
index 04d5fba1c3..2f29b9d21c 100644
--- a/src/ec/google/chromeec/ec.h
+++ b/src/ec/google/chromeec/ec.h
@@ -81,6 +81,18 @@ uint64_t  google_chromeec_get_events_b(void);
 int google_chromeec_clear_events_b(uint64_t mask);
 int google_chromeec_kbbacklight(int percent);
 bool google_chromeec_has_kbbacklight(void);
+enum google_chromeec_rgbkbd_color {
+	GOOGLE_CHROMEEC_RGBKBD_COLOR_UNSET = -1,
+	GOOGLE_CHROMEEC_RGBKBD_COLOR_OFF = 0,
+	GOOGLE_CHROMEEC_RGBKBD_COLOR_RED,
+	GOOGLE_CHROMEEC_RGBKBD_COLOR_GREEN,
+	GOOGLE_CHROMEEC_RGBKBD_COLOR_BLUE,
+	GOOGLE_CHROMEEC_RGBKBD_COLOR_YELLOW,
+	GOOGLE_CHROMEEC_RGBKBD_COLOR_WHITE,
+	GOOGLE_CHROMEEC_RGBKBD_COLOR_COUNT,
+};
+int google_chromeec_rgbkbd_set_color(enum google_chromeec_rgbkbd_color color);
+bool google_chromeec_has_rgbkbd(void);
 bool google_chromeec_has_fan(void);
 void google_chromeec_post(uint8_t postcode);
 uint8_t google_chromeec_get_switches(void);

From d97cb61b50812c9a1ea68cf96cfdbbbb87f228e1 Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Sun, 23 Nov 2025 18:10:35 -0600
Subject: [PATCH 2645/3886] ec/google/chromeec: Add CFR option for RGB keyboard
 boot color

Add ec_rgb_kb_color CFR option to select RGB keyboard color at
boot. Suppress regular keyboard backlight option when RGB keyboard
is present, as they are mutually exclusive.

TEST=build/boot google/mithrax, verify RGB keyboard option enabled,
all colors able to be set at boot.

Change-Id: I55848931248a70023c49b98190105679f2999ad9
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90160
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
---
 src/ec/google/chromeec/cfr.h | 28 +++++++++++++++++++++++++++-
 src/ec/google/chromeec/ec.c  |  4 ++++
 2 files changed, 31 insertions(+), 1 deletion(-)

diff --git a/src/ec/google/chromeec/cfr.h b/src/ec/google/chromeec/cfr.h
index 93b5bd0d78..2972bd5424 100644
--- a/src/ec/google/chromeec/cfr.h
+++ b/src/ec/google/chromeec/cfr.h
@@ -40,7 +40,7 @@ static const struct sm_enum_value ec_backlight_values[] = {
 
 static void update_kb_backlight(struct sm_object *new)
 {
-	if (!google_chromeec_has_kbbacklight()) {
+	if (!google_chromeec_has_kbbacklight() || google_chromeec_has_rgbkbd()) {
 		new->sm_bool.flags = CFR_OPTFLAG_SUPPRESS;
 		new->sm_bool.default_value = -1;
 	}
@@ -55,4 +55,30 @@ static const struct sm_object ec_kb_backlight = SM_DECLARE_ENUM({
 	.values         = ec_backlight_values,
 }, WITH_CALLBACK(update_kb_backlight));
 
+static const struct sm_enum_value ec_rgb_backlight_values[] = {
+	{ "Off",	GOOGLE_CHROMEEC_RGBKBD_COLOR_OFF },
+	{ "Red",	GOOGLE_CHROMEEC_RGBKBD_COLOR_RED },
+	{ "Green",	GOOGLE_CHROMEEC_RGBKBD_COLOR_GREEN },
+	{ "Blue",	GOOGLE_CHROMEEC_RGBKBD_COLOR_BLUE },
+	{ "Yellow",	GOOGLE_CHROMEEC_RGBKBD_COLOR_YELLOW },
+	{ "White",	GOOGLE_CHROMEEC_RGBKBD_COLOR_WHITE },
+	SM_ENUM_VALUE_END,
+};
+
+static void update_rgb_kb_backlight(struct sm_object *new)
+{
+	if (!google_chromeec_has_rgbkbd()) {
+		new->sm_bool.flags = CFR_OPTFLAG_SUPPRESS;
+		new->sm_bool.default_value = GOOGLE_CHROMEEC_RGBKBD_COLOR_OFF;
+	}
+}
+
+static const struct sm_object ec_rgb_kb_color = SM_DECLARE_ENUM({
+	.opt_name       = "ec_rgb_kb_color",
+	.ui_name        = "RGB Keyboard Color At Boot",
+	.ui_helptext    = "Select the static color applied to the RGB keyboard at boot.",
+	.default_value  = GOOGLE_CHROMEEC_RGBKBD_COLOR_OFF,
+	.values         = ec_rgb_backlight_values,
+}, WITH_CALLBACK(update_rgb_kb_backlight));
+
 #endif /* _CHROMEEC_CFR_H_ */
diff --git a/src/ec/google/chromeec/ec.c b/src/ec/google/chromeec/ec.c
index daf39975dd..b881fa47dc 100644
--- a/src/ec/google/chromeec/ec.c
+++ b/src/ec/google/chromeec/ec.c
@@ -1454,6 +1454,10 @@ void google_chromeec_init(void)
 	int backlight_level = get_uint_option("ec_kb_backlight", -1);
 	if (backlight_level != -1 && !acpi_is_wakeup_s3() && google_chromeec_has_kbbacklight())
 		google_chromeec_kbbacklight(backlight_level);
+
+	int rgb_color = get_uint_option("ec_rgb_kb_color", -1);
+	if (rgb_color != -1 && !acpi_is_wakeup_s3() && google_chromeec_has_rgbkbd())
+		google_chromeec_rgbkbd_set_color((enum google_chromeec_rgbkbd_color)rgb_color);
 }
 
 int google_ec_running_ro(void)

From d09ea1c35123720cc9b55d2404be652a28998829 Mon Sep 17 00:00:00 2001
From: Kilian Krause <kilian.krause@siemens.com>
Date: Tue, 4 Nov 2025 16:35:09 +0100
Subject: [PATCH 2646/3886] cpu/intel: Add SMBIOS Socket BGA1744 type

Enable SMBIOS Processor Upgrade Type reporting for Socket BGA1744.

- Add CPU_INTEL_SOCKET_BGA1744 Kconfig option
- Add socket_BGA1744 subdirectory to build system
- Map to PROCESSOR_UPGRADE_SOCKET_BGA1744 in SMBIOS Type 4

TEST=Built for mc_rpl1, verified `dmidecode -t processor | grep Upgrade`
     shows "Socket BGA1744"

Change-Id: I18123f8ab656d4ca8c540be402f47929f8550ede
Signed-off-by: Kilian Krause <kilian.krause@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89899
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
---
 src/arch/x86/smbios.c                | 2 ++
 src/cpu/intel/Kconfig                | 1 +
 src/cpu/intel/Makefile.mk            | 1 +
 src/cpu/intel/socket_BGA1744/Kconfig | 2 ++
 4 files changed, 6 insertions(+)
 create mode 100644 src/cpu/intel/socket_BGA1744/Kconfig

diff --git a/src/arch/x86/smbios.c b/src/arch/x86/smbios.c
index a59998e3c0..922340a886 100644
--- a/src/arch/x86/smbios.c
+++ b/src/arch/x86/smbios.c
@@ -48,6 +48,8 @@ static int get_socket_type(void)
 {
 	if (CONFIG(CPU_INTEL_SLOT_1))
 		return PROCESSOR_UPGRADE_SLOT_1;
+	if (CONFIG(CPU_INTEL_SOCKET_BGA1744))
+		return PROCESSOR_UPGRADE_SOCKET_BGA1744;
 	if (CONFIG(CPU_INTEL_SOCKET_MPGA604))
 		return PROCESSOR_UPGRADE_SOCKET_MPGA604;
 	if (CONFIG(CPU_INTEL_SOCKET_LGA775))
diff --git a/src/cpu/intel/Kconfig b/src/cpu/intel/Kconfig
index f28bbdbb03..d4a6266f25 100644
--- a/src/cpu/intel/Kconfig
+++ b/src/cpu/intel/Kconfig
@@ -19,6 +19,7 @@ source "src/cpu/intel/haswell/Kconfig"
 # Sockets/Slots
 source "src/cpu/intel/slot_1/Kconfig"
 source "src/cpu/intel/socket_BGA956/Kconfig"
+source "src/cpu/intel/socket_BGA1744/Kconfig"
 source "src/cpu/intel/socket_FCBGA559/Kconfig"
 source "src/cpu/intel/socket_m/Kconfig"
 source "src/cpu/intel/socket_p/Kconfig"
diff --git a/src/cpu/intel/Makefile.mk b/src/cpu/intel/Makefile.mk
index 77b4618663..9ccaa2c78d 100644
--- a/src/cpu/intel/Makefile.mk
+++ b/src/cpu/intel/Makefile.mk
@@ -8,6 +8,7 @@
 subdirs-$(CONFIG_CPU_INTEL_FIRMWARE_INTERFACE_TABLE) += fit
 subdirs-$(CONFIG_CPU_INTEL_SOCKET_441) += socket_441
 subdirs-$(CONFIG_CPU_INTEL_SOCKET_BGA956) += socket_BGA956
+subdirs-$(CONFIG_CPU_INTEL_SOCKET_BGA1744) += socket_BGA1744
 subdirs-$(CONFIG_CPU_INTEL_SOCKET_FCBGA559) += socket_FCBGA559
 subdirs-$(CONFIG_CPU_INTEL_SOCKET_M) += socket_m
 subdirs-$(CONFIG_CPU_INTEL_SOCKET_P) += socket_p
diff --git a/src/cpu/intel/socket_BGA1744/Kconfig b/src/cpu/intel/socket_BGA1744/Kconfig
new file mode 100644
index 0000000000..785f3f487d
--- /dev/null
+++ b/src/cpu/intel/socket_BGA1744/Kconfig
@@ -0,0 +1,2 @@
+config CPU_INTEL_SOCKET_BGA1744
+	bool

From ab4c2fd0e891558df84500a004a74a20c3891b12 Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Sun, 9 Nov 2025 16:50:52 -0600
Subject: [PATCH 2647/3886] drivers/intel/mipi_camera: Extract SSDB definitions
 into separate header
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Move the sensor SSDB struct and enums out of `chip.h` and into a new
`ssdb.h`. This keeps the chip interface header lean while providing a
dedicated spot for the additional SSDB field descriptors coming in
follow-up changes. No functional impact.

Change-Id: Ifb2dddb886f0123b1dfd059400dcacd75174fb6c
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90181
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/drivers/intel/mipi_camera/chip.h |  92 +-----------------------
 src/drivers/intel/mipi_camera/ssdb.h | 100 +++++++++++++++++++++++++++
 2 files changed, 101 insertions(+), 91 deletions(-)
 create mode 100644 src/drivers/intel/mipi_camera/ssdb.h

diff --git a/src/drivers/intel/mipi_camera/chip.h b/src/drivers/intel/mipi_camera/chip.h
index 696f52cc3a..84b7d0431e 100644
--- a/src/drivers/intel/mipi_camera/chip.h
+++ b/src/drivers/intel/mipi_camera/chip.h
@@ -6,6 +6,7 @@
 #include <stdint.h>
 #include <acpi/acpi_pld.h>
 #include <uuid.h>
+#include "ssdb.h"
 
 #define DEFAULT_LINK_FREQ	450000000
 #define MAX_PWDB_ENTRIES	12
@@ -33,43 +34,6 @@
 #define SEQ_OPS_GPIO_DISABLE(ind, delay) \
 	{ .type = GPIO, .index = (ind), .action = DISABLE, .delay_ms = (delay) }
 
-enum camera_device_type {
-	DEV_TYPE_SENSOR = 0,
-	DEV_TYPE_VCM,
-	DEV_TYPE_ROM
-};
-
-enum intel_camera_platform_type {
-	PLATFORM_BXT = 8,
-	PLATFORM_SKC = 9,
-	PLATFORM_CNL = 10,
-	PLATFORM_TGL = 12,
-	PLATFORM_JSL = 14,
-	PLATFORM_ADL = 15,
-	PLATFORM_MTL = 16,
-	PLATFORM_LNL = 17
-};
-
-enum intel_camera_flash_type {
-	FLASH_DEFAULT = 0,
-	FLASH_DISABLE = 2,
-	FLASH_ENABLE = 3
-};
-
-enum intel_camera_led_type {
-	PRIVACY_LED_DEFAULT = 0,
-	PRIVACY_LED_A_16mA
-};
-
-enum intel_camera_mipi_info {
-	MIPI_INFO_SENSOR_DRIVER = 0,
-	MIPI_INFO_ACPI_DEFINED
-};
-
-#define CLK_FREQ_19_2MHZ	19200000
-#define CLK_FREQ_24MHZ		24000000
-#define CLK_FREQ_20MHZ		20000000
-
 enum intel_camera_device_type {
 	INTEL_ACPI_CAMERA_CIO2,
 	INTEL_ACPI_CAMERA_IMGU,
@@ -147,60 +111,6 @@ struct operation_seq {
 	uint8_t ops_cnt;
 };
 
-struct intel_ssdb {
-	uint8_t version;			/* Current version */
-	uint8_t sensor_card_sku;		/* CRD Board type */
-	guid_t csi2_data_stream_interface;	/* CSI2 data stream GUID */
-	uint16_t bdf_value;			/* Bus number of the host
-						controller */
-	uint32_t dphy_link_en_fuses;		/* Host controller's fuses
-						information used to verify if
-						link is fused out or not */
-	uint32_t lanes_clock_division;		/* Lanes/clock divisions per
-						sensor */
-	uint8_t link_used;			/* Link used by this sensor
-						stream */
-	uint8_t lanes_used;			/* Number of lanes connected for
-						the sensor */
-	uint32_t csi_rx_dly_cnt_termen_clane;	/* MIPI timing information */
-	uint32_t csi_rx_dly_cnt_settle_clane;	/* MIPI timing information */
-	uint32_t csi_rx_dly_cnt_termen_dlane0;	/* MIPI timing information */
-	uint32_t csi_rx_dly_cnt_settle_dlane0;	/* MIPI timing information */
-	uint32_t csi_rx_dly_cnt_termen_dlane1;	/* MIPI timing information */
-	uint32_t csi_rx_dly_cnt_settle_dlane1;	/* MIPI timing information */
-	uint32_t csi_rx_dly_cnt_termen_dlane2;	/* MIPI timing information */
-	uint32_t csi_rx_dly_cnt_settle_dlane2;	/* MIPI timing information */
-	uint32_t csi_rx_dly_cnt_termen_dlane3;	/* MIPI timing information */
-	uint32_t csi_rx_dly_cnt_settle_dlane3;	/* MIPI timing information */
-	uint32_t max_lane_speed;		/* Maximum lane speed for
-						the sensor */
-	uint8_t sensor_cal_file_idx;		/* Legacy field for sensor
-						calibration file index */
-	uint8_t sensor_cal_file_idx_mbz[3];	/* Legacy field for sensor
-						calibration file index */
-	uint8_t rom_type;			/* NVM type of the camera
-						module */
-	uint8_t vcm_type;			/* VCM type of the camera
-						module */
-	uint8_t platform;			/* Platform information */
-	uint8_t platform_sub;			/* Platform sub-categories */
-	uint8_t flash_support;			/* Enable/disable flash
-						support */
-	uint8_t privacy_led;			/* Privacy LED support */
-	uint8_t degree;				/* Camera Orientation */
-	uint8_t mipi_define;			/* MIPI info defined in ACPI or
-						sensor driver */
-	uint32_t mclk_speed;			/* Clock info for sensor */
-	uint8_t control_logic_id;		/* PMIC device node used for
-						the camera sensor */
-	uint8_t mipi_data_format;		/* MIPI data format */
-	uint8_t silicon_version;		/* Silicon version */
-	uint8_t customer_id;			/* Customer ID */
-	uint8_t mclk_port;
-	uint8_t reserved[13];			/* Pads SSDB out so the binary blob in ACPI is
-						   the same size as seen on other firmwares.*/
-} __packed;
-
 struct intel_pwdb {
 	char name[32];		/* Name of the resource required by the power
 				action */
diff --git a/src/drivers/intel/mipi_camera/ssdb.h b/src/drivers/intel/mipi_camera/ssdb.h
new file mode 100644
index 0000000000..9845b162cd
--- /dev/null
+++ b/src/drivers/intel/mipi_camera/ssdb.h
@@ -0,0 +1,100 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef __INTEL_MIPI_CAMERA_SSDB_H__
+#define __INTEL_MIPI_CAMERA_SSDB_H__
+
+#include <stdint.h>
+#include <uuid.h>
+
+enum camera_device_type {
+	DEV_TYPE_SENSOR = 0,
+	DEV_TYPE_VCM,
+	DEV_TYPE_ROM
+};
+
+enum intel_camera_platform_type {
+	PLATFORM_BXT = 8,
+	PLATFORM_SKC = 9,
+	PLATFORM_CNL = 10,
+	PLATFORM_TGL = 12,
+	PLATFORM_JSL = 14,
+	PLATFORM_ADL = 15,
+	PLATFORM_MTL = 16,
+	PLATFORM_LNL = 17
+};
+
+enum intel_camera_flash_type {
+	FLASH_DEFAULT = 0,
+	FLASH_DISABLE = 2,
+	FLASH_ENABLE = 3
+};
+
+enum intel_camera_led_type {
+	PRIVACY_LED_DEFAULT = 0,
+	PRIVACY_LED_A_16mA
+};
+
+enum intel_camera_mipi_info {
+	MIPI_INFO_SENSOR_DRIVER = 0,
+	MIPI_INFO_ACPI_DEFINED
+};
+
+#define CLK_FREQ_19_2MHZ	19200000
+#define CLK_FREQ_24MHZ		24000000
+#define CLK_FREQ_20MHZ		20000000
+
+struct intel_ssdb {
+	uint8_t version;			/* Current version */
+	uint8_t sensor_card_sku;		/* CRD Board type */
+	guid_t csi2_data_stream_interface;	/* CSI2 data stream GUID */
+	uint16_t bdf_value;			/* Bus number of the host
+						controller */
+	uint32_t dphy_link_en_fuses;		/* Host controller's fuses
+						information used to verify if
+						link is fused out or not */
+	uint32_t lanes_clock_division;		/* Lanes/clock divisions per
+						sensor */
+	uint8_t link_used;			/* Link used by this sensor
+						stream */
+	uint8_t lanes_used;			/* Number of lanes connected for
+						the sensor */
+	uint32_t csi_rx_dly_cnt_termen_clane;	/* MIPI timing information */
+	uint32_t csi_rx_dly_cnt_settle_clane;	/* MIPI timing information */
+	uint32_t csi_rx_dly_cnt_termen_dlane0;	/* MIPI timing information */
+	uint32_t csi_rx_dly_cnt_settle_dlane0;	/* MIPI timing information */
+	uint32_t csi_rx_dly_cnt_termen_dlane1;	/* MIPI timing information */
+	uint32_t csi_rx_dly_cnt_settle_dlane1;	/* MIPI timing information */
+	uint32_t csi_rx_dly_cnt_termen_dlane2;	/* MIPI timing information */
+	uint32_t csi_rx_dly_cnt_settle_dlane2;	/* MIPI timing information */
+	uint32_t csi_rx_dly_cnt_termen_dlane3;	/* MIPI timing information */
+	uint32_t csi_rx_dly_cnt_settle_dlane3;	/* MIPI timing information */
+	uint32_t max_lane_speed;		/* Maximum lane speed for
+						the sensor */
+	uint8_t sensor_cal_file_idx;		/* Legacy field for sensor
+						calibration file index */
+	uint8_t sensor_cal_file_idx_mbz[3];	/* Legacy field for sensor
+						calibration file index */
+	uint8_t rom_type;			/* NVM type of the camera
+						module */
+	uint8_t vcm_type;			/* VCM type of the camera
+						module */
+	uint8_t platform;			/* Platform information */
+	uint8_t platform_sub;			/* Platform sub-categories */
+	uint8_t flash_support;			/* Enable/disable flash
+						support */
+	uint8_t privacy_led;			/* Privacy LED support */
+	uint8_t degree;				/* Camera Orientation */
+	uint8_t mipi_define;			/* MIPI info defined in ACPI or
+						sensor driver */
+	uint32_t mclk_speed;			/* Clock info for sensor */
+	uint8_t control_logic_id;		/* PMIC device node used for
+						the camera sensor */
+	uint8_t mipi_data_format;		/* MIPI data format */
+	uint8_t silicon_version;		/* Silicon version */
+	uint8_t customer_id;			/* Customer ID */
+	uint8_t mclk_port;
+	uint8_t reserved[13];			/* Pads SSDB out so the binary blob in ACPI is
+						   the same size as seen on other firmwares.*/
+} __packed;
+
+#endif

From b5d68e41a2af98d9a5797a52f380dd91846c68fd Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Sun, 9 Nov 2025 18:16:55 -0600
Subject: [PATCH 2648/3886] drivers/intel/mipi_camera: Tidy SSDB comment
 wrapping

Reflow the multiline comments in `ssdb.h` to 100 columns.
While this slightly exceeds the 96 column recommended limit in the
coding style guide, the overall effect improves rather than reduces
readability.

Change-Id: I5b98d48ea5a99e38eb3472dfd24be434433857cc
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90182
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
---
 src/drivers/intel/mipi_camera/ssdb.h | 41 ++++++++++------------------
 1 file changed, 14 insertions(+), 27 deletions(-)

diff --git a/src/drivers/intel/mipi_camera/ssdb.h b/src/drivers/intel/mipi_camera/ssdb.h
index 9845b162cd..68f234058c 100644
--- a/src/drivers/intel/mipi_camera/ssdb.h
+++ b/src/drivers/intel/mipi_camera/ssdb.h
@@ -47,17 +47,12 @@ struct intel_ssdb {
 	uint8_t version;			/* Current version */
 	uint8_t sensor_card_sku;		/* CRD Board type */
 	guid_t csi2_data_stream_interface;	/* CSI2 data stream GUID */
-	uint16_t bdf_value;			/* Bus number of the host
-						controller */
-	uint32_t dphy_link_en_fuses;		/* Host controller's fuses
-						information used to verify if
-						link is fused out or not */
-	uint32_t lanes_clock_division;		/* Lanes/clock divisions per
-						sensor */
-	uint8_t link_used;			/* Link used by this sensor
-						stream */
-	uint8_t lanes_used;			/* Number of lanes connected for
-						the sensor */
+	uint16_t bdf_value;			/* Bus number of the host controller */
+	uint32_t dphy_link_en_fuses;		/* Host controller's fuses information used to
+						   verify if link is fused out or not */
+	uint32_t lanes_clock_division;		/* Lanes/clock divisions per sensor */
+	uint8_t link_used;			/* Link used by this sensor stream */
+	uint8_t lanes_used;			/* Number of lanes connected for the sensor */
 	uint32_t csi_rx_dly_cnt_termen_clane;	/* MIPI timing information */
 	uint32_t csi_rx_dly_cnt_settle_clane;	/* MIPI timing information */
 	uint32_t csi_rx_dly_cnt_termen_dlane0;	/* MIPI timing information */
@@ -68,27 +63,19 @@ struct intel_ssdb {
 	uint32_t csi_rx_dly_cnt_settle_dlane2;	/* MIPI timing information */
 	uint32_t csi_rx_dly_cnt_termen_dlane3;	/* MIPI timing information */
 	uint32_t csi_rx_dly_cnt_settle_dlane3;	/* MIPI timing information */
-	uint32_t max_lane_speed;		/* Maximum lane speed for
-						the sensor */
-	uint8_t sensor_cal_file_idx;		/* Legacy field for sensor
-						calibration file index */
-	uint8_t sensor_cal_file_idx_mbz[3];	/* Legacy field for sensor
-						calibration file index */
-	uint8_t rom_type;			/* NVM type of the camera
-						module */
-	uint8_t vcm_type;			/* VCM type of the camera
-						module */
+	uint32_t max_lane_speed;		/* Maximum lane speed for the sensor */
+	uint8_t sensor_cal_file_idx;		/* Legacy field for sensor calibration file index */
+	uint8_t sensor_cal_file_idx_mbz[3];	/* Legacy field for sensor calibration file index */
+	uint8_t rom_type;			/* NVM type of the camera module */
+	uint8_t vcm_type;			/* VCM type of the camera module */
 	uint8_t platform;			/* Platform information */
 	uint8_t platform_sub;			/* Platform sub-categories */
-	uint8_t flash_support;			/* Enable/disable flash
-						support */
+	uint8_t flash_support;			/* Enable/disable flash support */
 	uint8_t privacy_led;			/* Privacy LED support */
 	uint8_t degree;				/* Camera Orientation */
-	uint8_t mipi_define;			/* MIPI info defined in ACPI or
-						sensor driver */
+	uint8_t mipi_define;			/* MIPI info defined in ACPI or sensor driver */
 	uint32_t mclk_speed;			/* Clock info for sensor */
-	uint8_t control_logic_id;		/* PMIC device node used for
-						the camera sensor */
+	uint8_t control_logic_id;		/* PMIC device node used for the camera sensor */
 	uint8_t mipi_data_format;		/* MIPI data format */
 	uint8_t silicon_version;		/* Silicon version */
 	uint8_t customer_id;			/* Customer ID */

From 0361e1a865bc5029562f1344dfc7b2d6e0879aa8 Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Sun, 9 Nov 2025 18:20:44 -0600
Subject: [PATCH 2649/3886] drivers/intel/mipi_camera: Verify SSDB struct size
 at build time

Add a static assert ensuring `struct ssdb` stays 0x6C bytes, matching
the sensor descriptor in ACPI. This guards future edits from drifting
away from the documented layout without changing runtime behavior.

Change-Id: I2b4dfb86494d13525cbc6e6de4573ceb36f0b482
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90183
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/drivers/intel/mipi_camera/ssdb.h | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/src/drivers/intel/mipi_camera/ssdb.h b/src/drivers/intel/mipi_camera/ssdb.h
index 68f234058c..318fb2e8c5 100644
--- a/src/drivers/intel/mipi_camera/ssdb.h
+++ b/src/drivers/intel/mipi_camera/ssdb.h
@@ -6,6 +6,8 @@
 #include <stdint.h>
 #include <uuid.h>
 
+#define SSDB_SIZE 108
+
 enum camera_device_type {
 	DEV_TYPE_SENSOR = 0,
 	DEV_TYPE_VCM,
@@ -83,5 +85,7 @@ struct intel_ssdb {
 	uint8_t reserved[13];			/* Pads SSDB out so the binary blob in ACPI is
 						   the same size as seen on other firmwares.*/
 } __packed;
+_Static_assert(sizeof(struct intel_ssdb) == SSDB_SIZE,
+		"SSDB structure size must match SSDB_SIZE");
 
 #endif

From c91ea7c5824a43cc41f8baed91196a5dd919f53f Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Sun, 9 Nov 2025 18:15:11 -0600
Subject: [PATCH 2650/3886] drivers/intel/mipi_camera: Flesh out SSDB platform
 enum

Rename `intel_camera_platform_type` to `platform_type` and populate it
using the available values from the Intel Camera DDK available on
Windows Update and slimbootloader.

Change-Id: I7c40e29dbf71caf7b655e8f2e5b4be7cc6970194
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90184
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/drivers/intel/mipi_camera/camera.c |  2 +-
 src/drivers/intel/mipi_camera/ssdb.h   | 30 ++++++++++++++++++--------
 2 files changed, 22 insertions(+), 10 deletions(-)

diff --git a/src/drivers/intel/mipi_camera/camera.c b/src/drivers/intel/mipi_camera/camera.c
index 4268646de8..24a424dba5 100644
--- a/src/drivers/intel/mipi_camera/camera.c
+++ b/src/drivers/intel/mipi_camera/camera.c
@@ -297,7 +297,7 @@ static void camera_fill_ssdb_defaults(struct drivers_intel_mipi_camera_config *c
 		config->ssdb.bdf_value = PCI_DEVFN(CIO2_PCI_DEV, CIO2_PCI_FN);
 
 	if (!config->ssdb.platform)
-		config->ssdb.platform = PLATFORM_SKC;
+		config->ssdb.platform = PLAT_SKC;
 
 	if (!config->ssdb.flash_support)
 		config->ssdb.flash_support = FLASH_DISABLE;
diff --git a/src/drivers/intel/mipi_camera/ssdb.h b/src/drivers/intel/mipi_camera/ssdb.h
index 318fb2e8c5..f7c7280623 100644
--- a/src/drivers/intel/mipi_camera/ssdb.h
+++ b/src/drivers/intel/mipi_camera/ssdb.h
@@ -14,15 +14,27 @@ enum camera_device_type {
 	DEV_TYPE_ROM
 };
 
-enum intel_camera_platform_type {
-	PLATFORM_BXT = 8,
-	PLATFORM_SKC = 9,
-	PLATFORM_CNL = 10,
-	PLATFORM_TGL = 12,
-	PLATFORM_JSL = 14,
-	PLATFORM_ADL = 15,
-	PLATFORM_MTL = 16,
-	PLATFORM_LNL = 17
+enum platform_type {
+	PLAT_UNK,
+	PLAT_BYT,
+	PLAT_CHT,
+	PLAT_CHT1,
+	PLAT_CHT2,
+	PLAT_CHT_CR,
+	PLAT_CHT_COPOP,
+	PLAT_BSW,
+	PLAT_BXT,
+	PLAT_SKC,
+	PLAT_CNL,
+	PLAT_LKF,
+	PLAT_TGL,
+	PLAT_TGL_H,
+	PLAT_JSL,
+	PLAT_ADL,
+	PLAT_MTL,
+	PLAT_LNL,
+	PLAT_PTL,
+	PLAT_NVL,
 };
 
 enum intel_camera_flash_type {

From 99cb6415ba27d3afdae7175f0f1334d382706c5f Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Sun, 9 Nov 2025 18:36:22 -0600
Subject: [PATCH 2651/3886] drivers/intel/mipi_camera: Rename flash enum to
 match SSDB field

Retitle the SSDB flash-support enum to `flash_support`, aligning its
name with the field in the struct and the spec. Also keep the existing
values and clarify the default case comment.

Change-Id: I49d825cb44d7f8784350e29e8b2b5a0772549f56
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90185
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/drivers/intel/mipi_camera/ssdb.h | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/src/drivers/intel/mipi_camera/ssdb.h b/src/drivers/intel/mipi_camera/ssdb.h
index f7c7280623..3cb4f120e5 100644
--- a/src/drivers/intel/mipi_camera/ssdb.h
+++ b/src/drivers/intel/mipi_camera/ssdb.h
@@ -37,8 +37,9 @@ enum platform_type {
 	PLAT_NVL,
 };
 
-enum intel_camera_flash_type {
-	FLASH_DEFAULT = 0,
+
+enum flash_support {
+	FLASH_DEFAULT = 0,	/* default is driver defined */
 	FLASH_DISABLE = 2,
 	FLASH_ENABLE = 3
 };

From f8d12a0bdb4623441f465fc1ec4e3282261b8dce Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Sun, 9 Nov 2025 18:37:09 -0600
Subject: [PATCH 2652/3886] drivers/intel/mipi_camera: Add SSDB platform
 subtype enum

Introduce `platform_subtype` constants for the SSDB `platform_sub`
field, matching the legacy FFD/CHT1/CHT2 values plus an unknown
default.

Change-Id: Ib705252b089d161a7addc372d05e5062307bfb21
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90186
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
---
 src/drivers/intel/mipi_camera/ssdb.h | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/src/drivers/intel/mipi_camera/ssdb.h b/src/drivers/intel/mipi_camera/ssdb.h
index 3cb4f120e5..3cd9e2de6a 100644
--- a/src/drivers/intel/mipi_camera/ssdb.h
+++ b/src/drivers/intel/mipi_camera/ssdb.h
@@ -37,6 +37,12 @@ enum platform_type {
 	PLAT_NVL,
 };
 
+enum platform_subtype {
+	PLAT_SUB_UNKNOWN,
+	PLAT_SUB_FFD,
+	PLAT_SUB_CHT1,
+	PLAT_SUB_CHT2,
+};
 
 enum flash_support {
 	FLASH_DEFAULT = 0,	/* default is driver defined */

From aa18a6fe8d5fe3b62d0e496c84d203c0c9de1c3d Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Sun, 9 Nov 2025 18:15:59 -0600
Subject: [PATCH 2653/3886] drivers/intel/mipi_camera: Codify SSDB field enums

Introduce enums covering the SSDB ROM/VCM types, orientation, control
logic, camera position, voltage rails, PHY config, MCLK source, SKU
vendor, and SKU card type fields, plus a packed helper for the SKU
bitfield. This replaces magic values with named constants ahead of
further SSDB work without changing behaviour.

Change-Id: Iacc1a844528e2427c9f4ca8fcebe338fb6c1bac4
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90187
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/drivers/intel/mipi_camera/ssdb.h | 92 ++++++++++++++++++++++++++++
 1 file changed, 92 insertions(+)

diff --git a/src/drivers/intel/mipi_camera/ssdb.h b/src/drivers/intel/mipi_camera/ssdb.h
index 3cd9e2de6a..e02b705f76 100644
--- a/src/drivers/intel/mipi_camera/ssdb.h
+++ b/src/drivers/intel/mipi_camera/ssdb.h
@@ -64,6 +64,98 @@ enum intel_camera_mipi_info {
 #define CLK_FREQ_24MHZ		24000000
 #define CLK_FREQ_20MHZ		20000000
 
+enum rom_type {
+	ROM_NONE,
+	ROM_OTP,
+	ROM_EEPROM_16K_64,
+	ROM_EEPROM_16K_16,
+	ROM_OTP_ACPI,
+	ROM_ACPI,
+	ROM_EEPROM_BRCA016GWZ,
+	ROM_EEPROM_24AA32,
+	ROM_EEPROM_CAT24C08,
+	ROM_EEPROM_M24C64,
+	ROM_EFLASH_DW9806B,
+	ROM_EEPROM_CAT24C16 = 16,
+	ROM_EEPROM_CAT24C64,
+	ROM_EEPROM_24AA16,
+};
+
+enum vcm_type {
+	VCM_NONE,
+	VCM_AD5823,
+	VCM_DW9714,
+	VCM_AD5816,
+	VCM_DW9719,
+	VCM_DW9718,
+	VCM_DW9806B,
+	VCM_WV517S,
+	VCM_LC898122XA,
+	VCM_LC898212AXB,
+	VCM_AK7371 = 15,
+	VCM_BU64297GWZ,
+	VCM_DW9800,
+	VCM_DW9808,
+	VCM_LC898217,
+};
+
+enum orientation {
+	DEGREE_0,
+	DEGREE_180,
+};
+
+enum control_logic_id {
+	PMIC_NODE_0,
+	PMIC_NODE_1,
+	PMIC_NODE_2,
+	PMIC_NODE_3,
+	PMIC_NODE_4,
+	PMIC_NODE_5,
+};
+
+enum cam_position {
+	CAM_POS_CRD_G2_LEFT,		/* Left position on CRD-G2 card (one PMIC controls two sensors) */
+	CAM_POS_CRD_G2_RIGHT,		/* Right position on CRD-G2 card (one PMIC controls two sensors) */
+	CAM_POS_CRD_G3_SHARED_RAIL,	/* Shared power rail sensor on CRD-G3 card */
+};
+
+enum voltage_rail {
+	VOLTAGE_THREE_RAILS = 0,	/* Sensor requires 3 voltage rails (typically Core, Analog, IO) */
+	VOLTAGE_TWO_RAILS = 1,		/* Sensor requires 2 voltage rails */
+};
+
+enum phy_config {
+	PHY_DPHY,
+	PHY_CPHY,
+};
+
+enum ext_mclk_source {
+	MCLK_INTERNAL,
+	MCLK_EXTERNAL,
+};
+
+enum sku_vendor {
+	VENDOR_SEMCO,
+	VENDOR_LITEON,
+};
+
+enum sku_card_type {
+	SKU_DEFAULT,
+	SKU_PTC,
+	SKU_CRD_D,
+	SKU_CRD_G,
+	SKU_KILSHON_PPV,
+	SKU_CRD_G2,
+	SKU_IMX135_CRD_D,
+	SKU_CRG_VALUE,
+	SKU_CRD_G3 = 9,
+};
+
+struct sensor_sku_info {
+	enum sku_vendor vendor : 4;
+	enum sku_card_type card_type : 4;
+} __packed;
+
 struct intel_ssdb {
 	uint8_t version;			/* Current version */
 	uint8_t sensor_card_sku;		/* CRD Board type */

From 423fbcd06b5dd9db2571d64da908d3e87e61c8e8 Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Sun, 9 Nov 2025 18:17:28 -0600
Subject: [PATCH 2654/3886] drivers/intel/mipi_camera: Adopt SSDB sensor SKU
 bitfield
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Switch the `sensor_card_sku` field in `struct intel_ssdb` from a raw
byte to the new `sensor_sku_info` bitfield wrapper so callers can access
the vendor/card type flags symbolically. Field size stays the same, so
layout and behavior are unchanged.

Change-Id: I85ecbbec1a749c07e4d83d953d47d76854447cb1
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90188
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
---
 src/drivers/intel/mipi_camera/ssdb.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/drivers/intel/mipi_camera/ssdb.h b/src/drivers/intel/mipi_camera/ssdb.h
index e02b705f76..9ef68dec66 100644
--- a/src/drivers/intel/mipi_camera/ssdb.h
+++ b/src/drivers/intel/mipi_camera/ssdb.h
@@ -158,7 +158,7 @@ struct sensor_sku_info {
 
 struct intel_ssdb {
 	uint8_t version;			/* Current version */
-	uint8_t sensor_card_sku;		/* CRD Board type */
+	struct sensor_sku_info sensor_card_sku;	/* CRD Board type */
 	guid_t csi2_data_stream_interface;	/* CSI2 data stream GUID */
 	uint16_t bdf_value;			/* Bus number of the host controller */
 	uint32_t dphy_link_en_fuses;		/* Host controller's fuses information used to

From c6ed8c91fbb813cc8b0187e3e076ad3358470224 Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Sun, 9 Nov 2025 18:18:21 -0600
Subject: [PATCH 2655/3886] drivers/intel/mipi_camera: Document more SSDB
 fields
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Add comments for the tail of `struct intel_ssdb`, naming the camera
position, voltage rail, PPR, flash, PHY, lane, and external MCLK fields
instead of treating them as an opaque reserved block. Keeps the struct
aligned with the ACPI blob while making each byte’s meaning explicit.

Change-Id: Id9ae2bf77e901ef0f88b6f51985b59d41c5529d9
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90189
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
---
 src/drivers/intel/mipi_camera/ssdb.h | 15 ++++++++++++---
 1 file changed, 12 insertions(+), 3 deletions(-)

diff --git a/src/drivers/intel/mipi_camera/ssdb.h b/src/drivers/intel/mipi_camera/ssdb.h
index 9ef68dec66..e3912ca4e4 100644
--- a/src/drivers/intel/mipi_camera/ssdb.h
+++ b/src/drivers/intel/mipi_camera/ssdb.h
@@ -192,9 +192,18 @@ struct intel_ssdb {
 	uint8_t mipi_data_format;		/* MIPI data format */
 	uint8_t silicon_version;		/* Silicon version */
 	uint8_t customer_id;			/* Customer ID */
-	uint8_t mclk_port;
-	uint8_t reserved[13];			/* Pads SSDB out so the binary blob in ACPI is
-						   the same size as seen on other firmwares.*/
+	uint8_t mclk_port;			/* MCLK port */
+	uint8_t camera_position;		/* Physical position on camera card and PMIC
+						   assignment. See enum cam_position */
+	uint8_t voltage_rail;			/* Number of voltage rails required by sensor */
+	uint8_t ppr_value;			/* Peak Power Rating value for sensor power mgmt */
+	uint8_t ppr_unit;			/* PPR unit multiplier */
+	uint8_t flash_id;			/* Flash ID: 0: default, 1: flash support */
+	uint8_t phy_config;			/* PHY config: 0: DPHY, 1: CPHY */
+	uint8_t lane_config;			/* 0: 1 lane, 1: 2 lanes,
+						   2: 3 lanes, 3: 4 lanes */
+	uint8_t use_ext_mclk_source;		/* 0: internal, 1: external */
+	uint8_t reserved[5];			/* Padding to match SSDB_SIZE */
 } __packed;
 _Static_assert(sizeof(struct intel_ssdb) == SSDB_SIZE,
 		"SSDB structure size must match SSDB_SIZE");

From 866b79c9fe303db2e67d84bb85159b02df58bc05 Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Sun, 23 Nov 2025 16:57:31 -0800
Subject: [PATCH 2656/3886] drivers/intel/mipi_camera: Always generate PLD for
 camera sensors

Remove the use_pld and disable_pld_defaults flags and always generate
the Physical Location Descriptor (PLD) for camera sensor devices. PLD
is required for proper camera enumeration and identification in modern
ACPI implementations, so making it optional was incorrect.

Changes:
- Remove use_pld field: PLD generation is now always enabled
- Remove disable_pld_defaults field: PLD defaults are always applied
- Always call apply_pld_defaults() and acpigen_write_pld()

TEST=tested with rest of patch train

Change-Id: Ifd408f32a4feaf9728913dd150d1cb3e7b1c3c60
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90193
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
---
 src/drivers/intel/mipi_camera/camera.c | 12 ++++--------
 src/drivers/intel/mipi_camera/chip.h   |  3 +--
 2 files changed, 5 insertions(+), 10 deletions(-)

diff --git a/src/drivers/intel/mipi_camera/camera.c b/src/drivers/intel/mipi_camera/camera.c
index 24a424dba5..1f347e7d88 100644
--- a/src/drivers/intel/mipi_camera/camera.c
+++ b/src/drivers/intel/mipi_camera/camera.c
@@ -169,15 +169,14 @@ static void apply_pld_defaults(struct drivers_intel_mipi_camera_config *config)
 
 	/*
 	 * PLD_PANEL_TOP has a value of zero, so the following will change any instance of
-	 * PLD_PANEL_TOP to PLD_PANEL_FRONT unless disable_pld_defaults is set.
+	 * PLD_PANEL_TOP to PLD_PANEL_FRONT.
 	 */
 	if (!config->pld.panel)
 		config->pld.panel = PLD_PANEL_FRONT;
 
 	/*
 	 * PLD_HORIZONTAL_POSITION_LEFT has a value of zero, so the following will change any
-	 * instance of that value to PLD_HORIZONTAL_POSITION_CENTER unless disable_pld_defaults
-	 * is set.
+	 * instance of that value to PLD_HORIZONTAL_POSITION_CENTER.
 	 */
 	if (!config->pld.horizontal_position)
 		config->pld.horizontal_position = PLD_HORIZONTAL_POSITION_CENTER;
@@ -193,12 +192,9 @@ static void camera_generate_pld(const struct device *dev)
 {
 	struct drivers_intel_mipi_camera_config *config = dev->chip_info;
 
-	if (config->use_pld) {
-		if (!config->disable_pld_defaults)
-			apply_pld_defaults(config);
+	apply_pld_defaults(config);
 
-		acpigen_write_pld(&config->pld);
-	}
+	acpigen_write_pld(&config->pld);
 }
 
 static uint32_t address_for_dev_type(const struct device *dev, uint8_t dev_type)
diff --git a/src/drivers/intel/mipi_camera/chip.h b/src/drivers/intel/mipi_camera/chip.h
index 84b7d0431e..85d3ba7188 100644
--- a/src/drivers/intel/mipi_camera/chip.h
+++ b/src/drivers/intel/mipi_camera/chip.h
@@ -150,8 +150,7 @@ struct drivers_intel_mipi_camera_config {
 	const char *sensor_name;	/* default "UNKNOWN" */
 	const char *remote_name;	/* default "\_SB.PCI0.CIO2" */
 	const char *vcm_name;		/* defaults to |vcm_address| device */
-	bool use_pld;
-	bool disable_pld_defaults;
+
 	struct acpi_pld pld;
 	uint16_t rom_address;		/* I2C to use if ssdb.rom_type != 0 */
 	uint16_t vcm_address;		/* I2C to use if ssdb.vcm_type != 0 */

From c75236d436c2450fc4a751340c2332dd84b6fc1f Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Mon, 24 Nov 2025 11:55:04 -0600
Subject: [PATCH 2657/3886] drivers/intel/mipi_camera: Set additional SSDB
 defaults

Set SSDB version and card type default values, as both fields
are required by both Linux and Windows MIPI camera drivers.

TEST=tested with rest of patch train

Change-Id: Ia43bc61caef427a86883a6295af1606eac00229f
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90194
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
---
 src/drivers/intel/mipi_camera/camera.c | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/src/drivers/intel/mipi_camera/camera.c b/src/drivers/intel/mipi_camera/camera.c
index 1f347e7d88..87fc644c11 100644
--- a/src/drivers/intel/mipi_camera/camera.c
+++ b/src/drivers/intel/mipi_camera/camera.c
@@ -287,6 +287,11 @@ static void camera_fill_ssdb_defaults(struct drivers_intel_mipi_camera_config *c
 	if (config->disable_ssdb_defaults)
 		return;
 
+	config->ssdb.version = 1;
+
+	if (!config->ssdb.sensor_card_sku.card_type)
+		config->ssdb.sensor_card_sku.card_type = SKU_CRD_D;
+
 	guidcpy(&config->ssdb.csi2_data_stream_interface, &CSI2_DATA_STREAM_INTERFACE_GUID);
 
 	if (!config->ssdb.bdf_value)

From 4c025191c7dfc1250cdbf8b6a9724bfef5c1c9e7 Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Mon, 24 Nov 2025 12:04:58 -0600
Subject: [PATCH 2658/3886] drivers/intel/mipi_camera: Remove
 disable_ssdb_defaults option

Remove the (unused) disable_ssdb_defaults field and its usage. SSDB
defaults should always be applied to ensure proper camera sensor
configuration. This simplifies the code and ensures consistent behavior
across all camera sensor configurations.

TEST=tested with rest of patch train

Change-Id: I3bc00cdd28ace925b44712a17dec07f7f2b8c97a
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90195
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
---
 src/drivers/intel/mipi_camera/camera.c | 3 ---
 src/drivers/intel/mipi_camera/chip.h   | 1 -
 2 files changed, 4 deletions(-)

diff --git a/src/drivers/intel/mipi_camera/camera.c b/src/drivers/intel/mipi_camera/camera.c
index 87fc644c11..0a0439a042 100644
--- a/src/drivers/intel/mipi_camera/camera.c
+++ b/src/drivers/intel/mipi_camera/camera.c
@@ -284,9 +284,6 @@ static void camera_fill_ssdb_defaults(struct drivers_intel_mipi_camera_config *c
 	struct device *cio2 = pcidev_on_root(CIO2_PCI_DEV, CIO2_PCI_FN);
 	struct drivers_intel_mipi_camera_config *cio2_config;
 
-	if (config->disable_ssdb_defaults)
-		return;
-
 	config->ssdb.version = 1;
 
 	if (!config->ssdb.sensor_card_sku.card_type)
diff --git a/src/drivers/intel/mipi_camera/chip.h b/src/drivers/intel/mipi_camera/chip.h
index 85d3ba7188..e6274d6dbc 100644
--- a/src/drivers/intel/mipi_camera/chip.h
+++ b/src/drivers/intel/mipi_camera/chip.h
@@ -143,7 +143,6 @@ struct drivers_intel_mipi_camera_config {
 	uint32_t cio2_prt[MAX_PORT_ENTRIES];
 
 	/* Settings specific to camera sensor */
-	bool disable_ssdb_defaults;
 
 	uint8_t num_freq_entries;	/* # of elements in link_freq */
 	uint32_t link_freq[MAX_LINK_FREQ_ENTRIES];

From 30b43839448750f4a118cbe628443d25985d3f56 Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Mon, 24 Nov 2025 14:06:36 -0600
Subject: [PATCH 2659/3886] mb/{google,intel}: Set SSDB platform field for MIPI
 camera sensors

The SSDB platform field was unset on many boards, causing the driver
to default to PLAT_SKC (Skylake). This field is required for proper
camera sensor initialization and is validated by the driver.

Set the correct platform enum value based on the SoC.

TEST=tested with rest of patch train

Change-Id: I34e0aba0ba34dabcf25287ff04bc4251135ca09e
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90196
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
---
 src/mainboard/google/brya/variants/anraggar/overridetree.cb    | 1 +
 src/mainboard/google/brya/variants/brya0/overridetree.cb       | 3 +++
 src/mainboard/google/brya/variants/craask/overridetree.cb      | 2 ++
 src/mainboard/google/brya/variants/kano/overridetree.cb        | 2 ++
 src/mainboard/google/brya/variants/meliks/overridetree.cb      | 1 +
 src/mainboard/google/brya/variants/nivviks/overridetree.cb     | 1 +
 src/mainboard/google/brya/variants/pirrha/overridetree.cb      | 1 +
 src/mainboard/google/brya/variants/pujjolo/overridetree.cb     | 1 +
 src/mainboard/google/brya/variants/redrix/overridetree.cb      | 2 ++
 src/mainboard/google/brya/variants/redrix4es/overridetree.cb   | 2 ++
 src/mainboard/google/brya/variants/riven/overridetree.cb       | 2 ++
 src/mainboard/google/brya/variants/skolas/overridetree.cb      | 3 +++
 src/mainboard/google/brya/variants/skolas4es/overridetree.cb   | 2 ++
 src/mainboard/google/brya/variants/teliks/overridetree.cb      | 1 +
 src/mainboard/google/brya/variants/telith/overridetree.cb      | 1 +
 src/mainboard/google/brya/variants/vell/overridetree.cb        | 1 +
 src/mainboard/google/brya/variants/xivu/overridetree.cb        | 1 +
 src/mainboard/google/brya/variants/yaviks/overridetree.cb      | 1 +
 src/mainboard/google/brya/variants/yavilla/overridetree.cb     | 1 +
 src/mainboard/google/brya/variants/zydron/overridetree.cb      | 2 ++
 src/mainboard/google/dedede/variants/bugzzy/overridetree.cb    | 1 +
 src/mainboard/google/dedede/variants/drawcia/overridetree.cb   | 1 +
 src/mainboard/google/dedede/variants/haboki/overridetree.cb    | 1 +
 src/mainboard/google/dedede/variants/lalala/overridetree.cb    | 1 +
 src/mainboard/google/dedede/variants/magolor/overridetree.cb   | 2 ++
 src/mainboard/google/dedede/variants/storo/overridetree.cb     | 1 +
 src/mainboard/google/dedede/variants/waddledoo/overridetree.cb | 1 +
 src/mainboard/google/fatcat/variants/fatcat/overridetree.cb    | 2 ++
 src/mainboard/google/rex/variants/kanix/overridetree.cb        | 1 +
 src/mainboard/google/rex/variants/karis/overridetree.cb        | 1 +
 src/mainboard/google/rex/variants/rex0/overridetree.cb         | 2 ++
 src/mainboard/google/rex/variants/screebo/overridetree.cb      | 1 +
 src/mainboard/intel/adlrvp/devicetree.cb                       | 2 ++
 src/mainboard/intel/adlrvp/devicetree_m.cb                     | 2 ++
 src/mainboard/intel/adlrvp/devicetree_n.cb                     | 2 ++
 .../intel/jasperlake_rvp/variants/jslrvp/devicetree.cb         | 3 +++
 .../intel/mtlrvp/variants/baseboard/mtlrvp_p/devicetree.cb     | 2 ++
 src/mainboard/intel/ptlrvp/variants/ptlrvp/overridetree.cb     | 2 ++
 .../intel/ptlrvp/variants/ptlrvp_chromeec/overridetree.cb      | 2 ++
 39 files changed, 61 insertions(+)

diff --git a/src/mainboard/google/brya/variants/anraggar/overridetree.cb b/src/mainboard/google/brya/variants/anraggar/overridetree.cb
index d102021488..f6d75396c0 100644
--- a/src/mainboard/google/brya/variants/anraggar/overridetree.cb
+++ b/src/mainboard/google/brya/variants/anraggar/overridetree.cb
@@ -270,6 +270,7 @@ chip soc/intel/alderlake
 				register "device_type" = "INTEL_ACPI_CAMERA_SENSOR"
 
 				register "ssdb.lanes_used" = "4"
+				register "ssdb.platform" = "PLAT_ADL"
 				register "ssdb.vcm_type" = "0x0C"
 				register "vcm_name" = ""VCM0""
 				register "num_freq_entries" = "1"
diff --git a/src/mainboard/google/brya/variants/brya0/overridetree.cb b/src/mainboard/google/brya/variants/brya0/overridetree.cb
index 24612c10de..189d015478 100644
--- a/src/mainboard/google/brya/variants/brya0/overridetree.cb
+++ b/src/mainboard/google/brya/variants/brya0/overridetree.cb
@@ -544,6 +544,7 @@ chip soc/intel/alderlake
 
 				register "ssdb.lanes_used" = "4"
 				register "ssdb.link_used" = "0"
+				register "ssdb.platform" = "PLAT_ADL"
 				register "ssdb.vcm_type" = "0x0C"
 				register "vcm_name" = ""VCM0""
 				register "num_freq_entries" = "2"
@@ -649,6 +650,7 @@ chip soc/intel/alderlake
 
 				register "ssdb.lanes_used" = "4"
 				register "ssdb.link_used" = "0"
+				register "ssdb.platform" = "PLAT_ADL"
 				register "ssdb.vcm_type" = "0x0C"
 				register "vcm_name" = ""VCM0""
 				register "num_freq_entries" = "2"
@@ -859,6 +861,7 @@ chip soc/intel/alderlake
 
 				register "ssdb.lanes_used" = "2"
 				register "ssdb.link_used" = "1"
+				register "ssdb.platform" = "PLAT_ADL"
 				register "num_freq_entries" = "2"
 				register "link_freq[0]" = "384 * MHz" # 384 MHz
 				register "link_freq[1]" = "96 * MHz" # 96 MHz
diff --git a/src/mainboard/google/brya/variants/craask/overridetree.cb b/src/mainboard/google/brya/variants/craask/overridetree.cb
index 7014e6a77f..1a8d5b1d17 100644
--- a/src/mainboard/google/brya/variants/craask/overridetree.cb
+++ b/src/mainboard/google/brya/variants/craask/overridetree.cb
@@ -481,6 +481,7 @@ chip soc/intel/alderlake
 
 				register "ssdb.lanes_used" = "2"
 				register "ssdb.link_used" = "1"
+				register "ssdb.platform" = "PLAT_ADL"
 				register "ssdb.vcm_type" = "0x0C"
 				register "vcm_name" = ""VCM0""
 				register "num_freq_entries" = "1"
@@ -528,6 +529,7 @@ chip soc/intel/alderlake
 
 				register "ssdb.lanes_used" = "2"
 				register "ssdb.link_used" = "1"
+				register "ssdb.platform" = "PLAT_ADL"
 				register "ssdb.vcm_type" = "0x0C"
 				register "vcm_name" = ""VCM0""
 				register "num_freq_entries" = "2"
diff --git a/src/mainboard/google/brya/variants/kano/overridetree.cb b/src/mainboard/google/brya/variants/kano/overridetree.cb
index c832f96301..d635ae788b 100644
--- a/src/mainboard/google/brya/variants/kano/overridetree.cb
+++ b/src/mainboard/google/brya/variants/kano/overridetree.cb
@@ -327,6 +327,7 @@ chip soc/intel/alderlake
 
 				register "ssdb.lanes_used" = "2"
 				register "ssdb.link_used" = "1"
+				register "ssdb.platform" = "PLAT_ADL"
 				register "num_freq_entries" = "1"
 				register "link_freq[0]" = "360 * MHz"
 				register "remote_name" = ""IPU0""
@@ -367,6 +368,7 @@ chip soc/intel/alderlake
 
 				register "ssdb.lanes_used" = "2"
 				register "ssdb.link_used" = "1"
+				register "ssdb.platform" = "PLAT_ADL"
 				register "num_freq_entries" = "1"
 				register "link_freq[0]" = "437 * MHz" # 437 MHz
 				register "remote_name" = ""IPU0""
diff --git a/src/mainboard/google/brya/variants/meliks/overridetree.cb b/src/mainboard/google/brya/variants/meliks/overridetree.cb
index 057bc74309..743dd2180c 100644
--- a/src/mainboard/google/brya/variants/meliks/overridetree.cb
+++ b/src/mainboard/google/brya/variants/meliks/overridetree.cb
@@ -265,6 +265,7 @@ chip soc/intel/alderlake
 
 				register "ssdb.lanes_used" = "4"
 				register "ssdb.link_used" = "1"
+				register "ssdb.platform" = "PLAT_ADL"
 				register "ssdb.vcm_type" = "0x0C"
 				register "vcm_name" = ""VCM0""
 				register "num_freq_entries" = "2"
diff --git a/src/mainboard/google/brya/variants/nivviks/overridetree.cb b/src/mainboard/google/brya/variants/nivviks/overridetree.cb
index 088459b6f4..fa7833d153 100644
--- a/src/mainboard/google/brya/variants/nivviks/overridetree.cb
+++ b/src/mainboard/google/brya/variants/nivviks/overridetree.cb
@@ -390,6 +390,7 @@ chip soc/intel/alderlake
 
 				register "ssdb.lanes_used" = "2"
 				register "ssdb.link_used" = "1"
+				register "ssdb.platform" = "PLAT_ADL"
 				register "ssdb.vcm_type" = "0x0C"
 				register "vcm_name" = ""VCM0""
 				register "num_freq_entries" = "1"
diff --git a/src/mainboard/google/brya/variants/pirrha/overridetree.cb b/src/mainboard/google/brya/variants/pirrha/overridetree.cb
index 9050462390..68cfb6f7b2 100644
--- a/src/mainboard/google/brya/variants/pirrha/overridetree.cb
+++ b/src/mainboard/google/brya/variants/pirrha/overridetree.cb
@@ -304,6 +304,7 @@ chip soc/intel/alderlake
 
 				register "ssdb.lanes_used" = "4"
 				register "ssdb.link_used" = "1"
+				register "ssdb.platform" = "PLAT_ADL"
 				register "ssdb.vcm_type" = "0x0C"
 				register "vcm_name" = ""VCM0""
 				register "num_freq_entries" = "2"
diff --git a/src/mainboard/google/brya/variants/pujjolo/overridetree.cb b/src/mainboard/google/brya/variants/pujjolo/overridetree.cb
index 7fa77801b2..318453c454 100644
--- a/src/mainboard/google/brya/variants/pujjolo/overridetree.cb
+++ b/src/mainboard/google/brya/variants/pujjolo/overridetree.cb
@@ -394,6 +394,7 @@ chip soc/intel/alderlake
 
 				register "ssdb.lanes_used" = "4"
 				register "ssdb.link_used" = "1"
+				register "ssdb.platform" = "PLAT_ADL"
 				register "ssdb.vcm_type" = "0x0C"
 				register "vcm_name" = ""VCM0""
 				register "num_freq_entries" = "2"
diff --git a/src/mainboard/google/brya/variants/redrix/overridetree.cb b/src/mainboard/google/brya/variants/redrix/overridetree.cb
index 4b486977c8..16e228182a 100644
--- a/src/mainboard/google/brya/variants/redrix/overridetree.cb
+++ b/src/mainboard/google/brya/variants/redrix/overridetree.cb
@@ -421,6 +421,7 @@ chip soc/intel/alderlake
 
 				register "ssdb.lanes_used" = "2"
 				register "ssdb.link_used" = "1"
+				register "ssdb.platform" = "PLAT_ADL"
 				register "num_freq_entries" = "1"
 				register "link_freq[0]" = "DEFAULT_LINK_FREQ"
 				register "remote_name" = ""IPU0""
@@ -461,6 +462,7 @@ chip soc/intel/alderlake
 
 				register "ssdb.lanes_used" = "2"
 				register "ssdb.link_used" = "1"
+				register "ssdb.platform" = "PLAT_ADL"
 				register "num_freq_entries" = "1"
 				register "link_freq[0]" = "437000000"
 				register "remote_name" = ""IPU0""
diff --git a/src/mainboard/google/brya/variants/redrix4es/overridetree.cb b/src/mainboard/google/brya/variants/redrix4es/overridetree.cb
index 01574421bd..93638c9021 100644
--- a/src/mainboard/google/brya/variants/redrix4es/overridetree.cb
+++ b/src/mainboard/google/brya/variants/redrix4es/overridetree.cb
@@ -351,6 +351,7 @@ chip soc/intel/alderlake
 
 				register "ssdb.lanes_used" = "2"
 				register "ssdb.link_used" = "1"
+				register "ssdb.platform" = "PLAT_ADL"
 				register "num_freq_entries" = "1"
 				register "link_freq[0]" = "DEFAULT_LINK_FREQ"
 				register "remote_name" = ""IPU0""
@@ -394,6 +395,7 @@ chip soc/intel/alderlake
 
 				register "ssdb.lanes_used" = "2"
 				register "ssdb.link_used" = "1"
+				register "ssdb.platform" = "PLAT_ADL"
 				register "num_freq_entries" = "1"
 				register "link_freq[0]" = "437000000"
 				register "remote_name" = ""IPU0""
diff --git a/src/mainboard/google/brya/variants/riven/overridetree.cb b/src/mainboard/google/brya/variants/riven/overridetree.cb
index 7f92627145..077acb0962 100644
--- a/src/mainboard/google/brya/variants/riven/overridetree.cb
+++ b/src/mainboard/google/brya/variants/riven/overridetree.cb
@@ -346,6 +346,7 @@ chip soc/intel/alderlake
 
 				register "ssdb.lanes_used" = "2"
 				register "ssdb.link_used" = "1"
+				register "ssdb.platform" = "PLAT_ADL"
 				register "ssdb.vcm_type" = "0x0C"
 				register "vcm_name" = ""VCM0""
 				register "num_freq_entries" = "1"
@@ -393,6 +394,7 @@ chip soc/intel/alderlake
 
 				register "ssdb.lanes_used" = "2"
 				register "ssdb.link_used" = "1"
+				register "ssdb.platform" = "PLAT_ADL"
 				register "ssdb.vcm_type" = "0x0C"
 				register "vcm_name" = ""VCM0""
 				register "num_freq_entries" = "2"
diff --git a/src/mainboard/google/brya/variants/skolas/overridetree.cb b/src/mainboard/google/brya/variants/skolas/overridetree.cb
index dc3ef3d34f..e984904425 100644
--- a/src/mainboard/google/brya/variants/skolas/overridetree.cb
+++ b/src/mainboard/google/brya/variants/skolas/overridetree.cb
@@ -543,6 +543,7 @@ chip soc/intel/alderlake
 
 				register "ssdb.lanes_used" = "4"
 				register "ssdb.link_used" = "0"
+				register "ssdb.platform" = "PLAT_ADL"
 				register "ssdb.vcm_type" = "0x0C"
 				register "vcm_name" = ""VCM0""
 				register "num_freq_entries" = "2"
@@ -648,6 +649,7 @@ chip soc/intel/alderlake
 
 				register "ssdb.lanes_used" = "4"
 				register "ssdb.link_used" = "0"
+				register "ssdb.platform" = "PLAT_ADL"
 				register "ssdb.vcm_type" = "0x0C"
 				register "vcm_name" = ""VCM0""
 				register "num_freq_entries" = "2"
@@ -858,6 +860,7 @@ chip soc/intel/alderlake
 
 				register "ssdb.lanes_used" = "2"
 				register "ssdb.link_used" = "1"
+				register "ssdb.platform" = "PLAT_ADL"
 				register "num_freq_entries" = "2"
 				register "link_freq[0]" = "384 * MHz" # 384 MHz
 				register "link_freq[1]" = "96 * MHz" # 96 MHz
diff --git a/src/mainboard/google/brya/variants/skolas4es/overridetree.cb b/src/mainboard/google/brya/variants/skolas4es/overridetree.cb
index 22f846b54f..05156bf967 100644
--- a/src/mainboard/google/brya/variants/skolas4es/overridetree.cb
+++ b/src/mainboard/google/brya/variants/skolas4es/overridetree.cb
@@ -384,6 +384,7 @@ chip soc/intel/alderlake
 
 				register "ssdb.lanes_used" = "4"
 				register "ssdb.link_used" = "0"
+				register "ssdb.platform" = "PLAT_ADL"
 				register "ssdb.vcm_type" = "0x0C"
 				register "vcm_name" = ""VCM0""
 				register "num_freq_entries" = "2"
@@ -586,6 +587,7 @@ chip soc/intel/alderlake
 
 				register "ssdb.lanes_used" = "2"
 				register "ssdb.link_used" = "1"
+				register "ssdb.platform" = "PLAT_ADL"
 				register "num_freq_entries" = "2"
 				register "link_freq[0]" = "384 * MHz" # 384 MHz
 				register "link_freq[1]" = "96 * MHz" # 96 MHz
diff --git a/src/mainboard/google/brya/variants/teliks/overridetree.cb b/src/mainboard/google/brya/variants/teliks/overridetree.cb
index 2010866b0f..4ef2718e74 100644
--- a/src/mainboard/google/brya/variants/teliks/overridetree.cb
+++ b/src/mainboard/google/brya/variants/teliks/overridetree.cb
@@ -287,6 +287,7 @@ chip soc/intel/alderlake
 				register "device_type" = "INTEL_ACPI_CAMERA_SENSOR"
 
 				register "ssdb.lanes_used" = "4"
+				register "ssdb.platform" = "PLAT_ADL"
 				register "ssdb.vcm_type" = "0x0C"
 				register "vcm_name" = ""VCM0""
 				register "num_freq_entries" = "1"
diff --git a/src/mainboard/google/brya/variants/telith/overridetree.cb b/src/mainboard/google/brya/variants/telith/overridetree.cb
index 7c8706d8bf..ea4dbd2687 100644
--- a/src/mainboard/google/brya/variants/telith/overridetree.cb
+++ b/src/mainboard/google/brya/variants/telith/overridetree.cb
@@ -413,6 +413,7 @@ chip soc/intel/alderlake
 				register "device_type" = "INTEL_ACPI_CAMERA_SENSOR"
 
 				register "ssdb.lanes_used" = "4"
+				register "ssdb.platform" = "PLAT_ADL"
 				register "ssdb.vcm_type" = "0x0C"
 				register "vcm_name" = ""VCM0""
 				register "num_freq_entries" = "1"
diff --git a/src/mainboard/google/brya/variants/vell/overridetree.cb b/src/mainboard/google/brya/variants/vell/overridetree.cb
index 273fb0e3ab..87d9748189 100644
--- a/src/mainboard/google/brya/variants/vell/overridetree.cb
+++ b/src/mainboard/google/brya/variants/vell/overridetree.cb
@@ -346,6 +346,7 @@ chip soc/intel/alderlake
 
 				register "ssdb.lanes_used" = "4"
 				register "ssdb.link_used" = "1"
+				register "ssdb.platform" = "PLAT_ADL"
 				register "num_freq_entries" = "2"
 				register "link_freq[0]" = "360000000"
 				register "link_freq[1]" = "180000000"
diff --git a/src/mainboard/google/brya/variants/xivu/overridetree.cb b/src/mainboard/google/brya/variants/xivu/overridetree.cb
index da7405b204..dd0fdbaff1 100644
--- a/src/mainboard/google/brya/variants/xivu/overridetree.cb
+++ b/src/mainboard/google/brya/variants/xivu/overridetree.cb
@@ -254,6 +254,7 @@ chip soc/intel/alderlake
 
 				register "ssdb.lanes_used" = "4"
 				register "ssdb.link_used" = "1"
+				register "ssdb.platform" = "PLAT_ADL"
 				register "ssdb.vcm_type" = "0x0C"
 				register "vcm_name" = ""VCM0""
 				register "num_freq_entries" = "2"
diff --git a/src/mainboard/google/brya/variants/yaviks/overridetree.cb b/src/mainboard/google/brya/variants/yaviks/overridetree.cb
index d1b49489c9..87f39473a3 100644
--- a/src/mainboard/google/brya/variants/yaviks/overridetree.cb
+++ b/src/mainboard/google/brya/variants/yaviks/overridetree.cb
@@ -332,6 +332,7 @@ chip soc/intel/alderlake
 
 				register "ssdb.lanes_used" = "2"
 				register "ssdb.link_used" = "1"
+				register "ssdb.platform" = "PLAT_ADL"
 				register "ssdb.vcm_type" = "0x0C"
 				register "vcm_name" = ""VCM0""
 				register "num_freq_entries" = "2"
diff --git a/src/mainboard/google/brya/variants/yavilla/overridetree.cb b/src/mainboard/google/brya/variants/yavilla/overridetree.cb
index b57ff9abd6..8e5cb70848 100644
--- a/src/mainboard/google/brya/variants/yavilla/overridetree.cb
+++ b/src/mainboard/google/brya/variants/yavilla/overridetree.cb
@@ -367,6 +367,7 @@ chip soc/intel/alderlake
 
 				register "ssdb.lanes_used" = "4"
 				register "ssdb.link_used" = "1"
+				register "ssdb.platform" = "PLAT_ADL"
 				register "ssdb.vcm_type" = "0x0C"
 				register "vcm_name" = ""VCM0""
 				register "num_freq_entries" = "2"
diff --git a/src/mainboard/google/brya/variants/zydron/overridetree.cb b/src/mainboard/google/brya/variants/zydron/overridetree.cb
index a3c4f34f6c..67b32dad44 100644
--- a/src/mainboard/google/brya/variants/zydron/overridetree.cb
+++ b/src/mainboard/google/brya/variants/zydron/overridetree.cb
@@ -303,6 +303,7 @@ chip soc/intel/alderlake
 
 				register "ssdb.lanes_used" = "2"
 				register "ssdb.link_used" = "1"
+				register "ssdb.platform" = "PLAT_ADL"
 				register "num_freq_entries" = "1"
 				register "link_freq[0]" = "360 * MHz"
 				register "remote_name" = ""IPU0""
@@ -343,6 +344,7 @@ chip soc/intel/alderlake
 
 				register "ssdb.lanes_used" = "2"
 				register "ssdb.link_used" = "1"
+				register "ssdb.platform" = "PLAT_ADL"
 				register "num_freq_entries" = "1"
 				register "link_freq[0]" = "437 * MHz" # 437 MHz
 				register "remote_name" = ""IPU0""
diff --git a/src/mainboard/google/dedede/variants/bugzzy/overridetree.cb b/src/mainboard/google/dedede/variants/bugzzy/overridetree.cb
index 252096656d..08ba6eba0d 100644
--- a/src/mainboard/google/dedede/variants/bugzzy/overridetree.cb
+++ b/src/mainboard/google/dedede/variants/bugzzy/overridetree.cb
@@ -240,6 +240,7 @@ chip soc/intel/jasperlake
 
 				register "ssdb.lanes_used" = "4"
 				register "ssdb.link_used" = "1"
+				register "ssdb.platform" = "PLAT_JSL"
 				register "ssdb.vcm_type" = "0x0C"
 				register "vcm_name" = ""VCM0""
 				register "num_freq_entries" = "2"
diff --git a/src/mainboard/google/dedede/variants/drawcia/overridetree.cb b/src/mainboard/google/dedede/variants/drawcia/overridetree.cb
index 9173036c1f..c2673c6c8d 100644
--- a/src/mainboard/google/dedede/variants/drawcia/overridetree.cb
+++ b/src/mainboard/google/dedede/variants/drawcia/overridetree.cb
@@ -306,6 +306,7 @@ chip soc/intel/jasperlake
 
 				register "ssdb.lanes_used" = "4"
 				register "ssdb.link_used" = "1"
+				register "ssdb.platform" = "PLAT_JSL"
 				register "ssdb.vcm_type" = "0x0C"
 				register "vcm_name" = ""VCM0""
 				register "num_freq_entries" = "2"
diff --git a/src/mainboard/google/dedede/variants/haboki/overridetree.cb b/src/mainboard/google/dedede/variants/haboki/overridetree.cb
index 712544639f..97408a674a 100644
--- a/src/mainboard/google/dedede/variants/haboki/overridetree.cb
+++ b/src/mainboard/google/dedede/variants/haboki/overridetree.cb
@@ -215,6 +215,7 @@ chip soc/intel/jasperlake
 
 				register "ssdb.lanes_used" = "4"
 				register "ssdb.link_used" = "1"
+				register "ssdb.platform" = "PLAT_JSL"
 				register "ssdb.vcm_type" = "0x0C"
 				register "vcm_name" = ""VCM0""
 				register "num_freq_entries" = "2"
diff --git a/src/mainboard/google/dedede/variants/lalala/overridetree.cb b/src/mainboard/google/dedede/variants/lalala/overridetree.cb
index 00046d8af5..a421b8c5e9 100644
--- a/src/mainboard/google/dedede/variants/lalala/overridetree.cb
+++ b/src/mainboard/google/dedede/variants/lalala/overridetree.cb
@@ -213,6 +213,7 @@ chip soc/intel/jasperlake
 
 				register "ssdb.lanes_used" = "2"
 				register "ssdb.link_used" = "1"
+				register "ssdb.platform" = "PLAT_JSL"
 				register "ssdb.vcm_type" = "0x0C"
 				register "vcm_name" = ""VCM0""
 				register "num_freq_entries" = "1"
diff --git a/src/mainboard/google/dedede/variants/magolor/overridetree.cb b/src/mainboard/google/dedede/variants/magolor/overridetree.cb
index 75fa38f9f5..c74c0fae9b 100644
--- a/src/mainboard/google/dedede/variants/magolor/overridetree.cb
+++ b/src/mainboard/google/dedede/variants/magolor/overridetree.cb
@@ -347,6 +347,7 @@ chip soc/intel/jasperlake
 
 				register "ssdb.lanes_used" = "2"
 				register "ssdb.link_used" = "1"
+				register "ssdb.platform" = "PLAT_JSL"
 				register "ssdb.vcm_type" = "0x0C"
 				register "vcm_name" = ""VCM0""
 				register "num_freq_entries" = "1"
@@ -391,6 +392,7 @@ chip soc/intel/jasperlake
 
 				register "ssdb.lanes_used" = "2"
 				register "ssdb.link_used" = "1"
+				register "ssdb.platform" = "PLAT_JSL"
 				register "ssdb.vcm_type" = "0x0C"
 				register "vcm_name" = ""VCM0""
 				register "num_freq_entries" = "2"
diff --git a/src/mainboard/google/dedede/variants/storo/overridetree.cb b/src/mainboard/google/dedede/variants/storo/overridetree.cb
index e243adaa11..400ec2f17e 100644
--- a/src/mainboard/google/dedede/variants/storo/overridetree.cb
+++ b/src/mainboard/google/dedede/variants/storo/overridetree.cb
@@ -230,6 +230,7 @@ chip soc/intel/jasperlake
 
 				register "ssdb.lanes_used" = "4"
 				register "ssdb.link_used" = "1"
+				register "ssdb.platform" = "PLAT_JSL"
 				register "ssdb.vcm_type" = "0x0C"
 				register "vcm_name" = ""VCM0""
 				register "num_freq_entries" = "2"
diff --git a/src/mainboard/google/dedede/variants/waddledoo/overridetree.cb b/src/mainboard/google/dedede/variants/waddledoo/overridetree.cb
index de3d542a24..38daca4903 100644
--- a/src/mainboard/google/dedede/variants/waddledoo/overridetree.cb
+++ b/src/mainboard/google/dedede/variants/waddledoo/overridetree.cb
@@ -147,6 +147,7 @@ chip soc/intel/jasperlake
 
 				register "ssdb.lanes_used" = "4"
 				register "ssdb.link_used" = "1"
+				register "ssdb.platform" = "PLAT_JSL"
 				register "ssdb.vcm_type" = "0x0C"
 				register "vcm_name" = ""VCM0""
 				register "num_freq_entries" = "2"
diff --git a/src/mainboard/google/fatcat/variants/fatcat/overridetree.cb b/src/mainboard/google/fatcat/variants/fatcat/overridetree.cb
index f98fb46d53..1beff24ccf 100644
--- a/src/mainboard/google/fatcat/variants/fatcat/overridetree.cb
+++ b/src/mainboard/google/fatcat/variants/fatcat/overridetree.cb
@@ -662,6 +662,7 @@ chip soc/intel/pantherlake
 				register "vcm_name" = ""VCM1""
 
 				register "ssdb.lanes_used" = "4"
+				register "ssdb.platform" = "PLAT_PTL"
 				register "num_freq_entries" = "1"
 				register "link_freq[0]" = "560 * MHz" # 560 MHz
 				register "remote_name" = ""IPU0""
@@ -763,6 +764,7 @@ chip soc/intel/pantherlake
 				register "vcm_name" = ""VCM1""
 
 				register "ssdb.lanes_used" = "2"
+				register "ssdb.platform" = "PLAT_PTL"
 				register "num_freq_entries" = "1"
 				register "link_freq[0]" = "560 * MHz" # 560 MHz
 				register "remote_name" = ""IPU0""
diff --git a/src/mainboard/google/rex/variants/kanix/overridetree.cb b/src/mainboard/google/rex/variants/kanix/overridetree.cb
index 31fbf555a6..3b8f9b78af 100644
--- a/src/mainboard/google/rex/variants/kanix/overridetree.cb
+++ b/src/mainboard/google/rex/variants/kanix/overridetree.cb
@@ -510,6 +510,7 @@ chip soc/intel/meteorlake
 
 				register "ssdb.lanes_used" = "2"
 				register "ssdb.link_used" = "1"
+				register "ssdb.platform" = "PLAT_MTL"
 				register "num_freq_entries" = "1"
 				register "link_freq[0]" = "437 * MHz"
 				register "remote_name" = ""IPU0""
diff --git a/src/mainboard/google/rex/variants/karis/overridetree.cb b/src/mainboard/google/rex/variants/karis/overridetree.cb
index 2607ad776f..a637e0474f 100644
--- a/src/mainboard/google/rex/variants/karis/overridetree.cb
+++ b/src/mainboard/google/rex/variants/karis/overridetree.cb
@@ -461,6 +461,7 @@ chip soc/intel/meteorlake
 
 				register "ssdb.lanes_used" = "2"
 				register "ssdb.link_used" = "1"
+				register "ssdb.platform" = "PLAT_MTL"
 				register "num_freq_entries" = "1"
 				register "link_freq[0]" = "437 * MHz"
 				register "remote_name" = ""IPU0""
diff --git a/src/mainboard/google/rex/variants/rex0/overridetree.cb b/src/mainboard/google/rex/variants/rex0/overridetree.cb
index 66b2bc9528..0ed077c587 100644
--- a/src/mainboard/google/rex/variants/rex0/overridetree.cb
+++ b/src/mainboard/google/rex/variants/rex0/overridetree.cb
@@ -470,6 +470,7 @@ chip soc/intel/meteorlake
 
 				register "ssdb.lanes_used" = "4"
 				register "ssdb.link_used" = "0"
+				register "ssdb.platform" = "PLAT_MTL"
 				register "ssdb.vcm_type" = "0x0C"
 				register "vcm_name" = ""VCM0""
 				register "num_freq_entries" = "1"
@@ -624,6 +625,7 @@ chip soc/intel/meteorlake
 
 				register "ssdb.lanes_used" = "2"
 				register "ssdb.link_used" = "1"
+				register "ssdb.platform" = "PLAT_MTL"
 				register "num_freq_entries" = "1"
 				register "link_freq[0]" = "437 * MHz"
 				register "remote_name" = ""IPU0""
diff --git a/src/mainboard/google/rex/variants/screebo/overridetree.cb b/src/mainboard/google/rex/variants/screebo/overridetree.cb
index cbfa652273..005d352b24 100644
--- a/src/mainboard/google/rex/variants/screebo/overridetree.cb
+++ b/src/mainboard/google/rex/variants/screebo/overridetree.cb
@@ -516,6 +516,7 @@ chip soc/intel/meteorlake
 				register "device_type" = "INTEL_ACPI_CAMERA_SENSOR"
 				register "ssdb.lanes_used" = "4"
 				register "ssdb.link_used" = "1"
+				register "ssdb.platform" = "PLAT_MTL"
 				register "num_freq_entries" = "1"
 				register "link_freq[0]" = "400 * MHz"
 				register "remote_name" = ""IPU0""
diff --git a/src/mainboard/intel/adlrvp/devicetree.cb b/src/mainboard/intel/adlrvp/devicetree.cb
index 031b2f059b..61317b4338 100644
--- a/src/mainboard/intel/adlrvp/devicetree.cb
+++ b/src/mainboard/intel/adlrvp/devicetree.cb
@@ -354,6 +354,7 @@ chip soc/intel/alderlake
 				register "device_type" = "INTEL_ACPI_CAMERA_SENSOR"
 
 				register "ssdb.lanes_used" = "2"
+				register "ssdb.platform" = "PLAT_ADL"
 				register "ssdb.vcm_type" = "0x0C"
 				register "vcm_name" = ""VCM0""
 				register "num_freq_entries" = "1"
@@ -407,6 +408,7 @@ chip soc/intel/alderlake
 				register "device_type" = "INTEL_ACPI_CAMERA_SENSOR"
 
 				register "ssdb.lanes_used" = "2"
+				register "ssdb.platform" = "PLAT_ADL"
 				register "num_freq_entries" = "1"
 				register "link_freq[0]" = "450000000"
 				register "remote_name" = ""IPU0""
diff --git a/src/mainboard/intel/adlrvp/devicetree_m.cb b/src/mainboard/intel/adlrvp/devicetree_m.cb
index 1ee0f324dc..54d2c17ae7 100644
--- a/src/mainboard/intel/adlrvp/devicetree_m.cb
+++ b/src/mainboard/intel/adlrvp/devicetree_m.cb
@@ -288,6 +288,7 @@ chip soc/intel/alderlake
 				register "device_type" = "INTEL_ACPI_CAMERA_SENSOR"
 
 				register "ssdb.lanes_used" = "2"
+				register "ssdb.platform" = "PLAT_ADL"
 				register "ssdb.vcm_type" = "0x0C"
 				register "vcm_name" = ""VCM0""
 				register "num_freq_entries" = "1"
@@ -341,6 +342,7 @@ chip soc/intel/alderlake
 				register "device_type" = "INTEL_ACPI_CAMERA_SENSOR"
 
 				register "ssdb.lanes_used" = "2"
+				register "ssdb.platform" = "PLAT_ADL"
 				register "num_freq_entries" = "1"
 				register "link_freq[0]" = "450000000"
 				register "remote_name" = ""IPU0""
diff --git a/src/mainboard/intel/adlrvp/devicetree_n.cb b/src/mainboard/intel/adlrvp/devicetree_n.cb
index 1eff9459d3..75eab4efcd 100644
--- a/src/mainboard/intel/adlrvp/devicetree_n.cb
+++ b/src/mainboard/intel/adlrvp/devicetree_n.cb
@@ -296,6 +296,7 @@ chip soc/intel/alderlake
 				register "device_type" = "INTEL_ACPI_CAMERA_SENSOR"
 
 				register "ssdb.lanes_used" = "2"
+				register "ssdb.platform" = "PLAT_ADL"
 				register "ssdb.vcm_type" = "0x0C"
 				register "vcm_name" = ""VCM0""
 				register "num_freq_entries" = "1"
@@ -349,6 +350,7 @@ chip soc/intel/alderlake
 				register "device_type" = "INTEL_ACPI_CAMERA_SENSOR"
 
 				register "ssdb.lanes_used" = "2"
+				register "ssdb.platform" = "PLAT_ADL"
 				register "num_freq_entries" = "1"
 				register "link_freq[0]" = "450000000"
 				register "remote_name" = ""IPU0""
diff --git a/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb b/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb
index b4a9261188..d9d90d325a 100644
--- a/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb
+++ b/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb
@@ -378,6 +378,7 @@ chip soc/intel/jasperlake
 				register "has_power_resource" = "true"
 
 				register "ssdb.lanes_used" = "2"
+				register "ssdb.platform" = "PLAT_JSL"
 				register "num_freq_entries" = "1"
 				register "link_freq[0]" = "360000000"
 				register "remote_name" = ""IPU0""
@@ -415,6 +416,7 @@ chip soc/intel/jasperlake
 
 				register "ssdb.lanes_used" = "2"
 				register "ssdb.link_used" = "1"
+				register "ssdb.platform" = "PLAT_JSL"
 				register "ssdb.vcm_type" = "0x0C"
 				register "vcm_name" = ""VCM0""
 				register "num_freq_entries" = "1"
@@ -455,6 +457,7 @@ chip soc/intel/jasperlake
 				register "vcm_compat" = ""dongwoon,dw9714""
 
 				register "ssdb.lanes_used" = "2"
+				register "ssdb.platform" = "PLAT_JSL"
 				register "num_freq_entries" = "1"
 				register "link_freq[0]" = "DEFAULT_LINK_FREQ"
 				register "remote_name" = ""IPU0""
diff --git a/src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/devicetree.cb b/src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/devicetree.cb
index 6d14b5819b..d59d6f7259 100644
--- a/src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/devicetree.cb
+++ b/src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/devicetree.cb
@@ -441,6 +441,7 @@ chip soc/intel/meteorlake
 				register "device_type" = "INTEL_ACPI_CAMERA_SENSOR"
 
 				register "ssdb.lanes_used" = "4"
+				register "ssdb.platform" = "PLAT_MTL"
 				register "num_freq_entries" = "1"
 				register "link_freq[0]" = "560000000"
 				register "remote_name" = ""IPU0""
@@ -480,6 +481,7 @@ chip soc/intel/meteorlake
 				register "vcm_name" = ""VCM1""
 
 				register "ssdb.lanes_used" = "4"
+				register "ssdb.platform" = "PLAT_MTL"
 				register "num_freq_entries" = "1"
 				register "link_freq[0]" = "560000000"
 				register "remote_name" = ""IPU0""
diff --git a/src/mainboard/intel/ptlrvp/variants/ptlrvp/overridetree.cb b/src/mainboard/intel/ptlrvp/variants/ptlrvp/overridetree.cb
index 4cb063bab7..84103fd3e9 100644
--- a/src/mainboard/intel/ptlrvp/variants/ptlrvp/overridetree.cb
+++ b/src/mainboard/intel/ptlrvp/variants/ptlrvp/overridetree.cb
@@ -662,6 +662,7 @@ chip soc/intel/pantherlake
 				register "vcm_name" = ""VCM1""
 
 				register "ssdb.lanes_used" = "4"
+				register "ssdb.platform" = "PLAT_PTL"
 				register "num_freq_entries" = "1"
 				register "link_freq[0]" = "560 * MHz" # 560 MHz
 				register "remote_name" = ""IPU0""
@@ -763,6 +764,7 @@ chip soc/intel/pantherlake
 				register "vcm_name" = ""VCM1""
 
 				register "ssdb.lanes_used" = "2"
+				register "ssdb.platform" = "PLAT_PTL"
 				register "num_freq_entries" = "1"
 				register "link_freq[0]" = "560 * MHz" # 560 MHz
 				register "remote_name" = ""IPU0""
diff --git a/src/mainboard/intel/ptlrvp/variants/ptlrvp_chromeec/overridetree.cb b/src/mainboard/intel/ptlrvp/variants/ptlrvp_chromeec/overridetree.cb
index 19785ecc7c..69bdd43cc8 100644
--- a/src/mainboard/intel/ptlrvp/variants/ptlrvp_chromeec/overridetree.cb
+++ b/src/mainboard/intel/ptlrvp/variants/ptlrvp_chromeec/overridetree.cb
@@ -662,6 +662,7 @@ chip soc/intel/pantherlake
 				register "vcm_name" = ""VCM1""
 
 				register "ssdb.lanes_used" = "4"
+				register "ssdb.platform" = "PLAT_PTL"
 				register "num_freq_entries" = "1"
 				register "link_freq[0]" = "560 * MHz" # 560 MHz
 				register "remote_name" = ""IPU0""
@@ -763,6 +764,7 @@ chip soc/intel/pantherlake
 				register "vcm_name" = ""VCM1""
 
 				register "ssdb.lanes_used" = "2"
+				register "ssdb.platform" = "PLAT_PTL"
 				register "num_freq_entries" = "1"
 				register "link_freq[0]" = "560 * MHz" # 560 MHz
 				register "remote_name" = ""IPU0""

From e9ebcb2918b9f862754e8b91ad4033c38a5472c0 Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Mon, 24 Nov 2025 14:49:30 -0600
Subject: [PATCH 2660/3886] mb/{google,intel}: Fix MIPI camera VCM type and
 address configuration

Many boards were incorrectly using the VCM I2C address (0x0C) as the
SSDB vcm_type field value. These are two separate fields:
- ssdb.vcm_type: Enum identifying the VCM chip model (VCM_DW9714,
  VCM_DW9808, etc.) used by drivers to select appropriate VCM functions
- vcm_address: I2C address of the VCM device (typically 0x0C)

Replace hardcoded "0x0C" values in ssdb.vcm_type with the correct enum
values based on the actual VCM device:
- VCM_DW9714 for boards using DW9714 VCMs
- VCM_DW9808 for boards using DW9768 VCMs (DW9768 doesn't have an enum,
  but DW9808 has compatible register layout)

Add vcm_address = "0x0C" to all affected boards to properly specify
the I2C address separately from the VCM type.

This ensures the Windows and Linux camera drivers receive the correct
VCM type information needed for proper initialization and function
pointer selection.

TEST=tested with rest of patch train

Change-Id: I53a560b0b03a1fe49d35ad8238679cc130327ade
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90197
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-by: Eric Lai <ericllai@google.com>
---
 src/mainboard/google/brya/variants/anraggar/overridetree.cb | 3 ++-
 src/mainboard/google/brya/variants/brya0/overridetree.cb    | 6 ++++--
 src/mainboard/google/brya/variants/craask/overridetree.cb   | 6 ++++--
 src/mainboard/google/brya/variants/meliks/overridetree.cb   | 3 ++-
 src/mainboard/google/brya/variants/nivviks/overridetree.cb  | 3 ++-
 src/mainboard/google/brya/variants/pirrha/overridetree.cb   | 3 ++-
 src/mainboard/google/brya/variants/pujjolo/overridetree.cb  | 3 ++-
 src/mainboard/google/brya/variants/riven/overridetree.cb    | 6 ++++--
 src/mainboard/google/brya/variants/skolas/overridetree.cb   | 6 ++++--
 .../google/brya/variants/skolas4es/overridetree.cb          | 3 ++-
 src/mainboard/google/brya/variants/teliks/overridetree.cb   | 3 ++-
 src/mainboard/google/brya/variants/telith/overridetree.cb   | 3 ++-
 src/mainboard/google/brya/variants/xivu/overridetree.cb     | 3 ++-
 src/mainboard/google/brya/variants/yaviks/overridetree.cb   | 3 ++-
 src/mainboard/google/brya/variants/yavilla/overridetree.cb  | 3 ++-
 src/mainboard/google/dedede/variants/bugzzy/overridetree.cb | 3 ++-
 .../google/dedede/variants/drawcia/overridetree.cb          | 3 ++-
 src/mainboard/google/dedede/variants/haboki/overridetree.cb | 3 ++-
 src/mainboard/google/dedede/variants/lalala/overridetree.cb | 3 ++-
 .../google/dedede/variants/magolor/overridetree.cb          | 6 ++++--
 src/mainboard/google/dedede/variants/storo/overridetree.cb  | 3 ++-
 .../google/dedede/variants/waddledoo/overridetree.cb        | 3 ++-
 src/mainboard/google/fatcat/variants/fatcat/overridetree.cb | 6 ++++--
 src/mainboard/google/rex/variants/rex0/overridetree.cb      | 3 ++-
 src/mainboard/intel/adlrvp/devicetree.cb                    | 3 ++-
 src/mainboard/intel/adlrvp/devicetree_m.cb                  | 3 ++-
 src/mainboard/intel/adlrvp/devicetree_n.cb                  | 3 ++-
 .../intel/jasperlake_rvp/variants/jslrvp/devicetree.cb      | 3 ++-
 .../intel/mtlrvp/variants/baseboard/mtlrvp_p/devicetree.cb  | 3 ++-
 src/mainboard/intel/ptlrvp/variants/ptlrvp/overridetree.cb  | 6 ++++--
 .../intel/ptlrvp/variants/ptlrvp_chromeec/overridetree.cb   | 6 ++++--
 31 files changed, 78 insertions(+), 39 deletions(-)

diff --git a/src/mainboard/google/brya/variants/anraggar/overridetree.cb b/src/mainboard/google/brya/variants/anraggar/overridetree.cb
index f6d75396c0..d5814bfb38 100644
--- a/src/mainboard/google/brya/variants/anraggar/overridetree.cb
+++ b/src/mainboard/google/brya/variants/anraggar/overridetree.cb
@@ -271,7 +271,8 @@ chip soc/intel/alderlake
 
 				register "ssdb.lanes_used" = "4"
 				register "ssdb.platform" = "PLAT_ADL"
-				register "ssdb.vcm_type" = "0x0C"
+				register "ssdb.vcm_type" = "VCM_DW9714"
+				register "vcm_address" = "0x0C"
 				register "vcm_name" = ""VCM0""
 				register "num_freq_entries" = "1"
 				register "link_freq[0]" = "560 * MHz"
diff --git a/src/mainboard/google/brya/variants/brya0/overridetree.cb b/src/mainboard/google/brya/variants/brya0/overridetree.cb
index 189d015478..9184fc4e1b 100644
--- a/src/mainboard/google/brya/variants/brya0/overridetree.cb
+++ b/src/mainboard/google/brya/variants/brya0/overridetree.cb
@@ -545,7 +545,8 @@ chip soc/intel/alderlake
 				register "ssdb.lanes_used" = "4"
 				register "ssdb.link_used" = "0"
 				register "ssdb.platform" = "PLAT_ADL"
-				register "ssdb.vcm_type" = "0x0C"
+				register "ssdb.vcm_type" = "VCM_DW9808"
+				register "vcm_address" = "0x0C"
 				register "vcm_name" = ""VCM0""
 				register "num_freq_entries" = "2"
 				register "link_freq[0]" = "360 * MHz" # 360 MHz
@@ -651,7 +652,8 @@ chip soc/intel/alderlake
 				register "ssdb.lanes_used" = "4"
 				register "ssdb.link_used" = "0"
 				register "ssdb.platform" = "PLAT_ADL"
-				register "ssdb.vcm_type" = "0x0C"
+				register "ssdb.vcm_type" = "VCM_DW9808"
+				register "vcm_address" = "0x0C"
 				register "vcm_name" = ""VCM0""
 				register "num_freq_entries" = "2"
 				register "link_freq[0]" = "360 * MHz" # 360 MHz
diff --git a/src/mainboard/google/brya/variants/craask/overridetree.cb b/src/mainboard/google/brya/variants/craask/overridetree.cb
index 1a8d5b1d17..186845ed4b 100644
--- a/src/mainboard/google/brya/variants/craask/overridetree.cb
+++ b/src/mainboard/google/brya/variants/craask/overridetree.cb
@@ -482,7 +482,8 @@ chip soc/intel/alderlake
 				register "ssdb.lanes_used" = "2"
 				register "ssdb.link_used" = "1"
 				register "ssdb.platform" = "PLAT_ADL"
-				register "ssdb.vcm_type" = "0x0C"
+				register "ssdb.vcm_type" = "VCM_DW9714"
+				register "vcm_address" = "0x0C"
 				register "vcm_name" = ""VCM0""
 				register "num_freq_entries" = "1"
 				register "link_freq[0]" = "DEFAULT_LINK_FREQ"
@@ -530,7 +531,8 @@ chip soc/intel/alderlake
 				register "ssdb.lanes_used" = "2"
 				register "ssdb.link_used" = "1"
 				register "ssdb.platform" = "PLAT_ADL"
-				register "ssdb.vcm_type" = "0x0C"
+				register "ssdb.vcm_type" = "VCM_DW9714"
+				register "vcm_address" = "0x0C"
 				register "vcm_name" = ""VCM0""
 				register "num_freq_entries" = "2"
 				register "link_freq[0]" = "720000000"
diff --git a/src/mainboard/google/brya/variants/meliks/overridetree.cb b/src/mainboard/google/brya/variants/meliks/overridetree.cb
index 743dd2180c..d830da70d0 100644
--- a/src/mainboard/google/brya/variants/meliks/overridetree.cb
+++ b/src/mainboard/google/brya/variants/meliks/overridetree.cb
@@ -266,7 +266,8 @@ chip soc/intel/alderlake
 				register "ssdb.lanes_used" = "4"
 				register "ssdb.link_used" = "1"
 				register "ssdb.platform" = "PLAT_ADL"
-				register "ssdb.vcm_type" = "0x0C"
+				register "ssdb.vcm_type" = "VCM_DW9714"
+				register "vcm_address" = "0x0C"
 				register "vcm_name" = ""VCM0""
 				register "num_freq_entries" = "2"
 				register "link_freq[0]" = "360000000"
diff --git a/src/mainboard/google/brya/variants/nivviks/overridetree.cb b/src/mainboard/google/brya/variants/nivviks/overridetree.cb
index fa7833d153..a4852608b1 100644
--- a/src/mainboard/google/brya/variants/nivviks/overridetree.cb
+++ b/src/mainboard/google/brya/variants/nivviks/overridetree.cb
@@ -391,7 +391,8 @@ chip soc/intel/alderlake
 				register "ssdb.lanes_used" = "2"
 				register "ssdb.link_used" = "1"
 				register "ssdb.platform" = "PLAT_ADL"
-				register "ssdb.vcm_type" = "0x0C"
+				register "ssdb.vcm_type" = "VCM_DW9714"
+				register "vcm_address" = "0x0C"
 				register "vcm_name" = ""VCM0""
 				register "num_freq_entries" = "1"
 				register "link_freq[0]" = "DEFAULT_LINK_FREQ"
diff --git a/src/mainboard/google/brya/variants/pirrha/overridetree.cb b/src/mainboard/google/brya/variants/pirrha/overridetree.cb
index 68cfb6f7b2..60354feafa 100644
--- a/src/mainboard/google/brya/variants/pirrha/overridetree.cb
+++ b/src/mainboard/google/brya/variants/pirrha/overridetree.cb
@@ -305,7 +305,8 @@ chip soc/intel/alderlake
 				register "ssdb.lanes_used" = "4"
 				register "ssdb.link_used" = "1"
 				register "ssdb.platform" = "PLAT_ADL"
-				register "ssdb.vcm_type" = "0x0C"
+				register "ssdb.vcm_type" = "VCM_DW9714"
+				register "vcm_address" = "0x0C"
 				register "vcm_name" = ""VCM0""
 				register "num_freq_entries" = "2"
 				register "link_freq[0]" = "360000000"
diff --git a/src/mainboard/google/brya/variants/pujjolo/overridetree.cb b/src/mainboard/google/brya/variants/pujjolo/overridetree.cb
index 318453c454..69d66abc8d 100644
--- a/src/mainboard/google/brya/variants/pujjolo/overridetree.cb
+++ b/src/mainboard/google/brya/variants/pujjolo/overridetree.cb
@@ -395,7 +395,8 @@ chip soc/intel/alderlake
 				register "ssdb.lanes_used" = "4"
 				register "ssdb.link_used" = "1"
 				register "ssdb.platform" = "PLAT_ADL"
-				register "ssdb.vcm_type" = "0x0C"
+				register "ssdb.vcm_type" = "VCM_DW9714"
+				register "vcm_address" = "0x0C"
 				register "vcm_name" = ""VCM0""
 				register "num_freq_entries" = "2"
 				register "link_freq[0]" = "360000000"
diff --git a/src/mainboard/google/brya/variants/riven/overridetree.cb b/src/mainboard/google/brya/variants/riven/overridetree.cb
index 077acb0962..1bd2c148a5 100644
--- a/src/mainboard/google/brya/variants/riven/overridetree.cb
+++ b/src/mainboard/google/brya/variants/riven/overridetree.cb
@@ -347,7 +347,8 @@ chip soc/intel/alderlake
 				register "ssdb.lanes_used" = "2"
 				register "ssdb.link_used" = "1"
 				register "ssdb.platform" = "PLAT_ADL"
-				register "ssdb.vcm_type" = "0x0C"
+				register "ssdb.vcm_type" = "VCM_DW9714"
+				register "vcm_address" = "0x0C"
 				register "vcm_name" = ""VCM0""
 				register "num_freq_entries" = "1"
 				register "link_freq[0]" = "DEFAULT_LINK_FREQ"
@@ -395,7 +396,8 @@ chip soc/intel/alderlake
 				register "ssdb.lanes_used" = "2"
 				register "ssdb.link_used" = "1"
 				register "ssdb.platform" = "PLAT_ADL"
-				register "ssdb.vcm_type" = "0x0C"
+				register "ssdb.vcm_type" = "VCM_DW9714"
+				register "vcm_address" = "0x0C"
 				register "vcm_name" = ""VCM0""
 				register "num_freq_entries" = "2"
 				register "link_freq[0]" = "720000000"
diff --git a/src/mainboard/google/brya/variants/skolas/overridetree.cb b/src/mainboard/google/brya/variants/skolas/overridetree.cb
index e984904425..8cc296e4dc 100644
--- a/src/mainboard/google/brya/variants/skolas/overridetree.cb
+++ b/src/mainboard/google/brya/variants/skolas/overridetree.cb
@@ -544,7 +544,8 @@ chip soc/intel/alderlake
 				register "ssdb.lanes_used" = "4"
 				register "ssdb.link_used" = "0"
 				register "ssdb.platform" = "PLAT_ADL"
-				register "ssdb.vcm_type" = "0x0C"
+				register "ssdb.vcm_type" = "VCM_DW9808"
+				register "vcm_address" = "0x0C"
 				register "vcm_name" = ""VCM0""
 				register "num_freq_entries" = "2"
 				register "link_freq[0]" = "360 * MHz" # 360 MHz
@@ -650,7 +651,8 @@ chip soc/intel/alderlake
 				register "ssdb.lanes_used" = "4"
 				register "ssdb.link_used" = "0"
 				register "ssdb.platform" = "PLAT_ADL"
-				register "ssdb.vcm_type" = "0x0C"
+				register "ssdb.vcm_type" = "VCM_DW9808"
+				register "vcm_address" = "0x0C"
 				register "vcm_name" = ""VCM0""
 				register "num_freq_entries" = "2"
 				register "link_freq[0]" = "360 * MHz" # 360 MHz
diff --git a/src/mainboard/google/brya/variants/skolas4es/overridetree.cb b/src/mainboard/google/brya/variants/skolas4es/overridetree.cb
index 05156bf967..d7b04119d8 100644
--- a/src/mainboard/google/brya/variants/skolas4es/overridetree.cb
+++ b/src/mainboard/google/brya/variants/skolas4es/overridetree.cb
@@ -385,7 +385,8 @@ chip soc/intel/alderlake
 				register "ssdb.lanes_used" = "4"
 				register "ssdb.link_used" = "0"
 				register "ssdb.platform" = "PLAT_ADL"
-				register "ssdb.vcm_type" = "0x0C"
+				register "ssdb.vcm_type" = "VCM_DW9808"
+				register "vcm_address" = "0x0C"
 				register "vcm_name" = ""VCM0""
 				register "num_freq_entries" = "2"
 				register "link_freq[0]" = "360 * MHz" # 360 MHz
diff --git a/src/mainboard/google/brya/variants/teliks/overridetree.cb b/src/mainboard/google/brya/variants/teliks/overridetree.cb
index 4ef2718e74..9dde7bfed8 100644
--- a/src/mainboard/google/brya/variants/teliks/overridetree.cb
+++ b/src/mainboard/google/brya/variants/teliks/overridetree.cb
@@ -288,7 +288,8 @@ chip soc/intel/alderlake
 
 				register "ssdb.lanes_used" = "4"
 				register "ssdb.platform" = "PLAT_ADL"
-				register "ssdb.vcm_type" = "0x0C"
+				register "ssdb.vcm_type" = "VCM_DW9714"
+				register "vcm_address" = "0x0C"
 				register "vcm_name" = ""VCM0""
 				register "num_freq_entries" = "1"
 				register "link_freq[0]" = "560 * MHz"
diff --git a/src/mainboard/google/brya/variants/telith/overridetree.cb b/src/mainboard/google/brya/variants/telith/overridetree.cb
index ea4dbd2687..bd80d97b39 100644
--- a/src/mainboard/google/brya/variants/telith/overridetree.cb
+++ b/src/mainboard/google/brya/variants/telith/overridetree.cb
@@ -414,7 +414,8 @@ chip soc/intel/alderlake
 
 				register "ssdb.lanes_used" = "4"
 				register "ssdb.platform" = "PLAT_ADL"
-				register "ssdb.vcm_type" = "0x0C"
+				register "ssdb.vcm_type" = "VCM_DW9714"
+				register "vcm_address" = "0x0C"
 				register "vcm_name" = ""VCM0""
 				register "num_freq_entries" = "1"
 				register "link_freq[0]" = "560 * MHz"
diff --git a/src/mainboard/google/brya/variants/xivu/overridetree.cb b/src/mainboard/google/brya/variants/xivu/overridetree.cb
index dd0fdbaff1..bf9a6c45ec 100644
--- a/src/mainboard/google/brya/variants/xivu/overridetree.cb
+++ b/src/mainboard/google/brya/variants/xivu/overridetree.cb
@@ -255,7 +255,8 @@ chip soc/intel/alderlake
 				register "ssdb.lanes_used" = "4"
 				register "ssdb.link_used" = "1"
 				register "ssdb.platform" = "PLAT_ADL"
-				register "ssdb.vcm_type" = "0x0C"
+				register "ssdb.vcm_type" = "VCM_DW9714"
+				register "vcm_address" = "0x0C"
 				register "vcm_name" = ""VCM0""
 				register "num_freq_entries" = "2"
 				register "link_freq[0]" = "360000000"
diff --git a/src/mainboard/google/brya/variants/yaviks/overridetree.cb b/src/mainboard/google/brya/variants/yaviks/overridetree.cb
index 87f39473a3..6ecfa73ab3 100644
--- a/src/mainboard/google/brya/variants/yaviks/overridetree.cb
+++ b/src/mainboard/google/brya/variants/yaviks/overridetree.cb
@@ -333,7 +333,8 @@ chip soc/intel/alderlake
 				register "ssdb.lanes_used" = "2"
 				register "ssdb.link_used" = "1"
 				register "ssdb.platform" = "PLAT_ADL"
-				register "ssdb.vcm_type" = "0x0C"
+				register "ssdb.vcm_type" = "VCM_DW9714"
+				register "vcm_address" = "0x0C"
 				register "vcm_name" = ""VCM0""
 				register "num_freq_entries" = "2"
 				register "link_freq[0]" = "360000000"
diff --git a/src/mainboard/google/brya/variants/yavilla/overridetree.cb b/src/mainboard/google/brya/variants/yavilla/overridetree.cb
index 8e5cb70848..f88db8d5b1 100644
--- a/src/mainboard/google/brya/variants/yavilla/overridetree.cb
+++ b/src/mainboard/google/brya/variants/yavilla/overridetree.cb
@@ -368,7 +368,8 @@ chip soc/intel/alderlake
 				register "ssdb.lanes_used" = "4"
 				register "ssdb.link_used" = "1"
 				register "ssdb.platform" = "PLAT_ADL"
-				register "ssdb.vcm_type" = "0x0C"
+				register "ssdb.vcm_type" = "VCM_DW9714"
+				register "vcm_address" = "0x0C"
 				register "vcm_name" = ""VCM0""
 				register "num_freq_entries" = "2"
 				register "link_freq[0]" = "360000000"
diff --git a/src/mainboard/google/dedede/variants/bugzzy/overridetree.cb b/src/mainboard/google/dedede/variants/bugzzy/overridetree.cb
index 08ba6eba0d..4d51d19fbc 100644
--- a/src/mainboard/google/dedede/variants/bugzzy/overridetree.cb
+++ b/src/mainboard/google/dedede/variants/bugzzy/overridetree.cb
@@ -241,7 +241,8 @@ chip soc/intel/jasperlake
 				register "ssdb.lanes_used" = "4"
 				register "ssdb.link_used" = "1"
 				register "ssdb.platform" = "PLAT_JSL"
-				register "ssdb.vcm_type" = "0x0C"
+				register "ssdb.vcm_type" = "VCM_DW9714"
+				register "vcm_address" = "0x0C"
 				register "vcm_name" = ""VCM0""
 				register "num_freq_entries" = "2"
 				register "link_freq[0]" = "360000000"
diff --git a/src/mainboard/google/dedede/variants/drawcia/overridetree.cb b/src/mainboard/google/dedede/variants/drawcia/overridetree.cb
index c2673c6c8d..e8546a5cae 100644
--- a/src/mainboard/google/dedede/variants/drawcia/overridetree.cb
+++ b/src/mainboard/google/dedede/variants/drawcia/overridetree.cb
@@ -307,7 +307,8 @@ chip soc/intel/jasperlake
 				register "ssdb.lanes_used" = "4"
 				register "ssdb.link_used" = "1"
 				register "ssdb.platform" = "PLAT_JSL"
-				register "ssdb.vcm_type" = "0x0C"
+				register "ssdb.vcm_type" = "VCM_DW9714"
+				register "vcm_address" = "0x0C"
 				register "vcm_name" = ""VCM0""
 				register "num_freq_entries" = "2"
 				register "link_freq[0]" = "360000000"
diff --git a/src/mainboard/google/dedede/variants/haboki/overridetree.cb b/src/mainboard/google/dedede/variants/haboki/overridetree.cb
index 97408a674a..d8bb09168d 100644
--- a/src/mainboard/google/dedede/variants/haboki/overridetree.cb
+++ b/src/mainboard/google/dedede/variants/haboki/overridetree.cb
@@ -216,7 +216,8 @@ chip soc/intel/jasperlake
 				register "ssdb.lanes_used" = "4"
 				register "ssdb.link_used" = "1"
 				register "ssdb.platform" = "PLAT_JSL"
-				register "ssdb.vcm_type" = "0x0C"
+				register "ssdb.vcm_type" = "VCM_DW9714"
+				register "vcm_address" = "0x0C"
 				register "vcm_name" = ""VCM0""
 				register "num_freq_entries" = "2"
 				register "link_freq[0]" = "360000000"
diff --git a/src/mainboard/google/dedede/variants/lalala/overridetree.cb b/src/mainboard/google/dedede/variants/lalala/overridetree.cb
index a421b8c5e9..358151025c 100644
--- a/src/mainboard/google/dedede/variants/lalala/overridetree.cb
+++ b/src/mainboard/google/dedede/variants/lalala/overridetree.cb
@@ -214,7 +214,8 @@ chip soc/intel/jasperlake
 				register "ssdb.lanes_used" = "2"
 				register "ssdb.link_used" = "1"
 				register "ssdb.platform" = "PLAT_JSL"
-				register "ssdb.vcm_type" = "0x0C"
+				register "ssdb.vcm_type" = "VCM_DW9714"
+				register "vcm_address" = "0x0C"
 				register "vcm_name" = ""VCM0""
 				register "num_freq_entries" = "1"
 				register "link_freq[0]" = "DEFAULT_LINK_FREQ"
diff --git a/src/mainboard/google/dedede/variants/magolor/overridetree.cb b/src/mainboard/google/dedede/variants/magolor/overridetree.cb
index c74c0fae9b..8f4176e85f 100644
--- a/src/mainboard/google/dedede/variants/magolor/overridetree.cb
+++ b/src/mainboard/google/dedede/variants/magolor/overridetree.cb
@@ -348,7 +348,8 @@ chip soc/intel/jasperlake
 				register "ssdb.lanes_used" = "2"
 				register "ssdb.link_used" = "1"
 				register "ssdb.platform" = "PLAT_JSL"
-				register "ssdb.vcm_type" = "0x0C"
+				register "ssdb.vcm_type" = "VCM_DW9714"
+				register "vcm_address" = "0x0C"
 				register "vcm_name" = ""VCM0""
 				register "num_freq_entries" = "1"
 				register "link_freq[0]" = "DEFAULT_LINK_FREQ"
@@ -393,7 +394,8 @@ chip soc/intel/jasperlake
 				register "ssdb.lanes_used" = "2"
 				register "ssdb.link_used" = "1"
 				register "ssdb.platform" = "PLAT_JSL"
-				register "ssdb.vcm_type" = "0x0C"
+				register "ssdb.vcm_type" = "VCM_DW9714"
+				register "vcm_address" = "0x0C"
 				register "vcm_name" = ""VCM0""
 				register "num_freq_entries" = "2"
 				register "link_freq[0]" = "720000000"
diff --git a/src/mainboard/google/dedede/variants/storo/overridetree.cb b/src/mainboard/google/dedede/variants/storo/overridetree.cb
index 400ec2f17e..1b21bf01af 100644
--- a/src/mainboard/google/dedede/variants/storo/overridetree.cb
+++ b/src/mainboard/google/dedede/variants/storo/overridetree.cb
@@ -231,7 +231,8 @@ chip soc/intel/jasperlake
 				register "ssdb.lanes_used" = "4"
 				register "ssdb.link_used" = "1"
 				register "ssdb.platform" = "PLAT_JSL"
-				register "ssdb.vcm_type" = "0x0C"
+				register "ssdb.vcm_type" = "VCM_DW9714"
+				register "vcm_address" = "0x0C"
 				register "vcm_name" = ""VCM0""
 				register "num_freq_entries" = "2"
 				register "link_freq[0]" = "360000000"
diff --git a/src/mainboard/google/dedede/variants/waddledoo/overridetree.cb b/src/mainboard/google/dedede/variants/waddledoo/overridetree.cb
index 38daca4903..acdfe0e496 100644
--- a/src/mainboard/google/dedede/variants/waddledoo/overridetree.cb
+++ b/src/mainboard/google/dedede/variants/waddledoo/overridetree.cb
@@ -148,7 +148,8 @@ chip soc/intel/jasperlake
 				register "ssdb.lanes_used" = "4"
 				register "ssdb.link_used" = "1"
 				register "ssdb.platform" = "PLAT_JSL"
-				register "ssdb.vcm_type" = "0x0C"
+				register "ssdb.vcm_type" = "VCM_DW9808"
+				register "vcm_address" = "0x0C"
 				register "vcm_name" = ""VCM0""
 				register "num_freq_entries" = "2"
 				register "link_freq[0]" = "360000000"
diff --git a/src/mainboard/google/fatcat/variants/fatcat/overridetree.cb b/src/mainboard/google/fatcat/variants/fatcat/overridetree.cb
index 1beff24ccf..f54b472b42 100644
--- a/src/mainboard/google/fatcat/variants/fatcat/overridetree.cb
+++ b/src/mainboard/google/fatcat/variants/fatcat/overridetree.cb
@@ -658,7 +658,8 @@ chip soc/intel/pantherlake
 				register "chip_name" = ""Ov 13b10 Camera""
 				register "device_type" = "INTEL_ACPI_CAMERA_SENSOR"
 
-				register "ssdb.vcm_type" = "0x0C"
+				register "ssdb.vcm_type" = "VCM_DW9714"
+				register "vcm_address" = "0x0C"
 				register "vcm_name" = ""VCM1""
 
 				register "ssdb.lanes_used" = "4"
@@ -760,7 +761,8 @@ chip soc/intel/pantherlake
 				register "chip_name" = ""Ov 13b10 Camera""
 				register "device_type" = "INTEL_ACPI_CAMERA_SENSOR"
 
-				register "ssdb.vcm_type" = "0x0C"
+				register "ssdb.vcm_type" = "VCM_DW9714"
+				register "vcm_address" = "0x0C"
 				register "vcm_name" = ""VCM1""
 
 				register "ssdb.lanes_used" = "2"
diff --git a/src/mainboard/google/rex/variants/rex0/overridetree.cb b/src/mainboard/google/rex/variants/rex0/overridetree.cb
index 0ed077c587..73e285e027 100644
--- a/src/mainboard/google/rex/variants/rex0/overridetree.cb
+++ b/src/mainboard/google/rex/variants/rex0/overridetree.cb
@@ -471,7 +471,8 @@ chip soc/intel/meteorlake
 				register "ssdb.lanes_used" = "4"
 				register "ssdb.link_used" = "0"
 				register "ssdb.platform" = "PLAT_MTL"
-				register "ssdb.vcm_type" = "0x0C"
+				register "ssdb.vcm_type" = "VCM_DW9714"
+				register "vcm_address" = "0x0C"
 				register "vcm_name" = ""VCM0""
 				register "num_freq_entries" = "1"
 				register "link_freq[0]" = "560 * MHz" # 560 MHz
diff --git a/src/mainboard/intel/adlrvp/devicetree.cb b/src/mainboard/intel/adlrvp/devicetree.cb
index 61317b4338..5c12bb3b80 100644
--- a/src/mainboard/intel/adlrvp/devicetree.cb
+++ b/src/mainboard/intel/adlrvp/devicetree.cb
@@ -355,7 +355,8 @@ chip soc/intel/alderlake
 
 				register "ssdb.lanes_used" = "2"
 				register "ssdb.platform" = "PLAT_ADL"
-				register "ssdb.vcm_type" = "0x0C"
+				register "ssdb.vcm_type" = "VCM_DW9714"
+				register "vcm_address" = "0x0C"
 				register "vcm_name" = ""VCM0""
 				register "num_freq_entries" = "1"
 				register "link_freq[0]" = "450000000"
diff --git a/src/mainboard/intel/adlrvp/devicetree_m.cb b/src/mainboard/intel/adlrvp/devicetree_m.cb
index 54d2c17ae7..7d197b0eca 100644
--- a/src/mainboard/intel/adlrvp/devicetree_m.cb
+++ b/src/mainboard/intel/adlrvp/devicetree_m.cb
@@ -289,7 +289,8 @@ chip soc/intel/alderlake
 
 				register "ssdb.lanes_used" = "2"
 				register "ssdb.platform" = "PLAT_ADL"
-				register "ssdb.vcm_type" = "0x0C"
+				register "ssdb.vcm_type" = "VCM_DW9714"
+				register "vcm_address" = "0x0C"
 				register "vcm_name" = ""VCM0""
 				register "num_freq_entries" = "1"
 				register "link_freq[0]" = "450000000"
diff --git a/src/mainboard/intel/adlrvp/devicetree_n.cb b/src/mainboard/intel/adlrvp/devicetree_n.cb
index 75eab4efcd..73b6828a38 100644
--- a/src/mainboard/intel/adlrvp/devicetree_n.cb
+++ b/src/mainboard/intel/adlrvp/devicetree_n.cb
@@ -297,7 +297,8 @@ chip soc/intel/alderlake
 
 				register "ssdb.lanes_used" = "2"
 				register "ssdb.platform" = "PLAT_ADL"
-				register "ssdb.vcm_type" = "0x0C"
+				register "ssdb.vcm_type" = "VCM_DW9714"
+				register "vcm_address" = "0x0C"
 				register "vcm_name" = ""VCM0""
 				register "num_freq_entries" = "1"
 				register "link_freq[0]" = "450000000"
diff --git a/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb b/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb
index d9d90d325a..d1fe840129 100644
--- a/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb
+++ b/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb
@@ -417,7 +417,8 @@ chip soc/intel/jasperlake
 				register "ssdb.lanes_used" = "2"
 				register "ssdb.link_used" = "1"
 				register "ssdb.platform" = "PLAT_JSL"
-				register "ssdb.vcm_type" = "0x0C"
+				register "ssdb.vcm_type" = "VCM_DW9714"
+				register "vcm_address" = "0x0C"
 				register "vcm_name" = ""VCM0""
 				register "num_freq_entries" = "1"
 				register "link_freq[0]" = "DEFAULT_LINK_FREQ"
diff --git a/src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/devicetree.cb b/src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/devicetree.cb
index d59d6f7259..c877a97945 100644
--- a/src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/devicetree.cb
+++ b/src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/devicetree.cb
@@ -477,7 +477,8 @@ chip soc/intel/meteorlake
 				register "chip_name" = ""Ov 13b10 Camera""
 				register "device_type" = "INTEL_ACPI_CAMERA_SENSOR"
 
-				register "ssdb.vcm_type" = "0x0C"
+				register "ssdb.vcm_type" = "VCM_DW9714"
+				register "vcm_address" = "0x0C"
 				register "vcm_name" = ""VCM1""
 
 				register "ssdb.lanes_used" = "4"
diff --git a/src/mainboard/intel/ptlrvp/variants/ptlrvp/overridetree.cb b/src/mainboard/intel/ptlrvp/variants/ptlrvp/overridetree.cb
index 84103fd3e9..b92a73a616 100644
--- a/src/mainboard/intel/ptlrvp/variants/ptlrvp/overridetree.cb
+++ b/src/mainboard/intel/ptlrvp/variants/ptlrvp/overridetree.cb
@@ -658,7 +658,8 @@ chip soc/intel/pantherlake
 				register "chip_name" = ""Ov 13b10 Camera""
 				register "device_type" = "INTEL_ACPI_CAMERA_SENSOR"
 
-				register "ssdb.vcm_type" = "0x0C"
+				register "ssdb.vcm_type" = "VCM_DW9714"
+				register "vcm_address" = "0x0C"
 				register "vcm_name" = ""VCM1""
 
 				register "ssdb.lanes_used" = "4"
@@ -760,7 +761,8 @@ chip soc/intel/pantherlake
 				register "chip_name" = ""Ov 13b10 Camera""
 				register "device_type" = "INTEL_ACPI_CAMERA_SENSOR"
 
-				register "ssdb.vcm_type" = "0x0C"
+				register "ssdb.vcm_type" = "VCM_DW9714"
+				register "vcm_address" = "0x0C"
 				register "vcm_name" = ""VCM1""
 
 				register "ssdb.lanes_used" = "2"
diff --git a/src/mainboard/intel/ptlrvp/variants/ptlrvp_chromeec/overridetree.cb b/src/mainboard/intel/ptlrvp/variants/ptlrvp_chromeec/overridetree.cb
index 69bdd43cc8..d2682891f6 100644
--- a/src/mainboard/intel/ptlrvp/variants/ptlrvp_chromeec/overridetree.cb
+++ b/src/mainboard/intel/ptlrvp/variants/ptlrvp_chromeec/overridetree.cb
@@ -658,7 +658,8 @@ chip soc/intel/pantherlake
 				register "chip_name" = ""Ov 13b10 Camera""
 				register "device_type" = "INTEL_ACPI_CAMERA_SENSOR"
 
-				register "ssdb.vcm_type" = "0x0C"
+				register "ssdb.vcm_type" = "VCM_DW9714"
+				register "vcm_address" = "0x0C"
 				register "vcm_name" = ""VCM1""
 
 				register "ssdb.lanes_used" = "4"
@@ -760,7 +761,8 @@ chip soc/intel/pantherlake
 				register "chip_name" = ""Ov 13b10 Camera""
 				register "device_type" = "INTEL_ACPI_CAMERA_SENSOR"
 
-				register "ssdb.vcm_type" = "0x0C"
+				register "ssdb.vcm_type" = "VCM_DW9714"
+				register "vcm_address" = "0x0C"
 				register "vcm_name" = ""VCM1""
 
 				register "ssdb.lanes_used" = "2"

From 49da58dccfdaf4bbec6ab7141270349bc0066bd2 Mon Sep 17 00:00:00 2001
From: Wentao Qin <qinwentao@huaqin.corp-partner.google.com>
Date: Sun, 2 Nov 2025 22:25:10 +0800
Subject: [PATCH 2661/3886] drivers/mipi: Add support for BOE NS130069-M00
 panel

Add BOE panel NS130069-M00 serializable data to CBFS.
Datasheet: NS130069-M00_V01_20250916.pdf

[INFO ]  CBFS: Found 'panel-BOE_NS130069_M00' @0xfc480 size 0x68b in mcache @0xfffdd62c

BUG=b:456907241
TEST=build and check the CBFS include the panel
BRANCH=none

Change-Id: Iefdfc7f6d8cea1d8d791e4d49ab63e78d306a6a4
Signed-off-by: Xiaokun Qiao <qiaoxiaokun@huaqin.corp-partner.google.com>
Signed-off-by: Wentao Qin <qinwentao@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90007
Reviewed-by: Chen-Tsung Hsieh <chentsung@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
---
 src/drivers/mipi/Kconfig                  |   3 +
 src/drivers/mipi/Makefile.mk              |   1 +
 src/drivers/mipi/panel-BOE_NS130069_M00.c | 638 ++++++++++++++++++++++
 3 files changed, 642 insertions(+)
 create mode 100644 src/drivers/mipi/panel-BOE_NS130069_M00.c

diff --git a/src/drivers/mipi/Kconfig b/src/drivers/mipi/Kconfig
index 62b28e5cf1..10d46628b4 100644
--- a/src/drivers/mipi/Kconfig
+++ b/src/drivers/mipi/Kconfig
@@ -12,6 +12,9 @@ config MIPI_PANEL_AUO_KD101N80_45NA
 config MIPI_PANEL_AUO_NT51021D8P
 	bool
 
+config MIPI_PANEL_BOE_NS130069_M00
+	bool
+
 config MIPI_PANEL_BOE_NV110WUM_L60
 	bool
 
diff --git a/src/drivers/mipi/Makefile.mk b/src/drivers/mipi/Makefile.mk
index 2d1ac9429a..92d5ebe987 100644
--- a/src/drivers/mipi/Makefile.mk
+++ b/src/drivers/mipi/Makefile.mk
@@ -8,6 +8,7 @@ panel-params-$(CONFIG_MIPI_PANEL_AUO_B101UAN08_3) += panel-AUO_B101UAN08_3
 panel-params-$(CONFIG_MIPI_PANEL_AUO_KD101N80_45NA) += panel-AUO_KD101N80_45NA
 panel-params-$(CONFIG_MIPI_PANEL_AUO_NT51021D8P) += panel-AUO_NT51021D8P
 
+panel-params-$(CONFIG_MIPI_PANEL_BOE_NS130069_M00) += panel-BOE_NS130069_M00
 panel-params-$(CONFIG_MIPI_PANEL_BOE_NV110WUM_L60) += panel-BOE_NV110WUM_L60
 panel-params-$(CONFIG_MIPI_PANEL_BOE_TV080WUM_NG0) += panel-BOE_TV080WUM_NG0
 panel-params-$(CONFIG_MIPI_PANEL_BOE_TV101WUM_N53) += panel-BOE_TV101WUM_N53
diff --git a/src/drivers/mipi/panel-BOE_NS130069_M00.c b/src/drivers/mipi/panel-BOE_NS130069_M00.c
new file mode 100644
index 0000000000..2e2accebfa
--- /dev/null
+++ b/src/drivers/mipi/panel-BOE_NS130069_M00.c
@@ -0,0 +1,638 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <mipi/panel.h>
+
+struct panel_serializable_data BOE_NS130069_M00 = {
+	.edid = {
+		.ascii_string = "NS130069",
+		.manufacturer_name = "BOE",
+		.panel_bits_per_color = 10,
+		.panel_bits_per_pixel = 24,
+		.mode = {
+			.pixel_clock = 1096243,
+			.lvds_dual_channel = 0,
+			.refresh = 120,
+			.ha = 3504, .hbl = 240, .hso = 104, .hspw = 8,
+			.va = 2190, .vbl = 250, .vso = 60, .vspw = 4,
+			.phsync = '-', .pvsync = '-',
+			.x_mm = 127, .y_mm = 203,
+		},
+	},
+	.init = {
+		PANEL_DCS(0xFF, 0x20),
+		PANEL_DCS(0xFB, 0x01),
+		PANEL_DCS(0x01, 0x44),
+		PANEL_DCS(0x05, 0x01),
+		PANEL_DCS(0x07, 0x41),
+		PANEL_DCS(0x08, 0x23),
+		PANEL_DCS(0x0D, 0x73),
+		PANEL_DCS(0x0E, 0x10),
+		PANEL_DCS(0x0F, 0x82),
+		PANEL_DCS(0x10, 0x46),
+		PANEL_DCS(0x1F, 0x00, 0x00, 0x00),
+		PANEL_DCS(0x30, 0x10),
+		PANEL_DCS(0x32, 0x72),
+		PANEL_DCS(0x58, 0x43),
+		PANEL_DCS(0x65, 0x66),
+		PANEL_DCS(0x69, 0xDD),
+		PANEL_DCS(0x6A, 0x73),
+		PANEL_DCS(0x6B, 0x71),
+		PANEL_DCS(0x6D, 0x66),
+		PANEL_DCS(0x6E, 0x20),
+		PANEL_DCS(0x78, 0x93),
+		PANEL_DCS(0x7D, 0x99),
+		PANEL_DCS(0x95, 0xFF),
+		PANEL_DCS(0x96, 0xFF),
+		PANEL_DCS(0xFF, 0x22),
+		PANEL_DCS(0xFB, 0x01),
+		PANEL_DCS(0x1E, 0x91),
+		PANEL_DCS(0x1F, 0x05),
+		PANEL_DCS(0x2F, 0x02),
+		PANEL_DCS(0x30, 0x6A),
+		PANEL_DCS(0x31, 0x02),
+		PANEL_DCS(0x32, 0x28),
+		PANEL_DCS(0x33, 0x03),
+		PANEL_DCS(0x34, 0x4A),
+		PANEL_DCS(0x6E, 0x13),
+		PANEL_DCS(0x6F, 0x04),
+		PANEL_DCS(0x70, 0x47),
+		PANEL_DCS(0x71, 0x04),
+		PANEL_DCS(0x73, 0x04),
+		PANEL_DCS(0x75, 0x00),
+		PANEL_DCS(0x76, 0x04),
+		PANEL_DCS(0x8A, 0x04),
+		PANEL_DCS(0x8C, 0x04),
+		PANEL_DCS(0x8E, 0xF3),
+		PANEL_DCS(0x8F, 0x23),
+		PANEL_DCS(0x90, 0x23),
+		PANEL_DCS(0x91, 0x23),
+		PANEL_DCS(0x92, 0x23),
+		PANEL_DCS(0x93, 0x23),
+		PANEL_DCS(0x96, 0x1A),
+		PANEL_DCS(0x9D, 0x1A),
+		PANEL_DCS(0x9F, 0x4C),
+		PANEL_DCS(0xA0, 0x17),
+		PANEL_DCS(0xA5, 0x09),
+		PANEL_DCS(0xA6, 0x10),
+		PANEL_DCS(0xA7, 0x16),
+		PANEL_DCS(0xA9, 0x50),
+		PANEL_DCS(0xAA, 0x5C),
+		PANEL_DCS(0xAB, 0x4A),
+		PANEL_DCS(0xAD, 0x10),
+		PANEL_DCS(0xB0, 0x0F, 0x0B, 0x0F, 0x0F),
+		PANEL_DCS(0xB1, 0xD7, 0xA8, 0xD7, 0xD7),
+		PANEL_DCS(0xB2, 0x0E, 0x0A, 0x0E, 0x0E),
+		PANEL_DCS(0xB3, 0xD1, 0xC0, 0xD1, 0xD1),
+		PANEL_DCS(0xB4, 0x0F, 0x0B, 0x0F, 0x0F),
+		PANEL_DCS(0xB5, 0x3D, 0x2C, 0x3D, 0x3D),
+		PANEL_DCS(0xB8, 0x03),
+		PANEL_DCS(0xB9, 0x6C, 0xA8),
+		PANEL_DCS(0xBA, 0x6C),
+		PANEL_DCS(0xBB, 0x6C),
+		PANEL_DCS(0xBC, 0x02),
+		PANEL_DCS(0xBD, 0x6C),
+		PANEL_DCS(0xBE, 0x0B),
+		PANEL_DCS(0xBF, 0x6C),
+		PANEL_DCS(0xC1, 0x6C),
+		PANEL_DCS(0xC2, 0x0C),
+		PANEL_DCS(0xC3, 0x6C),
+		PANEL_DCS(0xC6, 0x02),
+		PANEL_DCS(0xC7, 0x68),
+		PANEL_DCS(0xC8, 0x02),
+		PANEL_DCS(0xC9, 0x60),
+		PANEL_DCS(0xCB, 0x64),
+		PANEL_DCS(0xD0, 0x64),
+		PANEL_DCS(0xD1, 0x00),
+		PANEL_DCS(0xD2, 0x00),
+		PANEL_DCS(0xD4, 0x64),
+		PANEL_DCS(0xD8, 0x05),
+		PANEL_DCS(0xD9, 0x64),
+		PANEL_DCS(0xDA, 0x00),
+		PANEL_DCS(0xDB, 0x00),
+		PANEL_DCS(0xDC, 0x05),
+		PANEL_DCS(0xDD, 0x64),
+		PANEL_DCS(0xDE, 0x00),
+		PANEL_DCS(0xDF, 0x00),
+		PANEL_DCS(0xE1, 0x05),
+		PANEL_DCS(0xE2, 0x64),
+		PANEL_DCS(0xE6, 0x02),
+		PANEL_DCS(0xE7, 0x68),
+		PANEL_DCS(0xE8, 0x02),
+		PANEL_DCS(0xE9, 0x60),
+		PANEL_DCS(0xEB, 0x64),
+		PANEL_DCS(0xF3, 0x02),
+		PANEL_DCS(0xF4, 0x68),
+		PANEL_DCS(0xF6, 0x02),
+		PANEL_DCS(0xF7, 0x60),
+		PANEL_DCS(0xF8, 0x66),
+		PANEL_DCS(0xF9, 0x66),
+		PANEL_DCS(0xFF, 0x23),
+		PANEL_DCS(0xFB, 0x01),
+		PANEL_DCS(0x6B, 0x1A),
+		PANEL_DCS(0x6D, 0x1A),
+		PANEL_DCS(0x72, 0x04),
+		PANEL_DCS(0x76, 0x07, 0x02),
+		PANEL_DCS(0x77, 0x01, 0x02),
+		PANEL_DCS(0x78, 0x01, 0x02),
+		PANEL_DCS(0x7A, 0x12, 0xF4),
+		PANEL_DCS(0x7B, 0x32, 0x32),
+		PANEL_DCS(0x7C, 0x2D, 0x32),
+		PANEL_DCS(0x7E, 0x11, 0x10),
+		PANEL_DCS(0x89, 0xA4),
+		PANEL_DCS(0xBA, 0x00, 0x00, 0x21, 0x70, 0x00),
+		PANEL_DCS(0xBB, 0x00, 0x00, 0x1F, 0x70, 0x00),
+		PANEL_DCS(0xBC, 0xFF, 0x00, 0x01, 0x27, 0x00),
+		PANEL_DCS(0xFF, 0x24),
+		PANEL_DCS(0xFB, 0x01),
+		PANEL_DCS(0x00, 0x03, 0x27, 0x0D, 0x0C, 0x0F, 0x0E, 0x26, 0x26, 0x28, 0x04,
+			  0x05, 0x27, 0x26, 0x29, 0x29, 0x08),
+		PANEL_DCS(0x01, 0x27, 0x27, 0x30, 0x2E, 0x2C, 0x41, 0x3F, 0x3D),
+		PANEL_DCS(0x02, 0x03, 0x27, 0x0D, 0x0C, 0x0F, 0x0E, 0x26, 0x26, 0x28, 0x04,
+			  0x05, 0x27, 0x26, 0x29, 0x29, 0x08),
+		PANEL_DCS(0x03, 0x27, 0x27, 0x41, 0x3F, 0x3D, 0x30, 0x2E, 0x2C),
+		PANEL_DCS(0x09, 0x79, 0x79, 0x79, 0x79, 0x79, 0x79, 0x00),
+		PANEL_DCS(0x0A, 0xA0, 0xA0, 0xA0, 0xA0, 0xA0, 0xA0, 0xA0, 0xA0, 0x00),
+		PANEL_DCS(0x0B, 0x26, 0x26, 0x26, 0x26, 0x26, 0x26, 0x00),
+		PANEL_DCS(0x0C, 0x64, 0x64, 0x64, 0x64, 0x64, 0x64, 0x64, 0x64, 0x00),
+		PANEL_DCS(0x0D, 0x31, 0x31, 0x31, 0x31, 0x31, 0x31, 0x00),
+		PANEL_DCS(0x12, 0x21, 0x43, 0x65, 0x87, 0x34, 0x12, 0x56, 0x00),
+		PANEL_DCS(0x13, 0x21, 0x43, 0x00, 0x00, 0x00, 0x00, 0x34, 0x12, 0x56, 0x00,
+			  0x00, 0x00),
+		PANEL_DCS(0x17, 0x41, 0x25, 0x63, 0xA7, 0x8B, 0xC9, 0x0D, 0xE1, 0x2F, 0x63,
+			  0x47, 0x85, 0x00, 0x60, 0xFE),
+		PANEL_DCS(0x18, 0x41, 0x25, 0x63, 0xA7, 0x8B, 0xC9, 0x0D, 0xE1, 0x2F, 0x63,
+			  0x47, 0x85, 0x00, 0x60, 0xFE),
+		PANEL_DCS(0x1C, 0x80),
+		PANEL_DCS(0x2B, 0x12, 0x01, 0x00, 0x80),
+		PANEL_DCS(0x2F, 0x02),
+		PANEL_DCS(0x30, 0x01),
+		PANEL_DCS(0x31, 0x52),
+		PANEL_DCS(0x37, 0x22),
+		PANEL_DCS(0x3B, 0x59),
+		PANEL_DCS(0x3D, 0x02),
+		PANEL_DCS(0x3F, 0x0C),
+		PANEL_DCS(0x40, 0x04),
+		PANEL_DCS(0x41, 0x52),
+		PANEL_DCS(0x47, 0x24),
+		PANEL_DCS(0x4B, 0x51),
+		PANEL_DCS(0x4C, 0x01),
+		PANEL_DCS(0x50, 0x87),
+		PANEL_DCS(0x55, 0x0B, 0x03),
+		PANEL_DCS(0x56, 0x04),
+		PANEL_DCS(0x58, 0x10),
+		PANEL_DCS(0x59, 0x10),
+		PANEL_DCS(0x5A, 0x03),
+		PANEL_DCS(0x5B, 0x55),
+		PANEL_DCS(0x5E, 0x00, 0x0B),
+		PANEL_DCS(0x60, 0x81, 0xB6),
+		PANEL_DCS(0x61, 0x8E),
+		PANEL_DCS(0x67, 0x21),
+		PANEL_DCS(0x68, 0x43),
+		PANEL_DCS(0x71, 0x04),
+		PANEL_DCS(0x7E, 0x20),
+		PANEL_DCS(0x7F, 0xE1),
+		PANEL_DCS(0x92, 0x5C, 0x00, 0xF5, 0x7B),
+		PANEL_DCS(0x93, 0x3C, 0x00, 0x42, 0x00, 0x2C, 0x00),
+		PANEL_DCS(0x94, 0xBE, 0x00, 0x14, 0x98),
+		PANEL_DCS(0x95, 0x09),
+		PANEL_DCS(0x96, 0x80, 0xAA, 0x00),
+		PANEL_DCS(0x97, 0xC0),
+		PANEL_DCS(0x9A, 0x0B),
+		PANEL_DCS(0xA4, 0x00, 0x17),
+		PANEL_DCS(0xAA, 0xA3, 0xA3, 0x28),
+		PANEL_DCS(0xB6, 0x08, 0x08, 0x00),
+		PANEL_DCS(0xBC, 0x00, 0x00, 0x43, 0x22),
+		PANEL_DCS(0xC2, 0xCC, 0x00, 0x01, 0x00),
+		PANEL_DCS(0xD4, 0x03),
+		PANEL_DCS(0xD6, 0x46),
+		PANEL_DCS(0xD7, 0x25),
+		PANEL_DCS(0xD9, 0x21),
+		PANEL_DCS(0xDB, 0x34),
+		PANEL_DCS(0xDC, 0xA0),
+		PANEL_DCS(0xDD, 0x33),
+		PANEL_DCS(0xDE, 0x07, 0x00, 0x00, 0x00),
+		PANEL_DCS(0xDF, 0x04),
+		PANEL_DCS(0xE0, 0xA0),
+		PANEL_DCS(0xE1, 0x04),
+		PANEL_DCS(0xE2, 0xA0),
+		PANEL_DCS(0xE3, 0x04),
+		PANEL_DCS(0xE4, 0xA0),
+		PANEL_DCS(0xE5, 0x04),
+		PANEL_DCS(0xE6, 0xA0),
+		PANEL_DCS(0xE7, 0x03),
+		PANEL_DCS(0xE9, 0x04),
+		PANEL_DCS(0xEA, 0xA0),
+		PANEL_DCS(0xEB, 0x04),
+		PANEL_DCS(0xEC, 0x81),
+		PANEL_DCS(0xEE, 0xA0),
+		PANEL_DCS(0xEF, 0x04),
+		PANEL_DCS(0xF0, 0xA0),
+		PANEL_DCS(0xF1, 0x23),
+		PANEL_DCS(0xF2, 0x23),
+		PANEL_DCS(0xF3, 0x23),
+		PANEL_DCS(0xF4, 0x22),
+		PANEL_DCS(0xF5, 0x23),
+		PANEL_DCS(0xF6, 0x23),
+		PANEL_DCS(0xFF, 0x25),
+		PANEL_DCS(0xFB, 0x01),
+		PANEL_DCS(0x10, 0x00, 0x02, 0x53, 0x00),
+		PANEL_DCS(0x13, 0x01),
+		PANEL_DCS(0x14, 0xEB),
+		PANEL_DCS(0x15, 0x01),
+		PANEL_DCS(0x16, 0xB7),
+		PANEL_DCS(0x1F, 0x03),
+		PANEL_DCS(0x20, 0x55),
+		PANEL_DCS(0x24, 0x12),
+		PANEL_DCS(0x26, 0x03),
+		PANEL_DCS(0x27, 0x55),
+		PANEL_DCS(0x2B, 0x12),
+		PANEL_DCS(0x31, 0x20),
+		PANEL_DCS(0x33, 0x03),
+		PANEL_DCS(0x34, 0x55),
+		PANEL_DCS(0x38, 0x12),
+		PANEL_DCS(0x39, 0x08),
+		PANEL_DCS(0x3A, 0x02),
+		PANEL_DCS(0x3F, 0x20),
+		PANEL_DCS(0x40, 0x00),
+		PANEL_DCS(0x42, 0x0B),
+		PANEL_DCS(0x45, 0x59),
+		PANEL_DCS(0x47, 0x51),
+		PANEL_DCS(0x48, 0x03),
+		PANEL_DCS(0x49, 0x55),
+		PANEL_DCS(0x4D, 0x12),
+		PANEL_DCS(0x4E, 0x08),
+		PANEL_DCS(0x50, 0x03),
+		PANEL_DCS(0x51, 0x55),
+		PANEL_DCS(0x55, 0x12),
+		PANEL_DCS(0x56, 0x08),
+		PANEL_DCS(0x5B, 0xA0),
+		PANEL_DCS(0x5E, 0x59),
+		PANEL_DCS(0x60, 0x51),
+		PANEL_DCS(0x61, 0x03),
+		PANEL_DCS(0x62, 0x55),
+		PANEL_DCS(0x66, 0x12),
+		PANEL_DCS(0x67, 0x08),
+		PANEL_DCS(0x68, 0x0B),
+		PANEL_DCS(0x6A, 0x02),
+		PANEL_DCS(0x6B, 0x44),
+		PANEL_DCS(0x6C, 0x0E),
+		PANEL_DCS(0x6E, 0x1A),
+		PANEL_DCS(0x7B, 0x58),
+		PANEL_DCS(0x7F, 0x58),
+		PANEL_DCS(0x83, 0x58),
+		PANEL_DCS(0xBC, 0x02),
+		PANEL_DCS(0xBD, 0x9E),
+		PANEL_DCS(0xC6, 0x10),
+		PANEL_DCS(0xDC, 0xD0),
+		PANEL_DCS(0xDD, 0x02),
+		PANEL_DCS(0xDE, 0x83),
+		PANEL_DCS(0xEE, 0x1B),
+		PANEL_DCS(0xF6, 0x03),
+		PANEL_DCS(0xF7, 0xD6),
+		PANEL_DCS(0xF8, 0x0E, 0x00, 0x1A, 0x00),
+		PANEL_DCS(0xF9, 0x0E, 0x00, 0x1A, 0x00),
+		PANEL_DCS(0xFF, 0x26),
+		PANEL_DCS(0xFB, 0x01),
+		PANEL_DCS(0x04, 0x68),
+		PANEL_DCS(0x06, 0x01, 0x64, 0x1E),
+		PANEL_DCS(0x0A, 0x03),
+		PANEL_DCS(0x0C, 0x06),
+		PANEL_DCS(0x0D, 0x06),
+		PANEL_DCS(0x0F, 0x00),
+		PANEL_DCS(0x12, 0x51),
+		PANEL_DCS(0x13, 0x3A),
+		PANEL_DCS(0x14, 0x32),
+		PANEL_DCS(0x16, 0x01),
+		PANEL_DCS(0x19, 0x20, 0x1F, 0x20, 0x20),
+		PANEL_DCS(0x1A, 0xC4, 0xD0, 0xC4, 0xC4),
+		PANEL_DCS(0x1B, 0x1E, 0x1D, 0x1E, 0x1E),
+		PANEL_DCS(0x1C, 0xD6, 0xEB, 0xD6, 0xD6),
+		PANEL_DCS(0x1D, 0x00),
+		PANEL_DCS(0x1E, 0x5C),
+		PANEL_DCS(0x1F, 0x5C),
+		PANEL_DCS(0x24, 0x02),
+		PANEL_DCS(0x25, 0x5C),
+		PANEL_DCS(0x26, 0x26),
+		PANEL_DCS(0x27, 0x22),
+		PANEL_DCS(0x28, 0x22),
+		PANEL_DCS(0x29, 0x02),
+		PANEL_DCS(0x2A, 0x1F, 0x1E, 0x1F, 0x1F),
+		PANEL_DCS(0x2B, 0x42, 0x57, 0x42, 0x42),
+		PANEL_DCS(0x2F, 0x0B),
+		PANEL_DCS(0x30, 0x5C),
+		PANEL_DCS(0x32, 0x5C),
+		PANEL_DCS(0x33, 0x22),
+		PANEL_DCS(0x34, 0x92),
+		PANEL_DCS(0x35, 0x78),
+		PANEL_DCS(0x36, 0x96),
+		PANEL_DCS(0x37, 0x78),
+		PANEL_DCS(0x38, 0x16, 0x11, 0x01),
+		PANEL_DCS(0x3A, 0x5C),
+		PANEL_DCS(0x3D, 0x00, 0x00, 0x2A, 0x20, 0x00, 0x00),
+		PANEL_DCS(0x40, 0x57, 0x6E),
+		PANEL_DCS(0x41, 0x57),
+		PANEL_DCS(0x42, 0x57),
+		PANEL_DCS(0x43, 0x02),
+		PANEL_DCS(0x44, 0x57),
+		PANEL_DCS(0x45, 0x0B),
+		PANEL_DCS(0x46, 0x57),
+		PANEL_DCS(0x48, 0x57),
+		PANEL_DCS(0x4A, 0x57),
+		PANEL_DCS(0x4D, 0x02),
+		PANEL_DCS(0x4E, 0x54),
+		PANEL_DCS(0x4F, 0x02),
+		PANEL_DCS(0x50, 0x4C),
+		PANEL_DCS(0x51, 0x03),
+		PANEL_DCS(0x53, 0x02),
+		PANEL_DCS(0x54, 0x72),
+		PANEL_DCS(0x56, 0x03),
+		PANEL_DCS(0x59, 0x02),
+		PANEL_DCS(0x5A, 0x72),
+		PANEL_DCS(0x5B, 0x03),
+		PANEL_DCS(0x5D, 0x02),
+		PANEL_DCS(0x5E, 0x72),
+		PANEL_DCS(0x60, 0x03),
+		PANEL_DCS(0x61, 0x50),
+		PANEL_DCS(0x63, 0x72),
+		PANEL_DCS(0x64, 0x03),
+		PANEL_DCS(0x65, 0x50),
+		PANEL_DCS(0x67, 0x72),
+		PANEL_DCS(0x69, 0x03),
+		PANEL_DCS(0x6A, 0x50),
+		PANEL_DCS(0x6B, 0x02),
+		PANEL_DCS(0x6C, 0x72),
+		PANEL_DCS(0x6E, 0x02),
+		PANEL_DCS(0x6F, 0x54),
+		PANEL_DCS(0x70, 0x02),
+		PANEL_DCS(0x71, 0x4C),
+		PANEL_DCS(0x72, 0x03),
+		PANEL_DCS(0x74, 0x02),
+		PANEL_DCS(0x75, 0x72),
+		PANEL_DCS(0x7B, 0x02),
+		PANEL_DCS(0x7C, 0x54),
+		PANEL_DCS(0x7E, 0x02),
+		PANEL_DCS(0x7F, 0x4C),
+		PANEL_DCS(0x80, 0x66),
+		PANEL_DCS(0x81, 0x66),
+		PANEL_DCS(0x82, 0x00, 0x64, 0x64, 0x64),
+		PANEL_DCS(0x84, 0x14, 0x14, 0x14),
+		PANEL_DCS(0x85, 0x1A, 0x1A, 0x1A),
+		PANEL_DCS(0x8B, 0x74),
+		PANEL_DCS(0x8C, 0x08),
+		PANEL_DCS(0x8D, 0x00),
+		PANEL_DCS(0x8F, 0x00),
+		PANEL_DCS(0x91, 0x07),
+		PANEL_DCS(0x93, 0xF5),
+		PANEL_DCS(0x94, 0xE6),
+		PANEL_DCS(0x96, 0x10),
+		PANEL_DCS(0x99, 0x10, 0x0F, 0x10, 0x10),
+		PANEL_DCS(0x9A, 0xF5, 0x4C, 0xF5, 0xF5),
+		PANEL_DCS(0x9B, 0x0F, 0x0E, 0x0F, 0x0F),
+		PANEL_DCS(0x9C, 0x7C, 0x3D, 0x7C, 0x7C),
+		PANEL_DCS(0x9D, 0x0F, 0x0E, 0x0F, 0x0F),
+		PANEL_DCS(0x9E, 0xE8, 0xA9, 0xE8, 0xE8),
+		PANEL_DCS(0xA7, 0x01),
+		PANEL_DCS(0xC9, 0x1E, 0x00),
+		PANEL_DCS(0xCD, 0x1F, 0x97, 0x00),
+		PANEL_DCS(0xCE, 0x1D, 0x97, 0x00),
+		PANEL_DCS(0xCF, 0xFF, 0x00, 0x00),
+		PANEL_DCS(0xD2, 0x2D),
+		PANEL_DCS(0xD3, 0x12),
+		PANEL_DCS(0xFF, 0x27),
+		PANEL_DCS(0xFB, 0x01),
+		PANEL_DCS(0x00, 0x80),
+		PANEL_DCS(0x01, 0x36),
+		PANEL_DCS(0x03, 0x96),
+		PANEL_DCS(0x05, 0x04),
+		PANEL_DCS(0x06, 0x00),
+		PANEL_DCS(0x07, 0x04),
+		PANEL_DCS(0x08, 0x6A, 0x06),
+		PANEL_DCS(0x09, 0x48, 0x00),
+		PANEL_DCS(0x0A, 0x66, 0x00),
+		PANEL_DCS(0x0B, 0x30, 0x00),
+		PANEL_DCS(0x0C, 0x26, 0x00),
+		PANEL_DCS(0x0D, 0x46, 0x00),
+		PANEL_DCS(0x0E, 0x66, 0x00),
+		PANEL_DCS(0x0F, 0x30, 0x00),
+		PANEL_DCS(0x10, 0x26, 0x00),
+		PANEL_DCS(0x11, 0x80),
+		PANEL_DCS(0x13, 0x06),
+		PANEL_DCS(0x31, 0x2A, 0x00),
+		PANEL_DCS(0x58, 0x80),
+		PANEL_DCS(0x59, 0x00),
+		PANEL_DCS(0x5B, 0xB8),
+		PANEL_DCS(0x5E, 0x2A),
+		PANEL_DCS(0x5F, 0x00),
+		PANEL_DCS(0x61, 0x00, 0x00),
+		PANEL_DCS(0x63, 0x00, 0x00),
+		PANEL_DCS(0x64, 0x00, 0x00),
+		PANEL_DCS(0x65, 0x00, 0x00),
+		PANEL_DCS(0x67, 0x00, 0x00),
+		PANEL_DCS(0x68, 0x00, 0x00),
+		PANEL_DCS(0x69, 0x80),
+		PANEL_DCS(0x77, 0x2A, 0x00),
+		PANEL_DCS(0x78, 0x80),
+		PANEL_DCS(0x79, 0xA4),
+		PANEL_DCS(0x7A, 0x00),
+		PANEL_DCS(0x7B, 0x01),
+		PANEL_DCS(0x7D, 0x04),
+		PANEL_DCS(0x7E, 0x00),
+		PANEL_DCS(0x7F, 0x04),
+		PANEL_DCS(0x80, 0x7E, 0x0A),
+		PANEL_DCS(0x81, 0x59, 0x00),
+		PANEL_DCS(0x82, 0xFE, 0x00),
+		PANEL_DCS(0x83, 0x23, 0x00),
+		PANEL_DCS(0x84, 0x32, 0x00),
+		PANEL_DCS(0x85, 0x56, 0x00),
+		PANEL_DCS(0x86, 0xFE, 0x00),
+		PANEL_DCS(0x87, 0x23, 0x00),
+		PANEL_DCS(0x88, 0x32, 0x00),
+		PANEL_DCS(0x89, 0x80),
+		PANEL_DCS(0x97, 0x2A, 0x00),
+		PANEL_DCS(0xD1, 0x02, 0x00),
+		PANEL_DCS(0xFF, 0x2A),
+		PANEL_DCS(0xFB, 0x01),
+		PANEL_DCS(0x00, 0x13),
+		PANEL_DCS(0x01, 0x04),
+		PANEL_DCS(0x02, 0x44),
+		PANEL_DCS(0x03, 0x04),
+		PANEL_DCS(0x04, 0x64),
+		PANEL_DCS(0x05, 0x04),
+		PANEL_DCS(0x06, 0x64),
+		PANEL_DCS(0x08, 0x04),
+		PANEL_DCS(0x09, 0x64),
+		PANEL_DCS(0x0A, 0x04),
+		PANEL_DCS(0x0B, 0x64),
+		PANEL_DCS(0x0C, 0x04),
+		PANEL_DCS(0x0D, 0x64),
+		PANEL_DCS(0x0E, 0x23),
+		PANEL_DCS(0x0F, 0x23),
+		PANEL_DCS(0x10, 0x23),
+		PANEL_DCS(0x11, 0x23),
+		PANEL_DCS(0x12, 0x23),
+		PANEL_DCS(0x13, 0x23),
+		PANEL_DCS(0x16, 0x14),
+		PANEL_DCS(0x18, 0x14),
+		PANEL_DCS(0x1A, 0x14),
+		PANEL_DCS(0x1C, 0x14),
+		PANEL_DCS(0x1D, 0x06),
+		PANEL_DCS(0x27, 0x5F),
+		PANEL_DCS(0x28, 0x78),
+		PANEL_DCS(0x2F, 0x44, 0x21, 0x02),
+		PANEL_DCS(0x30, 0x03),
+		PANEL_DCS(0x32, 0x74),
+		PANEL_DCS(0x33, 0x91),
+		PANEL_DCS(0x40, 0x79, 0x79, 0x79, 0x79, 0x79, 0x79, 0x00, 0x79, 0x79, 0x79,
+			  0x79, 0x79, 0x79, 0x00),
+		PANEL_DCS(0x41, 0xA0, 0xA0, 0xA0, 0xA0, 0xA0, 0xA0, 0xA0, 0xA0, 0x00),
+		PANEL_DCS(0x42, 0x26, 0x26, 0x26, 0x26, 0x26, 0x26, 0x00, 0x26, 0x26, 0x26,
+			  0x26, 0x26, 0x26, 0x00),
+		PANEL_DCS(0x43, 0x64, 0x64, 0x64, 0x64, 0x64, 0x64, 0x64, 0x64, 0x00),
+		PANEL_DCS(0x44, 0x31, 0x31, 0x31, 0x31, 0x31, 0x31, 0x00, 0x31, 0x31, 0x31,
+			  0x31, 0x31, 0x31, 0x00),
+		PANEL_DCS(0x4B, 0x00, 0x00, 0xFF, 0x00, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00,
+			  0xFF, 0x00, 0xFF, 0x00, 0xFF),
+		PANEL_DCS(0x59, 0x00, 0x02, 0x00, 0x40),
+		PANEL_DCS(0x5C, 0x13),
+		PANEL_DCS(0x63, 0x22, 0x72, 0x86, 0x67, 0x78, 0x16, 0x11, 0x01),
+		PANEL_DCS(0x64, 0x96),
+		PANEL_DCS(0x66, 0x01),
+		PANEL_DCS(0x67, 0x9E),
+		PANEL_DCS(0x68, 0x00),
+		PANEL_DCS(0x69, 0x01),
+		PANEL_DCS(0x6A, 0x9E),
+		PANEL_DCS(0x6B, 0x00),
+		PANEL_DCS(0x6C, 0x01),
+		PANEL_DCS(0x7F, 0x96),
+		PANEL_DCS(0x81, 0x01),
+		PANEL_DCS(0x82, 0x96),
+		PANEL_DCS(0x84, 0x01),
+		PANEL_DCS(0x88, 0x9E),
+		PANEL_DCS(0x89, 0x00),
+		PANEL_DCS(0x8A, 0x01),
+		PANEL_DCS(0x8B, 0x16),
+		PANEL_DCS(0x8C, 0x00),
+		PANEL_DCS(0x8D, 0x00),
+		PANEL_DCS(0x8E, 0x16),
+		PANEL_DCS(0x8F, 0x00),
+		PANEL_DCS(0x90, 0x00),
+		PANEL_DCS(0x92, 0x00),
+		PANEL_DCS(0x93, 0x01),
+		PANEL_DCS(0x94, 0x06),
+		PANEL_DCS(0x99, 0x91),
+		PANEL_DCS(0x9A, 0x05),
+		PANEL_DCS(0xA2, 0x3F, 0x00),
+		PANEL_DCS(0xA4, 0x0F, 0x00),
+		PANEL_DCS(0xA5, 0xC3, 0x00),
+		PANEL_DCS(0xA9, 0x21),
+		PANEL_DCS(0xB1, 0x00, 0x01),
+		PANEL_DCS(0xB3, 0x16, 0x00, 0x00),
+		PANEL_DCS(0xB6, 0x00, 0xFF, 0xFF, 0x00, 0x00, 0x77, 0x77, 0x00, 0x00, 0x00),
+		PANEL_DCS(0xB9, 0xA0, 0x06, 0x40, 0x04, 0x5F, 0x41, 0x89, 0xEC, 0x89, 0xEC,
+			  0x55, 0x10, 0x40, 0x80, 0x40, 0x40),
+		PANEL_DCS(0xBC, 0x77, 0x07),
+		PANEL_DCS(0xC4, 0x22),
+		PANEL_DCS(0xC6, 0x12),
+		PANEL_DCS(0xC7, 0x73),
+		PANEL_DCS(0xC8, 0x08),
+		PANEL_DCS(0xCA, 0x01),
+		PANEL_DCS(0xCB, 0x11, 0x00, 0x00, 0x00),
+		PANEL_DCS(0xCC, 0x11, 0x33, 0x22, 0x44, 0x33, 0x11, 0x22, 0x44, 0x11, 0x33,
+			  0x22, 0x44, 0x33, 0x11, 0x22, 0x44),
+		PANEL_DCS(0xD0, 0x04),
+		PANEL_DCS(0xD1, 0x01),
+		PANEL_DCS(0xE4, 0x01),
+		PANEL_DCS(0xF4, 0x91),
+		PANEL_DCS(0xF5, 0x05),
+		PANEL_DCS(0xFF, 0xE0),
+		PANEL_DCS(0xFB, 0x01),
+		PANEL_DCS(0xBB, 0x00),
+		PANEL_DCS(0xFF, 0xF0),
+		PANEL_DCS(0xFB, 0x01),
+		PANEL_DCS(0xE6, 0x02),
+		PANEL_DCS(0xFF, 0x10),
+		PANEL_DCS(0xFB, 0x01),
+		PANEL_DCS(0x3B, 0x03, 0xBE, 0x3C, 0x04, 0x04, 0x00, 0x80, 0x14, 0x98),
+		PANEL_DCS(0x60, 0x00),
+		PANEL_DCS(0x90, 0x03, 0x00),
+		PANEL_DCS(0x91, 0xAB, 0xA8, 0x00, 0x1E, 0xD2, 0x00, 0x00, 0x00, 0x03, 0x68,
+			  0x00, 0x0C, 0x03, 0x97, 0x02, 0x17),
+		PANEL_DCS(0x92, 0x10, 0xF0),
+		PANEL_DCS(0xB2, 0x91, 0x80),
+		PANEL_DCS(0xB3, 0x40),
+
+		PANEL_DCS(0x11),
+		PANEL_DELAY(120),
+
+		PANEL_DCS(0x29),
+		PANEL_END,
+	},
+	.dsc_config = {
+		.dsc_version_major = 0x1,
+		.dsc_version_minor = 0x2,
+		.bits_per_component = 0xa,
+		.line_buf_depth = 0xb,
+		.block_pred_enable = true,
+		.convert_rgb = 1,
+		.simple_422 = false,
+		.bits_per_pixel = 8 << 4,
+		.pic_height = 2190,
+		.pic_width = 3504,
+		.slice_height = 30,
+		.slice_width = 876,
+		.slice_chunk_size = 876,
+		.initial_xmit_delay = 512,
+		.initial_dec_delay = 731,
+		.initial_scale_value = 32,
+		.scale_increment_interval = 872,
+		.scale_decrement_interval = 12,
+		.first_line_bpg_offset = 13,
+		.nfl_bpg_offset = 919,
+		.slice_bpg_offset = 535,
+		.initial_offset = 6144,
+		.final_offset = 4336,
+		.flatness_min_qp = 7,
+		.flatness_max_qp = 16,
+		.rc_model_size = 8192,
+		.rc_edge_factor = 6,
+		.rc_quant_incr_limit0 = 15,
+		.rc_quant_incr_limit1 = 15,
+		.rc_tgt_offset_high = 3,
+		.rc_tgt_offset_low = 3,
+		.rc_buf_thresh = { 14, 28, 42, 56, 70, 84, 98, 105,
+				   112, 119, 121, 123, 125, 126 },
+
+		.rc_range_params = {
+			[0] = { .range_min_qp = 0,  .range_max_qp = 8,
+				 .range_bpg_offset = 2 },
+			[1] = { .range_min_qp = 4,  .range_max_qp = 8,
+				 .range_bpg_offset = 0 },
+			[2] = { .range_min_qp = 5,  .range_max_qp = 9,
+				 .range_bpg_offset = 0 },
+			[3] = { .range_min_qp = 5,  .range_max_qp = 10,
+				 .range_bpg_offset = -2 },
+			[4] = { .range_min_qp = 7,  .range_max_qp = 11,
+				 .range_bpg_offset = -4 },
+			[5] = { .range_min_qp = 7,  .range_max_qp = 11,
+				 .range_bpg_offset = -6 },
+			[6] = { .range_min_qp = 7,  .range_max_qp = 11,
+				 .range_bpg_offset = -8 },
+			[7] = { .range_min_qp = 7,  .range_max_qp = 12,
+				 .range_bpg_offset = -8 },
+			[8] = { .range_min_qp = 7,  .range_max_qp = 13,
+				 .range_bpg_offset = -8 },
+			[9] = { .range_min_qp = 7,  .range_max_qp = 14,
+				 .range_bpg_offset = -10 },
+			[10] = { .range_min_qp = 9,  .range_max_qp = 14,
+				 .range_bpg_offset = -10 },
+			[11] = { .range_min_qp = 9,  .range_max_qp = 15,
+				 .range_bpg_offset = -12 },
+			[12] = { .range_min_qp = 9,  .range_max_qp = 15,
+				 .range_bpg_offset = -12 },
+			[13] = { .range_min_qp = 13, .range_max_qp = 16,
+				 .range_bpg_offset = -12 },
+			[14] = { .range_min_qp = 16, .range_max_qp = 17,
+				 .range_bpg_offset = -12 },
+		}
+	},
+};

From 5807b59fc56ae57fd11628c9a736a49895dad7f5 Mon Sep 17 00:00:00 2001
From: Wentao Qin <qinwentao@huaqin.corp-partner.google.com>
Date: Mon, 24 Nov 2025 23:25:01 +0800
Subject: [PATCH 2662/3886] mb/google/rauru: Report panel ID for sapphire

The panel id is sampled with AUXADC_VIN3 (PANEL_ID_HIGH_CHANNEL)
and AUXADC_VIN4 (PANEL_ID_LOW_CHANNEL).

    [DEBUG]  ADC[2]: Raw value=1744 ID=7
    [DEBUG]  ADC[3]: Raw value=283 ID=1
    [DEBUG]  Panel ID: 0x9

BUG=b:448281461
TEST=build and check the CBFS include the panel ID
BRANCH=none

Change-Id: I3b010162bb5b892d528c74e2d38e624465fa90dc
Signed-off-by: Wentao Qin <qinwentao@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90190
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Chen-Tsung Hsieh <chentsung@google.com>
---
 src/mainboard/google/rauru/boardid.c | 29 ++++++++++++++++++++++++++--
 src/mainboard/google/rauru/panel.h   |  2 ++
 2 files changed, 29 insertions(+), 2 deletions(-)

diff --git a/src/mainboard/google/rauru/boardid.c b/src/mainboard/google/rauru/boardid.c
index 6f04c04901..09194f5c0d 100644
--- a/src/mainboard/google/rauru/boardid.c
+++ b/src/mainboard/google/rauru/boardid.c
@@ -7,6 +7,7 @@
 #include <ec/google/chromeec/ec.h>
 #include <soc/mt6363_sdmadc.h>
 
+#include "panel.h"
 #include "storage.h"
 
 #define ADC_LEVELS 8
@@ -18,9 +19,12 @@ DEFINE_BITFIELD(PANEL_TYPE, 7, 0);
 enum {
 	/* Storage IDs */
 	STORAGE_ID_LOW_CHANNEL = AUXADC_CHAN_VIN1,
+	/* Panel IDS */
+	PANEL_ID0_CHANNEL = AUXADC_CHAN_VIN3,
+	PANEL_ID1_CHANNEL = AUXADC_CHAN_VIN4,
 };
 
-static const unsigned int storageid_voltages[ADC_LEVELS] = {
+static const unsigned int id_voltages[ADC_LEVELS] = {
 	/* ID : Voltage (unit: mV) */
 	[0]  =   50,
 	[1]  =  210,
@@ -33,7 +37,9 @@ static const unsigned int storageid_voltages[ADC_LEVELS] = {
 };
 
 static const unsigned int *adc_voltages[] = {
-	[STORAGE_ID_LOW_CHANNEL] = storageid_voltages,
+	[STORAGE_ID_LOW_CHANNEL] = id_voltages,
+	[PANEL_ID0_CHANNEL] = id_voltages,
+	[PANEL_ID1_CHANNEL] = id_voltages,
 };
 
 static uint32_t get_adc_index(unsigned int channel)
@@ -55,6 +61,25 @@ static uint32_t get_adc_index(unsigned int channel)
 	return id;
 }
 
+uint32_t panel_id(void)
+{
+	static uint32_t cached_panel_id = BOARD_ID_INIT;
+
+	if (cached_panel_id != BOARD_ID_INIT)
+		return cached_panel_id;
+
+	uint32_t id0 = get_adc_index(PANEL_ID0_CHANNEL);
+	uint32_t id1 = get_adc_index(PANEL_ID1_CHANNEL);
+
+	if (id0 && id0 != 0x7)
+		printk(BIOS_ERR, "Invalid Panel ID0: %#02x\n", id0);
+
+	cached_panel_id = (!!id0) << 3 | (id1 & 0x7);
+	printk(BIOS_DEBUG, "Panel ID: %#02x\n", cached_panel_id);
+
+	return cached_panel_id;
+}
+
 uint32_t storage_id(void)
 {
 	static uint32_t cached_storage_id = BOARD_ID_INIT;
diff --git a/src/mainboard/google/rauru/panel.h b/src/mainboard/google/rauru/panel.h
index 0fa2877789..9909cad06e 100644
--- a/src/mainboard/google/rauru/panel.h
+++ b/src/mainboard/google/rauru/panel.h
@@ -5,4 +5,6 @@
 
 #include <soc/display.h>
 
+uint32_t panel_id(void);
+
 #endif /* __MAINBOARD_GOOGLE_RAURU_PANEL_H__ */

From 36632a08a883a2fe53d76e271e919cb11805e55e Mon Sep 17 00:00:00 2001
From: Swathi Tamilselvan <tswathi@qualcomm.corp-partner.google.com>
Date: Tue, 25 Nov 2025 11:55:44 +0530
Subject: [PATCH 2663/3886] soc/qualcomm/x1p42100: Reserve 33 MB DRAM memory
 for Display requirement

Add support to reserve 33 MB DRAM memory for display in memlayout.ld
file.

TEST=Create an image.serial.bin and ensure it boots on X1P42100.
Basic device boot functionality with the specified memory reservation
has been validated. Display functionality has not yet been tested, as
the display driver porting is yet to be done.

Change-Id: I49a4a20b9869bc5cf0b11f4eb6cff7865bb2e761
Signed-off-by: Swathi Tamilselvan <tswathi@qualcomm.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90242
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/soc/qualcomm/common/include/soc/symbols_common.h | 1 +
 src/soc/qualcomm/x1p42100/memlayout.ld               | 7 ++++++-
 src/soc/qualcomm/x1p42100/soc.c                      | 1 +
 3 files changed, 8 insertions(+), 1 deletion(-)

diff --git a/src/soc/qualcomm/common/include/soc/symbols_common.h b/src/soc/qualcomm/common/include/soc/symbols_common.h
index 7df10ecde2..f679a6a2ab 100644
--- a/src/soc/qualcomm/common/include/soc/symbols_common.h
+++ b/src/soc/qualcomm/common/include/soc/symbols_common.h
@@ -45,6 +45,7 @@ DECLARE_REGION(dram_llcc_lpi)
 DECLARE_REGION(dram_ta)
 DECLARE_REGION(dram_pdp)
 DECLARE_REGION(dram_pil)
+DECLARE_REGION(dram_display)
 
 /*
  * DDR_SPACE (2 GB) aka `_dram`:  0x80000000 - 0x100000000
diff --git a/src/soc/qualcomm/x1p42100/memlayout.ld b/src/soc/qualcomm/x1p42100/memlayout.ld
index c93ed62462..3cb7506668 100644
--- a/src/soc/qualcomm/x1p42100/memlayout.ld
+++ b/src/soc/qualcomm/x1p42100/memlayout.ld
@@ -26,7 +26,11 @@
  *               |                       dram_acdb                          |      |        |
  *               +----------------------------------------------------------+      |        |
  *               |                ... Usable memory ...                     |      |        |
- * 0xDF4C0000    +----------------------------------------------------------+      |        |
+ * 0xE69C0000    +----------------------------------------------------------+      |        |
+ *               |                     dram_display                         |      |        |
+ * 0xE4800000    +----------------------------------------------------------+      |        |
+ *               |                ... Usable memory ...                     |      |        |
+ * 0xD9600000    +----------------------------------------------------------+      |        |
  *               |                       dram_ta                            |      |        |
  * 0xD8600000    +----------------------------------------------------------+      |        |
  *               |                 BL31 (ARM Trusted Firmware)              |      |        |
@@ -237,6 +241,7 @@ SECTIONS
 	REGION(dram_tz, 0xD8000000, 0x56A000, 4K)
 	BL31(0xD856A000, 600K)
 	REGION(dram_ta, 0xD8600000, 0x1000000, 4K)
+	REGION(dram_display, 0xE4800000, 0x21C0000, 4K)
 	REGION(dram_llcc_lpi, 0xFF800000, 0x600000, 4K)
 	REGION(dram_smem, 0xFFE00000, 0x200000, 4K)
 	DRAM_END(0x100000000)
diff --git a/src/soc/qualcomm/x1p42100/soc.c b/src/soc/qualcomm/x1p42100/soc.c
index d4fdb87396..b4afd98139 100644
--- a/src/soc/qualcomm/x1p42100/soc.c
+++ b/src/soc/qualcomm/x1p42100/soc.c
@@ -49,6 +49,7 @@ static void soc_read_resources(struct device *dev)
 	reserved_ram_range(dev, index++, (uintptr_t)_dram_wlan, REGION_SIZE(dram_wlan));
 	reserved_ram_range(dev, index++, (uintptr_t)_dram_pil, REGION_SIZE(dram_pil));
 	reserved_ram_range(dev, index++, (uintptr_t)_dram_ta, REGION_SIZE(dram_ta));
+	reserved_ram_range(dev, index++, (uintptr_t)_dram_display, REGION_SIZE(dram_display));
 
 	/* ACDB carveout region located at 0xFF800000 - (n*5.5 +1+32+3) where n is size of DDR */
 	reserved_ram_range(dev, index++, (uintptr_t)(_dram_llcc_lpi - calc_acdb_carveout_size()),

From 2e96a71e6f9b306869a4c6fca6ae40506fc9727e Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Mon, 10 Nov 2025 21:34:50 +0000
Subject: [PATCH 2664/3886] drivers/intel/gma: Cache brightness level

Cache the brightness level requested via _BCM and return it from XBQC
while the IGD OpRegion registers are still zeroed during S3 resume.
Once BCLM is valid we refresh the cache with the hardware reading.
This keeps _BQC from reporting zero after resume.

Change-Id: I3f06c9cf6529da6d634d7b0368f0c88b468f0c45
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89986
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
---
 .../gma/acpi/configure_brightness_levels.asl    | 17 +++++++++++++----
 1 file changed, 13 insertions(+), 4 deletions(-)

diff --git a/src/drivers/intel/gma/acpi/configure_brightness_levels.asl b/src/drivers/intel/gma/acpi/configure_brightness_levels.asl
index b6c27fbe92..92ffbcbe55 100644
--- a/src/drivers/intel/gma/acpi/configure_brightness_levels.asl
+++ b/src/drivers/intel/gma/acpi/configure_brightness_levels.asl
@@ -1,5 +1,6 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
+	Name (BRLV, 100)
 	/*
 	 * Pseudo device that contains methods to modify Opregion
 	 * "Mailbox 3 BIOS to Driver Notification"
@@ -147,6 +148,7 @@
 
 	Method (XBCM, 1, NotSerialized)
 	{
+		BRLV = Arg0
 		If (^BOX3.XBCM (Arg0) == Ones)
 		{
 			/*
@@ -163,9 +165,16 @@
 	Method (XBQC, 0, NotSerialized)
 	{
 		/*
-		 * Always query the hardware directly. Not all OS drivers
-		 * keep CBLV up to date (one is Linux' i915). Some years
-		 * after that is fixed we can probably use CBLV?
+		 * During early boot / resume the IGD driver has not yet populated
+		 * the OpRegion brightness fields (BCLM stays zero), so fall back to
+		 * the cached value we last exposed to the OS.
 		 */
-		Return (^LEGA.XBQC ())
+		If (BCLM == 0)
+		{
+			Return (BRLV)
+		}
+
+		Local0 = ^LEGA.XBQC ()
+		BRLV = Local0
+		Return (Local0)
 	}

From 2ad08f9d720710ba66701860e8188f4bf002b86d Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Mon, 10 Nov 2025 21:36:27 +0000
Subject: [PATCH 2665/3886] drivers/intel/gma: Expose full brightness ladder
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Our 18-entry BRIG table advertised is only a handful of steps and
identical AC/DC defaults, so after S3, the OS falls back to the
default index if the the cached entry doesn't match.

Populate BRIG with the full 0–100 ladder so every cached index
corresponds to an actual entry.

Change-Id: I319cf3a0ced3bf6021f9e768f0e9bb5529b12ed5
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89987
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 .../gma/acpi/default_brightness_levels.asl    | 87 ++++++++++++++++++-
 1 file changed, 86 insertions(+), 1 deletion(-)

diff --git a/src/drivers/intel/gma/acpi/default_brightness_levels.asl b/src/drivers/intel/gma/acpi/default_brightness_levels.asl
index 9e8174109f..733b02284e 100644
--- a/src/drivers/intel/gma/acpi/default_brightness_levels.asl
+++ b/src/drivers/intel/gma/acpi/default_brightness_levels.asl
@@ -4,25 +4,110 @@
 
 Scope (GFX0)
 {
-	Name (BRIG, Package (0x12)
+	Name (BRIG, Package (103)
 	{
 		100, /* default AC */
 		100, /* default Battery */
+		  0,
+		  1,
 		  2,
+		  3,
 		  4,
 		  5,
+		  6,
 		  7,
+		  8,
 		  9,
+		 10,
 		 11,
+		 12,
 		 13,
+		 14,
+		 15,
+		 16,
+		 17,
 		 18,
+		 19,
 		 20,
+		 21,
+		 22,
+		 23,
 		 24,
+		 25,
+		 26,
+		 27,
+		 28,
 		 29,
+		 30,
+		 31,
+		 32,
 		 33,
+		 34,
+		 35,
+		 36,
+		 37,
+		 38,
+		 39,
 		 40,
+		 41,
+		 42,
+		 43,
+		 44,
+		 45,
+		 46,
+		 47,
+		 48,
+		 49,
 		 50,
+		 51,
+		 52,
+		 53,
+		 54,
+		 55,
+		 56,
+		 57,
+		 58,
+		 59,
+		 60,
+		 61,
+		 62,
+		 63,
+		 64,
+		 65,
+		 66,
 		 67,
+		 68,
+		 69,
+		 70,
+		 71,
+		 72,
+		 73,
+		 74,
+		 75,
+		 76,
+		 77,
+		 78,
+		 79,
+		 80,
+		 81,
+		 82,
+		 83,
+		 84,
+		 85,
+		 86,
+		 87,
+		 88,
+		 89,
+		 90,
+		 91,
+		 92,
+		 93,
+		 94,
+		 95,
+		 96,
+		 97,
+		 98,
+		 99,
 		100,
 	})
 }

From 2d78478345ef95625a798824a2310f8932696669 Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Thu, 13 Nov 2025 20:06:08 +0000
Subject: [PATCH 2666/3886] drivers/intel/gma: Reapply cached brightness once
 BCLM is valid

The OS replays _BCM requests while the graphics driver is
still reinitializing, so hardware brightness can diverge
from what we cached in BRLV. Reapply the cached level once
the OpRegion is ready to keep firmware and OS state aligned.

Change-Id: I2e6ed0936b2e74f55a2c760e7f4fcf56a2e02c53
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90029
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
---
 .../gma/acpi/configure_brightness_levels.asl    | 17 +++++++++++++++++
 1 file changed, 17 insertions(+)

diff --git a/src/drivers/intel/gma/acpi/configure_brightness_levels.asl b/src/drivers/intel/gma/acpi/configure_brightness_levels.asl
index 92ffbcbe55..9fb30f0039 100644
--- a/src/drivers/intel/gma/acpi/configure_brightness_levels.asl
+++ b/src/drivers/intel/gma/acpi/configure_brightness_levels.asl
@@ -175,6 +175,23 @@
 		}
 
 		Local0 = ^LEGA.XBQC ()
+		If (Local0 != BRLV)
+		{
+			/*
+			 * The OS replays _BCM requests while the graphics driver is
+			 * still reinitializing, so hardware brightness can diverge
+			 * from what we cached in BRLV. Reapply the cached level once
+			 * the OpRegion is ready to keep firmware and OS state aligned.
+			 * Use BRCT flag to prevent recursion.
+			 */
+			If (BRCT == 0)
+			{
+				BRCT = 1
+				XBCM (BRLV)
+				Local0 = ^LEGA.XBQC ()
+				BRCT = 0
+			}
+		}
 		BRLV = Local0
 		Return (Local0)
 	}

From bae5262c692174e40f9cb06a5ac514a652f8cc76 Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Sat, 29 Nov 2025 22:55:29 -0600
Subject: [PATCH 2667/3886] include/option: Add verstage stub for UEFI variable
 store backend

Verstage cannot use the UEFI variable store because it runs before
the SMMSTORE is initialized/available, and because the required EDK2
headers are x86-specific. Provide inline stub that returns fallback
values to satisfy console_init() dependency.

TEST=build google/dewatt with CFR enabled

Change-Id: Icaa493692006cf3e0bb194ee3fdd9caf2f51cda1
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90295
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
---
 src/include/option.h | 10 ++++++++--
 1 file changed, 8 insertions(+), 2 deletions(-)

diff --git a/src/include/option.h b/src/include/option.h
index bee761acfb..083af9552d 100644
--- a/src/include/option.h
+++ b/src/include/option.h
@@ -8,8 +8,14 @@
 void sanitize_cmos(void);
 
 /* The CBFS file option backend cannot be used in SMM due to vboot
- * dependencies, which are not added to SMM */
-#if CONFIG(OPTION_BACKEND_NONE) || (CONFIG(USE_CBFS_FILE_OPTION_BACKEND) && ENV_SMM)
+ * dependencies, which are not added to SMM.
+ * The UEFI variable store option backend cannot be used in verstage because:
+ * - Verstage runs before SMM is available (needed for SMMSTORE access)
+ * - EDK2 headers required for UEFI variables are x86-specific and not available
+ *   in ARM verstage (PSP verstage). */
+#if CONFIG(OPTION_BACKEND_NONE) || \
+	(CONFIG(USE_CBFS_FILE_OPTION_BACKEND) && ENV_SMM) || \
+	(CONFIG(USE_UEFI_VARIABLE_STORE) && ENV_SEPARATE_VERSTAGE)
 
 static inline unsigned int get_uint_option(const char *name, const unsigned int fallback)
 {

From b94a84a7922c428d277c829873e674ec12b38d2c Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Sat, 29 Nov 2025 22:54:11 -0600
Subject: [PATCH 2668/3886] drivers/efi: Exclude verstage from EFI variable
 store files

The EFI variable store driver (efivars.c) and option backend
(option.c) require EDK2 headers which are x86-specific and not
available in ARM verstage. Use 'all_x86-' instead of 'all-' to
exclude verstage while keeping other x86 stages and SMM.

TEST=build google/dewatt with CFR enabled

Change-Id: I6d0955423cb55658725dfa3025b2118736f5e63b
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90296
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/drivers/efi/Makefile.mk | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/drivers/efi/Makefile.mk b/src/drivers/efi/Makefile.mk
index 2c3cf9c3bf..060c0130f4 100644
--- a/src/drivers/efi/Makefile.mk
+++ b/src/drivers/efi/Makefile.mk
@@ -1,11 +1,11 @@
 # SPDX-License-Identifier: GPL-2.0-only
 
-all-$(CONFIG_DRIVERS_EFI_VARIABLE_STORE)	+= efivars.c
+all_x86-$(CONFIG_DRIVERS_EFI_VARIABLE_STORE)	+= efivars.c
 smm-$(CONFIG_DRIVERS_EFI_VARIABLE_STORE)	+= efivars.c
 
 ramstage-$(CONFIG_DRIVERS_EFI_UPDATE_CAPSULES)	+= capsules.c
 
-all-$(CONFIG_USE_UEFI_VARIABLE_STORE)	+= option.c
+all_x86-$(CONFIG_USE_UEFI_VARIABLE_STORE)	+= option.c
 smm-$(CONFIG_USE_UEFI_VARIABLE_STORE)	+= option.c
 
 ramstage-$(CONFIG_DRIVERS_EFI_FW_INFO)	+= info.c

From 416f67f6704a5a0df1299c61dc267538e5c5d8f6 Mon Sep 17 00:00:00 2001
From: Maximilian Brune <maximilian.brune@9elements.com>
Date: Sun, 2 Nov 2025 23:11:21 +0100
Subject: [PATCH 2669/3886] vendorcode/amd/fsp/.../fsp_h_c99.h: Use fsp2_0
 structs

Since the structs are the same, we may as well use the ones directly
from the driver (since it implements the standard anyway).

Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: I44116e5e977029c37e1bf9b9d8ce8d6c022b5b0b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89870
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
---
 src/drivers/intel/fsp2_0/include/fsp/upd.h   |  6 ++++
 src/vendorcode/amd/fsp/cezanne/fsp_h_c99.h   | 29 +-------------------
 src/vendorcode/amd/fsp/common/fsp_h_c99.h    | 29 +-------------------
 src/vendorcode/amd/fsp/mendocino/fsp_h_c99.h | 29 +-------------------
 src/vendorcode/amd/fsp/picasso/fsp_h_c99.h   | 28 +------------------
 5 files changed, 10 insertions(+), 111 deletions(-)

diff --git a/src/drivers/intel/fsp2_0/include/fsp/upd.h b/src/drivers/intel/fsp2_0/include/fsp/upd.h
index 8c307c5748..cde479cd38 100644
--- a/src/drivers/intel/fsp2_0/include/fsp/upd.h
+++ b/src/drivers/intel/fsp2_0/include/fsp/upd.h
@@ -22,6 +22,8 @@ typedef struct {
 	uint8_t                       Reserved[23];
 } __packed FSP_UPD_HEADER;
 
+_Static_assert(sizeof(FSP_UPD_HEADER) == 32, "FSP_UPD_HEADER not packed");
+
 #if CONFIG(PLATFORM_USES_FSP2_X86_32)
 typedef struct {
 	///
@@ -55,6 +57,8 @@ typedef struct {
 	uint32_t                      BootMode;
 	uint8_t                       Reserved1[8];
 } __packed FSPM_ARCH_UPD;
+
+_Static_assert(sizeof(FSPM_ARCH_UPD) == 32, "FSPM_ARCH_UPD not packed");
 #else
 #error You need to implement this struct for x86_64 FSP
 #endif
@@ -77,4 +81,6 @@ typedef struct {
 	uint8_t                       Reserved2[19];
 } __packed FSPS_ARCH_UPD;
 
+_Static_assert(sizeof(FSPS_ARCH_UPD) == 32, "FSPS_ARCH_UPD not packed");
+
 #endif /* _FSP2_0_UPD_H_ */
diff --git a/src/vendorcode/amd/fsp/cezanne/fsp_h_c99.h b/src/vendorcode/amd/fsp/cezanne/fsp_h_c99.h
index 1a295f591a..17a5616711 100644
--- a/src/vendorcode/amd/fsp/cezanne/fsp_h_c99.h
+++ b/src/vendorcode/amd/fsp/cezanne/fsp_h_c99.h
@@ -8,6 +8,7 @@
 #ifndef FSP_H_C99_H
 #define FSP_H_C99_H
 
+#include <fsp/upd.h>
 #include <stdint.h>
 
 enum {
@@ -27,32 +28,4 @@ typedef enum {
 	EnumInitPhaseEndOfFirmware		= 0xF0
 } FSP_INIT_PHASE;
 
-typedef struct __packed {
-	uint64_t	Signature;
-	uint8_t		Revision;
-	uint8_t		Reserved[23];
-} FSP_UPD_HEADER;
-
-_Static_assert(sizeof(FSP_UPD_HEADER) == 32, "FSP_UPD_HEADER not packed");
-
-
-#if CONFIG(PLATFORM_USES_FSP2_X86_32)
-typedef struct __packed {
-	uint8_t		Revision;
-	uint8_t		Reserved[3];
-	/* Note: This ought to be void*, but that won't allow calling this binary on x86_64. */
-	uint32_t	NvsBufferPtr;
-	/* Note: This ought to be void*, but that won't allow calling this binary on x86_64. */
-	uint32_t	StackBase;
-	uint32_t	StackSize;
-	uint32_t	BootLoaderTolumSize;
-	uint32_t	BootMode;
-	uint8_t		Reserved1[8];
-} FSPM_ARCH_UPD;
-
-_Static_assert(sizeof(FSPM_ARCH_UPD) == 32, "FSPM_ARCH_UPD not packed");
-#else
-#error You need to implement this struct for x86_64 FSP
-#endif
-
 #endif /* FSP_H_C99_H */
diff --git a/src/vendorcode/amd/fsp/common/fsp_h_c99.h b/src/vendorcode/amd/fsp/common/fsp_h_c99.h
index 1a295f591a..17a5616711 100644
--- a/src/vendorcode/amd/fsp/common/fsp_h_c99.h
+++ b/src/vendorcode/amd/fsp/common/fsp_h_c99.h
@@ -8,6 +8,7 @@
 #ifndef FSP_H_C99_H
 #define FSP_H_C99_H
 
+#include <fsp/upd.h>
 #include <stdint.h>
 
 enum {
@@ -27,32 +28,4 @@ typedef enum {
 	EnumInitPhaseEndOfFirmware		= 0xF0
 } FSP_INIT_PHASE;
 
-typedef struct __packed {
-	uint64_t	Signature;
-	uint8_t		Revision;
-	uint8_t		Reserved[23];
-} FSP_UPD_HEADER;
-
-_Static_assert(sizeof(FSP_UPD_HEADER) == 32, "FSP_UPD_HEADER not packed");
-
-
-#if CONFIG(PLATFORM_USES_FSP2_X86_32)
-typedef struct __packed {
-	uint8_t		Revision;
-	uint8_t		Reserved[3];
-	/* Note: This ought to be void*, but that won't allow calling this binary on x86_64. */
-	uint32_t	NvsBufferPtr;
-	/* Note: This ought to be void*, but that won't allow calling this binary on x86_64. */
-	uint32_t	StackBase;
-	uint32_t	StackSize;
-	uint32_t	BootLoaderTolumSize;
-	uint32_t	BootMode;
-	uint8_t		Reserved1[8];
-} FSPM_ARCH_UPD;
-
-_Static_assert(sizeof(FSPM_ARCH_UPD) == 32, "FSPM_ARCH_UPD not packed");
-#else
-#error You need to implement this struct for x86_64 FSP
-#endif
-
 #endif /* FSP_H_C99_H */
diff --git a/src/vendorcode/amd/fsp/mendocino/fsp_h_c99.h b/src/vendorcode/amd/fsp/mendocino/fsp_h_c99.h
index 1a295f591a..17a5616711 100644
--- a/src/vendorcode/amd/fsp/mendocino/fsp_h_c99.h
+++ b/src/vendorcode/amd/fsp/mendocino/fsp_h_c99.h
@@ -8,6 +8,7 @@
 #ifndef FSP_H_C99_H
 #define FSP_H_C99_H
 
+#include <fsp/upd.h>
 #include <stdint.h>
 
 enum {
@@ -27,32 +28,4 @@ typedef enum {
 	EnumInitPhaseEndOfFirmware		= 0xF0
 } FSP_INIT_PHASE;
 
-typedef struct __packed {
-	uint64_t	Signature;
-	uint8_t		Revision;
-	uint8_t		Reserved[23];
-} FSP_UPD_HEADER;
-
-_Static_assert(sizeof(FSP_UPD_HEADER) == 32, "FSP_UPD_HEADER not packed");
-
-
-#if CONFIG(PLATFORM_USES_FSP2_X86_32)
-typedef struct __packed {
-	uint8_t		Revision;
-	uint8_t		Reserved[3];
-	/* Note: This ought to be void*, but that won't allow calling this binary on x86_64. */
-	uint32_t	NvsBufferPtr;
-	/* Note: This ought to be void*, but that won't allow calling this binary on x86_64. */
-	uint32_t	StackBase;
-	uint32_t	StackSize;
-	uint32_t	BootLoaderTolumSize;
-	uint32_t	BootMode;
-	uint8_t		Reserved1[8];
-} FSPM_ARCH_UPD;
-
-_Static_assert(sizeof(FSPM_ARCH_UPD) == 32, "FSPM_ARCH_UPD not packed");
-#else
-#error You need to implement this struct for x86_64 FSP
-#endif
-
 #endif /* FSP_H_C99_H */
diff --git a/src/vendorcode/amd/fsp/picasso/fsp_h_c99.h b/src/vendorcode/amd/fsp/picasso/fsp_h_c99.h
index 79ef9253f8..17a5616711 100644
--- a/src/vendorcode/amd/fsp/picasso/fsp_h_c99.h
+++ b/src/vendorcode/amd/fsp/picasso/fsp_h_c99.h
@@ -8,6 +8,7 @@
 #ifndef FSP_H_C99_H
 #define FSP_H_C99_H
 
+#include <fsp/upd.h>
 #include <stdint.h>
 
 enum {
@@ -27,31 +28,4 @@ typedef enum {
 	EnumInitPhaseEndOfFirmware		= 0xF0
 } FSP_INIT_PHASE;
 
-typedef struct __packed {
-	uint64_t	Signature;
-	uint8_t		Revision;
-	uint8_t		Reserved[23];
-} FSP_UPD_HEADER;
-
-_Static_assert(sizeof(FSP_UPD_HEADER) == 32, "FSP_UPD_HEADER not packed");
-
-#if CONFIG(PLATFORM_USES_FSP2_X86_32)
-typedef struct __packed {
-	uint8_t		Revision;
-	uint8_t		Reserved[3];
-	/* Note: This ought to be void*, but that won't allow calling this binary on x86_64. */
-	uint32_t	NvsBufferPtr;
-	/* Note: This ought to be void*, but that won't allow calling this binary on x86_64. */
-	uint32_t	StackBase;
-	uint32_t	StackSize;
-	uint32_t	BootLoaderTolumSize;
-	uint32_t	BootMode;
-	uint8_t		Reserved1[8];
-} FSPM_ARCH_UPD;
-
-_Static_assert(sizeof(FSPM_ARCH_UPD) == 32, "FSPM_ARCH_UPD not packed");
-#else
-#error You need to implement this struct for x86_64 FSP
-#endif
-
 #endif /* FSP_H_C99_H */

From f13e800a71106dcf1bef184c7c6d8df0cb7f06e6 Mon Sep 17 00:00:00 2001
From: Maximilian Brune <maximilian.brune@9elements.com>
Date: Mon, 10 Nov 2025 17:44:41 +0100
Subject: [PATCH 2670/3886] mb/amd/crater/Kconfig: Use A/B recovery scheme for
 renoir

renoir uses the A/B recovery flash layout without the ISH structure. But
this is handled by amdfwtool.

Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: If9d53bf8fb5fe80779af20ccf7aa3bd9d88a5cc1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90214
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
---
 src/mainboard/amd/crater/Kconfig | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/src/mainboard/amd/crater/Kconfig b/src/mainboard/amd/crater/Kconfig
index e8feffc94c..b2fc3d63e0 100644
--- a/src/mainboard/amd/crater/Kconfig
+++ b/src/mainboard/amd/crater/Kconfig
@@ -53,6 +53,9 @@ config CRATER_MCHP_FW_FILE
 	help
 	  The EC firmware blob is at the EC_BODY FMAP region of the firmware image.
 
+config PSP_RECOVERY_AB
+	default y
+
 config VBOOT
 	select VBOOT_NO_BOARD_SUPPORT
 	select VBOOT_SEPARATE_VERSTAGE

From cbfa28b06e20aa346b9929c9ea2c75abfab5d681 Mon Sep 17 00:00:00 2001
From: Luca Lai <luca.lai@lcfc.corp-partner.google.com>
Date: Thu, 27 Nov 2025 14:35:52 +0800
Subject: [PATCH 2671/3886] mb/google/fatcat/var/ruby: Modify power limit
 configuration

Modify the power limit setting like below
PL1 : 15
PL2 : 35
PL4 : 150

BUG=b:464422702
TEST=Build and check the system could boot to OS

Change-Id: I629af9bdf41cd2344d8b4189f49a0e27f5db695d
Signed-off-by: Luca Lai <luca.lai@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90246
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/google/fatcat/variants/ruby/overridetree.cb | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/src/mainboard/google/fatcat/variants/ruby/overridetree.cb b/src/mainboard/google/fatcat/variants/ruby/overridetree.cb
index 2de2dc082b..9cecdd7b05 100644
--- a/src/mainboard/google/fatcat/variants/ruby/overridetree.cb
+++ b/src/mainboard/google/fatcat/variants/ruby/overridetree.cb
@@ -16,14 +16,14 @@ chip soc/intel/pantherlake
 	# Apply PTL-U's thermal settings here to avoid thermal issues.
 	register "power_limits_config[PTL_CORE_1]" = "{
 		.tdp_pl1_override = 15,
-		.tdp_pl2_override = 55,
-		.tdp_pl4 = 152,
+		.tdp_pl2_override = 35,
+		.tdp_pl4 = 150,
 	}"
 
 	register "power_limits_config[PTL_CORE_2]" = "{
 		.tdp_pl1_override = 15,
-		.tdp_pl2_override = 55,
-		.tdp_pl4 = 152,
+		.tdp_pl2_override = 35,
+		.tdp_pl4 = 150,
 	}"
 
 	register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC_SKIP)"	# USB2_C0

From afc191357f613612589533833e89b0351a3b95db Mon Sep 17 00:00:00 2001
From: Felix Singer <felix.singer@secunet.com>
Date: Tue, 2 Dec 2025 14:54:23 +0000
Subject: [PATCH 2672/3886] 3rdparty/intel-microcode: Update to upstream main

Updating from commit id 4ded52b4b0e1:
2025-08-11 17:00:18 -0600 - (microcode-20250812 Release)

to commit id f910b0a225d6:
2025-11-10 16:26:35 -0600 - (microcode-20251111 Release)

This brings in 1 new commits:
f910b0a225d6 microcode-20251111 Release

Change-Id: I215558de6938c1955faff3250f791da34b97f0c4
Signed-off-by: Felix Singer <felix.singer@secunet.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90337
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
---
 3rdparty/intel-microcode | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/3rdparty/intel-microcode b/3rdparty/intel-microcode
index 4ded52b4b0..f910b0a225 160000
--- a/3rdparty/intel-microcode
+++ b/3rdparty/intel-microcode
@@ -1 +1 @@
-Subproject commit 4ded52b4b0e1d60e83259cc88d1f5ad22f71a63e
+Subproject commit f910b0a225d66a23a407710c61b0b63ee612b50f

From a87e699f043017e27a45fe3ba10cccbeda6b5179 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Micha=C5=82=20Kope=C4=87?= <michal.kopec@3mdeb.com>
Date: Sat, 29 Mar 2025 14:25:11 +0100
Subject: [PATCH 2673/3886] mb/lenovo/m900_tiny: Enable Vboot
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Add Vboot configuration (Kconfig and FMDs for RO only and RW_A layouts).

TEST=Build with UEFIPayload and boot to payload. Verify in cbmem logs
that verstage has executed and selected Slot A in the case of RW_A
layout.

Change-Id: Ide2a3a4b59be5b27bf7315690520c9392a98d044
Signed-off-by: Michał Kopeć <michal.kopec@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87043
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Filip Lewiński <filip.lewinski@3mdeb.com>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
---
 src/mainboard/lenovo/m900_tiny/Kconfig       | 11 ++++++
 src/mainboard/lenovo/m900_tiny/vboot-ro.fmd  | 30 ++++++++++++++++
 src/mainboard/lenovo/m900_tiny/vboot-rwa.fmd | 36 ++++++++++++++++++++
 3 files changed, 77 insertions(+)
 create mode 100644 src/mainboard/lenovo/m900_tiny/vboot-ro.fmd
 create mode 100644 src/mainboard/lenovo/m900_tiny/vboot-rwa.fmd

diff --git a/src/mainboard/lenovo/m900_tiny/Kconfig b/src/mainboard/lenovo/m900_tiny/Kconfig
index 8f018b5700..71a02d6118 100644
--- a/src/mainboard/lenovo/m900_tiny/Kconfig
+++ b/src/mainboard/lenovo/m900_tiny/Kconfig
@@ -41,4 +41,15 @@ config PRERAM_CBMEM_CONSOLE_SIZE
 config DIMM_SPD_SIZE
 	default 512 #DDR4
 
+config VBOOT
+	select GBB_FLAG_DISABLE_EC_SOFTWARE_SYNC
+	select GBB_FLAG_DISABLE_FWMP
+	select GBB_FLAG_DISABLE_LID_SHUTDOWN
+	select GBB_FLAG_DISABLE_PD_SOFTWARE_SYNC
+	select HAS_RECOVERY_MRC_CACHE
+	select VBOOT_VBNV_FLASH
+
+config FMDFILE
+	default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/vboot-rwa.fmd" if VBOOT
+
 endif
diff --git a/src/mainboard/lenovo/m900_tiny/vboot-ro.fmd b/src/mainboard/lenovo/m900_tiny/vboot-ro.fmd
new file mode 100644
index 0000000000..40855e7c01
--- /dev/null
+++ b/src/mainboard/lenovo/m900_tiny/vboot-ro.fmd
@@ -0,0 +1,30 @@
+FLASH 16M {
+	SI_ALL 8M {
+		SI_DESC 4K
+		SI_GBE 8K
+		SI_ME
+	}
+	SI_BIOS 8M {
+		RW_MISC 2M {
+			UNIFIED_MRC_CACHE(PRESERVE) 128K {
+				RECOVERY_MRC_CACHE 64K
+				RW_MRC_CACHE 64K
+			}
+			SMMSTORE(PRESERVE) 256K
+			RW_ELOG(PRESERVE) 16K
+			RW_SHARED 16K {
+				SHARED_DATA 8K
+				VBLOCK_DEV 8K
+			}
+			RW_NVRAM(PRESERVE) 24K
+		}
+
+		WP_RO {
+			FMAP 2K
+			RO_FRID 128
+			RO_PADDING 1920
+			GBB 120K
+			COREBOOT(CBFS)
+		}
+	}
+}
diff --git a/src/mainboard/lenovo/m900_tiny/vboot-rwa.fmd b/src/mainboard/lenovo/m900_tiny/vboot-rwa.fmd
new file mode 100644
index 0000000000..df3bfdb417
--- /dev/null
+++ b/src/mainboard/lenovo/m900_tiny/vboot-rwa.fmd
@@ -0,0 +1,36 @@
+FLASH 16M {
+	SI_ALL 8M {
+		SI_DESC 4K
+		SI_GBE 8K
+		SI_ME
+	}
+	SI_BIOS 8M {
+		RW_MISC 2M {
+			UNIFIED_MRC_CACHE(PRESERVE) 128K {
+				RECOVERY_MRC_CACHE 64K
+				RW_MRC_CACHE 64K
+			}
+			SMMSTORE(PRESERVE) 256K
+			RW_ELOG(PRESERVE) 16K
+			RW_SHARED 16K {
+				SHARED_DATA 8K
+				VBLOCK_DEV 8K
+			}
+			RW_NVRAM(PRESERVE) 24K
+		}
+
+		RW_SECTION_A 3M {
+			VBLOCK_A 8K
+			FW_MAIN_A(CBFS)
+			RW_FWID_A 128
+		}
+
+		WP_RO 3M {
+			FMAP 2K
+			RO_FRID 128
+			RO_PADDING 1920
+			GBB 120K
+			COREBOOT(CBFS)
+		}
+	}
+}

From 3c49c1399542c60d34bb0f63dd6f00bb11f1930d Mon Sep 17 00:00:00 2001
From: Daniel Maslowski <info@orangecms.org>
Date: Thu, 16 Oct 2025 14:54:45 +0200
Subject: [PATCH 2674/3886] util/ifdtool: fix typo PSL->MSL

This is the MCH Strap Length, and FMSBA is the corresponding
Flash MCH Strap Base Address. See ICH8 datasheet, FLMAP2.

Change-Id: I322c13d9228800a2736b0288377495287521712c
Signed-off-by: Daniel Maslowski <info@orangecms.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89614
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 util/ifdtool/ifdtool.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/util/ifdtool/ifdtool.c b/util/ifdtool/ifdtool.c
index fc0cb5fa4e..75238c73b2 100644
--- a/util/ifdtool/ifdtool.c
+++ b/util/ifdtool/ifdtool.c
@@ -1035,7 +1035,7 @@ static void dump_fd(char *image, int size)
 
 	if (!is_platform_with_100x_series_pch()) {
 		printf("FLMAP2:    0x%08x\n", fdb->flmap2);
-		printf("  PSL:     0x%04x\n", (fdb->flmap2 >> 8) & 0xffff);
+		printf("  MSL:     0x%04x\n", (fdb->flmap2 >> 8) & 0xffff);
 		printf("  FMSBA:   0x%x\n", ((fdb->flmap2) & 0xff) << 4);
 	}
 

From 2f95552802422160b1d9b88288953a2be3a19ee7 Mon Sep 17 00:00:00 2001
From: Uwe Poeche <uwe.poeche@siemens.com>
Date: Tue, 2 Dec 2025 13:45:35 +0100
Subject: [PATCH 2675/3886] mb/siemens/mc_ehl: Move Kconfig switch to variants

SOC_INTEL_ELKHARTLAKE_TCO_NO_REBOOT_EN has to be handled differently at
variant level in upcoming mainboards. This patch moves the switch from
upper mc_ehl level to board-specific level.

TEST=Compared .config files for all boards after defconfig completed
before and after the patch for all boards.

Change-Id: I5adb978152eb9f465e30988f39d1ea7815403ce0
Signed-off-by: Uwe Poeche <uwe.poeche@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90333
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
---
 src/mainboard/siemens/mc_ehl/Kconfig                  | 3 ---
 src/mainboard/siemens/mc_ehl/variants/mc_ehl1/Kconfig | 3 +++
 src/mainboard/siemens/mc_ehl/variants/mc_ehl2/Kconfig | 3 +++
 src/mainboard/siemens/mc_ehl/variants/mc_ehl3/Kconfig | 3 +++
 src/mainboard/siemens/mc_ehl/variants/mc_ehl4/Kconfig | 3 +++
 src/mainboard/siemens/mc_ehl/variants/mc_ehl5/Kconfig | 3 +++
 src/mainboard/siemens/mc_ehl/variants/mc_ehl6/Kconfig | 3 +++
 7 files changed, 18 insertions(+), 3 deletions(-)

diff --git a/src/mainboard/siemens/mc_ehl/Kconfig b/src/mainboard/siemens/mc_ehl/Kconfig
index 0841e1d486..5aff0be1b5 100644
--- a/src/mainboard/siemens/mc_ehl/Kconfig
+++ b/src/mainboard/siemens/mc_ehl/Kconfig
@@ -55,7 +55,4 @@ config MAINBOARD_PART_NUMBER
 config DEVICETREE
 	default "variants/\$(CONFIG_VARIANT_DIR)/devicetree.cb"
 
-config SOC_INTEL_ELKHARTLAKE_TCO_NO_REBOOT_EN
-	default y
-
 endif # BOARD_SIEMENS_BASEBOARD_MC_EHL
diff --git a/src/mainboard/siemens/mc_ehl/variants/mc_ehl1/Kconfig b/src/mainboard/siemens/mc_ehl/variants/mc_ehl1/Kconfig
index 03f78b7a8e..96e9ddccec 100644
--- a/src/mainboard/siemens/mc_ehl/variants/mc_ehl1/Kconfig
+++ b/src/mainboard/siemens/mc_ehl/variants/mc_ehl1/Kconfig
@@ -36,4 +36,7 @@ config EARLY_PCI_MMIO_BASE
 	depends on NC_FPGA_POST_CODE
 	default 0xfe800000
 
+config SOC_INTEL_ELKHARTLAKE_TCO_NO_REBOOT_EN
+	default y
+
 endif # BOARD_SIEMENS_MC_EHL1
diff --git a/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/Kconfig b/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/Kconfig
index 73ef1dadc4..211da6fb9f 100644
--- a/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/Kconfig
+++ b/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/Kconfig
@@ -21,4 +21,7 @@ config UART_FOR_CONSOLE
 	int
 	default 0
 
+config SOC_INTEL_ELKHARTLAKE_TCO_NO_REBOOT_EN
+	default y
+
 endif # BOARD_SIEMENS_MC_EHL2
diff --git a/src/mainboard/siemens/mc_ehl/variants/mc_ehl3/Kconfig b/src/mainboard/siemens/mc_ehl/variants/mc_ehl3/Kconfig
index 688074a55e..5f49d5e32c 100644
--- a/src/mainboard/siemens/mc_ehl/variants/mc_ehl3/Kconfig
+++ b/src/mainboard/siemens/mc_ehl/variants/mc_ehl3/Kconfig
@@ -22,4 +22,7 @@ config UART_FOR_CONSOLE
 	int
 	default 0
 
+config SOC_INTEL_ELKHARTLAKE_TCO_NO_REBOOT_EN
+	default y
+
 endif # BOARD_SIEMENS_MC_EHL3
diff --git a/src/mainboard/siemens/mc_ehl/variants/mc_ehl4/Kconfig b/src/mainboard/siemens/mc_ehl/variants/mc_ehl4/Kconfig
index 842ec11846..f67a31d529 100644
--- a/src/mainboard/siemens/mc_ehl/variants/mc_ehl4/Kconfig
+++ b/src/mainboard/siemens/mc_ehl/variants/mc_ehl4/Kconfig
@@ -31,4 +31,7 @@ config EARLY_PCI_MMIO_BASE
 	depends on NC_FPGA_POST_CODE
 	default 0xfe800000
 
+config SOC_INTEL_ELKHARTLAKE_TCO_NO_REBOOT_EN
+	default y
+
 endif # BOARD_SIEMENS_MC_EHL4
diff --git a/src/mainboard/siemens/mc_ehl/variants/mc_ehl5/Kconfig b/src/mainboard/siemens/mc_ehl/variants/mc_ehl5/Kconfig
index 3e0c61c3d9..731d12bc78 100644
--- a/src/mainboard/siemens/mc_ehl/variants/mc_ehl5/Kconfig
+++ b/src/mainboard/siemens/mc_ehl/variants/mc_ehl5/Kconfig
@@ -22,4 +22,7 @@ config UART_FOR_CONSOLE
 	int
 	default 0
 
+config SOC_INTEL_ELKHARTLAKE_TCO_NO_REBOOT_EN
+	default y
+
 endif # BOARD_SIEMENS_MC_EHL5
diff --git a/src/mainboard/siemens/mc_ehl/variants/mc_ehl6/Kconfig b/src/mainboard/siemens/mc_ehl/variants/mc_ehl6/Kconfig
index 936a452065..d7cb2dffaa 100644
--- a/src/mainboard/siemens/mc_ehl/variants/mc_ehl6/Kconfig
+++ b/src/mainboard/siemens/mc_ehl/variants/mc_ehl6/Kconfig
@@ -37,4 +37,7 @@ config EARLY_PCI_MMIO_BASE
 	depends on NC_FPGA_POST_CODE
 	default 0xfe800000
 
+config SOC_INTEL_ELKHARTLAKE_TCO_NO_REBOOT_EN
+	default y
+
 endif # BOARD_SIEMENS_MC_EHL6

From d51f78051503accea49c6c7acc3253fd5ce6c859 Mon Sep 17 00:00:00 2001
From: Kilian Krause <kilian.krause@siemens.com>
Date: Tue, 4 Nov 2025 16:48:20 +0100
Subject: [PATCH 2676/3886] mb/siemens/mc_rpl: Correct SMBIOS socket type to
 BGA1744

The mc_rpl platform uses BGA1744, not LGA1700. Update the Kconfig
selection to report the correct socket type in SMBIOS.

TEST=Built for mc_rpl1, verified `dmidecode -t processor | grep Upgrade`
     shows "Socket BGA1744"

Change-Id: I119c6e95ba0d4a5d7afd3f922f2662aa55ac3f64
Signed-off-by: Kilian Krause <kilian.krause@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89900
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
---
 src/mainboard/siemens/mc_rpl/Kconfig | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/mainboard/siemens/mc_rpl/Kconfig b/src/mainboard/siemens/mc_rpl/Kconfig
index cfb5712833..447735fbbc 100644
--- a/src/mainboard/siemens/mc_rpl/Kconfig
+++ b/src/mainboard/siemens/mc_rpl/Kconfig
@@ -3,7 +3,7 @@
 config BOARD_SIEMENS_BASEBOARD_MC_RPL
 	def_bool n
 	select BOARD_ROMSIZE_KB_16384
-	select CPU_INTEL_SOCKET_LGA1700
+	select CPU_INTEL_SOCKET_BGA1744
 	select DRIVER_SIEMENS_NC_FPGA
 	select DRIVERS_I2C_GENERIC
 	select DRIVERS_INTEL_DPTF

From db2ac42405a2b10bea1d740e2153f58162cb83df Mon Sep 17 00:00:00 2001
From: Yidi Lin <yidilin@google.com>
Date: Thu, 27 Nov 2025 20:07:53 +0800
Subject: [PATCH 2677/3886] soc/mediatek/common: Refactor DDP mode setting

Move common display mode parameter calculation from SoC-specific
mtk_ddp_mode_set functions to a new common mtk_ddp_mode_set function in
src/soc/mediatek/common/display.c.

Rename the SoC-specific mtk_ddp_mode_set functions to
mtk_ddp_soc_mode_set and modify them to directly accept the calculated
display parameters (format, bits per pixel, width, height, and vertical
refresh rate). This centralizes the common logic and improves code
reusability.

TEST=emerge-rauru coreboot -j && emerge-geralt coreboot -j

Change-Id: I2f86dd609f8ea5225ff4d788206c7494164b6e4b
Signed-off-by: Jarried Lin <jarried.lin@mediatek.corp-partner.google.com>
Signed-off-by: Yidi Lin <yidilin@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90245
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
---
 src/soc/mediatek/common/display.c             | 25 +++++++++++++++++++
 src/soc/mediatek/common/include/soc/display.h |  2 ++
 src/soc/mediatek/mt8186/ddp.c                 | 18 ++-----------
 src/soc/mediatek/mt8188/ddp.c                 | 24 ++----------------
 src/soc/mediatek/mt8189/ddp.c                 | 25 +++----------------
 src/soc/mediatek/mt8195/ddp.c                 | 24 ++----------------
 src/soc/mediatek/mt8196/ddp.c                 | 24 ++----------------
 7 files changed, 38 insertions(+), 104 deletions(-)

diff --git a/src/soc/mediatek/common/display.c b/src/soc/mediatek/common/display.c
index f48cdaf215..297fcc2fe8 100644
--- a/src/soc/mediatek/common/display.c
+++ b/src/soc/mediatek/common/display.c
@@ -199,3 +199,28 @@ int mtk_display_init(void)
 
 	return 0;
 }
+
+void mtk_ddp_mode_set(const struct edid *edid, enum disp_path_sel path)
+{
+	u32 fmt = OVL_INFMT_RGBA8888;
+	u32 bpp = edid->framebuffer_bits_per_pixel / 8;
+	u32 width = edid->mode.ha;
+	u32 height = edid->mode.va;
+	u32 vrefresh = edid->mode.refresh;
+
+	printk(BIOS_DEBUG, "%s: display resolution: %ux%u@%u bpp %u\n", __func__, width, height,
+	       vrefresh, bpp);
+
+	if (!vrefresh) {
+		if (!width || !height)
+			vrefresh = 60;
+		else
+			vrefresh = edid->mode.pixel_clock * 1000 /
+				   ((width + edid->mode.hbl) * (height + edid->mode.vbl));
+
+		printk(BIOS_WARNING, "%s: vrefresh is not provided; using %u\n", __func__,
+		       vrefresh);
+	}
+
+	mtk_ddp_soc_mode_set(fmt, bpp, width, height, vrefresh, path);
+}
diff --git a/src/soc/mediatek/common/include/soc/display.h b/src/soc/mediatek/common/include/soc/display.h
index f202c1d40e..2551e0b5e5 100644
--- a/src/soc/mediatek/common/include/soc/display.h
+++ b/src/soc/mediatek/common/include/soc/display.h
@@ -34,6 +34,8 @@ int mtk_display_init(void);
 
 void mtk_ddp_init(void);
 void mtk_ddp_mode_set(const struct edid *edid, enum disp_path_sel path);
+void mtk_ddp_soc_mode_set(u32 fmt, u32 bpp, u32 width, u32 height, u32 vrefresh,
+			  enum disp_path_sel path);
 void mtk_ddp_ovlsys_start(uintptr_t fb_addr);
 
 #endif
diff --git a/src/soc/mediatek/mt8186/ddp.c b/src/soc/mediatek/mt8186/ddp.c
index 5a5f5447ff..84593481b4 100644
--- a/src/soc/mediatek/mt8186/ddp.c
+++ b/src/soc/mediatek/mt8186/ddp.c
@@ -141,23 +141,9 @@ void mtk_ddp_init(void)
 	write32((void *)(SMI_LARB0 + SMI_LARB_PORT_L0_OVL_RDMA0), 0);
 }
 
-void mtk_ddp_mode_set(const struct edid *edid, enum disp_path_sel path)
+void mtk_ddp_soc_mode_set(u32 fmt, u32 bpp, u32 width, u32 height, u32 vrefresh,
+			  enum disp_path_sel path)
 {
-	u32 fmt = OVL_INFMT_RGBA8888;
-	u32 bpp = edid->framebuffer_bits_per_pixel / 8;
-	u32 width = edid->mode.ha;
-	u32 height = edid->mode.va;
-	u32 vrefresh = edid->mode.refresh;
-
-	printk(BIOS_INFO, "%s: display resolution: %ux%u@%u bpp %u\n",
-	       __func__, width, height, vrefresh, bpp);
-
-	if (!vrefresh) {
-		vrefresh = 60;
-		printk(BIOS_INFO, "%s: invalid vrefresh; setting to %u\n",
-		       __func__, vrefresh);
-	}
-
 	main_disp_path_setup(width, height, vrefresh);
 	rdma_start();
 	ovl_layer_config(fmt, bpp, width, height);
diff --git a/src/soc/mediatek/mt8188/ddp.c b/src/soc/mediatek/mt8188/ddp.c
index ce14fa7800..e37915e35c 100644
--- a/src/soc/mediatek/mt8188/ddp.c
+++ b/src/soc/mediatek/mt8188/ddp.c
@@ -145,29 +145,9 @@ void mtk_ddp_init(void)
 	write32p(SMI_LARB0 + SMI_LARB_PORT_L0_OVL_RDMA0, 0);
 }
 
-void mtk_ddp_mode_set(const struct edid *edid, enum disp_path_sel path)
+void mtk_ddp_soc_mode_set(u32 fmt, u32 bpp, u32 width, u32 height, u32 vrefresh,
+			  enum disp_path_sel path)
 {
-	u32 fmt = OVL_INFMT_RGBA8888;
-	u32 bpp = edid->framebuffer_bits_per_pixel / 8;
-	u32 width = edid->mode.ha;
-	u32 height = edid->mode.va;
-	u32 vrefresh = edid->mode.refresh;
-
-	printk(BIOS_DEBUG, "%s: display resolution: %dx%d@%d bpp %d\n",
-	       __func__, width, height, vrefresh, bpp);
-
-	if (!vrefresh) {
-		if (!width || !height)
-			vrefresh = 60;
-		else
-			vrefresh = edid->mode.pixel_clock * 1000 /
-				   ((width + edid->mode.hbl) *
-				    (height + edid->mode.vbl));
-
-		printk(BIOS_WARNING, "%s: vrefresh is not provided; using %d\n",
-		       __func__, vrefresh);
-	}
-
 	main_disp_path_setup(width, height, vrefresh, path);
 	rdma_start();
 	ovl_layer_config(fmt, bpp, width, height);
diff --git a/src/soc/mediatek/mt8189/ddp.c b/src/soc/mediatek/mt8189/ddp.c
index 1d5630736c..0fc82d8a27 100644
--- a/src/soc/mediatek/mt8189/ddp.c
+++ b/src/soc/mediatek/mt8189/ddp.c
@@ -137,29 +137,10 @@ void mtk_ddp_init(void)
 	       __func__, read32(&smi_larb0->port_l0_ovl_rdma[0]));
 }
 
-void mtk_ddp_mode_set(const struct edid *edid, enum disp_path_sel path)
+void mtk_ddp_soc_mode_set(u32 fmt, u32 bpp, u32 width, u32 height, u32 vrefresh,
+			  enum disp_path_sel path)
 {
-	u32 fmt = OVL_INFMT_RGBA8888;
-	u32 bpp = edid->framebuffer_bits_per_pixel / 8;
-	u32 width = edid->mode.ha;
-	u32 height = edid->mode.va;
-	u32 vrefresh_hz = edid->mode.refresh;
-
-	printk(BIOS_INFO, "%s: display resolution: %dx%d@%d bpp %d\n",
-	       __func__, width, height, vrefresh_hz, bpp);
-
-	if (!vrefresh_hz) {
-		if (!width || !height)
-			vrefresh_hz = 60;
-		else
-			vrefresh_hz = edid->mode.pixel_clock * 1000 /
-				   ((width + edid->mode.hbl) * (height + edid->mode.vbl));
-
-		printk(BIOS_WARNING, "%s: vrefresh is not provided; using %d\n",
-		       __func__, vrefresh_hz);
-	}
-
-	main_disp_path_setup(width, height, vrefresh_hz, path);
+	main_disp_path_setup(width, height, vrefresh, path);
 	rdma_start();
 	ovl_layer_config(fmt, bpp, width, height);
 }
diff --git a/src/soc/mediatek/mt8195/ddp.c b/src/soc/mediatek/mt8195/ddp.c
index 2bd95a2fac..875b3103e5 100644
--- a/src/soc/mediatek/mt8195/ddp.c
+++ b/src/soc/mediatek/mt8195/ddp.c
@@ -150,29 +150,9 @@ void mtk_ddp_init(void)
 	write32((void *)(SMI_LARB0 + SMI_LARB_PORT_L0_OVL_RDMA0), 0);
 }
 
-void mtk_ddp_mode_set(const struct edid *edid, enum disp_path_sel path)
+void mtk_ddp_soc_mode_set(u32 fmt, u32 bpp, u32 width, u32 height, u32 vrefresh,
+			  enum disp_path_sel path)
 {
-	u32 fmt = OVL_INFMT_RGBA8888;
-	u32 bpp = edid->framebuffer_bits_per_pixel / 8;
-	u32 width = edid->mode.ha;
-	u32 height = edid->mode.va;
-	u32 vrefresh = edid->mode.refresh;
-
-	printk(BIOS_DEBUG, "%s: display resolution: %dx%d@%d bpp %d\n",
-	       __func__, width, height, vrefresh, bpp);
-
-	if (!vrefresh) {
-		if (!width || !height)
-			vrefresh = 60;
-		else
-			vrefresh = edid->mode.pixel_clock * 1000 /
-				   ((width + edid->mode.hbl) *
-				    (height + edid->mode.vbl));
-
-		printk(BIOS_WARNING, "%s: vrefresh is not provided; using %d\n",
-		       __func__, vrefresh);
-	}
-
 	main_disp_path_setup(width, height, vrefresh);
 	rdma_start();
 	ovl_layer_config(fmt, bpp, width, height);
diff --git a/src/soc/mediatek/mt8196/ddp.c b/src/soc/mediatek/mt8196/ddp.c
index 6e63b376cd..cd7a50bd8b 100644
--- a/src/soc/mediatek/mt8196/ddp.c
+++ b/src/soc/mediatek/mt8196/ddp.c
@@ -428,32 +428,12 @@ void mtk_ddp_init(void)
 	disp_clock_on();
 }
 
-void mtk_ddp_mode_set(const struct edid *edid, enum disp_path_sel path)
+void mtk_ddp_soc_mode_set(u32 fmt, u32 bpp, u32 width, u32 height, u32 vrefresh,
+			  enum disp_path_sel path)
 {
-	u32 fmt = OVL_INFMT_RGBA8888;
-	u32 bpp = edid->framebuffer_bits_per_pixel / 8;
-	u32 width = edid->mode.ha;
-	u32 height = edid->mode.va;
-	u32 vrefresh = edid->mode.refresh;
-
-	printk(BIOS_DEBUG, "%s: display resolution: %ux%u@%u bpp %u\n", __func__, width, height,
-	       vrefresh, bpp);
-
-	if (!vrefresh) {
-		if (!width || !height)
-			vrefresh = 60;
-		else
-			vrefresh = edid->mode.pixel_clock * 1000 /
-				   ((width + edid->mode.hbl) * (height + edid->mode.vbl));
-
-		printk(BIOS_WARNING, "%s: vrefresh is not provided; using %u\n", __func__,
-		       vrefresh);
-	}
-
 	if (width > 0x1FFF || height > 0x1FFF)
 		printk(BIOS_WARNING, "%s: w/h: %d/%d exceed hw limit %u\n", __func__,
 		       width, height, 0x1FFF);
-
 	main_disp_path_setup(width, height, vrefresh, path);
 	ovlsys_layer_config(fmt, bpp, width, height, path);
 }

From 4f257a28f854a5aeec9661dd69ae39c5f9e92eca Mon Sep 17 00:00:00 2001
From: Sowmya Aralguppe <sowmya.aralguppe@intel.com>
Date: Fri, 28 Nov 2025 11:53:30 +0530
Subject: [PATCH 2678/3886] mb/google/ocelot: Add EC_GOOGLE_CHROMEEC_SKUID
 config

The Wildcat Lake Ocelot mainboard is missing the
EC_GOOGLE_CHROMEEC_SKUID configuration option, causing the sku_id()
function to call the weak implementation that returns
UNDEFINED_STRAPPING_ID instead of calling
google_chromeec_get_board_sku(). This results in incorrect SKU ID
reporting in the coreboot table.

This patch adds missing EC_GOOGLE_CHROMEEC_SKUID configuration to
retrieve SKU information from the Chrome EC.

BUG=b:459266759
TEST= SKU ID is properly configured as 1

Change-Id: I143bdffe40303336d66d1a42e97872aebcb817a3
Signed-off-by: Sowmya Aralguppe <sowmya.aralguppe@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90257
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tom, Poornima <poornima.tom@intel.com>
Reviewed-by: P, Usha <usha.p@intel.com>
Reviewed-by: Pranava Y N <pranavayn@google.com>
---
 src/mainboard/google/ocelot/Kconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/src/mainboard/google/ocelot/Kconfig b/src/mainboard/google/ocelot/Kconfig
index 8b3c377289..ebe107b962 100644
--- a/src/mainboard/google/ocelot/Kconfig
+++ b/src/mainboard/google/ocelot/Kconfig
@@ -21,6 +21,7 @@ config BOARD_GOOGLE_OCELOT_COMMON
 	select EC_GOOGLE_CHROMEEC
 	select EC_GOOGLE_CHROMEEC_BOARDID
 	select EC_GOOGLE_CHROMEEC_ESPI
+	select EC_GOOGLE_CHROMEEC_SKUID
 	select EC_GOOGLE_CHROMEEC_SMBIOS
 	select FW_CONFIG
 	select FW_CONFIG_SOURCE_CHROMEEC_CBI

From 0e9d85425e141c756fe7d758cb16d395b6b94ec7 Mon Sep 17 00:00:00 2001
From: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Date: Wed, 26 Nov 2025 08:49:37 +0800
Subject: [PATCH 2679/3886] mb/google/ocelot/var/matsu: Fix GPP_V3 internal
 pull-up configuration

According to doc#836031, GPP_V3 defaults to Native F1 with the integrated pull-up enabled. However, coreboot was configuring this pin with the internal pull-up set to NONE, which disabled the pull-up and caused GPP_V3/PWRBTN# to read low, leading to unexpected shutdowns.

Update the pad configuration to use the internal pull-up.

BUG=b:463193164
TEST=boots normally and no unexpected shutdown occurs.

Change-Id: Ia650aa9b60d7ce634827330954b1a9c9ac3d7567
Signed-off-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90218
Reviewed-by: Bob Moragues <moragues@google.com>
Reviewed-by: Pranava Y N <pranavayn@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/google/ocelot/variants/matsu/gpio.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/mainboard/google/ocelot/variants/matsu/gpio.c b/src/mainboard/google/ocelot/variants/matsu/gpio.c
index abbf708ffd..7bca115efd 100644
--- a/src/mainboard/google/ocelot/variants/matsu/gpio.c
+++ b/src/mainboard/google/ocelot/variants/matsu/gpio.c
@@ -339,7 +339,7 @@ static const struct pad_config gpio_table[] = {
 	/* GPP_V02:     LANWAKE_N_R */
 	PAD_CFG_NF(GPP_V02, NONE, DEEP, NF1),
 	/* GPP_V03:     PWRBTN_MCP_N */
-	PAD_CFG_NF(GPP_V03, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_V03, UP_20K, DEEP, NF1),
 	/* GPP_V04:     PM_SLP_S3_N */
 	PAD_CFG_NF(GPP_V04, NONE, DEEP, NF1),
 	/* GPP_V05:     PM_SLP_S4_N */

From 2975d7220a013a34584fe6f850a4e6cc2a1e8e05 Mon Sep 17 00:00:00 2001
From: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Date: Fri, 28 Nov 2025 13:23:00 +0800
Subject: [PATCH 2680/3886] mb/google/ocelot/var/matsu: Update devicetree

- Enable CNVi Wi-Fi and BT cores
- Remove unused tbt_pcie_rp0/rp1 nodes

BUG=b:463193164
TEST=Wifi/BT is enabled on Matsu.

Change-Id: Ie5ebf8b88c0ab31b0d2d36f3b7cda1225de77b1a
Signed-off-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90256
Reviewed-by: Bob Moragues <moragues@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Pranava Y N <pranavayn@google.com>
---
 src/mainboard/google/ocelot/variants/matsu/overridetree.cb | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/src/mainboard/google/ocelot/variants/matsu/overridetree.cb b/src/mainboard/google/ocelot/variants/matsu/overridetree.cb
index 196d47a358..299c2cccc0 100644
--- a/src/mainboard/google/ocelot/variants/matsu/overridetree.cb
+++ b/src/mainboard/google/ocelot/variants/matsu/overridetree.cb
@@ -24,6 +24,10 @@ chip soc/intel/pantherlake
 		[DDI_PORT_B] = DDI_ENABLE_HPD | DDI_ENABLE_DDC,
 	}"
 
+	# Enable CNVi Wi-Fi and Bluetooth
+	register "cnvi_wifi_core" = "true"
+	register "cnvi_bt_core" = "true"
+
 	register "serial_io_i2c_mode" = "{
 		[PchSerialIoIndexI2C0]  = PchSerialIoPci,
 		[PchSerialIoIndexI2C1]  = PchSerialIoPci,
@@ -197,8 +201,6 @@ chip soc/intel/pantherlake
 		end
 
 		device ref iaa off end
-		device ref tbt_pcie_rp0 on end
-		device ref tbt_pcie_rp1 on end
 		device ref tcss_xhci on
 			chip drivers/usb/acpi
 				device ref tcss_root_hub on

From 85101704ae893641ff588b38c4d8e1e569cb709c Mon Sep 17 00:00:00 2001
From: "chou.pierce" <chou.pierce@inventec.corp-partner.google.com>
Date: Mon, 10 Nov 2025 14:39:37 +0800
Subject: [PATCH 2681/3886] mb/ocelot/var/ocicat: Create ocicat variant

Create the ocicat variant of ocelot reference board by copying the
template files to a new directory named for the variant.

Due to new_variant.py limitation that repo can no longer be used in
inside, created this CL manually following google suggestion.

BUG=b:457879750
TEST=util/abuild/abuild -p none -t google/ocelot -x -a
make sure the build includes GOOGLE_OCICAT

Change-Id: I5112703146761ed5902737ba6ec5f9d7889b9cf4
Signed-off-by: chou.pierce <chou.pierce@inventec.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89979
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Pranava Y N <pranavayn@google.com>
Reviewed-by: Bob Moragues <moragues@google.com>
---
 src/mainboard/google/ocelot/Kconfig           |  21 +-
 src/mainboard/google/ocelot/Kconfig.name      |   3 +
 .../baseboard/ocelot/include/baseboard/gpio.h |   2 +
 .../google/ocelot/variants/ocicat/Makefile.mk |  11 +
 .../google/ocelot/variants/ocicat/fw_config.c |  28 ++
 .../google/ocelot/variants/ocicat/gpio.c      | 425 ++++++++++++++++++
 .../google/ocelot/variants/ocicat/hda_verb.c  | 126 ++++++
 .../variants/ocicat/include/variant/ec.h      |   8 +
 .../variants/ocicat/include/variant/gpio.h    |  11 +
 .../google/ocelot/variants/ocicat/memory.c    |  36 ++
 .../ocelot/variants/ocicat/overridetree.cb    | 421 +++++++++++++++++
 .../variants/ocicat/part_num_to_dram_id.c     |  35 ++
 .../google/ocelot/variants/ocicat/variant.c   |  48 ++
 13 files changed, 1173 insertions(+), 2 deletions(-)
 create mode 100644 src/mainboard/google/ocelot/variants/ocicat/Makefile.mk
 create mode 100644 src/mainboard/google/ocelot/variants/ocicat/fw_config.c
 create mode 100644 src/mainboard/google/ocelot/variants/ocicat/gpio.c
 create mode 100644 src/mainboard/google/ocelot/variants/ocicat/hda_verb.c
 create mode 100644 src/mainboard/google/ocelot/variants/ocicat/include/variant/ec.h
 create mode 100644 src/mainboard/google/ocelot/variants/ocicat/include/variant/gpio.h
 create mode 100644 src/mainboard/google/ocelot/variants/ocicat/memory.c
 create mode 100644 src/mainboard/google/ocelot/variants/ocicat/overridetree.cb
 create mode 100644 src/mainboard/google/ocelot/variants/ocicat/part_num_to_dram_id.c
 create mode 100644 src/mainboard/google/ocelot/variants/ocicat/variant.c

diff --git a/src/mainboard/google/ocelot/Kconfig b/src/mainboard/google/ocelot/Kconfig
index ebe107b962..dcada1fb6f 100644
--- a/src/mainboard/google/ocelot/Kconfig
+++ b/src/mainboard/google/ocelot/Kconfig
@@ -29,7 +29,7 @@ config BOARD_GOOGLE_OCELOT_COMMON
 	select GOOGLE_SMBIOS_MAINBOARD_VERSION
 	select HAVE_ACPI_RESUME
 	select HAVE_ACPI_TABLES
-	select HAVE_SPD_IN_CBFS if !BOARD_GOOGLE_MODEL_KODKOD
+	select HAVE_SPD_IN_CBFS if !BOARD_GOOGLE_MODEL_KODKOD && !BOARD_GOOGLE_MODEL_OCICAT
 	select I2C_TPM
 	select INTEL_LPSS_UART_FOR_CONSOLE
 	select MAINBOARD_DISABLE_STAGE_CACHE
@@ -51,7 +51,7 @@ config BOARD_GOOGLE_BASEBOARD_OCELOT
 	select DRIVERS_INTEL_USB4_RETIMER
 	select HAVE_SLP_S0_GATE
 	select MAINBOARD_HAS_CHROMEOS
-	select MEMORY_SOLDERDOWN  if !BOARD_GOOGLE_MODEL_KODKOD
+	select MEMORY_SOLDERDOWN  if !BOARD_GOOGLE_MODEL_KODKOD && !BOARD_GOOGLE_MODEL_OCICAT
 	select SOC_INTEL_COMMON_BLOCK_HDA_VERB
 	select SOC_INTEL_IOE_DIE_SUPPORT
 	select SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES
@@ -94,6 +94,16 @@ config BOARD_GOOGLE_MODEL_OJAL
 	select EC_GOOGLE_CHROMEEC_RTK
 	select EC_GOOGLE_CHROMEEC_LPC_GENERIC_MEMORY_RANGE
 
+config BOARD_GOOGLE_MODEL_OCICAT
+	def_bool n
+	select BOARD_GOOGLE_BASEBOARD_OCELOT
+	select DRIVERS_GENERIC_BAYHUB_LV2
+	select DRIVERS_GENERIC_MAX98357A
+	select DRIVERS_INTEL_TOUCH
+	select FSP_UGOP_EARLY_SIGN_OF_LIFE
+	select SPD_CACHE_ENABLE
+	select SPD_CACHE_IN_FMAP
+
 config BOARD_GOOGLE_KODKOD
 	select BOARD_GOOGLE_MODEL_KODKOD
 
@@ -123,6 +133,9 @@ config BOARD_GOOGLE_OCELOTMCHP4ES
 config BOARD_GOOGLE_OJAL
 	select BOARD_GOOGLE_MODEL_OJAL
 
+config BOARD_GOOGLE_OCICAT
+	select BOARD_GOOGLE_MODEL_OCICAT
+
 if BOARD_GOOGLE_OCELOT_COMMON
 
 config BASEBOARD_DIR
@@ -160,6 +173,7 @@ config DRIVER_TPM_I2C_BUS
 	default 0x01 if BOARD_GOOGLE_MODEL_MATSU
 	default 0x01 if BOARD_GOOGLE_MODEL_OCELOT
 	default 0x01 if BOARD_GOOGLE_MODEL_OJAL
+	default 0x01 if BOARD_GOOGLE_MODEL_OCICAT
 
 config HAVE_SLP_S0_GATE
 	def_bool n
@@ -176,6 +190,7 @@ config MAINBOARD_PART_NUMBER
 	default "Matsu" if BOARD_GOOGLE_MODEL_MATSU
 	default "Ocelot" if BOARD_GOOGLE_MODEL_OCELOT
 	default "Ojal" if BOARD_GOOGLE_OJAL
+	default "Ocicat" if BOARD_GOOGLE_OCICAT
 
 config MEMORY_SOLDERDOWN
 	def_bool n
@@ -188,6 +203,7 @@ config TPM_TIS_ACPI_INTERRUPT
 	default 78 if BOARD_GOOGLE_MODEL_MATSU # GPE0_DW2_14 (GPP_E14)
 	default 49 if BOARD_GOOGLE_MODEL_OCELOT # GPE0_DW1_17 (GPP_B17)
 	default 49 if BOARD_GOOGLE_MODEL_OJAL # GPE0_DW1_17 (GPP_B17)
+	default 49 if BOARD_GOOGLE_MODEL_OCICAT # GPE0_DW1_17 (GPP_B17)
 
 config UART_FOR_CONSOLE
 	int
@@ -202,6 +218,7 @@ config VARIANT_DIR
 	default "matsu" if BOARD_GOOGLE_MODEL_MATSU
 	default "ocelot" if BOARD_GOOGLE_MODEL_OCELOT
 	default "ojal" if BOARD_GOOGLE_MODEL_OJAL
+	default "ocicat" if BOARD_GOOGLE_MODEL_OCICAT
 
 config OVERRIDE_DEVICETREE
 	default "variants/\$(CONFIG_VARIANT_DIR)/overridetree.cb"
diff --git a/src/mainboard/google/ocelot/Kconfig.name b/src/mainboard/google/ocelot/Kconfig.name
index e6713f98cb..a57bc43c45 100644
--- a/src/mainboard/google/ocelot/Kconfig.name
+++ b/src/mainboard/google/ocelot/Kconfig.name
@@ -28,3 +28,6 @@ config BOARD_GOOGLE_OCELOTITE4ES
 
 config BOARD_GOOGLE_OCELOTMCHP4ES
 	bool "-> Ocelotmchp4ES"
+
+config BOARD_GOOGLE_OCICAT
+	bool "-> Ocicat"
diff --git a/src/mainboard/google/ocelot/variants/baseboard/ocelot/include/baseboard/gpio.h b/src/mainboard/google/ocelot/variants/baseboard/ocelot/include/baseboard/gpio.h
index 409c4d58e0..821b0da3ff 100644
--- a/src/mainboard/google/ocelot/variants/baseboard/ocelot/include/baseboard/gpio.h
+++ b/src/mainboard/google/ocelot/variants/baseboard/ocelot/include/baseboard/gpio.h
@@ -22,6 +22,8 @@
  #define EC_SYNC_IRQ	GPP_E08_IRQ
 #elif CONFIG(BOARD_GOOGLE_MODEL_MATSU)
  #define EC_SYNC_IRQ	GPP_E08_IRQ
+#elif CONFIG(BOARD_GOOGLE_MODEL_OCICAT)
+ #define EC_SYNC_IRQ	GPP_E08_IRQ
 #endif
 #define GPIO_PCH_WP	GPP_D02
 #define GPIO_SLP_S0_GATE	GPP_C08
diff --git a/src/mainboard/google/ocelot/variants/ocicat/Makefile.mk b/src/mainboard/google/ocelot/variants/ocicat/Makefile.mk
new file mode 100644
index 0000000000..1ec5666ec1
--- /dev/null
+++ b/src/mainboard/google/ocelot/variants/ocicat/Makefile.mk
@@ -0,0 +1,11 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
+bootblock-y += gpio.c
+romstage-y += gpio.c
+romstage-y += memory.c
+romstage-$(CONFIG_FW_CONFIG) += fw_config.c
+romstage-$(CONFIG_CHROMEOS_DRAM_PART_NUMBER_IN_CBI) += part_num_to_dram_id.c
+ramstage-y += gpio.c
+romstage-$(CONFIG_FW_CONFIG) += variant.c
+ramstage-$(CONFIG_FW_CONFIG) += variant.c
+ramstage-$(CONFIG_FW_CONFIG) += fw_config.c
diff --git a/src/mainboard/google/ocelot/variants/ocicat/fw_config.c b/src/mainboard/google/ocelot/variants/ocicat/fw_config.c
new file mode 100644
index 0000000000..8c207ed5e2
--- /dev/null
+++ b/src/mainboard/google/ocelot/variants/ocicat/fw_config.c
@@ -0,0 +1,28 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <baseboard/variants.h>
+#include <console/console.h>
+#include <fw_config.h>
+#include <gpio.h>
+#include <inttypes.h>
+
+/* t: base table; o: override table */
+#define GPIO_PADBASED_OVERRIDE(t, o) gpio_padbased_override(t, o, ARRAY_SIZE(o))
+/* t: table */
+#define GPIO_CONFIGURE_PADS(t) gpio_configure_pads(t, ARRAY_SIZE(t))
+
+void fw_config_configure_pre_mem_gpio(void)
+{
+	if (!fw_config_is_provisioned()) {
+		printk(BIOS_WARNING, "FW_CONFIG is not provisioned, Exiting\n");
+		return;
+	}
+}
+
+void fw_config_gpio_padbased_override(struct pad_config *padbased_table)
+{
+	if (!fw_config_is_provisioned()) {
+		printk(BIOS_WARNING, "FW_CONFIG is not provisioned, Exiting\n");
+		return;
+	}
+}
diff --git a/src/mainboard/google/ocelot/variants/ocicat/gpio.c b/src/mainboard/google/ocelot/variants/ocicat/gpio.c
new file mode 100644
index 0000000000..3e21608c6d
--- /dev/null
+++ b/src/mainboard/google/ocelot/variants/ocicat/gpio.c
@@ -0,0 +1,425 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <baseboard/gpio.h>
+#include <baseboard/variants.h>
+#include <boardid.h>
+#include <soc/gpio.h>
+
+/* Pad configuration in ramstage*/
+static const struct pad_config gpio_table[] = {
+	/* GPP_A */
+	/* GPP_A00:     ESPI_IO0_AIC */
+	/*  GPP_A00 : GPP_A00 ==> ESPI_IO0_EC_R configured on reset, do not touch */
+
+	/* GPP_A01:     ESPI_IO1_AIC */
+	/*  GPP_A01 : GPP_A01 ==> ESPI_IO1_EC_R configured on reset, do not touch */
+
+	/* GPP_A02:     ESPI_IO2_AIC */
+	/*  GPP_A02 : GPP_A02 ==> ESPI_IO2_EC_R configured on reset, do not touch */
+
+	/* GPP_A03:     ESPI_IO3_AIC */
+	/*  GPP_A03 : GPP_A03 ==> ESPI_IO3_EC_R configured on reset, do not touch */
+
+	/* GPP_A04:     ESPI_CS0_AIC_N */
+	/*  GPP_A04 : GPP_A04 ==> ESPI_CS0_HDR_L configured on reset, do not touch */
+
+	/* GPP_A05:     ESPI_CLK_AIC */
+	/*  GPP_A05 : GPP_A05 ==> ESPI_CLK_HDR configured on reset, do not touch */
+
+	/* GPP_A06:     ESPI_RST_AIC_N */
+	/*  GPP_A06 : GPP_A06 ==> ESPI_RST_HDR configured on reset, do not touch */
+
+	/* GPP_A08:     M2_GEN4_SSD_RESET_N */
+	PAD_CFG_GPO(GPP_A08, 1, PLTRST),
+	/* GPP_A09:     NC */
+	PAD_NC(GPP_A09, NONE),
+	/* GPP_A10:     NC */
+	PAD_NC(GPP_A10, NONE),
+	/* GPP_A11:     WLAN_RST_N */
+	PAD_CFG_GPO(GPP_A11, 1, PLTRST),
+	/* GPP_A12:     NC */
+	PAD_NC(GPP_A12, NONE),
+	/* GPP_A13:     NC */
+	PAD_NC(GPP_A13, NONE),
+	/* GPP_A15:     NC */
+	PAD_NC(GPP_A15, NONE),
+
+	/* GPP_B */
+	/* GPP_B00:     USBC_SML_CLK_PD */
+	PAD_CFG_NF(GPP_B00, NONE, DEEP, NF1),
+	/* GPP_B01:     USBC_SML_DATA_PD */
+	PAD_CFG_NF(GPP_B01, NONE, DEEP, NF1),
+	/* GPP_B02:     NC */
+	PAD_NC(GPP_B02, NONE),
+	/* GPP_B03:     NC */
+	PAD_NC(GPP_B03, NONE),
+	/* GPP_B04:     NC */
+	PAD_NC(GPP_B04, NONE),
+	/* GPP_B05:     EC_ISH_INT_ODL */
+	PAD_CFG_NF(GPP_B05, NONE, DEEP, NF4),
+	/* GPP_B06:     NC */
+	PAD_NC(GPP_B06, NONE),
+	/* GPP_B07:     NC */
+	PAD_NC(GPP_B07, NONE),
+	/* GPP_B08:     NC */
+	PAD_NC(GPP_B08, NONE),
+	/* GPP_B09:     BT_RF_KILL_N */
+	PAD_CFG_GPO(GPP_B09, 1, DEEP),
+	/* GPP_B10:     NC */
+	PAD_NC(GPP_B10, NONE),
+	/* GPP_B12:     PM_SLP_S0_N */
+	PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1),
+	/* GPP_B13:     PLT_RST_N */
+	PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1),
+	/* GPP_B14:     GPP_B14_DDSP_HPDB */
+	PAD_CFG_NF(GPP_B14, NONE, DEEP, NF2),
+	/* GPP_B15:     NC */
+	PAD_NC(GPP_B15, NONE),
+	/* GPP_B16:     NC */
+	PAD_NC(GPP_B16, NONE),
+	/* GPP_B17:     NC */
+	PAD_NC(GPP_B17, NONE),
+	/* GPP_B18:     ISH_I2C2_SDA_SNSR_HDR */
+	PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_B18, NONE, DEEP, NF1),
+	/* GPP_B19:     ISH_I2C2_SCL_SNSR_HDR */
+	PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_B19, NONE, DEEP, NF1),
+	/* GPP_B20:     NC */
+	PAD_NC(GPP_B20, NONE),
+	/* GPP_B21:     NC */
+	PAD_NC(GPP_B21, NONE),
+	/* GPP_B22:     ISH_GP_5_SNSR_HDR */
+	PAD_CFG_NF(GPP_B22, NONE, DEEP, NF4),
+	/* GPP_B23:     NC */
+	PAD_NC(GPP_B23, NONE),
+	/* GPP_B24:     NC */
+	PAD_NC(GPP_B24, NONE),
+	/* GPP_B25:     NC */
+	PAD_NC(GPP_B25, NONE),
+
+	/* GPP_C */
+	/* GPP_C00:     SPD_SMB_CLK */
+	PAD_CFG_NF(GPP_C00, NONE, DEEP, NF1),
+	/* GPP_C01:     SPD_SMB_DATA */
+	PAD_CFG_NF(GPP_C01, NONE, DEEP, NF1),
+	/* GPP_C02:     NC */
+	PAD_NC(GPP_C02, NONE),
+	/* GPP_C03:     NC */
+	PAD_NC(GPP_C03, NONE),
+	/* GPP_C04:     NC */
+	PAD_NC(GPP_C04, NONE),
+	/* GPP_C05:     NC */
+	PAD_NC(GPP_C05, NONE),
+	/* GPP_C06:     NC */
+	PAD_NC(GPP_C06, NONE),
+	/* GPP_C07:     NC */
+	PAD_NC(GPP_C07, NONE),
+	/* GPP_C08:     PM_SLP_S0_N_GPP_CNTRL */
+	PAD_CFG_GPO(GPP_C08, 1, PLTRST),
+	/* GPP_C09:     CLKREQ0_X1_GEN4_M2_WLAN_N */
+	PAD_CFG_NF(GPP_C09, NONE, DEEP, NF1),
+	/* GPP_C10:     WIFI_RF_KILL_N */
+	PAD_CFG_GPO(GPP_C10, 1, DEEP),
+	/* GPP_C11:     NC */
+	PAD_NC(GPP_C11, NONE),
+	/* GPP_C12:     CLKREQ3_X4_GEN4_M2_SSD_N */
+	PAD_CFG_NF(GPP_C12, NONE, DEEP, NF1),
+	/* GPP_C13:     NC */
+	PAD_NC(GPP_C13, NONE),
+	/* GPP_C14:     NC */
+	PAD_NC(GPP_C14, NONE),
+	/* GPP_C15:     NC */
+	PAD_NC(GPP_C15, NONE),
+	/* GPP_C16:     NC */
+	PAD_NC(GPP_C16, NONE),
+	/* GPP_C17:     NC */
+	PAD_NC(GPP_C17, NONE),
+	/* GPP_C18:     NC */
+	PAD_NC(GPP_C18, NONE),
+	/* GPP_C19:     NC */
+	PAD_NC(GPP_C19, NONE),
+	/* GPP_C22:     DDPB_HDMI_CTRLCLK */
+	PAD_CFG_NF(GPP_C22, NONE, DEEP, NF2),
+	/* GPP_C23:     DDPB_HDMI_CTRLDATA */
+	PAD_CFG_NF(GPP_C23, NONE, DEEP, NF2),
+
+	/* GPP_D */
+	/* GPP_D01:     NC */
+	PAD_NC(GPP_D01, NONE),
+	/* GPP_D02:     SOC_WP_OD */
+	PAD_CFG_GPI(GPP_D02, NONE, DEEP),
+	/* GPP_D03:     NC */
+	PAD_NC(GPP_D03, NONE),
+	/* GPP_D05:     ISH_UART0_ECAIC_RXD */
+	PAD_CFG_NF(GPP_D05, NONE, DEEP, NF2),
+	/* GPP_D06:     ISH_UART0_ECAIC_TXD */
+	PAD_CFG_NF(GPP_D06, NONE, DEEP, NF2),
+	/* GPP_D07:     NC */
+	PAD_NC(GPP_D07, NONE),
+	/* GPP_D08:     NC */
+	PAD_NC(GPP_D08, NONE),
+	/* GPP_D09:     NC */
+	PAD_NC(GPP_D09, NONE),
+	/* GPP_D10:     HDA_BCLK_I2S0_SCLK */
+	PAD_CFG_NF(GPP_D10, NONE, DEEP, NF1),
+	/* GPP_D11:     HDA_SYNC_I2S0_SFRM*/
+	PAD_CFG_NF(GPP_D11, NONE, DEEP, NF1),
+	/* GPP_D12:     HDA_SDO_I2S0_TXD_STRAP */
+	PAD_CFG_NF(GPP_D12, NONE, DEEP, NF1),
+	/* GPP_D13:     HDA_HP_SDI0_R */
+	PAD_CFG_NF(GPP_D13, NONE, DEEP, NF1),
+	/* GPP_D16:     NC */
+	PAD_NC(GPP_D16, NONE),
+	/* GPP_D17:     NC */
+	PAD_NC(GPP_D17, NONE),
+	/* GPP_D19:     TCHSCR_REPORT_EN */
+	PAD_CFG_GPO(GPP_D19, 1, PLTRST),
+	/* GPP_D21:     GPP_D21_UFS_REFCLK_R */
+	PAD_CFG_NF(GPP_D21, NONE, DEEP, NF1),
+
+	/* GPP_E */
+	/* GPP_E01:     NC */
+	PAD_NC(GPP_E01, NONE),
+	/* GPP_E02:     SOC_VR_ALERT_ODL */
+	PAD_CFG_NF(GPP_E02, NONE, DEEP, NF2),
+	/* GPP_E03:     NC */
+	PAD_NC(GPP_E03, NONE),
+	/* GPP_E05:     NC */
+	PAD_NC(GPP_E05, NONE),
+	/* GPP_E06:     NC */
+	PAD_NC(GPP_E06, NONE),
+	/* GPP_E07:     LAN_PCIE_WAKE_ODL */
+	PAD_CFG_GPI_SCI_LOW_LOCK(GPP_E07, NONE, EDGE_SINGLE, LOCK_CONFIG),
+	/* GPP_E08:     EC_SOC_INT_ODL */
+	PAD_CFG_GPI_APIC_LOCK(GPP_E08, NONE, LEVEL, INVERT, LOCK_CONFIG),
+	/* GPP_E09:     USB_FP_CONN_1_CONN_2_OC0_N */
+	PAD_CFG_NF(GPP_E09, NONE, DEEP, NF1),
+	/* GPP_E10:     NC */
+	PAD_NC(GPP_E10, NONE),
+	/* GPP_E11:     NC */
+	PAD_NC(GPP_E11, NONE),
+	/* GPP_E12:     I2C_TCHPAD_SCL */
+	PAD_CFG_NF(GPP_E12, NONE, DEEP, NF8),
+	/* GPP_E13:     I2C_TCHPAD_SDA */
+	PAD_CFG_NF(GPP_E13, NONE, DEEP, NF8),
+	/* GPP_E14:     GSC_SOC_INT_ODL */
+	PAD_CFG_GPI_APIC(GPP_E14, NONE, PLTRST, LEVEL, INVERT),
+	/* GPP_E15:     NC */
+	PAD_NC(GPP_E15, NONE),
+	/* GPP_E16:     NC */
+	PAD_NC(GPP_E16, NONE),
+	/* GPP_E17:     NC */
+	PAD_NC(GPP_E17, NONE),
+	/* GPP_E18:     THC0_SPI1_INT_N_TCH_PNL1 */
+	PAD_CFG_NF(GPP_E18, NONE, DEEP, NF3),
+	/* GPP_E19:     NC */
+	PAD_NC(GPP_E19, NONE),
+	/* GPP_E20:     NC */
+	PAD_NC(GPP_E20, NONE),
+	/* GPP_E21:     I2C_PMC_PD_INT_N */
+	PAD_CFG_NF(GPP_E21, NONE, DEEP, NF1),
+	/* GPP_E22:     NC */
+	PAD_NC(GPP_E22, NONE),
+
+	/* GPP_F */
+	/* GPP_F00:     M.2_CNV_BRI_DT_BT_UART2_RTS_N */
+	PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_F00, NONE, DEEP, NF1),
+	/* GPP_F01:     M.2_CNV_BRI_RSP_BT_UART2_RXD */
+	PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_F01, NONE, DEEP, NF1),
+	/* GPP_F02:     M.2_CNV_RGI_DT_BT_UART2_TXD */
+	PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_F02, NONE, DEEP, NF1),
+	/* GPP_F03:     M.2_CNV_RGI_RSP_BT_UART2_CTS_N */
+	PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_F03, NONE, DEEP, NF1),
+	/* GPP_F04:     CNV_RF_RESET_R_N */
+	PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_F04, NONE, DEEP, NF1),
+	/* GPP_F05:     CRF_CLKREQ_R */
+	PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_F05, NONE, DEEP, NF3),
+	/* GPP_F06:     NC */
+	PAD_NC(GPP_F06, NONE),
+	/* GPP_F07:     NC */
+	PAD_NC(GPP_F07, NONE),
+	/* GPP_F08:     TCH_PNL1_PWR_EN */
+	PAD_CFG_GPO(GPP_F08, 1, PLTRST),
+	/* GPP_F09:     M2_UFS_RST_N */
+	PAD_CFG_GPO(GPP_F09, 1, DEEP),
+	/* GPP_F10:     ISH_ACCEL_MB_INT_L */
+	PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_F05, NONE, DEEP, NF8),
+	/* GPP_F11:     NC */
+	PAD_NC(GPP_F11, NONE),
+	/* GPP_F12:     THC_I2C1_SCL_TCH_PAD */
+	PAD_CFG_NF(GPP_F12, NONE, DEEP, NF8),
+	/* GPP_F13:     THC_I2C1_SDA_TCH_PAD */
+	PAD_CFG_NF(GPP_F13, NONE, DEEP, NF8),
+	/* GPP_F14:     NC */
+	PAD_NC(GPP_F14, NONE),
+	/* GPP_F15:     NC */
+	PAD_NC(GPP_F15, NONE),
+	/* GPP_F16:     TCHSCR_RST_ODL */
+	PAD_CFG_NF(GPP_F16, NONE, DEEP, NF3),
+	/* GPP_F17:     NC */
+	PAD_NC(GPP_F17, NONE),
+	/* GPP_F18:     TCHSCR_INT_ODL */
+	PAD_CFG_NF(GPP_F18, NONE, DEEP, NF3),
+	/* GPP_F19:     NC */
+	PAD_NC(GPP_F19, NONE),
+	/* GPP_F20:     CSE_EARLY_SW */
+	PAD_CFG_GPI(GPP_F20, NONE, DEEP),
+	/* GPP_F22:     NC */
+	PAD_NC(GPP_F22, NONE),
+	/* GPP_F23:     NC */
+	PAD_NC(GPP_F23, NONE),
+
+	/* GPP_H */
+	/* GPP_H00:     NC */
+	PAD_NC(GPP_H00, NONE),
+	/* GPP_H01:     NC */
+	PAD_NC(GPP_H01, NONE),
+	/* GPP_H02:     NC */
+	PAD_NC(GPP_H02, NONE),
+	/* GPP_H03:     NC */
+	PAD_NC(GPP_H03, NONE),
+	/* GPP_H04:     NC */
+	PAD_NC(GPP_H04, NONE),
+	/* GPP_H05:     NC */
+	PAD_NC(GPP_H05, NONE),
+	/* GPP_H06:     NC */
+	PAD_NC(GPP_H06, NONE),
+	/* GPP_H07:     NC */
+	PAD_NC(GPP_H07, NONE),
+	/* GPP_H08:     SOC_BIOS_LOG_TTK_UART_RX */
+	PAD_CFG_NF(GPP_H08, NONE, DEEP, NF1),
+	/* GPP_H09:     SOC_BIOS_LOG_TTK_UART_TX */
+	PAD_CFG_NF(GPP_H09, NONE, DEEP, NF1),
+	/* GPP_H10:     NC */
+	PAD_NC(GPP_H10, NONE),
+	/* GPP_H11:     NC */
+	PAD_NC(GPP_H11, NONE),
+	/* GPP_H13:     CPU_C10_GATE_N_R */
+	PAD_CFG_NF(GPP_H13, NONE, DEEP, NF1),
+	/* GPP_H14:     NC */
+	PAD_NC(GPP_H14, NONE),
+	/* GPP_H15:     NC */
+	PAD_NC(GPP_H15, NONE),
+	/* GPP_H17:     NC */
+	PAD_NC(GPP_H17, NONE),
+	/* GPP_H18:     GEN4_SSD_PWREN */
+	PAD_CFG_GPO(GPP_H18, 1, DEEP),
+	/* GPP_H19:     NC */
+	PAD_NC(GPP_H19, NONE),
+	/* GPP_H20:     NC */
+	PAD_NC(GPP_H20, NONE),
+	/* GPP_H21:     I2C1_SDA_TTK_CHROME */
+	PAD_CFG_NF(GPP_H21, NONE, DEEP, NF1),
+	/* GPP_H22:     I2C1_SCL_TTK_CHROME */
+	PAD_CFG_NF(GPP_H22, NONE, DEEP, NF1),
+	/* GPP_H23:     NC */
+	PAD_NC(GPP_H23, NONE),
+	/* GPP_H24:     NC */
+	PAD_NC(GPP_H24, NONE),
+
+	/* GPP_S */
+	/* GPP_S00:     NC */
+	PAD_NC(GPP_S00, NONE),
+	/* GPP_S01:     NC */
+	PAD_NC(GPP_S01, NONE),
+	/* GPP_S02:     NC */
+	PAD_NC(GPP_S02, NONE),
+	/* GPP_S03:     NC */
+	PAD_NC(GPP_S03, NONE),
+	/* GPP_S04:	DMIC_CLK_A0 */
+	PAD_CFG_NF(GPP_S04, NONE, DEEP, NF5),
+	/* GPP_S05:	DMIC_DATA_0 */
+	PAD_CFG_NF(GPP_S05, NONE, DEEP, NF5),
+	/* GPP_S06:     NC */
+	PAD_NC(GPP_S06, NONE),
+	/* GPP_S07:     NC */
+	PAD_NC(GPP_S07, NONE),
+
+	/* GPP_V */
+	/* GPP_V00:     PM_BATLOW_N */
+	PAD_CFG_NF(GPP_V00, NONE, DEEP, NF1),
+	/* GPP_V01:     BC_ACOK_MCP */
+	PAD_CFG_NF(GPP_V01, NONE, DEEP, NF1),
+	/* GPP_V02:     LANWAKE_N_R */
+	PAD_CFG_NF(GPP_V02, NONE, DEEP, NF1),
+	/* GPP_V03:     PWRBTN_MCP_N */
+	PAD_CFG_NF(GPP_V03, NONE, DEEP, NF1),
+	/* GPP_V04:     PM_SLP_S3_N */
+	PAD_CFG_NF(GPP_V04, NONE, DEEP, NF1),
+	/* GPP_V05:     PM_SLP_S4_N */
+	PAD_CFG_NF(GPP_V05, NONE, DEEP, NF1),
+	/* GPP_V06:     PM_SLP_A_N */
+	PAD_NC(GPP_V06, NONE),
+	/* GPP_V07:     M.2_BTWIFI_SUS_CLK_LS */
+	PAD_CFG_NF(GPP_V07, NONE, DEEP, NF1),
+	/* GPP_V08:     NC */
+	PAD_NC(GPP_V08, NONE),
+	/* GPP_V09:     PM_SLP_S5_N */
+	PAD_CFG_NF(GPP_V09, NONE, DEEP, NF1),
+	/* GPP_V10:     NC */
+	PAD_NC(GPP_V10, NONE),
+	/* GPP_V11:     NC */
+	PAD_NC(GPP_V11, NONE),
+	/* GPP_V12:     WAKE_N */
+	PAD_CFG_NF(GPP_V12, NONE, DEEP, NF1),
+	/* GPP_V13:     NC */
+	PAD_NC(GPP_V13, NONE),
+	/* GPP_V14:     NC */
+	PAD_NC(GPP_V14, NONE),
+	/* GPP_V15:     NC */
+	PAD_NC(GPP_V15, NONE),
+	/* GPP_V16:     GPP_V16_VCCST_EN */
+	PAD_CFG_NF(GPP_V16, NONE, DEEP, NF1),
+};
+
+/* Early pad configuration in bootblock */
+static const struct pad_config early_gpio_table[] = {
+	/* GPP_E14:     GSC_SOC_INT_ODL */
+	PAD_CFG_GPI_APIC(GPP_E14, NONE, PLTRST, LEVEL, INVERT),
+	/* GPP_H08:     SOC_BIOS_LOG_TTK_UART_RX */
+	PAD_CFG_NF(GPP_H08, NONE, DEEP, NF1),
+	/* GPP_H09:     SOC_BIOS_LOG_TTK_UART_TX */
+	PAD_CFG_NF(GPP_H09, NONE, DEEP, NF1),
+	/* GPP_H21:     I2C1_SDA_TTK_CHROME */
+	PAD_CFG_NF(GPP_H21, NONE, DEEP, NF1),
+	/* GPP_H22:     I2C1_SCL_TTK_CHROME */
+	PAD_CFG_NF(GPP_H22, NONE, DEEP, NF1),
+};
+
+/* Pad configuration in romstage */
+static const struct pad_config romstage_gpio_table[] = {
+	/* GPP_C00:     SPD_SMB_CLK */
+	PAD_CFG_NF(GPP_C00, NONE, DEEP, NF1),
+	/* GPP_C01:     SPD_SMB_DATA */
+	PAD_CFG_NF(GPP_C01, NONE, DEEP, NF1),
+	/* GPP_C15:     FPS_RST_N */
+	PAD_NC(GPP_C15, NONE),
+};
+
+const struct pad_config *variant_gpio_table(size_t *num)
+{
+	*num = ARRAY_SIZE(gpio_table);
+	return gpio_table;
+}
+
+const struct pad_config *variant_early_gpio_table(size_t *num)
+{
+	*num = ARRAY_SIZE(early_gpio_table);
+	return early_gpio_table;
+}
+
+/* Create the stub for romstage gpio, typically use for power sequence */
+const struct pad_config *variant_romstage_gpio_table(size_t *num)
+{
+	*num = ARRAY_SIZE(romstage_gpio_table);
+	return romstage_gpio_table;
+}
+
+static const struct cros_gpio cros_gpios[] = {
+	CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE0_NAME),
+	CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE1_NAME),
+	CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE2_NAME),
+	CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE3_NAME),
+	CROS_GPIO_WP_AH(GPIO_PCH_WP, CROS_GPIO_DEVICE4_NAME),
+};
+
+DECLARE_CROS_GPIOS(cros_gpios);
diff --git a/src/mainboard/google/ocelot/variants/ocicat/hda_verb.c b/src/mainboard/google/ocelot/variants/ocicat/hda_verb.c
new file mode 100644
index 0000000000..2f703b78ee
--- /dev/null
+++ b/src/mainboard/google/ocelot/variants/ocicat/hda_verb.c
@@ -0,0 +1,126 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <device/azalia_device.h>
+
+const u32 cim_verb_data[] = {
+	/* coreboot specific header */
+	0x10ec0256,	/* Codec Vendor / Device ID: Realtek ALC256 */
+	0x10ec12ac,	/* Subsystem ID */
+	0x00000013,	/* Number of jacks (NID entries) */
+
+	AZALIA_RESET(0x1),
+	/* NID 0x01, HDA Codec Subsystem ID Verb Table */
+	AZALIA_SUBVENDOR(0, 0x10ec12ac),
+
+	/* Pin Widget Verb Table */
+	/*
+	 * DMIC
+	 * Requirement is to use PCH DMIC. Hence,
+	 * commented out codec's Internal DMIC.
+	 * AZALIA_PIN_CFG(0, 0x12, 0x90A60130),
+	 * AZALIA_PIN_CFG(0, 0x13, 0x40000000),
+	 */
+	/* Pin widget 0x14 - Front (Port-D) */
+	AZALIA_PIN_CFG(0, 0x14, 0x90170110),
+	/* Pin widget 0x18 - NPC */
+	AZALIA_PIN_CFG(0, 0x18, 0x411111F0),
+	/* Pin widget 0x19 - MIC2 (Port-F) */
+	AZALIA_PIN_CFG(0, 0x19, 0x04A11040),
+	/* Pin widget 0x1A - LINE1 (Port-C) */
+	AZALIA_PIN_CFG(0, 0x1a, 0x411111F0),
+	/* Pin widget 0x1B - NPC */
+	AZALIA_PIN_CFG(0, 0x1b, 0x411111F0),
+	/* Pin widget 0x1D - BEEP-IN */
+	AZALIA_PIN_CFG(0, 0x1d, 0x40610041),
+	/* Pin widget 0x1E - NPC */
+	AZALIA_PIN_CFG(0, 0x1e, 0x411111F0),
+	/* Pin widget 0x21 - HP1-OUT (Port-I) */
+	AZALIA_PIN_CFG(0, 0x21, 0x04211020),
+	/*
+	 * Widget node 0x20 - 1
+	 * Codec hidden reset and speaker power 2W/4ohm
+	 */
+	0x0205001A,
+	0x0204C003,
+	0x02050038,
+	0x02047901,
+	/*
+	 * Widget node 0x20 - 2
+	 * Class D power on Reset
+	 */
+	0x0205003C,
+	0x02040354,
+	0x0205003C,
+	0x02040314,
+	/*
+	 * Widget node 0x20 - 3
+	 * Disable AGC and set AGC limit to -1.5dB
+	 */
+	0x02050016,
+	0x02040C50,
+	0x02050012,
+	0x0204EBC1,
+	/*
+	 * Widget node 0x20 - 4
+	 * Set AGC Post gain +1.5dB then Enable AGC
+	 */
+	0x02050013,
+	0x02044023,
+	0x02050016,
+	0x02040E50,
+	/*
+	 * Widget node 0x20 - 5
+	 * Silence detector enabling + Set EAPD to verb control
+	 */
+	0x02050037,
+	0x0204FE15,
+	0x02050010,
+	0x02040020,
+	/*
+	 * Widget node 0x20 - 6
+	 * Silence data mode Threshold (-90dB)
+	 */
+	0x02050030,
+	0x0204A000,
+	0x0205001B,
+	0x02040A4B,
+	/*
+	 * Widget node 0x20 - 7
+	 * Default setting-1
+	 */
+	0x05750003,
+	0x05740DA3,
+	0x02050046,
+	0x02040004,
+	/*
+	 * Widget node 0x20 - 8
+	 * support 1 pin detect two port
+	 */
+	0x02050009,
+	0x0204E003,
+	0x0205000A,
+	0x02047770,
+	/*
+	 * Widget node 0x20 - 9
+	 * To set LDO1/LDO2 as default
+	 */
+	0x02050008,
+	0x02046A0C,
+	0x02050008,
+	0x02046A0C,
+};
+
+const u32 pc_beep_verbs[] = {
+	/* Dos beep path - 1 */
+	0x01470C00,
+	0x02050036,
+	0x02047151,
+	0x01470740,
+	/* Dos beep path - 2 */
+	0x0143b000,
+	0x01470C02,
+	0x01470C02,
+	0x01470C02,
+};
+
+AZALIA_ARRAY_SIZES;
diff --git a/src/mainboard/google/ocelot/variants/ocicat/include/variant/ec.h b/src/mainboard/google/ocelot/variants/ocicat/include/variant/ec.h
new file mode 100644
index 0000000000..4fc0622f15
--- /dev/null
+++ b/src/mainboard/google/ocelot/variants/ocicat/include/variant/ec.h
@@ -0,0 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#ifndef MAINBOARD_EC_H
+#define MAINBOARD_EC_H
+
+#include <baseboard/ec.h>
+
+#endif /* MAINBOARD_GPIO_H */
diff --git a/src/mainboard/google/ocelot/variants/ocicat/include/variant/gpio.h b/src/mainboard/google/ocelot/variants/ocicat/include/variant/gpio.h
new file mode 100644
index 0000000000..cced66807a
--- /dev/null
+++ b/src/mainboard/google/ocelot/variants/ocicat/include/variant/gpio.h
@@ -0,0 +1,11 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#ifndef __MAINBOARD_GPIO_H__
+#define __MAINBOARD_GPIO_H__
+
+#include <baseboard/gpio.h>
+
+/* EC wake is LAN_WAKE# which is a special DeepSX wake pin */
+#define GPE_EC_WAKE	GPE0_LAN_WAK
+
+#endif /* __MAINBOARD_GPIO_H__ */
diff --git a/src/mainboard/google/ocelot/variants/ocicat/memory.c b/src/mainboard/google/ocelot/variants/ocicat/memory.c
new file mode 100644
index 0000000000..263588c4ac
--- /dev/null
+++ b/src/mainboard/google/ocelot/variants/ocicat/memory.c
@@ -0,0 +1,36 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <baseboard/variants.h>
+#include <boardid.h>
+#include <soc/meminit.h>
+#include <soc/romstage.h>
+
+#define SMBUS_ADDR_DIMM	0x50
+
+static const struct mb_cfg ddr5_mem_config = {
+	.type = MEM_TYPE_DDR5,
+
+	.ect = true, /* Early Command Training */
+
+	.user_bd = BOARD_TYPE_ULT_ULX,
+
+	.ddr_config = {
+		.dq_pins_interleaved = false,
+	},
+
+	.rcomp = {
+		.resistor = 100,
+	},
+};
+
+const struct mb_cfg *variant_memory_params(void)
+{
+	return &ddr5_mem_config;
+}
+
+void variant_get_spd_info(struct mem_spd *spd_info)
+{
+	spd_info->topo = MEM_TOPO_DIMM_MODULE;
+	spd_info->smbus[0].addr_dimm[0] = SMBUS_ADDR_DIMM;
+	spd_info->smbus[1].addr_dimm[0] = SMBUS_ADDR_DIMM;
+}
diff --git a/src/mainboard/google/ocelot/variants/ocicat/overridetree.cb b/src/mainboard/google/ocelot/variants/ocicat/overridetree.cb
new file mode 100644
index 0000000000..99a73e6956
--- /dev/null
+++ b/src/mainboard/google/ocelot/variants/ocicat/overridetree.cb
@@ -0,0 +1,421 @@
+fw_config
+	field STORAGE 13 14
+		option STORAGE_UNKNOWN			0
+		option STORAGE_NVME_GEN4		1
+		option STORAGE_UFS			2
+	end
+end
+
+chip soc/intel/pantherlake
+
+	register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Type C port - various configurations - TCP0
+	register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Type C port - various configurations - TCP1
+	register "usb2_ports[2]" = "USB2_PORT_MID(OC0)" # USB3.2 Gen2x1 Type-A Port - TAP1 Vertical CONN
+	register "usb2_ports[4]" = "USB2_PORT_MID(OC_SKIP)" # UFC
+	register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # Discrete Bluetooth
+
+	register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)" # USB 3.2 Gen2 x1 Type-A Con - # 1
+
+	register "tcss_ports[0]" = "TCSS_PORT_DEFAULT(OC_SKIP)" # Type-C Port 1 (Virtual OC)
+	register "tcss_ports[1]" = "TCSS_PORT_DEFAULT(OC_SKIP)" # Type-C Port 2 (Virtual OC)
+
+	register "tcss_cap_policy[0]" = "TCSS_TYPE_C_PORT_FULL_FUN"
+	register "tcss_cap_policy[1]" = "TCSS_TYPE_C_PORT_FULL_FUN"
+
+	# Enable EDP in PortA & HDMI in Port B
+	register "ddi_port_A_config" = "1"
+	register "ddi_port_B_config" = "1"
+	register "ddi_ports_config" = "{
+		[DDI_PORT_A] = DDI_ENABLE_HPD,
+		[DDI_PORT_B] = DDI_ENABLE_HPD | DDI_ENABLE_DDC,
+	}"
+
+	register "serial_io_i2c_mode" = "{
+		[PchSerialIoIndexI2C0]  = PchSerialIoPci,
+		[PchSerialIoIndexI2C1]  = PchSerialIoPci,
+		[PchSerialIoIndexI2C2]  = PchSerialIoDisabled,
+		[PchSerialIoIndexI2C3]  = PchSerialIoDisabled,
+		[PchSerialIoIndexI2C4]  = PchSerialIoPci,
+		[PchSerialIoIndexI2C5]  = PchSerialIoPci,
+	}"
+
+	register "serial_io_gspi_mode" = "{
+		[PchSerialIoIndexGSPI0] = PchSerialIoPci,
+		[PchSerialIoIndexGSPI1] = PchSerialIoDisabled,
+		[PchSerialIoIndexGSPI0A] = PchSerialIoDisabled,
+	}"
+
+	# Intel Common SoC Config
+	#+-------------------+---------------------------+
+	#| Field             |  Value                    |
+	#+-------------------+---------------------------+
+	#| I2C1              | TPM(cr50)                 |
+	#| I2C4              | Touchpad                  |
+	#| I2C5              | TouchScreen               |
+	#+-------------------+---------------------------+
+	register "common_soc_config" = "{
+		/* Render OEM footer logo 100px above from the edge */
+		.logo_bottom_margin = 100,
+		.chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT,
+		.i2c[1] = {
+			.speed = I2C_SPEED_FAST,
+			.early_init = 1,
+		},
+		.i2c[4] = {
+			.speed = I2C_SPEED_FAST,
+		},
+		.i2c[5] = {
+			.speed = I2C_SPEED_FAST,
+		},
+	}"
+
+	device domain 0 on
+		device ref igpu on
+			chip drivers/gfx/generic
+				register "device_count" = "4"
+				# DDIA for eDP
+				register "device[0].name" = ""LCD0""
+				register "device[0].type" = "panel"
+				# DDIB for HDMI
+				# If HDMI is not enumerated in the kernel, then no GFX device should be added for DDIB
+				register "device[1].name" = ""DD01""
+				# TCP0 (DP-1) for port C0
+				register "device[2].name" = ""DD02""
+				register "device[2].use_pld" = "true"
+				register "device[2].pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(1, 1))"
+				# TCP1 (DP-2) for port C1
+				register "device[3].name" = ""DD03""
+				register "device[3].use_pld" = "true"
+				register "device[3].pld" = "ACPI_PLD_TYPE_C(LEFT, RIGHT, ACPI_PLD_GROUP(2, 1))"
+
+				device generic 0 on end
+			end
+		end
+
+		device ref dtt on
+			chip drivers/intel/dptf
+				## sensor information
+				register "options.tsr[0].desc" = ""DDR_SOC""
+				register "options.tsr[1].desc" = ""Ambient""
+				register "options.tsr[2].desc" = ""Charger""
+				register "options.tsr[3].desc" = ""wwan""
+
+				## Active Policy
+				# FIXME: below values are initial reference values only
+				register "policies.active" = "{
+						[0] = {
+							.target = DPTF_TEMP_SENSOR_0,
+							.thresholds = {
+									TEMP_PCT(70, 97),
+									TEMP_PCT(65, 90),
+									TEMP_PCT(60, 80),
+									TEMP_PCT(55, 75),
+									TEMP_PCT(50, 65),
+									TEMP_PCT(45, 45),
+									TEMP_PCT(43, 30),
+								}
+							},
+						[1] = {
+							.target = DPTF_TEMP_SENSOR_1,
+							.thresholds = {
+									TEMP_PCT(70, 97),
+									TEMP_PCT(65, 90),
+									TEMP_PCT(60, 80),
+									TEMP_PCT(55, 75),
+									TEMP_PCT(50, 65),
+									TEMP_PCT(45, 45),
+									TEMP_PCT(43, 30),
+								}
+							},
+						[2] = {
+							.target = DPTF_TEMP_SENSOR_2,
+							.thresholds = {
+									TEMP_PCT(75, 90),
+									TEMP_PCT(70, 80),
+									TEMP_PCT(65, 70),
+									TEMP_PCT(60, 50),
+								}
+							},
+						[3] = {
+							.target = DPTF_TEMP_SENSOR_3,
+							.thresholds = {
+									TEMP_PCT(75, 90),
+									TEMP_PCT(70, 80),
+									TEMP_PCT(65, 70),
+									TEMP_PCT(60, 60),
+									TEMP_PCT(55, 50),
+									TEMP_PCT(50, 40),
+									TEMP_PCT(45, 30),
+								}
+							}
+				}"
+
+				## Passive Policy
+				# TODO: below values are initial reference values only
+				register "policies.passive" = "{
+						[0] = DPTF_PASSIVE(CPU,         CPU,           95, 5000),
+						[1] = DPTF_PASSIVE(CPU,         TEMP_SENSOR_0, 80, 5000),
+						[2] = DPTF_PASSIVE(CPU,         TEMP_SENSOR_1, 80, 5000),
+						[3] = DPTF_PASSIVE(CHARGER,     TEMP_SENSOR_2, 75, 5000),
+						[4] = DPTF_PASSIVE(CPU,         TEMP_SENSOR_3, 80, 5000),
+				}"
+
+				## Critical Policy
+				# TODO: below values are initial reference values only
+				register "policies.critical" = "{
+						[0] = DPTF_CRITICAL(CPU,          105, SHUTDOWN),
+						[1] = DPTF_CRITICAL(TEMP_SENSOR_0, 85, SHUTDOWN),
+						[2] = DPTF_CRITICAL(TEMP_SENSOR_1, 85, SHUTDOWN),
+						[3] = DPTF_CRITICAL(TEMP_SENSOR_2, 85, SHUTDOWN),
+						[4] = DPTF_CRITICAL(TEMP_SENSOR_3, 85, SHUTDOWN),
+				}"
+
+				## Power Limits Control
+				register "controls.power_limits" = "{
+						.pl1 = {
+							.min_power = 25000,
+							.max_power = 25000,
+							.time_window_min = 28 * MSECS_PER_SEC,
+							.time_window_max = 32 * MSECS_PER_SEC,
+							.granularity = 200,
+						},
+						.pl2 = {
+							.min_power = 95000,
+							.max_power = 95000,
+							.time_window_min = 28 * MSECS_PER_SEC,
+							.time_window_max = 32 * MSECS_PER_SEC,
+							.granularity = 1000,
+						}
+				}"
+
+				## Charger Performance Control (Control, mA)
+				register "controls.charger_perf" = "{
+						[0] = { 255, 3000 },
+						[1] = {  24, 1500 },
+						[2] = {  16, 1000 },
+						[3] = {   8,  500 }
+				}"
+
+				## Fan Performance Control (Percent, Speed, Noise, Power)
+				register "controls.fan_perf" = "{
+						[0] = {  90, 6700, 220, 2200, },
+						[1] = {  80, 5800, 180, 1800, },
+						[2] = {  70, 5000, 145, 1450, },
+						[3] = {  60, 4900, 115, 1150, },
+						[4] = {  50, 3838,  90,  900, },
+						[5] = {  40, 2904,  55,  550, },
+						[6] = {  30, 2337,  30,  300, },
+						[7] = {  20, 1608,  15,  150, },
+						[8] = {  10,  800,  10,  100, },
+						[9] = {   0,    0,   0,   50, }
+				}"
+
+				## Fan options
+				register "options.fan.fine_grained_control" = "true"
+				register "options.fan.step_size" = "2"
+
+				device generic 0 alias dptf_policy on end
+			end
+		end
+
+		device ref iaa off end
+
+		device ref thc0 on
+			register "thc_wake_on_touch[0]" = "true"
+			# THC0 is function 0; hence it needs to be enabled when THC1 is to be enabled.
+			chip drivers/intel/touch
+				register "name" = "INTEL_THC0_NAME"
+				register "mode" = "THC_HID_I2C_MODE"
+				register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_F08)"
+				register "enable_delay_ms" = "2"
+				register "enable_off_delay_ms" = "2"
+				register "wake_on_touch" = "true"
+				# NOTE: Use GpioInt() in _CRS and does not use GPE.
+				register "wake_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW_WAKE(GPP_VGPIO3_THC0)"
+				register "active_ltr" = "1"
+				register "idle_ltr" = "0"
+				register "connected_device" = "TH_SENSOR_ELAN"
+				register "add_acpi_dma_property" = "true"
+				device generic 0 alias touch_0_i2c_elan on end
+			end
+		end
+		device ref thc1 on
+			register "thc_wake_on_touch[1]" = "true"
+			chip drivers/intel/touch
+				register "name" = "INTEL_THC1_NAME"
+				register "mode" = "THC_HID_I2C_MODE"
+				register "wake_on_touch" = "true"
+				# NOTE: Use GpioInt() in _CRS and does not use GPE.
+				register "wake_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW_WAKE(GPP_VGPIO3_THC1)"
+				register "active_ltr" = "1"
+				register "idle_ltr" = "0"
+				register "connected_device" = "TH_SENSOR_HYNITRON"
+				register "add_acpi_dma_property" = "true"
+				device generic 0 alias touch_1_i2c_hynitron on end
+			end
+		end
+
+		device ref tbt_pcie_rp0 on end
+		device ref tbt_pcie_rp1 on end
+		device ref tcss_xhci on
+			chip drivers/usb/acpi
+				device ref tcss_root_hub on
+					chip drivers/usb/acpi
+						register "desc" = ""USB3 Type-C Port C0""
+						register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
+						register "group" = "ACPI_PLD_GROUP(2, 2)"
+						device ref tcss_usb3_port0 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB3 Type-C Port C1""
+						register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
+						register "group" = "ACPI_PLD_GROUP(1, 2)"
+						device ref tcss_usb3_port1 on end
+					end
+				end
+			end
+		end
+
+		device ref ish on
+			chip drivers/intel/ish
+				register "add_acpi_dma_property" = "true"
+				device generic 0 on end
+			end
+		end
+
+		device ref xhci on
+			chip drivers/usb/acpi
+				device ref xhci_root_hub on
+					chip drivers/usb/acpi
+						register "desc" = ""USB2 Type-C Port C0""
+						register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
+						register "group" = "ACPI_PLD_GROUP(1, 1)"
+						device ref usb2_port1 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB2 Type-C Port C1""
+						register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
+						register "group" = "ACPI_PLD_GROUP(2, 1)"
+						device ref usb2_port2 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB2 Type-A Port 1""
+						register "type" = "UPC_TYPE_A"
+						register "group" = "ACPI_PLD_GROUP(3, 1)"
+						device ref usb2_port3 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB2 Camera""
+						register "type" = "UPC_TYPE_INTERNAL"
+						device ref usb2_port5 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB2 Bluetooth""
+						register "type" = "UPC_TYPE_INTERNAL"
+						register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B09)"
+						device ref usb2_port8 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB3 Type-A Port 1""
+						register "type" = "UPC_TYPE_USB3_A"
+						register "group" = "ACPI_PLD_GROUP(1, 2)"
+						device ref usb3_port1 on end
+					end
+				end
+			end
+		end
+
+		device ref ufs on
+			probe STORAGE STORAGE_UFS
+			probe STORAGE STORAGE_UNKNOWN
+		end
+
+		device ref pcie_rp1 on
+			probe STORAGE STORAGE_NVME_GEN4
+			probe STORAGE STORAGE_UNKNOWN
+			register "pcie_rp[PCIE_RP(1)]" = "{
+			.clk_src = 3,
+			.clk_req = 3,
+			.flags = PCIE_RP_CLK_REQ_DETECT | PCIE_RP_LTR | PCIE_RP_AER,
+			}"
+			chip soc/intel/common/block/pcie/rtd3
+				register "is_storage" = "true"
+				register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_H18)"
+				register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A08)"
+				register "srcclk_pin" = "3"
+				device generic 0 on end
+			end
+		end # Gen4 M.2 SSD
+
+		device ref cnvi_wifi on
+			chip drivers/wifi/generic
+				register "wake" = "GPE0_PME_B0"
+				register "add_acpi_dma_property" = "true"
+				register "enable_cnvi_ddr_rfim" = "true"
+				use cnvi_bluetooth as bluetooth_companion
+				device generic 0 on end
+			end
+		end # CNVi
+
+		# NOTE: i2c0 is function 0; hence it needs to be enabled when any of i2c1-5 is enabled.
+		# TPM device is under i2c1. Therefore, i2c0 needs to be enabled anyways.
+		device ref i2c0 on end
+		device ref i2c1 on
+			chip drivers/i2c/tpm
+				register "hid" = ""GOOG0005""
+				register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_E14_IRQ)"
+				device i2c 50 on end
+			end
+		end
+		device ref i2c4 on
+			chip drivers/i2c/generic
+				register "hid" = ""ELAN0000""
+				register "desc" = ""ELAN Touchpad""
+				register "irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_E18_IRQ)"
+				register "wake" = "GPE0_DW2_18"
+				register "detect" = "1"
+				device i2c 15 on end
+			end
+			chip drivers/i2c/hid
+				register "generic.hid" = ""SYNA0000""
+				register "generic.cid" = ""ACPI0C50""
+				register "generic.desc" = ""Synaptics Touchpad""
+				register "generic.irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_E18_IRQ)"
+				register "generic.wake" = "GPE0_DW2_18"
+				register "generic.detect" = "1"
+				register "hid_desc_reg_offset" = "0x20"
+				device i2c 0x2c on end
+			end
+		end # I2C4
+		device ref i2c5 on
+			chip drivers/i2c/hid
+				register "generic.hid" = ""ELAN9004""
+				register "generic.desc" = ""ELAN Touchscreen""
+				register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_F18_IRQ)"
+				register "generic.detect" = "1"
+				register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_F16)"
+				register "generic.reset_delay_ms" = "150"
+				register "generic.reset_off_delay_ms" = "2"
+				register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_F08)"
+				register "generic.enable_delay_ms" = "6"
+				register "generic.enable_off_delay_ms" = "1"
+				register "generic.stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D19)"
+				register "generic.stop_off_delay_ms" = "2"
+				register "generic.has_power_resource" = "1"
+				register "generic.use_gpio_for_status" = "true"
+				register "hid_desc_reg_offset" = "0x01"
+				device i2c 0x10 on end
+			end
+		end # I2C5
+
+		device ref smbus on end
+		device ref hda on
+			chip drivers/sof
+				register "spkr_tplg" = "max98360a"
+				register "jack_tplg" = "rt5682"
+				register "mic_tplg" = "_2ch_pdm0"
+				device generic 0 on end
+			end
+		end
+	end
+end
diff --git a/src/mainboard/google/ocelot/variants/ocicat/part_num_to_dram_id.c b/src/mainboard/google/ocelot/variants/ocicat/part_num_to_dram_id.c
new file mode 100644
index 0000000000..c73e5c9a12
--- /dev/null
+++ b/src/mainboard/google/ocelot/variants/ocicat/part_num_to_dram_id.c
@@ -0,0 +1,35 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <baseboard/variants.h>
+
+struct part_num_spd_index {
+	const char part_num[DIMM_INFO_PART_NUMBER_SIZE];
+	int spd_index;
+};
+
+static const struct part_num_spd_index part_number_map[] = {
+	{ "H58G56BK8BX068", 0 },
+	{ "H58G66BK7BX067", 1 },
+	{ "H58G66BK8BX067", 2 },
+	{ "H58GE6AK8BX104", 3 },
+	{ "H58G66CK8BX147", 2 },
+};
+
+int variant_memory_sku(void)
+{
+	int index;
+	size_t num_elements = ARRAY_SIZE(part_number_map);
+	const char *part_num = mainboard_get_dram_part_num();
+
+	if (part_num == NULL)
+		die("No part number in CBI, halting boot.\n");
+
+	for (index = 0; index < num_elements; index++) {
+		if (!strcmp(part_num, part_number_map[index].part_num))
+			/* exact match found */
+			return part_number_map[index].spd_index;
+	}
+
+	/* We didn't find a match for part_num, halt boot */
+	die("No part number found looking for %s, halting boot.\n", part_num);
+}
diff --git a/src/mainboard/google/ocelot/variants/ocicat/variant.c b/src/mainboard/google/ocelot/variants/ocicat/variant.c
new file mode 100644
index 0000000000..0bfbdf05ed
--- /dev/null
+++ b/src/mainboard/google/ocelot/variants/ocicat/variant.c
@@ -0,0 +1,48 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <baseboard/variants.h>
+#include <boardid.h>
+#include <ec/google/chromeec/ec.h>
+#include <fsp/api.h>
+#include <fw_config.h>
+#include <intelblocks/hda.h>
+#include <sar.h>
+#include <soc/gpio_soc_defs.h>
+#include <drivers/intel/touch/chip.h>
+
+void variant_update_soc_memory_init_params(FSPM_UPD *memupd)
+{
+	FSP_M_CONFIG *m_cfg = &memupd->FspmConfig;
+
+	/* Override FSP-M SaGv frequency and gear for DDR5 boards */
+	m_cfg->SaGvFreq[0] = 3200;
+	m_cfg->SaGvGear[0] = GEAR_4;
+
+	m_cfg->SaGvFreq[1] = 4800;
+	m_cfg->SaGvGear[1] = GEAR_4;
+
+	m_cfg->SaGvFreq[2] = 5600;
+	m_cfg->SaGvGear[2] = GEAR_4;
+
+	m_cfg->SaGvFreq[3] = 6400;
+	m_cfg->SaGvGear[3] = GEAR_4;
+
+	/*
+	 * Override FSP-M ChannelToCkdQckMapping to map memory channels
+	 * to Clock Driver (CKD) and Query Clock (QCK) signals.
+	 */
+
+	const uint8_t channel_to_ckd_qck[] = { 1, 0, 0, 0,
+		0, 0, 0, 0 };
+	memcpy(m_cfg->ChannelToCkdQckMapping, channel_to_ckd_qck
+		, sizeof(channel_to_ckd_qck));
+
+	/*
+	 * Override FSP-M PhyClockToCkdDimm to map PHY clocks
+	 * to Clock Driver DIMM connections.
+	 */
+	const uint8_t phy_clock_to_ckd_dimm[] = { 4, 0, 4, 0,
+		0, 0, 0, 0 };
+	memcpy(m_cfg->PhyClockToCkdDimm, phy_clock_to_ckd_dimm,
+		sizeof(phy_clock_to_ckd_dimm));
+}

From eb528621321c38337ed214c0cb487530b36d8ee9 Mon Sep 17 00:00:00 2001
From: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Date: Fri, 28 Nov 2025 15:56:58 +0800
Subject: [PATCH 2682/3886] mb/google/brox/var/caboc: Update SSD port and FPMCU
 setting

Start from next stage, Caboc route SSD to PEG60 and change SSD CLK_SRC
CLK_OUT, SSD_CLKREQ(GPP_D8-SRCCLKREQ3#) to port 3.

This CL updates PEG60 CLK_SRC, CLK_OUT to port 3, sets NF1 to GPP_D8-
SRCCLKREQ3. Update fingerprint PCH_FP_BOOT0 to GPP_D5.
Remove PEG62 settings include vGPIO, set NC GPP_H23 (SRCCLKREQ5#),
set NC GPP_F20 (EN_PP3300_SSD) follow schematic 1128A.

BUG=b:464243569, b:45604227, b:441591974
TEST=emerge-brox coreboot

Change-Id: I4376b6532b412215e39be499806e7ebd2eac9841
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90259
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com>
---
 .../google/brox/variants/caboc/fw_config.c    | 12 ++----
 .../google/brox/variants/caboc/gpio.c         | 42 +++++--------------
 .../brox/variants/caboc/overridetree.cb       | 23 ++--------
 3 files changed, 17 insertions(+), 60 deletions(-)

diff --git a/src/mainboard/google/brox/variants/caboc/fw_config.c b/src/mainboard/google/brox/variants/caboc/fw_config.c
index 092c45ba69..6f5d09d2e0 100644
--- a/src/mainboard/google/brox/variants/caboc/fw_config.c
+++ b/src/mainboard/google/brox/variants/caboc/fw_config.c
@@ -7,8 +7,8 @@
 #include <fw_config.h>
 
 static const struct pad_config fp_disable_pads[] = {
-	/* GPP_D8 : PCH_FP_BOOT0 */
-	PAD_NC(GPP_D8, NONE),
+	/* GPP_D5 : PCH_FP_BOOT0 */
+	PAD_NC(GPP_D5, NONE),
 	/* GPP_D9 : FP_RST_ODL */
 	PAD_NC(GPP_D9, NONE),
 	/* GPP_D11 : [] ==> EN_FP_PWR */
@@ -49,12 +49,8 @@ static const struct pad_config lte_disable_pads[] = {
 static const struct pad_config nvme_disable_pads[] = {
 	/* GPP_F9 : SSD_PERST_L */
 	PAD_NC(GPP_F9, NONE),
-	/* GPP_F20 : EN_PP3300_SSD */
-	PAD_NC(GPP_F20, NONE),
-	/* GPP_D5 : SSD_CLKREQ_ODL */
-	PAD_NC(GPP_D5, NONE),
-	/* GPP_H23 : SSD_CLKREQ5_ODL */
-	PAD_NC(GPP_H23, NONE),
+	/* GPP_D8 : SSD_CLKREQ_ODL */
+	PAD_NC(GPP_D8, NONE),
 };
 
 static void fw_config_handle(void *unused)
diff --git a/src/mainboard/google/brox/variants/caboc/gpio.c b/src/mainboard/google/brox/variants/caboc/gpio.c
index 7a683eacc4..db88777526 100644
--- a/src/mainboard/google/brox/variants/caboc/gpio.c
+++ b/src/mainboard/google/brox/variants/caboc/gpio.c
@@ -21,12 +21,12 @@ static const struct pad_config override_gpio_table[] = {
 
 	/* GPP_D4 : [NF1: IMGCLKOUT0 NF2: BK4 NF5: SBK4 NF6: USB_C_GPP_D4] ==> WWAN_GPS_XMIT_OFF */
 	PAD_CFG_GPO(GPP_D4, 0, DEEP),
-	/* GPP_D5 : SRCCLKREQ0_L ==> SSD_CLKREQ_ODL */
-	PAD_CFG_NF(GPP_D5, NONE, DEEP, NF1),
+	/* GPP_D5 : SRCCLKREQ0_L ==> PCH_FP_BOOT0 */
+	PAD_CFG_GPO_LOCK(GPP_D5, 0, LOCK_CONFIG),
 	/* GPP_D7 : SRCCLKREQ2_L ==> PCIE_CLKREQ_LAN */
 	PAD_CFG_NF(GPP_D7, NONE, DEEP, NF1),
-	/* GPP_D8 : [NF1: SRCCLKREQ3# NF6: USB_C_GPP_D8] ==> PCH_FP_BOOT0 */
-	PAD_CFG_GPO_LOCK(GPP_D8, 0, LOCK_CONFIG),
+	/* GPP_D8 : [NF1: SRCCLKREQ3# NF6: USB_C_GPP_D8] ==> SSD_CLKREQ_ODL */
+	PAD_CFG_NF(GPP_D8, NONE, DEEP, NF1),
 	/* GPP_D9 : [NF1: ISH_SPI_CS# NF2: DDP3_CTRLCLK NF4: TBT_LSX2_TXD NF5: BSSB_LS2_RX NF6: USB_C_GPP_D9 NF7: GSPI2_CS0#] ==> FP_RST_ODL */
 	PAD_CFG_GPO_LOCK(GPP_D9, 0, LOCK_CONFIG),
 	/* GPP_D10 : [NF1: ISH_SPI_CLK NF2: DDP3_CTRLDATA NF4: TBT_LSX2_RXD NF5: BSSB_LS2_TX NF6: USB_C_GPP_D10 NF7: GSPI2_CLK] ==> USB_C2_LSX_RX_STRAP(NC) */
@@ -65,13 +65,13 @@ static const struct pad_config override_gpio_table[] = {
 	PAD_CFG_NF_LOCK(GPP_F16, NONE, NF4, LOCK_CONFIG),
 	/* GPP_F19 : SRCCLKREQ6 ==> PCIE_CLKREQ_WWAN */
 	PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1),
-	/* GPP_F20 : [NF1: Reserved NF6: USB_C_GPP_F20] ==> EN_PP3300_SSD */
-	PAD_CFG_GPO(GPP_F20, 1, DEEP),
+	/* GPP_F20 : [NF1: Reserved NF6: USB_C_GPP_F20] ==> NC */
+	PAD_NC(GPP_F20, NONE),
 	/* F21 : [NF1: Reserved NF6: USB_C_GPP_F21] ==> WWAN_OFF#(WWAN_FCPO_L)*/
 	PAD_CFG_GPO(GPP_F21, 1, DEEP),
 
-	/* GPP_H23 : SRCCLKREQ5_L ==>  */
-	PAD_CFG_NF(GPP_H23, NONE, DEEP, NF2),
+	/* GPP_H23 : SRCCLKREQ5_L ==> NC  */
+	PAD_NC(GPP_H23, NONE),
 };
 
 /* Early pad configuration in bootblock */
@@ -102,8 +102,8 @@ static const struct pad_config early_gpio_table[] = {
 	PAD_CFG_GPI_LOCK(GPP_E8, NONE, LOCK_CONFIG),
 	/* GPP_F9 : [NF1: BOOTMPC NF6: USB_C_GPP_F9] ==> SSD_PERST_L */
 	PAD_CFG_GPO(GPP_F9, 0, DEEP),
-	/* GPP_F20 : [NF1: Reserved NF6: USB_C_GPP_F20] ==> EN_PP3300_SSD */
-	PAD_CFG_GPO(GPP_F20, 1, DEEP),
+	/* GPP_F20 : [NF1: Reserved NF6: USB_C_GPP_F20] ==> NC */
+	PAD_NC(GPP_F20, NONE),
 	/* GPP_H8 : [NF1: I2C4_SDA NF2: CNV_MFUART2_RXD NF6: USB_C_GPP_H8] ==> PCH_I2C_GSC_SDA */
 	PAD_CFG_NF(GPP_H8, NONE, DEEP, NF1),
 	/* GPP_H9 : [NF1: I2C4_SCL NF2: CNV_MFUART2_TXD] ==> PCH_I2C_GSC_SCL */
@@ -115,28 +115,6 @@ static const struct pad_config early_gpio_table[] = {
 	/* GPP_S0 : SNDW0_CLL/I2S1_SCLK ==> MEM_CH_SEL */
 	PAD_CFG_GPI(GPP_S0, NONE, DEEP),
 
-	/* CPU PCIe vGPIO for RP2 */
-	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_32, NONE, PLTRST, NF1),
-	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_33, NONE, PLTRST, NF1),
-	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_34, NONE, PLTRST, NF1),
-	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_35, NONE, PLTRST, NF1),
-	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_36, NONE, PLTRST, NF1),
-	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_37, NONE, PLTRST, NF1),
-	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_38, NONE, PLTRST, NF1),
-	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_39, NONE, PLTRST, NF1),
-	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_40, NONE, PLTRST, NF1),
-	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_41, NONE, PLTRST, NF1),
-	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_42, NONE, PLTRST, NF1),
-	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_43, NONE, PLTRST, NF1),
-	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_44, NONE, PLTRST, NF1),
-	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_45, NONE, PLTRST, NF1),
-	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_46, NONE, PLTRST, NF1),
-	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_47, NONE, PLTRST, NF1),
-	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_72, NONE, PLTRST, NF1),
-	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_73, NONE, PLTRST, NF1),
-	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_74, NONE, PLTRST, NF1),
-	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_75, NONE, PLTRST, NF1),
-
 	/* CPU PCIe vGPIO for PEG60 */
 	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_48, NONE, PLTRST, NF1),
 	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_49, NONE, PLTRST, NF1),
diff --git a/src/mainboard/google/brox/variants/caboc/overridetree.cb b/src/mainboard/google/brox/variants/caboc/overridetree.cb
index 6cf5defcdc..9816c123c1 100644
--- a/src/mainboard/google/brox/variants/caboc/overridetree.cb
+++ b/src/mainboard/google/brox/variants/caboc/overridetree.cb
@@ -273,30 +273,13 @@ chip soc/intel/alderlake
 			end
 		end
 		device ref pcie4_0 on
-			# Enable CPU PCIE RP 1 using CLK 5
+			# Enable CPU PCIE RP 1 using CLK 3
 			register "cpu_pcie_rp[CPU_RP(1)]" = "{
-				.clk_req = 5,
-				.clk_src = 5,
-				.flags = PCIE_RP_LTR | PCIE_RP_AER,
-			}"
-			probe STORAGE STORAGE_NVME
-			probe unprovisioned
-		end
-		device ref pcie4_1 on
-			# Enable CPU PCIE RP 3 using CLK 0
-			register "cpu_pcie_rp[CPU_RP(3)]" = "{
-				.clk_req = 0,
-				.clk_src = 0,
+				.clk_req = 3,
+				.clk_src = 3,
 				.flags = PCIE_RP_LTR | PCIE_RP_AER,
 				.pcie_rp_aspm = ASPM_L1,
 			}"
-			chip soc/intel/common/block/pcie/rtd3
-				register "is_storage" = "true"
-				register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_F20)"
-				register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_F9)"
-				register "srcclk_pin" = "0"
-				device generic 0 on end
-			end
 			probe STORAGE STORAGE_NVME
 			probe unprovisioned
 		end

From 60e375fae4c3b4b286bf699be37118fde8cf77e9 Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Sat, 29 Nov 2025 16:58:55 -0600
Subject: [PATCH 2683/3886] mb/google/guybrush: Increase size of SMMSTORE to
 512KB

Increase size of SMMSTORE FMAP region to 512KB to ensure a large
enough area is allocated to UEFI variable storage which allows for
variables (such as the UEFI revocation database) to be updated
via fwupd. Previously, such updates would fail with an error such as:
"efivar: No space left on device".

Change-Id: Iadc2c7d44d8e89f9b4a8f4adad4ac3dd07466984
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90289
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
---
 src/mainboard/google/guybrush/chromeos.fmd | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/mainboard/google/guybrush/chromeos.fmd b/src/mainboard/google/guybrush/chromeos.fmd
index 922ed6f4c8..8eaf5e9aec 100644
--- a/src/mainboard/google/guybrush/chromeos.fmd
+++ b/src/mainboard/google/guybrush/chromeos.fmd
@@ -18,7 +18,7 @@ FLASH 16M {
 		}
 		RW_VPD(PRESERVE) 8K
 		RW_NVRAM(PRESERVE) 20K
-		SMMSTORE(PRESERVE)@0x620000 256K
+		SMMSTORE(PRESERVE)@0x620000 512K
 		RW_LEGACY(CBFS)
 		WP_RO@8M 8M {
 			RO_VPD(PRESERVE) 16K

From dd1e54efc045faa7a8e7bead5d937870d270eeb3 Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Sat, 29 Nov 2025 17:00:39 -0600
Subject: [PATCH 2684/3886] mb/google/zork: Increase size of SMMSTORE to 512KB

Increase size of SMMSTORE FMAP region to 512KB to ensure a large
enough area is allocated to UEFI variable storage which allows for
variables (such as the UEFI revocation database) to be updated
via fwupd. Previously, such updates would fail with an error such as:
"efivar: No space left on device".

Change-Id: I71dcab53b8d570c1a3f37c11ce0b0fb3d86a5d45
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90294
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
---
 src/mainboard/google/zork/chromeos.fmd | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/mainboard/google/zork/chromeos.fmd b/src/mainboard/google/zork/chromeos.fmd
index c874c5657e..d313681bd0 100644
--- a/src/mainboard/google/zork/chromeos.fmd
+++ b/src/mainboard/google/zork/chromeos.fmd
@@ -19,7 +19,7 @@ FLASH 16M {
 		RW_VPD(PRESERVE) 8K
 		RW_NVRAM(PRESERVE) 20K
 		PAD_TO_ALIGN_STORE 16K
-		SMMSTORE(PRESERVE) 256K
+		SMMSTORE(PRESERVE) 512K
 		RW_LEGACY(CBFS)
 		WP_RO@8M 8M {
 			RO_VPD(PRESERVE) 16K

From bb18e0b91dc87944d783482d8212cae5f98ab51d Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Sat, 29 Nov 2025 17:00:21 -0600
Subject: [PATCH 2685/3886] mb/google/skyrim: Increase size of SMMSTORE to
 512KB

Increase size of SMMSTORE FMAP region to 512KB to ensure a large
enough area is allocated to UEFI variable storage which allows for
variables (such as the UEFI revocation database) to be updated
via fwupd. Previously, such updates would fail with an error such as:
"efivar: No space left on device".

Change-Id: I26b8bc194d9f28c2274b87f429821028120a4fcb
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90293
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
---
 src/mainboard/google/skyrim/chromeos.fmd | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/mainboard/google/skyrim/chromeos.fmd b/src/mainboard/google/skyrim/chromeos.fmd
index 12ad05f5ee..81d15b3452 100644
--- a/src/mainboard/google/skyrim/chromeos.fmd
+++ b/src/mainboard/google/skyrim/chromeos.fmd
@@ -20,7 +20,7 @@ FLASH 16M {
 		}
 		RW_VPD(PRESERVE) 8K
 		RW_NVRAM(PRESERVE) 20K
-		SMMSTORE(PRESERVE)@0x630000 256K
+		SMMSTORE(PRESERVE)@0x630000 512K
 		RW_VBIOS_CACHE 64K
 		RECOVERY_MRC_CACHE(PRESERVE) 120K
 		RW_LEGACY(CBFS)

From 67777b76719eeacfa21c69109d2e5aa8f0c7d908 Mon Sep 17 00:00:00 2001
From: Bora Guvendik <bora.guvendik@intel.com>
Date: Thu, 20 Nov 2025 16:14:14 -0800
Subject: [PATCH 2686/3886] soc/intel/common: Add LPCAMM memory topology
 support
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Add MEM_TOPO_LP5_CAMM topology type to support Low Profile Compression
Attached Memory Module (LPCAMM) configurations. LPCAMM is a removable
memory module format that provides similar functionality to DIMMs but
in a different physical form factor. Update the SPD reading logic to
handle both traditional DIMM modules and LPCAMM modules, as both are
removable memory types that require SPD detection and initialization.
This change enables platforms to properly detect and initialize LPCAMM
memory configurations alongside existing DIMM and memory-down support.

BUG=none
TEST=Build test on Intel platforms

Change-Id: I6db2fd76300dd4c96212427d9283b078ca621ed9
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90140
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
---
 src/soc/intel/common/block/include/intelblocks/meminit.h | 1 +
 src/soc/intel/common/block/memory/meminit.c              | 5 +++--
 2 files changed, 4 insertions(+), 2 deletions(-)

diff --git a/src/soc/intel/common/block/include/intelblocks/meminit.h b/src/soc/intel/common/block/include/intelblocks/meminit.h
index 566efa03d9..050e325c1c 100644
--- a/src/soc/intel/common/block/include/intelblocks/meminit.h
+++ b/src/soc/intel/common/block/include/intelblocks/meminit.h
@@ -24,6 +24,7 @@
 enum mem_topology {
 	MEM_TOPO_MEMORY_DOWN = BIT(0), // memory is soldered onto board
 	MEM_TOPO_DIMM_MODULE = BIT(1), // memory is composed of DIMM modules
+	MEM_TOPO_LP5_CAMM = BIT(2),    // memory is composed of LPCAMM modules
 	MEM_TOPO_MIXED = MEM_TOPO_MEMORY_DOWN | MEM_TOPO_DIMM_MODULE,
 };
 
diff --git a/src/soc/intel/common/block/memory/meminit.c b/src/soc/intel/common/block/memory/meminit.c
index fa80017c50..59c1b2a8bc 100644
--- a/src/soc/intel/common/block/memory/meminit.c
+++ b/src/soc/intel/common/block/memory/meminit.c
@@ -117,7 +117,7 @@ static bool read_spd_dimm(FSPM_UPD *memupd, const struct soc_mem_cfg *soc_mem_cf
 	 */
 	uint32_t pop_mask = 0;
 
-	if (!(info->topo & MEM_TOPO_DIMM_MODULE))
+	if (!(info->topo & (MEM_TOPO_DIMM_MODULE | MEM_TOPO_LP5_CAMM)))
 		return false;
 
 	for (ch = 0; ch < num_phys_ch; ch++) {
@@ -212,7 +212,8 @@ void mem_populate_channel_data(FSPM_UPD *memupd, const struct soc_mem_cfg *soc_m
 
 	if (spd_info->topo == MEM_TOPO_MEMORY_DOWN) {
 		data->spd_len = spd_md_len;
-	} else if (spd_info->topo == MEM_TOPO_DIMM_MODULE) {
+	} else if (spd_info->topo == MEM_TOPO_DIMM_MODULE ||
+			spd_info->topo == MEM_TOPO_LP5_CAMM) {
 		data->spd_len = spd_dimm_len;
 	} else {
 		/*

From 58cdf9e6685b0653cb485c0804037d4afc8f7383 Mon Sep 17 00:00:00 2001
From: Bora Guvendik <bora.guvendik@intel.com>
Date: Thu, 20 Nov 2025 12:20:32 -0800
Subject: [PATCH 2687/3886] soc/intel/pantherlake: Add LPCAMM memory support
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Extend memory initialization to support LPCAMM (Low Profile Compression
Attached Memory Module) configurations:
- Increase DIMM_MAX from default to 16 to accommodate LPCAMM SPD
  addressing requirements
- Generalize fill_dimm_module_info() to work with both DDR5 DIMMs and
  LP5X LPCAMM modules by using mb_cfg->type instead of hardcoded
  MEM_TYPE_DDR5
- Add LPCAMM SPD reading support for MEM_TYPE_LP5X when topology is
  MEM_TOPO_LP5_CAMM
- Move DQ/DQS initialization to appropriate locations for each memory
  type. LPCAMM modules use LPDDR5X memory technology but require SPD
  reading via SMBus similar to traditional DIMMs, unlike typical LP5X
  memory-down configurations.

BUG=none
TEST=Build test on Pantherlake platforms with LPCAMM support.

Change-Id: I22743305aa7f93968ec2959de9eaf19b9719260a
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90138
Reviewed-by: Kim, Wonkyu <wonkyu.kim@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
---
 src/soc/intel/pantherlake/Kconfig   |  3 +++
 src/soc/intel/pantherlake/meminit.c | 19 +++++++++++--------
 2 files changed, 14 insertions(+), 8 deletions(-)

diff --git a/src/soc/intel/pantherlake/Kconfig b/src/soc/intel/pantherlake/Kconfig
index 365d8e2736..bf02cde32f 100644
--- a/src/soc/intel/pantherlake/Kconfig
+++ b/src/soc/intel/pantherlake/Kconfig
@@ -389,6 +389,9 @@ config DIMMS_PER_CHANNEL
 	int
 	default 2
 
+config DIMM_MAX
+	default 16
+
 config MRC_CHANNEL_WIDTH
 	int
 	default 16
diff --git a/src/soc/intel/pantherlake/meminit.c b/src/soc/intel/pantherlake/meminit.c
index 01c217be3d..eef4adf5f0 100644
--- a/src/soc/intel/pantherlake/meminit.c
+++ b/src/soc/intel/pantherlake/meminit.c
@@ -167,20 +167,18 @@ static void mem_init_dqs_upds(FSP_M_CONFIG *mem_cfg, const struct mem_channel_da
 	mem_init_dq_dqs_upds(dqs_upds, mb_cfg->dqs_map, upd_size, data, auto_detect);
 }
 
-#define DDR5_CH_DIMM_OFFSET(ch, dimm)        ((ch) * CONFIG_DIMMS_PER_CHANNEL + (dimm))
+#define CH_DIMM_OFFSET(ch, dimm)        ((ch) * CONFIG_DIMMS_PER_CHANNEL + (dimm))
 
-static void ddr5_fill_dimm_module_info(FSP_M_CONFIG *mem_cfg, const struct mb_cfg *mb_cfg,
+static void fill_dimm_module_info(FSP_M_CONFIG *mem_cfg, const struct mb_cfg *mb_cfg,
 				       const struct mem_spd *spd_info)
 {
-	for (size_t ch = 0; ch < soc_mem_cfg[MEM_TYPE_DDR5].num_phys_channels; ch++) {
+	for (size_t ch = 0; ch < soc_mem_cfg[mb_cfg->type].num_phys_channels; ch++) {
 		for (size_t dimm = 0; dimm < CONFIG_DIMMS_PER_CHANNEL; dimm++) {
-			size_t mrc_ch = soc_mem_cfg[MEM_TYPE_DDR5].phys_to_mrc_map[ch];
-			mem_cfg->SpdAddressTable[DDR5_CH_DIMM_OFFSET(mrc_ch, dimm)] =
+			size_t mrc_ch = soc_mem_cfg[mb_cfg->type].phys_to_mrc_map[ch];
+			mem_cfg->SpdAddressTable[CH_DIMM_OFFSET(mrc_ch, dimm)] =
 				spd_info->smbus[ch].addr_dimm[dimm] << 1;
 		}
 	}
-	mem_init_dq_upds(mem_cfg, NULL, mb_cfg, true);
-	mem_init_dqs_upds(mem_cfg, NULL, mb_cfg, true);
 }
 
 void memcfg_init(FSPM_UPD *memupd, const struct mb_cfg *mb_cfg,
@@ -204,12 +202,17 @@ void memcfg_init(FSPM_UPD *memupd, const struct mb_cfg *mb_cfg,
 		 * updated to support DDR5 EEPROM reading.
 		 */
 		if (spd_info->topo == MEM_TOPO_DIMM_MODULE) {
-			ddr5_fill_dimm_module_info(mem_cfg, mb_cfg, spd_info);
+			fill_dimm_module_info(mem_cfg, mb_cfg, spd_info);
+			mem_init_dq_upds(mem_cfg, NULL, mb_cfg, true);
+			mem_init_dqs_upds(mem_cfg, NULL, mb_cfg, true);
 			return;
 		}
 		break;
 	case MEM_TYPE_LP5X:
 		meminit_lp5x(mem_cfg, &mb_cfg->lp5x_config);
+		/* For LPCAMM, read SPD using SMBus driver */
+		if (spd_info->topo == MEM_TOPO_LP5_CAMM)
+			fill_dimm_module_info(mem_cfg, mb_cfg, spd_info);
 		break;
 	default:
 		die("Unsupported memory type(%d)\n", mb_cfg->type);

From b31e62ae5cc8bdc4b10103e7d39cd30d07bc0185 Mon Sep 17 00:00:00 2001
From: Bora Guvendik <bora.guvendik@intel.com>
Date: Thu, 20 Nov 2025 12:21:13 -0800
Subject: [PATCH 2688/3886] mb/intel/ptlrvp: Add LPCAMM T3 RVP board support
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Add support for Pantherlake LPCAMM T3 Reference Validation Platform:
- Define PTLP_LPCAMM_T3_RVP board ID (0x02)
- Add memory configuration for LPCAMM including DQ/DQS mapping
- Configure SPD information for LPCAMM modules using SMBus address 0x50
  across all channels with MEM_TOPO_LP5_CAMM topology to enable SPD
  detection

BUG=none
TEST=Boot LPCAMM T3 RVP and verify memory detection.

Change-Id: I17325241c105a5af5a97931be5c75a025b2bd7c8
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90139
Reviewed-by: Kim, Wonkyu <wonkyu.kim@intel.com>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 .../baseboard/include/baseboard/variants.h    |  1 +
 .../intel/ptlrvp/variants/ptlrvp/gpio.c       |  1 +
 .../intel/ptlrvp/variants/ptlrvp/memory.c     | 79 +++++++++++++++++++
 3 files changed, 81 insertions(+)

diff --git a/src/mainboard/intel/ptlrvp/variants/baseboard/include/baseboard/variants.h b/src/mainboard/intel/ptlrvp/variants/baseboard/include/baseboard/variants.h
index 05ddf5bb5f..9378a33e84 100644
--- a/src/mainboard/intel/ptlrvp/variants/baseboard/include/baseboard/variants.h
+++ b/src/mainboard/intel/ptlrvp/variants/baseboard/include/baseboard/variants.h
@@ -12,6 +12,7 @@
 
 enum ptl_boardid {
 	PTLP_LP5_T3_RVP = 0x01,
+	PTLP_LPCAMM_T3_RVP = 0x02,
 	PTLP_LP5_T4_RVP = 0x03,
 	PTLP_DDR5_RVP = 0x04,
 	GCS_32GB = 0x11,
diff --git a/src/mainboard/intel/ptlrvp/variants/ptlrvp/gpio.c b/src/mainboard/intel/ptlrvp/variants/ptlrvp/gpio.c
index c2913c48d3..9d32ff3431 100644
--- a/src/mainboard/intel/ptlrvp/variants/ptlrvp/gpio.c
+++ b/src/mainboard/intel/ptlrvp/variants/ptlrvp/gpio.c
@@ -455,6 +455,7 @@ const struct pad_config *variant_board_gpio_diff_table(size_t *num)
 
 	switch (board_id) {
 	case PTLP_LP5_T3_RVP:
+	case PTLP_LPCAMM_T3_RVP:
 		return NULL;
 	case PTLP_LP5_T4_RVP:
 		*num = ARRAY_SIZE(t4_gpio_diff_table);
diff --git a/src/mainboard/intel/ptlrvp/variants/ptlrvp/memory.c b/src/mainboard/intel/ptlrvp/variants/ptlrvp/memory.c
index 4882edb324..de17b261a9 100644
--- a/src/mainboard/intel/ptlrvp/variants/ptlrvp/memory.c
+++ b/src/mainboard/intel/ptlrvp/variants/ptlrvp/memory.c
@@ -121,6 +121,64 @@ static const struct mb_cfg lp5_t3_mem_config = {
 	},
 };
 
+static const struct mb_cfg camm_t3_mem_config = {
+	.type = MEM_TYPE_LP5X,
+
+	.lpx_dq_map = {
+		.ddr0 = {
+			.dq0 = {  0,  3,  1,  2,  6,  7,  4,  5, },
+			.dq1 = {  13,  12,  15,  14,  8,  10,  11,  9 },
+		},
+		.ddr1 = {
+			.dq0 = {  8,  10,  11,  9,  13,  15,  14,  12, },
+			.dq1 = {  5,  7,  6,  4,  3,  2,  1,  0 },
+		},
+		.ddr2 = {
+			.dq0 = {  1,  3,  0,  2,  6,  7,  5,  4 },
+			.dq1 = {  12,  13,  15,  14,  8,  11,  9,  10, },
+		},
+		.ddr3 = {
+			.dq0 = {  14,  15,  12,  13,  10,  8,  11,  9, },
+			.dq1 = {  4,  6,  7,  5,  1,  3,  0,  2 },
+		},
+		.ddr4 = {
+			.dq0 = {  3,  0,  2,  1,  6,  7,  4,  5 },
+			.dq1 = {  13,  12,  15,  14,  8,  10,  11,  9, },
+		},
+		.ddr5 = {
+			.dq0 = {  10,  8,  11,  9,  13,  15,  12,  14, },
+			.dq1 = {  2,  1,  3,  0,  7,  6,  5,  4 },
+		},
+		.ddr6 = {
+			.dq0 = {  3,  1,  2,  0,  5,  7,  4,  6, },
+			.dq1 = {  12,  14,  15,  13,  9,  10,  11,  8 },
+		},
+		.ddr7 = {
+			.dq0 = {  8,  9,  10,  11,  12,  13,  14,  15, },
+			.dq1 = {  5,  6,  7,  4,  2,  1,  3,  0 },
+		},
+	},
+
+	.lpx_dqs_map = {
+		.ddr0 = { .dqs0 = 0, .dqs1 = 1 },
+		.ddr1 = { .dqs0 = 1, .dqs1 = 0 },
+		.ddr2 = { .dqs0 = 0, .dqs1 = 1 },
+		.ddr3 = { .dqs0 = 1, .dqs1 = 0 },
+		.ddr4 = { .dqs0 = 0, .dqs1 = 1 },
+		.ddr5 = { .dqs0 = 1, .dqs1 = 0 },
+		.ddr6 = { .dqs0 = 0, .dqs1 = 1 },
+		.ddr7 = { .dqs0 = 1, .dqs1 = 0 }
+	},
+
+	.ect = true, /* Early Command Training */
+
+	.user_bd = BOARD_TYPE_ULT_ULX,
+
+	.lp5x_config = {
+		.ccc_config = 0x55,
+	},
+};
+
 static const struct mb_cfg lp5_t4_mem_config = {
 	.type = MEM_TYPE_LP5X,
 
@@ -200,6 +258,8 @@ const struct mb_cfg *variant_memory_params(void)
 	int board_id = get_rvp_board_id();
 
 	switch (board_id) {
+	case PTLP_LPCAMM_T3_RVP:
+		return &camm_t3_mem_config;
 	case PTLP_LP5_T3_RVP:
 		return &lp5_t3_mem_config;
 	case PTLP_LP5_T4_RVP:
@@ -220,6 +280,25 @@ void variant_get_spd_info(struct mem_spd *spd_info)
 	int board_id = get_rvp_board_id();
 
 	switch (board_id) {
+	case PTLP_LPCAMM_T3_RVP:
+		spd_info->topo = MEM_TOPO_LP5_CAMM;
+		spd_info->smbus[0].addr_dimm[0] = 0x50;
+		spd_info->smbus[0].addr_dimm[1] = 0x0;
+		spd_info->smbus[1].addr_dimm[0] = 0x50;
+		spd_info->smbus[1].addr_dimm[1] = 0x0;
+		spd_info->smbus[2].addr_dimm[0] = 0x50;
+		spd_info->smbus[2].addr_dimm[1] = 0x0;
+		spd_info->smbus[3].addr_dimm[0] = 0x50;
+		spd_info->smbus[3].addr_dimm[1] = 0x0;
+		spd_info->smbus[4].addr_dimm[0] = 0x50;
+		spd_info->smbus[4].addr_dimm[1] = 0x0;
+		spd_info->smbus[5].addr_dimm[0] = 0x50;
+		spd_info->smbus[5].addr_dimm[1] = 0x0;
+		spd_info->smbus[6].addr_dimm[0] = 0x50;
+		spd_info->smbus[6].addr_dimm[1] = 0x0;
+		spd_info->smbus[7].addr_dimm[0] = 0x50;
+		spd_info->smbus[7].addr_dimm[1] = 0x0;
+		break;
 	case PTLP_LP5_T3_RVP:
 	case PTLP_LP5_T4_RVP:
 	case GCS_32GB:

From 2ce1068542fbb1a6772898d3d4efbe3d4a42e606 Mon Sep 17 00:00:00 2001
From: Varun Upadhyay <varun.upadhyay@intel.com>
Date: Mon, 1 Dec 2025 14:50:34 +0530
Subject: [PATCH 2689/3886] mb/google/ocelot/var/ojal: Decrease display count
 from 5 to 4

This change updates the actual number of displays supported by ojal
variant according to schematics revision 0.9.
RDC kit no:840138

Scope (\_SB.PCI0.GFX0)
  {
        Method (_DOD, 0, NotSerialized)
        {
            Return (Package (0x04)
            {
                0x80010400, // Display device 0 (LCD0 - internal eDP)
                0x80010000, // Display device 1 (DD01 - HDMI)
                0x80010000, // Display device 2 (DD02 - USB-C)
                0x80010000  // Display device 2 (DD02 - USB-C)
            })
        }

BUG=b:437459757
TEST=Build ojal and check all displays functionality booting to OS,
Also verify the available displays by dumping the SSDT table.

Change-Id: Ida3d6a03028467345c3e033e9581fe5f8fbe22c4
Signed-off-by: Varun Upadhyay <varun.upadhyay@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90301
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: P, Usha <usha.p@intel.com>
Reviewed-by: Pranava Y N <pranavayn@google.com>
---
 src/mainboard/google/ocelot/variants/ojal/overridetree.cb | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/mainboard/google/ocelot/variants/ojal/overridetree.cb b/src/mainboard/google/ocelot/variants/ojal/overridetree.cb
index c2977f6ac7..a8686cd986 100644
--- a/src/mainboard/google/ocelot/variants/ojal/overridetree.cb
+++ b/src/mainboard/google/ocelot/variants/ojal/overridetree.cb
@@ -108,7 +108,7 @@ chip soc/intel/pantherlake
 		device ref igpu on
 			probe DISPLAY DISPLAY_PRESENT
 			chip drivers/gfx/generic
-				register "device_count" = "5"
+				register "device_count" = "4"
 				# DDIA for eDP
 				register "device[0].name" = ""LCD0""
 				register "device[0].type" = "panel"

From a65b8744723d6521c384f2837ccfdd32c1bfd0b6 Mon Sep 17 00:00:00 2001
From: Walter Sonius <walterav1984@gmail.com>
Date: Fri, 8 Aug 2025 18:24:26 +0200
Subject: [PATCH 2690/3886] mb/dell: Convert OptiPlex 3050 into variant
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

To minimize code duplication when adding the new "optiplex_5040" port
CB:88735, the "optiplex_3050" should be turned into a variant first.

Naming of the template inspired by "ifdtool --platform quirk" and recent
"sklkbl_thinkpads" commit. However it's naming is not limmited to its
CPU support since some Coffee Lake (Refresh) CPUs are already tested!

Currently chose a more common name "desktops" although yet only Dell
OptiPlex units are supported Inspiron, Vostro or even Precision desktops
running the same chipset(s) and code should be foreseen.

Open to any other naming / convention suggestions?

Patch stages:
patch1: add variant template with duplicated code some specialized files
        but full devicetree.cb as overridetree.cb wont build as variant!
patch2: edit Kconfig(.name) and Makefile.mk to include both variants
        trim each overridetree.cb specific & derive common devicetree.cb
        builds both variants only tested and verified "optiplex_5040"
patch3: remove "optiplex_5040" variant so this only turns into a variant
        containing the converted "optiplex_3050"
patch12 customized gpio between 3050 and 5040 use gpio.c vs gpio.h

Further patches mostly rebasing.

TEST=Checksum BUILD_TIMELESS=1 matches if original build adds 1 ramstage
     linked file to variant folder! See comments howto verify checksum.

Change-Id: I16e3b92104f515b334afaacfed740a3b71f5b048
Signed-off-by: Walter Sonius <walterav1984@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88726
Reviewed-by: Máté Kukri <km@mkukri.xyz>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/dell/optiplex_3050/Makefile.mk  |  12 ---
 .../Kconfig                                   |  38 +++++----
 .../Kconfig.name                              |   0
 .../dell/sklkbl_desktops/Makefile.mk          |  15 ++++
 .../acpi/ec.asl                               |   0
 .../dell/sklkbl_desktops/board_info.txt       |   5 ++
 .../bootblock.c                               |   4 +-
 .../cmos.default                              |   0
 .../cmos.layout                               |   0
 .../dell/sklkbl_desktops/devicetree.cb        |  75 ++++++++++++++++++
 .../dsdt.asl                                  |   0
 .../sklkbl_desktops/include/variant/gpio.h    |   9 +++
 .../ramstage.c                                |   4 +-
 .../sch5555_ec.c                              |   0
 .../sch5555_ec.h                              |   0
 .../variants}/optiplex_3050/board_info.txt    |   0
 .../variants}/optiplex_3050/data.vbt          | Bin
 .../variants/optiplex_3050/early_gpio.c}      |  13 ++-
 .../variants}/optiplex_3050/gma-mainboard.ads |   0
 .../variants/optiplex_3050/gpio.c}            |  14 +++-
 .../variants}/optiplex_3050/hda_verb.c        |   0
 .../optiplex_3050/include}/acpi/superio.asl   |   0
 .../variants/optiplex_3050/overridetree.cb}   |  67 +++-------------
 .../variants}/optiplex_3050/romstage.c        |   0
 24 files changed, 165 insertions(+), 91 deletions(-)
 delete mode 100644 src/mainboard/dell/optiplex_3050/Makefile.mk
 rename src/mainboard/dell/{optiplex_3050 => sklkbl_desktops}/Kconfig (54%)
 rename src/mainboard/dell/{optiplex_3050 => sklkbl_desktops}/Kconfig.name (100%)
 create mode 100644 src/mainboard/dell/sklkbl_desktops/Makefile.mk
 rename src/mainboard/dell/{optiplex_3050 => sklkbl_desktops}/acpi/ec.asl (100%)
 create mode 100644 src/mainboard/dell/sklkbl_desktops/board_info.txt
 rename src/mainboard/dell/{optiplex_3050 => sklkbl_desktops}/bootblock.c (97%)
 rename src/mainboard/dell/{optiplex_3050 => sklkbl_desktops}/cmos.default (100%)
 rename src/mainboard/dell/{optiplex_3050 => sklkbl_desktops}/cmos.layout (100%)
 create mode 100644 src/mainboard/dell/sklkbl_desktops/devicetree.cb
 rename src/mainboard/dell/{optiplex_3050 => sklkbl_desktops}/dsdt.asl (100%)
 create mode 100644 src/mainboard/dell/sklkbl_desktops/include/variant/gpio.h
 rename src/mainboard/dell/{optiplex_3050 => sklkbl_desktops}/ramstage.c (99%)
 rename src/mainboard/dell/{optiplex_3050 => sklkbl_desktops}/sch5555_ec.c (100%)
 rename src/mainboard/dell/{optiplex_3050 => sklkbl_desktops}/sch5555_ec.h (100%)
 rename src/mainboard/dell/{ => sklkbl_desktops/variants}/optiplex_3050/board_info.txt (100%)
 rename src/mainboard/dell/{ => sklkbl_desktops/variants}/optiplex_3050/data.vbt (100%)
 rename src/mainboard/dell/{optiplex_3050/include/early_gpio.h => sklkbl_desktops/variants/optiplex_3050/early_gpio.c} (56%)
 rename src/mainboard/dell/{ => sklkbl_desktops/variants}/optiplex_3050/gma-mainboard.ads (100%)
 rename src/mainboard/dell/{optiplex_3050/include/gpio.h => sklkbl_desktops/variants/optiplex_3050/gpio.c} (97%)
 rename src/mainboard/dell/{ => sklkbl_desktops/variants}/optiplex_3050/hda_verb.c (100%)
 rename src/mainboard/dell/{optiplex_3050 => sklkbl_desktops/variants/optiplex_3050/include}/acpi/superio.asl (100%)
 rename src/mainboard/dell/{optiplex_3050/devicetree.cb => sklkbl_desktops/variants/optiplex_3050/overridetree.cb} (53%)
 rename src/mainboard/dell/{ => sklkbl_desktops/variants}/optiplex_3050/romstage.c (100%)

diff --git a/src/mainboard/dell/optiplex_3050/Makefile.mk b/src/mainboard/dell/optiplex_3050/Makefile.mk
deleted file mode 100644
index 0bd72fe691..0000000000
--- a/src/mainboard/dell/optiplex_3050/Makefile.mk
+++ /dev/null
@@ -1,12 +0,0 @@
-## SPDX-License-Identifier: GPL-2.0-only
-
-bootblock-y += bootblock.c
-bootblock-y += sch5555_ec.c
-
-romstage-y += romstage.c
-
-ramstage-y += ramstage.c
-ramstage-y += sch5555_ec.c
-ramstage-y += hda_verb.c
-
-ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads
diff --git a/src/mainboard/dell/optiplex_3050/Kconfig b/src/mainboard/dell/sklkbl_desktops/Kconfig
similarity index 54%
rename from src/mainboard/dell/optiplex_3050/Kconfig
rename to src/mainboard/dell/sklkbl_desktops/Kconfig
index 17cd2bee67..6d57c1ed10 100644
--- a/src/mainboard/dell/optiplex_3050/Kconfig
+++ b/src/mainboard/dell/sklkbl_desktops/Kconfig
@@ -1,9 +1,7 @@
 ## SPDX-License-Identifier: GPL-2.0-only
 
-if BOARD_DELL_OPTIPLEX_3050
-
-config BOARD_SPECIFIC_OPTIONS
-	def_bool y
+config BOARD_DELL_SKLKBL_DESKTOPS_COMMON
+	bool
 	select AZALIA_USE_LEGACY_VERB_TABLE
 	select BOARD_ROMSIZE_KB_16384
 	select HAVE_ACPI_RESUME
@@ -20,19 +18,31 @@ config BOARD_SPECIFIC_OPTIONS
 	select SOC_INTEL_KABYLAKE
 	select SUPERIO_SMSC_SCH555x
 
+config BOARD_DELL_OPTIPLEX_3050
+	bool
+	select BOARD_DELL_SKLKBL_DESKTOPS_COMMON
+
+if BOARD_DELL_SKLKBL_DESKTOPS_COMMON
+
+config MAINBOARD_DIR
+	default "dell/sklkbl_desktops"
+
+config MAINBOARD_PART_NUMBER
+	default "OptiPlex 3050 Micro" if BOARD_DELL_OPTIPLEX_3050
+
+config VARIANT_DIR
+	default "optiplex_3050" if BOARD_DELL_OPTIPLEX_3050
+
+config OVERRIDE_DEVICETREE
+	default "variants/\$(CONFIG_VARIANT_DIR)/overridetree.cb"
+
+config INTEL_GMA_VBT_FILE
+	default "src/mainboard/\$(MAINBOARDDIR)/variants/\$(CONFIG_VARIANT_DIR)/data.vbt"
+
 config CBFS_SIZE
 	default 0x900000
 
-config MAINBOARD_DIR
-	default "dell/optiplex_3050"
-
-config MAINBOARD_PART_NUMBER
-	default "OptiPlex 3050 Micro"
-
-config INTEL_GMA_VBT_FILE
-	default "src/mainboard/\$(MAINBOARDDIR)/data.vbt"
-
 config DIMM_SPD_SIZE
-	default 512	# DDR4
+	default 512 if BOARD_DELL_OPTIPLEX_3050	# DDR4
 
 endif
diff --git a/src/mainboard/dell/optiplex_3050/Kconfig.name b/src/mainboard/dell/sklkbl_desktops/Kconfig.name
similarity index 100%
rename from src/mainboard/dell/optiplex_3050/Kconfig.name
rename to src/mainboard/dell/sklkbl_desktops/Kconfig.name
diff --git a/src/mainboard/dell/sklkbl_desktops/Makefile.mk b/src/mainboard/dell/sklkbl_desktops/Makefile.mk
new file mode 100644
index 0000000000..305aa2a93f
--- /dev/null
+++ b/src/mainboard/dell/sklkbl_desktops/Makefile.mk
@@ -0,0 +1,15 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
+bootblock-y += bootblock.c
+bootblock-y += variants/$(VARIANT_DIR)/early_gpio.c
+bootblock-y += sch5555_ec.c
+
+romstage-y += variants/$(VARIANT_DIR)/romstage.c
+
+ramstage-y += ramstage.c
+ramstage-y += variants/$(VARIANT_DIR)/gpio.c
+ramstage-y += sch5555_ec.c
+ramstage-y += variants/$(VARIANT_DIR)/hda_verb.c
+ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += variants/$(VARIANT_DIR)/gma-mainboard.ads
+
+CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/include
diff --git a/src/mainboard/dell/optiplex_3050/acpi/ec.asl b/src/mainboard/dell/sklkbl_desktops/acpi/ec.asl
similarity index 100%
rename from src/mainboard/dell/optiplex_3050/acpi/ec.asl
rename to src/mainboard/dell/sklkbl_desktops/acpi/ec.asl
diff --git a/src/mainboard/dell/sklkbl_desktops/board_info.txt b/src/mainboard/dell/sklkbl_desktops/board_info.txt
new file mode 100644
index 0000000000..7ed9d984cd
--- /dev/null
+++ b/src/mainboard/dell/sklkbl_desktops/board_info.txt
@@ -0,0 +1,5 @@
+Category: desktop
+ROM package: SOIC-8
+ROM protocol: SPI
+ROM socketed: n
+Flashrom support: y
diff --git a/src/mainboard/dell/optiplex_3050/bootblock.c b/src/mainboard/dell/sklkbl_desktops/bootblock.c
similarity index 97%
rename from src/mainboard/dell/optiplex_3050/bootblock.c
rename to src/mainboard/dell/sklkbl_desktops/bootblock.c
index 10689c42a1..fc583ea5a1 100644
--- a/src/mainboard/dell/optiplex_3050/bootblock.c
+++ b/src/mainboard/dell/sklkbl_desktops/bootblock.c
@@ -4,7 +4,7 @@
 #include <device/pnp_ops.h>
 #include <soc/gpio.h>
 #include <superio/smsc/sch555x/sch555x.h>
-#include "include/early_gpio.h"
+#include "../../../include/variant/gpio.h"
 #include "sch5555_ec.h"
 
 struct ec_init_entry {
@@ -88,7 +88,7 @@ static void bootblock_ec_init(void)
 
 void bootblock_mainboard_early_init(void)
 {
-	gpio_configure_pads(early_gpio_table, ARRAY_SIZE(early_gpio_table));
+	variant_configure_early_gpios();
 
 	// Super I/O early init will map Runtime and EMI registers
 	sch555x_early_init(GLOBAL_DEV);
diff --git a/src/mainboard/dell/optiplex_3050/cmos.default b/src/mainboard/dell/sklkbl_desktops/cmos.default
similarity index 100%
rename from src/mainboard/dell/optiplex_3050/cmos.default
rename to src/mainboard/dell/sklkbl_desktops/cmos.default
diff --git a/src/mainboard/dell/optiplex_3050/cmos.layout b/src/mainboard/dell/sklkbl_desktops/cmos.layout
similarity index 100%
rename from src/mainboard/dell/optiplex_3050/cmos.layout
rename to src/mainboard/dell/sklkbl_desktops/cmos.layout
diff --git a/src/mainboard/dell/sklkbl_desktops/devicetree.cb b/src/mainboard/dell/sklkbl_desktops/devicetree.cb
new file mode 100644
index 0000000000..f66091f679
--- /dev/null
+++ b/src/mainboard/dell/sklkbl_desktops/devicetree.cb
@@ -0,0 +1,75 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
+chip soc/intel/skylake
+	register "deep_sx_config" = "DSX_EN_WAKE_PIN | DSX_EN_LAN_WAKE_PIN"
+
+	# Enable Enhanced Intel SpeedStep
+	register "eist_enable" = "1"
+
+	device domain 0 on
+
+		device ref peg0 off end
+
+		device ref igpu on
+			register "PrimaryDisplay" = "Display_iGFX"
+		end
+
+		device ref south_xhci on end
+
+		# ME interface is 'off' to avoid HECI reset delay due to HAP
+		device ref heci1 off end
+
+		device ref sata on end
+
+		device ref pcie_rp5 off end
+
+		device ref pcie_rp8 off end
+
+		device ref pcie_rp9 off end
+
+		device ref pcie_rp17 off end
+
+		device ref pcie_rp21 off end
+
+		# UART0 is exposed on test points on the bottom of the board
+		device ref uart0 on
+			register "SerialIoDevMode[PchSerialIoIndexUart0]" = "PchSerialIoPci"
+		end
+
+		device ref lpc_espi on
+			register "serirq_mode" = "SERIRQ_CONTINUOUS"
+
+			# I/O decode for EMI/Runtime registers
+			register "gen1_dec" = "0x007c0a01"
+
+			# SCH5553
+			chip superio/smsc/sch555x
+				device pnp 2e.0 on		# EMI
+					io 0x60 = 0xa00
+				end
+				device pnp 2e.1 off end		# 8042
+				device pnp 2e.7 on		# UART1
+					io 0x60 = 0x3f8
+					irq 0x0f = 2
+					irq 0x70 = 4
+				end
+				device pnp 2e.8 off end		# UART2
+				device pnp 2e.c on		# LPC interface
+					io 0x60 = 0x2e
+				end
+				device pnp 2e.a on		# Runtime registers
+					io 0x60 = 0xa40
+				end
+				device pnp 2e.b  off end	# Floppy Controller
+				device pnp 2e.11 off end	# Parallel Port
+			end
+
+		end
+
+		device ref hda on end
+
+		device ref smbus on end
+
+		device ref gbe off end
+	end
+end
diff --git a/src/mainboard/dell/optiplex_3050/dsdt.asl b/src/mainboard/dell/sklkbl_desktops/dsdt.asl
similarity index 100%
rename from src/mainboard/dell/optiplex_3050/dsdt.asl
rename to src/mainboard/dell/sklkbl_desktops/dsdt.asl
diff --git a/src/mainboard/dell/sklkbl_desktops/include/variant/gpio.h b/src/mainboard/dell/sklkbl_desktops/include/variant/gpio.h
new file mode 100644
index 0000000000..95d576294f
--- /dev/null
+++ b/src/mainboard/dell/sklkbl_desktops/include/variant/gpio.h
@@ -0,0 +1,9 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef VARIANT_GPIO_H
+#define VARIANT_GPIO_H
+
+void variant_configure_early_gpios(void);
+void variant_configure_gpios(void);
+
+#endif
diff --git a/src/mainboard/dell/optiplex_3050/ramstage.c b/src/mainboard/dell/sklkbl_desktops/ramstage.c
similarity index 99%
rename from src/mainboard/dell/optiplex_3050/ramstage.c
rename to src/mainboard/dell/sklkbl_desktops/ramstage.c
index 94778f60c9..b90e71394c 100644
--- a/src/mainboard/dell/optiplex_3050/ramstage.c
+++ b/src/mainboard/dell/sklkbl_desktops/ramstage.c
@@ -5,12 +5,12 @@
 #include <cpu/x86/msr.h>
 #include <soc/gpio.h>
 #include <soc/ramstage.h>
-#include "include/gpio.h"
+#include "../../../include/variant/gpio.h"
 #include "sch5555_ec.h"
 
 void mainboard_silicon_init_params(FSP_SIL_UPD *params)
 {
-	gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table));
+	variant_configure_gpios();
 }
 
 #define FORM_FACTOR_MICRO	0
diff --git a/src/mainboard/dell/optiplex_3050/sch5555_ec.c b/src/mainboard/dell/sklkbl_desktops/sch5555_ec.c
similarity index 100%
rename from src/mainboard/dell/optiplex_3050/sch5555_ec.c
rename to src/mainboard/dell/sklkbl_desktops/sch5555_ec.c
diff --git a/src/mainboard/dell/optiplex_3050/sch5555_ec.h b/src/mainboard/dell/sklkbl_desktops/sch5555_ec.h
similarity index 100%
rename from src/mainboard/dell/optiplex_3050/sch5555_ec.h
rename to src/mainboard/dell/sklkbl_desktops/sch5555_ec.h
diff --git a/src/mainboard/dell/optiplex_3050/board_info.txt b/src/mainboard/dell/sklkbl_desktops/variants/optiplex_3050/board_info.txt
similarity index 100%
rename from src/mainboard/dell/optiplex_3050/board_info.txt
rename to src/mainboard/dell/sklkbl_desktops/variants/optiplex_3050/board_info.txt
diff --git a/src/mainboard/dell/optiplex_3050/data.vbt b/src/mainboard/dell/sklkbl_desktops/variants/optiplex_3050/data.vbt
similarity index 100%
rename from src/mainboard/dell/optiplex_3050/data.vbt
rename to src/mainboard/dell/sklkbl_desktops/variants/optiplex_3050/data.vbt
diff --git a/src/mainboard/dell/optiplex_3050/include/early_gpio.h b/src/mainboard/dell/sklkbl_desktops/variants/optiplex_3050/early_gpio.c
similarity index 56%
rename from src/mainboard/dell/optiplex_3050/include/early_gpio.h
rename to src/mainboard/dell/sklkbl_desktops/variants/optiplex_3050/early_gpio.c
index 17a16371e3..9bc7013f18 100644
--- a/src/mainboard/dell/optiplex_3050/include/early_gpio.h
+++ b/src/mainboard/dell/sklkbl_desktops/variants/optiplex_3050/early_gpio.c
@@ -1,11 +1,22 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
+/*
 #ifndef __OPTIPLEX_3050_EARLY_GPIO_H__
 #define __OPTIPLEX_3050_EARLY_GPIO_H__
+*/
+
+#include <soc/gpe.h>
+#include <soc/gpio.h>
+#include "../../../include/variant/gpio.h"
 
 static const struct pad_config early_gpio_table[] = {
 	PAD_CFG_NF(GPP_C8, NONE, DEEP, NF1),	/* UART0_RXD */
 	PAD_CFG_NF(GPP_C9, NONE, DEEP, NF1),	/* UART0_TXD */
 };
 
-#endif
+// #endif
+
+void variant_configure_early_gpios(void)
+{
+	gpio_configure_pads(early_gpio_table, ARRAY_SIZE(early_gpio_table));
+}
diff --git a/src/mainboard/dell/optiplex_3050/gma-mainboard.ads b/src/mainboard/dell/sklkbl_desktops/variants/optiplex_3050/gma-mainboard.ads
similarity index 100%
rename from src/mainboard/dell/optiplex_3050/gma-mainboard.ads
rename to src/mainboard/dell/sklkbl_desktops/variants/optiplex_3050/gma-mainboard.ads
diff --git a/src/mainboard/dell/optiplex_3050/include/gpio.h b/src/mainboard/dell/sklkbl_desktops/variants/optiplex_3050/gpio.c
similarity index 97%
rename from src/mainboard/dell/optiplex_3050/include/gpio.h
rename to src/mainboard/dell/sklkbl_desktops/variants/optiplex_3050/gpio.c
index 83293c32a9..be066941aa 100644
--- a/src/mainboard/dell/optiplex_3050/include/gpio.h
+++ b/src/mainboard/dell/sklkbl_desktops/variants/optiplex_3050/gpio.c
@@ -1,7 +1,10 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
-#ifndef __OPTIPLEX_3050_GPIO_H__
-#define __OPTIPLEX_3050_GPIO_H__
+#include <soc/gpe.h>
+#include <soc/gpio.h>
+#include "../../../include/variant/gpio.h"
+
+/* #ifndef __OPTIPLEX_3050_GPIO_H__ #define __OPTIPLEX_3050_GPIO_H__ */
 
 static const struct pad_config gpio_table[] = {
 
@@ -238,4 +241,9 @@ static const struct pad_config gpio_table[] = {
 	PAD_CFG_NF(GPP_I10, DN_20K, PLTRST, NF1),			/* DDPD_CTRLDATA */
 };
 
-#endif
+void variant_configure_gpios(void)
+{
+	gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table));
+}
+
+// #endif
diff --git a/src/mainboard/dell/optiplex_3050/hda_verb.c b/src/mainboard/dell/sklkbl_desktops/variants/optiplex_3050/hda_verb.c
similarity index 100%
rename from src/mainboard/dell/optiplex_3050/hda_verb.c
rename to src/mainboard/dell/sklkbl_desktops/variants/optiplex_3050/hda_verb.c
diff --git a/src/mainboard/dell/optiplex_3050/acpi/superio.asl b/src/mainboard/dell/sklkbl_desktops/variants/optiplex_3050/include/acpi/superio.asl
similarity index 100%
rename from src/mainboard/dell/optiplex_3050/acpi/superio.asl
rename to src/mainboard/dell/sklkbl_desktops/variants/optiplex_3050/include/acpi/superio.asl
diff --git a/src/mainboard/dell/optiplex_3050/devicetree.cb b/src/mainboard/dell/sklkbl_desktops/variants/optiplex_3050/overridetree.cb
similarity index 53%
rename from src/mainboard/dell/optiplex_3050/devicetree.cb
rename to src/mainboard/dell/sklkbl_desktops/variants/optiplex_3050/overridetree.cb
index dda5583a16..c5f1749b2c 100644
--- a/src/mainboard/dell/optiplex_3050/devicetree.cb
+++ b/src/mainboard/dell/sklkbl_desktops/variants/optiplex_3050/overridetree.cb
@@ -1,15 +1,8 @@
 ## SPDX-License-Identifier: GPL-2.0-only
 
 chip soc/intel/skylake
-	register "deep_sx_config" = "DSX_EN_WAKE_PIN | DSX_EN_LAN_WAKE_PIN"
-
-	# Enable Enhanced Intel SpeedStep
-	register "eist_enable" = "1"
 
 	device domain 0 on
-		device ref igpu on
-			register "PrimaryDisplay" = "Display_iGFX"
-		end
 
 		device ref south_xhci on
 			register "usb2_ports" = "{
@@ -29,22 +22,9 @@ chip soc/intel/skylake
 			}"
 		end
 
-		# ME interface is 'off' to avoid HECI reset delay due to HAP
-		device ref heci1 off end
-
 		device ref sata on
-			register "SataSalpSupport" = "1"
-			register "SataPortsEnable[0]" = "1"
-		end
-
-		# M.2 SSD
-		device ref pcie_rp21 on
-			register "PcieRpClkReqSupport[20]"              = "true"
-			register "PcieRpClkReqNumber[20]"               = "3"
-			register "PcieRpAdvancedErrorReporting[20]"     = "1"
-			register "PcieRpLtrEnable[20]"                  = "true"
-			register "PcieRpClkSrcNumber[20]"               = "3"
-			register "PcieRpHotPlug[20]"                    = "1"
+			register "SataSalpSupport"			= "1"
+			register "SataPortsEnable[0]"			= "1"
 		end
 
 		# Realtek LAN
@@ -59,42 +39,15 @@ chip soc/intel/skylake
 			register "PcieRpHotPlug[7]"			= "1"
 		end
 
-		# UART0 is exposed on test points on the bottom of the board
-		device ref uart0 on
-			register "SerialIoDevMode[PchSerialIoIndexUart0]" = "PchSerialIoPci"
+		# M.2 SSD
+		device ref pcie_rp21 on
+			register "PcieRpClkReqSupport[20]"              = "true"
+			register "PcieRpClkReqNumber[20]"               = "3"
+			register "PcieRpAdvancedErrorReporting[20]"     = "1"
+			register "PcieRpLtrEnable[20]"                  = "true"
+			register "PcieRpClkSrcNumber[20]"               = "3"
+			register "PcieRpHotPlug[20]"                    = "1"
 		end
 
-		device ref lpc_espi on
-			register "serirq_mode" = "SERIRQ_CONTINUOUS"
-
-			# I/O decode for EMI/Runtime registers
-			register "gen1_dec" = "0x007c0a01"
-
-			# SCH5553
-			chip superio/smsc/sch555x
-				device pnp 2e.0 on		# EMI
-					io 0x60 = 0xa00
-				end
-				device pnp 2e.1 off end		# 8042
-				device pnp 2e.7 on		# UART1
-					io 0x60 = 0x3f8
-					irq 0x0f = 2
-					irq 0x70 = 4
-				end
-				device pnp 2e.8 off end 	# UART2
-				device pnp 2e.c on		# LPC interface
-					io 0x60 = 0x2e
-				end
-				device pnp 2e.a on		# Runtime registers
-					io 0x60 = 0xa40
-				end
-				device pnp 2e.b  off end	# Floppy Controller
-				device pnp 2e.11 off end	# Parallel Port
-			end
-		end
-
-		device ref hda on end
-
-		device ref smbus on end
 	end
 end
diff --git a/src/mainboard/dell/optiplex_3050/romstage.c b/src/mainboard/dell/sklkbl_desktops/variants/optiplex_3050/romstage.c
similarity index 100%
rename from src/mainboard/dell/optiplex_3050/romstage.c
rename to src/mainboard/dell/sklkbl_desktops/variants/optiplex_3050/romstage.c

From 4068ba39f8457471219dbbd727735b307a482793 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Filip=20Lewi=C5=84ski?= <filip.lewinski@3mdeb.com>
Date: Fri, 21 Nov 2025 12:19:48 +0100
Subject: [PATCH 2691/3886] soc/intel/common/block/rtc/rtc.c: Top Swap: add
 Slot B selection mechanism
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

If the Top Swap mechanism is enabled, after running the bootblock from
the TOP_SWAP region, boot from an updatable COREBOOT_TS FMAP region.

Having flashed the TOP_SWAP bootblock and COREBOOT_TS, this allows the
user to boot a newer version of the firmware with the ability to
revert to the previous known-good version by performing a CMOS reset.

Requires having a read-write COREBOOT_TS region in the FMAP file.

This is part of an ongoing implementation of a redundancy feature
proposed on the mailing list:
https://mail.coreboot.org/archives/list/coreboot@coreboot.org/thread/C6JN2PB7K7D67EG7OIKB6BBERZU5YV35/

TEST=Boot Protectli VP6650, setting the attempt_slot_b flag to
different values, observing the "Booting from COREBOOT/COREBOOT_TS
region" prints correspondingly.

Change-Id: Ieadc9bfbe940cbec79eb84f16a5d622bfbb82ede
Signed-off-by: Filip Lewiński <filip.lewinski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90147
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com>
---
 Makefile.mk                          | 14 ++++++++------
 src/cpu/intel/fit/Makefile.mk        |  3 +++
 src/include/fmap.h                   |  4 ++++
 src/lib/cbfs.c                       | 16 ++++++++++++++--
 src/soc/intel/common/block/rtc/rtc.c | 13 +++++++++++++
 5 files changed, 42 insertions(+), 8 deletions(-)

diff --git a/Makefile.mk b/Makefile.mk
index 93a26d0d95..75787b32d4 100644
--- a/Makefile.mk
+++ b/Makefile.mk
@@ -979,6 +979,14 @@ extract_nth=$(subst *,$(spc),$(patsubst -%-,%,$(word $(1), $(subst |,- -,-$(2)-)
 # multiple CBFSes in fmap regions, override it.
 regions-for-file ?= $(if $(value regions-for-file-$(1)), $(regions-for-file-$(1)), COREBOOT)
 
+ifeq ($(CONFIG_INTEL_ADD_TOP_SWAP_BOOTBLOCK),y)
+ifneq ($(CONFIG_INTEL_TOP_SWAP_SEPARATE_REGIONS),y)
+TS_OPTIONS := -j $(CONFIG_INTEL_TOP_SWAP_BOOTBLOCK_SIZE)
+else
+regions-for-file = $(if $(value regions-for-file-$(1)), $(regions-for-file-$(1)), COREBOOT,COREBOOT_TS)
+endif
+endif
+
 ifeq ($(CONFIG_CBFS_AUTOGEN_ATTRIBUTES),y)
 	cbfs-autogen-attributes=-g
 endif
@@ -1260,12 +1268,6 @@ $(obj)/fmap.fmap: $(obj)/fmap.fmd $(FMAPTOOL)
 	echo "    FMAP       $(FMAPTOOL) -h $(obj)/fmap_config.h $< $@"
 	$(FMAPTOOL) -h $(obj)/fmap_config.h -R $(obj)/fmap.desc $< $@
 
-ifeq ($(CONFIG_INTEL_ADD_TOP_SWAP_BOOTBLOCK),y)
-ifneq ($(CONFIG_INTEL_TOP_SWAP_SEPARATE_REGIONS),y)
-TS_OPTIONS := -j $(CONFIG_INTEL_TOP_SWAP_BOOTBLOCK_SIZE)
-endif
-endif
-
 ifneq ($(CONFIG_INTEL_TOP_SWAP_SEPARATE_REGIONS),y)
 BB_FIT_REGION = COREBOOT
 TS_FIT_REGION = COREBOOT
diff --git a/src/cpu/intel/fit/Makefile.mk b/src/cpu/intel/fit/Makefile.mk
index c8bb5bd26f..2729c0a6ae 100644
--- a/src/cpu/intel/fit/Makefile.mk
+++ b/src/cpu/intel/fit/Makefile.mk
@@ -66,6 +66,9 @@ pbp.bin-type := raw
 $(call add_intermediate, add_pbp_fit, set_fit_ptr $(IFITTOOL))
 	@printf "    UPDATE-FIT Platform Boot Policy binary\n"
 	$(IFITTOOL) -f $< -a -n pbp.bin -t 4 -s $(CONFIG_CPU_INTEL_NUM_FIT_ENTRIES) -r COREBOOT
+ifeq ($(CONFIG_INTEL_TOP_SWAP_SEPARATE_REGIONS),y)
+	$(IFITTOOL) -f $< -a -n pbp.bin -t 4 -s $(CONFIG_CPU_INTEL_NUM_FIT_ENTRIES) -r COREBOOT_TS
+endif
 
 endif # CONFIG_HAVE_PBP_BIN
 
diff --git a/src/include/fmap.h b/src/include/fmap.h
index fc49dbdf5e..900bfff542 100644
--- a/src/include/fmap.h
+++ b/src/include/fmap.h
@@ -13,6 +13,10 @@
 	#error "FMAP must always start flash address 0"
 #endif
 
+/* Return the name of the boot region. Falls back to COREBOOT, if not overridden
+ * by any multi-slot mechanism (e.g Intel Top Swap, vboot). */
+const char *cbfs_fmap_region_hint(void);
+
 /* Locate the named area in the fmap and fill in a region device representing
  * that area. The region is a sub-region of the readonly boot media. Return
  * 0 on success, < 0 on error. */
diff --git a/src/lib/cbfs.c b/src/lib/cbfs.c
index fab64d3b7b..0c47359260 100644
--- a/src/lib/cbfs.c
+++ b/src/lib/cbfs.c
@@ -31,6 +31,11 @@ struct mem_pool cbfs_cache =
 	MEM_POOL_INIT(_cbfs_cache, REGION_SIZE(cbfs_cache), CONFIG_CBFS_CACHE_ALIGN);
 #endif
 
+__weak const char *cbfs_fmap_region_hint(void)
+{
+	return "COREBOOT";
+}
+
 static void switch_to_postram_cache(int unused)
 {
 	if (_preram_cbfs_cache != _postram_cbfs_cache)
@@ -670,6 +675,7 @@ enum cb_err cbfs_init_boot_device(const struct cbfs_boot_device *cbd,
 
 const struct cbfs_boot_device *cbfs_get_boot_device(bool force_ro)
 {
+	printk(BIOS_DEBUG, "Starting cbfs_boot_device\n");
 	static struct cbfs_boot_device ro;
 
 	/* Ensure we always init RO mcache, even if the first file is from the RW CBFS.
@@ -693,8 +699,14 @@ const struct cbfs_boot_device *cbfs_get_boot_device(bool force_ro)
 	if (region_device_sz(&ro.rdev))
 		return &ro;
 
-	if (fmap_locate_area_as_rdev("COREBOOT", &ro.rdev))
-		die("Cannot locate primary CBFS");
+	/* Falls back to the default COREBOOT region if no overriding mechanisms are in
+	   place (e.g. Intel Top Swap). */
+	const char *region = cbfs_fmap_region_hint();
+
+	if (fmap_locate_area_as_rdev(region, &ro.rdev))
+		die("Cannot locate %s CBFS", region);
+
+	printk(BIOS_INFO, "Booting from %s region\n", region);
 
 	if (ENV_INITIAL_STAGE) {
 		enum cb_err err = cbfs_init_boot_device(&ro, metadata_hash_get());
diff --git a/src/soc/intel/common/block/rtc/rtc.c b/src/soc/intel/common/block/rtc/rtc.c
index fd8dc88755..25c4444511 100644
--- a/src/soc/intel/common/block/rtc/rtc.c
+++ b/src/soc/intel/common/block/rtc/rtc.c
@@ -1,5 +1,6 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
+#include <fmap.h>
 #include <intelblocks/pcr.h>
 #include <intelblocks/rtc.h>
 #include <option.h>
@@ -69,4 +70,16 @@ void sync_rtc_buc_top_swap(void)
 		board_reset();
 	}
 }
+
+/*
+ * Select the FMAP region to continue booting from, depending on the state of
+ * Top Swap
+ */
+const char *cbfs_fmap_region_hint(void)
+{
+	if (CONFIG(INTEL_TOP_SWAP_OPTION_CONTROL) && get_rtc_buc_top_swap_status())
+		return "COREBOOT_TS";
+	else
+		return "COREBOOT";
+}
 #endif

From 23b00a06da929f487743bad96ec905e9f0e9285d Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Wed, 19 Nov 2025 09:23:18 +0000
Subject: [PATCH 2692/3886] drivers/intel/gma: Fix brightness handling with
 valid-cache logic

The existing brightness level fallback logic duplicated the default
backlight value by hardcoding BRLV to 100% (0x64). This caused divergence
whenever a platform defined a different default brightness through BRIG[0].

This change removes the duplicated default and replaces it with a cached
brightness mechanism using BRVA (valid flag) and BRLV (cached level).
The firmware now:

 - Caches the last brightness level exposed to the OS.
 - Uses the cached level during early boot/resume when the OpRegion
   (BCLM/BCLV) is not yet initialized.
 - Falls back to BRIG[0] only when no cached brightness exists.
 - Preserves the existing replay-detection logic to keep firmware and OS
   brightness state aligned once the graphics driver is active.

This ensures consistent brightness reporting, avoids incorrect 0% fallback
values, and respects board-specific BRIG defaults.

No functional changes occur once the graphics driver has initialized the
OpRegion; the improvement only affects early boot/resume behavior and
eliminates duplicated platform policy.

Change-Id: I651dfd30aa0c283b4e0659e5d19051e1b58204fe
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90116
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
---
 .../gma/acpi/configure_brightness_levels.asl  | 23 +++++++++++++------
 1 file changed, 16 insertions(+), 7 deletions(-)

diff --git a/src/drivers/intel/gma/acpi/configure_brightness_levels.asl b/src/drivers/intel/gma/acpi/configure_brightness_levels.asl
index 9fb30f0039..11a7dd7725 100644
--- a/src/drivers/intel/gma/acpi/configure_brightness_levels.asl
+++ b/src/drivers/intel/gma/acpi/configure_brightness_levels.asl
@@ -1,6 +1,8 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
-	Name (BRLV, 100)
+	Name (BRLV, 0) /* Brightness Last Value */
+	Name (BRVA, 0) /* Brightness Valid */
+
 	/*
 	 * Pseudo device that contains methods to modify Opregion
 	 * "Mailbox 3 BIOS to Driver Notification"
@@ -149,6 +151,7 @@
 	Method (XBCM, 1, NotSerialized)
 	{
 		BRLV = Arg0
+		BRVA = 1
 		If (^BOX3.XBCM (Arg0) == Ones)
 		{
 			/*
@@ -167,16 +170,21 @@
 		/*
 		 * During early boot / resume the IGD driver has not yet populated
 		 * the OpRegion brightness fields (BCLM stays zero), so fall back to
-		 * the cached value we last exposed to the OS.
+		 * the cached value we last exposed to the OS. If there's no cached
+		 * value yet, use the platform's default from BRIG[0].
 		 */
-		If (BCLM == 0)
-		{
-			Return (BRLV)
+		If (BCLM == 0) {
+			If (BRVA != 0) {
+				Return (BRLV)
+			}
+
+			/* No cached brightness yet, fall back to platform default. */
+			Local0 = DeRefOf (BRIG[0])
+			Return (Local0)
 		}
 
 		Local0 = ^LEGA.XBQC ()
-		If (Local0 != BRLV)
-		{
+		If (BRVA != 0 && Local0 != BRLV) {
 			/*
 			 * The OS replays _BCM requests while the graphics driver is
 			 * still reinitializing, so hardware brightness can diverge
@@ -193,5 +201,6 @@
 			}
 		}
 		BRLV = Local0
+		BRVA = 1
 		Return (Local0)
 	}

From 7a98a62f7b2c544b6f8d2ee4c8289175db5bc0c7 Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Sun, 30 Nov 2025 20:48:31 +0000
Subject: [PATCH 2693/3886] drivers/intel/gma: Unify coding style

The breaks for `if` and `else` are inconsistent; remove all breaks for
these.

Change-Id: Ie76f38387fd5ef330b432c0462cb1101571c73db
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90286
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
---
 .../gma/acpi/configure_brightness_levels.asl      | 15 +++++----------
 1 file changed, 5 insertions(+), 10 deletions(-)

diff --git a/src/drivers/intel/gma/acpi/configure_brightness_levels.asl b/src/drivers/intel/gma/acpi/configure_brightness_levels.asl
index 11a7dd7725..4400f5159c 100644
--- a/src/drivers/intel/gma/acpi/configure_brightness_levels.asl
+++ b/src/drivers/intel/gma/acpi/configure_brightness_levels.asl
@@ -66,8 +66,7 @@
 			/* also set valid bit */
 			BCLP = Local1 | 0x80000000
 
-			If (ARDY == 0)
-			{
+			If (ARDY == 0) {
 				Return (Ones)
 			}
 
@@ -77,8 +76,7 @@
 			ASLE = 0x1
 
 			Local0 = 0x20
-			While (Local0 > 0)
-			{
+			While (Local0 > 0) {
 				Sleep (1)
 				If ((ASLC & 2) == 0) {
 					/* Request has been processed, check status: */
@@ -118,8 +116,7 @@
 		Method (XBQC, 0, NotSerialized)
 		{
 			/* Prevent DivideByZero if backlight control isn't enabled */
-			If (BCLM == 0)
-			{
+			If (BCLM == 0) {
 				Return (0)
 			}
 			/* Local0: current percentage */
@@ -152,14 +149,12 @@
 	{
 		BRLV = Arg0
 		BRVA = 1
-		If (^BOX3.XBCM (Arg0) == Ones)
-		{
+		If (^BOX3.XBCM (Arg0) == Ones) {
 			/*
 			 * Only touch the legacy PWM registers after the graphics driver
 			 * reprograms them during boot/resume (BCLM stays zero until then).
 			 */
-			If (BCLM != 0)
-			{
+			If (BCLM != 0) {
 				^LEGA.XBCM (Arg0)
 			}
 		}

From 8b97968e53d4b0ba6ecbe10dcc0890218de888e4 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Micha=C5=82=20=C5=BBygowski?= <michal.zygowski@3mdeb.com>
Date: Tue, 9 Sep 2025 10:14:11 +0200
Subject: [PATCH 2694/3886] soc/amd/common/block/pci/amd_pci_mmconf.c: Support
 64bit ECAM MMCONF
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

More complex systems, such as servers, may have scarse space below 4G
for MMIO. With multiple root bridges needing some 32bit MMIO space it
becomes very hard to squeeze all resources. Allow to set 64bit ECAM
MMCONF base address in the MSR to free some space in the 32bit address
space. Of course using 64bit ECAM MMCONF requires the use of x86_64
mode and a proper amount of address space to be mapped with page
tables.

TEST=Set ECAM MMCONF to 0x3ffb00000000 on Gigabyte MZ33-AR1 and observe
the PCI access works in the console output.

Change-Id: I80e5a1bed33e12aa089355df64cc29887acc27f2
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89112
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/soc/amd/common/block/pci/amd_pci_mmconf.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/soc/amd/common/block/pci/amd_pci_mmconf.c b/src/soc/amd/common/block/pci/amd_pci_mmconf.c
index e02bcde248..e436c112f6 100644
--- a/src/soc/amd/common/block/pci/amd_pci_mmconf.c
+++ b/src/soc/amd/common/block/pci/amd_pci_mmconf.c
@@ -10,8 +10,8 @@ void enable_pci_mmconf(void)
 {
 	msr_t mmconf;
 
-	mmconf.hi = 0;
-	mmconf.lo = CONFIG_ECAM_MMCONF_BASE_ADDRESS | MMIO_RANGE_EN
+	mmconf.hi = (uint64_t)CONFIG_ECAM_MMCONF_BASE_ADDRESS >> 32;
+	mmconf.lo = (CONFIG_ECAM_MMCONF_BASE_ADDRESS & 0xfff00000) | MMIO_RANGE_EN
 			| __fls(CONFIG_ECAM_MMCONF_BUS_NUMBER) << MMIO_BUS_RANGE_SHIFT;
 	wrmsr(MMIO_CONF_BASE, mmconf);
 }

From 33fc33c132c03de6d92734516c6d6490c2f1fe12 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Micha=C5=82=20=C5=BBygowski?= <michal.zygowski@3mdeb.com>
Date: Wed, 10 Sep 2025 23:13:10 +0200
Subject: [PATCH 2695/3886] soc/amd/common/block/cpu/noncar: Add support for
 bootblock CRTM init
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

On AMD non-car system the bootblock is integrated into PSP directories
and copied to host DRAM before reset vector. coreboot knows the exact
DRAM range where the bootblock will be copied to based on
CONFIG_ROMSTAGE_ADDR and CONFIG_C_ENV_BOOTBLOCK_SIZE. The code only
needs to check the exact coreboot program size using linker symbols
measure the right memory range.

Based on the Apollo Lake tspi_soc_measure_bootblock, create an
equivalent implementation for AMD platforms using mem_region_device.

TEST=Bootblock is measured properly on Gigabyte MZ33-AR1 when measured
boot is enabled and CRTM initialization no longer fails.

Change-Id: I163e6b0ef0313e7dbb66ba5b07c35724a14276aa
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89145
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 .../block/cpu/noncar/bootblock_measure.c      | 51 ++++++++++++++++++-
 1 file changed, 50 insertions(+), 1 deletion(-)

diff --git a/src/soc/amd/common/block/cpu/noncar/bootblock_measure.c b/src/soc/amd/common/block/cpu/noncar/bootblock_measure.c
index 16ba154bb7..77270a4e5e 100644
--- a/src/soc/amd/common/block/cpu/noncar/bootblock_measure.c
+++ b/src/soc/amd/common/block/cpu/noncar/bootblock_measure.c
@@ -1,8 +1,57 @@
 /* SPDX-License-Identifier: GPL-2.0-or-later */
 
+#include <commonlib/region.h>
 #include <security/tpm/tspi/crtm.h>
+#include <stddef.h>
+#include <stdint.h>
+#include <symbols.h>
 
+#define BOOTBLOCK_BASE	(CONFIG_ROMSTAGE_ADDR - CONFIG_C_ENV_BOOTBLOCK_SIZE)
+
+/* This region device covers the maximum range where bootblock can reside */
+static const struct mem_region_device bootblock_rdev =
+	MEM_REGION_DEV_RO_INIT(BOOTBLOCK_BASE, CONFIG_C_ENV_BOOTBLOCK_SIZE);
+
+
+static const struct region_device *get_bootblock_rdev(void)
+{
+	return &bootblock_rdev.rdev;
+}
+
+static const size_t get_bootblock_base(void)
+{
+	return (size_t)(bootblock_rdev.base);
+}
+
+/*
+ * The linker symbols _bootblock and _ebootblock provides the beginning and
+ * the end of the bootblock. Use them to get the start address offset of the
+ * bootblock in the RAM.
+ */
+static int locate_bootblock_as_rdev(struct region_device *rdev)
+{
+	size_t offset = (size_t)((uintptr_t)_bootblock - get_bootblock_base());
+	size_t size = (size_t)((uintptr_t)_ebootblock - (uintptr_t)_bootblock);
+
+	return rdev_chain(rdev, get_bootblock_rdev(), offset, size);
+}
+
+/*
+ * On AMD non-CAR system the bootblock is stitched into the PSP BIOS directory
+ * at build time. At execution time PSP loads the bootblock and uncompressed it
+ * into the host RAM. Then the CPU starts to operate from this RAM as it were
+ * in flash space. In order to provide a reliable CRTM init, the real executed
+ * bootblock code needs to be measured into TPM if VBOOT is selected.
+ */
 int tspi_soc_measure_bootblock(int pcr_index)
 {
-	return 1;
+	struct region_device rdev;
+
+	if (locate_bootblock_as_rdev(&rdev))
+		return 1;
+
+	if (tpm_measure_region(&rdev, pcr_index, "bootblock"))
+		return 1;
+
+	return 0;
 }

From 3bd554feb2be49e7af82a8932a8ca4ad3c521764 Mon Sep 17 00:00:00 2001
From: Crystal Guo <crystal.guo@mediatek.corp-partner.google.com>
Date: Fri, 28 Nov 2025 10:40:44 +0800
Subject: [PATCH 2696/3886] soc/mediatek/mt8196: Align the struct for storing
 DRAM calibration data

The current read calibration data flow may cause memory overwrite due to
struct size mismatch, resulting in fast calibration flow failure. Need
to align the struct for storing DRAM calibration data between coreboot
and mtk-dramk repo to prevent memory overwrite.

BUG=b:450724525
TEST=Bootup ok.

Change-Id: Ic59bc9c7f12c454702ba894dea5dce94984e2121
Signed-off-by: Crystal Guo <crystal.guo@mediatek.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90354
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: jason-ch chen <Jason-ch.Chen@mediatek.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/soc/mediatek/mt8196/include/soc/dramc_param.h | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/src/soc/mediatek/mt8196/include/soc/dramc_param.h b/src/soc/mediatek/mt8196/include/soc/dramc_param.h
index 819b1af6ce..7902336bc0 100644
--- a/src/soc/mediatek/mt8196/include/soc/dramc_param.h
+++ b/src/soc/mediatek/mt8196/include/soc/dramc_param.h
@@ -13,7 +13,7 @@
 #include <stdint.h>
 #include <sys/types.h>
 
-#define DRAMC_PARAM_HEADER_VERSION 4
+#define DRAMC_PARAM_HEADER_VERSION 5
 
 struct sdram_params {
 	/* rank, cbt */
@@ -21,7 +21,7 @@ struct sdram_params {
 	u32 dram_cbt_mode;
 
 	u16 delay_cell_timex100;
-	u8 u18ph_dly;
+	u8 u18ph_dly[CHANNEL_MAX];
 
 	/* duty */
 	s8 duty_clk_delay[CHANNEL_MAX][RANK_MAX];
@@ -91,7 +91,7 @@ struct sdram_params {
 	/* tx oe */
 	u8 tx_oe_dq_mck[CHANNEL_MAX][RANK_MAX][DQS_NUMBER_LP5];
 	u8 tx_oe_dq_ui[CHANNEL_MAX][RANK_MAX][DQS_NUMBER_LP5];
-	u16 tx_oe_offset[CHANNEL_MAX][RANK_MAX];
+	u16 tx_oe_offset[DQS_NUMBER_LP5];
 };
 
 struct dramc_data {

From 1a0d123ec13c28c45abd46f3bb75ceec400be77d Mon Sep 17 00:00:00 2001
From: Subrata Banik <subratabanik@google.com>
Date: Wed, 3 Dec 2025 12:30:42 +0530
Subject: [PATCH 2697/3886] ec/google/chromeec: Update EC headers

Generated using update_ec_headers.sh from EC repo commit:

  3a592ab3640 ("caboc: Correct thermal table logic")

BUG=none
BRANCH=none
TEST=Able to build google/quenbi.

Change-Id: I370130d59d035fe32feabeb982e64e4a6784854a
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90355
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/ec/google/chromeec/ec_commands.h | 39 ++++++++++++++++++++++++++++
 1 file changed, 39 insertions(+)

diff --git a/src/ec/google/chromeec/ec_commands.h b/src/ec/google/chromeec/ec_commands.h
index 091a9fbabb..1dbb7115f6 100644
--- a/src/ec/google/chromeec/ec_commands.h
+++ b/src/ec/google/chromeec/ec_commands.h
@@ -1776,6 +1776,10 @@ enum ec_feature_code {
 	 * The EC supports PoE.
 	 */
 	EC_FEATURE_POE = 56,
+	/*
+	 * The EC supports a hybrid boost charger
+	 */
+	EC_FEATURE_CHARGER_HYBRID_POWER_BOOST = 57,
 };
 
 #define EC_FEATURE_MASK_0(event_code) BIT(event_code % 32)
@@ -5821,6 +5825,7 @@ enum ec_reboot_cmd {
 };
 
 /* Flags for ec_params_reboot_ec.reboot_flags */
+#define EC_REBOOT_FLAG_IMMEDIATE 0 /* Trigger Cold Reset */
 #define EC_REBOOT_FLAG_RESERVED0 BIT(0) /* Was recovery request */
 #define EC_REBOOT_FLAG_ON_AP_SHUTDOWN BIT(1) /* Reboot after AP shutdown */
 #define EC_REBOOT_FLAG_SWITCH_RW_SLOT BIT(2) /* Switch RW slot */
@@ -5970,6 +5975,18 @@ struct ec_params_panic_log_read {
  * host_cmd_handler_args.response and host_cmd_handler_args.response_size.
  */
 
+/*
+ * Enter bootloader mode
+ *
+ * This command requests EC to enter bootloader mode.
+ */
+#define EC_CMD_ENTER_BOOTLOADER 0x00E2
+
+struct ec_params_enter_bootloader {
+	/* Mode to enter bootloader. Chip specific value. Can be unused. */
+	uint8_t mode;
+} __ec_align1;
+
 /*****************************************************************************/
 /*
  * PD commands
@@ -8659,6 +8676,20 @@ struct ec_params_fp_read_match_secret {
 	uint16_t fgr;
 } __ec_align4;
 
+/*
+ * Fingerprint vendor defined command.
+ *
+ * A custom per fingerprint vendor host command. It can be used to fetch some
+ * custom data during testing, manufacturing etc.
+ *
+ * This command should be handled only if the system is unlocked.
+ */
+#define EC_CMD_FP_VENDOR 0x040B
+struct ec_params_fp_vendor {
+	/* Parameter to be used by FP vendors. */
+	uint32_t param1;
+} __ec_align4;
+
 /* The positive match secret has the length of the SHA256 digest. */
 #define FP_POSITIVE_MATCH_SECRET_BYTES 32
 struct ec_response_fp_read_match_secret {
@@ -8960,6 +8991,14 @@ struct ec_response_get_boot_time {
 /* Issue AP shutdown */
 #define EC_CMD_AP_SHUTDOWN 0x0605
 
+/**
+ * Issue AP shutdown using heartbeat wake.
+ * The AP calls this to enter the low-power G3 state for off-mode charging.
+ * The EC then monitors battery SoC and wakes the AP when discharged by a
+ * configured threshold.
+ */
+#define EC_CMD_ENABLE_OFFMODE_HEARTBEAT 0x0606
+
 /*****************************************************************************/
 /*
  * Reserve a range of host commands for board-specific, experimental, or

From c77d256886b5b2c5a62bc2aca2af65761a0dec73 Mon Sep 17 00:00:00 2001
From: Subrata Banik <subratabanik@google.com>
Date: Sun, 30 Nov 2025 10:30:16 +0530
Subject: [PATCH 2698/3886] {mb, security}: Use EC_REBOOT_FLAG_IMMEDIATE for
 cold reboots

The value 0 passed as the reboot_flags argument to
google_chromeec_reboot is now explicitly defined as
EC_REBOOT_FLAG_IMMEDIATE in ec_commands.h.

Update calls to google_chromeec_reboot with EC_REBOOT_COLD to use the
new flag for clarity and to ensure the intended EC-based reboot is
performed.

This change doesn't introduce anything new, so there's no change
in behavior.

Change-Id: I6701c94101c5085cfcc7fbf2e614c4f23d843225
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90278
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
---
 src/mainboard/google/bluey/reset.c     | 2 +-
 src/mainboard/google/herobrine/reset.c | 2 +-
 src/mainboard/google/trogdor/reset.c   | 2 +-
 src/security/vboot/ec_sync.c           | 2 +-
 4 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/src/mainboard/google/bluey/reset.c b/src/mainboard/google/bluey/reset.c
index b10e4d481a..deb0ba8096 100644
--- a/src/mainboard/google/bluey/reset.c
+++ b/src/mainboard/google/bluey/reset.c
@@ -8,5 +8,5 @@
 void do_board_reset(void)
 {
 	if (CONFIG(EC_GOOGLE_CHROMEEC))
-		google_chromeec_reboot(EC_REBOOT_COLD, 0);
+		google_chromeec_reboot(EC_REBOOT_COLD, EC_REBOOT_FLAG_IMMEDIATE);
 }
diff --git a/src/mainboard/google/herobrine/reset.c b/src/mainboard/google/herobrine/reset.c
index d64c650b99..32dd8b3cf4 100644
--- a/src/mainboard/google/herobrine/reset.c
+++ b/src/mainboard/google/herobrine/reset.c
@@ -7,5 +7,5 @@
    but this works well enough for our purposes. */
 void do_board_reset(void)
 {
-	google_chromeec_reboot(EC_REBOOT_COLD, 0);
+	google_chromeec_reboot(EC_REBOOT_COLD, EC_REBOOT_FLAG_IMMEDIATE);
 }
diff --git a/src/mainboard/google/trogdor/reset.c b/src/mainboard/google/trogdor/reset.c
index d64c650b99..32dd8b3cf4 100644
--- a/src/mainboard/google/trogdor/reset.c
+++ b/src/mainboard/google/trogdor/reset.c
@@ -7,5 +7,5 @@
    but this works well enough for our purposes. */
 void do_board_reset(void)
 {
-	google_chromeec_reboot(EC_REBOOT_COLD, 0);
+	google_chromeec_reboot(EC_REBOOT_COLD, EC_REBOOT_FLAG_IMMEDIATE);
 }
diff --git a/src/security/vboot/ec_sync.c b/src/security/vboot/ec_sync.c
index e1d435e7cf..030c391ba0 100644
--- a/src/security/vboot/ec_sync.c
+++ b/src/security/vboot/ec_sync.c
@@ -56,7 +56,7 @@ void vboot_sync_ec(void)
 
 	case VB2_REQUEST_REBOOT_EC_TO_RO:
 		printk(BIOS_INFO, "EC Reboot requested. Doing cold reboot\n");
-		if (google_chromeec_reboot(EC_REBOOT_COLD, 0))
+		if (google_chromeec_reboot(EC_REBOOT_COLD, EC_REBOOT_FLAG_IMMEDIATE))
 			printk(BIOS_EMERG, "Failed to get EC to cold reboot\n");
 
 		halt();

From fc9f828ac07a0df029ba0ade4e3c14340f3cf17c Mon Sep 17 00:00:00 2001
From: Subrata Banik <subratabanik@google.com>
Date: Thu, 4 Dec 2025 05:52:50 +0000
Subject: [PATCH 2699/3886] mainboard/google/bluey: Select
 VBOOT_ALWAYS_ENABLE_DISPLAY

This change ensures that the display is always enabled for the Google
Bluey mainboard as firmware splash screen is POR for this device..

This change helps to avoid an additional reset while doing EC sync
operation by payload.

BUG=none
BRANCH=none
TEST=Able to avoid one additional resets during EC SW sync.

Change-Id: If1d8788cbbd72d6bc4397b1b7160e9f4669716db
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90361
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
---
 src/mainboard/google/bluey/Kconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/src/mainboard/google/bluey/Kconfig b/src/mainboard/google/bluey/Kconfig
index 53f6de67d8..249990c9f8 100644
--- a/src/mainboard/google/bluey/Kconfig
+++ b/src/mainboard/google/bluey/Kconfig
@@ -119,6 +119,7 @@ config MAINBOARD_VENDOR
 	default "Google"
 
 config VBOOT
+	select VBOOT_ALWAYS_ENABLE_DISPLAY
 	select VBOOT_NO_BOARD_SUPPORT if BOARD_GOOGLE_MODEL_BLUEY
 	select VBOOT_VBNV_FLASH
 

From 1d70286d4eb03385449f6aaf9db20387e1853ca6 Mon Sep 17 00:00:00 2001
From: Venkateshwar S <vens@qualcomm.corp-partner.google.com>
Date: Sat, 29 Nov 2025 08:34:04 -0800
Subject: [PATCH 2700/3886] soc/qualcomm/common: Add support for loading APDP
 image

This patch introduces a new Kconfig option, QC_APDP_ENABLE, to control
Application Processor Debug Policy (APDP) image loading. When this
option is enabled, the APDP image is loaded during the
qclib_load_and_run() sequence. It also adds a new CBFS file entry and
table entry definition for apdp_meta, along with a memory region symbol
apdp_ramdump_meta for metadata storage.

TEST=Create an image.serial.bin and ensure it boots on X1P42100.

Change-Id: I8d0847c99a1129359f2c758b7a07b9c022f1c8c8
Signed-off-by: Venkateshwar S <vens@qualcomm.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90303
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/soc/qualcomm/common/Kconfig               |  8 +++++++
 .../common/include/soc/qclib_common.h         |  2 ++
 .../common/include/soc/symbols_common.h       |  1 +
 src/soc/qualcomm/common/qclib.c               | 24 +++++++++++++++++++
 4 files changed, 35 insertions(+)

diff --git a/src/soc/qualcomm/common/Kconfig b/src/soc/qualcomm/common/Kconfig
index eca772ce59..9420087521 100644
--- a/src/soc/qualcomm/common/Kconfig
+++ b/src/soc/qualcomm/common/Kconfig
@@ -25,4 +25,12 @@ config QC_SDI_ENABLE
 	default n
 	prompt "Debug Build: enable SDI"
 
+config QC_APDP_ENABLE
+	bool
+	default n
+	prompt "Debug Build: enable APDP"
+	help
+	  Application Processor Debug Policy (APDP) is a configuration image
+	  to define and enforce debugging capabilities and restrictions for APPS.
+
 endif
diff --git a/src/soc/qualcomm/common/include/soc/qclib_common.h b/src/soc/qualcomm/common/include/soc/qclib_common.h
index e05663bae1..572b479e90 100644
--- a/src/soc/qualcomm/common/include/soc/qclib_common.h
+++ b/src/soc/qualcomm/common/include/soc/qclib_common.h
@@ -28,6 +28,7 @@
 #define QCLIB_TE_SHRM_META_SETTINGS	"shrm_metadata"
 #define QCLIB_TE_AOP_META_SETTINGS      "aop_metadata"
 #define QCLIB_TE_AOP_DEVCFG_META_SETTINGS	"aop_cfg_metadata"
+#define QCLIB_TE_APDP_META_SETTINGS	"apdp_metadata"
 
 /* BA_BMASK_VALUES (blob_attributes bit mask values) */
 #define QCLIB_BA_SAVE_TO_STORAGE 0x00000001
@@ -42,6 +43,7 @@ enum qclib_cbfs_file {
 	QCLIB_CBFS_SHRM_META,
 	QCLIB_CBFS_AOP_META,
 	QCLIB_CBFS_AOP_DEVCFG_META,
+	QCLIB_CBFS_APDP_META,
 	QCLIB_CBFS_MAX
 };
 
diff --git a/src/soc/qualcomm/common/include/soc/symbols_common.h b/src/soc/qualcomm/common/include/soc/symbols_common.h
index f679a6a2ab..6d6ff38635 100644
--- a/src/soc/qualcomm/common/include/soc/symbols_common.h
+++ b/src/soc/qualcomm/common/include/soc/symbols_common.h
@@ -17,6 +17,7 @@ DECLARE_REGION(dtb)
 DECLARE_REGION(cpr_settings)
 DECLARE_REGION(qc_blob_meta)
 DECLARE_REGION(aop_blob_meta)
+DECLARE_REGION(apdp_ramdump_meta)
 DECLARE_OPTIONAL_REGION(pmic)
 DECLARE_REGION(limits_cfg)
 DECLARE_REGION(aop)
diff --git a/src/soc/qualcomm/common/qclib.c b/src/soc/qualcomm/common/qclib.c
index dd679964cd..cb33170ea1 100644
--- a/src/soc/qualcomm/common/qclib.c
+++ b/src/soc/qualcomm/common/qclib.c
@@ -94,6 +94,8 @@ const char *qclib_file_default(enum qclib_cbfs_file file)
 		return CONFIG_CBFS_PREFIX "/aop_meta";
 	case QCLIB_CBFS_AOP_DEVCFG_META:
 		return CONFIG_CBFS_PREFIX "/aop_devcfg_meta";
+	case QCLIB_CBFS_APDP_META:
+		return CONFIG_CBFS_PREFIX "/apdp_meta";
 	default:
 		die("unknown QcLib file %d", file);
 	}
@@ -314,6 +316,28 @@ void qclib_load_and_run(void)
 		goto fail;
 	}
 
+	/* Load APDP image */
+	if (CONFIG(QC_APDP_ENABLE)) {
+		struct prog apdp_prog =
+				PROG_INIT(PROG_PAYLOAD, CONFIG_CBFS_PREFIX "/apdp");
+
+		if (!selfload(&apdp_prog))
+			die("SOC image: APDP load failed");
+
+		/* Attempt to load apdp_meta Blob. */
+		data_size = cbfs_load(qclib_file(QCLIB_CBFS_APDP_META),
+				_apdp_ramdump_meta, REGION_SIZE(apdp_ramdump_meta));
+		if (!data_size) {
+			printk(BIOS_ERR,
+				"[%s] /apdp_meta not loaded\n"
+				"apdp_meta is mandatory for APDP authentication; failure is fatal\n"
+				, __func__);
+			goto fail;
+		}
+
+		qclib_add_if_table_entry(QCLIB_TE_APDP_META_SETTINGS, _apdp_ramdump_meta, data_size, 0);
+	}
+
 	/* Attempt to load QCLib elf */
 	qclib = (struct prog)
 		PROG_INIT(PROG_REFCODE, qclib_file(QCLIB_CBFS_QCLIB));

From 3c563669b573d1f3ef79db8a075355612480cd96 Mon Sep 17 00:00:00 2001
From: Venkateshwar S <vens@qualcomm.corp-partner.google.com>
Date: Sat, 29 Nov 2025 08:52:37 -0800
Subject: [PATCH 2701/3886] soc/qualcomm/x1p42100: Add support for APDP image
 packing in CBFS

This patch adds build rules for packing the APDP image in CBFS.
It also updates the memory layout to include a dedicated region
for APDP metadata storage (4KB at 0x14890000).

TEST=Create an image.serial.bin and ensure it boots on X1P42100.

Change-Id: Ia3093ef6619dd504c829cf6ba6f672f16070f68a
Signed-off-by: Venkateshwar S <vens@qualcomm.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90302
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
---
 src/soc/qualcomm/x1p42100/Makefile.mk  | 25 +++++++++++++++++++++++++
 src/soc/qualcomm/x1p42100/memlayout.ld |  3 +++
 2 files changed, 28 insertions(+)

diff --git a/src/soc/qualcomm/x1p42100/Makefile.mk b/src/soc/qualcomm/x1p42100/Makefile.mk
index 85191ea52c..787d0db78b 100644
--- a/src/soc/qualcomm/x1p42100/Makefile.mk
+++ b/src/soc/qualcomm/x1p42100/Makefile.mk
@@ -295,6 +295,31 @@ $(HYPAC_CFG_FILE_CBFS)-type := payload
 $(HYPAC_CFG_FILE_CBFS)-compression := $(CBFS_COMPRESS_FLAG)
 cbfs-files-y += $(HYPAC_CFG_FILE_CBFS)
 
+################################################################################
+ifeq ($(CONFIG_QC_APDP_ENABLE),y)
+
+APDP_FILE := $(X1P42100_BLOB)/qtee/apdp.mbn
+APDP_CBFS := $(CONFIG_CBFS_PREFIX)/apdp
+$(APDP_CBFS)-file := $(APDP_FILE)
+$(APDP_CBFS)-type := payload
+$(APDP_CBFS)-compression := $(CBFS_COMPRESS_FLAG)
+cbfs-files-y += $(APDP_CBFS)
+
+################################################################################
+# Rule to create apdp_meta from apdp.mbn
+# This rule depends on apdp.mbn being built and the extractor script existing.
+$(obj)/mainboard/$(MAINBOARDDIR)/apdp_meta: $(X1P42100_BLOB)/qtee/apdp.mbn util/qualcomm/elf_segment_extractor.py
+	@echo "Extracting ELF headers and hash table segment from $< to $@"
+	@util/qualcomm/elf_segment_extractor.py --eh --pht --hashtable $< $@
+
+APDP_META_FILE := $(obj)/mainboard/$(MAINBOARDDIR)/apdp_meta
+APDP_META_CBFS := $(CONFIG_CBFS_PREFIX)/apdp_meta
+$(APDP_META_CBFS)-file := $(APDP_META_FILE)
+$(APDP_META_CBFS)-type := raw
+$(APDP_META_CBFS)-compression := $(CBFS_COMPRESS_FLAG)
+cbfs-files-y += $(APDP_META_CBFS)
+
+endif # ifeq ($(CONFIG_QC_APDP_ENABLE),y)
 endif # ifeq ($(CONFIG_USE_QC_BLOBS),y)
 
 endif # ifeq ($(CONFIG_QC_BLOBS_UPSTREAM),y)
diff --git a/src/soc/qualcomm/x1p42100/memlayout.ld b/src/soc/qualcomm/x1p42100/memlayout.ld
index 3cb7506668..afc38d3336 100644
--- a/src/soc/qualcomm/x1p42100/memlayout.ld
+++ b/src/soc/qualcomm/x1p42100/memlayout.ld
@@ -110,6 +110,8 @@
  *               |                       qclib                              |      |
  * 0x14897000    +----------------------------------------------------------+      |
  *               |                ... Usable memory ...                     |      |
+ * 0x14891000    +----------------------------------------------------------+      |
+ *               |                  apdp_ramdump_meta                       |      |
  * 0x14890000    +----------------------------------------------------------+      |
  *               |                    aop_blob_meta                         |      |
  * 0x1488C000    +----------------------------------------------------------+      |
@@ -207,6 +209,7 @@ SECTIONS
 	REGION(ddr_training, 0x14878000, 64K, 4K)
 	REGION(qc_blob_meta, 0x14888000, 16K, 4K)
 	REGION(aop_blob_meta, 0x1488c000, 16K, 4K)
+	REGION(apdp_ramdump_meta, 0x14890000, 4K, 4K)
 	REGION(qclib, 0x14897000, 1536K, 4K)
 	REGION(cpr_settings, 0x14A17000, 12K, 4K)
 	PRERAM_CBMEM_CONSOLE(0x14A30000, 32K)

From 445961c604afe8c0ad0dfad791f24bd30f65a2d0 Mon Sep 17 00:00:00 2001
From: Venkateshwar S <vens@qualcomm.corp-partner.google.com>
Date: Mon, 1 Dec 2025 04:07:16 -0800
Subject: [PATCH 2702/3886] soc/qualcomm/common: Add support for loading
 ramdump image

Ramdump is a debug image loaded during a crash to capture memory
contents for post-crash analysis. This patch adds support for
loading this image during the qclib_rerun() sequence.

Key changes:
1) Introduce QC_RAMDUMP_ENABLE Kconfig option to control ramdump image
   loading.
2) Add qclib_check_dload_mode() as a weak function that works in
   conjunction with the Kconfig check to decide whether the ramdump
   image should be loaded.
3) Add new CBFS file entry and table entry definition for ramdump_meta.
4) Re-use "apdp_ramdump_meta" region for ramdump metadata storage.

TEST=Create an image.serial.bin and ensure it boots on X1P42100.

Change-Id: I42bcd74c3d236a6af49ec4b548bc9cda33bd0825
Signed-off-by: Venkateshwar S <vens@qualcomm.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90306
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/soc/qualcomm/common/Kconfig               |  8 +++++
 .../common/include/soc/qclib_common.h         |  5 ++++
 src/soc/qualcomm/common/qclib.c               | 29 +++++++++++++++++++
 3 files changed, 42 insertions(+)

diff --git a/src/soc/qualcomm/common/Kconfig b/src/soc/qualcomm/common/Kconfig
index 9420087521..5d692779b0 100644
--- a/src/soc/qualcomm/common/Kconfig
+++ b/src/soc/qualcomm/common/Kconfig
@@ -33,4 +33,12 @@ config QC_APDP_ENABLE
 	  Application Processor Debug Policy (APDP) is a configuration image
 	  to define and enforce debugging capabilities and restrictions for APPS.
 
+config QC_RAMDUMP_ENABLE
+	bool
+	default n
+	prompt "Debug Build: enable Ramdump"
+	help
+	  Ramdump is a debug image that is loaded during a system crash to capture
+	  memory contents for post-crash analysis.
+
 endif
diff --git a/src/soc/qualcomm/common/include/soc/qclib_common.h b/src/soc/qualcomm/common/include/soc/qclib_common.h
index 572b479e90..ce5dd82bf3 100644
--- a/src/soc/qualcomm/common/include/soc/qclib_common.h
+++ b/src/soc/qualcomm/common/include/soc/qclib_common.h
@@ -3,6 +3,8 @@
 #ifndef _SOC_QUALCOMM_QCLIB_COMMON_H__
 #define _SOC_QUALCOMM_QCLIB_COMMON_H__
 
+#include <stdbool.h>
+
 /* coreboot & QCLib I/F definitions */
 
 /* string field lengths */
@@ -29,6 +31,7 @@
 #define QCLIB_TE_AOP_META_SETTINGS      "aop_metadata"
 #define QCLIB_TE_AOP_DEVCFG_META_SETTINGS	"aop_cfg_metadata"
 #define QCLIB_TE_APDP_META_SETTINGS	"apdp_metadata"
+#define QCLIB_TE_RAMDUMP_META_SETTINGS	"ramdump_metadata"
 
 /* BA_BMASK_VALUES (blob_attributes bit mask values) */
 #define QCLIB_BA_SAVE_TO_STORAGE 0x00000001
@@ -44,6 +47,7 @@ enum qclib_cbfs_file {
 	QCLIB_CBFS_AOP_META,
 	QCLIB_CBFS_AOP_DEVCFG_META,
 	QCLIB_CBFS_APDP_META,
+	QCLIB_CBFS_RAMDUMP_META,
 	QCLIB_CBFS_MAX
 };
 
@@ -82,6 +86,7 @@ void qclib_add_if_table_entry(const char *name, void *base,
 void qclib_load_and_run(void);
 void qclib_rerun(void);
 int  qclib_soc_override(struct qclib_cb_if_table *table);
+bool qclib_check_dload_mode(void);
 
 const char *qclib_file_default(enum qclib_cbfs_file file);
 const char *qclib_file(enum qclib_cbfs_file file);
diff --git a/src/soc/qualcomm/common/qclib.c b/src/soc/qualcomm/common/qclib.c
index cb33170ea1..41239d4b57 100644
--- a/src/soc/qualcomm/common/qclib.c
+++ b/src/soc/qualcomm/common/qclib.c
@@ -96,6 +96,8 @@ const char *qclib_file_default(enum qclib_cbfs_file file)
 		return CONFIG_CBFS_PREFIX "/aop_devcfg_meta";
 	case QCLIB_CBFS_APDP_META:
 		return CONFIG_CBFS_PREFIX "/apdp_meta";
+	case QCLIB_CBFS_RAMDUMP_META:
+		return CONFIG_CBFS_PREFIX "/ramdump_meta";
 	default:
 		die("unknown QcLib file %d", file);
 	}
@@ -186,6 +188,11 @@ static void dump_te_table(void)
 
 __weak int qclib_soc_override(struct qclib_cb_if_table *table) { return 0; }
 
+__weak bool qclib_check_dload_mode(void)
+{
+	return false;
+}
+
 static bool qclib_debug_log_level(void)
 {
 	return get_uint_option("qclib_debug_level", 1);
@@ -398,6 +405,28 @@ void qclib_rerun(void)
 
 	qclib_add_if_table_entry(QCLIB_TE_AOP_DEVCFG_META_SETTINGS, _aop_blob_meta, data_size, 0);
 
+	if (CONFIG(QC_RAMDUMP_ENABLE) && qclib_check_dload_mode()) {
+		struct prog ramdump_prog =
+				PROG_INIT(PROG_REFCODE, CONFIG_CBFS_PREFIX "/ramdump");
+
+		if (cbfs_prog_stage_load(&ramdump_prog))
+			die("SOC image: ramdump load failed");
+
+		/* Attempt to load ramdump_meta Blob. */
+		data_size = cbfs_load(qclib_file(QCLIB_CBFS_RAMDUMP_META),
+				_apdp_ramdump_meta, REGION_SIZE(apdp_ramdump_meta));
+		if (!data_size) {
+			printk(BIOS_ERR,
+			       "[%s] /ramdump_meta not loaded\n"
+			       "Ramdump will not be captured for crash analysis\n",
+			       __func__);
+
+			goto fail;
+		}
+
+		qclib_add_if_table_entry(QCLIB_TE_RAMDUMP_META_SETTINGS, _apdp_ramdump_meta, data_size, 0);
+	}
+
 	/* Set up the system and jump into QcLib */
 	printk(BIOS_DEBUG, "\n\n\nRe-enter QCLib to bring up AOP\n");
 	qclib_prepare_and_run();

From ed9239cd855e649208a48584edb701c930847c45 Mon Sep 17 00:00:00 2001
From: Yunlong Jia <yunlong.jia@ecs.corp-partner.google.com>
Date: Wed, 26 Nov 2025 08:44:16 +0000
Subject: [PATCH 2703/3886] mb/google/nissa/var/gothrax: Add Samsung parts to
 RAM ID table

Add the support RAM parts for gothrax.
Here is the ram part number list:
DRAM Part Name                 ID to assign
MT62F512M32D2DR-031 WT:B       0 (0000)
H58G56AK6BX069                 1 (0001)
K3LKBKB0BM-MGCP                2 (0010)
H9JCNNNBK3MLYR-N6E             0 (0000)
H9JCNNNCP3MLYR-N6E             3 (0011)
K3KL8L80CM-MGCT                4 (0100)

BUG=b:463859361
BRANCH=None
TEST=emerge-nissa coreboot

Change-Id: Ia43d300e63d22df27d5632d702a404a18442ea75
Signed-off-by: Yunlong Jia <yunlong.jia@ecs.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90239
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
---
 src/mainboard/google/brya/variants/gothrax/memory/Makefile.mk    | 1 +
 .../google/brya/variants/gothrax/memory/dram_id.generated.txt    | 1 +
 .../google/brya/variants/gothrax/memory/mem_parts_used.txt       | 1 +
 3 files changed, 3 insertions(+)

diff --git a/src/mainboard/google/brya/variants/gothrax/memory/Makefile.mk b/src/mainboard/google/brya/variants/gothrax/memory/Makefile.mk
index 96e2023b84..c323ea6ae6 100644
--- a/src/mainboard/google/brya/variants/gothrax/memory/Makefile.mk
+++ b/src/mainboard/google/brya/variants/gothrax/memory/Makefile.mk
@@ -8,3 +8,4 @@ SPD_SOURCES += spd/lp5/set-0/spd-1.hex      # ID = 0(0b0000)  Parts = MT62F512M3
 SPD_SOURCES += spd/lp5/set-0/spd-3.hex      # ID = 1(0b0001)  Parts = H58G56AK6BX069
 SPD_SOURCES += spd/lp5/set-0/spd-3.hex      # ID = 2(0b0010)  Parts = K3LKBKB0BM-MGCP
 SPD_SOURCES += spd/lp5/set-0/spd-2.hex      # ID = 3(0b0011)  Parts = H9JCNNNCP3MLYR-N6E
+SPD_SOURCES += spd/lp5/set-0/spd-7.hex      # ID = 4(0b0100)  Parts = K3KL8L80CM-MGCT
diff --git a/src/mainboard/google/brya/variants/gothrax/memory/dram_id.generated.txt b/src/mainboard/google/brya/variants/gothrax/memory/dram_id.generated.txt
index ee10ecfe49..8892ad8cb6 100644
--- a/src/mainboard/google/brya/variants/gothrax/memory/dram_id.generated.txt
+++ b/src/mainboard/google/brya/variants/gothrax/memory/dram_id.generated.txt
@@ -9,3 +9,4 @@ H58G56AK6BX069                 1 (0001)
 K3LKBKB0BM-MGCP                2 (0010)
 H9JCNNNBK3MLYR-N6E             0 (0000)
 H9JCNNNCP3MLYR-N6E             3 (0011)
+K3KL8L80CM-MGCT                4 (0100)
diff --git a/src/mainboard/google/brya/variants/gothrax/memory/mem_parts_used.txt b/src/mainboard/google/brya/variants/gothrax/memory/mem_parts_used.txt
index 5d050345ae..bb85c55f8b 100644
--- a/src/mainboard/google/brya/variants/gothrax/memory/mem_parts_used.txt
+++ b/src/mainboard/google/brya/variants/gothrax/memory/mem_parts_used.txt
@@ -15,3 +15,4 @@ H58G56AK6BX069,*1
 K3LKBKB0BM-MGCP,
 H9JCNNNBK3MLYR-N6E,
 H9JCNNNCP3MLYR-N6E,
+K3KL8L80CM-MGCT,

From 5b544c67eb8479d05a5d1cd788173f7963b42ade Mon Sep 17 00:00:00 2001
From: Wentao Qin <qinwentao@huaqin.corp-partner.google.com>
Date: Sun, 2 Nov 2025 21:47:42 +0800
Subject: [PATCH 2704/3886] mb/google/rauru: Add MIPI panel support with BOE
 NS130069-M00
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Add support for MIPI panel on Sapphire and enable NS130069-M00 as
the default panel. The panel uses TPS65132S as the bias IC, with supply
set to ±5.9V. Add TPS65132S initialization and power-on sequence are
configured according to the specification.

BUG=b:456907241, b:448281461
TEST=Check display initialization log and display are normal
BRANCH=none

Change-Id: I755b63725fe6243a45deff04e8b2fb10162d5f44
Signed-off-by: Xiaokun Qiao <qiaoxiaokun@huaqin.corp-partner.google.com>
Signed-off-by: Wentao Qin <qinwentao@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90008
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
---
 src/mainboard/google/rauru/Kconfig           |  1 +
 src/mainboard/google/rauru/Makefile.mk       |  3 ++
 src/mainboard/google/rauru/gpio.h            |  2 ++
 src/mainboard/google/rauru/panel.c           |  5 ++-
 src/mainboard/google/rauru/panel.h           | 16 +++++++++
 src/mainboard/google/rauru/panel_sapphire.c  | 36 +++++++++++++++++++
 src/mainboard/google/rauru/panel_tps65132s.c | 38 ++++++++++++++++++++
 src/soc/mediatek/mt8196/Makefile.mk          |  1 +
 8 files changed, 101 insertions(+), 1 deletion(-)
 create mode 100644 src/mainboard/google/rauru/panel_sapphire.c
 create mode 100644 src/mainboard/google/rauru/panel_tps65132s.c

diff --git a/src/mainboard/google/rauru/Kconfig b/src/mainboard/google/rauru/Kconfig
index 7acca4b9e5..fbf2efa3a2 100644
--- a/src/mainboard/google/rauru/Kconfig
+++ b/src/mainboard/google/rauru/Kconfig
@@ -38,6 +38,7 @@ config BOARD_SPECIFIC_OPTIONS
 	select FW_CONFIG
 	select FW_CONFIG_SOURCE_CHROMEEC_CBI
 	select RTC
+	select MIPI_PANEL_BOE_NS130069_M00 if BOARD_GOOGLE_SAPPHIRE
 
 config MAINBOARD_DIR
 	string
diff --git a/src/mainboard/google/rauru/Makefile.mk b/src/mainboard/google/rauru/Makefile.mk
index 64624a16a9..0d44451727 100644
--- a/src/mainboard/google/rauru/Makefile.mk
+++ b/src/mainboard/google/rauru/Makefile.mk
@@ -11,8 +11,11 @@ romstage-y += romstage.c
 ramstage-y += boardid.c
 ramstage-y += mainboard.c
 ramstage-y += panel.c
+ramstage-y += panel_tps65132s.c
 ramstage-y += regulator.c
 
+ramstage-$(CONFIG_BOARD_GOOGLE_SAPPHIRE) += panel_sapphire.c
+
 CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/include
 
 subdirs-y += variants/$(VARIANT_DIR)
diff --git a/src/mainboard/google/rauru/gpio.h b/src/mainboard/google/rauru/gpio.h
index ed7ec89123..5dace87ac8 100644
--- a/src/mainboard/google/rauru/gpio.h
+++ b/src/mainboard/google/rauru/gpio.h
@@ -47,6 +47,8 @@
 #define GPIO_AP_EDP_BKLTEN	GPIO(PERIPHERAL_EN4)
 #define GPIO_EN_PP3300_EDP_X	GPIO(PERIPHERAL_EN2)
 #define GPIO_EDP_HPD_1V8	GPIO(EINT13)
+#define GPIO_LCM_RST_1V8_L	GPIO(LCM_RST)
+#define GPIO_EN_PPVAR_MIPI_DISP	GPIO(EINT25)
 
 #define GPIO_I2SI4_BCK		GPIO(I2SIN1_BCK)
 #define GPIO_I2SI4_LRCK		GPIO(I2SIN1_LRCK)
diff --git a/src/mainboard/google/rauru/panel.c b/src/mainboard/google/rauru/panel.c
index 60afca61bb..beb979a009 100644
--- a/src/mainboard/google/rauru/panel.c
+++ b/src/mainboard/google/rauru/panel.c
@@ -9,7 +9,7 @@
 #include "gpio.h"
 #include "panel.h"
 
-static void configure_backlight(bool enable)
+void configure_backlight(bool enable)
 {
 	gpio_output(GPIO_AP_EDP_BKLTEN, enable);
 	gpio_output(GPIO_BL_PWM_1V8, enable);
@@ -47,6 +47,9 @@ __weak void fw_config_panel_override(struct panel_description *panel)
 
 struct panel_description *get_active_panel(void)
 {
+	if (CONFIG(BOARD_GOOGLE_SAPPHIRE))
+		return get_panel_description();
+
 	if (CONFIG(BOARD_GOOGLE_RAURU))
 		return &rauru_panel;
 
diff --git a/src/mainboard/google/rauru/panel.h b/src/mainboard/google/rauru/panel.h
index 9909cad06e..954a2e8405 100644
--- a/src/mainboard/google/rauru/panel.h
+++ b/src/mainboard/google/rauru/panel.h
@@ -3,8 +3,24 @@
 #ifndef __MAINBOARD_GOOGLE_RAURU_PANEL_H__
 #define __MAINBOARD_GOOGLE_RAURU_PANEL_H__
 
+#include <gpio.h>
 #include <soc/display.h>
+#include <soc/i2c.h>
+#include <soc/tps65132s.h>
+
+#define PMIC_TRS65132S_SLAVE	0x3e
+#define PMIC_I2C_BUS		I2C7
+
+struct tps65132s_config {
+	uint32_t i2c_bus;
+	gpio_t en;
+};
 
 uint32_t panel_id(void);
+void configure_backlight(bool enable);
+void tps65132s_power_on(struct tps65132s_cfg *config);
+
+/* Return the MIPI panel description */
+struct panel_description *get_panel_description(void);
 
 #endif /* __MAINBOARD_GOOGLE_RAURU_PANEL_H__ */
diff --git a/src/mainboard/google/rauru/panel_sapphire.c b/src/mainboard/google/rauru/panel_sapphire.c
new file mode 100644
index 0000000000..a832f7d6d1
--- /dev/null
+++ b/src/mainboard/google/rauru/panel_sapphire.c
@@ -0,0 +1,36 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <console/console.h>
+#include <soc/tps65132s.h>
+
+#include "gpio.h"
+#include "panel.h"
+
+static void mipi_panel_power_on(void)
+{
+	struct tps65132s_cfg config = {
+		.i2c_bus = PMIC_I2C_BUS,
+		.en = GPIO_EN_PP3300_EDP_X,
+		.sync = GPIO_EN_PPVAR_MIPI_DISP,
+	};
+	tps65132s_power_on(&config);
+}
+
+static struct panel_description sapphire_panels[] = {
+	[0x09] = {
+		.configure_backlight = configure_backlight,
+		.power_on = mipi_panel_power_on,
+		.name = "BOE_NS130069_M00",
+		.disp_path = DISP_PATH_DUAL_MIPI,
+		.orientation = LB_FB_ORIENTATION_NORMAL,
+	},
+};
+
+struct panel_description *get_panel_description(void)
+{
+	uint32_t id = panel_id();
+	if (id >= ARRAY_SIZE(sapphire_panels))
+		return NULL;
+
+	return &sapphire_panels[id];
+}
diff --git a/src/mainboard/google/rauru/panel_tps65132s.c b/src/mainboard/google/rauru/panel_tps65132s.c
new file mode 100644
index 0000000000..85677ea02d
--- /dev/null
+++ b/src/mainboard/google/rauru/panel_tps65132s.c
@@ -0,0 +1,38 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <console/console.h>
+#include <delay.h>
+#include <gpio.h>
+#include <soc/regulator.h>
+#include <soc/tps65132s.h>
+#include <soc/mt6363.h>
+
+#include "gpio.h"
+#include "panel.h"
+
+void tps65132s_power_on(struct tps65132s_cfg *config)
+{
+	const struct tps65132s_reg_setting reg_settings[] = {
+		{ PMIC_TPS65132_VPOS, 0x14, 0x1F },
+		{ PMIC_TPS65132_VNEG, 0x14, 0x1F },
+		{ PMIC_TPS65132_DLYX, 0x95, 0xFF },
+		{ PMIC_TPS65132_ASSDD, 0x5B, 0xFF },
+	};
+
+	mt6363_enable_vrf18(true);
+	config->settings = reg_settings;
+	config->setting_counts = ARRAY_SIZE(reg_settings);
+
+	mtk_i2c_bus_init(config->i2c_bus, I2C_SPEED_FAST);
+
+	if (tps65132s_setup(config) != CB_SUCCESS)
+		printk(BIOS_ERR, "Failed to set up tps65132s\n");
+
+	/* DISP_RST_1V8_L */
+	mdelay(10);
+	gpio_output(GPIO_LCM_RST_1V8_L, 1);
+	mdelay(10);
+	gpio_output(GPIO_LCM_RST_1V8_L, 0);
+	mdelay(10);
+	gpio_output(GPIO_LCM_RST_1V8_L, 1);
+}
diff --git a/src/soc/mediatek/mt8196/Makefile.mk b/src/soc/mediatek/mt8196/Makefile.mk
index a4926056aa..cc7ec0ad11 100644
--- a/src/soc/mediatek/mt8196/Makefile.mk
+++ b/src/soc/mediatek/mt8196/Makefile.mk
@@ -87,6 +87,7 @@ ramstage-y += ../common/pmif_clk.c pmif_clk.c
 ramstage-y += ../common/pmif.c pmif_init.c
 ramstage-y += ../common/pmif_spmi_v2.c pmif_spmi.c
 ramstage-y += ../common/rtc.c ../common/rtc_osc_init.c
+ramstage-y += ../common/tps65132s.c
 ramstage-y += ../common/usb.c usb.c
 
 BL31_MAKEARGS += PLAT=mt8196

From 8b3ceacd93f09447b53173f5b99527fc9249e60c Mon Sep 17 00:00:00 2001
From: Subrata Banik <subratabanik@google.com>
Date: Tue, 2 Dec 2025 13:18:47 +0000
Subject: [PATCH 2705/3886] ec/google: Check AC charger presence by reading
 host event register

The google_chromeec_is_charger_present function previously relied on
executing the EC_CMD_BATTERY_DYNAMIC_INFO command to check the
EC_BATT_FLAG_AC_PRESENT flag.

This commit refactors the function to directly read the host event
register (EC events B) and check for the EC_HOST_EVENT_AC_CONNECTED
event flag instead.

This approach is much more efficient as it avoids the overhead of
sending and receiving a full EC command (savings ~25-30ms), using a
readily available cached status instead.

TEST=Able to build and boot google/quenbi.

Change-Id: I2ec9aca5991394ed1d4998da37e074e9324bd672
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90334
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
---
 src/ec/google/chromeec/ec.c | 15 +++------------
 1 file changed, 3 insertions(+), 12 deletions(-)

diff --git a/src/ec/google/chromeec/ec.c b/src/ec/google/chromeec/ec.c
index b881fa47dc..03ae01c03d 100644
--- a/src/ec/google/chromeec/ec.c
+++ b/src/ec/google/chromeec/ec.c
@@ -1167,18 +1167,9 @@ bool google_chromeec_is_usb_pd_attached(void)
 /* This API checks if charger is present. */
 bool google_chromeec_is_charger_present(void)
 {
-	struct ec_params_battery_dynamic_info params = {
-		.index = 0,
-	};
-	struct ec_response_battery_dynamic_info resp;
-
-	if (ec_cmd_battery_get_dynamic(PLAT_EC, &params, &resp) == 0) {
-		/* Check if AC charger is present */
-		if (resp.flags & EC_BATT_FLAG_AC_PRESENT)
-			return true;
-	}
-
-	return false;
+	/* Check if the EC has posted the AC connect event. */
+	return !!(google_chromeec_get_events_b() &
+		  EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_CONNECTED));
 }
 
 /*

From 0599f3e1bd793caf053935a59cc9e5404c73ff5c Mon Sep 17 00:00:00 2001
From: Subrata Banik <subratabanik@google.com>
Date: Tue, 2 Dec 2025 13:19:53 +0000
Subject: [PATCH 2706/3886] mb/google/bluey: Condition slow charging enablement
 on charger presence

Update the logic to properly condition the slow battery charging feature.

Previously, enable_slow_battery_charging() was called solely if the
system was in a low-power boot state (is_low_power_boot()).

This commit adds an explicit check for
`google_chromeec_is_charger_present()` to ensure that the slow charging
feature is only enabled when a charger is physically connected.

TEST=Able to build and boot google/quenbi.

Change-Id: I24b6626343a25a4fab3f5d77c1d114e797781be7
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90335
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
---
 src/mainboard/google/bluey/mainboard.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/mainboard/google/bluey/mainboard.c b/src/mainboard/google/bluey/mainboard.c
index 07b50352c6..660a99f07a 100644
--- a/src/mainboard/google/bluey/mainboard.c
+++ b/src/mainboard/google/bluey/mainboard.c
@@ -59,8 +59,8 @@ void lb_add_boot_mode(struct lb_header *header)
 	mode->size = sizeof(*mode);
 	mode->boot_mode = get_boot_mode();
 
-	/* Enable charging only during off-mode or low-battery mode */
-	if (is_low_power_boot())
+	/* Enable charging only during off-mode or low-battery mode and charger present */
+	if (is_low_power_boot() && google_chromeec_is_charger_present())
 		enable_slow_battery_charging();
 }
 

From abe1ac07445ca31b55ae0d9e5488589328fe0212 Mon Sep 17 00:00:00 2001
From: John Su <john_su@compal.corp-partner.google.com>
Date: Fri, 28 Nov 2025 10:40:24 +0800
Subject: [PATCH 2707/3886] mb/google/brya/var/uldrenite: Add memory
 MT62F1G32D2DS-031RF WT:C

Add support for the new memory Micron MT62F1G32D2DS-031RF WT:C using
spd-3.hex.

DRAM Part Name                 ID to assign
H9JCNNNBK3MLYR-N6E             0 (0000)
K3KL6L60GM-MGCT                1 (0001)
K3KL8L80CM-MGCT                2 (0010)
MT62F1G32D2DS-026 WT:B         2 (0010)
H58G56CK8BX146                 3 (0011)
MT62F1G32D2DS-031RF WT:C       4 (0100)

BUG=b:459934066
BRANCH=firmware-trulo-15217.771.B
TEST=util/spd_tools/bin/part_id_gen ADL lp5 \
src/mainboard/google/brya/variants/uldrenite/memory \
src/mainboard/google/brya/variants/uldrenite/memory/mem_parts_used.txt

Change-Id: I76d8e1de2b96bd5f2cb319056d1f9307a7e2a114
Signed-off-by: John Su <john_su@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90255
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
---
 src/mainboard/google/brya/variants/uldrenite/memory/Makefile.mk  | 1 +
 .../google/brya/variants/uldrenite/memory/dram_id.generated.txt  | 1 +
 .../google/brya/variants/uldrenite/memory/mem_parts_used.txt     | 1 +
 3 files changed, 3 insertions(+)

diff --git a/src/mainboard/google/brya/variants/uldrenite/memory/Makefile.mk b/src/mainboard/google/brya/variants/uldrenite/memory/Makefile.mk
index 20c07f5f4a..36cd6aa962 100644
--- a/src/mainboard/google/brya/variants/uldrenite/memory/Makefile.mk
+++ b/src/mainboard/google/brya/variants/uldrenite/memory/Makefile.mk
@@ -8,3 +8,4 @@ SPD_SOURCES += spd/lp5/set-0/spd-1.hex      # ID = 0(0b0000)  Parts = H9JCNNNBK3
 SPD_SOURCES += spd/lp5/set-0/spd-9.hex      # ID = 1(0b0001)  Parts = K3KL6L60GM-MGCT
 SPD_SOURCES += spd/lp5/set-0/spd-7.hex      # ID = 2(0b0010)  Parts = K3KL8L80CM-MGCT, MT62F1G32D2DS-026 WT:B
 SPD_SOURCES += spd/lp5/set-0/spd-11.hex      # ID = 3(0b0011)  Parts = H58G56CK8BX146
+SPD_SOURCES += spd/lp5/set-0/spd-3.hex      # ID = 4(0b0100)  Parts = MT62F1G32D2DS-031RF WT:C
diff --git a/src/mainboard/google/brya/variants/uldrenite/memory/dram_id.generated.txt b/src/mainboard/google/brya/variants/uldrenite/memory/dram_id.generated.txt
index d1fe3d9e7c..9dd5abefe6 100644
--- a/src/mainboard/google/brya/variants/uldrenite/memory/dram_id.generated.txt
+++ b/src/mainboard/google/brya/variants/uldrenite/memory/dram_id.generated.txt
@@ -9,3 +9,4 @@ K3KL6L60GM-MGCT                1 (0001)
 K3KL8L80CM-MGCT                2 (0010)
 MT62F1G32D2DS-026 WT:B         2 (0010)
 H58G56CK8BX146                 3 (0011)
+MT62F1G32D2DS-031RF WT:C       4 (0100)
diff --git a/src/mainboard/google/brya/variants/uldrenite/memory/mem_parts_used.txt b/src/mainboard/google/brya/variants/uldrenite/memory/mem_parts_used.txt
index 3f143af738..fec92071e6 100644
--- a/src/mainboard/google/brya/variants/uldrenite/memory/mem_parts_used.txt
+++ b/src/mainboard/google/brya/variants/uldrenite/memory/mem_parts_used.txt
@@ -14,3 +14,4 @@ K3KL6L60GM-MGCT
 K3KL8L80CM-MGCT
 MT62F1G32D2DS-026 WT:B
 H58G56CK8BX146
+MT62F1G32D2DS-031RF WT:C

From 273a41c4d93c1c181e3c0c1d62a6a82752c04b73 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Micha=C5=82=20=C5=BBygowski?= <michal.zygowski@3mdeb.com>
Date: Mon, 6 Oct 2025 11:37:47 +0200
Subject: [PATCH 2708/3886] commonlib/memory_info: Introduce new fields to
 memory_info structure
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Some silcon initialization modules may provide more detailed
information about the DIMMs, like type details or voltages.

Extend the memory_info structure with type_detail and max/min
voltage. Use the new fields when producing SMBIOS tables if their
value is non-zero. Otherwise, keep previous behavior.

Change-Id: I01ae8ea1f5a8fec53e151c040d893376c3d23be2
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89483
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/commonlib/include/commonlib/memory_info.h | 23 +++++++++++++++++++
 src/lib/smbios.c                              | 14 +++++++----
 2 files changed, 32 insertions(+), 5 deletions(-)

diff --git a/src/commonlib/include/commonlib/memory_info.h b/src/commonlib/include/commonlib/memory_info.h
index 5465b1bccf..48b7158185 100644
--- a/src/commonlib/include/commonlib/memory_info.h
+++ b/src/commonlib/include/commonlib/memory_info.h
@@ -71,6 +71,27 @@ struct dimm_info {
 	 * e.g., SPD_RDIMM, SPD_SODIMM, SPD_MICRO_DIMM
 	 */
 	uint8_t mod_type;
+	/*
+	 * SMBIOS Type 17 Type Detail field:
+	 *
+	 * Bit 0 Reserved, set to 0
+	 * Bit 1 Other
+	 * Bit 2 Unknown
+	 * Bit 3 Fast-paged
+	 * Bit 4 Static column
+	 * Bit 5 Pseudo-static
+	 * Bit 6 RAMBUS
+	 * Bit 7 Synchronous
+	 * Bit 8 CMOS
+	 * Bit 9 EDO
+	 * Bit 10 Window DRAM
+	 * Bit 11 Cache DRAM
+	 * Bit 12 Non-volatile
+	 * Bit 13 Registered (Buffered)
+	 * Bit 14 Unbuffered (Unregistered)
+	 * Bit 15 LRDIMM
+	 */
+	uint16_t type_detail;
 	/*
 	 * SPD bus width.
 	 *
@@ -95,6 +116,8 @@ struct dimm_info {
 	 * Voltage Level
 	 */
 	uint16_t vdd_voltage;
+	uint16_t vdd_min_voltage;
+	uint16_t vdd_max_voltage;
 	/*
 	 * Max speed in MT/s
 	 * If the value is 0, ddr_frequency should be used instead.
diff --git a/src/lib/smbios.c b/src/lib/smbios.c
index 9cee637b69..7da3e2ad15 100644
--- a/src/lib/smbios.c
+++ b/src/lib/smbios.c
@@ -272,14 +272,18 @@ static int create_smbios_type17_for_dimm(struct dimm_info *dimm,
 
 	/* Voltage Levels */
 	t->configured_voltage = dimm->vdd_voltage;
-	t->minimum_voltage = dimm->vdd_voltage;
-	t->maximum_voltage = dimm->vdd_voltage;
+	t->minimum_voltage = dimm->vdd_min_voltage ? dimm->vdd_min_voltage : dimm->vdd_voltage;
+	t->maximum_voltage = dimm->vdd_max_voltage ? dimm->vdd_max_voltage : dimm->vdd_voltage;
 
 	/* Fill in type detail */
-	t->type_detail = info.type_detail;
+	if (dimm->type_detail != 0) {
+		t->type_detail = dimm->type_detail;
+	} else {
+		t->type_detail = info.type_detail;
+		/* Synchronous = 1 */
+		t->type_detail |= MEMORY_TYPE_DETAIL_SYNCHRONOUS;
+	}
 
-	/* Synchronous = 1 */
-	t->type_detail |= MEMORY_TYPE_DETAIL_SYNCHRONOUS;
 	/* no handle for error information */
 	t->memory_error_information_handle = 0xFFFE;
 	t->attributes = dimm->rank_per_dimm;

From 25c45012232e0d380d5f847d3942a15a4c05bfd8 Mon Sep 17 00:00:00 2001
From: Patrick Rudolph <patrick.rudolph@9elements.com>
Date: Fri, 5 Dec 2025 13:46:47 +0100
Subject: [PATCH 2709/3886] device/dram/ddr3: Fill in voltage fields for SMBIOS
 type 17

Parse the supported voltages from the DDR3 SPD and populate the
corresponding fields in CBMEM_ID_MEMINFO to make sure the SMBIOS
type 17 tables report the actual supported voltages of the DIMM.

Change-Id: I35af7c23f285af10b607a80eab7f4d9df664b3fd
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90395
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
---
 src/device/dram/ddr3.c                           | 16 ++++++++++++++++
 src/include/device/dram/ddr3.h                   |  4 ++++
 .../intel/sandybridge/raminit_common.h           |  2 +-
 3 files changed, 21 insertions(+), 1 deletion(-)

diff --git a/src/device/dram/ddr3.c b/src/device/dram/ddr3.c
index 30dbe83753..c99255ba5a 100644
--- a/src/device/dram/ddr3.c
+++ b/src/device/dram/ddr3.c
@@ -173,20 +173,29 @@ int spd_decode_ddr3(struct dimm_attr_ddr3_st *dimm, spd_ddr3_raw_data spd)
 
 	/* Module nominal voltage */
 	reg8 = spd[6];
+	dimm->min_voltage = UINT16_MAX;
+	dimm->max_voltage = 0;
+
 	printram("  Supported voltages :");
 	if (reg8 & (1 << 2)) {
 		dimm->flags.operable_1_25V = 1;
 		dimm->voltage = 1250;
+		dimm->max_voltage = MAX(dimm->voltage, dimm->max_voltage);
+		dimm->min_voltage = MIN(dimm->min_voltage, dimm->voltage);
 		printram(" 1.25V");
 	}
 	if (reg8 & (1 << 1)) {
 		dimm->flags.operable_1_35V = 1;
 		dimm->voltage = 1300;
+		dimm->max_voltage = MAX(dimm->voltage, dimm->max_voltage);
+		dimm->min_voltage = MIN(dimm->min_voltage, dimm->voltage);
 		printram(" 1.35V");
 	}
 	if (!(reg8 & (1 << 0))) {
 		dimm->flags.operable_1_50V = 1;
 		dimm->voltage = 1500;
+		dimm->max_voltage = MAX(dimm->voltage, dimm->max_voltage);
+		dimm->min_voltage = MIN(dimm->min_voltage, dimm->voltage);
 		printram(" 1.5V");
 	}
 	printram("\n");
@@ -454,6 +463,8 @@ int spd_xmp_decode_ddr3(struct dimm_attr_ddr3_st *dimm, spd_ddr3_raw_data spd,
 	dimm->voltage = (xmp[0] & 1) * 50;
 	dimm->voltage += ((xmp[0] >> 1) & 0xf) * 100;
 	dimm->voltage += ((xmp[0] >> 5) & 0x3) * 1000;
+	dimm->max_voltage = MAX(dimm->voltage, dimm->max_voltage);
+	dimm->min_voltage = MIN(dimm->min_voltage, dimm->voltage);
 
 	printram("  Requested voltage  : %u mV\n", dimm->voltage);
 
@@ -535,6 +546,9 @@ enum cb_err spd_add_smbios17(const u8 channel, const u8 slot, const u16 selected
 		dimm->channel_num = channel;
 		dimm->rank_per_dimm = info->ranks;
 		dimm->dimm_num = slot;
+		dimm->vdd_voltage = info->voltage;
+		dimm->vdd_min_voltage = info->min_voltage;
+		dimm->vdd_max_voltage = info->max_voltage;
 		memcpy(dimm->module_part_number, info->part_number, 16);
 		dimm->mod_id = info->manufacturer_id;
 		dimm->mod_type = info->dimm_type;
@@ -579,6 +593,8 @@ void dram_print_spd_ddr3(const struct dimm_attr_ddr3_st *dimm)
 	printk(BIOS_INFO, "  Column addr bits  : %u\n", dimm->col_bits);
 	printk(BIOS_INFO, "  Number of ranks   : %u\n", dimm->ranks);
 	printk(BIOS_INFO, "  DIMM Capacity     : %u MB\n", dimm->size_mb);
+	printk(BIOS_INFO, "  Vdd Min           : %u mV\n", dimm->min_voltage);
+	printk(BIOS_INFO, "  Vdd Max           : %u mV\n", dimm->max_voltage);
 
 	/* CAS Latencies Supported */
 	val16 = dimm->cas_supported;
diff --git a/src/include/device/dram/ddr3.h b/src/include/device/dram/ddr3.h
index 2f8766be8a..e752e0e060 100644
--- a/src/include/device/dram/ddr3.h
+++ b/src/include/device/dram/ddr3.h
@@ -138,6 +138,10 @@ struct dimm_attr_ddr3_st {
 	u8 reference_card;
 	/* XMP: Module voltage in mV */
 	u16 voltage;
+	/* Maximum voltage the DIMM supports in mV */
+	u16 max_voltage;
+	/* Minimum voltage the DIMM supports in mV */
+	u16 min_voltage;
 	/* XMP: max DIMMs per channel supported (1-4) */
 	u8 dimms_per_channel;
 	/* Manufacturer ID */
diff --git a/src/northbridge/intel/sandybridge/raminit_common.h b/src/northbridge/intel/sandybridge/raminit_common.h
index 202f67a78a..aa88a27616 100644
--- a/src/northbridge/intel/sandybridge/raminit_common.h
+++ b/src/northbridge/intel/sandybridge/raminit_common.h
@@ -305,7 +305,7 @@ void iosav_write_memory_test_sequence(ramctr_timing *ctrl, int channel, int slot
 /*
  * WARNING: Do not forget to increase MRC_CACHE_VERSION when the saved data is changed!
  */
-#define MRC_CACHE_VERSION 5
+#define MRC_CACHE_VERSION 6
 
 enum power_down_mode {
 	PDM_NONE        = 0,

From e6a8143d8b47a1f8bf490825f62ed7203835aec1 Mon Sep 17 00:00:00 2001
From: Cliff Huang <cliff.huang@intel.com>
Date: Tue, 16 Sep 2025 10:24:22 -0700
Subject: [PATCH 2710/3886] drivers/intel/touch: Add support for new Intel
 touch I2C _DSD entries
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

This update enhances the Intel touch driver by incorporating support for
newly added _DSD entries specific to I2C devices. The enhancements
include:

- Adding new entries in the I2C _DSD to enable configurations for
  maximum frame size and interrupt delay settings.
- Introducing device-specific interrupt delay settings tailored for
  Hynitron devices.

These changes ensure improved configurability and performance tuning for
supported devices. It is crucial to use this update with an operating
system that includes corresponding changes for this new support.

ATTENTION: This change requires a THC driver fix. If the OS does not
have the driver fix, please use LPSS I2C or disable the touchscreen
and touchpad. For instance, on the Google Fatcat board, use the
following CBI fw_config options:
TOUCHSCREEN field: TOUCHSCREEN_LPSS_I2C or TOUCHSCREEN_NONE
TOUCHPAD field: TOUCHPAD_LPSS_I2C or TOUCHPAD_NONE

BUG=none

Signed-off-by: Cliff Huang <cliff.huang@intel.com>
Change-Id: Iaab8329c97247161395d203a5efa92c053acb3a1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89214
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Reviewed-by: Kim, Kyoung Il <kyoung.il.kim@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/drivers/intel/touch/chip.h     |  4 ++++
 src/drivers/intel/touch/hynitron.h |  2 ++
 src/drivers/intel/touch/touch.c    | 23 +++++++++++++++++++++--
 3 files changed, 27 insertions(+), 2 deletions(-)

diff --git a/src/drivers/intel/touch/chip.h b/src/drivers/intel/touch/chip.h
index 69b58f83aa..83b5cd7d37 100644
--- a/src/drivers/intel/touch/chip.h
+++ b/src/drivers/intel/touch/chip.h
@@ -20,6 +20,10 @@ struct intel_thc_hidi2c_dev_info {
 	 * Otherwise, if not specified, use the speed setting from the platform.
 	 */
 	enum i2c_speed connection_speed;
+	/* Maximum Frame Size Value: FSVL; FSEN will be set if FSVL has non-zero value */
+	uint64_t max_frame_size_value;
+	/* Interrupt delay value: INDV; INDE will be set if INDV has non-zero value */
+	uint64_t interrupt_delay_value;
 };
 
 struct intel_thc_hidspi_dev_info {
diff --git a/src/drivers/intel/touch/hynitron.h b/src/drivers/intel/touch/hynitron.h
index 9932bbeb65..8ad065fe9b 100644
--- a/src/drivers/intel/touch/hynitron.h
+++ b/src/drivers/intel/touch/hynitron.h
@@ -13,6 +13,8 @@ static const struct drivers_intel_touch_config hynitron_touch_config = {
 		.intf.hidi2c.addr			= 0x2c,
 		.intf.hidi2c.descriptor_address		= 0x20,
 		.intf.hidi2c.connection_speed		= I2C_SPEED_FAST, /* fast mode */
+		.intf.hidi2c.interrupt_delay_value	= 4,	/* unit: 10 usec */
+		.intf.hidi2c.max_frame_size_value	= 50,	/* bytes */
 	},
 };
 
diff --git a/src/drivers/intel/touch/touch.c b/src/drivers/intel/touch/touch.c
index 5bca4173c6..85dd7f9159 100644
--- a/src/drivers/intel/touch/touch.c
+++ b/src/drivers/intel/touch/touch.c
@@ -237,7 +237,7 @@ static void touch_generate_acpi_i2cdev_dsd(const struct device *dev)
 	acpigen_write_name("ICRS");
 	acpigen_emit_byte(BUFFER_OP);
 	acpigen_write_len_f();
-	acpigen_write_integer(12); /* total size of ICRS + 1 */
+	acpigen_write_integer(2 + 8 + 1 + 1); /* total size of ICRS + 1 */
 	acpigen_pop_len(); /* Name */
 	acpigen_write_create_buffer_word_field("ICRS", 0x00, "DADR");
 	acpigen_write_create_buffer_qword_field("ICRS", 0x02, "DSPD");
@@ -246,7 +246,7 @@ static void touch_generate_acpi_i2cdev_dsd(const struct device *dev)
 	acpigen_write_name("ISUB");
 	acpigen_emit_byte(BUFFER_OP);
 	acpigen_write_len_f();
-	acpigen_write_integer(145); /* total size of ISUB + 1 */
+	acpigen_write_integer(22 * 8 + 1); /* total size of ISUB + 1 */
 	acpigen_pop_len();
 	acpigen_write_create_buffer_qword_field("ISUB", 0x00, "SMHX");
 	acpigen_write_create_buffer_qword_field("ISUB", 0x08, "SMLX");
@@ -266,6 +266,10 @@ static void touch_generate_acpi_i2cdev_dsd(const struct device *dev)
 	acpigen_write_create_buffer_qword_field("ISUB", 0x78, "HMTD");
 	acpigen_write_create_buffer_qword_field("ISUB", 0x80, "HMRD");
 	acpigen_write_create_buffer_qword_field("ISUB", 0x88, "HMSL");
+	acpigen_write_create_buffer_qword_field("ISUB", 0x90, "FSEN");
+	acpigen_write_create_buffer_qword_field("ISUB", 0x98, "FSVL");
+	acpigen_write_create_buffer_qword_field("ISUB", 0xa0, "INDE");
+	acpigen_write_create_buffer_qword_field("ISUB", 0xa8, "INDV");
 
 	acpigen_write_store_int_to_namestr(touch_get(dev, dev_hidi2c.intf.hidi2c.addr), "DADR");
 
@@ -305,6 +309,21 @@ static void touch_generate_acpi_i2cdev_dsd(const struct device *dev)
 	acpigen_write_store_int_to_namestr(touch_soc_get(dev, hidi2c, hm_sda_hold_rx_period), "HMRD");
 	acpigen_write_store_int_to_namestr(touch_soc_get(dev, hidi2c, suppressed_spikes_h_fp), "HMSL");
 
+	if (get_driver_config(dev)->dev_hidi2c.intf.hidi2c.max_frame_size_value) {
+		acpigen_write_store_int_to_namestr(1, "FSEN");
+		acpigen_write_store_int_to_namestr(touch_get(dev, dev_hidi2c.intf.hidi2c.max_frame_size_value), "FSVL");
+	} else {
+		acpigen_write_store_int_to_namestr(0, "FSEN");
+		acpigen_write_store_int_to_namestr(0, "FSVL");
+	}
+	if (get_driver_config(dev)->dev_hidi2c.intf.hidi2c.interrupt_delay_value) {
+		acpigen_write_store_int_to_namestr(1, "INDE");
+		acpigen_write_store_int_to_namestr(touch_get(dev, dev_hidi2c.intf.hidi2c.interrupt_delay_value), "INDV");
+	} else {
+		acpigen_write_store_int_to_namestr(0, "INDE");
+		acpigen_write_store_int_to_namestr(0, "INDV");
+	}
+
 	dsd_pkg_cnt = 4;
 	if (touch_get(dev, add_acpi_dma_property))
 		dsd_pkg_cnt += 2;

From 5a6addca4bcd7a439f925bf84e102ee64577d839 Mon Sep 17 00:00:00 2001
From: "luca.lai" <luca.lai@lcfc.corp-partner.google.com>
Date: Fri, 5 Dec 2025 19:08:26 +0800
Subject: [PATCH 2711/3886] mb/google/fatcat/var/ruby: Change GPIO pins to fix
 audio function

Change below GPIO pins status to fix audio function.
GPP_D10 : Native function 2
GPP_D11 : Native function 2
GPP_D12 : Native function 2
GPP_D13 : Native function 2

BUG=b:466263099
TEST=Build and boot to OS, check soundcard shows using command
'cat /proc/asound/cards' and check audio jack and amp are work.

Change-Id: Ieac732ebf5149a13fe7aba36bf14627ded4783ad
Signed-off-by: luca.lai <luca.lai@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90394
Reviewed-by: Derek Huang <derekhuang@google.com>
Reviewed-by: YH Lin <yueherngl@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/google/fatcat/variants/ruby/gpio.c | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/src/mainboard/google/fatcat/variants/ruby/gpio.c b/src/mainboard/google/fatcat/variants/ruby/gpio.c
index 43449b778f..b404a66082 100644
--- a/src/mainboard/google/fatcat/variants/ruby/gpio.c
+++ b/src/mainboard/google/fatcat/variants/ruby/gpio.c
@@ -160,13 +160,13 @@ static const struct pad_config gpio_table[] = {
 	/* GPP_D09:     I2S_MCLK1_OUT */
 	PAD_CFG_NF(GPP_D09, NONE, DEEP, NF2),
 	/* GPP_D10:     HDA_BCLK */
-	PAD_CFG_NF(GPP_D10, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_D10, NONE, DEEP, NF2),
 	/* GPP_D11:     HDA_SYNC */
-	PAD_CFG_NF(GPP_D11, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_D11, NONE, DEEP, NF2),
 	/* GPP_D12:     HDA_SDO */
-	PAD_CFG_NF(GPP_D12, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_D12, NONE, DEEP, NF2),
 	/* GPP_D13:     HDA_SDI0 */
-	PAD_CFG_NF(GPP_D13, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_D13, NONE, DEEP, NF2),
 	/* GPP_D14:     NC */
 	PAD_NC(GPP_D14, NONE),
 	/* GPP_D15:     NC */

From 26a18c674d0a01eac30f383ed6bc4162ce3ffa01 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Micha=C5=82=20=C5=BBygowski?= <michal.zygowski@3mdeb.com>
Date: Wed, 5 Nov 2025 14:13:30 +0100
Subject: [PATCH 2712/3886] acpi: Clear whole FACS table before filling it
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Running FWTS detected a problem with FACS having non-zero
values in reserved fields:

FAILED [MEDIUM] FACSReservedNonZero: Test 1, FACS Reserved field must be zero,
got 0x00fe7bcd instead
FAILED [HIGH] FACSReservedBitsNonZero: Test 1, FACS OSPM Flags Bits [31..1] must
be zero, got 0xf23bcdd8 instead
FAILED [LOW] FACSInvalidReserved1: Test 1, FACS: 2nd Reserved field is non-zero

Clear whole FACS table and then start filling the non-zero values to
fix the issue.

TEST=Run FWTS V25.01.00 on Gigabyte MZ33-AR1 and see no error for FACS
test.

Change-Id: I2af4caea155e3707e3b7832824e81e6b69f836a5
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89923
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/acpi/acpi.c | 7 +------
 1 file changed, 1 insertion(+), 6 deletions(-)

diff --git a/src/acpi/acpi.c b/src/acpi/acpi.c
index 7dad21f12d..b22c4bc2c0 100644
--- a/src/acpi/acpi.c
+++ b/src/acpi/acpi.c
@@ -936,14 +936,9 @@ static void acpi_create_facs(void *header)
 {
 	acpi_facs_t *facs = header;
 
+	memset(facs, 0, sizeof(acpi_facs_t));
 	memcpy(facs->signature, "FACS", 4);
 	facs->length = sizeof(acpi_facs_t);
-	facs->hardware_signature = 0;
-	facs->firmware_waking_vector = 0;
-	facs->global_lock = 0;
-	facs->flags = 0;
-	facs->x_firmware_waking_vector_l = 0;
-	facs->x_firmware_waking_vector_h = 0;
 	facs->version = get_acpi_table_revision(FACS);
 }
 

From 36edc2e371ce034e23f7daeb87f1962f60ea23be Mon Sep 17 00:00:00 2001
From: Venkateshwar S <vens@qualcomm.corp-partner.google.com>
Date: Mon, 1 Dec 2025 04:09:55 -0800
Subject: [PATCH 2713/3886] soc/qualcomm/x1p42100: Add Dload mode detection and
 ramdump packing

This patch adds support for download mode detection and packing of
ramdump image in CBFS.

Key changes:
1) qclib.c: Add qclib_check_dload_mode() to read TCSR register and
   detect download mode.
2) addressmap.h: Add TCSR_BOOT_MISC_DETECT register and download mode
   cookie definitions.
3) Makefile.mk: Add build rules for ramdump image.

TEST=Create an image.serial.bin and ensure it boots on X1P42100.

Change-Id: I7c6008be79ea0487273e060ac99ddf037111f6fa
Signed-off-by: Venkateshwar S <vens@qualcomm.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90307
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
---
 src/soc/qualcomm/x1p42100/Makefile.mk         | 26 +++++++++++++++++++
 .../x1p42100/include/soc/addressmap.h         | 11 ++++++++
 src/soc/qualcomm/x1p42100/qclib.c             | 18 +++++++++++++
 3 files changed, 55 insertions(+)

diff --git a/src/soc/qualcomm/x1p42100/Makefile.mk b/src/soc/qualcomm/x1p42100/Makefile.mk
index 787d0db78b..1fd7fb3d2e 100644
--- a/src/soc/qualcomm/x1p42100/Makefile.mk
+++ b/src/soc/qualcomm/x1p42100/Makefile.mk
@@ -320,6 +320,32 @@ $(APDP_META_CBFS)-compression := $(CBFS_COMPRESS_FLAG)
 cbfs-files-y += $(APDP_META_CBFS)
 
 endif # ifeq ($(CONFIG_QC_APDP_ENABLE),y)
+################################################################################
+ifeq ($(CONFIG_QC_RAMDUMP_ENABLE),y)
+
+RAMDUMP_FILE := $(X1P42100_BLOB)/boot/XblRamdump.elf
+RAMDUMP_CBFS := $(CONFIG_CBFS_PREFIX)/ramdump
+$(RAMDUMP_CBFS)-file := $(RAMDUMP_FILE)
+$(RAMDUMP_CBFS)-type := stage
+$(RAMDUMP_CBFS)-compression := $(CBFS_PRERAM_COMPRESS_FLAG)
+cbfs-files-y += $(RAMDUMP_CBFS)
+
+################################################################################
+# Rule to create ramdump_meta from XblRamdump.elf
+# This rule depends on XblRamdump.elf being built and the extractor script existing.
+$(obj)/mainboard/$(MAINBOARDDIR)/ramdump_meta: $(X1P42100_BLOB)/boot/XblRamdump.elf util/qualcomm/elf_segment_extractor.py
+	@echo "Extracting ELF headers and hash table segment from $< to $@"
+	@util/qualcomm/elf_segment_extractor.py --eh --pht --hashtable $< $@
+
+RAMDUMP_META_FILE := $(obj)/mainboard/$(MAINBOARDDIR)/ramdump_meta
+RAMDUMP_META_CBFS := $(CONFIG_CBFS_PREFIX)/ramdump_meta
+$(RAMDUMP_META_CBFS)-file := $(RAMDUMP_META_FILE)
+$(RAMDUMP_META_CBFS)-type := raw
+$(RAMDUMP_META_CBFS)-compression := $(CBFS_COMPRESS_FLAG)
+cbfs-files-y += $(RAMDUMP_META_CBFS)
+
+endif # ifeq ($(CONFIG_QC_RAMDUMP_ENABLE),y)
+
 endif # ifeq ($(CONFIG_USE_QC_BLOBS),y)
 
 endif # ifeq ($(CONFIG_QC_BLOBS_UPSTREAM),y)
diff --git a/src/soc/qualcomm/x1p42100/include/soc/addressmap.h b/src/soc/qualcomm/x1p42100/include/soc/addressmap.h
index 4df4cc99eb..11b6f794af 100644
--- a/src/soc/qualcomm/x1p42100/include/soc/addressmap.h
+++ b/src/soc/qualcomm/x1p42100/include/soc/addressmap.h
@@ -4,6 +4,7 @@
 #define _SOC_QUALCOMM_X1P42100_ADDRESS_MAP_H_
 
 #include <stdint.h>
+#include <types.h>
 
 #define AOSS_CC_BASE			0x0C2A0000
 #define QSPI_BASE			0x088DC000
@@ -176,6 +177,16 @@
 #define TCSR_GCC_USB2_2_CLKREF_EN_ADDR		((void *)0x1FD5118)
 #define USB_CLKREF_ENABLE_VALUE			0x1
 
+/* TCSR Boot Misc Detect Register for Download Mode */
+#define TCSR_BOOT_MISC_DETECT		0x1FD9000
+
+/* Bits 4 and 5 represent the ramdump download cookies in SoC logic */
+enum dload_mode_cookies {
+	DLOAD_FULL_DUMP = BIT(4),
+	DLOAD_MINI_DUMP = BIT(5),
+	DLOAD_BOTH = (DLOAD_FULL_DUMP | DLOAD_MINI_DUMP)
+};
+
 /* SPMI PMIC ARB */
 #define SPMI_PMIC_ARB_CORE_BASE		0x0C400000
 #define FIRST_APID_MAP_OFFSET		0x2000
diff --git a/src/soc/qualcomm/x1p42100/qclib.c b/src/soc/qualcomm/x1p42100/qclib.c
index ea1424c402..33de115dcf 100644
--- a/src/soc/qualcomm/x1p42100/qclib.c
+++ b/src/soc/qualcomm/x1p42100/qclib.c
@@ -6,6 +6,24 @@
 #include <soc/qclib_common.h>
 #include <device/mmio.h>
 #include <soc/symbols_common.h>
+#include <soc/addressmap.h>
+
+bool qclib_check_dload_mode(void)
+{
+	if (!CONFIG(QC_RAMDUMP_ENABLE))
+		return false;
+
+	uint32_t boot_misc_detect = read32((void *)TCSR_BOOT_MISC_DETECT);
+
+	if (boot_misc_detect & DLOAD_BOTH) {
+		printk(BIOS_DEBUG, "Download mode detected: 0x%x\n", boot_misc_detect);
+		return true;
+	}
+
+	printk(BIOS_DEBUG, "Download mode not enabled (TCSR value: 0x%x)\n",
+	       boot_misc_detect);
+	return false;
+}
 
 int qclib_soc_override(struct qclib_cb_if_table *table)
 {

From e3588d82bc3b037c1fade7d033f64f9dadcf6999 Mon Sep 17 00:00:00 2001
From: Ian Feng <ian_feng@compal.corp-partner.google.com>
Date: Fri, 5 Dec 2025 13:53:51 +0800
Subject: [PATCH 2714/3886] mb/google/ocelot/var/kodkod: Enable CNVi Wi-Fi and
 BT cores

Enable CNVi Wi-Fi and BT cores for kodkod.

BUG=b:466193315
TEST=Build and boot to OS in kodkod.
lspci -k : 00:14.3 :   iwlwifi
/vendor/bin/hw/hcitool.android-desktop cmd 4 9 :
Ok([14, 10, 1, 9, 16, 0, 242, 94, 138, 5, 241, 188])
/vendor/bin/hw/hcitool.android-desktop cmd 1 1 33 8B 9E 0A 00 :
Ok([15, 4, 0, 1, 1, 4])

Change-Id: I700bff4b38aa80c83859856282001ad9ad7df57c
Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90378
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Reviewed-by: Pranava Y N <pranavayn@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/google/ocelot/variants/kodkod/overridetree.cb | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/src/mainboard/google/ocelot/variants/kodkod/overridetree.cb b/src/mainboard/google/ocelot/variants/kodkod/overridetree.cb
index ceac680dcd..3426cb150e 100644
--- a/src/mainboard/google/ocelot/variants/kodkod/overridetree.cb
+++ b/src/mainboard/google/ocelot/variants/kodkod/overridetree.cb
@@ -30,6 +30,10 @@ chip soc/intel/pantherlake
 		[DDI_PORT_B] = DDI_ENABLE_HPD | DDI_ENABLE_DDC,
 	}"
 
+	# Enable CNVi Wi-Fi and Bluetooth
+	register "cnvi_wifi_core" = "true"
+	register "cnvi_bt_core" = "true"
+
 	register "serial_io_i2c_mode" = "{
 		[PchSerialIoIndexI2C0]  = PchSerialIoPci,
 		[PchSerialIoIndexI2C1]  = PchSerialIoPci,

From 94fe4c69266bf5bdc3e6cf7520863d307725f512 Mon Sep 17 00:00:00 2001
From: Ian Feng <ian_feng@compal.corp-partner.google.com>
Date: Fri, 5 Dec 2025 14:02:27 +0800
Subject: [PATCH 2715/3886] mb/google/ocelot/var/kodkod: Add wake configuration
 to cnvi_bluetooth

This commit adds wake functionality to the CNVi Bluetooth device by
registering to "GPE0_PME_B0" using the common CNVi block.

BUG=454341255
TEST=Able to wake up the device from a low power state using a keyboard
     Bluetooth device.

Change-Id: I5a0bbd0523611e8e38b62f8b3fdf77f736d3136f
Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90379
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Reviewed-by: Pranava Y N <pranavayn@google.com>
Reviewed-by: Upadhyay, Varun <varun.upadhyay@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/google/ocelot/variants/kodkod/overridetree.cb | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/src/mainboard/google/ocelot/variants/kodkod/overridetree.cb b/src/mainboard/google/ocelot/variants/kodkod/overridetree.cb
index 3426cb150e..264ff4db4c 100644
--- a/src/mainboard/google/ocelot/variants/kodkod/overridetree.cb
+++ b/src/mainboard/google/ocelot/variants/kodkod/overridetree.cb
@@ -215,6 +215,10 @@ chip soc/intel/pantherlake
 		end # CNVi
 
 		device ref cnvi_bluetooth on
+			chip soc/intel/common/block/cnvi
+				register "wake" = "GPE0_PME_B0"
+				device generic 0 on end
+			end
 		end
 
 		device ref i2c0 on

From 9a6d1d4d6928001373292055783fe1f79d85f737 Mon Sep 17 00:00:00 2001
From: "lai.kaiden" <lai.kaiden@inventec.corp-partner.google.com>
Date: Thu, 4 Dec 2025 10:43:05 +0800
Subject: [PATCH 2716/3886] mb/ocelot/var/ocicat: Modify ocicat Kconfig for
 bring up

Modify ocicat TPM_TIS_ACPI_INTERRUPT to fix TPM timeout

BUG=b:457879750
TEST=flash and boot to DUT, verify can boot to OS.

Change-Id: Ie6f35c8c68b8e5849a038124739f9ec4846f4aef
Signed-off-by: lai.kaiden <lai.kaiden@inventec.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90359
Reviewed-by: Pranava Y N <pranavayn@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/google/ocelot/Kconfig | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/mainboard/google/ocelot/Kconfig b/src/mainboard/google/ocelot/Kconfig
index dcada1fb6f..7b716de9b0 100644
--- a/src/mainboard/google/ocelot/Kconfig
+++ b/src/mainboard/google/ocelot/Kconfig
@@ -203,7 +203,7 @@ config TPM_TIS_ACPI_INTERRUPT
 	default 78 if BOARD_GOOGLE_MODEL_MATSU # GPE0_DW2_14 (GPP_E14)
 	default 49 if BOARD_GOOGLE_MODEL_OCELOT # GPE0_DW1_17 (GPP_B17)
 	default 49 if BOARD_GOOGLE_MODEL_OJAL # GPE0_DW1_17 (GPP_B17)
-	default 49 if BOARD_GOOGLE_MODEL_OCICAT # GPE0_DW1_17 (GPP_B17)
+	default 78 if BOARD_GOOGLE_MODEL_OCICAT # GPE0_DW2_14 (GPP_E14)
 
 config UART_FOR_CONSOLE
 	int

From 8e7975edfddc27c4807ab1d3fd2bbc178ecf4d90 Mon Sep 17 00:00:00 2001
From: Varun Upadhyay <varun.upadhyay@intel.com>
Date: Tue, 2 Dec 2025 09:06:56 +0530
Subject: [PATCH 2717/3886] mb/google/ocelot/var/ojal: enable CS42L43 driver
 options

This change adds Cirrus CS42L43 kconfig for enabling audio on ojal
variant according to schematics revision 0.9.
RDC kit no:840138

BUG=b:437459757
TEST=Build ojal variant.

Change-Id: I55b81ac5886a0b20ae049c1edd18f8d390ac51e1
Signed-off-by: Varun Upadhyay <varun.upadhyay@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90323
Reviewed-by: Bhat D, Krishna P <krishna.p.bhat.d@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/google/ocelot/Kconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/src/mainboard/google/ocelot/Kconfig b/src/mainboard/google/ocelot/Kconfig
index 7b716de9b0..8ea9de23f3 100644
--- a/src/mainboard/google/ocelot/Kconfig
+++ b/src/mainboard/google/ocelot/Kconfig
@@ -90,6 +90,7 @@ config BOARD_GOOGLE_MODEL_OJAL
 	select DRIVERS_GENERIC_BAYHUB_LV2
 	select DRIVERS_GENERIC_MAX98357A
 	select DRIVERS_INTEL_TOUCH
+	select DRIVERS_SOUNDWIRE_CS42L43
 	select FSP_UGOP_EARLY_SIGN_OF_LIFE
 	select EC_GOOGLE_CHROMEEC_RTK
 	select EC_GOOGLE_CHROMEEC_LPC_GENERIC_MEMORY_RANGE

From 980c2696437ecd58607ef399d57b2674545780aa Mon Sep 17 00:00:00 2001
From: Varun Upadhyay <varun.upadhyay@intel.com>
Date: Tue, 2 Dec 2025 13:34:25 +0530
Subject: [PATCH 2718/3886] mb/google/ocelot/var/ojal: Enable Audio Codec and
 update FW config

This patch enables Cirrus Audio codec and HDA in devicetree for ojal
and updates FW config for GPIO's according to schematics revision 0.9.
RDC kit no:840138

Scope (\_SB.PCI0.HDAS.SNDW)
    {
        Device (SW30)
        {
            Name (_ADR, 0x00033001FA424301)  // _ADR: Address
            Name (_DDN, "Headset Codec")  // _DDN: DOS Device Name
            Name (_SUB, "1337")  // _SUB: Subsystem ID
...

BUG=b:437459757
TEST=Build ojal board and check SSDT tables for codec.

Change-Id: Id4110263750ef5ff2375199d073175b47dc4f909
Signed-off-by: Varun Upadhyay <varun.upadhyay@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90331
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Bhat D, Krishna P <krishna.p.bhat.d@intel.com>
---
 .../google/ocelot/variants/ojal/fw_config.c   | 76 +++++++++++++++++++
 .../ocelot/variants/ojal/overridetree.cb      | 14 ++++
 2 files changed, 90 insertions(+)

diff --git a/src/mainboard/google/ocelot/variants/ojal/fw_config.c b/src/mainboard/google/ocelot/variants/ojal/fw_config.c
index 36bc5183a9..709723709f 100644
--- a/src/mainboard/google/ocelot/variants/ojal/fw_config.c
+++ b/src/mainboard/google/ocelot/variants/ojal/fw_config.c
@@ -11,6 +11,74 @@
 /* t: table */
 #define GPIO_CONFIGURE_PADS(t) gpio_configure_pads(t, ARRAY_SIZE(t))
 
+static const struct pad_config hda_enable_pads[] = {
+	/* GPP_D10:     HDA_BCLK (HDR) */
+	PAD_CFG_NF(GPP_D10, NONE, DEEP, NF1),
+	/* GPP_D11:     HDA_SYNC (HDR) */
+	PAD_CFG_NF(GPP_D11, NONE, DEEP, NF1),
+	/* GPP_D12:     HDA_SDO (HDR) */
+	PAD_CFG_NF(GPP_D12, NONE, DEEP, NF1),
+	/* GPP_D13:     HDA_SDI0 (HDR) */
+	PAD_CFG_NF(GPP_D13, NONE, DEEP, NF1),
+	/* GPP_D16:     HDA_RST_N (HDR) */
+	PAD_CFG_NF(GPP_D16, NONE, DEEP, NF1),
+	/* GPP_D17:     HDA_SDI1 (HDR) */
+	PAD_CFG_NF(GPP_D17, NONE, DEEP, NF1),
+	/* GPP_S04:     DMIC0_CLK (HDR) */
+	PAD_CFG_NF(GPP_S04, NONE, DEEP, NF5),
+	/* GPP_S05:     DMIC0_DATA (HDR) */
+	PAD_CFG_NF(GPP_S05, NONE, DEEP, NF5),
+	/* GPP_S06:     DMIC1_CLK (HDR) */
+	PAD_CFG_NF(GPP_S06, NONE, DEEP, NF5),
+	/* GPP_S07:     DMIC1_DATA (HDR) */
+	PAD_CFG_NF(GPP_S07, NONE, DEEP, NF5),
+};
+
+static const struct pad_config sndw_cs42l43_enable_pads[] = {
+	/* Soundwire GPIO Config */
+	/* GPP_S00:     SNDW3_CLK_CODEC (HDR) */
+	PAD_CFG_NF(GPP_S00, NONE, DEEP, NF1),
+	/* GPP_S01:     SNDW3_DATA0_CODEC (HDR) */
+	PAD_CFG_NF(GPP_S01, NONE, DEEP, NF1),
+	/* GPP_S02:     SNDW3_DATA1_CODEC (HDR) */
+	PAD_CFG_NF(GPP_S02, NONE, DEEP, NF1),
+	/* GPP_S04:     DMIC0_CLK (HDR) */
+	PAD_CFG_NF(GPP_S04, NONE, DEEP, NF5),
+	/* GPP_S05:     DMIC0_DATA (HDR) */
+	PAD_CFG_NF(GPP_S05, NONE, DEEP, NF5),
+};
+
+static const struct pad_config audio_disable_pads[] = {
+	/* GPP_D10:     HDA_BCLK (HDR) */
+	PAD_NC(GPP_D10, NONE),
+	/* GPP_D11:     HDA_SYNC (HDR) */
+	PAD_NC(GPP_D11, NONE),
+	/* GPP_D12:     HDA_SDO (HDR) */
+	PAD_NC(GPP_D12, NONE),
+	/* GPP_D13:     HDA_SDI0 (HDR) */
+	PAD_NC(GPP_D13, NONE),
+	/* GPP_D16:     HDA_RST_N (HDR) */
+	PAD_NC(GPP_D16, NONE),
+	/* GPP_D17:     HDA_SDI1 (HDR) */
+	PAD_NC(GPP_D17, NONE),
+	/* GPP_S00:     SNDW3_CLK_CODEC (HDR) */
+	PAD_NC(GPP_S00, NONE),
+	/* GPP_S01:     SNDW3_DATA0_CODEC (HDR) */
+	PAD_NC(GPP_S01, NONE),
+	/* GPP_S02:     SNDW3_DATA1_CODEC (HDR) */
+	PAD_NC(GPP_S02, NONE),
+	/* GPP_S03:     SNDW3_DATA2_CODEC (HDR) */
+	PAD_NC(GPP_S03, NONE),
+	/* GPP_S04:     DMIC0_CLK (HDR) */
+	PAD_NC(GPP_S04, NONE),
+	/* GPP_S05:     DMIC0_DATA (HDR) */
+	PAD_NC(GPP_S05, NONE),
+	/* GPP_S06:     DMIC1_CLK (HDR) */
+	PAD_NC(GPP_S06, NONE),
+	/* GPP_S07:     DMIC1_DATA (HDR) */
+	PAD_NC(GPP_S07, NONE),
+};
+
 static const struct pad_config pre_mem_gen4_ssd_pwr_pads[] = {
 	/* GPP_H18:     GEN4_SSD_PWREN */
 	PAD_CFG_GPO(GPP_H18, 0, PLTRST),
@@ -167,6 +235,14 @@ void fw_config_gpio_padbased_override(struct pad_config *padbased_table)
 		GPIO_PADBASED_OVERRIDE(padbased_table, ufs_enable_pads);
 	}
 
+	if (fw_config_probe(FW_CONFIG(AUDIO, AUDIO_NONE))) {
+		GPIO_PADBASED_OVERRIDE(padbased_table, audio_disable_pads);
+	} else if (fw_config_probe(FW_CONFIG(AUDIO, AUDIO_CS42L43_SNDW))) {
+		GPIO_PADBASED_OVERRIDE(padbased_table, sndw_cs42l43_enable_pads);
+	} else if (fw_config_probe(FW_CONFIG(AUDIO, AUDIO_ALC256_HDA))) {
+		GPIO_PADBASED_OVERRIDE(padbased_table, hda_enable_pads);
+	}
+
 	if (fw_config_probe(FW_CONFIG(WIFI, WIFI_CNVI_6)) ||
 		fw_config_probe(FW_CONFIG(WIFI, WIFI_CNVI_7))) {
 		GPIO_PADBASED_OVERRIDE(padbased_table, cnvi_enable_pads);
diff --git a/src/mainboard/google/ocelot/variants/ojal/overridetree.cb b/src/mainboard/google/ocelot/variants/ojal/overridetree.cb
index a8686cd986..adb8ece6a1 100644
--- a/src/mainboard/google/ocelot/variants/ojal/overridetree.cb
+++ b/src/mainboard/google/ocelot/variants/ojal/overridetree.cb
@@ -306,5 +306,19 @@ chip soc/intel/pantherlake
 		end
 
 		device ref smbus on end
+		device ref hda on
+			chip drivers/intel/soundwire
+				device generic 0 on
+					chip drivers/soundwire/cs42l43
+						# SoundWire Link 3 ID 1
+						register "desc" = ""Headset Codec""
+						register "sub" = ""1337""
+						device generic 3.1 on
+							probe AUDIO AUDIO_CS42L43_SNDW
+						end
+					end
+				end
+			end
+		end
 	end
 end

From d922ad79c6f6ed660a64a0544fa2d8a87ed5b1f4 Mon Sep 17 00:00:00 2001
From: Luca Lai <luca.lai@lcfc.corp-partner.google.com>
Date: Fri, 5 Dec 2025 09:26:28 +0800
Subject: [PATCH 2719/3886] mb/google/fatcat/var/ruby: Add firmware
 configuration fields with UFSC

Based on the Unified Firmware and Second Source Configuration(UFSC)
Developer's Guide to generate the UFSC firmware config file
ruby_ap_fw_config.cb and copy the content to overridetree.cb.

https://chromium.googlesource.com/chromiumos/config/+/refs/heads/main/
util/ufsc/ufsc_developer_guide.md

BUG=b:460231264
TEST=util/abuild/abuild -x -t GOOGLE_RUBY -a
BRANCH=none

Change-Id: Ia9536ba9b11ca83e80e7e6b3042a04fc6cdbf526
Signed-off-by: Luca Lai <luca.lai@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90375
Reviewed-by: Derek Huang <derekhuang@google.com>
Reviewed-by: YH Lin <yueherngl@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 .../fatcat/variants/ruby/overridetree.cb      | 32 +++++++++++++++++++
 1 file changed, 32 insertions(+)

diff --git a/src/mainboard/google/fatcat/variants/ruby/overridetree.cb b/src/mainboard/google/fatcat/variants/ruby/overridetree.cb
index 9cecdd7b05..8426b31cbc 100644
--- a/src/mainboard/google/fatcat/variants/ruby/overridetree.cb
+++ b/src/mainboard/google/fatcat/variants/ruby/overridetree.cb
@@ -7,6 +7,38 @@ fw_config
 		option AUDIO_AMPLIFIER_UNKNOWN	0
 		option AUDIO_AMPLIFIER_TAS2563	1
 	end
+	field CAMERA_UFC_NAME 6 8
+		option CAMERA_UFC_NAME_UNKNOWN	0
+		option CAMERA_UFC_NAME_BNN755UBP_21A	1
+		option CAMERA_UFC_NAME_HAA_N1H8D3	2
+		option CAMERA_UFC_NAME_CKFO518	3
+		option CAMERA_UFC_NAME_BBF503N3B	4
+	end
+	field STORAGE_TYPE 12 14
+		option STORAGE_TYPE_UNKNOWN	0
+		option STORAGE_TYPE_NVME_GEN4	1
+	end
+	field SENSOR_HUB 23 23
+		option ISH_ABSENT	0
+		option ISH_PRESENT	1
+	end
+	field FINGERPRINT_INTERFACE 24 25
+		option FINGERPRINT_INTERFACE_UNKNOWN	0
+		option FINGERPRINT_INTERFACE_SPI	1
+		option FINGERPRINT_INTERFACE_USB	2
+	end
+	field WIFI_INTERFACE 26 27
+		option WIFI_INTERFACE_UNKNOWN	0
+		option WIFI_INTERFACE_CNVI	1
+	end
+	field FORM_FACTOR 30 31
+		option FORM_FACTOR_UNKNOWN	0
+		option FORM_FACTOR_CLAMSHELL	1
+	end
+	field KB_BACKLIGHT 43 43
+		option KB_BACKLIGHT_ABSENT	0
+		option KB_BACKLIGHT_PRESENT	1
+	end
 end
 
 chip soc/intel/pantherlake

From ac5c57d24a30befe5eb772e09b22eac31ba177a1 Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Mon, 30 Sep 2024 21:22:13 +0100
Subject: [PATCH 2720/3886] drivers/tpm/ppi: Fix generated ACPI

The SSDT contains:
    CreateByteField (PPOP, Local0, TPPF)

However, CreateByteField requires the source argument to be
(Buffer | String | Integer).  PPOP is an OperationRegion, so
iasl correctly reports:

    Error 6058 - Invalid type ([Region] found)

Per ACPI spec, OperationRegions must use CreateField rather than
CreateByteField. Replace the AML emission with:

    CreateField (PPOP, Local0 * 8, 8, TPPF)

This reads one byte at an arbitrary offset inside the PPI
OpRegion and is fully standards-compliant. This isn't a
functional change, just "correct".

Test=boot starbook_mtl, verify iasl can decompile and recompile
SSDT and TPM is still operational.

Change-Id: If80bb5bf69562f8b904c1b315e95a0b5627efbc4
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84606
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
---
 src/drivers/tpm/ppi.c | 21 +++++++++++++++++----
 1 file changed, 17 insertions(+), 4 deletions(-)

diff --git a/src/drivers/tpm/ppi.c b/src/drivers/tpm/ppi.c
index 68923eaeda..0ddbfe5534 100644
--- a/src/drivers/tpm/ppi.c
+++ b/src/drivers/tpm/ppi.c
@@ -633,7 +633,10 @@ void tpm_ppi_acpi_fill_ssdt(const struct device *dev)
 	 */
 	acpigen_write_method_serialized("FUNC", 1);
 
+	/* Local0 = ToInteger(Arg0) */
 	acpigen_write_to_integer(ARG0_OP, LOCAL0_OP);
+
+	/* If (Local0 > 0x80) */
 	acpigen_write_if();
 	acpigen_emit_byte(LGREATER_OP);
 	acpigen_emit_byte(LOCAL0_OP);
@@ -641,17 +644,27 @@ void tpm_ppi_acpi_fill_ssdt(const struct device *dev)
 	acpigen_write_return_integer(0);
 	acpigen_pop_len(); /* If */
 
-	/* TPPF = CreateField("PPOP", Local0) */
-	acpigen_emit_byte(CREATE_BYTE_OP);
-	acpigen_emit_namestring("PPOP");
+	/* Local1 = (Local0 * 0x08) */
+	acpigen_emit_byte(MULTIPLY_OP);
 	acpigen_emit_byte(LOCAL0_OP);
+	acpigen_write_integer(8);
+	acpigen_emit_byte(LOCAL1_OP);
+
+	/* CreateField (PPOP, Local1, 0x08, TPPF) */
+	acpigen_emit_ext_op(CREATEFIELD_OP);
+	acpigen_emit_namestring("PPOP");
+	acpigen_emit_byte(LOCAL1_OP);
+	acpigen_write_integer(8);
+
+	/* Name of the dynamically-created field */
 	acpigen_emit_namestring("TPPF");
 
-	/* Local0 = ToInteger("TPPF") */
+	/* Local0 = ToInteger(TPPF) */
 	acpigen_emit_byte(TO_INTEGER_OP);
 	acpigen_emit_namestring("TPPF");
 	acpigen_emit_byte(LOCAL0_OP);
 
+	/* Return (Local0) */
 	acpigen_write_return_op(LOCAL0_OP);
 	acpigen_pop_len(); /* Method */
 

From 67a7e06c386970bdc9e6b5733a44d4844fb514e8 Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Sun, 30 Nov 2025 20:37:00 +0000
Subject: [PATCH 2721/3886] drivers/tpm: Remove duplicated op

Change-Id: I426b6c488fea57783168a68eb05d61e3821f6224
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90285
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
---
 src/drivers/tpm/ppi.c | 1 -
 1 file changed, 1 deletion(-)

diff --git a/src/drivers/tpm/ppi.c b/src/drivers/tpm/ppi.c
index 0ddbfe5534..7419b2842a 100644
--- a/src/drivers/tpm/ppi.c
+++ b/src/drivers/tpm/ppi.c
@@ -580,7 +580,6 @@ void tpm_ppi_acpi_fill_ssdt(const struct device *dev)
 	ppib->ppin = 1; // Not used by ACPI. Read by EDK-2, must be 1.
 	ppib->ppip = 0;
 	ppib->fret = 0;
-	ppib->next_step = 0;
 
 	bool found = false;
 	/* Fill in defaults, the TPM command executor may overwrite this list */

From aeee9450a2ff71593b39b5b7c4c79cad54ed5160 Mon Sep 17 00:00:00 2001
From: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Date: Mon, 1 Dec 2025 11:52:01 +0800
Subject: [PATCH 2722/3886] mb/google/ocelot/var/matsu: Add fw_config
 definitions with UFSC

Enable Unified Firmware and Secondary Source Configuration (UFSC)
support for Matsu.
UFSC standardizes the bitfields and bitmap definitions for firmware
configuration. Update overridetree.cb with new UFSC definitions and
enable EC_GOOGLE_CHROMEEC_FW_CONFIG_FROM_UFSC.

BUG=b:454549696,b:444322626
TEST=Ensure the probed fw_config matches the written configuration.
BRANCH=none

Change-Id: I55e2b9fd17290731f365632d92f1b26923c8022a
Signed-off-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90299
Reviewed-by: Bob Moragues <moragues@google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/google/ocelot/Kconfig           |  1 +
 .../google/ocelot/variants/matsu/Makefile.mk  |  4 ++
 .../google/ocelot/variants/matsu/fw_config.c  | 67 +++++++++++++++++++
 .../google/ocelot/variants/matsu/gpio.c       | 14 ----
 .../ocelot/variants/matsu/overridetree.cb     | 55 +++++++++++++--
 .../google/ocelot/variants/matsu/variant.c    | 13 ++++
 6 files changed, 136 insertions(+), 18 deletions(-)
 create mode 100644 src/mainboard/google/ocelot/variants/matsu/fw_config.c
 create mode 100644 src/mainboard/google/ocelot/variants/matsu/variant.c

diff --git a/src/mainboard/google/ocelot/Kconfig b/src/mainboard/google/ocelot/Kconfig
index 8ea9de23f3..1576db3671 100644
--- a/src/mainboard/google/ocelot/Kconfig
+++ b/src/mainboard/google/ocelot/Kconfig
@@ -110,6 +110,7 @@ config BOARD_GOOGLE_KODKOD
 
 config BOARD_GOOGLE_MATSU
 	select BOARD_GOOGLE_MODEL_MATSU
+	select EC_GOOGLE_CHROMEEC_FW_CONFIG_FROM_UFSC
 
 config BOARD_GOOGLE_OCELOT
 	select BOARD_GOOGLE_MODEL_OCELOT
diff --git a/src/mainboard/google/ocelot/variants/matsu/Makefile.mk b/src/mainboard/google/ocelot/variants/matsu/Makefile.mk
index 4c33dad4db..3fdd4642c0 100644
--- a/src/mainboard/google/ocelot/variants/matsu/Makefile.mk
+++ b/src/mainboard/google/ocelot/variants/matsu/Makefile.mk
@@ -3,4 +3,8 @@
 bootblock-y += gpio.c
 romstage-y += gpio.c
 romstage-y += memory.c
+romstage-$(CONFIG_FW_CONFIG) += fw_config.c
 ramstage-y += gpio.c
+romstage-$(CONFIG_FW_CONFIG) += variant.c
+ramstage-$(CONFIG_FW_CONFIG) += variant.c
+ramstage-$(CONFIG_FW_CONFIG) += fw_config.c
diff --git a/src/mainboard/google/ocelot/variants/matsu/fw_config.c b/src/mainboard/google/ocelot/variants/matsu/fw_config.c
new file mode 100644
index 0000000000..23c76888bd
--- /dev/null
+++ b/src/mainboard/google/ocelot/variants/matsu/fw_config.c
@@ -0,0 +1,67 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <baseboard/variants.h>
+#include <console/console.h>
+#include <fw_config.h>
+#include <gpio.h>
+#include <inttypes.h>
+
+/* t: base table; o: override table */
+#define GPIO_PADBASED_OVERRIDE(t, o) gpio_padbased_override(t, o, ARRAY_SIZE(o))
+/* t: table */
+#define GPIO_CONFIGURE_PADS(t) gpio_configure_pads(t, ARRAY_SIZE(t))
+
+/* Gen4 NVME: at the top M.2 slot */
+static const struct pad_config pre_mem_gen4_ssd_pwr_pads[] = {
+	/* GPP_H18:     GEN4_SSD_PWREN */
+	PAD_CFG_GPO(GPP_H18, 1, PLTRST),
+	/* GPP_A08:     M2_GEN4_SSD_RESET_N */
+	PAD_CFG_GPO(GPP_A08, 1, PLTRST),
+};
+
+static const struct pad_config gen4_ssd_pads[] = {
+	/* GPP_H18:     GEN4_SSD_PWREN */
+	PAD_CFG_GPO(GPP_H18, 1, PLTRST),
+	/* GPP_A08:     M2_GEN4_SSD_RESET_N */
+	PAD_CFG_GPO(GPP_A08, 1, PLTRST),
+	/* GPP_C12:     CLKREQ3_X4_GEN4_M2_SSD_N */
+	PAD_CFG_NF(GPP_C12, NONE, DEEP, NF1),
+};
+
+static const struct pad_config ufs_enable_pads[] = {
+	/* GPP_D21:     GPP_D21_UFS_REFCLK */
+	PAD_CFG_NF(GPP_D21, NONE, DEEP, NF1),
+	/* GPP_F09:     M2_UFS_RST_N */
+	PAD_CFG_GPO(GPP_F09, 1, DEEP),
+};
+
+void fw_config_configure_pre_mem_gpio(void)
+{
+	if (!fw_config_is_provisioned()) {
+		printk(BIOS_WARNING, "FW_CONFIG is not provisioned, Exiting\n");
+		return;
+	}
+
+	if (fw_config_probe(FW_CONFIG(STORAGE_TYPE, STORAGE_TYPE_NVME))) {
+		GPIO_CONFIGURE_PADS(pre_mem_gen4_ssd_pwr_pads);
+	} else if (fw_config_probe(FW_CONFIG(STORAGE_TYPE, STORAGE_TYPE_UNKNOWN))) {
+		GPIO_CONFIGURE_PADS(pre_mem_gen4_ssd_pwr_pads);
+	}
+}
+
+void fw_config_gpio_padbased_override(struct pad_config *padbased_table)
+{
+	if (!fw_config_is_provisioned()) {
+		printk(BIOS_WARNING, "FW_CONFIG is not provisioned, Exiting\n");
+		return;
+	}
+
+	if (fw_config_probe(FW_CONFIG(STORAGE_TYPE, STORAGE_TYPE_NVME))) {
+		GPIO_PADBASED_OVERRIDE(padbased_table, gen4_ssd_pads);
+	} else if (fw_config_probe(FW_CONFIG(STORAGE_TYPE, STORAGE_TYPE_UFS))) {
+		GPIO_PADBASED_OVERRIDE(padbased_table, ufs_enable_pads);
+	} else if (fw_config_probe(FW_CONFIG(STORAGE_TYPE, STORAGE_TYPE_UNKNOWN))) {
+		GPIO_PADBASED_OVERRIDE(padbased_table, gen4_ssd_pads);
+		GPIO_PADBASED_OVERRIDE(padbased_table, ufs_enable_pads);
+	}
+}
diff --git a/src/mainboard/google/ocelot/variants/matsu/gpio.c b/src/mainboard/google/ocelot/variants/matsu/gpio.c
index 7bca115efd..2455a48874 100644
--- a/src/mainboard/google/ocelot/variants/matsu/gpio.c
+++ b/src/mainboard/google/ocelot/variants/matsu/gpio.c
@@ -29,8 +29,6 @@ static const struct pad_config gpio_table[] = {
 	/* GPP_A06:     ESPI_RST_AIC_N */
 	/*  GPP_A06 : GPP_A06 ==> ESPI_RST_HDR configured on reset, do not touch */
 
-	/* GPP_A08:     M2_GEN4_SSD_RESET_N */
-	PAD_CFG_GPO(GPP_A08, 1, PLTRST),
 	/* GPP_A09:     NC */
 	PAD_NC(GPP_A09, NONE),
 	/* GPP_A10:     NC */
@@ -119,8 +117,6 @@ static const struct pad_config gpio_table[] = {
 	PAD_CFG_GPO(GPP_C10, 1, DEEP),
 	/* GPP_C11:     NC */
 	PAD_NC(GPP_C11, NONE),
-	/* GPP_C12:     CLKREQ3_X4_GEN4_M2_SSD_N */
-	PAD_CFG_NF(GPP_C12, NONE, DEEP, NF1),
 	/* GPP_C13:     NC */
 	PAD_NC(GPP_C13, NONE),
 	/* GPP_C14:     NC */
@@ -171,8 +167,6 @@ static const struct pad_config gpio_table[] = {
 	PAD_CFG_NF(GPP_D17, NONE, DEEP, NF3),
 	/* GPP_D19:     TCHSCR_RPT_EN */
 	PAD_CFG_GPO(GPP_D19, 0, PLTRST),
-	/* GPP_D21:     GPP_D21_UFS_REFCLK */
-	PAD_CFG_NF(GPP_D21, NONE, DEEP, NF1),
 
 	/* GPP_E */
 	/* GPP_E01:     NC */
@@ -237,8 +231,6 @@ static const struct pad_config gpio_table[] = {
 	PAD_NC(GPP_F07, NONE),
 	/* GPP_F08:     TCHSCR_PNL1_PWR_EN */
 	PAD_CFG_GPO(GPP_F08, 1, PLTRST),
-	/* GPP_F09:     M2_UFS_RST_N */
-	PAD_CFG_GPO(GPP_F09, 1, DEEP),
 	/* GPP_F10:     ISH_ACCEL_MB_INT_L*/
 	PAD_CFG_NF(GPP_F10, NONE, DEEP, NF8),
 	/* GPP_F11:     NC */
@@ -299,8 +291,6 @@ static const struct pad_config gpio_table[] = {
 	PAD_NC(GPP_H15, NONE),
 	/* GPP_H17:     NC */
 	PAD_NC(GPP_H17, NONE),
-	/* GPP_H18:     GEN4_SSD_PWREN */
-	PAD_CFG_GPO(GPP_H18, 1, DEEP),
 	/* GPP_H19:     NC */
 	PAD_NC(GPP_H19, NONE),
 	/* GPP_H20:     NC */
@@ -384,10 +374,6 @@ static const struct pad_config early_gpio_table[] = {
 
 /* Pad configuration in romstage */
 static const struct pad_config romstage_gpio_table[] = {
-	/* GPP_H18:     GEN4_SSD_PWREN */
-	PAD_CFG_GPO(GPP_H18, 1, PLTRST),
-	/* GPP_A08:     M2_GEN4_SSD_RESET_N */
-	PAD_CFG_GPO(GPP_A08, 1, PLTRST),
 };
 
 const struct pad_config *variant_gpio_table(size_t *num)
diff --git a/src/mainboard/google/ocelot/variants/matsu/overridetree.cb b/src/mainboard/google/ocelot/variants/matsu/overridetree.cb
index 299c2cccc0..59d6226735 100644
--- a/src/mainboard/google/ocelot/variants/matsu/overridetree.cb
+++ b/src/mainboard/google/ocelot/variants/matsu/overridetree.cb
@@ -1,3 +1,44 @@
+fw_config
+	field AUDIO_CODEC 0 2
+		option AUDIO_CODEC_UNKNOWN	0
+		option AUDIO_CODEC_ALC721	1
+	end
+	field STORAGE_TYPE 12 14
+		option STORAGE_TYPE_UNKNOWN	0
+		option STORAGE_TYPE_NVME	1
+		option STORAGE_TYPE_UFS	2
+	end
+	field SENSOR_HUB 23 23
+		option ISH_ABSENT	0
+		option ISH_PRESENT	1
+	end
+	field FINGERPRINT_INTERFACE 24 25
+		option FINGERPRINT_INTERFACE_UNKNOWN	0
+		option FINGERPRINT_INTERFACE_SPI	1
+		option FINGERPRINT_INTERFACE_USB	2
+	end
+	field WIFI_INTERFACE 26 27
+		option WIFI_INTERFACE_UNKNOWN	0
+		option WIFI_INTERFACE_CNVI	1
+	end
+	field FORM_FACTOR 30 31
+		option FORM_FACTOR_UNKNOWN	0
+		option FORM_FACTOR_CLAMSHELL	1
+		option FORM_FACTOR_CONVERTIBLE	2
+	end
+	field KB_BACKLIGHT 43 43
+		option KB_BACKLIGHT_ABSENT	0
+		option KB_BACKLIGHT_PRESENT	1
+	end
+	field KEYBOARD_LAYOUT 45 47
+		option KEYBOARD_LAYOUT_DEFAULT	0
+		option KEYBOARD_LAYOUT_CA_FR	1
+	end
+	field AP_OEM_2BIT_FIELD0 59 60
+		option IO_BOARD_USB2A2C_HDMI	0
+		option IO_BOARD_USB3C	1
+	end
+end
 chip soc/intel/pantherlake
 
 	register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Type C port - various configurations - TCP0
@@ -283,10 +324,14 @@ chip soc/intel/pantherlake
 				end
 			end
 		end
-		#ToDo: Probe using fw_config after decision.
-		device ref ufs on end
+		device ref ufs on
+			probe STORAGE_TYPE STORAGE_TYPE_UFS
+			probe STORAGE_TYPE STORAGE_TYPE_UNKNOWN
+		end
 		#ToDo: Probe using fw_config after decision.
 		device ref pcie_rp1 on
+			probe STORAGE_TYPE STORAGE_TYPE_NVME
+			probe STORAGE_TYPE STORAGE_TYPE_UNKNOWN
 			register "pcie_rp[PCIE_RP(1)]" = "{
 			.clk_src = 3,
 			.clk_req = 3,
@@ -369,8 +414,8 @@ chip soc/intel/pantherlake
 				device i2c 0x10 on end
 			end
 		end # I2C5
-		#ToDo: Probe using fw_config after decision.
 		device ref hda on
+			probe AUDIO_CODEC AUDIO_CODEC_ALC721
 			chip drivers/intel/soundwire
 				device generic 0 on
 					chip drivers/soundwire/alc711
@@ -380,7 +425,9 @@ chip soc/intel/pantherlake
 						register "alc711_address.part_id" = "MIPI_DEV_ID_REALTEK_ALC721"
 						register "disable_clkstop_sm_support" = "true"
 						# SoundWire Link 3 ID 1
-						device generic 3.1 on end
+						device generic 3.1 on
+							probe AUDIO_CODEC AUDIO_CODEC_ALC721
+						end
 					end
 				end
 			end
diff --git a/src/mainboard/google/ocelot/variants/matsu/variant.c b/src/mainboard/google/ocelot/variants/matsu/variant.c
new file mode 100644
index 0000000000..4868a76435
--- /dev/null
+++ b/src/mainboard/google/ocelot/variants/matsu/variant.c
@@ -0,0 +1,13 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <baseboard/variants.h>
+#include <ec/google/chromeec/ec.h>
+#include <fsp/api.h>
+#include <fw_config.h>
+#include <sar.h>
+#include <soc/gpio_soc_defs.h>
+
+const char *get_wifi_sar_cbfs_filename(void)
+{
+	return get_wifi_sar_fw_config_filename(FW_CONFIG_FIELD(WIFI_INTERFACE));
+}

From 3aaeca83780e85e41d79dd797d7e3c2b06ae5e0f Mon Sep 17 00:00:00 2001
From: Payne Lin <payne.lin@mediatek.corp-partner.google.com>
Date: Fri, 21 Nov 2025 15:08:04 +0800
Subject: [PATCH 2723/3886] soc/mediatek/common: Refactor mtk_dsi_dphy_timing

Refactor the MIPI DPHY implementation to improve modularity and
maintainability:
- Extract the dphy timing calculation to mtk_mipi_dphy_v1.c.
- Update Makefiles for multiple chips to include the new file.
- Enhance board-specific tuning by isolating timing configuration logic.

BUG=b:424782827
TEST=Build pass, boot ok, display ok

Change-Id: Ie0daa6e7b384a172ed483eda926e5acd1e3c539a
Signed-off-by: Payne Lin <payne.lin@mediatek.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90358
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/soc/mediatek/common/dsi_common.c          | 19 +-------------
 .../mediatek/common/include/soc/dsi_common.h  |  1 +
 src/soc/mediatek/common/mtk_mipi_dphy_v1.c    | 25 +++++++++++++++++++
 src/soc/mediatek/mt8173/Makefile.mk           |  1 +
 src/soc/mediatek/mt8183/Makefile.mk           |  1 +
 src/soc/mediatek/mt8186/Makefile.mk           |  1 +
 src/soc/mediatek/mt8188/Makefile.mk           |  1 +
 src/soc/mediatek/mt8189/Makefile.mk           |  1 +
 src/soc/mediatek/mt8192/Makefile.mk           |  1 +
 9 files changed, 33 insertions(+), 18 deletions(-)
 create mode 100644 src/soc/mediatek/common/mtk_mipi_dphy_v1.c

diff --git a/src/soc/mediatek/common/dsi_common.c b/src/soc/mediatek/common/dsi_common.c
index 027c748d0b..f9e7e2954b 100644
--- a/src/soc/mediatek/common/dsi_common.c
+++ b/src/soc/mediatek/common/dsi_common.c
@@ -76,24 +76,7 @@ static void mtk_dsi_dphy_timing(u32 data_rate, struct mtk_phy_timing *timing)
 	u32 timcon0, timcon1, timcon2, timcon3;
 	u32 data_rate_mhz = DIV_ROUND_UP(data_rate, MHz);
 
-	timing->lpx = (60 * data_rate_mhz / (8 * 1000)) + 1;
-	timing->da_hs_prepare = (80 * data_rate_mhz + 4 * 1000) / 8000;
-	timing->da_hs_zero = (170 * data_rate_mhz + 10 * 1000) / 8000 + 1 -
-			     timing->da_hs_prepare;
-	timing->da_hs_trail = timing->da_hs_prepare + 1;
-
-	timing->ta_go = 4 * timing->lpx - 2;
-	timing->ta_sure = timing->lpx + 2;
-	timing->ta_get = 4 * timing->lpx;
-	timing->da_hs_exit = 2 * timing->lpx + 1;
-
-	timing->da_hs_sync = 1;
-
-	timing->clk_hs_prepare = 70 * data_rate_mhz / (8 * 1000);
-	timing->clk_hs_post = timing->clk_hs_prepare + 8;
-	timing->clk_hs_trail = timing->clk_hs_prepare;
-	timing->clk_hs_zero = timing->clk_hs_trail * 4;
-	timing->clk_hs_exit = 2 * timing->clk_hs_trail;
+	mtk_dsi_dphy_timing_calculation(data_rate_mhz, timing);
 
 	/* Allow board-specific tuning. */
 	mtk_dsi_override_phy_timing(timing);
diff --git a/src/soc/mediatek/common/include/soc/dsi_common.h b/src/soc/mediatek/common/include/soc/dsi_common.h
index d741db0f1d..97161be45b 100644
--- a/src/soc/mediatek/common/include/soc/dsi_common.h
+++ b/src/soc/mediatek/common/include/soc/dsi_common.h
@@ -218,6 +218,7 @@ void mtk_dsi_cphy_vdo_timing(const u32 lanes, const struct edid *edid,
 			     s32 *hbp_byte, s32 *hfp_byte, u32 *hsync_active_byte);
 void mtk_dsi_cphy_disable_ck_mode(void);
 void mtk_dsi_dphy_disable_ck_mode(void);
+void mtk_dsi_dphy_timing_calculation(u32 data_rate_mhz, struct mtk_phy_timing *timing);
 void mtk_dsi_configure_mipi_tx(u32 data_rate, u32 lanes, bool is_cphy);
 int mtk_dsi_init(u32 mode_flags, u32 format, u32 lanes, const struct edid *edid,
 		 const u8 *init_commands);
diff --git a/src/soc/mediatek/common/mtk_mipi_dphy_v1.c b/src/soc/mediatek/common/mtk_mipi_dphy_v1.c
new file mode 100644
index 0000000000..65b21b064a
--- /dev/null
+++ b/src/soc/mediatek/common/mtk_mipi_dphy_v1.c
@@ -0,0 +1,25 @@
+/* SPDX-License-Identifier: GPL-2.0-only OR MIT */
+
+#include <device/mmio.h>
+#include <soc/dsi.h>
+
+void mtk_dsi_dphy_timing_calculation(u32 data_rate_mhz, struct mtk_phy_timing *timing)
+{
+	timing->lpx = (60 * data_rate_mhz / (8 * 1000)) + 1;
+	timing->da_hs_prepare = (80 * data_rate_mhz + 4 * 1000) / 8000;
+	timing->da_hs_zero = (170 * data_rate_mhz + 10 * 1000) / 8000 + 1 -
+			     timing->da_hs_prepare;
+	timing->da_hs_trail = timing->da_hs_prepare + 1;
+
+	timing->ta_go = 4 * timing->lpx - 2;
+	timing->ta_sure = timing->lpx + 2;
+	timing->ta_get = 4 * timing->lpx;
+	timing->da_hs_exit = 2 * timing->lpx + 1;
+	timing->da_hs_sync = 1;
+
+	timing->clk_hs_prepare = 70 * data_rate_mhz / (8 * 1000);
+	timing->clk_hs_post = timing->clk_hs_prepare + 8;
+	timing->clk_hs_trail = timing->clk_hs_prepare;
+	timing->clk_hs_zero = timing->clk_hs_trail * 4;
+	timing->clk_hs_exit = 2 * timing->clk_hs_trail;
+}
diff --git a/src/soc/mediatek/mt8173/Makefile.mk b/src/soc/mediatek/mt8173/Makefile.mk
index ef969ab24d..e149d9f6ac 100644
--- a/src/soc/mediatek/mt8173/Makefile.mk
+++ b/src/soc/mediatek/mt8173/Makefile.mk
@@ -72,6 +72,7 @@ ramstage-y += ../common/usb.c usb.c
 
 ramstage-y += ../common/ddp.c ddp.c
 ramstage-y += ../common/dsi_common.c dsi.c
+ramstage-y += ../common/mtk_mipi_dphy_v1.c
 
 BL31_MAKEARGS += PLAT=mt8173
 
diff --git a/src/soc/mediatek/mt8183/Makefile.mk b/src/soc/mediatek/mt8183/Makefile.mk
index 70f1b2a664..e1955d84c7 100644
--- a/src/soc/mediatek/mt8183/Makefile.mk
+++ b/src/soc/mediatek/mt8183/Makefile.mk
@@ -50,6 +50,7 @@ ramstage-y += emi.c
 ramstage-y += ../common/auxadc.c
 ramstage-y += ../common/ddp.c ddp.c
 ramstage-y += ../common/dsi_common.c ../common/dsi_v1.c ../common/mtk_mipi_dphy.c
+ramstage-y += ../common/mtk_mipi_dphy_v1.c
 ramstage-y += ../common/gpio_eint_v1.c ../common/gpio.c gpio.c
 ramstage-y += ../common/i2c.c i2c.c
 ramstage-y += ../common/mcu.c
diff --git a/src/soc/mediatek/mt8186/Makefile.mk b/src/soc/mediatek/mt8186/Makefile.mk
index f066b4bb3a..a956db51ce 100644
--- a/src/soc/mediatek/mt8186/Makefile.mk
+++ b/src/soc/mediatek/mt8186/Makefile.mk
@@ -41,6 +41,7 @@ ramstage-y += ../common/devapc.c devapc.c
 ramstage-y += ../common/dfd.c
 ramstage-y += ../common/display.c
 ramstage-y += ../common/dsi_common.c ../common/dsi_v1.c ../common/mtk_mipi_dphy.c
+ramstage-y += ../common/mtk_mipi_dphy_v1.c
 ramstage-y += ../common/emi.c
 ramstage-y += ../common/l2c_ops.c
 ramstage-y += ../common/mcu.c
diff --git a/src/soc/mediatek/mt8188/Makefile.mk b/src/soc/mediatek/mt8188/Makefile.mk
index 74ccbbdfac..5ae55587b9 100644
--- a/src/soc/mediatek/mt8188/Makefile.mk
+++ b/src/soc/mediatek/mt8188/Makefile.mk
@@ -46,6 +46,7 @@ ramstage-y += ../common/dpm.c
 ramstage-y += ../common/dpm_v1.c
 ramstage-$(CONFIG_DPM_FOUR_CHANNEL) += ../common/dpm_4ch.c
 ramstage-y += ../common/dsi_common.c ../common/dsi_v1.c ../common/mtk_mipi_dphy.c
+ramstage-y += ../common/mtk_mipi_dphy_v1.c
 ramstage-y += ../common/emi.c
 ramstage-y += ../common/l2c_ops.c
 ramstage-y += ../common/mcu.c
diff --git a/src/soc/mediatek/mt8189/Makefile.mk b/src/soc/mediatek/mt8189/Makefile.mk
index fe4c7d931b..8fda85b5d0 100644
--- a/src/soc/mediatek/mt8189/Makefile.mk
+++ b/src/soc/mediatek/mt8189/Makefile.mk
@@ -57,6 +57,7 @@ ramstage-y += ../common/mt6359p.c mt6359p.c
 ramstage-y += ../common/mtcmos.c mtcmos.c
 ramstage-y += ../common/mtk_fsp.c
 ramstage-y += ../common/mtk_mipi_cphy.c ../common/mtk_mipi_dphy.c
+ramstage-y += ../common/mtk_mipi_dphy_v1.c
 ramstage-y += ../common/pi_image.c
 ramstage-y += ../common/pmif.c ../common/pmif_clk.c ../common/pmif_init.c pmif_clk.c
 ramstage-y += ../common/pmif_spi.c pmif_spi.c
diff --git a/src/soc/mediatek/mt8192/Makefile.mk b/src/soc/mediatek/mt8192/Makefile.mk
index 8bbc8215b9..b60e8a7764 100644
--- a/src/soc/mediatek/mt8192/Makefile.mk
+++ b/src/soc/mediatek/mt8192/Makefile.mk
@@ -41,6 +41,7 @@ ramstage-y += ../common/dfd.c
 ramstage-y += ../common/dpm.c
 ramstage-y += ../common/dpm_v1.c
 ramstage-y += ../common/dsi_common.c ../common/dsi_v1.c ../common/mtk_mipi_dphy.c
+ramstage-y += ../common/mtk_mipi_dphy_v1.c
 ramstage-y += ../common/l2c_ops.c
 ramstage-y += ../common/mcu.c
 ramstage-y += ../common/mcupm.c

From 7e1aa974bfd74c6d03406b4c244df8b8b07b0ee7 Mon Sep 17 00:00:00 2001
From: Jarried Lin <jarried.lin@mediatek.corp-partner.google.com>
Date: Fri, 5 Dec 2025 11:32:26 +0800
Subject: [PATCH 2724/3886] soc/mediatek/common: Refactor mtk_ddp_mode_set to
 support dual DSI and DSC for MIPI

Add the dsc_config parameter to mtk_ddp_soc_mode_set to support DSC
configuration, and updated function calls to pass dsc_config from
panel_serializable_data. The MIPI_DSI_DUAL_CHANNEL flag is set when the
panel uses the dual MIPI path. This patch is prepared for upcoming MIPI
DSI and DSC changes.

BUG=b:424782827
TEST=Build pass.

Change-Id: Ia3ada4aca41a231adb2273c34deef636889c5c81
Signed-off-by: Jarried Lin <jarried.lin@mediatek.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90377
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
---
 src/soc/mediatek/common/display.c             | 21 ++++++++++++++++---
 src/soc/mediatek/common/include/soc/display.h |  5 +++--
 .../mediatek/common/include/soc/dsi_common.h  |  4 ++++
 src/soc/mediatek/mt8186/ddp.c                 |  3 ++-
 src/soc/mediatek/mt8188/ddp.c                 |  3 ++-
 src/soc/mediatek/mt8189/ddp.c                 |  3 ++-
 src/soc/mediatek/mt8195/ddp.c                 |  3 ++-
 src/soc/mediatek/mt8196/ddp.c                 |  3 ++-
 8 files changed, 35 insertions(+), 10 deletions(-)

diff --git a/src/soc/mediatek/common/display.c b/src/soc/mediatek/common/display.c
index 297fcc2fe8..afd74ee23a 100644
--- a/src/soc/mediatek/common/display.c
+++ b/src/soc/mediatek/common/display.c
@@ -99,6 +99,7 @@ int mtk_display_init(void)
 {
 	struct edid edid = {0};
 	struct mtk_dp mtk_edp = {0};
+	struct dsc_config *dsc_config_var = NULL;
 	struct fb_info *info;
 	const char *name;
 	struct panel_description *panel = get_active_panel();
@@ -125,6 +126,7 @@ int mtk_display_init(void)
 	process_panel_quirks(&mtk_edp, panel);
 
 	if (panel->disp_path == DISP_PATH_EDP) {
+		/* Currently eDP does not support DSC */
 		if (mtk_edp_init(&mtk_edp, &edid) < 0) {
 			printk(BIOS_ERR, "%s: Failed to initialize eDP\n", __func__);
 			return -1;
@@ -142,11 +144,23 @@ int mtk_display_init(void)
 			edid = mipi_data->edid;
 		}
 
+		dsc_config_var = &mipi_data->dsc_config;
 		u32 mipi_dsi_flags = (MIPI_DSI_MODE_VIDEO |
 				      MIPI_DSI_MODE_VIDEO_SYNC_PULSE |
 				      MIPI_DSI_MODE_LPM |
 				      MIPI_DSI_MODE_EOT_PACKET);
 
+		if (panel->disp_path == DISP_PATH_DUAL_MIPI) {
+			mipi_dsi_flags |= MIPI_DSI_DUAL_CHANNEL;
+			printk(BIOS_INFO, "%s: DSI dual mode\n", __func__);
+		}
+
+		if (dsc_config_var->dsc_version_major) {
+			mipi_dsi_flags |= MIPI_DSI_DSC_MODE;
+			printk(BIOS_INFO, "%s: DSC main version: %d\n", __func__,
+			       dsc_config_var->dsc_version_major);
+		}
+
 		if (mipi_data->flags & PANEL_FLAG_CPHY) {
 			mipi_dsi_flags |= MIPI_DSI_MODE_CPHY;
 			lanes = 3;
@@ -175,7 +189,7 @@ int mtk_display_init(void)
 
 	edid_set_framebuffer_bits_per_pixel(&edid, 32, 0);
 
-	mtk_ddp_mode_set(&edid, panel->disp_path);
+	mtk_ddp_mode_set(&edid, panel->disp_path, dsc_config_var);
 
 	if (panel->disp_path == DISP_PATH_EDP) {
 		if (mtk_edp_enable(&mtk_edp) < 0) {
@@ -200,7 +214,8 @@ int mtk_display_init(void)
 	return 0;
 }
 
-void mtk_ddp_mode_set(const struct edid *edid, enum disp_path_sel path)
+void mtk_ddp_mode_set(const struct edid *edid, enum disp_path_sel path,
+		      struct dsc_config *dsc_config)
 {
 	u32 fmt = OVL_INFMT_RGBA8888;
 	u32 bpp = edid->framebuffer_bits_per_pixel / 8;
@@ -222,5 +237,5 @@ void mtk_ddp_mode_set(const struct edid *edid, enum disp_path_sel path)
 		       vrefresh);
 	}
 
-	mtk_ddp_soc_mode_set(fmt, bpp, width, height, vrefresh, path);
+	mtk_ddp_soc_mode_set(fmt, bpp, width, height, vrefresh, path, dsc_config);
 }
diff --git a/src/soc/mediatek/common/include/soc/display.h b/src/soc/mediatek/common/include/soc/display.h
index 2551e0b5e5..ca8782280e 100644
--- a/src/soc/mediatek/common/include/soc/display.h
+++ b/src/soc/mediatek/common/include/soc/display.h
@@ -33,9 +33,10 @@ void mtk_display_disable_secure_mode(void);
 int mtk_display_init(void);
 
 void mtk_ddp_init(void);
-void mtk_ddp_mode_set(const struct edid *edid, enum disp_path_sel path);
 void mtk_ddp_soc_mode_set(u32 fmt, u32 bpp, u32 width, u32 height, u32 vrefresh,
-			  enum disp_path_sel path);
+			  enum disp_path_sel path, struct dsc_config *dsc_config);
+void mtk_ddp_mode_set(const struct edid *edid, enum disp_path_sel path,
+		      struct dsc_config *dsc_config);
 void mtk_ddp_ovlsys_start(uintptr_t fb_addr);
 
 #endif
diff --git a/src/soc/mediatek/common/include/soc/dsi_common.h b/src/soc/mediatek/common/include/soc/dsi_common.h
index 97161be45b..a21929809f 100644
--- a/src/soc/mediatek/common/include/soc/dsi_common.h
+++ b/src/soc/mediatek/common/include/soc/dsi_common.h
@@ -45,6 +45,10 @@ enum {
 	MIPI_DSI_MODE_LINE_END = BIT(12),
 	/* mipi is in CPHY mode */
 	MIPI_DSI_MODE_CPHY = BIT(13),
+	/* mipi is DSI Dual Channel mode */
+	MIPI_DSI_DUAL_CHANNEL = BIT(14),
+	/* mipi is DSC compression mode */
+	MIPI_DSI_DSC_MODE = BIT(15),
 };
 
 static struct dsi_regs *const dsi0 = (void *)DSI0_BASE;
diff --git a/src/soc/mediatek/mt8186/ddp.c b/src/soc/mediatek/mt8186/ddp.c
index 84593481b4..df796fcba4 100644
--- a/src/soc/mediatek/mt8186/ddp.c
+++ b/src/soc/mediatek/mt8186/ddp.c
@@ -9,6 +9,7 @@
 #include <edid.h>
 #include <soc/addressmap.h>
 #include <soc/ddp.h>
+#include <soc/display.h>
 
 static void disp_config_main_path_connection(void)
 {
@@ -142,7 +143,7 @@ void mtk_ddp_init(void)
 }
 
 void mtk_ddp_soc_mode_set(u32 fmt, u32 bpp, u32 width, u32 height, u32 vrefresh,
-			  enum disp_path_sel path)
+			  enum disp_path_sel path, struct dsc_config *dsc_config)
 {
 	main_disp_path_setup(width, height, vrefresh);
 	rdma_start();
diff --git a/src/soc/mediatek/mt8188/ddp.c b/src/soc/mediatek/mt8188/ddp.c
index e37915e35c..dfc0de3217 100644
--- a/src/soc/mediatek/mt8188/ddp.c
+++ b/src/soc/mediatek/mt8188/ddp.c
@@ -5,6 +5,7 @@
 #include <edid.h>
 #include <soc/addressmap.h>
 #include <soc/ddp.h>
+#include <soc/display.h>
 
 static void disp_config_main_path_connection(enum disp_path_sel path)
 {
@@ -146,7 +147,7 @@ void mtk_ddp_init(void)
 }
 
 void mtk_ddp_soc_mode_set(u32 fmt, u32 bpp, u32 width, u32 height, u32 vrefresh,
-			  enum disp_path_sel path)
+			  enum disp_path_sel path, struct dsc_config *dsc_config)
 {
 	main_disp_path_setup(width, height, vrefresh, path);
 	rdma_start();
diff --git a/src/soc/mediatek/mt8189/ddp.c b/src/soc/mediatek/mt8189/ddp.c
index 0fc82d8a27..6959fdbc1c 100644
--- a/src/soc/mediatek/mt8189/ddp.c
+++ b/src/soc/mediatek/mt8189/ddp.c
@@ -4,6 +4,7 @@
 #include <edid.h>
 #include <soc/addressmap.h>
 #include <soc/ddp.h>
+#include <soc/display.h>
 #include <device/mmio.h>
 
 static void disp_config_main_path_connection(enum disp_path_sel path)
@@ -138,7 +139,7 @@ void mtk_ddp_init(void)
 }
 
 void mtk_ddp_soc_mode_set(u32 fmt, u32 bpp, u32 width, u32 height, u32 vrefresh,
-			  enum disp_path_sel path)
+			  enum disp_path_sel path, struct dsc_config *dsc_config)
 {
 	main_disp_path_setup(width, height, vrefresh, path);
 	rdma_start();
diff --git a/src/soc/mediatek/mt8195/ddp.c b/src/soc/mediatek/mt8195/ddp.c
index 875b3103e5..28fc34b68d 100644
--- a/src/soc/mediatek/mt8195/ddp.c
+++ b/src/soc/mediatek/mt8195/ddp.c
@@ -5,6 +5,7 @@
 #include <edid.h>
 #include <soc/addressmap.h>
 #include <soc/ddp.h>
+#include <soc/display.h>
 
 #define MERGE_MODE	6
 #define MERGE_SWAP	0
@@ -151,7 +152,7 @@ void mtk_ddp_init(void)
 }
 
 void mtk_ddp_soc_mode_set(u32 fmt, u32 bpp, u32 width, u32 height, u32 vrefresh,
-			  enum disp_path_sel path)
+			  enum disp_path_sel path, struct dsc_config *dsc_config)
 {
 	main_disp_path_setup(width, height, vrefresh);
 	rdma_start();
diff --git a/src/soc/mediatek/mt8196/ddp.c b/src/soc/mediatek/mt8196/ddp.c
index cd7a50bd8b..380d52f171 100644
--- a/src/soc/mediatek/mt8196/ddp.c
+++ b/src/soc/mediatek/mt8196/ddp.c
@@ -6,6 +6,7 @@
 #include <edid.h>
 #include <soc/addressmap.h>
 #include <soc/ddp.h>
+#include <soc/display.h>
 
 #define SIZE(w, h) ((u32)(h) << 16 | (w))
 #define DUAL_PIPE(path) ((path) == DISP_PATH_DUAL_MIPI)
@@ -429,7 +430,7 @@ void mtk_ddp_init(void)
 }
 
 void mtk_ddp_soc_mode_set(u32 fmt, u32 bpp, u32 width, u32 height, u32 vrefresh,
-			  enum disp_path_sel path)
+			  enum disp_path_sel path, struct dsc_config *dsc_config)
 {
 	if (width > 0x1FFF || height > 0x1FFF)
 		printk(BIOS_WARNING, "%s: w/h: %d/%d exceed hw limit %u\n", __func__,

From 3053cd2dad10139879e2d171c0a6ebbf3bb6ff75 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Micha=C5=82=20=C5=BBygowski?= <michal.zygowski@3mdeb.com>
Date: Mon, 6 Oct 2025 12:09:46 +0200
Subject: [PATCH 2725/3886] soc/amd/common/acpi/lpc.asl: Report fixed base
 addresses
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

On systems with AMD ROM armor enabled the SPI base address register
in LPC bridge PCI device space is not accessible (returns all FFs).
In such case the AML code will not be able to retrieve the SPI BAR
and report it properly. Use fixed bases instead to avoid running
into this problem in the future.

Change-Id: Ia01508e5ddf2da053f9bf4116c5e05b89500f772
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89488
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/soc/amd/common/acpi/lpc.asl | 12 ++++--------
 1 file changed, 4 insertions(+), 8 deletions(-)

diff --git a/src/soc/amd/common/acpi/lpc.asl b/src/soc/amd/common/acpi/lpc.asl
index 254fc69793..d253c68140 100644
--- a/src/soc/amd/common/acpi/lpc.asl
+++ b/src/soc/amd/common/acpi/lpc.asl
@@ -1,5 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
+#include <soc/iomap.h>
+
 #if MAINBOARD_HAS_SPEAKER
 #define IO61_HID "PNP0800" /* AT style speaker */
 #else
@@ -14,10 +16,6 @@ Device(LPCB) {
 	*	DBGO("\\_SB\\PCI0\\LpcIsaBr\\_INI\n")
 	} */ /* End Method(_SB.SBRDG._INI) */
 
-	OperationRegion(CFG,PCI_Config,0x0,0x100) // Map PCI Configuration Space
-	Field(CFG,DWordAcc,NoLock,Preserve){
-		Offset(0xA0),
-		BAR,32}		// SPI Controller Base Address Register (Index 0xA0)
 
 	Device(LDRC)	// LPC device: Resource consumption
 	{
@@ -42,10 +40,8 @@ Device(LPCB) {
 		{
 			CreateDwordField(^CRS,^BAR0._BAS,SPIB)	// Field to hold SPI base address
 			CreateDwordField(^CRS,^BAR1._BAS,ESPB)	// Field to hold eSPI base address
-			Local0 = BAR & 0xffffff00
-			SPIB = Local0	// SPI base address mapped
-			Local1 = Local0 + 0x10000
-			ESPB = Local1	// eSPI base address mapped
+			SPIB = SPI_BASE_ADDRESS	// SPI base address mapped
+			ESPB = SPIB + 0x10000	// eSPI base address mapped
 			Return(CRS)
 		}
 	}

From 8929659d9365de8c9517f4787d3b71b0c8fbe691 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Micha=C5=82=20=C5=BBygowski?= <michal.zygowski@3mdeb.com>
Date: Mon, 6 Oct 2025 12:12:31 +0200
Subject: [PATCH 2726/3886] soc/amd/common/acpi/lpc.asl: Report ESPI1 fixed
 resource
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

There is ESPI1 fixed resource living 64K above the ESPI0 fixed
resource. Report it if the hardware has ESPI1 bus.

Change-Id: I7245850450cfa9de326f26c83c4f01c8d167f8be
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89489
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
---
 src/soc/amd/common/acpi/lpc.asl      | 11 +++++++++++
 src/soc/amd/common/block/lpc/Kconfig |  6 ++++++
 2 files changed, 17 insertions(+)

diff --git a/src/soc/amd/common/acpi/lpc.asl b/src/soc/amd/common/acpi/lpc.asl
index d253c68140..60f4eff696 100644
--- a/src/soc/amd/common/acpi/lpc.asl
+++ b/src/soc/amd/common/acpi/lpc.asl
@@ -34,6 +34,13 @@ Device(LPCB) {
 			0x00001000,			// Address Length
 			BAR1				// Descriptor Name
 			)
+#if CONFIG(SOC_AMD_COMMON_BLOCK_HAS_ESPI1)
+			Memory32Fixed(ReadWrite,	// Setup for fixed resource location for eSPI1 base address
+			0x00000000,			// Address Base
+			0x00001000,			// Address Length
+			BAR2
+			)
+#endif
 		})
 
 		Method(_CRS,0,Serialized)
@@ -42,6 +49,10 @@ Device(LPCB) {
 			CreateDwordField(^CRS,^BAR1._BAS,ESPB)	// Field to hold eSPI base address
 			SPIB = SPI_BASE_ADDRESS	// SPI base address mapped
 			ESPB = SPIB + 0x10000	// eSPI base address mapped
+#if CONFIG(SOC_AMD_COMMON_BLOCK_HAS_ESPI1)
+			CreateDwordField(^CRS,^BAR2._BAS,ESP1)	// Field to hold eSPI base address
+			ESP1 = ESPB + 0x10000	// eSPI base address mapped
+#endif
 			Return(CRS)
 		}
 	}
diff --git a/src/soc/amd/common/block/lpc/Kconfig b/src/soc/amd/common/block/lpc/Kconfig
index 9f41f22635..b78a6c5fda 100644
--- a/src/soc/amd/common/block/lpc/Kconfig
+++ b/src/soc/amd/common/block/lpc/Kconfig
@@ -58,6 +58,12 @@ config SOC_AMD_COMMON_BLOCK_USE_ESPI
 	  Select this option if mainboard uses eSPI instead of LPC (if supported
 	  by platform).
 
+config SOC_AMD_COMMON_BLOCK_HAS_ESPI1
+	bool
+	depends on SOC_AMD_COMMON_BLOCK_HAS_ESPI
+	help
+	  Select this option if SoC has eSPI1.
+
 config SOC_AMD_COMMON_BLOCK_ESPI_RETAIN_PORT80_EN
 	bool
 	depends on SOC_AMD_COMMON_BLOCK_USE_ESPI

From dcd4f071887f407d518ccf711f8d1c3fbe8a1820 Mon Sep 17 00:00:00 2001
From: Patrick Rudolph <patrick.rudolph@9elements.com>
Date: Fri, 5 Dec 2025 14:12:45 +0100
Subject: [PATCH 2727/3886] soc/amd/common/fsp: Fill in DIMM voltages

Fill in the DIMM voltages as reported by FSP.

Change-Id: I22d6bac93d8e8b8130f89a440be661829c700fe9
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90397
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
---
 src/soc/amd/common/fsp/dmi.c | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/src/soc/amd/common/fsp/dmi.c b/src/soc/amd/common/fsp/dmi.c
index fa630ff02e..289441a833 100644
--- a/src/soc/amd/common/fsp/dmi.c
+++ b/src/soc/amd/common/fsp/dmi.c
@@ -84,7 +84,10 @@ static void transfer_memory_info(const TYPE17_DMI_INFO *dmi17,
 
 	dimm->bank_locator = 0;
 
-	dimm->vdd_voltage = ddr_get_voltage(dmi17->MemoryType);
+	dimm->vdd_max_voltage = dmi17->MaximumVoltage;
+	dimm->vdd_min_voltage = dmi17->MinimumVoltage;
+	dimm->vdd_voltage = dmi17->ConfiguredVoltage ? dmi17->ConfiguredVoltage :
+			    ddr_get_voltage(dmi17->MemoryType);
 
 	strncpy((char *)dimm->module_part_number, dmi17->PartNumber,
 		sizeof(dimm->module_part_number) - 1);

From 87475d693a60972f11c466dcb73cc7727143db64 Mon Sep 17 00:00:00 2001
From: Maximilian Brune <maximilian.brune@9elements.com>
Date: Fri, 28 Nov 2025 16:25:52 +0100
Subject: [PATCH 2728/3886] soc/amd/glinda: Remove set_resets_to_cold

Glinda actually supports warm reset, so we don't need to toggle the
PwrGood for all resets.

Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: I70e9a13b84219847795e65b39c52114592a2cb61
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90415
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/soc/amd/glinda/Kconfig | 1 +
 src/soc/amd/glinda/fch.c   | 1 -
 2 files changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/soc/amd/glinda/Kconfig b/src/soc/amd/glinda/Kconfig
index 5cd7e7d1dc..77008a9345 100644
--- a/src/soc/amd/glinda/Kconfig
+++ b/src/soc/amd/glinda/Kconfig
@@ -92,6 +92,7 @@ config SOC_AMD_GLINDA
 	select X86_AMD_FIXED_MTRRS
 	select X86_INIT_NEED_1_SIPI
 	select HAVE_X86_64_SUPPORT
+	select SOC_AMD_SUPPORTS_WARM_RESET
 	help
 	  AMD Glinda support
 
diff --git a/src/soc/amd/glinda/fch.c b/src/soc/amd/glinda/fch.c
index 2ec54a101f..849e466442 100644
--- a/src/soc/amd/glinda/fch.c
+++ b/src/soc/amd/glinda/fch.c
@@ -156,7 +156,6 @@ static void cgpll_clock_gate_init(void)
 
 void fch_init(void *chip_info)
 {
-	set_resets_to_cold();
 	i2c_soc_init();
 	fch_init_acpi_ports();
 

From 9e5c7eb3f8751377afafcfc31380fde91947ca0d Mon Sep 17 00:00:00 2001
From: Patrick Rudolph <patrick.rudolph@9elements.com>
Date: Fri, 25 Jul 2025 10:14:08 +0200
Subject: [PATCH 2729/3886] soc/amd/glinda: Add XGBE devices

Some specific Glinda SoCs support dual 10G PCI ethernet devices.
Add defines and chipset entries for XGBE0 and XGBE1.

Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: I7e3bb1819165a7c2f4284b76450f831bb99b1ad3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90416
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/soc/amd/glinda/chipset.cb             | 2 ++
 src/soc/amd/glinda/include/soc/pci_devs.h | 8 ++++++++
 2 files changed, 10 insertions(+)

diff --git a/src/soc/amd/glinda/chipset.cb b/src/soc/amd/glinda/chipset.cb
index 853e05250f..e72cfb971b 100644
--- a/src/soc/amd/glinda/chipset.cb
+++ b/src/soc/amd/glinda/chipset.cb
@@ -60,6 +60,8 @@ chip soc/amd/glinda
 			ops amd_internal_pcie_gpp_ops
 			device pci 0.0 on end # dummy, do not disable
 			device pci 0.1 alias npu off end # Neural Processing Unit (NPU)
+			device pci 0.2 alias xgbe_0 off end # 10 GbE Controller Port 0 (XGBE0)
+			device pci 0.3 alias xgbe_1 off end # 10 GbE Controller Port 1 (XGBE1)
 		end
 
 		device pci 08.3 alias gpp_bridge_c on # Internal GPP Bridge 2 to Bus C
diff --git a/src/soc/amd/glinda/include/soc/pci_devs.h b/src/soc/amd/glinda/include/soc/pci_devs.h
index e85a6e3372..222addb00c 100644
--- a/src/soc/amd/glinda/include/soc/pci_devs.h
+++ b/src/soc/amd/glinda/include/soc/pci_devs.h
@@ -81,6 +81,14 @@
 #define PCIE_GPP_B_DEVFN	PCI_DEVFN(PCIE_ABC_BRIDGE_DEV, PCIE_ABC_B_FUNC)
 #define SOC_PCIE_GPP_B_DEV	_SOC_DEV(PCIE_ABC_BRIDGE_DEV, PCIE_ABC_B_FUNC)
 
+#define XGBE0_DEV		0x0
+#define XGBE0_FUNC		2
+#define XGBE0_DEVFN		PCI_DEVFN(XGBE0_DEV, XGBE0_FUNC)
+
+#define XGBE1_DEV		0x0
+#define XGBE1_FUNC		3
+#define XGBE1_DEVFN		PCI_DEVFN(XGBE1_DEV, XGBE1_FUNC)
+
 #define PCIE_ABC_C_FUNC		3
 #define PCIE_ABC_C_DEVFN	PCI_DEVFN(PCIE_ABC_BRIDGE_DEV, PCIE_ABC_C_FUNC)
 #define SOC_PCIE_GPP_C_DEV	_SOC_DEV(PCIE_ABC_BRIDGE_DEV, PCIE_ABC_C_FUNC)

From 244e8edf182a611fe65061e6bb4b9a4df70db9cd Mon Sep 17 00:00:00 2001
From: Patrick Rudolph <patrick.rudolph@9elements.com>
Date: Thu, 24 Jul 2025 11:22:24 +0200
Subject: [PATCH 2730/3886] soc/amd/glinda/Kconfig: Add Faegan SoC as Glinda
 variant

Glinda and Faegan are closely related and there's only very minimal
difference from the coreboot viewpoint, so Feagan is added as Glianda
variant and not as a new SoC folder. Faegan has a different CPUID, so
it's added to the CPU table, and some GPIO muxes have a few more valid
settings to route the MDIO pins related to the 2 XGBE controllers to
GPIO pins.

Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: I57699089a4a3ac7ddb037f254d42cb043b816c55
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90417
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/soc/amd/glinda/Kconfig            | 18 ++++++++--
 src/soc/amd/glinda/Makefile.mk        |  4 +--
 src/soc/amd/glinda/cpu.c              |  1 +
 src/soc/amd/glinda/include/soc/cpu.h  |  6 ++--
 src/soc/amd/glinda/include/soc/gpio.h | 48 +++++++++++++++++++++++++++
 5 files changed, 70 insertions(+), 7 deletions(-)

diff --git a/src/soc/amd/glinda/Kconfig b/src/soc/amd/glinda/Kconfig
index 77008a9345..3be4725763 100644
--- a/src/soc/amd/glinda/Kconfig
+++ b/src/soc/amd/glinda/Kconfig
@@ -3,7 +3,7 @@
 # TODO: Evaluate what can be moved to a common directory
 # TODO: Update for Glinda
 
-config SOC_AMD_GLINDA
+config SOC_AMD_GLINDA_BASE
 	bool
 	select ACPI_SOC_NVS
 	select ARCH_X86
@@ -96,7 +96,19 @@ config SOC_AMD_GLINDA
 	help
 	  AMD Glinda support
 
-if SOC_AMD_GLINDA
+config SOC_AMD_GLINDA
+	bool
+	select SOC_AMD_GLINDA_BASE
+	help
+	  AMD Glinda support
+
+config SOC_AMD_FAEGAN
+	bool
+	select SOC_AMD_GLINDA_BASE
+	help
+	  AMD Faegan support
+
+if SOC_AMD_GLINDA_BASE
 
 config CHIPSET_DEVICETREE
 	string
@@ -451,4 +463,4 @@ config RWB_REGION_ONLY
 
 endif # VBOOT_SLOTS_RW_AB && VBOOT_STARTS_BEFORE_BOOTBLOCK
 
-endif # SOC_AMD_GLINDA
+endif # SOC_AMD_GLINDA_BASE
diff --git a/src/soc/amd/glinda/Makefile.mk b/src/soc/amd/glinda/Makefile.mk
index e0ce02c666..1a71769701 100644
--- a/src/soc/amd/glinda/Makefile.mk
+++ b/src/soc/amd/glinda/Makefile.mk
@@ -3,7 +3,7 @@
 # TODO: Move as much as possible to common
 # TODO: Update for Glinda
 
-ifeq ($(CONFIG_SOC_AMD_GLINDA),y)
+ifeq ($(CONFIG_SOC_AMD_GLINDA_BASE),y)
 
 subdirs-$(CONFIG_VBOOT_STARTS_BEFORE_BOOTBLOCK) += psp_verstage
 
@@ -315,4 +315,4 @@ build_complete:: $(obj)/amdfw_a.rom $(obj)/amdfw_b.rom
 endif # CONFIG_SEPARATE_SIGNED_PSPFW
 endif
 
-endif # ($(CONFIG_SOC_AMD_GLINDA),y)
+endif # ($(CONFIG_SOC_AMD_GLINDA_BASE),y)
diff --git a/src/soc/amd/glinda/cpu.c b/src/soc/amd/glinda/cpu.c
index 2dcc3c5d21..d414afee4c 100644
--- a/src/soc/amd/glinda/cpu.c
+++ b/src/soc/amd/glinda/cpu.c
@@ -17,6 +17,7 @@ static struct device_operations cpu_dev_ops = {
 static struct cpu_device_id cpu_table[] = {
 	{ X86_VENDOR_AMD, GLINDA_A0_CPUID, CPUID_ALL_STEPPINGS_MASK },
 	{ X86_VENDOR_AMD, GLINDA_B0_CPUID, CPUID_ALL_STEPPINGS_MASK },
+	{ X86_VENDOR_AMD, FAEGAN_A0_CPUID, CPUID_ALL_STEPPINGS_MASK },
 	CPU_TABLE_END
 };
 
diff --git a/src/soc/amd/glinda/include/soc/cpu.h b/src/soc/amd/glinda/include/soc/cpu.h
index 834b1f94e7..0845cac5cc 100644
--- a/src/soc/amd/glinda/include/soc/cpu.h
+++ b/src/soc/amd/glinda/include/soc/cpu.h
@@ -3,6 +3,8 @@
 #ifndef AMD_GLINDA_CPU_H
 #define AMD_GLINDA_CPU_H
 
-#define GLINDA_A0_CPUID	CPUID_FROM_FMS(0x1a, 0x20, 0)
-#define GLINDA_B0_CPUID	CPUID_FROM_FMS(0x1a, 0x24, 0)
+#define GLINDA_A0_CPUID	CPUID_FROM_FMS(0x1a, 0x20, 0x0)
+#define GLINDA_B0_CPUID	CPUID_FROM_FMS(0x1a, 0x24, 0x0)
+#define FAEGAN_A0_CPUID	CPUID_FROM_FMS(0x1a, 0x68, 0x0)
+
 #endif /* AMD_GLINDA_CPU_H */
diff --git a/src/soc/amd/glinda/include/soc/gpio.h b/src/soc/amd/glinda/include/soc/gpio.h
index 3104889476..7a3a3fcee1 100644
--- a/src/soc/amd/glinda/include/soc/gpio.h
+++ b/src/soc/amd/glinda/include/soc/gpio.h
@@ -115,18 +115,27 @@
 #define GPIO_4_IOMUX_GPIOxx 0
 #define GPIO_5_IOMUX_GPIOxx 0
 #define GPIO_6_IOMUX_GPIOxx 0
+#if CONFIG(SOC_AMD_FAEGAN)
+#define GPIO_6_IOMUX_MDIO0_SCL 2
+#endif
 #define GPIO_7_IOMUX_GPIOxx 0
 #define GPIO_7_IOMUX_ZST_STUTTER_RAIL 1
 #define GPIO_8_IOMUX_GPIOxx 0
 #define GPIO_8_IOMUX_TMU_CLK_OUT0 1
 #define GPIO_8_IOMUX_TMU_CLK_OUT1 2
 #define GPIO_9_IOMUX_GPIOxx 0
+#if CONFIG(SOC_AMD_FAEGAN)
+#define GPIO_9_IOMUX_MDIO2_SCL 2
+#endif
 #define GPIO_10_IOMUX_GPIOxx 0
 #define GPIO_10_IOMUX_S0A3_GPIO 1
 /* GPIO 10 IOMUX == 2 is also GPIOxx */
 #define GPIO_10_IOMUX_DF_VRCONTEXT_0 3
 #define GPIO_11_IOMUX_GPIOxx 0
 #define GPIO_11_IOMUX_BLINK 1
+#if CONFIG(SOC_AMD_FAEGAN)
+#define GPIO_11_IOMUX_MDIO3_SDA 2
+#endif
 #define GPIO_12_IOMUX_LLB_L 0
 #define GPIO_12_IOMUX_GPIOxx 1
 #define GPIO_16_IOMUX_USB_OC0_L 0
@@ -152,6 +161,9 @@
 #define GPIO_22_IOMUX_SD0_CMD 3
 #define GPIO_23_IOMUX_AC_PRES 0
 #define GPIO_23_IOMUX_GPIOxx 1
+#if CONFIG(SOC_AMD_FAEGAN)
+#define GPIO_23_IOMUX_MDIO2_SDA 2
+#endif
 #define GPIO_24_IOMUX_USB_OC3_L 0
 #define GPIO_24_IOMUX_GPIOxx 1
 #define GPIO_26_IOMUX_PCIE_RST0_L 0
@@ -169,11 +181,23 @@
 #define GPIO_31_IOMUX_SPI2_CS3_L 3
 #define GPIO_32_IOMUX_GPIOxx 0
 #define GPIO_32_IOMUX_LPC_RST_L 1
+#if CONFIG(SOC_AMD_FAEGAN)
+#define GPIO_32_IOMUX_MDIO3_SCL 2
+#endif
 #define GPIO_38_IOMUX_CLK_REQ5_L 0
 #define GPIO_38_IOMUX_GPIOxx 1
+#if CONFIG(SOC_AMD_FAEGAN)
+#define GPIO_38_IOMUX_MDIO1_SDA 2
+#endif
 #define GPIO_39_IOMUX_CLK_REQ6_L 0
 #define GPIO_39_IOMUX_GPIOxx 1
+#if CONFIG(SOC_AMD_FAEGAN)
+#define GPIO_39_IOMUX_MDIO1_SCL 2
+#endif
 #define GPIO_40_IOMUX_GPIOxx 0
+#if CONFIG(SOC_AMD_FAEGAN)
+#define GPIO_40_IOMUX_MDIO0_SDA 2
+#endif
 #define GPIO_42_IOMUX_GPIOxx 0
 #define GPIO_42_IOMUX_DF_VRCONTEXT_1 1
 #define GPIO_67_IOMUX_SPI_ROM_REQ 0
@@ -257,13 +281,22 @@
 #define GPIO_135_IOMUX_UART3_TXD 2
 #define GPIO_136_IOMUX_GPIOxx 0
 #define GPIO_136_IOMUX_UART2_RXD 1
+#if CONFIG(SOC_AMD_FAEGAN)
+#define GPIO_136_IOMUX_XGBE_LED0 2
+#endif
 #define GPIO_137_IOMUX_GPIOxx 0
 #define GPIO_137_IOMUX_UART2_RTS_L 1
 #define GPIO_137_IOMUX_UART3_RXD 2
 #define GPIO_138_IOMUX_GPIOxx 0
 #define GPIO_138_IOMUX_UART2_TXD 1
+#if CONFIG(SOC_AMD_FAEGAN)
+#define GPIO_138_IOMUX_XGBE_LED1 2
+#endif
 #define GPIO_139_IOMUX_GPIOxx 0
 #define GPIO_139_IOMUX_UART2_INTR 1
+#if CONFIG(SOC_AMD_FAEGAN)
+#define GPIO_139_IOMUX_XGBE_LED2 2
+#endif
 #define GPIO_140_IOMUX_GPIOxx 0
 #define GPIO_140_IOMUX_UART0_CTS_L 1
 #define GPIO_140_IOMUX_UART1_TXD 2
@@ -291,13 +324,28 @@
 #define GPIO_148_IOMUX_GPIOxx 2
 #define GPIO_153_IOMUX_GPIOxx 0
 #define GPIO_153_IOMUX_UART4_CTS_L 1
+#if CONFIG(SOC_AMD_FAEGAN)
+#define GPIO_153_IOMUX_XGBE_LED3 2
+#endif
 #define GPIO_154_IOMUX_GPIOxx 0
 #define GPIO_154_IOMUX_UART4_RTS_L 1
+#if CONFIG(SOC_AMD_FAEGAN)
+#define GPIO_154_IOMUX_XGBE_LED4 2
+#endif
 #define GPIO_155_IOMUX_GPIOxx 0
 #define GPIO_155_IOMUX_UART4_RXD 1
+#if CONFIG(SOC_AMD_FAEGAN)
+#define GPIO_155_IOMUX_XGBE_LED5 2
+#endif
 #define GPIO_156_IOMUX_GPIOxx 0
 #define GPIO_156_IOMUX_UART4_TXD 1
+#if CONFIG(SOC_AMD_FAEGAN)
+#define GPIO_156_IOMUX_XGBE_LED6 2
+#endif
 #define GPIO_157_IOMUX_GPIOxx 0
 #define GPIO_157_IOMUX_UART4_INTR 1
+#if CONFIG(SOC_AMD_FAEGAN)
+#define GPIO_157_IOMUX_XGBE_LED7 2
+#endif
 
 #endif /* AMD_GLINDA_GPIO_H */

From f68450e39b1b0ed176537c10f02c49a9f05205d4 Mon Sep 17 00:00:00 2001
From: Patrick Rudolph <patrick.rudolph@9elements.com>
Date: Mon, 28 Jul 2025 09:07:30 +0200
Subject: [PATCH 2731/3886] vendorcode/amd/fsp/glinda: Update FSP UPDs

Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: I6162d3a8c71765ea1863eca4c875c2c672060a76
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90418
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/vendorcode/amd/fsp/glinda/FspmUpd.h       |  26 +++-
 .../amd/fsp/glinda/platform_descriptors.h     | 115 +++++++++++++++++-
 2 files changed, 138 insertions(+), 3 deletions(-)

diff --git a/src/vendorcode/amd/fsp/glinda/FspmUpd.h b/src/vendorcode/amd/fsp/glinda/FspmUpd.h
index 60a00b2bd0..4475a69180 100644
--- a/src/vendorcode/amd/fsp/glinda/FspmUpd.h
+++ b/src/vendorcode/amd/fsp/glinda/FspmUpd.h
@@ -98,7 +98,31 @@ typedef struct __packed {
 	/** Offset 0x04D7**/	uint8_t                     UnusedUpdSpace1;
 	/* usb_phy_ptr is actually struct usb_phy_config *, but that won't work for 64bit coreboot */
 	/** Offset 0x04D8**/	uint32_t                    usb_phy_ptr;
-	/** Offset 0x04DC**/	uint8_t                     UnusedUpdSpace2[292];
+	/** Offset 0x04DC**/	uint8_t                     Usb4Rt0En;
+	/** Offset 0x04DD**/	uint8_t                     Usb4Rt1En;
+	/** Offset 0x04DE**/	uint8_t                     Usb4Rt0XhciEn;
+	/** Offset 0x04DF**/	uint8_t                     Usb4Rt1XhciEn;
+	/** Offset 0x04E0**/	uint64_t                    xgbe_port0_mac;
+	/** Offset 0x04E8**/	uint64_t                    xgbe_port1_mac;
+	/** Offset 0x04F0**/	uint8_t                     xgbe_port0_config_en;
+	/** Offset 0x04F1**/	uint8_t                     xgbe_port1_config_en;
+	/* xgbe_port0_table_ptr is actually uint32_t *, but that won't work for 64bit coreboot */
+	/** Offset 0x04F2**/	uint32_t                    xgbe_port0_table_ptr;
+	/** Offset 0x04F6**/	uint32_t                    xgbe_port1_table_ptr;
+	/** Offset 0x04FA**/	uint8_t                     XgbeDisable;
+	/** Offset 0x04FB**/	uint8_t                     disp_combo_PHY;
+	/** Offset 0x04FC**/	uint8_t                     xgbe_led_en;
+	/** Offset 0x04FD**/	uint8_t                     xgbe_led_link_status0;
+	/** Offset 0x04FE**/	uint8_t                     xgbe_led_link_status1;
+	/** Offset 0x04FF**/	uint8_t                     xgbe_led_link_speed0;
+	/** Offset 0x0500**/	uint8_t                     xgbe_led_link_speed1;
+	/** Offset 0x0501**/	uint8_t                     xgbe_led_tx_rx_blink_rate0;
+	/** Offset 0x0502**/	uint8_t                     xgbe_led_tx_rx_blink_rate1;
+	/** Offset 0x0503**/	uint32_t                    fch_rt_device_enable_map;
+	/** Offset 0x0507**/	uint8_t                     amd_pcie_aer_report_mechanism;
+	/** Offset 0x0508**/	uint8_t                     amd_nbio_ras_controlv2;
+	/** Offset 0x0509**/	uint8_t                     pcie_ecrc_enablement;
+	/** Offset 0x050A**/	uint8_t                     UnusedUpdSpace2[246];
 	/** Offset 0x0600**/	uint16_t                    UpdTerminator;
 } FSP_M_CONFIG;
 
diff --git a/src/vendorcode/amd/fsp/glinda/platform_descriptors.h b/src/vendorcode/amd/fsp/glinda/platform_descriptors.h
index b214e915a9..c627517d6b 100644
--- a/src/vendorcode/amd/fsp/glinda/platform_descriptors.h
+++ b/src/vendorcode/amd/fsp/glinda/platform_descriptors.h
@@ -32,6 +32,7 @@ enum dxio_link_speed_cap {
 	GEN1,
 	GEN2,
 	GEN3,
+	GEN4,
 	GEN_INVALID		// Max Gen for boundary check
 };
 
@@ -199,7 +200,7 @@ typedef struct __packed {
 	uint32_t	reserved_3		:7;
 	uint32_t	device_number		:5;	// Desired root port device number
 	uint32_t	function_number		:3;	// Desired root port function number
-	uint32_t	link_speed_capability	:2;	// See dxio_link_speed_cap
+	uint32_t				:2;
 	uint32_t	auto_spd_change		:2;	// See dxio_upstream_auto_speed_change
 	uint32_t	eq_preset		:4;	// Gen3 equalization preset
 	uint32_t	link_aspm		:2;	// See dxio_aspm_type
@@ -209,7 +210,8 @@ typedef struct __packed {
 	uint8_t		link_hotplug;			// See dxio_link_hotplug_type
 	uint8_t		slot_power_limit;		// Currently unused by FSP
 	uint32_t	slot_power_limit_scale	:2;	// Currently unused by FSP
-	uint32_t	reserved_4		:6;
+	uint32_t	link_speed_capability	:3;	// See dxio_link_speed_cap
+	uint32_t				:3;
 	uint32_t	link_compliance_mode	:1;	// Currently unused by FSP
 	uint32_t	link_safe_mode		:1;	// Currently unused by FSP
 	uint32_t	sb_link			:1;	// Currently unused by FSP
@@ -221,4 +223,113 @@ typedef struct __packed {
 	uint16_t	port_params[NUM_DXIO_PORT_PARAMS*2];	// key-value parameters. see dxio_port_param_type
 } fsp_dxio_descriptor;
 
+typedef enum {
+	XGBE_PORT_DISABLE,
+	XGBE_PORT_ENABLE,
+} xgbe_port_enable;
+
+typedef enum {
+	XGBE_PHY_MODE_RJ45,
+	XGBE_PHY_MODE_SFP_PLUS,
+	XGBE_PHY_MODE_BACKPLANE
+} xgbe_port_phy_modes;
+
+typedef enum {
+	XGBE_RESERVED,
+	XGBE_10G_1G_BACKPLANE,
+	XGBE_2_5G_BACKPLANE,
+	XGBE_SOLDERED_DOWN_1000BASE_T,
+	XGBE_SOLDERED_DOWN_1000BASE_X,
+	XGBE_SOLDERED_DOWN_NBASE_T,
+	XGBE_SOLDERED_DOWN_10GBASE_T,
+	XGBE_SOLDERED_DOWN_10GBASE_R,
+	XGBE_SFP_PLUS_CONNECTOR,
+	XGBE_PORT_SGMII_BACKPLANE,
+	XGBE_5G_BACKPLANE,
+} xgbe_port_platform_config;
+
+typedef enum {
+	XGBE_PORT_SPEED_10M = 0x1,
+	XGBE_PORT_SPEED_100M = 0x2,
+	XGBE_PORT_SPEED_1G = 0x4,
+	XGBE_PORT_SPEED_2500M = 0x8,
+	XGBE_PORT_SPEED_5G = 0x32,
+	XGBE_PORT_SPEED_10G = 0x10,
+	XGBE_PORT_SPEED_10_100_1000M = 0x7,
+} xgbe_port_speed_config;
+
+typedef enum {
+	XGBE_PORT_NOT_USED = 0x0,
+	XGBE_SFP_PLUS_CONNECTION = 0x1,
+	XGBE_CONNECTION_MDIO_PHY = 0x2,
+	XGBE_BACKPLANE_CONNECTION = 0x4,
+} xgbe_port_connection_type;
+
+struct __packed xgbe_port_table {
+	uint8_t                 XgbePortConfig;                 ///< XGbE controller Port Config Enable/disable
+	uint8_t                 XgbePortPlatformConfig;         ///< Platform Config
+														  ///  @li   <b>0000</b> - Reserved
+														  ///  @li   <b>0001</b> - 10G/1G Backplane
+														  ///  @li   <b>0010</b> - 2.5G Backplane
+														  ///  @li   <b>0011</b> - 1000Base-T
+														  ///  @li   <b>0100</b> - 1000Base-X
+														  ///  @li   <b>0101</b> - NBase-T
+														  ///  @li   <b>0110</b> - 10GBase-T
+														  ///  @li   <b>0111</b> - 10GBase-X
+														  ///  @li   <b>1000</b> - SFP+
+	uint8_t                 XgbePortSupportedSpeed;         ///< Indicated Ethernet speeds supported on platform
+														  ///  @li   <b>1xxx</b> - 10/100/1000M
+														  ///  @li   <b>x1xx</b> - 1G
+														  ///  @li   <b>xx1x</b> - 1G
+														  ///  @li   <b>xxx1</b> - 100M
+	uint8_t                 XgbePortConnectedType;          ///< PHY connected type
+														  ///  @li   <b>000</b> - Port not used
+														  ///  @li   <b>001</b> - SFP+
+														  ///  @li   <b>010</b> - MDIO
+														  ///  @li   <b>100</b> - Backplane connection
+	uint8_t                 XgbePortMdioId;                 ///< MDIO ID of the PHY associated with this port
+	uint8_t                 XgbePortMdioResetType;          ///< MDIO PHY reset type
+														  ///  @li   <b>00</b> - None
+														  ///  @li   <b>01</b> - I2C GPIO
+														  ///  @li   <b>10</b> - Integrated GPIO
+														  ///  @li   <b>11</b> - Reserved
+	uint8_t                 XgbePortResetGpioNum;           ///< GPIO used to control the reset
+	uint8_t                 XgbePortMdioResetI2cAddress;    ///< I2C address of PCA9535 MDIO reset GPIO
+	uint8_t                 XgbePortSfpI2cAddress;          ///< I2C address of PCA9535 for SFP
+	uint8_t                 XgbePortSfpTxFaultGpio;         ///< GPIO number for SFP+ TX_FAULT
+	uint8_t                 XgbePortSfpRsGpio;              ///< GPIO number for SFP+ RS
+	uint8_t                 XgbePortSfpModAbsGpio;          ///< GPIO number for SFP+ Mod_ABS
+	uint8_t                 XgbePortSfpRxLosGpio;           ///< GPIO number for SFP+ Rx_LOS
+	uint8_t                 XgbePortSfpGpioMask;            ///< GPIO Mask for SFP+
+														  ///  @li   <b>1xxx</b> - Rx_LOS not supported
+														  ///  @li   <b>x1xx</b> - Mod_ABS not supported
+														  ///  @li   <b>xx1x</b> - RS not supported
+														  ///  @li   <b>xxx1</b> - TX_FAULT not supported
+	uint8_t                 XgbePortSfpTwiAddress;          ///< Address of PCA9545 I2C multiplexor
+	uint8_t                 XgbePortSfpTwiBus;              ///< Downstream channel of PCA9545
+	uint8_t                 XgbaPortRedriverPresent;        ///< Redriver Present or not
+	uint8_t                 Reserve0[3];                    ///< Reserved
+	uint8_t                 XgbaPortRedriverModel;          ///< Redriver Model
+														  ///  @li   <b>00</b> - InPhi 4223
+														  ///  @li   <b>01</b> - InPhi 4227
+	uint8_t                 XgbaPortRedriverInterface;      ///< Redriver Interface
+														  ///  @li   <b>00</b> - MDIO
+														  ///  @li   <b>01</b> - I2C
+	uint8_t                 XgbaPortRedriverAddress;        ///< Redriver Address
+	uint8_t                 XgbaPortRedriverLane;           ///< Redriver Lane
+	uint8_t                 XgbaPortPadGpio;                ///< Portx_GPIO Pad selection
+														  ///  @li   <b>001</b> - MDIO0 pin
+														  ///  @li   <b>010</b> - MDIO1 pin
+														  ///  @li   <b>100</b> - SFP pin
+	uint8_t                 XgbaPortPadMdio;                ///< Portx_Mdio Pad selection
+														  ///  @li   <b>001</b> - MDIO0 pin
+														  ///  @li   <b>010</b> - MDIO1 pin
+														  ///  @li   <b>100</b> - SFP pin
+	uint8_t                 XgbaPortPadI2C;                 ///< Portx_I2C Pad selection
+														  ///  @li   <b>001</b> - MDIO0 pin
+														  ///  @li   <b>010</b> - MDIO1 pin
+														  ///  @li   <b>100</b> - SFP pin
+	uint8_t                 Reserve1;                       ///< Reserved
+  };
+
 #endif /* PI_PLATFORM_DESCRIPTORS_H */

From f4aeac42767d36d3df97a5ebe382dd4710957174 Mon Sep 17 00:00:00 2001
From: Maximilian Brune <maximilian.brune@9elements.com>
Date: Fri, 28 Nov 2025 16:35:24 +0100
Subject: [PATCH 2732/3886] soc/amd/glinda: Set FSP UPDs from devicetree for
 USB4

Use is_dev_enabled() on devicetree device to enable/disable USB4 devices
by updating the corresponding FSP UPDs.

Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: If0ae88eaaf88954159b55fdf030eb96d74ee29f6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90419
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
---
 src/soc/amd/glinda/fsp_m_params.c | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/src/soc/amd/glinda/fsp_m_params.c b/src/soc/amd/glinda/fsp_m_params.c
index 1d297d481d..32a708fd70 100644
--- a/src/soc/amd/glinda/fsp_m_params.c
+++ b/src/soc/amd/glinda/fsp_m_params.c
@@ -137,6 +137,11 @@ void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version)
 	mcfg->s0i3_enable = config->s0ix_enable;
 	mcfg->iommu_support = is_devfn_enabled(IOMMU_DEVFN);
 
+	mcfg->Usb4Rt0En = is_dev_enabled(DEV_PTR(usb4_router_0));
+	mcfg->Usb4Rt1En = is_dev_enabled(DEV_PTR(usb4_router_1));
+	mcfg->Usb4Rt0XhciEn = is_dev_enabled(DEV_PTR(usb4_xhci_0));
+	mcfg->Usb4Rt1XhciEn = is_dev_enabled(DEV_PTR(usb4_xhci_1));
+
 	/* voltage regulator telemetry settings */
 	mcfg->telemetry_vddcrvddfull_scale_current =
 		config->telemetry_vddcrvddfull_scale_current_mA;

From 29bec62a22df770cd984074364f6f311d21cbcef Mon Sep 17 00:00:00 2001
From: Maximilian Brune <maximilian.brune@9elements.com>
Date: Wed, 27 Aug 2025 14:26:22 +0200
Subject: [PATCH 2733/3886] cpu/x86/Kconfig: Remove SOC_SETS_MSRS option

The option was introduced by
commit ae738acdc5f0 ("cpu/x86: Support CPUs without rdmsr/wrmsr")
for the intel quark SOC. However the SOC doesn't exist anymore in
coreboot. Nor does any other SOC use this option.

Therefore remove it.

Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: I4f3f5e91c00784c159042271387c2e862f351881
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90421
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/cpu/x86/Kconfig              |  7 -------
 src/include/cpu/x86/msr_access.h | 17 -----------------
 2 files changed, 24 deletions(-)

diff --git a/src/cpu/x86/Kconfig b/src/cpu/x86/Kconfig
index 15c884e1e8..7a701bb9d6 100644
--- a/src/cpu/x86/Kconfig
+++ b/src/cpu/x86/Kconfig
@@ -235,13 +235,6 @@ config X86_INIT_NEED_1_SIPI
 	  These newer AMD and Intel platforms don't need the 10ms wait between
 	  INIT and SIPI, so skip that too to save some time.
 
-config SOC_SETS_MSRS
-	bool
-	default n
-	help
-	  The SoC requires different access methods for reading and writing
-	  the MSRs.  Use SoC specific routines to handle the MSR access.
-
 config RESERVE_MTRRS_FOR_OS
 	bool
 	default n
diff --git a/src/include/cpu/x86/msr_access.h b/src/include/cpu/x86/msr_access.h
index 33029cc653..d6dd0967f6 100644
--- a/src/include/cpu/x86/msr_access.h
+++ b/src/include/cpu/x86/msr_access.h
@@ -15,22 +15,6 @@ typedef union msr_union {
 } msr_t;
 _Static_assert(sizeof(msr_t) == sizeof(uint64_t), "Incorrect size for msr_t");
 
-#if CONFIG(SOC_SETS_MSRS)
-msr_t soc_msr_read(unsigned int index);
-void soc_msr_write(unsigned int index, msr_t msr);
-
-/* Handle MSR references in the other source code */
-static __always_inline msr_t rdmsr(unsigned int index)
-{
-	return soc_msr_read(index);
-}
-
-static __always_inline void wrmsr(unsigned int index, msr_t msr)
-{
-	soc_msr_write(index, msr);
-}
-#else /* CONFIG_SOC_SETS_MSRS */
-
 /* The following functions require the __always_inline due to AMD
  * function STOP_CAR_AND_CPU that disables cache as
  * RAM, the cache as RAM stack can no longer be used. Called
@@ -61,6 +45,5 @@ static __always_inline void wrmsr(unsigned int index, msr_t msr)
 		);
 }
 
-#endif /* CONFIG_SOC_SETS_MSRS */
 #endif /* __ASSEMBLER__ */
 #endif /* CPU_X86_MSR_ACCESS_H */

From db01aa6cb29e3fe05631416fb70f95e195bbc0cc Mon Sep 17 00:00:00 2001
From: Maximilian Brune <maximilian.brune@9elements.com>
Date: Sun, 30 Nov 2025 03:23:58 +0100
Subject: [PATCH 2734/3886] commonlib/device_tree.c: Fix skipping NOP tokens

The current code doesn't make much sense. The offset created by the
skipping of NOP tokens is just ignored.

Reorder the lines to skip the NOP tokens first.

Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: I860a57e4a773b634149e84271b8322d78ac20e32
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90277
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
---
 src/commonlib/device_tree.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/src/commonlib/device_tree.c b/src/commonlib/device_tree.c
index 595c3cbb5d..b51f9fc31d 100644
--- a/src/commonlib/device_tree.c
+++ b/src/commonlib/device_tree.c
@@ -116,11 +116,12 @@ int fdt_next_property(const void *blob, uint32_t offset,
 		      struct fdt_property *prop)
 {
 	struct fdt_header *header = (struct fdt_header *)blob;
-	uint32_t *ptr = (uint32_t *)(((uint8_t *)blob) + offset);
 
 	// skip NOP tokens
 	offset += fdt_skip_nops(blob, offset);
 
+	uint32_t *ptr = (uint32_t *)(((uint8_t *)blob) + offset);
+
 	int index = 0;
 	if (be32toh(ptr[index++]) != FDT_TOKEN_PROPERTY)
 		return 0;

From 4a5d0dee4af4d2c10313e97bce8efb5913197171 Mon Sep 17 00:00:00 2001
From: Payne Lin <payne.lin@mediatek.corp-partner.google.com>
Date: Thu, 4 Dec 2025 10:43:35 +0800
Subject: [PATCH 2735/3886] soc/mediatek/mt8189: Correct AUX LDO mask bit
 definition

Fix the bit definition for RGS_AUX_LDO_EN_READY_MASK in the MT8189
dptx_reg.h file, changing it from BIT(2) to BIT(0). The MT8189 is only
polling BIT(0) status instead of BIT(2). This correction ensures proper
functionality of the AUX LDO readiness check.

BUG=b:461384417
TEST=Boot up can see develop mode.
BRANCH=skywalker

Signed-off-by: Payne Lin <payne.lin@mediatek.corp-partner.google.com>
Change-Id: Id4a85c619311fecde5bc84ad29c521b7d20ffdd8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90362
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/soc/mediatek/mt8189/include/soc/dptx_reg.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/soc/mediatek/mt8189/include/soc/dptx_reg.h b/src/soc/mediatek/mt8189/include/soc/dptx_reg.h
index 02366dc8d4..af2e6a131e 100644
--- a/src/soc/mediatek/mt8189/include/soc/dptx_reg.h
+++ b/src/soc/mediatek/mt8189/include/soc/dptx_reg.h
@@ -6,7 +6,7 @@
 #include <soc/dptx_reg_v2.h>
 
 #define DP_PHY_DIG_TX_CTL_0			0x1444
-#define RGS_AUX_LDO_EN_READY_MASK		BIT(2)
+#define RGS_AUX_LDO_EN_READY_MASK		BIT(0)
 #define DRIVING_FORCE				0x18
 #define EDP_TX_LN_PRE_EMPH_VAL_MASK		GENMASK(6, 5)
 #define EDP_TX_LN_PRE_EMPH_VAL_SHIFT		5

From 0513c45a38df0560a0c094b22e46c2b0da6dfe63 Mon Sep 17 00:00:00 2001
From: Wayby Zhai <wayby.zhai@lcfc.corp-partner.google.com>
Date: Mon, 8 Dec 2025 13:10:13 +0800
Subject: [PATCH 2736/3886] mb/google/nissa/var/pujjoga: Generate RAM ID for
 MT62F1G32D2DS-031RF WT:C

Generate RAM ID for MT62F512M32D1DS-023 WT:E

DRAM Part Name                 ID to assign
MT62F1G32D2DS-031RF WT:C       4 (0100)

BUG=b:466889567
TEST=emerge-nissa coreboot chromeos-bootimage

Change-Id: I6a6ed45cacc9a10bc7a2cfc3b41cee93c552a6cd
Signed-off-by: Wayby Zhai <wayby.zhai@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90411
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/google/brya/variants/pujjoga/memory/Makefile.mk    | 1 +
 .../google/brya/variants/pujjoga/memory/dram_id.generated.txt    | 1 +
 .../google/brya/variants/pujjoga/memory/mem_parts_used.txt       | 1 +
 3 files changed, 3 insertions(+)

diff --git a/src/mainboard/google/brya/variants/pujjoga/memory/Makefile.mk b/src/mainboard/google/brya/variants/pujjoga/memory/Makefile.mk
index 54cd4b0bc6..152fb78333 100644
--- a/src/mainboard/google/brya/variants/pujjoga/memory/Makefile.mk
+++ b/src/mainboard/google/brya/variants/pujjoga/memory/Makefile.mk
@@ -8,3 +8,4 @@ SPD_SOURCES += spd/lp5/set-0/spd-7.hex      # ID = 0(0b0000)  Parts = H58G56BK7B
 SPD_SOURCES += spd/lp5/set-0/spd-1.hex      # ID = 1(0b0001)  Parts = H9JCNNNBK3MLYR-N6E
 SPD_SOURCES += spd/lp5/set-0/spd-9.hex      # ID = 2(0b0010)  Parts = K3KL6L60GM-MGCT
 SPD_SOURCES += spd/lp5/set-0/spd-11.hex      # ID = 3(0b0011)  Parts = H58G56CK8BX146
+SPD_SOURCES += spd/lp5/set-0/spd-3.hex      # ID = 4(0b0100)  Parts = MT62F1G32D2DS-031RF WT:C
diff --git a/src/mainboard/google/brya/variants/pujjoga/memory/dram_id.generated.txt b/src/mainboard/google/brya/variants/pujjoga/memory/dram_id.generated.txt
index 40724af2c5..a4ddedd3bb 100644
--- a/src/mainboard/google/brya/variants/pujjoga/memory/dram_id.generated.txt
+++ b/src/mainboard/google/brya/variants/pujjoga/memory/dram_id.generated.txt
@@ -10,3 +10,4 @@ K3KL6L60GM-MGCT                2 (0010)
 K3KL8L80CM-MGCT                0 (0000)
 MT62F1G32D2DS-026 WT:B         0 (0000)
 H58G56CK8BX146                 3 (0011)
+MT62F1G32D2DS-031RF WT:C       4 (0100)
diff --git a/src/mainboard/google/brya/variants/pujjoga/memory/mem_parts_used.txt b/src/mainboard/google/brya/variants/pujjoga/memory/mem_parts_used.txt
index 98df9d25b1..9ffbcb47a7 100644
--- a/src/mainboard/google/brya/variants/pujjoga/memory/mem_parts_used.txt
+++ b/src/mainboard/google/brya/variants/pujjoga/memory/mem_parts_used.txt
@@ -15,3 +15,4 @@ K3KL6L60GM-MGCT
 K3KL8L80CM-MGCT
 MT62F1G32D2DS-026 WT:B
 H58G56CK8BX146
+MT62F1G32D2DS-031RF WT:C

From 626789b40a830d6859d76baec819b390104b9c59 Mon Sep 17 00:00:00 2001
From: Uwe Poeche <uwe.poeche@siemens.com>
Date: Tue, 2 Dec 2025 14:21:19 +0100
Subject: [PATCH 2737/3886] mb/siemens/mc_ehl{1..5}: Unify devicetrees
 SerialIoI2cPadsTermination

Unify the I2C pad termination on all mc_ehl boards for better code
readability and continuity in the devicetrees. This patch does not
change the actual I2C pad termination configuration.

All the mc_ehl boards use external resistors for I2C termination.
Therefore, there is no need for internal termination at all. If the FSP
parameter 'SerialIoI2cPadsTermination' is omitted from the device tree,
the generic GPIO settings can define termination. If
'SerialIoI2cPadsTermination' is specified for an inactive I2C
controller, those settings are ignored.

This patch consistently adds 'SerialIoI2cPadsTermination' to the device
tree for all active mc_ehl boards, and removes it for controllers that
are switched off.
This topic came up in review for commit 864e3ca66145
("mb/siemens/mc_ehl6: Adjust I2C setup").

TEST=Build and boot to OS on mc_ehl1/2/4 and compare register contents
of PAD_CFG_DW0/1 registers for all 8 I2C controllers before and after
the patch to ensure no change in I2C pad termination.

Change-Id: Iba75778893e0b6a7acb68535d0407dc1fc43d2ca
Signed-off-by: Uwe Poeche <uwe.poeche@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90364
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
---
 .../siemens/mc_ehl/variants/mc_ehl1/devicetree.cb        | 6 ------
 .../siemens/mc_ehl/variants/mc_ehl2/devicetree.cb        | 9 +++++++++
 .../siemens/mc_ehl/variants/mc_ehl3/devicetree.cb        | 9 +++++++++
 .../siemens/mc_ehl/variants/mc_ehl4/devicetree.cb        | 6 ------
 .../siemens/mc_ehl/variants/mc_ehl5/devicetree.cb        | 9 +++++++++
 5 files changed, 27 insertions(+), 12 deletions(-)

diff --git a/src/mainboard/siemens/mc_ehl/variants/mc_ehl1/devicetree.cb b/src/mainboard/siemens/mc_ehl/variants/mc_ehl1/devicetree.cb
index 60c4b474c7..6e85734887 100644
--- a/src/mainboard/siemens/mc_ehl/variants/mc_ehl1/devicetree.cb
+++ b/src/mainboard/siemens/mc_ehl/variants/mc_ehl1/devicetree.cb
@@ -95,14 +95,8 @@ chip soc/intel/elkhartlake
 	}"
 
 	register "SerialIoI2cPadsTermination" = "{
-		[PchSerialIoIndexI2C0] = 1,
 		[PchSerialIoIndexI2C1] = 1,
-		[PchSerialIoIndexI2C2] = 1,
-		[PchSerialIoIndexI2C3] = 1,
 		[PchSerialIoIndexI2C4] = 1,
-		[PchSerialIoIndexI2C5] = 1,
-		[PchSerialIoIndexI2C6] = 1,
-		[PchSerialIoIndexI2C7] = 1,
 	}"
 
 	register "SerialIoUartMode" = "{
diff --git a/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb b/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb
index 67ece6d158..4a7a997446 100644
--- a/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb
+++ b/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb
@@ -82,6 +82,15 @@ chip soc/intel/elkhartlake
 		[PchSerialIoIndexI2C7] = PchSerialIoDisabled,
 	}"
 
+	register "SerialIoI2cPadsTermination" = "{
+		[PchSerialIoIndexI2C0] = 1,
+		[PchSerialIoIndexI2C1] = 1,
+		[PchSerialIoIndexI2C2] = 1,
+		[PchSerialIoIndexI2C3] = 1,
+		[PchSerialIoIndexI2C4] = 1,
+		[PchSerialIoIndexI2C5] = 1,
+	}"
+
 	register "SerialIoUartMode" = "{
 		[PchSerialIoIndexUART0] = PchSerialIoPci,
 		[PchSerialIoIndexUART1] = PchSerialIoPci,
diff --git a/src/mainboard/siemens/mc_ehl/variants/mc_ehl3/devicetree.cb b/src/mainboard/siemens/mc_ehl/variants/mc_ehl3/devicetree.cb
index 54bd62b0f1..71baa47b11 100644
--- a/src/mainboard/siemens/mc_ehl/variants/mc_ehl3/devicetree.cb
+++ b/src/mainboard/siemens/mc_ehl/variants/mc_ehl3/devicetree.cb
@@ -84,6 +84,15 @@ chip soc/intel/elkhartlake
 		[PchSerialIoIndexI2C7] = PchSerialIoDisabled,
 	}"
 
+	register "SerialIoI2cPadsTermination" = "{
+		[PchSerialIoIndexI2C0] = 1,
+		[PchSerialIoIndexI2C1] = 1,
+		[PchSerialIoIndexI2C2] = 1,
+		[PchSerialIoIndexI2C3] = 1,
+		[PchSerialIoIndexI2C4] = 1,
+		[PchSerialIoIndexI2C5] = 1,
+	}"
+
 	register "SerialIoUartMode" = "{
 		[PchSerialIoIndexUART0] = PchSerialIoPci,
 		[PchSerialIoIndexUART1] = PchSerialIoPci,
diff --git a/src/mainboard/siemens/mc_ehl/variants/mc_ehl4/devicetree.cb b/src/mainboard/siemens/mc_ehl/variants/mc_ehl4/devicetree.cb
index 17d6780d37..f17052076a 100644
--- a/src/mainboard/siemens/mc_ehl/variants/mc_ehl4/devicetree.cb
+++ b/src/mainboard/siemens/mc_ehl/variants/mc_ehl4/devicetree.cb
@@ -102,14 +102,8 @@ chip soc/intel/elkhartlake
 	}"
 
 	register "SerialIoI2cPadsTermination" = "{
-		[PchSerialIoIndexI2C0] = 1,
 		[PchSerialIoIndexI2C1] = 1,
-		[PchSerialIoIndexI2C2] = 1,
-		[PchSerialIoIndexI2C3] = 1,
 		[PchSerialIoIndexI2C4] = 1,
-		[PchSerialIoIndexI2C5] = 1,
-		[PchSerialIoIndexI2C6] = 1,
-		[PchSerialIoIndexI2C7] = 1,
 	}"
 
 	register "SerialIoUartMode" = "{
diff --git a/src/mainboard/siemens/mc_ehl/variants/mc_ehl5/devicetree.cb b/src/mainboard/siemens/mc_ehl/variants/mc_ehl5/devicetree.cb
index 5998e0e09d..bcd76cb991 100644
--- a/src/mainboard/siemens/mc_ehl/variants/mc_ehl5/devicetree.cb
+++ b/src/mainboard/siemens/mc_ehl/variants/mc_ehl5/devicetree.cb
@@ -82,6 +82,15 @@ chip soc/intel/elkhartlake
 		[PchSerialIoIndexI2C7] = PchSerialIoDisabled,
 	}"
 
+	register "SerialIoI2cPadsTermination" = "{
+		[PchSerialIoIndexI2C0] = 1,
+		[PchSerialIoIndexI2C1] = 1,
+		[PchSerialIoIndexI2C2] = 1,
+		[PchSerialIoIndexI2C3] = 1,
+		[PchSerialIoIndexI2C4] = 1,
+		[PchSerialIoIndexI2C5] = 1,
+	}"
+
 	register "SerialIoUartMode" = "{
 		[PchSerialIoIndexUART0] = PchSerialIoPci,
 		[PchSerialIoIndexUART1] = PchSerialIoPci,

From fee2befc8270d79c1be8abe3fca3ef775874bed7 Mon Sep 17 00:00:00 2001
From: Felix Singer <felixsinger@posteo.net>
Date: Wed, 3 Dec 2025 19:12:54 +0000
Subject: [PATCH 2738/3886] 3rdparty/blobs: Update to upstream main

Updating from commit id 2aefd97c3e01:
2025-10-06 10:54:06 +0800 - (soc/mediatek/mt8196: Update PI_IMG firmware to v1.1)

to commit id 4a8de0324e7d:
2025-11-28 09:19:20 +0800 - (soc/mediatek/mt8196: Add GPUEB firmware v2.0)

This brings in 3 new commits:
4a8de0324e7d soc/mediatek/mt8196: Add GPUEB firmware v2.0
a89fd00da82f soc/mediatek/mt8196: Update DRAM blob to 16486.0.0
b8300132cebb soc/mediatek/mt8189: Update MCUPM firmware to v1.2 for 3.0GHz SoC

Change-Id: I45403316aa67e2f0afc6d2a74ab84c3402d56595
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90357
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
---
 3rdparty/blobs | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/3rdparty/blobs b/3rdparty/blobs
index 2aefd97c3e..4a8de0324e 160000
--- a/3rdparty/blobs
+++ b/3rdparty/blobs
@@ -1 +1 @@
-Subproject commit 2aefd97c3e012c87a7dbfd5728c987fe51200b71
+Subproject commit 4a8de0324e7d389454ec33cdf66939b653bf6800

From 459cdd09f40f9e93a5e8d29ed5b07ac09fee0209 Mon Sep 17 00:00:00 2001
From: Chen-Tsung Hsieh <chentsung@chromium.org>
Date: Mon, 1 Dec 2025 17:29:32 +0800
Subject: [PATCH 2739/3886] mb/google/rauru: Add variant-specific firmware
 config

This change introduces support for variant-specific firmware
configurations (fw_config) for the Rauru mainboard, specifically adding
initial support for the Sapphire variant.

The fw_config fields for Sapphire are defined in b:458266555.

All fw_config fields are now defined in variant-specific overridetree.cb
files (hylia, navi, rauru, sapphire). Consequently, access to these
fw_config values has been refactored to be encapsulated within
variant-specific fw_config.c files. This approach ensures that common
mainboard code does not need direct knowledge of variant-specific
fw_config definitions.

This is demonstrated by the audio amplifier initialization, which
now uses a variant-specific get_audio_amp_id() function to determine
the hardware present, rather than directly probing fw_config in the
common code.

BRANCH=None
BUG=b:458266555, b:448281461, b:461594346
TEST=emerge-tanjiro coreboot && emerge-rauru coreboot && test on navi

Change-Id: Iecca5820421f250e1a22cec110b36fb578edd9e7
Signed-off-by: Chen-Tsung Hsieh <chentsung@chromium.org>
Signed-off-by: Wentao Qin <qinwentao@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90330
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
---
 src/mainboard/google/rauru/Kconfig            |  6 ++-
 src/mainboard/google/rauru/chromeos.c         | 20 ++++++---
 src/mainboard/google/rauru/devicetree.cb      |  8 ----
 src/mainboard/google/rauru/include/variants.h |  9 ++++
 src/mainboard/google/rauru/mainboard.c        | 17 +++++---
 .../google/rauru/variants/hylia/Makefile.mk   |  3 ++
 .../google/rauru/variants/hylia/fw_config.c   | 15 +++++++
 .../rauru/variants/hylia/overridetree.cb      | 14 +++++++
 .../google/rauru/variants/navi/fw_config.c    | 11 +++++
 .../rauru/variants/navi/overridetree.cb       |  5 +++
 .../google/rauru/variants/rauru/Makefile.mk   |  3 ++
 .../google/rauru/variants/rauru/fw_config.c   | 15 +++++++
 .../rauru/variants/rauru/overridetree.cb      | 14 +++++++
 .../rauru/variants/sapphire/Makefile.mk       |  3 ++
 .../rauru/variants/sapphire/fw_config.c       | 12 ++++++
 .../rauru/variants/sapphire/overridetree.cb   | 41 +++++++++++++++++++
 16 files changed, 176 insertions(+), 20 deletions(-)
 create mode 100644 src/mainboard/google/rauru/variants/hylia/Makefile.mk
 create mode 100644 src/mainboard/google/rauru/variants/hylia/fw_config.c
 create mode 100644 src/mainboard/google/rauru/variants/hylia/overridetree.cb
 create mode 100644 src/mainboard/google/rauru/variants/rauru/Makefile.mk
 create mode 100644 src/mainboard/google/rauru/variants/rauru/fw_config.c
 create mode 100644 src/mainboard/google/rauru/variants/rauru/overridetree.cb
 create mode 100644 src/mainboard/google/rauru/variants/sapphire/Makefile.mk
 create mode 100644 src/mainboard/google/rauru/variants/sapphire/fw_config.c
 create mode 100644 src/mainboard/google/rauru/variants/sapphire/overridetree.cb

diff --git a/src/mainboard/google/rauru/Kconfig b/src/mainboard/google/rauru/Kconfig
index fbf2efa3a2..486e273874 100644
--- a/src/mainboard/google/rauru/Kconfig
+++ b/src/mainboard/google/rauru/Kconfig
@@ -29,6 +29,7 @@ config BOARD_SPECIFIC_OPTIONS
 	select CHROMEOS_USE_EC_WATCHDOG_FLAG if CHROMEOS
 	select EC_GOOGLE_CHROMEEC
 	select EC_GOOGLE_CHROMEEC_BOARDID
+	select EC_GOOGLE_CHROMEEC_FW_CONFIG_FROM_UFSC if BOARD_GOOGLE_SAPPHIRE
 	select EC_GOOGLE_CHROMEEC_SPI
 	select I2C_TPM if VBOOT
 	select MAINBOARD_HAS_TPM2 if VBOOT
@@ -52,10 +53,13 @@ config MAINBOARD_PART_NUMBER
 	default "Sapphire" if BOARD_GOOGLE_SAPPHIRE
 
 config VARIANT_DIR
+	default "hylia" if BOARD_GOOGLE_HYLIA
 	default "navi" if BOARD_GOOGLE_NAVI
+	default "rauru" if BOARD_GOOGLE_RAURU
+	default "sapphire" if BOARD_GOOGLE_SAPPHIRE
 
 config OVERRIDE_DEVICETREE
-	default "variants/\$(CONFIG_VARIANT_DIR)/overridetree.cb" if BOARD_GOOGLE_NAVI
+	default "variants/\$(CONFIG_VARIANT_DIR)/overridetree.cb"
 
 config BOOT_DEVICE_SPI_FLASH_BUS
 	int
diff --git a/src/mainboard/google/rauru/chromeos.c b/src/mainboard/google/rauru/chromeos.c
index 33316393ac..b784a2f3f7 100644
--- a/src/mainboard/google/rauru/chromeos.c
+++ b/src/mainboard/google/rauru/chromeos.c
@@ -2,8 +2,8 @@
 
 #include <boot/coreboot_tables.h>
 #include <drivers/tpm/cr50.h>
-#include <fw_config.h>
 #include <gpio.h>
+#include <variants.h>
 
 #include "gpio.h"
 
@@ -79,12 +79,20 @@ void fill_lb_gpios(struct lb_gpios *gpios)
 		{GPIO_EN_SPKR.id, ACTIVE_HIGH, -1, "speaker enable"},
 	};
 
-	if (fw_config_probe(FW_CONFIG(AUDIO_AMP, AMP_TAS2563)))
-		lb_add_gpios(gpios, smartamp_gpios, ARRAY_SIZE(smartamp_gpios));
-	else if (fw_config_probe(FW_CONFIG(AUDIO_AMP, AMP_ALC5645)))
-		lb_add_gpios(gpios, alc5645_gpios, ARRAY_SIZE(alc5645_gpios));
-	else
+	switch (get_audio_amp_id()) {
+	case AUD_AMP_ID_NAU8318:
 		lb_add_gpios(gpios, nau8318_gpios, ARRAY_SIZE(nau8318_gpios));
+		break;
+	case AUD_AMP_ID_TAS2563:
+		lb_add_gpios(gpios, smartamp_gpios, ARRAY_SIZE(smartamp_gpios));
+		break;
+	case AUD_AMP_ID_ALC5645:
+		lb_add_gpios(gpios, alc5645_gpios, ARRAY_SIZE(alc5645_gpios));
+		break;
+	case AUD_AMP_ID_UNKNOWN:
+	default:
+		break;
+	}
 
 	struct lb_gpio edp_pwm_backlight_gpios[] = {
 		{GPIO_BL_PWM_1V8.id, ACTIVE_HIGH, -1, "PWM control"},
diff --git a/src/mainboard/google/rauru/devicetree.cb b/src/mainboard/google/rauru/devicetree.cb
index 1705dbeb9b..df65b3f24b 100644
--- a/src/mainboard/google/rauru/devicetree.cb
+++ b/src/mainboard/google/rauru/devicetree.cb
@@ -1,13 +1,5 @@
 ## SPDX-License-Identifier: GPL-2.0-only
 
-fw_config
-	field AUDIO_AMP 28 29
-		option AMP_NAU8318 0
-		option AMP_TAS2563 1
-		option AMP_ALC5645 2
-	end
-end
-
 chip soc/mediatek/mt8196
 	device cpu_cluster 0 on end
 
diff --git a/src/mainboard/google/rauru/include/variants.h b/src/mainboard/google/rauru/include/variants.h
index 853b64a8ba..56eb334051 100644
--- a/src/mainboard/google/rauru/include/variants.h
+++ b/src/mainboard/google/rauru/include/variants.h
@@ -5,6 +5,15 @@
 
 #include <soc/display.h>
 
+enum audio_amplifier_id {
+	AUD_AMP_ID_UNKNOWN,
+	AUD_AMP_ID_NAU8318,
+	AUD_AMP_ID_TAS2563,
+	AUD_AMP_ID_ALC5645,
+};
+
+enum audio_amplifier_id get_audio_amp_id(void);
+
 void fw_config_panel_override(struct panel_description *panel);
 
 #endif /* __MAINBOARD_GOOGLE_RAURU_VARIANTS_H__ */
diff --git a/src/mainboard/google/rauru/mainboard.c b/src/mainboard/google/rauru/mainboard.c
index f55da81329..d0ed3ad7f7 100644
--- a/src/mainboard/google/rauru/mainboard.c
+++ b/src/mainboard/google/rauru/mainboard.c
@@ -3,7 +3,6 @@
 #include <bootmode.h>
 #include <console/console.h>
 #include <device/device.h>
-#include <fw_config.h>
 #include <gpio.h>
 #include <soc/addressmap.h>
 #include <soc/bl31.h>
@@ -17,6 +16,7 @@
 #include <soc/spm_common.h>
 #include <soc/storage.h>
 #include <soc/usb.h>
+#include <variants.h>
 
 #include "gpio.h"
 #include "storage.h"
@@ -52,15 +52,22 @@ static void configure_alc5645(void)
 
 	printk(BIOS_INFO, "%s: done\n", __func__);
 }
+
 static void configure_audio(void)
 {
-	if (fw_config_probe(FW_CONFIG(AUDIO_AMP, AMP_TAS2563))) {
+	switch (get_audio_amp_id()) {
+	case AUD_AMP_ID_TAS2563:
 		mtk_i2c_bus_init(I2C3, I2C_SPEED_FAST);
 		configure_tas2563();
-	} else if (fw_config_probe(FW_CONFIG(AUDIO_AMP, AMP_ALC5645))) {
+		break;
+	case AUD_AMP_ID_ALC5645:
 		configure_alc5645();
-	} else {
-		printk(BIOS_INFO, "Audio configure default amps NAU8318\n");
+		break;
+	case AUD_AMP_ID_NAU8318:
+	case AUD_AMP_ID_UNKNOWN:
+	default:
+		/* No configuration needed for NAU8318 or UNKNOWN */
+		break;
 	}
 
 	printk(BIOS_INFO, "%s: done\n", __func__);
diff --git a/src/mainboard/google/rauru/variants/hylia/Makefile.mk b/src/mainboard/google/rauru/variants/hylia/Makefile.mk
new file mode 100644
index 0000000000..52fd109576
--- /dev/null
+++ b/src/mainboard/google/rauru/variants/hylia/Makefile.mk
@@ -0,0 +1,3 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
+ramstage-y += fw_config.c
diff --git a/src/mainboard/google/rauru/variants/hylia/fw_config.c b/src/mainboard/google/rauru/variants/hylia/fw_config.c
new file mode 100644
index 0000000000..4332c97c62
--- /dev/null
+++ b/src/mainboard/google/rauru/variants/hylia/fw_config.c
@@ -0,0 +1,15 @@
+/* SPDX-License-Identifier: GPL-2.0-only OR MIT */
+
+#include <fw_config.h>
+#include <variants.h>
+
+enum audio_amplifier_id get_audio_amp_id(void)
+{
+	if (fw_config_probe(FW_CONFIG(AUDIO_AMPLIFIER, AUDIO_AMPLIFIER_TAS2563)))
+		return AUD_AMP_ID_TAS2563;
+
+	if (fw_config_probe(FW_CONFIG(AUDIO_AMPLIFIER, AUDIO_AMPLIFIER_ALC5645)))
+		return AUD_AMP_ID_ALC5645;
+
+	return AUD_AMP_ID_NAU8318;
+}
diff --git a/src/mainboard/google/rauru/variants/hylia/overridetree.cb b/src/mainboard/google/rauru/variants/hylia/overridetree.cb
new file mode 100644
index 0000000000..d3cc60d31b
--- /dev/null
+++ b/src/mainboard/google/rauru/variants/hylia/overridetree.cb
@@ -0,0 +1,14 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
+fw_config
+	field AUDIO_AMPLIFIER 28 29
+		option AUDIO_AMPLIFIER_NAU8318 0
+		option AUDIO_AMPLIFIER_TAS2563 1
+		option AUDIO_AMPLIFIER_ALC5645 2
+	end
+end
+
+chip soc/mediatek/mt8196
+	device domain 0 on
+	end
+end
diff --git a/src/mainboard/google/rauru/variants/navi/fw_config.c b/src/mainboard/google/rauru/variants/navi/fw_config.c
index 50f5df9903..55d16e763e 100644
--- a/src/mainboard/google/rauru/variants/navi/fw_config.c
+++ b/src/mainboard/google/rauru/variants/navi/fw_config.c
@@ -9,3 +9,14 @@ void fw_config_panel_override(struct panel_description *panel)
 	if (fw_config_probe(FW_CONFIG(OLED_WQXGA_PLUS, PRESENT)))
 		panel->quirks |= PANEL_QUIRK_FORCE_MAX_SWING;
 }
+
+enum audio_amplifier_id get_audio_amp_id(void)
+{
+	if (fw_config_probe(FW_CONFIG(AUDIO_AMPLIFIER, AUDIO_AMPLIFIER_TAS2563)))
+		return AUD_AMP_ID_TAS2563;
+
+	if (fw_config_probe(FW_CONFIG(AUDIO_AMPLIFIER, AUDIO_AMPLIFIER_ALC5645)))
+		return AUD_AMP_ID_ALC5645;
+
+	return AUD_AMP_ID_NAU8318;
+}
diff --git a/src/mainboard/google/rauru/variants/navi/overridetree.cb b/src/mainboard/google/rauru/variants/navi/overridetree.cb
index cbc5e29713..0f7e24f908 100644
--- a/src/mainboard/google/rauru/variants/navi/overridetree.cb
+++ b/src/mainboard/google/rauru/variants/navi/overridetree.cb
@@ -5,6 +5,11 @@ fw_config
 		option PRESENT	1
 		option ABSENT	0
 	end
+	field AUDIO_AMPLIFIER 28 29
+		option AUDIO_AMPLIFIER_NAU8318 0
+		option AUDIO_AMPLIFIER_TAS2563 1
+		option AUDIO_AMPLIFIER_ALC5645 2
+	end
 end
 
 chip soc/mediatek/mt8196
diff --git a/src/mainboard/google/rauru/variants/rauru/Makefile.mk b/src/mainboard/google/rauru/variants/rauru/Makefile.mk
new file mode 100644
index 0000000000..52fd109576
--- /dev/null
+++ b/src/mainboard/google/rauru/variants/rauru/Makefile.mk
@@ -0,0 +1,3 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
+ramstage-y += fw_config.c
diff --git a/src/mainboard/google/rauru/variants/rauru/fw_config.c b/src/mainboard/google/rauru/variants/rauru/fw_config.c
new file mode 100644
index 0000000000..4332c97c62
--- /dev/null
+++ b/src/mainboard/google/rauru/variants/rauru/fw_config.c
@@ -0,0 +1,15 @@
+/* SPDX-License-Identifier: GPL-2.0-only OR MIT */
+
+#include <fw_config.h>
+#include <variants.h>
+
+enum audio_amplifier_id get_audio_amp_id(void)
+{
+	if (fw_config_probe(FW_CONFIG(AUDIO_AMPLIFIER, AUDIO_AMPLIFIER_TAS2563)))
+		return AUD_AMP_ID_TAS2563;
+
+	if (fw_config_probe(FW_CONFIG(AUDIO_AMPLIFIER, AUDIO_AMPLIFIER_ALC5645)))
+		return AUD_AMP_ID_ALC5645;
+
+	return AUD_AMP_ID_NAU8318;
+}
diff --git a/src/mainboard/google/rauru/variants/rauru/overridetree.cb b/src/mainboard/google/rauru/variants/rauru/overridetree.cb
new file mode 100644
index 0000000000..d3cc60d31b
--- /dev/null
+++ b/src/mainboard/google/rauru/variants/rauru/overridetree.cb
@@ -0,0 +1,14 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
+fw_config
+	field AUDIO_AMPLIFIER 28 29
+		option AUDIO_AMPLIFIER_NAU8318 0
+		option AUDIO_AMPLIFIER_TAS2563 1
+		option AUDIO_AMPLIFIER_ALC5645 2
+	end
+end
+
+chip soc/mediatek/mt8196
+	device domain 0 on
+	end
+end
diff --git a/src/mainboard/google/rauru/variants/sapphire/Makefile.mk b/src/mainboard/google/rauru/variants/sapphire/Makefile.mk
new file mode 100644
index 0000000000..52fd109576
--- /dev/null
+++ b/src/mainboard/google/rauru/variants/sapphire/Makefile.mk
@@ -0,0 +1,3 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
+ramstage-y += fw_config.c
diff --git a/src/mainboard/google/rauru/variants/sapphire/fw_config.c b/src/mainboard/google/rauru/variants/sapphire/fw_config.c
new file mode 100644
index 0000000000..c5a1b6a0f8
--- /dev/null
+++ b/src/mainboard/google/rauru/variants/sapphire/fw_config.c
@@ -0,0 +1,12 @@
+/* SPDX-License-Identifier: GPL-2.0-only OR MIT */
+
+#include <fw_config.h>
+#include <variants.h>
+
+enum audio_amplifier_id get_audio_amp_id(void)
+{
+	if (fw_config_probe(FW_CONFIG(AUDIO_AMPLIFIER, AUDIO_AMPLIFIER_TAS2563)))
+		return AUD_AMP_ID_TAS2563;
+
+	return AUD_AMP_ID_UNKNOWN;
+}
diff --git a/src/mainboard/google/rauru/variants/sapphire/overridetree.cb b/src/mainboard/google/rauru/variants/sapphire/overridetree.cb
new file mode 100644
index 0000000000..5c70580d8d
--- /dev/null
+++ b/src/mainboard/google/rauru/variants/sapphire/overridetree.cb
@@ -0,0 +1,41 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
+fw_config
+	field AUDIO_CODEC 0 2
+		option AUDIO_CODEC_UNKNOWN	0
+		option AUDIO_CODEC_ALC5682IVS	1
+	end
+	field AUDIO_AMPLIFIER 3 5
+		option AUDIO_AMPLIFIER_UNKNOWN	0
+		option AUDIO_AMPLIFIER_TAS2563	1
+	end
+	field STORAGE_TYPE 12 14
+		option STORAGE_TYPE_UNKNOWN	0
+		option STORAGE_TYPE_UFS_40	1
+	end
+	field FINGERPRINT_INTERFACE 24 25
+		option FINGERPRINT_INTERFACE_UNKNOWN	0
+		option FINGERPRINT_INTERFACE_USB	1
+	end
+	field WIFI_INTERFACE 26 27
+		option WIFI_INTERFACE_UNKNOWN	0
+		option WIFI_INTERFACE_PCIE	1
+	end
+	field FORM_FACTOR 30 31
+		option FORM_FACTOR_UNKNOWN	0
+		option FORM_FACTOR_DETACHABLE	1
+	end
+	field PANEL_ID 39 42
+		option PANEL_ID_NS130070_M00	9
+		option PANEL_ID_UNKNOWN		15
+	end
+	field STYLUS 48 48
+		option STYLUS_PRESENT_ABSENT	0
+		option STYLUS_PRESENT_PRESENT	1
+	end
+end
+
+chip soc/mediatek/mt8196
+	device domain 0 on
+	end
+end

From c11faad2bf918835d349f076af742ab81e5ddfad Mon Sep 17 00:00:00 2001
From: Yu-Ping Wu <yupingso@chromium.org>
Date: Mon, 8 Dec 2025 15:33:43 +0800
Subject: [PATCH 2740/3886] mb/google/skywalker: Correct MIPI panel power
 sequence

Unlike other skywalker boards, GPIO14 is EN_PP6000_MIPI_DISP instead of
TCHSCR_REPORT_DISABLE on Padme. Therefore, in bootblock that GPIO should
be initialized low to meet the MIPI panel's required power-on sequence.
More precisely, IOVCC (LCD_VDDI) must lead AVDD by >2ms [1].

Add alias GPIO_EN_PP6000_MIPI_DISP to skywalker/gpio.h, and use it
instead of GPIO_TCHSCR_REPORT_DISABLE in the MIPI initialization code.
Also remove the EN_PP6000_MIPI_DISP pull-low in mipi_panel_power_on(),
as it has been pulled low in setup_chromeos_gpios().

[1] Preliminary+specification+TL121BVMS07+-00+V01+20250721.pdf

BUG=b:451746079
TEST=Boot Padme and confirm panel power-on timing is correct.
BRANCH=skywalker

Change-Id: I748a998cde35e58eac9eb590171b79864fc58ea9
Signed-off-by: Yang Wu <wuyang5@huaqin.corp-partner.google.com>
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90122
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Chen-Tsung Hsieh <chentsung@chromium.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
---
 src/mainboard/google/skywalker/chromeos.c | 5 ++++-
 src/mainboard/google/skywalker/gpio.h     | 3 +++
 src/mainboard/google/skywalker/panel.c    | 4 +---
 3 files changed, 8 insertions(+), 4 deletions(-)

diff --git a/src/mainboard/google/skywalker/chromeos.c b/src/mainboard/google/skywalker/chromeos.c
index d7494bb1bc..eace485648 100644
--- a/src/mainboard/google/skywalker/chromeos.c
+++ b/src/mainboard/google/skywalker/chromeos.c
@@ -32,7 +32,10 @@ void setup_chromeos_gpios(void)
 	gpio_output(GPIO_WWAN_RESET_L, 0);
 	gpio_output(GPIO_EN_PWR_FP, 0);
 	gpio_output(GPIO_EDP_BL_EN_1V8, 0);
-	gpio_output(GPIO_TCHSCR_REPORT_DISABLE, 1);
+	if (CONFIG(BOARD_GOOGLE_PADME))
+		gpio_output(GPIO_EN_PP6000_MIPI_DISP, 0);
+	else
+		gpio_output(GPIO_TCHSCR_REPORT_DISABLE, 1);
 	gpio_output(GPIO_CODEC_PWR_SOC_EN, 0);
 	gpio_output(GPIO_EN_PP3300_EDP_X, 0);
 	gpio_output(GPIO_EN_PP3300_WWAN_X, 0);
diff --git a/src/mainboard/google/skywalker/gpio.h b/src/mainboard/google/skywalker/gpio.h
index 58315677a2..68bd78e967 100644
--- a/src/mainboard/google/skywalker/gpio.h
+++ b/src/mainboard/google/skywalker/gpio.h
@@ -19,7 +19,10 @@
 #define GPIO_PEN_EJECT_OD			GPIO(GPIO11)
 #define GPIO_EN_PWR_FP				GPIO(GPIO12)
 #define GPIO_EDP_BL_EN_1V8			GPIO(GPIO13)
+/* For !BOARD_GOOGLE_PADME */
 #define GPIO_TCHSCR_REPORT_DISABLE		GPIO(GPIO14)
+/* For BOARD_GOOGLE_PADME */
+#define GPIO_EN_PP6000_MIPI_DISP		GPIO(GPIO14)
 #define GPIO_TCHSCR_INT_1V8_ODL			GPIO(GPIO15)
 #define GPIO_AP_WP_ODL				GPIO(GPIO16)
 #define GPIO_EC_AP_DPOC_EN_ODL			GPIO(GPIO17)
diff --git a/src/mainboard/google/skywalker/panel.c b/src/mainboard/google/skywalker/panel.c
index bd4ef3374f..32d684217e 100644
--- a/src/mainboard/google/skywalker/panel.c
+++ b/src/mainboard/google/skywalker/panel.c
@@ -44,10 +44,8 @@ void mipi_panel_power_on(void)
 {
 	struct aw37503_config config = {
 		.i2c_bus = PMIC_I2C_BUS,
-		.en = GPIO_TCHSCR_REPORT_DISABLE,
+		.en = GPIO_EN_PP6000_MIPI_DISP,
 	};
-	gpio_output(config.en, 0);
-	mdelay(1);
 
 	mainboard_set_regulator_voltage(MTK_REGULATOR_VCN18, 1800000);
 	mtk_i2c_bus_init(config.i2c_bus, I2C_SPEED_FAST);

From 41348477e3aaad93dd9e85b7846f984c73875e8f Mon Sep 17 00:00:00 2001
From: Sergii Dmytruk <sergii.dmytruk@3mdeb.com>
Date: Tue, 9 Dec 2025 00:48:13 +0200
Subject: [PATCH 2741/3886] sb/intel/common/firmware/Makefile.mk: fix
 INTEL_IFD_SET_TOP_SWAP_BOOTBLOCK_SIZE

Halfway through the review of CB:89493 (commit 6e4501661095 ("intel
soc,southbridge: Add Kconfig to set TSBS in IFD during build")) the
option was renamed and lost "CONFIG_" prefix in the Makefile.  Add the
missing prefix.

The omission was discovered and the fix tested while trying to use this
option on Protectli VP6670 where incorrect Top Swap size prevented a
boot.

Adding a missing space while at it.

Change-Id: Ie85fc0b81b2231760878306cf065598bec390e9f
Signed-off-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90432
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/southbridge/intel/common/firmware/Makefile.mk | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/southbridge/intel/common/firmware/Makefile.mk b/src/southbridge/intel/common/firmware/Makefile.mk
index 41ccca41d9..3c7ad906e6 100644
--- a/src/southbridge/intel/common/firmware/Makefile.mk
+++ b/src/southbridge/intel/common/firmware/Makefile.mk
@@ -47,7 +47,7 @@ ifeq ($(CONFIG_HAVE_EC_BIN),y)
 add_intel_firmware: $(call strip_quotes,$(CONFIG_EC_BIN_PATH))
 endif
 add_intel_firmware: $(obj)/coreboot.pre $(IFDTOOL)
-ifeq ($(INTEL_IFD_SET_TOP_SWAP_BOOTBLOCK_SIZE),y)
+ifeq ($(CONFIG_INTEL_IFD_SET_TOP_SWAP_BOOTBLOCK_SIZE),y)
 	printf "    IFDTOOL    Modifying top swap PCH strap in IFD\n"
 	printf "     $(IFDTOOL_USE_CHIPSET)"
 	$(objutil)/ifdtool/ifdtool \
@@ -56,7 +56,7 @@ ifeq ($(INTEL_IFD_SET_TOP_SWAP_BOOTBLOCK_SIZE),y)
 		-O $(obj)/ifd_custom_tsbs \
 		$(IFD_BIN_PATH)
 	printf "    DD         Adding Intel Firmware Descriptor\n"
-	dd if=$(obj)/ifd_custom_tsbs\
+	dd if=$(obj)/ifd_custom_tsbs \
 		of=$(obj)/coreboot.pre conv=notrunc >/dev/null 2>&1
 else
 	printf "    DD         Adding Intel Firmware Descriptor\n"

From 8795680828f108f2c8f6e650e55643ee88dc807e Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Micha=C5=82=20=C5=BBygowski?= <michal.zygowski@3mdeb.com>
Date: Fri, 24 Oct 2025 13:22:24 +0200
Subject: [PATCH 2742/3886] cpu/x86/lapic/lapic.c: Set spurious interrupt
 vector to 0xF
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

The MP Specification v1.4 says to program the spurious interrupt
in the following way:

"The APIC spurious interrupt must point to a vector whose lower
nibble is 0F, that is 0xF, where x is 0 - F. Here we use Int 00FH,
which handles spurious interrupts and supplies the necessary IRET.
This vector is assumed to have already been initialized in memory."

Follow the requirement and set the spurious interrupt vector
to 0x0F. This is what reference implementations, like EDK2, and also
BIOS vendors do.

Change-Id: I7bde413bbadca1de0079daf52b5501ba6638a4c3
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89736
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
---
 src/cpu/x86/lapic/lapic.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/cpu/x86/lapic/lapic.c b/src/cpu/x86/lapic/lapic.c
index 6afd6c56ea..2d47d3e95f 100644
--- a/src/cpu/x86/lapic/lapic.c
+++ b/src/cpu/x86/lapic/lapic.c
@@ -76,9 +76,9 @@ void setup_lapic_interrupts(void)
 	 */
 	lapic_update32(LAPIC_TASKPRI, ~LAPIC_TPRI_MASK, 0);
 
-	/* Set spurious interrupt vector to 0 and keep LAPIC enabled to
+	/* Set spurious interrupt vector to 0xF and keep LAPIC enabled to
 	   be able to clear LVT register mask bits. */
-	lapic_update32(LAPIC_SPIV, ~LAPIC_VECTOR_MASK, LAPIC_SPIV_ENABLE);
+	lapic_update32(LAPIC_SPIV, ~LAPIC_VECTOR_MASK, LAPIC_SPIV_ENABLE | 0xF);
 
 	/* Put the local APIC in virtual wire mode */
 	uint32_t mask = LAPIC_LVT_MASKED | LAPIC_LVT_LEVEL_TRIGGER | LAPIC_INPUT_POLARITY |

From 4f52ca6ba666dbebc7cc4e299d7b49796ac297d8 Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Sat, 29 Nov 2025 20:37:06 +0000
Subject: [PATCH 2743/3886] soc/intel/common/cse: Return usable error codes
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Currently, cse_request_reset() returns 0 if the reset type is
unsupported or CSE isn’t ready. This is the same as
CSE_TX_RX_SUCCESS, which makes failures impossible to detect.

Return CSE_TX_ERR_INPUT or CSE_TX_ERR_CSE_NOT_READY respectively,
so we can detect errors.

Change-Id: Idede7342157901946ba62ba6fcda6f304a4a3fd0
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90272
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
---
 src/soc/intel/common/block/cse/cse.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/soc/intel/common/block/cse/cse.c b/src/soc/intel/common/block/cse/cse.c
index 1f519312ce..d02bb85b37 100644
--- a/src/soc/intel/common/block/cse/cse.c
+++ b/src/soc/intel/common/block/cse/cse.c
@@ -737,12 +737,12 @@ static int cse_request_reset(enum rst_req_type rst_type)
 
 	if (!(rst_type == GLOBAL_RESET || rst_type == CSE_RESET_ONLY)) {
 		printk(BIOS_ERR, "HECI: Unsupported reset type is requested\n");
-		return 0;
+		return CSE_TX_ERR_INPUT;
 	}
 
 	if (!cse_is_global_reset_allowed() || !is_cse_enabled()) {
 		printk(BIOS_ERR, "HECI: CSE does not meet required prerequisites\n");
-		return 0;
+		return CSE_TX_ERR_CSE_NOT_READY;
 	}
 
 	heci_reset();

From 84a4cdc6a533dc909a25fde25d99dca13ad2d28c Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Sat, 29 Nov 2025 20:41:03 +0000
Subject: [PATCH 2744/3886] soc/intel/*: Only skip PMC fallback on successful
 CSE reset

cse_request_global_reset() returns CSE_TX_RX_SUCCESS on success. Make
do_global_reset() explicatly check for that, and fall back CF9 for any
other value.

Test=Disable and enable the Intel ME on starbook_mtl and verify the
system actually resets, rather than hanging.

Change-Id: I4c3fb7995bca8e7fe3793b9aee021e4004ace933
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90273
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
---
 src/soc/intel/alderlake/reset.c   | 2 +-
 src/soc/intel/cannonlake/reset.c  | 2 +-
 src/soc/intel/elkhartlake/reset.c | 2 +-
 src/soc/intel/jasperlake/reset.c  | 2 +-
 src/soc/intel/meteorlake/reset.c  | 2 +-
 src/soc/intel/pantherlake/reset.c | 2 +-
 src/soc/intel/tigerlake/reset.c   | 2 +-
 src/soc/intel/xeon_sp/spr/reset.c | 2 +-
 8 files changed, 8 insertions(+), 8 deletions(-)

diff --git a/src/soc/intel/alderlake/reset.c b/src/soc/intel/alderlake/reset.c
index bc5815ac7a..3c13f6dfe5 100644
--- a/src/soc/intel/alderlake/reset.c
+++ b/src/soc/intel/alderlake/reset.c
@@ -8,7 +8,7 @@
 void do_global_reset(void)
 {
 	/* Ask CSE to do the global reset */
-	if (cse_request_global_reset())
+	if (cse_request_global_reset() == CSE_TX_RX_SUCCESS)
 		return;
 
 	/* global reset if CSE fail to reset */
diff --git a/src/soc/intel/cannonlake/reset.c b/src/soc/intel/cannonlake/reset.c
index bc5815ac7a..3c13f6dfe5 100644
--- a/src/soc/intel/cannonlake/reset.c
+++ b/src/soc/intel/cannonlake/reset.c
@@ -8,7 +8,7 @@
 void do_global_reset(void)
 {
 	/* Ask CSE to do the global reset */
-	if (cse_request_global_reset())
+	if (cse_request_global_reset() == CSE_TX_RX_SUCCESS)
 		return;
 
 	/* global reset if CSE fail to reset */
diff --git a/src/soc/intel/elkhartlake/reset.c b/src/soc/intel/elkhartlake/reset.c
index bc5815ac7a..3c13f6dfe5 100644
--- a/src/soc/intel/elkhartlake/reset.c
+++ b/src/soc/intel/elkhartlake/reset.c
@@ -8,7 +8,7 @@
 void do_global_reset(void)
 {
 	/* Ask CSE to do the global reset */
-	if (cse_request_global_reset())
+	if (cse_request_global_reset() == CSE_TX_RX_SUCCESS)
 		return;
 
 	/* global reset if CSE fail to reset */
diff --git a/src/soc/intel/jasperlake/reset.c b/src/soc/intel/jasperlake/reset.c
index bc5815ac7a..3c13f6dfe5 100644
--- a/src/soc/intel/jasperlake/reset.c
+++ b/src/soc/intel/jasperlake/reset.c
@@ -8,7 +8,7 @@
 void do_global_reset(void)
 {
 	/* Ask CSE to do the global reset */
-	if (cse_request_global_reset())
+	if (cse_request_global_reset() == CSE_TX_RX_SUCCESS)
 		return;
 
 	/* global reset if CSE fail to reset */
diff --git a/src/soc/intel/meteorlake/reset.c b/src/soc/intel/meteorlake/reset.c
index bc5815ac7a..3c13f6dfe5 100644
--- a/src/soc/intel/meteorlake/reset.c
+++ b/src/soc/intel/meteorlake/reset.c
@@ -8,7 +8,7 @@
 void do_global_reset(void)
 {
 	/* Ask CSE to do the global reset */
-	if (cse_request_global_reset())
+	if (cse_request_global_reset() == CSE_TX_RX_SUCCESS)
 		return;
 
 	/* global reset if CSE fail to reset */
diff --git a/src/soc/intel/pantherlake/reset.c b/src/soc/intel/pantherlake/reset.c
index bc5815ac7a..3c13f6dfe5 100644
--- a/src/soc/intel/pantherlake/reset.c
+++ b/src/soc/intel/pantherlake/reset.c
@@ -8,7 +8,7 @@
 void do_global_reset(void)
 {
 	/* Ask CSE to do the global reset */
-	if (cse_request_global_reset())
+	if (cse_request_global_reset() == CSE_TX_RX_SUCCESS)
 		return;
 
 	/* global reset if CSE fail to reset */
diff --git a/src/soc/intel/tigerlake/reset.c b/src/soc/intel/tigerlake/reset.c
index bc5815ac7a..3c13f6dfe5 100644
--- a/src/soc/intel/tigerlake/reset.c
+++ b/src/soc/intel/tigerlake/reset.c
@@ -8,7 +8,7 @@
 void do_global_reset(void)
 {
 	/* Ask CSE to do the global reset */
-	if (cse_request_global_reset())
+	if (cse_request_global_reset() == CSE_TX_RX_SUCCESS)
 		return;
 
 	/* global reset if CSE fail to reset */
diff --git a/src/soc/intel/xeon_sp/spr/reset.c b/src/soc/intel/xeon_sp/spr/reset.c
index bc5815ac7a..3c13f6dfe5 100644
--- a/src/soc/intel/xeon_sp/spr/reset.c
+++ b/src/soc/intel/xeon_sp/spr/reset.c
@@ -8,7 +8,7 @@
 void do_global_reset(void)
 {
 	/* Ask CSE to do the global reset */
-	if (cse_request_global_reset())
+	if (cse_request_global_reset() == CSE_TX_RX_SUCCESS)
 		return;
 
 	/* global reset if CSE fail to reset */

From 5eaf85d19b0d5bf19c3be576ad7d665dc2ce1671 Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Sat, 29 Nov 2025 20:43:22 +0000
Subject: [PATCH 2745/3886] soc/intel/skylake: Use CSE reset status for reset
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

send_global_reset() now returns cse_tx_rx_status, and  skips the
CF9 reset only when CSE reports CSE_TX_RX_SUCCESS.

Test=Disable and enable the Intel ME on labtop_kbl and verify the
system actually resets, rather than hanging.

Change-Id: I5003ea9486a383ee7a4cace20ce6a54b0f94a166
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90274
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
---
 src/soc/intel/skylake/include/soc/me.h | 4 +++-
 src/soc/intel/skylake/me.c             | 4 ++--
 src/soc/intel/skylake/reset.c          | 2 +-
 3 files changed, 6 insertions(+), 4 deletions(-)

diff --git a/src/soc/intel/skylake/include/soc/me.h b/src/soc/intel/skylake/include/soc/me.h
index ffeb2f055a..2e16a322c5 100644
--- a/src/soc/intel/skylake/include/soc/me.h
+++ b/src/soc/intel/skylake/include/soc/me.h
@@ -3,6 +3,8 @@
 #ifndef _SKYLAKE_ME_H_
 #define _SKYLAKE_ME_H_
 
+#include <intelblocks/cse.h>
+
 /*
  * Management Engine PCI registers
  */
@@ -189,6 +191,6 @@ union me_hfsts6 {
 };
 
 void intel_me_status(void);
-int send_global_reset(void);
+enum cse_tx_rx_status send_global_reset(void);
 
 #endif
diff --git a/src/soc/intel/skylake/me.c b/src/soc/intel/skylake/me.c
index 89491f89c3..e91719f00c 100644
--- a/src/soc/intel/skylake/me.c
+++ b/src/soc/intel/skylake/me.c
@@ -338,9 +338,9 @@ void intel_me_status(void)
 	}
 }
 
-int send_global_reset(void)
+enum cse_tx_rx_status send_global_reset(void)
 {
-	int status = 0;
+	enum cse_tx_rx_status status = CSE_TX_ERR_CSE_NOT_READY;
 	union me_hfsts1 hfs1;
 
 	if (!is_cse_enabled())
diff --git a/src/soc/intel/skylake/reset.c b/src/soc/intel/skylake/reset.c
index 8bf9db5830..3ef5f09354 100644
--- a/src/soc/intel/skylake/reset.c
+++ b/src/soc/intel/skylake/reset.c
@@ -22,7 +22,7 @@ static void do_force_global_reset(void)
 
 void do_global_reset(void)
 {
-	if (!send_global_reset()) {
+	if (send_global_reset() != CSE_TX_RX_SUCCESS) {
 		/* If ME unable to reset platform then
 		 * force global reset using PMC CF9GR register*/
 		do_force_global_reset();

From 9a95aef482d31676cec45d3c23e20e2c6732d10e Mon Sep 17 00:00:00 2001
From: Swathi Tamilselvan <tswathi@qualcomm.corp-partner.google.com>
Date: Thu, 4 Dec 2025 12:14:09 +0530
Subject: [PATCH 2746/3886] soc/qualcomm/common: Add API to enable Lucidole PLL
 for X1P42100

Add API to enable Lucidole PLL.

TEST=Create an image.serial.bin and ensure it boots on X1P42100.

Change-Id: Idfefebcbe57498446e32c75d5c1532d321b8fb74
Signed-off-by: Swathi Tamilselvan <tswathi@qualcomm.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90392
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/soc/qualcomm/common/clock.c               | 20 +++++++++++++++++++
 .../common/include/soc/clock_common.h         |  2 ++
 2 files changed, 22 insertions(+)

diff --git a/src/soc/qualcomm/common/clock.c b/src/soc/qualcomm/common/clock.c
index 200e16e5c7..ede523e298 100644
--- a/src/soc/qualcomm/common/clock.c
+++ b/src/soc/qualcomm/common/clock.c
@@ -302,6 +302,26 @@ enum cb_err zondaole_pll_enable(struct alpha_pll_reg_val_config *cfg)
 	return CB_SUCCESS;
 }
 
+enum cb_err lucidole_pll_enable(struct alpha_pll_reg_val_config *cfg)
+{
+	/*
+	 * H/W requires a 1us delay between disabling the bypass and
+	 * de-asserting the reset.
+	 */
+	udelay(1);
+	setbits32(cfg->reg_opmode, PLL_RUN_MODE);
+	setbits32(cfg->reg_mode, BIT(PLL_RESET_SHFT));
+
+	if (!wait_us(100, read32(cfg->reg_mode) & PLL_LOCK_DET_BMSK)) {
+		printk(BIOS_ERR, "CPU PLL did not lock!\n");
+		return CB_ERR;
+	}
+
+	setbits32(cfg->reg_mode, BIT(PLL_OUTCTRL_SHFT));
+
+	return CB_SUCCESS;
+}
+
 /* Bring subsystem out of RESET */
 void clock_reset_subsystem(u32 *misc, u32 shft)
 {
diff --git a/src/soc/qualcomm/common/include/soc/clock_common.h b/src/soc/qualcomm/common/include/soc/clock_common.h
index f638ce00e6..fd3a073d01 100644
--- a/src/soc/qualcomm/common/include/soc/clock_common.h
+++ b/src/soc/qualcomm/common/include/soc/clock_common.h
@@ -182,6 +182,8 @@ enum cb_err agera_pll_enable(struct alpha_pll_reg_val_config *cfg);
 
 enum cb_err zonda_pll_enable(struct alpha_pll_reg_val_config *cfg);
 
+enum cb_err lucidole_pll_enable(struct alpha_pll_reg_val_config *cfg);
+
 /*
  * zondaole_pll_enable(): Enable Zondaole PLL at the given configuration (cfg).
  *

From 6957f84aa77b85feb9232a72e93a87d2d929b3e2 Mon Sep 17 00:00:00 2001
From: Swathi Tamilselvan <tswathi@qualcomm.corp-partner.google.com>
Date: Thu, 4 Dec 2025 12:19:51 +0530
Subject: [PATCH 2747/3886] soc/qualcomm/x1p42100: Define MDSS domain registers
 for display clock enablement

Add register address and clock value definitions required to enable
the display clock. The register details are part of HRD-X1P42100-S1
document.
https://docs.qualcomm.com/bundle/resource/topics/HRD-X1P42100-S1/

TEST=Generated image.serial.bin and verified boot on X1P42100.
Validated only basic device boot functionality, as clock enablement API
and its invocation sequence from display driver are not yet implemented.

Change-Id: Id23dd12c9c1ee4968546c8b928f9360163446a9d
Signed-off-by: Swathi Tamilselvan <tswathi@qualcomm.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90393
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
---
 .../x1p42100/include/soc/addressmap.h         |   4 +
 src/soc/qualcomm/x1p42100/include/soc/clock.h | 205 ++++++++++++++----
 2 files changed, 169 insertions(+), 40 deletions(-)

diff --git a/src/soc/qualcomm/x1p42100/include/soc/addressmap.h b/src/soc/qualcomm/x1p42100/include/soc/addressmap.h
index 11b6f794af..1c309a06d4 100644
--- a/src/soc/qualcomm/x1p42100/include/soc/addressmap.h
+++ b/src/soc/qualcomm/x1p42100/include/soc/addressmap.h
@@ -14,6 +14,9 @@
 #define GCC_QUPV3_WRAP0_BASE		0x142004
 #define GCC_QUPV3_WRAP1_BASE		0x118004
 #define GCC_QUPV3_WRAP2_BASE		0x11e004
+#define DISP_PLL0_BASE			0xAF00000
+#define DISP_PLL1_BASE			0xAF01000
+#define DISP_CC_BASE			0xAF08000
 
 #define CBMEM_TOP			0xC7800000
 /* X1P42100 NCC0 PLL CONFIG ADDRESSES */
@@ -175,6 +178,7 @@
 #define TCSR_GCC_USB2_1_CLKREF_EN_ADDR		((void *)0x1FD5114)
 #define TCSR_GCC_USB4_2_CLKREF_EN_ADDR		((void *)0x1FD5124)
 #define TCSR_GCC_USB2_2_CLKREF_EN_ADDR		((void *)0x1FD5118)
+#define TCSR_GCC_EDP_CLKREF_EN_ADDR		((void *)0x1FD5130)
 #define USB_CLKREF_ENABLE_VALUE			0x1
 
 /* TCSR Boot Misc Detect Register for Download Mode */
diff --git a/src/soc/qualcomm/x1p42100/include/soc/clock.h b/src/soc/qualcomm/x1p42100/include/soc/clock.h
index a0a6eae8a0..da082f66bd 100644
--- a/src/soc/qualcomm/x1p42100/include/soc/clock.h
+++ b/src/soc/qualcomm/x1p42100/include/soc/clock.h
@@ -13,10 +13,19 @@
 #define GPLL0_MAIN_HZ		(600 * MHz)
 #define CLK_100MHZ		(100 * MHz)
 #define CLK_200MHZ		(200 * MHz)
+#define CLK_400MHZ		(400 * MHz)
+#define CLK_75MHZ		(75 * MHz)
+#define CLK_575MHZ		(575 * MHz)
 
 /* CPU PLL*/
 #define L_VAL_1363P2MHz		0x47
 
+/* DISP PLL */
+#define L_VAL_1725MHz		0x59
+#define L_VAL_600MHz		0x1F
+#define DISP_PLL0_ALPHA_VAL	0xD800
+#define DISP_PLL1_ALPHA_VAL	0x4000
+
 #define PCIE_PHY_RCHNG_FREQ CLK_100MHZ
 #define USB3_MASTER_CLK_MIN_FREQ_HZ CLK_200MHZ
 
@@ -59,6 +68,21 @@ enum clk_pll_src {
 	SRC_GPLL0_EVEN_300MHZ = 6,
 };
 
+enum disp_cc_mdss_ahb_clk_src {
+	SRC_XO_19_2MHZ_AHB = 0,
+	SRC_DISP_CC_PLL1_MAIN_AHB = 4,
+	SRC_DISP_CC_PLL1_EVEN_AHB = 6,
+	SRC_CORE_BI_PLL_TEST_SE_AHB = 7,
+};
+
+enum disp_cc_mdss_mdp_clk_src {
+	SRC_XO_19_2MHZ_MDP = 0,
+	SRC_DISP_CC_PLL0_MAIN_MDP = 1,
+	SRC_DISP_CC_PLL1_MAIN_MDP = 4,
+	SRC_DISP_CC_PLL1_EVEN_MDP = 6,
+	SRC_CORE_BI_PLL_TEST_SE_MDP = 7,
+};
+
 enum apcs_branch_en_vote {
 	QUPV3_WRAP_0_M_AHB_CLK_ENA = 6,
 	QUPV3_WRAP_0_S_AHB_CLK_ENA = 7,
@@ -157,6 +181,72 @@ struct x1p42100_ncc0_clock {
 	u32 pll0_opmode;
 };
 
+struct x1p42100_disp_pll_clock {
+	u32 pll_mode;
+	u32 pll_opmode;
+	u32 pll_state;
+	u32 pll_status;
+	u32 pll_l;
+	u32 pll_alpha;
+	u32 pll_user_ctl;
+	u32 pll_user_ctl_u;
+};
+
+struct x1p42100_disp_cc {
+	uint8_t _res0[0x00C];
+	uint32_t mdss_mdp_cbcr;
+	uint8_t _res1[0x014];
+	uint32_t mdss_vsync_cbcr;
+	uint8_t _res2[0x06C];
+	uint32_t mdss_dptx3_pixel0_cbcr;
+	uint32_t mdss_dptx3_link_cbcr;
+	uint32_t mdss_dptx3_link_intf_cbcr;
+	uint32_t mdss_dptx3_aux_cbcr;
+	uint8_t _res3[0x004];
+	uint32_t mdss_ahb_cbcr;
+	uint8_t _res4[0x030];
+	struct clock_rcg mdss_mdp_rcg;
+	uint8_t _res5[0x010];
+	struct clock_rcg mdss_vsync_rcg;
+	uint8_t _res6[0x1A4];
+	struct clock_rcg mdss_dptx3_pixel0_rcg;
+	uint8_t _res7[0x010];
+	struct clock_rcg mdss_dptx3_link_rcg;
+	uint8_t _res8[0x014];
+	struct clock_rcg mdss_dptx3_aux_rcg;
+	uint8_t _res9[0x010];
+	struct clock_rcg mdss_ahb_rcg;
+	uint8_t  _res10[0x0D0C];
+	uint32_t mdss_core_gdscr;
+	uint8_t  _res11[0x3004];
+	uint32_t mdss_rscc_vsync_cbcr;
+	uint32_t mdss_rscc_ahb_cbcr;
+	uint8_t _res12[0x202C];
+	struct clock_rcg xo_rcg;
+	uint8_t _res13[0x010];
+	uint32_t xo_cbcr;
+};
+
+/* Offset checks (relative to DISP_CC_BASE) */
+check_member(x1p42100_disp_cc, mdss_mdp_cbcr,		0x00000C);
+check_member(x1p42100_disp_cc, mdss_vsync_cbcr,		0x000024);
+check_member(x1p42100_disp_cc, mdss_dptx3_pixel0_cbcr,	0x000094);
+check_member(x1p42100_disp_cc, mdss_dptx3_link_cbcr,	0x000098);
+check_member(x1p42100_disp_cc, mdss_dptx3_link_intf_cbcr,	0x00009C);
+check_member(x1p42100_disp_cc, mdss_dptx3_aux_cbcr,	0x0000A0);
+check_member(x1p42100_disp_cc, mdss_ahb_cbcr,		0x0000A8);
+check_member(x1p42100_disp_cc, mdss_mdp_rcg,		0x0000DC);
+check_member(x1p42100_disp_cc, mdss_vsync_rcg,		0x0000F4);
+check_member(x1p42100_disp_cc, mdss_dptx3_pixel0_rcg,	0x0002A0);
+check_member(x1p42100_disp_cc, mdss_dptx3_link_rcg,	0x0002B8);
+check_member(x1p42100_disp_cc, mdss_dptx3_aux_rcg,	0x0002D4);
+check_member(x1p42100_disp_cc, mdss_ahb_rcg,		0x0002EC);
+check_member(x1p42100_disp_cc, mdss_core_gdscr,	0x0001000);
+check_member(x1p42100_disp_cc, mdss_rscc_vsync_cbcr,	0x0004008);
+check_member(x1p42100_disp_cc, mdss_rscc_ahb_cbcr,	0x000400C);
+check_member(x1p42100_disp_cc, xo_rcg,			0x000603C);
+check_member(x1p42100_disp_cc, xo_cbcr,		0x0006054);
+
 struct x1p42100_pcie_noc {
 	u32 anoc_pcie_at_cbcr;
 	u32 anoc_pcie_tsctr_cbcr;
@@ -278,119 +368,125 @@ struct x1p42100_gcc {
 	u32 qup_wrap2_core_2x_cbcr;
 	u8 _res19[0x232c4 - 0x232bc];
 	struct clock_rcg qup_wrap2_core_2x;
-	u8 _res20[0x2a000 - 0x232cc];
+	u8 _res20[0x27004 - 0x232cc];
+	u32 gcc_disp_ahb_cbcr;
+	u8 _res21[0x2700c - 0x27008];
+	u32 gcc_disp_hf_axi_cbcr;
+	u8 _res22[0x27018 - 0x27010];
+	u32 gcc_disp_xo_cbcr;
+	u8 _res23[0x2a000 - 0x2701c];
 	u32 gcc_usb3_phy_sec_bcr;
 	u32 gcc_usb3phy_phy_sec_bcr;
-	u8 _res21[0x2a010 - 0x2a008];
+	u8 _res24[0x2a010 - 0x2a008];
 	u32 gcc_usb4_1_dp0_phy_sec_bcr;
-	u8 _res22[0x2d014 - 0x2a014];
+	u8 _res25[0x2d014 - 0x2a014];
 	u32 gcc_sys_noc_usb_axi_cbcr;
-	u8 _res23[0x2d024 - 0x2d018];
+	u8 _res26[0x2d024 - 0x2d018];
 	u32 gcc_cfg_noc_usb_anoc_ahb_cbcr;
 	u32 gcc_cfg_noc_usb_anoc_north_ahb_cbcr;
 	u32 gcc_cfg_noc_usb_anoc_south_ahb_cbcr;
-	u8 _res24[0x2d034 - 0x2d030];
+	u8 _res27[0x2d034 - 0x2d030];
 	u32 gcc_aggre_usb_noc_axi_cbcr;
-	u8 _res25[0x2d174 - 0x2d038];
+	u8 _res28[0x2d174 - 0x2d038];
 	u32 gcc_aggre_noc_usb_south_axi_cbcr;
-	u8 _res26[0x2d17c - 0x2d178];
+	u8 _res29[0x2d17c - 0x2d178];
 	u32 gcc_aggre_noc_usb_north_axi_cbcr;
-	u8 _res27[0x31000 - 0x2d180];
+	u8 _res30[0x31000 - 0x2d180];
 	struct x1p42100_pcie pcie_6a;
-	u8  _res28[0x39000 - 0x3108c];
+	u8  _res31[0x39000 - 0x3108c];
 	u32 gcc_usb30_prim_bcr;
 	u32 gcc_usb30_prim_gdscr;
-	u8  _res29[0x39018 - 0x39008];
+	u8  _res32[0x39018 - 0x39008];
 	u32 gcc_usb30_prim_master_cbcr;
-	u8  _res30[0x39024 - 0x3901c];
+	u8  _res33[0x39024 - 0x3901c];
 	u32 gcc_usb30_prim_sleep_cbcr;
 	u32 gcc_usb30_prim_mock_utmi_cbcr;
 	struct clock_rcg usb30_prim_master_rcg;
-	u8  _res31[0x39060 - 0x39034];
+	u8  _res34[0x39060 - 0x39034];
 	u32 gcc_usb3_prim_phy_aux_cbcr;
 	u32 gcc_usb3_prim_phy_com_aux_cbcr;
 	u32 gcc_usb3_prim_phy_pipe_cbcr;
 	u32 gcc_usb3_prim_phy_pipe_muxr;
 	u32 gcc_usb4_mode_prim_phy_pipe_muxr;
-	u8  _res32[0x3908c - 0x39074];
+	u8  _res35[0x3908c - 0x39074];
 	u32 gcc_cfg_noc_usb3_prim_axi_cbcr;
 	u32 gcc_aggre_usb3_prim_axi_cbcr;
-	u8  _res33[0x42004 - 0x39094];
+	u8  _res36[0x42004 - 0x39094];
 	struct qupv3_clock qup_wrap0_s[8];
-	u8 _res34[0x4b000 - 0x429c4];
+	u8 _res37[0x4b000 - 0x429c4];
 	u32 qspi_bcr;
 	u32 qspi_cnoc_ahb_cbcr;
 	u32 qspi_core_cbcr;
 	struct clock_rcg qspi_core;
-	u8 _res35[0x50000 - 0x4b014];
+	u8 _res38[0x50000 - 0x4b014];
 	u32 gcc_usb3_phy_prim_bcr;
 	u32 gcc_usb3phy_phy_prim_bcr;
-	u8 _res36[0x50010 - 0x50008];
+	u8 _res39[0x50010 - 0x50008];
 	u32 gcc_usb4_0_dp0_phy_prim_bcr;
-	u8 _res37[0x52000 - 0x50014];
+	u8 _res40[0x52000 - 0x50014];
 	u32 apcs_clk_br_en;
-	u8 _res38[0x52008 - 0x52004];
+	u8 _res41[0x52008 - 0x52004];
 	u32 apcs_clk_br_en1;
-	u8 _res39[0x52010 - 0x5200c];
+	u8 _res42[0x52010 - 0x5200c];
 	u32 apcs_clk_br_en2;
-	u8 _res40[0x52018 - 0x52014];
+	u8 _res43[0x52018 - 0x52014];
 	u32 apcs_clk_br_en3;
-	u8 _res41[0x52020 - 0x5201c];
+	u8 _res44[0x52020 - 0x5201c];
 	u32 apcs_clk_br_en4;
-	u8 _res42[0x52028 - 0x52024];
+	u8 _res45[0x52028 - 0x52024];
 	u32 apcs_clk_br_en5;
-	u8 _res43[0x52030 - 0x5202c];
+	u8 _res46[0x52030 - 0x5202c];
 	u32 apcs_pll_br_en;
-	u8 _res44[0x54000 - 0x52034];
+	u8 _res47[0x54000 - 0x52034];
 	u32 usb3_uniphy_mp1_bcr;
 	u32 usb3uniphy_phy_mp1_bcr;
 	u32 gcc_usb3_mp_ss1_phy_bcr;
 	u32 gcc_usb3_mp_ss1_phy_gdscr;
-	u8 _res45[0x8e000 - 0x54010];
+	u8 _res48[0x8e000 - 0x54010];
 	u32 pcie_6_phy_gdscr;
-	u8 _res46[0xa1000 - 0x8e004];
+	u8 _res49[0xa1000 - 0x8e004];
 	u32 gcc_usb30_sec_bcr;
 	u32 gcc_usb30_sec_gdscr;
-	u8 _res47[0xa1018 - 0xa1008];
+	u8 _res50[0xa1018 - 0xa1008];
 	u32 gcc_usb30_sec_master_cbcr;
-	u8 _res48[0xa1024 - 0xa101c];
+	u8 _res51[0xa1024 - 0xa101c];
 	u32 gcc_usb30_sec_sleep_cbcr;
 	u32 gcc_usb30_sec_mock_utmi_cbcr;
 	struct clock_rcg usb30_sec_master_rcg;
-	u8 _res49[0xa1060 - 0xa1034];
+	u8 _res52[0xa1060 - 0xa1034];
 	u32 gcc_usb3_sec_phy_aux_cbcr;
 	u32 gcc_usb3_sec_phy_com_aux_cbcr;
 	u32 gcc_usb3_sec_phy_pipe_cbcr;
 	u32 gcc_usb3_sec_phy_pipe_muxr;
-	u8 _res50[0xa108c - 0xa1070];
+	u8 _res53[0xa108c - 0xa1070];
 	u32 gcc_cfg_noc_usb3_sec_axi_cbcr;
 	u32 gcc_aggre_usb3_sec_axi_cbcr;
-	u8 _res51[0xa2000 - 0xa1094];
+	u8 _res54[0xa2000 - 0xa1094];
 	u32 gcc_usb30_tert_bcr;
 	u32 gcc_usb30_tert_gdscr;
-	u8 _res52[0xa2018 - 0xa2008];
+	u8 _res55[0xa2018 - 0xa2008];
 	u32 gcc_usb30_tert_master_cbcr;
-	u8 _res53[0xa2024 - 0xa201c];
+	u8 _res56[0xa2024 - 0xa201c];
 	u32 gcc_usb30_tert_sleep_cbcr;
 	u32 gcc_usb30_tert_mock_utmi_cbcr;
-	u8 _res54[0xa2034 - 0xa202c];
+	u8 _res57[0xa2034 - 0xa202c];
 	u32 gcc_usb30_tert_master_m;
 	u32 gcc_usb30_tert_master_n;
 	u32 gcc_usb30_tert_master_d;
-	u8 _res55[0xa2060 - 0xa2040];
+	u8 _res58[0xa2060 - 0xa2040];
 	u32 gcc_usb3_tert_phy_aux_cbcr;
 	u32 gcc_usb3_tert_phy_com_aux_cbcr;
 	u32 gcc_usb3_tert_phy_pipe_cbcr;
 	u32 gcc_usb3_tert_phy_pipe_muxr;
-	u8 _res56[0xa208c - 0xa2070];
+	u8 _res59[0xa208c - 0xa2070];
 	u32 gcc_cfg_noc_usb3_tert_axi_cbcr;
 	u32 gcc_aggre_usb3_tert_axi_cbcr;
-	u8 _res57[0xa3000 - 0xa2094];
+	u8 _res60[0xa3000 - 0xa2094];
 	u32 gcc_usb3_phy_tert_bcr;
 	u32 gcc_usb3phy_phy_tert_bcr;
-	u8 _res58[0xa3010 - 0xa3008];
+	u8 _res61[0xa3010 - 0xa3008];
 	u32 gcc_usb4_2_dp0_phy_tert_bcr;
-	u8 _res59[0xac01c - 0xa3014];
+	u8 _res62[0xac01c - 0xa3014];
 	u32 pcie_6a_phy_bcr;
 };
 
@@ -430,6 +526,9 @@ check_member(x1p42100_gcc, qup_wrap1_core_2x, 0x23174);
 check_member(x1p42100_gcc, qup_wrap2_m_ahb_cbcr, 0x232a0);
 check_member(x1p42100_gcc, qup_wrap2_core_cdivr, 0x232b4);
 check_member(x1p42100_gcc, qup_wrap2_core_2x, 0x232c4);
+check_member(x1p42100_gcc, gcc_disp_ahb_cbcr, 0x27004);
+check_member(x1p42100_gcc, gcc_disp_hf_axi_cbcr, 0x2700c);
+check_member(x1p42100_gcc, gcc_disp_xo_cbcr, 0x27018);
 check_member(x1p42100_gcc, gcc_sys_noc_usb_axi_cbcr, 0x2d014);
 check_member(x1p42100_gcc, gcc_cfg_noc_usb_anoc_north_ahb_cbcr, 0x2d028);
 check_member(x1p42100_gcc, gcc_aggre_usb_noc_axi_cbcr, 0x2d034);
@@ -545,6 +644,12 @@ enum clk_usb_gdsc {
 	USB30_SEC_GDSC,
 	MAX_USB_GDSC,
 };
+
+enum clk_disp_gdsc {
+	DISP_CC_CORE_GDSC,
+	MAX_DISP_GDSC,
+};
+
 enum clk_usb {
 	USB30_MP_MASTER_CBCR,
 	USB30_MP_SLEEP_CBCR,
@@ -564,6 +669,23 @@ enum clk_usb {
 	USB_CLK_COUNT,
 };
 
+enum clk_mdss {
+	GCC_DISP_AHB_CBCR,
+	GCC_DISP_XO_CBCR,
+	GCC_DISP_HF_AXI_CBCR,
+	DISP_CC_MDSS_AHB_CBCR,
+	DISP_CC_MDSS_MDP_CBCR,
+	DISP_CC_MDSS_VSYNC_CBCR,
+	DISP_CC_MDSS_RSCC_AHB_CBCR,
+	DISP_CC_MDSS_RSCC_VSYNC_CBCR,
+	DISP_CC_XO_CBCR,
+	DISP_CC_MDSS_DPTX3_PIXEL0_CBCR,
+	DISP_CC_MDSS_DPTX3_LINK_CBCR,
+	DISP_CC_MDSS_DPTX3_AUX_CBCR,
+	DISP_CC_MDSS_DPTX3_LINK_INTF_CBCR,
+	MDSS_CLK_COUNT,
+};
+
 enum clk_usb_prim {
 	USB_PRIM_SYS_NOC_USB_AXI_CBCR,
 	USB_PRIM_CFG_NOC_USB_ANOC_AHB_CBCR,
@@ -642,6 +764,9 @@ void usb_sec_clock_reset(enum clk_usb_sec clk_type, bool assert);
 static struct aoss *const aoss = (void *)AOSS_CC_BASE;
 static struct x1p42100_gcc *const gcc = (void *)GCC_BASE;
 static struct x1p42100_ncc0_clock *const apss_ncc0 = (void *)NCC0_BASE;
+static struct x1p42100_disp_pll_clock *const apss_disp_pll0 = (void *)DISP_PLL0_BASE;
+static struct x1p42100_disp_pll_clock *const apss_disp_pll1 = (void *)DISP_PLL1_BASE;
+static struct x1p42100_disp_cc *const disp_cc = (void *)DISP_CC_BASE;
 static struct x1p42100_qupv3_wrap *const qup_wrap0_clk = (void *)GCC_QUPV3_WRAP0_BASE;
 static struct x1p42100_qupv3_wrap *const qup_wrap1_clk = (void *)GCC_QUPV3_WRAP1_BASE;
 static struct x1p42100_qupv3_wrap *const qup_wrap2_clk = (void *)GCC_QUPV3_WRAP2_BASE;

From 04f83ff7dcae1977daa14ea1555e376a453a9e4f Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Micha=C5=82=20=C5=BBygowski?= <michal.zygowski@3mdeb.com>
Date: Tue, 16 Sep 2025 09:15:27 +0200
Subject: [PATCH 2748/3886] cpu/x86/mtrr: Simplify MTRR solution calculation on
 AMD systems
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

AMD systems have a TOM2WB bit in SYS_CFG MSR to forcefully cover the
address space between 4GB-TOM2 as WB. Any WB MTRR that falls into that
range may be skipped from programming. It can save a lot of MTRRs when
calculating the MTRR solution. It is especially needed when using a
temporary MTRR to cover the flash as WP, as the MTRR space gets more
fragmented.

Add checks for SYS_CFG TOM2WB in the MTRR driver and skip the WB MTRR
ranges when possible.

TEST=Successfully enable temporary MTRR range for flash on Gigabyte
MZ33-AR1.

Change-Id: Ie9af9b54a1037c843d8f019506af761a8d8769d0
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89199
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/cpu/x86/mtrr/mtrr.c                       | 38 +++++++++++++++++++
 .../amd/common/block/cpu/smm/smm_relocate.c   |  6 +--
 2 files changed, 39 insertions(+), 5 deletions(-)

diff --git a/src/cpu/x86/mtrr/mtrr.c b/src/cpu/x86/mtrr/mtrr.c
index 33fc46e362..72727861de 100644
--- a/src/cpu/x86/mtrr/mtrr.c
+++ b/src/cpu/x86/mtrr/mtrr.c
@@ -598,6 +598,25 @@ static void calc_var_mtrrs_with_hole(struct var_mtrr_state *var_state,
 	}
 }
 
+static bool is_tom2_wb_active(void)
+{
+	msr_t syscfg = rdmsr(SYSCFG_MSR);
+	syscfg.lo &= (SYSCFG_MSR_TOM2WB | SYSCFG_MSR_TOM2En);
+	return (syscfg.lo == (SYSCFG_MSR_TOM2WB | SYSCFG_MSR_TOM2En));
+}
+
+static bool is_range_in_tom2_wb(struct range_entry *r)
+{
+	const msr_t tom2_msr = rdmsr(TOP_MEM2_MSR);
+	const uint64_t tom2 = tom2_msr.lo | ((uint64_t)tom2_msr.hi << 32);
+	const int mtrr_type = range_entry_mtrr_type(r);
+
+	if ((r->begin >= (4ULL * GiB)) && (r->end < tom2))
+		return (mtrr_type == MTRR_TYPE_WRBACK);
+
+	return false;
+}
+
 static void __calc_var_mtrrs(struct memranges *addr_space,
 			     bool above4gb, int address_bits,
 			     int *num_def_wb_mtrrs, int *num_def_uc_mtrrs)
@@ -633,6 +652,15 @@ static void __calc_var_mtrrs(struct memranges *addr_space,
 
 		mtrr_type = range_entry_mtrr_type(r);
 
+		/*
+		 * WB MTRRs inside [4G - TOM2] range can be skipped on AMD, if
+		 * TOM2 WB is active.
+		 */
+		if (CONFIG(X86_AMD_FIXED_MTRRS) && above4gb) {
+			if (is_tom2_wb_active() && is_range_in_tom2_wb(r))
+				continue;
+		}
+
 		if (mtrr_type != MTRR_TYPE_UNCACHEABLE) {
 			var_state.mtrr_index = 0;
 			var_state.def_mtrr_type = MTRR_TYPE_UNCACHEABLE;
@@ -704,6 +732,16 @@ static void prepare_var_mtrrs(struct memranges *addr_space, int def_type,
 	memranges_each_entry(r, var_state.addr_space) {
 		if (range_entry_mtrr_type(r) == def_type)
 			continue;
+
+		/*
+		 * WB MTRRs inside [4G - TOM2] range can be skipped on AMD, if
+		 * TOM2 WB is active.
+		 */
+		if (CONFIG(X86_AMD_FIXED_MTRRS) && above4gb) {
+			if (is_tom2_wb_active() && is_range_in_tom2_wb(r))
+				continue;
+		}
+
 		calc_var_mtrrs_with_hole(&var_state, r);
 	}
 
diff --git a/src/soc/amd/common/block/cpu/smm/smm_relocate.c b/src/soc/amd/common/block/cpu/smm/smm_relocate.c
index d01f4c3e2d..e5b8d9d17a 100644
--- a/src/soc/amd/common/block/cpu/smm/smm_relocate.c
+++ b/src/soc/amd/common/block/cpu/smm/smm_relocate.c
@@ -17,11 +17,7 @@
 /* AP MTRRs will be synced to the BSP in the SIPI vector so set them up before MP init. */
 static void pre_mp_init(void)
 {
-	const msr_t syscfg = rdmsr(SYSCFG_MSR);
-	if (syscfg.lo & SYSCFG_MSR_TOM2WB)
-		x86_setup_mtrrs_with_detect_no_above_4gb();
-	else
-		x86_setup_mtrrs_with_detect();
+	x86_setup_mtrrs_with_detect();
 	x86_mtrr_check();
 	if (CONFIG(SOC_AMD_COMMON_BLOCK_UCODE))
 		amd_load_microcode_from_cbfs();

From c3afc13a0a52d870b086eed6cf86860b1cb7b1c8 Mon Sep 17 00:00:00 2001
From: Kirubakaran E <kirue@qualcomm.corp-partner.google.com>
Date: Wed, 3 Dec 2025 21:21:42 -0800
Subject: [PATCH 2749/3886] soc/qualcomm/x1p42100: Update memlayout for BL31
 region and realign TA region

TF-A feature additions have increased BL31 memory requirements. Expand
BL31 reservation from 600KB to 800KB and adjust the TA region start
address to prevent overlap. The TA region change requires FDT memory
reservation updates, which are handled in Depthcharge.This update
ensures proper memory alignment for secure firmware execution.

TEST=Created image.serial.bin and verified successful boot on X1P42100.
Basic device boot functionality with the updated memory reservation has
been validated.

Change-Id: Ia0145c9e8d5925de4a7fee3399efc76059944c10
Signed-off-by: Kirubakaran E <kirue@qualcomm.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90429
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
---
 src/soc/qualcomm/x1p42100/memlayout.ld | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/src/soc/qualcomm/x1p42100/memlayout.ld b/src/soc/qualcomm/x1p42100/memlayout.ld
index afc38d3336..5bd7d98f04 100644
--- a/src/soc/qualcomm/x1p42100/memlayout.ld
+++ b/src/soc/qualcomm/x1p42100/memlayout.ld
@@ -30,9 +30,9 @@
  *               |                     dram_display                         |      |        |
  * 0xE4800000    +----------------------------------------------------------+      |        |
  *               |                ... Usable memory ...                     |      |        |
- * 0xD9600000    +----------------------------------------------------------+      |        |
+ * 0xD9632000    +----------------------------------------------------------+      |        |
  *               |                       dram_ta                            |      |        |
- * 0xD8600000    +----------------------------------------------------------+      |        |
+ * 0xD8632000    +----------------------------------------------------------+      |        |
  *               |                 BL31 (ARM Trusted Firmware)              |      |        |
  * 0xD856A000    +----------------------------------------------------------+      |        |
  *               |                  dram_tz (TrustZone)                     |      |        |
@@ -242,8 +242,8 @@ SECTIONS
 	POSTRAM_CBFS_CACHE(0x9F800000, 16M)
 	RAMSTAGE(0xA0800000, 16M)
 	REGION(dram_tz, 0xD8000000, 0x56A000, 4K)
-	BL31(0xD856A000, 600K)
-	REGION(dram_ta, 0xD8600000, 0x1000000, 4K)
+	BL31(0xD856A000, 800K)
+	REGION(dram_ta, 0xD8632000, 0x1000000, 4K)
 	REGION(dram_display, 0xE4800000, 0x21C0000, 4K)
 	REGION(dram_llcc_lpi, 0xFF800000, 0x600000, 4K)
 	REGION(dram_smem, 0xFFE00000, 0x200000, 4K)

From 5eb7b8bd3474904759c83aa9f27889331da0ba60 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Micha=C5=82=20=C5=BBygowski?= <michal.zygowski@3mdeb.com>
Date: Mon, 6 Oct 2025 11:13:12 +0200
Subject: [PATCH 2750/3886] payloads/external/edk2/Makefile: Set SMBIOS to
 3.0.0
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

coreboot produces SMBIOS tables with version 3.0.0. The UEFI payload
may overwrite this value based on PCDs and cause a mismatch of the
SMBIOS tables version produced by coreboot and version visible to OS.
To ensure proper parsing of SMBIOS tables in OS, set the same version
of SMBIOS for UEFI payload using the PCDs.

TEST=Run dmidecode on Gigabyte MZ33-AR1 and see that the tool reports
SMBIOS 3.0.0 present.

Change-Id: Ie3cdcca65dbcdddc74cb352ef5c4d3e83bdc87f5
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89481
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
---
 payloads/external/edk2/Makefile | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/payloads/external/edk2/Makefile b/payloads/external/edk2/Makefile
index 6122cd4d30..c9bd36a27f 100644
--- a/payloads/external/edk2/Makefile
+++ b/payloads/external/edk2/Makefile
@@ -185,6 +185,10 @@ endif
 BUILD_STR += --pcd gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultOemId="COREv4"
 BUILD_STR += --pcd gUefiCpuPkgTokenSpaceGuid.PcdFirstTimeWakeUpAPsBySipi=FALSE
 
+# coreboot produces SMBIOS 3.0.0 tables
+BUILD_STR += --pcd gEfiMdeModulePkgTokenSpaceGuid.PcdSmbiosVersion=0x0300
+BUILD_STR += --pcd gEfiMdeModulePkgTokenSpaceGuid.PcdSmbiosDocRev=0x0
+
 bootloader = $(word 8,$(subst /, ,$(BUILD_STR)))
 
 ifneq ($(CONFIG_EDK2_CUSTOM_BUILD_PARAMS),)

From 02a2fe7907d94694dbbdee0eefc63368c25551be Mon Sep 17 00:00:00 2001
From: Julius Werner <jwerner@chromium.org>
Date: Mon, 1 Dec 2025 15:45:15 -0800
Subject: [PATCH 2751/3886] Merge coreboot and libpayload <endian.h> into
 commonlib

We've accumulated a number of endianness-handling and related macros
that are duplicated between coreboot and libpayload. This patch reduces
duplication by merging them into a commonlib header. This has the added
side-benefit of bringing the coreboot implementation of beXXenc/dec()
functions to libpayload, which lead to better code generation by
avoiding https://gcc.gnu.org/bugzilla/show_bug.cgi?id=92716.

Keep the htobell()-style functions in libpayload only since they're not
needed in coreboot and not preferred. Keep the cpu_to_beXX()-style
functions in coreboot only -- maybe we should deprecate those
eventually.

This patch is explicitly copying and relicensing some of the code I
originally added as GPLv2 in commit e8e92d60c4e2 ("endian.h: Add
be32dec/be32enc family of functions") to BSD-3.

Change-Id: I5eb83d44a98b3aa59bba65b8e22df668874d2668
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90308
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 payloads/libpayload/include/endian.h          | 218 +-----------------
 .../bsd/include/commonlib/bsd/_endian.h       | 170 ++++++++++++++
 src/include/device/mmio.h                     |  73 ------
 src/include/endian.h                          | 181 ++-------------
 4 files changed, 192 insertions(+), 450 deletions(-)
 create mode 100644 src/commonlib/bsd/include/commonlib/bsd/_endian.h

diff --git a/payloads/libpayload/include/endian.h b/payloads/libpayload/include/endian.h
index fd59af1b5c..46e5dfe6eb 100644
--- a/payloads/libpayload/include/endian.h
+++ b/payloads/libpayload/include/endian.h
@@ -32,152 +32,20 @@
 #include <arch/io.h>
 #include <arch/types.h>
 #include <libpayload-config.h>
+#include <string.h>
 
-/* Endian functions from glibc 2.9 / BSD "endian.h" */
+#define swab16(x) __builtin_bswap16(x)
+#define swab32(x) __builtin_bswap32(x)
+#define swab64(x) __builtin_bswap64(x)
 
 #if CONFIG(LP_BIG_ENDIAN)
-
-#define htobe16(in) (in)
-#define htobe32(in) (in)
-#define htobe64(in) (in)
-
-#define htole16(in) ((uint16_t)__builtin_bswap16(in))
-#define htole32(in) ((uint32_t)__builtin_bswap32(in))
-#define htole64(in) ((uint64_t)__builtin_bswap64(in))
-
+#define __BIG_ENDIAN
 #elif CONFIG(LP_LITTLE_ENDIAN)
-
-#define htobe16(in) ((uint16_t)__builtin_bswap16(in))
-#define htobe32(in) ((uint32_t)__builtin_bswap32(in))
-#define htobe64(in) ((uint64_t)__builtin_bswap64(in))
-
-#define htole16(in) (in)
-#define htole32(in) (in)
-#define htole64(in) (in)
-
-#else
-
-#error Cant tell if the CPU is little or big endian.
-
+#define __LITTLE_ENDIAN
 #endif /* CONFIG_*_ENDIAN */
 
-#define be16toh(in) htobe16(in)
-#define be32toh(in) htobe32(in)
-#define be64toh(in) htobe64(in)
-
-#define le16toh(in) htole16(in)
-#define le32toh(in) htole32(in)
-#define le64toh(in) htole64(in)
-
-#define htonw(in) htobe16(in)
-#define htonl(in) htobe32(in)
-#define htonll(in) htobe64(in)
-
-#define ntohw(in) be16toh(in)
-#define ntohl(in) be32toh(in)
-#define ntohll(in) be64toh(in)
-
-/*
- * Alignment-agnostic encode/decode bytestream to/from little/big endian.
- */
-
-static inline uint16_t be16dec(const void *pp)
-{
-	uint8_t const *p = (uint8_t const *)pp;
-
-	return (uint16_t)((p[0] << 8) | p[1]);
-}
-
-static inline uint32_t be32dec(const void *pp)
-{
-	uint8_t const *p = (uint8_t const *)pp;
-
-	return (((uint32_t)p[0] << 24) | (uint32_t)(p[1] << 16) |
-		(uint32_t)(p[2] << 8) | p[3]);
-}
-
-static inline uint64_t be64dec(const void *pp)
-{
-	uint8_t const *p = (uint8_t const *)pp;
-
-	return (((uint64_t)p[0] << 56) | ((uint64_t)p[1] << 48) |
-		((uint64_t)p[2] << 40) | ((uint64_t)p[3] << 32) |
-		((uint64_t)p[4] << 24) | ((uint64_t)p[5] << 16) |
-		((uint64_t)p[6] <<  8) | p[7]);
-}
-
-static inline uint16_t le16dec(const void *pp)
-{
-	uint8_t const *p = (uint8_t const *)pp;
-
-	return (uint16_t)((p[1] << 8) | p[0]);
-}
-
-static inline uint32_t le32dec(const void *pp)
-{
-	uint8_t const *p = (uint8_t const *)pp;
-
-	return ((uint32_t)(p[3] << 24) | (uint32_t)(p[2] << 16) |
-		(uint32_t)(p[1] << 8) | p[0]);
-}
-
-static inline uint64_t le64dec(const void *pp)
-{
-	uint8_t const *p = (uint8_t const *)pp;
-
-	return (((uint64_t)p[7] << 56) | ((uint64_t)p[6] << 48) |
-		((uint64_t)p[5] << 40) | ((uint64_t)p[4] << 32) |
-		((uint64_t)p[3] << 24) | ((uint64_t)p[2] << 16) |
-		((uint64_t)p[1] <<  8) | p[0]);
-}
-
-static inline void bebitenc(void *pp, uint32_t u, uint8_t b)
-{
-	uint8_t *p = (uint8_t *)pp;
-	int i;
-
-	for (i = 0; i < b; i++)
-		p[(b - 1) - i] = (u >> i*8) & 0xFF;
-}
-
-static inline void be16enc(void *pp, uint16_t u)
-{
-	bebitenc(pp, u, 2);
-}
-
-static inline void be32enc(void *pp, uint32_t u)
-{
-	bebitenc(pp, u, 4);
-}
-
-static inline void be64enc(void *pp, uint32_t u)
-{
-	bebitenc(pp, u, 8);
-}
-
-static inline void lebitenc(void *pp, uint32_t u, uint8_t b)
-{
-	uint8_t *p = (uint8_t *)pp;
-	int i;
-
-	for (i = 0; i < b; i++)
-		p[i] = (u >> i*8) & 0xFF;
-}
-
-static inline void le16enc(void *pp, uint16_t u)
-{
-	lebitenc(pp, u, 2);
-}
-
-static inline void le32enc(void *pp, uint32_t u)
-{
-	lebitenc(pp, u, 4);
-}
-
-static inline void le64enc(void *pp, uint32_t u)
-{
-	lebitenc(pp, u, 8);
-}
+/* This include depends on previous definitions, do not move to the top. */
+#include <commonlib/bsd/_endian.h>
 
 /* Deprecated names (not in glibc / BSD) */
 #define htobew(in) htobe16(in)
@@ -193,74 +61,4 @@ static inline void le64enc(void *pp, uint32_t u)
 #define letohl(in) le32toh(in)
 #define letohll(in) le64toh(in)
 
-/* read/write with uintptr_t address */
-#define read8p(addr)	read8((void *)((uintptr_t)(addr)))
-#define read16p(addr)	read16((void *)((uintptr_t)(addr)))
-#define read32p(addr)	read32((void *)((uintptr_t)(addr)))
-#define read64p(addr)	read64((void *)((uintptr_t)(addr)))
-#define write8p(addr, value)	write8((void *)((uintptr_t)(addr)), value)
-#define write16p(addr, value)	write16((void *)((uintptr_t)(addr)), value)
-#define write32p(addr, value)	write32((void *)((uintptr_t)(addr)), value)
-#define write64p(addr, value)	write64((void *)((uintptr_t)(addr)), value)
-
-/* Handy bit manipulation macros */
-
-#define __clrsetbits(endian, bits, addr, clear, set) \
-	write##bits(addr, hto##endian##bits((endian##bits##toh( \
-		read##bits(addr)) & ~((uint##bits##_t)(clear))) | (set)))
-
-#define clrbits_le64(addr, clear)	__clrsetbits(le, 64, addr, clear, 0)
-#define clrbits_be64(addr, clear)	__clrsetbits(be, 64, addr, clear, 0)
-#define clrbits_le32(addr, clear)	__clrsetbits(le, 32, addr, clear, 0)
-#define clrbits_be32(addr, clear)	__clrsetbits(be, 32, addr, clear, 0)
-#define clrbits_le16(addr, clear)	__clrsetbits(le, 16, addr, clear, 0)
-#define clrbits_be16(addr, clear)	__clrsetbits(be, 16, addr, clear, 0)
-
-#define setbits_le64(addr, set)		__clrsetbits(le, 64, addr, 0, set)
-#define setbits_be64(addr, set)		__clrsetbits(be, 64, addr, 0, set)
-#define setbits_le32(addr, set)		__clrsetbits(le, 32, addr, 0, set)
-#define setbits_be32(addr, set)		__clrsetbits(be, 32, addr, 0, set)
-#define setbits_le16(addr, set)		__clrsetbits(le, 16, addr, 0, set)
-#define setbits_be16(addr, set)		__clrsetbits(be, 16, addr, 0, set)
-
-#define clrsetbits_le64(addr, clear, set) __clrsetbits(le, 64, addr, clear, set)
-#define clrsetbits_be64(addr, clear, set) __clrsetbits(be, 64, addr, clear, set)
-#define clrsetbits_le32(addr, clear, set) __clrsetbits(le, 32, addr, clear, set)
-#define clrsetbits_be32(addr, clear, set) __clrsetbits(be, 32, addr, clear, set)
-#define clrsetbits_le16(addr, clear, set) __clrsetbits(le, 16, addr, clear, set)
-#define clrsetbits_be16(addr, clear, set) __clrsetbits(be, 16, addr, clear, set)
-
-#define __clrsetbits_impl(bits, addr, clear, set) write##bits(addr, \
-	(read##bits(addr) & ~((uint##bits##_t)(clear))) | (set))
-
-#define clrsetbits8(addr, clear, set)	__clrsetbits_impl(8, addr, clear, set)
-#define clrsetbits16(addr, clear, set)	__clrsetbits_impl(16, addr, clear, set)
-#define clrsetbits32(addr, clear, set)	__clrsetbits_impl(32, addr, clear, set)
-#define clrsetbits64(addr, clear, set)	__clrsetbits_impl(64, addr, clear, set)
-
-#define setbits8(addr, set)		clrsetbits8(addr, 0, set)
-#define setbits16(addr, set)		clrsetbits16(addr, 0, set)
-#define setbits32(addr, set)		clrsetbits32(addr, 0, set)
-#define setbits64(addr, set)		clrsetbits64(addr, 0, set)
-
-#define clrbits8(addr, clear)		clrsetbits8(addr, clear, 0)
-#define clrbits16(addr, clear)		clrsetbits16(addr, clear, 0)
-#define clrbits32(addr, clear)		clrsetbits32(addr, clear, 0)
-#define clrbits64(addr, clear)		clrsetbits64(addr, clear, 0)
-
-#define clrsetbits8p(addr, clear, set)	clrsetbits8((void *)((uintptr_t)(addr)), clear, set)
-#define clrsetbits16p(addr, clear, set)	clrsetbits16((void *)((uintptr_t)(addr)), clear, set)
-#define clrsetbits32p(addr, clear, set)	clrsetbits32((void *)((uintptr_t)(addr)), clear, set)
-#define clrsetbits64p(addr, clear, set)	clrsetbits64((void *)((uintptr_t)(addr)), clear, set)
-
-#define setbits8p(addr, set)		clrsetbits8((void *)((uintptr_t)(addr)), 0, set)
-#define setbits16p(addr, set)		clrsetbits16((void *)((uintptr_t)(addr)), 0, set)
-#define setbits32p(addr, set)		clrsetbits32((void *)((uintptr_t)(addr)), 0, set)
-#define setbits64p(addr, set)		clrsetbits64((void *)((uintptr_t)(addr)), 0, set)
-
-#define clrbits8p(addr, clear)		clrsetbits8((void *)((uintptr_t)(addr)), clear, 0)
-#define clrbits16p(addr, clear)		clrsetbits16((void *)((uintptr_t)(addr)), clear, 0)
-#define clrbits32p(addr, clear)		clrsetbits32((void *)((uintptr_t)(addr)), clear, 0)
-#define clrbits64p(addr, clear)		clrsetbits64((void *)((uintptr_t)(addr)), clear, 0)
-
 #endif /* _ENDIAN_H_ */
diff --git a/src/commonlib/bsd/include/commonlib/bsd/_endian.h b/src/commonlib/bsd/include/commonlib/bsd/_endian.h
new file mode 100644
index 0000000000..d0d5be9f9f
--- /dev/null
+++ b/src/commonlib/bsd/include/commonlib/bsd/_endian.h
@@ -0,0 +1,170 @@
+/* SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0-only */
+
+#ifndef _COMMONLIB_BSD__ENDIAN_H_
+#define _COMMONLIB_BSD__ENDIAN_H_
+
+/*
+ * This header should not be included directly. Including source must define
+ * prerequisites like uintXX_t types, the byteswap functions swabXX(),
+ * __BIG_ENDIAN or __LITTLE_ENDIAN and I/O accessors readXX()/writeXX().
+ */
+
+/* Endian functions from glibc 2.9 / BSD "endian.h" */
+
+#if defined(__BIG_ENDIAN)
+	#define htobe16(in) (in)
+	#define htobe32(in) (in)
+	#define htobe64(in) (in)
+	#define htole16(in) ((uint16_t)swab16(in))
+	#define htole32(in) ((uint32_t)swab32(in))
+	#define htole64(in) ((uint64_t)swab64(in))
+#elif defined(__LITTLE_ENDIAN)
+	#define htobe16(in) ((uint16_t)swab16(in))
+	#define htobe32(in) ((uint32_t)swab32(in))
+	#define htobe64(in) ((uint64_t)swab64(in))
+	#define htole16(in) (in)
+	#define htole32(in) (in)
+	#define htole64(in) (in)
+#else
+	#error "Including source must #define __LITTLE_ENDIAN or __BIG_ENDIAN"
+#endif
+
+#define be16toh(in) htobe16(in)
+#define be32toh(in) htobe32(in)
+#define be64toh(in) htobe64(in)
+
+#define le16toh(in) htole16(in)
+#define le32toh(in) htole32(in)
+#define le64toh(in) htole64(in)
+
+#define htonw(in) htobe16(in)
+#define htonl(in) htobe32(in)
+#define htonll(in) htobe64(in)
+
+#define ntohw(in) be16toh(in)
+#define ntohl(in) be32toh(in)
+#define ntohll(in) be64toh(in)
+
+/*
+ * RISC-V doesn't support misaligned access so it must use memcpy().
+ */
+#if defined(__COREBOOT__) && ENV_RISCV
+#define __ENDIAN_RISCV_WORKAROUND 1
+#else
+#define __ENDIAN_RISCV_WORKAROUND 0
+#endif
+
+/*
+ * be16dec/be32dec/be64dec/le16dec/le32dec/le64dec family of functions.
+ */
+#define DEFINE_ENDIAN_DEC(endian, width) \
+	static inline uint##width##_t endian##width##dec(const void *p) \
+	{ \
+		if (__ENDIAN_RISCV_WORKAROUND) { \
+			uint##width##_t val; \
+			memcpy(&val, p, sizeof(val)); \
+			return endian##width##toh(val); \
+		} else { \
+			return endian##width##toh(*(uint##width##_t *)p); \
+		} \
+	}
+
+DEFINE_ENDIAN_DEC(be, 16)
+DEFINE_ENDIAN_DEC(be, 32)
+DEFINE_ENDIAN_DEC(be, 64)
+DEFINE_ENDIAN_DEC(le, 16)
+DEFINE_ENDIAN_DEC(le, 32)
+DEFINE_ENDIAN_DEC(le, 64)
+
+/*
+ * be16enc/be32enc/be64enc/le16enc/le32enc/le64enc family of functions.
+ */
+#define DEFINE_ENDIAN_ENC(endian, width) \
+	static inline void endian##width##enc(void *p, uint##width##_t u) \
+	{ \
+		if (__ENDIAN_RISCV_WORKAROUND) { \
+			uint##width##_t val = hto##endian##width(u); \
+			memcpy(p, &val, sizeof(val)); \
+		} else { \
+			*(uint##width##_t *)p = hto##endian##width(u); \
+		} \
+	}
+
+DEFINE_ENDIAN_ENC(be, 16)
+DEFINE_ENDIAN_ENC(be, 32)
+DEFINE_ENDIAN_ENC(be, 64)
+DEFINE_ENDIAN_ENC(le, 16)
+DEFINE_ENDIAN_ENC(le, 32)
+DEFINE_ENDIAN_ENC(le, 64)
+
+/* read/write with uintptr_t address */
+#define read8p(addr)		read8((void *)((uintptr_t)(addr)))
+#define read16p(addr)		read16((void *)((uintptr_t)(addr)))
+#define read32p(addr)		read32((void *)((uintptr_t)(addr)))
+#define read64p(addr)		read64((void *)((uintptr_t)(addr)))
+#define write8p(addr, value)	write8((void *)((uintptr_t)(addr)), value)
+#define write16p(addr, value)	write16((void *)((uintptr_t)(addr)), value)
+#define write32p(addr, value)	write32((void *)((uintptr_t)(addr)), value)
+#define write64p(addr, value)	write64((void *)((uintptr_t)(addr)), value)
+
+/* Handy bit manipulation macros */
+
+#define __clrsetbits(endian, bits, addr, clear, set) \
+	write##bits(addr, hto##endian##bits((endian##bits##toh( \
+		read##bits(addr)) & ~((uint##bits##_t)(clear))) | (set)))
+
+#define clrbits_le64(addr, clear)	__clrsetbits(le, 64, addr, clear, 0)
+#define clrbits_be64(addr, clear)	__clrsetbits(be, 64, addr, clear, 0)
+#define clrbits_le32(addr, clear)	__clrsetbits(le, 32, addr, clear, 0)
+#define clrbits_be32(addr, clear)	__clrsetbits(be, 32, addr, clear, 0)
+#define clrbits_le16(addr, clear)	__clrsetbits(le, 16, addr, clear, 0)
+#define clrbits_be16(addr, clear)	__clrsetbits(be, 16, addr, clear, 0)
+
+#define setbits_le64(addr, set)		__clrsetbits(le, 64, addr, 0, set)
+#define setbits_be64(addr, set)		__clrsetbits(be, 64, addr, 0, set)
+#define setbits_le32(addr, set)		__clrsetbits(le, 32, addr, 0, set)
+#define setbits_be32(addr, set)		__clrsetbits(be, 32, addr, 0, set)
+#define setbits_le16(addr, set)		__clrsetbits(le, 16, addr, 0, set)
+#define setbits_be16(addr, set)		__clrsetbits(be, 16, addr, 0, set)
+
+#define clrsetbits_le64(addr, clear, set) __clrsetbits(le, 64, addr, clear, set)
+#define clrsetbits_be64(addr, clear, set) __clrsetbits(be, 64, addr, clear, set)
+#define clrsetbits_le32(addr, clear, set) __clrsetbits(le, 32, addr, clear, set)
+#define clrsetbits_be32(addr, clear, set) __clrsetbits(be, 32, addr, clear, set)
+#define clrsetbits_le16(addr, clear, set) __clrsetbits(le, 16, addr, clear, set)
+#define clrsetbits_be16(addr, clear, set) __clrsetbits(be, 16, addr, clear, set)
+
+#define __clrsetbits_impl(bits, addr, clear, set) write##bits(addr, \
+	(read##bits(addr) & ~((uint##bits##_t)(clear))) | (set))
+
+#define clrsetbits8(addr, clear, set)	__clrsetbits_impl(8, addr, clear, set)
+#define clrsetbits16(addr, clear, set)	__clrsetbits_impl(16, addr, clear, set)
+#define clrsetbits32(addr, clear, set)	__clrsetbits_impl(32, addr, clear, set)
+#define clrsetbits64(addr, clear, set)	__clrsetbits_impl(64, addr, clear, set)
+
+#define setbits8(addr, set)		clrsetbits8(addr, 0, set)
+#define setbits16(addr, set)		clrsetbits16(addr, 0, set)
+#define setbits32(addr, set)		clrsetbits32(addr, 0, set)
+#define setbits64(addr, set)		clrsetbits64(addr, 0, set)
+
+#define clrbits8(addr, clear)		clrsetbits8(addr, clear, 0)
+#define clrbits16(addr, clear)		clrsetbits16(addr, clear, 0)
+#define clrbits32(addr, clear)		clrsetbits32(addr, clear, 0)
+#define clrbits64(addr, clear)		clrsetbits64(addr, clear, 0)
+
+#define clrsetbits8p(addr, clear, set)	clrsetbits8((void *)((uintptr_t)(addr)), clear, set)
+#define clrsetbits16p(addr, clear, set)	clrsetbits16((void *)((uintptr_t)(addr)), clear, set)
+#define clrsetbits32p(addr, clear, set)	clrsetbits32((void *)((uintptr_t)(addr)), clear, set)
+#define clrsetbits64p(addr, clear, set)	clrsetbits64((void *)((uintptr_t)(addr)), clear, set)
+
+#define setbits8p(addr, set)		clrsetbits8((void *)((uintptr_t)(addr)), 0, set)
+#define setbits16p(addr, set)		clrsetbits16((void *)((uintptr_t)(addr)), 0, set)
+#define setbits32p(addr, set)		clrsetbits32((void *)((uintptr_t)(addr)), 0, set)
+#define setbits64p(addr, set)		clrsetbits64((void *)((uintptr_t)(addr)), 0, set)
+
+#define clrbits8p(addr, clear)		clrsetbits8((void *)((uintptr_t)(addr)), clear, 0)
+#define clrbits16p(addr, clear)		clrsetbits16((void *)((uintptr_t)(addr)), clear, 0)
+#define clrbits32p(addr, clear)		clrsetbits32((void *)((uintptr_t)(addr)), clear, 0)
+#define clrbits64p(addr, clear)		clrsetbits64((void *)((uintptr_t)(addr)), clear, 0)
+
+#endif /* _COMMONLIB_BSD__ENDIAN_H_ */
diff --git a/src/include/device/mmio.h b/src/include/device/mmio.h
index 2b9949e05a..d6b8b26398 100644
--- a/src/include/device/mmio.h
+++ b/src/include/device/mmio.h
@@ -8,39 +8,6 @@
 #include <endian.h>
 #include <types.h>
 
-#define __clrsetbits_impl(bits, addr, clear, set) write##bits(addr, \
-	(read##bits(addr) & ~((uint##bits##_t)(clear))) | (set))
-
-#define clrsetbits8(addr, clear, set)	__clrsetbits_impl(8, addr, clear, set)
-#define clrsetbits16(addr, clear, set)	__clrsetbits_impl(16, addr, clear, set)
-#define clrsetbits32(addr, clear, set)	__clrsetbits_impl(32, addr, clear, set)
-#define clrsetbits64(addr, clear, set)	__clrsetbits_impl(64, addr, clear, set)
-
-#define setbits8(addr, set)		clrsetbits8(addr, 0, set)
-#define setbits16(addr, set)		clrsetbits16(addr, 0, set)
-#define setbits32(addr, set)		clrsetbits32(addr, 0, set)
-#define setbits64(addr, set)		clrsetbits64(addr, 0, set)
-
-#define clrbits8(addr, clear)		clrsetbits8(addr, clear, 0)
-#define clrbits16(addr, clear)		clrsetbits16(addr, clear, 0)
-#define clrbits32(addr, clear)		clrsetbits32(addr, clear, 0)
-#define clrbits64(addr, clear)		clrsetbits64(addr, clear, 0)
-
-#define clrsetbits8p(addr, clear, set)	clrsetbits8((void *)((uintptr_t)addr), clear, set)
-#define clrsetbits16p(addr, clear, set)	clrsetbits16((void *)((uintptr_t)addr), clear, set)
-#define clrsetbits32p(addr, clear, set)	clrsetbits32((void *)((uintptr_t)addr), clear, set)
-#define clrsetbits64p(addr, clear, set)	clrsetbits64((void *)((uintptr_t)addr), clear, set)
-
-#define setbits8p(addr, set)		clrsetbits8((void *)((uintptr_t)addr), 0, set)
-#define setbits16p(addr, set)		clrsetbits16((void *)((uintptr_t)addr), 0, set)
-#define setbits32p(addr, set)		clrsetbits32((void *)((uintptr_t)addr), 0, set)
-#define setbits64p(addr, set)		clrsetbits64((void *)((uintptr_t)addr), 0, set)
-
-#define clrbits8p(addr, clear)		clrsetbits8((void *)((uintptr_t)addr), clear, 0)
-#define clrbits16p(addr, clear)		clrsetbits16((void *)((uintptr_t)addr), clear, 0)
-#define clrbits32p(addr, clear)		clrsetbits32((void *)((uintptr_t)addr), clear, 0)
-#define clrbits64p(addr, clear)		clrsetbits64((void *)((uintptr_t)addr), clear, 0)
-
 /*
  * Reads a transfer buffer from 32-bit FIFO registers. fifo_stride is the
  * distance in bytes between registers (e.g. pass 4 for a normal array of 32-bit
@@ -222,44 +189,4 @@ static inline void buffer_to_fifo32(const void *buffer, size_t size, void *fifo,
 #define READ32_BITFIELD(addr, name) \
 	EXTRACT_BITFIELD(read32(addr), name)
 
-static __always_inline uint8_t read8p(const uintptr_t addr)
-{
-	return read8((void *)addr);
-}
-
-static __always_inline uint16_t read16p(const uintptr_t addr)
-{
-	return read16((void *)addr);
-}
-
-static __always_inline uint32_t read32p(const uintptr_t addr)
-{
-	return read32((void *)addr);
-}
-
-static __always_inline uint64_t read64p(const uintptr_t addr)
-{
-	return read64((void *)addr);
-}
-
-static __always_inline void write8p(const uintptr_t addr, const uint8_t value)
-{
-	write8((void *)addr, value);
-}
-
-static __always_inline void write16p(const uintptr_t addr, const uint16_t value)
-{
-	write16((void *)addr, value);
-}
-
-static __always_inline void write32p(const uintptr_t addr, const uint32_t value)
-{
-	write32((void *)addr, value);
-}
-
-static __always_inline void write64p(const uintptr_t addr, const uint64_t value)
-{
-	write64((void *)addr, value);
-}
-
 #endif	/* __DEVICE_MMIO_H__ */
diff --git a/src/include/endian.h b/src/include/endian.h
index 5cdcb2db54..efc56dd7be 100644
--- a/src/include/endian.h
+++ b/src/include/endian.h
@@ -8,173 +8,20 @@
 #include <string.h>
 #include <swab.h>
 
-#if defined(__LITTLE_ENDIAN)
-	#define cpu_to_le64(x) ((uint64_t)(x))
-	#define le64_to_cpu(x) ((uint64_t)(x))
-	#define cpu_to_le32(x) ((uint32_t)(x))
-	#define le32_to_cpu(x) ((uint32_t)(x))
-	#define cpu_to_le16(x) ((uint16_t)(x))
-	#define le16_to_cpu(x) ((uint16_t)(x))
-	#define cpu_to_be64(x) swab64(x)
-	#define be64_to_cpu(x) swab64(x)
-	#define cpu_to_be32(x) swab32(x)
-	#define be32_to_cpu(x) swab32(x)
-	#define cpu_to_be16(x) swab16(x)
-	#define be16_to_cpu(x) swab16(x)
-#elif defined(__BIG_ENDIAN)
-	#define cpu_to_le64(x) swab64(x)
-	#define le64_to_cpu(x) swab64(x)
-	#define cpu_to_le32(x) swab32(x)
-	#define le32_to_cpu(x) swab32(x)
-	#define cpu_to_le16(x) swab16(x)
-	#define le16_to_cpu(x) swab16(x)
-	#define cpu_to_be64(x) ((uint64_t)(x))
-	#define be64_to_cpu(x) ((uint64_t)(x))
-	#define cpu_to_be32(x) ((uint32_t)(x))
-	#define be32_to_cpu(x) ((uint32_t)(x))
-	#define cpu_to_be16(x) ((uint16_t)(x))
-	#define be16_to_cpu(x) ((uint16_t)(x))
-#else
-	#error "<arch/byteorder.h> must #define __LITTLE_ENDIAN or __BIG_ENDIAN"
-#endif
+/* This include depends on previous ones, do not reorder. */
+#include <commonlib/bsd/_endian.h>
 
-#define ntohll(x) be64_to_cpu(x)
-#define htonll(x) cpu_to_be64(x)
-#define ntohl(x)  be32_to_cpu(x)
-#define htonl(x)  cpu_to_be32(x)
-
-#define __clrsetbits(endian, bits, addr, clear, set) \
-	write##bits(addr, cpu_to_##endian##bits((endian##bits##_to_cpu( \
-		read##bits(addr)) & ~((uint##bits##_t)(clear))) | (set)))
-
-#define clrbits_le64(addr, clear)	__clrsetbits(le, 64, addr, clear, 0)
-#define clrbits_be64(addr, clear)	__clrsetbits(be, 64, addr, clear, 0)
-#define clrbits_le32(addr, clear)	__clrsetbits(le, 32, addr, clear, 0)
-#define clrbits_be32(addr, clear)	__clrsetbits(be, 32, addr, clear, 0)
-#define clrbits_le16(addr, clear)	__clrsetbits(le, 16, addr, clear, 0)
-#define clrbits_be16(addr, clear)	__clrsetbits(be, 16, addr, clear, 0)
-
-#define setbits_le64(addr, set)		__clrsetbits(le, 64, addr, 0, set)
-#define setbits_be64(addr, set)		__clrsetbits(be, 64, addr, 0, set)
-#define setbits_le32(addr, set)		__clrsetbits(le, 32, addr, 0, set)
-#define setbits_be32(addr, set)		__clrsetbits(be, 32, addr, 0, set)
-#define setbits_le16(addr, set)		__clrsetbits(le, 16, addr, 0, set)
-#define setbits_be16(addr, set)		__clrsetbits(be, 16, addr, 0, set)
-
-#define clrsetbits_le64(addr, clear, set) __clrsetbits(le, 64, addr, clear, set)
-#define clrsetbits_be64(addr, clear, set) __clrsetbits(be, 64, addr, clear, set)
-#define clrsetbits_le32(addr, clear, set) __clrsetbits(le, 32, addr, clear, set)
-#define clrsetbits_be32(addr, clear, set) __clrsetbits(be, 32, addr, clear, set)
-#define clrsetbits_le16(addr, clear, set) __clrsetbits(le, 16, addr, clear, set)
-#define clrsetbits_be16(addr, clear, set) __clrsetbits(be, 16, addr, clear, set)
-
-/*
- * be16dec/be32dec/be64dec/le16dec/le32dec/le64dec family of functions.
- * RISC-V doesn't support misaligned access so decode it byte by byte.
- */
-#define DEFINE_ENDIAN_DEC(endian, width) \
-	static inline uint##width##_t endian##width##dec(const void *p) \
-	{ \
-		if (ENV_RISCV) { \
-			uint##width##_t val; \
-			memcpy(&val, p, sizeof(val)); \
-			return endian##width##_to_cpu(val); \
-		} else { \
-			return endian##width##_to_cpu(*(uint##width##_t *)p); \
-		} \
-	}
-
-DEFINE_ENDIAN_DEC(be, 16)
-DEFINE_ENDIAN_DEC(be, 32)
-DEFINE_ENDIAN_DEC(be, 64)
-DEFINE_ENDIAN_DEC(le, 16)
-DEFINE_ENDIAN_DEC(le, 32)
-DEFINE_ENDIAN_DEC(le, 64)
-
-/*
- * be16enc/be32enc/be64enc/le16enc/le32enc/le64enc family of functions.
- * RISC-V doesn't support misaligned access so encode it byte by byte.
- */
-#define DEFINE_ENDIAN_ENC(endian, width) \
-	static inline void endian##width##enc(void *p, uint##width##_t u) \
-	{ \
-		if (ENV_RISCV) { \
-			uint##width##_t val = cpu_to_##endian##width(u); \
-			memcpy(p, &val, sizeof(val)); \
-		} else { \
-			*(uint##width##_t *)p = cpu_to_##endian##width(u); \
-		} \
-	}
-
-DEFINE_ENDIAN_ENC(be, 16)
-DEFINE_ENDIAN_ENC(be, 32)
-DEFINE_ENDIAN_ENC(be, 64)
-DEFINE_ENDIAN_ENC(le, 16)
-DEFINE_ENDIAN_ENC(le, 32)
-DEFINE_ENDIAN_ENC(le, 64)
-
-/*
- * Portable (API) endian support that can be used in code that is shared
- * with userspace (man 3 endian) tools.
- */
-static inline uint16_t htobe16(uint16_t host_16bits)
-{
-	return cpu_to_be16(host_16bits);
-}
-
-static inline uint16_t htole16(uint16_t host_16bits)
-{
-	return cpu_to_le16(host_16bits);
-}
-
-static inline uint16_t be16toh(uint16_t big_endian_16bits)
-{
-	return be16_to_cpu(big_endian_16bits);
-}
-
-static inline uint16_t le16toh(uint16_t little_endian_16bits)
-{
-	return le16_to_cpu(little_endian_16bits);
-}
-
-static inline uint32_t htobe32(uint32_t host_32bits)
-{
-	return cpu_to_be32(host_32bits);
-}
-
-static inline uint32_t htole32(uint32_t host_32bits)
-{
-	return cpu_to_le32(host_32bits);
-}
-
-static inline uint32_t be32toh(uint32_t big_endian_32bits)
-{
-	return be32_to_cpu(big_endian_32bits);
-}
-
-static inline uint32_t le32toh(uint32_t little_endian_32bits)
-{
-	return le32_to_cpu(little_endian_32bits);
-}
-
-static inline uint64_t htobe64(uint64_t host_64bits)
-{
-	return cpu_to_be64(host_64bits);
-}
-
-static inline uint64_t htole64(uint64_t host_64bits)
-{
-	return cpu_to_le64(host_64bits);
-}
-
-static inline uint64_t be64toh(uint64_t big_endian_64bits)
-{
-	return be64_to_cpu(big_endian_64bits);
-}
-
-static inline uint64_t le64toh(uint64_t little_endian_64bits)
-{
-	return le64_to_cpu(little_endian_64bits);
-}
+#define be64_to_cpu(x) be64toh(x)
+#define be32_to_cpu(x) be32toh(x)
+#define be16_to_cpu(x) be16toh(x)
+#define le64_to_cpu(x) le64toh(x)
+#define le32_to_cpu(x) le32toh(x)
+#define le16_to_cpu(x) le16toh(x)
+#define cpu_to_be64(x) htobe64(x)
+#define cpu_to_be32(x) htobe32(x)
+#define cpu_to_be16(x) htobe16(x)
+#define cpu_to_le64(x) htole64(x)
+#define cpu_to_le32(x) htole32(x)
+#define cpu_to_le16(x) htole16(x)
 
 #endif

From d5ea359347ef0787e38bf42c2fe4e9fbc7c1524b Mon Sep 17 00:00:00 2001
From: Integral <integral@member.fsf.org>
Date: Tue, 9 Dec 2025 23:35:36 +0800
Subject: [PATCH 2752/3886] soc/intel/**/cfr.h: Fix typo of "ACPI" in UI help
 text

Correct "APCI" to "ACPI" in the UI help text.

Change-Id: I56343c82b2ddc73e565501f723538fbe96877cd6
Signed-off-by: Integral <integral@member.fsf.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90431
Reviewed-by: Jakub "Kuba" Czapiga <czapiga@google.com>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/soc/intel/alderlake/include/soc/cfr.h  | 2 +-
 src/soc/intel/cannonlake/include/soc/cfr.h | 2 +-
 src/soc/intel/jasperlake/include/soc/cfr.h | 2 +-
 src/soc/intel/meteorlake/include/soc/cfr.h | 2 +-
 src/soc/intel/skylake/include/soc/cfr.h    | 2 +-
 src/soc/intel/tigerlake/include/soc/cfr.h  | 2 +-
 6 files changed, 6 insertions(+), 6 deletions(-)

diff --git a/src/soc/intel/alderlake/include/soc/cfr.h b/src/soc/intel/alderlake/include/soc/cfr.h
index 1e54d585f1..b31302ae05 100644
--- a/src/soc/intel/alderlake/include/soc/cfr.h
+++ b/src/soc/intel/alderlake/include/soc/cfr.h
@@ -73,7 +73,7 @@ static const struct sm_object legacy_8254_timer = SM_DECLARE_ENUM({
 static const struct sm_object s0ix_enable = SM_DECLARE_ENUM({
 	.opt_name	= "s0ix_enable",
 	.ui_name	= "Modern Standby (S0ix)",
-	.ui_helptext	= "Enabled: use Modern Standby / S0ix. Disabled: use APCI S3 sleep",
+	.ui_helptext	= "Enabled: use Modern Standby / S0ix. Disabled: use ACPI S3 sleep",
 	.default_value	= 1,
 	.values		= (const struct sm_enum_value[]) {
 				{ "Disabled",		0	},
diff --git a/src/soc/intel/cannonlake/include/soc/cfr.h b/src/soc/intel/cannonlake/include/soc/cfr.h
index 1526256703..1c185ef4fe 100644
--- a/src/soc/intel/cannonlake/include/soc/cfr.h
+++ b/src/soc/intel/cannonlake/include/soc/cfr.h
@@ -65,7 +65,7 @@ static const struct sm_object legacy_8254_timer = SM_DECLARE_ENUM({
 static const struct sm_object s0ix_enable = SM_DECLARE_ENUM({
 	.opt_name	= "s0ix_enable",
 	.ui_name	= "Modern Standby (S0ix)",
-	.ui_helptext	= "Enabled: use Modern Standby / S0ix. Disabled: use APCI S3 sleep",
+	.ui_helptext	= "Enabled: use Modern Standby / S0ix. Disabled: use ACPI S3 sleep",
 	.default_value	= 1,
 	.values		= (const struct sm_enum_value[]) {
 				{ "Disabled",		0	},
diff --git a/src/soc/intel/jasperlake/include/soc/cfr.h b/src/soc/intel/jasperlake/include/soc/cfr.h
index 9aca7bb0d0..810369baa3 100644
--- a/src/soc/intel/jasperlake/include/soc/cfr.h
+++ b/src/soc/intel/jasperlake/include/soc/cfr.h
@@ -55,7 +55,7 @@ static const struct sm_object legacy_8254_timer = SM_DECLARE_ENUM({
 static const struct sm_object s0ix_enable = SM_DECLARE_ENUM({
 	.opt_name	= "s0ix_enable",
 	.ui_name	= "Modern Standby (S0ix)",
-	.ui_helptext	= "Enabled: use Modern Standby / S0ix. Disabled: use APCI S3 sleep",
+	.ui_helptext	= "Enabled: use Modern Standby / S0ix. Disabled: use ACPI S3 sleep",
 	.default_value	= 1,
 	.values		= (const struct sm_enum_value[]) {
 				{ "Disabled",		0	},
diff --git a/src/soc/intel/meteorlake/include/soc/cfr.h b/src/soc/intel/meteorlake/include/soc/cfr.h
index c8db514c99..66fb3c838a 100644
--- a/src/soc/intel/meteorlake/include/soc/cfr.h
+++ b/src/soc/intel/meteorlake/include/soc/cfr.h
@@ -53,7 +53,7 @@ static const struct sm_object legacy_8254_timer = SM_DECLARE_ENUM({
 static const struct sm_object s0ix_enable = SM_DECLARE_ENUM({
 	.opt_name	= "s0ix_enable",
 	.ui_name	= "Modern Standby (S0ix)",
-	.ui_helptext	= "Enabled: use Modern Standby / S0ix. Disabled: use APCI S3 sleep",
+	.ui_helptext	= "Enabled: use Modern Standby / S0ix. Disabled: use ACPI S3 sleep",
 	.default_value	= 1,
 	.values		= (const struct sm_enum_value[]) {
 				{ "Disabled",		0	},
diff --git a/src/soc/intel/skylake/include/soc/cfr.h b/src/soc/intel/skylake/include/soc/cfr.h
index 52899015d3..bcbf57f062 100644
--- a/src/soc/intel/skylake/include/soc/cfr.h
+++ b/src/soc/intel/skylake/include/soc/cfr.h
@@ -65,7 +65,7 @@ static const struct sm_object legacy_8254_timer = SM_DECLARE_ENUM({
 static const struct sm_object s0ix_enable = SM_DECLARE_ENUM({
 	.opt_name	= "s0ix_enable",
 	.ui_name	= "Modern Standby (S0ix)",
-	.ui_helptext	= "Enabled: use Modern Standby / S0ix. Disabled: use APCI S3 sleep",
+	.ui_helptext	= "Enabled: use Modern Standby / S0ix. Disabled: use ACPI S3 sleep",
 	.default_value	= 1,
 	.values		= (const struct sm_enum_value[]) {
 				{ "Disabled",		0	},
diff --git a/src/soc/intel/tigerlake/include/soc/cfr.h b/src/soc/intel/tigerlake/include/soc/cfr.h
index 529a4eba79..3154e05a87 100644
--- a/src/soc/intel/tigerlake/include/soc/cfr.h
+++ b/src/soc/intel/tigerlake/include/soc/cfr.h
@@ -73,7 +73,7 @@ static const struct sm_object legacy_8254_timer = SM_DECLARE_ENUM({
 static const struct sm_object s0ix_enable = SM_DECLARE_ENUM({
 	.opt_name	= "s0ix_enable",
 	.ui_name	= "Modern Standby (S0ix)",
-	.ui_helptext	= "Enabled: use Modern Standby / S0ix. Disabled: use APCI S3 sleep",
+	.ui_helptext	= "Enabled: use Modern Standby / S0ix. Disabled: use ACPI S3 sleep",
 	.default_value	= 1,
 	.values		= (const struct sm_enum_value[]) {
 				{ "Disabled",		0	},

From 7f93e2fe29fc38ffba1d8e8c78ada4990784b461 Mon Sep 17 00:00:00 2001
From: Ulysse Ballesteros <ulysse.ballesteros@outlook.fr>
Date: Sun, 26 Oct 2025 22:26:43 +0100
Subject: [PATCH 2753/3886] soc/intel/*: Add CFR option to enable/disable the
 Intel iGPU

TEST=Build and boot to OS. Verify functions work. (skylake)

Change-Id: I9d25c04302d23afd9b95625ddf03dfeee2fdf7c2
Signed-off-by: Ulysse Ballesteros <ulysse.ballesteros@outlook.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89752
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Jakub "Kuba" Czapiga <czapiga@google.com>
---
 src/soc/intel/alderlake/include/soc/cfr.h      | 16 ++++++++++++++--
 src/soc/intel/alderlake/romstage/fsp_params.c  |  2 +-
 src/soc/intel/cannonlake/include/soc/cfr.h     | 16 ++++++++++++++--
 src/soc/intel/cannonlake/romstage/fsp_params.c |  2 +-
 src/soc/intel/jasperlake/include/soc/cfr.h     | 16 ++++++++++++++--
 src/soc/intel/jasperlake/romstage/fsp_params.c |  2 +-
 src/soc/intel/meteorlake/include/soc/cfr.h     | 14 +++++++++++++-
 src/soc/intel/meteorlake/romstage/fsp_params.c |  2 +-
 src/soc/intel/skylake/include/soc/cfr.h        | 16 ++++++++++++++--
 src/soc/intel/skylake/romstage/fsp_params.c    |  2 +-
 src/soc/intel/tigerlake/include/soc/cfr.h      | 16 ++++++++++++++--
 src/soc/intel/tigerlake/romstage/fsp_params.c  |  2 +-
 12 files changed, 89 insertions(+), 17 deletions(-)

diff --git a/src/soc/intel/alderlake/include/soc/cfr.h b/src/soc/intel/alderlake/include/soc/cfr.h
index b31302ae05..1cacac618c 100644
--- a/src/soc/intel/alderlake/include/soc/cfr.h
+++ b/src/soc/intel/alderlake/include/soc/cfr.h
@@ -22,6 +22,18 @@ static const struct sm_object hyper_threading = SM_DECLARE_ENUM({
 				SM_ENUM_VALUE_END		},
 });
 
+/* IGD Enabled */
+static const struct sm_object igd_enabled = SM_DECLARE_ENUM({
+	.opt_name	= "igd_enabled",
+	.ui_name	= "Enable the Intel iGPU",
+	.ui_helptext	= "Enable or disable the Intel iGPU",
+	.default_value	= !CONFIG(SOC_INTEL_DISABLE_IGD),
+	.values		= (const struct sm_enum_value[]) {
+				{ "Disabled",		0	},
+				{ "Enabled",		1	},
+				SM_ENUM_VALUE_END		},
+});
+
 /* IGD Aperture Size */
 static const struct sm_object igd_aperture = SM_DECLARE_ENUM({
 	.opt_name	= "igd_aperture_size",
@@ -39,7 +51,7 @@ static const struct sm_object igd_aperture = SM_DECLARE_ENUM({
 				{ " 512 MB",		IGD_AP_SZ_512MB		},
 #endif
 				SM_ENUM_VALUE_END				},
-});
+}, WITH_DEP_VALUES(&igd_enabled, 1));
 
 /* IGD DVMT pre-allocated memory */
 static const struct sm_object igd_dvmt = SM_DECLARE_ENUM({
@@ -55,7 +67,7 @@ static const struct sm_object igd_dvmt = SM_DECLARE_ENUM({
 				{ "128 MB",		IGD_SM_128MB	},
 				{ "160 MB",		IGD_SM_160MB	},
 				SM_ENUM_VALUE_END			},
-});
+}, WITH_DEP_VALUES(&igd_enabled, 1));
 
 /* Legacy 8254 Timer */
 static const struct sm_object legacy_8254_timer = SM_DECLARE_ENUM({
diff --git a/src/soc/intel/alderlake/romstage/fsp_params.c b/src/soc/intel/alderlake/romstage/fsp_params.c
index 041b0fb4e1..730b1f82b2 100644
--- a/src/soc/intel/alderlake/romstage/fsp_params.c
+++ b/src/soc/intel/alderlake/romstage/fsp_params.c
@@ -152,7 +152,7 @@ static void fill_fspm_igd_params(FSP_M_CONFIG *m_cfg,
 		[DDI_PORT_3] = {&m_cfg->DdiPort3Ddc, &m_cfg->DdiPort3Hpd},
 		[DDI_PORT_4] = {&m_cfg->DdiPort4Ddc, &m_cfg->DdiPort4Hpd},
 	};
-	m_cfg->InternalGfx = !CONFIG(SOC_INTEL_DISABLE_IGD) && is_devfn_enabled(SA_DEVFN_IGD);
+	m_cfg->InternalGfx = get_uint_option("igd_enabled", !CONFIG(SOC_INTEL_DISABLE_IGD)) && is_devfn_enabled(SA_DEVFN_IGD);
 	if (m_cfg->InternalGfx) {
 		/* IGD is enabled, set IGD stolen size to 60MB. */
 		m_cfg->IgdDvmt50PreAlloc = get_uint_option("igd_dvmt_prealloc", IGD_SM_60MB);
diff --git a/src/soc/intel/cannonlake/include/soc/cfr.h b/src/soc/intel/cannonlake/include/soc/cfr.h
index 1c185ef4fe..d177d2db83 100644
--- a/src/soc/intel/cannonlake/include/soc/cfr.h
+++ b/src/soc/intel/cannonlake/include/soc/cfr.h
@@ -22,6 +22,18 @@ static const struct sm_object hyper_threading = SM_DECLARE_ENUM({
 				SM_ENUM_VALUE_END		},
 });
 
+/* IGD Enabled */
+static const struct sm_object igd_enabled = SM_DECLARE_ENUM({
+	.opt_name	= "igd_enabled",
+	.ui_name	= "Enable the Intel iGPU",
+	.ui_helptext	= "Enable or disable the Intel iGPU",
+	.default_value	= !CONFIG(SOC_INTEL_DISABLE_IGD),
+	.values		= (const struct sm_enum_value[]) {
+				{ "Disabled",		0	},
+				{ "Enabled",		1	},
+				SM_ENUM_VALUE_END		},
+});
+
 /* IGD Aperture Size */
 static const struct sm_object igd_aperture = SM_DECLARE_ENUM({
 	.opt_name	= "igd_aperture_size",
@@ -33,7 +45,7 @@ static const struct sm_object igd_aperture = SM_DECLARE_ENUM({
 				{ "256 MB",	IGD_AP_SZ_256MB	},
 				{ "512 MB",	IGD_AP_SZ_512MB	},
 				SM_ENUM_VALUE_END		},
-});
+}, WITH_DEP_VALUES(&igd_enabled, 1));
 
 /* IGD DVMT pre-allocated memory */
 static const struct sm_object igd_dvmt = SM_DECLARE_ENUM({
@@ -47,7 +59,7 @@ static const struct sm_object igd_dvmt = SM_DECLARE_ENUM({
 				{ "96 MB",	IGD_SM_96MB	},
 				{ "128 MB",	IGD_SM_128MB	},
 				SM_ENUM_VALUE_END		},
-});
+}, WITH_DEP_VALUES(&igd_enabled, 1));
 
 /* Legacy 8254 Timer */
 static const struct sm_object legacy_8254_timer = SM_DECLARE_ENUM({
diff --git a/src/soc/intel/cannonlake/romstage/fsp_params.c b/src/soc/intel/cannonlake/romstage/fsp_params.c
index a8523f14ab..38dfdd8922 100644
--- a/src/soc/intel/cannonlake/romstage/fsp_params.c
+++ b/src/soc/intel/cannonlake/romstage/fsp_params.c
@@ -34,7 +34,7 @@ void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version)
 	 * Probe for no IGD and disable InternalGfx and panel power to prevent a
 	 * crash in FSP-M.
 	 */
-	const bool igd_on = !CONFIG(SOC_INTEL_DISABLE_IGD) && is_devfn_enabled(SA_DEVFN_IGD);
+	const bool igd_on = get_uint_option("igd_enabled", !CONFIG(SOC_INTEL_DISABLE_IGD)) && is_devfn_enabled(SA_DEVFN_IGD);
 	if (igd_on && pci_read_config16(SA_DEV_IGD, PCI_VENDOR_ID) != 0xffff) {
 		/* Set IGD stolen size to 64MB. */
 		m_cfg->InternalGfx = 1;
diff --git a/src/soc/intel/jasperlake/include/soc/cfr.h b/src/soc/intel/jasperlake/include/soc/cfr.h
index 810369baa3..c275324d65 100644
--- a/src/soc/intel/jasperlake/include/soc/cfr.h
+++ b/src/soc/intel/jasperlake/include/soc/cfr.h
@@ -10,6 +10,18 @@
 #include <drivers/option/cfr_frontend.h>
 #include <soc/soc_chip.h>
 
+/* IGD Enabled */
+static const struct sm_object igd_enabled = SM_DECLARE_ENUM({
+	.opt_name	= "igd_enabled",
+	.ui_name	= "Enable the Intel iGPU",
+	.ui_helptext	= "Enable or disable the Intel iGPU",
+	.default_value	= !CONFIG(SOC_INTEL_DISABLE_IGD),
+	.values		= (const struct sm_enum_value[]) {
+				{ "Disabled",		0	},
+				{ "Enabled",		1	},
+				SM_ENUM_VALUE_END		},
+});
+
 /* IGD Aperture Size */
 static const struct sm_object igd_aperture = SM_DECLARE_ENUM({
 	.opt_name	= "igd_aperture_size",
@@ -21,7 +33,7 @@ static const struct sm_object igd_aperture = SM_DECLARE_ENUM({
 				{ " 256 MB",		IGD_AP_SZ_256MB		},
 				{ " 512 MB",		IGD_AP_SZ_512MB		},
 				SM_ENUM_VALUE_END				},
-});
+}, WITH_DEP_VALUES(&igd_enabled, 1));
 
 /* IGD DVMT pre-allocated memory */
 static const struct sm_object igd_dvmt = SM_DECLARE_ENUM({
@@ -37,7 +49,7 @@ static const struct sm_object igd_dvmt = SM_DECLARE_ENUM({
 				{ "128 MB",		IGD_SM_128MB	},
 				{ "160 MB",		IGD_SM_160MB	},
 				SM_ENUM_VALUE_END			},
-});
+}, WITH_DEP_VALUES(&igd_enabled, 1));
 
 /* Legacy 8254 Timer */
 static const struct sm_object legacy_8254_timer = SM_DECLARE_ENUM({
diff --git a/src/soc/intel/jasperlake/romstage/fsp_params.c b/src/soc/intel/jasperlake/romstage/fsp_params.c
index b39bd778ba..68d88625b6 100644
--- a/src/soc/intel/jasperlake/romstage/fsp_params.c
+++ b/src/soc/intel/jasperlake/romstage/fsp_params.c
@@ -19,7 +19,7 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg,
 {
 	unsigned int i;
 
-	m_cfg->InternalGfx = !CONFIG(SOC_INTEL_DISABLE_IGD) && is_devfn_enabled(SA_DEVFN_IGD);
+	m_cfg->InternalGfx = get_uint_option("igd_enabled", !CONFIG(SOC_INTEL_DISABLE_IGD)) && is_devfn_enabled(SA_DEVFN_IGD);
 
 	if (m_cfg->InternalGfx) {
 		/* IGD is enabled, set IGD stolen size to 60MB. */
diff --git a/src/soc/intel/meteorlake/include/soc/cfr.h b/src/soc/intel/meteorlake/include/soc/cfr.h
index 66fb3c838a..5379f439c4 100644
--- a/src/soc/intel/meteorlake/include/soc/cfr.h
+++ b/src/soc/intel/meteorlake/include/soc/cfr.h
@@ -22,6 +22,18 @@ static const struct sm_object hyper_threading = SM_DECLARE_ENUM({
 				SM_ENUM_VALUE_END		},
 });
 
+/* IGD Enabled */
+static const struct sm_object igd_enabled = SM_DECLARE_ENUM({
+	.opt_name	= "igd_enabled",
+	.ui_name	= "Enable the Intel iGPU",
+	.ui_helptext	= "Enable or disable the Intel iGPU",
+	.default_value	= !CONFIG(SOC_INTEL_DISABLE_IGD),
+	.values		= (const struct sm_enum_value[]) {
+				{ "Disabled",		0	},
+				{ "Enabled",		1	},
+				SM_ENUM_VALUE_END		},
+});
+
 /* IGD DVMT pre-allocated memory */
 static const struct sm_object igd_dvmt = SM_DECLARE_ENUM({
 	.opt_name	= "igd_dvmt_prealloc",
@@ -35,7 +47,7 @@ static const struct sm_object igd_dvmt = SM_DECLARE_ENUM({
 				{ "128 MB",		IGD_SM_128MB	},
 				{ "160 MB",		IGD_SM_160MB	},
 				SM_ENUM_VALUE_END			},
-});
+}, WITH_DEP_VALUES(&igd_enabled, 1));
 
 /* Legacy 8254 Timer */
 static const struct sm_object legacy_8254_timer = SM_DECLARE_ENUM({
diff --git a/src/soc/intel/meteorlake/romstage/fsp_params.c b/src/soc/intel/meteorlake/romstage/fsp_params.c
index f16def4aef..cec8304281 100644
--- a/src/soc/intel/meteorlake/romstage/fsp_params.c
+++ b/src/soc/intel/meteorlake/romstage/fsp_params.c
@@ -123,7 +123,7 @@ static void fill_fspm_igd_params(FSP_M_CONFIG *m_cfg,
 		[DDI_PORT_3] = {&m_cfg->DdiPort3Ddc, &m_cfg->DdiPort3Hpd},
 		[DDI_PORT_4] = {&m_cfg->DdiPort4Ddc, &m_cfg->DdiPort4Hpd},
 	};
-	m_cfg->InternalGfx = !CONFIG(SOC_INTEL_DISABLE_IGD) && is_devfn_enabled(PCI_DEVFN_IGD);
+	m_cfg->InternalGfx = get_uint_option("igd_enabled", !CONFIG(SOC_INTEL_DISABLE_IGD)) && is_devfn_enabled(PCI_DEVFN_IGD);
 	if (m_cfg->InternalGfx) {
 		/* IGD is enabled, set IGD stolen size to 128MB. */
 		m_cfg->IgdDvmt50PreAlloc = get_uint_option("igd_dvmt_prealloc", IGD_SM_128MB);
diff --git a/src/soc/intel/skylake/include/soc/cfr.h b/src/soc/intel/skylake/include/soc/cfr.h
index bcbf57f062..355dea6b8f 100644
--- a/src/soc/intel/skylake/include/soc/cfr.h
+++ b/src/soc/intel/skylake/include/soc/cfr.h
@@ -22,6 +22,18 @@ static const struct sm_object hyper_threading = SM_DECLARE_ENUM({
 				SM_ENUM_VALUE_END		},
 });
 
+/* IGD Enabled */
+static const struct sm_object igd_enabled = SM_DECLARE_ENUM({
+	.opt_name	= "igd_enabled",
+	.ui_name	= "Enable the Intel iGPU",
+	.ui_helptext	= "Enable or disable the Intel iGPU",
+	.default_value	= !CONFIG(SOC_INTEL_DISABLE_IGD),
+	.values		= (const struct sm_enum_value[]) {
+				{ "Disabled",		0	},
+				{ "Enabled",		1	},
+				SM_ENUM_VALUE_END		},
+});
+
 /* IGD Aperture Size */
 static const struct sm_object igd_aperture = SM_DECLARE_ENUM({
 	.opt_name	= "igd_aperture_size",
@@ -33,7 +45,7 @@ static const struct sm_object igd_aperture = SM_DECLARE_ENUM({
 				{ "256 MB",	IGD_AP_SZ_256MB	},
 				{ "512 MB",	IGD_AP_SZ_512MB	},
 				SM_ENUM_VALUE_END		},
-});
+}, WITH_DEP_VALUES(&igd_enabled, 1));
 
 /* IGD DVMT pre-allocated memory */
 static const struct sm_object igd_dvmt = SM_DECLARE_ENUM({
@@ -47,7 +59,7 @@ static const struct sm_object igd_dvmt = SM_DECLARE_ENUM({
 				{ "96 MB",	IGD_SM_96MB	},
 				{ "128 MB",	IGD_SM_128MB	},
 				SM_ENUM_VALUE_END		},
-});
+}, WITH_DEP_VALUES(&igd_enabled, 1));
 
 /* Legacy 8254 Timer */
 static const struct sm_object legacy_8254_timer = SM_DECLARE_ENUM({
diff --git a/src/soc/intel/skylake/romstage/fsp_params.c b/src/soc/intel/skylake/romstage/fsp_params.c
index 02123f837a..3ca8a48472 100644
--- a/src/soc/intel/skylake/romstage/fsp_params.c
+++ b/src/soc/intel/skylake/romstage/fsp_params.c
@@ -104,7 +104,7 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg,
 static void soc_primary_gfx_config_params(FSP_M_CONFIG *m_cfg,
 				const struct soc_intel_skylake_config *config)
 {
-	m_cfg->InternalGfx = !CONFIG(SOC_INTEL_DISABLE_IGD) && is_devfn_enabled(SA_DEVFN_IGD);
+	m_cfg->InternalGfx = get_uint_option("igd_enabled", !CONFIG(SOC_INTEL_DISABLE_IGD)) && is_devfn_enabled(SA_DEVFN_IGD);
 
 	/*
 	 * If iGPU is enabled, set IGD stolen size to 64MB. The FBC
diff --git a/src/soc/intel/tigerlake/include/soc/cfr.h b/src/soc/intel/tigerlake/include/soc/cfr.h
index 3154e05a87..d424946c5a 100644
--- a/src/soc/intel/tigerlake/include/soc/cfr.h
+++ b/src/soc/intel/tigerlake/include/soc/cfr.h
@@ -22,6 +22,18 @@ static const struct sm_object hyper_threading = SM_DECLARE_ENUM({
 				SM_ENUM_VALUE_END		},
 });
 
+/* IGD Enabled */
+static const struct sm_object igd_enabled = SM_DECLARE_ENUM({
+	.opt_name	= "igd_enabled",
+	.ui_name	= "Enable the Intel iGPU",
+	.ui_helptext	= "Enable or disable the Intel iGPU",
+	.default_value	= !CONFIG(SOC_INTEL_DISABLE_IGD),
+	.values		= (const struct sm_enum_value[]) {
+				{ "Disabled",		0	},
+				{ "Enabled",		1	},
+				SM_ENUM_VALUE_END		},
+});
+
 /* IGD Aperture Size */
 static const struct sm_object igd_aperture = SM_DECLARE_ENUM({
 	.opt_name	= "igd_aperture_size",
@@ -39,7 +51,7 @@ static const struct sm_object igd_aperture = SM_DECLARE_ENUM({
 				{ " 512 MB",		IGD_AP_SZ_512MB		},
 #endif
 				SM_ENUM_VALUE_END				},
-});
+}, WITH_DEP_VALUES(&igd_enabled, 1));
 
 /* IGD DVMT pre-allocated memory */
 static const struct sm_object igd_dvmt = SM_DECLARE_ENUM({
@@ -55,7 +67,7 @@ static const struct sm_object igd_dvmt = SM_DECLARE_ENUM({
 				{ "128 MB",		IGD_SM_128MB	},
 				{ "160 MB",		IGD_SM_160MB	},
 				SM_ENUM_VALUE_END			},
-});
+}, WITH_DEP_VALUES(&igd_enabled, 1));
 
 /* Legacy 8254 Timer */
 static const struct sm_object legacy_8254_timer = SM_DECLARE_ENUM({
diff --git a/src/soc/intel/tigerlake/romstage/fsp_params.c b/src/soc/intel/tigerlake/romstage/fsp_params.c
index 82c4c64ff9..3e171b198a 100644
--- a/src/soc/intel/tigerlake/romstage/fsp_params.c
+++ b/src/soc/intel/tigerlake/romstage/fsp_params.c
@@ -27,7 +27,7 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg,
 
 	m_cfg->HyperThreading = get_uint_option("hyper_threading", CONFIG(FSP_HYPERTHREADING));
 
-	m_cfg->InternalGfx = !CONFIG(SOC_INTEL_DISABLE_IGD) && is_devfn_enabled(SA_DEVFN_IGD);
+	m_cfg->InternalGfx = get_uint_option("igd_enabled", !CONFIG(SOC_INTEL_DISABLE_IGD)) && is_devfn_enabled(SA_DEVFN_IGD);
 
 	if (m_cfg->InternalGfx) {
 		/* IGD is enabled, set IGD stolen size to 60MB. */

From 519332de10509d443797d62f58fdccff672bf98f Mon Sep 17 00:00:00 2001
From: Luca Lai <luca.lai@lcfc.corp-partner.google.com>
Date: Thu, 4 Dec 2025 13:31:52 +0800
Subject: [PATCH 2754/3886] mb/google/fatcat/var/ruby: Modify VCCCORE VR Fast
 Vmode ICC limit

For FVM, the function should be enable and set VR Fast Vmode ICC Limit
in BIOS.

According to VRTT test result by PWM IC vendor tuning.
VCCCORE VR Fast Vmode ICC Limit can set as 74A.
VCCGT VR Fast Vmode ICC Limit can set as 38A.
VCCSA VR Fast Vmode ICC Limit can set as 38A.

BUG=b:464422702
TEST=Build and check the system could boot to OS

Change-Id: Ia9dffbfde8d57044392b742d68c62398d6f3dfa3
Signed-off-by: Luca Lai <luca.lai@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90360
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Derek Huang <derekhuang@google.com>
Reviewed-by: YH Lin <yueherngl@google.com>
---
 .../google/fatcat/variants/ruby/overridetree.cb       | 11 +++++++++++
 1 file changed, 11 insertions(+)

diff --git a/src/mainboard/google/fatcat/variants/ruby/overridetree.cb b/src/mainboard/google/fatcat/variants/ruby/overridetree.cb
index 8426b31cbc..c85b2b13c5 100644
--- a/src/mainboard/google/fatcat/variants/ruby/overridetree.cb
+++ b/src/mainboard/google/fatcat/variants/ruby/overridetree.cb
@@ -58,6 +58,17 @@ chip soc/intel/pantherlake
 		.tdp_pl4 = 150,
 	}"
 
+	register "fast_vmode_i_trip[PTL_CORE_1]" = "{
+		[VR_DOMAIN_IA] = 74 * 4,
+		[VR_DOMAIN_GT] = 38 * 4,
+		[VR_DOMAIN_SA] = 38 * 4
+	}"
+	register "fast_vmode_i_trip[PTL_CORE_2]" = "{
+		[VR_DOMAIN_IA] = 74 * 4,
+		[VR_DOMAIN_GT] = 38 * 4,
+		[VR_DOMAIN_SA] = 38 * 4
+	}"
+
 	register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC_SKIP)"	# USB2_C0
 	register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC_SKIP)"	# USB2_C1
 	register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # USB HUB (USB2 Camera)

From c109fc92ff24602e1dd26de92c99c6f059cabc6b Mon Sep 17 00:00:00 2001
From: Jakub Czapiga <czapiga@google.com>
Date: Tue, 9 Dec 2025 10:18:38 +0000
Subject: [PATCH 2755/3886] libpayload: Add API to get physical memory size

sysinfo contains both CBMEM_ID_MEMINFO and CBMEM_ID_MEM_CHIP.
This new function allows to easily retrieve the amount of memory the
system has based on the mentioned CBMEM entries structures.

BUG=b:450374306
TEST=Checked on Google/Brya/Omnigul (x86) - MEMINFO
TEST=Checked on Google/Rauru/Navi (ARM64) - MEM_CHIP

Change-Id: Iaf69c54dfb3d2eaffbccacee8bee3be425b78a3f
Signed-off-by: Jakub Czapiga <czapiga@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90430
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 payloads/libpayload/include/libpayload.h |  9 +++++++++
 payloads/libpayload/libc/sysinfo.c       | 20 ++++++++++++++++++++
 2 files changed, 29 insertions(+)

diff --git a/payloads/libpayload/include/libpayload.h b/payloads/libpayload/include/libpayload.h
index 09bd4be69c..86429144ec 100644
--- a/payloads/libpayload/include/libpayload.h
+++ b/payloads/libpayload/include/libpayload.h
@@ -493,6 +493,15 @@ u8 *sha1(const u8 *data, size_t len, u8 *buf);
  */
 
 int sysinfo_have_multiboot(unsigned long *addr);
+
+/**
+ * Check CBMEM_ID_MEM_CHIP and CBMEM_ID_MEMINFO, extract physical memory size
+ * present in the system.
+ *
+ * @returns physical memory detected in the system or zero in case of failure
+ */
+size_t sysinfo_get_physical_memory_size_mib(void);
+
 /** @} */
 
 /**
diff --git a/payloads/libpayload/libc/sysinfo.c b/payloads/libpayload/libc/sysinfo.c
index cb063fc6f7..e2fa84190c 100644
--- a/payloads/libpayload/libc/sysinfo.c
+++ b/payloads/libpayload/libc/sysinfo.c
@@ -34,3 +34,23 @@ int sysinfo_have_multiboot(unsigned long *addr)
 	*addr = (unsigned long) lib_sysinfo.mbtable;
 	return (lib_sysinfo.mbtable == 0) ? 0 : 1;
 }
+
+size_t sysinfo_get_physical_memory_size_mib(void)
+{
+	const struct mem_chip_info *mc = phys_to_virt(lib_sysinfo.mem_chip_base);
+
+	if (mc)
+		return mem_chip_info_total_density_bytes(mc) / MiB;
+
+#if CONFIG(LP_GPL)
+	const struct memory_info *memory_info = phys_to_virt(lib_sysinfo.memory_info);
+	size_t memory_size_mib = 0;
+	if (memory_info) {
+		for (int i = 0; i < memory_info->dimm_cnt; ++i)
+			memory_size_mib += memory_info->dimm[i].dimm_size;
+		return memory_size_mib;
+	}
+#endif
+
+	return 0;
+}

From d32a3728465d213164a1ac6e3b89d8e5ba41a212 Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Sat, 29 Nov 2025 16:43:01 -0600
Subject: [PATCH 2756/3886] drivers/smmstore: Increase default size of store to
 512KB

The previous default size of 256KB provided for only 64KB of actual
space for EFI variables, and after accounting for fragmentation, did
not provide enough free space for applying updates, such as for the
UEFI revocation database (DBX). Increasing it to 512KB allows for
192KB space for variables, and allows the UEFI DBX to be updated
properly via fwupd.

TEST=build/boot google/drobit, verify UEFI DBX able to be successfully
updated via fwupd.

Change-Id: I8d6a2051f3ad50117d41cec2bbbe3aaafa7e65c2
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90287
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
---
 src/drivers/smmstore/Kconfig | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/drivers/smmstore/Kconfig b/src/drivers/smmstore/Kconfig
index 62aa3aaca8..da3dd28c20 100644
--- a/src/drivers/smmstore/Kconfig
+++ b/src/drivers/smmstore/Kconfig
@@ -23,7 +23,7 @@ if SMMSTORE
 
 config SMMSTORE_SIZE
 	hex "size of the SMMSTORE FMAP region"
-	default 0x40000
+	default 0x80000
 	help
 	  Sets the size of the default SMMSTORE FMAP region.
 	  If using an UEFI payload, note that UEFI specifies at least 64K.

From d7cb2d2bc5544c8dfbeabf0c4b9687ee54c7d81b Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Sat, 29 Nov 2025 16:55:45 -0600
Subject: [PATCH 2757/3886] mb/google/drallion: Increase size of SMMSTORE to
 512KB

Increase size of SMMSTORE FMAP region to 512KB to ensure a large
enough area is allocated to UEFI variable storage which allows for
variables (such as the UEFI revocation database) to be updated
via fwupd. Previously, such updates would fail with an error such as:
"efivar: No space left on device".

Change-Id: I4073f7d1aed589544f072c2a64cada2cdddbe8bf
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90288
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
---
 src/mainboard/google/drallion/default.fmd | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/mainboard/google/drallion/default.fmd b/src/mainboard/google/drallion/default.fmd
index 9d1216b009..4a9738c6c9 100644
--- a/src/mainboard/google/drallion/default.fmd
+++ b/src/mainboard/google/drallion/default.fmd
@@ -2,7 +2,7 @@ FLASH 0x2000000 {
 	SI_BIOS@0x400000 {
 		MEMORY_MAPPED@0xc00000 { /* 16MiB total */
 			RW_MRC_CACHE 0x10000
-			SMMSTORE 0x40000
+			SMMSTORE 0x80000
 			RO_VPD 0x4000
 			FMAP 0x300
 			COREBOOT(CBFS)

From 36a345f99e978bc20a9475ec2a94e36ef4aad521 Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Sat, 29 Nov 2025 16:59:17 -0600
Subject: [PATCH 2758/3886] mb/google/octopus: Increase size of SMMSTORE to
 512KB

Increase size of SMMSTORE FMAP region to 512KB to ensure a large
enough area is allocated to UEFI variable storage which allows for
variables (such as the UEFI revocation database) to be updated
via fwupd. Previously, such updates would fail with an error such as:
"efivar: No space left on device".

Change-Id: Ia7566b31991b6891b4c194ad9b494da2e5ea8e01
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90290
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
---
 src/mainboard/google/octopus/default.fmd | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/mainboard/google/octopus/default.fmd b/src/mainboard/google/octopus/default.fmd
index ca8324381a..67a2a0aed0 100644
--- a/src/mainboard/google/octopus/default.fmd
+++ b/src/mainboard/google/octopus/default.fmd
@@ -3,7 +3,7 @@ FLASH 16M {
 	SI_BIOS@0x1000 0xf7e000 {
 		IFWI@0x0 0x1ff000
 		# SMMSTORE requires 64k alignment
-		SMMSTORE@0xa4f000 0x40000
+		SMMSTORE@0xa4f000 0x80000
 		UNIFIED_MRC_CACHE 0x21000 {
 			RECOVERY_MRC_CACHE 0x10000
 			RW_MRC_CACHE 0x10000

From 91c6a0b5e68bc64450b33c773160dcb4cfd0a137 Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Sat, 29 Nov 2025 16:59:37 -0600
Subject: [PATCH 2759/3886] mb/google/reef: Increase size of SMMSTORE to 512KB

Increase size of SMMSTORE FMAP region to 512KB to ensure a large
enough area is allocated to UEFI variable storage which allows for
variables (such as the UEFI revocation database) to be updated
via fwupd. Previously, such updates would fail with an error such as:
"efivar: No space left on device".

Change-Id: I1ef876de4ccb3a0ed2ff0a96b66c6b02bf274a3e
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90291
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
---
 src/mainboard/google/reef/default.fmd | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/mainboard/google/reef/default.fmd b/src/mainboard/google/reef/default.fmd
index 6eb99b590d..7f60521ab0 100644
--- a/src/mainboard/google/reef/default.fmd
+++ b/src/mainboard/google/reef/default.fmd
@@ -3,7 +3,7 @@ FLASH 16M {
 	SI_BIOS@0x1000 0xf7e000 {
 		IFWI@0x0 0x1ff000
 		# SMMSTORE requires 64k alignment
-		SMMSTORE@0xa4f000 0x40000
+		SMMSTORE@0xa4f000 0x80000
 		UNIFIED_MRC_CACHE 0x21000 {
 			RECOVERY_MRC_CACHE@0x0 0x10000
 			RW_MRC_CACHE 0x10000

From 2e10f75751c16daea3d9384fddcbbc532ae0360b Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Sat, 29 Nov 2025 16:59:52 -0600
Subject: [PATCH 2760/3886] mb/google/sarien: Increase size of SMMSTORE to
 512KB

Increase size of SMMSTORE FMAP region to 512KB to ensure a large
enough area is allocated to UEFI variable storage which allows for
variables (such as the UEFI revocation database) to be updated
via fwupd. Previously, such updates would fail with an error such as:
"efivar: No space left on device".

Change-Id: Ic959d5242879a991da93b33d3bf73beeb1448723
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90292
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
---
 src/mainboard/google/sarien/default.fmd | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/mainboard/google/sarien/default.fmd b/src/mainboard/google/sarien/default.fmd
index 9d1216b009..4a9738c6c9 100644
--- a/src/mainboard/google/sarien/default.fmd
+++ b/src/mainboard/google/sarien/default.fmd
@@ -2,7 +2,7 @@ FLASH 0x2000000 {
 	SI_BIOS@0x400000 {
 		MEMORY_MAPPED@0xc00000 { /* 16MiB total */
 			RW_MRC_CACHE 0x10000
-			SMMSTORE 0x40000
+			SMMSTORE 0x80000
 			RO_VPD 0x4000
 			FMAP 0x300
 			COREBOOT(CBFS)

From cde428079669291527388f2b416db95a0e3edc68 Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Sun, 31 Aug 2025 17:39:12 -0500
Subject: [PATCH 2761/3886] soc/intel/apollolake: Add CFR objects for existing
 options

Add a header with CFR objects for existing configuration options,
so that supported boards can make use of them without duplication.

CFR options are added for the following options:
- legacy_8254_timer
- s0ix_enable
- vtd

TEST=build/boot google/reef with CFR support

Change-Id: Ia58bf53f93742417c2aac683c96f7c8f382a35c0
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90309
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
---
 src/soc/intel/apollolake/include/soc/cfr.h | 49 ++++++++++++++++++++++
 1 file changed, 49 insertions(+)
 create mode 100644 src/soc/intel/apollolake/include/soc/cfr.h

diff --git a/src/soc/intel/apollolake/include/soc/cfr.h b/src/soc/intel/apollolake/include/soc/cfr.h
new file mode 100644
index 0000000000..df4a9200cc
--- /dev/null
+++ b/src/soc/intel/apollolake/include/soc/cfr.h
@@ -0,0 +1,49 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+/*
+ * CFR enums and structs which are used to control SoC settings.
+ */
+
+#ifndef _APOLLOLAKE_CFR_H_
+#define _APOLLOLAKE_CFR_H_
+
+#include <drivers/option/cfr_frontend.h>
+#include <soc/soc_chip.h>
+
+/* Legacy 8254 Timer */
+static const struct sm_object legacy_8254_timer = SM_DECLARE_ENUM({
+	.opt_name	= "legacy_8254_timer",
+	.ui_name	= "Legacy 8254 Timer",
+	.ui_helptext	= "Enable the legacy 8254 timer by disabling clock gating.",
+	.default_value	= 0,
+	.values		= (const struct sm_enum_value[]) {
+				{ "Disabled",		0	},
+				{ "Enabled",		1	},
+				SM_ENUM_VALUE_END		},
+});
+
+/* S0ix Enable */
+static const struct sm_object s0ix_enable = SM_DECLARE_ENUM({
+	.opt_name	= "s0ix_enable",
+	.ui_name	= "Modern Standby (S0ix)",
+	.ui_helptext	= "Enabled: use Modern Standby / S0ix. Disabled: use APCI S3 sleep",
+	.default_value	= 1,
+	.values		= (const struct sm_enum_value[]) {
+				{ "Disabled",		0	},
+				{ "Enabled",		1	},
+				SM_ENUM_VALUE_END		},
+});
+
+/* VT-d */
+static const struct sm_object vtd = SM_DECLARE_ENUM({
+	.opt_name	= "vtd",
+	.ui_name	= "VT-d",
+	.ui_helptext	= "Enable or disable Intel VT-d (virtualization)",
+	.default_value	= 1,
+	.values		= (const struct sm_enum_value[]) {
+				{ "Disabled",		0	},
+				{ "Enabled",		1	},
+				SM_ENUM_VALUE_END		},
+});
+
+#endif /* _APOLLOLAKE_CFR_H_ */

From a8a77f9da22051500ce4106d587bc153fc7dbc36 Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Mon, 1 Dec 2025 20:06:54 -0600
Subject: [PATCH 2762/3886] mb/google/fizz: Add CFR option for automatic fan
 control

Allow users to enable/disable automatic fan control via CFR options
menu.

TEST=build/boot fizz w/edk2 payload, verify automatic fan control
toggle functional.

Change-Id: I40e72b21f34e943b0f4bd6a206d004d89ec9692a
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90310
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
---
 src/mainboard/google/fizz/cfr.c | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/src/mainboard/google/fizz/cfr.c b/src/mainboard/google/fizz/cfr.c
index c775136d54..10df17757c 100644
--- a/src/mainboard/google/fizz/cfr.c
+++ b/src/mainboard/google/fizz/cfr.c
@@ -2,6 +2,7 @@
 
 #include <boot/coreboot_tables.h>
 #include <drivers/option/cfr_frontend.h>
+#include <ec/google/chromeec/cfr.h>
 #include <intelblocks/cfr.h>
 #include <soc/cfr.h>
 
@@ -24,6 +25,14 @@ static struct sm_obj_form system = {
 	},
 };
 
+static struct sm_obj_form ec = {
+	.ui_name = "ChromeEC Embedded Controller",
+	.obj_list = (const struct sm_object *[]) {
+		&auto_fan_control,
+		NULL
+	},
+};
+
 static struct sm_obj_form power = {
 	.ui_name = "Power",
 	.obj_list = (const struct sm_object *[]) {
@@ -34,6 +43,7 @@ static struct sm_obj_form power = {
 
 static struct sm_obj_form *sm_root[] = {
 	&system,
+	&ec,
 	&power,
 	NULL
 };

From 2b959f4560fd821965ca797d1a77d79aee04a4a4 Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Mon, 1 Dec 2025 20:10:21 -0600
Subject: [PATCH 2763/3886] mb/google/puff: Add CFR option for automatic fan
 control

Allow users to enable/disable automatic fan control via CFR options
menu.

TEST=build/boot puff (wyvern) w/edk2 payload, verify automatic fan
control toggle functional.

Change-Id: I188e4393776b986809cbb1e51accaa88864b667f
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90311
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
---
 src/mainboard/google/puff/cfr.c | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/src/mainboard/google/puff/cfr.c b/src/mainboard/google/puff/cfr.c
index 8a60ed7d53..e50af539c8 100644
--- a/src/mainboard/google/puff/cfr.c
+++ b/src/mainboard/google/puff/cfr.c
@@ -3,6 +3,7 @@
 
 #include <boot/coreboot_tables.h>
 #include <drivers/option/cfr_frontend.h>
+#include <ec/google/chromeec/cfr.h>
 #include <intelblocks/cfr.h>
 #include <soc/cfr.h>
 
@@ -25,6 +26,14 @@ static struct sm_obj_form system = {
 	},
 };
 
+static struct sm_obj_form ec = {
+	.ui_name = "ChromeEC Embedded Controller",
+	.obj_list = (const struct sm_object *[]) {
+		&auto_fan_control,
+		NULL
+	},
+};
+
 static struct sm_obj_form power = {
 	.ui_name = "Power",
 	.obj_list = (const struct sm_object *[]) {
@@ -35,6 +44,7 @@ static struct sm_obj_form power = {
 
 static struct sm_obj_form *sm_root[] = {
 	&system,
+	&ec,
 	&power,
 	NULL
 };

From f0346845cd592ba59df6dc8843809f878ef17d08 Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Tue, 2 Dec 2025 12:47:56 -0600
Subject: [PATCH 2764/3886] mb/google/reef: Add CFR option menu support

Add CFR option menu support when using edk2 payload and SMMSTORE.
Include relevant items from Apollolake SoC, Intel common, and ChromeEC.

TEST=build/boot google/reef (electro), verify CFR option
functionality.

Change-Id: I8d9fdcaccc2d5cf35dcea6042f0a73d4bfd7ce69
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90341
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/google/reef/Kconfig     |  1 +
 src/mainboard/google/reef/Makefile.mk |  1 +
 src/mainboard/google/reef/cfr.c       | 42 +++++++++++++++++++++++++++
 3 files changed, 44 insertions(+)
 create mode 100644 src/mainboard/google/reef/cfr.c

diff --git a/src/mainboard/google/reef/Kconfig b/src/mainboard/google/reef/Kconfig
index d27feb2b49..899efeb4b8 100644
--- a/src/mainboard/google/reef/Kconfig
+++ b/src/mainboard/google/reef/Kconfig
@@ -7,6 +7,7 @@ config BOARD_GOOGLE_BASEBOARD_REEF
 	select DRIVERS_I2C_DA7219
 	select DRIVERS_I2C_GENERIC
 	select DRIVERS_I2C_HID
+	select DRIVERS_OPTION_CFR_ENABLED if PAYLOAD_EDK2 && SMMSTORE
 	select EC_GOOGLE_CHROMEEC
 	select EC_GOOGLE_CHROMEEC_BOARDID
 	select EC_GOOGLE_CHROMEEC_LPC
diff --git a/src/mainboard/google/reef/Makefile.mk b/src/mainboard/google/reef/Makefile.mk
index accb4633f3..7633d79606 100644
--- a/src/mainboard/google/reef/Makefile.mk
+++ b/src/mainboard/google/reef/Makefile.mk
@@ -5,6 +5,7 @@ bootblock-y += ec.c
 
 romstage-$(CONFIG_CHROMEOS) += chromeos.c
 
+ramstage-$(CONFIG_DRIVERS_OPTION_CFR) += cfr.c
 ramstage-$(CONFIG_CHROMEOS) += chromeos.c
 ramstage-y += ec.c
 ramstage-y += mainboard.c
diff --git a/src/mainboard/google/reef/cfr.c b/src/mainboard/google/reef/cfr.c
new file mode 100644
index 0000000000..bedb686b4e
--- /dev/null
+++ b/src/mainboard/google/reef/cfr.c
@@ -0,0 +1,42 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <boot/coreboot_tables.h>
+#include <drivers/option/cfr_frontend.h>
+#include <ec/google/chromeec/cfr.h>
+#include <intelblocks/cfr.h>
+#include <soc/cfr.h>
+
+static struct sm_obj_form system = {
+	.ui_name = "System",
+	.obj_list = (const struct sm_object *[]) {
+		&legacy_8254_timer,
+		&me_state,
+		&me_state_counter,
+		&pciexp_aspm,
+		&pciexp_clk_pm,
+		&pciexp_l1ss,
+		&pciexp_speed,
+		&s0ix_enable,
+		&vtd,
+		NULL
+	},
+};
+
+static struct sm_obj_form ec = {
+	.ui_name = "ChromeEC Embedded Controller",
+	.obj_list = (const struct sm_object *[]) {
+		&ec_kb_backlight,
+		NULL
+	},
+};
+
+static struct sm_obj_form *sm_root[] = {
+	&system,
+	&ec,
+	NULL
+};
+
+void mb_cfr_setup_menu(struct lb_cfr *cfr_root)
+{
+	cfr_write_setup_menu(cfr_root, sm_root);
+}

From 0f93d154b24aa66a00ddfaf067680441d4746e1e Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Tue, 2 Dec 2025 12:50:14 -0600
Subject: [PATCH 2765/3886] mb/google/octopus: Add CFR option menu support

Add CFR option menu support when using edk2 payload and SMMSTORE.
Include relevant items from Geminilake SoC, Intel common, and ChromeEC.

TEST=build/boot google/octopus (ampton), verify CFR option
functionality.

Change-Id: I5ed3e038684c852c71bd812d6a4b8d05290d5361
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90342
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
---
 src/mainboard/google/octopus/Kconfig     |  1 +
 src/mainboard/google/octopus/Makefile.mk |  1 +
 src/mainboard/google/octopus/cfr.c       | 42 ++++++++++++++++++++++++
 3 files changed, 44 insertions(+)
 create mode 100644 src/mainboard/google/octopus/cfr.c

diff --git a/src/mainboard/google/octopus/Kconfig b/src/mainboard/google/octopus/Kconfig
index 3078224cc9..1ba172e687 100644
--- a/src/mainboard/google/octopus/Kconfig
+++ b/src/mainboard/google/octopus/Kconfig
@@ -10,6 +10,7 @@ config BOARD_GOOGLE_BASEBOARD_OCTOPUS
 	select DRIVERS_I2C_GENERIC
 	select DRIVERS_I2C_HID
 	select DRIVERS_I2C_SX9310
+	select DRIVERS_OPTION_CFR_ENABLED if PAYLOAD_EDK2 && SMMSTORE
 	select DRIVERS_SPI_ACPI
 	select DRIVERS_USB_ACPI
 	select EC_GOOGLE_CHROMEEC
diff --git a/src/mainboard/google/octopus/Makefile.mk b/src/mainboard/google/octopus/Makefile.mk
index accb4633f3..7633d79606 100644
--- a/src/mainboard/google/octopus/Makefile.mk
+++ b/src/mainboard/google/octopus/Makefile.mk
@@ -5,6 +5,7 @@ bootblock-y += ec.c
 
 romstage-$(CONFIG_CHROMEOS) += chromeos.c
 
+ramstage-$(CONFIG_DRIVERS_OPTION_CFR) += cfr.c
 ramstage-$(CONFIG_CHROMEOS) += chromeos.c
 ramstage-y += ec.c
 ramstage-y += mainboard.c
diff --git a/src/mainboard/google/octopus/cfr.c b/src/mainboard/google/octopus/cfr.c
new file mode 100644
index 0000000000..bedb686b4e
--- /dev/null
+++ b/src/mainboard/google/octopus/cfr.c
@@ -0,0 +1,42 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <boot/coreboot_tables.h>
+#include <drivers/option/cfr_frontend.h>
+#include <ec/google/chromeec/cfr.h>
+#include <intelblocks/cfr.h>
+#include <soc/cfr.h>
+
+static struct sm_obj_form system = {
+	.ui_name = "System",
+	.obj_list = (const struct sm_object *[]) {
+		&legacy_8254_timer,
+		&me_state,
+		&me_state_counter,
+		&pciexp_aspm,
+		&pciexp_clk_pm,
+		&pciexp_l1ss,
+		&pciexp_speed,
+		&s0ix_enable,
+		&vtd,
+		NULL
+	},
+};
+
+static struct sm_obj_form ec = {
+	.ui_name = "ChromeEC Embedded Controller",
+	.obj_list = (const struct sm_object *[]) {
+		&ec_kb_backlight,
+		NULL
+	},
+};
+
+static struct sm_obj_form *sm_root[] = {
+	&system,
+	&ec,
+	NULL
+};
+
+void mb_cfr_setup_menu(struct lb_cfr *cfr_root)
+{
+	cfr_write_setup_menu(cfr_root, sm_root);
+}

From 89902e8c802eecefb75ef567245674b24df541de Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Tue, 2 Dec 2025 12:53:58 -0600
Subject: [PATCH 2766/3886] mb/google/hatch: Add CFR option menu support

Add CFR option menu support when using edk2 payload and SMMSTORE.
Include relevant items from Cometlake SoC, Intel common, and ChromeEC.

TEST=build/boot google/hatch (akemi), verify CFR option
functionality.

Change-Id: I29158a2d1fe6956799156fbe066ad4e97c110226
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90343
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
---
 src/mainboard/google/hatch/Kconfig     |  1 +
 src/mainboard/google/hatch/Makefile.mk |  1 +
 src/mainboard/google/hatch/cfr.c       | 47 ++++++++++++++++++++++++++
 3 files changed, 49 insertions(+)
 create mode 100644 src/mainboard/google/hatch/cfr.c

diff --git a/src/mainboard/google/hatch/Kconfig b/src/mainboard/google/hatch/Kconfig
index 850234153f..1336c65eed 100644
--- a/src/mainboard/google/hatch/Kconfig
+++ b/src/mainboard/google/hatch/Kconfig
@@ -10,6 +10,7 @@ config BOARD_GOOGLE_BASEBOARD_HATCH
 	select DRIVERS_I2C_GENERIC
 	select DRIVERS_I2C_HID
 	select DRIVERS_I2C_SX9310
+	select DRIVERS_OPTION_CFR_ENABLED if PAYLOAD_EDK2 && SMMSTORE
 	select DRIVERS_SPI_ACPI
 	select DRIVERS_USB_ACPI
 	select EC_GOOGLE_CHROMEEC
diff --git a/src/mainboard/google/hatch/Makefile.mk b/src/mainboard/google/hatch/Makefile.mk
index c1bd77a1f4..4ce672cbf8 100644
--- a/src/mainboard/google/hatch/Makefile.mk
+++ b/src/mainboard/google/hatch/Makefile.mk
@@ -6,6 +6,7 @@ bootblock-$(CONFIG_CHROMEOS) += chromeos.c
 ramstage-y += ramstage.c
 ramstage-$(CONFIG_CHROMEOS) += chromeos.c
 ramstage-$(CONFIG_EC_GOOGLE_CHROMEEC) += ec.c
+ramstage-$(CONFIG_DRIVERS_OPTION_CFR) += cfr.c
 
 romstage-$(CONFIG_ROMSTAGE_SPD_CBFS) += romstage_spd_cbfs.c
 romstage-$(CONFIG_ROMSTAGE_SPD_SMBUS) += romstage_spd_smbus.c
diff --git a/src/mainboard/google/hatch/cfr.c b/src/mainboard/google/hatch/cfr.c
new file mode 100644
index 0000000000..855b08d488
--- /dev/null
+++ b/src/mainboard/google/hatch/cfr.c
@@ -0,0 +1,47 @@
+
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <boot/coreboot_tables.h>
+#include <drivers/option/cfr_frontend.h>
+#include <ec/google/chromeec/cfr.h>
+#include <intelblocks/cfr.h>
+#include <soc/cfr.h>
+
+static struct sm_obj_form system = {
+	.ui_name = "System",
+	.obj_list = (const struct sm_object *[]) {
+		&hyper_threading,
+		&igd_dvmt,
+		&igd_aperture,
+		&legacy_8254_timer,
+		&me_state,
+		&me_state_counter,
+		&pciexp_aspm,
+		&pciexp_clk_pm,
+		&pciexp_l1ss,
+		&pciexp_speed,
+		&s0ix_enable,
+		&vtd,
+		NULL
+	},
+};
+
+static struct sm_obj_form ec = {
+	.ui_name = "ChromeEC Embedded Controller",
+	.obj_list = (const struct sm_object *[]) {
+		auto_fan_control,
+		&ec_kb_backlight,
+		NULL
+	},
+};
+
+static struct sm_obj_form *sm_root[] = {
+	&system,
+	&ec,
+	NULL
+};
+
+void mb_cfr_setup_menu(struct lb_cfr *cfr_root)
+{
+	cfr_write_setup_menu(cfr_root, sm_root);
+}

From 0762c7d6eee4cd00821bf22ff91ea235e643e407 Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Sun, 31 Aug 2025 17:48:07 -0500
Subject: [PATCH 2767/3886] mb/google/drallion/Makefile: Organize and group
 entries by stage

Tidy up before adding a new CFR entry in a subsequent patch.

Change-Id: Ifbb52e9930998187dcd310a50449b312f56e20e3
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90344
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
---
 src/mainboard/google/drallion/Makefile.mk | 18 ++++++++----------
 1 file changed, 8 insertions(+), 10 deletions(-)

diff --git a/src/mainboard/google/drallion/Makefile.mk b/src/mainboard/google/drallion/Makefile.mk
index 3c355c5a2e..569e54ffeb 100644
--- a/src/mainboard/google/drallion/Makefile.mk
+++ b/src/mainboard/google/drallion/Makefile.mk
@@ -1,22 +1,20 @@
 ## SPDX-License-Identifier: GPL-2.0-only
 
 bootblock-y += bootblock.c
+bootblock-$(CONFIG_CHROMEOS) += chromeos.c
+bootblock-y += ec.c
 
-ramstage-y += ramstage.c
+verstage-$(CONFIG_CHROMEOS) += chromeos.c
+verstage-y += ec.c
 
+romstage-$(CONFIG_CHROMEOS) += chromeos.c
+romstage-y += ec.c
 romstage-y += romstage.c
 
-bootblock-$(CONFIG_CHROMEOS) += chromeos.c
 ramstage-$(CONFIG_CHROMEOS) += chromeos.c
-romstage-$(CONFIG_CHROMEOS) += chromeos.c
-verstage-$(CONFIG_CHROMEOS) += chromeos.c
-
-ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_HDA_VERB) += hda_verb.c
-
-bootblock-y += ec.c
 ramstage-y += ec.c
-romstage-y += ec.c
-verstage-y += ec.c
+ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_HDA_VERB) += hda_verb.c
+ramstage-y += ramstage.c
 
 subdirs-y += variants/baseboard
 CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/baseboard/include

From 8b34490137a1ac53d76e47d2324b81c69d932fe8 Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Tue, 2 Dec 2025 12:57:25 -0600
Subject: [PATCH 2768/3886] mb/google/drallion: Add CFR option menu support

Add CFR option menu support when using edk2 payload and SMMSTORE.
Include relevant items from Cometlake SoC and Intel common.

TEST=build/boot google/drallion, verify CFR option functionality.

Change-Id: I9cff10b4782f6066e79cca8d39cb7cbc053d88ea
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90345
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/google/drallion/Kconfig     |  1 +
 src/mainboard/google/drallion/Makefile.mk |  1 +
 src/mainboard/google/drallion/cfr.c       | 36 +++++++++++++++++++++++
 3 files changed, 38 insertions(+)
 create mode 100644 src/mainboard/google/drallion/cfr.c

diff --git a/src/mainboard/google/drallion/Kconfig b/src/mainboard/google/drallion/Kconfig
index 365424f92e..34c9da5a8e 100644
--- a/src/mainboard/google/drallion/Kconfig
+++ b/src/mainboard/google/drallion/Kconfig
@@ -8,6 +8,7 @@ config BOARD_GOOGLE_BASEBOARD_DRALLION
 	select DRIVERS_I2C_GENERIC
 	select DRIVERS_I2C_HID
 	select DRIVERS_INTEL_ISH
+	select DRIVERS_OPTION_CFR_ENABLED if PAYLOAD_EDK2 && SMMSTORE
 	select DRIVERS_SPI_ACPI
 	select DRIVERS_USB_ACPI
 	select EC_GOOGLE_WILCO
diff --git a/src/mainboard/google/drallion/Makefile.mk b/src/mainboard/google/drallion/Makefile.mk
index 569e54ffeb..4757811dc9 100644
--- a/src/mainboard/google/drallion/Makefile.mk
+++ b/src/mainboard/google/drallion/Makefile.mk
@@ -11,6 +11,7 @@ romstage-$(CONFIG_CHROMEOS) += chromeos.c
 romstage-y += ec.c
 romstage-y += romstage.c
 
+ramstage-$(CONFIG_DRIVERS_OPTION_CFR) += cfr.c
 ramstage-$(CONFIG_CHROMEOS) += chromeos.c
 ramstage-y += ec.c
 ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_HDA_VERB) += hda_verb.c
diff --git a/src/mainboard/google/drallion/cfr.c b/src/mainboard/google/drallion/cfr.c
new file mode 100644
index 0000000000..aa9265db7d
--- /dev/null
+++ b/src/mainboard/google/drallion/cfr.c
@@ -0,0 +1,36 @@
+
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <boot/coreboot_tables.h>
+#include <drivers/option/cfr_frontend.h>
+#include <intelblocks/cfr.h>
+#include <soc/cfr.h>
+
+static struct sm_obj_form system = {
+	.ui_name = "System",
+	.obj_list = (const struct sm_object *[]) {
+		&hyper_threading,
+		&igd_dvmt,
+		&igd_aperture,
+		&legacy_8254_timer,
+		&me_state,
+		&me_state_counter,
+		&pciexp_aspm,
+		&pciexp_clk_pm,
+		&pciexp_l1ss,
+		&pciexp_speed,
+		&s0ix_enable,
+		&vtd,
+		NULL
+	},
+};
+
+static struct sm_obj_form *sm_root[] = {
+	&system,
+	NULL
+};
+
+void mb_cfr_setup_menu(struct lb_cfr *cfr_root)
+{
+	cfr_write_setup_menu(cfr_root, sm_root);
+}

From a58e0704c77a3782bef18c8e77486af0021a1294 Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Tue, 2 Dec 2025 12:59:30 -0600
Subject: [PATCH 2769/3886] mb/google/volteer: Add CFR option menu support

Add CFR option menu support when using edk2 payload and SMMSTORE.
Include relevant items from Tigerlake SoC, Intel common, and ChromeEC.

TEST=build/boot google/volteer (drobit), verify CFR option
functionality.

Change-Id: Ic6848825aefa8e0627240fc04b2a6b7a33188de6
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90346
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
---
 src/mainboard/google/volteer/Kconfig     |  1 +
 src/mainboard/google/volteer/Makefile.mk |  1 +
 src/mainboard/google/volteer/cfr.c       | 47 ++++++++++++++++++++++++
 3 files changed, 49 insertions(+)
 create mode 100644 src/mainboard/google/volteer/cfr.c

diff --git a/src/mainboard/google/volteer/Kconfig b/src/mainboard/google/volteer/Kconfig
index fdda53b48b..a7537c0fd2 100644
--- a/src/mainboard/google/volteer/Kconfig
+++ b/src/mainboard/google/volteer/Kconfig
@@ -15,6 +15,7 @@ config BOARD_GOOGLE_BASEBOARD_VOLTEER
 	select DRIVERS_INTEL_PMC
 	select DRIVERS_INTEL_SOUNDWIRE
 	select DRIVERS_INTEL_USB4_RETIMER
+	select DRIVERS_OPTION_CFR_ENABLED if PAYLOAD_EDK2 && SMMSTORE
 	select DRIVERS_SOUNDWIRE_ALC5682
 	select DRIVERS_SOUNDWIRE_MAX98373
 	select DRIVERS_SPI_ACPI
diff --git a/src/mainboard/google/volteer/Makefile.mk b/src/mainboard/google/volteer/Makefile.mk
index 493bf1d77d..bdf2b41a4c 100644
--- a/src/mainboard/google/volteer/Makefile.mk
+++ b/src/mainboard/google/volteer/Makefile.mk
@@ -6,6 +6,7 @@ bootblock-y += bootblock.c
 romstage-$(CONFIG_CHROMEOS) += chromeos.c
 romstage-y += romstage.c
 
+ramstage-$(CONFIG_DRIVERS_OPTION_CFR) += cfr.c
 ramstage-$(CONFIG_CHROMEOS) += chromeos.c
 ramstage-y += ec.c
 ramstage-$(CONFIG_FW_CONFIG) += fw_config.c
diff --git a/src/mainboard/google/volteer/cfr.c b/src/mainboard/google/volteer/cfr.c
new file mode 100644
index 0000000000..2de1ebbb7c
--- /dev/null
+++ b/src/mainboard/google/volteer/cfr.c
@@ -0,0 +1,47 @@
+
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <boot/coreboot_tables.h>
+#include <drivers/option/cfr_frontend.h>
+#include <ec/google/chromeec/cfr.h>
+#include <intelblocks/cfr.h>
+#include <soc/cfr.h>
+
+static struct sm_obj_form system = {
+	.ui_name = "System",
+	.obj_list = (const struct sm_object *[]) {
+		&hyper_threading,
+		&igd_dvmt,
+		&igd_aperture,
+		&legacy_8254_timer,
+		&me_state,
+		&me_state_counter,
+		&pciexp_aspm,
+		&pciexp_clk_pm,
+		&pciexp_l1ss,
+		&pciexp_speed,
+		&s0ix_enable,
+		&vtd,
+		NULL
+	},
+};
+
+static struct sm_obj_form ec = {
+	.ui_name = "ChromeEC Embedded Controller",
+	.obj_list = (const struct sm_object *[]) {
+		&auto_fan_control,
+		&ec_kb_backlight,
+		NULL
+	},
+};
+
+static struct sm_obj_form *sm_root[] = {
+	&system,
+	&ec,
+	NULL
+};
+
+void mb_cfr_setup_menu(struct lb_cfr *cfr_root)
+{
+	cfr_write_setup_menu(cfr_root, sm_root);
+}

From bd89858f0910d50b1b6569c6bb36c3584bc793cb Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Tue, 2 Dec 2025 13:03:36 -0600
Subject: [PATCH 2770/3886] mb/google/brya: Add CFR option menu support

Add CFR option menu support when using edk2 payload and SMMSTORE.
Include relevant items from Alderlake SoC, Intel common, and ChromeEC.

TEST=build/boot google/brya (yaviks), verify CFR option functionality.

Change-Id: I4b450fbc3e376dcb256a2c6b8ca7fb2267fa5df3
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90347
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
---
 src/mainboard/google/brya/Kconfig     |  1 +
 src/mainboard/google/brya/Makefile.mk |  1 +
 src/mainboard/google/brya/cfr.c       | 48 +++++++++++++++++++++++++++
 3 files changed, 50 insertions(+)
 create mode 100644 src/mainboard/google/brya/cfr.c

diff --git a/src/mainboard/google/brya/Kconfig b/src/mainboard/google/brya/Kconfig
index e5f5dc991d..b871d32fa6 100644
--- a/src/mainboard/google/brya/Kconfig
+++ b/src/mainboard/google/brya/Kconfig
@@ -15,6 +15,7 @@ config BOARD_GOOGLE_BRYA_COMMON
 	select DRIVERS_INTEL_PMC
 	select DRIVERS_INTEL_SOUNDWIRE
 	select DRIVERS_INTEL_USB4_RETIMER
+	select DRIVERS_OPTION_CFR_ENABLED if PAYLOAD_EDK2 && SMMSTORE
 	select DRIVERS_SOUNDWIRE_ALC5682
 	select DRIVERS_SOUNDWIRE_MAX98373
 	select DRIVERS_SPI_ACPI
diff --git a/src/mainboard/google/brya/Makefile.mk b/src/mainboard/google/brya/Makefile.mk
index 8c7e42d5f7..b10bdfbc5a 100644
--- a/src/mainboard/google/brya/Makefile.mk
+++ b/src/mainboard/google/brya/Makefile.mk
@@ -10,6 +10,7 @@ romstage-y += romstage.c
 ramstage-$(CONFIG_CHROMEOS) += chromeos.c
 ramstage-y += mainboard.c
 ramstage-y += ec.c
+ramstage-$(CONFIG_DRIVERS_OPTION_CFR) += cfr.c
 
 BASEBOARD_DIR:=$(call strip_quotes,$(CONFIG_BASEBOARD_DIR))
 
diff --git a/src/mainboard/google/brya/cfr.c b/src/mainboard/google/brya/cfr.c
new file mode 100644
index 0000000000..637e1b38d5
--- /dev/null
+++ b/src/mainboard/google/brya/cfr.c
@@ -0,0 +1,48 @@
+
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <boot/coreboot_tables.h>
+#include <drivers/option/cfr_frontend.h>
+#include <ec/google/chromeec/cfr.h>
+#include <intelblocks/cfr.h>
+#include <soc/cfr.h>
+
+static struct sm_obj_form system = {
+	.ui_name = "System",
+	.obj_list = (const struct sm_object *[]) {
+		&hyper_threading,
+		&igd_dvmt,
+		&igd_aperture,
+		&legacy_8254_timer,
+		&me_state,
+		&me_state_counter,
+		&pciexp_aspm,
+		&pciexp_clk_pm,
+		&pciexp_l1ss,
+		&pciexp_speed,
+		&s0ix_enable,
+		&vtd,
+		NULL
+	},
+};
+
+static struct sm_obj_form ec = {
+	.ui_name = "ChromeEC Embedded Controller",
+	.obj_list = (const struct sm_object *[]) {
+		&auto_fan_control,
+		&ec_kb_backlight,
+		&ec_rgb_kb_color,
+		NULL
+	},
+};
+
+static struct sm_obj_form *sm_root[] = {
+	&system,
+	&ec,
+	NULL
+};
+
+void mb_cfr_setup_menu(struct lb_cfr *cfr_root)
+{
+	cfr_write_setup_menu(cfr_root, sm_root);
+}

From 1890c6d165efff2cdac88fdb44859c5c31e1f682 Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Tue, 2 Dec 2025 13:06:46 -0600
Subject: [PATCH 2771/3886] mb/google/dedede: Add CFR option menu support

Add CFR option menu support when using edk2 payload and SMMSTORE.
Include relevant items from Jasperlake SoC, Intel common, and ChromeEC.

TEST=build/boot google/dedede (maglia), verify CFR option
functionality.

Change-Id: I36b567a32232cb0f561c9f428157e421319d8dab
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90348
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
---
 src/mainboard/google/dedede/Kconfig     |  1 +
 src/mainboard/google/dedede/Makefile.mk |  1 +
 src/mainboard/google/dedede/cfr.c       | 44 +++++++++++++++++++++++++
 3 files changed, 46 insertions(+)
 create mode 100644 src/mainboard/google/dedede/cfr.c

diff --git a/src/mainboard/google/dedede/Kconfig b/src/mainboard/google/dedede/Kconfig
index 57b7c05720..a17c756046 100644
--- a/src/mainboard/google/dedede/Kconfig
+++ b/src/mainboard/google/dedede/Kconfig
@@ -14,6 +14,7 @@ config BOARD_GOOGLE_BASEBOARD_DEDEDE
 	select DRIVERS_I2C_RT5645
 	select DRIVERS_INTEL_DPTF
 	select DRIVERS_INTEL_MIPI_CAMERA
+	select DRIVERS_OPTION_CFR_ENABLED if PAYLOAD_EDK2 && SMMSTORE
 	select DRIVERS_SPI_ACPI
 	select DRIVERS_USB_ACPI
 	select EC_GOOGLE_CHROMEEC
diff --git a/src/mainboard/google/dedede/Makefile.mk b/src/mainboard/google/dedede/Makefile.mk
index fdc26306bb..c0e69e50f5 100644
--- a/src/mainboard/google/dedede/Makefile.mk
+++ b/src/mainboard/google/dedede/Makefile.mk
@@ -12,6 +12,7 @@ ramstage-y += mainboard.c
 ramstage-y += ec.c
 ramstage-y += board_info.c
 ramstage-y += fw_config.c
+ramstage-$(CONFIG_DRIVERS_OPTION_CFR) += cfr.c
 
 
 subdirs-y += variants/baseboard
diff --git a/src/mainboard/google/dedede/cfr.c b/src/mainboard/google/dedede/cfr.c
new file mode 100644
index 0000000000..852b9f165c
--- /dev/null
+++ b/src/mainboard/google/dedede/cfr.c
@@ -0,0 +1,44 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <boot/coreboot_tables.h>
+#include <drivers/option/cfr_frontend.h>
+#include <ec/google/chromeec/cfr.h>
+#include <intelblocks/cfr.h>
+#include <soc/cfr.h>
+
+static struct sm_obj_form system = {
+	.ui_name = "System",
+	.obj_list = (const struct sm_object *[]) {
+		&igd_dvmt,
+		&igd_aperture,
+		&legacy_8254_timer,
+		&me_state,
+		&me_state_counter,
+		&pciexp_aspm,
+		&pciexp_clk_pm,
+		&pciexp_l1ss,
+		&pciexp_speed,
+		&s0ix_enable,
+		&vtd,
+		NULL
+	},
+};
+
+static struct sm_obj_form ec = {
+	.ui_name = "ChromeEC Embedded Controller",
+	.obj_list = (const struct sm_object *[]) {
+		&ec_kb_backlight,
+		NULL
+	},
+};
+
+static struct sm_obj_form *sm_root[] = {
+	&system,
+	&ec,
+	NULL
+};
+
+void mb_cfr_setup_menu(struct lb_cfr *cfr_root)
+{
+	cfr_write_setup_menu(cfr_root, sm_root);
+}

From 7a78543eca7f4351772b213ae9ed3e245ab85425 Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Sun, 19 Oct 2025 15:05:33 -0500
Subject: [PATCH 2772/3886] mb/google/dedede/drawcia: Add CFR option for
 touchscreen selection

The i2c auto-detection fails to find a touchscreen on Drawcia, so
create a user-selectable CFR option instead, with the default being
all enabled. This allows Linux to probe and detect the correct
device, and Windows users to select the appropriate selection.

Change-Id: I2e4a760b7d6c9b1546418630f75538adccdcf8e1
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90349
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
---
 src/mainboard/google/dedede/cfr.c             | 27 +++++++++++
 .../dedede/variants/drawcia/overridetree.cb   | 15 ++----
 .../google/dedede/variants/drawcia/ramstage.c | 47 +++++++++++++++++++
 3 files changed, 79 insertions(+), 10 deletions(-)

diff --git a/src/mainboard/google/dedede/cfr.c b/src/mainboard/google/dedede/cfr.c
index 852b9f165c..50f85c90cb 100644
--- a/src/mainboard/google/dedede/cfr.c
+++ b/src/mainboard/google/dedede/cfr.c
@@ -6,6 +6,24 @@
 #include <intelblocks/cfr.h>
 #include <soc/cfr.h>
 
+static const struct sm_object touchscreen = SM_DECLARE_ENUM({
+	.opt_name	= "touchscreen",
+	.ui_name	= "Touchscreen Type",
+	.ui_helptext	= "Select the model of the integrated touchscreen device",
+	.default_value	= 0,
+	.values		= (const struct sm_enum_value[]) {
+		{ "Auto-select",	0		},
+		{ "ELAN0001",		1		},
+		{ "GTCH7503",		2		},
+		{ "GDIX0000",		3		},
+		{ "ELAN2513",		4		},
+		{ "WDHT0002",		5		},
+		SM_ENUM_VALUE_END			},
+#if !CONFIG(BOARD_GOOGLE_DRAWCIA)
+	.flags		= CFR_OPTFLAG_SUPPRESS,
+#endif
+});
+
 static struct sm_obj_form system = {
 	.ui_name = "System",
 	.obj_list = (const struct sm_object *[]) {
@@ -32,8 +50,17 @@ static struct sm_obj_form ec = {
 	},
 };
 
+static struct sm_obj_form devices = {
+	.ui_name = "Devices",
+	.obj_list = (const struct sm_object *[]) {
+		&touchscreen,
+		NULL
+	},
+};
+
 static struct sm_obj_form *sm_root[] = {
 	&system,
+	&devices,
 	&ec,
 	NULL
 };
diff --git a/src/mainboard/google/dedede/variants/drawcia/overridetree.cb b/src/mainboard/google/dedede/variants/drawcia/overridetree.cb
index e8546a5cae..fdcfd0226b 100644
--- a/src/mainboard/google/dedede/variants/drawcia/overridetree.cb
+++ b/src/mainboard/google/dedede/variants/drawcia/overridetree.cb
@@ -231,32 +231,29 @@ chip soc/intel/jasperlake
 				register "hid" = ""ELAN0001""
 				register "desc" = ""ELAN Touchscreen""
 				register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_D4_IRQ)"
-				register "detect" = "1"
 				register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D5)"
 				register "reset_delay_ms" = "20"
 				register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D6)"
 				register "enable_delay_ms" = "1"
 				register "has_power_resource" = "true"
-				device i2c 10 on end
+				device i2c 10 alias elan0001 on end
 			end
 			chip drivers/i2c/hid
 				register "generic.hid" = ""GTCH7503""
 				register "generic.desc" = ""G2TOUCH Touchscreen""
 				register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_D4_IRQ)"
-				register "generic.detect" = "1"
 				register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D5)"
 				register "generic.reset_delay_ms" = "50"
 				register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D6)"
 				register "generic.enable_delay_ms" = "1"
 				register "generic.has_power_resource" = "1"
 				register "hid_desc_reg_offset" = "0x01"
-				device i2c 40 on end
+				device i2c 40 alias gtch7503 on end
 			end
 			chip drivers/i2c/hid
 				register "generic.hid" = ""GDIX0000""
 				register "generic.desc" = ""Goodix Touchscreen""
 				register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_D4_IRQ)"
-				register "generic.detect" = "1"
 				register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D5)"
 				register "generic.reset_delay_ms" = "120"
 				register "generic.reset_off_delay_ms" = "2"
@@ -264,13 +261,12 @@ chip soc/intel/jasperlake
 				register "generic.enable_delay_ms" = "12"
 				register "generic.has_power_resource" = "1"
 				register "hid_desc_reg_offset" = "0x01"
-				device i2c 0x5d on end
+				device i2c 0x5d alias gdix0000 on end
 			end
 			chip drivers/i2c/hid
 				register "generic.hid" = ""ELAN2513""
 				register "generic.desc" = ""ELAN Touchscreen""
 				register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_D4_IRQ)"
-				register "generic.detect" = "1"
 				register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D5)"
 				register "generic.reset_delay_ms" = "20"
 				register "generic.reset_off_delay_ms" = "2"
@@ -280,20 +276,19 @@ chip soc/intel/jasperlake
 				register "generic.stop_delay_ms" = "130"
 				register "generic.has_power_resource" = "1"
 				register "hid_desc_reg_offset" = "0x01"
-				device i2c 15 on end
+				device i2c 15 alias elan2513 on end
 			end
 			chip drivers/i2c/hid
 				register "generic.hid" = ""WDHT0002""
 				register "generic.desc" = ""WDT Touchscreen""
 				register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_D4_IRQ)"
-				register "generic.detect" = "1"
 				register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D5)"
 				register "generic.reset_delay_ms" = "130"
 				register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D6)"
 				register "generic.enable_delay_ms" = "10"
 				register "generic.has_power_resource" = "1"
 				register "hid_desc_reg_offset" = "0x20"
-				device i2c 2c on end
+				device i2c 2c alias wdht0002 on end
 			end
 		end # I2C 2
 		device pci 15.3 on
diff --git a/src/mainboard/google/dedede/variants/drawcia/ramstage.c b/src/mainboard/google/dedede/variants/drawcia/ramstage.c
index f44a170217..be1b253219 100644
--- a/src/mainboard/google/dedede/variants/drawcia/ramstage.c
+++ b/src/mainboard/google/dedede/variants/drawcia/ramstage.c
@@ -5,6 +5,7 @@
 #include <device/device.h>
 #include <drivers/usb/acpi/chip.h>
 #include <fw_config.h>
+#include <option.h>
 #include <soc/soc_chip.h>
 #include <static.h>
 
@@ -28,9 +29,21 @@ static void update_lte_device_drawcia(void)
 	config->reset_gpio = lte_reset_gpio;
 }
 
+#define TS_TYPE_AUTO_SELECT 0
+#define TS_TYPE_ELAN0001 0
+#define TS_TYPE_GTCH7503 1
+#define TS_TYPE_GDIX0000 2
+#define TS_TYPE_ELAN2513 3
+#define TS_TYPE_WDHT0002 4
+
 void variant_devtree_update(void)
 {
 	uint32_t board_version = board_id();
+	struct device *ts_elan0001 = DEV_PTR(elan0001);
+	struct device *ts_gtch7503 = DEV_PTR(gtch7503);
+	struct device *ts_gdix0000 = DEV_PTR(gdix0000);
+	struct device *ts_elan2513 = DEV_PTR(elan2513);
+	struct device *ts_wdht0002 = DEV_PTR(wdht0002);
 
 	/* Remove power IC after board version 0xb for Draw* and Oscino units */
 	if (board_version > 0xb)
@@ -38,4 +51,38 @@ void variant_devtree_update(void)
 	/* Board version 0xa, 0xb and 0xf are for Drawper units */
 	if (board_version != 0xa && board_version != 0xb && board_version != 0xf)
 		update_lte_device_drawcia();
+
+	/* Update touchscreen device */
+	switch (get_uint_option("touchscreen", TS_TYPE_AUTO_SELECT)) {
+	case TS_TYPE_ELAN0001:
+		ts_gtch7503->enabled = 0;
+		ts_gdix0000->enabled = 0;
+		ts_elan2513->enabled = 0;
+		ts_wdht0002->enabled = 0;
+		break;
+	case TS_TYPE_GTCH7503:
+		ts_elan0001->enabled = 0;
+		ts_gdix0000->enabled = 0;
+		ts_elan2513->enabled = 0;
+		ts_wdht0002->enabled = 0;
+		break;
+	case TS_TYPE_GDIX0000:
+		ts_elan0001->enabled = 0;
+		ts_gtch7503->enabled = 0;
+		ts_elan2513->enabled = 0;
+		ts_wdht0002->enabled = 0;
+		break;
+	case TS_TYPE_ELAN2513:
+		ts_elan0001->enabled = 0;
+		ts_gtch7503->enabled = 0;
+		ts_gdix0000->enabled = 0;
+		ts_wdht0002->enabled = 0;
+		break;
+	case TS_TYPE_WDHT0002:
+		ts_elan0001->enabled = 0;
+		ts_gtch7503->enabled = 0;
+		ts_gdix0000->enabled = 0;
+		ts_elan2513->enabled = 0;
+		break;
+	}
 }

From ee599486ac4a2aed195a7c53f8eec2832359110d Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Sun, 19 Oct 2025 16:13:41 -0500
Subject: [PATCH 2773/3886] mb/google/dedede/galtic: Add CFR option for
 touchpad type

The i2c auto-detection cannot distinguish between two touchpads using
the same i2c bus and address, so drop the 'detect' flag amd implement
a user-selectable CFR option instead, defaulting to both enabled.
This will allow either touchpad to work properly under Linux, and
give the user the ability to only enable the touchpad actually present
should they wish to run Windows.

Change-Id: Iaf1406c2d10bbf10b9aea30ae1cd2b2281bfcc5d
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90350
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
---
 src/mainboard/google/dedede/cfr.c             | 16 +++++++++++++
 .../dedede/variants/galtic/overridetree.cb    |  6 ++---
 .../google/dedede/variants/galtic/variant.c   | 24 +++++++++++++++++++
 3 files changed, 42 insertions(+), 4 deletions(-)

diff --git a/src/mainboard/google/dedede/cfr.c b/src/mainboard/google/dedede/cfr.c
index 50f85c90cb..63705fcd3d 100644
--- a/src/mainboard/google/dedede/cfr.c
+++ b/src/mainboard/google/dedede/cfr.c
@@ -24,6 +24,21 @@ static const struct sm_object touchscreen = SM_DECLARE_ENUM({
 #endif
 });
 
+static const struct sm_object touchpad = SM_DECLARE_ENUM({
+	.opt_name	= "touchpad",
+	.ui_name	= "Touchpad Type",
+	.ui_helptext	= "Select the model of the integrated touchpad device",
+	.default_value	= 0,
+	.values		= (const struct sm_enum_value[]) {
+		{ "Auto-select",	0		},
+		{ "ELAN0000",		1		},
+		{ "ELAN2702",		2		},
+		SM_ENUM_VALUE_END			},
+#if !CONFIG(BOARD_GOOGLE_GALTIC)
+	.flags		= CFR_OPTFLAG_SUPPRESS,
+#endif
+});
+
 static struct sm_obj_form system = {
 	.ui_name = "System",
 	.obj_list = (const struct sm_object *[]) {
@@ -54,6 +69,7 @@ static struct sm_obj_form devices = {
 	.ui_name = "Devices",
 	.obj_list = (const struct sm_object *[]) {
 		&touchscreen,
+		&touchpad,
 		NULL
 	},
 };
diff --git a/src/mainboard/google/dedede/variants/galtic/overridetree.cb b/src/mainboard/google/dedede/variants/galtic/overridetree.cb
index 32977c6e99..0ef9cdb5da 100644
--- a/src/mainboard/google/dedede/variants/galtic/overridetree.cb
+++ b/src/mainboard/google/dedede/variants/galtic/overridetree.cb
@@ -143,17 +143,15 @@ chip soc/intel/jasperlake
 				register "desc" = ""ELAN Touchpad""
 				register "irq" = "ACPI_IRQ_WAKE_EDGE_LOW(GPP_B3_IRQ)"
 				register "wake" = "GPE0_DW0_03"
-				register "detect" = "1"
-				device i2c 15 on end
+				device i2c 15 alias elan0000 on end
 			end
 			chip drivers/i2c/hid
 				register "generic.hid" = ""ELAN2702""
 				register "generic.desc" = ""ELAN Touchpad""
 				register "generic.irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_B3_IRQ)"
 				register "generic.wake" = "GPE0_DW0_03"
-				register "generic.detect" = "1"
 				register "hid_desc_reg_offset" = "0x01"
-				device i2c 15 on end
+				device i2c 15 alias elan2702 on end
 			end
 		end
 		device pci 15.2 on
diff --git a/src/mainboard/google/dedede/variants/galtic/variant.c b/src/mainboard/google/dedede/variants/galtic/variant.c
index 1e62f0c187..a3f91896c0 100644
--- a/src/mainboard/google/dedede/variants/galtic/variant.c
+++ b/src/mainboard/google/dedede/variants/galtic/variant.c
@@ -1,8 +1,12 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
+#include <baseboard/variants.h>
+#include <device/device.h>
 #include <ec/google/chromeec/ec.h>
 #include <fw_config.h>
+#include <option.h>
 #include <sar.h>
+#include <static.h>
 
 enum {
 	GALTIC_SKU_START    = 0x120000,
@@ -37,3 +41,23 @@ const char *get_wifi_sar_cbfs_filename(void)
 
 	return WIFI_SAR_CBFS_DEFAULT_FILENAME;
 }
+
+#define TP_TYPE_AUTO_SELECT 0
+#define TP_TYPE_ELAN0000 1
+#define TP_TYPE_ELAN2702 2
+
+void variant_devtree_update(void)
+{
+	struct device *tp_elan0000 = DEV_PTR(elan0000);
+	struct device *tp_elan2702 = DEV_PTR(elan2702);
+
+	/* Update touchpad device */
+	switch (get_uint_option("touchpad", TP_TYPE_AUTO_SELECT)) {
+	case TP_TYPE_ELAN0000:
+		tp_elan2702->enabled = 0;
+		break;
+	case TP_TYPE_ELAN2702:
+		tp_elan0000->enabled = 0;
+		break;
+	}
+}

From d0345005ad3d4bce087449177469156e3c24b6b1 Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Tue, 2 Dec 2025 15:36:13 -0600
Subject: [PATCH 2774/3886] mb/google/brox: Add CFR option menu support

Add CFR option menu support when using edk2 payload and SMMSTORE.
Include relevant items from Alderlake SoC, Intel common, and ChromeEC.

Change-Id: I99505f3f8b24c2f89329a3164963e874f5861374
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90351
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
---
 src/mainboard/google/brox/Kconfig     |  1 +
 src/mainboard/google/brox/Makefile.mk |  1 +
 src/mainboard/google/brox/cfr.c       | 46 +++++++++++++++++++++++++++
 3 files changed, 48 insertions(+)
 create mode 100644 src/mainboard/google/brox/cfr.c

diff --git a/src/mainboard/google/brox/Kconfig b/src/mainboard/google/brox/Kconfig
index 23cd594e20..cec63f53be 100644
--- a/src/mainboard/google/brox/Kconfig
+++ b/src/mainboard/google/brox/Kconfig
@@ -11,6 +11,7 @@ config BOARD_GOOGLE_BROX_COMMON
 	select DRIVERS_INTEL_PMC
 	select DRIVERS_INTEL_SOUNDWIRE
 	select DRIVERS_INTEL_USB4_RETIMER
+	select DRIVERS_OPTION_CFR_ENABLED if PAYLOAD_EDK2 && SMMSTORE
 	select DRIVERS_SPI_ACPI
 	select DRIVERS_WIFI_GENERIC
 	select EC_GOOGLE_CHROMEEC
diff --git a/src/mainboard/google/brox/Makefile.mk b/src/mainboard/google/brox/Makefile.mk
index 10f1230830..66d7f60cfc 100644
--- a/src/mainboard/google/brox/Makefile.mk
+++ b/src/mainboard/google/brox/Makefile.mk
@@ -11,6 +11,7 @@ ramstage-$(CONFIG_CHROMEOS) += chromeos.c
 ramstage-y += mainboard.c
 ramstage-y += ec.c
 ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_HDA_VERB) += hda_verb.c
+ramstage-$(CONFIG_DRIVERS_OPTION_CFR) += cfr.c
 
 BASEBOARD_DIR:=$(call strip_quotes,$(CONFIG_BASEBOARD_DIR))
 
diff --git a/src/mainboard/google/brox/cfr.c b/src/mainboard/google/brox/cfr.c
new file mode 100644
index 0000000000..2025ad32ee
--- /dev/null
+++ b/src/mainboard/google/brox/cfr.c
@@ -0,0 +1,46 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <boot/coreboot_tables.h>
+#include <drivers/option/cfr_frontend.h>
+#include <ec/google/chromeec/cfr.h>
+#include <intelblocks/cfr.h>
+#include <soc/cfr.h>
+
+static struct sm_obj_form system = {
+	.ui_name = "System",
+	.obj_list = (const struct sm_object *[]) {
+		&hyper_threading,
+		&igd_dvmt,
+		&igd_aperture,
+		&legacy_8254_timer,
+		&me_state,
+		&me_state_counter,
+		&pciexp_aspm,
+		&pciexp_clk_pm,
+		&pciexp_l1ss,
+		&pciexp_speed,
+		&s0ix_enable,
+		&vtd,
+		NULL
+	},
+};
+
+static struct sm_obj_form ec = {
+	.ui_name = "ChromeEC Embedded Controller",
+	.obj_list = (const struct sm_object *[]) {
+		&auto_fan_control,
+		&ec_kb_backlight,
+		NULL
+	},
+};
+
+static struct sm_obj_form *sm_root[] = {
+	&system,
+	&ec,
+	NULL
+};
+
+void mb_cfr_setup_menu(struct lb_cfr *cfr_root)
+{
+	cfr_write_setup_menu(cfr_root, sm_root);
+}

From e3bee6397d21db7e7c897ae484f87e17d266069c Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Tue, 2 Dec 2025 15:38:16 -0600
Subject: [PATCH 2775/3886] mb/google/rex: Add CFR option menu support

Add CFR option menu support when using edk2 payload and SMMSTORE.
Include relevant items from Meteorlake SoC, Intel common, and ChromeEC.

TEST=build/boot google/rex (karis), verify CFR option functionality.

Change-Id: Ic115272f69c2b37263d7ca0f921e6d9eceaaa8c3
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90352
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
---
 src/mainboard/google/rex/Kconfig     |  1 +
 src/mainboard/google/rex/Makefile.mk |  1 +
 src/mainboard/google/rex/cfr.c       | 46 ++++++++++++++++++++++++++++
 3 files changed, 48 insertions(+)
 create mode 100644 src/mainboard/google/rex/cfr.c

diff --git a/src/mainboard/google/rex/Kconfig b/src/mainboard/google/rex/Kconfig
index b5f5c10b98..f9afd38141 100644
--- a/src/mainboard/google/rex/Kconfig
+++ b/src/mainboard/google/rex/Kconfig
@@ -3,6 +3,7 @@
 config BOARD_GOOGLE_REX_COMMON
 	def_bool n
 	select BOARD_ROMSIZE_KB_32768
+	select DRIVERS_OPTION_CFR_ENABLED if PAYLOAD_EDK2 && SMMSTORE
 	select DRIVERS_GFX_GENERIC
 	select DRIVERS_I2C_GENERIC
 	select DRIVERS_I2C_HID
diff --git a/src/mainboard/google/rex/Makefile.mk b/src/mainboard/google/rex/Makefile.mk
index 8c60c591aa..08ef12e4b1 100644
--- a/src/mainboard/google/rex/Makefile.mk
+++ b/src/mainboard/google/rex/Makefile.mk
@@ -9,6 +9,7 @@ romstage-$(CONFIG_CHROMEOS) += chromeos.c
 
 ramstage-y += mainboard.c
 ramstage-$(CONFIG_CHROMEOS) += chromeos.c
+ramstage-$(CONFIG_DRIVERS_OPTION_CFR) += cfr.c
 ramstage-y += ec.c
 
 smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c
diff --git a/src/mainboard/google/rex/cfr.c b/src/mainboard/google/rex/cfr.c
new file mode 100644
index 0000000000..a84d9aae4d
--- /dev/null
+++ b/src/mainboard/google/rex/cfr.c
@@ -0,0 +1,46 @@
+
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <boot/coreboot_tables.h>
+#include <drivers/option/cfr_frontend.h>
+#include <ec/google/chromeec/cfr.h>
+#include <intelblocks/cfr.h>
+#include <soc/cfr.h>
+
+static struct sm_obj_form system = {
+	.ui_name = "System",
+	.obj_list = (const struct sm_object *[]) {
+		&hyper_threading,
+		&igd_dvmt,
+		&legacy_8254_timer,
+		&me_state,
+		&me_state_counter,
+		&pciexp_aspm,
+		&pciexp_clk_pm,
+		&pciexp_l1ss,
+		&pciexp_speed,
+		&s0ix_enable,
+		&vtd,
+		NULL
+	},
+};
+
+static struct sm_obj_form ec = {
+	.ui_name = "ChromeEC Embedded Controller",
+	.obj_list = (const struct sm_object *[]) {
+		&auto_fan_control,
+		&ec_kb_backlight,
+		NULL
+	},
+	};
+
+static struct sm_obj_form *sm_root[] = {
+	&system,
+	&ec,
+	NULL
+};
+
+void mb_cfr_setup_menu(struct lb_cfr *cfr_root)
+{
+	cfr_write_setup_menu(cfr_root, sm_root);
+}

From 46a32a2b5652f2f4d406a38ff0ae3c8d4aabd5e0 Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Tue, 2 Dec 2025 15:39:57 -0600
Subject: [PATCH 2776/3886] mb/google/sarien: Add CFR option menu support

Add CFR option menu support when using edk2 payload and SMMSTORE.
Include relevant items from Cometlake SoC and Intel common.

TEST=build/boot google/sarien, verify CFR option functionality.

Change-Id: Id7b023cecba36ac4a5c65eb5ece05361e8881980
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90353
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
---
 src/mainboard/google/sarien/Kconfig     |  1 +
 src/mainboard/google/sarien/Makefile.mk |  1 +
 src/mainboard/google/sarien/cfr.c       | 36 +++++++++++++++++++++++++
 3 files changed, 38 insertions(+)
 create mode 100644 src/mainboard/google/sarien/cfr.c

diff --git a/src/mainboard/google/sarien/Kconfig b/src/mainboard/google/sarien/Kconfig
index d01866bf8a..dcf94470ec 100644
--- a/src/mainboard/google/sarien/Kconfig
+++ b/src/mainboard/google/sarien/Kconfig
@@ -8,6 +8,7 @@ config BOARD_GOOGLE_BASEBOARD_SARIEN
 	select DRIVERS_GFX_GENERIC
 	select DRIVERS_I2C_GENERIC
 	select DRIVERS_I2C_HID
+	select DRIVERS_OPTION_CFR_ENABLED if PAYLOAD_EDK2 && SMMSTORE
 	select DRIVERS_SPI_ACPI
 	select DRIVERS_USB_ACPI
 	select EC_GOOGLE_WILCO
diff --git a/src/mainboard/google/sarien/Makefile.mk b/src/mainboard/google/sarien/Makefile.mk
index 6bc69efbc9..4f2286a2c1 100644
--- a/src/mainboard/google/sarien/Makefile.mk
+++ b/src/mainboard/google/sarien/Makefile.mk
@@ -4,6 +4,7 @@ bootblock-y += bootblock.c
 
 ramstage-y += ramstage.c
 ramstage-y += sku.c
+ramstage-$(CONFIG_DRIVERS_OPTION_CFR) += cfr.c
 
 romstage-y += romstage.c
 
diff --git a/src/mainboard/google/sarien/cfr.c b/src/mainboard/google/sarien/cfr.c
new file mode 100644
index 0000000000..aa9265db7d
--- /dev/null
+++ b/src/mainboard/google/sarien/cfr.c
@@ -0,0 +1,36 @@
+
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <boot/coreboot_tables.h>
+#include <drivers/option/cfr_frontend.h>
+#include <intelblocks/cfr.h>
+#include <soc/cfr.h>
+
+static struct sm_obj_form system = {
+	.ui_name = "System",
+	.obj_list = (const struct sm_object *[]) {
+		&hyper_threading,
+		&igd_dvmt,
+		&igd_aperture,
+		&legacy_8254_timer,
+		&me_state,
+		&me_state_counter,
+		&pciexp_aspm,
+		&pciexp_clk_pm,
+		&pciexp_l1ss,
+		&pciexp_speed,
+		&s0ix_enable,
+		&vtd,
+		NULL
+	},
+};
+
+static struct sm_obj_form *sm_root[] = {
+	&system,
+	NULL
+};
+
+void mb_cfr_setup_menu(struct lb_cfr *cfr_root)
+{
+	cfr_write_setup_menu(cfr_root, sm_root);
+}

From d105934073ae3fd31cf87d0f46e880b1905978a2 Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Mon, 1 Dec 2025 20:20:11 -0600
Subject: [PATCH 2777/3886] mb/google/kahlee: Add CFR option menu support

Add CFR option menu support when using edk2 payload and SMMSTORE.
Include relevant items from ChromeEC.

TEST=build/boot google/kahlee (liara), verify CFR option functionality

Change-Id: I19f059f1e0c0e7c71e5e84560fe72f271d33412c
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90312
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
---
 src/mainboard/google/kahlee/Kconfig     |  1 +
 src/mainboard/google/kahlee/Makefile.mk |  1 +
 src/mainboard/google/kahlee/cfr.c       | 23 +++++++++++++++++++++++
 3 files changed, 25 insertions(+)
 create mode 100644 src/mainboard/google/kahlee/cfr.c

diff --git a/src/mainboard/google/kahlee/Kconfig b/src/mainboard/google/kahlee/Kconfig
index 60630fe5c1..b3fb71a04e 100644
--- a/src/mainboard/google/kahlee/Kconfig
+++ b/src/mainboard/google/kahlee/Kconfig
@@ -15,6 +15,7 @@ config BOARD_GOOGLE_BASEBOARD_KAHLEE
 	select DRIVERS_I2C_DA7219
 	select DRIVERS_I2C_GENERIC
 	select DRIVERS_I2C_HID
+	select DRIVERS_OPTION_CFR_ENABLED if PAYLOAD_EDK2 && SMMSTORE
 	select EC_GOOGLE_CHROMEEC
 	select EC_GOOGLE_CHROMEEC_BOARDID
 	select EC_GOOGLE_CHROMEEC_LPC
diff --git a/src/mainboard/google/kahlee/Makefile.mk b/src/mainboard/google/kahlee/Makefile.mk
index 94705922a6..687b015e35 100644
--- a/src/mainboard/google/kahlee/Makefile.mk
+++ b/src/mainboard/google/kahlee/Makefile.mk
@@ -12,6 +12,7 @@ ramstage-y += BiosCallOuts.c
 ramstage-y += chromeos.c
 ramstage-y += ec.c
 ramstage-y += OemCustomize.c
+ramstage-$(CONFIG_DRIVERS_OPTION_CFR) += cfr.c
 
 verstage-y += chromeos.c
 verstage-y += ec.c
diff --git a/src/mainboard/google/kahlee/cfr.c b/src/mainboard/google/kahlee/cfr.c
new file mode 100644
index 0000000000..8e6ac7dfcf
--- /dev/null
+++ b/src/mainboard/google/kahlee/cfr.c
@@ -0,0 +1,23 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <boot/coreboot_tables.h>
+#include <drivers/option/cfr_frontend.h>
+#include <ec/google/chromeec/cfr.h>
+
+static struct sm_obj_form ec = {
+	.ui_name = "ChromeEC Embedded Controller",
+	.obj_list = (const struct sm_object *[]) {
+		&ec_kb_backlight,
+		NULL
+	},
+};
+
+static struct sm_obj_form *sm_root[] = {
+	&ec,
+	NULL
+};
+
+void mb_cfr_setup_menu(struct lb_cfr *cfr_root)
+{
+	cfr_write_setup_menu(cfr_root, sm_root);
+}

From c1f0be39dae430392de5ead0ec244d7df200f7de Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Mon, 1 Dec 2025 20:17:02 -0600
Subject: [PATCH 2778/3886] mb/google/zork: Add CFR option menu support

Add CFR option menu support when using edk2 payload and SMMSTORE.
Include relevant items from ChromeEC.

TEST=build/boot google/zork (morphius), verify CFR option functionality

Change-Id: I21f6d01ab425fb698872735bca3514ae366bcdda
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90313
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
---
 src/mainboard/google/zork/Kconfig     |  1 +
 src/mainboard/google/zork/Makefile.mk |  1 +
 src/mainboard/google/zork/cfr.c       | 24 ++++++++++++++++++++++++
 3 files changed, 26 insertions(+)
 create mode 100644 src/mainboard/google/zork/cfr.c

diff --git a/src/mainboard/google/zork/Kconfig b/src/mainboard/google/zork/Kconfig
index b998de0f1c..b828a5a004 100644
--- a/src/mainboard/google/zork/Kconfig
+++ b/src/mainboard/google/zork/Kconfig
@@ -55,6 +55,7 @@ config BOARD_SPECIFIC_OPTIONS
 	select DRIVERS_USB_ACPI
 	select DRIVERS_I2C_GENERIC
 	select DRIVERS_I2C_HID
+	select DRIVERS_OPTION_CFR_ENABLED if PAYLOAD_EDK2 && SMMSTORE
 	select EC_GOOGLE_CHROMEEC
 	select EC_GOOGLE_CHROMEEC_AUDIO_CODEC
 	select EC_GOOGLE_CHROMEEC_BOARDID
diff --git a/src/mainboard/google/zork/Makefile.mk b/src/mainboard/google/zork/Makefile.mk
index df809cb488..b68fe19587 100644
--- a/src/mainboard/google/zork/Makefile.mk
+++ b/src/mainboard/google/zork/Makefile.mk
@@ -9,6 +9,7 @@ romstage-y += romstage.c
 ramstage-y += chromeos.c
 ramstage-y += ec.c
 ramstage-y += sku_id.c
+ramstage-$(CONFIG_DRIVERS_OPTION_CFR) += cfr.c
 
 verstage-y += chromeos.c
 verstage-y += verstage.c
diff --git a/src/mainboard/google/zork/cfr.c b/src/mainboard/google/zork/cfr.c
new file mode 100644
index 0000000000..5565d31cd8
--- /dev/null
+++ b/src/mainboard/google/zork/cfr.c
@@ -0,0 +1,24 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <boot/coreboot_tables.h>
+#include <drivers/option/cfr_frontend.h>
+#include <ec/google/chromeec/cfr.h>
+
+static struct sm_obj_form ec = {
+	.ui_name = "ChromeEC Embedded Controller",
+	.obj_list = (const struct sm_object *[]) {
+		&auto_fan_control
+		&ec_kb_backlight,
+		NULL
+	},
+};
+
+static struct sm_obj_form *sm_root[] = {
+	&ec,
+	NULL
+};
+
+void mb_cfr_setup_menu(struct lb_cfr *cfr_root)
+{
+	cfr_write_setup_menu(cfr_root, sm_root);
+}

From c397821cb69a4e35eae69adae78dc352193078b8 Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Mon, 1 Dec 2025 20:22:32 -0600
Subject: [PATCH 2779/3886] mb/google/guybrush: Add CFR option menu support

Add CFR option menu support when using edk2 payload and SMMSTORE.
Include relevant items from ChromeEC.

TEST=build/boot google/guybrush (dewatt), verify CFR option
functionality.

Change-Id: I16e80e2ba1e51617956043137cd8fee1400b57f2
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90314
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/google/guybrush/Kconfig     |  1 +
 src/mainboard/google/guybrush/Makefile.mk |  1 +
 src/mainboard/google/guybrush/cfr.c       | 24 +++++++++++++++++++++++
 3 files changed, 26 insertions(+)
 create mode 100644 src/mainboard/google/guybrush/cfr.c

diff --git a/src/mainboard/google/guybrush/Kconfig b/src/mainboard/google/guybrush/Kconfig
index 8c85f9723f..dae3bf7170 100644
--- a/src/mainboard/google/guybrush/Kconfig
+++ b/src/mainboard/google/guybrush/Kconfig
@@ -15,6 +15,7 @@ config BOARD_GOOGLE_BASEBOARD_GUYBRUSH
 	select DRIVERS_GENERIC_MAX98357A
 	select DRIVERS_I2C_GENERIC
 	select DRIVERS_I2C_HID
+	select DRIVERS_OPTION_CFR_ENABLED if PAYLOAD_EDK2 && SMMSTORE
 	select DRIVERS_PCIE_RTD3_DEVICE
 	select DRIVERS_UART_ACPI
 	select DRIVERS_PCIE_GENERIC
diff --git a/src/mainboard/google/guybrush/Makefile.mk b/src/mainboard/google/guybrush/Makefile.mk
index fd03124dcd..7fc60b88ba 100644
--- a/src/mainboard/google/guybrush/Makefile.mk
+++ b/src/mainboard/google/guybrush/Makefile.mk
@@ -10,6 +10,7 @@ ramstage-y += mainboard.c
 ramstage-y += ec.c
 ramstage-y += port_descriptors.c
 ramstage-$(CONFIG_CHROMEOS) += chromeos.c
+ramstage-$(CONFIG_DRIVERS_OPTION_CFR) += cfr.c
 
 all-y += spi_speeds.c
 
diff --git a/src/mainboard/google/guybrush/cfr.c b/src/mainboard/google/guybrush/cfr.c
new file mode 100644
index 0000000000..5822ae9226
--- /dev/null
+++ b/src/mainboard/google/guybrush/cfr.c
@@ -0,0 +1,24 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <boot/coreboot_tables.h>
+#include <drivers/option/cfr_frontend.h>
+#include <ec/google/chromeec/cfr.h>
+
+static struct sm_obj_form ec = {
+	.ui_name = "ChromeEC Embedded Controller",
+	.obj_list = (const struct sm_object *[]) {
+		&ec_kb_backlight,
+		&auto_fan_control,
+		NULL
+	},
+};
+
+static struct sm_obj_form *sm_root[] = {
+	&ec,
+	NULL
+};
+
+void mb_cfr_setup_menu(struct lb_cfr *cfr_root)
+{
+	cfr_write_setup_menu(cfr_root, sm_root);
+}

From 0d81d38a31f846df7f799ec85ea2724ed17b94f6 Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Mon, 1 Dec 2025 20:23:58 -0600
Subject: [PATCH 2780/3886] mb/google/skyrim: Add CFR option menu support

Add CFR option menu support when using edk2 payload and SMMSTORE.
Include relevant items from ChromeEC.

TEST=build/boot google/skyrim (frostflow), verify CFR option
functionality.

Change-Id: Ife5b20725794cdecc47f632e10421b86ceac68a5
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90315
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/google/skyrim/Kconfig     |  1 +
 src/mainboard/google/skyrim/Makefile.mk |  1 +
 src/mainboard/google/skyrim/cfr.c       | 24 ++++++++++++++++++++++++
 3 files changed, 26 insertions(+)
 create mode 100644 src/mainboard/google/skyrim/cfr.c

diff --git a/src/mainboard/google/skyrim/Kconfig b/src/mainboard/google/skyrim/Kconfig
index e1718bb2fd..4977602d3b 100644
--- a/src/mainboard/google/skyrim/Kconfig
+++ b/src/mainboard/google/skyrim/Kconfig
@@ -42,6 +42,7 @@ config BOARD_SPECIFIC_OPTIONS
 	select DRIVERS_I2C_GENERIC
 	select DRIVERS_I2C_HID
 	select DRIVERS_I2C_NAU8825
+	select DRIVERS_OPTION_CFR_ENABLED if PAYLOAD_EDK2 && SMMSTORE
 	select DRIVERS_USB_HUB
 	select DRIVERS_UART_ACPI
 	select DRIVERS_PCIE_GENERIC
diff --git a/src/mainboard/google/skyrim/Makefile.mk b/src/mainboard/google/skyrim/Makefile.mk
index 933341314e..8240e3e214 100644
--- a/src/mainboard/google/skyrim/Makefile.mk
+++ b/src/mainboard/google/skyrim/Makefile.mk
@@ -8,6 +8,7 @@ ramstage-y += mainboard.c
 ramstage-y += ec.c
 ramstage-y += port_descriptors.c
 ramstage-$(CONFIG_CHROMEOS) += chromeos.c
+ramstage-$(CONFIG_DRIVERS_OPTION_CFR) += cfr.c
 
 verstage-$(CONFIG_VBOOT_STARTS_BEFORE_BOOTBLOCK) += verstage.c
 
diff --git a/src/mainboard/google/skyrim/cfr.c b/src/mainboard/google/skyrim/cfr.c
new file mode 100644
index 0000000000..5822ae9226
--- /dev/null
+++ b/src/mainboard/google/skyrim/cfr.c
@@ -0,0 +1,24 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <boot/coreboot_tables.h>
+#include <drivers/option/cfr_frontend.h>
+#include <ec/google/chromeec/cfr.h>
+
+static struct sm_obj_form ec = {
+	.ui_name = "ChromeEC Embedded Controller",
+	.obj_list = (const struct sm_object *[]) {
+		&ec_kb_backlight,
+		&auto_fan_control,
+		NULL
+	},
+};
+
+static struct sm_obj_form *sm_root[] = {
+	&ec,
+	NULL
+};
+
+void mb_cfr_setup_menu(struct lb_cfr *cfr_root)
+{
+	cfr_write_setup_menu(cfr_root, sm_root);
+}

From 99d67bae637b935573bfbeb98598ba1e8d5d285f Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Mon, 1 Dec 2025 20:31:43 -0600
Subject: [PATCH 2781/3886] mb/google/glados: Add CFR option menu support

Add CFR option menu support when using edk2 payload and SMMSTORE.
Include relevant items from Skylake SoC, Intel common, and ChromeEC.

TEST=build/boot google/glados (chell), verify CFR option
functionality.

Change-Id: Ie124d69e979c7d0ca8dd119046412cb637eb04da
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90316
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
---
 src/mainboard/google/glados/Kconfig     |  1 +
 src/mainboard/google/glados/Makefile.mk |  2 +-
 src/mainboard/google/glados/cfr.c       | 46 +++++++++++++++++++++++++
 3 files changed, 48 insertions(+), 1 deletion(-)
 create mode 100644 src/mainboard/google/glados/cfr.c

diff --git a/src/mainboard/google/glados/Kconfig b/src/mainboard/google/glados/Kconfig
index 779dc48bac..811a03deac 100644
--- a/src/mainboard/google/glados/Kconfig
+++ b/src/mainboard/google/glados/Kconfig
@@ -5,6 +5,7 @@ config BOARD_GOOGLE_BASEBOARD_GLADOS
 	select BOARD_ROMSIZE_KB_16384
 	select DRIVERS_I2C_GENERIC
 	select DRIVERS_I2C_NAU8825
+	select DRIVERS_OPTION_CFR_ENABLED if PAYLOAD_EDK2 && SMMSTORE
 	select EC_GOOGLE_CHROMEEC
 	select EC_GOOGLE_CHROMEEC_BOARDID
 	select EC_GOOGLE_CHROMEEC_LPC
diff --git a/src/mainboard/google/glados/Makefile.mk b/src/mainboard/google/glados/Makefile.mk
index 9fd41f89a7..dc6e3393d7 100644
--- a/src/mainboard/google/glados/Makefile.mk
+++ b/src/mainboard/google/glados/Makefile.mk
@@ -12,7 +12,7 @@ romstage-$(CONFIG_CHROMEOS) += chromeos.c
 ramstage-$(CONFIG_CHROMEOS) += chromeos.c
 
 ramstage-$(CONFIG_EC_GOOGLE_CHROMEEC) += ec.c
-
+ramstage-$(CONFIG_DRIVERS_OPTION_CFR) += cfr.c
 ramstage-y += mainboard.c
 
 ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads
diff --git a/src/mainboard/google/glados/cfr.c b/src/mainboard/google/glados/cfr.c
new file mode 100644
index 0000000000..2025ad32ee
--- /dev/null
+++ b/src/mainboard/google/glados/cfr.c
@@ -0,0 +1,46 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <boot/coreboot_tables.h>
+#include <drivers/option/cfr_frontend.h>
+#include <ec/google/chromeec/cfr.h>
+#include <intelblocks/cfr.h>
+#include <soc/cfr.h>
+
+static struct sm_obj_form system = {
+	.ui_name = "System",
+	.obj_list = (const struct sm_object *[]) {
+		&hyper_threading,
+		&igd_dvmt,
+		&igd_aperture,
+		&legacy_8254_timer,
+		&me_state,
+		&me_state_counter,
+		&pciexp_aspm,
+		&pciexp_clk_pm,
+		&pciexp_l1ss,
+		&pciexp_speed,
+		&s0ix_enable,
+		&vtd,
+		NULL
+	},
+};
+
+static struct sm_obj_form ec = {
+	.ui_name = "ChromeEC Embedded Controller",
+	.obj_list = (const struct sm_object *[]) {
+		&auto_fan_control,
+		&ec_kb_backlight,
+		NULL
+	},
+};
+
+static struct sm_obj_form *sm_root[] = {
+	&system,
+	&ec,
+	NULL
+};
+
+void mb_cfr_setup_menu(struct lb_cfr *cfr_root)
+{
+	cfr_write_setup_menu(cfr_root, sm_root);
+}

From ae8f2d8cee067841ee6f13c555484f43c3ad2548 Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Mon, 1 Dec 2025 20:25:46 -0600
Subject: [PATCH 2782/3886] mb/google/poppy: Add CFR option menu support

Add CFR option menu support when using edk2 payload and SMMSTORE.
Include relevant items from Kabylake SoC, Intel common, and ChromeEC.

TEST=build/boot google/poppy (nocturne), verify CFR option
functionality.

Change-Id: Ib63c2a105a715a540a93b6163ff7e6f86deab5d0
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90317
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
---
 src/mainboard/google/poppy/Kconfig     |  1 +
 src/mainboard/google/poppy/Makefile.mk |  1 +
 src/mainboard/google/poppy/cfr.c       | 46 ++++++++++++++++++++++++++
 3 files changed, 48 insertions(+)
 create mode 100644 src/mainboard/google/poppy/cfr.c

diff --git a/src/mainboard/google/poppy/Kconfig b/src/mainboard/google/poppy/Kconfig
index fea28b4f25..a9b45920db 100644
--- a/src/mainboard/google/poppy/Kconfig
+++ b/src/mainboard/google/poppy/Kconfig
@@ -6,6 +6,7 @@ config BOARD_GOOGLE_BASEBOARD_POPPY
 	select DRIVERS_GENERIC_GPIO_KEYS
 	select DRIVERS_I2C_GENERIC
 	select DRIVERS_I2C_HID
+	select DRIVERS_OPTION_CFR_ENABLED if PAYLOAD_EDK2 && SMMSTORE
 	select EC_GOOGLE_CHROMEEC
 	select EC_GOOGLE_CHROMEEC_BOARDID
 	select EC_GOOGLE_CHROMEEC_ESPI
diff --git a/src/mainboard/google/poppy/Makefile.mk b/src/mainboard/google/poppy/Makefile.mk
index 9f36e79463..65b8a87895 100644
--- a/src/mainboard/google/poppy/Makefile.mk
+++ b/src/mainboard/google/poppy/Makefile.mk
@@ -8,6 +8,7 @@ verstage-$(CONFIG_CHROMEOS) += chromeos.c
 romstage-$(CONFIG_CHROMEOS) += chromeos.c
 
 ramstage-$(CONFIG_CHROMEOS) += chromeos.c
+ramstage-$(CONFIG_DRIVERS_OPTION_CFR) += cfr.c
 ramstage-$(CONFIG_EC_GOOGLE_CHROMEEC) += ec.c
 ramstage-y += mainboard.c
 ramstage-y += ramstage.c
diff --git a/src/mainboard/google/poppy/cfr.c b/src/mainboard/google/poppy/cfr.c
new file mode 100644
index 0000000000..2025ad32ee
--- /dev/null
+++ b/src/mainboard/google/poppy/cfr.c
@@ -0,0 +1,46 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <boot/coreboot_tables.h>
+#include <drivers/option/cfr_frontend.h>
+#include <ec/google/chromeec/cfr.h>
+#include <intelblocks/cfr.h>
+#include <soc/cfr.h>
+
+static struct sm_obj_form system = {
+	.ui_name = "System",
+	.obj_list = (const struct sm_object *[]) {
+		&hyper_threading,
+		&igd_dvmt,
+		&igd_aperture,
+		&legacy_8254_timer,
+		&me_state,
+		&me_state_counter,
+		&pciexp_aspm,
+		&pciexp_clk_pm,
+		&pciexp_l1ss,
+		&pciexp_speed,
+		&s0ix_enable,
+		&vtd,
+		NULL
+	},
+};
+
+static struct sm_obj_form ec = {
+	.ui_name = "ChromeEC Embedded Controller",
+	.obj_list = (const struct sm_object *[]) {
+		&auto_fan_control,
+		&ec_kb_backlight,
+		NULL
+	},
+};
+
+static struct sm_obj_form *sm_root[] = {
+	&system,
+	&ec,
+	NULL
+};
+
+void mb_cfr_setup_menu(struct lb_cfr *cfr_root)
+{
+	cfr_write_setup_menu(cfr_root, sm_root);
+}

From 75460f531c17832ab8622bda994c6b97e3ca140f Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Tue, 14 Oct 2025 18:48:17 -0500
Subject: [PATCH 2783/3886] mb/google/poppy: Add CFR option to enable/disable
 IPU cameras

IPU cameras on popp-based devices are currently not properly supported
under Windows, which causes the camera status LED to be permanently on
when using Windows. To work around this, add a CFR option to disable
the IPU camera(s) on a given board.

TEST=build/boot google/poppy (nocturne), verify camera status LED is
off when CFR option disable and Windows booted.

Change-Id: I664ecac47211350b861504c3075e524f045dbf40
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90318
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
---
 src/mainboard/google/poppy/cfr.c              | 24 +++++++++++++++++++
 src/mainboard/google/poppy/mainboard.c        | 13 ++++++++++
 .../atlas/include/variant/acpi/cam0.asl       |  6 +++--
 .../baseboard/include/baseboard/acpi/cam0.asl |  9 ++++---
 .../baseboard/include/baseboard/acpi/cam1.asl |  3 ++-
 .../include/baseboard/acpi/camera_pmic.asl    |  3 ++-
 .../nautilus/include/variant/acpi/cam0.asl    |  9 ++++---
 .../nocturne/include/variant/acpi/cam0.asl    |  6 +++--
 .../nocturne/include/variant/acpi/cam1.asl    |  9 ++++---
 9 files changed, 67 insertions(+), 15 deletions(-)

diff --git a/src/mainboard/google/poppy/cfr.c b/src/mainboard/google/poppy/cfr.c
index 2025ad32ee..01793c080c 100644
--- a/src/mainboard/google/poppy/cfr.c
+++ b/src/mainboard/google/poppy/cfr.c
@@ -6,6 +6,21 @@
 #include <intelblocks/cfr.h>
 #include <soc/cfr.h>
 
+static const struct sm_object ipu_camera = SM_DECLARE_ENUM({
+	.opt_name	= "ipu_camera",
+	.ui_name	= "IPU Camera",
+	.ui_helptext	= "Enable or disable integrated camera devices",
+	.default_value	= true,
+	.values		= (const struct sm_enum_value[]) {
+		{ "Disabled",		0		},
+		{ "Enabled",		1		},
+		SM_ENUM_VALUE_END			},
+	#if !CONFIG(VARIANT_HAS_CAMERA_ACPI)
+	.flags		= CFR_OPTFLAG_SUPPRESS,
+	#endif
+});
+
+
 static struct sm_obj_form system = {
 	.ui_name = "System",
 	.obj_list = (const struct sm_object *[]) {
@@ -34,9 +49,18 @@ static struct sm_obj_form ec = {
 	},
 };
 
+static struct sm_obj_form devices = {
+	.ui_name = "Devices",
+	.obj_list = (const struct sm_object *[]) {
+		&ipu_camera,
+		NULL
+	},
+};
+
 static struct sm_obj_form *sm_root[] = {
 	&system,
 	&ec,
+	&devices,
 	NULL
 };
 
diff --git a/src/mainboard/google/poppy/mainboard.c b/src/mainboard/google/poppy/mainboard.c
index 30b46fb771..b9847b7ac1 100644
--- a/src/mainboard/google/poppy/mainboard.c
+++ b/src/mainboard/google/poppy/mainboard.c
@@ -1,9 +1,11 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
 #include <acpi/acpi.h>
+#include <acpi/acpigen.h>
 #include <baseboard/variants.h>
 #include <device/device.h>
 #include <ec/ec.h>
+#include <option.h>
 #include <soc/pci_devs.h>
 #include <soc/nhlt.h>
 
@@ -14,6 +16,16 @@ static void mainboard_init(struct device *dev)
 	mainboard_ec_init();
 }
 
+static void mainboard_fill_ssdt(const struct device *dev)
+{
+	/* Get camera enable option from CFR */
+	unsigned int camera_enabled = get_uint_option("ipu_camera", 1);
+
+	acpigen_write_scope("\\_SB.PCI0");
+	acpigen_write_name_integer("CSTA", camera_enabled ? 0xF : 0x0);
+	acpigen_pop_len(); /* Scope */
+}
+
 static unsigned long mainboard_write_acpi_tables(const struct device *device,
 	unsigned long current, acpi_rsdp_t *rsdp)
 {
@@ -47,6 +59,7 @@ static void mainboard_enable(struct device *dev)
 {
 	dev->ops->init = mainboard_init;
 	dev->ops->write_acpi_tables = mainboard_write_acpi_tables;
+	dev->ops->acpi_fill_ssdt = mainboard_fill_ssdt;
 }
 
 static void mainboard_chip_init(void *chip_info)
diff --git a/src/mainboard/google/poppy/variants/atlas/include/variant/acpi/cam0.asl b/src/mainboard/google/poppy/variants/atlas/include/variant/acpi/cam0.asl
index a3098a961f..a5779524f9 100644
--- a/src/mainboard/google/poppy/variants/atlas/include/variant/acpi/cam0.asl
+++ b/src/mainboard/google/poppy/variants/atlas/include/variant/acpi/cam0.asl
@@ -49,10 +49,11 @@ Scope (\_SB.PCI0.I2C3)
 		Name (_HID, "INT3478")
 		Name (_UID, 0)
 		Name (_DDN, "SONY IMX208 Camera")  /* _DDN: DOS Device Name */
+		External (CSTA, IntObj)
 
 		Method (_STA, 0, NotSerialized)
 		{
-			Return (0x0F)
+			Return (CSTA)
 		}
 
 		Name (_CRS, ResourceTemplate ()
@@ -111,10 +112,11 @@ Scope (\_SB.PCI0.I2C3)
 		Name (_HID, "INT3499")
 		Name (_UID, 0)
 		Name (_DDN, "GT24C16S")  /* _DDN: DOS Device Name */
+		External (CSTA, IntObj)
 
 		Method (_STA, 0, NotSerialized)
 		{
-			Return (0x0F)
+			Return (CSTA)
 		}
 
 		Name (_CRS, ResourceTemplate ()
diff --git a/src/mainboard/google/poppy/variants/baseboard/include/baseboard/acpi/cam0.asl b/src/mainboard/google/poppy/variants/baseboard/include/baseboard/acpi/cam0.asl
index d7b7aef505..8dc9068c33 100644
--- a/src/mainboard/google/poppy/variants/baseboard/include/baseboard/acpi/cam0.asl
+++ b/src/mainboard/google/poppy/variants/baseboard/include/baseboard/acpi/cam0.asl
@@ -8,10 +8,11 @@ Scope (\_SB.PCI0.I2C2)
 		Name (_UID, 0)
 		Name (_DDN, "OV 13858 Camera") /* _DDN: DOS Device Name */
 		Name (CAMD, 0x02)
+		External (CSTA, IntObj)
 
 		Method (_STA, 0, NotSerialized)
 		{
-			Return (0x0F)
+			Return (CSTA)
 		}
 
 		Name (_DEP, Package() { \_SB.PCI0.I2C2.PMIC })
@@ -95,10 +96,11 @@ Scope (\_SB.PCI0.I2C2)
 		Name (_UID, 0)
 		Name (_DDN, "Dongwoon AF DAC") /* _DDN: DOS Device Name */
 		Name (CAMD, 0x03)
+		External (CSTA, IntObj)
 
 		Method (_STA, 0, NotSerialized)
 		{
-			Return (0x0F)
+			Return (CSTA)
 		}
 
 		Name (_DEP, Package() { \_SB.PCI0.I2C2.PMIC })
@@ -126,10 +128,11 @@ Scope (\_SB.PCI0.I2C2)
 		Name (_HID, "INT3499")
 		Name (_UID, 0)
 		Name (_DDN, "GT24C16S/CAT24C16")  /* _DDN: DOS Device Name */
+		External (CSTA, IntObj)
 
 		Method (_STA, 0, NotSerialized)
 		{
-			Return (0x0F)
+			Return (CSTA)
 		}
 
 		Name (_DEP, Package() { \_SB.PCI0.I2C2.PMIC })
diff --git a/src/mainboard/google/poppy/variants/baseboard/include/baseboard/acpi/cam1.asl b/src/mainboard/google/poppy/variants/baseboard/include/baseboard/acpi/cam1.asl
index 38284b33f2..286c1699de 100644
--- a/src/mainboard/google/poppy/variants/baseboard/include/baseboard/acpi/cam1.asl
+++ b/src/mainboard/google/poppy/variants/baseboard/include/baseboard/acpi/cam1.asl
@@ -8,10 +8,11 @@ Scope (\_SB.PCI0.I2C4)
 		Name (_UID, 0)
 		Name (_DDN, "OV 5670 Camera")  /* _DDN: DOS Device Name */
 		Name (CAMD, 0x02)
+		External (CSTA, IntObj)
 
 		Method (_STA, 0, NotSerialized)
 		{
-			Return (0x0F)
+			Return (CSTA)
 		}
 
 		Name (_DEP, Package() { \_SB.PCI0.I2C2.PMIC })
diff --git a/src/mainboard/google/poppy/variants/baseboard/include/baseboard/acpi/camera_pmic.asl b/src/mainboard/google/poppy/variants/baseboard/include/baseboard/acpi/camera_pmic.asl
index 82f52b9d36..0294cab6e7 100644
--- a/src/mainboard/google/poppy/variants/baseboard/include/baseboard/acpi/camera_pmic.asl
+++ b/src/mainboard/google/poppy/variants/baseboard/include/baseboard/acpi/camera_pmic.asl
@@ -8,10 +8,11 @@ Scope (\_SB.PCI0.I2C2)
 		Name (_UID, 0)
 		Name (_DDN, "TPS68470 PMIC")  /* _DDN: DOS Device Name */
 		Name (CAMD, 0x64)
+		External (CSTA, IntObj)
 
 		Method (_STA, 0, NotSerialized)
 		{
-			Return (0x0F)
+			Return (CSTA)
 		}
 
 		Method (PMON, 0, Serialized) {
diff --git a/src/mainboard/google/poppy/variants/nautilus/include/variant/acpi/cam0.asl b/src/mainboard/google/poppy/variants/nautilus/include/variant/acpi/cam0.asl
index fd1c6eed20..f6bc683aac 100644
--- a/src/mainboard/google/poppy/variants/nautilus/include/variant/acpi/cam0.asl
+++ b/src/mainboard/google/poppy/variants/nautilus/include/variant/acpi/cam0.asl
@@ -7,10 +7,11 @@ Scope (\_SB.PCI0.I2C2)
 		Name (_HID, "SONY258A")
 		Name (_UID, 0)
 		Name (_DDN, "SONY IMX258 Camera") /* _DDN: DOS Device Name */
+		External (CSTA, IntObj)
 
 		Method (_STA, 0, NotSerialized)
 		{
-			Return (0x0F)
+			Return (CSTA)
 		}
 
 		Name (_DEP, Package() { \_SB.PCI0.I2C2.PMIC })
@@ -75,10 +76,11 @@ Scope (\_SB.PCI0.I2C2)
 		Name (_HID, "PRP0001")
 		Name (_UID, 0)
 		Name (_DDN, "Dongwoon AF DAC") /* _DDN: DOS Device Name */
+		External (CSTA, IntObj)
 
 		Method (_STA, 0, NotSerialized)
 		{
-			Return (0x0F)
+			Return (CSTA)
 		}
 
 		Name (_DEP, Package() { \_SB.PCI0.I2C2.PMIC })
@@ -106,10 +108,11 @@ Scope (\_SB.PCI0.I2C2)
 		Name (_HID, "INT3499")
 		Name (_UID, 0)
 		Name (_DDN, "Dongwoon NVM")  /* _DDN: DOS Device Name */
+		External (CSTA, IntObj)
 
 		Method (_STA, 0, NotSerialized)
 		{
-			Return (0x0F)
+			Return (CSTA)
 		}
 
 		Name (_DEP, Package() { \_SB.PCI0.I2C2.PMIC })
diff --git a/src/mainboard/google/poppy/variants/nocturne/include/variant/acpi/cam0.asl b/src/mainboard/google/poppy/variants/nocturne/include/variant/acpi/cam0.asl
index cedab20530..ac3413a4fd 100644
--- a/src/mainboard/google/poppy/variants/nocturne/include/variant/acpi/cam0.asl
+++ b/src/mainboard/google/poppy/variants/nocturne/include/variant/acpi/cam0.asl
@@ -43,10 +43,11 @@ Scope (\_SB.PCI0.I2C3)
 		Name (_HID, "SONY319A")
 		Name (_UID, 0)
 		Name (_DDN, "Sony IMX319 Camera")  /* _DDN: DOS Device Name */
+		External (CSTA, IntObj)
 
 		Method (_STA, 0, NotSerialized)
 		{
-			Return (0x0F)
+			Return (CSTA)
 		}
 
 		Name (_CRS, ResourceTemplate ()
@@ -106,10 +107,11 @@ Scope (\_SB.PCI0.I2C3)
 		Name (_HID, "INT3499")
 		Name (_UID, 0)
 		Name (_DDN, "M24C64S")  /* _DDN: DOS Device Name */
+		External (CSTA, IntObj)
 
 		Method (_STA, 0, NotSerialized)
 		{
-			Return (0x0F)
+			Return (CSTA)
 		}
 
 		Name (_CRS, ResourceTemplate ()
diff --git a/src/mainboard/google/poppy/variants/nocturne/include/variant/acpi/cam1.asl b/src/mainboard/google/poppy/variants/nocturne/include/variant/acpi/cam1.asl
index bab32e9f5d..50d672172f 100644
--- a/src/mainboard/google/poppy/variants/nocturne/include/variant/acpi/cam1.asl
+++ b/src/mainboard/google/poppy/variants/nocturne/include/variant/acpi/cam1.asl
@@ -42,10 +42,11 @@ Scope (\_SB.PCI0.I2C5)
 		Name (_HID, "SONY355A")
 		Name (_UID, 0)
 		Name (_DDN, "SONY IMX355A Camera") /* _DDN: DOS Device Name */
+		External (CSTA, IntObj)
 
 		Method (_STA, 0, NotSerialized)
 		{
-			Return (0x0F)
+			Return (CSTA)
 		}
 
 		Name (_CRS, ResourceTemplate ()
@@ -108,10 +109,11 @@ Scope (\_SB.PCI0.I2C5)
 		Name (_HID, "PRP0001")
 		Name (_UID, 3)
 		Name (_DDN, "AKM AF DAC") /* _DDN: DOS Device Name */
+		External (CSTA, IntObj)
 
 		Method (_STA, 0, NotSerialized)
 		{
-			Return (0x0F)
+			Return (CSTA)
 		}
 
 		Name (_CRS, ResourceTemplate ()
@@ -140,10 +142,11 @@ Scope (\_SB.PCI0.I2C5)
 		Name (_HID, "INT3499")
 		Name (_UID, 1)
 		Name (_DDN, "M24C64S")  /* _DDN: DOS Device Name */
+		External (CSTA, IntObj)
 
 		Method (_STA, 0, NotSerialized)
 		{
-			Return (0x0F)
+			Return (CSTA)
 		}
 
 		Name (_CRS, ResourceTemplate ()

From f61ecfa1542d4b1692256a3229413167a0ab1b4b Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Mon, 1 Dec 2025 20:34:03 -0600
Subject: [PATCH 2784/3886] mb/google/link: Add CFR option menu support

Add CFR option menu support when using edk2 payload and SMMSTORE.
Include relevant items from Sandy/Ivybridge, C216 SB, and ChromeEC.

TEST=build/boot google/link, verify CFR option functionality.

Change-Id: I08cccf136f20018aee925372b5c181bf4b55e0cd
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90319
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/google/link/Kconfig     |  1 +
 src/mainboard/google/link/Makefile.mk |  2 ++
 src/mainboard/google/link/cfr.c       | 38 +++++++++++++++++++++++++++
 3 files changed, 41 insertions(+)
 create mode 100644 src/mainboard/google/link/cfr.c

diff --git a/src/mainboard/google/link/Kconfig b/src/mainboard/google/link/Kconfig
index 17c41bd8dd..86dd014f2a 100644
--- a/src/mainboard/google/link/Kconfig
+++ b/src/mainboard/google/link/Kconfig
@@ -7,6 +7,7 @@ config BOARD_SPECIFIC_OPTIONS
 	select AZALIA_USE_LEGACY_VERB_TABLE
 	select ACPI_GNVS_USB_CHARGECTL
 	select BOARD_ROMSIZE_KB_8192
+	select DRIVERS_OPTION_CFR_ENABLED if PAYLOAD_EDK2 && SMMSTORE
 	select EC_GOOGLE_CHROMEEC
 	select EC_GOOGLE_CHROMEEC_AUTO_FAN_CTRL
 	select EC_GOOGLE_CHROMEEC_LPC
diff --git a/src/mainboard/google/link/Makefile.mk b/src/mainboard/google/link/Makefile.mk
index 6b3f1b568c..c057bdc178 100644
--- a/src/mainboard/google/link/Makefile.mk
+++ b/src/mainboard/google/link/Makefile.mk
@@ -15,3 +15,5 @@ bootblock-y += gpio.c
 romstage-y += gpio.c
 bootblock-y += early_init.c
 romstage-y += early_init.c
+
+ramstage-$(CONFIG_DRIVERS_OPTION_CFR) += cfr.c
diff --git a/src/mainboard/google/link/cfr.c b/src/mainboard/google/link/cfr.c
new file mode 100644
index 0000000000..fb40c308d2
--- /dev/null
+++ b/src/mainboard/google/link/cfr.c
@@ -0,0 +1,38 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <boot/coreboot_tables.h>
+#include <drivers/option/cfr_frontend.h>
+#include <ec/google/chromeec/cfr.h>
+#include <northbridge/intel/sandybridge/cfr.h>
+#include <southbridge/intel/bd82x6x/cfr.h>
+
+static struct sm_obj_form system = {
+	.ui_name = "System",
+	.obj_list = (const struct sm_object *[]) {
+		&gfx_uma_size,
+		&me_state,
+		&me_state_prev,
+		&nmi,
+		&sata_mode,
+		NULL
+	},
+};
+
+static struct sm_obj_form ec = {
+	.ui_name = "ChromeEC Embedded Controller",
+	.obj_list = (const struct sm_object *[]) {
+		&auto_fan_control,
+		&ec_kb_backlight,
+		NULL
+	},
+};
+static struct sm_obj_form *sm_root[] = {
+	&system,
+	&ec,
+	NULL
+};
+
+void mb_cfr_setup_menu(struct lb_cfr *cfr_root)
+{
+	cfr_write_setup_menu(cfr_root, sm_root);
+}

From c36b14939298dff0623d7e1db88d35acffc217e9 Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Sun, 31 Aug 2025 17:29:13 -0500
Subject: [PATCH 2785/3886] mb/google/eve/Makefile: Organize and group entries
 by stage

Tidy up before adding a new CFR entry in a subsequent patch.

Change-Id: I14dc011622acad43b6a21a00d97a958ea6d3152f
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90320
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/google/eve/Makefile.mk | 12 ++++++------
 1 file changed, 6 insertions(+), 6 deletions(-)

diff --git a/src/mainboard/google/eve/Makefile.mk b/src/mainboard/google/eve/Makefile.mk
index fc6dc660f1..3ffd22009a 100644
--- a/src/mainboard/google/eve/Makefile.mk
+++ b/src/mainboard/google/eve/Makefile.mk
@@ -1,15 +1,15 @@
 ## SPDX-License-Identifier: GPL-2.0-only
 
-subdirs-y += spd
-
 bootblock-y += bootblock.c
-
 bootblock-$(CONFIG_CHROMEOS) += chromeos.c
+
 verstage-$(CONFIG_CHROMEOS) += chromeos.c
+
 romstage-$(CONFIG_CHROMEOS) += chromeos.c
+
 ramstage-$(CONFIG_CHROMEOS) += chromeos.c
-
-ramstage-y += mainboard.c
 ramstage-$(CONFIG_EC_GOOGLE_CHROMEEC) += ec.c
-
 ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads
+ramstage-y += mainboard.c
+
+subdirs-y += spd

From 72010408b5b65a2d038452c31a2a6001b34ee7c5 Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Mon, 1 Dec 2025 20:38:56 -0600
Subject: [PATCH 2786/3886] mb/google/eve: Add CFR option menu support

Add CFR option menu support when using edk2 payload and SMMSTORE.
Include relevant items from Kabylake SoC, Intel common, and ChromeEC.

TEST=build/boot google/eve, verify CFR option functionality.

Change-Id: Id878bbd06b7eb06f12c063486fd475c742a9a13b
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90321
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
---
 src/mainboard/google/eve/Kconfig     |  1 +
 src/mainboard/google/eve/Makefile.mk |  1 +
 src/mainboard/google/eve/cfr.c       | 45 ++++++++++++++++++++++++++++
 3 files changed, 47 insertions(+)
 create mode 100644 src/mainboard/google/eve/cfr.c

diff --git a/src/mainboard/google/eve/Kconfig b/src/mainboard/google/eve/Kconfig
index a415921fe5..40eebc5c50 100644
--- a/src/mainboard/google/eve/Kconfig
+++ b/src/mainboard/google/eve/Kconfig
@@ -9,6 +9,7 @@ config BOARD_SPECIFIC_OPTIONS
 	select DRIVERS_I2C_HID
 	select DRIVERS_I2C_MAX98927
 	select DRIVERS_I2C_RT5663
+	select DRIVERS_OPTION_CFR_ENABLED if PAYLOAD_EDK2 && SMMSTORE
 	select DRIVERS_SPI_ACPI
 	select DRIVERS_USB_ACPI
 	select EC_GOOGLE_CHROMEEC
diff --git a/src/mainboard/google/eve/Makefile.mk b/src/mainboard/google/eve/Makefile.mk
index 3ffd22009a..1ec948d231 100644
--- a/src/mainboard/google/eve/Makefile.mk
+++ b/src/mainboard/google/eve/Makefile.mk
@@ -7,6 +7,7 @@ verstage-$(CONFIG_CHROMEOS) += chromeos.c
 
 romstage-$(CONFIG_CHROMEOS) += chromeos.c
 
+ramstage-$(CONFIG_DRIVERS_OPTION_CFR) += cfr.c
 ramstage-$(CONFIG_CHROMEOS) += chromeos.c
 ramstage-$(CONFIG_EC_GOOGLE_CHROMEEC) += ec.c
 ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads
diff --git a/src/mainboard/google/eve/cfr.c b/src/mainboard/google/eve/cfr.c
new file mode 100644
index 0000000000..efddc4d7c8
--- /dev/null
+++ b/src/mainboard/google/eve/cfr.c
@@ -0,0 +1,45 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <boot/coreboot_tables.h>
+#include <drivers/option/cfr_frontend.h>
+#include <ec/google/chromeec/cfr.h>
+#include <intelblocks/cfr.h>
+#include <soc/cfr.h>
+
+static struct sm_obj_form system = {
+	.ui_name = "System",
+	.obj_list = (const struct sm_object *[]) {
+		&hyper_threading,
+		&igd_dvmt,
+		&igd_aperture,
+		&legacy_8254_timer,
+		&me_state,
+		&me_state_counter,
+		&pciexp_aspm,
+		&pciexp_clk_pm,
+		&pciexp_l1ss,
+		&pciexp_speed,
+		&s0ix_enable,
+		&vtd,
+		NULL
+	},
+};
+
+static struct sm_obj_form ec = {
+	.ui_name = "ChromeEC Embedded Controller",
+	.obj_list = (const struct sm_object *[]) {
+		&ec_kb_backlight,
+		NULL
+	},
+};
+
+static struct sm_obj_form *sm_root[] = {
+	&system,
+	&ec,
+	NULL
+};
+
+void mb_cfr_setup_menu(struct lb_cfr *cfr_root)
+{
+	cfr_write_setup_menu(cfr_root, sm_root);
+}

From 403a42f1f0c7b661fba0d920930d1918a48d8f0e Mon Sep 17 00:00:00 2001
From: Yu-Ping Wu <yupingso@chromium.org>
Date: Wed, 10 Dec 2025 17:58:33 +0800
Subject: [PATCH 2787/3886] soc/mediatek/mt8173: Fix mipi_tx1 address

The address of mipi_tx1 should be MIPI_TX1_BASE instead of
MIPI_TX0_BASE. This doesn't cause any issue in practice because mipi_tx1
is unused.

Also rename lvds_tx1/lvds_tx2 to lvds_tx0/lvds_tx1 for consistency with
the MIPI_TX0_BASE/MIPI_TX1_BASE naming.

BUG=none
TEST=none
BRANCH=none

Change-Id: I040b0a2a447333141cf6f4a012fa5d2aefd936c7
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90444
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Chen-Tsung Hsieh <chentsung@google.com>
---
 src/soc/mediatek/mt8173/dsi.c             | 6 +++---
 src/soc/mediatek/mt8173/include/soc/dsi.h | 6 +++---
 2 files changed, 6 insertions(+), 6 deletions(-)

diff --git a/src/soc/mediatek/mt8173/dsi.c b/src/soc/mediatek/mt8173/dsi.c
index c47634ef4e..3e87ba448a 100644
--- a/src/soc/mediatek/mt8173/dsi.c
+++ b/src/soc/mediatek/mt8173/dsi.c
@@ -118,7 +118,7 @@ void mtk_dsi_pin_drv_ctrl(void)
 	struct stopwatch sw;
 	uint32_t pwr_ack;
 
-	setbits32(&lvds_tx1->vopll_ctl3, RG_DA_LVDSTX_PWR_ON);
+	setbits32(&lvds_tx0->vopll_ctl3, RG_DA_LVDSTX_PWR_ON);
 
 	stopwatch_init_usecs_expire(&sw, 1000);
 
@@ -127,8 +127,8 @@ void mtk_dsi_pin_drv_ctrl(void)
 			printk(BIOS_ERR, "enable lvdstx_power failed!!!\n");
 			return;
 		}
-		pwr_ack = read32(&lvds_tx1->vopll_ctl3) & RG_AD_LVDSTX_PWR_ACK;
+		pwr_ack = read32(&lvds_tx0->vopll_ctl3) & RG_AD_LVDSTX_PWR_ACK;
 	} while (pwr_ack == 0);
 
-	clrbits32(&lvds_tx1->vopll_ctl3, RG_DA_LVDS_ISO_EN);
+	clrbits32(&lvds_tx0->vopll_ctl3, RG_DA_LVDS_ISO_EN);
 }
diff --git a/src/soc/mediatek/mt8173/include/soc/dsi.h b/src/soc/mediatek/mt8173/include/soc/dsi.h
index 22010c90a1..0255d4ca04 100644
--- a/src/soc/mediatek/mt8173/include/soc/dsi.h
+++ b/src/soc/mediatek/mt8173/include/soc/dsi.h
@@ -50,7 +50,7 @@ check_member(mipi_tx_regs, dsi_top_con, 0x40);
 check_member(mipi_tx_regs, dsi_pll_pwr, 0x68);
 
 static struct mipi_tx_regs *const mipi_tx0 = (void *)MIPI_TX0_BASE;
-static struct mipi_tx_regs *const mipi_tx1 = (void *)MIPI_TX0_BASE;
+static struct mipi_tx_regs *const mipi_tx1 = (void *)MIPI_TX1_BASE;
 
 /* MIPITX_DSI0_CON */
 enum {
@@ -144,8 +144,8 @@ struct lvds_tx1_regs {
 	u32 vopll_ctl3;
 };
 
-static struct lvds_tx1_regs *const lvds_tx1 = (void *)(MIPI_TX0_BASE + 0x800);
-static struct lvds_tx1_regs *const lvds_tx2 = (void *)(MIPI_TX1_BASE + 0x800);
+static struct lvds_tx1_regs *const lvds_tx0 = (void *)(MIPI_TX0_BASE + 0x800);
+static struct lvds_tx1_regs *const lvds_tx1 = (void *)(MIPI_TX1_BASE + 0x800);
 
 /* LVDS_VOPLL_CTRL3 */
 enum {

From cf0b91d774978e9c9b7b236b3ba001d0b0e0ebf9 Mon Sep 17 00:00:00 2001
From: Yu-Ping Wu <yupingso@chromium.org>
Date: Wed, 10 Dec 2025 18:13:03 +0800
Subject: [PATCH 2788/3886] soc/mediatek: Move dsi_regs/mipi_tx_regs
 definitions to soc/dsi_reg.h

In an upcoming change, a dsi_regs/mipi_tx_regs argument will be added to
functions declared in dsi_common.h. Currently those structs are all
defined in soc/dsi.h. However, dsi_common.h cannot include soc/dsi.h
because soc/dsi.h already includes dsi_common.h. To solve the circular
dependency issue, move the dsi_regs/mipi_tx_regs definitions to a new
file soc/dsi_reg.h.

As mt8183/mt8186/mt8188/mt8189/mt8192 all share compatible mipi_tx_regs
definitions, create a common mipi_tx_reg_v1.h and include it in these
SoCs' soc/mipi_tx_reg.h. The mt8173 remains its own struct definition.

Also, rename MIPITX_BASE to MIPITX0_BASE in soc/addressmap.h, to have
consistent naming across all SoCs. Note that MIPITX1_BASE will be added
for mt8196 in a future patch.

BUG=b:424782827
TEST=emerge-skywalker coreboot
BRANCH=none

Change-Id: I0e2159fde5bfc358691a4b3bdebc2657f0a598a8
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90445
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 .../common/include/soc/mipi_tx_reg_v1.h       |  53 ++++++++
 src/soc/mediatek/mt8173/include/soc/dsi.h     | 126 +-----------------
 src/soc/mediatek/mt8173/include/soc/dsi_reg.h | 126 ++++++++++++++++++
 .../mediatek/mt8183/include/soc/addressmap.h  |   2 +-
 src/soc/mediatek/mt8183/include/soc/dsi.h     |  48 +------
 src/soc/mediatek/mt8183/include/soc/dsi_reg.h |   9 ++
 .../mediatek/mt8186/include/soc/addressmap.h  |   2 +-
 src/soc/mediatek/mt8186/include/soc/dsi.h     |  48 +------
 src/soc/mediatek/mt8186/include/soc/dsi_reg.h |   9 ++
 .../mediatek/mt8188/include/soc/addressmap.h  |   2 +-
 src/soc/mediatek/mt8188/include/soc/dsi.h     |  48 +------
 src/soc/mediatek/mt8188/include/soc/dsi_reg.h |   9 ++
 src/soc/mediatek/mt8189/include/soc/dsi.h     |  54 +-------
 src/soc/mediatek/mt8189/include/soc/dsi_reg.h |   9 ++
 .../mediatek/mt8192/include/soc/addressmap.h  |   2 +-
 src/soc/mediatek/mt8192/include/soc/dsi.h     |  48 +------
 src/soc/mediatek/mt8192/include/soc/dsi_reg.h |   9 ++
 .../mediatek/mt8195/include/soc/addressmap.h  |   2 +-
 18 files changed, 253 insertions(+), 353 deletions(-)
 create mode 100644 src/soc/mediatek/common/include/soc/mipi_tx_reg_v1.h
 create mode 100644 src/soc/mediatek/mt8173/include/soc/dsi_reg.h
 create mode 100644 src/soc/mediatek/mt8183/include/soc/dsi_reg.h
 create mode 100644 src/soc/mediatek/mt8186/include/soc/dsi_reg.h
 create mode 100644 src/soc/mediatek/mt8188/include/soc/dsi_reg.h
 create mode 100644 src/soc/mediatek/mt8189/include/soc/dsi_reg.h
 create mode 100644 src/soc/mediatek/mt8192/include/soc/dsi_reg.h

diff --git a/src/soc/mediatek/common/include/soc/mipi_tx_reg_v1.h b/src/soc/mediatek/common/include/soc/mipi_tx_reg_v1.h
new file mode 100644
index 0000000000..6c1beca20a
--- /dev/null
+++ b/src/soc/mediatek/common/include/soc/mipi_tx_reg_v1.h
@@ -0,0 +1,53 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef _SOC_MEDIATEK_COMMON_MIPI_TX_REG_V1_H_
+#define _SOC_MEDIATEK_COMMON_MIPI_TX_REG_V1_H_
+
+#include <commonlib/bsd/helpers.h>
+#include <types.h>
+
+/* MIPITX_REG */
+struct mipi_tx_regs {
+	u32 reserved0[3];
+	u32 lane_con;
+	u32 voltage_sel;
+	u32 reserved1[5];
+	u32 pll_pwr;
+	u32 pll_con0;
+	u32 pll_con1;
+	u32 pll_con2;
+	u32 pll_con3;
+	u32 pll_con4;
+	u32 phy_sel[4];
+	u32 reserved2[61];
+	u32 d2_sw_ctl_en;
+	u32 reserved3[63];
+	u32 d0_sw_ctl_en;
+	u32 reserved4[56];
+	u32 ck_ckmode_en;
+	u32 reserved5[6];
+	u32 ck_sw_ctl_en;
+	u32 reserved6[63];
+	u32 d1_sw_ctl_en;
+	u32 reserved7[63];
+	u32 d3_sw_ctl_en;
+};
+
+check_member(mipi_tx_regs, voltage_sel, 0x10);
+check_member(mipi_tx_regs, pll_con4, 0x3C);
+check_member(mipi_tx_regs, phy_sel[0], 0x40);
+check_member(mipi_tx_regs, phy_sel[3], 0x4C);
+check_member(mipi_tx_regs, d3_sw_ctl_en, 0x544);
+
+static struct mipi_tx_regs *const mipi_tx = (void *)MIPITX0_BASE;
+
+/* Register values */
+#define DSI_CK_CKMODE_EN	BIT(0)
+#define DSI_SW_CTL_EN		BIT(0)
+#define AD_DSI_PLL_SDM_PWR_ON	BIT(0)
+#define AD_DSI_PLL_SDM_ISO_EN	BIT(1)
+
+#define RG_DSI_PLL_EN		BIT(4)
+#define RG_DSI_PLL_POSDIV	(0x7 << 8)
+
+#endif /* _SOC_MEDIATEK_COMMON_MIPI_TX_REG_V1_H_ */
diff --git a/src/soc/mediatek/mt8173/include/soc/dsi.h b/src/soc/mediatek/mt8173/include/soc/dsi.h
index 0255d4ca04..7747b14c33 100644
--- a/src/soc/mediatek/mt8173/include/soc/dsi.h
+++ b/src/soc/mediatek/mt8173/include/soc/dsi.h
@@ -1,10 +1,10 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
-#ifndef _DSI_REG_H_
-#define _DSI_REG_H_
+#ifndef _SOC_MEDIATEK_MT8173_DSI_H_
+#define _SOC_MEDIATEK_MT8173_DSI_H_
 
 #include <soc/dsi_common.h>
-#include <soc/dsi_register_v1.h>
+#include <soc/dsi_reg.h>
 #include <types.h>
 
 /* DSI features */
@@ -14,124 +14,6 @@
 #define MTK_DSI_HAVE_SIZE_CON 0
 #define PIXEL_STREAM_CUSTOM_HEADER 0
 
-/* MIPITX is SOC specific and cannot live in common. */
-
-/* MIPITX_REG */
-struct mipi_tx_regs {
-	u32 dsi_con;
-	u32 dsi_clock_lane;
-	u32 dsi_data_lane[4];
-	u8 reserved0[40];
-	u32 dsi_top_con;
-	u32 dsi_bg_con;
-	u8 reserved1[8];
-	u32 dsi_pll_con0;
-	u32 dsi_pll_con1;
-	u32 dsi_pll_con2;
-	u32 dsi_pll_con3;
-	u32 dsi_pll_chg;
-	u32 dsi_pll_top;
-	u32 dsi_pll_pwr;
-	u8 reserved2[4];
-	u32 dsi_rgs;
-	u32 dsi_gpi_en;
-	u32 dsi_gpi_pull;
-	u32 dsi_phy_sel;
-	u32 dsi_sw_ctrl_en;
-	u32 dsi_sw_ctrl_con0;
-	u32 dsi_sw_ctrl_con1;
-	u32 dsi_sw_ctrl_con2;
-	u32 dsi_dbg_con;
-	u32 dsi_dbg_out;
-	u32 dsi_apb_async_sta;
-};
-
-check_member(mipi_tx_regs, dsi_top_con, 0x40);
-check_member(mipi_tx_regs, dsi_pll_pwr, 0x68);
-
-static struct mipi_tx_regs *const mipi_tx0 = (void *)MIPI_TX0_BASE;
-static struct mipi_tx_regs *const mipi_tx1 = (void *)MIPI_TX1_BASE;
-
-/* MIPITX_DSI0_CON */
-enum {
-	RG_DSI0_LDOCORE_EN = BIT(0),
-	RG_DSI0_CKG_LDOOUT_EN = BIT(1),
-	RG_DSI0_BCLK_SEL = (3 << 2),
-	RG_DSI0_LD_IDX_SEL = (7 << 4),
-	RG_DSI0_PHYCLK_SEL = (2 << 8),
-	RG_DSI0_DSICLK_FREQ_SEL = BIT(10),
-	RG_DSI0_LPTX_CLMP_EN = BIT(11)
-};
-
-/* MIPITX_DSI0_CLOCK_LANE */
-enum {
-	LDOOUT_EN = BIT(0),
-	CKLANE_EN = BIT(1),
-	IPLUS1 = BIT(2),
-	LPTX_IPLUS2 = BIT(3),
-	LPTX_IMINUS = BIT(4),
-	LPCD_IPLUS = BIT(5),
-	LPCD_IMLUS = BIT(6),
-	RT_CODE = (0xf << 8)
-};
-
-/* MIPITX_DSI_TOP_CON */
-enum {
-	RG_DSI_LNT_INTR_EN = BIT(0),
-	RG_DSI_LNT_HS_BIAS_EN = BIT(1),
-	RG_DSI_LNT_IMP_CAL_EN = BIT(2),
-	RG_DSI_LNT_TESTMODE_EN = BIT(3),
-	RG_DSI_LNT_IMP_CAL_CODE = (0xf << 4),
-	RG_DSI_LNT_AIO_SEL = (7 << 8),
-	RG_DSI_PAD_TIE_LOW_EN = BIT(11),
-	RG_DSI_DEBUG_INPUT_EN = BIT(12),
-	RG_DSI_PRESERVE = (7 << 13)
-};
-
-/* MIPITX_DSI_BG_CON */
-enum {
-	RG_DSI_BG_CORE_EN = BIT(0),
-	RG_DSI_BG_CKEN = BIT(1),
-	RG_DSI_BG_DIV = (0x3 << 2),
-	RG_DSI_BG_FAST_CHARGE = BIT(4),
-	RG_DSI_V12_SEL = (7 << 5),
-	RG_DSI_V10_SEL = (7 << 8),
-	RG_DSI_V072_SEL = (7 << 11),
-	RG_DSI_V04_SEL = (7 << 14),
-	RG_DSI_V032_SEL = (7 << 17),
-	RG_DSI_V02_SEL = (7 << 20),
-	rsv_23 = BIT(23),
-	RG_DSI_BG_R1_TRIM = (0xf << 24),
-	RG_DSI_BG_R2_TRIM = (0xf << 28)
-};
-
-/* MIPITX_DSI_PLL_CON0 */
-enum {
-	RG_DSI0_MPPLL_PLL_EN = BIT(0),
-	RG_DSI0_MPPLL_PREDIV = (3 << 1),
-	RG_DSI0_MPPLL_TXDIV0 = (3 << 3),
-	RG_DSI0_MPPLL_TXDIV1 = (3 << 5),
-	RG_DSI0_MPPLL_POSDIV = (7 << 7),
-	RG_DSI0_MPPLL_MONVC_EN = BIT(10),
-	RG_DSI0_MPPLL_MONREF_EN = BIT(11),
-	RG_DSI0_MPPLL_VOD_EN = BIT(12)
-};
-
-/* MIPITX_DSI_PLL_CON1 */
-enum {
-	RG_DSI0_MPPLL_SDM_FRA_EN = BIT(0),
-	RG_DSI0_MPPLL_SDM_SSC_PH_INIT = BIT(1),
-	RG_DSI0_MPPLL_SDM_SSC_EN = BIT(2),
-	RG_DSI0_MPPLL_SDM_SSC_PRD = (0xffff << 16)
-};
-
-/* MIPITX_DSI_PLL_PWR */
-enum {
-	RG_DSI_MPPLL_SDM_PWR_ON = BIT(0),
-	RG_DSI_MPPLL_SDM_ISO_EN = BIT(1),
-	RG_DSI_MPPLL_SDM_PWR_ACK = BIT(8)
-};
-
 /* LVDS_TX1_REG */
 struct lvds_tx1_regs {
 	u32 lvdstx1_ctl1;
@@ -161,4 +43,4 @@ enum {
 /* SOC specific functions */
 void mtk_dsi_pin_drv_ctrl(void);
 
-#endif
+#endif /* _SOC_MEDIATEK_MT8173_DSI_H_ */
diff --git a/src/soc/mediatek/mt8173/include/soc/dsi_reg.h b/src/soc/mediatek/mt8173/include/soc/dsi_reg.h
new file mode 100644
index 0000000000..dfc6bdf515
--- /dev/null
+++ b/src/soc/mediatek/mt8173/include/soc/dsi_reg.h
@@ -0,0 +1,126 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef _SOC_MEDIATEK_MT8173_DSI_REG_H_
+#define _SOC_MEDIATEK_MT8173_DSI_REG_H_
+
+#include <soc/dsi_register_v1.h>
+
+/* MIPITX is SOC specific and cannot live in common. */
+
+/* MIPITX_REG */
+struct mipi_tx_regs {
+	u32 dsi_con;
+	u32 dsi_clock_lane;
+	u32 dsi_data_lane[4];
+	u8 reserved0[40];
+	u32 dsi_top_con;
+	u32 dsi_bg_con;
+	u8 reserved1[8];
+	u32 dsi_pll_con0;
+	u32 dsi_pll_con1;
+	u32 dsi_pll_con2;
+	u32 dsi_pll_con3;
+	u32 dsi_pll_chg;
+	u32 dsi_pll_top;
+	u32 dsi_pll_pwr;
+	u8 reserved2[4];
+	u32 dsi_rgs;
+	u32 dsi_gpi_en;
+	u32 dsi_gpi_pull;
+	u32 dsi_phy_sel;
+	u32 dsi_sw_ctrl_en;
+	u32 dsi_sw_ctrl_con0;
+	u32 dsi_sw_ctrl_con1;
+	u32 dsi_sw_ctrl_con2;
+	u32 dsi_dbg_con;
+	u32 dsi_dbg_out;
+	u32 dsi_apb_async_sta;
+};
+
+check_member(mipi_tx_regs, dsi_top_con, 0x40);
+check_member(mipi_tx_regs, dsi_pll_pwr, 0x68);
+
+static struct mipi_tx_regs *const mipi_tx0 = (void *)MIPI_TX0_BASE;
+static struct mipi_tx_regs *const mipi_tx1 = (void *)MIPI_TX1_BASE;
+
+/* MIPITX_DSI0_CON */
+enum {
+	RG_DSI0_LDOCORE_EN = BIT(0),
+	RG_DSI0_CKG_LDOOUT_EN = BIT(1),
+	RG_DSI0_BCLK_SEL = (3 << 2),
+	RG_DSI0_LD_IDX_SEL = (7 << 4),
+	RG_DSI0_PHYCLK_SEL = (2 << 8),
+	RG_DSI0_DSICLK_FREQ_SEL = BIT(10),
+	RG_DSI0_LPTX_CLMP_EN = BIT(11)
+};
+
+/* MIPITX_DSI0_CLOCK_LANE */
+enum {
+	LDOOUT_EN = BIT(0),
+	CKLANE_EN = BIT(1),
+	IPLUS1 = BIT(2),
+	LPTX_IPLUS2 = BIT(3),
+	LPTX_IMINUS = BIT(4),
+	LPCD_IPLUS = BIT(5),
+	LPCD_IMLUS = BIT(6),
+	RT_CODE = (0xf << 8)
+};
+
+/* MIPITX_DSI_TOP_CON */
+enum {
+	RG_DSI_LNT_INTR_EN = BIT(0),
+	RG_DSI_LNT_HS_BIAS_EN = BIT(1),
+	RG_DSI_LNT_IMP_CAL_EN = BIT(2),
+	RG_DSI_LNT_TESTMODE_EN = BIT(3),
+	RG_DSI_LNT_IMP_CAL_CODE = (0xf << 4),
+	RG_DSI_LNT_AIO_SEL = (7 << 8),
+	RG_DSI_PAD_TIE_LOW_EN = BIT(11),
+	RG_DSI_DEBUG_INPUT_EN = BIT(12),
+	RG_DSI_PRESERVE = (7 << 13)
+};
+
+/* MIPITX_DSI_BG_CON */
+enum {
+	RG_DSI_BG_CORE_EN = BIT(0),
+	RG_DSI_BG_CKEN = BIT(1),
+	RG_DSI_BG_DIV = (0x3 << 2),
+	RG_DSI_BG_FAST_CHARGE = BIT(4),
+	RG_DSI_V12_SEL = (7 << 5),
+	RG_DSI_V10_SEL = (7 << 8),
+	RG_DSI_V072_SEL = (7 << 11),
+	RG_DSI_V04_SEL = (7 << 14),
+	RG_DSI_V032_SEL = (7 << 17),
+	RG_DSI_V02_SEL = (7 << 20),
+	rsv_23 = BIT(23),
+	RG_DSI_BG_R1_TRIM = (0xf << 24),
+	RG_DSI_BG_R2_TRIM = (0xf << 28)
+};
+
+/* MIPITX_DSI_PLL_CON0 */
+enum {
+	RG_DSI0_MPPLL_PLL_EN = BIT(0),
+	RG_DSI0_MPPLL_PREDIV = (3 << 1),
+	RG_DSI0_MPPLL_TXDIV0 = (3 << 3),
+	RG_DSI0_MPPLL_TXDIV1 = (3 << 5),
+	RG_DSI0_MPPLL_POSDIV = (7 << 7),
+	RG_DSI0_MPPLL_MONVC_EN = BIT(10),
+	RG_DSI0_MPPLL_MONREF_EN = BIT(11),
+	RG_DSI0_MPPLL_VOD_EN = BIT(12)
+};
+
+/* MIPITX_DSI_PLL_CON1 */
+enum {
+	RG_DSI0_MPPLL_SDM_FRA_EN = BIT(0),
+	RG_DSI0_MPPLL_SDM_SSC_PH_INIT = BIT(1),
+	RG_DSI0_MPPLL_SDM_SSC_EN = BIT(2),
+	RG_DSI0_MPPLL_SDM_SSC_PRD = (0xffff << 16)
+};
+
+/* MIPITX_DSI_PLL_PWR */
+enum {
+	RG_DSI_MPPLL_SDM_PWR_ON = BIT(0),
+	RG_DSI_MPPLL_SDM_ISO_EN = BIT(1),
+	RG_DSI_MPPLL_SDM_PWR_ACK = BIT(8)
+};
+
+#endif /* _SOC_MEDIATEK_MT8173_DSI_REG_H_ */
diff --git a/src/soc/mediatek/mt8183/include/soc/addressmap.h b/src/soc/mediatek/mt8183/include/soc/addressmap.h
index ad8b5a085b..c579b1a38b 100644
--- a/src/soc/mediatek/mt8183/include/soc/addressmap.h
+++ b/src/soc/mediatek/mt8183/include/soc/addressmap.h
@@ -38,7 +38,7 @@ enum {
 	IOCFG_RT_BASE		= IO_PHYS + 0x01C50000,
 	IOCFG_RM_BASE		= IO_PHYS + 0x01D20000,
 	IOCFG_RB_BASE		= IO_PHYS + 0x01D30000,
-	MIPITX_BASE             = IO_PHYS + 0x01E50000,
+	MIPITX0_BASE		= IO_PHYS + 0x01E50000,
 	IOCFG_LB_BASE		= IO_PHYS + 0x01E70000,
 	IOCFG_LM_BASE		= IO_PHYS + 0x01E80000,
 	IOCFG_BL_BASE		= IO_PHYS + 0x01E90000,
diff --git a/src/soc/mediatek/mt8183/include/soc/dsi.h b/src/soc/mediatek/mt8183/include/soc/dsi.h
index 3fcc281b2d..c1737f3c7f 100644
--- a/src/soc/mediatek/mt8183/include/soc/dsi.h
+++ b/src/soc/mediatek/mt8183/include/soc/dsi.h
@@ -1,10 +1,10 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
-#ifndef SOC_MEDIATEK_MT8183_DSI_H
-#define SOC_MEDIATEK_MT8183_DSI_H
+#ifndef _SOC_MEDIATEK_MT8183_DSI_H_
+#define _SOC_MEDIATEK_MT8183_DSI_H_
 
 #include <soc/dsi_common.h>
-#include <soc/dsi_register_v1.h>
+#include <soc/dsi_reg.h>
 #include <types.h>
 
 /* DSI features */
@@ -14,44 +14,4 @@
 #define MTK_DSI_HAVE_SIZE_CON 1
 #define PIXEL_STREAM_CUSTOM_HEADER 0xb
 
-/* MIPITX is SOC specific and cannot live in common. */
-
-/* MIPITX_REG */
-struct mipi_tx_regs {
-	u32 reserved0[3];
-	u32 lane_con;
-	u32 reserved1[6];
-	u32 pll_pwr;
-	u32 pll_con0;
-	u32 pll_con1;
-	u32 pll_con2;
-	u32 pll_con3;
-	u32 pll_con4;
-	u32 reserved2[65];
-	u32 d2_sw_ctl_en;
-	u32 reserved3[63];
-	u32 d0_sw_ctl_en;
-	u32 reserved4[56];
-	u32 ck_ckmode_en;
-	u32 reserved5[6];
-	u32 ck_sw_ctl_en;
-	u32 reserved6[63];
-	u32 d1_sw_ctl_en;
-	u32 reserved7[63];
-	u32 d3_sw_ctl_en;
-};
-
-check_member(mipi_tx_regs, pll_con4, 0x3c);
-check_member(mipi_tx_regs, d3_sw_ctl_en, 0x544);
-static struct mipi_tx_regs *const mipi_tx = (void *)MIPITX_BASE;
-
-/* Register values */
-#define DSI_CK_CKMODE_EN	BIT(0)
-#define DSI_SW_CTL_EN		BIT(0)
-#define AD_DSI_PLL_SDM_PWR_ON	BIT(0)
-#define AD_DSI_PLL_SDM_ISO_EN	BIT(1)
-
-#define RG_DSI_PLL_EN		BIT(4)
-#define RG_DSI_PLL_POSDIV	(0x7 << 8)
-
-#endif
+#endif /* _SOC_MEDIATEK_MT8183_DSI_H_ */
diff --git a/src/soc/mediatek/mt8183/include/soc/dsi_reg.h b/src/soc/mediatek/mt8183/include/soc/dsi_reg.h
new file mode 100644
index 0000000000..13a64aa004
--- /dev/null
+++ b/src/soc/mediatek/mt8183/include/soc/dsi_reg.h
@@ -0,0 +1,9 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef _SOC_MEDIATEK_MT8183_DSI_REG_H_
+#define _SOC_MEDIATEK_MT8183_DSI_REG_H_
+
+#include <soc/dsi_register_v1.h>
+#include <soc/mipi_tx_reg_v1.h>
+
+#endif /* _SOC_MEDIATEK_MT8183_DSI_REG_H_ */
diff --git a/src/soc/mediatek/mt8186/include/soc/addressmap.h b/src/soc/mediatek/mt8186/include/soc/addressmap.h
index 64500aaad0..c042022aca 100644
--- a/src/soc/mediatek/mt8186/include/soc/addressmap.h
+++ b/src/soc/mediatek/mt8186/include/soc/addressmap.h
@@ -84,7 +84,7 @@ enum {
 	SSUSB_SIF_BASE			= IO_PHYS + 0x01C80300,
 	SSUSB_SIF_BASE_P0		= IO_PHYS + 0x01CA0300,
 	EFUSEC_BASE			= IO_PHYS + 0x01CB0000,
-	MIPITX_BASE			= IO_PHYS + 0x01CC0000,
+	MIPITX0_BASE			= IO_PHYS + 0x01CC0000,
 	MSDC0_TOP_BASE			= IO_PHYS + 0x01CD0000,
 	MMSYS_BASE			= IO_PHYS + 0x04000000,
 	DISP_MUTEX_BASE			= IO_PHYS + 0x04001000,
diff --git a/src/soc/mediatek/mt8186/include/soc/dsi.h b/src/soc/mediatek/mt8186/include/soc/dsi.h
index 1a7c2f992e..181965d72f 100644
--- a/src/soc/mediatek/mt8186/include/soc/dsi.h
+++ b/src/soc/mediatek/mt8186/include/soc/dsi.h
@@ -5,11 +5,11 @@
  * Chapter number: 6.9
  */
 
-#ifndef SOC_MEDIATEK_MT8186_DSI_H
-#define SOC_MEDIATEK_MT8186_DSI_H
+#ifndef _SOC_MEDIATEK_MT8186_DSI_H_
+#define _SOC_MEDIATEK_MT8186_DSI_H_
 
 #include <soc/dsi_common.h>
-#include <soc/dsi_register_v2.h>
+#include <soc/dsi_reg.h>
 
 /* DSI features */
 #define MTK_DSI_MIPI_RATIO_NUMERATOR 100
@@ -18,44 +18,4 @@
 #define MTK_DSI_HAVE_SIZE_CON 1
 #define PIXEL_STREAM_CUSTOM_HEADER 0xb
 
-/* MIPITX is SOC specific and cannot live in common. */
-
-/* MIPITX_REG */
-struct mipi_tx_regs {
-	u32 reserved0[3];
-	u32 lane_con;
-	u32 reserved1[6];
-	u32 pll_pwr;
-	u32 pll_con0;
-	u32 pll_con1;
-	u32 pll_con2;
-	u32 pll_con3;
-	u32 pll_con4;
-	u32 reserved2[65];
-	u32 d2_sw_ctl_en;
-	u32 reserved3[63];
-	u32 d0_sw_ctl_en;
-	u32 reserved4[56];
-	u32 ck_ckmode_en;
-	u32 reserved5[6];
-	u32 ck_sw_ctl_en;
-	u32 reserved6[63];
-	u32 d1_sw_ctl_en;
-	u32 reserved7[63];
-	u32 d3_sw_ctl_en;
-};
-
-check_member(mipi_tx_regs, pll_con4, 0x3c);
-check_member(mipi_tx_regs, d3_sw_ctl_en, 0x544);
-static struct mipi_tx_regs *const mipi_tx = (void *)MIPITX_BASE;
-
-/* Register values */
-#define DSI_CK_CKMODE_EN	BIT(0)
-#define DSI_SW_CTL_EN		BIT(0)
-#define AD_DSI_PLL_SDM_PWR_ON	BIT(0)
-#define AD_DSI_PLL_SDM_ISO_EN	BIT(1)
-
-#define RG_DSI_PLL_EN		BIT(4)
-#define RG_DSI_PLL_POSDIV	(0x7 << 8)
-
-#endif
+#endif /* _SOC_MEDIATEK_MT8186_DSI_H_ */
diff --git a/src/soc/mediatek/mt8186/include/soc/dsi_reg.h b/src/soc/mediatek/mt8186/include/soc/dsi_reg.h
new file mode 100644
index 0000000000..507cd3bdf8
--- /dev/null
+++ b/src/soc/mediatek/mt8186/include/soc/dsi_reg.h
@@ -0,0 +1,9 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef _SOC_MEDIATEK_MT8186_DSI_REG_H_
+#define _SOC_MEDIATEK_MT8186_DSI_REG_H_
+
+#include <soc/dsi_register_v2.h>
+#include <soc/mipi_tx_reg_v1.h>
+
+#endif /* _SOC_MEDIATEK_MT8186_DSI_REG_H_ */
diff --git a/src/soc/mediatek/mt8188/include/soc/addressmap.h b/src/soc/mediatek/mt8188/include/soc/addressmap.h
index b942a85d5d..0fbbf55b39 100644
--- a/src/soc/mediatek/mt8188/include/soc/addressmap.h
+++ b/src/soc/mediatek/mt8188/include/soc/addressmap.h
@@ -88,7 +88,7 @@ enum {
 	I2C3_BASE		= IO_PHYS + 0x01282000,
 	SFLASH_REG_BASE		= IO_PHYS + 0x0132C000,
 	IOCFG_RM_BASE		= IO_PHYS + 0x01C00000,
-	MIPITX_BASE		= IO_PHYS + 0x01C80000,
+	MIPITX0_BASE		= IO_PHYS + 0x01C80000,
 	I2C1_BASE		= IO_PHYS + 0x01E00000,
 	I2C4_BASE		= IO_PHYS + 0x01E01000,
 	IOCFG_LT_BASE		= IO_PHYS + 0x01E10000,
diff --git a/src/soc/mediatek/mt8188/include/soc/dsi.h b/src/soc/mediatek/mt8188/include/soc/dsi.h
index 1a4eab43f6..b149df6290 100644
--- a/src/soc/mediatek/mt8188/include/soc/dsi.h
+++ b/src/soc/mediatek/mt8188/include/soc/dsi.h
@@ -1,10 +1,10 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
-#ifndef SOC_MEDIATEK_MT8188_DSI_H
-#define SOC_MEDIATEK_MT8188_DSI_H
+#ifndef _SOC_MEDIATEK_MT8188_DSI_H_
+#define _SOC_MEDIATEK_MT8188_DSI_H_
 
 #include <soc/dsi_common.h>
-#include <soc/dsi_register_v2.h>
+#include <soc/dsi_reg.h>
 
 /* DSI features */
 #define MTK_DSI_MIPI_RATIO_NUMERATOR	100
@@ -13,44 +13,4 @@
 #define MTK_DSI_HAVE_SIZE_CON		1
 #define PIXEL_STREAM_CUSTOM_HEADER	0xb
 
-/* MIPITX is SOC specific and cannot live in common. */
-
-/* MIPITX_REG */
-struct mipi_tx_regs {
-	u32 reserved0[3];
-	u32 lane_con;
-	u32 reserved1[6];
-	u32 pll_pwr;
-	u32 pll_con0;
-	u32 pll_con1;
-	u32 pll_con2;
-	u32 pll_con3;
-	u32 pll_con4;
-	u32 reserved2[65];
-	u32 d2_sw_ctl_en;
-	u32 reserved3[63];
-	u32 d0_sw_ctl_en;
-	u32 reserved4[56];
-	u32 ck_ckmode_en;
-	u32 reserved5[6];
-	u32 ck_sw_ctl_en;
-	u32 reserved6[63];
-	u32 d1_sw_ctl_en;
-	u32 reserved7[63];
-	u32 d3_sw_ctl_en;
-};
-
-check_member(mipi_tx_regs, pll_con4, 0x3c);
-check_member(mipi_tx_regs, d3_sw_ctl_en, 0x544);
-static struct mipi_tx_regs *const mipi_tx = (void *)MIPITX_BASE;
-
-/* Register values */
-#define DSI_CK_CKMODE_EN	BIT(0)
-#define DSI_SW_CTL_EN		BIT(0)
-#define AD_DSI_PLL_SDM_PWR_ON	BIT(0)
-#define AD_DSI_PLL_SDM_ISO_EN	BIT(1)
-
-#define RG_DSI_PLL_EN		BIT(4)
-#define RG_DSI_PLL_POSDIV	(0x7 << 8)
-
-#endif
+#endif /* _SOC_MEDIATEK_MT8188_DSI_H_ */
diff --git a/src/soc/mediatek/mt8188/include/soc/dsi_reg.h b/src/soc/mediatek/mt8188/include/soc/dsi_reg.h
new file mode 100644
index 0000000000..372d0ef04b
--- /dev/null
+++ b/src/soc/mediatek/mt8188/include/soc/dsi_reg.h
@@ -0,0 +1,9 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef _SOC_MEDIATEK_MT8188_DSI_REG_H_
+#define _SOC_MEDIATEK_MT8188_DSI_REG_H_
+
+#include <soc/dsi_register_v2.h>
+#include <soc/mipi_tx_reg_v1.h>
+
+#endif /* _SOC_MEDIATEK_MT8188_DSI_REG_H_ */
diff --git a/src/soc/mediatek/mt8189/include/soc/dsi.h b/src/soc/mediatek/mt8189/include/soc/dsi.h
index ad3a04d721..4194005898 100644
--- a/src/soc/mediatek/mt8189/include/soc/dsi.h
+++ b/src/soc/mediatek/mt8189/include/soc/dsi.h
@@ -1,11 +1,10 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
-#ifndef SOC_MEDIATEK_MT8189_DSI_H
-#define SOC_MEDIATEK_MT8189_DSI_H
+#ifndef _SOC_MEDIATEK_MT8189_DSI_H_
+#define _SOC_MEDIATEK_MT8189_DSI_H_
 
 #include <soc/dsi_common.h>
-#include <soc/dsi_register_v2.h>
-#include <types.h>
+#include <soc/dsi_reg.h>
 
 /* DSI features */
 #define MTK_DSI_MIPI_RATIO_NUMERATOR 100
@@ -14,49 +13,4 @@
 #define MTK_DSI_HAVE_SIZE_CON 1
 #define PIXEL_STREAM_CUSTOM_HEADER 0xb
 
-/* MIPITX is SOC specific and cannot live in common. */
-
-/* MIPITX_REG */
-struct mipi_tx_regs {
-	u32 reserved0[3];
-	u32 lane_con;
-	u32 voltage_sel;
-	u32 reserved1[5];
-	u32 pll_pwr;
-	u32 pll_con0;
-	u32 pll_con1;
-	u32 pll_con2;
-	u32 pll_con3;
-	u32 pll_con4;
-	u32 phy_sel[4];
-	u32 reserved2[61];
-	u32 d2_sw_ctl_en;
-	u32 reserved3[63];
-	u32 d0_sw_ctl_en;
-	u32 reserved4[56];
-	u32 ck_ckmode_en;
-	u32 reserved5[6];
-	u32 ck_sw_ctl_en;
-	u32 reserved6[63];
-	u32 d1_sw_ctl_en;
-	u32 reserved7[63];
-	u32 d3_sw_ctl_en;
-};
-
-check_member(mipi_tx_regs, voltage_sel, 0x10);
-check_member(mipi_tx_regs, pll_con4, 0x3C);
-check_member(mipi_tx_regs, phy_sel[0], 0x40);
-check_member(mipi_tx_regs, phy_sel[3], 0x4C);
-check_member(mipi_tx_regs, d3_sw_ctl_en, 0x544);
-static struct mipi_tx_regs *const mipi_tx = (void *)MIPITX0_BASE;
-
-/* Register values */
-#define DSI_CK_CKMODE_EN	BIT(0)
-#define DSI_SW_CTL_EN		BIT(0)
-#define AD_DSI_PLL_SDM_PWR_ON	BIT(0)
-#define AD_DSI_PLL_SDM_ISO_EN	BIT(1)
-
-#define RG_DSI_PLL_EN		BIT(4)
-#define RG_DSI_PLL_POSDIV	(0x7 << 8)
-
-#endif
+#endif /* _SOC_MEDIATEK_MT8189_DSI_H_ */
diff --git a/src/soc/mediatek/mt8189/include/soc/dsi_reg.h b/src/soc/mediatek/mt8189/include/soc/dsi_reg.h
new file mode 100644
index 0000000000..475aea4361
--- /dev/null
+++ b/src/soc/mediatek/mt8189/include/soc/dsi_reg.h
@@ -0,0 +1,9 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef _SOC_MEDIATEK_MT8189_DSI_REG_H_
+#define _SOC_MEDIATEK_MT8189_DSI_REG_H_
+
+#include <soc/dsi_register_v2.h>
+#include <soc/mipi_tx_reg_v1.h>
+
+#endif /* _SOC_MEDIATEK_MT8189_DSI_REG_H_ */
diff --git a/src/soc/mediatek/mt8192/include/soc/addressmap.h b/src/soc/mediatek/mt8192/include/soc/addressmap.h
index 440f7ca3c9..d70dc6f6a5 100644
--- a/src/soc/mediatek/mt8192/include/soc/addressmap.h
+++ b/src/soc/mediatek/mt8192/include/soc/addressmap.h
@@ -70,7 +70,7 @@ enum {
 	IOCFG_BR_BASE		= IO_PHYS + 0x01D40000,
 	IOCFG_LM_BASE		= IO_PHYS + 0x01E20000,
 	SSUSB_SIF_BASE		= IO_PHYS + 0x01E40300,
-	MIPITX_BASE		= IO_PHYS + 0x01E50000,
+	MIPITX0_BASE		= IO_PHYS + 0x01E50000,
 	IOCFG_LB_BASE		= IO_PHYS + 0x01E70000,
 	IOCFG_RT_BASE		= IO_PHYS + 0x01EA0000,
 	IOCFG_LT_BASE		= IO_PHYS + 0x01F20000,
diff --git a/src/soc/mediatek/mt8192/include/soc/dsi.h b/src/soc/mediatek/mt8192/include/soc/dsi.h
index 9ce55faba6..495233f285 100644
--- a/src/soc/mediatek/mt8192/include/soc/dsi.h
+++ b/src/soc/mediatek/mt8192/include/soc/dsi.h
@@ -1,10 +1,10 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
-#ifndef SOC_MEDIATEK_MT8192_DSI_H
-#define SOC_MEDIATEK_MT8192_DSI_H
+#ifndef _SOC_MEDIATEK_MT8192_DSI_H_
+#define _SOC_MEDIATEK_MT8192_DSI_H_
 
 #include <soc/dsi_common.h>
-#include <soc/dsi_register_v1.h>
+#include <soc/dsi_reg.h>
 
 /* DSI features */
 #define MTK_DSI_MIPI_RATIO_NUMERATOR 100
@@ -13,44 +13,4 @@
 #define MTK_DSI_HAVE_SIZE_CON 1
 #define PIXEL_STREAM_CUSTOM_HEADER 0xb
 
-/* MIPITX is SOC specific and cannot live in common. */
-
-/* MIPITX_REG */
-struct mipi_tx_regs {
-	u32 reserved0[3];
-	u32 lane_con;
-	u32 reserved1[6];
-	u32 pll_pwr;
-	u32 pll_con0;
-	u32 pll_con1;
-	u32 pll_con2;
-	u32 pll_con3;
-	u32 pll_con4;
-	u32 reserved2[65];
-	u32 d2_sw_ctl_en;
-	u32 reserved3[63];
-	u32 d0_sw_ctl_en;
-	u32 reserved4[56];
-	u32 ck_ckmode_en;
-	u32 reserved5[6];
-	u32 ck_sw_ctl_en;
-	u32 reserved6[63];
-	u32 d1_sw_ctl_en;
-	u32 reserved7[63];
-	u32 d3_sw_ctl_en;
-};
-
-check_member(mipi_tx_regs, pll_con4, 0x3c);
-check_member(mipi_tx_regs, d3_sw_ctl_en, 0x544);
-static struct mipi_tx_regs *const mipi_tx = (void *)MIPITX_BASE;
-
-/* Register values */
-#define DSI_CK_CKMODE_EN	BIT(0)
-#define DSI_SW_CTL_EN		BIT(0)
-#define AD_DSI_PLL_SDM_PWR_ON	BIT(0)
-#define AD_DSI_PLL_SDM_ISO_EN	BIT(1)
-
-#define RG_DSI_PLL_EN		BIT(4)
-#define RG_DSI_PLL_POSDIV	(0x7 << 8)
-
-#endif
+#endif /* _SOC_MEDIATEK_MT8192_DSI_H_ */
diff --git a/src/soc/mediatek/mt8192/include/soc/dsi_reg.h b/src/soc/mediatek/mt8192/include/soc/dsi_reg.h
new file mode 100644
index 0000000000..10991c1cbf
--- /dev/null
+++ b/src/soc/mediatek/mt8192/include/soc/dsi_reg.h
@@ -0,0 +1,9 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef _SOC_MEDIATEK_MT8192_DSI_REG_H_
+#define _SOC_MEDIATEK_MT8192_DSI_REG_H_
+
+#include <soc/dsi_register_v1.h>
+#include <soc/mipi_tx_reg_v1.h>
+
+#endif /* _SOC_MEDIATEK_MT8192_DSI_REG_H_ */
diff --git a/src/soc/mediatek/mt8195/include/soc/addressmap.h b/src/soc/mediatek/mt8195/include/soc/addressmap.h
index 0edb44c1c2..4e51e588e2 100644
--- a/src/soc/mediatek/mt8195/include/soc/addressmap.h
+++ b/src/soc/mediatek/mt8195/include/soc/addressmap.h
@@ -72,7 +72,7 @@ enum {
 	UFSHCI_BASE		= IO_PHYS + 0x01270000,
 	SFLASH_REG_BASE		= IO_PHYS + 0x0132C000,
 	EFUSEC_BASE		= IO_PHYS + 0x01C10000,
-	MIPITX_BASE		= IO_PHYS + 0x01C80000,
+	MIPITX0_BASE		= IO_PHYS + 0x01C80000,
 	IOCFG_BM_BASE		= IO_PHYS + 0x01D10000,
 	IOCFG_BL_BASE		= IO_PHYS + 0x01D30000,
 	IOCFG_BR_BASE		= IO_PHYS + 0x01D40000,

From 7ef424c75e707914bd1f34ac6c2febba24ea3638 Mon Sep 17 00:00:00 2001
From: Yu-Ping Wu <yupingso@chromium.org>
Date: Wed, 10 Dec 2025 23:48:11 +0800
Subject: [PATCH 2789/3886] soc/mediatek/common: Rename mipi_tx to mipi_tx0

In preparation for the upcoming DSI dual channel support, where mipi_tx1
will be added, rename mipi_tx to mipi_tx0.

BUG=b:424782827
TEST=emerge-skywalker coreboot
BRANCH=none

Change-Id: Idcbcc9e71bd3657f543d97b70bf875af907da328
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90448
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Chen-Tsung Hsieh <chentsung@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/soc/mediatek/common/dsi_v1.c              | 26 +++++++++----------
 .../common/include/soc/mipi_tx_reg_v1.h       |  2 +-
 src/soc/mediatek/common/mtk_mipi_cphy.c       | 16 ++++++------
 src/soc/mediatek/common/mtk_mipi_dphy.c       |  2 +-
 4 files changed, 23 insertions(+), 23 deletions(-)

diff --git a/src/soc/mediatek/common/dsi_v1.c b/src/soc/mediatek/common/dsi_v1.c
index 6177bc35ad..030f034052 100644
--- a/src/soc/mediatek/common/dsi_v1.c
+++ b/src/soc/mediatek/common/dsi_v1.c
@@ -30,34 +30,34 @@ void mtk_dsi_configure_mipi_tx(u32 data_rate, u32 lanes, bool is_cphy)
 	if (CONFIG(MEDIATEK_DSI_CPHY) && is_cphy)
 		mtk_dsi_cphy_lane_sel_setting();
 
-	clrbits32(&mipi_tx->pll_con4, BIT(11) | BIT(10));
-	setbits32(&mipi_tx->pll_pwr, AD_DSI_PLL_SDM_PWR_ON);
+	clrbits32(&mipi_tx0->pll_con4, BIT(11) | BIT(10));
+	setbits32(&mipi_tx0->pll_pwr, AD_DSI_PLL_SDM_PWR_ON);
 	udelay(30);
-	clrbits32(&mipi_tx->pll_pwr, AD_DSI_PLL_SDM_ISO_EN);
+	clrbits32(&mipi_tx0->pll_pwr, AD_DSI_PLL_SDM_ISO_EN);
 
 	pcw = (u64)data_rate * (1 << txdiv0);
 	pcw <<= 24;
 	pcw /= CLK26M_HZ;
 
-	write32(&mipi_tx->pll_con0, pcw);
-	clrsetbits32(&mipi_tx->pll_con1, RG_DSI_PLL_POSDIV, txdiv0 << 8);
+	write32(&mipi_tx0->pll_con0, pcw);
+	clrsetbits32(&mipi_tx0->pll_con1, RG_DSI_PLL_POSDIV, txdiv0 << 8);
 	udelay(30);
-	setbits32(&mipi_tx->pll_con1, RG_DSI_PLL_EN);
+	setbits32(&mipi_tx0->pll_con1, RG_DSI_PLL_EN);
 
 	/* BG_LPF_EN / BG_CORE_EN */
-	write32(&mipi_tx->lane_con, 0x3FFF0180);
+	write32(&mipi_tx0->lane_con, 0x3FFF0180);
 	udelay(40);
-	write32(&mipi_tx->lane_con, 0x3FFF00C0);
+	write32(&mipi_tx0->lane_con, 0x3FFF00C0);
 
 	if (CONFIG(MEDIATEK_DSI_CPHY) && is_cphy)
 		mtk_dsi_cphy_enable();
 
 	/* Switch OFF each Lane */
-	clrbits32(&mipi_tx->d0_sw_ctl_en, DSI_SW_CTL_EN);
-	clrbits32(&mipi_tx->d1_sw_ctl_en, DSI_SW_CTL_EN);
-	clrbits32(&mipi_tx->d2_sw_ctl_en, DSI_SW_CTL_EN);
-	clrbits32(&mipi_tx->d3_sw_ctl_en, DSI_SW_CTL_EN);
-	clrbits32(&mipi_tx->ck_sw_ctl_en, DSI_SW_CTL_EN);
+	clrbits32(&mipi_tx0->d0_sw_ctl_en, DSI_SW_CTL_EN);
+	clrbits32(&mipi_tx0->d1_sw_ctl_en, DSI_SW_CTL_EN);
+	clrbits32(&mipi_tx0->d2_sw_ctl_en, DSI_SW_CTL_EN);
+	clrbits32(&mipi_tx0->d3_sw_ctl_en, DSI_SW_CTL_EN);
+	clrbits32(&mipi_tx0->ck_sw_ctl_en, DSI_SW_CTL_EN);
 
 	if (CONFIG(MEDIATEK_DSI_CPHY) && is_cphy)
 		mtk_dsi_cphy_disable_ck_mode();
diff --git a/src/soc/mediatek/common/include/soc/mipi_tx_reg_v1.h b/src/soc/mediatek/common/include/soc/mipi_tx_reg_v1.h
index 6c1beca20a..2957201e0d 100644
--- a/src/soc/mediatek/common/include/soc/mipi_tx_reg_v1.h
+++ b/src/soc/mediatek/common/include/soc/mipi_tx_reg_v1.h
@@ -39,7 +39,7 @@ check_member(mipi_tx_regs, phy_sel[0], 0x40);
 check_member(mipi_tx_regs, phy_sel[3], 0x4C);
 check_member(mipi_tx_regs, d3_sw_ctl_en, 0x544);
 
-static struct mipi_tx_regs *const mipi_tx = (void *)MIPITX0_BASE;
+static struct mipi_tx_regs *const mipi_tx0 = (void *)MIPITX0_BASE;
 
 /* Register values */
 #define DSI_CK_CKMODE_EN	BIT(0)
diff --git a/src/soc/mediatek/common/mtk_mipi_cphy.c b/src/soc/mediatek/common/mtk_mipi_cphy.c
index 9ff62240fc..8578d84e4e 100644
--- a/src/soc/mediatek/common/mtk_mipi_cphy.c
+++ b/src/soc/mediatek/common/mtk_mipi_cphy.c
@@ -19,22 +19,22 @@
 
 void mtk_dsi_cphy_lane_sel_setting(void)
 {
-	write32(&mipi_tx->phy_sel[0], MIPITX_CPHY_LANE_SEL0_SETTING);
-	write32(&mipi_tx->phy_sel[1], MIPITX_CPHY_LANE_SEL1_SETTING);
-	write32(&mipi_tx->phy_sel[2], MIPITX_CPHY_LANE_SEL2_SETTING);
-	write32(&mipi_tx->phy_sel[3], MIPITX_CPHY_LANE_SEL3_SETTING);
+	write32(&mipi_tx0->phy_sel[0], MIPITX_CPHY_LANE_SEL0_SETTING);
+	write32(&mipi_tx0->phy_sel[1], MIPITX_CPHY_LANE_SEL1_SETTING);
+	write32(&mipi_tx0->phy_sel[2], MIPITX_CPHY_LANE_SEL2_SETTING);
+	write32(&mipi_tx0->phy_sel[3], MIPITX_CPHY_LANE_SEL3_SETTING);
 }
 
 void mtk_dsi_cphy_enable(void)
 {
-	setbits32(&mipi_tx->lane_con, DSI_CPHY_EN);
+	setbits32(&mipi_tx0->lane_con, DSI_CPHY_EN);
 }
 
 void mtk_dsi_cphy_disable_ck_mode(void)
 {
-	clrsetbits32(&mipi_tx->voltage_sel, DSI_HSTX_LDO_REF_SEL, 0xF << 6);
-	clrbits32(&mipi_tx->ck_ckmode_en, DSI_CK_CKMODE_EN);
-	setbits32(&mipi_tx->lane_con, DE_EMPHASIS_EN);
+	clrsetbits32(&mipi_tx0->voltage_sel, DSI_HSTX_LDO_REF_SEL, 0xF << 6);
+	clrbits32(&mipi_tx0->ck_ckmode_en, DSI_CK_CKMODE_EN);
+	setbits32(&mipi_tx0->lane_con, DE_EMPHASIS_EN);
 }
 
 void mtk_dsi_cphy_enable_cmdq_6byte(void)
diff --git a/src/soc/mediatek/common/mtk_mipi_dphy.c b/src/soc/mediatek/common/mtk_mipi_dphy.c
index 278f578cf2..3ebaa40109 100644
--- a/src/soc/mediatek/common/mtk_mipi_dphy.c
+++ b/src/soc/mediatek/common/mtk_mipi_dphy.c
@@ -5,5 +5,5 @@
 
 void mtk_dsi_dphy_disable_ck_mode(void)
 {
-	setbits32(&mipi_tx->ck_ckmode_en, DSI_CK_CKMODE_EN);
+	setbits32(&mipi_tx0->ck_ckmode_en, DSI_CK_CKMODE_EN);
 }

From 3607024944720f80ac6074b73fe4c57e4a2824aa Mon Sep 17 00:00:00 2001
From: Yu-Ping Wu <yupingso@chromium.org>
Date: Wed, 10 Dec 2025 23:53:25 +0800
Subject: [PATCH 2790/3886] soc/mediatek: Move mtk_dsi_init declaration to
 display_dsi.h

The soc/dsi.h header contains SoC-specific dsi and mipi_tx register
definitions, which are not needed for SoCs not supporting MIPI DSI
panels (such as mt8195). To decouple the generic display.c (used for
both eDP and MIPI panels) from those register definitions, move the
mtk_dsi_init() declaration and MIPI_DSI_* enums to display_dsi.h.

This allows us to remove the unused soc/dsi.h for mt8195.

BUG=b:424782827
TEST=util/abuild/abuild -x -t GOOGLE_ASURADA -a
TEST=emerge-skywalker coreboot
BRANCH=none

Change-Id: I56e458ec8077ed48929637b9b5c70f08653cc73f
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90449
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Chen-Tsung Hsieh <chentsung@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/soc/mediatek/common/display.c             |  2 +-
 src/soc/mediatek/common/dsi_common.c          |  1 +
 .../mediatek/common/include/soc/display_dsi.h | 55 +++++++++++++++++++
 .../mediatek/common/include/soc/dsi_common.h  | 49 +----------------
 src/soc/mediatek/mt8195/include/soc/dsi.h     |  8 ---
 5 files changed, 60 insertions(+), 55 deletions(-)
 create mode 100644 src/soc/mediatek/common/include/soc/display_dsi.h
 delete mode 100644 src/soc/mediatek/mt8195/include/soc/dsi.h

diff --git a/src/soc/mediatek/common/display.c b/src/soc/mediatek/common/display.c
index afd74ee23a..d1880e4299 100644
--- a/src/soc/mediatek/common/display.c
+++ b/src/soc/mediatek/common/display.c
@@ -9,8 +9,8 @@
 #include <framebuffer_info.h>
 #include <soc/ddp.h>
 #include <soc/display.h>
+#include <soc/display_dsi.h>
 #include <soc/dptx.h>
-#include <soc/dsi.h>
 #include <soc/mtcmos.h>
 #include <stdio.h>
 #include <symbols.h>
diff --git a/src/soc/mediatek/common/dsi_common.c b/src/soc/mediatek/common/dsi_common.c
index f9e7e2954b..66a5aaf2e1 100644
--- a/src/soc/mediatek/common/dsi_common.c
+++ b/src/soc/mediatek/common/dsi_common.c
@@ -5,6 +5,7 @@
 #include <device/mmio.h>
 #include <delay.h>
 #include <edid.h>
+#include <soc/display_dsi.h>
 #include <soc/dsi.h>
 #include <string.h>
 #include <timer.h>
diff --git a/src/soc/mediatek/common/include/soc/display_dsi.h b/src/soc/mediatek/common/include/soc/display_dsi.h
new file mode 100644
index 0000000000..62bdb3cca3
--- /dev/null
+++ b/src/soc/mediatek/common/include/soc/display_dsi.h
@@ -0,0 +1,55 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef SOC_MEDIATEK_DISPLAY_DSI_H
+#define SOC_MEDIATEK_DISPLAY_DSI_H
+
+#include <edid.h>
+#include <types.h>
+
+enum mipi_dsi_pixel_format {
+	MIPI_DSI_FMT_RGB888,
+	MIPI_DSI_FMT_RGB666,
+	MIPI_DSI_FMT_RGB666_PACKED,
+	MIPI_DSI_FMT_RGB565
+};
+
+/* video mode */
+enum {
+	MIPI_DSI_MODE_VIDEO = BIT(0),
+	/* video burst mode */
+	MIPI_DSI_MODE_VIDEO_BURST = BIT(1),
+	/* video pulse mode */
+	MIPI_DSI_MODE_VIDEO_SYNC_PULSE = BIT(2),
+	/* enable auto vertical count mode */
+	MIPI_DSI_MODE_VIDEO_AUTO_VERT = BIT(3),
+	/* enable hsync-end packets in vsync-pulse and v-porch area */
+	MIPI_DSI_MODE_VIDEO_HSE = BIT(4),
+	/* disable hfront-porch area */
+	MIPI_DSI_MODE_VIDEO_HFP = BIT(5),
+	/* disable hback-porch area */
+	MIPI_DSI_MODE_VIDEO_HBP = BIT(6),
+	/* disable hsync-active area */
+	MIPI_DSI_MODE_VIDEO_HSA = BIT(7),
+	/* flush display FIFO on vsync pulse */
+	MIPI_DSI_MODE_VSYNC_FLUSH = BIT(8),
+	/* disable EoT packets in HS mode */
+	MIPI_DSI_MODE_EOT_PACKET = BIT(9),
+	/* device supports non-continuous clock behavior (DSI spec 5.6.1) */
+	MIPI_DSI_CLOCK_NON_CONTINUOUS = BIT(10),
+	/* transmit data in low power */
+	MIPI_DSI_MODE_LPM = BIT(11),
+	/* dsi per line's data end same time on all lanes */
+	MIPI_DSI_MODE_LINE_END = BIT(12),
+	/* mipi is in CPHY mode */
+	MIPI_DSI_MODE_CPHY = BIT(13),
+	/* mipi is DSI Dual Channel mode */
+	MIPI_DSI_DUAL_CHANNEL = BIT(14),
+	/* mipi is DSC compression mode */
+	MIPI_DSI_DSC_MODE = BIT(15),
+};
+
+/* Public API for common display code (display.c). */
+int mtk_dsi_init(u32 mode_flags, u32 format, u32 lanes, const struct edid *edid,
+		 const u8 *init_commands);
+
+#endif /* SOC_MEDIATEK_DISPLAY_DSI_H */
diff --git a/src/soc/mediatek/common/include/soc/dsi_common.h b/src/soc/mediatek/common/include/soc/dsi_common.h
index a21929809f..83f6254777 100644
--- a/src/soc/mediatek/common/include/soc/dsi_common.h
+++ b/src/soc/mediatek/common/include/soc/dsi_common.h
@@ -8,48 +8,7 @@
 #include <mipi/dsi.h>
 #include <types.h>
 #include <soc/addressmap.h>
-
-enum mipi_dsi_pixel_format {
-	MIPI_DSI_FMT_RGB888,
-	MIPI_DSI_FMT_RGB666,
-	MIPI_DSI_FMT_RGB666_PACKED,
-	MIPI_DSI_FMT_RGB565
-};
-
-/* video mode */
-enum {
-	MIPI_DSI_MODE_VIDEO = BIT(0),
-	/* video burst mode */
-	MIPI_DSI_MODE_VIDEO_BURST = BIT(1),
-	/* video pulse mode */
-	MIPI_DSI_MODE_VIDEO_SYNC_PULSE = BIT(2),
-	/* enable auto vertical count mode */
-	MIPI_DSI_MODE_VIDEO_AUTO_VERT = BIT(3),
-	/* enable hsync-end packets in vsync-pulse and v-porch area */
-	MIPI_DSI_MODE_VIDEO_HSE = BIT(4),
-	/* disable hfront-porch area */
-	MIPI_DSI_MODE_VIDEO_HFP = BIT(5),
-	/* disable hback-porch area */
-	MIPI_DSI_MODE_VIDEO_HBP = BIT(6),
-	/* disable hsync-active area */
-	MIPI_DSI_MODE_VIDEO_HSA = BIT(7),
-	/* flush display FIFO on vsync pulse */
-	MIPI_DSI_MODE_VSYNC_FLUSH = BIT(8),
-	/* disable EoT packets in HS mode */
-	MIPI_DSI_MODE_EOT_PACKET = BIT(9),
-	/* device supports non-continuous clock behavior (DSI spec 5.6.1) */
-	MIPI_DSI_CLOCK_NON_CONTINUOUS = BIT(10),
-	/* transmit data in low power */
-	MIPI_DSI_MODE_LPM = BIT(11),
-	/* dsi per line's data end same time on all lanes */
-	MIPI_DSI_MODE_LINE_END = BIT(12),
-	/* mipi is in CPHY mode */
-	MIPI_DSI_MODE_CPHY = BIT(13),
-	/* mipi is DSI Dual Channel mode */
-	MIPI_DSI_DUAL_CHANNEL = BIT(14),
-	/* mipi is DSC compression mode */
-	MIPI_DSI_DSC_MODE = BIT(15),
-};
+#include <soc/display_dsi.h>
 
 static struct dsi_regs *const dsi0 = (void *)DSI0_BASE;
 
@@ -209,8 +168,8 @@ void mtk_dsi_reset(void);
 void mtk_dsi_override_phy_timing(struct mtk_phy_timing *timing);
 
 /*
- * Public API provided in common/dsi_common.c, common/dsi_v1.c, and
- * common/mtk_mipi_{c/d}phy.c
+ * DSI-internal APIs provided in common/dsi_common.c, common/dsi_v1.c,
+ * and common/mtk_mipi_{c/d}phy.c
  */
 void mtk_dsi_cphy_enable(void);
 void mtk_dsi_cphy_enable_cmdq_6byte(void);
@@ -224,7 +183,5 @@ void mtk_dsi_cphy_disable_ck_mode(void);
 void mtk_dsi_dphy_disable_ck_mode(void);
 void mtk_dsi_dphy_timing_calculation(u32 data_rate_mhz, struct mtk_phy_timing *timing);
 void mtk_dsi_configure_mipi_tx(u32 data_rate, u32 lanes, bool is_cphy);
-int mtk_dsi_init(u32 mode_flags, u32 format, u32 lanes, const struct edid *edid,
-		 const u8 *init_commands);
 
 #endif /* SOC_MEDIATEK_DSI_COMMON_H */
diff --git a/src/soc/mediatek/mt8195/include/soc/dsi.h b/src/soc/mediatek/mt8195/include/soc/dsi.h
deleted file mode 100644
index 0fd65b93f8..0000000000
--- a/src/soc/mediatek/mt8195/include/soc/dsi.h
+++ /dev/null
@@ -1,8 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#ifndef SOC_MEDIATEK_MT8195_DSI_H
-#define SOC_MEDIATEK_MT8195_DSI_H
-
-#include <soc/dsi_common.h>
-
-#endif

From a3317182ff8f01c6232609e9c210d736b6050374 Mon Sep 17 00:00:00 2001
From: Yu-Ping Wu <yupingso@chromium.org>
Date: Thu, 11 Dec 2025 06:42:09 +0800
Subject: [PATCH 2791/3886] soc/mediatek/common: Move dsi0 definition to
 dsi_register_v*.h

Move dsi0 variable definition to dsi_register_v*.h to be closer to the
register struct definition. This also allows us to define dsi1 for
mt8196 at the same place as dsi0 in a future patch. The dsi1 variable
cannot be defined in dsi_common.h because not all MediaTek SoCs using
the header have the DSI1_BASE register.

BUG=b:424782827
TEST=util/abuild/abuild -x -t GOOGLE_SAPPHIRE -a
BRANCH=none

Change-Id: I643f8d0317d0fb8bd8ea7bf8870ec99051c35c1b
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90452
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Chen-Tsung Hsieh <chentsung@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/soc/mediatek/common/include/soc/dsi_common.h      | 2 --
 src/soc/mediatek/common/include/soc/dsi_register_v1.h | 2 ++
 src/soc/mediatek/common/include/soc/dsi_register_v2.h | 2 ++
 3 files changed, 4 insertions(+), 2 deletions(-)

diff --git a/src/soc/mediatek/common/include/soc/dsi_common.h b/src/soc/mediatek/common/include/soc/dsi_common.h
index 83f6254777..c166f62e2f 100644
--- a/src/soc/mediatek/common/include/soc/dsi_common.h
+++ b/src/soc/mediatek/common/include/soc/dsi_common.h
@@ -10,8 +10,6 @@
 #include <soc/addressmap.h>
 #include <soc/display_dsi.h>
 
-static struct dsi_regs *const dsi0 = (void *)DSI0_BASE;
-
 /* DSI_INTSTA */
 enum {
 	LPRX_RD_RDY_INT_FLAG = BIT(0),
diff --git a/src/soc/mediatek/common/include/soc/dsi_register_v1.h b/src/soc/mediatek/common/include/soc/dsi_register_v1.h
index ec5dfdac63..3f9f4cb543 100644
--- a/src/soc/mediatek/common/include/soc/dsi_register_v1.h
+++ b/src/soc/mediatek/common/include/soc/dsi_register_v1.h
@@ -53,4 +53,6 @@ check_member(dsi_regs, dsi_vm_cmd_con, 0x130);
 check_member(dsi_regs, dsi_force_commit, 0x190);
 check_member(dsi_regs, dsi_cmdq, 0x200);
 
+static struct dsi_regs *const dsi0 = (void *)DSI0_BASE;
+
 #endif /* DSI_REGISTER_V1_H */
diff --git a/src/soc/mediatek/common/include/soc/dsi_register_v2.h b/src/soc/mediatek/common/include/soc/dsi_register_v2.h
index 5c26ba51af..193c96ecb3 100644
--- a/src/soc/mediatek/common/include/soc/dsi_register_v2.h
+++ b/src/soc/mediatek/common/include/soc/dsi_register_v2.h
@@ -58,4 +58,6 @@ check_member(dsi_regs, dsi_vm_cmd_con, 0x130);
 check_member(dsi_regs, dsi_force_commit, 0x190);
 check_member(dsi_regs, dsi_cmdq, 0xd00);
 
+static struct dsi_regs *const dsi0 = (void *)DSI0_BASE;
+
 #endif /* DSI_REGISTER_V2_H */

From 74c13eead40e08dbe7fb94702042e76ba37faadf Mon Sep 17 00:00:00 2001
From: Yu-Ping Wu <yupingso@chromium.org>
Date: Thu, 11 Dec 2025 00:59:58 +0800
Subject: [PATCH 2792/3886] soc/mediatek/mt8196: Define dsi_regs/mipi_tx_regs
 structs

Add dsi_register_v3.h to define dsi_regs struct for mt8196, and add
dsi_reg.h to define mipi_tx_regs struct. Unlike other SoCs, mt8196
has dsi1 and mipi_tx1 registers in order to support DSI dual channel.

BUG=b:424782827
TEST=util/abuild/abuild -x -t GOOGLE_SAPPHIRE -a
BRANCH=none

Change-Id: I2b541c89a007f380de482bffa86aca60c351b526
Signed-off-by: Payne Lin <payne.lin@mediatek.corp-partner.google.com>
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90451
Reviewed-by: Chen-Tsung Hsieh <chentsung@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
---
 .../common/include/soc/dsi_register_v3.h      | 192 +++++++
 .../mediatek/mt8196/include/soc/addressmap.h  |   6 +-
 src/soc/mediatek/mt8196/include/soc/dsi.h     |   7 +
 src/soc/mediatek/mt8196/include/soc/dsi_reg.h | 506 ++++++++++++++++++
 4 files changed, 709 insertions(+), 2 deletions(-)
 create mode 100644 src/soc/mediatek/common/include/soc/dsi_register_v3.h
 create mode 100644 src/soc/mediatek/mt8196/include/soc/dsi_reg.h

diff --git a/src/soc/mediatek/common/include/soc/dsi_register_v3.h b/src/soc/mediatek/common/include/soc/dsi_register_v3.h
new file mode 100644
index 0000000000..f0bd0a9f52
--- /dev/null
+++ b/src/soc/mediatek/common/include/soc/dsi_register_v3.h
@@ -0,0 +1,192 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef DSI_REGISTER_V3_H
+#define DSI_REGISTER_V3_H
+
+#include <commonlib/helpers.h>
+#include <soc/addressmap.h>
+#include <types.h>
+
+struct dsi_regs {
+	u32 dsi_start;
+	u32 dsi_status;
+	u32 dsi_inten;
+	u32 dsi_intsta;
+	u32 dsi_dp_inten;
+	u32 dsi_dp_intsta;
+	u32 dsi_scp_inten;
+	u32 dsi_scp_intsta;
+	u32 dsi_cg_con;
+	u32 dsi_rst_con;
+	u32 dsi_1tnp_con;
+	u32 dsi_size_con;
+	u32 dsi_con_ctrl;
+	u32 dsi_mode_ctrl;
+	u32 dsi_txrx_ctrl;
+	u32 dsi_psctrl;
+	u32 dsi_v3d_con;
+	u32 dsi_cmdq_size;
+	u32 dsi_mem_conti;
+	u32 dsi_frm_bc;
+	u32 dsi_cmd_type1_hs;
+	u32 dsi_cmd_type1_lp_ext;
+	u32 dsi_ext_source;
+	u32 reserved0;
+	u32 dsi_vsa_nl;
+	u32 dsi_vbp_nl;
+	u32 dsi_vfp_nl;
+	u32 dsi_vact_nl;
+	u32 reserved1[4];
+	u32 dsi_hsa_wc;
+	u32 dsi_hbp_wc;
+	u32 dsi_hfp_wc;
+	u32 dsi_bllp_wc;
+	u32 reserved2[4];
+	u32 dsi_rx_con;
+	u32 dsi_rx_data03;
+	u32 dsi_rx_data47;
+	u32 dsi_rx_data8b;
+	u32 dsi_rx_datac;
+	u32 dsi_rx_rack;
+	u32 dsi_rx_trig_sta;
+	u32 reserved3;
+	u32 dsi_dma_in_con0;
+	u32 dsi_dma_in_con1;
+	u32 reserved4[2];
+	u32 dsi_shadow_ctrl;
+	u32 dsi_shadow_group_en;
+	u32 dsi_shadow_source_sel;
+	u32 dsi_shadow_sta;
+	u32 reserved5[4];
+	u32 dsi_target_nl;
+	u32 reserved6;
+	u32 dsi_scramble_con;
+	u32 reserved7;
+	u32 dsi_hstx_cklp_wc;
+	u32 dsi_hstx_cklp_wc_auto_result;
+	u32 reserved8[2];
+	u32 dsi_vm_cmd_con;
+	u32 dsi_vm_cmd_con1;
+	u32 dsi_vm_cmd_data[16];
+	u32 reserved9[6];
+	u32 dsi_vfp_early_stop;
+	u32 dsi_vfp_early_stop_interval;
+	u32 dsi_vfp_early_stop_l0;
+	u32 dsi_vfp_early_stop_l2;
+	u32 dsi_vfp_early_stop_l4;
+	u32 dsi_vfp_early_stop_l6;
+	u32 reserved10[2];
+	u32 dsi_em_gen_con;
+	u32 reserved11[3];
+	u32 dsi_lfr_con;	/* Available since MT8183 */
+	u32 dsi_lfr_sta;	/* Available since MT8183 */
+	u32 dsi_ltpo_vdo_con;
+	u32 dsi_ltpo_vdo_sq0;
+	u32 dsi_ltpo_vdo_sq1;
+	u32 dsi_ltpo_vdo_sq2;
+	u32 dsi_ltpo_vdo_sq3;
+	u32 dsi_ltpo_vdo_sq4;
+	u32 reserved12[4];
+	u32 dsi_phy_lccon;
+	u32 dsi_phy_ld0con;
+	u32 dsi_phy_syncon;
+	u32 reserved13;
+	u32 dsi_cphy_con0;
+	u32 dsi_cphy_con1;
+	u32 reserved14[6];
+	u32 dsi_time_con0;
+	u32 dsi_time_con1;
+	u32 dsi_time_con2;
+	u32 reserved15;
+	u32 dsi_gce_event_con0;
+	u32 dsi_gce_event_con1;
+	u32 reserved16[2];
+	u32 dsi_dbg_con0;
+	u32 dsi_dbg_con1;
+	u32 reserved17[2];
+	u32 dsi_self_pat_con0;
+	u32 dsi_self_pat_con1;
+	u32 reserved18[2];
+	u32 dsi_input_setting;
+	u32 dsi_input_debug;
+	u32 dsi_in_cksm;
+	u32 reserved19;
+	u32 dsi_cksm_out;
+	u32 dsi_crc_cksm;
+	u32 dsi_sof_num;
+	u32 reserved20;
+	u32 dsi_frame_cnt_dsick;
+	u32 dsi_frame_cnt_mmck;
+	u32 reserved21[2];
+	u32 dsi_mac_state_dbg0[5];
+	u32 reserved22[7];
+	u32 dsi_mute_mode_con;
+	u32 dsi_mute_mode_dbg;
+	u32 reserved23[22];
+	u32 dsi_buf_con0;
+	u32 dsi_buf_con1;
+	u32 dsi_buf_reset;
+	u32 dsi_buf_log;
+	u32 dsi_buf_rw_times;
+	u32 dsi_buf_sodi_high;
+	u32 dsi_buf_sodi_low;
+	u32 dsi_buf_dvfs_high;
+	u32 dsi_buf_dvfs_low;
+	u32 dsi_buf_preultra_high;
+	u32 dsi_buf_preultra_low;
+	u32 dsi_buf_ultra_high;
+	u32 dsi_buf_ultra_low;
+	u32 dsi_buf_urgent_high;
+	u32 dsi_buf_urgent_low;
+	u32 dsi_buf_preurgent_high;
+	u32 reserved24[32];
+	u32 dsi_ocla_con0;
+	u32 reserved25;
+	u32 dsi_ocla_sub_log[5];
+	u32 dsi_ocla_dsi_log[5];
+	u32 dsi_mac_err;
+	u32 dsi_rollback_dbg;
+	u32 dsi_reserved;
+	u32 dsi_reserved_w_shadow;
+	u32 dsi_cmdq[128];
+	u32 dsi_phy_timecon0;
+	u32 dsi_phy_timecon1;
+	u32 dsi_phy_timecon2;
+	u32 dsi_phy_timecon3;
+	u32 dsi_phy_lcpat;
+	u32 dsi_phy_con;
+	u32 dsi_dphy_lane_swap;
+	u32 dsi_cphy_trio_swap;
+	u32 reserved26[2];
+	u32 dsi_cphy_trio_con;
+	u32 reserved27;
+	u32 dsi_dphy_dbg0;
+	u32 dsi_dphy_dbg1;
+	u32 dsi_dphy_dbg2;
+	u32 dsi_dphy_dbg3;
+	u32 dsi_dphy_dbg4;
+	u32 dsi_dphy_dbg5;
+	u32 dsi_dphy_dbg6;
+	u32 reserved28;
+	u32 dsi_cphy_dbg0;
+	u32 dsi_cphy_dbg1;
+	u32 reserved29[2];
+	u32 dsi_phy_dbg_con;
+	u32 reserved30[8];
+	u32 dsi_line_time_fix;
+	u32 reserved31[2];
+	u32 dsi_phy_cg_con;
+	u32 reserved32[26];
+	u32 dsi_phy_rollback_dbg;
+};
+
+check_member(dsi_regs, dsi_buf_con0, 0x300);
+check_member(dsi_regs, dsi_ocla_con0, 0x3C0);
+check_member(dsi_regs, dsi_phy_timecon0, 0x600);
+check_member(dsi_regs, dsi_phy_cg_con, 0x690);
+check_member(dsi_regs, dsi_phy_rollback_dbg, 0x6FC);
+
+static struct dsi_regs *const dsi0 = (void *)DSI0_BASE;
+static struct dsi_regs *const dsi1 = (void *)DSI1_BASE;
+
+#endif /* DSI_REGISTER_V3_H */
diff --git a/src/soc/mediatek/mt8196/include/soc/addressmap.h b/src/soc/mediatek/mt8196/include/soc/addressmap.h
index dd16892646..b7b5ef8027 100644
--- a/src/soc/mediatek/mt8196/include/soc/addressmap.h
+++ b/src/soc/mediatek/mt8196/include/soc/addressmap.h
@@ -76,8 +76,9 @@ enum {
 	IOCFG_LM1_BASE		= IO_PHYS + 0x03020000,
 	IOCFG_LM2_BASE		= IO_PHYS + 0x03040000,
 	EDP_PHY_BASE		= IO_PHYS + 0x030A0000,
-	MIPITX0_BASE		= IO_PHYS + 0x030b0000,
-	IOCFG_LB1_BASE		= IO_PHYS + 0x030f0000,
+	MIPITX0_BASE		= IO_PHYS + 0x030B0000,
+	MIPITX1_BASE		= IO_PHYS + 0x030C0000,
+	IOCFG_LB1_BASE		= IO_PHYS + 0x030F0000,
 	IOCFG_LB2_BASE		= IO_PHYS + 0x03110000,
 	I2C0_BASE		= IO_PHYS + 0x03130000,
 	I2C3_BASE		= IO_PHYS + 0x03150000,
@@ -214,6 +215,7 @@ enum {
 	DSC2_BASE		= IO_PHYS + 0x22470000,
 	DSC3_BASE		= IO_PHYS + 0x22480000,
 	DSI0_BASE		= IO_PHYS + 0x22490000,
+	DSI1_BASE		= IO_PHYS + 0x224A0000,
 	DISP_DVO0		= IO_PHYS + 0x224C0000,
 	OVLSYS_CONFIG_BASE	= IO_PHYS + 0x22800000,
 	OVLSYS_MUTEX_BASE	= IO_PHYS + 0x22820000,
diff --git a/src/soc/mediatek/mt8196/include/soc/dsi.h b/src/soc/mediatek/mt8196/include/soc/dsi.h
index 07278c2532..f9021346f4 100644
--- a/src/soc/mediatek/mt8196/include/soc/dsi.h
+++ b/src/soc/mediatek/mt8196/include/soc/dsi.h
@@ -4,5 +4,12 @@
 #define SOC_MEDIATEK_MT8196_DSI_H
 
 #include <soc/dsi_common.h>
+#include <soc/dsi_reg.h>
+
+#define MTK_DSI_MIPI_RATIO_NUMERATOR	100
+#define MTK_DSI_MIPI_RATIO_DENOMINATOR	100
+#define MTK_DSI_DATA_RATE_MIN_MHZ	125
+#define MTK_DSI_HAVE_SIZE_CON		1
+#define PIXEL_STREAM_CUSTOM_HEADER	0xb
 
 #endif
diff --git a/src/soc/mediatek/mt8196/include/soc/dsi_reg.h b/src/soc/mediatek/mt8196/include/soc/dsi_reg.h
new file mode 100644
index 0000000000..05460ff167
--- /dev/null
+++ b/src/soc/mediatek/mt8196/include/soc/dsi_reg.h
@@ -0,0 +1,506 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef _SOC_MEDIATEK_MT8196_DSI_REG_H_
+#define _SOC_MEDIATEK_MT8196_DSI_REG_H_
+
+#include <commonlib/helpers.h>
+#include <soc/addressmap.h>
+#include <soc/dsi_register_v3.h>
+#include <types.h>
+
+/* MIPITX_REG */
+struct mipi_tx_regs {
+	u32 reserved0;
+	u32 lane_con;
+	u32 voltage_sel;
+	u32 cdphy_preserved;
+	u32 dphy_lane_con;
+	u32 dphy_voltage_sel;
+	u32 dphy_preserved;
+	u32 test_con;
+	u32 top_con;
+	u32 ser_data;
+	u32 pll_pwr;
+	u32 pll_con0;
+	u32 pll_con1;
+	u32 pll_con2;
+	u32 pll_con3;
+	u32 pll_con4;
+	u32 phy_sel0;
+	u32 pa_con;
+	u32 ser_data1;
+	u32 ser_con;
+	u32 sw_ctrl_con4;
+	u32 gpio_con;
+	u32 dbg_con;
+	u32 err_sta;
+	u32 in_mux_sel;
+	u32 vidle_con;
+	u32 vidle_trig;
+	u32 vidle_timing_con0;
+	u32 vidle_timing_con1;
+	u32 vidle_dbg_sta0;
+	u32 vidle_dbg_sta1;
+	u32 vidle_cap_addr0;
+	u32 vidle_cap_addr1;
+	u32 vidle_cap_data0;
+	u32 vidle_cap_data1;
+	u32 vidle_cap_data2;
+	u32 vidle_cap_data3;
+	u32 reserved1[27];
+	u32 d2p_rtcode3_0;
+	u32 d2p_rtcode4;
+	u32 d2n_rtcode3_0;
+	u32 d2n_rtcode4;
+	u32 d2p_skew_hi;
+	u32 d2p_skew_lo;
+	u32 d2n_skew_hi;
+	u32 d2n_skew_lo;
+	u32 d2_ckmode_en;
+	u32 d2_ana_pn_swap_en;
+	u32 d2_t0_tiel_en;
+	u32 d2_ser_bisttog;
+	u32 d2_ser_din_sel;
+	u32 d2_ldoout_en;
+	u32 d2_loopback_en;
+	u32 d2_lptx_iplus1;
+	u32 d2_lptx_iplus2;
+	u32 d2_lptx_iminus;
+	u32 d2_lpcd_iplus;
+	u32 d2_lpcd_iminus;
+	u32 d2_rtcode;
+	u32 d2_cklane_en;
+	u32 d2_dig_pn_swap_en;
+	u32 d2_sw_ctl_en;
+	u32 d2_sw_lptx_pre_oe;
+	u32 d2_sw_lptx_oe;
+	u32 d2_sw_lptx_dp;
+	u32 d2_sw_lptx_dn;
+	u32 d2_sw_lprx_en;
+	u32 d2_sw_hstx_pre_oe;
+	u32 d2_sw_hstx_oe;
+	u32 d2_sw_hstx_rdy;
+	u32 d2c_sw_lptx_pre_oe;
+	u32 d2c_sw_lptx_oe;
+	u32 d2c_sw_lprx_en;
+	u32 d2c_sw_hstx_pre_oe;
+	u32 d2c_sw_hstx_oe;
+	u32 d2c_sw_hstx_rdy;
+	u32 d2_sw_hstx_data1_0;
+	u32 d2_sw_hstx_data3_2;
+	u32 d2_sw_hstx_data5_4;
+	u32 d2_sw_hstx_data7_6;
+	u32 d2c_sw_hstx_data1_0;
+	u32 d2c_sw_hstx_data3_2;
+	u32 d2c_sw_hstx_data5_4;
+	u32 d2c_sw_hstx_data6;
+	u32 d2_sw_cd_con;
+	u32 d2_ad_rx;
+	u32 d2_ad_cd;
+	u32 d2p_rt_dem_code;
+	u32 d2n_rt_dem_code;
+	u32 d2_hstx_ldo_iboost_en;
+	u32 d2_dbg_sel;
+	u32 d2_chksum0;
+	u32 d2_chksum1;
+	u32 d2_chksum2;
+	u32 d2_chksum3;
+	u32 d2_chksum4;
+	u32 d2_chksum5;
+	u32 d2_phy_rst_sel;
+	u32 d2c_abc_swap_sel;
+	u32 reserved2[3];
+	u32 d0p_rtcode3_0;
+	u32 d0p_rtcode4;
+	u32 d0n_rtcode3_0;
+	u32 d0n_rtcode4;
+	u32 d0p_skew_hi;
+	u32 d0p_skew_lo;
+	u32 d0n_skew_hi;
+	u32 d0n_skew_lo;
+	u32 d0_ckmode_en;
+	u32 d0_ana_pn_swap_en;
+	u32 d0_t0_tiel_en;
+	u32 d0_ser_bisttog;
+	u32 d0_ser_din_sel;
+	u32 d0_ldoout_en;
+	u32 d0_loopback_en;
+	u32 d0_lptx_iplus1;
+	u32 d0_lptx_iplus2;
+	u32 d0_lptx_iminus;
+	u32 d0_lpcd_iplus;
+	u32 d0_lpcd_iminus;
+	u32 d0_rtcode;
+	u32 d0_cklane_en;
+	u32 d0_dig_pn_swap_en;
+	u32 d0_sw_ctl_en;
+	u32 d0_sw_lptx_pre_oe;
+	u32 d0_sw_lptx_oe;
+	u32 d0_sw_lptx_dp;
+	u32 d0_sw_lptx_dn;
+	u32 d0_sw_lprx_en;
+	u32 d0_sw_hstx_pre_oe;
+	u32 d0_sw_hstx_oe;
+	u32 d0_sw_hstx_rdy;
+	u32 d0c_sw_lptx_pre_oe;
+	u32 d0c_sw_lptx_oe;
+	u32 d0c_sw_lprx_en;
+	u32 d0c_sw_hstx_pre_oe;
+	u32 d0c_sw_hstx_oe;
+	u32 d0c_sw_hstx_rdy;
+	u32 d0_sw_hstx_data1_0;
+	u32 d0_sw_hstx_data3_2;
+	u32 d0_sw_hstx_data5_4;
+	u32 d0_sw_hstx_data7_6;
+	u32 d0c_sw_hstx_data1_0;
+	u32 d0c_sw_hstx_data3_2;
+	u32 d0c_sw_hstx_data5_4;
+	u32 d0c_sw_hstx_data6;
+	u32 d0_sw_cd_con;
+	u32 d0_ad_rx;
+	u32 d0_ad_cd;
+	u32 d0p_rt_dem_code;
+	u32 d0n_rt_dem_code;
+	u32 d0_hstx_ldo_iboost_en;
+	u32 d0_dbg_sel;
+	u32 d0_chksum0;
+	u32 d0_chksum1;
+	u32 d0_chksum2;
+	u32 d0_chksum3;
+	u32 d0_chksum4;
+	u32 d0_chksum5;
+	u32 d0_phy_rst_sel;
+	u32 d0c_abc_swap_sel;
+	u32 reserved3[3];
+	u32 ckp_rtcode3_0;
+	u32 ckp_rtcode4;
+	u32 ckn_rtcode3_0;
+	u32 ckn_rtcode4;
+	u32 ckp_skew_hi;
+	u32 ckp_skew_lo;
+	u32 ckn_skew_hi;
+	u32 ckn_skew_lo;
+	u32 ck_ckmode_en;
+	u32 ck_ana_pn_swap_en;
+	u32 ck_t0_tiel_en;
+	u32 ck_ser_bisttog;
+	u32 ck_ser_din_sel;
+	u32 ck_ldoout_en;
+	u32 ck_loopback_en;
+	u32 ck_lptx_iplus1;
+	u32 ck_lptx_iplus2;
+	u32 ck_lptx_iminus;
+	u32 ck_lpcd_iplus;
+	u32 ck_lpcd_iminus;
+	u32 ck_rtcode;
+	u32 ck_cklane_en;
+	u32 ck_dig_pn_swap_en;
+	u32 ck_sw_ctl_en;
+	u32 ck_sw_lptx_pre_oe;
+	u32 ck_sw_lptx_oe;
+	u32 ck_sw_lptx_dp;
+	u32 ck_sw_lptx_dn;
+	u32 ck_sw_lprx_en;
+	u32 ck_sw_hstx_pre_oe;
+	u32 ck_sw_hstx_oe;
+	u32 ck_sw_hstx_rdy;
+	u32 ckc_sw_lptx_pre_oe;
+	u32 ckc_sw_lptx_oe;
+	u32 ckc_sw_lprx_en;
+	u32 ckc_sw_hstx_pre_oe;
+	u32 ckc_sw_hstx_oe;
+	u32 ckc_sw_hstx_rdy;
+	u32 ck_sw_hstx_data1_0;
+	u32 ck_sw_hstx_data3_2;
+	u32 ck_sw_hstx_data5_4;
+	u32 ck_sw_hstx_data7_6;
+	u32 ckc_sw_hstx_data1_0;
+	u32 ckc_sw_hstx_data3_2;
+	u32 ckc_sw_hstx_data5_4;
+	u32 ckc_sw_hstx_data6;
+	u32 ck_sw_cd_con;
+	u32 ck_ad_rx;
+	u32 ck_ad_cd;
+	u32 ckp_rt_dem_code;
+	u32 ckn_rt_dem_code;
+	u32 ck_hstx_ldo_iboost_en;
+	u32 ck_dbg_sel;
+	u32 ck_chksum0;
+	u32 ck_chksum1;
+	u32 ck_chksum2;
+	u32 ck_chksum3;
+	u32 ck_chksum4;
+	u32 ck_chksum5;
+	u32 ck_phy_rst_sel;
+	u32 ckc_abc_swap_sel;
+	u32 reserved4[3];
+	u32 d1p_rtcode3_0;
+	u32 d1p_rtcode4;
+	u32 d1n_rtcode3_0;
+	u32 d1n_rtcode4;
+	u32 d1p_skew_hi;
+	u32 d1p_skew_lo;
+	u32 d1n_skew_hi;
+	u32 d1n_skew_lo;
+	u32 d1_ckmode_en;
+	u32 d1_ana_pn_swap_en;
+	u32 d1_t0_tiel_en;
+	u32 d1_ser_bisttog;
+	u32 d1_ser_din_sel;
+	u32 d1_ldoout_en;
+	u32 d1_loopback_en;
+	u32 d1_lptx_iplus1;
+	u32 d1_lptx_iplus2;
+	u32 d1_lptx_iminus;
+	u32 d1_lpcd_iplus;
+	u32 d1_lpcd_iminus;
+	u32 d1_rtcode;
+	u32 d1_cklane_en;
+	u32 d1_dig_pn_swap_en;
+	u32 d1_sw_ctl_en;
+	u32 d1_sw_lptx_pre_oe;
+	u32 d1_sw_lptx_oe;
+	u32 d1_sw_lptx_dp;
+	u32 d1_sw_lptx_dn;
+	u32 d1_sw_lprx_en;
+	u32 d1_sw_hstx_pre_oe;
+	u32 d1_sw_hstx_oe;
+	u32 d1_sw_hstx_rdy;
+	u32 d1c_sw_lptx_pre_oe;
+	u32 d1c_sw_lptx_oe;
+	u32 d1c_sw_lprx_en;
+	u32 d1c_sw_hstx_pre_oe;
+	u32 d1c_sw_hstx_oe;
+	u32 d1c_sw_hstx_rdy;
+	u32 d1_sw_hstx_data1_0;
+	u32 d1_sw_hstx_data3_2;
+	u32 d1_sw_hstx_data5_4;
+	u32 d1_sw_hstx_data7_6;
+	u32 d1c_sw_hstx_data1_0;
+	u32 d1c_sw_hstx_data3_2;
+	u32 d1c_sw_hstx_data5_4;
+	u32 d1c_sw_hstx_data6;
+	u32 d1_sw_cd_con;
+	u32 d1_ad_rx;
+	u32 d1_ad_cd;
+	u32 d1p_rt_dem_code;
+	u32 d1n_rt_dem_code;
+	u32 d1_hstx_ldo_iboost_en;
+	u32 d1_dbg_sel;
+	u32 d1_chksum0;
+	u32 d1_chksum1;
+	u32 d1_chksum2;
+	u32 d1_chksum3;
+	u32 d1_chksum4;
+	u32 d1_chksum5;
+	u32 d1_phy_rst_sel;
+	u32 d1c_abc_swap_sel;
+	u32 reserved5[3];
+	u32 d3p_rtcode3_0;
+	u32 d3p_rtcode4;
+	u32 d3n_rtcode3_0;
+	u32 d3n_rtcode4;
+	u32 d3p_skew_hi;
+	u32 d3p_skew_lo;
+	u32 d3n_skew_hi;
+	u32 d3n_skew_lo;
+	u32 d3_ckmode_en;
+	u32 d3_ana_pn_swap_en;
+	u32 d3_t0_tiel_en;
+	u32 d3_ser_bisttog;
+	u32 d3_ser_din_sel;
+	u32 d3_ldoout_en;
+	u32 d3_loopback_en;
+	u32 d3_lptx_iplus1;
+	u32 d3_lptx_iplus2;
+	u32 d3_lptx_iminus;
+	u32 d3_lpcd_iplus;
+	u32 d3_lpcd_iminus;
+	u32 d3_rtcode;
+	u32 d3_cklane_en;
+	u32 d3_dig_pn_swap_en;
+	u32 d3_sw_ctl_en;
+	u32 d3_sw_lptx_pre_oe;
+	u32 d3_sw_lptx_oe;
+	u32 d3_sw_lptx_dp;
+	u32 d3_sw_lptx_dn;
+	u32 d3_sw_lprx_en;
+	u32 d3_sw_hstx_pre_oe;
+	u32 d3_sw_hstx_oe;
+	u32 d3_sw_hstx_rdy;
+	u32 d3c_sw_lptx_pre_oe;
+	u32 d3c_sw_lptx_oe;
+	u32 d3c_sw_lprx_en;
+	u32 d3c_sw_hstx_pre_oe;
+	u32 d3c_sw_hstx_oe;
+	u32 d3c_sw_hstx_rdy;
+	u32 d3_sw_hstx_data1_0;
+	u32 d3_sw_hstx_data3_2;
+	u32 d3_sw_hstx_data5_4;
+	u32 d3_sw_hstx_data7_6;
+	u32 d3c_sw_hstx_data1_0;
+	u32 d3c_sw_hstx_data3_2;
+	u32 d3c_sw_hstx_data5_4;
+	u32 d3c_sw_hstx_data6;
+	u32 d3_sw_cd_con;
+	u32 d3_ad_rx;
+	u32 d3_ad_cd;
+	u32 d3p_rt_dem_code;
+	u32 d3n_rt_dem_code;
+	u32 d3_hstx_ldo_iboost_en;
+	u32 d3_dbg_sel;
+	u32 d3_chksum0;
+	u32 d3_chksum1;
+	u32 d3_chksum2;
+	u32 d3_chksum3;
+	u32 d3_chksum4;
+	u32 d3_chksum5;
+	u32 d3_phy_rst_sel;
+	u32 d3c_abc_swap_sel;
+	u32 reserved6[3];
+	u32 dphy_bist_con0;
+	u32 dphy_bist_con1;
+	u32 dphy_bist_con2;
+	u32 reserved7[2];
+	u32 dphy_bist_pattern_0;
+	u32 dphy_bist_pattern_1;
+	u32 dphy_bist_pattern_2;
+	u32 dphy_bist_pattern_3;
+	u32 dphy_bist_pattern_4;
+	u32 dphy_bist_pattern_5;
+	u32 dphy_bist_pattern_6;
+	u32 dphy_bist_pattern_7;
+	u32 cphy_bist_con0;
+	u32 cphy_bist_con1;
+	u32 cphy_bist_wire_state;
+	u32 cphy_bist_prb_sel;
+	u32 reserved8[4];
+	u32 cphy_bist_progseq_lsb_0;
+	u32 cphy_bist_progseq_lsb_1;
+	u32 cphy_bist_progseq_lsb_2;
+	u32 cphy_bist_progseq_lsb_3;
+	u32 cphy_bist_progseq_lsb_4;
+	u32 cphy_bist_progseq_lsb_5;
+	u32 cphy_bist_progseq_lsb_6;
+	u32 cphy_bist_progseq_lsb_7;
+	u32 cphy_bist_progseq_msb_0;
+	u32 cphy_bist_progseq_msb_1;
+	u32 cphy_bist_progseq_msb_2;
+	u32 cphy_bist_prb_seed_0;
+	u32 cphy_bist_prb_seed_1;
+	u32 cphy_bist_prb_seed_2;
+	u32 cphy_bist_prb_seed_3;
+	u32 cphy_bist_prb_seed_4;
+	u32 cphy_bist_prebegin_sym;
+	u32 cphy_bist_preend_sym;
+	u32 reserved9;
+	u32 bist_timing00_hi;
+	u32 bist_timing00_lo;
+	u32 bist_timing01_hi;
+	u32 bist_timing01_lo;
+	u32 bist_timing02_hi;
+	u32 bist_timing02_lo;
+	u32 bist_timing03_hi;
+	u32 bist_timing03_lo;
+	u32 bist_timing04_hi;
+	u32 bist_timing04_lo;
+	u32 bist_timing05_hi;
+	u32 bist_timing05_lo;
+	u32 bist_timing06_hi;
+	u32 bist_timing06_lo;
+	u32 bist_timing07_hi;
+	u32 bist_timing07_lo;
+	u32 bist_timing08_hi;
+	u32 bist_timing08_lo;
+	u32 bist_timing09_hi;
+	u32 bist_timing09_lo;
+	u32 bist_timing10_hi;
+	u32 bist_timing10_lo;
+	u32 reserved10[2];
+	u32 ck1p_rtcode3_0;
+	u32 ck1p_rtcode4;
+	u32 ck1n_rtcode3_0;
+	u32 ck1n_rtcode4;
+	u32 ck1p_skew_hi;
+	u32 ck1p_skew_lo;
+	u32 ck1n_skew_hi;
+	u32 ck1n_skew_lo;
+	u32 ck1_ckmode_en;
+	u32 ck1_ana_pn_swap_en;
+	u32 ck1_t0_tiel_en;
+	u32 ck1_ser_bisttog;
+	u32 ck1_ser_din_sel;
+	u32 ck1_ldoout_en;
+	u32 ck1_loopback_en;
+	u32 ck1_lptx_iplus1;
+	u32 ck1_lptx_iplus2;
+	u32 ck1_lptx_iminus;
+	u32 ck1_lpcd_iplus;
+	u32 ck1_lpcd_iminus;
+	u32 ck1_rtcode;
+	u32 ck1_cklane_en;
+	u32 ck1_dig_pn_swap_en;
+	u32 ck1_sw_ctl_en;
+	u32 ck1_sw_lptx_pre_oe;
+	u32 ck1_sw_lptx_oe;
+	u32 ck1_sw_lptx_dp;
+	u32 ck1_sw_lptx_dn;
+	u32 ck1_sw_lprx_en;
+	u32 ck1_sw_hstx_pre_oe;
+	u32 ck1_sw_hstx_oe;
+	u32 ck1_sw_hstx_rdy;
+	u32 ck1c_sw_lptx_pre_oe;
+	u32 ck1c_sw_lptx_oe;
+	u32 ck1c_sw_lprx_en;
+	u32 ck1c_sw_hstx_pre_oe;
+	u32 ck1c_sw_hstx_oe;
+	u32 ck1c_sw_hstx_rdy;
+	u32 ck1_sw_hstx_data1_0;
+	u32 ck1_sw_hstx_data3_2;
+	u32 ck1_sw_hstx_data5_4;
+	u32 ck1_sw_hstx_data7_6;
+	u32 ck1c_sw_hstx_data1_0;
+	u32 ck1c_sw_hstx_data3_2;
+	u32 ck1c_sw_hstx_data5_4;
+	u32 ck1c_sw_hstx_data6;
+	u32 ck1_sw_cd_con;
+	u32 ck1_ad_rx;
+	u32 ck1_ad_cd;
+	u32 ck1p_rt_dem_code;
+	u32 ck1n_rt_dem_code;
+	u32 ck1_hstx_ldo_iboost_en;
+	u32 ck1_dbg_sel;
+	u32 ck1_chksum0;
+	u32 ck1_chksum1;
+	u32 ck1_chksum2;
+	u32 ck1_chksum3;
+	u32 ck1_chksum4;
+	u32 ck1_chksum5;
+	u32 ck1_phy_rst_sel;
+	u32 ck1c_abc_swap_sel;
+};
+
+check_member(mipi_tx_regs, d2p_rtcode3_0, 0x100);
+check_member(mipi_tx_regs, d0c_abc_swap_sel, 0x2F0);
+check_member(mipi_tx_regs, ck1p_rtcode3_0, 0x700);
+check_member(mipi_tx_regs, ck1c_abc_swap_sel, 0x7F0);
+
+static struct mipi_tx_regs *const mipi_tx0 = (void *)MIPITX0_BASE;
+static struct mipi_tx_regs *const mipi_tx1 = (void *)MIPITX1_BASE;
+
+/* Register values */
+#define RG_DSI_HSTX_LDO_REF_SEL		GENMASK(9, 6)
+#define RG_DSI_PRD_REF_SEL		GENMASK(5, 0)
+#define RG_DSI_PRD_REF_MINI		0
+#define RG_DSI_PRD_REF_DEF		4
+#define RG_DSI_PRD_REF_MAX		7
+
+#define DSI_CK_CKMODE_EN	BIT(0)
+#define DSI_SW_CTL_EN		BIT(0)
+#define AD_DSI_PLL_SDM_PWR_ON	BIT(0)
+#define AD_DSI_PLL_SDM_ISO_EN	BIT(1)
+
+#define RG_DSI_PLL_EN		BIT(0)
+#define RG_DSI_PLL_POSDIV	GENMASK(10, 8)
+
+#endif /* _SOC_MEDIATEK_MT8196_DSI_REG_H_ */

From 6b5a872ce850b92a79445e27eee3c4eabe76a30d Mon Sep 17 00:00:00 2001
From: Yu-Ping Wu <yupingso@chromium.org>
Date: Wed, 10 Dec 2025 17:18:56 +0800
Subject: [PATCH 2793/3886] soc/mediatek: Pass dsi_regs/mipi_tx_regs to DSI API

In preparation for the upcoming DSI dual channel support, pass dsi_regs
and mipi_tx_regs to DSI functions that need to access these registers.

BUG=b:424782827
TEST=util/abuild/abuild -x -t GOOGLE_SAPPHIRE -a
BRANCH=none

Change-Id: Ia0c9051148e38a7703119f800d417f2f8b52f78a
Signed-off-by: Payne Lin <payne.lin@mediatek.corp-partner.google.com>
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90446
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Chen-Tsung Hsieh <chentsung@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/soc/mediatek/common/dsi_common.c          |  6 +--
 src/soc/mediatek/common/dsi_v1.c              | 46 ++++++++++---------
 .../mediatek/common/include/soc/dsi_common.h  | 16 ++++---
 src/soc/mediatek/common/mtk_mipi_cphy.c       | 26 +++++------
 src/soc/mediatek/common/mtk_mipi_dphy.c       |  4 +-
 src/soc/mediatek/mt8173/dsi.c                 | 37 +++++++--------
 6 files changed, 70 insertions(+), 65 deletions(-)

diff --git a/src/soc/mediatek/common/dsi_common.c b/src/soc/mediatek/common/dsi_common.c
index 66a5aaf2e1..5ee8985dfd 100644
--- a/src/soc/mediatek/common/dsi_common.c
+++ b/src/soc/mediatek/common/dsi_common.c
@@ -290,7 +290,7 @@ static void mtk_dsi_config_vdo_timing(u32 mode_flags, u32 format, u32 lanes,
 			edid->mode.va << DSI_SIZE_CON_HEIGHT_SHIFT |
 			hactive << DSI_SIZE_CON_WIDTH_SHIFT);
 	if (CONFIG(MEDIATEK_DSI_CPHY) && is_cphy)
-		mtk_dsi_cphy_enable_cmdq_6byte();
+		mtk_dsi_cphy_enable_cmdq_6byte(dsi0);
 }
 
 static void mtk_dsi_start(void)
@@ -385,8 +385,8 @@ int mtk_dsi_init(u32 mode_flags, u32 format, u32 lanes, const struct edid *edid,
 	if (!data_rate)
 		return -1;
 
-	mtk_dsi_configure_mipi_tx(data_rate, lanes, is_cphy);
-	mtk_dsi_reset();
+	mtk_dsi_configure_mipi_tx(mipi_tx0, data_rate, lanes, is_cphy);
+	mtk_dsi_reset(dsi0);
 	struct mtk_phy_timing phy_timing = {};
 	if (CONFIG(MEDIATEK_DSI_CPHY) && is_cphy)
 		mtk_dsi_cphy_timing(data_rate, &phy_timing);
diff --git a/src/soc/mediatek/common/dsi_v1.c b/src/soc/mediatek/common/dsi_v1.c
index 030f034052..9d41104d82 100644
--- a/src/soc/mediatek/common/dsi_v1.c
+++ b/src/soc/mediatek/common/dsi_v1.c
@@ -6,7 +6,8 @@
 #include <soc/dsi.h>
 #include <soc/pll.h>
 
-void mtk_dsi_configure_mipi_tx(u32 data_rate, u32 lanes, bool is_cphy)
+void mtk_dsi_configure_mipi_tx(struct mipi_tx_regs *mipi_tx_reg,
+			       u32 data_rate, u32 lanes, bool is_cphy)
 {
 	unsigned int txdiv0;
 	u64 pcw;
@@ -28,47 +29,48 @@ void mtk_dsi_configure_mipi_tx(u32 data_rate, u32 lanes, bool is_cphy)
 	}
 
 	if (CONFIG(MEDIATEK_DSI_CPHY) && is_cphy)
-		mtk_dsi_cphy_lane_sel_setting();
+		mtk_dsi_cphy_lane_sel_setting(mipi_tx_reg);
 
-	clrbits32(&mipi_tx0->pll_con4, BIT(11) | BIT(10));
-	setbits32(&mipi_tx0->pll_pwr, AD_DSI_PLL_SDM_PWR_ON);
+	clrbits32(&mipi_tx_reg->pll_con4, BIT(11) | BIT(10));
+	setbits32(&mipi_tx_reg->pll_pwr, AD_DSI_PLL_SDM_PWR_ON);
 	udelay(30);
-	clrbits32(&mipi_tx0->pll_pwr, AD_DSI_PLL_SDM_ISO_EN);
+	clrbits32(&mipi_tx_reg->pll_pwr, AD_DSI_PLL_SDM_ISO_EN);
 
 	pcw = (u64)data_rate * (1 << txdiv0);
 	pcw <<= 24;
 	pcw /= CLK26M_HZ;
 
-	write32(&mipi_tx0->pll_con0, pcw);
-	clrsetbits32(&mipi_tx0->pll_con1, RG_DSI_PLL_POSDIV, txdiv0 << 8);
+	write32(&mipi_tx_reg->pll_con0, pcw);
+	clrsetbits32(&mipi_tx_reg->pll_con1, RG_DSI_PLL_POSDIV, txdiv0 << 8);
 	udelay(30);
-	setbits32(&mipi_tx0->pll_con1, RG_DSI_PLL_EN);
+	setbits32(&mipi_tx_reg->pll_con1, RG_DSI_PLL_EN);
 
 	/* BG_LPF_EN / BG_CORE_EN */
-	write32(&mipi_tx0->lane_con, 0x3FFF0180);
+	write32(&mipi_tx_reg->lane_con, 0x3FFF0180);
 	udelay(40);
-	write32(&mipi_tx0->lane_con, 0x3FFF00C0);
+	write32(&mipi_tx_reg->lane_con, 0x3FFF00C0);
 
 	if (CONFIG(MEDIATEK_DSI_CPHY) && is_cphy)
-		mtk_dsi_cphy_enable();
+		mtk_dsi_cphy_enable(mipi_tx_reg);
 
 	/* Switch OFF each Lane */
-	clrbits32(&mipi_tx0->d0_sw_ctl_en, DSI_SW_CTL_EN);
-	clrbits32(&mipi_tx0->d1_sw_ctl_en, DSI_SW_CTL_EN);
-	clrbits32(&mipi_tx0->d2_sw_ctl_en, DSI_SW_CTL_EN);
-	clrbits32(&mipi_tx0->d3_sw_ctl_en, DSI_SW_CTL_EN);
-	clrbits32(&mipi_tx0->ck_sw_ctl_en, DSI_SW_CTL_EN);
+	clrbits32(&mipi_tx_reg->d0_sw_ctl_en, DSI_SW_CTL_EN);
+	clrbits32(&mipi_tx_reg->d1_sw_ctl_en, DSI_SW_CTL_EN);
+	clrbits32(&mipi_tx_reg->d2_sw_ctl_en, DSI_SW_CTL_EN);
+	clrbits32(&mipi_tx_reg->d3_sw_ctl_en, DSI_SW_CTL_EN);
+	clrbits32(&mipi_tx_reg->ck_sw_ctl_en, DSI_SW_CTL_EN);
 
 	if (CONFIG(MEDIATEK_DSI_CPHY) && is_cphy)
-		mtk_dsi_cphy_disable_ck_mode();
+		mtk_dsi_cphy_disable_ck_mode(mipi_tx_reg);
 	else
-		mtk_dsi_dphy_disable_ck_mode();
+		mtk_dsi_dphy_disable_ck_mode(mipi_tx_reg);
+
 }
 
-void mtk_dsi_reset(void)
+void mtk_dsi_reset(struct dsi_regs *dsi_reg)
 {
-	write32(&dsi0->dsi_force_commit,
+	write32(&dsi_reg->dsi_force_commit,
 		DSI_FORCE_COMMIT_USE_MMSYS | DSI_FORCE_COMMIT_ALWAYS);
-	write32(&dsi0->dsi_con_ctrl, 1);
-	write32(&dsi0->dsi_con_ctrl, 0);
+	write32(&dsi_reg->dsi_con_ctrl, 1);
+	write32(&dsi_reg->dsi_con_ctrl, 0);
 }
diff --git a/src/soc/mediatek/common/include/soc/dsi_common.h b/src/soc/mediatek/common/include/soc/dsi_common.h
index c166f62e2f..e06701f490 100644
--- a/src/soc/mediatek/common/include/soc/dsi_common.h
+++ b/src/soc/mediatek/common/include/soc/dsi_common.h
@@ -9,6 +9,7 @@
 #include <types.h>
 #include <soc/addressmap.h>
 #include <soc/display_dsi.h>
+#include <soc/dsi_reg.h>
 
 /* DSI_INTSTA */
 enum {
@@ -160,7 +161,7 @@ struct mtk_phy_timing {
 };
 
 /* Functions that each SOC should provide. */
-void mtk_dsi_reset(void);
+void mtk_dsi_reset(struct dsi_regs *dsi_reg);
 
 /* Functions as weak no-ops that can be overridden. */
 void mtk_dsi_override_phy_timing(struct mtk_phy_timing *timing);
@@ -169,17 +170,18 @@ void mtk_dsi_override_phy_timing(struct mtk_phy_timing *timing);
  * DSI-internal APIs provided in common/dsi_common.c, common/dsi_v1.c,
  * and common/mtk_mipi_{c/d}phy.c
  */
-void mtk_dsi_cphy_enable(void);
-void mtk_dsi_cphy_enable_cmdq_6byte(void);
-void mtk_dsi_cphy_lane_sel_setting(void);
+void mtk_dsi_cphy_enable(struct mipi_tx_regs *mipi_tx_reg);
+void mtk_dsi_cphy_enable_cmdq_6byte(struct dsi_regs *dsi_reg);
+void mtk_dsi_cphy_lane_sel_setting(struct mipi_tx_regs *mipi_tx_reg);
 void mtk_dsi_cphy_timing(u32 data_rate, struct mtk_phy_timing *timing);
 void mtk_dsi_cphy_vdo_timing(const u32 lanes, const struct edid *edid,
 			     const struct mtk_phy_timing *phy_timing,
 			     const u32 bytes_per_pixel, const u32 hbp, const u32 hfp,
 			     s32 *hbp_byte, s32 *hfp_byte, u32 *hsync_active_byte);
-void mtk_dsi_cphy_disable_ck_mode(void);
-void mtk_dsi_dphy_disable_ck_mode(void);
+void mtk_dsi_cphy_disable_ck_mode(struct mipi_tx_regs *mipi_tx_reg);
+void mtk_dsi_dphy_disable_ck_mode(struct mipi_tx_regs *mipi_tx_reg);
 void mtk_dsi_dphy_timing_calculation(u32 data_rate_mhz, struct mtk_phy_timing *timing);
-void mtk_dsi_configure_mipi_tx(u32 data_rate, u32 lanes, bool is_cphy);
+void mtk_dsi_configure_mipi_tx(struct mipi_tx_regs *mipi_tx_reg,
+			       u32 data_rate, u32 lanes, bool is_cphy);
 
 #endif /* SOC_MEDIATEK_DSI_COMMON_H */
diff --git a/src/soc/mediatek/common/mtk_mipi_cphy.c b/src/soc/mediatek/common/mtk_mipi_cphy.c
index 8578d84e4e..3e78376951 100644
--- a/src/soc/mediatek/common/mtk_mipi_cphy.c
+++ b/src/soc/mediatek/common/mtk_mipi_cphy.c
@@ -17,29 +17,29 @@
 #define MIPITX_CPHY_LANE_SEL2_SETTING	0x68543102
 #define MIPITX_CPHY_LANE_SEL3_SETTING	0x00000007
 
-void mtk_dsi_cphy_lane_sel_setting(void)
+void mtk_dsi_cphy_lane_sel_setting(struct mipi_tx_regs *mipi_tx_reg)
 {
-	write32(&mipi_tx0->phy_sel[0], MIPITX_CPHY_LANE_SEL0_SETTING);
-	write32(&mipi_tx0->phy_sel[1], MIPITX_CPHY_LANE_SEL1_SETTING);
-	write32(&mipi_tx0->phy_sel[2], MIPITX_CPHY_LANE_SEL2_SETTING);
-	write32(&mipi_tx0->phy_sel[3], MIPITX_CPHY_LANE_SEL3_SETTING);
+	write32(&mipi_tx_reg->phy_sel[0], MIPITX_CPHY_LANE_SEL0_SETTING);
+	write32(&mipi_tx_reg->phy_sel[1], MIPITX_CPHY_LANE_SEL1_SETTING);
+	write32(&mipi_tx_reg->phy_sel[2], MIPITX_CPHY_LANE_SEL2_SETTING);
+	write32(&mipi_tx_reg->phy_sel[3], MIPITX_CPHY_LANE_SEL3_SETTING);
 }
 
-void mtk_dsi_cphy_enable(void)
+void mtk_dsi_cphy_enable(struct mipi_tx_regs *mipi_tx_reg)
 {
-	setbits32(&mipi_tx0->lane_con, DSI_CPHY_EN);
+	setbits32(&mipi_tx_reg->lane_con, DSI_CPHY_EN);
 }
 
-void mtk_dsi_cphy_disable_ck_mode(void)
+void mtk_dsi_cphy_disable_ck_mode(struct mipi_tx_regs *mipi_tx_reg)
 {
-	clrsetbits32(&mipi_tx0->voltage_sel, DSI_HSTX_LDO_REF_SEL, 0xF << 6);
-	clrbits32(&mipi_tx0->ck_ckmode_en, DSI_CK_CKMODE_EN);
-	setbits32(&mipi_tx0->lane_con, DE_EMPHASIS_EN);
+	clrsetbits32(&mipi_tx_reg->voltage_sel, DSI_HSTX_LDO_REF_SEL, 0xF << 6);
+	clrbits32(&mipi_tx_reg->ck_ckmode_en, DSI_CK_CKMODE_EN);
+	setbits32(&mipi_tx_reg->lane_con, DE_EMPHASIS_EN);
 }
 
-void mtk_dsi_cphy_enable_cmdq_6byte(void)
+void mtk_dsi_cphy_enable_cmdq_6byte(struct dsi_regs *dsi_reg)
 {
-	clrbits32(&dsi0->dsi_cmd_type1_hs, CMD_CPHY_6BYTE_EN);
+	clrbits32(&dsi_reg->dsi_cmd_type1_hs, CMD_CPHY_6BYTE_EN);
 }
 
 void mtk_dsi_cphy_timing(u32 data_rate, struct mtk_phy_timing *timing)
diff --git a/src/soc/mediatek/common/mtk_mipi_dphy.c b/src/soc/mediatek/common/mtk_mipi_dphy.c
index 3ebaa40109..6f161002db 100644
--- a/src/soc/mediatek/common/mtk_mipi_dphy.c
+++ b/src/soc/mediatek/common/mtk_mipi_dphy.c
@@ -3,7 +3,7 @@
 #include <device/mmio.h>
 #include <soc/dsi.h>
 
-void mtk_dsi_dphy_disable_ck_mode(void)
+void mtk_dsi_dphy_disable_ck_mode(struct mipi_tx_regs *mipi_tx_reg)
 {
-	setbits32(&mipi_tx0->ck_ckmode_en, DSI_CK_CKMODE_EN);
+	setbits32(&mipi_tx_reg->ck_ckmode_en, DSI_CK_CKMODE_EN);
 }
diff --git a/src/soc/mediatek/mt8173/dsi.c b/src/soc/mediatek/mt8173/dsi.c
index 3e87ba448a..8c1b02d3d6 100644
--- a/src/soc/mediatek/mt8173/dsi.c
+++ b/src/soc/mediatek/mt8173/dsi.c
@@ -7,14 +7,15 @@
 #include <soc/dsi.h>
 #include <timer.h>
 
-void mtk_dsi_configure_mipi_tx(u32 data_rate, u32 lanes, bool is_cphy)
+void mtk_dsi_configure_mipi_tx(struct mipi_tx_regs *mipi_tx_reg, u32 data_rate,
+			       u32 lanes, bool is_cphy)
 {
 	u32 txdiv0, txdiv1;
 	u64 pcw;
 	u32 reg;
 	int i;
 
-	reg = read32(&mipi_tx0->dsi_bg_con);
+	reg = read32(&mipi_tx_reg->dsi_bg_con);
 
 	reg = (reg & (~RG_DSI_V02_SEL)) | (4 << 20);
 	reg = (reg & (~RG_DSI_V032_SEL)) | (4 << 17);
@@ -24,19 +25,19 @@ void mtk_dsi_configure_mipi_tx(u32 data_rate, u32 lanes, bool is_cphy)
 	reg = (reg & (~RG_DSI_V12_SEL)) | (4 << 5);
 	reg |= RG_DSI_BG_CKEN;
 	reg |= RG_DSI_BG_CORE_EN;
-	write32(&mipi_tx0->dsi_bg_con, reg);
+	write32(&mipi_tx_reg->dsi_bg_con, reg);
 	udelay(30);
 
-	clrsetbits32(&mipi_tx0->dsi_top_con, RG_DSI_LNT_IMP_CAL_CODE,
+	clrsetbits32(&mipi_tx_reg->dsi_top_con, RG_DSI_LNT_IMP_CAL_CODE,
 		     8 << 4 | RG_DSI_LNT_HS_BIAS_EN);
 
-	setbits32(&mipi_tx0->dsi_con,
+	setbits32(&mipi_tx_reg->dsi_con,
 		  RG_DSI0_CKG_LDOOUT_EN | RG_DSI0_LDOCORE_EN);
 
-	clrsetbits32(&mipi_tx0->dsi_pll_pwr, RG_DSI_MPPLL_SDM_ISO_EN,
+	clrsetbits32(&mipi_tx_reg->dsi_pll_pwr, RG_DSI_MPPLL_SDM_ISO_EN,
 		     RG_DSI_MPPLL_SDM_PWR_ON);
 
-	clrbits32(&mipi_tx0->dsi_pll_con0, RG_DSI0_MPPLL_PLL_EN);
+	clrbits32(&mipi_tx_reg->dsi_pll_con0, RG_DSI0_MPPLL_PLL_EN);
 
 	if (data_rate > 500 * MHz) {
 		txdiv0 = 0;
@@ -57,7 +58,7 @@ void mtk_dsi_configure_mipi_tx(u32 data_rate, u32 lanes, bool is_cphy)
 		txdiv1 = 2;
 	}
 
-	clrsetbits32(&mipi_tx0->dsi_pll_con0,
+	clrsetbits32(&mipi_tx_reg->dsi_pll_con0,
 		     RG_DSI0_MPPLL_TXDIV1 | RG_DSI0_MPPLL_TXDIV0 |
 		     RG_DSI0_MPPLL_PREDIV, txdiv1 << 5 | txdiv0 << 3);
 
@@ -71,27 +72,27 @@ void mtk_dsi_configure_mipi_tx(u32 data_rate, u32 lanes, bool is_cphy)
 	 */
 	pcw = (u64)(data_rate * (1 << txdiv0) * (1 << txdiv1)) << 24;
 	pcw /= 13 * MHz;
-	write32(&mipi_tx0->dsi_pll_con2, pcw);
+	write32(&mipi_tx_reg->dsi_pll_con2, pcw);
 
-	setbits32(&mipi_tx0->dsi_pll_con1, RG_DSI0_MPPLL_SDM_FRA_EN);
+	setbits32(&mipi_tx_reg->dsi_pll_con1, RG_DSI0_MPPLL_SDM_FRA_EN);
 
-	setbits32(&mipi_tx0->dsi_clock_lane, LDOOUT_EN);
+	setbits32(&mipi_tx_reg->dsi_clock_lane, LDOOUT_EN);
 
 	for (i = 0; i < lanes; i++)
-		setbits32(&mipi_tx0->dsi_data_lane[i], LDOOUT_EN);
+		setbits32(&mipi_tx_reg->dsi_data_lane[i], LDOOUT_EN);
 
-	setbits32(&mipi_tx0->dsi_pll_con0, RG_DSI0_MPPLL_PLL_EN);
+	setbits32(&mipi_tx_reg->dsi_pll_con0, RG_DSI0_MPPLL_PLL_EN);
 
 	udelay(40);
 
-	clrbits32(&mipi_tx0->dsi_pll_con1, RG_DSI0_MPPLL_SDM_SSC_EN);
-	clrbits32(&mipi_tx0->dsi_top_con, RG_DSI_PAD_TIE_LOW_EN);
+	clrbits32(&mipi_tx_reg->dsi_pll_con1, RG_DSI0_MPPLL_SDM_SSC_EN);
+	clrbits32(&mipi_tx_reg->dsi_top_con, RG_DSI_PAD_TIE_LOW_EN);
 }
 
-void mtk_dsi_reset(void)
+void mtk_dsi_reset(struct dsi_regs *dsi_reg)
 {
-	setbits32(&dsi0->dsi_con_ctrl, 3);
-	clrbits32(&dsi0->dsi_con_ctrl, 1);
+	setbits32(&dsi_reg->dsi_con_ctrl, 3);
+	clrbits32(&dsi_reg->dsi_con_ctrl, 1);
 }
 
 void mtk_dsi_override_phy_timing(struct mtk_phy_timing *timing)

From d556bc65c244f968f38dd9bcad58b3b23c4b7fbd Mon Sep 17 00:00:00 2001
From: "luca.lai" <luca.lai@lcfc.corp-partner.google.com>
Date: Thu, 11 Dec 2025 17:15:43 +0800
Subject: [PATCH 2794/3886] mb/google/fatcat/var/ruby: Change GPIO pins to fix
 audio function

Change below GPIO pins status to fix audio function.
GPP_H19 : Native function 1
GPP_H20 : Native function 1

BUG=b:466263099
TEST=Build and boot to OS, check soundcard shows using command
'cat /proc/asound/cards' and check audio jack and amp are work.

Change-Id: I1771d063d8f15fef672119f56482d7cf3c954c27
Signed-off-by: luca.lai <luca.lai@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90455
Reviewed-by: Derek Huang <derekhuang@google.com>
Reviewed-by: YH Lin <yueherngl@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
---
 src/mainboard/google/fatcat/variants/ruby/gpio.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/mainboard/google/fatcat/variants/ruby/gpio.c b/src/mainboard/google/fatcat/variants/ruby/gpio.c
index b404a66082..6324a5d9b8 100644
--- a/src/mainboard/google/fatcat/variants/ruby/gpio.c
+++ b/src/mainboard/google/fatcat/variants/ruby/gpio.c
@@ -321,9 +321,9 @@ static const struct pad_config gpio_table[] = {
 	/* GPP_H17:     SOC_HP_INT_L */
 	PAD_CFG_GPI_INT(GPP_H17, NONE, PLTRST, EDGE_BOTH),
 	/* GPP_H19:     I3C0_SDA_HDR */
-	PAD_CFG_NF(GPP_H19, NONE, DEEP, NF2),
+	PAD_CFG_NF(GPP_H19, NONE, DEEP, NF1),
 	/* GPP_H20:     I3C0_SCL_HDR */
-	PAD_CFG_NF(GPP_H20, NONE, DEEP, NF2),
+	PAD_CFG_NF(GPP_H20, NONE, DEEP, NF1),
 	/* GPP_H21:     CAL_SDA_IN */
 	PAD_CFG_NF(GPP_H21, NONE, DEEP, NF1),
 	/* GPP_H22:     CAL_SCL_IN */

From 8f34fdfab3ac0ec76e7600222310afb0b18c26d0 Mon Sep 17 00:00:00 2001
From: Julius Werner <jwerner@chromium.org>
Date: Tue, 9 Dec 2025 11:34:18 -0800
Subject: [PATCH 2795/3886] Remove <swab.h> and swabXX() functions

GCC generates correct code for __builtin_bswapXX() on all architectures,
including ArmV4. It seems that whatever bug caused this to not work back
in commit 879ea7fce8a2 ("endian: Replace explicit byte swapping with
compiler builtin") has been fixed now. We can eliminate the swabXX()
functions and simplify the code.

All instances that had been calling these functions directly should have
been using real endianness conversions anyway.

Change-Id: I19713fd009aa5c0e01c4a42e0cf012364d6bed60
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90438
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
---
 payloads/libpayload/include/endian.h          |  4 --
 .../bsd/include/commonlib/bsd/_endian.h       | 16 +++---
 src/ec/clevo/it5570e/commands.c               |  4 +-
 src/include/endian.h                          |  1 -
 src/include/swab.h                            | 55 -------------------
 src/mainboard/prodrive/hermes/eeprom.c        |  3 +-
 .../amd/common/psp_verstage/vboot_crypto.c    |  6 +-
 src/vendorcode/eltan/security/mboot/mboot.c   |  3 +-
 src/vendorcode/eltan/security/mboot/mboot.h   |  1 -
 9 files changed, 17 insertions(+), 76 deletions(-)
 delete mode 100644 src/include/swab.h

diff --git a/payloads/libpayload/include/endian.h b/payloads/libpayload/include/endian.h
index 46e5dfe6eb..31d5f4f900 100644
--- a/payloads/libpayload/include/endian.h
+++ b/payloads/libpayload/include/endian.h
@@ -34,10 +34,6 @@
 #include <libpayload-config.h>
 #include <string.h>
 
-#define swab16(x) __builtin_bswap16(x)
-#define swab32(x) __builtin_bswap32(x)
-#define swab64(x) __builtin_bswap64(x)
-
 #if CONFIG(LP_BIG_ENDIAN)
 #define __BIG_ENDIAN
 #elif CONFIG(LP_LITTLE_ENDIAN)
diff --git a/src/commonlib/bsd/include/commonlib/bsd/_endian.h b/src/commonlib/bsd/include/commonlib/bsd/_endian.h
index d0d5be9f9f..d3fa661060 100644
--- a/src/commonlib/bsd/include/commonlib/bsd/_endian.h
+++ b/src/commonlib/bsd/include/commonlib/bsd/_endian.h
@@ -5,8 +5,8 @@
 
 /*
  * This header should not be included directly. Including source must define
- * prerequisites like uintXX_t types, the byteswap functions swabXX(),
- * __BIG_ENDIAN or __LITTLE_ENDIAN and I/O accessors readXX()/writeXX().
+ * prerequisites like uintXX_t types, __BIG_ENDIAN or __LITTLE_ENDIAN and
+ * I/O accessors readXX()/writeXX().
  */
 
 /* Endian functions from glibc 2.9 / BSD "endian.h" */
@@ -15,13 +15,13 @@
 	#define htobe16(in) (in)
 	#define htobe32(in) (in)
 	#define htobe64(in) (in)
-	#define htole16(in) ((uint16_t)swab16(in))
-	#define htole32(in) ((uint32_t)swab32(in))
-	#define htole64(in) ((uint64_t)swab64(in))
+	#define htole16(in) ((uint16_t)__builtin_bswap16(in))
+	#define htole32(in) ((uint32_t)__builtin_bswap32(in))
+	#define htole64(in) ((uint64_t)__builtin_bswap64(in))
 #elif defined(__LITTLE_ENDIAN)
-	#define htobe16(in) ((uint16_t)swab16(in))
-	#define htobe32(in) ((uint32_t)swab32(in))
-	#define htobe64(in) ((uint64_t)swab64(in))
+	#define htobe16(in) ((uint16_t)__builtin_bswap16(in))
+	#define htobe32(in) ((uint32_t)__builtin_bswap32(in))
+	#define htobe64(in) ((uint64_t)__builtin_bswap64(in))
 	#define htole16(in) (in)
 	#define htole32(in) (in)
 	#define htole64(in) (in)
diff --git a/src/ec/clevo/it5570e/commands.c b/src/ec/clevo/it5570e/commands.c
index 8f53bb18c8..d5f08a4a23 100644
--- a/src/ec/clevo/it5570e/commands.c
+++ b/src/ec/clevo/it5570e/commands.c
@@ -3,7 +3,7 @@
 #include <console/console.h>
 #include <device/mmio.h>
 #include <ec/acpi/ec.h>
-#include <swab.h>
+#include <endian.h>
 #include <timer.h>
 #include <types.h>
 
@@ -102,7 +102,7 @@ void ec_set_kbled_timeout(uint16_t timeout)
 	printk(BIOS_DEBUG, "EC: set keyboard backlight timeout to %us\n", timeout);
 
 	write8p(ECRAM + FDAT, timeout ? 0xff : 0x00);
-	write16p(ECRAM + FBUF, swab16(timeout));
+	write16p(ECRAM + FBUF, htobe16(timeout));
 	ec_fcmd(FCMD_SET_KBLED_TIMEOUT);
 }
 
diff --git a/src/include/endian.h b/src/include/endian.h
index efc56dd7be..7300ae839f 100644
--- a/src/include/endian.h
+++ b/src/include/endian.h
@@ -6,7 +6,6 @@
 #include <arch/byteorder.h>
 #include <stdint.h>
 #include <string.h>
-#include <swab.h>
 
 /* This include depends on previous ones, do not reorder. */
 #include <commonlib/bsd/_endian.h>
diff --git a/src/include/swab.h b/src/include/swab.h
deleted file mode 100644
index eadf293745..0000000000
--- a/src/include/swab.h
+++ /dev/null
@@ -1,55 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-/*
- * linux/byteorder/swab.h
- * Byte-swapping, independently from CPU endianness
- *	swabXX[ps]?(foo)
- *
- * Francois-Rene Rideau <fare@tunes.org> 19971205
- *    separated swab functions from cpu_to_XX,
- *    to clean up support for bizarre-endian architectures.
- *
- * See asm-i386/byteorder.h and such for examples of how to provide
- * architecture-dependent optimized versions
- *
- */
-
-/* casts are necessary for constants, because we never know how for sure
- * how U/UL/ULL map to __u16, __u32, __u64. At least not in a portable way.
- */
-
-#ifndef _SWAB_H
-#define _SWAB_H
-
-#include <stdint.h>
-
-#if ENV_ARMV4
-#define swab16(x) \
-	((unsigned short)( \
-		(((unsigned short)(x) & (unsigned short)0x00ffU) << 8) | \
-		(((unsigned short)(x) & (unsigned short)0xff00U) >> 8)))
-
-#define swab32(x) \
-	((unsigned int)( \
-		(((unsigned int)(x) & 0x000000ffUL) << 24) | \
-		(((unsigned int)(x) & 0x0000ff00UL) <<  8) | \
-		(((unsigned int)(x) & 0x00ff0000UL) >>  8) | \
-		(((unsigned int)(x) & 0xff000000UL) >> 24)))
-
-#define swab64(x) \
-	((uint64_t)( \
-		(((uint64_t)(x) & (uint64_t)0x00000000000000ffULL) << 56) | \
-		(((uint64_t)(x) & (uint64_t)0x000000000000ff00ULL) << 40) | \
-		(((uint64_t)(x) & (uint64_t)0x0000000000ff0000ULL) << 24) | \
-		(((uint64_t)(x) & (uint64_t)0x00000000ff000000ULL) <<  8) | \
-		(((uint64_t)(x) & (uint64_t)0x000000ff00000000ULL) >>  8) | \
-		(((uint64_t)(x) & (uint64_t)0x0000ff0000000000ULL) >> 24) | \
-		(((uint64_t)(x) & (uint64_t)0x00ff000000000000ULL) >> 40) | \
-		(((uint64_t)(x) & (uint64_t)0xff00000000000000ULL) >> 56)))
-#else	/* ENV_ARMV4 */
-#define swab16(x) ((uint16_t)__builtin_bswap16(x))
-#define swab32(x) ((uint32_t)__builtin_bswap32(x))
-#define swab64(x) ((uint64_t)__builtin_bswap64(x))
-#endif	/* !ENV_ARMV4 */
-
-#endif /* _SWAB_H */
diff --git a/src/mainboard/prodrive/hermes/eeprom.c b/src/mainboard/prodrive/hermes/eeprom.c
index c0e9cb6648..685b7a6372 100644
--- a/src/mainboard/prodrive/hermes/eeprom.c
+++ b/src/mainboard/prodrive/hermes/eeprom.c
@@ -6,6 +6,7 @@
 #include <delay.h>
 #include <device/pci_ops.h>
 #include <device/smbus_host.h>
+#include <endian.h>
 #include <soc/intel/common/block/smbus/smbuslib.h>
 #include <string.h>
 #include <types.h>
@@ -163,7 +164,7 @@ bool eeprom_read_buffer(void *blob, size_t read_offset, size_t size)
 		u8 tmp[2] = {0};
 
 		ret = do_smbus_process_call(SMBUS_IO_BASE, I2C_ADDR_EEPROM, 0,
-			swab16(read_offset + i), (uint16_t *)&tmp[0]);
+			htobe16(read_offset + i), (uint16_t *)&tmp[0]);
 		if (ret < 0)
 			break;
 
diff --git a/src/soc/amd/common/psp_verstage/vboot_crypto.c b/src/soc/amd/common/psp_verstage/vboot_crypto.c
index 370416f8f7..bc094349e3 100644
--- a/src/soc/amd/common/psp_verstage/vboot_crypto.c
+++ b/src/soc/amd/common/psp_verstage/vboot_crypto.c
@@ -5,11 +5,11 @@
 #include <bl_uapp/bl_syscall_public.h>
 #include <commonlib/bsd/helpers.h>
 #include <console/console.h>
+#include <endian.h>
 #include "psp_verstage.h"
 #include <soc/psp_verstage_addr.h>
 #include <stddef.h>
 #include <string.h>
-#include <swab.h>
 #include <symbols.h>
 #include <vb2_api.h>
 
@@ -161,7 +161,7 @@ vb2_error_t vb2ex_hwcrypto_modexp(const struct vb2_public_key *key,
 		return VB2_ERROR_WORKBUF_SMALL;
 
 	for (i = 0; i < key->arrsize; i++)
-		sig_swapped[i] = swab32(inout_32[key->arrsize - i - 1]);
+		sig_swapped[i] = be32toh(inout_32[key->arrsize - i - 1]);
 
 	mod_exp_param.pExponent = (char *)&exp;
 	mod_exp_param.ExpSize = sizeof(exp);
@@ -179,7 +179,7 @@ vb2_error_t vb2ex_hwcrypto_modexp(const struct vb2_public_key *key,
 
 	/* vboot expects results in *inout with BE, so copy & convert. */
 	for (i = 0; i < key->arrsize; i++)
-		inout_32[i] = swab32(output_buffer[key->arrsize - i - 1]);
+		inout_32[i] = htobe32(output_buffer[key->arrsize - i - 1]);
 
 	return VB2_SUCCESS;
 }
diff --git a/src/vendorcode/eltan/security/mboot/mboot.c b/src/vendorcode/eltan/security/mboot/mboot.c
index 9cdd0de2fe..fa513007cc 100644
--- a/src/vendorcode/eltan/security/mboot/mboot.c
+++ b/src/vendorcode/eltan/security/mboot/mboot.c
@@ -3,6 +3,7 @@
 #include <mboot.h>
 #include <assert.h>
 #include <build.h>
+#include <endian.h>
 #include <vb2_api.h>
 #include <board_mboot.h>
 
@@ -87,7 +88,7 @@ tpm_result_t tpm2_get_capability_pcrs(TPML_PCR_SELECTION *Pcrs)
 		printk(BIOS_DEBUG, "Pcrs->count = %d\n", Pcrs->count);
 		for (index = 0; index < Pcrs->count; index++) {
 			Pcrs->pcrSelections[index].hash =
-				swab16(TpmCap.data.assignedPCR.pcrSelections[index].hash);
+				be16toh(TpmCap.data.assignedPCR.pcrSelections[index].hash);
 			printk(BIOS_DEBUG, "Pcrs->pcrSelections[%d].hash = %#x\n", index,
 			       Pcrs->pcrSelections[index].hash);
 			Pcrs->pcrSelections[index].sizeofSelect =
diff --git a/src/vendorcode/eltan/security/mboot/mboot.h b/src/vendorcode/eltan/security/mboot/mboot.h
index 20333fc1b1..b8510ac47e 100644
--- a/src/vendorcode/eltan/security/mboot/mboot.h
+++ b/src/vendorcode/eltan/security/mboot/mboot.h
@@ -12,7 +12,6 @@
 #include <boot/coreboot_tables.h>
 #include <security/tpm/tss/tcg-2.0/tss_structures.h>
 #include <security/tpm/tss.h>
-#include <swab.h>
 
 /* TPM2 interface */
 #define EFI_TPM2_ACPI_TABLE_START_METHOD_TIS	6

From 35cb6aea509830b6ed2d6ecc7a04460edab03195 Mon Sep 17 00:00:00 2001
From: Alicja Michalska <alicja.michalska@9elements.com>
Date: Fri, 12 Dec 2025 02:35:42 +0100
Subject: [PATCH 2796/3886] mb/google/hatch: Fix CFR pointer

Typo in CFR causes build failure, this patch fixes it.

TEST: Build for KOHAKU with EDK2 payload and CFR options.

Change-Id: If17e12ad7f99e65d7b9037f0e8e599490cecb6a4
Signed-off-by: Alicja Michalska <alicja.michalska@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90483
Reviewed-by: Ingo Reitz <9l@9lo.re>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/google/hatch/cfr.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/mainboard/google/hatch/cfr.c b/src/mainboard/google/hatch/cfr.c
index 855b08d488..2de1ebbb7c 100644
--- a/src/mainboard/google/hatch/cfr.c
+++ b/src/mainboard/google/hatch/cfr.c
@@ -29,7 +29,7 @@ static struct sm_obj_form system = {
 static struct sm_obj_form ec = {
 	.ui_name = "ChromeEC Embedded Controller",
 	.obj_list = (const struct sm_object *[]) {
-		auto_fan_control,
+		&auto_fan_control,
 		&ec_kb_backlight,
 		NULL
 	},

From 510f1950b425bdd117fc739242359f02a3891963 Mon Sep 17 00:00:00 2001
From: "chou.pierce" <chou.pierce@inventec.corp-partner.google.com>
Date: Fri, 5 Dec 2025 15:33:09 +0800
Subject: [PATCH 2797/3886] mb/google/ocelot/var/ocicat: Update devicetree

- Enable CNVi Wi-Fi and BT cores
- Remove unused tbt_pcie_rp0/rp1 nodes

BUG=b:466246282
TEST=CNVi Wifi/BT is enabled on ocicat.

Change-Id: Ibeee5c83f35df1637d0284f96bf5e715eac4efbd
Signed-off-by: chou.pierce <chou.pierce@inventec.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90380
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
---
 .../ocelot/variants/ocicat/overridetree.cb    | 47 +++++++++++++++----
 1 file changed, 37 insertions(+), 10 deletions(-)

diff --git a/src/mainboard/google/ocelot/variants/ocicat/overridetree.cb b/src/mainboard/google/ocelot/variants/ocicat/overridetree.cb
index 99a73e6956..be41823ce6 100644
--- a/src/mainboard/google/ocelot/variants/ocicat/overridetree.cb
+++ b/src/mainboard/google/ocelot/variants/ocicat/overridetree.cb
@@ -1,7 +1,12 @@
 fw_config
-	field STORAGE 13 14
-		option STORAGE_UNKNOWN			0
-		option STORAGE_NVME_GEN4		1
+	field WIFI 2 4
+		option WIFI_NONE			0
+		option WIFI_CNVI_7			1
+		option WIFI_PCIE_7			2
+	end
+	field STORAGE_TYPE 12 14
+		option STORAGE_TYPE_UNKNOWN		0
+		option STORAGE_TYPE_NVME_GEN4		1
 		option STORAGE_UFS			2
 	end
 end
@@ -30,6 +35,10 @@ chip soc/intel/pantherlake
 		[DDI_PORT_B] = DDI_ENABLE_HPD | DDI_ENABLE_DDC,
 	}"
 
+	# Enable CNVi Wi-Fi and Bluetooth
+	register "cnvi_wifi_core" = "true"
+	register "cnvi_bt_core" = "true"
+
 	register "serial_io_i2c_mode" = "{
 		[PchSerialIoIndexI2C0]  = PchSerialIoPci,
 		[PchSerialIoIndexI2C1]  = PchSerialIoPci,
@@ -255,8 +264,6 @@ chip soc/intel/pantherlake
 			end
 		end
 
-		device ref tbt_pcie_rp0 on end
-		device ref tbt_pcie_rp1 on end
 		device ref tcss_xhci on
 			chip drivers/usb/acpi
 				device ref tcss_root_hub on
@@ -313,7 +320,10 @@ chip soc/intel/pantherlake
 						register "desc" = ""USB2 Bluetooth""
 						register "type" = "UPC_TYPE_INTERNAL"
 						register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B09)"
-						device ref usb2_port8 on end
+						device ref usb2_port8 on
+							probe WIFI WIFI_PCIE_7
+	                                	end
+
 					end
 					chip drivers/usb/acpi
 						register "desc" = ""USB3 Type-A Port 1""
@@ -326,13 +336,13 @@ chip soc/intel/pantherlake
 		end
 
 		device ref ufs on
-			probe STORAGE STORAGE_UFS
-			probe STORAGE STORAGE_UNKNOWN
+			probe STORAGE_TYPE STORAGE_UFS
+			probe STORAGE_TYPE STORAGE_TYPE_UNKNOWN
 		end
 
 		device ref pcie_rp1 on
-			probe STORAGE STORAGE_NVME_GEN4
-			probe STORAGE STORAGE_UNKNOWN
+			probe STORAGE_TYPE STORAGE_TYPE_NVME_GEN4
+			probe STORAGE_TYPE STORAGE_TYPE_UNKNOWN
 			register "pcie_rp[PCIE_RP(1)]" = "{
 			.clk_src = 3,
 			.clk_req = 3,
@@ -347,6 +357,15 @@ chip soc/intel/pantherlake
 			end
 		end # Gen4 M.2 SSD
 
+		device ref pcie_rp5 on
+			probe WIFI WIFI_PCIE_7
+			register "pcie_rp[PCIE_RP(5)]" = "{
+			.clk_src = 0,
+			.clk_req = 0,
+			.flags = PCIE_RP_CLK_REQ_DETECT | PCIE_RP_LTR | PCIE_RP_AER,
+			}"
+		end # M.2 WLAN KEY-E
+
 		device ref cnvi_wifi on
 			chip drivers/wifi/generic
 				register "wake" = "GPE0_PME_B0"
@@ -357,6 +376,14 @@ chip soc/intel/pantherlake
 			end
 		end # CNVi
 
+		device ref cnvi_bluetooth on
+			probe WIFI WIFI_CNVI_7
+			chip soc/intel/common/block/cnvi
+				register "wake" = "GPE0_PME_B0"
+				device generic 0 on end
+			end
+		end
+
 		# NOTE: i2c0 is function 0; hence it needs to be enabled when any of i2c1-5 is enabled.
 		# TPM device is under i2c1. Therefore, i2c0 needs to be enabled anyways.
 		device ref i2c0 on end

From 4f78a40f53fe53fda0d14e3d760c8584f0e8a69f Mon Sep 17 00:00:00 2001
From: "chou.pierce" <chou.pierce@inventec.corp-partner.google.com>
Date: Wed, 10 Dec 2025 10:58:31 +0800
Subject: [PATCH 2798/3886] mb/google/ocelot/var/ocicat: Update Touchscreen
 settings

- Update Touchscreen settings
- Modify GPP_F16 to output pin
- Modify GPP_F18 to INT pin

BUG=b:466246282
TEST=Flash and boot on DUT, touchscreen works normally

Change-Id: I6d9ba83993321e59a677d1341fd4255084e68215
Signed-off-by: chou.pierce <chou.pierce@inventec.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90439
Reviewed-by: Pranava Y N <pranavayn@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 .../google/ocelot/variants/ocicat/gpio.c      |  4 +-
 .../ocelot/variants/ocicat/overridetree.cb    | 39 +++++++++++++++----
 2 files changed, 34 insertions(+), 9 deletions(-)

diff --git a/src/mainboard/google/ocelot/variants/ocicat/gpio.c b/src/mainboard/google/ocelot/variants/ocicat/gpio.c
index 3e21608c6d..3a9a7b4ed2 100644
--- a/src/mainboard/google/ocelot/variants/ocicat/gpio.c
+++ b/src/mainboard/google/ocelot/variants/ocicat/gpio.c
@@ -254,11 +254,11 @@ static const struct pad_config gpio_table[] = {
 	/* GPP_F15:     NC */
 	PAD_NC(GPP_F15, NONE),
 	/* GPP_F16:     TCHSCR_RST_ODL */
-	PAD_CFG_NF(GPP_F16, NONE, DEEP, NF3),
+	PAD_CFG_GPO(GPP_F16, 1, DEEP),
 	/* GPP_F17:     NC */
 	PAD_NC(GPP_F17, NONE),
 	/* GPP_F18:     TCHSCR_INT_ODL */
-	PAD_CFG_NF(GPP_F18, NONE, DEEP, NF3),
+	PAD_CFG_GPI_APIC(GPP_F18, NONE, PLTRST, LEVEL, INVERT),
 	/* GPP_F19:     NC */
 	PAD_NC(GPP_F19, NONE),
 	/* GPP_F20:     CSE_EARLY_SW */
diff --git a/src/mainboard/google/ocelot/variants/ocicat/overridetree.cb b/src/mainboard/google/ocelot/variants/ocicat/overridetree.cb
index be41823ce6..ba43e1589e 100644
--- a/src/mainboard/google/ocelot/variants/ocicat/overridetree.cb
+++ b/src/mainboard/google/ocelot/variants/ocicat/overridetree.cb
@@ -9,6 +9,11 @@ fw_config
 		option STORAGE_TYPE_NVME_GEN4		1
 		option STORAGE_UFS			2
 	end
+	field TOUCHSCREEN 17 18
+		option TOUCHSCREEN_UNKNOWN	0
+		option TOUCH_ELAN_TOP	1
+		option TOUCH_ELAN_DBTS	2
+	end
 end
 
 chip soc/intel/pantherlake
@@ -416,22 +421,42 @@ chip soc/intel/pantherlake
 		end # I2C4
 		device ref i2c5 on
 			chip drivers/i2c/hid
-				register "generic.hid" = ""ELAN9004""
+				register "generic.hid" = ""ELAN2513""
 				register "generic.desc" = ""ELAN Touchscreen""
 				register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_F18_IRQ)"
 				register "generic.detect" = "1"
 				register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_F16)"
-				register "generic.reset_delay_ms" = "150"
+				register "generic.reset_delay_ms" = "20"
 				register "generic.reset_off_delay_ms" = "2"
-				register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_F08)"
-				register "generic.enable_delay_ms" = "6"
-				register "generic.enable_off_delay_ms" = "1"
 				register "generic.stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D19)"
+				register "generic.stop_delay_ms" = "280"
 				register "generic.stop_off_delay_ms" = "2"
+				register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_F08)"
+				register "generic.enable_delay_ms" = "1"
 				register "generic.has_power_resource" = "1"
-				register "generic.use_gpio_for_status" = "true"
 				register "hid_desc_reg_offset" = "0x01"
-				device i2c 0x10 on end
+				device i2c 10 on
+					probe TOUCHSCREEN TOUCH_ELAN_TOP
+				end
+			end
+
+			chip drivers/i2c/hid
+				register "generic.hid" = ""ELAN2513""
+				register "generic.desc" = ""ELAN Touchscreen""
+				register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_F18_IRQ)"
+				register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_F16)"
+				register "generic.reset_delay_ms" = "20"
+				register "generic.reset_off_delay_ms" = "2"
+				register "generic.stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D19)"
+				register "generic.stop_delay_ms" = "280"
+				register "generic.stop_off_delay_ms" = "2"
+				register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_F08)"
+				register "generic.enable_delay_ms" = "1"
+				register "generic.has_power_resource" = "1"
+				register "hid_desc_reg_offset" = "0x01"
+				device i2c 15 on
+					probe TOUCHSCREEN TOUCH_ELAN_DBTS
+				end
 			end
 		end # I2C5
 

From 2d45723d87b3bec2812cf34d0785d80194fae3d1 Mon Sep 17 00:00:00 2001
From: Yidi Lin <yidilin@google.com>
Date: Wed, 10 Dec 2025 18:05:43 +0800
Subject: [PATCH 2799/3886] lib/bootmem: Add bootmem_add_range_from function

This patch introduces a new function, bootmem_add_range_from, which
allows adding a memory range of a specific type only if it is carved
out from a range of another specific type. This is useful for cases
where memory needs to be allocated from a pre-defined region.

The function checks if the target range is fully contained within a
range of `from_tag` before marking it as `new_tag`. Error reporting
is included to log cases where the allocation is not possible.

BUG=b:438666196

Change-Id: Icfdb5ef9114572c075be6ef4e57d00151300a17a
Signed-off-by: Yidi Lin <yidilin@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90469
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/include/bootmem.h | 16 ++++++++++++++++
 src/lib/bootmem.c     | 20 ++++++++++++++++++++
 2 files changed, 36 insertions(+)

diff --git a/src/include/bootmem.h b/src/include/bootmem.h
index 5796765ad6..b1352e395b 100644
--- a/src/include/bootmem.h
+++ b/src/include/bootmem.h
@@ -61,6 +61,22 @@ void bootmem_platform_add_ranges(void);
 void bootmem_add_range(uint64_t start, uint64_t size,
 		       const enum bootmem_type tag);
 
+/*
+ * bootmem_add_range_from - Add a memory range of a specific type from another range
+ * @start: Start address of the new memory range
+ * @size: Size of the new memory range
+ * @new_tag: The new bootmem_type for the range
+ * @from_tag: The bootmem_type from which the new range should be carved out
+ *
+ * This function adds a memory range with `new_tag` only if it is fully
+ * contained within an existing range of `from_tag`. This is useful for
+ * carving out specific memory regions from a larger, already defined area.
+ *
+ * Return: 0 on success, or a negative error code on failure.
+ */
+int bootmem_add_range_from(uint64_t start, uint64_t size, const enum bootmem_type new_tag,
+			   const enum bootmem_type from_tag);
+
 /* Print current range map of boot memory. */
 void bootmem_dump_ranges(void);
 
diff --git a/src/lib/bootmem.c b/src/lib/bootmem.c
index ab15e85d08..f8963f3299 100644
--- a/src/lib/bootmem.c
+++ b/src/lib/bootmem.c
@@ -14,6 +14,8 @@ static int table_written;
 static struct memranges bootmem;
 static struct memranges bootmem_os;
 
+static const char *bootmem_range_string(const enum bootmem_type tag);
+
 static int bootmem_is_initialized(void)
 {
 	return initialized;
@@ -106,6 +108,24 @@ void bootmem_add_range(uint64_t start, uint64_t size,
 	};
 }
 
+int bootmem_add_range_from(uint64_t start, uint64_t size, const enum bootmem_type new_tag,
+			   const enum bootmem_type from_tag)
+{
+	if (new_tag == from_tag)
+		return -1;
+
+	if (!bootmem_region_targets_type(start, size, from_tag)) {
+		printk(BIOS_ERR, "%s: Failed to add the range [%#llx, %#llx)"
+		       " from tag %s to %s\n", __func__, start, start + size,
+		       bootmem_range_string(from_tag), bootmem_range_string(new_tag));
+		return -1;
+	}
+
+	bootmem_add_range(start, size, new_tag);
+
+	return 0;
+}
+
 void bootmem_write_memory_table(struct lb_memory *mem)
 {
 	const struct range_entry *r;

From 3d5135fdd070d9121e2914c4f9d2d82a1f9033e6 Mon Sep 17 00:00:00 2001
From: Yidi Lin <yidilin@google.com>
Date: Thu, 11 Dec 2025 12:03:46 +0800
Subject: [PATCH 2800/3886] lib/bootmem: Add memory type for Armv9 MTE tag
 storage

The Armv9-A architecture introduces the Memory Tagging Extension (MTE),
which uses a dedicated memory region for tag storage.

This patch adds a new memory type, BM_MEM_TAG, to allow for the proper
accounting and reservation of this memory region. This ensures that the
payload, e.g. depthcharge, can correctly identify and utilize the tag
storage area.

BUG=b:438666196

Change-Id: I2f6d2b3c2c1a8e1f0e9b2c3d4e5f6a7b8c9d0e1f
Signed-off-by: Yidi Lin <yidilin@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90470
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
---
 src/commonlib/include/commonlib/coreboot_tables.h | 1 +
 src/include/bootmem.h                             | 1 +
 src/lib/bootmem.c                                 | 3 +++
 3 files changed, 5 insertions(+)

diff --git a/src/commonlib/include/commonlib/coreboot_tables.h b/src/commonlib/include/commonlib/coreboot_tables.h
index fa966b5fef..251e2c4491 100644
--- a/src/commonlib/include/commonlib/coreboot_tables.h
+++ b/src/commonlib/include/commonlib/coreboot_tables.h
@@ -143,6 +143,7 @@ struct lb_memory_range {
 #define LB_MEM_NVS		 4	/* ACPI NVS Memory */
 #define LB_MEM_UNUSABLE		 5	/* Unusable address space */
 #define LB_MEM_VENDOR_RSVD	 6	/* Vendor Reserved */
+#define LB_MEM_TAG		 7	/* Armv9 tag storage for MTE */
 #define LB_MEM_TABLE		16    /* Ram configuration tables are kept in */
 #define LB_MEM_SOFT_RESERVED	0xefffffff /* Specific purpose memory */
 };
diff --git a/src/include/bootmem.h b/src/include/bootmem.h
index b1352e395b..6bd2aab9eb 100644
--- a/src/include/bootmem.h
+++ b/src/include/bootmem.h
@@ -29,6 +29,7 @@ enum bootmem_type {
 	BM_MEM_VENDOR_RSVD,	/* Vendor Reserved */
 	BM_MEM_OPENSBI,		/* Risc-V OpenSBI */
 	BM_MEM_BL31,		/* Arm64 BL31 executable */
+	BM_MEM_TAG,		/* Armv9-A tag storage for MTE */
 	BM_MEM_TABLE,		/* Ram configuration tables are kept in */
 	/* Tags below this point are ignored for the OS table. */
 	BM_MEM_OS_CUTOFF = BM_MEM_TABLE,
diff --git a/src/lib/bootmem.c b/src/lib/bootmem.c
index f8963f3299..dbd8450f06 100644
--- a/src/lib/bootmem.c
+++ b/src/lib/bootmem.c
@@ -55,6 +55,8 @@ static uint32_t bootmem_to_lb_tag(const enum bootmem_type tag)
 		return LB_MEM_TABLE;
 	case BM_MEM_SOFT_RESERVED:
 		return LB_MEM_SOFT_RESERVED;
+	case BM_MEM_TAG:
+		return LB_MEM_TAG;
 	default:
 		printk(BIOS_ERR, "Unsupported tag %u\n", tag);
 		return LB_MEM_RESERVED;
@@ -166,6 +168,7 @@ static const struct range_strings type_strings[] = {
 	{ BM_MEM_SOFT_RESERVED, "SOFT RESERVED" },
 	{ BM_MEM_RAMSTAGE, "RAMSTAGE" },
 	{ BM_MEM_PAYLOAD, "PAYLOAD" },
+	{ BM_MEM_TAG, "TAG STORAGE" },
 };
 
 static const char *bootmem_range_string(const enum bootmem_type tag)

From 9203cc827f9881dc7a19b640364510581a299234 Mon Sep 17 00:00:00 2001
From: Yidi Lin <yidilin@google.com>
Date: Thu, 11 Dec 2025 17:13:54 +0800
Subject: [PATCH 2801/3886] soc/mediatek/mt8196: Add MTE tag memory to bootmem

This patch enables MTE (Memory Tagging Extension) for the MediaTek
MT8196 SoC.

During `soc_init`, it calculates the required size and start address for
the MTE tag storage based on the physical DRAM size. It then calls
`booker_mte_init` to initialize the MTE hardware with the calculated
start address.

Later, during memory initialization, `bootmem_platform_add_ranges` uses
`bootmem_add_range_from` to reserve the calculated memory region for
MTE tag storage, preventing it from being used for other purposes.

BUG=b:438666196
TEST=Check cbmem log.
[DEBUG]  booker_mte_init: MTE tag addr 0x460f70000
...
[DEBUG]  17. 0000000460f70000-000000047ffeffff: TAG STORAGE
[DEBUG]  18. 000000047fff0000-000000047fffffff: RESERVED

Change-Id: I7caa4fde4f314261383a68e942b0e3fb06c6184b
Signed-off-by: Yidi Lin <yidilin@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90144
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Chen-Tsung Hsieh <chentsung@google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
---
 src/soc/mediatek/common/dramc_info.c          |  2 +-
 .../mediatek/common/include/soc/dramc_info.h  |  4 ++++
 src/soc/mediatek/mt8196/soc.c                 | 19 ++++++++++++++++++-
 3 files changed, 23 insertions(+), 2 deletions(-)

diff --git a/src/soc/mediatek/common/dramc_info.c b/src/soc/mediatek/common/dramc_info.c
index d64796370f..fc4ab9cc72 100644
--- a/src/soc/mediatek/common/dramc_info.c
+++ b/src/soc/mediatek/common/dramc_info.c
@@ -12,7 +12,7 @@ void reserve_buffer_for_dramc(void)
 {
 	const struct mem_chip_info *mc = cbmem_find(CBMEM_ID_MEM_CHIP_INFO);
 	int i;
-	const uint32_t reserved_size = 64 * KiB;
+	const uint32_t reserved_size = HW_TX_TRACING_BUF_SIZE;
 	uint64_t cbmem_top_addr = cbmem_top();
 	uint64_t reserved_addr;
 	uint64_t rank_size_sum = 0;
diff --git a/src/soc/mediatek/common/include/soc/dramc_info.h b/src/soc/mediatek/common/include/soc/dramc_info.h
index a0be6403e5..77ab0dc140 100644
--- a/src/soc/mediatek/common/include/soc/dramc_info.h
+++ b/src/soc/mediatek/common/include/soc/dramc_info.h
@@ -3,6 +3,10 @@
 #ifndef __SOC_MEDIATEK_COMMON_DRAMC_INFO_H__
 #define __SOC_MEDIATEK_COMMON_DRAMC_INFO_H__
 
+#include <commonlib/bsd/helpers.h>
+
+#define HW_TX_TRACING_BUF_SIZE	(64 * KiB)
+
 void reserve_buffer_for_dramc(void);
 
 #endif	/* __SOC_MEDIATEK_COMMON_DRAMC_INFO_H__ */
diff --git a/src/soc/mediatek/mt8196/soc.c b/src/soc/mediatek/mt8196/soc.c
index 1fbe09025f..bacbe0c2c5 100644
--- a/src/soc/mediatek/mt8196/soc.c
+++ b/src/soc/mediatek/mt8196/soc.c
@@ -19,6 +19,9 @@
 #include <soc/symbols.h>
 #include <symbols.h>
 
+static uint64_t mte_start;
+static size_t mte_size;
+
 void bootmem_platform_add_ranges(void)
 {
 	if (CONFIG(ARM64_BL31_OPTEE_WITH_SMC))
@@ -30,6 +33,8 @@ void bootmem_platform_add_ranges(void)
 	bootmem_add_range((uint64_t)_resv_mem_gpu, REGION_SIZE(resv_mem_gpu), BM_MEM_RESERVED);
 	bootmem_add_range((uint64_t)_resv_mem_gpueb,
 			  REGION_SIZE(resv_mem_gpueb), BM_MEM_RESERVED);
+
+	bootmem_add_range_from(mte_start, mte_size, BM_MEM_TAG, BM_MEM_RAM);
 }
 
 static void soc_read_resources(struct device *dev)
@@ -37,6 +42,18 @@ static void soc_read_resources(struct device *dev)
 	ram_range(dev, 0, (uintptr_t)_dram, sdram_size());
 }
 
+#define MTE_SIZE_ALIGNMENT	(64 * KiB)
+
+static void mte_setup(void)
+{
+	size_t dram_size = sdram_size();
+
+	mte_size = ALIGN_UP(dram_size / 33, MTE_SIZE_ALIGNMENT);
+	mte_start = ALIGN_DOWN((uint64_t)_dram + dram_size - mte_size - HW_TX_TRACING_BUF_SIZE,
+			       MTE_SIZE_ALIGNMENT);
+	booker_mte_init(mte_start);
+}
+
 static void soc_init(struct device *dev)
 {
 	uint32_t storage_type = mainboard_get_storage_type();
@@ -57,7 +74,7 @@ static void soc_init(struct device *dev)
 	 * Registers are only accessible by Secure accesses. Writes to them must occur prior to
 	 * the first non-configuration access targeting the device.
 	 */
-	booker_mte_init(MTE_TAG_ADDR);
+	mte_setup();
 }
 
 static struct device_operations soc_ops = {

From 1e8cea55a068ae5f4f1bd9bf48bfd75b24962094 Mon Sep 17 00:00:00 2001
From: Yidi Lin <yidilin@google.com>
Date: Fri, 12 Dec 2025 12:37:52 +0800
Subject: [PATCH 2802/3886] soc/mediatek/common/emi: Cache SDRAM size

Optimize the `sdram_size` function by caching the calculated SDRAM
size in a static variable. This prevents redundant calls to
`mtk_dram_size()` or `mem_chip_info_total_density_bytes()` if the size
has already been determined, improving performance in scenarios where
`sdram_size` is called multiple times.

BUG=none
TEST=emerege-tanjiro coreboot

Change-Id: I0ca0df80ee9cb781a5bb6d55ee28a2c1153be0ad
Signed-off-by: Yidi Lin <yidilin@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90485
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
---
 src/soc/mediatek/common/emi.c | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/src/soc/mediatek/common/emi.c b/src/soc/mediatek/common/emi.c
index a8163cb14d..c96f10ad5a 100644
--- a/src/soc/mediatek/common/emi.c
+++ b/src/soc/mediatek/common/emi.c
@@ -8,7 +8,10 @@
 size_t sdram_size(void)
 {
 	const struct mem_chip_info *mc;
-	size_t size = 0;
+	static size_t size = 0;
+
+	if (size)
+		return size;
 
 	if (ENV_RAMINIT) {
 		size = mtk_dram_size();

From 9a3818f9b6e7c19d4b8b9b4859d6767f4213c956 Mon Sep 17 00:00:00 2001
From: Yu-Ping Wu <yupingso@chromium.org>
Date: Fri, 12 Dec 2025 12:22:06 +0800
Subject: [PATCH 2803/3886] soc/mediatek/common: Print DRAM calibration status
 as string

Logs such as "DRAM-K: calibration failed: status = 1" give little
information about the failure reason. Add get_status_string() and use it
to print the return status as a string.

Change-Id: If20282f0de7ba8ce884d0016fe8da1dc93a33ea4
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90484
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Chen-Tsung Hsieh <chentsung@google.com>
---
 src/soc/mediatek/common/dramc_param.c         | 21 +++++++++++++++++++
 .../common/include/soc/dramc_param_common.h   |  1 +
 src/soc/mediatek/common/memory.c              |  8 ++++---
 3 files changed, 27 insertions(+), 3 deletions(-)

diff --git a/src/soc/mediatek/common/dramc_param.c b/src/soc/mediatek/common/dramc_param.c
index c596adb208..4e05bc2e73 100644
--- a/src/soc/mediatek/common/dramc_param.c
+++ b/src/soc/mediatek/common/dramc_param.c
@@ -11,6 +11,27 @@ struct dramc_param *get_dramc_param_from_blob(void *blob)
 	return (struct dramc_param *)blob;
 }
 
+static const char *const status_strings[] = {
+	[DRAMC_SUCCESS] = "success",
+	[DRAMC_ERR_INVALID_VERSION] = "invalid version",
+	[DRAMC_ERR_INVALID_SIZE] = "invalid size",
+	[DRAMC_ERR_INVALID_FLAGS] = "invalid flags",
+	[DRAMC_ERR_RECALIBRATE] = "full calibration needed",
+	[DRAMC_ERR_INIT_DRAM] = "calibration error",
+	[DRAMC_ERR_COMPLEX_RW_MEM_TEST] = "mem test failure",
+	[DRAMC_ERR_1ST_COMPLEX_RW_MEM_TEST] = "1st mem test failure",
+	[DRAMC_ERR_2ND_COMPLEX_RW_MEM_TEST] = "2nd mem test failure",
+	[DRAMC_ERR_FAST_CALIBRATION] = "fast calibration error",
+};
+
+const char *get_status_string(u16 status)
+{
+	const char *s = NULL;
+	if (status < ARRAY_SIZE(status_strings))
+		s = status_strings[status];
+	return s ? s : "UNKNOWN STATUS";
+}
+
 void dump_param_header(const void *blob)
 {
 	const struct dramc_param *dparam = blob;
diff --git a/src/soc/mediatek/common/include/soc/dramc_param_common.h b/src/soc/mediatek/common/include/soc/dramc_param_common.h
index 3c72cb55d3..57ee16d7e5 100644
--- a/src/soc/mediatek/common/include/soc/dramc_param_common.h
+++ b/src/soc/mediatek/common/include/soc/dramc_param_common.h
@@ -105,6 +105,7 @@ struct ddr_base_info {
 
 const struct sdram_info *get_sdram_config(void);
 struct dramc_param *get_dramc_param_from_blob(void *blob);
+const char *get_status_string(u16 status);
 void dump_param_header(const void *blob);
 int validate_dramc_param(const void *blob);
 int is_valid_dramc_param(const void *blob);
diff --git a/src/soc/mediatek/common/memory.c b/src/soc/mediatek/common/memory.c
index f08b1d55cf..6408ac03e8 100644
--- a/src/soc/mediatek/common/memory.c
+++ b/src/soc/mediatek/common/memory.c
@@ -172,9 +172,11 @@ static int run_dram_blob(struct dramc_param *dparam)
 
 	prog_set_entry(&dram, prog_entry(&dram), dparam);
 	prog_run(&dram);
-	if (dparam->header.status != DRAMC_SUCCESS) {
-		printk(BIOS_ERR, "DRAM-K: calibration failed: status = %d\n",
-		       dparam->header.status);
+
+	u16 status = dparam->header.status;
+	if (status != DRAMC_SUCCESS) {
+		printk(BIOS_ERR, "DRAM-K: calibration failed: status = %d (%s)\n",
+		       status, get_status_string(status));
 		return -3;
 	}
 

From 0b4d41004db07d1606192822ae5355141ec2704e Mon Sep 17 00:00:00 2001
From: "Johann C. Rode" <jcrode@gmx.net>
Date: Thu, 27 Nov 2025 16:54:52 -0800
Subject: [PATCH 2804/3886] mb/lenovo/sklkbl: Add Lenovo Thinkpad X280 as a
 variant

The hardware of this machine is mostly identical to the already
supported Thinkpad Tx80 machines. Minor differences are the absence of
SODIMM slots (i.e. all RAM is soldered on), two fewer eDP lane pairs,
and different PCIe lane assignment.

All the hardware configuration settings (VBT, GPIO register dumps,
hda verbs, and so on) have been obtained running the latest BIOS/EC
firmware (1.59/N20ET74W, 1.15/N20HT28W). PCIe port assignments as well
as USB, RAM SPD and GPIO assignments have been cross-checked against
publicly available schematics (Finn-1).

Basic functionality has been validated on a Thinkpad X280 part number
20KF-002QUS with 16GB onboard RAM, i7-8650U CPU. The laptop has been
tested with SeaBIOS 1.17 as a payload booting either debian 13 or
Windows 10. A cursory check of the hardware (video, wifi, audio, wired
ethernet, reboot, sleep) shows no issues. This patch also includes a
fix for the headphone jack detection that's been already validated
on the Thinkpad T480 with commit e5d10e5d23d3 ("mb/lenovo/t480: Fix
headphone jack").

Change-Id: Ia8e6c40b200dee240d08d79253fbbe0842882a80
Signed-off-by: Johann C. Rode <jcrode@gmx.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90254
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 Documentation/mainboard/index.md              |   2 +-
 Documentation/mainboard/lenovo/skylake.md     |  32 ++-
 src/mainboard/lenovo/sklkbl_thinkpad/Kconfig  |  14 +-
 .../lenovo/sklkbl_thinkpad/Kconfig.name       |   3 +
 .../lenovo/sklkbl_thinkpad/Makefile.mk        |   5 +
 .../sklkbl_thinkpad/variants/x280/data.vbt    | Bin 0 -> 6144 bytes
 .../variants/x280/gma-mainboard.ads           |  19 ++
 .../sklkbl_thinkpad/variants/x280/gpio.c      | 200 ++++++++++++++++++
 .../sklkbl_thinkpad/variants/x280/hda_verb.c  | 124 +++++++++++
 .../variants/x280/memory/Makefile.mk          |  22 ++
 .../x280/memory/dram_id.generated.txt         |  22 ++
 .../variants/x280/memory/mem_parts_used.txt   |  16 ++
 .../variants/x280/memory_init_params.c        |  57 +++++
 .../variants/x280/overridetree.cb             |  85 ++++++++
 14 files changed, 593 insertions(+), 8 deletions(-)
 create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/x280/data.vbt
 create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/x280/gma-mainboard.ads
 create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/x280/gpio.c
 create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/x280/hda_verb.c
 create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/x280/memory/Makefile.mk
 create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/x280/memory/dram_id.generated.txt
 create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/x280/memory/mem_parts_used.txt
 create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/x280/memory_init_params.c
 create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/x280/overridetree.cb

diff --git a/Documentation/mainboard/index.md b/Documentation/mainboard/index.md
index 1b2697c9c0..bbfe831fc9 100644
--- a/Documentation/mainboard/index.md
+++ b/Documentation/mainboard/index.md
@@ -248,7 +248,7 @@ T440p <lenovo/t440p.md>
 ```{toctree}
 :maxdepth: 1
 
-T470s/T480/T480s/T580 <lenovo/skylake.md>
+T470s/T480/T480s/T580/X280 <lenovo/skylake.md>
 ```
 ## Libretrend
 
diff --git a/Documentation/mainboard/lenovo/skylake.md b/Documentation/mainboard/lenovo/skylake.md
index 18e741daa0..64e075e2cd 100644
--- a/Documentation/mainboard/lenovo/skylake.md
+++ b/Documentation/mainboard/lenovo/skylake.md
@@ -1,7 +1,7 @@
-# Lenovo ThinkPad T470s/T480/T480s/T580
+# Lenovo ThinkPad T470s/T480/T480s/T580/X280
 
 This page describes how to run coreboot on the Lenovo [Thinkpad T470s], [ThinkPad T480],
-[Thinkpad T480s], and [Thinkpad T580].
+[Thinkpad T480s], [Thinkpad T580], and [Thinkpad X280].
 
 ## Important Notes
 
@@ -105,10 +105,12 @@ firmware image from the updater:
 
     python Dell_PFS_Extract.py Inspiron_5468_1.3.0.exe
 
-The resulting binary should be renamed `me_donor.bin` and moved to the `binaries` folder with
-the IFD and GBE binaries.
+The resulting binary should be renamed `me_donor.bin` (file size 0x1f0000 bytes, sha256 
+`912271bb3ff2cf0e2e27ccfb94337baaca027e6c90b4245f9807a592c8a652e1`) and moved to the `binaries`
+folder with the IFD and GBE binaries.
 
-Then, generate the deguarded ME firmware image adjusting the `--delta` argument accordingly:
+Then, generate the deguarded ME firmware image adjusting the `--delta` argument according to 
+your laptop's model:
 
     ./finalimage.py --delta data/delta/thinkpad_t480 --version 11.6.0.1126 --pch LP --sku 2M --fake-fpfs data/fpfs/zero --input ../coreboot/binaries/me_donor.bin --output ../coreboot/binaries/me_deguarded.bin
 
@@ -131,6 +133,25 @@ HAP bit in the IFD using `ifdtool`:
 The modified IFD will be saved as `ifd.bin.new`. Rename the original file to `ifd.bin.orig` and
 the HAP-enabled one to `ifd.bin`
 
+If you want to allocate the space that has become available from truncating the ME firmware to
+corebios, you can modify the IFD layout. First, save the layout below into a text file
+`layout.txt`:
+
+    00000000:00000fff fd
+    001f4000:00ffffff bios
+    00003000:001f3fff me
+    00001000:00002fff gbe
+
+Then run ifdtool again:
+
+    util/ifdtool/ifdtool -p sklkbl -n layout.txt binaries/ifd.bin
+
+Once again, the modified IFD will be saved as `ifd.bin.new`. Rename `ifd.bin.new` to `ifd.bin`.
+
+The layout above allows you to maximize the CBFS size in your coreboot `.config`:
+
+    CONFIG_CBFS_SIZE=0xE0C000
+
 ## Building coreboot
 
 You can use `make menuconfig` or `make nconfig` to select the mainboard matching your machine,
@@ -204,6 +225,7 @@ binaries if only flashing the `bios` region.
 [ThinkPad T480]: https://pcsupport.lenovo.com/us/en/products/laptops-and-netbooks/thinkpad-t-series-laptops/thinkpad-t480-type-20l5-20l6/
 [ThinkPad T480s]: https://pcsupport.lenovo.com/us/en/products/laptops-and-netbooks/thinkpad-t-series-laptops/thinkpad-t480s-type-20l7-20l8/
 [Thinkpad T580]: https://pcsupport.lenovo.com/us/en/products/laptops-and-netbooks/thinkpad-t-series-laptops/thinkpad-t580-type-20l9-20la/
+[Thinkpad X280]: https://pcsupport.lenovo.com/us/en/products/laptops-and-netbooks/thinkpad-x-series-laptops/thinkpad-x280-type-20kf-20ke/
 [on Lenovo's site]: https://support.lenovo.com/us/en/downloads/ds502355-bios-update-utility-bootable-cd-for-windows-10-64-bit-linux-thinkpad-t480
 [from Lenovo's site]: https://pcsupport.lenovo.com/gb/en/products/laptops-and-netbooks/thinkpad-t-series-laptops/thinkpad-t480s-type-20l7-20l8/solutions/ht508988-critical-intel-thunderbolt-software-and-firmware-updates-thinkpad
 [how to externally flash the TB3 firmware]: https://libreboot.org/docs/install/t480.html#thunderbolt-issue-read-this-before-flashing
diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/Kconfig b/src/mainboard/lenovo/sklkbl_thinkpad/Kconfig
index 8db4676391..d69d94f638 100644
--- a/src/mainboard/lenovo/sklkbl_thinkpad/Kconfig
+++ b/src/mainboard/lenovo/sklkbl_thinkpad/Kconfig
@@ -20,33 +20,41 @@ config BOARD_LENOVO_SKLKBL_THINKPAD_COMMON
 	select MAINBOARD_USES_IFD_GBE_REGION
 	select MEMORY_MAPPED_TPM
 	select SOC_INTEL_COMMON_BLOCK_HDA_VERB
-	select SOC_INTEL_KABYLAKE if BOARD_LENOVO_T480 || BOARD_LENOVO_T480S || BOARD_LENOVO_T580
-	select SOC_INTEL_SKYLAKE if BOARD_LENOVO_T470S
 	select SPD_READ_BY_WORD
 	select SYSTEM_TYPE_LAPTOP
 
 config BOARD_LENOVO_T470S
 	bool
 	select BOARD_LENOVO_SKLKBL_THINKPAD_COMMON
+	select SOC_INTEL_SKYLAKE
 	select HAVE_SPD_IN_CBFS
 
 config BOARD_LENOVO_T480
 	bool
 	select BOARD_LENOVO_SKLKBL_THINKPAD_COMMON
+	select SOC_INTEL_KABYLAKE
 	select MEC1653_HAS_DEBUG_UNLOCK
 	select VARIANT_HAS_DGPU
 
 config BOARD_LENOVO_T480S
 	bool
 	select BOARD_LENOVO_SKLKBL_THINKPAD_COMMON
+	select SOC_INTEL_KABYLAKE
 	select VARIANT_HAS_DGPU
 
 config BOARD_LENOVO_T580
 	bool
 	select BOARD_LENOVO_SKLKBL_THINKPAD_COMMON
+	select SOC_INTEL_KABYLAKE
 	select MEC1653_HAS_DEBUG_UNLOCK
 	select VARIANT_HAS_DGPU
 
+config BOARD_LENOVO_X280
+	bool
+	select BOARD_LENOVO_SKLKBL_THINKPAD_COMMON
+	select SOC_INTEL_KABYLAKE
+	select HAVE_SPD_IN_CBFS
+
 if BOARD_LENOVO_SKLKBL_THINKPAD_COMMON
 
 config MAINBOARD_DIR
@@ -57,6 +65,7 @@ config VARIANT_DIR
 	default "t480" if BOARD_LENOVO_T480
 	default "t480s" if BOARD_LENOVO_T480S
 	default "t580" if BOARD_LENOVO_T580
+	default "x280" if BOARD_LENOVO_X280
 
 config OVERRIDE_DEVICETREE
 	default "variants/\$(CONFIG_VARIANT_DIR)/overridetree.cb"
@@ -66,6 +75,7 @@ config MAINBOARD_PART_NUMBER
 	default "T480" if BOARD_LENOVO_T480
 	default "T480s" if BOARD_LENOVO_T480S
 	default "T580" if BOARD_LENOVO_T580
+	default "X280" if BOARD_LENOVO_X280
 
 config CBFS_SIZE
 	default 0x900000
diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/Kconfig.name b/src/mainboard/lenovo/sklkbl_thinkpad/Kconfig.name
index 26c4a3c65b..1d2888840f 100644
--- a/src/mainboard/lenovo/sklkbl_thinkpad/Kconfig.name
+++ b/src/mainboard/lenovo/sklkbl_thinkpad/Kconfig.name
@@ -11,3 +11,6 @@ config BOARD_LENOVO_T480S
 
 config BOARD_LENOVO_T580
 	bool "ThinkPad T580"
+
+config BOARD_LENOVO_X280
+	bool "ThinkPad X280"
diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/Makefile.mk b/src/mainboard/lenovo/sklkbl_thinkpad/Makefile.mk
index 8d530b7416..eebe6f457d 100644
--- a/src/mainboard/lenovo/sklkbl_thinkpad/Makefile.mk
+++ b/src/mainboard/lenovo/sklkbl_thinkpad/Makefile.mk
@@ -18,6 +18,11 @@ subdirs-y += variants/$(VARIANT_DIR)/memory
 subdirs-y += spd
 endif
 
+ifeq ($(CONFIG_BOARD_LENOVO_X280),y)
+subdirs-y += variants/$(VARIANT_DIR)/memory
+subdirs-y += spd
+endif
+
 ifeq ($(CONFIG_VARIANT_HAS_DGPU),y)
 CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/include
 endif
diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/x280/data.vbt b/src/mainboard/lenovo/sklkbl_thinkpad/variants/x280/data.vbt
new file mode 100644
index 0000000000000000000000000000000000000000..bfb312850e0ab4ea834c535df35edb45834ed248
GIT binary patch
literal 6144
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diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/x280/gma-mainboard.ads b/src/mainboard/lenovo/sklkbl_thinkpad/variants/x280/gma-mainboard.ads
new file mode 100644
index 0000000000..fcfbd75a92
--- /dev/null
+++ b/src/mainboard/lenovo/sklkbl_thinkpad/variants/x280/gma-mainboard.ads
@@ -0,0 +1,19 @@
+-- SPDX-License-Identifier: GPL-2.0-or-later
+
+with HW.GFX.GMA;
+with HW.GFX.GMA.Display_Probing;
+
+use HW.GFX.GMA;
+use HW.GFX.GMA.Display_Probing;
+
+private package GMA.Mainboard is
+
+   ports : constant Port_List :=
+     (eDP,
+      DP1,
+      DP2,
+      HDMI1,
+      HDMI2,
+      others => Disabled);
+
+end GMA.Mainboard;
diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/x280/gpio.c b/src/mainboard/lenovo/sklkbl_thinkpad/variants/x280/gpio.c
new file mode 100644
index 0000000000..f38734be85
--- /dev/null
+++ b/src/mainboard/lenovo/sklkbl_thinkpad/variants/x280/gpio.c
@@ -0,0 +1,200 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <soc/gpio.h>
+#include "../../variant.h"
+
+static const struct pad_config gpio_table[] = {
+	/* ------- GPIO Community 0 ------- */
+
+	/* ------- GPIO Group GPP_A ------- */
+	PAD_CFG_NF(GPP_A0, NONE, DEEP, NF1),				/* -KBRC */
+	PAD_CFG_NF(GPP_A1, NATIVE, DEEP, NF1),				/* LPC_AD0 */
+	PAD_CFG_NF(GPP_A2, NATIVE, DEEP, NF1),				/* LPC_AD1 */
+	PAD_CFG_NF(GPP_A3, NATIVE, DEEP, NF1),				/* LPC_AD2 */
+	PAD_CFG_NF(GPP_A4, NATIVE, DEEP, NF1),				/* LPC_AD3 */
+	PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1),				/* -LPC_FRAME */
+	PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1),				/* IRQSER */
+	PAD_CFG_NF(GPP_A7, NONE, DEEP, NF1),				/* -TPM_IRQ */
+	PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1),				/* -CLKRUN */
+	PAD_CFG_NF(GPP_A9, DN_20K, DEEP, NF1),				/* LPCCLK_EC_24M */
+	PAD_CFG_NF(GPP_A10, DN_20K, DEEP, NF1),				/* LPCCLK_DEBUG_24M */
+	PAD_NC(GPP_A11, NONE),
+	PAD_NC(GPP_A12, NONE),
+	PAD_CFG_NF(GPP_A13, NATIVE, DEEP, NF1),				/* -SUSWARN */
+	PAD_CFG_NF(GPP_A14, NATIVE, DEEP, NF1),				/* -SUS_STAT */
+	PAD_CFG_NF(GPP_A15, NATIVE, DEEP, NF1),				/* -SUSACK*/
+	PAD_NC(GPP_A16, NONE),
+	PAD_NC(GPP_A17, NONE),
+	PAD_NC(GPP_A18, NONE),
+	PAD_NC(GPP_A19, NONE),
+	PAD_NC(GPP_A20, NONE),
+	PAD_NC(GPP_A21, NONE),
+	PAD_NC(GPP_A22, NONE),
+	PAD_NC(GPP_A23, NONE),
+
+	/* ------- GPIO Group GPP_B ------- */
+	PAD_CFG_NF(GPP_B0, NONE, DEEP, NF1),				/* CORE_VID0 */
+	PAD_CFG_NF(GPP_B1, NONE, DEEP, NF1),				/* CORE_VID1 */
+	PAD_NC(GPP_B2, NONE),
+	PAD_NC(GPP_B3, NONE),
+	PAD_CFG_GPI_SCI(GPP_B4, NONE, DEEP, EDGE_SINGLE, INVERT),	/* -TBT_PLUG_EVENT */
+	PAD_CFG_NF(GPP_B5, NONE, DEEP, NF1),				/* -CLKREQ_PCIE0 (TB) */
+	PAD_CFG_NF(GPP_B6, NONE, DEEP, NF1),				/* -CLKREQ_PCIE1 (WLAN) */
+	PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1),				/* -CLKREQ_PCIE2 (GBE) */
+	PAD_CFG_NF(GPP_B8, NONE, DEEP, NF1),				/* -CLKREQ_PCIE3 (NVMe) */
+	PAD_CFG_NF(GPP_B9, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_B10, NONE, DEEP, NF1),				/* -CLKREQ_PCIE5 (WWAN) */
+	PAD_CFG_NF(GPP_B11, NONE, DEEP, NF1),				/* -EXT_PWR_GATE */
+	PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1),				/* -PCH_SLP_S0 */
+	PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1),				/* -PLTRST */
+	PAD_CFG_NF(GPP_B14, NATIVE, DEEP, NF1),				/* PCH_SPKR */
+	PAD_CFG_GPO(GPP_B15, 0, DEEP),					/* NFC_DLREQ */
+	PAD_NC(GPP_B16, NONE),
+	PAD_NC(GPP_B17, NONE),
+	PAD_NC(GPP_B18, NONE),
+	PAD_NC(GPP_B19, NONE),
+	PAD_NC(GPP_B20, NONE),
+	PAD_NC(GPP_B21, NONE),
+	PAD_NC(GPP_B22, NONE),
+	PAD_NC(GPP_B23, NONE),
+
+	/* ------- GPIO Community 1 ------- */
+
+	/* ------- GPIO Group GPP_C ------- */
+	PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1),				/* SMB_CLK */
+	PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1),				/* SMB_DATA */
+	PAD_NC(GPP_C2, NONE),						/* -SMBALERT */
+	PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1),				/* SML0_CLK */
+	PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1),				/* SML0_DATA */
+	PAD_NC(GPP_C5, NONE),
+	PAD_CFG_NF(GPP_C6, NONE, DEEP, NF1),				/* EC_SCL2 */
+	PAD_CFG_NF(GPP_C7, NONE, DEEP, NF1),				/* EC_SDA2 */
+	PAD_NC(GPP_C8, NONE),
+	PAD_NC(GPP_C9, NONE),
+	PAD_NC(GPP_C10, NONE),
+	PAD_NC(GPP_C11, NONE),
+	PAD_NC(GPP_C12, NONE),
+	PAD_NC(GPP_C13, NONE),
+	PAD_NC(GPP_C14, NONE),
+	PAD_NC(GPP_C15, NONE),
+	PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1),				/* I2C0_DATA */
+	PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1),				/* I2C0_CLK */
+	PAD_NC(GPP_C18, NONE),
+	PAD_NC(GPP_C19, NONE),
+	PAD_NC(GPP_C20, NONE),
+	PAD_CFG_GPO(GPP_C21, 0, DEEP),					/* TBT_FORCE_PWR */
+	PAD_CFG_GPI_SCI(GPP_C22, NONE, DEEP, EDGE_SINGLE, INVERT),	/* -EC_SCI */
+	PAD_CFG_GPI_SCI(GPP_C23, NONE, DEEP, EDGE_SINGLE, INVERT),	/* -EC_WAKE */
+
+	/* ------- GPIO Group GPP_D ------- */
+	PAD_NC(GPP_D0, NONE),
+	PAD_NC(GPP_D1, NONE),
+	PAD_NC(GPP_D2, NONE),
+	PAD_NC(GPP_D3, NONE),
+	PAD_NC(GPP_D4, NONE),
+	PAD_NC(GPP_D5, NONE),
+	PAD_NC(GPP_D6, NONE),
+	PAD_NC(GPP_D7, NONE),
+	PAD_NC(GPP_D8, NONE),
+	PAD_NC(GPP_D9, UP_20K),
+	PAD_NC(GPP_D10, NONE),
+	PAD_NC(GPP_D11, UP_20K),
+	PAD_NC(GPP_D12, UP_20K),
+	PAD_NC(GPP_D13, NONE),
+	PAD_NC(GPP_D14, NONE),
+	PAD_NC(GPP_D15, NONE),
+	PAD_NC(GPP_D16, NONE),
+	PAD_CFG_GPO(GPP_D17, 0, DEEP),					/* DDI_PRIORITY */
+	PAD_NC(GPP_D18, NONE),
+	PAD_NC(GPP_D19, NONE),
+	PAD_NC(GPP_D20, NONE),
+	PAD_NC(GPP_D21, NONE),
+	PAD_CFG_GPI_TRIG_OWN(GPP_D22, UP_20K, DEEP, OFF, ACPI),		/* -NFC_DTCT */
+	PAD_NC(GPP_D23, NONE),
+
+	/* ------- GPIO Group GPP_E ------- */
+	PAD_CFG_GPO(GPP_E0, 1, DEEP),                                   /* BDC_ON */
+	PAD_CFG_NF(GPP_E1, NONE, DEEP, NF1),                            /* -SATA1_DTCT */
+	PAD_NC(GPP_E2, NONE),
+	PAD_CFG_GPI_TRIG_OWN(GPP_E3, NONE, DEEP, EDGE_SINGLE, ACPI),    /* -TBT_PLUG_EVENT */
+	PAD_CFG_GPO(GPP_E4, 1, DEEP),					/* NFC_ON */
+	PAD_CFG_NF(GPP_E5, NONE, RSMRST, NF1),				/* SATA1_DEVSLP */
+	PAD_NC(GPP_E6, NONE),
+	PAD_CFG_GPO(GPP_E7, 1, DEEP),					/* -WWAN_DISABLE */
+	PAD_NC(GPP_E8, NONE),
+	PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1),				/* -USB_PORT0_OC0 */
+	PAD_CFG_NF(GPP_E10, NONE, DEEP, NF1),				/* -USB_PORT1_OC1 */
+	PAD_NC(GPP_E11, NONE),
+	PAD_CFG_GPI_APIC_HIGH(GPP_E12, NONE, DEEP),			/* NFC_INT */
+	PAD_CFG_NF(GPP_E13, NONE, DEEP, NF1),				/* DDIP1_HPD */
+	PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1),				/* DDIP2_HPD */
+	PAD_NC(GPP_E15, NONE),
+	PAD_NC(GPP_E16, NONE),
+	PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1),				/* EDP_HPD */
+	PAD_NC(GPP_E18, NONE),
+	PAD_CFG_NF(GPP_E19, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_E20, NONE, DEEP, NF1),				/* DDIP2_CTRLCLK */
+	PAD_CFG_NF(GPP_E21, NONE, DEEP, NF1),				/* DDIP2_CTRLDATA */
+	PAD_NC(GPP_E22, NONE),
+	PAD_NC(GPP_E23, NONE),
+
+	/* ------- GPIO Community 2 ------- */
+
+	/* -------- GPIO Group GPD -------- */
+	PAD_CFG_NF(GPD0, NONE, PWROK, NF1),				/* -BATLOW */
+	PAD_CFG_NF(GPD1, NATIVE, PWROK, NF1),				/* AC_PRESENT */
+	PAD_CFG_NF(GPD2, NATIVE, PWROK, NF1),				/* -LANWAKE */
+	PAD_CFG_NF(GPD3, UP_20K, PWROK, NF1),				/* -PWRSW_EC */
+	PAD_CFG_NF(GPD4, NONE, PWROK, NF1),				/* -PCH_SLP_S3 */
+	PAD_CFG_NF(GPD5, NONE, PWROK, NF1),				/* -PCH_SLP_S4 */
+	PAD_CFG_NF(GPD6, NONE, PWROK, NF1),				/* -PCH_SLP_M */
+	PAD_NC(GPD7, NONE),
+	PAD_CFG_NF(GPD8, NONE, PWROK, NF1),				/* SUSCLK_32K */
+	PAD_CFG_NF(GPD9, NONE, PWROK, NF1),				/* -PCH_SLP_WLAN */
+	PAD_CFG_NF(GPD10, NONE, PWROK, NF1),				/* -PCH_SLP_S5 */
+	PAD_CFG_NF(GPD11, NONE, PWROK, NF1),				/* LANPHYPC */
+
+	/* ------- GPIO Community 3 ------- */
+
+	/* ------- GPIO Group GPP_F ------- */
+	PAD_NC(GPP_F0, NONE),					/* NFC_ACTIVE */
+	PAD_NC(GPP_F1, NONE),
+	PAD_NC(GPP_F2, NONE),
+	PAD_NC(GPP_F3, NONE),
+	PAD_NC(GPP_F4, NONE),					/* -WWAN_RESET */
+	PAD_NC(GPP_F5, UP_20K),
+	PAD_CFG_GPI_TRIG_OWN(GPP_F6, UP_20K, RSMRST, OFF, ACPI),		/* -MIC_HW_EN (R961 to GND) */
+	PAD_CFG_GPI_TRIG_OWN(GPP_F7, UP_20K, RSMRST, OFF, ACPI),		/* -INT_MIC_DTCT */
+	PAD_CFG_GPI_TRIG_OWN(GPP_F8, UP_20K, RSMRST, OFF, ACPI),		/* WWAN_CFG0 */
+	PAD_CFG_GPI_TRIG_OWN(GPP_F9, UP_20K, RSMRST, OFF, ACPI),		/* WWAN_CFG1 */
+	PAD_CFG_GPI_TRIG_OWN(GPP_F10, UP_20K, RSMRST, OFF, ACPI),		/* WWAN_CFG2 */
+	PAD_CFG_GPI_TRIG_OWN(GPP_F11, UP_20K, RSMRST, OFF, ACPI),		/* WWAN_CFG3 */
+	PAD_CFG_GPI_TRIG_OWN(GPP_F12, UP_20K, RSMRST, OFF, ACPI),		/* PLANARID0 */
+	PAD_CFG_GPI_TRIG_OWN(GPP_F13, UP_20K, RSMRST, OFF, ACPI),		/* PLANARID1 */
+	PAD_CFG_GPI_TRIG_OWN(GPP_F14, UP_20K, RSMRST, OFF, ACPI),		/* PLANARID2 */
+	PAD_CFG_GPI_TRIG_OWN(GPP_F15, UP_20K, RSMRST, OFF, ACPI),		/* PLANARID3 */
+	PAD_CFG_GPI_TRIG_OWN(GPP_F16, UP_20K, RSMRST, OFF, ACPI),		/* MEMORYID0 */
+	PAD_CFG_GPI_TRIG_OWN(GPP_F17, UP_20K, RSMRST, OFF, ACPI),		/* MEMORYID1 */
+	PAD_CFG_GPI_TRIG_OWN(GPP_F18, UP_20K, RSMRST, OFF, ACPI),		/* MEMORYID2 */
+	PAD_CFG_GPI_TRIG_OWN(GPP_F19, UP_20K, RSMRST, OFF, ACPI),		/* MEMORYID3 */
+	PAD_CFG_GPI_TRIG_OWN(GPP_F20, UP_20K, RSMRST, OFF, ACPI),		/* MEMORYID4 */
+	PAD_NC(GPP_F21, UP_20K),
+	PAD_CFG_GPI_TRIG_OWN(GPP_F22, UP_20K, RSMRST, OFF, ACPI),		/* -TAMPER_SW_DTCT */
+	PAD_CFG_GPI_TRIG_OWN(GPP_F23, UP_20K, RSMRST, OFF, ACPI),		/* -SC_DTCT */
+
+	/* ------- GPIO Group GPP_G ------- */
+	PAD_NC(GPP_G0, NONE),
+	PAD_NC(GPP_G1, NONE),
+	PAD_NC(GPP_G2, NONE),
+	PAD_NC(GPP_G3, NONE),
+	PAD_CFG_GPO(GPP_G4, 0, DEEP),                                   /* TBT_RTD3_PWR_EN */
+	PAD_CFG_GPO(GPP_G5, 0, DEEP),                                   /* TBT_FORCE_USB_PWR */
+	PAD_CFG_GPO(GPP_G6, 0, DEEP),                                   /* -TBT_PERST */
+	PAD_CFG_GPI_SCI(GPP_G7, NONE, DEEP, LEVEL, INVERT),             /* -TBT_PCIE_WAKE */
+
+};
+
+void variant_config_gpios(void)
+{
+	gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table));
+}
diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/x280/hda_verb.c b/src/mainboard/lenovo/sklkbl_thinkpad/variants/x280/hda_verb.c
new file mode 100644
index 0000000000..089e605eaf
--- /dev/null
+++ b/src/mainboard/lenovo/sklkbl_thinkpad/variants/x280/hda_verb.c
@@ -0,0 +1,124 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <device/azalia_device.h>
+
+const u32 cim_verb_data[] = {
+	0x10ec0257, // Vendor/Device ID: Realtek ALC257
+	0x17aa2256, // Subsystem ID
+	18,
+	AZALIA_SUBVENDOR(0, 0x17aa2256),
+
+	AZALIA_PIN_CFG(0, 0x12, AZALIA_PIN_DESC(
+		AZALIA_INTEGRATED,
+		AZALIA_INTERNAL,
+		AZALIA_MIC_IN,
+		AZALIA_OTHER_DIGITAL,
+		AZALIA_COLOR_UNKNOWN,
+		AZALIA_NO_JACK_PRESENCE_DETECT,
+		2, 0
+	)),
+	AZALIA_PIN_CFG(0, 0x13, 0x40000000), // does not describe a jack or internal device
+	AZALIA_PIN_CFG(0, 0x14, AZALIA_PIN_DESC(
+		AZALIA_INTEGRATED,
+		AZALIA_INTERNAL,
+		AZALIA_SPEAKER,
+		AZALIA_OTHER_ANALOG,
+		AZALIA_COLOR_UNKNOWN,
+		AZALIA_NO_JACK_PRESENCE_DETECT,
+		1, 0
+	)),
+	AZALIA_PIN_CFG(0, 0x18, AZALIA_PIN_CFG_NC(0)),
+	AZALIA_PIN_CFG(0, 0x19, AZALIA_PIN_DESC(
+		AZALIA_JACK,
+		AZALIA_EXTERNAL_PRIMARY_CHASSIS | AZALIA_RIGHT,
+		AZALIA_MIC_IN,
+		AZALIA_STEREO_MONO_1_8,
+		AZALIA_BLACK,
+		AZALIA_JACK_PRESENCE_DETECT,
+		3, 0
+	)),
+	AZALIA_PIN_CFG(0, 0x1a, AZALIA_PIN_CFG_NC(0)),
+	AZALIA_PIN_CFG(0, 0x1b, AZALIA_PIN_CFG_NC(0)),
+	AZALIA_PIN_CFG(0, 0x1d, 0x40661b45), // does not describe a jack or internal device
+	AZALIA_PIN_CFG(0, 0x1e, AZALIA_PIN_CFG_NC(0)),
+	AZALIA_PIN_CFG(0, 0x21, AZALIA_PIN_DESC(
+		AZALIA_JACK,
+		AZALIA_EXTERNAL_PRIMARY_CHASSIS | AZALIA_RIGHT,
+		AZALIA_HP_OUT,
+		AZALIA_STEREO_MONO_1_8,
+		AZALIA_BLACK,
+		AZALIA_JACK_PRESENCE_DETECT,
+		1, 15
+	)),
+
+	//==========Widget node 0x20 - 0 :Hidden register SW reset
+	0x0205001A,
+	0x0204C003,
+	0x0205001A,
+	0x0204C003,
+	0x05850000,
+	0x0584F880,
+	0x05850000,
+	0x0584F880,
+	//==========Widget node 0x20 - 1 : ClassD 2W
+	0x02050038,
+	0x02048981,
+	0x0205001B,
+	0x02040A4B,
+	//==========Widget node 0x20 - 2
+	0x0205003C,
+	0x02043154,
+	0x0205003C,
+	0x02043114,
+	//==========Widget node 0x20 - 3 :
+	0x02050046,
+	0x02040004,
+	0x05750003,
+	0x057409A3,
+	//==========Widget node 0x20 - 4 :JD1 enable 1JD port for HP JD
+	0x02050009,
+	0x02046003,
+	0x0205000A,
+	0x02047770,
+	//==========Widget node 0x20 - 5 : Silence data mode Threshold (-84dB)
+	0x02050037,
+	0x0204FE15,
+	0x02050030,
+	0x02049004,
+
+	0x8086280b, // Vendor/Device ID: Intel Kabylake HDMI
+	0x80860101, // Subsystem ID
+	4,
+	AZALIA_SUBVENDOR(2, 0x80860101),
+
+	AZALIA_PIN_CFG(2, 0x05, AZALIA_PIN_DESC(
+		AZALIA_JACK,
+		AZALIA_DIGITAL_DISPLAY,
+		AZALIA_DIGITAL_OTHER_OUT,
+		AZALIA_OTHER_DIGITAL,
+		AZALIA_COLOR_UNKNOWN,
+		AZALIA_JACK_PRESENCE_DETECT,
+		1, 0
+	)),
+	AZALIA_PIN_CFG(2, 0x06, AZALIA_PIN_DESC(
+		AZALIA_JACK,
+		AZALIA_DIGITAL_DISPLAY,
+		AZALIA_DIGITAL_OTHER_OUT,
+		AZALIA_OTHER_DIGITAL,
+		AZALIA_COLOR_UNKNOWN,
+		AZALIA_JACK_PRESENCE_DETECT,
+		1, 0
+	)),
+	AZALIA_PIN_CFG(2, 0x07, AZALIA_PIN_DESC(
+		AZALIA_JACK,
+		AZALIA_DIGITAL_DISPLAY,
+		AZALIA_DIGITAL_OTHER_OUT,
+		AZALIA_OTHER_DIGITAL,
+		AZALIA_COLOR_UNKNOWN,
+		AZALIA_JACK_PRESENCE_DETECT,
+		1, 0
+	)),
+};
+
+const u32 pc_beep_verbs[] = {};
+AZALIA_ARRAY_SIZES;
diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/x280/memory/Makefile.mk b/src/mainboard/lenovo/sklkbl_thinkpad/variants/x280/memory/Makefile.mk
new file mode 100644
index 0000000000..cba70e22ac
--- /dev/null
+++ b/src/mainboard/lenovo/sklkbl_thinkpad/variants/x280/memory/Makefile.mk
@@ -0,0 +1,22 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+# This is an auto-generated file. Do not edit!!
+# Generated by:
+# util/spd_tools/bin/part_id_gen TGL ddr4 src/mainboard/lenovo/sklkbl_thinkpad/variants/x280/memory src/mainboard/lenovo/sklkbl_thinkpad/variants/x280/memory/mem_parts_used.txt
+
+SPD_SOURCES =
+SPD_SOURCES += spd/ddr4/set-0/spd-15.hex      # ID = 0(0b0000)  Parts = MT40A256M16GE-083E:B
+SPD_SOURCES += spd/ddr4/set-0/spd-12.hex      # ID = 1(0b0001)  Parts = MT40A512M16JY-083E:B
+SPD_SOURCES += spd/ddr4/set-0/spd-12.hex      # ID = 2(0b0010)  Parts = MT40A512M16JY-083E:B
+SPD_SOURCES += spd/ddr4/set-0/spd-12.hex      # ID = 3(0b0011)  Parts = MT40A512M16LY-075:H
+SPD_SOURCES += spd/ddr4/set-0/spd-12.hex      # ID = 4(0b0100)  Parts = MT40A512M16LY-075:H
+SPD_SOURCES += spd/ddr4/set-0/spd-13.hex      # ID = 5(0b0101)  Parts = MT40A1G16WBU-083E:B
+SPD_SOURCES += spd/ddr4/set-0/spd-16.hex      # ID = 6(0b0110)  Parts = K4A4G165WE-BCRC
+SPD_SOURCES += spd/ddr4/set-0/spd-12.hex      # ID = 7(0b0111)  Parts = K4A8G165WC-BCRC
+SPD_SOURCES += spd/ddr4/set-0/spd-12.hex      # ID = 8(0b1000)  Parts = K4A8G165WC-BCRC
+SPD_SOURCES += spd/ddr4/set-0/spd-14.hex      # ID = 9(0b1001)  Parts = K4AAG165WB-MCRC
+SPD_SOURCES += spd/ddr4/set-0/spd-16.hex      # ID = 10(0b1010)  Parts = H5AN4G6NAFR-UHC
+SPD_SOURCES += spd/ddr4/set-0/spd-12.hex      # ID = 11(0b1011)  Parts = H5AN8G6NAFR-UHC
+SPD_SOURCES += spd/ddr4/set-0/spd-12.hex      # ID = 12(0b1100)  Parts = H5AN8G6NAFR-UHC
+SPD_SOURCES += spd/ddr4/set-0/spd-17.hex      # ID = 13(0b1101)  Parts = H5ANAG6NAMR-UHC
+SPD_SOURCES += spd/ddr4/set-0/spd-12.hex      # ID = 14(0b1110)  Parts = MT40A512M16LY-075:E
+SPD_SOURCES += spd/ddr4/set-0/spd-12.hex      # ID = 15(0b1111)  Parts = MT40A512M16LY-075:E
diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/x280/memory/dram_id.generated.txt b/src/mainboard/lenovo/sklkbl_thinkpad/variants/x280/memory/dram_id.generated.txt
new file mode 100644
index 0000000000..8a4e39e2c6
--- /dev/null
+++ b/src/mainboard/lenovo/sklkbl_thinkpad/variants/x280/memory/dram_id.generated.txt
@@ -0,0 +1,22 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+# This is an auto-generated file. Do not edit!!
+# Generated by:
+# util/spd_tools/bin/part_id_gen TGL ddr4 src/mainboard/lenovo/sklkbl_thinkpad/variants/x280/memory src/mainboard/lenovo/sklkbl_thinkpad/variants/x280/memory/mem_parts_used.txt
+
+DRAM Part Name                 ID to assign
+MT40A256M16GE-083E:B           0 (0000)
+MT40A512M16JY-083E:B           1 (0001)
+MT40A512M16JY-083E:B           2 (0010)
+MT40A512M16LY-075:H            3 (0011)
+MT40A512M16LY-075:H            4 (0100)
+MT40A1G16WBU-083E:B            5 (0101)
+K4A4G165WE-BCRC                6 (0110)
+K4A8G165WC-BCRC                7 (0111)
+K4A8G165WC-BCRC                8 (1000)
+K4AAG165WB-MCRC                9 (1001)
+H5AN4G6NAFR-UHC                10 (1010)
+H5AN8G6NAFR-UHC                11 (1011)
+H5AN8G6NAFR-UHC                12 (1100)
+H5ANAG6NAMR-UHC                13 (1101)
+MT40A512M16LY-075:E            14 (1110)
+MT40A512M16LY-075:E            15 (1111)
diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/x280/memory/mem_parts_used.txt b/src/mainboard/lenovo/sklkbl_thinkpad/variants/x280/memory/mem_parts_used.txt
new file mode 100644
index 0000000000..0f33b84f84
--- /dev/null
+++ b/src/mainboard/lenovo/sklkbl_thinkpad/variants/x280/memory/mem_parts_used.txt
@@ -0,0 +1,16 @@
+MT40A256M16GE-083E:B,0
+MT40A512M16JY-083E:B,1
+MT40A512M16JY-083E:B,2
+MT40A512M16LY-075:H,3
+MT40A512M16LY-075:H,4
+MT40A1G16WBU-083E:B,5
+K4A4G165WE-BCRC,6
+K4A8G165WC-BCRC,7
+K4A8G165WC-BCRC,8
+K4AAG165WB-MCRC,9
+H5AN4G6NAFR-UHC,10
+H5AN8G6NAFR-UHC,11
+H5AN8G6NAFR-UHC,12
+H5ANAG6NAMR-UHC,13
+MT40A512M16LY-075:E,14
+MT40A512M16LY-075:E,15
diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/x280/memory_init_params.c b/src/mainboard/lenovo/sklkbl_thinkpad/variants/x280/memory_init_params.c
new file mode 100644
index 0000000000..f14d69a105
--- /dev/null
+++ b/src/mainboard/lenovo/sklkbl_thinkpad/variants/x280/memory_init_params.c
@@ -0,0 +1,57 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <cbfs.h>
+#include <gpio.h>
+#include <soc/gpio.h>
+#include <soc/romstage.h>
+#include <spd_bin.h>
+#include <stdio.h>
+#include "../../spd/spd.h"
+#include "../../variant.h"
+
+static const struct pad_config memory_id_gpio_table[] = {
+	PAD_CFG_GPI_TRIG_OWN(GPP_F16, UP_20K, DEEP, OFF, ACPI),		/* MEMORYID0 */
+	PAD_CFG_GPI_TRIG_OWN(GPP_F17, UP_20K, DEEP, OFF, ACPI),		/* MEMORYID1 */
+	PAD_CFG_GPI_TRIG_OWN(GPP_F18, UP_20K, DEEP, OFF, ACPI),		/* MEMORYID2 */
+	PAD_CFG_GPI_TRIG_OWN(GPP_F19, UP_20K, DEEP, OFF, ACPI),		/* MEMORYID3 */
+	PAD_CFG_GPI_TRIG_OWN(GPP_F20, UP_20K, DEEP, OFF, ACPI),		/* MEMORYID4 */
+};
+
+uint8_t variant_memory_sku(void)
+{
+	gpio_t spd_gpios[] = {
+		GPP_F16,
+		GPP_F17,
+		GPP_F18,
+		GPP_F19,
+		GPP_F20,
+	};
+
+	return gpio_base2_value(spd_gpios, ARRAY_SIZE(spd_gpios));
+}
+
+void mainboard_memory_init_params(FSPM_UPD *mupd)
+{
+	uint8_t spd_idx;
+
+	FSP_M_CONFIG *mem_cfg = &mupd->FspmConfig;
+	mem_cfg->CaVrefConfig      = 2;				/* VREF_CA to CH_A and VREF_DQ_B to CH_B */
+	mem_cfg->DqPinsInterleaved = false;			/* DDR_DQ in non-interleave mode */
+	mem_cfg->MemorySpdDataLen  = CONFIG_DIMM_SPD_SIZE;
+
+	/* Get SPD for soldered RAM SPD (CH 1 and 2) */
+	gpio_configure_pads(memory_id_gpio_table, ARRAY_SIZE(memory_id_gpio_table));
+
+	spd_idx = variant_memory_sku();
+	printk(BIOS_DEBUG, "Detected MEMORY_ID = %d\n", spd_idx);
+	mem_cfg->MemorySpdPtr00    = (uintptr_t)mainboard_find_spd_data(spd_idx);
+	switch (spd_idx) {
+	case 1: case 3: case 7: case 11: case 14:
+		printk(BIOS_DEBUG, "Detected single channel\n");
+		break;
+	default:
+		printk(BIOS_DEBUG, "Detected dual channel\n");
+		mem_cfg->MemorySpdPtr10    = mem_cfg->MemorySpdPtr00;
+		break;
+	}
+}
diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/x280/overridetree.cb b/src/mainboard/lenovo/sklkbl_thinkpad/variants/x280/overridetree.cb
new file mode 100644
index 0000000000..1ef139c8f5
--- /dev/null
+++ b/src/mainboard/lenovo/sklkbl_thinkpad/variants/x280/overridetree.cb
@@ -0,0 +1,85 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
+chip soc/intel/skylake
+	device domain 0 on
+		device ref south_xhci on
+			register "usb2_ports" = "{
+				[0] = USB2_PORT_MID(OC0),		// JUSB1 (USB-A always on)
+				[1] = USB2_PORT_MID(OC1),		// JUSB2 (USB-A)
+				[2] = USB2_PORT_MID(OC_SKIP),		// JFPR (smartcard slot)
+				[3] = USB2_PORT_MID(OC_SKIP),		// JUSBC (USB docking station)
+				[4] = USB2_PORT_MID(OC_SKIP),		// JIRCAM (IR camera)
+				[5] = USB2_PORT_MID(OC_SKIP),		// JWWAN (M.2 WWAN USB)
+				[6] = USB2_PORT_MID(OC_SKIP),		// JWLAN (M.2 WLAN USB)
+				[7] = USB2_PORT_MID(OC_SKIP),		// JCAM (webcam)
+				[8] = USB2_PORT_MID(OC_SKIP),		// JFPR (fingerprint reader)
+				[9] = USB2_PORT_MID(OC_SKIP),		// JLCD (touch panel)
+			}"
+			register "usb3_ports" = "{
+				[0] = USB3_PORT_DEFAULT(OC0),		// JUSB1 (USB-A always on)
+				[1] = USB3_PORT_DEFAULT(OC1),		// JUSB2 (USB-A)
+				[2] = USB3_PORT_DEFAULT(OC_SKIP),	// JSD (SD card reader)
+				[3] = USB3_PORT_DEFAULT(OC_SKIP),	// JUSB3 (USB docking station)
+			}"
+		end
+
+		# PCIe
+		#   PCIe Controller 1 - 1x2 + 2x1
+		#   PCIE 1-2   - RP1  - TB   - CLKOUT0 - CLKREQ0
+		#   PCIE 3     - RP3  - WLAN - CLKOUT1 - CLKREQ1
+		#   PCIE 4     - GbE  - GbE  - CLKOUT2 - CLKREQ2
+		#   PCIe Controller 2 - 1x4
+		#   PCIE 5-8   - RP5  - NVMe - CLKOUT3 - CLKREQ3
+		#   PCIe Controller 3 - 4x1
+		#   PCIE 12    - RP9 - WWAN - CLKOUT5 - CLKREQ5
+
+		# TB - x2
+		device ref pcie_rp1 on
+			register "PcieRpClkReqSupport[0]"		= "true"
+			register "PcieRpClkReqNumber[0]"		= "0"
+			register "PcieRpClkSrcNumber[0]"		= "0"
+			register "PcieRpAdvancedErrorReporting[0]"	= "true"
+			register "PcieRpHotPlug[0]"			= "true"
+		end
+
+		# M.2 WLAN x1
+		device ref pcie_rp3 on
+			register "PcieRpClkReqSupport[2]"		= "true"
+			register "PcieRpClkReqNumber[2]"		= "1"
+			register "PcieRpClkSrcNumber[2]"		= "1"
+			register "PcieRpAdvancedErrorReporting[2]"	= "true"
+			register "PcieRpLtrEnable[2]"			= "true"
+			smbios_slot_desc "SlotTypeM2Socket1_DP" "SlotLengthOther" "M.2/A 2230" "SlotDataBusWidth1X"
+		end
+
+		# Ethernet (clobbers RP4)
+                device ref gbe on
+                        register "LanClkReqSupported"                   = "true"
+                        register "LanClkReqNumber"                      = "2"
+			register "PcieRpClkReqNumber[3]"		= "2"
+			register "PcieRpClkSrcNumber[3]"		= "2"
+                        register "EnableLanLtr"                         = "true"
+                        register "EnableLanK1Off"                       = "true"
+                end
+
+		# M.2 2280 SSD - x4 (RP9)
+		device ref pcie_rp5 on
+			register "PcieRpClkReqSupport[4]"		= "true"
+			register "PcieRpClkReqNumber[4]"		= "3"
+			register "PcieRpClkSrcNumber[4]"		= "3"
+			register "PcieRpAdvancedErrorReporting[4]"	= "true"
+			register "PcieRpLtrEnable[4]"			= "true"
+			smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M.2/M 2280" "SlotDataBusWidth4X"
+		end
+
+		# M.2 WLAN x1
+		device ref pcie_rp9 on
+			register "PcieRpClkReqSupport[8]"		= "true"
+			register "PcieRpClkReqNumber[8]"		= "5"
+			register "PcieRpClkSrcNumber[8]"		= "5"
+			register "PcieRpAdvancedErrorReporting[8]"	= "true"
+			register "PcieRpLtrEnable[8]"			= "true"
+			smbios_slot_desc "SlotTypeM2Socket1_DP" "SlotLengthOther" "M.2/A 2230" "SlotDataBusWidth1X"
+		end
+	end
+end

From a5d3c4c119ae81030c9904b1e671c75bf8fb9293 Mon Sep 17 00:00:00 2001
From: "Johann C. Rode" <jcrode@gmx.net>
Date: Thu, 11 Dec 2025 16:59:43 -0800
Subject: [PATCH 2805/3886] mb/lenovo/sklkbl: Fix headphone jack

This proliferates the fixes from commit e5d10e5d23d3, CB:90023 ("mb/
lenovo/t480: Fix headphone jack") to the other SKL/KBL Thinkpad
variants T580, T470s, and T480s. This has been only validated on the
former two machines, but since the hardware changes between the
different models appear to be minimal, it should be safe to deploy
this fix to the T480s variant blindly.

Change-Id: I1edf8dc33231b9d1e1cf2eaf3f4f296736b7be32
Signed-off-by: Johann C. Rode <jcrode@gmx.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90482
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
---
 .../sklkbl_thinkpad/variants/t470s/hda_verb.c | 37 ++++++++++++++++++-
 .../sklkbl_thinkpad/variants/t480s/hda_verb.c | 37 ++++++++++++++++++-
 .../sklkbl_thinkpad/variants/t580/hda_verb.c  | 37 ++++++++++++++++++-
 3 files changed, 108 insertions(+), 3 deletions(-)

diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t470s/hda_verb.c b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t470s/hda_verb.c
index 1901127390..952ace72f4 100644
--- a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t470s/hda_verb.c
+++ b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t470s/hda_verb.c
@@ -5,7 +5,7 @@
 const u32 cim_verb_data[] = {
 	0x10ec0298, // Vendor/Device ID: Realtek ALC298
 	0x17aa224b, // Subsystem ID
-	12,
+	19,
 	AZALIA_SUBVENDOR(0, 0x17aa224b),
 
 	AZALIA_PIN_CFG(0, 0x12, AZALIA_PIN_DESC(
@@ -52,6 +52,41 @@ const u32 cim_verb_data[] = {
 		2, 0
 	)),
 
+	//==========Widget node 0x20 - 0 :Hidden register SW reset
+	0x0205001A,
+	0x0204C003,
+	0x0205001A,
+	0x0204C003,
+	0x05850000,
+	0x0584F880,
+	0x05850000,
+	0x0584F880,
+	//==========Widget node 0x20 - 1 : ClassD 2W
+	0x02050038,
+	0x02048981,
+	0x0205001B,
+	0x02040A4B,
+	//==========Widget node 0x20 - 2
+	0x0205003C,
+	0x02043154,
+	0x0205003C,
+	0x02043114,
+	//==========Widget node 0x20 - 3 :
+	0x02050046,
+	0x02040004,
+	0x05750003,
+	0x057409A3,
+	//==========Widget node 0x20 - 4 :JD1 enable 1JD port for HP JD
+	0x02050009,
+	0x02046003,
+	0x0205000A,
+	0x02047770,
+	//==========Widget node 0x20 - 5 : Silence data mode Threshold (-84dB)
+	0x02050037,
+	0x0204FE15,
+	0x02050030,
+	0x02049004,
+
 	0x80862809, // Vendor/Device ID: Intel Skylake HDMI
 	0x80860101, // Subsystem ID
 	4,
diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/hda_verb.c b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/hda_verb.c
index b1d96c5a76..9eb9287f9b 100644
--- a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/hda_verb.c
+++ b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/hda_verb.c
@@ -5,7 +5,7 @@
 const u32 cim_verb_data[] = {
 	0x10ec0257, // Vendor/Device ID: Realtek ALC257
 	0x17aa2258, // Subsystem ID
-	11,
+	18,
 	AZALIA_SUBVENDOR(0, 0x17aa2258),
 
 	AZALIA_PIN_CFG(0, 0x12, AZALIA_PIN_DESC(
@@ -51,6 +51,41 @@ const u32 cim_verb_data[] = {
 		1, 15
 	)),
 
+	//==========Widget node 0x20 - 0 :Hidden register SW reset
+	0x0205001A,
+	0x0204C003,
+	0x0205001A,
+	0x0204C003,
+	0x05850000,
+	0x0584F880,
+	0x05850000,
+	0x0584F880,
+	//==========Widget node 0x20 - 1 : ClassD 2W
+	0x02050038,
+	0x02048981,
+	0x0205001B,
+	0x02040A4B,
+	//==========Widget node 0x20 - 2
+	0x0205003C,
+	0x02043154,
+	0x0205003C,
+	0x02043114,
+	//==========Widget node 0x20 - 3 :
+	0x02050046,
+	0x02040004,
+	0x05750003,
+	0x057409A3,
+	//==========Widget node 0x20 - 4 :JD1 enable 1JD port for HP JD
+	0x02050009,
+	0x02046003,
+	0x0205000A,
+	0x02047770,
+	//==========Widget node 0x20 - 5 : Silence data mode Threshold (-84dB)
+	0x02050037,
+	0x0204FE15,
+	0x02050030,
+	0x02049004,
+
 	0x8086280b, // Vendor/Device ID: Intel Kabylake HDMI
 	0x80860101, // Subsystem ID
 	4,
diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t580/hda_verb.c b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t580/hda_verb.c
index 65245c8e21..943d1fbae9 100644
--- a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t580/hda_verb.c
+++ b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t580/hda_verb.c
@@ -5,7 +5,7 @@
 const u32 cim_verb_data[] = {
 	0x10ec0257, // Vendor/Device ID: Realtek ALC257
 	0x17aa225a, // Subsystem ID
-	11,
+	18,
 	AZALIA_SUBVENDOR(0, 0x17aa225a),
 
 	AZALIA_PIN_CFG(0, 0x12, AZALIA_PIN_DESC(
@@ -51,6 +51,41 @@ const u32 cim_verb_data[] = {
 		1, 15
 	)),
 
+	//==========Widget node 0x20 - 0 :Hidden register SW reset
+	0x0205001A,
+	0x0204C003,
+	0x0205001A,
+	0x0204C003,
+	0x05850000,
+	0x0584F880,
+	0x05850000,
+	0x0584F880,
+	//==========Widget node 0x20 - 1 : ClassD 2W
+	0x02050038,
+	0x02048981,
+	0x0205001B,
+	0x02040A4B,
+	//==========Widget node 0x20 - 2
+	0x0205003C,
+	0x02043154,
+	0x0205003C,
+	0x02043114,
+	//==========Widget node 0x20 - 3 :
+	0x02050046,
+	0x02040004,
+	0x05750003,
+	0x057409A3,
+	//==========Widget node 0x20 - 4 :JD1 enable 1JD port for HP JD
+	0x02050009,
+	0x02046003,
+	0x0205000A,
+	0x02047770,
+	//==========Widget node 0x20 - 5 : Silence data mode Threshold (-84dB)
+	0x02050037,
+	0x0204FE15,
+	0x02050030,
+	0x02049004,
+
 	0x8086280b, // Vendor/Device ID: Intel Kabylake HDMI
 	0x80860101, // Subsystem ID
 	4,

From 2171af0f5f67c4e29c043c9e6a8be41b451dabcf Mon Sep 17 00:00:00 2001
From: "Johann C. Rode" <jcrode@gmx.net>
Date: Sat, 13 Dec 2025 11:54:29 -0800
Subject: [PATCH 2806/3886] mb/lenovo/sklkbl_x280: Fix build failure

This fixes the build failure for commit 0b4d41004 (mb/lenovo/sklkbl: Add
Lenovo Thinkpad X280 as a variant) caused by a discrepancy between
memory/Makefile.mk and the actual content of spd/ddr4.

Change-Id: I92a4446e7bd457a7f09a107a0cb0fe1d7a6e1de4
Signed-off-by: Johann C. Rode <jcrode@gmx.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90503
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 .../sklkbl_thinkpad/variants/x280/memory/Makefile.mk   | 10 +++++-----
 1 file changed, 5 insertions(+), 5 deletions(-)

diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/x280/memory/Makefile.mk b/src/mainboard/lenovo/sklkbl_thinkpad/variants/x280/memory/Makefile.mk
index cba70e22ac..68617d4dfa 100644
--- a/src/mainboard/lenovo/sklkbl_thinkpad/variants/x280/memory/Makefile.mk
+++ b/src/mainboard/lenovo/sklkbl_thinkpad/variants/x280/memory/Makefile.mk
@@ -4,19 +4,19 @@
 # util/spd_tools/bin/part_id_gen TGL ddr4 src/mainboard/lenovo/sklkbl_thinkpad/variants/x280/memory src/mainboard/lenovo/sklkbl_thinkpad/variants/x280/memory/mem_parts_used.txt
 
 SPD_SOURCES =
-SPD_SOURCES += spd/ddr4/set-0/spd-15.hex      # ID = 0(0b0000)  Parts = MT40A256M16GE-083E:B
+SPD_SOURCES += spd/ddr4/set-0/spd-14.hex      # ID = 0(0b0000)  Parts = MT40A256M16GE-083E:B
 SPD_SOURCES += spd/ddr4/set-0/spd-12.hex      # ID = 1(0b0001)  Parts = MT40A512M16JY-083E:B
 SPD_SOURCES += spd/ddr4/set-0/spd-12.hex      # ID = 2(0b0010)  Parts = MT40A512M16JY-083E:B
 SPD_SOURCES += spd/ddr4/set-0/spd-12.hex      # ID = 3(0b0011)  Parts = MT40A512M16LY-075:H
 SPD_SOURCES += spd/ddr4/set-0/spd-12.hex      # ID = 4(0b0100)  Parts = MT40A512M16LY-075:H
 SPD_SOURCES += spd/ddr4/set-0/spd-13.hex      # ID = 5(0b0101)  Parts = MT40A1G16WBU-083E:B
-SPD_SOURCES += spd/ddr4/set-0/spd-16.hex      # ID = 6(0b0110)  Parts = K4A4G165WE-BCRC
+SPD_SOURCES += spd/ddr4/set-0/spd-15.hex      # ID = 6(0b0110)  Parts = K4A4G165WE-BCRC
 SPD_SOURCES += spd/ddr4/set-0/spd-12.hex      # ID = 7(0b0111)  Parts = K4A8G165WC-BCRC
 SPD_SOURCES += spd/ddr4/set-0/spd-12.hex      # ID = 8(0b1000)  Parts = K4A8G165WC-BCRC
-SPD_SOURCES += spd/ddr4/set-0/spd-14.hex      # ID = 9(0b1001)  Parts = K4AAG165WB-MCRC
-SPD_SOURCES += spd/ddr4/set-0/spd-16.hex      # ID = 10(0b1010)  Parts = H5AN4G6NAFR-UHC
+SPD_SOURCES += spd/ddr4/set-0/spd-13.hex      # ID = 9(0b1001)  Parts = K4AAG165WB-MCRC
+SPD_SOURCES += spd/ddr4/set-0/spd-15.hex      # ID = 10(0b1010)  Parts = H5AN4G6NAFR-UHC
 SPD_SOURCES += spd/ddr4/set-0/spd-12.hex      # ID = 11(0b1011)  Parts = H5AN8G6NAFR-UHC
 SPD_SOURCES += spd/ddr4/set-0/spd-12.hex      # ID = 12(0b1100)  Parts = H5AN8G6NAFR-UHC
-SPD_SOURCES += spd/ddr4/set-0/spd-17.hex      # ID = 13(0b1101)  Parts = H5ANAG6NAMR-UHC
+SPD_SOURCES += spd/ddr4/set-0/spd-16.hex      # ID = 13(0b1101)  Parts = H5ANAG6NAMR-UHC
 SPD_SOURCES += spd/ddr4/set-0/spd-12.hex      # ID = 14(0b1110)  Parts = MT40A512M16LY-075:E
 SPD_SOURCES += spd/ddr4/set-0/spd-12.hex      # ID = 15(0b1111)  Parts = MT40A512M16LY-075:E

From 9f6e297399b3dd74191305fde174849dbc0c7817 Mon Sep 17 00:00:00 2001
From: Appukuttan V K <appukuttan.vk@intel.com>
Date: Fri, 12 Dec 2025 11:33:35 +0530
Subject: [PATCH 2807/3886] vc/intel/fsp/mtl: Fix license header in
 MemInfoHob.h

Replace the incorrect Intel confidential license header with the
proper BSD license header in the MemInfoHob.h file to align with
the standard licensing used for Intel FSP vendorcode.

BUG=None
TEST=None

Change-Id: I242d9abedc2910f819c70be597c5d1cbca996a2a
Signed-off-by: Appukuttan V K <appukuttan.vk@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90494
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
---
 .../fsp/fsp2_0/meteorlake/x86_64/MemInfoHob.h | 35 +++++--------------
 1 file changed, 8 insertions(+), 27 deletions(-)

diff --git a/src/vendorcode/intel/fsp/fsp2_0/meteorlake/x86_64/MemInfoHob.h b/src/vendorcode/intel/fsp/fsp2_0/meteorlake/x86_64/MemInfoHob.h
index 56af141742..7660a30d30 100644
--- a/src/vendorcode/intel/fsp/fsp2_0/meteorlake/x86_64/MemInfoHob.h
+++ b/src/vendorcode/intel/fsp/fsp2_0/meteorlake/x86_64/MemInfoHob.h
@@ -3,34 +3,15 @@
   Memory S3 Save data, Memory Info data and Memory Platform
   data hobs.
 
-@copyright
-  INTEL CONFIDENTIAL
-  Copyright 1999 - 2022 Intel Corporation.
+  @copyright
+  Copyright (c) 1999 - 2022, Intel Corporation. All rights reserved.<BR>
+  This program and the accompanying materials are licensed and made available under
+  the terms and conditions of the BSD License that accompanies this distribution.
+  The full text of the license may be found at
+  http://opensource.org/licenses/bsd-license.php.
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
 
-  The source code contained or described herein and all documents related to the
-  source code ("Material") are owned by Intel Corporation or its suppliers or
-  licensors. Title to the Material remains with Intel Corporation or its suppliers
-  and licensors. The Material may contain trade secrets and proprietary and
-  confidential information of Intel Corporation and its suppliers and licensors,
-  and is protected by worldwide copyright and trade secret laws and treaty
-  provisions. No part of the Material may be used, copied, reproduced, modified,
-  published, uploaded, posted, transmitted, distributed, or disclosed in any way
-  without Intel's prior express written permission.
-
-  No license under any patent, copyright, trade secret or other intellectual
-  property right is granted to or conferred upon you by disclosure or delivery
-  of the Materials, either expressly, by implication, inducement, estoppel or
-  otherwise. Any license under such intellectual property rights must be
-  express and approved by Intel in writing.
-
-  Unless otherwise agreed by Intel in writing, you may not remove or alter
-  this notice or any other notice embedded in Materials by Intel or
-  Intel's suppliers or licensors in any way.
-
-  This file contains an 'Intel Peripheral Driver' and is uniquely identified as
-  "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
-  the terms of your license agreement with Intel or your vendor. This file may
-  be modified by the user, subject to additional terms of the license agreement.
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
 
 @par Specification Reference:
 **/

From 71b79018daeb757a9d1c7d5600dfad96ed95d2ec Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Fri, 12 Dec 2025 21:12:53 -0600
Subject: [PATCH 2808/3886] util/release/genrelnotes: Restore to saved HEAD
 instead of origin/main

The script was failing when origin/main doesn't exist. Instead of
trying to detect or use a main branch, simply save the current HEAD
hash and restore it when done. This works regardless of branch names
or remote configuration.

Also improve the clean check to use git diff-files instead of
comparing to a specific branch.

Change-Id: I237de4b1e8a06fd4e1e3ef08286208c130e7a6bd
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90502
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 util/release/genrelnotes | 10 +++++++---
 1 file changed, 7 insertions(+), 3 deletions(-)

diff --git a/util/release/genrelnotes b/util/release/genrelnotes
index 5ac8abffbf..2b6619b836 100755
--- a/util/release/genrelnotes
+++ b/util/release/genrelnotes
@@ -26,9 +26,12 @@ then
 	exit 1
 fi
 
+# Save the original HEAD hash to restore later
+ORIGINAL_HEAD=$(git rev-parse HEAD)
+
 # Try to verify that the repo is clean before losing state.
 if ! git diff-index --quiet --cached HEAD 2>/dev/null || \
-	[ "$(git diff origin/main --shortstat 2>/dev/null | tail -n1)" != "" ]; then
+	! git diff-files --quiet 2>/dev/null; then
 	echo "ERROR: repo is not clean.  Exiting." >&2
 	exit 1
 fi
@@ -185,7 +188,7 @@ find_areas() {
 # up manually.
 version_ctrl_c() {
 	printf "\n Cleaning up and exiting.\n" >&2
-	git checkout origin/main > /dev/null 2>&1
+	git checkout "$ORIGINAL_HEAD" > /dev/null 2>&1
 	git submodule update --init --checkout  > /dev/null 2>&1
 	rm "$LOGFILE"
 	exit 1;
@@ -290,7 +293,8 @@ southbridge_list_new=$(find_areas "src/southbridge" "Kconfig" "")
 printf "Calculating new SLOC\n"
 NEW_SLOC=$(get_sloc)
 
-git checkout origin/main  > /dev/null 2>&1
+# Restore to original HEAD
+git checkout "$ORIGINAL_HEAD" > /dev/null 2>&1
 git submodule update --init --checkout  > /dev/null 2>&1
 trap "" SIGINT
 

From fad9878a3e11d7b6f302022b010d1dd59fc45c11 Mon Sep 17 00:00:00 2001
From: Sowmya V <v.sowmya@intel.com>
Date: Fri, 12 Dec 2025 21:03:26 +0530
Subject: [PATCH 2809/3886] vc/intel/fsp/fsp2_0/wildcatlake: Update WCL FSP
 headers to FSP WCL.3393.02

Update Wildcatlake FSP headers from version WCL.3393.02

FspmUpd.h: Add below upds
* Vdd2HVoltage
* Vdd1Voltage
* Vdd2LVoltage
* VddqVoltage

FspsUpd.h: Add below upds
* UfsInlineEncryption
* MaxActiveDisplays

MemInfoHob.h:
* PprTargetedStatus - PPR status of each Targeted PPR request

BUG=b:464402767
TEST=Able to build google/ocelot with the latest header changes

Change-Id: I66f22452fb7cd771752afe8bd7c0c3e5dac2106e
Signed-off-by: Sowmya V <v.sowmya@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90496
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
---
 .../intel/fsp/fsp2_0/wildcatlake/FspmUpd.h    | 26 ++++++++++++++++++-
 .../intel/fsp/fsp2_0/wildcatlake/FspsUpd.h    | 22 +++++++++++++---
 .../intel/fsp/fsp2_0/wildcatlake/MemInfoHob.h |  4 +++
 3 files changed, 47 insertions(+), 5 deletions(-)

diff --git a/src/vendorcode/intel/fsp/fsp2_0/wildcatlake/FspmUpd.h b/src/vendorcode/intel/fsp/fsp2_0/wildcatlake/FspmUpd.h
index dace75895d..661948e325 100644
--- a/src/vendorcode/intel/fsp/fsp2_0/wildcatlake/FspmUpd.h
+++ b/src/vendorcode/intel/fsp/fsp2_0/wildcatlake/FspmUpd.h
@@ -3121,7 +3121,31 @@ typedef struct {
 
 /** Offset 0x0B31 - Reserved
 **/
-  UINT8                       Reserved93[55];
+  UINT8                       Reserved93[17];
+
+/** Offset 0x0B42 - VDD2 Voltage
+  Voltage is multiple of 5mV where 0 means Auto.
+**/
+  UINT16                      Vdd2HVoltage;
+
+/** Offset 0x0B44 - VDD1 Voltage
+  Voltage is multiple of 5mV where 0 means Auto.
+**/
+  UINT16                      Vdd1Voltage;
+
+/** Offset 0x0B46 - VDD2L Voltage Override
+  Voltage is multiple of 5mV where 0 means Auto.
+**/
+  UINT16                      Vdd2LVoltage;
+
+/** Offset 0x0B48 - VDDQ Voltage Override
+  Voltage is multiple of 5mV where 0 means Auto.
+**/
+  UINT16                      VddqVoltage;
+
+/** Offset 0x0B4A - Reserved
+**/
+  UINT8                       Reserved94[30];
 } FSP_M_CONFIG;
 
 /** Fsp M UPD Configuration
diff --git a/src/vendorcode/intel/fsp/fsp2_0/wildcatlake/FspsUpd.h b/src/vendorcode/intel/fsp/fsp2_0/wildcatlake/FspsUpd.h
index b5194418b1..ae0ffe29dd 100644
--- a/src/vendorcode/intel/fsp/fsp2_0/wildcatlake/FspsUpd.h
+++ b/src/vendorcode/intel/fsp/fsp2_0/wildcatlake/FspsUpd.h
@@ -458,9 +458,17 @@ typedef struct {
 **/
   UINT8                       UfsEnable[2];
 
-/** Offset 0x014D - Reserved
+/** Offset 0x014D - UFS Inline Encryption enable/disable
+  Enable/Disable UFS Inline Encryption feature, One byte for each Controller - (1,0)
+  to enable Inline Encryption for controller 0 and (0, 1) to enable Inline Encryption
+  for controller 1
+  $EN_DIS
 **/
-  UINT8                       Reserved12[4];
+  UINT8                       UfsInlineEncryption[2];
+
+/** Offset 0x014F - Reserved
+**/
+  UINT8                       Reserved12[2];
 
 /** Offset 0x0151 - Enable/Disable PCIe tunneling for USB4
   Enable/Disable PCIe tunneling for USB4, default is enable
@@ -2026,9 +2034,15 @@ typedef struct {
 **/
   UINT8                       LidStatus;
 
-/** Offset 0x1401 - Reserved
+/** Offset 0x1401 - Select MaxActiveDisplays
+  Max Active Display : 0 - Default VBT, 1 - 1 display, 2 - 2 displays, Maximum supported
+  is 2 displays only
 **/
-  UINT8                       Reserved50[67];
+  UINT8                       MaxActiveDisplays;
+
+/** Offset 0x1402 - Reserved
+**/
+  UINT8                       Reserved50[66];
 
 /** Offset 0x1444 - Address of PCH_DEVICE_INTERRUPT_CONFIG table.
   The address of the table of PCH_DEVICE_INTERRUPT_CONFIG.
diff --git a/src/vendorcode/intel/fsp/fsp2_0/wildcatlake/MemInfoHob.h b/src/vendorcode/intel/fsp/fsp2_0/wildcatlake/MemInfoHob.h
index 83e346ca5c..c89cf2cab1 100644
--- a/src/vendorcode/intel/fsp/fsp2_0/wildcatlake/MemInfoHob.h
+++ b/src/vendorcode/intel/fsp/fsp2_0/wildcatlake/MemInfoHob.h
@@ -35,6 +35,9 @@ extern EFI_GUID gSiMemoryPlatformDataGuid;
 #define _MAX_RANK_IN_CHANNEL       (4)       ///< The maximum number of ranks per channel.
 #define _MAX_SDRAM_IN_DIMM         (5)       ///< The maximum number of SDRAMs per DIMM.
 
+// Must match the corresponding definition in CMrcExtTypes.h
+#define PPR_REQUEST_MAX           (2)
+
 // Must match definitions in
 // Intel\OneSiliconPkg\IpBlock\MemoryInit\Mtl\Include\MrcInterface.h
 #define HOB_MAX_SAGV_POINTS 4
@@ -359,6 +362,7 @@ typedef struct {
   BOOLEAN           MixedEccDimms;                     ///< TRUE if both ECC and nonECC Dimms were detected in the system
   UINT8             MaxRankCapacity;                   ///< Maximum possible rank capacity in [GB]
   UINT16            PprFailingChannelBitMask;          ///< PPR failing channel mask
+  BOOLEAN           PprTargetedStatus[PPR_REQUEST_MAX]; ///< PPR status of each Targeted PPR request (0 = Targeted PPR was successful, 1 = PPR failed)
 } MEMORY_INFO_DATA_HOB;
 
 /**

From 2183326306790b74a7830298113356441b56cf1a Mon Sep 17 00:00:00 2001
From: Subrata Banik <subratabanik@google.com>
Date: Mon, 15 Dec 2025 07:05:42 +0000
Subject: [PATCH 2810/3886] soc/qualcomm/x1p42100: Rename qcsdi region to
 aop_sdi in memlayout

On the X1P42100 SoC, the System Debug Image (SDI) flow is handled by
the Always-On Processor (AOP), unlike previous architectures (e.g.,
Kodiak) which utilized a dedicated 'QcSDI' image.

Rename the memory region at 0x14699000 from 'qcsdi' to 'aop_sdi' to
accurately reflect ownership by the AOP and to align with the new
chipset architecture. This change clarifies the memory map and serves
as a prerequisite for removing legacy QcSDI artifacts once the
modern SDI flow is fully enabled.

BUG=b:456953373
TEST=Build and boot on google/quenbih target.

Change-Id: Ic5626c06decaadfd459aa21bde4efcfec92e1e47
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90505
Reviewed-by: Jayvik Desai <jayvik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/soc/qualcomm/x1p42100/memlayout.ld | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/soc/qualcomm/x1p42100/memlayout.ld b/src/soc/qualcomm/x1p42100/memlayout.ld
index 5bd7d98f04..554295e956 100644
--- a/src/soc/qualcomm/x1p42100/memlayout.ld
+++ b/src/soc/qualcomm/x1p42100/memlayout.ld
@@ -161,7 +161,7 @@
  * 0x146AA000    +----------------------------------------------------------+      |
  *               |                ... Usable memory ...                     |    SSRAM
  * 0x146A5000    +----------------------------------------------------------+      |
- *               |                       qcsdi                              |      |
+ *               |                      AOP SDI                             |      |
  * 0x14699000    +----------------------------------------------------------+      |
  *               |                       STACK                              |      v
  * 0x14680000    +----------------------------------------------------------+ <---------
@@ -187,7 +187,7 @@ SECTIONS
 
 	SSRAM_START(0x14680000)
 	STACK(0x14680000, 16K)
-	REGION(qcsdi, 0x14699000, 48K, 4K)
+	REGION(aop_sdi, 0x14699000, 48K, 4K)
 	REGION(shared_imem, 0x146AA000, 0x1000, 4K)
 	REGION(ddr_information, 0x146ABFE8, 16, 8)
 	WATCHDOG_TOMBSTONE(0x146ABFFC, 4)

From 641f7ac677b65b6e2f24f47015c694b445a75cf7 Mon Sep 17 00:00:00 2001
From: Subrata Banik <subratabanik@google.com>
Date: Sat, 6 Dec 2025 19:07:38 +0000
Subject: [PATCH 2811/3886] arch/arm64: Introduce distinct PRERAM and POSTRAM
 stack regions

Refactor the stack definition macros to explicitly define separate
memory regions for the stack, addressing resource conflicts on
certain SoCs like Qualcomm x1p42100.

The original STACK macro is split into PRERAM_STACK and
POSTRAM_STACK.

Motivation:
On the Qualcomm x1p42100 SoC, the boot flow presents two
constraints for the initial stack location:
 - Boot IMEM is unavailable after the ADSP is loaded.
 - The existing SSRAM stack address is reserved for QC QSEE by the
   Trust Zone.

Solution:
 - PRERAM_STACK: Used by coreboot (e.g., till romstage) for static
   stack allocation (from an alternative SSRAM or BOOT IMEM region).
 - POSTRAM_STACK: Used starting from ramstage, leveraging the
   DRAM-mapped memory.

This conditional split allows coreboot to manage stack memory
independently for the limited environment before DRAM is fully
initialized (ENV_ROMSTAGE_OR_BEFORE), resolving the hardware memory
conflicts while maintaining compatibility with existing code via
aliasing.

BUG=b:456953373
BRANCH=None
TEST=Able to build google/bluey.

Change-Id: I6356adc63d595f59050e6dc5961404be4a9534c0
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90402
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jayvik Desai <jayvik@google.com>
---
 src/arch/arm64/include/arch/memlayout.h | 20 +++++++++++++++++++-
 src/include/symbols.h                   |  2 ++
 2 files changed, 21 insertions(+), 1 deletion(-)

diff --git a/src/arch/arm64/include/arch/memlayout.h b/src/arch/arm64/include/arch/memlayout.h
index 5c648b36f0..d84e7714fc 100644
--- a/src/arch/arm64/include/arch/memlayout.h
+++ b/src/arch/arm64/include/arch/memlayout.h
@@ -17,7 +17,25 @@
 /* ARM64 stacks need 16-byte alignment. */
 #define STACK(addr, size) \
 	REGION(stack, addr, size, 16) \
-	_ = ASSERT(size >= 2K, "stack should be >= 2K, see toolchain.mk");
+	_ = ASSERT(size >= 2K, "stack should be >= 2K, see toolchain.mk"); \
+	ALIAS_REGION(stack, preram_stack) \
+	ALIAS_REGION(stack, postram_stack)
+
+#if ENV_ROMSTAGE_OR_BEFORE
+	#define PRERAM_STACK(addr, size) \
+		REGION(preram_stack, addr, size, 16) \
+		_ = ASSERT(size >= 2K, "preram_stack should be >= 2K, see toolchain.mk"); \
+		ALIAS_REGION(preram_stack, stack)
+	#define POSTRAM_STACK(addr, size) \
+		REGION(postram_stack, addr, size, 16)
+#else
+	#define PRERAM_STACK(addr, size) \
+		REGION(preram_stack, addr, size, 16)
+	#define POSTRAM_STACK(addr, size) \
+		REGION(postram_stack, addr, size, 16) \
+		_ = ASSERT(size >= 2K, "postram_stack should be >= 2K, see toolchain.mk"); \
+		ALIAS_REGION(postram_stack, stack)
+#endif
 
 #define BL31(addr, size) \
 	REGION(bl31, addr, size, 4K) \
diff --git a/src/include/symbols.h b/src/include/symbols.h
index c46b6ff9ef..53dbfb94a3 100644
--- a/src/include/symbols.h
+++ b/src/include/symbols.h
@@ -31,6 +31,8 @@ DECLARE_OPTIONAL_REGION(timestamp)
 DECLARE_REGION(preram_cbmem_console)
 DECLARE_REGION(cbmem_init_hooks)
 DECLARE_REGION(stack)
+DECLARE_REGION(preram_stack)
+DECLARE_REGION(postram_stack)
 DECLARE_OPTIONAL_REGION(preram_cbfs_cache)
 DECLARE_OPTIONAL_REGION(postram_cbfs_cache)
 DECLARE_OPTIONAL_REGION(cbfs_cache)

From 1b599a8844928752905be4363df64010fb97a540 Mon Sep 17 00:00:00 2001
From: Subrata Banik <subratabanik@google.com>
Date: Sat, 6 Dec 2025 19:18:37 +0000
Subject: [PATCH 2812/3886] arch/arm64: Add an alternative entry point for
 ramstage code

This change prepares an alternative entry point for the ARM64
ramstage. It is written in assembly language, avoids the usage of the
stack, and overrides the program stack pointer (SP register) if the
`preram_stack` and `postram_stack` point to different addresses.

Previous Boot Flow:
 - header.ld -> jump into `stage_entry` C code for ROMSTAGE onwards ->
     `stage_entry` being called and followed by `main` function

Updated Boot Flow:
 - header.ld -> jump into `_start` (assembly entry point) for
      ramstage specifically -> Update the existing SP (stack pointer)
      register if the `preram_` or `postram_` stack address is not
      same -> call into `stage_entry` and follow the `main` function.

BUG=b:456953373
BRANCH=None
TEST=Able to build google/bluey.

Change-Id: I4eec24aff1c9d01180c3452a3631dd344656c771
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90403
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Jayvik Desai <jayvik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/arch/arm64/armv8/Makefile.mk      |  1 +
 src/arch/arm64/armv8/ramstage_entry.S | 34 +++++++++++++++++++++++++++
 src/arch/arm64/include/arch/header.ld |  2 +-
 3 files changed, 36 insertions(+), 1 deletion(-)
 create mode 100644 src/arch/arm64/armv8/ramstage_entry.S

diff --git a/src/arch/arm64/armv8/Makefile.mk b/src/arch/arm64/armv8/Makefile.mk
index 15d80e64e8..85c83d74da 100644
--- a/src/arch/arm64/armv8/Makefile.mk
+++ b/src/arch/arm64/armv8/Makefile.mk
@@ -73,6 +73,7 @@ endif
 ################################################################################
 ifeq ($(CONFIG_ARCH_RAMSTAGE_ARMV8_64),y)
 
+ramstage-y += ramstage_entry.S
 ramstage-y += cache.c
 ramstage-y += cpu.S
 ramstage-y += exception.c
diff --git a/src/arch/arm64/armv8/ramstage_entry.S b/src/arch/arm64/armv8/ramstage_entry.S
new file mode 100644
index 0000000000..823b12d13a
--- /dev/null
+++ b/src/arch/arm64/armv8/ramstage_entry.S
@@ -0,0 +1,34 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Ramstage entrypoint code for aarch64 (a.k.a. armv8)
+ */
+
+#include <arch/asm.h>
+
+ENTRY(_start)
+	/*
+	 * Note: x0 must be preserved as it contains the CBMEM top pointer
+	 * for the next stage entry.
+	 */
+	ldr	x10, =_preram_stack
+	ldr	x11, =_postram_stack
+
+	cmp	x10, x11
+	beq	stack_init_done
+
+	/* Initialize stack with sentinel value to later check overflow. */
+	ldr	x9, =0xdeadbeefdeadbeef
+	ldr	x10, =_epostram_stack
+1:
+	stp	x9, x9, [x11], #16
+	cmp	x11, x10
+	bne	1b
+
+	/* Update stack pointer with DRAM mapped stack base */
+	/* Leave a line of beef dead for easier visibility in stack dumps. */
+	sub	sp, x11, #16
+
+stack_init_done:
+	/* Call the C function. */
+	bl	stage_entry
+ENDPROC(_start)
diff --git a/src/arch/arm64/include/arch/header.ld b/src/arch/arm64/include/arch/header.ld
index c6d48e704f..4590be1f8b 100644
--- a/src/arch/arm64/include/arch/header.ld
+++ b/src/arch/arm64/include/arch/header.ld
@@ -9,7 +9,7 @@ PHDRS
 	to_load PT_LOAD;
 }
 
-#if ENV_DECOMPRESSOR || ENV_BOOTBLOCK || ENV_RMODULE
+#if ENV_DECOMPRESSOR || ENV_BOOTBLOCK || ENV_RMODULE || ENV_RAMSTAGE
 ENTRY(_start)
 #else
 ENTRY(stage_entry)

From a26b718d5a4dc98a36ceb9d43e8b20a4142c6ea2 Mon Sep 17 00:00:00 2001
From: Subrata Banik <subratabanik@google.com>
Date: Sat, 6 Dec 2025 19:38:13 +0000
Subject: [PATCH 2813/3886] soc/qc/x1p42100: Define pre- & post-RAM stack
 regions in linker script

Implement the newly introduced PRERAM_STACK and POSTRAM_STACK macros in
the x1p42100 memory layout, addressing the memory constraints on this
SoC.

Changes
 - Pre-RAM Stack: The temporary stack used before DRAM is ready is
   defined using PRERAM_STACK(0x14680000, 16K) in the SSRAM region,
   replacing the old generic STACK definition.

 - Post-RAM Stack: The final stack is defined using
   POSTRAM_STACK(0x80000000, 16K) at the start of DRAM.

 - The POSTRAM_DMA_COHERENT region is shifted up to 0x80004000 to
   accommodate the new 16KB post-RAM stack, avoiding memory overlap.

This guarantees a distinct and properly sized stack region for each
stage of the boot process, resolving conflicts with Trust Zone and
ensuring a clean stack transition during the RAM stage.

BUG=b:456953373
BRANCH=None
TEST=Able to build google/bluey.

w/o this patch

```
[SPEW ]  stack: top_of_stack address is 0x14684000
```

w/ this patch

```
[SPEW ]  stack: top_of_stack address is 0x80004000
```

Change-Id: Iccf3f99aff31a8e44386ea52b2196b49797caa79
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90405
Reviewed-by: Jayvik Desai <jayvik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/soc/qualcomm/x1p42100/memlayout.ld | 11 +++++++----
 1 file changed, 7 insertions(+), 4 deletions(-)

diff --git a/src/soc/qualcomm/x1p42100/memlayout.ld b/src/soc/qualcomm/x1p42100/memlayout.ld
index 554295e956..76c0ff2dfd 100644
--- a/src/soc/qualcomm/x1p42100/memlayout.ld
+++ b/src/soc/qualcomm/x1p42100/memlayout.ld
@@ -85,7 +85,9 @@
  * 0x80E00000    +----------------------------------------------------------+      |        |
  *               |                      dram_ncc                            |      |        |
  * 0x80A00000    +----------------------------------------------------------+      |        |
- *               |              postram_dma_coherent_dram                   |      v        v
+ *               |              postram_dma_coherent_dram                   |      |        |
+ * 0x80004000    +----------------------------------------------------------+      |        |
+ *               |                    POSTRAM STACK                         |      v        v
  * 0x80000000    +----------------------------------------------------------+ <--------------
  *               |         ... (Memory not mapped: Unavailable) ...         | XXXXXXXXX
  * 0x24060000    +----------------------------------------------------------+ <---------
@@ -163,7 +165,7 @@
  * 0x146A5000    +----------------------------------------------------------+      |
  *               |                      AOP SDI                             |      |
  * 0x14699000    +----------------------------------------------------------+      |
- *               |                       STACK                              |      v
+ *               |                    PRERAM STACK                          |      v
  * 0x14680000    +----------------------------------------------------------+ <---------
  *               |         ... (Memory not mapped: Unavailable) ...         | XXXXXXXXX
  * 0x0B100000    +----------------------------------------------------------+ <---------
@@ -186,7 +188,7 @@ SECTIONS
 	AOPSRAM_END(0x0B100000)
 
 	SSRAM_START(0x14680000)
-	STACK(0x14680000, 16K)
+	PRERAM_STACK(0x14680000, 16K)
 	REGION(aop_sdi, 0x14699000, 48K, 4K)
 	REGION(shared_imem, 0x146AA000, 0x1000, 4K)
 	REGION(ddr_information, 0x146ABFE8, 16, 8)
@@ -221,7 +223,8 @@ SECTIONS
 	REGION(shrm, 0x24040000, 128K , 4K)
 
 	DRAM_START(0x80000000)
-	POSTRAM_DMA_COHERENT(0x80000000, 8K)
+	POSTRAM_STACK(0x80000000, 16K)
+	POSTRAM_DMA_COHERENT(0x80004000, 8K)
 	REGION(dram_ncc, 0x80A00000, 0x400000, 4K)
 	REGION(dram_cpucp, 0x80E00000, 0x7A0000, 4K)
 

From 4d53aa77042ae3233e0ed3949730ac274cfbf3ed Mon Sep 17 00:00:00 2001
From: Subrata Banik <subratabanik@google.com>
Date: Sat, 6 Dec 2025 19:45:46 +0000
Subject: [PATCH 2814/3886] soc/qualcomm/x1p42100: Relocate PRERAM stack to
 BSRAM memory

Relocate the PRERAM_STACK region to a new address to resolve a memory
conflict with the QSEE Trust Zone environment.

Details:
 - The previous location of the PRERAM_STACK starting at 0x14680000 in
   SSRAM is now reserved for QC QSEE.

 - This change moves the 16KB PRERAM_STACK from 0x14680000 (SSRAM) to
   the available memory region starting at 0x14850000 in the BSRAM.

BUG=b:456953373
BRANCH=None
TEST=Able to build google/bluey.

Change-Id: Ifa9bc457e28b9ec21aa59c6ab9114993f23b2bc8
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90406
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jayvik Desai <jayvik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
---
 src/soc/qualcomm/x1p42100/memlayout.ld | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/src/soc/qualcomm/x1p42100/memlayout.ld b/src/soc/qualcomm/x1p42100/memlayout.ld
index 76c0ff2dfd..cbcbd57ca9 100644
--- a/src/soc/qualcomm/x1p42100/memlayout.ld
+++ b/src/soc/qualcomm/x1p42100/memlayout.ld
@@ -139,6 +139,8 @@
  * 0x14857000    +----------------------------------------------------------+      |
  *               |                    VBOOT2_WORK                           |      |
  * 0x14854000    +----------------------------------------------------------+      |
+ *               |                    PRERAM STACK                          |      |
+ * 0x14850000    +----------------------------------------------------------+      |
  *               |             TTB (Translation Table Base)                 |      |
  * 0x14842000    +----------------------------------------------------------+      |
  *               |                     TIMESTAMP                            |      |
@@ -165,7 +167,7 @@
  * 0x146A5000    +----------------------------------------------------------+      |
  *               |                      AOP SDI                             |      |
  * 0x14699000    +----------------------------------------------------------+      |
- *               |                    PRERAM STACK                          |      v
+ *               |                 Reserved for QSEE                        |      v
  * 0x14680000    +----------------------------------------------------------+ <---------
  *               |         ... (Memory not mapped: Unavailable) ...         | XXXXXXXXX
  * 0x0B100000    +----------------------------------------------------------+ <---------
@@ -188,7 +190,6 @@ SECTIONS
 	AOPSRAM_END(0x0B100000)
 
 	SSRAM_START(0x14680000)
-	PRERAM_STACK(0x14680000, 16K)
 	REGION(aop_sdi, 0x14699000, 48K, 4K)
 	REGION(shared_imem, 0x146AA000, 0x1000, 4K)
 	REGION(ddr_information, 0x146ABFE8, 16, 8)
@@ -201,6 +202,7 @@ SECTIONS
 	PRERAM_CBFS_CACHE(0x14828000, 103K)
 	TIMESTAMP(0x14841C00, 1K)
 	TTB(0x14842000, 56K)
+	PRERAM_STACK(0x14850000, 16K)
 	VBOOT2_WORK(0x14854000, 12K)
 	PRERAM_DMA_COHERENT(0x14857000, 8K)
 	REGION(qclib_serial_log, 0x1485B000, 4K, 4K)

From 22e54a701dfe2195028577802348ba345e9353e1 Mon Sep 17 00:00:00 2001
From: Subrata Banik <subratabanik@google.com>
Date: Wed, 10 Dec 2025 09:55:16 +0000
Subject: [PATCH 2815/3886] soc/qualcomm/x1p42100: Add AOP, QDSS, and QSEE
 regions to SSRAM layout

This commit updates the SSRAM memory layout in memlayout.ld to reserve
space for several new regions.

The following regions are added to the SSRAM section:
 - qsee: 100K at 0x14680000
 - qdss_usb_trace: 8K at 0x146A6000
 - aop_imem: 8K at 0x146A8000

The memory map diagram in the comments is also updated to reflect the
reservation of aop_imem and qdss_usb_trace.

BUG=b:456953373
TEST=Able to build and boot google/quenbih.

Change-Id: I17c2a97d31cdcb81ffdd0c83d8c6d19b9a03a91b
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90443
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jayvik Desai <jayvik@google.com>
---
 src/soc/qualcomm/x1p42100/memlayout.ld | 9 ++++++++-
 1 file changed, 8 insertions(+), 1 deletion(-)

diff --git a/src/soc/qualcomm/x1p42100/memlayout.ld b/src/soc/qualcomm/x1p42100/memlayout.ld
index cbcbd57ca9..ae1ee96355 100644
--- a/src/soc/qualcomm/x1p42100/memlayout.ld
+++ b/src/soc/qualcomm/x1p42100/memlayout.ld
@@ -163,7 +163,11 @@
  * 0x146ABFE8    +----------------------------------------------------------+      |
  *               |                     shared_imem                          |      |
  * 0x146AA000    +----------------------------------------------------------+      |
- *               |                ... Usable memory ...                     |    SSRAM
+ *               |                      aop_imem                            |      |
+ * 0x146A8000    +----------------------------------------------------------+    SSRAM
+ *               |                   qdss_usb_trace                         |      |
+ * 0x146A6000    +----------------------------------------------------------+      |
+ *               |                ... Usable memory ...                     |      |
  * 0x146A5000    +----------------------------------------------------------+      |
  *               |                      AOP SDI                             |      |
  * 0x14699000    +----------------------------------------------------------+      |
@@ -190,7 +194,10 @@ SECTIONS
 	AOPSRAM_END(0x0B100000)
 
 	SSRAM_START(0x14680000)
+	REGION(qsee, 0x14680000, 100K, 4K)
 	REGION(aop_sdi, 0x14699000, 48K, 4K)
+	REGION(qdss_usb_trace, 0x146A6000, 8K, 4K)
+	REGION(aop_imem, 0x146A8000, 8K, 4K)
 	REGION(shared_imem, 0x146AA000, 0x1000, 4K)
 	REGION(ddr_information, 0x146ABFE8, 16, 8)
 	WATCHDOG_TOMBSTONE(0x146ABFFC, 4)

From 8ece648c301df69f8cf0bed18b44344ecd9ab8fd Mon Sep 17 00:00:00 2001
From: Kapil Porwal <kapilporwal@google.com>
Date: Mon, 15 Dec 2025 18:03:28 +0530
Subject: [PATCH 2816/3886] soc/qualcomm/common: Use bitwise OR for
 global_attributes

Ensure that existing flags in global_attributes are not overwritten
when enabling UART logging. Using a bitwise OR preserves any
previously set attributes.

BUG=b:457566143
TEST=Verify the QcLib global attributes.

With this CL -
```
[DEBUG]  Global Attributes[0x3]..Table Entries Count[8]
```

Change-Id: Iffceb06cb800ba4c9e5c07381745cbed1fb7d550
Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90509
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/soc/qualcomm/common/qclib.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/soc/qualcomm/common/qclib.c b/src/soc/qualcomm/common/qclib.c
index 41239d4b57..8dad95715d 100644
--- a/src/soc/qualcomm/common/qclib.c
+++ b/src/soc/qualcomm/common/qclib.c
@@ -213,7 +213,7 @@ static void qclib_prepare_and_run(void)
 
 	/* Enable QCLib serial output, if below condition is met */
 	if (CONFIG(CONSOLE_SERIAL) && qclib_debug_log_level())
-		qclib_cb_if_table.global_attributes =
+		qclib_cb_if_table.global_attributes |=
 			QCLIB_GA_ENABLE_UART_LOGGING;
 
 	dump_te_table();

From eb79807bece575cb8f188f8f33b053fa37033166 Mon Sep 17 00:00:00 2001
From: Kapil Porwal <kapilporwal@google.com>
Date: Mon, 15 Dec 2025 18:28:08 +0530
Subject: [PATCH 2817/3886] soc/qualcomm/x1p42100: Add mainboard hook for QcLib
 override

Introduce a weak function qclib_mainboard_override to allow
mainboards to customize QcLib policies or global attributes.
This hook is called from the SoC-specific QcLib initialization
path.

BUG=b:457566143
TEST=Configure QcLib policy for Google/Quenbi.

Change-Id: I0397b7138db260973ea86852cfa9f408e14d195d
Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90510
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
---
 src/soc/qualcomm/common/include/soc/qclib_common.h | 1 +
 src/soc/qualcomm/x1p42100/qclib.c                  | 8 ++++++++
 2 files changed, 9 insertions(+)

diff --git a/src/soc/qualcomm/common/include/soc/qclib_common.h b/src/soc/qualcomm/common/include/soc/qclib_common.h
index ce5dd82bf3..65c87d7ec7 100644
--- a/src/soc/qualcomm/common/include/soc/qclib_common.h
+++ b/src/soc/qualcomm/common/include/soc/qclib_common.h
@@ -86,6 +86,7 @@ void qclib_add_if_table_entry(const char *name, void *base,
 void qclib_load_and_run(void);
 void qclib_rerun(void);
 int  qclib_soc_override(struct qclib_cb_if_table *table);
+int  qclib_mainboard_override(struct qclib_cb_if_table *table);
 bool qclib_check_dload_mode(void);
 
 const char *qclib_file_default(enum qclib_cbfs_file file);
diff --git a/src/soc/qualcomm/x1p42100/qclib.c b/src/soc/qualcomm/x1p42100/qclib.c
index 33de115dcf..c67b3591f0 100644
--- a/src/soc/qualcomm/x1p42100/qclib.c
+++ b/src/soc/qualcomm/x1p42100/qclib.c
@@ -8,6 +8,8 @@
 #include <soc/symbols_common.h>
 #include <soc/addressmap.h>
 
+__weak int qclib_mainboard_override(struct qclib_cb_if_table *table) { return 0; }
+
 bool qclib_check_dload_mode(void)
 {
 	if (!CONFIG(QC_RAMDUMP_ENABLE))
@@ -55,5 +57,11 @@ int qclib_soc_override(struct qclib_cb_if_table *table)
 
 	qclib_add_if_table_entry(QCLIB_TE_SHRM_META_SETTINGS, _qc_blob_meta, data_size, 0);
 
+	/* hook for platform specific policy configuration */
+	if (qclib_mainboard_override(table)) {
+		printk(BIOS_ERR, "qclib_mainboard_override failed\n");
+		return -1;
+	}
+
 	return 0;
 }

From 679ea61d4deee500f24bea0b9654177d966dcaf2 Mon Sep 17 00:00:00 2001
From: Maximilian Brune <maximilian.brune@9elements.com>
Date: Thu, 11 Dec 2025 17:14:55 +0100
Subject: [PATCH 2818/3886] include/acpi/acpi_apei.h: Add APEI definitions

Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: If391b0fdc31f513bef5d1e940c008eb5a5b1f802
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90474
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
---
 src/include/acpi/acpi_apei.h | 26 ++++++++++++++++++++++++++
 1 file changed, 26 insertions(+)

diff --git a/src/include/acpi/acpi_apei.h b/src/include/acpi/acpi_apei.h
index 8c3e77e5a3..5f0b8a3a1b 100644
--- a/src/include/acpi/acpi_apei.h
+++ b/src/include/acpi/acpi_apei.h
@@ -13,6 +13,19 @@
 
 #include <acpi/acpi.h>
 
+#define MAX_ERROR_BLOCK_SIZE      0x1000
+#define MAX_MCA_ERROR_BLOCK_SIZE  0x0400
+
+// Hardware Error Notification types. All other values are reserved
+#define HARDWARE_ERROR_NOTIFICATION_POLLED              0
+#define HARDWARE_ERROR_NOTIFICATION_EXTERNAL_INTERRUPT  1
+#define HARDWARE_ERROR_NOTIFICATION_LOCAL_INTERRUPT     2
+#define HARDWARE_ERROR_NOTIFICATION_SCI                 3
+#define HARDWARE_ERROR_NOTIFICATION_NMI                 4
+#define HARDWARE_ERROR_NOTIFICATION_CMCI                5
+#define HARDWARE_ERROR_NOTIFICATION_MCE                 6
+#define HARDWARE_ERROR_NOTIFICATION_GPIO                7
+
 /* HEST (Hardware Error Source Table) */
 typedef struct acpi_hest {
 	acpi_header_t header;
@@ -32,6 +45,19 @@ typedef struct acpi_hest_esd {
 					 */
 	u32 max_section_per_record;
 } __packed acpi_hest_esd_t;
+#define ACPI_APEI_ESD_TYPE_MCE          0 // Machine Check Exception
+#define ACPI_APEI_ESD_TYPE_CMC          1 // Corrected Machine Check
+#define ACPI_APEI_ESD_TYPE_NMI          2 // Non Maskable Interrupt
+#define ACPI_APEI_ESD_TYPE_RPORT_AER    6 // PCIe Root Port AER
+#define ACPI_APEI_ESD_TYPE_DEVICE_AER   7 // PCIe Device/Endpoint AER
+#define ACPI_APEI_ESD_TYPE_BRIDGE_AER   8 // PCIe Bridge AER
+#define ACPI_APEI_ESD_TYPE_GHE          9 // Generic Hardware Error
+#define ACPI_APEI_ESD_TYPE_GHE_V2      10 // Generic Hardware Error
+#define ACPI_APEI_ESD_TYPE_DMC         11 // Deferred Machine Check
+
+#define ERROR_SOURCE_FLAG_FIRMWARE_FIRST  BIT(0)
+#define ERROR_SOURCE_FLAG_GLOBAL          BIT(1)
+#define ERROR_SOURCE_FLAG_GHES_ASSIST     BIT(2)
 
 /* Hardware Error Notification */
 typedef struct acpi_hest_hen {

From 847d91b82e5c6bb18447a8ee19c950365d4b2877 Mon Sep 17 00:00:00 2001
From: Maximilian Brune <maximilian.brune@9elements.com>
Date: Thu, 11 Dec 2025 23:34:52 +0100
Subject: [PATCH 2819/3886] include/acpi/acpi_apei.h: Update APEI structs for
 better readability

Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: I380c793700b3b42373df556c17718e4fd2b147d5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90475
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
---
 src/acpi/acpi.c              |  4 ++--
 src/include/acpi/acpi_apei.h | 16 ++++++++--------
 2 files changed, 10 insertions(+), 10 deletions(-)

diff --git a/src/acpi/acpi.c b/src/acpi/acpi.c
index b22c4bc2c0..abdcf26160 100644
--- a/src/acpi/acpi.c
+++ b/src/acpi/acpi.c
@@ -648,7 +648,7 @@ void acpi_create_einj(acpi_einj_t *einj, uintptr_t addr, u8 actions)
 			.action = SET_ERROR_TYPE_WITH_ADDRESS,
 			.instruction = WRITE_REGISTER,
 			.flags = FLAG_PRESERVE,
-			.reg = EINJ_REG_MEMORY((u64)(uintptr_t)&einj_smi->setaddrtable),
+			.reg = EINJ_REG_MEMORY((u64)(uintptr_t)&einj_smi->set_addr_table),
 			.value = 1,
 			.mask = 0xffffffff
 		}
@@ -1027,7 +1027,7 @@ unsigned long acpi_create_hest_error_source(acpi_hest_t *hest,
 		memset(pos, 0, sizeof(acpi_hest_hen_t));
 		hen->type = 3;		/* SCI? */
 		hen->length = sizeof(acpi_hest_hen_t);
-		hen->conf_we = 0;	/* Configuration Write Enable. */
+		hen->conf_write_enable = 0;
 		hen->poll_interval = 0;
 		hen->vector = 0;
 		hen->sw2poll_threshold_val = 0;
diff --git a/src/include/acpi/acpi_apei.h b/src/include/acpi/acpi_apei.h
index 5f0b8a3a1b..3885994c25 100644
--- a/src/include/acpi/acpi_apei.h
+++ b/src/include/acpi/acpi_apei.h
@@ -63,7 +63,7 @@ typedef struct acpi_hest_esd {
 typedef struct acpi_hest_hen {
 	u8 type;
 	u8 length;
-	u16 conf_we;		/* Configuration Write Enable */
+	u16 conf_write_enable;
 	u32 poll_interval;
 	u32 vector;
 	u32 sw2poll_threshold_val;
@@ -240,13 +240,13 @@ typedef struct acpi_einj_trigger_table {
 } __packed acpi_einj_trigger_table_t;
 
 typedef struct set_error_type {
-	u32 errtype;
-	u32 vendorerrortype;
+	u32 err_type;
+	u32 vendor_error_type;
 	u32 flags;
-	u32 apicid;
-	u64 memaddr;
-	u64 memrange;
-	u32 pciesbdf;
+	u32 apic_id;
+	u64 mem_addr;
+	u64 mem_range;
+	u32 pcie_sbdf;
 } __packed set_error_type_t;
 
 #define EINJ_PARAM_NUM 6
@@ -259,7 +259,7 @@ typedef struct acpi_einj_smi {
 	u64 cmd_sts;
 	u64 einj_addr;
 	u64 einj_addr_msk;
-	set_error_type_t setaddrtable;
+	set_error_type_t set_addr_table;
 	u64 reserved[50];
 } __packed acpi_einj_smi_t;
 

From b70309350f8143bee2f0086c45ce1ecc4f4327f6 Mon Sep 17 00:00:00 2001
From: Maximilian Brune <maximilian.brune@9elements.com>
Date: Mon, 25 Aug 2025 16:25:47 +0200
Subject: [PATCH 2820/3886] arch/x86/acpi_bert_storage.c: Fix Error Section
 GUID compare
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

If the section guid is CPER_SEC_PROC_IA32X64_GUID we want the x86
processor specific section instead of the generic one.
This was probably some kind copy error from the line above.

Change-Id: I6a6a885bf8ab97cb5d256513cf8134078b707d3c
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Signed-off-by: Patrick Rudolph <patrick.rudolph@amd.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90476
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
---
 src/arch/x86/acpi_bert_storage.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/arch/x86/acpi_bert_storage.c b/src/arch/x86/acpi_bert_storage.c
index 2d5a055ec6..8b19403a5d 100644
--- a/src/arch/x86/acpi_bert_storage.c
+++ b/src/arch/x86/acpi_bert_storage.c
@@ -531,7 +531,7 @@ acpi_generic_error_status_t *bert_new_event(guid_t *guid)
 
 	if (!guidcmp(guid, &CPER_SEC_PROC_GENERIC_GUID))
 		r = bert_append_genproc(status);
-	else if (!guidcmp(guid, &CPER_SEC_PROC_GENERIC_GUID))
+	else if (!guidcmp(guid, &CPER_SEC_PROC_IA32X64_GUID))
 		r = bert_append_ia32x64(status);
 	else if (!guidcmp(guid, &CPER_SEC_FW_ERR_REC_REF_GUID))
 		r = bert_append_fw_err(status);

From f28997dcddd585d34924a3df59293453f9dcf033 Mon Sep 17 00:00:00 2001
From: Kapil Porwal <kapilporwal@google.com>
Date: Mon, 15 Dec 2025 18:44:18 +0530
Subject: [PATCH 2821/3886] soc/qualcomm/common: Add PD negotiation attribute
 macro

Define the QCLIB_GA_ENABLE_PD_NEGOTIATION bit in the QcLib global
attributes. This flag signals to QcLib that Power Delivery
negotiation should be performed.

BUG=b:457566143
TEST=Verify different boot modes on Google/Quenbi.
TEST=Verify that PD negotiation is skipped in normal mode.

Change-Id: Ia046f68ebeacaa1c1d9a73c4b957315c9f7b68b6
Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90512
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/soc/qualcomm/common/include/soc/qclib_common.h | 1 +
 1 file changed, 1 insertion(+)

diff --git a/src/soc/qualcomm/common/include/soc/qclib_common.h b/src/soc/qualcomm/common/include/soc/qclib_common.h
index 65c87d7ec7..8ce24f2b35 100644
--- a/src/soc/qualcomm/common/include/soc/qclib_common.h
+++ b/src/soc/qualcomm/common/include/soc/qclib_common.h
@@ -60,6 +60,7 @@ struct qclib_cb_if_table_entry {
 
 /* GA_BMASK_VALUES (global_attributes bit mask values) */
 #define QCLIB_GA_ENABLE_UART_LOGGING   BIT(0)
+#define QCLIB_GA_ENABLE_PD_NEGOTIATION BIT(1)
 #define QCLIB_GA_FORCE_COLD_REBOOT BIT(3)
 #define QCLIB_GA_DDR_FMAX_LIMIT_HYNIX8GB BIT(5)
 

From 173a32aa55656e687f6a47f78df4154cbb596941 Mon Sep 17 00:00:00 2001
From: Jayvik Desai <jayvik@google.com>
Date: Mon, 15 Dec 2025 16:23:54 +0530
Subject: [PATCH 2822/3886] MAINTAINERS: Add Jayvik Desai to Google Bluey &
 Qualcomm SoCs

Change-Id: Ie9059d68cc661fb421d8f280a77865a114ba4b78
Signed-off-by: Jayvik Desai <jayvik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90508
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 MAINTAINERS | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/MAINTAINERS b/MAINTAINERS
index a676f72b99..083f91e9e6 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -322,6 +322,7 @@ F:	src/mainboard/gigabyte/ga-h61m-series/
 GOOGLE BLUEY MAINBOARDS
 M:	Subrata Banik <subratabanik@google.com>
 M:	Kapil Porwal <kapilporwal@google.com>
+M:	Jayvik Desai <jayvik@google.com>
 F:	src/mainboard/google/bluey/
 
 GOOGLE REX MAINBOARDS
@@ -974,6 +975,7 @@ F:	src/vendorcode/mediatek/mt8192/
 QUALCOMM SOCS
 M:	Subrata Banik <subratabanik@google.com>
 M:	Kapil Porwal <kapilporwal@google.com>
+M:	Jayvik Desai <jayvik@google.com>
 F:	src/soc/qualcomm/
 
 ORPHANED ARM SOCS

From 4cc830349cbc6c786ec00e87b800eac7b4a7a504 Mon Sep 17 00:00:00 2001
From: Kenneth Chan <kenneth.chan@quanta.corp-partner.google.com>
Date: Thu, 11 Dec 2025 18:20:41 +0800
Subject: [PATCH 2823/3886] mb/google/rex/var/karis: Add fw_config probe to
 enable all wifi

Add fw_config probe to enable all wifi for factory usage.

TEST=Build and run Google/Rex/Karis

Change-Id: I4934699a9fc83feadae7c5e3c3027c3a11fb0f6e
Signed-off-by: Kenneth Chan <kenneth.chan@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90456
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jakub "Kuba" Czapiga <czapiga@google.com>
---
 src/mainboard/google/rex/variants/karis/overridetree.cb | 9 ++++++++-
 1 file changed, 8 insertions(+), 1 deletion(-)

diff --git a/src/mainboard/google/rex/variants/karis/overridetree.cb b/src/mainboard/google/rex/variants/karis/overridetree.cb
index a637e0474f..904d437986 100644
--- a/src/mainboard/google/rex/variants/karis/overridetree.cb
+++ b/src/mainboard/google/rex/variants/karis/overridetree.cb
@@ -24,7 +24,7 @@ fw_config
 	end
 	field KB_TYPE 12
 		option KB_TYPE_DEFAULT		0
-		option KB_TYPE_CA			1
+		option KB_TYPE_CA		1
 	end
 	field WIFI_TYPE 13
 		option WIFI_CNVI		0
@@ -34,6 +34,9 @@ fw_config
 		option DISABLE			0
 		option ENABLE			1
 	end
+	field FACTORY 16
+		option WIFI_ALL			1
+	end
 end
 
 chip soc/intel/meteorlake
@@ -356,6 +359,7 @@ chip soc/intel/meteorlake
 				register "enable_cnvi_ddr_rfim" = "true"
 				device generic 0 on
 					probe WIFI_TYPE WIFI_CNVI
+					probe FACTORY WIFI_ALL
 				end
 			end
 		end
@@ -527,6 +531,7 @@ chip soc/intel/meteorlake
 		end #I2C5
 		device ref pcie_rp5 on
 			probe WIFI_TYPE WIFI_PCIE
+			probe FACTORY WIFI_ALL
 			# Enable WLAN Card PCIE 5 using clk 5
 			register "pcie_rp[PCH_RP(5)]" = "{
 				.clk_src = 5,
@@ -539,6 +544,7 @@ chip soc/intel/meteorlake
 				use usb2_port10 as bluetooth_companion
 				device pci 00.0 on
 					probe WIFI_TYPE WIFI_PCIE
+					probe FACTORY WIFI_ALL
 				end
 			end
 			chip soc/intel/common/block/pcie/rtd3
@@ -547,6 +553,7 @@ chip soc/intel/meteorlake
 				register "srcclk_pin" = "5"
 				device generic 0 on
 					probe WIFI_TYPE WIFI_PCIE
+					probe FACTORY WIFI_ALL
 				end
 			end
 		end	#PCIE5 WLAN card

From e54b82b85b0731682e72133df2ead96dc523e268 Mon Sep 17 00:00:00 2001
From: Ian Feng <ian_feng@compal.corp-partner.google.com>
Date: Tue, 9 Dec 2025 09:39:07 +0800
Subject: [PATCH 2824/3886] mb/google/ocelot/var/kodkod: Enable pcie_rp5 to
 allow proper enumeration of pcie_rp6
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

pcie_rp5 and pcie_rp6 belong to the same PCIe controller group
(Port C1–C2). Within this controller, pcie_rp5 represents function 0
and pcie_rp6 represents function 1. For multi-function PCIe root
ports, function 0 must be enabled for the controller to initialize
fully.

If only pcie_rp6 (function 1) is enabled, the controller does not
complete initialization and the downstream LAN device fails to
enumerate. Enabling pcie_rp5 ensures the PCIe controller group is
brought up correctly and allows the RTL8111H LAN device behind
pcie_rp6 to enumerate as expected.

BUG=b:466908212
TEST=Build and boot to OS in kodkod.
kodkod:/ # pclspci -v
01:00.0 Class 0200: Device 10ec:8168 (rev 15)
	DeviceName: Ethernet controller
	Kernel driver in use: r8169

Change-Id: I4332f3d612f1f66cd30dda7da723c47bcfce35a3
Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90422
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Pranava Y N <pranavayn@google.com>
---
 src/mainboard/google/ocelot/variants/kodkod/overridetree.cb | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/src/mainboard/google/ocelot/variants/kodkod/overridetree.cb b/src/mainboard/google/ocelot/variants/kodkod/overridetree.cb
index 264ff4db4c..03c12dd9db 100644
--- a/src/mainboard/google/ocelot/variants/kodkod/overridetree.cb
+++ b/src/mainboard/google/ocelot/variants/kodkod/overridetree.cb
@@ -188,6 +188,9 @@ chip soc/intel/pantherlake
 				device generic 0 on end
 			end
 		end # Gen4 M.2 SSD
+
+		device ref pcie_rp5 on end
+
 		device ref pcie_rp6 on
 			register "pcie_rp[PCIE_RP(6)]" = "{
 				.clk_src = 2,

From 42c1947d9904d303bf17e937b94d1d2929b3af33 Mon Sep 17 00:00:00 2001
From: Kapil Porwal <kapilporwal@google.com>
Date: Mon, 15 Dec 2025 18:42:08 +0530
Subject: [PATCH 2825/3886] mb/google/bluey: Implement EC-based off-mode
 detection

Update off-mode detection logic to use ChromeEC host events. If
the system is powered on by AC insertion (without power button
or lid open events), identify the boot as off-mode charging.

BUG=b:457566143
TEST=Verify off-mode battery charging on Google/Quenbi.

Change-Id: Ibfbbf9cbeabd229595f625104f94eb814012e2f8
Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90511
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/google/bluey/charging.c | 16 ----------------
 src/mainboard/google/bluey/romstage.c | 26 +++++++++++++++++++++++++-
 2 files changed, 25 insertions(+), 17 deletions(-)

diff --git a/src/mainboard/google/bluey/charging.c b/src/mainboard/google/bluey/charging.c
index 56deedcdb9..bbb849d438 100644
--- a/src/mainboard/google/bluey/charging.c
+++ b/src/mainboard/google/bluey/charging.c
@@ -43,19 +43,3 @@ void disable_slow_battery_charging(void)
 	spmi_write8(SMB1_CHGR_CHRG_EN_CMD, CHRG_DISABLE);
 	spmi_write8(SMB2_CHGR_CHRG_EN_CMD, CHRG_DISABLE);
 }
-
-/*
- * is_off_mode - Check if the system is booting due to an off-mode power event.
- *
- * This function provides the board-level policy wrapper for detecting if the
- * system power-on was triggered by an external charging event (e.g., cable
- * insertion). This is typically used to enter LB_BOOT_MODE_OFFMODE_CHARGING.
- *
- * @return true if the system was triggered by a specific off-mode reason
- * (e.g., charging cable insertion).
- * @return false otherwise.
- */
-bool is_off_mode(void)
-{
-	return is_pon_on_ac();
-}
diff --git a/src/mainboard/google/bluey/romstage.c b/src/mainboard/google/bluey/romstage.c
index c2cbf5b7c4..657c7ad177 100644
--- a/src/mainboard/google/bluey/romstage.c
+++ b/src/mainboard/google/bluey/romstage.c
@@ -14,6 +14,31 @@
 
 static enum boot_mode_t boot_mode = LB_BOOT_MODE_NORMAL;
 
+/*
+ * is_off_mode - Check if the system is booting due to an off-mode power event.
+ *
+ * This function provides the board-level policy wrapper for detecting if the
+ * system power-on was triggered by an external charging event (e.g., cable
+ * insertion). This is typically used to enter LB_BOOT_MODE_OFFMODE_CHARGING.
+ *
+ * @return true if the system was triggered by a specific off-mode reason
+ * (e.g., charging cable insertion).
+ * @return false otherwise.
+ */
+bool is_off_mode(void)
+{
+	const uint64_t manual_pwron_event_mask =
+		(EC_HOST_EVENT_MASK(EC_HOST_EVENT_POWER_BUTTON) |
+		EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN));
+	uint64_t ec_events = google_chromeec_get_events_b();
+
+	if (!(ec_events & manual_pwron_event_mask) &&
+		(ec_events & EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_CONNECTED)))
+		return true;
+
+	return false;
+}
+
 static void set_boot_mode(void)
 {
 	if (!CONFIG(EC_GOOGLE_CHROMEEC))
@@ -35,7 +60,6 @@ void platform_romstage_main(void)
 	/* QCLib: DDR init & train */
 	qclib_load_and_run();
 
-	/* Underlying PMIC registers are accessible only at this point */
 	set_boot_mode();
 
 	aop_fw_load_reset();

From 1dc3e45f7ceb310419546117b2338d1a4f3c7032 Mon Sep 17 00:00:00 2001
From: Yu-Ping Wu <yupingso@chromium.org>
Date: Tue, 16 Dec 2025 11:38:34 +0800
Subject: [PATCH 2826/3886] mipi: Support passing user data to mipi_cmd_func_t

The mipi_cmd_func_t callback for mipi_panel_parse_init_commands()
currently doesn't support passing additional data for storing context.
Therefore user code would need to store any extra data in global
variables. For example, in the upcoming DSI dual channel support for
MediaTek platforms, the callback needs to know whether the MIPI panel
supports dual channel or not. To support that use case, pass an extra
`user_data` argument to mipi_cmd_func_t.

BUG=b:424782827
TEST=util/abuild/abuild -x -t GOOGLE_SAPPHIRE -a
BRANCH=none

Change-Id: Id5d7b168cdcadfe8d8435c29d7e855a535815057
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90519
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
---
 src/drivers/mipi/panel.c              |  5 +++--
 src/include/mipi/panel.h              | 13 +++++++++++--
 src/soc/mediatek/common/dsi_common.c  |  5 +++--
 src/soc/qualcomm/sc7180/display/dsi.c |  5 +++--
 4 files changed, 20 insertions(+), 8 deletions(-)

diff --git a/src/drivers/mipi/panel.c b/src/drivers/mipi/panel.c
index 7279d17b9a..0182a8594a 100644
--- a/src/drivers/mipi/panel.c
+++ b/src/drivers/mipi/panel.c
@@ -5,7 +5,8 @@
 #include <mipi/panel.h>
 #include <types.h>
 
-enum cb_err mipi_panel_parse_init_commands(const void *buf, mipi_cmd_func_t cmd_func)
+enum cb_err mipi_panel_parse_init_commands(const void *buf, mipi_cmd_func_t cmd_func,
+					   void *user_data)
 {
 	const struct panel_init_command *init = buf;
 	enum mipi_dsi_transaction type;
@@ -69,7 +70,7 @@ enum cb_err mipi_panel_parse_init_commands(const void *buf, mipi_cmd_func_t cmd_
 			return CB_ERR;
 		}
 
-		enum cb_err ret = cmd_func(type, init->data, len);
+		enum cb_err ret = cmd_func(type, init->data, len, user_data);
 		if (ret != CB_SUCCESS)
 			return ret;
 		buf += len;
diff --git a/src/include/mipi/panel.h b/src/include/mipi/panel.h
index 938f87dc3b..d306f06fb4 100644
--- a/src/include/mipi/panel.h
+++ b/src/include/mipi/panel.h
@@ -223,10 +223,19 @@ struct panel_serializable_data {
 	u8 init[]; /* A packed array of panel_init_command */
 };
 
-typedef enum cb_err (*mipi_cmd_func_t)(enum mipi_dsi_transaction type, const u8 *data, u8 len);
+/*
+ * Callback function type for mipi_panel_parse_init_commands().
+ * @param type		MIPI DSI transaction type.
+ * @param data		panel_init_command data.
+ * @param len		panel_init_command len.
+ * @param user_data	Arbitrary user data passed from mipi_panel_parse_init_commands().
+ */
+typedef enum cb_err (*mipi_cmd_func_t)(enum mipi_dsi_transaction type, const u8 *data, u8 len,
+				       void *user_data);
 
 /* Parse a command array and call cmd_func() for each entry. Delays get handled internally. */
-enum cb_err mipi_panel_parse_init_commands(const void *buf, mipi_cmd_func_t cmd_func);
+enum cb_err mipi_panel_parse_init_commands(const void *buf, mipi_cmd_func_t cmd_func,
+					   void *user_data);
 
 #define PANEL_DCS(...) \
 	PANEL_CMD_DCS, \
diff --git a/src/soc/mediatek/common/dsi_common.c b/src/soc/mediatek/common/dsi_common.c
index 5ee8985dfd..2298aa0ace 100644
--- a/src/soc/mediatek/common/dsi_common.c
+++ b/src/soc/mediatek/common/dsi_common.c
@@ -313,7 +313,8 @@ static bool mtk_dsi_is_read_command(enum mipi_dsi_transaction type)
 	}
 }
 
-static enum cb_err mtk_dsi_cmdq(enum mipi_dsi_transaction type, const u8 *data, u8 len)
+static enum cb_err mtk_dsi_cmdq(enum mipi_dsi_transaction type, const u8 *data, u8 len,
+				void *user_data)
 {
 	const u8 *tx_buf = data;
 	u32 config;
@@ -399,7 +400,7 @@ int mtk_dsi_init(u32 mode_flags, u32 format, u32 lanes, const struct edid *edid,
 	mtk_dsi_config_vdo_timing(mode_flags, format, lanes, edid, &phy_timing);
 	mtk_dsi_clk_hs_mode_enable();
 	if (init_commands)
-		mipi_panel_parse_init_commands(init_commands, mtk_dsi_cmdq);
+		mipi_panel_parse_init_commands(init_commands, mtk_dsi_cmdq, NULL);
 	mtk_dsi_set_mode(mode_flags);
 	mtk_dsi_start();
 
diff --git a/src/soc/qualcomm/sc7180/display/dsi.c b/src/soc/qualcomm/sc7180/display/dsi.c
index 9e6977ca7b..c1e75e1090 100644
--- a/src/soc/qualcomm/sc7180/display/dsi.c
+++ b/src/soc/qualcomm/sc7180/display/dsi.c
@@ -205,7 +205,7 @@ static int mdss_dsi_cmd_dma_trigger_for_panel(void)
 }
 
 static enum cb_err mdss_dsi_send_init_cmd(enum mipi_dsi_transaction type, const u8 *body,
-					  u8 len)
+					  u8 len, void *user_data)
 {
 	uint8_t *pload = _dma_coherent;
 	uint32_t size;
@@ -287,7 +287,8 @@ enum cb_err mdss_dsi_panel_initialize(const u8 *init_cmds)
 	/* Enable command mode before sending the commands */
 	write32(&dsi0->ctrl, ctrl_mode | 0x04);
 
-	enum cb_err ret = mipi_panel_parse_init_commands(init_cmds, mdss_dsi_send_init_cmd);
+	enum cb_err ret = mipi_panel_parse_init_commands(init_cmds, mdss_dsi_send_init_cmd,
+							 NULL);
 	write32(&dsi0->ctrl, ctrl_mode);
 	mdss_dsi_clear_intr();
 

From b67725d3f51c141b9ee3c4ad9c16cafd38a54e44 Mon Sep 17 00:00:00 2001
From: Kapil Porwal <kapilporwal@google.com>
Date: Wed, 17 Dec 2025 15:12:36 +0530
Subject: [PATCH 2827/3886] Revert "mb/google/bluey: Implement EC-based
 off-mode detection"

This reverts commit 42c1947d9904d303bf17e937b94d1d2929b3af33.

Reason: It breaks warm reboot flow.

Change-Id: Id3662c70853a4bbb14870d2d0225396f66ea5dee
Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90540
Reviewed-by: Jayvik Desai <jayvik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Pranava Y N <pranavayn@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
---
 src/mainboard/google/bluey/charging.c | 16 ++++++++++++++++
 src/mainboard/google/bluey/romstage.c | 26 +-------------------------
 2 files changed, 17 insertions(+), 25 deletions(-)

diff --git a/src/mainboard/google/bluey/charging.c b/src/mainboard/google/bluey/charging.c
index bbb849d438..56deedcdb9 100644
--- a/src/mainboard/google/bluey/charging.c
+++ b/src/mainboard/google/bluey/charging.c
@@ -43,3 +43,19 @@ void disable_slow_battery_charging(void)
 	spmi_write8(SMB1_CHGR_CHRG_EN_CMD, CHRG_DISABLE);
 	spmi_write8(SMB2_CHGR_CHRG_EN_CMD, CHRG_DISABLE);
 }
+
+/*
+ * is_off_mode - Check if the system is booting due to an off-mode power event.
+ *
+ * This function provides the board-level policy wrapper for detecting if the
+ * system power-on was triggered by an external charging event (e.g., cable
+ * insertion). This is typically used to enter LB_BOOT_MODE_OFFMODE_CHARGING.
+ *
+ * @return true if the system was triggered by a specific off-mode reason
+ * (e.g., charging cable insertion).
+ * @return false otherwise.
+ */
+bool is_off_mode(void)
+{
+	return is_pon_on_ac();
+}
diff --git a/src/mainboard/google/bluey/romstage.c b/src/mainboard/google/bluey/romstage.c
index 657c7ad177..c2cbf5b7c4 100644
--- a/src/mainboard/google/bluey/romstage.c
+++ b/src/mainboard/google/bluey/romstage.c
@@ -14,31 +14,6 @@
 
 static enum boot_mode_t boot_mode = LB_BOOT_MODE_NORMAL;
 
-/*
- * is_off_mode - Check if the system is booting due to an off-mode power event.
- *
- * This function provides the board-level policy wrapper for detecting if the
- * system power-on was triggered by an external charging event (e.g., cable
- * insertion). This is typically used to enter LB_BOOT_MODE_OFFMODE_CHARGING.
- *
- * @return true if the system was triggered by a specific off-mode reason
- * (e.g., charging cable insertion).
- * @return false otherwise.
- */
-bool is_off_mode(void)
-{
-	const uint64_t manual_pwron_event_mask =
-		(EC_HOST_EVENT_MASK(EC_HOST_EVENT_POWER_BUTTON) |
-		EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN));
-	uint64_t ec_events = google_chromeec_get_events_b();
-
-	if (!(ec_events & manual_pwron_event_mask) &&
-		(ec_events & EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_CONNECTED)))
-		return true;
-
-	return false;
-}
-
 static void set_boot_mode(void)
 {
 	if (!CONFIG(EC_GOOGLE_CHROMEEC))
@@ -60,6 +35,7 @@ void platform_romstage_main(void)
 	/* QCLib: DDR init & train */
 	qclib_load_and_run();
 
+	/* Underlying PMIC registers are accessible only at this point */
 	set_boot_mode();
 
 	aop_fw_load_reset();

From 1b5f1055959ef0574c81c5d55eea75a0f22a46cd Mon Sep 17 00:00:00 2001
From: Megha Verma <megha.verma@intel.com>
Date: Thu, 13 Nov 2025 14:29:50 +0530
Subject: [PATCH 2828/3886] mb/google/ocelot/var/ocelot: disable ISH UART0 RX
 pin

On WCL RVP, ISH (Intel Sensor Hub) shares UART with FPS (Finger Print
Sensor), we can enable either ISH UART or FPS UART, or disable both
UART by changing the DIP switch settings. When DIP switch is not set
for ISH, ISH RX signal is disconnected, causing ISH low power mode
failure. Therefore, NC ISH RX pin mux to minimize the impact on ISH PM.
As a result, ISH console won't accept input since this pin is not
connected.

BUG=b:428084925
TEST=DIP SW1317 3-6, 4-5 on WCL RVP DT card ON to enable FPS UART,
ISH main firmware boots up and runs successfully.
SW1317 all switches OFF to disable both FPS and ISH UART, ISH main
firmware boots up and runs successfully.
Put system into suspend state and resume back. System enters into
low power mode as substate_residencies are updated. Verified using
console command "cat /sys/kernel/debug/pmc_core/substate_residencies".

Change-Id: I1165e0151c0a6d0e82038215703626e863739b39
Signed-off-by: Megha Verma <megha.verma@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90022
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Bhat D, Krishna P <krishna.p.bhat.d@intel.com>
Reviewed-by: P, Usha <usha.p@intel.com>
---
 src/mainboard/google/ocelot/variants/ocelot/fw_config.c | 4 ----
 src/mainboard/google/ocelot/variants/ocelot/gpio.c      | 2 ++
 2 files changed, 2 insertions(+), 4 deletions(-)

diff --git a/src/mainboard/google/ocelot/variants/ocelot/fw_config.c b/src/mainboard/google/ocelot/variants/ocelot/fw_config.c
index b299a406f2..e89c59482f 100644
--- a/src/mainboard/google/ocelot/variants/ocelot/fw_config.c
+++ b/src/mainboard/google/ocelot/variants/ocelot/fw_config.c
@@ -392,8 +392,6 @@ static const struct pad_config ish_disable_pads[] = {
 	PAD_NC(GPP_B22, NONE),
 	/* GPP_B23:     ISH_GP_6_SNSR_HDR */
 	PAD_NC(GPP_B23, NONE),
-	/* GPP_D05:     ISH_UART0_ECAIC_RXD */
-	PAD_NC(GPP_D05, NONE),
 	/* GPP_D06:     ISH_UART0_ECAIC_TXD */
 	PAD_NC(GPP_D06, NONE),
 	/* GPP_F23:     SMC_LID / ISH_GP9A*/
@@ -413,8 +411,6 @@ static const struct pad_config ish_enable_pads[] = {
 	PAD_CFG_NF(GPP_B22, NONE, DEEP, NF4),
 	/* GPP_B23:     ISH_GP_6_SNSR_HDR */
 	PAD_CFG_NF(GPP_B23, NONE, DEEP, NF4),
-	/* GPP_D05:     ISH_UART0_ECAIC_RXD */
-	PAD_CFG_NF(GPP_D05, NONE, DEEP, NF2),
 	/* GPP_D06:     ISH_UART0_ECAIC_TXD */
 	PAD_CFG_NF(GPP_D06, NONE, DEEP, NF2),
 	/* GPP_F23:     SMC_LID / ISH_GP9A*/
diff --git a/src/mainboard/google/ocelot/variants/ocelot/gpio.c b/src/mainboard/google/ocelot/variants/ocelot/gpio.c
index 405a424600..9166668efb 100644
--- a/src/mainboard/google/ocelot/variants/ocelot/gpio.c
+++ b/src/mainboard/google/ocelot/variants/ocelot/gpio.c
@@ -135,6 +135,8 @@ static const struct pad_config gpio_table[] = {
 	PAD_CFG_GPO(GPP_D02, 0, DEEP),
 	/* GPP_D03:     X4_SLOT_WAKE_N */
 	PAD_CFG_GPI_SCI_LOW(GPP_D03, NONE, DEEP, LEVEL),
+	/* GPP_D05:     disable ISH_UART0_RXD */
+	PAD_NC(GPP_D05, NONE),
 	/* GPP_D07:     ISH_UART0_RTS_N_SNSR_HDR */
 	PAD_NC(GPP_D07, NONE),
 	/* GPP_D08:     ISH_UART0_CTS_N_SNSR_HDR */

From a4cc17848609bdcc11c6112fd225bb74f84ba0c1 Mon Sep 17 00:00:00 2001
From: Swathi Tamilselvan <tswathi@qualcomm.corp-partner.google.com>
Date: Tue, 16 Dec 2025 10:27:59 +0530
Subject: [PATCH 2829/3886] soc/qualcomm/common: Map AOP CMD-DB region as
 uncached region in MMU

Add support to map AOP CMD-DB region as uncached region in MMU. The
reason for this change is that the CMD-DB region is configured as
read-only region and any write to this region will be treated as
fatal. Mapping it as cacheable can lead to cache-line writebacks,
causing invalid accesses and device crashes.

Test=1. Create an image.serial.bin and ensure it boots on X1P42100.
MMU Table dump from Trace32:
'M:0000000081C60000--0000000081C7FFFF|    AM:0000000081C60000--0000000081C7FFFF| s  |  | 00001000| read/write access        exec        | yes| inn| non-cacheable                     |  1| no | \\ramstage\Global\_dram_aop_cmd_db'

Change-Id: I296b505f670f3be28eb998fdac8164a85bf757b0
Signed-off-by: Swathi Tamilselvan <tswathi@qualcomm.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90464
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/soc/qualcomm/common/include/soc/symbols_common.h | 2 ++
 src/soc/qualcomm/common/mmu.c                        | 3 +++
 2 files changed, 5 insertions(+)

diff --git a/src/soc/qualcomm/common/include/soc/symbols_common.h b/src/soc/qualcomm/common/include/soc/symbols_common.h
index 6d6ff38635..ee2d3510b6 100644
--- a/src/soc/qualcomm/common/include/soc/symbols_common.h
+++ b/src/soc/qualcomm/common/include/soc/symbols_common.h
@@ -11,6 +11,8 @@ DECLARE_REGION(ddr_information);
 DECLARE_REGION(ssram)
 DECLARE_REGION(bsram)
 DECLARE_REGION(dram_aop)
+DECLARE_OPTIONAL_REGION(dram_aop_cmd_db)
+DECLARE_REGION(dram_aop_config)
 DECLARE_REGION(dram_soc)
 DECLARE_REGION(dcb)
 DECLARE_REGION(dtb)
diff --git a/src/soc/qualcomm/common/mmu.c b/src/soc/qualcomm/common/mmu.c
index b589d966a9..480b7a9fea 100644
--- a/src/soc/qualcomm/common/mmu.c
+++ b/src/soc/qualcomm/common/mmu.c
@@ -76,4 +76,7 @@ void qc_mmu_dram_config_post_dram_init(size_t ddr_size)
 	if (_preram_dma_coherent != _postram_dma_coherent)
 		mmu_config_range((void *)_postram_dma_coherent, REGION_SIZE(postram_dma_coherent),
 							UNCACHED_RAM);
+
+	if (REGION_SIZE(dram_aop_cmd_db) != 0)
+		mmu_config_range((void *)_dram_aop_cmd_db, REGION_SIZE(dram_aop_cmd_db), UNCACHED_RAM);
 }

From 2277edff88b870fcb6217fdef85292589b0dcbcb Mon Sep 17 00:00:00 2001
From: Swathi Tamilselvan <tswathi@qualcomm.corp-partner.google.com>
Date: Tue, 16 Dec 2025 10:30:03 +0530
Subject: [PATCH 2830/3886] soc/qualcomm/x1p42100: Split dram_aop region to map
 dram_aop_cmd_db as non-cacheable

Add support to split the dram_aop memory region into three in order to
map dram_aop_cmd_db as non-cacheable. The purpose of dram_aop_config
is memory region where the aop_devcfg.mbn image is loaded.

Test=1. Build and boot on X1P42100.
2. Dump the MMU table in coreboot ramstage and verify whether the region
is mapped as non-cacheable.

Change-Id: Id73d878b7d343f248a845bd5727c43e22c4c348a
Signed-off-by: Swathi Tamilselvan <tswathi@qualcomm.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90521
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/soc/qualcomm/x1p42100/memlayout.ld | 8 +++++++-
 src/soc/qualcomm/x1p42100/soc.c        | 2 ++
 2 files changed, 9 insertions(+), 1 deletion(-)

diff --git a/src/soc/qualcomm/x1p42100/memlayout.ld b/src/soc/qualcomm/x1p42100/memlayout.ld
index ae1ee96355..110444a87a 100644
--- a/src/soc/qualcomm/x1p42100/memlayout.ld
+++ b/src/soc/qualcomm/x1p42100/memlayout.ld
@@ -73,6 +73,10 @@
  * 0x81CE0000    +----------------------------------------------------------+      |        |
  *               |                  dram_tme_crashdump                      |      |        |
  * 0x81CA0000    +----------------------------------------------------------+      |        |
+ *               |                   dram_aop_config                        |      |        |
+ * 0x81C80000    +----------------------------------------------------------+      |        |
+ *               |                   dram_aop_cmd_db                        |      |        |
+ * 0x81C60000    +----------------------------------------------------------+      |        |
  *               |                       dram_aop                           |      |        |
  * 0x81C00000    +----------------------------------------------------------+      |        |
  *               |                     dram_ramdump                         |      |        |
@@ -240,7 +244,9 @@ SECTIONS
 	REGION(dram_xbl_log, 0x81A00000, 0x40000, 4K)
 	REGION(dram_ramdump, 0x81A40000, 0x1C0000, 4K)
 
-	REGION(dram_aop, 0x81C00000, 0xA0000, 4K)
+	REGION(dram_aop, 0x81C00000, 0x60000, 4K)
+	REGION(dram_aop_cmd_db, 0x81C60000, 0x20000, 4K)
+	REGION(dram_aop_config, 0x81C80000, 0x20000, 4K)
 	REGION(dram_tme_crashdump, 0x81CA0000, 0x40000, 4K)
 	REGION(dram_tme_log, 0x81CE0000, 0x4000, 4K)
 	REGION(dram_dc_log, 0x81CE4000, 0x10000, 4K)
diff --git a/src/soc/qualcomm/x1p42100/soc.c b/src/soc/qualcomm/x1p42100/soc.c
index b4afd98139..d1762237d5 100644
--- a/src/soc/qualcomm/x1p42100/soc.c
+++ b/src/soc/qualcomm/x1p42100/soc.c
@@ -30,6 +30,7 @@ static void soc_read_resources(struct device *dev)
 	for (int i = 0; i < count; i++)
 		ram_range(dev, index++, (uintptr_t)config[i].offset, config[i].size);
 
+	mmio_range(dev, index++, (uintptr_t)_dram_aop_cmd_db, REGION_SIZE(dram_aop_cmd_db));
 	reserved_ram_range(dev, index++, (uintptr_t)_dram_ncc, REGION_SIZE(dram_ncc));
 	reserved_ram_range(dev, index++, (uintptr_t)_dram_cpucp, REGION_SIZE(dram_cpucp));
 	reserved_ram_range(dev, index++, (uintptr_t)_dram_xbl_log, REGION_SIZE(dram_xbl_log));
@@ -39,6 +40,7 @@ static void soc_read_resources(struct device *dev)
 	reserved_ram_range(dev, index++, (uintptr_t)_dram_tz, REGION_SIZE(dram_tz));
 
 	reserved_ram_range(dev, index++, (uintptr_t)_dram_aop, REGION_SIZE(dram_aop));
+	reserved_ram_range(dev, index++, (uintptr_t)_dram_aop_config, REGION_SIZE(dram_aop_config));
 	reserved_ram_range(dev, index++, (uintptr_t)_dram_tme_crashdump, REGION_SIZE(dram_tme_crashdump));
 	reserved_ram_range(dev, index++, (uintptr_t)_dram_tme_log, REGION_SIZE(dram_tme_log));
 	reserved_ram_range(dev, index++, (uintptr_t)_dram_dc_log, REGION_SIZE(dram_dc_log));

From 01bc527afa2af5818eefab28948c4189da65f910 Mon Sep 17 00:00:00 2001
From: Swathi Tamilselvan <tswathi@qualcomm.corp-partner.google.com>
Date: Wed, 10 Dec 2025 16:12:53 +0530
Subject: [PATCH 2831/3886] soc/qualcomm/common: Add CMD-DB driver support

Introduce CMD-DB driver to enable reading command database entries,
querying SoC resource data, and providing helper functions required
by AOP and other subsystems.

Test=Create an image.serial.bin and ensure it boots on X1P42100.

Change-Id: I3788bf7c97cc1133ae4893f4fdeaf36882e71276
Signed-off-by: Swathi Tamilselvan <tswathi@qualcomm.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90465
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
---
 src/soc/qualcomm/common/cmd_db.c             | 247 +++++++++++++++++++
 src/soc/qualcomm/common/include/soc/cmd_db.h |  91 +++++++
 src/soc/qualcomm/x1p42100/Makefile.mk        |   1 +
 3 files changed, 339 insertions(+)
 create mode 100644 src/soc/qualcomm/common/cmd_db.c
 create mode 100644 src/soc/qualcomm/common/include/soc/cmd_db.h

diff --git a/src/soc/qualcomm/common/cmd_db.c b/src/soc/qualcomm/common/cmd_db.c
new file mode 100644
index 0000000000..fbe3acd96f
--- /dev/null
+++ b/src/soc/qualcomm/common/cmd_db.c
@@ -0,0 +1,247 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <console/console.h>
+#include <device/mmio.h>
+#include <string.h>
+#include <soc/cmd_db.h>
+#include <types.h>
+#include <string.h>
+#include <endian.h>
+
+/**
+ * struct entry_header: header for each entry in cmd_db
+ *
+ * @id: resource's identifier
+ * @priority: unused
+ * @addr: the address of the resource
+ * @len: length of the data
+ * @offset: offset from :@data_offset, start of the data
+ */
+struct entry_header {
+	u8 id[8];
+	u32 priority[NUM_PRIORITY];
+	u32 addr;
+	u16 len;
+	u16 offset;
+} __packed;
+/**
+ * struct rsc_hdr: resource header information
+ *
+ * @slv_id: id for the resource
+ * @header_offset: entry's header at offset from the end of the cmd_db_header
+ * @data_offset: entry's data at offset from the end of the cmd_db_header
+ * @cnt: number of entries for HW type
+ * @version: MSB is major, LSB is minor
+ * @reserved: reserved for future use.
+ */
+struct rsc_hdr {
+	u16 slv_id;
+	u16 header_offset;
+	u16 data_offset;
+	u16 cnt;
+	u16 version;
+	u16 reserved[3];
+} __packed;
+
+/**
+ * struct cmd_db_header: The DB header information
+ *
+ * @version: The cmd db version
+ * @magic: constant expected in the database
+ * @header: array of resources
+ * @checksum: checksum for the header. Unused.
+ * @reserved: reserved memory
+ * @data: driver specific data
+ */
+struct cmd_db_header {
+	u32 version;
+	u8 magic[4];
+	struct rsc_hdr header[MAX_SLV_ID];
+	u32 checksum;
+	u32 reserved;
+	u8 data[];
+} __packed;
+
+/**
+ * DOC: Description of the Command DB database.
+ *
+ * At the start of the command DB memory is the cmd_db_header structure.
+ * The cmd_db_header holds the version, checksum, magic key as well as an
+ * array for header for each slave (depicted by the rsc_header). Each h/w
+ * based accelerator is a 'slave' (shared resource) and has slave id indicating
+ * the type of accelerator. The rsc_header is the header for such individual
+ * slaves of a given type. The entries for each of these slaves begin at the
+ * rsc_hdr.header_offset. In addition each slave could have auxiliary data
+ * that may be needed by the driver. The data for the slave starts at the
+ * entry_header.offset to the location pointed to by the rsc_hdr.data_offset.
+ *
+ * Drivers have a stringified key to a slave/resource. They can query the slave
+ * information and get the slave id and the auxiliary data and the length of the
+ * data. Using this information, they can format the request to be sent to the
+ * h/w accelerator and request a resource state.
+ */
+
+static const u8 CMD_DB_MAGIC[] = { 0xdb, 0x30, 0x03, 0x0c };
+
+static struct cmd_db_header *cmd_db_header;
+
+static bool cmd_db_magic_matches(const struct cmd_db_header *header)
+{
+	return memcmp(header->magic, CMD_DB_MAGIC, sizeof(CMD_DB_MAGIC)) == 0;
+}
+
+static inline const void *rsc_to_entry_header(const struct rsc_hdr *hdr)
+{
+	u16 offset = hdr->header_offset;
+	return cmd_db_header->data + offset;
+}
+
+static inline void *rsc_offset(const struct rsc_hdr *hdr,
+			       const struct entry_header *ent)
+{
+	u16 offset = hdr->data_offset;
+	u16 loffset = ent->offset;
+
+	return cmd_db_header->data + offset + loffset;
+}
+
+enum cb_err cmd_db_ready(void)
+{
+	if (cmd_db_header == NULL)
+		return CB_ERR;
+	else if (!cmd_db_magic_matches(cmd_db_header))
+		return CB_ERR;
+
+	return CB_SUCCESS;
+}
+
+static enum cb_err cmd_db_get_header(const char *id,
+				     const struct entry_header **eh,
+				     const struct rsc_hdr **rh)
+{
+	const struct rsc_hdr *rsc_hdr;
+	const struct entry_header *ent;
+	enum cb_err ret;
+	int i, j;
+	u8 query[sizeof(ent->id)];
+	size_t id_len;
+
+	ret = cmd_db_ready();
+	if (ret != CB_SUCCESS)
+		return ret;
+
+	memset(query, 0, sizeof(query));
+	id_len = strlen(id);
+	if (id_len > sizeof(query))
+		id_len = sizeof(query);
+	memcpy(query, id, id_len);
+
+	for (i = 0; i < MAX_SLV_ID; i++) {
+		rsc_hdr = &cmd_db_header->header[i];
+		if (!rsc_hdr->slv_id)
+			break;
+
+		ent = rsc_to_entry_header(rsc_hdr);
+		for (j = 0; j < rsc_hdr->cnt; j++, ent++) {
+			if (memcmp(ent->id, query, sizeof(ent->id)) == 0) {
+				if (eh)
+					*eh = ent;
+				if (rh)
+					*rh = rsc_hdr;
+				return CB_SUCCESS;
+			}
+		}
+	}
+
+	return CB_ERR;
+}
+
+u32 cmd_db_read_addr(const char *id)
+{
+	enum cb_err ret;
+	const struct entry_header *ent;
+
+	ret = cmd_db_get_header(id, &ent, NULL);
+	if (ret != CB_SUCCESS)
+		return 0;
+
+	return ent->addr;
+}
+
+const void *cmd_db_read_aux_data(const char *id, size_t *len)
+{
+	enum cb_err ret;
+	const struct entry_header *ent;
+	const struct rsc_hdr *rsc_hdr;
+
+	ret = cmd_db_get_header(id, &ent, &rsc_hdr);
+	if (ret != CB_SUCCESS)
+		return NULL;
+
+	if (len)
+		*len = ent->len;
+
+	return rsc_offset(rsc_hdr, ent);
+}
+
+bool cmd_db_match_resource_addr(u32 addr1, u32 addr2)
+{
+	if (addr1 == addr2)
+		return true;
+	else if (SLAVE_ID(addr1) == CMD_DB_HW_VRM &&
+		 VRM_ADDR(addr1) == VRM_ADDR(addr2))
+		return true;
+
+	return false;
+}
+
+enum cmd_db_hw_type cmd_db_read_slave_id(const char *id)
+{
+	enum cb_err ret;
+	const struct entry_header *ent;
+	u32 addr;
+
+	ret = cmd_db_get_header(id, &ent, NULL);
+	if (ret != CB_SUCCESS)
+		return CMD_DB_HW_INVALID;
+
+	addr = ent->addr;
+	return (addr >> SLAVE_ID_SHIFT) & SLAVE_ID_MASK;
+}
+
+bool cmd_db_is_standalone(void)
+{
+	enum cb_err ret = cmd_db_ready();
+	u32 standalone;
+
+	if (ret != CB_SUCCESS)
+		return false;
+
+	standalone = cmd_db_header->reserved & CMD_DB_STANDALONE_MASK;
+	return standalone != 0;
+}
+
+enum cb_err cmd_db_init(uintptr_t base, size_t size)
+{
+	if (base == 0 || size == 0) {
+		printk(BIOS_ERR, "CMD_DB: Invalid base address or size\n");
+		return CB_ERR;
+	}
+
+	/* Map the command DB memory region */
+	cmd_db_header = (struct cmd_db_header *)base;
+
+	if (!cmd_db_magic_matches(cmd_db_header)) {
+		printk(BIOS_ERR, "CMD_DB: Invalid Command DB Magic\n");
+		cmd_db_header = NULL;
+		return CB_ERR;
+	}
+
+	printk(BIOS_DEBUG, "CMD_DB: Initialized at 0x%lx, size: 0x%zx\n",
+	       base, size);
+
+	if (cmd_db_is_standalone())
+		printk(BIOS_DEBUG, "CMD_DB: Running in standalone mode\n");
+
+	return CB_SUCCESS;
+}
diff --git a/src/soc/qualcomm/common/include/soc/cmd_db.h b/src/soc/qualcomm/common/include/soc/cmd_db.h
new file mode 100644
index 0000000000..d508fce15b
--- /dev/null
+++ b/src/soc/qualcomm/common/include/soc/cmd_db.h
@@ -0,0 +1,91 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef __SOC_QUALCOMM_CMD_DB_H__
+#define __SOC_QUALCOMM_CMD_DB_H__
+
+#include <types.h>
+
+#define NUM_PRIORITY		2
+#define MAX_SLV_ID		8
+#define SLAVE_ID_MASK		0x7
+#define SLAVE_ID_SHIFT		16
+#define CMD_DB_STANDALONE_MASK	BIT(0)
+
+#define SLAVE_ID(addr)		(((addr) >> 16) & 0xF)
+#define VRM_ADDR(addr)		(((addr) >> 4) & 0xFFFF)
+
+enum cmd_db_hw_type {
+	CMD_DB_HW_INVALID = 0,
+	CMD_DB_HW_MIN     = 3,
+	CMD_DB_HW_ARC     = CMD_DB_HW_MIN,
+	CMD_DB_HW_VRM     = 4,
+	CMD_DB_HW_BCM     = 5,
+	CMD_DB_HW_MAX     = CMD_DB_HW_BCM,
+	CMD_DB_HW_ALL     = 0xff,
+};
+
+/**
+ * cmd_db_ready - Indicates if command DB is available
+ *
+ * Return: CB_SUCCESS on success, CB_ERR otherwise
+ */
+enum cb_err cmd_db_ready(void);
+
+/**
+ * cmd_db_read_addr() - Query command db for resource id address.
+ *
+ * @id: resource id to query for address
+ *
+ * Return: resource address on success, 0 on error
+ *
+ * This is used to retrieve resource address based on resource id.
+ */
+u32 cmd_db_read_addr(const char *id);
+
+/**
+ * cmd_db_read_aux_data() - Query command db for aux data.
+ *
+ * @id: Resource to retrieve AUX Data on
+ * @len: size of data buffer returned
+ *
+ * Return: pointer to data on success, NULL otherwise
+ */
+const void *cmd_db_read_aux_data(const char *id, size_t *len);
+
+/**
+ * cmd_db_match_resource_addr() - Compare if both Resource addresses are same
+ *
+ * @addr1: Resource address to compare
+ * @addr2: Resource address to compare
+ *
+ * Return: true if two addresses refer to the same resource, false otherwise
+ */
+bool cmd_db_match_resource_addr(u32 addr1, u32 addr2);
+
+/**
+ * cmd_db_read_slave_id - Get the slave ID for a given resource address
+ *
+ * @id: Resource id to query the DB for version
+ *
+ * Return: cmd_db_hw_type enum on success, CMD_DB_HW_INVALID on error
+ */
+enum cmd_db_hw_type cmd_db_read_slave_id(const char *id);
+
+/**
+ * cmd_db_is_standalone - Check if command DB is in standalone mode
+ *
+ * Return: true if standalone, false otherwise
+ */
+bool cmd_db_is_standalone(void);
+
+/**
+ * cmd_db_init - Initialize the command DB
+ *
+ * @base: Physical base address of the command DB memory region
+ * @size: Size of the command DB memory region
+ *
+ * Return: CB_SUCCESS on success, CB_ERR otherwise
+ */
+enum cb_err cmd_db_init(uintptr_t base, size_t size);
+
+#endif /* __SOC_QUALCOMM_CMD_DB_H__ */
diff --git a/src/soc/qualcomm/x1p42100/Makefile.mk b/src/soc/qualcomm/x1p42100/Makefile.mk
index 1fd7fb3d2e..abf5971e20 100644
--- a/src/soc/qualcomm/x1p42100/Makefile.mk
+++ b/src/soc/qualcomm/x1p42100/Makefile.mk
@@ -52,6 +52,7 @@ ramstage-$(CONFIG_PCI) += ../common/pcie_common.c
 ramstage-y += ../common/spmi.c
 ramstage-$(CONFIG_PCI) += pcie.c
 ramstage-y += cpucp_load_reset.c
+ramstage-y += ../common/cmd_db.c
 
 ################################################################################
 

From 8e23c46beb877d003cd4a857b265986b6f1611ab Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Fri, 12 Dec 2025 13:25:20 -0600
Subject: [PATCH 2832/3886] Docs/releases: Update release notes for 25.12
 release

These are the preliminary release notes. They'll need to be updated
with any changes done this week. We'll need another patch after the tag
to capture the final statistics. The notes will be changed from
"Upcoming release" after the tag is done.

Change-Id: Ic8c5a4f374adc6560eff8383d45d05d16ba84759
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90497
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 .../releases/coreboot-25.12-relnotes.md       | 268 +++++++++++++++---
 1 file changed, 230 insertions(+), 38 deletions(-)

diff --git a/Documentation/releases/coreboot-25.12-relnotes.md b/Documentation/releases/coreboot-25.12-relnotes.md
index 9fcc671278..894d8f9da7 100644
--- a/Documentation/releases/coreboot-25.12-relnotes.md
+++ b/Documentation/releases/coreboot-25.12-relnotes.md
@@ -1,38 +1,205 @@
 Upcoming release - coreboot 25.12
 ========================================================================
 
-The 25.12 release is scheduled for the end of December, 2025
+The coreboot project is pleased to announce the release of coreboot
+25.12, continuing our commitment to advancing open-source firmware
+development. This release incorporates over 680 commits from more than
+110 contributors, including numerous first-time authors.
 
+Key improvements include:
+- Addition of runtime setup options, also known as "coreboot Forms Representation" (CFR), for
+  many platforms.
+- Increased capacity of SMMSTORE.
+- Improved support for MIPI cameras on Intel platforms (IPU).
+- Qualcomm X1P42100 platform enablement.
 
-Update this document with changes that should be in the release notes.
-
-* Please use Markdown.
-* See the past few release notes for the general format.
-* The chip and board additions and removals will be updated right
-  before the release, so those do not need to be added.
-* Note that all changes before the release are done are marked upcoming.
-  A final version of the notes are done after the release.
+As always, the coreboot project extends our gratitude to all
+contributors who made this release possible. From experienced
+developers implementing complex features to community members
+providing testing and feedback, your collective contributions drive
+the continued evolution of open-source firmware. The sustained engagement
+from our growing community demonstrates the importance of transparent
+system initialization.
 
+The next coreboot release, 26.03, is scheduled for the end of March 2026.
 
 
 Significant or interesting changes
 ----------------------------------
 
-* Add changes that need a full description here
+### drivers/option: Comprehensive setup option menu support
 
-* This section should have full descriptions and can or should have
-  a link to the referenced commits.
+Extensive implementation of setup option menu support has been added
+across numerous Google ChromeOS mainboards, enabling user-accessible
+runtime firmware configuration. This enhancement allows platforms to
+expose firmware options like iGPU enablement, touchpad/touchscreen
+selection, fan control, and various hardware features through a
+consistent API that can be exposed by payloads.
 
+The option menu framework enables mainboards to define configuration
+options providing user-visible names, help text, default values, and
+runtime flags. Over 40 mainboards (and their variants) now include setup
+option menu support, significantly expanding the reach of user-
+configurable firmware options. Intel SoC code has also been enhanced
+with additional menu item support (cde42807966), and SoC-level support
+for iGPU enable/disable has been added (7f93e2fe29f).
+
+This implementation enables OEMs and end- users to modify firmware
+behavior without requiring re-compilation or reflashing, improving
+accessibility and flexibility of open-source firmware solutions. The
+framework maintains backward compatibility while providing a modern,
+structured approach to firmware option management that can integrate
+with UEFI variable storage and other persistent storage backends.
+
+
+### drivers/smmstore: Increased default storage capacity
+
+The SMMSTORE driver default size has been increased from 256KB to
+512KB (d32a3728465), with numerous Google ChromeOS mainboards updated
+to take advantage of the expanded storage capacity. This change
+provides more space for UEFI variables and other persistent data
+stored in SMM-protected regions.
+
+Multiple platforms including Sarien, Reef, Octopus, Drallion,
+Skyrim, Zork, and Guybrush have been updated to use the larger
+512KB store size, ensuring adequate space for modern firmware variable
+requirements. Additionally, alignment fixes for the SMMSTORE v2
+structure (2a9deabc35f) improve compatibility across different
+architectures and payload expectations.
+
+
+### drivers/intel/mipi_camera: Enhanced SSDB (Sensor Static Data Block) support
+
+Comprehensive improvements to the MIPI camera driver include expanded
+SSDB field support with proper enums and bitfield handling
+(423fbcd06b5, aa18a6fe8d5, f8d12a0bdb4, c91ea7c5824). The driver now
+always generates PLD (Physical Location Descriptor) information for
+camera sensors, ensuring proper ACPI representation of camera physical
+locations.
+
+Additional SSDB defaults are now automatically set
+(c75236d436c), and the driver properly handles platform field
+configuration (30b43839448) and VCM type and address settings
+(e9ebcb2918b). These enhancements improve camera sensor enumeration and
+configuration under modern operating systems, particularly Windows,
+as proper SSDB and PLD configuration is required for full functionality.
+
+
+### soc/qualcomm/x1p42100: Expanded platform support and debug capabilities
+
+Significant enhancements to the Qualcomm X1P42100 platform include
+download mode detection and ramdump packing capabilities
+(36edc2e371c), enabling better debugging workflows for development and
+field diagnostics. Support for loading ramdump images
+(445961c604a) and APDP (Application Processor Debug Policy) image
+packing in CBFS (3c563669b57, 1d70286d4eb) provides comprehensive
+debug infrastructure.
+
+Display subsystem improvements include MDSS (Mobile Display
+Subsystem) domain register definitions for clock enablement
+(6957f84aa77), Lucidole PLL API support (9a95aef482d), and proper
+DRAM reservation for display requirements (36632a08a88). Memory
+layout refinements (c3afc13a0a5) optimize BL31 region placement and
+TZ Application memory alignment, improving overall platform memory
+utilization and security boundaries.
+
+
+### soc/intel: LPCAMM (Low Power Compression Attached Memory Module) support
+
+Support for LPCAMM has been added to Intel Panther Lake platforms
+(58cdf9e6685), providing infrastructure for this emerging memory
+standard. LPCAMM topology support (67777b76719) enables platforms to
+properly enumerate and configure these new memory modules, with initial
+board support added for Panther Lake RVP T3 (b31e62ae5cc).
+
+This addition positions coreboot to support future Intel platforms
+utilizing LPCAMM, ensuring compatibility with next-generation laptop and
+mobile form factors adopting this memory standard.
+
+
+### soc/amd: Glinda/Faegan enhancements and ACPI improvements
+
+AMD Glinda platform support has been expanded with Faegan SoC variant
+support (244e8edf182), USB4 FSP UPD configuration from devicetree
+(f4aeac42767), and 10GbE device additions (9e5c7eb3f87). The platform
+now properly fills DIMM voltage information in FSP configuration
+(dcd4f071887).
+
+ACPI improvements include fixed base address reporting for LPC
+(8929659d936, 3053cd2dad1), I3C controller ACPI code
+(c1958597487), and HEST (Hardware Error Source Table) support
+(2aadfc2b5e1, cc542c15f42) for enhanced error reporting capabilities.
+ECAM MMCONF support has been extended to 64-bit addressing
+(8b97968e53d), and bootblock CRTM (Core Root of Trust for
+Measurement) initialization support has been added
+(33fc33c132c), improving security and system reliability.
+
+
+### commonlib: Code consolidation and endian handling improvements
+
+The `<endian.h>` header implementations from both coreboot and
+libpayload have been merged into commonlib (02a2fe7907d), eliminating
+code duplication and ensuring consistent endian conversion behavior
+across all coreboot components. The deprecated `<swab.h>` header and
+swabXX() functions have been removed (8f34fdfab3a), completing the
+transition to standard endian conversion APIs.
+
+Memory information structures have been enhanced with new fields
+(273a41c4d93), improving SMBIOS memory type 17 compatibility and
+supporting DDR3 voltage field reporting (25c45012232). Device tree
+handling improvements fix NOP token skipping issues (db01aa6cb29),
+and boot mode information is now stored in CBMEM for payload
+coordination (27fcb8617dc).
 
 
 Additional coreboot changes
 ---------------------------
 
-The following are changes across a number of patches, or changes worth
-noting, but not needing a full description.
-
-* Changes that only need a line or two of description go here.
-
+* SMMSTORE structure alignment fixes improving cross-architecture
+  compatibility (2a9deabc35f)
+* MediaTek display subsystem refactoring supporting dual DSI and DSC
+  (Display Stream Compression) for MIPI displays (7e1aa974bfd, 3aaeca83780)
+* MediaTek DSI API improvements with proper register structure passing
+  (6b5a872ce85, 74c13eead40, cf0b91d7749)
+* Intel Skylake CSE reset status utilization improving reset reliability
+  (5eaf85d19b0, 84a4cdc6a53, 4f52ca6ba66)
+* AMD MTRR calculation simplifications for improved boot performance
+  (04f83ff7dca)
+* Enhanced Intel touch driver support for new I2C _DSD entries
+  (e6a8143d8b4)
+* Improved ACPI FACS table initialization with proper clearing
+  (26a18c674d0)
+* TPM driver improvements removing duplicate operations and fixing
+  generated ACPI (67a7e06c386, ac5c57d24a3)
+* Intel GMA brightness handling improvements with caching and valid-cache
+  logic (23b00a06da9, 2d78478345e, 2e96a71e6f9)
+* LAPIC spurious interrupt vector standardization (8795680828f)
+* Intel Fast SPI DMA improvements ensuring proper completion before
+  lockdown
+* Enhanced device tree overlay detection API (ee59936e833)
+* Libpayload API additions for physical memory size querying
+  (c109fc92ff2)
+* Libpayload ARM64 asynchronous exception routing fixes (7fb0f14ebea)
+* Libpayload LZ4 legacy compression format support (d62653749cf)
+* Enhanced EC reboot flag usage for immediate cold reboots
+  (c77d256886b, 1a0d123ec13)
+* Improved SPD support with additional DDR4 parts and dual die package
+  width corrections (e4a809d4415, 4eb524ee9d1)
+* SMBIOS socket type additions for BGA1744 packages (d09ea1c3512)
+* EC RGB keyboard boot color configuration options (d97cb61b508, e695731399d)
+* Panel ID reporting improvements for Google platforms
+* Intel FSP UPD header typedef additions (2ce4e094690)
+* Azalia verb table implementation rework for improved maintainability
+  (31fc5b06a6b) across multiple platforms
+* Intel touch driver enhancements for new devices with improved I2C
+  speed handling (f1708cf21a2, fce489e9e5c, 1af54d9784b)
+* Qualcomm USB Type-C support with PHY configuration and repeater support
+  (8ffa58723a2, 45cedbb9922, 155041ad4cf, b18dfde22a7)
+* SoundWire drivers for Cirrus Logic CS35L56 and CS42L43 codecs
+  (a5252bd5b97, f1c973bbff5)
+* RISC-V ACPI support additions (5daf497df49)
+* Numerous mainboard-specific enhancements across Intel, AMD, MediaTek,
+  and Qualcomm platforms
 
 
 Changes to external resources
@@ -40,49 +207,74 @@ Changes to external resources
 
 ### Toolchain updates
 
+* Upgrade binutils from version 2.44 to 2.45 (4a3cc37cbd6)
+* Upgrade ACPICA from 20250404 to 20250807 (402ac7cd812)
+* Drop nds32le-elf toolchain from default builds (14fc6c34690)
+
+
+### Vendorcode updates
+
+* Updates to FSP headers for Panther Lake (PTL) to FSP 3373_03 and Wildcat
+  Lake (WCL) to 3344_03 (0eafe672e32, 1699d455e70)
+* AMD FSP updates for Glinda platform (f68450e39b1)
 
 
 ### Git submodule pointers
 
+* 3rdparty/blobs: Update from commit id a0726508b8 to 4a8de0324e (39 commits)
+* 3rdparty/intel-microcode: Update from commit id 4ded52b4b0 to f910b0a225 (1 commit)
 
 ### External payloads
 
+* Libpayload enhancements including:
+  - physical memory size API (c109fc92ff2)
+  - endian.h consolidation with coreboot (02a2fe7907d)
+  - ARM64 exception routing fixes (7fb0f14ebea)
+  - legacy LZ4 compression support (d62653749cf)
 
 
 Platform Updates
 ----------------
 
-### Added mainboards:
-* To be filled in immediately before the release by the release team
+### Added mainboards/variants:
+
+* ASRock Z77 Extreme4
+* ASUS PRIME H610I-PLUS D4
+* Google Fatcat: ruby
+* Google Ocelot: kodkod, ocicat
+* Google Rauru: Sapphire
+* Google Skywalker: Dooku, Grogu
+* Lenovo ThinkPad (sklkbl_thinkpad): T470s, T580
+* Siemens MC EHL: MC EHL6
+* Star Labs Starfighter: Arrow Lake (285H)
+* Topton ADL: TWL (X2E_N150)
 
 
-### Removed Mainboards
-* To be filled in immediately before the release by the release team
+### Added SoCs:
+
+* AMD Turin POC (proof of concept)
 
 
 ### Updated SoCs
-* To be filled in immediately before the release by the release team
-
-
-
-Plans to move platform support to a branch
-------------------------------------------
-* To be filled in immediately before the release by the release team
 
+* Enhanced qualcomm/x1p42100 with ramdump, APDP, and display support
+* Enhanced amd/glinda with Faegan variant, USB4, and XGBE support
+* Enhanced intel/pantherlake with LPCAMM memory support
 
 
 Statistics from the 25.09 to the 25.12 release
 --------------------------------------------
-* To be filled in immediately before the release by the release team
-
-
-
-Significant Known and Open Issues
----------------------------------
-
-Issues from the coreboot bugtracker: <https://ticket.coreboot.org/>
-* To be filled in immediately before the release by the release team
-
+* Total Commits: 687
+* Average Commits per day: 8.79
+* Total lines added: 57757
+* Average lines added per commit: 84.07
+* Number of patches adding more than 100 lines: 69
+* Average lines added per small commit: 42.00
+* Total lines removed: 9190
+* Average lines removed per commit: 13.38
+* Total difference between added and removed: 48567
+* Total authors: 106
+* New authors: 21
 
 
 coreboot Links and Contact Information

From d5d27badd4b56d5e1cb152a904f5d977e0c8a2f1 Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Fri, 12 Dec 2025 13:26:09 -0600
Subject: [PATCH 2833/3886] Documentation: Add coreboot release 26.03 template

This adds the release notes template for the upcoming March 2026
release of coreboot.

Change-Id: I7702ee6b5dffce067503ff6e4ccb6508d30bf48f
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90498
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
---
 .../releases/coreboot-26.03-relnotes.md       | 97 +++++++++++++++++++
 Documentation/releases/index.md               |  3 +-
 2 files changed, 99 insertions(+), 1 deletion(-)
 create mode 100644 Documentation/releases/coreboot-26.03-relnotes.md

diff --git a/Documentation/releases/coreboot-26.03-relnotes.md b/Documentation/releases/coreboot-26.03-relnotes.md
new file mode 100644
index 0000000000..d709bb0f0f
--- /dev/null
+++ b/Documentation/releases/coreboot-26.03-relnotes.md
@@ -0,0 +1,97 @@
+Upcoming release - coreboot 26.03
+========================================================================
+
+The 26.03 release is scheduled for the end of March, 2026
+
+
+Update this document with changes that should be in the release notes.
+
+* Please use Markdown.
+* See the past few release notes for the general format.
+* The chip and board additions and removals will be updated right
+  before the release, so those do not need to be added.
+* Note that all changes before the release are done are marked upcoming.
+  A final version of the notes are done after the release.
+
+
+
+Significant or interesting changes
+----------------------------------
+
+* Add changes that need a full description here
+
+* This section should have full descriptions and can or should have
+  a link to the referenced commits.
+
+
+
+Additional coreboot changes
+---------------------------
+
+The following are changes across a number of patches, or changes worth
+noting, but not needing a full description.
+
+* Changes that only need a line or two of description go here.
+
+
+
+Changes to external resources
+-----------------------------
+
+### Toolchain updates
+
+
+
+### Git submodule pointers
+
+
+### External payloads
+
+
+
+Platform Updates
+----------------
+
+### Added mainboards:
+* To be filled in immediately before the release by the release team
+
+
+### Removed Mainboards
+* To be filled in immediately before the release by the release team
+
+
+### Updated SoCs
+* To be filled in immediately before the release by the release team
+
+
+
+Plans to move platform support to a branch
+------------------------------------------
+* To be filled in immediately before the release by the release team
+
+
+
+Statistics from the 25.12 to the 26.03 release
+--------------------------------------------
+* To be filled in immediately before the release by the release team
+
+
+
+Significant Known and Open Issues
+---------------------------------
+
+Issues from the coreboot bugtracker: <https://ticket.coreboot.org/>
+* To be filled in immediately before the release by the release team
+
+
+
+coreboot Links and Contact Information
+--------------------------------------
+
+* Main Web site: <https://www.coreboot.org>
+* Downloads: <https://coreboot.org/downloads.html>
+* Source control: <https://review.coreboot.org>
+* Documentation: <https://doc.coreboot.org>
+* Issue tracker: <https://ticket.coreboot.org/projects/coreboot>
+* Donations: <https://coreboot.org/donate.html>
+
diff --git a/Documentation/releases/index.md b/Documentation/releases/index.md
index 8cf8678b2d..b6d53a94a6 100644
--- a/Documentation/releases/index.md
+++ b/Documentation/releases/index.md
@@ -6,7 +6,7 @@ Please add to the release notes as changes are added:
 ```{toctree}
 :maxdepth: 1
 
-25.12  - December 2025 <coreboot-25.12-relnotes.md>
+26.03  - March 2026 <coreboot-26.03-relnotes.md>
 ```
 
 The [checklist] contains instructions to ensure that a release covers all
@@ -22,6 +22,7 @@ important is taken care of.
 ```{toctree}
 :maxdepth: 1
 
+25.12  - December 2025 <coreboot-25.12-relnotes.md>
 25.09  - September 2025 <coreboot-25.09-relnotes.md>
 25.06  - June 2025 <coreboot-25.06-relnotes.md>
 25.03  - March 2025 <coreboot-25.03-relnotes.md>

From ecf202b8e4ac085f8b09b942a48e7f745fdac0d6 Mon Sep 17 00:00:00 2001
From: Nico Huber <nico.h@gmx.de>
Date: Sat, 20 Jul 2024 12:54:03 +0200
Subject: [PATCH 2834/3886] device/azalia: Add missing 521us delay after RESET#
 de-assertion

The spec[1] says a codec is allowed to take up to 521us before sig-
naling an initialization request. Our original SB600 implementation
had a 1ms delay here since commit 4505948faec7 ("Use the correct device
for switching on HDA.")

Most codecs are a lot faster, which is probably why nobody noticed
the missing delay. For instance, the Realtek ALC272 datasheet spe-
cifies a 1 frame (1/48kHz) maximum[2]. It doesn't hurt, though, to
be correct here. We have a lot longer delays around.

[1] High Definition Audio Specification 1.0a: "4.3 Codec Discovery"
[2] ALC272 datasheet: "9.2.1. Link Reset and Initialization Timing"

TEST= Verbs were loaded correctly on off-tree HP ProBook 450 G3.

Change-Id: Ifd3357758fb3678e60b4c6edcfbdb60b3bda9746
Signed-off-by: Nico Huber <nico.h@gmx.de>
Signed-off-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89651
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
---
 src/device/azalia_device.c | 8 +++++++-
 1 file changed, 7 insertions(+), 1 deletion(-)

diff --git a/src/device/azalia_device.c b/src/device/azalia_device.c
index 82c6fdca41..937ca89f55 100644
--- a/src/device/azalia_device.c
+++ b/src/device/azalia_device.c
@@ -40,7 +40,13 @@ enum cb_err azalia_enter_reset(u8 *base)
 enum cb_err azalia_exit_reset(u8 *base)
 {
 	/* Set bit 0 to 1 to exit reset state (BAR + 0x8)[0] */
-	return azalia_set_bits(base + HDA_GCTL_REG, HDA_GCTL_CRST, HDA_GCTL_CRST);
+	if (azalia_set_bits(base + HDA_GCTL_REG, HDA_GCTL_CRST, HDA_GCTL_CRST) != CB_SUCCESS)
+		return CB_ERR;
+
+	/* Codecs have up to 25 frames (at 48kHz) to signal an
+	   initialization request (HDA Spec 1.0a "4.3 Codec Discovery"). */
+	udelay(521);
+	return CB_SUCCESS;
 }
 
 static u16 codec_detect(u8 *base)

From 6e074550a5c18fcc53a0df15d8feec6a61ff8ec8 Mon Sep 17 00:00:00 2001
From: Nico Huber <nico.h@gmx.de>
Date: Sat, 20 Jul 2024 13:38:07 +0200
Subject: [PATCH 2835/3886] device/azalia: Repurpose azalia_set_bits() for
 link-reset only

The azalia_set_bits() function does some sequencing specific to the
CRST# bit. Name it accordingly and adapt its signature.

The while loop was also changed to match the other functions (e.g.
wait_for_ready()).

TEST= Verbs were loaded correctly on off-tree HP ProBook 450 G3.

Change-Id: I5ac766f2ddf8b48b436a54469815bf799ae31d52
Signed-off-by: Nico Huber <nico.h@gmx.de>
Signed-off-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89652
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/device/azalia_device.c | 27 ++++++++++++---------------
 1 file changed, 12 insertions(+), 15 deletions(-)

diff --git a/src/device/azalia_device.c b/src/device/azalia_device.c
index 937ca89f55..9cda449302 100644
--- a/src/device/azalia_device.c
+++ b/src/device/azalia_device.c
@@ -9,38 +9,35 @@
 #include <timer.h>
 #include <types.h>
 
-static enum cb_err azalia_set_bits(void *port, u32 mask, u32 val)
+static enum cb_err azalia_assert_reset(u8 *base, bool reset)
 {
+	const u32 val = reset ? 0 : HDA_GCTL_CRST; /* active-low CRST# */
 	struct stopwatch sw;
-	u32 reg32;
 
-	clrsetbits32(port, mask, val);
+	clrsetbits32(base + HDA_GCTL_REG, HDA_GCTL_CRST, val);
 
-	/* Wait for readback of register to match what was just written to it */
+	/* Wait for the controller to complete the link-reset sequence */
 	stopwatch_init_msecs_expire(&sw, 50);
+
 	do {
 		/* Wait 1ms based on BKDG wait time */
 		mdelay(1);
-		reg32 = read32(port);
-		reg32 &= mask;
-	} while ((reg32 != val) && !stopwatch_expired(&sw));
+		u32 reg32 = read32(base + HDA_GCTL_REG);
+		if ((reg32 & HDA_GCTL_CRST) == val)
+			return CB_SUCCESS;
+	} while (!stopwatch_expired(&sw));
 
-	/* Timeout occurred */
-	if (stopwatch_expired(&sw))
-		return CB_ERR;
-	return CB_SUCCESS;
+	return CB_ERR;
 }
 
 enum cb_err azalia_enter_reset(u8 *base)
 {
-	/* Set bit 0 to 0 to enter reset state (BAR + 0x8)[0] */
-	return azalia_set_bits(base + HDA_GCTL_REG, HDA_GCTL_CRST, 0);
+	return azalia_assert_reset(base, true);
 }
 
 enum cb_err azalia_exit_reset(u8 *base)
 {
-	/* Set bit 0 to 1 to exit reset state (BAR + 0x8)[0] */
-	if (azalia_set_bits(base + HDA_GCTL_REG, HDA_GCTL_CRST, HDA_GCTL_CRST) != CB_SUCCESS)
+	if (azalia_assert_reset(base, false) != CB_SUCCESS)
 		return CB_ERR;
 
 	/* Codecs have up to 25 frames (at 48kHz) to signal an

From 152914272c1068097891dceb76ae21924656abad Mon Sep 17 00:00:00 2001
From: Nico Huber <nico.h@gmx.de>
Date: Sat, 20 Jul 2024 13:48:16 +0200
Subject: [PATCH 2836/3886] device/azalia: Drop spurious read-back of STATESTS

The STATESTS register is a very simple read/write-1-clear status
register. OS drivers have to read and clear it all the time with-
out any quirk handling.  So it seems unlikely that this sequence
was ever necessary for any coreboot-supported chip.

More likely, that sequence was copied from the dance around the
reset bit when Poulsbo support was added in commit be61a173512e
("Support Intel SCH (Poulsbo) and add iwave/iWRainbowG6 board
which uses it.").

TEST= Verbs were loaded correctly on off-tree HP ProBook 450 G3.

Change-Id: I1fbea8ffb71a2fcb4ce5f42b3cb8f816ec336c5b
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89653
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/device/azalia_device.c | 15 ---------------
 1 file changed, 15 deletions(-)

diff --git a/src/device/azalia_device.c b/src/device/azalia_device.c
index 9cda449302..d130c5b998 100644
--- a/src/device/azalia_device.c
+++ b/src/device/azalia_device.c
@@ -48,7 +48,6 @@ enum cb_err azalia_exit_reset(u8 *base)
 
 static u16 codec_detect(u8 *base)
 {
-	struct stopwatch sw;
 	u16 reg16;
 
 	if (azalia_exit_reset(base) != CB_SUCCESS)
@@ -71,20 +70,6 @@ static u16 codec_detect(u8 *base)
 	/* clear STATESTS bits (BAR + 0x0e)[14:0] */
 	setbits16(base + HDA_STATESTS_REG, 0x7fff);
 
-	/* Wait for readback of register to
-	 * match what was just written to it
-	 */
-	stopwatch_init_msecs_expire(&sw, 50);
-	do {
-		/* Wait 1ms based on BKDG wait time */
-		mdelay(1);
-		reg16 = read16(base + HDA_STATESTS_REG);
-	} while ((reg16 != 0) && !stopwatch_expired(&sw));
-
-	/* Timeout occurred */
-	if (stopwatch_expired(&sw))
-		goto no_codec;
-
 	if (azalia_enter_reset(base) != CB_SUCCESS)
 		goto no_codec;
 

From 7e1962a3cccbfce174d9e4d6d99c48def59d83f4 Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Tue, 16 Dec 2025 19:35:47 -0600
Subject: [PATCH 2837/3886] mb/google/hatch: Make touchpad wake user-selectable
 via CFR

Add CFR option "touchpad_wake" (default: false) to allow users to
enable touchpad wake from sleep. Wake is disabled by default to
prevent random wakeups when systems are moved while sleeping.

Implementation:
- Add touchpad_wake CFR option to System form
- Add device alias "touchpad" to variant devicetree files
- Conditionally disable wake in ramstage based on CFR option

When the option is disabled (default), config->wake and
config->irq.wake are set to 0, preventing the touchpad ACPI device
from defining wake methods and capability.

TEST=Build for KOHAKU, boot into mainline Linux (Fedora 43, kernel
6.18). Suspend the machine, close the lid, apply pressure to trackpad
area. Ensure that system doesn't wake up.

Change-Id: I620d7c0f0ebec8ca72ec018c93747f58735fd3e5
Co-authored-by: Alicja Michalska <alicja.michalska@9elements.com>
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90491
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/google/hatch/cfr.c              | 14 ++++++++
 src/mainboard/google/hatch/ramstage.c         | 34 +++++++++++++++++++
 .../hatch/variants/akemi/overridetree.cb      |  2 +-
 .../hatch/variants/dratini/overridetree.cb    |  2 +-
 .../hatch/variants/hatch/overridetree.cb      |  2 +-
 .../hatch/variants/helios/overridetree.cb     |  2 +-
 .../variants/helios_diskswap/overridetree.cb  |  2 +-
 .../hatch/variants/jinlon/overridetree.cb     |  2 +-
 .../hatch/variants/kindred/overridetree.cb    |  2 +-
 .../hatch/variants/kohaku/overridetree.cb     |  2 +-
 .../hatch/variants/mushu/overridetree.cb      |  2 +-
 .../hatch/variants/nightfury/overridetree.cb  |  2 +-
 .../hatch/variants/palkia/overridetree.cb     |  2 +-
 13 files changed, 59 insertions(+), 11 deletions(-)

diff --git a/src/mainboard/google/hatch/cfr.c b/src/mainboard/google/hatch/cfr.c
index 2de1ebbb7c..76f12e232c 100644
--- a/src/mainboard/google/hatch/cfr.c
+++ b/src/mainboard/google/hatch/cfr.c
@@ -7,6 +7,19 @@
 #include <intelblocks/cfr.h>
 #include <soc/cfr.h>
 
+static const struct sm_object touchpad_wake = SM_DECLARE_ENUM({
+	.opt_name	= "touchpad_wake",
+	.ui_name	= "Touchpad Wake",
+	.ui_helptext	= "Enable or disable touchpad wake from sleep.\n"
+			  "Disabled by default to prevent random wakeups when\n"
+			  "the system is moved while sleeping.",
+	.default_value	= 0,
+	.values		= (const struct sm_enum_value[]) {
+				{ "Disabled",	0	},
+				{ "Enabled",	1	},
+				SM_ENUM_VALUE_END	},
+});
+
 static struct sm_obj_form system = {
 	.ui_name = "System",
 	.obj_list = (const struct sm_object *[]) {
@@ -21,6 +34,7 @@ static struct sm_obj_form system = {
 		&pciexp_l1ss,
 		&pciexp_speed,
 		&s0ix_enable,
+		&touchpad_wake,
 		&vtd,
 		NULL
 	},
diff --git a/src/mainboard/google/hatch/ramstage.c b/src/mainboard/google/hatch/ramstage.c
index 6cce734c90..c91ce7c449 100644
--- a/src/mainboard/google/hatch/ramstage.c
+++ b/src/mainboard/google/hatch/ramstage.c
@@ -1,9 +1,15 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
 #include <baseboard/variants.h>
+#include <console/console.h>
+#include <device/device.h>
+#include <drivers/i2c/generic/chip.h>
 #include <ec/ec.h>
+#include <intelblocks/gpio.h>
+#include <option.h>
 #include <soc/gpio.h>
 #include <soc/ramstage.h>
+#include <static.h>
 #include <variant/gpio.h>
 
 void mainboard_silicon_init_params(FSPS_UPD *supd)
@@ -26,6 +32,33 @@ void __weak variant_mainboard_enable(struct device *dev)
 	/* Override mainboard settings per board */
 }
 
+static void update_touchpad_wake_config(void)
+{
+	const struct device *touchpad = DEV_PTR(touchpad);
+	if (!touchpad || !touchpad->chip_info)
+		return;
+
+	/* Check CFR option for touchpad wake */
+	unsigned int touchpad_wake_enabled = get_uint_option("touchpad_wake", 0);
+
+	printk(BIOS_DEBUG, "Touchpad wake: %s\n", touchpad_wake_enabled?"enabled":"disabled");
+
+	/* Modify devicetree config directly */
+	struct drivers_i2c_generic_config *config =
+		(struct drivers_i2c_generic_config *)touchpad->chip_info;
+	if (!touchpad_wake_enabled) {
+		/* Disable wake GPE and wake flag in IRQ descriptor */
+		config->wake = 0;
+		config->irq.wake = 0;
+
+		/* Reconfigure GPIO pad to remove wake capability */
+		const struct pad_config touchpad_gpio[] = {
+			PAD_CFG_GPI_APIC(GPP_A21, NONE, DEEP, LEVEL, INVERT),
+		};
+		gpio_configure_pads(touchpad_gpio, ARRAY_SIZE(touchpad_gpio));
+	}
+}
+
 static void mainboard_init(struct device *dev)
 {
 	mainboard_ec_init();
@@ -35,6 +68,7 @@ static void mainboard_enable(struct device *dev)
 {
 	dev->ops->init = mainboard_init;
 	variant_mainboard_enable(dev);
+	update_touchpad_wake_config();
 }
 
 static void mainboard_chip_init(void *chip_info)
diff --git a/src/mainboard/google/hatch/variants/akemi/overridetree.cb b/src/mainboard/google/hatch/variants/akemi/overridetree.cb
index 1102c8731b..0510844e26 100644
--- a/src/mainboard/google/hatch/variants/akemi/overridetree.cb
+++ b/src/mainboard/google/hatch/variants/akemi/overridetree.cb
@@ -120,7 +120,7 @@ chip soc/intel/cannonlake
 				register "irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_A21_IRQ)"
 				register "wake" = "GPE0_DW0_21"
 				register "detect" = "1"
-				device i2c 15 on end
+				device i2c 15 alias touchpad on end
 			end
 			chip drivers/i2c/hid
 				register "generic.hid" = ""SYNA0000""
diff --git a/src/mainboard/google/hatch/variants/dratini/overridetree.cb b/src/mainboard/google/hatch/variants/dratini/overridetree.cb
index 5ae9481f7e..b160a9161a 100644
--- a/src/mainboard/google/hatch/variants/dratini/overridetree.cb
+++ b/src/mainboard/google/hatch/variants/dratini/overridetree.cb
@@ -80,7 +80,7 @@ chip soc/intel/cannonlake
 				register "irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_A21_IRQ)"
 				register "wake" = "GPE0_DW0_21"
 				register "detect" = "1"
-				device i2c 15 on end
+				device i2c 15 alias touchpad on end
 			end
 		end
 		device ref i2c1		on
diff --git a/src/mainboard/google/hatch/variants/hatch/overridetree.cb b/src/mainboard/google/hatch/variants/hatch/overridetree.cb
index 36f489516b..23b0be2a98 100644
--- a/src/mainboard/google/hatch/variants/hatch/overridetree.cb
+++ b/src/mainboard/google/hatch/variants/hatch/overridetree.cb
@@ -79,7 +79,7 @@ chip soc/intel/cannonlake
 				register "desc" = ""ELAN Touchpad""
 				register "irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_A21_IRQ)"
 				register "wake" = "GPE0_DW0_21"
-				device i2c 15 on end
+				device i2c 15 alias touchpad on end
 			end
 		end
 		device ref i2c1		on
diff --git a/src/mainboard/google/hatch/variants/helios/overridetree.cb b/src/mainboard/google/hatch/variants/helios/overridetree.cb
index c9f0caeb0d..880ba21c18 100644
--- a/src/mainboard/google/hatch/variants/helios/overridetree.cb
+++ b/src/mainboard/google/hatch/variants/helios/overridetree.cb
@@ -90,7 +90,7 @@ chip soc/intel/cannonlake
 				register "desc" = ""ELAN Touchpad""
 				register "irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_A21_IRQ)"
 				register "wake" = "GPE0_DW0_21"
-				device i2c 15 on end
+				device i2c 15 alias touchpad on end
 			end
 		end
 		device ref i2c1		on
diff --git a/src/mainboard/google/hatch/variants/helios_diskswap/overridetree.cb b/src/mainboard/google/hatch/variants/helios_diskswap/overridetree.cb
index b4421b0ec6..91fa294619 100644
--- a/src/mainboard/google/hatch/variants/helios_diskswap/overridetree.cb
+++ b/src/mainboard/google/hatch/variants/helios_diskswap/overridetree.cb
@@ -104,7 +104,7 @@ chip soc/intel/cannonlake
 				register "desc" = ""ELAN Touchpad""
 				register "irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_A21_IRQ)"
 				register "wake" = "GPE0_DW0_21"
-				device i2c 15 on end
+				device i2c 15 alias touchpad on end
 			end
 		end
 		device ref i2c1		on
diff --git a/src/mainboard/google/hatch/variants/jinlon/overridetree.cb b/src/mainboard/google/hatch/variants/jinlon/overridetree.cb
index 4f861c9ba1..79e7aff362 100644
--- a/src/mainboard/google/hatch/variants/jinlon/overridetree.cb
+++ b/src/mainboard/google/hatch/variants/jinlon/overridetree.cb
@@ -110,7 +110,7 @@ chip soc/intel/cannonlake
 				register "irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_A21_IRQ)"
 				register "wake" = "GPE0_DW0_21"
 				register "detect" = "1"
-				device i2c 15 on end
+				device i2c 15 alias touchpad on end
 			end
 		end
 		device ref i2c1		on
diff --git a/src/mainboard/google/hatch/variants/kindred/overridetree.cb b/src/mainboard/google/hatch/variants/kindred/overridetree.cb
index f47fce0405..c6c478ebb9 100644
--- a/src/mainboard/google/hatch/variants/kindred/overridetree.cb
+++ b/src/mainboard/google/hatch/variants/kindred/overridetree.cb
@@ -116,7 +116,7 @@ chip soc/intel/cannonlake
 				register "irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_A21_IRQ)"
 				register "wake" = "GPE0_DW0_21"
 				register "detect" = "1"
-				device i2c 15 on end
+				device i2c 15 alias touchpad on end
 			end
 			chip drivers/i2c/hid
 				register "generic.hid" = ""SYNA0000""
diff --git a/src/mainboard/google/hatch/variants/kohaku/overridetree.cb b/src/mainboard/google/hatch/variants/kohaku/overridetree.cb
index f00d9bb9d5..59704cafa1 100644
--- a/src/mainboard/google/hatch/variants/kohaku/overridetree.cb
+++ b/src/mainboard/google/hatch/variants/kohaku/overridetree.cb
@@ -129,7 +129,7 @@ chip soc/intel/cannonlake
 				register "generic.detect" = "1"
 				register "generic.wake" = "GPE0_DW0_21"
 				register "hid_desc_reg_offset" = "0x20"
-				device i2c 0x20 on end
+				device i2c 0x20 alias touchpad on end
 			end
 		end
 		device ref i2c1		on
diff --git a/src/mainboard/google/hatch/variants/mushu/overridetree.cb b/src/mainboard/google/hatch/variants/mushu/overridetree.cb
index 8766c9ec3a..f3b98ecc09 100644
--- a/src/mainboard/google/hatch/variants/mushu/overridetree.cb
+++ b/src/mainboard/google/hatch/variants/mushu/overridetree.cb
@@ -97,7 +97,7 @@ chip soc/intel/cannonlake
 				register "desc" = ""ELAN Touchpad""
 				register "irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_A21_IRQ)"
 				register "wake" = "GPE0_DW0_21"
-				device i2c 15 on end
+				device i2c 15 alias touchpad on end
 			end
 		end
 		device ref i2c1		on
diff --git a/src/mainboard/google/hatch/variants/nightfury/overridetree.cb b/src/mainboard/google/hatch/variants/nightfury/overridetree.cb
index f020f468c4..6b91bbdcdb 100644
--- a/src/mainboard/google/hatch/variants/nightfury/overridetree.cb
+++ b/src/mainboard/google/hatch/variants/nightfury/overridetree.cb
@@ -164,7 +164,7 @@ chip soc/intel/cannonlake
 				register "irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_A21_IRQ)"
 				register "detect" = "1"
 				register "wake" = "GPE0_DW0_21"
-				device i2c 0x15 on end
+				device i2c 0x15 alias touchpad on end
 			end
 		end
 		device ref i2c1		on
diff --git a/src/mainboard/google/hatch/variants/palkia/overridetree.cb b/src/mainboard/google/hatch/variants/palkia/overridetree.cb
index 7fca6cc661..6c6b7470e4 100644
--- a/src/mainboard/google/hatch/variants/palkia/overridetree.cb
+++ b/src/mainboard/google/hatch/variants/palkia/overridetree.cb
@@ -101,7 +101,7 @@ chip soc/intel/cannonlake
 				register "desc" = ""ELAN Touchpad""
 				register "irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_A21_IRQ)"
 				register "wake" = "GPE0_DW0_21"
-				device i2c 15 on end
+				device i2c 15 alias touchpad on end
 			end
 		end
 		device ref i2c1		on

From 8ed87f71ec6802f33131c622656e026d4354630c Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Tue, 16 Dec 2025 19:34:48 -0600
Subject: [PATCH 2838/3886] mb/google/volteer: Make touchpad wake
 user-selectable via CFR

Add CFR option "touchpad_wake" (default: false) to allow users to
enable touchpad wake from sleep. Wake is disabled by default to
prevent random wakeups when systems are moved while sleeping.

Implementation:
- Add touchpad_wake CFR option to System form
- Add device alias "touchpad" to variant devicetree files
  (add touchpad2 where a 2nd touchpad option is present)
- Update variant GPIO configs to support wake capability
  (this was set inconsistently)
- Conditionally disable wake in ramstage based on CFR option

When the option is disabled (default), config->wake and
config->irq.wake are set to 0, preventing the touchpad ACPI device
from defining wake methods and capability.

TEST_1: Build for ELDRID, boot system into mainlinue Linux (Fedora).
Close the lid to suspend the system, firmly grab it with both hands and
jump 10 times. Make sure that system doesn't wake up from sleep state.

TEST_2: Build for DROBIT, boot system into mainline Linux (NixOS).
Close the lid to suspend the system, firmly grab it with both hands and
jump few times. Make sure that system doesn't wake up from sleep state.

Tested-by: Ingo Reitz <9l@9lo.re>
Change-Id: Ie3b5013bcf2d5ea45388bcdce987dd9ae5870597
Co-authored-by: Alicja Michalska <alicja.michalska@9elements.com>
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90500
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
---
 src/mainboard/google/volteer/cfr.c            | 14 ++++++++
 src/mainboard/google/volteer/mainboard.c      | 33 +++++++++++++++++++
 .../variants/chronicler/overridetree.cb       |  2 +-
 .../volteer/variants/collis/overridetree.cb   |  4 +--
 .../volteer/variants/copano/overridetree.cb   |  4 +--
 .../volteer/variants/delbin/overridetree.cb   |  2 +-
 .../volteer/variants/drobit/overridetree.cb   |  2 +-
 .../volteer/variants/eldrid/overridetree.cb   |  2 +-
 .../volteer/variants/elemi/overridetree.cb    |  2 +-
 .../volteer/variants/halvor/overridetree.cb   |  2 +-
 .../volteer/variants/lindar/overridetree.cb   |  2 +-
 .../volteer/variants/malefor/overridetree.cb  |  2 +-
 .../volteer/variants/terrador/overridetree.cb |  2 +-
 .../volteer/variants/todor/overridetree.cb    |  2 +-
 .../google/volteer/variants/trondo/gpio.c     |  2 +-
 .../volteer/variants/trondo/overridetree.cb   |  2 +-
 .../volteer/variants/voema/overridetree.cb    |  2 +-
 .../google/volteer/variants/volet/gpio.c      |  2 +-
 .../volteer/variants/volet/overridetree.cb    |  2 +-
 .../volteer/variants/volteer/overridetree.cb  |  2 +-
 .../volteer/variants/volteer2/overridetree.cb |  2 +-
 .../google/volteer/variants/voxel/gpio.c      |  2 +-
 .../volteer/variants/voxel/overridetree.cb    |  2 +-
 23 files changed, 70 insertions(+), 23 deletions(-)

diff --git a/src/mainboard/google/volteer/cfr.c b/src/mainboard/google/volteer/cfr.c
index 2de1ebbb7c..76f12e232c 100644
--- a/src/mainboard/google/volteer/cfr.c
+++ b/src/mainboard/google/volteer/cfr.c
@@ -7,6 +7,19 @@
 #include <intelblocks/cfr.h>
 #include <soc/cfr.h>
 
+static const struct sm_object touchpad_wake = SM_DECLARE_ENUM({
+	.opt_name	= "touchpad_wake",
+	.ui_name	= "Touchpad Wake",
+	.ui_helptext	= "Enable or disable touchpad wake from sleep.\n"
+			  "Disabled by default to prevent random wakeups when\n"
+			  "the system is moved while sleeping.",
+	.default_value	= 0,
+	.values		= (const struct sm_enum_value[]) {
+				{ "Disabled",	0	},
+				{ "Enabled",	1	},
+				SM_ENUM_VALUE_END	},
+});
+
 static struct sm_obj_form system = {
 	.ui_name = "System",
 	.obj_list = (const struct sm_object *[]) {
@@ -21,6 +34,7 @@ static struct sm_obj_form system = {
 		&pciexp_l1ss,
 		&pciexp_speed,
 		&s0ix_enable,
+		&touchpad_wake,
 		&vtd,
 		NULL
 	},
diff --git a/src/mainboard/google/volteer/mainboard.c b/src/mainboard/google/volteer/mainboard.c
index 4d62ed6118..c17dd7cdb7 100644
--- a/src/mainboard/google/volteer/mainboard.c
+++ b/src/mainboard/google/volteer/mainboard.c
@@ -4,10 +4,12 @@
 #include <baseboard/variants.h>
 #include <device/device.h>
 #include <drivers/tpm/cr50.h>
+#include <drivers/i2c/generic/chip.h>
 #include <ec/ec.h>
 #include <fw_config.h>
 #include <gpio.h>
 #include <intelblocks/gpio.h>
+#include <option.h>
 #include <security/tpm/tss.h>
 #include <intelblocks/tcss.h>
 #include <soc/pci_devs.h>
@@ -16,10 +18,13 @@
 #include <stdio.h>
 #include <variant/gpio.h>
 #include <vb2_api.h>
+#include <static.h>
 
 #include "drivers/intel/pmc_mux/conn/chip.h"
 
 WEAK_DEV_PTR(conn1);
+WEAK_DEV_PTR(touchpad);
+WEAK_DEV_PTR(touchpad2);
 
 static void typec_orientation_fixup(void)
 {
@@ -74,12 +79,40 @@ static void mainboard_smbios_strings(struct device *dev, struct smbios_type11 *t
 	fw_config_for_each_found(add_fw_config_oem_string, t);
 }
 
+static void update_touchpad_wake_config(const struct device *touchpad)
+{
+	if (!touchpad || !touchpad->chip_info || !is_dev_enabled(touchpad))
+		return;
+
+	/* Check CFR option for touchpad wake */
+	unsigned int touchpad_wake_enabled = get_uint_option("touchpad_wake", 0);
+
+	printk(BIOS_DEBUG, "Touchpad wake: %s\n", touchpad_wake_enabled?"enabled":"disabled");
+
+	/* Modify devicetree config directly */
+	struct drivers_i2c_generic_config *config =
+		(struct drivers_i2c_generic_config *)touchpad->chip_info;
+	if (!touchpad_wake_enabled) {
+		/* Disable wake GPE and wake flag in IRQ descriptor */
+		config->wake = 0;
+		config->irq.wake = 0;
+
+		/* Reconfigure GPIO pad to remove wake capability */
+		const struct pad_config touchpad_gpio[] = {
+			PAD_CFG_GPI_APIC(GPP_E15, NONE, PLTRST, LEVEL, INVERT),
+		};
+		gpio_configure_pads(touchpad_gpio, ARRAY_SIZE(touchpad_gpio));
+	}
+}
+
 static void mainboard_enable(struct device *dev)
 {
 	dev->ops->init = mainboard_init;
 	dev->ops->get_smbios_strings = mainboard_smbios_strings;
 
 	variant_ramstage_init();
+	update_touchpad_wake_config(DEV_PTR(touchpad));
+	update_touchpad_wake_config(DEV_PTR(touchpad2));
 }
 
 void mainboard_update_soc_chip_config(struct soc_intel_tigerlake_config *cfg)
diff --git a/src/mainboard/google/volteer/variants/chronicler/overridetree.cb b/src/mainboard/google/volteer/variants/chronicler/overridetree.cb
index 4688c23144..180acca7b3 100644
--- a/src/mainboard/google/volteer/variants/chronicler/overridetree.cb
+++ b/src/mainboard/google/volteer/variants/chronicler/overridetree.cb
@@ -242,7 +242,7 @@ chip soc/intel/tigerlake
 				register "irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_E15_IRQ)"
 				register "wake" = "GPE0_DW2_15"
 				register "detect" = "1"
-				device i2c 15 on end
+				device i2c 15 alias touchpad on end
 			end
 		end
 		device ref pch_espi on
diff --git a/src/mainboard/google/volteer/variants/collis/overridetree.cb b/src/mainboard/google/volteer/variants/collis/overridetree.cb
index b5426c16ba..b3f04d9e9c 100644
--- a/src/mainboard/google/volteer/variants/collis/overridetree.cb
+++ b/src/mainboard/google/volteer/variants/collis/overridetree.cb
@@ -157,7 +157,7 @@ chip soc/intel/tigerlake
 				register "irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_E15_IRQ)"
 				register "wake" = "GPE0_DW2_15"
 				register "detect" = "1"
-				device i2c 15 on
+				device i2c 15 alias touchpad on
 					probe TOUCHPAD REGULAR_TOUCHPAD
 				end
 			end
@@ -168,7 +168,7 @@ chip soc/intel/tigerlake
 				register "generic.wake" = "GPE0_DW2_15"
 				register "generic.detect" = "1"
 				register "hid_desc_reg_offset" = "0x01"
-				device i2c 15 on
+				device i2c 15 alias touchpad2 on
 					probe TOUCHPAD NUMPAD_TOUCHPAD
 				end
 			end
diff --git a/src/mainboard/google/volteer/variants/copano/overridetree.cb b/src/mainboard/google/volteer/variants/copano/overridetree.cb
index 6ff20d0d9a..5ec8c9ac76 100644
--- a/src/mainboard/google/volteer/variants/copano/overridetree.cb
+++ b/src/mainboard/google/volteer/variants/copano/overridetree.cb
@@ -184,7 +184,7 @@ chip soc/intel/tigerlake
 				register "irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_E15_IRQ)"
 				register "wake" = "GPE0_DW2_15"
 				register "detect" = "1"
-				device i2c 15 on
+				device i2c 15 alias touchpad on
 					probe TOUCHPAD REGULAR_TOUCHPAD
 				end
 			end
@@ -195,7 +195,7 @@ chip soc/intel/tigerlake
 				register "generic.wake" = "GPE0_DW2_15"
 				register "generic.detect" = "1"
 				register "hid_desc_reg_offset" = "0x01"
-				device i2c 15 on
+				device i2c 15 alias touchpad2 on
 					probe TOUCHPAD NUMPAD_TOUCHPAD
 				end
 			end
diff --git a/src/mainboard/google/volteer/variants/delbin/overridetree.cb b/src/mainboard/google/volteer/variants/delbin/overridetree.cb
index cca423f99d..f40378b8ab 100644
--- a/src/mainboard/google/volteer/variants/delbin/overridetree.cb
+++ b/src/mainboard/google/volteer/variants/delbin/overridetree.cb
@@ -176,7 +176,7 @@ chip soc/intel/tigerlake
 				register "irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_E15_IRQ)"
 				register "wake" = "GPE0_DW2_15"
 				register "detect" = "1"
-				device i2c 15 on end
+				device i2c 15 alias touchpad on end
 			end
 		end
 		device ref pch_espi on
diff --git a/src/mainboard/google/volteer/variants/drobit/overridetree.cb b/src/mainboard/google/volteer/variants/drobit/overridetree.cb
index 148af6e66f..be0b99baff 100644
--- a/src/mainboard/google/volteer/variants/drobit/overridetree.cb
+++ b/src/mainboard/google/volteer/variants/drobit/overridetree.cb
@@ -186,7 +186,7 @@ chip soc/intel/tigerlake
 				register "generic.wake" = "GPE0_DW2_15"
 				register "generic.detect" = "1"
 				register "hid_desc_reg_offset" = "0x01"
-				device i2c 15 on end
+				device i2c 15 alias touchpad on end
 			end
 		end
 		device ref pch_espi on
diff --git a/src/mainboard/google/volteer/variants/eldrid/overridetree.cb b/src/mainboard/google/volteer/variants/eldrid/overridetree.cb
index 89b0d15123..cd146a6bfb 100644
--- a/src/mainboard/google/volteer/variants/eldrid/overridetree.cb
+++ b/src/mainboard/google/volteer/variants/eldrid/overridetree.cb
@@ -148,7 +148,7 @@ chip soc/intel/tigerlake
 				register "irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_E15_IRQ)"
 				register "wake" = "GPE0_DW2_15"
 				register "detect" = "1"
-				device i2c 15 on end
+				device i2c 15 alias touchpad on end
 			end
 		end
 		device ref pch_espi on
diff --git a/src/mainboard/google/volteer/variants/elemi/overridetree.cb b/src/mainboard/google/volteer/variants/elemi/overridetree.cb
index abf2345be0..8f220b8fcd 100644
--- a/src/mainboard/google/volteer/variants/elemi/overridetree.cb
+++ b/src/mainboard/google/volteer/variants/elemi/overridetree.cb
@@ -243,7 +243,7 @@ chip soc/intel/tigerlake
 				register "irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_E15_IRQ)"
 				register "wake" = "GPE0_DW2_15"
 				register "detect" = "1"
-				device i2c 15 on end
+				device i2c 15 alias touchpad on end
 			end
 		end
 		device ref pch_espi on
diff --git a/src/mainboard/google/volteer/variants/halvor/overridetree.cb b/src/mainboard/google/volteer/variants/halvor/overridetree.cb
index 46a9014ed1..3a5ef7422c 100644
--- a/src/mainboard/google/volteer/variants/halvor/overridetree.cb
+++ b/src/mainboard/google/volteer/variants/halvor/overridetree.cb
@@ -93,7 +93,7 @@ chip soc/intel/tigerlake
 				register "irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_E15_IRQ)"
 				register "wake" = "GPE0_DW2_15"
 				register "detect" = "1"
-				device i2c 15 on end
+				device i2c 15 alias touchpad on end
 			end
 		end
 		device ref hda on end
diff --git a/src/mainboard/google/volteer/variants/lindar/overridetree.cb b/src/mainboard/google/volteer/variants/lindar/overridetree.cb
index 0f04be23a8..cbca78928a 100644
--- a/src/mainboard/google/volteer/variants/lindar/overridetree.cb
+++ b/src/mainboard/google/volteer/variants/lindar/overridetree.cb
@@ -240,7 +240,7 @@ chip soc/intel/tigerlake
 				register "irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_E15_IRQ)"
 				register "wake" = "GPE0_DW2_15"
 				register "detect" = "1"
-				device i2c 15 on end
+				device i2c 15 alias touchpad on end
 			end
 			chip drivers/i2c/hid
 				register "generic.hid" = ""SYNA0000""
diff --git a/src/mainboard/google/volteer/variants/malefor/overridetree.cb b/src/mainboard/google/volteer/variants/malefor/overridetree.cb
index 23e4cfc3be..3827bc2fa1 100644
--- a/src/mainboard/google/volteer/variants/malefor/overridetree.cb
+++ b/src/mainboard/google/volteer/variants/malefor/overridetree.cb
@@ -72,7 +72,7 @@ chip soc/intel/tigerlake
 				register "irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_E15_IRQ)"
 				register "wake" = "GPE0_DW2_15"
 				register "detect" = "1"
-				device i2c 15 on end
+				device i2c 15 alias touchpad on end
 			end
 		end
 		device ref hda on
diff --git a/src/mainboard/google/volteer/variants/terrador/overridetree.cb b/src/mainboard/google/volteer/variants/terrador/overridetree.cb
index ff99716d5a..2dd4c5a8b4 100644
--- a/src/mainboard/google/volteer/variants/terrador/overridetree.cb
+++ b/src/mainboard/google/volteer/variants/terrador/overridetree.cb
@@ -112,7 +112,7 @@ chip soc/intel/tigerlake
 				register "generic.wake" = "GPE0_DW2_15"
 				register "generic.detect" = "1"
 				register "hid_desc_reg_offset" = "0x01"
-				device i2c 15 on end
+				device i2c 15 alias touchpad on end
 			end
 		end
 		device ref pch_espi on
diff --git a/src/mainboard/google/volteer/variants/todor/overridetree.cb b/src/mainboard/google/volteer/variants/todor/overridetree.cb
index e5ebdd1576..2e712e687a 100644
--- a/src/mainboard/google/volteer/variants/todor/overridetree.cb
+++ b/src/mainboard/google/volteer/variants/todor/overridetree.cb
@@ -124,7 +124,7 @@ chip soc/intel/tigerlake
 				register "generic.wake" = "GPE0_DW2_15"
 				register "generic.detect" = "1"
 				register "hid_desc_reg_offset" = "0x01"
-				device i2c 15 on end
+				device i2c 15 alias touchpad on end
 			end
 		end
 		device ref pch_espi on
diff --git a/src/mainboard/google/volteer/variants/trondo/gpio.c b/src/mainboard/google/volteer/variants/trondo/gpio.c
index b759e3f1e0..dd7c8709b6 100644
--- a/src/mainboard/google/volteer/variants/trondo/gpio.c
+++ b/src/mainboard/google/volteer/variants/trondo/gpio.c
@@ -128,7 +128,7 @@ static const struct pad_config override_gpio_table[] = {
 	/* E12 : SPI1_MISO_IO1 ==> PEN_OC_ODL */
 	PAD_CFG_GPI(GPP_E12, NONE, DEEP),
 	/* E15 : ISH_GP6 ==> TRACKPAD_INT_ODL */
-	PAD_CFG_GPI_APIC(GPP_E15, NONE, PLTRST, LEVEL, INVERT),
+	PAD_CFG_GPI_IRQ_WAKE(GPP_E15, NONE, PLTRST, LEVEL, INVERT),
 	/* E16 : ISH_GP7 ==> WWAN_SIM1_DET_OD */
 	PAD_CFG_GPI(GPP_E16, NONE, DEEP),
 	/* E17 : THC0_SPI1_INT# ==> WWAN_PERST_L */
diff --git a/src/mainboard/google/volteer/variants/trondo/overridetree.cb b/src/mainboard/google/volteer/variants/trondo/overridetree.cb
index ec86cb52b4..6c0a6821aa 100644
--- a/src/mainboard/google/volteer/variants/trondo/overridetree.cb
+++ b/src/mainboard/google/volteer/variants/trondo/overridetree.cb
@@ -65,7 +65,7 @@ chip soc/intel/tigerlake
 				register "irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_E15_IRQ)"
 				register "wake" = "GPE0_DW2_15"
 				register "detect" = "1"
-				device i2c 15 on end
+				device i2c 15 alias touchpad on end
 			end
 		end
 		device ref north_xhci on
diff --git a/src/mainboard/google/volteer/variants/voema/overridetree.cb b/src/mainboard/google/volteer/variants/voema/overridetree.cb
index bbf51356ac..e4b2616807 100644
--- a/src/mainboard/google/volteer/variants/voema/overridetree.cb
+++ b/src/mainboard/google/volteer/variants/voema/overridetree.cb
@@ -69,7 +69,7 @@ chip soc/intel/tigerlake
 				register "irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_E15_IRQ)"
 				register "wake" = "GPE0_DW2_15"
 				register "detect" = "1"
-				device i2c 15 on end
+				device i2c 15 alias touchpad on end
 			end
 		end
 		device ref pch_espi on
diff --git a/src/mainboard/google/volteer/variants/volet/gpio.c b/src/mainboard/google/volteer/variants/volet/gpio.c
index 4f755bb9b5..407f093023 100644
--- a/src/mainboard/google/volteer/variants/volet/gpio.c
+++ b/src/mainboard/google/volteer/variants/volet/gpio.c
@@ -128,7 +128,7 @@ static const struct pad_config override_gpio_table[] = {
 	/* E12 : SPI1_MISO_IO1 ==> PEN_OC_ODL */
 	PAD_CFG_GPI(GPP_E12, NONE, DEEP),
 	/* E15 : ISH_GP6 ==> TRACKPAD_INT_ODL */
-	PAD_CFG_GPI_APIC(GPP_E15, NONE, PLTRST, LEVEL, INVERT),
+	PAD_CFG_GPI_IRQ_WAKE(GPP_E15, NONE, PLTRST, LEVEL, INVERT),
 	/* E16 : ISH_GP7 ==> WWAN_SIM1_DET_OD */
 	PAD_CFG_GPI(GPP_E16, NONE, DEEP),
 	/* E17 : THC0_SPI1_INT# ==> WWAN_PERST_L */
diff --git a/src/mainboard/google/volteer/variants/volet/overridetree.cb b/src/mainboard/google/volteer/variants/volet/overridetree.cb
index 1f8a7b26a4..4aaeda4073 100644
--- a/src/mainboard/google/volteer/variants/volet/overridetree.cb
+++ b/src/mainboard/google/volteer/variants/volet/overridetree.cb
@@ -107,7 +107,7 @@ chip soc/intel/tigerlake
 				register "irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_E15_IRQ)"
 				register "wake" = "GPE0_DW2_15"
 				register "detect" = "1"
-				device i2c 15 on end
+				device i2c 15 alias touchpad on end
 			end
 			chip drivers/i2c/hid
 				register "generic.hid" = ""SYNA0000""
diff --git a/src/mainboard/google/volteer/variants/volteer/overridetree.cb b/src/mainboard/google/volteer/variants/volteer/overridetree.cb
index cca74ba986..c489c2dc91 100644
--- a/src/mainboard/google/volteer/variants/volteer/overridetree.cb
+++ b/src/mainboard/google/volteer/variants/volteer/overridetree.cb
@@ -174,7 +174,7 @@ chip soc/intel/tigerlake
 				register "irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_E15_IRQ)"
 				register "wake" = "GPE0_DW2_15"
 				register "detect" = "1"
-				device i2c 15 on end
+				device i2c 15 alias touchpad on end
 			end
 		end
 		device ref hda on
diff --git a/src/mainboard/google/volteer/variants/volteer2/overridetree.cb b/src/mainboard/google/volteer/variants/volteer2/overridetree.cb
index ab49d5f320..ee181c86e0 100644
--- a/src/mainboard/google/volteer/variants/volteer2/overridetree.cb
+++ b/src/mainboard/google/volteer/variants/volteer2/overridetree.cb
@@ -233,7 +233,7 @@ chip soc/intel/tigerlake
 				register "irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_E15_IRQ)"
 				register "wake" = "GPE0_DW2_15"
 				register "detect" = "1"
-				device i2c 15 on end
+				device i2c 15 alias touchpad on end
 			end
 		end
 		device ref hda on
diff --git a/src/mainboard/google/volteer/variants/voxel/gpio.c b/src/mainboard/google/volteer/variants/voxel/gpio.c
index fc428b25a3..2d20fabb76 100644
--- a/src/mainboard/google/volteer/variants/voxel/gpio.c
+++ b/src/mainboard/google/volteer/variants/voxel/gpio.c
@@ -128,7 +128,7 @@ static const struct pad_config override_gpio_table[] = {
 	/* E12 : SPI1_MISO_IO1 ==> PEN_OC_ODL */
 	PAD_CFG_GPI(GPP_E12, NONE, DEEP),
 	/* E15 : ISH_GP6 ==> TRACKPAD_INT_ODL */
-	PAD_CFG_GPI_APIC(GPP_E15, NONE, PLTRST, LEVEL, INVERT),
+	PAD_CFG_GPI_IRQ_WAKE(GPP_E15, NONE, PLTRST, LEVEL, INVERT),
 	/* E16 : ISH_GP7 ==> WWAN_SIM1_DET_OD */
 	PAD_CFG_GPI(GPP_E16, NONE, DEEP),
 	/* E17 : THC0_SPI1_INT# ==> WWAN_PERST_L */
diff --git a/src/mainboard/google/volteer/variants/voxel/overridetree.cb b/src/mainboard/google/volteer/variants/voxel/overridetree.cb
index 3a4bb1bdec..6475a119ed 100644
--- a/src/mainboard/google/volteer/variants/voxel/overridetree.cb
+++ b/src/mainboard/google/volteer/variants/voxel/overridetree.cb
@@ -200,7 +200,7 @@ chip soc/intel/tigerlake
 				register "irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_E15_IRQ)"
 				register "wake" = "GPE0_DW2_15"
 				register "detect" = "1"
-				device i2c 15 on end
+				device i2c 15 alias touchpad on end
 			end
 			chip drivers/i2c/hid
 				register "generic.hid" = ""SYNA0000""

From 11ea868b02d8d07281d47e8c3d3bd5e2f4722799 Mon Sep 17 00:00:00 2001
From: Ingo Reitz <9l@9lo.re>
Date: Sat, 13 Dec 2025 00:56:41 +0100
Subject: [PATCH 2839/3886] mb/google/volteer/var/drobit: Update pl2 minimum
 value

Apply the change of commit a97fb7f9604e
("mb/google/volteer/variants: Update Power Limit2 minimum value")
to drobit since it looks like it has been forgotten. It is the
last variant where pl2 min != max.

TEST=Build and boot google/drobit and verify sane clock speeds and
tempoeratures under full CPU load.

Change-Id: I7b09825ebd95fd2795408cdaa0396bbf19baded9
Signed-off-by: Ingo Reitz <9l@9lo.re>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90501
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/google/volteer/variants/drobit/overridetree.cb | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/mainboard/google/volteer/variants/drobit/overridetree.cb b/src/mainboard/google/volteer/variants/drobit/overridetree.cb
index be0b99baff..ea25ff65b0 100644
--- a/src/mainboard/google/volteer/variants/drobit/overridetree.cb
+++ b/src/mainboard/google/volteer/variants/drobit/overridetree.cb
@@ -83,7 +83,7 @@ chip soc/intel/tigerlake
 						.time_window_min = 28 * MSECS_PER_SEC,
 						.time_window_max = 32 * MSECS_PER_SEC,
 						.granularity = 125,},
-					.pl2 = {.min_power = 28000,
+					.pl2 = {.min_power = 64000,
 						.max_power = 64000,
 						.time_window_min = 28 * MSECS_PER_SEC,
 						.time_window_max = 32 * MSECS_PER_SEC,

From 6459a2007a513305a39288628786e698380fd7d3 Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Thu, 11 Dec 2025 12:04:26 -0600
Subject: [PATCH 2840/3886] mb/{google,intel}: Add ROM type and address for
 MIPI camera sensors

Add ssdb.rom_type and rom_address registers to board variants for MIPI
camera sensor SSDB settings, which are necessary for the Intel driver
stack under Windows and mainline Linux. A handful of boards, mostly not
released to the public, include a commented-out placeholder as ROM type
24C1024 is currently unsupported.

TEST=tested with rest of patch train on screebo, redrix, and others.

Change-Id: I16b44609c1b07ac686d67cc59b4b5311495117ae
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90486
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
---
 .../google/brya/variants/anraggar/overridetree.cb         | 2 ++
 src/mainboard/google/brya/variants/brya0/overridetree.cb  | 8 ++++++++
 src/mainboard/google/brya/variants/craask/overridetree.cb | 2 ++
 src/mainboard/google/brya/variants/kano/overridetree.cb   | 4 ++++
 src/mainboard/google/brya/variants/meliks/overridetree.cb | 2 ++
 .../google/brya/variants/nivviks/overridetree.cb          | 2 ++
 src/mainboard/google/brya/variants/pirrha/overridetree.cb | 2 ++
 .../google/brya/variants/pujjolo/overridetree.cb          | 2 ++
 src/mainboard/google/brya/variants/redrix/overridetree.cb | 4 ++++
 .../google/brya/variants/redrix4es/overridetree.cb        | 4 ++++
 src/mainboard/google/brya/variants/riven/overridetree.cb  | 4 ++++
 src/mainboard/google/brya/variants/skolas/overridetree.cb | 8 ++++++++
 .../google/brya/variants/skolas4es/overridetree.cb        | 6 ++++++
 src/mainboard/google/brya/variants/teliks/overridetree.cb | 2 ++
 src/mainboard/google/brya/variants/telith/overridetree.cb | 2 ++
 src/mainboard/google/brya/variants/vell/overridetree.cb   | 3 +++
 src/mainboard/google/brya/variants/xivu/overridetree.cb   | 2 ++
 src/mainboard/google/brya/variants/yaviks/overridetree.cb | 2 ++
 .../google/brya/variants/yavilla/overridetree.cb          | 2 ++
 src/mainboard/google/brya/variants/zydron/overridetree.cb | 4 ++++
 .../google/dedede/variants/bugzzy/overridetree.cb         | 2 ++
 .../google/dedede/variants/drawcia/overridetree.cb        | 2 ++
 .../google/dedede/variants/haboki/overridetree.cb         | 2 ++
 .../google/dedede/variants/lalala/overridetree.cb         | 2 ++
 .../google/dedede/variants/magolor/overridetree.cb        | 2 ++
 .../google/dedede/variants/storo/overridetree.cb          | 2 ++
 .../google/dedede/variants/waddledoo/overridetree.cb      | 3 +++
 .../google/fatcat/variants/fatcat/overridetree.cb         | 4 ++++
 src/mainboard/google/rex/variants/kanix/overridetree.cb   | 2 ++
 src/mainboard/google/rex/variants/karis/overridetree.cb   | 2 ++
 src/mainboard/google/rex/variants/rex0/overridetree.cb    | 4 ++++
 src/mainboard/google/rex/variants/screebo/overridetree.cb | 2 ++
 .../mtlrvp/variants/baseboard/mtlrvp_p/devicetree.cb      | 2 ++
 .../intel/ptlrvp/variants/ptlrvp/overridetree.cb          | 4 ++++
 .../intel/ptlrvp/variants/ptlrvp_chromeec/overridetree.cb | 4 ++++
 35 files changed, 106 insertions(+)

diff --git a/src/mainboard/google/brya/variants/anraggar/overridetree.cb b/src/mainboard/google/brya/variants/anraggar/overridetree.cb
index d5814bfb38..877eec4700 100644
--- a/src/mainboard/google/brya/variants/anraggar/overridetree.cb
+++ b/src/mainboard/google/brya/variants/anraggar/overridetree.cb
@@ -274,6 +274,8 @@ chip soc/intel/alderlake
 				register "ssdb.vcm_type" = "VCM_DW9714"
 				register "vcm_address" = "0x0C"
 				register "vcm_name" = ""VCM0""
+				register "ssdb.rom_type" = "ROM_EEPROM_CAT24C64"
+				register "rom_address" = "0x50"
 				register "num_freq_entries" = "1"
 				register "link_freq[0]" = "560 * MHz"
 				register "remote_name" = ""IPU0""
diff --git a/src/mainboard/google/brya/variants/brya0/overridetree.cb b/src/mainboard/google/brya/variants/brya0/overridetree.cb
index 9184fc4e1b..3139af5218 100644
--- a/src/mainboard/google/brya/variants/brya0/overridetree.cb
+++ b/src/mainboard/google/brya/variants/brya0/overridetree.cb
@@ -548,6 +548,9 @@ chip soc/intel/alderlake
 				register "ssdb.vcm_type" = "VCM_DW9808"
 				register "vcm_address" = "0x0C"
 				register "vcm_name" = ""VCM0""
+				# placeholder; ROM type 24C1024 currently unsupported
+				# register "ssdb.rom_type" = "ROM_EEPROM_24C1024"
+				# register "rom_address" = "0x50"
 				register "num_freq_entries" = "2"
 				register "link_freq[0]" = "360 * MHz" # 360 MHz
 				register "link_freq[1]" = "180 * MHz" # 180 MHz
@@ -655,6 +658,8 @@ chip soc/intel/alderlake
 				register "ssdb.vcm_type" = "VCM_DW9808"
 				register "vcm_address" = "0x0C"
 				register "vcm_name" = ""VCM0""
+				register "ssdb.rom_type" = "ROM_EEPROM_CAT24C08"
+				register "rom_address" = "0x50"
 				register "num_freq_entries" = "2"
 				register "link_freq[0]" = "360 * MHz" # 360 MHz
 				register "link_freq[1]" = "180 * MHz" # 180 MHz
@@ -864,6 +869,9 @@ chip soc/intel/alderlake
 				register "ssdb.lanes_used" = "2"
 				register "ssdb.link_used" = "1"
 				register "ssdb.platform" = "PLAT_ADL"
+				# placeholder; ROM type 24C1024 currently unsupported
+				# register "ssdb.rom_type" = "ROM_EEPROM_24C1024"
+				# register "rom_address" = "0x50"
 				register "num_freq_entries" = "2"
 				register "link_freq[0]" = "384 * MHz" # 384 MHz
 				register "link_freq[1]" = "96 * MHz" # 96 MHz
diff --git a/src/mainboard/google/brya/variants/craask/overridetree.cb b/src/mainboard/google/brya/variants/craask/overridetree.cb
index 186845ed4b..86a5cfc465 100644
--- a/src/mainboard/google/brya/variants/craask/overridetree.cb
+++ b/src/mainboard/google/brya/variants/craask/overridetree.cb
@@ -534,6 +534,8 @@ chip soc/intel/alderlake
 				register "ssdb.vcm_type" = "VCM_DW9714"
 				register "vcm_address" = "0x0C"
 				register "vcm_name" = ""VCM0""
+				register "ssdb.rom_type" = "ROM_EEPROM_CAT24C08"
+				register "rom_address" = "0x50"
 				register "num_freq_entries" = "2"
 				register "link_freq[0]" = "720000000"
 				register "link_freq[1]" = "360000000"
diff --git a/src/mainboard/google/brya/variants/kano/overridetree.cb b/src/mainboard/google/brya/variants/kano/overridetree.cb
index d635ae788b..73065130e6 100644
--- a/src/mainboard/google/brya/variants/kano/overridetree.cb
+++ b/src/mainboard/google/brya/variants/kano/overridetree.cb
@@ -328,6 +328,8 @@ chip soc/intel/alderlake
 				register "ssdb.lanes_used" = "2"
 				register "ssdb.link_used" = "1"
 				register "ssdb.platform" = "PLAT_ADL"
+				register "ssdb.rom_type" = "ROM_EEPROM_CAT24C64"
+				register "rom_address" = "0x50"
 				register "num_freq_entries" = "1"
 				register "link_freq[0]" = "360 * MHz"
 				register "remote_name" = ""IPU0""
@@ -369,6 +371,8 @@ chip soc/intel/alderlake
 				register "ssdb.lanes_used" = "2"
 				register "ssdb.link_used" = "1"
 				register "ssdb.platform" = "PLAT_ADL"
+				register "ssdb.rom_type" = "ROM_EEPROM_CAT24C64"
+				register "rom_address" = "0x50"
 				register "num_freq_entries" = "1"
 				register "link_freq[0]" = "437 * MHz" # 437 MHz
 				register "remote_name" = ""IPU0""
diff --git a/src/mainboard/google/brya/variants/meliks/overridetree.cb b/src/mainboard/google/brya/variants/meliks/overridetree.cb
index d830da70d0..26cc775217 100644
--- a/src/mainboard/google/brya/variants/meliks/overridetree.cb
+++ b/src/mainboard/google/brya/variants/meliks/overridetree.cb
@@ -269,6 +269,8 @@ chip soc/intel/alderlake
 				register "ssdb.vcm_type" = "VCM_DW9714"
 				register "vcm_address" = "0x0C"
 				register "vcm_name" = ""VCM0""
+				register "ssdb.rom_type" = "ROM_EEPROM_CAT24C08"
+				register "rom_address" = "0x50"
 				register "num_freq_entries" = "2"
 				register "link_freq[0]" = "360000000"
 				register "link_freq[1]" = "180000000"
diff --git a/src/mainboard/google/brya/variants/nivviks/overridetree.cb b/src/mainboard/google/brya/variants/nivviks/overridetree.cb
index a4852608b1..b90cda1782 100644
--- a/src/mainboard/google/brya/variants/nivviks/overridetree.cb
+++ b/src/mainboard/google/brya/variants/nivviks/overridetree.cb
@@ -394,6 +394,8 @@ chip soc/intel/alderlake
 				register "ssdb.vcm_type" = "VCM_DW9714"
 				register "vcm_address" = "0x0C"
 				register "vcm_name" = ""VCM0""
+				register "ssdb.rom_type" = "ROM_EEPROM_CAT24C08"
+				register "rom_address" = "0x50"
 				register "num_freq_entries" = "1"
 				register "link_freq[0]" = "DEFAULT_LINK_FREQ"
 				register "remote_name" = ""IPU0""
diff --git a/src/mainboard/google/brya/variants/pirrha/overridetree.cb b/src/mainboard/google/brya/variants/pirrha/overridetree.cb
index 60354feafa..48f317157d 100644
--- a/src/mainboard/google/brya/variants/pirrha/overridetree.cb
+++ b/src/mainboard/google/brya/variants/pirrha/overridetree.cb
@@ -308,6 +308,8 @@ chip soc/intel/alderlake
 				register "ssdb.vcm_type" = "VCM_DW9714"
 				register "vcm_address" = "0x0C"
 				register "vcm_name" = ""VCM0""
+				register "ssdb.rom_type" = "ROM_EEPROM_CAT24C08"
+				register "rom_address" = "0x50"
 				register "num_freq_entries" = "2"
 				register "link_freq[0]" = "360000000"
 				register "link_freq[1]" = "180000000"
diff --git a/src/mainboard/google/brya/variants/pujjolo/overridetree.cb b/src/mainboard/google/brya/variants/pujjolo/overridetree.cb
index 69d66abc8d..738f1cb31e 100644
--- a/src/mainboard/google/brya/variants/pujjolo/overridetree.cb
+++ b/src/mainboard/google/brya/variants/pujjolo/overridetree.cb
@@ -398,6 +398,8 @@ chip soc/intel/alderlake
 				register "ssdb.vcm_type" = "VCM_DW9714"
 				register "vcm_address" = "0x0C"
 				register "vcm_name" = ""VCM0""
+				register "ssdb.rom_type" = "ROM_EEPROM_CAT24C08"
+				register "rom_address" = "0x50"
 				register "num_freq_entries" = "2"
 				register "link_freq[0]" = "360000000"
 				register "link_freq[1]" = "180000000"
diff --git a/src/mainboard/google/brya/variants/redrix/overridetree.cb b/src/mainboard/google/brya/variants/redrix/overridetree.cb
index 16e228182a..9f79c6ab21 100644
--- a/src/mainboard/google/brya/variants/redrix/overridetree.cb
+++ b/src/mainboard/google/brya/variants/redrix/overridetree.cb
@@ -422,6 +422,8 @@ chip soc/intel/alderlake
 				register "ssdb.lanes_used" = "2"
 				register "ssdb.link_used" = "1"
 				register "ssdb.platform" = "PLAT_ADL"
+				register "ssdb.rom_type" = "ROM_EEPROM_CAT24C64"
+				register "rom_address" = "0x50"
 				register "num_freq_entries" = "1"
 				register "link_freq[0]" = "DEFAULT_LINK_FREQ"
 				register "remote_name" = ""IPU0""
@@ -463,6 +465,8 @@ chip soc/intel/alderlake
 				register "ssdb.lanes_used" = "2"
 				register "ssdb.link_used" = "1"
 				register "ssdb.platform" = "PLAT_ADL"
+				register "ssdb.rom_type" = "ROM_EEPROM_CAT24C64"
+				register "rom_address" = "0x50"
 				register "num_freq_entries" = "1"
 				register "link_freq[0]" = "437000000"
 				register "remote_name" = ""IPU0""
diff --git a/src/mainboard/google/brya/variants/redrix4es/overridetree.cb b/src/mainboard/google/brya/variants/redrix4es/overridetree.cb
index 93638c9021..d36f91e414 100644
--- a/src/mainboard/google/brya/variants/redrix4es/overridetree.cb
+++ b/src/mainboard/google/brya/variants/redrix4es/overridetree.cb
@@ -352,6 +352,8 @@ chip soc/intel/alderlake
 				register "ssdb.lanes_used" = "2"
 				register "ssdb.link_used" = "1"
 				register "ssdb.platform" = "PLAT_ADL"
+				register "ssdb.rom_type" = "ROM_EEPROM_CAT24C64"
+				register "rom_address" = "0x50"
 				register "num_freq_entries" = "1"
 				register "link_freq[0]" = "DEFAULT_LINK_FREQ"
 				register "remote_name" = ""IPU0""
@@ -396,6 +398,8 @@ chip soc/intel/alderlake
 				register "ssdb.lanes_used" = "2"
 				register "ssdb.link_used" = "1"
 				register "ssdb.platform" = "PLAT_ADL"
+				register "ssdb.rom_type" = "ROM_EEPROM_CAT24C64"
+				register "rom_address" = "0x50"
 				register "num_freq_entries" = "1"
 				register "link_freq[0]" = "437000000"
 				register "remote_name" = ""IPU0""
diff --git a/src/mainboard/google/brya/variants/riven/overridetree.cb b/src/mainboard/google/brya/variants/riven/overridetree.cb
index 1bd2c148a5..60111e5af2 100644
--- a/src/mainboard/google/brya/variants/riven/overridetree.cb
+++ b/src/mainboard/google/brya/variants/riven/overridetree.cb
@@ -350,6 +350,8 @@ chip soc/intel/alderlake
 				register "ssdb.vcm_type" = "VCM_DW9714"
 				register "vcm_address" = "0x0C"
 				register "vcm_name" = ""VCM0""
+				register "ssdb.rom_type" = "ROM_EEPROM_CAT24C08"
+				register "rom_address" = "0x50"
 				register "num_freq_entries" = "1"
 				register "link_freq[0]" = "DEFAULT_LINK_FREQ"
 				register "remote_name" = ""IPU0""
@@ -399,6 +401,8 @@ chip soc/intel/alderlake
 				register "ssdb.vcm_type" = "VCM_DW9714"
 				register "vcm_address" = "0x0C"
 				register "vcm_name" = ""VCM0""
+				register "ssdb.rom_type" = "ROM_EEPROM_CAT24C08"
+				register "rom_address" = "0x50"
 				register "num_freq_entries" = "2"
 				register "link_freq[0]" = "720000000"
 				register "link_freq[1]" = "360000000"
diff --git a/src/mainboard/google/brya/variants/skolas/overridetree.cb b/src/mainboard/google/brya/variants/skolas/overridetree.cb
index 8cc296e4dc..0f5a6cf651 100644
--- a/src/mainboard/google/brya/variants/skolas/overridetree.cb
+++ b/src/mainboard/google/brya/variants/skolas/overridetree.cb
@@ -547,6 +547,9 @@ chip soc/intel/alderlake
 				register "ssdb.vcm_type" = "VCM_DW9808"
 				register "vcm_address" = "0x0C"
 				register "vcm_name" = ""VCM0""
+				# placeholder; ROM type 24C1024 currently unsupported
+				# register "ssdb.rom_type" = "ROM_EEPROM_24C1024"
+				# register "rom_address" = "0x50"
 				register "num_freq_entries" = "2"
 				register "link_freq[0]" = "360 * MHz" # 360 MHz
 				register "link_freq[1]" = "180 * MHz" # 180 MHz
@@ -654,6 +657,8 @@ chip soc/intel/alderlake
 				register "ssdb.vcm_type" = "VCM_DW9808"
 				register "vcm_address" = "0x0C"
 				register "vcm_name" = ""VCM0""
+				register "ssdb.rom_type" = "ROM_EEPROM_CAT24C08"
+				register "rom_address" = "0x50"
 				register "num_freq_entries" = "2"
 				register "link_freq[0]" = "360 * MHz" # 360 MHz
 				register "link_freq[1]" = "180 * MHz" # 180 MHz
@@ -863,6 +868,9 @@ chip soc/intel/alderlake
 				register "ssdb.lanes_used" = "2"
 				register "ssdb.link_used" = "1"
 				register "ssdb.platform" = "PLAT_ADL"
+				# placeholder; ROM type 24C1024 currently unsupported
+				# register "ssdb.rom_type" = "ROM_EEPROM_24C1024"
+				# register "rom_address" = "0x50"
 				register "num_freq_entries" = "2"
 				register "link_freq[0]" = "384 * MHz" # 384 MHz
 				register "link_freq[1]" = "96 * MHz" # 96 MHz
diff --git a/src/mainboard/google/brya/variants/skolas4es/overridetree.cb b/src/mainboard/google/brya/variants/skolas4es/overridetree.cb
index d7b04119d8..95a27df342 100644
--- a/src/mainboard/google/brya/variants/skolas4es/overridetree.cb
+++ b/src/mainboard/google/brya/variants/skolas4es/overridetree.cb
@@ -388,6 +388,9 @@ chip soc/intel/alderlake
 				register "ssdb.vcm_type" = "VCM_DW9808"
 				register "vcm_address" = "0x0C"
 				register "vcm_name" = ""VCM0""
+				# placeholder; ROM type 24C1024 currently unsupported
+				# register "ssdb.rom_type" = "ROM_EEPROM_24C1024"
+				# register "rom_address" = "0x50"
 				register "num_freq_entries" = "2"
 				register "link_freq[0]" = "360 * MHz" # 360 MHz
 				register "link_freq[1]" = "180 * MHz" # 180 MHz
@@ -589,6 +592,9 @@ chip soc/intel/alderlake
 				register "ssdb.lanes_used" = "2"
 				register "ssdb.link_used" = "1"
 				register "ssdb.platform" = "PLAT_ADL"
+				# placeholder; ROM type 24C1024 currently unsupported
+				# register "ssdb.rom_type" = "ROM_EEPROM_24C1024"
+				# register "rom_address" = "0x50"
 				register "num_freq_entries" = "2"
 				register "link_freq[0]" = "384 * MHz" # 384 MHz
 				register "link_freq[1]" = "96 * MHz" # 96 MHz
diff --git a/src/mainboard/google/brya/variants/teliks/overridetree.cb b/src/mainboard/google/brya/variants/teliks/overridetree.cb
index 9dde7bfed8..121f432af1 100644
--- a/src/mainboard/google/brya/variants/teliks/overridetree.cb
+++ b/src/mainboard/google/brya/variants/teliks/overridetree.cb
@@ -291,6 +291,8 @@ chip soc/intel/alderlake
 				register "ssdb.vcm_type" = "VCM_DW9714"
 				register "vcm_address" = "0x0C"
 				register "vcm_name" = ""VCM0""
+				register "ssdb.rom_type" = "ROM_EEPROM_CAT24C64"
+				register "rom_address" = "0x50"
 				register "num_freq_entries" = "1"
 				register "link_freq[0]" = "560 * MHz"
 				register "remote_name" = ""IPU0""
diff --git a/src/mainboard/google/brya/variants/telith/overridetree.cb b/src/mainboard/google/brya/variants/telith/overridetree.cb
index bd80d97b39..7b5ebee441 100644
--- a/src/mainboard/google/brya/variants/telith/overridetree.cb
+++ b/src/mainboard/google/brya/variants/telith/overridetree.cb
@@ -417,6 +417,8 @@ chip soc/intel/alderlake
 				register "ssdb.vcm_type" = "VCM_DW9714"
 				register "vcm_address" = "0x0C"
 				register "vcm_name" = ""VCM0""
+				register "ssdb.rom_type" = "ROM_EEPROM_CAT24C64"
+				register "rom_address" = "0x50"
 				register "num_freq_entries" = "1"
 				register "link_freq[0]" = "560 * MHz"
 				register "remote_name" = ""IPU0""
diff --git a/src/mainboard/google/brya/variants/vell/overridetree.cb b/src/mainboard/google/brya/variants/vell/overridetree.cb
index 87d9748189..7fa68933df 100644
--- a/src/mainboard/google/brya/variants/vell/overridetree.cb
+++ b/src/mainboard/google/brya/variants/vell/overridetree.cb
@@ -347,6 +347,9 @@ chip soc/intel/alderlake
 				register "ssdb.lanes_used" = "4"
 				register "ssdb.link_used" = "1"
 				register "ssdb.platform" = "PLAT_ADL"
+				# placeholder; ROM type 24C1024 currently unsupported
+				# register "ssdb.rom_type" = "ROM_EEPROM_24C1024"
+				# register "rom_address" = "0x50"
 				register "num_freq_entries" = "2"
 				register "link_freq[0]" = "360000000"
 				register "link_freq[1]" = "180000000"
diff --git a/src/mainboard/google/brya/variants/xivu/overridetree.cb b/src/mainboard/google/brya/variants/xivu/overridetree.cb
index bf9a6c45ec..5b1dc9fd3d 100644
--- a/src/mainboard/google/brya/variants/xivu/overridetree.cb
+++ b/src/mainboard/google/brya/variants/xivu/overridetree.cb
@@ -258,6 +258,8 @@ chip soc/intel/alderlake
 				register "ssdb.vcm_type" = "VCM_DW9714"
 				register "vcm_address" = "0x0C"
 				register "vcm_name" = ""VCM0""
+				register "ssdb.rom_type" = "ROM_EEPROM_CAT24C08"
+				register "rom_address" = "0x50"
 				register "num_freq_entries" = "2"
 				register "link_freq[0]" = "360000000"
 				register "link_freq[1]" = "180000000"
diff --git a/src/mainboard/google/brya/variants/yaviks/overridetree.cb b/src/mainboard/google/brya/variants/yaviks/overridetree.cb
index 6ecfa73ab3..334b2bc619 100644
--- a/src/mainboard/google/brya/variants/yaviks/overridetree.cb
+++ b/src/mainboard/google/brya/variants/yaviks/overridetree.cb
@@ -336,6 +336,8 @@ chip soc/intel/alderlake
 				register "ssdb.vcm_type" = "VCM_DW9714"
 				register "vcm_address" = "0x0C"
 				register "vcm_name" = ""VCM0""
+				register "ssdb.rom_type" = "ROM_EEPROM_CAT24C08"
+				register "rom_address" = "0x50"
 				register "num_freq_entries" = "2"
 				register "link_freq[0]" = "360000000"
 				register "link_freq[1]" = "180000000"
diff --git a/src/mainboard/google/brya/variants/yavilla/overridetree.cb b/src/mainboard/google/brya/variants/yavilla/overridetree.cb
index f88db8d5b1..588919da54 100644
--- a/src/mainboard/google/brya/variants/yavilla/overridetree.cb
+++ b/src/mainboard/google/brya/variants/yavilla/overridetree.cb
@@ -371,6 +371,8 @@ chip soc/intel/alderlake
 				register "ssdb.vcm_type" = "VCM_DW9714"
 				register "vcm_address" = "0x0C"
 				register "vcm_name" = ""VCM0""
+				register "ssdb.rom_type" = "ROM_EEPROM_CAT24C08"
+				register "rom_address" = "0x50"
 				register "num_freq_entries" = "2"
 				register "link_freq[0]" = "360000000"
 				register "link_freq[1]" = "180000000"
diff --git a/src/mainboard/google/brya/variants/zydron/overridetree.cb b/src/mainboard/google/brya/variants/zydron/overridetree.cb
index 67b32dad44..a632d36294 100644
--- a/src/mainboard/google/brya/variants/zydron/overridetree.cb
+++ b/src/mainboard/google/brya/variants/zydron/overridetree.cb
@@ -304,6 +304,8 @@ chip soc/intel/alderlake
 				register "ssdb.lanes_used" = "2"
 				register "ssdb.link_used" = "1"
 				register "ssdb.platform" = "PLAT_ADL"
+				register "ssdb.rom_type" = "ROM_EEPROM_CAT24C64"
+				register "rom_address" = "0x50"
 				register "num_freq_entries" = "1"
 				register "link_freq[0]" = "360 * MHz"
 				register "remote_name" = ""IPU0""
@@ -345,6 +347,8 @@ chip soc/intel/alderlake
 				register "ssdb.lanes_used" = "2"
 				register "ssdb.link_used" = "1"
 				register "ssdb.platform" = "PLAT_ADL"
+				register "ssdb.rom_type" = "ROM_EEPROM_CAT24C64"
+				register "rom_address" = "0x50"
 				register "num_freq_entries" = "1"
 				register "link_freq[0]" = "437 * MHz" # 437 MHz
 				register "remote_name" = ""IPU0""
diff --git a/src/mainboard/google/dedede/variants/bugzzy/overridetree.cb b/src/mainboard/google/dedede/variants/bugzzy/overridetree.cb
index 4d51d19fbc..6c399f8768 100644
--- a/src/mainboard/google/dedede/variants/bugzzy/overridetree.cb
+++ b/src/mainboard/google/dedede/variants/bugzzy/overridetree.cb
@@ -244,6 +244,8 @@ chip soc/intel/jasperlake
 				register "ssdb.vcm_type" = "VCM_DW9714"
 				register "vcm_address" = "0x0C"
 				register "vcm_name" = ""VCM0""
+				register "ssdb.rom_type" = "ROM_EEPROM_CAT24C08"
+				register "rom_address" = "0x50"
 				register "num_freq_entries" = "2"
 				register "link_freq[0]" = "360000000"
 				register "link_freq[1]" = "180000000"
diff --git a/src/mainboard/google/dedede/variants/drawcia/overridetree.cb b/src/mainboard/google/dedede/variants/drawcia/overridetree.cb
index fdcfd0226b..c84f9487fe 100644
--- a/src/mainboard/google/dedede/variants/drawcia/overridetree.cb
+++ b/src/mainboard/google/dedede/variants/drawcia/overridetree.cb
@@ -305,6 +305,8 @@ chip soc/intel/jasperlake
 				register "ssdb.vcm_type" = "VCM_DW9714"
 				register "vcm_address" = "0x0C"
 				register "vcm_name" = ""VCM0""
+				register "ssdb.rom_type" = "ROM_EEPROM_CAT24C08"
+				register "rom_address" = "0x50"
 				register "num_freq_entries" = "2"
 				register "link_freq[0]" = "360000000"
 				register "link_freq[1]" = "180000000"
diff --git a/src/mainboard/google/dedede/variants/haboki/overridetree.cb b/src/mainboard/google/dedede/variants/haboki/overridetree.cb
index d8bb09168d..92b3bb2c48 100644
--- a/src/mainboard/google/dedede/variants/haboki/overridetree.cb
+++ b/src/mainboard/google/dedede/variants/haboki/overridetree.cb
@@ -219,6 +219,8 @@ chip soc/intel/jasperlake
 				register "ssdb.vcm_type" = "VCM_DW9714"
 				register "vcm_address" = "0x0C"
 				register "vcm_name" = ""VCM0""
+				register "ssdb.rom_type" = "ROM_EEPROM_CAT24C08"
+				register "rom_address" = "0x50"
 				register "num_freq_entries" = "2"
 				register "link_freq[0]" = "360000000"
 				register "link_freq[1]" = "180000000"
diff --git a/src/mainboard/google/dedede/variants/lalala/overridetree.cb b/src/mainboard/google/dedede/variants/lalala/overridetree.cb
index 358151025c..9609011a0c 100644
--- a/src/mainboard/google/dedede/variants/lalala/overridetree.cb
+++ b/src/mainboard/google/dedede/variants/lalala/overridetree.cb
@@ -217,6 +217,8 @@ chip soc/intel/jasperlake
 				register "ssdb.vcm_type" = "VCM_DW9714"
 				register "vcm_address" = "0x0C"
 				register "vcm_name" = ""VCM0""
+				register "ssdb.rom_type" = "ROM_EEPROM_CAT24C08"
+				register "rom_address" = "0x50"
 				register "num_freq_entries" = "1"
 				register "link_freq[0]" = "DEFAULT_LINK_FREQ"
 				register "remote_name" = ""IPU0""
diff --git a/src/mainboard/google/dedede/variants/magolor/overridetree.cb b/src/mainboard/google/dedede/variants/magolor/overridetree.cb
index 8f4176e85f..a09adeeff2 100644
--- a/src/mainboard/google/dedede/variants/magolor/overridetree.cb
+++ b/src/mainboard/google/dedede/variants/magolor/overridetree.cb
@@ -397,6 +397,8 @@ chip soc/intel/jasperlake
 				register "ssdb.vcm_type" = "VCM_DW9714"
 				register "vcm_address" = "0x0C"
 				register "vcm_name" = ""VCM0""
+				register "ssdb.rom_type" = "ROM_EEPROM_CAT24C08"
+				register "rom_address" = "0x50"
 				register "num_freq_entries" = "2"
 				register "link_freq[0]" = "720000000"
 				register "link_freq[1]" = "360000000"
diff --git a/src/mainboard/google/dedede/variants/storo/overridetree.cb b/src/mainboard/google/dedede/variants/storo/overridetree.cb
index 1b21bf01af..c22c796f68 100644
--- a/src/mainboard/google/dedede/variants/storo/overridetree.cb
+++ b/src/mainboard/google/dedede/variants/storo/overridetree.cb
@@ -234,6 +234,8 @@ chip soc/intel/jasperlake
 				register "ssdb.vcm_type" = "VCM_DW9714"
 				register "vcm_address" = "0x0C"
 				register "vcm_name" = ""VCM0""
+				register "ssdb.rom_type" = "ROM_EEPROM_CAT24C08"
+				register "rom_address" = "0x50"
 				register "num_freq_entries" = "2"
 				register "link_freq[0]" = "360000000"
 				register "link_freq[1]" = "180000000"
diff --git a/src/mainboard/google/dedede/variants/waddledoo/overridetree.cb b/src/mainboard/google/dedede/variants/waddledoo/overridetree.cb
index acdfe0e496..228a1720a6 100644
--- a/src/mainboard/google/dedede/variants/waddledoo/overridetree.cb
+++ b/src/mainboard/google/dedede/variants/waddledoo/overridetree.cb
@@ -151,6 +151,9 @@ chip soc/intel/jasperlake
 				register "ssdb.vcm_type" = "VCM_DW9808"
 				register "vcm_address" = "0x0C"
 				register "vcm_name" = ""VCM0""
+				# placeholder; ROM type 24C1024 currently unsupported
+				# register "ssdb.rom_type" = "ROM_EEPROM_24C1024"
+				# register "rom_address" = "0x50"
 				register "num_freq_entries" = "2"
 				register "link_freq[0]" = "360000000"
 				register "link_freq[1]" = "180000000"
diff --git a/src/mainboard/google/fatcat/variants/fatcat/overridetree.cb b/src/mainboard/google/fatcat/variants/fatcat/overridetree.cb
index f54b472b42..f520410847 100644
--- a/src/mainboard/google/fatcat/variants/fatcat/overridetree.cb
+++ b/src/mainboard/google/fatcat/variants/fatcat/overridetree.cb
@@ -662,6 +662,8 @@ chip soc/intel/pantherlake
 				register "vcm_address" = "0x0C"
 				register "vcm_name" = ""VCM1""
 
+				register "ssdb.rom_type" = "ROM_EEPROM_CAT24C16"
+				register "rom_address" = "0x50"
 				register "ssdb.lanes_used" = "4"
 				register "ssdb.platform" = "PLAT_PTL"
 				register "num_freq_entries" = "1"
@@ -765,6 +767,8 @@ chip soc/intel/pantherlake
 				register "vcm_address" = "0x0C"
 				register "vcm_name" = ""VCM1""
 
+				register "ssdb.rom_type" = "ROM_EEPROM_CAT24C16"
+				register "rom_address" = "0x50"
 				register "ssdb.lanes_used" = "2"
 				register "ssdb.platform" = "PLAT_PTL"
 				register "num_freq_entries" = "1"
diff --git a/src/mainboard/google/rex/variants/kanix/overridetree.cb b/src/mainboard/google/rex/variants/kanix/overridetree.cb
index 3b8f9b78af..a9feef6b16 100644
--- a/src/mainboard/google/rex/variants/kanix/overridetree.cb
+++ b/src/mainboard/google/rex/variants/kanix/overridetree.cb
@@ -511,6 +511,8 @@ chip soc/intel/meteorlake
 				register "ssdb.lanes_used" = "2"
 				register "ssdb.link_used" = "1"
 				register "ssdb.platform" = "PLAT_MTL"
+				register "ssdb.rom_type" = "ROM_EEPROM_CAT24C64"
+				register "rom_address" = "0x50"
 				register "num_freq_entries" = "1"
 				register "link_freq[0]" = "437 * MHz"
 				register "remote_name" = ""IPU0""
diff --git a/src/mainboard/google/rex/variants/karis/overridetree.cb b/src/mainboard/google/rex/variants/karis/overridetree.cb
index 904d437986..580bb9d033 100644
--- a/src/mainboard/google/rex/variants/karis/overridetree.cb
+++ b/src/mainboard/google/rex/variants/karis/overridetree.cb
@@ -466,6 +466,8 @@ chip soc/intel/meteorlake
 				register "ssdb.lanes_used" = "2"
 				register "ssdb.link_used" = "1"
 				register "ssdb.platform" = "PLAT_MTL"
+				register "ssdb.rom_type" = "ROM_EEPROM_CAT24C64"
+				register "rom_address" = "0x50"
 				register "num_freq_entries" = "1"
 				register "link_freq[0]" = "437 * MHz"
 				register "remote_name" = ""IPU0""
diff --git a/src/mainboard/google/rex/variants/rex0/overridetree.cb b/src/mainboard/google/rex/variants/rex0/overridetree.cb
index 73e285e027..c82d773ff0 100644
--- a/src/mainboard/google/rex/variants/rex0/overridetree.cb
+++ b/src/mainboard/google/rex/variants/rex0/overridetree.cb
@@ -474,6 +474,8 @@ chip soc/intel/meteorlake
 				register "ssdb.vcm_type" = "VCM_DW9714"
 				register "vcm_address" = "0x0C"
 				register "vcm_name" = ""VCM0""
+				register "ssdb.rom_type" = "ROM_EEPROM_CAT24C16"
+				register "rom_address" = "0x50"
 				register "num_freq_entries" = "1"
 				register "link_freq[0]" = "560 * MHz" # 560 MHz
 				register "remote_name" = ""IPU0""
@@ -627,6 +629,8 @@ chip soc/intel/meteorlake
 				register "ssdb.lanes_used" = "2"
 				register "ssdb.link_used" = "1"
 				register "ssdb.platform" = "PLAT_MTL"
+				register "ssdb.rom_type" = "ROM_EEPROM_CAT24C64"
+				register "rom_address" = "0x50"
 				register "num_freq_entries" = "1"
 				register "link_freq[0]" = "437 * MHz"
 				register "remote_name" = ""IPU0""
diff --git a/src/mainboard/google/rex/variants/screebo/overridetree.cb b/src/mainboard/google/rex/variants/screebo/overridetree.cb
index 005d352b24..b1e8ff7ce1 100644
--- a/src/mainboard/google/rex/variants/screebo/overridetree.cb
+++ b/src/mainboard/google/rex/variants/screebo/overridetree.cb
@@ -517,6 +517,8 @@ chip soc/intel/meteorlake
 				register "ssdb.lanes_used" = "4"
 				register "ssdb.link_used" = "1"
 				register "ssdb.platform" = "PLAT_MTL"
+				register "ssdb.rom_type" = "ROM_EEPROM_CAT24C64"
+				register "rom_address" = "0x50"
 				register "num_freq_entries" = "1"
 				register "link_freq[0]" = "400 * MHz"
 				register "remote_name" = ""IPU0""
diff --git a/src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/devicetree.cb b/src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/devicetree.cb
index c877a97945..a01364dde1 100644
--- a/src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/devicetree.cb
+++ b/src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/devicetree.cb
@@ -481,6 +481,8 @@ chip soc/intel/meteorlake
 				register "vcm_address" = "0x0C"
 				register "vcm_name" = ""VCM1""
 
+				register "ssdb.rom_type" = "ROM_EEPROM_CAT24C16"
+				register "rom_address" = "0x50"
 				register "ssdb.lanes_used" = "4"
 				register "ssdb.platform" = "PLAT_MTL"
 				register "num_freq_entries" = "1"
diff --git a/src/mainboard/intel/ptlrvp/variants/ptlrvp/overridetree.cb b/src/mainboard/intel/ptlrvp/variants/ptlrvp/overridetree.cb
index b92a73a616..73294ec6f1 100644
--- a/src/mainboard/intel/ptlrvp/variants/ptlrvp/overridetree.cb
+++ b/src/mainboard/intel/ptlrvp/variants/ptlrvp/overridetree.cb
@@ -662,6 +662,8 @@ chip soc/intel/pantherlake
 				register "vcm_address" = "0x0C"
 				register "vcm_name" = ""VCM1""
 
+				register "ssdb.rom_type" = "ROM_EEPROM_CAT24C16"
+				register "rom_address" = "0x50"
 				register "ssdb.lanes_used" = "4"
 				register "ssdb.platform" = "PLAT_PTL"
 				register "num_freq_entries" = "1"
@@ -765,6 +767,8 @@ chip soc/intel/pantherlake
 				register "vcm_address" = "0x0C"
 				register "vcm_name" = ""VCM1""
 
+				register "ssdb.rom_type" = "ROM_EEPROM_CAT24C16"
+				register "rom_address" = "0x50"
 				register "ssdb.lanes_used" = "2"
 				register "ssdb.platform" = "PLAT_PTL"
 				register "num_freq_entries" = "1"
diff --git a/src/mainboard/intel/ptlrvp/variants/ptlrvp_chromeec/overridetree.cb b/src/mainboard/intel/ptlrvp/variants/ptlrvp_chromeec/overridetree.cb
index d2682891f6..2c7782f841 100644
--- a/src/mainboard/intel/ptlrvp/variants/ptlrvp_chromeec/overridetree.cb
+++ b/src/mainboard/intel/ptlrvp/variants/ptlrvp_chromeec/overridetree.cb
@@ -662,6 +662,8 @@ chip soc/intel/pantherlake
 				register "vcm_address" = "0x0C"
 				register "vcm_name" = ""VCM1""
 
+				register "ssdb.rom_type" = "ROM_EEPROM_CAT24C16"
+				register "rom_address" = "0x50"
 				register "ssdb.lanes_used" = "4"
 				register "ssdb.platform" = "PLAT_PTL"
 				register "num_freq_entries" = "1"
@@ -765,6 +767,8 @@ chip soc/intel/pantherlake
 				register "vcm_address" = "0x0C"
 				register "vcm_name" = ""VCM1""
 
+				register "ssdb.rom_type" = "ROM_EEPROM_CAT24C16"
+				register "rom_address" = "0x50"
 				register "ssdb.lanes_used" = "2"
 				register "ssdb.platform" = "PLAT_PTL"
 				register "num_freq_entries" = "1"

From ea099e8b8c999d8b5cc93da86ec4513413fddac4 Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Thu, 11 Dec 2025 20:07:00 -0600
Subject: [PATCH 2841/3886] drivers/intel/mipi_camera: Split DSM generation
 into per-UUID functions

Refactor camera_generate_dsm() to call separate functions for each
DSM UUID type, improving code organization and maintainability, in
preparation for adding the generation of additional DSM UUIDs in
subsequent patches.

This is a non-functional change.

TEST=tested with rest of patch train on screebo, redrix, and others.

Change-Id: I8b3fb6e3004ea30aa7c11217c9971bddb977ded5
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90487
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
---
 src/drivers/intel/mipi_camera/camera.c | 28 ++++++++++++++++++--------
 1 file changed, 20 insertions(+), 8 deletions(-)

diff --git a/src/drivers/intel/mipi_camera/camera.c b/src/drivers/intel/mipi_camera/camera.c
index 0a0439a042..d827ea6d0c 100644
--- a/src/drivers/intel/mipi_camera/camera.c
+++ b/src/drivers/intel/mipi_camera/camera.c
@@ -220,16 +220,9 @@ static uint32_t address_for_dev_type(const struct device *dev, uint8_t dev_type)
 	return (((uint32_t)i2c_bus) << 24 | ((uint32_t)i2c_addr) << 8 | dev_type);
 }
 
-static void camera_generate_dsm(const struct device *dev)
+static void camera_generate_dsm_sensor_name(const struct device *dev)
 {
 	struct drivers_intel_mipi_camera_config *config = dev->chip_info;
-	int local1_ret = 1 + (config->ssdb.vcm_type ? 1 : 0) + (config->ssdb.rom_type ? 1 : 0);
-	int next_local1 = 1;
-	/* Method (_DSM, 4, NotSerialized) */
-	acpigen_write_method("_DSM", 4);
-
-	/* ToBuffer (Arg0, Local0) */
-	acpigen_write_to_buffer(ARG0_OP, LOCAL0_OP);
 
 	/* If (LEqual (Local0, ToUUID(uuid))) */
 	acpigen_write_if();
@@ -238,6 +231,13 @@ static void camera_generate_dsm(const struct device *dev)
 	acpigen_write_uuid(SENSOR_NAME_UUID);
 	acpigen_write_return_string(config->sensor_name ? config->sensor_name : "UNKNOWN");
 	acpigen_pop_len();	/* If */
+}
+
+static void camera_generate_dsm_sensor_type(const struct device *dev)
+{
+	struct drivers_intel_mipi_camera_config *config = dev->chip_info;
+	int local1_ret = 1 + (config->ssdb.vcm_type ? 1 : 0) + (config->ssdb.rom_type ? 1 : 0);
+	int next_local1 = 1;
 
 	/* If (LEqual (Local0, ToUUID(uuid))) */
 	acpigen_write_if();
@@ -272,6 +272,18 @@ static void camera_generate_dsm(const struct device *dev)
 	}
 
 	acpigen_pop_len();      /* If uuid */
+}
+
+static void camera_generate_dsm(const struct device *dev)
+{
+	/* Method (_DSM, 4, NotSerialized) */
+	acpigen_write_method("_DSM", 4);
+
+	/* ToBuffer (Arg0, Local0) */
+	acpigen_write_to_buffer(ARG0_OP, LOCAL0_OP);
+
+	camera_generate_dsm_sensor_name(dev);
+	camera_generate_dsm_sensor_type(dev);
 
 	/* Return (Buffer (One) { 0x0 }) */
 	acpigen_write_return_singleton_buffer(0x0);

From c8f89e00e4c90991a817380b2e9ced34b1048159 Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Thu, 11 Dec 2025 21:00:13 -0600
Subject: [PATCH 2842/3886] drv/intel/mipi_camera: Refactor DSM generator
 functions

Rename UUID macros to match external conventions used in Linux kernel
and Windows Camera DDK:
- SENSOR_NAME_UUID -> UUID_DSM_SENSOR
- SENSOR_TYPE_UUID -> UUID_DSM_I2C

Rename functions for clarity:
- camera_generate_dsm_sensor_name -> camera_generate_dsm_sensor
- camera_generate_dsm_sensor_type -> camera_generate_dsm_i2c

Add ACPI-compliant function query support (Arg2==0) to sensor DSM,
returning bitmask of supported functions as required by ACPI spec.

Add ASL documentation comment blocks above each DSM generator function
showing the generated ACPI code structure.

Improve variable naming (i2c_dev_count, i2c_dev_idx) for readability.

TEST=tested with rest of patch train on screebo, redrix, and others.

Change-Id: I38facaf85ea59aa82621d82555858c0d72b1ee30
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90488
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
---
 src/drivers/intel/mipi_camera/camera.c | 97 +++++++++++++++++++++-----
 1 file changed, 78 insertions(+), 19 deletions(-)

diff --git a/src/drivers/intel/mipi_camera/camera.c b/src/drivers/intel/mipi_camera/camera.c
index d827ea6d0c..f937e7220b 100644
--- a/src/drivers/intel/mipi_camera/camera.c
+++ b/src/drivers/intel/mipi_camera/camera.c
@@ -17,8 +17,8 @@
 	GUID_INIT(0x8A395669, 0x11F7, 0x4EA9, \
 	0x9C, 0x7D, 0x20, 0xEE, 0x0A, 0xB5, 0xCA, 0x40)
 
-#define SENSOR_NAME_UUID	"822ace8f-2814-4174-a56b-5f029fe079ee"
-#define SENSOR_TYPE_UUID	"26257549-9271-4ca4-bb43-c4899d5a4881"
+#define UUID_DSM_SENSOR		"822ace8f-2814-4174-a56b-5f029fe079ee"
+#define UUID_DSM_I2C		"26257549-9271-4ca4-bb43-c4899d5a4881"
 #define DEFAULT_ENDPOINT	0
 #define DEFAULT_REMOTE_NAME	"\\_SB.PCI0.CIO2"
 #define CIO2_PCI_DEV		0x14
@@ -220,53 +220,112 @@ static uint32_t address_for_dev_type(const struct device *dev, uint8_t dev_type)
 	return (((uint32_t)i2c_bus) << 24 | ((uint32_t)i2c_addr) << 8 | dev_type);
 }
 
-static void camera_generate_dsm_sensor_name(const struct device *dev)
+/*
+ * Generate ASL DSM code for Sensor Device
+ *
+ * Generated ASL:
+ * If (LEqual (Local0, ToUUID ("822ace8f-2814-4174-a56b-5f029fe079ee"))) {
+ *     If (LEqual (Arg2, Zero)) {
+ *         If (LEqual (Arg1, Zero)) {
+ *             Return (Buffer (One) { 0x3 })
+ *         } Else {
+ *             Return (Buffer (One) { 0x1 })
+ *         }
+ *     }
+ *     If (LEqual (Arg2, One)) {
+ *         If (sensor_name exists)
+ *             Return ("sensor_name")
+ *         Else
+ *             Return ("UNKNOWN")
+ *     }
+ * }
+ */
+static void camera_generate_dsm_sensor(const struct device *dev)
 {
 	struct drivers_intel_mipi_camera_config *config = dev->chip_info;
 
-	/* If (LEqual (Local0, ToUUID(uuid))) */
+	/* If (LEqual (Local0, ToUUID (UUID_DSM_SENSOR))) */
 	acpigen_write_if();
 	acpigen_emit_byte(LEQUAL_OP);
 	acpigen_emit_byte(LOCAL0_OP);
-	acpigen_write_uuid(SENSOR_NAME_UUID);
-	acpigen_write_return_string(config->sensor_name ? config->sensor_name : "UNKNOWN");
-	acpigen_pop_len();	/* If */
+	acpigen_write_uuid(UUID_DSM_SENSOR);
+
+	/* If (LEqual (Arg2, Zero)) */
+	acpigen_write_if_lequal_op_int(ARG2_OP, 0);
+	/* If (LEqual (Arg1, Zero)) */
+	acpigen_write_if_lequal_op_int(ARG1_OP, 0);
+	/* Return (Buffer (One) { 0x3 }) */
+	acpigen_write_return_singleton_buffer(0x3);
+	/* Else */
+	acpigen_write_else();
+	/* Return (Buffer (One) { 0x1 }) */
+	acpigen_write_return_singleton_buffer(0x1);
+	acpigen_pop_len();	/* If Arg1=0 */
+
+	acpigen_pop_len();	/* If Arg2=0 */
+
+	/* If (LEqual (Arg2, One)) */
+	acpigen_write_if_lequal_op_int(ARG2_OP, 1);
+	acpigen_write_return_string(config && config->sensor_name ? config->sensor_name : "UNKNOWN");
+	acpigen_pop_len();	/* If Arg2=1 */
+
+	acpigen_pop_len();	/* If uuid */
 }
 
-static void camera_generate_dsm_sensor_type(const struct device *dev)
+/*
+ * Generate ASL DSM code for I2C device count and addresses
+ *
+ * Generated ASL:
+ * If (LEqual (Local0, ToUUID ("26257549-9271-4ca4-bb43-c4899d5a4881"))) {
+ *     ToInteger (Arg2, Local1)
+ *     If (LEqual (Local1, 1)) {
+ *         Return (i2c_dev_count)
+ *     }
+ *     If (LEqual (Local1, 2)) {
+ *         Return (sensor_address)
+ *     }
+ *     If (LEqual (Local1, 3)) {
+ *         Return (vcm_address)  // if vcm_type exists
+ *     }
+ *     If (LEqual (Local1, 3 or 4)) {
+ *         Return (rom_address)  // if rom_type exists (index depends on vcm)
+ *     }
+ * }
+ */
+static void camera_generate_dsm_i2c(const struct device *dev)
 {
 	struct drivers_intel_mipi_camera_config *config = dev->chip_info;
-	int local1_ret = 1 + (config->ssdb.vcm_type ? 1 : 0) + (config->ssdb.rom_type ? 1 : 0);
-	int next_local1 = 1;
+	int i2c_dev_count = 1 + (config->ssdb.vcm_type ? 1 : 0) + (config->ssdb.rom_type ? 1 : 0);
+	int i2c_dev_idx = 1;
 
-	/* If (LEqual (Local0, ToUUID(uuid))) */
+	/* If (LEqual (Local0, ToUUID (UUID_DSM_I2C))) */
 	acpigen_write_if();
 	acpigen_emit_byte(LEQUAL_OP);
 	acpigen_emit_byte(LOCAL0_OP);
-	acpigen_write_uuid(SENSOR_TYPE_UUID);
+	acpigen_write_uuid(UUID_DSM_I2C);
 	/* ToInteger (Arg2, Local1) */
 	acpigen_write_to_integer(ARG2_OP, LOCAL1_OP);
 
 	/* If (LEqual (Local1, 1)) */
-	acpigen_write_if_lequal_op_int(LOCAL1_OP, next_local1++);
-	acpigen_write_return_integer(local1_ret);
+	acpigen_write_if_lequal_op_int(LOCAL1_OP, i2c_dev_idx++);
+	acpigen_write_return_integer(i2c_dev_count);
 	acpigen_pop_len();	/* If Arg2=1 */
 
 	/* If (LEqual (Local1, 2)) */
-	acpigen_write_if_lequal_op_int(LOCAL1_OP, next_local1++);
+	acpigen_write_if_lequal_op_int(LOCAL1_OP, i2c_dev_idx++);
 	acpigen_write_return_integer(address_for_dev_type(dev, DEV_TYPE_SENSOR));
 	acpigen_pop_len();	/* If Arg2=2 */
 
 	if (config->ssdb.vcm_type) {
 		/* If (LEqual (Local1, 3)) */
-		acpigen_write_if_lequal_op_int(LOCAL1_OP, next_local1++);
+		acpigen_write_if_lequal_op_int(LOCAL1_OP, i2c_dev_idx++);
 		acpigen_write_return_integer(address_for_dev_type(dev, DEV_TYPE_VCM));
 		acpigen_pop_len();      /* If Arg2=3 */
 	}
 
 	if (config->ssdb.rom_type) {
 		/* If (LEqual (Local1, 3 or 4)) */
-		acpigen_write_if_lequal_op_int(LOCAL1_OP, next_local1);
+		acpigen_write_if_lequal_op_int(LOCAL1_OP, i2c_dev_idx);
 		acpigen_write_return_integer(address_for_dev_type(dev, DEV_TYPE_ROM));
 		acpigen_pop_len();      /* If Arg2=3 or 4 */
 	}
@@ -282,8 +341,8 @@ static void camera_generate_dsm(const struct device *dev)
 	/* ToBuffer (Arg0, Local0) */
 	acpigen_write_to_buffer(ARG0_OP, LOCAL0_OP);
 
-	camera_generate_dsm_sensor_name(dev);
-	camera_generate_dsm_sensor_type(dev);
+	camera_generate_dsm_sensor(dev);
+	camera_generate_dsm_i2c(dev);
 
 	/* Return (Buffer (One) { 0x0 }) */
 	acpigen_write_return_singleton_buffer(0x0);

From a64b93562d0677d9c534df6cdde542bc7146a924 Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Fri, 12 Dec 2025 09:12:20 -0600
Subject: [PATCH 2843/3886] drv/intel/mipi_camera: Add I2C V2 DSM function

Add camera_generate_dsm_i2c_v2() to support the I2C V2 DSM UUID
(5815c5c8-c47d-477b-9a8d-76173176414b) which returns I2C device
addresses in a buffer format, rather than individually. Includes
ACPI-compliant function query handling (Arg2==0) and ASL code
documentation.

This UUID is utilized by the standard Intel drivers under both Windows
and mainline Linux.

TEST=tested with rest of patch train on screebo, redrix, and others.

Change-Id: Ifd35b53b21d0d1be9e9802059c724bf544ca1a1a
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90489
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/drivers/intel/mipi_camera/camera.c | 78 ++++++++++++++++++++++++++
 1 file changed, 78 insertions(+)

diff --git a/src/drivers/intel/mipi_camera/camera.c b/src/drivers/intel/mipi_camera/camera.c
index f937e7220b..bd7b930ccc 100644
--- a/src/drivers/intel/mipi_camera/camera.c
+++ b/src/drivers/intel/mipi_camera/camera.c
@@ -19,6 +19,7 @@
 
 #define UUID_DSM_SENSOR		"822ace8f-2814-4174-a56b-5f029fe079ee"
 #define UUID_DSM_I2C		"26257549-9271-4ca4-bb43-c4899d5a4881"
+#define UUID_DSM_I2C_V2		"5815c5c8-c47d-477b-9a8d-76173176414b"
 #define DEFAULT_ENDPOINT	0
 #define DEFAULT_REMOTE_NAME	"\\_SB.PCI0.CIO2"
 #define CIO2_PCI_DEV		0x14
@@ -333,6 +334,82 @@ static void camera_generate_dsm_i2c(const struct device *dev)
 	acpigen_pop_len();      /* If uuid */
 }
 
+/*
+ * Generate ASL DSM code for I2C device count and addresses (V2)
+ *
+ * Generated ASL:
+ * If (LEqual (Local0, ToUUID ("5815c5c8-c47d-477b-9a8d-76173176414b"))) {
+ *     If (LEqual (Arg2, Zero)) {
+ *         If (LEqual (Arg1, Zero)) {
+ *             Return (Buffer (One) { 0x3 })
+ *         } Else {
+ *             Return (Buffer (One) { 0x1 })
+ *         }
+ *     }
+ *     If (LEqual (Arg2, One)) {
+ *         Return (Buffer (52) {
+ *             i2c_count, sensor_addr, [vcm_addr], [rom_addr], 0, 0, ...
+ *         })
+ *         // Buffer is 13 * 4 = 52 bytes: count + up to 12 device addresses
+ *     }
+ * }
+ */
+static void camera_generate_dsm_i2c_v2(const struct device *dev)
+{
+	struct drivers_intel_mipi_camera_config *config = dev->chip_info;
+	if (!config)
+		return;
+
+	int i2c_count = 1 + (config->ssdb.vcm_type ? 1 : 0) + (config->ssdb.rom_type ? 1 : 0);
+	int i2c_idx = 1;
+
+	/* If (LEqual (Local0, ToUUID(UUID_DSM_I2C_V2))) */
+	acpigen_write_if();
+	acpigen_emit_byte(LEQUAL_OP);
+	acpigen_emit_byte(LOCAL0_OP);
+	acpigen_write_uuid(UUID_DSM_I2C_V2);
+
+	/* If (LEqual (Arg2, Zero)) */
+	acpigen_write_if_lequal_op_int(ARG2_OP, 0);
+
+	/* If (LEqual (Arg1, Zero)) */
+	acpigen_write_if_lequal_op_int(ARG1_OP, 0);
+	/* Return (Buffer (One) { 0x3 }) */
+	acpigen_write_return_singleton_buffer(0x3);
+	/* Else */
+	acpigen_write_else();
+	/* Return (Buffer (One) { 0x1 }) */
+	acpigen_write_return_singleton_buffer(0x1);
+	acpigen_pop_len();	/* If Arg1=0 */
+
+	acpigen_pop_len();	/* If Arg2=0 */
+
+	/* If (LEqual (Arg2, One)) */
+	acpigen_write_if_lequal_op_int(ARG2_OP, 1);
+
+	/* Buffer is 13 * 4 = 52 bytes: count + up to 12 device addresses */
+	uint32_t i2c_buffer[13] = {0};
+	_Static_assert(sizeof(i2c_buffer) == 52, "i2c_buffer size must be 52 bytes");
+
+	i2c_buffer[0] = i2c_count;
+	i2c_buffer[i2c_idx++] = address_for_dev_type(dev, DEV_TYPE_SENSOR);
+
+	if (config->ssdb.vcm_type) {
+		i2c_buffer[i2c_idx++] = address_for_dev_type(dev, DEV_TYPE_VCM);
+	}
+
+	if (config->ssdb.rom_type) {
+		i2c_buffer[i2c_idx] = address_for_dev_type(dev, DEV_TYPE_ROM);
+	}
+
+	acpigen_write_return_byte_buffer((uint8_t *)i2c_buffer, sizeof(i2c_buffer));
+
+	acpigen_pop_len();	/* If Arg2=1 */
+
+	acpigen_pop_len();	/* If uuid */
+}
+
+
 static void camera_generate_dsm(const struct device *dev)
 {
 	/* Method (_DSM, 4, NotSerialized) */
@@ -343,6 +420,7 @@ static void camera_generate_dsm(const struct device *dev)
 
 	camera_generate_dsm_sensor(dev);
 	camera_generate_dsm_i2c(dev);
+	camera_generate_dsm_i2c_v2(dev);
 
 	/* Return (Buffer (One) { 0x0 }) */
 	acpigen_write_return_singleton_buffer(0x0);

From 1532eb60ee7e66140b8ae7ff4cd335f3c0c903bc Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Thu, 11 Dec 2025 21:33:08 -0600
Subject: [PATCH 2844/3886] drv/intel/mipi_camera: Add CVF Support DSM function

Add support for Computer Vision Framework Support DSM UUID with ACPI-
compliant query handling and ASL documentation. Currently we are
always returning Zero (unsupported/disabled), but support will be
added in future patches.

This UUID is utilized by the standard Intel drivers under both Windows
and mainline Linux.

TEST=tested with rest of patch train on screebo, redrix, and others.

Change-Id: I6db88285d757826fa0f3eb5aa4bb1cc4176b95b3
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90490
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/drivers/intel/mipi_camera/camera.c | 35 ++++++++++++++++++++++++++
 1 file changed, 35 insertions(+)

diff --git a/src/drivers/intel/mipi_camera/camera.c b/src/drivers/intel/mipi_camera/camera.c
index bd7b930ccc..472537c8e6 100644
--- a/src/drivers/intel/mipi_camera/camera.c
+++ b/src/drivers/intel/mipi_camera/camera.c
@@ -20,6 +20,7 @@
 #define UUID_DSM_SENSOR		"822ace8f-2814-4174-a56b-5f029fe079ee"
 #define UUID_DSM_I2C		"26257549-9271-4ca4-bb43-c4899d5a4881"
 #define UUID_DSM_I2C_V2		"5815c5c8-c47d-477b-9a8d-76173176414b"
+#define UUID_DSM_CVF		"02f55f0c-2e63-4f05-84f3-bf1980f9af79"
 #define DEFAULT_ENDPOINT	0
 #define DEFAULT_REMOTE_NAME	"\\_SB.PCI0.CIO2"
 #define CIO2_PCI_DEV		0x14
@@ -409,6 +410,39 @@ static void camera_generate_dsm_i2c_v2(const struct device *dev)
 	acpigen_pop_len();	/* If uuid */
 }
 
+/*
+ * Generate ASL DSM code for Computer Vision Framework (CVF)
+ *
+ * Generated ASL:
+ * If (LEqual (Local0, ToUUID ("02f55f0c-2e63-4f05-84f3-bf1980f9af79"))) {
+ *     If (LEqual (Arg2, Zero)) {
+ *         Return (Buffer (One) { 0x3 })
+ *     }
+ *     If (LEqual (Arg2, One)) {
+ *         Return (Zero)
+ *     }
+ * }
+ */
+static void camera_generate_dsm_cvf(const struct device *dev)
+{
+	/* If (LEqual (Local0, ToUUID (UUID_DSM_CVF))) */
+	acpigen_write_if();
+	acpigen_emit_byte(LEQUAL_OP);
+	acpigen_emit_byte(LOCAL0_OP);
+	acpigen_write_uuid(UUID_DSM_CVF);
+
+	/* If (LEqual (Arg2, Zero)) */
+	acpigen_write_if_lequal_op_int(ARG2_OP, 0);
+	acpigen_write_return_singleton_buffer(0x3);
+	acpigen_pop_len();
+
+	/* If (LEqual (Arg2, One)) */
+	acpigen_write_if_lequal_op_int(ARG2_OP, 1);
+	acpigen_write_return_integer(0);
+	acpigen_pop_len();
+
+	acpigen_pop_len();	/* If uuid */
+}
 
 static void camera_generate_dsm(const struct device *dev)
 {
@@ -421,6 +455,7 @@ static void camera_generate_dsm(const struct device *dev)
 	camera_generate_dsm_sensor(dev);
 	camera_generate_dsm_i2c(dev);
 	camera_generate_dsm_i2c_v2(dev);
+	camera_generate_dsm_cvf(dev);
 
 	/* Return (Buffer (One) { 0x0 }) */
 	acpigen_write_return_singleton_buffer(0x0);

From ae0d23240216c09b95e4b564df51d598f3e01e20 Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Mon, 15 Dec 2025 17:41:27 -0600
Subject: [PATCH 2845/3886] drivers/intel/mipi_camera: Add ACPI device type
 selection

Refactor the MIPI camera driver to support two ACPI device generation
modes via a Kconfig choice:

1. Windows/Linux mode (MIPI_ACPI_TYPE_WINDOWS_LINUX): Generates a
   single ACPI device for the camera sensor and any associated VCM or
   NVM devices on the same I2C bus. The IPU ACPI device is attached to
   the iGPU, not standalone. This is the preferred method for Windows
   and mainline Linux.

2. ChromeOS mode (MIPI_ACPI_TYPE_CHROMEOS): Generates separate ACPI
   devices for each camera component (sensor, CIO2, VCM, NVM). The IPU
   ACPI device is generated separately from the iGPU. This maintains
   compatibility with the existing ChromeOS-style setup.

The implementation uses runtime conditionals to select between the two
modes. Common helper functions are shared between modes, while device-
specific logic is conditional based on the selected ACPI type.

The default selection is MIPI_ACPI_TYPE_CHROMEOS for ChromeOS builds and
MIPI_ACPI_TYPE_WINDOWS_LINUX otherwise.

Change-Id: I0bc4894aff04d6b296011e85d790d624890da055
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90522
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
---
 src/drivers/intel/mipi_camera/Kconfig  | 28 ++++++++
 src/drivers/intel/mipi_camera/camera.c | 96 ++++++++++++++++++++------
 2 files changed, 101 insertions(+), 23 deletions(-)

diff --git a/src/drivers/intel/mipi_camera/Kconfig b/src/drivers/intel/mipi_camera/Kconfig
index 88c97bd0de..6bf307a581 100644
--- a/src/drivers/intel/mipi_camera/Kconfig
+++ b/src/drivers/intel/mipi_camera/Kconfig
@@ -8,8 +8,36 @@ config DRIVERS_INTEL_MIPI_CAMERA
 	  MIPI CSI I2C camera SSDT generator. Generates SSDB and PWDB
 	  structures which are used by the Intel kernel drivers.
 
+if DRIVERS_INTEL_MIPI_CAMERA
+
 config DRIVERS_INTEL_MIPI_SUPPORTS_PRE_PRODUCTION_SOC
 	def_bool n
 	help
 	  Use this config to provide information to IPU kernel driver
 	  if pre-production or production signed IPU FW needs to be loaded.
+
+choice
+	prompt "MIPI camera ACPI type"
+	default MIPI_ACPI_TYPE_CHROMEOS if CHROMEOS
+	default MIPI_ACPI_TYPE_WINDOWS_LINUX
+	help
+	  Select the ACPI device type to generate for the MIPI camera.
+
+config MIPI_ACPI_TYPE_WINDOWS_LINUX
+	bool "Windows / Linux"
+	help
+	  Generates a single ACPI device for the camera sensor and any
+	  associated VCM or NVM devices on the same I2C bus, instead of
+	  separate ACPI devices for each camera related device. The IPU
+	  ACPI device is attached to the iGPU, not standalone. This is
+	  the preferred method for Windows and mainline Linux.
+
+config MIPI_ACPI_TYPE_CHROMEOS
+	bool "Chrome OS"
+	help
+	  Generates separate ACPI devices for each camera related device.
+	  The IPU ACPI device is generated separately from the iGPU.
+	  This is the preferred method for ChromeOS.
+
+endchoice
+endif
diff --git a/src/drivers/intel/mipi_camera/camera.c b/src/drivers/intel/mipi_camera/camera.c
index 472537c8e6..e4365d1b36 100644
--- a/src/drivers/intel/mipi_camera/camera.c
+++ b/src/drivers/intel/mipi_camera/camera.c
@@ -513,27 +513,44 @@ static void camera_fill_ssdb_defaults(struct drivers_intel_mipi_camera_config *c
 }
 
 /*
- * Adds settings for a camera sensor device (typically at "\_SB.PCI0.I2Cx.CAMy"). The drivers
- * for Linux tends to expect the camera sensor device and any related nvram / vcm devices to be
- * separate ACPI devices, while the drivers for Windows want all of these to be grouped
- * together in the camera sensor ACPI device. This implementation tries to satisfy both,
- * though the unfortunate tradeoff is that the same I2C address for nvram and vcm is advertised
- * by multiple devices in ACPI (via "_CRS"). The Windows driver can use the "_DSM" method to
- * disambiguate the I2C resources in the camera sensor ACPI device.  Drivers for Windows
- * typically query "SSDB" for configuration information (represented as a binary blob dump of
- * struct), while Linux drivers typically consult individual parameters in "_DSD".
+ * Adds settings for a camera sensor device (typically at "\_SB.PCI0.I2Cx.CAMy").
+ *
+ * Single ACPI device mode: The drivers for Windows and Linux want the sensor and any associated
+ * VCM or NVM devices to be grouped together in the camera sensor ACPI device. The OS driver
+ * uses the "_DSM" method to disambiguate the I2C resources in the camera sensor ACPI device.
+ * Drivers typically query "SSDB" for configuration information (represented as a binary blob
+ * dump of struct).
+ *
+ * Multi ACPI device mode: The drivers for ChromeOS expect the camera sensor device and any
+ * related nvram / vcm devices to be separate ACPI devices.
  *
  * The tree of tables in "_DSD" is analogous to what's used for the "CIO2" device.  The _DSD
  * specifies a child table for the sensor's port (e.g., PRT0 for "port0"--this implementation
  * assumes a camera only has 1 port). The PRT0 table specifies a table for each endpoint
  * (though only 1 endpoint is supported by this implementation so the table only has an
  * "endpoint0" that points to a EP00 table). The EP00 table primarily describes the # of lanes
- * in "data-lines", a list of frequencies in "list-frequencies", and specifies the name of the
+ * in "data-lanes", a list of frequencies in "list-frequencies", and specifies the name of the
  * other side in "remote-endpoint" (typically "\_SB.PCI0.CIO2").
  */
 static void camera_fill_sensor(const struct device *dev)
 {
 	struct drivers_intel_mipi_camera_config *config = dev->chip_info;
+
+	camera_generate_pld(dev);
+
+	camera_fill_ssdb_defaults(config);
+
+	/* _DSM */
+	camera_generate_dsm(dev);
+
+	if (CONFIG(MIPI_ACPI_TYPE_WINDOWS_LINUX)) {
+		acpigen_write_method_serialized("SSDB", 0);
+		acpigen_write_return_byte_buffer((uint8_t *)&config->ssdb, sizeof(config->ssdb));
+		acpigen_pop_len(); /* Method */
+		return;
+	}
+
+	/* Multi-device mode: add _DSD with endpoint information */
 	struct acpi_dp *ep00 = NULL;
 	struct acpi_dp *prt0 = NULL;
 	struct acpi_dp *dsd = NULL;
@@ -543,13 +560,6 @@ static void camera_fill_sensor(const struct device *dev)
 	const char *remote_name;
 	struct device *cio2 = pcidev_on_root(CIO2_PCI_DEV, CIO2_PCI_FN);
 
-	camera_generate_pld(dev);
-
-	camera_fill_ssdb_defaults(config);
-
-	/* _DSM */
-	camera_generate_dsm(dev);
-
 	ep00 = acpi_dp_new_table("EP00");
 	acpi_dp_add_integer(ep00, "endpoint", DEFAULT_ENDPOINT);
 	acpi_dp_add_integer(ep00, "clock-lanes", 0);
@@ -1035,7 +1045,10 @@ static void write_i2c_camera_device(const struct device *dev, const char *scope)
 		acpigen_write_name_integer("_ADR", 0);
 
 	acpigen_write_name_integer("_UID", config->acpi_uid);
-	acpigen_write_name_string("_DDN", config->chip_name);
+	if (CONFIG(MIPI_ACPI_TYPE_WINDOWS_LINUX))
+		acpigen_write_name_string("_DDN", config->sensor_name);
+	else
+		acpigen_write_name_string("_DDN", config->chip_name);
 	acpigen_write_STA(acpi_device_status(dev));
 	acpigen_write_method("_DSC", 0);
 	acpigen_write_return_integer(config->max_dstate_for_probe);
@@ -1071,11 +1084,12 @@ static void write_camera_device_common(const struct device *dev)
 {
 	struct drivers_intel_mipi_camera_config *config = dev->chip_info;
 
-	/* Mark it as Camera related device */
-	if (config->device_type == INTEL_ACPI_CAMERA_CIO2 ||
-	    config->device_type == INTEL_ACPI_CAMERA_IMGU ||
-	    config->device_type == INTEL_ACPI_CAMERA_SENSOR ||
-	    config->device_type == INTEL_ACPI_CAMERA_VCM) {
+	/* Mark it as Camera related device (multi-device mode only) */
+	if (CONFIG(MIPI_ACPI_TYPE_CHROMEOS) &&
+	    (config->device_type == INTEL_ACPI_CAMERA_CIO2 ||
+	     config->device_type == INTEL_ACPI_CAMERA_IMGU ||
+	     config->device_type == INTEL_ACPI_CAMERA_SENSOR ||
+	     config->device_type == INTEL_ACPI_CAMERA_VCM)) {
 		acpigen_write_name_integer("CAMD", config->device_type);
 	}
 
@@ -1114,6 +1128,36 @@ static void camera_fill_ssdt(const struct device *dev)
 	const char *scope = NULL;
 	const struct device *pdev = dev->upstream->dev;
 
+	if (CONFIG(MIPI_ACPI_TYPE_WINDOWS_LINUX)) {
+		/* Only generate SSDT for an i2c-attached sensor device */
+		if (dev->path.type != DEVICE_PATH_I2C || config->device_type != INTEL_ACPI_CAMERA_SENSOR)
+			return;
+
+		scope = acpi_device_scope(dev);
+		if (!scope) {
+			printk(BIOS_ERR, "Failed to get scope for device %s\n", dev_path(dev));
+			return;
+		}
+
+		acpigen_write_scope(scope);
+
+		if (config->has_power_resource && pdev && pdev->enabled) {
+			add_guarded_operations(config, &config->on_seq);
+			add_guarded_operations(config, &config->off_seq);
+		}
+
+		write_i2c_camera_device(dev, scope);
+		write_camera_device_common(dev);
+
+		acpigen_pop_len(); /* Device */
+		acpigen_pop_len(); /* Scope */
+
+		printk(BIOS_INFO, "%s: %s at I2C 0x%02x\n", acpi_device_path(dev),
+		       dev->chip_ops->name, dev->path.i2c.device);
+		return;
+	}
+
+	/* Multi-device mode */
 	if (config->has_power_resource) {
 		if (!pdev || !pdev->enabled)
 			return;
@@ -1175,6 +1219,12 @@ static const char *camera_acpi_name(const struct device *dev)
 	if (config->acpi_name)
 		return config->acpi_name;
 
+	if (CONFIG(MIPI_ACPI_TYPE_WINDOWS_LINUX)) {
+		snprintf(name, sizeof(name), "CAM%1u", config->acpi_uid);
+		return name;
+	}
+
+	/* Multi-device mode */
 	switch (config->device_type) {
 	case INTEL_ACPI_CAMERA_CIO2:
 		return "CIO2";

From 0f1ae4ae5f15a6b322448f39b93768b62a9bbfe0 Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Thu, 4 Dec 2025 19:16:08 -0600
Subject: [PATCH 2846/3886] drivers/gfx/generic: Add support for non-VGA
 devices

Add support for non-VGA devices (e.g., Intel IPU) in the generic
graphics driver by:

- Adding DOD_NONVGA bit definition per ACPI spec 6.5 table B-2
- Adding non_vga_device boolean field to device config structure
- Increasing device array size from 6 to 7 to accommodate IPU
- Updating ACPI _DOD generation to use DOD_NONVGA flag for non-VGA
  devices instead of DOD_FW_DETECT

This allows proper ACPI enumeration of non-VGA devices whose power
is related to the VGA device, such as Intel Image Processing Units.

TEST=tested with rest of patch train on screebo, redrix, and others.

Change-Id: I60472e1232959fe407f63b4b8e6bffba995e7f79
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90516
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
---
 src/drivers/gfx/generic/chip.h    | 7 +++++--
 src/drivers/gfx/generic/generic.c | 5 ++++-
 2 files changed, 9 insertions(+), 3 deletions(-)

diff --git a/src/drivers/gfx/generic/chip.h b/src/drivers/gfx/generic/chip.h
index 2710367a3c..3c8a776370 100644
--- a/src/drivers/gfx/generic/chip.h
+++ b/src/drivers/gfx/generic/chip.h
@@ -8,6 +8,7 @@
 
 /* ACPI spec 6.5 table B-2, Display Output Device */
 #define DOD_FW_DETECT	BIT(16)	/* Platform boot firmware can detect the device. */
+#define DOD_NONVGA	BIT(17) /* Non-VGA device whose power is related to the VGA device */
 #define DOD_DID_STD	BIT(31)	/* DID Scheme: Use standard bit-field definitions */
 enum display_type {
 	other	= 0,
@@ -53,6 +54,8 @@ struct drivers_gfx_generic_device_config {
 	/* Physical location of connection point */
 	bool use_pld;
 	struct acpi_pld pld;
+	/* Non-VGA device (e.g. Intel IPU) */
+	bool non_vga_device;
 };
 
 /* Config for an ACPI video device defined in Appendix A of the ACPI spec */
@@ -65,8 +68,8 @@ struct drivers_gfx_generic_config {
 	/* The number of output devices defined */
 	int device_count;
 	/* Config for output devices */
-	/* 1 DDIA + 1 DDIB + max 4 TCP = up to 6 GFX devices */
-	struct drivers_gfx_generic_device_config device[6];
+	/* 1 DDIA + 1 DDIB + max 4 TCP + IPU = up to 7 (6 GFX + 1 non-GFX) devices */
+	struct drivers_gfx_generic_device_config device[7];
 };
 
 #endif /* __DRIVERS_GFX_GENERIC_CHIP_H__ */
diff --git a/src/drivers/gfx/generic/generic.c b/src/drivers/gfx/generic/generic.c
index 01129313a0..51384f6e27 100644
--- a/src/drivers/gfx/generic/generic.c
+++ b/src/drivers/gfx/generic/generic.c
@@ -120,7 +120,10 @@ static void gfx_fill_ssdt_generator(const struct device *dev)
 			/* Though not strictly necessary, set the display index and
 			   port attachment to the device index, to ensure uniqueness */
 			config->device[i].addr = (config->device[i].type << 8) | (i << 4) | (i);
-		acpigen_write_dword(DOD_DID_STD | DOD_FW_DETECT | config->device[i].addr);
+		if (config->device[i].non_vga_device)
+			acpigen_write_dword(DOD_DID_STD | DOD_NONVGA | config->device[i].addr);
+		else
+			acpigen_write_dword(DOD_DID_STD | DOD_FW_DETECT | config->device[i].addr);
 	}
 	acpigen_pop_len(); /* End Package. */
 	acpigen_pop_len(); /* End Method. */

From 5001b07f9c9a994bb0fb258c77c9ea968b5fcd9a Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Mon, 15 Dec 2025 15:17:23 -0600
Subject: [PATCH 2847/3886] drivers/intel/mipi_camera: Add validation and
 remove unused defaults

Add validation checks in camera_enable() for required parameters:
- ssdb.lanes_used
- ssdb.platform
- rom_address (when rom_type is set)
- vcm_address (when vcm_type is set)

Remove default values for ssdb.platform and ssdb.lanes_used from
camera_fill_ssdb_defaults() since these parameters are now required
and validated. All boards in the tree explicitly set these values
in their devicetree configurations, so the defaults were never used.

Also remove the unused cio2 and cio2_config variables that were only
used for the lanes_used default logic.

Change-Id: Idcb84c25b94ed9259698aafba201cc4f4e0f1af7
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90517
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
---
 src/drivers/intel/mipi_camera/camera.c | 54 ++++++++++++++------------
 1 file changed, 30 insertions(+), 24 deletions(-)

diff --git a/src/drivers/intel/mipi_camera/camera.c b/src/drivers/intel/mipi_camera/camera.c
index e4365d1b36..bab652fccb 100644
--- a/src/drivers/intel/mipi_camera/camera.c
+++ b/src/drivers/intel/mipi_camera/camera.c
@@ -465,9 +465,6 @@ static void camera_generate_dsm(const struct device *dev)
 
 static void camera_fill_ssdb_defaults(struct drivers_intel_mipi_camera_config *config)
 {
-	struct device *cio2 = pcidev_on_root(CIO2_PCI_DEV, CIO2_PCI_FN);
-	struct drivers_intel_mipi_camera_config *cio2_config;
-
 	config->ssdb.version = 1;
 
 	if (!config->ssdb.sensor_card_sku.card_type)
@@ -478,9 +475,6 @@ static void camera_fill_ssdb_defaults(struct drivers_intel_mipi_camera_config *c
 	if (!config->ssdb.bdf_value)
 		config->ssdb.bdf_value = PCI_DEVFN(CIO2_PCI_DEV, CIO2_PCI_FN);
 
-	if (!config->ssdb.platform)
-		config->ssdb.platform = PLAT_SKC;
-
 	if (!config->ssdb.flash_support)
 		config->ssdb.flash_support = FLASH_DISABLE;
 
@@ -492,24 +486,6 @@ static void camera_fill_ssdb_defaults(struct drivers_intel_mipi_camera_config *c
 
 	if (!config->ssdb.mclk_speed)
 		config->ssdb.mclk_speed = CLK_FREQ_19_2MHZ;
-
-	if (!config->ssdb.lanes_used) {
-		cio2_config = cio2 ? cio2->chip_info : NULL;
-
-		if (!cio2_config) {
-			printk(BIOS_ERR, "Failed to get CIO2 config\n");
-		} else if (cio2_config->device_type != INTEL_ACPI_CAMERA_CIO2) {
-			printk(BIOS_ERR, "Device type isn't CIO2: %u\n",
-			       (u32)cio2_config->device_type);
-		} else if (config->ssdb.link_used >= cio2_config->cio2_num_ports) {
-			printk(BIOS_ERR, "%u exceeds CIO2's %u links\n",
-			       (u32)config->ssdb.link_used,
-			       (u32)cio2_config->cio2_num_ports);
-		} else {
-			config->ssdb.lanes_used =
-				cio2_config->cio2_lanes_used[config->ssdb.link_used];
-		}
-	}
 }
 
 /*
@@ -1266,6 +1242,36 @@ static struct device_operations camera_ops = {
 
 static void camera_enable(struct device *dev)
 {
+	//Validate Camera Parameters
+	struct drivers_intel_mipi_camera_config *config = dev->chip_info;
+	bool params_error = false;
+
+	if (!config->ssdb.lanes_used) {
+		printk(BIOS_ERR, "MIPI camera: SSDB lanes_used not set\n");
+		params_error = true;
+	}
+
+	if (!config->ssdb.platform) {
+		printk(BIOS_ERR, "MIPI camera: SSDB platform not set\n");
+		params_error = true;
+	}
+
+	if (config->ssdb.rom_type && !config->rom_address) {
+		printk(BIOS_ERR, "MIPI camera: ROM address not set\n");
+		params_error = true;
+	}
+
+	if (config->ssdb.vcm_type && !config->vcm_address) {
+		printk(BIOS_ERR, "MIPI camera: VCM address not set\n");
+		params_error = true;
+	}
+
+	if (params_error) {
+		printk(BIOS_ERR, "MIPI camera: Parameters missing, ACPI device(s) will not be created.\n");
+		printk(BIOS_ERR, "MIPI camera: Please fix your devicetree configuration.\n");
+		return;
+	}
+
 	dev->ops = &camera_ops;
 }
 

From 53350d5c8d5e2a4e737ea77053b76ce375e8011c Mon Sep 17 00:00:00 2001
From: Maximilian Brune <maximilian.brune@9elements.com>
Date: Fri, 12 Dec 2025 01:06:45 +0100
Subject: [PATCH 2848/3886] include/acpi/acpi_apei.h: Add internal acpi_head_t
 struct

Each error source descriptor basically has these values at the
beginning. The error source descriptors are added in the follow up
patches.

Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: Ic6873cb8cf7373435be3ce26382aa8ae37cd5938
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90481
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
---
 src/include/acpi/acpi_apei.h | 11 +++++++++++
 1 file changed, 11 insertions(+)

diff --git a/src/include/acpi/acpi_apei.h b/src/include/acpi/acpi_apei.h
index 3885994c25..81e574601b 100644
--- a/src/include/acpi/acpi_apei.h
+++ b/src/include/acpi/acpi_apei.h
@@ -91,6 +91,17 @@ typedef struct ghes_record {
 	u32 err_sts_blk_len;
 } __packed ghes_record_t;
 
+// internal struct only. It is common between all Error Source Descriptors.
+struct __packed apei_esd_header {
+	u16 type;
+	u16 source_id;
+	u16 reserved;
+	u8 flags;
+	u8 enabled;
+	u32 prealloc_record_count;
+	u32 max_sections_per_record;
+};
+
 /* BERT (Boot Error Record Table) */
 typedef struct acpi_bert {
 	acpi_header_t header;

From 5251284e39263f9f0e22bc23549f360ac0de1520 Mon Sep 17 00:00:00 2001
From: Maximilian Brune <maximilian.brune@9elements.com>
Date: Thu, 11 Dec 2025 23:10:38 +0100
Subject: [PATCH 2849/3886] include/acpi/acpi_apei.h: Add PCIe APEI structs

Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: Ib1da20c03026437a24df76218c2b78fc2d4093a7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90471
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
---
 src/include/acpi/acpi_apei.h | 49 ++++++++++++++++++++++++++++++++++++
 1 file changed, 49 insertions(+)

diff --git a/src/include/acpi/acpi_apei.h b/src/include/acpi/acpi_apei.h
index 81e574601b..61bade1c7b 100644
--- a/src/include/acpi/acpi_apei.h
+++ b/src/include/acpi/acpi_apei.h
@@ -102,6 +102,55 @@ struct __packed apei_esd_header {
 	u32 max_sections_per_record;
 };
 
+struct __packed apei_ia32_pci_root_port_aer {
+	struct apei_esd_header esd;
+	u32 bus;
+	u16 device;
+	u16 function;
+	u16 device_control;
+	u16 reserved2;
+	u32 uncorrectable_error_mask;
+	u32 uncorrectable_error_severity;
+	u32 correctable_error_mask;
+	u32 advanced_error_capabilities;
+	u32 root_error_command;
+};
+_Static_assert(sizeof(struct apei_ia32_pci_root_port_aer) == 48,
+		"wrong acpi_ia32_pci_device_aer size");
+
+struct __packed apei_ia32_pci_device_aer {
+	struct apei_esd_header esd;
+	u32 bus;
+	u16 device;
+	u16 function;
+	u16 device_control;
+	u16 reserved2;
+	u32 uncorrectable_error_mask;
+	u32 uncorrectable_error_severity;
+	u32 correctable_error_mask;
+	u32 advanced_error_capabilities;
+};
+_Static_assert(sizeof(struct apei_ia32_pci_device_aer) == 44,
+		"wrong acpi_ia32_pci_device_aer size");
+
+struct __packed apei_ia32_pci_bridge_aer {
+	struct apei_esd_header esd;
+	u32 bus;
+	u16 device;
+	u16 function;
+	u16 device_control;
+	u16 reserved2;
+	u32 uncorrectable_error_mask;
+	u32 uncorrectable_error_severity;
+	u32 correctable_error_mask;
+	u32 advanced_error_capabilities;
+	u32 secondary_uncorrectable_error_mask;
+	u32 secondary_uncorrectable_error_severity;
+	u32 secondary_advanced_capabilities;
+};
+_Static_assert(sizeof(struct apei_ia32_pci_bridge_aer) == 56,
+		"wrong acpi_ia32_pci_bridge_aer size");
+
 /* BERT (Boot Error Record Table) */
 typedef struct acpi_bert {
 	acpi_header_t header;

From 7a41dc416beab1d5ce8af0d8fccb362541e4ecba Mon Sep 17 00:00:00 2001
From: Maximilian Brune <maximilian.brune@9elements.com>
Date: Thu, 11 Dec 2025 23:20:39 +0100
Subject: [PATCH 2850/3886] include/acpi/acpi_apei.h: Add NMI APEI struct

Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: I2f9d9f91d6f322da79ce86c98d1e458d8193b9ac
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90472
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
---
 src/include/acpi/acpi_apei.h | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/src/include/acpi/acpi_apei.h b/src/include/acpi/acpi_apei.h
index 61bade1c7b..08a65552f2 100644
--- a/src/include/acpi/acpi_apei.h
+++ b/src/include/acpi/acpi_apei.h
@@ -102,6 +102,13 @@ struct __packed apei_esd_header {
 	u32 max_sections_per_record;
 };
 
+struct __packed apei_ia32_nmi {
+	struct apei_esd_header esd;
+	u32 max_raw_data_length;
+};
+_Static_assert(sizeof(struct apei_ia32_nmi) == 20,
+		"wrong acpi_ia32_nmi size");
+
 struct __packed apei_ia32_pci_root_port_aer {
 	struct apei_esd_header esd;
 	u32 bus;

From b689671e79d642d9c36c7aa2732acabbbaaf81c3 Mon Sep 17 00:00:00 2001
From: Maximilian Brune <maximilian.brune@9elements.com>
Date: Thu, 11 Dec 2025 23:22:33 +0100
Subject: [PATCH 2851/3886] include/acpi/acpi_apei.h: Add MCE APEI structs

Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: I31527048dd5ac12f05f299e3226d8fbde502f626
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90473
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/include/acpi/acpi_apei.h | 45 ++++++++++++++++++++++++++++++++++++
 1 file changed, 45 insertions(+)

diff --git a/src/include/acpi/acpi_apei.h b/src/include/acpi/acpi_apei.h
index 08a65552f2..2be8108d27 100644
--- a/src/include/acpi/acpi_apei.h
+++ b/src/include/acpi/acpi_apei.h
@@ -102,6 +102,51 @@ struct __packed apei_esd_header {
 	u32 max_sections_per_record;
 };
 
+struct __packed apei_ia32_mce_bank {
+	u8 bank_number;
+	u8 clear_status_on_initialization;
+	u8 status_data_format;
+	u8 reserved;
+	u32 control_reg_msr_addr;
+	u64 control_init_data;
+	u32 status_reg_msr_addr;
+	u32 address_reg_msr_addr;
+	u32 misc_reg_msr_addr;
+};
+_Static_assert(sizeof(struct apei_ia32_mce_bank) == 28,
+		"wrong acpi_ia32_mce_bank size");
+
+struct __packed apei_ia32_mce {
+	struct apei_esd_header esd;
+	u64 global_capability_init_data;
+	u64 global_control_init_data;
+	u8 number_of_hardware_banks;
+	u8 reserved[7];
+	struct apei_ia32_mce_bank banks[];
+};
+_Static_assert(sizeof(struct apei_ia32_mce) == 40,
+		"wrong acpi_ia32_mce size");
+
+struct __packed apei_ia32_corrected_mce {
+	struct apei_esd_header esd;
+	acpi_hest_hen_t notify;
+	u8 number_of_hardware_banks;
+	u8 reserved[3];
+	struct apei_ia32_mce_bank banks[];
+};
+_Static_assert(sizeof(struct apei_ia32_corrected_mce) == 48,
+		"wrong acpi_ia32_corrected_mce size");
+
+struct __packed apei_ia32_deferred_mce {
+	struct apei_esd_header esd;
+	acpi_hest_hen_t notify;
+	u8 number_of_hardware_banks;
+	u8 reserved[3];
+	struct apei_ia32_mce_bank banks[];
+};
+_Static_assert(sizeof(struct apei_ia32_deferred_mce) == 48,
+		"wrong acpi_ia32_deferred_mce size");
+
 struct __packed apei_ia32_nmi {
 	struct apei_esd_header esd;
 	u32 max_raw_data_length;

From 793c15a866b6634318b7574995eb11338d2261b7 Mon Sep 17 00:00:00 2001
From: Appukuttan V K <appukuttan.vk@intel.com>
Date: Thu, 4 Dec 2025 12:03:51 +0530
Subject: [PATCH 2852/3886] mb/google/ocelot: Fix Gen4 SSD power sequencing

Move Gen4 SSD power enable (GPP_H18) from ramstage GPIO table to
pre-memory configuration to ensure proper delay between power enable
and reset signals. This is required to fix PCIe speed downgrade or
link failure issues seen with some NVMe parts when a non-serial image
is used for boot.

Changes:
 - Enable GPP_H18 (GEN4_SSD_PWREN) in pre_mem_gen4_ssd_pwr_pads
 - Remove duplicate GPP_H18 configuration from gen4_ssd_pads
 - Remove GPP_H18 from ramstage gpio_table

BUG=None
TEST=Build Ocelot and check PCIe link speed over multiple cold boot
iterations and ensure that the link is trained to maximum capability.

Test Steps:
 - Cold reboot the system: ectool reboot_ec
 - Check the current link speed and max link speed:
    cat /sys/bus/pci/devices/0000:00\:1c.0/current_link_speed
	16.0 GT/s PCIe
    cat /sys/bus/pci/devices/0000:00\:1c.0/max_link_speed
	16.0 GT/s PCIe
 - Repeat these steps for multiple iterations and ensure that current
   link speed is equivalent to max link speed.

Change-Id: I31a0a92c168e9c851246359e69faabd786248b5c
Signed-off-by: Appukuttan V K <appukuttan.vk@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90363
Reviewed-by: P, Usha <usha.p@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 .../google/ocelot/variants/ocelot/fw_config.c  | 18 ++++++++++++++----
 .../google/ocelot/variants/ocelot/gpio.c       |  2 --
 .../google/ocelot/variants/ojal/fw_config.c    | 17 +++++++++++++----
 .../google/ocelot/variants/ojal/gpio.c         |  2 --
 4 files changed, 27 insertions(+), 12 deletions(-)

diff --git a/src/mainboard/google/ocelot/variants/ocelot/fw_config.c b/src/mainboard/google/ocelot/variants/ocelot/fw_config.c
index e89c59482f..818be9b9aa 100644
--- a/src/mainboard/google/ocelot/variants/ocelot/fw_config.c
+++ b/src/mainboard/google/ocelot/variants/ocelot/fw_config.c
@@ -190,14 +190,17 @@ static const struct pad_config wwan_disable_pads[] = {
 };
 
 /* Gen4 NVME: at the top M.2 slot */
-static const struct pad_config pre_mem_gen4_ssd_pwr_pads[] = {
+static const struct pad_config pre_mem_gen4_ssd_pwr_seq1_pads[] = {
 	/* GPP_H18:     GEN4_SSD_PWREN */
 	PAD_CFG_GPO(GPP_H18, 0, PLTRST),
 };
 
-static const struct pad_config gen4_ssd_pads[] = {
+static const struct pad_config pre_mem_gen4_ssd_pwr_seq2_pads[] = {
 	/* GPP_H18:     GEN4_SSD_PWREN */
 	PAD_CFG_GPO(GPP_H18, 1, PLTRST),
+};
+
+static const struct pad_config gen4_ssd_pads[] = {
 	/* GPP_A08:     M2_GEN4_SSD_RESET_N */
 	PAD_CFG_GPO(GPP_A08, 1, PLTRST),
 };
@@ -471,9 +474,9 @@ void fw_config_configure_pre_mem_gpio(void)
 		GPIO_CONFIGURE_PADS(pre_mem_wwan_pwr_seq1_pads);
 
 	if (fw_config_probe(FW_CONFIG(STORAGE, STORAGE_NVME_GEN4))) {
-		GPIO_CONFIGURE_PADS(pre_mem_gen4_ssd_pwr_pads);
+		GPIO_CONFIGURE_PADS(pre_mem_gen4_ssd_pwr_seq1_pads);
 	} else if (fw_config_probe(FW_CONFIG(STORAGE, STORAGE_UNKNOWN))) {
-		GPIO_CONFIGURE_PADS(pre_mem_gen4_ssd_pwr_pads);
+		GPIO_CONFIGURE_PADS(pre_mem_gen4_ssd_pwr_seq1_pads);
 	}
 
 	/*
@@ -492,6 +495,13 @@ void fw_config_configure_pre_mem_gpio(void)
 	if (fw_config_probe(FW_CONFIG(FP, FP_PRESENT)))
 		GPIO_CONFIGURE_PADS(pre_mem_fp_enable_pads);
 
+	if (fw_config_probe(FW_CONFIG(STORAGE, STORAGE_NVME_GEN4))) {
+		GPIO_CONFIGURE_PADS(pre_mem_gen4_ssd_pwr_seq2_pads);
+	} else if (fw_config_probe(FW_CONFIG(STORAGE, STORAGE_UNKNOWN))) {
+		GPIO_CONFIGURE_PADS(pre_mem_gen4_ssd_pwr_seq2_pads);
+	}
+
+
 }
 
 void fw_config_gpio_padbased_override(struct pad_config *padbased_table)
diff --git a/src/mainboard/google/ocelot/variants/ocelot/gpio.c b/src/mainboard/google/ocelot/variants/ocelot/gpio.c
index 9166668efb..658896c0f0 100644
--- a/src/mainboard/google/ocelot/variants/ocelot/gpio.c
+++ b/src/mainboard/google/ocelot/variants/ocelot/gpio.c
@@ -288,8 +288,6 @@ static const struct pad_config gpio_table[] = {
 	PAD_NC(GPP_H15, NONE),
 	/* GPP_H17:     MIC MUTE LED */
 	PAD_CFG_NF(GPP_H17, NONE, DEEP, NF1),
-	/* GPP_H18:     GEN4_SSD_PWREN */
-	PAD_CFG_GPO(GPP_H18, 1, DEEP),
 	/* GPP_H19:     I3C0_SDA_HDR */
 	PAD_CFG_NF(GPP_H19, NONE, DEEP, NF2),
 	/* GPP_H20:     I3C0_SCL_HDR */
diff --git a/src/mainboard/google/ocelot/variants/ojal/fw_config.c b/src/mainboard/google/ocelot/variants/ojal/fw_config.c
index 709723709f..39762a967c 100644
--- a/src/mainboard/google/ocelot/variants/ojal/fw_config.c
+++ b/src/mainboard/google/ocelot/variants/ojal/fw_config.c
@@ -79,14 +79,17 @@ static const struct pad_config audio_disable_pads[] = {
 	PAD_NC(GPP_S07, NONE),
 };
 
-static const struct pad_config pre_mem_gen4_ssd_pwr_pads[] = {
+static const struct pad_config pre_mem_gen4_ssd_pwr_seq1_pads[] = {
 	/* GPP_H18:     GEN4_SSD_PWREN */
 	PAD_CFG_GPO(GPP_H18, 0, PLTRST),
 };
 
-static const struct pad_config gen4_ssd_pads[] = {
+static const struct pad_config pre_mem_gen4_ssd_pwr_seq2_pads[] = {
 	/* GPP_H18:     GEN4_SSD_PWREN */
 	PAD_CFG_GPO(GPP_H18, 1, PLTRST),
+};
+
+static const struct pad_config gen4_ssd_pads[] = {
 	/* GPP_A08:     M2_GEN4_SSD_RESET_N */
 	PAD_CFG_GPO(GPP_A08, 1, PLTRST),
 };
@@ -208,13 +211,19 @@ void fw_config_configure_pre_mem_gpio(void)
 	}
 
 	if (fw_config_probe(FW_CONFIG(STORAGE, STORAGE_NVME_GEN4))) {
-		GPIO_CONFIGURE_PADS(pre_mem_gen4_ssd_pwr_pads);
+		GPIO_CONFIGURE_PADS(pre_mem_gen4_ssd_pwr_seq1_pads);
 	} else if (fw_config_probe(FW_CONFIG(STORAGE, STORAGE_UNKNOWN))) {
-		GPIO_CONFIGURE_PADS(pre_mem_gen4_ssd_pwr_pads);
+		GPIO_CONFIGURE_PADS(pre_mem_gen4_ssd_pwr_seq1_pads);
 	}
 
 	if (fw_config_probe(FW_CONFIG(FP, FP_PRESENT)))
 		GPIO_CONFIGURE_PADS(pre_mem_fp_enable_pads);
+
+	if (fw_config_probe(FW_CONFIG(STORAGE, STORAGE_NVME_GEN4))) {
+		GPIO_CONFIGURE_PADS(pre_mem_gen4_ssd_pwr_seq2_pads);
+	} else if (fw_config_probe(FW_CONFIG(STORAGE, STORAGE_UNKNOWN))) {
+		GPIO_CONFIGURE_PADS(pre_mem_gen4_ssd_pwr_seq2_pads);
+	}
 }
 
 void fw_config_gpio_padbased_override(struct pad_config *padbased_table)
diff --git a/src/mainboard/google/ocelot/variants/ojal/gpio.c b/src/mainboard/google/ocelot/variants/ojal/gpio.c
index 8c9686ea2d..acbb9199cf 100644
--- a/src/mainboard/google/ocelot/variants/ojal/gpio.c
+++ b/src/mainboard/google/ocelot/variants/ojal/gpio.c
@@ -283,8 +283,6 @@ static const struct pad_config gpio_table[] = {
 	PAD_NC(GPP_H15, NONE),
 	/* GPP_H17:     MIC MUTE LED */
 	PAD_CFG_NF(GPP_H17, NONE, DEEP, NF1),
-	/* GPP_H18:     GEN4_SSD_PWREN */
-	PAD_CFG_GPO(GPP_H18, 1, DEEP),
 	/* GPP_H19:     I3C0_SDA_HDR */
 	PAD_CFG_NF(GPP_H19, NONE, DEEP, NF2),
 	/* GPP_H20:     I3C0_SCL_HDR */

From a225eefd4cfcd9ae27d3d36c28e880fcd260b523 Mon Sep 17 00:00:00 2001
From: Alicja Michalska <alicja.michalska@9elements.com>
Date: Fri, 12 Sep 2025 17:40:33 +0200
Subject: [PATCH 2853/3886] drivers/spi: Add Macronix MX77U51250F chip id

Change-Id: I7526c2bad1ee1f2c532ffeb182298797d00de40b
Signed-off-by: Alicja Michalska <alicja.michalska@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89157
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/drivers/spi/macronix.c | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/src/drivers/spi/macronix.c b/src/drivers/spi/macronix.c
index cc834d9ee9..1225bcdeb9 100644
--- a/src/drivers/spi/macronix.c
+++ b/src/drivers/spi/macronix.c
@@ -143,6 +143,11 @@ static const struct spi_flash_part_id flash_table[] = {
 		.id[0] = 0x7539,
 		.nr_sectors_shift = 13,
 	},
+	{
+		/* MX77U51250F */
+		.id[0] = 0x753a,
+		.nr_sectors_shift = 14,
+	},
 };
 
 const struct spi_flash_vendor_info spi_flash_macronix_vi = {

From c4ee22e2675b2a980f7ebb1924fd13d60b967cab Mon Sep 17 00:00:00 2001
From: Kapil Porwal <kapilporwal@google.com>
Date: Wed, 17 Dec 2025 18:44:33 +0530
Subject: [PATCH 2854/3886] Reapply "mb/google/bluey: Implement EC-based
 off-mode detection"

This reverts commit b67725d3f51c141b9ee3c4ad9c16cafd38a54e44.

Reason: Warm reset issue is fixed in new QC blobs.

Change-Id: Iab1e0b7085f5d116704c54da4d286bb41b502853
Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90542
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/google/bluey/charging.c | 16 ----------------
 src/mainboard/google/bluey/romstage.c | 26 +++++++++++++++++++++++++-
 2 files changed, 25 insertions(+), 17 deletions(-)

diff --git a/src/mainboard/google/bluey/charging.c b/src/mainboard/google/bluey/charging.c
index 56deedcdb9..bbb849d438 100644
--- a/src/mainboard/google/bluey/charging.c
+++ b/src/mainboard/google/bluey/charging.c
@@ -43,19 +43,3 @@ void disable_slow_battery_charging(void)
 	spmi_write8(SMB1_CHGR_CHRG_EN_CMD, CHRG_DISABLE);
 	spmi_write8(SMB2_CHGR_CHRG_EN_CMD, CHRG_DISABLE);
 }
-
-/*
- * is_off_mode - Check if the system is booting due to an off-mode power event.
- *
- * This function provides the board-level policy wrapper for detecting if the
- * system power-on was triggered by an external charging event (e.g., cable
- * insertion). This is typically used to enter LB_BOOT_MODE_OFFMODE_CHARGING.
- *
- * @return true if the system was triggered by a specific off-mode reason
- * (e.g., charging cable insertion).
- * @return false otherwise.
- */
-bool is_off_mode(void)
-{
-	return is_pon_on_ac();
-}
diff --git a/src/mainboard/google/bluey/romstage.c b/src/mainboard/google/bluey/romstage.c
index c2cbf5b7c4..657c7ad177 100644
--- a/src/mainboard/google/bluey/romstage.c
+++ b/src/mainboard/google/bluey/romstage.c
@@ -14,6 +14,31 @@
 
 static enum boot_mode_t boot_mode = LB_BOOT_MODE_NORMAL;
 
+/*
+ * is_off_mode - Check if the system is booting due to an off-mode power event.
+ *
+ * This function provides the board-level policy wrapper for detecting if the
+ * system power-on was triggered by an external charging event (e.g., cable
+ * insertion). This is typically used to enter LB_BOOT_MODE_OFFMODE_CHARGING.
+ *
+ * @return true if the system was triggered by a specific off-mode reason
+ * (e.g., charging cable insertion).
+ * @return false otherwise.
+ */
+bool is_off_mode(void)
+{
+	const uint64_t manual_pwron_event_mask =
+		(EC_HOST_EVENT_MASK(EC_HOST_EVENT_POWER_BUTTON) |
+		EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN));
+	uint64_t ec_events = google_chromeec_get_events_b();
+
+	if (!(ec_events & manual_pwron_event_mask) &&
+		(ec_events & EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_CONNECTED)))
+		return true;
+
+	return false;
+}
+
 static void set_boot_mode(void)
 {
 	if (!CONFIG(EC_GOOGLE_CHROMEEC))
@@ -35,7 +60,6 @@ void platform_romstage_main(void)
 	/* QCLib: DDR init & train */
 	qclib_load_and_run();
 
-	/* Underlying PMIC registers are accessible only at this point */
 	set_boot_mode();
 
 	aop_fw_load_reset();

From ddc1b51b432eaaef67d58b95abb29364caf19fb3 Mon Sep 17 00:00:00 2001
From: Kapil Porwal <kapilporwal@google.com>
Date: Mon, 15 Dec 2025 18:47:25 +0530
Subject: [PATCH 2855/3886] mb/google/bluey: Enable PD negotiation in charging
 modes

Implement the qclib_mainboard_override hook to enable Power
Delivery negotiation when the system boots into off-mode charging
or low battery mode. This ensures proper charging levels are
negotiated early in the boot process.

BUG=b:457566143
TEST=Verify different boot modes on Google/Quenbi.
TEST=Verify that PD negotiation is skipped in normal mode.

Change-Id: I6c4b861862d739b002c4043ade21328e02186bbd
Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90513
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/google/bluey/romstage.c | 20 ++++++++++++++++----
 1 file changed, 16 insertions(+), 4 deletions(-)

diff --git a/src/mainboard/google/bluey/romstage.c b/src/mainboard/google/bluey/romstage.c
index 657c7ad177..63136a91f1 100644
--- a/src/mainboard/google/bluey/romstage.c
+++ b/src/mainboard/google/bluey/romstage.c
@@ -39,15 +39,27 @@ bool is_off_mode(void)
 	return false;
 }
 
-static void set_boot_mode(void)
+static enum boot_mode_t set_boot_mode(void)
 {
 	if (!CONFIG(EC_GOOGLE_CHROMEEC))
-		return;
+		return boot_mode;
 
+	enum boot_mode_t boot_mode_new = LB_BOOT_MODE_NORMAL;
 	if (is_off_mode())
-		boot_mode = LB_BOOT_MODE_OFFMODE_CHARGING;
+		boot_mode_new = LB_BOOT_MODE_OFFMODE_CHARGING;
 	else if (google_chromeec_is_below_critical_threshold())
-		boot_mode = LB_BOOT_MODE_LOW_BATTERY;
+		boot_mode_new = LB_BOOT_MODE_LOW_BATTERY;
+	boot_mode = boot_mode_new;
+	return boot_mode_new;
+}
+
+int qclib_mainboard_override(struct qclib_cb_if_table *table)
+{
+	if (set_boot_mode() != LB_BOOT_MODE_NORMAL)
+		table->global_attributes |= QCLIB_GA_ENABLE_PD_NEGOTIATION;
+	else
+		table->global_attributes &= ~QCLIB_GA_ENABLE_PD_NEGOTIATION;
+	return 0;
 }
 
 void platform_romstage_main(void)

From cfb0d8a144a344538caeb9ab2021256bfe7948ba Mon Sep 17 00:00:00 2001
From: Kapil Porwal <kapilporwal@google.com>
Date: Wed, 17 Dec 2025 12:28:34 +0530
Subject: [PATCH 2856/3886] mb/google/bluey: Enable PD negotiation when battery
 is missing

Update the qclib_mainboard_override hook to enable Power Delivery
negotiation if no battery is detected, even in normal boot mode.
This allows the system to negotiate higher power levels when
running solely on AC power.

BUG=b:457566143
TEST=Verify different boot modes on Google/Quenbi.

Change-Id: If1660e4c50575eb4b6d5af606c35accdb4c67982
Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90539
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
---
 src/mainboard/google/bluey/romstage.c | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/src/mainboard/google/bluey/romstage.c b/src/mainboard/google/bluey/romstage.c
index 63136a91f1..3c5b307fd8 100644
--- a/src/mainboard/google/bluey/romstage.c
+++ b/src/mainboard/google/bluey/romstage.c
@@ -55,7 +55,10 @@ static enum boot_mode_t set_boot_mode(void)
 
 int qclib_mainboard_override(struct qclib_cb_if_table *table)
 {
-	if (set_boot_mode() != LB_BOOT_MODE_NORMAL)
+	if (!CONFIG(EC_GOOGLE_CHROMEEC))
+		return 0;
+
+	if ((set_boot_mode() != LB_BOOT_MODE_NORMAL) || !google_chromeec_is_battery_present())
 		table->global_attributes |= QCLIB_GA_ENABLE_PD_NEGOTIATION;
 	else
 		table->global_attributes &= ~QCLIB_GA_ENABLE_PD_NEGOTIATION;

From de87ea0efad719a438b8ebed3d2e18ba3d12e884 Mon Sep 17 00:00:00 2001
From: Kapil Porwal <kapilporwal@google.com>
Date: Tue, 16 Dec 2025 00:41:54 +0530
Subject: [PATCH 2857/3886] mb/google/bluey: Add parallel charging
 infrastructure

Add support for parallel charging by configuring PMC8380F GPIO07
and GPIO09. These GPIOs are configured as outputs with inverted
logic. A new Kconfig option MAINBOARD_SUPPORTS_PARALLEL_CHARGING
is introduced to allow variants to opt-in to this configuration.

BUG=b:468120472
TEST=Build Google/Quartz.

Change-Id: I0126d987650c660e305f704708c09356908633e4
Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90514
Reviewed-by: Pranava Y N <pranavayn@google.com>
Reviewed-by: Jayvik Desai <jayvik@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/google/bluey/Kconfig     |  6 ++++++
 src/mainboard/google/bluey/board.h     |  1 +
 src/mainboard/google/bluey/charging.c  | 29 ++++++++++++++++++++++++++
 src/mainboard/google/bluey/mainboard.c |  2 ++
 4 files changed, 38 insertions(+)

diff --git a/src/mainboard/google/bluey/Kconfig b/src/mainboard/google/bluey/Kconfig
index 249990c9f8..0ddf0211ea 100644
--- a/src/mainboard/google/bluey/Kconfig
+++ b/src/mainboard/google/bluey/Kconfig
@@ -94,6 +94,12 @@ config MAINBOARD_NO_USB_A_PORT
 	help
 	  Enable this option if your mainboard is not equipped with USB-A port.
 
+config MAINBOARD_SUPPORTS_PARALLEL_CHARGING
+	bool
+	default n
+	help
+	  Enable this option if your mainboard supports parallel charging.
+
 config MAINBOARD_HAS_GOOGLE_TPM
 	bool
 	default n
diff --git a/src/mainboard/google/bluey/board.h b/src/mainboard/google/bluey/board.h
index af2715b898..40e63791dc 100644
--- a/src/mainboard/google/bluey/board.h
+++ b/src/mainboard/google/bluey/board.h
@@ -42,6 +42,7 @@
 
 void setup_chromeos_gpios(void);
 bool is_off_mode(void);
+void configure_parallel_charging(void);
 void enable_slow_battery_charging(void);
 void disable_slow_battery_charging(void);
 
diff --git a/src/mainboard/google/bluey/charging.c b/src/mainboard/google/bluey/charging.c
index bbb849d438..9d53372f9b 100644
--- a/src/mainboard/google/bluey/charging.c
+++ b/src/mainboard/google/bluey/charging.c
@@ -21,6 +21,35 @@ enum charging_status {
 	CHRG_ENABLE,
 };
 
+#define PMC8380F_SLAVE_ID	0x05
+#define GPIO07_MODE_CTL			0x8E40
+#define GPIO07_DIG_OUT_SOURCE_CTL	0x8E44
+#define GPIO07_EN_CTL			0x8E46
+#define GPIO09_MODE_CTL			0x9040
+#define GPIO09_DIG_OUT_SOURCE_CTL	0x9044
+#define GPIO09_EN_CTL			0x9046
+
+#define MODE_OUTPUT		0x01
+#define OUTPUT_INVERT		0x80
+#define PERPH_EN		0x80
+
+/*
+ * Enable PMC8380F GPIO07 & GPIO09 for parallel charging.
+ */
+void configure_parallel_charging(void)
+{
+	if (!CONFIG(MAINBOARD_SUPPORTS_PARALLEL_CHARGING))
+		return;
+
+	printk(BIOS_INFO, "Configure parallel charging support\n");
+	spmi_write8(SPMI_ADDR(PMC8380F_SLAVE_ID, GPIO07_MODE_CTL), MODE_OUTPUT);
+	spmi_write8(SPMI_ADDR(PMC8380F_SLAVE_ID, GPIO07_DIG_OUT_SOURCE_CTL), OUTPUT_INVERT);
+	spmi_write8(SPMI_ADDR(PMC8380F_SLAVE_ID, GPIO07_EN_CTL), PERPH_EN);
+	spmi_write8(SPMI_ADDR(PMC8380F_SLAVE_ID, GPIO09_MODE_CTL), MODE_OUTPUT);
+	spmi_write8(SPMI_ADDR(PMC8380F_SLAVE_ID, GPIO09_DIG_OUT_SOURCE_CTL), OUTPUT_INVERT);
+	spmi_write8(SPMI_ADDR(PMC8380F_SLAVE_ID, GPIO09_EN_CTL), PERPH_EN);
+}
+
 /*
  * Enable charging w/ 1A Icurrent supply at max.
  */
diff --git a/src/mainboard/google/bluey/mainboard.c b/src/mainboard/google/bluey/mainboard.c
index 660a99f07a..7b31a8cba6 100644
--- a/src/mainboard/google/bluey/mainboard.c
+++ b/src/mainboard/google/bluey/mainboard.c
@@ -85,6 +85,8 @@ static void display_startup(void)
 
 static void mainboard_init(struct device *dev)
 {
+	configure_parallel_charging();
+
 	/* Skip mainboard initialization if boot mode is "low-battery" or "off-mode charging"*/
 	if (is_low_power_boot())
 		return;

From 896984e800a60ff6a45006dd147ffee0ca979f72 Mon Sep 17 00:00:00 2001
From: Kapil Porwal <kapilporwal@google.com>
Date: Tue, 16 Dec 2025 00:49:07 +0530
Subject: [PATCH 2858/3886] mb/google/bluey/quartz: Enable parallel charging
 support

Select MAINBOARD_SUPPORTS_PARALLEL_CHARGING for the Quartz variant
to enable the PMC8380F GPIO configuration required for parallel
charging.

BUG=b:468120472
TEST=Build Google/Quartz.

Change-Id: I3f6eacae589ac0496d766e56ac82aa4d1138df3b
Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90515
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jayvik Desai <jayvik@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Pranava Y N <pranavayn@google.com>
---
 src/mainboard/google/bluey/Kconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/src/mainboard/google/bluey/Kconfig b/src/mainboard/google/bluey/Kconfig
index 0ddf0211ea..8c90202643 100644
--- a/src/mainboard/google/bluey/Kconfig
+++ b/src/mainboard/google/bluey/Kconfig
@@ -55,6 +55,7 @@ config BOARD_GOOGLE_QUARTZ
 	select BOARD_GOOGLE_MODEL_QUARTZ
 	select SOC_QUALCOMM_HAMOA
 	select MAINBOARD_NO_USB_A_PORT
+	select MAINBOARD_SUPPORTS_PARALLEL_CHARGING
 
 if BOARD_GOOGLE_BLUEY_COMMON
 

From a923470688341877f1eaf696b15e574cab017391 Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Wed, 17 Dec 2025 14:43:26 -0600
Subject: [PATCH 2859/3886] drv/intel/mipi_camera: Remove duplicate comments
 for DSM methods

The DSM methods already have the full ASL generated by the acpigen
calls in a comment above the function, so there's no need for line-
by-line comments for the acpigen calls. Keep the comments for
acpigen_pop_len() as they do enhance readability.

TEST=n/a, non functional change

Change-Id: I95bbc0b36706a45883ea50b7947c6c0235f546f7
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90544
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
---
 src/drivers/intel/mipi_camera/camera.c | 23 -----------------------
 1 file changed, 23 deletions(-)

diff --git a/src/drivers/intel/mipi_camera/camera.c b/src/drivers/intel/mipi_camera/camera.c
index bab652fccb..1b2fc692d8 100644
--- a/src/drivers/intel/mipi_camera/camera.c
+++ b/src/drivers/intel/mipi_camera/camera.c
@@ -246,27 +246,20 @@ static void camera_generate_dsm_sensor(const struct device *dev)
 {
 	struct drivers_intel_mipi_camera_config *config = dev->chip_info;
 
-	/* If (LEqual (Local0, ToUUID (UUID_DSM_SENSOR))) */
 	acpigen_write_if();
 	acpigen_emit_byte(LEQUAL_OP);
 	acpigen_emit_byte(LOCAL0_OP);
 	acpigen_write_uuid(UUID_DSM_SENSOR);
 
-	/* If (LEqual (Arg2, Zero)) */
 	acpigen_write_if_lequal_op_int(ARG2_OP, 0);
-	/* If (LEqual (Arg1, Zero)) */
 	acpigen_write_if_lequal_op_int(ARG1_OP, 0);
-	/* Return (Buffer (One) { 0x3 }) */
 	acpigen_write_return_singleton_buffer(0x3);
-	/* Else */
 	acpigen_write_else();
-	/* Return (Buffer (One) { 0x1 }) */
 	acpigen_write_return_singleton_buffer(0x1);
 	acpigen_pop_len();	/* If Arg1=0 */
 
 	acpigen_pop_len();	/* If Arg2=0 */
 
-	/* If (LEqual (Arg2, One)) */
 	acpigen_write_if_lequal_op_int(ARG2_OP, 1);
 	acpigen_write_return_string(config && config->sensor_name ? config->sensor_name : "UNKNOWN");
 	acpigen_pop_len();	/* If Arg2=1 */
@@ -300,33 +293,27 @@ static void camera_generate_dsm_i2c(const struct device *dev)
 	int i2c_dev_count = 1 + (config->ssdb.vcm_type ? 1 : 0) + (config->ssdb.rom_type ? 1 : 0);
 	int i2c_dev_idx = 1;
 
-	/* If (LEqual (Local0, ToUUID (UUID_DSM_I2C))) */
 	acpigen_write_if();
 	acpigen_emit_byte(LEQUAL_OP);
 	acpigen_emit_byte(LOCAL0_OP);
 	acpigen_write_uuid(UUID_DSM_I2C);
-	/* ToInteger (Arg2, Local1) */
 	acpigen_write_to_integer(ARG2_OP, LOCAL1_OP);
 
-	/* If (LEqual (Local1, 1)) */
 	acpigen_write_if_lequal_op_int(LOCAL1_OP, i2c_dev_idx++);
 	acpigen_write_return_integer(i2c_dev_count);
 	acpigen_pop_len();	/* If Arg2=1 */
 
-	/* If (LEqual (Local1, 2)) */
 	acpigen_write_if_lequal_op_int(LOCAL1_OP, i2c_dev_idx++);
 	acpigen_write_return_integer(address_for_dev_type(dev, DEV_TYPE_SENSOR));
 	acpigen_pop_len();	/* If Arg2=2 */
 
 	if (config->ssdb.vcm_type) {
-		/* If (LEqual (Local1, 3)) */
 		acpigen_write_if_lequal_op_int(LOCAL1_OP, i2c_dev_idx++);
 		acpigen_write_return_integer(address_for_dev_type(dev, DEV_TYPE_VCM));
 		acpigen_pop_len();      /* If Arg2=3 */
 	}
 
 	if (config->ssdb.rom_type) {
-		/* If (LEqual (Local1, 3 or 4)) */
 		acpigen_write_if_lequal_op_int(LOCAL1_OP, i2c_dev_idx);
 		acpigen_write_return_integer(address_for_dev_type(dev, DEV_TYPE_ROM));
 		acpigen_pop_len();      /* If Arg2=3 or 4 */
@@ -364,28 +351,21 @@ static void camera_generate_dsm_i2c_v2(const struct device *dev)
 	int i2c_count = 1 + (config->ssdb.vcm_type ? 1 : 0) + (config->ssdb.rom_type ? 1 : 0);
 	int i2c_idx = 1;
 
-	/* If (LEqual (Local0, ToUUID(UUID_DSM_I2C_V2))) */
 	acpigen_write_if();
 	acpigen_emit_byte(LEQUAL_OP);
 	acpigen_emit_byte(LOCAL0_OP);
 	acpigen_write_uuid(UUID_DSM_I2C_V2);
 
-	/* If (LEqual (Arg2, Zero)) */
 	acpigen_write_if_lequal_op_int(ARG2_OP, 0);
 
-	/* If (LEqual (Arg1, Zero)) */
 	acpigen_write_if_lequal_op_int(ARG1_OP, 0);
-	/* Return (Buffer (One) { 0x3 }) */
 	acpigen_write_return_singleton_buffer(0x3);
-	/* Else */
 	acpigen_write_else();
-	/* Return (Buffer (One) { 0x1 }) */
 	acpigen_write_return_singleton_buffer(0x1);
 	acpigen_pop_len();	/* If Arg1=0 */
 
 	acpigen_pop_len();	/* If Arg2=0 */
 
-	/* If (LEqual (Arg2, One)) */
 	acpigen_write_if_lequal_op_int(ARG2_OP, 1);
 
 	/* Buffer is 13 * 4 = 52 bytes: count + up to 12 device addresses */
@@ -425,18 +405,15 @@ static void camera_generate_dsm_i2c_v2(const struct device *dev)
  */
 static void camera_generate_dsm_cvf(const struct device *dev)
 {
-	/* If (LEqual (Local0, ToUUID (UUID_DSM_CVF))) */
 	acpigen_write_if();
 	acpigen_emit_byte(LEQUAL_OP);
 	acpigen_emit_byte(LOCAL0_OP);
 	acpigen_write_uuid(UUID_DSM_CVF);
 
-	/* If (LEqual (Arg2, Zero)) */
 	acpigen_write_if_lequal_op_int(ARG2_OP, 0);
 	acpigen_write_return_singleton_buffer(0x3);
 	acpigen_pop_len();
 
-	/* If (LEqual (Arg2, One)) */
 	acpigen_write_if_lequal_op_int(ARG2_OP, 1);
 	acpigen_write_return_integer(0);
 	acpigen_pop_len();

From 92f03c0c287e92f6c82b342277a416dff92e5a75 Mon Sep 17 00:00:00 2001
From: Ian Feng <ian_feng@compal.corp-partner.google.com>
Date: Tue, 9 Dec 2025 10:04:53 +0800
Subject: [PATCH 2860/3886] mb/google/ocelot/var/kodkod: Config touchpad I2C
 frequency

Configure the touchpad I2C bus high and low time.

BUG=b:466136598
TEST=Build and boot to OS in kodkod.
kodkod:/ # getevent
add device 2: /dev/input/event4
  name:     "Elan Touchpad"

Change-Id: I5c996ccf69e8dfe1485c7161ea2efd5579190975
Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90423
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Reviewed-by: Pranava Y N <pranavayn@google.com>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
---
 src/mainboard/google/ocelot/variants/kodkod/overridetree.cb | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/src/mainboard/google/ocelot/variants/kodkod/overridetree.cb b/src/mainboard/google/ocelot/variants/kodkod/overridetree.cb
index 03c12dd9db..0c34b2f25c 100644
--- a/src/mainboard/google/ocelot/variants/kodkod/overridetree.cb
+++ b/src/mainboard/google/ocelot/variants/kodkod/overridetree.cb
@@ -64,6 +64,12 @@ chip soc/intel/pantherlake
 		.chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT,
 		.i2c[0] = {
 			.speed = I2C_SPEED_FAST,
+			.speed_config[0] = {
+				.speed = I2C_SPEED_FAST,
+				.scl_lcnt = 257,
+				.scl_hcnt = 257,
+				.sda_hold = 30,
+			}
 		},
 		.i2c[1] = {
                         .speed = I2C_SPEED_FAST,

From 0a867b397171d138f5688a7f7f486b15323c5970 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Micha=C5=82=20=C5=BBygowski?= <michal.zygowski@3mdeb.com>
Date: Tue, 16 Sep 2025 09:24:20 +0200
Subject: [PATCH 2861/3886] acpi/ivrs: Fill second EFR image value
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Based on AMD doc #48882 PUB Rev 3.10 [1]. Now, the IVHD type 11h and
40h have a second 64bit EFR value that should be filled with IOMMU MMIO
offset 0x1A0 register value if EFR is supported.

[1] https://docs.amd.com/v/u/en-US/48882_IOMMU

Change-Id: I0da79bed8994671c651328cd7a29d9480a122528
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89200
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
---
 src/include/acpi/acpi.h              | 3 ++-
 src/include/acpi/acpi_ivrs.h         | 3 ++-
 src/soc/amd/common/block/acpi/ivrs.c | 4 ++++
 3 files changed, 8 insertions(+), 2 deletions(-)

diff --git a/src/include/acpi/acpi.h b/src/include/acpi/acpi.h
index ca1ec7d894..87c99a1eb3 100644
--- a/src/include/acpi/acpi.h
+++ b/src/include/acpi/acpi.h
@@ -595,7 +595,8 @@ typedef struct acpi_ivrs_ivhd_11 {
 	struct ivhd11_iommu_attr iommu_attributes;
 	uint32_t efr_reg_image_low;
 	uint32_t efr_reg_image_high;
-	uint32_t reserved[2];
+	uint32_t efr_reg_image2_low;
+	uint32_t efr_reg_image2_high;
 	uint8_t entry[];
 } __packed acpi_ivrs_ivhd11_t;
 
diff --git a/src/include/acpi/acpi_ivrs.h b/src/include/acpi/acpi_ivrs.h
index ad86e6a2f3..3efd654e53 100644
--- a/src/include/acpi/acpi_ivrs.h
+++ b/src/include/acpi/acpi_ivrs.h
@@ -200,7 +200,8 @@ typedef struct acpi_ivrs_ivhd_40 {
 	uint32_t iommu_attributes;
 	uint32_t efr_reg_image_low;
 	uint32_t efr_reg_image_high;
-	uint32_t reserved[2];
+	uint32_t efr_reg_image2_low;
+	uint32_t efr_reg_image2_high;
 	uint8_t entry[];
 } __packed acpi_ivrs_ivhd40_t;
 
diff --git a/src/soc/amd/common/block/acpi/ivrs.c b/src/soc/amd/common/block/acpi/ivrs.c
index 451a6c0879..2301158a0a 100644
--- a/src/soc/amd/common/block/acpi/ivrs.c
+++ b/src/soc/amd/common/block/acpi/ivrs.c
@@ -223,6 +223,8 @@ static unsigned long acpi_fill_ivrs40(unsigned long current, acpi_ivrs_ivhd_t *i
 	if (pci_read_config32(iommu_dev, ivhd_40->capability_offset) & EFR_FEATURE_SUP) {
 		ivhd_40->efr_reg_image_low  = read32p(ivhd_40->iommu_base_low + 0x30);
 		ivhd_40->efr_reg_image_high = read32p(ivhd_40->iommu_base_low + 0x34);
+		ivhd_40->efr_reg_image2_low  = read32p(ivhd_40->iommu_base_low + 0x1a0);
+		ivhd_40->efr_reg_image2_high = read32p(ivhd_40->iommu_base_low + 0x1a4);
 	}
 
 	current += sizeof(acpi_ivrs_ivhd40_t);
@@ -282,6 +284,8 @@ static unsigned long acpi_fill_ivrs11(unsigned long current, acpi_ivrs_ivhd_t *i
 	if (pci_read_config32(iommu_dev, ivhd_11->capability_offset) & EFR_FEATURE_SUP) {
 		ivhd_11->efr_reg_image_low  = read32p(ivhd_11->iommu_base_low + 0x30);
 		ivhd_11->efr_reg_image_high = read32p(ivhd_11->iommu_base_low + 0x34);
+		ivhd_11->efr_reg_image2_low  = read32p(ivhd_11->iommu_base_low + 0x1a0);
+		ivhd_11->efr_reg_image2_high = read32p(ivhd_11->iommu_base_low + 0x1a4);
 	}
 
 	current += sizeof(acpi_ivrs_ivhd11_t);

From 4b353affd49175ad4c7955e22df361f980911012 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Micha=C5=82=20=C5=BBygowski?= <michal.zygowski@3mdeb.com>
Date: Wed, 5 Nov 2025 14:17:30 +0100
Subject: [PATCH 2862/3886] soc/amd/common/acpi/lpc.asl: Add HPET device
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

FWTS complains on HPET base not being found in DSDT/SSDT:

Test 3 of 4: Test HPET base in DSDT and/or SSDT.
WARNING: Test 3, Test skipped because HPET Device address was not
found in DSDT/SSDT.

Declare HPET device under LPC device to fix the issue.

TEST=Run FWTS on Gigabyte MZ33-AR1 and see no error in HPET tests.

Change-Id: I68b872291dc93320e7a0b33a79e3336e1372b178
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89924
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/soc/amd/common/acpi/lpc.asl | 44 ++++++++++++++++++++++++++++++++-
 1 file changed, 43 insertions(+), 1 deletion(-)

diff --git a/src/soc/amd/common/acpi/lpc.asl b/src/soc/amd/common/acpi/lpc.asl
index 60f4eff696..174241f887 100644
--- a/src/soc/amd/common/acpi/lpc.asl
+++ b/src/soc/amd/common/acpi/lpc.asl
@@ -16,6 +16,12 @@ Device(LPCB) {
 	*	DBGO("\\_SB\\PCI0\\LpcIsaBr\\_INI\n")
 	} */ /* End Method(_SB.SBRDG._INI) */
 
+	OperationRegion (ERMM, SystemMemory, 0xFED80300, 0x1)
+	Field (ERMM, AnyAcc, NoLock, Preserve)
+	{
+		, 6,
+		HPEN, 1
+	}
 
 	Device(LDRC)	// LPC device: Resource consumption
 	{
@@ -60,10 +66,23 @@ Device(LPCB) {
 	/* Real Time Clock Device */
 	Device(RTC0) {
 		Name(_HID, EISAID("PNP0B00"))   /* AT Real Time Clock (not PIIX4 compatible) */
-		Name(_CRS, ResourceTemplate() {
+		Name(CRS0, ResourceTemplate() {
+			IO(Decode16,0x0070, 0x0070, 0, 2)
+		})
+		Name(CRS1, ResourceTemplate() {
 			IRQNoFlags(){8}
 			IO(Decode16,0x0070, 0x0070, 0, 2)
 		})
+		Method (_CRS, 0)
+		{
+			/* Avoid IRQ resource conflict with HPET */
+			If (^^HPEN)
+			{
+				Return (CRS0)
+			}
+
+			Return (CRS1)
+		}
 	} /* End Device(_SB.PCI0.LpcIsaBr.RTC0) */
 
 	Device(TMR) {	/* Timer */
@@ -111,4 +130,27 @@ Device(LPCB) {
 			IRQNoFlags(){13}
 		})
 	} /* End Device(_SB.PCI0.LpcIsaBr.COPR) */
+
+	Device (HPET) {
+		Name (_HID,EISAID("PNP0103"))	/* HPET System Timer */
+		Name (_CRS, ResourceTemplate () {
+			Memory32Fixed(ReadWrite,
+			0xFED00000,
+			0x00000400,
+			)
+			IRQNoFlags(){0}
+			IRQNoFlags(){8}
+		})
+
+		Method (_STA, 0, NotSerialized)
+		{
+			If (^^HPEN)
+			{
+				Return (0xF)
+			}
+
+			Return (0x1)
+		}
+	}
+
 } /* end LPCB */

From 077191641befb8b4e28af13dea18bdfc05602d56 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Micha=C5=82=20=C5=BBygowski?= <michal.zygowski@3mdeb.com>
Date: Mon, 6 Oct 2025 14:21:03 +0200
Subject: [PATCH 2863/3886] vendorcode/amd/opensil/Makefile.mk: Add 0x prefix
 for BIOS address
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

The Makefile is patching the BIOS moudule base address and size so that
the openSIL knows where the reset vector resides. However, the printf
used for hex convertion is missing 0x prefix for hexvalue. Kconfig hex
values start with 0x prefix. Otherwise, there is a chance the bios_base
variable could be interpreted as decimal integer. This could result
in improper reset vector address being calculated in OpenSIL and APs not
able to be brought up.

Change-Id: Ib528491b266ec2e8d74b9c8713788f8f37037162
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89472
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
---
 src/vendorcode/amd/opensil/Makefile.mk | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/vendorcode/amd/opensil/Makefile.mk b/src/vendorcode/amd/opensil/Makefile.mk
index 3e8661d804..5c881f9bc6 100644
--- a/src/vendorcode/amd/opensil/Makefile.mk
+++ b/src/vendorcode/amd/opensil/Makefile.mk
@@ -53,7 +53,7 @@ PYTHON?=python
 
 OPENSIL_CONFIG=opensil_config
 
-bios_base=$(shell printf "%x" $(call int-subtract, $(CONFIG_ROMSTAGE_ADDR) $(CONFIG_C_ENV_BOOTBLOCK_SIZE)))
+bios_base=$(shell printf "0x%x" $(call int-subtract, $(CONFIG_ROMSTAGE_ADDR) $(CONFIG_C_ENV_BOOTBLOCK_SIZE)))
 bios_size=$(CONFIG_C_ENV_BOOTBLOCK_SIZE)
 
 $(OBJPATH)/$(OPENSIL_CONFIG): $(opensil_dir)/../opensil_config.template

From 5bb7a83a7a7bfc766426cfe57e9a66bb27eb6152 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Micha=C5=82=20=C5=BBygowski?= <michal.zygowski@3mdeb.com>
Date: Mon, 6 Oct 2025 10:42:40 +0200
Subject: [PATCH 2864/3886] acpi/acpi_apic.c: Generate MADT LAPIC entries based
 on current mode
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Depending on the Kconfig, LAPIC may be in either xAPIC or x2APIC mode.
However, coreboot generates MADT LAPIC entries based on APIC ID rather
than currently enabled LAPIC mode. This resulted in LAPICs enabled in
x2APIC mode being described as xAPICs in MADT.

Create appropriate MADT LAPIC entries based on currently enabled mode
by calling is_x2apic_mode.

TEST=MADT describes LAPICs in x2APIC mode on Gigabyte MZ33-AR1, matching
the actually enabled LAPIC mode.

Change-Id: Iebbbca415f0b775339cbfab5c24848940d92878d
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89475
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/acpi/acpi_apic.c | 18 ++++++++++--------
 1 file changed, 10 insertions(+), 8 deletions(-)

diff --git a/src/acpi/acpi_apic.c b/src/acpi/acpi_apic.c
index 1862195e7f..355d3f9836 100644
--- a/src/acpi/acpi_apic.c
+++ b/src/acpi/acpi_apic.c
@@ -6,6 +6,7 @@
 #include <arch/smp/mpspec.h>
 #include <commonlib/sort.h>
 #include <cpu/cpu.h>
+#include <cpu/x86/lapic.h>
 #include <device/device.h>
 
 static int acpi_create_madt_lapic(acpi_madt_lapic_t *lapic, u8 cpu, u8 apic)
@@ -33,12 +34,12 @@ static int acpi_create_madt_lx2apic(acpi_madt_lx2apic_t *lapic, u32 cpu, u32 api
 
 unsigned long acpi_create_madt_one_lapic(unsigned long current, u32 index, u32 lapic_id)
 {
-	if (lapic_id <= ACPI_MADT_MAX_LAPIC_ID)
-		current += acpi_create_madt_lapic((acpi_madt_lapic_t *)current, index,
-						  lapic_id);
-	else
+	if (is_x2apic_mode())
 		current += acpi_create_madt_lx2apic((acpi_madt_lx2apic_t *)current, index,
 						    lapic_id);
+	else
+		current += acpi_create_madt_lapic((acpi_madt_lapic_t *)current, index,
+						  lapic_id);
 
 	return current;
 }
@@ -181,12 +182,13 @@ unsigned long acpi_create_madt_lapic_nmis(unsigned long current)
 
 	/* 1: LINT1 connect to NMI */
 	/* create all subtables for processors */
-	current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *)current,
-			ACPI_MADT_LAPIC_NMI_ALL_PROCESSORS, flags, 1);
-
-	if (!CONFIG(XAPIC_ONLY))
+	if (is_x2apic_mode())
 		current += acpi_create_madt_lx2apic_nmi((acpi_madt_lx2apic_nmi_t *)current,
 			ACPI_MADT_LX2APIC_NMI_ALL_PROCESSORS, flags, 1);
+	else
+		current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *)current,
+			ACPI_MADT_LAPIC_NMI_ALL_PROCESSORS, flags, 1);
+
 
 	return current;
 }

From fc37085ddbb936bf6fd254e28f87e776e688aa3f Mon Sep 17 00:00:00 2001
From: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com>
Date: Thu, 18 Dec 2025 18:57:33 -0800
Subject: [PATCH 2865/3886] Documentation/vboot: Update vboot supported boards
 list

Auto-generated by util/vboot_list/vboot_list.sh.

Change-Id: I0f8d5a7857a9a1ad954204481cf56f64f34ee7ca
Signed-off-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90552
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
---
 Documentation/security/vboot/list_vboot.md | 151 +++++++++++----------
 1 file changed, 79 insertions(+), 72 deletions(-)

diff --git a/Documentation/security/vboot/list_vboot.md b/Documentation/security/vboot/list_vboot.md
index 667bbee5b0..2c66a1e87c 100644
--- a/Documentation/security/vboot/list_vboot.md
+++ b/Documentation/security/vboot/list_vboot.md
@@ -25,7 +25,7 @@
 ## Google
 - Asurada
 - Hayato
-- Spherion
+- Spherion (Acer Chromebook 514 (CB514-2H, CB514-2HT))
 - Auron_Paine (Acer C740 Chromebook)
 - Auron_Yuna (Acer Chromebook 15 (C910/CB5-531))
 - Buddy (Acer Chromebase 24)
@@ -48,84 +48,84 @@
 - Brox TI PDC
 - Caboc
 - Greenbayupoc
-- Jubilant
-- Lotso
+- Jubilant (Multiple devices - See help text)
+- Lotso (Lenovo Chromebook Plus 2-in-1)
 - Agah
-- Anahera
+- Anahera (HP Elite c640 14 inch G3 Chromebook)
 - Anahera4ES
-- Anraggar
-- Aurash
-- Banshee
+- Anraggar (ASUS Chromebook CR12 CR1204C)
+- Aurash (AOpen Chromebox Commercial 3)
+- Banshee (Framework Laptop Chromebook Edition)
 - Brask
 - Brya 0
-- Craask
-- Craaskov
-- Constitution
-- Crota
-- Dirks
-- Dochi
-- Domika
-- Felwinter
+- Craask (Acer Chromebook Spin 512)
+- Craaskov (Acer Chromebook Spin 312)
+- Constitution (Google Meet Series Two)
+- Crota (Multiple devices - See help text)
+- Dirks (Acer Chromebox Mini CXM2 (TWL))
+- Dochi (Acer Chromebook Plus Spin 514)
+- Domika (Multiple devices - See help text)
+- Felwinter (ASUS Chromebook Flip CX5(CX5601))
 - Gaelin
-- Gimble
+- Gimble (HP Chromebook x360 14c-cd0)
 - Gimble4ES
-- Gladios
-- Glassway
-- Gothrax
-- Guren
+- Gladios (HP Chromebox Enterprise G4)
+- Glassway (CTL Chromebook Plus PX141GX)
+- Gothrax (Multiple OEM Chromebooks)
+- Guren (CTL Chromebook PX121E)
 - Hades
-- Kano
+- Kano (Acer Chromebook Spin 714)
 - Kaladin
-- Kinox
-- Kuldax
-- Joxer
-- Lisbon
-- Marasov
-- Mithrax
-- Moli
-- Moxie
+- Kinox (Lenovo ThinkCentre M60q Chromebox)
+- Kuldax (ASUS Chromebox 5/5a (CN67))
+- Joxer (HP Chromebook x360 14b)
+- Lisbon (Multiple devices - See help text)
+- Marasov (ASUS Chromebook Plus CX34 CX3402)
+- Mithrax (ASUS Chromebook CX34 Flip (CX3401))
+- Moli (Acer Chromebox CXI5)
+- Moxie (Acer Chromebox CXI6)
 - Nivviks
 - Nereid
 - Nokris
-- Omnigul
-- Osiris
+- Omnigul (Multiple devices - See help text)
+- Osiris (Acer Chromebook 516 GE)
 - Pirrha
-- Primus
-- Pujjo
-- Pujjoniru
-- Quandiso
-- Quandiso2
-- Redrix
+- Primus (Lenovo ThinkPad C14 Gen 1 Chromebook)
+- Pujjo (Lenovo 500e Yoga/Flex 3i Chromebook)
+- Pujjoniru (Lenovo Chromebook Plus 2-in-1 14ITN10)
+- Quandiso (CTL Chromebook NL73)
+- Quandiso2 (CTL Chromebook NL73 Gen 2)
+- Redrix (HP Elite Dragonfly Chromebook)
 - Redrix4ES
-- Riven
-- Rull
+- Riven (Acer Chromebook Spin 511)
+- Rull (Acer Chromebook 514 C937)
 - Skolas
 - Skolas4ES
-- Taeko
+- Taeko (Lenovo IdeaPad/Flex 5i Chromebook 14)
 - Taeko4ES
-- Taniks
-- Teliks
+- Taniks (Lenovo IdeaPad Gaming Chromebook 16)
+- Teliks (ASUS Chromebook CR11 (CR1104CTA))
 - Tereid
 - Tivviks
 - Trulo
-- Uldren
+- Uldren (Dell Chromebook 3120)
 - Uldrenite
-- Vell
-- Volmar
-- Xivu
-- Yaviks
-- Yavilla
+- Vell (HP Dragonfly Pro Chromebook)
+- Volmar (Acer Chromebook Vero 514)
+- Xivu (Asus Chromebook CR11 [CR1102C])
+- Yaviks (HP Chromebook 15.6)
+- Yavilla (HP Fortis 11 G10 Chromebook)
 - Zydron
-- Xol
+- Xol (Galaxy Chromebook Plus)
 - Nova
-- Bujia
+- Bujia (Multiple devices - See help text)
 - Yavista
-- Sundance
-- Pujjoga
-- Pujjogatwin
+- Sundance (NEC Chromebook Y4)
+- Pujjoga (Lenovo 500e Chromebook Gen 4s)
+- Pujjogatwin (Lenovo 500e Chromebook Gen 4s)
 - Pujjolo
 - Orisa
-- Telith
+- Telith (ASUS Chromebook CX15 (CX1505CTA))
 - Meliks
 - Epic
 - Pujjocento
@@ -154,11 +154,11 @@
 - Edgar (Acer Chromebook 14 (CB3-431))
 - Kefka (Dell Chromebook 11 3180/3189)
 - Reks (Lenovo N22/N42 Chromebook)
-- Relm
+- Relm (Multiple devices - See help text)
 - Setzer (HP Chromebook 11 G5)
 - Terra (ASUS Chromebook C202SA/C300SA/C301SA)
 - Ultima (Lenovo Yoga 11e G3)
-- Wizpig
+- Wizpig (Multiple devices - See help text)
 - Drallion
 - Eve (Google Pixelbook)
 - Fatcat
@@ -175,9 +175,10 @@
 - Kinmen
 - Lapis
 - Moonstone
-- Fizz
-- Karma
-- Endeavour
+- Ruby
+- Fizz (Multiple devices - See help text)
+- Karma (Acer Chromebase 24I2)
+- Endeavour (Google Meet Series One (Lenovo))
 - Foster
 - Gale (Google WiFi)
 - Geralt
@@ -192,7 +193,7 @@
 - Kevin (Samsung Chromebook Plus)
 - Gru
 - Bob (Asus Chromebook Flip C101PA)
-- Scarlet
+- Scarlet (Acer Chromebook Tab 10)
 - Nefario
 - Rainier
 - Dewatt (Acer Chromebook Spin 514)
@@ -233,7 +234,7 @@
 - Kodama (Lenovo 10e Chromebook Tablet)
 - Kakadu
 - Flapjack
-- Katsu
+- Katsu (ASUS Chromebook Detachable CZ1)
 - Jacuzzi
 - Juniper (Acer Chromebook Spin 311 (CP311-3H))
 - Kappa
@@ -244,7 +245,7 @@
 - Esche (HP Chromebook 11MK G9 EE)
 - Burnet (HP Chromebook x360 11MK G3 EE)
 - Fennel
-- Cozmo
+- Cozmo (Acer Chromebook 314 (CB314-2H/CB314-2HT))
 - Makomo
 - Munna
 - Pico
@@ -257,6 +258,7 @@
 - Oak
 - Elm (Acer Chromebook R13)
 - Hana (Lenovo N23 Yoga Chromebook)
+- Kodkod
 - Matsu
 - Ocelot
 - Ocelotite
@@ -265,6 +267,7 @@
 - Ocelot4ES
 - Ocelotite4ES
 - Ocelotmchp4ES
+- Ocicat
 - Parrot (Acer C7/C710 Chromebook)
 - Atlas (Google Pixelbook Go)
 - Poppy
@@ -285,10 +288,11 @@
 - Noibat (HP Chromebox G3)
 - Puff
 - Scout (Series One Desk 27)
-- Wyvern (CTL Chromebox CBx2)
+- Wyvern (Multiple devices - See help text)
 - Hylia
 - Navi
 - Rauru
+- Sapphire
 - Reef/Electro (Acer Chromebook Spin 11 R751T)
 - Pyro (Lenovo Thinkpad (Yoga) 11e Chromebook)
 - Sand (Acer Chromebook 15 CB515-1HT/1H)
@@ -296,7 +300,7 @@
 - Coral
 - Deku
 - Deku4ES
-- Karis
+- Karis (Acer Chromebook Plus Spin 714)
 - Karis4ES
 - Ovis
 - Ovis4ES
@@ -305,18 +309,20 @@
 - Rex4ES
 - Rex4ES EC ISH
 - Rex 64
-- Screebo
+- Screebo (ASUS ExpertBook CX54 Chromebook Plus (CX5403))
 - Screebo4ES
-- Kanix
+- Kanix (Acer Chromebook Plus 714)
 - Arcada (Latitude 5300 2-in-1 Chromebook Enterprise)
 - Sarien (Dell Latitude 5400 Chromebook Enterprise)
-- Crystaldrift
+- Crystaldrift (SPC Chromebook V1)
 - Frostflow (ASUS Chromebook CM34 Flip)
 - Markarth (Acer Chromebook Plus 514)
 - Skyrim
 - Winterhold (Dell Latitude 3445 Chromebook)
 - Anakin
 - Baze
+- Dooku
+- Grogu
 - Obiwan
 - Padme
 - Skywalker
@@ -330,16 +336,16 @@
 - Storm (OnHub Router TGR1900)
 - Stout (Lenovo Thinkpad X131e Chromebook)
 - Bubs
-- Coachz
+- Coachz (HP Chromebook x2 11-da0)
 - Gelarshie
 - Homestar
 - Kingoftown
-- Lazor
+- Lazor (Acer Chromebook Spin 513, CP513-1H/1HL, R841T/LT)
 - Marzipan
 - Mrbland
 - Pazquel
 - Pompom
-- Quackingstick
+- Quackingstick (Acer Chromebook Tab 510 / Enterprise Tab 510)
 - Wormdingler
 - Trogdor
 - Veyron_Jaq (Haier Chromebook 11)
@@ -428,6 +434,7 @@
 ## Lenovo
 - ThinkPad T440p
 - ThinkPad W541
+- ThinkCentre M700 / M900 Tiny
 - ThinkPad T400
 - ThinkPad T500
 - ThinkPad R400
@@ -503,8 +510,8 @@
 - Star Labs StarBook Mk VII (N200)
 - Star Labs StarBook Mk VII (165H)
 - Star Labs StarFighter Mk I (i3-1315U, i7-13700H and i9-13900H)
-- Star Labs Lite Mk V (N200)
-- Star Labs Lite Mk V Smart Battery (N200)
+- Star Labs StarFighter Mk II (125H and 285H)
+- Star Labs Lite Mk V (N200/N355)
 
 ## Supermicro
 - X11SSH-TF

From def7aa7094122147aed5d36b8f50c56496ee7ab5 Mon Sep 17 00:00:00 2001
From: Maximilian Brune <maximilian.brune@9elements.com>
Date: Sun, 16 Nov 2025 20:00:43 +0100
Subject: [PATCH 2866/3886] arch/riscv/smp: Fix race condition

If the APs are much faster then the working hart, it is possible that it
will enter HART_SLEEPING state before the working hart checks whether or
not the APs woke up by checking the HART_AWAKE state.

One can reproduce this issue by adding the following print message and
testing it in QEMU. One will notice that it will get stuck.
+ printk(BIOS_SPEW, "waiting for hart %d\n", i);
while (atomic_read(&OTHER_HLS(i)->entry.sync_a) != HART_AWAKE)

Fix it by adding another sync step at the end of `smp_resume()`.

Tested: QEMU RISC-V with -smp 64 parameter

Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: I1e0485831f71dde400d793b9f7bda88ae6519913
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87299
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
---
 src/arch/riscv/smp.c | 28 ++++++++++++++++++++++++++++
 1 file changed, 28 insertions(+)

diff --git a/src/arch/riscv/smp.c b/src/arch/riscv/smp.c
index 67dc13b8fc..ab6e0add3a 100644
--- a/src/arch/riscv/smp.c
+++ b/src/arch/riscv/smp.c
@@ -4,9 +4,25 @@
 #include <arch/encoding.h>
 #include <arch/smp/smp.h>
 #include <arch/smp/atomic.h>
+#include <assert.h>
 #include <console/console.h>
 #include <mcall.h>
 
+/*
+ *                                                               BSP
+ *                                                 --------------------------------- <---
+ *                          AP                     |     sync_b=HART_SLEEPING      |     |
+ *    ---> ---------------------------------       ---------------------------------     |
+ *   |     |     sync_a=HART_SLEEPING      | ----> | Wait for sync_a=HART_SLEEPING |     |
+ *   |     ---------------------------------       ---------------------------------     |
+ *   |     |      Wait for Interrupt       | <---- |        set_msip()             |     |
+ *   |     ---------------------------------       ---------------------------------     |
+ *   |     |     sync_a=HART_AWAKE         | ----> | Wait for sync_a=HART_AWAKE    |     |
+ *   |     ---------------------------------       ---------------------------------     |
+ *   |     |  Wait for sync_b=HART_AWAKE   | <---- |     sync_b=HART_AWAKE         |     |
+ *    ---- ---------------------------------       --------------------------------- ----
+ */
+
 // made up value to sync hart state
 #define HART_SLEEPING 0x1
 #define HART_AWAKE    0x2
@@ -29,6 +45,11 @@ void smp_pause(int working_hartid)
 		} while ((read_csr(mip) & MIP_MSIP) == 0);
 
 		atomic_set(&HLS()->entry.sync_a, HART_AWAKE); // mark the hart as awake
+
+		// wait for working_hart to notice that this hart is awake
+		while (atomic_read(&HLS()->entry.sync_b) != HART_AWAKE)
+			;
+
 		HLS()->entry.fn(HLS()->entry.arg);
 	}
 }
@@ -47,6 +68,8 @@ void smp_resume(void (*fn)(void *), void *arg)
 	if (CONFIG(RISCV_GET_HART_COUNT_AT_RUNTIME))
 		hart_count = smp_get_hart_count();
 
+	assert(hart_count <= CONFIG_MAX_CPUS);
+
 	// check that all harts are present
 
 	u32 count_awake_harts = 0;
@@ -55,6 +78,8 @@ void smp_resume(void (*fn)(void *), void *arg)
 		if (i == working_hartid)
 			continue;
 
+		atomic_set(&OTHER_HLS(i)->entry.sync_b, HART_SLEEPING);
+
 		if (atomic_read(&OTHER_HLS(i)->entry.sync_a) != HART_SLEEPING) {
 			/*
 			 * we assmue here that the time between smp_pause and smp_resume
@@ -83,6 +108,9 @@ void smp_resume(void (*fn)(void *), void *arg)
 		// wait for hart to publish its waking state
 		while (atomic_read(&OTHER_HLS(i)->entry.sync_a) != HART_AWAKE)
 			;
+
+		// signal to hart that we noticed it woke up
+		atomic_set(&OTHER_HLS(i)->entry.sync_b, HART_AWAKE);
 		count_awake_harts++;
 	}
 	printk(BIOS_DEBUG, "all harts up and running...\n");

From 060d18f0704ed31f74f413f921cdbe3ffcf078e2 Mon Sep 17 00:00:00 2001
From: Payne Lin <payne.lin@mediatek.corp-partner.google.com>
Date: Mon, 17 Nov 2025 21:02:57 +0800
Subject: [PATCH 2867/3886] soc/mediatek/mt8196: Add DSI dual channel

Add support for DSI dual channel and dual Display Stream Compression
(DSC) features.
- Add DSI dual channel and dual DSC feature.
- Add dsi1, mipi1, dsc0, dsc1 engine drivers.
- Add configuration for dual channel feature selection.
- Add 'dsi.c' for mt8196 mipi data rate calculation.
- Add 'mtk_mipi_dphy.c' for mt8196 timing calculation.

BUG=b:424782827
TEST=Build pass, boot ok.
Verify display output on the following platforms:
- 8196 Navi: eDP path.
- 8189 Skywalker: eDP path.
- 8189 Padme: single MIPI path (without DSC).
- 8196 Sapphire: dual MIPI path (with DSC).

Change-Id: I2bea829da72d23165a74b399eabfcdd55a7f28a1
Signed-off-by: Payne Lin <payne.lin@mediatek.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90504
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Chen-Tsung Hsieh <chentsung@google.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
---
 src/soc/mediatek/common/Kconfig               |   6 +
 src/soc/mediatek/common/dsi_common.c          | 332 ++++++++++++------
 .../mediatek/common/include/soc/dsi_common.h  |   1 +
 src/soc/mediatek/mt8196/Kconfig               |   1 +
 src/soc/mediatek/mt8196/Makefile.mk           |   2 +
 src/soc/mediatek/mt8196/ddp.c                 | 280 ++++++++++++++-
 src/soc/mediatek/mt8196/dsi.c                 |  88 +++++
 src/soc/mediatek/mt8196/include/soc/ddp.h     |  52 ++-
 src/soc/mediatek/mt8196/mtk_mipi_dphy.c       |  29 ++
 9 files changed, 655 insertions(+), 136 deletions(-)
 create mode 100644 src/soc/mediatek/mt8196/dsi.c
 create mode 100644 src/soc/mediatek/mt8196/mtk_mipi_dphy.c

diff --git a/src/soc/mediatek/common/Kconfig b/src/soc/mediatek/common/Kconfig
index 30cab53df6..c52f8ed407 100644
--- a/src/soc/mediatek/common/Kconfig
+++ b/src/soc/mediatek/common/Kconfig
@@ -69,6 +69,12 @@ config MEDIATEK_WDT_RESET_BY_SW
 	  If the kernel disables WDT external reset (mediatek,disable-extrst),
 	  then this option must be disabled to allow WDT hardware external reset.
 
+config MEDIATEK_DSI_DUAL_CHANNEL
+	bool
+	default n
+	help
+	  The configuration to support DSI dual channel.
+
 config MEMORY_TEST
 	bool
 	default y
diff --git a/src/soc/mediatek/common/dsi_common.c b/src/soc/mediatek/common/dsi_common.c
index 2298aa0ace..008817ade9 100644
--- a/src/soc/mediatek/common/dsi_common.c
+++ b/src/soc/mediatek/common/dsi_common.c
@@ -16,6 +16,25 @@
 #define CPHY_SYMBOL_RATE		7
 #define CPHY_SYMBOL_RATE_DIVISOR	16
 
+#define COMPRESSION_RATIO	3
+#define UNCOMPRESSED_RATIO	1
+
+static const struct {
+	struct dsi_regs *const dsi_reg;
+	struct mipi_tx_regs *const mipi_reg;
+} dsi_mipi_regs[] = {
+	{
+		.dsi_reg = dsi0,
+		.mipi_reg = mipi_tx0,
+	},
+#if CONFIG(MEDIATEK_DSI_DUAL_CHANNEL)
+	{
+		.dsi_reg = dsi1,
+		.mipi_reg = mipi_tx1,
+	},
+#endif
+};
+
 static unsigned int mtk_dsi_get_bits_per_pixel(u32 format)
 {
 	switch (format) {
@@ -33,7 +52,7 @@ static unsigned int mtk_dsi_get_bits_per_pixel(u32 format)
 }
 
 static u32 mtk_dsi_get_data_rate(u32 bits_per_pixel, u32 lanes,
-				 const struct edid *edid, bool is_cphy)
+				 const struct edid *edid, u32 mode_flags)
 {
 	/* data_rate = pixel_clock * bits_per_pixel * mipi_ratio / lanes
 	 * Note pixel_clock comes in kHz and returned data_rate is in bps.
@@ -41,9 +60,18 @@ static u32 mtk_dsi_get_data_rate(u32 bits_per_pixel, u32 lanes,
 	 * for older platforms which do not have complete implementation in HFP.
 	 * Newer platforms should just set that to 1.0 (100 / 100).
 	 */
+	u64 pixel_clock = edid->mode.pixel_clock;
 	u32 data_rate;
-	u64 dividend = (u64)edid->mode.pixel_clock * bits_per_pixel * 1000 *
-			MTK_DSI_MIPI_RATIO_NUMERATOR;
+	bool is_cphy = !!(mode_flags & MIPI_DSI_MODE_CPHY);
+	bool is_dsi_dual_channel = !!(mode_flags & MIPI_DSI_DUAL_CHANNEL);
+	bool is_dsc_enabled = !!(mode_flags & MIPI_DSI_DSC_MODE);
+
+	if (is_dsc_enabled)
+		pixel_clock = pixel_clock *
+			      (DIV_ROUND_UP(edid->mode.ha, 3) + edid->mode.hbl) /
+			      (edid->mode.ha + edid->mode.hbl);
+
+	u64 dividend = pixel_clock * bits_per_pixel * 1000 * MTK_DSI_MIPI_RATIO_NUMERATOR;
 	u64 divisor = (u64)lanes * MTK_DSI_MIPI_RATIO_DENOMINATOR;
 
 	if (is_cphy) {
@@ -51,15 +79,20 @@ static u32 mtk_dsi_get_data_rate(u32 bits_per_pixel, u32 lanes,
 		divisor *= CPHY_SYMBOL_RATE_DIVISOR;
 	}
 	data_rate = DIV_ROUND_UP(dividend, divisor);
-	printk(BIOS_INFO, "DSI data_rate: %u bps\n", data_rate);
+	printk(BIOS_INFO, "pixel_clock: %lld\n", pixel_clock);
+	printk(BIOS_INFO, "bits_per_pixel: %d\n", bits_per_pixel);
+	if (is_dsi_dual_channel)
+		data_rate = data_rate / 2;
+
+	printk(BIOS_INFO, "DSI final data_rate: %u bps\n", data_rate);
 
 	if (data_rate < MTK_DSI_DATA_RATE_MIN_MHZ * MHz) {
 		printk(BIOS_ERR, "data rate (%ubps) must be >= %ubps. "
-		       "Please check the pixel clock (%u), "
+		       "Please check the pixel clock (%llu), "
 		       "bits per pixel (%u), "
 		       "mipi_ratio (%d%%) and number of lanes (%d)\n",
 		       data_rate, MTK_DSI_DATA_RATE_MIN_MHZ * MHz,
-		       edid->mode.pixel_clock, bits_per_pixel,
+		       pixel_clock, bits_per_pixel,
 		       (100 * MTK_DSI_MIPI_RATIO_NUMERATOR /
 			MTK_DSI_MIPI_RATIO_DENOMINATOR), lanes);
 		return 0;
@@ -72,7 +105,8 @@ __weak void mtk_dsi_override_phy_timing(struct mtk_phy_timing *timing)
 	/* Do nothing. */
 }
 
-static void mtk_dsi_dphy_timing(u32 data_rate, struct mtk_phy_timing *timing)
+static void mtk_dsi_dphy_timing(struct dsi_regs *dsi_reg, u32 data_rate,
+				struct mtk_phy_timing *timing)
 {
 	u32 timcon0, timcon1, timcon2, timcon3;
 	u32 data_rate_mhz = DIV_ROUND_UP(data_rate, MHz);
@@ -91,23 +125,23 @@ static void mtk_dsi_dphy_timing(u32 data_rate, struct mtk_phy_timing *timing)
 	timcon3 = timing->clk_hs_prepare | timing->clk_hs_post << 8 |
 		  timing->clk_hs_exit << 16;
 
-	write32(&dsi0->dsi_phy_timecon0, timcon0);
-	write32(&dsi0->dsi_phy_timecon1, timcon1);
-	write32(&dsi0->dsi_phy_timecon2, timcon2);
-	write32(&dsi0->dsi_phy_timecon3, timcon3);
+	write32(&dsi_reg->dsi_phy_timecon0, timcon0);
+	write32(&dsi_reg->dsi_phy_timecon1, timcon1);
+	write32(&dsi_reg->dsi_phy_timecon2, timcon2);
+	write32(&dsi_reg->dsi_phy_timecon3, timcon3);
 }
 
-static void mtk_dsi_clk_hs_mode_enable(void)
+static void mtk_dsi_clk_hs_mode_enable(struct dsi_regs *dsi_reg)
 {
-	setbits32(&dsi0->dsi_phy_lccon, LC_HS_TX_EN);
+	setbits32(&dsi_reg->dsi_phy_lccon, LC_HS_TX_EN);
 }
 
-static void mtk_dsi_clk_hs_mode_disable(void)
+static void mtk_dsi_clk_hs_mode_disable(struct dsi_regs *dsi_reg)
 {
-	clrbits32(&dsi0->dsi_phy_lccon, LC_HS_TX_EN);
+	clrbits32(&dsi_reg->dsi_phy_lccon, LC_HS_TX_EN);
 }
 
-static void mtk_dsi_set_mode(u32 mode_flags)
+static void mtk_dsi_set_mode(struct dsi_regs *dsi_reg, u32 mode_flags)
 {
 	u32 tmp_reg1 = 0;
 
@@ -121,10 +155,10 @@ static void mtk_dsi_set_mode(u32 mode_flags)
 			tmp_reg1 = SYNC_PULSE_MODE;
 	}
 
-	write32(&dsi0->dsi_mode_ctrl, tmp_reg1);
+	write32(&dsi_reg->dsi_mode_ctrl, tmp_reg1);
 }
 
-static void mtk_dsi_rxtx_control(u32 mode_flags, u32 lanes)
+static void mtk_dsi_rxtx_control(struct dsi_regs *dsi_reg, u32 mode_flags, u32 lanes)
 {
 	u32 tmp_reg = 0;
 
@@ -150,7 +184,7 @@ static void mtk_dsi_rxtx_control(u32 mode_flags, u32 lanes)
 	if (!(mode_flags & MIPI_DSI_MODE_EOT_PACKET))
 		tmp_reg |= EOTP_DISABLE;
 
-	write32(&dsi0->dsi_txrx_ctrl, tmp_reg);
+	write32(&dsi_reg->dsi_txrx_ctrl, tmp_reg);
 }
 
 static void mtk_dsi_dphy_vdo_timing(const u32 mode_flags,
@@ -168,6 +202,9 @@ static void mtk_dsi_dphy_vdo_timing(const u32 mode_flags,
 				phy_timing->da_hs_zero + phy_timing->da_hs_exit + 3;
 
 	u32 delta = 10;
+	int channels = (mode_flags & MIPI_DSI_DUAL_CHANNEL) ? 2 : 1;
+	int dsc_ratio = (mode_flags & MIPI_DSI_DSC_MODE) ? COMPRESSION_RATIO :
+							   UNCOMPRESSED_RATIO;
 
 	if (mode_flags & MIPI_DSI_MODE_EOT_PACKET)
 		delta += 2;
@@ -188,17 +225,44 @@ static void mtk_dsi_dphy_vdo_timing(const u32 mode_flags,
 			hbp * bytes_per_pixel, d_phy);
 	}
 
-	*hsync_active_byte = edid->mode.hspw * bytes_per_pixel - 10;
+	*hsync_active_byte = edid->mode.hspw / channels * bytes_per_pixel - 10;
+
 	if (mode_flags & MIPI_DSI_MODE_LINE_END) {
 		*hsync_active_byte = DIV_ROUND_UP(*hsync_active_byte, lanes) * lanes - 2;
 		*hbp_byte = DIV_ROUND_UP(*hbp_byte, lanes) * lanes - 2;
 		*hfp_byte = DIV_ROUND_UP(*hfp_byte, lanes) * lanes - 2;
-		*hbp_byte -= (edid->mode.ha * bytes_per_pixel + 2) % lanes;
+		*hbp_byte -= (edid->mode.ha / dsc_ratio / channels * bytes_per_pixel + 2) %
+			     lanes;
 	}
 }
 
-static void mtk_dsi_config_vdo_timing(u32 mode_flags, u32 format, u32 lanes,
-				      const struct edid *edid,
+static u32 mtk_dsi_get_packet_fmt(u32 format)
+{
+	u32 packet_fmt;
+
+	switch (format) {
+	case MIPI_DSI_FMT_RGB888:
+		packet_fmt = PACKED_PS_24BIT_RGB888;
+		break;
+	case MIPI_DSI_FMT_RGB666:
+		packet_fmt = LOOSELY_PS_18BIT_RGB666;
+		break;
+	case MIPI_DSI_FMT_RGB666_PACKED:
+		packet_fmt = PACKED_PS_18BIT_RGB666;
+		break;
+	case MIPI_DSI_FMT_RGB565:
+		packet_fmt = PACKED_PS_16BIT_RGB565;
+		break;
+	default:
+		packet_fmt = PACKED_PS_24BIT_RGB888;
+		break;
+	}
+
+	return packet_fmt;
+}
+
+static void mtk_dsi_config_vdo_timing(struct dsi_regs *const dsi_reg, u32 mode_flags,
+				      u32 format, u32 lanes, const struct edid *edid,
 				      const struct mtk_phy_timing *phy_timing)
 {
 	u32 hsync_active_byte;
@@ -211,26 +275,30 @@ static void mtk_dsi_config_vdo_timing(u32 mode_flags, u32 format, u32 lanes,
 	u32 bytes_per_pixel;
 	u32 packet_fmt;
 	u32 hactive;
+	u32 hbp_offset;
 	bool is_cphy = !!(mode_flags & MIPI_DSI_MODE_CPHY);
+	bool is_dsc_enabled = !!(mode_flags & MIPI_DSI_DSC_MODE);
+	int channels = !!(mode_flags & MIPI_DSI_DUAL_CHANNEL) ? 2 : 1;
+	int dsc_ratio = is_dsc_enabled ? COMPRESSION_RATIO : UNCOMPRESSED_RATIO;
 
 	bytes_per_pixel = DIV_ROUND_UP(mtk_dsi_get_bits_per_pixel(format), 8);
 	vbp_byte = edid->mode.vbl - edid->mode.vso - edid->mode.vspw -
 		   edid->mode.vborder;
 	vfp_byte = edid->mode.vso - edid->mode.vborder;
 
-	write32(&dsi0->dsi_vsa_nl, edid->mode.vspw);
-	write32(&dsi0->dsi_vbp_nl, vbp_byte);
-	write32(&dsi0->dsi_vfp_nl, vfp_byte);
-	write32(&dsi0->dsi_vact_nl, edid->mode.va);
+	write32(&dsi_reg->dsi_vsa_nl, edid->mode.vspw);
+	write32(&dsi_reg->dsi_vbp_nl, vbp_byte);
+	write32(&dsi_reg->dsi_vfp_nl, vfp_byte);
+	write32(&dsi_reg->dsi_vact_nl, edid->mode.va);
 
-	hbp = edid->mode.hbl - edid->mode.hso - edid->mode.hspw -
-	      edid->mode.hborder;
-	hfp = edid->mode.hso - edid->mode.hborder;
+	hbp = (edid->mode.hbl - edid->mode.hso - edid->mode.hspw -
+	       edid->mode.hborder) / channels;
+	hfp = (edid->mode.hso - edid->mode.hborder) / channels;
+
+	hbp_offset = (mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE) ?
+		     0 : (edid->mode.hspw / channels);
+	hbp_byte = (hbp + hbp_offset) * bytes_per_pixel - 10;
 
-	if (mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE)
-		hbp_byte = hbp * bytes_per_pixel - 10;
-	else
-		hbp_byte = (hbp + edid->mode.hspw) * bytes_per_pixel - 10;
 	hfp_byte = hfp * bytes_per_pixel;
 
 	if (CONFIG(MEDIATEK_DSI_CPHY) && is_cphy)
@@ -255,49 +323,40 @@ static void mtk_dsi_config_vdo_timing(u32 mode_flags, u32 format, u32 lanes,
 		hbp_byte = MIN_HBP_BYTE;
 	}
 
-	write32(&dsi0->dsi_hsa_wc, hsync_active_byte);
-	write32(&dsi0->dsi_hbp_wc, hbp_byte);
-	write32(&dsi0->dsi_hfp_wc, hfp_byte);
+	write32(&dsi_reg->dsi_hsa_wc, hsync_active_byte);
+	write32(&dsi_reg->dsi_hbp_wc, hbp_byte);
+	write32(&dsi_reg->dsi_hfp_wc, hfp_byte);
 
-	switch (format) {
-	case MIPI_DSI_FMT_RGB888:
-		packet_fmt = PACKED_PS_24BIT_RGB888;
-		break;
-	case MIPI_DSI_FMT_RGB666:
-		packet_fmt = LOOSELY_PS_18BIT_RGB666;
-		break;
-	case MIPI_DSI_FMT_RGB666_PACKED:
-		packet_fmt = PACKED_PS_18BIT_RGB666;
-		break;
-	case MIPI_DSI_FMT_RGB565:
-		packet_fmt = PACKED_PS_16BIT_RGB565;
-		break;
-	default:
-		packet_fmt = PACKED_PS_24BIT_RGB888;
-		break;
-	}
+	if (is_dsc_enabled)
+		packet_fmt = COMPRESSED_PIXEL_STREAM_V2;
+	else
+		packet_fmt = mtk_dsi_get_packet_fmt(format);
 
-	hactive = edid->mode.ha;
+	hactive = edid->mode.ha / dsc_ratio / channels;
 	packet_fmt |= (hactive * bytes_per_pixel) & DSI_PS_WC;
 
-	write32(&dsi0->dsi_psctrl,
+	write32(&dsi_reg->dsi_psctrl,
 		PIXEL_STREAM_CUSTOM_HEADER << DSI_PSCON_CUSTOM_HEADER_SHIFT |
 		packet_fmt);
 
 	/* Older systems like MT8173 do not support size_con. */
 	if (MTK_DSI_HAVE_SIZE_CON)
-		write32(&dsi0->dsi_size_con,
+		write32(&dsi_reg->dsi_size_con,
 			edid->mode.va << DSI_SIZE_CON_HEIGHT_SHIFT |
 			hactive << DSI_SIZE_CON_WIDTH_SHIFT);
 	if (CONFIG(MEDIATEK_DSI_CPHY) && is_cphy)
-		mtk_dsi_cphy_enable_cmdq_6byte(dsi0);
+		mtk_dsi_cphy_enable_cmdq_6byte(dsi_reg);
 }
 
-static void mtk_dsi_start(void)
+static void mtk_dsi_dual_enable(struct dsi_regs *dsi_reg, bool enable)
 {
-	write32(&dsi0->dsi_start, 0);
-	/* Only start master DSI */
-	write32(&dsi0->dsi_start, 1);
+	clrsetbits32(&dsi_reg->dsi_con_ctrl, DSI_DUAL, (enable ? DSI_DUAL : 0));
+}
+
+static void mtk_dsi_start(struct dsi_regs *dsi_reg)
+{
+	write32(&dsi_reg->dsi_start, 0);
+	write32(&dsi_reg->dsi_start, 1);
 }
 
 static bool mtk_dsi_is_read_command(enum mipi_dsi_transaction type)
@@ -313,60 +372,77 @@ static bool mtk_dsi_is_read_command(enum mipi_dsi_transaction type)
 	}
 }
 
+static void mtk_dsi_enable_and_start(bool is_dsi_dual_channel)
+{
+	/*
+	 * For dual channel synchronization,
+	 * the secondary dsi1 must be dual-enabled before starting the primary dsi0.
+	 */
+	if (is_dsi_dual_channel)
+		mtk_dsi_dual_enable(dsi_mipi_regs[ARRAY_SIZE(dsi_mipi_regs) - 1].dsi_reg, true);
+	/*
+	 * Only start primary dsi0 for single or dual channel mode.
+	 * The secondary dsi1 is dual-enabled in mtk_dsi_dual_enable()
+	 * and does not require a separate start.
+	 * Starting only the primary dsi0 ensures correct synchronization
+	 * with secondary dsi1 if there is.
+	 */
+	mtk_dsi_start(dsi_mipi_regs[0].dsi_reg);
+}
+
 static enum cb_err mtk_dsi_cmdq(enum mipi_dsi_transaction type, const u8 *data, u8 len,
 				void *user_data)
 {
 	const u8 *tx_buf = data;
 	u32 config;
-	int i, j;
+	uint32_t *mode_flags = (uint32_t *)user_data;
+	bool is_dsi_dual_channel = (*mode_flags & MIPI_DSI_DUAL_CHANNEL);
 
-	if (!wait_ms(20, !(read32(&dsi0->dsi_intsta) & DSI_BUSY))) {
-		printk(BIOS_ERR, "%s: cannot get DSI ready for sending commands"
-		       " after 20ms and the panel may not work properly.\n",
-		       __func__);
-		return CB_ERR;
-	}
-	write32(&dsi0->dsi_intsta, 0);
-
-	if (mtk_dsi_is_read_command(type))
-		config = BTA;
-	else
-		config = (len > 2) ? LONG_PACKET : SHORT_PACKET;
-
-	if (len <= 2) {
-		uint32_t val = (type << 8) | config;
-		for (i = 0; i < len; i++)
-			val |= tx_buf[i] << (i + 2) * 8;
-		write32(&dsi0->dsi_cmdq[0], val);
-		write32(&dsi0->dsi_cmdq_size, 1);
-	} else {
-		/* TODO(hungte) Replace by buffer_to_fifo32_prefix */
-		write32(&dsi0->dsi_cmdq[0], (len << 16) | (type << 8) | config);
-		for (i = 0; i < len; i += 4) {
-			uint32_t val = 0;
-			for (j = 0; j < MIN(len - i, 4); j++)
-				val |= tx_buf[i + j] << j * 8;
-			write32(&dsi0->dsi_cmdq[i / 4 + 1], val);
+	for (unsigned int k = 0; k < ARRAY_SIZE(dsi_mipi_regs); k++) {
+		struct dsi_regs *dsi = dsi_mipi_regs[k].dsi_reg;
+		if (!wait_ms(20, !(read32(&dsi->dsi_intsta) & DSI_BUSY))) {
+			printk(BIOS_ERR, "%s: cannot get DSI-%d ready for sending commands"
+			       " after 20ms and the panel may not work properly.\n",
+			       __func__, k);
+			return CB_ERR;
 		}
-		write32(&dsi0->dsi_cmdq_size, 1 + DIV_ROUND_UP(len, 4));
+		write32(&dsi->dsi_intsta, 0);
+
+		if (mtk_dsi_is_read_command(type))
+			config = BTA;
+		else
+			config = (len > 2) ? LONG_PACKET : SHORT_PACKET;
+
+		u32 prefix = config | type << 8;
+		int prefsz = 2;
+		if (len > 2) {
+			prefix |= len << 16;
+			prefsz += 2;
+		}
+		buffer_to_fifo32_prefix(tx_buf, prefix, prefsz, prefsz + len, &dsi->dsi_cmdq[0],
+					4, 4);
+		write32(&dsi->dsi_cmdq_size, DIV_ROUND_UP(prefsz + len, 4));
+		setbits32(&dsi->dsi_cmdq_size, CMDQ_SIZE_SEL);
 	}
-	setbits32(&dsi0->dsi_cmdq_size, CMDQ_SIZE_SEL);
 
-	mtk_dsi_start();
+	mtk_dsi_enable_and_start(is_dsi_dual_channel);
 
-	if (!wait_us(400, read32(&dsi0->dsi_intsta) & CMD_DONE_INT_FLAG)) {
-		printk(BIOS_ERR, "%s: failed sending DSI command, "
-		       "panel may not work.\n", __func__);
-		return CB_ERR;
+	for (unsigned int k = 0; k < ARRAY_SIZE(dsi_mipi_regs); k++) {
+		struct dsi_regs *dsi = dsi_mipi_regs[k].dsi_reg;
+		if (!wait_us(400, read32(&dsi->dsi_intsta) & CMD_DONE_INT_FLAG)) {
+			printk(BIOS_ERR, "%s: failed sending DSI-%d command, "
+			       "panel may not work.\n", __func__, k);
+			return CB_ERR;
+		}
 	}
 
 	return CB_SUCCESS;
 }
 
-static void mtk_dsi_reset_phy(void)
+static void mtk_dsi_reset_phy(struct dsi_regs *const dsi_reg)
 {
-	setbits32(&dsi0->dsi_con_ctrl, DPHY_RESET);
-	clrbits32(&dsi0->dsi_con_ctrl, DPHY_RESET);
+	setbits32(&dsi_reg->dsi_con_ctrl, DPHY_RESET);
+	clrbits32(&dsi_reg->dsi_con_ctrl, DPHY_RESET);
 }
 
 int mtk_dsi_init(u32 mode_flags, u32 format, u32 lanes, const struct edid *edid,
@@ -375,6 +451,8 @@ int mtk_dsi_init(u32 mode_flags, u32 format, u32 lanes, const struct edid *edid,
 	u32 data_rate;
 	u32 bits_per_pixel = mtk_dsi_get_bits_per_pixel(format);
 	bool is_cphy = !!(mode_flags & MIPI_DSI_MODE_CPHY);
+	bool is_dsi_dual_channel = !!(mode_flags & MIPI_DSI_DUAL_CHANNEL);
+	unsigned int num_dsi = is_dsi_dual_channel ? 2 : 1;
 
 	if (!CONFIG(MEDIATEK_DSI_CPHY) && is_cphy) {
 		printk(BIOS_ERR, "%s: Board is built without C-PHY interface support. "
@@ -382,27 +460,47 @@ int mtk_dsi_init(u32 mode_flags, u32 format, u32 lanes, const struct edid *edid,
 		return -1;
 	}
 
-	data_rate = mtk_dsi_get_data_rate(bits_per_pixel, lanes, edid, is_cphy);
+	if (num_dsi > ARRAY_SIZE(dsi_mipi_regs)) {
+		printk(BIOS_ERR, "%s: num_dsi %d > %lu\n", __func__,
+		       num_dsi, ARRAY_SIZE(dsi_mipi_regs));
+		return -1;
+	}
+
+	data_rate = mtk_dsi_get_data_rate(bits_per_pixel, lanes, edid, mode_flags);
 	if (!data_rate)
 		return -1;
 
-	mtk_dsi_configure_mipi_tx(mipi_tx0, data_rate, lanes, is_cphy);
-	mtk_dsi_reset(dsi0);
-	struct mtk_phy_timing phy_timing = {};
-	if (CONFIG(MEDIATEK_DSI_CPHY) && is_cphy)
-		mtk_dsi_cphy_timing(data_rate, &phy_timing);
-	else
-		mtk_dsi_dphy_timing(data_rate, &phy_timing);
-	mtk_dsi_rxtx_control(mode_flags, lanes);
-	mdelay(1);
-	mtk_dsi_reset_phy();
-	mtk_dsi_clk_hs_mode_disable();
-	mtk_dsi_config_vdo_timing(mode_flags, format, lanes, edid, &phy_timing);
-	mtk_dsi_clk_hs_mode_enable();
+	for (unsigned int i = 0; i < num_dsi; i++) {
+		struct dsi_regs *dsi = dsi_mipi_regs[i].dsi_reg;
+		struct mipi_tx_regs *mipi = dsi_mipi_regs[i].mipi_reg;
+		if (!dsi || !mipi) {
+			printk(BIOS_ERR, "%s: Null dsi/mipi reg for DSI-%d\n", __func__, i);
+			return -1;
+		}
+		mtk_dsi_configure_mipi_tx(mipi, data_rate, lanes, is_cphy);
+		mtk_dsi_reset(dsi);
+		struct mtk_phy_timing phy_timing = {};
+		if (CONFIG(MEDIATEK_DSI_CPHY) && is_cphy)
+			/* Dual channel is not implemented for CPHY. */
+			mtk_dsi_cphy_timing(data_rate, &phy_timing);
+		else
+			mtk_dsi_dphy_timing(dsi, data_rate, &phy_timing);
+
+		mtk_dsi_rxtx_control(dsi, mode_flags, lanes);
+		mdelay(1);
+		mtk_dsi_reset_phy(dsi);
+		mtk_dsi_clk_hs_mode_disable(dsi);
+		mtk_dsi_config_vdo_timing(dsi, mode_flags, format, lanes, edid, &phy_timing);
+		mtk_dsi_clk_hs_mode_enable(dsi);
+	}
+
 	if (init_commands)
-		mipi_panel_parse_init_commands(init_commands, mtk_dsi_cmdq, NULL);
-	mtk_dsi_set_mode(mode_flags);
-	mtk_dsi_start();
+		mipi_panel_parse_init_commands(init_commands, mtk_dsi_cmdq, &mode_flags);
+
+	for (unsigned int i = 0; i < num_dsi; i++)
+		mtk_dsi_set_mode(dsi_mipi_regs[i].dsi_reg, mode_flags);
+
+	mtk_dsi_enable_and_start(is_dsi_dual_channel);
 
 	return 0;
 }
diff --git a/src/soc/mediatek/common/include/soc/dsi_common.h b/src/soc/mediatek/common/include/soc/dsi_common.h
index e06701f490..57961d10bb 100644
--- a/src/soc/mediatek/common/include/soc/dsi_common.h
+++ b/src/soc/mediatek/common/include/soc/dsi_common.h
@@ -59,6 +59,7 @@ enum {
 	LOOSELY_PS_18BIT_RGB666 = (1 << 16),
 	PACKED_PS_18BIT_RGB666 = (2 << 16),
 	PACKED_PS_24BIT_RGB888 = (3 << 16),
+	COMPRESSED_PIXEL_STREAM_V2 = (5 << 16),
 
 	DSI_PSCON_CUSTOM_HEADER_SHIFT = 26,
 };
diff --git a/src/soc/mediatek/mt8196/Kconfig b/src/soc/mediatek/mt8196/Kconfig
index 90c85007ef..c6eedf9341 100644
--- a/src/soc/mediatek/mt8196/Kconfig
+++ b/src/soc/mediatek/mt8196/Kconfig
@@ -18,6 +18,7 @@ config SOC_MEDIATEK_MT8196
 	select ARM64_USE_ARCH_TIMER
 	select PCI
 	select EARLY_MMU_INIT
+	select MEDIATEK_DSI_DUAL_CHANNEL
 
 if SOC_MEDIATEK_MT8196
 
diff --git a/src/soc/mediatek/mt8196/Makefile.mk b/src/soc/mediatek/mt8196/Makefile.mk
index cc7ec0ad11..47f9592bc8 100644
--- a/src/soc/mediatek/mt8196/Makefile.mk
+++ b/src/soc/mediatek/mt8196/Makefile.mk
@@ -64,12 +64,14 @@ ramstage-y += ../common/dp/dp_intf_v2.c
 ramstage-y += ../common/dp/dptx_common.c ../common/dp/dptx_v2.c dptx.c
 ramstage-y += ../common/dp/dptx_hal_common.c ../common/dp/dptx_hal_v2.c dptx_hal.c
 ramstage-y += ../common/dramc_info.c
+ramstage-y += ../common/dsi_common.c dsi.c
 ramstage-y += ../common/early_init.c
 ramstage-y += ../common/emi.c
 ramstage-y += gpueb.c
 ramstage-y += l2c_ops.c
 ramstage-y += ../common/mcu.c mcupm.c
 ramstage-y += ../common/mmu_operations.c
+ramstage-y += ../common/mtk_mipi_dphy.c mtk_mipi_dphy.c
 ramstage-$(CONFIG_PCI) += ../common/pcie.c pcie.c
 ramstage-$(CONFIG_COMMONLIB_STORAGE_MMC) += msdc.c
 ramstage-y += ../common/mt6363.c mt6363.c
diff --git a/src/soc/mediatek/mt8196/ddp.c b/src/soc/mediatek/mt8196/ddp.c
index 380d52f171..ba317d4e79 100644
--- a/src/soc/mediatek/mt8196/ddp.c
+++ b/src/soc/mediatek/mt8196/ddp.c
@@ -11,6 +11,30 @@
 #define SIZE(w, h) ((u32)(h) << 16 | (w))
 #define DUAL_PIPE(path) ((path) == DISP_PATH_DUAL_MIPI)
 
+#define DSC_EN					BIT(0)
+#define DSC_DUAL_INOUT				BIT(2)
+#define DSC_IN_SRC_SEL				BIT(3)
+#define DSC_BYPASS				BIT(4)
+#define DSC_RELAY				BIT(5)
+#define DSC_PT_MEM_EN                           BIT(7)
+#define DSC_EMPTY_FLAG_SEL			GENMASK(15, 14)
+#define DSC_EMPTY_FLAG_ALWAYS_LOW		BIT(15)
+#define DSC_UFOE_SEL				BIT(16)
+#define DSC_ZERO_FIFO_STALL_DISABLE		BIT(20)
+
+#define DSC_INTEN_SEL				GENMASK(6, 0)
+#define DSC_ZERO_FIFO				BIT(2)
+
+#define DSC_INTACK_SEL				GENMASK(6, 0)
+#define DSC_INTACK_BUF_UNDERFLOW		BIT(6)
+
+#define DSC_PIC_PREPAD_HEIGHT_SEL		GENMASK(15, 0)
+#define DSC_PIC_PREPAD_WIDTH_SEL		GENMASK(31, 16)
+
+#define ALIGN_PADDING(V, N)	(((N) - ((V) % (N))) % (N))
+/* Provide default value for x == 0. */
+#define DEF(x, default) ((x) == 0 ? (default) : (x))
+
 struct disp_pipe_regs {
 	struct disp_mdp_rsz_regs *const mdp_rsz;
 	struct disp_tdshp_regs *const tdshp;
@@ -44,6 +68,245 @@ static const struct disp_pipe_regs disp_pipe1_regs = {
 	.dsc      = disp_dsc3_reg,
 };
 
+static void dsc_configure_registers(struct disp_dsc_regs *reg, u16 w, u16 h,
+				    const struct dsc_config *dsc_cfg)
+{
+	u32 init_delay_limit, init_delay_height;
+	u32 pic_group_width, pic_height_ext_num;
+	u32 slice_group_width;
+	u32 pad_num;
+	u32 slice_mode;
+	u32 dsc_cfg_mode = 0x22;
+	u32 mask;
+	u32 val;
+	u32 rgb_swap = 0;
+
+	if (dsc_cfg->bits_per_component == 0xA)
+		dsc_cfg_mode = 0x828;
+
+	assert(dsc_cfg->pic_width > 0);
+	assert(dsc_cfg->pic_width >= dsc_cfg->slice_width);
+	assert(dsc_cfg->slice_width > 0);
+	slice_mode = dsc_cfg->pic_width / dsc_cfg->slice_width - 1;
+	pic_group_width = DIV_ROUND_UP(dsc_cfg->pic_width, 3);
+	pic_height_ext_num = DIV_ROUND_UP(h, dsc_cfg->slice_height);
+	slice_group_width = DIV_ROUND_UP(dsc_cfg->slice_width, 3);
+	pad_num = ALIGN_PADDING(dsc_cfg->slice_chunk_size * (slice_mode + 1), 3);
+	init_delay_limit = DIV_ROUND_UP(dsc_cfg->initial_xmit_delay, 3);
+	init_delay_limit = DIV_ROUND_UP((128 + init_delay_limit) * 3, dsc_cfg->slice_width);
+	init_delay_height = MIN(15, init_delay_limit);
+
+	mask = DSC_EN | DSC_DUAL_INOUT | DSC_IN_SRC_SEL | DSC_BYPASS | DSC_RELAY |
+	       DSC_PT_MEM_EN | DSC_EMPTY_FLAG_SEL | DSC_UFOE_SEL |
+	       DSC_ZERO_FIFO_STALL_DISABLE;
+	val = DSC_PT_MEM_EN | DSC_EMPTY_FLAG_ALWAYS_LOW |  DSC_UFOE_SEL |
+	      DSC_ZERO_FIFO_STALL_DISABLE;
+
+	clrsetbits32(&reg->dsc_con, mask, val);
+	clrsetbits32(&reg->dsc_inten, DSC_INTEN_SEL, 0x7F);
+	clrsetbits32(&reg->dsc_intack, DSC_INTACK_SEL, DSC_INTACK_BUF_UNDERFLOW);
+
+	write32(&reg->dsc_spr, 0x0);
+
+	val = w | (pic_group_width - 1) << 16;
+	write32(&reg->pic_w, val);
+
+	val = (h - 1) | (pic_height_ext_num * dsc_cfg->slice_height - 1) << 16;
+	write32(&reg->pic_h, val);
+
+	val = dsc_cfg->slice_width | (slice_group_width - 1) << 16;
+	write32(&reg->dsc_slice_w, val);
+
+	val = (dsc_cfg->slice_height - 1) | (pic_height_ext_num - 1) << 16 |
+	      (dsc_cfg->slice_width % 3) << 30;
+	write32(&reg->dsc_slice_h, val);
+
+	val = dsc_cfg->slice_chunk_size |
+	      (((dsc_cfg->slice_chunk_size << slice_mode) + 2) / 3) << 16;
+	write32(&reg->chunk_size, val);
+
+	mask = GENMASK(23, 0);
+	val = dsc_cfg->slice_chunk_size * dsc_cfg->slice_height;
+	clrsetbits32(&reg->dsc_buf_size, mask, val);
+
+	mask = BIT(0) | BIT(2) | GENMASK(11, 8);
+	val = slice_mode | rgb_swap << 2 | init_delay_height << 8;
+	clrsetbits32(&reg->dsc_mode, mask, val);
+
+	write32(&reg->dsc_cfg, dsc_cfg_mode);
+
+	mask = GENMASK(2, 0);
+	val = pad_num;
+	clrsetbits32(&reg->dsc_pad, mask, val);
+
+	val = dsc_cfg->slice_width | dsc_cfg->pic_width << 16;
+	write32(&reg->dsc_enc_width, val);
+
+	mask = DSC_PIC_PREPAD_HEIGHT_SEL | DSC_PIC_PREPAD_WIDTH_SEL;
+	val = h | w << 16;
+	clrsetbits32(&reg->dsc_pic_pre_pad_size, mask, val);
+
+	setbits32(&reg->dsc_dbg_con, BIT(9));
+
+	write32(&reg->dsc_obuf, 0x410);
+
+	DEFINE_BITFIELD(LINE_BUF_DEPTH, 3, 0)
+	DEFINE_BITFIELD(BITS_PER_COMPONENT, 7, 4)
+	DEFINE_BITFIELD(BITS_PER_PIXEL, 17, 8)
+	DEFINE_BIT(CONVERT_RGB, 18)
+	DEFINE_BIT(BLOCK_PRED_ENABLE, 19)
+	SET32_BITFIELDS(&reg->dsc_pps[0],
+			LINE_BUF_DEPTH, DEF(dsc_cfg->line_buf_depth, 0x9),
+			BITS_PER_COMPONENT, DEF(dsc_cfg->bits_per_component, 0x8),
+			BITS_PER_PIXEL, DEF(dsc_cfg->bits_per_pixel, 0x80),
+			CONVERT_RGB, DEF((u8)dsc_cfg->convert_rgb, 1),
+			BLOCK_PRED_ENABLE, DEF((u8)dsc_cfg->block_pred_enable, 0));
+
+	DEFINE_BITFIELD(INITIAL_DEC_DELAY, 31, 16)
+	DEFINE_BITFIELD(INITIAL_XMIT_DELAY, 15, 0)
+	WRITE32_BITFIELDS(&reg->dsc_pps[1],
+			  INITIAL_DEC_DELAY, DEF(dsc_cfg->initial_dec_delay, 0x268),
+			  INITIAL_XMIT_DELAY, DEF(dsc_cfg->initial_xmit_delay, 0x200));
+
+	DEFINE_BITFIELD(INITIAL_SCALE_VALUE, 15, 0)
+	DEFINE_BITFIELD(SCALE_INCREMENT_INTERVAL, 31, 16)
+	WRITE32_BITFIELDS(&reg->dsc_pps[2],
+			  INITIAL_SCALE_VALUE, DEF(dsc_cfg->initial_scale_value, 0x20),
+			  SCALE_INCREMENT_INTERVAL,
+			  DEF(dsc_cfg->scale_increment_interval, 0x387));
+
+	DEFINE_BITFIELD(FIRST_LINE_BPG_OFFSET, 31, 16)
+	DEFINE_BITFIELD(SCALE_DECREMENT_INTERVAL, 15, 0)
+	WRITE32_BITFIELDS(&reg->dsc_pps[3],
+			  FIRST_LINE_BPG_OFFSET, DEF(dsc_cfg->first_line_bpg_offset, 0xc),
+			  SCALE_DECREMENT_INTERVAL,
+			  DEF(dsc_cfg->scale_decrement_interval, 0xa));
+
+	DEFINE_BITFIELD(NFL_BPG_OFFSET, 15, 0)
+	DEFINE_BITFIELD(SLICE_BPG_OFFSET, 31, 16)
+	WRITE32_BITFIELDS(&reg->dsc_pps[4],
+			  NFL_BPG_OFFSET, DEF(dsc_cfg->nfl_bpg_offset, 0x319),
+			  SLICE_BPG_OFFSET, DEF(dsc_cfg->slice_bpg_offset, 0x263));
+
+	DEFINE_BITFIELD(INITIAL_OFFSET, 15, 0)
+	DEFINE_BITFIELD(FINAL_OFFSET, 31, 16)
+	WRITE32_BITFIELDS(&reg->dsc_pps[5],
+			  INITIAL_OFFSET, DEF(dsc_cfg->initial_offset, 0x1800),
+			  FINAL_OFFSET, DEF(dsc_cfg->final_offset, 0x10f0));
+
+	DEFINE_BITFIELD(FLATNESS_MIN_QP, 4, 0)
+	DEFINE_BITFIELD(FLATNESS_MAX_QP, 12, 8)
+	DEFINE_BITFIELD(RC_MODEL_SIZE, 31, 16)
+	SET32_BITFIELDS(&reg->dsc_pps[6],
+			FLATNESS_MIN_QP, DEF(dsc_cfg->flatness_min_qp, 0x3),
+			FLATNESS_MAX_QP, DEF(dsc_cfg->flatness_max_qp, 0xc),
+			RC_MODEL_SIZE, DEF(dsc_cfg->rc_model_size, 0x2000));
+
+	DEFINE_BITFIELD(RC_TGT_OFFSET_LOW, 31, 28)
+	DEFINE_BITFIELD(RC_TGT_OFFSET_HIGH, 27, 24)
+	DEFINE_BITFIELD(RC_QUANT_INCR_LIMIT1, 20, 16)
+	DEFINE_BITFIELD(RC_QUANT_INCR_LIMIT0, 12, 8)
+	DEFINE_BITFIELD(RC_EDGE_FACTOR, 7, 0)
+	WRITE32_BITFIELDS(&reg->dsc_pps[7],
+			  RC_TGT_OFFSET_LOW, dsc_cfg->rc_tgt_offset_low,
+			  RC_TGT_OFFSET_HIGH, dsc_cfg->rc_tgt_offset_high,
+			  RC_QUANT_INCR_LIMIT1, dsc_cfg->rc_quant_incr_limit1,
+			  RC_QUANT_INCR_LIMIT0, dsc_cfg->rc_quant_incr_limit0,
+			  RC_EDGE_FACTOR, dsc_cfg->rc_edge_factor);
+
+	DEFINE_BITFIELD(RC_BUF_THRESH_3, 31, 24)
+	DEFINE_BITFIELD(RC_BUF_THRESH_2, 23, 16)
+	DEFINE_BITFIELD(RC_BUF_THRESH_1, 15, 8)
+	DEFINE_BITFIELD(RC_BUF_THRESH_0, 7, 0)
+	WRITE32_BITFIELDS(&reg->dsc_pps[8],
+			  RC_BUF_THRESH_3, dsc_cfg->rc_buf_thresh[3],
+			  RC_BUF_THRESH_2, dsc_cfg->rc_buf_thresh[2],
+			  RC_BUF_THRESH_1, dsc_cfg->rc_buf_thresh[1],
+			  RC_BUF_THRESH_0, dsc_cfg->rc_buf_thresh[0]);
+
+	DEFINE_BITFIELD(RC_BUF_THRESH_7, 31, 24)
+	DEFINE_BITFIELD(RC_BUF_THRESH_6, 23, 16)
+	DEFINE_BITFIELD(RC_BUF_THRESH_5, 15, 8)
+	DEFINE_BITFIELD(RC_BUF_THRESH_4, 7, 0)
+	WRITE32_BITFIELDS(&reg->dsc_pps[9],
+			  RC_BUF_THRESH_7, dsc_cfg->rc_buf_thresh[7],
+			  RC_BUF_THRESH_6, dsc_cfg->rc_buf_thresh[6],
+			  RC_BUF_THRESH_5, dsc_cfg->rc_buf_thresh[5],
+			  RC_BUF_THRESH_4, dsc_cfg->rc_buf_thresh[4]);
+
+	DEFINE_BITFIELD(RC_BUF_THRESH_11, 31, 24)
+	DEFINE_BITFIELD(RC_BUF_THRESH_10, 23, 16)
+	DEFINE_BITFIELD(RC_BUF_THRESH_9, 15, 8)
+	DEFINE_BITFIELD(RC_BUF_THRESH_8, 7, 0)
+	WRITE32_BITFIELDS(&reg->dsc_pps[10],
+			  RC_BUF_THRESH_11, dsc_cfg->rc_buf_thresh[11],
+			  RC_BUF_THRESH_10, dsc_cfg->rc_buf_thresh[10],
+			  RC_BUF_THRESH_9, dsc_cfg->rc_buf_thresh[9],
+			  RC_BUF_THRESH_8, dsc_cfg->rc_buf_thresh[8]);
+
+	DEFINE_BITFIELD(RC_BUF_THRESH_13, 15, 8)
+	DEFINE_BITFIELD(RC_BUF_THRESH_12, 7, 0)
+	WRITE32_BITFIELDS(&reg->dsc_pps[11],
+			  RC_BUF_THRESH_13, dsc_cfg->rc_buf_thresh[13],
+			  RC_BUF_THRESH_12, dsc_cfg->rc_buf_thresh[12]);
+
+	DEFINE_BITFIELD(RC_RANGE_BPG_OFFSET_ODD, 31, 26)
+	DEFINE_BITFIELD(RC_RANGE_MAX_QP_ODD, 25, 21)
+	DEFINE_BITFIELD(RC_RANGE_MIN_QP_ODD, 20, 16)
+	DEFINE_BITFIELD(RC_RANGE_BPG_OFFSET_EVEN, 15, 10)
+	DEFINE_BITFIELD(RC_RANGE_MAX_QP_EVEN, 9, 5)
+	DEFINE_BITFIELD(RC_RANGE_MIN_QP_EVEN, 4, 0)
+	for (int i = 0; i < 7; i++) {
+		WRITE32_BITFIELDS(&reg->dsc_pps_rc_range_params[i],
+				  RC_RANGE_BPG_OFFSET_ODD,
+				  dsc_cfg->rc_range_params[2 * i + 1].range_bpg_offset,
+				  RC_RANGE_MAX_QP_ODD,
+				  dsc_cfg->rc_range_params[2 * i + 1].range_max_qp,
+				  RC_RANGE_MIN_QP_ODD,
+				  dsc_cfg->rc_range_params[2 * i + 1].range_min_qp,
+				  RC_RANGE_BPG_OFFSET_EVEN,
+				  dsc_cfg->rc_range_params[2 * i].range_bpg_offset,
+				  RC_RANGE_MAX_QP_EVEN,
+				  dsc_cfg->rc_range_params[2 * i].range_max_qp,
+				  RC_RANGE_MIN_QP_EVEN,
+				  dsc_cfg->rc_range_params[2 * i].range_min_qp);
+	}
+	/* Special case for the last register */
+	WRITE32_BITFIELDS(&reg->dsc_pps_rc_range_params[7],
+			  RC_RANGE_BPG_OFFSET_EVEN,
+			  dsc_cfg->rc_range_params[14].range_bpg_offset,
+			  RC_RANGE_MAX_QP_EVEN, dsc_cfg->rc_range_params[14].range_max_qp,
+			  RC_RANGE_MIN_QP_EVEN, dsc_cfg->rc_range_params[14].range_min_qp);
+
+	if (dsc_cfg->dsc_version_minor == 1)
+		write32(&reg->dsc_shadow, 0x20);
+	else if (dsc_cfg->dsc_version_minor == 2)
+		write32(&reg->dsc_shadow, 0x40);
+	else
+		printk(BIOS_WARNING, "%s : wrong version minor:%d\n", __func__,
+		       dsc_cfg->dsc_version_minor);
+}
+
+static void dsc_config(struct disp_dsc_regs *reg, u16 w, u16 h,
+		       const struct dsc_config *dsc_cfg)
+{
+	bool dsc_enable;
+
+	dsc_enable = (dsc_cfg && dsc_cfg->dsc_version_major);
+	printk(BIOS_INFO, "%s: w:%d, h:%d, dsc enable:%d\n",  __func__,  w, h, dsc_enable);
+
+	if (!dsc_enable) {
+		setbits32(&reg->dsc_con, DSC_RELAY);
+		clrsetbits32(&reg->chunk_size, GENMASK(31, 16), w << 16);
+		clrsetbits32(&reg->pic_w, GENMASK(15, 0), w);
+		clrsetbits32(&reg->pic_h, GENMASK(15, 0), h);
+		printk(BIOS_INFO, "%s: DSC_relay mode\n", __func__);
+		return;
+	}
+
+	dsc_configure_registers(reg, w, h, dsc_cfg);
+}
+
 static void blender_config(struct blender *reg, u16 width, u16 height,
 			   enum mtk_disp_blender_layer type)
 {
@@ -157,17 +420,9 @@ static void dither_start(struct disp_dither_regs *reg)
 	setbits32(&reg->en, BIT(0));
 }
 
-static void dsc_config(struct disp_dsc_regs *reg, u16 width, u16 height)
-{
-	write32(&reg->dsc_con, BIT(5));
-	write32(&reg->pic_w, width);
-	write32(&reg->pic_h, height);
-	write32(&reg->chunk_size, width << 16);
-}
-
 static void dsc_start(struct disp_dsc_regs *reg)
 {
-	setbits32(&reg->dsc_con, BIT(0));
+	setbits32(&reg->dsc_con, DSC_EN);
 }
 
 static void ovlsys_path_connect(struct ovlsys_cfg *reg)
@@ -325,7 +580,8 @@ static void disp_config_blender(struct blender *const blenders[], size_t size, u
 	}
 }
 
-static void main_disp_path_setup(u16 width, u16 height, u32 vrefresh, enum disp_path_sel path)
+static void main_disp_path_setup(u16 width, u16 height, u32 vrefresh, enum disp_path_sel path,
+				 const struct dsc_config *dsc_cfg)
 {
 	u16 w = width;
 	size_t num_pipe = DUAL_PIPE(path) ? 2 : 1;
@@ -361,7 +617,7 @@ static void main_disp_path_setup(u16 width, u16 height, u32 vrefresh, enum disp_
 		postmask_start(pipes[i].postmask);
 		dither_config(pipes[i].dither, w, height);
 		dither_start(pipes[i].dither);
-		dsc_config(pipes[i].dsc, w, height);
+		dsc_config(pipes[i].dsc, w, height, dsc_cfg);
 		dsc_start(pipes[i].dsc);
 	}
 
@@ -435,7 +691,7 @@ void mtk_ddp_soc_mode_set(u32 fmt, u32 bpp, u32 width, u32 height, u32 vrefresh,
 	if (width > 0x1FFF || height > 0x1FFF)
 		printk(BIOS_WARNING, "%s: w/h: %d/%d exceed hw limit %u\n", __func__,
 		       width, height, 0x1FFF);
-	main_disp_path_setup(width, height, vrefresh, path);
+	main_disp_path_setup(width, height, vrefresh, path, dsc_config);
 	ovlsys_layer_config(fmt, bpp, width, height, path);
 }
 
diff --git a/src/soc/mediatek/mt8196/dsi.c b/src/soc/mediatek/mt8196/dsi.c
new file mode 100644
index 0000000000..6d6705986b
--- /dev/null
+++ b/src/soc/mediatek/mt8196/dsi.c
@@ -0,0 +1,88 @@
+/* SPDX-License-Identifier: GPL-2.0-only OR MIT */
+
+#include <assert.h>
+#include <delay.h>
+#include <device/mmio.h>
+#include <soc/dsi.h>
+#include <soc/pll.h>
+
+#define RG_DSI_PRD_REF_SEL		GENMASK(5, 0)
+#define RG_DSI_PRD_REF_MINI		0
+#define RG_DSI_PRD_REF_DEF		4
+#define RG_DSI_PRD_REF_MAX		7
+
+void mtk_dsi_configure_mipi_tx(struct mipi_tx_regs *mipi_tx_reg, u32 data_rate,
+			       u32 lanes, bool is_cphy)
+{
+	unsigned int txdiv0;
+	u64 pcw;
+
+	/* Select different voltage when different data rate */
+	if (data_rate < (u32)2500 * MHz) {
+		clrsetbits32(&mipi_tx_reg->pll_con1, RG_DSI_PRD_REF_SEL, RG_DSI_PRD_REF_MINI);
+		write32(&mipi_tx_reg->cdphy_preserved, 0xFFFF00F0);
+	} else {
+		clrsetbits32(&mipi_tx_reg->pll_con1, RG_DSI_PRD_REF_SEL, RG_DSI_PRD_REF_DEF);
+		write32(&mipi_tx_reg->cdphy_preserved, 0xFFFF0030);
+	}
+
+	if (data_rate >= 2000 * MHz) {
+		txdiv0 = 0;
+	} else if (data_rate >= 1000 * MHz) {
+		txdiv0 = 1;
+	} else if (data_rate >= 500 * MHz) {
+		txdiv0 = 2;
+	} else if (data_rate > 250 * MHz) {
+		/* (data_rate == 250MHz) is a special case that should go to the
+		   else-block below (txdiv0 = 4) */
+		txdiv0 = 3;
+	} else {
+		/* MIN = 125 */
+		assert(data_rate >= MTK_DSI_DATA_RATE_MIN_MHZ * MHz);
+		txdiv0 = 4;
+	}
+
+	if (CONFIG(MEDIATEK_DSI_CPHY) && is_cphy)
+		mtk_dsi_cphy_lane_sel_setting(mipi_tx_reg);
+
+	clrbits32(&mipi_tx_reg->pll_con4, BIT(11) | BIT(10));
+	setbits32(&mipi_tx_reg->pll_pwr, AD_DSI_PLL_SDM_PWR_ON);
+	udelay(30);
+	clrbits32(&mipi_tx_reg->pll_pwr, AD_DSI_PLL_SDM_ISO_EN);
+
+	pcw = (u64)(data_rate >> 1) * (1 << txdiv0);
+	pcw <<= 24;
+	pcw /= CLK26M_HZ;
+
+	write32(&mipi_tx_reg->pll_con0, pcw);
+	clrsetbits32(&mipi_tx_reg->pll_con1, RG_DSI_PLL_POSDIV, txdiv0 << 8);
+	udelay(30);
+	setbits32(&mipi_tx_reg->pll_con1, RG_DSI_PLL_EN);
+
+	/* BG_LPF_EN / BG_CORE_EN */
+	write32(&mipi_tx_reg->lane_con, 0x3FFF0180);
+	udelay(40);
+	write32(&mipi_tx_reg->lane_con, 0x3FFF00C0);
+
+	if (CONFIG(MEDIATEK_DSI_CPHY) && is_cphy)
+		mtk_dsi_cphy_enable(mipi_tx_reg);
+
+	/* Switch OFF each Lane */
+	clrbits32(&mipi_tx_reg->d0_sw_ctl_en, DSI_SW_CTL_EN);
+	clrbits32(&mipi_tx_reg->d1_sw_ctl_en, DSI_SW_CTL_EN);
+	clrbits32(&mipi_tx_reg->d2_sw_ctl_en, DSI_SW_CTL_EN);
+	clrbits32(&mipi_tx_reg->d3_sw_ctl_en, DSI_SW_CTL_EN);
+	clrbits32(&mipi_tx_reg->ck_sw_ctl_en, DSI_SW_CTL_EN);
+
+	if (CONFIG(MEDIATEK_DSI_CPHY) && is_cphy)
+		mtk_dsi_cphy_disable_ck_mode(mipi_tx_reg);
+	else
+		mtk_dsi_dphy_disable_ck_mode(mipi_tx_reg);
+}
+
+void mtk_dsi_reset(struct dsi_regs *dsi_reg)
+{
+	write32(&dsi_reg->dsi_shadow_ctrl, DSI_FORCE_COMMIT_ALWAYS);
+	write32(&dsi_reg->dsi_con_ctrl, 1);
+	write32(&dsi_reg->dsi_con_ctrl, 0);
+}
diff --git a/src/soc/mediatek/mt8196/include/soc/ddp.h b/src/soc/mediatek/mt8196/include/soc/ddp.h
index 2c91747345..5d0130842f 100644
--- a/src/soc/mediatek/mt8196/include/soc/ddp.h
+++ b/src/soc/mediatek/mt8196/include/soc/ddp.h
@@ -539,17 +539,55 @@ check_member(disp_postmask_regs, size, 0x30);
 
 struct disp_dsc_regs {
 	u32 dsc_con;
-	u32 reserved0x4[5];
+	u32 dsc_inten;
+	u32 dsc_intsta;
+	u32 dsc_intack;
+	u32 dsc_sta;
+	u32 dsc_spr;
 	u32 pic_w;
 	u32 pic_h;
-	u32 reserved0x20;
-	u32 reserved0x24;
+	u32 dsc_slice_w;
+	u32 dsc_slice_h;
 	u32 chunk_size;
+	u32 dsc_buf_size;
+	u32 dsc_mode;
+	u32 dsc_cfg;
+	u32 dsc_pad;
+	u32 dsc_enc_width;
+	u32 dsc_pic_pre_pad_size;
+	u32 dsc_pic_pre_pad_value;
+	u32 reserved0[6];
+	u32 dsc_dbg_con;
+	u32 dsc_cksm_mon0;
+	u32 dsc_cksm_mon1;
+	u32 dsc_resv;
+	u32 dsc_obuf;
+	u32 dsc_obuf_mon;
+	u32 dsc_mute_con;
+	u32 dsc_ddren;
+	u32 dsc_pps[12];
+	u32 dsc_pps_rc_range_params[8];
+	u32 reserved1[12];
+	u32 dsc_dbg[21];
+	u32 reserved2[3];
+	u32 dsc_enc_dbg[5];
+	u32 dsc_enc_cov;
+	u32 reserved3[34];
+	u32 dsc_shadow;
+	u32 reserved4[7];
+	u32 dsc_dummy;
+	u32 reserved5;
+	u32 shadow_ctrl;
+	u32 reserved6;
+	u32 dsc_up_inten;
+	u32 dsc_up_intsta;
+	u32 dsc_up_intack;
 };
-check_member(disp_dsc_regs, dsc_con, 0x0);
-check_member(disp_dsc_regs, pic_w, 0x18);
-check_member(disp_dsc_regs, pic_h, 0x1C);
-check_member(disp_dsc_regs, chunk_size, 0x28);
+check_member(disp_dsc_regs, dsc_slice_w, 0x20);
+check_member(disp_dsc_regs, dsc_dbg_con, 0x60);
+check_member(disp_dsc_regs, dsc_enc_cov, 0x174);
+check_member(disp_dsc_regs, dsc_shadow, 0x200);
+check_member(disp_dsc_regs, dsc_up_intack, 0x238);
 
 static struct disp_mdp_rsz_regs *const disp_mdp_rsz0_reg	= (void *)DISP_MDP_RSZ0_BASE;
 static struct disp_mdp_rsz_regs *const disp_mdp_rsz1_reg	= (void *)DISP_MDP_RSZ1_BASE;
diff --git a/src/soc/mediatek/mt8196/mtk_mipi_dphy.c b/src/soc/mediatek/mt8196/mtk_mipi_dphy.c
new file mode 100644
index 0000000000..62001ec254
--- /dev/null
+++ b/src/soc/mediatek/mt8196/mtk_mipi_dphy.c
@@ -0,0 +1,29 @@
+/* SPDX-License-Identifier: GPL-2.0-only OR MIT */
+
+#include <device/mmio.h>
+#include <soc/dsi.h>
+
+#define PHY_TIMING_DIV(x) (((x) / 8000) + 1)
+
+void mtk_dsi_dphy_timing_calculation(u32 data_rate_mhz, struct mtk_phy_timing *timing)
+{
+	u32 temp;
+	timing->lpx = ALIGN_UP(PHY_TIMING_DIV(80 * data_rate_mhz), 2);
+	timing->da_hs_prepare = ALIGN_UP(PHY_TIMING_DIV(59 * data_rate_mhz + 4 * 1000), 2);
+	timing->da_hs_zero = PHY_TIMING_DIV(163 * data_rate_mhz + 11 * 1000) -
+			     timing->da_hs_prepare;
+
+	temp = data_rate_mhz < 740 ? 443 : 420;
+	timing->da_hs_trail = PHY_TIMING_DIV(66 * data_rate_mhz + temp * 100);
+	timing->ta_go = 4 * timing->lpx;
+	timing->ta_sure = 3 * timing->lpx / 2;
+	timing->ta_get = 5 * timing->lpx;
+	timing->da_hs_exit = ALIGN_UP(PHY_TIMING_DIV(118 * data_rate_mhz), 2);
+	timing->da_hs_sync = 1;
+
+	timing->clk_hs_prepare = ALIGN_UP(PHY_TIMING_DIV(57 * data_rate_mhz), 2);
+	timing->clk_hs_post = PHY_TIMING_DIV(65 * data_rate_mhz + 53 * 1000);
+	timing->clk_hs_trail = PHY_TIMING_DIV(65 * data_rate_mhz + 52 * 1000);
+	timing->clk_hs_zero = PHY_TIMING_DIV(330 * data_rate_mhz) - timing->clk_hs_prepare;
+	timing->clk_hs_exit = PHY_TIMING_DIV(118 * data_rate_mhz);
+}

From 65833355ca36029eff45838068f32b6db8fb5972 Mon Sep 17 00:00:00 2001
From: Felix Singer <felixsinger@posteo.net>
Date: Thu, 18 Dec 2025 19:18:27 +0100
Subject: [PATCH 2868/3886] tests: Disable gcov warnings

Newer gcov/lcov versions shipped in CI container images throw a warning
and thus cause the CI to fail. It's unclear how to fix this warning at
the moment, but gcov isn't critical anyway. So disable this specific
warning for now, so that we can roll out new CI images.

Excluding file '/home/coreboot/node-root/workspace/test_coreboot/payloads/libpayload/tests/libcbfs/cbfs-lookup-test.c'
lcov: WARNING: (inconsistent) /home/coreboot/node-root/workspace/test_coreboot/payloads/libpayload/libcbfs/cbfs.c:79: unexecuted block on non-branch line with non-zero hit count.  Use "geninfo --rc geninfo_unexecuted_blocks=1 to set count to zero.
    (use "lcov --ignore-errors inconsistent,inconsistent ..." to suppress this warning)
Excluding file '/home/coreboot/node-root/workspace/test_coreboot/payloads/libpayload/tests/libcbfs/cbfs-lookup-test.c'

[snip]

Message summary:
  1 warning message:
    inconsistent: 1
genhtml: ERROR: (corrupt) unable to read trace file 'build/coverage/tests.info': genhtml: ERROR: (inconsistent) "/home/coreboot/node-root/workspace/test_coreboot/payloads/libpayload/libcbfs/cbfs.c":77: function 'cbfs_unmap' is not hit but line 79 is.
    To skip consistency checks, see the 'check_data_consistency' section in man lcovrc(5).
    (use "genhtml --ignore-errors inconsistent ..." to bypass this error)
    (use "genhtml --ignore-errors corrupt ..." to bypass this error)
make[1]: *** [tests/Makefile.mk:277: coverage-report] Error 1
make: *** [util/testing/Makefile.mk:103: what-jenkins-does] Error 2

Change-Id: I2c52c53fbe856a8bca062f34c576fdfda3818f2b
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90554
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
---
 payloads/libpayload/tests/Makefile.mk | 2 +-
 tests/Makefile.mk                     | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/payloads/libpayload/tests/Makefile.mk b/payloads/libpayload/tests/Makefile.mk
index a6cee5f480..9ab8c3b71c 100644
--- a/payloads/libpayload/tests/Makefile.mk
+++ b/payloads/libpayload/tests/Makefile.mk
@@ -273,7 +273,7 @@ clean-junit.xml-unit-tests:
 
 ifeq ($(COV),1)
 coverage-report:
-	lcov -o $(testobj)/tests.info -c -d $(testobj) --exclude '$(testsrc)/*'
+	lcov --ignore-errors inconsistent -o $(testobj)/tests.info -c -d $(testobj) --exclude '$(testsrc)/*'
 	genhtml -q -o $(coverage-dir) -t "coreboot unit tests" -s $(testobj)/tests.info
 
 clean-coverage-report:
diff --git a/tests/Makefile.mk b/tests/Makefile.mk
index f3f122dd38..08ba3dc3cb 100644
--- a/tests/Makefile.mk
+++ b/tests/Makefile.mk
@@ -149,7 +149,7 @@ clean-junit.xml-unit-tests:
 ifeq ($(COV),1)
 coverage-report:
 	lcov -o $(testobj)/tests.info -c -d $(testobj) --exclude '$(testsrc)/*'
-	genhtml -q -o $(testobj)/$(coverage_dir) -t "coreboot unit tests" \
+	genhtml --ignore-errors inconsistent,corrupt -q -o $(testobj)/$(coverage_dir) -t "coreboot unit tests" \
 	-s $(testobj)/tests.info
 
 clean-coverage-report:

From d528561130af22a2bc73ced71cd43df2ac5faeed Mon Sep 17 00:00:00 2001
From: Kapil Porwal <kapilporwal@google.com>
Date: Thu, 18 Dec 2025 19:26:31 +0530
Subject: [PATCH 2869/3886] mb/google/bluey: Use PMIC for off-mode detection

Refactor boot mode detection to use is_pon_on_ac() for identifying
off-mode charging, relying on the underlying PMIC registers.
Additionally, introduce is_pd_sync_required() to centralize logic
for enabling Power Delivery negotiation during off-mode, low
battery, or no-battery boot scenarios.

BUG=b:457566143
TEST=Verify different boot modes on Google/Quenbi.

Change-Id: I7bdece2fc920310f3b1c59a1a6b90cf3bd03e3d9
Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90551
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jayvik Desai <jayvik@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
---
 src/mainboard/google/bluey/romstage.c | 35 ++++++++++++++++++---------
 1 file changed, 24 insertions(+), 11 deletions(-)

diff --git a/src/mainboard/google/bluey/romstage.c b/src/mainboard/google/bluey/romstage.c
index 3c5b307fd8..e21777b715 100644
--- a/src/mainboard/google/bluey/romstage.c
+++ b/src/mainboard/google/bluey/romstage.c
@@ -8,6 +8,7 @@
 #include <ec/google/chromeec/ec.h>
 #include <gpio.h>
 #include <soc/aop_common.h>
+#include <soc/pmic.h>
 #include <soc/qclib_common.h>
 #include <soc/shrm.h>
 #include <soc/watchdog.h>
@@ -27,16 +28,7 @@ static enum boot_mode_t boot_mode = LB_BOOT_MODE_NORMAL;
  */
 bool is_off_mode(void)
 {
-	const uint64_t manual_pwron_event_mask =
-		(EC_HOST_EVENT_MASK(EC_HOST_EVENT_POWER_BUTTON) |
-		EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN));
-	uint64_t ec_events = google_chromeec_get_events_b();
-
-	if (!(ec_events & manual_pwron_event_mask) &&
-		(ec_events & EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_CONNECTED)))
-		return true;
-
-	return false;
+	return is_pon_on_ac();
 }
 
 static enum boot_mode_t set_boot_mode(void)
@@ -53,12 +45,32 @@ static enum boot_mode_t set_boot_mode(void)
 	return boot_mode_new;
 }
 
+static bool is_pd_sync_required(void)
+{
+	if (!CONFIG(EC_GOOGLE_CHROMEEC))
+		return false;
+
+	const uint64_t manual_pwron_event_mask =
+		(EC_HOST_EVENT_MASK(EC_HOST_EVENT_POWER_BUTTON) |
+		EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN));
+	uint64_t ec_events = google_chromeec_get_events_b();
+
+	if (!(ec_events & manual_pwron_event_mask) &&
+		(ec_events & EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_CONNECTED)))
+		return true;
+
+	if (google_chromeec_is_below_critical_threshold() || !google_chromeec_is_battery_present())
+		return true;
+
+	return false;
+}
+
 int qclib_mainboard_override(struct qclib_cb_if_table *table)
 {
 	if (!CONFIG(EC_GOOGLE_CHROMEEC))
 		return 0;
 
-	if ((set_boot_mode() != LB_BOOT_MODE_NORMAL) || !google_chromeec_is_battery_present())
+	if (is_pd_sync_required())
 		table->global_attributes |= QCLIB_GA_ENABLE_PD_NEGOTIATION;
 	else
 		table->global_attributes &= ~QCLIB_GA_ENABLE_PD_NEGOTIATION;
@@ -75,6 +87,7 @@ void platform_romstage_main(void)
 	/* QCLib: DDR init & train */
 	qclib_load_and_run();
 
+	/* Underlying PMIC registers are accessible only at this point */
 	set_boot_mode();
 
 	aop_fw_load_reset();

From d1e1003217c764ebf27428066cac974ba78070da Mon Sep 17 00:00:00 2001
From: Zheng Li <lizheng@huaqin.corp-partner.google.com>
Date: Wed, 19 Nov 2025 11:34:33 +0800
Subject: [PATCH 2870/3886] spd/lp5: Add SPD for MT62F2G32D4DS-031RFWT:C

Add MT62F2G32D4DS-031RFWT:C  in the memory_parts.json and re-generate
the SPD.

Micron: MT62F2G32D4DS-031RFWT:C

BUG=b:447273470
TEST=util/spd_tools/bin/spd_gen spd/lp5/memory_parts.json lp5

Change-Id: I2dc0151db31ed07c61454e800d539c9b546a1ea7
Signed-off-by: Zheng Li <lizheng@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90109
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kun Liu <liukun11@huaqin.corp-partner.google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
---
 spd/lp5/memory_parts.json                      | 10 ++++++++++
 spd/lp5/set-0/parts_spd_manifest.generated.txt |  1 +
 spd/lp5/set-1/parts_spd_manifest.generated.txt |  1 +
 3 files changed, 12 insertions(+)

diff --git a/spd/lp5/memory_parts.json b/spd/lp5/memory_parts.json
index c012c2eb50..bb725fcb73 100644
--- a/spd/lp5/memory_parts.json
+++ b/spd/lp5/memory_parts.json
@@ -413,6 +413,16 @@
             "ranksPerChannel": 1,
             "speedMbps": 6400
        }
+    },
+    {
+        "name":  "MT62F2G32D4DS-031RF WT:C",
+        "attribs": {
+            "densityPerDieGb": 16,
+            "diesPerPackage": 4,
+            "bitWidthPerChannel": 16,
+            "ranksPerChannel": 2,
+            "speedMbps": 6400
+        }
     }
     ]
 }
diff --git a/spd/lp5/set-0/parts_spd_manifest.generated.txt b/spd/lp5/set-0/parts_spd_manifest.generated.txt
index 9566fc2752..7d3c3f378a 100644
--- a/spd/lp5/set-0/parts_spd_manifest.generated.txt
+++ b/spd/lp5/set-0/parts_spd_manifest.generated.txt
@@ -40,3 +40,4 @@ K3KLALA0EM-MGCU,spd-13.hex
 MT62F1G32D2DS-020 WT:D,spd-11.hex
 K3KL8L80EM-MGCV,spd-11.hex
 MT62F1G32D2DS-031RF WT:C,spd-3.hex
+MT62F2G32D4DS-031RF WT:C,spd-6.hex
diff --git a/spd/lp5/set-1/parts_spd_manifest.generated.txt b/spd/lp5/set-1/parts_spd_manifest.generated.txt
index 9566fc2752..7d3c3f378a 100644
--- a/spd/lp5/set-1/parts_spd_manifest.generated.txt
+++ b/spd/lp5/set-1/parts_spd_manifest.generated.txt
@@ -40,3 +40,4 @@ K3KLALA0EM-MGCU,spd-13.hex
 MT62F1G32D2DS-020 WT:D,spd-11.hex
 K3KL8L80EM-MGCV,spd-11.hex
 MT62F1G32D2DS-031RF WT:C,spd-3.hex
+MT62F2G32D4DS-031RF WT:C,spd-6.hex

From a3adf4898b32360f55689f64fead81e96c9b463e Mon Sep 17 00:00:00 2001
From: Zheng Li <lizheng@huaqin.corp-partner.google.com>
Date: Thu, 11 Dec 2025 10:53:46 +0800
Subject: [PATCH 2871/3886] mb/google/brya/var/pujjocento: Add 2 Micron modules
 to RAM id table

Add support for the new memory Micron MT62F1G32D2DS-031RF WT:C using
spd-3.hex, and MT62F2G32D4DS-031RF WT:C using spd-6.hex

DRAM Part Name                 ID to assign
K3KL6L60GM-MGCT                0 (0000)
H9JCNNNBK3MLYR-N6E             1 (0001)
H58G56CK8BX146                 2 (0010)
K3KL8L80CM-MGCT                3 (0011)
MT62F1G32D2DS-031RF WT:C       4 (0100)
MT62F2G32D4DS-031RF WT:C       5 (0101)

BUG=b:447273470
BRANCH=firmware-trulo-15217.771.B
TEST=util/spd_tools/bin/part_id_gen ADL lp5 \
src/mainboard/google/brya/variants/pujjocento/memory \
src/mainboard/google/brya/variants/pujjocento/memory/mem_parts_used.txt

Change-Id: Ica96fefb3fb8b18ed693383641960c67e128e7e7
Signed-off-by: Zheng Li <lizheng@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90454
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Kun Liu <liukun11@huaqin.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 .../google/brya/variants/pujjocento/memory/Makefile.mk          | 2 ++
 .../brya/variants/pujjocento/memory/dram_id.generated.txt       | 2 ++
 .../google/brya/variants/pujjocento/memory/mem_parts_used.txt   | 2 ++
 3 files changed, 6 insertions(+)

diff --git a/src/mainboard/google/brya/variants/pujjocento/memory/Makefile.mk b/src/mainboard/google/brya/variants/pujjocento/memory/Makefile.mk
index c60f5439fe..5c2e43e1aa 100644
--- a/src/mainboard/google/brya/variants/pujjocento/memory/Makefile.mk
+++ b/src/mainboard/google/brya/variants/pujjocento/memory/Makefile.mk
@@ -8,3 +8,5 @@ SPD_SOURCES += spd/lp5/set-0/spd-9.hex      # ID = 0(0b0000)  Parts = K3KL6L60GM
 SPD_SOURCES += spd/lp5/set-0/spd-1.hex      # ID = 1(0b0001)  Parts = H9JCNNNBK3MLYR-N6E
 SPD_SOURCES += spd/lp5/set-0/spd-11.hex      # ID = 2(0b0010)  Parts = H58G56CK8BX146
 SPD_SOURCES += spd/lp5/set-0/spd-7.hex      # ID = 3(0b0011)  Parts = K3KL8L80CM-MGCT
+SPD_SOURCES += spd/lp5/set-0/spd-3.hex      # ID = 4(0b0100)  Parts = MT62F1G32D2DS-031RF WT:C
+SPD_SOURCES += spd/lp5/set-0/spd-6.hex      # ID = 5(0b0101)  Parts = MT62F2G32D4DS-031RF WT:C
diff --git a/src/mainboard/google/brya/variants/pujjocento/memory/dram_id.generated.txt b/src/mainboard/google/brya/variants/pujjocento/memory/dram_id.generated.txt
index 94e605c7b2..d7e389d451 100644
--- a/src/mainboard/google/brya/variants/pujjocento/memory/dram_id.generated.txt
+++ b/src/mainboard/google/brya/variants/pujjocento/memory/dram_id.generated.txt
@@ -8,3 +8,5 @@ K3KL6L60GM-MGCT                0 (0000)
 H9JCNNNBK3MLYR-N6E             1 (0001)
 H58G56CK8BX146                 2 (0010)
 K3KL8L80CM-MGCT                3 (0011)
+MT62F1G32D2DS-031RF WT:C       4 (0100)
+MT62F2G32D4DS-031RF WT:C       5 (0101)
diff --git a/src/mainboard/google/brya/variants/pujjocento/memory/mem_parts_used.txt b/src/mainboard/google/brya/variants/pujjocento/memory/mem_parts_used.txt
index e38d99697d..6d5723fdbf 100644
--- a/src/mainboard/google/brya/variants/pujjocento/memory/mem_parts_used.txt
+++ b/src/mainboard/google/brya/variants/pujjocento/memory/mem_parts_used.txt
@@ -13,3 +13,5 @@ K3KL6L60GM-MGCT
 H9JCNNNBK3MLYR-N6E
 H58G56CK8BX146
 K3KL8L80CM-MGCT
+MT62F1G32D2DS-031RF WT:C
+MT62F2G32D4DS-031RF WT:C

From 76e963534602ac1a100a622e0cfc7e0ea3638839 Mon Sep 17 00:00:00 2001
From: Patrick Rudolph <patrick.rudolph@9elements.com>
Date: Tue, 2 Dec 2025 08:36:14 +0100
Subject: [PATCH 2872/3886] amdfwread: Parse and print directory sizes

Parse the directory table size field and print along walking
the PSP directory tables.

Example output:
Table: FW   Offset     Size
PSPL1: Dir  [0x00b10000-0x00b12000)
+-->PSPL1: 0x48 0x00b30000 0x00010000
    +-->PSPL2: Dir  [0x00030000-0x00081000)
        +-->PSPL2: 0x00 0x00040000 0x00000440

Change-Id: I355c301c83af25524353a2e980066ce78b01fc37
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90329
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
---
 util/amdfwtool/amdfwread.c | 96 +++++++++++++++++++++++++++++++++++---
 1 file changed, 90 insertions(+), 6 deletions(-)

diff --git a/util/amdfwtool/amdfwread.c b/util/amdfwtool/amdfwread.c
index ddd0bc3fb0..46884f1e48 100644
--- a/util/amdfwtool/amdfwread.c
+++ b/util/amdfwtool/amdfwread.c
@@ -113,6 +113,9 @@ static int read_psp_directory(FILE *fw, uint32_t offset, uint32_t expected_cooki
 		return 1;
 	}
 
+	if (!entries || !num_entries)
+		return 0;
+
 	/* Read the entries */
 	*num_entries = header->num_entries;
 	*entries = malloc(sizeof(psp_directory_entry) * header->num_entries);
@@ -148,6 +151,9 @@ static int read_bios_directory(FILE *fw, uint32_t offset, uint32_t expected_cook
 		return 1;
 	}
 
+	if (!entries || !num_entries)
+		return 0;
+
 	/* Read the entries */
 	*num_entries = header->num_entries;
 	*entries = malloc(sizeof(bios_directory_entry) * header->num_entries);
@@ -313,6 +319,64 @@ static int amdfw_bios_dir_walk(FILE *fw, uint32_t bios_offset, uint32_t cookie,
 	return 0;
 }
 
+/*
+ * Returns the size of the PSP directory.
+ *
+ * @param fw			File to operate on
+ * @param psp_offset		Relative offset to PSP directory
+ * @param cookie		Expected table cookie
+ * @param size			Where to write the size to
+ *
+ * @return 0 on success, or < 0 on error.
+ */
+static int amdfw_psp_dir_size(FILE *fw, uint32_t psp_offset, uint32_t cookie, uint32_t *size)
+{
+	psp_directory_header header;
+
+	if (!fw || !size)
+		return -1;
+
+	if (read_psp_directory(fw, psp_offset, cookie, &header, NULL, NULL) != 0)
+		return -1;
+
+	if (header.additional_info_fields.version == 1)
+		*size = header.additional_info_fields_v1.dir_size;
+	else
+		*size = header.additional_info_fields.dir_size;
+
+	*size *= TABLE_ALIGNMENT;
+	return 0;
+}
+
+/*
+ * Returns the size of the BIOS directory.
+ *
+ * @param fw			File to operate on
+ * @param bios_offset		Relative offset to BIOS directory
+ * @param cookie		Expected table cookie
+ * @param size			Where to write the size to
+ *
+ * @return 0 on success, or < 0 on error.
+ */
+static int amdfw_bios_dir_size(FILE *fw, uint32_t bios_offset, uint32_t cookie, uint32_t *size)
+{
+	bios_directory_hdr header;
+
+	if (!fw || !size)
+		return -1;
+
+	if (read_bios_directory(fw, bios_offset, cookie, &header, NULL, NULL) != 0)
+		return -1;
+
+	if (header.additional_info_fields.version == 1)
+		*size = header.additional_info_fields_v1.dir_size;
+	else
+		*size = header.additional_info_fields.dir_size;
+
+	*size *= TABLE_ALIGNMENT;
+	return 0;
+}
+
 static int amdfw_psp_dir_walk(FILE *fw, uint32_t psp_offset, uint32_t cookie, uint8_t level)
 {
 	psp_directory_entry *current_entries = NULL;
@@ -339,7 +403,7 @@ static int amdfw_psp_dir_walk(FILE *fw, uint32_t psp_offset, uint32_t cookie, ui
 		uint32_t type = current_entries[i].type;
 		uint64_t mode = current_entries[i].address_mode;
 		uint64_t addr = current_entries[i].addr;
-
+		uint32_t dir_size = 0;
 		if (dir_mode < 2)
 			mode = dir_mode;
 
@@ -365,6 +429,10 @@ static int amdfw_psp_dir_walk(FILE *fw, uint32_t psp_offset, uint32_t cookie, ui
 
 			l2_dir_offset = relative_offset(psp_offset, addr, mode);
 			printf("    %sPSPL2: Dir  0x%08x\n", indent, l2_dir_offset);
+			if (amdfw_psp_dir_size(fw, l2_dir_offset, PSPL2_COOKIE, &dir_size) == 0)
+				printf("    %sPSPL2: Dir  [0x%08x-0x%08x)\n", indent, l2_dir_offset, l2_dir_offset + dir_size);
+			else
+				printf("    %sPSPL2: Dir  @0x%08x\n", indent, l2_dir_offset);
 			amdfw_psp_dir_walk(fw, l2_dir_offset, PSPL2_COOKIE, level + 2);
 			break;
 
@@ -384,13 +452,19 @@ static int amdfw_psp_dir_walk(FILE *fw, uint32_t psp_offset, uint32_t cookie, ui
 			}
 
 			l2_dir_offset = ish_dir.pl2_location;
-			printf("    %sPSPL2: Dir  0x%08x\n", indent, l2_dir_offset);
+			if (amdfw_psp_dir_size(fw, l2_dir_offset, PSPL2_COOKIE, &dir_size) == 0)
+				printf("    %sPSPL2: Dir  [0x%08x-0x%08x)\n", indent, l2_dir_offset, l2_dir_offset + dir_size);
+			else
+				printf("    %sPSPL2: Dir  @0x%08x\n", indent, l2_dir_offset);
 			amdfw_psp_dir_walk(fw, l2_dir_offset, PSPL2_COOKIE, level + 2);
 			break;
 
 		case AMD_FW_BIOS_TABLE:
 			bios_dir_offset = relative_offset(psp_offset, addr, mode);
-			printf("    %sBIOSL2: Dir  0x%08x\n", indent, bios_dir_offset);
+			if (amdfw_bios_dir_size(fw, bios_dir_offset, BHDL2_COOKIE, &dir_size) == 0)
+				printf("    %sBIOSL2: Dir  [0x%08x-0x%08x)\n", indent, bios_dir_offset, bios_dir_offset + dir_size);
+			else
+				printf("    %sBIOSL2: Dir  @0x%08x\n", indent, bios_dir_offset);
 			amdfw_bios_dir_walk(fw, bios_dir_offset, BHDL2_COOKIE, level + 2);
 			break;
 
@@ -406,7 +480,7 @@ static int amdfw_psp_dir_walk(FILE *fw, uint32_t psp_offset, uint32_t cookie, ui
 
 static int list_amdfw_psp_dir(FILE *fw, const embedded_firmware *fw_header)
 {
-	uint32_t psp_offset = 0;
+	uint32_t psp_offset = 0, dir_size = 0;
 
 	/* 0xffffffff or 0x00000000 indicates that the offset is in new_psp_directory */
 	if (fw_header->psp_directory != 0xffffffff && fw_header->psp_directory != 0x00000000)
@@ -414,18 +488,28 @@ static int list_amdfw_psp_dir(FILE *fw, const embedded_firmware *fw_header)
 	else
 		psp_offset = fw_header->new_psp_directory;
 
-	printf("PSPL1: Dir  0x%08x\n", psp_offset);
+	if (amdfw_psp_dir_size(fw, psp_offset, PSP_COOKIE, &dir_size) == 0)
+		printf("PSPL1: Dir  [0x%08x-0x%08x)\n", psp_offset, psp_offset + dir_size);
+	else
+		printf("PSPL1: Dir  @0x%08x\n", psp_offset);
+
 	amdfw_psp_dir_walk(fw, psp_offset, PSP_COOKIE, 0);
 	return 0;
 }
 
 static int list_amdfw_bios_dir(FILE *fw, const embedded_firmware *fw_header)
 {
+	uint32_t dir_size = 0;
+
 	/* 0xffffffff or 0x00000000 implies that the SoC uses recovery A/B
 	   layout. Only BIOS L2 directory is present and that too as part of
 	   PSP L2 directory. */
 	if (fw_header->bios3_entry != 0xffffffff && fw_header->bios3_entry != 0x00000000) {
-		printf("BIOSL1: Dir  0x%08x\n", fw_header->bios3_entry);
+		if (amdfw_psp_dir_size(fw, fw_header->bios3_entry, BHD_COOKIE, &dir_size) == 0)
+			printf("BIOSL1: Dir  [0x%08x-0x%08x)\n", fw_header->bios3_entry, fw_header->bios3_entry + dir_size);
+		else
+			printf("BIOSL1: Dir  @0x%08x\n", fw_header->bios3_entry);
+
 		amdfw_bios_dir_walk(fw, fw_header->bios3_entry, BHD_COOKIE, 0);
 	}
 	return 0;

From 0302b2ee07782761f6efa8088af6ab930d1613a1 Mon Sep 17 00:00:00 2001
From: Patrick Rudolph <patrick.rudolph@9elements.com>
Date: Sat, 22 Nov 2025 11:47:16 +0100
Subject: [PATCH 2873/3886] lib/xxhash: Move to commonlib/bsd

Move the xxhash lib to commonlib/bsd folder so that it can be
easily included by tools. Update use of standard headers to
allow compilation on POSIX compatible systems as well.

Use the new xxhash lib in cbfstool over the existing duplicated
xxhash lib residing in lz4/lib.

Change-Id: I21041409d5b734cecf43294dcaf3bf17531dbc15
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89682
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/commonlib/Makefile.mk                     |   2 +
 .../bsd/include/commonlib/bsd}/xxhash.h       |   3 +-
 src/{lib => commonlib/bsd}/xxhash.c           |   3 +-
 src/drivers/mrc_cache/mrc_cache.c             |   2 +-
 src/lib/Makefile.mk                           |   3 -
 src/soc/amd/common/block/apob/apob_cache.c    |   2 +-
 util/cbfstool/cbfstool.c                      |   2 +-
 util/cbfstool/lz4/lib/lz4_xxhash.h            |  13 +
 util/cbfstool/lz4/lib/lz4frame.c              |   2 +-
 util/cbfstool/lz4/lib/xxhash.c                | 962 ------------------
 util/cbfstool/lz4/lib/xxhash.h                | 192 ----
 11 files changed, 22 insertions(+), 1164 deletions(-)
 rename src/{include => commonlib/bsd/include/commonlib/bsd}/xxhash.h (99%)
 rename src/{lib => commonlib/bsd}/xxhash.c (99%)
 create mode 100644 util/cbfstool/lz4/lib/lz4_xxhash.h
 delete mode 100644 util/cbfstool/lz4/lib/xxhash.c
 delete mode 100644 util/cbfstool/lz4/lib/xxhash.h

diff --git a/src/commonlib/Makefile.mk b/src/commonlib/Makefile.mk
index 91648c5170..44f63e1ea6 100644
--- a/src/commonlib/Makefile.mk
+++ b/src/commonlib/Makefile.mk
@@ -73,3 +73,5 @@ all-y += bsd/ipchksum.c
 decompressor-y += bsd/string.c
 smm-y += bsd/string.c
 all-y += bsd/string.c
+
+all-y += bsd/xxhash.c
diff --git a/src/include/xxhash.h b/src/commonlib/bsd/include/commonlib/bsd/xxhash.h
similarity index 99%
rename from src/include/xxhash.h
rename to src/commonlib/bsd/include/commonlib/bsd/xxhash.h
index f6340cb791..a859b67d8a 100644
--- a/src/include/xxhash.h
+++ b/src/commonlib/bsd/include/commonlib/bsd/xxhash.h
@@ -46,7 +46,8 @@
 #ifndef XXHASH_H
 #define XXHASH_H
 
-#include <types.h>
+#include <stdint.h>
+#include <stddef.h>
 
 /*-****************************
  * Simple Hash Functions
diff --git a/src/lib/xxhash.c b/src/commonlib/bsd/xxhash.c
similarity index 99%
rename from src/lib/xxhash.c
rename to src/commonlib/bsd/xxhash.c
index c14fb96815..e6c9d2edb7 100644
--- a/src/lib/xxhash.c
+++ b/src/commonlib/bsd/xxhash.c
@@ -9,10 +9,9 @@
  * - xxHash source repository: https://github.com/Cyan4973/xxHash
  */
 
-#include <arch/byteorder.h>
+#include <commonlib/bsd/xxhash.h>
 #include <endian.h>
 #include <string.h>
-#include <xxhash.h>
 
 /*-*************************************
  * Macros
diff --git a/src/drivers/mrc_cache/mrc_cache.c b/src/drivers/mrc_cache/mrc_cache.c
index a066fa8f3a..e6b1ed20a7 100644
--- a/src/drivers/mrc_cache/mrc_cache.c
+++ b/src/drivers/mrc_cache/mrc_cache.c
@@ -5,6 +5,7 @@
 #include <bootstate.h>
 #include <bootmode.h>
 #include <console/console.h>
+#include <commonlib/bsd/xxhash.h>
 #include <cbmem.h>
 #include <elog.h>
 #include <fmap.h>
@@ -14,7 +15,6 @@
 #include <security/vboot/mrc_cache_hash_tpm.h>
 #include <security/vboot/vboot_common.h>
 #include <spi_flash.h>
-#include <xxhash.h>
 
 #include "mrc_cache.h"
 
diff --git a/src/lib/Makefile.mk b/src/lib/Makefile.mk
index 073d9fbb68..9deefaf95b 100644
--- a/src/lib/Makefile.mk
+++ b/src/lib/Makefile.mk
@@ -275,9 +275,6 @@ postcar-y += crc_byte.c
 ramstage-y += crc_byte.c
 smm-y += crc_byte.c
 
-romstage-y += xxhash.c
-ramstage-y += xxhash.c
-
 postcar-y += bootmode.c
 postcar-y += boot_device.c
 postcar-y += cbfs.c
diff --git a/src/soc/amd/common/block/apob/apob_cache.c b/src/soc/amd/common/block/apob/apob_cache.c
index 713826a297..d70adfc5b2 100644
--- a/src/soc/amd/common/block/apob/apob_cache.c
+++ b/src/soc/amd/common/block/apob/apob_cache.c
@@ -7,6 +7,7 @@
 #include <bootstate.h>
 #include <commonlib/helpers.h>
 #include <commonlib/region.h>
+#include <commonlib/bsd/xxhash.h>
 #include <console/console.h>
 #include <fmap.h>
 #include <fmap_config.h>
@@ -16,7 +17,6 @@
 #include <thread.h>
 #include <timestamp.h>
 #include <types.h>
-#include <xxhash.h>
 
 #define DEFAULT_MRC_CACHE	"RW_MRC_CACHE"
 #define DEFAULT_MRC_CACHE_SIZE	FMAP_SECTION_RW_MRC_CACHE_SIZE
diff --git a/util/cbfstool/cbfstool.c b/util/cbfstool/cbfstool.c
index 1b9931063e..5555b57364 100644
--- a/util/cbfstool/cbfstool.c
+++ b/util/cbfstool/cbfstool.c
@@ -14,7 +14,7 @@
 #include "cbfs_sections.h"
 #include "elfparsing.h"
 #include "partitioned_file.h"
-#include "lz4/lib/xxhash.h"
+#include "lz4/lib/lz4_xxhash.h"
 #include <commonlib/bsd/cbfs_private.h>
 #include <commonlib/bsd/compression.h>
 #include <commonlib/bsd/metadata_hash.h>
diff --git a/util/cbfstool/lz4/lib/lz4_xxhash.h b/util/cbfstool/lz4/lib/lz4_xxhash.h
new file mode 100644
index 0000000000..2e380e4e20
--- /dev/null
+++ b/util/cbfstool/lz4/lib/lz4_xxhash.h
@@ -0,0 +1,13 @@
+#include <commonlib/bsd/xxhash.h>
+
+typedef struct xxh64_state XXH64_state_t;
+#define XXH64_update xxh64_update
+#define XXH64_reset  xxh64_reset
+#define XXH64_digest xxh64_digest
+#define XXH64 xxh64
+
+typedef struct xxh32_state XXH32_state_t;
+#define XXH32_update xxh32_update
+#define XXH32_reset  xxh32_reset
+#define XXH32_digest xxh32_digest
+#define XXH32 xxh32
diff --git a/util/cbfstool/lz4/lib/lz4frame.c b/util/cbfstool/lz4/lib/lz4frame.c
index aef508d8df..8aebc63cd3 100644
--- a/util/cbfstool/lz4/lib/lz4frame.c
+++ b/util/cbfstool/lz4/lib/lz4frame.c
@@ -62,7 +62,7 @@ You can contact the author at :
 #include "lz4frame_static.h"
 #include "lz4.h"
 #include "lz4hc.h"
-#include "xxhash.h"
+#include "lz4_xxhash.h"
 
 
 /**************************************
diff --git a/util/cbfstool/lz4/lib/xxhash.c b/util/cbfstool/lz4/lib/xxhash.c
deleted file mode 100644
index 0f896266f0..0000000000
--- a/util/cbfstool/lz4/lib/xxhash.c
+++ /dev/null
@@ -1,962 +0,0 @@
-/*
-xxHash - Fast Hash algorithm
-Copyright (C) 2012-2015, Yann Collet
-
-BSD 2-Clause License (http://www.opensource.org/licenses/bsd-license.php)
-
-Redistribution and use in source and binary forms, with or without
-modification, are permitted provided that the following conditions are
-met:
-
-* Redistributions of source code must retain the above copyright
-notice, this list of conditions and the following disclaimer.
-* Redistributions in binary form must reproduce the above
-copyright notice, this list of conditions and the following disclaimer
-in the documentation and/or other materials provided with the
-distribution.
-
-THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-"AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
-OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-
-You can contact the author at :
-- xxHash source repository : https://github.com/Cyan4973/xxHash
-*/
-
-
-/**************************************
-*  Tuning parameters
-**************************************/
-/* XXH_FORCE_MEMORY_ACCESS
- * By default, access to unaligned memory is controlled by `memcpy()`, which is safe and portable.
- * Unfortunately, on some target/compiler combinations, the generated assembly is sub-optimal.
- * The below switch allow to select different access method for improved performance.
- * Method 0 (default) : use `memcpy()`. Safe and portable.
- * Method 1 : `__packed` statement. It depends on compiler extension (ie, not portable).
- *            This method is safe if your compiler supports it, and *generally* as fast or faster than `memcpy`.
- * Method 2 : direct access. This method is portable but violate C standard.
- *            It can generate buggy code on targets which generate assembly depending on alignment.
- *            But in some circumstances, it's the only known way to get the most performance (ie GCC + ARMv6)
- * See http://stackoverflow.com/a/32095106/646947 for details.
- * Prefer these methods in priority order (0 > 1 > 2)
- */
-#ifndef XXH_FORCE_MEMORY_ACCESS   /* can be defined externally, on command line for example */
-#  if defined(__GNUC__) && ( defined(__ARM_ARCH_6__) || defined(__ARM_ARCH_6J__) || defined(__ARM_ARCH_6K__) || defined(__ARM_ARCH_6Z__) || defined(__ARM_ARCH_6ZK__) || defined(__ARM_ARCH_6T2__) )
-#    define XXH_FORCE_MEMORY_ACCESS 2
-#  elif defined(__INTEL_COMPILER) || \
-  (defined(__GNUC__) && ( defined(__ARM_ARCH_7__) || defined(__ARM_ARCH_7A__) || defined(__ARM_ARCH_7R__) || defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7S__) ))
-#    define XXH_FORCE_MEMORY_ACCESS 1
-#  endif
-#endif
-
-/* XXH_ACCEPT_NULL_INPUT_POINTER :
- * If the input pointer is a null pointer, xxHash default behavior is to trigger a memory access error, since it is a bad pointer.
- * When this option is enabled, xxHash output for null input pointers will be the same as a null-length input.
- * By default, this option is disabled. To enable it, uncomment below define :
- */
-/* #define XXH_ACCEPT_NULL_INPUT_POINTER 1 */
-
-/* XXH_FORCE_NATIVE_FORMAT :
- * By default, xxHash library provides endian-independent Hash values, based on little-endian convention.
- * Results are therefore identical for little-endian and big-endian CPU.
- * This comes at a performance cost for big-endian CPU, since some swapping is required to emulate little-endian format.
- * Should endian-independance be of no importance for your application, you may set the #define below to 1,
- * to improve speed for Big-endian CPU.
- * This option has no impact on Little_Endian CPU.
- */
-#define XXH_FORCE_NATIVE_FORMAT 0
-
-/* XXH_USELESS_ALIGN_BRANCH :
- * This is a minor performance trick, only useful with lots of very small keys.
- * It means : don't make a test between aligned/unaligned, because performance will be the same.
- * It saves one initial branch per hash.
- */
-#if defined(__i386) || defined(_M_IX86) || defined(__x86_64__) || defined(_M_X64)
-#  define XXH_USELESS_ALIGN_BRANCH 1
-#endif
-
-
-/**************************************
-*  Compiler Specific Options
-***************************************/
-#ifdef _MSC_VER    /* Visual Studio */
-#  pragma warning(disable : 4127)      /* disable: C4127: conditional expression is constant */
-#  define FORCE_INLINE static __forceinline
-#else
-#  if defined (__STDC_VERSION__) && __STDC_VERSION__ >= 199901L   /* C99 */
-#    ifdef __GNUC__
-#      define FORCE_INLINE static inline __attribute__((always_inline))
-#    else
-#      define FORCE_INLINE static inline
-#    endif
-#  else
-#    define FORCE_INLINE static
-#  endif /* __STDC_VERSION__ */
-#endif
-
-
-/**************************************
-*  Includes & Memory related functions
-***************************************/
-#include "xxhash.h"
-/* Modify the local functions below should you wish to use some other memory routines */
-/* for malloc(), free() */
-#include <stdlib.h>
-static void* XXH_malloc(size_t s) { return malloc(s); }
-static void  XXH_free  (void* p)  { free(p); }
-/* for memcpy() */
-#include <string.h>
-static void* XXH_memcpy(void* dest, const void* src, size_t size) { return memcpy(dest,src,size); }
-
-
-/**************************************
-*  Basic Types
-***************************************/
-#if defined (__STDC_VERSION__) && __STDC_VERSION__ >= 199901L   /* C99 */
-# include <stdint.h>
-  typedef uint8_t  BYTE;
-  typedef uint16_t U16;
-  typedef uint32_t U32;
-  typedef  int32_t S32;
-  typedef uint64_t U64;
-#else
-  typedef unsigned char      BYTE;
-  typedef unsigned short     U16;
-  typedef unsigned int       U32;
-  typedef   signed int       S32;
-  typedef unsigned long long U64;
-#endif
-
-
-#if (defined(XXH_FORCE_MEMORY_ACCESS) && (XXH_FORCE_MEMORY_ACCESS==2))
-
-/* Force direct memory access. Only works on CPU which support unaligned memory access in hardware */
-static U32 XXH_read32(const void* memPtr) { return *(const U32*) memPtr; }
-static U64 XXH_read64(const void* memPtr) { return *(const U64*) memPtr; }
-
-#elif (defined(XXH_FORCE_MEMORY_ACCESS) && (XXH_FORCE_MEMORY_ACCESS==1))
-
-/* __pack instructions are safer, but compiler specific, hence potentially problematic for some compilers */
-/* currently only defined for gcc and icc */
-typedef union { U32 u32; U64 u64; } __packed unalign;
-
-static U32 XXH_read32(const void* ptr) { return ((const unalign*)ptr)->u32; }
-static U64 XXH_read64(const void* ptr) { return ((const unalign*)ptr)->u64; }
-
-#else
-
-/* portable and safe solution. Generally efficient.
- * see : http://stackoverflow.com/a/32095106/646947
- */
-
-static U32 XXH_read32(const void* memPtr)
-{
-    U32 val;
-    memcpy(&val, memPtr, sizeof(val));
-    return val;
-}
-
-static U64 XXH_read64(const void* memPtr)
-{
-    U64 val;
-    memcpy(&val, memPtr, sizeof(val));
-    return val;
-}
-
-#endif // XXH_FORCE_DIRECT_MEMORY_ACCESS
-
-
-/******************************************
-*  Compiler-specific Functions and Macros
-******************************************/
-#define GCC_VERSION (__GNUC__ * 100 + __GNUC_MINOR__)
-
-/* Note : although _rotl exists for minGW (GCC under windows), performance seems poor */
-#if defined(_MSC_VER)
-#  define XXH_rotl32(x,r) _rotl(x,r)
-#  define XXH_rotl64(x,r) _rotl64(x,r)
-#else
-#  define XXH_rotl32(x,r) ((x << r) | (x >> (32 - r)))
-#  define XXH_rotl64(x,r) ((x << r) | (x >> (64 - r)))
-#endif
-
-#if defined(_MSC_VER)     /* Visual Studio */
-#  define XXH_swap32 _byteswap_ulong
-#  define XXH_swap64 _byteswap_uint64
-#elif GCC_VERSION >= 403
-#  define XXH_swap32 __builtin_bswap32
-#  define XXH_swap64 __builtin_bswap64
-#else
-static U32 XXH_swap32 (U32 x)
-{
-    return  ((x << 24) & 0xff000000 ) |
-            ((x <<  8) & 0x00ff0000 ) |
-            ((x >>  8) & 0x0000ff00 ) |
-            ((x >> 24) & 0x000000ff );
-}
-static U64 XXH_swap64 (U64 x)
-{
-    return  ((x << 56) & 0xff00000000000000ULL) |
-            ((x << 40) & 0x00ff000000000000ULL) |
-            ((x << 24) & 0x0000ff0000000000ULL) |
-            ((x << 8)  & 0x000000ff00000000ULL) |
-            ((x >> 8)  & 0x00000000ff000000ULL) |
-            ((x >> 24) & 0x0000000000ff0000ULL) |
-            ((x >> 40) & 0x000000000000ff00ULL) |
-            ((x >> 56) & 0x00000000000000ffULL);
-}
-#endif
-
-
-/***************************************
-*  Architecture Macros
-***************************************/
-typedef enum { XXH_bigEndian=0, XXH_littleEndian=1 } XXH_endianness;
-
-/* XXH_CPU_LITTLE_ENDIAN can be defined externally, for example one the compiler command line */
-#ifndef XXH_CPU_LITTLE_ENDIAN
-    static const int one = 1;
-#   define XXH_CPU_LITTLE_ENDIAN   (*(const char*)(&one))
-#endif
-
-
-/*****************************
-*  Memory reads
-*****************************/
-typedef enum { XXH_aligned, XXH_unaligned } XXH_alignment;
-
-FORCE_INLINE U32 XXH_readLE32_align(const void* ptr, XXH_endianness endian, XXH_alignment align)
-{
-    if (align==XXH_unaligned)
-        return endian==XXH_littleEndian ? XXH_read32(ptr) : XXH_swap32(XXH_read32(ptr));
-    else
-        return endian==XXH_littleEndian ? *(const U32*)ptr : XXH_swap32(*(const U32*)ptr);
-}
-
-FORCE_INLINE U32 XXH_readLE32(const void* ptr, XXH_endianness endian)
-{
-    return XXH_readLE32_align(ptr, endian, XXH_unaligned);
-}
-
-FORCE_INLINE U64 XXH_readLE64_align(const void* ptr, XXH_endianness endian, XXH_alignment align)
-{
-    if (align==XXH_unaligned)
-        return endian==XXH_littleEndian ? XXH_read64(ptr) : XXH_swap64(XXH_read64(ptr));
-    else
-        return endian==XXH_littleEndian ? *(const U64*)ptr : XXH_swap64(*(const U64*)ptr);
-}
-
-FORCE_INLINE U64 XXH_readLE64(const void* ptr, XXH_endianness endian)
-{
-    return XXH_readLE64_align(ptr, endian, XXH_unaligned);
-}
-
-
-/***************************************
-*  Macros
-***************************************/
-#define XXH_STATIC_ASSERT(c)   { enum { XXH_static_assert = 1/(!!(c)) }; }    /* use only *after* variable declarations */
-
-
-/***************************************
-*  Constants
-***************************************/
-#define PRIME32_1   2654435761U
-#define PRIME32_2   2246822519U
-#define PRIME32_3   3266489917U
-#define PRIME32_4    668265263U
-#define PRIME32_5    374761393U
-
-#define PRIME64_1 11400714785074694791ULL
-#define PRIME64_2 14029467366897019727ULL
-#define PRIME64_3  1609587929392839161ULL
-#define PRIME64_4  9650029242287828579ULL
-#define PRIME64_5  2870177450012600261ULL
-
-
-/*****************************
-*  Simple Hash Functions
-*****************************/
-FORCE_INLINE U32 XXH32_endian_align(const void* input, size_t len, U32 seed, XXH_endianness endian, XXH_alignment align)
-{
-    const BYTE* p = (const BYTE*)input;
-    const BYTE* bEnd = p + len;
-    U32 h32;
-#define XXH_get32bits(p) XXH_readLE32_align(p, endian, align)
-
-#ifdef XXH_ACCEPT_NULL_INPUT_POINTER
-    if (p==NULL)
-    {
-        len=0;
-        bEnd=p=(const BYTE*)(size_t)16;
-    }
-#endif
-
-    if (len>=16)
-    {
-        const BYTE* const limit = bEnd - 16;
-        U32 v1 = seed + PRIME32_1 + PRIME32_2;
-        U32 v2 = seed + PRIME32_2;
-        U32 v3 = seed + 0;
-        U32 v4 = seed - PRIME32_1;
-
-        do
-        {
-            v1 += XXH_get32bits(p) * PRIME32_2;
-            v1 = XXH_rotl32(v1, 13);
-            v1 *= PRIME32_1;
-            p+=4;
-            v2 += XXH_get32bits(p) * PRIME32_2;
-            v2 = XXH_rotl32(v2, 13);
-            v2 *= PRIME32_1;
-            p+=4;
-            v3 += XXH_get32bits(p) * PRIME32_2;
-            v3 = XXH_rotl32(v3, 13);
-            v3 *= PRIME32_1;
-            p+=4;
-            v4 += XXH_get32bits(p) * PRIME32_2;
-            v4 = XXH_rotl32(v4, 13);
-            v4 *= PRIME32_1;
-            p+=4;
-        }
-        while (p<=limit);
-
-        h32 = XXH_rotl32(v1, 1) + XXH_rotl32(v2, 7) + XXH_rotl32(v3, 12) + XXH_rotl32(v4, 18);
-    }
-    else
-    {
-        h32  = seed + PRIME32_5;
-    }
-
-    h32 += (U32) len;
-
-    while (p+4<=bEnd)
-    {
-        h32 += XXH_get32bits(p) * PRIME32_3;
-        h32  = XXH_rotl32(h32, 17) * PRIME32_4 ;
-        p+=4;
-    }
-
-    while (p<bEnd)
-    {
-        h32 += (*p) * PRIME32_5;
-        h32 = XXH_rotl32(h32, 11) * PRIME32_1 ;
-        p++;
-    }
-
-    h32 ^= h32 >> 15;
-    h32 *= PRIME32_2;
-    h32 ^= h32 >> 13;
-    h32 *= PRIME32_3;
-    h32 ^= h32 >> 16;
-
-    return h32;
-}
-
-
-unsigned int XXH32 (const void* input, size_t len, unsigned int seed)
-{
-#if 0
-    /* Simple version, good for code maintenance, but unfortunately slow for small inputs */
-    XXH32_state_t state;
-    XXH32_reset(&state, seed);
-    XXH32_update(&state, input, len);
-    return XXH32_digest(&state);
-#else
-    XXH_endianness endian_detected = (XXH_endianness)XXH_CPU_LITTLE_ENDIAN;
-
-#  if !defined(XXH_USELESS_ALIGN_BRANCH)
-    if ((((size_t)input) & 3) == 0)   /* Input is 4-bytes aligned, leverage the speed benefit */
-    {
-        if ((endian_detected==XXH_littleEndian) || XXH_FORCE_NATIVE_FORMAT)
-            return XXH32_endian_align(input, len, seed, XXH_littleEndian, XXH_aligned);
-        else
-            return XXH32_endian_align(input, len, seed, XXH_bigEndian, XXH_aligned);
-    }
-#  endif
-
-    if ((endian_detected==XXH_littleEndian) || XXH_FORCE_NATIVE_FORMAT)
-        return XXH32_endian_align(input, len, seed, XXH_littleEndian, XXH_unaligned);
-    else
-        return XXH32_endian_align(input, len, seed, XXH_bigEndian, XXH_unaligned);
-#endif
-}
-
-FORCE_INLINE U64 XXH64_endian_align(const void* input, size_t len, U64 seed, XXH_endianness endian, XXH_alignment align)
-{
-    const BYTE* p = (const BYTE*)input;
-    const BYTE* bEnd = p + len;
-    U64 h64;
-#define XXH_get64bits(p) XXH_readLE64_align(p, endian, align)
-
-#ifdef XXH_ACCEPT_NULL_INPUT_POINTER
-    if (p==NULL)
-    {
-        len=0;
-        bEnd=p=(const BYTE*)(size_t)32;
-    }
-#endif
-
-    if (len>=32)
-    {
-        const BYTE* const limit = bEnd - 32;
-        U64 v1 = seed + PRIME64_1 + PRIME64_2;
-        U64 v2 = seed + PRIME64_2;
-        U64 v3 = seed + 0;
-        U64 v4 = seed - PRIME64_1;
-
-        do
-        {
-            v1 += XXH_get64bits(p) * PRIME64_2;
-            p+=8;
-            v1 = XXH_rotl64(v1, 31);
-            v1 *= PRIME64_1;
-            v2 += XXH_get64bits(p) * PRIME64_2;
-            p+=8;
-            v2 = XXH_rotl64(v2, 31);
-            v2 *= PRIME64_1;
-            v3 += XXH_get64bits(p) * PRIME64_2;
-            p+=8;
-            v3 = XXH_rotl64(v3, 31);
-            v3 *= PRIME64_1;
-            v4 += XXH_get64bits(p) * PRIME64_2;
-            p+=8;
-            v4 = XXH_rotl64(v4, 31);
-            v4 *= PRIME64_1;
-        }
-        while (p<=limit);
-
-        h64 = XXH_rotl64(v1, 1) + XXH_rotl64(v2, 7) + XXH_rotl64(v3, 12) + XXH_rotl64(v4, 18);
-
-        v1 *= PRIME64_2;
-        v1 = XXH_rotl64(v1, 31);
-        v1 *= PRIME64_1;
-        h64 ^= v1;
-        h64 = h64 * PRIME64_1 + PRIME64_4;
-
-        v2 *= PRIME64_2;
-        v2 = XXH_rotl64(v2, 31);
-        v2 *= PRIME64_1;
-        h64 ^= v2;
-        h64 = h64 * PRIME64_1 + PRIME64_4;
-
-        v3 *= PRIME64_2;
-        v3 = XXH_rotl64(v3, 31);
-        v3 *= PRIME64_1;
-        h64 ^= v3;
-        h64 = h64 * PRIME64_1 + PRIME64_4;
-
-        v4 *= PRIME64_2;
-        v4 = XXH_rotl64(v4, 31);
-        v4 *= PRIME64_1;
-        h64 ^= v4;
-        h64 = h64 * PRIME64_1 + PRIME64_4;
-    }
-    else
-    {
-        h64  = seed + PRIME64_5;
-    }
-
-    h64 += (U64) len;
-
-    while (p+8<=bEnd)
-    {
-        U64 k1 = XXH_get64bits(p);
-        k1 *= PRIME64_2;
-        k1 = XXH_rotl64(k1,31);
-        k1 *= PRIME64_1;
-        h64 ^= k1;
-        h64 = XXH_rotl64(h64,27) * PRIME64_1 + PRIME64_4;
-        p+=8;
-    }
-
-    if (p+4<=bEnd)
-    {
-        h64 ^= (U64)(XXH_get32bits(p)) * PRIME64_1;
-        h64 = XXH_rotl64(h64, 23) * PRIME64_2 + PRIME64_3;
-        p+=4;
-    }
-
-    while (p<bEnd)
-    {
-        h64 ^= (*p) * PRIME64_5;
-        h64 = XXH_rotl64(h64, 11) * PRIME64_1;
-        p++;
-    }
-
-    h64 ^= h64 >> 33;
-    h64 *= PRIME64_2;
-    h64 ^= h64 >> 29;
-    h64 *= PRIME64_3;
-    h64 ^= h64 >> 32;
-
-    return h64;
-}
-
-
-unsigned long long XXH64 (const void* input, size_t len, unsigned long long seed)
-{
-#if 0
-    /* Simple version, good for code maintenance, but unfortunately slow for small inputs */
-    XXH64_state_t state;
-    XXH64_reset(&state, seed);
-    XXH64_update(&state, input, len);
-    return XXH64_digest(&state);
-#else
-    XXH_endianness endian_detected = (XXH_endianness)XXH_CPU_LITTLE_ENDIAN;
-
-#  if !defined(XXH_USELESS_ALIGN_BRANCH)
-    if ((((size_t)input) & 7)==0)   /* Input is aligned, let's leverage the speed advantage */
-    {
-        if ((endian_detected==XXH_littleEndian) || XXH_FORCE_NATIVE_FORMAT)
-            return XXH64_endian_align(input, len, seed, XXH_littleEndian, XXH_aligned);
-        else
-            return XXH64_endian_align(input, len, seed, XXH_bigEndian, XXH_aligned);
-    }
-#  endif
-
-    if ((endian_detected==XXH_littleEndian) || XXH_FORCE_NATIVE_FORMAT)
-        return XXH64_endian_align(input, len, seed, XXH_littleEndian, XXH_unaligned);
-    else
-        return XXH64_endian_align(input, len, seed, XXH_bigEndian, XXH_unaligned);
-#endif
-}
-
-/****************************************************
-*  Advanced Hash Functions
-****************************************************/
-
-/*** Allocation ***/
-typedef struct
-{
-    U64 total_len;
-    U32 seed;
-    U32 v1;
-    U32 v2;
-    U32 v3;
-    U32 v4;
-    U32 mem32[4];   /* defined as U32 for alignment */
-    U32 memsize;
-} XXH_istate32_t;
-
-typedef struct
-{
-    U64 total_len;
-    U64 seed;
-    U64 v1;
-    U64 v2;
-    U64 v3;
-    U64 v4;
-    U64 mem64[4];   /* defined as U64 for alignment */
-    U32 memsize;
-} XXH_istate64_t;
-
-
-XXH32_state_t* XXH32_createState(void)
-{
-    XXH_STATIC_ASSERT(sizeof(XXH32_state_t) >= sizeof(XXH_istate32_t));   /* A compilation error here means XXH32_state_t is not large enough */
-    return (XXH32_state_t*)XXH_malloc(sizeof(XXH32_state_t));
-}
-XXH_errorcode XXH32_freeState(XXH32_state_t* statePtr)
-{
-    XXH_free(statePtr);
-    return XXH_OK;
-}
-
-XXH64_state_t* XXH64_createState(void)
-{
-    XXH_STATIC_ASSERT(sizeof(XXH64_state_t) >= sizeof(XXH_istate64_t));   /* A compilation error here means XXH64_state_t is not large enough */
-    return (XXH64_state_t*)XXH_malloc(sizeof(XXH64_state_t));
-}
-XXH_errorcode XXH64_freeState(XXH64_state_t* statePtr)
-{
-    XXH_free(statePtr);
-    return XXH_OK;
-}
-
-
-/*** Hash feed ***/
-
-XXH_errorcode XXH32_reset(XXH32_state_t* state_in, unsigned int seed)
-{
-    XXH_istate32_t* state = (XXH_istate32_t*) state_in;
-    state->seed = seed;
-    state->v1 = seed + PRIME32_1 + PRIME32_2;
-    state->v2 = seed + PRIME32_2;
-    state->v3 = seed + 0;
-    state->v4 = seed - PRIME32_1;
-    state->total_len = 0;
-    state->memsize = 0;
-    return XXH_OK;
-}
-
-XXH_errorcode XXH64_reset(XXH64_state_t* state_in, unsigned long long seed)
-{
-    XXH_istate64_t* state = (XXH_istate64_t*) state_in;
-    state->seed = seed;
-    state->v1 = seed + PRIME64_1 + PRIME64_2;
-    state->v2 = seed + PRIME64_2;
-    state->v3 = seed + 0;
-    state->v4 = seed - PRIME64_1;
-    state->total_len = 0;
-    state->memsize = 0;
-    return XXH_OK;
-}
-
-
-FORCE_INLINE XXH_errorcode XXH32_update_endian (XXH32_state_t* state_in, const void* input, size_t len, XXH_endianness endian)
-{
-    XXH_istate32_t* state = (XXH_istate32_t *) state_in;
-    const BYTE* p = (const BYTE*)input;
-    const BYTE* const bEnd = p + len;
-
-#ifdef XXH_ACCEPT_NULL_INPUT_POINTER
-    if (input==NULL) return XXH_ERROR;
-#endif
-
-    state->total_len += len;
-
-    if (state->memsize + len < 16)   /* fill in tmp buffer */
-    {
-        XXH_memcpy((BYTE*)(state->mem32) + state->memsize, input, len);
-        state->memsize += (U32)len;
-        return XXH_OK;
-    }
-
-    if (state->memsize)   /* some data left from previous update */
-    {
-        XXH_memcpy((BYTE*)(state->mem32) + state->memsize, input, 16-state->memsize);
-        {
-            const U32* p32 = state->mem32;
-            state->v1 += XXH_readLE32(p32, endian) * PRIME32_2;
-            state->v1 = XXH_rotl32(state->v1, 13);
-            state->v1 *= PRIME32_1;
-            p32++;
-            state->v2 += XXH_readLE32(p32, endian) * PRIME32_2;
-            state->v2 = XXH_rotl32(state->v2, 13);
-            state->v2 *= PRIME32_1;
-            p32++;
-            state->v3 += XXH_readLE32(p32, endian) * PRIME32_2;
-            state->v3 = XXH_rotl32(state->v3, 13);
-            state->v3 *= PRIME32_1;
-            p32++;
-            state->v4 += XXH_readLE32(p32, endian) * PRIME32_2;
-            state->v4 = XXH_rotl32(state->v4, 13);
-            state->v4 *= PRIME32_1;
-            p32++;
-        }
-        p += 16-state->memsize;
-        state->memsize = 0;
-    }
-
-    if (p <= bEnd-16)
-    {
-        const BYTE* const limit = bEnd - 16;
-        U32 v1 = state->v1;
-        U32 v2 = state->v2;
-        U32 v3 = state->v3;
-        U32 v4 = state->v4;
-
-        do
-        {
-            v1 += XXH_readLE32(p, endian) * PRIME32_2;
-            v1 = XXH_rotl32(v1, 13);
-            v1 *= PRIME32_1;
-            p+=4;
-            v2 += XXH_readLE32(p, endian) * PRIME32_2;
-            v2 = XXH_rotl32(v2, 13);
-            v2 *= PRIME32_1;
-            p+=4;
-            v3 += XXH_readLE32(p, endian) * PRIME32_2;
-            v3 = XXH_rotl32(v3, 13);
-            v3 *= PRIME32_1;
-            p+=4;
-            v4 += XXH_readLE32(p, endian) * PRIME32_2;
-            v4 = XXH_rotl32(v4, 13);
-            v4 *= PRIME32_1;
-            p+=4;
-        }
-        while (p<=limit);
-
-        state->v1 = v1;
-        state->v2 = v2;
-        state->v3 = v3;
-        state->v4 = v4;
-    }
-
-    if (p < bEnd)
-    {
-        XXH_memcpy(state->mem32, p, bEnd-p);
-        state->memsize = (int)(bEnd-p);
-    }
-
-    return XXH_OK;
-}
-
-XXH_errorcode XXH32_update (XXH32_state_t* state_in, const void* input, size_t len)
-{
-    XXH_endianness endian_detected = (XXH_endianness)XXH_CPU_LITTLE_ENDIAN;
-
-    if ((endian_detected==XXH_littleEndian) || XXH_FORCE_NATIVE_FORMAT)
-        return XXH32_update_endian(state_in, input, len, XXH_littleEndian);
-    else
-        return XXH32_update_endian(state_in, input, len, XXH_bigEndian);
-}
-
-
-
-FORCE_INLINE U32 XXH32_digest_endian (const XXH32_state_t* state_in, XXH_endianness endian)
-{
-    const XXH_istate32_t* state = (const XXH_istate32_t*) state_in;
-    const BYTE * p = (const BYTE*)state->mem32;
-    const BYTE* bEnd = (const BYTE*)(state->mem32) + state->memsize;
-    U32 h32;
-
-    if (state->total_len >= 16)
-    {
-        h32 = XXH_rotl32(state->v1, 1) + XXH_rotl32(state->v2, 7) + XXH_rotl32(state->v3, 12) + XXH_rotl32(state->v4, 18);
-    }
-    else
-    {
-        h32  = state->seed + PRIME32_5;
-    }
-
-    h32 += (U32) state->total_len;
-
-    while (p+4<=bEnd)
-    {
-        h32 += XXH_readLE32(p, endian) * PRIME32_3;
-        h32  = XXH_rotl32(h32, 17) * PRIME32_4;
-        p+=4;
-    }
-
-    while (p<bEnd)
-    {
-        h32 += (*p) * PRIME32_5;
-        h32 = XXH_rotl32(h32, 11) * PRIME32_1;
-        p++;
-    }
-
-    h32 ^= h32 >> 15;
-    h32 *= PRIME32_2;
-    h32 ^= h32 >> 13;
-    h32 *= PRIME32_3;
-    h32 ^= h32 >> 16;
-
-    return h32;
-}
-
-
-unsigned int XXH32_digest (const XXH32_state_t* state_in)
-{
-    XXH_endianness endian_detected = (XXH_endianness)XXH_CPU_LITTLE_ENDIAN;
-
-    if ((endian_detected==XXH_littleEndian) || XXH_FORCE_NATIVE_FORMAT)
-        return XXH32_digest_endian(state_in, XXH_littleEndian);
-    else
-        return XXH32_digest_endian(state_in, XXH_bigEndian);
-}
-
-
-FORCE_INLINE XXH_errorcode XXH64_update_endian (XXH64_state_t* state_in, const void* input, size_t len, XXH_endianness endian)
-{
-    XXH_istate64_t * state = (XXH_istate64_t *) state_in;
-    const BYTE* p = (const BYTE*)input;
-    const BYTE* const bEnd = p + len;
-
-#ifdef XXH_ACCEPT_NULL_INPUT_POINTER
-    if (input==NULL) return XXH_ERROR;
-#endif
-
-    state->total_len += len;
-
-    if (state->memsize + len < 32)   /* fill in tmp buffer */
-    {
-        XXH_memcpy(((BYTE*)state->mem64) + state->memsize, input, len);
-        state->memsize += (U32)len;
-        return XXH_OK;
-    }
-
-    if (state->memsize)   /* some data left from previous update */
-    {
-        XXH_memcpy(((BYTE*)state->mem64) + state->memsize, input, 32-state->memsize);
-        {
-            const U64* p64 = state->mem64;
-            state->v1 += XXH_readLE64(p64, endian) * PRIME64_2;
-            state->v1 = XXH_rotl64(state->v1, 31);
-            state->v1 *= PRIME64_1;
-            p64++;
-            state->v2 += XXH_readLE64(p64, endian) * PRIME64_2;
-            state->v2 = XXH_rotl64(state->v2, 31);
-            state->v2 *= PRIME64_1;
-            p64++;
-            state->v3 += XXH_readLE64(p64, endian) * PRIME64_2;
-            state->v3 = XXH_rotl64(state->v3, 31);
-            state->v3 *= PRIME64_1;
-            p64++;
-            state->v4 += XXH_readLE64(p64, endian) * PRIME64_2;
-            state->v4 = XXH_rotl64(state->v4, 31);
-            state->v4 *= PRIME64_1;
-            p64++;
-        }
-        p += 32-state->memsize;
-        state->memsize = 0;
-    }
-
-    if (p+32 <= bEnd)
-    {
-        const BYTE* const limit = bEnd - 32;
-        U64 v1 = state->v1;
-        U64 v2 = state->v2;
-        U64 v3 = state->v3;
-        U64 v4 = state->v4;
-
-        do
-        {
-            v1 += XXH_readLE64(p, endian) * PRIME64_2;
-            v1 = XXH_rotl64(v1, 31);
-            v1 *= PRIME64_1;
-            p+=8;
-            v2 += XXH_readLE64(p, endian) * PRIME64_2;
-            v2 = XXH_rotl64(v2, 31);
-            v2 *= PRIME64_1;
-            p+=8;
-            v3 += XXH_readLE64(p, endian) * PRIME64_2;
-            v3 = XXH_rotl64(v3, 31);
-            v3 *= PRIME64_1;
-            p+=8;
-            v4 += XXH_readLE64(p, endian) * PRIME64_2;
-            v4 = XXH_rotl64(v4, 31);
-            v4 *= PRIME64_1;
-            p+=8;
-        }
-        while (p<=limit);
-
-        state->v1 = v1;
-        state->v2 = v2;
-        state->v3 = v3;
-        state->v4 = v4;
-    }
-
-    if (p < bEnd)
-    {
-        XXH_memcpy(state->mem64, p, bEnd-p);
-        state->memsize = (int)(bEnd-p);
-    }
-
-    return XXH_OK;
-}
-
-XXH_errorcode XXH64_update (XXH64_state_t* state_in, const void* input, size_t len)
-{
-    XXH_endianness endian_detected = (XXH_endianness)XXH_CPU_LITTLE_ENDIAN;
-
-    if ((endian_detected==XXH_littleEndian) || XXH_FORCE_NATIVE_FORMAT)
-        return XXH64_update_endian(state_in, input, len, XXH_littleEndian);
-    else
-        return XXH64_update_endian(state_in, input, len, XXH_bigEndian);
-}
-
-
-
-FORCE_INLINE U64 XXH64_digest_endian (const XXH64_state_t* state_in, XXH_endianness endian)
-{
-    const XXH_istate64_t * state = (const XXH_istate64_t *) state_in;
-    const BYTE * p = (const BYTE*)state->mem64;
-    const BYTE* bEnd = (const BYTE*)state->mem64 + state->memsize;
-    U64 h64;
-
-    if (state->total_len >= 32)
-    {
-        U64 v1 = state->v1;
-        U64 v2 = state->v2;
-        U64 v3 = state->v3;
-        U64 v4 = state->v4;
-
-        h64 = XXH_rotl64(v1, 1) + XXH_rotl64(v2, 7) + XXH_rotl64(v3, 12) + XXH_rotl64(v4, 18);
-
-        v1 *= PRIME64_2;
-        v1 = XXH_rotl64(v1, 31);
-        v1 *= PRIME64_1;
-        h64 ^= v1;
-        h64 = h64*PRIME64_1 + PRIME64_4;
-
-        v2 *= PRIME64_2;
-        v2 = XXH_rotl64(v2, 31);
-        v2 *= PRIME64_1;
-        h64 ^= v2;
-        h64 = h64*PRIME64_1 + PRIME64_4;
-
-        v3 *= PRIME64_2;
-        v3 = XXH_rotl64(v3, 31);
-        v3 *= PRIME64_1;
-        h64 ^= v3;
-        h64 = h64*PRIME64_1 + PRIME64_4;
-
-        v4 *= PRIME64_2;
-        v4 = XXH_rotl64(v4, 31);
-        v4 *= PRIME64_1;
-        h64 ^= v4;
-        h64 = h64*PRIME64_1 + PRIME64_4;
-    }
-    else
-    {
-        h64  = state->seed + PRIME64_5;
-    }
-
-    h64 += (U64) state->total_len;
-
-    while (p+8<=bEnd)
-    {
-        U64 k1 = XXH_readLE64(p, endian);
-        k1 *= PRIME64_2;
-        k1 = XXH_rotl64(k1,31);
-        k1 *= PRIME64_1;
-        h64 ^= k1;
-        h64 = XXH_rotl64(h64,27) * PRIME64_1 + PRIME64_4;
-        p+=8;
-    }
-
-    if (p+4<=bEnd)
-    {
-        h64 ^= (U64)(XXH_readLE32(p, endian)) * PRIME64_1;
-        h64 = XXH_rotl64(h64, 23) * PRIME64_2 + PRIME64_3;
-        p+=4;
-    }
-
-    while (p<bEnd)
-    {
-        h64 ^= (*p) * PRIME64_5;
-        h64 = XXH_rotl64(h64, 11) * PRIME64_1;
-        p++;
-    }
-
-    h64 ^= h64 >> 33;
-    h64 *= PRIME64_2;
-    h64 ^= h64 >> 29;
-    h64 *= PRIME64_3;
-    h64 ^= h64 >> 32;
-
-    return h64;
-}
-
-
-unsigned long long XXH64_digest (const XXH64_state_t* state_in)
-{
-    XXH_endianness endian_detected = (XXH_endianness)XXH_CPU_LITTLE_ENDIAN;
-
-    if ((endian_detected==XXH_littleEndian) || XXH_FORCE_NATIVE_FORMAT)
-        return XXH64_digest_endian(state_in, XXH_littleEndian);
-    else
-        return XXH64_digest_endian(state_in, XXH_bigEndian);
-}
-
-
diff --git a/util/cbfstool/lz4/lib/xxhash.h b/util/cbfstool/lz4/lib/xxhash.h
deleted file mode 100644
index c60aa61571..0000000000
--- a/util/cbfstool/lz4/lib/xxhash.h
+++ /dev/null
@@ -1,192 +0,0 @@
-/*
-   xxHash - Extremely Fast Hash algorithm
-   Header File
-   Copyright (C) 2012-2015, Yann Collet.
-
-   BSD 2-Clause License (http://www.opensource.org/licenses/bsd-license.php)
-
-   Redistribution and use in source and binary forms, with or without
-   modification, are permitted provided that the following conditions are
-   met:
-
-       * Redistributions of source code must retain the above copyright
-   notice, this list of conditions and the following disclaimer.
-       * Redistributions in binary form must reproduce the above
-   copyright notice, this list of conditions and the following disclaimer
-   in the documentation and/or other materials provided with the
-   distribution.
-
-   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
-   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-
-   You can contact the author at :
-   - xxHash source repository : https://github.com/Cyan4973/xxHash
-*/
-
-/* Notice extracted from xxHash homepage :
-
-xxHash is an extremely fast Hash algorithm, running at RAM speed limits.
-It also successfully passes all tests from the SMHasher suite.
-
-Comparison (single thread, Windows Seven 32 bits, using SMHasher on a Core 2 Duo @3GHz)
-
-Name            Speed       Q.Score   Author
-xxHash          5.4 GB/s     10
-CrapWow         3.2 GB/s      2       Andrew
-MumurHash 3a    2.7 GB/s     10       Austin Appleby
-SpookyHash      2.0 GB/s     10       Bob Jenkins
-SBox            1.4 GB/s      9       Bret Mulvey
-Lookup3         1.2 GB/s      9       Bob Jenkins
-SuperFastHash   1.2 GB/s      1       Paul Hsieh
-CityHash64      1.05 GB/s    10       Pike & Alakuijala
-FNV             0.55 GB/s     5       Fowler, Noll, Vo
-CRC32           0.43 GB/s     9
-MD5-32          0.33 GB/s    10       Ronald L. Rivest
-SHA1-32         0.28 GB/s    10
-
-Q.Score is a measure of quality of the hash function.
-It depends on successfully passing SMHasher test set.
-10 is a perfect score.
-
-A 64-bits version, named XXH64, is available since r35.
-It offers much better speed, but for 64-bits applications only.
-Name     Speed on 64 bits    Speed on 32 bits
-XXH64       13.8 GB/s            1.9 GB/s
-XXH32        6.8 GB/s            6.0 GB/s
-*/
-
-#pragma once
-
-#if defined (__cplusplus)
-extern "C" {
-#endif
-
-
-/*****************************
-*  Definitions
-*****************************/
-#include <stddef.h>   /* size_t */
-typedef enum { XXH_OK=0, XXH_ERROR } XXH_errorcode;
-
-
-/*****************************
-*  Namespace Emulation
-*****************************/
-/* Motivations :
-
-If you need to include xxHash into your library,
-but wish to avoid xxHash symbols to be present on your library interface
-in an effort to avoid potential name collision if another library also includes xxHash,
-
-you can use XXH_NAMESPACE, which will automatically prefix any symbol from xxHash
-with the value of XXH_NAMESPACE (so avoid to keep it NULL, and avoid numeric values).
-
-Note that no change is required within the calling program :
-it can still call xxHash functions using their regular name.
-They will be automatically translated by this header.
-*/
-#ifdef XXH_NAMESPACE
-#  define XXH_CAT(A,B) A##B
-#  define XXH_NAME2(A,B) XXH_CAT(A,B)
-#  define XXH32 XXH_NAME2(XXH_NAMESPACE, XXH32)
-#  define XXH64 XXH_NAME2(XXH_NAMESPACE, XXH64)
-#  define XXH32_createState XXH_NAME2(XXH_NAMESPACE, XXH32_createState)
-#  define XXH64_createState XXH_NAME2(XXH_NAMESPACE, XXH64_createState)
-#  define XXH32_freeState XXH_NAME2(XXH_NAMESPACE, XXH32_freeState)
-#  define XXH64_freeState XXH_NAME2(XXH_NAMESPACE, XXH64_freeState)
-#  define XXH32_reset XXH_NAME2(XXH_NAMESPACE, XXH32_reset)
-#  define XXH64_reset XXH_NAME2(XXH_NAMESPACE, XXH64_reset)
-#  define XXH32_update XXH_NAME2(XXH_NAMESPACE, XXH32_update)
-#  define XXH64_update XXH_NAME2(XXH_NAMESPACE, XXH64_update)
-#  define XXH32_digest XXH_NAME2(XXH_NAMESPACE, XXH32_digest)
-#  define XXH64_digest XXH_NAME2(XXH_NAMESPACE, XXH64_digest)
-#endif
-
-
-/*****************************
-*  Simple Hash Functions
-*****************************/
-
-unsigned int       XXH32 (const void* input, size_t length, unsigned seed);
-unsigned long long XXH64 (const void* input, size_t length, unsigned long long seed);
-
-/*
-XXH32() :
-    Calculate the 32-bits hash of sequence "length" bytes stored at memory address "input".
-    The memory between input & input+length must be valid (allocated and read-accessible).
-    "seed" can be used to alter the result predictably.
-    This function successfully passes all SMHasher tests.
-    Speed on Core 2 Duo @ 3 GHz (single thread, SMHasher benchmark) : 5.4 GB/s
-XXH64() :
-    Calculate the 64-bits hash of sequence of length "len" stored at memory address "input".
-    Faster on 64-bits systems. Slower on 32-bits systems.
-*/
-
-
-
-/*****************************
-*  Advanced Hash Functions
-*****************************/
-typedef struct { long long ll[ 6]; } XXH32_state_t;
-typedef struct { long long ll[11]; } XXH64_state_t;
-
-/*
-These structures allow static allocation of XXH states.
-States must then be initialized using XXHnn_reset() before first use.
-
-If you prefer dynamic allocation, please refer to functions below.
-*/
-
-XXH32_state_t* XXH32_createState(void);
-XXH_errorcode  XXH32_freeState(XXH32_state_t* statePtr);
-
-XXH64_state_t* XXH64_createState(void);
-XXH_errorcode  XXH64_freeState(XXH64_state_t* statePtr);
-
-/*
-These functions create and release memory for XXH state.
-States must then be initialized using XXHnn_reset() before first use.
-*/
-
-
-XXH_errorcode XXH32_reset  (XXH32_state_t* statePtr, unsigned seed);
-XXH_errorcode XXH32_update (XXH32_state_t* statePtr, const void* input, size_t length);
-unsigned int  XXH32_digest (const XXH32_state_t* statePtr);
-
-XXH_errorcode      XXH64_reset  (XXH64_state_t* statePtr, unsigned long long seed);
-XXH_errorcode      XXH64_update (XXH64_state_t* statePtr, const void* input, size_t length);
-unsigned long long XXH64_digest (const XXH64_state_t* statePtr);
-
-/*
-These functions calculate the xxHash of an input provided in multiple smaller packets,
-as opposed to an input provided as a single block.
-
-XXH state space must first be allocated, using either static or dynamic method provided above.
-
-Start a new hash by initializing state with a seed, using XXHnn_reset().
-
-Then, feed the hash state by calling XXHnn_update() as many times as necessary.
-Obviously, input must be valid, meaning allocated and read accessible.
-The function returns an error code, with 0 meaning OK, and any other value meaning there is an error.
-
-Finally, you can produce a hash anytime, by using XXHnn_digest().
-This function returns the final nn-bits hash.
-You can nonetheless continue feeding the hash state with more input,
-and therefore get some new hashes, by calling again XXHnn_digest().
-
-When you are done, don't forget to free XXH state space, using typically XXHnn_freeState().
-*/
-
-
-#if defined (__cplusplus)
-}
-#endif

From 0421ef2cd844936660f31a8564b17deae8540a26 Mon Sep 17 00:00:00 2001
From: Arthur Heymans <arthur@aheymans.xyz>
Date: Tue, 22 Nov 2022 16:17:10 +0100
Subject: [PATCH 2874/3886] util/cbfstool: Add zstd support

This adds zstd support to cbfstool. The code is taken from zstd-1.5.7
with modifications:
- renaming bits.h to zstd_bits.h to avoid conflicts with coreboot's
  bits.h used on riscv
- renaming compiler.h to zstd_compiler.h to avoid conflicts with
  coreboot's compiler.h
- Dropped all streaming API functions
- Dropped multithreaded support, since it's now unused
- Dropped local DDict support

zstd offers similar compression ratios to LZMA, but a vastly fast
decompress speed. Typically zstd results in slightly larger binaries
than LZMA. Whether zstd should then be preferred over LZMA depends on
a few things:
- Caching: When loading from memory mapped boot devices, zstd will read
  the boot medium multiple times, while LZMA will not. If the memory
  mapped boot medium is not cached zstd results in much slower
  decompression.
- Boot medium speed: Often, but not always LZMA results in smaller
  binaries. If the boot medium is the bottleneck, than loading smaller
  binaries might actually be faster. On a fast boot medium (high spi
  freq, using quad/dual io), the performance benefits from zstd might be
  more substantial
- zstd decompression code has a much larger footprint than LZMA. If the
  stage (postcar) is loaded in uncached memory the size increase might
  slow things down.
  On QEMU Q35 postcar .text section size doubled, while heap section
  has growen by 50%.
- zstd uses a lot of .bss (CTX is about 32KiB large). This might not be
  available in some environments.

Orignal commit from 2022 was using zstd-1.5.2. Updated to zstd-1.5.7.

Change-Id: I34508268f8767008ef25cb9e466d201345881232
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69753
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 .../include/commonlib/bsd/cbfs_serialized.h   |    1 +
 .../bsd/include/commonlib/bsd/compression.h   |    3 +
 src/commonlib/bsd/zstd/common/allocations.h   |   57 +
 src/commonlib/bsd/zstd/common/bitstream.h     |  456 ++
 src/commonlib/bsd/zstd/common/cpu.h           |  251 +
 src/commonlib/bsd/zstd/common/debug.c         |   32 +
 src/commonlib/bsd/zstd/common/debug.h         |  109 +
 .../bsd/zstd/common/entropy_common.c          |  342 +
 src/commonlib/bsd/zstd/common/error_private.c |   66 +
 src/commonlib/bsd/zstd/common/error_private.h |  160 +
 src/commonlib/bsd/zstd/common/fse.h           |  627 ++
 .../bsd/zstd/common/fse_decompress.c          |  317 +
 src/commonlib/bsd/zstd/common/huf.h           |  279 +
 src/commonlib/bsd/zstd/common/mem.h           |  424 ++
 .../bsd/zstd/common/portability_macros.h      |  173 +
 src/commonlib/bsd/zstd/common/zstd_bits.h     |  206 +
 src/commonlib/bsd/zstd/common/zstd_common.c   |   50 +
 src/commonlib/bsd/zstd/common/zstd_compiler.h |  462 ++
 src/commonlib/bsd/zstd/common/zstd_deps.h     |  125 +
 src/commonlib/bsd/zstd/common/zstd_internal.h |  324 +
 src/commonlib/bsd/zstd/common/zstd_trace.h    |  158 +
 src/commonlib/bsd/zstd/common/zstd_xxhash.h   |   20 +
 src/commonlib/bsd/zstd/compress/clevels.h     |  136 +
 .../bsd/zstd/compress/fse_compress.c          |  627 ++
 src/commonlib/bsd/zstd/compress/hist.c        |  193 +
 src/commonlib/bsd/zstd/compress/hist.h        |   84 +
 .../bsd/zstd/compress/huf_compress.c          | 1466 ++++
 .../bsd/zstd/compress/zstd_compress.c         | 6046 +++++++++++++++++
 .../zstd/compress/zstd_compress_internal.h    | 1625 +++++
 .../zstd/compress/zstd_compress_literals.c    |  237 +
 .../zstd/compress/zstd_compress_literals.h    |   41 +
 .../zstd/compress/zstd_compress_sequences.c   |  444 ++
 .../zstd/compress/zstd_compress_sequences.h   |   57 +
 .../zstd/compress/zstd_compress_superblock.c  |  690 ++
 .../zstd/compress/zstd_compress_superblock.h  |   34 +
 src/commonlib/bsd/zstd/compress/zstd_cwksp.h  |  767 +++
 .../bsd/zstd/compress/zstd_double_fast.c      |  780 +++
 .../bsd/zstd/compress/zstd_double_fast.h      |   44 +
 src/commonlib/bsd/zstd/compress/zstd_fast.c   |  987 +++
 src/commonlib/bsd/zstd/compress/zstd_fast.h   |   32 +
 src/commonlib/bsd/zstd/compress/zstd_lazy.c   | 2201 ++++++
 src/commonlib/bsd/zstd/compress/zstd_lazy.h   |  195 +
 src/commonlib/bsd/zstd/compress/zstd_ldm.c    |  747 ++
 src/commonlib/bsd/zstd/compress/zstd_ldm.h    |  111 +
 .../bsd/zstd/compress/zstd_ldm_geartab.h      |  108 +
 src/commonlib/bsd/zstd/compress/zstd_opt.c    | 1582 +++++
 src/commonlib/bsd/zstd/compress/zstd_opt.h    |   74 +
 .../bsd/zstd/compress/zstd_preSplit.c         |  239 +
 .../bsd/zstd/compress/zstd_preSplit.h         |   34 +
 .../bsd/zstd/decompress/huf_decompress.c      | 1946 ++++++
 .../bsd/zstd/decompress/zstd_ddict.c          |  246 +
 .../bsd/zstd/decompress/zstd_ddict.h          |   46 +
 .../bsd/zstd/decompress/zstd_decompress.c     |  922 +++
 .../zstd/decompress/zstd_decompress_block.c   | 2188 ++++++
 .../zstd/decompress/zstd_decompress_block.h   |   69 +
 .../decompress/zstd_decompress_internal.h     |  240 +
 src/commonlib/bsd/zstd/zdict.h                |  483 ++
 src/commonlib/bsd/zstd/zstd.h                 | 2646 ++++++++
 src/commonlib/bsd/zstd/zstd_errors.h          |  109 +
 util/cbfstool/Makefile.mk                     |   34 +
 util/cbfstool/cbfs.h                          |    1 +
 util/cbfstool/compress.c                      |   56 +-
 62 files changed, 33208 insertions(+), 1 deletion(-)
 create mode 100644 src/commonlib/bsd/zstd/common/allocations.h
 create mode 100644 src/commonlib/bsd/zstd/common/bitstream.h
 create mode 100644 src/commonlib/bsd/zstd/common/cpu.h
 create mode 100644 src/commonlib/bsd/zstd/common/debug.c
 create mode 100644 src/commonlib/bsd/zstd/common/debug.h
 create mode 100644 src/commonlib/bsd/zstd/common/entropy_common.c
 create mode 100644 src/commonlib/bsd/zstd/common/error_private.c
 create mode 100644 src/commonlib/bsd/zstd/common/error_private.h
 create mode 100644 src/commonlib/bsd/zstd/common/fse.h
 create mode 100644 src/commonlib/bsd/zstd/common/fse_decompress.c
 create mode 100644 src/commonlib/bsd/zstd/common/huf.h
 create mode 100644 src/commonlib/bsd/zstd/common/mem.h
 create mode 100644 src/commonlib/bsd/zstd/common/portability_macros.h
 create mode 100644 src/commonlib/bsd/zstd/common/zstd_bits.h
 create mode 100644 src/commonlib/bsd/zstd/common/zstd_common.c
 create mode 100644 src/commonlib/bsd/zstd/common/zstd_compiler.h
 create mode 100644 src/commonlib/bsd/zstd/common/zstd_deps.h
 create mode 100644 src/commonlib/bsd/zstd/common/zstd_internal.h
 create mode 100644 src/commonlib/bsd/zstd/common/zstd_trace.h
 create mode 100644 src/commonlib/bsd/zstd/common/zstd_xxhash.h
 create mode 100644 src/commonlib/bsd/zstd/compress/clevels.h
 create mode 100644 src/commonlib/bsd/zstd/compress/fse_compress.c
 create mode 100644 src/commonlib/bsd/zstd/compress/hist.c
 create mode 100644 src/commonlib/bsd/zstd/compress/hist.h
 create mode 100644 src/commonlib/bsd/zstd/compress/huf_compress.c
 create mode 100644 src/commonlib/bsd/zstd/compress/zstd_compress.c
 create mode 100644 src/commonlib/bsd/zstd/compress/zstd_compress_internal.h
 create mode 100644 src/commonlib/bsd/zstd/compress/zstd_compress_literals.c
 create mode 100644 src/commonlib/bsd/zstd/compress/zstd_compress_literals.h
 create mode 100644 src/commonlib/bsd/zstd/compress/zstd_compress_sequences.c
 create mode 100644 src/commonlib/bsd/zstd/compress/zstd_compress_sequences.h
 create mode 100644 src/commonlib/bsd/zstd/compress/zstd_compress_superblock.c
 create mode 100644 src/commonlib/bsd/zstd/compress/zstd_compress_superblock.h
 create mode 100644 src/commonlib/bsd/zstd/compress/zstd_cwksp.h
 create mode 100644 src/commonlib/bsd/zstd/compress/zstd_double_fast.c
 create mode 100644 src/commonlib/bsd/zstd/compress/zstd_double_fast.h
 create mode 100644 src/commonlib/bsd/zstd/compress/zstd_fast.c
 create mode 100644 src/commonlib/bsd/zstd/compress/zstd_fast.h
 create mode 100644 src/commonlib/bsd/zstd/compress/zstd_lazy.c
 create mode 100644 src/commonlib/bsd/zstd/compress/zstd_lazy.h
 create mode 100644 src/commonlib/bsd/zstd/compress/zstd_ldm.c
 create mode 100644 src/commonlib/bsd/zstd/compress/zstd_ldm.h
 create mode 100644 src/commonlib/bsd/zstd/compress/zstd_ldm_geartab.h
 create mode 100644 src/commonlib/bsd/zstd/compress/zstd_opt.c
 create mode 100644 src/commonlib/bsd/zstd/compress/zstd_opt.h
 create mode 100644 src/commonlib/bsd/zstd/compress/zstd_preSplit.c
 create mode 100644 src/commonlib/bsd/zstd/compress/zstd_preSplit.h
 create mode 100644 src/commonlib/bsd/zstd/decompress/huf_decompress.c
 create mode 100644 src/commonlib/bsd/zstd/decompress/zstd_ddict.c
 create mode 100644 src/commonlib/bsd/zstd/decompress/zstd_ddict.h
 create mode 100644 src/commonlib/bsd/zstd/decompress/zstd_decompress.c
 create mode 100644 src/commonlib/bsd/zstd/decompress/zstd_decompress_block.c
 create mode 100644 src/commonlib/bsd/zstd/decompress/zstd_decompress_block.h
 create mode 100644 src/commonlib/bsd/zstd/decompress/zstd_decompress_internal.h
 create mode 100644 src/commonlib/bsd/zstd/zdict.h
 create mode 100644 src/commonlib/bsd/zstd/zstd.h
 create mode 100644 src/commonlib/bsd/zstd/zstd_errors.h

diff --git a/src/commonlib/bsd/include/commonlib/bsd/cbfs_serialized.h b/src/commonlib/bsd/include/commonlib/bsd/cbfs_serialized.h
index b6a7baa20e..7a0fb27755 100644
--- a/src/commonlib/bsd/include/commonlib/bsd/cbfs_serialized.h
+++ b/src/commonlib/bsd/include/commonlib/bsd/cbfs_serialized.h
@@ -10,6 +10,7 @@ enum cbfs_compression {
 	CBFS_COMPRESS_NONE	= 0,
 	CBFS_COMPRESS_LZMA	= 1,
 	CBFS_COMPRESS_LZ4	= 2,
+	CBFS_COMPRESS_ZSTD	= 3,
 };
 
 enum cbfs_type {
diff --git a/src/commonlib/bsd/include/commonlib/bsd/compression.h b/src/commonlib/bsd/include/commonlib/bsd/compression.h
index 873e7e4e15..1f70fa4c60 100644
--- a/src/commonlib/bsd/include/commonlib/bsd/compression.h
+++ b/src/commonlib/bsd/include/commonlib/bsd/compression.h
@@ -18,4 +18,7 @@ size_t ulz4fn(const void *src, size_t srcn, void *dst, size_t dstn);
 /* Same as ulz4fn() but does not perform any bounds checks. */
 size_t ulz4f(const void *src, void *dst);
 
+/* Decompresses ZSTD image */
+size_t uzstdfn(const void *src, size_t srcn, void *dst, size_t dstn);
+
 #endif	/* _COMMONLIB_COMPRESSION_H_ */
diff --git a/src/commonlib/bsd/zstd/common/allocations.h b/src/commonlib/bsd/zstd/common/allocations.h
new file mode 100644
index 0000000000..1bfa3db9e9
--- /dev/null
+++ b/src/commonlib/bsd/zstd/common/allocations.h
@@ -0,0 +1,57 @@
+
+/* SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0-only */
+/*
+ * Copyright (c) Meta Platforms, Inc. and affiliates.
+ * All rights reserved.
+ *
+ * This source code is licensed under both the BSD-style license (found in the
+ * LICENSE file in the root directory of this source tree) and the GPLv2 (found
+ * in the COPYING file in the root directory of this source tree).
+ * You may select, at your option, one of the above-listed licenses.
+ */
+
+/* This file provides custom allocation primitives
+ */
+
+#define ZSTD_DEPS_NEED_MALLOC
+#include "zstd_deps.h"   /* ZSTD_malloc, ZSTD_calloc, ZSTD_free, ZSTD_memset */
+
+#include "zstd_compiler.h" /* MEM_STATIC */
+#define ZSTD_STATIC_LINKING_ONLY
+#include "../zstd.h" /* ZSTD_customMem */
+
+#ifndef ZSTD_ALLOCATIONS_H
+#define ZSTD_ALLOCATIONS_H
+
+/* custom memory allocation functions */
+
+MEM_STATIC void* ZSTD_customMalloc(size_t size, ZSTD_customMem customMem)
+{
+    if (customMem.customAlloc)
+        return customMem.customAlloc(customMem.opaque, size);
+    return ZSTD_malloc(size);
+}
+
+MEM_STATIC void* ZSTD_customCalloc(size_t size, ZSTD_customMem customMem)
+{
+    if (customMem.customAlloc) {
+        /* calloc implemented as malloc+memset;
+         * not as efficient as calloc, but next best guess for custom malloc */
+        void* const ptr = customMem.customAlloc(customMem.opaque, size);
+        ZSTD_memset(ptr, 0, size);
+        return ptr;
+    }
+    return ZSTD_calloc(1, size);
+}
+
+MEM_STATIC void ZSTD_customFree(void* ptr, ZSTD_customMem customMem)
+{
+    if (ptr!=NULL) {
+        if (customMem.customFree)
+            customMem.customFree(customMem.opaque, ptr);
+        else
+            ZSTD_free(ptr);
+    }
+}
+
+#endif /* ZSTD_ALLOCATIONS_H */
diff --git a/src/commonlib/bsd/zstd/common/bitstream.h b/src/commonlib/bsd/zstd/common/bitstream.h
new file mode 100644
index 0000000000..b0d433ff6f
--- /dev/null
+++ b/src/commonlib/bsd/zstd/common/bitstream.h
@@ -0,0 +1,456 @@
+/* SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0-only */
+
+/* ******************************************************************
+ * bitstream
+ * Part of FSE library
+ * Copyright (c) Meta Platforms, Inc. and affiliates.
+ *
+ * You can contact the author at :
+ * - Source repository : https://github.com/Cyan4973/FiniteStateEntropy
+ *
+ * This source code is licensed under both the BSD-style license (found in the
+ * LICENSE file in the root directory of this source tree) and the GPLv2 (found
+ * in the COPYING file in the root directory of this source tree).
+ * You may select, at your option, one of the above-listed licenses.
+****************************************************************** */
+#ifndef BITSTREAM_H_MODULE
+#define BITSTREAM_H_MODULE
+
+/*
+*  This API consists of small unitary functions, which must be inlined for best performance.
+*  Since link-time-optimization is not available for all compilers,
+*  these functions are defined into a .h to be included.
+*/
+
+/*-****************************************
+*  Dependencies
+******************************************/
+#include "mem.h"            /* unaligned access routines */
+#include "zstd_compiler.h"       /* UNLIKELY() */
+#include "debug.h"          /* assert(), DEBUGLOG(), RAWLOG() */
+#include "error_private.h"  /* error codes and messages */
+#include "zstd_bits.h"           /* ZSTD_highbit32 */
+
+/*=========================================
+*  Target specific
+=========================================*/
+#ifndef ZSTD_NO_INTRINSICS
+#  if (defined(__BMI__) || defined(__BMI2__)) && defined(__GNUC__)
+#    include <immintrin.h>   /* support for bextr (experimental)/bzhi */
+#  elif defined(__ICCARM__)
+#    include <intrinsics.h>
+#  endif
+#endif
+
+#define STREAM_ACCUMULATOR_MIN_32  25
+#define STREAM_ACCUMULATOR_MIN_64  57
+#define STREAM_ACCUMULATOR_MIN    ((U32)(MEM_32bits() ? STREAM_ACCUMULATOR_MIN_32 : STREAM_ACCUMULATOR_MIN_64))
+
+
+/*-******************************************
+*  bitStream encoding API (write forward)
+********************************************/
+typedef size_t BitContainerType;
+/* bitStream can mix input from multiple sources.
+ * A critical property of these streams is that they encode and decode in **reverse** direction.
+ * So the first bit sequence you add will be the last to be read, like a LIFO stack.
+ */
+typedef struct {
+    BitContainerType bitContainer;
+    unsigned bitPos;
+    char*  startPtr;
+    char*  ptr;
+    char*  endPtr;
+} BIT_CStream_t;
+
+MEM_STATIC size_t BIT_initCStream(BIT_CStream_t* bitC, void* dstBuffer, size_t dstCapacity);
+MEM_STATIC void   BIT_addBits(BIT_CStream_t* bitC, BitContainerType value, unsigned nbBits);
+MEM_STATIC void   BIT_flushBits(BIT_CStream_t* bitC);
+MEM_STATIC size_t BIT_closeCStream(BIT_CStream_t* bitC);
+
+/* Start with initCStream, providing the size of buffer to write into.
+*  bitStream will never write outside of this buffer.
+*  `dstCapacity` must be >= sizeof(bitD->bitContainer), otherwise @return will be an error code.
+*
+*  bits are first added to a local register.
+*  Local register is BitContainerType, 64-bits on 64-bits systems, or 32-bits on 32-bits systems.
+*  Writing data into memory is an explicit operation, performed by the flushBits function.
+*  Hence keep track how many bits are potentially stored into local register to avoid register overflow.
+*  After a flushBits, a maximum of 7 bits might still be stored into local register.
+*
+*  Avoid storing elements of more than 24 bits if you want compatibility with 32-bits bitstream readers.
+*
+*  Last operation is to close the bitStream.
+*  The function returns the final size of CStream in bytes.
+*  If data couldn't fit into `dstBuffer`, it will return a 0 ( == not storable)
+*/
+
+
+/*-********************************************
+*  bitStream decoding API (read backward)
+**********************************************/
+typedef struct {
+    BitContainerType bitContainer;
+    unsigned bitsConsumed;
+    const char* ptr;
+    const char* start;
+    const char* limitPtr;
+} BIT_DStream_t;
+
+typedef enum { BIT_DStream_unfinished = 0,  /* fully refilled */
+               BIT_DStream_endOfBuffer = 1, /* still some bits left in bitstream */
+               BIT_DStream_completed = 2,   /* bitstream entirely consumed, bit-exact */
+               BIT_DStream_overflow = 3     /* user requested more bits than present in bitstream */
+    } BIT_DStream_status;  /* result of BIT_reloadDStream() */
+
+MEM_STATIC size_t   BIT_initDStream(BIT_DStream_t* bitD, const void* srcBuffer, size_t srcSize);
+MEM_STATIC BitContainerType BIT_readBits(BIT_DStream_t* bitD, unsigned nbBits);
+MEM_STATIC BIT_DStream_status BIT_reloadDStream(BIT_DStream_t* bitD);
+MEM_STATIC unsigned BIT_endOfDStream(const BIT_DStream_t* bitD);
+
+
+/* Start by invoking BIT_initDStream().
+*  A chunk of the bitStream is then stored into a local register.
+*  Local register size is 64-bits on 64-bits systems, 32-bits on 32-bits systems (BitContainerType).
+*  You can then retrieve bitFields stored into the local register, **in reverse order**.
+*  Local register is explicitly reloaded from memory by the BIT_reloadDStream() method.
+*  A reload guarantee a minimum of ((8*sizeof(bitD->bitContainer))-7) bits when its result is BIT_DStream_unfinished.
+*  Otherwise, it can be less than that, so proceed accordingly.
+*  Checking if DStream has reached its end can be performed with BIT_endOfDStream().
+*/
+
+
+/*-****************************************
+*  unsafe API
+******************************************/
+MEM_STATIC void BIT_addBitsFast(BIT_CStream_t* bitC, BitContainerType value, unsigned nbBits);
+/* faster, but works only if value is "clean", meaning all high bits above nbBits are 0 */
+
+MEM_STATIC void BIT_flushBitsFast(BIT_CStream_t* bitC);
+/* unsafe version; does not check buffer overflow */
+
+MEM_STATIC size_t BIT_readBitsFast(BIT_DStream_t* bitD, unsigned nbBits);
+/* faster, but works only if nbBits >= 1 */
+
+/*=====    Local Constants   =====*/
+static const unsigned BIT_mask[] = {
+    0,          1,         3,         7,         0xF,       0x1F,
+    0x3F,       0x7F,      0xFF,      0x1FF,     0x3FF,     0x7FF,
+    0xFFF,      0x1FFF,    0x3FFF,    0x7FFF,    0xFFFF,    0x1FFFF,
+    0x3FFFF,    0x7FFFF,   0xFFFFF,   0x1FFFFF,  0x3FFFFF,  0x7FFFFF,
+    0xFFFFFF,   0x1FFFFFF, 0x3FFFFFF, 0x7FFFFFF, 0xFFFFFFF, 0x1FFFFFFF,
+    0x3FFFFFFF, 0x7FFFFFFF}; /* up to 31 bits */
+#define BIT_MASK_SIZE (sizeof(BIT_mask) / sizeof(BIT_mask[0]))
+
+/*-**************************************************************
+*  bitStream encoding
+****************************************************************/
+/*! BIT_initCStream() :
+ *  `dstCapacity` must be > sizeof(size_t)
+ *  @return : 0 if success,
+ *            otherwise an error code (can be tested using ERR_isError()) */
+MEM_STATIC size_t BIT_initCStream(BIT_CStream_t* bitC,
+                                  void* startPtr, size_t dstCapacity)
+{
+    bitC->bitContainer = 0;
+    bitC->bitPos = 0;
+    bitC->startPtr = (char*)startPtr;
+    bitC->ptr = bitC->startPtr;
+    bitC->endPtr = bitC->startPtr + dstCapacity - sizeof(bitC->bitContainer);
+    if (dstCapacity <= sizeof(bitC->bitContainer)) return ERROR(dstSize_tooSmall);
+    return 0;
+}
+
+FORCE_INLINE_TEMPLATE BitContainerType BIT_getLowerBits(BitContainerType bitContainer, U32 const nbBits)
+{
+#if STATIC_BMI2 && !defined(ZSTD_NO_INTRINSICS)
+#  if (defined(__x86_64__) || defined(_M_X64)) && !defined(__ILP32__)
+    return _bzhi_u64(bitContainer, nbBits);
+#  else
+    DEBUG_STATIC_ASSERT(sizeof(bitContainer) == sizeof(U32));
+    return _bzhi_u32(bitContainer, nbBits);
+#  endif
+#else
+    assert(nbBits < BIT_MASK_SIZE);
+    return bitContainer & BIT_mask[nbBits];
+#endif
+}
+
+/*! BIT_addBits() :
+ *  can add up to 31 bits into `bitC`.
+ *  Note : does not check for register overflow ! */
+MEM_STATIC void BIT_addBits(BIT_CStream_t* bitC,
+                            BitContainerType value, unsigned nbBits)
+{
+    DEBUG_STATIC_ASSERT(BIT_MASK_SIZE == 32);
+    assert(nbBits < BIT_MASK_SIZE);
+    assert(nbBits + bitC->bitPos < sizeof(bitC->bitContainer) * 8);
+    bitC->bitContainer |= BIT_getLowerBits(value, nbBits) << bitC->bitPos;
+    bitC->bitPos += nbBits;
+}
+
+/*! BIT_addBitsFast() :
+ *  works only if `value` is _clean_,
+ *  meaning all high bits above nbBits are 0 */
+MEM_STATIC void BIT_addBitsFast(BIT_CStream_t* bitC,
+                                BitContainerType value, unsigned nbBits)
+{
+    assert((value>>nbBits) == 0);
+    assert(nbBits + bitC->bitPos < sizeof(bitC->bitContainer) * 8);
+    bitC->bitContainer |= value << bitC->bitPos;
+    bitC->bitPos += nbBits;
+}
+
+/*! BIT_flushBitsFast() :
+ *  assumption : bitContainer has not overflowed
+ *  unsafe version; does not check buffer overflow */
+MEM_STATIC void BIT_flushBitsFast(BIT_CStream_t* bitC)
+{
+    size_t const nbBytes = bitC->bitPos >> 3;
+    assert(bitC->bitPos < sizeof(bitC->bitContainer) * 8);
+    assert(bitC->ptr <= bitC->endPtr);
+    MEM_writeLEST(bitC->ptr, bitC->bitContainer);
+    bitC->ptr += nbBytes;
+    bitC->bitPos &= 7;
+    bitC->bitContainer >>= nbBytes*8;
+}
+
+/*! BIT_flushBits() :
+ *  assumption : bitContainer has not overflowed
+ *  safe version; check for buffer overflow, and prevents it.
+ *  note : does not signal buffer overflow.
+ *  overflow will be revealed later on using BIT_closeCStream() */
+MEM_STATIC void BIT_flushBits(BIT_CStream_t* bitC)
+{
+    size_t const nbBytes = bitC->bitPos >> 3;
+    assert(bitC->bitPos < sizeof(bitC->bitContainer) * 8);
+    assert(bitC->ptr <= bitC->endPtr);
+    MEM_writeLEST(bitC->ptr, bitC->bitContainer);
+    bitC->ptr += nbBytes;
+    if (bitC->ptr > bitC->endPtr) bitC->ptr = bitC->endPtr;
+    bitC->bitPos &= 7;
+    bitC->bitContainer >>= nbBytes*8;
+}
+
+/*! BIT_closeCStream() :
+ *  @return : size of CStream, in bytes,
+ *            or 0 if it could not fit into dstBuffer */
+MEM_STATIC size_t BIT_closeCStream(BIT_CStream_t* bitC)
+{
+    BIT_addBitsFast(bitC, 1, 1);   /* endMark */
+    BIT_flushBits(bitC);
+    if (bitC->ptr >= bitC->endPtr) return 0; /* overflow detected */
+    return (size_t)(bitC->ptr - bitC->startPtr) + (bitC->bitPos > 0);
+}
+
+
+/*-********************************************************
+*  bitStream decoding
+**********************************************************/
+/*! BIT_initDStream() :
+ *  Initialize a BIT_DStream_t.
+ * `bitD` : a pointer to an already allocated BIT_DStream_t structure.
+ * `srcSize` must be the *exact* size of the bitStream, in bytes.
+ * @return : size of stream (== srcSize), or an errorCode if a problem is detected
+ */
+MEM_STATIC size_t BIT_initDStream(BIT_DStream_t* bitD, const void* srcBuffer, size_t srcSize)
+{
+    if (srcSize < 1) { ZSTD_memset(bitD, 0, sizeof(*bitD)); return ERROR(srcSize_wrong); }
+
+    bitD->start = (const char*)srcBuffer;
+    bitD->limitPtr = bitD->start + sizeof(bitD->bitContainer);
+
+    if (srcSize >=  sizeof(bitD->bitContainer)) {  /* normal case */
+        bitD->ptr   = (const char*)srcBuffer + srcSize - sizeof(bitD->bitContainer);
+        bitD->bitContainer = MEM_readLEST(bitD->ptr);
+        { BYTE const lastByte = ((const BYTE*)srcBuffer)[srcSize-1];
+          bitD->bitsConsumed = lastByte ? 8 - ZSTD_highbit32(lastByte) : 0;  /* ensures bitsConsumed is always set */
+          if (lastByte == 0) return ERROR(GENERIC); /* endMark not present */ }
+    } else {
+        bitD->ptr   = bitD->start;
+        bitD->bitContainer = *(const BYTE*)(bitD->start);
+        switch(srcSize)
+        {
+        case 7: bitD->bitContainer += (BitContainerType)(((const BYTE*)(srcBuffer))[6]) << (sizeof(bitD->bitContainer)*8 - 16);
+                ZSTD_FALLTHROUGH;
+
+        case 6: bitD->bitContainer += (BitContainerType)(((const BYTE*)(srcBuffer))[5]) << (sizeof(bitD->bitContainer)*8 - 24);
+                ZSTD_FALLTHROUGH;
+
+        case 5: bitD->bitContainer += (BitContainerType)(((const BYTE*)(srcBuffer))[4]) << (sizeof(bitD->bitContainer)*8 - 32);
+                ZSTD_FALLTHROUGH;
+
+        case 4: bitD->bitContainer += (BitContainerType)(((const BYTE*)(srcBuffer))[3]) << 24;
+                ZSTD_FALLTHROUGH;
+
+        case 3: bitD->bitContainer += (BitContainerType)(((const BYTE*)(srcBuffer))[2]) << 16;
+                ZSTD_FALLTHROUGH;
+
+        case 2: bitD->bitContainer += (BitContainerType)(((const BYTE*)(srcBuffer))[1]) <<  8;
+                ZSTD_FALLTHROUGH;
+
+        default: break;
+        }
+        {   BYTE const lastByte = ((const BYTE*)srcBuffer)[srcSize-1];
+            bitD->bitsConsumed = lastByte ? 8 - ZSTD_highbit32(lastByte) : 0;
+            if (lastByte == 0) return ERROR(corruption_detected);  /* endMark not present */
+        }
+        bitD->bitsConsumed += (U32)(sizeof(bitD->bitContainer) - srcSize)*8;
+    }
+
+    return srcSize;
+}
+
+FORCE_INLINE_TEMPLATE BitContainerType BIT_getUpperBits(BitContainerType bitContainer, U32 const start)
+{
+    return bitContainer >> start;
+}
+
+FORCE_INLINE_TEMPLATE BitContainerType BIT_getMiddleBits(BitContainerType bitContainer, U32 const start, U32 const nbBits)
+{
+    U32 const regMask = sizeof(bitContainer)*8 - 1;
+    /* if start > regMask, bitstream is corrupted, and result is undefined */
+    assert(nbBits < BIT_MASK_SIZE);
+    /* x86 transform & ((1 << nbBits) - 1) to bzhi instruction, it is better
+     * than accessing memory. When bmi2 instruction is not present, we consider
+     * such cpus old (pre-Haswell, 2013) and their performance is not of that
+     * importance.
+     */
+#if defined(__x86_64__) || defined(_M_X64)
+    return (bitContainer >> (start & regMask)) & ((((U64)1) << nbBits) - 1);
+#else
+    return (bitContainer >> (start & regMask)) & BIT_mask[nbBits];
+#endif
+}
+
+/*! BIT_lookBits() :
+ *  Provides next n bits from local register.
+ *  local register is not modified.
+ *  On 32-bits, maxNbBits==24.
+ *  On 64-bits, maxNbBits==56.
+ * @return : value extracted */
+FORCE_INLINE_TEMPLATE BitContainerType BIT_lookBits(const BIT_DStream_t*  bitD, U32 nbBits)
+{
+    /* arbitrate between double-shift and shift+mask */
+#if 1
+    /* if bitD->bitsConsumed + nbBits > sizeof(bitD->bitContainer)*8,
+     * bitstream is likely corrupted, and result is undefined */
+    return BIT_getMiddleBits(bitD->bitContainer, (sizeof(bitD->bitContainer)*8) - bitD->bitsConsumed - nbBits, nbBits);
+#else
+    /* this code path is slower on my os-x laptop */
+    U32 const regMask = sizeof(bitD->bitContainer)*8 - 1;
+    return ((bitD->bitContainer << (bitD->bitsConsumed & regMask)) >> 1) >> ((regMask-nbBits) & regMask);
+#endif
+}
+
+/*! BIT_lookBitsFast() :
+ *  unsafe version; only works if nbBits >= 1 */
+MEM_STATIC BitContainerType BIT_lookBitsFast(const BIT_DStream_t* bitD, U32 nbBits)
+{
+    U32 const regMask = sizeof(bitD->bitContainer)*8 - 1;
+    assert(nbBits >= 1);
+    return (bitD->bitContainer << (bitD->bitsConsumed & regMask)) >> (((regMask+1)-nbBits) & regMask);
+}
+
+FORCE_INLINE_TEMPLATE void BIT_skipBits(BIT_DStream_t* bitD, U32 nbBits)
+{
+    bitD->bitsConsumed += nbBits;
+}
+
+/*! BIT_readBits() :
+ *  Read (consume) next n bits from local register and update.
+ *  Pay attention to not read more than nbBits contained into local register.
+ * @return : extracted value. */
+FORCE_INLINE_TEMPLATE BitContainerType BIT_readBits(BIT_DStream_t* bitD, unsigned nbBits)
+{
+    BitContainerType const value = BIT_lookBits(bitD, nbBits);
+    BIT_skipBits(bitD, nbBits);
+    return value;
+}
+
+/*! BIT_readBitsFast() :
+ *  unsafe version; only works if nbBits >= 1 */
+MEM_STATIC BitContainerType BIT_readBitsFast(BIT_DStream_t* bitD, unsigned nbBits)
+{
+    BitContainerType const value = BIT_lookBitsFast(bitD, nbBits);
+    assert(nbBits >= 1);
+    BIT_skipBits(bitD, nbBits);
+    return value;
+}
+
+/*! BIT_reloadDStream_internal() :
+ *  Simple variant of BIT_reloadDStream(), with two conditions:
+ *  1. bitstream is valid : bitsConsumed <= sizeof(bitD->bitContainer)*8
+ *  2. look window is valid after shifted down : bitD->ptr >= bitD->start
+ */
+MEM_STATIC BIT_DStream_status BIT_reloadDStream_internal(BIT_DStream_t* bitD)
+{
+    assert(bitD->bitsConsumed <= sizeof(bitD->bitContainer)*8);
+    bitD->ptr -= bitD->bitsConsumed >> 3;
+    assert(bitD->ptr >= bitD->start);
+    bitD->bitsConsumed &= 7;
+    bitD->bitContainer = MEM_readLEST(bitD->ptr);
+    return BIT_DStream_unfinished;
+}
+
+/*! BIT_reloadDStreamFast() :
+ *  Similar to BIT_reloadDStream(), but with two differences:
+ *  1. bitsConsumed <= sizeof(bitD->bitContainer)*8 must hold!
+ *  2. Returns BIT_DStream_overflow when bitD->ptr < bitD->limitPtr, at this
+ *     point you must use BIT_reloadDStream() to reload.
+ */
+MEM_STATIC BIT_DStream_status BIT_reloadDStreamFast(BIT_DStream_t* bitD)
+{
+    if (UNLIKELY(bitD->ptr < bitD->limitPtr))
+        return BIT_DStream_overflow;
+    return BIT_reloadDStream_internal(bitD);
+}
+
+/*! BIT_reloadDStream() :
+ *  Refill `bitD` from buffer previously set in BIT_initDStream() .
+ *  This function is safe, it guarantees it will not never beyond src buffer.
+ * @return : status of `BIT_DStream_t` internal register.
+ *           when status == BIT_DStream_unfinished, internal register is filled with at least 25 or 57 bits */
+FORCE_INLINE_TEMPLATE BIT_DStream_status BIT_reloadDStream(BIT_DStream_t* bitD)
+{
+    /* note : once in overflow mode, a bitstream remains in this mode until it's reset */
+    if (UNLIKELY(bitD->bitsConsumed > (sizeof(bitD->bitContainer)*8))) {
+        static const BitContainerType zeroFilled = 0;
+        bitD->ptr = (const char*)&zeroFilled; /* aliasing is allowed for char */
+        /* overflow detected, erroneous scenario or end of stream: no update */
+        return BIT_DStream_overflow;
+    }
+
+    assert(bitD->ptr >= bitD->start);
+
+    if (bitD->ptr >= bitD->limitPtr) {
+        return BIT_reloadDStream_internal(bitD);
+    }
+    if (bitD->ptr == bitD->start) {
+        /* reached end of bitStream => no update */
+        if (bitD->bitsConsumed < sizeof(bitD->bitContainer)*8) return BIT_DStream_endOfBuffer;
+        return BIT_DStream_completed;
+    }
+    /* start < ptr < limitPtr => cautious update */
+    {   U32 nbBytes = bitD->bitsConsumed >> 3;
+        BIT_DStream_status result = BIT_DStream_unfinished;
+        if (bitD->ptr - nbBytes < bitD->start) {
+            nbBytes = (U32)(bitD->ptr - bitD->start);  /* ptr > start */
+            result = BIT_DStream_endOfBuffer;
+        }
+        bitD->ptr -= nbBytes;
+        bitD->bitsConsumed -= nbBytes*8;
+        bitD->bitContainer = MEM_readLEST(bitD->ptr);   /* reminder : srcSize > sizeof(bitD->bitContainer), otherwise bitD->ptr == bitD->start */
+        return result;
+    }
+}
+
+/*! BIT_endOfDStream() :
+ * @return : 1 if DStream has _exactly_ reached its end (all bits consumed).
+ */
+MEM_STATIC unsigned BIT_endOfDStream(const BIT_DStream_t* DStream)
+{
+    return ((DStream->ptr == DStream->start) && (DStream->bitsConsumed == sizeof(DStream->bitContainer)*8));
+}
+
+#endif /* BITSTREAM_H_MODULE */
diff --git a/src/commonlib/bsd/zstd/common/cpu.h b/src/commonlib/bsd/zstd/common/cpu.h
new file mode 100644
index 0000000000..7f841fea6c
--- /dev/null
+++ b/src/commonlib/bsd/zstd/common/cpu.h
@@ -0,0 +1,251 @@
+/* SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0-only */
+
+/*
+ * Copyright (c) Meta Platforms, Inc. and affiliates.
+ * All rights reserved.
+ *
+ * This source code is licensed under both the BSD-style license (found in the
+ * LICENSE file in the root directory of this source tree) and the GPLv2 (found
+ * in the COPYING file in the root directory of this source tree).
+ * You may select, at your option, one of the above-listed licenses.
+ */
+
+#ifndef ZSTD_COMMON_CPU_H
+#define ZSTD_COMMON_CPU_H
+
+/**
+ * Implementation taken from folly/CpuId.h
+ * https://github.com/facebook/folly/blob/master/folly/CpuId.h
+ */
+
+#include "mem.h"
+
+#ifdef _MSC_VER
+#include <intrin.h>
+#endif
+
+typedef struct {
+    U32 f1c;
+    U32 f1d;
+    U32 f7b;
+    U32 f7c;
+} ZSTD_cpuid_t;
+
+MEM_STATIC ZSTD_cpuid_t ZSTD_cpuid(void) {
+    U32 f1c = 0;
+    U32 f1d = 0;
+    U32 f7b = 0;
+    U32 f7c = 0;
+#if defined(_MSC_VER) && (defined(_M_X64) || defined(_M_IX86))
+#if !defined(_M_X64) || !defined(__clang__) || __clang_major__ >= 16
+    int reg[4];
+    __cpuid((int*)reg, 0);
+    {
+        int const n = reg[0];
+        if (n >= 1) {
+            __cpuid((int*)reg, 1);
+            f1c = (U32)reg[2];
+            f1d = (U32)reg[3];
+        }
+        if (n >= 7) {
+            __cpuidex((int*)reg, 7, 0);
+            f7b = (U32)reg[1];
+            f7c = (U32)reg[2];
+        }
+    }
+#else
+    /* Clang compiler has a bug (fixed in https://reviews.llvm.org/D101338) in
+     * which the `__cpuid` intrinsic does not save and restore `rbx` as it needs
+     * to due to being a reserved register. So in that case, do the `cpuid`
+     * ourselves. Clang supports inline assembly anyway.
+     */
+    U32 n;
+    __asm__(
+        "pushq %%rbx\n\t"
+        "cpuid\n\t"
+        "popq %%rbx\n\t"
+        : "=a"(n)
+        : "a"(0)
+        : "rcx", "rdx");
+    if (n >= 1) {
+      U32 f1a;
+      __asm__(
+          "pushq %%rbx\n\t"
+          "cpuid\n\t"
+          "popq %%rbx\n\t"
+          : "=a"(f1a), "=c"(f1c), "=d"(f1d)
+          : "a"(1)
+          :);
+    }
+    if (n >= 7) {
+      __asm__(
+          "pushq %%rbx\n\t"
+          "cpuid\n\t"
+          "movq %%rbx, %%rax\n\t"
+          "popq %%rbx"
+          : "=a"(f7b), "=c"(f7c)
+          : "a"(7), "c"(0)
+          : "rdx");
+    }
+#endif
+#elif defined(__i386__) && defined(__PIC__) && !defined(__clang__) && defined(__GNUC__)
+    /* The following block like the normal cpuid branch below, but gcc
+     * reserves ebx for use of its pic register so we must specially
+     * handle the save and restore to avoid clobbering the register
+     */
+    U32 n;
+    __asm__(
+        "pushl %%ebx\n\t"
+        "cpuid\n\t"
+        "popl %%ebx\n\t"
+        : "=a"(n)
+        : "a"(0)
+        : "ecx", "edx");
+    if (n >= 1) {
+      U32 f1a;
+      __asm__(
+          "pushl %%ebx\n\t"
+          "cpuid\n\t"
+          "popl %%ebx\n\t"
+          : "=a"(f1a), "=c"(f1c), "=d"(f1d)
+          : "a"(1));
+    }
+    if (n >= 7) {
+      __asm__(
+          "pushl %%ebx\n\t"
+          "cpuid\n\t"
+          "movl %%ebx, %%eax\n\t"
+          "popl %%ebx"
+          : "=a"(f7b), "=c"(f7c)
+          : "a"(7), "c"(0)
+          : "edx");
+    }
+#elif defined(__x86_64__) || defined(_M_X64) || defined(__i386__)
+    U32 n;
+    __asm__("cpuid" : "=a"(n) : "a"(0) : "ebx", "ecx", "edx");
+    if (n >= 1) {
+      U32 f1a;
+      __asm__("cpuid" : "=a"(f1a), "=c"(f1c), "=d"(f1d) : "a"(1) : "ebx");
+    }
+    if (n >= 7) {
+      U32 f7a;
+      __asm__("cpuid"
+              : "=a"(f7a), "=b"(f7b), "=c"(f7c)
+              : "a"(7), "c"(0)
+              : "edx");
+    }
+#endif
+    {
+        ZSTD_cpuid_t cpuid;
+        cpuid.f1c = f1c;
+        cpuid.f1d = f1d;
+        cpuid.f7b = f7b;
+        cpuid.f7c = f7c;
+        return cpuid;
+    }
+}
+
+#define X(name, r, bit)                                                        \
+  MEM_STATIC int ZSTD_cpuid_##name(ZSTD_cpuid_t const cpuid) {                 \
+    return ((cpuid.r) & (1U << bit)) != 0;                                     \
+  }
+
+/* cpuid(1): Processor Info and Feature Bits. */
+#define C(name, bit) X(name, f1c, bit)
+  C(sse3, 0)
+  C(pclmuldq, 1)
+  C(dtes64, 2)
+  C(monitor, 3)
+  C(dscpl, 4)
+  C(vmx, 5)
+  C(smx, 6)
+  C(eist, 7)
+  C(tm2, 8)
+  C(ssse3, 9)
+  C(cnxtid, 10)
+  C(fma, 12)
+  C(cx16, 13)
+  C(xtpr, 14)
+  C(pdcm, 15)
+  C(pcid, 17)
+  C(dca, 18)
+  C(sse41, 19)
+  C(sse42, 20)
+  C(x2apic, 21)
+  C(movbe, 22)
+  C(popcnt, 23)
+  C(tscdeadline, 24)
+  C(aes, 25)
+  C(xsave, 26)
+  C(osxsave, 27)
+  C(avx, 28)
+  C(f16c, 29)
+  C(rdrand, 30)
+#undef C
+#define D(name, bit) X(name, f1d, bit)
+  D(fpu, 0)
+  D(vme, 1)
+  D(de, 2)
+  D(pse, 3)
+  D(tsc, 4)
+  D(msr, 5)
+  D(pae, 6)
+  D(mce, 7)
+  D(cx8, 8)
+  D(apic, 9)
+  D(sep, 11)
+  D(mtrr, 12)
+  D(pge, 13)
+  D(mca, 14)
+  D(cmov, 15)
+  D(pat, 16)
+  D(pse36, 17)
+  D(psn, 18)
+  D(clfsh, 19)
+  D(ds, 21)
+  D(acpi, 22)
+  D(mmx, 23)
+  D(fxsr, 24)
+  D(sse, 25)
+  D(sse2, 26)
+  D(ss, 27)
+  D(htt, 28)
+  D(tm, 29)
+  D(pbe, 31)
+#undef D
+
+/* cpuid(7): Extended Features. */
+#define B(name, bit) X(name, f7b, bit)
+  B(bmi1, 3)
+  B(hle, 4)
+  B(avx2, 5)
+  B(smep, 7)
+  B(bmi2, 8)
+  B(erms, 9)
+  B(invpcid, 10)
+  B(rtm, 11)
+  B(mpx, 14)
+  B(avx512f, 16)
+  B(avx512dq, 17)
+  B(rdseed, 18)
+  B(adx, 19)
+  B(smap, 20)
+  B(avx512ifma, 21)
+  B(pcommit, 22)
+  B(clflushopt, 23)
+  B(clwb, 24)
+  B(avx512pf, 26)
+  B(avx512er, 27)
+  B(avx512cd, 28)
+  B(sha, 29)
+  B(avx512bw, 30)
+  B(avx512vl, 31)
+#undef B
+#define C(name, bit) X(name, f7c, bit)
+  C(prefetchwt1, 0)
+  C(avx512vbmi, 1)
+#undef C
+
+#undef X
+
+#endif /* ZSTD_COMMON_CPU_H */
diff --git a/src/commonlib/bsd/zstd/common/debug.c b/src/commonlib/bsd/zstd/common/debug.c
new file mode 100644
index 0000000000..c42634e21d
--- /dev/null
+++ b/src/commonlib/bsd/zstd/common/debug.c
@@ -0,0 +1,32 @@
+/* SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0-only */
+
+/* ******************************************************************
+ * debug
+ * Part of FSE library
+ * Copyright (c) Meta Platforms, Inc. and affiliates.
+ *
+ * You can contact the author at :
+ * - Source repository : https://github.com/Cyan4973/FiniteStateEntropy
+ *
+ * This source code is licensed under both the BSD-style license (found in the
+ * LICENSE file in the root directory of this source tree) and the GPLv2 (found
+ * in the COPYING file in the root directory of this source tree).
+ * You may select, at your option, one of the above-listed licenses.
+****************************************************************** */
+
+
+/*
+ * This module only hosts one global variable
+ * which can be used to dynamically influence the verbosity of traces,
+ * such as DEBUGLOG and RAWLOG
+ */
+
+#include "debug.h"
+
+#if !defined(ZSTD_LINUX_KERNEL) || (DEBUGLEVEL>=2)
+/* We only use this when DEBUGLEVEL>=2, but we get -Werror=pedantic errors if a
+ * translation unit is empty. So remove this from Linux kernel builds, but
+ * otherwise just leave it in.
+ */
+int g_debuglevel = DEBUGLEVEL;
+#endif
diff --git a/src/commonlib/bsd/zstd/common/debug.h b/src/commonlib/bsd/zstd/common/debug.h
new file mode 100644
index 0000000000..2634d9d70e
--- /dev/null
+++ b/src/commonlib/bsd/zstd/common/debug.h
@@ -0,0 +1,109 @@
+/* SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0-only */
+
+/* ******************************************************************
+ * debug
+ * Part of FSE library
+ * Copyright (c) Meta Platforms, Inc. and affiliates.
+ *
+ * You can contact the author at :
+ * - Source repository : https://github.com/Cyan4973/FiniteStateEntropy
+ *
+ * This source code is licensed under both the BSD-style license (found in the
+ * LICENSE file in the root directory of this source tree) and the GPLv2 (found
+ * in the COPYING file in the root directory of this source tree).
+ * You may select, at your option, one of the above-listed licenses.
+****************************************************************** */
+
+
+/*
+ * The purpose of this header is to enable debug functions.
+ * They regroup assert(), DEBUGLOG() and RAWLOG() for run-time,
+ * and DEBUG_STATIC_ASSERT() for compile-time.
+ *
+ * By default, DEBUGLEVEL==0, which means run-time debug is disabled.
+ *
+ * Level 1 enables assert() only.
+ * Starting level 2, traces can be generated and pushed to stderr.
+ * The higher the level, the more verbose the traces.
+ *
+ * It's possible to dynamically adjust level using variable g_debug_level,
+ * which is only declared if DEBUGLEVEL>=2,
+ * and is a global variable, not multi-thread protected (use with care)
+ */
+
+#ifndef DEBUG_H_12987983217
+#define DEBUG_H_12987983217
+
+
+/* static assert is triggered at compile time, leaving no runtime artefact.
+ * static assert only works with compile-time constants.
+ * Also, this variant can only be used inside a function. */
+#define DEBUG_STATIC_ASSERT(c) (void)sizeof(char[(c) ? 1 : -1])
+
+
+/* DEBUGLEVEL is expected to be defined externally,
+ * typically through compiler command line.
+ * Value must be a number. */
+#ifndef DEBUGLEVEL
+#  define DEBUGLEVEL 0
+#endif
+
+
+/* recommended values for DEBUGLEVEL :
+ * 0 : release mode, no debug, all run-time checks disabled
+ * 1 : enables assert() only, no display
+ * 2 : reserved, for currently active debug path
+ * 3 : events once per object lifetime (CCtx, CDict, etc.)
+ * 4 : events once per frame
+ * 5 : events once per block
+ * 6 : events once per sequence (verbose)
+ * 7+: events at every position (*very* verbose)
+ *
+ * It's generally inconvenient to output traces > 5.
+ * In which case, it's possible to selectively trigger high verbosity levels
+ * by modifying g_debug_level.
+ */
+
+#if (DEBUGLEVEL>=1)
+#  define ZSTD_DEPS_NEED_ASSERT
+#  include "zstd_deps.h"
+#else
+#  ifndef assert   /* assert may be already defined, due to prior #include <assert.h> */
+#    define assert(condition) ((void)0)   /* disable assert (default) */
+#  endif
+#endif
+
+#if (DEBUGLEVEL>=2)
+#  define ZSTD_DEPS_NEED_IO
+#  include "zstd_deps.h"
+extern int g_debuglevel; /* the variable is only declared,
+                            it actually lives in debug.c,
+                            and is shared by the whole process.
+                            It's not thread-safe.
+                            It's useful when enabling very verbose levels
+                            on selective conditions (such as position in src) */
+
+#  define RAWLOG(l, ...)                   \
+    do {                                   \
+        if (l<=g_debuglevel) {             \
+            ZSTD_DEBUG_PRINT(__VA_ARGS__); \
+        }                                  \
+    } while (0)
+
+#define STRINGIFY(x) #x
+#define TOSTRING(x) STRINGIFY(x)
+#define LINE_AS_STRING TOSTRING(__LINE__)
+
+#  define DEBUGLOG(l, ...)                               \
+    do {                                                 \
+        if (l<=g_debuglevel) {                           \
+            ZSTD_DEBUG_PRINT(__FILE__ ":" LINE_AS_STRING ": " __VA_ARGS__); \
+            ZSTD_DEBUG_PRINT(" \n");                     \
+        }                                                \
+    } while (0)
+#else
+#  define RAWLOG(l, ...)   do { } while (0)    /* disabled */
+#  define DEBUGLOG(l, ...) do { } while (0)    /* disabled */
+#endif
+
+#endif /* DEBUG_H_12987983217 */
diff --git a/src/commonlib/bsd/zstd/common/entropy_common.c b/src/commonlib/bsd/zstd/common/entropy_common.c
new file mode 100644
index 0000000000..0b2a60a0dd
--- /dev/null
+++ b/src/commonlib/bsd/zstd/common/entropy_common.c
@@ -0,0 +1,342 @@
+/* SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0-only */
+
+/* ******************************************************************
+ * Common functions of New Generation Entropy library
+ * Copyright (c) Meta Platforms, Inc. and affiliates.
+ *
+ *  You can contact the author at :
+ *  - FSE+HUF source repository : https://github.com/Cyan4973/FiniteStateEntropy
+ *  - Public forum : https://groups.google.com/forum/#!forum/lz4c
+ *
+ * This source code is licensed under both the BSD-style license (found in the
+ * LICENSE file in the root directory of this source tree) and the GPLv2 (found
+ * in the COPYING file in the root directory of this source tree).
+ * You may select, at your option, one of the above-listed licenses.
+****************************************************************** */
+
+/* *************************************
+*  Dependencies
+***************************************/
+#include "mem.h"
+#include "error_private.h"       /* ERR_*, ERROR */
+#define FSE_STATIC_LINKING_ONLY  /* FSE_MIN_TABLELOG */
+#include "fse.h"
+#include "huf.h"
+#include "zstd_bits.h"                /* ZSDT_highbit32, ZSTD_countTrailingZeros32 */
+
+
+/*===   Version   ===*/
+unsigned FSE_versionNumber(void) { return FSE_VERSION_NUMBER; }
+
+
+/*===   Error Management   ===*/
+unsigned FSE_isError(size_t code) { return ERR_isError(code); }
+const char* FSE_getErrorName(size_t code) { return ERR_getErrorName(code); }
+
+unsigned HUF_isError(size_t code) { return ERR_isError(code); }
+const char* HUF_getErrorName(size_t code) { return ERR_getErrorName(code); }
+
+
+/*-**************************************************************
+*  FSE NCount encoding-decoding
+****************************************************************/
+FORCE_INLINE_TEMPLATE
+size_t FSE_readNCount_body(short* normalizedCounter, unsigned* maxSVPtr, unsigned* tableLogPtr,
+                           const void* headerBuffer, size_t hbSize)
+{
+    const BYTE* const istart = (const BYTE*) headerBuffer;
+    const BYTE* const iend = istart + hbSize;
+    const BYTE* ip = istart;
+    int nbBits;
+    int remaining;
+    int threshold;
+    U32 bitStream;
+    int bitCount;
+    unsigned charnum = 0;
+    unsigned const maxSV1 = *maxSVPtr + 1;
+    int previous0 = 0;
+
+    if (hbSize < 8) {
+        /* This function only works when hbSize >= 8 */
+        char buffer[8] = {0};
+        ZSTD_memcpy(buffer, headerBuffer, hbSize);
+        {   size_t const countSize = FSE_readNCount(normalizedCounter, maxSVPtr, tableLogPtr,
+                                                    buffer, sizeof(buffer));
+            if (FSE_isError(countSize)) return countSize;
+            if (countSize > hbSize) return ERROR(corruption_detected);
+            return countSize;
+    }   }
+    assert(hbSize >= 8);
+
+    /* init */
+    ZSTD_memset(normalizedCounter, 0, (*maxSVPtr+1) * sizeof(normalizedCounter[0]));   /* all symbols not present in NCount have a frequency of 0 */
+    bitStream = MEM_readLE32(ip);
+    nbBits = (bitStream & 0xF) + FSE_MIN_TABLELOG;   /* extract tableLog */
+    if (nbBits > FSE_TABLELOG_ABSOLUTE_MAX) return ERROR(tableLog_tooLarge);
+    bitStream >>= 4;
+    bitCount = 4;
+    *tableLogPtr = nbBits;
+    remaining = (1<<nbBits)+1;
+    threshold = 1<<nbBits;
+    nbBits++;
+
+    for (;;) {
+        if (previous0) {
+            /* Count the number of repeats. Each time the
+             * 2-bit repeat code is 0b11 there is another
+             * repeat.
+             * Avoid UB by setting the high bit to 1.
+             */
+            int repeats = ZSTD_countTrailingZeros32(~bitStream | 0x80000000) >> 1;
+            while (repeats >= 12) {
+                charnum += 3 * 12;
+                if (LIKELY(ip <= iend-7)) {
+                    ip += 3;
+                } else {
+                    bitCount -= (int)(8 * (iend - 7 - ip));
+                    bitCount &= 31;
+                    ip = iend - 4;
+                }
+                bitStream = MEM_readLE32(ip) >> bitCount;
+                repeats = ZSTD_countTrailingZeros32(~bitStream | 0x80000000) >> 1;
+            }
+            charnum += 3 * repeats;
+            bitStream >>= 2 * repeats;
+            bitCount += 2 * repeats;
+
+            /* Add the final repeat which isn't 0b11. */
+            assert((bitStream & 3) < 3);
+            charnum += bitStream & 3;
+            bitCount += 2;
+
+            /* This is an error, but break and return an error
+             * at the end, because returning out of a loop makes
+             * it harder for the compiler to optimize.
+             */
+            if (charnum >= maxSV1) break;
+
+            /* We don't need to set the normalized count to 0
+             * because we already memset the whole buffer to 0.
+             */
+
+            if (LIKELY(ip <= iend-7) || (ip + (bitCount>>3) <= iend-4)) {
+                assert((bitCount >> 3) <= 3); /* For first condition to work */
+                ip += bitCount>>3;
+                bitCount &= 7;
+            } else {
+                bitCount -= (int)(8 * (iend - 4 - ip));
+                bitCount &= 31;
+                ip = iend - 4;
+            }
+            bitStream = MEM_readLE32(ip) >> bitCount;
+        }
+        {
+            int const max = (2*threshold-1) - remaining;
+            int count;
+
+            if ((bitStream & (threshold-1)) < (U32)max) {
+                count = bitStream & (threshold-1);
+                bitCount += nbBits-1;
+            } else {
+                count = bitStream & (2*threshold-1);
+                if (count >= threshold) count -= max;
+                bitCount += nbBits;
+            }
+
+            count--;   /* extra accuracy */
+            /* When it matters (small blocks), this is a
+             * predictable branch, because we don't use -1.
+             */
+            if (count >= 0) {
+                remaining -= count;
+            } else {
+                assert(count == -1);
+                remaining += count;
+            }
+            normalizedCounter[charnum++] = (short)count;
+            previous0 = !count;
+
+            assert(threshold > 1);
+            if (remaining < threshold) {
+                /* This branch can be folded into the
+                 * threshold update condition because we
+                 * know that threshold > 1.
+                 */
+                if (remaining <= 1) break;
+                nbBits = ZSTD_highbit32(remaining) + 1;
+                threshold = 1 << (nbBits - 1);
+            }
+            if (charnum >= maxSV1) break;
+
+            if (LIKELY(ip <= iend-7) || (ip + (bitCount>>3) <= iend-4)) {
+                ip += bitCount>>3;
+                bitCount &= 7;
+            } else {
+                bitCount -= (int)(8 * (iend - 4 - ip));
+                bitCount &= 31;
+                ip = iend - 4;
+            }
+            bitStream = MEM_readLE32(ip) >> bitCount;
+    }   }
+    if (remaining != 1) return ERROR(corruption_detected);
+    /* Only possible when there are too many zeros. */
+    if (charnum > maxSV1) return ERROR(maxSymbolValue_tooSmall);
+    if (bitCount > 32) return ERROR(corruption_detected);
+    *maxSVPtr = charnum-1;
+
+    ip += (bitCount+7)>>3;
+    return ip-istart;
+}
+
+/* Avoids the FORCE_INLINE of the _body() function. */
+static size_t FSE_readNCount_body_default(
+        short* normalizedCounter, unsigned* maxSVPtr, unsigned* tableLogPtr,
+        const void* headerBuffer, size_t hbSize)
+{
+    return FSE_readNCount_body(normalizedCounter, maxSVPtr, tableLogPtr, headerBuffer, hbSize);
+}
+
+#if DYNAMIC_BMI2
+BMI2_TARGET_ATTRIBUTE static size_t FSE_readNCount_body_bmi2(
+        short* normalizedCounter, unsigned* maxSVPtr, unsigned* tableLogPtr,
+        const void* headerBuffer, size_t hbSize)
+{
+    return FSE_readNCount_body(normalizedCounter, maxSVPtr, tableLogPtr, headerBuffer, hbSize);
+}
+#endif
+
+size_t FSE_readNCount_bmi2(
+        short* normalizedCounter, unsigned* maxSVPtr, unsigned* tableLogPtr,
+        const void* headerBuffer, size_t hbSize, int bmi2)
+{
+#if DYNAMIC_BMI2
+    if (bmi2) {
+        return FSE_readNCount_body_bmi2(normalizedCounter, maxSVPtr, tableLogPtr, headerBuffer, hbSize);
+    }
+#endif
+    (void)bmi2;
+    return FSE_readNCount_body_default(normalizedCounter, maxSVPtr, tableLogPtr, headerBuffer, hbSize);
+}
+
+size_t FSE_readNCount(
+        short* normalizedCounter, unsigned* maxSVPtr, unsigned* tableLogPtr,
+        const void* headerBuffer, size_t hbSize)
+{
+    return FSE_readNCount_bmi2(normalizedCounter, maxSVPtr, tableLogPtr, headerBuffer, hbSize, /* bmi2 */ 0);
+}
+
+
+/*! HUF_readStats() :
+    Read compact Huffman tree, saved by HUF_writeCTable().
+    `huffWeight` is destination buffer.
+    `rankStats` is assumed to be a table of at least HUF_TABLELOG_MAX U32.
+    @return : size read from `src` , or an error Code .
+    Note : Needed by HUF_readCTable() and HUF_readDTableX?() .
+*/
+size_t HUF_readStats(BYTE* huffWeight, size_t hwSize, U32* rankStats,
+                     U32* nbSymbolsPtr, U32* tableLogPtr,
+                     const void* src, size_t srcSize)
+{
+    U32 wksp[HUF_READ_STATS_WORKSPACE_SIZE_U32];
+    return HUF_readStats_wksp(huffWeight, hwSize, rankStats, nbSymbolsPtr, tableLogPtr, src, srcSize, wksp, sizeof(wksp), /* flags */ 0);
+}
+
+FORCE_INLINE_TEMPLATE size_t
+HUF_readStats_body(BYTE* huffWeight, size_t hwSize, U32* rankStats,
+                   U32* nbSymbolsPtr, U32* tableLogPtr,
+                   const void* src, size_t srcSize,
+                   void* workSpace, size_t wkspSize,
+                   int bmi2)
+{
+    U32 weightTotal;
+    const BYTE* ip = (const BYTE*) src;
+    size_t iSize;
+    size_t oSize;
+
+    if (!srcSize) return ERROR(srcSize_wrong);
+    iSize = ip[0];
+    /* ZSTD_memset(huffWeight, 0, hwSize);   *//* is not necessary, even though some analyzer complain ... */
+
+    if (iSize >= 128) {  /* special header */
+        oSize = iSize - 127;
+        iSize = ((oSize+1)/2);
+        if (iSize+1 > srcSize) return ERROR(srcSize_wrong);
+        if (oSize >= hwSize) return ERROR(corruption_detected);
+        ip += 1;
+        {   U32 n;
+            for (n=0; n<oSize; n+=2) {
+                huffWeight[n]   = ip[n/2] >> 4;
+                huffWeight[n+1] = ip[n/2] & 15;
+    }   }   }
+    else  {   /* header compressed with FSE (normal case) */
+        if (iSize+1 > srcSize) return ERROR(srcSize_wrong);
+        /* max (hwSize-1) values decoded, as last one is implied */
+        oSize = FSE_decompress_wksp_bmi2(huffWeight, hwSize-1, ip+1, iSize, 6, workSpace, wkspSize, bmi2);
+        if (FSE_isError(oSize)) return oSize;
+    }
+
+    /* collect weight stats */
+    ZSTD_memset(rankStats, 0, (HUF_TABLELOG_MAX + 1) * sizeof(U32));
+    weightTotal = 0;
+    {   U32 n; for (n=0; n<oSize; n++) {
+            if (huffWeight[n] > HUF_TABLELOG_MAX) return ERROR(corruption_detected);
+            rankStats[huffWeight[n]]++;
+            weightTotal += (1 << huffWeight[n]) >> 1;
+    }   }
+    if (weightTotal == 0) return ERROR(corruption_detected);
+
+    /* get last non-null symbol weight (implied, total must be 2^n) */
+    {   U32 const tableLog = ZSTD_highbit32(weightTotal) + 1;
+        if (tableLog > HUF_TABLELOG_MAX) return ERROR(corruption_detected);
+        *tableLogPtr = tableLog;
+        /* determine last weight */
+        {   U32 const total = 1 << tableLog;
+            U32 const rest = total - weightTotal;
+            U32 const verif = 1 << ZSTD_highbit32(rest);
+            U32 const lastWeight = ZSTD_highbit32(rest) + 1;
+            if (verif != rest) return ERROR(corruption_detected);    /* last value must be a clean power of 2 */
+            huffWeight[oSize] = (BYTE)lastWeight;
+            rankStats[lastWeight]++;
+    }   }
+
+    /* check tree construction validity */
+    if ((rankStats[1] < 2) || (rankStats[1] & 1)) return ERROR(corruption_detected);   /* by construction : at least 2 elts of rank 1, must be even */
+
+    /* results */
+    *nbSymbolsPtr = (U32)(oSize+1);
+    return iSize+1;
+}
+
+/* Avoids the FORCE_INLINE of the _body() function. */
+static size_t HUF_readStats_body_default(BYTE* huffWeight, size_t hwSize, U32* rankStats,
+                     U32* nbSymbolsPtr, U32* tableLogPtr,
+                     const void* src, size_t srcSize,
+                     void* workSpace, size_t wkspSize)
+{
+    return HUF_readStats_body(huffWeight, hwSize, rankStats, nbSymbolsPtr, tableLogPtr, src, srcSize, workSpace, wkspSize, 0);
+}
+
+#if DYNAMIC_BMI2
+static BMI2_TARGET_ATTRIBUTE size_t HUF_readStats_body_bmi2(BYTE* huffWeight, size_t hwSize, U32* rankStats,
+                     U32* nbSymbolsPtr, U32* tableLogPtr,
+                     const void* src, size_t srcSize,
+                     void* workSpace, size_t wkspSize)
+{
+    return HUF_readStats_body(huffWeight, hwSize, rankStats, nbSymbolsPtr, tableLogPtr, src, srcSize, workSpace, wkspSize, 1);
+}
+#endif
+
+size_t HUF_readStats_wksp(BYTE* huffWeight, size_t hwSize, U32* rankStats,
+                     U32* nbSymbolsPtr, U32* tableLogPtr,
+                     const void* src, size_t srcSize,
+                     void* workSpace, size_t wkspSize,
+                     int flags)
+{
+#if DYNAMIC_BMI2
+    if (flags & HUF_flags_bmi2) {
+        return HUF_readStats_body_bmi2(huffWeight, hwSize, rankStats, nbSymbolsPtr, tableLogPtr, src, srcSize, workSpace, wkspSize);
+    }
+#endif
+    (void)flags;
+    return HUF_readStats_body_default(huffWeight, hwSize, rankStats, nbSymbolsPtr, tableLogPtr, src, srcSize, workSpace, wkspSize);
+}
diff --git a/src/commonlib/bsd/zstd/common/error_private.c b/src/commonlib/bsd/zstd/common/error_private.c
new file mode 100644
index 0000000000..2d8e3bdd61
--- /dev/null
+++ b/src/commonlib/bsd/zstd/common/error_private.c
@@ -0,0 +1,66 @@
+/* SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0-only */
+
+/*
+ * Copyright (c) Meta Platforms, Inc. and affiliates.
+ * All rights reserved.
+ *
+ * This source code is licensed under both the BSD-style license (found in the
+ * LICENSE file in the root directory of this source tree) and the GPLv2 (found
+ * in the COPYING file in the root directory of this source tree).
+ * You may select, at your option, one of the above-listed licenses.
+ */
+
+/* The purpose of this file is to have a single list of error strings embedded in binary */
+
+#include "error_private.h"
+
+const char* ERR_getErrorString(ERR_enum code)
+{
+#ifdef ZSTD_STRIP_ERROR_STRINGS
+    (void)code;
+    return "Error strings stripped";
+#else
+    static const char* const notErrorCode = "Unspecified error code";
+    switch( code )
+    {
+    case PREFIX(no_error): return "No error detected";
+    case PREFIX(GENERIC):  return "Error (generic)";
+    case PREFIX(prefix_unknown): return "Unknown frame descriptor";
+    case PREFIX(version_unsupported): return "Version not supported";
+    case PREFIX(frameParameter_unsupported): return "Unsupported frame parameter";
+    case PREFIX(frameParameter_windowTooLarge): return "Frame requires too much memory for decoding";
+    case PREFIX(corruption_detected): return "Data corruption detected";
+    case PREFIX(checksum_wrong): return "Restored data doesn't match checksum";
+    case PREFIX(literals_headerWrong): return "Header of Literals' block doesn't respect format specification";
+    case PREFIX(parameter_unsupported): return "Unsupported parameter";
+    case PREFIX(parameter_combination_unsupported): return "Unsupported combination of parameters";
+    case PREFIX(parameter_outOfBound): return "Parameter is out of bound";
+    case PREFIX(init_missing): return "Context should be init first";
+    case PREFIX(memory_allocation): return "Allocation error : not enough memory";
+    case PREFIX(workSpace_tooSmall): return "workSpace buffer is not large enough";
+    case PREFIX(stage_wrong): return "Operation not authorized at current processing stage";
+    case PREFIX(tableLog_tooLarge): return "tableLog requires too much memory : unsupported";
+    case PREFIX(maxSymbolValue_tooLarge): return "Unsupported max Symbol Value : too large";
+    case PREFIX(maxSymbolValue_tooSmall): return "Specified maxSymbolValue is too small";
+    case PREFIX(cannotProduce_uncompressedBlock): return "This mode cannot generate an uncompressed block";
+    case PREFIX(stabilityCondition_notRespected): return "pledged buffer stability condition is not respected";
+    case PREFIX(dictionary_corrupted): return "Dictionary is corrupted";
+    case PREFIX(dictionary_wrong): return "Dictionary mismatch";
+    case PREFIX(dictionaryCreation_failed): return "Cannot create Dictionary from provided samples";
+    case PREFIX(dstSize_tooSmall): return "Destination buffer is too small";
+    case PREFIX(srcSize_wrong): return "Src size is incorrect";
+    case PREFIX(dstBuffer_null): return "Operation on NULL destination buffer";
+    case PREFIX(noForwardProgress_destFull): return "Operation made no progress over multiple calls, due to output buffer being full";
+    case PREFIX(noForwardProgress_inputEmpty): return "Operation made no progress over multiple calls, due to input being empty";
+        /* following error codes are not stable and may be removed or changed in a future version */
+    case PREFIX(frameIndex_tooLarge): return "Frame index is too large";
+    case PREFIX(seekableIO): return "An I/O error occurred when reading/seeking";
+    case PREFIX(dstBuffer_wrong): return "Destination buffer is wrong";
+    case PREFIX(srcBuffer_wrong): return "Source buffer is wrong";
+    case PREFIX(sequenceProducer_failed): return "Block-level external sequence producer returned an error code";
+    case PREFIX(externalSequences_invalid): return "External sequences are not valid";
+    case PREFIX(maxCode):
+    default: return notErrorCode;
+    }
+#endif
+}
diff --git a/src/commonlib/bsd/zstd/common/error_private.h b/src/commonlib/bsd/zstd/common/error_private.h
new file mode 100644
index 0000000000..eeee67f52e
--- /dev/null
+++ b/src/commonlib/bsd/zstd/common/error_private.h
@@ -0,0 +1,160 @@
+/* SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0-only */
+
+/*
+ * Copyright (c) Meta Platforms, Inc. and affiliates.
+ * All rights reserved.
+ *
+ * This source code is licensed under both the BSD-style license (found in the
+ * LICENSE file in the root directory of this source tree) and the GPLv2 (found
+ * in the COPYING file in the root directory of this source tree).
+ * You may select, at your option, one of the above-listed licenses.
+ */
+
+/* Note : this module is expected to remain private, do not expose it */
+
+#ifndef ERROR_H_MODULE
+#define ERROR_H_MODULE
+
+/* ****************************************
+*  Dependencies
+******************************************/
+#include "../zstd_errors.h"  /* enum list */
+#include "zstd_compiler.h"
+#include "debug.h"
+#include "zstd_deps.h"       /* size_t */
+
+/* ****************************************
+*  Compiler-specific
+******************************************/
+#if defined(__GNUC__)
+#  define ERR_STATIC static __attribute__((unused))
+#elif defined (__cplusplus) || (defined (__STDC_VERSION__) && (__STDC_VERSION__ >= 199901L) /* C99 */)
+#  define ERR_STATIC static inline
+#elif defined(_MSC_VER)
+#  define ERR_STATIC static __inline
+#else
+#  define ERR_STATIC static  /* this version may generate warnings for unused static functions; disable the relevant warning */
+#endif
+
+
+/*-****************************************
+*  Customization (error_public.h)
+******************************************/
+typedef ZSTD_ErrorCode ERR_enum;
+#define PREFIX(name) ZSTD_error_##name
+
+
+/*-****************************************
+*  Error codes handling
+******************************************/
+#undef ERROR   /* already defined on Visual Studio */
+#define ERROR(name) ZSTD_ERROR(name)
+#define ZSTD_ERROR(name) ((size_t)-PREFIX(name))
+
+ERR_STATIC unsigned ERR_isError(size_t code) { return (code > ERROR(maxCode)); }
+
+ERR_STATIC ERR_enum ERR_getErrorCode(size_t code) { if (!ERR_isError(code)) return (ERR_enum)0; return (ERR_enum) (0-code); }
+
+/* check and forward error code */
+#define CHECK_V_F(e, f)     \
+    size_t const e = f;     \
+    do {                    \
+        if (ERR_isError(e)) \
+            return e;       \
+    } while (0)
+#define CHECK_F(f)   do { CHECK_V_F(_var_err__, f); } while (0)
+
+
+/*-****************************************
+*  Error Strings
+******************************************/
+
+const char* ERR_getErrorString(ERR_enum code);   /* error_private.c */
+
+ERR_STATIC const char* ERR_getErrorName(size_t code)
+{
+    return ERR_getErrorString(ERR_getErrorCode(code));
+}
+
+/**
+ * Ignore: this is an internal helper.
+ *
+ * This is a helper function to help force C99-correctness during compilation.
+ * Under strict compilation modes, variadic macro arguments can't be empty.
+ * However, variadic function arguments can be. Using a function therefore lets
+ * us statically check that at least one (string) argument was passed,
+ * independent of the compilation flags.
+ */
+static INLINE_KEYWORD UNUSED_ATTR
+void _force_has_format_string(const char *format, ...) {
+  (void)format;
+}
+
+/**
+ * Ignore: this is an internal helper.
+ *
+ * We want to force this function invocation to be syntactically correct, but
+ * we don't want to force runtime evaluation of its arguments.
+ */
+#define _FORCE_HAS_FORMAT_STRING(...)              \
+    do {                                           \
+        if (0) {                                   \
+            _force_has_format_string(__VA_ARGS__); \
+        }                                          \
+    } while (0)
+
+#define ERR_QUOTE(str) #str
+
+/**
+ * Return the specified error if the condition evaluates to true.
+ *
+ * In debug modes, prints additional information.
+ * In order to do that (particularly, printing the conditional that failed),
+ * this can't just wrap RETURN_ERROR().
+ */
+#define RETURN_ERROR_IF(cond, err, ...)                                        \
+    do {                                                                       \
+        if (cond) {                                                            \
+            RAWLOG(3, "%s:%d: ERROR!: check %s failed, returning %s",          \
+                  __FILE__, __LINE__, ERR_QUOTE(cond), ERR_QUOTE(ERROR(err))); \
+            _FORCE_HAS_FORMAT_STRING(__VA_ARGS__);                             \
+            RAWLOG(3, ": " __VA_ARGS__);                                       \
+            RAWLOG(3, "\n");                                                   \
+            return ERROR(err);                                                 \
+        }                                                                      \
+    } while (0)
+
+/**
+ * Unconditionally return the specified error.
+ *
+ * In debug modes, prints additional information.
+ */
+#define RETURN_ERROR(err, ...)                                               \
+    do {                                                                     \
+        RAWLOG(3, "%s:%d: ERROR!: unconditional check failed, returning %s", \
+              __FILE__, __LINE__, ERR_QUOTE(ERROR(err)));                    \
+        _FORCE_HAS_FORMAT_STRING(__VA_ARGS__);                               \
+        RAWLOG(3, ": " __VA_ARGS__);                                         \
+        RAWLOG(3, "\n");                                                     \
+        return ERROR(err);                                                   \
+    } while(0)
+
+/**
+ * If the provided expression evaluates to an error code, returns that error code.
+ *
+ * In debug modes, prints additional information.
+ */
+#define FORWARD_IF_ERROR(err, ...)                                                 \
+    do {                                                                           \
+        size_t const err_code = (err);                                             \
+        if (ERR_isError(err_code)) {                                               \
+            RAWLOG(3, "%s:%d: ERROR!: forwarding error in %s: %s",                 \
+                  __FILE__, __LINE__, ERR_QUOTE(err), ERR_getErrorName(err_code)); \
+            _FORCE_HAS_FORMAT_STRING(__VA_ARGS__);                                 \
+            RAWLOG(3, ": " __VA_ARGS__);                                           \
+            RAWLOG(3, "\n");                                                       \
+            return err_code;                                                       \
+        }                                                                          \
+    } while(0)
+
+#endif /* ERROR_H_MODULE */
diff --git a/src/commonlib/bsd/zstd/common/fse.h b/src/commonlib/bsd/zstd/common/fse.h
new file mode 100644
index 0000000000..2b450b9579
--- /dev/null
+++ b/src/commonlib/bsd/zstd/common/fse.h
@@ -0,0 +1,627 @@
+/* SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0-only */
+
+/* ******************************************************************
+ * FSE : Finite State Entropy codec
+ * Public Prototypes declaration
+ * Copyright (c) Meta Platforms, Inc. and affiliates.
+ *
+ * You can contact the author at :
+ * - Source repository : https://github.com/Cyan4973/FiniteStateEntropy
+ *
+ * This source code is licensed under both the BSD-style license (found in the
+ * LICENSE file in the root directory of this source tree) and the GPLv2 (found
+ * in the COPYING file in the root directory of this source tree).
+ * You may select, at your option, one of the above-listed licenses.
+****************************************************************** */
+#ifndef FSE_H
+#define FSE_H
+
+
+/*-*****************************************
+*  Dependencies
+******************************************/
+#include "zstd_deps.h"    /* size_t, ptrdiff_t */
+
+/*-*****************************************
+*  FSE_PUBLIC_API : control library symbols visibility
+******************************************/
+#if defined(FSE_DLL_EXPORT) && (FSE_DLL_EXPORT==1) && defined(__GNUC__) && (__GNUC__ >= 4)
+#  define FSE_PUBLIC_API __attribute__ ((visibility ("default")))
+#elif defined(FSE_DLL_EXPORT) && (FSE_DLL_EXPORT==1)   /* Visual expected */
+#  define FSE_PUBLIC_API __declspec(dllexport)
+#elif defined(FSE_DLL_IMPORT) && (FSE_DLL_IMPORT==1)
+#  define FSE_PUBLIC_API __declspec(dllimport) /* It isn't required but allows to generate better code, saving a function pointer load from the IAT and an indirect jump.*/
+#else
+#  define FSE_PUBLIC_API
+#endif
+
+/*------   Version   ------*/
+#define FSE_VERSION_MAJOR    0
+#define FSE_VERSION_MINOR    9
+#define FSE_VERSION_RELEASE  0
+
+#define FSE_LIB_VERSION FSE_VERSION_MAJOR.FSE_VERSION_MINOR.FSE_VERSION_RELEASE
+#define FSE_QUOTE(str) #str
+#define FSE_EXPAND_AND_QUOTE(str) FSE_QUOTE(str)
+#define FSE_VERSION_STRING FSE_EXPAND_AND_QUOTE(FSE_LIB_VERSION)
+
+#define FSE_VERSION_NUMBER  (FSE_VERSION_MAJOR *100*100 + FSE_VERSION_MINOR *100 + FSE_VERSION_RELEASE)
+FSE_PUBLIC_API unsigned FSE_versionNumber(void);   /**< library version number; to be used when checking dll version */
+
+
+/*-*****************************************
+*  Tool functions
+******************************************/
+FSE_PUBLIC_API size_t FSE_compressBound(size_t size);       /* maximum compressed size */
+
+/* Error Management */
+FSE_PUBLIC_API unsigned    FSE_isError(size_t code);        /* tells if a return value is an error code */
+FSE_PUBLIC_API const char* FSE_getErrorName(size_t code);   /* provides error code string (useful for debugging) */
+
+
+/*-*****************************************
+*  FSE detailed API
+******************************************/
+/*!
+FSE_compress() does the following:
+1. count symbol occurrence from source[] into table count[] (see hist.h)
+2. normalize counters so that sum(count[]) == Power_of_2 (2^tableLog)
+3. save normalized counters to memory buffer using writeNCount()
+4. build encoding table 'CTable' from normalized counters
+5. encode the data stream using encoding table 'CTable'
+
+FSE_decompress() does the following:
+1. read normalized counters with readNCount()
+2. build decoding table 'DTable' from normalized counters
+3. decode the data stream using decoding table 'DTable'
+
+The following API allows targeting specific sub-functions for advanced tasks.
+For example, it's possible to compress several blocks using the same 'CTable',
+or to save and provide normalized distribution using external method.
+*/
+
+/* *** COMPRESSION *** */
+
+/*! FSE_optimalTableLog():
+    dynamically downsize 'tableLog' when conditions are met.
+    It saves CPU time, by using smaller tables, while preserving or even improving compression ratio.
+    @return : recommended tableLog (necessarily <= 'maxTableLog') */
+FSE_PUBLIC_API unsigned FSE_optimalTableLog(unsigned maxTableLog, size_t srcSize, unsigned maxSymbolValue);
+
+/*! FSE_normalizeCount():
+    normalize counts so that sum(count[]) == Power_of_2 (2^tableLog)
+    'normalizedCounter' is a table of short, of minimum size (maxSymbolValue+1).
+    useLowProbCount is a boolean parameter which trades off compressed size for
+    faster header decoding. When it is set to 1, the compressed data will be slightly
+    smaller. And when it is set to 0, FSE_readNCount() and FSE_buildDTable() will be
+    faster. If you are compressing a small amount of data (< 2 KB) then useLowProbCount=0
+    is a good default, since header deserialization makes a big speed difference.
+    Otherwise, useLowProbCount=1 is a good default, since the speed difference is small.
+    @return : tableLog,
+              or an errorCode, which can be tested using FSE_isError() */
+FSE_PUBLIC_API size_t FSE_normalizeCount(short* normalizedCounter, unsigned tableLog,
+                    const unsigned* count, size_t srcSize, unsigned maxSymbolValue, unsigned useLowProbCount);
+
+/*! FSE_NCountWriteBound():
+    Provides the maximum possible size of an FSE normalized table, given 'maxSymbolValue' and 'tableLog'.
+    Typically useful for allocation purpose. */
+FSE_PUBLIC_API size_t FSE_NCountWriteBound(unsigned maxSymbolValue, unsigned tableLog);
+
+/*! FSE_writeNCount():
+    Compactly save 'normalizedCounter' into 'buffer'.
+    @return : size of the compressed table,
+              or an errorCode, which can be tested using FSE_isError(). */
+FSE_PUBLIC_API size_t FSE_writeNCount (void* buffer, size_t bufferSize,
+                                 const short* normalizedCounter,
+                                 unsigned maxSymbolValue, unsigned tableLog);
+
+/*! Constructor and Destructor of FSE_CTable.
+    Note that FSE_CTable size depends on 'tableLog' and 'maxSymbolValue' */
+typedef unsigned FSE_CTable;   /* don't allocate that. It's only meant to be more restrictive than void* */
+
+/*! FSE_buildCTable():
+    Builds `ct`, which must be already allocated, using FSE_createCTable().
+    @return : 0, or an errorCode, which can be tested using FSE_isError() */
+FSE_PUBLIC_API size_t FSE_buildCTable(FSE_CTable* ct, const short* normalizedCounter, unsigned maxSymbolValue, unsigned tableLog);
+
+/*! FSE_compress_usingCTable():
+    Compress `src` using `ct` into `dst` which must be already allocated.
+    @return : size of compressed data (<= `dstCapacity`),
+              or 0 if compressed data could not fit into `dst`,
+              or an errorCode, which can be tested using FSE_isError() */
+FSE_PUBLIC_API size_t FSE_compress_usingCTable (void* dst, size_t dstCapacity, const void* src, size_t srcSize, const FSE_CTable* ct);
+
+/*!
+Tutorial :
+----------
+The first step is to count all symbols. FSE_count() does this job very fast.
+Result will be saved into 'count', a table of unsigned int, which must be already allocated, and have 'maxSymbolValuePtr[0]+1' cells.
+'src' is a table of bytes of size 'srcSize'. All values within 'src' MUST be <= maxSymbolValuePtr[0]
+maxSymbolValuePtr[0] will be updated, with its real value (necessarily <= original value)
+FSE_count() will return the number of occurrence of the most frequent symbol.
+This can be used to know if there is a single symbol within 'src', and to quickly evaluate its compressibility.
+If there is an error, the function will return an ErrorCode (which can be tested using FSE_isError()).
+
+The next step is to normalize the frequencies.
+FSE_normalizeCount() will ensure that sum of frequencies is == 2 ^'tableLog'.
+It also guarantees a minimum of 1 to any Symbol with frequency >= 1.
+You can use 'tableLog'==0 to mean "use default tableLog value".
+If you are unsure of which tableLog value to use, you can ask FSE_optimalTableLog(),
+which will provide the optimal valid tableLog given sourceSize, maxSymbolValue, and a user-defined maximum (0 means "default").
+
+The result of FSE_normalizeCount() will be saved into a table,
+called 'normalizedCounter', which is a table of signed short.
+'normalizedCounter' must be already allocated, and have at least 'maxSymbolValue+1' cells.
+The return value is tableLog if everything proceeded as expected.
+It is 0 if there is a single symbol within distribution.
+If there is an error (ex: invalid tableLog value), the function will return an ErrorCode (which can be tested using FSE_isError()).
+
+'normalizedCounter' can be saved in a compact manner to a memory area using FSE_writeNCount().
+'buffer' must be already allocated.
+For guaranteed success, buffer size must be at least FSE_headerBound().
+The result of the function is the number of bytes written into 'buffer'.
+If there is an error, the function will return an ErrorCode (which can be tested using FSE_isError(); ex : buffer size too small).
+
+'normalizedCounter' can then be used to create the compression table 'CTable'.
+The space required by 'CTable' must be already allocated, using FSE_createCTable().
+You can then use FSE_buildCTable() to fill 'CTable'.
+If there is an error, both functions will return an ErrorCode (which can be tested using FSE_isError()).
+
+'CTable' can then be used to compress 'src', with FSE_compress_usingCTable().
+Similar to FSE_count(), the convention is that 'src' is assumed to be a table of char of size 'srcSize'
+The function returns the size of compressed data (without header), necessarily <= `dstCapacity`.
+If it returns '0', compressed data could not fit into 'dst'.
+If there is an error, the function will return an ErrorCode (which can be tested using FSE_isError()).
+*/
+
+
+/* *** DECOMPRESSION *** */
+
+/*! FSE_readNCount():
+    Read compactly saved 'normalizedCounter' from 'rBuffer'.
+    @return : size read from 'rBuffer',
+              or an errorCode, which can be tested using FSE_isError().
+              maxSymbolValuePtr[0] and tableLogPtr[0] will also be updated with their respective values */
+FSE_PUBLIC_API size_t FSE_readNCount (short* normalizedCounter,
+                           unsigned* maxSymbolValuePtr, unsigned* tableLogPtr,
+                           const void* rBuffer, size_t rBuffSize);
+
+/*! FSE_readNCount_bmi2():
+ * Same as FSE_readNCount() but pass bmi2=1 when your CPU supports BMI2 and 0 otherwise.
+ */
+FSE_PUBLIC_API size_t FSE_readNCount_bmi2(short* normalizedCounter,
+                           unsigned* maxSymbolValuePtr, unsigned* tableLogPtr,
+                           const void* rBuffer, size_t rBuffSize, int bmi2);
+
+typedef unsigned FSE_DTable;   /* don't allocate that. It's just a way to be more restrictive than void* */
+
+/*!
+Tutorial :
+----------
+(Note : these functions only decompress FSE-compressed blocks.
+ If block is uncompressed, use memcpy() instead
+ If block is a single repeated byte, use memset() instead )
+
+The first step is to obtain the normalized frequencies of symbols.
+This can be performed by FSE_readNCount() if it was saved using FSE_writeNCount().
+'normalizedCounter' must be already allocated, and have at least 'maxSymbolValuePtr[0]+1' cells of signed short.
+In practice, that means it's necessary to know 'maxSymbolValue' beforehand,
+or size the table to handle worst case situations (typically 256).
+FSE_readNCount() will provide 'tableLog' and 'maxSymbolValue'.
+The result of FSE_readNCount() is the number of bytes read from 'rBuffer'.
+Note that 'rBufferSize' must be at least 4 bytes, even if useful information is less than that.
+If there is an error, the function will return an error code, which can be tested using FSE_isError().
+
+The next step is to build the decompression tables 'FSE_DTable' from 'normalizedCounter'.
+This is performed by the function FSE_buildDTable().
+The space required by 'FSE_DTable' must be already allocated using FSE_createDTable().
+If there is an error, the function will return an error code, which can be tested using FSE_isError().
+
+`FSE_DTable` can then be used to decompress `cSrc`, with FSE_decompress_usingDTable().
+`cSrcSize` must be strictly correct, otherwise decompression will fail.
+FSE_decompress_usingDTable() result will tell how many bytes were regenerated (<=`dstCapacity`).
+If there is an error, the function will return an error code, which can be tested using FSE_isError(). (ex: dst buffer too small)
+*/
+
+#endif  /* FSE_H */
+
+
+#if defined(FSE_STATIC_LINKING_ONLY) && !defined(FSE_H_FSE_STATIC_LINKING_ONLY)
+#define FSE_H_FSE_STATIC_LINKING_ONLY
+#include "bitstream.h"
+
+/* *****************************************
+*  Static allocation
+*******************************************/
+/* FSE buffer bounds */
+#define FSE_NCOUNTBOUND 512
+#define FSE_BLOCKBOUND(size) ((size) + ((size)>>7) + 4 /* fse states */ + sizeof(size_t) /* bitContainer */)
+#define FSE_COMPRESSBOUND(size) (FSE_NCOUNTBOUND + FSE_BLOCKBOUND(size))   /* Macro version, useful for static allocation */
+
+/* It is possible to statically allocate FSE CTable/DTable as a table of FSE_CTable/FSE_DTable using below macros */
+#define FSE_CTABLE_SIZE_U32(maxTableLog, maxSymbolValue)   (1 + (1<<((maxTableLog)-1)) + (((maxSymbolValue)+1)*2))
+#define FSE_DTABLE_SIZE_U32(maxTableLog)                   (1 + (1<<(maxTableLog)))
+
+/* or use the size to malloc() space directly. Pay attention to alignment restrictions though */
+#define FSE_CTABLE_SIZE(maxTableLog, maxSymbolValue)   (FSE_CTABLE_SIZE_U32(maxTableLog, maxSymbolValue) * sizeof(FSE_CTable))
+#define FSE_DTABLE_SIZE(maxTableLog)                   (FSE_DTABLE_SIZE_U32(maxTableLog) * sizeof(FSE_DTable))
+
+
+/* *****************************************
+ *  FSE advanced API
+ ***************************************** */
+
+unsigned FSE_optimalTableLog_internal(unsigned maxTableLog, size_t srcSize, unsigned maxSymbolValue, unsigned minus);
+/**< same as FSE_optimalTableLog(), which used `minus==2` */
+
+size_t FSE_buildCTable_rle (FSE_CTable* ct, unsigned char symbolValue);
+/**< build a fake FSE_CTable, designed to compress always the same symbolValue */
+
+/* FSE_buildCTable_wksp() :
+ * Same as FSE_buildCTable(), but using an externally allocated scratch buffer (`workSpace`).
+ * `wkspSize` must be >= `FSE_BUILD_CTABLE_WORKSPACE_SIZE_U32(maxSymbolValue, tableLog)` of `unsigned`.
+ * See FSE_buildCTable_wksp() for breakdown of workspace usage.
+ */
+#define FSE_BUILD_CTABLE_WORKSPACE_SIZE_U32(maxSymbolValue, tableLog) (((maxSymbolValue + 2) + (1ull << (tableLog)))/2 + sizeof(U64)/sizeof(U32) /* additional 8 bytes for potential table overwrite */)
+#define FSE_BUILD_CTABLE_WORKSPACE_SIZE(maxSymbolValue, tableLog) (sizeof(unsigned) * FSE_BUILD_CTABLE_WORKSPACE_SIZE_U32(maxSymbolValue, tableLog))
+size_t FSE_buildCTable_wksp(FSE_CTable* ct, const short* normalizedCounter, unsigned maxSymbolValue, unsigned tableLog, void* workSpace, size_t wkspSize);
+
+#define FSE_BUILD_DTABLE_WKSP_SIZE(maxTableLog, maxSymbolValue) (sizeof(short) * (maxSymbolValue + 1) + (1ULL << maxTableLog) + 8)
+#define FSE_BUILD_DTABLE_WKSP_SIZE_U32(maxTableLog, maxSymbolValue) ((FSE_BUILD_DTABLE_WKSP_SIZE(maxTableLog, maxSymbolValue) + sizeof(unsigned) - 1) / sizeof(unsigned))
+FSE_PUBLIC_API size_t FSE_buildDTable_wksp(FSE_DTable* dt, const short* normalizedCounter, unsigned maxSymbolValue, unsigned tableLog, void* workSpace, size_t wkspSize);
+/**< Same as FSE_buildDTable(), using an externally allocated `workspace` produced with `FSE_BUILD_DTABLE_WKSP_SIZE_U32(maxSymbolValue)` */
+
+#define FSE_DECOMPRESS_WKSP_SIZE_U32(maxTableLog, maxSymbolValue) (FSE_DTABLE_SIZE_U32(maxTableLog) + 1 + FSE_BUILD_DTABLE_WKSP_SIZE_U32(maxTableLog, maxSymbolValue) + (FSE_MAX_SYMBOL_VALUE + 1) / 2 + 1)
+#define FSE_DECOMPRESS_WKSP_SIZE(maxTableLog, maxSymbolValue) (FSE_DECOMPRESS_WKSP_SIZE_U32(maxTableLog, maxSymbolValue) * sizeof(unsigned))
+size_t FSE_decompress_wksp_bmi2(void* dst, size_t dstCapacity, const void* cSrc, size_t cSrcSize, unsigned maxLog, void* workSpace, size_t wkspSize, int bmi2);
+/**< same as FSE_decompress(), using an externally allocated `workSpace` produced with `FSE_DECOMPRESS_WKSP_SIZE_U32(maxLog, maxSymbolValue)`.
+ * Set bmi2 to 1 if your CPU supports BMI2 or 0 if it doesn't */
+
+typedef enum {
+   FSE_repeat_none,  /**< Cannot use the previous table */
+   FSE_repeat_check, /**< Can use the previous table but it must be checked */
+   FSE_repeat_valid  /**< Can use the previous table and it is assumed to be valid */
+ } FSE_repeat;
+
+/* *****************************************
+*  FSE symbol compression API
+*******************************************/
+/*!
+   This API consists of small unitary functions, which highly benefit from being inlined.
+   Hence their body are included in next section.
+*/
+typedef struct {
+    ptrdiff_t   value;
+    const void* stateTable;
+    const void* symbolTT;
+    unsigned    stateLog;
+} FSE_CState_t;
+
+static void FSE_initCState(FSE_CState_t* CStatePtr, const FSE_CTable* ct);
+
+static void FSE_encodeSymbol(BIT_CStream_t* bitC, FSE_CState_t* CStatePtr, unsigned symbol);
+
+static void FSE_flushCState(BIT_CStream_t* bitC, const FSE_CState_t* CStatePtr);
+
+/**<
+These functions are inner components of FSE_compress_usingCTable().
+They allow the creation of custom streams, mixing multiple tables and bit sources.
+
+A key property to keep in mind is that encoding and decoding are done **in reverse direction**.
+So the first symbol you will encode is the last you will decode, like a LIFO stack.
+
+You will need a few variables to track your CStream. They are :
+
+FSE_CTable    ct;         // Provided by FSE_buildCTable()
+BIT_CStream_t bitStream;  // bitStream tracking structure
+FSE_CState_t  state;      // State tracking structure (can have several)
+
+
+The first thing to do is to init bitStream and state.
+    size_t errorCode = BIT_initCStream(&bitStream, dstBuffer, maxDstSize);
+    FSE_initCState(&state, ct);
+
+Note that BIT_initCStream() can produce an error code, so its result should be tested, using FSE_isError();
+You can then encode your input data, byte after byte.
+FSE_encodeSymbol() outputs a maximum of 'tableLog' bits at a time.
+Remember decoding will be done in reverse direction.
+    FSE_encodeByte(&bitStream, &state, symbol);
+
+At any time, you can also add any bit sequence.
+Note : maximum allowed nbBits is 25, for compatibility with 32-bits decoders
+    BIT_addBits(&bitStream, bitField, nbBits);
+
+The above methods don't commit data to memory, they just store it into local register, for speed.
+Local register size is 64-bits on 64-bits systems, 32-bits on 32-bits systems (size_t).
+Writing data to memory is a manual operation, performed by the flushBits function.
+    BIT_flushBits(&bitStream);
+
+Your last FSE encoding operation shall be to flush your last state value(s).
+    FSE_flushState(&bitStream, &state);
+
+Finally, you must close the bitStream.
+The function returns the size of CStream in bytes.
+If data couldn't fit into dstBuffer, it will return a 0 ( == not compressible)
+If there is an error, it returns an errorCode (which can be tested using FSE_isError()).
+    size_t size = BIT_closeCStream(&bitStream);
+*/
+
+
+/* *****************************************
+*  FSE symbol decompression API
+*******************************************/
+typedef struct {
+    size_t      state;
+    const void* table;   /* precise table may vary, depending on U16 */
+} FSE_DState_t;
+
+
+static void     FSE_initDState(FSE_DState_t* DStatePtr, BIT_DStream_t* bitD, const FSE_DTable* dt);
+
+static unsigned char FSE_decodeSymbol(FSE_DState_t* DStatePtr, BIT_DStream_t* bitD);
+
+static unsigned FSE_endOfDState(const FSE_DState_t* DStatePtr);
+
+/**<
+Let's now decompose FSE_decompress_usingDTable() into its unitary components.
+You will decode FSE-encoded symbols from the bitStream,
+and also any other bitFields you put in, **in reverse order**.
+
+You will need a few variables to track your bitStream. They are :
+
+BIT_DStream_t DStream;    // Stream context
+FSE_DState_t  DState;     // State context. Multiple ones are possible
+FSE_DTable*   DTablePtr;  // Decoding table, provided by FSE_buildDTable()
+
+The first thing to do is to init the bitStream.
+    errorCode = BIT_initDStream(&DStream, srcBuffer, srcSize);
+
+You should then retrieve your initial state(s)
+(in reverse flushing order if you have several ones) :
+    errorCode = FSE_initDState(&DState, &DStream, DTablePtr);
+
+You can then decode your data, symbol after symbol.
+For information the maximum number of bits read by FSE_decodeSymbol() is 'tableLog'.
+Keep in mind that symbols are decoded in reverse order, like a LIFO stack (last in, first out).
+    unsigned char symbol = FSE_decodeSymbol(&DState, &DStream);
+
+You can retrieve any bitfield you eventually stored into the bitStream (in reverse order)
+Note : maximum allowed nbBits is 25, for 32-bits compatibility
+    size_t bitField = BIT_readBits(&DStream, nbBits);
+
+All above operations only read from local register (which size depends on size_t).
+Refueling the register from memory is manually performed by the reload method.
+    endSignal = FSE_reloadDStream(&DStream);
+
+BIT_reloadDStream() result tells if there is still some more data to read from DStream.
+BIT_DStream_unfinished : there is still some data left into the DStream.
+BIT_DStream_endOfBuffer : Dstream reached end of buffer. Its container may no longer be completely filled.
+BIT_DStream_completed : Dstream reached its exact end, corresponding in general to decompression completed.
+BIT_DStream_tooFar : Dstream went too far. Decompression result is corrupted.
+
+When reaching end of buffer (BIT_DStream_endOfBuffer), progress slowly, notably if you decode multiple symbols per loop,
+to properly detect the exact end of stream.
+After each decoded symbol, check if DStream is fully consumed using this simple test :
+    BIT_reloadDStream(&DStream) >= BIT_DStream_completed
+
+When it's done, verify decompression is fully completed, by checking both DStream and the relevant states.
+Checking if DStream has reached its end is performed by :
+    BIT_endOfDStream(&DStream);
+Check also the states. There might be some symbols left there, if some high probability ones (>50%) are possible.
+    FSE_endOfDState(&DState);
+*/
+
+
+/* *****************************************
+*  FSE unsafe API
+*******************************************/
+static unsigned char FSE_decodeSymbolFast(FSE_DState_t* DStatePtr, BIT_DStream_t* bitD);
+/* faster, but works only if nbBits is always >= 1 (otherwise, result will be corrupted) */
+
+
+/* *****************************************
+*  Implementation of inlined functions
+*******************************************/
+typedef struct {
+    int deltaFindState;
+    U32 deltaNbBits;
+} FSE_symbolCompressionTransform; /* total 8 bytes */
+
+MEM_STATIC void FSE_initCState(FSE_CState_t* statePtr, const FSE_CTable* ct)
+{
+    const void* ptr = ct;
+    const U16* u16ptr = (const U16*) ptr;
+    const U32 tableLog = MEM_read16(ptr);
+    statePtr->value = (ptrdiff_t)1<<tableLog;
+    statePtr->stateTable = u16ptr+2;
+    statePtr->symbolTT = ct + 1 + (tableLog ? (1<<(tableLog-1)) : 1);
+    statePtr->stateLog = tableLog;
+}
+
+
+/*! FSE_initCState2() :
+*   Same as FSE_initCState(), but the first symbol to include (which will be the last to be read)
+*   uses the smallest state value possible, saving the cost of this symbol */
+MEM_STATIC void FSE_initCState2(FSE_CState_t* statePtr, const FSE_CTable* ct, U32 symbol)
+{
+    FSE_initCState(statePtr, ct);
+    {   const FSE_symbolCompressionTransform symbolTT = ((const FSE_symbolCompressionTransform*)(statePtr->symbolTT))[symbol];
+        const U16* stateTable = (const U16*)(statePtr->stateTable);
+        U32 nbBitsOut  = (U32)((symbolTT.deltaNbBits + (1<<15)) >> 16);
+        statePtr->value = (nbBitsOut << 16) - symbolTT.deltaNbBits;
+        statePtr->value = stateTable[(statePtr->value >> nbBitsOut) + symbolTT.deltaFindState];
+    }
+}
+
+MEM_STATIC void FSE_encodeSymbol(BIT_CStream_t* bitC, FSE_CState_t* statePtr, unsigned symbol)
+{
+    FSE_symbolCompressionTransform const symbolTT = ((const FSE_symbolCompressionTransform*)(statePtr->symbolTT))[symbol];
+    const U16* const stateTable = (const U16*)(statePtr->stateTable);
+    U32 const nbBitsOut  = (U32)((statePtr->value + symbolTT.deltaNbBits) >> 16);
+    BIT_addBits(bitC, (BitContainerType)statePtr->value, nbBitsOut);
+    statePtr->value = stateTable[ (statePtr->value >> nbBitsOut) + symbolTT.deltaFindState];
+}
+
+MEM_STATIC void FSE_flushCState(BIT_CStream_t* bitC, const FSE_CState_t* statePtr)
+{
+    BIT_addBits(bitC, (BitContainerType)statePtr->value, statePtr->stateLog);
+    BIT_flushBits(bitC);
+}
+
+
+/* FSE_getMaxNbBits() :
+ * Approximate maximum cost of a symbol, in bits.
+ * Fractional get rounded up (i.e. a symbol with a normalized frequency of 3 gives the same result as a frequency of 2)
+ * note 1 : assume symbolValue is valid (<= maxSymbolValue)
+ * note 2 : if freq[symbolValue]==0, @return a fake cost of tableLog+1 bits */
+MEM_STATIC U32 FSE_getMaxNbBits(const void* symbolTTPtr, U32 symbolValue)
+{
+    const FSE_symbolCompressionTransform* symbolTT = (const FSE_symbolCompressionTransform*) symbolTTPtr;
+    return (symbolTT[symbolValue].deltaNbBits + ((1<<16)-1)) >> 16;
+}
+
+/* FSE_bitCost() :
+ * Approximate symbol cost, as fractional value, using fixed-point format (accuracyLog fractional bits)
+ * note 1 : assume symbolValue is valid (<= maxSymbolValue)
+ * note 2 : if freq[symbolValue]==0, @return a fake cost of tableLog+1 bits */
+MEM_STATIC U32 FSE_bitCost(const void* symbolTTPtr, U32 tableLog, U32 symbolValue, U32 accuracyLog)
+{
+    const FSE_symbolCompressionTransform* symbolTT = (const FSE_symbolCompressionTransform*) symbolTTPtr;
+    U32 const minNbBits = symbolTT[symbolValue].deltaNbBits >> 16;
+    U32 const threshold = (minNbBits+1) << 16;
+    assert(tableLog < 16);
+    assert(accuracyLog < 31-tableLog);  /* ensure enough room for renormalization double shift */
+    {   U32 const tableSize = 1 << tableLog;
+        U32 const deltaFromThreshold = threshold - (symbolTT[symbolValue].deltaNbBits + tableSize);
+        U32 const normalizedDeltaFromThreshold = (deltaFromThreshold << accuracyLog) >> tableLog;   /* linear interpolation (very approximate) */
+        U32 const bitMultiplier = 1 << accuracyLog;
+        assert(symbolTT[symbolValue].deltaNbBits + tableSize <= threshold);
+        assert(normalizedDeltaFromThreshold <= bitMultiplier);
+        return (minNbBits+1)*bitMultiplier - normalizedDeltaFromThreshold;
+    }
+}
+
+
+/* ======    Decompression    ====== */
+
+typedef struct {
+    U16 tableLog;
+    U16 fastMode;
+} FSE_DTableHeader;   /* sizeof U32 */
+
+typedef struct
+{
+    unsigned short newState;
+    unsigned char  symbol;
+    unsigned char  nbBits;
+} FSE_decode_t;   /* size == U32 */
+
+MEM_STATIC void FSE_initDState(FSE_DState_t* DStatePtr, BIT_DStream_t* bitD, const FSE_DTable* dt)
+{
+    const void* ptr = dt;
+    const FSE_DTableHeader* const DTableH = (const FSE_DTableHeader*)ptr;
+    DStatePtr->state = BIT_readBits(bitD, DTableH->tableLog);
+    BIT_reloadDStream(bitD);
+    DStatePtr->table = dt + 1;
+}
+
+MEM_STATIC BYTE FSE_peekSymbol(const FSE_DState_t* DStatePtr)
+{
+    FSE_decode_t const DInfo = ((const FSE_decode_t*)(DStatePtr->table))[DStatePtr->state];
+    return DInfo.symbol;
+}
+
+MEM_STATIC void FSE_updateState(FSE_DState_t* DStatePtr, BIT_DStream_t* bitD)
+{
+    FSE_decode_t const DInfo = ((const FSE_decode_t*)(DStatePtr->table))[DStatePtr->state];
+    U32 const nbBits = DInfo.nbBits;
+    size_t const lowBits = BIT_readBits(bitD, nbBits);
+    DStatePtr->state = DInfo.newState + lowBits;
+}
+
+MEM_STATIC BYTE FSE_decodeSymbol(FSE_DState_t* DStatePtr, BIT_DStream_t* bitD)
+{
+    FSE_decode_t const DInfo = ((const FSE_decode_t*)(DStatePtr->table))[DStatePtr->state];
+    U32 const nbBits = DInfo.nbBits;
+    BYTE const symbol = DInfo.symbol;
+    size_t const lowBits = BIT_readBits(bitD, nbBits);
+
+    DStatePtr->state = DInfo.newState + lowBits;
+    return symbol;
+}
+
+/*! FSE_decodeSymbolFast() :
+    unsafe, only works if no symbol has a probability > 50% */
+MEM_STATIC BYTE FSE_decodeSymbolFast(FSE_DState_t* DStatePtr, BIT_DStream_t* bitD)
+{
+    FSE_decode_t const DInfo = ((const FSE_decode_t*)(DStatePtr->table))[DStatePtr->state];
+    U32 const nbBits = DInfo.nbBits;
+    BYTE const symbol = DInfo.symbol;
+    size_t const lowBits = BIT_readBitsFast(bitD, nbBits);
+
+    DStatePtr->state = DInfo.newState + lowBits;
+    return symbol;
+}
+
+MEM_STATIC unsigned FSE_endOfDState(const FSE_DState_t* DStatePtr)
+{
+    return DStatePtr->state == 0;
+}
+
+
+
+#ifndef FSE_COMMONDEFS_ONLY
+
+/* **************************************************************
+*  Tuning parameters
+****************************************************************/
+/*!MEMORY_USAGE :
+*  Memory usage formula : N->2^N Bytes (examples : 10 -> 1KB; 12 -> 4KB ; 16 -> 64KB; 20 -> 1MB; etc.)
+*  Increasing memory usage improves compression ratio
+*  Reduced memory usage can improve speed, due to cache effect
+*  Recommended max value is 14, for 16KB, which nicely fits into Intel x86 L1 cache */
+#ifndef FSE_MAX_MEMORY_USAGE
+#  define FSE_MAX_MEMORY_USAGE 14
+#endif
+#ifndef FSE_DEFAULT_MEMORY_USAGE
+#  define FSE_DEFAULT_MEMORY_USAGE 13
+#endif
+#if (FSE_DEFAULT_MEMORY_USAGE > FSE_MAX_MEMORY_USAGE)
+#  error "FSE_DEFAULT_MEMORY_USAGE must be <= FSE_MAX_MEMORY_USAGE"
+#endif
+
+/*!FSE_MAX_SYMBOL_VALUE :
+*  Maximum symbol value authorized.
+*  Required for proper stack allocation */
+#ifndef FSE_MAX_SYMBOL_VALUE
+#  define FSE_MAX_SYMBOL_VALUE 255
+#endif
+
+/* **************************************************************
+*  template functions type & suffix
+****************************************************************/
+#define FSE_FUNCTION_TYPE BYTE
+#define FSE_FUNCTION_EXTENSION
+#define FSE_DECODE_TYPE FSE_decode_t
+
+
+#endif   /* !FSE_COMMONDEFS_ONLY */
+
+
+/* ***************************************************************
+*  Constants
+*****************************************************************/
+#define FSE_MAX_TABLELOG  (FSE_MAX_MEMORY_USAGE-2)
+#define FSE_MAX_TABLESIZE (1U<<FSE_MAX_TABLELOG)
+#define FSE_MAXTABLESIZE_MASK (FSE_MAX_TABLESIZE-1)
+#define FSE_DEFAULT_TABLELOG (FSE_DEFAULT_MEMORY_USAGE-2)
+#define FSE_MIN_TABLELOG 5
+
+#define FSE_TABLELOG_ABSOLUTE_MAX 15
+#if FSE_MAX_TABLELOG > FSE_TABLELOG_ABSOLUTE_MAX
+#  error "FSE_MAX_TABLELOG > FSE_TABLELOG_ABSOLUTE_MAX is not supported"
+#endif
+
+#define FSE_TABLESTEP(tableSize) (((tableSize)>>1) + ((tableSize)>>3) + 3)
+
+#endif /* FSE_STATIC_LINKING_ONLY */
diff --git a/src/commonlib/bsd/zstd/common/fse_decompress.c b/src/commonlib/bsd/zstd/common/fse_decompress.c
new file mode 100644
index 0000000000..6fbac2992a
--- /dev/null
+++ b/src/commonlib/bsd/zstd/common/fse_decompress.c
@@ -0,0 +1,317 @@
+/* SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0-only */
+
+/* ******************************************************************
+ * FSE : Finite State Entropy decoder
+ * Copyright (c) Meta Platforms, Inc. and affiliates.
+ *
+ *  You can contact the author at :
+ *  - FSE source repository : https://github.com/Cyan4973/FiniteStateEntropy
+ *  - Public forum : https://groups.google.com/forum/#!forum/lz4c
+ *
+ * This source code is licensed under both the BSD-style license (found in the
+ * LICENSE file in the root directory of this source tree) and the GPLv2 (found
+ * in the COPYING file in the root directory of this source tree).
+ * You may select, at your option, one of the above-listed licenses.
+****************************************************************** */
+
+
+/* **************************************************************
+*  Includes
+****************************************************************/
+#include "debug.h"      /* assert */
+#include "bitstream.h"
+#include "zstd_compiler.h"
+#define FSE_STATIC_LINKING_ONLY
+#include "fse.h"
+#include "error_private.h"
+#include "zstd_deps.h"  /* ZSTD_memcpy */
+#include "zstd_bits.h"       /* ZSTD_highbit32 */
+
+
+/* **************************************************************
+*  Error Management
+****************************************************************/
+#define FSE_isError ERR_isError
+#define FSE_STATIC_ASSERT(c) DEBUG_STATIC_ASSERT(c)   /* use only *after* variable declarations */
+
+
+/* **************************************************************
+*  Templates
+****************************************************************/
+/*
+  designed to be included
+  for type-specific functions (template emulation in C)
+  Objective is to write these functions only once, for improved maintenance
+*/
+
+/* safety checks */
+#ifndef FSE_FUNCTION_EXTENSION
+#  error "FSE_FUNCTION_EXTENSION must be defined"
+#endif
+#ifndef FSE_FUNCTION_TYPE
+#  error "FSE_FUNCTION_TYPE must be defined"
+#endif
+
+/* Function names */
+#define FSE_CAT(X,Y) X##Y
+#define FSE_FUNCTION_NAME(X,Y) FSE_CAT(X,Y)
+#define FSE_TYPE_NAME(X,Y) FSE_CAT(X,Y)
+
+static size_t FSE_buildDTable_internal(FSE_DTable* dt, const short* normalizedCounter, unsigned maxSymbolValue, unsigned tableLog, void* workSpace, size_t wkspSize)
+{
+    void* const tdPtr = dt+1;   /* because *dt is unsigned, 32-bits aligned on 32-bits */
+    FSE_DECODE_TYPE* const tableDecode = (FSE_DECODE_TYPE*) (tdPtr);
+    U16* symbolNext = (U16*)workSpace;
+    BYTE* spread = (BYTE*)(symbolNext + maxSymbolValue + 1);
+
+    U32 const maxSV1 = maxSymbolValue + 1;
+    U32 const tableSize = 1 << tableLog;
+    U32 highThreshold = tableSize-1;
+
+    /* Sanity Checks */
+    if (FSE_BUILD_DTABLE_WKSP_SIZE(tableLog, maxSymbolValue) > wkspSize) return ERROR(maxSymbolValue_tooLarge);
+    if (maxSymbolValue > FSE_MAX_SYMBOL_VALUE) return ERROR(maxSymbolValue_tooLarge);
+    if (tableLog > FSE_MAX_TABLELOG) return ERROR(tableLog_tooLarge);
+
+    /* Init, lay down lowprob symbols */
+    {   FSE_DTableHeader DTableH;
+        DTableH.tableLog = (U16)tableLog;
+        DTableH.fastMode = 1;
+        {   S16 const largeLimit= (S16)(1 << (tableLog-1));
+            U32 s;
+            for (s=0; s<maxSV1; s++) {
+                if (normalizedCounter[s]==-1) {
+                    tableDecode[highThreshold--].symbol = (FSE_FUNCTION_TYPE)s;
+                    symbolNext[s] = 1;
+                } else {
+                    if (normalizedCounter[s] >= largeLimit) DTableH.fastMode=0;
+                    symbolNext[s] = (U16)normalizedCounter[s];
+        }   }   }
+        ZSTD_memcpy(dt, &DTableH, sizeof(DTableH));
+    }
+
+    /* Spread symbols */
+    if (highThreshold == tableSize - 1) {
+        size_t const tableMask = tableSize-1;
+        size_t const step = FSE_TABLESTEP(tableSize);
+        /* First lay down the symbols in order.
+         * We use a uint64_t to lay down 8 bytes at a time. This reduces branch
+         * misses since small blocks generally have small table logs, so nearly
+         * all symbols have counts <= 8. We ensure we have 8 bytes at the end of
+         * our buffer to handle the over-write.
+         */
+        {   U64 const add = 0x0101010101010101ull;
+            size_t pos = 0;
+            U64 sv = 0;
+            U32 s;
+            for (s=0; s<maxSV1; ++s, sv += add) {
+                int i;
+                int const n = normalizedCounter[s];
+                MEM_write64(spread + pos, sv);
+                for (i = 8; i < n; i += 8) {
+                    MEM_write64(spread + pos + i, sv);
+                }
+                pos += (size_t)n;
+        }   }
+        /* Now we spread those positions across the table.
+         * The benefit of doing it in two stages is that we avoid the
+         * variable size inner loop, which caused lots of branch misses.
+         * Now we can run through all the positions without any branch misses.
+         * We unroll the loop twice, since that is what empirically worked best.
+         */
+        {
+            size_t position = 0;
+            size_t s;
+            size_t const unroll = 2;
+            assert(tableSize % unroll == 0); /* FSE_MIN_TABLELOG is 5 */
+            for (s = 0; s < (size_t)tableSize; s += unroll) {
+                size_t u;
+                for (u = 0; u < unroll; ++u) {
+                    size_t const uPosition = (position + (u * step)) & tableMask;
+                    tableDecode[uPosition].symbol = spread[s + u];
+                }
+                position = (position + (unroll * step)) & tableMask;
+            }
+            assert(position == 0);
+        }
+    } else {
+        U32 const tableMask = tableSize-1;
+        U32 const step = FSE_TABLESTEP(tableSize);
+        U32 s, position = 0;
+        for (s=0; s<maxSV1; s++) {
+            int i;
+            for (i=0; i<normalizedCounter[s]; i++) {
+                tableDecode[position].symbol = (FSE_FUNCTION_TYPE)s;
+                position = (position + step) & tableMask;
+                while (position > highThreshold) position = (position + step) & tableMask;   /* lowprob area */
+        }   }
+        if (position!=0) return ERROR(GENERIC);   /* position must reach all cells once, otherwise normalizedCounter is incorrect */
+    }
+
+    /* Build Decoding table */
+    {   U32 u;
+        for (u=0; u<tableSize; u++) {
+            FSE_FUNCTION_TYPE const symbol = (FSE_FUNCTION_TYPE)(tableDecode[u].symbol);
+            U32 const nextState = symbolNext[symbol]++;
+            tableDecode[u].nbBits = (BYTE) (tableLog - ZSTD_highbit32(nextState) );
+            tableDecode[u].newState = (U16) ( (nextState << tableDecode[u].nbBits) - tableSize);
+    }   }
+
+    return 0;
+}
+
+size_t FSE_buildDTable_wksp(FSE_DTable* dt, const short* normalizedCounter, unsigned maxSymbolValue, unsigned tableLog, void* workSpace, size_t wkspSize)
+{
+    return FSE_buildDTable_internal(dt, normalizedCounter, maxSymbolValue, tableLog, workSpace, wkspSize);
+}
+
+
+#ifndef FSE_COMMONDEFS_ONLY
+
+/*-*******************************************************
+*  Decompression (Byte symbols)
+*********************************************************/
+
+FORCE_INLINE_TEMPLATE size_t FSE_decompress_usingDTable_generic(
+          void* dst, size_t maxDstSize,
+    const void* cSrc, size_t cSrcSize,
+    const FSE_DTable* dt, const unsigned fast)
+{
+    BYTE* const ostart = (BYTE*) dst;
+    BYTE* op = ostart;
+    BYTE* const omax = op + maxDstSize;
+    BYTE* const olimit = omax-3;
+
+    BIT_DStream_t bitD;
+    FSE_DState_t state1;
+    FSE_DState_t state2;
+
+    /* Init */
+    CHECK_F(BIT_initDStream(&bitD, cSrc, cSrcSize));
+
+    FSE_initDState(&state1, &bitD, dt);
+    FSE_initDState(&state2, &bitD, dt);
+
+    RETURN_ERROR_IF(BIT_reloadDStream(&bitD)==BIT_DStream_overflow, corruption_detected, "");
+
+#define FSE_GETSYMBOL(statePtr) fast ? FSE_decodeSymbolFast(statePtr, &bitD) : FSE_decodeSymbol(statePtr, &bitD)
+
+    /* 4 symbols per loop */
+    for ( ; (BIT_reloadDStream(&bitD)==BIT_DStream_unfinished) & (op<olimit) ; op+=4) {
+        op[0] = FSE_GETSYMBOL(&state1);
+
+        if (FSE_MAX_TABLELOG*2+7 > sizeof(bitD.bitContainer)*8)    /* This test must be static */
+            BIT_reloadDStream(&bitD);
+
+        op[1] = FSE_GETSYMBOL(&state2);
+
+        if (FSE_MAX_TABLELOG*4+7 > sizeof(bitD.bitContainer)*8)    /* This test must be static */
+            { if (BIT_reloadDStream(&bitD) > BIT_DStream_unfinished) { op+=2; break; } }
+
+        op[2] = FSE_GETSYMBOL(&state1);
+
+        if (FSE_MAX_TABLELOG*2+7 > sizeof(bitD.bitContainer)*8)    /* This test must be static */
+            BIT_reloadDStream(&bitD);
+
+        op[3] = FSE_GETSYMBOL(&state2);
+    }
+
+    /* tail */
+    /* note : BIT_reloadDStream(&bitD) >= FSE_DStream_partiallyFilled; Ends at exactly BIT_DStream_completed */
+    while (1) {
+        if (op>(omax-2)) return ERROR(dstSize_tooSmall);
+        *op++ = FSE_GETSYMBOL(&state1);
+        if (BIT_reloadDStream(&bitD)==BIT_DStream_overflow) {
+            *op++ = FSE_GETSYMBOL(&state2);
+            break;
+        }
+
+        if (op>(omax-2)) return ERROR(dstSize_tooSmall);
+        *op++ = FSE_GETSYMBOL(&state2);
+        if (BIT_reloadDStream(&bitD)==BIT_DStream_overflow) {
+            *op++ = FSE_GETSYMBOL(&state1);
+            break;
+    }   }
+
+    assert(op >= ostart);
+    return (size_t)(op-ostart);
+}
+
+typedef struct {
+    short ncount[FSE_MAX_SYMBOL_VALUE + 1];
+} FSE_DecompressWksp;
+
+
+FORCE_INLINE_TEMPLATE size_t FSE_decompress_wksp_body(
+        void* dst, size_t dstCapacity,
+        const void* cSrc, size_t cSrcSize,
+        unsigned maxLog, void* workSpace, size_t wkspSize,
+        int bmi2)
+{
+    const BYTE* const istart = (const BYTE*)cSrc;
+    const BYTE* ip = istart;
+    unsigned tableLog;
+    unsigned maxSymbolValue = FSE_MAX_SYMBOL_VALUE;
+    FSE_DecompressWksp* const wksp = (FSE_DecompressWksp*)workSpace;
+    size_t const dtablePos = sizeof(FSE_DecompressWksp) / sizeof(FSE_DTable);
+    FSE_DTable* const dtable = (FSE_DTable*)workSpace + dtablePos;
+
+    FSE_STATIC_ASSERT((FSE_MAX_SYMBOL_VALUE + 1) % 2 == 0);
+    if (wkspSize < sizeof(*wksp)) return ERROR(GENERIC);
+
+    /* correct offset to dtable depends on this property */
+    FSE_STATIC_ASSERT(sizeof(FSE_DecompressWksp) % sizeof(FSE_DTable) == 0);
+
+    /* normal FSE decoding mode */
+    {   size_t const NCountLength =
+            FSE_readNCount_bmi2(wksp->ncount, &maxSymbolValue, &tableLog, istart, cSrcSize, bmi2);
+        if (FSE_isError(NCountLength)) return NCountLength;
+        if (tableLog > maxLog) return ERROR(tableLog_tooLarge);
+        assert(NCountLength <= cSrcSize);
+        ip += NCountLength;
+        cSrcSize -= NCountLength;
+    }
+
+    if (FSE_DECOMPRESS_WKSP_SIZE(tableLog, maxSymbolValue) > wkspSize) return ERROR(tableLog_tooLarge);
+    assert(sizeof(*wksp) + FSE_DTABLE_SIZE(tableLog) <= wkspSize);
+    workSpace = (BYTE*)workSpace + sizeof(*wksp) + FSE_DTABLE_SIZE(tableLog);
+    wkspSize -= sizeof(*wksp) + FSE_DTABLE_SIZE(tableLog);
+
+    CHECK_F( FSE_buildDTable_internal(dtable, wksp->ncount, maxSymbolValue, tableLog, workSpace, wkspSize) );
+
+    {
+        const void* ptr = dtable;
+        const FSE_DTableHeader* DTableH = (const FSE_DTableHeader*)ptr;
+        const U32 fastMode = DTableH->fastMode;
+
+        /* select fast mode (static) */
+        if (fastMode) return FSE_decompress_usingDTable_generic(dst, dstCapacity, ip, cSrcSize, dtable, 1);
+        return FSE_decompress_usingDTable_generic(dst, dstCapacity, ip, cSrcSize, dtable, 0);
+    }
+}
+
+/* Avoids the FORCE_INLINE of the _body() function. */
+static size_t FSE_decompress_wksp_body_default(void* dst, size_t dstCapacity, const void* cSrc, size_t cSrcSize, unsigned maxLog, void* workSpace, size_t wkspSize)
+{
+    return FSE_decompress_wksp_body(dst, dstCapacity, cSrc, cSrcSize, maxLog, workSpace, wkspSize, 0);
+}
+
+#if DYNAMIC_BMI2
+BMI2_TARGET_ATTRIBUTE static size_t FSE_decompress_wksp_body_bmi2(void* dst, size_t dstCapacity, const void* cSrc, size_t cSrcSize, unsigned maxLog, void* workSpace, size_t wkspSize)
+{
+    return FSE_decompress_wksp_body(dst, dstCapacity, cSrc, cSrcSize, maxLog, workSpace, wkspSize, 1);
+}
+#endif
+
+size_t FSE_decompress_wksp_bmi2(void* dst, size_t dstCapacity, const void* cSrc, size_t cSrcSize, unsigned maxLog, void* workSpace, size_t wkspSize, int bmi2)
+{
+#if DYNAMIC_BMI2
+    if (bmi2) {
+        return FSE_decompress_wksp_body_bmi2(dst, dstCapacity, cSrc, cSrcSize, maxLog, workSpace, wkspSize);
+    }
+#endif
+    (void)bmi2;
+    return FSE_decompress_wksp_body_default(dst, dstCapacity, cSrc, cSrcSize, maxLog, workSpace, wkspSize);
+}
+
+#endif   /* FSE_COMMONDEFS_ONLY */
diff --git a/src/commonlib/bsd/zstd/common/huf.h b/src/commonlib/bsd/zstd/common/huf.h
new file mode 100644
index 0000000000..c7c0f3fd43
--- /dev/null
+++ b/src/commonlib/bsd/zstd/common/huf.h
@@ -0,0 +1,279 @@
+/* SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0-only */
+
+/* ******************************************************************
+ * huff0 huffman codec,
+ * part of Finite State Entropy library
+ * Copyright (c) Meta Platforms, Inc. and affiliates.
+ *
+ * You can contact the author at :
+ * - Source repository : https://github.com/Cyan4973/FiniteStateEntropy
+ *
+ * This source code is licensed under both the BSD-style license (found in the
+ * LICENSE file in the root directory of this source tree) and the GPLv2 (found
+ * in the COPYING file in the root directory of this source tree).
+ * You may select, at your option, one of the above-listed licenses.
+****************************************************************** */
+
+#ifndef HUF_H_298734234
+#define HUF_H_298734234
+
+/* *** Dependencies *** */
+#include "zstd_deps.h"    /* size_t */
+#include "mem.h"          /* U32 */
+#define FSE_STATIC_LINKING_ONLY
+#include "fse.h"
+
+/* ***   Tool functions *** */
+#define HUF_BLOCKSIZE_MAX (128 * 1024)   /**< maximum input size for a single block compressed with HUF_compress */
+size_t HUF_compressBound(size_t size);   /**< maximum compressed size (worst case) */
+
+/* Error Management */
+unsigned    HUF_isError(size_t code);       /**< tells if a return value is an error code */
+const char* HUF_getErrorName(size_t code);  /**< provides error code string (useful for debugging) */
+
+
+#define HUF_WORKSPACE_SIZE ((8 << 10) + 512 /* sorting scratch space */)
+#define HUF_WORKSPACE_SIZE_U64 (HUF_WORKSPACE_SIZE / sizeof(U64))
+
+/* *** Constants *** */
+#define HUF_TABLELOG_MAX      12      /* max runtime value of tableLog (due to static allocation); can be modified up to HUF_TABLELOG_ABSOLUTEMAX */
+#define HUF_TABLELOG_DEFAULT  11      /* default tableLog value when none specified */
+#define HUF_SYMBOLVALUE_MAX  255
+
+#define HUF_TABLELOG_ABSOLUTEMAX  12  /* absolute limit of HUF_MAX_TABLELOG. Beyond that value, code does not work */
+#if (HUF_TABLELOG_MAX > HUF_TABLELOG_ABSOLUTEMAX)
+#  error "HUF_TABLELOG_MAX is too large !"
+#endif
+
+
+/* ****************************************
+*  Static allocation
+******************************************/
+/* HUF buffer bounds */
+#define HUF_CTABLEBOUND 129
+#define HUF_BLOCKBOUND(size) (size + (size>>8) + 8)   /* only true when incompressible is pre-filtered with fast heuristic */
+#define HUF_COMPRESSBOUND(size) (HUF_CTABLEBOUND + HUF_BLOCKBOUND(size))   /* Macro version, useful for static allocation */
+
+/* static allocation of HUF's Compression Table */
+/* this is a private definition, just exposed for allocation and strict aliasing purpose. never EVER access its members directly */
+typedef size_t HUF_CElt;   /* consider it an incomplete type */
+#define HUF_CTABLE_SIZE_ST(maxSymbolValue)   ((maxSymbolValue)+2)   /* Use tables of size_t, for proper alignment */
+#define HUF_CTABLE_SIZE(maxSymbolValue)       (HUF_CTABLE_SIZE_ST(maxSymbolValue) * sizeof(size_t))
+#define HUF_CREATE_STATIC_CTABLE(name, maxSymbolValue) \
+    HUF_CElt name[HUF_CTABLE_SIZE_ST(maxSymbolValue)] /* no final ; */
+
+/* static allocation of HUF's DTable */
+typedef U32 HUF_DTable;
+#define HUF_DTABLE_SIZE(maxTableLog)   (1 + (1<<(maxTableLog)))
+#define HUF_CREATE_STATIC_DTABLEX1(DTable, maxTableLog) \
+        HUF_DTable DTable[HUF_DTABLE_SIZE((maxTableLog)-1)] = { ((U32)((maxTableLog)-1) * 0x01000001) }
+#define HUF_CREATE_STATIC_DTABLEX2(DTable, maxTableLog) \
+        HUF_DTable DTable[HUF_DTABLE_SIZE(maxTableLog)] = { ((U32)(maxTableLog) * 0x01000001) }
+
+
+/* ****************************************
+*  Advanced decompression functions
+******************************************/
+
+/**
+ * Huffman flags bitset.
+ * For all flags, 0 is the default value.
+ */
+typedef enum {
+    /**
+     * If compiled with DYNAMIC_BMI2: Set flag only if the CPU supports BMI2 at runtime.
+     * Otherwise: Ignored.
+     */
+    HUF_flags_bmi2 = (1 << 0),
+    /**
+     * If set: Test possible table depths to find the one that produces the smallest header + encoded size.
+     * If unset: Use heuristic to find the table depth.
+     */
+    HUF_flags_optimalDepth = (1 << 1),
+    /**
+     * If set: If the previous table can encode the input, always reuse the previous table.
+     * If unset: If the previous table can encode the input, reuse the previous table if it results in a smaller output.
+     */
+    HUF_flags_preferRepeat = (1 << 2),
+    /**
+     * If set: Sample the input and check if the sample is uncompressible, if it is then don't attempt to compress.
+     * If unset: Always histogram the entire input.
+     */
+    HUF_flags_suspectUncompressible = (1 << 3),
+    /**
+     * If set: Don't use assembly implementations
+     * If unset: Allow using assembly implementations
+     */
+    HUF_flags_disableAsm = (1 << 4),
+    /**
+     * If set: Don't use the fast decoding loop, always use the fallback decoding loop.
+     * If unset: Use the fast decoding loop when possible.
+     */
+    HUF_flags_disableFast = (1 << 5)
+} HUF_flags_e;
+
+
+/* ****************************************
+ *  HUF detailed API
+ * ****************************************/
+#define HUF_OPTIMAL_DEPTH_THRESHOLD ZSTD_btultra
+
+/*! HUF_compress() does the following:
+ *  1. count symbol occurrence from source[] into table count[] using FSE_count() (exposed within "fse.h")
+ *  2. (optional) refine tableLog using HUF_optimalTableLog()
+ *  3. build Huffman table from count using HUF_buildCTable()
+ *  4. save Huffman table to memory buffer using HUF_writeCTable()
+ *  5. encode the data stream using HUF_compress4X_usingCTable()
+ *
+ *  The following API allows targeting specific sub-functions for advanced tasks.
+ *  For example, it's possible to compress several blocks using the same 'CTable',
+ *  or to save and regenerate 'CTable' using external methods.
+ */
+unsigned HUF_minTableLog(unsigned symbolCardinality);
+unsigned HUF_cardinality(const unsigned* count, unsigned maxSymbolValue);
+unsigned HUF_optimalTableLog(unsigned maxTableLog, size_t srcSize, unsigned maxSymbolValue, void* workSpace,
+ size_t wkspSize, HUF_CElt* table, const unsigned* count, int flags); /* table is used as scratch space for building and testing tables, not a return value */
+size_t HUF_writeCTable_wksp(void* dst, size_t maxDstSize, const HUF_CElt* CTable, unsigned maxSymbolValue, unsigned huffLog, void* workspace, size_t workspaceSize);
+size_t HUF_compress4X_usingCTable(void* dst, size_t dstSize, const void* src, size_t srcSize, const HUF_CElt* CTable, int flags);
+size_t HUF_estimateCompressedSize(const HUF_CElt* CTable, const unsigned* count, unsigned maxSymbolValue);
+int HUF_validateCTable(const HUF_CElt* CTable, const unsigned* count, unsigned maxSymbolValue);
+
+typedef enum {
+   HUF_repeat_none,  /**< Cannot use the previous table */
+   HUF_repeat_check, /**< Can use the previous table but it must be checked. Note : The previous table must have been constructed by HUF_compress{1, 4}X_repeat */
+   HUF_repeat_valid  /**< Can use the previous table and it is assumed to be valid */
+ } HUF_repeat;
+
+/** HUF_compress4X_repeat() :
+ *  Same as HUF_compress4X_wksp(), but considers using hufTable if *repeat != HUF_repeat_none.
+ *  If it uses hufTable it does not modify hufTable or repeat.
+ *  If it doesn't, it sets *repeat = HUF_repeat_none, and it sets hufTable to the table used.
+ *  If preferRepeat then the old table will always be used if valid.
+ *  If suspectUncompressible then some sampling checks will be run to potentially skip huffman coding */
+size_t HUF_compress4X_repeat(void* dst, size_t dstSize,
+                       const void* src, size_t srcSize,
+                       unsigned maxSymbolValue, unsigned tableLog,
+                       void* workSpace, size_t wkspSize,    /**< `workSpace` must be aligned on 4-bytes boundaries, `wkspSize` must be >= HUF_WORKSPACE_SIZE */
+                       HUF_CElt* hufTable, HUF_repeat* repeat, int flags);
+
+/** HUF_buildCTable_wksp() :
+ *  Same as HUF_buildCTable(), but using externally allocated scratch buffer.
+ * `workSpace` must be aligned on 4-bytes boundaries, and its size must be >= HUF_CTABLE_WORKSPACE_SIZE.
+ */
+#define HUF_CTABLE_WORKSPACE_SIZE_U32 ((4 * (HUF_SYMBOLVALUE_MAX + 1)) + 192)
+#define HUF_CTABLE_WORKSPACE_SIZE (HUF_CTABLE_WORKSPACE_SIZE_U32 * sizeof(unsigned))
+size_t HUF_buildCTable_wksp (HUF_CElt* tree,
+                       const unsigned* count, U32 maxSymbolValue, U32 maxNbBits,
+                             void* workSpace, size_t wkspSize);
+
+/*! HUF_readStats() :
+ *  Read compact Huffman tree, saved by HUF_writeCTable().
+ * `huffWeight` is destination buffer.
+ * @return : size read from `src` , or an error Code .
+ *  Note : Needed by HUF_readCTable() and HUF_readDTableXn() . */
+size_t HUF_readStats(BYTE* huffWeight, size_t hwSize,
+                     U32* rankStats, U32* nbSymbolsPtr, U32* tableLogPtr,
+                     const void* src, size_t srcSize);
+
+/*! HUF_readStats_wksp() :
+ * Same as HUF_readStats() but takes an external workspace which must be
+ * 4-byte aligned and its size must be >= HUF_READ_STATS_WORKSPACE_SIZE.
+ * If the CPU has BMI2 support, pass bmi2=1, otherwise pass bmi2=0.
+ */
+#define HUF_READ_STATS_WORKSPACE_SIZE_U32 FSE_DECOMPRESS_WKSP_SIZE_U32(6, HUF_TABLELOG_MAX-1)
+#define HUF_READ_STATS_WORKSPACE_SIZE (HUF_READ_STATS_WORKSPACE_SIZE_U32 * sizeof(unsigned))
+size_t HUF_readStats_wksp(BYTE* huffWeight, size_t hwSize,
+                          U32* rankStats, U32* nbSymbolsPtr, U32* tableLogPtr,
+                          const void* src, size_t srcSize,
+                          void* workspace, size_t wkspSize,
+                          int flags);
+
+/** HUF_readCTable() :
+ *  Loading a CTable saved with HUF_writeCTable() */
+size_t HUF_readCTable (HUF_CElt* CTable, unsigned* maxSymbolValuePtr, const void* src, size_t srcSize, unsigned *hasZeroWeights);
+
+/** HUF_getNbBitsFromCTable() :
+ *  Read nbBits from CTable symbolTable, for symbol `symbolValue` presumed <= HUF_SYMBOLVALUE_MAX
+ *  Note 1 : If symbolValue > HUF_readCTableHeader(symbolTable).maxSymbolValue, returns 0
+ *  Note 2 : is not inlined, as HUF_CElt definition is private
+ */
+U32 HUF_getNbBitsFromCTable(const HUF_CElt* symbolTable, U32 symbolValue);
+
+typedef struct {
+    BYTE tableLog;
+    BYTE maxSymbolValue;
+    BYTE unused[sizeof(size_t) - 2];
+} HUF_CTableHeader;
+
+/** HUF_readCTableHeader() :
+ *  @returns The header from the CTable specifying the tableLog and the maxSymbolValue.
+ */
+HUF_CTableHeader HUF_readCTableHeader(HUF_CElt const* ctable);
+
+/*
+ * HUF_decompress() does the following:
+ * 1. select the decompression algorithm (X1, X2) based on pre-computed heuristics
+ * 2. build Huffman table from save, using HUF_readDTableX?()
+ * 3. decode 1 or 4 segments in parallel using HUF_decompress?X?_usingDTable()
+ */
+
+/** HUF_selectDecoder() :
+ *  Tells which decoder is likely to decode faster,
+ *  based on a set of pre-computed metrics.
+ * @return : 0==HUF_decompress4X1, 1==HUF_decompress4X2 .
+ *  Assumption : 0 < dstSize <= 128 KB */
+U32 HUF_selectDecoder (size_t dstSize, size_t cSrcSize);
+
+/**
+ *  The minimum workspace size for the `workSpace` used in
+ *  HUF_readDTableX1_wksp() and HUF_readDTableX2_wksp().
+ *
+ *  The space used depends on HUF_TABLELOG_MAX, ranging from ~1500 bytes when
+ *  HUF_TABLE_LOG_MAX=12 to ~1850 bytes when HUF_TABLE_LOG_MAX=15.
+ *  Buffer overflow errors may potentially occur if code modifications result in
+ *  a required workspace size greater than that specified in the following
+ *  macro.
+ */
+#define HUF_DECOMPRESS_WORKSPACE_SIZE ((2 << 10) + (1 << 9))
+#define HUF_DECOMPRESS_WORKSPACE_SIZE_U32 (HUF_DECOMPRESS_WORKSPACE_SIZE / sizeof(U32))
+
+
+/* ====================== */
+/* single stream variants */
+/* ====================== */
+
+size_t HUF_compress1X_usingCTable(void* dst, size_t dstSize, const void* src, size_t srcSize, const HUF_CElt* CTable, int flags);
+/** HUF_compress1X_repeat() :
+ *  Same as HUF_compress1X_wksp(), but considers using hufTable if *repeat != HUF_repeat_none.
+ *  If it uses hufTable it does not modify hufTable or repeat.
+ *  If it doesn't, it sets *repeat = HUF_repeat_none, and it sets hufTable to the table used.
+ *  If preferRepeat then the old table will always be used if valid.
+ *  If suspectUncompressible then some sampling checks will be run to potentially skip huffman coding */
+size_t HUF_compress1X_repeat(void* dst, size_t dstSize,
+                       const void* src, size_t srcSize,
+                       unsigned maxSymbolValue, unsigned tableLog,
+                       void* workSpace, size_t wkspSize,   /**< `workSpace` must be aligned on 4-bytes boundaries, `wkspSize` must be >= HUF_WORKSPACE_SIZE */
+                       HUF_CElt* hufTable, HUF_repeat* repeat, int flags);
+
+size_t HUF_decompress1X_DCtx_wksp(HUF_DTable* dctx, void* dst, size_t dstSize, const void* cSrc, size_t cSrcSize, void* workSpace, size_t wkspSize, int flags);
+#ifndef HUF_FORCE_DECOMPRESS_X1
+size_t HUF_decompress1X2_DCtx_wksp(HUF_DTable* dctx, void* dst, size_t dstSize, const void* cSrc, size_t cSrcSize, void* workSpace, size_t wkspSize, int flags);   /**< double-symbols decoder */
+#endif
+
+/* BMI2 variants.
+ * If the CPU has BMI2 support, pass bmi2=1, otherwise pass bmi2=0.
+ */
+size_t HUF_decompress1X_usingDTable(void* dst, size_t maxDstSize, const void* cSrc, size_t cSrcSize, const HUF_DTable* DTable, int flags);
+#ifndef HUF_FORCE_DECOMPRESS_X2
+size_t HUF_decompress1X1_DCtx_wksp(HUF_DTable* dctx, void* dst, size_t dstSize, const void* cSrc, size_t cSrcSize, void* workSpace, size_t wkspSize, int flags);
+#endif
+size_t HUF_decompress4X_usingDTable(void* dst, size_t maxDstSize, const void* cSrc, size_t cSrcSize, const HUF_DTable* DTable, int flags);
+size_t HUF_decompress4X_hufOnly_wksp(HUF_DTable* dctx, void* dst, size_t dstSize, const void* cSrc, size_t cSrcSize, void* workSpace, size_t wkspSize, int flags);
+#ifndef HUF_FORCE_DECOMPRESS_X2
+size_t HUF_readDTableX1_wksp(HUF_DTable* DTable, const void* src, size_t srcSize, void* workSpace, size_t wkspSize, int flags);
+#endif
+#ifndef HUF_FORCE_DECOMPRESS_X1
+size_t HUF_readDTableX2_wksp(HUF_DTable* DTable, const void* src, size_t srcSize, void* workSpace, size_t wkspSize, int flags);
+#endif
+
+#endif   /* HUF_H_298734234 */
diff --git a/src/commonlib/bsd/zstd/common/mem.h b/src/commonlib/bsd/zstd/common/mem.h
new file mode 100644
index 0000000000..4b2a4aebef
--- /dev/null
+++ b/src/commonlib/bsd/zstd/common/mem.h
@@ -0,0 +1,424 @@
+/* SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0-only */
+
+/*
+ * Copyright (c) Meta Platforms, Inc. and affiliates.
+ * All rights reserved.
+ *
+ * This source code is licensed under both the BSD-style license (found in the
+ * LICENSE file in the root directory of this source tree) and the GPLv2 (found
+ * in the COPYING file in the root directory of this source tree).
+ * You may select, at your option, one of the above-listed licenses.
+ */
+
+#ifndef MEM_H_MODULE
+#define MEM_H_MODULE
+
+/*-****************************************
+*  Dependencies
+******************************************/
+#include <stddef.h>  /* size_t, ptrdiff_t */
+#include "zstd_compiler.h"  /* __has_builtin */
+#include "debug.h"  /* DEBUG_STATIC_ASSERT */
+#include "zstd_deps.h"  /* ZSTD_memcpy */
+
+
+/*-****************************************
+*  Compiler specifics
+******************************************/
+#if defined(_MSC_VER)   /* Visual Studio */
+#   include <stdlib.h>  /* _byteswap_ulong */
+#   include <intrin.h>  /* _byteswap_* */
+#elif defined(__ICCARM__)
+#   include <intrinsics.h>
+#endif
+
+/*-**************************************************************
+*  Basic Types
+*****************************************************************/
+#if  !defined (__VMS) && (defined (__cplusplus) || (defined (__STDC_VERSION__) && (__STDC_VERSION__ >= 199901L) /* C99 */) )
+#  if defined(_AIX)
+#    include <inttypes.h>
+#  else
+#    include <stdint.h> /* intptr_t */
+#  endif
+  typedef   uint8_t BYTE;
+  typedef   uint8_t U8;
+  typedef    int8_t S8;
+  typedef  uint16_t U16;
+  typedef   int16_t S16;
+  typedef  uint32_t U32;
+  typedef   int32_t S32;
+  typedef  uint64_t U64;
+  typedef   int64_t S64;
+#else
+# include <limits.h>
+#if CHAR_BIT != 8
+#  error "this implementation requires char to be exactly 8-bit type"
+#endif
+  typedef unsigned char      BYTE;
+  typedef unsigned char      U8;
+  typedef   signed char      S8;
+#if USHRT_MAX != 65535
+#  error "this implementation requires short to be exactly 16-bit type"
+#endif
+  typedef unsigned short      U16;
+  typedef   signed short      S16;
+#if UINT_MAX != 4294967295
+#  error "this implementation requires int to be exactly 32-bit type"
+#endif
+  typedef unsigned int        U32;
+  typedef   signed int        S32;
+/* note : there are no limits defined for long long type in C90.
+ * limits exist in C99, however, in such case, <stdint.h> is preferred */
+  typedef unsigned long long  U64;
+  typedef   signed long long  S64;
+#endif
+
+/*-**************************************************************
+*  Memory I/O API
+*****************************************************************/
+/*=== Static platform detection ===*/
+MEM_STATIC unsigned MEM_32bits(void);
+MEM_STATIC unsigned MEM_64bits(void);
+MEM_STATIC unsigned MEM_isLittleEndian(void);
+
+/*=== Native unaligned read/write ===*/
+MEM_STATIC U16 MEM_read16(const void* memPtr);
+MEM_STATIC U32 MEM_read32(const void* memPtr);
+MEM_STATIC U64 MEM_read64(const void* memPtr);
+MEM_STATIC size_t MEM_readST(const void* memPtr);
+
+MEM_STATIC void MEM_write16(void* memPtr, U16 value);
+MEM_STATIC void MEM_write32(void* memPtr, U32 value);
+MEM_STATIC void MEM_write64(void* memPtr, U64 value);
+
+/*=== Little endian unaligned read/write ===*/
+MEM_STATIC U16 MEM_readLE16(const void* memPtr);
+MEM_STATIC U32 MEM_readLE24(const void* memPtr);
+MEM_STATIC U32 MEM_readLE32(const void* memPtr);
+MEM_STATIC U64 MEM_readLE64(const void* memPtr);
+MEM_STATIC size_t MEM_readLEST(const void* memPtr);
+
+MEM_STATIC void MEM_writeLE16(void* memPtr, U16 val);
+MEM_STATIC void MEM_writeLE24(void* memPtr, U32 val);
+MEM_STATIC void MEM_writeLE32(void* memPtr, U32 val32);
+MEM_STATIC void MEM_writeLE64(void* memPtr, U64 val64);
+MEM_STATIC void MEM_writeLEST(void* memPtr, size_t val);
+
+/*=== Big endian unaligned read/write ===*/
+MEM_STATIC U32 MEM_readBE32(const void* memPtr);
+MEM_STATIC U64 MEM_readBE64(const void* memPtr);
+MEM_STATIC size_t MEM_readBEST(const void* memPtr);
+
+MEM_STATIC void MEM_writeBE32(void* memPtr, U32 val32);
+MEM_STATIC void MEM_writeBE64(void* memPtr, U64 val64);
+MEM_STATIC void MEM_writeBEST(void* memPtr, size_t val);
+
+/*=== Byteswap ===*/
+MEM_STATIC U32 MEM_swap32(U32 in);
+MEM_STATIC U64 MEM_swap64(U64 in);
+MEM_STATIC size_t MEM_swapST(size_t in);
+
+
+/*-**************************************************************
+*  Memory I/O Implementation
+*****************************************************************/
+/* MEM_FORCE_MEMORY_ACCESS : For accessing unaligned memory:
+ * Method 0 : always use `memcpy()`. Safe and portable.
+ * Method 1 : Use compiler extension to set unaligned access.
+ * Method 2 : direct access. This method is portable but violate C standard.
+ *            It can generate buggy code on targets depending on alignment.
+ * Default  : method 1 if supported, else method 0
+ */
+#ifndef MEM_FORCE_MEMORY_ACCESS   /* can be defined externally, on command line for example */
+#  ifdef __GNUC__
+#    define MEM_FORCE_MEMORY_ACCESS 1
+#  endif
+#endif
+
+MEM_STATIC unsigned MEM_32bits(void) { return sizeof(size_t)==4; }
+MEM_STATIC unsigned MEM_64bits(void) { return sizeof(size_t)==8; }
+
+MEM_STATIC unsigned MEM_isLittleEndian(void)
+{
+#if defined(__BYTE_ORDER__) && defined(__ORDER_LITTLE_ENDIAN__) && (__BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__)
+    return 1;
+#elif defined(__BYTE_ORDER__) && defined(__ORDER_BIG_ENDIAN__) && (__BYTE_ORDER__ == __ORDER_BIG_ENDIAN__)
+    return 0;
+#elif defined(__clang__) && __LITTLE_ENDIAN__
+    return 1;
+#elif defined(__clang__) && __BIG_ENDIAN__
+    return 0;
+#elif defined(_MSC_VER) && (_M_X64 || _M_IX86)
+    return 1;
+#elif defined(__DMC__) && defined(_M_IX86)
+    return 1;
+#elif defined(__IAR_SYSTEMS_ICC__) && __LITTLE_ENDIAN__
+    return 1;
+#else
+    const union { U32 u; BYTE c[4]; } one = { 1 };   /* don't use static : performance detrimental  */
+    return one.c[0];
+#endif
+}
+
+#if defined(MEM_FORCE_MEMORY_ACCESS) && (MEM_FORCE_MEMORY_ACCESS==2)
+
+/* violates C standard, by lying on structure alignment.
+Only use if no other choice to achieve best performance on target platform */
+MEM_STATIC U16 MEM_read16(const void* memPtr) { return *(const U16*) memPtr; }
+MEM_STATIC U32 MEM_read32(const void* memPtr) { return *(const U32*) memPtr; }
+MEM_STATIC U64 MEM_read64(const void* memPtr) { return *(const U64*) memPtr; }
+MEM_STATIC size_t MEM_readST(const void* memPtr) { return *(const size_t*) memPtr; }
+
+MEM_STATIC void MEM_write16(void* memPtr, U16 value) { *(U16*)memPtr = value; }
+MEM_STATIC void MEM_write32(void* memPtr, U32 value) { *(U32*)memPtr = value; }
+MEM_STATIC void MEM_write64(void* memPtr, U64 value) { *(U64*)memPtr = value; }
+
+#elif defined(MEM_FORCE_MEMORY_ACCESS) && (MEM_FORCE_MEMORY_ACCESS==1)
+
+typedef __attribute__((aligned(1))) U16 unalign16;
+typedef __attribute__((aligned(1))) U32 unalign32;
+typedef __attribute__((aligned(1))) U64 unalign64;
+typedef __attribute__((aligned(1))) size_t unalignArch;
+
+MEM_STATIC U16 MEM_read16(const void* ptr) { return *(const unalign16*)ptr; }
+MEM_STATIC U32 MEM_read32(const void* ptr) { return *(const unalign32*)ptr; }
+MEM_STATIC U64 MEM_read64(const void* ptr) { return *(const unalign64*)ptr; }
+MEM_STATIC size_t MEM_readST(const void* ptr) { return *(const unalignArch*)ptr; }
+
+MEM_STATIC void MEM_write16(void* memPtr, U16 value) { *(unalign16*)memPtr = value; }
+MEM_STATIC void MEM_write32(void* memPtr, U32 value) { *(unalign32*)memPtr = value; }
+MEM_STATIC void MEM_write64(void* memPtr, U64 value) { *(unalign64*)memPtr = value; }
+
+#else
+
+/* default method, safe and standard.
+   can sometimes prove slower */
+
+MEM_STATIC U16 MEM_read16(const void* memPtr)
+{
+    U16 val; ZSTD_memcpy(&val, memPtr, sizeof(val)); return val;
+}
+
+MEM_STATIC U32 MEM_read32(const void* memPtr)
+{
+    U32 val; ZSTD_memcpy(&val, memPtr, sizeof(val)); return val;
+}
+
+MEM_STATIC U64 MEM_read64(const void* memPtr)
+{
+    U64 val; ZSTD_memcpy(&val, memPtr, sizeof(val)); return val;
+}
+
+MEM_STATIC size_t MEM_readST(const void* memPtr)
+{
+    size_t val; ZSTD_memcpy(&val, memPtr, sizeof(val)); return val;
+}
+
+MEM_STATIC void MEM_write16(void* memPtr, U16 value)
+{
+    ZSTD_memcpy(memPtr, &value, sizeof(value));
+}
+
+MEM_STATIC void MEM_write32(void* memPtr, U32 value)
+{
+    ZSTD_memcpy(memPtr, &value, sizeof(value));
+}
+
+MEM_STATIC void MEM_write64(void* memPtr, U64 value)
+{
+    ZSTD_memcpy(memPtr, &value, sizeof(value));
+}
+
+#endif /* MEM_FORCE_MEMORY_ACCESS */
+
+MEM_STATIC U32 MEM_swap32_fallback(U32 in)
+{
+    return  ((in << 24) & 0xff000000 ) |
+            ((in <<  8) & 0x00ff0000 ) |
+            ((in >>  8) & 0x0000ff00 ) |
+            ((in >> 24) & 0x000000ff );
+}
+
+MEM_STATIC U32 MEM_swap32(U32 in)
+{
+#if defined(_MSC_VER)     /* Visual Studio */
+    return _byteswap_ulong(in);
+#elif (defined (__GNUC__) && (__GNUC__ * 100 + __GNUC_MINOR__ >= 403)) \
+  || (defined(__clang__) && __has_builtin(__builtin_bswap32))
+    return __builtin_bswap32(in);
+#elif defined(__ICCARM__)
+    return __REV(in);
+#else
+    return MEM_swap32_fallback(in);
+#endif
+}
+
+MEM_STATIC U64 MEM_swap64_fallback(U64 in)
+{
+     return  ((in << 56) & 0xff00000000000000ULL) |
+            ((in << 40) & 0x00ff000000000000ULL) |
+            ((in << 24) & 0x0000ff0000000000ULL) |
+            ((in << 8)  & 0x000000ff00000000ULL) |
+            ((in >> 8)  & 0x00000000ff000000ULL) |
+            ((in >> 24) & 0x0000000000ff0000ULL) |
+            ((in >> 40) & 0x000000000000ff00ULL) |
+            ((in >> 56) & 0x00000000000000ffULL);
+}
+
+MEM_STATIC U64 MEM_swap64(U64 in)
+{
+#if defined(_MSC_VER)     /* Visual Studio */
+    return _byteswap_uint64(in);
+#elif (defined (__GNUC__) && (__GNUC__ * 100 + __GNUC_MINOR__ >= 403)) \
+  || (defined(__clang__) && __has_builtin(__builtin_bswap64))
+    return __builtin_bswap64(in);
+#else
+    return MEM_swap64_fallback(in);
+#endif
+}
+
+MEM_STATIC size_t MEM_swapST(size_t in)
+{
+    if (MEM_32bits())
+        return (size_t)MEM_swap32((U32)in);
+    else
+        return (size_t)MEM_swap64((U64)in);
+}
+
+/*=== Little endian r/w ===*/
+
+MEM_STATIC U16 MEM_readLE16(const void* memPtr)
+{
+    if (MEM_isLittleEndian())
+        return MEM_read16(memPtr);
+    else {
+        const BYTE* p = (const BYTE*)memPtr;
+        return (U16)(p[0] + (p[1]<<8));
+    }
+}
+
+MEM_STATIC void MEM_writeLE16(void* memPtr, U16 val)
+{
+    if (MEM_isLittleEndian()) {
+        MEM_write16(memPtr, val);
+    } else {
+        BYTE* p = (BYTE*)memPtr;
+        p[0] = (BYTE)val;
+        p[1] = (BYTE)(val>>8);
+    }
+}
+
+MEM_STATIC U32 MEM_readLE24(const void* memPtr)
+{
+    return (U32)MEM_readLE16(memPtr) + ((U32)(((const BYTE*)memPtr)[2]) << 16);
+}
+
+MEM_STATIC void MEM_writeLE24(void* memPtr, U32 val)
+{
+    MEM_writeLE16(memPtr, (U16)val);
+    ((BYTE*)memPtr)[2] = (BYTE)(val>>16);
+}
+
+MEM_STATIC U32 MEM_readLE32(const void* memPtr)
+{
+    if (MEM_isLittleEndian())
+        return MEM_read32(memPtr);
+    else
+        return MEM_swap32(MEM_read32(memPtr));
+}
+
+MEM_STATIC void MEM_writeLE32(void* memPtr, U32 val32)
+{
+    if (MEM_isLittleEndian())
+        MEM_write32(memPtr, val32);
+    else
+        MEM_write32(memPtr, MEM_swap32(val32));
+}
+
+MEM_STATIC U64 MEM_readLE64(const void* memPtr)
+{
+    if (MEM_isLittleEndian())
+        return MEM_read64(memPtr);
+    else
+        return MEM_swap64(MEM_read64(memPtr));
+}
+
+MEM_STATIC void MEM_writeLE64(void* memPtr, U64 val64)
+{
+    if (MEM_isLittleEndian())
+        MEM_write64(memPtr, val64);
+    else
+        MEM_write64(memPtr, MEM_swap64(val64));
+}
+
+MEM_STATIC size_t MEM_readLEST(const void* memPtr)
+{
+    if (MEM_32bits())
+        return (size_t)MEM_readLE32(memPtr);
+    else
+        return (size_t)MEM_readLE64(memPtr);
+}
+
+MEM_STATIC void MEM_writeLEST(void* memPtr, size_t val)
+{
+    if (MEM_32bits())
+        MEM_writeLE32(memPtr, (U32)val);
+    else
+        MEM_writeLE64(memPtr, (U64)val);
+}
+
+/*=== Big endian r/w ===*/
+
+MEM_STATIC U32 MEM_readBE32(const void* memPtr)
+{
+    if (MEM_isLittleEndian())
+        return MEM_swap32(MEM_read32(memPtr));
+    else
+        return MEM_read32(memPtr);
+}
+
+MEM_STATIC void MEM_writeBE32(void* memPtr, U32 val32)
+{
+    if (MEM_isLittleEndian())
+        MEM_write32(memPtr, MEM_swap32(val32));
+    else
+        MEM_write32(memPtr, val32);
+}
+
+MEM_STATIC U64 MEM_readBE64(const void* memPtr)
+{
+    if (MEM_isLittleEndian())
+        return MEM_swap64(MEM_read64(memPtr));
+    else
+        return MEM_read64(memPtr);
+}
+
+MEM_STATIC void MEM_writeBE64(void* memPtr, U64 val64)
+{
+    if (MEM_isLittleEndian())
+        MEM_write64(memPtr, MEM_swap64(val64));
+    else
+        MEM_write64(memPtr, val64);
+}
+
+MEM_STATIC size_t MEM_readBEST(const void* memPtr)
+{
+    if (MEM_32bits())
+        return (size_t)MEM_readBE32(memPtr);
+    else
+        return (size_t)MEM_readBE64(memPtr);
+}
+
+MEM_STATIC void MEM_writeBEST(void* memPtr, size_t val)
+{
+    if (MEM_32bits())
+        MEM_writeBE32(memPtr, (U32)val);
+    else
+        MEM_writeBE64(memPtr, (U64)val);
+}
+
+/* code only tested on 32 and 64 bits systems */
+MEM_STATIC void MEM_check(void) { DEBUG_STATIC_ASSERT((sizeof(size_t)==4) || (sizeof(size_t)==8)); }
+
+#endif /* MEM_H_MODULE */
diff --git a/src/commonlib/bsd/zstd/common/portability_macros.h b/src/commonlib/bsd/zstd/common/portability_macros.h
new file mode 100644
index 0000000000..e61f0784d3
--- /dev/null
+++ b/src/commonlib/bsd/zstd/common/portability_macros.h
@@ -0,0 +1,173 @@
+/* SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0-only */
+
+/*
+ * Copyright (c) Meta Platforms, Inc. and affiliates.
+ * All rights reserved.
+ *
+ * This source code is licensed under both the BSD-style license (found in the
+ * LICENSE file in the root directory of this source tree) and the GPLv2 (found
+ * in the COPYING file in the root directory of this source tree).
+ * You may select, at your option, one of the above-listed licenses.
+ */
+
+#ifndef ZSTD_PORTABILITY_MACROS_H
+#define ZSTD_PORTABILITY_MACROS_H
+
+/**
+ * This header file contains macro definitions to support portability.
+ * This header is shared between C and ASM code, so it MUST only
+ * contain macro definitions. It MUST not contain any C code.
+ *
+ * This header ONLY defines macros to detect platforms/feature support.
+ *
+ */
+
+
+/* compat. with non-clang compilers */
+#ifndef __has_attribute
+  #define __has_attribute(x) 0
+#endif
+
+/* compat. with non-clang compilers */
+#ifndef __has_builtin
+#  define __has_builtin(x) 0
+#endif
+
+/* compat. with non-clang compilers */
+#ifndef __has_feature
+#  define __has_feature(x) 0
+#endif
+
+/* detects whether we are being compiled under msan */
+#ifndef ZSTD_MEMORY_SANITIZER
+#  if __has_feature(memory_sanitizer)
+#    define ZSTD_MEMORY_SANITIZER 1
+#  else
+#    define ZSTD_MEMORY_SANITIZER 0
+#  endif
+#endif
+
+/* detects whether we are being compiled under asan */
+#ifndef ZSTD_ADDRESS_SANITIZER
+#  if __has_feature(address_sanitizer)
+#    define ZSTD_ADDRESS_SANITIZER 1
+#  elif defined(__SANITIZE_ADDRESS__)
+#    define ZSTD_ADDRESS_SANITIZER 1
+#  else
+#    define ZSTD_ADDRESS_SANITIZER 0
+#  endif
+#endif
+
+/* detects whether we are being compiled under dfsan */
+#ifndef ZSTD_DATAFLOW_SANITIZER
+# if __has_feature(dataflow_sanitizer)
+#  define ZSTD_DATAFLOW_SANITIZER 1
+# else
+#  define ZSTD_DATAFLOW_SANITIZER 0
+# endif
+#endif
+
+/* Mark the internal assembly functions as hidden  */
+#ifdef __ELF__
+# define ZSTD_HIDE_ASM_FUNCTION(func) .hidden func
+#elif defined(__APPLE__)
+# define ZSTD_HIDE_ASM_FUNCTION(func) .private_extern func
+#else
+# define ZSTD_HIDE_ASM_FUNCTION(func)
+#endif
+
+/* Compile time determination of BMI2 support */
+#ifndef STATIC_BMI2
+#  if defined(__BMI2__)
+#    define STATIC_BMI2 1
+#  elif defined(_MSC_VER) && defined(__AVX2__)
+#    define STATIC_BMI2 1 /* MSVC does not have a BMI2 specific flag, but every CPU that supports AVX2 also supports BMI2 */
+#  endif
+#endif
+
+#ifndef STATIC_BMI2
+#  define STATIC_BMI2 0
+#endif
+
+/* Enable runtime BMI2 dispatch based on the CPU.
+ * Enabled for clang & gcc >=4.8 on x86 when BMI2 isn't enabled by default.
+ */
+#ifndef DYNAMIC_BMI2
+#  if ((defined(__clang__) && __has_attribute(__target__)) \
+      || (defined(__GNUC__) \
+          && (__GNUC__ >= 5 || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)))) \
+      && (defined(__i386__) || defined(__x86_64__) || defined(_M_IX86) || defined(_M_X64)) \
+      && !defined(__BMI2__)
+#    define DYNAMIC_BMI2 1
+#  else
+#    define DYNAMIC_BMI2 0
+#  endif
+#endif
+
+/**
+ * Only enable assembly for GNU C compatible compilers,
+ * because other platforms may not support GAS assembly syntax.
+ *
+ * Only enable assembly for Linux / MacOS / Win32, other platforms may
+ * work, but they haven't been tested. This could likely be
+ * extended to BSD systems.
+ *
+ * Disable assembly when MSAN is enabled, because MSAN requires
+ * 100% of code to be instrumented to work.
+ */
+#if defined(__GNUC__)
+#  if defined(__linux__) || defined(__linux) || defined(__APPLE__) || defined(_WIN32)
+#    if ZSTD_MEMORY_SANITIZER
+#      define ZSTD_ASM_SUPPORTED 0
+#    elif ZSTD_DATAFLOW_SANITIZER
+#      define ZSTD_ASM_SUPPORTED 0
+#    else
+#      define ZSTD_ASM_SUPPORTED 1
+#    endif
+#  else
+#    define ZSTD_ASM_SUPPORTED 0
+#  endif
+#else
+#  define ZSTD_ASM_SUPPORTED 0
+#endif
+
+/**
+ * Determines whether we should enable assembly for x86-64
+ * with BMI2.
+ *
+ * Enable if all of the following conditions hold:
+ * - ASM hasn't been explicitly disabled by defining ZSTD_DISABLE_ASM
+ * - Assembly is supported
+ * - We are compiling for x86-64 and either:
+ *   - DYNAMIC_BMI2 is enabled
+ *   - BMI2 is supported at compile time
+ */
+#if !defined(ZSTD_DISABLE_ASM) &&                                 \
+    ZSTD_ASM_SUPPORTED &&                                         \
+    defined(__x86_64__) &&                                        \
+    (DYNAMIC_BMI2 || defined(__BMI2__))
+# define ZSTD_ENABLE_ASM_X86_64_BMI2 1
+#else
+# define ZSTD_ENABLE_ASM_X86_64_BMI2 0
+#endif
+
+/*
+ * For x86 ELF targets, add .note.gnu.property section for Intel CET in
+ * assembly sources when CET is enabled.
+ *
+ * Additionally, any function that may be called indirectly must begin
+ * with ZSTD_CET_ENDBRANCH.
+ */
+#if defined(__ELF__) && (defined(__x86_64__) || defined(__i386__)) \
+    && defined(__has_include)
+# if __has_include(<cet.h>)
+#  include <cet.h>
+#  define ZSTD_CET_ENDBRANCH _CET_ENDBR
+# endif
+#endif
+
+#ifndef ZSTD_CET_ENDBRANCH
+# define ZSTD_CET_ENDBRANCH
+#endif
+
+#endif /* ZSTD_PORTABILITY_MACROS_H */
diff --git a/src/commonlib/bsd/zstd/common/zstd_bits.h b/src/commonlib/bsd/zstd/common/zstd_bits.h
new file mode 100644
index 0000000000..5128d00ccf
--- /dev/null
+++ b/src/commonlib/bsd/zstd/common/zstd_bits.h
@@ -0,0 +1,206 @@
+/* SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0-only */
+/*
+ * Copyright (c) Meta Platforms, Inc. and affiliates.
+ * All rights reserved.
+ *
+ * This source code is licensed under both the BSD-style license (found in the
+ * LICENSE file in the root directory of this source tree) and the GPLv2 (found
+ * in the COPYING file in the root directory of this source tree).
+ * You may select, at your option, one of the above-listed licenses.
+ */
+
+#ifndef ZSTD_BITS_H
+#define ZSTD_BITS_H
+
+#include "mem.h"
+
+MEM_STATIC unsigned ZSTD_countTrailingZeros32_fallback(U32 val)
+{
+    assert(val != 0);
+    {
+        static const U32 DeBruijnBytePos[32] = {0, 1, 28, 2, 29, 14, 24, 3,
+                                                30, 22, 20, 15, 25, 17, 4, 8,
+                                                31, 27, 13, 23, 21, 19, 16, 7,
+                                                26, 12, 18, 6, 11, 5, 10, 9};
+        return DeBruijnBytePos[((U32) ((val & -(S32) val) * 0x077CB531U)) >> 27];
+    }
+}
+
+MEM_STATIC unsigned ZSTD_countTrailingZeros32(U32 val)
+{
+    assert(val != 0);
+#if defined(_MSC_VER)
+#  if STATIC_BMI2
+    return (unsigned)_tzcnt_u32(val);
+#  else
+    if (val != 0) {
+        unsigned long r;
+        _BitScanForward(&r, val);
+        return (unsigned)r;
+    } else {
+        __assume(0); /* Should not reach this code path */
+    }
+#  endif
+#elif defined(__GNUC__) && (__GNUC__ >= 4)
+    return (unsigned)__builtin_ctz(val);
+#elif defined(__ICCARM__)
+    return (unsigned)__builtin_ctz(val);
+#else
+    return ZSTD_countTrailingZeros32_fallback(val);
+#endif
+}
+
+MEM_STATIC unsigned ZSTD_countLeadingZeros32_fallback(U32 val)
+{
+    assert(val != 0);
+    {
+        static const U32 DeBruijnClz[32] = {0, 9, 1, 10, 13, 21, 2, 29,
+                                            11, 14, 16, 18, 22, 25, 3, 30,
+                                            8, 12, 20, 28, 15, 17, 24, 7,
+                                            19, 27, 23, 6, 26, 5, 4, 31};
+        val |= val >> 1;
+        val |= val >> 2;
+        val |= val >> 4;
+        val |= val >> 8;
+        val |= val >> 16;
+        return 31 - DeBruijnClz[(val * 0x07C4ACDDU) >> 27];
+    }
+}
+
+MEM_STATIC unsigned ZSTD_countLeadingZeros32(U32 val)
+{
+    assert(val != 0);
+#if defined(_MSC_VER)
+#  if STATIC_BMI2
+    return (unsigned)_lzcnt_u32(val);
+#  else
+    if (val != 0) {
+        unsigned long r;
+        _BitScanReverse(&r, val);
+        return (unsigned)(31 - r);
+    } else {
+        __assume(0); /* Should not reach this code path */
+    }
+#  endif
+#elif defined(__GNUC__) && (__GNUC__ >= 4)
+    return (unsigned)__builtin_clz(val);
+#elif defined(__ICCARM__)
+    return (unsigned)__builtin_clz(val);
+#else
+    return ZSTD_countLeadingZeros32_fallback(val);
+#endif
+}
+
+MEM_STATIC unsigned ZSTD_countTrailingZeros64(U64 val)
+{
+    assert(val != 0);
+#if defined(_MSC_VER) && defined(_WIN64)
+#  if STATIC_BMI2
+    return (unsigned)_tzcnt_u64(val);
+#  else
+    if (val != 0) {
+        unsigned long r;
+        _BitScanForward64(&r, val);
+        return (unsigned)r;
+    } else {
+        __assume(0); /* Should not reach this code path */
+    }
+#  endif
+#elif defined(__GNUC__) && (__GNUC__ >= 4) && defined(__LP64__)
+    return (unsigned)__builtin_ctzll(val);
+#elif defined(__ICCARM__)
+    return (unsigned)__builtin_ctzll(val);
+#else
+    {
+        U32 mostSignificantWord = (U32)(val >> 32);
+        U32 leastSignificantWord = (U32)val;
+        if (leastSignificantWord == 0) {
+            return 32 + ZSTD_countTrailingZeros32(mostSignificantWord);
+        } else {
+            return ZSTD_countTrailingZeros32(leastSignificantWord);
+        }
+    }
+#endif
+}
+
+MEM_STATIC unsigned ZSTD_countLeadingZeros64(U64 val)
+{
+    assert(val != 0);
+#if defined(_MSC_VER) && defined(_WIN64)
+#  if STATIC_BMI2
+    return (unsigned)_lzcnt_u64(val);
+#  else
+    if (val != 0) {
+        unsigned long r;
+        _BitScanReverse64(&r, val);
+        return (unsigned)(63 - r);
+    } else {
+        __assume(0); /* Should not reach this code path */
+    }
+#  endif
+#elif defined(__GNUC__) && (__GNUC__ >= 4)
+    return (unsigned)(__builtin_clzll(val));
+#elif defined(__ICCARM__)
+    return (unsigned)(__builtin_clzll(val));
+#else
+    {
+        U32 mostSignificantWord = (U32)(val >> 32);
+        U32 leastSignificantWord = (U32)val;
+        if (mostSignificantWord == 0) {
+            return 32 + ZSTD_countLeadingZeros32(leastSignificantWord);
+        } else {
+            return ZSTD_countLeadingZeros32(mostSignificantWord);
+        }
+    }
+#endif
+}
+
+MEM_STATIC unsigned ZSTD_NbCommonBytes(size_t val)
+{
+    if (MEM_isLittleEndian()) {
+        if (MEM_64bits()) {
+            return ZSTD_countTrailingZeros64((U64)val) >> 3;
+        } else {
+            return ZSTD_countTrailingZeros32((U32)val) >> 3;
+        }
+    } else {  /* Big Endian CPU */
+        if (MEM_64bits()) {
+            return ZSTD_countLeadingZeros64((U64)val) >> 3;
+        } else {
+            return ZSTD_countLeadingZeros32((U32)val) >> 3;
+        }
+    }
+}
+
+MEM_STATIC unsigned ZSTD_highbit32(U32 val)   /* compress, dictBuilder, decodeCorpus */
+{
+    assert(val != 0);
+    return 31 - ZSTD_countLeadingZeros32(val);
+}
+
+/* ZSTD_rotateRight_*():
+ * Rotates a bitfield to the right by "count" bits.
+ * https://en.wikipedia.org/w/index.php?title=Circular_shift&oldid=991635599#Implementing_circular_shifts
+ */
+MEM_STATIC
+U64 ZSTD_rotateRight_U64(U64 const value, U32 count) {
+    assert(count < 64);
+    count &= 0x3F; /* for fickle pattern recognition */
+    return (value >> count) | (U64)(value << ((0U - count) & 0x3F));
+}
+
+MEM_STATIC
+U32 ZSTD_rotateRight_U32(U32 const value, U32 count) {
+    assert(count < 32);
+    count &= 0x1F; /* for fickle pattern recognition */
+    return (value >> count) | (U32)(value << ((0U - count) & 0x1F));
+}
+
+MEM_STATIC
+U16 ZSTD_rotateRight_U16(U16 const value, U32 count) {
+    assert(count < 16);
+    count &= 0x0F; /* for fickle pattern recognition */
+    return (value >> count) | (U16)(value << ((0U - count) & 0x0F));
+}
+
+#endif /* ZSTD_BITS_H */
diff --git a/src/commonlib/bsd/zstd/common/zstd_common.c b/src/commonlib/bsd/zstd/common/zstd_common.c
new file mode 100644
index 0000000000..9b551ec867
--- /dev/null
+++ b/src/commonlib/bsd/zstd/common/zstd_common.c
@@ -0,0 +1,50 @@
+/* SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0-only */
+
+/*
+ * Copyright (c) Meta Platforms, Inc. and affiliates.
+ * All rights reserved.
+ *
+ * This source code is licensed under both the BSD-style license (found in the
+ * LICENSE file in the root directory of this source tree) and the GPLv2 (found
+ * in the COPYING file in the root directory of this source tree).
+ * You may select, at your option, one of the above-listed licenses.
+ */
+
+
+
+/*-*************************************
+*  Dependencies
+***************************************/
+#define ZSTD_DEPS_NEED_MALLOC
+#include "error_private.h"
+#include "zstd_internal.h"
+
+
+/*-****************************************
+*  Version
+******************************************/
+unsigned ZSTD_versionNumber(void) { return ZSTD_VERSION_NUMBER; }
+
+const char* ZSTD_versionString(void) { return ZSTD_VERSION_STRING; }
+
+
+/*-****************************************
+*  ZSTD Error Management
+******************************************/
+#undef ZSTD_isError   /* defined within zstd_internal.h */
+/*! ZSTD_isError() :
+ *  tells if a return value is an error code
+ *  symbol is required for external callers */
+unsigned ZSTD_isError(size_t code) { return ERR_isError(code); }
+
+/*! ZSTD_getErrorName() :
+ *  provides error code string from function result (useful for debugging) */
+const char* ZSTD_getErrorName(size_t code) { return ERR_getErrorName(code); }
+
+/*! ZSTD_getError() :
+ *  convert a `size_t` function result into a proper ZSTD_errorCode enum */
+ZSTD_ErrorCode ZSTD_getErrorCode(size_t code) { return ERR_getErrorCode(code); }
+
+/*! ZSTD_getErrorString() :
+ *  provides error code string from enum */
+const char* ZSTD_getErrorString(ZSTD_ErrorCode code) { return ERR_getErrorString(code); }
diff --git a/src/commonlib/bsd/zstd/common/zstd_compiler.h b/src/commonlib/bsd/zstd/common/zstd_compiler.h
new file mode 100644
index 0000000000..80df87162e
--- /dev/null
+++ b/src/commonlib/bsd/zstd/common/zstd_compiler.h
@@ -0,0 +1,462 @@
+/* SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0-only */
+/*
+ * Copyright (c) Meta Platforms, Inc. and affiliates.
+ * All rights reserved.
+ *
+ * This source code is licensed under both the BSD-style license (found in the
+ * LICENSE file in the root directory of this source tree) and the GPLv2 (found
+ * in the COPYING file in the root directory of this source tree).
+ * You may select, at your option, one of the above-listed licenses.
+ */
+
+#ifndef ZSTD_COMPILER_H
+#define ZSTD_COMPILER_H
+
+#include <stddef.h>
+
+#include "portability_macros.h"
+
+/*-*******************************************************
+*  Compiler specifics
+*********************************************************/
+/* force inlining */
+
+#if !defined(ZSTD_NO_INLINE)
+#if (defined(__GNUC__) && !defined(__STRICT_ANSI__)) || defined(__cplusplus) || defined(__STDC_VERSION__) && __STDC_VERSION__ >= 199901L   /* C99 */
+#  define INLINE_KEYWORD inline
+#else
+#  define INLINE_KEYWORD
+#endif
+
+#if defined(__GNUC__) || defined(__IAR_SYSTEMS_ICC__)
+#  define FORCE_INLINE_ATTR __attribute__((always_inline))
+#elif defined(_MSC_VER)
+#  define FORCE_INLINE_ATTR __forceinline
+#else
+#  define FORCE_INLINE_ATTR
+#endif
+
+#else
+
+#define INLINE_KEYWORD
+#define FORCE_INLINE_ATTR
+
+#endif
+
+/**
+  On MSVC qsort requires that functions passed into it use the __cdecl calling conversion(CC).
+  This explicitly marks such functions as __cdecl so that the code will still compile
+  if a CC other than __cdecl has been made the default.
+*/
+#if  defined(_MSC_VER)
+#  define WIN_CDECL __cdecl
+#else
+#  define WIN_CDECL
+#endif
+
+/* UNUSED_ATTR tells the compiler it is okay if the function is unused. */
+#if defined(__GNUC__) || defined(__IAR_SYSTEMS_ICC__)
+#  define UNUSED_ATTR __attribute__((unused))
+#else
+#  define UNUSED_ATTR
+#endif
+
+/**
+ * FORCE_INLINE_TEMPLATE is used to define C "templates", which take constant
+ * parameters. They must be inlined for the compiler to eliminate the constant
+ * branches.
+ */
+#define FORCE_INLINE_TEMPLATE static INLINE_KEYWORD FORCE_INLINE_ATTR UNUSED_ATTR
+/**
+ * HINT_INLINE is used to help the compiler generate better code. It is *not*
+ * used for "templates", so it can be tweaked based on the compilers
+ * performance.
+ *
+ * gcc-4.8 and gcc-4.9 have been shown to benefit from leaving off the
+ * always_inline attribute.
+ *
+ * clang up to 5.0.0 (trunk) benefit tremendously from the always_inline
+ * attribute.
+ */
+#if !defined(__clang__) && defined(__GNUC__) && __GNUC__ >= 4 && __GNUC_MINOR__ >= 8 && __GNUC__ < 5
+#  define HINT_INLINE static INLINE_KEYWORD
+#else
+#  define HINT_INLINE FORCE_INLINE_TEMPLATE
+#endif
+
+/* "soft" inline :
+ * The compiler is free to select if it's a good idea to inline or not.
+ * The main objective is to silence compiler warnings
+ * when a defined function in included but not used.
+ *
+ * Note : this macro is prefixed `MEM_` because it used to be provided by `mem.h` unit.
+ * Updating the prefix is probably preferable, but requires a fairly large codemod,
+ * since this name is used everywhere.
+ */
+#ifndef MEM_STATIC  /* already defined in Linux Kernel mem.h */
+#if defined(__GNUC__)
+#  define MEM_STATIC static __inline UNUSED_ATTR
+#elif defined(__IAR_SYSTEMS_ICC__)
+#  define MEM_STATIC static inline UNUSED_ATTR
+#elif defined (__cplusplus) || (defined (__STDC_VERSION__) && (__STDC_VERSION__ >= 199901L) /* C99 */)
+#  define MEM_STATIC static inline
+#elif defined(_MSC_VER)
+#  define MEM_STATIC static __inline
+#else
+#  define MEM_STATIC static  /* this version may generate warnings for unused static functions; disable the relevant warning */
+#endif
+#endif
+
+/* force no inlining */
+#ifdef _MSC_VER
+#  define FORCE_NOINLINE static __declspec(noinline)
+#else
+#  if defined(__GNUC__) || defined(__IAR_SYSTEMS_ICC__)
+#    define FORCE_NOINLINE static __attribute__((__noinline__))
+#  else
+#    define FORCE_NOINLINE static
+#  endif
+#endif
+
+
+/* target attribute */
+#if defined(__GNUC__) || defined(__IAR_SYSTEMS_ICC__)
+#  define TARGET_ATTRIBUTE(target) __attribute__((__target__(target)))
+#else
+#  define TARGET_ATTRIBUTE(target)
+#endif
+
+/* Target attribute for BMI2 dynamic dispatch.
+ * Enable lzcnt, bmi, and bmi2.
+ * We test for bmi1 & bmi2. lzcnt is included in bmi1.
+ */
+#define BMI2_TARGET_ATTRIBUTE TARGET_ATTRIBUTE("lzcnt,bmi,bmi2")
+
+/* prefetch
+ * can be disabled, by declaring NO_PREFETCH build macro */
+#if defined(NO_PREFETCH)
+#  define PREFETCH_L1(ptr)  do { (void)(ptr); } while (0)  /* disabled */
+#  define PREFETCH_L2(ptr)  do { (void)(ptr); } while (0)  /* disabled */
+#else
+#  if defined(_MSC_VER) && (defined(_M_X64) || defined(_M_I86)) && !defined(_M_ARM64EC)  /* _mm_prefetch() is not defined outside of x86/x64 */
+#    include <mmintrin.h>   /* https://msdn.microsoft.com/fr-fr/library/84szxsww(v=vs.90).aspx */
+#    define PREFETCH_L1(ptr)  _mm_prefetch((const char*)(ptr), _MM_HINT_T0)
+#    define PREFETCH_L2(ptr)  _mm_prefetch((const char*)(ptr), _MM_HINT_T1)
+#  elif defined(__GNUC__) && ( (__GNUC__ >= 4) || ( (__GNUC__ == 3) && (__GNUC_MINOR__ >= 1) ) )
+#    define PREFETCH_L1(ptr)  __builtin_prefetch((ptr), 0 /* rw==read */, 3 /* locality */)
+#    define PREFETCH_L2(ptr)  __builtin_prefetch((ptr), 0 /* rw==read */, 2 /* locality */)
+#  elif defined(__aarch64__)
+#    define PREFETCH_L1(ptr)  do { __asm__ __volatile__("prfm pldl1keep, %0" ::"Q"(*(ptr))); } while (0)
+#    define PREFETCH_L2(ptr)  do { __asm__ __volatile__("prfm pldl2keep, %0" ::"Q"(*(ptr))); } while (0)
+#  else
+#    define PREFETCH_L1(ptr) do { (void)(ptr); } while (0)  /* disabled */
+#    define PREFETCH_L2(ptr) do { (void)(ptr); } while (0)  /* disabled */
+#  endif
+#endif  /* NO_PREFETCH */
+
+#define CACHELINE_SIZE 64
+
+#define PREFETCH_AREA(p, s)                              \
+    do {                                                 \
+        const char* const _ptr = (const char*)(p);       \
+        size_t const _size = (size_t)(s);                \
+        size_t _pos;                                     \
+        for (_pos=0; _pos<_size; _pos+=CACHELINE_SIZE) { \
+            PREFETCH_L2(_ptr + _pos);                    \
+        }                                                \
+    } while (0)
+
+/* vectorization
+ * older GCC (pre gcc-4.3 picked as the cutoff) uses a different syntax,
+ * and some compilers, like Intel ICC and MCST LCC, do not support it at all. */
+#if !defined(__INTEL_COMPILER) && !defined(__clang__) && defined(__GNUC__) && !defined(__LCC__)
+#  if (__GNUC__ == 4 && __GNUC_MINOR__ > 3) || (__GNUC__ >= 5)
+#    define DONT_VECTORIZE __attribute__((optimize("no-tree-vectorize")))
+#  else
+#    define DONT_VECTORIZE _Pragma("GCC optimize(\"no-tree-vectorize\")")
+#  endif
+#else
+#  define DONT_VECTORIZE
+#endif
+
+/* Tell the compiler that a branch is likely or unlikely.
+ * Only use these macros if it causes the compiler to generate better code.
+ * If you can remove a LIKELY/UNLIKELY annotation without speed changes in gcc
+ * and clang, please do.
+ */
+#if defined(__GNUC__)
+#define LIKELY(x) (__builtin_expect((x), 1))
+#define UNLIKELY(x) (__builtin_expect((x), 0))
+#else
+#define LIKELY(x) (x)
+#define UNLIKELY(x) (x)
+#endif
+
+#if __has_builtin(__builtin_unreachable) || (defined(__GNUC__) && (__GNUC__ > 4 || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5)))
+#  define ZSTD_UNREACHABLE do { assert(0), __builtin_unreachable(); } while (0)
+#else
+#  define ZSTD_UNREACHABLE do { assert(0); } while (0)
+#endif
+
+/* disable warnings */
+#ifdef _MSC_VER    /* Visual Studio */
+#  include <intrin.h>                    /* For Visual 2005 */
+#  pragma warning(disable : 4100)        /* disable: C4100: unreferenced formal parameter */
+#  pragma warning(disable : 4127)        /* disable: C4127: conditional expression is constant */
+#  pragma warning(disable : 4204)        /* disable: C4204: non-constant aggregate initializer */
+#  pragma warning(disable : 4214)        /* disable: C4214: non-int bitfields */
+#  pragma warning(disable : 4324)        /* disable: C4324: padded structure */
+#endif
+
+/* compile time determination of SIMD support */
+#if !defined(ZSTD_NO_INTRINSICS)
+#  if defined(__AVX2__)
+#    define ZSTD_ARCH_X86_AVX2
+#  endif
+#  if defined(__SSE2__) || defined(_M_X64) || (defined (_M_IX86) && defined(_M_IX86_FP) && (_M_IX86_FP >= 2))
+#    define ZSTD_ARCH_X86_SSE2
+#  endif
+#
+#  if defined(ZSTD_ARCH_X86_AVX2)
+#    include <immintrin.h>
+#  endif
+#  if defined(ZSTD_ARCH_X86_SSE2)
+#    include <emmintrin.h>
+#  elif defined(ZSTD_ARCH_ARM_NEON)
+#    include <arm_neon.h>
+#  endif
+#endif
+
+/* C-language Attributes are added in C23. */
+#if defined(__STDC_VERSION__) && (__STDC_VERSION__ > 201710L) && defined(__has_c_attribute)
+# define ZSTD_HAS_C_ATTRIBUTE(x) __has_c_attribute(x)
+#else
+# define ZSTD_HAS_C_ATTRIBUTE(x) 0
+#endif
+
+/* Only use C++ attributes in C++. Some compilers report support for C++
+ * attributes when compiling with C.
+ */
+#if defined(__cplusplus) && defined(__has_cpp_attribute)
+# define ZSTD_HAS_CPP_ATTRIBUTE(x) __has_cpp_attribute(x)
+#else
+# define ZSTD_HAS_CPP_ATTRIBUTE(x) 0
+#endif
+
+/* Define ZSTD_FALLTHROUGH macro for annotating switch case with the 'fallthrough' attribute.
+ * - C23: https://en.cppreference.com/w/c/language/attributes/fallthrough
+ * - CPP17: https://en.cppreference.com/w/cpp/language/attributes/fallthrough
+ * - Else: __attribute__((__fallthrough__))
+ */
+#ifndef ZSTD_FALLTHROUGH
+# if ZSTD_HAS_C_ATTRIBUTE(fallthrough)
+#  define ZSTD_FALLTHROUGH [[fallthrough]]
+# elif ZSTD_HAS_CPP_ATTRIBUTE(fallthrough)
+#  define ZSTD_FALLTHROUGH [[fallthrough]]
+# elif __has_attribute(__fallthrough__)
+/* Leading semicolon is to satisfy gcc-11 with -pedantic. Without the semicolon
+ * gcc complains about: a label can only be part of a statement and a declaration is not a statement.
+ */
+#  define ZSTD_FALLTHROUGH ; __attribute__((__fallthrough__))
+# else
+#  define ZSTD_FALLTHROUGH
+# endif
+#endif
+
+/*-**************************************************************
+*  Alignment
+*****************************************************************/
+
+/* @return 1 if @u is a 2^n value, 0 otherwise
+ * useful to check a value is valid for alignment restrictions */
+MEM_STATIC int ZSTD_isPower2(size_t u) {
+    return (u & (u-1)) == 0;
+}
+
+/* this test was initially positioned in mem.h,
+ * but this file is removed (or replaced) for linux kernel
+ * so it's now hosted in compiler.h,
+ * which remains valid for both user & kernel spaces.
+ */
+
+#ifndef ZSTD_ALIGNOF
+# if defined(__GNUC__) || defined(_MSC_VER)
+/* covers gcc, clang & MSVC */
+/* note : this section must come first, before C11,
+ * due to a limitation in the kernel source generator */
+#  define ZSTD_ALIGNOF(T) __alignof(T)
+
+# elif defined(__STDC_VERSION__) && (__STDC_VERSION__ >= 201112L)
+/* C11 support */
+#  include <stdalign.h>
+#  define ZSTD_ALIGNOF(T) alignof(T)
+
+# else
+/* No known support for alignof() - imperfect backup */
+#  define ZSTD_ALIGNOF(T) (sizeof(void*) < sizeof(T) ? sizeof(void*) : sizeof(T))
+
+# endif
+#endif /* ZSTD_ALIGNOF */
+
+#ifndef ZSTD_ALIGNED
+/* C90-compatible alignment macro (GCC/Clang). Adjust for other compilers if needed. */
+# if defined(__GNUC__) || defined(__clang__)
+#  define ZSTD_ALIGNED(a) __attribute__((aligned(a)))
+# elif defined(__STDC_VERSION__) && (__STDC_VERSION__ >= 201112L) /* C11 */
+#  define ZSTD_ALIGNED(a) _Alignas(a)
+#elif defined(_MSC_VER)
+#  define ZSTD_ALIGNED(n) __declspec(align(n))
+# else
+   /* this compiler will require its own alignment instruction */
+#  define ZSTD_ALIGNED(...)
+# endif
+#endif /* ZSTD_ALIGNED */
+
+
+/*-**************************************************************
+*  Sanitizer
+*****************************************************************/
+
+/**
+ * Zstd relies on pointer overflow in its decompressor.
+ * We add this attribute to functions that rely on pointer overflow.
+ */
+#ifndef ZSTD_ALLOW_POINTER_OVERFLOW_ATTR
+#  if __has_attribute(no_sanitize)
+#    if !defined(__clang__) && defined(__GNUC__) && __GNUC__ < 8
+       /* gcc < 8 only has signed-integer-overlow which triggers on pointer overflow */
+#      define ZSTD_ALLOW_POINTER_OVERFLOW_ATTR __attribute__((no_sanitize("signed-integer-overflow")))
+#    else
+       /* older versions of clang [3.7, 5.0) will warn that pointer-overflow is ignored. */
+#      define ZSTD_ALLOW_POINTER_OVERFLOW_ATTR __attribute__((no_sanitize("pointer-overflow")))
+#    endif
+#  else
+#    define ZSTD_ALLOW_POINTER_OVERFLOW_ATTR
+#  endif
+#endif
+
+/**
+ * Helper function to perform a wrapped pointer difference without triggering
+ * UBSAN.
+ *
+ * @returns lhs - rhs with wrapping
+ */
+MEM_STATIC
+ZSTD_ALLOW_POINTER_OVERFLOW_ATTR
+ptrdiff_t ZSTD_wrappedPtrDiff(unsigned char const* lhs, unsigned char const* rhs)
+{
+    return lhs - rhs;
+}
+
+/**
+ * Helper function to perform a wrapped pointer add without triggering UBSAN.
+ *
+ * @return ptr + add with wrapping
+ */
+MEM_STATIC
+ZSTD_ALLOW_POINTER_OVERFLOW_ATTR
+unsigned char const* ZSTD_wrappedPtrAdd(unsigned char const* ptr, ptrdiff_t add)
+{
+    return ptr + add;
+}
+
+/**
+ * Helper function to perform a wrapped pointer subtraction without triggering
+ * UBSAN.
+ *
+ * @return ptr - sub with wrapping
+ */
+MEM_STATIC
+ZSTD_ALLOW_POINTER_OVERFLOW_ATTR
+unsigned char const* ZSTD_wrappedPtrSub(unsigned char const* ptr, ptrdiff_t sub)
+{
+    return ptr - sub;
+}
+
+/**
+ * Helper function to add to a pointer that works around C's undefined behavior
+ * of adding 0 to NULL.
+ *
+ * @returns `ptr + add` except it defines `NULL + 0 == NULL`.
+ */
+MEM_STATIC
+unsigned char* ZSTD_maybeNullPtrAdd(unsigned char* ptr, ptrdiff_t add)
+{
+    return add > 0 ? ptr + add : ptr;
+}
+
+/* Issue #3240 reports an ASAN failure on an llvm-mingw build. Out of an
+ * abundance of caution, disable our custom poisoning on mingw. */
+#ifdef __MINGW32__
+#ifndef ZSTD_ASAN_DONT_POISON_WORKSPACE
+#define ZSTD_ASAN_DONT_POISON_WORKSPACE 1
+#endif
+#ifndef ZSTD_MSAN_DONT_POISON_WORKSPACE
+#define ZSTD_MSAN_DONT_POISON_WORKSPACE 1
+#endif
+#endif
+
+#if ZSTD_MEMORY_SANITIZER && !defined(ZSTD_MSAN_DONT_POISON_WORKSPACE)
+/* Not all platforms that support msan provide sanitizers/msan_interface.h.
+ * We therefore declare the functions we need ourselves, rather than trying to
+ * include the header file... */
+#include <stddef.h>  /* size_t */
+#define ZSTD_DEPS_NEED_STDINT
+#include "zstd_deps.h"  /* intptr_t */
+
+/* Make memory region fully initialized (without changing its contents). */
+void __msan_unpoison(const volatile void *a, size_t size);
+
+/* Make memory region fully uninitialized (without changing its contents).
+   This is a legacy interface that does not update origin information. Use
+   __msan_allocated_memory() instead. */
+void __msan_poison(const volatile void *a, size_t size);
+
+/* Returns the offset of the first (at least partially) poisoned byte in the
+   memory range, or -1 if the whole range is good. */
+intptr_t __msan_test_shadow(const volatile void *x, size_t size);
+
+/* Print shadow and origin for the memory range to stderr in a human-readable
+   format. */
+void __msan_print_shadow(const volatile void *x, size_t size);
+#endif
+
+#if ZSTD_ADDRESS_SANITIZER && !defined(ZSTD_ASAN_DONT_POISON_WORKSPACE)
+/* Not all platforms that support asan provide sanitizers/asan_interface.h.
+ * We therefore declare the functions we need ourselves, rather than trying to
+ * include the header file... */
+#include <stddef.h>  /* size_t */
+
+/**
+ * Marks a memory region (<c>[addr, addr+size)</c>) as unaddressable.
+ *
+ * This memory must be previously allocated by your program. Instrumented
+ * code is forbidden from accessing addresses in this region until it is
+ * unpoisoned. This function is not guaranteed to poison the entire region -
+ * it could poison only a subregion of <c>[addr, addr+size)</c> due to ASan
+ * alignment restrictions.
+ *
+ * \note This function is not thread-safe because no two threads can poison or
+ * unpoison memory in the same memory region simultaneously.
+ *
+ * \param addr Start of memory region.
+ * \param size Size of memory region. */
+void __asan_poison_memory_region(void const volatile *addr, size_t size);
+
+/**
+ * Marks a memory region (<c>[addr, addr+size)</c>) as addressable.
+ *
+ * This memory must be previously allocated by your program. Accessing
+ * addresses in this region is allowed until this region is poisoned again.
+ * This function could unpoison a super-region of <c>[addr, addr+size)</c> due
+ * to ASan alignment restrictions.
+ *
+ * \note This function is not thread-safe because no two threads can
+ * poison or unpoison memory in the same memory region simultaneously.
+ *
+ * \param addr Start of memory region.
+ * \param size Size of memory region. */
+void __asan_unpoison_memory_region(void const volatile *addr, size_t size);
+#endif
+
+#endif /* ZSTD_COMPILER_H */
diff --git a/src/commonlib/bsd/zstd/common/zstd_deps.h b/src/commonlib/bsd/zstd/common/zstd_deps.h
new file mode 100644
index 0000000000..7ad8df1a21
--- /dev/null
+++ b/src/commonlib/bsd/zstd/common/zstd_deps.h
@@ -0,0 +1,125 @@
+/* SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0-only */
+
+/*
+ * Copyright (c) Meta Platforms, Inc. and affiliates.
+ * All rights reserved.
+ *
+ * This source code is licensed under both the BSD-style license (found in the
+ * LICENSE file in the root directory of this source tree) and the GPLv2 (found
+ * in the COPYING file in the root directory of this source tree).
+ * You may select, at your option, one of the above-listed licenses.
+ */
+
+/* This file provides common libc dependencies that zstd requires.
+ * The purpose is to allow replacing this file with a custom implementation
+ * to compile zstd without libc support.
+ */
+
+/* Need:
+ * NULL
+ * INT_MAX
+ * UINT_MAX
+ * ZSTD_memcpy()
+ * ZSTD_memset()
+ * ZSTD_memmove()
+ */
+#ifndef ZSTD_DEPS_COMMON
+#define ZSTD_DEPS_COMMON
+
+/* Even though we use qsort_r only for the dictionary builder, the macro
+ * _GNU_SOURCE has to be declared *before* the inclusion of any standard
+ * header and the script 'combine.sh' combines the whole zstd source code
+ * in a single file.
+ */
+#if defined(__linux) || defined(__linux__) || defined(linux) || defined(__gnu_linux__) || \
+    defined(__CYGWIN__) || defined(__MSYS__)
+#if !defined(_GNU_SOURCE) && !defined(__ANDROID__) /* NDK doesn't ship qsort_r(). */
+#define _GNU_SOURCE
+#endif
+#endif
+
+#include <limits.h>
+#include <stddef.h>
+#include <string.h>
+
+#if defined(__GNUC__) && __GNUC__ >= 4
+# define ZSTD_memcpy(d,s,l) __builtin_memcpy((d),(s),(l))
+# define ZSTD_memmove(d,s,l) __builtin_memmove((d),(s),(l))
+# define ZSTD_memset(p,v,l) __builtin_memset((p),(v),(l))
+#else
+# define ZSTD_memcpy(d,s,l) memcpy((d),(s),(l))
+# define ZSTD_memmove(d,s,l) memmove((d),(s),(l))
+# define ZSTD_memset(p,v,l) memset((p),(v),(l))
+#endif
+
+#endif /* ZSTD_DEPS_COMMON */
+
+/* Need:
+ * ZSTD_malloc()
+ * ZSTD_free()
+ * ZSTD_calloc()
+ */
+#ifdef ZSTD_DEPS_NEED_MALLOC
+#ifndef ZSTD_DEPS_MALLOC
+#define ZSTD_DEPS_MALLOC
+
+#include <stdlib.h>
+
+#define ZSTD_malloc(s) malloc(s)
+#define ZSTD_calloc(n,s) calloc((n), (s))
+#define ZSTD_free(p) free((p))
+
+#endif /* ZSTD_DEPS_MALLOC */
+#endif /* ZSTD_DEPS_NEED_MALLOC */
+
+/*
+ * Provides 64-bit math support.
+ * Need:
+ * U64 ZSTD_div64(U64 dividend, U32 divisor)
+ */
+#ifdef ZSTD_DEPS_NEED_MATH64
+#ifndef ZSTD_DEPS_MATH64
+#define ZSTD_DEPS_MATH64
+
+#define ZSTD_div64(dividend, divisor) ((dividend) / (divisor))
+
+#endif /* ZSTD_DEPS_MATH64 */
+#endif /* ZSTD_DEPS_NEED_MATH64 */
+
+/* Need:
+ * assert()
+ */
+#ifdef ZSTD_DEPS_NEED_ASSERT
+#ifndef ZSTD_DEPS_ASSERT
+#define ZSTD_DEPS_ASSERT
+
+#include <assert.h>
+
+#endif /* ZSTD_DEPS_ASSERT */
+#endif /* ZSTD_DEPS_NEED_ASSERT */
+
+/* Need:
+ * ZSTD_DEBUG_PRINT()
+ */
+#ifdef ZSTD_DEPS_NEED_IO
+#ifndef ZSTD_DEPS_IO
+#define ZSTD_DEPS_IO
+
+#include <stdio.h>
+#define ZSTD_DEBUG_PRINT(...) fprintf(stderr, __VA_ARGS__)
+
+#endif /* ZSTD_DEPS_IO */
+#endif /* ZSTD_DEPS_NEED_IO */
+
+/* Only requested when <stdint.h> is known to be present.
+ * Need:
+ * intptr_t
+ */
+#ifdef ZSTD_DEPS_NEED_STDINT
+#ifndef ZSTD_DEPS_STDINT
+#define ZSTD_DEPS_STDINT
+
+#include <stdint.h>
+
+#endif /* ZSTD_DEPS_STDINT */
+#endif /* ZSTD_DEPS_NEED_STDINT */
diff --git a/src/commonlib/bsd/zstd/common/zstd_internal.h b/src/commonlib/bsd/zstd/common/zstd_internal.h
new file mode 100644
index 0000000000..eef669f9d8
--- /dev/null
+++ b/src/commonlib/bsd/zstd/common/zstd_internal.h
@@ -0,0 +1,324 @@
+/* SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0-only */
+
+/*
+ * Copyright (c) Meta Platforms, Inc. and affiliates.
+ * All rights reserved.
+ *
+ * This source code is licensed under both the BSD-style license (found in the
+ * LICENSE file in the root directory of this source tree) and the GPLv2 (found
+ * in the COPYING file in the root directory of this source tree).
+ * You may select, at your option, one of the above-listed licenses.
+ */
+
+#ifndef ZSTD_CCOMMON_H_MODULE
+#define ZSTD_CCOMMON_H_MODULE
+
+/* this module contains definitions which must be identical
+ * across compression, decompression and dictBuilder.
+ * It also contains a few functions useful to at least 2 of them
+ * and which benefit from being inlined */
+
+/*-*************************************
+*  Dependencies
+***************************************/
+#include "zstd_compiler.h"
+#include "cpu.h"
+#include "mem.h"
+#include "debug.h"                 /* assert, DEBUGLOG, RAWLOG, g_debuglevel */
+#include "error_private.h"
+#define ZSTD_STATIC_LINKING_ONLY
+#include "../zstd.h"
+#define FSE_STATIC_LINKING_ONLY
+#include "fse.h"
+#include "huf.h"
+#include "zstd_xxhash.h"
+
+#ifndef ZSTD_NO_TRACE
+#  include "zstd_trace.h"
+#else
+#  define ZSTD_TRACE 0
+#endif
+
+/* ---- static assert (debug) --- */
+#define ZSTD_STATIC_ASSERT(c) DEBUG_STATIC_ASSERT(c)
+#define ZSTD_isError ERR_isError   /* for inlining */
+#define FSE_isError  ERR_isError
+#define HUF_isError  ERR_isError
+
+
+/*-*************************************
+*  shared macros
+***************************************/
+#undef MIN
+#undef MAX
+#define MIN(a,b) ((a)<(b) ? (a) : (b))
+#define MAX(a,b) ((a)>(b) ? (a) : (b))
+#define BOUNDED(min,val,max) (MAX(min,MIN(val,max)))
+
+
+/*-*************************************
+*  Common constants
+***************************************/
+#define ZSTD_OPT_NUM    (1<<12)
+
+#define ZSTD_REP_NUM      3                 /* number of repcodes */
+static UNUSED_ATTR const U32 repStartValue[ZSTD_REP_NUM] = { 1, 4, 8 };
+
+#define KB *(1 <<10)
+#define MB *(1 <<20)
+#define GB *(1U<<30)
+
+#define BIT7 128
+#define BIT6  64
+#define BIT5  32
+#define BIT4  16
+#define BIT1   2
+#define BIT0   1
+
+#define ZSTD_WINDOWLOG_ABSOLUTEMIN 10
+static UNUSED_ATTR const size_t ZSTD_fcs_fieldSize[4] = { 0, 2, 4, 8 };
+static UNUSED_ATTR const size_t ZSTD_did_fieldSize[4] = { 0, 1, 2, 4 };
+
+#define ZSTD_FRAMEIDSIZE 4   /* magic number size */
+
+#define ZSTD_BLOCKHEADERSIZE 3   /* C standard doesn't allow `static const` variable to be init using another `static const` variable */
+static UNUSED_ATTR const size_t ZSTD_blockHeaderSize = ZSTD_BLOCKHEADERSIZE;
+typedef enum { bt_raw, bt_rle, bt_compressed, bt_reserved } blockType_e;
+
+#define ZSTD_FRAMECHECKSUMSIZE 4
+
+#define MIN_SEQUENCES_SIZE 1 /* nbSeq==0 */
+#define MIN_CBLOCK_SIZE (1 /*litCSize*/ + 1 /* RLE or RAW */)   /* for a non-null block */
+#define MIN_LITERALS_FOR_4_STREAMS 6
+
+typedef enum { set_basic, set_rle, set_compressed, set_repeat } SymbolEncodingType_e;
+
+#define LONGNBSEQ 0x7F00
+
+#define MINMATCH 3
+
+#define Litbits  8
+#define LitHufLog 11
+#define MaxLit ((1<<Litbits) - 1)
+#define MaxML   52
+#define MaxLL   35
+#define DefaultMaxOff 28
+#define MaxOff  31
+#define MaxSeq MAX(MaxLL, MaxML)   /* Assumption : MaxOff < MaxLL,MaxML */
+#define MLFSELog    9
+#define LLFSELog    9
+#define OffFSELog   8
+#define MaxFSELog  MAX(MAX(MLFSELog, LLFSELog), OffFSELog)
+#define MaxMLBits 16
+#define MaxLLBits 16
+
+#define ZSTD_MAX_HUF_HEADER_SIZE 128 /* header + <= 127 byte tree description */
+/* Each table cannot take more than #symbols * FSELog bits */
+#define ZSTD_MAX_FSE_HEADERS_SIZE (((MaxML + 1) * MLFSELog + (MaxLL + 1) * LLFSELog + (MaxOff + 1) * OffFSELog + 7) / 8)
+
+static UNUSED_ATTR const U8 LL_bits[MaxLL+1] = {
+     0, 0, 0, 0, 0, 0, 0, 0,
+     0, 0, 0, 0, 0, 0, 0, 0,
+     1, 1, 1, 1, 2, 2, 3, 3,
+     4, 6, 7, 8, 9,10,11,12,
+    13,14,15,16
+};
+static UNUSED_ATTR const S16 LL_defaultNorm[MaxLL+1] = {
+     4, 3, 2, 2, 2, 2, 2, 2,
+     2, 2, 2, 2, 2, 1, 1, 1,
+     2, 2, 2, 2, 2, 2, 2, 2,
+     2, 3, 2, 1, 1, 1, 1, 1,
+    -1,-1,-1,-1
+};
+#define LL_DEFAULTNORMLOG 6  /* for static allocation */
+static UNUSED_ATTR const U32 LL_defaultNormLog = LL_DEFAULTNORMLOG;
+
+static UNUSED_ATTR const U8 ML_bits[MaxML+1] = {
+     0, 0, 0, 0, 0, 0, 0, 0,
+     0, 0, 0, 0, 0, 0, 0, 0,
+     0, 0, 0, 0, 0, 0, 0, 0,
+     0, 0, 0, 0, 0, 0, 0, 0,
+     1, 1, 1, 1, 2, 2, 3, 3,
+     4, 4, 5, 7, 8, 9,10,11,
+    12,13,14,15,16
+};
+static UNUSED_ATTR const S16 ML_defaultNorm[MaxML+1] = {
+     1, 4, 3, 2, 2, 2, 2, 2,
+     2, 1, 1, 1, 1, 1, 1, 1,
+     1, 1, 1, 1, 1, 1, 1, 1,
+     1, 1, 1, 1, 1, 1, 1, 1,
+     1, 1, 1, 1, 1, 1, 1, 1,
+     1, 1, 1, 1, 1, 1,-1,-1,
+    -1,-1,-1,-1,-1
+};
+#define ML_DEFAULTNORMLOG 6  /* for static allocation */
+static UNUSED_ATTR const U32 ML_defaultNormLog = ML_DEFAULTNORMLOG;
+
+static UNUSED_ATTR const S16 OF_defaultNorm[DefaultMaxOff+1] = {
+     1, 1, 1, 1, 1, 1, 2, 2,
+     2, 1, 1, 1, 1, 1, 1, 1,
+     1, 1, 1, 1, 1, 1, 1, 1,
+    -1,-1,-1,-1,-1
+};
+#define OF_DEFAULTNORMLOG 5  /* for static allocation */
+static UNUSED_ATTR const U32 OF_defaultNormLog = OF_DEFAULTNORMLOG;
+
+
+/*-*******************************************
+*  Shared functions to include for inlining
+*********************************************/
+static void ZSTD_copy8(void* dst, const void* src) {
+#if defined(ZSTD_ARCH_ARM_NEON)
+    vst1_u8((uint8_t*)dst, vld1_u8((const uint8_t*)src));
+#else
+    ZSTD_memcpy(dst, src, 8);
+#endif
+}
+#define COPY8(d,s) do { ZSTD_copy8(d,s); d+=8; s+=8; } while (0)
+
+/* Need to use memmove here since the literal buffer can now be located within
+   the dst buffer. In circumstances where the op "catches up" to where the
+   literal buffer is, there can be partial overlaps in this call on the final
+   copy if the literal is being shifted by less than 16 bytes. */
+static void ZSTD_copy16(void* dst, const void* src) {
+#if defined(ZSTD_ARCH_ARM_NEON)
+    vst1q_u8((uint8_t*)dst, vld1q_u8((const uint8_t*)src));
+#elif defined(ZSTD_ARCH_X86_SSE2)
+    _mm_storeu_si128((__m128i*)dst, _mm_loadu_si128((const __m128i*)src));
+#elif defined(__clang__)
+    ZSTD_memmove(dst, src, 16);
+#else
+    /* ZSTD_memmove is not inlined properly by gcc */
+    BYTE copy16_buf[16];
+    ZSTD_memcpy(copy16_buf, src, 16);
+    ZSTD_memcpy(dst, copy16_buf, 16);
+#endif
+}
+#define COPY16(d,s) do { ZSTD_copy16(d,s); d+=16; s+=16; } while (0)
+
+#define WILDCOPY_OVERLENGTH 32
+#define WILDCOPY_VECLEN 16
+
+typedef enum {
+    ZSTD_no_overlap,
+    ZSTD_overlap_src_before_dst
+    /*  ZSTD_overlap_dst_before_src, */
+} ZSTD_overlap_e;
+
+/*! ZSTD_wildcopy() :
+ *  Custom version of ZSTD_memcpy(), can over read/write up to WILDCOPY_OVERLENGTH bytes (if length==0)
+ *  @param ovtype controls the overlap detection
+ *         - ZSTD_no_overlap: The source and destination are guaranteed to be at least WILDCOPY_VECLEN bytes apart.
+ *         - ZSTD_overlap_src_before_dst: The src and dst may overlap, but they MUST be at least 8 bytes apart.
+ *           The src buffer must be before the dst buffer.
+ */
+MEM_STATIC FORCE_INLINE_ATTR
+void ZSTD_wildcopy(void* dst, const void* src, ptrdiff_t length, ZSTD_overlap_e const ovtype)
+{
+    ptrdiff_t diff = (BYTE*)dst - (const BYTE*)src;
+    const BYTE* ip = (const BYTE*)src;
+    BYTE* op = (BYTE*)dst;
+    BYTE* const oend = op + length;
+
+    if (ovtype == ZSTD_overlap_src_before_dst && diff < WILDCOPY_VECLEN) {
+        /* Handle short offset copies. */
+        do {
+            COPY8(op, ip);
+        } while (op < oend);
+    } else {
+        assert(diff >= WILDCOPY_VECLEN || diff <= -WILDCOPY_VECLEN);
+        /* Separate out the first COPY16() call because the copy length is
+         * almost certain to be short, so the branches have different
+         * probabilities. Since it is almost certain to be short, only do
+         * one COPY16() in the first call. Then, do two calls per loop since
+         * at that point it is more likely to have a high trip count.
+         */
+        ZSTD_copy16(op, ip);
+        if (16 >= length) return;
+        op += 16;
+        ip += 16;
+        do {
+            COPY16(op, ip);
+            COPY16(op, ip);
+        }
+        while (op < oend);
+    }
+}
+
+MEM_STATIC size_t ZSTD_limitCopy(void* dst, size_t dstCapacity, const void* src, size_t srcSize)
+{
+    size_t const length = MIN(dstCapacity, srcSize);
+    if (length > 0) {
+        ZSTD_memcpy(dst, src, length);
+    }
+    return length;
+}
+
+/* define "workspace is too large" as this number of times larger than needed */
+#define ZSTD_WORKSPACETOOLARGE_FACTOR 3
+
+/* when workspace is continuously too large
+ * during at least this number of times,
+ * context's memory usage is considered wasteful,
+ * because it's sized to handle a worst case scenario which rarely happens.
+ * In which case, resize it down to free some memory */
+#define ZSTD_WORKSPACETOOLARGE_MAXDURATION 128
+
+/* Controls whether the input/output buffer is buffered or stable. */
+typedef enum {
+    ZSTD_bm_buffered = 0,  /* Buffer the input/output */
+    ZSTD_bm_stable = 1     /* ZSTD_inBuffer/ZSTD_outBuffer is stable */
+} ZSTD_bufferMode_e;
+
+
+/*-*******************************************
+*  Private declarations
+*********************************************/
+
+/**
+ * Contains the compressed frame size and an upper-bound for the decompressed frame size.
+ * Note: before using `compressedSize`, check for errors using ZSTD_isError().
+ *       similarly, before using `decompressedBound`, check for errors using:
+ *          `decompressedBound != ZSTD_CONTENTSIZE_ERROR`
+ */
+typedef struct {
+    size_t nbBlocks;
+    size_t compressedSize;
+    unsigned long long decompressedBound;
+} ZSTD_frameSizeInfo;   /* decompress & legacy */
+
+/* ZSTD_invalidateRepCodes() :
+ * ensures next compression will not use repcodes from previous block.
+ * Note : only works with regular variant;
+ *        do not use with extDict variant ! */
+void ZSTD_invalidateRepCodes(ZSTD_CCtx* cctx);   /* zstdmt, adaptive_compression (shouldn't get this definition from here) */
+
+
+typedef struct {
+    blockType_e blockType;
+    U32 lastBlock;
+    U32 origSize;
+} blockProperties_t;   /* declared here for decompress and fullbench */
+
+/*! ZSTD_getcBlockSize() :
+ *  Provides the size of compressed block from block header `src` */
+/*  Used by: decompress, fullbench */
+size_t ZSTD_getcBlockSize(const void* src, size_t srcSize,
+                          blockProperties_t* bpPtr);
+
+/*! ZSTD_decodeSeqHeaders() :
+ *  decode sequence header from src */
+/*  Used by: zstd_decompress_block, fullbench */
+size_t ZSTD_decodeSeqHeaders(ZSTD_DCtx* dctx, int* nbSeqPtr,
+                       const void* src, size_t srcSize);
+
+/**
+ * @returns true iff the CPU supports dynamic BMI2 dispatch.
+ */
+MEM_STATIC int ZSTD_cpuSupportsBmi2(void)
+{
+    ZSTD_cpuid_t cpuid = ZSTD_cpuid();
+    return ZSTD_cpuid_bmi1(cpuid) && ZSTD_cpuid_bmi2(cpuid);
+}
+
+#endif   /* ZSTD_CCOMMON_H_MODULE */
diff --git a/src/commonlib/bsd/zstd/common/zstd_trace.h b/src/commonlib/bsd/zstd/common/zstd_trace.h
new file mode 100644
index 0000000000..dc08bd4cb6
--- /dev/null
+++ b/src/commonlib/bsd/zstd/common/zstd_trace.h
@@ -0,0 +1,158 @@
+/* SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0-only */
+
+/*
+ * Copyright (c) Meta Platforms, Inc. and affiliates.
+ * All rights reserved.
+ *
+ * This source code is licensed under both the BSD-style license (found in the
+ * LICENSE file in the root directory of this source tree) and the GPLv2 (found
+ * in the COPYING file in the root directory of this source tree).
+ * You may select, at your option, one of the above-listed licenses.
+ */
+
+#ifndef ZSTD_TRACE_H
+#define ZSTD_TRACE_H
+
+#include <stddef.h>
+
+/* weak symbol support
+ * For now, enable conservatively:
+ * - Only GNUC
+ * - Only ELF
+ * - Only x86-64, i386, aarch64 and risc-v.
+ * Also, explicitly disable on platforms known not to work so they aren't
+ * forgotten in the future.
+ */
+#if !defined(ZSTD_HAVE_WEAK_SYMBOLS) && \
+    defined(__GNUC__) && defined(__ELF__) && \
+    (defined(__x86_64__) || defined(_M_X64) || defined(__i386__) || \
+     defined(_M_IX86) || defined(__aarch64__) || defined(__riscv)) && \
+    !defined(__APPLE__) && !defined(_WIN32) && !defined(__MINGW32__) && \
+    !defined(__CYGWIN__) && !defined(_AIX)
+#  define ZSTD_HAVE_WEAK_SYMBOLS 1
+#else
+#  define ZSTD_HAVE_WEAK_SYMBOLS 0
+#endif
+#if ZSTD_HAVE_WEAK_SYMBOLS
+#  define ZSTD_WEAK_ATTR __attribute__((__weak__))
+#else
+#  define ZSTD_WEAK_ATTR
+#endif
+
+/* Only enable tracing when weak symbols are available. */
+#ifndef ZSTD_TRACE
+#  define ZSTD_TRACE ZSTD_HAVE_WEAK_SYMBOLS
+#endif
+
+#if ZSTD_TRACE
+
+struct ZSTD_CCtx_s;
+struct ZSTD_DCtx_s;
+struct ZSTD_CCtx_params_s;
+
+typedef struct {
+    /**
+     * ZSTD_VERSION_NUMBER
+     *
+     * This is guaranteed to be the first member of ZSTD_trace.
+     * Otherwise, this struct is not stable between versions. If
+     * the version number does not match your expectation, you
+     * should not interpret the rest of the struct.
+     */
+    unsigned version;
+    /**
+     * Non-zero if streaming (de)compression is used.
+     */
+    int streaming;
+    /**
+     * The dictionary ID.
+     */
+    unsigned dictionaryID;
+    /**
+     * Is the dictionary cold?
+     * Only set on decompression.
+     */
+    int dictionaryIsCold;
+    /**
+     * The dictionary size or zero if no dictionary.
+     */
+    size_t dictionarySize;
+    /**
+     * The uncompressed size of the data.
+     */
+    size_t uncompressedSize;
+    /**
+     * The compressed size of the data.
+     */
+    size_t compressedSize;
+    /**
+     * The fully resolved CCtx parameters (NULL on decompression).
+     */
+    struct ZSTD_CCtx_params_s const* params;
+    /**
+     * The ZSTD_CCtx pointer (NULL on decompression).
+     */
+    struct ZSTD_CCtx_s const* cctx;
+    /**
+     * The ZSTD_DCtx pointer (NULL on compression).
+     */
+    struct ZSTD_DCtx_s const* dctx;
+} ZSTD_Trace;
+
+/**
+ * A tracing context. It must be 0 when tracing is disabled.
+ * Otherwise, any non-zero value returned by a tracing begin()
+ * function is presented to any subsequent calls to end().
+ *
+ * Any non-zero value is treated as tracing is enabled and not
+ * interpreted by the library.
+ *
+ * Two possible uses are:
+ * * A timestamp for when the begin() function was called.
+ * * A unique key identifying the (de)compression, like the
+ *   address of the [dc]ctx pointer if you need to track
+ *   more information than just a timestamp.
+ */
+typedef unsigned long long ZSTD_TraceCtx;
+
+/**
+ * Trace the beginning of a compression call.
+ * @param cctx The dctx pointer for the compression.
+ *             It can be used as a key to map begin() to end().
+ * @returns Non-zero if tracing is enabled. The return value is
+ *          passed to ZSTD_trace_compress_end().
+ */
+ZSTD_WEAK_ATTR ZSTD_TraceCtx ZSTD_trace_compress_begin(
+    struct ZSTD_CCtx_s const* cctx);
+
+/**
+ * Trace the end of a compression call.
+ * @param ctx The return value of ZSTD_trace_compress_begin().
+ * @param trace The zstd tracing info.
+ */
+ZSTD_WEAK_ATTR void ZSTD_trace_compress_end(
+    ZSTD_TraceCtx ctx,
+    ZSTD_Trace const* trace);
+
+/**
+ * Trace the beginning of a decompression call.
+ * @param dctx The dctx pointer for the decompression.
+ *             It can be used as a key to map begin() to end().
+ * @returns Non-zero if tracing is enabled. The return value is
+ *          passed to ZSTD_trace_compress_end().
+ */
+ZSTD_WEAK_ATTR ZSTD_TraceCtx ZSTD_trace_decompress_begin(
+    struct ZSTD_DCtx_s const* dctx);
+
+/**
+ * Trace the end of a decompression call.
+ * @param ctx The return value of ZSTD_trace_decompress_begin().
+ * @param trace The zstd tracing info.
+ */
+ZSTD_WEAK_ATTR void ZSTD_trace_decompress_end(
+    ZSTD_TraceCtx ctx,
+    ZSTD_Trace const* trace);
+
+#endif /* ZSTD_TRACE */
+
+#endif /* ZSTD_TRACE_H */
diff --git a/src/commonlib/bsd/zstd/common/zstd_xxhash.h b/src/commonlib/bsd/zstd/common/zstd_xxhash.h
new file mode 100644
index 0000000000..4e3f2480d9
--- /dev/null
+++ b/src/commonlib/bsd/zstd/common/zstd_xxhash.h
@@ -0,0 +1,20 @@
+/* SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0-only */
+
+#ifndef ZSTD_XXHASH_COMMON
+#define ZSTD_XXHASH_COMMON
+
+#include <commonlib/bsd/xxhash.h>
+
+typedef struct xxh64_state XXH64_state_t;
+#define XXH64_update xxh64_update
+#define XXH64_reset  xxh64_reset
+#define XXH64_digest xxh64_digest
+#define XXH64 xxh64
+
+typedef struct xxh32_state XXH32_state_t;
+#define XXH32_update xxh32_update
+#define XXH32_reset  xxh32_reset
+#define XXH32_digest xxh32_digest
+#define XXH32 xxh32
+
+#endif /* ZSTD_XXHASH_COMMON */
diff --git a/src/commonlib/bsd/zstd/compress/clevels.h b/src/commonlib/bsd/zstd/compress/clevels.h
new file mode 100644
index 0000000000..8ebf1be282
--- /dev/null
+++ b/src/commonlib/bsd/zstd/compress/clevels.h
@@ -0,0 +1,136 @@
+/* SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0-only */
+
+/*
+ * Copyright (c) Meta Platforms, Inc. and affiliates.
+ * All rights reserved.
+ *
+ * This source code is licensed under both the BSD-style license (found in the
+ * LICENSE file in the root directory of this source tree) and the GPLv2 (found
+ * in the COPYING file in the root directory of this source tree).
+ * You may select, at your option, one of the above-listed licenses.
+ */
+
+#ifndef ZSTD_CLEVELS_H
+#define ZSTD_CLEVELS_H
+
+#define ZSTD_STATIC_LINKING_ONLY  /* ZSTD_compressionParameters  */
+#include "../zstd.h"
+
+/*-=====  Pre-defined compression levels  =====-*/
+
+#define ZSTD_MAX_CLEVEL     22
+
+#ifdef __GNUC__
+__attribute__((__unused__))
+#endif
+
+static const ZSTD_compressionParameters ZSTD_defaultCParameters[4][ZSTD_MAX_CLEVEL+1] = {
+{   /* "default" - for any srcSize > 256 KB */
+    /* W,  C,  H,  S,  L, TL, strat */
+    { 19, 12, 13,  1,  6,  1, ZSTD_fast    },  /* base for negative levels */
+    { 19, 13, 14,  1,  7,  0, ZSTD_fast    },  /* level  1 */
+    { 20, 15, 16,  1,  6,  0, ZSTD_fast    },  /* level  2 */
+    { 21, 16, 17,  1,  5,  0, ZSTD_dfast   },  /* level  3 */
+    { 21, 18, 18,  1,  5,  0, ZSTD_dfast   },  /* level  4 */
+    { 21, 18, 19,  3,  5,  2, ZSTD_greedy  },  /* level  5 */
+    { 21, 18, 19,  3,  5,  4, ZSTD_lazy    },  /* level  6 */
+    { 21, 19, 20,  4,  5,  8, ZSTD_lazy    },  /* level  7 */
+    { 21, 19, 20,  4,  5, 16, ZSTD_lazy2   },  /* level  8 */
+    { 22, 20, 21,  4,  5, 16, ZSTD_lazy2   },  /* level  9 */
+    { 22, 21, 22,  5,  5, 16, ZSTD_lazy2   },  /* level 10 */
+    { 22, 21, 22,  6,  5, 16, ZSTD_lazy2   },  /* level 11 */
+    { 22, 22, 23,  6,  5, 32, ZSTD_lazy2   },  /* level 12 */
+    { 22, 22, 22,  4,  5, 32, ZSTD_btlazy2 },  /* level 13 */
+    { 22, 22, 23,  5,  5, 32, ZSTD_btlazy2 },  /* level 14 */
+    { 22, 23, 23,  6,  5, 32, ZSTD_btlazy2 },  /* level 15 */
+    { 22, 22, 22,  5,  5, 48, ZSTD_btopt   },  /* level 16 */
+    { 23, 23, 22,  5,  4, 64, ZSTD_btopt   },  /* level 17 */
+    { 23, 23, 22,  6,  3, 64, ZSTD_btultra },  /* level 18 */
+    { 23, 24, 22,  7,  3,256, ZSTD_btultra2},  /* level 19 */
+    { 25, 25, 23,  7,  3,256, ZSTD_btultra2},  /* level 20 */
+    { 26, 26, 24,  7,  3,512, ZSTD_btultra2},  /* level 21 */
+    { 27, 27, 25,  9,  3,999, ZSTD_btultra2},  /* level 22 */
+},
+{   /* for srcSize <= 256 KB */
+    /* W,  C,  H,  S,  L,  T, strat */
+    { 18, 12, 13,  1,  5,  1, ZSTD_fast    },  /* base for negative levels */
+    { 18, 13, 14,  1,  6,  0, ZSTD_fast    },  /* level  1 */
+    { 18, 14, 14,  1,  5,  0, ZSTD_dfast   },  /* level  2 */
+    { 18, 16, 16,  1,  4,  0, ZSTD_dfast   },  /* level  3 */
+    { 18, 16, 17,  3,  5,  2, ZSTD_greedy  },  /* level  4.*/
+    { 18, 17, 18,  5,  5,  2, ZSTD_greedy  },  /* level  5.*/
+    { 18, 18, 19,  3,  5,  4, ZSTD_lazy    },  /* level  6.*/
+    { 18, 18, 19,  4,  4,  4, ZSTD_lazy    },  /* level  7 */
+    { 18, 18, 19,  4,  4,  8, ZSTD_lazy2   },  /* level  8 */
+    { 18, 18, 19,  5,  4,  8, ZSTD_lazy2   },  /* level  9 */
+    { 18, 18, 19,  6,  4,  8, ZSTD_lazy2   },  /* level 10 */
+    { 18, 18, 19,  5,  4, 12, ZSTD_btlazy2 },  /* level 11.*/
+    { 18, 19, 19,  7,  4, 12, ZSTD_btlazy2 },  /* level 12.*/
+    { 18, 18, 19,  4,  4, 16, ZSTD_btopt   },  /* level 13 */
+    { 18, 18, 19,  4,  3, 32, ZSTD_btopt   },  /* level 14.*/
+    { 18, 18, 19,  6,  3,128, ZSTD_btopt   },  /* level 15.*/
+    { 18, 19, 19,  6,  3,128, ZSTD_btultra },  /* level 16.*/
+    { 18, 19, 19,  8,  3,256, ZSTD_btultra },  /* level 17.*/
+    { 18, 19, 19,  6,  3,128, ZSTD_btultra2},  /* level 18.*/
+    { 18, 19, 19,  8,  3,256, ZSTD_btultra2},  /* level 19.*/
+    { 18, 19, 19, 10,  3,512, ZSTD_btultra2},  /* level 20.*/
+    { 18, 19, 19, 12,  3,512, ZSTD_btultra2},  /* level 21.*/
+    { 18, 19, 19, 13,  3,999, ZSTD_btultra2},  /* level 22.*/
+},
+{   /* for srcSize <= 128 KB */
+    /* W,  C,  H,  S,  L,  T, strat */
+    { 17, 12, 12,  1,  5,  1, ZSTD_fast    },  /* base for negative levels */
+    { 17, 12, 13,  1,  6,  0, ZSTD_fast    },  /* level  1 */
+    { 17, 13, 15,  1,  5,  0, ZSTD_fast    },  /* level  2 */
+    { 17, 15, 16,  2,  5,  0, ZSTD_dfast   },  /* level  3 */
+    { 17, 17, 17,  2,  4,  0, ZSTD_dfast   },  /* level  4 */
+    { 17, 16, 17,  3,  4,  2, ZSTD_greedy  },  /* level  5 */
+    { 17, 16, 17,  3,  4,  4, ZSTD_lazy    },  /* level  6 */
+    { 17, 16, 17,  3,  4,  8, ZSTD_lazy2   },  /* level  7 */
+    { 17, 16, 17,  4,  4,  8, ZSTD_lazy2   },  /* level  8 */
+    { 17, 16, 17,  5,  4,  8, ZSTD_lazy2   },  /* level  9 */
+    { 17, 16, 17,  6,  4,  8, ZSTD_lazy2   },  /* level 10 */
+    { 17, 17, 17,  5,  4,  8, ZSTD_btlazy2 },  /* level 11 */
+    { 17, 18, 17,  7,  4, 12, ZSTD_btlazy2 },  /* level 12 */
+    { 17, 18, 17,  3,  4, 12, ZSTD_btopt   },  /* level 13.*/
+    { 17, 18, 17,  4,  3, 32, ZSTD_btopt   },  /* level 14.*/
+    { 17, 18, 17,  6,  3,256, ZSTD_btopt   },  /* level 15.*/
+    { 17, 18, 17,  6,  3,128, ZSTD_btultra },  /* level 16.*/
+    { 17, 18, 17,  8,  3,256, ZSTD_btultra },  /* level 17.*/
+    { 17, 18, 17, 10,  3,512, ZSTD_btultra },  /* level 18.*/
+    { 17, 18, 17,  5,  3,256, ZSTD_btultra2},  /* level 19.*/
+    { 17, 18, 17,  7,  3,512, ZSTD_btultra2},  /* level 20.*/
+    { 17, 18, 17,  9,  3,512, ZSTD_btultra2},  /* level 21.*/
+    { 17, 18, 17, 11,  3,999, ZSTD_btultra2},  /* level 22.*/
+},
+{   /* for srcSize <= 16 KB */
+    /* W,  C,  H,  S,  L,  T, strat */
+    { 14, 12, 13,  1,  5,  1, ZSTD_fast    },  /* base for negative levels */
+    { 14, 14, 15,  1,  5,  0, ZSTD_fast    },  /* level  1 */
+    { 14, 14, 15,  1,  4,  0, ZSTD_fast    },  /* level  2 */
+    { 14, 14, 15,  2,  4,  0, ZSTD_dfast   },  /* level  3 */
+    { 14, 14, 14,  4,  4,  2, ZSTD_greedy  },  /* level  4 */
+    { 14, 14, 14,  3,  4,  4, ZSTD_lazy    },  /* level  5.*/
+    { 14, 14, 14,  4,  4,  8, ZSTD_lazy2   },  /* level  6 */
+    { 14, 14, 14,  6,  4,  8, ZSTD_lazy2   },  /* level  7 */
+    { 14, 14, 14,  8,  4,  8, ZSTD_lazy2   },  /* level  8.*/
+    { 14, 15, 14,  5,  4,  8, ZSTD_btlazy2 },  /* level  9.*/
+    { 14, 15, 14,  9,  4,  8, ZSTD_btlazy2 },  /* level 10.*/
+    { 14, 15, 14,  3,  4, 12, ZSTD_btopt   },  /* level 11.*/
+    { 14, 15, 14,  4,  3, 24, ZSTD_btopt   },  /* level 12.*/
+    { 14, 15, 14,  5,  3, 32, ZSTD_btultra },  /* level 13.*/
+    { 14, 15, 15,  6,  3, 64, ZSTD_btultra },  /* level 14.*/
+    { 14, 15, 15,  7,  3,256, ZSTD_btultra },  /* level 15.*/
+    { 14, 15, 15,  5,  3, 48, ZSTD_btultra2},  /* level 16.*/
+    { 14, 15, 15,  6,  3,128, ZSTD_btultra2},  /* level 17.*/
+    { 14, 15, 15,  7,  3,256, ZSTD_btultra2},  /* level 18.*/
+    { 14, 15, 15,  8,  3,256, ZSTD_btultra2},  /* level 19.*/
+    { 14, 15, 15,  8,  3,512, ZSTD_btultra2},  /* level 20.*/
+    { 14, 15, 15,  9,  3,512, ZSTD_btultra2},  /* level 21.*/
+    { 14, 15, 15, 10,  3,999, ZSTD_btultra2},  /* level 22.*/
+},
+};
+
+
+
+#endif  /* ZSTD_CLEVELS_H */
diff --git a/src/commonlib/bsd/zstd/compress/fse_compress.c b/src/commonlib/bsd/zstd/compress/fse_compress.c
new file mode 100644
index 0000000000..7ef32108ef
--- /dev/null
+++ b/src/commonlib/bsd/zstd/compress/fse_compress.c
@@ -0,0 +1,627 @@
+/* SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0-only */
+
+/* ******************************************************************
+ * FSE : Finite State Entropy encoder
+ * Copyright (c) Meta Platforms, Inc. and affiliates.
+ *
+ *  You can contact the author at :
+ *  - FSE source repository : https://github.com/Cyan4973/FiniteStateEntropy
+ *  - Public forum : https://groups.google.com/forum/#!forum/lz4c
+ *
+ * This source code is licensed under both the BSD-style license (found in the
+ * LICENSE file in the root directory of this source tree) and the GPLv2 (found
+ * in the COPYING file in the root directory of this source tree).
+ * You may select, at your option, one of the above-listed licenses.
+****************************************************************** */
+
+/* **************************************************************
+*  Includes
+****************************************************************/
+#include "../common/zstd_compiler.h"
+#include "../common/mem.h"        /* U32, U16, etc. */
+#include "../common/debug.h"      /* assert, DEBUGLOG */
+#include "hist.h"       /* HIST_count_wksp */
+#include "../common/bitstream.h"
+#define FSE_STATIC_LINKING_ONLY
+#include "../common/fse.h"
+#include "../common/error_private.h"
+#define ZSTD_DEPS_NEED_MALLOC
+#define ZSTD_DEPS_NEED_MATH64
+#include "../common/zstd_deps.h"  /* ZSTD_memset */
+#include "../common/zstd_bits.h" /* ZSTD_highbit32 */
+
+
+/* **************************************************************
+*  Error Management
+****************************************************************/
+#define FSE_isError ERR_isError
+
+
+/* **************************************************************
+*  Templates
+****************************************************************/
+/*
+  designed to be included
+  for type-specific functions (template emulation in C)
+  Objective is to write these functions only once, for improved maintenance
+*/
+
+/* safety checks */
+#ifndef FSE_FUNCTION_EXTENSION
+#  error "FSE_FUNCTION_EXTENSION must be defined"
+#endif
+#ifndef FSE_FUNCTION_TYPE
+#  error "FSE_FUNCTION_TYPE must be defined"
+#endif
+
+/* Function names */
+#define FSE_CAT(X,Y) X##Y
+#define FSE_FUNCTION_NAME(X,Y) FSE_CAT(X,Y)
+#define FSE_TYPE_NAME(X,Y) FSE_CAT(X,Y)
+
+
+/* Function templates */
+
+/* FSE_buildCTable_wksp() :
+ * Same as FSE_buildCTable(), but using an externally allocated scratch buffer (`workSpace`).
+ * wkspSize should be sized to handle worst case situation, which is `1<<max_tableLog * sizeof(FSE_FUNCTION_TYPE)`
+ * workSpace must also be properly aligned with FSE_FUNCTION_TYPE requirements
+ */
+size_t FSE_buildCTable_wksp(FSE_CTable* ct,
+                      const short* normalizedCounter, unsigned maxSymbolValue, unsigned tableLog,
+                            void* workSpace, size_t wkspSize)
+{
+    U32 const tableSize = 1 << tableLog;
+    U32 const tableMask = tableSize - 1;
+    void* const ptr = ct;
+    U16* const tableU16 = ( (U16*) ptr) + 2;
+    void* const FSCT = ((U32*)ptr) + 1 /* header */ + (tableLog ? tableSize>>1 : 1) ;
+    FSE_symbolCompressionTransform* const symbolTT = (FSE_symbolCompressionTransform*) (FSCT);
+    U32 const step = FSE_TABLESTEP(tableSize);
+    U32 const maxSV1 = maxSymbolValue+1;
+
+    U16* cumul = (U16*)workSpace;   /* size = maxSV1 */
+    FSE_FUNCTION_TYPE* const tableSymbol = (FSE_FUNCTION_TYPE*)(cumul + (maxSV1+1));  /* size = tableSize */
+
+    U32 highThreshold = tableSize-1;
+
+    assert(((size_t)workSpace & 1) == 0);  /* Must be 2 bytes-aligned */
+    if (FSE_BUILD_CTABLE_WORKSPACE_SIZE(maxSymbolValue, tableLog) > wkspSize) return ERROR(tableLog_tooLarge);
+    /* CTable header */
+    tableU16[-2] = (U16) tableLog;
+    tableU16[-1] = (U16) maxSymbolValue;
+    assert(tableLog < 16);   /* required for threshold strategy to work */
+
+    /* For explanations on how to distribute symbol values over the table :
+     * https://fastcompression.blogspot.fr/2014/02/fse-distributing-symbol-values.html */
+
+     #ifdef __clang_analyzer__
+     ZSTD_memset(tableSymbol, 0, sizeof(*tableSymbol) * tableSize);   /* useless initialization, just to keep scan-build happy */
+     #endif
+
+    /* symbol start positions */
+    {   U32 u;
+        cumul[0] = 0;
+        for (u=1; u <= maxSV1; u++) {
+            if (normalizedCounter[u-1]==-1) {  /* Low proba symbol */
+                cumul[u] = cumul[u-1] + 1;
+                tableSymbol[highThreshold--] = (FSE_FUNCTION_TYPE)(u-1);
+            } else {
+                assert(normalizedCounter[u-1] >= 0);
+                cumul[u] = cumul[u-1] + (U16)normalizedCounter[u-1];
+                assert(cumul[u] >= cumul[u-1]);  /* no overflow */
+        }   }
+        cumul[maxSV1] = (U16)(tableSize+1);
+    }
+
+    /* Spread symbols */
+    if (highThreshold == tableSize - 1) {
+        /* Case for no low prob count symbols. Lay down 8 bytes at a time
+         * to reduce branch misses since we are operating on a small block
+         */
+        BYTE* const spread = tableSymbol + tableSize; /* size = tableSize + 8 (may write beyond tableSize) */
+        {   U64 const add = 0x0101010101010101ull;
+            size_t pos = 0;
+            U64 sv = 0;
+            U32 s;
+            for (s=0; s<maxSV1; ++s, sv += add) {
+                int i;
+                int const n = normalizedCounter[s];
+                MEM_write64(spread + pos, sv);
+                for (i = 8; i < n; i += 8) {
+                    MEM_write64(spread + pos + i, sv);
+                }
+                assert(n>=0);
+                pos += (size_t)n;
+            }
+        }
+        /* Spread symbols across the table. Lack of lowprob symbols means that
+         * we don't need variable sized inner loop, so we can unroll the loop and
+         * reduce branch misses.
+         */
+        {   size_t position = 0;
+            size_t s;
+            size_t const unroll = 2; /* Experimentally determined optimal unroll */
+            assert(tableSize % unroll == 0); /* FSE_MIN_TABLELOG is 5 */
+            for (s = 0; s < (size_t)tableSize; s += unroll) {
+                size_t u;
+                for (u = 0; u < unroll; ++u) {
+                    size_t const uPosition = (position + (u * step)) & tableMask;
+                    tableSymbol[uPosition] = spread[s + u];
+                }
+                position = (position + (unroll * step)) & tableMask;
+            }
+            assert(position == 0);   /* Must have initialized all positions */
+        }
+    } else {
+        U32 position = 0;
+        U32 symbol;
+        for (symbol=0; symbol<maxSV1; symbol++) {
+            int nbOccurrences;
+            int const freq = normalizedCounter[symbol];
+            for (nbOccurrences=0; nbOccurrences<freq; nbOccurrences++) {
+                tableSymbol[position] = (FSE_FUNCTION_TYPE)symbol;
+                position = (position + step) & tableMask;
+                while (position > highThreshold)
+                    position = (position + step) & tableMask;   /* Low proba area */
+        }   }
+        assert(position==0);  /* Must have initialized all positions */
+    }
+
+    /* Build table */
+    {   U32 u; for (u=0; u<tableSize; u++) {
+        FSE_FUNCTION_TYPE s = tableSymbol[u];   /* note : static analyzer may not understand tableSymbol is properly initialized */
+        tableU16[cumul[s]++] = (U16) (tableSize+u);   /* TableU16 : sorted by symbol order; gives next state value */
+    }   }
+
+    /* Build Symbol Transformation Table */
+    {   unsigned total = 0;
+        unsigned s;
+        for (s=0; s<=maxSymbolValue; s++) {
+            switch (normalizedCounter[s])
+            {
+            case  0:
+                /* filling nonetheless, for compatibility with FSE_getMaxNbBits() */
+                symbolTT[s].deltaNbBits = ((tableLog+1) << 16) - (1<<tableLog);
+                break;
+
+            case -1:
+            case  1:
+                symbolTT[s].deltaNbBits = (tableLog << 16) - (1<<tableLog);
+                assert(total <= INT_MAX);
+                symbolTT[s].deltaFindState = (int)(total - 1);
+                total ++;
+                break;
+            default :
+                assert(normalizedCounter[s] > 1);
+                {   U32 const maxBitsOut = tableLog - ZSTD_highbit32 ((U32)normalizedCounter[s]-1);
+                    U32 const minStatePlus = (U32)normalizedCounter[s] << maxBitsOut;
+                    symbolTT[s].deltaNbBits = (maxBitsOut << 16) - minStatePlus;
+                    symbolTT[s].deltaFindState = (int)(total - (unsigned)normalizedCounter[s]);
+                    total +=  (unsigned)normalizedCounter[s];
+    }   }   }   }
+
+#if 0  /* debug : symbol costs */
+    DEBUGLOG(5, "\n --- table statistics : ");
+    {   U32 symbol;
+        for (symbol=0; symbol<=maxSymbolValue; symbol++) {
+            DEBUGLOG(5, "%3u: w=%3i,   maxBits=%u, fracBits=%.2f",
+                symbol, normalizedCounter[symbol],
+                FSE_getMaxNbBits(symbolTT, symbol),
+                (double)FSE_bitCost(symbolTT, tableLog, symbol, 8) / 256);
+    }   }
+#endif
+
+    return 0;
+}
+
+
+
+#ifndef FSE_COMMONDEFS_ONLY
+
+/*-**************************************************************
+*  FSE NCount encoding
+****************************************************************/
+size_t FSE_NCountWriteBound(unsigned maxSymbolValue, unsigned tableLog)
+{
+    size_t const maxHeaderSize = (((maxSymbolValue+1) * tableLog
+                                   + 4 /* bitCount initialized at 4 */
+                                   + 2 /* first two symbols may use one additional bit each */) / 8)
+                                   + 1 /* round up to whole nb bytes */
+                                   + 2 /* additional two bytes for bitstream flush */;
+    return maxSymbolValue ? maxHeaderSize : FSE_NCOUNTBOUND;  /* maxSymbolValue==0 ? use default */
+}
+
+static size_t
+FSE_writeNCount_generic (void* header, size_t headerBufferSize,
+                   const short* normalizedCounter, unsigned maxSymbolValue, unsigned tableLog,
+                         unsigned writeIsSafe)
+{
+    BYTE* const ostart = (BYTE*) header;
+    BYTE* out = ostart;
+    BYTE* const oend = ostart + headerBufferSize;
+    int nbBits;
+    const int tableSize = 1 << tableLog;
+    int remaining;
+    int threshold;
+    U32 bitStream = 0;
+    int bitCount = 0;
+    unsigned symbol = 0;
+    unsigned const alphabetSize = maxSymbolValue + 1;
+    int previousIs0 = 0;
+
+    /* Table Size */
+    bitStream += (tableLog-FSE_MIN_TABLELOG) << bitCount;
+    bitCount  += 4;
+
+    /* Init */
+    remaining = tableSize+1;   /* +1 for extra accuracy */
+    threshold = tableSize;
+    nbBits = (int)tableLog+1;
+
+    while ((symbol < alphabetSize) && (remaining>1)) {  /* stops at 1 */
+        if (previousIs0) {
+            unsigned start = symbol;
+            while ((symbol < alphabetSize) && !normalizedCounter[symbol]) symbol++;
+            if (symbol == alphabetSize) break;   /* incorrect distribution */
+            while (symbol >= start+24) {
+                start+=24;
+                bitStream += 0xFFFFU << bitCount;
+                if ((!writeIsSafe) && (out > oend-2))
+                    return ERROR(dstSize_tooSmall);   /* Buffer overflow */
+                out[0] = (BYTE) bitStream;
+                out[1] = (BYTE)(bitStream>>8);
+                out+=2;
+                bitStream>>=16;
+            }
+            while (symbol >= start+3) {
+                start+=3;
+                bitStream += 3U << bitCount;
+                bitCount += 2;
+            }
+            bitStream += (symbol-start) << bitCount;
+            bitCount += 2;
+            if (bitCount>16) {
+                if ((!writeIsSafe) && (out > oend - 2))
+                    return ERROR(dstSize_tooSmall);   /* Buffer overflow */
+                out[0] = (BYTE)bitStream;
+                out[1] = (BYTE)(bitStream>>8);
+                out += 2;
+                bitStream >>= 16;
+                bitCount -= 16;
+        }   }
+        {   int count = normalizedCounter[symbol++];
+            int const max = (2*threshold-1) - remaining;
+            remaining -= count < 0 ? -count : count;
+            count++;   /* +1 for extra accuracy */
+            if (count>=threshold)
+                count += max;   /* [0..max[ [max..threshold[ (...) [threshold+max 2*threshold[ */
+            bitStream += (U32)count << bitCount;
+            bitCount  += nbBits;
+            bitCount  -= (count<max);
+            previousIs0  = (count==1);
+            if (remaining<1) return ERROR(GENERIC);
+            while (remaining<threshold) { nbBits--; threshold>>=1; }
+        }
+        if (bitCount>16) {
+            if ((!writeIsSafe) && (out > oend - 2))
+                return ERROR(dstSize_tooSmall);   /* Buffer overflow */
+            out[0] = (BYTE)bitStream;
+            out[1] = (BYTE)(bitStream>>8);
+            out += 2;
+            bitStream >>= 16;
+            bitCount -= 16;
+    }   }
+
+    if (remaining != 1)
+        return ERROR(GENERIC);  /* incorrect normalized distribution */
+    assert(symbol <= alphabetSize);
+
+    /* flush remaining bitStream */
+    if ((!writeIsSafe) && (out > oend - 2))
+        return ERROR(dstSize_tooSmall);   /* Buffer overflow */
+    out[0] = (BYTE)bitStream;
+    out[1] = (BYTE)(bitStream>>8);
+    out+= (bitCount+7) /8;
+
+    assert(out >= ostart);
+    return (size_t)(out-ostart);
+}
+
+
+size_t FSE_writeNCount (void* buffer, size_t bufferSize,
+                  const short* normalizedCounter, unsigned maxSymbolValue, unsigned tableLog)
+{
+    if (tableLog > FSE_MAX_TABLELOG) return ERROR(tableLog_tooLarge);   /* Unsupported */
+    if (tableLog < FSE_MIN_TABLELOG) return ERROR(GENERIC);   /* Unsupported */
+
+    if (bufferSize < FSE_NCountWriteBound(maxSymbolValue, tableLog))
+        return FSE_writeNCount_generic(buffer, bufferSize, normalizedCounter, maxSymbolValue, tableLog, 0);
+
+    return FSE_writeNCount_generic(buffer, bufferSize, normalizedCounter, maxSymbolValue, tableLog, 1 /* write in buffer is safe */);
+}
+
+
+/*-**************************************************************
+*  FSE Compression Code
+****************************************************************/
+
+/* provides the minimum logSize to safely represent a distribution */
+static unsigned FSE_minTableLog(size_t srcSize, unsigned maxSymbolValue)
+{
+    U32 minBitsSrc = ZSTD_highbit32((U32)(srcSize)) + 1;
+    U32 minBitsSymbols = ZSTD_highbit32(maxSymbolValue) + 2;
+    U32 minBits = minBitsSrc < minBitsSymbols ? minBitsSrc : minBitsSymbols;
+    assert(srcSize > 1); /* Not supported, RLE should be used instead */
+    return minBits;
+}
+
+unsigned FSE_optimalTableLog_internal(unsigned maxTableLog, size_t srcSize, unsigned maxSymbolValue, unsigned minus)
+{
+    U32 maxBitsSrc = ZSTD_highbit32((U32)(srcSize - 1)) - minus;
+    U32 tableLog = maxTableLog;
+    U32 minBits = FSE_minTableLog(srcSize, maxSymbolValue);
+    assert(srcSize > 1); /* Not supported, RLE should be used instead */
+    if (tableLog==0) tableLog = FSE_DEFAULT_TABLELOG;
+    if (maxBitsSrc < tableLog) tableLog = maxBitsSrc;   /* Accuracy can be reduced */
+    if (minBits > tableLog) tableLog = minBits;   /* Need a minimum to safely represent all symbol values */
+    if (tableLog < FSE_MIN_TABLELOG) tableLog = FSE_MIN_TABLELOG;
+    if (tableLog > FSE_MAX_TABLELOG) tableLog = FSE_MAX_TABLELOG;
+    return tableLog;
+}
+
+unsigned FSE_optimalTableLog(unsigned maxTableLog, size_t srcSize, unsigned maxSymbolValue)
+{
+    return FSE_optimalTableLog_internal(maxTableLog, srcSize, maxSymbolValue, 2);
+}
+
+/* Secondary normalization method.
+   To be used when primary method fails. */
+
+static size_t FSE_normalizeM2(short* norm, U32 tableLog, const unsigned* count, size_t total, U32 maxSymbolValue, short lowProbCount)
+{
+    short const NOT_YET_ASSIGNED = -2;
+    U32 s;
+    U32 distributed = 0;
+    U32 ToDistribute;
+
+    /* Init */
+    U32 const lowThreshold = (U32)(total >> tableLog);
+    U32 lowOne = (U32)((total * 3) >> (tableLog + 1));
+
+    for (s=0; s<=maxSymbolValue; s++) {
+        if (count[s] == 0) {
+            norm[s]=0;
+            continue;
+        }
+        if (count[s] <= lowThreshold) {
+            norm[s] = lowProbCount;
+            distributed++;
+            total -= count[s];
+            continue;
+        }
+        if (count[s] <= lowOne) {
+            norm[s] = 1;
+            distributed++;
+            total -= count[s];
+            continue;
+        }
+
+        norm[s]=NOT_YET_ASSIGNED;
+    }
+    ToDistribute = (1 << tableLog) - distributed;
+
+    if (ToDistribute == 0)
+        return 0;
+
+    if ((total / ToDistribute) > lowOne) {
+        /* risk of rounding to zero */
+        lowOne = (U32)((total * 3) / (ToDistribute * 2));
+        for (s=0; s<=maxSymbolValue; s++) {
+            if ((norm[s] == NOT_YET_ASSIGNED) && (count[s] <= lowOne)) {
+                norm[s] = 1;
+                distributed++;
+                total -= count[s];
+                continue;
+        }   }
+        ToDistribute = (1 << tableLog) - distributed;
+    }
+
+    if (distributed == maxSymbolValue+1) {
+        /* all values are pretty poor;
+           probably incompressible data (should have already been detected);
+           find max, then give all remaining points to max */
+        U32 maxV = 0, maxC = 0;
+        for (s=0; s<=maxSymbolValue; s++)
+            if (count[s] > maxC) { maxV=s; maxC=count[s]; }
+        norm[maxV] += (short)ToDistribute;
+        return 0;
+    }
+
+    if (total == 0) {
+        /* all of the symbols were low enough for the lowOne or lowThreshold */
+        for (s=0; ToDistribute > 0; s = (s+1)%(maxSymbolValue+1))
+            if (norm[s] > 0) { ToDistribute--; norm[s]++; }
+        return 0;
+    }
+
+    {   U64 const vStepLog = 62 - tableLog;
+        U64 const mid = (1ULL << (vStepLog-1)) - 1;
+        U64 const rStep = ZSTD_div64((((U64)1<<vStepLog) * ToDistribute) + mid, (U32)total);   /* scale on remaining */
+        U64 tmpTotal = mid;
+        for (s=0; s<=maxSymbolValue; s++) {
+            if (norm[s]==NOT_YET_ASSIGNED) {
+                U64 const end = tmpTotal + (count[s] * rStep);
+                U32 const sStart = (U32)(tmpTotal >> vStepLog);
+                U32 const sEnd = (U32)(end >> vStepLog);
+                U32 const weight = sEnd - sStart;
+                if (weight < 1)
+                    return ERROR(GENERIC);
+                norm[s] = (short)weight;
+                tmpTotal = end;
+    }   }   }
+
+    return 0;
+}
+
+size_t FSE_normalizeCount (short* normalizedCounter, unsigned tableLog,
+                           const unsigned* count, size_t total,
+                           unsigned maxSymbolValue, unsigned useLowProbCount)
+{
+    /* Sanity checks */
+    if (tableLog==0) tableLog = FSE_DEFAULT_TABLELOG;
+    if (tableLog < FSE_MIN_TABLELOG) return ERROR(GENERIC);   /* Unsupported size */
+    if (tableLog > FSE_MAX_TABLELOG) return ERROR(tableLog_tooLarge);   /* Unsupported size */
+    if (tableLog < FSE_minTableLog(total, maxSymbolValue)) return ERROR(GENERIC);   /* Too small tableLog, compression potentially impossible */
+
+    {   static U32 const rtbTable[] = {     0, 473195, 504333, 520860, 550000, 700000, 750000, 830000 };
+        short const lowProbCount = useLowProbCount ? -1 : 1;
+        U64 const scale = 62 - tableLog;
+        U64 const step = ZSTD_div64((U64)1<<62, (U32)total);   /* <== here, one division ! */
+        U64 const vStep = 1ULL<<(scale-20);
+        int stillToDistribute = 1<<tableLog;
+        unsigned s;
+        unsigned largest=0;
+        short largestP=0;
+        U32 lowThreshold = (U32)(total >> tableLog);
+
+        for (s=0; s<=maxSymbolValue; s++) {
+            if (count[s] == total) return 0;   /* rle special case */
+            if (count[s] == 0) { normalizedCounter[s]=0; continue; }
+            if (count[s] <= lowThreshold) {
+                normalizedCounter[s] = lowProbCount;
+                stillToDistribute--;
+            } else {
+                short proba = (short)((count[s]*step) >> scale);
+                if (proba<8) {
+                    U64 restToBeat = vStep * rtbTable[proba];
+                    proba += (count[s]*step) - ((U64)proba<<scale) > restToBeat;
+                }
+                if (proba > largestP) { largestP=proba; largest=s; }
+                normalizedCounter[s] = proba;
+                stillToDistribute -= proba;
+        }   }
+        if (-stillToDistribute >= (normalizedCounter[largest] >> 1)) {
+            /* corner case, need another normalization method */
+            size_t const errorCode = FSE_normalizeM2(normalizedCounter, tableLog, count, total, maxSymbolValue, lowProbCount);
+            if (FSE_isError(errorCode)) return errorCode;
+        }
+        else normalizedCounter[largest] += (short)stillToDistribute;
+    }
+
+#if 0
+    {   /* Print Table (debug) */
+        U32 s;
+        U32 nTotal = 0;
+        for (s=0; s<=maxSymbolValue; s++)
+            RAWLOG(2, "%3i: %4i \n", s, normalizedCounter[s]);
+        for (s=0; s<=maxSymbolValue; s++)
+            nTotal += abs(normalizedCounter[s]);
+        if (nTotal != (1U<<tableLog))
+            RAWLOG(2, "Warning !!! Total == %u != %u !!!", nTotal, 1U<<tableLog);
+        getchar();
+    }
+#endif
+
+    return tableLog;
+}
+
+/* fake FSE_CTable, for rle input (always same symbol) */
+size_t FSE_buildCTable_rle (FSE_CTable* ct, BYTE symbolValue)
+{
+    void* ptr = ct;
+    U16* tableU16 = ( (U16*) ptr) + 2;
+    void* FSCTptr = (U32*)ptr + 2;
+    FSE_symbolCompressionTransform* symbolTT = (FSE_symbolCompressionTransform*) FSCTptr;
+
+    /* header */
+    tableU16[-2] = (U16) 0;
+    tableU16[-1] = (U16) symbolValue;
+
+    /* Build table */
+    tableU16[0] = 0;
+    tableU16[1] = 0;   /* just in case */
+
+    /* Build Symbol Transformation Table */
+    symbolTT[symbolValue].deltaNbBits = 0;
+    symbolTT[symbolValue].deltaFindState = 0;
+
+    return 0;
+}
+
+
+static size_t FSE_compress_usingCTable_generic (void* dst, size_t dstSize,
+                           const void* src, size_t srcSize,
+                           const FSE_CTable* ct, const unsigned fast)
+{
+    const BYTE* const istart = (const BYTE*) src;
+    const BYTE* const iend = istart + srcSize;
+    const BYTE* ip=iend;
+
+    BIT_CStream_t bitC;
+    FSE_CState_t CState1, CState2;
+
+    /* init */
+    if (srcSize <= 2) return 0;
+    { size_t const initError = BIT_initCStream(&bitC, dst, dstSize);
+      if (FSE_isError(initError)) return 0; /* not enough space available to write a bitstream */ }
+
+#define FSE_FLUSHBITS(s)  (fast ? BIT_flushBitsFast(s) : BIT_flushBits(s))
+
+    if (srcSize & 1) {
+        FSE_initCState2(&CState1, ct, *--ip);
+        FSE_initCState2(&CState2, ct, *--ip);
+        FSE_encodeSymbol(&bitC, &CState1, *--ip);
+        FSE_FLUSHBITS(&bitC);
+    } else {
+        FSE_initCState2(&CState2, ct, *--ip);
+        FSE_initCState2(&CState1, ct, *--ip);
+    }
+
+    /* join to mod 4 */
+    srcSize -= 2;
+    if ((sizeof(bitC.bitContainer)*8 > FSE_MAX_TABLELOG*4+7 ) && (srcSize & 2)) {  /* test bit 2 */
+        FSE_encodeSymbol(&bitC, &CState2, *--ip);
+        FSE_encodeSymbol(&bitC, &CState1, *--ip);
+        FSE_FLUSHBITS(&bitC);
+    }
+
+    /* 2 or 4 encoding per loop */
+    while ( ip>istart ) {
+
+        FSE_encodeSymbol(&bitC, &CState2, *--ip);
+
+        if (sizeof(bitC.bitContainer)*8 < FSE_MAX_TABLELOG*2+7 )   /* this test must be static */
+            FSE_FLUSHBITS(&bitC);
+
+        FSE_encodeSymbol(&bitC, &CState1, *--ip);
+
+        if (sizeof(bitC.bitContainer)*8 > FSE_MAX_TABLELOG*4+7 ) {  /* this test must be static */
+            FSE_encodeSymbol(&bitC, &CState2, *--ip);
+            FSE_encodeSymbol(&bitC, &CState1, *--ip);
+        }
+
+        FSE_FLUSHBITS(&bitC);
+    }
+
+    FSE_flushCState(&bitC, &CState2);
+    FSE_flushCState(&bitC, &CState1);
+    return BIT_closeCStream(&bitC);
+}
+
+size_t FSE_compress_usingCTable (void* dst, size_t dstSize,
+                           const void* src, size_t srcSize,
+                           const FSE_CTable* ct)
+{
+    unsigned const fast = (dstSize >= FSE_BLOCKBOUND(srcSize));
+
+    if (fast)
+        return FSE_compress_usingCTable_generic(dst, dstSize, src, srcSize, ct, 1);
+    else
+        return FSE_compress_usingCTable_generic(dst, dstSize, src, srcSize, ct, 0);
+}
+
+
+size_t FSE_compressBound(size_t size) { return FSE_COMPRESSBOUND(size); }
+
+#endif   /* FSE_COMMONDEFS_ONLY */
diff --git a/src/commonlib/bsd/zstd/compress/hist.c b/src/commonlib/bsd/zstd/compress/hist.c
new file mode 100644
index 0000000000..f5c6ecbc5c
--- /dev/null
+++ b/src/commonlib/bsd/zstd/compress/hist.c
@@ -0,0 +1,193 @@
+/* SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0-only */
+
+/* ******************************************************************
+ * hist : Histogram functions
+ * part of Finite State Entropy project
+ * Copyright (c) Meta Platforms, Inc. and affiliates.
+ *
+ *  You can contact the author at :
+ *  - FSE source repository : https://github.com/Cyan4973/FiniteStateEntropy
+ *  - Public forum : https://groups.google.com/forum/#!forum/lz4c
+ *
+ * This source code is licensed under both the BSD-style license (found in the
+ * LICENSE file in the root directory of this source tree) and the GPLv2 (found
+ * in the COPYING file in the root directory of this source tree).
+ * You may select, at your option, one of the above-listed licenses.
+****************************************************************** */
+
+/* --- dependencies --- */
+#include "../common/mem.h"             /* U32, BYTE, etc. */
+#include "../common/debug.h"           /* assert, DEBUGLOG */
+#include "../common/error_private.h"   /* ERROR */
+#include "hist.h"
+
+
+/* --- Error management --- */
+unsigned HIST_isError(size_t code) { return ERR_isError(code); }
+
+/*-**************************************************************
+ *  Histogram functions
+ ****************************************************************/
+void HIST_add(unsigned* count, const void* src, size_t srcSize)
+{
+    const BYTE* ip = (const BYTE*)src;
+    const BYTE* const end = ip + srcSize;
+
+    while (ip<end) {
+        count[*ip++]++;
+    }
+}
+
+unsigned HIST_count_simple(unsigned* count, unsigned* maxSymbolValuePtr,
+                           const void* src, size_t srcSize)
+{
+    const BYTE* ip = (const BYTE*)src;
+    const BYTE* const end = ip + srcSize;
+    unsigned maxSymbolValue = *maxSymbolValuePtr;
+    unsigned largestCount=0;
+
+    ZSTD_memset(count, 0, (maxSymbolValue+1) * sizeof(*count));
+    if (srcSize==0) { *maxSymbolValuePtr = 0; return 0; }
+
+    while (ip<end) {
+        assert(*ip <= maxSymbolValue);
+        count[*ip++]++;
+    }
+
+    while (!count[maxSymbolValue]) maxSymbolValue--;
+    *maxSymbolValuePtr = maxSymbolValue;
+
+    {   U32 s;
+        for (s=0; s<=maxSymbolValue; s++)
+            if (count[s] > largestCount) largestCount = count[s];
+    }
+
+    return largestCount;
+}
+
+typedef enum { trustInput, checkMaxSymbolValue } HIST_checkInput_e;
+
+/* HIST_count_parallel_wksp() :
+ * store histogram into 4 intermediate tables, recombined at the end.
+ * this design makes better use of OoO cpus,
+ * and is noticeably faster when some values are heavily repeated.
+ * But it needs some additional workspace for intermediate tables.
+ * `workSpace` must be a U32 table of size >= HIST_WKSP_SIZE_U32.
+ * @return : largest histogram frequency,
+ *           or an error code (notably when histogram's alphabet is larger than *maxSymbolValuePtr) */
+static size_t HIST_count_parallel_wksp(
+                                unsigned* count, unsigned* maxSymbolValuePtr,
+                                const void* source, size_t sourceSize,
+                                HIST_checkInput_e check,
+                                U32* const workSpace)
+{
+    const BYTE* ip = (const BYTE*)source;
+    const BYTE* const iend = ip+sourceSize;
+    size_t const countSize = (*maxSymbolValuePtr + 1) * sizeof(*count);
+    unsigned max=0;
+    U32* const Counting1 = workSpace;
+    U32* const Counting2 = Counting1 + 256;
+    U32* const Counting3 = Counting2 + 256;
+    U32* const Counting4 = Counting3 + 256;
+
+    /* safety checks */
+    assert(*maxSymbolValuePtr <= 255);
+    if (!sourceSize) {
+        ZSTD_memset(count, 0, countSize);
+        *maxSymbolValuePtr = 0;
+        return 0;
+    }
+    ZSTD_memset(workSpace, 0, 4*256*sizeof(unsigned));
+
+    /* by stripes of 16 bytes */
+    {   U32 cached = MEM_read32(ip); ip += 4;
+        while (ip < iend-15) {
+            U32 c = cached; cached = MEM_read32(ip); ip += 4;
+            Counting1[(BYTE) c     ]++;
+            Counting2[(BYTE)(c>>8) ]++;
+            Counting3[(BYTE)(c>>16)]++;
+            Counting4[       c>>24 ]++;
+            c = cached; cached = MEM_read32(ip); ip += 4;
+            Counting1[(BYTE) c     ]++;
+            Counting2[(BYTE)(c>>8) ]++;
+            Counting3[(BYTE)(c>>16)]++;
+            Counting4[       c>>24 ]++;
+            c = cached; cached = MEM_read32(ip); ip += 4;
+            Counting1[(BYTE) c     ]++;
+            Counting2[(BYTE)(c>>8) ]++;
+            Counting3[(BYTE)(c>>16)]++;
+            Counting4[       c>>24 ]++;
+            c = cached; cached = MEM_read32(ip); ip += 4;
+            Counting1[(BYTE) c     ]++;
+            Counting2[(BYTE)(c>>8) ]++;
+            Counting3[(BYTE)(c>>16)]++;
+            Counting4[       c>>24 ]++;
+        }
+        ip-=4;
+    }
+
+    /* finish last symbols */
+    while (ip<iend) Counting1[*ip++]++;
+
+    {   U32 s;
+        for (s=0; s<256; s++) {
+            Counting1[s] += Counting2[s] + Counting3[s] + Counting4[s];
+            if (Counting1[s] > max) max = Counting1[s];
+    }   }
+
+    {   unsigned maxSymbolValue = 255;
+        while (!Counting1[maxSymbolValue]) maxSymbolValue--;
+        if (check && maxSymbolValue > *maxSymbolValuePtr) return ERROR(maxSymbolValue_tooSmall);
+        *maxSymbolValuePtr = maxSymbolValue;
+        ZSTD_memmove(count, Counting1, countSize);   /* in case count & Counting1 are overlapping */
+    }
+    return (size_t)max;
+}
+
+/* HIST_countFast_wksp() :
+ * Same as HIST_countFast(), but using an externally provided scratch buffer.
+ * `workSpace` is a writable buffer which must be 4-bytes aligned,
+ * `workSpaceSize` must be >= HIST_WKSP_SIZE
+ */
+size_t HIST_countFast_wksp(unsigned* count, unsigned* maxSymbolValuePtr,
+                          const void* source, size_t sourceSize,
+                          void* workSpace, size_t workSpaceSize)
+{
+    if (sourceSize < 1500) /* heuristic threshold */
+        return HIST_count_simple(count, maxSymbolValuePtr, source, sourceSize);
+    if ((size_t)workSpace & 3) return ERROR(GENERIC);  /* must be aligned on 4-bytes boundaries */
+    if (workSpaceSize < HIST_WKSP_SIZE) return ERROR(workSpace_tooSmall);
+    return HIST_count_parallel_wksp(count, maxSymbolValuePtr, source, sourceSize, trustInput, (U32*)workSpace);
+}
+
+/* HIST_count_wksp() :
+ * Same as HIST_count(), but using an externally provided scratch buffer.
+ * `workSpace` size must be table of >= HIST_WKSP_SIZE_U32 unsigned */
+size_t HIST_count_wksp(unsigned* count, unsigned* maxSymbolValuePtr,
+                       const void* source, size_t sourceSize,
+                       void* workSpace, size_t workSpaceSize)
+{
+    if ((size_t)workSpace & 3) return ERROR(GENERIC);  /* must be aligned on 4-bytes boundaries */
+    if (workSpaceSize < HIST_WKSP_SIZE) return ERROR(workSpace_tooSmall);
+    if (*maxSymbolValuePtr < 255)
+        return HIST_count_parallel_wksp(count, maxSymbolValuePtr, source, sourceSize, checkMaxSymbolValue, (U32*)workSpace);
+    *maxSymbolValuePtr = 255;
+    return HIST_countFast_wksp(count, maxSymbolValuePtr, source, sourceSize, workSpace, workSpaceSize);
+}
+
+#ifndef ZSTD_NO_UNUSED_FUNCTIONS
+/* fast variant (unsafe : won't check if src contains values beyond count[] limit) */
+size_t HIST_countFast(unsigned* count, unsigned* maxSymbolValuePtr,
+                     const void* source, size_t sourceSize)
+{
+    unsigned tmpCounters[HIST_WKSP_SIZE_U32];
+    return HIST_countFast_wksp(count, maxSymbolValuePtr, source, sourceSize, tmpCounters, sizeof(tmpCounters));
+}
+
+size_t HIST_count(unsigned* count, unsigned* maxSymbolValuePtr,
+                 const void* src, size_t srcSize)
+{
+    unsigned tmpCounters[HIST_WKSP_SIZE_U32];
+    return HIST_count_wksp(count, maxSymbolValuePtr, src, srcSize, tmpCounters, sizeof(tmpCounters));
+}
+#endif
diff --git a/src/commonlib/bsd/zstd/compress/hist.h b/src/commonlib/bsd/zstd/compress/hist.h
new file mode 100644
index 0000000000..acb2aec6d5
--- /dev/null
+++ b/src/commonlib/bsd/zstd/compress/hist.h
@@ -0,0 +1,84 @@
+/* SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0-only */
+
+/* ******************************************************************
+ * hist : Histogram functions
+ * part of Finite State Entropy project
+ * Copyright (c) Meta Platforms, Inc. and affiliates.
+ *
+ *  You can contact the author at :
+ *  - FSE source repository : https://github.com/Cyan4973/FiniteStateEntropy
+ *  - Public forum : https://groups.google.com/forum/#!forum/lz4c
+ *
+ * This source code is licensed under both the BSD-style license (found in the
+ * LICENSE file in the root directory of this source tree) and the GPLv2 (found
+ * in the COPYING file in the root directory of this source tree).
+ * You may select, at your option, one of the above-listed licenses.
+****************************************************************** */
+
+/* --- dependencies --- */
+#include "../common/zstd_deps.h"   /* size_t */
+
+
+/* --- simple histogram functions --- */
+
+/*! HIST_count():
+ *  Provides the precise count of each byte within a table 'count'.
+ * 'count' is a table of unsigned int, of minimum size (*maxSymbolValuePtr+1).
+ *  Updates *maxSymbolValuePtr with actual largest symbol value detected.
+ * @return : count of the most frequent symbol (which isn't identified).
+ *           or an error code, which can be tested using HIST_isError().
+ *           note : if return == srcSize, there is only one symbol.
+ */
+size_t HIST_count(unsigned* count, unsigned* maxSymbolValuePtr,
+                  const void* src, size_t srcSize);
+
+unsigned HIST_isError(size_t code);  /**< tells if a return value is an error code */
+
+
+/* --- advanced histogram functions --- */
+
+#define HIST_WKSP_SIZE_U32 1024
+#define HIST_WKSP_SIZE    (HIST_WKSP_SIZE_U32 * sizeof(unsigned))
+/** HIST_count_wksp() :
+ *  Same as HIST_count(), but using an externally provided scratch buffer.
+ *  Benefit is this function will use very little stack space.
+ * `workSpace` is a writable buffer which must be 4-bytes aligned,
+ * `workSpaceSize` must be >= HIST_WKSP_SIZE
+ */
+size_t HIST_count_wksp(unsigned* count, unsigned* maxSymbolValuePtr,
+                       const void* src, size_t srcSize,
+                       void* workSpace, size_t workSpaceSize);
+
+/** HIST_countFast() :
+ *  same as HIST_count(), but blindly trusts that all byte values within src are <= *maxSymbolValuePtr.
+ *  This function is unsafe, and will segfault if any value within `src` is `> *maxSymbolValuePtr`
+ */
+size_t HIST_countFast(unsigned* count, unsigned* maxSymbolValuePtr,
+                      const void* src, size_t srcSize);
+
+/** HIST_countFast_wksp() :
+ *  Same as HIST_countFast(), but using an externally provided scratch buffer.
+ * `workSpace` is a writable buffer which must be 4-bytes aligned,
+ * `workSpaceSize` must be >= HIST_WKSP_SIZE
+ */
+size_t HIST_countFast_wksp(unsigned* count, unsigned* maxSymbolValuePtr,
+                           const void* src, size_t srcSize,
+                           void* workSpace, size_t workSpaceSize);
+
+/*! HIST_count_simple() :
+ *  Same as HIST_countFast(), this function is unsafe,
+ *  and will segfault if any value within `src` is `> *maxSymbolValuePtr`.
+ *  It is also a bit slower for large inputs.
+ *  However, it does not need any additional memory (not even on stack).
+ * @return : count of the most frequent symbol.
+ *  Note this function doesn't produce any error (i.e. it must succeed).
+ */
+unsigned HIST_count_simple(unsigned* count, unsigned* maxSymbolValuePtr,
+                           const void* src, size_t srcSize);
+
+/*! HIST_add() :
+ *  Lowest level: just add nb of occurrences of characters from @src into @count.
+ *  @count is not reset. @count array is presumed large enough (i.e. 1 KB).
+ @  This function does not need any additional stack memory.
+ */
+void HIST_add(unsigned* count, const void* src, size_t srcSize);
diff --git a/src/commonlib/bsd/zstd/compress/huf_compress.c b/src/commonlib/bsd/zstd/compress/huf_compress.c
new file mode 100644
index 0000000000..add0c589fd
--- /dev/null
+++ b/src/commonlib/bsd/zstd/compress/huf_compress.c
@@ -0,0 +1,1466 @@
+/* SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0-only */
+
+/* ******************************************************************
+ * Huffman encoder, part of New Generation Entropy library
+ * Copyright (c) Meta Platforms, Inc. and affiliates.
+ *
+ *  You can contact the author at :
+ *  - FSE+HUF source repository : https://github.com/Cyan4973/FiniteStateEntropy
+ *  - Public forum : https://groups.google.com/forum/#!forum/lz4c
+ *
+ * This source code is licensed under both the BSD-style license (found in the
+ * LICENSE file in the root directory of this source tree) and the GPLv2 (found
+ * in the COPYING file in the root directory of this source tree).
+ * You may select, at your option, one of the above-listed licenses.
+****************************************************************** */
+
+/* **************************************************************
+*  Compiler specifics
+****************************************************************/
+#ifdef _MSC_VER    /* Visual Studio */
+#  pragma warning(disable : 4127)        /* disable: C4127: conditional expression is constant */
+#endif
+
+
+/* **************************************************************
+*  Includes
+****************************************************************/
+#include "../common/zstd_deps.h"     /* ZSTD_memcpy, ZSTD_memset */
+#include "../common/zstd_compiler.h"
+#include "../common/bitstream.h"
+#include "hist.h"
+#define FSE_STATIC_LINKING_ONLY   /* FSE_optimalTableLog_internal */
+#include "../common/fse.h"        /* header compression */
+#include "../common/huf.h"
+#include "../common/error_private.h"
+#include "../common/zstd_bits.h"       /* ZSTD_highbit32 */
+
+
+/* **************************************************************
+*  Error Management
+****************************************************************/
+#define HUF_isError ERR_isError
+#define HUF_STATIC_ASSERT(c) DEBUG_STATIC_ASSERT(c)   /* use only *after* variable declarations */
+
+
+/* **************************************************************
+*  Required declarations
+****************************************************************/
+typedef struct nodeElt_s {
+    U32 count;
+    U16 parent;
+    BYTE byte;
+    BYTE nbBits;
+} nodeElt;
+
+
+/* **************************************************************
+*  Debug Traces
+****************************************************************/
+
+#if DEBUGLEVEL >= 2
+
+static size_t showU32(const U32* arr, size_t size)
+{
+    size_t u;
+    for (u=0; u<size; u++) {
+        RAWLOG(6, " %u", arr[u]); (void)arr;
+    }
+    RAWLOG(6, " \n");
+    return size;
+}
+
+static size_t HUF_getNbBits(HUF_CElt elt);
+
+static size_t showCTableBits(const HUF_CElt* ctable, size_t size)
+{
+    size_t u;
+    for (u=0; u<size; u++) {
+        RAWLOG(6, " %zu", HUF_getNbBits(ctable[u])); (void)ctable;
+    }
+    RAWLOG(6, " \n");
+    return size;
+
+}
+
+static size_t showHNodeSymbols(const nodeElt* hnode, size_t size)
+{
+    size_t u;
+    for (u=0; u<size; u++) {
+        RAWLOG(6, " %u", hnode[u].byte); (void)hnode;
+    }
+    RAWLOG(6, " \n");
+    return size;
+}
+
+static size_t showHNodeBits(const nodeElt* hnode, size_t size)
+{
+    size_t u;
+    for (u=0; u<size; u++) {
+        RAWLOG(6, " %u", hnode[u].nbBits); (void)hnode;
+    }
+    RAWLOG(6, " \n");
+    return size;
+}
+
+#endif
+
+
+/* *******************************************************
+*  HUF : Huffman block compression
+*********************************************************/
+#define HUF_WORKSPACE_MAX_ALIGNMENT 8
+
+static void* HUF_alignUpWorkspace(void* workspace, size_t* workspaceSizePtr, size_t align)
+{
+    size_t const mask = align - 1;
+    size_t const rem = (size_t)workspace & mask;
+    size_t const add = (align - rem) & mask;
+    BYTE* const aligned = (BYTE*)workspace + add;
+    assert((align & (align - 1)) == 0); /* pow 2 */
+    assert(align <= HUF_WORKSPACE_MAX_ALIGNMENT);
+    if (*workspaceSizePtr >= add) {
+        assert(add < align);
+        assert(((size_t)aligned & mask) == 0);
+        *workspaceSizePtr -= add;
+        return aligned;
+    } else {
+        *workspaceSizePtr = 0;
+        return NULL;
+    }
+}
+
+
+/* HUF_compressWeights() :
+ * Same as FSE_compress(), but dedicated to huff0's weights compression.
+ * The use case needs much less stack memory.
+ * Note : all elements within weightTable are supposed to be <= HUF_TABLELOG_MAX.
+ */
+#define MAX_FSE_TABLELOG_FOR_HUFF_HEADER 6
+
+typedef struct {
+    FSE_CTable CTable[FSE_CTABLE_SIZE_U32(MAX_FSE_TABLELOG_FOR_HUFF_HEADER, HUF_TABLELOG_MAX)];
+    U32 scratchBuffer[FSE_BUILD_CTABLE_WORKSPACE_SIZE_U32(HUF_TABLELOG_MAX, MAX_FSE_TABLELOG_FOR_HUFF_HEADER)];
+    unsigned count[HUF_TABLELOG_MAX+1];
+    S16 norm[HUF_TABLELOG_MAX+1];
+} HUF_CompressWeightsWksp;
+
+static size_t
+HUF_compressWeights(void* dst, size_t dstSize,
+              const void* weightTable, size_t wtSize,
+                    void* workspace, size_t workspaceSize)
+{
+    BYTE* const ostart = (BYTE*) dst;
+    BYTE* op = ostart;
+    BYTE* const oend = ostart + dstSize;
+
+    unsigned maxSymbolValue = HUF_TABLELOG_MAX;
+    U32 tableLog = MAX_FSE_TABLELOG_FOR_HUFF_HEADER;
+    HUF_CompressWeightsWksp* wksp = (HUF_CompressWeightsWksp*)HUF_alignUpWorkspace(workspace, &workspaceSize, ZSTD_ALIGNOF(U32));
+
+    if (workspaceSize < sizeof(HUF_CompressWeightsWksp)) return ERROR(GENERIC);
+
+    /* init conditions */
+    if (wtSize <= 1) return 0;  /* Not compressible */
+
+    /* Scan input and build symbol stats */
+    {   unsigned const maxCount = HIST_count_simple(wksp->count, &maxSymbolValue, weightTable, wtSize);   /* never fails */
+        if (maxCount == wtSize) return 1;   /* only a single symbol in src : rle */
+        if (maxCount == 1) return 0;        /* each symbol present maximum once => not compressible */
+    }
+
+    tableLog = FSE_optimalTableLog(tableLog, wtSize, maxSymbolValue);
+    CHECK_F( FSE_normalizeCount(wksp->norm, tableLog, wksp->count, wtSize, maxSymbolValue, /* useLowProbCount */ 0) );
+
+    /* Write table description header */
+    {   CHECK_V_F(hSize, FSE_writeNCount(op, (size_t)(oend-op), wksp->norm, maxSymbolValue, tableLog) );
+        op += hSize;
+    }
+
+    /* Compress */
+    CHECK_F( FSE_buildCTable_wksp(wksp->CTable, wksp->norm, maxSymbolValue, tableLog, wksp->scratchBuffer, sizeof(wksp->scratchBuffer)) );
+    {   CHECK_V_F(cSize, FSE_compress_usingCTable(op, (size_t)(oend - op), weightTable, wtSize, wksp->CTable) );
+        if (cSize == 0) return 0;   /* not enough space for compressed data */
+        op += cSize;
+    }
+
+    return (size_t)(op-ostart);
+}
+
+static size_t HUF_getNbBits(HUF_CElt elt)
+{
+    return elt & 0xFF;
+}
+
+static size_t HUF_getNbBitsFast(HUF_CElt elt)
+{
+    return elt;
+}
+
+static size_t HUF_getValue(HUF_CElt elt)
+{
+    return elt & ~(size_t)0xFF;
+}
+
+static size_t HUF_getValueFast(HUF_CElt elt)
+{
+    return elt;
+}
+
+static void HUF_setNbBits(HUF_CElt* elt, size_t nbBits)
+{
+    assert(nbBits <= HUF_TABLELOG_ABSOLUTEMAX);
+    *elt = nbBits;
+}
+
+static void HUF_setValue(HUF_CElt* elt, size_t value)
+{
+    size_t const nbBits = HUF_getNbBits(*elt);
+    if (nbBits > 0) {
+        assert((value >> nbBits) == 0);
+        *elt |= value << (sizeof(HUF_CElt) * 8 - nbBits);
+    }
+}
+
+HUF_CTableHeader HUF_readCTableHeader(HUF_CElt const* ctable)
+{
+    HUF_CTableHeader header;
+    ZSTD_memcpy(&header, ctable, sizeof(header));
+    return header;
+}
+
+static void HUF_writeCTableHeader(HUF_CElt* ctable, U32 tableLog, U32 maxSymbolValue)
+{
+    HUF_CTableHeader header;
+    HUF_STATIC_ASSERT(sizeof(ctable[0]) == sizeof(header));
+    ZSTD_memset(&header, 0, sizeof(header));
+    assert(tableLog < 256);
+    header.tableLog = (BYTE)tableLog;
+    assert(maxSymbolValue < 256);
+    header.maxSymbolValue = (BYTE)maxSymbolValue;
+    ZSTD_memcpy(ctable, &header, sizeof(header));
+}
+
+typedef struct {
+    HUF_CompressWeightsWksp wksp;
+    BYTE bitsToWeight[HUF_TABLELOG_MAX + 1];   /* precomputed conversion table */
+    BYTE huffWeight[HUF_SYMBOLVALUE_MAX];
+} HUF_WriteCTableWksp;
+
+size_t HUF_writeCTable_wksp(void* dst, size_t maxDstSize,
+                            const HUF_CElt* CTable, unsigned maxSymbolValue, unsigned huffLog,
+                            void* workspace, size_t workspaceSize)
+{
+    HUF_CElt const* const ct = CTable + 1;
+    BYTE* op = (BYTE*)dst;
+    U32 n;
+    HUF_WriteCTableWksp* wksp = (HUF_WriteCTableWksp*)HUF_alignUpWorkspace(workspace, &workspaceSize, ZSTD_ALIGNOF(U32));
+
+    HUF_STATIC_ASSERT(HUF_CTABLE_WORKSPACE_SIZE >= sizeof(HUF_WriteCTableWksp));
+
+    assert(HUF_readCTableHeader(CTable).maxSymbolValue == maxSymbolValue);
+    assert(HUF_readCTableHeader(CTable).tableLog == huffLog);
+
+    /* check conditions */
+    if (workspaceSize < sizeof(HUF_WriteCTableWksp)) return ERROR(GENERIC);
+    if (maxSymbolValue > HUF_SYMBOLVALUE_MAX) return ERROR(maxSymbolValue_tooLarge);
+
+    /* convert to weight */
+    wksp->bitsToWeight[0] = 0;
+    for (n=1; n<huffLog+1; n++)
+        wksp->bitsToWeight[n] = (BYTE)(huffLog + 1 - n);
+    for (n=0; n<maxSymbolValue; n++)
+        wksp->huffWeight[n] = wksp->bitsToWeight[HUF_getNbBits(ct[n])];
+
+    /* attempt weights compression by FSE */
+    if (maxDstSize < 1) return ERROR(dstSize_tooSmall);
+    {   CHECK_V_F(hSize, HUF_compressWeights(op+1, maxDstSize-1, wksp->huffWeight, maxSymbolValue, &wksp->wksp, sizeof(wksp->wksp)) );
+        if ((hSize>1) & (hSize < maxSymbolValue/2)) {   /* FSE compressed */
+            op[0] = (BYTE)hSize;
+            return hSize+1;
+    }   }
+
+    /* write raw values as 4-bits (max : 15) */
+    if (maxSymbolValue > (256-128)) return ERROR(GENERIC);   /* should not happen : likely means source cannot be compressed */
+    if (((maxSymbolValue+1)/2) + 1 > maxDstSize) return ERROR(dstSize_tooSmall);   /* not enough space within dst buffer */
+    op[0] = (BYTE)(128 /*special case*/ + (maxSymbolValue-1));
+    wksp->huffWeight[maxSymbolValue] = 0;   /* to be sure it doesn't cause msan issue in final combination */
+    for (n=0; n<maxSymbolValue; n+=2)
+        op[(n/2)+1] = (BYTE)((wksp->huffWeight[n] << 4) + wksp->huffWeight[n+1]);
+    return ((maxSymbolValue+1)/2) + 1;
+}
+
+
+size_t HUF_readCTable (HUF_CElt* CTable, unsigned* maxSymbolValuePtr, const void* src, size_t srcSize, unsigned* hasZeroWeights)
+{
+    BYTE huffWeight[HUF_SYMBOLVALUE_MAX + 1];   /* init not required, even though some static analyzer may complain */
+    U32 rankVal[HUF_TABLELOG_ABSOLUTEMAX + 1];   /* large enough for values from 0 to 16 */
+    U32 tableLog = 0;
+    U32 nbSymbols = 0;
+    HUF_CElt* const ct = CTable + 1;
+
+    /* get symbol weights */
+    CHECK_V_F(readSize, HUF_readStats(huffWeight, HUF_SYMBOLVALUE_MAX+1, rankVal, &nbSymbols, &tableLog, src, srcSize));
+    *hasZeroWeights = (rankVal[0] > 0);
+
+    /* check result */
+    if (tableLog > HUF_TABLELOG_MAX) return ERROR(tableLog_tooLarge);
+    if (nbSymbols > *maxSymbolValuePtr+1) return ERROR(maxSymbolValue_tooSmall);
+
+    *maxSymbolValuePtr = nbSymbols - 1;
+
+    HUF_writeCTableHeader(CTable, tableLog, *maxSymbolValuePtr);
+
+    /* Prepare base value per rank */
+    {   U32 n, nextRankStart = 0;
+        for (n=1; n<=tableLog; n++) {
+            U32 curr = nextRankStart;
+            nextRankStart += (rankVal[n] << (n-1));
+            rankVal[n] = curr;
+    }   }
+
+    /* fill nbBits */
+    {   U32 n; for (n=0; n<nbSymbols; n++) {
+            const U32 w = huffWeight[n];
+            HUF_setNbBits(ct + n, (BYTE)(tableLog + 1 - w) & -(w != 0));
+    }   }
+
+    /* fill val */
+    {   U16 nbPerRank[HUF_TABLELOG_MAX+2]  = {0};  /* support w=0=>n=tableLog+1 */
+        U16 valPerRank[HUF_TABLELOG_MAX+2] = {0};
+        { U32 n; for (n=0; n<nbSymbols; n++) nbPerRank[HUF_getNbBits(ct[n])]++; }
+        /* determine stating value per rank */
+        valPerRank[tableLog+1] = 0;   /* for w==0 */
+        {   U16 min = 0;
+            U32 n; for (n=tableLog; n>0; n--) {  /* start at n=tablelog <-> w=1 */
+                valPerRank[n] = min;     /* get starting value within each rank */
+                min += nbPerRank[n];
+                min >>= 1;
+        }   }
+        /* assign value within rank, symbol order */
+        { U32 n; for (n=0; n<nbSymbols; n++) HUF_setValue(ct + n, valPerRank[HUF_getNbBits(ct[n])]++); }
+    }
+
+    return readSize;
+}
+
+U32 HUF_getNbBitsFromCTable(HUF_CElt const* CTable, U32 symbolValue)
+{
+    const HUF_CElt* const ct = CTable + 1;
+    assert(symbolValue <= HUF_SYMBOLVALUE_MAX);
+    if (symbolValue > HUF_readCTableHeader(CTable).maxSymbolValue)
+        return 0;
+    return (U32)HUF_getNbBits(ct[symbolValue]);
+}
+
+
+/**
+ * HUF_setMaxHeight():
+ * Try to enforce @targetNbBits on the Huffman tree described in @huffNode.
+ *
+ * It attempts to convert all nodes with nbBits > @targetNbBits
+ * to employ @targetNbBits instead. Then it adjusts the tree
+ * so that it remains a valid canonical Huffman tree.
+ *
+ * @pre               The sum of the ranks of each symbol == 2^largestBits,
+ *                    where largestBits == huffNode[lastNonNull].nbBits.
+ * @post              The sum of the ranks of each symbol == 2^largestBits,
+ *                    where largestBits is the return value (expected <= targetNbBits).
+ *
+ * @param huffNode    The Huffman tree modified in place to enforce targetNbBits.
+ *                    It's presumed sorted, from most frequent to rarest symbol.
+ * @param lastNonNull The symbol with the lowest count in the Huffman tree.
+ * @param targetNbBits  The allowed number of bits, which the Huffman tree
+ *                    may not respect. After this function the Huffman tree will
+ *                    respect targetNbBits.
+ * @return            The maximum number of bits of the Huffman tree after adjustment.
+ */
+static U32 HUF_setMaxHeight(nodeElt* huffNode, U32 lastNonNull, U32 targetNbBits)
+{
+    const U32 largestBits = huffNode[lastNonNull].nbBits;
+    /* early exit : no elt > targetNbBits, so the tree is already valid. */
+    if (largestBits <= targetNbBits) return largestBits;
+
+    DEBUGLOG(5, "HUF_setMaxHeight (targetNbBits = %u)", targetNbBits);
+
+    /* there are several too large elements (at least >= 2) */
+    {   int totalCost = 0;
+        const U32 baseCost = 1 << (largestBits - targetNbBits);
+        int n = (int)lastNonNull;
+
+        /* Adjust any ranks > targetNbBits to targetNbBits.
+         * Compute totalCost, which is how far the sum of the ranks is
+         * we are over 2^largestBits after adjust the offending ranks.
+         */
+        while (huffNode[n].nbBits > targetNbBits) {
+            totalCost += baseCost - (1 << (largestBits - huffNode[n].nbBits));
+            huffNode[n].nbBits = (BYTE)targetNbBits;
+            n--;
+        }
+        /* n stops at huffNode[n].nbBits <= targetNbBits */
+        assert(huffNode[n].nbBits <= targetNbBits);
+        /* n end at index of smallest symbol using < targetNbBits */
+        while (huffNode[n].nbBits == targetNbBits) --n;
+
+        /* renorm totalCost from 2^largestBits to 2^targetNbBits
+         * note : totalCost is necessarily a multiple of baseCost */
+        assert(((U32)totalCost & (baseCost - 1)) == 0);
+        totalCost >>= (largestBits - targetNbBits);
+        assert(totalCost > 0);
+
+        /* repay normalized cost */
+        {   U32 const noSymbol = 0xF0F0F0F0;
+            U32 rankLast[HUF_TABLELOG_MAX+2];
+
+            /* Get pos of last (smallest = lowest cum. count) symbol per rank */
+            ZSTD_memset(rankLast, 0xF0, sizeof(rankLast));
+            {   U32 currentNbBits = targetNbBits;
+                int pos;
+                for (pos=n ; pos >= 0; pos--) {
+                    if (huffNode[pos].nbBits >= currentNbBits) continue;
+                    currentNbBits = huffNode[pos].nbBits;   /* < targetNbBits */
+                    rankLast[targetNbBits-currentNbBits] = (U32)pos;
+            }   }
+
+            while (totalCost > 0) {
+                /* Try to reduce the next power of 2 above totalCost because we
+                 * gain back half the rank.
+                 */
+                U32 nBitsToDecrease = ZSTD_highbit32((U32)totalCost) + 1;
+                for ( ; nBitsToDecrease > 1; nBitsToDecrease--) {
+                    U32 const highPos = rankLast[nBitsToDecrease];
+                    U32 const lowPos = rankLast[nBitsToDecrease-1];
+                    if (highPos == noSymbol) continue;
+                    /* Decrease highPos if no symbols of lowPos or if it is
+                     * not cheaper to remove 2 lowPos than highPos.
+                     */
+                    if (lowPos == noSymbol) break;
+                    {   U32 const highTotal = huffNode[highPos].count;
+                        U32 const lowTotal = 2 * huffNode[lowPos].count;
+                        if (highTotal <= lowTotal) break;
+                }   }
+                /* only triggered when no more rank 1 symbol left => find closest one (note : there is necessarily at least one !) */
+                assert(rankLast[nBitsToDecrease] != noSymbol || nBitsToDecrease == 1);
+                /* HUF_MAX_TABLELOG test just to please gcc 5+; but it should not be necessary */
+                while ((nBitsToDecrease<=HUF_TABLELOG_MAX) && (rankLast[nBitsToDecrease] == noSymbol))
+                    nBitsToDecrease++;
+                assert(rankLast[nBitsToDecrease] != noSymbol);
+                /* Increase the number of bits to gain back half the rank cost. */
+                totalCost -= 1 << (nBitsToDecrease-1);
+                huffNode[rankLast[nBitsToDecrease]].nbBits++;
+
+                /* Fix up the new rank.
+                 * If the new rank was empty, this symbol is now its smallest.
+                 * Otherwise, this symbol will be the largest in the new rank so no adjustment.
+                 */
+                if (rankLast[nBitsToDecrease-1] == noSymbol)
+                    rankLast[nBitsToDecrease-1] = rankLast[nBitsToDecrease];
+                /* Fix up the old rank.
+                 * If the symbol was at position 0, meaning it was the highest weight symbol in the tree,
+                 * it must be the only symbol in its rank, so the old rank now has no symbols.
+                 * Otherwise, since the Huffman nodes are sorted by count, the previous position is now
+                 * the smallest node in the rank. If the previous position belongs to a different rank,
+                 * then the rank is now empty.
+                 */
+                if (rankLast[nBitsToDecrease] == 0)    /* special case, reached largest symbol */
+                    rankLast[nBitsToDecrease] = noSymbol;
+                else {
+                    rankLast[nBitsToDecrease]--;
+                    if (huffNode[rankLast[nBitsToDecrease]].nbBits != targetNbBits-nBitsToDecrease)
+                        rankLast[nBitsToDecrease] = noSymbol;   /* this rank is now empty */
+                }
+            }   /* while (totalCost > 0) */
+
+            /* If we've removed too much weight, then we have to add it back.
+             * To avoid overshooting again, we only adjust the smallest rank.
+             * We take the largest nodes from the lowest rank 0 and move them
+             * to rank 1. There's guaranteed to be enough rank 0 symbols because
+             * TODO.
+             */
+            while (totalCost < 0) {  /* Sometimes, cost correction overshoot */
+                /* special case : no rank 1 symbol (using targetNbBits-1);
+                 * let's create one from largest rank 0 (using targetNbBits).
+                 */
+                if (rankLast[1] == noSymbol) {
+                    while (huffNode[n].nbBits == targetNbBits) n--;
+                    huffNode[n+1].nbBits--;
+                    assert(n >= 0);
+                    rankLast[1] = (U32)(n+1);
+                    totalCost++;
+                    continue;
+                }
+                huffNode[ rankLast[1] + 1 ].nbBits--;
+                rankLast[1]++;
+                totalCost ++;
+            }
+        }   /* repay normalized cost */
+    }   /* there are several too large elements (at least >= 2) */
+
+    return targetNbBits;
+}
+
+typedef struct {
+    U16 base;
+    U16 curr;
+} rankPos;
+
+typedef nodeElt huffNodeTable[2 * (HUF_SYMBOLVALUE_MAX + 1)];
+
+/* Number of buckets available for HUF_sort() */
+#define RANK_POSITION_TABLE_SIZE 192
+
+typedef struct {
+  huffNodeTable huffNodeTbl;
+  rankPos rankPosition[RANK_POSITION_TABLE_SIZE];
+} HUF_buildCTable_wksp_tables;
+
+/* RANK_POSITION_DISTINCT_COUNT_CUTOFF == Cutoff point in HUF_sort() buckets for which we use log2 bucketing.
+ * Strategy is to use as many buckets as possible for representing distinct
+ * counts while using the remainder to represent all "large" counts.
+ *
+ * To satisfy this requirement for 192 buckets, we can do the following:
+ * Let buckets 0-166 represent distinct counts of [0, 166]
+ * Let buckets 166 to 192 represent all remaining counts up to RANK_POSITION_MAX_COUNT_LOG using log2 bucketing.
+ */
+#define RANK_POSITION_MAX_COUNT_LOG 32
+#define RANK_POSITION_LOG_BUCKETS_BEGIN ((RANK_POSITION_TABLE_SIZE - 1) - RANK_POSITION_MAX_COUNT_LOG - 1 /* == 158 */)
+#define RANK_POSITION_DISTINCT_COUNT_CUTOFF (RANK_POSITION_LOG_BUCKETS_BEGIN + ZSTD_highbit32(RANK_POSITION_LOG_BUCKETS_BEGIN) /* == 166 */)
+
+/* Return the appropriate bucket index for a given count. See definition of
+ * RANK_POSITION_DISTINCT_COUNT_CUTOFF for explanation of bucketing strategy.
+ */
+static U32 HUF_getIndex(U32 const count) {
+    return (count < RANK_POSITION_DISTINCT_COUNT_CUTOFF)
+        ? count
+        : ZSTD_highbit32(count) + RANK_POSITION_LOG_BUCKETS_BEGIN;
+}
+
+/* Helper swap function for HUF_quickSortPartition() */
+static void HUF_swapNodes(nodeElt* a, nodeElt* b) {
+	nodeElt tmp = *a;
+	*a = *b;
+	*b = tmp;
+}
+
+/* Returns 0 if the huffNode array is not sorted by descending count */
+MEM_STATIC int HUF_isSorted(nodeElt huffNode[], U32 const maxSymbolValue1) {
+    U32 i;
+    for (i = 1; i < maxSymbolValue1; ++i) {
+        if (huffNode[i].count > huffNode[i-1].count) {
+            return 0;
+        }
+    }
+    return 1;
+}
+
+/* Insertion sort by descending order */
+HINT_INLINE void HUF_insertionSort(nodeElt huffNode[], int const low, int const high) {
+    int i;
+    int const size = high-low+1;
+    huffNode += low;
+    for (i = 1; i < size; ++i) {
+        nodeElt const key = huffNode[i];
+        int j = i - 1;
+        while (j >= 0 && huffNode[j].count < key.count) {
+            huffNode[j + 1] = huffNode[j];
+            j--;
+        }
+        huffNode[j + 1] = key;
+    }
+}
+
+/* Pivot helper function for quicksort. */
+static int HUF_quickSortPartition(nodeElt arr[], int const low, int const high) {
+    /* Simply select rightmost element as pivot. "Better" selectors like
+     * median-of-three don't experimentally appear to have any benefit.
+     */
+    U32 const pivot = arr[high].count;
+    int i = low - 1;
+    int j = low;
+    for ( ; j < high; j++) {
+        if (arr[j].count > pivot) {
+            i++;
+            HUF_swapNodes(&arr[i], &arr[j]);
+        }
+    }
+    HUF_swapNodes(&arr[i + 1], &arr[high]);
+    return i + 1;
+}
+
+/* Classic quicksort by descending with partially iterative calls
+ * to reduce worst case callstack size.
+ */
+static void HUF_simpleQuickSort(nodeElt arr[], int low, int high) {
+    int const kInsertionSortThreshold = 8;
+    if (high - low < kInsertionSortThreshold) {
+        HUF_insertionSort(arr, low, high);
+        return;
+    }
+    while (low < high) {
+        int const idx = HUF_quickSortPartition(arr, low, high);
+        if (idx - low < high - idx) {
+            HUF_simpleQuickSort(arr, low, idx - 1);
+            low = idx + 1;
+        } else {
+            HUF_simpleQuickSort(arr, idx + 1, high);
+            high = idx - 1;
+        }
+    }
+}
+
+/**
+ * HUF_sort():
+ * Sorts the symbols [0, maxSymbolValue] by count[symbol] in decreasing order.
+ * This is a typical bucket sorting strategy that uses either quicksort or insertion sort to sort each bucket.
+ *
+ * @param[out] huffNode       Sorted symbols by decreasing count. Only members `.count` and `.byte` are filled.
+ *                            Must have (maxSymbolValue + 1) entries.
+ * @param[in]  count          Histogram of the symbols.
+ * @param[in]  maxSymbolValue Maximum symbol value.
+ * @param      rankPosition   This is a scratch workspace. Must have RANK_POSITION_TABLE_SIZE entries.
+ */
+static void HUF_sort(nodeElt huffNode[], const unsigned count[], U32 const maxSymbolValue, rankPos rankPosition[]) {
+    U32 n;
+    U32 const maxSymbolValue1 = maxSymbolValue+1;
+
+    /* Compute base and set curr to base.
+     * For symbol s let lowerRank = HUF_getIndex(count[n]) and rank = lowerRank + 1.
+     * See HUF_getIndex to see bucketing strategy.
+     * We attribute each symbol to lowerRank's base value, because we want to know where
+     * each rank begins in the output, so for rank R we want to count ranks R+1 and above.
+     */
+    ZSTD_memset(rankPosition, 0, sizeof(*rankPosition) * RANK_POSITION_TABLE_SIZE);
+    for (n = 0; n < maxSymbolValue1; ++n) {
+        U32 lowerRank = HUF_getIndex(count[n]);
+        assert(lowerRank < RANK_POSITION_TABLE_SIZE - 1);
+        rankPosition[lowerRank].base++;
+    }
+
+    assert(rankPosition[RANK_POSITION_TABLE_SIZE - 1].base == 0);
+    /* Set up the rankPosition table */
+    for (n = RANK_POSITION_TABLE_SIZE - 1; n > 0; --n) {
+        rankPosition[n-1].base += rankPosition[n].base;
+        rankPosition[n-1].curr = rankPosition[n-1].base;
+    }
+
+    /* Insert each symbol into their appropriate bucket, setting up rankPosition table. */
+    for (n = 0; n < maxSymbolValue1; ++n) {
+        U32 const c = count[n];
+        U32 const r = HUF_getIndex(c) + 1;
+        U32 const pos = rankPosition[r].curr++;
+        assert(pos < maxSymbolValue1);
+        huffNode[pos].count = c;
+        huffNode[pos].byte  = (BYTE)n;
+    }
+
+    /* Sort each bucket. */
+    for (n = RANK_POSITION_DISTINCT_COUNT_CUTOFF; n < RANK_POSITION_TABLE_SIZE - 1; ++n) {
+        int const bucketSize = rankPosition[n].curr - rankPosition[n].base;
+        U32 const bucketStartIdx = rankPosition[n].base;
+        if (bucketSize > 1) {
+            assert(bucketStartIdx < maxSymbolValue1);
+            HUF_simpleQuickSort(huffNode + bucketStartIdx, 0, bucketSize-1);
+        }
+    }
+
+    assert(HUF_isSorted(huffNode, maxSymbolValue1));
+}
+
+
+/** HUF_buildCTable_wksp() :
+ *  Same as HUF_buildCTable(), but using externally allocated scratch buffer.
+ *  `workSpace` must be aligned on 4-bytes boundaries, and be at least as large as sizeof(HUF_buildCTable_wksp_tables).
+ */
+#define STARTNODE (HUF_SYMBOLVALUE_MAX+1)
+
+/* HUF_buildTree():
+ * Takes the huffNode array sorted by HUF_sort() and builds an unlimited-depth Huffman tree.
+ *
+ * @param huffNode        The array sorted by HUF_sort(). Builds the Huffman tree in this array.
+ * @param maxSymbolValue  The maximum symbol value.
+ * @return                The smallest node in the Huffman tree (by count).
+ */
+static int HUF_buildTree(nodeElt* huffNode, U32 maxSymbolValue)
+{
+    nodeElt* const huffNode0 = huffNode - 1;
+    int nonNullRank;
+    int lowS, lowN;
+    int nodeNb = STARTNODE;
+    int n, nodeRoot;
+    DEBUGLOG(5, "HUF_buildTree (alphabet size = %u)", maxSymbolValue + 1);
+    /* init for parents */
+    nonNullRank = (int)maxSymbolValue;
+    while(huffNode[nonNullRank].count == 0) nonNullRank--;
+    lowS = nonNullRank; nodeRoot = nodeNb + lowS - 1; lowN = nodeNb;
+    huffNode[nodeNb].count = huffNode[lowS].count + huffNode[lowS-1].count;
+    huffNode[lowS].parent = huffNode[lowS-1].parent = (U16)nodeNb;
+    nodeNb++; lowS-=2;
+    for (n=nodeNb; n<=nodeRoot; n++) huffNode[n].count = (U32)(1U<<30);
+    huffNode0[0].count = (U32)(1U<<31);  /* fake entry, strong barrier */
+
+    /* create parents */
+    while (nodeNb <= nodeRoot) {
+        int const n1 = (huffNode[lowS].count < huffNode[lowN].count) ? lowS-- : lowN++;
+        int const n2 = (huffNode[lowS].count < huffNode[lowN].count) ? lowS-- : lowN++;
+        huffNode[nodeNb].count = huffNode[n1].count + huffNode[n2].count;
+        huffNode[n1].parent = huffNode[n2].parent = (U16)nodeNb;
+        nodeNb++;
+    }
+
+    /* distribute weights (unlimited tree height) */
+    huffNode[nodeRoot].nbBits = 0;
+    for (n=nodeRoot-1; n>=STARTNODE; n--)
+        huffNode[n].nbBits = huffNode[ huffNode[n].parent ].nbBits + 1;
+    for (n=0; n<=nonNullRank; n++)
+        huffNode[n].nbBits = huffNode[ huffNode[n].parent ].nbBits + 1;
+
+    DEBUGLOG(6, "Initial distribution of bits completed (%zu sorted symbols)", showHNodeBits(huffNode, maxSymbolValue+1));
+
+    return nonNullRank;
+}
+
+/**
+ * HUF_buildCTableFromTree():
+ * Build the CTable given the Huffman tree in huffNode.
+ *
+ * @param[out] CTable         The output Huffman CTable.
+ * @param      huffNode       The Huffman tree.
+ * @param      nonNullRank    The last and smallest node in the Huffman tree.
+ * @param      maxSymbolValue The maximum symbol value.
+ * @param      maxNbBits      The exact maximum number of bits used in the Huffman tree.
+ */
+static void HUF_buildCTableFromTree(HUF_CElt* CTable, nodeElt const* huffNode, int nonNullRank, U32 maxSymbolValue, U32 maxNbBits)
+{
+    HUF_CElt* const ct = CTable + 1;
+    /* fill result into ctable (val, nbBits) */
+    int n;
+    U16 nbPerRank[HUF_TABLELOG_MAX+1] = {0};
+    U16 valPerRank[HUF_TABLELOG_MAX+1] = {0};
+    int const alphabetSize = (int)(maxSymbolValue + 1);
+    for (n=0; n<=nonNullRank; n++)
+        nbPerRank[huffNode[n].nbBits]++;
+    /* determine starting value per rank */
+    {   U16 min = 0;
+        for (n=(int)maxNbBits; n>0; n--) {
+            valPerRank[n] = min;      /* get starting value within each rank */
+            min += nbPerRank[n];
+            min >>= 1;
+    }   }
+    for (n=0; n<alphabetSize; n++)
+        HUF_setNbBits(ct + huffNode[n].byte, huffNode[n].nbBits);   /* push nbBits per symbol, symbol order */
+    for (n=0; n<alphabetSize; n++)
+        HUF_setValue(ct + n, valPerRank[HUF_getNbBits(ct[n])]++);   /* assign value within rank, symbol order */
+
+    HUF_writeCTableHeader(CTable, maxNbBits, maxSymbolValue);
+}
+
+size_t
+HUF_buildCTable_wksp(HUF_CElt* CTable, const unsigned* count, U32 maxSymbolValue, U32 maxNbBits,
+                     void* workSpace, size_t wkspSize)
+{
+    HUF_buildCTable_wksp_tables* const wksp_tables =
+        (HUF_buildCTable_wksp_tables*)HUF_alignUpWorkspace(workSpace, &wkspSize, ZSTD_ALIGNOF(U32));
+    nodeElt* const huffNode0 = wksp_tables->huffNodeTbl;
+    nodeElt* const huffNode = huffNode0+1;
+    int nonNullRank;
+
+    HUF_STATIC_ASSERT(HUF_CTABLE_WORKSPACE_SIZE == sizeof(HUF_buildCTable_wksp_tables));
+
+    DEBUGLOG(5, "HUF_buildCTable_wksp (alphabet size = %u)", maxSymbolValue+1);
+
+    /* safety checks */
+    if (wkspSize < sizeof(HUF_buildCTable_wksp_tables))
+        return ERROR(workSpace_tooSmall);
+    if (maxNbBits == 0) maxNbBits = HUF_TABLELOG_DEFAULT;
+    if (maxSymbolValue > HUF_SYMBOLVALUE_MAX)
+        return ERROR(maxSymbolValue_tooLarge);
+    ZSTD_memset(huffNode0, 0, sizeof(huffNodeTable));
+
+    /* sort, decreasing order */
+    HUF_sort(huffNode, count, maxSymbolValue, wksp_tables->rankPosition);
+    DEBUGLOG(6, "sorted symbols completed (%zu symbols)", showHNodeSymbols(huffNode, maxSymbolValue+1));
+
+    /* build tree */
+    nonNullRank = HUF_buildTree(huffNode, maxSymbolValue);
+
+    /* determine and enforce maxTableLog */
+    maxNbBits = HUF_setMaxHeight(huffNode, (U32)nonNullRank, maxNbBits);
+    if (maxNbBits > HUF_TABLELOG_MAX) return ERROR(GENERIC);   /* check fit into table */
+
+    HUF_buildCTableFromTree(CTable, huffNode, nonNullRank, maxSymbolValue, maxNbBits);
+
+    return maxNbBits;
+}
+
+size_t HUF_estimateCompressedSize(const HUF_CElt* CTable, const unsigned* count, unsigned maxSymbolValue)
+{
+    HUF_CElt const* ct = CTable + 1;
+    size_t nbBits = 0;
+    int s;
+    for (s = 0; s <= (int)maxSymbolValue; ++s) {
+        nbBits += HUF_getNbBits(ct[s]) * count[s];
+    }
+    return nbBits >> 3;
+}
+
+int HUF_validateCTable(const HUF_CElt* CTable, const unsigned* count, unsigned maxSymbolValue) {
+    HUF_CTableHeader header = HUF_readCTableHeader(CTable);
+    HUF_CElt const* ct = CTable + 1;
+    int bad = 0;
+    int s;
+
+    assert(header.tableLog <= HUF_TABLELOG_ABSOLUTEMAX);
+
+    if (header.maxSymbolValue < maxSymbolValue)
+        return 0;
+
+    for (s = 0; s <= (int)maxSymbolValue; ++s) {
+        bad |= (count[s] != 0) & (HUF_getNbBits(ct[s]) == 0);
+    }
+    return !bad;
+}
+
+size_t HUF_compressBound(size_t size) { return HUF_COMPRESSBOUND(size); }
+
+/** HUF_CStream_t:
+ * Huffman uses its own BIT_CStream_t implementation.
+ * There are three major differences from BIT_CStream_t:
+ *   1. HUF_addBits() takes a HUF_CElt (size_t) which is
+ *      the pair (nbBits, value) in the format:
+ *      format:
+ *        - Bits [0, 4)            = nbBits
+ *        - Bits [4, 64 - nbBits)  = 0
+ *        - Bits [64 - nbBits, 64) = value
+ *   2. The bitContainer is built from the upper bits and
+ *      right shifted. E.g. to add a new value of N bits
+ *      you right shift the bitContainer by N, then or in
+ *      the new value into the N upper bits.
+ *   3. The bitstream has two bit containers. You can add
+ *      bits to the second container and merge them into
+ *      the first container.
+ */
+
+#define HUF_BITS_IN_CONTAINER (sizeof(size_t) * 8)
+
+typedef struct {
+    size_t bitContainer[2];
+    size_t bitPos[2];
+
+    BYTE* startPtr;
+    BYTE* ptr;
+    BYTE* endPtr;
+} HUF_CStream_t;
+
+/**! HUF_initCStream():
+ * Initializes the bitstream.
+ * @returns 0 or an error code.
+ */
+static size_t HUF_initCStream(HUF_CStream_t* bitC,
+                                  void* startPtr, size_t dstCapacity)
+{
+    ZSTD_memset(bitC, 0, sizeof(*bitC));
+    bitC->startPtr = (BYTE*)startPtr;
+    bitC->ptr = bitC->startPtr;
+    bitC->endPtr = bitC->startPtr + dstCapacity - sizeof(bitC->bitContainer[0]);
+    if (dstCapacity <= sizeof(bitC->bitContainer[0])) return ERROR(dstSize_tooSmall);
+    return 0;
+}
+
+/*! HUF_addBits():
+ * Adds the symbol stored in HUF_CElt elt to the bitstream.
+ *
+ * @param elt   The element we're adding. This is a (nbBits, value) pair.
+ *              See the HUF_CStream_t docs for the format.
+ * @param idx   Insert into the bitstream at this idx.
+ * @param kFast This is a template parameter. If the bitstream is guaranteed
+ *              to have at least 4 unused bits after this call it may be 1,
+ *              otherwise it must be 0. HUF_addBits() is faster when fast is set.
+ */
+FORCE_INLINE_TEMPLATE void HUF_addBits(HUF_CStream_t* bitC, HUF_CElt elt, int idx, int kFast)
+{
+    assert(idx <= 1);
+    assert(HUF_getNbBits(elt) <= HUF_TABLELOG_ABSOLUTEMAX);
+    /* This is efficient on x86-64 with BMI2 because shrx
+     * only reads the low 6 bits of the register. The compiler
+     * knows this and elides the mask. When fast is set,
+     * every operation can use the same value loaded from elt.
+     */
+    bitC->bitContainer[idx] >>= HUF_getNbBits(elt);
+    bitC->bitContainer[idx] |= kFast ? HUF_getValueFast(elt) : HUF_getValue(elt);
+    /* We only read the low 8 bits of bitC->bitPos[idx] so it
+     * doesn't matter that the high bits have noise from the value.
+     */
+    bitC->bitPos[idx] += HUF_getNbBitsFast(elt);
+    assert((bitC->bitPos[idx] & 0xFF) <= HUF_BITS_IN_CONTAINER);
+    /* The last 4-bits of elt are dirty if fast is set,
+     * so we must not be overwriting bits that have already been
+     * inserted into the bit container.
+     */
+#if DEBUGLEVEL >= 1
+    {
+        size_t const nbBits = HUF_getNbBits(elt);
+        size_t const dirtyBits = nbBits == 0 ? 0 : ZSTD_highbit32((U32)nbBits) + 1;
+        (void)dirtyBits;
+        /* Middle bits are 0. */
+        assert(((elt >> dirtyBits) << (dirtyBits + nbBits)) == 0);
+        /* We didn't overwrite any bits in the bit container. */
+        assert(!kFast || (bitC->bitPos[idx] & 0xFF) <= HUF_BITS_IN_CONTAINER);
+        (void)dirtyBits;
+    }
+#endif
+}
+
+FORCE_INLINE_TEMPLATE void HUF_zeroIndex1(HUF_CStream_t* bitC)
+{
+    bitC->bitContainer[1] = 0;
+    bitC->bitPos[1] = 0;
+}
+
+/*! HUF_mergeIndex1() :
+ * Merges the bit container @ index 1 into the bit container @ index 0
+ * and zeros the bit container @ index 1.
+ */
+FORCE_INLINE_TEMPLATE void HUF_mergeIndex1(HUF_CStream_t* bitC)
+{
+    assert((bitC->bitPos[1] & 0xFF) < HUF_BITS_IN_CONTAINER);
+    bitC->bitContainer[0] >>= (bitC->bitPos[1] & 0xFF);
+    bitC->bitContainer[0] |= bitC->bitContainer[1];
+    bitC->bitPos[0] += bitC->bitPos[1];
+    assert((bitC->bitPos[0] & 0xFF) <= HUF_BITS_IN_CONTAINER);
+}
+
+/*! HUF_flushBits() :
+* Flushes the bits in the bit container @ index 0.
+*
+* @post bitPos will be < 8.
+* @param kFast If kFast is set then we must know a-priori that
+*              the bit container will not overflow.
+*/
+FORCE_INLINE_TEMPLATE void HUF_flushBits(HUF_CStream_t* bitC, int kFast)
+{
+    /* The upper bits of bitPos are noisy, so we must mask by 0xFF. */
+    size_t const nbBits = bitC->bitPos[0] & 0xFF;
+    size_t const nbBytes = nbBits >> 3;
+    /* The top nbBits bits of bitContainer are the ones we need. */
+    size_t const bitContainer = bitC->bitContainer[0] >> (HUF_BITS_IN_CONTAINER - nbBits);
+    /* Mask bitPos to account for the bytes we consumed. */
+    bitC->bitPos[0] &= 7;
+    assert(nbBits > 0);
+    assert(nbBits <= sizeof(bitC->bitContainer[0]) * 8);
+    assert(bitC->ptr <= bitC->endPtr);
+    MEM_writeLEST(bitC->ptr, bitContainer);
+    bitC->ptr += nbBytes;
+    assert(!kFast || bitC->ptr <= bitC->endPtr);
+    if (!kFast && bitC->ptr > bitC->endPtr) bitC->ptr = bitC->endPtr;
+    /* bitContainer doesn't need to be modified because the leftover
+     * bits are already the top bitPos bits. And we don't care about
+     * noise in the lower values.
+     */
+}
+
+/*! HUF_endMark()
+ * @returns The Huffman stream end mark: A 1-bit value = 1.
+ */
+static HUF_CElt HUF_endMark(void)
+{
+    HUF_CElt endMark;
+    HUF_setNbBits(&endMark, 1);
+    HUF_setValue(&endMark, 1);
+    return endMark;
+}
+
+/*! HUF_closeCStream() :
+ *  @return Size of CStream, in bytes,
+ *          or 0 if it could not fit into dstBuffer */
+static size_t HUF_closeCStream(HUF_CStream_t* bitC)
+{
+    HUF_addBits(bitC, HUF_endMark(), /* idx */ 0, /* kFast */ 0);
+    HUF_flushBits(bitC, /* kFast */ 0);
+    {
+        size_t const nbBits = bitC->bitPos[0] & 0xFF;
+        if (bitC->ptr >= bitC->endPtr) return 0; /* overflow detected */
+        return (size_t)(bitC->ptr - bitC->startPtr) + (nbBits > 0);
+    }
+}
+
+FORCE_INLINE_TEMPLATE void
+HUF_encodeSymbol(HUF_CStream_t* bitCPtr, U32 symbol, const HUF_CElt* CTable, int idx, int fast)
+{
+    HUF_addBits(bitCPtr, CTable[symbol], idx, fast);
+}
+
+FORCE_INLINE_TEMPLATE void
+HUF_compress1X_usingCTable_internal_body_loop(HUF_CStream_t* bitC,
+                                   const BYTE* ip, size_t srcSize,
+                                   const HUF_CElt* ct,
+                                   int kUnroll, int kFastFlush, int kLastFast)
+{
+    /* Join to kUnroll */
+    int n = (int)srcSize;
+    int rem = n % kUnroll;
+    if (rem > 0) {
+        for (; rem > 0; --rem) {
+            HUF_encodeSymbol(bitC, ip[--n], ct, 0, /* fast */ 0);
+        }
+        HUF_flushBits(bitC, kFastFlush);
+    }
+    assert(n % kUnroll == 0);
+
+    /* Join to 2 * kUnroll */
+    if (n % (2 * kUnroll)) {
+        int u;
+        for (u = 1; u < kUnroll; ++u) {
+            HUF_encodeSymbol(bitC, ip[n - u], ct, 0, 1);
+        }
+        HUF_encodeSymbol(bitC, ip[n - kUnroll], ct, 0, kLastFast);
+        HUF_flushBits(bitC, kFastFlush);
+        n -= kUnroll;
+    }
+    assert(n % (2 * kUnroll) == 0);
+
+    for (; n>0; n-= 2 * kUnroll) {
+        /* Encode kUnroll symbols into the bitstream @ index 0. */
+        int u;
+        for (u = 1; u < kUnroll; ++u) {
+            HUF_encodeSymbol(bitC, ip[n - u], ct, /* idx */ 0, /* fast */ 1);
+        }
+        HUF_encodeSymbol(bitC, ip[n - kUnroll], ct, /* idx */ 0, /* fast */ kLastFast);
+        HUF_flushBits(bitC, kFastFlush);
+        /* Encode kUnroll symbols into the bitstream @ index 1.
+         * This allows us to start filling the bit container
+         * without any data dependencies.
+         */
+        HUF_zeroIndex1(bitC);
+        for (u = 1; u < kUnroll; ++u) {
+            HUF_encodeSymbol(bitC, ip[n - kUnroll - u], ct, /* idx */ 1, /* fast */ 1);
+        }
+        HUF_encodeSymbol(bitC, ip[n - kUnroll - kUnroll], ct, /* idx */ 1, /* fast */ kLastFast);
+        /* Merge bitstream @ index 1 into the bitstream @ index 0 */
+        HUF_mergeIndex1(bitC);
+        HUF_flushBits(bitC, kFastFlush);
+    }
+    assert(n == 0);
+
+}
+
+/**
+ * Returns a tight upper bound on the output space needed by Huffman
+ * with 8 bytes buffer to handle over-writes. If the output is at least
+ * this large we don't need to do bounds checks during Huffman encoding.
+ */
+static size_t HUF_tightCompressBound(size_t srcSize, size_t tableLog)
+{
+    return ((srcSize * tableLog) >> 3) + 8;
+}
+
+
+FORCE_INLINE_TEMPLATE size_t
+HUF_compress1X_usingCTable_internal_body(void* dst, size_t dstSize,
+                                   const void* src, size_t srcSize,
+                                   const HUF_CElt* CTable)
+{
+    U32 const tableLog = HUF_readCTableHeader(CTable).tableLog;
+    HUF_CElt const* ct = CTable + 1;
+    const BYTE* ip = (const BYTE*) src;
+    BYTE* const ostart = (BYTE*)dst;
+    BYTE* const oend = ostart + dstSize;
+    HUF_CStream_t bitC;
+
+    /* init */
+    if (dstSize < 8) return 0;   /* not enough space to compress */
+    { BYTE* op = ostart;
+      size_t const initErr = HUF_initCStream(&bitC, op, (size_t)(oend-op));
+      if (HUF_isError(initErr)) return 0; }
+
+    if (dstSize < HUF_tightCompressBound(srcSize, (size_t)tableLog) || tableLog > 11)
+        HUF_compress1X_usingCTable_internal_body_loop(&bitC, ip, srcSize, ct, /* kUnroll */ MEM_32bits() ? 2 : 4, /* kFast */ 0, /* kLastFast */ 0);
+    else {
+        if (MEM_32bits()) {
+            switch (tableLog) {
+            case 11:
+                HUF_compress1X_usingCTable_internal_body_loop(&bitC, ip, srcSize, ct, /* kUnroll */ 2, /* kFastFlush */ 1, /* kLastFast */ 0);
+                break;
+            case 10: ZSTD_FALLTHROUGH;
+            case 9: ZSTD_FALLTHROUGH;
+            case 8:
+                HUF_compress1X_usingCTable_internal_body_loop(&bitC, ip, srcSize, ct, /* kUnroll */ 2, /* kFastFlush */ 1, /* kLastFast */ 1);
+                break;
+            case 7: ZSTD_FALLTHROUGH;
+            default:
+                HUF_compress1X_usingCTable_internal_body_loop(&bitC, ip, srcSize, ct, /* kUnroll */ 3, /* kFastFlush */ 1, /* kLastFast */ 1);
+                break;
+            }
+        } else {
+            switch (tableLog) {
+            case 11:
+                HUF_compress1X_usingCTable_internal_body_loop(&bitC, ip, srcSize, ct, /* kUnroll */ 5, /* kFastFlush */ 1, /* kLastFast */ 0);
+                break;
+            case 10:
+                HUF_compress1X_usingCTable_internal_body_loop(&bitC, ip, srcSize, ct, /* kUnroll */ 5, /* kFastFlush */ 1, /* kLastFast */ 1);
+                break;
+            case 9:
+                HUF_compress1X_usingCTable_internal_body_loop(&bitC, ip, srcSize, ct, /* kUnroll */ 6, /* kFastFlush */ 1, /* kLastFast */ 0);
+                break;
+            case 8:
+                HUF_compress1X_usingCTable_internal_body_loop(&bitC, ip, srcSize, ct, /* kUnroll */ 7, /* kFastFlush */ 1, /* kLastFast */ 0);
+                break;
+            case 7:
+                HUF_compress1X_usingCTable_internal_body_loop(&bitC, ip, srcSize, ct, /* kUnroll */ 8, /* kFastFlush */ 1, /* kLastFast */ 0);
+                break;
+            case 6: ZSTD_FALLTHROUGH;
+            default:
+                HUF_compress1X_usingCTable_internal_body_loop(&bitC, ip, srcSize, ct, /* kUnroll */ 9, /* kFastFlush */ 1, /* kLastFast */ 1);
+                break;
+            }
+        }
+    }
+    assert(bitC.ptr <= bitC.endPtr);
+
+    return HUF_closeCStream(&bitC);
+}
+
+#if DYNAMIC_BMI2
+
+static BMI2_TARGET_ATTRIBUTE size_t
+HUF_compress1X_usingCTable_internal_bmi2(void* dst, size_t dstSize,
+                                   const void* src, size_t srcSize,
+                                   const HUF_CElt* CTable)
+{
+    return HUF_compress1X_usingCTable_internal_body(dst, dstSize, src, srcSize, CTable);
+}
+
+static size_t
+HUF_compress1X_usingCTable_internal_default(void* dst, size_t dstSize,
+                                      const void* src, size_t srcSize,
+                                      const HUF_CElt* CTable)
+{
+    return HUF_compress1X_usingCTable_internal_body(dst, dstSize, src, srcSize, CTable);
+}
+
+static size_t
+HUF_compress1X_usingCTable_internal(void* dst, size_t dstSize,
+                              const void* src, size_t srcSize,
+                              const HUF_CElt* CTable, const int flags)
+{
+    if (flags & HUF_flags_bmi2) {
+        return HUF_compress1X_usingCTable_internal_bmi2(dst, dstSize, src, srcSize, CTable);
+    }
+    return HUF_compress1X_usingCTable_internal_default(dst, dstSize, src, srcSize, CTable);
+}
+
+#else
+
+static size_t
+HUF_compress1X_usingCTable_internal(void* dst, size_t dstSize,
+                              const void* src, size_t srcSize,
+                              const HUF_CElt* CTable, const int flags)
+{
+    (void)flags;
+    return HUF_compress1X_usingCTable_internal_body(dst, dstSize, src, srcSize, CTable);
+}
+
+#endif
+
+size_t HUF_compress1X_usingCTable(void* dst, size_t dstSize, const void* src, size_t srcSize, const HUF_CElt* CTable, int flags)
+{
+    return HUF_compress1X_usingCTable_internal(dst, dstSize, src, srcSize, CTable, flags);
+}
+
+static size_t
+HUF_compress4X_usingCTable_internal(void* dst, size_t dstSize,
+                              const void* src, size_t srcSize,
+                              const HUF_CElt* CTable, int flags)
+{
+    size_t const segmentSize = (srcSize+3)/4;   /* first 3 segments */
+    const BYTE* ip = (const BYTE*) src;
+    const BYTE* const iend = ip + srcSize;
+    BYTE* const ostart = (BYTE*) dst;
+    BYTE* const oend = ostart + dstSize;
+    BYTE* op = ostart;
+
+    if (dstSize < 6 + 1 + 1 + 1 + 8) return 0;   /* minimum space to compress successfully */
+    if (srcSize < 12) return 0;   /* no saving possible : too small input */
+    op += 6;   /* jumpTable */
+
+    assert(op <= oend);
+    {   CHECK_V_F(cSize, HUF_compress1X_usingCTable_internal(op, (size_t)(oend-op), ip, segmentSize, CTable, flags) );
+        if (cSize == 0 || cSize > 65535) return 0;
+        MEM_writeLE16(ostart, (U16)cSize);
+        op += cSize;
+    }
+
+    ip += segmentSize;
+    assert(op <= oend);
+    {   CHECK_V_F(cSize, HUF_compress1X_usingCTable_internal(op, (size_t)(oend-op), ip, segmentSize, CTable, flags) );
+        if (cSize == 0 || cSize > 65535) return 0;
+        MEM_writeLE16(ostart+2, (U16)cSize);
+        op += cSize;
+    }
+
+    ip += segmentSize;
+    assert(op <= oend);
+    {   CHECK_V_F(cSize, HUF_compress1X_usingCTable_internal(op, (size_t)(oend-op), ip, segmentSize, CTable, flags) );
+        if (cSize == 0 || cSize > 65535) return 0;
+        MEM_writeLE16(ostart+4, (U16)cSize);
+        op += cSize;
+    }
+
+    ip += segmentSize;
+    assert(op <= oend);
+    assert(ip <= iend);
+    {   CHECK_V_F(cSize, HUF_compress1X_usingCTable_internal(op, (size_t)(oend-op), ip, (size_t)(iend-ip), CTable, flags) );
+        if (cSize == 0 || cSize > 65535) return 0;
+        op += cSize;
+    }
+
+    return (size_t)(op-ostart);
+}
+
+size_t HUF_compress4X_usingCTable(void* dst, size_t dstSize, const void* src, size_t srcSize, const HUF_CElt* CTable, int flags)
+{
+    return HUF_compress4X_usingCTable_internal(dst, dstSize, src, srcSize, CTable, flags);
+}
+
+typedef enum { HUF_singleStream, HUF_fourStreams } HUF_nbStreams_e;
+
+static size_t HUF_compressCTable_internal(
+                BYTE* const ostart, BYTE* op, BYTE* const oend,
+                const void* src, size_t srcSize,
+                HUF_nbStreams_e nbStreams, const HUF_CElt* CTable, const int flags)
+{
+    size_t const cSize = (nbStreams==HUF_singleStream) ?
+                         HUF_compress1X_usingCTable_internal(op, (size_t)(oend - op), src, srcSize, CTable, flags) :
+                         HUF_compress4X_usingCTable_internal(op, (size_t)(oend - op), src, srcSize, CTable, flags);
+    if (HUF_isError(cSize)) { return cSize; }
+    if (cSize==0) { return 0; }   /* uncompressible */
+    op += cSize;
+    /* check compressibility */
+    assert(op >= ostart);
+    if ((size_t)(op-ostart) >= srcSize-1) { return 0; }
+    return (size_t)(op-ostart);
+}
+
+typedef struct {
+    unsigned count[HUF_SYMBOLVALUE_MAX + 1];
+    HUF_CElt CTable[HUF_CTABLE_SIZE_ST(HUF_SYMBOLVALUE_MAX)];
+    union {
+        HUF_buildCTable_wksp_tables buildCTable_wksp;
+        HUF_WriteCTableWksp writeCTable_wksp;
+        U32 hist_wksp[HIST_WKSP_SIZE_U32];
+    } wksps;
+} HUF_compress_tables_t;
+
+#define SUSPECT_INCOMPRESSIBLE_SAMPLE_SIZE 4096
+#define SUSPECT_INCOMPRESSIBLE_SAMPLE_RATIO 10  /* Must be >= 2 */
+
+unsigned HUF_cardinality(const unsigned* count, unsigned maxSymbolValue)
+{
+    unsigned cardinality = 0;
+    unsigned i;
+
+    for (i = 0; i < maxSymbolValue + 1; i++) {
+        if (count[i] != 0) cardinality += 1;
+    }
+
+    return cardinality;
+}
+
+unsigned HUF_minTableLog(unsigned symbolCardinality)
+{
+    U32 minBitsSymbols = ZSTD_highbit32(symbolCardinality) + 1;
+    return minBitsSymbols;
+}
+
+unsigned HUF_optimalTableLog(
+            unsigned maxTableLog,
+            size_t srcSize,
+            unsigned maxSymbolValue,
+            void* workSpace, size_t wkspSize,
+            HUF_CElt* table,
+      const unsigned* count,
+            int flags)
+{
+    assert(srcSize > 1); /* Not supported, RLE should be used instead */
+    assert(wkspSize >= sizeof(HUF_buildCTable_wksp_tables));
+
+    if (!(flags & HUF_flags_optimalDepth)) {
+        /* cheap evaluation, based on FSE */
+        return FSE_optimalTableLog_internal(maxTableLog, srcSize, maxSymbolValue, 1);
+    }
+
+    {   BYTE* dst = (BYTE*)workSpace + sizeof(HUF_WriteCTableWksp);
+        size_t dstSize = wkspSize - sizeof(HUF_WriteCTableWksp);
+        size_t hSize, newSize;
+        const unsigned symbolCardinality = HUF_cardinality(count, maxSymbolValue);
+        const unsigned minTableLog = HUF_minTableLog(symbolCardinality);
+        size_t optSize = ((size_t) ~0) - 1;
+        unsigned optLog = maxTableLog, optLogGuess;
+
+        DEBUGLOG(6, "HUF_optimalTableLog: probing huf depth (srcSize=%zu)", srcSize);
+
+        /* Search until size increases */
+        for (optLogGuess = minTableLog; optLogGuess <= maxTableLog; optLogGuess++) {
+            DEBUGLOG(7, "checking for huffLog=%u", optLogGuess);
+
+            {   size_t maxBits = HUF_buildCTable_wksp(table, count, maxSymbolValue, optLogGuess, workSpace, wkspSize);
+                if (ERR_isError(maxBits)) continue;
+
+                if (maxBits < optLogGuess && optLogGuess > minTableLog) break;
+
+                hSize = HUF_writeCTable_wksp(dst, dstSize, table, maxSymbolValue, (U32)maxBits, workSpace, wkspSize);
+            }
+
+            if (ERR_isError(hSize)) continue;
+
+            newSize = HUF_estimateCompressedSize(table, count, maxSymbolValue) + hSize;
+
+            if (newSize > optSize + 1) {
+                break;
+            }
+
+            if (newSize < optSize) {
+                optSize = newSize;
+                optLog = optLogGuess;
+            }
+        }
+        assert(optLog <= HUF_TABLELOG_MAX);
+        return optLog;
+    }
+}
+
+/* HUF_compress_internal() :
+ * `workSpace_align4` must be aligned on 4-bytes boundaries,
+ * and occupies the same space as a table of HUF_WORKSPACE_SIZE_U64 unsigned */
+static size_t
+HUF_compress_internal (void* dst, size_t dstSize,
+                 const void* src, size_t srcSize,
+                       unsigned maxSymbolValue, unsigned huffLog,
+                       HUF_nbStreams_e nbStreams,
+                       void* workSpace, size_t wkspSize,
+                       HUF_CElt* oldHufTable, HUF_repeat* repeat, int flags)
+{
+    HUF_compress_tables_t* const table = (HUF_compress_tables_t*)HUF_alignUpWorkspace(workSpace, &wkspSize, ZSTD_ALIGNOF(size_t));
+    BYTE* const ostart = (BYTE*)dst;
+    BYTE* const oend = ostart + dstSize;
+    BYTE* op = ostart;
+
+    DEBUGLOG(5, "HUF_compress_internal (srcSize=%zu)", srcSize);
+    HUF_STATIC_ASSERT(sizeof(*table) + HUF_WORKSPACE_MAX_ALIGNMENT <= HUF_WORKSPACE_SIZE);
+
+    /* checks & inits */
+    if (wkspSize < sizeof(*table)) return ERROR(workSpace_tooSmall);
+    if (!srcSize) return 0;  /* Uncompressed */
+    if (!dstSize) return 0;  /* cannot fit anything within dst budget */
+    if (srcSize > HUF_BLOCKSIZE_MAX) return ERROR(srcSize_wrong);   /* current block size limit */
+    if (huffLog > HUF_TABLELOG_MAX) return ERROR(tableLog_tooLarge);
+    if (maxSymbolValue > HUF_SYMBOLVALUE_MAX) return ERROR(maxSymbolValue_tooLarge);
+    if (!maxSymbolValue) maxSymbolValue = HUF_SYMBOLVALUE_MAX;
+    if (!huffLog) huffLog = HUF_TABLELOG_DEFAULT;
+
+    /* Heuristic : If old table is valid, use it for small inputs */
+    if ((flags & HUF_flags_preferRepeat) && repeat && *repeat == HUF_repeat_valid) {
+        return HUF_compressCTable_internal(ostart, op, oend,
+                                           src, srcSize,
+                                           nbStreams, oldHufTable, flags);
+    }
+
+    /* If uncompressible data is suspected, do a smaller sampling first */
+    DEBUG_STATIC_ASSERT(SUSPECT_INCOMPRESSIBLE_SAMPLE_RATIO >= 2);
+    if ((flags & HUF_flags_suspectUncompressible) && srcSize >= (SUSPECT_INCOMPRESSIBLE_SAMPLE_SIZE * SUSPECT_INCOMPRESSIBLE_SAMPLE_RATIO)) {
+        size_t largestTotal = 0;
+        DEBUGLOG(5, "input suspected incompressible : sampling to check");
+        {   unsigned maxSymbolValueBegin = maxSymbolValue;
+            CHECK_V_F(largestBegin, HIST_count_simple (table->count, &maxSymbolValueBegin, (const BYTE*)src, SUSPECT_INCOMPRESSIBLE_SAMPLE_SIZE) );
+            largestTotal += largestBegin;
+        }
+        {   unsigned maxSymbolValueEnd = maxSymbolValue;
+            CHECK_V_F(largestEnd, HIST_count_simple (table->count, &maxSymbolValueEnd, (const BYTE*)src + srcSize - SUSPECT_INCOMPRESSIBLE_SAMPLE_SIZE, SUSPECT_INCOMPRESSIBLE_SAMPLE_SIZE) );
+            largestTotal += largestEnd;
+        }
+        if (largestTotal <= ((2 * SUSPECT_INCOMPRESSIBLE_SAMPLE_SIZE) >> 7)+4) return 0;   /* heuristic : probably not compressible enough */
+    }
+
+    /* Scan input and build symbol stats */
+    {   CHECK_V_F(largest, HIST_count_wksp (table->count, &maxSymbolValue, (const BYTE*)src, srcSize, table->wksps.hist_wksp, sizeof(table->wksps.hist_wksp)) );
+        if (largest == srcSize) { *ostart = ((const BYTE*)src)[0]; return 1; }   /* single symbol, rle */
+        if (largest <= (srcSize >> 7)+4) return 0;   /* heuristic : probably not compressible enough */
+    }
+    DEBUGLOG(6, "histogram detail completed (%zu symbols)", showU32(table->count, maxSymbolValue+1));
+
+    /* Check validity of previous table */
+    if ( repeat
+      && *repeat == HUF_repeat_check
+      && !HUF_validateCTable(oldHufTable, table->count, maxSymbolValue)) {
+        *repeat = HUF_repeat_none;
+    }
+    /* Heuristic : use existing table for small inputs */
+    if ((flags & HUF_flags_preferRepeat) && repeat && *repeat != HUF_repeat_none) {
+        return HUF_compressCTable_internal(ostart, op, oend,
+                                           src, srcSize,
+                                           nbStreams, oldHufTable, flags);
+    }
+
+    /* Build Huffman Tree */
+    huffLog = HUF_optimalTableLog(huffLog, srcSize, maxSymbolValue, &table->wksps, sizeof(table->wksps), table->CTable, table->count, flags);
+    {   size_t const maxBits = HUF_buildCTable_wksp(table->CTable, table->count,
+                                            maxSymbolValue, huffLog,
+                                            &table->wksps.buildCTable_wksp, sizeof(table->wksps.buildCTable_wksp));
+        CHECK_F(maxBits);
+        huffLog = (U32)maxBits;
+        DEBUGLOG(6, "bit distribution completed (%zu symbols)", showCTableBits(table->CTable + 1, maxSymbolValue+1));
+    }
+
+    /* Write table description header */
+    {   CHECK_V_F(hSize, HUF_writeCTable_wksp(op, dstSize, table->CTable, maxSymbolValue, huffLog,
+                                              &table->wksps.writeCTable_wksp, sizeof(table->wksps.writeCTable_wksp)) );
+        /* Check if using previous huffman table is beneficial */
+        if (repeat && *repeat != HUF_repeat_none) {
+            size_t const oldSize = HUF_estimateCompressedSize(oldHufTable, table->count, maxSymbolValue);
+            size_t const newSize = HUF_estimateCompressedSize(table->CTable, table->count, maxSymbolValue);
+            if (oldSize <= hSize + newSize || hSize + 12 >= srcSize) {
+                return HUF_compressCTable_internal(ostart, op, oend,
+                                                   src, srcSize,
+                                                   nbStreams, oldHufTable, flags);
+        }   }
+
+        /* Use the new huffman table */
+        if (hSize + 12ul >= srcSize) { return 0; }
+        op += hSize;
+        if (repeat) { *repeat = HUF_repeat_none; }
+        if (oldHufTable)
+            ZSTD_memcpy(oldHufTable, table->CTable, sizeof(table->CTable));  /* Save new table */
+    }
+    return HUF_compressCTable_internal(ostart, op, oend,
+                                       src, srcSize,
+                                       nbStreams, table->CTable, flags);
+}
+
+size_t HUF_compress1X_repeat (void* dst, size_t dstSize,
+                      const void* src, size_t srcSize,
+                      unsigned maxSymbolValue, unsigned huffLog,
+                      void* workSpace, size_t wkspSize,
+                      HUF_CElt* hufTable, HUF_repeat* repeat, int flags)
+{
+    DEBUGLOG(5, "HUF_compress1X_repeat (srcSize = %zu)", srcSize);
+    return HUF_compress_internal(dst, dstSize, src, srcSize,
+                                 maxSymbolValue, huffLog, HUF_singleStream,
+                                 workSpace, wkspSize, hufTable,
+                                 repeat, flags);
+}
+
+/* HUF_compress4X_repeat():
+ * compress input using 4 streams.
+ * consider skipping quickly
+ * reuse an existing huffman compression table */
+size_t HUF_compress4X_repeat (void* dst, size_t dstSize,
+                      const void* src, size_t srcSize,
+                      unsigned maxSymbolValue, unsigned huffLog,
+                      void* workSpace, size_t wkspSize,
+                      HUF_CElt* hufTable, HUF_repeat* repeat, int flags)
+{
+    DEBUGLOG(5, "HUF_compress4X_repeat (srcSize = %zu)", srcSize);
+    return HUF_compress_internal(dst, dstSize, src, srcSize,
+                                 maxSymbolValue, huffLog, HUF_fourStreams,
+                                 workSpace, wkspSize,
+                                 hufTable, repeat, flags);
+}
diff --git a/src/commonlib/bsd/zstd/compress/zstd_compress.c b/src/commonlib/bsd/zstd/compress/zstd_compress.c
new file mode 100644
index 0000000000..7cf21cc5cb
--- /dev/null
+++ b/src/commonlib/bsd/zstd/compress/zstd_compress.c
@@ -0,0 +1,6046 @@
+/* SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0-only */
+
+/*
+ * Copyright (c) Meta Platforms, Inc. and affiliates.
+ * All rights reserved.
+ *
+ * This source code is licensed under both the BSD-style license (found in the
+ * LICENSE file in the root directory of this source tree) and the GPLv2 (found
+ * in the COPYING file in the root directory of this source tree).
+ * You may select, at your option, one of the above-listed licenses.
+ */
+
+/*-*************************************
+*  Dependencies
+***************************************/
+#include "../common/allocations.h"  /* ZSTD_customMalloc, ZSTD_customCalloc, ZSTD_customFree */
+#include "../common/zstd_deps.h"  /* INT_MAX, ZSTD_memset, ZSTD_memcpy */
+#include "../common/mem.h"
+#include "../common/error_private.h"
+#include "hist.h"           /* HIST_countFast_wksp */
+#define FSE_STATIC_LINKING_ONLY   /* FSE_encodeSymbol */
+#include "../common/fse.h"
+#include "../common/huf.h"
+#include "zstd_compress_internal.h"
+#include "zstd_compress_sequences.h"
+#include "zstd_compress_literals.h"
+#include "zstd_fast.h"
+#include "zstd_double_fast.h"
+#include "zstd_lazy.h"
+#include "zstd_opt.h"
+#include "zstd_ldm.h"
+#include "zstd_compress_superblock.h"
+#include  "../common/zstd_bits.h"      /* ZSTD_highbit32, ZSTD_rotateRight_U64 */
+
+/* ***************************************************************
+*  Tuning parameters
+*****************************************************************/
+/*!
+ * COMPRESS_HEAPMODE :
+ * Select how default decompression function ZSTD_compress() allocates its context,
+ * on stack (0, default), or into heap (1).
+ * Note that functions with explicit context such as ZSTD_compressCCtx() are unaffected.
+ */
+#ifndef ZSTD_COMPRESS_HEAPMODE
+#  define ZSTD_COMPRESS_HEAPMODE 0
+#endif
+
+/*!
+ * ZSTD_HASHLOG3_MAX :
+ * Maximum size of the hash table dedicated to find 3-bytes matches,
+ * in log format, aka 17 => 1 << 17 == 128Ki positions.
+ * This structure is only used in zstd_opt.
+ * Since allocation is centralized for all strategies, it has to be known here.
+ * The actual (selected) size of the hash table is then stored in ZSTD_MatchState_t.hashLog3,
+ * so that zstd_opt.c doesn't need to know about this constant.
+ */
+#ifndef ZSTD_HASHLOG3_MAX
+#  define ZSTD_HASHLOG3_MAX 17
+#endif
+
+/*-*************************************
+*  Helper functions
+***************************************/
+/* ZSTD_compressBound()
+ * Note that the result from this function is only valid for
+ * the one-pass compression functions.
+ * When employing the streaming mode,
+ * if flushes are frequently altering the size of blocks,
+ * the overhead from block headers can make the compressed data larger
+ * than the return value of ZSTD_compressBound().
+ */
+size_t ZSTD_compressBound(size_t srcSize) {
+    size_t const r = ZSTD_COMPRESSBOUND(srcSize);
+    if (r==0) return ERROR(srcSize_wrong);
+    return r;
+}
+
+
+/*-*************************************
+*  Context memory management
+***************************************/
+struct ZSTD_CDict_s {
+    const void* dictContent;
+    size_t dictContentSize;
+    ZSTD_dictContentType_e dictContentType; /* The dictContentType the CDict was created with */
+    U32* entropyWorkspace; /* entropy workspace of HUF_WORKSPACE_SIZE bytes */
+    ZSTD_cwksp workspace;
+    ZSTD_MatchState_t matchState;
+    ZSTD_compressedBlockState_t cBlockState;
+    ZSTD_customMem customMem;
+    U32 dictID;
+    int compressionLevel; /* 0 indicates that advanced API was used to select CDict params */
+    ZSTD_ParamSwitch_e useRowMatchFinder; /* Indicates whether the CDict was created with params that would use
+                                           * row-based matchfinder. Unless the cdict is reloaded, we will use
+                                           * the same greedy/lazy matchfinder at compression time.
+                                           */
+};  /* typedef'd to ZSTD_CDict within "zstd.h" */
+
+ZSTD_CCtx* ZSTD_createCCtx(void)
+{
+    return ZSTD_createCCtx_advanced(ZSTD_defaultCMem);
+}
+
+static void ZSTD_initCCtx(ZSTD_CCtx* cctx, ZSTD_customMem memManager)
+{
+    assert(cctx != NULL);
+    ZSTD_memset(cctx, 0, sizeof(*cctx));
+    cctx->customMem = memManager;
+    cctx->bmi2 = ZSTD_cpuSupportsBmi2();
+    {   size_t const err = ZSTD_CCtx_reset(cctx, ZSTD_reset_parameters);
+        assert(!ZSTD_isError(err));
+        (void)err;
+    }
+}
+
+ZSTD_CCtx* ZSTD_createCCtx_advanced(ZSTD_customMem customMem)
+{
+    ZSTD_STATIC_ASSERT(zcss_init==0);
+    ZSTD_STATIC_ASSERT(ZSTD_CONTENTSIZE_UNKNOWN==(0ULL - 1));
+    if ((!customMem.customAlloc) ^ (!customMem.customFree)) return NULL;
+    {   ZSTD_CCtx* const cctx = (ZSTD_CCtx*)ZSTD_customMalloc(sizeof(ZSTD_CCtx), customMem);
+        if (!cctx) return NULL;
+        ZSTD_initCCtx(cctx, customMem);
+        return cctx;
+    }
+}
+
+ZSTD_CCtx* ZSTD_initStaticCCtx(void* workspace, size_t workspaceSize)
+{
+    ZSTD_cwksp ws;
+    ZSTD_CCtx* cctx;
+    if (workspaceSize <= sizeof(ZSTD_CCtx)) return NULL;  /* minimum size */
+    if ((size_t)workspace & 7) return NULL;  /* must be 8-aligned */
+    ZSTD_cwksp_init(&ws, workspace, workspaceSize, ZSTD_cwksp_static_alloc);
+
+    cctx = (ZSTD_CCtx*)ZSTD_cwksp_reserve_object(&ws, sizeof(ZSTD_CCtx));
+    if (cctx == NULL) return NULL;
+
+    ZSTD_memset(cctx, 0, sizeof(ZSTD_CCtx));
+    ZSTD_cwksp_move(&cctx->workspace, &ws);
+    cctx->staticSize = workspaceSize;
+
+    /* statically sized space. tmpWorkspace never moves (but prev/next block swap places) */
+    if (!ZSTD_cwksp_check_available(&cctx->workspace, TMP_WORKSPACE_SIZE + 2 * sizeof(ZSTD_compressedBlockState_t))) return NULL;
+    cctx->blockState.prevCBlock = (ZSTD_compressedBlockState_t*)ZSTD_cwksp_reserve_object(&cctx->workspace, sizeof(ZSTD_compressedBlockState_t));
+    cctx->blockState.nextCBlock = (ZSTD_compressedBlockState_t*)ZSTD_cwksp_reserve_object(&cctx->workspace, sizeof(ZSTD_compressedBlockState_t));
+    cctx->tmpWorkspace = ZSTD_cwksp_reserve_object(&cctx->workspace, TMP_WORKSPACE_SIZE);
+    cctx->tmpWkspSize = TMP_WORKSPACE_SIZE;
+    cctx->bmi2 = ZSTD_cpuid_bmi2(ZSTD_cpuid());
+    return cctx;
+}
+
+/**
+ * Clears and frees all of the dictionaries in the CCtx.
+ */
+static void ZSTD_clearAllDicts(ZSTD_CCtx* cctx)
+{
+    ZSTD_customFree(cctx->localDict.dictBuffer, cctx->customMem);
+    ZSTD_freeCDict(cctx->localDict.cdict);
+    ZSTD_memset(&cctx->localDict, 0, sizeof(cctx->localDict));
+    ZSTD_memset(&cctx->prefixDict, 0, sizeof(cctx->prefixDict));
+    cctx->cdict = NULL;
+}
+
+static size_t ZSTD_sizeof_localDict(ZSTD_localDict dict)
+{
+    size_t const bufferSize = dict.dictBuffer != NULL ? dict.dictSize : 0;
+    size_t const cdictSize = ZSTD_sizeof_CDict(dict.cdict);
+    return bufferSize + cdictSize;
+}
+
+static void ZSTD_freeCCtxContent(ZSTD_CCtx* cctx)
+{
+    assert(cctx != NULL);
+    assert(cctx->staticSize == 0);
+    ZSTD_clearAllDicts(cctx);
+#ifdef ZSTD_MULTITHREAD
+    ZSTDMT_freeCCtx(cctx->mtctx); cctx->mtctx = NULL;
+#endif
+    ZSTD_cwksp_free(&cctx->workspace, cctx->customMem);
+}
+
+size_t ZSTD_freeCCtx(ZSTD_CCtx* cctx)
+{
+    DEBUGLOG(3, "ZSTD_freeCCtx (address: %p)", (void*)cctx);
+    if (cctx==NULL) return 0;   /* support free on NULL */
+    RETURN_ERROR_IF(cctx->staticSize, memory_allocation,
+                    "not compatible with static CCtx");
+    {   int cctxInWorkspace = ZSTD_cwksp_owns_buffer(&cctx->workspace, cctx);
+        ZSTD_freeCCtxContent(cctx);
+        if (!cctxInWorkspace) ZSTD_customFree(cctx, cctx->customMem);
+    }
+    return 0;
+}
+
+
+static size_t ZSTD_sizeof_mtctx(const ZSTD_CCtx* cctx)
+{
+#ifdef ZSTD_MULTITHREAD
+    return ZSTDMT_sizeof_CCtx(cctx->mtctx);
+#else
+    (void)cctx;
+    return 0;
+#endif
+}
+
+
+size_t ZSTD_sizeof_CCtx(const ZSTD_CCtx* cctx)
+{
+    if (cctx==NULL) return 0;   /* support sizeof on NULL */
+    /* cctx may be in the workspace */
+    return (cctx->workspace.workspace == cctx ? 0 : sizeof(*cctx))
+           + ZSTD_cwksp_sizeof(&cctx->workspace)
+           + ZSTD_sizeof_localDict(cctx->localDict)
+           + ZSTD_sizeof_mtctx(cctx);
+}
+
+/* private API call, for dictBuilder only */
+const SeqStore_t* ZSTD_getSeqStore(const ZSTD_CCtx* ctx) { return &(ctx->seqStore); }
+
+/* Returns true if the strategy supports using a row based matchfinder */
+static int ZSTD_rowMatchFinderSupported(const ZSTD_strategy strategy) {
+    return (strategy >= ZSTD_greedy && strategy <= ZSTD_lazy2);
+}
+
+/* Returns true if the strategy and useRowMatchFinder mode indicate that we will use the row based matchfinder
+ * for this compression.
+ */
+static int ZSTD_rowMatchFinderUsed(const ZSTD_strategy strategy, const ZSTD_ParamSwitch_e mode) {
+    assert(mode != ZSTD_ps_auto);
+    return ZSTD_rowMatchFinderSupported(strategy) && (mode == ZSTD_ps_enable);
+}
+
+/* Returns row matchfinder usage given an initial mode and cParams */
+static ZSTD_ParamSwitch_e ZSTD_resolveRowMatchFinderMode(ZSTD_ParamSwitch_e mode,
+                                                         const ZSTD_compressionParameters* const cParams) {
+    if (mode != ZSTD_ps_auto) return mode; /* if requested enabled, but no SIMD, we still will use row matchfinder */
+    mode = ZSTD_ps_disable;
+    if (!ZSTD_rowMatchFinderSupported(cParams->strategy)) return mode;
+    if (cParams->windowLog > 14) mode = ZSTD_ps_enable;
+    return mode;
+}
+
+/* Returns block splitter usage (generally speaking, when using slower/stronger compression modes) */
+static ZSTD_ParamSwitch_e ZSTD_resolveBlockSplitterMode(ZSTD_ParamSwitch_e mode,
+                                                        const ZSTD_compressionParameters* const cParams) {
+    if (mode != ZSTD_ps_auto) return mode;
+    return (cParams->strategy >= ZSTD_btopt && cParams->windowLog >= 17) ? ZSTD_ps_enable : ZSTD_ps_disable;
+}
+
+/* Returns 1 if the arguments indicate that we should allocate a chainTable, 0 otherwise */
+static int ZSTD_allocateChainTable(const ZSTD_strategy strategy,
+                                   const ZSTD_ParamSwitch_e useRowMatchFinder,
+                                   const U32 forDDSDict) {
+    assert(useRowMatchFinder != ZSTD_ps_auto);
+    /* We always should allocate a chaintable if we are allocating a matchstate for a DDS dictionary matchstate.
+     * We do not allocate a chaintable if we are using ZSTD_fast, or are using the row-based matchfinder.
+     */
+    return forDDSDict || ((strategy != ZSTD_fast) && !ZSTD_rowMatchFinderUsed(strategy, useRowMatchFinder));
+}
+
+/* Returns ZSTD_ps_enable if compression parameters are such that we should
+ * enable long distance matching (wlog >= 27, strategy >= btopt).
+ * Returns ZSTD_ps_disable otherwise.
+ */
+static ZSTD_ParamSwitch_e ZSTD_resolveEnableLdm(ZSTD_ParamSwitch_e mode,
+                                 const ZSTD_compressionParameters* const cParams) {
+    if (mode != ZSTD_ps_auto) return mode;
+    return (cParams->strategy >= ZSTD_btopt && cParams->windowLog >= 27) ? ZSTD_ps_enable : ZSTD_ps_disable;
+}
+
+static int ZSTD_resolveExternalSequenceValidation(int mode) {
+    return mode;
+}
+
+/* Resolves maxBlockSize to the default if no value is present. */
+static size_t ZSTD_resolveMaxBlockSize(size_t maxBlockSize) {
+    if (maxBlockSize == 0) {
+        return ZSTD_BLOCKSIZE_MAX;
+    } else {
+        return maxBlockSize;
+    }
+}
+
+static ZSTD_ParamSwitch_e ZSTD_resolveExternalRepcodeSearch(ZSTD_ParamSwitch_e value, int cLevel) {
+    if (value != ZSTD_ps_auto) return value;
+    if (cLevel < 10) {
+        return ZSTD_ps_disable;
+    } else {
+        return ZSTD_ps_enable;
+    }
+}
+
+/* Returns 1 if compression parameters are such that CDict hashtable and chaintable indices are tagged.
+ * If so, the tags need to be removed in ZSTD_resetCCtx_byCopyingCDict. */
+static int ZSTD_CDictIndicesAreTagged(const ZSTD_compressionParameters* const cParams) {
+    return cParams->strategy == ZSTD_fast || cParams->strategy == ZSTD_dfast;
+}
+
+static ZSTD_CCtx_params ZSTD_makeCCtxParamsFromCParams(
+        ZSTD_compressionParameters cParams)
+{
+    ZSTD_CCtx_params cctxParams;
+    /* should not matter, as all cParams are presumed properly defined */
+    ZSTD_CCtxParams_init(&cctxParams, ZSTD_CLEVEL_DEFAULT);
+    cctxParams.cParams = cParams;
+
+    /* Adjust advanced params according to cParams */
+    cctxParams.ldmParams.enableLdm = ZSTD_resolveEnableLdm(cctxParams.ldmParams.enableLdm, &cParams);
+    if (cctxParams.ldmParams.enableLdm == ZSTD_ps_enable) {
+        ZSTD_ldm_adjustParameters(&cctxParams.ldmParams, &cParams);
+        assert(cctxParams.ldmParams.hashLog >= cctxParams.ldmParams.bucketSizeLog);
+        assert(cctxParams.ldmParams.hashRateLog < 32);
+    }
+    cctxParams.postBlockSplitter = ZSTD_resolveBlockSplitterMode(cctxParams.postBlockSplitter, &cParams);
+    cctxParams.useRowMatchFinder = ZSTD_resolveRowMatchFinderMode(cctxParams.useRowMatchFinder, &cParams);
+    cctxParams.validateSequences = ZSTD_resolveExternalSequenceValidation(cctxParams.validateSequences);
+    cctxParams.maxBlockSize = ZSTD_resolveMaxBlockSize(cctxParams.maxBlockSize);
+    cctxParams.searchForExternalRepcodes = ZSTD_resolveExternalRepcodeSearch(cctxParams.searchForExternalRepcodes,
+                                                                             cctxParams.compressionLevel);
+    assert(!ZSTD_checkCParams(cParams));
+    return cctxParams;
+}
+
+static ZSTD_CCtx_params* ZSTD_createCCtxParams_advanced(
+        ZSTD_customMem customMem)
+{
+    ZSTD_CCtx_params* params;
+    if ((!customMem.customAlloc) ^ (!customMem.customFree)) return NULL;
+    params = (ZSTD_CCtx_params*)ZSTD_customCalloc(
+            sizeof(ZSTD_CCtx_params), customMem);
+    if (!params) { return NULL; }
+    ZSTD_CCtxParams_init(params, ZSTD_CLEVEL_DEFAULT);
+    params->customMem = customMem;
+    return params;
+}
+
+ZSTD_CCtx_params* ZSTD_createCCtxParams(void)
+{
+    return ZSTD_createCCtxParams_advanced(ZSTD_defaultCMem);
+}
+
+size_t ZSTD_freeCCtxParams(ZSTD_CCtx_params* params)
+{
+    if (params == NULL) { return 0; }
+    ZSTD_customFree(params, params->customMem);
+    return 0;
+}
+
+size_t ZSTD_CCtxParams_reset(ZSTD_CCtx_params* params)
+{
+    return ZSTD_CCtxParams_init(params, ZSTD_CLEVEL_DEFAULT);
+}
+
+size_t ZSTD_CCtxParams_init(ZSTD_CCtx_params* cctxParams, int compressionLevel) {
+    RETURN_ERROR_IF(!cctxParams, GENERIC, "NULL pointer!");
+    ZSTD_memset(cctxParams, 0, sizeof(*cctxParams));
+    cctxParams->compressionLevel = compressionLevel;
+    cctxParams->fParams.contentSizeFlag = 1;
+    return 0;
+}
+
+#define ZSTD_NO_CLEVEL 0
+
+/**
+ * Initializes `cctxParams` from `params` and `compressionLevel`.
+ * @param compressionLevel If params are derived from a compression level then that compression level, otherwise ZSTD_NO_CLEVEL.
+ */
+static void
+ZSTD_CCtxParams_init_internal(ZSTD_CCtx_params* cctxParams,
+                        const ZSTD_parameters* params,
+                              int compressionLevel)
+{
+    assert(!ZSTD_checkCParams(params->cParams));
+    ZSTD_memset(cctxParams, 0, sizeof(*cctxParams));
+    cctxParams->cParams = params->cParams;
+    cctxParams->fParams = params->fParams;
+    /* Should not matter, as all cParams are presumed properly defined.
+     * But, set it for tracing anyway.
+     */
+    cctxParams->compressionLevel = compressionLevel;
+    cctxParams->useRowMatchFinder = ZSTD_resolveRowMatchFinderMode(cctxParams->useRowMatchFinder, &params->cParams);
+    cctxParams->postBlockSplitter = ZSTD_resolveBlockSplitterMode(cctxParams->postBlockSplitter, &params->cParams);
+    cctxParams->ldmParams.enableLdm = ZSTD_resolveEnableLdm(cctxParams->ldmParams.enableLdm, &params->cParams);
+    cctxParams->validateSequences = ZSTD_resolveExternalSequenceValidation(cctxParams->validateSequences);
+    cctxParams->maxBlockSize = ZSTD_resolveMaxBlockSize(cctxParams->maxBlockSize);
+    cctxParams->searchForExternalRepcodes = ZSTD_resolveExternalRepcodeSearch(cctxParams->searchForExternalRepcodes, compressionLevel);
+    DEBUGLOG(4, "ZSTD_CCtxParams_init_internal: useRowMatchFinder=%d, useBlockSplitter=%d ldm=%d",
+                cctxParams->useRowMatchFinder, cctxParams->postBlockSplitter, cctxParams->ldmParams.enableLdm);
+}
+
+size_t ZSTD_CCtxParams_init_advanced(ZSTD_CCtx_params* cctxParams, ZSTD_parameters params)
+{
+    RETURN_ERROR_IF(!cctxParams, GENERIC, "NULL pointer!");
+    FORWARD_IF_ERROR( ZSTD_checkCParams(params.cParams) , "");
+    ZSTD_CCtxParams_init_internal(cctxParams, &params, ZSTD_NO_CLEVEL);
+    return 0;
+}
+
+ZSTD_bounds ZSTD_cParam_getBounds(ZSTD_cParameter param)
+{
+    ZSTD_bounds bounds = { 0, 0, 0 };
+
+    switch(param)
+    {
+    case ZSTD_c_compressionLevel:
+        bounds.lowerBound = ZSTD_minCLevel();
+        bounds.upperBound = ZSTD_maxCLevel();
+        return bounds;
+
+    case ZSTD_c_windowLog:
+        bounds.lowerBound = ZSTD_WINDOWLOG_MIN;
+        bounds.upperBound = ZSTD_WINDOWLOG_MAX;
+        return bounds;
+
+    case ZSTD_c_hashLog:
+        bounds.lowerBound = ZSTD_HASHLOG_MIN;
+        bounds.upperBound = ZSTD_HASHLOG_MAX;
+        return bounds;
+
+    case ZSTD_c_chainLog:
+        bounds.lowerBound = ZSTD_CHAINLOG_MIN;
+        bounds.upperBound = ZSTD_CHAINLOG_MAX;
+        return bounds;
+
+    case ZSTD_c_searchLog:
+        bounds.lowerBound = ZSTD_SEARCHLOG_MIN;
+        bounds.upperBound = ZSTD_SEARCHLOG_MAX;
+        return bounds;
+
+    case ZSTD_c_minMatch:
+        bounds.lowerBound = ZSTD_MINMATCH_MIN;
+        bounds.upperBound = ZSTD_MINMATCH_MAX;
+        return bounds;
+
+    case ZSTD_c_targetLength:
+        bounds.lowerBound = ZSTD_TARGETLENGTH_MIN;
+        bounds.upperBound = ZSTD_TARGETLENGTH_MAX;
+        return bounds;
+
+    case ZSTD_c_strategy:
+        bounds.lowerBound = ZSTD_STRATEGY_MIN;
+        bounds.upperBound = ZSTD_STRATEGY_MAX;
+        return bounds;
+
+    case ZSTD_c_contentSizeFlag:
+        bounds.lowerBound = 0;
+        bounds.upperBound = 1;
+        return bounds;
+
+    case ZSTD_c_checksumFlag:
+        bounds.lowerBound = 0;
+        bounds.upperBound = 1;
+        return bounds;
+
+    case ZSTD_c_dictIDFlag:
+        bounds.lowerBound = 0;
+        bounds.upperBound = 1;
+        return bounds;
+
+    case ZSTD_c_nbWorkers:
+        bounds.lowerBound = 0;
+#ifdef ZSTD_MULTITHREAD
+        bounds.upperBound = ZSTDMT_NBWORKERS_MAX;
+#else
+        bounds.upperBound = 0;
+#endif
+        return bounds;
+
+    case ZSTD_c_jobSize:
+        bounds.lowerBound = 0;
+#ifdef ZSTD_MULTITHREAD
+        bounds.upperBound = ZSTDMT_JOBSIZE_MAX;
+#else
+        bounds.upperBound = 0;
+#endif
+        return bounds;
+
+    case ZSTD_c_overlapLog:
+#ifdef ZSTD_MULTITHREAD
+        bounds.lowerBound = ZSTD_OVERLAPLOG_MIN;
+        bounds.upperBound = ZSTD_OVERLAPLOG_MAX;
+#else
+        bounds.lowerBound = 0;
+        bounds.upperBound = 0;
+#endif
+        return bounds;
+
+    case ZSTD_c_enableDedicatedDictSearch:
+        bounds.lowerBound = 0;
+        bounds.upperBound = 1;
+        return bounds;
+
+    case ZSTD_c_enableLongDistanceMatching:
+        bounds.lowerBound = (int)ZSTD_ps_auto;
+        bounds.upperBound = (int)ZSTD_ps_disable;
+        return bounds;
+
+    case ZSTD_c_ldmHashLog:
+        bounds.lowerBound = ZSTD_LDM_HASHLOG_MIN;
+        bounds.upperBound = ZSTD_LDM_HASHLOG_MAX;
+        return bounds;
+
+    case ZSTD_c_ldmMinMatch:
+        bounds.lowerBound = ZSTD_LDM_MINMATCH_MIN;
+        bounds.upperBound = ZSTD_LDM_MINMATCH_MAX;
+        return bounds;
+
+    case ZSTD_c_ldmBucketSizeLog:
+        bounds.lowerBound = ZSTD_LDM_BUCKETSIZELOG_MIN;
+        bounds.upperBound = ZSTD_LDM_BUCKETSIZELOG_MAX;
+        return bounds;
+
+    case ZSTD_c_ldmHashRateLog:
+        bounds.lowerBound = ZSTD_LDM_HASHRATELOG_MIN;
+        bounds.upperBound = ZSTD_LDM_HASHRATELOG_MAX;
+        return bounds;
+
+    /* experimental parameters */
+    case ZSTD_c_rsyncable:
+        bounds.lowerBound = 0;
+        bounds.upperBound = 1;
+        return bounds;
+
+    case ZSTD_c_forceMaxWindow :
+        bounds.lowerBound = 0;
+        bounds.upperBound = 1;
+        return bounds;
+
+    case ZSTD_c_format:
+        ZSTD_STATIC_ASSERT(ZSTD_f_zstd1 < ZSTD_f_zstd1_magicless);
+        bounds.lowerBound = ZSTD_f_zstd1;
+        bounds.upperBound = ZSTD_f_zstd1_magicless;   /* note : how to ensure at compile time that this is the highest value enum ? */
+        return bounds;
+
+    case ZSTD_c_forceAttachDict:
+        ZSTD_STATIC_ASSERT(ZSTD_dictDefaultAttach < ZSTD_dictForceLoad);
+        bounds.lowerBound = ZSTD_dictDefaultAttach;
+        bounds.upperBound = ZSTD_dictForceLoad;       /* note : how to ensure at compile time that this is the highest value enum ? */
+        return bounds;
+
+    case ZSTD_c_literalCompressionMode:
+        ZSTD_STATIC_ASSERT(ZSTD_ps_auto < ZSTD_ps_enable && ZSTD_ps_enable < ZSTD_ps_disable);
+        bounds.lowerBound = (int)ZSTD_ps_auto;
+        bounds.upperBound = (int)ZSTD_ps_disable;
+        return bounds;
+
+    case ZSTD_c_targetCBlockSize:
+        bounds.lowerBound = ZSTD_TARGETCBLOCKSIZE_MIN;
+        bounds.upperBound = ZSTD_TARGETCBLOCKSIZE_MAX;
+        return bounds;
+
+    case ZSTD_c_srcSizeHint:
+        bounds.lowerBound = ZSTD_SRCSIZEHINT_MIN;
+        bounds.upperBound = ZSTD_SRCSIZEHINT_MAX;
+        return bounds;
+
+    case ZSTD_c_stableInBuffer:
+    case ZSTD_c_stableOutBuffer:
+        bounds.lowerBound = (int)ZSTD_bm_buffered;
+        bounds.upperBound = (int)ZSTD_bm_stable;
+        return bounds;
+
+    case ZSTD_c_blockDelimiters:
+        bounds.lowerBound = (int)ZSTD_sf_noBlockDelimiters;
+        bounds.upperBound = (int)ZSTD_sf_explicitBlockDelimiters;
+        return bounds;
+
+    case ZSTD_c_validateSequences:
+        bounds.lowerBound = 0;
+        bounds.upperBound = 1;
+        return bounds;
+
+    case ZSTD_c_splitAfterSequences:
+        bounds.lowerBound = (int)ZSTD_ps_auto;
+        bounds.upperBound = (int)ZSTD_ps_disable;
+        return bounds;
+
+    case ZSTD_c_blockSplitterLevel:
+        bounds.lowerBound = 0;
+        bounds.upperBound = ZSTD_BLOCKSPLITTER_LEVEL_MAX;
+        return bounds;
+
+    case ZSTD_c_useRowMatchFinder:
+        bounds.lowerBound = (int)ZSTD_ps_auto;
+        bounds.upperBound = (int)ZSTD_ps_disable;
+        return bounds;
+
+    case ZSTD_c_deterministicRefPrefix:
+        bounds.lowerBound = 0;
+        bounds.upperBound = 1;
+        return bounds;
+
+    case ZSTD_c_prefetchCDictTables:
+        bounds.lowerBound = (int)ZSTD_ps_auto;
+        bounds.upperBound = (int)ZSTD_ps_disable;
+        return bounds;
+
+    case ZSTD_c_enableSeqProducerFallback:
+        bounds.lowerBound = 0;
+        bounds.upperBound = 1;
+        return bounds;
+
+    case ZSTD_c_maxBlockSize:
+        bounds.lowerBound = ZSTD_BLOCKSIZE_MAX_MIN;
+        bounds.upperBound = ZSTD_BLOCKSIZE_MAX;
+        return bounds;
+
+    case ZSTD_c_repcodeResolution:
+        bounds.lowerBound = (int)ZSTD_ps_auto;
+        bounds.upperBound = (int)ZSTD_ps_disable;
+        return bounds;
+
+    default:
+        bounds.error = ERROR(parameter_unsupported);
+        return bounds;
+    }
+}
+
+/* ZSTD_cParam_clampBounds:
+ * Clamps the value into the bounded range.
+ */
+static size_t ZSTD_cParam_clampBounds(ZSTD_cParameter cParam, int* value)
+{
+    ZSTD_bounds const bounds = ZSTD_cParam_getBounds(cParam);
+    if (ZSTD_isError(bounds.error)) return bounds.error;
+    if (*value < bounds.lowerBound) *value = bounds.lowerBound;
+    if (*value > bounds.upperBound) *value = bounds.upperBound;
+    return 0;
+}
+
+#define BOUNDCHECK(cParam, val)                                       \
+    do {                                                              \
+        RETURN_ERROR_IF(!ZSTD_cParam_withinBounds(cParam,val),        \
+                        parameter_outOfBound, "Param out of bounds"); \
+    } while (0)
+
+
+static int ZSTD_isUpdateAuthorized(ZSTD_cParameter param)
+{
+    switch(param)
+    {
+    case ZSTD_c_compressionLevel:
+    case ZSTD_c_hashLog:
+    case ZSTD_c_chainLog:
+    case ZSTD_c_searchLog:
+    case ZSTD_c_minMatch:
+    case ZSTD_c_targetLength:
+    case ZSTD_c_strategy:
+    case ZSTD_c_blockSplitterLevel:
+        return 1;
+
+    case ZSTD_c_format:
+    case ZSTD_c_windowLog:
+    case ZSTD_c_contentSizeFlag:
+    case ZSTD_c_checksumFlag:
+    case ZSTD_c_dictIDFlag:
+    case ZSTD_c_forceMaxWindow :
+    case ZSTD_c_nbWorkers:
+    case ZSTD_c_jobSize:
+    case ZSTD_c_overlapLog:
+    case ZSTD_c_rsyncable:
+    case ZSTD_c_enableDedicatedDictSearch:
+    case ZSTD_c_enableLongDistanceMatching:
+    case ZSTD_c_ldmHashLog:
+    case ZSTD_c_ldmMinMatch:
+    case ZSTD_c_ldmBucketSizeLog:
+    case ZSTD_c_ldmHashRateLog:
+    case ZSTD_c_forceAttachDict:
+    case ZSTD_c_literalCompressionMode:
+    case ZSTD_c_targetCBlockSize:
+    case ZSTD_c_srcSizeHint:
+    case ZSTD_c_stableInBuffer:
+    case ZSTD_c_stableOutBuffer:
+    case ZSTD_c_blockDelimiters:
+    case ZSTD_c_validateSequences:
+    case ZSTD_c_splitAfterSequences:
+    case ZSTD_c_useRowMatchFinder:
+    case ZSTD_c_deterministicRefPrefix:
+    case ZSTD_c_prefetchCDictTables:
+    case ZSTD_c_enableSeqProducerFallback:
+    case ZSTD_c_maxBlockSize:
+    case ZSTD_c_repcodeResolution:
+    default:
+        return 0;
+    }
+}
+
+size_t ZSTD_CCtx_setParameter(ZSTD_CCtx* cctx, ZSTD_cParameter param, int value)
+{
+    DEBUGLOG(4, "ZSTD_CCtx_setParameter (%i, %i)", (int)param, value);
+    if (cctx->streamStage != zcss_init) {
+        if (ZSTD_isUpdateAuthorized(param)) {
+            cctx->cParamsChanged = 1;
+        } else {
+            RETURN_ERROR(stage_wrong, "can only set params in cctx init stage");
+    }   }
+
+    switch(param)
+    {
+    case ZSTD_c_nbWorkers:
+        RETURN_ERROR_IF((value!=0) && cctx->staticSize, parameter_unsupported,
+                        "MT not compatible with static alloc");
+        break;
+
+    case ZSTD_c_compressionLevel:
+    case ZSTD_c_windowLog:
+    case ZSTD_c_hashLog:
+    case ZSTD_c_chainLog:
+    case ZSTD_c_searchLog:
+    case ZSTD_c_minMatch:
+    case ZSTD_c_targetLength:
+    case ZSTD_c_strategy:
+    case ZSTD_c_ldmHashRateLog:
+    case ZSTD_c_format:
+    case ZSTD_c_contentSizeFlag:
+    case ZSTD_c_checksumFlag:
+    case ZSTD_c_dictIDFlag:
+    case ZSTD_c_forceMaxWindow:
+    case ZSTD_c_forceAttachDict:
+    case ZSTD_c_literalCompressionMode:
+    case ZSTD_c_jobSize:
+    case ZSTD_c_overlapLog:
+    case ZSTD_c_rsyncable:
+    case ZSTD_c_enableDedicatedDictSearch:
+    case ZSTD_c_enableLongDistanceMatching:
+    case ZSTD_c_ldmHashLog:
+    case ZSTD_c_ldmMinMatch:
+    case ZSTD_c_ldmBucketSizeLog:
+    case ZSTD_c_targetCBlockSize:
+    case ZSTD_c_srcSizeHint:
+    case ZSTD_c_stableInBuffer:
+    case ZSTD_c_stableOutBuffer:
+    case ZSTD_c_blockDelimiters:
+    case ZSTD_c_validateSequences:
+    case ZSTD_c_splitAfterSequences:
+    case ZSTD_c_blockSplitterLevel:
+    case ZSTD_c_useRowMatchFinder:
+    case ZSTD_c_deterministicRefPrefix:
+    case ZSTD_c_prefetchCDictTables:
+    case ZSTD_c_enableSeqProducerFallback:
+    case ZSTD_c_maxBlockSize:
+    case ZSTD_c_repcodeResolution:
+        break;
+
+    default: RETURN_ERROR(parameter_unsupported, "unknown parameter");
+    }
+    return ZSTD_CCtxParams_setParameter(&cctx->requestedParams, param, value);
+}
+
+size_t ZSTD_CCtxParams_setParameter(ZSTD_CCtx_params* CCtxParams,
+                                    ZSTD_cParameter param, int value)
+{
+    DEBUGLOG(4, "ZSTD_CCtxParams_setParameter (%i, %i)", (int)param, value);
+    switch(param)
+    {
+    case ZSTD_c_format :
+        BOUNDCHECK(ZSTD_c_format, value);
+        CCtxParams->format = (ZSTD_format_e)value;
+        return (size_t)CCtxParams->format;
+
+    case ZSTD_c_compressionLevel : {
+        FORWARD_IF_ERROR(ZSTD_cParam_clampBounds(param, &value), "");
+        if (value == 0)
+            CCtxParams->compressionLevel = ZSTD_CLEVEL_DEFAULT; /* 0 == default */
+        else
+            CCtxParams->compressionLevel = value;
+        if (CCtxParams->compressionLevel >= 0) return (size_t)CCtxParams->compressionLevel;
+        return 0;  /* return type (size_t) cannot represent negative values */
+    }
+
+    case ZSTD_c_windowLog :
+        if (value!=0)   /* 0 => use default */
+            BOUNDCHECK(ZSTD_c_windowLog, value);
+        CCtxParams->cParams.windowLog = (U32)value;
+        return CCtxParams->cParams.windowLog;
+
+    case ZSTD_c_hashLog :
+        if (value!=0)   /* 0 => use default */
+            BOUNDCHECK(ZSTD_c_hashLog, value);
+        CCtxParams->cParams.hashLog = (U32)value;
+        return CCtxParams->cParams.hashLog;
+
+    case ZSTD_c_chainLog :
+        if (value!=0)   /* 0 => use default */
+            BOUNDCHECK(ZSTD_c_chainLog, value);
+        CCtxParams->cParams.chainLog = (U32)value;
+        return CCtxParams->cParams.chainLog;
+
+    case ZSTD_c_searchLog :
+        if (value!=0)   /* 0 => use default */
+            BOUNDCHECK(ZSTD_c_searchLog, value);
+        CCtxParams->cParams.searchLog = (U32)value;
+        return (size_t)value;
+
+    case ZSTD_c_minMatch :
+        if (value!=0)   /* 0 => use default */
+            BOUNDCHECK(ZSTD_c_minMatch, value);
+        CCtxParams->cParams.minMatch = (U32)value;
+        return CCtxParams->cParams.minMatch;
+
+    case ZSTD_c_targetLength :
+        BOUNDCHECK(ZSTD_c_targetLength, value);
+        CCtxParams->cParams.targetLength = (U32)value;
+        return CCtxParams->cParams.targetLength;
+
+    case ZSTD_c_strategy :
+        if (value!=0)   /* 0 => use default */
+            BOUNDCHECK(ZSTD_c_strategy, value);
+        CCtxParams->cParams.strategy = (ZSTD_strategy)value;
+        return (size_t)CCtxParams->cParams.strategy;
+
+    case ZSTD_c_contentSizeFlag :
+        /* Content size written in frame header _when known_ (default:1) */
+        DEBUGLOG(4, "set content size flag = %u", (value!=0));
+        CCtxParams->fParams.contentSizeFlag = value != 0;
+        return (size_t)CCtxParams->fParams.contentSizeFlag;
+
+    case ZSTD_c_checksumFlag :
+        /* A 32-bits content checksum will be calculated and written at end of frame (default:0) */
+        CCtxParams->fParams.checksumFlag = value != 0;
+        return (size_t)CCtxParams->fParams.checksumFlag;
+
+    case ZSTD_c_dictIDFlag : /* When applicable, dictionary's dictID is provided in frame header (default:1) */
+        DEBUGLOG(4, "set dictIDFlag = %u", (value!=0));
+        CCtxParams->fParams.noDictIDFlag = !value;
+        return !CCtxParams->fParams.noDictIDFlag;
+
+    case ZSTD_c_forceMaxWindow :
+        CCtxParams->forceWindow = (value != 0);
+        return (size_t)CCtxParams->forceWindow;
+
+    case ZSTD_c_forceAttachDict : {
+        const ZSTD_dictAttachPref_e pref = (ZSTD_dictAttachPref_e)value;
+        BOUNDCHECK(ZSTD_c_forceAttachDict, (int)pref);
+        CCtxParams->attachDictPref = pref;
+        return CCtxParams->attachDictPref;
+    }
+
+    case ZSTD_c_literalCompressionMode : {
+        const ZSTD_ParamSwitch_e lcm = (ZSTD_ParamSwitch_e)value;
+        BOUNDCHECK(ZSTD_c_literalCompressionMode, (int)lcm);
+        CCtxParams->literalCompressionMode = lcm;
+        return CCtxParams->literalCompressionMode;
+    }
+
+    case ZSTD_c_nbWorkers :
+#ifndef ZSTD_MULTITHREAD
+        RETURN_ERROR_IF(value!=0, parameter_unsupported, "not compiled with multithreading");
+        return 0;
+#else
+        FORWARD_IF_ERROR(ZSTD_cParam_clampBounds(param, &value), "");
+        CCtxParams->nbWorkers = value;
+        return (size_t)(CCtxParams->nbWorkers);
+#endif
+
+    case ZSTD_c_jobSize :
+#ifndef ZSTD_MULTITHREAD
+        RETURN_ERROR_IF(value!=0, parameter_unsupported, "not compiled with multithreading");
+        return 0;
+#else
+        /* Adjust to the minimum non-default value. */
+        if (value != 0 && value < ZSTDMT_JOBSIZE_MIN)
+            value = ZSTDMT_JOBSIZE_MIN;
+        FORWARD_IF_ERROR(ZSTD_cParam_clampBounds(param, &value), "");
+        assert(value >= 0);
+        CCtxParams->jobSize = (size_t)value;
+        return CCtxParams->jobSize;
+#endif
+
+    case ZSTD_c_overlapLog :
+#ifndef ZSTD_MULTITHREAD
+        RETURN_ERROR_IF(value!=0, parameter_unsupported, "not compiled with multithreading");
+        return 0;
+#else
+        FORWARD_IF_ERROR(ZSTD_cParam_clampBounds(ZSTD_c_overlapLog, &value), "");
+        CCtxParams->overlapLog = value;
+        return (size_t)CCtxParams->overlapLog;
+#endif
+
+    case ZSTD_c_rsyncable :
+#ifndef ZSTD_MULTITHREAD
+        RETURN_ERROR_IF(value!=0, parameter_unsupported, "not compiled with multithreading");
+        return 0;
+#else
+        FORWARD_IF_ERROR(ZSTD_cParam_clampBounds(ZSTD_c_overlapLog, &value), "");
+        CCtxParams->rsyncable = value;
+        return (size_t)CCtxParams->rsyncable;
+#endif
+
+    case ZSTD_c_enableDedicatedDictSearch :
+        CCtxParams->enableDedicatedDictSearch = (value!=0);
+        return (size_t)CCtxParams->enableDedicatedDictSearch;
+
+    case ZSTD_c_enableLongDistanceMatching :
+        BOUNDCHECK(ZSTD_c_enableLongDistanceMatching, value);
+        CCtxParams->ldmParams.enableLdm = (ZSTD_ParamSwitch_e)value;
+        return CCtxParams->ldmParams.enableLdm;
+
+    case ZSTD_c_ldmHashLog :
+        if (value!=0)   /* 0 ==> auto */
+            BOUNDCHECK(ZSTD_c_ldmHashLog, value);
+        CCtxParams->ldmParams.hashLog = (U32)value;
+        return CCtxParams->ldmParams.hashLog;
+
+    case ZSTD_c_ldmMinMatch :
+        if (value!=0)   /* 0 ==> default */
+            BOUNDCHECK(ZSTD_c_ldmMinMatch, value);
+        CCtxParams->ldmParams.minMatchLength = (U32)value;
+        return CCtxParams->ldmParams.minMatchLength;
+
+    case ZSTD_c_ldmBucketSizeLog :
+        if (value!=0)   /* 0 ==> default */
+            BOUNDCHECK(ZSTD_c_ldmBucketSizeLog, value);
+        CCtxParams->ldmParams.bucketSizeLog = (U32)value;
+        return CCtxParams->ldmParams.bucketSizeLog;
+
+    case ZSTD_c_ldmHashRateLog :
+        if (value!=0)   /* 0 ==> default */
+            BOUNDCHECK(ZSTD_c_ldmHashRateLog, value);
+        CCtxParams->ldmParams.hashRateLog = (U32)value;
+        return CCtxParams->ldmParams.hashRateLog;
+
+    case ZSTD_c_targetCBlockSize :
+        if (value!=0) {  /* 0 ==> default */
+            value = MAX(value, ZSTD_TARGETCBLOCKSIZE_MIN);
+            BOUNDCHECK(ZSTD_c_targetCBlockSize, value);
+        }
+        CCtxParams->targetCBlockSize = (U32)value;
+        return CCtxParams->targetCBlockSize;
+
+    case ZSTD_c_srcSizeHint :
+        if (value!=0)    /* 0 ==> default */
+            BOUNDCHECK(ZSTD_c_srcSizeHint, value);
+        CCtxParams->srcSizeHint = value;
+        return (size_t)CCtxParams->srcSizeHint;
+
+    case ZSTD_c_stableInBuffer:
+        BOUNDCHECK(ZSTD_c_stableInBuffer, value);
+        CCtxParams->inBufferMode = (ZSTD_bufferMode_e)value;
+        return CCtxParams->inBufferMode;
+
+    case ZSTD_c_stableOutBuffer:
+        BOUNDCHECK(ZSTD_c_stableOutBuffer, value);
+        CCtxParams->outBufferMode = (ZSTD_bufferMode_e)value;
+        return CCtxParams->outBufferMode;
+
+    case ZSTD_c_blockDelimiters:
+        BOUNDCHECK(ZSTD_c_blockDelimiters, value);
+        CCtxParams->blockDelimiters = (ZSTD_SequenceFormat_e)value;
+        return CCtxParams->blockDelimiters;
+
+    case ZSTD_c_validateSequences:
+        BOUNDCHECK(ZSTD_c_validateSequences, value);
+        CCtxParams->validateSequences = value;
+        return (size_t)CCtxParams->validateSequences;
+
+    case ZSTD_c_splitAfterSequences:
+        BOUNDCHECK(ZSTD_c_splitAfterSequences, value);
+        CCtxParams->postBlockSplitter = (ZSTD_ParamSwitch_e)value;
+        return CCtxParams->postBlockSplitter;
+
+    case ZSTD_c_blockSplitterLevel:
+        BOUNDCHECK(ZSTD_c_blockSplitterLevel, value);
+        CCtxParams->preBlockSplitter_level = value;
+        return (size_t)CCtxParams->preBlockSplitter_level;
+
+    case ZSTD_c_useRowMatchFinder:
+        BOUNDCHECK(ZSTD_c_useRowMatchFinder, value);
+        CCtxParams->useRowMatchFinder = (ZSTD_ParamSwitch_e)value;
+        return CCtxParams->useRowMatchFinder;
+
+    case ZSTD_c_deterministicRefPrefix:
+        BOUNDCHECK(ZSTD_c_deterministicRefPrefix, value);
+        CCtxParams->deterministicRefPrefix = !!value;
+        return (size_t)CCtxParams->deterministicRefPrefix;
+
+    case ZSTD_c_prefetchCDictTables:
+        BOUNDCHECK(ZSTD_c_prefetchCDictTables, value);
+        CCtxParams->prefetchCDictTables = (ZSTD_ParamSwitch_e)value;
+        return CCtxParams->prefetchCDictTables;
+
+    case ZSTD_c_enableSeqProducerFallback:
+        BOUNDCHECK(ZSTD_c_enableSeqProducerFallback, value);
+        CCtxParams->enableMatchFinderFallback = value;
+        return (size_t)CCtxParams->enableMatchFinderFallback;
+
+    case ZSTD_c_maxBlockSize:
+        if (value!=0)    /* 0 ==> default */
+            BOUNDCHECK(ZSTD_c_maxBlockSize, value);
+        assert(value>=0);
+        CCtxParams->maxBlockSize = (size_t)value;
+        return CCtxParams->maxBlockSize;
+
+    case ZSTD_c_repcodeResolution:
+        BOUNDCHECK(ZSTD_c_repcodeResolution, value);
+        CCtxParams->searchForExternalRepcodes = (ZSTD_ParamSwitch_e)value;
+        return CCtxParams->searchForExternalRepcodes;
+
+    default: RETURN_ERROR(parameter_unsupported, "unknown parameter");
+    }
+}
+
+size_t ZSTD_CCtx_getParameter(ZSTD_CCtx const* cctx, ZSTD_cParameter param, int* value)
+{
+    return ZSTD_CCtxParams_getParameter(&cctx->requestedParams, param, value);
+}
+
+size_t ZSTD_CCtxParams_getParameter(
+        ZSTD_CCtx_params const* CCtxParams, ZSTD_cParameter param, int* value)
+{
+    switch(param)
+    {
+    case ZSTD_c_format :
+        *value = (int)CCtxParams->format;
+        break;
+    case ZSTD_c_compressionLevel :
+        *value = CCtxParams->compressionLevel;
+        break;
+    case ZSTD_c_windowLog :
+        *value = (int)CCtxParams->cParams.windowLog;
+        break;
+    case ZSTD_c_hashLog :
+        *value = (int)CCtxParams->cParams.hashLog;
+        break;
+    case ZSTD_c_chainLog :
+        *value = (int)CCtxParams->cParams.chainLog;
+        break;
+    case ZSTD_c_searchLog :
+        *value = (int)CCtxParams->cParams.searchLog;
+        break;
+    case ZSTD_c_minMatch :
+        *value = (int)CCtxParams->cParams.minMatch;
+        break;
+    case ZSTD_c_targetLength :
+        *value = (int)CCtxParams->cParams.targetLength;
+        break;
+    case ZSTD_c_strategy :
+        *value = (int)CCtxParams->cParams.strategy;
+        break;
+    case ZSTD_c_contentSizeFlag :
+        *value = CCtxParams->fParams.contentSizeFlag;
+        break;
+    case ZSTD_c_checksumFlag :
+        *value = CCtxParams->fParams.checksumFlag;
+        break;
+    case ZSTD_c_dictIDFlag :
+        *value = !CCtxParams->fParams.noDictIDFlag;
+        break;
+    case ZSTD_c_forceMaxWindow :
+        *value = CCtxParams->forceWindow;
+        break;
+    case ZSTD_c_forceAttachDict :
+        *value = (int)CCtxParams->attachDictPref;
+        break;
+    case ZSTD_c_literalCompressionMode :
+        *value = (int)CCtxParams->literalCompressionMode;
+        break;
+    case ZSTD_c_nbWorkers :
+#ifndef ZSTD_MULTITHREAD
+        assert(CCtxParams->nbWorkers == 0);
+#endif
+        *value = CCtxParams->nbWorkers;
+        break;
+    case ZSTD_c_jobSize :
+#ifndef ZSTD_MULTITHREAD
+        RETURN_ERROR(parameter_unsupported, "not compiled with multithreading");
+#else
+        assert(CCtxParams->jobSize <= INT_MAX);
+        *value = (int)CCtxParams->jobSize;
+        break;
+#endif
+    case ZSTD_c_overlapLog :
+#ifndef ZSTD_MULTITHREAD
+        RETURN_ERROR(parameter_unsupported, "not compiled with multithreading");
+#else
+        *value = CCtxParams->overlapLog;
+        break;
+#endif
+    case ZSTD_c_rsyncable :
+#ifndef ZSTD_MULTITHREAD
+        RETURN_ERROR(parameter_unsupported, "not compiled with multithreading");
+#else
+        *value = CCtxParams->rsyncable;
+        break;
+#endif
+    case ZSTD_c_enableDedicatedDictSearch :
+        *value = CCtxParams->enableDedicatedDictSearch;
+        break;
+    case ZSTD_c_enableLongDistanceMatching :
+        *value = (int)CCtxParams->ldmParams.enableLdm;
+        break;
+    case ZSTD_c_ldmHashLog :
+        *value = (int)CCtxParams->ldmParams.hashLog;
+        break;
+    case ZSTD_c_ldmMinMatch :
+        *value = (int)CCtxParams->ldmParams.minMatchLength;
+        break;
+    case ZSTD_c_ldmBucketSizeLog :
+        *value = (int)CCtxParams->ldmParams.bucketSizeLog;
+        break;
+    case ZSTD_c_ldmHashRateLog :
+        *value = (int)CCtxParams->ldmParams.hashRateLog;
+        break;
+    case ZSTD_c_targetCBlockSize :
+        *value = (int)CCtxParams->targetCBlockSize;
+        break;
+    case ZSTD_c_srcSizeHint :
+        *value = (int)CCtxParams->srcSizeHint;
+        break;
+    case ZSTD_c_stableInBuffer :
+        *value = (int)CCtxParams->inBufferMode;
+        break;
+    case ZSTD_c_stableOutBuffer :
+        *value = (int)CCtxParams->outBufferMode;
+        break;
+    case ZSTD_c_blockDelimiters :
+        *value = (int)CCtxParams->blockDelimiters;
+        break;
+    case ZSTD_c_validateSequences :
+        *value = (int)CCtxParams->validateSequences;
+        break;
+    case ZSTD_c_splitAfterSequences :
+        *value = (int)CCtxParams->postBlockSplitter;
+        break;
+    case ZSTD_c_blockSplitterLevel :
+        *value = CCtxParams->preBlockSplitter_level;
+        break;
+    case ZSTD_c_useRowMatchFinder :
+        *value = (int)CCtxParams->useRowMatchFinder;
+        break;
+    case ZSTD_c_deterministicRefPrefix:
+        *value = (int)CCtxParams->deterministicRefPrefix;
+        break;
+    case ZSTD_c_prefetchCDictTables:
+        *value = (int)CCtxParams->prefetchCDictTables;
+        break;
+    case ZSTD_c_enableSeqProducerFallback:
+        *value = CCtxParams->enableMatchFinderFallback;
+        break;
+    case ZSTD_c_maxBlockSize:
+        *value = (int)CCtxParams->maxBlockSize;
+        break;
+    case ZSTD_c_repcodeResolution:
+        *value = (int)CCtxParams->searchForExternalRepcodes;
+        break;
+    default: RETURN_ERROR(parameter_unsupported, "unknown parameter");
+    }
+    return 0;
+}
+
+/** ZSTD_CCtx_setParametersUsingCCtxParams() :
+ *  just applies `params` into `cctx`
+ *  no action is performed, parameters are merely stored.
+ *  If ZSTDMT is enabled, parameters are pushed to cctx->mtctx.
+ *    This is possible even if a compression is ongoing.
+ *    In which case, new parameters will be applied on the fly, starting with next compression job.
+ */
+size_t ZSTD_CCtx_setParametersUsingCCtxParams(
+        ZSTD_CCtx* cctx, const ZSTD_CCtx_params* params)
+{
+    DEBUGLOG(4, "ZSTD_CCtx_setParametersUsingCCtxParams");
+    RETURN_ERROR_IF(cctx->streamStage != zcss_init, stage_wrong,
+                    "The context is in the wrong stage!");
+    RETURN_ERROR_IF(cctx->cdict, stage_wrong,
+                    "Can't override parameters with cdict attached (some must "
+                    "be inherited from the cdict).");
+
+    cctx->requestedParams = *params;
+    return 0;
+}
+
+size_t ZSTD_CCtx_setCParams(ZSTD_CCtx* cctx, ZSTD_compressionParameters cparams)
+{
+    ZSTD_STATIC_ASSERT(sizeof(cparams) == 7 * 4 /* all params are listed below */);
+    DEBUGLOG(4, "ZSTD_CCtx_setCParams");
+    /* only update if all parameters are valid */
+    FORWARD_IF_ERROR(ZSTD_checkCParams(cparams), "");
+    FORWARD_IF_ERROR(ZSTD_CCtx_setParameter(cctx, ZSTD_c_windowLog, (int)cparams.windowLog), "");
+    FORWARD_IF_ERROR(ZSTD_CCtx_setParameter(cctx, ZSTD_c_chainLog, (int)cparams.chainLog), "");
+    FORWARD_IF_ERROR(ZSTD_CCtx_setParameter(cctx, ZSTD_c_hashLog, (int)cparams.hashLog), "");
+    FORWARD_IF_ERROR(ZSTD_CCtx_setParameter(cctx, ZSTD_c_searchLog, (int)cparams.searchLog), "");
+    FORWARD_IF_ERROR(ZSTD_CCtx_setParameter(cctx, ZSTD_c_minMatch, (int)cparams.minMatch), "");
+    FORWARD_IF_ERROR(ZSTD_CCtx_setParameter(cctx, ZSTD_c_targetLength, (int)cparams.targetLength), "");
+    FORWARD_IF_ERROR(ZSTD_CCtx_setParameter(cctx, ZSTD_c_strategy, (int)cparams.strategy), "");
+    return 0;
+}
+
+size_t ZSTD_CCtx_setFParams(ZSTD_CCtx* cctx, ZSTD_frameParameters fparams)
+{
+    ZSTD_STATIC_ASSERT(sizeof(fparams) == 3 * 4 /* all params are listed below */);
+    DEBUGLOG(4, "ZSTD_CCtx_setFParams");
+    FORWARD_IF_ERROR(ZSTD_CCtx_setParameter(cctx, ZSTD_c_contentSizeFlag, fparams.contentSizeFlag != 0), "");
+    FORWARD_IF_ERROR(ZSTD_CCtx_setParameter(cctx, ZSTD_c_checksumFlag, fparams.checksumFlag != 0), "");
+    FORWARD_IF_ERROR(ZSTD_CCtx_setParameter(cctx, ZSTD_c_dictIDFlag, fparams.noDictIDFlag == 0), "");
+    return 0;
+}
+
+size_t ZSTD_CCtx_setParams(ZSTD_CCtx* cctx, ZSTD_parameters params)
+{
+    DEBUGLOG(4, "ZSTD_CCtx_setParams");
+    /* First check cParams, because we want to update all or none. */
+    FORWARD_IF_ERROR(ZSTD_checkCParams(params.cParams), "");
+    /* Next set fParams, because this could fail if the cctx isn't in init stage. */
+    FORWARD_IF_ERROR(ZSTD_CCtx_setFParams(cctx, params.fParams), "");
+    /* Finally set cParams, which should succeed. */
+    FORWARD_IF_ERROR(ZSTD_CCtx_setCParams(cctx, params.cParams), "");
+    return 0;
+}
+
+size_t ZSTD_CCtx_setPledgedSrcSize(ZSTD_CCtx* cctx, unsigned long long pledgedSrcSize)
+{
+    DEBUGLOG(4, "ZSTD_CCtx_setPledgedSrcSize to %llu bytes", pledgedSrcSize);
+    RETURN_ERROR_IF(cctx->streamStage != zcss_init, stage_wrong,
+                    "Can't set pledgedSrcSize when not in init stage.");
+    cctx->pledgedSrcSizePlusOne = pledgedSrcSize+1;
+    return 0;
+}
+
+static ZSTD_compressionParameters ZSTD_dedicatedDictSearch_getCParams(
+        int const compressionLevel,
+        size_t const dictSize);
+static int ZSTD_dedicatedDictSearch_isSupported(
+        const ZSTD_compressionParameters* cParams);
+static void ZSTD_dedicatedDictSearch_revertCParams(
+        ZSTD_compressionParameters* cParams);
+
+size_t ZSTD_CCtx_loadDictionary_advanced(
+        ZSTD_CCtx* cctx,
+        const void* dict, size_t dictSize,
+        ZSTD_dictLoadMethod_e dictLoadMethod,
+        ZSTD_dictContentType_e dictContentType)
+{
+    DEBUGLOG(4, "ZSTD_CCtx_loadDictionary_advanced (size: %u)", (U32)dictSize);
+    RETURN_ERROR_IF(cctx->streamStage != zcss_init, stage_wrong,
+                    "Can't load a dictionary when cctx is not in init stage.");
+    ZSTD_clearAllDicts(cctx);  /* erase any previously set dictionary */
+    if (dict == NULL || dictSize == 0)  /* no dictionary */
+        return 0;
+    if (dictLoadMethod == ZSTD_dlm_byRef) {
+        cctx->localDict.dict = dict;
+    } else {
+        /* copy dictionary content inside CCtx to own its lifetime */
+        void* dictBuffer;
+        RETURN_ERROR_IF(cctx->staticSize, memory_allocation,
+                        "static CCtx can't allocate for an internal copy of dictionary");
+        dictBuffer = ZSTD_customMalloc(dictSize, cctx->customMem);
+        RETURN_ERROR_IF(dictBuffer==NULL, memory_allocation,
+                        "allocation failed for dictionary content");
+        ZSTD_memcpy(dictBuffer, dict, dictSize);
+        cctx->localDict.dictBuffer = dictBuffer;  /* owned ptr to free */
+        cctx->localDict.dict = dictBuffer;        /* read-only reference */
+    }
+    cctx->localDict.dictSize = dictSize;
+    cctx->localDict.dictContentType = dictContentType;
+    return 0;
+}
+
+size_t ZSTD_CCtx_loadDictionary_byReference(
+      ZSTD_CCtx* cctx, const void* dict, size_t dictSize)
+{
+    return ZSTD_CCtx_loadDictionary_advanced(
+            cctx, dict, dictSize, ZSTD_dlm_byRef, ZSTD_dct_auto);
+}
+
+size_t ZSTD_CCtx_loadDictionary(ZSTD_CCtx* cctx, const void* dict, size_t dictSize)
+{
+    return ZSTD_CCtx_loadDictionary_advanced(
+            cctx, dict, dictSize, ZSTD_dlm_byCopy, ZSTD_dct_auto);
+}
+
+size_t ZSTD_CCtx_refCDict(ZSTD_CCtx* cctx, const ZSTD_CDict* cdict)
+{
+    RETURN_ERROR_IF(cctx->streamStage != zcss_init, stage_wrong,
+                    "Can't ref a dict when ctx not in init stage.");
+    /* Free the existing local cdict (if any) to save memory. */
+    ZSTD_clearAllDicts(cctx);
+    cctx->cdict = cdict;
+    return 0;
+}
+
+size_t ZSTD_CCtx_refThreadPool(ZSTD_CCtx* cctx, ZSTD_threadPool* pool)
+{
+    RETURN_ERROR_IF(cctx->streamStage != zcss_init, stage_wrong,
+                    "Can't ref a pool when ctx not in init stage.");
+    cctx->pool = pool;
+    return 0;
+}
+
+size_t ZSTD_CCtx_refPrefix(ZSTD_CCtx* cctx, const void* prefix, size_t prefixSize)
+{
+    return ZSTD_CCtx_refPrefix_advanced(cctx, prefix, prefixSize, ZSTD_dct_rawContent);
+}
+
+size_t ZSTD_CCtx_refPrefix_advanced(
+        ZSTD_CCtx* cctx, const void* prefix, size_t prefixSize, ZSTD_dictContentType_e dictContentType)
+{
+    RETURN_ERROR_IF(cctx->streamStage != zcss_init, stage_wrong,
+                    "Can't ref a prefix when ctx not in init stage.");
+    ZSTD_clearAllDicts(cctx);
+    if (prefix != NULL && prefixSize > 0) {
+        cctx->prefixDict.dict = prefix;
+        cctx->prefixDict.dictSize = prefixSize;
+        cctx->prefixDict.dictContentType = dictContentType;
+    }
+    return 0;
+}
+
+/*! ZSTD_CCtx_reset() :
+ *  Also dumps dictionary */
+size_t ZSTD_CCtx_reset(ZSTD_CCtx* cctx, ZSTD_ResetDirective reset)
+{
+    if ( (reset == ZSTD_reset_session_only)
+      || (reset == ZSTD_reset_session_and_parameters) ) {
+        cctx->streamStage = zcss_init;
+        cctx->pledgedSrcSizePlusOne = 0;
+    }
+    if ( (reset == ZSTD_reset_parameters)
+      || (reset == ZSTD_reset_session_and_parameters) ) {
+        RETURN_ERROR_IF(cctx->streamStage != zcss_init, stage_wrong,
+                        "Reset parameters is only possible during init stage.");
+        ZSTD_clearAllDicts(cctx);
+        return ZSTD_CCtxParams_reset(&cctx->requestedParams);
+    }
+    return 0;
+}
+
+
+/** ZSTD_checkCParams() :
+    control CParam values remain within authorized range.
+    @return : 0, or an error code if one value is beyond authorized range */
+size_t ZSTD_checkCParams(ZSTD_compressionParameters cParams)
+{
+    BOUNDCHECK(ZSTD_c_windowLog, (int)cParams.windowLog);
+    BOUNDCHECK(ZSTD_c_chainLog,  (int)cParams.chainLog);
+    BOUNDCHECK(ZSTD_c_hashLog,   (int)cParams.hashLog);
+    BOUNDCHECK(ZSTD_c_searchLog, (int)cParams.searchLog);
+    BOUNDCHECK(ZSTD_c_minMatch,  (int)cParams.minMatch);
+    BOUNDCHECK(ZSTD_c_targetLength,(int)cParams.targetLength);
+    BOUNDCHECK(ZSTD_c_strategy,  (int)cParams.strategy);
+    return 0;
+}
+
+/** ZSTD_clampCParams() :
+ *  make CParam values within valid range.
+ *  @return : valid CParams */
+static ZSTD_compressionParameters
+ZSTD_clampCParams(ZSTD_compressionParameters cParams)
+{
+#   define CLAMP_TYPE(cParam, val, type)                                      \
+        do {                                                                  \
+            ZSTD_bounds const bounds = ZSTD_cParam_getBounds(cParam);         \
+            if ((int)val<bounds.lowerBound) val=(type)bounds.lowerBound;      \
+            else if ((int)val>bounds.upperBound) val=(type)bounds.upperBound; \
+        } while (0)
+#   define CLAMP(cParam, val) CLAMP_TYPE(cParam, val, unsigned)
+    CLAMP(ZSTD_c_windowLog, cParams.windowLog);
+    CLAMP(ZSTD_c_chainLog,  cParams.chainLog);
+    CLAMP(ZSTD_c_hashLog,   cParams.hashLog);
+    CLAMP(ZSTD_c_searchLog, cParams.searchLog);
+    CLAMP(ZSTD_c_minMatch,  cParams.minMatch);
+    CLAMP(ZSTD_c_targetLength,cParams.targetLength);
+    CLAMP_TYPE(ZSTD_c_strategy,cParams.strategy, ZSTD_strategy);
+    return cParams;
+}
+
+/** ZSTD_cycleLog() :
+ *  condition for correct operation : hashLog > 1 */
+U32 ZSTD_cycleLog(U32 hashLog, ZSTD_strategy strat)
+{
+    U32 const btScale = ((U32)strat >= (U32)ZSTD_btlazy2);
+    return hashLog - btScale;
+}
+
+/** ZSTD_dictAndWindowLog() :
+ * Returns an adjusted window log that is large enough to fit the source and the dictionary.
+ * The zstd format says that the entire dictionary is valid if one byte of the dictionary
+ * is within the window. So the hashLog and chainLog should be large enough to reference both
+ * the dictionary and the window. So we must use this adjusted dictAndWindowLog when downsizing
+ * the hashLog and windowLog.
+ * NOTE: srcSize must not be ZSTD_CONTENTSIZE_UNKNOWN.
+ */
+static U32 ZSTD_dictAndWindowLog(U32 windowLog, U64 srcSize, U64 dictSize)
+{
+    const U64 maxWindowSize = 1ULL << ZSTD_WINDOWLOG_MAX;
+    /* No dictionary ==> No change */
+    if (dictSize == 0) {
+        return windowLog;
+    }
+    assert(windowLog <= ZSTD_WINDOWLOG_MAX);
+    assert(srcSize != ZSTD_CONTENTSIZE_UNKNOWN); /* Handled in ZSTD_adjustCParams_internal() */
+    {
+        U64 const windowSize = 1ULL << windowLog;
+        U64 const dictAndWindowSize = dictSize + windowSize;
+        /* If the window size is already large enough to fit both the source and the dictionary
+         * then just use the window size. Otherwise adjust so that it fits the dictionary and
+         * the window.
+         */
+        if (windowSize >= dictSize + srcSize) {
+            return windowLog; /* Window size large enough already */
+        } else if (dictAndWindowSize >= maxWindowSize) {
+            return ZSTD_WINDOWLOG_MAX; /* Larger than max window log */
+        } else  {
+            return ZSTD_highbit32((U32)dictAndWindowSize - 1) + 1;
+        }
+    }
+}
+
+/** ZSTD_adjustCParams_internal() :
+ *  optimize `cPar` for a specified input (`srcSize` and `dictSize`).
+ *  mostly downsize to reduce memory consumption and initialization latency.
+ * `srcSize` can be ZSTD_CONTENTSIZE_UNKNOWN when not known.
+ * `mode` is the mode for parameter adjustment. See docs for `ZSTD_CParamMode_e`.
+ *  note : `srcSize==0` means 0!
+ *  condition : cPar is presumed validated (can be checked using ZSTD_checkCParams()). */
+static ZSTD_compressionParameters
+ZSTD_adjustCParams_internal(ZSTD_compressionParameters cPar,
+                            unsigned long long srcSize,
+                            size_t dictSize,
+                            ZSTD_CParamMode_e mode,
+                            ZSTD_ParamSwitch_e useRowMatchFinder)
+{
+    const U64 minSrcSize = 513; /* (1<<9) + 1 */
+    const U64 maxWindowResize = 1ULL << (ZSTD_WINDOWLOG_MAX-1);
+    assert(ZSTD_checkCParams(cPar)==0);
+
+    /* Cascade the selected strategy down to the next-highest one built into
+     * this binary. */
+#ifdef ZSTD_EXCLUDE_BTULTRA_BLOCK_COMPRESSOR
+    if (cPar.strategy == ZSTD_btultra2) {
+        cPar.strategy = ZSTD_btultra;
+    }
+    if (cPar.strategy == ZSTD_btultra) {
+        cPar.strategy = ZSTD_btopt;
+    }
+#endif
+#ifdef ZSTD_EXCLUDE_BTOPT_BLOCK_COMPRESSOR
+    if (cPar.strategy == ZSTD_btopt) {
+        cPar.strategy = ZSTD_btlazy2;
+    }
+#endif
+#ifdef ZSTD_EXCLUDE_BTLAZY2_BLOCK_COMPRESSOR
+    if (cPar.strategy == ZSTD_btlazy2) {
+        cPar.strategy = ZSTD_lazy2;
+    }
+#endif
+#ifdef ZSTD_EXCLUDE_LAZY2_BLOCK_COMPRESSOR
+    if (cPar.strategy == ZSTD_lazy2) {
+        cPar.strategy = ZSTD_lazy;
+    }
+#endif
+#ifdef ZSTD_EXCLUDE_LAZY_BLOCK_COMPRESSOR
+    if (cPar.strategy == ZSTD_lazy) {
+        cPar.strategy = ZSTD_greedy;
+    }
+#endif
+#ifdef ZSTD_EXCLUDE_GREEDY_BLOCK_COMPRESSOR
+    if (cPar.strategy == ZSTD_greedy) {
+        cPar.strategy = ZSTD_dfast;
+    }
+#endif
+#ifdef ZSTD_EXCLUDE_DFAST_BLOCK_COMPRESSOR
+    if (cPar.strategy == ZSTD_dfast) {
+        cPar.strategy = ZSTD_fast;
+        cPar.targetLength = 0;
+    }
+#endif
+
+    switch (mode) {
+    case ZSTD_cpm_unknown:
+    case ZSTD_cpm_noAttachDict:
+        /* If we don't know the source size, don't make any
+         * assumptions about it. We will already have selected
+         * smaller parameters if a dictionary is in use.
+         */
+        break;
+    case ZSTD_cpm_createCDict:
+        /* Assume a small source size when creating a dictionary
+         * with an unknown source size.
+         */
+        if (dictSize && srcSize == ZSTD_CONTENTSIZE_UNKNOWN)
+            srcSize = minSrcSize;
+        break;
+    case ZSTD_cpm_attachDict:
+        /* Dictionary has its own dedicated parameters which have
+         * already been selected. We are selecting parameters
+         * for only the source.
+         */
+        dictSize = 0;
+        break;
+    default:
+        assert(0);
+        break;
+    }
+
+    /* resize windowLog if input is small enough, to use less memory */
+    if ( (srcSize <= maxWindowResize)
+      && (dictSize <= maxWindowResize) )  {
+        U32 const tSize = (U32)(srcSize + dictSize);
+        static U32 const hashSizeMin = 1 << ZSTD_HASHLOG_MIN;
+        U32 const srcLog = (tSize < hashSizeMin) ? ZSTD_HASHLOG_MIN :
+                            ZSTD_highbit32(tSize-1) + 1;
+        if (cPar.windowLog > srcLog) cPar.windowLog = srcLog;
+    }
+    if (srcSize != ZSTD_CONTENTSIZE_UNKNOWN) {
+        U32 const dictAndWindowLog = ZSTD_dictAndWindowLog(cPar.windowLog, (U64)srcSize, (U64)dictSize);
+        U32 const cycleLog = ZSTD_cycleLog(cPar.chainLog, cPar.strategy);
+        if (cPar.hashLog > dictAndWindowLog+1) cPar.hashLog = dictAndWindowLog+1;
+        if (cycleLog > dictAndWindowLog)
+            cPar.chainLog -= (cycleLog - dictAndWindowLog);
+    }
+
+    if (cPar.windowLog < ZSTD_WINDOWLOG_ABSOLUTEMIN)
+        cPar.windowLog = ZSTD_WINDOWLOG_ABSOLUTEMIN;  /* minimum wlog required for valid frame header */
+
+    /* We can't use more than 32 bits of hash in total, so that means that we require:
+     * (hashLog + 8) <= 32 && (chainLog + 8) <= 32
+     */
+    if (mode == ZSTD_cpm_createCDict && ZSTD_CDictIndicesAreTagged(&cPar)) {
+        U32 const maxShortCacheHashLog = 32 - ZSTD_SHORT_CACHE_TAG_BITS;
+        if (cPar.hashLog > maxShortCacheHashLog) {
+            cPar.hashLog = maxShortCacheHashLog;
+        }
+        if (cPar.chainLog > maxShortCacheHashLog) {
+            cPar.chainLog = maxShortCacheHashLog;
+        }
+    }
+
+
+    /* At this point, we aren't 100% sure if we are using the row match finder.
+     * Unless it is explicitly disabled, conservatively assume that it is enabled.
+     * In this case it will only be disabled for small sources, so shrinking the
+     * hash log a little bit shouldn't result in any ratio loss.
+     */
+    if (useRowMatchFinder == ZSTD_ps_auto)
+        useRowMatchFinder = ZSTD_ps_enable;
+
+    /* We can't hash more than 32-bits in total. So that means that we require:
+     * (hashLog - rowLog + 8) <= 32
+     */
+    if (ZSTD_rowMatchFinderUsed(cPar.strategy, useRowMatchFinder)) {
+        /* Switch to 32-entry rows if searchLog is 5 (or more) */
+        U32 const rowLog = BOUNDED(4, cPar.searchLog, 6);
+        U32 const maxRowHashLog = 32 - ZSTD_ROW_HASH_TAG_BITS;
+        U32 const maxHashLog = maxRowHashLog + rowLog;
+        assert(cPar.hashLog >= rowLog);
+        if (cPar.hashLog > maxHashLog) {
+            cPar.hashLog = maxHashLog;
+        }
+    }
+
+    return cPar;
+}
+
+ZSTD_compressionParameters
+ZSTD_adjustCParams(ZSTD_compressionParameters cPar,
+                   unsigned long long srcSize,
+                   size_t dictSize)
+{
+    cPar = ZSTD_clampCParams(cPar);   /* resulting cPar is necessarily valid (all parameters within range) */
+    if (srcSize == 0) srcSize = ZSTD_CONTENTSIZE_UNKNOWN;
+    return ZSTD_adjustCParams_internal(cPar, srcSize, dictSize, ZSTD_cpm_unknown, ZSTD_ps_auto);
+}
+
+static ZSTD_compressionParameters ZSTD_getCParams_internal(int compressionLevel, unsigned long long srcSizeHint, size_t dictSize, ZSTD_CParamMode_e mode);
+static ZSTD_parameters ZSTD_getParams_internal(int compressionLevel, unsigned long long srcSizeHint, size_t dictSize, ZSTD_CParamMode_e mode);
+
+static void ZSTD_overrideCParams(
+              ZSTD_compressionParameters* cParams,
+        const ZSTD_compressionParameters* overrides)
+{
+    if (overrides->windowLog)    cParams->windowLog    = overrides->windowLog;
+    if (overrides->hashLog)      cParams->hashLog      = overrides->hashLog;
+    if (overrides->chainLog)     cParams->chainLog     = overrides->chainLog;
+    if (overrides->searchLog)    cParams->searchLog    = overrides->searchLog;
+    if (overrides->minMatch)     cParams->minMatch     = overrides->minMatch;
+    if (overrides->targetLength) cParams->targetLength = overrides->targetLength;
+    if (overrides->strategy)     cParams->strategy     = overrides->strategy;
+}
+
+ZSTD_compressionParameters ZSTD_getCParamsFromCCtxParams(
+        const ZSTD_CCtx_params* CCtxParams, U64 srcSizeHint, size_t dictSize, ZSTD_CParamMode_e mode)
+{
+    ZSTD_compressionParameters cParams;
+    if (srcSizeHint == ZSTD_CONTENTSIZE_UNKNOWN && CCtxParams->srcSizeHint > 0) {
+        assert(CCtxParams->srcSizeHint>=0);
+        srcSizeHint = (U64)CCtxParams->srcSizeHint;
+    }
+    cParams = ZSTD_getCParams_internal(CCtxParams->compressionLevel, srcSizeHint, dictSize, mode);
+    if (CCtxParams->ldmParams.enableLdm == ZSTD_ps_enable) cParams.windowLog = ZSTD_LDM_DEFAULT_WINDOW_LOG;
+    ZSTD_overrideCParams(&cParams, &CCtxParams->cParams);
+    assert(!ZSTD_checkCParams(cParams));
+    /* srcSizeHint == 0 means 0 */
+    return ZSTD_adjustCParams_internal(cParams, srcSizeHint, dictSize, mode, CCtxParams->useRowMatchFinder);
+}
+
+static size_t
+ZSTD_sizeof_matchState(const ZSTD_compressionParameters* const cParams,
+                       const ZSTD_ParamSwitch_e useRowMatchFinder,
+                       const int enableDedicatedDictSearch,
+                       const U32 forCCtx)
+{
+    /* chain table size should be 0 for fast or row-hash strategies */
+    size_t const chainSize = ZSTD_allocateChainTable(cParams->strategy, useRowMatchFinder, enableDedicatedDictSearch && !forCCtx)
+                                ? ((size_t)1 << cParams->chainLog)
+                                : 0;
+    size_t const hSize = ((size_t)1) << cParams->hashLog;
+    U32    const hashLog3 = (forCCtx && cParams->minMatch==3) ? MIN(ZSTD_HASHLOG3_MAX, cParams->windowLog) : 0;
+    size_t const h3Size = hashLog3 ? ((size_t)1) << hashLog3 : 0;
+    /* We don't use ZSTD_cwksp_alloc_size() here because the tables aren't
+     * surrounded by redzones in ASAN. */
+    size_t const tableSpace = chainSize * sizeof(U32)
+                            + hSize * sizeof(U32)
+                            + h3Size * sizeof(U32);
+    size_t const optPotentialSpace =
+        ZSTD_cwksp_aligned64_alloc_size((MaxML+1) * sizeof(U32))
+      + ZSTD_cwksp_aligned64_alloc_size((MaxLL+1) * sizeof(U32))
+      + ZSTD_cwksp_aligned64_alloc_size((MaxOff+1) * sizeof(U32))
+      + ZSTD_cwksp_aligned64_alloc_size((1<<Litbits) * sizeof(U32))
+      + ZSTD_cwksp_aligned64_alloc_size(ZSTD_OPT_SIZE * sizeof(ZSTD_match_t))
+      + ZSTD_cwksp_aligned64_alloc_size(ZSTD_OPT_SIZE * sizeof(ZSTD_optimal_t));
+    size_t const lazyAdditionalSpace = ZSTD_rowMatchFinderUsed(cParams->strategy, useRowMatchFinder)
+                                            ? ZSTD_cwksp_aligned64_alloc_size(hSize)
+                                            : 0;
+    size_t const optSpace = (forCCtx && (cParams->strategy >= ZSTD_btopt))
+                                ? optPotentialSpace
+                                : 0;
+    size_t const slackSpace = ZSTD_cwksp_slack_space_required();
+
+    /* tables are guaranteed to be sized in multiples of 64 bytes (or 16 uint32_t) */
+    ZSTD_STATIC_ASSERT(ZSTD_HASHLOG_MIN >= 4 && ZSTD_WINDOWLOG_MIN >= 4 && ZSTD_CHAINLOG_MIN >= 4);
+    assert(useRowMatchFinder != ZSTD_ps_auto);
+
+    DEBUGLOG(4, "chainSize: %u - hSize: %u - h3Size: %u",
+                (U32)chainSize, (U32)hSize, (U32)h3Size);
+    return tableSpace + optSpace + slackSpace + lazyAdditionalSpace;
+}
+
+/* Helper function for calculating memory requirements.
+ * Gives a tighter bound than ZSTD_sequenceBound() by taking minMatch into account. */
+static size_t ZSTD_maxNbSeq(size_t blockSize, unsigned minMatch, int useSequenceProducer) {
+    U32 const divider = (minMatch==3 || useSequenceProducer) ? 3 : 4;
+    return blockSize / divider;
+}
+
+static size_t ZSTD_estimateCCtxSize_usingCCtxParams_internal(
+        const ZSTD_compressionParameters* cParams,
+        const ldmParams_t* ldmParams,
+        const int isStatic,
+        const ZSTD_ParamSwitch_e useRowMatchFinder,
+        const size_t buffInSize,
+        const size_t buffOutSize,
+        const U64 pledgedSrcSize,
+        int useSequenceProducer,
+        size_t maxBlockSize)
+{
+    size_t const windowSize = (size_t) BOUNDED(1ULL, 1ULL << cParams->windowLog, pledgedSrcSize);
+    size_t const blockSize = MIN(ZSTD_resolveMaxBlockSize(maxBlockSize), windowSize);
+    size_t const maxNbSeq = ZSTD_maxNbSeq(blockSize, cParams->minMatch, useSequenceProducer);
+    size_t const tokenSpace = ZSTD_cwksp_alloc_size(WILDCOPY_OVERLENGTH + blockSize)
+                            + ZSTD_cwksp_aligned64_alloc_size(maxNbSeq * sizeof(SeqDef))
+                            + 3 * ZSTD_cwksp_alloc_size(maxNbSeq * sizeof(BYTE));
+    size_t const tmpWorkSpace = ZSTD_cwksp_alloc_size(TMP_WORKSPACE_SIZE);
+    size_t const blockStateSpace = 2 * ZSTD_cwksp_alloc_size(sizeof(ZSTD_compressedBlockState_t));
+    size_t const matchStateSize = ZSTD_sizeof_matchState(cParams, useRowMatchFinder, /* enableDedicatedDictSearch */ 0, /* forCCtx */ 1);
+
+    size_t const ldmSpace = ZSTD_ldm_getTableSize(*ldmParams);
+    size_t const maxNbLdmSeq = ZSTD_ldm_getMaxNbSeq(*ldmParams, blockSize);
+    size_t const ldmSeqSpace = ldmParams->enableLdm == ZSTD_ps_enable ?
+        ZSTD_cwksp_aligned64_alloc_size(maxNbLdmSeq * sizeof(rawSeq)) : 0;
+
+
+    size_t const bufferSpace = ZSTD_cwksp_alloc_size(buffInSize)
+                             + ZSTD_cwksp_alloc_size(buffOutSize);
+
+    size_t const cctxSpace = isStatic ? ZSTD_cwksp_alloc_size(sizeof(ZSTD_CCtx)) : 0;
+
+    size_t const maxNbExternalSeq = ZSTD_sequenceBound(blockSize);
+    size_t const externalSeqSpace = useSequenceProducer
+        ? ZSTD_cwksp_aligned64_alloc_size(maxNbExternalSeq * sizeof(ZSTD_Sequence))
+        : 0;
+
+    size_t const neededSpace =
+        cctxSpace +
+        tmpWorkSpace +
+        blockStateSpace +
+        ldmSpace +
+        ldmSeqSpace +
+        matchStateSize +
+        tokenSpace +
+        bufferSpace +
+        externalSeqSpace;
+
+    DEBUGLOG(5, "estimate workspace : %u", (U32)neededSpace);
+    return neededSpace;
+}
+
+size_t ZSTD_estimateCCtxSize_usingCCtxParams(const ZSTD_CCtx_params* params)
+{
+    ZSTD_compressionParameters const cParams =
+                ZSTD_getCParamsFromCCtxParams(params, ZSTD_CONTENTSIZE_UNKNOWN, 0, ZSTD_cpm_noAttachDict);
+    ZSTD_ParamSwitch_e const useRowMatchFinder = ZSTD_resolveRowMatchFinderMode(params->useRowMatchFinder,
+                                                                               &cParams);
+
+    RETURN_ERROR_IF(params->nbWorkers > 0, GENERIC, "Estimate CCtx size is supported for single-threaded compression only.");
+    /* estimateCCtxSize is for one-shot compression. So no buffers should
+     * be needed. However, we still allocate two 0-sized buffers, which can
+     * take space under ASAN. */
+    return ZSTD_estimateCCtxSize_usingCCtxParams_internal(
+        &cParams, &params->ldmParams, 1, useRowMatchFinder, 0, 0, ZSTD_CONTENTSIZE_UNKNOWN, ZSTD_hasExtSeqProd(params), params->maxBlockSize);
+}
+
+size_t ZSTD_estimateCCtxSize_usingCParams(ZSTD_compressionParameters cParams)
+{
+    ZSTD_CCtx_params initialParams = ZSTD_makeCCtxParamsFromCParams(cParams);
+    if (ZSTD_rowMatchFinderSupported(cParams.strategy)) {
+        /* Pick bigger of not using and using row-based matchfinder for greedy and lazy strategies */
+        size_t noRowCCtxSize;
+        size_t rowCCtxSize;
+        initialParams.useRowMatchFinder = ZSTD_ps_disable;
+        noRowCCtxSize = ZSTD_estimateCCtxSize_usingCCtxParams(&initialParams);
+        initialParams.useRowMatchFinder = ZSTD_ps_enable;
+        rowCCtxSize = ZSTD_estimateCCtxSize_usingCCtxParams(&initialParams);
+        return MAX(noRowCCtxSize, rowCCtxSize);
+    } else {
+        return ZSTD_estimateCCtxSize_usingCCtxParams(&initialParams);
+    }
+}
+
+static size_t ZSTD_estimateCCtxSize_internal(int compressionLevel)
+{
+    int tier = 0;
+    size_t largestSize = 0;
+    static const unsigned long long srcSizeTiers[4] = {16 KB, 128 KB, 256 KB, ZSTD_CONTENTSIZE_UNKNOWN};
+    for (; tier < 4; ++tier) {
+        /* Choose the set of cParams for a given level across all srcSizes that give the largest cctxSize */
+        ZSTD_compressionParameters const cParams = ZSTD_getCParams_internal(compressionLevel, srcSizeTiers[tier], 0, ZSTD_cpm_noAttachDict);
+        largestSize = MAX(ZSTD_estimateCCtxSize_usingCParams(cParams), largestSize);
+    }
+    return largestSize;
+}
+
+size_t ZSTD_estimateCCtxSize(int compressionLevel)
+{
+    int level;
+    size_t memBudget = 0;
+    for (level=MIN(compressionLevel, 1); level<=compressionLevel; level++) {
+        /* Ensure monotonically increasing memory usage as compression level increases */
+        size_t const newMB = ZSTD_estimateCCtxSize_internal(level);
+        if (newMB > memBudget) memBudget = newMB;
+    }
+    return memBudget;
+}
+
+static void ZSTD_assertEqualCParams(ZSTD_compressionParameters cParams1,
+                                    ZSTD_compressionParameters cParams2)
+{
+    (void)cParams1;
+    (void)cParams2;
+    assert(cParams1.windowLog    == cParams2.windowLog);
+    assert(cParams1.chainLog     == cParams2.chainLog);
+    assert(cParams1.hashLog      == cParams2.hashLog);
+    assert(cParams1.searchLog    == cParams2.searchLog);
+    assert(cParams1.minMatch     == cParams2.minMatch);
+    assert(cParams1.targetLength == cParams2.targetLength);
+    assert(cParams1.strategy     == cParams2.strategy);
+}
+
+void ZSTD_reset_compressedBlockState(ZSTD_compressedBlockState_t* bs)
+{
+    int i;
+    for (i = 0; i < ZSTD_REP_NUM; ++i)
+        bs->rep[i] = repStartValue[i];
+    bs->entropy.huf.repeatMode = HUF_repeat_none;
+    bs->entropy.fse.offcode_repeatMode = FSE_repeat_none;
+    bs->entropy.fse.matchlength_repeatMode = FSE_repeat_none;
+    bs->entropy.fse.litlength_repeatMode = FSE_repeat_none;
+}
+
+/*! ZSTD_invalidateMatchState()
+ *  Invalidate all the matches in the match finder tables.
+ *  Requires nextSrc and base to be set (can be NULL).
+ */
+static void ZSTD_invalidateMatchState(ZSTD_MatchState_t* ms)
+{
+    ZSTD_window_clear(&ms->window);
+
+    ms->nextToUpdate = ms->window.dictLimit;
+    ms->loadedDictEnd = 0;
+    ms->opt.litLengthSum = 0;  /* force reset of btopt stats */
+    ms->dictMatchState = NULL;
+}
+
+/**
+ * Controls, for this matchState reset, whether the tables need to be cleared /
+ * prepared for the coming compression (ZSTDcrp_makeClean), or whether the
+ * tables can be left unclean (ZSTDcrp_leaveDirty), because we know that a
+ * subsequent operation will overwrite the table space anyways (e.g., copying
+ * the matchState contents in from a CDict).
+ */
+typedef enum {
+    ZSTDcrp_makeClean,
+    ZSTDcrp_leaveDirty
+} ZSTD_compResetPolicy_e;
+
+/**
+ * Controls, for this matchState reset, whether indexing can continue where it
+ * left off (ZSTDirp_continue), or whether it needs to be restarted from zero
+ * (ZSTDirp_reset).
+ */
+typedef enum {
+    ZSTDirp_continue,
+    ZSTDirp_reset
+} ZSTD_indexResetPolicy_e;
+
+typedef enum {
+    ZSTD_resetTarget_CDict,
+    ZSTD_resetTarget_CCtx
+} ZSTD_resetTarget_e;
+
+/* Mixes bits in a 64 bits in a value, based on XXH3_rrmxmx */
+static U64 ZSTD_bitmix(U64 val, U64 len) {
+    val ^= ZSTD_rotateRight_U64(val, 49) ^ ZSTD_rotateRight_U64(val, 24);
+    val *= 0x9FB21C651E98DF25ULL;
+    val ^= (val >> 35) + len ;
+    val *= 0x9FB21C651E98DF25ULL;
+    return val ^ (val >> 28);
+}
+
+/* Mixes in the hashSalt and hashSaltEntropy to create a new hashSalt */
+static void ZSTD_advanceHashSalt(ZSTD_MatchState_t* ms) {
+    ms->hashSalt = ZSTD_bitmix(ms->hashSalt, 8) ^ ZSTD_bitmix((U64) ms->hashSaltEntropy, 4);
+}
+
+static size_t
+ZSTD_reset_matchState(ZSTD_MatchState_t* ms,
+                      ZSTD_cwksp* ws,
+                const ZSTD_compressionParameters* cParams,
+                const ZSTD_ParamSwitch_e useRowMatchFinder,
+                const ZSTD_compResetPolicy_e crp,
+                const ZSTD_indexResetPolicy_e forceResetIndex,
+                const ZSTD_resetTarget_e forWho)
+{
+    /* disable chain table allocation for fast or row-based strategies */
+    size_t const chainSize = ZSTD_allocateChainTable(cParams->strategy, useRowMatchFinder,
+                                                     ms->dedicatedDictSearch && (forWho == ZSTD_resetTarget_CDict))
+                                ? ((size_t)1 << cParams->chainLog)
+                                : 0;
+    size_t const hSize = ((size_t)1) << cParams->hashLog;
+    U32    const hashLog3 = ((forWho == ZSTD_resetTarget_CCtx) && cParams->minMatch==3) ? MIN(ZSTD_HASHLOG3_MAX, cParams->windowLog) : 0;
+    size_t const h3Size = hashLog3 ? ((size_t)1) << hashLog3 : 0;
+
+    DEBUGLOG(4, "reset indices : %u", forceResetIndex == ZSTDirp_reset);
+    assert(useRowMatchFinder != ZSTD_ps_auto);
+    if (forceResetIndex == ZSTDirp_reset) {
+        ZSTD_window_init(&ms->window);
+        ZSTD_cwksp_mark_tables_dirty(ws);
+    }
+
+    ms->hashLog3 = hashLog3;
+    ms->lazySkipping = 0;
+
+    ZSTD_invalidateMatchState(ms);
+
+    assert(!ZSTD_cwksp_reserve_failed(ws)); /* check that allocation hasn't already failed */
+
+    ZSTD_cwksp_clear_tables(ws);
+
+    DEBUGLOG(5, "reserving table space");
+    /* table Space */
+    ms->hashTable = (U32*)ZSTD_cwksp_reserve_table(ws, hSize * sizeof(U32));
+    ms->chainTable = (U32*)ZSTD_cwksp_reserve_table(ws, chainSize * sizeof(U32));
+    ms->hashTable3 = (U32*)ZSTD_cwksp_reserve_table(ws, h3Size * sizeof(U32));
+    RETURN_ERROR_IF(ZSTD_cwksp_reserve_failed(ws), memory_allocation,
+                    "failed a workspace allocation in ZSTD_reset_matchState");
+
+    DEBUGLOG(4, "reset table : %u", crp!=ZSTDcrp_leaveDirty);
+    if (crp!=ZSTDcrp_leaveDirty) {
+        /* reset tables only */
+        ZSTD_cwksp_clean_tables(ws);
+    }
+
+    if (ZSTD_rowMatchFinderUsed(cParams->strategy, useRowMatchFinder)) {
+        /* Row match finder needs an additional table of hashes ("tags") */
+        size_t const tagTableSize = hSize;
+        /* We want to generate a new salt in case we reset a Cctx, but we always want to use
+         * 0 when we reset a Cdict */
+        if(forWho == ZSTD_resetTarget_CCtx) {
+            ms->tagTable = (BYTE*) ZSTD_cwksp_reserve_aligned_init_once(ws, tagTableSize);
+            ZSTD_advanceHashSalt(ms);
+        } else {
+            /* When we are not salting we want to always memset the memory */
+            ms->tagTable = (BYTE*) ZSTD_cwksp_reserve_aligned64(ws, tagTableSize);
+            ZSTD_memset(ms->tagTable, 0, tagTableSize);
+            ms->hashSalt = 0;
+        }
+        {   /* Switch to 32-entry rows if searchLog is 5 (or more) */
+            U32 const rowLog = BOUNDED(4, cParams->searchLog, 6);
+            assert(cParams->hashLog >= rowLog);
+            ms->rowHashLog = cParams->hashLog - rowLog;
+        }
+    }
+
+    /* opt parser space */
+    if ((forWho == ZSTD_resetTarget_CCtx) && (cParams->strategy >= ZSTD_btopt)) {
+        DEBUGLOG(4, "reserving optimal parser space");
+        ms->opt.litFreq = (unsigned*)ZSTD_cwksp_reserve_aligned64(ws, (1<<Litbits) * sizeof(unsigned));
+        ms->opt.litLengthFreq = (unsigned*)ZSTD_cwksp_reserve_aligned64(ws, (MaxLL+1) * sizeof(unsigned));
+        ms->opt.matchLengthFreq = (unsigned*)ZSTD_cwksp_reserve_aligned64(ws, (MaxML+1) * sizeof(unsigned));
+        ms->opt.offCodeFreq = (unsigned*)ZSTD_cwksp_reserve_aligned64(ws, (MaxOff+1) * sizeof(unsigned));
+        ms->opt.matchTable = (ZSTD_match_t*)ZSTD_cwksp_reserve_aligned64(ws, ZSTD_OPT_SIZE * sizeof(ZSTD_match_t));
+        ms->opt.priceTable = (ZSTD_optimal_t*)ZSTD_cwksp_reserve_aligned64(ws, ZSTD_OPT_SIZE * sizeof(ZSTD_optimal_t));
+    }
+
+    ms->cParams = *cParams;
+
+    RETURN_ERROR_IF(ZSTD_cwksp_reserve_failed(ws), memory_allocation,
+                    "failed a workspace allocation in ZSTD_reset_matchState");
+    return 0;
+}
+
+/* ZSTD_indexTooCloseToMax() :
+ * minor optimization : prefer memset() rather than reduceIndex()
+ * which is measurably slow in some circumstances (reported for Visual Studio).
+ * Works when re-using a context for a lot of smallish inputs :
+ * if all inputs are smaller than ZSTD_INDEXOVERFLOW_MARGIN,
+ * memset() will be triggered before reduceIndex().
+ */
+#define ZSTD_INDEXOVERFLOW_MARGIN (16 MB)
+static int ZSTD_indexTooCloseToMax(ZSTD_window_t w)
+{
+    return (size_t)(w.nextSrc - w.base) > (ZSTD_CURRENT_MAX - ZSTD_INDEXOVERFLOW_MARGIN);
+}
+
+/** ZSTD_dictTooBig():
+ * When dictionaries are larger than ZSTD_CHUNKSIZE_MAX they can't be loaded in
+ * one go generically. So we ensure that in that case we reset the tables to zero,
+ * so that we can load as much of the dictionary as possible.
+ */
+static int ZSTD_dictTooBig(size_t const loadedDictSize)
+{
+    return loadedDictSize > ZSTD_CHUNKSIZE_MAX;
+}
+
+/*! ZSTD_resetCCtx_internal() :
+ * @param loadedDictSize The size of the dictionary to be loaded
+ * into the context, if any. If no dictionary is used, or the
+ * dictionary is being attached / copied, then pass 0.
+ * note : `params` are assumed fully validated at this stage.
+ */
+static size_t ZSTD_resetCCtx_internal(ZSTD_CCtx* zc,
+                                      ZSTD_CCtx_params const* params,
+                                      U64 const pledgedSrcSize,
+                                      size_t const loadedDictSize,
+                                      ZSTD_compResetPolicy_e const crp,
+                                      ZSTD_buffered_policy_e const zbuff)
+{
+    ZSTD_cwksp* const ws = &zc->workspace;
+    DEBUGLOG(4, "ZSTD_resetCCtx_internal: pledgedSrcSize=%u, wlog=%u, useRowMatchFinder=%d useBlockSplitter=%d",
+                (U32)pledgedSrcSize, params->cParams.windowLog, (int)params->useRowMatchFinder, (int)params->postBlockSplitter);
+    assert(!ZSTD_isError(ZSTD_checkCParams(params->cParams)));
+
+    zc->isFirstBlock = 1;
+
+    /* Set applied params early so we can modify them for LDM,
+     * and point params at the applied params.
+     */
+    zc->appliedParams = *params;
+    params = &zc->appliedParams;
+
+    assert(params->useRowMatchFinder != ZSTD_ps_auto);
+    assert(params->postBlockSplitter != ZSTD_ps_auto);
+    assert(params->ldmParams.enableLdm != ZSTD_ps_auto);
+    assert(params->maxBlockSize != 0);
+    if (params->ldmParams.enableLdm == ZSTD_ps_enable) {
+        /* Adjust long distance matching parameters */
+        ZSTD_ldm_adjustParameters(&zc->appliedParams.ldmParams, &params->cParams);
+        assert(params->ldmParams.hashLog >= params->ldmParams.bucketSizeLog);
+        assert(params->ldmParams.hashRateLog < 32);
+    }
+
+    {   size_t const windowSize = MAX(1, (size_t)MIN(((U64)1 << params->cParams.windowLog), pledgedSrcSize));
+        size_t const blockSize = MIN(params->maxBlockSize, windowSize);
+        size_t const maxNbSeq = ZSTD_maxNbSeq(blockSize, params->cParams.minMatch, ZSTD_hasExtSeqProd(params));
+        size_t const buffOutSize = (zbuff == ZSTDb_buffered && params->outBufferMode == ZSTD_bm_buffered)
+                ? ZSTD_compressBound(blockSize) + 1
+                : 0;
+        size_t const buffInSize = (zbuff == ZSTDb_buffered && params->inBufferMode == ZSTD_bm_buffered)
+                ? windowSize + blockSize
+                : 0;
+        size_t const maxNbLdmSeq = ZSTD_ldm_getMaxNbSeq(params->ldmParams, blockSize);
+
+        int const indexTooClose = ZSTD_indexTooCloseToMax(zc->blockState.matchState.window);
+        int const dictTooBig = ZSTD_dictTooBig(loadedDictSize);
+        ZSTD_indexResetPolicy_e needsIndexReset =
+            (indexTooClose || dictTooBig || !zc->initialized) ? ZSTDirp_reset : ZSTDirp_continue;
+
+        size_t const neededSpace =
+            ZSTD_estimateCCtxSize_usingCCtxParams_internal(
+                &params->cParams, &params->ldmParams, zc->staticSize != 0, params->useRowMatchFinder,
+                buffInSize, buffOutSize, pledgedSrcSize, ZSTD_hasExtSeqProd(params), params->maxBlockSize);
+
+        FORWARD_IF_ERROR(neededSpace, "cctx size estimate failed!");
+
+        if (!zc->staticSize) ZSTD_cwksp_bump_oversized_duration(ws, 0);
+
+        {   /* Check if workspace is large enough, alloc a new one if needed */
+            int const workspaceTooSmall = ZSTD_cwksp_sizeof(ws) < neededSpace;
+            int const workspaceWasteful = ZSTD_cwksp_check_wasteful(ws, neededSpace);
+            int resizeWorkspace = workspaceTooSmall || workspaceWasteful;
+            DEBUGLOG(4, "Need %zu B workspace", neededSpace);
+            DEBUGLOG(4, "windowSize: %zu - blockSize: %zu", windowSize, blockSize);
+
+            if (resizeWorkspace) {
+                DEBUGLOG(4, "Resize workspaceSize from %zuKB to %zuKB",
+                            ZSTD_cwksp_sizeof(ws) >> 10,
+                            neededSpace >> 10);
+
+                RETURN_ERROR_IF(zc->staticSize, memory_allocation, "static cctx : no resize");
+
+                needsIndexReset = ZSTDirp_reset;
+
+                ZSTD_cwksp_free(ws, zc->customMem);
+                FORWARD_IF_ERROR(ZSTD_cwksp_create(ws, neededSpace, zc->customMem), "");
+
+                DEBUGLOG(5, "reserving object space");
+                /* Statically sized space.
+                 * tmpWorkspace never moves,
+                 * though prev/next block swap places */
+                assert(ZSTD_cwksp_check_available(ws, 2 * sizeof(ZSTD_compressedBlockState_t)));
+                zc->blockState.prevCBlock = (ZSTD_compressedBlockState_t*) ZSTD_cwksp_reserve_object(ws, sizeof(ZSTD_compressedBlockState_t));
+                RETURN_ERROR_IF(zc->blockState.prevCBlock == NULL, memory_allocation, "couldn't allocate prevCBlock");
+                zc->blockState.nextCBlock = (ZSTD_compressedBlockState_t*) ZSTD_cwksp_reserve_object(ws, sizeof(ZSTD_compressedBlockState_t));
+                RETURN_ERROR_IF(zc->blockState.nextCBlock == NULL, memory_allocation, "couldn't allocate nextCBlock");
+                zc->tmpWorkspace = ZSTD_cwksp_reserve_object(ws, TMP_WORKSPACE_SIZE);
+                RETURN_ERROR_IF(zc->tmpWorkspace == NULL, memory_allocation, "couldn't allocate tmpWorkspace");
+                zc->tmpWkspSize = TMP_WORKSPACE_SIZE;
+        }   }
+
+        ZSTD_cwksp_clear(ws);
+
+        /* init params */
+        zc->blockState.matchState.cParams = params->cParams;
+        zc->blockState.matchState.prefetchCDictTables = params->prefetchCDictTables == ZSTD_ps_enable;
+        zc->pledgedSrcSizePlusOne = pledgedSrcSize+1;
+        zc->consumedSrcSize = 0;
+        zc->producedCSize = 0;
+        if (pledgedSrcSize == ZSTD_CONTENTSIZE_UNKNOWN)
+            zc->appliedParams.fParams.contentSizeFlag = 0;
+        DEBUGLOG(4, "pledged content size : %u ; flag : %u",
+            (unsigned)pledgedSrcSize, zc->appliedParams.fParams.contentSizeFlag);
+        zc->blockSizeMax = blockSize;
+
+        XXH64_reset(&zc->xxhState, 0);
+        zc->stage = ZSTDcs_init;
+        zc->dictID = 0;
+        zc->dictContentSize = 0;
+
+        ZSTD_reset_compressedBlockState(zc->blockState.prevCBlock);
+
+        FORWARD_IF_ERROR(ZSTD_reset_matchState(
+                &zc->blockState.matchState,
+                ws,
+                &params->cParams,
+                params->useRowMatchFinder,
+                crp,
+                needsIndexReset,
+                ZSTD_resetTarget_CCtx), "");
+
+        zc->seqStore.sequencesStart = (SeqDef*)ZSTD_cwksp_reserve_aligned64(ws, maxNbSeq * sizeof(SeqDef));
+
+        /* ldm hash table */
+        if (params->ldmParams.enableLdm == ZSTD_ps_enable) {
+            /* TODO: avoid memset? */
+            size_t const ldmHSize = ((size_t)1) << params->ldmParams.hashLog;
+            zc->ldmState.hashTable = (ldmEntry_t*)ZSTD_cwksp_reserve_aligned64(ws, ldmHSize * sizeof(ldmEntry_t));
+            ZSTD_memset(zc->ldmState.hashTable, 0, ldmHSize * sizeof(ldmEntry_t));
+            zc->ldmSequences = (rawSeq*)ZSTD_cwksp_reserve_aligned64(ws, maxNbLdmSeq * sizeof(rawSeq));
+            zc->maxNbLdmSequences = maxNbLdmSeq;
+
+            ZSTD_window_init(&zc->ldmState.window);
+            zc->ldmState.loadedDictEnd = 0;
+        }
+
+        /* reserve space for block-level external sequences */
+        if (ZSTD_hasExtSeqProd(params)) {
+            size_t const maxNbExternalSeq = ZSTD_sequenceBound(blockSize);
+            zc->extSeqBufCapacity = maxNbExternalSeq;
+            zc->extSeqBuf =
+                (ZSTD_Sequence*)ZSTD_cwksp_reserve_aligned64(ws, maxNbExternalSeq * sizeof(ZSTD_Sequence));
+        }
+
+        /* buffers */
+
+        /* ZSTD_wildcopy() is used to copy into the literals buffer,
+         * so we have to oversize the buffer by WILDCOPY_OVERLENGTH bytes.
+         */
+        zc->seqStore.litStart = ZSTD_cwksp_reserve_buffer(ws, blockSize + WILDCOPY_OVERLENGTH);
+        zc->seqStore.maxNbLit = blockSize;
+
+        zc->bufferedPolicy = zbuff;
+        zc->inBuffSize = buffInSize;
+        zc->inBuff = (char*)ZSTD_cwksp_reserve_buffer(ws, buffInSize);
+        zc->outBuffSize = buffOutSize;
+        zc->outBuff = (char*)ZSTD_cwksp_reserve_buffer(ws, buffOutSize);
+
+        /* ldm bucketOffsets table */
+        if (params->ldmParams.enableLdm == ZSTD_ps_enable) {
+            /* TODO: avoid memset? */
+            size_t const numBuckets =
+                  ((size_t)1) << (params->ldmParams.hashLog -
+                                  params->ldmParams.bucketSizeLog);
+            zc->ldmState.bucketOffsets = ZSTD_cwksp_reserve_buffer(ws, numBuckets);
+            ZSTD_memset(zc->ldmState.bucketOffsets, 0, numBuckets);
+        }
+
+        /* sequences storage */
+        ZSTD_referenceExternalSequences(zc, NULL, 0);
+        zc->seqStore.maxNbSeq = maxNbSeq;
+        zc->seqStore.llCode = ZSTD_cwksp_reserve_buffer(ws, maxNbSeq * sizeof(BYTE));
+        zc->seqStore.mlCode = ZSTD_cwksp_reserve_buffer(ws, maxNbSeq * sizeof(BYTE));
+        zc->seqStore.ofCode = ZSTD_cwksp_reserve_buffer(ws, maxNbSeq * sizeof(BYTE));
+
+        DEBUGLOG(3, "wksp: finished allocating, %zd bytes remain available", ZSTD_cwksp_available_space(ws));
+        assert(ZSTD_cwksp_estimated_space_within_bounds(ws, neededSpace));
+
+        zc->initialized = 1;
+
+        return 0;
+    }
+}
+
+/* ZSTD_invalidateRepCodes() :
+ * ensures next compression will not use repcodes from previous block.
+ * Note : only works with regular variant;
+ *        do not use with extDict variant ! */
+void ZSTD_invalidateRepCodes(ZSTD_CCtx* cctx) {
+    int i;
+    for (i=0; i<ZSTD_REP_NUM; i++) cctx->blockState.prevCBlock->rep[i] = 0;
+    assert(!ZSTD_window_hasExtDict(cctx->blockState.matchState.window));
+}
+
+/* These are the approximate sizes for each strategy past which copying the
+ * dictionary tables into the working context is faster than using them
+ * in-place.
+ */
+static const size_t attachDictSizeCutoffs[ZSTD_STRATEGY_MAX+1] = {
+    8 KB,  /* unused */
+    8 KB,  /* ZSTD_fast */
+    16 KB, /* ZSTD_dfast */
+    32 KB, /* ZSTD_greedy */
+    32 KB, /* ZSTD_lazy */
+    32 KB, /* ZSTD_lazy2 */
+    32 KB, /* ZSTD_btlazy2 */
+    32 KB, /* ZSTD_btopt */
+    8 KB,  /* ZSTD_btultra */
+    8 KB   /* ZSTD_btultra2 */
+};
+
+static int ZSTD_shouldAttachDict(const ZSTD_CDict* cdict,
+                                 const ZSTD_CCtx_params* params,
+                                 U64 pledgedSrcSize)
+{
+    size_t cutoff = attachDictSizeCutoffs[cdict->matchState.cParams.strategy];
+    int const dedicatedDictSearch = cdict->matchState.dedicatedDictSearch;
+    return dedicatedDictSearch
+        || ( ( pledgedSrcSize <= cutoff
+            || pledgedSrcSize == ZSTD_CONTENTSIZE_UNKNOWN
+            || params->attachDictPref == ZSTD_dictForceAttach )
+          && params->attachDictPref != ZSTD_dictForceCopy
+          && !params->forceWindow ); /* dictMatchState isn't correctly
+                                      * handled in _enforceMaxDist */
+}
+
+static size_t
+ZSTD_resetCCtx_byAttachingCDict(ZSTD_CCtx* cctx,
+                        const ZSTD_CDict* cdict,
+                        ZSTD_CCtx_params params,
+                        U64 pledgedSrcSize,
+                        ZSTD_buffered_policy_e zbuff)
+{
+    DEBUGLOG(4, "ZSTD_resetCCtx_byAttachingCDict() pledgedSrcSize=%llu",
+                (unsigned long long)pledgedSrcSize);
+    {
+        ZSTD_compressionParameters adjusted_cdict_cParams = cdict->matchState.cParams;
+        unsigned const windowLog = params.cParams.windowLog;
+        assert(windowLog != 0);
+        /* Resize working context table params for input only, since the dict
+         * has its own tables. */
+        /* pledgedSrcSize == 0 means 0! */
+
+        if (cdict->matchState.dedicatedDictSearch) {
+            ZSTD_dedicatedDictSearch_revertCParams(&adjusted_cdict_cParams);
+        }
+
+        params.cParams = ZSTD_adjustCParams_internal(adjusted_cdict_cParams, pledgedSrcSize,
+                                                     cdict->dictContentSize, ZSTD_cpm_attachDict,
+                                                     params.useRowMatchFinder);
+        params.cParams.windowLog = windowLog;
+        params.useRowMatchFinder = cdict->useRowMatchFinder;    /* cdict overrides */
+        FORWARD_IF_ERROR(ZSTD_resetCCtx_internal(cctx, &params, pledgedSrcSize,
+                                                 /* loadedDictSize */ 0,
+                                                 ZSTDcrp_makeClean, zbuff), "");
+        assert(cctx->appliedParams.cParams.strategy == adjusted_cdict_cParams.strategy);
+    }
+
+    {   const U32 cdictEnd = (U32)( cdict->matchState.window.nextSrc
+                                  - cdict->matchState.window.base);
+        const U32 cdictLen = cdictEnd - cdict->matchState.window.dictLimit;
+        if (cdictLen == 0) {
+            /* don't even attach dictionaries with no contents */
+            DEBUGLOG(4, "skipping attaching empty dictionary");
+        } else {
+            DEBUGLOG(4, "attaching dictionary into context");
+            cctx->blockState.matchState.dictMatchState = &cdict->matchState;
+
+            /* prep working match state so dict matches never have negative indices
+             * when they are translated to the working context's index space. */
+            if (cctx->blockState.matchState.window.dictLimit < cdictEnd) {
+                cctx->blockState.matchState.window.nextSrc =
+                    cctx->blockState.matchState.window.base + cdictEnd;
+                ZSTD_window_clear(&cctx->blockState.matchState.window);
+            }
+            /* loadedDictEnd is expressed within the referential of the active context */
+            cctx->blockState.matchState.loadedDictEnd = cctx->blockState.matchState.window.dictLimit;
+    }   }
+
+    cctx->dictID = cdict->dictID;
+    cctx->dictContentSize = cdict->dictContentSize;
+
+    /* copy block state */
+    ZSTD_memcpy(cctx->blockState.prevCBlock, &cdict->cBlockState, sizeof(cdict->cBlockState));
+
+    return 0;
+}
+
+static void ZSTD_copyCDictTableIntoCCtx(U32* dst, U32 const* src, size_t tableSize,
+                                        ZSTD_compressionParameters const* cParams) {
+    if (ZSTD_CDictIndicesAreTagged(cParams)){
+        /* Remove tags from the CDict table if they are present.
+         * See docs on "short cache" in zstd_compress_internal.h for context. */
+        size_t i;
+        for (i = 0; i < tableSize; i++) {
+            U32 const taggedIndex = src[i];
+            U32 const index = taggedIndex >> ZSTD_SHORT_CACHE_TAG_BITS;
+            dst[i] = index;
+        }
+    } else {
+        ZSTD_memcpy(dst, src, tableSize * sizeof(U32));
+    }
+}
+
+static size_t ZSTD_resetCCtx_byCopyingCDict(ZSTD_CCtx* cctx,
+                            const ZSTD_CDict* cdict,
+                            ZSTD_CCtx_params params,
+                            U64 pledgedSrcSize,
+                            ZSTD_buffered_policy_e zbuff)
+{
+    const ZSTD_compressionParameters *cdict_cParams = &cdict->matchState.cParams;
+
+    assert(!cdict->matchState.dedicatedDictSearch);
+    DEBUGLOG(4, "ZSTD_resetCCtx_byCopyingCDict() pledgedSrcSize=%llu",
+                (unsigned long long)pledgedSrcSize);
+
+    {   unsigned const windowLog = params.cParams.windowLog;
+        assert(windowLog != 0);
+        /* Copy only compression parameters related to tables. */
+        params.cParams = *cdict_cParams;
+        params.cParams.windowLog = windowLog;
+        params.useRowMatchFinder = cdict->useRowMatchFinder;
+        FORWARD_IF_ERROR(ZSTD_resetCCtx_internal(cctx, &params, pledgedSrcSize,
+                                                 /* loadedDictSize */ 0,
+                                                 ZSTDcrp_leaveDirty, zbuff), "");
+        assert(cctx->appliedParams.cParams.strategy == cdict_cParams->strategy);
+        assert(cctx->appliedParams.cParams.hashLog == cdict_cParams->hashLog);
+        assert(cctx->appliedParams.cParams.chainLog == cdict_cParams->chainLog);
+    }
+
+    ZSTD_cwksp_mark_tables_dirty(&cctx->workspace);
+    assert(params.useRowMatchFinder != ZSTD_ps_auto);
+
+    /* copy tables */
+    {   size_t const chainSize = ZSTD_allocateChainTable(cdict_cParams->strategy, cdict->useRowMatchFinder, 0 /* DDS guaranteed disabled */)
+                                                            ? ((size_t)1 << cdict_cParams->chainLog)
+                                                            : 0;
+        size_t const hSize =  (size_t)1 << cdict_cParams->hashLog;
+
+        ZSTD_copyCDictTableIntoCCtx(cctx->blockState.matchState.hashTable,
+                                cdict->matchState.hashTable,
+                                hSize, cdict_cParams);
+
+        /* Do not copy cdict's chainTable if cctx has parameters such that it would not use chainTable */
+        if (ZSTD_allocateChainTable(cctx->appliedParams.cParams.strategy, cctx->appliedParams.useRowMatchFinder, 0 /* forDDSDict */)) {
+            ZSTD_copyCDictTableIntoCCtx(cctx->blockState.matchState.chainTable,
+                                    cdict->matchState.chainTable,
+                                    chainSize, cdict_cParams);
+        }
+        /* copy tag table */
+        if (ZSTD_rowMatchFinderUsed(cdict_cParams->strategy, cdict->useRowMatchFinder)) {
+            size_t const tagTableSize = hSize;
+            ZSTD_memcpy(cctx->blockState.matchState.tagTable,
+                        cdict->matchState.tagTable,
+                        tagTableSize);
+            cctx->blockState.matchState.hashSalt = cdict->matchState.hashSalt;
+        }
+    }
+
+    /* Zero the hashTable3, since the cdict never fills it */
+    assert(cctx->blockState.matchState.hashLog3 <= 31);
+    {   U32 const h3log = cctx->blockState.matchState.hashLog3;
+        size_t const h3Size = h3log ? ((size_t)1 << h3log) : 0;
+        assert(cdict->matchState.hashLog3 == 0);
+        ZSTD_memset(cctx->blockState.matchState.hashTable3, 0, h3Size * sizeof(U32));
+    }
+
+    ZSTD_cwksp_mark_tables_clean(&cctx->workspace);
+
+    /* copy dictionary offsets */
+    {   ZSTD_MatchState_t const* srcMatchState = &cdict->matchState;
+        ZSTD_MatchState_t* dstMatchState = &cctx->blockState.matchState;
+        dstMatchState->window       = srcMatchState->window;
+        dstMatchState->nextToUpdate = srcMatchState->nextToUpdate;
+        dstMatchState->loadedDictEnd= srcMatchState->loadedDictEnd;
+    }
+
+    cctx->dictID = cdict->dictID;
+    cctx->dictContentSize = cdict->dictContentSize;
+
+    /* copy block state */
+    ZSTD_memcpy(cctx->blockState.prevCBlock, &cdict->cBlockState, sizeof(cdict->cBlockState));
+
+    return 0;
+}
+
+/* We have a choice between copying the dictionary context into the working
+ * context, or referencing the dictionary context from the working context
+ * in-place. We decide here which strategy to use. */
+static size_t ZSTD_resetCCtx_usingCDict(ZSTD_CCtx* cctx,
+                            const ZSTD_CDict* cdict,
+                            const ZSTD_CCtx_params* params,
+                            U64 pledgedSrcSize,
+                            ZSTD_buffered_policy_e zbuff)
+{
+
+    DEBUGLOG(4, "ZSTD_resetCCtx_usingCDict (pledgedSrcSize=%u)",
+                (unsigned)pledgedSrcSize);
+
+    if (ZSTD_shouldAttachDict(cdict, params, pledgedSrcSize)) {
+        return ZSTD_resetCCtx_byAttachingCDict(
+            cctx, cdict, *params, pledgedSrcSize, zbuff);
+    } else {
+        return ZSTD_resetCCtx_byCopyingCDict(
+            cctx, cdict, *params, pledgedSrcSize, zbuff);
+    }
+}
+
+/*! ZSTD_copyCCtx_internal() :
+ *  Duplicate an existing context `srcCCtx` into another one `dstCCtx`.
+ *  Only works during stage ZSTDcs_init (i.e. after creation, but before first call to ZSTD_compressContinue()).
+ *  The "context", in this case, refers to the hash and chain tables,
+ *  entropy tables, and dictionary references.
+ * `windowLog` value is enforced if != 0, otherwise value is copied from srcCCtx.
+ * @return : 0, or an error code */
+static size_t ZSTD_copyCCtx_internal(ZSTD_CCtx* dstCCtx,
+                            const ZSTD_CCtx* srcCCtx,
+                            ZSTD_frameParameters fParams,
+                            U64 pledgedSrcSize,
+                            ZSTD_buffered_policy_e zbuff)
+{
+    RETURN_ERROR_IF(srcCCtx->stage!=ZSTDcs_init, stage_wrong,
+                    "Can't copy a ctx that's not in init stage.");
+    DEBUGLOG(5, "ZSTD_copyCCtx_internal");
+    ZSTD_memcpy(&dstCCtx->customMem, &srcCCtx->customMem, sizeof(ZSTD_customMem));
+    {   ZSTD_CCtx_params params = dstCCtx->requestedParams;
+        /* Copy only compression parameters related to tables. */
+        params.cParams = srcCCtx->appliedParams.cParams;
+        assert(srcCCtx->appliedParams.useRowMatchFinder != ZSTD_ps_auto);
+        assert(srcCCtx->appliedParams.postBlockSplitter != ZSTD_ps_auto);
+        assert(srcCCtx->appliedParams.ldmParams.enableLdm != ZSTD_ps_auto);
+        params.useRowMatchFinder = srcCCtx->appliedParams.useRowMatchFinder;
+        params.postBlockSplitter = srcCCtx->appliedParams.postBlockSplitter;
+        params.ldmParams = srcCCtx->appliedParams.ldmParams;
+        params.fParams = fParams;
+        params.maxBlockSize = srcCCtx->appliedParams.maxBlockSize;
+        ZSTD_resetCCtx_internal(dstCCtx, &params, pledgedSrcSize,
+                                /* loadedDictSize */ 0,
+                                ZSTDcrp_leaveDirty, zbuff);
+        assert(dstCCtx->appliedParams.cParams.windowLog == srcCCtx->appliedParams.cParams.windowLog);
+        assert(dstCCtx->appliedParams.cParams.strategy == srcCCtx->appliedParams.cParams.strategy);
+        assert(dstCCtx->appliedParams.cParams.hashLog == srcCCtx->appliedParams.cParams.hashLog);
+        assert(dstCCtx->appliedParams.cParams.chainLog == srcCCtx->appliedParams.cParams.chainLog);
+        assert(dstCCtx->blockState.matchState.hashLog3 == srcCCtx->blockState.matchState.hashLog3);
+    }
+
+    ZSTD_cwksp_mark_tables_dirty(&dstCCtx->workspace);
+
+    /* copy tables */
+    {   size_t const chainSize = ZSTD_allocateChainTable(srcCCtx->appliedParams.cParams.strategy,
+                                                         srcCCtx->appliedParams.useRowMatchFinder,
+                                                         0 /* forDDSDict */)
+                                    ? ((size_t)1 << srcCCtx->appliedParams.cParams.chainLog)
+                                    : 0;
+        size_t const hSize =  (size_t)1 << srcCCtx->appliedParams.cParams.hashLog;
+        U32 const h3log = srcCCtx->blockState.matchState.hashLog3;
+        size_t const h3Size = h3log ? ((size_t)1 << h3log) : 0;
+
+        ZSTD_memcpy(dstCCtx->blockState.matchState.hashTable,
+               srcCCtx->blockState.matchState.hashTable,
+               hSize * sizeof(U32));
+        ZSTD_memcpy(dstCCtx->blockState.matchState.chainTable,
+               srcCCtx->blockState.matchState.chainTable,
+               chainSize * sizeof(U32));
+        ZSTD_memcpy(dstCCtx->blockState.matchState.hashTable3,
+               srcCCtx->blockState.matchState.hashTable3,
+               h3Size * sizeof(U32));
+    }
+
+    ZSTD_cwksp_mark_tables_clean(&dstCCtx->workspace);
+
+    /* copy dictionary offsets */
+    {
+        const ZSTD_MatchState_t* srcMatchState = &srcCCtx->blockState.matchState;
+        ZSTD_MatchState_t* dstMatchState = &dstCCtx->blockState.matchState;
+        dstMatchState->window       = srcMatchState->window;
+        dstMatchState->nextToUpdate = srcMatchState->nextToUpdate;
+        dstMatchState->loadedDictEnd= srcMatchState->loadedDictEnd;
+    }
+    dstCCtx->dictID = srcCCtx->dictID;
+    dstCCtx->dictContentSize = srcCCtx->dictContentSize;
+
+    /* copy block state */
+    ZSTD_memcpy(dstCCtx->blockState.prevCBlock, srcCCtx->blockState.prevCBlock, sizeof(*srcCCtx->blockState.prevCBlock));
+
+    return 0;
+}
+
+/*! ZSTD_copyCCtx() :
+ *  Duplicate an existing context `srcCCtx` into another one `dstCCtx`.
+ *  Only works during stage ZSTDcs_init (i.e. after creation, but before first call to ZSTD_compressContinue()).
+ *  pledgedSrcSize==0 means "unknown".
+*   @return : 0, or an error code */
+size_t ZSTD_copyCCtx(ZSTD_CCtx* dstCCtx, const ZSTD_CCtx* srcCCtx, unsigned long long pledgedSrcSize)
+{
+    ZSTD_frameParameters fParams = { 1 /*content*/, 0 /*checksum*/, 0 /*noDictID*/ };
+    ZSTD_buffered_policy_e const zbuff = srcCCtx->bufferedPolicy;
+    ZSTD_STATIC_ASSERT((U32)ZSTDb_buffered==1);
+    if (pledgedSrcSize==0) pledgedSrcSize = ZSTD_CONTENTSIZE_UNKNOWN;
+    fParams.contentSizeFlag = (pledgedSrcSize != ZSTD_CONTENTSIZE_UNKNOWN);
+
+    return ZSTD_copyCCtx_internal(dstCCtx, srcCCtx,
+                                fParams, pledgedSrcSize,
+                                zbuff);
+}
+
+
+#define ZSTD_ROWSIZE 16
+/*! ZSTD_reduceTable() :
+ *  reduce table indexes by `reducerValue`, or squash to zero.
+ *  PreserveMark preserves "unsorted mark" for btlazy2 strategy.
+ *  It must be set to a clear 0/1 value, to remove branch during inlining.
+ *  Presume table size is a multiple of ZSTD_ROWSIZE
+ *  to help auto-vectorization */
+FORCE_INLINE_TEMPLATE void
+ZSTD_reduceTable_internal (U32* const table, U32 const size, U32 const reducerValue, int const preserveMark)
+{
+    int const nbRows = (int)size / ZSTD_ROWSIZE;
+    int cellNb = 0;
+    int rowNb;
+    /* Protect special index values < ZSTD_WINDOW_START_INDEX. */
+    U32 const reducerThreshold = reducerValue + ZSTD_WINDOW_START_INDEX;
+    assert((size & (ZSTD_ROWSIZE-1)) == 0);  /* multiple of ZSTD_ROWSIZE */
+    assert(size < (1U<<31));   /* can be cast to int */
+
+#if ZSTD_MEMORY_SANITIZER && !defined (ZSTD_MSAN_DONT_POISON_WORKSPACE)
+    /* To validate that the table reuse logic is sound, and that we don't
+     * access table space that we haven't cleaned, we re-"poison" the table
+     * space every time we mark it dirty.
+     *
+     * This function however is intended to operate on those dirty tables and
+     * re-clean them. So when this function is used correctly, we can unpoison
+     * the memory it operated on. This introduces a blind spot though, since
+     * if we now try to operate on __actually__ poisoned memory, we will not
+     * detect that. */
+    __msan_unpoison(table, size * sizeof(U32));
+#endif
+
+    for (rowNb=0 ; rowNb < nbRows ; rowNb++) {
+        int column;
+        for (column=0; column<ZSTD_ROWSIZE; column++) {
+            U32 newVal;
+            if (preserveMark && table[cellNb] == ZSTD_DUBT_UNSORTED_MARK) {
+                /* This write is pointless, but is required(?) for the compiler
+                 * to auto-vectorize the loop. */
+                newVal = ZSTD_DUBT_UNSORTED_MARK;
+            } else if (table[cellNb] < reducerThreshold) {
+                newVal = 0;
+            } else {
+                newVal = table[cellNb] - reducerValue;
+            }
+            table[cellNb] = newVal;
+            cellNb++;
+    }   }
+}
+
+static void ZSTD_reduceTable(U32* const table, U32 const size, U32 const reducerValue)
+{
+    ZSTD_reduceTable_internal(table, size, reducerValue, 0);
+}
+
+static void ZSTD_reduceTable_btlazy2(U32* const table, U32 const size, U32 const reducerValue)
+{
+    ZSTD_reduceTable_internal(table, size, reducerValue, 1);
+}
+
+/*! ZSTD_reduceIndex() :
+*   rescale all indexes to avoid future overflow (indexes are U32) */
+static void ZSTD_reduceIndex (ZSTD_MatchState_t* ms, ZSTD_CCtx_params const* params, const U32 reducerValue)
+{
+    {   U32 const hSize = (U32)1 << params->cParams.hashLog;
+        ZSTD_reduceTable(ms->hashTable, hSize, reducerValue);
+    }
+
+    if (ZSTD_allocateChainTable(params->cParams.strategy, params->useRowMatchFinder, (U32)ms->dedicatedDictSearch)) {
+        U32 const chainSize = (U32)1 << params->cParams.chainLog;
+        if (params->cParams.strategy == ZSTD_btlazy2)
+            ZSTD_reduceTable_btlazy2(ms->chainTable, chainSize, reducerValue);
+        else
+            ZSTD_reduceTable(ms->chainTable, chainSize, reducerValue);
+    }
+
+    if (ms->hashLog3) {
+        U32 const h3Size = (U32)1 << ms->hashLog3;
+        ZSTD_reduceTable(ms->hashTable3, h3Size, reducerValue);
+    }
+}
+
+
+/*-*******************************************************
+*  Block entropic compression
+*********************************************************/
+
+/* See doc/zstd_compression_format.md for detailed format description */
+
+int ZSTD_seqToCodes(const SeqStore_t* seqStorePtr)
+{
+    const SeqDef* const sequences = seqStorePtr->sequencesStart;
+    BYTE* const llCodeTable = seqStorePtr->llCode;
+    BYTE* const ofCodeTable = seqStorePtr->ofCode;
+    BYTE* const mlCodeTable = seqStorePtr->mlCode;
+    U32 const nbSeq = (U32)(seqStorePtr->sequences - seqStorePtr->sequencesStart);
+    U32 u;
+    int longOffsets = 0;
+    assert(nbSeq <= seqStorePtr->maxNbSeq);
+    for (u=0; u<nbSeq; u++) {
+        U32 const llv = sequences[u].litLength;
+        U32 const ofCode = ZSTD_highbit32(sequences[u].offBase);
+        U32 const mlv = sequences[u].mlBase;
+        llCodeTable[u] = (BYTE)ZSTD_LLcode(llv);
+        ofCodeTable[u] = (BYTE)ofCode;
+        mlCodeTable[u] = (BYTE)ZSTD_MLcode(mlv);
+        assert(!(MEM_64bits() && ofCode >= STREAM_ACCUMULATOR_MIN));
+        if (MEM_32bits() && ofCode >= STREAM_ACCUMULATOR_MIN)
+            longOffsets = 1;
+    }
+    if (seqStorePtr->longLengthType==ZSTD_llt_literalLength)
+        llCodeTable[seqStorePtr->longLengthPos] = MaxLL;
+    if (seqStorePtr->longLengthType==ZSTD_llt_matchLength)
+        mlCodeTable[seqStorePtr->longLengthPos] = MaxML;
+    return longOffsets;
+}
+
+/* ZSTD_useTargetCBlockSize():
+ * Returns if target compressed block size param is being used.
+ * If used, compression will do best effort to make a compressed block size to be around targetCBlockSize.
+ * Returns 1 if true, 0 otherwise. */
+static int ZSTD_useTargetCBlockSize(const ZSTD_CCtx_params* cctxParams)
+{
+    DEBUGLOG(5, "ZSTD_useTargetCBlockSize (targetCBlockSize=%zu)", cctxParams->targetCBlockSize);
+    return (cctxParams->targetCBlockSize != 0);
+}
+
+/* ZSTD_blockSplitterEnabled():
+ * Returns if block splitting param is being used
+ * If used, compression will do best effort to split a block in order to improve compression ratio.
+ * At the time this function is called, the parameter must be finalized.
+ * Returns 1 if true, 0 otherwise. */
+static int ZSTD_blockSplitterEnabled(ZSTD_CCtx_params* cctxParams)
+{
+    DEBUGLOG(5, "ZSTD_blockSplitterEnabled (postBlockSplitter=%d)", cctxParams->postBlockSplitter);
+    assert(cctxParams->postBlockSplitter != ZSTD_ps_auto);
+    return (cctxParams->postBlockSplitter == ZSTD_ps_enable);
+}
+
+/* Type returned by ZSTD_buildSequencesStatistics containing finalized symbol encoding types
+ * and size of the sequences statistics
+ */
+typedef struct {
+    U32 LLtype;
+    U32 Offtype;
+    U32 MLtype;
+    size_t size;
+    size_t lastCountSize; /* Accounts for bug in 1.3.4. More detail in ZSTD_entropyCompressSeqStore_internal() */
+    int longOffsets;
+} ZSTD_symbolEncodingTypeStats_t;
+
+/* ZSTD_buildSequencesStatistics():
+ * Returns a ZSTD_symbolEncodingTypeStats_t, or a zstd error code in the `size` field.
+ * Modifies `nextEntropy` to have the appropriate values as a side effect.
+ * nbSeq must be greater than 0.
+ *
+ * entropyWkspSize must be of size at least ENTROPY_WORKSPACE_SIZE - (MaxSeq + 1)*sizeof(U32)
+ */
+static ZSTD_symbolEncodingTypeStats_t
+ZSTD_buildSequencesStatistics(
+                const SeqStore_t* seqStorePtr, size_t nbSeq,
+                const ZSTD_fseCTables_t* prevEntropy, ZSTD_fseCTables_t* nextEntropy,
+                      BYTE* dst, const BYTE* const dstEnd,
+                      ZSTD_strategy strategy, unsigned* countWorkspace,
+                      void* entropyWorkspace, size_t entropyWkspSize)
+{
+    BYTE* const ostart = dst;
+    const BYTE* const oend = dstEnd;
+    BYTE* op = ostart;
+    FSE_CTable* CTable_LitLength = nextEntropy->litlengthCTable;
+    FSE_CTable* CTable_OffsetBits = nextEntropy->offcodeCTable;
+    FSE_CTable* CTable_MatchLength = nextEntropy->matchlengthCTable;
+    const BYTE* const ofCodeTable = seqStorePtr->ofCode;
+    const BYTE* const llCodeTable = seqStorePtr->llCode;
+    const BYTE* const mlCodeTable = seqStorePtr->mlCode;
+    ZSTD_symbolEncodingTypeStats_t stats;
+
+    stats.lastCountSize = 0;
+    /* convert length/distances into codes */
+    stats.longOffsets = ZSTD_seqToCodes(seqStorePtr);
+    assert(op <= oend);
+    assert(nbSeq != 0); /* ZSTD_selectEncodingType() divides by nbSeq */
+    /* build CTable for Literal Lengths */
+    {   unsigned max = MaxLL;
+        size_t const mostFrequent = HIST_countFast_wksp(countWorkspace, &max, llCodeTable, nbSeq, entropyWorkspace, entropyWkspSize);   /* can't fail */
+        DEBUGLOG(5, "Building LL table");
+        nextEntropy->litlength_repeatMode = prevEntropy->litlength_repeatMode;
+        stats.LLtype = ZSTD_selectEncodingType(&nextEntropy->litlength_repeatMode,
+                                        countWorkspace, max, mostFrequent, nbSeq,
+                                        LLFSELog, prevEntropy->litlengthCTable,
+                                        LL_defaultNorm, LL_defaultNormLog,
+                                        ZSTD_defaultAllowed, strategy);
+        assert(set_basic < set_compressed && set_rle < set_compressed);
+        assert(!(stats.LLtype < set_compressed && nextEntropy->litlength_repeatMode != FSE_repeat_none)); /* We don't copy tables */
+        {   size_t const countSize = ZSTD_buildCTable(
+                op, (size_t)(oend - op),
+                CTable_LitLength, LLFSELog, (SymbolEncodingType_e)stats.LLtype,
+                countWorkspace, max, llCodeTable, nbSeq,
+                LL_defaultNorm, LL_defaultNormLog, MaxLL,
+                prevEntropy->litlengthCTable,
+                sizeof(prevEntropy->litlengthCTable),
+                entropyWorkspace, entropyWkspSize);
+            if (ZSTD_isError(countSize)) {
+                DEBUGLOG(3, "ZSTD_buildCTable for LitLens failed");
+                stats.size = countSize;
+                return stats;
+            }
+            if (stats.LLtype == set_compressed)
+                stats.lastCountSize = countSize;
+            op += countSize;
+            assert(op <= oend);
+    }   }
+    /* build CTable for Offsets */
+    {   unsigned max = MaxOff;
+        size_t const mostFrequent = HIST_countFast_wksp(
+            countWorkspace, &max, ofCodeTable, nbSeq, entropyWorkspace, entropyWkspSize);  /* can't fail */
+        /* We can only use the basic table if max <= DefaultMaxOff, otherwise the offsets are too large */
+        ZSTD_DefaultPolicy_e const defaultPolicy = (max <= DefaultMaxOff) ? ZSTD_defaultAllowed : ZSTD_defaultDisallowed;
+        DEBUGLOG(5, "Building OF table");
+        nextEntropy->offcode_repeatMode = prevEntropy->offcode_repeatMode;
+        stats.Offtype = ZSTD_selectEncodingType(&nextEntropy->offcode_repeatMode,
+                                        countWorkspace, max, mostFrequent, nbSeq,
+                                        OffFSELog, prevEntropy->offcodeCTable,
+                                        OF_defaultNorm, OF_defaultNormLog,
+                                        defaultPolicy, strategy);
+        assert(!(stats.Offtype < set_compressed && nextEntropy->offcode_repeatMode != FSE_repeat_none)); /* We don't copy tables */
+        {   size_t const countSize = ZSTD_buildCTable(
+                op, (size_t)(oend - op),
+                CTable_OffsetBits, OffFSELog, (SymbolEncodingType_e)stats.Offtype,
+                countWorkspace, max, ofCodeTable, nbSeq,
+                OF_defaultNorm, OF_defaultNormLog, DefaultMaxOff,
+                prevEntropy->offcodeCTable,
+                sizeof(prevEntropy->offcodeCTable),
+                entropyWorkspace, entropyWkspSize);
+            if (ZSTD_isError(countSize)) {
+                DEBUGLOG(3, "ZSTD_buildCTable for Offsets failed");
+                stats.size = countSize;
+                return stats;
+            }
+            if (stats.Offtype == set_compressed)
+                stats.lastCountSize = countSize;
+            op += countSize;
+            assert(op <= oend);
+    }   }
+    /* build CTable for MatchLengths */
+    {   unsigned max = MaxML;
+        size_t const mostFrequent = HIST_countFast_wksp(
+            countWorkspace, &max, mlCodeTable, nbSeq, entropyWorkspace, entropyWkspSize);   /* can't fail */
+        DEBUGLOG(5, "Building ML table (remaining space : %i)", (int)(oend-op));
+        nextEntropy->matchlength_repeatMode = prevEntropy->matchlength_repeatMode;
+        stats.MLtype = ZSTD_selectEncodingType(&nextEntropy->matchlength_repeatMode,
+                                        countWorkspace, max, mostFrequent, nbSeq,
+                                        MLFSELog, prevEntropy->matchlengthCTable,
+                                        ML_defaultNorm, ML_defaultNormLog,
+                                        ZSTD_defaultAllowed, strategy);
+        assert(!(stats.MLtype < set_compressed && nextEntropy->matchlength_repeatMode != FSE_repeat_none)); /* We don't copy tables */
+        {   size_t const countSize = ZSTD_buildCTable(
+                op, (size_t)(oend - op),
+                CTable_MatchLength, MLFSELog, (SymbolEncodingType_e)stats.MLtype,
+                countWorkspace, max, mlCodeTable, nbSeq,
+                ML_defaultNorm, ML_defaultNormLog, MaxML,
+                prevEntropy->matchlengthCTable,
+                sizeof(prevEntropy->matchlengthCTable),
+                entropyWorkspace, entropyWkspSize);
+            if (ZSTD_isError(countSize)) {
+                DEBUGLOG(3, "ZSTD_buildCTable for MatchLengths failed");
+                stats.size = countSize;
+                return stats;
+            }
+            if (stats.MLtype == set_compressed)
+                stats.lastCountSize = countSize;
+            op += countSize;
+            assert(op <= oend);
+    }   }
+    stats.size = (size_t)(op-ostart);
+    return stats;
+}
+
+/* ZSTD_entropyCompressSeqStore_internal():
+ * compresses both literals and sequences
+ * Returns compressed size of block, or a zstd error.
+ */
+#define SUSPECT_UNCOMPRESSIBLE_LITERAL_RATIO 20
+MEM_STATIC size_t
+ZSTD_entropyCompressSeqStore_internal(
+                              void* dst, size_t dstCapacity,
+                        const void* literals, size_t litSize,
+                        const SeqStore_t* seqStorePtr,
+                        const ZSTD_entropyCTables_t* prevEntropy,
+                              ZSTD_entropyCTables_t* nextEntropy,
+                        const ZSTD_CCtx_params* cctxParams,
+                              void* entropyWorkspace, size_t entropyWkspSize,
+                        const int bmi2)
+{
+    ZSTD_strategy const strategy = cctxParams->cParams.strategy;
+    unsigned* count = (unsigned*)entropyWorkspace;
+    FSE_CTable* CTable_LitLength = nextEntropy->fse.litlengthCTable;
+    FSE_CTable* CTable_OffsetBits = nextEntropy->fse.offcodeCTable;
+    FSE_CTable* CTable_MatchLength = nextEntropy->fse.matchlengthCTable;
+    const SeqDef* const sequences = seqStorePtr->sequencesStart;
+    const size_t nbSeq = (size_t)(seqStorePtr->sequences - seqStorePtr->sequencesStart);
+    const BYTE* const ofCodeTable = seqStorePtr->ofCode;
+    const BYTE* const llCodeTable = seqStorePtr->llCode;
+    const BYTE* const mlCodeTable = seqStorePtr->mlCode;
+    BYTE* const ostart = (BYTE*)dst;
+    BYTE* const oend = ostart + dstCapacity;
+    BYTE* op = ostart;
+    size_t lastCountSize;
+    int longOffsets = 0;
+
+    entropyWorkspace = count + (MaxSeq + 1);
+    entropyWkspSize -= (MaxSeq + 1) * sizeof(*count);
+
+    DEBUGLOG(5, "ZSTD_entropyCompressSeqStore_internal (nbSeq=%zu, dstCapacity=%zu)", nbSeq, dstCapacity);
+    ZSTD_STATIC_ASSERT(HUF_WORKSPACE_SIZE >= (1<<MAX(MLFSELog,LLFSELog)));
+    assert(entropyWkspSize >= HUF_WORKSPACE_SIZE);
+
+    /* Compress literals */
+    {   size_t const numSequences = (size_t)(seqStorePtr->sequences - seqStorePtr->sequencesStart);
+        /* Base suspicion of uncompressibility on ratio of literals to sequences */
+        int const suspectUncompressible = (numSequences == 0) || (litSize / numSequences >= SUSPECT_UNCOMPRESSIBLE_LITERAL_RATIO);
+
+        size_t const cSize = ZSTD_compressLiterals(
+                                    op, dstCapacity,
+                                    literals, litSize,
+                                    entropyWorkspace, entropyWkspSize,
+                                    &prevEntropy->huf, &nextEntropy->huf,
+                                    cctxParams->cParams.strategy,
+                                    ZSTD_literalsCompressionIsDisabled(cctxParams),
+                                    suspectUncompressible, bmi2);
+        FORWARD_IF_ERROR(cSize, "ZSTD_compressLiterals failed");
+        assert(cSize <= dstCapacity);
+        op += cSize;
+    }
+
+    /* Sequences Header */
+    RETURN_ERROR_IF((oend-op) < 3 /*max nbSeq Size*/ + 1 /*seqHead*/,
+                    dstSize_tooSmall, "Can't fit seq hdr in output buf!");
+    if (nbSeq < 128) {
+        *op++ = (BYTE)nbSeq;
+    } else if (nbSeq < LONGNBSEQ) {
+        op[0] = (BYTE)((nbSeq>>8) + 0x80);
+        op[1] = (BYTE)nbSeq;
+        op+=2;
+    } else {
+        op[0]=0xFF;
+        MEM_writeLE16(op+1, (U16)(nbSeq - LONGNBSEQ));
+        op+=3;
+    }
+    assert(op <= oend);
+    if (nbSeq==0) {
+        /* Copy the old tables over as if we repeated them */
+        ZSTD_memcpy(&nextEntropy->fse, &prevEntropy->fse, sizeof(prevEntropy->fse));
+        return (size_t)(op - ostart);
+    }
+    {   BYTE* const seqHead = op++;
+        /* build stats for sequences */
+        const ZSTD_symbolEncodingTypeStats_t stats =
+                ZSTD_buildSequencesStatistics(seqStorePtr, nbSeq,
+                                             &prevEntropy->fse, &nextEntropy->fse,
+                                              op, oend,
+                                              strategy, count,
+                                              entropyWorkspace, entropyWkspSize);
+        FORWARD_IF_ERROR(stats.size, "ZSTD_buildSequencesStatistics failed!");
+        *seqHead = (BYTE)((stats.LLtype<<6) + (stats.Offtype<<4) + (stats.MLtype<<2));
+        lastCountSize = stats.lastCountSize;
+        op += stats.size;
+        longOffsets = stats.longOffsets;
+    }
+
+    {   size_t const bitstreamSize = ZSTD_encodeSequences(
+                                        op, (size_t)(oend - op),
+                                        CTable_MatchLength, mlCodeTable,
+                                        CTable_OffsetBits, ofCodeTable,
+                                        CTable_LitLength, llCodeTable,
+                                        sequences, nbSeq,
+                                        longOffsets, bmi2);
+        FORWARD_IF_ERROR(bitstreamSize, "ZSTD_encodeSequences failed");
+        op += bitstreamSize;
+        assert(op <= oend);
+        /* zstd versions <= 1.3.4 mistakenly report corruption when
+         * FSE_readNCount() receives a buffer < 4 bytes.
+         * Fixed by https://github.com/facebook/zstd/pull/1146.
+         * This can happen when the last set_compressed table present is 2
+         * bytes and the bitstream is only one byte.
+         * In this exceedingly rare case, we will simply emit an uncompressed
+         * block, since it isn't worth optimizing.
+         */
+        if (lastCountSize && (lastCountSize + bitstreamSize) < 4) {
+            /* lastCountSize >= 2 && bitstreamSize > 0 ==> lastCountSize == 3 */
+            assert(lastCountSize + bitstreamSize == 3);
+            DEBUGLOG(5, "Avoiding bug in zstd decoder in versions <= 1.3.4 by "
+                        "emitting an uncompressed block.");
+            return 0;
+        }
+    }
+
+    DEBUGLOG(5, "compressed block size : %u", (unsigned)(op - ostart));
+    return (size_t)(op - ostart);
+}
+
+static size_t
+ZSTD_entropyCompressSeqStore_wExtLitBuffer(
+                          void* dst, size_t dstCapacity,
+                    const void* literals, size_t litSize,
+                          size_t blockSize,
+                    const SeqStore_t* seqStorePtr,
+                    const ZSTD_entropyCTables_t* prevEntropy,
+                          ZSTD_entropyCTables_t* nextEntropy,
+                    const ZSTD_CCtx_params* cctxParams,
+                          void* entropyWorkspace, size_t entropyWkspSize,
+                          int bmi2)
+{
+    size_t const cSize = ZSTD_entropyCompressSeqStore_internal(
+                            dst, dstCapacity,
+                            literals, litSize,
+                            seqStorePtr, prevEntropy, nextEntropy, cctxParams,
+                            entropyWorkspace, entropyWkspSize, bmi2);
+    if (cSize == 0) return 0;
+    /* When srcSize <= dstCapacity, there is enough space to write a raw uncompressed block.
+     * Since we ran out of space, block must be not compressible, so fall back to raw uncompressed block.
+     */
+    if ((cSize == ERROR(dstSize_tooSmall)) & (blockSize <= dstCapacity)) {
+        DEBUGLOG(4, "not enough dstCapacity (%zu) for ZSTD_entropyCompressSeqStore_internal()=> do not compress block", dstCapacity);
+        return 0;  /* block not compressed */
+    }
+    FORWARD_IF_ERROR(cSize, "ZSTD_entropyCompressSeqStore_internal failed");
+
+    /* Check compressibility */
+    {   size_t const maxCSize = blockSize - ZSTD_minGain(blockSize, cctxParams->cParams.strategy);
+        if (cSize >= maxCSize) return 0;  /* block not compressed */
+    }
+    DEBUGLOG(5, "ZSTD_entropyCompressSeqStore() cSize: %zu", cSize);
+    /* libzstd decoder before  > v1.5.4 is not compatible with compressed blocks of size ZSTD_BLOCKSIZE_MAX exactly.
+     * This restriction is indirectly already fulfilled by respecting ZSTD_minGain() condition above.
+     */
+    assert(cSize < ZSTD_BLOCKSIZE_MAX);
+    return cSize;
+}
+
+static size_t
+ZSTD_entropyCompressSeqStore(
+                    const SeqStore_t* seqStorePtr,
+                    const ZSTD_entropyCTables_t* prevEntropy,
+                          ZSTD_entropyCTables_t* nextEntropy,
+                    const ZSTD_CCtx_params* cctxParams,
+                          void* dst, size_t dstCapacity,
+                          size_t srcSize,
+                          void* entropyWorkspace, size_t entropyWkspSize,
+                          int bmi2)
+{
+    return ZSTD_entropyCompressSeqStore_wExtLitBuffer(
+                dst, dstCapacity,
+                seqStorePtr->litStart, (size_t)(seqStorePtr->lit - seqStorePtr->litStart),
+                srcSize,
+                seqStorePtr,
+                prevEntropy, nextEntropy,
+                cctxParams,
+                entropyWorkspace, entropyWkspSize,
+                bmi2);
+}
+
+/* ZSTD_selectBlockCompressor() :
+ * Not static, but internal use only (used by long distance matcher)
+ * assumption : strat is a valid strategy */
+ZSTD_BlockCompressor_f ZSTD_selectBlockCompressor(ZSTD_strategy strat, ZSTD_ParamSwitch_e useRowMatchFinder, ZSTD_dictMode_e dictMode)
+{
+    static const ZSTD_BlockCompressor_f blockCompressor[4][ZSTD_STRATEGY_MAX+1] = {
+        { ZSTD_compressBlock_fast  /* default for 0 */,
+          ZSTD_compressBlock_fast,
+          ZSTD_COMPRESSBLOCK_DOUBLEFAST,
+          ZSTD_COMPRESSBLOCK_GREEDY,
+          ZSTD_COMPRESSBLOCK_LAZY,
+          ZSTD_COMPRESSBLOCK_LAZY2,
+          ZSTD_COMPRESSBLOCK_BTLAZY2,
+          ZSTD_COMPRESSBLOCK_BTOPT,
+          ZSTD_COMPRESSBLOCK_BTULTRA,
+          ZSTD_COMPRESSBLOCK_BTULTRA2
+        },
+        { ZSTD_compressBlock_fast_extDict  /* default for 0 */,
+          ZSTD_compressBlock_fast_extDict,
+          ZSTD_COMPRESSBLOCK_DOUBLEFAST_EXTDICT,
+          ZSTD_COMPRESSBLOCK_GREEDY_EXTDICT,
+          ZSTD_COMPRESSBLOCK_LAZY_EXTDICT,
+          ZSTD_COMPRESSBLOCK_LAZY2_EXTDICT,
+          ZSTD_COMPRESSBLOCK_BTLAZY2_EXTDICT,
+          ZSTD_COMPRESSBLOCK_BTOPT_EXTDICT,
+          ZSTD_COMPRESSBLOCK_BTULTRA_EXTDICT,
+          ZSTD_COMPRESSBLOCK_BTULTRA_EXTDICT
+        },
+        { ZSTD_compressBlock_fast_dictMatchState  /* default for 0 */,
+          ZSTD_compressBlock_fast_dictMatchState,
+          ZSTD_COMPRESSBLOCK_DOUBLEFAST_DICTMATCHSTATE,
+          ZSTD_COMPRESSBLOCK_GREEDY_DICTMATCHSTATE,
+          ZSTD_COMPRESSBLOCK_LAZY_DICTMATCHSTATE,
+          ZSTD_COMPRESSBLOCK_LAZY2_DICTMATCHSTATE,
+          ZSTD_COMPRESSBLOCK_BTLAZY2_DICTMATCHSTATE,
+          ZSTD_COMPRESSBLOCK_BTOPT_DICTMATCHSTATE,
+          ZSTD_COMPRESSBLOCK_BTULTRA_DICTMATCHSTATE,
+          ZSTD_COMPRESSBLOCK_BTULTRA_DICTMATCHSTATE
+        },
+        { NULL  /* default for 0 */,
+          NULL,
+          NULL,
+          ZSTD_COMPRESSBLOCK_GREEDY_DEDICATEDDICTSEARCH,
+          ZSTD_COMPRESSBLOCK_LAZY_DEDICATEDDICTSEARCH,
+          ZSTD_COMPRESSBLOCK_LAZY2_DEDICATEDDICTSEARCH,
+          NULL,
+          NULL,
+          NULL,
+          NULL }
+    };
+    ZSTD_BlockCompressor_f selectedCompressor;
+    ZSTD_STATIC_ASSERT((unsigned)ZSTD_fast == 1);
+
+    assert(ZSTD_cParam_withinBounds(ZSTD_c_strategy, (int)strat));
+    DEBUGLOG(5, "Selected block compressor: dictMode=%d strat=%d rowMatchfinder=%d", (int)dictMode, (int)strat, (int)useRowMatchFinder);
+    if (ZSTD_rowMatchFinderUsed(strat, useRowMatchFinder)) {
+        static const ZSTD_BlockCompressor_f rowBasedBlockCompressors[4][3] = {
+            {
+                ZSTD_COMPRESSBLOCK_GREEDY_ROW,
+                ZSTD_COMPRESSBLOCK_LAZY_ROW,
+                ZSTD_COMPRESSBLOCK_LAZY2_ROW
+            },
+            {
+                ZSTD_COMPRESSBLOCK_GREEDY_EXTDICT_ROW,
+                ZSTD_COMPRESSBLOCK_LAZY_EXTDICT_ROW,
+                ZSTD_COMPRESSBLOCK_LAZY2_EXTDICT_ROW
+            },
+            {
+                ZSTD_COMPRESSBLOCK_GREEDY_DICTMATCHSTATE_ROW,
+                ZSTD_COMPRESSBLOCK_LAZY_DICTMATCHSTATE_ROW,
+                ZSTD_COMPRESSBLOCK_LAZY2_DICTMATCHSTATE_ROW
+            },
+            {
+                ZSTD_COMPRESSBLOCK_GREEDY_DEDICATEDDICTSEARCH_ROW,
+                ZSTD_COMPRESSBLOCK_LAZY_DEDICATEDDICTSEARCH_ROW,
+                ZSTD_COMPRESSBLOCK_LAZY2_DEDICATEDDICTSEARCH_ROW
+            }
+        };
+        DEBUGLOG(5, "Selecting a row-based matchfinder");
+        assert(useRowMatchFinder != ZSTD_ps_auto);
+        selectedCompressor = rowBasedBlockCompressors[(int)dictMode][(int)strat - (int)ZSTD_greedy];
+    } else {
+        selectedCompressor = blockCompressor[(int)dictMode][(int)strat];
+    }
+    assert(selectedCompressor != NULL);
+    return selectedCompressor;
+}
+
+static void ZSTD_storeLastLiterals(SeqStore_t* seqStorePtr,
+                                   const BYTE* anchor, size_t lastLLSize)
+{
+    ZSTD_memcpy(seqStorePtr->lit, anchor, lastLLSize);
+    seqStorePtr->lit += lastLLSize;
+}
+
+void ZSTD_resetSeqStore(SeqStore_t* ssPtr)
+{
+    ssPtr->lit = ssPtr->litStart;
+    ssPtr->sequences = ssPtr->sequencesStart;
+    ssPtr->longLengthType = ZSTD_llt_none;
+}
+
+/* ZSTD_postProcessSequenceProducerResult() :
+ * Validates and post-processes sequences obtained through the external matchfinder API:
+ *   - Checks whether nbExternalSeqs represents an error condition.
+ *   - Appends a block delimiter to outSeqs if one is not already present.
+ *     See zstd.h for context regarding block delimiters.
+ * Returns the number of sequences after post-processing, or an error code. */
+static size_t ZSTD_postProcessSequenceProducerResult(
+    ZSTD_Sequence* outSeqs, size_t nbExternalSeqs, size_t outSeqsCapacity, size_t srcSize
+) {
+    RETURN_ERROR_IF(
+        nbExternalSeqs > outSeqsCapacity,
+        sequenceProducer_failed,
+        "External sequence producer returned error code %lu",
+        (unsigned long)nbExternalSeqs
+    );
+
+    RETURN_ERROR_IF(
+        nbExternalSeqs == 0 && srcSize > 0,
+        sequenceProducer_failed,
+        "Got zero sequences from external sequence producer for a non-empty src buffer!"
+    );
+
+    if (srcSize == 0) {
+        ZSTD_memset(&outSeqs[0], 0, sizeof(ZSTD_Sequence));
+        return 1;
+    }
+
+    {
+        ZSTD_Sequence const lastSeq = outSeqs[nbExternalSeqs - 1];
+
+        /* We can return early if lastSeq is already a block delimiter. */
+        if (lastSeq.offset == 0 && lastSeq.matchLength == 0) {
+            return nbExternalSeqs;
+        }
+
+        /* This error condition is only possible if the external matchfinder
+         * produced an invalid parse, by definition of ZSTD_sequenceBound(). */
+        RETURN_ERROR_IF(
+            nbExternalSeqs == outSeqsCapacity,
+            sequenceProducer_failed,
+            "nbExternalSeqs == outSeqsCapacity but lastSeq is not a block delimiter!"
+        );
+
+        /* lastSeq is not a block delimiter, so we need to append one. */
+        ZSTD_memset(&outSeqs[nbExternalSeqs], 0, sizeof(ZSTD_Sequence));
+        return nbExternalSeqs + 1;
+    }
+}
+
+/* ZSTD_fastSequenceLengthSum() :
+ * Returns sum(litLen) + sum(matchLen) + lastLits for *seqBuf*.
+ * Similar to another function in zstd_compress.c (determine_blockSize),
+ * except it doesn't check for a block delimiter to end summation.
+ * Removing the early exit allows the compiler to auto-vectorize (https://godbolt.org/z/cY1cajz9P).
+ * This function can be deleted and replaced by determine_blockSize after we resolve issue #3456. */
+static size_t ZSTD_fastSequenceLengthSum(ZSTD_Sequence const* seqBuf, size_t seqBufSize) {
+    size_t matchLenSum, litLenSum, i;
+    matchLenSum = 0;
+    litLenSum = 0;
+    for (i = 0; i < seqBufSize; i++) {
+        litLenSum += seqBuf[i].litLength;
+        matchLenSum += seqBuf[i].matchLength;
+    }
+    return litLenSum + matchLenSum;
+}
+
+/**
+ * Function to validate sequences produced by a block compressor.
+ */
+static void ZSTD_validateSeqStore(const SeqStore_t* seqStore, const ZSTD_compressionParameters* cParams)
+{
+#if DEBUGLEVEL >= 1
+    const SeqDef* seq = seqStore->sequencesStart;
+    const SeqDef* const seqEnd = seqStore->sequences;
+    size_t const matchLenLowerBound = cParams->minMatch == 3 ? 3 : 4;
+    for (; seq < seqEnd; ++seq) {
+        const ZSTD_SequenceLength seqLength = ZSTD_getSequenceLength(seqStore, seq);
+        assert(seqLength.matchLength >= matchLenLowerBound);
+        (void)seqLength;
+        (void)matchLenLowerBound;
+    }
+#else
+    (void)seqStore;
+    (void)cParams;
+#endif
+}
+
+static size_t
+ZSTD_transferSequences_wBlockDelim(ZSTD_CCtx* cctx,
+                                   ZSTD_SequencePosition* seqPos,
+                             const ZSTD_Sequence* const inSeqs, size_t inSeqsSize,
+                             const void* src, size_t blockSize,
+                                   ZSTD_ParamSwitch_e externalRepSearch);
+
+typedef enum { ZSTDbss_compress, ZSTDbss_noCompress } ZSTD_BuildSeqStore_e;
+
+static size_t ZSTD_buildSeqStore(ZSTD_CCtx* zc, const void* src, size_t srcSize)
+{
+    ZSTD_MatchState_t* const ms = &zc->blockState.matchState;
+    DEBUGLOG(5, "ZSTD_buildSeqStore (srcSize=%zu)", srcSize);
+    assert(srcSize <= ZSTD_BLOCKSIZE_MAX);
+    /* Assert that we have correctly flushed the ctx params into the ms's copy */
+    ZSTD_assertEqualCParams(zc->appliedParams.cParams, ms->cParams);
+    /* TODO: See 3090. We reduced MIN_CBLOCK_SIZE from 3 to 2 so to compensate we are adding
+     * additional 1. We need to revisit and change this logic to be more consistent */
+    if (srcSize < MIN_CBLOCK_SIZE+ZSTD_blockHeaderSize+1+1) {
+        if (zc->appliedParams.cParams.strategy >= ZSTD_btopt) {
+            ZSTD_ldm_skipRawSeqStoreBytes(&zc->externSeqStore, srcSize);
+        } else {
+            ZSTD_ldm_skipSequences(&zc->externSeqStore, srcSize, zc->appliedParams.cParams.minMatch);
+        }
+        return ZSTDbss_noCompress; /* don't even attempt compression below a certain srcSize */
+    }
+    ZSTD_resetSeqStore(&(zc->seqStore));
+    /* required for optimal parser to read stats from dictionary */
+    ms->opt.symbolCosts = &zc->blockState.prevCBlock->entropy;
+    /* tell the optimal parser how we expect to compress literals */
+    ms->opt.literalCompressionMode = zc->appliedParams.literalCompressionMode;
+    /* a gap between an attached dict and the current window is not safe,
+     * they must remain adjacent,
+     * and when that stops being the case, the dict must be unset */
+    assert(ms->dictMatchState == NULL || ms->loadedDictEnd == ms->window.dictLimit);
+
+    /* limited update after a very long match */
+    {   const BYTE* const base = ms->window.base;
+        const BYTE* const istart = (const BYTE*)src;
+        const U32 curr = (U32)(istart-base);
+        if (sizeof(ptrdiff_t)==8) assert(istart - base < (ptrdiff_t)(U32)(-1));   /* ensure no overflow */
+        if (curr > ms->nextToUpdate + 384)
+            ms->nextToUpdate = curr - MIN(192, (U32)(curr - ms->nextToUpdate - 384));
+    }
+
+    /* select and store sequences */
+    {   ZSTD_dictMode_e const dictMode = ZSTD_matchState_dictMode(ms);
+        size_t lastLLSize;
+        {   int i;
+            for (i = 0; i < ZSTD_REP_NUM; ++i)
+                zc->blockState.nextCBlock->rep[i] = zc->blockState.prevCBlock->rep[i];
+        }
+        if (zc->externSeqStore.pos < zc->externSeqStore.size) {
+            assert(zc->appliedParams.ldmParams.enableLdm == ZSTD_ps_disable);
+
+            /* External matchfinder + LDM is technically possible, just not implemented yet.
+             * We need to revisit soon and implement it. */
+            RETURN_ERROR_IF(
+                ZSTD_hasExtSeqProd(&zc->appliedParams),
+                parameter_combination_unsupported,
+                "Long-distance matching with external sequence producer enabled is not currently supported."
+            );
+
+            /* Updates ldmSeqStore.pos */
+            lastLLSize =
+                ZSTD_ldm_blockCompress(&zc->externSeqStore,
+                                       ms, &zc->seqStore,
+                                       zc->blockState.nextCBlock->rep,
+                                       zc->appliedParams.useRowMatchFinder,
+                                       src, srcSize);
+            assert(zc->externSeqStore.pos <= zc->externSeqStore.size);
+        } else if (zc->appliedParams.ldmParams.enableLdm == ZSTD_ps_enable) {
+            RawSeqStore_t ldmSeqStore = kNullRawSeqStore;
+
+            /* External matchfinder + LDM is technically possible, just not implemented yet.
+             * We need to revisit soon and implement it. */
+            RETURN_ERROR_IF(
+                ZSTD_hasExtSeqProd(&zc->appliedParams),
+                parameter_combination_unsupported,
+                "Long-distance matching with external sequence producer enabled is not currently supported."
+            );
+
+            ldmSeqStore.seq = zc->ldmSequences;
+            ldmSeqStore.capacity = zc->maxNbLdmSequences;
+            /* Updates ldmSeqStore.size */
+            FORWARD_IF_ERROR(ZSTD_ldm_generateSequences(&zc->ldmState, &ldmSeqStore,
+                                               &zc->appliedParams.ldmParams,
+                                               src, srcSize), "");
+            /* Updates ldmSeqStore.pos */
+            lastLLSize =
+                ZSTD_ldm_blockCompress(&ldmSeqStore,
+                                       ms, &zc->seqStore,
+                                       zc->blockState.nextCBlock->rep,
+                                       zc->appliedParams.useRowMatchFinder,
+                                       src, srcSize);
+            assert(ldmSeqStore.pos == ldmSeqStore.size);
+        } else if (ZSTD_hasExtSeqProd(&zc->appliedParams)) {
+            assert(
+                zc->extSeqBufCapacity >= ZSTD_sequenceBound(srcSize)
+            );
+            assert(zc->appliedParams.extSeqProdFunc != NULL);
+
+            {   U32 const windowSize = (U32)1 << zc->appliedParams.cParams.windowLog;
+
+                size_t const nbExternalSeqs = (zc->appliedParams.extSeqProdFunc)(
+                    zc->appliedParams.extSeqProdState,
+                    zc->extSeqBuf,
+                    zc->extSeqBufCapacity,
+                    src, srcSize,
+                    NULL, 0,  /* dict and dictSize, currently not supported */
+                    zc->appliedParams.compressionLevel,
+                    windowSize
+                );
+
+                size_t const nbPostProcessedSeqs = ZSTD_postProcessSequenceProducerResult(
+                    zc->extSeqBuf,
+                    nbExternalSeqs,
+                    zc->extSeqBufCapacity,
+                    srcSize
+                );
+
+                /* Return early if there is no error, since we don't need to worry about last literals */
+                if (!ZSTD_isError(nbPostProcessedSeqs)) {
+                    ZSTD_SequencePosition seqPos = {0,0,0};
+                    size_t const seqLenSum = ZSTD_fastSequenceLengthSum(zc->extSeqBuf, nbPostProcessedSeqs);
+                    RETURN_ERROR_IF(seqLenSum > srcSize, externalSequences_invalid, "External sequences imply too large a block!");
+                    FORWARD_IF_ERROR(
+                        ZSTD_transferSequences_wBlockDelim(
+                            zc, &seqPos,
+                            zc->extSeqBuf, nbPostProcessedSeqs,
+                            src, srcSize,
+                            zc->appliedParams.searchForExternalRepcodes
+                        ),
+                        "Failed to copy external sequences to seqStore!"
+                    );
+                    ms->ldmSeqStore = NULL;
+                    DEBUGLOG(5, "Copied %lu sequences from external sequence producer to internal seqStore.", (unsigned long)nbExternalSeqs);
+                    return ZSTDbss_compress;
+                }
+
+                /* Propagate the error if fallback is disabled */
+                if (!zc->appliedParams.enableMatchFinderFallback) {
+                    return nbPostProcessedSeqs;
+                }
+
+                /* Fallback to software matchfinder */
+                {   ZSTD_BlockCompressor_f const blockCompressor =
+                        ZSTD_selectBlockCompressor(
+                            zc->appliedParams.cParams.strategy,
+                            zc->appliedParams.useRowMatchFinder,
+                            dictMode);
+                    ms->ldmSeqStore = NULL;
+                    DEBUGLOG(
+                        5,
+                        "External sequence producer returned error code %lu. Falling back to internal parser.",
+                        (unsigned long)nbExternalSeqs
+                    );
+                    lastLLSize = blockCompressor(ms, &zc->seqStore, zc->blockState.nextCBlock->rep, src, srcSize);
+            }   }
+        } else {   /* not long range mode and no external matchfinder */
+            ZSTD_BlockCompressor_f const blockCompressor = ZSTD_selectBlockCompressor(
+                    zc->appliedParams.cParams.strategy,
+                    zc->appliedParams.useRowMatchFinder,
+                    dictMode);
+            ms->ldmSeqStore = NULL;
+            lastLLSize = blockCompressor(ms, &zc->seqStore, zc->blockState.nextCBlock->rep, src, srcSize);
+        }
+        {   const BYTE* const lastLiterals = (const BYTE*)src + srcSize - lastLLSize;
+            ZSTD_storeLastLiterals(&zc->seqStore, lastLiterals, lastLLSize);
+    }   }
+    ZSTD_validateSeqStore(&zc->seqStore, &zc->appliedParams.cParams);
+    return ZSTDbss_compress;
+}
+
+static size_t ZSTD_copyBlockSequences(SeqCollector* seqCollector, const SeqStore_t* seqStore, const U32 prevRepcodes[ZSTD_REP_NUM])
+{
+    const SeqDef* inSeqs = seqStore->sequencesStart;
+    const size_t nbInSequences = (size_t)(seqStore->sequences - inSeqs);
+    const size_t nbInLiterals = (size_t)(seqStore->lit - seqStore->litStart);
+
+    ZSTD_Sequence* outSeqs = seqCollector->seqIndex == 0 ? seqCollector->seqStart : seqCollector->seqStart + seqCollector->seqIndex;
+    const size_t nbOutSequences = nbInSequences + 1;
+    size_t nbOutLiterals = 0;
+    Repcodes_t repcodes;
+    size_t i;
+
+    /* Bounds check that we have enough space for every input sequence
+     * and the block delimiter
+     */
+    assert(seqCollector->seqIndex <= seqCollector->maxSequences);
+    RETURN_ERROR_IF(
+        nbOutSequences > (size_t)(seqCollector->maxSequences - seqCollector->seqIndex),
+        dstSize_tooSmall,
+        "Not enough space to copy sequences");
+
+    ZSTD_memcpy(&repcodes, prevRepcodes, sizeof(repcodes));
+    for (i = 0; i < nbInSequences; ++i) {
+        U32 rawOffset;
+        outSeqs[i].litLength = inSeqs[i].litLength;
+        outSeqs[i].matchLength = inSeqs[i].mlBase + MINMATCH;
+        outSeqs[i].rep = 0;
+
+        /* Handle the possible single length >= 64K
+         * There can only be one because we add MINMATCH to every match length,
+         * and blocks are at most 128K.
+         */
+        if (i == seqStore->longLengthPos) {
+            if (seqStore->longLengthType == ZSTD_llt_literalLength) {
+                outSeqs[i].litLength += 0x10000;
+            } else if (seqStore->longLengthType == ZSTD_llt_matchLength) {
+                outSeqs[i].matchLength += 0x10000;
+            }
+        }
+
+        /* Determine the raw offset given the offBase, which may be a repcode. */
+        if (OFFBASE_IS_REPCODE(inSeqs[i].offBase)) {
+            const U32 repcode = OFFBASE_TO_REPCODE(inSeqs[i].offBase);
+            assert(repcode > 0);
+            outSeqs[i].rep = repcode;
+            if (outSeqs[i].litLength != 0) {
+                rawOffset = repcodes.rep[repcode - 1];
+            } else {
+                if (repcode == 3) {
+                    assert(repcodes.rep[0] > 1);
+                    rawOffset = repcodes.rep[0] - 1;
+                } else {
+                    rawOffset = repcodes.rep[repcode];
+                }
+            }
+        } else {
+            rawOffset = OFFBASE_TO_OFFSET(inSeqs[i].offBase);
+        }
+        outSeqs[i].offset = rawOffset;
+
+        /* Update repcode history for the sequence */
+        ZSTD_updateRep(repcodes.rep,
+                       inSeqs[i].offBase,
+                       inSeqs[i].litLength == 0);
+
+        nbOutLiterals += outSeqs[i].litLength;
+    }
+    /* Insert last literals (if any exist) in the block as a sequence with ml == off == 0.
+     * If there are no last literals, then we'll emit (of: 0, ml: 0, ll: 0), which is a marker
+     * for the block boundary, according to the API.
+     */
+    assert(nbInLiterals >= nbOutLiterals);
+    {
+        const size_t lastLLSize = nbInLiterals - nbOutLiterals;
+        outSeqs[nbInSequences].litLength = (U32)lastLLSize;
+        outSeqs[nbInSequences].matchLength = 0;
+        outSeqs[nbInSequences].offset = 0;
+        assert(nbOutSequences == nbInSequences + 1);
+    }
+    seqCollector->seqIndex += nbOutSequences;
+    assert(seqCollector->seqIndex <= seqCollector->maxSequences);
+
+    return 0;
+}
+
+size_t ZSTD_sequenceBound(size_t srcSize) {
+    const size_t maxNbSeq = (srcSize / ZSTD_MINMATCH_MIN) + 1;
+    const size_t maxNbDelims = (srcSize / ZSTD_BLOCKSIZE_MAX_MIN) + 1;
+    return maxNbSeq + maxNbDelims;
+}
+
+size_t ZSTD_mergeBlockDelimiters(ZSTD_Sequence* sequences, size_t seqsSize) {
+    size_t in = 0;
+    size_t out = 0;
+    for (; in < seqsSize; ++in) {
+        if (sequences[in].offset == 0 && sequences[in].matchLength == 0) {
+            if (in != seqsSize - 1) {
+                sequences[in+1].litLength += sequences[in].litLength;
+            }
+        } else {
+            sequences[out] = sequences[in];
+            ++out;
+        }
+    }
+    return out;
+}
+
+/* Unrolled loop to read four size_ts of input at a time. Returns 1 if is RLE, 0 if not. */
+static int ZSTD_isRLE(const BYTE* src, size_t length) {
+    const BYTE* ip = src;
+    const BYTE value = ip[0];
+    const size_t valueST = (size_t)((U64)value * 0x0101010101010101ULL);
+    const size_t unrollSize = sizeof(size_t) * 4;
+    const size_t unrollMask = unrollSize - 1;
+    const size_t prefixLength = length & unrollMask;
+    size_t i;
+    if (length == 1) return 1;
+    /* Check if prefix is RLE first before using unrolled loop */
+    if (prefixLength && ZSTD_count(ip+1, ip, ip+prefixLength) != prefixLength-1) {
+        return 0;
+    }
+    for (i = prefixLength; i != length; i += unrollSize) {
+        size_t u;
+        for (u = 0; u < unrollSize; u += sizeof(size_t)) {
+            if (MEM_readST(ip + i + u) != valueST) {
+                return 0;
+    }   }   }
+    return 1;
+}
+
+/* Returns true if the given block may be RLE.
+ * This is just a heuristic based on the compressibility.
+ * It may return both false positives and false negatives.
+ */
+static int ZSTD_maybeRLE(SeqStore_t const* seqStore)
+{
+    size_t const nbSeqs = (size_t)(seqStore->sequences - seqStore->sequencesStart);
+    size_t const nbLits = (size_t)(seqStore->lit - seqStore->litStart);
+
+    return nbSeqs < 4 && nbLits < 10;
+}
+
+static void
+ZSTD_blockState_confirmRepcodesAndEntropyTables(ZSTD_blockState_t* const bs)
+{
+    ZSTD_compressedBlockState_t* const tmp = bs->prevCBlock;
+    bs->prevCBlock = bs->nextCBlock;
+    bs->nextCBlock = tmp;
+}
+
+/* Writes the block header */
+static void
+writeBlockHeader(void* op, size_t cSize, size_t blockSize, U32 lastBlock)
+{
+    U32 const cBlockHeader = cSize == 1 ?
+                        lastBlock + (((U32)bt_rle)<<1) + (U32)(blockSize << 3) :
+                        lastBlock + (((U32)bt_compressed)<<1) + (U32)(cSize << 3);
+    MEM_writeLE24(op, cBlockHeader);
+    DEBUGLOG(5, "writeBlockHeader: cSize: %zu blockSize: %zu lastBlock: %u", cSize, blockSize, lastBlock);
+}
+
+/** ZSTD_buildBlockEntropyStats_literals() :
+ *  Builds entropy for the literals.
+ *  Stores literals block type (raw, rle, compressed, repeat) and
+ *  huffman description table to hufMetadata.
+ *  Requires ENTROPY_WORKSPACE_SIZE workspace
+ * @return : size of huffman description table, or an error code
+ */
+static size_t
+ZSTD_buildBlockEntropyStats_literals(void* const src, size_t srcSize,
+                               const ZSTD_hufCTables_t* prevHuf,
+                                     ZSTD_hufCTables_t* nextHuf,
+                                     ZSTD_hufCTablesMetadata_t* hufMetadata,
+                               const int literalsCompressionIsDisabled,
+                                     void* workspace, size_t wkspSize,
+                                     int hufFlags)
+{
+    BYTE* const wkspStart = (BYTE*)workspace;
+    BYTE* const wkspEnd = wkspStart + wkspSize;
+    BYTE* const countWkspStart = wkspStart;
+    unsigned* const countWksp = (unsigned*)workspace;
+    const size_t countWkspSize = (HUF_SYMBOLVALUE_MAX + 1) * sizeof(unsigned);
+    BYTE* const nodeWksp = countWkspStart + countWkspSize;
+    const size_t nodeWkspSize = (size_t)(wkspEnd - nodeWksp);
+    unsigned maxSymbolValue = HUF_SYMBOLVALUE_MAX;
+    unsigned huffLog = LitHufLog;
+    HUF_repeat repeat = prevHuf->repeatMode;
+    DEBUGLOG(5, "ZSTD_buildBlockEntropyStats_literals (srcSize=%zu)", srcSize);
+
+    /* Prepare nextEntropy assuming reusing the existing table */
+    ZSTD_memcpy(nextHuf, prevHuf, sizeof(*prevHuf));
+
+    if (literalsCompressionIsDisabled) {
+        DEBUGLOG(5, "set_basic - disabled");
+        hufMetadata->hType = set_basic;
+        return 0;
+    }
+
+    /* small ? don't even attempt compression (speed opt) */
+#ifndef COMPRESS_LITERALS_SIZE_MIN
+# define COMPRESS_LITERALS_SIZE_MIN 63  /* heuristic */
+#endif
+    {   size_t const minLitSize = (prevHuf->repeatMode == HUF_repeat_valid) ? 6 : COMPRESS_LITERALS_SIZE_MIN;
+        if (srcSize <= minLitSize) {
+            DEBUGLOG(5, "set_basic - too small");
+            hufMetadata->hType = set_basic;
+            return 0;
+    }   }
+
+    /* Scan input and build symbol stats */
+    {   size_t const largest =
+            HIST_count_wksp (countWksp, &maxSymbolValue,
+                            (const BYTE*)src, srcSize,
+                            workspace, wkspSize);
+        FORWARD_IF_ERROR(largest, "HIST_count_wksp failed");
+        if (largest == srcSize) {
+            /* only one literal symbol */
+            DEBUGLOG(5, "set_rle");
+            hufMetadata->hType = set_rle;
+            return 0;
+        }
+        if (largest <= (srcSize >> 7)+4) {
+            /* heuristic: likely not compressible */
+            DEBUGLOG(5, "set_basic - no gain");
+            hufMetadata->hType = set_basic;
+            return 0;
+    }   }
+
+    /* Validate the previous Huffman table */
+    if (repeat == HUF_repeat_check
+      && !HUF_validateCTable((HUF_CElt const*)prevHuf->CTable, countWksp, maxSymbolValue)) {
+        repeat = HUF_repeat_none;
+    }
+
+    /* Build Huffman Tree */
+    ZSTD_memset(nextHuf->CTable, 0, sizeof(nextHuf->CTable));
+    huffLog = HUF_optimalTableLog(huffLog, srcSize, maxSymbolValue, nodeWksp, nodeWkspSize, nextHuf->CTable, countWksp, hufFlags);
+    assert(huffLog <= LitHufLog);
+    {   size_t const maxBits = HUF_buildCTable_wksp((HUF_CElt*)nextHuf->CTable, countWksp,
+                                                    maxSymbolValue, huffLog,
+                                                    nodeWksp, nodeWkspSize);
+        FORWARD_IF_ERROR(maxBits, "HUF_buildCTable_wksp");
+        huffLog = (U32)maxBits;
+    }
+    {   /* Build and write the CTable */
+        size_t const newCSize = HUF_estimateCompressedSize(
+                (HUF_CElt*)nextHuf->CTable, countWksp, maxSymbolValue);
+        size_t const hSize = HUF_writeCTable_wksp(
+                hufMetadata->hufDesBuffer, sizeof(hufMetadata->hufDesBuffer),
+                (HUF_CElt*)nextHuf->CTable, maxSymbolValue, huffLog,
+                nodeWksp, nodeWkspSize);
+        /* Check against repeating the previous CTable */
+        if (repeat != HUF_repeat_none) {
+            size_t const oldCSize = HUF_estimateCompressedSize(
+                    (HUF_CElt const*)prevHuf->CTable, countWksp, maxSymbolValue);
+            if (oldCSize < srcSize && (oldCSize <= hSize + newCSize || hSize + 12 >= srcSize)) {
+                DEBUGLOG(5, "set_repeat - smaller");
+                ZSTD_memcpy(nextHuf, prevHuf, sizeof(*prevHuf));
+                hufMetadata->hType = set_repeat;
+                return 0;
+        }   }
+        if (newCSize + hSize >= srcSize) {
+            DEBUGLOG(5, "set_basic - no gains");
+            ZSTD_memcpy(nextHuf, prevHuf, sizeof(*prevHuf));
+            hufMetadata->hType = set_basic;
+            return 0;
+        }
+        DEBUGLOG(5, "set_compressed (hSize=%u)", (U32)hSize);
+        hufMetadata->hType = set_compressed;
+        nextHuf->repeatMode = HUF_repeat_check;
+        return hSize;
+    }
+}
+
+
+/* ZSTD_buildDummySequencesStatistics():
+ * Returns a ZSTD_symbolEncodingTypeStats_t with all encoding types as set_basic,
+ * and updates nextEntropy to the appropriate repeatMode.
+ */
+static ZSTD_symbolEncodingTypeStats_t
+ZSTD_buildDummySequencesStatistics(ZSTD_fseCTables_t* nextEntropy)
+{
+    ZSTD_symbolEncodingTypeStats_t stats = {set_basic, set_basic, set_basic, 0, 0, 0};
+    nextEntropy->litlength_repeatMode = FSE_repeat_none;
+    nextEntropy->offcode_repeatMode = FSE_repeat_none;
+    nextEntropy->matchlength_repeatMode = FSE_repeat_none;
+    return stats;
+}
+
+/** ZSTD_buildBlockEntropyStats_sequences() :
+ *  Builds entropy for the sequences.
+ *  Stores symbol compression modes and fse table to fseMetadata.
+ *  Requires ENTROPY_WORKSPACE_SIZE wksp.
+ * @return : size of fse tables or error code */
+static size_t
+ZSTD_buildBlockEntropyStats_sequences(
+                const SeqStore_t* seqStorePtr,
+                const ZSTD_fseCTables_t* prevEntropy,
+                      ZSTD_fseCTables_t* nextEntropy,
+                const ZSTD_CCtx_params* cctxParams,
+                      ZSTD_fseCTablesMetadata_t* fseMetadata,
+                      void* workspace, size_t wkspSize)
+{
+    ZSTD_strategy const strategy = cctxParams->cParams.strategy;
+    size_t const nbSeq = (size_t)(seqStorePtr->sequences - seqStorePtr->sequencesStart);
+    BYTE* const ostart = fseMetadata->fseTablesBuffer;
+    BYTE* const oend = ostart + sizeof(fseMetadata->fseTablesBuffer);
+    BYTE* op = ostart;
+    unsigned* countWorkspace = (unsigned*)workspace;
+    unsigned* entropyWorkspace = countWorkspace + (MaxSeq + 1);
+    size_t entropyWorkspaceSize = wkspSize - (MaxSeq + 1) * sizeof(*countWorkspace);
+    ZSTD_symbolEncodingTypeStats_t stats;
+
+    DEBUGLOG(5, "ZSTD_buildBlockEntropyStats_sequences (nbSeq=%zu)", nbSeq);
+    stats = nbSeq != 0 ? ZSTD_buildSequencesStatistics(seqStorePtr, nbSeq,
+                                          prevEntropy, nextEntropy, op, oend,
+                                          strategy, countWorkspace,
+                                          entropyWorkspace, entropyWorkspaceSize)
+                       : ZSTD_buildDummySequencesStatistics(nextEntropy);
+    FORWARD_IF_ERROR(stats.size, "ZSTD_buildSequencesStatistics failed!");
+    fseMetadata->llType = (SymbolEncodingType_e) stats.LLtype;
+    fseMetadata->ofType = (SymbolEncodingType_e) stats.Offtype;
+    fseMetadata->mlType = (SymbolEncodingType_e) stats.MLtype;
+    fseMetadata->lastCountSize = stats.lastCountSize;
+    return stats.size;
+}
+
+
+/** ZSTD_buildBlockEntropyStats() :
+ *  Builds entropy for the block.
+ *  Requires workspace size ENTROPY_WORKSPACE_SIZE
+ * @return : 0 on success, or an error code
+ *  Note : also employed in superblock
+ */
+size_t ZSTD_buildBlockEntropyStats(
+            const SeqStore_t* seqStorePtr,
+            const ZSTD_entropyCTables_t* prevEntropy,
+                  ZSTD_entropyCTables_t* nextEntropy,
+            const ZSTD_CCtx_params* cctxParams,
+                  ZSTD_entropyCTablesMetadata_t* entropyMetadata,
+                  void* workspace, size_t wkspSize)
+{
+    size_t const litSize = (size_t)(seqStorePtr->lit - seqStorePtr->litStart);
+    int const huf_useOptDepth = (cctxParams->cParams.strategy >= HUF_OPTIMAL_DEPTH_THRESHOLD);
+    int const hufFlags = huf_useOptDepth ? HUF_flags_optimalDepth : 0;
+
+    entropyMetadata->hufMetadata.hufDesSize =
+        ZSTD_buildBlockEntropyStats_literals(seqStorePtr->litStart, litSize,
+                                            &prevEntropy->huf, &nextEntropy->huf,
+                                            &entropyMetadata->hufMetadata,
+                                            ZSTD_literalsCompressionIsDisabled(cctxParams),
+                                            workspace, wkspSize, hufFlags);
+
+    FORWARD_IF_ERROR(entropyMetadata->hufMetadata.hufDesSize, "ZSTD_buildBlockEntropyStats_literals failed");
+    entropyMetadata->fseMetadata.fseTablesSize =
+        ZSTD_buildBlockEntropyStats_sequences(seqStorePtr,
+                                              &prevEntropy->fse, &nextEntropy->fse,
+                                              cctxParams,
+                                              &entropyMetadata->fseMetadata,
+                                              workspace, wkspSize);
+    FORWARD_IF_ERROR(entropyMetadata->fseMetadata.fseTablesSize, "ZSTD_buildBlockEntropyStats_sequences failed");
+    return 0;
+}
+
+/* Returns the size estimate for the literals section (header + content) of a block */
+static size_t
+ZSTD_estimateBlockSize_literal(const BYTE* literals, size_t litSize,
+                               const ZSTD_hufCTables_t* huf,
+                               const ZSTD_hufCTablesMetadata_t* hufMetadata,
+                               void* workspace, size_t wkspSize,
+                               int writeEntropy)
+{
+    unsigned* const countWksp = (unsigned*)workspace;
+    unsigned maxSymbolValue = HUF_SYMBOLVALUE_MAX;
+    size_t literalSectionHeaderSize = 3 + (litSize >= 1 KB) + (litSize >= 16 KB);
+    U32 singleStream = litSize < 256;
+
+    if (hufMetadata->hType == set_basic) return litSize;
+    else if (hufMetadata->hType == set_rle) return 1;
+    else if (hufMetadata->hType == set_compressed || hufMetadata->hType == set_repeat) {
+        size_t const largest = HIST_count_wksp (countWksp, &maxSymbolValue, (const BYTE*)literals, litSize, workspace, wkspSize);
+        if (ZSTD_isError(largest)) return litSize;
+        {   size_t cLitSizeEstimate = HUF_estimateCompressedSize((const HUF_CElt*)huf->CTable, countWksp, maxSymbolValue);
+            if (writeEntropy) cLitSizeEstimate += hufMetadata->hufDesSize;
+            if (!singleStream) cLitSizeEstimate += 6; /* multi-stream huffman uses 6-byte jump table */
+            return cLitSizeEstimate + literalSectionHeaderSize;
+    }   }
+    assert(0); /* impossible */
+    return 0;
+}
+
+/* Returns the size estimate for the FSE-compressed symbols (of, ml, ll) of a block */
+static size_t
+ZSTD_estimateBlockSize_symbolType(SymbolEncodingType_e type,
+                    const BYTE* codeTable, size_t nbSeq, unsigned maxCode,
+                    const FSE_CTable* fseCTable,
+                    const U8* additionalBits,
+                    short const* defaultNorm, U32 defaultNormLog, U32 defaultMax,
+                    void* workspace, size_t wkspSize)
+{
+    unsigned* const countWksp = (unsigned*)workspace;
+    const BYTE* ctp = codeTable;
+    const BYTE* const ctStart = ctp;
+    const BYTE* const ctEnd = ctStart + nbSeq;
+    size_t cSymbolTypeSizeEstimateInBits = 0;
+    unsigned max = maxCode;
+
+    HIST_countFast_wksp(countWksp, &max, codeTable, nbSeq, workspace, wkspSize);  /* can't fail */
+    if (type == set_basic) {
+        /* We selected this encoding type, so it must be valid. */
+        assert(max <= defaultMax);
+        (void)defaultMax;
+        cSymbolTypeSizeEstimateInBits = ZSTD_crossEntropyCost(defaultNorm, defaultNormLog, countWksp, max);
+    } else if (type == set_rle) {
+        cSymbolTypeSizeEstimateInBits = 0;
+    } else if (type == set_compressed || type == set_repeat) {
+        cSymbolTypeSizeEstimateInBits = ZSTD_fseBitCost(fseCTable, countWksp, max);
+    }
+    if (ZSTD_isError(cSymbolTypeSizeEstimateInBits)) {
+        return nbSeq * 10;
+    }
+    while (ctp < ctEnd) {
+        if (additionalBits) cSymbolTypeSizeEstimateInBits += additionalBits[*ctp];
+        else cSymbolTypeSizeEstimateInBits += *ctp; /* for offset, offset code is also the number of additional bits */
+        ctp++;
+    }
+    return cSymbolTypeSizeEstimateInBits >> 3;
+}
+
+/* Returns the size estimate for the sequences section (header + content) of a block */
+static size_t
+ZSTD_estimateBlockSize_sequences(const BYTE* ofCodeTable,
+                                 const BYTE* llCodeTable,
+                                 const BYTE* mlCodeTable,
+                                 size_t nbSeq,
+                                 const ZSTD_fseCTables_t* fseTables,
+                                 const ZSTD_fseCTablesMetadata_t* fseMetadata,
+                                 void* workspace, size_t wkspSize,
+                                 int writeEntropy)
+{
+    size_t sequencesSectionHeaderSize = 1 /* seqHead */ + 1 /* min seqSize size */ + (nbSeq >= 128) + (nbSeq >= LONGNBSEQ);
+    size_t cSeqSizeEstimate = 0;
+    cSeqSizeEstimate += ZSTD_estimateBlockSize_symbolType(fseMetadata->ofType, ofCodeTable, nbSeq, MaxOff,
+                                    fseTables->offcodeCTable, NULL,
+                                    OF_defaultNorm, OF_defaultNormLog, DefaultMaxOff,
+                                    workspace, wkspSize);
+    cSeqSizeEstimate += ZSTD_estimateBlockSize_symbolType(fseMetadata->llType, llCodeTable, nbSeq, MaxLL,
+                                    fseTables->litlengthCTable, LL_bits,
+                                    LL_defaultNorm, LL_defaultNormLog, MaxLL,
+                                    workspace, wkspSize);
+    cSeqSizeEstimate += ZSTD_estimateBlockSize_symbolType(fseMetadata->mlType, mlCodeTable, nbSeq, MaxML,
+                                    fseTables->matchlengthCTable, ML_bits,
+                                    ML_defaultNorm, ML_defaultNormLog, MaxML,
+                                    workspace, wkspSize);
+    if (writeEntropy) cSeqSizeEstimate += fseMetadata->fseTablesSize;
+    return cSeqSizeEstimate + sequencesSectionHeaderSize;
+}
+
+/* Returns the size estimate for a given stream of literals, of, ll, ml */
+static size_t
+ZSTD_estimateBlockSize(const BYTE* literals, size_t litSize,
+                       const BYTE* ofCodeTable,
+                       const BYTE* llCodeTable,
+                       const BYTE* mlCodeTable,
+                       size_t nbSeq,
+                       const ZSTD_entropyCTables_t* entropy,
+                       const ZSTD_entropyCTablesMetadata_t* entropyMetadata,
+                       void* workspace, size_t wkspSize,
+                       int writeLitEntropy, int writeSeqEntropy)
+{
+    size_t const literalsSize = ZSTD_estimateBlockSize_literal(literals, litSize,
+                                    &entropy->huf, &entropyMetadata->hufMetadata,
+                                    workspace, wkspSize, writeLitEntropy);
+    size_t const seqSize = ZSTD_estimateBlockSize_sequences(ofCodeTable, llCodeTable, mlCodeTable,
+                                    nbSeq, &entropy->fse, &entropyMetadata->fseMetadata,
+                                    workspace, wkspSize, writeSeqEntropy);
+    return seqSize + literalsSize + ZSTD_blockHeaderSize;
+}
+
+/* Builds entropy statistics and uses them for blocksize estimation.
+ *
+ * @return: estimated compressed size of the seqStore, or a zstd error.
+ */
+static size_t
+ZSTD_buildEntropyStatisticsAndEstimateSubBlockSize(SeqStore_t* seqStore, ZSTD_CCtx* zc)
+{
+    ZSTD_entropyCTablesMetadata_t* const entropyMetadata = &zc->blockSplitCtx.entropyMetadata;
+    DEBUGLOG(6, "ZSTD_buildEntropyStatisticsAndEstimateSubBlockSize()");
+    FORWARD_IF_ERROR(ZSTD_buildBlockEntropyStats(seqStore,
+                    &zc->blockState.prevCBlock->entropy,
+                    &zc->blockState.nextCBlock->entropy,
+                    &zc->appliedParams,
+                    entropyMetadata,
+                    zc->tmpWorkspace, zc->tmpWkspSize), "");
+    return ZSTD_estimateBlockSize(
+                    seqStore->litStart, (size_t)(seqStore->lit - seqStore->litStart),
+                    seqStore->ofCode, seqStore->llCode, seqStore->mlCode,
+                    (size_t)(seqStore->sequences - seqStore->sequencesStart),
+                    &zc->blockState.nextCBlock->entropy,
+                    entropyMetadata,
+                    zc->tmpWorkspace, zc->tmpWkspSize,
+                    (int)(entropyMetadata->hufMetadata.hType == set_compressed), 1);
+}
+
+/* Returns literals bytes represented in a seqStore */
+static size_t ZSTD_countSeqStoreLiteralsBytes(const SeqStore_t* const seqStore)
+{
+    size_t literalsBytes = 0;
+    size_t const nbSeqs = (size_t)(seqStore->sequences - seqStore->sequencesStart);
+    size_t i;
+    for (i = 0; i < nbSeqs; ++i) {
+        SeqDef const seq = seqStore->sequencesStart[i];
+        literalsBytes += seq.litLength;
+        if (i == seqStore->longLengthPos && seqStore->longLengthType == ZSTD_llt_literalLength) {
+            literalsBytes += 0x10000;
+    }   }
+    return literalsBytes;
+}
+
+/* Returns match bytes represented in a seqStore */
+static size_t ZSTD_countSeqStoreMatchBytes(const SeqStore_t* const seqStore)
+{
+    size_t matchBytes = 0;
+    size_t const nbSeqs = (size_t)(seqStore->sequences - seqStore->sequencesStart);
+    size_t i;
+    for (i = 0; i < nbSeqs; ++i) {
+        SeqDef seq = seqStore->sequencesStart[i];
+        matchBytes += seq.mlBase + MINMATCH;
+        if (i == seqStore->longLengthPos && seqStore->longLengthType == ZSTD_llt_matchLength) {
+            matchBytes += 0x10000;
+    }   }
+    return matchBytes;
+}
+
+/* Derives the seqStore that is a chunk of the originalSeqStore from [startIdx, endIdx).
+ * Stores the result in resultSeqStore.
+ */
+static void ZSTD_deriveSeqStoreChunk(SeqStore_t* resultSeqStore,
+                               const SeqStore_t* originalSeqStore,
+                                     size_t startIdx, size_t endIdx)
+{
+    *resultSeqStore = *originalSeqStore;
+    if (startIdx > 0) {
+        resultSeqStore->sequences = originalSeqStore->sequencesStart + startIdx;
+        resultSeqStore->litStart += ZSTD_countSeqStoreLiteralsBytes(resultSeqStore);
+    }
+
+    /* Move longLengthPos into the correct position if necessary */
+    if (originalSeqStore->longLengthType != ZSTD_llt_none) {
+        if (originalSeqStore->longLengthPos < startIdx || originalSeqStore->longLengthPos > endIdx) {
+            resultSeqStore->longLengthType = ZSTD_llt_none;
+        } else {
+            resultSeqStore->longLengthPos -= (U32)startIdx;
+        }
+    }
+    resultSeqStore->sequencesStart = originalSeqStore->sequencesStart + startIdx;
+    resultSeqStore->sequences = originalSeqStore->sequencesStart + endIdx;
+    if (endIdx == (size_t)(originalSeqStore->sequences - originalSeqStore->sequencesStart)) {
+        /* This accounts for possible last literals if the derived chunk reaches the end of the block */
+        assert(resultSeqStore->lit == originalSeqStore->lit);
+    } else {
+        size_t const literalsBytes = ZSTD_countSeqStoreLiteralsBytes(resultSeqStore);
+        resultSeqStore->lit = resultSeqStore->litStart + literalsBytes;
+    }
+    resultSeqStore->llCode += startIdx;
+    resultSeqStore->mlCode += startIdx;
+    resultSeqStore->ofCode += startIdx;
+}
+
+/**
+ * Returns the raw offset represented by the combination of offBase, ll0, and repcode history.
+ * offBase must represent a repcode in the numeric representation of ZSTD_storeSeq().
+ */
+static U32
+ZSTD_resolveRepcodeToRawOffset(const U32 rep[ZSTD_REP_NUM], const U32 offBase, const U32 ll0)
+{
+    U32 const adjustedRepCode = OFFBASE_TO_REPCODE(offBase) - 1 + ll0;  /* [ 0 - 3 ] */
+    assert(OFFBASE_IS_REPCODE(offBase));
+    if (adjustedRepCode == ZSTD_REP_NUM) {
+        assert(ll0);
+        /* litlength == 0 and offCode == 2 implies selection of first repcode - 1
+         * This is only valid if it results in a valid offset value, aka > 0.
+         * Note : it may happen that `rep[0]==1` in exceptional circumstances.
+         * In which case this function will return 0, which is an invalid offset.
+         * It's not an issue though, since this value will be
+         * compared and discarded within ZSTD_seqStore_resolveOffCodes().
+         */
+        return rep[0] - 1;
+    }
+    return rep[adjustedRepCode];
+}
+
+/**
+ * ZSTD_seqStore_resolveOffCodes() reconciles any possible divergences in offset history that may arise
+ * due to emission of RLE/raw blocks that disturb the offset history,
+ * and replaces any repcodes within the seqStore that may be invalid.
+ *
+ * dRepcodes are updated as would be on the decompression side.
+ * cRepcodes are updated exactly in accordance with the seqStore.
+ *
+ * Note : this function assumes seq->offBase respects the following numbering scheme :
+ *        0 : invalid
+ *        1-3 : repcode 1-3
+ *        4+ : real_offset+3
+ */
+static void
+ZSTD_seqStore_resolveOffCodes(Repcodes_t* const dRepcodes, Repcodes_t* const cRepcodes,
+                        const SeqStore_t* const seqStore, U32 const nbSeq)
+{
+    U32 idx = 0;
+    U32 const longLitLenIdx = seqStore->longLengthType == ZSTD_llt_literalLength ? seqStore->longLengthPos : nbSeq;
+    for (; idx < nbSeq; ++idx) {
+        SeqDef* const seq = seqStore->sequencesStart + idx;
+        U32 const ll0 = (seq->litLength == 0) && (idx != longLitLenIdx);
+        U32 const offBase = seq->offBase;
+        assert(offBase > 0);
+        if (OFFBASE_IS_REPCODE(offBase)) {
+            U32 const dRawOffset = ZSTD_resolveRepcodeToRawOffset(dRepcodes->rep, offBase, ll0);
+            U32 const cRawOffset = ZSTD_resolveRepcodeToRawOffset(cRepcodes->rep, offBase, ll0);
+            /* Adjust simulated decompression repcode history if we come across a mismatch. Replace
+             * the repcode with the offset it actually references, determined by the compression
+             * repcode history.
+             */
+            if (dRawOffset != cRawOffset) {
+                seq->offBase = OFFSET_TO_OFFBASE(cRawOffset);
+            }
+        }
+        /* Compression repcode history is always updated with values directly from the unmodified seqStore.
+         * Decompression repcode history may use modified seq->offset value taken from compression repcode history.
+         */
+        ZSTD_updateRep(dRepcodes->rep, seq->offBase, ll0);
+        ZSTD_updateRep(cRepcodes->rep, offBase, ll0);
+    }
+}
+
+/* ZSTD_compressSeqStore_singleBlock():
+ * Compresses a seqStore into a block with a block header, into the buffer dst.
+ *
+ * Returns the total size of that block (including header) or a ZSTD error code.
+ */
+static size_t
+ZSTD_compressSeqStore_singleBlock(ZSTD_CCtx* zc,
+                            const SeqStore_t* const seqStore,
+                                  Repcodes_t* const dRep, Repcodes_t* const cRep,
+                                  void* dst, size_t dstCapacity,
+                            const void* src, size_t srcSize,
+                                  U32 lastBlock, U32 isPartition)
+{
+    const U32 rleMaxLength = 25;
+    BYTE* op = (BYTE*)dst;
+    const BYTE* ip = (const BYTE*)src;
+    size_t cSize;
+    size_t cSeqsSize;
+
+    /* In case of an RLE or raw block, the simulated decompression repcode history must be reset */
+    Repcodes_t const dRepOriginal = *dRep;
+    DEBUGLOG(5, "ZSTD_compressSeqStore_singleBlock");
+    if (isPartition)
+        ZSTD_seqStore_resolveOffCodes(dRep, cRep, seqStore, (U32)(seqStore->sequences - seqStore->sequencesStart));
+
+    RETURN_ERROR_IF(dstCapacity < ZSTD_blockHeaderSize, dstSize_tooSmall, "Block header doesn't fit");
+    cSeqsSize = ZSTD_entropyCompressSeqStore(seqStore,
+                &zc->blockState.prevCBlock->entropy, &zc->blockState.nextCBlock->entropy,
+                &zc->appliedParams,
+                op + ZSTD_blockHeaderSize, dstCapacity - ZSTD_blockHeaderSize,
+                srcSize,
+                zc->tmpWorkspace, zc->tmpWkspSize /* statically allocated in resetCCtx */,
+                zc->bmi2);
+    FORWARD_IF_ERROR(cSeqsSize, "ZSTD_entropyCompressSeqStore failed!");
+
+    if (!zc->isFirstBlock &&
+        cSeqsSize < rleMaxLength &&
+        ZSTD_isRLE((BYTE const*)src, srcSize)) {
+        /* We don't want to emit our first block as a RLE even if it qualifies because
+        * doing so will cause the decoder (cli only) to throw a "should consume all input error."
+        * This is only an issue for zstd <= v1.4.3
+        */
+        cSeqsSize = 1;
+    }
+
+    /* Sequence collection not supported when block splitting */
+    if (zc->seqCollector.collectSequences) {
+        FORWARD_IF_ERROR(ZSTD_copyBlockSequences(&zc->seqCollector, seqStore, dRepOriginal.rep), "copyBlockSequences failed");
+        ZSTD_blockState_confirmRepcodesAndEntropyTables(&zc->blockState);
+        return 0;
+    }
+
+    if (cSeqsSize == 0) {
+        cSize = ZSTD_noCompressBlock(op, dstCapacity, ip, srcSize, lastBlock);
+        FORWARD_IF_ERROR(cSize, "Nocompress block failed");
+        DEBUGLOG(5, "Writing out nocompress block, size: %zu", cSize);
+        *dRep = dRepOriginal; /* reset simulated decompression repcode history */
+    } else if (cSeqsSize == 1) {
+        cSize = ZSTD_rleCompressBlock(op, dstCapacity, *ip, srcSize, lastBlock);
+        FORWARD_IF_ERROR(cSize, "RLE compress block failed");
+        DEBUGLOG(5, "Writing out RLE block, size: %zu", cSize);
+        *dRep = dRepOriginal; /* reset simulated decompression repcode history */
+    } else {
+        ZSTD_blockState_confirmRepcodesAndEntropyTables(&zc->blockState);
+        writeBlockHeader(op, cSeqsSize, srcSize, lastBlock);
+        cSize = ZSTD_blockHeaderSize + cSeqsSize;
+        DEBUGLOG(5, "Writing out compressed block, size: %zu", cSize);
+    }
+
+    if (zc->blockState.prevCBlock->entropy.fse.offcode_repeatMode == FSE_repeat_valid)
+        zc->blockState.prevCBlock->entropy.fse.offcode_repeatMode = FSE_repeat_check;
+
+    return cSize;
+}
+
+/* Struct to keep track of where we are in our recursive calls. */
+typedef struct {
+    U32* splitLocations;    /* Array of split indices */
+    size_t idx;             /* The current index within splitLocations being worked on */
+} seqStoreSplits;
+
+#define MIN_SEQUENCES_BLOCK_SPLITTING 300
+
+/* Helper function to perform the recursive search for block splits.
+ * Estimates the cost of seqStore prior to split, and estimates the cost of splitting the sequences in half.
+ * If advantageous to split, then we recurse down the two sub-blocks.
+ * If not, or if an error occurred in estimation, then we do not recurse.
+ *
+ * Note: The recursion depth is capped by a heuristic minimum number of sequences,
+ * defined by MIN_SEQUENCES_BLOCK_SPLITTING.
+ * In theory, this means the absolute largest recursion depth is 10 == log2(maxNbSeqInBlock/MIN_SEQUENCES_BLOCK_SPLITTING).
+ * In practice, recursion depth usually doesn't go beyond 4.
+ *
+ * Furthermore, the number of splits is capped by ZSTD_MAX_NB_BLOCK_SPLITS.
+ * At ZSTD_MAX_NB_BLOCK_SPLITS == 196 with the current existing blockSize
+ * maximum of 128 KB, this value is actually impossible to reach.
+ */
+static void
+ZSTD_deriveBlockSplitsHelper(seqStoreSplits* splits, size_t startIdx, size_t endIdx,
+                             ZSTD_CCtx* zc, const SeqStore_t* origSeqStore)
+{
+    SeqStore_t* const fullSeqStoreChunk = &zc->blockSplitCtx.fullSeqStoreChunk;
+    SeqStore_t* const firstHalfSeqStore = &zc->blockSplitCtx.firstHalfSeqStore;
+    SeqStore_t* const secondHalfSeqStore = &zc->blockSplitCtx.secondHalfSeqStore;
+    size_t estimatedOriginalSize;
+    size_t estimatedFirstHalfSize;
+    size_t estimatedSecondHalfSize;
+    size_t midIdx = (startIdx + endIdx)/2;
+
+    DEBUGLOG(5, "ZSTD_deriveBlockSplitsHelper: startIdx=%zu endIdx=%zu", startIdx, endIdx);
+    assert(endIdx >= startIdx);
+    if (endIdx - startIdx < MIN_SEQUENCES_BLOCK_SPLITTING || splits->idx >= ZSTD_MAX_NB_BLOCK_SPLITS) {
+        DEBUGLOG(6, "ZSTD_deriveBlockSplitsHelper: Too few sequences (%zu)", endIdx - startIdx);
+        return;
+    }
+    ZSTD_deriveSeqStoreChunk(fullSeqStoreChunk, origSeqStore, startIdx, endIdx);
+    ZSTD_deriveSeqStoreChunk(firstHalfSeqStore, origSeqStore, startIdx, midIdx);
+    ZSTD_deriveSeqStoreChunk(secondHalfSeqStore, origSeqStore, midIdx, endIdx);
+    estimatedOriginalSize = ZSTD_buildEntropyStatisticsAndEstimateSubBlockSize(fullSeqStoreChunk, zc);
+    estimatedFirstHalfSize = ZSTD_buildEntropyStatisticsAndEstimateSubBlockSize(firstHalfSeqStore, zc);
+    estimatedSecondHalfSize = ZSTD_buildEntropyStatisticsAndEstimateSubBlockSize(secondHalfSeqStore, zc);
+    DEBUGLOG(5, "Estimated original block size: %zu -- First half split: %zu -- Second half split: %zu",
+             estimatedOriginalSize, estimatedFirstHalfSize, estimatedSecondHalfSize);
+    if (ZSTD_isError(estimatedOriginalSize) || ZSTD_isError(estimatedFirstHalfSize) || ZSTD_isError(estimatedSecondHalfSize)) {
+        return;
+    }
+    if (estimatedFirstHalfSize + estimatedSecondHalfSize < estimatedOriginalSize) {
+        DEBUGLOG(5, "split decided at seqNb:%zu", midIdx);
+        ZSTD_deriveBlockSplitsHelper(splits, startIdx, midIdx, zc, origSeqStore);
+        splits->splitLocations[splits->idx] = (U32)midIdx;
+        splits->idx++;
+        ZSTD_deriveBlockSplitsHelper(splits, midIdx, endIdx, zc, origSeqStore);
+    }
+}
+
+/* Base recursive function.
+ * Populates a table with intra-block partition indices that can improve compression ratio.
+ *
+ * @return: number of splits made (which equals the size of the partition table - 1).
+ */
+static size_t ZSTD_deriveBlockSplits(ZSTD_CCtx* zc, U32 partitions[], U32 nbSeq)
+{
+    seqStoreSplits splits;
+    splits.splitLocations = partitions;
+    splits.idx = 0;
+    if (nbSeq <= 4) {
+        DEBUGLOG(5, "ZSTD_deriveBlockSplits: Too few sequences to split (%u <= 4)", nbSeq);
+        /* Refuse to try and split anything with less than 4 sequences */
+        return 0;
+    }
+    ZSTD_deriveBlockSplitsHelper(&splits, 0, nbSeq, zc, &zc->seqStore);
+    splits.splitLocations[splits.idx] = nbSeq;
+    DEBUGLOG(5, "ZSTD_deriveBlockSplits: final nb partitions: %zu", splits.idx+1);
+    return splits.idx;
+}
+
+/* ZSTD_compressBlock_splitBlock():
+ * Attempts to split a given block into multiple blocks to improve compression ratio.
+ *
+ * Returns combined size of all blocks (which includes headers), or a ZSTD error code.
+ */
+static size_t
+ZSTD_compressBlock_splitBlock_internal(ZSTD_CCtx* zc,
+                                    void* dst, size_t dstCapacity,
+                              const void* src, size_t blockSize,
+                                    U32 lastBlock, U32 nbSeq)
+{
+    size_t cSize = 0;
+    const BYTE* ip = (const BYTE*)src;
+    BYTE* op = (BYTE*)dst;
+    size_t i = 0;
+    size_t srcBytesTotal = 0;
+    U32* const partitions = zc->blockSplitCtx.partitions; /* size == ZSTD_MAX_NB_BLOCK_SPLITS */
+    SeqStore_t* const nextSeqStore = &zc->blockSplitCtx.nextSeqStore;
+    SeqStore_t* const currSeqStore = &zc->blockSplitCtx.currSeqStore;
+    size_t const numSplits = ZSTD_deriveBlockSplits(zc, partitions, nbSeq);
+
+    /* If a block is split and some partitions are emitted as RLE/uncompressed, then repcode history
+     * may become invalid. In order to reconcile potentially invalid repcodes, we keep track of two
+     * separate repcode histories that simulate repcode history on compression and decompression side,
+     * and use the histories to determine whether we must replace a particular repcode with its raw offset.
+     *
+     * 1) cRep gets updated for each partition, regardless of whether the block was emitted as uncompressed
+     *    or RLE. This allows us to retrieve the offset value that an invalid repcode references within
+     *    a nocompress/RLE block.
+     * 2) dRep gets updated only for compressed partitions, and when a repcode gets replaced, will use
+     *    the replacement offset value rather than the original repcode to update the repcode history.
+     *    dRep also will be the final repcode history sent to the next block.
+     *
+     * See ZSTD_seqStore_resolveOffCodes() for more details.
+     */
+    Repcodes_t dRep;
+    Repcodes_t cRep;
+    ZSTD_memcpy(dRep.rep, zc->blockState.prevCBlock->rep, sizeof(Repcodes_t));
+    ZSTD_memcpy(cRep.rep, zc->blockState.prevCBlock->rep, sizeof(Repcodes_t));
+    ZSTD_memset(nextSeqStore, 0, sizeof(SeqStore_t));
+
+    DEBUGLOG(5, "ZSTD_compressBlock_splitBlock_internal (dstCapacity=%u, dictLimit=%u, nextToUpdate=%u)",
+                (unsigned)dstCapacity, (unsigned)zc->blockState.matchState.window.dictLimit,
+                (unsigned)zc->blockState.matchState.nextToUpdate);
+
+    if (numSplits == 0) {
+        size_t cSizeSingleBlock =
+            ZSTD_compressSeqStore_singleBlock(zc, &zc->seqStore,
+                                            &dRep, &cRep,
+                                            op, dstCapacity,
+                                            ip, blockSize,
+                                            lastBlock, 0 /* isPartition */);
+        FORWARD_IF_ERROR(cSizeSingleBlock, "Compressing single block from splitBlock_internal() failed!");
+        DEBUGLOG(5, "ZSTD_compressBlock_splitBlock_internal: No splits");
+        assert(zc->blockSizeMax <= ZSTD_BLOCKSIZE_MAX);
+        assert(cSizeSingleBlock <= zc->blockSizeMax + ZSTD_blockHeaderSize);
+        return cSizeSingleBlock;
+    }
+
+    ZSTD_deriveSeqStoreChunk(currSeqStore, &zc->seqStore, 0, partitions[0]);
+    for (i = 0; i <= numSplits; ++i) {
+        size_t cSizeChunk;
+        U32 const lastPartition = (i == numSplits);
+        U32 lastBlockEntireSrc = 0;
+
+        size_t srcBytes = ZSTD_countSeqStoreLiteralsBytes(currSeqStore) + ZSTD_countSeqStoreMatchBytes(currSeqStore);
+        srcBytesTotal += srcBytes;
+        if (lastPartition) {
+            /* This is the final partition, need to account for possible last literals */
+            srcBytes += blockSize - srcBytesTotal;
+            lastBlockEntireSrc = lastBlock;
+        } else {
+            ZSTD_deriveSeqStoreChunk(nextSeqStore, &zc->seqStore, partitions[i], partitions[i+1]);
+        }
+
+        cSizeChunk = ZSTD_compressSeqStore_singleBlock(zc, currSeqStore,
+                                                      &dRep, &cRep,
+                                                       op, dstCapacity,
+                                                       ip, srcBytes,
+                                                       lastBlockEntireSrc, 1 /* isPartition */);
+        DEBUGLOG(5, "Estimated size: %zu vs %zu : actual size",
+                    ZSTD_buildEntropyStatisticsAndEstimateSubBlockSize(currSeqStore, zc), cSizeChunk);
+        FORWARD_IF_ERROR(cSizeChunk, "Compressing chunk failed!");
+
+        ip += srcBytes;
+        op += cSizeChunk;
+        dstCapacity -= cSizeChunk;
+        cSize += cSizeChunk;
+        *currSeqStore = *nextSeqStore;
+        assert(cSizeChunk <= zc->blockSizeMax + ZSTD_blockHeaderSize);
+    }
+    /* cRep and dRep may have diverged during the compression.
+     * If so, we use the dRep repcodes for the next block.
+     */
+    ZSTD_memcpy(zc->blockState.prevCBlock->rep, dRep.rep, sizeof(Repcodes_t));
+    return cSize;
+}
+
+static size_t
+ZSTD_compressBlock_splitBlock(ZSTD_CCtx* zc,
+                              void* dst, size_t dstCapacity,
+                              const void* src, size_t srcSize, U32 lastBlock)
+{
+    U32 nbSeq;
+    size_t cSize;
+    DEBUGLOG(5, "ZSTD_compressBlock_splitBlock");
+    assert(zc->appliedParams.postBlockSplitter == ZSTD_ps_enable);
+
+    {   const size_t bss = ZSTD_buildSeqStore(zc, src, srcSize);
+        FORWARD_IF_ERROR(bss, "ZSTD_buildSeqStore failed");
+        if (bss == ZSTDbss_noCompress) {
+            if (zc->blockState.prevCBlock->entropy.fse.offcode_repeatMode == FSE_repeat_valid)
+                zc->blockState.prevCBlock->entropy.fse.offcode_repeatMode = FSE_repeat_check;
+            RETURN_ERROR_IF(zc->seqCollector.collectSequences, sequenceProducer_failed, "Uncompressible block");
+            cSize = ZSTD_noCompressBlock(dst, dstCapacity, src, srcSize, lastBlock);
+            FORWARD_IF_ERROR(cSize, "ZSTD_noCompressBlock failed");
+            DEBUGLOG(5, "ZSTD_compressBlock_splitBlock: Nocompress block");
+            return cSize;
+        }
+        nbSeq = (U32)(zc->seqStore.sequences - zc->seqStore.sequencesStart);
+    }
+
+    cSize = ZSTD_compressBlock_splitBlock_internal(zc, dst, dstCapacity, src, srcSize, lastBlock, nbSeq);
+    FORWARD_IF_ERROR(cSize, "Splitting blocks failed!");
+    return cSize;
+}
+
+static size_t
+ZSTD_compressBlock_internal(ZSTD_CCtx* zc,
+                            void* dst, size_t dstCapacity,
+                            const void* src, size_t srcSize, U32 frame)
+{
+    /* This is an estimated upper bound for the length of an rle block.
+     * This isn't the actual upper bound.
+     * Finding the real threshold needs further investigation.
+     */
+    const U32 rleMaxLength = 25;
+    size_t cSize;
+    const BYTE* ip = (const BYTE*)src;
+    BYTE* op = (BYTE*)dst;
+    DEBUGLOG(5, "ZSTD_compressBlock_internal (dstCapacity=%u, dictLimit=%u, nextToUpdate=%u)",
+                (unsigned)dstCapacity, (unsigned)zc->blockState.matchState.window.dictLimit,
+                (unsigned)zc->blockState.matchState.nextToUpdate);
+
+    {   const size_t bss = ZSTD_buildSeqStore(zc, src, srcSize);
+        FORWARD_IF_ERROR(bss, "ZSTD_buildSeqStore failed");
+        if (bss == ZSTDbss_noCompress) {
+            RETURN_ERROR_IF(zc->seqCollector.collectSequences, sequenceProducer_failed, "Uncompressible block");
+            cSize = 0;
+            goto out;
+        }
+    }
+
+    if (zc->seqCollector.collectSequences) {
+        FORWARD_IF_ERROR(ZSTD_copyBlockSequences(&zc->seqCollector, ZSTD_getSeqStore(zc), zc->blockState.prevCBlock->rep), "copyBlockSequences failed");
+        ZSTD_blockState_confirmRepcodesAndEntropyTables(&zc->blockState);
+        return 0;
+    }
+
+    /* encode sequences and literals */
+    cSize = ZSTD_entropyCompressSeqStore(&zc->seqStore,
+            &zc->blockState.prevCBlock->entropy, &zc->blockState.nextCBlock->entropy,
+            &zc->appliedParams,
+            dst, dstCapacity,
+            srcSize,
+            zc->tmpWorkspace, zc->tmpWkspSize /* statically allocated in resetCCtx */,
+            zc->bmi2);
+
+    if (frame &&
+        /* We don't want to emit our first block as a RLE even if it qualifies because
+         * doing so will cause the decoder (cli only) to throw a "should consume all input error."
+         * This is only an issue for zstd <= v1.4.3
+         */
+        !zc->isFirstBlock &&
+        cSize < rleMaxLength &&
+        ZSTD_isRLE(ip, srcSize))
+    {
+        cSize = 1;
+        op[0] = ip[0];
+    }
+
+out:
+    if (!ZSTD_isError(cSize) && cSize > 1) {
+        ZSTD_blockState_confirmRepcodesAndEntropyTables(&zc->blockState);
+    }
+    /* We check that dictionaries have offset codes available for the first
+     * block. After the first block, the offcode table might not have large
+     * enough codes to represent the offsets in the data.
+     */
+    if (zc->blockState.prevCBlock->entropy.fse.offcode_repeatMode == FSE_repeat_valid)
+        zc->blockState.prevCBlock->entropy.fse.offcode_repeatMode = FSE_repeat_check;
+
+    return cSize;
+}
+
+static size_t ZSTD_compressBlock_targetCBlockSize_body(ZSTD_CCtx* zc,
+                               void* dst, size_t dstCapacity,
+                               const void* src, size_t srcSize,
+                               const size_t bss, U32 lastBlock)
+{
+    DEBUGLOG(6, "Attempting ZSTD_compressSuperBlock()");
+    if (bss == ZSTDbss_compress) {
+        if (/* We don't want to emit our first block as a RLE even if it qualifies because
+            * doing so will cause the decoder (cli only) to throw a "should consume all input error."
+            * This is only an issue for zstd <= v1.4.3
+            */
+            !zc->isFirstBlock &&
+            ZSTD_maybeRLE(&zc->seqStore) &&
+            ZSTD_isRLE((BYTE const*)src, srcSize))
+        {
+            return ZSTD_rleCompressBlock(dst, dstCapacity, *(BYTE const*)src, srcSize, lastBlock);
+        }
+        /* Attempt superblock compression.
+         *
+         * Note that compressed size of ZSTD_compressSuperBlock() is not bound by the
+         * standard ZSTD_compressBound(). This is a problem, because even if we have
+         * space now, taking an extra byte now could cause us to run out of space later
+         * and violate ZSTD_compressBound().
+         *
+         * Define blockBound(blockSize) = blockSize + ZSTD_blockHeaderSize.
+         *
+         * In order to respect ZSTD_compressBound() we must attempt to emit a raw
+         * uncompressed block in these cases:
+         *   * cSize == 0: Return code for an uncompressed block.
+         *   * cSize == dstSize_tooSmall: We may have expanded beyond blockBound(srcSize).
+         *     ZSTD_noCompressBlock() will return dstSize_tooSmall if we are really out of
+         *     output space.
+         *   * cSize >= blockBound(srcSize): We have expanded the block too much so
+         *     emit an uncompressed block.
+         */
+        {   size_t const cSize =
+                ZSTD_compressSuperBlock(zc, dst, dstCapacity, src, srcSize, lastBlock);
+            if (cSize != ERROR(dstSize_tooSmall)) {
+                size_t const maxCSize =
+                    srcSize - ZSTD_minGain(srcSize, zc->appliedParams.cParams.strategy);
+                FORWARD_IF_ERROR(cSize, "ZSTD_compressSuperBlock failed");
+                if (cSize != 0 && cSize < maxCSize + ZSTD_blockHeaderSize) {
+                    ZSTD_blockState_confirmRepcodesAndEntropyTables(&zc->blockState);
+                    return cSize;
+                }
+            }
+        }
+    } /* if (bss == ZSTDbss_compress)*/
+
+    DEBUGLOG(6, "Resorting to ZSTD_noCompressBlock()");
+    /* Superblock compression failed, attempt to emit a single no compress block.
+     * The decoder will be able to stream this block since it is uncompressed.
+     */
+    return ZSTD_noCompressBlock(dst, dstCapacity, src, srcSize, lastBlock);
+}
+
+static size_t ZSTD_compressBlock_targetCBlockSize(ZSTD_CCtx* zc,
+                               void* dst, size_t dstCapacity,
+                               const void* src, size_t srcSize,
+                               U32 lastBlock)
+{
+    size_t cSize = 0;
+    const size_t bss = ZSTD_buildSeqStore(zc, src, srcSize);
+    DEBUGLOG(5, "ZSTD_compressBlock_targetCBlockSize (dstCapacity=%u, dictLimit=%u, nextToUpdate=%u, srcSize=%zu)",
+                (unsigned)dstCapacity, (unsigned)zc->blockState.matchState.window.dictLimit, (unsigned)zc->blockState.matchState.nextToUpdate, srcSize);
+    FORWARD_IF_ERROR(bss, "ZSTD_buildSeqStore failed");
+
+    cSize = ZSTD_compressBlock_targetCBlockSize_body(zc, dst, dstCapacity, src, srcSize, bss, lastBlock);
+    FORWARD_IF_ERROR(cSize, "ZSTD_compressBlock_targetCBlockSize_body failed");
+
+    if (zc->blockState.prevCBlock->entropy.fse.offcode_repeatMode == FSE_repeat_valid)
+        zc->blockState.prevCBlock->entropy.fse.offcode_repeatMode = FSE_repeat_check;
+
+    return cSize;
+}
+
+static void ZSTD_overflowCorrectIfNeeded(ZSTD_MatchState_t* ms,
+                                         ZSTD_cwksp* ws,
+                                         ZSTD_CCtx_params const* params,
+                                         void const* ip,
+                                         void const* iend)
+{
+    U32 const cycleLog = ZSTD_cycleLog(params->cParams.chainLog, params->cParams.strategy);
+    U32 const maxDist = (U32)1 << params->cParams.windowLog;
+    if (ZSTD_window_needOverflowCorrection(ms->window, cycleLog, maxDist, ms->loadedDictEnd, ip, iend)) {
+        U32 const correction = ZSTD_window_correctOverflow(&ms->window, cycleLog, maxDist, ip);
+        ZSTD_STATIC_ASSERT(ZSTD_CHAINLOG_MAX <= 30);
+        ZSTD_STATIC_ASSERT(ZSTD_WINDOWLOG_MAX_32 <= 30);
+        ZSTD_STATIC_ASSERT(ZSTD_WINDOWLOG_MAX <= 31);
+        ZSTD_cwksp_mark_tables_dirty(ws);
+        ZSTD_reduceIndex(ms, params, correction);
+        ZSTD_cwksp_mark_tables_clean(ws);
+        if (ms->nextToUpdate < correction) ms->nextToUpdate = 0;
+        else ms->nextToUpdate -= correction;
+        /* invalidate dictionaries on overflow correction */
+        ms->loadedDictEnd = 0;
+        ms->dictMatchState = NULL;
+    }
+}
+
+#include "zstd_preSplit.h"
+
+static size_t ZSTD_optimalBlockSize(ZSTD_CCtx* cctx, const void* src, size_t srcSize, size_t blockSizeMax, int splitLevel, ZSTD_strategy strat, S64 savings)
+{
+    /* split level based on compression strategy, from `fast` to `btultra2` */
+    static const int splitLevels[] = { 0, 0, 1, 2, 2, 3, 3, 4, 4, 4 };
+    /* note: conservatively only split full blocks (128 KB) currently.
+     * While it's possible to go lower, let's keep it simple for a first implementation.
+     * Besides, benefits of splitting are reduced when blocks are already small.
+     */
+    if (srcSize < 128 KB || blockSizeMax < 128 KB)
+        return MIN(srcSize, blockSizeMax);
+    /* do not split incompressible data though:
+     * require verified savings to allow pre-splitting.
+     * Note: as a consequence, the first full block is not split.
+     */
+    if (savings < 3) {
+        DEBUGLOG(6, "don't attempt splitting: savings (%i) too low", (int)savings);
+        return 128 KB;
+    }
+    /* apply @splitLevel, or use default value (which depends on @strat).
+     * note that splitting heuristic is still conditioned by @savings >= 3,
+     * so the first block will not reach this code path */
+    if (splitLevel == 1) return 128 KB;
+    if (splitLevel == 0) {
+        assert(ZSTD_fast <= strat && strat <= ZSTD_btultra2);
+        splitLevel = splitLevels[strat];
+    } else {
+        assert(2 <= splitLevel && splitLevel <= 6);
+        splitLevel -= 2;
+    }
+    return ZSTD_splitBlock(src, blockSizeMax, splitLevel, cctx->tmpWorkspace, cctx->tmpWkspSize);
+}
+
+/*! ZSTD_compress_frameChunk() :
+*   Compress a chunk of data into one or multiple blocks.
+*   All blocks will be terminated, all input will be consumed.
+*   Function will issue an error if there is not enough `dstCapacity` to hold the compressed content.
+*   Frame is supposed already started (header already produced)
+*  @return : compressed size, or an error code
+*/
+static size_t ZSTD_compress_frameChunk(ZSTD_CCtx* cctx,
+                                     void* dst, size_t dstCapacity,
+                               const void* src, size_t srcSize,
+                                     U32 lastFrameChunk)
+{
+    size_t blockSizeMax = cctx->blockSizeMax;
+    size_t remaining = srcSize;
+    const BYTE* ip = (const BYTE*)src;
+    BYTE* const ostart = (BYTE*)dst;
+    BYTE* op = ostart;
+    U32 const maxDist = (U32)1 << cctx->appliedParams.cParams.windowLog;
+    S64 savings = (S64)cctx->consumedSrcSize - (S64)cctx->producedCSize;
+
+    assert(cctx->appliedParams.cParams.windowLog <= ZSTD_WINDOWLOG_MAX);
+
+    DEBUGLOG(5, "ZSTD_compress_frameChunk (srcSize=%u, blockSizeMax=%u)", (unsigned)srcSize, (unsigned)blockSizeMax);
+    if (cctx->appliedParams.fParams.checksumFlag && srcSize)
+        XXH64_update(&cctx->xxhState, src, srcSize);
+
+    while (remaining) {
+        ZSTD_MatchState_t* const ms = &cctx->blockState.matchState;
+        size_t const blockSize = ZSTD_optimalBlockSize(cctx,
+                                ip, remaining,
+                                blockSizeMax,
+                                cctx->appliedParams.preBlockSplitter_level,
+                                cctx->appliedParams.cParams.strategy,
+                                savings);
+        U32 const lastBlock = lastFrameChunk & (blockSize == remaining);
+        assert(blockSize <= remaining);
+
+        /* TODO: See 3090. We reduced MIN_CBLOCK_SIZE from 3 to 2 so to compensate we are adding
+         * additional 1. We need to revisit and change this logic to be more consistent */
+        RETURN_ERROR_IF(dstCapacity < ZSTD_blockHeaderSize + MIN_CBLOCK_SIZE + 1,
+                        dstSize_tooSmall,
+                        "not enough space to store compressed block");
+
+        ZSTD_overflowCorrectIfNeeded(
+            ms, &cctx->workspace, &cctx->appliedParams, ip, ip + blockSize);
+        ZSTD_checkDictValidity(&ms->window, ip + blockSize, maxDist, &ms->loadedDictEnd, &ms->dictMatchState);
+        ZSTD_window_enforceMaxDist(&ms->window, ip, maxDist, &ms->loadedDictEnd, &ms->dictMatchState);
+
+        /* Ensure hash/chain table insertion resumes no sooner than lowlimit */
+        if (ms->nextToUpdate < ms->window.lowLimit) ms->nextToUpdate = ms->window.lowLimit;
+
+        {   size_t cSize;
+            if (ZSTD_useTargetCBlockSize(&cctx->appliedParams)) {
+                cSize = ZSTD_compressBlock_targetCBlockSize(cctx, op, dstCapacity, ip, blockSize, lastBlock);
+                FORWARD_IF_ERROR(cSize, "ZSTD_compressBlock_targetCBlockSize failed");
+                assert(cSize > 0);
+                assert(cSize <= blockSize + ZSTD_blockHeaderSize);
+            } else if (ZSTD_blockSplitterEnabled(&cctx->appliedParams)) {
+                cSize = ZSTD_compressBlock_splitBlock(cctx, op, dstCapacity, ip, blockSize, lastBlock);
+                FORWARD_IF_ERROR(cSize, "ZSTD_compressBlock_splitBlock failed");
+                assert(cSize > 0 || cctx->seqCollector.collectSequences == 1);
+            } else {
+                cSize = ZSTD_compressBlock_internal(cctx,
+                                        op+ZSTD_blockHeaderSize, dstCapacity-ZSTD_blockHeaderSize,
+                                        ip, blockSize, 1 /* frame */);
+                FORWARD_IF_ERROR(cSize, "ZSTD_compressBlock_internal failed");
+
+                if (cSize == 0) {  /* block is not compressible */
+                    cSize = ZSTD_noCompressBlock(op, dstCapacity, ip, blockSize, lastBlock);
+                    FORWARD_IF_ERROR(cSize, "ZSTD_noCompressBlock failed");
+                } else {
+                    U32 const cBlockHeader = cSize == 1 ?
+                        lastBlock + (((U32)bt_rle)<<1) + (U32)(blockSize << 3) :
+                        lastBlock + (((U32)bt_compressed)<<1) + (U32)(cSize << 3);
+                    MEM_writeLE24(op, cBlockHeader);
+                    cSize += ZSTD_blockHeaderSize;
+                }
+            }  /* if (ZSTD_useTargetCBlockSize(&cctx->appliedParams))*/
+
+            /* @savings is employed to ensure that splitting doesn't worsen expansion of incompressible data.
+             * Without splitting, the maximum expansion is 3 bytes per full block.
+             * An adversarial input could attempt to fudge the split detector,
+             * and make it split incompressible data, resulting in more block headers.
+             * Note that, since ZSTD_COMPRESSBOUND() assumes a worst case scenario of 1KB per block,
+             * and the splitter never creates blocks that small (current lower limit is 8 KB),
+             * there is already no risk to expand beyond ZSTD_COMPRESSBOUND() limit.
+             * But if the goal is to not expand by more than 3-bytes per 128 KB full block,
+             * then yes, it becomes possible to make the block splitter oversplit incompressible data.
+             * Using @savings, we enforce an even more conservative condition,
+             * requiring the presence of enough savings (at least 3 bytes) to authorize splitting,
+             * otherwise only full blocks are used.
+             * But being conservative is fine,
+             * since splitting barely compressible blocks is not fruitful anyway */
+            savings += (S64)blockSize - (S64)cSize;
+
+            ip += blockSize;
+            assert(remaining >= blockSize);
+            remaining -= blockSize;
+            op += cSize;
+            assert(dstCapacity >= cSize);
+            dstCapacity -= cSize;
+            cctx->isFirstBlock = 0;
+            DEBUGLOG(5, "ZSTD_compress_frameChunk: adding a block of size %u",
+                        (unsigned)cSize);
+    }   }
+
+    if (lastFrameChunk && (op>ostart)) cctx->stage = ZSTDcs_ending;
+    return (size_t)(op-ostart);
+}
+
+
+static size_t ZSTD_writeFrameHeader(void* dst, size_t dstCapacity,
+                                    const ZSTD_CCtx_params* params,
+                                    U64 pledgedSrcSize, U32 dictID)
+{
+    BYTE* const op = (BYTE*)dst;
+    U32   const dictIDSizeCodeLength = (dictID>0) + (dictID>=256) + (dictID>=65536);   /* 0-3 */
+    U32   const dictIDSizeCode = params->fParams.noDictIDFlag ? 0 : dictIDSizeCodeLength;   /* 0-3 */
+    U32   const checksumFlag = params->fParams.checksumFlag>0;
+    U32   const windowSize = (U32)1 << params->cParams.windowLog;
+    U32   const singleSegment = params->fParams.contentSizeFlag && (windowSize >= pledgedSrcSize);
+    BYTE  const windowLogByte = (BYTE)((params->cParams.windowLog - ZSTD_WINDOWLOG_ABSOLUTEMIN) << 3);
+    U32   const fcsCode = params->fParams.contentSizeFlag ?
+                     (pledgedSrcSize>=256) + (pledgedSrcSize>=65536+256) + (pledgedSrcSize>=0xFFFFFFFFU) : 0;  /* 0-3 */
+    BYTE  const frameHeaderDescriptionByte = (BYTE)(dictIDSizeCode + (checksumFlag<<2) + (singleSegment<<5) + (fcsCode<<6) );
+    size_t pos=0;
+
+    assert(!(params->fParams.contentSizeFlag && pledgedSrcSize == ZSTD_CONTENTSIZE_UNKNOWN));
+    RETURN_ERROR_IF(dstCapacity < ZSTD_FRAMEHEADERSIZE_MAX, dstSize_tooSmall,
+                    "dst buf is too small to fit worst-case frame header size.");
+    DEBUGLOG(4, "ZSTD_writeFrameHeader : dictIDFlag : %u ; dictID : %u ; dictIDSizeCode : %u",
+                !params->fParams.noDictIDFlag, (unsigned)dictID, (unsigned)dictIDSizeCode);
+    if (params->format == ZSTD_f_zstd1) {
+        MEM_writeLE32(dst, ZSTD_MAGICNUMBER);
+        pos = 4;
+    }
+    op[pos++] = frameHeaderDescriptionByte;
+    if (!singleSegment) op[pos++] = windowLogByte;
+    switch(dictIDSizeCode)
+    {
+        default:
+            assert(0); /* impossible */
+            ZSTD_FALLTHROUGH;
+        case 0 : break;
+        case 1 : op[pos] = (BYTE)(dictID); pos++; break;
+        case 2 : MEM_writeLE16(op+pos, (U16)dictID); pos+=2; break;
+        case 3 : MEM_writeLE32(op+pos, dictID); pos+=4; break;
+    }
+    switch(fcsCode)
+    {
+        default:
+            assert(0); /* impossible */
+            ZSTD_FALLTHROUGH;
+        case 0 : if (singleSegment) op[pos++] = (BYTE)(pledgedSrcSize); break;
+        case 1 : MEM_writeLE16(op+pos, (U16)(pledgedSrcSize-256)); pos+=2; break;
+        case 2 : MEM_writeLE32(op+pos, (U32)(pledgedSrcSize)); pos+=4; break;
+        case 3 : MEM_writeLE64(op+pos, (U64)(pledgedSrcSize)); pos+=8; break;
+    }
+    return pos;
+}
+
+/* ZSTD_writeSkippableFrame_advanced() :
+ * Writes out a skippable frame with the specified magic number variant (16 are supported),
+ * from ZSTD_MAGIC_SKIPPABLE_START to ZSTD_MAGIC_SKIPPABLE_START+15, and the desired source data.
+ *
+ * Returns the total number of bytes written, or a ZSTD error code.
+ */
+size_t ZSTD_writeSkippableFrame(void* dst, size_t dstCapacity,
+                                const void* src, size_t srcSize, unsigned magicVariant) {
+    BYTE* op = (BYTE*)dst;
+    RETURN_ERROR_IF(dstCapacity < srcSize + ZSTD_SKIPPABLEHEADERSIZE /* Skippable frame overhead */,
+                    dstSize_tooSmall, "Not enough room for skippable frame");
+    RETURN_ERROR_IF(srcSize > (unsigned)0xFFFFFFFF, srcSize_wrong, "Src size too large for skippable frame");
+    RETURN_ERROR_IF(magicVariant > 15, parameter_outOfBound, "Skippable frame magic number variant not supported");
+
+    MEM_writeLE32(op, (U32)(ZSTD_MAGIC_SKIPPABLE_START + magicVariant));
+    MEM_writeLE32(op+4, (U32)srcSize);
+    ZSTD_memcpy(op+8, src, srcSize);
+    return srcSize + ZSTD_SKIPPABLEHEADERSIZE;
+}
+
+/* ZSTD_writeLastEmptyBlock() :
+ * output an empty Block with end-of-frame mark to complete a frame
+ * @return : size of data written into `dst` (== ZSTD_blockHeaderSize (defined in zstd_internal.h))
+ *           or an error code if `dstCapacity` is too small (<ZSTD_blockHeaderSize)
+ */
+size_t ZSTD_writeLastEmptyBlock(void* dst, size_t dstCapacity)
+{
+    RETURN_ERROR_IF(dstCapacity < ZSTD_blockHeaderSize, dstSize_tooSmall,
+                    "dst buf is too small to write frame trailer empty block.");
+    {   U32 const cBlockHeader24 = 1 /*lastBlock*/ + (((U32)bt_raw)<<1);  /* 0 size */
+        MEM_writeLE24(dst, cBlockHeader24);
+        return ZSTD_blockHeaderSize;
+    }
+}
+
+void ZSTD_referenceExternalSequences(ZSTD_CCtx* cctx, rawSeq* seq, size_t nbSeq)
+{
+    assert(cctx->stage == ZSTDcs_init);
+    assert(nbSeq == 0 || cctx->appliedParams.ldmParams.enableLdm != ZSTD_ps_enable);
+    cctx->externSeqStore.seq = seq;
+    cctx->externSeqStore.size = nbSeq;
+    cctx->externSeqStore.capacity = nbSeq;
+    cctx->externSeqStore.pos = 0;
+    cctx->externSeqStore.posInSequence = 0;
+}
+
+
+static size_t ZSTD_compressContinue_internal (ZSTD_CCtx* cctx,
+                              void* dst, size_t dstCapacity,
+                        const void* src, size_t srcSize,
+                               U32 frame, U32 lastFrameChunk)
+{
+    ZSTD_MatchState_t* const ms = &cctx->blockState.matchState;
+    size_t fhSize = 0;
+
+    DEBUGLOG(5, "ZSTD_compressContinue_internal, stage: %u, srcSize: %u",
+                cctx->stage, (unsigned)srcSize);
+    RETURN_ERROR_IF(cctx->stage==ZSTDcs_created, stage_wrong,
+                    "missing init (ZSTD_compressBegin)");
+
+    if (frame && (cctx->stage==ZSTDcs_init)) {
+        fhSize = ZSTD_writeFrameHeader(dst, dstCapacity, &cctx->appliedParams,
+                                       cctx->pledgedSrcSizePlusOne-1, cctx->dictID);
+        FORWARD_IF_ERROR(fhSize, "ZSTD_writeFrameHeader failed");
+        assert(fhSize <= dstCapacity);
+        dstCapacity -= fhSize;
+        dst = (char*)dst + fhSize;
+        cctx->stage = ZSTDcs_ongoing;
+    }
+
+    if (!srcSize) return fhSize;  /* do not generate an empty block if no input */
+
+    if (!ZSTD_window_update(&ms->window, src, srcSize, ms->forceNonContiguous)) {
+        ms->forceNonContiguous = 0;
+        ms->nextToUpdate = ms->window.dictLimit;
+    }
+    if (cctx->appliedParams.ldmParams.enableLdm == ZSTD_ps_enable) {
+        ZSTD_window_update(&cctx->ldmState.window, src, srcSize, /* forceNonContiguous */ 0);
+    }
+
+    if (!frame) {
+        /* overflow check and correction for block mode */
+        ZSTD_overflowCorrectIfNeeded(
+            ms, &cctx->workspace, &cctx->appliedParams,
+            src, (BYTE const*)src + srcSize);
+    }
+
+    DEBUGLOG(5, "ZSTD_compressContinue_internal (blockSize=%u)", (unsigned)cctx->blockSizeMax);
+    {   size_t const cSize = frame ?
+                             ZSTD_compress_frameChunk (cctx, dst, dstCapacity, src, srcSize, lastFrameChunk) :
+                             ZSTD_compressBlock_internal (cctx, dst, dstCapacity, src, srcSize, 0 /* frame */);
+        FORWARD_IF_ERROR(cSize, "%s", frame ? "ZSTD_compress_frameChunk failed" : "ZSTD_compressBlock_internal failed");
+        cctx->consumedSrcSize += srcSize;
+        cctx->producedCSize += (cSize + fhSize);
+        assert(!(cctx->appliedParams.fParams.contentSizeFlag && cctx->pledgedSrcSizePlusOne == 0));
+        if (cctx->pledgedSrcSizePlusOne != 0) {  /* control src size */
+            ZSTD_STATIC_ASSERT(ZSTD_CONTENTSIZE_UNKNOWN == (unsigned long long)-1);
+            RETURN_ERROR_IF(
+                cctx->consumedSrcSize+1 > cctx->pledgedSrcSizePlusOne,
+                srcSize_wrong,
+                "error : pledgedSrcSize = %u, while realSrcSize >= %u",
+                (unsigned)cctx->pledgedSrcSizePlusOne-1,
+                (unsigned)cctx->consumedSrcSize);
+        }
+        return cSize + fhSize;
+    }
+}
+
+size_t ZSTD_compressContinue_public(ZSTD_CCtx* cctx,
+                                        void* dst, size_t dstCapacity,
+                                  const void* src, size_t srcSize)
+{
+    DEBUGLOG(5, "ZSTD_compressContinue (srcSize=%u)", (unsigned)srcSize);
+    return ZSTD_compressContinue_internal(cctx, dst, dstCapacity, src, srcSize, 1 /* frame mode */, 0 /* last chunk */);
+}
+
+/* NOTE: Must just wrap ZSTD_compressContinue_public() */
+size_t ZSTD_compressContinue(ZSTD_CCtx* cctx,
+                             void* dst, size_t dstCapacity,
+                       const void* src, size_t srcSize)
+{
+    return ZSTD_compressContinue_public(cctx, dst, dstCapacity, src, srcSize);
+}
+
+static size_t ZSTD_getBlockSize_deprecated(const ZSTD_CCtx* cctx)
+{
+    ZSTD_compressionParameters const cParams = cctx->appliedParams.cParams;
+    assert(!ZSTD_checkCParams(cParams));
+    return MIN(cctx->appliedParams.maxBlockSize, (size_t)1 << cParams.windowLog);
+}
+
+/* NOTE: Must just wrap ZSTD_getBlockSize_deprecated() */
+size_t ZSTD_getBlockSize(const ZSTD_CCtx* cctx)
+{
+    return ZSTD_getBlockSize_deprecated(cctx);
+}
+
+/* NOTE: Must just wrap ZSTD_compressBlock_deprecated() */
+size_t ZSTD_compressBlock_deprecated(ZSTD_CCtx* cctx, void* dst, size_t dstCapacity, const void* src, size_t srcSize)
+{
+    DEBUGLOG(5, "ZSTD_compressBlock: srcSize = %u", (unsigned)srcSize);
+    { size_t const blockSizeMax = ZSTD_getBlockSize_deprecated(cctx);
+      RETURN_ERROR_IF(srcSize > blockSizeMax, srcSize_wrong, "input is larger than a block"); }
+
+    return ZSTD_compressContinue_internal(cctx, dst, dstCapacity, src, srcSize, 0 /* frame mode */, 0 /* last chunk */);
+}
+
+/* NOTE: Must just wrap ZSTD_compressBlock_deprecated() */
+size_t ZSTD_compressBlock(ZSTD_CCtx* cctx, void* dst, size_t dstCapacity, const void* src, size_t srcSize)
+{
+    return ZSTD_compressBlock_deprecated(cctx, dst, dstCapacity, src, srcSize);
+}
+
+/*! ZSTD_loadDictionaryContent() :
+ *  @return : 0, or an error code
+ */
+static size_t
+ZSTD_loadDictionaryContent(ZSTD_MatchState_t* ms,
+                        ldmState_t* ls,
+                        ZSTD_cwksp* ws,
+                        ZSTD_CCtx_params const* params,
+                        const void* src, size_t srcSize,
+                        ZSTD_dictTableLoadMethod_e dtlm,
+                        ZSTD_tableFillPurpose_e tfp)
+{
+    const BYTE* ip = (const BYTE*) src;
+    const BYTE* const iend = ip + srcSize;
+    int const loadLdmDict = params->ldmParams.enableLdm == ZSTD_ps_enable && ls != NULL;
+
+    /* Assert that the ms params match the params we're being given */
+    ZSTD_assertEqualCParams(params->cParams, ms->cParams);
+
+    {   /* Ensure large dictionaries can't cause index overflow */
+
+        /* Allow the dictionary to set indices up to exactly ZSTD_CURRENT_MAX.
+         * Dictionaries right at the edge will immediately trigger overflow
+         * correction, but I don't want to insert extra constraints here.
+         */
+        U32 maxDictSize = ZSTD_CURRENT_MAX - ZSTD_WINDOW_START_INDEX;
+
+        int const CDictTaggedIndices = ZSTD_CDictIndicesAreTagged(&params->cParams);
+        if (CDictTaggedIndices && tfp == ZSTD_tfp_forCDict) {
+            /* Some dictionary matchfinders in zstd use "short cache",
+             * which treats the lower ZSTD_SHORT_CACHE_TAG_BITS of each
+             * CDict hashtable entry as a tag rather than as part of an index.
+             * When short cache is used, we need to truncate the dictionary
+             * so that its indices don't overlap with the tag. */
+            U32 const shortCacheMaxDictSize = (1u << (32 - ZSTD_SHORT_CACHE_TAG_BITS)) - ZSTD_WINDOW_START_INDEX;
+            maxDictSize = MIN(maxDictSize, shortCacheMaxDictSize);
+            assert(!loadLdmDict);
+        }
+
+        /* If the dictionary is too large, only load the suffix of the dictionary. */
+        if (srcSize > maxDictSize) {
+            ip = iend - maxDictSize;
+            src = ip;
+            srcSize = maxDictSize;
+        }
+    }
+
+    if (srcSize > ZSTD_CHUNKSIZE_MAX) {
+        /* We must have cleared our windows when our source is this large. */
+        assert(ZSTD_window_isEmpty(ms->window));
+        if (loadLdmDict) assert(ZSTD_window_isEmpty(ls->window));
+    }
+    ZSTD_window_update(&ms->window, src, srcSize, /* forceNonContiguous */ 0);
+
+    DEBUGLOG(4, "ZSTD_loadDictionaryContent: useRowMatchFinder=%d", (int)params->useRowMatchFinder);
+
+    if (loadLdmDict) { /* Load the entire dict into LDM matchfinders. */
+        DEBUGLOG(4, "ZSTD_loadDictionaryContent: Trigger loadLdmDict");
+        ZSTD_window_update(&ls->window, src, srcSize, /* forceNonContiguous */ 0);
+        ls->loadedDictEnd = params->forceWindow ? 0 : (U32)(iend - ls->window.base);
+        ZSTD_ldm_fillHashTable(ls, ip, iend, &params->ldmParams);
+        DEBUGLOG(4, "ZSTD_loadDictionaryContent: ZSTD_ldm_fillHashTable completes");
+    }
+
+    /* If the dict is larger than we can reasonably index in our tables, only load the suffix. */
+    {   U32 maxDictSize = 1U << MIN(MAX(params->cParams.hashLog + 3, params->cParams.chainLog + 1), 31);
+        if (srcSize > maxDictSize) {
+            ip = iend - maxDictSize;
+            src = ip;
+            srcSize = maxDictSize;
+        }
+    }
+
+    ms->nextToUpdate = (U32)(ip - ms->window.base);
+    ms->loadedDictEnd = params->forceWindow ? 0 : (U32)(iend - ms->window.base);
+    ms->forceNonContiguous = params->deterministicRefPrefix;
+
+    if (srcSize <= HASH_READ_SIZE) return 0;
+
+    ZSTD_overflowCorrectIfNeeded(ms, ws, params, ip, iend);
+
+    switch(params->cParams.strategy)
+    {
+    case ZSTD_fast:
+        ZSTD_fillHashTable(ms, iend, dtlm, tfp);
+        break;
+    case ZSTD_dfast:
+#ifndef ZSTD_EXCLUDE_DFAST_BLOCK_COMPRESSOR
+        ZSTD_fillDoubleHashTable(ms, iend, dtlm, tfp);
+#else
+        assert(0); /* shouldn't be called: cparams should've been adjusted. */
+#endif
+        break;
+
+    case ZSTD_greedy:
+    case ZSTD_lazy:
+    case ZSTD_lazy2:
+#if !defined(ZSTD_EXCLUDE_GREEDY_BLOCK_COMPRESSOR) \
+ || !defined(ZSTD_EXCLUDE_LAZY_BLOCK_COMPRESSOR) \
+ || !defined(ZSTD_EXCLUDE_LAZY2_BLOCK_COMPRESSOR)
+        assert(srcSize >= HASH_READ_SIZE);
+        if (ms->dedicatedDictSearch) {
+            assert(ms->chainTable != NULL);
+            ZSTD_dedicatedDictSearch_lazy_loadDictionary(ms, iend-HASH_READ_SIZE);
+        } else {
+            assert(params->useRowMatchFinder != ZSTD_ps_auto);
+            if (params->useRowMatchFinder == ZSTD_ps_enable) {
+                size_t const tagTableSize = ((size_t)1 << params->cParams.hashLog);
+                ZSTD_memset(ms->tagTable, 0, tagTableSize);
+                ZSTD_row_update(ms, iend-HASH_READ_SIZE);
+                DEBUGLOG(4, "Using row-based hash table for lazy dict");
+            } else {
+                ZSTD_insertAndFindFirstIndex(ms, iend-HASH_READ_SIZE);
+                DEBUGLOG(4, "Using chain-based hash table for lazy dict");
+            }
+        }
+#else
+        assert(0); /* shouldn't be called: cparams should've been adjusted. */
+#endif
+        break;
+
+    case ZSTD_btlazy2:   /* we want the dictionary table fully sorted */
+    case ZSTD_btopt:
+    case ZSTD_btultra:
+    case ZSTD_btultra2:
+#if !defined(ZSTD_EXCLUDE_BTLAZY2_BLOCK_COMPRESSOR) \
+ || !defined(ZSTD_EXCLUDE_BTOPT_BLOCK_COMPRESSOR) \
+ || !defined(ZSTD_EXCLUDE_BTULTRA_BLOCK_COMPRESSOR)
+        assert(srcSize >= HASH_READ_SIZE);
+        DEBUGLOG(4, "Fill %u bytes into the Binary Tree", (unsigned)srcSize);
+        ZSTD_updateTree(ms, iend-HASH_READ_SIZE, iend);
+#else
+        assert(0); /* shouldn't be called: cparams should've been adjusted. */
+#endif
+        break;
+
+    default:
+        assert(0);  /* not possible : not a valid strategy id */
+    }
+
+    ms->nextToUpdate = (U32)(iend - ms->window.base);
+    return 0;
+}
+
+
+/* Dictionaries that assign zero probability to symbols that show up causes problems
+ * when FSE encoding. Mark dictionaries with zero probability symbols as FSE_repeat_check
+ * and only dictionaries with 100% valid symbols can be assumed valid.
+ */
+static FSE_repeat ZSTD_dictNCountRepeat(short* normalizedCounter, unsigned dictMaxSymbolValue, unsigned maxSymbolValue)
+{
+    U32 s;
+    if (dictMaxSymbolValue < maxSymbolValue) {
+        return FSE_repeat_check;
+    }
+    for (s = 0; s <= maxSymbolValue; ++s) {
+        if (normalizedCounter[s] == 0) {
+            return FSE_repeat_check;
+        }
+    }
+    return FSE_repeat_valid;
+}
+
+size_t ZSTD_loadCEntropy(ZSTD_compressedBlockState_t* bs, void* workspace,
+                         const void* const dict, size_t dictSize)
+{
+    short offcodeNCount[MaxOff+1];
+    unsigned offcodeMaxValue = MaxOff;
+    const BYTE* dictPtr = (const BYTE*)dict;    /* skip magic num and dict ID */
+    const BYTE* const dictEnd = dictPtr + dictSize;
+    dictPtr += 8;
+    bs->entropy.huf.repeatMode = HUF_repeat_check;
+
+    {   unsigned maxSymbolValue = 255;
+        unsigned hasZeroWeights = 1;
+        size_t const hufHeaderSize = HUF_readCTable((HUF_CElt*)bs->entropy.huf.CTable, &maxSymbolValue, dictPtr,
+            (size_t)(dictEnd-dictPtr), &hasZeroWeights);
+
+        /* We only set the loaded table as valid if it contains all non-zero
+         * weights. Otherwise, we set it to check */
+        if (!hasZeroWeights && maxSymbolValue == 255)
+            bs->entropy.huf.repeatMode = HUF_repeat_valid;
+
+        RETURN_ERROR_IF(HUF_isError(hufHeaderSize), dictionary_corrupted, "");
+        dictPtr += hufHeaderSize;
+    }
+
+    {   unsigned offcodeLog;
+        size_t const offcodeHeaderSize = FSE_readNCount(offcodeNCount, &offcodeMaxValue, &offcodeLog, dictPtr, (size_t)(dictEnd-dictPtr));
+        RETURN_ERROR_IF(FSE_isError(offcodeHeaderSize), dictionary_corrupted, "");
+        RETURN_ERROR_IF(offcodeLog > OffFSELog, dictionary_corrupted, "");
+        /* fill all offset symbols to avoid garbage at end of table */
+        RETURN_ERROR_IF(FSE_isError(FSE_buildCTable_wksp(
+                bs->entropy.fse.offcodeCTable,
+                offcodeNCount, MaxOff, offcodeLog,
+                workspace, HUF_WORKSPACE_SIZE)),
+            dictionary_corrupted, "");
+        /* Defer checking offcodeMaxValue because we need to know the size of the dictionary content */
+        dictPtr += offcodeHeaderSize;
+    }
+
+    {   short matchlengthNCount[MaxML+1];
+        unsigned matchlengthMaxValue = MaxML, matchlengthLog;
+        size_t const matchlengthHeaderSize = FSE_readNCount(matchlengthNCount, &matchlengthMaxValue, &matchlengthLog, dictPtr, (size_t)(dictEnd-dictPtr));
+        RETURN_ERROR_IF(FSE_isError(matchlengthHeaderSize), dictionary_corrupted, "");
+        RETURN_ERROR_IF(matchlengthLog > MLFSELog, dictionary_corrupted, "");
+        RETURN_ERROR_IF(FSE_isError(FSE_buildCTable_wksp(
+                bs->entropy.fse.matchlengthCTable,
+                matchlengthNCount, matchlengthMaxValue, matchlengthLog,
+                workspace, HUF_WORKSPACE_SIZE)),
+            dictionary_corrupted, "");
+        bs->entropy.fse.matchlength_repeatMode = ZSTD_dictNCountRepeat(matchlengthNCount, matchlengthMaxValue, MaxML);
+        dictPtr += matchlengthHeaderSize;
+    }
+
+    {   short litlengthNCount[MaxLL+1];
+        unsigned litlengthMaxValue = MaxLL, litlengthLog;
+        size_t const litlengthHeaderSize = FSE_readNCount(litlengthNCount, &litlengthMaxValue, &litlengthLog, dictPtr, (size_t)(dictEnd-dictPtr));
+        RETURN_ERROR_IF(FSE_isError(litlengthHeaderSize), dictionary_corrupted, "");
+        RETURN_ERROR_IF(litlengthLog > LLFSELog, dictionary_corrupted, "");
+        RETURN_ERROR_IF(FSE_isError(FSE_buildCTable_wksp(
+                bs->entropy.fse.litlengthCTable,
+                litlengthNCount, litlengthMaxValue, litlengthLog,
+                workspace, HUF_WORKSPACE_SIZE)),
+            dictionary_corrupted, "");
+        bs->entropy.fse.litlength_repeatMode = ZSTD_dictNCountRepeat(litlengthNCount, litlengthMaxValue, MaxLL);
+        dictPtr += litlengthHeaderSize;
+    }
+
+    RETURN_ERROR_IF(dictPtr+12 > dictEnd, dictionary_corrupted, "");
+    bs->rep[0] = MEM_readLE32(dictPtr+0);
+    bs->rep[1] = MEM_readLE32(dictPtr+4);
+    bs->rep[2] = MEM_readLE32(dictPtr+8);
+    dictPtr += 12;
+
+    {   size_t const dictContentSize = (size_t)(dictEnd - dictPtr);
+        U32 offcodeMax = MaxOff;
+        if (dictContentSize <= ((U32)-1) - 128 KB) {
+            U32 const maxOffset = (U32)dictContentSize + 128 KB; /* The maximum offset that must be supported */
+            offcodeMax = ZSTD_highbit32(maxOffset); /* Calculate minimum offset code required to represent maxOffset */
+        }
+        /* All offset values <= dictContentSize + 128 KB must be representable for a valid table */
+        bs->entropy.fse.offcode_repeatMode = ZSTD_dictNCountRepeat(offcodeNCount, offcodeMaxValue, MIN(offcodeMax, MaxOff));
+
+        /* All repCodes must be <= dictContentSize and != 0 */
+        {   U32 u;
+            for (u=0; u<3; u++) {
+                RETURN_ERROR_IF(bs->rep[u] == 0, dictionary_corrupted, "");
+                RETURN_ERROR_IF(bs->rep[u] > dictContentSize, dictionary_corrupted, "");
+    }   }   }
+
+    return (size_t)(dictPtr - (const BYTE*)dict);
+}
+
+/* Dictionary format :
+ * See :
+ * https://github.com/facebook/zstd/blob/release/doc/zstd_compression_format.md#dictionary-format
+ */
+/*! ZSTD_loadZstdDictionary() :
+ * @return : dictID, or an error code
+ *  assumptions : magic number supposed already checked
+ *                dictSize supposed >= 8
+ */
+static size_t ZSTD_loadZstdDictionary(ZSTD_compressedBlockState_t* bs,
+                                      ZSTD_MatchState_t* ms,
+                                      ZSTD_cwksp* ws,
+                                      ZSTD_CCtx_params const* params,
+                                      const void* dict, size_t dictSize,
+                                      ZSTD_dictTableLoadMethod_e dtlm,
+                                      ZSTD_tableFillPurpose_e tfp,
+                                      void* workspace)
+{
+    const BYTE* dictPtr = (const BYTE*)dict;
+    const BYTE* const dictEnd = dictPtr + dictSize;
+    size_t dictID;
+    size_t eSize;
+    ZSTD_STATIC_ASSERT(HUF_WORKSPACE_SIZE >= (1<<MAX(MLFSELog,LLFSELog)));
+    assert(dictSize >= 8);
+    assert(MEM_readLE32(dictPtr) == ZSTD_MAGIC_DICTIONARY);
+
+    dictID = params->fParams.noDictIDFlag ? 0 :  MEM_readLE32(dictPtr + 4 /* skip magic number */ );
+    eSize = ZSTD_loadCEntropy(bs, workspace, dict, dictSize);
+    FORWARD_IF_ERROR(eSize, "ZSTD_loadCEntropy failed");
+    dictPtr += eSize;
+
+    {
+        size_t const dictContentSize = (size_t)(dictEnd - dictPtr);
+        FORWARD_IF_ERROR(ZSTD_loadDictionaryContent(
+            ms, NULL, ws, params, dictPtr, dictContentSize, dtlm, tfp), "");
+    }
+    return dictID;
+}
+
+/** ZSTD_compress_insertDictionary() :
+*   @return : dictID, or an error code */
+static size_t
+ZSTD_compress_insertDictionary(ZSTD_compressedBlockState_t* bs,
+                               ZSTD_MatchState_t* ms,
+                               ldmState_t* ls,
+                               ZSTD_cwksp* ws,
+                         const ZSTD_CCtx_params* params,
+                         const void* dict, size_t dictSize,
+                               ZSTD_dictContentType_e dictContentType,
+                               ZSTD_dictTableLoadMethod_e dtlm,
+                               ZSTD_tableFillPurpose_e tfp,
+                               void* workspace)
+{
+    DEBUGLOG(4, "ZSTD_compress_insertDictionary (dictSize=%u)", (U32)dictSize);
+    if ((dict==NULL) || (dictSize<8)) {
+        RETURN_ERROR_IF(dictContentType == ZSTD_dct_fullDict, dictionary_wrong, "");
+        return 0;
+    }
+
+    ZSTD_reset_compressedBlockState(bs);
+
+    /* dict restricted modes */
+    if (dictContentType == ZSTD_dct_rawContent)
+        return ZSTD_loadDictionaryContent(ms, ls, ws, params, dict, dictSize, dtlm, tfp);
+
+    if (MEM_readLE32(dict) != ZSTD_MAGIC_DICTIONARY) {
+        if (dictContentType == ZSTD_dct_auto) {
+            DEBUGLOG(4, "raw content dictionary detected");
+            return ZSTD_loadDictionaryContent(
+                ms, ls, ws, params, dict, dictSize, dtlm, tfp);
+        }
+        RETURN_ERROR_IF(dictContentType == ZSTD_dct_fullDict, dictionary_wrong, "");
+        assert(0);   /* impossible */
+    }
+
+    /* dict as full zstd dictionary */
+    return ZSTD_loadZstdDictionary(
+        bs, ms, ws, params, dict, dictSize, dtlm, tfp, workspace);
+}
+
+#define ZSTD_USE_CDICT_PARAMS_SRCSIZE_CUTOFF (128 KB)
+#define ZSTD_USE_CDICT_PARAMS_DICTSIZE_MULTIPLIER (6ULL)
+
+/*! ZSTD_compressBegin_internal() :
+ * Assumption : either @dict OR @cdict (or none) is non-NULL, never both
+ * @return : 0, or an error code */
+static size_t ZSTD_compressBegin_internal(ZSTD_CCtx* cctx,
+                                    const void* dict, size_t dictSize,
+                                    ZSTD_dictContentType_e dictContentType,
+                                    ZSTD_dictTableLoadMethod_e dtlm,
+                                    const ZSTD_CDict* cdict,
+                                    const ZSTD_CCtx_params* params, U64 pledgedSrcSize,
+                                    ZSTD_buffered_policy_e zbuff)
+{
+    size_t const dictContentSize = cdict ? cdict->dictContentSize : dictSize;
+#if ZSTD_TRACE
+    cctx->traceCtx = (ZSTD_trace_compress_begin != NULL) ? ZSTD_trace_compress_begin(cctx) : 0;
+#endif
+    DEBUGLOG(4, "ZSTD_compressBegin_internal: wlog=%u", params->cParams.windowLog);
+    /* params are supposed to be fully validated at this point */
+    assert(!ZSTD_isError(ZSTD_checkCParams(params->cParams)));
+    assert(!((dict) && (cdict)));  /* either dict or cdict, not both */
+    if ( (cdict)
+      && (cdict->dictContentSize > 0)
+      && ( pledgedSrcSize < ZSTD_USE_CDICT_PARAMS_SRCSIZE_CUTOFF
+        || pledgedSrcSize < cdict->dictContentSize * ZSTD_USE_CDICT_PARAMS_DICTSIZE_MULTIPLIER
+        || pledgedSrcSize == ZSTD_CONTENTSIZE_UNKNOWN
+        || cdict->compressionLevel == 0)
+      && (params->attachDictPref != ZSTD_dictForceLoad) ) {
+        return ZSTD_resetCCtx_usingCDict(cctx, cdict, params, pledgedSrcSize, zbuff);
+    }
+
+    FORWARD_IF_ERROR( ZSTD_resetCCtx_internal(cctx, params, pledgedSrcSize,
+                                     dictContentSize,
+                                     ZSTDcrp_makeClean, zbuff) , "");
+    {   size_t const dictID = cdict ?
+                ZSTD_compress_insertDictionary(
+                        cctx->blockState.prevCBlock, &cctx->blockState.matchState,
+                        &cctx->ldmState, &cctx->workspace, &cctx->appliedParams, cdict->dictContent,
+                        cdict->dictContentSize, cdict->dictContentType, dtlm,
+                        ZSTD_tfp_forCCtx, cctx->tmpWorkspace)
+              : ZSTD_compress_insertDictionary(
+                        cctx->blockState.prevCBlock, &cctx->blockState.matchState,
+                        &cctx->ldmState, &cctx->workspace, &cctx->appliedParams, dict, dictSize,
+                        dictContentType, dtlm, ZSTD_tfp_forCCtx, cctx->tmpWorkspace);
+        FORWARD_IF_ERROR(dictID, "ZSTD_compress_insertDictionary failed");
+        assert(dictID <= UINT_MAX);
+        cctx->dictID = (U32)dictID;
+        cctx->dictContentSize = dictContentSize;
+    }
+    return 0;
+}
+
+size_t ZSTD_compressBegin_advanced_internal(ZSTD_CCtx* cctx,
+                                    const void* dict, size_t dictSize,
+                                    ZSTD_dictContentType_e dictContentType,
+                                    ZSTD_dictTableLoadMethod_e dtlm,
+                                    const ZSTD_CDict* cdict,
+                                    const ZSTD_CCtx_params* params,
+                                    unsigned long long pledgedSrcSize)
+{
+    DEBUGLOG(4, "ZSTD_compressBegin_advanced_internal: wlog=%u", params->cParams.windowLog);
+    /* compression parameters verification and optimization */
+    FORWARD_IF_ERROR( ZSTD_checkCParams(params->cParams) , "");
+    return ZSTD_compressBegin_internal(cctx,
+                                       dict, dictSize, dictContentType, dtlm,
+                                       cdict,
+                                       params, pledgedSrcSize,
+                                       ZSTDb_not_buffered);
+}
+
+/*! ZSTD_compressBegin_advanced() :
+*   @return : 0, or an error code */
+size_t ZSTD_compressBegin_advanced(ZSTD_CCtx* cctx,
+                             const void* dict, size_t dictSize,
+                                   ZSTD_parameters params, unsigned long long pledgedSrcSize)
+{
+    ZSTD_CCtx_params cctxParams;
+    ZSTD_CCtxParams_init_internal(&cctxParams, &params, ZSTD_NO_CLEVEL);
+    return ZSTD_compressBegin_advanced_internal(cctx,
+                                            dict, dictSize, ZSTD_dct_auto, ZSTD_dtlm_fast,
+                                            NULL /*cdict*/,
+                                            &cctxParams, pledgedSrcSize);
+}
+
+static size_t
+ZSTD_compressBegin_usingDict_deprecated(ZSTD_CCtx* cctx, const void* dict, size_t dictSize, int compressionLevel)
+{
+    ZSTD_CCtx_params cctxParams;
+    {   ZSTD_parameters const params = ZSTD_getParams_internal(compressionLevel, ZSTD_CONTENTSIZE_UNKNOWN, dictSize, ZSTD_cpm_noAttachDict);
+        ZSTD_CCtxParams_init_internal(&cctxParams, &params, (compressionLevel == 0) ? ZSTD_CLEVEL_DEFAULT : compressionLevel);
+    }
+    DEBUGLOG(4, "ZSTD_compressBegin_usingDict (dictSize=%u)", (unsigned)dictSize);
+    return ZSTD_compressBegin_internal(cctx, dict, dictSize, ZSTD_dct_auto, ZSTD_dtlm_fast, NULL,
+                                       &cctxParams, ZSTD_CONTENTSIZE_UNKNOWN, ZSTDb_not_buffered);
+}
+
+size_t
+ZSTD_compressBegin_usingDict(ZSTD_CCtx* cctx, const void* dict, size_t dictSize, int compressionLevel)
+{
+    return ZSTD_compressBegin_usingDict_deprecated(cctx, dict, dictSize, compressionLevel);
+}
+
+size_t ZSTD_compressBegin(ZSTD_CCtx* cctx, int compressionLevel)
+{
+    return ZSTD_compressBegin_usingDict_deprecated(cctx, NULL, 0, compressionLevel);
+}
+
+
+/*! ZSTD_writeEpilogue() :
+*   Ends a frame.
+*   @return : nb of bytes written into dst (or an error code) */
+static size_t ZSTD_writeEpilogue(ZSTD_CCtx* cctx, void* dst, size_t dstCapacity)
+{
+    BYTE* const ostart = (BYTE*)dst;
+    BYTE* op = ostart;
+
+    DEBUGLOG(4, "ZSTD_writeEpilogue");
+    RETURN_ERROR_IF(cctx->stage == ZSTDcs_created, stage_wrong, "init missing");
+
+    /* special case : empty frame */
+    if (cctx->stage == ZSTDcs_init) {
+        size_t fhSize = ZSTD_writeFrameHeader(dst, dstCapacity, &cctx->appliedParams, 0, 0);
+        FORWARD_IF_ERROR(fhSize, "ZSTD_writeFrameHeader failed");
+        dstCapacity -= fhSize;
+        op += fhSize;
+        cctx->stage = ZSTDcs_ongoing;
+    }
+
+    if (cctx->stage != ZSTDcs_ending) {
+        /* write one last empty block, make it the "last" block */
+        U32 const cBlockHeader24 = 1 /* last block */ + (((U32)bt_raw)<<1) + 0;
+        ZSTD_STATIC_ASSERT(ZSTD_BLOCKHEADERSIZE == 3);
+        RETURN_ERROR_IF(dstCapacity<3, dstSize_tooSmall, "no room for epilogue");
+        MEM_writeLE24(op, cBlockHeader24);
+        op += ZSTD_blockHeaderSize;
+        dstCapacity -= ZSTD_blockHeaderSize;
+    }
+
+    if (cctx->appliedParams.fParams.checksumFlag) {
+        U32 const checksum = (U32) XXH64_digest(&cctx->xxhState);
+        RETURN_ERROR_IF(dstCapacity<4, dstSize_tooSmall, "no room for checksum");
+        DEBUGLOG(4, "ZSTD_writeEpilogue: write checksum : %08X", (unsigned)checksum);
+        MEM_writeLE32(op, checksum);
+        op += 4;
+    }
+
+    cctx->stage = ZSTDcs_created;  /* return to "created but no init" status */
+    return (size_t)(op-ostart);
+}
+
+void ZSTD_CCtx_trace(ZSTD_CCtx* cctx, size_t extraCSize)
+{
+#if ZSTD_TRACE
+    if (cctx->traceCtx && ZSTD_trace_compress_end != NULL) {
+        int const streaming = cctx->inBuffSize > 0 || cctx->outBuffSize > 0 || cctx->appliedParams.nbWorkers > 0;
+        ZSTD_Trace trace;
+        ZSTD_memset(&trace, 0, sizeof(trace));
+        trace.version = ZSTD_VERSION_NUMBER;
+        trace.streaming = streaming;
+        trace.dictionaryID = cctx->dictID;
+        trace.dictionarySize = cctx->dictContentSize;
+        trace.uncompressedSize = cctx->consumedSrcSize;
+        trace.compressedSize = cctx->producedCSize + extraCSize;
+        trace.params = &cctx->appliedParams;
+        trace.cctx = cctx;
+        ZSTD_trace_compress_end(cctx->traceCtx, &trace);
+    }
+    cctx->traceCtx = 0;
+#else
+    (void)cctx;
+    (void)extraCSize;
+#endif
+}
+
+size_t ZSTD_compressEnd_public(ZSTD_CCtx* cctx,
+                               void* dst, size_t dstCapacity,
+                         const void* src, size_t srcSize)
+{
+    size_t endResult;
+    size_t const cSize = ZSTD_compressContinue_internal(cctx,
+                                dst, dstCapacity, src, srcSize,
+                                1 /* frame mode */, 1 /* last chunk */);
+    FORWARD_IF_ERROR(cSize, "ZSTD_compressContinue_internal failed");
+    endResult = ZSTD_writeEpilogue(cctx, (char*)dst + cSize, dstCapacity-cSize);
+    FORWARD_IF_ERROR(endResult, "ZSTD_writeEpilogue failed");
+    assert(!(cctx->appliedParams.fParams.contentSizeFlag && cctx->pledgedSrcSizePlusOne == 0));
+    if (cctx->pledgedSrcSizePlusOne != 0) {  /* control src size */
+        ZSTD_STATIC_ASSERT(ZSTD_CONTENTSIZE_UNKNOWN == (unsigned long long)-1);
+        DEBUGLOG(4, "end of frame : controlling src size");
+        RETURN_ERROR_IF(
+            cctx->pledgedSrcSizePlusOne != cctx->consumedSrcSize+1,
+            srcSize_wrong,
+             "error : pledgedSrcSize = %u, while realSrcSize = %u",
+            (unsigned)cctx->pledgedSrcSizePlusOne-1,
+            (unsigned)cctx->consumedSrcSize);
+    }
+    ZSTD_CCtx_trace(cctx, endResult);
+    return cSize + endResult;
+}
+
+/* NOTE: Must just wrap ZSTD_compressEnd_public() */
+size_t ZSTD_compressEnd(ZSTD_CCtx* cctx,
+                        void* dst, size_t dstCapacity,
+                  const void* src, size_t srcSize)
+{
+    return ZSTD_compressEnd_public(cctx, dst, dstCapacity, src, srcSize);
+}
+
+size_t ZSTD_compress_advanced (ZSTD_CCtx* cctx,
+                               void* dst, size_t dstCapacity,
+                         const void* src, size_t srcSize,
+                         const void* dict,size_t dictSize,
+                               ZSTD_parameters params)
+{
+    DEBUGLOG(4, "ZSTD_compress_advanced");
+    FORWARD_IF_ERROR(ZSTD_checkCParams(params.cParams), "");
+    ZSTD_CCtxParams_init_internal(&cctx->simpleApiParams, &params, ZSTD_NO_CLEVEL);
+    return ZSTD_compress_advanced_internal(cctx,
+                                           dst, dstCapacity,
+                                           src, srcSize,
+                                           dict, dictSize,
+                                           &cctx->simpleApiParams);
+}
+
+/* Internal */
+size_t ZSTD_compress_advanced_internal(
+        ZSTD_CCtx* cctx,
+        void* dst, size_t dstCapacity,
+        const void* src, size_t srcSize,
+        const void* dict,size_t dictSize,
+        const ZSTD_CCtx_params* params)
+{
+    DEBUGLOG(4, "ZSTD_compress_advanced_internal (srcSize:%u)", (unsigned)srcSize);
+    FORWARD_IF_ERROR( ZSTD_compressBegin_internal(cctx,
+                         dict, dictSize, ZSTD_dct_auto, ZSTD_dtlm_fast, NULL,
+                         params, srcSize, ZSTDb_not_buffered) , "");
+    return ZSTD_compressEnd_public(cctx, dst, dstCapacity, src, srcSize);
+}
+
+size_t ZSTD_compress_usingDict(ZSTD_CCtx* cctx,
+                               void* dst, size_t dstCapacity,
+                         const void* src, size_t srcSize,
+                         const void* dict, size_t dictSize,
+                               int compressionLevel)
+{
+    {
+        ZSTD_parameters const params = ZSTD_getParams_internal(compressionLevel, srcSize, dict ? dictSize : 0, ZSTD_cpm_noAttachDict);
+        assert(params.fParams.contentSizeFlag == 1);
+        ZSTD_CCtxParams_init_internal(&cctx->simpleApiParams, &params, (compressionLevel == 0) ? ZSTD_CLEVEL_DEFAULT: compressionLevel);
+    }
+    DEBUGLOG(4, "ZSTD_compress_usingDict (srcSize=%u)", (unsigned)srcSize);
+    return ZSTD_compress_advanced_internal(cctx, dst, dstCapacity, src, srcSize, dict, dictSize, &cctx->simpleApiParams);
+}
+
+size_t ZSTD_compressCCtx(ZSTD_CCtx* cctx,
+                         void* dst, size_t dstCapacity,
+                   const void* src, size_t srcSize,
+                         int compressionLevel)
+{
+    DEBUGLOG(4, "ZSTD_compressCCtx (srcSize=%u)", (unsigned)srcSize);
+    assert(cctx != NULL);
+    return ZSTD_compress_usingDict(cctx, dst, dstCapacity, src, srcSize, NULL, 0, compressionLevel);
+}
+
+size_t ZSTD_compress(void* dst, size_t dstCapacity,
+               const void* src, size_t srcSize,
+                     int compressionLevel)
+{
+    size_t result;
+#if ZSTD_COMPRESS_HEAPMODE
+    ZSTD_CCtx* cctx = ZSTD_createCCtx();
+    RETURN_ERROR_IF(!cctx, memory_allocation, "ZSTD_createCCtx failed");
+    result = ZSTD_compressCCtx(cctx, dst, dstCapacity, src, srcSize, compressionLevel);
+    ZSTD_freeCCtx(cctx);
+#else
+    ZSTD_CCtx ctxBody;
+    ZSTD_initCCtx(&ctxBody, ZSTD_defaultCMem);
+    result = ZSTD_compressCCtx(&ctxBody, dst, dstCapacity, src, srcSize, compressionLevel);
+    ZSTD_freeCCtxContent(&ctxBody);   /* can't free ctxBody itself, as it's on stack; free only heap content */
+#endif
+    return result;
+}
+
+
+/* =====  Dictionary API  ===== */
+
+/*! ZSTD_estimateCDictSize_advanced() :
+ *  Estimate amount of memory that will be needed to create a dictionary with following arguments */
+size_t ZSTD_estimateCDictSize_advanced(
+        size_t dictSize, ZSTD_compressionParameters cParams,
+        ZSTD_dictLoadMethod_e dictLoadMethod)
+{
+    DEBUGLOG(5, "sizeof(ZSTD_CDict) : %u", (unsigned)sizeof(ZSTD_CDict));
+    return ZSTD_cwksp_alloc_size(sizeof(ZSTD_CDict))
+         + ZSTD_cwksp_alloc_size(HUF_WORKSPACE_SIZE)
+         /* enableDedicatedDictSearch == 1 ensures that CDict estimation will not be too small
+          * in case we are using DDS with row-hash. */
+         + ZSTD_sizeof_matchState(&cParams, ZSTD_resolveRowMatchFinderMode(ZSTD_ps_auto, &cParams),
+                                  /* enableDedicatedDictSearch */ 1, /* forCCtx */ 0)
+         + (dictLoadMethod == ZSTD_dlm_byRef ? 0
+            : ZSTD_cwksp_alloc_size(ZSTD_cwksp_align(dictSize, sizeof(void *))));
+}
+
+size_t ZSTD_estimateCDictSize(size_t dictSize, int compressionLevel)
+{
+    ZSTD_compressionParameters const cParams = ZSTD_getCParams_internal(compressionLevel, ZSTD_CONTENTSIZE_UNKNOWN, dictSize, ZSTD_cpm_createCDict);
+    return ZSTD_estimateCDictSize_advanced(dictSize, cParams, ZSTD_dlm_byCopy);
+}
+
+size_t ZSTD_sizeof_CDict(const ZSTD_CDict* cdict)
+{
+    if (cdict==NULL) return 0;   /* support sizeof on NULL */
+    DEBUGLOG(5, "sizeof(*cdict) : %u", (unsigned)sizeof(*cdict));
+    /* cdict may be in the workspace */
+    return (cdict->workspace.workspace == cdict ? 0 : sizeof(*cdict))
+        + ZSTD_cwksp_sizeof(&cdict->workspace);
+}
+
+static size_t ZSTD_initCDict_internal(
+                    ZSTD_CDict* cdict,
+              const void* dictBuffer, size_t dictSize,
+                    ZSTD_dictLoadMethod_e dictLoadMethod,
+                    ZSTD_dictContentType_e dictContentType,
+                    ZSTD_CCtx_params params)
+{
+    DEBUGLOG(3, "ZSTD_initCDict_internal (dictContentType:%u)", (unsigned)dictContentType);
+    assert(!ZSTD_checkCParams(params.cParams));
+    cdict->matchState.cParams = params.cParams;
+    cdict->matchState.dedicatedDictSearch = params.enableDedicatedDictSearch;
+    if ((dictLoadMethod == ZSTD_dlm_byRef) || (!dictBuffer) || (!dictSize)) {
+        cdict->dictContent = dictBuffer;
+    } else {
+         void *internalBuffer = ZSTD_cwksp_reserve_object(&cdict->workspace, ZSTD_cwksp_align(dictSize, sizeof(void*)));
+        RETURN_ERROR_IF(!internalBuffer, memory_allocation, "NULL pointer!");
+        cdict->dictContent = internalBuffer;
+        ZSTD_memcpy(internalBuffer, dictBuffer, dictSize);
+    }
+    cdict->dictContentSize = dictSize;
+    cdict->dictContentType = dictContentType;
+
+    cdict->entropyWorkspace = (U32*)ZSTD_cwksp_reserve_object(&cdict->workspace, HUF_WORKSPACE_SIZE);
+
+
+    /* Reset the state to no dictionary */
+    ZSTD_reset_compressedBlockState(&cdict->cBlockState);
+    FORWARD_IF_ERROR(ZSTD_reset_matchState(
+        &cdict->matchState,
+        &cdict->workspace,
+        &params.cParams,
+        params.useRowMatchFinder,
+        ZSTDcrp_makeClean,
+        ZSTDirp_reset,
+        ZSTD_resetTarget_CDict), "");
+    /* (Maybe) load the dictionary
+     * Skips loading the dictionary if it is < 8 bytes.
+     */
+    {   params.compressionLevel = ZSTD_CLEVEL_DEFAULT;
+        params.fParams.contentSizeFlag = 1;
+        {   size_t const dictID = ZSTD_compress_insertDictionary(
+                    &cdict->cBlockState, &cdict->matchState, NULL, &cdict->workspace,
+                    &params, cdict->dictContent, cdict->dictContentSize,
+                    dictContentType, ZSTD_dtlm_full, ZSTD_tfp_forCDict, cdict->entropyWorkspace);
+            FORWARD_IF_ERROR(dictID, "ZSTD_compress_insertDictionary failed");
+            assert(dictID <= (size_t)(U32)-1);
+            cdict->dictID = (U32)dictID;
+        }
+    }
+
+    return 0;
+}
+
+static ZSTD_CDict*
+ZSTD_createCDict_advanced_internal(size_t dictSize,
+                                ZSTD_dictLoadMethod_e dictLoadMethod,
+                                ZSTD_compressionParameters cParams,
+                                ZSTD_ParamSwitch_e useRowMatchFinder,
+                                int enableDedicatedDictSearch,
+                                ZSTD_customMem customMem)
+{
+    if ((!customMem.customAlloc) ^ (!customMem.customFree)) return NULL;
+    DEBUGLOG(3, "ZSTD_createCDict_advanced_internal (dictSize=%u)", (unsigned)dictSize);
+
+    {   size_t const workspaceSize =
+            ZSTD_cwksp_alloc_size(sizeof(ZSTD_CDict)) +
+            ZSTD_cwksp_alloc_size(HUF_WORKSPACE_SIZE) +
+            ZSTD_sizeof_matchState(&cParams, useRowMatchFinder, enableDedicatedDictSearch, /* forCCtx */ 0) +
+            (dictLoadMethod == ZSTD_dlm_byRef ? 0
+             : ZSTD_cwksp_alloc_size(ZSTD_cwksp_align(dictSize, sizeof(void*))));
+        void* const workspace = ZSTD_customMalloc(workspaceSize, customMem);
+        ZSTD_cwksp ws;
+        ZSTD_CDict* cdict;
+
+        if (!workspace) {
+            ZSTD_customFree(workspace, customMem);
+            return NULL;
+        }
+
+        ZSTD_cwksp_init(&ws, workspace, workspaceSize, ZSTD_cwksp_dynamic_alloc);
+
+        cdict = (ZSTD_CDict*)ZSTD_cwksp_reserve_object(&ws, sizeof(ZSTD_CDict));
+        assert(cdict != NULL);
+        ZSTD_cwksp_move(&cdict->workspace, &ws);
+        cdict->customMem = customMem;
+        cdict->compressionLevel = ZSTD_NO_CLEVEL; /* signals advanced API usage */
+        cdict->useRowMatchFinder = useRowMatchFinder;
+        return cdict;
+    }
+}
+
+ZSTD_CDict* ZSTD_createCDict_advanced(const void* dictBuffer, size_t dictSize,
+                                      ZSTD_dictLoadMethod_e dictLoadMethod,
+                                      ZSTD_dictContentType_e dictContentType,
+                                      ZSTD_compressionParameters cParams,
+                                      ZSTD_customMem customMem)
+{
+    ZSTD_CCtx_params cctxParams;
+    ZSTD_memset(&cctxParams, 0, sizeof(cctxParams));
+    DEBUGLOG(3, "ZSTD_createCDict_advanced, dictSize=%u, mode=%u", (unsigned)dictSize, (unsigned)dictContentType);
+    ZSTD_CCtxParams_init(&cctxParams, 0);
+    cctxParams.cParams = cParams;
+    cctxParams.customMem = customMem;
+    return ZSTD_createCDict_advanced2(
+        dictBuffer, dictSize,
+        dictLoadMethod, dictContentType,
+        &cctxParams, customMem);
+}
+
+ZSTD_CDict* ZSTD_createCDict_advanced2(
+        const void* dict, size_t dictSize,
+        ZSTD_dictLoadMethod_e dictLoadMethod,
+        ZSTD_dictContentType_e dictContentType,
+        const ZSTD_CCtx_params* originalCctxParams,
+        ZSTD_customMem customMem)
+{
+    ZSTD_CCtx_params cctxParams = *originalCctxParams;
+    ZSTD_compressionParameters cParams;
+    ZSTD_CDict* cdict;
+
+    DEBUGLOG(3, "ZSTD_createCDict_advanced2, dictSize=%u, mode=%u", (unsigned)dictSize, (unsigned)dictContentType);
+    if (!customMem.customAlloc ^ !customMem.customFree) return NULL;
+
+    if (cctxParams.enableDedicatedDictSearch) {
+        cParams = ZSTD_dedicatedDictSearch_getCParams(
+            cctxParams.compressionLevel, dictSize);
+        ZSTD_overrideCParams(&cParams, &cctxParams.cParams);
+    } else {
+        cParams = ZSTD_getCParamsFromCCtxParams(
+            &cctxParams, ZSTD_CONTENTSIZE_UNKNOWN, dictSize, ZSTD_cpm_createCDict);
+    }
+
+    if (!ZSTD_dedicatedDictSearch_isSupported(&cParams)) {
+        /* Fall back to non-DDSS params */
+        cctxParams.enableDedicatedDictSearch = 0;
+        cParams = ZSTD_getCParamsFromCCtxParams(
+            &cctxParams, ZSTD_CONTENTSIZE_UNKNOWN, dictSize, ZSTD_cpm_createCDict);
+    }
+
+    DEBUGLOG(3, "ZSTD_createCDict_advanced2: DedicatedDictSearch=%u", cctxParams.enableDedicatedDictSearch);
+    cctxParams.cParams = cParams;
+    cctxParams.useRowMatchFinder = ZSTD_resolveRowMatchFinderMode(cctxParams.useRowMatchFinder, &cParams);
+
+    cdict = ZSTD_createCDict_advanced_internal(dictSize,
+                        dictLoadMethod, cctxParams.cParams,
+                        cctxParams.useRowMatchFinder, cctxParams.enableDedicatedDictSearch,
+                        customMem);
+
+    if (!cdict || ZSTD_isError( ZSTD_initCDict_internal(cdict,
+                                    dict, dictSize,
+                                    dictLoadMethod, dictContentType,
+                                    cctxParams) )) {
+        ZSTD_freeCDict(cdict);
+        return NULL;
+    }
+
+    return cdict;
+}
+
+ZSTD_CDict* ZSTD_createCDict(const void* dict, size_t dictSize, int compressionLevel)
+{
+    ZSTD_compressionParameters cParams = ZSTD_getCParams_internal(compressionLevel, ZSTD_CONTENTSIZE_UNKNOWN, dictSize, ZSTD_cpm_createCDict);
+    ZSTD_CDict* const cdict = ZSTD_createCDict_advanced(dict, dictSize,
+                                                  ZSTD_dlm_byCopy, ZSTD_dct_auto,
+                                                  cParams, ZSTD_defaultCMem);
+    if (cdict)
+        cdict->compressionLevel = (compressionLevel == 0) ? ZSTD_CLEVEL_DEFAULT : compressionLevel;
+    return cdict;
+}
+
+ZSTD_CDict* ZSTD_createCDict_byReference(const void* dict, size_t dictSize, int compressionLevel)
+{
+    ZSTD_compressionParameters cParams = ZSTD_getCParams_internal(compressionLevel, ZSTD_CONTENTSIZE_UNKNOWN, dictSize, ZSTD_cpm_createCDict);
+    ZSTD_CDict* const cdict = ZSTD_createCDict_advanced(dict, dictSize,
+                                     ZSTD_dlm_byRef, ZSTD_dct_auto,
+                                     cParams, ZSTD_defaultCMem);
+    if (cdict)
+        cdict->compressionLevel = (compressionLevel == 0) ? ZSTD_CLEVEL_DEFAULT : compressionLevel;
+    return cdict;
+}
+
+size_t ZSTD_freeCDict(ZSTD_CDict* cdict)
+{
+    if (cdict==NULL) return 0;   /* support free on NULL */
+    {   ZSTD_customMem const cMem = cdict->customMem;
+        int cdictInWorkspace = ZSTD_cwksp_owns_buffer(&cdict->workspace, cdict);
+        ZSTD_cwksp_free(&cdict->workspace, cMem);
+        if (!cdictInWorkspace) {
+            ZSTD_customFree(cdict, cMem);
+        }
+        return 0;
+    }
+}
+
+/*! ZSTD_initStaticCDict_advanced() :
+ *  Generate a digested dictionary in provided memory area.
+ *  workspace: The memory area to emplace the dictionary into.
+ *             Provided pointer must 8-bytes aligned.
+ *             It must outlive dictionary usage.
+ *  workspaceSize: Use ZSTD_estimateCDictSize()
+ *                 to determine how large workspace must be.
+ *  cParams : use ZSTD_getCParams() to transform a compression level
+ *            into its relevant cParams.
+ * @return : pointer to ZSTD_CDict*, or NULL if error (size too small)
+ *  Note : there is no corresponding "free" function.
+ *         Since workspace was allocated externally, it must be freed externally.
+ */
+const ZSTD_CDict* ZSTD_initStaticCDict(
+                                 void* workspace, size_t workspaceSize,
+                           const void* dict, size_t dictSize,
+                                 ZSTD_dictLoadMethod_e dictLoadMethod,
+                                 ZSTD_dictContentType_e dictContentType,
+                                 ZSTD_compressionParameters cParams)
+{
+    ZSTD_ParamSwitch_e const useRowMatchFinder = ZSTD_resolveRowMatchFinderMode(ZSTD_ps_auto, &cParams);
+    /* enableDedicatedDictSearch == 1 ensures matchstate is not too small in case this CDict will be used for DDS + row hash */
+    size_t const matchStateSize = ZSTD_sizeof_matchState(&cParams, useRowMatchFinder, /* enableDedicatedDictSearch */ 1, /* forCCtx */ 0);
+    size_t const neededSize = ZSTD_cwksp_alloc_size(sizeof(ZSTD_CDict))
+                            + (dictLoadMethod == ZSTD_dlm_byRef ? 0
+                               : ZSTD_cwksp_alloc_size(ZSTD_cwksp_align(dictSize, sizeof(void*))))
+                            + ZSTD_cwksp_alloc_size(HUF_WORKSPACE_SIZE)
+                            + matchStateSize;
+    ZSTD_CDict* cdict;
+    ZSTD_CCtx_params params;
+
+    DEBUGLOG(4, "ZSTD_initStaticCDict (dictSize==%u)", (unsigned)dictSize);
+    if ((size_t)workspace & 7) return NULL;  /* 8-aligned */
+
+    {
+        ZSTD_cwksp ws;
+        ZSTD_cwksp_init(&ws, workspace, workspaceSize, ZSTD_cwksp_static_alloc);
+        cdict = (ZSTD_CDict*)ZSTD_cwksp_reserve_object(&ws, sizeof(ZSTD_CDict));
+        if (cdict == NULL) return NULL;
+        ZSTD_cwksp_move(&cdict->workspace, &ws);
+    }
+
+    if (workspaceSize < neededSize) return NULL;
+
+    ZSTD_CCtxParams_init(&params, 0);
+    params.cParams = cParams;
+    params.useRowMatchFinder = useRowMatchFinder;
+    cdict->useRowMatchFinder = useRowMatchFinder;
+    cdict->compressionLevel = ZSTD_NO_CLEVEL;
+
+    if (ZSTD_isError( ZSTD_initCDict_internal(cdict,
+                                              dict, dictSize,
+                                              dictLoadMethod, dictContentType,
+                                              params) ))
+        return NULL;
+
+    return cdict;
+}
+
+ZSTD_compressionParameters ZSTD_getCParamsFromCDict(const ZSTD_CDict* cdict)
+{
+    assert(cdict != NULL);
+    return cdict->matchState.cParams;
+}
+
+/*! ZSTD_getDictID_fromCDict() :
+ *  Provides the dictID of the dictionary loaded into `cdict`.
+ *  If @return == 0, the dictionary is not conformant to Zstandard specification, or empty.
+ *  Non-conformant dictionaries can still be loaded, but as content-only dictionaries. */
+unsigned ZSTD_getDictID_fromCDict(const ZSTD_CDict* cdict)
+{
+    if (cdict==NULL) return 0;
+    return cdict->dictID;
+}
+
+/* ZSTD_compressBegin_usingCDict_internal() :
+ * Implementation of various ZSTD_compressBegin_usingCDict* functions.
+ */
+static size_t ZSTD_compressBegin_usingCDict_internal(
+    ZSTD_CCtx* const cctx, const ZSTD_CDict* const cdict,
+    ZSTD_frameParameters const fParams, unsigned long long const pledgedSrcSize)
+{
+    ZSTD_CCtx_params cctxParams;
+    DEBUGLOG(4, "ZSTD_compressBegin_usingCDict_internal");
+    RETURN_ERROR_IF(cdict==NULL, dictionary_wrong, "NULL pointer!");
+    /* Initialize the cctxParams from the cdict */
+    {
+        ZSTD_parameters params;
+        params.fParams = fParams;
+        params.cParams = ( pledgedSrcSize < ZSTD_USE_CDICT_PARAMS_SRCSIZE_CUTOFF
+                        || pledgedSrcSize < cdict->dictContentSize * ZSTD_USE_CDICT_PARAMS_DICTSIZE_MULTIPLIER
+                        || pledgedSrcSize == ZSTD_CONTENTSIZE_UNKNOWN
+                        || cdict->compressionLevel == 0 ) ?
+                ZSTD_getCParamsFromCDict(cdict)
+              : ZSTD_getCParams(cdict->compressionLevel,
+                                pledgedSrcSize,
+                                cdict->dictContentSize);
+        ZSTD_CCtxParams_init_internal(&cctxParams, &params, cdict->compressionLevel);
+    }
+    /* Increase window log to fit the entire dictionary and source if the
+     * source size is known. Limit the increase to 19, which is the
+     * window log for compression level 1 with the largest source size.
+     */
+    if (pledgedSrcSize != ZSTD_CONTENTSIZE_UNKNOWN) {
+        U32 const limitedSrcSize = (U32)MIN(pledgedSrcSize, 1U << 19);
+        U32 const limitedSrcLog = limitedSrcSize > 1 ? ZSTD_highbit32(limitedSrcSize - 1) + 1 : 1;
+        cctxParams.cParams.windowLog = MAX(cctxParams.cParams.windowLog, limitedSrcLog);
+    }
+    return ZSTD_compressBegin_internal(cctx,
+                                        NULL, 0, ZSTD_dct_auto, ZSTD_dtlm_fast,
+                                        cdict,
+                                        &cctxParams, pledgedSrcSize,
+                                        ZSTDb_not_buffered);
+}
+
+
+/* ZSTD_compressBegin_usingCDict_advanced() :
+ * This function is DEPRECATED.
+ * cdict must be != NULL */
+size_t ZSTD_compressBegin_usingCDict_advanced(
+    ZSTD_CCtx* const cctx, const ZSTD_CDict* const cdict,
+    ZSTD_frameParameters const fParams, unsigned long long const pledgedSrcSize)
+{
+    return ZSTD_compressBegin_usingCDict_internal(cctx, cdict, fParams, pledgedSrcSize);
+}
+
+/* ZSTD_compressBegin_usingCDict() :
+ * cdict must be != NULL */
+size_t ZSTD_compressBegin_usingCDict_deprecated(ZSTD_CCtx* cctx, const ZSTD_CDict* cdict)
+{
+    ZSTD_frameParameters const fParams = { 0 /*content*/, 0 /*checksum*/, 0 /*noDictID*/ };
+    return ZSTD_compressBegin_usingCDict_internal(cctx, cdict, fParams, ZSTD_CONTENTSIZE_UNKNOWN);
+}
+
+size_t ZSTD_compressBegin_usingCDict(ZSTD_CCtx* cctx, const ZSTD_CDict* cdict)
+{
+    return ZSTD_compressBegin_usingCDict_deprecated(cctx, cdict);
+}
+
+/*! ZSTD_compress_usingCDict_internal():
+ * Implementation of various ZSTD_compress_usingCDict* functions.
+ */
+static size_t ZSTD_compress_usingCDict_internal(ZSTD_CCtx* cctx,
+                                void* dst, size_t dstCapacity,
+                                const void* src, size_t srcSize,
+                                const ZSTD_CDict* cdict, ZSTD_frameParameters fParams)
+{
+    FORWARD_IF_ERROR(ZSTD_compressBegin_usingCDict_internal(cctx, cdict, fParams, srcSize), ""); /* will check if cdict != NULL */
+    return ZSTD_compressEnd_public(cctx, dst, dstCapacity, src, srcSize);
+}
+
+/*! ZSTD_compress_usingCDict_advanced():
+ * This function is DEPRECATED.
+ */
+size_t ZSTD_compress_usingCDict_advanced(ZSTD_CCtx* cctx,
+                                void* dst, size_t dstCapacity,
+                                const void* src, size_t srcSize,
+                                const ZSTD_CDict* cdict, ZSTD_frameParameters fParams)
+{
+    return ZSTD_compress_usingCDict_internal(cctx, dst, dstCapacity, src, srcSize, cdict, fParams);
+}
+
+/*! ZSTD_compress_usingCDict() :
+ *  Compression using a digested Dictionary.
+ *  Faster startup than ZSTD_compress_usingDict(), recommended when same dictionary is used multiple times.
+ *  Note that compression parameters are decided at CDict creation time
+ *  while frame parameters are hardcoded */
+size_t ZSTD_compress_usingCDict(ZSTD_CCtx* cctx,
+                                void* dst, size_t dstCapacity,
+                                const void* src, size_t srcSize,
+                                const ZSTD_CDict* cdict)
+{
+    ZSTD_frameParameters const fParams = { 1 /*content*/, 0 /*checksum*/, 0 /*noDictID*/ };
+    return ZSTD_compress_usingCDict_internal(cctx, dst, dstCapacity, src, srcSize, cdict, fParams);
+}
+
+/*======   Compression   ======*/
+
+/* ZSTD_validateSequence() :
+ * @offBase : must use the format required by ZSTD_storeSeq()
+ * @returns a ZSTD error code if sequence is not valid
+ */
+static size_t
+ZSTD_validateSequence(U32 offBase, U32 matchLength, U32 minMatch,
+                      size_t posInSrc, U32 windowLog, size_t dictSize, int useSequenceProducer)
+{
+    U32 const windowSize = 1u << windowLog;
+    /* posInSrc represents the amount of data the decoder would decode up to this point.
+     * As long as the amount of data decoded is less than or equal to window size, offsets may be
+     * larger than the total length of output decoded in order to reference the dict, even larger than
+     * window size. After output surpasses windowSize, we're limited to windowSize offsets again.
+     */
+    size_t const offsetBound = posInSrc > windowSize ? (size_t)windowSize : posInSrc + (size_t)dictSize;
+    size_t const matchLenLowerBound = (minMatch == 3 || useSequenceProducer) ? 3 : 4;
+    RETURN_ERROR_IF(offBase > OFFSET_TO_OFFBASE(offsetBound), externalSequences_invalid, "Offset too large!");
+    /* Validate maxNbSeq is large enough for the given matchLength and minMatch */
+    RETURN_ERROR_IF(matchLength < matchLenLowerBound, externalSequences_invalid, "Matchlength too small for the minMatch");
+    return 0;
+}
+
+/* Returns an offset code, given a sequence's raw offset, the ongoing repcode array, and whether litLength == 0 */
+static U32 ZSTD_finalizeOffBase(U32 rawOffset, const U32 rep[ZSTD_REP_NUM], U32 ll0)
+{
+    U32 offBase = OFFSET_TO_OFFBASE(rawOffset);
+
+    if (!ll0 && rawOffset == rep[0]) {
+        offBase = REPCODE1_TO_OFFBASE;
+    } else if (rawOffset == rep[1]) {
+        offBase = REPCODE_TO_OFFBASE(2 - ll0);
+    } else if (rawOffset == rep[2]) {
+        offBase = REPCODE_TO_OFFBASE(3 - ll0);
+    } else if (ll0 && rawOffset == rep[0] - 1) {
+        offBase = REPCODE3_TO_OFFBASE;
+    }
+    return offBase;
+}
+
+/* This function scans through an array of ZSTD_Sequence,
+ * storing the sequences it reads, until it reaches a block delimiter.
+ * Note that the block delimiter includes the last literals of the block.
+ * @blockSize must be == sum(sequence_lengths).
+ * @returns @blockSize on success, and a ZSTD_error otherwise.
+ */
+static size_t
+ZSTD_transferSequences_wBlockDelim(ZSTD_CCtx* cctx,
+                                   ZSTD_SequencePosition* seqPos,
+                             const ZSTD_Sequence* const inSeqs, size_t inSeqsSize,
+                             const void* src, size_t blockSize,
+                                   ZSTD_ParamSwitch_e externalRepSearch)
+{
+    U32 idx = seqPos->idx;
+    U32 const startIdx = idx;
+    BYTE const* ip = (BYTE const*)(src);
+    const BYTE* const iend = ip + blockSize;
+    Repcodes_t updatedRepcodes;
+    U32 dictSize;
+
+    DEBUGLOG(5, "ZSTD_transferSequences_wBlockDelim (blockSize = %zu)", blockSize);
+
+    if (cctx->cdict) {
+        dictSize = (U32)cctx->cdict->dictContentSize;
+    } else if (cctx->prefixDict.dict) {
+        dictSize = (U32)cctx->prefixDict.dictSize;
+    } else {
+        dictSize = 0;
+    }
+    ZSTD_memcpy(updatedRepcodes.rep, cctx->blockState.prevCBlock->rep, sizeof(Repcodes_t));
+    for (; idx < inSeqsSize && (inSeqs[idx].matchLength != 0 || inSeqs[idx].offset != 0); ++idx) {
+        U32 const litLength = inSeqs[idx].litLength;
+        U32 const matchLength = inSeqs[idx].matchLength;
+        U32 offBase;
+
+        if (externalRepSearch == ZSTD_ps_disable) {
+            offBase = OFFSET_TO_OFFBASE(inSeqs[idx].offset);
+        } else {
+            U32 const ll0 = (litLength == 0);
+            offBase = ZSTD_finalizeOffBase(inSeqs[idx].offset, updatedRepcodes.rep, ll0);
+            ZSTD_updateRep(updatedRepcodes.rep, offBase, ll0);
+        }
+
+        DEBUGLOG(6, "Storing sequence: (of: %u, ml: %u, ll: %u)", offBase, matchLength, litLength);
+        if (cctx->appliedParams.validateSequences) {
+            seqPos->posInSrc += litLength + matchLength;
+            FORWARD_IF_ERROR(ZSTD_validateSequence(offBase, matchLength, cctx->appliedParams.cParams.minMatch,
+                                                seqPos->posInSrc,
+                                                cctx->appliedParams.cParams.windowLog, dictSize,
+                                                ZSTD_hasExtSeqProd(&cctx->appliedParams)),
+                                                "Sequence validation failed");
+        }
+        RETURN_ERROR_IF(idx - seqPos->idx >= cctx->seqStore.maxNbSeq, externalSequences_invalid,
+                        "Not enough memory allocated. Try adjusting ZSTD_c_minMatch.");
+        ZSTD_storeSeq(&cctx->seqStore, litLength, ip, iend, offBase, matchLength);
+        ip += matchLength + litLength;
+    }
+    RETURN_ERROR_IF(idx == inSeqsSize, externalSequences_invalid, "Block delimiter not found.");
+
+    /* If we skipped repcode search while parsing, we need to update repcodes now */
+    assert(externalRepSearch != ZSTD_ps_auto);
+    assert(idx >= startIdx);
+    if (externalRepSearch == ZSTD_ps_disable && idx != startIdx) {
+        U32* const rep = updatedRepcodes.rep;
+        U32 lastSeqIdx = idx - 1; /* index of last non-block-delimiter sequence */
+
+        if (lastSeqIdx >= startIdx + 2) {
+            rep[2] = inSeqs[lastSeqIdx - 2].offset;
+            rep[1] = inSeqs[lastSeqIdx - 1].offset;
+            rep[0] = inSeqs[lastSeqIdx].offset;
+        } else if (lastSeqIdx == startIdx + 1) {
+            rep[2] = rep[0];
+            rep[1] = inSeqs[lastSeqIdx - 1].offset;
+            rep[0] = inSeqs[lastSeqIdx].offset;
+        } else {
+            assert(lastSeqIdx == startIdx);
+            rep[2] = rep[1];
+            rep[1] = rep[0];
+            rep[0] = inSeqs[lastSeqIdx].offset;
+        }
+    }
+
+    ZSTD_memcpy(cctx->blockState.nextCBlock->rep, updatedRepcodes.rep, sizeof(Repcodes_t));
+
+    if (inSeqs[idx].litLength) {
+        DEBUGLOG(6, "Storing last literals of size: %u", inSeqs[idx].litLength);
+        ZSTD_storeLastLiterals(&cctx->seqStore, ip, inSeqs[idx].litLength);
+        ip += inSeqs[idx].litLength;
+        seqPos->posInSrc += inSeqs[idx].litLength;
+    }
+    RETURN_ERROR_IF(ip != iend, externalSequences_invalid, "Blocksize doesn't agree with block delimiter!");
+    seqPos->idx = idx+1;
+    return blockSize;
+}
+
+/*-=====  Pre-defined compression levels  =====-*/
+#include "clevels.h"
+
+int ZSTD_maxCLevel(void) { return ZSTD_MAX_CLEVEL; }
+int ZSTD_minCLevel(void) { return (int)-ZSTD_TARGETLENGTH_MAX; }
+int ZSTD_defaultCLevel(void) { return ZSTD_CLEVEL_DEFAULT; }
+
+static ZSTD_compressionParameters ZSTD_dedicatedDictSearch_getCParams(int const compressionLevel, size_t const dictSize)
+{
+    ZSTD_compressionParameters cParams = ZSTD_getCParams_internal(compressionLevel, 0, dictSize, ZSTD_cpm_createCDict);
+    switch (cParams.strategy) {
+        case ZSTD_fast:
+        case ZSTD_dfast:
+            break;
+        case ZSTD_greedy:
+        case ZSTD_lazy:
+        case ZSTD_lazy2:
+            cParams.hashLog += ZSTD_LAZY_DDSS_BUCKET_LOG;
+            break;
+        case ZSTD_btlazy2:
+        case ZSTD_btopt:
+        case ZSTD_btultra:
+        case ZSTD_btultra2:
+            break;
+    }
+    return cParams;
+}
+
+static int ZSTD_dedicatedDictSearch_isSupported(
+        ZSTD_compressionParameters const* cParams)
+{
+    return (cParams->strategy >= ZSTD_greedy)
+        && (cParams->strategy <= ZSTD_lazy2)
+        && (cParams->hashLog > cParams->chainLog)
+        && (cParams->chainLog <= 24);
+}
+
+/**
+ * Reverses the adjustment applied to cparams when enabling dedicated dict
+ * search. This is used to recover the params set to be used in the working
+ * context. (Otherwise, those tables would also grow.)
+ */
+static void ZSTD_dedicatedDictSearch_revertCParams(
+        ZSTD_compressionParameters* cParams) {
+    switch (cParams->strategy) {
+        case ZSTD_fast:
+        case ZSTD_dfast:
+            break;
+        case ZSTD_greedy:
+        case ZSTD_lazy:
+        case ZSTD_lazy2:
+            cParams->hashLog -= ZSTD_LAZY_DDSS_BUCKET_LOG;
+            if (cParams->hashLog < ZSTD_HASHLOG_MIN) {
+                cParams->hashLog = ZSTD_HASHLOG_MIN;
+            }
+            break;
+        case ZSTD_btlazy2:
+        case ZSTD_btopt:
+        case ZSTD_btultra:
+        case ZSTD_btultra2:
+            break;
+    }
+}
+
+static U64 ZSTD_getCParamRowSize(U64 srcSizeHint, size_t dictSize, ZSTD_CParamMode_e mode)
+{
+    switch (mode) {
+    case ZSTD_cpm_unknown:
+    case ZSTD_cpm_noAttachDict:
+    case ZSTD_cpm_createCDict:
+        break;
+    case ZSTD_cpm_attachDict:
+        dictSize = 0;
+        break;
+    default:
+        assert(0);
+        break;
+    }
+    {   int const unknown = srcSizeHint == ZSTD_CONTENTSIZE_UNKNOWN;
+        size_t const addedSize = unknown && dictSize > 0 ? 500 : 0;
+        return unknown && dictSize == 0 ? ZSTD_CONTENTSIZE_UNKNOWN : srcSizeHint+dictSize+addedSize;
+    }
+}
+
+/*! ZSTD_getCParams_internal() :
+ * @return ZSTD_compressionParameters structure for a selected compression level, srcSize and dictSize.
+ *  Note: srcSizeHint 0 means 0, use ZSTD_CONTENTSIZE_UNKNOWN for unknown.
+ *        Use dictSize == 0 for unknown or unused.
+ *  Note: `mode` controls how we treat the `dictSize`. See docs for `ZSTD_CParamMode_e`. */
+static ZSTD_compressionParameters ZSTD_getCParams_internal(int compressionLevel, unsigned long long srcSizeHint, size_t dictSize, ZSTD_CParamMode_e mode)
+{
+    U64 const rSize = ZSTD_getCParamRowSize(srcSizeHint, dictSize, mode);
+    U32 const tableID = (rSize <= 256 KB) + (rSize <= 128 KB) + (rSize <= 16 KB);
+    int row;
+    DEBUGLOG(5, "ZSTD_getCParams_internal (cLevel=%i)", compressionLevel);
+
+    /* row */
+    if (compressionLevel == 0) row = ZSTD_CLEVEL_DEFAULT;   /* 0 == default */
+    else if (compressionLevel < 0) row = 0;   /* entry 0 is baseline for fast mode */
+    else if (compressionLevel > ZSTD_MAX_CLEVEL) row = ZSTD_MAX_CLEVEL;
+    else row = compressionLevel;
+
+    {   ZSTD_compressionParameters cp = ZSTD_defaultCParameters[tableID][row];
+        DEBUGLOG(5, "ZSTD_getCParams_internal selected tableID: %u row: %u strat: %u", tableID, row, (U32)cp.strategy);
+        /* acceleration factor */
+        if (compressionLevel < 0) {
+            int const clampedCompressionLevel = MAX(ZSTD_minCLevel(), compressionLevel);
+            cp.targetLength = (unsigned)(-clampedCompressionLevel);
+        }
+        /* refine parameters based on srcSize & dictSize */
+        return ZSTD_adjustCParams_internal(cp, srcSizeHint, dictSize, mode, ZSTD_ps_auto);
+    }
+}
+
+/*! ZSTD_getCParams() :
+ * @return ZSTD_compressionParameters structure for a selected compression level, srcSize and dictSize.
+ *  Size values are optional, provide 0 if not known or unused */
+ZSTD_compressionParameters ZSTD_getCParams(int compressionLevel, unsigned long long srcSizeHint, size_t dictSize)
+{
+    if (srcSizeHint == 0) srcSizeHint = ZSTD_CONTENTSIZE_UNKNOWN;
+    return ZSTD_getCParams_internal(compressionLevel, srcSizeHint, dictSize, ZSTD_cpm_unknown);
+}
+
+/*! ZSTD_getParams() :
+ *  same idea as ZSTD_getCParams()
+ * @return a `ZSTD_parameters` structure (instead of `ZSTD_compressionParameters`).
+ *  Fields of `ZSTD_frameParameters` are set to default values */
+static ZSTD_parameters
+ZSTD_getParams_internal(int compressionLevel, unsigned long long srcSizeHint, size_t dictSize, ZSTD_CParamMode_e mode)
+{
+    ZSTD_parameters params;
+    ZSTD_compressionParameters const cParams = ZSTD_getCParams_internal(compressionLevel, srcSizeHint, dictSize, mode);
+    DEBUGLOG(5, "ZSTD_getParams (cLevel=%i)", compressionLevel);
+    ZSTD_memset(&params, 0, sizeof(params));
+    params.cParams = cParams;
+    params.fParams.contentSizeFlag = 1;
+    return params;
+}
+
+/*! ZSTD_getParams() :
+ *  same idea as ZSTD_getCParams()
+ * @return a `ZSTD_parameters` structure (instead of `ZSTD_compressionParameters`).
+ *  Fields of `ZSTD_frameParameters` are set to default values */
+ZSTD_parameters ZSTD_getParams(int compressionLevel, unsigned long long srcSizeHint, size_t dictSize)
+{
+    if (srcSizeHint == 0) srcSizeHint = ZSTD_CONTENTSIZE_UNKNOWN;
+    return ZSTD_getParams_internal(compressionLevel, srcSizeHint, dictSize, ZSTD_cpm_unknown);
+}
+
+void ZSTD_registerSequenceProducer(
+    ZSTD_CCtx* zc,
+    void* extSeqProdState,
+    ZSTD_sequenceProducer_F extSeqProdFunc)
+{
+    assert(zc != NULL);
+    ZSTD_CCtxParams_registerSequenceProducer(
+        &zc->requestedParams, extSeqProdState, extSeqProdFunc
+    );
+}
+
+void ZSTD_CCtxParams_registerSequenceProducer(
+  ZSTD_CCtx_params* params,
+  void* extSeqProdState,
+  ZSTD_sequenceProducer_F extSeqProdFunc)
+{
+    assert(params != NULL);
+    if (extSeqProdFunc != NULL) {
+        params->extSeqProdFunc = extSeqProdFunc;
+        params->extSeqProdState = extSeqProdState;
+    } else {
+        params->extSeqProdFunc = NULL;
+        params->extSeqProdState = NULL;
+    }
+}
diff --git a/src/commonlib/bsd/zstd/compress/zstd_compress_internal.h b/src/commonlib/bsd/zstd/compress/zstd_compress_internal.h
new file mode 100644
index 0000000000..1d26c60867
--- /dev/null
+++ b/src/commonlib/bsd/zstd/compress/zstd_compress_internal.h
@@ -0,0 +1,1625 @@
+/* SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0-only */
+
+/*
+ * Copyright (c) Meta Platforms, Inc. and affiliates.
+ * All rights reserved.
+ *
+ * This source code is licensed under both the BSD-style license (found in the
+ * LICENSE file in the root directory of this source tree) and the GPLv2 (found
+ * in the COPYING file in the root directory of this source tree).
+ * You may select, at your option, one of the above-listed licenses.
+ */
+
+/* This header contains definitions
+ * that shall **only** be used by modules within lib/compress.
+ */
+
+#ifndef ZSTD_COMPRESS_H
+#define ZSTD_COMPRESS_H
+
+/*-*************************************
+*  Dependencies
+***************************************/
+#include "../common/zstd_internal.h"
+#include "zstd_cwksp.h"
+#include "../common/zstd_bits.h" /* ZSTD_highbit32, ZSTD_NbCommonBytes */
+#include "zstd_preSplit.h" /* ZSTD_SLIPBLOCK_WORKSPACESIZE */
+
+/*-*************************************
+*  Constants
+***************************************/
+#define kSearchStrength      8
+#define HASH_READ_SIZE       8
+#define ZSTD_DUBT_UNSORTED_MARK 1   /* For btlazy2 strategy, index ZSTD_DUBT_UNSORTED_MARK==1 means "unsorted".
+                                       It could be confused for a real successor at index "1", if sorted as larger than its predecessor.
+                                       It's not a big deal though : candidate will just be sorted again.
+                                       Additionally, candidate position 1 will be lost.
+                                       But candidate 1 cannot hide a large tree of candidates, so it's a minimal loss.
+                                       The benefit is that ZSTD_DUBT_UNSORTED_MARK cannot be mishandled after table reuse with a different strategy.
+                                       This constant is required by ZSTD_compressBlock_btlazy2() and ZSTD_reduceTable_internal() */
+
+
+/*-*************************************
+*  Context memory management
+***************************************/
+typedef enum { ZSTDcs_created=0, ZSTDcs_init, ZSTDcs_ongoing, ZSTDcs_ending } ZSTD_compressionStage_e;
+typedef enum { zcss_init=0, zcss_load, zcss_flush } ZSTD_cStreamStage;
+
+typedef struct ZSTD_prefixDict_s {
+    const void* dict;
+    size_t dictSize;
+    ZSTD_dictContentType_e dictContentType;
+} ZSTD_prefixDict;
+
+typedef struct {
+    void* dictBuffer;
+    void const* dict;
+    size_t dictSize;
+    ZSTD_dictContentType_e dictContentType;
+    ZSTD_CDict* cdict;
+} ZSTD_localDict;
+
+typedef struct {
+    HUF_CElt CTable[HUF_CTABLE_SIZE_ST(255)];
+    HUF_repeat repeatMode;
+} ZSTD_hufCTables_t;
+
+typedef struct {
+    FSE_CTable offcodeCTable[FSE_CTABLE_SIZE_U32(OffFSELog, MaxOff)];
+    FSE_CTable matchlengthCTable[FSE_CTABLE_SIZE_U32(MLFSELog, MaxML)];
+    FSE_CTable litlengthCTable[FSE_CTABLE_SIZE_U32(LLFSELog, MaxLL)];
+    FSE_repeat offcode_repeatMode;
+    FSE_repeat matchlength_repeatMode;
+    FSE_repeat litlength_repeatMode;
+} ZSTD_fseCTables_t;
+
+typedef struct {
+    ZSTD_hufCTables_t huf;
+    ZSTD_fseCTables_t fse;
+} ZSTD_entropyCTables_t;
+
+/***********************************************
+*  Sequences *
+***********************************************/
+typedef struct SeqDef_s {
+    U32 offBase;   /* offBase == Offset + ZSTD_REP_NUM, or repcode 1,2,3 */
+    U16 litLength;
+    U16 mlBase;    /* mlBase == matchLength - MINMATCH */
+} SeqDef;
+
+/* Controls whether seqStore has a single "long" litLength or matchLength. See SeqStore_t. */
+typedef enum {
+    ZSTD_llt_none = 0,             /* no longLengthType */
+    ZSTD_llt_literalLength = 1,    /* represents a long literal */
+    ZSTD_llt_matchLength = 2       /* represents a long match */
+} ZSTD_longLengthType_e;
+
+typedef struct {
+    SeqDef* sequencesStart;
+    SeqDef* sequences;      /* ptr to end of sequences */
+    BYTE*  litStart;
+    BYTE*  lit;             /* ptr to end of literals */
+    BYTE*  llCode;
+    BYTE*  mlCode;
+    BYTE*  ofCode;
+    size_t maxNbSeq;
+    size_t maxNbLit;
+
+    /* longLengthPos and longLengthType to allow us to represent either a single litLength or matchLength
+     * in the seqStore that has a value larger than U16 (if it exists). To do so, we increment
+     * the existing value of the litLength or matchLength by 0x10000.
+     */
+    ZSTD_longLengthType_e longLengthType;
+    U32                   longLengthPos;  /* Index of the sequence to apply long length modification to */
+} SeqStore_t;
+
+typedef struct {
+    U32 litLength;
+    U32 matchLength;
+} ZSTD_SequenceLength;
+
+/**
+ * Returns the ZSTD_SequenceLength for the given sequences. It handles the decoding of long sequences
+ * indicated by longLengthPos and longLengthType, and adds MINMATCH back to matchLength.
+ */
+MEM_STATIC ZSTD_SequenceLength ZSTD_getSequenceLength(SeqStore_t const* seqStore, SeqDef const* seq)
+{
+    ZSTD_SequenceLength seqLen;
+    seqLen.litLength = seq->litLength;
+    seqLen.matchLength = seq->mlBase + MINMATCH;
+    if (seqStore->longLengthPos == (U32)(seq - seqStore->sequencesStart)) {
+        if (seqStore->longLengthType == ZSTD_llt_literalLength) {
+            seqLen.litLength += 0x10000;
+        }
+        if (seqStore->longLengthType == ZSTD_llt_matchLength) {
+            seqLen.matchLength += 0x10000;
+        }
+    }
+    return seqLen;
+}
+
+const SeqStore_t* ZSTD_getSeqStore(const ZSTD_CCtx* ctx);   /* compress & dictBuilder */
+int ZSTD_seqToCodes(const SeqStore_t* seqStorePtr);   /* compress, dictBuilder, decodeCorpus (shouldn't get its definition from here) */
+
+
+/***********************************************
+*  Entropy buffer statistics structs and funcs *
+***********************************************/
+/** ZSTD_hufCTablesMetadata_t :
+ *  Stores Literals Block Type for a super-block in hType, and
+ *  huffman tree description in hufDesBuffer.
+ *  hufDesSize refers to the size of huffman tree description in bytes.
+ *  This metadata is populated in ZSTD_buildBlockEntropyStats_literals() */
+typedef struct {
+    SymbolEncodingType_e hType;
+    BYTE hufDesBuffer[ZSTD_MAX_HUF_HEADER_SIZE];
+    size_t hufDesSize;
+} ZSTD_hufCTablesMetadata_t;
+
+/** ZSTD_fseCTablesMetadata_t :
+ *  Stores symbol compression modes for a super-block in {ll, ol, ml}Type, and
+ *  fse tables in fseTablesBuffer.
+ *  fseTablesSize refers to the size of fse tables in bytes.
+ *  This metadata is populated in ZSTD_buildBlockEntropyStats_sequences() */
+typedef struct {
+    SymbolEncodingType_e llType;
+    SymbolEncodingType_e ofType;
+    SymbolEncodingType_e mlType;
+    BYTE fseTablesBuffer[ZSTD_MAX_FSE_HEADERS_SIZE];
+    size_t fseTablesSize;
+    size_t lastCountSize; /* This is to account for bug in 1.3.4. More detail in ZSTD_entropyCompressSeqStore_internal() */
+} ZSTD_fseCTablesMetadata_t;
+
+typedef struct {
+    ZSTD_hufCTablesMetadata_t hufMetadata;
+    ZSTD_fseCTablesMetadata_t fseMetadata;
+} ZSTD_entropyCTablesMetadata_t;
+
+/** ZSTD_buildBlockEntropyStats() :
+ *  Builds entropy for the block.
+ *  @return : 0 on success or error code */
+size_t ZSTD_buildBlockEntropyStats(
+                    const SeqStore_t* seqStorePtr,
+                    const ZSTD_entropyCTables_t* prevEntropy,
+                          ZSTD_entropyCTables_t* nextEntropy,
+                    const ZSTD_CCtx_params* cctxParams,
+                          ZSTD_entropyCTablesMetadata_t* entropyMetadata,
+                          void* workspace, size_t wkspSize);
+
+/*********************************
+*  Compression internals structs *
+*********************************/
+
+typedef struct {
+    U32 off;            /* Offset sumtype code for the match, using ZSTD_storeSeq() format */
+    U32 len;            /* Raw length of match */
+} ZSTD_match_t;
+
+typedef struct {
+    U32 offset;         /* Offset of sequence */
+    U32 litLength;      /* Length of literals prior to match */
+    U32 matchLength;    /* Raw length of match */
+} rawSeq;
+
+typedef struct {
+  rawSeq* seq;          /* The start of the sequences */
+  size_t pos;           /* The index in seq where reading stopped. pos <= size. */
+  size_t posInSequence; /* The position within the sequence at seq[pos] where reading
+                           stopped. posInSequence <= seq[pos].litLength + seq[pos].matchLength */
+  size_t size;          /* The number of sequences. <= capacity. */
+  size_t capacity;      /* The capacity starting from `seq` pointer */
+} RawSeqStore_t;
+
+UNUSED_ATTR static const RawSeqStore_t kNullRawSeqStore = {NULL, 0, 0, 0, 0};
+
+typedef struct {
+    int price;  /* price from beginning of segment to this position */
+    U32 off;    /* offset of previous match */
+    U32 mlen;   /* length of previous match */
+    U32 litlen; /* nb of literals since previous match */
+    U32 rep[ZSTD_REP_NUM];  /* offset history after previous match */
+} ZSTD_optimal_t;
+
+typedef enum { zop_dynamic=0, zop_predef } ZSTD_OptPrice_e;
+
+#define ZSTD_OPT_SIZE (ZSTD_OPT_NUM+3)
+typedef struct {
+    /* All tables are allocated inside cctx->workspace by ZSTD_resetCCtx_internal() */
+    unsigned* litFreq;           /* table of literals statistics, of size 256 */
+    unsigned* litLengthFreq;     /* table of litLength statistics, of size (MaxLL+1) */
+    unsigned* matchLengthFreq;   /* table of matchLength statistics, of size (MaxML+1) */
+    unsigned* offCodeFreq;       /* table of offCode statistics, of size (MaxOff+1) */
+    ZSTD_match_t* matchTable;    /* list of found matches, of size ZSTD_OPT_SIZE */
+    ZSTD_optimal_t* priceTable;  /* All positions tracked by optimal parser, of size ZSTD_OPT_SIZE */
+
+    U32  litSum;                 /* nb of literals */
+    U32  litLengthSum;           /* nb of litLength codes */
+    U32  matchLengthSum;         /* nb of matchLength codes */
+    U32  offCodeSum;             /* nb of offset codes */
+    U32  litSumBasePrice;        /* to compare to log2(litfreq) */
+    U32  litLengthSumBasePrice;  /* to compare to log2(llfreq)  */
+    U32  matchLengthSumBasePrice;/* to compare to log2(mlfreq)  */
+    U32  offCodeSumBasePrice;    /* to compare to log2(offreq)  */
+    ZSTD_OptPrice_e priceType;   /* prices can be determined dynamically, or follow a pre-defined cost structure */
+    const ZSTD_entropyCTables_t* symbolCosts;  /* pre-calculated dictionary statistics */
+    ZSTD_ParamSwitch_e literalCompressionMode;
+} optState_t;
+
+typedef struct {
+  ZSTD_entropyCTables_t entropy;
+  U32 rep[ZSTD_REP_NUM];
+} ZSTD_compressedBlockState_t;
+
+typedef struct {
+    BYTE const* nextSrc;       /* next block here to continue on current prefix */
+    BYTE const* base;          /* All regular indexes relative to this position */
+    BYTE const* dictBase;      /* extDict indexes relative to this position */
+    U32 dictLimit;             /* below that point, need extDict */
+    U32 lowLimit;              /* below that point, no more valid data */
+    U32 nbOverflowCorrections; /* Number of times overflow correction has run since
+                                * ZSTD_window_init(). Useful for debugging coredumps
+                                * and for ZSTD_WINDOW_OVERFLOW_CORRECT_FREQUENTLY.
+                                */
+} ZSTD_window_t;
+
+#define ZSTD_WINDOW_START_INDEX 2
+
+typedef struct ZSTD_MatchState_t ZSTD_MatchState_t;
+
+#define ZSTD_ROW_HASH_CACHE_SIZE 8       /* Size of prefetching hash cache for row-based matchfinder */
+
+struct ZSTD_MatchState_t {
+    ZSTD_window_t window;   /* State for window round buffer management */
+    U32 loadedDictEnd;      /* index of end of dictionary, within context's referential.
+                             * When loadedDictEnd != 0, a dictionary is in use, and still valid.
+                             * This relies on a mechanism to set loadedDictEnd=0 when dictionary is no longer within distance.
+                             * Such mechanism is provided within ZSTD_window_enforceMaxDist() and ZSTD_checkDictValidity().
+                             * When dict referential is copied into active context (i.e. not attached),
+                             * loadedDictEnd == dictSize, since referential starts from zero.
+                             */
+    U32 nextToUpdate;       /* index from which to continue table update */
+    U32 hashLog3;           /* dispatch table for matches of len==3 : larger == faster, more memory */
+
+    U32 rowHashLog;                          /* For row-based matchfinder: Hashlog based on nb of rows in the hashTable.*/
+    BYTE* tagTable;                          /* For row-based matchFinder: A row-based table containing the hashes and head index. */
+    U32 hashCache[ZSTD_ROW_HASH_CACHE_SIZE]; /* For row-based matchFinder: a cache of hashes to improve speed */
+    U64 hashSalt;                            /* For row-based matchFinder: salts the hash for reuse of tag table */
+    U32 hashSaltEntropy;                     /* For row-based matchFinder: collects entropy for salt generation */
+
+    U32* hashTable;
+    U32* hashTable3;
+    U32* chainTable;
+
+    int forceNonContiguous; /* Non-zero if we should force non-contiguous load for the next window update. */
+
+    int dedicatedDictSearch;  /* Indicates whether this matchState is using the
+                               * dedicated dictionary search structure.
+                               */
+    optState_t opt;         /* optimal parser state */
+    const ZSTD_MatchState_t* dictMatchState;
+    ZSTD_compressionParameters cParams;
+    const RawSeqStore_t* ldmSeqStore;
+
+    /* Controls prefetching in some dictMatchState matchfinders.
+     * This behavior is controlled from the cctx ms.
+     * This parameter has no effect in the cdict ms. */
+    int prefetchCDictTables;
+
+    /* When == 0, lazy match finders insert every position.
+     * When != 0, lazy match finders only insert positions they search.
+     * This allows them to skip much faster over incompressible data,
+     * at a small cost to compression ratio.
+     */
+    int lazySkipping;
+};
+
+typedef struct {
+    ZSTD_compressedBlockState_t* prevCBlock;
+    ZSTD_compressedBlockState_t* nextCBlock;
+    ZSTD_MatchState_t matchState;
+} ZSTD_blockState_t;
+
+typedef struct {
+    U32 offset;
+    U32 checksum;
+} ldmEntry_t;
+
+typedef struct {
+    BYTE const* split;
+    U32 hash;
+    U32 checksum;
+    ldmEntry_t* bucket;
+} ldmMatchCandidate_t;
+
+#define LDM_BATCH_SIZE 64
+
+typedef struct {
+    ZSTD_window_t window;   /* State for the window round buffer management */
+    ldmEntry_t* hashTable;
+    U32 loadedDictEnd;
+    BYTE* bucketOffsets;    /* Next position in bucket to insert entry */
+    size_t splitIndices[LDM_BATCH_SIZE];
+    ldmMatchCandidate_t matchCandidates[LDM_BATCH_SIZE];
+} ldmState_t;
+
+typedef struct {
+    ZSTD_ParamSwitch_e enableLdm; /* ZSTD_ps_enable to enable LDM. ZSTD_ps_auto by default */
+    U32 hashLog;            /* Log size of hashTable */
+    U32 bucketSizeLog;      /* Log bucket size for collision resolution, at most 8 */
+    U32 minMatchLength;     /* Minimum match length */
+    U32 hashRateLog;       /* Log number of entries to skip */
+    U32 windowLog;          /* Window log for the LDM */
+} ldmParams_t;
+
+typedef struct {
+    int collectSequences;
+    ZSTD_Sequence* seqStart;
+    size_t seqIndex;
+    size_t maxSequences;
+} SeqCollector;
+
+struct ZSTD_CCtx_params_s {
+    ZSTD_format_e format;
+    ZSTD_compressionParameters cParams;
+    ZSTD_frameParameters fParams;
+
+    int compressionLevel;
+    int forceWindow;           /* force back-references to respect limit of
+                                * 1<<wLog, even for dictionary */
+    size_t targetCBlockSize;   /* Tries to fit compressed block size to be around targetCBlockSize.
+                                * No target when targetCBlockSize == 0.
+                                * There is no guarantee on compressed block size */
+    int srcSizeHint;           /* User's best guess of source size.
+                                * Hint is not valid when srcSizeHint == 0.
+                                * There is no guarantee that hint is close to actual source size */
+
+    ZSTD_dictAttachPref_e attachDictPref;
+    ZSTD_ParamSwitch_e literalCompressionMode;
+
+    /* Multithreading: used to pass parameters to mtctx */
+    int nbWorkers;
+    size_t jobSize;
+    int overlapLog;
+    int rsyncable;
+
+    /* Long distance matching parameters */
+    ldmParams_t ldmParams;
+
+    /* Dedicated dict search algorithm trigger */
+    int enableDedicatedDictSearch;
+
+    /* Input/output buffer modes */
+    ZSTD_bufferMode_e inBufferMode;
+    ZSTD_bufferMode_e outBufferMode;
+
+    /* Sequence compression API */
+    ZSTD_SequenceFormat_e blockDelimiters;
+    int validateSequences;
+
+    /* Block splitting
+     * @postBlockSplitter executes split analysis after sequences are produced,
+     * it's more accurate but consumes more resources.
+     * @preBlockSplitter_level splits before knowing sequences,
+     * it's more approximative but also cheaper.
+     * Valid @preBlockSplitter_level values range from 0 to 6 (included).
+     * 0 means auto, 1 means do not split,
+     * then levels are sorted in increasing cpu budget, from 2 (fastest) to 6 (slowest).
+     * Highest @preBlockSplitter_level combines well with @postBlockSplitter.
+     */
+    ZSTD_ParamSwitch_e postBlockSplitter;
+    int preBlockSplitter_level;
+
+    /* Adjust the max block size*/
+    size_t maxBlockSize;
+
+    /* Param for deciding whether to use row-based matchfinder */
+    ZSTD_ParamSwitch_e useRowMatchFinder;
+
+    /* Always load a dictionary in ext-dict mode (not prefix mode)? */
+    int deterministicRefPrefix;
+
+    /* Internal use, for createCCtxParams() and freeCCtxParams() only */
+    ZSTD_customMem customMem;
+
+    /* Controls prefetching in some dictMatchState matchfinders */
+    ZSTD_ParamSwitch_e prefetchCDictTables;
+
+    /* Controls whether zstd will fall back to an internal matchfinder
+     * if the external matchfinder returns an error code. */
+    int enableMatchFinderFallback;
+
+    /* Parameters for the external sequence producer API.
+     * Users set these parameters through ZSTD_registerSequenceProducer().
+     * It is not possible to set these parameters individually through the public API. */
+    void* extSeqProdState;
+    ZSTD_sequenceProducer_F extSeqProdFunc;
+
+    /* Controls repcode search in external sequence parsing */
+    ZSTD_ParamSwitch_e searchForExternalRepcodes;
+};  /* typedef'd to ZSTD_CCtx_params within "zstd.h" */
+
+#define COMPRESS_SEQUENCES_WORKSPACE_SIZE (sizeof(unsigned) * (MaxSeq + 2))
+#define ENTROPY_WORKSPACE_SIZE (HUF_WORKSPACE_SIZE + COMPRESS_SEQUENCES_WORKSPACE_SIZE)
+#define TMP_WORKSPACE_SIZE (MAX(ENTROPY_WORKSPACE_SIZE, ZSTD_SLIPBLOCK_WORKSPACESIZE))
+
+/**
+ * Indicates whether this compression proceeds directly from user-provided
+ * source buffer to user-provided destination buffer (ZSTDb_not_buffered), or
+ * whether the context needs to buffer the input/output (ZSTDb_buffered).
+ */
+typedef enum {
+    ZSTDb_not_buffered,
+    ZSTDb_buffered
+} ZSTD_buffered_policy_e;
+
+/**
+ * Struct that contains all elements of block splitter that should be allocated
+ * in a wksp.
+ */
+#define ZSTD_MAX_NB_BLOCK_SPLITS 196
+typedef struct {
+    SeqStore_t fullSeqStoreChunk;
+    SeqStore_t firstHalfSeqStore;
+    SeqStore_t secondHalfSeqStore;
+    SeqStore_t currSeqStore;
+    SeqStore_t nextSeqStore;
+
+    U32 partitions[ZSTD_MAX_NB_BLOCK_SPLITS];
+    ZSTD_entropyCTablesMetadata_t entropyMetadata;
+} ZSTD_blockSplitCtx;
+
+struct ZSTD_CCtx_s {
+    ZSTD_compressionStage_e stage;
+    int cParamsChanged;                  /* == 1 if cParams(except wlog) or compression level are changed in requestedParams. Triggers transmission of new params to ZSTDMT (if available) then reset to 0. */
+    int bmi2;                            /* == 1 if the CPU supports BMI2 and 0 otherwise. CPU support is determined dynamically once per context lifetime. */
+    ZSTD_CCtx_params requestedParams;
+    ZSTD_CCtx_params appliedParams;
+    ZSTD_CCtx_params simpleApiParams;    /* Param storage used by the simple API - not sticky. Must only be used in top-level simple API functions for storage. */
+    U32   dictID;
+    size_t dictContentSize;
+
+    ZSTD_cwksp workspace; /* manages buffer for dynamic allocations */
+    size_t blockSizeMax;
+    unsigned long long pledgedSrcSizePlusOne;  /* this way, 0 (default) == unknown */
+    unsigned long long consumedSrcSize;
+    unsigned long long producedCSize;
+    XXH64_state_t xxhState;
+    ZSTD_customMem customMem;
+    ZSTD_threadPool* pool;
+    size_t staticSize;
+    SeqCollector seqCollector;
+    int isFirstBlock;
+    int initialized;
+
+    SeqStore_t seqStore;      /* sequences storage ptrs */
+    ldmState_t ldmState;      /* long distance matching state */
+    rawSeq* ldmSequences;     /* Storage for the ldm output sequences */
+    size_t maxNbLdmSequences;
+    RawSeqStore_t externSeqStore; /* Mutable reference to external sequences */
+    ZSTD_blockState_t blockState;
+    void* tmpWorkspace;  /* used as substitute of stack space - must be aligned for S64 type */
+    size_t tmpWkspSize;
+
+    /* Whether we are streaming or not */
+    ZSTD_buffered_policy_e bufferedPolicy;
+
+    /* streaming */
+    char*  inBuff;
+    size_t inBuffSize;
+    size_t inToCompress;
+    size_t inBuffPos;
+    size_t inBuffTarget;
+    char*  outBuff;
+    size_t outBuffSize;
+    size_t outBuffContentSize;
+    size_t outBuffFlushedSize;
+    ZSTD_cStreamStage streamStage;
+    U32    frameEnded;
+
+    /* Stable in/out buffer verification */
+    ZSTD_inBuffer expectedInBuffer;
+    size_t stableIn_notConsumed; /* nb bytes within stable input buffer that are said to be consumed but are not */
+    size_t expectedOutBufferSize;
+
+    /* Dictionary */
+    ZSTD_localDict localDict;
+    const ZSTD_CDict* cdict;
+    ZSTD_prefixDict prefixDict;   /* single-usage dictionary */
+
+    /* Multi-threading */
+#ifdef ZSTD_MULTITHREAD
+    ZSTDMT_CCtx* mtctx;
+#endif
+
+    /* Tracing */
+#if ZSTD_TRACE
+    ZSTD_TraceCtx traceCtx;
+#endif
+
+    /* Workspace for block splitter */
+    ZSTD_blockSplitCtx blockSplitCtx;
+
+    /* Buffer for output from external sequence producer */
+    ZSTD_Sequence* extSeqBuf;
+    size_t extSeqBufCapacity;
+};
+
+typedef enum { ZSTD_dtlm_fast, ZSTD_dtlm_full } ZSTD_dictTableLoadMethod_e;
+typedef enum { ZSTD_tfp_forCCtx, ZSTD_tfp_forCDict } ZSTD_tableFillPurpose_e;
+
+typedef enum {
+    ZSTD_noDict = 0,
+    ZSTD_extDict = 1,
+    ZSTD_dictMatchState = 2,
+    ZSTD_dedicatedDictSearch = 3
+} ZSTD_dictMode_e;
+
+typedef enum {
+    ZSTD_cpm_noAttachDict = 0,  /* Compression with ZSTD_noDict or ZSTD_extDict.
+                                 * In this mode we use both the srcSize and the dictSize
+                                 * when selecting and adjusting parameters.
+                                 */
+    ZSTD_cpm_attachDict = 1,    /* Compression with ZSTD_dictMatchState or ZSTD_dedicatedDictSearch.
+                                 * In this mode we only take the srcSize into account when selecting
+                                 * and adjusting parameters.
+                                 */
+    ZSTD_cpm_createCDict = 2,   /* Creating a CDict.
+                                 * In this mode we take both the source size and the dictionary size
+                                 * into account when selecting and adjusting the parameters.
+                                 */
+    ZSTD_cpm_unknown = 3        /* ZSTD_getCParams, ZSTD_getParams, ZSTD_adjustParams.
+                                 * We don't know what these parameters are for. We default to the legacy
+                                 * behavior of taking both the source size and the dict size into account
+                                 * when selecting and adjusting parameters.
+                                 */
+} ZSTD_CParamMode_e;
+
+typedef size_t (*ZSTD_BlockCompressor_f) (
+        ZSTD_MatchState_t* bs, SeqStore_t* seqStore, U32 rep[ZSTD_REP_NUM],
+        void const* src, size_t srcSize);
+ZSTD_BlockCompressor_f ZSTD_selectBlockCompressor(ZSTD_strategy strat, ZSTD_ParamSwitch_e rowMatchfinderMode, ZSTD_dictMode_e dictMode);
+
+
+MEM_STATIC U32 ZSTD_LLcode(U32 litLength)
+{
+    static const BYTE LL_Code[64] = {  0,  1,  2,  3,  4,  5,  6,  7,
+                                       8,  9, 10, 11, 12, 13, 14, 15,
+                                      16, 16, 17, 17, 18, 18, 19, 19,
+                                      20, 20, 20, 20, 21, 21, 21, 21,
+                                      22, 22, 22, 22, 22, 22, 22, 22,
+                                      23, 23, 23, 23, 23, 23, 23, 23,
+                                      24, 24, 24, 24, 24, 24, 24, 24,
+                                      24, 24, 24, 24, 24, 24, 24, 24 };
+    static const U32 LL_deltaCode = 19;
+    return (litLength > 63) ? ZSTD_highbit32(litLength) + LL_deltaCode : LL_Code[litLength];
+}
+
+/* ZSTD_MLcode() :
+ * note : mlBase = matchLength - MINMATCH;
+ *        because it's the format it's stored in seqStore->sequences */
+MEM_STATIC U32 ZSTD_MLcode(U32 mlBase)
+{
+    static const BYTE ML_Code[128] = { 0,  1,  2,  3,  4,  5,  6,  7,  8,  9, 10, 11, 12, 13, 14, 15,
+                                      16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31,
+                                      32, 32, 33, 33, 34, 34, 35, 35, 36, 36, 36, 36, 37, 37, 37, 37,
+                                      38, 38, 38, 38, 38, 38, 38, 38, 39, 39, 39, 39, 39, 39, 39, 39,
+                                      40, 40, 40, 40, 40, 40, 40, 40, 40, 40, 40, 40, 40, 40, 40, 40,
+                                      41, 41, 41, 41, 41, 41, 41, 41, 41, 41, 41, 41, 41, 41, 41, 41,
+                                      42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42,
+                                      42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42 };
+    static const U32 ML_deltaCode = 36;
+    return (mlBase > 127) ? ZSTD_highbit32(mlBase) + ML_deltaCode : ML_Code[mlBase];
+}
+
+/* ZSTD_cParam_withinBounds:
+ * @return 1 if value is within cParam bounds,
+ * 0 otherwise */
+MEM_STATIC int ZSTD_cParam_withinBounds(ZSTD_cParameter cParam, int value)
+{
+    ZSTD_bounds const bounds = ZSTD_cParam_getBounds(cParam);
+    if (ZSTD_isError(bounds.error)) return 0;
+    if (value < bounds.lowerBound) return 0;
+    if (value > bounds.upperBound) return 0;
+    return 1;
+}
+
+/* ZSTD_selectAddr:
+ * @return index >= lowLimit ? candidate : backup,
+ * tries to force branchless codegen. */
+MEM_STATIC const BYTE*
+ZSTD_selectAddr(U32 index, U32 lowLimit, const BYTE* candidate, const BYTE* backup)
+{
+#if defined(__GNUC__) && defined(__x86_64__)
+    __asm__ (
+        "cmp %1, %2\n"
+        "cmova %3, %0\n"
+        : "+r"(candidate)
+        : "r"(index), "r"(lowLimit), "r"(backup)
+        );
+    return candidate;
+#else
+    return index >= lowLimit ? candidate : backup;
+#endif
+}
+
+/* ZSTD_noCompressBlock() :
+ * Writes uncompressed block to dst buffer from given src.
+ * Returns the size of the block */
+MEM_STATIC size_t
+ZSTD_noCompressBlock(void* dst, size_t dstCapacity, const void* src, size_t srcSize, U32 lastBlock)
+{
+    U32 const cBlockHeader24 = lastBlock + (((U32)bt_raw)<<1) + (U32)(srcSize << 3);
+    DEBUGLOG(5, "ZSTD_noCompressBlock (srcSize=%zu, dstCapacity=%zu)", srcSize, dstCapacity);
+    RETURN_ERROR_IF(srcSize + ZSTD_blockHeaderSize > dstCapacity,
+                    dstSize_tooSmall, "dst buf too small for uncompressed block");
+    MEM_writeLE24(dst, cBlockHeader24);
+    ZSTD_memcpy((BYTE*)dst + ZSTD_blockHeaderSize, src, srcSize);
+    return ZSTD_blockHeaderSize + srcSize;
+}
+
+MEM_STATIC size_t
+ZSTD_rleCompressBlock(void* dst, size_t dstCapacity, BYTE src, size_t srcSize, U32 lastBlock)
+{
+    BYTE* const op = (BYTE*)dst;
+    U32 const cBlockHeader = lastBlock + (((U32)bt_rle)<<1) + (U32)(srcSize << 3);
+    RETURN_ERROR_IF(dstCapacity < 4, dstSize_tooSmall, "");
+    MEM_writeLE24(op, cBlockHeader);
+    op[3] = src;
+    return 4;
+}
+
+
+/* ZSTD_minGain() :
+ * minimum compression required
+ * to generate a compress block or a compressed literals section.
+ * note : use same formula for both situations */
+MEM_STATIC size_t ZSTD_minGain(size_t srcSize, ZSTD_strategy strat)
+{
+    U32 const minlog = (strat>=ZSTD_btultra) ? (U32)(strat) - 1 : 6;
+    ZSTD_STATIC_ASSERT(ZSTD_btultra == 8);
+    assert(ZSTD_cParam_withinBounds(ZSTD_c_strategy, (int)strat));
+    return (srcSize >> minlog) + 2;
+}
+
+MEM_STATIC int ZSTD_literalsCompressionIsDisabled(const ZSTD_CCtx_params* cctxParams)
+{
+    switch (cctxParams->literalCompressionMode) {
+    case ZSTD_ps_enable:
+        return 0;
+    case ZSTD_ps_disable:
+        return 1;
+    default:
+        assert(0 /* impossible: pre-validated */);
+        ZSTD_FALLTHROUGH;
+    case ZSTD_ps_auto:
+        return (cctxParams->cParams.strategy == ZSTD_fast) && (cctxParams->cParams.targetLength > 0);
+    }
+}
+
+/*! ZSTD_safecopyLiterals() :
+ *  memcpy() function that won't read beyond more than WILDCOPY_OVERLENGTH bytes past ilimit_w.
+ *  Only called when the sequence ends past ilimit_w, so it only needs to be optimized for single
+ *  large copies.
+ */
+static void
+ZSTD_safecopyLiterals(BYTE* op, BYTE const* ip, BYTE const* const iend, BYTE const* ilimit_w)
+{
+    assert(iend > ilimit_w);
+    if (ip <= ilimit_w) {
+        ZSTD_wildcopy(op, ip, ilimit_w - ip, ZSTD_no_overlap);
+        op += ilimit_w - ip;
+        ip = ilimit_w;
+    }
+    while (ip < iend) *op++ = *ip++;
+}
+
+
+#define REPCODE1_TO_OFFBASE REPCODE_TO_OFFBASE(1)
+#define REPCODE2_TO_OFFBASE REPCODE_TO_OFFBASE(2)
+#define REPCODE3_TO_OFFBASE REPCODE_TO_OFFBASE(3)
+#define REPCODE_TO_OFFBASE(r) (assert((r)>=1), assert((r)<=ZSTD_REP_NUM), (r)) /* accepts IDs 1,2,3 */
+#define OFFSET_TO_OFFBASE(o)  (assert((o)>0), o + ZSTD_REP_NUM)
+#define OFFBASE_IS_OFFSET(o)  ((o) > ZSTD_REP_NUM)
+#define OFFBASE_IS_REPCODE(o) ( 1 <= (o) && (o) <= ZSTD_REP_NUM)
+#define OFFBASE_TO_OFFSET(o)  (assert(OFFBASE_IS_OFFSET(o)), (o) - ZSTD_REP_NUM)
+#define OFFBASE_TO_REPCODE(o) (assert(OFFBASE_IS_REPCODE(o)), (o))  /* returns ID 1,2,3 */
+
+/*! ZSTD_storeSeqOnly() :
+ *  Store a sequence (litlen, litPtr, offBase and matchLength) into SeqStore_t.
+ *  Literals themselves are not copied, but @litPtr is updated.
+ *  @offBase : Users should employ macros REPCODE_TO_OFFBASE() and OFFSET_TO_OFFBASE().
+ *  @matchLength : must be >= MINMATCH
+*/
+HINT_INLINE UNUSED_ATTR void
+ZSTD_storeSeqOnly(SeqStore_t* seqStorePtr,
+              size_t litLength,
+              U32 offBase,
+              size_t matchLength)
+{
+    assert((size_t)(seqStorePtr->sequences - seqStorePtr->sequencesStart) < seqStorePtr->maxNbSeq);
+
+    /* literal Length */
+    assert(litLength <= ZSTD_BLOCKSIZE_MAX);
+    if (UNLIKELY(litLength>0xFFFF)) {
+        assert(seqStorePtr->longLengthType == ZSTD_llt_none); /* there can only be a single long length */
+        seqStorePtr->longLengthType = ZSTD_llt_literalLength;
+        seqStorePtr->longLengthPos = (U32)(seqStorePtr->sequences - seqStorePtr->sequencesStart);
+    }
+    seqStorePtr->sequences[0].litLength = (U16)litLength;
+
+    /* match offset */
+    seqStorePtr->sequences[0].offBase = offBase;
+
+    /* match Length */
+    assert(matchLength <= ZSTD_BLOCKSIZE_MAX);
+    assert(matchLength >= MINMATCH);
+    {   size_t const mlBase = matchLength - MINMATCH;
+        if (UNLIKELY(mlBase>0xFFFF)) {
+            assert(seqStorePtr->longLengthType == ZSTD_llt_none); /* there can only be a single long length */
+            seqStorePtr->longLengthType = ZSTD_llt_matchLength;
+            seqStorePtr->longLengthPos = (U32)(seqStorePtr->sequences - seqStorePtr->sequencesStart);
+        }
+        seqStorePtr->sequences[0].mlBase = (U16)mlBase;
+    }
+
+    seqStorePtr->sequences++;
+}
+
+/*! ZSTD_storeSeq() :
+ *  Store a sequence (litlen, litPtr, offBase and matchLength) into SeqStore_t.
+ *  @offBase : Users should employ macros REPCODE_TO_OFFBASE() and OFFSET_TO_OFFBASE().
+ *  @matchLength : must be >= MINMATCH
+ *  Allowed to over-read literals up to litLimit.
+*/
+HINT_INLINE UNUSED_ATTR void
+ZSTD_storeSeq(SeqStore_t* seqStorePtr,
+              size_t litLength, const BYTE* literals, const BYTE* litLimit,
+              U32 offBase,
+              size_t matchLength)
+{
+    BYTE const* const litLimit_w = litLimit - WILDCOPY_OVERLENGTH;
+    BYTE const* const litEnd = literals + litLength;
+#if defined(DEBUGLEVEL) && (DEBUGLEVEL >= 6)
+    static const BYTE* g_start = NULL;
+    if (g_start==NULL) g_start = (const BYTE*)literals;  /* note : index only works for compression within a single segment */
+    {   U32 const pos = (U32)((const BYTE*)literals - g_start);
+        DEBUGLOG(6, "Cpos%7u :%3u literals, match%4u bytes at offBase%7u",
+               pos, (U32)litLength, (U32)matchLength, (U32)offBase);
+    }
+#endif
+    assert((size_t)(seqStorePtr->sequences - seqStorePtr->sequencesStart) < seqStorePtr->maxNbSeq);
+    /* copy Literals */
+    assert(seqStorePtr->maxNbLit <= 128 KB);
+    assert(seqStorePtr->lit + litLength <= seqStorePtr->litStart + seqStorePtr->maxNbLit);
+    assert(literals + litLength <= litLimit);
+    if (litEnd <= litLimit_w) {
+        /* Common case we can use wildcopy.
+         * First copy 16 bytes, because literals are likely short.
+         */
+        ZSTD_STATIC_ASSERT(WILDCOPY_OVERLENGTH >= 16);
+        ZSTD_copy16(seqStorePtr->lit, literals);
+        if (litLength > 16) {
+            ZSTD_wildcopy(seqStorePtr->lit+16, literals+16, (ptrdiff_t)litLength-16, ZSTD_no_overlap);
+        }
+    } else {
+        ZSTD_safecopyLiterals(seqStorePtr->lit, literals, litEnd, litLimit_w);
+    }
+    seqStorePtr->lit += litLength;
+
+    ZSTD_storeSeqOnly(seqStorePtr, litLength, offBase, matchLength);
+}
+
+/* ZSTD_updateRep() :
+ * updates in-place @rep (array of repeat offsets)
+ * @offBase : sum-type, using numeric representation of ZSTD_storeSeq()
+ */
+MEM_STATIC void
+ZSTD_updateRep(U32 rep[ZSTD_REP_NUM], U32 const offBase, U32 const ll0)
+{
+    if (OFFBASE_IS_OFFSET(offBase)) {  /* full offset */
+        rep[2] = rep[1];
+        rep[1] = rep[0];
+        rep[0] = OFFBASE_TO_OFFSET(offBase);
+    } else {   /* repcode */
+        U32 const repCode = OFFBASE_TO_REPCODE(offBase) - 1 + ll0;
+        if (repCode > 0) {  /* note : if repCode==0, no change */
+            U32 const currentOffset = (repCode==ZSTD_REP_NUM) ? (rep[0] - 1) : rep[repCode];
+            rep[2] = (repCode >= 2) ? rep[1] : rep[2];
+            rep[1] = rep[0];
+            rep[0] = currentOffset;
+        } else {   /* repCode == 0 */
+            /* nothing to do */
+        }
+    }
+}
+
+typedef struct repcodes_s {
+    U32 rep[3];
+} Repcodes_t;
+
+MEM_STATIC Repcodes_t
+ZSTD_newRep(U32 const rep[ZSTD_REP_NUM], U32 const offBase, U32 const ll0)
+{
+    Repcodes_t newReps;
+    ZSTD_memcpy(&newReps, rep, sizeof(newReps));
+    ZSTD_updateRep(newReps.rep, offBase, ll0);
+    return newReps;
+}
+
+
+/*-*************************************
+*  Match length counter
+***************************************/
+MEM_STATIC size_t ZSTD_count(const BYTE* pIn, const BYTE* pMatch, const BYTE* const pInLimit)
+{
+    const BYTE* const pStart = pIn;
+    const BYTE* const pInLoopLimit = pInLimit - (sizeof(size_t)-1);
+
+    if (pIn < pInLoopLimit) {
+        { size_t const diff = MEM_readST(pMatch) ^ MEM_readST(pIn);
+          if (diff) return ZSTD_NbCommonBytes(diff); }
+        pIn+=sizeof(size_t); pMatch+=sizeof(size_t);
+        while (pIn < pInLoopLimit) {
+            size_t const diff = MEM_readST(pMatch) ^ MEM_readST(pIn);
+            if (!diff) { pIn+=sizeof(size_t); pMatch+=sizeof(size_t); continue; }
+            pIn += ZSTD_NbCommonBytes(diff);
+            return (size_t)(pIn - pStart);
+    }   }
+    if (MEM_64bits() && (pIn<(pInLimit-3)) && (MEM_read32(pMatch) == MEM_read32(pIn))) { pIn+=4; pMatch+=4; }
+    if ((pIn<(pInLimit-1)) && (MEM_read16(pMatch) == MEM_read16(pIn))) { pIn+=2; pMatch+=2; }
+    if ((pIn<pInLimit) && (*pMatch == *pIn)) pIn++;
+    return (size_t)(pIn - pStart);
+}
+
+/** ZSTD_count_2segments() :
+ *  can count match length with `ip` & `match` in 2 different segments.
+ *  convention : on reaching mEnd, match count continue starting from iStart
+ */
+MEM_STATIC size_t
+ZSTD_count_2segments(const BYTE* ip, const BYTE* match,
+                     const BYTE* iEnd, const BYTE* mEnd, const BYTE* iStart)
+{
+    const BYTE* const vEnd = MIN( ip + (mEnd - match), iEnd);
+    size_t const matchLength = ZSTD_count(ip, match, vEnd);
+    if (match + matchLength != mEnd) return matchLength;
+    DEBUGLOG(7, "ZSTD_count_2segments: found a 2-parts match (current length==%zu)", matchLength);
+    DEBUGLOG(7, "distance from match beginning to end dictionary = %i", (int)(mEnd - match));
+    DEBUGLOG(7, "distance from current pos to end buffer = %i", (int)(iEnd - ip));
+    DEBUGLOG(7, "next byte : ip==%02X, istart==%02X", ip[matchLength], *iStart);
+    DEBUGLOG(7, "final match length = %zu", matchLength + ZSTD_count(ip+matchLength, iStart, iEnd));
+    return matchLength + ZSTD_count(ip+matchLength, iStart, iEnd);
+}
+
+
+/*-*************************************
+ *  Hashes
+ ***************************************/
+static const U32 prime3bytes = 506832829U;
+static U32    ZSTD_hash3(U32 u, U32 h, U32 s) { assert(h <= 32); return (((u << (32-24)) * prime3bytes) ^ s)  >> (32-h) ; }
+MEM_STATIC size_t ZSTD_hash3Ptr(const void* ptr, U32 h) { return ZSTD_hash3(MEM_readLE32(ptr), h, 0); } /* only in zstd_opt.h */
+MEM_STATIC size_t ZSTD_hash3PtrS(const void* ptr, U32 h, U32 s) { return ZSTD_hash3(MEM_readLE32(ptr), h, s); }
+
+static const U32 prime4bytes = 2654435761U;
+static U32    ZSTD_hash4(U32 u, U32 h, U32 s) { assert(h <= 32); return ((u * prime4bytes) ^ s) >> (32-h) ; }
+static size_t ZSTD_hash4Ptr(const void* ptr, U32 h) { return ZSTD_hash4(MEM_readLE32(ptr), h, 0); }
+static size_t ZSTD_hash4PtrS(const void* ptr, U32 h, U32 s) { return ZSTD_hash4(MEM_readLE32(ptr), h, s); }
+
+static const U64 prime5bytes = 889523592379ULL;
+static size_t ZSTD_hash5(U64 u, U32 h, U64 s) { assert(h <= 64); return (size_t)((((u  << (64-40)) * prime5bytes) ^ s) >> (64-h)) ; }
+static size_t ZSTD_hash5Ptr(const void* p, U32 h) { return ZSTD_hash5(MEM_readLE64(p), h, 0); }
+static size_t ZSTD_hash5PtrS(const void* p, U32 h, U64 s) { return ZSTD_hash5(MEM_readLE64(p), h, s); }
+
+static const U64 prime6bytes = 227718039650203ULL;
+static size_t ZSTD_hash6(U64 u, U32 h, U64 s) { assert(h <= 64); return (size_t)((((u  << (64-48)) * prime6bytes) ^ s) >> (64-h)) ; }
+static size_t ZSTD_hash6Ptr(const void* p, U32 h) { return ZSTD_hash6(MEM_readLE64(p), h, 0); }
+static size_t ZSTD_hash6PtrS(const void* p, U32 h, U64 s) { return ZSTD_hash6(MEM_readLE64(p), h, s); }
+
+static const U64 prime7bytes = 58295818150454627ULL;
+static size_t ZSTD_hash7(U64 u, U32 h, U64 s) { assert(h <= 64); return (size_t)((((u  << (64-56)) * prime7bytes) ^ s) >> (64-h)) ; }
+static size_t ZSTD_hash7Ptr(const void* p, U32 h) { return ZSTD_hash7(MEM_readLE64(p), h, 0); }
+static size_t ZSTD_hash7PtrS(const void* p, U32 h, U64 s) { return ZSTD_hash7(MEM_readLE64(p), h, s); }
+
+static const U64 prime8bytes = 0xCF1BBCDCB7A56463ULL;
+static size_t ZSTD_hash8(U64 u, U32 h, U64 s) { assert(h <= 64); return (size_t)((((u) * prime8bytes)  ^ s) >> (64-h)) ; }
+static size_t ZSTD_hash8Ptr(const void* p, U32 h) { return ZSTD_hash8(MEM_readLE64(p), h, 0); }
+static size_t ZSTD_hash8PtrS(const void* p, U32 h, U64 s) { return ZSTD_hash8(MEM_readLE64(p), h, s); }
+
+
+MEM_STATIC FORCE_INLINE_ATTR
+size_t ZSTD_hashPtr(const void* p, U32 hBits, U32 mls)
+{
+    /* Although some of these hashes do support hBits up to 64, some do not.
+     * To be on the safe side, always avoid hBits > 32. */
+    assert(hBits <= 32);
+
+    switch(mls)
+    {
+    default:
+    case 4: return ZSTD_hash4Ptr(p, hBits);
+    case 5: return ZSTD_hash5Ptr(p, hBits);
+    case 6: return ZSTD_hash6Ptr(p, hBits);
+    case 7: return ZSTD_hash7Ptr(p, hBits);
+    case 8: return ZSTD_hash8Ptr(p, hBits);
+    }
+}
+
+MEM_STATIC FORCE_INLINE_ATTR
+size_t ZSTD_hashPtrSalted(const void* p, U32 hBits, U32 mls, const U64 hashSalt) {
+    /* Although some of these hashes do support hBits up to 64, some do not.
+     * To be on the safe side, always avoid hBits > 32. */
+    assert(hBits <= 32);
+
+    switch(mls)
+    {
+        default:
+        case 4: return ZSTD_hash4PtrS(p, hBits, (U32)hashSalt);
+        case 5: return ZSTD_hash5PtrS(p, hBits, hashSalt);
+        case 6: return ZSTD_hash6PtrS(p, hBits, hashSalt);
+        case 7: return ZSTD_hash7PtrS(p, hBits, hashSalt);
+        case 8: return ZSTD_hash8PtrS(p, hBits, hashSalt);
+    }
+}
+
+
+/** ZSTD_ipow() :
+ * Return base^exponent.
+ */
+static U64 ZSTD_ipow(U64 base, U64 exponent)
+{
+    U64 power = 1;
+    while (exponent) {
+      if (exponent & 1) power *= base;
+      exponent >>= 1;
+      base *= base;
+    }
+    return power;
+}
+
+#define ZSTD_ROLL_HASH_CHAR_OFFSET 10
+
+/** ZSTD_rollingHash_append() :
+ * Add the buffer to the hash value.
+ */
+static U64 ZSTD_rollingHash_append(U64 hash, void const* buf, size_t size)
+{
+    BYTE const* istart = (BYTE const*)buf;
+    size_t pos;
+    for (pos = 0; pos < size; ++pos) {
+        hash *= prime8bytes;
+        hash += istart[pos] + ZSTD_ROLL_HASH_CHAR_OFFSET;
+    }
+    return hash;
+}
+
+/** ZSTD_rollingHash_compute() :
+ * Compute the rolling hash value of the buffer.
+ */
+MEM_STATIC U64 ZSTD_rollingHash_compute(void const* buf, size_t size)
+{
+    return ZSTD_rollingHash_append(0, buf, size);
+}
+
+/** ZSTD_rollingHash_primePower() :
+ * Compute the primePower to be passed to ZSTD_rollingHash_rotate() for a hash
+ * over a window of length bytes.
+ */
+MEM_STATIC U64 ZSTD_rollingHash_primePower(U32 length)
+{
+    return ZSTD_ipow(prime8bytes, length - 1);
+}
+
+/** ZSTD_rollingHash_rotate() :
+ * Rotate the rolling hash by one byte.
+ */
+MEM_STATIC U64 ZSTD_rollingHash_rotate(U64 hash, BYTE toRemove, BYTE toAdd, U64 primePower)
+{
+    hash -= (toRemove + ZSTD_ROLL_HASH_CHAR_OFFSET) * primePower;
+    hash *= prime8bytes;
+    hash += toAdd + ZSTD_ROLL_HASH_CHAR_OFFSET;
+    return hash;
+}
+
+/*-*************************************
+*  Round buffer management
+***************************************/
+/* Max @current value allowed:
+ * In 32-bit mode: we want to avoid crossing the 2 GB limit,
+ *                 reducing risks of side effects in case of signed operations on indexes.
+ * In 64-bit mode: we want to ensure that adding the maximum job size (512 MB)
+ *                 doesn't overflow U32 index capacity (4 GB) */
+#define ZSTD_CURRENT_MAX (MEM_64bits() ? 3500U MB : 2000U MB)
+/* Maximum chunk size before overflow correction needs to be called again */
+#define ZSTD_CHUNKSIZE_MAX                                                     \
+    ( ((U32)-1)                  /* Maximum ending current index */            \
+    - ZSTD_CURRENT_MAX)          /* Maximum beginning lowLimit */
+
+/**
+ * ZSTD_window_clear():
+ * Clears the window containing the history by simply setting it to empty.
+ */
+MEM_STATIC void ZSTD_window_clear(ZSTD_window_t* window)
+{
+    size_t const endT = (size_t)(window->nextSrc - window->base);
+    U32 const end = (U32)endT;
+
+    window->lowLimit = end;
+    window->dictLimit = end;
+}
+
+MEM_STATIC U32 ZSTD_window_isEmpty(ZSTD_window_t const window)
+{
+    return window.dictLimit == ZSTD_WINDOW_START_INDEX &&
+           window.lowLimit == ZSTD_WINDOW_START_INDEX &&
+           (window.nextSrc - window.base) == ZSTD_WINDOW_START_INDEX;
+}
+
+/**
+ * ZSTD_window_hasExtDict():
+ * Returns non-zero if the window has a non-empty extDict.
+ */
+MEM_STATIC U32 ZSTD_window_hasExtDict(ZSTD_window_t const window)
+{
+    return window.lowLimit < window.dictLimit;
+}
+
+/**
+ * ZSTD_matchState_dictMode():
+ * Inspects the provided matchState and figures out what dictMode should be
+ * passed to the compressor.
+ */
+MEM_STATIC ZSTD_dictMode_e ZSTD_matchState_dictMode(const ZSTD_MatchState_t *ms)
+{
+    return ZSTD_window_hasExtDict(ms->window) ?
+        ZSTD_extDict :
+        ms->dictMatchState != NULL ?
+            (ms->dictMatchState->dedicatedDictSearch ? ZSTD_dedicatedDictSearch : ZSTD_dictMatchState) :
+            ZSTD_noDict;
+}
+
+/* Defining this macro to non-zero tells zstd to run the overflow correction
+ * code much more frequently. This is very inefficient, and should only be
+ * used for tests and fuzzers.
+ */
+#ifndef ZSTD_WINDOW_OVERFLOW_CORRECT_FREQUENTLY
+#  ifdef FUZZING_BUILD_MODE_UNSAFE_FOR_PRODUCTION
+#    define ZSTD_WINDOW_OVERFLOW_CORRECT_FREQUENTLY 1
+#  else
+#    define ZSTD_WINDOW_OVERFLOW_CORRECT_FREQUENTLY 0
+#  endif
+#endif
+
+/**
+ * ZSTD_window_canOverflowCorrect():
+ * Returns non-zero if the indices are large enough for overflow correction
+ * to work correctly without impacting compression ratio.
+ */
+MEM_STATIC U32 ZSTD_window_canOverflowCorrect(ZSTD_window_t const window,
+                                              U32 cycleLog,
+                                              U32 maxDist,
+                                              U32 loadedDictEnd,
+                                              void const* src)
+{
+    U32 const cycleSize = 1u << cycleLog;
+    U32 const curr = (U32)((BYTE const*)src - window.base);
+    U32 const minIndexToOverflowCorrect = cycleSize
+                                        + MAX(maxDist, cycleSize)
+                                        + ZSTD_WINDOW_START_INDEX;
+
+    /* Adjust the min index to backoff the overflow correction frequency,
+     * so we don't waste too much CPU in overflow correction. If this
+     * computation overflows we don't really care, we just need to make
+     * sure it is at least minIndexToOverflowCorrect.
+     */
+    U32 const adjustment = window.nbOverflowCorrections + 1;
+    U32 const adjustedIndex = MAX(minIndexToOverflowCorrect * adjustment,
+                                  minIndexToOverflowCorrect);
+    U32 const indexLargeEnough = curr > adjustedIndex;
+
+    /* Only overflow correct early if the dictionary is invalidated already,
+     * so we don't hurt compression ratio.
+     */
+    U32 const dictionaryInvalidated = curr > maxDist + loadedDictEnd;
+
+    return indexLargeEnough && dictionaryInvalidated;
+}
+
+/**
+ * ZSTD_window_needOverflowCorrection():
+ * Returns non-zero if the indices are getting too large and need overflow
+ * protection.
+ */
+MEM_STATIC U32 ZSTD_window_needOverflowCorrection(ZSTD_window_t const window,
+                                                  U32 cycleLog,
+                                                  U32 maxDist,
+                                                  U32 loadedDictEnd,
+                                                  void const* src,
+                                                  void const* srcEnd)
+{
+    U32 const curr = (U32)((BYTE const*)srcEnd - window.base);
+    if (ZSTD_WINDOW_OVERFLOW_CORRECT_FREQUENTLY) {
+        if (ZSTD_window_canOverflowCorrect(window, cycleLog, maxDist, loadedDictEnd, src)) {
+            return 1;
+        }
+    }
+    return curr > ZSTD_CURRENT_MAX;
+}
+
+/**
+ * ZSTD_window_correctOverflow():
+ * Reduces the indices to protect from index overflow.
+ * Returns the correction made to the indices, which must be applied to every
+ * stored index.
+ *
+ * The least significant cycleLog bits of the indices must remain the same,
+ * which may be 0. Every index up to maxDist in the past must be valid.
+ */
+MEM_STATIC
+ZSTD_ALLOW_POINTER_OVERFLOW_ATTR
+U32 ZSTD_window_correctOverflow(ZSTD_window_t* window, U32 cycleLog,
+                                           U32 maxDist, void const* src)
+{
+    /* preemptive overflow correction:
+     * 1. correction is large enough:
+     *    lowLimit > (3<<29) ==> current > 3<<29 + 1<<windowLog
+     *    1<<windowLog <= newCurrent < 1<<chainLog + 1<<windowLog
+     *
+     *    current - newCurrent
+     *    > (3<<29 + 1<<windowLog) - (1<<windowLog + 1<<chainLog)
+     *    > (3<<29) - (1<<chainLog)
+     *    > (3<<29) - (1<<30)             (NOTE: chainLog <= 30)
+     *    > 1<<29
+     *
+     * 2. (ip+ZSTD_CHUNKSIZE_MAX - cctx->base) doesn't overflow:
+     *    After correction, current is less than (1<<chainLog + 1<<windowLog).
+     *    In 64-bit mode we are safe, because we have 64-bit ptrdiff_t.
+     *    In 32-bit mode we are safe, because (chainLog <= 29), so
+     *    ip+ZSTD_CHUNKSIZE_MAX - cctx->base < 1<<32.
+     * 3. (cctx->lowLimit + 1<<windowLog) < 1<<32:
+     *    windowLog <= 31 ==> 3<<29 + 1<<windowLog < 7<<29 < 1<<32.
+     */
+    U32 const cycleSize = 1u << cycleLog;
+    U32 const cycleMask = cycleSize - 1;
+    U32 const curr = (U32)((BYTE const*)src - window->base);
+    U32 const currentCycle = curr & cycleMask;
+    /* Ensure newCurrent - maxDist >= ZSTD_WINDOW_START_INDEX. */
+    U32 const currentCycleCorrection = currentCycle < ZSTD_WINDOW_START_INDEX
+                                     ? MAX(cycleSize, ZSTD_WINDOW_START_INDEX)
+                                     : 0;
+    U32 const newCurrent = currentCycle
+                         + currentCycleCorrection
+                         + MAX(maxDist, cycleSize);
+    U32 const correction = curr - newCurrent;
+    /* maxDist must be a power of two so that:
+     *   (newCurrent & cycleMask) == (curr & cycleMask)
+     * This is required to not corrupt the chains / binary tree.
+     */
+    assert((maxDist & (maxDist - 1)) == 0);
+    assert((curr & cycleMask) == (newCurrent & cycleMask));
+    assert(curr > newCurrent);
+    if (!ZSTD_WINDOW_OVERFLOW_CORRECT_FREQUENTLY) {
+        /* Loose bound, should be around 1<<29 (see above) */
+        assert(correction > 1<<28);
+    }
+
+    window->base += correction;
+    window->dictBase += correction;
+    if (window->lowLimit < correction + ZSTD_WINDOW_START_INDEX) {
+        window->lowLimit = ZSTD_WINDOW_START_INDEX;
+    } else {
+        window->lowLimit -= correction;
+    }
+    if (window->dictLimit < correction + ZSTD_WINDOW_START_INDEX) {
+        window->dictLimit = ZSTD_WINDOW_START_INDEX;
+    } else {
+        window->dictLimit -= correction;
+    }
+
+    /* Ensure we can still reference the full window. */
+    assert(newCurrent >= maxDist);
+    assert(newCurrent - maxDist >= ZSTD_WINDOW_START_INDEX);
+    /* Ensure that lowLimit and dictLimit didn't underflow. */
+    assert(window->lowLimit <= newCurrent);
+    assert(window->dictLimit <= newCurrent);
+
+    ++window->nbOverflowCorrections;
+
+    DEBUGLOG(4, "Correction of 0x%x bytes to lowLimit=0x%x", correction,
+             window->lowLimit);
+    return correction;
+}
+
+/**
+ * ZSTD_window_enforceMaxDist():
+ * Updates lowLimit so that:
+ *    (srcEnd - base) - lowLimit == maxDist + loadedDictEnd
+ *
+ * It ensures index is valid as long as index >= lowLimit.
+ * This must be called before a block compression call.
+ *
+ * loadedDictEnd is only defined if a dictionary is in use for current compression.
+ * As the name implies, loadedDictEnd represents the index at end of dictionary.
+ * The value lies within context's referential, it can be directly compared to blockEndIdx.
+ *
+ * If loadedDictEndPtr is NULL, no dictionary is in use, and we use loadedDictEnd == 0.
+ * If loadedDictEndPtr is not NULL, we set it to zero after updating lowLimit.
+ * This is because dictionaries are allowed to be referenced fully
+ * as long as the last byte of the dictionary is in the window.
+ * Once input has progressed beyond window size, dictionary cannot be referenced anymore.
+ *
+ * In normal dict mode, the dictionary lies between lowLimit and dictLimit.
+ * In dictMatchState mode, lowLimit and dictLimit are the same,
+ * and the dictionary is below them.
+ * forceWindow and dictMatchState are therefore incompatible.
+ */
+MEM_STATIC void
+ZSTD_window_enforceMaxDist(ZSTD_window_t* window,
+                     const void* blockEnd,
+                           U32   maxDist,
+                           U32*  loadedDictEndPtr,
+                     const ZSTD_MatchState_t** dictMatchStatePtr)
+{
+    U32 const blockEndIdx = (U32)((BYTE const*)blockEnd - window->base);
+    U32 const loadedDictEnd = (loadedDictEndPtr != NULL) ? *loadedDictEndPtr : 0;
+    DEBUGLOG(5, "ZSTD_window_enforceMaxDist: blockEndIdx=%u, maxDist=%u, loadedDictEnd=%u",
+                (unsigned)blockEndIdx, (unsigned)maxDist, (unsigned)loadedDictEnd);
+
+    /* - When there is no dictionary : loadedDictEnd == 0.
+         In which case, the test (blockEndIdx > maxDist) is merely to avoid
+         overflowing next operation `newLowLimit = blockEndIdx - maxDist`.
+       - When there is a standard dictionary :
+         Index referential is copied from the dictionary,
+         which means it starts from 0.
+         In which case, loadedDictEnd == dictSize,
+         and it makes sense to compare `blockEndIdx > maxDist + dictSize`
+         since `blockEndIdx` also starts from zero.
+       - When there is an attached dictionary :
+         loadedDictEnd is expressed within the referential of the context,
+         so it can be directly compared against blockEndIdx.
+    */
+    if (blockEndIdx > maxDist + loadedDictEnd) {
+        U32 const newLowLimit = blockEndIdx - maxDist;
+        if (window->lowLimit < newLowLimit) window->lowLimit = newLowLimit;
+        if (window->dictLimit < window->lowLimit) {
+            DEBUGLOG(5, "Update dictLimit to match lowLimit, from %u to %u",
+                        (unsigned)window->dictLimit, (unsigned)window->lowLimit);
+            window->dictLimit = window->lowLimit;
+        }
+        /* On reaching window size, dictionaries are invalidated */
+        if (loadedDictEndPtr) *loadedDictEndPtr = 0;
+        if (dictMatchStatePtr) *dictMatchStatePtr = NULL;
+    }
+}
+
+/* Similar to ZSTD_window_enforceMaxDist(),
+ * but only invalidates dictionary
+ * when input progresses beyond window size.
+ * assumption : loadedDictEndPtr and dictMatchStatePtr are valid (non NULL)
+ *              loadedDictEnd uses same referential as window->base
+ *              maxDist is the window size */
+MEM_STATIC void
+ZSTD_checkDictValidity(const ZSTD_window_t* window,
+                       const void* blockEnd,
+                             U32   maxDist,
+                             U32*  loadedDictEndPtr,
+                       const ZSTD_MatchState_t** dictMatchStatePtr)
+{
+    assert(loadedDictEndPtr != NULL);
+    assert(dictMatchStatePtr != NULL);
+    {   U32 const blockEndIdx = (U32)((BYTE const*)blockEnd - window->base);
+        U32 const loadedDictEnd = *loadedDictEndPtr;
+        DEBUGLOG(5, "ZSTD_checkDictValidity: blockEndIdx=%u, maxDist=%u, loadedDictEnd=%u",
+                    (unsigned)blockEndIdx, (unsigned)maxDist, (unsigned)loadedDictEnd);
+        assert(blockEndIdx >= loadedDictEnd);
+
+        if (blockEndIdx > loadedDictEnd + maxDist || loadedDictEnd != window->dictLimit) {
+            /* On reaching window size, dictionaries are invalidated.
+             * For simplification, if window size is reached anywhere within next block,
+             * the dictionary is invalidated for the full block.
+             *
+             * We also have to invalidate the dictionary if ZSTD_window_update() has detected
+             * non-contiguous segments, which means that loadedDictEnd != window->dictLimit.
+             * loadedDictEnd may be 0, if forceWindow is true, but in that case we never use
+             * dictMatchState, so setting it to NULL is not a problem.
+             */
+            DEBUGLOG(6, "invalidating dictionary for current block (distance > windowSize)");
+            *loadedDictEndPtr = 0;
+            *dictMatchStatePtr = NULL;
+        } else {
+            if (*loadedDictEndPtr != 0) {
+                DEBUGLOG(6, "dictionary considered valid for current block");
+    }   }   }
+}
+
+MEM_STATIC void ZSTD_window_init(ZSTD_window_t* window) {
+    ZSTD_memset(window, 0, sizeof(*window));
+    window->base = (BYTE const*)" ";
+    window->dictBase = (BYTE const*)" ";
+    ZSTD_STATIC_ASSERT(ZSTD_DUBT_UNSORTED_MARK < ZSTD_WINDOW_START_INDEX); /* Start above ZSTD_DUBT_UNSORTED_MARK */
+    window->dictLimit = ZSTD_WINDOW_START_INDEX;    /* start from >0, so that 1st position is valid */
+    window->lowLimit = ZSTD_WINDOW_START_INDEX;     /* it ensures first and later CCtx usages compress the same */
+    window->nextSrc = window->base + ZSTD_WINDOW_START_INDEX;   /* see issue #1241 */
+    window->nbOverflowCorrections = 0;
+}
+
+/**
+ * ZSTD_window_update():
+ * Updates the window by appending [src, src + srcSize) to the window.
+ * If it is not contiguous, the current prefix becomes the extDict, and we
+ * forget about the extDict. Handles overlap of the prefix and extDict.
+ * Returns non-zero if the segment is contiguous.
+ */
+MEM_STATIC
+ZSTD_ALLOW_POINTER_OVERFLOW_ATTR
+U32 ZSTD_window_update(ZSTD_window_t* window,
+                 const void* src, size_t srcSize,
+                       int forceNonContiguous)
+{
+    BYTE const* const ip = (BYTE const*)src;
+    U32 contiguous = 1;
+    DEBUGLOG(5, "ZSTD_window_update");
+    if (srcSize == 0)
+        return contiguous;
+    assert(window->base != NULL);
+    assert(window->dictBase != NULL);
+    /* Check if blocks follow each other */
+    if (src != window->nextSrc || forceNonContiguous) {
+        /* not contiguous */
+        size_t const distanceFromBase = (size_t)(window->nextSrc - window->base);
+        DEBUGLOG(5, "Non contiguous blocks, new segment starts at %u", window->dictLimit);
+        window->lowLimit = window->dictLimit;
+        assert(distanceFromBase == (size_t)(U32)distanceFromBase);  /* should never overflow */
+        window->dictLimit = (U32)distanceFromBase;
+        window->dictBase = window->base;
+        window->base = ip - distanceFromBase;
+        /* ms->nextToUpdate = window->dictLimit; */
+        if (window->dictLimit - window->lowLimit < HASH_READ_SIZE) window->lowLimit = window->dictLimit;   /* too small extDict */
+        contiguous = 0;
+    }
+    window->nextSrc = ip + srcSize;
+    /* if input and dictionary overlap : reduce dictionary (area presumed modified by input) */
+    if ( (ip+srcSize > window->dictBase + window->lowLimit)
+       & (ip < window->dictBase + window->dictLimit)) {
+        size_t const highInputIdx = (size_t)((ip + srcSize) - window->dictBase);
+        U32 const lowLimitMax = (highInputIdx > (size_t)window->dictLimit) ? window->dictLimit : (U32)highInputIdx;
+        assert(highInputIdx < UINT_MAX);
+        window->lowLimit = lowLimitMax;
+        DEBUGLOG(5, "Overlapping extDict and input : new lowLimit = %u", window->lowLimit);
+    }
+    return contiguous;
+}
+
+/**
+ * Returns the lowest allowed match index. It may either be in the ext-dict or the prefix.
+ */
+MEM_STATIC U32 ZSTD_getLowestMatchIndex(const ZSTD_MatchState_t* ms, U32 curr, unsigned windowLog)
+{
+    U32 const maxDistance = 1U << windowLog;
+    U32 const lowestValid = ms->window.lowLimit;
+    U32 const withinWindow = (curr - lowestValid > maxDistance) ? curr - maxDistance : lowestValid;
+    U32 const isDictionary = (ms->loadedDictEnd != 0);
+    /* When using a dictionary the entire dictionary is valid if a single byte of the dictionary
+     * is within the window. We invalidate the dictionary (and set loadedDictEnd to 0) when it isn't
+     * valid for the entire block. So this check is sufficient to find the lowest valid match index.
+     */
+    U32 const matchLowest = isDictionary ? lowestValid : withinWindow;
+    return matchLowest;
+}
+
+/**
+ * Returns the lowest allowed match index in the prefix.
+ */
+MEM_STATIC U32 ZSTD_getLowestPrefixIndex(const ZSTD_MatchState_t* ms, U32 curr, unsigned windowLog)
+{
+    U32    const maxDistance = 1U << windowLog;
+    U32    const lowestValid = ms->window.dictLimit;
+    U32    const withinWindow = (curr - lowestValid > maxDistance) ? curr - maxDistance : lowestValid;
+    U32    const isDictionary = (ms->loadedDictEnd != 0);
+    /* When computing the lowest prefix index we need to take the dictionary into account to handle
+     * the edge case where the dictionary and the source are contiguous in memory.
+     */
+    U32    const matchLowest = isDictionary ? lowestValid : withinWindow;
+    return matchLowest;
+}
+
+/* index_safety_check:
+ * intentional underflow : ensure repIndex isn't overlapping dict + prefix
+ * @return 1 if values are not overlapping,
+ * 0 otherwise */
+MEM_STATIC int ZSTD_index_overlap_check(const U32 prefixLowestIndex, const U32 repIndex) {
+    return ((U32)((prefixLowestIndex-1)  - repIndex) >= 3);
+}
+
+
+/* debug functions */
+#if (DEBUGLEVEL>=2)
+
+MEM_STATIC double ZSTD_fWeight(U32 rawStat)
+{
+    U32 const fp_accuracy = 8;
+    U32 const fp_multiplier = (1 << fp_accuracy);
+    U32 const newStat = rawStat + 1;
+    U32 const hb = ZSTD_highbit32(newStat);
+    U32 const BWeight = hb * fp_multiplier;
+    U32 const FWeight = (newStat << fp_accuracy) >> hb;
+    U32 const weight = BWeight + FWeight;
+    assert(hb + fp_accuracy < 31);
+    return (double)weight / fp_multiplier;
+}
+
+/* display a table content,
+ * listing each element, its frequency, and its predicted bit cost */
+MEM_STATIC void ZSTD_debugTable(const U32* table, U32 max)
+{
+    unsigned u, sum;
+    for (u=0, sum=0; u<=max; u++) sum += table[u];
+    DEBUGLOG(2, "total nb elts: %u", sum);
+    for (u=0; u<=max; u++) {
+        DEBUGLOG(2, "%2u: %5u  (%.2f)",
+                u, table[u], ZSTD_fWeight(sum) - ZSTD_fWeight(table[u]) );
+    }
+}
+
+#endif
+
+/* Short Cache */
+
+/* Normally, zstd matchfinders follow this flow:
+ *     1. Compute hash at ip
+ *     2. Load index from hashTable[hash]
+ *     3. Check if *ip == *(base + index)
+ * In dictionary compression, loading *(base + index) is often an L2 or even L3 miss.
+ *
+ * Short cache is an optimization which allows us to avoid step 3 most of the time
+ * when the data doesn't actually match. With short cache, the flow becomes:
+ *     1. Compute (hash, currentTag) at ip. currentTag is an 8-bit independent hash at ip.
+ *     2. Load (index, matchTag) from hashTable[hash]. See ZSTD_writeTaggedIndex to understand how this works.
+ *     3. Only if currentTag == matchTag, check *ip == *(base + index). Otherwise, continue.
+ *
+ * Currently, short cache is only implemented in CDict hashtables. Thus, its use is limited to
+ * dictMatchState matchfinders.
+ */
+#define ZSTD_SHORT_CACHE_TAG_BITS 8
+#define ZSTD_SHORT_CACHE_TAG_MASK ((1u << ZSTD_SHORT_CACHE_TAG_BITS) - 1)
+
+/* Helper function for ZSTD_fillHashTable and ZSTD_fillDoubleHashTable.
+ * Unpacks hashAndTag into (hash, tag), then packs (index, tag) into hashTable[hash]. */
+MEM_STATIC void ZSTD_writeTaggedIndex(U32* const hashTable, size_t hashAndTag, U32 index) {
+    size_t const hash = hashAndTag >> ZSTD_SHORT_CACHE_TAG_BITS;
+    U32 const tag = (U32)(hashAndTag & ZSTD_SHORT_CACHE_TAG_MASK);
+    assert(index >> (32 - ZSTD_SHORT_CACHE_TAG_BITS) == 0);
+    hashTable[hash] = (index << ZSTD_SHORT_CACHE_TAG_BITS) | tag;
+}
+
+/* Helper function for short cache matchfinders.
+ * Unpacks tag1 and tag2 from lower bits of packedTag1 and packedTag2, then checks if the tags match. */
+MEM_STATIC int ZSTD_comparePackedTags(size_t packedTag1, size_t packedTag2) {
+    U32 const tag1 = packedTag1 & ZSTD_SHORT_CACHE_TAG_MASK;
+    U32 const tag2 = packedTag2 & ZSTD_SHORT_CACHE_TAG_MASK;
+    return tag1 == tag2;
+}
+
+/* ===============================================================
+ * Shared internal declarations
+ * These prototypes may be called from sources not in lib/compress
+ * =============================================================== */
+
+/* ZSTD_loadCEntropy() :
+ * dict : must point at beginning of a valid zstd dictionary.
+ * return : size of dictionary header (size of magic number + dict ID + entropy tables)
+ * assumptions : magic number supposed already checked
+ *               and dictSize >= 8 */
+size_t ZSTD_loadCEntropy(ZSTD_compressedBlockState_t* bs, void* workspace,
+                         const void* const dict, size_t dictSize);
+
+void ZSTD_reset_compressedBlockState(ZSTD_compressedBlockState_t* bs);
+
+typedef struct {
+    U32 idx;            /* Index in array of ZSTD_Sequence */
+    U32 posInSequence;  /* Position within sequence at idx */
+    size_t posInSrc;    /* Number of bytes given by sequences provided so far */
+} ZSTD_SequencePosition;
+
+/* for benchmark */
+size_t ZSTD_convertBlockSequences(ZSTD_CCtx* cctx,
+                        const ZSTD_Sequence* const inSeqs, size_t nbSequences,
+                        int const repcodeResolution);
+
+typedef struct {
+    size_t nbSequences;
+    size_t blockSize;
+    size_t litSize;
+} BlockSummary;
+
+BlockSummary ZSTD_get1BlockSummary(const ZSTD_Sequence* seqs, size_t nbSeqs);
+
+/* ==============================================================
+ * Private declarations
+ * These prototypes shall only be called from within lib/compress
+ * ============================================================== */
+
+/* ZSTD_getCParamsFromCCtxParams() :
+ * cParams are built depending on compressionLevel, src size hints,
+ * LDM and manually set compression parameters.
+ * Note: srcSizeHint == 0 means 0!
+ */
+ZSTD_compressionParameters ZSTD_getCParamsFromCCtxParams(
+        const ZSTD_CCtx_params* CCtxParams, U64 srcSizeHint, size_t dictSize, ZSTD_CParamMode_e mode);
+
+void ZSTD_resetSeqStore(SeqStore_t* ssPtr);
+
+/*! ZSTD_getCParamsFromCDict() :
+ *  as the name implies */
+ZSTD_compressionParameters ZSTD_getCParamsFromCDict(const ZSTD_CDict* cdict);
+
+/* ZSTD_compressBegin_advanced_internal() :
+ * Private use only. To be called from zstdmt_compress.c. */
+size_t ZSTD_compressBegin_advanced_internal(ZSTD_CCtx* cctx,
+                                    const void* dict, size_t dictSize,
+                                    ZSTD_dictContentType_e dictContentType,
+                                    ZSTD_dictTableLoadMethod_e dtlm,
+                                    const ZSTD_CDict* cdict,
+                                    const ZSTD_CCtx_params* params,
+                                    unsigned long long pledgedSrcSize);
+
+/* ZSTD_compress_advanced_internal() :
+ * Private use only. To be called from zstdmt_compress.c. */
+size_t ZSTD_compress_advanced_internal(ZSTD_CCtx* cctx,
+                                       void* dst, size_t dstCapacity,
+                                 const void* src, size_t srcSize,
+                                 const void* dict,size_t dictSize,
+                                 const ZSTD_CCtx_params* params);
+
+
+/* ZSTD_writeLastEmptyBlock() :
+ * output an empty Block with end-of-frame mark to complete a frame
+ * @return : size of data written into `dst` (== ZSTD_blockHeaderSize (defined in zstd_internal.h))
+ *           or an error code if `dstCapacity` is too small (<ZSTD_blockHeaderSize)
+ */
+size_t ZSTD_writeLastEmptyBlock(void* dst, size_t dstCapacity);
+
+
+/* ZSTD_referenceExternalSequences() :
+ * Must be called before starting a compression operation.
+ * seqs must parse a prefix of the source.
+ * This cannot be used when long range matching is enabled.
+ * Zstd will use these sequences, and pass the literals to a secondary block
+ * compressor.
+ * NOTE: seqs are not verified! Invalid sequences can cause out-of-bounds memory
+ * access and data corruption.
+ */
+void ZSTD_referenceExternalSequences(ZSTD_CCtx* cctx, rawSeq* seq, size_t nbSeq);
+
+/** ZSTD_cycleLog() :
+ *  condition for correct operation : hashLog > 1 */
+U32 ZSTD_cycleLog(U32 hashLog, ZSTD_strategy strat);
+
+/** ZSTD_CCtx_trace() :
+ *  Trace the end of a compression call.
+ */
+void ZSTD_CCtx_trace(ZSTD_CCtx* cctx, size_t extraCSize);
+
+/* Returns 1 if an external sequence producer is registered, otherwise returns 0. */
+MEM_STATIC int ZSTD_hasExtSeqProd(const ZSTD_CCtx_params* params) {
+    return params->extSeqProdFunc != NULL;
+}
+
+/* ===============================================================
+ * Deprecated definitions that are still used internally to avoid
+ * deprecation warnings. These functions are exactly equivalent to
+ * their public variants, but avoid the deprecation warnings.
+ * =============================================================== */
+
+size_t ZSTD_compressBegin_usingCDict_deprecated(ZSTD_CCtx* cctx, const ZSTD_CDict* cdict);
+
+size_t ZSTD_compressContinue_public(ZSTD_CCtx* cctx,
+                                    void* dst, size_t dstCapacity,
+                              const void* src, size_t srcSize);
+
+size_t ZSTD_compressEnd_public(ZSTD_CCtx* cctx,
+                               void* dst, size_t dstCapacity,
+                         const void* src, size_t srcSize);
+
+size_t ZSTD_compressBlock_deprecated(ZSTD_CCtx* cctx, void* dst, size_t dstCapacity, const void* src, size_t srcSize);
+
+
+#endif /* ZSTD_COMPRESS_H */
diff --git a/src/commonlib/bsd/zstd/compress/zstd_compress_literals.c b/src/commonlib/bsd/zstd/compress/zstd_compress_literals.c
new file mode 100644
index 0000000000..7c4960e6d6
--- /dev/null
+++ b/src/commonlib/bsd/zstd/compress/zstd_compress_literals.c
@@ -0,0 +1,237 @@
+/* SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0-only */
+
+/*
+ * Copyright (c) Meta Platforms, Inc. and affiliates.
+ * All rights reserved.
+ *
+ * This source code is licensed under both the BSD-style license (found in the
+ * LICENSE file in the root directory of this source tree) and the GPLv2 (found
+ * in the COPYING file in the root directory of this source tree).
+ * You may select, at your option, one of the above-listed licenses.
+ */
+
+ /*-*************************************
+ *  Dependencies
+ ***************************************/
+#include "zstd_compress_literals.h"
+
+
+/* **************************************************************
+*  Debug Traces
+****************************************************************/
+#if DEBUGLEVEL >= 2
+
+static size_t showHexa(const void* src, size_t srcSize)
+{
+    const BYTE* const ip = (const BYTE*)src;
+    size_t u;
+    for (u=0; u<srcSize; u++) {
+        RAWLOG(5, " %02X", ip[u]); (void)ip;
+    }
+    RAWLOG(5, " \n");
+    return srcSize;
+}
+
+#endif
+
+
+/* **************************************************************
+*  Literals compression - special cases
+****************************************************************/
+size_t ZSTD_noCompressLiterals (void* dst, size_t dstCapacity, const void* src, size_t srcSize)
+{
+    BYTE* const ostart = (BYTE*)dst;
+    U32   const flSize = 1 + (srcSize>31) + (srcSize>4095);
+
+    DEBUGLOG(5, "ZSTD_noCompressLiterals: srcSize=%zu, dstCapacity=%zu", srcSize, dstCapacity);
+
+    RETURN_ERROR_IF(srcSize + flSize > dstCapacity, dstSize_tooSmall, "");
+
+    switch(flSize)
+    {
+        case 1: /* 2 - 1 - 5 */
+            ostart[0] = (BYTE)((U32)set_basic + (srcSize<<3));
+            break;
+        case 2: /* 2 - 2 - 12 */
+            MEM_writeLE16(ostart, (U16)((U32)set_basic + (1<<2) + (srcSize<<4)));
+            break;
+        case 3: /* 2 - 2 - 20 */
+            MEM_writeLE32(ostart, (U32)((U32)set_basic + (3<<2) + (srcSize<<4)));
+            break;
+        default:   /* not necessary : flSize is {1,2,3} */
+            assert(0);
+    }
+
+    ZSTD_memcpy(ostart + flSize, src, srcSize);
+    DEBUGLOG(5, "Raw (uncompressed) literals: %u -> %u", (U32)srcSize, (U32)(srcSize + flSize));
+    return srcSize + flSize;
+}
+
+static int allBytesIdentical(const void* src, size_t srcSize)
+{
+    assert(srcSize >= 1);
+    assert(src != NULL);
+    {   const BYTE b = ((const BYTE*)src)[0];
+        size_t p;
+        for (p=1; p<srcSize; p++) {
+            if (((const BYTE*)src)[p] != b) return 0;
+        }
+        return 1;
+    }
+}
+
+size_t ZSTD_compressRleLiteralsBlock (void* dst, size_t dstCapacity, const void* src, size_t srcSize)
+{
+    BYTE* const ostart = (BYTE*)dst;
+    U32   const flSize = 1 + (srcSize>31) + (srcSize>4095);
+
+    assert(dstCapacity >= 4); (void)dstCapacity;
+    assert(allBytesIdentical(src, srcSize));
+
+    switch(flSize)
+    {
+        case 1: /* 2 - 1 - 5 */
+            ostart[0] = (BYTE)((U32)set_rle + (srcSize<<3));
+            break;
+        case 2: /* 2 - 2 - 12 */
+            MEM_writeLE16(ostart, (U16)((U32)set_rle + (1<<2) + (srcSize<<4)));
+            break;
+        case 3: /* 2 - 2 - 20 */
+            MEM_writeLE32(ostart, (U32)((U32)set_rle + (3<<2) + (srcSize<<4)));
+            break;
+        default:   /* not necessary : flSize is {1,2,3} */
+            assert(0);
+    }
+
+    ostart[flSize] = *(const BYTE*)src;
+    DEBUGLOG(5, "RLE : Repeated Literal (%02X: %u times) -> %u bytes encoded", ((const BYTE*)src)[0], (U32)srcSize, (U32)flSize + 1);
+    return flSize+1;
+}
+
+/* ZSTD_minLiteralsToCompress() :
+ * returns minimal amount of literals
+ * for literal compression to even be attempted.
+ * Minimum is made tighter as compression strategy increases.
+ */
+static size_t
+ZSTD_minLiteralsToCompress(ZSTD_strategy strategy, HUF_repeat huf_repeat)
+{
+    assert((int)strategy >= 0);
+    assert((int)strategy <= 9);
+    /* btultra2 : min 8 bytes;
+     * then 2x larger for each successive compression strategy
+     * max threshold 64 bytes */
+    {   int const shift = MIN(9-(int)strategy, 3);
+        size_t const mintc = (huf_repeat == HUF_repeat_valid) ? 6 : (size_t)8 << shift;
+        DEBUGLOG(7, "minLiteralsToCompress = %zu", mintc);
+        return mintc;
+    }
+}
+
+size_t ZSTD_compressLiterals (
+                  void* dst, size_t dstCapacity,
+            const void* src, size_t srcSize,
+                  void* entropyWorkspace, size_t entropyWorkspaceSize,
+            const ZSTD_hufCTables_t* prevHuf,
+                  ZSTD_hufCTables_t* nextHuf,
+                  ZSTD_strategy strategy,
+                  int disableLiteralCompression,
+                  int suspectUncompressible,
+                  int bmi2)
+{
+    size_t const lhSize = 3 + (srcSize >= 1 KB) + (srcSize >= 16 KB);
+    BYTE*  const ostart = (BYTE*)dst;
+    U32 singleStream = srcSize < 256;
+    SymbolEncodingType_e hType = set_compressed;
+    size_t cLitSize;
+
+    DEBUGLOG(5,"ZSTD_compressLiterals (disableLiteralCompression=%i, srcSize=%u, dstCapacity=%zu)",
+                disableLiteralCompression, (U32)srcSize, dstCapacity);
+
+    DEBUGLOG(6, "Completed literals listing (%zu bytes)", showHexa(src, srcSize));
+
+    /* Prepare nextEntropy assuming reusing the existing table */
+    ZSTD_memcpy(nextHuf, prevHuf, sizeof(*prevHuf));
+
+    if (disableLiteralCompression)
+        return ZSTD_noCompressLiterals(dst, dstCapacity, src, srcSize);
+
+    /* if too small, don't even attempt compression (speed opt) */
+    if (srcSize < ZSTD_minLiteralsToCompress(strategy, prevHuf->repeatMode))
+        return ZSTD_noCompressLiterals(dst, dstCapacity, src, srcSize);
+
+    RETURN_ERROR_IF(dstCapacity < lhSize+1, dstSize_tooSmall, "not enough space for compression");
+    {   HUF_repeat repeat = prevHuf->repeatMode;
+        int const flags = 0
+            | (bmi2 ? HUF_flags_bmi2 : 0)
+            | (strategy < ZSTD_lazy && srcSize <= 1024 ? HUF_flags_preferRepeat : 0)
+            | (strategy >= HUF_OPTIMAL_DEPTH_THRESHOLD ? HUF_flags_optimalDepth : 0)
+            | (suspectUncompressible ? HUF_flags_suspectUncompressible : 0);
+
+        typedef size_t (*huf_compress_f)(void*, size_t, const void*, size_t, unsigned, unsigned, void*, size_t, HUF_CElt*, HUF_repeat*, int);
+        huf_compress_f huf_compress;
+        if (repeat == HUF_repeat_valid && lhSize == 3) singleStream = 1;
+        huf_compress = singleStream ? HUF_compress1X_repeat : HUF_compress4X_repeat;
+        cLitSize = huf_compress(ostart+lhSize, dstCapacity-lhSize,
+                                src, srcSize,
+                                HUF_SYMBOLVALUE_MAX, LitHufLog,
+                                entropyWorkspace, entropyWorkspaceSize,
+                                (HUF_CElt*)nextHuf->CTable,
+                                &repeat, flags);
+        DEBUGLOG(5, "%zu literals compressed into %zu bytes (before header)", srcSize, cLitSize);
+        if (repeat != HUF_repeat_none) {
+            /* reused the existing table */
+            DEBUGLOG(5, "reusing statistics from previous huffman block");
+            hType = set_repeat;
+        }
+    }
+
+    {   size_t const minGain = ZSTD_minGain(srcSize, strategy);
+        if ((cLitSize==0) || (cLitSize >= srcSize - minGain) || ERR_isError(cLitSize)) {
+            ZSTD_memcpy(nextHuf, prevHuf, sizeof(*prevHuf));
+            return ZSTD_noCompressLiterals(dst, dstCapacity, src, srcSize);
+    }   }
+    if (cLitSize==1) {
+        /* A return value of 1 signals that the alphabet consists of a single symbol.
+         * However, in some rare circumstances, it could be the compressed size (a single byte).
+         * For that outcome to have a chance to happen, it's necessary that `srcSize < 8`.
+         * (it's also necessary to not generate statistics).
+         * Therefore, in such a case, actively check that all bytes are identical. */
+        if ((srcSize >= 8) || allBytesIdentical(src, srcSize)) {
+            ZSTD_memcpy(nextHuf, prevHuf, sizeof(*prevHuf));
+            return ZSTD_compressRleLiteralsBlock(dst, dstCapacity, src, srcSize);
+    }   }
+
+    if (hType == set_compressed) {
+        /* using a newly constructed table */
+        nextHuf->repeatMode = HUF_repeat_check;
+    }
+
+    /* Build header */
+    switch(lhSize)
+    {
+    case 3: /* 2 - 2 - 10 - 10 */
+        if (!singleStream) assert(srcSize >= MIN_LITERALS_FOR_4_STREAMS);
+        {   U32 const lhc = hType + ((U32)(!singleStream) << 2) + ((U32)srcSize<<4) + ((U32)cLitSize<<14);
+            MEM_writeLE24(ostart, lhc);
+            break;
+        }
+    case 4: /* 2 - 2 - 14 - 14 */
+        assert(srcSize >= MIN_LITERALS_FOR_4_STREAMS);
+        {   U32 const lhc = hType + (2 << 2) + ((U32)srcSize<<4) + ((U32)cLitSize<<18);
+            MEM_writeLE32(ostart, lhc);
+            break;
+        }
+    case 5: /* 2 - 2 - 18 - 18 */
+        assert(srcSize >= MIN_LITERALS_FOR_4_STREAMS);
+        {   U32 const lhc = hType + (3 << 2) + ((U32)srcSize<<4) + ((U32)cLitSize<<22);
+            MEM_writeLE32(ostart, lhc);
+            ostart[4] = (BYTE)(cLitSize >> 10);
+            break;
+        }
+    default:  /* not possible : lhSize is {3,4,5} */
+        assert(0);
+    }
+    DEBUGLOG(5, "Compressed literals: %u -> %u", (U32)srcSize, (U32)(lhSize+cLitSize));
+    return lhSize+cLitSize;
+}
diff --git a/src/commonlib/bsd/zstd/compress/zstd_compress_literals.h b/src/commonlib/bsd/zstd/compress/zstd_compress_literals.h
new file mode 100644
index 0000000000..994ca02e4d
--- /dev/null
+++ b/src/commonlib/bsd/zstd/compress/zstd_compress_literals.h
@@ -0,0 +1,41 @@
+/* SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0-only */
+
+/*
+ * Copyright (c) Meta Platforms, Inc. and affiliates.
+ * All rights reserved.
+ *
+ * This source code is licensed under both the BSD-style license (found in the
+ * LICENSE file in the root directory of this source tree) and the GPLv2 (found
+ * in the COPYING file in the root directory of this source tree).
+ * You may select, at your option, one of the above-listed licenses.
+ */
+
+#ifndef ZSTD_COMPRESS_LITERALS_H
+#define ZSTD_COMPRESS_LITERALS_H
+
+#include "zstd_compress_internal.h" /* ZSTD_hufCTables_t, ZSTD_minGain() */
+
+
+size_t ZSTD_noCompressLiterals (void* dst, size_t dstCapacity, const void* src, size_t srcSize);
+
+/* ZSTD_compressRleLiteralsBlock() :
+ * Conditions :
+ * - All bytes in @src are identical
+ * - dstCapacity >= 4 */
+size_t ZSTD_compressRleLiteralsBlock (void* dst, size_t dstCapacity, const void* src, size_t srcSize);
+
+/* ZSTD_compressLiterals():
+ * @entropyWorkspace: must be aligned on 4-bytes boundaries
+ * @entropyWorkspaceSize : must be >= HUF_WORKSPACE_SIZE
+ * @suspectUncompressible: sampling checks, to potentially skip huffman coding
+ */
+size_t ZSTD_compressLiterals (void* dst, size_t dstCapacity,
+                        const void* src, size_t srcSize,
+                              void* entropyWorkspace, size_t entropyWorkspaceSize,
+                        const ZSTD_hufCTables_t* prevHuf,
+                              ZSTD_hufCTables_t* nextHuf,
+                              ZSTD_strategy strategy, int disableLiteralCompression,
+                              int suspectUncompressible,
+                              int bmi2);
+
+#endif /* ZSTD_COMPRESS_LITERALS_H */
diff --git a/src/commonlib/bsd/zstd/compress/zstd_compress_sequences.c b/src/commonlib/bsd/zstd/compress/zstd_compress_sequences.c
new file mode 100644
index 0000000000..46b43b5bc9
--- /dev/null
+++ b/src/commonlib/bsd/zstd/compress/zstd_compress_sequences.c
@@ -0,0 +1,444 @@
+/* SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0-only */
+
+/*
+ * Copyright (c) Meta Platforms, Inc. and affiliates.
+ * All rights reserved.
+ *
+ * This source code is licensed under both the BSD-style license (found in the
+ * LICENSE file in the root directory of this source tree) and the GPLv2 (found
+ * in the COPYING file in the root directory of this source tree).
+ * You may select, at your option, one of the above-listed licenses.
+ */
+
+ /*-*************************************
+ *  Dependencies
+ ***************************************/
+#include "zstd_compress_sequences.h"
+
+/**
+ * -log2(x / 256) lookup table for x in [0, 256).
+ * If x == 0: Return 0
+ * Else: Return floor(-log2(x / 256) * 256)
+ */
+static unsigned const kInverseProbabilityLog256[256] = {
+    0,    2048, 1792, 1642, 1536, 1453, 1386, 1329, 1280, 1236, 1197, 1162,
+    1130, 1100, 1073, 1047, 1024, 1001, 980,  960,  941,  923,  906,  889,
+    874,  859,  844,  830,  817,  804,  791,  779,  768,  756,  745,  734,
+    724,  714,  704,  694,  685,  676,  667,  658,  650,  642,  633,  626,
+    618,  610,  603,  595,  588,  581,  574,  567,  561,  554,  548,  542,
+    535,  529,  523,  517,  512,  506,  500,  495,  489,  484,  478,  473,
+    468,  463,  458,  453,  448,  443,  438,  434,  429,  424,  420,  415,
+    411,  407,  402,  398,  394,  390,  386,  382,  377,  373,  370,  366,
+    362,  358,  354,  350,  347,  343,  339,  336,  332,  329,  325,  322,
+    318,  315,  311,  308,  305,  302,  298,  295,  292,  289,  286,  282,
+    279,  276,  273,  270,  267,  264,  261,  258,  256,  253,  250,  247,
+    244,  241,  239,  236,  233,  230,  228,  225,  222,  220,  217,  215,
+    212,  209,  207,  204,  202,  199,  197,  194,  192,  190,  187,  185,
+    182,  180,  178,  175,  173,  171,  168,  166,  164,  162,  159,  157,
+    155,  153,  151,  149,  146,  144,  142,  140,  138,  136,  134,  132,
+    130,  128,  126,  123,  121,  119,  117,  115,  114,  112,  110,  108,
+    106,  104,  102,  100,  98,   96,   94,   93,   91,   89,   87,   85,
+    83,   82,   80,   78,   76,   74,   73,   71,   69,   67,   66,   64,
+    62,   61,   59,   57,   55,   54,   52,   50,   49,   47,   46,   44,
+    42,   41,   39,   37,   36,   34,   33,   31,   30,   28,   26,   25,
+    23,   22,   20,   19,   17,   16,   14,   13,   11,   10,   8,    7,
+    5,    4,    2,    1,
+};
+
+static unsigned ZSTD_getFSEMaxSymbolValue(FSE_CTable const* ctable) {
+  void const* ptr = ctable;
+  U16 const* u16ptr = (U16 const*)ptr;
+  U32 const maxSymbolValue = MEM_read16(u16ptr + 1);
+  return maxSymbolValue;
+}
+
+/**
+ * Returns true if we should use ncount=-1 else we should
+ * use ncount=1 for low probability symbols instead.
+ */
+static unsigned ZSTD_useLowProbCount(size_t const nbSeq)
+{
+    /* Heuristic: This should cover most blocks <= 16K and
+     * start to fade out after 16K to about 32K depending on
+     * compressibility.
+     */
+    return nbSeq >= 2048;
+}
+
+/**
+ * Returns the cost in bytes of encoding the normalized count header.
+ * Returns an error if any of the helper functions return an error.
+ */
+static size_t ZSTD_NCountCost(unsigned const* count, unsigned const max,
+                              size_t const nbSeq, unsigned const FSELog)
+{
+    BYTE wksp[FSE_NCOUNTBOUND];
+    S16 norm[MaxSeq + 1];
+    const U32 tableLog = FSE_optimalTableLog(FSELog, nbSeq, max);
+    FORWARD_IF_ERROR(FSE_normalizeCount(norm, tableLog, count, nbSeq, max, ZSTD_useLowProbCount(nbSeq)), "");
+    return FSE_writeNCount(wksp, sizeof(wksp), norm, max, tableLog);
+}
+
+/**
+ * Returns the cost in bits of encoding the distribution described by count
+ * using the entropy bound.
+ */
+static size_t ZSTD_entropyCost(unsigned const* count, unsigned const max, size_t const total)
+{
+    unsigned cost = 0;
+    unsigned s;
+
+    assert(total > 0);
+    for (s = 0; s <= max; ++s) {
+        unsigned norm = (unsigned)((256 * count[s]) / total);
+        if (count[s] != 0 && norm == 0)
+            norm = 1;
+        assert(count[s] < total);
+        cost += count[s] * kInverseProbabilityLog256[norm];
+    }
+    return cost >> 8;
+}
+
+/**
+ * Returns the cost in bits of encoding the distribution in count using ctable.
+ * Returns an error if ctable cannot represent all the symbols in count.
+ */
+size_t ZSTD_fseBitCost(
+    FSE_CTable const* ctable,
+    unsigned const* count,
+    unsigned const max)
+{
+    unsigned const kAccuracyLog = 8;
+    size_t cost = 0;
+    unsigned s;
+    FSE_CState_t cstate;
+    FSE_initCState(&cstate, ctable);
+    if (ZSTD_getFSEMaxSymbolValue(ctable) < max) {
+        DEBUGLOG(5, "Repeat FSE_CTable has maxSymbolValue %u < %u",
+                    ZSTD_getFSEMaxSymbolValue(ctable), max);
+        return ERROR(GENERIC);
+    }
+    for (s = 0; s <= max; ++s) {
+        unsigned const tableLog = cstate.stateLog;
+        unsigned const badCost = (tableLog + 1) << kAccuracyLog;
+        unsigned const bitCost = FSE_bitCost(cstate.symbolTT, tableLog, s, kAccuracyLog);
+        if (count[s] == 0)
+            continue;
+        if (bitCost >= badCost) {
+            DEBUGLOG(5, "Repeat FSE_CTable has Prob[%u] == 0", s);
+            return ERROR(GENERIC);
+        }
+        cost += (size_t)count[s] * bitCost;
+    }
+    return cost >> kAccuracyLog;
+}
+
+/**
+ * Returns the cost in bits of encoding the distribution in count using the
+ * table described by norm. The max symbol support by norm is assumed >= max.
+ * norm must be valid for every symbol with non-zero probability in count.
+ */
+size_t ZSTD_crossEntropyCost(short const* norm, unsigned accuracyLog,
+                             unsigned const* count, unsigned const max)
+{
+    unsigned const shift = 8 - accuracyLog;
+    size_t cost = 0;
+    unsigned s;
+    assert(accuracyLog <= 8);
+    for (s = 0; s <= max; ++s) {
+        unsigned const normAcc = (norm[s] != -1) ? (unsigned)norm[s] : 1;
+        unsigned const norm256 = normAcc << shift;
+        assert(norm256 > 0);
+        assert(norm256 < 256);
+        cost += count[s] * kInverseProbabilityLog256[norm256];
+    }
+    return cost >> 8;
+}
+
+SymbolEncodingType_e
+ZSTD_selectEncodingType(
+        FSE_repeat* repeatMode, unsigned const* count, unsigned const max,
+        size_t const mostFrequent, size_t nbSeq, unsigned const FSELog,
+        FSE_CTable const* prevCTable,
+        short const* defaultNorm, U32 defaultNormLog,
+        ZSTD_DefaultPolicy_e const isDefaultAllowed,
+        ZSTD_strategy const strategy)
+{
+    ZSTD_STATIC_ASSERT(ZSTD_defaultDisallowed == 0 && ZSTD_defaultAllowed != 0);
+    if (mostFrequent == nbSeq) {
+        *repeatMode = FSE_repeat_none;
+        if (isDefaultAllowed && nbSeq <= 2) {
+            /* Prefer set_basic over set_rle when there are 2 or fewer symbols,
+             * since RLE uses 1 byte, but set_basic uses 5-6 bits per symbol.
+             * If basic encoding isn't possible, always choose RLE.
+             */
+            DEBUGLOG(5, "Selected set_basic");
+            return set_basic;
+        }
+        DEBUGLOG(5, "Selected set_rle");
+        return set_rle;
+    }
+    if (strategy < ZSTD_lazy) {
+        if (isDefaultAllowed) {
+            size_t const staticFse_nbSeq_max = 1000;
+            size_t const mult = 10 - strategy;
+            size_t const baseLog = 3;
+            size_t const dynamicFse_nbSeq_min = (((size_t)1 << defaultNormLog) * mult) >> baseLog;  /* 28-36 for offset, 56-72 for lengths */
+            assert(defaultNormLog >= 5 && defaultNormLog <= 6);  /* xx_DEFAULTNORMLOG */
+            assert(mult <= 9 && mult >= 7);
+            if ( (*repeatMode == FSE_repeat_valid)
+              && (nbSeq < staticFse_nbSeq_max) ) {
+                DEBUGLOG(5, "Selected set_repeat");
+                return set_repeat;
+            }
+            if ( (nbSeq < dynamicFse_nbSeq_min)
+              || (mostFrequent < (nbSeq >> (defaultNormLog-1))) ) {
+                DEBUGLOG(5, "Selected set_basic");
+                /* The format allows default tables to be repeated, but it isn't useful.
+                 * When using simple heuristics to select encoding type, we don't want
+                 * to confuse these tables with dictionaries. When running more careful
+                 * analysis, we don't need to waste time checking both repeating tables
+                 * and default tables.
+                 */
+                *repeatMode = FSE_repeat_none;
+                return set_basic;
+            }
+        }
+    } else {
+        size_t const basicCost = isDefaultAllowed ? ZSTD_crossEntropyCost(defaultNorm, defaultNormLog, count, max) : ERROR(GENERIC);
+        size_t const repeatCost = *repeatMode != FSE_repeat_none ? ZSTD_fseBitCost(prevCTable, count, max) : ERROR(GENERIC);
+        size_t const NCountCost = ZSTD_NCountCost(count, max, nbSeq, FSELog);
+        size_t const compressedCost = (NCountCost << 3) + ZSTD_entropyCost(count, max, nbSeq);
+
+        if (isDefaultAllowed) {
+            assert(!ZSTD_isError(basicCost));
+            assert(!(*repeatMode == FSE_repeat_valid && ZSTD_isError(repeatCost)));
+        }
+        assert(!ZSTD_isError(NCountCost));
+        assert(compressedCost < ERROR(maxCode));
+        DEBUGLOG(5, "Estimated bit costs: basic=%u\trepeat=%u\tcompressed=%u",
+                    (unsigned)basicCost, (unsigned)repeatCost, (unsigned)compressedCost);
+        if (basicCost <= repeatCost && basicCost <= compressedCost) {
+            DEBUGLOG(5, "Selected set_basic");
+            assert(isDefaultAllowed);
+            *repeatMode = FSE_repeat_none;
+            return set_basic;
+        }
+        if (repeatCost <= compressedCost) {
+            DEBUGLOG(5, "Selected set_repeat");
+            assert(!ZSTD_isError(repeatCost));
+            return set_repeat;
+        }
+        assert(compressedCost < basicCost && compressedCost < repeatCost);
+    }
+    DEBUGLOG(5, "Selected set_compressed");
+    *repeatMode = FSE_repeat_check;
+    return set_compressed;
+}
+
+typedef struct {
+    S16 norm[MaxSeq + 1];
+    U32 wksp[FSE_BUILD_CTABLE_WORKSPACE_SIZE_U32(MaxSeq, MaxFSELog)];
+} ZSTD_BuildCTableWksp;
+
+size_t
+ZSTD_buildCTable(void* dst, size_t dstCapacity,
+                FSE_CTable* nextCTable, U32 FSELog, SymbolEncodingType_e type,
+                unsigned* count, U32 max,
+                const BYTE* codeTable, size_t nbSeq,
+                const S16* defaultNorm, U32 defaultNormLog, U32 defaultMax,
+                const FSE_CTable* prevCTable, size_t prevCTableSize,
+                void* entropyWorkspace, size_t entropyWorkspaceSize)
+{
+    BYTE* op = (BYTE*)dst;
+    const BYTE* const oend = op + dstCapacity;
+    DEBUGLOG(6, "ZSTD_buildCTable (dstCapacity=%u)", (unsigned)dstCapacity);
+
+    switch (type) {
+    case set_rle:
+        FORWARD_IF_ERROR(FSE_buildCTable_rle(nextCTable, (BYTE)max), "");
+        RETURN_ERROR_IF(dstCapacity==0, dstSize_tooSmall, "not enough space");
+        *op = codeTable[0];
+        return 1;
+    case set_repeat:
+        ZSTD_memcpy(nextCTable, prevCTable, prevCTableSize);
+        return 0;
+    case set_basic:
+        FORWARD_IF_ERROR(FSE_buildCTable_wksp(nextCTable, defaultNorm, defaultMax, defaultNormLog, entropyWorkspace, entropyWorkspaceSize), "");  /* note : could be pre-calculated */
+        return 0;
+    case set_compressed: {
+        ZSTD_BuildCTableWksp* wksp = (ZSTD_BuildCTableWksp*)entropyWorkspace;
+        size_t nbSeq_1 = nbSeq;
+        const U32 tableLog = FSE_optimalTableLog(FSELog, nbSeq, max);
+        if (count[codeTable[nbSeq-1]] > 1) {
+            count[codeTable[nbSeq-1]]--;
+            nbSeq_1--;
+        }
+        assert(nbSeq_1 > 1);
+        assert(entropyWorkspaceSize >= sizeof(ZSTD_BuildCTableWksp));
+        (void)entropyWorkspaceSize;
+        FORWARD_IF_ERROR(FSE_normalizeCount(wksp->norm, tableLog, count, nbSeq_1, max, ZSTD_useLowProbCount(nbSeq_1)), "FSE_normalizeCount failed");
+        assert(oend >= op);
+        {   size_t const NCountSize = FSE_writeNCount(op, (size_t)(oend - op), wksp->norm, max, tableLog);   /* overflow protected */
+            FORWARD_IF_ERROR(NCountSize, "FSE_writeNCount failed");
+            FORWARD_IF_ERROR(FSE_buildCTable_wksp(nextCTable, wksp->norm, max, tableLog, wksp->wksp, sizeof(wksp->wksp)), "FSE_buildCTable_wksp failed");
+            return NCountSize;
+        }
+    }
+    default: assert(0); RETURN_ERROR(GENERIC, "impossible to reach");
+    }
+}
+
+FORCE_INLINE_TEMPLATE size_t
+ZSTD_encodeSequences_body(
+            void* dst, size_t dstCapacity,
+            FSE_CTable const* CTable_MatchLength, BYTE const* mlCodeTable,
+            FSE_CTable const* CTable_OffsetBits, BYTE const* ofCodeTable,
+            FSE_CTable const* CTable_LitLength, BYTE const* llCodeTable,
+            SeqDef const* sequences, size_t nbSeq, int longOffsets)
+{
+    BIT_CStream_t blockStream;
+    FSE_CState_t  stateMatchLength;
+    FSE_CState_t  stateOffsetBits;
+    FSE_CState_t  stateLitLength;
+
+    RETURN_ERROR_IF(
+        ERR_isError(BIT_initCStream(&blockStream, dst, dstCapacity)),
+        dstSize_tooSmall, "not enough space remaining");
+    DEBUGLOG(6, "available space for bitstream : %i  (dstCapacity=%u)",
+                (int)(blockStream.endPtr - blockStream.startPtr),
+                (unsigned)dstCapacity);
+
+    /* first symbols */
+    FSE_initCState2(&stateMatchLength, CTable_MatchLength, mlCodeTable[nbSeq-1]);
+    FSE_initCState2(&stateOffsetBits,  CTable_OffsetBits,  ofCodeTable[nbSeq-1]);
+    FSE_initCState2(&stateLitLength,   CTable_LitLength,   llCodeTable[nbSeq-1]);
+    BIT_addBits(&blockStream, sequences[nbSeq-1].litLength, LL_bits[llCodeTable[nbSeq-1]]);
+    if (MEM_32bits()) BIT_flushBits(&blockStream);
+    BIT_addBits(&blockStream, sequences[nbSeq-1].mlBase, ML_bits[mlCodeTable[nbSeq-1]]);
+    if (MEM_32bits()) BIT_flushBits(&blockStream);
+    if (longOffsets) {
+        U32 const ofBits = ofCodeTable[nbSeq-1];
+        unsigned const extraBits = ofBits - MIN(ofBits, STREAM_ACCUMULATOR_MIN-1);
+        if (extraBits) {
+            BIT_addBits(&blockStream, sequences[nbSeq-1].offBase, extraBits);
+            BIT_flushBits(&blockStream);
+        }
+        BIT_addBits(&blockStream, sequences[nbSeq-1].offBase >> extraBits,
+                    ofBits - extraBits);
+    } else {
+        BIT_addBits(&blockStream, sequences[nbSeq-1].offBase, ofCodeTable[nbSeq-1]);
+    }
+    BIT_flushBits(&blockStream);
+
+    {   size_t n;
+        for (n=nbSeq-2 ; n<nbSeq ; n--) {      /* intentional underflow */
+            BYTE const llCode = llCodeTable[n];
+            BYTE const ofCode = ofCodeTable[n];
+            BYTE const mlCode = mlCodeTable[n];
+            U32  const llBits = LL_bits[llCode];
+            U32  const ofBits = ofCode;
+            U32  const mlBits = ML_bits[mlCode];
+            DEBUGLOG(6, "encoding: litlen:%2u - matchlen:%2u - offCode:%7u",
+                        (unsigned)sequences[n].litLength,
+                        (unsigned)sequences[n].mlBase + MINMATCH,
+                        (unsigned)sequences[n].offBase);
+                                                                            /* 32b*/  /* 64b*/
+                                                                            /* (7)*/  /* (7)*/
+            FSE_encodeSymbol(&blockStream, &stateOffsetBits, ofCode);       /* 15 */  /* 15 */
+            FSE_encodeSymbol(&blockStream, &stateMatchLength, mlCode);      /* 24 */  /* 24 */
+            if (MEM_32bits()) BIT_flushBits(&blockStream);                  /* (7)*/
+            FSE_encodeSymbol(&blockStream, &stateLitLength, llCode);        /* 16 */  /* 33 */
+            if (MEM_32bits() || (ofBits+mlBits+llBits >= 64-7-(LLFSELog+MLFSELog+OffFSELog)))
+                BIT_flushBits(&blockStream);                                /* (7)*/
+            BIT_addBits(&blockStream, sequences[n].litLength, llBits);
+            if (MEM_32bits() && ((llBits+mlBits)>24)) BIT_flushBits(&blockStream);
+            BIT_addBits(&blockStream, sequences[n].mlBase, mlBits);
+            if (MEM_32bits() || (ofBits+mlBits+llBits > 56)) BIT_flushBits(&blockStream);
+            if (longOffsets) {
+                unsigned const extraBits = ofBits - MIN(ofBits, STREAM_ACCUMULATOR_MIN-1);
+                if (extraBits) {
+                    BIT_addBits(&blockStream, sequences[n].offBase, extraBits);
+                    BIT_flushBits(&blockStream);                            /* (7)*/
+                }
+                BIT_addBits(&blockStream, sequences[n].offBase >> extraBits,
+                            ofBits - extraBits);                            /* 31 */
+            } else {
+                BIT_addBits(&blockStream, sequences[n].offBase, ofBits);     /* 31 */
+            }
+            BIT_flushBits(&blockStream);                                    /* (7)*/
+            DEBUGLOG(7, "remaining space : %i", (int)(blockStream.endPtr - blockStream.ptr));
+    }   }
+
+    DEBUGLOG(6, "ZSTD_encodeSequences: flushing ML state with %u bits", stateMatchLength.stateLog);
+    FSE_flushCState(&blockStream, &stateMatchLength);
+    DEBUGLOG(6, "ZSTD_encodeSequences: flushing Off state with %u bits", stateOffsetBits.stateLog);
+    FSE_flushCState(&blockStream, &stateOffsetBits);
+    DEBUGLOG(6, "ZSTD_encodeSequences: flushing LL state with %u bits", stateLitLength.stateLog);
+    FSE_flushCState(&blockStream, &stateLitLength);
+
+    {   size_t const streamSize = BIT_closeCStream(&blockStream);
+        RETURN_ERROR_IF(streamSize==0, dstSize_tooSmall, "not enough space");
+        return streamSize;
+    }
+}
+
+static size_t
+ZSTD_encodeSequences_default(
+            void* dst, size_t dstCapacity,
+            FSE_CTable const* CTable_MatchLength, BYTE const* mlCodeTable,
+            FSE_CTable const* CTable_OffsetBits, BYTE const* ofCodeTable,
+            FSE_CTable const* CTable_LitLength, BYTE const* llCodeTable,
+            SeqDef const* sequences, size_t nbSeq, int longOffsets)
+{
+    return ZSTD_encodeSequences_body(dst, dstCapacity,
+                                    CTable_MatchLength, mlCodeTable,
+                                    CTable_OffsetBits, ofCodeTable,
+                                    CTable_LitLength, llCodeTable,
+                                    sequences, nbSeq, longOffsets);
+}
+
+
+#if DYNAMIC_BMI2
+
+static BMI2_TARGET_ATTRIBUTE size_t
+ZSTD_encodeSequences_bmi2(
+            void* dst, size_t dstCapacity,
+            FSE_CTable const* CTable_MatchLength, BYTE const* mlCodeTable,
+            FSE_CTable const* CTable_OffsetBits, BYTE const* ofCodeTable,
+            FSE_CTable const* CTable_LitLength, BYTE const* llCodeTable,
+            SeqDef const* sequences, size_t nbSeq, int longOffsets)
+{
+    return ZSTD_encodeSequences_body(dst, dstCapacity,
+                                    CTable_MatchLength, mlCodeTable,
+                                    CTable_OffsetBits, ofCodeTable,
+                                    CTable_LitLength, llCodeTable,
+                                    sequences, nbSeq, longOffsets);
+}
+
+#endif
+
+size_t ZSTD_encodeSequences(
+            void* dst, size_t dstCapacity,
+            FSE_CTable const* CTable_MatchLength, BYTE const* mlCodeTable,
+            FSE_CTable const* CTable_OffsetBits, BYTE const* ofCodeTable,
+            FSE_CTable const* CTable_LitLength, BYTE const* llCodeTable,
+            SeqDef const* sequences, size_t nbSeq, int longOffsets, int bmi2)
+{
+    DEBUGLOG(5, "ZSTD_encodeSequences: dstCapacity = %u", (unsigned)dstCapacity);
+#if DYNAMIC_BMI2
+    if (bmi2) {
+        return ZSTD_encodeSequences_bmi2(dst, dstCapacity,
+                                         CTable_MatchLength, mlCodeTable,
+                                         CTable_OffsetBits, ofCodeTable,
+                                         CTable_LitLength, llCodeTable,
+                                         sequences, nbSeq, longOffsets);
+    }
+#endif
+    (void)bmi2;
+    return ZSTD_encodeSequences_default(dst, dstCapacity,
+                                        CTable_MatchLength, mlCodeTable,
+                                        CTable_OffsetBits, ofCodeTable,
+                                        CTable_LitLength, llCodeTable,
+                                        sequences, nbSeq, longOffsets);
+}
diff --git a/src/commonlib/bsd/zstd/compress/zstd_compress_sequences.h b/src/commonlib/bsd/zstd/compress/zstd_compress_sequences.h
new file mode 100644
index 0000000000..bcc1da97e3
--- /dev/null
+++ b/src/commonlib/bsd/zstd/compress/zstd_compress_sequences.h
@@ -0,0 +1,57 @@
+/* SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0-only */
+
+/*
+ * Copyright (c) Meta Platforms, Inc. and affiliates.
+ * All rights reserved.
+ *
+ * This source code is licensed under both the BSD-style license (found in the
+ * LICENSE file in the root directory of this source tree) and the GPLv2 (found
+ * in the COPYING file in the root directory of this source tree).
+ * You may select, at your option, one of the above-listed licenses.
+ */
+
+#ifndef ZSTD_COMPRESS_SEQUENCES_H
+#define ZSTD_COMPRESS_SEQUENCES_H
+
+#include "zstd_compress_internal.h" /* SeqDef */
+#include "../common/fse.h" /* FSE_repeat, FSE_CTable */
+#include "../common/zstd_internal.h" /* SymbolEncodingType_e, ZSTD_strategy */
+
+typedef enum {
+    ZSTD_defaultDisallowed = 0,
+    ZSTD_defaultAllowed = 1
+} ZSTD_DefaultPolicy_e;
+
+SymbolEncodingType_e
+ZSTD_selectEncodingType(
+        FSE_repeat* repeatMode, unsigned const* count, unsigned const max,
+        size_t const mostFrequent, size_t nbSeq, unsigned const FSELog,
+        FSE_CTable const* prevCTable,
+        short const* defaultNorm, U32 defaultNormLog,
+        ZSTD_DefaultPolicy_e const isDefaultAllowed,
+        ZSTD_strategy const strategy);
+
+size_t
+ZSTD_buildCTable(void* dst, size_t dstCapacity,
+                FSE_CTable* nextCTable, U32 FSELog, SymbolEncodingType_e type,
+                unsigned* count, U32 max,
+                const BYTE* codeTable, size_t nbSeq,
+                const S16* defaultNorm, U32 defaultNormLog, U32 defaultMax,
+                const FSE_CTable* prevCTable, size_t prevCTableSize,
+                void* entropyWorkspace, size_t entropyWorkspaceSize);
+
+size_t ZSTD_encodeSequences(
+            void* dst, size_t dstCapacity,
+            FSE_CTable const* CTable_MatchLength, BYTE const* mlCodeTable,
+            FSE_CTable const* CTable_OffsetBits, BYTE const* ofCodeTable,
+            FSE_CTable const* CTable_LitLength, BYTE const* llCodeTable,
+            SeqDef const* sequences, size_t nbSeq, int longOffsets, int bmi2);
+
+size_t ZSTD_fseBitCost(
+    FSE_CTable const* ctable,
+    unsigned const* count,
+    unsigned const max);
+
+size_t ZSTD_crossEntropyCost(short const* norm, unsigned accuracyLog,
+                             unsigned const* count, unsigned const max);
+#endif /* ZSTD_COMPRESS_SEQUENCES_H */
diff --git a/src/commonlib/bsd/zstd/compress/zstd_compress_superblock.c b/src/commonlib/bsd/zstd/compress/zstd_compress_superblock.c
new file mode 100644
index 0000000000..85a2f1c231
--- /dev/null
+++ b/src/commonlib/bsd/zstd/compress/zstd_compress_superblock.c
@@ -0,0 +1,690 @@
+/* SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0-only */
+
+/*
+ * Copyright (c) Meta Platforms, Inc. and affiliates.
+ * All rights reserved.
+ *
+ * This source code is licensed under both the BSD-style license (found in the
+ * LICENSE file in the root directory of this source tree) and the GPLv2 (found
+ * in the COPYING file in the root directory of this source tree).
+ * You may select, at your option, one of the above-listed licenses.
+ */
+
+ /*-*************************************
+ *  Dependencies
+ ***************************************/
+#include "zstd_compress_superblock.h"
+
+#include "../common/zstd_internal.h"  /* ZSTD_getSequenceLength */
+#include "hist.h"                     /* HIST_countFast_wksp */
+#include "zstd_compress_internal.h"   /* ZSTD_[huf|fse|entropy]CTablesMetadata_t */
+#include "zstd_compress_sequences.h"
+#include "zstd_compress_literals.h"
+
+/** ZSTD_compressSubBlock_literal() :
+ *  Compresses literals section for a sub-block.
+ *  When we have to write the Huffman table we will sometimes choose a header
+ *  size larger than necessary. This is because we have to pick the header size
+ *  before we know the table size + compressed size, so we have a bound on the
+ *  table size. If we guessed incorrectly, we fall back to uncompressed literals.
+ *
+ *  We write the header when writeEntropy=1 and set entropyWritten=1 when we succeeded
+ *  in writing the header, otherwise it is set to 0.
+ *
+ *  hufMetadata->hType has literals block type info.
+ *      If it is set_basic, all sub-blocks literals section will be Raw_Literals_Block.
+ *      If it is set_rle, all sub-blocks literals section will be RLE_Literals_Block.
+ *      If it is set_compressed, first sub-block's literals section will be Compressed_Literals_Block
+ *      If it is set_compressed, first sub-block's literals section will be Treeless_Literals_Block
+ *      and the following sub-blocks' literals sections will be Treeless_Literals_Block.
+ *  @return : compressed size of literals section of a sub-block
+ *            Or 0 if unable to compress.
+ *            Or error code */
+static size_t
+ZSTD_compressSubBlock_literal(const HUF_CElt* hufTable,
+                              const ZSTD_hufCTablesMetadata_t* hufMetadata,
+                              const BYTE* literals, size_t litSize,
+                              void* dst, size_t dstSize,
+                              const int bmi2, int writeEntropy, int* entropyWritten)
+{
+    size_t const header = writeEntropy ? 200 : 0;
+    size_t const lhSize = 3 + (litSize >= (1 KB - header)) + (litSize >= (16 KB - header));
+    BYTE* const ostart = (BYTE*)dst;
+    BYTE* const oend = ostart + dstSize;
+    BYTE* op = ostart + lhSize;
+    U32 const singleStream = lhSize == 3;
+    SymbolEncodingType_e hType = writeEntropy ? hufMetadata->hType : set_repeat;
+    size_t cLitSize = 0;
+
+    DEBUGLOG(5, "ZSTD_compressSubBlock_literal (litSize=%zu, lhSize=%zu, writeEntropy=%d)", litSize, lhSize, writeEntropy);
+
+    *entropyWritten = 0;
+    if (litSize == 0 || hufMetadata->hType == set_basic) {
+      DEBUGLOG(5, "ZSTD_compressSubBlock_literal using raw literal");
+      return ZSTD_noCompressLiterals(dst, dstSize, literals, litSize);
+    } else if (hufMetadata->hType == set_rle) {
+      DEBUGLOG(5, "ZSTD_compressSubBlock_literal using rle literal");
+      return ZSTD_compressRleLiteralsBlock(dst, dstSize, literals, litSize);
+    }
+
+    assert(litSize > 0);
+    assert(hufMetadata->hType == set_compressed || hufMetadata->hType == set_repeat);
+
+    if (writeEntropy && hufMetadata->hType == set_compressed) {
+        ZSTD_memcpy(op, hufMetadata->hufDesBuffer, hufMetadata->hufDesSize);
+        op += hufMetadata->hufDesSize;
+        cLitSize += hufMetadata->hufDesSize;
+        DEBUGLOG(5, "ZSTD_compressSubBlock_literal (hSize=%zu)", hufMetadata->hufDesSize);
+    }
+
+    {   int const flags = bmi2 ? HUF_flags_bmi2 : 0;
+        const size_t cSize = singleStream ? HUF_compress1X_usingCTable(op, (size_t)(oend-op), literals, litSize, hufTable, flags)
+                                          : HUF_compress4X_usingCTable(op, (size_t)(oend-op), literals, litSize, hufTable, flags);
+        op += cSize;
+        cLitSize += cSize;
+        if (cSize == 0 || ERR_isError(cSize)) {
+            DEBUGLOG(5, "Failed to write entropy tables %s", ZSTD_getErrorName(cSize));
+            return 0;
+        }
+        /* If we expand and we aren't writing a header then emit uncompressed */
+        if (!writeEntropy && cLitSize >= litSize) {
+            DEBUGLOG(5, "ZSTD_compressSubBlock_literal using raw literal because uncompressible");
+            return ZSTD_noCompressLiterals(dst, dstSize, literals, litSize);
+        }
+        /* If we are writing headers then allow expansion that doesn't change our header size. */
+        if (lhSize < (size_t)(3 + (cLitSize >= 1 KB) + (cLitSize >= 16 KB))) {
+            assert(cLitSize > litSize);
+            DEBUGLOG(5, "Literals expanded beyond allowed header size");
+            return ZSTD_noCompressLiterals(dst, dstSize, literals, litSize);
+        }
+        DEBUGLOG(5, "ZSTD_compressSubBlock_literal (cSize=%zu)", cSize);
+    }
+
+    /* Build header */
+    switch(lhSize)
+    {
+    case 3: /* 2 - 2 - 10 - 10 */
+        {   U32 const lhc = hType + ((U32)(!singleStream) << 2) + ((U32)litSize<<4) + ((U32)cLitSize<<14);
+            MEM_writeLE24(ostart, lhc);
+            break;
+        }
+    case 4: /* 2 - 2 - 14 - 14 */
+        {   U32 const lhc = hType + (2 << 2) + ((U32)litSize<<4) + ((U32)cLitSize<<18);
+            MEM_writeLE32(ostart, lhc);
+            break;
+        }
+    case 5: /* 2 - 2 - 18 - 18 */
+        {   U32 const lhc = hType + (3 << 2) + ((U32)litSize<<4) + ((U32)cLitSize<<22);
+            MEM_writeLE32(ostart, lhc);
+            ostart[4] = (BYTE)(cLitSize >> 10);
+            break;
+        }
+    default:  /* not possible : lhSize is {3,4,5} */
+        assert(0);
+    }
+    *entropyWritten = 1;
+    DEBUGLOG(5, "Compressed literals: %u -> %u", (U32)litSize, (U32)(op-ostart));
+    return (size_t)(op-ostart);
+}
+
+static size_t
+ZSTD_seqDecompressedSize(SeqStore_t const* seqStore,
+                   const SeqDef* sequences, size_t nbSeqs,
+                         size_t litSize, int lastSubBlock)
+{
+    size_t matchLengthSum = 0;
+    size_t litLengthSum = 0;
+    size_t n;
+    for (n=0; n<nbSeqs; n++) {
+        const ZSTD_SequenceLength seqLen = ZSTD_getSequenceLength(seqStore, sequences+n);
+        litLengthSum += seqLen.litLength;
+        matchLengthSum += seqLen.matchLength;
+    }
+    DEBUGLOG(5, "ZSTD_seqDecompressedSize: %u sequences from %p: %u literals + %u matchlength",
+                (unsigned)nbSeqs, (const void*)sequences,
+                (unsigned)litLengthSum, (unsigned)matchLengthSum);
+    if (!lastSubBlock)
+        assert(litLengthSum == litSize);
+    else
+        assert(litLengthSum <= litSize);
+    (void)litLengthSum;
+    return matchLengthSum + litSize;
+}
+
+/** ZSTD_compressSubBlock_sequences() :
+ *  Compresses sequences section for a sub-block.
+ *  fseMetadata->llType, fseMetadata->ofType, and fseMetadata->mlType have
+ *  symbol compression modes for the super-block.
+ *  The first successfully compressed block will have these in its header.
+ *  We set entropyWritten=1 when we succeed in compressing the sequences.
+ *  The following sub-blocks will always have repeat mode.
+ *  @return : compressed size of sequences section of a sub-block
+ *            Or 0 if it is unable to compress
+ *            Or error code. */
+static size_t
+ZSTD_compressSubBlock_sequences(const ZSTD_fseCTables_t* fseTables,
+                                const ZSTD_fseCTablesMetadata_t* fseMetadata,
+                                const SeqDef* sequences, size_t nbSeq,
+                                const BYTE* llCode, const BYTE* mlCode, const BYTE* ofCode,
+                                const ZSTD_CCtx_params* cctxParams,
+                                void* dst, size_t dstCapacity,
+                                const int bmi2, int writeEntropy, int* entropyWritten)
+{
+    const int longOffsets = cctxParams->cParams.windowLog > STREAM_ACCUMULATOR_MIN;
+    BYTE* const ostart = (BYTE*)dst;
+    BYTE* const oend = ostart + dstCapacity;
+    BYTE* op = ostart;
+    BYTE* seqHead;
+
+    DEBUGLOG(5, "ZSTD_compressSubBlock_sequences (nbSeq=%zu, writeEntropy=%d, longOffsets=%d)", nbSeq, writeEntropy, longOffsets);
+
+    *entropyWritten = 0;
+    /* Sequences Header */
+    RETURN_ERROR_IF((oend-op) < 3 /*max nbSeq Size*/ + 1 /*seqHead*/,
+                    dstSize_tooSmall, "");
+    if (nbSeq < 128)
+        *op++ = (BYTE)nbSeq;
+    else if (nbSeq < LONGNBSEQ)
+        op[0] = (BYTE)((nbSeq>>8) + 0x80), op[1] = (BYTE)nbSeq, op+=2;
+    else
+        op[0]=0xFF, MEM_writeLE16(op+1, (U16)(nbSeq - LONGNBSEQ)), op+=3;
+    if (nbSeq==0) {
+        return (size_t)(op - ostart);
+    }
+
+    /* seqHead : flags for FSE encoding type */
+    seqHead = op++;
+
+    DEBUGLOG(5, "ZSTD_compressSubBlock_sequences (seqHeadSize=%u)", (unsigned)(op-ostart));
+
+    if (writeEntropy) {
+        const U32 LLtype = fseMetadata->llType;
+        const U32 Offtype = fseMetadata->ofType;
+        const U32 MLtype = fseMetadata->mlType;
+        DEBUGLOG(5, "ZSTD_compressSubBlock_sequences (fseTablesSize=%zu)", fseMetadata->fseTablesSize);
+        *seqHead = (BYTE)((LLtype<<6) + (Offtype<<4) + (MLtype<<2));
+        ZSTD_memcpy(op, fseMetadata->fseTablesBuffer, fseMetadata->fseTablesSize);
+        op += fseMetadata->fseTablesSize;
+    } else {
+        const U32 repeat = set_repeat;
+        *seqHead = (BYTE)((repeat<<6) + (repeat<<4) + (repeat<<2));
+    }
+
+    {   size_t const bitstreamSize = ZSTD_encodeSequences(
+                                        op, (size_t)(oend - op),
+                                        fseTables->matchlengthCTable, mlCode,
+                                        fseTables->offcodeCTable, ofCode,
+                                        fseTables->litlengthCTable, llCode,
+                                        sequences, nbSeq,
+                                        longOffsets, bmi2);
+        FORWARD_IF_ERROR(bitstreamSize, "ZSTD_encodeSequences failed");
+        op += bitstreamSize;
+        /* zstd versions <= 1.3.4 mistakenly report corruption when
+         * FSE_readNCount() receives a buffer < 4 bytes.
+         * Fixed by https://github.com/facebook/zstd/pull/1146.
+         * This can happen when the last set_compressed table present is 2
+         * bytes and the bitstream is only one byte.
+         * In this exceedingly rare case, we will simply emit an uncompressed
+         * block, since it isn't worth optimizing.
+         */
+#ifndef FUZZING_BUILD_MODE_UNSAFE_FOR_PRODUCTION
+        if (writeEntropy && fseMetadata->lastCountSize && fseMetadata->lastCountSize + bitstreamSize < 4) {
+            /* NCountSize >= 2 && bitstreamSize > 0 ==> lastCountSize == 3 */
+            assert(fseMetadata->lastCountSize + bitstreamSize == 3);
+            DEBUGLOG(5, "Avoiding bug in zstd decoder in versions <= 1.3.4 by "
+                        "emitting an uncompressed block.");
+            return 0;
+        }
+#endif
+        DEBUGLOG(5, "ZSTD_compressSubBlock_sequences (bitstreamSize=%zu)", bitstreamSize);
+    }
+
+    /* zstd versions <= 1.4.0 mistakenly report error when
+     * sequences section body size is less than 3 bytes.
+     * Fixed by https://github.com/facebook/zstd/pull/1664.
+     * This can happen when the previous sequences section block is compressed
+     * with rle mode and the current block's sequences section is compressed
+     * with repeat mode where sequences section body size can be 1 byte.
+     */
+#ifndef FUZZING_BUILD_MODE_UNSAFE_FOR_PRODUCTION
+    if (op-seqHead < 4) {
+        DEBUGLOG(5, "Avoiding bug in zstd decoder in versions <= 1.4.0 by emitting "
+                    "an uncompressed block when sequences are < 4 bytes");
+        return 0;
+    }
+#endif
+
+    *entropyWritten = 1;
+    return (size_t)(op - ostart);
+}
+
+/** ZSTD_compressSubBlock() :
+ *  Compresses a single sub-block.
+ *  @return : compressed size of the sub-block
+ *            Or 0 if it failed to compress. */
+static size_t ZSTD_compressSubBlock(const ZSTD_entropyCTables_t* entropy,
+                                    const ZSTD_entropyCTablesMetadata_t* entropyMetadata,
+                                    const SeqDef* sequences, size_t nbSeq,
+                                    const BYTE* literals, size_t litSize,
+                                    const BYTE* llCode, const BYTE* mlCode, const BYTE* ofCode,
+                                    const ZSTD_CCtx_params* cctxParams,
+                                    void* dst, size_t dstCapacity,
+                                    const int bmi2,
+                                    int writeLitEntropy, int writeSeqEntropy,
+                                    int* litEntropyWritten, int* seqEntropyWritten,
+                                    U32 lastBlock)
+{
+    BYTE* const ostart = (BYTE*)dst;
+    BYTE* const oend = ostart + dstCapacity;
+    BYTE* op = ostart + ZSTD_blockHeaderSize;
+    DEBUGLOG(5, "ZSTD_compressSubBlock (litSize=%zu, nbSeq=%zu, writeLitEntropy=%d, writeSeqEntropy=%d, lastBlock=%d)",
+                litSize, nbSeq, writeLitEntropy, writeSeqEntropy, lastBlock);
+    {   size_t cLitSize = ZSTD_compressSubBlock_literal((const HUF_CElt*)entropy->huf.CTable,
+                                                        &entropyMetadata->hufMetadata, literals, litSize,
+                                                        op, (size_t)(oend-op),
+                                                        bmi2, writeLitEntropy, litEntropyWritten);
+        FORWARD_IF_ERROR(cLitSize, "ZSTD_compressSubBlock_literal failed");
+        if (cLitSize == 0) return 0;
+        op += cLitSize;
+    }
+    {   size_t cSeqSize = ZSTD_compressSubBlock_sequences(&entropy->fse,
+                                                  &entropyMetadata->fseMetadata,
+                                                  sequences, nbSeq,
+                                                  llCode, mlCode, ofCode,
+                                                  cctxParams,
+                                                  op, (size_t)(oend-op),
+                                                  bmi2, writeSeqEntropy, seqEntropyWritten);
+        FORWARD_IF_ERROR(cSeqSize, "ZSTD_compressSubBlock_sequences failed");
+        if (cSeqSize == 0) return 0;
+        op += cSeqSize;
+    }
+    /* Write block header */
+    {   size_t cSize = (size_t)(op-ostart) - ZSTD_blockHeaderSize;
+        U32 const cBlockHeader24 = lastBlock + (((U32)bt_compressed)<<1) + (U32)(cSize << 3);
+        MEM_writeLE24(ostart, cBlockHeader24);
+    }
+    return (size_t)(op-ostart);
+}
+
+static size_t ZSTD_estimateSubBlockSize_literal(const BYTE* literals, size_t litSize,
+                                                const ZSTD_hufCTables_t* huf,
+                                                const ZSTD_hufCTablesMetadata_t* hufMetadata,
+                                                void* workspace, size_t wkspSize,
+                                                int writeEntropy)
+{
+    unsigned* const countWksp = (unsigned*)workspace;
+    unsigned maxSymbolValue = 255;
+    size_t literalSectionHeaderSize = 3; /* Use hard coded size of 3 bytes */
+
+    if (hufMetadata->hType == set_basic) return litSize;
+    else if (hufMetadata->hType == set_rle) return 1;
+    else if (hufMetadata->hType == set_compressed || hufMetadata->hType == set_repeat) {
+        size_t const largest = HIST_count_wksp (countWksp, &maxSymbolValue, (const BYTE*)literals, litSize, workspace, wkspSize);
+        if (ZSTD_isError(largest)) return litSize;
+        {   size_t cLitSizeEstimate = HUF_estimateCompressedSize((const HUF_CElt*)huf->CTable, countWksp, maxSymbolValue);
+            if (writeEntropy) cLitSizeEstimate += hufMetadata->hufDesSize;
+            return cLitSizeEstimate + literalSectionHeaderSize;
+    }   }
+    assert(0); /* impossible */
+    return 0;
+}
+
+static size_t ZSTD_estimateSubBlockSize_symbolType(SymbolEncodingType_e type,
+                        const BYTE* codeTable, unsigned maxCode,
+                        size_t nbSeq, const FSE_CTable* fseCTable,
+                        const U8* additionalBits,
+                        short const* defaultNorm, U32 defaultNormLog, U32 defaultMax,
+                        void* workspace, size_t wkspSize)
+{
+    unsigned* const countWksp = (unsigned*)workspace;
+    const BYTE* ctp = codeTable;
+    const BYTE* const ctStart = ctp;
+    const BYTE* const ctEnd = ctStart + nbSeq;
+    size_t cSymbolTypeSizeEstimateInBits = 0;
+    unsigned max = maxCode;
+
+    HIST_countFast_wksp(countWksp, &max, codeTable, nbSeq, workspace, wkspSize);  /* can't fail */
+    if (type == set_basic) {
+        /* We selected this encoding type, so it must be valid. */
+        assert(max <= defaultMax);
+        cSymbolTypeSizeEstimateInBits = max <= defaultMax
+                ? ZSTD_crossEntropyCost(defaultNorm, defaultNormLog, countWksp, max)
+                : ERROR(GENERIC);
+    } else if (type == set_rle) {
+        cSymbolTypeSizeEstimateInBits = 0;
+    } else if (type == set_compressed || type == set_repeat) {
+        cSymbolTypeSizeEstimateInBits = ZSTD_fseBitCost(fseCTable, countWksp, max);
+    }
+    if (ZSTD_isError(cSymbolTypeSizeEstimateInBits)) return nbSeq * 10;
+    while (ctp < ctEnd) {
+        if (additionalBits) cSymbolTypeSizeEstimateInBits += additionalBits[*ctp];
+        else cSymbolTypeSizeEstimateInBits += *ctp; /* for offset, offset code is also the number of additional bits */
+        ctp++;
+    }
+    return cSymbolTypeSizeEstimateInBits / 8;
+}
+
+static size_t ZSTD_estimateSubBlockSize_sequences(const BYTE* ofCodeTable,
+                                                  const BYTE* llCodeTable,
+                                                  const BYTE* mlCodeTable,
+                                                  size_t nbSeq,
+                                                  const ZSTD_fseCTables_t* fseTables,
+                                                  const ZSTD_fseCTablesMetadata_t* fseMetadata,
+                                                  void* workspace, size_t wkspSize,
+                                                  int writeEntropy)
+{
+    size_t const sequencesSectionHeaderSize = 3; /* Use hard coded size of 3 bytes */
+    size_t cSeqSizeEstimate = 0;
+    if (nbSeq == 0) return sequencesSectionHeaderSize;
+    cSeqSizeEstimate += ZSTD_estimateSubBlockSize_symbolType(fseMetadata->ofType, ofCodeTable, MaxOff,
+                                         nbSeq, fseTables->offcodeCTable, NULL,
+                                         OF_defaultNorm, OF_defaultNormLog, DefaultMaxOff,
+                                         workspace, wkspSize);
+    cSeqSizeEstimate += ZSTD_estimateSubBlockSize_symbolType(fseMetadata->llType, llCodeTable, MaxLL,
+                                         nbSeq, fseTables->litlengthCTable, LL_bits,
+                                         LL_defaultNorm, LL_defaultNormLog, MaxLL,
+                                         workspace, wkspSize);
+    cSeqSizeEstimate += ZSTD_estimateSubBlockSize_symbolType(fseMetadata->mlType, mlCodeTable, MaxML,
+                                         nbSeq, fseTables->matchlengthCTable, ML_bits,
+                                         ML_defaultNorm, ML_defaultNormLog, MaxML,
+                                         workspace, wkspSize);
+    if (writeEntropy) cSeqSizeEstimate += fseMetadata->fseTablesSize;
+    return cSeqSizeEstimate + sequencesSectionHeaderSize;
+}
+
+typedef struct {
+    size_t estLitSize;
+    size_t estBlockSize;
+} EstimatedBlockSize;
+static EstimatedBlockSize ZSTD_estimateSubBlockSize(const BYTE* literals, size_t litSize,
+                                        const BYTE* ofCodeTable,
+                                        const BYTE* llCodeTable,
+                                        const BYTE* mlCodeTable,
+                                        size_t nbSeq,
+                                        const ZSTD_entropyCTables_t* entropy,
+                                        const ZSTD_entropyCTablesMetadata_t* entropyMetadata,
+                                        void* workspace, size_t wkspSize,
+                                        int writeLitEntropy, int writeSeqEntropy)
+{
+    EstimatedBlockSize ebs;
+    ebs.estLitSize = ZSTD_estimateSubBlockSize_literal(literals, litSize,
+                                                        &entropy->huf, &entropyMetadata->hufMetadata,
+                                                        workspace, wkspSize, writeLitEntropy);
+    ebs.estBlockSize = ZSTD_estimateSubBlockSize_sequences(ofCodeTable, llCodeTable, mlCodeTable,
+                                                         nbSeq, &entropy->fse, &entropyMetadata->fseMetadata,
+                                                         workspace, wkspSize, writeSeqEntropy);
+    ebs.estBlockSize += ebs.estLitSize + ZSTD_blockHeaderSize;
+    return ebs;
+}
+
+static int ZSTD_needSequenceEntropyTables(ZSTD_fseCTablesMetadata_t const* fseMetadata)
+{
+    if (fseMetadata->llType == set_compressed || fseMetadata->llType == set_rle)
+        return 1;
+    if (fseMetadata->mlType == set_compressed || fseMetadata->mlType == set_rle)
+        return 1;
+    if (fseMetadata->ofType == set_compressed || fseMetadata->ofType == set_rle)
+        return 1;
+    return 0;
+}
+
+static size_t countLiterals(SeqStore_t const* seqStore, const SeqDef* sp, size_t seqCount)
+{
+    size_t n, total = 0;
+    assert(sp != NULL);
+    for (n=0; n<seqCount; n++) {
+        total += ZSTD_getSequenceLength(seqStore, sp+n).litLength;
+    }
+    DEBUGLOG(6, "countLiterals for %zu sequences from %p => %zu bytes", seqCount, (const void*)sp, total);
+    return total;
+}
+
+#define BYTESCALE 256
+
+static size_t sizeBlockSequences(const SeqDef* sp, size_t nbSeqs,
+                size_t targetBudget, size_t avgLitCost, size_t avgSeqCost,
+                int firstSubBlock)
+{
+    size_t n, budget = 0, inSize=0;
+    /* entropy headers */
+    size_t const headerSize = (size_t)firstSubBlock * 120 * BYTESCALE; /* generous estimate */
+    assert(firstSubBlock==0 || firstSubBlock==1);
+    budget += headerSize;
+
+    /* first sequence => at least one sequence*/
+    budget += sp[0].litLength * avgLitCost + avgSeqCost;
+    if (budget > targetBudget) return 1;
+    inSize = sp[0].litLength + (sp[0].mlBase+MINMATCH);
+
+    /* loop over sequences */
+    for (n=1; n<nbSeqs; n++) {
+        size_t currentCost = sp[n].litLength * avgLitCost + avgSeqCost;
+        budget += currentCost;
+        inSize += sp[n].litLength + (sp[n].mlBase+MINMATCH);
+        /* stop when sub-block budget is reached */
+        if ( (budget > targetBudget)
+            /* though continue to expand until the sub-block is deemed compressible */
+          && (budget < inSize * BYTESCALE) )
+            break;
+    }
+
+    return n;
+}
+
+/** ZSTD_compressSubBlock_multi() :
+ *  Breaks super-block into multiple sub-blocks and compresses them.
+ *  Entropy will be written into the first block.
+ *  The following blocks use repeat_mode to compress.
+ *  Sub-blocks are all compressed, except the last one when beneficial.
+ *  @return : compressed size of the super block (which features multiple ZSTD blocks)
+ *            or 0 if it failed to compress. */
+static size_t ZSTD_compressSubBlock_multi(const SeqStore_t* seqStorePtr,
+                            const ZSTD_compressedBlockState_t* prevCBlock,
+                            ZSTD_compressedBlockState_t* nextCBlock,
+                            const ZSTD_entropyCTablesMetadata_t* entropyMetadata,
+                            const ZSTD_CCtx_params* cctxParams,
+                                  void* dst, size_t dstCapacity,
+                            const void* src, size_t srcSize,
+                            const int bmi2, U32 lastBlock,
+                            void* workspace, size_t wkspSize)
+{
+    const SeqDef* const sstart = seqStorePtr->sequencesStart;
+    const SeqDef* const send = seqStorePtr->sequences;
+    const SeqDef* sp = sstart; /* tracks progresses within seqStorePtr->sequences */
+    size_t const nbSeqs = (size_t)(send - sstart);
+    const BYTE* const lstart = seqStorePtr->litStart;
+    const BYTE* const lend = seqStorePtr->lit;
+    const BYTE* lp = lstart;
+    size_t const nbLiterals = (size_t)(lend - lstart);
+    BYTE const* ip = (BYTE const*)src;
+    BYTE const* const iend = ip + srcSize;
+    BYTE* const ostart = (BYTE*)dst;
+    BYTE* const oend = ostart + dstCapacity;
+    BYTE* op = ostart;
+    const BYTE* llCodePtr = seqStorePtr->llCode;
+    const BYTE* mlCodePtr = seqStorePtr->mlCode;
+    const BYTE* ofCodePtr = seqStorePtr->ofCode;
+    size_t const minTarget = ZSTD_TARGETCBLOCKSIZE_MIN; /* enforce minimum size, to reduce undesirable side effects */
+    size_t const targetCBlockSize = MAX(minTarget, cctxParams->targetCBlockSize);
+    int writeLitEntropy = (entropyMetadata->hufMetadata.hType == set_compressed);
+    int writeSeqEntropy = 1;
+
+    DEBUGLOG(5, "ZSTD_compressSubBlock_multi (srcSize=%u, litSize=%u, nbSeq=%u)",
+               (unsigned)srcSize, (unsigned)(lend-lstart), (unsigned)(send-sstart));
+
+        /* let's start by a general estimation for the full block */
+    if (nbSeqs > 0) {
+        EstimatedBlockSize const ebs =
+                ZSTD_estimateSubBlockSize(lp, nbLiterals,
+                                        ofCodePtr, llCodePtr, mlCodePtr, nbSeqs,
+                                        &nextCBlock->entropy, entropyMetadata,
+                                        workspace, wkspSize,
+                                        writeLitEntropy, writeSeqEntropy);
+        /* quick estimation */
+        size_t const avgLitCost = nbLiterals ? (ebs.estLitSize * BYTESCALE) / nbLiterals : BYTESCALE;
+        size_t const avgSeqCost = ((ebs.estBlockSize - ebs.estLitSize) * BYTESCALE) / nbSeqs;
+        const size_t nbSubBlocks = MAX((ebs.estBlockSize + (targetCBlockSize/2)) / targetCBlockSize, 1);
+        size_t n, avgBlockBudget, blockBudgetSupp=0;
+        avgBlockBudget = (ebs.estBlockSize * BYTESCALE) / nbSubBlocks;
+        DEBUGLOG(5, "estimated fullblock size=%u bytes ; avgLitCost=%.2f ; avgSeqCost=%.2f ; targetCBlockSize=%u, nbSubBlocks=%u ; avgBlockBudget=%.0f bytes",
+                    (unsigned)ebs.estBlockSize, (double)avgLitCost/BYTESCALE, (double)avgSeqCost/BYTESCALE,
+                    (unsigned)targetCBlockSize, (unsigned)nbSubBlocks, (double)avgBlockBudget/BYTESCALE);
+        /* simplification: if estimates states that the full superblock doesn't compress, just bail out immediately
+         * this will result in the production of a single uncompressed block covering @srcSize.*/
+        if (ebs.estBlockSize > srcSize) return 0;
+
+        /* compress and write sub-blocks */
+        assert(nbSubBlocks>0);
+        for (n=0; n < nbSubBlocks-1; n++) {
+            /* determine nb of sequences for current sub-block + nbLiterals from next sequence */
+            size_t const seqCount = sizeBlockSequences(sp, (size_t)(send-sp),
+                                        avgBlockBudget + blockBudgetSupp, avgLitCost, avgSeqCost, n==0);
+            /* if reached last sequence : break to last sub-block (simplification) */
+            assert(seqCount <= (size_t)(send-sp));
+            if (sp + seqCount == send) break;
+            assert(seqCount > 0);
+            /* compress sub-block */
+            {   int litEntropyWritten = 0;
+                int seqEntropyWritten = 0;
+                size_t litSize = countLiterals(seqStorePtr, sp, seqCount);
+                const size_t decompressedSize =
+                        ZSTD_seqDecompressedSize(seqStorePtr, sp, seqCount, litSize, 0);
+                size_t const cSize = ZSTD_compressSubBlock(&nextCBlock->entropy, entropyMetadata,
+                                                sp, seqCount,
+                                                lp, litSize,
+                                                llCodePtr, mlCodePtr, ofCodePtr,
+                                                cctxParams,
+                                                op, (size_t)(oend-op),
+                                                bmi2, writeLitEntropy, writeSeqEntropy,
+                                                &litEntropyWritten, &seqEntropyWritten,
+                                                0);
+                FORWARD_IF_ERROR(cSize, "ZSTD_compressSubBlock failed");
+
+                /* check compressibility, update state components */
+                if (cSize > 0 && cSize < decompressedSize) {
+                    DEBUGLOG(5, "Committed sub-block compressing %u bytes => %u bytes",
+                                (unsigned)decompressedSize, (unsigned)cSize);
+                    assert(ip + decompressedSize <= iend);
+                    ip += decompressedSize;
+                    lp += litSize;
+                    op += cSize;
+                    llCodePtr += seqCount;
+                    mlCodePtr += seqCount;
+                    ofCodePtr += seqCount;
+                    /* Entropy only needs to be written once */
+                    if (litEntropyWritten) {
+                        writeLitEntropy = 0;
+                    }
+                    if (seqEntropyWritten) {
+                        writeSeqEntropy = 0;
+                    }
+                    sp += seqCount;
+                    blockBudgetSupp = 0;
+            }   }
+            /* otherwise : do not compress yet, coalesce current sub-block with following one */
+        }
+    } /* if (nbSeqs > 0) */
+
+    /* write last block */
+    DEBUGLOG(5, "Generate last sub-block: %u sequences remaining", (unsigned)(send - sp));
+    {   int litEntropyWritten = 0;
+        int seqEntropyWritten = 0;
+        size_t litSize = (size_t)(lend - lp);
+        size_t seqCount = (size_t)(send - sp);
+        const size_t decompressedSize =
+                ZSTD_seqDecompressedSize(seqStorePtr, sp, seqCount, litSize, 1);
+        size_t const cSize = ZSTD_compressSubBlock(&nextCBlock->entropy, entropyMetadata,
+                                            sp, seqCount,
+                                            lp, litSize,
+                                            llCodePtr, mlCodePtr, ofCodePtr,
+                                            cctxParams,
+                                            op, (size_t)(oend-op),
+                                            bmi2, writeLitEntropy, writeSeqEntropy,
+                                            &litEntropyWritten, &seqEntropyWritten,
+                                            lastBlock);
+        FORWARD_IF_ERROR(cSize, "ZSTD_compressSubBlock failed");
+
+        /* update pointers, the nb of literals borrowed from next sequence must be preserved */
+        if (cSize > 0 && cSize < decompressedSize) {
+            DEBUGLOG(5, "Last sub-block compressed %u bytes => %u bytes",
+                        (unsigned)decompressedSize, (unsigned)cSize);
+            assert(ip + decompressedSize <= iend);
+            ip += decompressedSize;
+            lp += litSize;
+            op += cSize;
+            llCodePtr += seqCount;
+            mlCodePtr += seqCount;
+            ofCodePtr += seqCount;
+            /* Entropy only needs to be written once */
+            if (litEntropyWritten) {
+                writeLitEntropy = 0;
+            }
+            if (seqEntropyWritten) {
+                writeSeqEntropy = 0;
+            }
+            sp += seqCount;
+        }
+    }
+
+
+    if (writeLitEntropy) {
+        DEBUGLOG(5, "Literal entropy tables were never written");
+        ZSTD_memcpy(&nextCBlock->entropy.huf, &prevCBlock->entropy.huf, sizeof(prevCBlock->entropy.huf));
+    }
+    if (writeSeqEntropy && ZSTD_needSequenceEntropyTables(&entropyMetadata->fseMetadata)) {
+        /* If we haven't written our entropy tables, then we've violated our contract and
+         * must emit an uncompressed block.
+         */
+        DEBUGLOG(5, "Sequence entropy tables were never written => cancel, emit an uncompressed block");
+        return 0;
+    }
+
+    if (ip < iend) {
+        /* some data left : last part of the block sent uncompressed */
+        size_t const rSize = (size_t)((iend - ip));
+        size_t const cSize = ZSTD_noCompressBlock(op, (size_t)(oend - op), ip, rSize, lastBlock);
+        DEBUGLOG(5, "Generate last uncompressed sub-block of %u bytes", (unsigned)(rSize));
+        FORWARD_IF_ERROR(cSize, "ZSTD_noCompressBlock failed");
+        assert(cSize != 0);
+        op += cSize;
+        /* We have to regenerate the repcodes because we've skipped some sequences */
+        if (sp < send) {
+            const SeqDef* seq;
+            Repcodes_t rep;
+            ZSTD_memcpy(&rep, prevCBlock->rep, sizeof(rep));
+            for (seq = sstart; seq < sp; ++seq) {
+                ZSTD_updateRep(rep.rep, seq->offBase, ZSTD_getSequenceLength(seqStorePtr, seq).litLength == 0);
+            }
+            ZSTD_memcpy(nextCBlock->rep, &rep, sizeof(rep));
+        }
+    }
+
+    DEBUGLOG(5, "ZSTD_compressSubBlock_multi compressed all subBlocks: total compressed size = %u",
+                (unsigned)(op-ostart));
+    return (size_t)(op-ostart);
+}
+
+size_t ZSTD_compressSuperBlock(ZSTD_CCtx* zc,
+                               void* dst, size_t dstCapacity,
+                               const void* src, size_t srcSize,
+                               unsigned lastBlock)
+{
+    ZSTD_entropyCTablesMetadata_t entropyMetadata;
+
+    FORWARD_IF_ERROR(ZSTD_buildBlockEntropyStats(&zc->seqStore,
+          &zc->blockState.prevCBlock->entropy,
+          &zc->blockState.nextCBlock->entropy,
+          &zc->appliedParams,
+          &entropyMetadata,
+          zc->tmpWorkspace, zc->tmpWkspSize /* statically allocated in resetCCtx */), "");
+
+    return ZSTD_compressSubBlock_multi(&zc->seqStore,
+            zc->blockState.prevCBlock,
+            zc->blockState.nextCBlock,
+            &entropyMetadata,
+            &zc->appliedParams,
+            dst, dstCapacity,
+            src, srcSize,
+            zc->bmi2, lastBlock,
+            zc->tmpWorkspace, zc->tmpWkspSize /* statically allocated in resetCCtx */);
+}
diff --git a/src/commonlib/bsd/zstd/compress/zstd_compress_superblock.h b/src/commonlib/bsd/zstd/compress/zstd_compress_superblock.h
new file mode 100644
index 0000000000..a8765694d9
--- /dev/null
+++ b/src/commonlib/bsd/zstd/compress/zstd_compress_superblock.h
@@ -0,0 +1,34 @@
+/* SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0-only */
+
+/*
+ * Copyright (c) Meta Platforms, Inc. and affiliates.
+ * All rights reserved.
+ *
+ * This source code is licensed under both the BSD-style license (found in the
+ * LICENSE file in the root directory of this source tree) and the GPLv2 (found
+ * in the COPYING file in the root directory of this source tree).
+ * You may select, at your option, one of the above-listed licenses.
+ */
+
+#ifndef ZSTD_COMPRESS_ADVANCED_H
+#define ZSTD_COMPRESS_ADVANCED_H
+
+/*-*************************************
+*  Dependencies
+***************************************/
+
+#include "../zstd.h" /* ZSTD_CCtx */
+
+/*-*************************************
+*  Target Compressed Block Size
+***************************************/
+
+/* ZSTD_compressSuperBlock() :
+ * Used to compress a super block when targetCBlockSize is being used.
+ * The given block will be compressed into multiple sub blocks that are around targetCBlockSize. */
+size_t ZSTD_compressSuperBlock(ZSTD_CCtx* zc,
+                               void* dst, size_t dstCapacity,
+                               void const* src, size_t srcSize,
+                               unsigned lastBlock);
+
+#endif /* ZSTD_COMPRESS_ADVANCED_H */
diff --git a/src/commonlib/bsd/zstd/compress/zstd_cwksp.h b/src/commonlib/bsd/zstd/compress/zstd_cwksp.h
new file mode 100644
index 0000000000..bb5d283a22
--- /dev/null
+++ b/src/commonlib/bsd/zstd/compress/zstd_cwksp.h
@@ -0,0 +1,767 @@
+/* SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0-only */
+
+/*
+ * Copyright (c) Meta Platforms, Inc. and affiliates.
+ * All rights reserved.
+ *
+ * This source code is licensed under both the BSD-style license (found in the
+ * LICENSE file in the root directory of this source tree) and the GPLv2 (found
+ * in the COPYING file in the root directory of this source tree).
+ * You may select, at your option, one of the above-listed licenses.
+ */
+
+#ifndef ZSTD_CWKSP_H
+#define ZSTD_CWKSP_H
+
+/*-*************************************
+*  Dependencies
+***************************************/
+#include "../common/allocations.h"  /* ZSTD_customMalloc, ZSTD_customFree */
+#include "../common/zstd_internal.h"
+#include "../common/portability_macros.h"
+#include "../common/zstd_compiler.h" /* ZS2_isPower2 */
+
+/*-*************************************
+*  Constants
+***************************************/
+
+/* Since the workspace is effectively its own little malloc implementation /
+ * arena, when we run under ASAN, we should similarly insert redzones between
+ * each internal element of the workspace, so ASAN will catch overruns that
+ * reach outside an object but that stay inside the workspace.
+ *
+ * This defines the size of that redzone.
+ */
+#ifndef ZSTD_CWKSP_ASAN_REDZONE_SIZE
+#define ZSTD_CWKSP_ASAN_REDZONE_SIZE 128
+#endif
+
+
+/* Set our tables and aligneds to align by 64 bytes */
+#define ZSTD_CWKSP_ALIGNMENT_BYTES 64
+
+/*-*************************************
+*  Structures
+***************************************/
+typedef enum {
+    ZSTD_cwksp_alloc_objects,
+    ZSTD_cwksp_alloc_aligned_init_once,
+    ZSTD_cwksp_alloc_aligned,
+    ZSTD_cwksp_alloc_buffers
+} ZSTD_cwksp_alloc_phase_e;
+
+/**
+ * Used to describe whether the workspace is statically allocated (and will not
+ * necessarily ever be freed), or if it's dynamically allocated and we can
+ * expect a well-formed caller to free this.
+ */
+typedef enum {
+    ZSTD_cwksp_dynamic_alloc,
+    ZSTD_cwksp_static_alloc
+} ZSTD_cwksp_static_alloc_e;
+
+/**
+ * Zstd fits all its internal datastructures into a single continuous buffer,
+ * so that it only needs to perform a single OS allocation (or so that a buffer
+ * can be provided to it and it can perform no allocations at all). This buffer
+ * is called the workspace.
+ *
+ * Several optimizations complicate that process of allocating memory ranges
+ * from this workspace for each internal datastructure:
+ *
+ * - These different internal datastructures have different setup requirements:
+ *
+ *   - The static objects need to be cleared once and can then be trivially
+ *     reused for each compression.
+ *
+ *   - Various buffers don't need to be initialized at all--they are always
+ *     written into before they're read.
+ *
+ *   - The matchstate tables have a unique requirement that they don't need
+ *     their memory to be totally cleared, but they do need the memory to have
+ *     some bound, i.e., a guarantee that all values in the memory they've been
+ *     allocated is less than some maximum value (which is the starting value
+ *     for the indices that they will then use for compression). When this
+ *     guarantee is provided to them, they can use the memory without any setup
+ *     work. When it can't, they have to clear the area.
+ *
+ * - These buffers also have different alignment requirements.
+ *
+ * - We would like to reuse the objects in the workspace for multiple
+ *   compressions without having to perform any expensive reallocation or
+ *   reinitialization work.
+ *
+ * - We would like to be able to efficiently reuse the workspace across
+ *   multiple compressions **even when the compression parameters change** and
+ *   we need to resize some of the objects (where possible).
+ *
+ * To attempt to manage this buffer, given these constraints, the ZSTD_cwksp
+ * abstraction was created. It works as follows:
+ *
+ * Workspace Layout:
+ *
+ * [                        ... workspace ...                           ]
+ * [objects][tables ->] free space [<- buffers][<- aligned][<- init once]
+ *
+ * The various objects that live in the workspace are divided into the
+ * following categories, and are allocated separately:
+ *
+ * - Static objects: this is optionally the enclosing ZSTD_CCtx or ZSTD_CDict,
+ *   so that literally everything fits in a single buffer. Note: if present,
+ *   this must be the first object in the workspace, since ZSTD_customFree{CCtx,
+ *   CDict}() rely on a pointer comparison to see whether one or two frees are
+ *   required.
+ *
+ * - Fixed size objects: these are fixed-size, fixed-count objects that are
+ *   nonetheless "dynamically" allocated in the workspace so that we can
+ *   control how they're initialized separately from the broader ZSTD_CCtx.
+ *   Examples:
+ *   - Entropy Workspace
+ *   - 2 x ZSTD_compressedBlockState_t
+ *   - CDict dictionary contents
+ *
+ * - Tables: these are any of several different datastructures (hash tables,
+ *   chain tables, binary trees) that all respect a common format: they are
+ *   uint32_t arrays, all of whose values are between 0 and (nextSrc - base).
+ *   Their sizes depend on the cparams. These tables are 64-byte aligned.
+ *
+ * - Init once: these buffers require to be initialized at least once before
+ *   use. They should be used when we want to skip memory initialization
+ *   while not triggering memory checkers (like Valgrind) when reading from
+ *   from this memory without writing to it first.
+ *   These buffers should be used carefully as they might contain data
+ *   from previous compressions.
+ *   Buffers are aligned to 64 bytes.
+ *
+ * - Aligned: these buffers don't require any initialization before they're
+ *   used. The user of the buffer should make sure they write into a buffer
+ *   location before reading from it.
+ *   Buffers are aligned to 64 bytes.
+ *
+ * - Buffers: these buffers are used for various purposes that don't require
+ *   any alignment or initialization before they're used. This means they can
+ *   be moved around at no cost for a new compression.
+ *
+ * Allocating Memory:
+ *
+ * The various types of objects must be allocated in order, so they can be
+ * correctly packed into the workspace buffer. That order is:
+ *
+ * 1. Objects
+ * 2. Init once / Tables
+ * 3. Aligned / Tables
+ * 4. Buffers / Tables
+ *
+ * Attempts to reserve objects of different types out of order will fail.
+ */
+typedef struct {
+    void* workspace;
+    void* workspaceEnd;
+
+    void* objectEnd;
+    void* tableEnd;
+    void* tableValidEnd;
+    void* allocStart;
+    void* initOnceStart;
+
+    BYTE allocFailed;
+    int workspaceOversizedDuration;
+    ZSTD_cwksp_alloc_phase_e phase;
+    ZSTD_cwksp_static_alloc_e isStatic;
+} ZSTD_cwksp;
+
+/*-*************************************
+*  Functions
+***************************************/
+
+MEM_STATIC size_t ZSTD_cwksp_available_space(ZSTD_cwksp* ws);
+MEM_STATIC void*  ZSTD_cwksp_initialAllocStart(ZSTD_cwksp* ws);
+
+MEM_STATIC void ZSTD_cwksp_assert_internal_consistency(ZSTD_cwksp* ws) {
+    (void)ws;
+    assert(ws->workspace <= ws->objectEnd);
+    assert(ws->objectEnd <= ws->tableEnd);
+    assert(ws->objectEnd <= ws->tableValidEnd);
+    assert(ws->tableEnd <= ws->allocStart);
+    assert(ws->tableValidEnd <= ws->allocStart);
+    assert(ws->allocStart <= ws->workspaceEnd);
+    assert(ws->initOnceStart <= ZSTD_cwksp_initialAllocStart(ws));
+    assert(ws->workspace <= ws->initOnceStart);
+#if ZSTD_MEMORY_SANITIZER
+    {
+        intptr_t const offset = __msan_test_shadow(ws->initOnceStart,
+            (U8*)ZSTD_cwksp_initialAllocStart(ws) - (U8*)ws->initOnceStart);
+        (void)offset;
+#if defined(ZSTD_MSAN_PRINT)
+        if(offset!=-1) {
+            __msan_print_shadow((U8*)ws->initOnceStart + offset - 8, 32);
+        }
+#endif
+        assert(offset==-1);
+    };
+#endif
+}
+
+/**
+ * Align must be a power of 2.
+ */
+MEM_STATIC size_t ZSTD_cwksp_align(size_t size, size_t align) {
+    size_t const mask = align - 1;
+    assert(ZSTD_isPower2(align));
+    return (size + mask) & ~mask;
+}
+
+/**
+ * Use this to determine how much space in the workspace we will consume to
+ * allocate this object. (Normally it should be exactly the size of the object,
+ * but under special conditions, like ASAN, where we pad each object, it might
+ * be larger.)
+ *
+ * Since tables aren't currently redzoned, you don't need to call through this
+ * to figure out how much space you need for the matchState tables. Everything
+ * else is though.
+ *
+ * Do not use for sizing aligned buffers. Instead, use ZSTD_cwksp_aligned64_alloc_size().
+ */
+MEM_STATIC size_t ZSTD_cwksp_alloc_size(size_t size) {
+    if (size == 0)
+        return 0;
+#if ZSTD_ADDRESS_SANITIZER && !defined (ZSTD_ASAN_DONT_POISON_WORKSPACE)
+    return size + 2 * ZSTD_CWKSP_ASAN_REDZONE_SIZE;
+#else
+    return size;
+#endif
+}
+
+MEM_STATIC size_t ZSTD_cwksp_aligned_alloc_size(size_t size, size_t alignment) {
+    return ZSTD_cwksp_alloc_size(ZSTD_cwksp_align(size, alignment));
+}
+
+/**
+ * Returns an adjusted alloc size that is the nearest larger multiple of 64 bytes.
+ * Used to determine the number of bytes required for a given "aligned".
+ */
+MEM_STATIC size_t ZSTD_cwksp_aligned64_alloc_size(size_t size) {
+    return ZSTD_cwksp_aligned_alloc_size(size, ZSTD_CWKSP_ALIGNMENT_BYTES);
+}
+
+/**
+ * Returns the amount of additional space the cwksp must allocate
+ * for internal purposes (currently only alignment).
+ */
+MEM_STATIC size_t ZSTD_cwksp_slack_space_required(void) {
+    /* For alignment, the wksp will always allocate an additional 2*ZSTD_CWKSP_ALIGNMENT_BYTES
+     * bytes to align the beginning of tables section and end of buffers;
+     */
+    size_t const slackSpace = ZSTD_CWKSP_ALIGNMENT_BYTES * 2;
+    return slackSpace;
+}
+
+
+/**
+ * Return the number of additional bytes required to align a pointer to the given number of bytes.
+ * alignBytes must be a power of two.
+ */
+MEM_STATIC size_t ZSTD_cwksp_bytes_to_align_ptr(void* ptr, const size_t alignBytes) {
+    size_t const alignBytesMask = alignBytes - 1;
+    size_t const bytes = (alignBytes - ((size_t)ptr & (alignBytesMask))) & alignBytesMask;
+    assert(ZSTD_isPower2(alignBytes));
+    assert(bytes < alignBytes);
+    return bytes;
+}
+
+/**
+ * Returns the initial value for allocStart which is used to determine the position from
+ * which we can allocate from the end of the workspace.
+ */
+MEM_STATIC void*  ZSTD_cwksp_initialAllocStart(ZSTD_cwksp* ws)
+{
+    char* endPtr = (char*)ws->workspaceEnd;
+    assert(ZSTD_isPower2(ZSTD_CWKSP_ALIGNMENT_BYTES));
+    endPtr = endPtr - ((size_t)endPtr % ZSTD_CWKSP_ALIGNMENT_BYTES);
+    return (void*)endPtr;
+}
+
+/**
+ * Internal function. Do not use directly.
+ * Reserves the given number of bytes within the aligned/buffer segment of the wksp,
+ * which counts from the end of the wksp (as opposed to the object/table segment).
+ *
+ * Returns a pointer to the beginning of that space.
+ */
+MEM_STATIC void*
+ZSTD_cwksp_reserve_internal_buffer_space(ZSTD_cwksp* ws, size_t const bytes)
+{
+    void* const alloc = (BYTE*)ws->allocStart - bytes;
+    void* const bottom = ws->tableEnd;
+    DEBUGLOG(5, "cwksp: reserving [0x%p]:%zd bytes; %zd bytes remaining",
+        alloc, bytes, ZSTD_cwksp_available_space(ws) - bytes);
+    ZSTD_cwksp_assert_internal_consistency(ws);
+    assert(alloc >= bottom);
+    if (alloc < bottom) {
+        DEBUGLOG(4, "cwksp: alloc failed!");
+        ws->allocFailed = 1;
+        return NULL;
+    }
+    /* the area is reserved from the end of wksp.
+     * If it overlaps with tableValidEnd, it voids guarantees on values' range */
+    if (alloc < ws->tableValidEnd) {
+        ws->tableValidEnd = alloc;
+    }
+    ws->allocStart = alloc;
+    return alloc;
+}
+
+/**
+ * Moves the cwksp to the next phase, and does any necessary allocations.
+ * cwksp initialization must necessarily go through each phase in order.
+ * Returns a 0 on success, or zstd error
+ */
+MEM_STATIC size_t
+ZSTD_cwksp_internal_advance_phase(ZSTD_cwksp* ws, ZSTD_cwksp_alloc_phase_e phase)
+{
+    assert(phase >= ws->phase);
+    if (phase > ws->phase) {
+        /* Going from allocating objects to allocating initOnce / tables */
+        if (ws->phase < ZSTD_cwksp_alloc_aligned_init_once &&
+            phase >= ZSTD_cwksp_alloc_aligned_init_once) {
+            ws->tableValidEnd = ws->objectEnd;
+            ws->initOnceStart = ZSTD_cwksp_initialAllocStart(ws);
+
+            {   /* Align the start of the tables to 64 bytes. Use [0, 63] bytes */
+                void *const alloc = ws->objectEnd;
+                size_t const bytesToAlign = ZSTD_cwksp_bytes_to_align_ptr(alloc, ZSTD_CWKSP_ALIGNMENT_BYTES);
+                void *const objectEnd = (BYTE *) alloc + bytesToAlign;
+                DEBUGLOG(5, "reserving table alignment addtl space: %zu", bytesToAlign);
+                RETURN_ERROR_IF(objectEnd > ws->workspaceEnd, memory_allocation,
+                                "table phase - alignment initial allocation failed!");
+                ws->objectEnd = objectEnd;
+                ws->tableEnd = objectEnd;  /* table area starts being empty */
+                if (ws->tableValidEnd < ws->tableEnd) {
+                    ws->tableValidEnd = ws->tableEnd;
+                }
+            }
+        }
+        ws->phase = phase;
+        ZSTD_cwksp_assert_internal_consistency(ws);
+    }
+    return 0;
+}
+
+/**
+ * Returns whether this object/buffer/etc was allocated in this workspace.
+ */
+MEM_STATIC int ZSTD_cwksp_owns_buffer(const ZSTD_cwksp* ws, const void* ptr)
+{
+    return (ptr != NULL) && (ws->workspace <= ptr) && (ptr < ws->workspaceEnd);
+}
+
+/**
+ * Internal function. Do not use directly.
+ */
+MEM_STATIC void*
+ZSTD_cwksp_reserve_internal(ZSTD_cwksp* ws, size_t bytes, ZSTD_cwksp_alloc_phase_e phase)
+{
+    void* alloc;
+    if (ZSTD_isError(ZSTD_cwksp_internal_advance_phase(ws, phase)) || bytes == 0) {
+        return NULL;
+    }
+
+#if ZSTD_ADDRESS_SANITIZER && !defined (ZSTD_ASAN_DONT_POISON_WORKSPACE)
+    /* over-reserve space */
+    bytes += 2 * ZSTD_CWKSP_ASAN_REDZONE_SIZE;
+#endif
+
+    alloc = ZSTD_cwksp_reserve_internal_buffer_space(ws, bytes);
+
+#if ZSTD_ADDRESS_SANITIZER && !defined (ZSTD_ASAN_DONT_POISON_WORKSPACE)
+    /* Move alloc so there's ZSTD_CWKSP_ASAN_REDZONE_SIZE unused space on
+     * either size. */
+    if (alloc) {
+        alloc = (BYTE *)alloc + ZSTD_CWKSP_ASAN_REDZONE_SIZE;
+        if (ws->isStatic == ZSTD_cwksp_dynamic_alloc) {
+            /* We need to keep the redzone poisoned while unpoisoning the bytes that
+             * are actually allocated. */
+            __asan_unpoison_memory_region(alloc, bytes - 2 * ZSTD_CWKSP_ASAN_REDZONE_SIZE);
+        }
+    }
+#endif
+
+    return alloc;
+}
+
+/**
+ * Reserves and returns unaligned memory.
+ */
+MEM_STATIC BYTE* ZSTD_cwksp_reserve_buffer(ZSTD_cwksp* ws, size_t bytes)
+{
+    return (BYTE*)ZSTD_cwksp_reserve_internal(ws, bytes, ZSTD_cwksp_alloc_buffers);
+}
+
+/**
+ * Reserves and returns memory sized on and aligned on ZSTD_CWKSP_ALIGNMENT_BYTES (64 bytes).
+ * This memory has been initialized at least once in the past.
+ * This doesn't mean it has been initialized this time, and it might contain data from previous
+ * operations.
+ * The main usage is for algorithms that might need read access into uninitialized memory.
+ * The algorithm must maintain safety under these conditions and must make sure it doesn't
+ * leak any of the past data (directly or in side channels).
+ */
+MEM_STATIC void* ZSTD_cwksp_reserve_aligned_init_once(ZSTD_cwksp* ws, size_t bytes)
+{
+    size_t const alignedBytes = ZSTD_cwksp_align(bytes, ZSTD_CWKSP_ALIGNMENT_BYTES);
+    void* ptr = ZSTD_cwksp_reserve_internal(ws, alignedBytes, ZSTD_cwksp_alloc_aligned_init_once);
+    assert(((size_t)ptr & (ZSTD_CWKSP_ALIGNMENT_BYTES-1)) == 0);
+    if(ptr && ptr < ws->initOnceStart) {
+        /* We assume the memory following the current allocation is either:
+         * 1. Not usable as initOnce memory (end of workspace)
+         * 2. Another initOnce buffer that has been allocated before (and so was previously memset)
+         * 3. An ASAN redzone, in which case we don't want to write on it
+         * For these reasons it should be fine to not explicitly zero every byte up to ws->initOnceStart.
+         * Note that we assume here that MSAN and ASAN cannot run in the same time. */
+        ZSTD_memset(ptr, 0, MIN((size_t)((U8*)ws->initOnceStart - (U8*)ptr), alignedBytes));
+        ws->initOnceStart = ptr;
+    }
+#if ZSTD_MEMORY_SANITIZER
+    assert(__msan_test_shadow(ptr, bytes) == -1);
+#endif
+    return ptr;
+}
+
+/**
+ * Reserves and returns memory sized on and aligned on ZSTD_CWKSP_ALIGNMENT_BYTES (64 bytes).
+ */
+MEM_STATIC void* ZSTD_cwksp_reserve_aligned64(ZSTD_cwksp* ws, size_t bytes)
+{
+    void* const ptr = ZSTD_cwksp_reserve_internal(ws,
+                        ZSTD_cwksp_align(bytes, ZSTD_CWKSP_ALIGNMENT_BYTES),
+                        ZSTD_cwksp_alloc_aligned);
+    assert(((size_t)ptr & (ZSTD_CWKSP_ALIGNMENT_BYTES-1)) == 0);
+    return ptr;
+}
+
+/**
+ * Aligned on 64 bytes. These buffers have the special property that
+ * their values remain constrained, allowing us to reuse them without
+ * memset()-ing them.
+ */
+MEM_STATIC void* ZSTD_cwksp_reserve_table(ZSTD_cwksp* ws, size_t bytes)
+{
+    const ZSTD_cwksp_alloc_phase_e phase = ZSTD_cwksp_alloc_aligned_init_once;
+    void* alloc;
+    void* end;
+    void* top;
+
+    /* We can only start allocating tables after we are done reserving space for objects at the
+     * start of the workspace */
+    if(ws->phase < phase) {
+        if (ZSTD_isError(ZSTD_cwksp_internal_advance_phase(ws, phase))) {
+            return NULL;
+        }
+    }
+    alloc = ws->tableEnd;
+    end = (BYTE *)alloc + bytes;
+    top = ws->allocStart;
+
+    DEBUGLOG(5, "cwksp: reserving %p table %zd bytes, %zd bytes remaining",
+        alloc, bytes, ZSTD_cwksp_available_space(ws) - bytes);
+    assert((bytes & (sizeof(U32)-1)) == 0);
+    ZSTD_cwksp_assert_internal_consistency(ws);
+    assert(end <= top);
+    if (end > top) {
+        DEBUGLOG(4, "cwksp: table alloc failed!");
+        ws->allocFailed = 1;
+        return NULL;
+    }
+    ws->tableEnd = end;
+
+#if ZSTD_ADDRESS_SANITIZER && !defined (ZSTD_ASAN_DONT_POISON_WORKSPACE)
+    if (ws->isStatic == ZSTD_cwksp_dynamic_alloc) {
+        __asan_unpoison_memory_region(alloc, bytes);
+    }
+#endif
+
+    assert((bytes & (ZSTD_CWKSP_ALIGNMENT_BYTES-1)) == 0);
+    assert(((size_t)alloc & (ZSTD_CWKSP_ALIGNMENT_BYTES-1)) == 0);
+    return alloc;
+}
+
+/**
+ * Aligned on sizeof(void*).
+ * Note : should happen only once, at workspace first initialization
+ */
+MEM_STATIC void* ZSTD_cwksp_reserve_object(ZSTD_cwksp* ws, size_t bytes)
+{
+    size_t const roundedBytes = ZSTD_cwksp_align(bytes, sizeof(void*));
+    void* alloc = ws->objectEnd;
+    void* end = (BYTE*)alloc + roundedBytes;
+
+#if ZSTD_ADDRESS_SANITIZER && !defined (ZSTD_ASAN_DONT_POISON_WORKSPACE)
+    /* over-reserve space */
+    end = (BYTE *)end + 2 * ZSTD_CWKSP_ASAN_REDZONE_SIZE;
+#endif
+
+    DEBUGLOG(4,
+        "cwksp: reserving %p object %zd bytes (rounded to %zd), %zd bytes remaining",
+        alloc, bytes, roundedBytes, ZSTD_cwksp_available_space(ws) - roundedBytes);
+    assert((size_t)alloc % ZSTD_ALIGNOF(void*) == 0);
+    assert(bytes % ZSTD_ALIGNOF(void*) == 0);
+    ZSTD_cwksp_assert_internal_consistency(ws);
+    /* we must be in the first phase, no advance is possible */
+    if (ws->phase != ZSTD_cwksp_alloc_objects || end > ws->workspaceEnd) {
+        DEBUGLOG(3, "cwksp: object alloc failed!");
+        ws->allocFailed = 1;
+        return NULL;
+    }
+    ws->objectEnd = end;
+    ws->tableEnd = end;
+    ws->tableValidEnd = end;
+
+#if ZSTD_ADDRESS_SANITIZER && !defined (ZSTD_ASAN_DONT_POISON_WORKSPACE)
+    /* Move alloc so there's ZSTD_CWKSP_ASAN_REDZONE_SIZE unused space on
+     * either size. */
+    alloc = (BYTE*)alloc + ZSTD_CWKSP_ASAN_REDZONE_SIZE;
+    if (ws->isStatic == ZSTD_cwksp_dynamic_alloc) {
+        __asan_unpoison_memory_region(alloc, bytes);
+    }
+#endif
+
+    return alloc;
+}
+/**
+ * with alignment control
+ * Note : should happen only once, at workspace first initialization
+ */
+MEM_STATIC void* ZSTD_cwksp_reserve_object_aligned(ZSTD_cwksp* ws, size_t byteSize, size_t alignment)
+{
+    size_t const mask = alignment - 1;
+    size_t const surplus = (alignment > sizeof(void*)) ? alignment - sizeof(void*) : 0;
+    void* const start = ZSTD_cwksp_reserve_object(ws, byteSize + surplus);
+    if (start == NULL) return NULL;
+    if (surplus == 0) return start;
+    assert(ZSTD_isPower2(alignment));
+    return (void*)(((size_t)start + surplus) & ~mask);
+}
+
+MEM_STATIC void ZSTD_cwksp_mark_tables_dirty(ZSTD_cwksp* ws)
+{
+    DEBUGLOG(4, "cwksp: ZSTD_cwksp_mark_tables_dirty");
+
+#if ZSTD_MEMORY_SANITIZER && !defined (ZSTD_MSAN_DONT_POISON_WORKSPACE)
+    /* To validate that the table reuse logic is sound, and that we don't
+     * access table space that we haven't cleaned, we re-"poison" the table
+     * space every time we mark it dirty.
+     * Since tableValidEnd space and initOnce space may overlap we don't poison
+     * the initOnce portion as it break its promise. This means that this poisoning
+     * check isn't always applied fully. */
+    {
+        size_t size = (BYTE*)ws->tableValidEnd - (BYTE*)ws->objectEnd;
+        assert(__msan_test_shadow(ws->objectEnd, size) == -1);
+        if((BYTE*)ws->tableValidEnd < (BYTE*)ws->initOnceStart) {
+            __msan_poison(ws->objectEnd, size);
+        } else {
+            assert(ws->initOnceStart >= ws->objectEnd);
+            __msan_poison(ws->objectEnd, (BYTE*)ws->initOnceStart - (BYTE*)ws->objectEnd);
+        }
+    }
+#endif
+
+    assert(ws->tableValidEnd >= ws->objectEnd);
+    assert(ws->tableValidEnd <= ws->allocStart);
+    ws->tableValidEnd = ws->objectEnd;
+    ZSTD_cwksp_assert_internal_consistency(ws);
+}
+
+MEM_STATIC void ZSTD_cwksp_mark_tables_clean(ZSTD_cwksp* ws) {
+    DEBUGLOG(4, "cwksp: ZSTD_cwksp_mark_tables_clean");
+    assert(ws->tableValidEnd >= ws->objectEnd);
+    assert(ws->tableValidEnd <= ws->allocStart);
+    if (ws->tableValidEnd < ws->tableEnd) {
+        ws->tableValidEnd = ws->tableEnd;
+    }
+    ZSTD_cwksp_assert_internal_consistency(ws);
+}
+
+/**
+ * Zero the part of the allocated tables not already marked clean.
+ */
+MEM_STATIC void ZSTD_cwksp_clean_tables(ZSTD_cwksp* ws) {
+    DEBUGLOG(4, "cwksp: ZSTD_cwksp_clean_tables");
+    assert(ws->tableValidEnd >= ws->objectEnd);
+    assert(ws->tableValidEnd <= ws->allocStart);
+    if (ws->tableValidEnd < ws->tableEnd) {
+        ZSTD_memset(ws->tableValidEnd, 0, (size_t)((BYTE*)ws->tableEnd - (BYTE*)ws->tableValidEnd));
+    }
+    ZSTD_cwksp_mark_tables_clean(ws);
+}
+
+/**
+ * Invalidates table allocations.
+ * All other allocations remain valid.
+ */
+MEM_STATIC void ZSTD_cwksp_clear_tables(ZSTD_cwksp* ws)
+{
+    DEBUGLOG(4, "cwksp: clearing tables!");
+
+#if ZSTD_ADDRESS_SANITIZER && !defined (ZSTD_ASAN_DONT_POISON_WORKSPACE)
+    /* We don't do this when the workspace is statically allocated, because
+     * when that is the case, we have no capability to hook into the end of the
+     * workspace's lifecycle to unpoison the memory.
+     */
+    if (ws->isStatic == ZSTD_cwksp_dynamic_alloc) {
+        size_t size = (BYTE*)ws->tableValidEnd - (BYTE*)ws->objectEnd;
+        __asan_poison_memory_region(ws->objectEnd, size);
+    }
+#endif
+
+    ws->tableEnd = ws->objectEnd;
+    ZSTD_cwksp_assert_internal_consistency(ws);
+}
+
+/**
+ * Invalidates all buffer, aligned, and table allocations.
+ * Object allocations remain valid.
+ */
+MEM_STATIC void ZSTD_cwksp_clear(ZSTD_cwksp* ws) {
+    DEBUGLOG(4, "cwksp: clearing!");
+
+#if ZSTD_MEMORY_SANITIZER && !defined (ZSTD_MSAN_DONT_POISON_WORKSPACE)
+    /* To validate that the context reuse logic is sound, and that we don't
+     * access stuff that this compression hasn't initialized, we re-"poison"
+     * the workspace except for the areas in which we expect memory reuse
+     * without initialization (objects, valid tables area and init once
+     * memory). */
+    {
+        if((BYTE*)ws->tableValidEnd < (BYTE*)ws->initOnceStart) {
+            size_t size = (BYTE*)ws->initOnceStart - (BYTE*)ws->tableValidEnd;
+            __msan_poison(ws->tableValidEnd, size);
+        }
+    }
+#endif
+
+#if ZSTD_ADDRESS_SANITIZER && !defined (ZSTD_ASAN_DONT_POISON_WORKSPACE)
+    /* We don't do this when the workspace is statically allocated, because
+     * when that is the case, we have no capability to hook into the end of the
+     * workspace's lifecycle to unpoison the memory.
+     */
+    if (ws->isStatic == ZSTD_cwksp_dynamic_alloc) {
+        size_t size = (BYTE*)ws->workspaceEnd - (BYTE*)ws->objectEnd;
+        __asan_poison_memory_region(ws->objectEnd, size);
+    }
+#endif
+
+    ws->tableEnd = ws->objectEnd;
+    ws->allocStart = ZSTD_cwksp_initialAllocStart(ws);
+    ws->allocFailed = 0;
+    if (ws->phase > ZSTD_cwksp_alloc_aligned_init_once) {
+        ws->phase = ZSTD_cwksp_alloc_aligned_init_once;
+    }
+    ZSTD_cwksp_assert_internal_consistency(ws);
+}
+
+MEM_STATIC size_t ZSTD_cwksp_sizeof(const ZSTD_cwksp* ws) {
+    return (size_t)((BYTE*)ws->workspaceEnd - (BYTE*)ws->workspace);
+}
+
+MEM_STATIC size_t ZSTD_cwksp_used(const ZSTD_cwksp* ws) {
+    return (size_t)((BYTE*)ws->tableEnd - (BYTE*)ws->workspace)
+         + (size_t)((BYTE*)ws->workspaceEnd - (BYTE*)ws->allocStart);
+}
+
+/**
+ * The provided workspace takes ownership of the buffer [start, start+size).
+ * Any existing values in the workspace are ignored (the previously managed
+ * buffer, if present, must be separately freed).
+ */
+MEM_STATIC void ZSTD_cwksp_init(ZSTD_cwksp* ws, void* start, size_t size, ZSTD_cwksp_static_alloc_e isStatic) {
+    DEBUGLOG(4, "cwksp: init'ing workspace with %zd bytes", size);
+    assert(((size_t)start & (sizeof(void*)-1)) == 0); /* ensure correct alignment */
+    ws->workspace = start;
+    ws->workspaceEnd = (BYTE*)start + size;
+    ws->objectEnd = ws->workspace;
+    ws->tableValidEnd = ws->objectEnd;
+    ws->initOnceStart = ZSTD_cwksp_initialAllocStart(ws);
+    ws->phase = ZSTD_cwksp_alloc_objects;
+    ws->isStatic = isStatic;
+    ZSTD_cwksp_clear(ws);
+    ws->workspaceOversizedDuration = 0;
+    ZSTD_cwksp_assert_internal_consistency(ws);
+}
+
+MEM_STATIC size_t ZSTD_cwksp_create(ZSTD_cwksp* ws, size_t size, ZSTD_customMem customMem) {
+    void* workspace = ZSTD_customMalloc(size, customMem);
+    DEBUGLOG(4, "cwksp: creating new workspace with %zd bytes", size);
+    RETURN_ERROR_IF(workspace == NULL, memory_allocation, "NULL pointer!");
+    ZSTD_cwksp_init(ws, workspace, size, ZSTD_cwksp_dynamic_alloc);
+    return 0;
+}
+
+MEM_STATIC void ZSTD_cwksp_free(ZSTD_cwksp* ws, ZSTD_customMem customMem) {
+    void *ptr = ws->workspace;
+    DEBUGLOG(4, "cwksp: freeing workspace");
+#if ZSTD_MEMORY_SANITIZER && !defined(ZSTD_MSAN_DONT_POISON_WORKSPACE)
+    if (ptr != NULL && customMem.customFree != NULL) {
+        __msan_unpoison(ptr, ZSTD_cwksp_sizeof(ws));
+    }
+#endif
+    ZSTD_memset(ws, 0, sizeof(ZSTD_cwksp));
+    ZSTD_customFree(ptr, customMem);
+}
+
+/**
+ * Moves the management of a workspace from one cwksp to another. The src cwksp
+ * is left in an invalid state (src must be re-init()'ed before it's used again).
+ */
+MEM_STATIC void ZSTD_cwksp_move(ZSTD_cwksp* dst, ZSTD_cwksp* src) {
+    *dst = *src;
+    ZSTD_memset(src, 0, sizeof(ZSTD_cwksp));
+}
+
+MEM_STATIC int ZSTD_cwksp_reserve_failed(const ZSTD_cwksp* ws) {
+    return ws->allocFailed;
+}
+
+/*-*************************************
+*  Functions Checking Free Space
+***************************************/
+
+/* ZSTD_alignmentSpaceWithinBounds() :
+ * Returns if the estimated space needed for a wksp is within an acceptable limit of the
+ * actual amount of space used.
+ */
+MEM_STATIC int ZSTD_cwksp_estimated_space_within_bounds(const ZSTD_cwksp *const ws, size_t const estimatedSpace) {
+    /* We have an alignment space between objects and tables between tables and buffers, so we can have up to twice
+     * the alignment bytes difference between estimation and actual usage */
+    return (estimatedSpace - ZSTD_cwksp_slack_space_required()) <= ZSTD_cwksp_used(ws) &&
+           ZSTD_cwksp_used(ws) <= estimatedSpace;
+}
+
+
+MEM_STATIC size_t ZSTD_cwksp_available_space(ZSTD_cwksp* ws) {
+    return (size_t)((BYTE*)ws->allocStart - (BYTE*)ws->tableEnd);
+}
+
+MEM_STATIC int ZSTD_cwksp_check_available(ZSTD_cwksp* ws, size_t additionalNeededSpace) {
+    return ZSTD_cwksp_available_space(ws) >= additionalNeededSpace;
+}
+
+MEM_STATIC int ZSTD_cwksp_check_too_large(ZSTD_cwksp* ws, size_t additionalNeededSpace) {
+    return ZSTD_cwksp_check_available(
+        ws, additionalNeededSpace * ZSTD_WORKSPACETOOLARGE_FACTOR);
+}
+
+MEM_STATIC int ZSTD_cwksp_check_wasteful(ZSTD_cwksp* ws, size_t additionalNeededSpace) {
+    return ZSTD_cwksp_check_too_large(ws, additionalNeededSpace)
+        && ws->workspaceOversizedDuration > ZSTD_WORKSPACETOOLARGE_MAXDURATION;
+}
+
+MEM_STATIC void ZSTD_cwksp_bump_oversized_duration(
+        ZSTD_cwksp* ws, size_t additionalNeededSpace) {
+    if (ZSTD_cwksp_check_too_large(ws, additionalNeededSpace)) {
+        ws->workspaceOversizedDuration++;
+    } else {
+        ws->workspaceOversizedDuration = 0;
+    }
+}
+
+#endif /* ZSTD_CWKSP_H */
diff --git a/src/commonlib/bsd/zstd/compress/zstd_double_fast.c b/src/commonlib/bsd/zstd/compress/zstd_double_fast.c
new file mode 100644
index 0000000000..7a2a56b823
--- /dev/null
+++ b/src/commonlib/bsd/zstd/compress/zstd_double_fast.c
@@ -0,0 +1,780 @@
+/* SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0-only */
+
+/*
+ * Copyright (c) Meta Platforms, Inc. and affiliates.
+ * All rights reserved.
+ *
+ * This source code is licensed under both the BSD-style license (found in the
+ * LICENSE file in the root directory of this source tree) and the GPLv2 (found
+ * in the COPYING file in the root directory of this source tree).
+ * You may select, at your option, one of the above-listed licenses.
+ */
+
+#include "zstd_compress_internal.h"
+#include "zstd_double_fast.h"
+
+#ifndef ZSTD_EXCLUDE_DFAST_BLOCK_COMPRESSOR
+
+static
+ZSTD_ALLOW_POINTER_OVERFLOW_ATTR
+void ZSTD_fillDoubleHashTableForCDict(ZSTD_MatchState_t* ms,
+                              void const* end, ZSTD_dictTableLoadMethod_e dtlm)
+{
+    const ZSTD_compressionParameters* const cParams = &ms->cParams;
+    U32* const hashLarge = ms->hashTable;
+    U32  const hBitsL = cParams->hashLog + ZSTD_SHORT_CACHE_TAG_BITS;
+    U32  const mls = cParams->minMatch;
+    U32* const hashSmall = ms->chainTable;
+    U32  const hBitsS = cParams->chainLog + ZSTD_SHORT_CACHE_TAG_BITS;
+    const BYTE* const base = ms->window.base;
+    const BYTE* ip = base + ms->nextToUpdate;
+    const BYTE* const iend = ((const BYTE*)end) - HASH_READ_SIZE;
+    const U32 fastHashFillStep = 3;
+
+    /* Always insert every fastHashFillStep position into the hash tables.
+     * Insert the other positions into the large hash table if their entry
+     * is empty.
+     */
+    for (; ip + fastHashFillStep - 1 <= iend; ip += fastHashFillStep) {
+        U32 const curr = (U32)(ip - base);
+        U32 i;
+        for (i = 0; i < fastHashFillStep; ++i) {
+            size_t const smHashAndTag = ZSTD_hashPtr(ip + i, hBitsS, mls);
+            size_t const lgHashAndTag = ZSTD_hashPtr(ip + i, hBitsL, 8);
+            if (i == 0) {
+                ZSTD_writeTaggedIndex(hashSmall, smHashAndTag, curr + i);
+            }
+            if (i == 0 || hashLarge[lgHashAndTag >> ZSTD_SHORT_CACHE_TAG_BITS] == 0) {
+                ZSTD_writeTaggedIndex(hashLarge, lgHashAndTag, curr + i);
+            }
+            /* Only load extra positions for ZSTD_dtlm_full */
+            if (dtlm == ZSTD_dtlm_fast)
+                break;
+    }   }
+}
+
+static
+ZSTD_ALLOW_POINTER_OVERFLOW_ATTR
+void ZSTD_fillDoubleHashTableForCCtx(ZSTD_MatchState_t* ms,
+                              void const* end, ZSTD_dictTableLoadMethod_e dtlm)
+{
+    const ZSTD_compressionParameters* const cParams = &ms->cParams;
+    U32* const hashLarge = ms->hashTable;
+    U32  const hBitsL = cParams->hashLog;
+    U32  const mls = cParams->minMatch;
+    U32* const hashSmall = ms->chainTable;
+    U32  const hBitsS = cParams->chainLog;
+    const BYTE* const base = ms->window.base;
+    const BYTE* ip = base + ms->nextToUpdate;
+    const BYTE* const iend = ((const BYTE*)end) - HASH_READ_SIZE;
+    const U32 fastHashFillStep = 3;
+
+    /* Always insert every fastHashFillStep position into the hash tables.
+     * Insert the other positions into the large hash table if their entry
+     * is empty.
+     */
+    for (; ip + fastHashFillStep - 1 <= iend; ip += fastHashFillStep) {
+        U32 const curr = (U32)(ip - base);
+        U32 i;
+        for (i = 0; i < fastHashFillStep; ++i) {
+            size_t const smHash = ZSTD_hashPtr(ip + i, hBitsS, mls);
+            size_t const lgHash = ZSTD_hashPtr(ip + i, hBitsL, 8);
+            if (i == 0)
+                hashSmall[smHash] = curr + i;
+            if (i == 0 || hashLarge[lgHash] == 0)
+                hashLarge[lgHash] = curr + i;
+            /* Only load extra positions for ZSTD_dtlm_full */
+            if (dtlm == ZSTD_dtlm_fast)
+                break;
+        }   }
+}
+
+void ZSTD_fillDoubleHashTable(ZSTD_MatchState_t* ms,
+                        const void* const end,
+                        ZSTD_dictTableLoadMethod_e dtlm,
+                        ZSTD_tableFillPurpose_e tfp)
+{
+    if (tfp == ZSTD_tfp_forCDict) {
+        ZSTD_fillDoubleHashTableForCDict(ms, end, dtlm);
+    } else {
+        ZSTD_fillDoubleHashTableForCCtx(ms, end, dtlm);
+    }
+}
+
+
+FORCE_INLINE_TEMPLATE
+ZSTD_ALLOW_POINTER_OVERFLOW_ATTR
+size_t ZSTD_compressBlock_doubleFast_noDict_generic(
+        ZSTD_MatchState_t* ms, SeqStore_t* seqStore, U32 rep[ZSTD_REP_NUM],
+        void const* src, size_t srcSize, U32 const mls /* template */)
+{
+    ZSTD_compressionParameters const* cParams = &ms->cParams;
+    U32* const hashLong = ms->hashTable;
+    const U32 hBitsL = cParams->hashLog;
+    U32* const hashSmall = ms->chainTable;
+    const U32 hBitsS = cParams->chainLog;
+    const BYTE* const base = ms->window.base;
+    const BYTE* const istart = (const BYTE*)src;
+    const BYTE* anchor = istart;
+    const U32 endIndex = (U32)((size_t)(istart - base) + srcSize);
+    /* presumes that, if there is a dictionary, it must be using Attach mode */
+    const U32 prefixLowestIndex = ZSTD_getLowestPrefixIndex(ms, endIndex, cParams->windowLog);
+    const BYTE* const prefixLowest = base + prefixLowestIndex;
+    const BYTE* const iend = istart + srcSize;
+    const BYTE* const ilimit = iend - HASH_READ_SIZE;
+    U32 offset_1=rep[0], offset_2=rep[1];
+    U32 offsetSaved1 = 0, offsetSaved2 = 0;
+
+    size_t mLength;
+    U32 offset;
+    U32 curr;
+
+    /* how many positions to search before increasing step size */
+    const size_t kStepIncr = 1 << kSearchStrength;
+    /* the position at which to increment the step size if no match is found */
+    const BYTE* nextStep;
+    size_t step; /* the current step size */
+
+    size_t hl0; /* the long hash at ip */
+    size_t hl1; /* the long hash at ip1 */
+
+    U32 idxl0; /* the long match index for ip */
+    U32 idxl1; /* the long match index for ip1 */
+
+    const BYTE* matchl0; /* the long match for ip */
+    const BYTE* matchs0; /* the short match for ip */
+    const BYTE* matchl1; /* the long match for ip1 */
+    const BYTE* matchs0_safe; /* matchs0 or safe address */
+
+    const BYTE* ip = istart; /* the current position */
+    const BYTE* ip1; /* the next position */
+    /* Array of ~random data, should have low probability of matching data
+     * we load from here instead of from tables, if matchl0/matchl1 are
+     * invalid indices. Used to avoid unpredictable branches. */
+    const BYTE dummy[] = {0x12,0x34,0x56,0x78,0x9a,0xbc,0xde,0xf0,0xe2,0xb4};
+
+    DEBUGLOG(5, "ZSTD_compressBlock_doubleFast_noDict_generic");
+
+    /* init */
+    ip += ((ip - prefixLowest) == 0);
+    {
+        U32 const current = (U32)(ip - base);
+        U32 const windowLow = ZSTD_getLowestPrefixIndex(ms, current, cParams->windowLog);
+        U32 const maxRep = current - windowLow;
+        if (offset_2 > maxRep) offsetSaved2 = offset_2, offset_2 = 0;
+        if (offset_1 > maxRep) offsetSaved1 = offset_1, offset_1 = 0;
+    }
+
+    /* Outer Loop: one iteration per match found and stored */
+    while (1) {
+        step = 1;
+        nextStep = ip + kStepIncr;
+        ip1 = ip + step;
+
+        if (ip1 > ilimit) {
+            goto _cleanup;
+        }
+
+        hl0 = ZSTD_hashPtr(ip, hBitsL, 8);
+        idxl0 = hashLong[hl0];
+        matchl0 = base + idxl0;
+
+        /* Inner Loop: one iteration per search / position */
+        do {
+            const size_t hs0 = ZSTD_hashPtr(ip, hBitsS, mls);
+            const U32 idxs0 = hashSmall[hs0];
+            curr = (U32)(ip-base);
+            matchs0 = base + idxs0;
+
+            hashLong[hl0] = hashSmall[hs0] = curr;   /* update hash tables */
+
+            /* check noDict repcode */
+            if ((offset_1 > 0) & (MEM_read32(ip+1-offset_1) == MEM_read32(ip+1))) {
+                mLength = ZSTD_count(ip+1+4, ip+1+4-offset_1, iend) + 4;
+                ip++;
+                ZSTD_storeSeq(seqStore, (size_t)(ip-anchor), anchor, iend, REPCODE1_TO_OFFBASE, mLength);
+                goto _match_stored;
+            }
+
+            hl1 = ZSTD_hashPtr(ip1, hBitsL, 8);
+
+            /* idxl0 > prefixLowestIndex is a (somewhat) unpredictable branch.
+             * However expression below complies into conditional move. Since
+             * match is unlikely and we only *branch* on idxl0 > prefixLowestIndex
+             * if there is a match, all branches become predictable. */
+            {   const BYTE*  const matchl0_safe = ZSTD_selectAddr(idxl0, prefixLowestIndex, matchl0, &dummy[0]);
+
+                /* check prefix long match */
+                if (MEM_read64(matchl0_safe) == MEM_read64(ip) && matchl0_safe == matchl0) {
+                    mLength = ZSTD_count(ip+8, matchl0+8, iend) + 8;
+                    offset = (U32)(ip-matchl0);
+                    while (((ip>anchor) & (matchl0>prefixLowest)) && (ip[-1] == matchl0[-1])) { ip--; matchl0--; mLength++; } /* catch up */
+                    goto _match_found;
+            }   }
+
+            idxl1 = hashLong[hl1];
+            matchl1 = base + idxl1;
+
+            /* Same optimization as matchl0 above */
+            matchs0_safe = ZSTD_selectAddr(idxs0, prefixLowestIndex, matchs0, &dummy[0]);
+
+            /* check prefix short match */
+            if(MEM_read32(matchs0_safe) == MEM_read32(ip) && matchs0_safe == matchs0) {
+                  goto _search_next_long;
+            }
+
+            if (ip1 >= nextStep) {
+                PREFETCH_L1(ip1 + 64);
+                PREFETCH_L1(ip1 + 128);
+                step++;
+                nextStep += kStepIncr;
+            }
+            ip = ip1;
+            ip1 += step;
+
+            hl0 = hl1;
+            idxl0 = idxl1;
+            matchl0 = matchl1;
+    #if defined(__aarch64__)
+            PREFETCH_L1(ip+256);
+    #endif
+        } while (ip1 <= ilimit);
+
+_cleanup:
+        /* If offset_1 started invalid (offsetSaved1 != 0) and became valid (offset_1 != 0),
+         * rotate saved offsets. See comment in ZSTD_compressBlock_fast_noDict for more context. */
+        offsetSaved2 = ((offsetSaved1 != 0) && (offset_1 != 0)) ? offsetSaved1 : offsetSaved2;
+
+        /* save reps for next block */
+        rep[0] = offset_1 ? offset_1 : offsetSaved1;
+        rep[1] = offset_2 ? offset_2 : offsetSaved2;
+
+        /* Return the last literals size */
+        return (size_t)(iend - anchor);
+
+_search_next_long:
+
+        /* short match found: let's check for a longer one */
+        mLength = ZSTD_count(ip+4, matchs0+4, iend) + 4;
+        offset = (U32)(ip - matchs0);
+
+        /* check long match at +1 position */
+        if ((idxl1 > prefixLowestIndex) && (MEM_read64(matchl1) == MEM_read64(ip1))) {
+            size_t const l1len = ZSTD_count(ip1+8, matchl1+8, iend) + 8;
+            if (l1len > mLength) {
+                /* use the long match instead */
+                ip = ip1;
+                mLength = l1len;
+                offset = (U32)(ip-matchl1);
+                matchs0 = matchl1;
+            }
+        }
+
+        while (((ip>anchor) & (matchs0>prefixLowest)) && (ip[-1] == matchs0[-1])) { ip--; matchs0--; mLength++; } /* complete backward */
+
+        /* fall-through */
+
+_match_found: /* requires ip, offset, mLength */
+        offset_2 = offset_1;
+        offset_1 = offset;
+
+        if (step < 4) {
+            /* It is unsafe to write this value back to the hashtable when ip1 is
+             * greater than or equal to the new ip we will have after we're done
+             * processing this match. Rather than perform that test directly
+             * (ip1 >= ip + mLength), which costs speed in practice, we do a simpler
+             * more predictable test. The minmatch even if we take a short match is
+             * 4 bytes, so as long as step, the distance between ip and ip1
+             * (initially) is less than 4, we know ip1 < new ip. */
+            hashLong[hl1] = (U32)(ip1 - base);
+        }
+
+        ZSTD_storeSeq(seqStore, (size_t)(ip-anchor), anchor, iend, OFFSET_TO_OFFBASE(offset), mLength);
+
+_match_stored:
+        /* match found */
+        ip += mLength;
+        anchor = ip;
+
+        if (ip <= ilimit) {
+            /* Complementary insertion */
+            /* done after iLimit test, as candidates could be > iend-8 */
+            {   U32 const indexToInsert = curr+2;
+                hashLong[ZSTD_hashPtr(base+indexToInsert, hBitsL, 8)] = indexToInsert;
+                hashLong[ZSTD_hashPtr(ip-2, hBitsL, 8)] = (U32)(ip-2-base);
+                hashSmall[ZSTD_hashPtr(base+indexToInsert, hBitsS, mls)] = indexToInsert;
+                hashSmall[ZSTD_hashPtr(ip-1, hBitsS, mls)] = (U32)(ip-1-base);
+            }
+
+            /* check immediate repcode */
+            while ( (ip <= ilimit)
+                 && ( (offset_2>0)
+                    & (MEM_read32(ip) == MEM_read32(ip - offset_2)) )) {
+                /* store sequence */
+                size_t const rLength = ZSTD_count(ip+4, ip+4-offset_2, iend) + 4;
+                U32 const tmpOff = offset_2; offset_2 = offset_1; offset_1 = tmpOff;  /* swap offset_2 <=> offset_1 */
+                hashSmall[ZSTD_hashPtr(ip, hBitsS, mls)] = (U32)(ip-base);
+                hashLong[ZSTD_hashPtr(ip, hBitsL, 8)] = (U32)(ip-base);
+                ZSTD_storeSeq(seqStore, 0, anchor, iend, REPCODE1_TO_OFFBASE, rLength);
+                ip += rLength;
+                anchor = ip;
+                continue;   /* faster when present ... (?) */
+            }
+        }
+    }
+}
+
+
+FORCE_INLINE_TEMPLATE
+ZSTD_ALLOW_POINTER_OVERFLOW_ATTR
+size_t ZSTD_compressBlock_doubleFast_dictMatchState_generic(
+        ZSTD_MatchState_t* ms, SeqStore_t* seqStore, U32 rep[ZSTD_REP_NUM],
+        void const* src, size_t srcSize,
+        U32 const mls /* template */)
+{
+    ZSTD_compressionParameters const* cParams = &ms->cParams;
+    U32* const hashLong = ms->hashTable;
+    const U32 hBitsL = cParams->hashLog;
+    U32* const hashSmall = ms->chainTable;
+    const U32 hBitsS = cParams->chainLog;
+    const BYTE* const base = ms->window.base;
+    const BYTE* const istart = (const BYTE*)src;
+    const BYTE* ip = istart;
+    const BYTE* anchor = istart;
+    const U32 endIndex = (U32)((size_t)(istart - base) + srcSize);
+    /* presumes that, if there is a dictionary, it must be using Attach mode */
+    const U32 prefixLowestIndex = ZSTD_getLowestPrefixIndex(ms, endIndex, cParams->windowLog);
+    const BYTE* const prefixLowest = base + prefixLowestIndex;
+    const BYTE* const iend = istart + srcSize;
+    const BYTE* const ilimit = iend - HASH_READ_SIZE;
+    U32 offset_1=rep[0], offset_2=rep[1];
+
+    const ZSTD_MatchState_t* const dms = ms->dictMatchState;
+    const ZSTD_compressionParameters* const dictCParams = &dms->cParams;
+    const U32* const dictHashLong  = dms->hashTable;
+    const U32* const dictHashSmall = dms->chainTable;
+    const U32 dictStartIndex       = dms->window.dictLimit;
+    const BYTE* const dictBase     = dms->window.base;
+    const BYTE* const dictStart    = dictBase + dictStartIndex;
+    const BYTE* const dictEnd      = dms->window.nextSrc;
+    const U32 dictIndexDelta       = prefixLowestIndex - (U32)(dictEnd - dictBase);
+    const U32 dictHBitsL           = dictCParams->hashLog + ZSTD_SHORT_CACHE_TAG_BITS;
+    const U32 dictHBitsS           = dictCParams->chainLog + ZSTD_SHORT_CACHE_TAG_BITS;
+    const U32 dictAndPrefixLength  = (U32)((ip - prefixLowest) + (dictEnd - dictStart));
+
+    DEBUGLOG(5, "ZSTD_compressBlock_doubleFast_dictMatchState_generic");
+
+    /* if a dictionary is attached, it must be within window range */
+    assert(ms->window.dictLimit + (1U << cParams->windowLog) >= endIndex);
+
+    if (ms->prefetchCDictTables) {
+        size_t const hashTableBytes = (((size_t)1) << dictCParams->hashLog) * sizeof(U32);
+        size_t const chainTableBytes = (((size_t)1) << dictCParams->chainLog) * sizeof(U32);
+        PREFETCH_AREA(dictHashLong, hashTableBytes);
+        PREFETCH_AREA(dictHashSmall, chainTableBytes);
+    }
+
+    /* init */
+    ip += (dictAndPrefixLength == 0);
+
+    /* dictMatchState repCode checks don't currently handle repCode == 0
+     * disabling. */
+    assert(offset_1 <= dictAndPrefixLength);
+    assert(offset_2 <= dictAndPrefixLength);
+
+    /* Main Search Loop */
+    while (ip < ilimit) {   /* < instead of <=, because repcode check at (ip+1) */
+        size_t mLength;
+        U32 offset;
+        size_t const h2 = ZSTD_hashPtr(ip, hBitsL, 8);
+        size_t const h = ZSTD_hashPtr(ip, hBitsS, mls);
+        size_t const dictHashAndTagL = ZSTD_hashPtr(ip, dictHBitsL, 8);
+        size_t const dictHashAndTagS = ZSTD_hashPtr(ip, dictHBitsS, mls);
+        U32 const dictMatchIndexAndTagL = dictHashLong[dictHashAndTagL >> ZSTD_SHORT_CACHE_TAG_BITS];
+        U32 const dictMatchIndexAndTagS = dictHashSmall[dictHashAndTagS >> ZSTD_SHORT_CACHE_TAG_BITS];
+        int const dictTagsMatchL = ZSTD_comparePackedTags(dictMatchIndexAndTagL, dictHashAndTagL);
+        int const dictTagsMatchS = ZSTD_comparePackedTags(dictMatchIndexAndTagS, dictHashAndTagS);
+        U32 const curr = (U32)(ip-base);
+        U32 const matchIndexL = hashLong[h2];
+        U32 matchIndexS = hashSmall[h];
+        const BYTE* matchLong = base + matchIndexL;
+        const BYTE* match = base + matchIndexS;
+        const U32 repIndex = curr + 1 - offset_1;
+        const BYTE* repMatch = (repIndex < prefixLowestIndex) ?
+                               dictBase + (repIndex - dictIndexDelta) :
+                               base + repIndex;
+        hashLong[h2] = hashSmall[h] = curr;   /* update hash tables */
+
+        /* check repcode */
+        if ((ZSTD_index_overlap_check(prefixLowestIndex, repIndex))
+            && (MEM_read32(repMatch) == MEM_read32(ip+1)) ) {
+            const BYTE* repMatchEnd = repIndex < prefixLowestIndex ? dictEnd : iend;
+            mLength = ZSTD_count_2segments(ip+1+4, repMatch+4, iend, repMatchEnd, prefixLowest) + 4;
+            ip++;
+            ZSTD_storeSeq(seqStore, (size_t)(ip-anchor), anchor, iend, REPCODE1_TO_OFFBASE, mLength);
+            goto _match_stored;
+        }
+
+        if ((matchIndexL >= prefixLowestIndex) && (MEM_read64(matchLong) == MEM_read64(ip))) {
+            /* check prefix long match */
+            mLength = ZSTD_count(ip+8, matchLong+8, iend) + 8;
+            offset = (U32)(ip-matchLong);
+            while (((ip>anchor) & (matchLong>prefixLowest)) && (ip[-1] == matchLong[-1])) { ip--; matchLong--; mLength++; } /* catch up */
+            goto _match_found;
+        } else if (dictTagsMatchL) {
+            /* check dictMatchState long match */
+            U32 const dictMatchIndexL = dictMatchIndexAndTagL >> ZSTD_SHORT_CACHE_TAG_BITS;
+            const BYTE* dictMatchL = dictBase + dictMatchIndexL;
+            assert(dictMatchL < dictEnd);
+
+            if (dictMatchL > dictStart && MEM_read64(dictMatchL) == MEM_read64(ip)) {
+                mLength = ZSTD_count_2segments(ip+8, dictMatchL+8, iend, dictEnd, prefixLowest) + 8;
+                offset = (U32)(curr - dictMatchIndexL - dictIndexDelta);
+                while (((ip>anchor) & (dictMatchL>dictStart)) && (ip[-1] == dictMatchL[-1])) { ip--; dictMatchL--; mLength++; } /* catch up */
+                goto _match_found;
+        }   }
+
+        if (matchIndexS > prefixLowestIndex) {
+            /* short match  candidate */
+            if (MEM_read32(match) == MEM_read32(ip)) {
+                goto _search_next_long;
+            }
+        } else if (dictTagsMatchS) {
+            /* check dictMatchState short match */
+            U32 const dictMatchIndexS = dictMatchIndexAndTagS >> ZSTD_SHORT_CACHE_TAG_BITS;
+            match = dictBase + dictMatchIndexS;
+            matchIndexS = dictMatchIndexS + dictIndexDelta;
+
+            if (match > dictStart && MEM_read32(match) == MEM_read32(ip)) {
+                goto _search_next_long;
+        }   }
+
+        ip += ((ip-anchor) >> kSearchStrength) + 1;
+#if defined(__aarch64__)
+        PREFETCH_L1(ip+256);
+#endif
+        continue;
+
+_search_next_long:
+        {   size_t const hl3 = ZSTD_hashPtr(ip+1, hBitsL, 8);
+            size_t const dictHashAndTagL3 = ZSTD_hashPtr(ip+1, dictHBitsL, 8);
+            U32 const matchIndexL3 = hashLong[hl3];
+            U32 const dictMatchIndexAndTagL3 = dictHashLong[dictHashAndTagL3 >> ZSTD_SHORT_CACHE_TAG_BITS];
+            int const dictTagsMatchL3 = ZSTD_comparePackedTags(dictMatchIndexAndTagL3, dictHashAndTagL3);
+            const BYTE* matchL3 = base + matchIndexL3;
+            hashLong[hl3] = curr + 1;
+
+            /* check prefix long +1 match */
+            if ((matchIndexL3 >= prefixLowestIndex) && (MEM_read64(matchL3) == MEM_read64(ip+1))) {
+                mLength = ZSTD_count(ip+9, matchL3+8, iend) + 8;
+                ip++;
+                offset = (U32)(ip-matchL3);
+                while (((ip>anchor) & (matchL3>prefixLowest)) && (ip[-1] == matchL3[-1])) { ip--; matchL3--; mLength++; } /* catch up */
+                goto _match_found;
+            } else if (dictTagsMatchL3) {
+                /* check dict long +1 match */
+                U32 const dictMatchIndexL3 = dictMatchIndexAndTagL3 >> ZSTD_SHORT_CACHE_TAG_BITS;
+                const BYTE* dictMatchL3 = dictBase + dictMatchIndexL3;
+                assert(dictMatchL3 < dictEnd);
+                if (dictMatchL3 > dictStart && MEM_read64(dictMatchL3) == MEM_read64(ip+1)) {
+                    mLength = ZSTD_count_2segments(ip+1+8, dictMatchL3+8, iend, dictEnd, prefixLowest) + 8;
+                    ip++;
+                    offset = (U32)(curr + 1 - dictMatchIndexL3 - dictIndexDelta);
+                    while (((ip>anchor) & (dictMatchL3>dictStart)) && (ip[-1] == dictMatchL3[-1])) { ip--; dictMatchL3--; mLength++; } /* catch up */
+                    goto _match_found;
+        }   }   }
+
+        /* if no long +1 match, explore the short match we found */
+        if (matchIndexS < prefixLowestIndex) {
+            mLength = ZSTD_count_2segments(ip+4, match+4, iend, dictEnd, prefixLowest) + 4;
+            offset = (U32)(curr - matchIndexS);
+            while (((ip>anchor) & (match>dictStart)) && (ip[-1] == match[-1])) { ip--; match--; mLength++; } /* catch up */
+        } else {
+            mLength = ZSTD_count(ip+4, match+4, iend) + 4;
+            offset = (U32)(ip - match);
+            while (((ip>anchor) & (match>prefixLowest)) && (ip[-1] == match[-1])) { ip--; match--; mLength++; } /* catch up */
+        }
+
+_match_found:
+        offset_2 = offset_1;
+        offset_1 = offset;
+
+        ZSTD_storeSeq(seqStore, (size_t)(ip-anchor), anchor, iend, OFFSET_TO_OFFBASE(offset), mLength);
+
+_match_stored:
+        /* match found */
+        ip += mLength;
+        anchor = ip;
+
+        if (ip <= ilimit) {
+            /* Complementary insertion */
+            /* done after iLimit test, as candidates could be > iend-8 */
+            {   U32 const indexToInsert = curr+2;
+                hashLong[ZSTD_hashPtr(base+indexToInsert, hBitsL, 8)] = indexToInsert;
+                hashLong[ZSTD_hashPtr(ip-2, hBitsL, 8)] = (U32)(ip-2-base);
+                hashSmall[ZSTD_hashPtr(base+indexToInsert, hBitsS, mls)] = indexToInsert;
+                hashSmall[ZSTD_hashPtr(ip-1, hBitsS, mls)] = (U32)(ip-1-base);
+            }
+
+            /* check immediate repcode */
+            while (ip <= ilimit) {
+                U32 const current2 = (U32)(ip-base);
+                U32 const repIndex2 = current2 - offset_2;
+                const BYTE* repMatch2 = repIndex2 < prefixLowestIndex ?
+                        dictBase + repIndex2 - dictIndexDelta :
+                        base + repIndex2;
+                if ( (ZSTD_index_overlap_check(prefixLowestIndex, repIndex2))
+                   && (MEM_read32(repMatch2) == MEM_read32(ip)) ) {
+                    const BYTE* const repEnd2 = repIndex2 < prefixLowestIndex ? dictEnd : iend;
+                    size_t const repLength2 = ZSTD_count_2segments(ip+4, repMatch2+4, iend, repEnd2, prefixLowest) + 4;
+                    U32 tmpOffset = offset_2; offset_2 = offset_1; offset_1 = tmpOffset;   /* swap offset_2 <=> offset_1 */
+                    ZSTD_storeSeq(seqStore, 0, anchor, iend, REPCODE1_TO_OFFBASE, repLength2);
+                    hashSmall[ZSTD_hashPtr(ip, hBitsS, mls)] = current2;
+                    hashLong[ZSTD_hashPtr(ip, hBitsL, 8)] = current2;
+                    ip += repLength2;
+                    anchor = ip;
+                    continue;
+                }
+                break;
+            }
+        }
+    }   /* while (ip < ilimit) */
+
+    /* save reps for next block */
+    rep[0] = offset_1;
+    rep[1] = offset_2;
+
+    /* Return the last literals size */
+    return (size_t)(iend - anchor);
+}
+
+#define ZSTD_GEN_DFAST_FN(dictMode, mls)                                                                 \
+    static size_t ZSTD_compressBlock_doubleFast_##dictMode##_##mls(                                      \
+            ZSTD_MatchState_t* ms, SeqStore_t* seqStore, U32 rep[ZSTD_REP_NUM],                          \
+            void const* src, size_t srcSize)                                                             \
+    {                                                                                                    \
+        return ZSTD_compressBlock_doubleFast_##dictMode##_generic(ms, seqStore, rep, src, srcSize, mls); \
+    }
+
+ZSTD_GEN_DFAST_FN(noDict, 4)
+ZSTD_GEN_DFAST_FN(noDict, 5)
+ZSTD_GEN_DFAST_FN(noDict, 6)
+ZSTD_GEN_DFAST_FN(noDict, 7)
+
+ZSTD_GEN_DFAST_FN(dictMatchState, 4)
+ZSTD_GEN_DFAST_FN(dictMatchState, 5)
+ZSTD_GEN_DFAST_FN(dictMatchState, 6)
+ZSTD_GEN_DFAST_FN(dictMatchState, 7)
+
+
+size_t ZSTD_compressBlock_doubleFast(
+        ZSTD_MatchState_t* ms, SeqStore_t* seqStore, U32 rep[ZSTD_REP_NUM],
+        void const* src, size_t srcSize)
+{
+    const U32 mls = ms->cParams.minMatch;
+    switch(mls)
+    {
+    default: /* includes case 3 */
+    case 4 :
+        return ZSTD_compressBlock_doubleFast_noDict_4(ms, seqStore, rep, src, srcSize);
+    case 5 :
+        return ZSTD_compressBlock_doubleFast_noDict_5(ms, seqStore, rep, src, srcSize);
+    case 6 :
+        return ZSTD_compressBlock_doubleFast_noDict_6(ms, seqStore, rep, src, srcSize);
+    case 7 :
+        return ZSTD_compressBlock_doubleFast_noDict_7(ms, seqStore, rep, src, srcSize);
+    }
+}
+
+
+size_t ZSTD_compressBlock_doubleFast_dictMatchState(
+        ZSTD_MatchState_t* ms, SeqStore_t* seqStore, U32 rep[ZSTD_REP_NUM],
+        void const* src, size_t srcSize)
+{
+    const U32 mls = ms->cParams.minMatch;
+    switch(mls)
+    {
+    default: /* includes case 3 */
+    case 4 :
+        return ZSTD_compressBlock_doubleFast_dictMatchState_4(ms, seqStore, rep, src, srcSize);
+    case 5 :
+        return ZSTD_compressBlock_doubleFast_dictMatchState_5(ms, seqStore, rep, src, srcSize);
+    case 6 :
+        return ZSTD_compressBlock_doubleFast_dictMatchState_6(ms, seqStore, rep, src, srcSize);
+    case 7 :
+        return ZSTD_compressBlock_doubleFast_dictMatchState_7(ms, seqStore, rep, src, srcSize);
+    }
+}
+
+
+static
+ZSTD_ALLOW_POINTER_OVERFLOW_ATTR
+size_t ZSTD_compressBlock_doubleFast_extDict_generic(
+        ZSTD_MatchState_t* ms, SeqStore_t* seqStore, U32 rep[ZSTD_REP_NUM],
+        void const* src, size_t srcSize,
+        U32 const mls /* template */)
+{
+    ZSTD_compressionParameters const* cParams = &ms->cParams;
+    U32* const hashLong = ms->hashTable;
+    U32  const hBitsL = cParams->hashLog;
+    U32* const hashSmall = ms->chainTable;
+    U32  const hBitsS = cParams->chainLog;
+    const BYTE* const istart = (const BYTE*)src;
+    const BYTE* ip = istart;
+    const BYTE* anchor = istart;
+    const BYTE* const iend = istart + srcSize;
+    const BYTE* const ilimit = iend - 8;
+    const BYTE* const base = ms->window.base;
+    const U32   endIndex = (U32)((size_t)(istart - base) + srcSize);
+    const U32   lowLimit = ZSTD_getLowestMatchIndex(ms, endIndex, cParams->windowLog);
+    const U32   dictStartIndex = lowLimit;
+    const U32   dictLimit = ms->window.dictLimit;
+    const U32   prefixStartIndex = (dictLimit > lowLimit) ? dictLimit : lowLimit;
+    const BYTE* const prefixStart = base + prefixStartIndex;
+    const BYTE* const dictBase = ms->window.dictBase;
+    const BYTE* const dictStart = dictBase + dictStartIndex;
+    const BYTE* const dictEnd = dictBase + prefixStartIndex;
+    U32 offset_1=rep[0], offset_2=rep[1];
+
+    DEBUGLOG(5, "ZSTD_compressBlock_doubleFast_extDict_generic (srcSize=%zu)", srcSize);
+
+    /* if extDict is invalidated due to maxDistance, switch to "regular" variant */
+    if (prefixStartIndex == dictStartIndex)
+        return ZSTD_compressBlock_doubleFast(ms, seqStore, rep, src, srcSize);
+
+    /* Search Loop */
+    while (ip < ilimit) {  /* < instead of <=, because (ip+1) */
+        const size_t hSmall = ZSTD_hashPtr(ip, hBitsS, mls);
+        const U32 matchIndex = hashSmall[hSmall];
+        const BYTE* const matchBase = matchIndex < prefixStartIndex ? dictBase : base;
+        const BYTE* match = matchBase + matchIndex;
+
+        const size_t hLong = ZSTD_hashPtr(ip, hBitsL, 8);
+        const U32 matchLongIndex = hashLong[hLong];
+        const BYTE* const matchLongBase = matchLongIndex < prefixStartIndex ? dictBase : base;
+        const BYTE* matchLong = matchLongBase + matchLongIndex;
+
+        const U32 curr = (U32)(ip-base);
+        const U32 repIndex = curr + 1 - offset_1;   /* offset_1 expected <= curr +1 */
+        const BYTE* const repBase = repIndex < prefixStartIndex ? dictBase : base;
+        const BYTE* const repMatch = repBase + repIndex;
+        size_t mLength;
+        hashSmall[hSmall] = hashLong[hLong] = curr;   /* update hash table */
+
+        if (((ZSTD_index_overlap_check(prefixStartIndex, repIndex))
+            & (offset_1 <= curr+1 - dictStartIndex)) /* note: we are searching at curr+1 */
+          && (MEM_read32(repMatch) == MEM_read32(ip+1)) ) {
+            const BYTE* repMatchEnd = repIndex < prefixStartIndex ? dictEnd : iend;
+            mLength = ZSTD_count_2segments(ip+1+4, repMatch+4, iend, repMatchEnd, prefixStart) + 4;
+            ip++;
+            ZSTD_storeSeq(seqStore, (size_t)(ip-anchor), anchor, iend, REPCODE1_TO_OFFBASE, mLength);
+        } else {
+            if ((matchLongIndex > dictStartIndex) && (MEM_read64(matchLong) == MEM_read64(ip))) {
+                const BYTE* const matchEnd = matchLongIndex < prefixStartIndex ? dictEnd : iend;
+                const BYTE* const lowMatchPtr = matchLongIndex < prefixStartIndex ? dictStart : prefixStart;
+                U32 offset;
+                mLength = ZSTD_count_2segments(ip+8, matchLong+8, iend, matchEnd, prefixStart) + 8;
+                offset = curr - matchLongIndex;
+                while (((ip>anchor) & (matchLong>lowMatchPtr)) && (ip[-1] == matchLong[-1])) { ip--; matchLong--; mLength++; }   /* catch up */
+                offset_2 = offset_1;
+                offset_1 = offset;
+                ZSTD_storeSeq(seqStore, (size_t)(ip-anchor), anchor, iend, OFFSET_TO_OFFBASE(offset), mLength);
+
+            } else if ((matchIndex > dictStartIndex) && (MEM_read32(match) == MEM_read32(ip))) {
+                size_t const h3 = ZSTD_hashPtr(ip+1, hBitsL, 8);
+                U32 const matchIndex3 = hashLong[h3];
+                const BYTE* const match3Base = matchIndex3 < prefixStartIndex ? dictBase : base;
+                const BYTE* match3 = match3Base + matchIndex3;
+                U32 offset;
+                hashLong[h3] = curr + 1;
+                if ( (matchIndex3 > dictStartIndex) && (MEM_read64(match3) == MEM_read64(ip+1)) ) {
+                    const BYTE* const matchEnd = matchIndex3 < prefixStartIndex ? dictEnd : iend;
+                    const BYTE* const lowMatchPtr = matchIndex3 < prefixStartIndex ? dictStart : prefixStart;
+                    mLength = ZSTD_count_2segments(ip+9, match3+8, iend, matchEnd, prefixStart) + 8;
+                    ip++;
+                    offset = curr+1 - matchIndex3;
+                    while (((ip>anchor) & (match3>lowMatchPtr)) && (ip[-1] == match3[-1])) { ip--; match3--; mLength++; } /* catch up */
+                } else {
+                    const BYTE* const matchEnd = matchIndex < prefixStartIndex ? dictEnd : iend;
+                    const BYTE* const lowMatchPtr = matchIndex < prefixStartIndex ? dictStart : prefixStart;
+                    mLength = ZSTD_count_2segments(ip+4, match+4, iend, matchEnd, prefixStart) + 4;
+                    offset = curr - matchIndex;
+                    while (((ip>anchor) & (match>lowMatchPtr)) && (ip[-1] == match[-1])) { ip--; match--; mLength++; }   /* catch up */
+                }
+                offset_2 = offset_1;
+                offset_1 = offset;
+                ZSTD_storeSeq(seqStore, (size_t)(ip-anchor), anchor, iend, OFFSET_TO_OFFBASE(offset), mLength);
+
+            } else {
+                ip += ((ip-anchor) >> kSearchStrength) + 1;
+                continue;
+        }   }
+
+        /* move to next sequence start */
+        ip += mLength;
+        anchor = ip;
+
+        if (ip <= ilimit) {
+            /* Complementary insertion */
+            /* done after iLimit test, as candidates could be > iend-8 */
+            {   U32 const indexToInsert = curr+2;
+                hashLong[ZSTD_hashPtr(base+indexToInsert, hBitsL, 8)] = indexToInsert;
+                hashLong[ZSTD_hashPtr(ip-2, hBitsL, 8)] = (U32)(ip-2-base);
+                hashSmall[ZSTD_hashPtr(base+indexToInsert, hBitsS, mls)] = indexToInsert;
+                hashSmall[ZSTD_hashPtr(ip-1, hBitsS, mls)] = (U32)(ip-1-base);
+            }
+
+            /* check immediate repcode */
+            while (ip <= ilimit) {
+                U32 const current2 = (U32)(ip-base);
+                U32 const repIndex2 = current2 - offset_2;
+                const BYTE* repMatch2 = repIndex2 < prefixStartIndex ? dictBase + repIndex2 : base + repIndex2;
+                if ( ((ZSTD_index_overlap_check(prefixStartIndex, repIndex2))
+                    & (offset_2 <= current2 - dictStartIndex))
+                  && (MEM_read32(repMatch2) == MEM_read32(ip)) ) {
+                    const BYTE* const repEnd2 = repIndex2 < prefixStartIndex ? dictEnd : iend;
+                    size_t const repLength2 = ZSTD_count_2segments(ip+4, repMatch2+4, iend, repEnd2, prefixStart) + 4;
+                    U32 const tmpOffset = offset_2; offset_2 = offset_1; offset_1 = tmpOffset;   /* swap offset_2 <=> offset_1 */
+                    ZSTD_storeSeq(seqStore, 0, anchor, iend, REPCODE1_TO_OFFBASE, repLength2);
+                    hashSmall[ZSTD_hashPtr(ip, hBitsS, mls)] = current2;
+                    hashLong[ZSTD_hashPtr(ip, hBitsL, 8)] = current2;
+                    ip += repLength2;
+                    anchor = ip;
+                    continue;
+                }
+                break;
+    }   }   }
+
+    /* save reps for next block */
+    rep[0] = offset_1;
+    rep[1] = offset_2;
+
+    /* Return the last literals size */
+    return (size_t)(iend - anchor);
+}
+
+ZSTD_GEN_DFAST_FN(extDict, 4)
+ZSTD_GEN_DFAST_FN(extDict, 5)
+ZSTD_GEN_DFAST_FN(extDict, 6)
+ZSTD_GEN_DFAST_FN(extDict, 7)
+
+size_t ZSTD_compressBlock_doubleFast_extDict(
+        ZSTD_MatchState_t* ms, SeqStore_t* seqStore, U32 rep[ZSTD_REP_NUM],
+        void const* src, size_t srcSize)
+{
+    U32 const mls = ms->cParams.minMatch;
+    switch(mls)
+    {
+    default: /* includes case 3 */
+    case 4 :
+        return ZSTD_compressBlock_doubleFast_extDict_4(ms, seqStore, rep, src, srcSize);
+    case 5 :
+        return ZSTD_compressBlock_doubleFast_extDict_5(ms, seqStore, rep, src, srcSize);
+    case 6 :
+        return ZSTD_compressBlock_doubleFast_extDict_6(ms, seqStore, rep, src, srcSize);
+    case 7 :
+        return ZSTD_compressBlock_doubleFast_extDict_7(ms, seqStore, rep, src, srcSize);
+    }
+}
+
+#endif /* ZSTD_EXCLUDE_DFAST_BLOCK_COMPRESSOR */
diff --git a/src/commonlib/bsd/zstd/compress/zstd_double_fast.h b/src/commonlib/bsd/zstd/compress/zstd_double_fast.h
new file mode 100644
index 0000000000..73c5e710c8
--- /dev/null
+++ b/src/commonlib/bsd/zstd/compress/zstd_double_fast.h
@@ -0,0 +1,44 @@
+/* SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0-only */
+
+/*
+ * Copyright (c) Meta Platforms, Inc. and affiliates.
+ * All rights reserved.
+ *
+ * This source code is licensed under both the BSD-style license (found in the
+ * LICENSE file in the root directory of this source tree) and the GPLv2 (found
+ * in the COPYING file in the root directory of this source tree).
+ * You may select, at your option, one of the above-listed licenses.
+ */
+
+#ifndef ZSTD_DOUBLE_FAST_H
+#define ZSTD_DOUBLE_FAST_H
+
+#include "../common/mem.h"      /* U32 */
+#include "zstd_compress_internal.h"     /* ZSTD_CCtx, size_t */
+
+#ifndef ZSTD_EXCLUDE_DFAST_BLOCK_COMPRESSOR
+
+void ZSTD_fillDoubleHashTable(ZSTD_MatchState_t* ms,
+                              void const* end, ZSTD_dictTableLoadMethod_e dtlm,
+                              ZSTD_tableFillPurpose_e tfp);
+
+size_t ZSTD_compressBlock_doubleFast(
+        ZSTD_MatchState_t* ms, SeqStore_t* seqStore, U32 rep[ZSTD_REP_NUM],
+        void const* src, size_t srcSize);
+size_t ZSTD_compressBlock_doubleFast_dictMatchState(
+        ZSTD_MatchState_t* ms, SeqStore_t* seqStore, U32 rep[ZSTD_REP_NUM],
+        void const* src, size_t srcSize);
+size_t ZSTD_compressBlock_doubleFast_extDict(
+        ZSTD_MatchState_t* ms, SeqStore_t* seqStore, U32 rep[ZSTD_REP_NUM],
+        void const* src, size_t srcSize);
+
+#define ZSTD_COMPRESSBLOCK_DOUBLEFAST ZSTD_compressBlock_doubleFast
+#define ZSTD_COMPRESSBLOCK_DOUBLEFAST_DICTMATCHSTATE ZSTD_compressBlock_doubleFast_dictMatchState
+#define ZSTD_COMPRESSBLOCK_DOUBLEFAST_EXTDICT ZSTD_compressBlock_doubleFast_extDict
+#else
+#define ZSTD_COMPRESSBLOCK_DOUBLEFAST NULL
+#define ZSTD_COMPRESSBLOCK_DOUBLEFAST_DICTMATCHSTATE NULL
+#define ZSTD_COMPRESSBLOCK_DOUBLEFAST_EXTDICT NULL
+#endif /* ZSTD_EXCLUDE_DFAST_BLOCK_COMPRESSOR */
+
+#endif /* ZSTD_DOUBLE_FAST_H */
diff --git a/src/commonlib/bsd/zstd/compress/zstd_fast.c b/src/commonlib/bsd/zstd/compress/zstd_fast.c
new file mode 100644
index 0000000000..1cc9de5dbd
--- /dev/null
+++ b/src/commonlib/bsd/zstd/compress/zstd_fast.c
@@ -0,0 +1,987 @@
+/* SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0-only */
+
+/*
+ * Copyright (c) Meta Platforms, Inc. and affiliates.
+ * All rights reserved.
+ *
+ * This source code is licensed under both the BSD-style license (found in the
+ * LICENSE file in the root directory of this source tree) and the GPLv2 (found
+ * in the COPYING file in the root directory of this source tree).
+ * You may select, at your option, one of the above-listed licenses.
+ */
+
+#include "zstd_compress_internal.h"  /* ZSTD_hashPtr, ZSTD_count, ZSTD_storeSeq */
+#include "zstd_fast.h"
+
+static
+ZSTD_ALLOW_POINTER_OVERFLOW_ATTR
+void ZSTD_fillHashTableForCDict(ZSTD_MatchState_t* ms,
+                        const void* const end,
+                        ZSTD_dictTableLoadMethod_e dtlm)
+{
+    const ZSTD_compressionParameters* const cParams = &ms->cParams;
+    U32* const hashTable = ms->hashTable;
+    U32  const hBits = cParams->hashLog + ZSTD_SHORT_CACHE_TAG_BITS;
+    U32  const mls = cParams->minMatch;
+    const BYTE* const base = ms->window.base;
+    const BYTE* ip = base + ms->nextToUpdate;
+    const BYTE* const iend = ((const BYTE*)end) - HASH_READ_SIZE;
+    const U32 fastHashFillStep = 3;
+
+    /* Currently, we always use ZSTD_dtlm_full for filling CDict tables.
+     * Feel free to remove this assert if there's a good reason! */
+    assert(dtlm == ZSTD_dtlm_full);
+
+    /* Always insert every fastHashFillStep position into the hash table.
+     * Insert the other positions if their hash entry is empty.
+     */
+    for ( ; ip + fastHashFillStep < iend + 2; ip += fastHashFillStep) {
+        U32 const curr = (U32)(ip - base);
+        {   size_t const hashAndTag = ZSTD_hashPtr(ip, hBits, mls);
+            ZSTD_writeTaggedIndex(hashTable, hashAndTag, curr);   }
+
+        if (dtlm == ZSTD_dtlm_fast) continue;
+        /* Only load extra positions for ZSTD_dtlm_full */
+        {   U32 p;
+            for (p = 1; p < fastHashFillStep; ++p) {
+                size_t const hashAndTag = ZSTD_hashPtr(ip + p, hBits, mls);
+                if (hashTable[hashAndTag >> ZSTD_SHORT_CACHE_TAG_BITS] == 0) {  /* not yet filled */
+                    ZSTD_writeTaggedIndex(hashTable, hashAndTag, curr + p);
+    }   }   }   }
+}
+
+static
+ZSTD_ALLOW_POINTER_OVERFLOW_ATTR
+void ZSTD_fillHashTableForCCtx(ZSTD_MatchState_t* ms,
+                        const void* const end,
+                        ZSTD_dictTableLoadMethod_e dtlm)
+{
+    const ZSTD_compressionParameters* const cParams = &ms->cParams;
+    U32* const hashTable = ms->hashTable;
+    U32  const hBits = cParams->hashLog;
+    U32  const mls = cParams->minMatch;
+    const BYTE* const base = ms->window.base;
+    const BYTE* ip = base + ms->nextToUpdate;
+    const BYTE* const iend = ((const BYTE*)end) - HASH_READ_SIZE;
+    const U32 fastHashFillStep = 3;
+
+    /* Currently, we always use ZSTD_dtlm_fast for filling CCtx tables.
+     * Feel free to remove this assert if there's a good reason! */
+    assert(dtlm == ZSTD_dtlm_fast);
+
+    /* Always insert every fastHashFillStep position into the hash table.
+     * Insert the other positions if their hash entry is empty.
+     */
+    for ( ; ip + fastHashFillStep < iend + 2; ip += fastHashFillStep) {
+        U32 const curr = (U32)(ip - base);
+        size_t const hash0 = ZSTD_hashPtr(ip, hBits, mls);
+        hashTable[hash0] = curr;
+        if (dtlm == ZSTD_dtlm_fast) continue;
+        /* Only load extra positions for ZSTD_dtlm_full */
+        {   U32 p;
+            for (p = 1; p < fastHashFillStep; ++p) {
+                size_t const hash = ZSTD_hashPtr(ip + p, hBits, mls);
+                if (hashTable[hash] == 0) {  /* not yet filled */
+                    hashTable[hash] = curr + p;
+    }   }   }   }
+}
+
+void ZSTD_fillHashTable(ZSTD_MatchState_t* ms,
+                        const void* const end,
+                        ZSTD_dictTableLoadMethod_e dtlm,
+                        ZSTD_tableFillPurpose_e tfp)
+{
+    if (tfp == ZSTD_tfp_forCDict) {
+        ZSTD_fillHashTableForCDict(ms, end, dtlm);
+    } else {
+        ZSTD_fillHashTableForCCtx(ms, end, dtlm);
+    }
+}
+
+
+typedef int (*ZSTD_match4Found) (const BYTE* currentPtr, const BYTE* matchAddress, U32 matchIdx, U32 idxLowLimit);
+
+static int
+ZSTD_match4Found_cmov(const BYTE* currentPtr, const BYTE* matchAddress, U32 matchIdx, U32 idxLowLimit)
+{
+    /* Array of ~random data, should have low probability of matching data.
+     * Load from here if the index is invalid.
+     * Used to avoid unpredictable branches. */
+    static const BYTE dummy[] = {0x12,0x34,0x56,0x78};
+
+    /* currentIdx >= lowLimit is a (somewhat) unpredictable branch.
+     * However expression below compiles into conditional move.
+     */
+    const BYTE* mvalAddr = ZSTD_selectAddr(matchIdx, idxLowLimit, matchAddress, dummy);
+    /* Note: this used to be written as : return test1 && test2;
+     * Unfortunately, once inlined, these tests become branches,
+     * in which case it becomes critical that they are executed in the right order (test1 then test2).
+     * So we have to write these tests in a specific manner to ensure their ordering.
+     */
+    if (MEM_read32(currentPtr) != MEM_read32(mvalAddr)) return 0;
+    /* force ordering of these tests, which matters once the function is inlined, as they become branches */
+#if defined(__GNUC__)
+    __asm__("");
+#endif
+    return matchIdx >= idxLowLimit;
+}
+
+static int
+ZSTD_match4Found_branch(const BYTE* currentPtr, const BYTE* matchAddress, U32 matchIdx, U32 idxLowLimit)
+{
+    /* using a branch instead of a cmov,
+     * because it's faster in scenarios where matchIdx >= idxLowLimit is generally true,
+     * aka almost all candidates are within range */
+    U32 mval;
+    if (matchIdx >= idxLowLimit) {
+        mval = MEM_read32(matchAddress);
+    } else {
+        mval = MEM_read32(currentPtr) ^ 1; /* guaranteed to not match. */
+    }
+
+    return (MEM_read32(currentPtr) == mval);
+}
+
+
+/**
+ * If you squint hard enough (and ignore repcodes), the search operation at any
+ * given position is broken into 4 stages:
+ *
+ * 1. Hash   (map position to hash value via input read)
+ * 2. Lookup (map hash val to index via hashtable read)
+ * 3. Load   (map index to value at that position via input read)
+ * 4. Compare
+ *
+ * Each of these steps involves a memory read at an address which is computed
+ * from the previous step. This means these steps must be sequenced and their
+ * latencies are cumulative.
+ *
+ * Rather than do 1->2->3->4 sequentially for a single position before moving
+ * onto the next, this implementation interleaves these operations across the
+ * next few positions:
+ *
+ * R = Repcode Read & Compare
+ * H = Hash
+ * T = Table Lookup
+ * M = Match Read & Compare
+ *
+ * Pos | Time -->
+ * ----+-------------------
+ * N   | ... M
+ * N+1 | ...   TM
+ * N+2 |    R H   T M
+ * N+3 |         H    TM
+ * N+4 |           R H   T M
+ * N+5 |                H   ...
+ * N+6 |                  R ...
+ *
+ * This is very much analogous to the pipelining of execution in a CPU. And just
+ * like a CPU, we have to dump the pipeline when we find a match (i.e., take a
+ * branch).
+ *
+ * When this happens, we throw away our current state, and do the following prep
+ * to re-enter the loop:
+ *
+ * Pos | Time -->
+ * ----+-------------------
+ * N   | H T
+ * N+1 |  H
+ *
+ * This is also the work we do at the beginning to enter the loop initially.
+ */
+FORCE_INLINE_TEMPLATE
+ZSTD_ALLOW_POINTER_OVERFLOW_ATTR
+size_t ZSTD_compressBlock_fast_noDict_generic(
+        ZSTD_MatchState_t* ms, SeqStore_t* seqStore, U32 rep[ZSTD_REP_NUM],
+        void const* src, size_t srcSize,
+        U32 const mls, int useCmov)
+{
+    const ZSTD_compressionParameters* const cParams = &ms->cParams;
+    U32* const hashTable = ms->hashTable;
+    U32 const hlog = cParams->hashLog;
+    size_t const stepSize = cParams->targetLength + !(cParams->targetLength) + 1; /* min 2 */
+    const BYTE* const base = ms->window.base;
+    const BYTE* const istart = (const BYTE*)src;
+    const U32   endIndex = (U32)((size_t)(istart - base) + srcSize);
+    const U32   prefixStartIndex = ZSTD_getLowestPrefixIndex(ms, endIndex, cParams->windowLog);
+    const BYTE* const prefixStart = base + prefixStartIndex;
+    const BYTE* const iend = istart + srcSize;
+    const BYTE* const ilimit = iend - HASH_READ_SIZE;
+
+    const BYTE* anchor = istart;
+    const BYTE* ip0 = istart;
+    const BYTE* ip1;
+    const BYTE* ip2;
+    const BYTE* ip3;
+    U32 current0;
+
+    U32 rep_offset1 = rep[0];
+    U32 rep_offset2 = rep[1];
+    U32 offsetSaved1 = 0, offsetSaved2 = 0;
+
+    size_t hash0; /* hash for ip0 */
+    size_t hash1; /* hash for ip1 */
+    U32 matchIdx; /* match idx for ip0 */
+
+    U32 offcode;
+    const BYTE* match0;
+    size_t mLength;
+
+    /* ip0 and ip1 are always adjacent. The targetLength skipping and
+     * uncompressibility acceleration is applied to every other position,
+     * matching the behavior of #1562. step therefore represents the gap
+     * between pairs of positions, from ip0 to ip2 or ip1 to ip3. */
+    size_t step;
+    const BYTE* nextStep;
+    const size_t kStepIncr = (1 << (kSearchStrength - 1));
+    const ZSTD_match4Found matchFound = useCmov ? ZSTD_match4Found_cmov : ZSTD_match4Found_branch;
+
+    DEBUGLOG(5, "ZSTD_compressBlock_fast_generic");
+    ip0 += (ip0 == prefixStart);
+    {   U32 const curr = (U32)(ip0 - base);
+        U32 const windowLow = ZSTD_getLowestPrefixIndex(ms, curr, cParams->windowLog);
+        U32 const maxRep = curr - windowLow;
+        if (rep_offset2 > maxRep) offsetSaved2 = rep_offset2, rep_offset2 = 0;
+        if (rep_offset1 > maxRep) offsetSaved1 = rep_offset1, rep_offset1 = 0;
+    }
+
+    /* start each op */
+_start: /* Requires: ip0 */
+
+    step = stepSize;
+    nextStep = ip0 + kStepIncr;
+
+    /* calculate positions, ip0 - anchor == 0, so we skip step calc */
+    ip1 = ip0 + 1;
+    ip2 = ip0 + step;
+    ip3 = ip2 + 1;
+
+    if (ip3 >= ilimit) {
+        goto _cleanup;
+    }
+
+    hash0 = ZSTD_hashPtr(ip0, hlog, mls);
+    hash1 = ZSTD_hashPtr(ip1, hlog, mls);
+
+    matchIdx = hashTable[hash0];
+
+    do {
+        /* load repcode match for ip[2]*/
+        const U32 rval = MEM_read32(ip2 - rep_offset1);
+
+        /* write back hash table entry */
+        current0 = (U32)(ip0 - base);
+        hashTable[hash0] = current0;
+
+        /* check repcode at ip[2] */
+        if ((MEM_read32(ip2) == rval) & (rep_offset1 > 0)) {
+            ip0 = ip2;
+            match0 = ip0 - rep_offset1;
+            mLength = ip0[-1] == match0[-1];
+            ip0 -= mLength;
+            match0 -= mLength;
+            offcode = REPCODE1_TO_OFFBASE;
+            mLength += 4;
+
+            /* Write next hash table entry: it's already calculated.
+             * This write is known to be safe because ip1 is before the
+             * repcode (ip2). */
+            hashTable[hash1] = (U32)(ip1 - base);
+
+            goto _match;
+        }
+
+         if (matchFound(ip0, base + matchIdx, matchIdx, prefixStartIndex)) {
+            /* Write next hash table entry (it's already calculated).
+            * This write is known to be safe because the ip1 == ip0 + 1,
+            * so searching will resume after ip1 */
+            hashTable[hash1] = (U32)(ip1 - base);
+
+            goto _offset;
+        }
+
+        /* lookup ip[1] */
+        matchIdx = hashTable[hash1];
+
+        /* hash ip[2] */
+        hash0 = hash1;
+        hash1 = ZSTD_hashPtr(ip2, hlog, mls);
+
+        /* advance to next positions */
+        ip0 = ip1;
+        ip1 = ip2;
+        ip2 = ip3;
+
+        /* write back hash table entry */
+        current0 = (U32)(ip0 - base);
+        hashTable[hash0] = current0;
+
+         if (matchFound(ip0, base + matchIdx, matchIdx, prefixStartIndex)) {
+            /* Write next hash table entry, since it's already calculated */
+            if (step <= 4) {
+                /* Avoid writing an index if it's >= position where search will resume.
+                * The minimum possible match has length 4, so search can resume at ip0 + 4.
+                */
+                hashTable[hash1] = (U32)(ip1 - base);
+            }
+            goto _offset;
+        }
+
+        /* lookup ip[1] */
+        matchIdx = hashTable[hash1];
+
+        /* hash ip[2] */
+        hash0 = hash1;
+        hash1 = ZSTD_hashPtr(ip2, hlog, mls);
+
+        /* advance to next positions */
+        ip0 = ip1;
+        ip1 = ip2;
+        ip2 = ip0 + step;
+        ip3 = ip1 + step;
+
+        /* calculate step */
+        if (ip2 >= nextStep) {
+            step++;
+            PREFETCH_L1(ip1 + 64);
+            PREFETCH_L1(ip1 + 128);
+            nextStep += kStepIncr;
+        }
+    } while (ip3 < ilimit);
+
+_cleanup:
+    /* Note that there are probably still a couple positions one could search.
+     * However, it seems to be a meaningful performance hit to try to search
+     * them. So let's not. */
+
+    /* When the repcodes are outside of the prefix, we set them to zero before the loop.
+     * When the offsets are still zero, we need to restore them after the block to have a correct
+     * repcode history. If only one offset was invalid, it is easy. The tricky case is when both
+     * offsets were invalid. We need to figure out which offset to refill with.
+     *     - If both offsets are zero they are in the same order.
+     *     - If both offsets are non-zero, we won't restore the offsets from `offsetSaved[12]`.
+     *     - If only one is zero, we need to decide which offset to restore.
+     *         - If rep_offset1 is non-zero, then rep_offset2 must be offsetSaved1.
+     *         - It is impossible for rep_offset2 to be non-zero.
+     *
+     * So if rep_offset1 started invalid (offsetSaved1 != 0) and became valid (rep_offset1 != 0), then
+     * set rep[0] = rep_offset1 and rep[1] = offsetSaved1.
+     */
+    offsetSaved2 = ((offsetSaved1 != 0) && (rep_offset1 != 0)) ? offsetSaved1 : offsetSaved2;
+
+    /* save reps for next block */
+    rep[0] = rep_offset1 ? rep_offset1 : offsetSaved1;
+    rep[1] = rep_offset2 ? rep_offset2 : offsetSaved2;
+
+    /* Return the last literals size */
+    return (size_t)(iend - anchor);
+
+_offset: /* Requires: ip0, idx */
+
+    /* Compute the offset code. */
+    match0 = base + matchIdx;
+    rep_offset2 = rep_offset1;
+    rep_offset1 = (U32)(ip0-match0);
+    offcode = OFFSET_TO_OFFBASE(rep_offset1);
+    mLength = 4;
+
+    /* Count the backwards match length. */
+    while (((ip0>anchor) & (match0>prefixStart)) && (ip0[-1] == match0[-1])) {
+        ip0--;
+        match0--;
+        mLength++;
+    }
+
+_match: /* Requires: ip0, match0, offcode */
+
+    /* Count the forward length. */
+    mLength += ZSTD_count(ip0 + mLength, match0 + mLength, iend);
+
+    ZSTD_storeSeq(seqStore, (size_t)(ip0 - anchor), anchor, iend, offcode, mLength);
+
+    ip0 += mLength;
+    anchor = ip0;
+
+    /* Fill table and check for immediate repcode. */
+    if (ip0 <= ilimit) {
+        /* Fill Table */
+        assert(base+current0+2 > istart);  /* check base overflow */
+        hashTable[ZSTD_hashPtr(base+current0+2, hlog, mls)] = current0+2;  /* here because current+2 could be > iend-8 */
+        hashTable[ZSTD_hashPtr(ip0-2, hlog, mls)] = (U32)(ip0-2-base);
+
+        if (rep_offset2 > 0) { /* rep_offset2==0 means rep_offset2 is invalidated */
+            while ( (ip0 <= ilimit) && (MEM_read32(ip0) == MEM_read32(ip0 - rep_offset2)) ) {
+                /* store sequence */
+                size_t const rLength = ZSTD_count(ip0+4, ip0+4-rep_offset2, iend) + 4;
+                { U32 const tmpOff = rep_offset2; rep_offset2 = rep_offset1; rep_offset1 = tmpOff; } /* swap rep_offset2 <=> rep_offset1 */
+                hashTable[ZSTD_hashPtr(ip0, hlog, mls)] = (U32)(ip0-base);
+                ip0 += rLength;
+                ZSTD_storeSeq(seqStore, 0 /*litLen*/, anchor, iend, REPCODE1_TO_OFFBASE, rLength);
+                anchor = ip0;
+                continue;   /* faster when present (confirmed on gcc-8) ... (?) */
+    }   }   }
+
+    goto _start;
+}
+
+#define ZSTD_GEN_FAST_FN(dictMode, mml, cmov)                                                       \
+    static size_t ZSTD_compressBlock_fast_##dictMode##_##mml##_##cmov(                              \
+            ZSTD_MatchState_t* ms, SeqStore_t* seqStore, U32 rep[ZSTD_REP_NUM],                    \
+            void const* src, size_t srcSize)                                                       \
+    {                                                                                              \
+        return ZSTD_compressBlock_fast_##dictMode##_generic(ms, seqStore, rep, src, srcSize, mml, cmov); \
+    }
+
+ZSTD_GEN_FAST_FN(noDict, 4, 1)
+ZSTD_GEN_FAST_FN(noDict, 5, 1)
+ZSTD_GEN_FAST_FN(noDict, 6, 1)
+ZSTD_GEN_FAST_FN(noDict, 7, 1)
+
+ZSTD_GEN_FAST_FN(noDict, 4, 0)
+ZSTD_GEN_FAST_FN(noDict, 5, 0)
+ZSTD_GEN_FAST_FN(noDict, 6, 0)
+ZSTD_GEN_FAST_FN(noDict, 7, 0)
+
+size_t ZSTD_compressBlock_fast(
+        ZSTD_MatchState_t* ms, SeqStore_t* seqStore, U32 rep[ZSTD_REP_NUM],
+        void const* src, size_t srcSize)
+{
+    U32 const mml = ms->cParams.minMatch;
+    /* use cmov when "candidate in range" branch is likely unpredictable */
+    int const useCmov = ms->cParams.windowLog < 19;
+    assert(ms->dictMatchState == NULL);
+    if (useCmov) {
+        switch(mml)
+        {
+        default: /* includes case 3 */
+        case 4 :
+            return ZSTD_compressBlock_fast_noDict_4_1(ms, seqStore, rep, src, srcSize);
+        case 5 :
+            return ZSTD_compressBlock_fast_noDict_5_1(ms, seqStore, rep, src, srcSize);
+        case 6 :
+            return ZSTD_compressBlock_fast_noDict_6_1(ms, seqStore, rep, src, srcSize);
+        case 7 :
+            return ZSTD_compressBlock_fast_noDict_7_1(ms, seqStore, rep, src, srcSize);
+        }
+    } else {
+        /* use a branch instead */
+        switch(mml)
+        {
+        default: /* includes case 3 */
+        case 4 :
+            return ZSTD_compressBlock_fast_noDict_4_0(ms, seqStore, rep, src, srcSize);
+        case 5 :
+            return ZSTD_compressBlock_fast_noDict_5_0(ms, seqStore, rep, src, srcSize);
+        case 6 :
+            return ZSTD_compressBlock_fast_noDict_6_0(ms, seqStore, rep, src, srcSize);
+        case 7 :
+            return ZSTD_compressBlock_fast_noDict_7_0(ms, seqStore, rep, src, srcSize);
+        }
+    }
+}
+
+FORCE_INLINE_TEMPLATE
+ZSTD_ALLOW_POINTER_OVERFLOW_ATTR
+size_t ZSTD_compressBlock_fast_dictMatchState_generic(
+        ZSTD_MatchState_t* ms, SeqStore_t* seqStore, U32 rep[ZSTD_REP_NUM],
+        void const* src, size_t srcSize, U32 const mls, U32 const hasStep)
+{
+    const ZSTD_compressionParameters* const cParams = &ms->cParams;
+    U32* const hashTable = ms->hashTable;
+    U32 const hlog = cParams->hashLog;
+    /* support stepSize of 0 */
+    U32 const stepSize = cParams->targetLength + !(cParams->targetLength);
+    const BYTE* const base = ms->window.base;
+    const BYTE* const istart = (const BYTE*)src;
+    const BYTE* ip0 = istart;
+    const BYTE* ip1 = ip0 + stepSize; /* we assert below that stepSize >= 1 */
+    const BYTE* anchor = istart;
+    const U32   prefixStartIndex = ms->window.dictLimit;
+    const BYTE* const prefixStart = base + prefixStartIndex;
+    const BYTE* const iend = istart + srcSize;
+    const BYTE* const ilimit = iend - HASH_READ_SIZE;
+    U32 offset_1=rep[0], offset_2=rep[1];
+
+    const ZSTD_MatchState_t* const dms = ms->dictMatchState;
+    const ZSTD_compressionParameters* const dictCParams = &dms->cParams ;
+    const U32* const dictHashTable = dms->hashTable;
+    const U32 dictStartIndex       = dms->window.dictLimit;
+    const BYTE* const dictBase     = dms->window.base;
+    const BYTE* const dictStart    = dictBase + dictStartIndex;
+    const BYTE* const dictEnd      = dms->window.nextSrc;
+    const U32 dictIndexDelta       = prefixStartIndex - (U32)(dictEnd - dictBase);
+    const U32 dictAndPrefixLength  = (U32)(istart - prefixStart + dictEnd - dictStart);
+    const U32 dictHBits            = dictCParams->hashLog + ZSTD_SHORT_CACHE_TAG_BITS;
+
+    /* if a dictionary is still attached, it necessarily means that
+     * it is within window size. So we just check it. */
+    const U32 maxDistance = 1U << cParams->windowLog;
+    const U32 endIndex = (U32)((size_t)(istart - base) + srcSize);
+    assert(endIndex - prefixStartIndex <= maxDistance);
+    (void)maxDistance; (void)endIndex;   /* these variables are not used when assert() is disabled */
+
+    (void)hasStep; /* not currently specialized on whether it's accelerated */
+
+    /* ensure there will be no underflow
+     * when translating a dict index into a local index */
+    assert(prefixStartIndex >= (U32)(dictEnd - dictBase));
+
+    if (ms->prefetchCDictTables) {
+        size_t const hashTableBytes = (((size_t)1) << dictCParams->hashLog) * sizeof(U32);
+        PREFETCH_AREA(dictHashTable, hashTableBytes);
+    }
+
+    /* init */
+    DEBUGLOG(5, "ZSTD_compressBlock_fast_dictMatchState_generic");
+    ip0 += (dictAndPrefixLength == 0);
+    /* dictMatchState repCode checks don't currently handle repCode == 0
+     * disabling. */
+    assert(offset_1 <= dictAndPrefixLength);
+    assert(offset_2 <= dictAndPrefixLength);
+
+    /* Outer search loop */
+    assert(stepSize >= 1);
+    while (ip1 <= ilimit) {   /* repcode check at (ip0 + 1) is safe because ip0 < ip1 */
+        size_t mLength;
+        size_t hash0 = ZSTD_hashPtr(ip0, hlog, mls);
+
+        size_t const dictHashAndTag0 = ZSTD_hashPtr(ip0, dictHBits, mls);
+        U32 dictMatchIndexAndTag = dictHashTable[dictHashAndTag0 >> ZSTD_SHORT_CACHE_TAG_BITS];
+        int dictTagsMatch = ZSTD_comparePackedTags(dictMatchIndexAndTag, dictHashAndTag0);
+
+        U32 matchIndex = hashTable[hash0];
+        U32 curr = (U32)(ip0 - base);
+        size_t step = stepSize;
+        const size_t kStepIncr = 1 << kSearchStrength;
+        const BYTE* nextStep = ip0 + kStepIncr;
+
+        /* Inner search loop */
+        while (1) {
+            const BYTE* match = base + matchIndex;
+            const U32 repIndex = curr + 1 - offset_1;
+            const BYTE* repMatch = (repIndex < prefixStartIndex) ?
+                                   dictBase + (repIndex - dictIndexDelta) :
+                                   base + repIndex;
+            const size_t hash1 = ZSTD_hashPtr(ip1, hlog, mls);
+            size_t const dictHashAndTag1 = ZSTD_hashPtr(ip1, dictHBits, mls);
+            hashTable[hash0] = curr;   /* update hash table */
+
+            if ((ZSTD_index_overlap_check(prefixStartIndex, repIndex))
+                && (MEM_read32(repMatch) == MEM_read32(ip0 + 1))) {
+                const BYTE* const repMatchEnd = repIndex < prefixStartIndex ? dictEnd : iend;
+                mLength = ZSTD_count_2segments(ip0 + 1 + 4, repMatch + 4, iend, repMatchEnd, prefixStart) + 4;
+                ip0++;
+                ZSTD_storeSeq(seqStore, (size_t) (ip0 - anchor), anchor, iend, REPCODE1_TO_OFFBASE, mLength);
+                break;
+            }
+
+            if (dictTagsMatch) {
+                /* Found a possible dict match */
+                const U32 dictMatchIndex = dictMatchIndexAndTag >> ZSTD_SHORT_CACHE_TAG_BITS;
+                const BYTE* dictMatch = dictBase + dictMatchIndex;
+                if (dictMatchIndex > dictStartIndex &&
+                    MEM_read32(dictMatch) == MEM_read32(ip0)) {
+                    /* To replicate extDict parse behavior, we only use dict matches when the normal matchIndex is invalid */
+                    if (matchIndex <= prefixStartIndex) {
+                        U32 const offset = (U32) (curr - dictMatchIndex - dictIndexDelta);
+                        mLength = ZSTD_count_2segments(ip0 + 4, dictMatch + 4, iend, dictEnd, prefixStart) + 4;
+                        while (((ip0 > anchor) & (dictMatch > dictStart))
+                            && (ip0[-1] == dictMatch[-1])) {
+                            ip0--;
+                            dictMatch--;
+                            mLength++;
+                        } /* catch up */
+                        offset_2 = offset_1;
+                        offset_1 = offset;
+                        ZSTD_storeSeq(seqStore, (size_t) (ip0 - anchor), anchor, iend, OFFSET_TO_OFFBASE(offset), mLength);
+                        break;
+                    }
+                }
+            }
+
+            if (ZSTD_match4Found_cmov(ip0, match, matchIndex, prefixStartIndex)) {
+                /* found a regular match of size >= 4 */
+                U32 const offset = (U32) (ip0 - match);
+                mLength = ZSTD_count(ip0 + 4, match + 4, iend) + 4;
+                while (((ip0 > anchor) & (match > prefixStart))
+                       && (ip0[-1] == match[-1])) {
+                    ip0--;
+                    match--;
+                    mLength++;
+                } /* catch up */
+                offset_2 = offset_1;
+                offset_1 = offset;
+                ZSTD_storeSeq(seqStore, (size_t) (ip0 - anchor), anchor, iend, OFFSET_TO_OFFBASE(offset), mLength);
+                break;
+            }
+
+            /* Prepare for next iteration */
+            dictMatchIndexAndTag = dictHashTable[dictHashAndTag1 >> ZSTD_SHORT_CACHE_TAG_BITS];
+            dictTagsMatch = ZSTD_comparePackedTags(dictMatchIndexAndTag, dictHashAndTag1);
+            matchIndex = hashTable[hash1];
+
+            if (ip1 >= nextStep) {
+                step++;
+                nextStep += kStepIncr;
+            }
+            ip0 = ip1;
+            ip1 = ip1 + step;
+            if (ip1 > ilimit) goto _cleanup;
+
+            curr = (U32)(ip0 - base);
+            hash0 = hash1;
+        }   /* end inner search loop */
+
+        /* match found */
+        assert(mLength);
+        ip0 += mLength;
+        anchor = ip0;
+
+        if (ip0 <= ilimit) {
+            /* Fill Table */
+            assert(base+curr+2 > istart);  /* check base overflow */
+            hashTable[ZSTD_hashPtr(base+curr+2, hlog, mls)] = curr+2;  /* here because curr+2 could be > iend-8 */
+            hashTable[ZSTD_hashPtr(ip0-2, hlog, mls)] = (U32)(ip0-2-base);
+
+            /* check immediate repcode */
+            while (ip0 <= ilimit) {
+                U32 const current2 = (U32)(ip0-base);
+                U32 const repIndex2 = current2 - offset_2;
+                const BYTE* repMatch2 = repIndex2 < prefixStartIndex ?
+                        dictBase - dictIndexDelta + repIndex2 :
+                        base + repIndex2;
+                if ( (ZSTD_index_overlap_check(prefixStartIndex, repIndex2))
+                   && (MEM_read32(repMatch2) == MEM_read32(ip0))) {
+                    const BYTE* const repEnd2 = repIndex2 < prefixStartIndex ? dictEnd : iend;
+                    size_t const repLength2 = ZSTD_count_2segments(ip0+4, repMatch2+4, iend, repEnd2, prefixStart) + 4;
+                    U32 tmpOffset = offset_2; offset_2 = offset_1; offset_1 = tmpOffset;   /* swap offset_2 <=> offset_1 */
+                    ZSTD_storeSeq(seqStore, 0, anchor, iend, REPCODE1_TO_OFFBASE, repLength2);
+                    hashTable[ZSTD_hashPtr(ip0, hlog, mls)] = current2;
+                    ip0 += repLength2;
+                    anchor = ip0;
+                    continue;
+                }
+                break;
+            }
+        }
+
+        /* Prepare for next iteration */
+        assert(ip0 == anchor);
+        ip1 = ip0 + stepSize;
+    }
+
+_cleanup:
+    /* save reps for next block */
+    rep[0] = offset_1;
+    rep[1] = offset_2;
+
+    /* Return the last literals size */
+    return (size_t)(iend - anchor);
+}
+
+
+ZSTD_GEN_FAST_FN(dictMatchState, 4, 0)
+ZSTD_GEN_FAST_FN(dictMatchState, 5, 0)
+ZSTD_GEN_FAST_FN(dictMatchState, 6, 0)
+ZSTD_GEN_FAST_FN(dictMatchState, 7, 0)
+
+size_t ZSTD_compressBlock_fast_dictMatchState(
+        ZSTD_MatchState_t* ms, SeqStore_t* seqStore, U32 rep[ZSTD_REP_NUM],
+        void const* src, size_t srcSize)
+{
+    U32 const mls = ms->cParams.minMatch;
+    assert(ms->dictMatchState != NULL);
+    switch(mls)
+    {
+    default: /* includes case 3 */
+    case 4 :
+        return ZSTD_compressBlock_fast_dictMatchState_4_0(ms, seqStore, rep, src, srcSize);
+    case 5 :
+        return ZSTD_compressBlock_fast_dictMatchState_5_0(ms, seqStore, rep, src, srcSize);
+    case 6 :
+        return ZSTD_compressBlock_fast_dictMatchState_6_0(ms, seqStore, rep, src, srcSize);
+    case 7 :
+        return ZSTD_compressBlock_fast_dictMatchState_7_0(ms, seqStore, rep, src, srcSize);
+    }
+}
+
+
+static
+ZSTD_ALLOW_POINTER_OVERFLOW_ATTR
+size_t ZSTD_compressBlock_fast_extDict_generic(
+        ZSTD_MatchState_t* ms, SeqStore_t* seqStore, U32 rep[ZSTD_REP_NUM],
+        void const* src, size_t srcSize, U32 const mls, U32 const hasStep)
+{
+    const ZSTD_compressionParameters* const cParams = &ms->cParams;
+    U32* const hashTable = ms->hashTable;
+    U32 const hlog = cParams->hashLog;
+    /* support stepSize of 0 */
+    size_t const stepSize = cParams->targetLength + !(cParams->targetLength) + 1;
+    const BYTE* const base = ms->window.base;
+    const BYTE* const dictBase = ms->window.dictBase;
+    const BYTE* const istart = (const BYTE*)src;
+    const BYTE* anchor = istart;
+    const U32   endIndex = (U32)((size_t)(istart - base) + srcSize);
+    const U32   lowLimit = ZSTD_getLowestMatchIndex(ms, endIndex, cParams->windowLog);
+    const U32   dictStartIndex = lowLimit;
+    const BYTE* const dictStart = dictBase + dictStartIndex;
+    const U32   dictLimit = ms->window.dictLimit;
+    const U32   prefixStartIndex = dictLimit < lowLimit ? lowLimit : dictLimit;
+    const BYTE* const prefixStart = base + prefixStartIndex;
+    const BYTE* const dictEnd = dictBase + prefixStartIndex;
+    const BYTE* const iend = istart + srcSize;
+    const BYTE* const ilimit = iend - 8;
+    U32 offset_1=rep[0], offset_2=rep[1];
+    U32 offsetSaved1 = 0, offsetSaved2 = 0;
+
+    const BYTE* ip0 = istart;
+    const BYTE* ip1;
+    const BYTE* ip2;
+    const BYTE* ip3;
+    U32 current0;
+
+
+    size_t hash0; /* hash for ip0 */
+    size_t hash1; /* hash for ip1 */
+    U32 idx; /* match idx for ip0 */
+    const BYTE* idxBase; /* base pointer for idx */
+
+    U32 offcode;
+    const BYTE* match0;
+    size_t mLength;
+    const BYTE* matchEnd = 0; /* initialize to avoid warning, assert != 0 later */
+
+    size_t step;
+    const BYTE* nextStep;
+    const size_t kStepIncr = (1 << (kSearchStrength - 1));
+
+    (void)hasStep; /* not currently specialized on whether it's accelerated */
+
+    DEBUGLOG(5, "ZSTD_compressBlock_fast_extDict_generic (offset_1=%u)", offset_1);
+
+    /* switch to "regular" variant if extDict is invalidated due to maxDistance */
+    if (prefixStartIndex == dictStartIndex)
+        return ZSTD_compressBlock_fast(ms, seqStore, rep, src, srcSize);
+
+    {   U32 const curr = (U32)(ip0 - base);
+        U32 const maxRep = curr - dictStartIndex;
+        if (offset_2 >= maxRep) offsetSaved2 = offset_2, offset_2 = 0;
+        if (offset_1 >= maxRep) offsetSaved1 = offset_1, offset_1 = 0;
+    }
+
+    /* start each op */
+_start: /* Requires: ip0 */
+
+    step = stepSize;
+    nextStep = ip0 + kStepIncr;
+
+    /* calculate positions, ip0 - anchor == 0, so we skip step calc */
+    ip1 = ip0 + 1;
+    ip2 = ip0 + step;
+    ip3 = ip2 + 1;
+
+    if (ip3 >= ilimit) {
+        goto _cleanup;
+    }
+
+    hash0 = ZSTD_hashPtr(ip0, hlog, mls);
+    hash1 = ZSTD_hashPtr(ip1, hlog, mls);
+
+    idx = hashTable[hash0];
+    idxBase = idx < prefixStartIndex ? dictBase : base;
+
+    do {
+        {   /* load repcode match for ip[2] */
+            U32 const current2 = (U32)(ip2 - base);
+            U32 const repIndex = current2 - offset_1;
+            const BYTE* const repBase = repIndex < prefixStartIndex ? dictBase : base;
+            U32 rval;
+            if ( ((U32)(prefixStartIndex - repIndex) >= 4) /* intentional underflow */
+                 & (offset_1 > 0) ) {
+                rval = MEM_read32(repBase + repIndex);
+            } else {
+                rval = MEM_read32(ip2) ^ 1; /* guaranteed to not match. */
+            }
+
+            /* write back hash table entry */
+            current0 = (U32)(ip0 - base);
+            hashTable[hash0] = current0;
+
+            /* check repcode at ip[2] */
+            if (MEM_read32(ip2) == rval) {
+                ip0 = ip2;
+                match0 = repBase + repIndex;
+                matchEnd = repIndex < prefixStartIndex ? dictEnd : iend;
+                assert((match0 != prefixStart) & (match0 != dictStart));
+                mLength = ip0[-1] == match0[-1];
+                ip0 -= mLength;
+                match0 -= mLength;
+                offcode = REPCODE1_TO_OFFBASE;
+                mLength += 4;
+                goto _match;
+        }   }
+
+        {   /* load match for ip[0] */
+            U32 const mval = idx >= dictStartIndex ?
+                    MEM_read32(idxBase + idx) :
+                    MEM_read32(ip0) ^ 1; /* guaranteed not to match */
+
+            /* check match at ip[0] */
+            if (MEM_read32(ip0) == mval) {
+                /* found a match! */
+                goto _offset;
+        }   }
+
+        /* lookup ip[1] */
+        idx = hashTable[hash1];
+        idxBase = idx < prefixStartIndex ? dictBase : base;
+
+        /* hash ip[2] */
+        hash0 = hash1;
+        hash1 = ZSTD_hashPtr(ip2, hlog, mls);
+
+        /* advance to next positions */
+        ip0 = ip1;
+        ip1 = ip2;
+        ip2 = ip3;
+
+        /* write back hash table entry */
+        current0 = (U32)(ip0 - base);
+        hashTable[hash0] = current0;
+
+        {   /* load match for ip[0] */
+            U32 const mval = idx >= dictStartIndex ?
+                    MEM_read32(idxBase + idx) :
+                    MEM_read32(ip0) ^ 1; /* guaranteed not to match */
+
+            /* check match at ip[0] */
+            if (MEM_read32(ip0) == mval) {
+                /* found a match! */
+                goto _offset;
+        }   }
+
+        /* lookup ip[1] */
+        idx = hashTable[hash1];
+        idxBase = idx < prefixStartIndex ? dictBase : base;
+
+        /* hash ip[2] */
+        hash0 = hash1;
+        hash1 = ZSTD_hashPtr(ip2, hlog, mls);
+
+        /* advance to next positions */
+        ip0 = ip1;
+        ip1 = ip2;
+        ip2 = ip0 + step;
+        ip3 = ip1 + step;
+
+        /* calculate step */
+        if (ip2 >= nextStep) {
+            step++;
+            PREFETCH_L1(ip1 + 64);
+            PREFETCH_L1(ip1 + 128);
+            nextStep += kStepIncr;
+        }
+    } while (ip3 < ilimit);
+
+_cleanup:
+    /* Note that there are probably still a couple positions we could search.
+     * However, it seems to be a meaningful performance hit to try to search
+     * them. So let's not. */
+
+    /* If offset_1 started invalid (offsetSaved1 != 0) and became valid (offset_1 != 0),
+     * rotate saved offsets. See comment in ZSTD_compressBlock_fast_noDict for more context. */
+    offsetSaved2 = ((offsetSaved1 != 0) && (offset_1 != 0)) ? offsetSaved1 : offsetSaved2;
+
+    /* save reps for next block */
+    rep[0] = offset_1 ? offset_1 : offsetSaved1;
+    rep[1] = offset_2 ? offset_2 : offsetSaved2;
+
+    /* Return the last literals size */
+    return (size_t)(iend - anchor);
+
+_offset: /* Requires: ip0, idx, idxBase */
+
+    /* Compute the offset code. */
+    {   U32 const offset = current0 - idx;
+        const BYTE* const lowMatchPtr = idx < prefixStartIndex ? dictStart : prefixStart;
+        matchEnd = idx < prefixStartIndex ? dictEnd : iend;
+        match0 = idxBase + idx;
+        offset_2 = offset_1;
+        offset_1 = offset;
+        offcode = OFFSET_TO_OFFBASE(offset);
+        mLength = 4;
+
+        /* Count the backwards match length. */
+        while (((ip0>anchor) & (match0>lowMatchPtr)) && (ip0[-1] == match0[-1])) {
+            ip0--;
+            match0--;
+            mLength++;
+    }   }
+
+_match: /* Requires: ip0, match0, offcode, matchEnd */
+
+    /* Count the forward length. */
+    assert(matchEnd != 0);
+    mLength += ZSTD_count_2segments(ip0 + mLength, match0 + mLength, iend, matchEnd, prefixStart);
+
+    ZSTD_storeSeq(seqStore, (size_t)(ip0 - anchor), anchor, iend, offcode, mLength);
+
+    ip0 += mLength;
+    anchor = ip0;
+
+    /* write next hash table entry */
+    if (ip1 < ip0) {
+        hashTable[hash1] = (U32)(ip1 - base);
+    }
+
+    /* Fill table and check for immediate repcode. */
+    if (ip0 <= ilimit) {
+        /* Fill Table */
+        assert(base+current0+2 > istart);  /* check base overflow */
+        hashTable[ZSTD_hashPtr(base+current0+2, hlog, mls)] = current0+2;  /* here because current+2 could be > iend-8 */
+        hashTable[ZSTD_hashPtr(ip0-2, hlog, mls)] = (U32)(ip0-2-base);
+
+        while (ip0 <= ilimit) {
+            U32 const repIndex2 = (U32)(ip0-base) - offset_2;
+            const BYTE* const repMatch2 = repIndex2 < prefixStartIndex ? dictBase + repIndex2 : base + repIndex2;
+            if ( ((ZSTD_index_overlap_check(prefixStartIndex, repIndex2)) & (offset_2 > 0))
+                 && (MEM_read32(repMatch2) == MEM_read32(ip0)) ) {
+                const BYTE* const repEnd2 = repIndex2 < prefixStartIndex ? dictEnd : iend;
+                size_t const repLength2 = ZSTD_count_2segments(ip0+4, repMatch2+4, iend, repEnd2, prefixStart) + 4;
+                { U32 const tmpOffset = offset_2; offset_2 = offset_1; offset_1 = tmpOffset; }  /* swap offset_2 <=> offset_1 */
+                ZSTD_storeSeq(seqStore, 0 /*litlen*/, anchor, iend, REPCODE1_TO_OFFBASE, repLength2);
+                hashTable[ZSTD_hashPtr(ip0, hlog, mls)] = (U32)(ip0-base);
+                ip0 += repLength2;
+                anchor = ip0;
+                continue;
+            }
+            break;
+    }   }
+
+    goto _start;
+}
+
+ZSTD_GEN_FAST_FN(extDict, 4, 0)
+ZSTD_GEN_FAST_FN(extDict, 5, 0)
+ZSTD_GEN_FAST_FN(extDict, 6, 0)
+ZSTD_GEN_FAST_FN(extDict, 7, 0)
+
+size_t ZSTD_compressBlock_fast_extDict(
+        ZSTD_MatchState_t* ms, SeqStore_t* seqStore, U32 rep[ZSTD_REP_NUM],
+        void const* src, size_t srcSize)
+{
+    U32 const mls = ms->cParams.minMatch;
+    assert(ms->dictMatchState == NULL);
+    switch(mls)
+    {
+    default: /* includes case 3 */
+    case 4 :
+        return ZSTD_compressBlock_fast_extDict_4_0(ms, seqStore, rep, src, srcSize);
+    case 5 :
+        return ZSTD_compressBlock_fast_extDict_5_0(ms, seqStore, rep, src, srcSize);
+    case 6 :
+        return ZSTD_compressBlock_fast_extDict_6_0(ms, seqStore, rep, src, srcSize);
+    case 7 :
+        return ZSTD_compressBlock_fast_extDict_7_0(ms, seqStore, rep, src, srcSize);
+    }
+}
diff --git a/src/commonlib/bsd/zstd/compress/zstd_fast.h b/src/commonlib/bsd/zstd/compress/zstd_fast.h
new file mode 100644
index 0000000000..4ba4217f87
--- /dev/null
+++ b/src/commonlib/bsd/zstd/compress/zstd_fast.h
@@ -0,0 +1,32 @@
+/* SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0-only */
+
+/*
+ * Copyright (c) Meta Platforms, Inc. and affiliates.
+ * All rights reserved.
+ *
+ * This source code is licensed under both the BSD-style license (found in the
+ * LICENSE file in the root directory of this source tree) and the GPLv2 (found
+ * in the COPYING file in the root directory of this source tree).
+ * You may select, at your option, one of the above-listed licenses.
+ */
+
+#ifndef ZSTD_FAST_H
+#define ZSTD_FAST_H
+
+#include "../common/mem.h"      /* U32 */
+#include "zstd_compress_internal.h"
+
+void ZSTD_fillHashTable(ZSTD_MatchState_t* ms,
+                        void const* end, ZSTD_dictTableLoadMethod_e dtlm,
+                        ZSTD_tableFillPurpose_e tfp);
+size_t ZSTD_compressBlock_fast(
+        ZSTD_MatchState_t* ms, SeqStore_t* seqStore, U32 rep[ZSTD_REP_NUM],
+        void const* src, size_t srcSize);
+size_t ZSTD_compressBlock_fast_dictMatchState(
+        ZSTD_MatchState_t* ms, SeqStore_t* seqStore, U32 rep[ZSTD_REP_NUM],
+        void const* src, size_t srcSize);
+size_t ZSTD_compressBlock_fast_extDict(
+        ZSTD_MatchState_t* ms, SeqStore_t* seqStore, U32 rep[ZSTD_REP_NUM],
+        void const* src, size_t srcSize);
+
+#endif /* ZSTD_FAST_H */
diff --git a/src/commonlib/bsd/zstd/compress/zstd_lazy.c b/src/commonlib/bsd/zstd/compress/zstd_lazy.c
new file mode 100644
index 0000000000..ef1f2fe015
--- /dev/null
+++ b/src/commonlib/bsd/zstd/compress/zstd_lazy.c
@@ -0,0 +1,2201 @@
+/* SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0-only */
+
+/*
+ * Copyright (c) Meta Platforms, Inc. and affiliates.
+ * All rights reserved.
+ *
+ * This source code is licensed under both the BSD-style license (found in the
+ * LICENSE file in the root directory of this source tree) and the GPLv2 (found
+ * in the COPYING file in the root directory of this source tree).
+ * You may select, at your option, one of the above-listed licenses.
+ */
+
+#include "zstd_compress_internal.h"
+#include "zstd_lazy.h"
+#include "../common/zstd_bits.h" /* ZSTD_countTrailingZeros64 */
+
+#if !defined(ZSTD_EXCLUDE_GREEDY_BLOCK_COMPRESSOR) \
+ || !defined(ZSTD_EXCLUDE_LAZY_BLOCK_COMPRESSOR) \
+ || !defined(ZSTD_EXCLUDE_LAZY2_BLOCK_COMPRESSOR) \
+ || !defined(ZSTD_EXCLUDE_BTLAZY2_BLOCK_COMPRESSOR)
+
+#define kLazySkippingStep 8
+
+
+/*-*************************************
+*  Binary Tree search
+***************************************/
+
+static
+ZSTD_ALLOW_POINTER_OVERFLOW_ATTR
+void ZSTD_updateDUBT(ZSTD_MatchState_t* ms,
+                const BYTE* ip, const BYTE* iend,
+                U32 mls)
+{
+    const ZSTD_compressionParameters* const cParams = &ms->cParams;
+    U32* const hashTable = ms->hashTable;
+    U32  const hashLog = cParams->hashLog;
+
+    U32* const bt = ms->chainTable;
+    U32  const btLog  = cParams->chainLog - 1;
+    U32  const btMask = (1 << btLog) - 1;
+
+    const BYTE* const base = ms->window.base;
+    U32 const target = (U32)(ip - base);
+    U32 idx = ms->nextToUpdate;
+
+    if (idx != target)
+        DEBUGLOG(7, "ZSTD_updateDUBT, from %u to %u (dictLimit:%u)",
+                    idx, target, ms->window.dictLimit);
+    assert(ip + 8 <= iend);   /* condition for ZSTD_hashPtr */
+    (void)iend;
+
+    assert(idx >= ms->window.dictLimit);   /* condition for valid base+idx */
+    for ( ; idx < target ; idx++) {
+        size_t const h  = ZSTD_hashPtr(base + idx, hashLog, mls);   /* assumption : ip + 8 <= iend */
+        U32    const matchIndex = hashTable[h];
+
+        U32*   const nextCandidatePtr = bt + 2*(idx&btMask);
+        U32*   const sortMarkPtr  = nextCandidatePtr + 1;
+
+        DEBUGLOG(8, "ZSTD_updateDUBT: insert %u", idx);
+        hashTable[h] = idx;   /* Update Hash Table */
+        *nextCandidatePtr = matchIndex;   /* update BT like a chain */
+        *sortMarkPtr = ZSTD_DUBT_UNSORTED_MARK;
+    }
+    ms->nextToUpdate = target;
+}
+
+
+/** ZSTD_insertDUBT1() :
+ *  sort one already inserted but unsorted position
+ *  assumption : curr >= btlow == (curr - btmask)
+ *  doesn't fail */
+static
+ZSTD_ALLOW_POINTER_OVERFLOW_ATTR
+void ZSTD_insertDUBT1(const ZSTD_MatchState_t* ms,
+                 U32 curr, const BYTE* inputEnd,
+                 U32 nbCompares, U32 btLow,
+                 const ZSTD_dictMode_e dictMode)
+{
+    const ZSTD_compressionParameters* const cParams = &ms->cParams;
+    U32* const bt = ms->chainTable;
+    U32  const btLog  = cParams->chainLog - 1;
+    U32  const btMask = (1 << btLog) - 1;
+    size_t commonLengthSmaller=0, commonLengthLarger=0;
+    const BYTE* const base = ms->window.base;
+    const BYTE* const dictBase = ms->window.dictBase;
+    const U32 dictLimit = ms->window.dictLimit;
+    const BYTE* const ip = (curr>=dictLimit) ? base + curr : dictBase + curr;
+    const BYTE* const iend = (curr>=dictLimit) ? inputEnd : dictBase + dictLimit;
+    const BYTE* const dictEnd = dictBase + dictLimit;
+    const BYTE* const prefixStart = base + dictLimit;
+    const BYTE* match;
+    U32* smallerPtr = bt + 2*(curr&btMask);
+    U32* largerPtr  = smallerPtr + 1;
+    U32 matchIndex = *smallerPtr;   /* this candidate is unsorted : next sorted candidate is reached through *smallerPtr, while *largerPtr contains previous unsorted candidate (which is already saved and can be overwritten) */
+    U32 dummy32;   /* to be nullified at the end */
+    U32 const windowValid = ms->window.lowLimit;
+    U32 const maxDistance = 1U << cParams->windowLog;
+    U32 const windowLow = (curr - windowValid > maxDistance) ? curr - maxDistance : windowValid;
+
+
+    DEBUGLOG(8, "ZSTD_insertDUBT1(%u) (dictLimit=%u, lowLimit=%u)",
+                curr, dictLimit, windowLow);
+    assert(curr >= btLow);
+    assert(ip < iend);   /* condition for ZSTD_count */
+
+    for (; nbCompares && (matchIndex > windowLow); --nbCompares) {
+        U32* const nextPtr = bt + 2*(matchIndex & btMask);
+        size_t matchLength = MIN(commonLengthSmaller, commonLengthLarger);   /* guaranteed minimum nb of common bytes */
+        assert(matchIndex < curr);
+        /* note : all candidates are now supposed sorted,
+         * but it's still possible to have nextPtr[1] == ZSTD_DUBT_UNSORTED_MARK
+         * when a real index has the same value as ZSTD_DUBT_UNSORTED_MARK */
+
+        if ( (dictMode != ZSTD_extDict)
+          || (matchIndex+matchLength >= dictLimit)  /* both in current segment*/
+          || (curr < dictLimit) /* both in extDict */) {
+            const BYTE* const mBase = ( (dictMode != ZSTD_extDict)
+                                     || (matchIndex+matchLength >= dictLimit)) ?
+                                        base : dictBase;
+            assert( (matchIndex+matchLength >= dictLimit)   /* might be wrong if extDict is incorrectly set to 0 */
+                 || (curr < dictLimit) );
+            match = mBase + matchIndex;
+            matchLength += ZSTD_count(ip+matchLength, match+matchLength, iend);
+        } else {
+            match = dictBase + matchIndex;
+            matchLength += ZSTD_count_2segments(ip+matchLength, match+matchLength, iend, dictEnd, prefixStart);
+            if (matchIndex+matchLength >= dictLimit)
+                match = base + matchIndex;   /* preparation for next read of match[matchLength] */
+        }
+
+        DEBUGLOG(8, "ZSTD_insertDUBT1: comparing %u with %u : found %u common bytes ",
+                    curr, matchIndex, (U32)matchLength);
+
+        if (ip+matchLength == iend) {   /* equal : no way to know if inf or sup */
+            break;   /* drop , to guarantee consistency ; miss a bit of compression, but other solutions can corrupt tree */
+        }
+
+        if (match[matchLength] < ip[matchLength]) {  /* necessarily within buffer */
+            /* match is smaller than current */
+            *smallerPtr = matchIndex;             /* update smaller idx */
+            commonLengthSmaller = matchLength;    /* all smaller will now have at least this guaranteed common length */
+            if (matchIndex <= btLow) { smallerPtr=&dummy32; break; }   /* beyond tree size, stop searching */
+            DEBUGLOG(8, "ZSTD_insertDUBT1: %u (>btLow=%u) is smaller : next => %u",
+                        matchIndex, btLow, nextPtr[1]);
+            smallerPtr = nextPtr+1;               /* new "candidate" => larger than match, which was smaller than target */
+            matchIndex = nextPtr[1];              /* new matchIndex, larger than previous and closer to current */
+        } else {
+            /* match is larger than current */
+            *largerPtr = matchIndex;
+            commonLengthLarger = matchLength;
+            if (matchIndex <= btLow) { largerPtr=&dummy32; break; }   /* beyond tree size, stop searching */
+            DEBUGLOG(8, "ZSTD_insertDUBT1: %u (>btLow=%u) is larger => %u",
+                        matchIndex, btLow, nextPtr[0]);
+            largerPtr = nextPtr;
+            matchIndex = nextPtr[0];
+    }   }
+
+    *smallerPtr = *largerPtr = 0;
+}
+
+
+static
+ZSTD_ALLOW_POINTER_OVERFLOW_ATTR
+size_t ZSTD_DUBT_findBetterDictMatch (
+        const ZSTD_MatchState_t* ms,
+        const BYTE* const ip, const BYTE* const iend,
+        size_t* offsetPtr,
+        size_t bestLength,
+        U32 nbCompares,
+        U32 const mls,
+        const ZSTD_dictMode_e dictMode)
+{
+    const ZSTD_MatchState_t * const dms = ms->dictMatchState;
+    const ZSTD_compressionParameters* const dmsCParams = &dms->cParams;
+    const U32 * const dictHashTable = dms->hashTable;
+    U32         const hashLog = dmsCParams->hashLog;
+    size_t      const h  = ZSTD_hashPtr(ip, hashLog, mls);
+    U32               dictMatchIndex = dictHashTable[h];
+
+    const BYTE* const base = ms->window.base;
+    const BYTE* const prefixStart = base + ms->window.dictLimit;
+    U32         const curr = (U32)(ip-base);
+    const BYTE* const dictBase = dms->window.base;
+    const BYTE* const dictEnd = dms->window.nextSrc;
+    U32         const dictHighLimit = (U32)(dms->window.nextSrc - dms->window.base);
+    U32         const dictLowLimit = dms->window.lowLimit;
+    U32         const dictIndexDelta = ms->window.lowLimit - dictHighLimit;
+
+    U32*        const dictBt = dms->chainTable;
+    U32         const btLog  = dmsCParams->chainLog - 1;
+    U32         const btMask = (1 << btLog) - 1;
+    U32         const btLow = (btMask >= dictHighLimit - dictLowLimit) ? dictLowLimit : dictHighLimit - btMask;
+
+    size_t commonLengthSmaller=0, commonLengthLarger=0;
+
+    (void)dictMode;
+    assert(dictMode == ZSTD_dictMatchState);
+
+    for (; nbCompares && (dictMatchIndex > dictLowLimit); --nbCompares) {
+        U32* const nextPtr = dictBt + 2*(dictMatchIndex & btMask);
+        size_t matchLength = MIN(commonLengthSmaller, commonLengthLarger);   /* guaranteed minimum nb of common bytes */
+        const BYTE* match = dictBase + dictMatchIndex;
+        matchLength += ZSTD_count_2segments(ip+matchLength, match+matchLength, iend, dictEnd, prefixStart);
+        if (dictMatchIndex+matchLength >= dictHighLimit)
+            match = base + dictMatchIndex + dictIndexDelta;   /* to prepare for next usage of match[matchLength] */
+
+        if (matchLength > bestLength) {
+            U32 matchIndex = dictMatchIndex + dictIndexDelta;
+            if ( (4*(int)(matchLength-bestLength)) > (int)(ZSTD_highbit32(curr-matchIndex+1) - ZSTD_highbit32((U32)offsetPtr[0]+1)) ) {
+                DEBUGLOG(9, "ZSTD_DUBT_findBetterDictMatch(%u) : found better match length %u -> %u and offsetCode %u -> %u (dictMatchIndex %u, matchIndex %u)",
+                    curr, (U32)bestLength, (U32)matchLength, (U32)*offsetPtr, OFFSET_TO_OFFBASE(curr - matchIndex), dictMatchIndex, matchIndex);
+                bestLength = matchLength, *offsetPtr = OFFSET_TO_OFFBASE(curr - matchIndex);
+            }
+            if (ip+matchLength == iend) {   /* reached end of input : ip[matchLength] is not valid, no way to know if it's larger or smaller than match */
+                break;   /* drop, to guarantee consistency (miss a little bit of compression) */
+            }
+        }
+
+        if (match[matchLength] < ip[matchLength]) {
+            if (dictMatchIndex <= btLow) { break; }   /* beyond tree size, stop the search */
+            commonLengthSmaller = matchLength;    /* all smaller will now have at least this guaranteed common length */
+            dictMatchIndex = nextPtr[1];              /* new matchIndex larger than previous (closer to current) */
+        } else {
+            /* match is larger than current */
+            if (dictMatchIndex <= btLow) { break; }   /* beyond tree size, stop the search */
+            commonLengthLarger = matchLength;
+            dictMatchIndex = nextPtr[0];
+        }
+    }
+
+    if (bestLength >= MINMATCH) {
+        U32 const mIndex = curr - (U32)OFFBASE_TO_OFFSET(*offsetPtr); (void)mIndex;
+        DEBUGLOG(8, "ZSTD_DUBT_findBetterDictMatch(%u) : found match of length %u and offsetCode %u (pos %u)",
+                    curr, (U32)bestLength, (U32)*offsetPtr, mIndex);
+    }
+    return bestLength;
+
+}
+
+
+static
+ZSTD_ALLOW_POINTER_OVERFLOW_ATTR
+size_t ZSTD_DUBT_findBestMatch(ZSTD_MatchState_t* ms,
+                        const BYTE* const ip, const BYTE* const iend,
+                        size_t* offBasePtr,
+                        U32 const mls,
+                        const ZSTD_dictMode_e dictMode)
+{
+    const ZSTD_compressionParameters* const cParams = &ms->cParams;
+    U32*   const hashTable = ms->hashTable;
+    U32    const hashLog = cParams->hashLog;
+    size_t const h  = ZSTD_hashPtr(ip, hashLog, mls);
+    U32          matchIndex  = hashTable[h];
+
+    const BYTE* const base = ms->window.base;
+    U32    const curr = (U32)(ip-base);
+    U32    const windowLow = ZSTD_getLowestMatchIndex(ms, curr, cParams->windowLog);
+
+    U32*   const bt = ms->chainTable;
+    U32    const btLog  = cParams->chainLog - 1;
+    U32    const btMask = (1 << btLog) - 1;
+    U32    const btLow = (btMask >= curr) ? 0 : curr - btMask;
+    U32    const unsortLimit = MAX(btLow, windowLow);
+
+    U32*         nextCandidate = bt + 2*(matchIndex&btMask);
+    U32*         unsortedMark = bt + 2*(matchIndex&btMask) + 1;
+    U32          nbCompares = 1U << cParams->searchLog;
+    U32          nbCandidates = nbCompares;
+    U32          previousCandidate = 0;
+
+    DEBUGLOG(7, "ZSTD_DUBT_findBestMatch (%u) ", curr);
+    assert(ip <= iend-8);   /* required for h calculation */
+    assert(dictMode != ZSTD_dedicatedDictSearch);
+
+    /* reach end of unsorted candidates list */
+    while ( (matchIndex > unsortLimit)
+         && (*unsortedMark == ZSTD_DUBT_UNSORTED_MARK)
+         && (nbCandidates > 1) ) {
+        DEBUGLOG(8, "ZSTD_DUBT_findBestMatch: candidate %u is unsorted",
+                    matchIndex);
+        *unsortedMark = previousCandidate;  /* the unsortedMark becomes a reversed chain, to move up back to original position */
+        previousCandidate = matchIndex;
+        matchIndex = *nextCandidate;
+        nextCandidate = bt + 2*(matchIndex&btMask);
+        unsortedMark = bt + 2*(matchIndex&btMask) + 1;
+        nbCandidates --;
+    }
+
+    /* nullify last candidate if it's still unsorted
+     * simplification, detrimental to compression ratio, beneficial for speed */
+    if ( (matchIndex > unsortLimit)
+      && (*unsortedMark==ZSTD_DUBT_UNSORTED_MARK) ) {
+        DEBUGLOG(7, "ZSTD_DUBT_findBestMatch: nullify last unsorted candidate %u",
+                    matchIndex);
+        *nextCandidate = *unsortedMark = 0;
+    }
+
+    /* batch sort stacked candidates */
+    matchIndex = previousCandidate;
+    while (matchIndex) {  /* will end on matchIndex == 0 */
+        U32* const nextCandidateIdxPtr = bt + 2*(matchIndex&btMask) + 1;
+        U32 const nextCandidateIdx = *nextCandidateIdxPtr;
+        ZSTD_insertDUBT1(ms, matchIndex, iend,
+                         nbCandidates, unsortLimit, dictMode);
+        matchIndex = nextCandidateIdx;
+        nbCandidates++;
+    }
+
+    /* find longest match */
+    {   size_t commonLengthSmaller = 0, commonLengthLarger = 0;
+        const BYTE* const dictBase = ms->window.dictBase;
+        const U32 dictLimit = ms->window.dictLimit;
+        const BYTE* const dictEnd = dictBase + dictLimit;
+        const BYTE* const prefixStart = base + dictLimit;
+        U32* smallerPtr = bt + 2*(curr&btMask);
+        U32* largerPtr  = bt + 2*(curr&btMask) + 1;
+        U32 matchEndIdx = curr + 8 + 1;
+        U32 dummy32;   /* to be nullified at the end */
+        size_t bestLength = 0;
+
+        matchIndex  = hashTable[h];
+        hashTable[h] = curr;   /* Update Hash Table */
+
+        for (; nbCompares && (matchIndex > windowLow); --nbCompares) {
+            U32* const nextPtr = bt + 2*(matchIndex & btMask);
+            size_t matchLength = MIN(commonLengthSmaller, commonLengthLarger);   /* guaranteed minimum nb of common bytes */
+            const BYTE* match;
+
+            if ((dictMode != ZSTD_extDict) || (matchIndex+matchLength >= dictLimit)) {
+                match = base + matchIndex;
+                matchLength += ZSTD_count(ip+matchLength, match+matchLength, iend);
+            } else {
+                match = dictBase + matchIndex;
+                matchLength += ZSTD_count_2segments(ip+matchLength, match+matchLength, iend, dictEnd, prefixStart);
+                if (matchIndex+matchLength >= dictLimit)
+                    match = base + matchIndex;   /* to prepare for next usage of match[matchLength] */
+            }
+
+            if (matchLength > bestLength) {
+                if (matchLength > matchEndIdx - matchIndex)
+                    matchEndIdx = matchIndex + (U32)matchLength;
+                if ( (4*(int)(matchLength-bestLength)) > (int)(ZSTD_highbit32(curr - matchIndex + 1) - ZSTD_highbit32((U32)*offBasePtr)) )
+                    bestLength = matchLength, *offBasePtr = OFFSET_TO_OFFBASE(curr - matchIndex);
+                if (ip+matchLength == iend) {   /* equal : no way to know if inf or sup */
+                    if (dictMode == ZSTD_dictMatchState) {
+                        nbCompares = 0; /* in addition to avoiding checking any
+                                         * further in this loop, make sure we
+                                         * skip checking in the dictionary. */
+                    }
+                    break;   /* drop, to guarantee consistency (miss a little bit of compression) */
+                }
+            }
+
+            if (match[matchLength] < ip[matchLength]) {
+                /* match is smaller than current */
+                *smallerPtr = matchIndex;             /* update smaller idx */
+                commonLengthSmaller = matchLength;    /* all smaller will now have at least this guaranteed common length */
+                if (matchIndex <= btLow) { smallerPtr=&dummy32; break; }   /* beyond tree size, stop the search */
+                smallerPtr = nextPtr+1;               /* new "smaller" => larger of match */
+                matchIndex = nextPtr[1];              /* new matchIndex larger than previous (closer to current) */
+            } else {
+                /* match is larger than current */
+                *largerPtr = matchIndex;
+                commonLengthLarger = matchLength;
+                if (matchIndex <= btLow) { largerPtr=&dummy32; break; }   /* beyond tree size, stop the search */
+                largerPtr = nextPtr;
+                matchIndex = nextPtr[0];
+        }   }
+
+        *smallerPtr = *largerPtr = 0;
+
+        assert(nbCompares <= (1U << ZSTD_SEARCHLOG_MAX)); /* Check we haven't underflowed. */
+        if (dictMode == ZSTD_dictMatchState && nbCompares) {
+            bestLength = ZSTD_DUBT_findBetterDictMatch(
+                    ms, ip, iend,
+                    offBasePtr, bestLength, nbCompares,
+                    mls, dictMode);
+        }
+
+        assert(matchEndIdx > curr+8); /* ensure nextToUpdate is increased */
+        ms->nextToUpdate = matchEndIdx - 8;   /* skip repetitive patterns */
+        if (bestLength >= MINMATCH) {
+            U32 const mIndex = curr - (U32)OFFBASE_TO_OFFSET(*offBasePtr); (void)mIndex;
+            DEBUGLOG(8, "ZSTD_DUBT_findBestMatch(%u) : found match of length %u and offsetCode %u (pos %u)",
+                        curr, (U32)bestLength, (U32)*offBasePtr, mIndex);
+        }
+        return bestLength;
+    }
+}
+
+
+/** ZSTD_BtFindBestMatch() : Tree updater, providing best match */
+FORCE_INLINE_TEMPLATE
+ZSTD_ALLOW_POINTER_OVERFLOW_ATTR
+size_t ZSTD_BtFindBestMatch( ZSTD_MatchState_t* ms,
+                const BYTE* const ip, const BYTE* const iLimit,
+                      size_t* offBasePtr,
+                const U32 mls /* template */,
+                const ZSTD_dictMode_e dictMode)
+{
+    DEBUGLOG(7, "ZSTD_BtFindBestMatch");
+    if (ip < ms->window.base + ms->nextToUpdate) return 0;   /* skipped area */
+    ZSTD_updateDUBT(ms, ip, iLimit, mls);
+    return ZSTD_DUBT_findBestMatch(ms, ip, iLimit, offBasePtr, mls, dictMode);
+}
+
+/***********************************
+* Dedicated dict search
+***********************************/
+
+void ZSTD_dedicatedDictSearch_lazy_loadDictionary(ZSTD_MatchState_t* ms, const BYTE* const ip)
+{
+    const BYTE* const base = ms->window.base;
+    U32 const target = (U32)(ip - base);
+    U32* const hashTable = ms->hashTable;
+    U32* const chainTable = ms->chainTable;
+    U32 const chainSize = 1 << ms->cParams.chainLog;
+    U32 idx = ms->nextToUpdate;
+    U32 const minChain = chainSize < target - idx ? target - chainSize : idx;
+    U32 const bucketSize = 1 << ZSTD_LAZY_DDSS_BUCKET_LOG;
+    U32 const cacheSize = bucketSize - 1;
+    U32 const chainAttempts = (1 << ms->cParams.searchLog) - cacheSize;
+    U32 const chainLimit = chainAttempts > 255 ? 255 : chainAttempts;
+
+    /* We know the hashtable is oversized by a factor of `bucketSize`.
+     * We are going to temporarily pretend `bucketSize == 1`, keeping only a
+     * single entry. We will use the rest of the space to construct a temporary
+     * chaintable.
+     */
+    U32 const hashLog = ms->cParams.hashLog - ZSTD_LAZY_DDSS_BUCKET_LOG;
+    U32* const tmpHashTable = hashTable;
+    U32* const tmpChainTable = hashTable + ((size_t)1 << hashLog);
+    U32 const tmpChainSize = (U32)((1 << ZSTD_LAZY_DDSS_BUCKET_LOG) - 1) << hashLog;
+    U32 const tmpMinChain = tmpChainSize < target ? target - tmpChainSize : idx;
+    U32 hashIdx;
+
+    assert(ms->cParams.chainLog <= 24);
+    assert(ms->cParams.hashLog > ms->cParams.chainLog);
+    assert(idx != 0);
+    assert(tmpMinChain <= minChain);
+
+    /* fill conventional hash table and conventional chain table */
+    for ( ; idx < target; idx++) {
+        U32 const h = (U32)ZSTD_hashPtr(base + idx, hashLog, ms->cParams.minMatch);
+        if (idx >= tmpMinChain) {
+            tmpChainTable[idx - tmpMinChain] = hashTable[h];
+        }
+        tmpHashTable[h] = idx;
+    }
+
+    /* sort chains into ddss chain table */
+    {
+        U32 chainPos = 0;
+        for (hashIdx = 0; hashIdx < (1U << hashLog); hashIdx++) {
+            U32 count;
+            U32 countBeyondMinChain = 0;
+            U32 i = tmpHashTable[hashIdx];
+            for (count = 0; i >= tmpMinChain && count < cacheSize; count++) {
+                /* skip through the chain to the first position that won't be
+                 * in the hash cache bucket */
+                if (i < minChain) {
+                    countBeyondMinChain++;
+                }
+                i = tmpChainTable[i - tmpMinChain];
+            }
+            if (count == cacheSize) {
+                for (count = 0; count < chainLimit;) {
+                    if (i < minChain) {
+                        if (!i || ++countBeyondMinChain > cacheSize) {
+                            /* only allow pulling `cacheSize` number of entries
+                             * into the cache or chainTable beyond `minChain`,
+                             * to replace the entries pulled out of the
+                             * chainTable into the cache. This lets us reach
+                             * back further without increasing the total number
+                             * of entries in the chainTable, guaranteeing the
+                             * DDSS chain table will fit into the space
+                             * allocated for the regular one. */
+                            break;
+                        }
+                    }
+                    chainTable[chainPos++] = i;
+                    count++;
+                    if (i < tmpMinChain) {
+                        break;
+                    }
+                    i = tmpChainTable[i - tmpMinChain];
+                }
+            } else {
+                count = 0;
+            }
+            if (count) {
+                tmpHashTable[hashIdx] = ((chainPos - count) << 8) + count;
+            } else {
+                tmpHashTable[hashIdx] = 0;
+            }
+        }
+        assert(chainPos <= chainSize); /* I believe this is guaranteed... */
+    }
+
+    /* move chain pointers into the last entry of each hash bucket */
+    for (hashIdx = (1 << hashLog); hashIdx; ) {
+        U32 const bucketIdx = --hashIdx << ZSTD_LAZY_DDSS_BUCKET_LOG;
+        U32 const chainPackedPointer = tmpHashTable[hashIdx];
+        U32 i;
+        for (i = 0; i < cacheSize; i++) {
+            hashTable[bucketIdx + i] = 0;
+        }
+        hashTable[bucketIdx + bucketSize - 1] = chainPackedPointer;
+    }
+
+    /* fill the buckets of the hash table */
+    for (idx = ms->nextToUpdate; idx < target; idx++) {
+        U32 const h = (U32)ZSTD_hashPtr(base + idx, hashLog, ms->cParams.minMatch)
+                   << ZSTD_LAZY_DDSS_BUCKET_LOG;
+        U32 i;
+        /* Shift hash cache down 1. */
+        for (i = cacheSize - 1; i; i--)
+            hashTable[h + i] = hashTable[h + i - 1];
+        hashTable[h] = idx;
+    }
+
+    ms->nextToUpdate = target;
+}
+
+/* Returns the longest match length found in the dedicated dict search structure.
+ * If none are longer than the argument ml, then ml will be returned.
+ */
+FORCE_INLINE_TEMPLATE
+size_t ZSTD_dedicatedDictSearch_lazy_search(size_t* offsetPtr, size_t ml, U32 nbAttempts,
+                                            const ZSTD_MatchState_t* const dms,
+                                            const BYTE* const ip, const BYTE* const iLimit,
+                                            const BYTE* const prefixStart, const U32 curr,
+                                            const U32 dictLimit, const size_t ddsIdx) {
+    const U32 ddsLowestIndex  = dms->window.dictLimit;
+    const BYTE* const ddsBase = dms->window.base;
+    const BYTE* const ddsEnd  = dms->window.nextSrc;
+    const U32 ddsSize         = (U32)(ddsEnd - ddsBase);
+    const U32 ddsIndexDelta   = dictLimit - ddsSize;
+    const U32 bucketSize      = (1 << ZSTD_LAZY_DDSS_BUCKET_LOG);
+    const U32 bucketLimit     = nbAttempts < bucketSize - 1 ? nbAttempts : bucketSize - 1;
+    U32 ddsAttempt;
+    U32 matchIndex;
+
+    for (ddsAttempt = 0; ddsAttempt < bucketSize - 1; ddsAttempt++) {
+        PREFETCH_L1(ddsBase + dms->hashTable[ddsIdx + ddsAttempt]);
+    }
+
+    {
+        U32 const chainPackedPointer = dms->hashTable[ddsIdx + bucketSize - 1];
+        U32 const chainIndex = chainPackedPointer >> 8;
+
+        PREFETCH_L1(&dms->chainTable[chainIndex]);
+    }
+
+    for (ddsAttempt = 0; ddsAttempt < bucketLimit; ddsAttempt++) {
+        size_t currentMl=0;
+        const BYTE* match;
+        matchIndex = dms->hashTable[ddsIdx + ddsAttempt];
+        match = ddsBase + matchIndex;
+
+        if (!matchIndex) {
+            return ml;
+        }
+
+        /* guaranteed by table construction */
+        (void)ddsLowestIndex;
+        assert(matchIndex >= ddsLowestIndex);
+        assert(match+4 <= ddsEnd);
+        if (MEM_read32(match) == MEM_read32(ip)) {
+            /* assumption : matchIndex <= dictLimit-4 (by table construction) */
+            currentMl = ZSTD_count_2segments(ip+4, match+4, iLimit, ddsEnd, prefixStart) + 4;
+        }
+
+        /* save best solution */
+        if (currentMl > ml) {
+            ml = currentMl;
+            *offsetPtr = OFFSET_TO_OFFBASE(curr - (matchIndex + ddsIndexDelta));
+            if (ip+currentMl == iLimit) {
+                /* best possible, avoids read overflow on next attempt */
+                return ml;
+            }
+        }
+    }
+
+    {
+        U32 const chainPackedPointer = dms->hashTable[ddsIdx + bucketSize - 1];
+        U32 chainIndex = chainPackedPointer >> 8;
+        U32 const chainLength = chainPackedPointer & 0xFF;
+        U32 const chainAttempts = nbAttempts - ddsAttempt;
+        U32 const chainLimit = chainAttempts > chainLength ? chainLength : chainAttempts;
+        U32 chainAttempt;
+
+        for (chainAttempt = 0 ; chainAttempt < chainLimit; chainAttempt++) {
+            PREFETCH_L1(ddsBase + dms->chainTable[chainIndex + chainAttempt]);
+        }
+
+        for (chainAttempt = 0 ; chainAttempt < chainLimit; chainAttempt++, chainIndex++) {
+            size_t currentMl=0;
+            const BYTE* match;
+            matchIndex = dms->chainTable[chainIndex];
+            match = ddsBase + matchIndex;
+
+            /* guaranteed by table construction */
+            assert(matchIndex >= ddsLowestIndex);
+            assert(match+4 <= ddsEnd);
+            if (MEM_read32(match) == MEM_read32(ip)) {
+                /* assumption : matchIndex <= dictLimit-4 (by table construction) */
+                currentMl = ZSTD_count_2segments(ip+4, match+4, iLimit, ddsEnd, prefixStart) + 4;
+            }
+
+            /* save best solution */
+            if (currentMl > ml) {
+                ml = currentMl;
+                *offsetPtr = OFFSET_TO_OFFBASE(curr - (matchIndex + ddsIndexDelta));
+                if (ip+currentMl == iLimit) break; /* best possible, avoids read overflow on next attempt */
+            }
+        }
+    }
+    return ml;
+}
+
+
+/* *********************************
+*  Hash Chain
+***********************************/
+#define NEXT_IN_CHAIN(d, mask)   chainTable[(d) & (mask)]
+
+/* Update chains up to ip (excluded)
+   Assumption : always within prefix (i.e. not within extDict) */
+FORCE_INLINE_TEMPLATE
+ZSTD_ALLOW_POINTER_OVERFLOW_ATTR
+U32 ZSTD_insertAndFindFirstIndex_internal(
+                        ZSTD_MatchState_t* ms,
+                        const ZSTD_compressionParameters* const cParams,
+                        const BYTE* ip, U32 const mls, U32 const lazySkipping)
+{
+    U32* const hashTable  = ms->hashTable;
+    const U32 hashLog = cParams->hashLog;
+    U32* const chainTable = ms->chainTable;
+    const U32 chainMask = (1 << cParams->chainLog) - 1;
+    const BYTE* const base = ms->window.base;
+    const U32 target = (U32)(ip - base);
+    U32 idx = ms->nextToUpdate;
+
+    while(idx < target) { /* catch up */
+        size_t const h = ZSTD_hashPtr(base+idx, hashLog, mls);
+        NEXT_IN_CHAIN(idx, chainMask) = hashTable[h];
+        hashTable[h] = idx;
+        idx++;
+        /* Stop inserting every position when in the lazy skipping mode. */
+        if (lazySkipping)
+            break;
+    }
+
+    ms->nextToUpdate = target;
+    return hashTable[ZSTD_hashPtr(ip, hashLog, mls)];
+}
+
+U32 ZSTD_insertAndFindFirstIndex(ZSTD_MatchState_t* ms, const BYTE* ip) {
+    const ZSTD_compressionParameters* const cParams = &ms->cParams;
+    return ZSTD_insertAndFindFirstIndex_internal(ms, cParams, ip, ms->cParams.minMatch, /* lazySkipping*/ 0);
+}
+
+/* inlining is important to hardwire a hot branch (template emulation) */
+FORCE_INLINE_TEMPLATE
+ZSTD_ALLOW_POINTER_OVERFLOW_ATTR
+size_t ZSTD_HcFindBestMatch(
+                        ZSTD_MatchState_t* ms,
+                        const BYTE* const ip, const BYTE* const iLimit,
+                        size_t* offsetPtr,
+                        const U32 mls, const ZSTD_dictMode_e dictMode)
+{
+    const ZSTD_compressionParameters* const cParams = &ms->cParams;
+    U32* const chainTable = ms->chainTable;
+    const U32 chainSize = (1 << cParams->chainLog);
+    const U32 chainMask = chainSize-1;
+    const BYTE* const base = ms->window.base;
+    const BYTE* const dictBase = ms->window.dictBase;
+    const U32 dictLimit = ms->window.dictLimit;
+    const BYTE* const prefixStart = base + dictLimit;
+    const BYTE* const dictEnd = dictBase + dictLimit;
+    const U32 curr = (U32)(ip-base);
+    const U32 maxDistance = 1U << cParams->windowLog;
+    const U32 lowestValid = ms->window.lowLimit;
+    const U32 withinMaxDistance = (curr - lowestValid > maxDistance) ? curr - maxDistance : lowestValid;
+    const U32 isDictionary = (ms->loadedDictEnd != 0);
+    const U32 lowLimit = isDictionary ? lowestValid : withinMaxDistance;
+    const U32 minChain = curr > chainSize ? curr - chainSize : 0;
+    U32 nbAttempts = 1U << cParams->searchLog;
+    size_t ml=4-1;
+
+    const ZSTD_MatchState_t* const dms = ms->dictMatchState;
+    const U32 ddsHashLog = dictMode == ZSTD_dedicatedDictSearch
+                         ? dms->cParams.hashLog - ZSTD_LAZY_DDSS_BUCKET_LOG : 0;
+    const size_t ddsIdx = dictMode == ZSTD_dedicatedDictSearch
+                        ? ZSTD_hashPtr(ip, ddsHashLog, mls) << ZSTD_LAZY_DDSS_BUCKET_LOG : 0;
+
+    U32 matchIndex;
+
+    if (dictMode == ZSTD_dedicatedDictSearch) {
+        const U32* entry = &dms->hashTable[ddsIdx];
+        PREFETCH_L1(entry);
+    }
+
+    /* HC4 match finder */
+    matchIndex = ZSTD_insertAndFindFirstIndex_internal(ms, cParams, ip, mls, ms->lazySkipping);
+
+    for ( ; (matchIndex>=lowLimit) & (nbAttempts>0) ; nbAttempts--) {
+        size_t currentMl=0;
+        if ((dictMode != ZSTD_extDict) || matchIndex >= dictLimit) {
+            const BYTE* const match = base + matchIndex;
+            assert(matchIndex >= dictLimit);   /* ensures this is true if dictMode != ZSTD_extDict */
+            /* read 4B starting from (match + ml + 1 - sizeof(U32)) */
+            if (MEM_read32(match + ml - 3) == MEM_read32(ip + ml - 3))   /* potentially better */
+                currentMl = ZSTD_count(ip, match, iLimit);
+        } else {
+            const BYTE* const match = dictBase + matchIndex;
+            assert(match+4 <= dictEnd);
+            if (MEM_read32(match) == MEM_read32(ip))   /* assumption : matchIndex <= dictLimit-4 (by table construction) */
+                currentMl = ZSTD_count_2segments(ip+4, match+4, iLimit, dictEnd, prefixStart) + 4;
+        }
+
+        /* save best solution */
+        if (currentMl > ml) {
+            ml = currentMl;
+            *offsetPtr = OFFSET_TO_OFFBASE(curr - matchIndex);
+            if (ip+currentMl == iLimit) break; /* best possible, avoids read overflow on next attempt */
+        }
+
+        if (matchIndex <= minChain) break;
+        matchIndex = NEXT_IN_CHAIN(matchIndex, chainMask);
+    }
+
+    assert(nbAttempts <= (1U << ZSTD_SEARCHLOG_MAX)); /* Check we haven't underflowed. */
+    if (dictMode == ZSTD_dedicatedDictSearch) {
+        ml = ZSTD_dedicatedDictSearch_lazy_search(offsetPtr, ml, nbAttempts, dms,
+                                                  ip, iLimit, prefixStart, curr, dictLimit, ddsIdx);
+    } else if (dictMode == ZSTD_dictMatchState) {
+        const U32* const dmsChainTable = dms->chainTable;
+        const U32 dmsChainSize         = (1 << dms->cParams.chainLog);
+        const U32 dmsChainMask         = dmsChainSize - 1;
+        const U32 dmsLowestIndex       = dms->window.dictLimit;
+        const BYTE* const dmsBase      = dms->window.base;
+        const BYTE* const dmsEnd       = dms->window.nextSrc;
+        const U32 dmsSize              = (U32)(dmsEnd - dmsBase);
+        const U32 dmsIndexDelta        = dictLimit - dmsSize;
+        const U32 dmsMinChain = dmsSize > dmsChainSize ? dmsSize - dmsChainSize : 0;
+
+        matchIndex = dms->hashTable[ZSTD_hashPtr(ip, dms->cParams.hashLog, mls)];
+
+        for ( ; (matchIndex>=dmsLowestIndex) & (nbAttempts>0) ; nbAttempts--) {
+            size_t currentMl=0;
+            const BYTE* const match = dmsBase + matchIndex;
+            assert(match+4 <= dmsEnd);
+            if (MEM_read32(match) == MEM_read32(ip))   /* assumption : matchIndex <= dictLimit-4 (by table construction) */
+                currentMl = ZSTD_count_2segments(ip+4, match+4, iLimit, dmsEnd, prefixStart) + 4;
+
+            /* save best solution */
+            if (currentMl > ml) {
+                ml = currentMl;
+                assert(curr > matchIndex + dmsIndexDelta);
+                *offsetPtr = OFFSET_TO_OFFBASE(curr - (matchIndex + dmsIndexDelta));
+                if (ip+currentMl == iLimit) break; /* best possible, avoids read overflow on next attempt */
+            }
+
+            if (matchIndex <= dmsMinChain) break;
+
+            matchIndex = dmsChainTable[matchIndex & dmsChainMask];
+        }
+    }
+
+    return ml;
+}
+
+/* *********************************
+* (SIMD) Row-based matchfinder
+***********************************/
+/* Constants for row-based hash */
+#define ZSTD_ROW_HASH_TAG_MASK ((1u << ZSTD_ROW_HASH_TAG_BITS) - 1)
+#define ZSTD_ROW_HASH_MAX_ENTRIES 64    /* absolute maximum number of entries per row, for all configurations */
+
+#define ZSTD_ROW_HASH_CACHE_MASK (ZSTD_ROW_HASH_CACHE_SIZE - 1)
+
+typedef U64 ZSTD_VecMask;   /* Clarifies when we are interacting with a U64 representing a mask of matches */
+
+/* ZSTD_VecMask_next():
+ * Starting from the LSB, returns the idx of the next non-zero bit.
+ * Basically counting the nb of trailing zeroes.
+ */
+MEM_STATIC U32 ZSTD_VecMask_next(ZSTD_VecMask val) {
+    return ZSTD_countTrailingZeros64(val);
+}
+
+/* ZSTD_row_nextIndex():
+ * Returns the next index to insert at within a tagTable row, and updates the "head"
+ * value to reflect the update. Essentially cycles backwards from [1, {entries per row})
+ */
+FORCE_INLINE_TEMPLATE U32 ZSTD_row_nextIndex(BYTE* const tagRow, U32 const rowMask) {
+    U32 next = (*tagRow-1) & rowMask;
+    next += (next == 0) ? rowMask : 0; /* skip first position */
+    *tagRow = (BYTE)next;
+    return next;
+}
+
+/* ZSTD_isAligned():
+ * Checks that a pointer is aligned to "align" bytes which must be a power of 2.
+ */
+MEM_STATIC int ZSTD_isAligned(void const* ptr, size_t align) {
+    assert((align & (align - 1)) == 0);
+    return (((size_t)ptr) & (align - 1)) == 0;
+}
+
+/* ZSTD_row_prefetch():
+ * Performs prefetching for the hashTable and tagTable at a given row.
+ */
+FORCE_INLINE_TEMPLATE void ZSTD_row_prefetch(U32 const* hashTable, BYTE const* tagTable, U32 const relRow, U32 const rowLog) {
+    PREFETCH_L1(hashTable + relRow);
+    if (rowLog >= 5) {
+        PREFETCH_L1(hashTable + relRow + 16);
+        /* Note: prefetching more of the hash table does not appear to be beneficial for 128-entry rows */
+    }
+    PREFETCH_L1(tagTable + relRow);
+    if (rowLog == 6) {
+        PREFETCH_L1(tagTable + relRow + 32);
+    }
+    assert(rowLog == 4 || rowLog == 5 || rowLog == 6);
+    assert(ZSTD_isAligned(hashTable + relRow, 64));                 /* prefetched hash row always 64-byte aligned */
+    assert(ZSTD_isAligned(tagTable + relRow, (size_t)1 << rowLog)); /* prefetched tagRow sits on correct multiple of bytes (32,64,128) */
+}
+
+/* ZSTD_row_fillHashCache():
+ * Fill up the hash cache starting at idx, prefetching up to ZSTD_ROW_HASH_CACHE_SIZE entries,
+ * but not beyond iLimit.
+ */
+FORCE_INLINE_TEMPLATE
+ZSTD_ALLOW_POINTER_OVERFLOW_ATTR
+void ZSTD_row_fillHashCache(ZSTD_MatchState_t* ms, const BYTE* base,
+                                   U32 const rowLog, U32 const mls,
+                                   U32 idx, const BYTE* const iLimit)
+{
+    U32 const* const hashTable = ms->hashTable;
+    BYTE const* const tagTable = ms->tagTable;
+    U32 const hashLog = ms->rowHashLog;
+    U32 const maxElemsToPrefetch = (base + idx) > iLimit ? 0 : (U32)(iLimit - (base + idx) + 1);
+    U32 const lim = idx + MIN(ZSTD_ROW_HASH_CACHE_SIZE, maxElemsToPrefetch);
+
+    for (; idx < lim; ++idx) {
+        U32 const hash = (U32)ZSTD_hashPtrSalted(base + idx, hashLog + ZSTD_ROW_HASH_TAG_BITS, mls, ms->hashSalt);
+        U32 const row = (hash >> ZSTD_ROW_HASH_TAG_BITS) << rowLog;
+        ZSTD_row_prefetch(hashTable, tagTable, row, rowLog);
+        ms->hashCache[idx & ZSTD_ROW_HASH_CACHE_MASK] = hash;
+    }
+
+    DEBUGLOG(6, "ZSTD_row_fillHashCache(): [%u %u %u %u %u %u %u %u]", ms->hashCache[0], ms->hashCache[1],
+                                                     ms->hashCache[2], ms->hashCache[3], ms->hashCache[4],
+                                                     ms->hashCache[5], ms->hashCache[6], ms->hashCache[7]);
+}
+
+/* ZSTD_row_nextCachedHash():
+ * Returns the hash of base + idx, and replaces the hash in the hash cache with the byte at
+ * base + idx + ZSTD_ROW_HASH_CACHE_SIZE. Also prefetches the appropriate rows from hashTable and tagTable.
+ */
+FORCE_INLINE_TEMPLATE
+ZSTD_ALLOW_POINTER_OVERFLOW_ATTR
+U32 ZSTD_row_nextCachedHash(U32* cache, U32 const* hashTable,
+                                                  BYTE const* tagTable, BYTE const* base,
+                                                  U32 idx, U32 const hashLog,
+                                                  U32 const rowLog, U32 const mls,
+                                                  U64 const hashSalt)
+{
+    U32 const newHash = (U32)ZSTD_hashPtrSalted(base+idx+ZSTD_ROW_HASH_CACHE_SIZE, hashLog + ZSTD_ROW_HASH_TAG_BITS, mls, hashSalt);
+    U32 const row = (newHash >> ZSTD_ROW_HASH_TAG_BITS) << rowLog;
+    ZSTD_row_prefetch(hashTable, tagTable, row, rowLog);
+    {   U32 const hash = cache[idx & ZSTD_ROW_HASH_CACHE_MASK];
+        cache[idx & ZSTD_ROW_HASH_CACHE_MASK] = newHash;
+        return hash;
+    }
+}
+
+/* ZSTD_row_update_internalImpl():
+ * Updates the hash table with positions starting from updateStartIdx until updateEndIdx.
+ */
+FORCE_INLINE_TEMPLATE
+ZSTD_ALLOW_POINTER_OVERFLOW_ATTR
+void ZSTD_row_update_internalImpl(ZSTD_MatchState_t* ms,
+                                  U32 updateStartIdx, U32 const updateEndIdx,
+                                  U32 const mls, U32 const rowLog,
+                                  U32 const rowMask, U32 const useCache)
+{
+    U32* const hashTable = ms->hashTable;
+    BYTE* const tagTable = ms->tagTable;
+    U32 const hashLog = ms->rowHashLog;
+    const BYTE* const base = ms->window.base;
+
+    DEBUGLOG(6, "ZSTD_row_update_internalImpl(): updateStartIdx=%u, updateEndIdx=%u", updateStartIdx, updateEndIdx);
+    for (; updateStartIdx < updateEndIdx; ++updateStartIdx) {
+        U32 const hash = useCache ? ZSTD_row_nextCachedHash(ms->hashCache, hashTable, tagTable, base, updateStartIdx, hashLog, rowLog, mls, ms->hashSalt)
+                                  : (U32)ZSTD_hashPtrSalted(base + updateStartIdx, hashLog + ZSTD_ROW_HASH_TAG_BITS, mls, ms->hashSalt);
+        U32 const relRow = (hash >> ZSTD_ROW_HASH_TAG_BITS) << rowLog;
+        U32* const row = hashTable + relRow;
+        BYTE* tagRow = tagTable + relRow;
+        U32 const pos = ZSTD_row_nextIndex(tagRow, rowMask);
+
+        assert(hash == ZSTD_hashPtrSalted(base + updateStartIdx, hashLog + ZSTD_ROW_HASH_TAG_BITS, mls, ms->hashSalt));
+        tagRow[pos] = hash & ZSTD_ROW_HASH_TAG_MASK;
+        row[pos] = updateStartIdx;
+    }
+}
+
+/* ZSTD_row_update_internal():
+ * Inserts the byte at ip into the appropriate position in the hash table, and updates ms->nextToUpdate.
+ * Skips sections of long matches as is necessary.
+ */
+FORCE_INLINE_TEMPLATE
+ZSTD_ALLOW_POINTER_OVERFLOW_ATTR
+void ZSTD_row_update_internal(ZSTD_MatchState_t* ms, const BYTE* ip,
+                              U32 const mls, U32 const rowLog,
+                              U32 const rowMask, U32 const useCache)
+{
+    U32 idx = ms->nextToUpdate;
+    const BYTE* const base = ms->window.base;
+    const U32 target = (U32)(ip - base);
+    const U32 kSkipThreshold = 384;
+    const U32 kMaxMatchStartPositionsToUpdate = 96;
+    const U32 kMaxMatchEndPositionsToUpdate = 32;
+
+    if (useCache) {
+        /* Only skip positions when using hash cache, i.e.
+         * if we are loading a dict, don't skip anything.
+         * If we decide to skip, then we only update a set number
+         * of positions at the beginning and end of the match.
+         */
+        if (UNLIKELY(target - idx > kSkipThreshold)) {
+            U32 const bound = idx + kMaxMatchStartPositionsToUpdate;
+            ZSTD_row_update_internalImpl(ms, idx, bound, mls, rowLog, rowMask, useCache);
+            idx = target - kMaxMatchEndPositionsToUpdate;
+            ZSTD_row_fillHashCache(ms, base, rowLog, mls, idx, ip+1);
+        }
+    }
+    assert(target >= idx);
+    ZSTD_row_update_internalImpl(ms, idx, target, mls, rowLog, rowMask, useCache);
+    ms->nextToUpdate = target;
+}
+
+/* ZSTD_row_update():
+ * External wrapper for ZSTD_row_update_internal(). Used for filling the hashtable during dictionary
+ * processing.
+ */
+void ZSTD_row_update(ZSTD_MatchState_t* const ms, const BYTE* ip) {
+    const U32 rowLog = BOUNDED(4, ms->cParams.searchLog, 6);
+    const U32 rowMask = (1u << rowLog) - 1;
+    const U32 mls = MIN(ms->cParams.minMatch, 6 /* mls caps out at 6 */);
+
+    DEBUGLOG(5, "ZSTD_row_update(), rowLog=%u", rowLog);
+    ZSTD_row_update_internal(ms, ip, mls, rowLog, rowMask, 0 /* don't use cache */);
+}
+
+/* Returns the mask width of bits group of which will be set to 1. Given not all
+ * architectures have easy movemask instruction, this helps to iterate over
+ * groups of bits easier and faster.
+ */
+FORCE_INLINE_TEMPLATE U32
+ZSTD_row_matchMaskGroupWidth(const U32 rowEntries)
+{
+    assert((rowEntries == 16) || (rowEntries == 32) || rowEntries == 64);
+    assert(rowEntries <= ZSTD_ROW_HASH_MAX_ENTRIES);
+    (void)rowEntries;
+#if defined(ZSTD_ARCH_ARM_NEON)
+    /* NEON path only works for little endian */
+    if (!MEM_isLittleEndian()) {
+        return 1;
+    }
+    if (rowEntries == 16) {
+        return 4;
+    }
+    if (rowEntries == 32) {
+        return 2;
+    }
+    if (rowEntries == 64) {
+        return 1;
+    }
+#endif
+    return 1;
+}
+
+#if defined(ZSTD_ARCH_X86_SSE2)
+FORCE_INLINE_TEMPLATE ZSTD_VecMask
+ZSTD_row_getSSEMask(int nbChunks, const BYTE* const src, const BYTE tag, const U32 head)
+{
+    const __m128i comparisonMask = _mm_set1_epi8((char)tag);
+    int matches[4] = {0};
+    int i;
+    assert(nbChunks == 1 || nbChunks == 2 || nbChunks == 4);
+    for (i=0; i<nbChunks; i++) {
+        const __m128i chunk = _mm_loadu_si128((const __m128i*)(const void*)(src + 16*i));
+        const __m128i equalMask = _mm_cmpeq_epi8(chunk, comparisonMask);
+        matches[i] = _mm_movemask_epi8(equalMask);
+    }
+    if (nbChunks == 1) return ZSTD_rotateRight_U16((U16)matches[0], head);
+    if (nbChunks == 2) return ZSTD_rotateRight_U32((U32)matches[1] << 16 | (U32)matches[0], head);
+    assert(nbChunks == 4);
+    return ZSTD_rotateRight_U64((U64)matches[3] << 48 | (U64)matches[2] << 32 | (U64)matches[1] << 16 | (U64)matches[0], head);
+}
+#endif
+
+#if defined(ZSTD_ARCH_ARM_NEON)
+FORCE_INLINE_TEMPLATE ZSTD_VecMask
+ZSTD_row_getNEONMask(const U32 rowEntries, const BYTE* const src, const BYTE tag, const U32 headGrouped)
+{
+    assert((rowEntries == 16) || (rowEntries == 32) || rowEntries == 64);
+    if (rowEntries == 16) {
+        /* vshrn_n_u16 shifts by 4 every u16 and narrows to 8 lower bits.
+         * After that groups of 4 bits represent the equalMask. We lower
+         * all bits except the highest in these groups by doing AND with
+         * 0x88 = 0b10001000.
+         */
+        const uint8x16_t chunk = vld1q_u8(src);
+        const uint16x8_t equalMask = vreinterpretq_u16_u8(vceqq_u8(chunk, vdupq_n_u8(tag)));
+        const uint8x8_t res = vshrn_n_u16(equalMask, 4);
+        const U64 matches = vget_lane_u64(vreinterpret_u64_u8(res), 0);
+        return ZSTD_rotateRight_U64(matches, headGrouped) & 0x8888888888888888ull;
+    } else if (rowEntries == 32) {
+        /* Same idea as with rowEntries == 16 but doing AND with
+         * 0x55 = 0b01010101.
+         */
+        const uint16x8x2_t chunk = vld2q_u16((const uint16_t*)(const void*)src);
+        const uint8x16_t chunk0 = vreinterpretq_u8_u16(chunk.val[0]);
+        const uint8x16_t chunk1 = vreinterpretq_u8_u16(chunk.val[1]);
+        const uint8x16_t dup = vdupq_n_u8(tag);
+        const uint8x8_t t0 = vshrn_n_u16(vreinterpretq_u16_u8(vceqq_u8(chunk0, dup)), 6);
+        const uint8x8_t t1 = vshrn_n_u16(vreinterpretq_u16_u8(vceqq_u8(chunk1, dup)), 6);
+        const uint8x8_t res = vsli_n_u8(t0, t1, 4);
+        const U64 matches = vget_lane_u64(vreinterpret_u64_u8(res), 0) ;
+        return ZSTD_rotateRight_U64(matches, headGrouped) & 0x5555555555555555ull;
+    } else { /* rowEntries == 64 */
+        const uint8x16x4_t chunk = vld4q_u8(src);
+        const uint8x16_t dup = vdupq_n_u8(tag);
+        const uint8x16_t cmp0 = vceqq_u8(chunk.val[0], dup);
+        const uint8x16_t cmp1 = vceqq_u8(chunk.val[1], dup);
+        const uint8x16_t cmp2 = vceqq_u8(chunk.val[2], dup);
+        const uint8x16_t cmp3 = vceqq_u8(chunk.val[3], dup);
+
+        const uint8x16_t t0 = vsriq_n_u8(cmp1, cmp0, 1);
+        const uint8x16_t t1 = vsriq_n_u8(cmp3, cmp2, 1);
+        const uint8x16_t t2 = vsriq_n_u8(t1, t0, 2);
+        const uint8x16_t t3 = vsriq_n_u8(t2, t2, 4);
+        const uint8x8_t t4 = vshrn_n_u16(vreinterpretq_u16_u8(t3), 4);
+        const U64 matches = vget_lane_u64(vreinterpret_u64_u8(t4), 0);
+        return ZSTD_rotateRight_U64(matches, headGrouped);
+    }
+}
+#endif
+
+/* Returns a ZSTD_VecMask (U64) that has the nth group (determined by
+ * ZSTD_row_matchMaskGroupWidth) of bits set to 1 if the newly-computed "tag"
+ * matches the hash at the nth position in a row of the tagTable.
+ * Each row is a circular buffer beginning at the value of "headGrouped". So we
+ * must rotate the "matches" bitfield to match up with the actual layout of the
+ * entries within the hashTable */
+FORCE_INLINE_TEMPLATE ZSTD_VecMask
+ZSTD_row_getMatchMask(const BYTE* const tagRow, const BYTE tag, const U32 headGrouped, const U32 rowEntries)
+{
+    const BYTE* const src = tagRow;
+    assert((rowEntries == 16) || (rowEntries == 32) || rowEntries == 64);
+    assert(rowEntries <= ZSTD_ROW_HASH_MAX_ENTRIES);
+    assert(ZSTD_row_matchMaskGroupWidth(rowEntries) * rowEntries <= sizeof(ZSTD_VecMask) * 8);
+
+#if defined(ZSTD_ARCH_X86_SSE2)
+
+    return ZSTD_row_getSSEMask(rowEntries / 16, src, tag, headGrouped);
+
+#else /* SW or NEON-LE */
+
+# if defined(ZSTD_ARCH_ARM_NEON)
+  /* This NEON path only works for little endian - otherwise use SWAR below */
+    if (MEM_isLittleEndian()) {
+        return ZSTD_row_getNEONMask(rowEntries, src, tag, headGrouped);
+    }
+# endif /* ZSTD_ARCH_ARM_NEON */
+    /* SWAR */
+    {   const int chunkSize = sizeof(size_t);
+        const size_t shiftAmount = ((chunkSize * 8) - chunkSize);
+        const size_t xFF = ~((size_t)0);
+        const size_t x01 = xFF / 0xFF;
+        const size_t x80 = x01 << 7;
+        const size_t splatChar = tag * x01;
+        ZSTD_VecMask matches = 0;
+        int i = rowEntries - chunkSize;
+        assert((sizeof(size_t) == 4) || (sizeof(size_t) == 8));
+        if (MEM_isLittleEndian()) { /* runtime check so have two loops */
+            const size_t extractMagic = (xFF / 0x7F) >> chunkSize;
+            do {
+                size_t chunk = MEM_readST(&src[i]);
+                chunk ^= splatChar;
+                chunk = (((chunk | x80) - x01) | chunk) & x80;
+                matches <<= chunkSize;
+                matches |= (chunk * extractMagic) >> shiftAmount;
+                i -= chunkSize;
+            } while (i >= 0);
+        } else { /* big endian: reverse bits during extraction */
+            const size_t msb = xFF ^ (xFF >> 1);
+            const size_t extractMagic = (msb / 0x1FF) | msb;
+            do {
+                size_t chunk = MEM_readST(&src[i]);
+                chunk ^= splatChar;
+                chunk = (((chunk | x80) - x01) | chunk) & x80;
+                matches <<= chunkSize;
+                matches |= ((chunk >> 7) * extractMagic) >> shiftAmount;
+                i -= chunkSize;
+            } while (i >= 0);
+        }
+        matches = ~matches;
+        if (rowEntries == 16) {
+            return ZSTD_rotateRight_U16((U16)matches, headGrouped);
+        } else if (rowEntries == 32) {
+            return ZSTD_rotateRight_U32((U32)matches, headGrouped);
+        } else {
+            return ZSTD_rotateRight_U64((U64)matches, headGrouped);
+        }
+    }
+#endif
+}
+
+/* The high-level approach of the SIMD row based match finder is as follows:
+ * - Figure out where to insert the new entry:
+ *      - Generate a hash for current input position and split it into a one byte of tag and `rowHashLog` bits of index.
+ *           - The hash is salted by a value that changes on every context reset, so when the same table is used
+ *             we will avoid collisions that would otherwise slow us down by introducing phantom matches.
+ *      - The hashTable is effectively split into groups or "rows" of 15 or 31 entries of U32, and the index determines
+ *        which row to insert into.
+ *      - Determine the correct position within the row to insert the entry into. Each row of 15 or 31 can
+ *        be considered as a circular buffer with a "head" index that resides in the tagTable (overall 16 or 32 bytes
+ *        per row).
+ * - Use SIMD to efficiently compare the tags in the tagTable to the 1-byte tag calculated for the position and
+ *   generate a bitfield that we can cycle through to check the collisions in the hash table.
+ * - Pick the longest match.
+ * - Insert the tag into the equivalent row and position in the tagTable.
+ */
+FORCE_INLINE_TEMPLATE
+ZSTD_ALLOW_POINTER_OVERFLOW_ATTR
+size_t ZSTD_RowFindBestMatch(
+                        ZSTD_MatchState_t* ms,
+                        const BYTE* const ip, const BYTE* const iLimit,
+                        size_t* offsetPtr,
+                        const U32 mls, const ZSTD_dictMode_e dictMode,
+                        const U32 rowLog)
+{
+    U32* const hashTable = ms->hashTable;
+    BYTE* const tagTable = ms->tagTable;
+    U32* const hashCache = ms->hashCache;
+    const U32 hashLog = ms->rowHashLog;
+    const ZSTD_compressionParameters* const cParams = &ms->cParams;
+    const BYTE* const base = ms->window.base;
+    const BYTE* const dictBase = ms->window.dictBase;
+    const U32 dictLimit = ms->window.dictLimit;
+    const BYTE* const prefixStart = base + dictLimit;
+    const BYTE* const dictEnd = dictBase + dictLimit;
+    const U32 curr = (U32)(ip-base);
+    const U32 maxDistance = 1U << cParams->windowLog;
+    const U32 lowestValid = ms->window.lowLimit;
+    const U32 withinMaxDistance = (curr - lowestValid > maxDistance) ? curr - maxDistance : lowestValid;
+    const U32 isDictionary = (ms->loadedDictEnd != 0);
+    const U32 lowLimit = isDictionary ? lowestValid : withinMaxDistance;
+    const U32 rowEntries = (1U << rowLog);
+    const U32 rowMask = rowEntries - 1;
+    const U32 cappedSearchLog = MIN(cParams->searchLog, rowLog); /* nb of searches is capped at nb entries per row */
+    const U32 groupWidth = ZSTD_row_matchMaskGroupWidth(rowEntries);
+    const U64 hashSalt = ms->hashSalt;
+    U32 nbAttempts = 1U << cappedSearchLog;
+    size_t ml=4-1;
+    U32 hash;
+
+    /* DMS/DDS variables that may be referenced laster */
+    const ZSTD_MatchState_t* const dms = ms->dictMatchState;
+
+    /* Initialize the following variables to satisfy static analyzer */
+    size_t ddsIdx = 0;
+    U32 ddsExtraAttempts = 0; /* cctx hash tables are limited in searches, but allow extra searches into DDS */
+    U32 dmsTag = 0;
+    U32* dmsRow = NULL;
+    BYTE* dmsTagRow = NULL;
+
+    if (dictMode == ZSTD_dedicatedDictSearch) {
+        const U32 ddsHashLog = dms->cParams.hashLog - ZSTD_LAZY_DDSS_BUCKET_LOG;
+        {   /* Prefetch DDS hashtable entry */
+            ddsIdx = ZSTD_hashPtr(ip, ddsHashLog, mls) << ZSTD_LAZY_DDSS_BUCKET_LOG;
+            PREFETCH_L1(&dms->hashTable[ddsIdx]);
+        }
+        ddsExtraAttempts = cParams->searchLog > rowLog ? 1U << (cParams->searchLog - rowLog) : 0;
+    }
+
+    if (dictMode == ZSTD_dictMatchState) {
+        /* Prefetch DMS rows */
+        U32* const dmsHashTable = dms->hashTable;
+        BYTE* const dmsTagTable = dms->tagTable;
+        U32 const dmsHash = (U32)ZSTD_hashPtr(ip, dms->rowHashLog + ZSTD_ROW_HASH_TAG_BITS, mls);
+        U32 const dmsRelRow = (dmsHash >> ZSTD_ROW_HASH_TAG_BITS) << rowLog;
+        dmsTag = dmsHash & ZSTD_ROW_HASH_TAG_MASK;
+        dmsTagRow = (BYTE*)(dmsTagTable + dmsRelRow);
+        dmsRow = dmsHashTable + dmsRelRow;
+        ZSTD_row_prefetch(dmsHashTable, dmsTagTable, dmsRelRow, rowLog);
+    }
+
+    /* Update the hashTable and tagTable up to (but not including) ip */
+    if (!ms->lazySkipping) {
+        ZSTD_row_update_internal(ms, ip, mls, rowLog, rowMask, 1 /* useCache */);
+        hash = ZSTD_row_nextCachedHash(hashCache, hashTable, tagTable, base, curr, hashLog, rowLog, mls, hashSalt);
+    } else {
+        /* Stop inserting every position when in the lazy skipping mode.
+         * The hash cache is also not kept up to date in this mode.
+         */
+        hash = (U32)ZSTD_hashPtrSalted(ip, hashLog + ZSTD_ROW_HASH_TAG_BITS, mls, hashSalt);
+        ms->nextToUpdate = curr;
+    }
+    ms->hashSaltEntropy += hash; /* collect salt entropy */
+
+    {   /* Get the hash for ip, compute the appropriate row */
+        U32 const relRow = (hash >> ZSTD_ROW_HASH_TAG_BITS) << rowLog;
+        U32 const tag = hash & ZSTD_ROW_HASH_TAG_MASK;
+        U32* const row = hashTable + relRow;
+        BYTE* tagRow = (BYTE*)(tagTable + relRow);
+        U32 const headGrouped = (*tagRow & rowMask) * groupWidth;
+        U32 matchBuffer[ZSTD_ROW_HASH_MAX_ENTRIES];
+        size_t numMatches = 0;
+        size_t currMatch = 0;
+        ZSTD_VecMask matches = ZSTD_row_getMatchMask(tagRow, (BYTE)tag, headGrouped, rowEntries);
+
+        /* Cycle through the matches and prefetch */
+        for (; (matches > 0) && (nbAttempts > 0); matches &= (matches - 1)) {
+            U32 const matchPos = ((headGrouped + ZSTD_VecMask_next(matches)) / groupWidth) & rowMask;
+            U32 const matchIndex = row[matchPos];
+            if(matchPos == 0) continue;
+            assert(numMatches < rowEntries);
+            if (matchIndex < lowLimit)
+                break;
+            if ((dictMode != ZSTD_extDict) || matchIndex >= dictLimit) {
+                PREFETCH_L1(base + matchIndex);
+            } else {
+                PREFETCH_L1(dictBase + matchIndex);
+            }
+            matchBuffer[numMatches++] = matchIndex;
+            --nbAttempts;
+        }
+
+        /* Speed opt: insert current byte into hashtable too. This allows us to avoid one iteration of the loop
+           in ZSTD_row_update_internal() at the next search. */
+        {
+            U32 const pos = ZSTD_row_nextIndex(tagRow, rowMask);
+            tagRow[pos] = (BYTE)tag;
+            row[pos] = ms->nextToUpdate++;
+        }
+
+        /* Return the longest match */
+        for (; currMatch < numMatches; ++currMatch) {
+            U32 const matchIndex = matchBuffer[currMatch];
+            size_t currentMl=0;
+            assert(matchIndex < curr);
+            assert(matchIndex >= lowLimit);
+
+            if ((dictMode != ZSTD_extDict) || matchIndex >= dictLimit) {
+                const BYTE* const match = base + matchIndex;
+                assert(matchIndex >= dictLimit);   /* ensures this is true if dictMode != ZSTD_extDict */
+                /* read 4B starting from (match + ml + 1 - sizeof(U32)) */
+                if (MEM_read32(match + ml - 3) == MEM_read32(ip + ml - 3))   /* potentially better */
+                    currentMl = ZSTD_count(ip, match, iLimit);
+            } else {
+                const BYTE* const match = dictBase + matchIndex;
+                assert(match+4 <= dictEnd);
+                if (MEM_read32(match) == MEM_read32(ip))   /* assumption : matchIndex <= dictLimit-4 (by table construction) */
+                    currentMl = ZSTD_count_2segments(ip+4, match+4, iLimit, dictEnd, prefixStart) + 4;
+            }
+
+            /* Save best solution */
+            if (currentMl > ml) {
+                ml = currentMl;
+                *offsetPtr = OFFSET_TO_OFFBASE(curr - matchIndex);
+                if (ip+currentMl == iLimit) break; /* best possible, avoids read overflow on next attempt */
+            }
+        }
+    }
+
+    assert(nbAttempts <= (1U << ZSTD_SEARCHLOG_MAX)); /* Check we haven't underflowed. */
+    if (dictMode == ZSTD_dedicatedDictSearch) {
+        ml = ZSTD_dedicatedDictSearch_lazy_search(offsetPtr, ml, nbAttempts + ddsExtraAttempts, dms,
+                                                  ip, iLimit, prefixStart, curr, dictLimit, ddsIdx);
+    } else if (dictMode == ZSTD_dictMatchState) {
+        /* TODO: Measure and potentially add prefetching to DMS */
+        const U32 dmsLowestIndex       = dms->window.dictLimit;
+        const BYTE* const dmsBase      = dms->window.base;
+        const BYTE* const dmsEnd       = dms->window.nextSrc;
+        const U32 dmsSize              = (U32)(dmsEnd - dmsBase);
+        const U32 dmsIndexDelta        = dictLimit - dmsSize;
+
+        {   U32 const headGrouped = (*dmsTagRow & rowMask) * groupWidth;
+            U32 matchBuffer[ZSTD_ROW_HASH_MAX_ENTRIES];
+            size_t numMatches = 0;
+            size_t currMatch = 0;
+            ZSTD_VecMask matches = ZSTD_row_getMatchMask(dmsTagRow, (BYTE)dmsTag, headGrouped, rowEntries);
+
+            for (; (matches > 0) && (nbAttempts > 0); matches &= (matches - 1)) {
+                U32 const matchPos = ((headGrouped + ZSTD_VecMask_next(matches)) / groupWidth) & rowMask;
+                U32 const matchIndex = dmsRow[matchPos];
+                if(matchPos == 0) continue;
+                if (matchIndex < dmsLowestIndex)
+                    break;
+                PREFETCH_L1(dmsBase + matchIndex);
+                matchBuffer[numMatches++] = matchIndex;
+                --nbAttempts;
+            }
+
+            /* Return the longest match */
+            for (; currMatch < numMatches; ++currMatch) {
+                U32 const matchIndex = matchBuffer[currMatch];
+                size_t currentMl=0;
+                assert(matchIndex >= dmsLowestIndex);
+                assert(matchIndex < curr);
+
+                {   const BYTE* const match = dmsBase + matchIndex;
+                    assert(match+4 <= dmsEnd);
+                    if (MEM_read32(match) == MEM_read32(ip))
+                        currentMl = ZSTD_count_2segments(ip+4, match+4, iLimit, dmsEnd, prefixStart) + 4;
+                }
+
+                if (currentMl > ml) {
+                    ml = currentMl;
+                    assert(curr > matchIndex + dmsIndexDelta);
+                    *offsetPtr = OFFSET_TO_OFFBASE(curr - (matchIndex + dmsIndexDelta));
+                    if (ip+currentMl == iLimit) break;
+                }
+            }
+        }
+    }
+    return ml;
+}
+
+
+/**
+ * Generate search functions templated on (dictMode, mls, rowLog).
+ * These functions are outlined for code size & compilation time.
+ * ZSTD_searchMax() dispatches to the correct implementation function.
+ *
+ * TODO: The start of the search function involves loading and calculating a
+ * bunch of constants from the ZSTD_MatchState_t. These computations could be
+ * done in an initialization function, and saved somewhere in the match state.
+ * Then we could pass a pointer to the saved state instead of the match state,
+ * and avoid duplicate computations.
+ *
+ * TODO: Move the match re-winding into searchMax. This improves compression
+ * ratio, and unlocks further simplifications with the next TODO.
+ *
+ * TODO: Try moving the repcode search into searchMax. After the re-winding
+ * and repcode search are in searchMax, there is no more logic in the match
+ * finder loop that requires knowledge about the dictMode. So we should be
+ * able to avoid force inlining it, and we can join the extDict loop with
+ * the single segment loop. It should go in searchMax instead of its own
+ * function to avoid having multiple virtual function calls per search.
+ */
+
+#define ZSTD_BT_SEARCH_FN(dictMode, mls) ZSTD_BtFindBestMatch_##dictMode##_##mls
+#define ZSTD_HC_SEARCH_FN(dictMode, mls) ZSTD_HcFindBestMatch_##dictMode##_##mls
+#define ZSTD_ROW_SEARCH_FN(dictMode, mls, rowLog) ZSTD_RowFindBestMatch_##dictMode##_##mls##_##rowLog
+
+#define ZSTD_SEARCH_FN_ATTRS FORCE_NOINLINE
+
+#define GEN_ZSTD_BT_SEARCH_FN(dictMode, mls)                                           \
+    ZSTD_SEARCH_FN_ATTRS size_t ZSTD_BT_SEARCH_FN(dictMode, mls)(                      \
+            ZSTD_MatchState_t* ms,                                                     \
+            const BYTE* ip, const BYTE* const iLimit,                                  \
+            size_t* offBasePtr)                                                        \
+    {                                                                                  \
+        assert(MAX(4, MIN(6, ms->cParams.minMatch)) == mls);                           \
+        return ZSTD_BtFindBestMatch(ms, ip, iLimit, offBasePtr, mls, ZSTD_##dictMode); \
+    }                                                                                  \
+
+#define GEN_ZSTD_HC_SEARCH_FN(dictMode, mls)                                          \
+    ZSTD_SEARCH_FN_ATTRS size_t ZSTD_HC_SEARCH_FN(dictMode, mls)(                     \
+            ZSTD_MatchState_t* ms,                                                    \
+            const BYTE* ip, const BYTE* const iLimit,                                 \
+            size_t* offsetPtr)                                                        \
+    {                                                                                 \
+        assert(MAX(4, MIN(6, ms->cParams.minMatch)) == mls);                          \
+        return ZSTD_HcFindBestMatch(ms, ip, iLimit, offsetPtr, mls, ZSTD_##dictMode); \
+    }                                                                                 \
+
+#define GEN_ZSTD_ROW_SEARCH_FN(dictMode, mls, rowLog)                                          \
+    ZSTD_SEARCH_FN_ATTRS size_t ZSTD_ROW_SEARCH_FN(dictMode, mls, rowLog)(                     \
+            ZSTD_MatchState_t* ms,                                                             \
+            const BYTE* ip, const BYTE* const iLimit,                                          \
+            size_t* offsetPtr)                                                                 \
+    {                                                                                          \
+        assert(MAX(4, MIN(6, ms->cParams.minMatch)) == mls);                                   \
+        assert(MAX(4, MIN(6, ms->cParams.searchLog)) == rowLog);                               \
+        return ZSTD_RowFindBestMatch(ms, ip, iLimit, offsetPtr, mls, ZSTD_##dictMode, rowLog); \
+    }                                                                                          \
+
+#define ZSTD_FOR_EACH_ROWLOG(X, dictMode, mls) \
+    X(dictMode, mls, 4)                        \
+    X(dictMode, mls, 5)                        \
+    X(dictMode, mls, 6)
+
+#define ZSTD_FOR_EACH_MLS_ROWLOG(X, dictMode) \
+    ZSTD_FOR_EACH_ROWLOG(X, dictMode, 4)      \
+    ZSTD_FOR_EACH_ROWLOG(X, dictMode, 5)      \
+    ZSTD_FOR_EACH_ROWLOG(X, dictMode, 6)
+
+#define ZSTD_FOR_EACH_MLS(X, dictMode) \
+    X(dictMode, 4)                     \
+    X(dictMode, 5)                     \
+    X(dictMode, 6)
+
+#define ZSTD_FOR_EACH_DICT_MODE(X, ...) \
+    X(__VA_ARGS__, noDict)              \
+    X(__VA_ARGS__, extDict)             \
+    X(__VA_ARGS__, dictMatchState)      \
+    X(__VA_ARGS__, dedicatedDictSearch)
+
+/* Generate row search fns for each combination of (dictMode, mls, rowLog) */
+ZSTD_FOR_EACH_DICT_MODE(ZSTD_FOR_EACH_MLS_ROWLOG, GEN_ZSTD_ROW_SEARCH_FN)
+/* Generate binary Tree search fns for each combination of (dictMode, mls) */
+ZSTD_FOR_EACH_DICT_MODE(ZSTD_FOR_EACH_MLS, GEN_ZSTD_BT_SEARCH_FN)
+/* Generate hash chain search fns for each combination of (dictMode, mls) */
+ZSTD_FOR_EACH_DICT_MODE(ZSTD_FOR_EACH_MLS, GEN_ZSTD_HC_SEARCH_FN)
+
+typedef enum { search_hashChain=0, search_binaryTree=1, search_rowHash=2 } searchMethod_e;
+
+#define GEN_ZSTD_CALL_BT_SEARCH_FN(dictMode, mls)                         \
+    case mls:                                                             \
+        return ZSTD_BT_SEARCH_FN(dictMode, mls)(ms, ip, iend, offsetPtr);
+#define GEN_ZSTD_CALL_HC_SEARCH_FN(dictMode, mls)                         \
+    case mls:                                                             \
+        return ZSTD_HC_SEARCH_FN(dictMode, mls)(ms, ip, iend, offsetPtr);
+#define GEN_ZSTD_CALL_ROW_SEARCH_FN(dictMode, mls, rowLog)                         \
+    case rowLog:                                                                   \
+        return ZSTD_ROW_SEARCH_FN(dictMode, mls, rowLog)(ms, ip, iend, offsetPtr);
+
+#define ZSTD_SWITCH_MLS(X, dictMode)   \
+    switch (mls) {                     \
+        ZSTD_FOR_EACH_MLS(X, dictMode) \
+    }
+
+#define ZSTD_SWITCH_ROWLOG(dictMode, mls)                                    \
+    case mls:                                                                \
+        switch (rowLog) {                                                    \
+            ZSTD_FOR_EACH_ROWLOG(GEN_ZSTD_CALL_ROW_SEARCH_FN, dictMode, mls) \
+        }                                                                    \
+        ZSTD_UNREACHABLE;                                                    \
+        break;
+
+#define ZSTD_SWITCH_SEARCH_METHOD(dictMode)                       \
+    switch (searchMethod) {                                       \
+        case search_hashChain:                                    \
+            ZSTD_SWITCH_MLS(GEN_ZSTD_CALL_HC_SEARCH_FN, dictMode) \
+            break;                                                \
+        case search_binaryTree:                                   \
+            ZSTD_SWITCH_MLS(GEN_ZSTD_CALL_BT_SEARCH_FN, dictMode) \
+            break;                                                \
+        case search_rowHash:                                      \
+            ZSTD_SWITCH_MLS(ZSTD_SWITCH_ROWLOG, dictMode)         \
+            break;                                                \
+    }                                                             \
+    ZSTD_UNREACHABLE;
+
+/**
+ * Searches for the longest match at @p ip.
+ * Dispatches to the correct implementation function based on the
+ * (searchMethod, dictMode, mls, rowLog). We use switch statements
+ * here instead of using an indirect function call through a function
+ * pointer because after Spectre and Meltdown mitigations, indirect
+ * function calls can be very costly, especially in the kernel.
+ *
+ * NOTE: dictMode and searchMethod should be templated, so those switch
+ * statements should be optimized out. Only the mls & rowLog switches
+ * should be left.
+ *
+ * @param ms The match state.
+ * @param ip The position to search at.
+ * @param iend The end of the input data.
+ * @param[out] offsetPtr Stores the match offset into this pointer.
+ * @param mls The minimum search length, in the range [4, 6].
+ * @param rowLog The row log (if applicable), in the range [4, 6].
+ * @param searchMethod The search method to use (templated).
+ * @param dictMode The dictMode (templated).
+ *
+ * @returns The length of the longest match found, or < mls if no match is found.
+ * If a match is found its offset is stored in @p offsetPtr.
+ */
+FORCE_INLINE_TEMPLATE size_t ZSTD_searchMax(
+    ZSTD_MatchState_t* ms,
+    const BYTE* ip,
+    const BYTE* iend,
+    size_t* offsetPtr,
+    U32 const mls,
+    U32 const rowLog,
+    searchMethod_e const searchMethod,
+    ZSTD_dictMode_e const dictMode)
+{
+    if (dictMode == ZSTD_noDict) {
+        ZSTD_SWITCH_SEARCH_METHOD(noDict)
+    } else if (dictMode == ZSTD_extDict) {
+        ZSTD_SWITCH_SEARCH_METHOD(extDict)
+    } else if (dictMode == ZSTD_dictMatchState) {
+        ZSTD_SWITCH_SEARCH_METHOD(dictMatchState)
+    } else if (dictMode == ZSTD_dedicatedDictSearch) {
+        ZSTD_SWITCH_SEARCH_METHOD(dedicatedDictSearch)
+    }
+    ZSTD_UNREACHABLE;
+    return 0;
+}
+
+/* *******************************
+*  Common parser - lazy strategy
+*********************************/
+
+FORCE_INLINE_TEMPLATE
+ZSTD_ALLOW_POINTER_OVERFLOW_ATTR
+size_t ZSTD_compressBlock_lazy_generic(
+                        ZSTD_MatchState_t* ms, SeqStore_t* seqStore,
+                        U32 rep[ZSTD_REP_NUM],
+                        const void* src, size_t srcSize,
+                        const searchMethod_e searchMethod, const U32 depth,
+                        ZSTD_dictMode_e const dictMode)
+{
+    const BYTE* const istart = (const BYTE*)src;
+    const BYTE* ip = istart;
+    const BYTE* anchor = istart;
+    const BYTE* const iend = istart + srcSize;
+    const BYTE* const ilimit = (searchMethod == search_rowHash) ? iend - 8 - ZSTD_ROW_HASH_CACHE_SIZE : iend - 8;
+    const BYTE* const base = ms->window.base;
+    const U32 prefixLowestIndex = ms->window.dictLimit;
+    const BYTE* const prefixLowest = base + prefixLowestIndex;
+    const U32 mls = BOUNDED(4, ms->cParams.minMatch, 6);
+    const U32 rowLog = BOUNDED(4, ms->cParams.searchLog, 6);
+
+    U32 offset_1 = rep[0], offset_2 = rep[1];
+    U32 offsetSaved1 = 0, offsetSaved2 = 0;
+
+    const int isDMS = dictMode == ZSTD_dictMatchState;
+    const int isDDS = dictMode == ZSTD_dedicatedDictSearch;
+    const int isDxS = isDMS || isDDS;
+    const ZSTD_MatchState_t* const dms = ms->dictMatchState;
+    const U32 dictLowestIndex      = isDxS ? dms->window.dictLimit : 0;
+    const BYTE* const dictBase     = isDxS ? dms->window.base : NULL;
+    const BYTE* const dictLowest   = isDxS ? dictBase + dictLowestIndex : NULL;
+    const BYTE* const dictEnd      = isDxS ? dms->window.nextSrc : NULL;
+    const U32 dictIndexDelta       = isDxS ?
+                                     prefixLowestIndex - (U32)(dictEnd - dictBase) :
+                                     0;
+    const U32 dictAndPrefixLength = (U32)((ip - prefixLowest) + (dictEnd - dictLowest));
+
+    DEBUGLOG(5, "ZSTD_compressBlock_lazy_generic (dictMode=%u) (searchFunc=%u)", (U32)dictMode, (U32)searchMethod);
+    ip += (dictAndPrefixLength == 0);
+    if (dictMode == ZSTD_noDict) {
+        U32 const curr = (U32)(ip - base);
+        U32 const windowLow = ZSTD_getLowestPrefixIndex(ms, curr, ms->cParams.windowLog);
+        U32 const maxRep = curr - windowLow;
+        if (offset_2 > maxRep) offsetSaved2 = offset_2, offset_2 = 0;
+        if (offset_1 > maxRep) offsetSaved1 = offset_1, offset_1 = 0;
+    }
+    if (isDxS) {
+        /* dictMatchState repCode checks don't currently handle repCode == 0
+         * disabling. */
+        assert(offset_1 <= dictAndPrefixLength);
+        assert(offset_2 <= dictAndPrefixLength);
+    }
+
+    /* Reset the lazy skipping state */
+    ms->lazySkipping = 0;
+
+    if (searchMethod == search_rowHash) {
+        ZSTD_row_fillHashCache(ms, base, rowLog, mls, ms->nextToUpdate, ilimit);
+    }
+
+    /* Match Loop */
+#if defined(__GNUC__) && defined(__x86_64__)
+    /* I've measured random a 5% speed loss on levels 5 & 6 (greedy) when the
+     * code alignment is perturbed. To fix the instability align the loop on 32-bytes.
+     */
+    __asm__(".p2align 5");
+#endif
+    while (ip < ilimit) {
+        size_t matchLength=0;
+        size_t offBase = REPCODE1_TO_OFFBASE;
+        const BYTE* start=ip+1;
+        DEBUGLOG(7, "search baseline (depth 0)");
+
+        /* check repCode */
+        if (isDxS) {
+            const U32 repIndex = (U32)(ip - base) + 1 - offset_1;
+            const BYTE* repMatch = ((dictMode == ZSTD_dictMatchState || dictMode == ZSTD_dedicatedDictSearch)
+                                && repIndex < prefixLowestIndex) ?
+                                   dictBase + (repIndex - dictIndexDelta) :
+                                   base + repIndex;
+            if ((ZSTD_index_overlap_check(prefixLowestIndex, repIndex))
+                && (MEM_read32(repMatch) == MEM_read32(ip+1)) ) {
+                const BYTE* repMatchEnd = repIndex < prefixLowestIndex ? dictEnd : iend;
+                matchLength = ZSTD_count_2segments(ip+1+4, repMatch+4, iend, repMatchEnd, prefixLowest) + 4;
+                if (depth==0) goto _storeSequence;
+            }
+        }
+        if ( dictMode == ZSTD_noDict
+          && ((offset_1 > 0) & (MEM_read32(ip+1-offset_1) == MEM_read32(ip+1)))) {
+            matchLength = ZSTD_count(ip+1+4, ip+1+4-offset_1, iend) + 4;
+            if (depth==0) goto _storeSequence;
+        }
+
+        /* first search (depth 0) */
+        {   size_t offbaseFound = 999999999;
+            size_t const ml2 = ZSTD_searchMax(ms, ip, iend, &offbaseFound, mls, rowLog, searchMethod, dictMode);
+            if (ml2 > matchLength)
+                matchLength = ml2, start = ip, offBase = offbaseFound;
+        }
+
+        if (matchLength < 4) {
+            size_t const step = ((size_t)(ip-anchor) >> kSearchStrength) + 1;   /* jump faster over incompressible sections */;
+            ip += step;
+            /* Enter the lazy skipping mode once we are skipping more than 8 bytes at a time.
+             * In this mode we stop inserting every position into our tables, and only insert
+             * positions that we search, which is one in step positions.
+             * The exact cutoff is flexible, I've just chosen a number that is reasonably high,
+             * so we minimize the compression ratio loss in "normal" scenarios. This mode gets
+             * triggered once we've gone 2KB without finding any matches.
+             */
+            ms->lazySkipping = step > kLazySkippingStep;
+            continue;
+        }
+
+        /* let's try to find a better solution */
+        if (depth>=1)
+        while (ip<ilimit) {
+            DEBUGLOG(7, "search depth 1");
+            ip ++;
+            if ( (dictMode == ZSTD_noDict)
+              && (offBase) && ((offset_1>0) & (MEM_read32(ip) == MEM_read32(ip - offset_1)))) {
+                size_t const mlRep = ZSTD_count(ip+4, ip+4-offset_1, iend) + 4;
+                int const gain2 = (int)(mlRep * 3);
+                int const gain1 = (int)(matchLength*3 - ZSTD_highbit32((U32)offBase) + 1);
+                if ((mlRep >= 4) && (gain2 > gain1))
+                    matchLength = mlRep, offBase = REPCODE1_TO_OFFBASE, start = ip;
+            }
+            if (isDxS) {
+                const U32 repIndex = (U32)(ip - base) - offset_1;
+                const BYTE* repMatch = repIndex < prefixLowestIndex ?
+                               dictBase + (repIndex - dictIndexDelta) :
+                               base + repIndex;
+                if ((ZSTD_index_overlap_check(prefixLowestIndex, repIndex))
+                    && (MEM_read32(repMatch) == MEM_read32(ip)) ) {
+                    const BYTE* repMatchEnd = repIndex < prefixLowestIndex ? dictEnd : iend;
+                    size_t const mlRep = ZSTD_count_2segments(ip+4, repMatch+4, iend, repMatchEnd, prefixLowest) + 4;
+                    int const gain2 = (int)(mlRep * 3);
+                    int const gain1 = (int)(matchLength*3 - ZSTD_highbit32((U32)offBase) + 1);
+                    if ((mlRep >= 4) && (gain2 > gain1))
+                        matchLength = mlRep, offBase = REPCODE1_TO_OFFBASE, start = ip;
+                }
+            }
+            {   size_t ofbCandidate=999999999;
+                size_t const ml2 = ZSTD_searchMax(ms, ip, iend, &ofbCandidate, mls, rowLog, searchMethod, dictMode);
+                int const gain2 = (int)(ml2*4 - ZSTD_highbit32((U32)ofbCandidate));   /* raw approx */
+                int const gain1 = (int)(matchLength*4 - ZSTD_highbit32((U32)offBase) + 4);
+                if ((ml2 >= 4) && (gain2 > gain1)) {
+                    matchLength = ml2, offBase = ofbCandidate, start = ip;
+                    continue;   /* search a better one */
+            }   }
+
+            /* let's find an even better one */
+            if ((depth==2) && (ip<ilimit)) {
+                DEBUGLOG(7, "search depth 2");
+                ip ++;
+                if ( (dictMode == ZSTD_noDict)
+                  && (offBase) && ((offset_1>0) & (MEM_read32(ip) == MEM_read32(ip - offset_1)))) {
+                    size_t const mlRep = ZSTD_count(ip+4, ip+4-offset_1, iend) + 4;
+                    int const gain2 = (int)(mlRep * 4);
+                    int const gain1 = (int)(matchLength*4 - ZSTD_highbit32((U32)offBase) + 1);
+                    if ((mlRep >= 4) && (gain2 > gain1))
+                        matchLength = mlRep, offBase = REPCODE1_TO_OFFBASE, start = ip;
+                }
+                if (isDxS) {
+                    const U32 repIndex = (U32)(ip - base) - offset_1;
+                    const BYTE* repMatch = repIndex < prefixLowestIndex ?
+                                   dictBase + (repIndex - dictIndexDelta) :
+                                   base + repIndex;
+                    if ((ZSTD_index_overlap_check(prefixLowestIndex, repIndex))
+                        && (MEM_read32(repMatch) == MEM_read32(ip)) ) {
+                        const BYTE* repMatchEnd = repIndex < prefixLowestIndex ? dictEnd : iend;
+                        size_t const mlRep = ZSTD_count_2segments(ip+4, repMatch+4, iend, repMatchEnd, prefixLowest) + 4;
+                        int const gain2 = (int)(mlRep * 4);
+                        int const gain1 = (int)(matchLength*4 - ZSTD_highbit32((U32)offBase) + 1);
+                        if ((mlRep >= 4) && (gain2 > gain1))
+                            matchLength = mlRep, offBase = REPCODE1_TO_OFFBASE, start = ip;
+                    }
+                }
+                {   size_t ofbCandidate=999999999;
+                    size_t const ml2 = ZSTD_searchMax(ms, ip, iend, &ofbCandidate, mls, rowLog, searchMethod, dictMode);
+                    int const gain2 = (int)(ml2*4 - ZSTD_highbit32((U32)ofbCandidate));   /* raw approx */
+                    int const gain1 = (int)(matchLength*4 - ZSTD_highbit32((U32)offBase) + 7);
+                    if ((ml2 >= 4) && (gain2 > gain1)) {
+                        matchLength = ml2, offBase = ofbCandidate, start = ip;
+                        continue;
+            }   }   }
+            break;  /* nothing found : store previous solution */
+        }
+
+        /* NOTE:
+         * Pay attention that `start[-value]` can lead to strange undefined behavior
+         * notably if `value` is unsigned, resulting in a large positive `-value`.
+         */
+        /* catch up */
+        if (OFFBASE_IS_OFFSET(offBase)) {
+            if (dictMode == ZSTD_noDict) {
+                while ( ((start > anchor) & (start - OFFBASE_TO_OFFSET(offBase) > prefixLowest))
+                     && (start[-1] == (start-OFFBASE_TO_OFFSET(offBase))[-1]) )  /* only search for offset within prefix */
+                    { start--; matchLength++; }
+            }
+            if (isDxS) {
+                U32 const matchIndex = (U32)((size_t)(start-base) - OFFBASE_TO_OFFSET(offBase));
+                const BYTE* match = (matchIndex < prefixLowestIndex) ? dictBase + matchIndex - dictIndexDelta : base + matchIndex;
+                const BYTE* const mStart = (matchIndex < prefixLowestIndex) ? dictLowest : prefixLowest;
+                while ((start>anchor) && (match>mStart) && (start[-1] == match[-1])) { start--; match--; matchLength++; }  /* catch up */
+            }
+            offset_2 = offset_1; offset_1 = (U32)OFFBASE_TO_OFFSET(offBase);
+        }
+        /* store sequence */
+_storeSequence:
+        {   size_t const litLength = (size_t)(start - anchor);
+            ZSTD_storeSeq(seqStore, litLength, anchor, iend, (U32)offBase, matchLength);
+            anchor = ip = start + matchLength;
+        }
+        if (ms->lazySkipping) {
+            /* We've found a match, disable lazy skipping mode, and refill the hash cache. */
+            if (searchMethod == search_rowHash) {
+                ZSTD_row_fillHashCache(ms, base, rowLog, mls, ms->nextToUpdate, ilimit);
+            }
+            ms->lazySkipping = 0;
+        }
+
+        /* check immediate repcode */
+        if (isDxS) {
+            while (ip <= ilimit) {
+                U32 const current2 = (U32)(ip-base);
+                U32 const repIndex = current2 - offset_2;
+                const BYTE* repMatch = repIndex < prefixLowestIndex ?
+                        dictBase - dictIndexDelta + repIndex :
+                        base + repIndex;
+                if ( (ZSTD_index_overlap_check(prefixLowestIndex, repIndex))
+                   && (MEM_read32(repMatch) == MEM_read32(ip)) ) {
+                    const BYTE* const repEnd2 = repIndex < prefixLowestIndex ? dictEnd : iend;
+                    matchLength = ZSTD_count_2segments(ip+4, repMatch+4, iend, repEnd2, prefixLowest) + 4;
+                    offBase = offset_2; offset_2 = offset_1; offset_1 = (U32)offBase;   /* swap offset_2 <=> offset_1 */
+                    ZSTD_storeSeq(seqStore, 0, anchor, iend, REPCODE1_TO_OFFBASE, matchLength);
+                    ip += matchLength;
+                    anchor = ip;
+                    continue;
+                }
+                break;
+            }
+        }
+
+        if (dictMode == ZSTD_noDict) {
+            while ( ((ip <= ilimit) & (offset_2>0))
+                 && (MEM_read32(ip) == MEM_read32(ip - offset_2)) ) {
+                /* store sequence */
+                matchLength = ZSTD_count(ip+4, ip+4-offset_2, iend) + 4;
+                offBase = offset_2; offset_2 = offset_1; offset_1 = (U32)offBase; /* swap repcodes */
+                ZSTD_storeSeq(seqStore, 0, anchor, iend, REPCODE1_TO_OFFBASE, matchLength);
+                ip += matchLength;
+                anchor = ip;
+                continue;   /* faster when present ... (?) */
+    }   }   }
+
+    /* If offset_1 started invalid (offsetSaved1 != 0) and became valid (offset_1 != 0),
+     * rotate saved offsets. See comment in ZSTD_compressBlock_fast_noDict for more context. */
+    offsetSaved2 = ((offsetSaved1 != 0) && (offset_1 != 0)) ? offsetSaved1 : offsetSaved2;
+
+    /* save reps for next block */
+    rep[0] = offset_1 ? offset_1 : offsetSaved1;
+    rep[1] = offset_2 ? offset_2 : offsetSaved2;
+
+    /* Return the last literals size */
+    return (size_t)(iend - anchor);
+}
+#endif /* build exclusions */
+
+
+#ifndef ZSTD_EXCLUDE_GREEDY_BLOCK_COMPRESSOR
+size_t ZSTD_compressBlock_greedy(
+        ZSTD_MatchState_t* ms, SeqStore_t* seqStore, U32 rep[ZSTD_REP_NUM],
+        void const* src, size_t srcSize)
+{
+    return ZSTD_compressBlock_lazy_generic(ms, seqStore, rep, src, srcSize, search_hashChain, 0, ZSTD_noDict);
+}
+
+size_t ZSTD_compressBlock_greedy_dictMatchState(
+        ZSTD_MatchState_t* ms, SeqStore_t* seqStore, U32 rep[ZSTD_REP_NUM],
+        void const* src, size_t srcSize)
+{
+    return ZSTD_compressBlock_lazy_generic(ms, seqStore, rep, src, srcSize, search_hashChain, 0, ZSTD_dictMatchState);
+}
+
+size_t ZSTD_compressBlock_greedy_dedicatedDictSearch(
+        ZSTD_MatchState_t* ms, SeqStore_t* seqStore, U32 rep[ZSTD_REP_NUM],
+        void const* src, size_t srcSize)
+{
+    return ZSTD_compressBlock_lazy_generic(ms, seqStore, rep, src, srcSize, search_hashChain, 0, ZSTD_dedicatedDictSearch);
+}
+
+size_t ZSTD_compressBlock_greedy_row(
+        ZSTD_MatchState_t* ms, SeqStore_t* seqStore, U32 rep[ZSTD_REP_NUM],
+        void const* src, size_t srcSize)
+{
+    return ZSTD_compressBlock_lazy_generic(ms, seqStore, rep, src, srcSize, search_rowHash, 0, ZSTD_noDict);
+}
+
+size_t ZSTD_compressBlock_greedy_dictMatchState_row(
+        ZSTD_MatchState_t* ms, SeqStore_t* seqStore, U32 rep[ZSTD_REP_NUM],
+        void const* src, size_t srcSize)
+{
+    return ZSTD_compressBlock_lazy_generic(ms, seqStore, rep, src, srcSize, search_rowHash, 0, ZSTD_dictMatchState);
+}
+
+size_t ZSTD_compressBlock_greedy_dedicatedDictSearch_row(
+        ZSTD_MatchState_t* ms, SeqStore_t* seqStore, U32 rep[ZSTD_REP_NUM],
+        void const* src, size_t srcSize)
+{
+    return ZSTD_compressBlock_lazy_generic(ms, seqStore, rep, src, srcSize, search_rowHash, 0, ZSTD_dedicatedDictSearch);
+}
+#endif
+
+#ifndef ZSTD_EXCLUDE_LAZY_BLOCK_COMPRESSOR
+size_t ZSTD_compressBlock_lazy(
+        ZSTD_MatchState_t* ms, SeqStore_t* seqStore, U32 rep[ZSTD_REP_NUM],
+        void const* src, size_t srcSize)
+{
+    return ZSTD_compressBlock_lazy_generic(ms, seqStore, rep, src, srcSize, search_hashChain, 1, ZSTD_noDict);
+}
+
+size_t ZSTD_compressBlock_lazy_dictMatchState(
+        ZSTD_MatchState_t* ms, SeqStore_t* seqStore, U32 rep[ZSTD_REP_NUM],
+        void const* src, size_t srcSize)
+{
+    return ZSTD_compressBlock_lazy_generic(ms, seqStore, rep, src, srcSize, search_hashChain, 1, ZSTD_dictMatchState);
+}
+
+size_t ZSTD_compressBlock_lazy_dedicatedDictSearch(
+        ZSTD_MatchState_t* ms, SeqStore_t* seqStore, U32 rep[ZSTD_REP_NUM],
+        void const* src, size_t srcSize)
+{
+    return ZSTD_compressBlock_lazy_generic(ms, seqStore, rep, src, srcSize, search_hashChain, 1, ZSTD_dedicatedDictSearch);
+}
+
+size_t ZSTD_compressBlock_lazy_row(
+        ZSTD_MatchState_t* ms, SeqStore_t* seqStore, U32 rep[ZSTD_REP_NUM],
+        void const* src, size_t srcSize)
+{
+    return ZSTD_compressBlock_lazy_generic(ms, seqStore, rep, src, srcSize, search_rowHash, 1, ZSTD_noDict);
+}
+
+size_t ZSTD_compressBlock_lazy_dictMatchState_row(
+        ZSTD_MatchState_t* ms, SeqStore_t* seqStore, U32 rep[ZSTD_REP_NUM],
+        void const* src, size_t srcSize)
+{
+    return ZSTD_compressBlock_lazy_generic(ms, seqStore, rep, src, srcSize, search_rowHash, 1, ZSTD_dictMatchState);
+}
+
+size_t ZSTD_compressBlock_lazy_dedicatedDictSearch_row(
+        ZSTD_MatchState_t* ms, SeqStore_t* seqStore, U32 rep[ZSTD_REP_NUM],
+        void const* src, size_t srcSize)
+{
+    return ZSTD_compressBlock_lazy_generic(ms, seqStore, rep, src, srcSize, search_rowHash, 1, ZSTD_dedicatedDictSearch);
+}
+#endif
+
+#ifndef ZSTD_EXCLUDE_LAZY2_BLOCK_COMPRESSOR
+size_t ZSTD_compressBlock_lazy2(
+        ZSTD_MatchState_t* ms, SeqStore_t* seqStore, U32 rep[ZSTD_REP_NUM],
+        void const* src, size_t srcSize)
+{
+    return ZSTD_compressBlock_lazy_generic(ms, seqStore, rep, src, srcSize, search_hashChain, 2, ZSTD_noDict);
+}
+
+size_t ZSTD_compressBlock_lazy2_dictMatchState(
+        ZSTD_MatchState_t* ms, SeqStore_t* seqStore, U32 rep[ZSTD_REP_NUM],
+        void const* src, size_t srcSize)
+{
+    return ZSTD_compressBlock_lazy_generic(ms, seqStore, rep, src, srcSize, search_hashChain, 2, ZSTD_dictMatchState);
+}
+
+size_t ZSTD_compressBlock_lazy2_dedicatedDictSearch(
+        ZSTD_MatchState_t* ms, SeqStore_t* seqStore, U32 rep[ZSTD_REP_NUM],
+        void const* src, size_t srcSize)
+{
+    return ZSTD_compressBlock_lazy_generic(ms, seqStore, rep, src, srcSize, search_hashChain, 2, ZSTD_dedicatedDictSearch);
+}
+
+size_t ZSTD_compressBlock_lazy2_row(
+        ZSTD_MatchState_t* ms, SeqStore_t* seqStore, U32 rep[ZSTD_REP_NUM],
+        void const* src, size_t srcSize)
+{
+    return ZSTD_compressBlock_lazy_generic(ms, seqStore, rep, src, srcSize, search_rowHash, 2, ZSTD_noDict);
+}
+
+size_t ZSTD_compressBlock_lazy2_dictMatchState_row(
+        ZSTD_MatchState_t* ms, SeqStore_t* seqStore, U32 rep[ZSTD_REP_NUM],
+        void const* src, size_t srcSize)
+{
+    return ZSTD_compressBlock_lazy_generic(ms, seqStore, rep, src, srcSize, search_rowHash, 2, ZSTD_dictMatchState);
+}
+
+size_t ZSTD_compressBlock_lazy2_dedicatedDictSearch_row(
+        ZSTD_MatchState_t* ms, SeqStore_t* seqStore, U32 rep[ZSTD_REP_NUM],
+        void const* src, size_t srcSize)
+{
+    return ZSTD_compressBlock_lazy_generic(ms, seqStore, rep, src, srcSize, search_rowHash, 2, ZSTD_dedicatedDictSearch);
+}
+#endif
+
+#ifndef ZSTD_EXCLUDE_BTLAZY2_BLOCK_COMPRESSOR
+size_t ZSTD_compressBlock_btlazy2(
+        ZSTD_MatchState_t* ms, SeqStore_t* seqStore, U32 rep[ZSTD_REP_NUM],
+        void const* src, size_t srcSize)
+{
+    return ZSTD_compressBlock_lazy_generic(ms, seqStore, rep, src, srcSize, search_binaryTree, 2, ZSTD_noDict);
+}
+
+size_t ZSTD_compressBlock_btlazy2_dictMatchState(
+        ZSTD_MatchState_t* ms, SeqStore_t* seqStore, U32 rep[ZSTD_REP_NUM],
+        void const* src, size_t srcSize)
+{
+    return ZSTD_compressBlock_lazy_generic(ms, seqStore, rep, src, srcSize, search_binaryTree, 2, ZSTD_dictMatchState);
+}
+#endif
+
+#if !defined(ZSTD_EXCLUDE_GREEDY_BLOCK_COMPRESSOR) \
+ || !defined(ZSTD_EXCLUDE_LAZY_BLOCK_COMPRESSOR) \
+ || !defined(ZSTD_EXCLUDE_LAZY2_BLOCK_COMPRESSOR) \
+ || !defined(ZSTD_EXCLUDE_BTLAZY2_BLOCK_COMPRESSOR)
+FORCE_INLINE_TEMPLATE
+ZSTD_ALLOW_POINTER_OVERFLOW_ATTR
+size_t ZSTD_compressBlock_lazy_extDict_generic(
+                        ZSTD_MatchState_t* ms, SeqStore_t* seqStore,
+                        U32 rep[ZSTD_REP_NUM],
+                        const void* src, size_t srcSize,
+                        const searchMethod_e searchMethod, const U32 depth)
+{
+    const BYTE* const istart = (const BYTE*)src;
+    const BYTE* ip = istart;
+    const BYTE* anchor = istart;
+    const BYTE* const iend = istart + srcSize;
+    const BYTE* const ilimit = searchMethod == search_rowHash ? iend - 8 - ZSTD_ROW_HASH_CACHE_SIZE : iend - 8;
+    const BYTE* const base = ms->window.base;
+    const U32 dictLimit = ms->window.dictLimit;
+    const BYTE* const prefixStart = base + dictLimit;
+    const BYTE* const dictBase = ms->window.dictBase;
+    const BYTE* const dictEnd  = dictBase + dictLimit;
+    const BYTE* const dictStart  = dictBase + ms->window.lowLimit;
+    const U32 windowLog = ms->cParams.windowLog;
+    const U32 mls = BOUNDED(4, ms->cParams.minMatch, 6);
+    const U32 rowLog = BOUNDED(4, ms->cParams.searchLog, 6);
+
+    U32 offset_1 = rep[0], offset_2 = rep[1];
+
+    DEBUGLOG(5, "ZSTD_compressBlock_lazy_extDict_generic (searchFunc=%u)", (U32)searchMethod);
+
+    /* Reset the lazy skipping state */
+    ms->lazySkipping = 0;
+
+    /* init */
+    ip += (ip == prefixStart);
+    if (searchMethod == search_rowHash) {
+        ZSTD_row_fillHashCache(ms, base, rowLog, mls, ms->nextToUpdate, ilimit);
+    }
+
+    /* Match Loop */
+#if defined(__GNUC__) && defined(__x86_64__)
+    /* I've measured random a 5% speed loss on levels 5 & 6 (greedy) when the
+     * code alignment is perturbed. To fix the instability align the loop on 32-bytes.
+     */
+    __asm__(".p2align 5");
+#endif
+    while (ip < ilimit) {
+        size_t matchLength=0;
+        size_t offBase = REPCODE1_TO_OFFBASE;
+        const BYTE* start=ip+1;
+        U32 curr = (U32)(ip-base);
+
+        /* check repCode */
+        {   const U32 windowLow = ZSTD_getLowestMatchIndex(ms, curr+1, windowLog);
+            const U32 repIndex = (U32)(curr+1 - offset_1);
+            const BYTE* const repBase = repIndex < dictLimit ? dictBase : base;
+            const BYTE* const repMatch = repBase + repIndex;
+            if ( (ZSTD_index_overlap_check(dictLimit, repIndex))
+               & (offset_1 <= curr+1 - windowLow) ) /* note: we are searching at curr+1 */
+            if (MEM_read32(ip+1) == MEM_read32(repMatch)) {
+                /* repcode detected we should take it */
+                const BYTE* const repEnd = repIndex < dictLimit ? dictEnd : iend;
+                matchLength = ZSTD_count_2segments(ip+1+4, repMatch+4, iend, repEnd, prefixStart) + 4;
+                if (depth==0) goto _storeSequence;
+        }   }
+
+        /* first search (depth 0) */
+        {   size_t ofbCandidate = 999999999;
+            size_t const ml2 = ZSTD_searchMax(ms, ip, iend, &ofbCandidate, mls, rowLog, searchMethod, ZSTD_extDict);
+            if (ml2 > matchLength)
+                matchLength = ml2, start = ip, offBase = ofbCandidate;
+        }
+
+        if (matchLength < 4) {
+            size_t const step = ((size_t)(ip-anchor) >> kSearchStrength);
+            ip += step + 1;   /* jump faster over incompressible sections */
+            /* Enter the lazy skipping mode once we are skipping more than 8 bytes at a time.
+             * In this mode we stop inserting every position into our tables, and only insert
+             * positions that we search, which is one in step positions.
+             * The exact cutoff is flexible, I've just chosen a number that is reasonably high,
+             * so we minimize the compression ratio loss in "normal" scenarios. This mode gets
+             * triggered once we've gone 2KB without finding any matches.
+             */
+            ms->lazySkipping = step > kLazySkippingStep;
+            continue;
+        }
+
+        /* let's try to find a better solution */
+        if (depth>=1)
+        while (ip<ilimit) {
+            ip ++;
+            curr++;
+            /* check repCode */
+            if (offBase) {
+                const U32 windowLow = ZSTD_getLowestMatchIndex(ms, curr, windowLog);
+                const U32 repIndex = (U32)(curr - offset_1);
+                const BYTE* const repBase = repIndex < dictLimit ? dictBase : base;
+                const BYTE* const repMatch = repBase + repIndex;
+                if ( (ZSTD_index_overlap_check(dictLimit, repIndex))
+                   & (offset_1 <= curr - windowLow) ) /* equivalent to `curr > repIndex >= windowLow` */
+                if (MEM_read32(ip) == MEM_read32(repMatch)) {
+                    /* repcode detected */
+                    const BYTE* const repEnd = repIndex < dictLimit ? dictEnd : iend;
+                    size_t const repLength = ZSTD_count_2segments(ip+4, repMatch+4, iend, repEnd, prefixStart) + 4;
+                    int const gain2 = (int)(repLength * 3);
+                    int const gain1 = (int)(matchLength*3 - ZSTD_highbit32((U32)offBase) + 1);
+                    if ((repLength >= 4) && (gain2 > gain1))
+                        matchLength = repLength, offBase = REPCODE1_TO_OFFBASE, start = ip;
+            }   }
+
+            /* search match, depth 1 */
+            {   size_t ofbCandidate = 999999999;
+                size_t const ml2 = ZSTD_searchMax(ms, ip, iend, &ofbCandidate, mls, rowLog, searchMethod, ZSTD_extDict);
+                int const gain2 = (int)(ml2*4 - ZSTD_highbit32((U32)ofbCandidate));   /* raw approx */
+                int const gain1 = (int)(matchLength*4 - ZSTD_highbit32((U32)offBase) + 4);
+                if ((ml2 >= 4) && (gain2 > gain1)) {
+                    matchLength = ml2, offBase = ofbCandidate, start = ip;
+                    continue;   /* search a better one */
+            }   }
+
+            /* let's find an even better one */
+            if ((depth==2) && (ip<ilimit)) {
+                ip ++;
+                curr++;
+                /* check repCode */
+                if (offBase) {
+                    const U32 windowLow = ZSTD_getLowestMatchIndex(ms, curr, windowLog);
+                    const U32 repIndex = (U32)(curr - offset_1);
+                    const BYTE* const repBase = repIndex < dictLimit ? dictBase : base;
+                    const BYTE* const repMatch = repBase + repIndex;
+                    if ( (ZSTD_index_overlap_check(dictLimit, repIndex))
+                       & (offset_1 <= curr - windowLow) ) /* equivalent to `curr > repIndex >= windowLow` */
+                    if (MEM_read32(ip) == MEM_read32(repMatch)) {
+                        /* repcode detected */
+                        const BYTE* const repEnd = repIndex < dictLimit ? dictEnd : iend;
+                        size_t const repLength = ZSTD_count_2segments(ip+4, repMatch+4, iend, repEnd, prefixStart) + 4;
+                        int const gain2 = (int)(repLength * 4);
+                        int const gain1 = (int)(matchLength*4 - ZSTD_highbit32((U32)offBase) + 1);
+                        if ((repLength >= 4) && (gain2 > gain1))
+                            matchLength = repLength, offBase = REPCODE1_TO_OFFBASE, start = ip;
+                }   }
+
+                /* search match, depth 2 */
+                {   size_t ofbCandidate = 999999999;
+                    size_t const ml2 = ZSTD_searchMax(ms, ip, iend, &ofbCandidate, mls, rowLog, searchMethod, ZSTD_extDict);
+                    int const gain2 = (int)(ml2*4 - ZSTD_highbit32((U32)ofbCandidate));   /* raw approx */
+                    int const gain1 = (int)(matchLength*4 - ZSTD_highbit32((U32)offBase) + 7);
+                    if ((ml2 >= 4) && (gain2 > gain1)) {
+                        matchLength = ml2, offBase = ofbCandidate, start = ip;
+                        continue;
+            }   }   }
+            break;  /* nothing found : store previous solution */
+        }
+
+        /* catch up */
+        if (OFFBASE_IS_OFFSET(offBase)) {
+            U32 const matchIndex = (U32)((size_t)(start-base) - OFFBASE_TO_OFFSET(offBase));
+            const BYTE* match = (matchIndex < dictLimit) ? dictBase + matchIndex : base + matchIndex;
+            const BYTE* const mStart = (matchIndex < dictLimit) ? dictStart : prefixStart;
+            while ((start>anchor) && (match>mStart) && (start[-1] == match[-1])) { start--; match--; matchLength++; }  /* catch up */
+            offset_2 = offset_1; offset_1 = (U32)OFFBASE_TO_OFFSET(offBase);
+        }
+
+        /* store sequence */
+_storeSequence:
+        {   size_t const litLength = (size_t)(start - anchor);
+            ZSTD_storeSeq(seqStore, litLength, anchor, iend, (U32)offBase, matchLength);
+            anchor = ip = start + matchLength;
+        }
+        if (ms->lazySkipping) {
+            /* We've found a match, disable lazy skipping mode, and refill the hash cache. */
+            if (searchMethod == search_rowHash) {
+                ZSTD_row_fillHashCache(ms, base, rowLog, mls, ms->nextToUpdate, ilimit);
+            }
+            ms->lazySkipping = 0;
+        }
+
+        /* check immediate repcode */
+        while (ip <= ilimit) {
+            const U32 repCurrent = (U32)(ip-base);
+            const U32 windowLow = ZSTD_getLowestMatchIndex(ms, repCurrent, windowLog);
+            const U32 repIndex = repCurrent - offset_2;
+            const BYTE* const repBase = repIndex < dictLimit ? dictBase : base;
+            const BYTE* const repMatch = repBase + repIndex;
+            if ( (ZSTD_index_overlap_check(dictLimit, repIndex))
+               & (offset_2 <= repCurrent - windowLow) ) /* equivalent to `curr > repIndex >= windowLow` */
+            if (MEM_read32(ip) == MEM_read32(repMatch)) {
+                /* repcode detected we should take it */
+                const BYTE* const repEnd = repIndex < dictLimit ? dictEnd : iend;
+                matchLength = ZSTD_count_2segments(ip+4, repMatch+4, iend, repEnd, prefixStart) + 4;
+                offBase = offset_2; offset_2 = offset_1; offset_1 = (U32)offBase;   /* swap offset history */
+                ZSTD_storeSeq(seqStore, 0, anchor, iend, REPCODE1_TO_OFFBASE, matchLength);
+                ip += matchLength;
+                anchor = ip;
+                continue;   /* faster when present ... (?) */
+            }
+            break;
+    }   }
+
+    /* Save reps for next block */
+    rep[0] = offset_1;
+    rep[1] = offset_2;
+
+    /* Return the last literals size */
+    return (size_t)(iend - anchor);
+}
+#endif /* build exclusions */
+
+#ifndef ZSTD_EXCLUDE_GREEDY_BLOCK_COMPRESSOR
+size_t ZSTD_compressBlock_greedy_extDict(
+        ZSTD_MatchState_t* ms, SeqStore_t* seqStore, U32 rep[ZSTD_REP_NUM],
+        void const* src, size_t srcSize)
+{
+    return ZSTD_compressBlock_lazy_extDict_generic(ms, seqStore, rep, src, srcSize, search_hashChain, 0);
+}
+
+size_t ZSTD_compressBlock_greedy_extDict_row(
+        ZSTD_MatchState_t* ms, SeqStore_t* seqStore, U32 rep[ZSTD_REP_NUM],
+        void const* src, size_t srcSize)
+{
+    return ZSTD_compressBlock_lazy_extDict_generic(ms, seqStore, rep, src, srcSize, search_rowHash, 0);
+}
+#endif
+
+#ifndef ZSTD_EXCLUDE_LAZY_BLOCK_COMPRESSOR
+size_t ZSTD_compressBlock_lazy_extDict(
+        ZSTD_MatchState_t* ms, SeqStore_t* seqStore, U32 rep[ZSTD_REP_NUM],
+        void const* src, size_t srcSize)
+
+{
+    return ZSTD_compressBlock_lazy_extDict_generic(ms, seqStore, rep, src, srcSize, search_hashChain, 1);
+}
+
+size_t ZSTD_compressBlock_lazy_extDict_row(
+        ZSTD_MatchState_t* ms, SeqStore_t* seqStore, U32 rep[ZSTD_REP_NUM],
+        void const* src, size_t srcSize)
+
+{
+    return ZSTD_compressBlock_lazy_extDict_generic(ms, seqStore, rep, src, srcSize, search_rowHash, 1);
+}
+#endif
+
+#ifndef ZSTD_EXCLUDE_LAZY2_BLOCK_COMPRESSOR
+size_t ZSTD_compressBlock_lazy2_extDict(
+        ZSTD_MatchState_t* ms, SeqStore_t* seqStore, U32 rep[ZSTD_REP_NUM],
+        void const* src, size_t srcSize)
+
+{
+    return ZSTD_compressBlock_lazy_extDict_generic(ms, seqStore, rep, src, srcSize, search_hashChain, 2);
+}
+
+size_t ZSTD_compressBlock_lazy2_extDict_row(
+        ZSTD_MatchState_t* ms, SeqStore_t* seqStore, U32 rep[ZSTD_REP_NUM],
+        void const* src, size_t srcSize)
+{
+    return ZSTD_compressBlock_lazy_extDict_generic(ms, seqStore, rep, src, srcSize, search_rowHash, 2);
+}
+#endif
+
+#ifndef ZSTD_EXCLUDE_BTLAZY2_BLOCK_COMPRESSOR
+size_t ZSTD_compressBlock_btlazy2_extDict(
+        ZSTD_MatchState_t* ms, SeqStore_t* seqStore, U32 rep[ZSTD_REP_NUM],
+        void const* src, size_t srcSize)
+
+{
+    return ZSTD_compressBlock_lazy_extDict_generic(ms, seqStore, rep, src, srcSize, search_binaryTree, 2);
+}
+#endif
diff --git a/src/commonlib/bsd/zstd/compress/zstd_lazy.h b/src/commonlib/bsd/zstd/compress/zstd_lazy.h
new file mode 100644
index 0000000000..f959a855f6
--- /dev/null
+++ b/src/commonlib/bsd/zstd/compress/zstd_lazy.h
@@ -0,0 +1,195 @@
+/* SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0-only */
+
+/*
+ * Copyright (c) Meta Platforms, Inc. and affiliates.
+ * All rights reserved.
+ *
+ * This source code is licensed under both the BSD-style license (found in the
+ * LICENSE file in the root directory of this source tree) and the GPLv2 (found
+ * in the COPYING file in the root directory of this source tree).
+ * You may select, at your option, one of the above-listed licenses.
+ */
+
+#ifndef ZSTD_LAZY_H
+#define ZSTD_LAZY_H
+
+#include "zstd_compress_internal.h"
+
+/**
+ * Dedicated Dictionary Search Structure bucket log. In the
+ * ZSTD_dedicatedDictSearch mode, the hashTable has
+ * 2 ** ZSTD_LAZY_DDSS_BUCKET_LOG entries in each bucket, rather than just
+ * one.
+ */
+#define ZSTD_LAZY_DDSS_BUCKET_LOG 2
+
+#define ZSTD_ROW_HASH_TAG_BITS 8        /* nb bits to use for the tag */
+
+#if !defined(ZSTD_EXCLUDE_GREEDY_BLOCK_COMPRESSOR) \
+ || !defined(ZSTD_EXCLUDE_LAZY_BLOCK_COMPRESSOR) \
+ || !defined(ZSTD_EXCLUDE_LAZY2_BLOCK_COMPRESSOR) \
+ || !defined(ZSTD_EXCLUDE_BTLAZY2_BLOCK_COMPRESSOR)
+U32 ZSTD_insertAndFindFirstIndex(ZSTD_MatchState_t* ms, const BYTE* ip);
+void ZSTD_row_update(ZSTD_MatchState_t* const ms, const BYTE* ip);
+
+void ZSTD_dedicatedDictSearch_lazy_loadDictionary(ZSTD_MatchState_t* ms, const BYTE* const ip);
+
+void ZSTD_preserveUnsortedMark (U32* const table, U32 const size, U32 const reducerValue);  /*! used in ZSTD_reduceIndex(). preemptively increase value of ZSTD_DUBT_UNSORTED_MARK */
+#endif
+
+#ifndef ZSTD_EXCLUDE_GREEDY_BLOCK_COMPRESSOR
+size_t ZSTD_compressBlock_greedy(
+        ZSTD_MatchState_t* ms, SeqStore_t* seqStore, U32 rep[ZSTD_REP_NUM],
+        void const* src, size_t srcSize);
+size_t ZSTD_compressBlock_greedy_row(
+        ZSTD_MatchState_t* ms, SeqStore_t* seqStore, U32 rep[ZSTD_REP_NUM],
+        void const* src, size_t srcSize);
+size_t ZSTD_compressBlock_greedy_dictMatchState(
+        ZSTD_MatchState_t* ms, SeqStore_t* seqStore, U32 rep[ZSTD_REP_NUM],
+        void const* src, size_t srcSize);
+size_t ZSTD_compressBlock_greedy_dictMatchState_row(
+        ZSTD_MatchState_t* ms, SeqStore_t* seqStore, U32 rep[ZSTD_REP_NUM],
+        void const* src, size_t srcSize);
+size_t ZSTD_compressBlock_greedy_dedicatedDictSearch(
+        ZSTD_MatchState_t* ms, SeqStore_t* seqStore, U32 rep[ZSTD_REP_NUM],
+        void const* src, size_t srcSize);
+size_t ZSTD_compressBlock_greedy_dedicatedDictSearch_row(
+        ZSTD_MatchState_t* ms, SeqStore_t* seqStore, U32 rep[ZSTD_REP_NUM],
+        void const* src, size_t srcSize);
+size_t ZSTD_compressBlock_greedy_extDict(
+        ZSTD_MatchState_t* ms, SeqStore_t* seqStore, U32 rep[ZSTD_REP_NUM],
+        void const* src, size_t srcSize);
+size_t ZSTD_compressBlock_greedy_extDict_row(
+        ZSTD_MatchState_t* ms, SeqStore_t* seqStore, U32 rep[ZSTD_REP_NUM],
+        void const* src, size_t srcSize);
+
+#define ZSTD_COMPRESSBLOCK_GREEDY ZSTD_compressBlock_greedy
+#define ZSTD_COMPRESSBLOCK_GREEDY_ROW ZSTD_compressBlock_greedy_row
+#define ZSTD_COMPRESSBLOCK_GREEDY_DICTMATCHSTATE ZSTD_compressBlock_greedy_dictMatchState
+#define ZSTD_COMPRESSBLOCK_GREEDY_DICTMATCHSTATE_ROW ZSTD_compressBlock_greedy_dictMatchState_row
+#define ZSTD_COMPRESSBLOCK_GREEDY_DEDICATEDDICTSEARCH ZSTD_compressBlock_greedy_dedicatedDictSearch
+#define ZSTD_COMPRESSBLOCK_GREEDY_DEDICATEDDICTSEARCH_ROW ZSTD_compressBlock_greedy_dedicatedDictSearch_row
+#define ZSTD_COMPRESSBLOCK_GREEDY_EXTDICT ZSTD_compressBlock_greedy_extDict
+#define ZSTD_COMPRESSBLOCK_GREEDY_EXTDICT_ROW ZSTD_compressBlock_greedy_extDict_row
+#else
+#define ZSTD_COMPRESSBLOCK_GREEDY NULL
+#define ZSTD_COMPRESSBLOCK_GREEDY_ROW NULL
+#define ZSTD_COMPRESSBLOCK_GREEDY_DICTMATCHSTATE NULL
+#define ZSTD_COMPRESSBLOCK_GREEDY_DICTMATCHSTATE_ROW NULL
+#define ZSTD_COMPRESSBLOCK_GREEDY_DEDICATEDDICTSEARCH NULL
+#define ZSTD_COMPRESSBLOCK_GREEDY_DEDICATEDDICTSEARCH_ROW NULL
+#define ZSTD_COMPRESSBLOCK_GREEDY_EXTDICT NULL
+#define ZSTD_COMPRESSBLOCK_GREEDY_EXTDICT_ROW NULL
+#endif
+
+#ifndef ZSTD_EXCLUDE_LAZY_BLOCK_COMPRESSOR
+size_t ZSTD_compressBlock_lazy(
+        ZSTD_MatchState_t* ms, SeqStore_t* seqStore, U32 rep[ZSTD_REP_NUM],
+        void const* src, size_t srcSize);
+size_t ZSTD_compressBlock_lazy_row(
+        ZSTD_MatchState_t* ms, SeqStore_t* seqStore, U32 rep[ZSTD_REP_NUM],
+        void const* src, size_t srcSize);
+size_t ZSTD_compressBlock_lazy_dictMatchState(
+        ZSTD_MatchState_t* ms, SeqStore_t* seqStore, U32 rep[ZSTD_REP_NUM],
+        void const* src, size_t srcSize);
+size_t ZSTD_compressBlock_lazy_dictMatchState_row(
+        ZSTD_MatchState_t* ms, SeqStore_t* seqStore, U32 rep[ZSTD_REP_NUM],
+        void const* src, size_t srcSize);
+size_t ZSTD_compressBlock_lazy_dedicatedDictSearch(
+        ZSTD_MatchState_t* ms, SeqStore_t* seqStore, U32 rep[ZSTD_REP_NUM],
+        void const* src, size_t srcSize);
+size_t ZSTD_compressBlock_lazy_dedicatedDictSearch_row(
+        ZSTD_MatchState_t* ms, SeqStore_t* seqStore, U32 rep[ZSTD_REP_NUM],
+        void const* src, size_t srcSize);
+size_t ZSTD_compressBlock_lazy_extDict(
+        ZSTD_MatchState_t* ms, SeqStore_t* seqStore, U32 rep[ZSTD_REP_NUM],
+        void const* src, size_t srcSize);
+size_t ZSTD_compressBlock_lazy_extDict_row(
+        ZSTD_MatchState_t* ms, SeqStore_t* seqStore, U32 rep[ZSTD_REP_NUM],
+        void const* src, size_t srcSize);
+
+#define ZSTD_COMPRESSBLOCK_LAZY ZSTD_compressBlock_lazy
+#define ZSTD_COMPRESSBLOCK_LAZY_ROW ZSTD_compressBlock_lazy_row
+#define ZSTD_COMPRESSBLOCK_LAZY_DICTMATCHSTATE ZSTD_compressBlock_lazy_dictMatchState
+#define ZSTD_COMPRESSBLOCK_LAZY_DICTMATCHSTATE_ROW ZSTD_compressBlock_lazy_dictMatchState_row
+#define ZSTD_COMPRESSBLOCK_LAZY_DEDICATEDDICTSEARCH ZSTD_compressBlock_lazy_dedicatedDictSearch
+#define ZSTD_COMPRESSBLOCK_LAZY_DEDICATEDDICTSEARCH_ROW ZSTD_compressBlock_lazy_dedicatedDictSearch_row
+#define ZSTD_COMPRESSBLOCK_LAZY_EXTDICT ZSTD_compressBlock_lazy_extDict
+#define ZSTD_COMPRESSBLOCK_LAZY_EXTDICT_ROW ZSTD_compressBlock_lazy_extDict_row
+#else
+#define ZSTD_COMPRESSBLOCK_LAZY NULL
+#define ZSTD_COMPRESSBLOCK_LAZY_ROW NULL
+#define ZSTD_COMPRESSBLOCK_LAZY_DICTMATCHSTATE NULL
+#define ZSTD_COMPRESSBLOCK_LAZY_DICTMATCHSTATE_ROW NULL
+#define ZSTD_COMPRESSBLOCK_LAZY_DEDICATEDDICTSEARCH NULL
+#define ZSTD_COMPRESSBLOCK_LAZY_DEDICATEDDICTSEARCH_ROW NULL
+#define ZSTD_COMPRESSBLOCK_LAZY_EXTDICT NULL
+#define ZSTD_COMPRESSBLOCK_LAZY_EXTDICT_ROW NULL
+#endif
+
+#ifndef ZSTD_EXCLUDE_LAZY2_BLOCK_COMPRESSOR
+size_t ZSTD_compressBlock_lazy2(
+        ZSTD_MatchState_t* ms, SeqStore_t* seqStore, U32 rep[ZSTD_REP_NUM],
+        void const* src, size_t srcSize);
+size_t ZSTD_compressBlock_lazy2_row(
+        ZSTD_MatchState_t* ms, SeqStore_t* seqStore, U32 rep[ZSTD_REP_NUM],
+        void const* src, size_t srcSize);
+size_t ZSTD_compressBlock_lazy2_dictMatchState(
+        ZSTD_MatchState_t* ms, SeqStore_t* seqStore, U32 rep[ZSTD_REP_NUM],
+        void const* src, size_t srcSize);
+size_t ZSTD_compressBlock_lazy2_dictMatchState_row(
+        ZSTD_MatchState_t* ms, SeqStore_t* seqStore, U32 rep[ZSTD_REP_NUM],
+        void const* src, size_t srcSize);
+size_t ZSTD_compressBlock_lazy2_dedicatedDictSearch(
+        ZSTD_MatchState_t* ms, SeqStore_t* seqStore, U32 rep[ZSTD_REP_NUM],
+        void const* src, size_t srcSize);
+size_t ZSTD_compressBlock_lazy2_dedicatedDictSearch_row(
+        ZSTD_MatchState_t* ms, SeqStore_t* seqStore, U32 rep[ZSTD_REP_NUM],
+        void const* src, size_t srcSize);
+size_t ZSTD_compressBlock_lazy2_extDict(
+        ZSTD_MatchState_t* ms, SeqStore_t* seqStore, U32 rep[ZSTD_REP_NUM],
+        void const* src, size_t srcSize);
+size_t ZSTD_compressBlock_lazy2_extDict_row(
+        ZSTD_MatchState_t* ms, SeqStore_t* seqStore, U32 rep[ZSTD_REP_NUM],
+        void const* src, size_t srcSize);
+
+#define ZSTD_COMPRESSBLOCK_LAZY2 ZSTD_compressBlock_lazy2
+#define ZSTD_COMPRESSBLOCK_LAZY2_ROW ZSTD_compressBlock_lazy2_row
+#define ZSTD_COMPRESSBLOCK_LAZY2_DICTMATCHSTATE ZSTD_compressBlock_lazy2_dictMatchState
+#define ZSTD_COMPRESSBLOCK_LAZY2_DICTMATCHSTATE_ROW ZSTD_compressBlock_lazy2_dictMatchState_row
+#define ZSTD_COMPRESSBLOCK_LAZY2_DEDICATEDDICTSEARCH ZSTD_compressBlock_lazy2_dedicatedDictSearch
+#define ZSTD_COMPRESSBLOCK_LAZY2_DEDICATEDDICTSEARCH_ROW ZSTD_compressBlock_lazy2_dedicatedDictSearch_row
+#define ZSTD_COMPRESSBLOCK_LAZY2_EXTDICT ZSTD_compressBlock_lazy2_extDict
+#define ZSTD_COMPRESSBLOCK_LAZY2_EXTDICT_ROW ZSTD_compressBlock_lazy2_extDict_row
+#else
+#define ZSTD_COMPRESSBLOCK_LAZY2 NULL
+#define ZSTD_COMPRESSBLOCK_LAZY2_ROW NULL
+#define ZSTD_COMPRESSBLOCK_LAZY2_DICTMATCHSTATE NULL
+#define ZSTD_COMPRESSBLOCK_LAZY2_DICTMATCHSTATE_ROW NULL
+#define ZSTD_COMPRESSBLOCK_LAZY2_DEDICATEDDICTSEARCH NULL
+#define ZSTD_COMPRESSBLOCK_LAZY2_DEDICATEDDICTSEARCH_ROW NULL
+#define ZSTD_COMPRESSBLOCK_LAZY2_EXTDICT NULL
+#define ZSTD_COMPRESSBLOCK_LAZY2_EXTDICT_ROW NULL
+#endif
+
+#ifndef ZSTD_EXCLUDE_BTLAZY2_BLOCK_COMPRESSOR
+size_t ZSTD_compressBlock_btlazy2(
+        ZSTD_MatchState_t* ms, SeqStore_t* seqStore, U32 rep[ZSTD_REP_NUM],
+        void const* src, size_t srcSize);
+size_t ZSTD_compressBlock_btlazy2_dictMatchState(
+        ZSTD_MatchState_t* ms, SeqStore_t* seqStore, U32 rep[ZSTD_REP_NUM],
+        void const* src, size_t srcSize);
+size_t ZSTD_compressBlock_btlazy2_extDict(
+        ZSTD_MatchState_t* ms, SeqStore_t* seqStore, U32 rep[ZSTD_REP_NUM],
+        void const* src, size_t srcSize);
+
+#define ZSTD_COMPRESSBLOCK_BTLAZY2 ZSTD_compressBlock_btlazy2
+#define ZSTD_COMPRESSBLOCK_BTLAZY2_DICTMATCHSTATE ZSTD_compressBlock_btlazy2_dictMatchState
+#define ZSTD_COMPRESSBLOCK_BTLAZY2_EXTDICT ZSTD_compressBlock_btlazy2_extDict
+#else
+#define ZSTD_COMPRESSBLOCK_BTLAZY2 NULL
+#define ZSTD_COMPRESSBLOCK_BTLAZY2_DICTMATCHSTATE NULL
+#define ZSTD_COMPRESSBLOCK_BTLAZY2_EXTDICT NULL
+#endif
+
+#endif /* ZSTD_LAZY_H */
diff --git a/src/commonlib/bsd/zstd/compress/zstd_ldm.c b/src/commonlib/bsd/zstd/compress/zstd_ldm.c
new file mode 100644
index 0000000000..969b73152f
--- /dev/null
+++ b/src/commonlib/bsd/zstd/compress/zstd_ldm.c
@@ -0,0 +1,747 @@
+/* SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0-only */
+
+/*
+ * Copyright (c) Meta Platforms, Inc. and affiliates.
+ * All rights reserved.
+ *
+ * This source code is licensed under both the BSD-style license (found in the
+ * LICENSE file in the root directory of this source tree) and the GPLv2 (found
+ * in the COPYING file in the root directory of this source tree).
+ * You may select, at your option, one of the above-listed licenses.
+ */
+
+#include "zstd_ldm.h"
+
+#include "../common/debug.h"
+#include <commonlib/bsd/xxhash.h>
+#include "zstd_fast.h"          /* ZSTD_fillHashTable() */
+#include "zstd_double_fast.h"   /* ZSTD_fillDoubleHashTable() */
+#include "zstd_ldm_geartab.h"
+
+#define LDM_BUCKET_SIZE_LOG 4
+#define LDM_MIN_MATCH_LENGTH 64
+#define LDM_HASH_RLOG 7
+
+typedef struct {
+    U64 rolling;
+    U64 stopMask;
+} ldmRollingHashState_t;
+
+/** ZSTD_ldm_gear_init():
+ *
+ * Initializes the rolling hash state such that it will honor the
+ * settings in params. */
+static void ZSTD_ldm_gear_init(ldmRollingHashState_t* state, ldmParams_t const* params)
+{
+    unsigned maxBitsInMask = MIN(params->minMatchLength, 64);
+    unsigned hashRateLog = params->hashRateLog;
+
+    state->rolling = ~(U32)0;
+
+    /* The choice of the splitting criterion is subject to two conditions:
+     *   1. it has to trigger on average every 2^(hashRateLog) bytes;
+     *   2. ideally, it has to depend on a window of minMatchLength bytes.
+     *
+     * In the gear hash algorithm, bit n depends on the last n bytes;
+     * so in order to obtain a good quality splitting criterion it is
+     * preferable to use bits with high weight.
+     *
+     * To match condition 1 we use a mask with hashRateLog bits set
+     * and, because of the previous remark, we make sure these bits
+     * have the highest possible weight while still respecting
+     * condition 2.
+     */
+    if (hashRateLog > 0 && hashRateLog <= maxBitsInMask) {
+        state->stopMask = (((U64)1 << hashRateLog) - 1) << (maxBitsInMask - hashRateLog);
+    } else {
+        /* In this degenerate case we simply honor the hash rate. */
+        state->stopMask = ((U64)1 << hashRateLog) - 1;
+    }
+}
+
+/** ZSTD_ldm_gear_reset()
+ * Feeds [data, data + minMatchLength) into the hash without registering any
+ * splits. This effectively resets the hash state. This is used when skipping
+ * over data, either at the beginning of a block, or skipping sections.
+ */
+static void ZSTD_ldm_gear_reset(ldmRollingHashState_t* state,
+                                BYTE const* data, size_t minMatchLength)
+{
+    U64 hash = state->rolling;
+    size_t n = 0;
+
+#define GEAR_ITER_ONCE() do {                                  \
+        hash = (hash << 1) + ZSTD_ldm_gearTab[data[n] & 0xff]; \
+        n += 1;                                                \
+    } while (0)
+    while (n + 3 < minMatchLength) {
+        GEAR_ITER_ONCE();
+        GEAR_ITER_ONCE();
+        GEAR_ITER_ONCE();
+        GEAR_ITER_ONCE();
+    }
+    while (n < minMatchLength) {
+        GEAR_ITER_ONCE();
+    }
+#undef GEAR_ITER_ONCE
+}
+
+/** ZSTD_ldm_gear_feed():
+ *
+ * Registers in the splits array all the split points found in the first
+ * size bytes following the data pointer. This function terminates when
+ * either all the data has been processed or LDM_BATCH_SIZE splits are
+ * present in the splits array.
+ *
+ * Precondition: The splits array must not be full.
+ * Returns: The number of bytes processed. */
+static size_t ZSTD_ldm_gear_feed(ldmRollingHashState_t* state,
+                                 BYTE const* data, size_t size,
+                                 size_t* splits, unsigned* numSplits)
+{
+    size_t n;
+    U64 hash, mask;
+
+    hash = state->rolling;
+    mask = state->stopMask;
+    n = 0;
+
+#define GEAR_ITER_ONCE() do { \
+        hash = (hash << 1) + ZSTD_ldm_gearTab[data[n] & 0xff]; \
+        n += 1; \
+        if (UNLIKELY((hash & mask) == 0)) { \
+            splits[*numSplits] = n; \
+            *numSplits += 1; \
+            if (*numSplits == LDM_BATCH_SIZE) \
+                goto done; \
+        } \
+    } while (0)
+
+    while (n + 3 < size) {
+        GEAR_ITER_ONCE();
+        GEAR_ITER_ONCE();
+        GEAR_ITER_ONCE();
+        GEAR_ITER_ONCE();
+    }
+    while (n < size) {
+        GEAR_ITER_ONCE();
+    }
+
+#undef GEAR_ITER_ONCE
+
+done:
+    state->rolling = hash;
+    return n;
+}
+
+void ZSTD_ldm_adjustParameters(ldmParams_t* params,
+                        const ZSTD_compressionParameters* cParams)
+{
+    params->windowLog = cParams->windowLog;
+    ZSTD_STATIC_ASSERT(LDM_BUCKET_SIZE_LOG <= ZSTD_LDM_BUCKETSIZELOG_MAX);
+    DEBUGLOG(4, "ZSTD_ldm_adjustParameters");
+    if (params->hashRateLog == 0) {
+        if (params->hashLog > 0) {
+            /* if params->hashLog is set, derive hashRateLog from it */
+            assert(params->hashLog <= ZSTD_HASHLOG_MAX);
+            if (params->windowLog > params->hashLog) {
+                params->hashRateLog = params->windowLog - params->hashLog;
+            }
+        } else {
+            assert(1 <= (int)cParams->strategy && (int)cParams->strategy <= 9);
+            /* mapping from [fast, rate7] to [btultra2, rate4] */
+            params->hashRateLog = 7 - (cParams->strategy/3);
+        }
+    }
+    if (params->hashLog == 0) {
+        params->hashLog = BOUNDED(ZSTD_HASHLOG_MIN, params->windowLog - params->hashRateLog, ZSTD_HASHLOG_MAX);
+    }
+    if (params->minMatchLength == 0) {
+        params->minMatchLength = LDM_MIN_MATCH_LENGTH;
+        if (cParams->strategy >= ZSTD_btultra)
+            params->minMatchLength /= 2;
+    }
+    if (params->bucketSizeLog==0) {
+        assert(1 <= (int)cParams->strategy && (int)cParams->strategy <= 9);
+        params->bucketSizeLog = BOUNDED(LDM_BUCKET_SIZE_LOG, (U32)cParams->strategy, ZSTD_LDM_BUCKETSIZELOG_MAX);
+    }
+    params->bucketSizeLog = MIN(params->bucketSizeLog, params->hashLog);
+}
+
+size_t ZSTD_ldm_getTableSize(ldmParams_t params)
+{
+    size_t const ldmHSize = ((size_t)1) << params.hashLog;
+    size_t const ldmBucketSizeLog = MIN(params.bucketSizeLog, params.hashLog);
+    size_t const ldmBucketSize = ((size_t)1) << (params.hashLog - ldmBucketSizeLog);
+    size_t const totalSize = ZSTD_cwksp_alloc_size(ldmBucketSize)
+                           + ZSTD_cwksp_alloc_size(ldmHSize * sizeof(ldmEntry_t));
+    return params.enableLdm == ZSTD_ps_enable ? totalSize : 0;
+}
+
+size_t ZSTD_ldm_getMaxNbSeq(ldmParams_t params, size_t maxChunkSize)
+{
+    return params.enableLdm == ZSTD_ps_enable ? (maxChunkSize / params.minMatchLength) : 0;
+}
+
+/** ZSTD_ldm_getBucket() :
+ *  Returns a pointer to the start of the bucket associated with hash. */
+static ldmEntry_t* ZSTD_ldm_getBucket(
+        const ldmState_t* ldmState, size_t hash, U32 const bucketSizeLog)
+{
+    return ldmState->hashTable + (hash << bucketSizeLog);
+}
+
+/** ZSTD_ldm_insertEntry() :
+ *  Insert the entry with corresponding hash into the hash table */
+static void ZSTD_ldm_insertEntry(ldmState_t* ldmState,
+                                 size_t const hash, const ldmEntry_t entry,
+                                 U32 const bucketSizeLog)
+{
+    BYTE* const pOffset = ldmState->bucketOffsets + hash;
+    unsigned const offset = *pOffset;
+
+    *(ZSTD_ldm_getBucket(ldmState, hash, bucketSizeLog) + offset) = entry;
+    *pOffset = (BYTE)((offset + 1) & ((1u << bucketSizeLog) - 1));
+
+}
+
+/** ZSTD_ldm_countBackwardsMatch() :
+ *  Returns the number of bytes that match backwards before pIn and pMatch.
+ *
+ *  We count only bytes where pMatch >= pBase and pIn >= pAnchor. */
+static size_t ZSTD_ldm_countBackwardsMatch(
+            const BYTE* pIn, const BYTE* pAnchor,
+            const BYTE* pMatch, const BYTE* pMatchBase)
+{
+    size_t matchLength = 0;
+    while (pIn > pAnchor && pMatch > pMatchBase && pIn[-1] == pMatch[-1]) {
+        pIn--;
+        pMatch--;
+        matchLength++;
+    }
+    return matchLength;
+}
+
+/** ZSTD_ldm_countBackwardsMatch_2segments() :
+ *  Returns the number of bytes that match backwards from pMatch,
+ *  even with the backwards match spanning 2 different segments.
+ *
+ *  On reaching `pMatchBase`, start counting from mEnd */
+static size_t ZSTD_ldm_countBackwardsMatch_2segments(
+                    const BYTE* pIn, const BYTE* pAnchor,
+                    const BYTE* pMatch, const BYTE* pMatchBase,
+                    const BYTE* pExtDictStart, const BYTE* pExtDictEnd)
+{
+    size_t matchLength = ZSTD_ldm_countBackwardsMatch(pIn, pAnchor, pMatch, pMatchBase);
+    if (pMatch - matchLength != pMatchBase || pMatchBase == pExtDictStart) {
+        /* If backwards match is entirely in the extDict or prefix, immediately return */
+        return matchLength;
+    }
+    DEBUGLOG(7, "ZSTD_ldm_countBackwardsMatch_2segments: found 2-parts backwards match (length in prefix==%zu)", matchLength);
+    matchLength += ZSTD_ldm_countBackwardsMatch(pIn - matchLength, pAnchor, pExtDictEnd, pExtDictStart);
+    DEBUGLOG(7, "final backwards match length = %zu", matchLength);
+    return matchLength;
+}
+
+/** ZSTD_ldm_fillFastTables() :
+ *
+ *  Fills the relevant tables for the ZSTD_fast and ZSTD_dfast strategies.
+ *  This is similar to ZSTD_loadDictionaryContent.
+ *
+ *  The tables for the other strategies are filled within their
+ *  block compressors. */
+static size_t ZSTD_ldm_fillFastTables(ZSTD_MatchState_t* ms,
+                                      void const* end)
+{
+    const BYTE* const iend = (const BYTE*)end;
+
+    switch(ms->cParams.strategy)
+    {
+    case ZSTD_fast:
+        ZSTD_fillHashTable(ms, iend, ZSTD_dtlm_fast, ZSTD_tfp_forCCtx);
+        break;
+
+    case ZSTD_dfast:
+#ifndef ZSTD_EXCLUDE_DFAST_BLOCK_COMPRESSOR
+        ZSTD_fillDoubleHashTable(ms, iend, ZSTD_dtlm_fast, ZSTD_tfp_forCCtx);
+#else
+        assert(0); /* shouldn't be called: cparams should've been adjusted. */
+#endif
+        break;
+
+    case ZSTD_greedy:
+    case ZSTD_lazy:
+    case ZSTD_lazy2:
+    case ZSTD_btlazy2:
+    case ZSTD_btopt:
+    case ZSTD_btultra:
+    case ZSTD_btultra2:
+        break;
+    default:
+        assert(0);  /* not possible : not a valid strategy id */
+    }
+
+    return 0;
+}
+
+void ZSTD_ldm_fillHashTable(
+            ldmState_t* ldmState, const BYTE* ip,
+            const BYTE* iend, ldmParams_t const* params)
+{
+    U32 const minMatchLength = params->minMatchLength;
+    U32 const bucketSizeLog = params->bucketSizeLog;
+    U32 const hBits = params->hashLog - bucketSizeLog;
+    BYTE const* const base = ldmState->window.base;
+    BYTE const* const istart = ip;
+    ldmRollingHashState_t hashState;
+    size_t* const splits = ldmState->splitIndices;
+    unsigned numSplits;
+
+    DEBUGLOG(5, "ZSTD_ldm_fillHashTable");
+
+    ZSTD_ldm_gear_init(&hashState, params);
+    while (ip < iend) {
+        size_t hashed;
+        unsigned n;
+
+        numSplits = 0;
+        hashed = ZSTD_ldm_gear_feed(&hashState, ip, (size_t)(iend - ip), splits, &numSplits);
+
+        for (n = 0; n < numSplits; n++) {
+            if (ip + splits[n] >= istart + minMatchLength) {
+                BYTE const* const split = ip + splits[n] - minMatchLength;
+                U64 const xxhash = XXH64(split, minMatchLength, 0);
+                U32 const hash = (U32)(xxhash & (((U32)1 << hBits) - 1));
+                ldmEntry_t entry;
+
+                entry.offset = (U32)(split - base);
+                entry.checksum = (U32)(xxhash >> 32);
+                ZSTD_ldm_insertEntry(ldmState, hash, entry, params->bucketSizeLog);
+            }
+        }
+
+        ip += hashed;
+    }
+}
+
+
+/** ZSTD_ldm_limitTableUpdate() :
+ *
+ *  Sets cctx->nextToUpdate to a position corresponding closer to anchor
+ *  if it is far way
+ *  (after a long match, only update tables a limited amount). */
+static void ZSTD_ldm_limitTableUpdate(ZSTD_MatchState_t* ms, const BYTE* anchor)
+{
+    U32 const curr = (U32)(anchor - ms->window.base);
+    if (curr > ms->nextToUpdate + 1024) {
+        ms->nextToUpdate =
+            curr - MIN(512, curr - ms->nextToUpdate - 1024);
+    }
+}
+
+static
+ZSTD_ALLOW_POINTER_OVERFLOW_ATTR
+size_t ZSTD_ldm_generateSequences_internal(
+        ldmState_t* ldmState, RawSeqStore_t* rawSeqStore,
+        ldmParams_t const* params, void const* src, size_t srcSize)
+{
+    /* LDM parameters */
+    int const extDict = ZSTD_window_hasExtDict(ldmState->window);
+    U32 const minMatchLength = params->minMatchLength;
+    U32 const entsPerBucket = 1U << params->bucketSizeLog;
+    U32 const hBits = params->hashLog - params->bucketSizeLog;
+    /* Prefix and extDict parameters */
+    U32 const dictLimit = ldmState->window.dictLimit;
+    U32 const lowestIndex = extDict ? ldmState->window.lowLimit : dictLimit;
+    BYTE const* const base = ldmState->window.base;
+    BYTE const* const dictBase = extDict ? ldmState->window.dictBase : NULL;
+    BYTE const* const dictStart = extDict ? dictBase + lowestIndex : NULL;
+    BYTE const* const dictEnd = extDict ? dictBase + dictLimit : NULL;
+    BYTE const* const lowPrefixPtr = base + dictLimit;
+    /* Input bounds */
+    BYTE const* const istart = (BYTE const*)src;
+    BYTE const* const iend = istart + srcSize;
+    BYTE const* const ilimit = iend - HASH_READ_SIZE;
+    /* Input positions */
+    BYTE const* anchor = istart;
+    BYTE const* ip = istart;
+    /* Rolling hash state */
+    ldmRollingHashState_t hashState;
+    /* Arrays for staged-processing */
+    size_t* const splits = ldmState->splitIndices;
+    ldmMatchCandidate_t* const candidates = ldmState->matchCandidates;
+    unsigned numSplits;
+
+    if (srcSize < minMatchLength)
+        return iend - anchor;
+
+    /* Initialize the rolling hash state with the first minMatchLength bytes */
+    ZSTD_ldm_gear_init(&hashState, params);
+    ZSTD_ldm_gear_reset(&hashState, ip, minMatchLength);
+    ip += minMatchLength;
+
+    while (ip < ilimit) {
+        size_t hashed;
+        unsigned n;
+
+        numSplits = 0;
+        hashed = ZSTD_ldm_gear_feed(&hashState, ip, ilimit - ip,
+                                    splits, &numSplits);
+
+        for (n = 0; n < numSplits; n++) {
+            BYTE const* const split = ip + splits[n] - minMatchLength;
+            U64 const xxhash = XXH64(split, minMatchLength, 0);
+            U32 const hash = (U32)(xxhash & (((U32)1 << hBits) - 1));
+
+            candidates[n].split = split;
+            candidates[n].hash = hash;
+            candidates[n].checksum = (U32)(xxhash >> 32);
+            candidates[n].bucket = ZSTD_ldm_getBucket(ldmState, hash, params->bucketSizeLog);
+            PREFETCH_L1(candidates[n].bucket);
+        }
+
+        for (n = 0; n < numSplits; n++) {
+            size_t forwardMatchLength = 0, backwardMatchLength = 0,
+                   bestMatchLength = 0, mLength;
+            U32 offset;
+            BYTE const* const split = candidates[n].split;
+            U32 const checksum = candidates[n].checksum;
+            U32 const hash = candidates[n].hash;
+            ldmEntry_t* const bucket = candidates[n].bucket;
+            ldmEntry_t const* cur;
+            ldmEntry_t const* bestEntry = NULL;
+            ldmEntry_t newEntry;
+
+            newEntry.offset = (U32)(split - base);
+            newEntry.checksum = checksum;
+
+            /* If a split point would generate a sequence overlapping with
+             * the previous one, we merely register it in the hash table and
+             * move on */
+            if (split < anchor) {
+                ZSTD_ldm_insertEntry(ldmState, hash, newEntry, params->bucketSizeLog);
+                continue;
+            }
+
+            for (cur = bucket; cur < bucket + entsPerBucket; cur++) {
+                size_t curForwardMatchLength, curBackwardMatchLength,
+                       curTotalMatchLength;
+                if (cur->checksum != checksum || cur->offset <= lowestIndex) {
+                    continue;
+                }
+                if (extDict) {
+                    BYTE const* const curMatchBase =
+                        cur->offset < dictLimit ? dictBase : base;
+                    BYTE const* const pMatch = curMatchBase + cur->offset;
+                    BYTE const* const matchEnd =
+                        cur->offset < dictLimit ? dictEnd : iend;
+                    BYTE const* const lowMatchPtr =
+                        cur->offset < dictLimit ? dictStart : lowPrefixPtr;
+                    curForwardMatchLength =
+                        ZSTD_count_2segments(split, pMatch, iend, matchEnd, lowPrefixPtr);
+                    if (curForwardMatchLength < minMatchLength) {
+                        continue;
+                    }
+                    curBackwardMatchLength = ZSTD_ldm_countBackwardsMatch_2segments(
+                            split, anchor, pMatch, lowMatchPtr, dictStart, dictEnd);
+                } else { /* !extDict */
+                    BYTE const* const pMatch = base + cur->offset;
+                    curForwardMatchLength = ZSTD_count(split, pMatch, iend);
+                    if (curForwardMatchLength < minMatchLength) {
+                        continue;
+                    }
+                    curBackwardMatchLength =
+                        ZSTD_ldm_countBackwardsMatch(split, anchor, pMatch, lowPrefixPtr);
+                }
+                curTotalMatchLength = curForwardMatchLength + curBackwardMatchLength;
+
+                if (curTotalMatchLength > bestMatchLength) {
+                    bestMatchLength = curTotalMatchLength;
+                    forwardMatchLength = curForwardMatchLength;
+                    backwardMatchLength = curBackwardMatchLength;
+                    bestEntry = cur;
+                }
+            }
+
+            /* No match found -- insert an entry into the hash table
+             * and process the next candidate match */
+            if (bestEntry == NULL) {
+                ZSTD_ldm_insertEntry(ldmState, hash, newEntry, params->bucketSizeLog);
+                continue;
+            }
+
+            /* Match found */
+            offset = (U32)(split - base) - bestEntry->offset;
+            mLength = forwardMatchLength + backwardMatchLength;
+            {
+                rawSeq* const seq = rawSeqStore->seq + rawSeqStore->size;
+
+                /* Out of sequence storage */
+                if (rawSeqStore->size == rawSeqStore->capacity)
+                    return ERROR(dstSize_tooSmall);
+                seq->litLength = (U32)(split - backwardMatchLength - anchor);
+                seq->matchLength = (U32)mLength;
+                seq->offset = offset;
+                rawSeqStore->size++;
+            }
+
+            /* Insert the current entry into the hash table --- it must be
+             * done after the previous block to avoid clobbering bestEntry */
+            ZSTD_ldm_insertEntry(ldmState, hash, newEntry, params->bucketSizeLog);
+
+            anchor = split + forwardMatchLength;
+
+            /* If we find a match that ends after the data that we've hashed
+             * then we have a repeating, overlapping, pattern. E.g. all zeros.
+             * If one repetition of the pattern matches our `stopMask` then all
+             * repetitions will. We don't need to insert them all into out table,
+             * only the first one. So skip over overlapping matches.
+             * This is a major speed boost (20x) for compressing a single byte
+             * repeated, when that byte ends up in the table.
+             */
+            if (anchor > ip + hashed) {
+                ZSTD_ldm_gear_reset(&hashState, anchor - minMatchLength, minMatchLength);
+                /* Continue the outer loop at anchor (ip + hashed == anchor). */
+                ip = anchor - hashed;
+                break;
+            }
+        }
+
+        ip += hashed;
+    }
+
+    return iend - anchor;
+}
+
+/*! ZSTD_ldm_reduceTable() :
+ *  reduce table indexes by `reducerValue` */
+static void ZSTD_ldm_reduceTable(ldmEntry_t* const table, U32 const size,
+                                 U32 const reducerValue)
+{
+    U32 u;
+    for (u = 0; u < size; u++) {
+        if (table[u].offset < reducerValue) table[u].offset = 0;
+        else table[u].offset -= reducerValue;
+    }
+}
+
+size_t ZSTD_ldm_generateSequences(
+        ldmState_t* ldmState, RawSeqStore_t* sequences,
+        ldmParams_t const* params, void const* src, size_t srcSize)
+{
+    U32 const maxDist = 1U << params->windowLog;
+    BYTE const* const istart = (BYTE const*)src;
+    BYTE const* const iend = istart + srcSize;
+    size_t const kMaxChunkSize = 1 << 20;
+    size_t const nbChunks = (srcSize / kMaxChunkSize) + ((srcSize % kMaxChunkSize) != 0);
+    size_t chunk;
+    size_t leftoverSize = 0;
+
+    assert(ZSTD_CHUNKSIZE_MAX >= kMaxChunkSize);
+    /* Check that ZSTD_window_update() has been called for this chunk prior
+     * to passing it to this function.
+     */
+    assert(ldmState->window.nextSrc >= (BYTE const*)src + srcSize);
+    /* The input could be very large (in zstdmt), so it must be broken up into
+     * chunks to enforce the maximum distance and handle overflow correction.
+     */
+    assert(sequences->pos <= sequences->size);
+    assert(sequences->size <= sequences->capacity);
+    for (chunk = 0; chunk < nbChunks && sequences->size < sequences->capacity; ++chunk) {
+        BYTE const* const chunkStart = istart + chunk * kMaxChunkSize;
+        size_t const remaining = (size_t)(iend - chunkStart);
+        BYTE const *const chunkEnd =
+            (remaining < kMaxChunkSize) ? iend : chunkStart + kMaxChunkSize;
+        size_t const chunkSize = chunkEnd - chunkStart;
+        size_t newLeftoverSize;
+        size_t const prevSize = sequences->size;
+
+        assert(chunkStart < iend);
+        /* 1. Perform overflow correction if necessary. */
+        if (ZSTD_window_needOverflowCorrection(ldmState->window, 0, maxDist, ldmState->loadedDictEnd, chunkStart, chunkEnd)) {
+            U32 const ldmHSize = 1U << params->hashLog;
+            U32 const correction = ZSTD_window_correctOverflow(
+                &ldmState->window, /* cycleLog */ 0, maxDist, chunkStart);
+            ZSTD_ldm_reduceTable(ldmState->hashTable, ldmHSize, correction);
+            /* invalidate dictionaries on overflow correction */
+            ldmState->loadedDictEnd = 0;
+        }
+        /* 2. We enforce the maximum offset allowed.
+         *
+         * kMaxChunkSize should be small enough that we don't lose too much of
+         * the window through early invalidation.
+         * TODO: * Test the chunk size.
+         *       * Try invalidation after the sequence generation and test the
+         *         offset against maxDist directly.
+         *
+         * NOTE: Because of dictionaries + sequence splitting we MUST make sure
+         * that any offset used is valid at the END of the sequence, since it may
+         * be split into two sequences. This condition holds when using
+         * ZSTD_window_enforceMaxDist(), but if we move to checking offsets
+         * against maxDist directly, we'll have to carefully handle that case.
+         */
+        ZSTD_window_enforceMaxDist(&ldmState->window, chunkEnd, maxDist, &ldmState->loadedDictEnd, NULL);
+        /* 3. Generate the sequences for the chunk, and get newLeftoverSize. */
+        newLeftoverSize = ZSTD_ldm_generateSequences_internal(
+            ldmState, sequences, params, chunkStart, chunkSize);
+        if (ZSTD_isError(newLeftoverSize))
+            return newLeftoverSize;
+        /* 4. We add the leftover literals from previous iterations to the first
+         *    newly generated sequence, or add the `newLeftoverSize` if none are
+         *    generated.
+         */
+        /* Prepend the leftover literals from the last call */
+        if (prevSize < sequences->size) {
+            sequences->seq[prevSize].litLength += (U32)leftoverSize;
+            leftoverSize = newLeftoverSize;
+        } else {
+            assert(newLeftoverSize == chunkSize);
+            leftoverSize += chunkSize;
+        }
+    }
+    return 0;
+}
+
+void
+ZSTD_ldm_skipSequences(RawSeqStore_t* rawSeqStore, size_t srcSize, U32 const minMatch)
+{
+    while (srcSize > 0 && rawSeqStore->pos < rawSeqStore->size) {
+        rawSeq* seq = rawSeqStore->seq + rawSeqStore->pos;
+        if (srcSize <= seq->litLength) {
+            /* Skip past srcSize literals */
+            seq->litLength -= (U32)srcSize;
+            return;
+        }
+        srcSize -= seq->litLength;
+        seq->litLength = 0;
+        if (srcSize < seq->matchLength) {
+            /* Skip past the first srcSize of the match */
+            seq->matchLength -= (U32)srcSize;
+            if (seq->matchLength < minMatch) {
+                /* The match is too short, omit it */
+                if (rawSeqStore->pos + 1 < rawSeqStore->size) {
+                    seq[1].litLength += seq[0].matchLength;
+                }
+                rawSeqStore->pos++;
+            }
+            return;
+        }
+        srcSize -= seq->matchLength;
+        seq->matchLength = 0;
+        rawSeqStore->pos++;
+    }
+}
+
+/**
+ * If the sequence length is longer than remaining then the sequence is split
+ * between this block and the next.
+ *
+ * Returns the current sequence to handle, or if the rest of the block should
+ * be literals, it returns a sequence with offset == 0.
+ */
+static rawSeq maybeSplitSequence(RawSeqStore_t* rawSeqStore,
+                                 U32 const remaining, U32 const minMatch)
+{
+    rawSeq sequence = rawSeqStore->seq[rawSeqStore->pos];
+    assert(sequence.offset > 0);
+    /* Likely: No partial sequence */
+    if (remaining >= sequence.litLength + sequence.matchLength) {
+        rawSeqStore->pos++;
+        return sequence;
+    }
+    /* Cut the sequence short (offset == 0 ==> rest is literals). */
+    if (remaining <= sequence.litLength) {
+        sequence.offset = 0;
+    } else if (remaining < sequence.litLength + sequence.matchLength) {
+        sequence.matchLength = remaining - sequence.litLength;
+        if (sequence.matchLength < minMatch) {
+            sequence.offset = 0;
+        }
+    }
+    /* Skip past `remaining` bytes for the future sequences. */
+    ZSTD_ldm_skipSequences(rawSeqStore, remaining, minMatch);
+    return sequence;
+}
+
+void ZSTD_ldm_skipRawSeqStoreBytes(RawSeqStore_t* rawSeqStore, size_t nbBytes) {
+    U32 currPos = (U32)(rawSeqStore->posInSequence + nbBytes);
+    while (currPos && rawSeqStore->pos < rawSeqStore->size) {
+        rawSeq currSeq = rawSeqStore->seq[rawSeqStore->pos];
+        if (currPos >= currSeq.litLength + currSeq.matchLength) {
+            currPos -= currSeq.litLength + currSeq.matchLength;
+            rawSeqStore->pos++;
+        } else {
+            rawSeqStore->posInSequence = currPos;
+            break;
+        }
+    }
+    if (currPos == 0 || rawSeqStore->pos == rawSeqStore->size) {
+        rawSeqStore->posInSequence = 0;
+    }
+}
+
+size_t ZSTD_ldm_blockCompress(RawSeqStore_t* rawSeqStore,
+    ZSTD_MatchState_t* ms, SeqStore_t* seqStore, U32 rep[ZSTD_REP_NUM],
+    ZSTD_ParamSwitch_e useRowMatchFinder,
+    void const* src, size_t srcSize)
+{
+    const ZSTD_compressionParameters* const cParams = &ms->cParams;
+    unsigned const minMatch = cParams->minMatch;
+    ZSTD_BlockCompressor_f const blockCompressor =
+        ZSTD_selectBlockCompressor(cParams->strategy, useRowMatchFinder, ZSTD_matchState_dictMode(ms));
+    /* Input bounds */
+    BYTE const* const istart = (BYTE const*)src;
+    BYTE const* const iend = istart + srcSize;
+    /* Input positions */
+    BYTE const* ip = istart;
+
+    DEBUGLOG(5, "ZSTD_ldm_blockCompress: srcSize=%zu", srcSize);
+    /* If using opt parser, use LDMs only as candidates rather than always accepting them */
+    if (cParams->strategy >= ZSTD_btopt) {
+        size_t lastLLSize;
+        ms->ldmSeqStore = rawSeqStore;
+        lastLLSize = blockCompressor(ms, seqStore, rep, src, srcSize);
+        ZSTD_ldm_skipRawSeqStoreBytes(rawSeqStore, srcSize);
+        return lastLLSize;
+    }
+
+    assert(rawSeqStore->pos <= rawSeqStore->size);
+    assert(rawSeqStore->size <= rawSeqStore->capacity);
+    /* Loop through each sequence and apply the block compressor to the literals */
+    while (rawSeqStore->pos < rawSeqStore->size && ip < iend) {
+        /* maybeSplitSequence updates rawSeqStore->pos */
+        rawSeq const sequence = maybeSplitSequence(rawSeqStore,
+                                                   (U32)(iend - ip), minMatch);
+        /* End signal */
+        if (sequence.offset == 0)
+            break;
+
+        assert(ip + sequence.litLength + sequence.matchLength <= iend);
+
+        /* Fill tables for block compressor */
+        ZSTD_ldm_limitTableUpdate(ms, ip);
+        ZSTD_ldm_fillFastTables(ms, ip);
+        /* Run the block compressor */
+        DEBUGLOG(5, "pos %u : calling block compressor on segment of size %u", (unsigned)(ip-istart), sequence.litLength);
+        {
+            int i;
+            size_t const newLitLength =
+                blockCompressor(ms, seqStore, rep, ip, sequence.litLength);
+            ip += sequence.litLength;
+            /* Update the repcodes */
+            for (i = ZSTD_REP_NUM - 1; i > 0; i--)
+                rep[i] = rep[i-1];
+            rep[0] = sequence.offset;
+            /* Store the sequence */
+            ZSTD_storeSeq(seqStore, newLitLength, ip - newLitLength, iend,
+                          OFFSET_TO_OFFBASE(sequence.offset),
+                          sequence.matchLength);
+            ip += sequence.matchLength;
+        }
+    }
+    /* Fill the tables for the block compressor */
+    ZSTD_ldm_limitTableUpdate(ms, ip);
+    ZSTD_ldm_fillFastTables(ms, ip);
+    /* Compress the last literals */
+    return blockCompressor(ms, seqStore, rep, ip, iend - ip);
+}
diff --git a/src/commonlib/bsd/zstd/compress/zstd_ldm.h b/src/commonlib/bsd/zstd/compress/zstd_ldm.h
new file mode 100644
index 0000000000..d69c3648ce
--- /dev/null
+++ b/src/commonlib/bsd/zstd/compress/zstd_ldm.h
@@ -0,0 +1,111 @@
+/* SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0-only */
+
+/*
+ * Copyright (c) Meta Platforms, Inc. and affiliates.
+ * All rights reserved.
+ *
+ * This source code is licensed under both the BSD-style license (found in the
+ * LICENSE file in the root directory of this source tree) and the GPLv2 (found
+ * in the COPYING file in the root directory of this source tree).
+ * You may select, at your option, one of the above-listed licenses.
+ */
+
+#ifndef ZSTD_LDM_H
+#define ZSTD_LDM_H
+
+#include "zstd_compress_internal.h"   /* ldmParams_t, U32 */
+#include "../zstd.h"   /* ZSTD_CCtx, size_t */
+
+/*-*************************************
+*  Long distance matching
+***************************************/
+
+#define ZSTD_LDM_DEFAULT_WINDOW_LOG ZSTD_WINDOWLOG_LIMIT_DEFAULT
+
+void ZSTD_ldm_fillHashTable(
+            ldmState_t* state, const BYTE* ip,
+            const BYTE* iend, ldmParams_t const* params);
+
+/**
+ * ZSTD_ldm_generateSequences():
+ *
+ * Generates the sequences using the long distance match finder.
+ * Generates long range matching sequences in `sequences`, which parse a prefix
+ * of the source. `sequences` must be large enough to store every sequence,
+ * which can be checked with `ZSTD_ldm_getMaxNbSeq()`.
+ * @returns 0 or an error code.
+ *
+ * NOTE: The user must have called ZSTD_window_update() for all of the input
+ * they have, even if they pass it to ZSTD_ldm_generateSequences() in chunks.
+ * NOTE: This function returns an error if it runs out of space to store
+ *       sequences.
+ */
+size_t ZSTD_ldm_generateSequences(
+            ldmState_t* ldms, RawSeqStore_t* sequences,
+            ldmParams_t const* params, void const* src, size_t srcSize);
+
+/**
+ * ZSTD_ldm_blockCompress():
+ *
+ * Compresses a block using the predefined sequences, along with a secondary
+ * block compressor. The literals section of every sequence is passed to the
+ * secondary block compressor, and those sequences are interspersed with the
+ * predefined sequences. Returns the length of the last literals.
+ * Updates `rawSeqStore.pos` to indicate how many sequences have been consumed.
+ * `rawSeqStore.seq` may also be updated to split the last sequence between two
+ * blocks.
+ * @return The length of the last literals.
+ *
+ * NOTE: The source must be at most the maximum block size, but the predefined
+ * sequences can be any size, and may be longer than the block. In the case that
+ * they are longer than the block, the last sequences may need to be split into
+ * two. We handle that case correctly, and update `rawSeqStore` appropriately.
+ * NOTE: This function does not return any errors.
+ */
+size_t ZSTD_ldm_blockCompress(RawSeqStore_t* rawSeqStore,
+            ZSTD_MatchState_t* ms, SeqStore_t* seqStore, U32 rep[ZSTD_REP_NUM],
+            ZSTD_ParamSwitch_e useRowMatchFinder,
+            void const* src, size_t srcSize);
+
+/**
+ * ZSTD_ldm_skipSequences():
+ *
+ * Skip past `srcSize` bytes worth of sequences in `rawSeqStore`.
+ * Avoids emitting matches less than `minMatch` bytes.
+ * Must be called for data that is not passed to ZSTD_ldm_blockCompress().
+ */
+void ZSTD_ldm_skipSequences(RawSeqStore_t* rawSeqStore, size_t srcSize,
+    U32 const minMatch);
+
+/* ZSTD_ldm_skipRawSeqStoreBytes():
+ * Moves forward in rawSeqStore by nbBytes, updating fields 'pos' and 'posInSequence'.
+ * Not to be used in conjunction with ZSTD_ldm_skipSequences().
+ * Must be called for data with is not passed to ZSTD_ldm_blockCompress().
+ */
+void ZSTD_ldm_skipRawSeqStoreBytes(RawSeqStore_t* rawSeqStore, size_t nbBytes);
+
+/** ZSTD_ldm_getTableSize() :
+ *  Estimate the space needed for long distance matching tables or 0 if LDM is
+ *  disabled.
+ */
+size_t ZSTD_ldm_getTableSize(ldmParams_t params);
+
+/** ZSTD_ldm_getSeqSpace() :
+ *  Return an upper bound on the number of sequences that can be produced by
+ *  the long distance matcher, or 0 if LDM is disabled.
+ */
+size_t ZSTD_ldm_getMaxNbSeq(ldmParams_t params, size_t maxChunkSize);
+
+/** ZSTD_ldm_adjustParameters() :
+ *  If the params->hashRateLog is not set, set it to its default value based on
+ *  windowLog and params->hashLog.
+ *
+ *  Ensures that params->bucketSizeLog is <= params->hashLog (setting it to
+ *  params->hashLog if it is not).
+ *
+ *  Ensures that the minMatchLength >= targetLength during optimal parsing.
+ */
+void ZSTD_ldm_adjustParameters(ldmParams_t* params,
+                               ZSTD_compressionParameters const* cParams);
+
+#endif /* ZSTD_FAST_H */
diff --git a/src/commonlib/bsd/zstd/compress/zstd_ldm_geartab.h b/src/commonlib/bsd/zstd/compress/zstd_ldm_geartab.h
new file mode 100644
index 0000000000..be292bb256
--- /dev/null
+++ b/src/commonlib/bsd/zstd/compress/zstd_ldm_geartab.h
@@ -0,0 +1,108 @@
+/* SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0-only */
+
+/*
+ * Copyright (c) Meta Platforms, Inc. and affiliates.
+ * All rights reserved.
+ *
+ * This source code is licensed under both the BSD-style license (found in the
+ * LICENSE file in the root directory of this source tree) and the GPLv2 (found
+ * in the COPYING file in the root directory of this source tree).
+ * You may select, at your option, one of the above-listed licenses.
+ */
+
+#ifndef ZSTD_LDM_GEARTAB_H
+#define ZSTD_LDM_GEARTAB_H
+
+#include "../common/zstd_compiler.h" /* UNUSED_ATTR */
+#include "../common/mem.h"      /* U64 */
+
+static UNUSED_ATTR const U64 ZSTD_ldm_gearTab[256] = {
+    0xf5b8f72c5f77775c, 0x84935f266b7ac412, 0xb647ada9ca730ccc,
+    0xb065bb4b114fb1de, 0x34584e7e8c3a9fd0, 0x4e97e17c6ae26b05,
+    0x3a03d743bc99a604, 0xcecd042422c4044f, 0x76de76c58524259e,
+    0x9c8528f65badeaca, 0x86563706e2097529, 0x2902475fa375d889,
+    0xafb32a9739a5ebe6, 0xce2714da3883e639, 0x21eaf821722e69e,
+    0x37b628620b628,    0x49a8d455d88caf5,  0x8556d711e6958140,
+    0x4f7ae74fc605c1f,  0x829f0c3468bd3a20, 0x4ffdc885c625179e,
+    0x8473de048a3daf1b, 0x51008822b05646b2, 0x69d75d12b2d1cc5f,
+    0x8c9d4a19159154bc, 0xc3cc10f4abbd4003, 0xd06ddc1cecb97391,
+    0xbe48e6e7ed80302e, 0x3481db31cee03547, 0xacc3f67cdaa1d210,
+    0x65cb771d8c7f96cc, 0x8eb27177055723dd, 0xc789950d44cd94be,
+    0x934feadc3700b12b, 0x5e485f11edbdf182, 0x1e2e2a46fd64767a,
+    0x2969ca71d82efa7c, 0x9d46e9935ebbba2e, 0xe056b67e05e6822b,
+    0x94d73f55739d03a0, 0xcd7010bdb69b5a03, 0x455ef9fcd79b82f4,
+    0x869cb54a8749c161, 0x38d1a4fa6185d225, 0xb475166f94bbe9bb,
+    0xa4143548720959f1, 0x7aed4780ba6b26ba, 0xd0ce264439e02312,
+    0x84366d746078d508, 0xa8ce973c72ed17be, 0x21c323a29a430b01,
+    0x9962d617e3af80ee, 0xab0ce91d9c8cf75b, 0x530e8ee6d19a4dbc,
+    0x2ef68c0cf53f5d72, 0xc03a681640a85506, 0x496e4e9f9c310967,
+    0x78580472b59b14a0, 0x273824c23b388577, 0x66bf923ad45cb553,
+    0x47ae1a5a2492ba86, 0x35e304569e229659, 0x4765182a46870b6f,
+    0x6cbab625e9099412, 0xddac9a2e598522c1, 0x7172086e666624f2,
+    0xdf5003ca503b7837, 0x88c0c1db78563d09, 0x58d51865acfc289d,
+    0x177671aec65224f1, 0xfb79d8a241e967d7, 0x2be1e101cad9a49a,
+    0x6625682f6e29186b, 0x399553457ac06e50, 0x35dffb4c23abb74,
+    0x429db2591f54aade, 0xc52802a8037d1009, 0x6acb27381f0b25f3,
+    0xf45e2551ee4f823b, 0x8b0ea2d99580c2f7, 0x3bed519cbcb4e1e1,
+    0xff452823dbb010a,  0x9d42ed614f3dd267, 0x5b9313c06257c57b,
+    0xa114b8008b5e1442, 0xc1fe311c11c13d4b, 0x66e8763ea34c5568,
+    0x8b982af1c262f05d, 0xee8876faaa75fbb7, 0x8a62a4d0d172bb2a,
+    0xc13d94a3b7449a97, 0x6dbbba9dc15d037c, 0xc786101f1d92e0f1,
+    0xd78681a907a0b79b, 0xf61aaf2962c9abb9, 0x2cfd16fcd3cb7ad9,
+    0x868c5b6744624d21, 0x25e650899c74ddd7, 0xba042af4a7c37463,
+    0x4eb1a539465a3eca, 0xbe09dbf03b05d5ca, 0x774e5a362b5472ba,
+    0x47a1221229d183cd, 0x504b0ca18ef5a2df, 0xdffbdfbde2456eb9,
+    0x46cd2b2fbee34634, 0xf2aef8fe819d98c3, 0x357f5276d4599d61,
+    0x24a5483879c453e3, 0x88026889192b4b9,  0x28da96671782dbec,
+    0x4ef37c40588e9aaa, 0x8837b90651bc9fb3, 0xc164f741d3f0e5d6,
+    0xbc135a0a704b70ba, 0x69cd868f7622ada,  0xbc37ba89e0b9c0ab,
+    0x47c14a01323552f6, 0x4f00794bacee98bb, 0x7107de7d637a69d5,
+    0x88af793bb6f2255e, 0xf3c6466b8799b598, 0xc288c616aa7f3b59,
+    0x81ca63cf42fca3fd, 0x88d85ace36a2674b, 0xd056bd3792389e7,
+    0xe55c396c4e9dd32d, 0xbefb504571e6c0a6, 0x96ab32115e91e8cc,
+    0xbf8acb18de8f38d1, 0x66dae58801672606, 0x833b6017872317fb,
+    0xb87c16f2d1c92864, 0xdb766a74e58b669c, 0x89659f85c61417be,
+    0xc8daad856011ea0c, 0x76a4b565b6fe7eae, 0xa469d085f6237312,
+    0xaaf0365683a3e96c, 0x4dbb746f8424f7b8, 0x638755af4e4acc1,
+    0x3d7807f5bde64486, 0x17be6d8f5bbb7639, 0x903f0cd44dc35dc,
+    0x67b672eafdf1196c, 0xa676ff93ed4c82f1, 0x521d1004c5053d9d,
+    0x37ba9ad09ccc9202, 0x84e54d297aacfb51, 0xa0b4b776a143445,
+    0x820d471e20b348e,  0x1874383cb83d46dc, 0x97edeec7a1efe11c,
+    0xb330e50b1bdc42aa, 0x1dd91955ce70e032, 0xa514cdb88f2939d5,
+    0x2791233fd90db9d3, 0x7b670a4cc50f7a9b, 0x77c07d2a05c6dfa5,
+    0xe3778b6646d0a6fa, 0xb39c8eda47b56749, 0x933ed448addbef28,
+    0xaf846af6ab7d0bf4, 0xe5af208eb666e49,  0x5e6622f73534cd6a,
+    0x297daeca42ef5b6e, 0x862daef3d35539a6, 0xe68722498f8e1ea9,
+    0x981c53093dc0d572, 0xfa09b0bfbf86fbf5, 0x30b1e96166219f15,
+    0x70e7d466bdc4fb83, 0x5a66736e35f2a8e9, 0xcddb59d2b7c1baef,
+    0xd6c7d247d26d8996, 0xea4e39eac8de1ba3, 0x539c8bb19fa3aff2,
+    0x9f90e4c5fd508d8,  0xa34e5956fbaf3385, 0x2e2f8e151d3ef375,
+    0x173691e9b83faec1, 0xb85a8d56bf016379, 0x8382381267408ae3,
+    0xb90f901bbdc0096d, 0x7c6ad32933bcec65, 0x76bb5e2f2c8ad595,
+    0x390f851a6cf46d28, 0xc3e6064da1c2da72, 0xc52a0c101cfa5389,
+    0xd78eaf84a3fbc530, 0x3781b9e2288b997e, 0x73c2f6dea83d05c4,
+    0x4228e364c5b5ed7,  0x9d7a3edf0da43911, 0x8edcfeda24686756,
+    0x5e7667a7b7a9b3a1, 0x4c4f389fa143791d, 0xb08bc1023da7cddc,
+    0x7ab4be3ae529b1cc, 0x754e6132dbe74ff9, 0x71635442a839df45,
+    0x2f6fb1643fbe52de, 0x961e0a42cf7a8177, 0xf3b45d83d89ef2ea,
+    0xee3de4cf4a6e3e9b, 0xcd6848542c3295e7, 0xe4cee1664c78662f,
+    0x9947548b474c68c4, 0x25d73777a5ed8b0b, 0xc915b1d636b7fc,
+    0x21c2ba75d9b0d2da, 0x5f6b5dcf608a64a1, 0xdcf333255ff9570c,
+    0x633b922418ced4ee, 0xc136dde0b004b34a, 0x58cc83b05d4b2f5a,
+    0x5eb424dda28e42d2, 0x62df47369739cd98, 0xb4e0b42485e4ce17,
+    0x16e1f0c1f9a8d1e7, 0x8ec3916707560ebf, 0x62ba6e2df2cc9db3,
+    0xcbf9f4ff77d83a16, 0x78d9d7d07d2bbcc4, 0xef554ce1e02c41f4,
+    0x8d7581127eccf94d, 0xa9b53336cb3c8a05, 0x38c42c0bf45c4f91,
+    0x640893cdf4488863, 0x80ec34bc575ea568, 0x39f324f5b48eaa40,
+    0xe9d9ed1f8eff527f, 0x9224fc058cc5a214, 0xbaba00b04cfe7741,
+    0x309a9f120fcf52af, 0xa558f3ec65626212, 0x424bec8b7adabe2f,
+    0x41622513a6aea433, 0xb88da2d5324ca798, 0xd287733b245528a4,
+    0x9a44697e6d68aec3, 0x7b1093be2f49bb28, 0x50bbec632e3d8aad,
+    0x6cd90723e1ea8283, 0x897b9e7431b02bf3, 0x219efdcb338a7047,
+    0x3b0311f0a27c0656, 0xdb17bf91c0db96e7, 0x8cd4fd6b4e85a5b2,
+    0xfab071054ba6409d, 0x40d6fe831fa9dfd9, 0xaf358debad7d791e,
+    0xeb8d0e25a65e3e58, 0xbbcbd3df14e08580, 0xcf751f27ecdab2b,
+    0x2b4da14f2613d8f4
+};
+
+#endif /* ZSTD_LDM_GEARTAB_H */
diff --git a/src/commonlib/bsd/zstd/compress/zstd_opt.c b/src/commonlib/bsd/zstd/compress/zstd_opt.c
new file mode 100644
index 0000000000..519091b82d
--- /dev/null
+++ b/src/commonlib/bsd/zstd/compress/zstd_opt.c
@@ -0,0 +1,1582 @@
+/* SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0-only */
+
+/*
+ * Copyright (c) Meta Platforms, Inc. and affiliates.
+ * All rights reserved.
+ *
+ * This source code is licensed under both the BSD-style license (found in the
+ * LICENSE file in the root directory of this source tree) and the GPLv2 (found
+ * in the COPYING file in the root directory of this source tree).
+ * You may select, at your option, one of the above-listed licenses.
+ */
+
+#include "zstd_compress_internal.h"
+#include "hist.h"
+#include "zstd_opt.h"
+
+#if !defined(ZSTD_EXCLUDE_BTLAZY2_BLOCK_COMPRESSOR) \
+ || !defined(ZSTD_EXCLUDE_BTOPT_BLOCK_COMPRESSOR) \
+ || !defined(ZSTD_EXCLUDE_BTULTRA_BLOCK_COMPRESSOR)
+
+#define ZSTD_LITFREQ_ADD    2   /* scaling factor for litFreq, so that frequencies adapt faster to new stats */
+#define ZSTD_MAX_PRICE     (1<<30)
+
+#define ZSTD_PREDEF_THRESHOLD 8   /* if srcSize < ZSTD_PREDEF_THRESHOLD, symbols' cost is assumed static, directly determined by pre-defined distributions */
+
+
+/*-*************************************
+*  Price functions for optimal parser
+***************************************/
+
+#if 0    /* approximation at bit level (for tests) */
+#  define BITCOST_ACCURACY 0
+#  define BITCOST_MULTIPLIER (1 << BITCOST_ACCURACY)
+#  define WEIGHT(stat, opt) ((void)(opt), ZSTD_bitWeight(stat))
+#elif 0  /* fractional bit accuracy (for tests) */
+#  define BITCOST_ACCURACY 8
+#  define BITCOST_MULTIPLIER (1 << BITCOST_ACCURACY)
+#  define WEIGHT(stat,opt) ((void)(opt), ZSTD_fracWeight(stat))
+#else    /* opt==approx, ultra==accurate */
+#  define BITCOST_ACCURACY 8
+#  define BITCOST_MULTIPLIER (1 << BITCOST_ACCURACY)
+#  define WEIGHT(stat,opt) ((opt) ? ZSTD_fracWeight(stat) : ZSTD_bitWeight(stat))
+#endif
+
+/* ZSTD_bitWeight() :
+ * provide estimated "cost" of a stat in full bits only */
+MEM_STATIC U32 ZSTD_bitWeight(U32 stat)
+{
+    return (ZSTD_highbit32(stat+1) * BITCOST_MULTIPLIER);
+}
+
+/* ZSTD_fracWeight() :
+ * provide fractional-bit "cost" of a stat,
+ * using linear interpolation approximation */
+MEM_STATIC U32 ZSTD_fracWeight(U32 rawStat)
+{
+    U32 const stat = rawStat + 1;
+    U32 const hb = ZSTD_highbit32(stat);
+    U32 const BWeight = hb * BITCOST_MULTIPLIER;
+    /* Fweight was meant for "Fractional weight"
+     * but it's effectively a value between 1 and 2
+     * using fixed point arithmetic */
+    U32 const FWeight = (stat << BITCOST_ACCURACY) >> hb;
+    U32 const weight = BWeight + FWeight;
+    assert(hb + BITCOST_ACCURACY < 31);
+    return weight;
+}
+
+#if (DEBUGLEVEL>=2)
+/* debugging function,
+ * @return price in bytes as fractional value
+ * for debug messages only */
+MEM_STATIC double ZSTD_fCost(int price)
+{
+    return (double)price / (BITCOST_MULTIPLIER*8);
+}
+#endif
+
+static int ZSTD_compressedLiterals(optState_t const* const optPtr)
+{
+    return optPtr->literalCompressionMode != ZSTD_ps_disable;
+}
+
+static void ZSTD_setBasePrices(optState_t* optPtr, int optLevel)
+{
+    if (ZSTD_compressedLiterals(optPtr))
+        optPtr->litSumBasePrice = WEIGHT(optPtr->litSum, optLevel);
+    optPtr->litLengthSumBasePrice = WEIGHT(optPtr->litLengthSum, optLevel);
+    optPtr->matchLengthSumBasePrice = WEIGHT(optPtr->matchLengthSum, optLevel);
+    optPtr->offCodeSumBasePrice = WEIGHT(optPtr->offCodeSum, optLevel);
+}
+
+
+static U32 sum_u32(const unsigned table[], size_t nbElts)
+{
+    size_t n;
+    U32 total = 0;
+    for (n=0; n<nbElts; n++) {
+        total += table[n];
+    }
+    return total;
+}
+
+typedef enum { base_0possible=0, base_1guaranteed=1 } base_directive_e;
+
+static U32
+ZSTD_downscaleStats(unsigned* table, U32 lastEltIndex, U32 shift, base_directive_e base1)
+{
+    U32 s, sum=0;
+    DEBUGLOG(5, "ZSTD_downscaleStats (nbElts=%u, shift=%u)",
+            (unsigned)lastEltIndex+1, (unsigned)shift );
+    assert(shift < 30);
+    for (s=0; s<lastEltIndex+1; s++) {
+        unsigned const base = base1 ? 1 : (table[s]>0);
+        unsigned const newStat = base + (table[s] >> shift);
+        sum += newStat;
+        table[s] = newStat;
+    }
+    return sum;
+}
+
+/* ZSTD_scaleStats() :
+ * reduce all elt frequencies in table if sum too large
+ * return the resulting sum of elements */
+static U32 ZSTD_scaleStats(unsigned* table, U32 lastEltIndex, U32 logTarget)
+{
+    U32 const prevsum = sum_u32(table, lastEltIndex+1);
+    U32 const factor = prevsum >> logTarget;
+    DEBUGLOG(5, "ZSTD_scaleStats (nbElts=%u, target=%u)", (unsigned)lastEltIndex+1, (unsigned)logTarget);
+    assert(logTarget < 30);
+    if (factor <= 1) return prevsum;
+    return ZSTD_downscaleStats(table, lastEltIndex, ZSTD_highbit32(factor), base_1guaranteed);
+}
+
+/* ZSTD_rescaleFreqs() :
+ * if first block (detected by optPtr->litLengthSum == 0) : init statistics
+ *    take hints from dictionary if there is one
+ *    and init from zero if there is none,
+ *    using src for literals stats, and baseline stats for sequence symbols
+ * otherwise downscale existing stats, to be used as seed for next block.
+ */
+static void
+ZSTD_rescaleFreqs(optState_t* const optPtr,
+            const BYTE* const src, size_t const srcSize,
+                  int const optLevel)
+{
+    int const compressedLiterals = ZSTD_compressedLiterals(optPtr);
+    DEBUGLOG(5, "ZSTD_rescaleFreqs (srcSize=%u)", (unsigned)srcSize);
+    optPtr->priceType = zop_dynamic;
+
+    if (optPtr->litLengthSum == 0) {  /* no literals stats collected -> first block assumed -> init */
+
+        /* heuristic: use pre-defined stats for too small inputs */
+        if (srcSize <= ZSTD_PREDEF_THRESHOLD) {
+            DEBUGLOG(5, "srcSize <= %i : use predefined stats", ZSTD_PREDEF_THRESHOLD);
+            optPtr->priceType = zop_predef;
+        }
+
+        assert(optPtr->symbolCosts != NULL);
+        if (optPtr->symbolCosts->huf.repeatMode == HUF_repeat_valid) {
+
+            /* huffman stats covering the full value set : table presumed generated by dictionary */
+            optPtr->priceType = zop_dynamic;
+
+            if (compressedLiterals) {
+                /* generate literals statistics from huffman table */
+                unsigned lit;
+                assert(optPtr->litFreq != NULL);
+                optPtr->litSum = 0;
+                for (lit=0; lit<=MaxLit; lit++) {
+                    U32 const scaleLog = 11;   /* scale to 2K */
+                    U32 const bitCost = HUF_getNbBitsFromCTable(optPtr->symbolCosts->huf.CTable, lit);
+                    assert(bitCost <= scaleLog);
+                    optPtr->litFreq[lit] = bitCost ? 1 << (scaleLog-bitCost) : 1 /*minimum to calculate cost*/;
+                    optPtr->litSum += optPtr->litFreq[lit];
+            }   }
+
+            {   unsigned ll;
+                FSE_CState_t llstate;
+                FSE_initCState(&llstate, optPtr->symbolCosts->fse.litlengthCTable);
+                optPtr->litLengthSum = 0;
+                for (ll=0; ll<=MaxLL; ll++) {
+                    U32 const scaleLog = 10;   /* scale to 1K */
+                    U32 const bitCost = FSE_getMaxNbBits(llstate.symbolTT, ll);
+                    assert(bitCost < scaleLog);
+                    optPtr->litLengthFreq[ll] = bitCost ? 1 << (scaleLog-bitCost) : 1 /*minimum to calculate cost*/;
+                    optPtr->litLengthSum += optPtr->litLengthFreq[ll];
+            }   }
+
+            {   unsigned ml;
+                FSE_CState_t mlstate;
+                FSE_initCState(&mlstate, optPtr->symbolCosts->fse.matchlengthCTable);
+                optPtr->matchLengthSum = 0;
+                for (ml=0; ml<=MaxML; ml++) {
+                    U32 const scaleLog = 10;
+                    U32 const bitCost = FSE_getMaxNbBits(mlstate.symbolTT, ml);
+                    assert(bitCost < scaleLog);
+                    optPtr->matchLengthFreq[ml] = bitCost ? 1 << (scaleLog-bitCost) : 1 /*minimum to calculate cost*/;
+                    optPtr->matchLengthSum += optPtr->matchLengthFreq[ml];
+            }   }
+
+            {   unsigned of;
+                FSE_CState_t ofstate;
+                FSE_initCState(&ofstate, optPtr->symbolCosts->fse.offcodeCTable);
+                optPtr->offCodeSum = 0;
+                for (of=0; of<=MaxOff; of++) {
+                    U32 const scaleLog = 10;
+                    U32 const bitCost = FSE_getMaxNbBits(ofstate.symbolTT, of);
+                    assert(bitCost < scaleLog);
+                    optPtr->offCodeFreq[of] = bitCost ? 1 << (scaleLog-bitCost) : 1 /*minimum to calculate cost*/;
+                    optPtr->offCodeSum += optPtr->offCodeFreq[of];
+            }   }
+
+        } else {  /* first block, no dictionary */
+
+            assert(optPtr->litFreq != NULL);
+            if (compressedLiterals) {
+                /* base initial cost of literals on direct frequency within src */
+                unsigned lit = MaxLit;
+                HIST_count_simple(optPtr->litFreq, &lit, src, srcSize);   /* use raw first block to init statistics */
+                optPtr->litSum = ZSTD_downscaleStats(optPtr->litFreq, MaxLit, 8, base_0possible);
+            }
+
+            {   unsigned const baseLLfreqs[MaxLL+1] = {
+                    4, 2, 1, 1, 1, 1, 1, 1,
+                    1, 1, 1, 1, 1, 1, 1, 1,
+                    1, 1, 1, 1, 1, 1, 1, 1,
+                    1, 1, 1, 1, 1, 1, 1, 1,
+                    1, 1, 1, 1
+                };
+                ZSTD_memcpy(optPtr->litLengthFreq, baseLLfreqs, sizeof(baseLLfreqs));
+                optPtr->litLengthSum = sum_u32(baseLLfreqs, MaxLL+1);
+            }
+
+            {   unsigned ml;
+                for (ml=0; ml<=MaxML; ml++)
+                    optPtr->matchLengthFreq[ml] = 1;
+            }
+            optPtr->matchLengthSum = MaxML+1;
+
+            {   unsigned const baseOFCfreqs[MaxOff+1] = {
+                    6, 2, 1, 1, 2, 3, 4, 4,
+                    4, 3, 2, 1, 1, 1, 1, 1,
+                    1, 1, 1, 1, 1, 1, 1, 1,
+                    1, 1, 1, 1, 1, 1, 1, 1
+                };
+                ZSTD_memcpy(optPtr->offCodeFreq, baseOFCfreqs, sizeof(baseOFCfreqs));
+                optPtr->offCodeSum = sum_u32(baseOFCfreqs, MaxOff+1);
+            }
+
+        }
+
+    } else {   /* new block : scale down accumulated statistics */
+
+        if (compressedLiterals)
+            optPtr->litSum = ZSTD_scaleStats(optPtr->litFreq, MaxLit, 12);
+        optPtr->litLengthSum = ZSTD_scaleStats(optPtr->litLengthFreq, MaxLL, 11);
+        optPtr->matchLengthSum = ZSTD_scaleStats(optPtr->matchLengthFreq, MaxML, 11);
+        optPtr->offCodeSum = ZSTD_scaleStats(optPtr->offCodeFreq, MaxOff, 11);
+    }
+
+    ZSTD_setBasePrices(optPtr, optLevel);
+}
+
+/* ZSTD_rawLiteralsCost() :
+ * price of literals (only) in specified segment (which length can be 0).
+ * does not include price of literalLength symbol */
+static U32 ZSTD_rawLiteralsCost(const BYTE* const literals, U32 const litLength,
+                                const optState_t* const optPtr,
+                                int optLevel)
+{
+    DEBUGLOG(8, "ZSTD_rawLiteralsCost (%u literals)", litLength);
+    if (litLength == 0) return 0;
+
+    if (!ZSTD_compressedLiterals(optPtr))
+        return (litLength << 3) * BITCOST_MULTIPLIER;  /* Uncompressed - 8 bytes per literal. */
+
+    if (optPtr->priceType == zop_predef)
+        return (litLength*6) * BITCOST_MULTIPLIER;  /* 6 bit per literal - no statistic used */
+
+    /* dynamic statistics */
+    {   U32 price = optPtr->litSumBasePrice * litLength;
+        U32 const litPriceMax = optPtr->litSumBasePrice - BITCOST_MULTIPLIER;
+        U32 u;
+        assert(optPtr->litSumBasePrice >= BITCOST_MULTIPLIER);
+        for (u=0; u < litLength; u++) {
+            U32 litPrice = WEIGHT(optPtr->litFreq[literals[u]], optLevel);
+            if (UNLIKELY(litPrice > litPriceMax)) litPrice = litPriceMax;
+            price -= litPrice;
+        }
+        return price;
+    }
+}
+
+/* ZSTD_litLengthPrice() :
+ * cost of literalLength symbol */
+static U32 ZSTD_litLengthPrice(U32 const litLength, const optState_t* const optPtr, int optLevel)
+{
+    assert(litLength <= ZSTD_BLOCKSIZE_MAX);
+    if (optPtr->priceType == zop_predef)
+        return WEIGHT(litLength, optLevel);
+
+    /* ZSTD_LLcode() can't compute litLength price for sizes >= ZSTD_BLOCKSIZE_MAX
+     * because it isn't representable in the zstd format.
+     * So instead just pretend it would cost 1 bit more than ZSTD_BLOCKSIZE_MAX - 1.
+     * In such a case, the block would be all literals.
+     */
+    if (litLength == ZSTD_BLOCKSIZE_MAX)
+        return BITCOST_MULTIPLIER + ZSTD_litLengthPrice(ZSTD_BLOCKSIZE_MAX - 1, optPtr, optLevel);
+
+    /* dynamic statistics */
+    {   U32 const llCode = ZSTD_LLcode(litLength);
+        return (LL_bits[llCode] * BITCOST_MULTIPLIER)
+             + optPtr->litLengthSumBasePrice
+             - WEIGHT(optPtr->litLengthFreq[llCode], optLevel);
+    }
+}
+
+/* ZSTD_getMatchPrice() :
+ * Provides the cost of the match part (offset + matchLength) of a sequence.
+ * Must be combined with ZSTD_fullLiteralsCost() to get the full cost of a sequence.
+ * @offBase : sumtype, representing an offset or a repcode, and using numeric representation of ZSTD_storeSeq()
+ * @optLevel: when <2, favors small offset for decompression speed (improved cache efficiency)
+ */
+FORCE_INLINE_TEMPLATE U32
+ZSTD_getMatchPrice(U32 const offBase,
+                   U32 const matchLength,
+             const optState_t* const optPtr,
+                   int const optLevel)
+{
+    U32 price;
+    U32 const offCode = ZSTD_highbit32(offBase);
+    U32 const mlBase = matchLength - MINMATCH;
+    assert(matchLength >= MINMATCH);
+
+    if (optPtr->priceType == zop_predef)  /* fixed scheme, does not use statistics */
+        return WEIGHT(mlBase, optLevel)
+             + ((16 + offCode) * BITCOST_MULTIPLIER); /* emulated offset cost */
+
+    /* dynamic statistics */
+    price = (offCode * BITCOST_MULTIPLIER) + (optPtr->offCodeSumBasePrice - WEIGHT(optPtr->offCodeFreq[offCode], optLevel));
+    if ((optLevel<2) /*static*/ && offCode >= 20)
+        price += (offCode-19)*2 * BITCOST_MULTIPLIER; /* handicap for long distance offsets, favor decompression speed */
+
+    /* match Length */
+    {   U32 const mlCode = ZSTD_MLcode(mlBase);
+        price += (ML_bits[mlCode] * BITCOST_MULTIPLIER) + (optPtr->matchLengthSumBasePrice - WEIGHT(optPtr->matchLengthFreq[mlCode], optLevel));
+    }
+
+    price += BITCOST_MULTIPLIER / 5;   /* heuristic : make matches a bit more costly to favor less sequences -> faster decompression speed */
+
+    DEBUGLOG(8, "ZSTD_getMatchPrice(ml:%u) = %u", matchLength, price);
+    return price;
+}
+
+/* ZSTD_updateStats() :
+ * assumption : literals + litLength <= iend */
+static void ZSTD_updateStats(optState_t* const optPtr,
+                             U32 litLength, const BYTE* literals,
+                             U32 offBase, U32 matchLength)
+{
+    /* literals */
+    if (ZSTD_compressedLiterals(optPtr)) {
+        U32 u;
+        for (u=0; u < litLength; u++)
+            optPtr->litFreq[literals[u]] += ZSTD_LITFREQ_ADD;
+        optPtr->litSum += litLength*ZSTD_LITFREQ_ADD;
+    }
+
+    /* literal Length */
+    {   U32 const llCode = ZSTD_LLcode(litLength);
+        optPtr->litLengthFreq[llCode]++;
+        optPtr->litLengthSum++;
+    }
+
+    /* offset code : follows storeSeq() numeric representation */
+    {   U32 const offCode = ZSTD_highbit32(offBase);
+        assert(offCode <= MaxOff);
+        optPtr->offCodeFreq[offCode]++;
+        optPtr->offCodeSum++;
+    }
+
+    /* match Length */
+    {   U32 const mlBase = matchLength - MINMATCH;
+        U32 const mlCode = ZSTD_MLcode(mlBase);
+        optPtr->matchLengthFreq[mlCode]++;
+        optPtr->matchLengthSum++;
+    }
+}
+
+
+/* ZSTD_readMINMATCH() :
+ * function safe only for comparisons
+ * assumption : memPtr must be at least 4 bytes before end of buffer */
+MEM_STATIC U32 ZSTD_readMINMATCH(const void* memPtr, U32 length)
+{
+    switch (length)
+    {
+    default :
+    case 4 : return MEM_read32(memPtr);
+    case 3 : if (MEM_isLittleEndian())
+                return MEM_read32(memPtr)<<8;
+             else
+                return MEM_read32(memPtr)>>8;
+    }
+}
+
+
+/* Update hashTable3 up to ip (excluded)
+   Assumption : always within prefix (i.e. not within extDict) */
+static
+ZSTD_ALLOW_POINTER_OVERFLOW_ATTR
+U32 ZSTD_insertAndFindFirstIndexHash3 (const ZSTD_MatchState_t* ms,
+                                       U32* nextToUpdate3,
+                                       const BYTE* const ip)
+{
+    U32* const hashTable3 = ms->hashTable3;
+    U32 const hashLog3 = ms->hashLog3;
+    const BYTE* const base = ms->window.base;
+    U32 idx = *nextToUpdate3;
+    U32 const target = (U32)(ip - base);
+    size_t const hash3 = ZSTD_hash3Ptr(ip, hashLog3);
+    assert(hashLog3 > 0);
+
+    while(idx < target) {
+        hashTable3[ZSTD_hash3Ptr(base+idx, hashLog3)] = idx;
+        idx++;
+    }
+
+    *nextToUpdate3 = target;
+    return hashTable3[hash3];
+}
+
+
+/*-*************************************
+*  Binary Tree search
+***************************************/
+/** ZSTD_insertBt1() : add one or multiple positions to tree.
+ * @param ip assumed <= iend-8 .
+ * @param target The target of ZSTD_updateTree_internal() - we are filling to this position
+ * @return : nb of positions added */
+static
+ZSTD_ALLOW_POINTER_OVERFLOW_ATTR
+U32 ZSTD_insertBt1(
+                const ZSTD_MatchState_t* ms,
+                const BYTE* const ip, const BYTE* const iend,
+                U32 const target,
+                U32 const mls, const int extDict)
+{
+    const ZSTD_compressionParameters* const cParams = &ms->cParams;
+    U32*   const hashTable = ms->hashTable;
+    U32    const hashLog = cParams->hashLog;
+    size_t const h  = ZSTD_hashPtr(ip, hashLog, mls);
+    U32*   const bt = ms->chainTable;
+    U32    const btLog  = cParams->chainLog - 1;
+    U32    const btMask = (1 << btLog) - 1;
+    U32 matchIndex = hashTable[h];
+    size_t commonLengthSmaller=0, commonLengthLarger=0;
+    const BYTE* const base = ms->window.base;
+    const BYTE* const dictBase = ms->window.dictBase;
+    const U32 dictLimit = ms->window.dictLimit;
+    const BYTE* const dictEnd = dictBase + dictLimit;
+    const BYTE* const prefixStart = base + dictLimit;
+    const BYTE* match;
+    const U32 curr = (U32)(ip-base);
+    const U32 btLow = btMask >= curr ? 0 : curr - btMask;
+    U32* smallerPtr = bt + 2*(curr&btMask);
+    U32* largerPtr  = smallerPtr + 1;
+    U32 dummy32;   /* to be nullified at the end */
+    /* windowLow is based on target because
+     * we only need positions that will be in the window at the end of the tree update.
+     */
+    U32 const windowLow = ZSTD_getLowestMatchIndex(ms, target, cParams->windowLog);
+    U32 matchEndIdx = curr+8+1;
+    size_t bestLength = 8;
+    U32 nbCompares = 1U << cParams->searchLog;
+#ifdef ZSTD_C_PREDICT
+    U32 predictedSmall = *(bt + 2*((curr-1)&btMask) + 0);
+    U32 predictedLarge = *(bt + 2*((curr-1)&btMask) + 1);
+    predictedSmall += (predictedSmall>0);
+    predictedLarge += (predictedLarge>0);
+#endif /* ZSTD_C_PREDICT */
+
+    DEBUGLOG(8, "ZSTD_insertBt1 (%u)", curr);
+
+    assert(curr <= target);
+    assert(ip <= iend-8);   /* required for h calculation */
+    hashTable[h] = curr;   /* Update Hash Table */
+
+    assert(windowLow > 0);
+    for (; nbCompares && (matchIndex >= windowLow); --nbCompares) {
+        U32* const nextPtr = bt + 2*(matchIndex & btMask);
+        size_t matchLength = MIN(commonLengthSmaller, commonLengthLarger);   /* guaranteed minimum nb of common bytes */
+        assert(matchIndex < curr);
+
+#ifdef ZSTD_C_PREDICT   /* note : can create issues when hlog small <= 11 */
+        const U32* predictPtr = bt + 2*((matchIndex-1) & btMask);   /* written this way, as bt is a roll buffer */
+        if (matchIndex == predictedSmall) {
+            /* no need to check length, result known */
+            *smallerPtr = matchIndex;
+            if (matchIndex <= btLow) { smallerPtr=&dummy32; break; }   /* beyond tree size, stop the search */
+            smallerPtr = nextPtr+1;               /* new "smaller" => larger of match */
+            matchIndex = nextPtr[1];              /* new matchIndex larger than previous (closer to current) */
+            predictedSmall = predictPtr[1] + (predictPtr[1]>0);
+            continue;
+        }
+        if (matchIndex == predictedLarge) {
+            *largerPtr = matchIndex;
+            if (matchIndex <= btLow) { largerPtr=&dummy32; break; }   /* beyond tree size, stop the search */
+            largerPtr = nextPtr;
+            matchIndex = nextPtr[0];
+            predictedLarge = predictPtr[0] + (predictPtr[0]>0);
+            continue;
+        }
+#endif
+
+        if (!extDict || (matchIndex+matchLength >= dictLimit)) {
+            assert(matchIndex+matchLength >= dictLimit);   /* might be wrong if actually extDict */
+            match = base + matchIndex;
+            matchLength += ZSTD_count(ip+matchLength, match+matchLength, iend);
+        } else {
+            match = dictBase + matchIndex;
+            matchLength += ZSTD_count_2segments(ip+matchLength, match+matchLength, iend, dictEnd, prefixStart);
+            if (matchIndex+matchLength >= dictLimit)
+                match = base + matchIndex;   /* to prepare for next usage of match[matchLength] */
+        }
+
+        if (matchLength > bestLength) {
+            bestLength = matchLength;
+            if (matchLength > matchEndIdx - matchIndex)
+                matchEndIdx = matchIndex + (U32)matchLength;
+        }
+
+        if (ip+matchLength == iend) {   /* equal : no way to know if inf or sup */
+            break;   /* drop , to guarantee consistency ; miss a bit of compression, but other solutions can corrupt tree */
+        }
+
+        if (match[matchLength] < ip[matchLength]) {  /* necessarily within buffer */
+            /* match is smaller than current */
+            *smallerPtr = matchIndex;             /* update smaller idx */
+            commonLengthSmaller = matchLength;    /* all smaller will now have at least this guaranteed common length */
+            if (matchIndex <= btLow) { smallerPtr=&dummy32; break; }   /* beyond tree size, stop searching */
+            smallerPtr = nextPtr+1;               /* new "candidate" => larger than match, which was smaller than target */
+            matchIndex = nextPtr[1];              /* new matchIndex, larger than previous and closer to current */
+        } else {
+            /* match is larger than current */
+            *largerPtr = matchIndex;
+            commonLengthLarger = matchLength;
+            if (matchIndex <= btLow) { largerPtr=&dummy32; break; }   /* beyond tree size, stop searching */
+            largerPtr = nextPtr;
+            matchIndex = nextPtr[0];
+    }   }
+
+    *smallerPtr = *largerPtr = 0;
+    {   U32 positions = 0;
+        if (bestLength > 384) positions = MIN(192, (U32)(bestLength - 384));   /* speed optimization */
+        assert(matchEndIdx > curr + 8);
+        return MAX(positions, matchEndIdx - (curr + 8));
+    }
+}
+
+FORCE_INLINE_TEMPLATE
+ZSTD_ALLOW_POINTER_OVERFLOW_ATTR
+void ZSTD_updateTree_internal(
+                ZSTD_MatchState_t* ms,
+                const BYTE* const ip, const BYTE* const iend,
+                const U32 mls, const ZSTD_dictMode_e dictMode)
+{
+    const BYTE* const base = ms->window.base;
+    U32 const target = (U32)(ip - base);
+    U32 idx = ms->nextToUpdate;
+    DEBUGLOG(7, "ZSTD_updateTree_internal, from %u to %u  (dictMode:%u)",
+                idx, target, dictMode);
+
+    while(idx < target) {
+        U32 const forward = ZSTD_insertBt1(ms, base+idx, iend, target, mls, dictMode == ZSTD_extDict);
+        assert(idx < (U32)(idx + forward));
+        idx += forward;
+    }
+    assert((size_t)(ip - base) <= (size_t)(U32)(-1));
+    assert((size_t)(iend - base) <= (size_t)(U32)(-1));
+    ms->nextToUpdate = target;
+}
+
+void ZSTD_updateTree(ZSTD_MatchState_t* ms, const BYTE* ip, const BYTE* iend) {
+    ZSTD_updateTree_internal(ms, ip, iend, ms->cParams.minMatch, ZSTD_noDict);
+}
+
+FORCE_INLINE_TEMPLATE
+ZSTD_ALLOW_POINTER_OVERFLOW_ATTR
+U32
+ZSTD_insertBtAndGetAllMatches (
+                ZSTD_match_t* matches,  /* store result (found matches) in this table (presumed large enough) */
+                ZSTD_MatchState_t* ms,
+                U32* nextToUpdate3,
+                const BYTE* const ip, const BYTE* const iLimit,
+                const ZSTD_dictMode_e dictMode,
+                const U32 rep[ZSTD_REP_NUM],
+                const U32 ll0,  /* tells if associated literal length is 0 or not. This value must be 0 or 1 */
+                const U32 lengthToBeat,
+                const U32 mls /* template */)
+{
+    const ZSTD_compressionParameters* const cParams = &ms->cParams;
+    U32 const sufficient_len = MIN(cParams->targetLength, ZSTD_OPT_NUM -1);
+    const BYTE* const base = ms->window.base;
+    U32 const curr = (U32)(ip-base);
+    U32 const hashLog = cParams->hashLog;
+    U32 const minMatch = (mls==3) ? 3 : 4;
+    U32* const hashTable = ms->hashTable;
+    size_t const h  = ZSTD_hashPtr(ip, hashLog, mls);
+    U32 matchIndex  = hashTable[h];
+    U32* const bt   = ms->chainTable;
+    U32 const btLog = cParams->chainLog - 1;
+    U32 const btMask= (1U << btLog) - 1;
+    size_t commonLengthSmaller=0, commonLengthLarger=0;
+    const BYTE* const dictBase = ms->window.dictBase;
+    U32 const dictLimit = ms->window.dictLimit;
+    const BYTE* const dictEnd = dictBase + dictLimit;
+    const BYTE* const prefixStart = base + dictLimit;
+    U32 const btLow = (btMask >= curr) ? 0 : curr - btMask;
+    U32 const windowLow = ZSTD_getLowestMatchIndex(ms, curr, cParams->windowLog);
+    U32 const matchLow = windowLow ? windowLow : 1;
+    U32* smallerPtr = bt + 2*(curr&btMask);
+    U32* largerPtr  = bt + 2*(curr&btMask) + 1;
+    U32 matchEndIdx = curr+8+1;   /* farthest referenced position of any match => detects repetitive patterns */
+    U32 dummy32;   /* to be nullified at the end */
+    U32 mnum = 0;
+    U32 nbCompares = 1U << cParams->searchLog;
+
+    const ZSTD_MatchState_t* dms    = dictMode == ZSTD_dictMatchState ? ms->dictMatchState : NULL;
+    const ZSTD_compressionParameters* const dmsCParams =
+                                      dictMode == ZSTD_dictMatchState ? &dms->cParams : NULL;
+    const BYTE* const dmsBase       = dictMode == ZSTD_dictMatchState ? dms->window.base : NULL;
+    const BYTE* const dmsEnd        = dictMode == ZSTD_dictMatchState ? dms->window.nextSrc : NULL;
+    U32         const dmsHighLimit  = dictMode == ZSTD_dictMatchState ? (U32)(dmsEnd - dmsBase) : 0;
+    U32         const dmsLowLimit   = dictMode == ZSTD_dictMatchState ? dms->window.lowLimit : 0;
+    U32         const dmsIndexDelta = dictMode == ZSTD_dictMatchState ? windowLow - dmsHighLimit : 0;
+    U32         const dmsHashLog    = dictMode == ZSTD_dictMatchState ? dmsCParams->hashLog : hashLog;
+    U32         const dmsBtLog      = dictMode == ZSTD_dictMatchState ? dmsCParams->chainLog - 1 : btLog;
+    U32         const dmsBtMask     = dictMode == ZSTD_dictMatchState ? (1U << dmsBtLog) - 1 : 0;
+    U32         const dmsBtLow      = dictMode == ZSTD_dictMatchState && dmsBtMask < dmsHighLimit - dmsLowLimit ? dmsHighLimit - dmsBtMask : dmsLowLimit;
+
+    size_t bestLength = lengthToBeat-1;
+    DEBUGLOG(8, "ZSTD_insertBtAndGetAllMatches: current=%u", curr);
+
+    /* check repCode */
+    assert(ll0 <= 1);   /* necessarily 1 or 0 */
+    {   U32 const lastR = ZSTD_REP_NUM + ll0;
+        U32 repCode;
+        for (repCode = ll0; repCode < lastR; repCode++) {
+            U32 const repOffset = (repCode==ZSTD_REP_NUM) ? (rep[0] - 1) : rep[repCode];
+            U32 const repIndex = curr - repOffset;
+            U32 repLen = 0;
+            assert(curr >= dictLimit);
+            if (repOffset-1 /* intentional overflow, discards 0 and -1 */ < curr-dictLimit) {  /* equivalent to `curr > repIndex >= dictLimit` */
+                /* We must validate the repcode offset because when we're using a dictionary the
+                 * valid offset range shrinks when the dictionary goes out of bounds.
+                 */
+                if ((repIndex >= windowLow) & (ZSTD_readMINMATCH(ip, minMatch) == ZSTD_readMINMATCH(ip - repOffset, minMatch))) {
+                    repLen = (U32)ZSTD_count(ip+minMatch, ip+minMatch-repOffset, iLimit) + minMatch;
+                }
+            } else {  /* repIndex < dictLimit || repIndex >= curr */
+                const BYTE* const repMatch = dictMode == ZSTD_dictMatchState ?
+                                             dmsBase + repIndex - dmsIndexDelta :
+                                             dictBase + repIndex;
+                assert(curr >= windowLow);
+                if ( dictMode == ZSTD_extDict
+                  && ( ((repOffset-1) /*intentional overflow*/ < curr - windowLow)  /* equivalent to `curr > repIndex >= windowLow` */
+                     & (ZSTD_index_overlap_check(dictLimit, repIndex)) )
+                  && (ZSTD_readMINMATCH(ip, minMatch) == ZSTD_readMINMATCH(repMatch, minMatch)) ) {
+                    repLen = (U32)ZSTD_count_2segments(ip+minMatch, repMatch+minMatch, iLimit, dictEnd, prefixStart) + minMatch;
+                }
+                if (dictMode == ZSTD_dictMatchState
+                  && ( ((repOffset-1) /*intentional overflow*/ < curr - (dmsLowLimit + dmsIndexDelta))  /* equivalent to `curr > repIndex >= dmsLowLimit` */
+                     & (ZSTD_index_overlap_check(dictLimit, repIndex)) )
+                  && (ZSTD_readMINMATCH(ip, minMatch) == ZSTD_readMINMATCH(repMatch, minMatch)) ) {
+                    repLen = (U32)ZSTD_count_2segments(ip+minMatch, repMatch+minMatch, iLimit, dmsEnd, prefixStart) + minMatch;
+            }   }
+            /* save longer solution */
+            if (repLen > bestLength) {
+                DEBUGLOG(8, "found repCode %u (ll0:%u, offset:%u) of length %u",
+                            repCode, ll0, repOffset, repLen);
+                bestLength = repLen;
+                matches[mnum].off = REPCODE_TO_OFFBASE(repCode - ll0 + 1);  /* expect value between 1 and 3 */
+                matches[mnum].len = (U32)repLen;
+                mnum++;
+                if ( (repLen > sufficient_len)
+                   | (ip+repLen == iLimit) ) {  /* best possible */
+                    return mnum;
+    }   }   }   }
+
+    /* HC3 match finder */
+    if ((mls == 3) /*static*/ && (bestLength < mls)) {
+        U32 const matchIndex3 = ZSTD_insertAndFindFirstIndexHash3(ms, nextToUpdate3, ip);
+        if ((matchIndex3 >= matchLow)
+          & (curr - matchIndex3 < (1<<18)) /*heuristic : longer distance likely too expensive*/ ) {
+            size_t mlen;
+            if ((dictMode == ZSTD_noDict) /*static*/ || (dictMode == ZSTD_dictMatchState) /*static*/ || (matchIndex3 >= dictLimit)) {
+                const BYTE* const match = base + matchIndex3;
+                mlen = ZSTD_count(ip, match, iLimit);
+            } else {
+                const BYTE* const match = dictBase + matchIndex3;
+                mlen = ZSTD_count_2segments(ip, match, iLimit, dictEnd, prefixStart);
+            }
+
+            /* save best solution */
+            if (mlen >= mls /* == 3 > bestLength */) {
+                DEBUGLOG(8, "found small match with hlog3, of length %u",
+                            (U32)mlen);
+                bestLength = mlen;
+                assert(curr > matchIndex3);
+                assert(mnum==0);  /* no prior solution */
+                matches[0].off = OFFSET_TO_OFFBASE(curr - matchIndex3);
+                matches[0].len = (U32)mlen;
+                mnum = 1;
+                if ( (mlen > sufficient_len) |
+                     (ip+mlen == iLimit) ) {  /* best possible length */
+                    ms->nextToUpdate = curr+1;  /* skip insertion */
+                    return 1;
+        }   }   }
+        /* no dictMatchState lookup: dicts don't have a populated HC3 table */
+    }  /* if (mls == 3) */
+
+    hashTable[h] = curr;   /* Update Hash Table */
+
+    for (; nbCompares && (matchIndex >= matchLow); --nbCompares) {
+        U32* const nextPtr = bt + 2*(matchIndex & btMask);
+        const BYTE* match;
+        size_t matchLength = MIN(commonLengthSmaller, commonLengthLarger);   /* guaranteed minimum nb of common bytes */
+        assert(curr > matchIndex);
+
+        if ((dictMode == ZSTD_noDict) || (dictMode == ZSTD_dictMatchState) || (matchIndex+matchLength >= dictLimit)) {
+            assert(matchIndex+matchLength >= dictLimit);  /* ensure the condition is correct when !extDict */
+            match = base + matchIndex;
+            if (matchIndex >= dictLimit) assert(memcmp(match, ip, matchLength) == 0);  /* ensure early section of match is equal as expected */
+            matchLength += ZSTD_count(ip+matchLength, match+matchLength, iLimit);
+        } else {
+            match = dictBase + matchIndex;
+            assert(memcmp(match, ip, matchLength) == 0);  /* ensure early section of match is equal as expected */
+            matchLength += ZSTD_count_2segments(ip+matchLength, match+matchLength, iLimit, dictEnd, prefixStart);
+            if (matchIndex+matchLength >= dictLimit)
+                match = base + matchIndex;   /* prepare for match[matchLength] read */
+        }
+
+        if (matchLength > bestLength) {
+            DEBUGLOG(8, "found match of length %u at distance %u (offBase=%u)",
+                    (U32)matchLength, curr - matchIndex, OFFSET_TO_OFFBASE(curr - matchIndex));
+            assert(matchEndIdx > matchIndex);
+            if (matchLength > matchEndIdx - matchIndex)
+                matchEndIdx = matchIndex + (U32)matchLength;
+            bestLength = matchLength;
+            matches[mnum].off = OFFSET_TO_OFFBASE(curr - matchIndex);
+            matches[mnum].len = (U32)matchLength;
+            mnum++;
+            if ( (matchLength > ZSTD_OPT_NUM)
+               | (ip+matchLength == iLimit) /* equal : no way to know if inf or sup */) {
+                if (dictMode == ZSTD_dictMatchState) nbCompares = 0; /* break should also skip searching dms */
+                break; /* drop, to preserve bt consistency (miss a little bit of compression) */
+        }   }
+
+        if (match[matchLength] < ip[matchLength]) {
+            /* match smaller than current */
+            *smallerPtr = matchIndex;             /* update smaller idx */
+            commonLengthSmaller = matchLength;    /* all smaller will now have at least this guaranteed common length */
+            if (matchIndex <= btLow) { smallerPtr=&dummy32; break; }   /* beyond tree size, stop the search */
+            smallerPtr = nextPtr+1;               /* new candidate => larger than match, which was smaller than current */
+            matchIndex = nextPtr[1];              /* new matchIndex, larger than previous, closer to current */
+        } else {
+            *largerPtr = matchIndex;
+            commonLengthLarger = matchLength;
+            if (matchIndex <= btLow) { largerPtr=&dummy32; break; }   /* beyond tree size, stop the search */
+            largerPtr = nextPtr;
+            matchIndex = nextPtr[0];
+    }   }
+
+    *smallerPtr = *largerPtr = 0;
+
+    assert(nbCompares <= (1U << ZSTD_SEARCHLOG_MAX)); /* Check we haven't underflowed. */
+    if (dictMode == ZSTD_dictMatchState && nbCompares) {
+        size_t const dmsH = ZSTD_hashPtr(ip, dmsHashLog, mls);
+        U32 dictMatchIndex = dms->hashTable[dmsH];
+        const U32* const dmsBt = dms->chainTable;
+        commonLengthSmaller = commonLengthLarger = 0;
+        for (; nbCompares && (dictMatchIndex > dmsLowLimit); --nbCompares) {
+            const U32* const nextPtr = dmsBt + 2*(dictMatchIndex & dmsBtMask);
+            size_t matchLength = MIN(commonLengthSmaller, commonLengthLarger);   /* guaranteed minimum nb of common bytes */
+            const BYTE* match = dmsBase + dictMatchIndex;
+            matchLength += ZSTD_count_2segments(ip+matchLength, match+matchLength, iLimit, dmsEnd, prefixStart);
+            if (dictMatchIndex+matchLength >= dmsHighLimit)
+                match = base + dictMatchIndex + dmsIndexDelta;   /* to prepare for next usage of match[matchLength] */
+
+            if (matchLength > bestLength) {
+                matchIndex = dictMatchIndex + dmsIndexDelta;
+                DEBUGLOG(8, "found dms match of length %u at distance %u (offBase=%u)",
+                        (U32)matchLength, curr - matchIndex, OFFSET_TO_OFFBASE(curr - matchIndex));
+                if (matchLength > matchEndIdx - matchIndex)
+                    matchEndIdx = matchIndex + (U32)matchLength;
+                bestLength = matchLength;
+                matches[mnum].off = OFFSET_TO_OFFBASE(curr - matchIndex);
+                matches[mnum].len = (U32)matchLength;
+                mnum++;
+                if ( (matchLength > ZSTD_OPT_NUM)
+                   | (ip+matchLength == iLimit) /* equal : no way to know if inf or sup */) {
+                    break;   /* drop, to guarantee consistency (miss a little bit of compression) */
+            }   }
+
+            if (dictMatchIndex <= dmsBtLow) { break; }   /* beyond tree size, stop the search */
+            if (match[matchLength] < ip[matchLength]) {
+                commonLengthSmaller = matchLength;    /* all smaller will now have at least this guaranteed common length */
+                dictMatchIndex = nextPtr[1];              /* new matchIndex larger than previous (closer to current) */
+            } else {
+                /* match is larger than current */
+                commonLengthLarger = matchLength;
+                dictMatchIndex = nextPtr[0];
+    }   }   }  /* if (dictMode == ZSTD_dictMatchState) */
+
+    assert(matchEndIdx > curr+8);
+    ms->nextToUpdate = matchEndIdx - 8;  /* skip repetitive patterns */
+    return mnum;
+}
+
+typedef U32 (*ZSTD_getAllMatchesFn)(
+    ZSTD_match_t*,
+    ZSTD_MatchState_t*,
+    U32*,
+    const BYTE*,
+    const BYTE*,
+    const U32 rep[ZSTD_REP_NUM],
+    U32 const ll0,
+    U32 const lengthToBeat);
+
+FORCE_INLINE_TEMPLATE
+ZSTD_ALLOW_POINTER_OVERFLOW_ATTR
+U32 ZSTD_btGetAllMatches_internal(
+        ZSTD_match_t* matches,
+        ZSTD_MatchState_t* ms,
+        U32* nextToUpdate3,
+        const BYTE* ip,
+        const BYTE* const iHighLimit,
+        const U32 rep[ZSTD_REP_NUM],
+        U32 const ll0,
+        U32 const lengthToBeat,
+        const ZSTD_dictMode_e dictMode,
+        const U32 mls)
+{
+    assert(BOUNDED(3, ms->cParams.minMatch, 6) == mls);
+    DEBUGLOG(8, "ZSTD_BtGetAllMatches(dictMode=%d, mls=%u)", (int)dictMode, mls);
+    if (ip < ms->window.base + ms->nextToUpdate)
+        return 0;   /* skipped area */
+    ZSTD_updateTree_internal(ms, ip, iHighLimit, mls, dictMode);
+    return ZSTD_insertBtAndGetAllMatches(matches, ms, nextToUpdate3, ip, iHighLimit, dictMode, rep, ll0, lengthToBeat, mls);
+}
+
+#define ZSTD_BT_GET_ALL_MATCHES_FN(dictMode, mls) ZSTD_btGetAllMatches_##dictMode##_##mls
+
+#define GEN_ZSTD_BT_GET_ALL_MATCHES_(dictMode, mls)            \
+    static U32 ZSTD_BT_GET_ALL_MATCHES_FN(dictMode, mls)(      \
+            ZSTD_match_t* matches,                             \
+            ZSTD_MatchState_t* ms,                             \
+            U32* nextToUpdate3,                                \
+            const BYTE* ip,                                    \
+            const BYTE* const iHighLimit,                      \
+            const U32 rep[ZSTD_REP_NUM],                       \
+            U32 const ll0,                                     \
+            U32 const lengthToBeat)                            \
+    {                                                          \
+        return ZSTD_btGetAllMatches_internal(                  \
+                matches, ms, nextToUpdate3, ip, iHighLimit,    \
+                rep, ll0, lengthToBeat, ZSTD_##dictMode, mls); \
+    }
+
+#define GEN_ZSTD_BT_GET_ALL_MATCHES(dictMode)  \
+    GEN_ZSTD_BT_GET_ALL_MATCHES_(dictMode, 3)  \
+    GEN_ZSTD_BT_GET_ALL_MATCHES_(dictMode, 4)  \
+    GEN_ZSTD_BT_GET_ALL_MATCHES_(dictMode, 5)  \
+    GEN_ZSTD_BT_GET_ALL_MATCHES_(dictMode, 6)
+
+GEN_ZSTD_BT_GET_ALL_MATCHES(noDict)
+GEN_ZSTD_BT_GET_ALL_MATCHES(extDict)
+GEN_ZSTD_BT_GET_ALL_MATCHES(dictMatchState)
+
+#define ZSTD_BT_GET_ALL_MATCHES_ARRAY(dictMode)  \
+    {                                            \
+        ZSTD_BT_GET_ALL_MATCHES_FN(dictMode, 3), \
+        ZSTD_BT_GET_ALL_MATCHES_FN(dictMode, 4), \
+        ZSTD_BT_GET_ALL_MATCHES_FN(dictMode, 5), \
+        ZSTD_BT_GET_ALL_MATCHES_FN(dictMode, 6)  \
+    }
+
+static ZSTD_getAllMatchesFn
+ZSTD_selectBtGetAllMatches(ZSTD_MatchState_t const* ms, ZSTD_dictMode_e const dictMode)
+{
+    ZSTD_getAllMatchesFn const getAllMatchesFns[3][4] = {
+        ZSTD_BT_GET_ALL_MATCHES_ARRAY(noDict),
+        ZSTD_BT_GET_ALL_MATCHES_ARRAY(extDict),
+        ZSTD_BT_GET_ALL_MATCHES_ARRAY(dictMatchState)
+    };
+    U32 const mls = BOUNDED(3, ms->cParams.minMatch, 6);
+    assert((U32)dictMode < 3);
+    assert(mls - 3 < 4);
+    return getAllMatchesFns[(int)dictMode][mls - 3];
+}
+
+/*************************
+*  LDM helper functions  *
+*************************/
+
+/* Struct containing info needed to make decision about ldm inclusion */
+typedef struct {
+    RawSeqStore_t seqStore;   /* External match candidates store for this block */
+    U32 startPosInBlock;      /* Start position of the current match candidate */
+    U32 endPosInBlock;        /* End position of the current match candidate */
+    U32 offset;               /* Offset of the match candidate */
+} ZSTD_optLdm_t;
+
+/* ZSTD_optLdm_skipRawSeqStoreBytes():
+ * Moves forward in @rawSeqStore by @nbBytes,
+ * which will update the fields 'pos' and 'posInSequence'.
+ */
+static void ZSTD_optLdm_skipRawSeqStoreBytes(RawSeqStore_t* rawSeqStore, size_t nbBytes)
+{
+    U32 currPos = (U32)(rawSeqStore->posInSequence + nbBytes);
+    while (currPos && rawSeqStore->pos < rawSeqStore->size) {
+        rawSeq currSeq = rawSeqStore->seq[rawSeqStore->pos];
+        if (currPos >= currSeq.litLength + currSeq.matchLength) {
+            currPos -= currSeq.litLength + currSeq.matchLength;
+            rawSeqStore->pos++;
+        } else {
+            rawSeqStore->posInSequence = currPos;
+            break;
+        }
+    }
+    if (currPos == 0 || rawSeqStore->pos == rawSeqStore->size) {
+        rawSeqStore->posInSequence = 0;
+    }
+}
+
+/* ZSTD_opt_getNextMatchAndUpdateSeqStore():
+ * Calculates the beginning and end of the next match in the current block.
+ * Updates 'pos' and 'posInSequence' of the ldmSeqStore.
+ */
+static void
+ZSTD_opt_getNextMatchAndUpdateSeqStore(ZSTD_optLdm_t* optLdm, U32 currPosInBlock,
+                                       U32 blockBytesRemaining)
+{
+    rawSeq currSeq;
+    U32 currBlockEndPos;
+    U32 literalsBytesRemaining;
+    U32 matchBytesRemaining;
+
+    /* Setting match end position to MAX to ensure we never use an LDM during this block */
+    if (optLdm->seqStore.size == 0 || optLdm->seqStore.pos >= optLdm->seqStore.size) {
+        optLdm->startPosInBlock = UINT_MAX;
+        optLdm->endPosInBlock = UINT_MAX;
+        return;
+    }
+    /* Calculate appropriate bytes left in matchLength and litLength
+     * after adjusting based on ldmSeqStore->posInSequence */
+    currSeq = optLdm->seqStore.seq[optLdm->seqStore.pos];
+    assert(optLdm->seqStore.posInSequence <= currSeq.litLength + currSeq.matchLength);
+    currBlockEndPos = currPosInBlock + blockBytesRemaining;
+    literalsBytesRemaining = (optLdm->seqStore.posInSequence < currSeq.litLength) ?
+            currSeq.litLength - (U32)optLdm->seqStore.posInSequence :
+            0;
+    matchBytesRemaining = (literalsBytesRemaining == 0) ?
+            currSeq.matchLength - ((U32)optLdm->seqStore.posInSequence - currSeq.litLength) :
+            currSeq.matchLength;
+
+    /* If there are more literal bytes than bytes remaining in block, no ldm is possible */
+    if (literalsBytesRemaining >= blockBytesRemaining) {
+        optLdm->startPosInBlock = UINT_MAX;
+        optLdm->endPosInBlock = UINT_MAX;
+        ZSTD_optLdm_skipRawSeqStoreBytes(&optLdm->seqStore, blockBytesRemaining);
+        return;
+    }
+
+    /* Matches may be < minMatch by this process. In that case, we will reject them
+       when we are deciding whether or not to add the ldm */
+    optLdm->startPosInBlock = currPosInBlock + literalsBytesRemaining;
+    optLdm->endPosInBlock = optLdm->startPosInBlock + matchBytesRemaining;
+    optLdm->offset = currSeq.offset;
+
+    if (optLdm->endPosInBlock > currBlockEndPos) {
+        /* Match ends after the block ends, we can't use the whole match */
+        optLdm->endPosInBlock = currBlockEndPos;
+        ZSTD_optLdm_skipRawSeqStoreBytes(&optLdm->seqStore, currBlockEndPos - currPosInBlock);
+    } else {
+        /* Consume nb of bytes equal to size of sequence left */
+        ZSTD_optLdm_skipRawSeqStoreBytes(&optLdm->seqStore, literalsBytesRemaining + matchBytesRemaining);
+    }
+}
+
+/* ZSTD_optLdm_maybeAddMatch():
+ * Adds a match if it's long enough,
+ * based on it's 'matchStartPosInBlock' and 'matchEndPosInBlock',
+ * into 'matches'. Maintains the correct ordering of 'matches'.
+ */
+static void ZSTD_optLdm_maybeAddMatch(ZSTD_match_t* matches, U32* nbMatches,
+                                      const ZSTD_optLdm_t* optLdm, U32 currPosInBlock,
+                                      U32 minMatch)
+{
+    U32 const posDiff = currPosInBlock - optLdm->startPosInBlock;
+    /* Note: ZSTD_match_t actually contains offBase and matchLength (before subtracting MINMATCH) */
+    U32 const candidateMatchLength = optLdm->endPosInBlock - optLdm->startPosInBlock - posDiff;
+
+    /* Ensure that current block position is not outside of the match */
+    if (currPosInBlock < optLdm->startPosInBlock
+      || currPosInBlock >= optLdm->endPosInBlock
+      || candidateMatchLength < minMatch) {
+        return;
+    }
+
+    if (*nbMatches == 0 || ((candidateMatchLength > matches[*nbMatches-1].len) && *nbMatches < ZSTD_OPT_NUM)) {
+        U32 const candidateOffBase = OFFSET_TO_OFFBASE(optLdm->offset);
+        DEBUGLOG(6, "ZSTD_optLdm_maybeAddMatch(): Adding ldm candidate match (offBase: %u matchLength %u) at block position=%u",
+                 candidateOffBase, candidateMatchLength, currPosInBlock);
+        matches[*nbMatches].len = candidateMatchLength;
+        matches[*nbMatches].off = candidateOffBase;
+        (*nbMatches)++;
+    }
+}
+
+/* ZSTD_optLdm_processMatchCandidate():
+ * Wrapper function to update ldm seq store and call ldm functions as necessary.
+ */
+static void
+ZSTD_optLdm_processMatchCandidate(ZSTD_optLdm_t* optLdm,
+                                  ZSTD_match_t* matches, U32* nbMatches,
+                                  U32 currPosInBlock, U32 remainingBytes,
+                                  U32 minMatch)
+{
+    if (optLdm->seqStore.size == 0 || optLdm->seqStore.pos >= optLdm->seqStore.size) {
+        return;
+    }
+
+    if (currPosInBlock >= optLdm->endPosInBlock) {
+        if (currPosInBlock > optLdm->endPosInBlock) {
+            /* The position at which ZSTD_optLdm_processMatchCandidate() is called is not necessarily
+             * at the end of a match from the ldm seq store, and will often be some bytes
+             * over beyond matchEndPosInBlock. As such, we need to correct for these "overshoots"
+             */
+            U32 const posOvershoot = currPosInBlock - optLdm->endPosInBlock;
+            ZSTD_optLdm_skipRawSeqStoreBytes(&optLdm->seqStore, posOvershoot);
+        }
+        ZSTD_opt_getNextMatchAndUpdateSeqStore(optLdm, currPosInBlock, remainingBytes);
+    }
+    ZSTD_optLdm_maybeAddMatch(matches, nbMatches, optLdm, currPosInBlock, minMatch);
+}
+
+
+/*-*******************************
+*  Optimal parser
+*********************************/
+
+#if 0 /* debug */
+
+static void
+listStats(const U32* table, int lastEltID)
+{
+    int const nbElts = lastEltID + 1;
+    int enb;
+    for (enb=0; enb < nbElts; enb++) {
+        (void)table;
+        /* RAWLOG(2, "%3i:%3i,  ", enb, table[enb]); */
+        RAWLOG(2, "%4i,", table[enb]);
+    }
+    RAWLOG(2, " \n");
+}
+
+#endif
+
+#define LIT_PRICE(_p) (int)ZSTD_rawLiteralsCost(_p, 1, optStatePtr, optLevel)
+#define LL_PRICE(_l) (int)ZSTD_litLengthPrice(_l, optStatePtr, optLevel)
+#define LL_INCPRICE(_l) (LL_PRICE(_l) - LL_PRICE(_l-1))
+
+FORCE_INLINE_TEMPLATE
+ZSTD_ALLOW_POINTER_OVERFLOW_ATTR
+size_t
+ZSTD_compressBlock_opt_generic(ZSTD_MatchState_t* ms,
+                               SeqStore_t* seqStore,
+                               U32 rep[ZSTD_REP_NUM],
+                         const void* src, size_t srcSize,
+                         const int optLevel,
+                         const ZSTD_dictMode_e dictMode)
+{
+    optState_t* const optStatePtr = &ms->opt;
+    const BYTE* const istart = (const BYTE*)src;
+    const BYTE* ip = istart;
+    const BYTE* anchor = istart;
+    const BYTE* const iend = istart + srcSize;
+    const BYTE* const ilimit = iend - 8;
+    const BYTE* const base = ms->window.base;
+    const BYTE* const prefixStart = base + ms->window.dictLimit;
+    const ZSTD_compressionParameters* const cParams = &ms->cParams;
+
+    ZSTD_getAllMatchesFn getAllMatches = ZSTD_selectBtGetAllMatches(ms, dictMode);
+
+    U32 const sufficient_len = MIN(cParams->targetLength, ZSTD_OPT_NUM -1);
+    U32 const minMatch = (cParams->minMatch == 3) ? 3 : 4;
+    U32 nextToUpdate3 = ms->nextToUpdate;
+
+    ZSTD_optimal_t* const opt = optStatePtr->priceTable;
+    ZSTD_match_t* const matches = optStatePtr->matchTable;
+    ZSTD_optimal_t lastStretch;
+    ZSTD_optLdm_t optLdm;
+
+    ZSTD_memset(&lastStretch, 0, sizeof(ZSTD_optimal_t));
+
+    optLdm.seqStore = ms->ldmSeqStore ? *ms->ldmSeqStore : kNullRawSeqStore;
+    optLdm.endPosInBlock = optLdm.startPosInBlock = optLdm.offset = 0;
+    ZSTD_opt_getNextMatchAndUpdateSeqStore(&optLdm, (U32)(ip-istart), (U32)(iend-ip));
+
+    /* init */
+    DEBUGLOG(5, "ZSTD_compressBlock_opt_generic: current=%u, prefix=%u, nextToUpdate=%u",
+                (U32)(ip - base), ms->window.dictLimit, ms->nextToUpdate);
+    assert(optLevel <= 2);
+    ZSTD_rescaleFreqs(optStatePtr, (const BYTE*)src, srcSize, optLevel);
+    ip += (ip==prefixStart);
+
+    /* Match Loop */
+    while (ip < ilimit) {
+        U32 cur, last_pos = 0;
+
+        /* find first match */
+        {   U32 const litlen = (U32)(ip - anchor);
+            U32 const ll0 = !litlen;
+            U32 nbMatches = getAllMatches(matches, ms, &nextToUpdate3, ip, iend, rep, ll0, minMatch);
+            ZSTD_optLdm_processMatchCandidate(&optLdm, matches, &nbMatches,
+                                              (U32)(ip-istart), (U32)(iend-ip),
+                                              minMatch);
+            if (!nbMatches) {
+                DEBUGLOG(8, "no match found at cPos %u", (unsigned)(ip-istart));
+                ip++;
+                continue;
+            }
+
+            /* Match found: let's store this solution, and eventually find more candidates.
+             * During this forward pass, @opt is used to store stretches,
+             * defined as "a match followed by N literals".
+             * Note how this is different from a Sequence, which is "N literals followed by a match".
+             * Storing stretches allows us to store different match predecessors
+             * for each literal position part of a literals run. */
+
+            /* initialize opt[0] */
+            opt[0].mlen = 0;  /* there are only literals so far */
+            opt[0].litlen = litlen;
+            /* No need to include the actual price of the literals before the first match
+             * because it is static for the duration of the forward pass, and is included
+             * in every subsequent price. But, we include the literal length because
+             * the cost variation of litlen depends on the value of litlen.
+             */
+            opt[0].price = LL_PRICE(litlen);
+            ZSTD_STATIC_ASSERT(sizeof(opt[0].rep[0]) == sizeof(rep[0]));
+            ZSTD_memcpy(&opt[0].rep, rep, sizeof(opt[0].rep));
+
+            /* large match -> immediate encoding */
+            {   U32 const maxML = matches[nbMatches-1].len;
+                U32 const maxOffBase = matches[nbMatches-1].off;
+                DEBUGLOG(6, "found %u matches of maxLength=%u and maxOffBase=%u at cPos=%u => start new series",
+                            nbMatches, maxML, maxOffBase, (U32)(ip-prefixStart));
+
+                if (maxML > sufficient_len) {
+                    lastStretch.litlen = 0;
+                    lastStretch.mlen = maxML;
+                    lastStretch.off = maxOffBase;
+                    DEBUGLOG(6, "large match (%u>%u) => immediate encoding",
+                                maxML, sufficient_len);
+                    cur = 0;
+                    last_pos = maxML;
+                    goto _shortestPath;
+            }   }
+
+            /* set prices for first matches starting position == 0 */
+            assert(opt[0].price >= 0);
+            {   U32 pos;
+                U32 matchNb;
+                for (pos = 1; pos < minMatch; pos++) {
+                    opt[pos].price = ZSTD_MAX_PRICE;
+                    opt[pos].mlen = 0;
+                    opt[pos].litlen = litlen + pos;
+                }
+                for (matchNb = 0; matchNb < nbMatches; matchNb++) {
+                    U32 const offBase = matches[matchNb].off;
+                    U32 const end = matches[matchNb].len;
+                    for ( ; pos <= end ; pos++ ) {
+                        int const matchPrice = (int)ZSTD_getMatchPrice(offBase, pos, optStatePtr, optLevel);
+                        int const sequencePrice = opt[0].price + matchPrice;
+                        DEBUGLOG(7, "rPos:%u => set initial price : %.2f",
+                                    pos, ZSTD_fCost(sequencePrice));
+                        opt[pos].mlen = pos;
+                        opt[pos].off = offBase;
+                        opt[pos].litlen = 0; /* end of match */
+                        opt[pos].price = sequencePrice + LL_PRICE(0);
+                    }
+                }
+                last_pos = pos-1;
+                opt[pos].price = ZSTD_MAX_PRICE;
+            }
+        }
+
+        /* check further positions */
+        for (cur = 1; cur <= last_pos; cur++) {
+            const BYTE* const inr = ip + cur;
+            assert(cur <= ZSTD_OPT_NUM);
+            DEBUGLOG(7, "cPos:%i==rPos:%u", (int)(inr-istart), cur);
+
+            /* Fix current position with one literal if cheaper */
+            {   U32 const litlen = opt[cur-1].litlen + 1;
+                int const price = opt[cur-1].price
+                                + LIT_PRICE(ip+cur-1)
+                                + LL_INCPRICE(litlen);
+                assert(price < 1000000000); /* overflow check */
+                if (price <= opt[cur].price) {
+                    ZSTD_optimal_t const prevMatch = opt[cur];
+                    DEBUGLOG(7, "cPos:%i==rPos:%u : better price (%.2f<=%.2f) using literal (ll==%u) (hist:%u,%u,%u)",
+                                (int)(inr-istart), cur, ZSTD_fCost(price), ZSTD_fCost(opt[cur].price), litlen,
+                                opt[cur-1].rep[0], opt[cur-1].rep[1], opt[cur-1].rep[2]);
+                    opt[cur] = opt[cur-1];
+                    opt[cur].litlen = litlen;
+                    opt[cur].price = price;
+                    if ( (optLevel >= 1) /* additional check only for higher modes */
+                      && (prevMatch.litlen == 0) /* replace a match */
+                      && (LL_INCPRICE(1) < 0) /* ll1 is cheaper than ll0 */
+                      && LIKELY(ip + cur < iend)
+                    ) {
+                        /* check next position, in case it would be cheaper */
+                        int with1literal = prevMatch.price + LIT_PRICE(ip+cur) + LL_INCPRICE(1);
+                        int withMoreLiterals = price + LIT_PRICE(ip+cur) + LL_INCPRICE(litlen+1);
+                        DEBUGLOG(7, "then at next rPos %u : match+1lit %.2f vs %ulits %.2f",
+                                cur+1, ZSTD_fCost(with1literal), litlen+1, ZSTD_fCost(withMoreLiterals));
+                        if ( (with1literal < withMoreLiterals)
+                          && (with1literal < opt[cur+1].price) ) {
+                            /* update offset history - before it disappears */
+                            U32 const prev = cur - prevMatch.mlen;
+                            Repcodes_t const newReps = ZSTD_newRep(opt[prev].rep, prevMatch.off, opt[prev].litlen==0);
+                            assert(cur >= prevMatch.mlen);
+                            DEBUGLOG(7, "==> match+1lit is cheaper (%.2f < %.2f) (hist:%u,%u,%u) !",
+                                        ZSTD_fCost(with1literal), ZSTD_fCost(withMoreLiterals),
+                                        newReps.rep[0], newReps.rep[1], newReps.rep[2] );
+                            opt[cur+1] = prevMatch;  /* mlen & offbase */
+                            ZSTD_memcpy(opt[cur+1].rep, &newReps, sizeof(Repcodes_t));
+                            opt[cur+1].litlen = 1;
+                            opt[cur+1].price = with1literal;
+                            if (last_pos < cur+1) last_pos = cur+1;
+                        }
+                    }
+                } else {
+                    DEBUGLOG(7, "cPos:%i==rPos:%u : literal would cost more (%.2f>%.2f)",
+                                (int)(inr-istart), cur, ZSTD_fCost(price), ZSTD_fCost(opt[cur].price));
+                }
+            }
+
+            /* Offset history is not updated during match comparison.
+             * Do it here, now that the match is selected and confirmed.
+             */
+            ZSTD_STATIC_ASSERT(sizeof(opt[cur].rep) == sizeof(Repcodes_t));
+            assert(cur >= opt[cur].mlen);
+            if (opt[cur].litlen == 0) {
+                /* just finished a match => alter offset history */
+                U32 const prev = cur - opt[cur].mlen;
+                Repcodes_t const newReps = ZSTD_newRep(opt[prev].rep, opt[cur].off, opt[prev].litlen==0);
+                ZSTD_memcpy(opt[cur].rep, &newReps, sizeof(Repcodes_t));
+            }
+
+            /* last match must start at a minimum distance of 8 from oend */
+            if (inr > ilimit) continue;
+
+            if (cur == last_pos) break;
+
+            if ( (optLevel==0) /*static_test*/
+              && (opt[cur+1].price <= opt[cur].price + (BITCOST_MULTIPLIER/2)) ) {
+                DEBUGLOG(7, "skip current position : next rPos(%u) price is cheaper", cur+1);
+                continue;  /* skip unpromising positions; about ~+6% speed, -0.01 ratio */
+            }
+
+            assert(opt[cur].price >= 0);
+            {   U32 const ll0 = (opt[cur].litlen == 0);
+                int const previousPrice = opt[cur].price;
+                int const basePrice = previousPrice + LL_PRICE(0);
+                U32 nbMatches = getAllMatches(matches, ms, &nextToUpdate3, inr, iend, opt[cur].rep, ll0, minMatch);
+                U32 matchNb;
+
+                ZSTD_optLdm_processMatchCandidate(&optLdm, matches, &nbMatches,
+                                                  (U32)(inr-istart), (U32)(iend-inr),
+                                                  minMatch);
+
+                if (!nbMatches) {
+                    DEBUGLOG(7, "rPos:%u : no match found", cur);
+                    continue;
+                }
+
+                {   U32 const longestML = matches[nbMatches-1].len;
+                    DEBUGLOG(7, "cPos:%i==rPos:%u, found %u matches, of longest ML=%u",
+                                (int)(inr-istart), cur, nbMatches, longestML);
+
+                    if ( (longestML > sufficient_len)
+                      || (cur + longestML >= ZSTD_OPT_NUM)
+                      || (ip + cur + longestML >= iend) ) {
+                        lastStretch.mlen = longestML;
+                        lastStretch.off = matches[nbMatches-1].off;
+                        lastStretch.litlen = 0;
+                        last_pos = cur + longestML;
+                        goto _shortestPath;
+                }   }
+
+                /* set prices using matches found at position == cur */
+                for (matchNb = 0; matchNb < nbMatches; matchNb++) {
+                    U32 const offset = matches[matchNb].off;
+                    U32 const lastML = matches[matchNb].len;
+                    U32 const startML = (matchNb>0) ? matches[matchNb-1].len+1 : minMatch;
+                    U32 mlen;
+
+                    DEBUGLOG(7, "testing match %u => offBase=%4u, mlen=%2u, llen=%2u",
+                                matchNb, matches[matchNb].off, lastML, opt[cur].litlen);
+
+                    for (mlen = lastML; mlen >= startML; mlen--) {  /* scan downward */
+                        U32 const pos = cur + mlen;
+                        int const price = basePrice + (int)ZSTD_getMatchPrice(offset, mlen, optStatePtr, optLevel);
+
+                        if ((pos > last_pos) || (price < opt[pos].price)) {
+                            DEBUGLOG(7, "rPos:%u (ml=%2u) => new better price (%.2f<%.2f)",
+                                        pos, mlen, ZSTD_fCost(price), ZSTD_fCost(opt[pos].price));
+                            while (last_pos < pos) {
+                                /* fill empty positions, for future comparisons */
+                                last_pos++;
+                                opt[last_pos].price = ZSTD_MAX_PRICE;
+                                opt[last_pos].litlen = !0;  /* just needs to be != 0, to mean "not an end of match" */
+                            }
+                            opt[pos].mlen = mlen;
+                            opt[pos].off = offset;
+                            opt[pos].litlen = 0;
+                            opt[pos].price = price;
+                        } else {
+                            DEBUGLOG(7, "rPos:%u (ml=%2u) => new price is worse (%.2f>=%.2f)",
+                                        pos, mlen, ZSTD_fCost(price), ZSTD_fCost(opt[pos].price));
+                            if (optLevel==0) break;  /* early update abort; gets ~+10% speed for about -0.01 ratio loss */
+                        }
+            }   }   }
+            opt[last_pos+1].price = ZSTD_MAX_PRICE;
+        }  /* for (cur = 1; cur <= last_pos; cur++) */
+
+        lastStretch = opt[last_pos];
+        assert(cur >= lastStretch.mlen);
+        cur = last_pos - lastStretch.mlen;
+
+_shortestPath:   /* cur, last_pos, best_mlen, best_off have to be set */
+        assert(opt[0].mlen == 0);
+        assert(last_pos >= lastStretch.mlen);
+        assert(cur == last_pos - lastStretch.mlen);
+
+        if (lastStretch.mlen==0) {
+            /* no solution : all matches have been converted into literals */
+            assert(lastStretch.litlen == (ip - anchor) + last_pos);
+            ip += last_pos;
+            continue;
+        }
+        assert(lastStretch.off > 0);
+
+        /* Update offset history */
+        if (lastStretch.litlen == 0) {
+            /* finishing on a match : update offset history */
+            Repcodes_t const reps = ZSTD_newRep(opt[cur].rep, lastStretch.off, opt[cur].litlen==0);
+            ZSTD_memcpy(rep, &reps, sizeof(Repcodes_t));
+        } else {
+            ZSTD_memcpy(rep, lastStretch.rep, sizeof(Repcodes_t));
+            assert(cur >= lastStretch.litlen);
+            cur -= lastStretch.litlen;
+        }
+
+        /* Let's write the shortest path solution.
+         * It is stored in @opt in reverse order,
+         * starting from @storeEnd (==cur+2),
+         * effectively partially @opt overwriting.
+         * Content is changed too:
+         * - So far, @opt stored stretches, aka a match followed by literals
+         * - Now, it will store sequences, aka literals followed by a match
+         */
+        {   U32 const storeEnd = cur + 2;
+            U32 storeStart = storeEnd;
+            U32 stretchPos = cur;
+
+            DEBUGLOG(6, "start reverse traversal (last_pos:%u, cur:%u)",
+                        last_pos, cur); (void)last_pos;
+            assert(storeEnd < ZSTD_OPT_SIZE);
+            DEBUGLOG(6, "last stretch copied into pos=%u (llen=%u,mlen=%u,ofc=%u)",
+                        storeEnd, lastStretch.litlen, lastStretch.mlen, lastStretch.off);
+            if (lastStretch.litlen > 0) {
+                /* last "sequence" is unfinished: just a bunch of literals */
+                opt[storeEnd].litlen = lastStretch.litlen;
+                opt[storeEnd].mlen = 0;
+                storeStart = storeEnd-1;
+                opt[storeStart] = lastStretch;
+            } {
+                opt[storeEnd] = lastStretch;  /* note: litlen will be fixed */
+                storeStart = storeEnd;
+            }
+            while (1) {
+                ZSTD_optimal_t nextStretch = opt[stretchPos];
+                opt[storeStart].litlen = nextStretch.litlen;
+                DEBUGLOG(6, "selected sequence (llen=%u,mlen=%u,ofc=%u)",
+                            opt[storeStart].litlen, opt[storeStart].mlen, opt[storeStart].off);
+                if (nextStretch.mlen == 0) {
+                    /* reaching beginning of segment */
+                    break;
+                }
+                storeStart--;
+                opt[storeStart] = nextStretch; /* note: litlen will be fixed */
+                assert(nextStretch.litlen + nextStretch.mlen <= stretchPos);
+                stretchPos -= nextStretch.litlen + nextStretch.mlen;
+            }
+
+            /* save sequences */
+            DEBUGLOG(6, "sending selected sequences into seqStore");
+            {   U32 storePos;
+                for (storePos=storeStart; storePos <= storeEnd; storePos++) {
+                    U32 const llen = opt[storePos].litlen;
+                    U32 const mlen = opt[storePos].mlen;
+                    U32 const offBase = opt[storePos].off;
+                    U32 const advance = llen + mlen;
+                    DEBUGLOG(6, "considering seq starting at %i, llen=%u, mlen=%u",
+                                (int)(anchor - istart), (unsigned)llen, (unsigned)mlen);
+
+                    if (mlen==0) {  /* only literals => must be last "sequence", actually starting a new stream of sequences */
+                        assert(storePos == storeEnd);   /* must be last sequence */
+                        ip = anchor + llen;     /* last "sequence" is a bunch of literals => don't progress anchor */
+                        continue;   /* will finish */
+                    }
+
+                    assert(anchor + llen <= iend);
+                    ZSTD_updateStats(optStatePtr, llen, anchor, offBase, mlen);
+                    ZSTD_storeSeq(seqStore, llen, anchor, iend, offBase, mlen);
+                    anchor += advance;
+                    ip = anchor;
+            }   }
+            DEBUGLOG(7, "new offset history : %u, %u, %u", rep[0], rep[1], rep[2]);
+
+            /* update all costs */
+            ZSTD_setBasePrices(optStatePtr, optLevel);
+        }
+    }   /* while (ip < ilimit) */
+
+    /* Return the last literals size */
+    return (size_t)(iend - anchor);
+}
+#endif /* build exclusions */
+
+#ifndef ZSTD_EXCLUDE_BTOPT_BLOCK_COMPRESSOR
+static size_t ZSTD_compressBlock_opt0(
+        ZSTD_MatchState_t* ms, SeqStore_t* seqStore, U32 rep[ZSTD_REP_NUM],
+        const void* src, size_t srcSize, const ZSTD_dictMode_e dictMode)
+{
+    return ZSTD_compressBlock_opt_generic(ms, seqStore, rep, src, srcSize, 0 /* optLevel */, dictMode);
+}
+#endif
+
+#ifndef ZSTD_EXCLUDE_BTULTRA_BLOCK_COMPRESSOR
+static size_t ZSTD_compressBlock_opt2(
+        ZSTD_MatchState_t* ms, SeqStore_t* seqStore, U32 rep[ZSTD_REP_NUM],
+        const void* src, size_t srcSize, const ZSTD_dictMode_e dictMode)
+{
+    return ZSTD_compressBlock_opt_generic(ms, seqStore, rep, src, srcSize, 2 /* optLevel */, dictMode);
+}
+#endif
+
+#ifndef ZSTD_EXCLUDE_BTOPT_BLOCK_COMPRESSOR
+size_t ZSTD_compressBlock_btopt(
+        ZSTD_MatchState_t* ms, SeqStore_t* seqStore, U32 rep[ZSTD_REP_NUM],
+        const void* src, size_t srcSize)
+{
+    DEBUGLOG(5, "ZSTD_compressBlock_btopt");
+    return ZSTD_compressBlock_opt0(ms, seqStore, rep, src, srcSize, ZSTD_noDict);
+}
+#endif
+
+
+
+
+#ifndef ZSTD_EXCLUDE_BTULTRA_BLOCK_COMPRESSOR
+/* ZSTD_initStats_ultra():
+ * make a first compression pass, just to seed stats with more accurate starting values.
+ * only works on first block, with no dictionary and no ldm.
+ * this function cannot error out, its narrow contract must be respected.
+ */
+static
+ZSTD_ALLOW_POINTER_OVERFLOW_ATTR
+void ZSTD_initStats_ultra(ZSTD_MatchState_t* ms,
+                          SeqStore_t* seqStore,
+                          U32 rep[ZSTD_REP_NUM],
+                    const void* src, size_t srcSize)
+{
+    U32 tmpRep[ZSTD_REP_NUM];  /* updated rep codes will sink here */
+    ZSTD_memcpy(tmpRep, rep, sizeof(tmpRep));
+
+    DEBUGLOG(4, "ZSTD_initStats_ultra (srcSize=%zu)", srcSize);
+    assert(ms->opt.litLengthSum == 0);    /* first block */
+    assert(seqStore->sequences == seqStore->sequencesStart);   /* no ldm */
+    assert(ms->window.dictLimit == ms->window.lowLimit);   /* no dictionary */
+    assert(ms->window.dictLimit - ms->nextToUpdate <= 1);  /* no prefix (note: intentional overflow, defined as 2-complement) */
+
+    ZSTD_compressBlock_opt2(ms, seqStore, tmpRep, src, srcSize, ZSTD_noDict);   /* generate stats into ms->opt*/
+
+    /* invalidate first scan from history, only keep entropy stats */
+    ZSTD_resetSeqStore(seqStore);
+    ms->window.base -= srcSize;
+    ms->window.dictLimit += (U32)srcSize;
+    ms->window.lowLimit = ms->window.dictLimit;
+    ms->nextToUpdate = ms->window.dictLimit;
+
+}
+
+size_t ZSTD_compressBlock_btultra(
+        ZSTD_MatchState_t* ms, SeqStore_t* seqStore, U32 rep[ZSTD_REP_NUM],
+        const void* src, size_t srcSize)
+{
+    DEBUGLOG(5, "ZSTD_compressBlock_btultra (srcSize=%zu)", srcSize);
+    return ZSTD_compressBlock_opt2(ms, seqStore, rep, src, srcSize, ZSTD_noDict);
+}
+
+size_t ZSTD_compressBlock_btultra2(
+        ZSTD_MatchState_t* ms, SeqStore_t* seqStore, U32 rep[ZSTD_REP_NUM],
+        const void* src, size_t srcSize)
+{
+    U32 const curr = (U32)((const BYTE*)src - ms->window.base);
+    DEBUGLOG(5, "ZSTD_compressBlock_btultra2 (srcSize=%zu)", srcSize);
+
+    /* 2-passes strategy:
+     * this strategy makes a first pass over first block to collect statistics
+     * in order to seed next round's statistics with it.
+     * After 1st pass, function forgets history, and starts a new block.
+     * Consequently, this can only work if no data has been previously loaded in tables,
+     * aka, no dictionary, no prefix, no ldm preprocessing.
+     * The compression ratio gain is generally small (~0.5% on first block),
+     * the cost is 2x cpu time on first block. */
+    assert(srcSize <= ZSTD_BLOCKSIZE_MAX);
+    if ( (ms->opt.litLengthSum==0)   /* first block */
+      && (seqStore->sequences == seqStore->sequencesStart)  /* no ldm */
+      && (ms->window.dictLimit == ms->window.lowLimit)   /* no dictionary */
+      && (curr == ms->window.dictLimit)    /* start of frame, nothing already loaded nor skipped */
+      && (srcSize > ZSTD_PREDEF_THRESHOLD) /* input large enough to not employ default stats */
+      ) {
+        ZSTD_initStats_ultra(ms, seqStore, rep, src, srcSize);
+    }
+
+    return ZSTD_compressBlock_opt2(ms, seqStore, rep, src, srcSize, ZSTD_noDict);
+}
+#endif
+
+#ifndef ZSTD_EXCLUDE_BTOPT_BLOCK_COMPRESSOR
+size_t ZSTD_compressBlock_btopt_dictMatchState(
+        ZSTD_MatchState_t* ms, SeqStore_t* seqStore, U32 rep[ZSTD_REP_NUM],
+        const void* src, size_t srcSize)
+{
+    return ZSTD_compressBlock_opt0(ms, seqStore, rep, src, srcSize, ZSTD_dictMatchState);
+}
+
+size_t ZSTD_compressBlock_btopt_extDict(
+        ZSTD_MatchState_t* ms, SeqStore_t* seqStore, U32 rep[ZSTD_REP_NUM],
+        const void* src, size_t srcSize)
+{
+    return ZSTD_compressBlock_opt0(ms, seqStore, rep, src, srcSize, ZSTD_extDict);
+}
+#endif
+
+#ifndef ZSTD_EXCLUDE_BTULTRA_BLOCK_COMPRESSOR
+size_t ZSTD_compressBlock_btultra_dictMatchState(
+        ZSTD_MatchState_t* ms, SeqStore_t* seqStore, U32 rep[ZSTD_REP_NUM],
+        const void* src, size_t srcSize)
+{
+    return ZSTD_compressBlock_opt2(ms, seqStore, rep, src, srcSize, ZSTD_dictMatchState);
+}
+
+size_t ZSTD_compressBlock_btultra_extDict(
+        ZSTD_MatchState_t* ms, SeqStore_t* seqStore, U32 rep[ZSTD_REP_NUM],
+        const void* src, size_t srcSize)
+{
+    return ZSTD_compressBlock_opt2(ms, seqStore, rep, src, srcSize, ZSTD_extDict);
+}
+#endif
+
+/* note : no btultra2 variant for extDict nor dictMatchState,
+ * because btultra2 is not meant to work with dictionaries
+ * and is only specific for the first block (no prefix) */
diff --git a/src/commonlib/bsd/zstd/compress/zstd_opt.h b/src/commonlib/bsd/zstd/compress/zstd_opt.h
new file mode 100644
index 0000000000..365c0a573e
--- /dev/null
+++ b/src/commonlib/bsd/zstd/compress/zstd_opt.h
@@ -0,0 +1,74 @@
+/* SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0-only */
+
+/*
+ * Copyright (c) Meta Platforms, Inc. and affiliates.
+ * All rights reserved.
+ *
+ * This source code is licensed under both the BSD-style license (found in the
+ * LICENSE file in the root directory of this source tree) and the GPLv2 (found
+ * in the COPYING file in the root directory of this source tree).
+ * You may select, at your option, one of the above-listed licenses.
+ */
+
+#ifndef ZSTD_OPT_H
+#define ZSTD_OPT_H
+
+#include "zstd_compress_internal.h"
+
+#if !defined(ZSTD_EXCLUDE_BTLAZY2_BLOCK_COMPRESSOR) \
+ || !defined(ZSTD_EXCLUDE_BTOPT_BLOCK_COMPRESSOR) \
+ || !defined(ZSTD_EXCLUDE_BTULTRA_BLOCK_COMPRESSOR)
+/* used in ZSTD_loadDictionaryContent() */
+void ZSTD_updateTree(ZSTD_MatchState_t* ms, const BYTE* ip, const BYTE* iend);
+#endif
+
+#ifndef ZSTD_EXCLUDE_BTOPT_BLOCK_COMPRESSOR
+size_t ZSTD_compressBlock_btopt(
+        ZSTD_MatchState_t* ms, SeqStore_t* seqStore, U32 rep[ZSTD_REP_NUM],
+        void const* src, size_t srcSize);
+size_t ZSTD_compressBlock_btopt_dictMatchState(
+        ZSTD_MatchState_t* ms, SeqStore_t* seqStore, U32 rep[ZSTD_REP_NUM],
+        void const* src, size_t srcSize);
+size_t ZSTD_compressBlock_btopt_extDict(
+        ZSTD_MatchState_t* ms, SeqStore_t* seqStore, U32 rep[ZSTD_REP_NUM],
+        void const* src, size_t srcSize);
+
+#define ZSTD_COMPRESSBLOCK_BTOPT ZSTD_compressBlock_btopt
+#define ZSTD_COMPRESSBLOCK_BTOPT_DICTMATCHSTATE ZSTD_compressBlock_btopt_dictMatchState
+#define ZSTD_COMPRESSBLOCK_BTOPT_EXTDICT ZSTD_compressBlock_btopt_extDict
+#else
+#define ZSTD_COMPRESSBLOCK_BTOPT NULL
+#define ZSTD_COMPRESSBLOCK_BTOPT_DICTMATCHSTATE NULL
+#define ZSTD_COMPRESSBLOCK_BTOPT_EXTDICT NULL
+#endif
+
+#ifndef ZSTD_EXCLUDE_BTULTRA_BLOCK_COMPRESSOR
+size_t ZSTD_compressBlock_btultra(
+        ZSTD_MatchState_t* ms, SeqStore_t* seqStore, U32 rep[ZSTD_REP_NUM],
+        void const* src, size_t srcSize);
+size_t ZSTD_compressBlock_btultra_dictMatchState(
+        ZSTD_MatchState_t* ms, SeqStore_t* seqStore, U32 rep[ZSTD_REP_NUM],
+        void const* src, size_t srcSize);
+size_t ZSTD_compressBlock_btultra_extDict(
+        ZSTD_MatchState_t* ms, SeqStore_t* seqStore, U32 rep[ZSTD_REP_NUM],
+        void const* src, size_t srcSize);
+
+        /* note : no btultra2 variant for extDict nor dictMatchState,
+         * because btultra2 is not meant to work with dictionaries
+         * and is only specific for the first block (no prefix) */
+size_t ZSTD_compressBlock_btultra2(
+        ZSTD_MatchState_t* ms, SeqStore_t* seqStore, U32 rep[ZSTD_REP_NUM],
+        void const* src, size_t srcSize);
+
+#define ZSTD_COMPRESSBLOCK_BTULTRA ZSTD_compressBlock_btultra
+#define ZSTD_COMPRESSBLOCK_BTULTRA_DICTMATCHSTATE ZSTD_compressBlock_btultra_dictMatchState
+#define ZSTD_COMPRESSBLOCK_BTULTRA_EXTDICT ZSTD_compressBlock_btultra_extDict
+#define ZSTD_COMPRESSBLOCK_BTULTRA2 ZSTD_compressBlock_btultra2
+#else
+#define ZSTD_COMPRESSBLOCK_BTULTRA NULL
+#define ZSTD_COMPRESSBLOCK_BTULTRA_DICTMATCHSTATE NULL
+#define ZSTD_COMPRESSBLOCK_BTULTRA_EXTDICT NULL
+#define ZSTD_COMPRESSBLOCK_BTULTRA2 NULL
+#endif
+
+#endif /* ZSTD_OPT_H */
diff --git a/src/commonlib/bsd/zstd/compress/zstd_preSplit.c b/src/commonlib/bsd/zstd/compress/zstd_preSplit.c
new file mode 100644
index 0000000000..b4a2a738e5
--- /dev/null
+++ b/src/commonlib/bsd/zstd/compress/zstd_preSplit.c
@@ -0,0 +1,239 @@
+/* SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0-only */
+/*
+ * Copyright (c) Meta Platforms, Inc. and affiliates.
+ * All rights reserved.
+ *
+ * This source code is licensed under both the BSD-style license (found in the
+ * LICENSE file in the root directory of this source tree) and the GPLv2 (found
+ * in the COPYING file in the root directory of this source tree).
+ * You may select, at your option, one of the above-listed licenses.
+ */
+
+#include "../common/zstd_compiler.h" /* ZSTD_ALIGNOF */
+#include "../common/mem.h" /* S64 */
+#include "../common/zstd_deps.h" /* ZSTD_memset */
+#include "../common/zstd_internal.h" /* ZSTD_STATIC_ASSERT */
+#include "hist.h" /* HIST_add */
+#include "zstd_preSplit.h"
+
+
+#define BLOCKSIZE_MIN 3500
+#define THRESHOLD_PENALTY_RATE 16
+#define THRESHOLD_BASE (THRESHOLD_PENALTY_RATE - 2)
+#define THRESHOLD_PENALTY 3
+
+#define HASHLENGTH 2
+#define HASHLOG_MAX 10
+#define HASHTABLESIZE (1 << HASHLOG_MAX)
+#define HASHMASK (HASHTABLESIZE - 1)
+#define KNUTH 0x9e3779b9
+
+/* for hashLog > 8, hash 2 bytes.
+ * for hashLog == 8, just take the byte, no hashing.
+ * The speed of this method relies on compile-time constant propagation */
+FORCE_INLINE_TEMPLATE unsigned hash2(const void *p, unsigned hashLog)
+{
+    assert(hashLog >= 8);
+    if (hashLog == 8) return (U32)((const BYTE*)p)[0];
+    assert(hashLog <= HASHLOG_MAX);
+    return (U32)(MEM_read16(p)) * KNUTH >> (32 - hashLog);
+}
+
+
+typedef struct {
+  unsigned events[HASHTABLESIZE];
+  size_t nbEvents;
+} Fingerprint;
+typedef struct {
+    Fingerprint pastEvents;
+    Fingerprint newEvents;
+} FPStats;
+
+static void initStats(FPStats* fpstats)
+{
+    ZSTD_memset(fpstats, 0, sizeof(FPStats));
+}
+
+FORCE_INLINE_TEMPLATE void
+addEvents_generic(Fingerprint* fp, const void* src, size_t srcSize, size_t samplingRate, unsigned hashLog)
+{
+    const char* p = (const char*)src;
+    size_t limit = srcSize - HASHLENGTH + 1;
+    size_t n;
+    assert(srcSize >= HASHLENGTH);
+    for (n = 0; n < limit; n+=samplingRate) {
+        fp->events[hash2(p+n, hashLog)]++;
+    }
+    fp->nbEvents += limit/samplingRate;
+}
+
+FORCE_INLINE_TEMPLATE void
+recordFingerprint_generic(Fingerprint* fp, const void* src, size_t srcSize, size_t samplingRate, unsigned hashLog)
+{
+    ZSTD_memset(fp, 0, sizeof(unsigned) * ((size_t)1 << hashLog));
+    fp->nbEvents = 0;
+    addEvents_generic(fp, src, srcSize, samplingRate, hashLog);
+}
+
+typedef void (*RecordEvents_f)(Fingerprint* fp, const void* src, size_t srcSize);
+
+#define FP_RECORD(_rate) ZSTD_recordFingerprint_##_rate
+
+#define ZSTD_GEN_RECORD_FINGERPRINT(_rate, _hSize)                                 \
+    static void FP_RECORD(_rate)(Fingerprint* fp, const void* src, size_t srcSize) \
+    {                                                                              \
+        recordFingerprint_generic(fp, src, srcSize, _rate, _hSize);                \
+    }
+
+ZSTD_GEN_RECORD_FINGERPRINT(1, 10)
+ZSTD_GEN_RECORD_FINGERPRINT(5, 10)
+ZSTD_GEN_RECORD_FINGERPRINT(11, 9)
+ZSTD_GEN_RECORD_FINGERPRINT(43, 8)
+
+
+static U64 abs64(S64 s64) { return (U64)((s64 < 0) ? -s64 : s64); }
+
+static U64 fpDistance(const Fingerprint* fp1, const Fingerprint* fp2, unsigned hashLog)
+{
+    U64 distance = 0;
+    size_t n;
+    assert(hashLog <= HASHLOG_MAX);
+    for (n = 0; n < ((size_t)1 << hashLog); n++) {
+        distance +=
+            abs64((S64)fp1->events[n] * (S64)fp2->nbEvents - (S64)fp2->events[n] * (S64)fp1->nbEvents);
+    }
+    return distance;
+}
+
+/* Compare newEvents with pastEvents
+ * return 1 when considered "too different"
+ */
+static int compareFingerprints(const Fingerprint* ref,
+                            const Fingerprint* newfp,
+                            int penalty,
+                            unsigned hashLog)
+{
+    assert(ref->nbEvents > 0);
+    assert(newfp->nbEvents > 0);
+    {   U64 p50 = (U64)ref->nbEvents * (U64)newfp->nbEvents;
+        U64 deviation = fpDistance(ref, newfp, hashLog);
+        U64 threshold = p50 * (U64)(THRESHOLD_BASE + penalty) / THRESHOLD_PENALTY_RATE;
+        return deviation >= threshold;
+    }
+}
+
+static void mergeEvents(Fingerprint* acc, const Fingerprint* newfp)
+{
+    size_t n;
+    for (n = 0; n < HASHTABLESIZE; n++) {
+        acc->events[n] += newfp->events[n];
+    }
+    acc->nbEvents += newfp->nbEvents;
+}
+
+static void flushEvents(FPStats* fpstats)
+{
+    size_t n;
+    for (n = 0; n < HASHTABLESIZE; n++) {
+        fpstats->pastEvents.events[n] = fpstats->newEvents.events[n];
+    }
+    fpstats->pastEvents.nbEvents = fpstats->newEvents.nbEvents;
+    ZSTD_memset(&fpstats->newEvents, 0, sizeof(fpstats->newEvents));
+}
+
+static void removeEvents(Fingerprint* acc, const Fingerprint* slice)
+{
+    size_t n;
+    for (n = 0; n < HASHTABLESIZE; n++) {
+        assert(acc->events[n] >= slice->events[n]);
+        acc->events[n] -= slice->events[n];
+    }
+    acc->nbEvents -= slice->nbEvents;
+}
+
+#define CHUNKSIZE (8 << 10)
+static size_t ZSTD_splitBlock_byChunks(const void* blockStart, size_t blockSize,
+                        int level,
+                        void* workspace, size_t wkspSize)
+{
+    static const RecordEvents_f records_fs[] = {
+        FP_RECORD(43), FP_RECORD(11), FP_RECORD(5), FP_RECORD(1)
+    };
+    static const unsigned hashParams[] = { 8, 9, 10, 10 };
+    const RecordEvents_f record_f = (assert(0<=level && level<=3), records_fs[level]);
+    FPStats* const fpstats = (FPStats*)workspace;
+    const char* p = (const char*)blockStart;
+    int penalty = THRESHOLD_PENALTY;
+    size_t pos = 0;
+    assert(blockSize == (128 << 10));
+    assert(workspace != NULL);
+    assert((size_t)workspace % ZSTD_ALIGNOF(FPStats) == 0);
+    ZSTD_STATIC_ASSERT(ZSTD_SLIPBLOCK_WORKSPACESIZE >= sizeof(FPStats));
+    assert(wkspSize >= sizeof(FPStats)); (void)wkspSize;
+
+    initStats(fpstats);
+    record_f(&fpstats->pastEvents, p, CHUNKSIZE);
+    for (pos = CHUNKSIZE; pos <= blockSize - CHUNKSIZE; pos += CHUNKSIZE) {
+        record_f(&fpstats->newEvents, p + pos, CHUNKSIZE);
+        if (compareFingerprints(&fpstats->pastEvents, &fpstats->newEvents, penalty, hashParams[level])) {
+            return pos;
+        } else {
+            mergeEvents(&fpstats->pastEvents, &fpstats->newEvents);
+            if (penalty > 0) penalty--;
+        }
+    }
+    assert(pos == blockSize);
+    return blockSize;
+    (void)flushEvents; (void)removeEvents;
+}
+
+/* ZSTD_splitBlock_fromBorders(): very fast strategy :
+ * compare fingerprint from beginning and end of the block,
+ * derive from their difference if it's preferable to split in the middle,
+ * repeat the process a second time, for finer grained decision.
+ * 3 times did not brought improvements, so I stopped at 2.
+ * Benefits are good enough for a cheap heuristic.
+ * More accurate splitting saves more, but speed impact is also more perceptible.
+ * For better accuracy, use more elaborate variant *_byChunks.
+ */
+static size_t ZSTD_splitBlock_fromBorders(const void* blockStart, size_t blockSize,
+                        void* workspace, size_t wkspSize)
+{
+#define SEGMENT_SIZE 512
+    FPStats* const fpstats = (FPStats*)workspace;
+    Fingerprint* middleEvents = (Fingerprint*)(void*)((char*)workspace + 512 * sizeof(unsigned));
+    assert(blockSize == (128 << 10));
+    assert(workspace != NULL);
+    assert((size_t)workspace % ZSTD_ALIGNOF(FPStats) == 0);
+    ZSTD_STATIC_ASSERT(ZSTD_SLIPBLOCK_WORKSPACESIZE >= sizeof(FPStats));
+    assert(wkspSize >= sizeof(FPStats)); (void)wkspSize;
+
+    initStats(fpstats);
+    HIST_add(fpstats->pastEvents.events, blockStart, SEGMENT_SIZE);
+    HIST_add(fpstats->newEvents.events, (const char*)blockStart + blockSize - SEGMENT_SIZE, SEGMENT_SIZE);
+    fpstats->pastEvents.nbEvents = fpstats->newEvents.nbEvents = SEGMENT_SIZE;
+    if (!compareFingerprints(&fpstats->pastEvents, &fpstats->newEvents, 0, 8))
+        return blockSize;
+
+    HIST_add(middleEvents->events, (const char*)blockStart + blockSize/2 - SEGMENT_SIZE/2, SEGMENT_SIZE);
+    middleEvents->nbEvents = SEGMENT_SIZE;
+    {   U64 const distFromBegin = fpDistance(&fpstats->pastEvents, middleEvents, 8);
+        U64 const distFromEnd = fpDistance(&fpstats->newEvents, middleEvents, 8);
+        U64 const minDistance = SEGMENT_SIZE * SEGMENT_SIZE / 3;
+        if (abs64((S64)distFromBegin - (S64)distFromEnd) < minDistance)
+            return 64 KB;
+        return (distFromBegin > distFromEnd) ? 32 KB : 96 KB;
+    }
+}
+
+size_t ZSTD_splitBlock(const void* blockStart, size_t blockSize,
+                    int level,
+                    void* workspace, size_t wkspSize)
+{
+    DEBUGLOG(6, "ZSTD_splitBlock (level=%i)", level);
+    assert(0<=level && level<=4);
+    if (level == 0)
+        return ZSTD_splitBlock_fromBorders(blockStart, blockSize, workspace, wkspSize);
+    /* level >= 1*/
+    return ZSTD_splitBlock_byChunks(blockStart, blockSize, level-1, workspace, wkspSize);
+}
diff --git a/src/commonlib/bsd/zstd/compress/zstd_preSplit.h b/src/commonlib/bsd/zstd/compress/zstd_preSplit.h
new file mode 100644
index 0000000000..3adda529fa
--- /dev/null
+++ b/src/commonlib/bsd/zstd/compress/zstd_preSplit.h
@@ -0,0 +1,34 @@
+/* SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0-only */
+/*
+ * Copyright (c) Meta Platforms, Inc. and affiliates.
+ * All rights reserved.
+ *
+ * This source code is licensed under both the BSD-style license (found in the
+ * LICENSE file in the root directory of this source tree) and the GPLv2 (found
+ * in the COPYING file in the root directory of this source tree).
+ * You may select, at your option, one of the above-listed licenses.
+ */
+
+#ifndef ZSTD_PRESPLIT_H
+#define ZSTD_PRESPLIT_H
+
+#include <stddef.h>  /* size_t */
+
+#define ZSTD_SLIPBLOCK_WORKSPACESIZE 8208
+
+/* ZSTD_splitBlock():
+ * @level must be a value between 0 and 4.
+ *        higher levels spend more energy to detect block boundaries.
+ * @workspace must be aligned for size_t.
+ * @wkspSize must be at least >= ZSTD_SLIPBLOCK_WORKSPACESIZE
+ * note:
+ * For the time being, this function only accepts full 128 KB blocks.
+ * Therefore, @blockSize must be == 128 KB.
+ * While this could be extended to smaller sizes in the future,
+ * it is not yet clear if this would be useful. TBD.
+ */
+size_t ZSTD_splitBlock(const void* blockStart, size_t blockSize,
+                    int level,
+                    void* workspace, size_t wkspSize);
+
+#endif /* ZSTD_PRESPLIT_H */
diff --git a/src/commonlib/bsd/zstd/decompress/huf_decompress.c b/src/commonlib/bsd/zstd/decompress/huf_decompress.c
new file mode 100644
index 0000000000..2248ba8deb
--- /dev/null
+++ b/src/commonlib/bsd/zstd/decompress/huf_decompress.c
@@ -0,0 +1,1946 @@
+/* SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0-only */
+
+/* ******************************************************************
+ * huff0 huffman decoder,
+ * part of Finite State Entropy library
+ * Copyright (c) Meta Platforms, Inc. and affiliates.
+ *
+ *  You can contact the author at :
+ *  - FSE+HUF source repository : https://github.com/Cyan4973/FiniteStateEntropy
+ *
+ * This source code is licensed under both the BSD-style license (found in the
+ * LICENSE file in the root directory of this source tree) and the GPLv2 (found
+ * in the COPYING file in the root directory of this source tree).
+ * You may select, at your option, one of the above-listed licenses.
+****************************************************************** */
+
+/* **************************************************************
+*  Dependencies
+****************************************************************/
+#include "../common/zstd_deps.h"  /* ZSTD_memcpy, ZSTD_memset */
+#include "../common/zstd_compiler.h"
+#include "../common/bitstream.h"  /* BIT_* */
+#include "../common/fse.h"        /* to compress headers */
+#include "../common/huf.h"
+#include "../common/error_private.h"
+#include "../common/zstd_internal.h"
+#include "../common/zstd_bits.h"       /* ZSTD_highbit32, ZSTD_countTrailingZeros64 */
+
+/* **************************************************************
+*  Constants
+****************************************************************/
+
+#define HUF_DECODER_FAST_TABLELOG 11
+
+/* **************************************************************
+*  Macros
+****************************************************************/
+
+#ifdef HUF_DISABLE_FAST_DECODE
+# define HUF_ENABLE_FAST_DECODE 0
+#else
+# define HUF_ENABLE_FAST_DECODE 1
+#endif
+
+/* These two optional macros force the use one way or another of the two
+ * Huffman decompression implementations. You can't force in both directions
+ * at the same time.
+ */
+#if defined(HUF_FORCE_DECOMPRESS_X1) && \
+    defined(HUF_FORCE_DECOMPRESS_X2)
+#error "Cannot force the use of the X1 and X2 decoders at the same time!"
+#endif
+
+/* When DYNAMIC_BMI2 is enabled, fast decoders are only called when bmi2 is
+ * supported at runtime, so we can add the BMI2 target attribute.
+ * When it is disabled, we will still get BMI2 if it is enabled statically.
+ */
+#if DYNAMIC_BMI2
+# define HUF_FAST_BMI2_ATTRS BMI2_TARGET_ATTRIBUTE
+#else
+# define HUF_FAST_BMI2_ATTRS
+#endif
+
+#ifdef __cplusplus
+# define HUF_EXTERN_C extern "C"
+#else
+# define HUF_EXTERN_C
+#endif
+#define HUF_ASM_DECL HUF_EXTERN_C
+
+#if DYNAMIC_BMI2
+# define HUF_NEED_BMI2_FUNCTION 1
+#else
+# define HUF_NEED_BMI2_FUNCTION 0
+#endif
+
+/* **************************************************************
+*  Error Management
+****************************************************************/
+#define HUF_isError ERR_isError
+
+
+/* **************************************************************
+*  Byte alignment for workSpace management
+****************************************************************/
+#define HUF_ALIGN(x, a)         HUF_ALIGN_MASK((x), (a) - 1)
+#define HUF_ALIGN_MASK(x, mask) (((x) + (mask)) & ~(mask))
+
+
+/* **************************************************************
+*  BMI2 Variant Wrappers
+****************************************************************/
+typedef size_t (*HUF_DecompressUsingDTableFn)(void *dst, size_t dstSize,
+                                              const void *cSrc,
+                                              size_t cSrcSize,
+                                              const HUF_DTable *DTable);
+
+#if DYNAMIC_BMI2
+
+#define HUF_DGEN(fn)                                                        \
+                                                                            \
+    static size_t fn##_default(                                             \
+                  void* dst,  size_t dstSize,                               \
+            const void* cSrc, size_t cSrcSize,                              \
+            const HUF_DTable* DTable)                                       \
+    {                                                                       \
+        return fn##_body(dst, dstSize, cSrc, cSrcSize, DTable);             \
+    }                                                                       \
+                                                                            \
+    static BMI2_TARGET_ATTRIBUTE size_t fn##_bmi2(                          \
+                  void* dst,  size_t dstSize,                               \
+            const void* cSrc, size_t cSrcSize,                              \
+            const HUF_DTable* DTable)                                       \
+    {                                                                       \
+        return fn##_body(dst, dstSize, cSrc, cSrcSize, DTable);             \
+    }                                                                       \
+                                                                            \
+    static size_t fn(void* dst, size_t dstSize, void const* cSrc,           \
+                     size_t cSrcSize, HUF_DTable const* DTable, int flags)  \
+    {                                                                       \
+        if (flags & HUF_flags_bmi2) {                                       \
+            return fn##_bmi2(dst, dstSize, cSrc, cSrcSize, DTable);         \
+        }                                                                   \
+        return fn##_default(dst, dstSize, cSrc, cSrcSize, DTable);          \
+    }
+
+#else
+
+#define HUF_DGEN(fn)                                                        \
+    static size_t fn(void* dst, size_t dstSize, void const* cSrc,           \
+                     size_t cSrcSize, HUF_DTable const* DTable, int flags)  \
+    {                                                                       \
+        (void)flags;                                                        \
+        return fn##_body(dst, dstSize, cSrc, cSrcSize, DTable);             \
+    }
+
+#endif
+
+
+/*-***************************/
+/*  generic DTableDesc       */
+/*-***************************/
+typedef struct { BYTE maxTableLog; BYTE tableType; BYTE tableLog; BYTE reserved; } DTableDesc;
+
+static DTableDesc HUF_getDTableDesc(const HUF_DTable* table)
+{
+    DTableDesc dtd;
+    ZSTD_memcpy(&dtd, table, sizeof(dtd));
+    return dtd;
+}
+
+static size_t HUF_initFastDStream(BYTE const* ip) {
+    BYTE const lastByte = ip[7];
+    size_t const bitsConsumed = lastByte ? 8 - ZSTD_highbit32(lastByte) : 0;
+    size_t const value = MEM_readLEST(ip) | 1;
+    assert(bitsConsumed <= 8);
+    assert(sizeof(size_t) == 8);
+    return value << bitsConsumed;
+}
+
+
+/**
+ * The input/output arguments to the Huffman fast decoding loop:
+ *
+ * ip [in/out] - The input pointers, must be updated to reflect what is consumed.
+ * op [in/out] - The output pointers, must be updated to reflect what is written.
+ * bits [in/out] - The bitstream containers, must be updated to reflect the current state.
+ * dt [in] - The decoding table.
+ * ilowest [in] - The beginning of the valid range of the input. Decoders may read
+ *                down to this pointer. It may be below iend[0].
+ * oend [in] - The end of the output stream. op[3] must not cross oend.
+ * iend [in] - The end of each input stream. ip[i] may cross iend[i],
+ *             as long as it is above ilowest, but that indicates corruption.
+ */
+typedef struct {
+    BYTE const* ip[4];
+    BYTE* op[4];
+    U64 bits[4];
+    void const* dt;
+    BYTE const* ilowest;
+    BYTE* oend;
+    BYTE const* iend[4];
+} HUF_DecompressFastArgs;
+
+typedef void (*HUF_DecompressFastLoopFn)(HUF_DecompressFastArgs*);
+
+/**
+ * Initializes args for the fast decoding loop.
+ * @returns 1 on success
+ *          0 if the fallback implementation should be used.
+ *          Or an error code on failure.
+ */
+static size_t HUF_DecompressFastArgs_init(HUF_DecompressFastArgs* args, void* dst, size_t dstSize, void const* src, size_t srcSize, const HUF_DTable* DTable)
+{
+    void const* dt = DTable + 1;
+    U32 const dtLog = HUF_getDTableDesc(DTable).tableLog;
+
+    const BYTE* const istart = (const BYTE*)src;
+
+    BYTE* const oend = ZSTD_maybeNullPtrAdd((BYTE*)dst, dstSize);
+
+    /* The fast decoding loop assumes 64-bit little-endian.
+     * This condition is false on x32.
+     */
+    if (!MEM_isLittleEndian() || MEM_32bits())
+        return 0;
+
+    /* Avoid nullptr addition */
+    if (dstSize == 0)
+        return 0;
+    assert(dst != NULL);
+
+    /* strict minimum : jump table + 1 byte per stream */
+    if (srcSize < 10)
+        return ERROR(corruption_detected);
+
+    /* Must have at least 8 bytes per stream because we don't handle initializing smaller bit containers.
+     * If table log is not correct at this point, fallback to the old decoder.
+     * On small inputs we don't have enough data to trigger the fast loop, so use the old decoder.
+     */
+    if (dtLog != HUF_DECODER_FAST_TABLELOG)
+        return 0;
+
+    /* Read the jump table. */
+    {
+        size_t const length1 = MEM_readLE16(istart);
+        size_t const length2 = MEM_readLE16(istart+2);
+        size_t const length3 = MEM_readLE16(istart+4);
+        size_t const length4 = srcSize - (length1 + length2 + length3 + 6);
+        args->iend[0] = istart + 6;  /* jumpTable */
+        args->iend[1] = args->iend[0] + length1;
+        args->iend[2] = args->iend[1] + length2;
+        args->iend[3] = args->iend[2] + length3;
+
+        /* HUF_initFastDStream() requires this, and this small of an input
+         * won't benefit from the ASM loop anyways.
+         */
+        if (length1 < 8 || length2 < 8 || length3 < 8 || length4 < 8)
+            return 0;
+        if (length4 > srcSize) return ERROR(corruption_detected);   /* overflow */
+    }
+    /* ip[] contains the position that is currently loaded into bits[]. */
+    args->ip[0] = args->iend[1] - sizeof(U64);
+    args->ip[1] = args->iend[2] - sizeof(U64);
+    args->ip[2] = args->iend[3] - sizeof(U64);
+    args->ip[3] = (BYTE const*)src + srcSize - sizeof(U64);
+
+    /* op[] contains the output pointers. */
+    args->op[0] = (BYTE*)dst;
+    args->op[1] = args->op[0] + (dstSize+3)/4;
+    args->op[2] = args->op[1] + (dstSize+3)/4;
+    args->op[3] = args->op[2] + (dstSize+3)/4;
+
+    /* No point to call the ASM loop for tiny outputs. */
+    if (args->op[3] >= oend)
+        return 0;
+
+    /* bits[] is the bit container.
+        * It is read from the MSB down to the LSB.
+        * It is shifted left as it is read, and zeros are
+        * shifted in. After the lowest valid bit a 1 is
+        * set, so that CountTrailingZeros(bits[]) can be used
+        * to count how many bits we've consumed.
+        */
+    args->bits[0] = HUF_initFastDStream(args->ip[0]);
+    args->bits[1] = HUF_initFastDStream(args->ip[1]);
+    args->bits[2] = HUF_initFastDStream(args->ip[2]);
+    args->bits[3] = HUF_initFastDStream(args->ip[3]);
+
+    /* The decoders must be sure to never read beyond ilowest.
+     * This is lower than iend[0], but allowing decoders to read
+     * down to ilowest can allow an extra iteration or two in the
+     * fast loop.
+     */
+    args->ilowest = istart;
+
+    args->oend = oend;
+    args->dt = dt;
+
+    return 1;
+}
+
+static size_t HUF_initRemainingDStream(BIT_DStream_t* bit, HUF_DecompressFastArgs const* args, int stream, BYTE* segmentEnd)
+{
+    /* Validate that we haven't overwritten. */
+    if (args->op[stream] > segmentEnd)
+        return ERROR(corruption_detected);
+    /* Validate that we haven't read beyond iend[].
+        * Note that ip[] may be < iend[] because the MSB is
+        * the next bit to read, and we may have consumed 100%
+        * of the stream, so down to iend[i] - 8 is valid.
+        */
+    if (args->ip[stream] < args->iend[stream] - 8)
+        return ERROR(corruption_detected);
+
+    /* Construct the BIT_DStream_t. */
+    assert(sizeof(size_t) == 8);
+    bit->bitContainer = MEM_readLEST(args->ip[stream]);
+    bit->bitsConsumed = ZSTD_countTrailingZeros64(args->bits[stream]);
+    bit->start = (const char*)args->ilowest;
+    bit->limitPtr = bit->start + sizeof(size_t);
+    bit->ptr = (const char*)args->ip[stream];
+
+    return 0;
+}
+
+/* Calls X(N) for each stream 0, 1, 2, 3. */
+#define HUF_4X_FOR_EACH_STREAM(X) \
+    do {                          \
+        X(0);                     \
+        X(1);                     \
+        X(2);                     \
+        X(3);                     \
+    } while (0)
+
+/* Calls X(N, var) for each stream 0, 1, 2, 3. */
+#define HUF_4X_FOR_EACH_STREAM_WITH_VAR(X, var) \
+    do {                                        \
+        X(0, (var));                            \
+        X(1, (var));                            \
+        X(2, (var));                            \
+        X(3, (var));                            \
+    } while (0)
+
+
+#ifndef HUF_FORCE_DECOMPRESS_X2
+
+/*-***************************/
+/*  single-symbol decoding   */
+/*-***************************/
+typedef struct { BYTE nbBits; BYTE byte; } HUF_DEltX1;   /* single-symbol decoding */
+
+/**
+ * Packs 4 HUF_DEltX1 structs into a U64. This is used to lay down 4 entries at
+ * a time.
+ */
+static U64 HUF_DEltX1_set4(BYTE symbol, BYTE nbBits) {
+    U64 D4;
+    if (MEM_isLittleEndian()) {
+        D4 = (U64)((symbol << 8) + nbBits);
+    } else {
+        D4 = (U64)(symbol + (nbBits << 8));
+    }
+    assert(D4 < (1U << 16));
+    D4 *= 0x0001000100010001ULL;
+    return D4;
+}
+
+/**
+ * Increase the tableLog to targetTableLog and rescales the stats.
+ * If tableLog > targetTableLog this is a no-op.
+ * @returns New tableLog
+ */
+static U32 HUF_rescaleStats(BYTE* huffWeight, U32* rankVal, U32 nbSymbols, U32 tableLog, U32 targetTableLog)
+{
+    if (tableLog > targetTableLog)
+        return tableLog;
+    if (tableLog < targetTableLog) {
+        U32 const scale = targetTableLog - tableLog;
+        U32 s;
+        /* Increase the weight for all non-zero probability symbols by scale. */
+        for (s = 0; s < nbSymbols; ++s) {
+            huffWeight[s] += (BYTE)((huffWeight[s] == 0) ? 0 : scale);
+        }
+        /* Update rankVal to reflect the new weights.
+         * All weights except 0 get moved to weight + scale.
+         * Weights [1, scale] are empty.
+         */
+        for (s = targetTableLog; s > scale; --s) {
+            rankVal[s] = rankVal[s - scale];
+        }
+        for (s = scale; s > 0; --s) {
+            rankVal[s] = 0;
+        }
+    }
+    return targetTableLog;
+}
+
+typedef struct {
+        U32 rankVal[HUF_TABLELOG_ABSOLUTEMAX + 1];
+        U32 rankStart[HUF_TABLELOG_ABSOLUTEMAX + 1];
+        U32 statsWksp[HUF_READ_STATS_WORKSPACE_SIZE_U32];
+        BYTE symbols[HUF_SYMBOLVALUE_MAX + 1];
+        BYTE huffWeight[HUF_SYMBOLVALUE_MAX + 1];
+} HUF_ReadDTableX1_Workspace;
+
+size_t HUF_readDTableX1_wksp(HUF_DTable* DTable, const void* src, size_t srcSize, void* workSpace, size_t wkspSize, int flags)
+{
+    U32 tableLog = 0;
+    U32 nbSymbols = 0;
+    size_t iSize;
+    void* const dtPtr = DTable + 1;
+    HUF_DEltX1* const dt = (HUF_DEltX1*)dtPtr;
+    HUF_ReadDTableX1_Workspace* wksp = (HUF_ReadDTableX1_Workspace*)workSpace;
+
+    DEBUG_STATIC_ASSERT(HUF_DECOMPRESS_WORKSPACE_SIZE >= sizeof(*wksp));
+    if (sizeof(*wksp) > wkspSize) return ERROR(tableLog_tooLarge);
+
+    DEBUG_STATIC_ASSERT(sizeof(DTableDesc) == sizeof(HUF_DTable));
+    /* ZSTD_memset(huffWeight, 0, sizeof(huffWeight)); */   /* is not necessary, even though some analyzer complain ... */
+
+    iSize = HUF_readStats_wksp(wksp->huffWeight, HUF_SYMBOLVALUE_MAX + 1, wksp->rankVal, &nbSymbols, &tableLog, src, srcSize, wksp->statsWksp, sizeof(wksp->statsWksp), flags);
+    if (HUF_isError(iSize)) return iSize;
+
+
+    /* Table header */
+    {   DTableDesc dtd = HUF_getDTableDesc(DTable);
+        U32 const maxTableLog = dtd.maxTableLog + 1;
+        U32 const targetTableLog = MIN(maxTableLog, HUF_DECODER_FAST_TABLELOG);
+        tableLog = HUF_rescaleStats(wksp->huffWeight, wksp->rankVal, nbSymbols, tableLog, targetTableLog);
+        if (tableLog > (U32)(dtd.maxTableLog+1)) return ERROR(tableLog_tooLarge);   /* DTable too small, Huffman tree cannot fit in */
+        dtd.tableType = 0;
+        dtd.tableLog = (BYTE)tableLog;
+        ZSTD_memcpy(DTable, &dtd, sizeof(dtd));
+    }
+
+    /* Compute symbols and rankStart given rankVal:
+     *
+     * rankVal already contains the number of values of each weight.
+     *
+     * symbols contains the symbols ordered by weight. First are the rankVal[0]
+     * weight 0 symbols, followed by the rankVal[1] weight 1 symbols, and so on.
+     * symbols[0] is filled (but unused) to avoid a branch.
+     *
+     * rankStart contains the offset where each rank belongs in the DTable.
+     * rankStart[0] is not filled because there are no entries in the table for
+     * weight 0.
+     */
+    {   int n;
+        U32 nextRankStart = 0;
+        int const unroll = 4;
+        int const nLimit = (int)nbSymbols - unroll + 1;
+        for (n=0; n<(int)tableLog+1; n++) {
+            U32 const curr = nextRankStart;
+            nextRankStart += wksp->rankVal[n];
+            wksp->rankStart[n] = curr;
+        }
+        for (n=0; n < nLimit; n += unroll) {
+            int u;
+            for (u=0; u < unroll; ++u) {
+                size_t const w = wksp->huffWeight[n+u];
+                wksp->symbols[wksp->rankStart[w]++] = (BYTE)(n+u);
+            }
+        }
+        for (; n < (int)nbSymbols; ++n) {
+            size_t const w = wksp->huffWeight[n];
+            wksp->symbols[wksp->rankStart[w]++] = (BYTE)n;
+        }
+    }
+
+    /* fill DTable
+     * We fill all entries of each weight in order.
+     * That way length is a constant for each iteration of the outer loop.
+     * We can switch based on the length to a different inner loop which is
+     * optimized for that particular case.
+     */
+    {   U32 w;
+        int symbol = wksp->rankVal[0];
+        int rankStart = 0;
+        for (w=1; w<tableLog+1; ++w) {
+            int const symbolCount = wksp->rankVal[w];
+            int const length = (1 << w) >> 1;
+            int uStart = rankStart;
+            BYTE const nbBits = (BYTE)(tableLog + 1 - w);
+            int s;
+            int u;
+            switch (length) {
+            case 1:
+                for (s=0; s<symbolCount; ++s) {
+                    HUF_DEltX1 D;
+                    D.byte = wksp->symbols[symbol + s];
+                    D.nbBits = nbBits;
+                    dt[uStart] = D;
+                    uStart += 1;
+                }
+                break;
+            case 2:
+                for (s=0; s<symbolCount; ++s) {
+                    HUF_DEltX1 D;
+                    D.byte = wksp->symbols[symbol + s];
+                    D.nbBits = nbBits;
+                    dt[uStart+0] = D;
+                    dt[uStart+1] = D;
+                    uStart += 2;
+                }
+                break;
+            case 4:
+                for (s=0; s<symbolCount; ++s) {
+                    U64 const D4 = HUF_DEltX1_set4(wksp->symbols[symbol + s], nbBits);
+                    MEM_write64(dt + uStart, D4);
+                    uStart += 4;
+                }
+                break;
+            case 8:
+                for (s=0; s<symbolCount; ++s) {
+                    U64 const D4 = HUF_DEltX1_set4(wksp->symbols[symbol + s], nbBits);
+                    MEM_write64(dt + uStart, D4);
+                    MEM_write64(dt + uStart + 4, D4);
+                    uStart += 8;
+                }
+                break;
+            default:
+                for (s=0; s<symbolCount; ++s) {
+                    U64 const D4 = HUF_DEltX1_set4(wksp->symbols[symbol + s], nbBits);
+                    for (u=0; u < length; u += 16) {
+                        MEM_write64(dt + uStart + u + 0, D4);
+                        MEM_write64(dt + uStart + u + 4, D4);
+                        MEM_write64(dt + uStart + u + 8, D4);
+                        MEM_write64(dt + uStart + u + 12, D4);
+                    }
+                    assert(u == length);
+                    uStart += length;
+                }
+                break;
+            }
+            symbol += symbolCount;
+            rankStart += symbolCount * length;
+        }
+    }
+    return iSize;
+}
+
+FORCE_INLINE_TEMPLATE BYTE
+HUF_decodeSymbolX1(BIT_DStream_t* Dstream, const HUF_DEltX1* dt, const U32 dtLog)
+{
+    size_t const val = BIT_lookBitsFast(Dstream, dtLog); /* note : dtLog >= 1 */
+    BYTE const c = dt[val].byte;
+    BIT_skipBits(Dstream, dt[val].nbBits);
+    return c;
+}
+
+#define HUF_DECODE_SYMBOLX1_0(ptr, DStreamPtr) \
+    do { *ptr++ = HUF_decodeSymbolX1(DStreamPtr, dt, dtLog); } while (0)
+
+#define HUF_DECODE_SYMBOLX1_1(ptr, DStreamPtr)      \
+    do {                                            \
+        if (MEM_64bits() || (HUF_TABLELOG_MAX<=12)) \
+            HUF_DECODE_SYMBOLX1_0(ptr, DStreamPtr); \
+    } while (0)
+
+#define HUF_DECODE_SYMBOLX1_2(ptr, DStreamPtr)      \
+    do {                                            \
+        if (MEM_64bits())                           \
+            HUF_DECODE_SYMBOLX1_0(ptr, DStreamPtr); \
+    } while (0)
+
+HINT_INLINE size_t
+HUF_decodeStreamX1(BYTE* p, BIT_DStream_t* const bitDPtr, BYTE* const pEnd, const HUF_DEltX1* const dt, const U32 dtLog)
+{
+    BYTE* const pStart = p;
+
+    /* up to 4 symbols at a time */
+    if ((pEnd - p) > 3) {
+        while ((BIT_reloadDStream(bitDPtr) == BIT_DStream_unfinished) & (p < pEnd-3)) {
+            HUF_DECODE_SYMBOLX1_2(p, bitDPtr);
+            HUF_DECODE_SYMBOLX1_1(p, bitDPtr);
+            HUF_DECODE_SYMBOLX1_2(p, bitDPtr);
+            HUF_DECODE_SYMBOLX1_0(p, bitDPtr);
+        }
+    } else {
+        BIT_reloadDStream(bitDPtr);
+    }
+
+    /* [0-3] symbols remaining */
+    if (MEM_32bits())
+        while ((BIT_reloadDStream(bitDPtr) == BIT_DStream_unfinished) & (p < pEnd))
+            HUF_DECODE_SYMBOLX1_0(p, bitDPtr);
+
+    /* no more data to retrieve from bitstream, no need to reload */
+    while (p < pEnd)
+        HUF_DECODE_SYMBOLX1_0(p, bitDPtr);
+
+    return (size_t)(pEnd-pStart);
+}
+
+FORCE_INLINE_TEMPLATE size_t
+HUF_decompress1X1_usingDTable_internal_body(
+          void* dst,  size_t dstSize,
+    const void* cSrc, size_t cSrcSize,
+    const HUF_DTable* DTable)
+{
+    BYTE* op = (BYTE*)dst;
+    BYTE* const oend = ZSTD_maybeNullPtrAdd(op, dstSize);
+    const void* dtPtr = DTable + 1;
+    const HUF_DEltX1* const dt = (const HUF_DEltX1*)dtPtr;
+    BIT_DStream_t bitD;
+    DTableDesc const dtd = HUF_getDTableDesc(DTable);
+    U32 const dtLog = dtd.tableLog;
+
+    CHECK_F( BIT_initDStream(&bitD, cSrc, cSrcSize) );
+
+    HUF_decodeStreamX1(op, &bitD, oend, dt, dtLog);
+
+    if (!BIT_endOfDStream(&bitD)) return ERROR(corruption_detected);
+
+    return dstSize;
+}
+
+/* HUF_decompress4X1_usingDTable_internal_body():
+ * Conditions :
+ * @dstSize >= 6
+ */
+FORCE_INLINE_TEMPLATE size_t
+HUF_decompress4X1_usingDTable_internal_body(
+          void* dst,  size_t dstSize,
+    const void* cSrc, size_t cSrcSize,
+    const HUF_DTable* DTable)
+{
+    /* Check */
+    if (cSrcSize < 10) return ERROR(corruption_detected);  /* strict minimum : jump table + 1 byte per stream */
+    if (dstSize < 6) return ERROR(corruption_detected);         /* stream 4-split doesn't work */
+
+    {   const BYTE* const istart = (const BYTE*) cSrc;
+        BYTE* const ostart = (BYTE*) dst;
+        BYTE* const oend = ostart + dstSize;
+        BYTE* const olimit = oend - 3;
+        const void* const dtPtr = DTable + 1;
+        const HUF_DEltX1* const dt = (const HUF_DEltX1*)dtPtr;
+
+        /* Init */
+        BIT_DStream_t bitD1;
+        BIT_DStream_t bitD2;
+        BIT_DStream_t bitD3;
+        BIT_DStream_t bitD4;
+        size_t const length1 = MEM_readLE16(istart);
+        size_t const length2 = MEM_readLE16(istart+2);
+        size_t const length3 = MEM_readLE16(istart+4);
+        size_t const length4 = cSrcSize - (length1 + length2 + length3 + 6);
+        const BYTE* const istart1 = istart + 6;  /* jumpTable */
+        const BYTE* const istart2 = istart1 + length1;
+        const BYTE* const istart3 = istart2 + length2;
+        const BYTE* const istart4 = istart3 + length3;
+        const size_t segmentSize = (dstSize+3) / 4;
+        BYTE* const opStart2 = ostart + segmentSize;
+        BYTE* const opStart3 = opStart2 + segmentSize;
+        BYTE* const opStart4 = opStart3 + segmentSize;
+        BYTE* op1 = ostart;
+        BYTE* op2 = opStart2;
+        BYTE* op3 = opStart3;
+        BYTE* op4 = opStart4;
+        DTableDesc const dtd = HUF_getDTableDesc(DTable);
+        U32 const dtLog = dtd.tableLog;
+        U32 endSignal = 1;
+
+        if (length4 > cSrcSize) return ERROR(corruption_detected);   /* overflow */
+        if (opStart4 > oend) return ERROR(corruption_detected);      /* overflow */
+        assert(dstSize >= 6); /* validated above */
+        CHECK_F( BIT_initDStream(&bitD1, istart1, length1) );
+        CHECK_F( BIT_initDStream(&bitD2, istart2, length2) );
+        CHECK_F( BIT_initDStream(&bitD3, istart3, length3) );
+        CHECK_F( BIT_initDStream(&bitD4, istart4, length4) );
+
+        /* up to 16 symbols per loop (4 symbols per stream) in 64-bit mode */
+        if ((size_t)(oend - op4) >= sizeof(size_t)) {
+            for ( ; (endSignal) & (op4 < olimit) ; ) {
+                HUF_DECODE_SYMBOLX1_2(op1, &bitD1);
+                HUF_DECODE_SYMBOLX1_2(op2, &bitD2);
+                HUF_DECODE_SYMBOLX1_2(op3, &bitD3);
+                HUF_DECODE_SYMBOLX1_2(op4, &bitD4);
+                HUF_DECODE_SYMBOLX1_1(op1, &bitD1);
+                HUF_DECODE_SYMBOLX1_1(op2, &bitD2);
+                HUF_DECODE_SYMBOLX1_1(op3, &bitD3);
+                HUF_DECODE_SYMBOLX1_1(op4, &bitD4);
+                HUF_DECODE_SYMBOLX1_2(op1, &bitD1);
+                HUF_DECODE_SYMBOLX1_2(op2, &bitD2);
+                HUF_DECODE_SYMBOLX1_2(op3, &bitD3);
+                HUF_DECODE_SYMBOLX1_2(op4, &bitD4);
+                HUF_DECODE_SYMBOLX1_0(op1, &bitD1);
+                HUF_DECODE_SYMBOLX1_0(op2, &bitD2);
+                HUF_DECODE_SYMBOLX1_0(op3, &bitD3);
+                HUF_DECODE_SYMBOLX1_0(op4, &bitD4);
+                endSignal &= BIT_reloadDStreamFast(&bitD1) == BIT_DStream_unfinished;
+                endSignal &= BIT_reloadDStreamFast(&bitD2) == BIT_DStream_unfinished;
+                endSignal &= BIT_reloadDStreamFast(&bitD3) == BIT_DStream_unfinished;
+                endSignal &= BIT_reloadDStreamFast(&bitD4) == BIT_DStream_unfinished;
+            }
+        }
+
+        /* check corruption */
+        /* note : should not be necessary : op# advance in lock step, and we control op4.
+         *        but curiously, binary generated by gcc 7.2 & 7.3 with -mbmi2 runs faster when >=1 test is present */
+        if (op1 > opStart2) return ERROR(corruption_detected);
+        if (op2 > opStart3) return ERROR(corruption_detected);
+        if (op3 > opStart4) return ERROR(corruption_detected);
+        /* note : op4 supposed already verified within main loop */
+
+        /* finish bitStreams one by one */
+        HUF_decodeStreamX1(op1, &bitD1, opStart2, dt, dtLog);
+        HUF_decodeStreamX1(op2, &bitD2, opStart3, dt, dtLog);
+        HUF_decodeStreamX1(op3, &bitD3, opStart4, dt, dtLog);
+        HUF_decodeStreamX1(op4, &bitD4, oend,     dt, dtLog);
+
+        /* check */
+        { U32 const endCheck = BIT_endOfDStream(&bitD1) & BIT_endOfDStream(&bitD2) & BIT_endOfDStream(&bitD3) & BIT_endOfDStream(&bitD4);
+          if (!endCheck) return ERROR(corruption_detected); }
+
+        /* decoded size */
+        return dstSize;
+    }
+}
+
+#if HUF_NEED_BMI2_FUNCTION
+static BMI2_TARGET_ATTRIBUTE
+size_t HUF_decompress4X1_usingDTable_internal_bmi2(void* dst, size_t dstSize, void const* cSrc,
+                    size_t cSrcSize, HUF_DTable const* DTable) {
+    return HUF_decompress4X1_usingDTable_internal_body(dst, dstSize, cSrc, cSrcSize, DTable);
+}
+#endif
+
+static
+size_t HUF_decompress4X1_usingDTable_internal_default(void* dst, size_t dstSize, void const* cSrc,
+                    size_t cSrcSize, HUF_DTable const* DTable) {
+    return HUF_decompress4X1_usingDTable_internal_body(dst, dstSize, cSrc, cSrcSize, DTable);
+}
+
+#if ZSTD_ENABLE_ASM_X86_64_BMI2
+
+HUF_ASM_DECL void HUF_decompress4X1_usingDTable_internal_fast_asm_loop(HUF_DecompressFastArgs* args) ZSTDLIB_HIDDEN;
+
+#endif
+
+static HUF_FAST_BMI2_ATTRS
+void HUF_decompress4X1_usingDTable_internal_fast_c_loop(HUF_DecompressFastArgs* args)
+{
+    U64 bits[4];
+    BYTE const* ip[4];
+    BYTE* op[4];
+    U16 const* const dtable = (U16 const*)args->dt;
+    BYTE* const oend = args->oend;
+    BYTE const* const ilowest = args->ilowest;
+
+    /* Copy the arguments to local variables */
+    ZSTD_memcpy(&bits, &args->bits, sizeof(bits));
+    ZSTD_memcpy((void*)(&ip), &args->ip, sizeof(ip));
+    ZSTD_memcpy(&op, &args->op, sizeof(op));
+
+    assert(MEM_isLittleEndian());
+    assert(!MEM_32bits());
+
+    for (;;) {
+        BYTE* olimit;
+        int stream;
+
+        /* Assert loop preconditions */
+#ifndef NDEBUG
+        for (stream = 0; stream < 4; ++stream) {
+            assert(op[stream] <= (stream == 3 ? oend : op[stream + 1]));
+            assert(ip[stream] >= ilowest);
+        }
+#endif
+        /* Compute olimit */
+        {
+            /* Each iteration produces 5 output symbols per stream */
+            size_t const oiters = (size_t)(oend - op[3]) / 5;
+            /* Each iteration consumes up to 11 bits * 5 = 55 bits < 7 bytes
+             * per stream.
+             */
+            size_t const iiters = (size_t)(ip[0] - ilowest) / 7;
+            /* We can safely run iters iterations before running bounds checks */
+            size_t const iters = MIN(oiters, iiters);
+            size_t const symbols = iters * 5;
+
+            /* We can simply check that op[3] < olimit, instead of checking all
+             * of our bounds, since we can't hit the other bounds until we've run
+             * iters iterations, which only happens when op[3] == olimit.
+             */
+            olimit = op[3] + symbols;
+
+            /* Exit fast decoding loop once we reach the end. */
+            if (op[3] == olimit)
+                break;
+
+            /* Exit the decoding loop if any input pointer has crossed the
+             * previous one. This indicates corruption, and a precondition
+             * to our loop is that ip[i] >= ip[0].
+             */
+            for (stream = 1; stream < 4; ++stream) {
+                if (ip[stream] < ip[stream - 1])
+                    goto _out;
+            }
+        }
+
+#ifndef NDEBUG
+        for (stream = 1; stream < 4; ++stream) {
+            assert(ip[stream] >= ip[stream - 1]);
+        }
+#endif
+
+#define HUF_4X1_DECODE_SYMBOL(_stream, _symbol)                 \
+    do {                                                        \
+        int const index = (int)(bits[(_stream)] >> 53);         \
+        int const entry = (int)dtable[index];                   \
+        bits[(_stream)] <<= (entry & 0x3F);                     \
+        op[(_stream)][(_symbol)] = (BYTE)((entry >> 8) & 0xFF); \
+    } while (0)
+
+#define HUF_4X1_RELOAD_STREAM(_stream)                              \
+    do {                                                            \
+        int const ctz = ZSTD_countTrailingZeros64(bits[(_stream)]); \
+        int const nbBits = ctz & 7;                                 \
+        int const nbBytes = ctz >> 3;                               \
+        op[(_stream)] += 5;                                         \
+        ip[(_stream)] -= nbBytes;                                   \
+        bits[(_stream)] = MEM_read64(ip[(_stream)]) | 1;            \
+        bits[(_stream)] <<= nbBits;                                 \
+    } while (0)
+
+        /* Manually unroll the loop because compilers don't consistently
+         * unroll the inner loops, which destroys performance.
+         */
+        do {
+            /* Decode 5 symbols in each of the 4 streams */
+            HUF_4X_FOR_EACH_STREAM_WITH_VAR(HUF_4X1_DECODE_SYMBOL, 0);
+            HUF_4X_FOR_EACH_STREAM_WITH_VAR(HUF_4X1_DECODE_SYMBOL, 1);
+            HUF_4X_FOR_EACH_STREAM_WITH_VAR(HUF_4X1_DECODE_SYMBOL, 2);
+            HUF_4X_FOR_EACH_STREAM_WITH_VAR(HUF_4X1_DECODE_SYMBOL, 3);
+            HUF_4X_FOR_EACH_STREAM_WITH_VAR(HUF_4X1_DECODE_SYMBOL, 4);
+
+            /* Reload each of the 4 the bitstreams */
+            HUF_4X_FOR_EACH_STREAM(HUF_4X1_RELOAD_STREAM);
+        } while (op[3] < olimit);
+
+#undef HUF_4X1_DECODE_SYMBOL
+#undef HUF_4X1_RELOAD_STREAM
+    }
+
+_out:
+
+    /* Save the final values of each of the state variables back to args. */
+    ZSTD_memcpy(&args->bits, &bits, sizeof(bits));
+    ZSTD_memcpy((void*)(&args->ip), &ip, sizeof(ip));
+    ZSTD_memcpy(&args->op, &op, sizeof(op));
+}
+
+/**
+ * @returns @p dstSize on success (>= 6)
+ *          0 if the fallback implementation should be used
+ *          An error if an error occurred
+ */
+static HUF_FAST_BMI2_ATTRS
+size_t
+HUF_decompress4X1_usingDTable_internal_fast(
+          void* dst,  size_t dstSize,
+    const void* cSrc, size_t cSrcSize,
+    const HUF_DTable* DTable,
+    HUF_DecompressFastLoopFn loopFn)
+{
+    void const* dt = DTable + 1;
+    BYTE const* const ilowest = (BYTE const*)cSrc;
+    BYTE* const oend = ZSTD_maybeNullPtrAdd((BYTE*)dst, dstSize);
+    HUF_DecompressFastArgs args;
+    {   size_t const ret = HUF_DecompressFastArgs_init(&args, dst, dstSize, cSrc, cSrcSize, DTable);
+        FORWARD_IF_ERROR(ret, "Failed to init fast loop args");
+        if (ret == 0)
+            return 0;
+    }
+
+    assert(args.ip[0] >= args.ilowest);
+    loopFn(&args);
+
+    /* Our loop guarantees that ip[] >= ilowest and that we haven't
+    * overwritten any op[].
+    */
+    assert(args.ip[0] >= ilowest);
+    assert(args.ip[0] >= ilowest);
+    assert(args.ip[1] >= ilowest);
+    assert(args.ip[2] >= ilowest);
+    assert(args.ip[3] >= ilowest);
+    assert(args.op[3] <= oend);
+
+    assert(ilowest == args.ilowest);
+    assert(ilowest + 6 == args.iend[0]);
+    (void)ilowest;
+
+    /* finish bit streams one by one. */
+    {   size_t const segmentSize = (dstSize+3) / 4;
+        BYTE* segmentEnd = (BYTE*)dst;
+        int i;
+        for (i = 0; i < 4; ++i) {
+            BIT_DStream_t bit;
+            if (segmentSize <= (size_t)(oend - segmentEnd))
+                segmentEnd += segmentSize;
+            else
+                segmentEnd = oend;
+            FORWARD_IF_ERROR(HUF_initRemainingDStream(&bit, &args, i, segmentEnd), "corruption");
+            /* Decompress and validate that we've produced exactly the expected length. */
+            args.op[i] += HUF_decodeStreamX1(args.op[i], &bit, segmentEnd, (HUF_DEltX1 const*)dt, HUF_DECODER_FAST_TABLELOG);
+            if (args.op[i] != segmentEnd) return ERROR(corruption_detected);
+        }
+    }
+
+    /* decoded size */
+    assert(dstSize != 0);
+    return dstSize;
+}
+
+HUF_DGEN(HUF_decompress1X1_usingDTable_internal)
+
+static size_t HUF_decompress4X1_usingDTable_internal(void* dst, size_t dstSize, void const* cSrc,
+                    size_t cSrcSize, HUF_DTable const* DTable, int flags)
+{
+    HUF_DecompressUsingDTableFn fallbackFn = HUF_decompress4X1_usingDTable_internal_default;
+    HUF_DecompressFastLoopFn loopFn = HUF_decompress4X1_usingDTable_internal_fast_c_loop;
+
+#if DYNAMIC_BMI2
+    if (flags & HUF_flags_bmi2) {
+        fallbackFn = HUF_decompress4X1_usingDTable_internal_bmi2;
+# if ZSTD_ENABLE_ASM_X86_64_BMI2
+        if (!(flags & HUF_flags_disableAsm)) {
+            loopFn = HUF_decompress4X1_usingDTable_internal_fast_asm_loop;
+        }
+# endif
+    } else {
+        return fallbackFn(dst, dstSize, cSrc, cSrcSize, DTable);
+    }
+#endif
+
+#if ZSTD_ENABLE_ASM_X86_64_BMI2 && defined(__BMI2__)
+    if (!(flags & HUF_flags_disableAsm)) {
+        loopFn = HUF_decompress4X1_usingDTable_internal_fast_asm_loop;
+    }
+#endif
+
+    if (HUF_ENABLE_FAST_DECODE && !(flags & HUF_flags_disableFast)) {
+        size_t const ret = HUF_decompress4X1_usingDTable_internal_fast(dst, dstSize, cSrc, cSrcSize, DTable, loopFn);
+        if (ret != 0)
+            return ret;
+    }
+    return fallbackFn(dst, dstSize, cSrc, cSrcSize, DTable);
+}
+
+static size_t HUF_decompress4X1_DCtx_wksp(HUF_DTable* dctx, void* dst, size_t dstSize,
+                                   const void* cSrc, size_t cSrcSize,
+                                   void* workSpace, size_t wkspSize, int flags)
+{
+    const BYTE* ip = (const BYTE*) cSrc;
+
+    size_t const hSize = HUF_readDTableX1_wksp(dctx, cSrc, cSrcSize, workSpace, wkspSize, flags);
+    if (HUF_isError(hSize)) return hSize;
+    if (hSize >= cSrcSize) return ERROR(srcSize_wrong);
+    ip += hSize; cSrcSize -= hSize;
+
+    return HUF_decompress4X1_usingDTable_internal(dst, dstSize, ip, cSrcSize, dctx, flags);
+}
+
+#endif /* HUF_FORCE_DECOMPRESS_X2 */
+
+
+#ifndef HUF_FORCE_DECOMPRESS_X1
+
+/* *************************/
+/* double-symbols decoding */
+/* *************************/
+
+typedef struct { U16 sequence; BYTE nbBits; BYTE length; } HUF_DEltX2;  /* double-symbols decoding */
+typedef struct { BYTE symbol; } sortedSymbol_t;
+typedef U32 rankValCol_t[HUF_TABLELOG_MAX + 1];
+typedef rankValCol_t rankVal_t[HUF_TABLELOG_MAX];
+
+/**
+ * Constructs a HUF_DEltX2 in a U32.
+ */
+static U32 HUF_buildDEltX2U32(U32 symbol, U32 nbBits, U32 baseSeq, int level)
+{
+    U32 seq;
+    DEBUG_STATIC_ASSERT(offsetof(HUF_DEltX2, sequence) == 0);
+    DEBUG_STATIC_ASSERT(offsetof(HUF_DEltX2, nbBits) == 2);
+    DEBUG_STATIC_ASSERT(offsetof(HUF_DEltX2, length) == 3);
+    DEBUG_STATIC_ASSERT(sizeof(HUF_DEltX2) == sizeof(U32));
+    if (MEM_isLittleEndian()) {
+        seq = level == 1 ? symbol : (baseSeq + (symbol << 8));
+        return seq + (nbBits << 16) + ((U32)level << 24);
+    } else {
+        seq = level == 1 ? (symbol << 8) : ((baseSeq << 8) + symbol);
+        return (seq << 16) + (nbBits << 8) + (U32)level;
+    }
+}
+
+/**
+ * Constructs a HUF_DEltX2.
+ */
+static HUF_DEltX2 HUF_buildDEltX2(U32 symbol, U32 nbBits, U32 baseSeq, int level)
+{
+    HUF_DEltX2 DElt;
+    U32 const val = HUF_buildDEltX2U32(symbol, nbBits, baseSeq, level);
+    DEBUG_STATIC_ASSERT(sizeof(DElt) == sizeof(val));
+    ZSTD_memcpy(&DElt, &val, sizeof(val));
+    return DElt;
+}
+
+/**
+ * Constructs 2 HUF_DEltX2s and packs them into a U64.
+ */
+static U64 HUF_buildDEltX2U64(U32 symbol, U32 nbBits, U16 baseSeq, int level)
+{
+    U32 DElt = HUF_buildDEltX2U32(symbol, nbBits, baseSeq, level);
+    return (U64)DElt + ((U64)DElt << 32);
+}
+
+/**
+ * Fills the DTable rank with all the symbols from [begin, end) that are each
+ * nbBits long.
+ *
+ * @param DTableRank The start of the rank in the DTable.
+ * @param begin The first symbol to fill (inclusive).
+ * @param end The last symbol to fill (exclusive).
+ * @param nbBits Each symbol is nbBits long.
+ * @param tableLog The table log.
+ * @param baseSeq If level == 1 { 0 } else { the first level symbol }
+ * @param level The level in the table. Must be 1 or 2.
+ */
+static void HUF_fillDTableX2ForWeight(
+    HUF_DEltX2* DTableRank,
+    sortedSymbol_t const* begin, sortedSymbol_t const* end,
+    U32 nbBits, U32 tableLog,
+    U16 baseSeq, int const level)
+{
+    U32 const length = 1U << ((tableLog - nbBits) & 0x1F /* quiet static-analyzer */);
+    const sortedSymbol_t* ptr;
+    assert(level >= 1 && level <= 2);
+    switch (length) {
+    case 1:
+        for (ptr = begin; ptr != end; ++ptr) {
+            HUF_DEltX2 const DElt = HUF_buildDEltX2(ptr->symbol, nbBits, baseSeq, level);
+            *DTableRank++ = DElt;
+        }
+        break;
+    case 2:
+        for (ptr = begin; ptr != end; ++ptr) {
+            HUF_DEltX2 const DElt = HUF_buildDEltX2(ptr->symbol, nbBits, baseSeq, level);
+            DTableRank[0] = DElt;
+            DTableRank[1] = DElt;
+            DTableRank += 2;
+        }
+        break;
+    case 4:
+        for (ptr = begin; ptr != end; ++ptr) {
+            U64 const DEltX2 = HUF_buildDEltX2U64(ptr->symbol, nbBits, baseSeq, level);
+            ZSTD_memcpy(DTableRank + 0, &DEltX2, sizeof(DEltX2));
+            ZSTD_memcpy(DTableRank + 2, &DEltX2, sizeof(DEltX2));
+            DTableRank += 4;
+        }
+        break;
+    case 8:
+        for (ptr = begin; ptr != end; ++ptr) {
+            U64 const DEltX2 = HUF_buildDEltX2U64(ptr->symbol, nbBits, baseSeq, level);
+            ZSTD_memcpy(DTableRank + 0, &DEltX2, sizeof(DEltX2));
+            ZSTD_memcpy(DTableRank + 2, &DEltX2, sizeof(DEltX2));
+            ZSTD_memcpy(DTableRank + 4, &DEltX2, sizeof(DEltX2));
+            ZSTD_memcpy(DTableRank + 6, &DEltX2, sizeof(DEltX2));
+            DTableRank += 8;
+        }
+        break;
+    default:
+        for (ptr = begin; ptr != end; ++ptr) {
+            U64 const DEltX2 = HUF_buildDEltX2U64(ptr->symbol, nbBits, baseSeq, level);
+            HUF_DEltX2* const DTableRankEnd = DTableRank + length;
+            for (; DTableRank != DTableRankEnd; DTableRank += 8) {
+                ZSTD_memcpy(DTableRank + 0, &DEltX2, sizeof(DEltX2));
+                ZSTD_memcpy(DTableRank + 2, &DEltX2, sizeof(DEltX2));
+                ZSTD_memcpy(DTableRank + 4, &DEltX2, sizeof(DEltX2));
+                ZSTD_memcpy(DTableRank + 6, &DEltX2, sizeof(DEltX2));
+            }
+        }
+        break;
+    }
+}
+
+/* HUF_fillDTableX2Level2() :
+ * `rankValOrigin` must be a table of at least (HUF_TABLELOG_MAX + 1) U32 */
+static void HUF_fillDTableX2Level2(HUF_DEltX2* DTable, U32 targetLog, const U32 consumedBits,
+                           const U32* rankVal, const int minWeight, const int maxWeight1,
+                           const sortedSymbol_t* sortedSymbols, U32 const* rankStart,
+                           U32 nbBitsBaseline, U16 baseSeq)
+{
+    /* Fill skipped values (all positions up to rankVal[minWeight]).
+     * These are positions only get a single symbol because the combined weight
+     * is too large.
+     */
+    if (minWeight>1) {
+        U32 const length = 1U << ((targetLog - consumedBits) & 0x1F /* quiet static-analyzer */);
+        U64 const DEltX2 = HUF_buildDEltX2U64(baseSeq, consumedBits, /* baseSeq */ 0, /* level */ 1);
+        int const skipSize = rankVal[minWeight];
+        assert(length > 1);
+        assert((U32)skipSize < length);
+        switch (length) {
+        case 2:
+            assert(skipSize == 1);
+            ZSTD_memcpy(DTable, &DEltX2, sizeof(DEltX2));
+            break;
+        case 4:
+            assert(skipSize <= 4);
+            ZSTD_memcpy(DTable + 0, &DEltX2, sizeof(DEltX2));
+            ZSTD_memcpy(DTable + 2, &DEltX2, sizeof(DEltX2));
+            break;
+        default:
+            {
+                int i;
+                for (i = 0; i < skipSize; i += 8) {
+                    ZSTD_memcpy(DTable + i + 0, &DEltX2, sizeof(DEltX2));
+                    ZSTD_memcpy(DTable + i + 2, &DEltX2, sizeof(DEltX2));
+                    ZSTD_memcpy(DTable + i + 4, &DEltX2, sizeof(DEltX2));
+                    ZSTD_memcpy(DTable + i + 6, &DEltX2, sizeof(DEltX2));
+                }
+            }
+        }
+    }
+
+    /* Fill each of the second level symbols by weight. */
+    {
+        int w;
+        for (w = minWeight; w < maxWeight1; ++w) {
+            int const begin = rankStart[w];
+            int const end = rankStart[w+1];
+            U32 const nbBits = nbBitsBaseline - w;
+            U32 const totalBits = nbBits + consumedBits;
+            HUF_fillDTableX2ForWeight(
+                DTable + rankVal[w],
+                sortedSymbols + begin, sortedSymbols + end,
+                totalBits, targetLog,
+                baseSeq, /* level */ 2);
+        }
+    }
+}
+
+static void HUF_fillDTableX2(HUF_DEltX2* DTable, const U32 targetLog,
+                           const sortedSymbol_t* sortedList,
+                           const U32* rankStart, rankValCol_t* rankValOrigin, const U32 maxWeight,
+                           const U32 nbBitsBaseline)
+{
+    U32* const rankVal = rankValOrigin[0];
+    const int scaleLog = nbBitsBaseline - targetLog;   /* note : targetLog >= srcLog, hence scaleLog <= 1 */
+    const U32 minBits  = nbBitsBaseline - maxWeight;
+    int w;
+    int const wEnd = (int)maxWeight + 1;
+
+    /* Fill DTable in order of weight. */
+    for (w = 1; w < wEnd; ++w) {
+        int const begin = (int)rankStart[w];
+        int const end = (int)rankStart[w+1];
+        U32 const nbBits = nbBitsBaseline - w;
+
+        if (targetLog-nbBits >= minBits) {
+            /* Enough room for a second symbol. */
+            int start = rankVal[w];
+            U32 const length = 1U << ((targetLog - nbBits) & 0x1F /* quiet static-analyzer */);
+            int minWeight = nbBits + scaleLog;
+            int s;
+            if (minWeight < 1) minWeight = 1;
+            /* Fill the DTable for every symbol of weight w.
+             * These symbols get at least 1 second symbol.
+             */
+            for (s = begin; s != end; ++s) {
+                HUF_fillDTableX2Level2(
+                    DTable + start, targetLog, nbBits,
+                    rankValOrigin[nbBits], minWeight, wEnd,
+                    sortedList, rankStart,
+                    nbBitsBaseline, sortedList[s].symbol);
+                start += length;
+            }
+        } else {
+            /* Only a single symbol. */
+            HUF_fillDTableX2ForWeight(
+                DTable + rankVal[w],
+                sortedList + begin, sortedList + end,
+                nbBits, targetLog,
+                /* baseSeq */ 0, /* level */ 1);
+        }
+    }
+}
+
+typedef struct {
+    rankValCol_t rankVal[HUF_TABLELOG_MAX];
+    U32 rankStats[HUF_TABLELOG_MAX + 1];
+    U32 rankStart0[HUF_TABLELOG_MAX + 3];
+    sortedSymbol_t sortedSymbol[HUF_SYMBOLVALUE_MAX + 1];
+    BYTE weightList[HUF_SYMBOLVALUE_MAX + 1];
+    U32 calleeWksp[HUF_READ_STATS_WORKSPACE_SIZE_U32];
+} HUF_ReadDTableX2_Workspace;
+
+size_t HUF_readDTableX2_wksp(HUF_DTable* DTable,
+                       const void* src, size_t srcSize,
+                             void* workSpace, size_t wkspSize, int flags)
+{
+    U32 tableLog, maxW, nbSymbols;
+    DTableDesc dtd = HUF_getDTableDesc(DTable);
+    U32 maxTableLog = dtd.maxTableLog;
+    size_t iSize;
+    void* dtPtr = DTable+1;   /* force compiler to avoid strict-aliasing */
+    HUF_DEltX2* const dt = (HUF_DEltX2*)dtPtr;
+    U32 *rankStart;
+
+    HUF_ReadDTableX2_Workspace* const wksp = (HUF_ReadDTableX2_Workspace*)workSpace;
+
+    if (sizeof(*wksp) > wkspSize) return ERROR(GENERIC);
+
+    rankStart = wksp->rankStart0 + 1;
+    ZSTD_memset(wksp->rankStats, 0, sizeof(wksp->rankStats));
+    ZSTD_memset(wksp->rankStart0, 0, sizeof(wksp->rankStart0));
+
+    DEBUG_STATIC_ASSERT(sizeof(HUF_DEltX2) == sizeof(HUF_DTable));   /* if compiler fails here, assertion is wrong */
+    if (maxTableLog > HUF_TABLELOG_MAX) return ERROR(tableLog_tooLarge);
+    /* ZSTD_memset(weightList, 0, sizeof(weightList)); */  /* is not necessary, even though some analyzer complain ... */
+
+    iSize = HUF_readStats_wksp(wksp->weightList, HUF_SYMBOLVALUE_MAX + 1, wksp->rankStats, &nbSymbols, &tableLog, src, srcSize, wksp->calleeWksp, sizeof(wksp->calleeWksp), flags);
+    if (HUF_isError(iSize)) return iSize;
+
+    /* check result */
+    if (tableLog > maxTableLog) return ERROR(tableLog_tooLarge);   /* DTable can't fit code depth */
+    if (tableLog <= HUF_DECODER_FAST_TABLELOG && maxTableLog > HUF_DECODER_FAST_TABLELOG) maxTableLog = HUF_DECODER_FAST_TABLELOG;
+
+    /* find maxWeight */
+    for (maxW = tableLog; wksp->rankStats[maxW]==0; maxW--) {}  /* necessarily finds a solution before 0 */
+
+    /* Get start index of each weight */
+    {   U32 w, nextRankStart = 0;
+        for (w=1; w<maxW+1; w++) {
+            U32 curr = nextRankStart;
+            nextRankStart += wksp->rankStats[w];
+            rankStart[w] = curr;
+        }
+        rankStart[0] = nextRankStart;   /* put all 0w symbols at the end of sorted list*/
+        rankStart[maxW+1] = nextRankStart;
+    }
+
+    /* sort symbols by weight */
+    {   U32 s;
+        for (s=0; s<nbSymbols; s++) {
+            U32 const w = wksp->weightList[s];
+            U32 const r = rankStart[w]++;
+            wksp->sortedSymbol[r].symbol = (BYTE)s;
+        }
+        rankStart[0] = 0;   /* forget 0w symbols; this is beginning of weight(1) */
+    }
+
+    /* Build rankVal */
+    {   U32* const rankVal0 = wksp->rankVal[0];
+        {   int const rescale = (maxTableLog-tableLog) - 1;   /* tableLog <= maxTableLog */
+            U32 nextRankVal = 0;
+            U32 w;
+            for (w=1; w<maxW+1; w++) {
+                U32 curr = nextRankVal;
+                nextRankVal += wksp->rankStats[w] << (w+rescale);
+                rankVal0[w] = curr;
+        }   }
+        {   U32 const minBits = tableLog+1 - maxW;
+            U32 consumed;
+            for (consumed = minBits; consumed < maxTableLog - minBits + 1; consumed++) {
+                U32* const rankValPtr = wksp->rankVal[consumed];
+                U32 w;
+                for (w = 1; w < maxW+1; w++) {
+                    rankValPtr[w] = rankVal0[w] >> consumed;
+    }   }   }   }
+
+    HUF_fillDTableX2(dt, maxTableLog,
+                   wksp->sortedSymbol,
+                   wksp->rankStart0, wksp->rankVal, maxW,
+                   tableLog+1);
+
+    dtd.tableLog = (BYTE)maxTableLog;
+    dtd.tableType = 1;
+    ZSTD_memcpy(DTable, &dtd, sizeof(dtd));
+    return iSize;
+}
+
+
+FORCE_INLINE_TEMPLATE U32
+HUF_decodeSymbolX2(void* op, BIT_DStream_t* DStream, const HUF_DEltX2* dt, const U32 dtLog)
+{
+    size_t const val = BIT_lookBitsFast(DStream, dtLog);   /* note : dtLog >= 1 */
+    ZSTD_memcpy(op, &dt[val].sequence, 2);
+    BIT_skipBits(DStream, dt[val].nbBits);
+    return dt[val].length;
+}
+
+FORCE_INLINE_TEMPLATE U32
+HUF_decodeLastSymbolX2(void* op, BIT_DStream_t* DStream, const HUF_DEltX2* dt, const U32 dtLog)
+{
+    size_t const val = BIT_lookBitsFast(DStream, dtLog);   /* note : dtLog >= 1 */
+    ZSTD_memcpy(op, &dt[val].sequence, 1);
+    if (dt[val].length==1) {
+        BIT_skipBits(DStream, dt[val].nbBits);
+    } else {
+        if (DStream->bitsConsumed < (sizeof(DStream->bitContainer)*8)) {
+            BIT_skipBits(DStream, dt[val].nbBits);
+            if (DStream->bitsConsumed > (sizeof(DStream->bitContainer)*8))
+                /* ugly hack; works only because it's the last symbol. Note : can't easily extract nbBits from just this symbol */
+                DStream->bitsConsumed = (sizeof(DStream->bitContainer)*8);
+        }
+    }
+    return 1;
+}
+
+#define HUF_DECODE_SYMBOLX2_0(ptr, DStreamPtr) \
+    do { ptr += HUF_decodeSymbolX2(ptr, DStreamPtr, dt, dtLog); } while (0)
+
+#define HUF_DECODE_SYMBOLX2_1(ptr, DStreamPtr)                     \
+    do {                                                           \
+        if (MEM_64bits() || (HUF_TABLELOG_MAX<=12))                \
+            ptr += HUF_decodeSymbolX2(ptr, DStreamPtr, dt, dtLog); \
+    } while (0)
+
+#define HUF_DECODE_SYMBOLX2_2(ptr, DStreamPtr)                     \
+    do {                                                           \
+        if (MEM_64bits())                                          \
+            ptr += HUF_decodeSymbolX2(ptr, DStreamPtr, dt, dtLog); \
+    } while (0)
+
+HINT_INLINE size_t
+HUF_decodeStreamX2(BYTE* p, BIT_DStream_t* bitDPtr, BYTE* const pEnd,
+                const HUF_DEltX2* const dt, const U32 dtLog)
+{
+    BYTE* const pStart = p;
+
+    /* up to 8 symbols at a time */
+    if ((size_t)(pEnd - p) >= sizeof(bitDPtr->bitContainer)) {
+        if (dtLog <= 11 && MEM_64bits()) {
+            /* up to 10 symbols at a time */
+            while ((BIT_reloadDStream(bitDPtr) == BIT_DStream_unfinished) & (p < pEnd-9)) {
+                HUF_DECODE_SYMBOLX2_0(p, bitDPtr);
+                HUF_DECODE_SYMBOLX2_0(p, bitDPtr);
+                HUF_DECODE_SYMBOLX2_0(p, bitDPtr);
+                HUF_DECODE_SYMBOLX2_0(p, bitDPtr);
+                HUF_DECODE_SYMBOLX2_0(p, bitDPtr);
+            }
+        } else {
+            /* up to 8 symbols at a time */
+            while ((BIT_reloadDStream(bitDPtr) == BIT_DStream_unfinished) & (p < pEnd-(sizeof(bitDPtr->bitContainer)-1))) {
+                HUF_DECODE_SYMBOLX2_2(p, bitDPtr);
+                HUF_DECODE_SYMBOLX2_1(p, bitDPtr);
+                HUF_DECODE_SYMBOLX2_2(p, bitDPtr);
+                HUF_DECODE_SYMBOLX2_0(p, bitDPtr);
+            }
+        }
+    } else {
+        BIT_reloadDStream(bitDPtr);
+    }
+
+    /* closer to end : up to 2 symbols at a time */
+    if ((size_t)(pEnd - p) >= 2) {
+        while ((BIT_reloadDStream(bitDPtr) == BIT_DStream_unfinished) & (p <= pEnd-2))
+            HUF_DECODE_SYMBOLX2_0(p, bitDPtr);
+
+        while (p <= pEnd-2)
+            HUF_DECODE_SYMBOLX2_0(p, bitDPtr);   /* no need to reload : reached the end of DStream */
+    }
+
+    if (p < pEnd)
+        p += HUF_decodeLastSymbolX2(p, bitDPtr, dt, dtLog);
+
+    return p-pStart;
+}
+
+FORCE_INLINE_TEMPLATE size_t
+HUF_decompress1X2_usingDTable_internal_body(
+          void* dst,  size_t dstSize,
+    const void* cSrc, size_t cSrcSize,
+    const HUF_DTable* DTable)
+{
+    BIT_DStream_t bitD;
+
+    /* Init */
+    CHECK_F( BIT_initDStream(&bitD, cSrc, cSrcSize) );
+
+    /* decode */
+    {   BYTE* const ostart = (BYTE*) dst;
+        BYTE* const oend = ZSTD_maybeNullPtrAdd(ostart, dstSize);
+        const void* const dtPtr = DTable+1;   /* force compiler to not use strict-aliasing */
+        const HUF_DEltX2* const dt = (const HUF_DEltX2*)dtPtr;
+        DTableDesc const dtd = HUF_getDTableDesc(DTable);
+        HUF_decodeStreamX2(ostart, &bitD, oend, dt, dtd.tableLog);
+    }
+
+    /* check */
+    if (!BIT_endOfDStream(&bitD)) return ERROR(corruption_detected);
+
+    /* decoded size */
+    return dstSize;
+}
+
+/* HUF_decompress4X2_usingDTable_internal_body():
+ * Conditions:
+ * @dstSize >= 6
+ */
+FORCE_INLINE_TEMPLATE size_t
+HUF_decompress4X2_usingDTable_internal_body(
+          void* dst,  size_t dstSize,
+    const void* cSrc, size_t cSrcSize,
+    const HUF_DTable* DTable)
+{
+    if (cSrcSize < 10) return ERROR(corruption_detected);   /* strict minimum : jump table + 1 byte per stream */
+    if (dstSize < 6) return ERROR(corruption_detected);         /* stream 4-split doesn't work */
+
+    {   const BYTE* const istart = (const BYTE*) cSrc;
+        BYTE* const ostart = (BYTE*) dst;
+        BYTE* const oend = ostart + dstSize;
+        BYTE* const olimit = oend - (sizeof(size_t)-1);
+        const void* const dtPtr = DTable+1;
+        const HUF_DEltX2* const dt = (const HUF_DEltX2*)dtPtr;
+
+        /* Init */
+        BIT_DStream_t bitD1;
+        BIT_DStream_t bitD2;
+        BIT_DStream_t bitD3;
+        BIT_DStream_t bitD4;
+        size_t const length1 = MEM_readLE16(istart);
+        size_t const length2 = MEM_readLE16(istart+2);
+        size_t const length3 = MEM_readLE16(istart+4);
+        size_t const length4 = cSrcSize - (length1 + length2 + length3 + 6);
+        const BYTE* const istart1 = istart + 6;  /* jumpTable */
+        const BYTE* const istart2 = istart1 + length1;
+        const BYTE* const istart3 = istart2 + length2;
+        const BYTE* const istart4 = istart3 + length3;
+        size_t const segmentSize = (dstSize+3) / 4;
+        BYTE* const opStart2 = ostart + segmentSize;
+        BYTE* const opStart3 = opStart2 + segmentSize;
+        BYTE* const opStart4 = opStart3 + segmentSize;
+        BYTE* op1 = ostart;
+        BYTE* op2 = opStart2;
+        BYTE* op3 = opStart3;
+        BYTE* op4 = opStart4;
+        U32 endSignal = 1;
+        DTableDesc const dtd = HUF_getDTableDesc(DTable);
+        U32 const dtLog = dtd.tableLog;
+
+        if (length4 > cSrcSize) return ERROR(corruption_detected);  /* overflow */
+        if (opStart4 > oend) return ERROR(corruption_detected);     /* overflow */
+        assert(dstSize >= 6 /* validated above */);
+        CHECK_F( BIT_initDStream(&bitD1, istart1, length1) );
+        CHECK_F( BIT_initDStream(&bitD2, istart2, length2) );
+        CHECK_F( BIT_initDStream(&bitD3, istart3, length3) );
+        CHECK_F( BIT_initDStream(&bitD4, istart4, length4) );
+
+        /* 16-32 symbols per loop (4-8 symbols per stream) */
+        if ((size_t)(oend - op4) >= sizeof(size_t)) {
+            for ( ; (endSignal) & (op4 < olimit); ) {
+#if defined(__clang__) && (defined(__x86_64__) || defined(__i386__))
+                HUF_DECODE_SYMBOLX2_2(op1, &bitD1);
+                HUF_DECODE_SYMBOLX2_1(op1, &bitD1);
+                HUF_DECODE_SYMBOLX2_2(op1, &bitD1);
+                HUF_DECODE_SYMBOLX2_0(op1, &bitD1);
+                HUF_DECODE_SYMBOLX2_2(op2, &bitD2);
+                HUF_DECODE_SYMBOLX2_1(op2, &bitD2);
+                HUF_DECODE_SYMBOLX2_2(op2, &bitD2);
+                HUF_DECODE_SYMBOLX2_0(op2, &bitD2);
+                endSignal &= BIT_reloadDStreamFast(&bitD1) == BIT_DStream_unfinished;
+                endSignal &= BIT_reloadDStreamFast(&bitD2) == BIT_DStream_unfinished;
+                HUF_DECODE_SYMBOLX2_2(op3, &bitD3);
+                HUF_DECODE_SYMBOLX2_1(op3, &bitD3);
+                HUF_DECODE_SYMBOLX2_2(op3, &bitD3);
+                HUF_DECODE_SYMBOLX2_0(op3, &bitD3);
+                HUF_DECODE_SYMBOLX2_2(op4, &bitD4);
+                HUF_DECODE_SYMBOLX2_1(op4, &bitD4);
+                HUF_DECODE_SYMBOLX2_2(op4, &bitD4);
+                HUF_DECODE_SYMBOLX2_0(op4, &bitD4);
+                endSignal &= BIT_reloadDStreamFast(&bitD3) == BIT_DStream_unfinished;
+                endSignal &= BIT_reloadDStreamFast(&bitD4) == BIT_DStream_unfinished;
+#else
+                HUF_DECODE_SYMBOLX2_2(op1, &bitD1);
+                HUF_DECODE_SYMBOLX2_2(op2, &bitD2);
+                HUF_DECODE_SYMBOLX2_2(op3, &bitD3);
+                HUF_DECODE_SYMBOLX2_2(op4, &bitD4);
+                HUF_DECODE_SYMBOLX2_1(op1, &bitD1);
+                HUF_DECODE_SYMBOLX2_1(op2, &bitD2);
+                HUF_DECODE_SYMBOLX2_1(op3, &bitD3);
+                HUF_DECODE_SYMBOLX2_1(op4, &bitD4);
+                HUF_DECODE_SYMBOLX2_2(op1, &bitD1);
+                HUF_DECODE_SYMBOLX2_2(op2, &bitD2);
+                HUF_DECODE_SYMBOLX2_2(op3, &bitD3);
+                HUF_DECODE_SYMBOLX2_2(op4, &bitD4);
+                HUF_DECODE_SYMBOLX2_0(op1, &bitD1);
+                HUF_DECODE_SYMBOLX2_0(op2, &bitD2);
+                HUF_DECODE_SYMBOLX2_0(op3, &bitD3);
+                HUF_DECODE_SYMBOLX2_0(op4, &bitD4);
+                endSignal = (U32)LIKELY((U32)
+                            (BIT_reloadDStreamFast(&bitD1) == BIT_DStream_unfinished)
+                        & (BIT_reloadDStreamFast(&bitD2) == BIT_DStream_unfinished)
+                        & (BIT_reloadDStreamFast(&bitD3) == BIT_DStream_unfinished)
+                        & (BIT_reloadDStreamFast(&bitD4) == BIT_DStream_unfinished));
+#endif
+            }
+        }
+
+        /* check corruption */
+        if (op1 > opStart2) return ERROR(corruption_detected);
+        if (op2 > opStart3) return ERROR(corruption_detected);
+        if (op3 > opStart4) return ERROR(corruption_detected);
+        /* note : op4 already verified within main loop */
+
+        /* finish bitStreams one by one */
+        HUF_decodeStreamX2(op1, &bitD1, opStart2, dt, dtLog);
+        HUF_decodeStreamX2(op2, &bitD2, opStart3, dt, dtLog);
+        HUF_decodeStreamX2(op3, &bitD3, opStart4, dt, dtLog);
+        HUF_decodeStreamX2(op4, &bitD4, oend,     dt, dtLog);
+
+        /* check */
+        { U32 const endCheck = BIT_endOfDStream(&bitD1) & BIT_endOfDStream(&bitD2) & BIT_endOfDStream(&bitD3) & BIT_endOfDStream(&bitD4);
+          if (!endCheck) return ERROR(corruption_detected); }
+
+        /* decoded size */
+        return dstSize;
+    }
+}
+
+#if HUF_NEED_BMI2_FUNCTION
+static BMI2_TARGET_ATTRIBUTE
+size_t HUF_decompress4X2_usingDTable_internal_bmi2(void* dst, size_t dstSize, void const* cSrc,
+                    size_t cSrcSize, HUF_DTable const* DTable) {
+    return HUF_decompress4X2_usingDTable_internal_body(dst, dstSize, cSrc, cSrcSize, DTable);
+}
+#endif
+
+static
+size_t HUF_decompress4X2_usingDTable_internal_default(void* dst, size_t dstSize, void const* cSrc,
+                    size_t cSrcSize, HUF_DTable const* DTable) {
+    return HUF_decompress4X2_usingDTable_internal_body(dst, dstSize, cSrc, cSrcSize, DTable);
+}
+
+#if ZSTD_ENABLE_ASM_X86_64_BMI2
+
+HUF_ASM_DECL void HUF_decompress4X2_usingDTable_internal_fast_asm_loop(HUF_DecompressFastArgs* args) ZSTDLIB_HIDDEN;
+
+#endif
+
+static HUF_FAST_BMI2_ATTRS
+void HUF_decompress4X2_usingDTable_internal_fast_c_loop(HUF_DecompressFastArgs* args)
+{
+    U64 bits[4];
+    BYTE const* ip[4];
+    BYTE* op[4];
+    BYTE* oend[4];
+    HUF_DEltX2 const* const dtable = (HUF_DEltX2 const*)args->dt;
+    BYTE const* const ilowest = args->ilowest;
+
+    /* Copy the arguments to local registers. */
+    ZSTD_memcpy(&bits, &args->bits, sizeof(bits));
+    ZSTD_memcpy((void*)(&ip), &args->ip, sizeof(ip));
+    ZSTD_memcpy(&op, &args->op, sizeof(op));
+
+    oend[0] = op[1];
+    oend[1] = op[2];
+    oend[2] = op[3];
+    oend[3] = args->oend;
+
+    assert(MEM_isLittleEndian());
+    assert(!MEM_32bits());
+
+    for (;;) {
+        BYTE* olimit;
+        int stream;
+
+        /* Assert loop preconditions */
+#ifndef NDEBUG
+        for (stream = 0; stream < 4; ++stream) {
+            assert(op[stream] <= oend[stream]);
+            assert(ip[stream] >= ilowest);
+        }
+#endif
+        /* Compute olimit */
+        {
+            /* Each loop does 5 table lookups for each of the 4 streams.
+             * Each table lookup consumes up to 11 bits of input, and produces
+             * up to 2 bytes of output.
+             */
+            /* We can consume up to 7 bytes of input per iteration per stream.
+             * We also know that each input pointer is >= ip[0]. So we can run
+             * iters loops before running out of input.
+             */
+            size_t iters = (size_t)(ip[0] - ilowest) / 7;
+            /* Each iteration can produce up to 10 bytes of output per stream.
+             * Each output stream my advance at different rates. So take the
+             * minimum number of safe iterations among all the output streams.
+             */
+            for (stream = 0; stream < 4; ++stream) {
+                size_t const oiters = (size_t)(oend[stream] - op[stream]) / 10;
+                iters = MIN(iters, oiters);
+            }
+
+            /* Each iteration produces at least 5 output symbols. So until
+             * op[3] crosses olimit, we know we haven't executed iters
+             * iterations yet. This saves us maintaining an iters counter,
+             * at the expense of computing the remaining # of iterations
+             * more frequently.
+             */
+            olimit = op[3] + (iters * 5);
+
+            /* Exit the fast decoding loop once we reach the end. */
+            if (op[3] == olimit)
+                break;
+
+            /* Exit the decoding loop if any input pointer has crossed the
+             * previous one. This indicates corruption, and a precondition
+             * to our loop is that ip[i] >= ip[0].
+             */
+            for (stream = 1; stream < 4; ++stream) {
+                if (ip[stream] < ip[stream - 1])
+                    goto _out;
+            }
+        }
+
+#ifndef NDEBUG
+        for (stream = 1; stream < 4; ++stream) {
+            assert(ip[stream] >= ip[stream - 1]);
+        }
+#endif
+
+#define HUF_4X2_DECODE_SYMBOL(_stream, _decode3)                      \
+    do {                                                              \
+        if ((_decode3) || (_stream) != 3) {                           \
+            int const index = (int)(bits[(_stream)] >> 53);           \
+            HUF_DEltX2 const entry = dtable[index];                   \
+            MEM_write16(op[(_stream)], entry.sequence); \
+            bits[(_stream)] <<= (entry.nbBits) & 0x3F;                \
+            op[(_stream)] += (entry.length);                          \
+        }                                                             \
+    } while (0)
+
+#define HUF_4X2_RELOAD_STREAM(_stream)                                  \
+    do {                                                                \
+        HUF_4X2_DECODE_SYMBOL(3, 1);                                    \
+        {                                                               \
+            int const ctz = ZSTD_countTrailingZeros64(bits[(_stream)]); \
+            int const nbBits = ctz & 7;                                 \
+            int const nbBytes = ctz >> 3;                               \
+            ip[(_stream)] -= nbBytes;                                   \
+            bits[(_stream)] = MEM_read64(ip[(_stream)]) | 1;            \
+            bits[(_stream)] <<= nbBits;                                 \
+        }                                                               \
+    } while (0)
+
+        /* Manually unroll the loop because compilers don't consistently
+         * unroll the inner loops, which destroys performance.
+         */
+        do {
+            /* Decode 5 symbols from each of the first 3 streams.
+             * The final stream will be decoded during the reload phase
+             * to reduce register pressure.
+             */
+            HUF_4X_FOR_EACH_STREAM_WITH_VAR(HUF_4X2_DECODE_SYMBOL, 0);
+            HUF_4X_FOR_EACH_STREAM_WITH_VAR(HUF_4X2_DECODE_SYMBOL, 0);
+            HUF_4X_FOR_EACH_STREAM_WITH_VAR(HUF_4X2_DECODE_SYMBOL, 0);
+            HUF_4X_FOR_EACH_STREAM_WITH_VAR(HUF_4X2_DECODE_SYMBOL, 0);
+            HUF_4X_FOR_EACH_STREAM_WITH_VAR(HUF_4X2_DECODE_SYMBOL, 0);
+
+            /* Decode one symbol from the final stream */
+            HUF_4X2_DECODE_SYMBOL(3, 1);
+
+            /* Decode 4 symbols from the final stream & reload bitstreams.
+             * The final stream is reloaded last, meaning that all 5 symbols
+             * are decoded from the final stream before it is reloaded.
+             */
+            HUF_4X_FOR_EACH_STREAM(HUF_4X2_RELOAD_STREAM);
+        } while (op[3] < olimit);
+    }
+
+#undef HUF_4X2_DECODE_SYMBOL
+#undef HUF_4X2_RELOAD_STREAM
+
+_out:
+
+    /* Save the final values of each of the state variables back to args. */
+    ZSTD_memcpy(&args->bits, &bits, sizeof(bits));
+    ZSTD_memcpy((void*)(&args->ip), &ip, sizeof(ip));
+    ZSTD_memcpy(&args->op, &op, sizeof(op));
+}
+
+
+static HUF_FAST_BMI2_ATTRS size_t
+HUF_decompress4X2_usingDTable_internal_fast(
+          void* dst,  size_t dstSize,
+    const void* cSrc, size_t cSrcSize,
+    const HUF_DTable* DTable,
+    HUF_DecompressFastLoopFn loopFn) {
+    void const* dt = DTable + 1;
+    const BYTE* const ilowest = (const BYTE*)cSrc;
+    BYTE* const oend = ZSTD_maybeNullPtrAdd((BYTE*)dst, dstSize);
+    HUF_DecompressFastArgs args;
+    {
+        size_t const ret = HUF_DecompressFastArgs_init(&args, dst, dstSize, cSrc, cSrcSize, DTable);
+        FORWARD_IF_ERROR(ret, "Failed to init asm args");
+        if (ret == 0)
+            return 0;
+    }
+
+    assert(args.ip[0] >= args.ilowest);
+    loopFn(&args);
+
+    /* note : op4 already verified within main loop */
+    assert(args.ip[0] >= ilowest);
+    assert(args.ip[1] >= ilowest);
+    assert(args.ip[2] >= ilowest);
+    assert(args.ip[3] >= ilowest);
+    assert(args.op[3] <= oend);
+
+    assert(ilowest == args.ilowest);
+    assert(ilowest + 6 == args.iend[0]);
+    (void)ilowest;
+
+    /* finish bitStreams one by one */
+    {
+        size_t const segmentSize = (dstSize+3) / 4;
+        BYTE* segmentEnd = (BYTE*)dst;
+        int i;
+        for (i = 0; i < 4; ++i) {
+            BIT_DStream_t bit;
+            if (segmentSize <= (size_t)(oend - segmentEnd))
+                segmentEnd += segmentSize;
+            else
+                segmentEnd = oend;
+            FORWARD_IF_ERROR(HUF_initRemainingDStream(&bit, &args, i, segmentEnd), "corruption");
+            args.op[i] += HUF_decodeStreamX2(args.op[i], &bit, segmentEnd, (HUF_DEltX2 const*)dt, HUF_DECODER_FAST_TABLELOG);
+            if (args.op[i] != segmentEnd)
+                return ERROR(corruption_detected);
+        }
+    }
+
+    /* decoded size */
+    return dstSize;
+}
+
+static size_t HUF_decompress4X2_usingDTable_internal(void* dst, size_t dstSize, void const* cSrc,
+                    size_t cSrcSize, HUF_DTable const* DTable, int flags)
+{
+    HUF_DecompressUsingDTableFn fallbackFn = HUF_decompress4X2_usingDTable_internal_default;
+    HUF_DecompressFastLoopFn loopFn = HUF_decompress4X2_usingDTable_internal_fast_c_loop;
+
+#if DYNAMIC_BMI2
+    if (flags & HUF_flags_bmi2) {
+        fallbackFn = HUF_decompress4X2_usingDTable_internal_bmi2;
+# if ZSTD_ENABLE_ASM_X86_64_BMI2
+        if (!(flags & HUF_flags_disableAsm)) {
+            loopFn = HUF_decompress4X2_usingDTable_internal_fast_asm_loop;
+        }
+# endif
+    } else {
+        return fallbackFn(dst, dstSize, cSrc, cSrcSize, DTable);
+    }
+#endif
+
+#if ZSTD_ENABLE_ASM_X86_64_BMI2 && defined(__BMI2__)
+    if (!(flags & HUF_flags_disableAsm)) {
+        loopFn = HUF_decompress4X2_usingDTable_internal_fast_asm_loop;
+    }
+#endif
+
+    if (HUF_ENABLE_FAST_DECODE && !(flags & HUF_flags_disableFast)) {
+        size_t const ret = HUF_decompress4X2_usingDTable_internal_fast(dst, dstSize, cSrc, cSrcSize, DTable, loopFn);
+        if (ret != 0)
+            return ret;
+    }
+    return fallbackFn(dst, dstSize, cSrc, cSrcSize, DTable);
+}
+
+HUF_DGEN(HUF_decompress1X2_usingDTable_internal)
+
+size_t HUF_decompress1X2_DCtx_wksp(HUF_DTable* DCtx, void* dst, size_t dstSize,
+                                   const void* cSrc, size_t cSrcSize,
+                                   void* workSpace, size_t wkspSize, int flags)
+{
+    const BYTE* ip = (const BYTE*) cSrc;
+
+    size_t const hSize = HUF_readDTableX2_wksp(DCtx, cSrc, cSrcSize,
+                                               workSpace, wkspSize, flags);
+    if (HUF_isError(hSize)) return hSize;
+    if (hSize >= cSrcSize) return ERROR(srcSize_wrong);
+    ip += hSize; cSrcSize -= hSize;
+
+    return HUF_decompress1X2_usingDTable_internal(dst, dstSize, ip, cSrcSize, DCtx, flags);
+}
+
+static size_t HUF_decompress4X2_DCtx_wksp(HUF_DTable* dctx, void* dst, size_t dstSize,
+                                   const void* cSrc, size_t cSrcSize,
+                                   void* workSpace, size_t wkspSize, int flags)
+{
+    const BYTE* ip = (const BYTE*) cSrc;
+
+    size_t hSize = HUF_readDTableX2_wksp(dctx, cSrc, cSrcSize,
+                                         workSpace, wkspSize, flags);
+    if (HUF_isError(hSize)) return hSize;
+    if (hSize >= cSrcSize) return ERROR(srcSize_wrong);
+    ip += hSize; cSrcSize -= hSize;
+
+    return HUF_decompress4X2_usingDTable_internal(dst, dstSize, ip, cSrcSize, dctx, flags);
+}
+
+#endif /* HUF_FORCE_DECOMPRESS_X1 */
+
+
+/* ***********************************/
+/* Universal decompression selectors */
+/* ***********************************/
+
+
+#if !defined(HUF_FORCE_DECOMPRESS_X1) && !defined(HUF_FORCE_DECOMPRESS_X2)
+typedef struct { U32 tableTime; U32 decode256Time; } algo_time_t;
+static const algo_time_t algoTime[16 /* Quantization */][2 /* single, double */] =
+{
+    /* single, double, quad */
+    {{0,0}, {1,1}},  /* Q==0 : impossible */
+    {{0,0}, {1,1}},  /* Q==1 : impossible */
+    {{ 150,216}, { 381,119}},   /* Q == 2 : 12-18% */
+    {{ 170,205}, { 514,112}},   /* Q == 3 : 18-25% */
+    {{ 177,199}, { 539,110}},   /* Q == 4 : 25-32% */
+    {{ 197,194}, { 644,107}},   /* Q == 5 : 32-38% */
+    {{ 221,192}, { 735,107}},   /* Q == 6 : 38-44% */
+    {{ 256,189}, { 881,106}},   /* Q == 7 : 44-50% */
+    {{ 359,188}, {1167,109}},   /* Q == 8 : 50-56% */
+    {{ 582,187}, {1570,114}},   /* Q == 9 : 56-62% */
+    {{ 688,187}, {1712,122}},   /* Q ==10 : 62-69% */
+    {{ 825,186}, {1965,136}},   /* Q ==11 : 69-75% */
+    {{ 976,185}, {2131,150}},   /* Q ==12 : 75-81% */
+    {{1180,186}, {2070,175}},   /* Q ==13 : 81-87% */
+    {{1377,185}, {1731,202}},   /* Q ==14 : 87-93% */
+    {{1412,185}, {1695,202}},   /* Q ==15 : 93-99% */
+};
+#endif
+
+/** HUF_selectDecoder() :
+ *  Tells which decoder is likely to decode faster,
+ *  based on a set of pre-computed metrics.
+ * @return : 0==HUF_decompress4X1, 1==HUF_decompress4X2 .
+ *  Assumption : 0 < dstSize <= 128 KB */
+U32 HUF_selectDecoder (size_t dstSize, size_t cSrcSize)
+{
+    assert(dstSize > 0);
+    assert(dstSize <= 128*1024);
+#if defined(HUF_FORCE_DECOMPRESS_X1)
+    (void)dstSize;
+    (void)cSrcSize;
+    return 0;
+#elif defined(HUF_FORCE_DECOMPRESS_X2)
+    (void)dstSize;
+    (void)cSrcSize;
+    return 1;
+#else
+    /* decoder timing evaluation */
+    {   U32 const Q = (cSrcSize >= dstSize) ? 15 : (U32)(cSrcSize * 16 / dstSize);   /* Q < 16 */
+        U32 const D256 = (U32)(dstSize >> 8);
+        U32 const DTime0 = algoTime[Q][0].tableTime + (algoTime[Q][0].decode256Time * D256);
+        U32 DTime1 = algoTime[Q][1].tableTime + (algoTime[Q][1].decode256Time * D256);
+        DTime1 += DTime1 >> 5;  /* small advantage to algorithm using less memory, to reduce cache eviction */
+        return DTime1 < DTime0;
+    }
+#endif
+}
+
+size_t HUF_decompress1X_DCtx_wksp(HUF_DTable* dctx, void* dst, size_t dstSize,
+                                  const void* cSrc, size_t cSrcSize,
+                                  void* workSpace, size_t wkspSize, int flags)
+{
+    /* validation checks */
+    if (dstSize == 0) return ERROR(dstSize_tooSmall);
+    if (cSrcSize > dstSize) return ERROR(corruption_detected);   /* invalid */
+    if (cSrcSize == dstSize) { ZSTD_memcpy(dst, cSrc, dstSize); return dstSize; }   /* not compressed */
+    if (cSrcSize == 1) { ZSTD_memset(dst, *(const BYTE*)cSrc, dstSize); return dstSize; }   /* RLE */
+
+    {   U32 const algoNb = HUF_selectDecoder(dstSize, cSrcSize);
+#if defined(HUF_FORCE_DECOMPRESS_X1)
+        (void)algoNb;
+        assert(algoNb == 0);
+        return HUF_decompress1X1_DCtx_wksp(dctx, dst, dstSize, cSrc,
+                                cSrcSize, workSpace, wkspSize, flags);
+#elif defined(HUF_FORCE_DECOMPRESS_X2)
+        (void)algoNb;
+        assert(algoNb == 1);
+        return HUF_decompress1X2_DCtx_wksp(dctx, dst, dstSize, cSrc,
+                                cSrcSize, workSpace, wkspSize, flags);
+#else
+        return algoNb ? HUF_decompress1X2_DCtx_wksp(dctx, dst, dstSize, cSrc,
+                                cSrcSize, workSpace, wkspSize, flags):
+                        HUF_decompress1X1_DCtx_wksp(dctx, dst, dstSize, cSrc,
+                                cSrcSize, workSpace, wkspSize, flags);
+#endif
+    }
+}
+
+
+size_t HUF_decompress1X_usingDTable(void* dst, size_t maxDstSize, const void* cSrc, size_t cSrcSize, const HUF_DTable* DTable, int flags)
+{
+    DTableDesc const dtd = HUF_getDTableDesc(DTable);
+#if defined(HUF_FORCE_DECOMPRESS_X1)
+    (void)dtd;
+    assert(dtd.tableType == 0);
+    return HUF_decompress1X1_usingDTable_internal(dst, maxDstSize, cSrc, cSrcSize, DTable, flags);
+#elif defined(HUF_FORCE_DECOMPRESS_X2)
+    (void)dtd;
+    assert(dtd.tableType == 1);
+    return HUF_decompress1X2_usingDTable_internal(dst, maxDstSize, cSrc, cSrcSize, DTable, flags);
+#else
+    return dtd.tableType ? HUF_decompress1X2_usingDTable_internal(dst, maxDstSize, cSrc, cSrcSize, DTable, flags) :
+                           HUF_decompress1X1_usingDTable_internal(dst, maxDstSize, cSrc, cSrcSize, DTable, flags);
+#endif
+}
+
+#ifndef HUF_FORCE_DECOMPRESS_X2
+size_t HUF_decompress1X1_DCtx_wksp(HUF_DTable* dctx, void* dst, size_t dstSize, const void* cSrc, size_t cSrcSize, void* workSpace, size_t wkspSize, int flags)
+{
+    const BYTE* ip = (const BYTE*) cSrc;
+
+    size_t const hSize = HUF_readDTableX1_wksp(dctx, cSrc, cSrcSize, workSpace, wkspSize, flags);
+    if (HUF_isError(hSize)) return hSize;
+    if (hSize >= cSrcSize) return ERROR(srcSize_wrong);
+    ip += hSize; cSrcSize -= hSize;
+
+    return HUF_decompress1X1_usingDTable_internal(dst, dstSize, ip, cSrcSize, dctx, flags);
+}
+#endif
+
+size_t HUF_decompress4X_usingDTable(void* dst, size_t maxDstSize, const void* cSrc, size_t cSrcSize, const HUF_DTable* DTable, int flags)
+{
+    DTableDesc const dtd = HUF_getDTableDesc(DTable);
+#if defined(HUF_FORCE_DECOMPRESS_X1)
+    (void)dtd;
+    assert(dtd.tableType == 0);
+    return HUF_decompress4X1_usingDTable_internal(dst, maxDstSize, cSrc, cSrcSize, DTable, flags);
+#elif defined(HUF_FORCE_DECOMPRESS_X2)
+    (void)dtd;
+    assert(dtd.tableType == 1);
+    return HUF_decompress4X2_usingDTable_internal(dst, maxDstSize, cSrc, cSrcSize, DTable, flags);
+#else
+    return dtd.tableType ? HUF_decompress4X2_usingDTable_internal(dst, maxDstSize, cSrc, cSrcSize, DTable, flags) :
+                           HUF_decompress4X1_usingDTable_internal(dst, maxDstSize, cSrc, cSrcSize, DTable, flags);
+#endif
+}
+
+size_t HUF_decompress4X_hufOnly_wksp(HUF_DTable* dctx, void* dst, size_t dstSize, const void* cSrc, size_t cSrcSize, void* workSpace, size_t wkspSize, int flags)
+{
+    /* validation checks */
+    if (dstSize == 0) return ERROR(dstSize_tooSmall);
+    if (cSrcSize == 0) return ERROR(corruption_detected);
+
+    {   U32 const algoNb = HUF_selectDecoder(dstSize, cSrcSize);
+#if defined(HUF_FORCE_DECOMPRESS_X1)
+        (void)algoNb;
+        assert(algoNb == 0);
+        return HUF_decompress4X1_DCtx_wksp(dctx, dst, dstSize, cSrc, cSrcSize, workSpace, wkspSize, flags);
+#elif defined(HUF_FORCE_DECOMPRESS_X2)
+        (void)algoNb;
+        assert(algoNb == 1);
+        return HUF_decompress4X2_DCtx_wksp(dctx, dst, dstSize, cSrc, cSrcSize, workSpace, wkspSize, flags);
+#else
+        return algoNb ? HUF_decompress4X2_DCtx_wksp(dctx, dst, dstSize, cSrc, cSrcSize, workSpace, wkspSize, flags) :
+                        HUF_decompress4X1_DCtx_wksp(dctx, dst, dstSize, cSrc, cSrcSize, workSpace, wkspSize, flags);
+#endif
+    }
+}
diff --git a/src/commonlib/bsd/zstd/decompress/zstd_ddict.c b/src/commonlib/bsd/zstd/decompress/zstd_ddict.c
new file mode 100644
index 0000000000..d1ec182f4c
--- /dev/null
+++ b/src/commonlib/bsd/zstd/decompress/zstd_ddict.c
@@ -0,0 +1,246 @@
+/* SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0-only */
+
+/*
+ * Copyright (c) Meta Platforms, Inc. and affiliates.
+ * All rights reserved.
+ *
+ * This source code is licensed under both the BSD-style license (found in the
+ * LICENSE file in the root directory of this source tree) and the GPLv2 (found
+ * in the COPYING file in the root directory of this source tree).
+ * You may select, at your option, one of the above-listed licenses.
+ */
+
+/* zstd_ddict.c :
+ * concentrates all logic that needs to know the internals of ZSTD_DDict object */
+
+/*-*******************************************************
+*  Dependencies
+*********************************************************/
+#include "../common/allocations.h"  /* ZSTD_customMalloc, ZSTD_customFree */
+#include "../common/zstd_deps.h"   /* ZSTD_memcpy, ZSTD_memmove, ZSTD_memset */
+#include "../common/cpu.h"         /* bmi2 */
+#include "../common/mem.h"         /* low level memory routines */
+#define FSE_STATIC_LINKING_ONLY
+#include "../common/fse.h"
+#include "../common/huf.h"
+#include "zstd_decompress_internal.h"
+#include "zstd_ddict.h"
+
+#if defined(ZSTD_LEGACY_SUPPORT) && (ZSTD_LEGACY_SUPPORT>=1)
+#  include "../legacy/zstd_legacy.h"
+#endif
+
+
+
+/*-*******************************************************
+*  Types
+*********************************************************/
+struct ZSTD_DDict_s {
+    void* dictBuffer;
+    const void* dictContent;
+    size_t dictSize;
+    ZSTD_entropyDTables_t entropy;
+    U32 dictID;
+    U32 entropyPresent;
+    ZSTD_customMem cMem;
+};  /* typedef'd to ZSTD_DDict within "zstd.h" */
+
+const void* ZSTD_DDict_dictContent(const ZSTD_DDict* ddict)
+{
+    assert(ddict != NULL);
+    return ddict->dictContent;
+}
+
+size_t ZSTD_DDict_dictSize(const ZSTD_DDict* ddict)
+{
+    assert(ddict != NULL);
+    return ddict->dictSize;
+}
+
+void ZSTD_copyDDictParameters(ZSTD_DCtx* dctx, const ZSTD_DDict* ddict)
+{
+    DEBUGLOG(4, "ZSTD_copyDDictParameters");
+    assert(dctx != NULL);
+    assert(ddict != NULL);
+    dctx->dictID = ddict->dictID;
+    dctx->prefixStart = ddict->dictContent;
+    dctx->virtualStart = ddict->dictContent;
+    dctx->dictEnd = (const BYTE*)ddict->dictContent + ddict->dictSize;
+    dctx->previousDstEnd = dctx->dictEnd;
+#ifdef FUZZING_BUILD_MODE_UNSAFE_FOR_PRODUCTION
+    dctx->dictContentBeginForFuzzing = dctx->prefixStart;
+    dctx->dictContentEndForFuzzing = dctx->previousDstEnd;
+#endif
+    if (ddict->entropyPresent) {
+        dctx->litEntropy = 1;
+        dctx->fseEntropy = 1;
+        dctx->LLTptr = ddict->entropy.LLTable;
+        dctx->MLTptr = ddict->entropy.MLTable;
+        dctx->OFTptr = ddict->entropy.OFTable;
+        dctx->HUFptr = ddict->entropy.hufTable;
+        dctx->entropy.rep[0] = ddict->entropy.rep[0];
+        dctx->entropy.rep[1] = ddict->entropy.rep[1];
+        dctx->entropy.rep[2] = ddict->entropy.rep[2];
+    } else {
+        dctx->litEntropy = 0;
+        dctx->fseEntropy = 0;
+    }
+}
+
+
+static size_t
+ZSTD_loadEntropy_intoDDict(ZSTD_DDict* ddict,
+                           ZSTD_dictContentType_e dictContentType)
+{
+    ddict->dictID = 0;
+    ddict->entropyPresent = 0;
+    if (dictContentType == ZSTD_dct_rawContent) return 0;
+
+    if (ddict->dictSize < 8) {
+        if (dictContentType == ZSTD_dct_fullDict)
+            return ERROR(dictionary_corrupted);   /* only accept specified dictionaries */
+        return 0;   /* pure content mode */
+    }
+    {   U32 const magic = MEM_readLE32(ddict->dictContent);
+        if (magic != ZSTD_MAGIC_DICTIONARY) {
+            if (dictContentType == ZSTD_dct_fullDict)
+                return ERROR(dictionary_corrupted);   /* only accept specified dictionaries */
+            return 0;   /* pure content mode */
+        }
+    }
+    ddict->dictID = MEM_readLE32((const char*)ddict->dictContent + ZSTD_FRAMEIDSIZE);
+
+    /* load entropy tables */
+    RETURN_ERROR_IF(ZSTD_isError(ZSTD_loadDEntropy(
+            &ddict->entropy, ddict->dictContent, ddict->dictSize)),
+        dictionary_corrupted, "");
+    ddict->entropyPresent = 1;
+    return 0;
+}
+
+
+static size_t ZSTD_initDDict_internal(ZSTD_DDict* ddict,
+                                      const void* dict, size_t dictSize,
+                                      ZSTD_dictLoadMethod_e dictLoadMethod,
+                                      ZSTD_dictContentType_e dictContentType)
+{
+    if ((dictLoadMethod == ZSTD_dlm_byRef) || (!dict) || (!dictSize)) {
+        ddict->dictBuffer = NULL;
+        ddict->dictContent = dict;
+        if (!dict) dictSize = 0;
+    } else {
+        void* const internalBuffer = ZSTD_customMalloc(dictSize, ddict->cMem);
+        ddict->dictBuffer = internalBuffer;
+        ddict->dictContent = internalBuffer;
+        if (!internalBuffer) return ERROR(memory_allocation);
+        ZSTD_memcpy(internalBuffer, dict, dictSize);
+    }
+    ddict->dictSize = dictSize;
+    ddict->entropy.hufTable[0] = (HUF_DTable)((ZSTD_HUFFDTABLE_CAPACITY_LOG)*0x1000001);  /* cover both little and big endian */
+
+    /* parse dictionary content */
+    FORWARD_IF_ERROR( ZSTD_loadEntropy_intoDDict(ddict, dictContentType) , "");
+
+    return 0;
+}
+
+ZSTD_DDict* ZSTD_createDDict_advanced(const void* dict, size_t dictSize,
+                                      ZSTD_dictLoadMethod_e dictLoadMethod,
+                                      ZSTD_dictContentType_e dictContentType,
+                                      ZSTD_customMem customMem)
+{
+    if ((!customMem.customAlloc) ^ (!customMem.customFree)) return NULL;
+
+    {   ZSTD_DDict* const ddict = (ZSTD_DDict*) ZSTD_customMalloc(sizeof(ZSTD_DDict), customMem);
+        if (ddict == NULL) return NULL;
+        ddict->cMem = customMem;
+        {   size_t const initResult = ZSTD_initDDict_internal(ddict,
+                                            dict, dictSize,
+                                            dictLoadMethod, dictContentType);
+            if (ZSTD_isError(initResult)) {
+                ZSTD_freeDDict(ddict);
+                return NULL;
+        }   }
+        return ddict;
+    }
+}
+
+/*! ZSTD_createDDict() :
+*   Create a digested dictionary, to start decompression without startup delay.
+*   `dict` content is copied inside DDict.
+*   Consequently, `dict` can be released after `ZSTD_DDict` creation */
+ZSTD_DDict* ZSTD_createDDict(const void* dict, size_t dictSize)
+{
+    ZSTD_customMem const allocator = { NULL, NULL, NULL };
+    return ZSTD_createDDict_advanced(dict, dictSize, ZSTD_dlm_byCopy, ZSTD_dct_auto, allocator);
+}
+
+/*! ZSTD_createDDict_byReference() :
+ *  Create a digested dictionary, to start decompression without startup delay.
+ *  Dictionary content is simply referenced, it will be accessed during decompression.
+ *  Warning : dictBuffer must outlive DDict (DDict must be freed before dictBuffer) */
+ZSTD_DDict* ZSTD_createDDict_byReference(const void* dictBuffer, size_t dictSize)
+{
+    ZSTD_customMem const allocator = { NULL, NULL, NULL };
+    return ZSTD_createDDict_advanced(dictBuffer, dictSize, ZSTD_dlm_byRef, ZSTD_dct_auto, allocator);
+}
+
+
+const ZSTD_DDict* ZSTD_initStaticDDict(
+                                void* sBuffer, size_t sBufferSize,
+                                const void* dict, size_t dictSize,
+                                ZSTD_dictLoadMethod_e dictLoadMethod,
+                                ZSTD_dictContentType_e dictContentType)
+{
+    size_t const neededSpace = sizeof(ZSTD_DDict)
+                             + (dictLoadMethod == ZSTD_dlm_byRef ? 0 : dictSize);
+    ZSTD_DDict* const ddict = (ZSTD_DDict*)sBuffer;
+    assert(sBuffer != NULL);
+    assert(dict != NULL);
+    if ((size_t)sBuffer & 7) return NULL;   /* 8-aligned */
+    if (sBufferSize < neededSpace) return NULL;
+    if (dictLoadMethod == ZSTD_dlm_byCopy) {
+        ZSTD_memcpy(ddict+1, dict, dictSize);  /* local copy */
+        dict = ddict+1;
+    }
+    if (ZSTD_isError( ZSTD_initDDict_internal(ddict,
+                                              dict, dictSize,
+                                              ZSTD_dlm_byRef, dictContentType) ))
+        return NULL;
+    return ddict;
+}
+
+
+size_t ZSTD_freeDDict(ZSTD_DDict* ddict)
+{
+    if (ddict==NULL) return 0;   /* support free on NULL */
+    {   ZSTD_customMem const cMem = ddict->cMem;
+        ZSTD_customFree(ddict->dictBuffer, cMem);
+        ZSTD_customFree(ddict, cMem);
+        return 0;
+    }
+}
+
+/*! ZSTD_estimateDDictSize() :
+ *  Estimate amount of memory that will be needed to create a dictionary for decompression.
+ *  Note : dictionary created by reference using ZSTD_dlm_byRef are smaller */
+size_t ZSTD_estimateDDictSize(size_t dictSize, ZSTD_dictLoadMethod_e dictLoadMethod)
+{
+    return sizeof(ZSTD_DDict) + (dictLoadMethod == ZSTD_dlm_byRef ? 0 : dictSize);
+}
+
+size_t ZSTD_sizeof_DDict(const ZSTD_DDict* ddict)
+{
+    if (ddict==NULL) return 0;   /* support sizeof on NULL */
+    return sizeof(*ddict) + (ddict->dictBuffer ? ddict->dictSize : 0) ;
+}
+
+/*! ZSTD_getDictID_fromDDict() :
+ *  Provides the dictID of the dictionary loaded into `ddict`.
+ *  If @return == 0, the dictionary is not conformant to Zstandard specification, or empty.
+ *  Non-conformant dictionaries can still be loaded, but as content-only dictionaries. */
+unsigned ZSTD_getDictID_fromDDict(const ZSTD_DDict* ddict)
+{
+    if (ddict==NULL) return 0;
+    return ddict->dictID;
+}
diff --git a/src/commonlib/bsd/zstd/decompress/zstd_ddict.h b/src/commonlib/bsd/zstd/decompress/zstd_ddict.h
new file mode 100644
index 0000000000..ef8000417a
--- /dev/null
+++ b/src/commonlib/bsd/zstd/decompress/zstd_ddict.h
@@ -0,0 +1,46 @@
+/* SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0-only */
+
+/*
+ * Copyright (c) Meta Platforms, Inc. and affiliates.
+ * All rights reserved.
+ *
+ * This source code is licensed under both the BSD-style license (found in the
+ * LICENSE file in the root directory of this source tree) and the GPLv2 (found
+ * in the COPYING file in the root directory of this source tree).
+ * You may select, at your option, one of the above-listed licenses.
+ */
+
+
+#ifndef ZSTD_DDICT_H
+#define ZSTD_DDICT_H
+
+/*-*******************************************************
+ *  Dependencies
+ *********************************************************/
+#include "../common/zstd_deps.h"   /* size_t */
+#include "../zstd.h"     /* ZSTD_DDict, and several public functions */
+
+
+/*-*******************************************************
+ *  Interface
+ *********************************************************/
+
+/* note: several prototypes are already published in `zstd.h` :
+ * ZSTD_createDDict()
+ * ZSTD_createDDict_byReference()
+ * ZSTD_createDDict_advanced()
+ * ZSTD_freeDDict()
+ * ZSTD_initStaticDDict()
+ * ZSTD_sizeof_DDict()
+ * ZSTD_estimateDDictSize()
+ * ZSTD_getDictID_fromDict()
+ */
+
+const void* ZSTD_DDict_dictContent(const ZSTD_DDict* ddict);
+size_t ZSTD_DDict_dictSize(const ZSTD_DDict* ddict);
+
+void ZSTD_copyDDictParameters(ZSTD_DCtx* dctx, const ZSTD_DDict* ddict);
+
+
+
+#endif /* ZSTD_DDICT_H */
diff --git a/src/commonlib/bsd/zstd/decompress/zstd_decompress.c b/src/commonlib/bsd/zstd/decompress/zstd_decompress.c
new file mode 100644
index 0000000000..e24795d15e
--- /dev/null
+++ b/src/commonlib/bsd/zstd/decompress/zstd_decompress.c
@@ -0,0 +1,922 @@
+/* SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0-only */
+
+/*
+ * Copyright (c) Meta Platforms, Inc. and affiliates.
+ * All rights reserved.
+ *
+ * This source code is licensed under both the BSD-style license (found in the
+ * LICENSE file in the root directory of this source tree) and the GPLv2 (found
+ * in the COPYING file in the root directory of this source tree).
+ * You may select, at your option, one of the above-listed licenses.
+ */
+
+
+/* ***************************************************************
+*  Tuning parameters
+*****************************************************************/
+
+/*!
+*  LEGACY_SUPPORT :
+*  if set to 1+, ZSTD_decompress() can decode older formats (v0.1+)
+*/
+#ifndef ZSTD_LEGACY_SUPPORT
+#  define ZSTD_LEGACY_SUPPORT 0
+#endif
+
+/*!
+ *  MAXWINDOWSIZE_DEFAULT :
+ *  maximum window size accepted by DStream __by default__.
+ *  Frames requiring more memory will be rejected.
+ *  It's possible to set a different limit using ZSTD_DCtx_setMaxWindowSize().
+ */
+#ifndef ZSTD_MAXWINDOWSIZE_DEFAULT
+#  define ZSTD_MAXWINDOWSIZE_DEFAULT (((U32)1 << ZSTD_WINDOWLOG_LIMIT_DEFAULT) + 1)
+#endif
+
+/*!
+ *  NO_FORWARD_PROGRESS_MAX :
+ *  maximum allowed nb of calls to ZSTD_decompressStream()
+ *  without any forward progress
+ *  (defined as: no byte read from input, and no byte flushed to output)
+ *  before triggering an error.
+ */
+#ifndef ZSTD_NO_FORWARD_PROGRESS_MAX
+#  define ZSTD_NO_FORWARD_PROGRESS_MAX 16
+#endif
+
+
+/*-*******************************************************
+*  Dependencies
+*********************************************************/
+#include "../common/zstd_deps.h"   /* ZSTD_memcpy, ZSTD_memmove, ZSTD_memset */
+#include "../common/allocations.h"  /* ZSTD_customMalloc, ZSTD_customCalloc, ZSTD_customFree */
+#include "../common/error_private.h"
+#include "../common/zstd_internal.h"  /* blockProperties_t */
+#include "../common/mem.h"         /* low level memory routines */
+#include "../common/zstd_bits.h"  /* ZSTD_highbit32 */
+#define FSE_STATIC_LINKING_ONLY
+#include "../common/fse.h"
+#include "../common/huf.h"
+#include <commonlib/bsd/xxhash.h>
+#include "zstd_decompress_internal.h"   /* ZSTD_DCtx */
+#include "zstd_ddict.h"  /* ZSTD_DDictDictContent */
+#include "zstd_decompress_block.h"   /* ZSTD_decompressBlock_internal */
+
+#if defined(ZSTD_LEGACY_SUPPORT) && (ZSTD_LEGACY_SUPPORT>=1)
+#  include "../legacy/zstd_legacy.h"
+#endif
+
+/*-*************************************************************
+*   Context management
+***************************************************************/
+size_t ZSTD_sizeof_DCtx (const ZSTD_DCtx* dctx)
+{
+    if (dctx==NULL) return 0;   /* support sizeof NULL */
+    return sizeof(*dctx)
+           + dctx->inBuffSize + dctx->outBuffSize;
+}
+
+size_t ZSTD_estimateDCtxSize(void) { return sizeof(ZSTD_DCtx); }
+
+static size_t ZSTD_startingInputLength(ZSTD_format_e format)
+{
+    size_t const startingInputLength = ZSTD_FRAMEHEADERSIZE_PREFIX(format);
+    /* only supports formats ZSTD_f_zstd1 and ZSTD_f_zstd1_magicless */
+    assert( (format == ZSTD_f_zstd1) || (format == ZSTD_f_zstd1_magicless) );
+    return startingInputLength;
+}
+
+static void ZSTD_DCtx_resetParameters(ZSTD_DCtx* dctx)
+{
+    assert(dctx->streamStage == zdss_init);
+    dctx->format = ZSTD_f_zstd1;
+    dctx->maxWindowSize = ZSTD_MAXWINDOWSIZE_DEFAULT;
+    dctx->outBufferMode = ZSTD_bm_buffered;
+    dctx->forceIgnoreChecksum = ZSTD_d_validateChecksum;
+    dctx->refMultipleDDicts = ZSTD_rmd_refSingleDDict;
+    dctx->disableHufAsm = 0;
+    dctx->maxBlockSizeParam = 0;
+}
+
+static void ZSTD_initDCtx_internal(ZSTD_DCtx* dctx)
+{
+    dctx->staticSize  = 0;
+    dctx->ddict       = NULL;
+    dctx->dictEnd     = NULL;
+    dctx->ddictIsCold = 0;
+    dctx->dictUses = ZSTD_dont_use;
+    dctx->inBuff      = NULL;
+    dctx->inBuffSize  = 0;
+    dctx->outBuffSize = 0;
+    dctx->streamStage = zdss_init;
+#if defined(ZSTD_LEGACY_SUPPORT) && (ZSTD_LEGACY_SUPPORT>=1)
+    dctx->legacyContext = NULL;
+    dctx->previousLegacyVersion = 0;
+#endif
+    dctx->noForwardProgress = 0;
+    dctx->oversizedDuration = 0;
+    dctx->isFrameDecompression = 1;
+#if DYNAMIC_BMI2
+    dctx->bmi2 = ZSTD_cpuSupportsBmi2();
+#endif
+    ZSTD_DCtx_resetParameters(dctx);
+#ifdef FUZZING_BUILD_MODE_UNSAFE_FOR_PRODUCTION
+    dctx->dictContentEndForFuzzing = NULL;
+#endif
+}
+
+ZSTD_DCtx* ZSTD_initStaticDCtx(void *workspace, size_t workspaceSize)
+{
+    ZSTD_DCtx* const dctx = (ZSTD_DCtx*) workspace;
+
+    if ((size_t)workspace & 7) return NULL;  /* 8-aligned */
+    if (workspaceSize < sizeof(ZSTD_DCtx)) return NULL;  /* minimum size */
+
+    ZSTD_initDCtx_internal(dctx);
+    dctx->staticSize = workspaceSize;
+    dctx->inBuff = (char*)(dctx+1);
+    return dctx;
+}
+
+static ZSTD_DCtx* ZSTD_createDCtx_internal(ZSTD_customMem customMem) {
+    if ((!customMem.customAlloc) ^ (!customMem.customFree)) return NULL;
+
+    {   ZSTD_DCtx* const dctx = (ZSTD_DCtx*)ZSTD_customMalloc(sizeof(*dctx), customMem);
+        if (!dctx) return NULL;
+        dctx->customMem = customMem;
+        ZSTD_initDCtx_internal(dctx);
+        return dctx;
+    }
+}
+
+ZSTD_DCtx* ZSTD_createDCtx_advanced(ZSTD_customMem customMem)
+{
+    return ZSTD_createDCtx_internal(customMem);
+}
+
+ZSTD_DCtx* ZSTD_createDCtx(void)
+{
+    DEBUGLOG(3, "ZSTD_createDCtx");
+    return ZSTD_createDCtx_internal(ZSTD_defaultCMem);
+}
+
+static void ZSTD_clearDict(ZSTD_DCtx* dctx)
+{
+    dctx->ddict = NULL;
+    dctx->dictUses = ZSTD_dont_use;
+}
+
+size_t ZSTD_freeDCtx(ZSTD_DCtx* dctx)
+{
+    if (dctx==NULL) return 0;   /* support free on NULL */
+    RETURN_ERROR_IF(dctx->staticSize, memory_allocation, "not compatible with static DCtx");
+    {   ZSTD_customMem const cMem = dctx->customMem;
+        ZSTD_clearDict(dctx);
+        ZSTD_customFree(dctx->inBuff, cMem);
+        dctx->inBuff = NULL;
+#if defined(ZSTD_LEGACY_SUPPORT) && (ZSTD_LEGACY_SUPPORT >= 1)
+        if (dctx->legacyContext)
+            ZSTD_freeLegacyStreamContext(dctx->legacyContext, dctx->previousLegacyVersion);
+#endif
+        ZSTD_customFree(dctx, cMem);
+        return 0;
+    }
+}
+
+/* no longer useful */
+void ZSTD_copyDCtx(ZSTD_DCtx* dstDCtx, const ZSTD_DCtx* srcDCtx)
+{
+    size_t const toCopy = (size_t)((char*)(&dstDCtx->inBuff) - (char*)dstDCtx);
+    ZSTD_memcpy(dstDCtx, srcDCtx, toCopy);  /* no need to copy workspace */
+}
+
+
+/*-*************************************************************
+ *   Frame header decoding
+ ***************************************************************/
+
+/*! ZSTD_isFrame() :
+ *  Tells if the content of `buffer` starts with a valid Frame Identifier.
+ *  Note : Frame Identifier is 4 bytes. If `size < 4`, @return will always be 0.
+ *  Note 2 : Legacy Frame Identifiers are considered valid only if Legacy Support is enabled.
+ *  Note 3 : Skippable Frame Identifiers are considered valid. */
+unsigned ZSTD_isFrame(const void* buffer, size_t size)
+{
+    if (size < ZSTD_FRAMEIDSIZE) return 0;
+    {   U32 const magic = MEM_readLE32(buffer);
+        if (magic == ZSTD_MAGICNUMBER) return 1;
+        if ((magic & ZSTD_MAGIC_SKIPPABLE_MASK) == ZSTD_MAGIC_SKIPPABLE_START) return 1;
+    }
+#if defined(ZSTD_LEGACY_SUPPORT) && (ZSTD_LEGACY_SUPPORT >= 1)
+    if (ZSTD_isLegacy(buffer, size)) return 1;
+#endif
+    return 0;
+}
+
+/*! ZSTD_isSkippableFrame() :
+ *  Tells if the content of `buffer` starts with a valid Frame Identifier for a skippable frame.
+ *  Note : Frame Identifier is 4 bytes. If `size < 4`, @return will always be 0.
+ */
+unsigned ZSTD_isSkippableFrame(const void* buffer, size_t size)
+{
+    if (size < ZSTD_FRAMEIDSIZE) return 0;
+    {   U32 const magic = MEM_readLE32(buffer);
+        if ((magic & ZSTD_MAGIC_SKIPPABLE_MASK) == ZSTD_MAGIC_SKIPPABLE_START) return 1;
+    }
+    return 0;
+}
+
+/** ZSTD_frameHeaderSize_internal() :
+ *  srcSize must be large enough to reach header size fields.
+ *  note : only works for formats ZSTD_f_zstd1 and ZSTD_f_zstd1_magicless.
+ * @return : size of the Frame Header
+ *           or an error code, which can be tested with ZSTD_isError() */
+static size_t ZSTD_frameHeaderSize_internal(const void* src, size_t srcSize, ZSTD_format_e format)
+{
+    size_t const minInputSize = ZSTD_startingInputLength(format);
+    RETURN_ERROR_IF(srcSize < minInputSize, srcSize_wrong, "");
+
+    {   BYTE const fhd = ((const BYTE*)src)[minInputSize-1];
+        U32 const dictID= fhd & 3;
+        U32 const singleSegment = (fhd >> 5) & 1;
+        U32 const fcsId = fhd >> 6;
+        return minInputSize + !singleSegment
+             + ZSTD_did_fieldSize[dictID] + ZSTD_fcs_fieldSize[fcsId]
+             + (singleSegment && !fcsId);
+    }
+}
+
+/** ZSTD_frameHeaderSize() :
+ *  srcSize must be >= ZSTD_frameHeaderSize_prefix.
+ * @return : size of the Frame Header,
+ *           or an error code (if srcSize is too small) */
+size_t ZSTD_frameHeaderSize(const void* src, size_t srcSize)
+{
+    return ZSTD_frameHeaderSize_internal(src, srcSize, ZSTD_f_zstd1);
+}
+
+/** ZSTD_getFrameHeader_advanced() :
+ *  decode Frame Header, or require larger `srcSize`.
+ *  note : only works for formats ZSTD_f_zstd1 and ZSTD_f_zstd1_magicless
+ * @return : 0, `zfhPtr` is correctly filled,
+ *          >0, `srcSize` is too small, value is wanted `srcSize` amount,
+**           or an error code, which can be tested using ZSTD_isError() */
+size_t ZSTD_getFrameHeader_advanced(ZSTD_FrameHeader* zfhPtr, const void* src, size_t srcSize, ZSTD_format_e format)
+{
+    const BYTE* ip = (const BYTE*)src;
+    size_t const minInputSize = ZSTD_startingInputLength(format);
+
+    DEBUGLOG(5, "ZSTD_getFrameHeader_advanced: minInputSize = %zu, srcSize = %zu", minInputSize, srcSize);
+
+    if (srcSize > 0) {
+        /* note : technically could be considered an assert(), since it's an invalid entry */
+        RETURN_ERROR_IF(src==NULL, GENERIC, "invalid parameter : src==NULL, but srcSize>0");
+    }
+    if (srcSize < minInputSize) {
+        if (srcSize > 0 && format != ZSTD_f_zstd1_magicless) {
+            /* when receiving less than @minInputSize bytes,
+             * control these bytes at least correspond to a supported magic number
+             * in order to error out early if they don't.
+            **/
+            size_t const toCopy = MIN(4, srcSize);
+            unsigned char hbuf[4]; MEM_writeLE32(hbuf, ZSTD_MAGICNUMBER);
+            assert(src != NULL);
+            ZSTD_memcpy(hbuf, src, toCopy);
+            if ( MEM_readLE32(hbuf) != ZSTD_MAGICNUMBER ) {
+                /* not a zstd frame : let's check if it's a skippable frame */
+                MEM_writeLE32(hbuf, ZSTD_MAGIC_SKIPPABLE_START);
+                ZSTD_memcpy(hbuf, src, toCopy);
+                if ((MEM_readLE32(hbuf) & ZSTD_MAGIC_SKIPPABLE_MASK) != ZSTD_MAGIC_SKIPPABLE_START) {
+                    RETURN_ERROR(prefix_unknown,
+                                "first bytes don't correspond to any supported magic number");
+        }   }   }
+        return minInputSize;
+    }
+
+    ZSTD_memset(zfhPtr, 0, sizeof(*zfhPtr));   /* not strictly necessary, but static analyzers may not understand that zfhPtr will be read only if return value is zero, since they are 2 different signals */
+    if ( (format != ZSTD_f_zstd1_magicless)
+      && (MEM_readLE32(src) != ZSTD_MAGICNUMBER) ) {
+        if ((MEM_readLE32(src) & ZSTD_MAGIC_SKIPPABLE_MASK) == ZSTD_MAGIC_SKIPPABLE_START) {
+            /* skippable frame */
+            if (srcSize < ZSTD_SKIPPABLEHEADERSIZE)
+                return ZSTD_SKIPPABLEHEADERSIZE; /* magic number + frame length */
+            ZSTD_memset(zfhPtr, 0, sizeof(*zfhPtr));
+            zfhPtr->frameType = ZSTD_skippableFrame;
+            zfhPtr->dictID = MEM_readLE32(src) - ZSTD_MAGIC_SKIPPABLE_START;
+            zfhPtr->headerSize = ZSTD_SKIPPABLEHEADERSIZE;
+            zfhPtr->frameContentSize = MEM_readLE32((const char *)src + ZSTD_FRAMEIDSIZE);
+            return 0;
+        }
+        RETURN_ERROR(prefix_unknown, "");
+    }
+
+    /* ensure there is enough `srcSize` to fully read/decode frame header */
+    {   size_t const fhsize = ZSTD_frameHeaderSize_internal(src, srcSize, format);
+        if (srcSize < fhsize) return fhsize;
+        zfhPtr->headerSize = (U32)fhsize;
+    }
+
+    {   BYTE const fhdByte = ip[minInputSize-1];
+        size_t pos = minInputSize;
+        U32 const dictIDSizeCode = fhdByte&3;
+        U32 const checksumFlag = (fhdByte>>2)&1;
+        U32 const singleSegment = (fhdByte>>5)&1;
+        U32 const fcsID = fhdByte>>6;
+        U64 windowSize = 0;
+        U32 dictID = 0;
+        U64 frameContentSize = ZSTD_CONTENTSIZE_UNKNOWN;
+        RETURN_ERROR_IF((fhdByte & 0x08) != 0, frameParameter_unsupported,
+                        "reserved bits, must be zero");
+
+        if (!singleSegment) {
+            BYTE const wlByte = ip[pos++];
+            U32 const windowLog = (wlByte >> 3) + ZSTD_WINDOWLOG_ABSOLUTEMIN;
+            RETURN_ERROR_IF(windowLog > ZSTD_WINDOWLOG_MAX, frameParameter_windowTooLarge, "");
+            windowSize = (1ULL << windowLog);
+            windowSize += (windowSize >> 3) * (wlByte&7);
+        }
+        switch(dictIDSizeCode)
+        {
+            default:
+                assert(0);  /* impossible */
+                ZSTD_FALLTHROUGH;
+            case 0 : break;
+            case 1 : dictID = ip[pos]; pos++; break;
+            case 2 : dictID = MEM_readLE16(ip+pos); pos+=2; break;
+            case 3 : dictID = MEM_readLE32(ip+pos); pos+=4; break;
+        }
+        switch(fcsID)
+        {
+            default:
+                assert(0);  /* impossible */
+                ZSTD_FALLTHROUGH;
+            case 0 : if (singleSegment) frameContentSize = ip[pos]; break;
+            case 1 : frameContentSize = MEM_readLE16(ip+pos)+256; break;
+            case 2 : frameContentSize = MEM_readLE32(ip+pos); break;
+            case 3 : frameContentSize = MEM_readLE64(ip+pos); break;
+        }
+        if (singleSegment) windowSize = frameContentSize;
+
+        zfhPtr->frameType = ZSTD_frame;
+        zfhPtr->frameContentSize = frameContentSize;
+        zfhPtr->windowSize = windowSize;
+        zfhPtr->blockSizeMax = (unsigned) MIN(windowSize, ZSTD_BLOCKSIZE_MAX);
+        zfhPtr->dictID = dictID;
+        zfhPtr->checksumFlag = checksumFlag;
+    }
+    return 0;
+}
+
+/** ZSTD_getFrameHeader() :
+ *  decode Frame Header, or require larger `srcSize`.
+ *  note : this function does not consume input, it only reads it.
+ * @return : 0, `zfhPtr` is correctly filled,
+ *          >0, `srcSize` is too small, value is wanted `srcSize` amount,
+ *           or an error code, which can be tested using ZSTD_isError() */
+size_t ZSTD_getFrameHeader(ZSTD_FrameHeader* zfhPtr, const void* src, size_t srcSize)
+{
+    return ZSTD_getFrameHeader_advanced(zfhPtr, src, srcSize, ZSTD_f_zstd1);
+}
+
+static size_t readSkippableFrameSize(void const* src, size_t srcSize)
+{
+    size_t const skippableHeaderSize = ZSTD_SKIPPABLEHEADERSIZE;
+    U32 sizeU32;
+
+    RETURN_ERROR_IF(srcSize < ZSTD_SKIPPABLEHEADERSIZE, srcSize_wrong, "");
+
+    sizeU32 = MEM_readLE32((BYTE const*)src + ZSTD_FRAMEIDSIZE);
+    RETURN_ERROR_IF((U32)(sizeU32 + ZSTD_SKIPPABLEHEADERSIZE) < sizeU32,
+                    frameParameter_unsupported, "");
+    {   size_t const skippableSize = skippableHeaderSize + sizeU32;
+        RETURN_ERROR_IF(skippableSize > srcSize, srcSize_wrong, "");
+        return skippableSize;
+    }
+}
+
+/** ZSTD_decodeFrameHeader() :
+ * `headerSize` must be the size provided by ZSTD_frameHeaderSize().
+ * If multiple DDict references are enabled, also will choose the correct DDict to use.
+ * @return : 0 if success, or an error code, which can be tested using ZSTD_isError() */
+static size_t ZSTD_decodeFrameHeader(ZSTD_DCtx* dctx, const void* src, size_t headerSize)
+{
+    size_t const result = ZSTD_getFrameHeader_advanced(&(dctx->fParams), src, headerSize, dctx->format);
+    if (ZSTD_isError(result)) return result;    /* invalid header */
+    RETURN_ERROR_IF(result>0, srcSize_wrong, "headerSize too small");
+
+#ifndef FUZZING_BUILD_MODE_UNSAFE_FOR_PRODUCTION
+    /* Skip the dictID check in fuzzing mode, because it makes the search
+     * harder.
+     */
+    RETURN_ERROR_IF(dctx->fParams.dictID && (dctx->dictID != dctx->fParams.dictID),
+                    dictionary_wrong, "");
+#endif
+    dctx->validateChecksum = (dctx->fParams.checksumFlag && !dctx->forceIgnoreChecksum) ? 1 : 0;
+    if (dctx->validateChecksum) XXH64_reset(&dctx->xxhState, 0);
+    dctx->processedCSize += headerSize;
+    return 0;
+}
+
+static size_t ZSTD_copyRawBlock(void* dst, size_t dstCapacity,
+                          const void* src, size_t srcSize)
+{
+    DEBUGLOG(5, "ZSTD_copyRawBlock");
+    RETURN_ERROR_IF(srcSize > dstCapacity, dstSize_tooSmall, "");
+    if (dst == NULL) {
+        if (srcSize == 0) return 0;
+        RETURN_ERROR(dstBuffer_null, "");
+    }
+    ZSTD_memmove(dst, src, srcSize);
+    return srcSize;
+}
+
+static size_t ZSTD_setRleBlock(void* dst, size_t dstCapacity,
+                               BYTE b,
+                               size_t regenSize)
+{
+    RETURN_ERROR_IF(regenSize > dstCapacity, dstSize_tooSmall, "");
+    if (dst == NULL) {
+        if (regenSize == 0) return 0;
+        RETURN_ERROR(dstBuffer_null, "");
+    }
+    ZSTD_memset(dst, b, regenSize);
+    return regenSize;
+}
+
+static void ZSTD_DCtx_trace_end(ZSTD_DCtx const* dctx, U64 uncompressedSize, U64 compressedSize, int streaming)
+{
+#if ZSTD_TRACE
+    if (dctx->traceCtx && ZSTD_trace_decompress_end != NULL) {
+        ZSTD_Trace trace;
+        ZSTD_memset(&trace, 0, sizeof(trace));
+        trace.version = ZSTD_VERSION_NUMBER;
+        trace.streaming = streaming;
+        if (dctx->ddict) {
+            trace.dictionaryID = ZSTD_getDictID_fromDDict(dctx->ddict);
+            trace.dictionarySize = ZSTD_DDict_dictSize(dctx->ddict);
+            trace.dictionaryIsCold = dctx->ddictIsCold;
+        }
+        trace.uncompressedSize = (size_t)uncompressedSize;
+        trace.compressedSize = (size_t)compressedSize;
+        trace.dctx = dctx;
+        ZSTD_trace_decompress_end(dctx->traceCtx, &trace);
+    }
+#else
+    (void)dctx;
+    (void)uncompressedSize;
+    (void)compressedSize;
+    (void)streaming;
+#endif
+}
+
+/*! ZSTD_decompressFrame() :
+ * @dctx must be properly initialized
+ *  will update *srcPtr and *srcSizePtr,
+ *  to make *srcPtr progress by one frame. */
+static size_t ZSTD_decompressFrame(ZSTD_DCtx* dctx,
+                                   void* dst, size_t dstCapacity,
+                             const void** srcPtr, size_t *srcSizePtr)
+{
+    const BYTE* const istart = (const BYTE*)(*srcPtr);
+    const BYTE* ip = istart;
+    BYTE* const ostart = (BYTE*)dst;
+    BYTE* const oend = dstCapacity != 0 ? ostart + dstCapacity : ostart;
+    BYTE* op = ostart;
+    size_t remainingSrcSize = *srcSizePtr;
+
+    DEBUGLOG(4, "ZSTD_decompressFrame (srcSize:%i)", (int)*srcSizePtr);
+
+    /* check */
+    RETURN_ERROR_IF(
+        remainingSrcSize < ZSTD_FRAMEHEADERSIZE_MIN(dctx->format)+ZSTD_blockHeaderSize,
+        srcSize_wrong, "");
+
+    /* Frame Header */
+    {   size_t const frameHeaderSize = ZSTD_frameHeaderSize_internal(
+                ip, ZSTD_FRAMEHEADERSIZE_PREFIX(dctx->format), dctx->format);
+        if (ZSTD_isError(frameHeaderSize)) return frameHeaderSize;
+        RETURN_ERROR_IF(remainingSrcSize < frameHeaderSize+ZSTD_blockHeaderSize,
+                        srcSize_wrong, "");
+        FORWARD_IF_ERROR( ZSTD_decodeFrameHeader(dctx, ip, frameHeaderSize) , "");
+        ip += frameHeaderSize; remainingSrcSize -= frameHeaderSize;
+    }
+
+    /* Shrink the blockSizeMax if enabled */
+    if (dctx->maxBlockSizeParam != 0)
+        dctx->fParams.blockSizeMax = MIN(dctx->fParams.blockSizeMax, (unsigned)dctx->maxBlockSizeParam);
+
+    /* Loop on each block */
+    while (1) {
+        BYTE* oBlockEnd = oend;
+        size_t decodedSize;
+        blockProperties_t blockProperties;
+        size_t const cBlockSize = ZSTD_getcBlockSize(ip, remainingSrcSize, &blockProperties);
+        if (ZSTD_isError(cBlockSize)) return cBlockSize;
+
+        ip += ZSTD_blockHeaderSize;
+        remainingSrcSize -= ZSTD_blockHeaderSize;
+        RETURN_ERROR_IF(cBlockSize > remainingSrcSize, srcSize_wrong, "");
+
+        if (ip >= op && ip < oBlockEnd) {
+            /* We are decompressing in-place. Limit the output pointer so that we
+             * don't overwrite the block that we are currently reading. This will
+             * fail decompression if the input & output pointers aren't spaced
+             * far enough apart.
+             *
+             * This is important to set, even when the pointers are far enough
+             * apart, because ZSTD_decompressBlock_internal() can decide to store
+             * literals in the output buffer, after the block it is decompressing.
+             * Since we don't want anything to overwrite our input, we have to tell
+             * ZSTD_decompressBlock_internal to never write past ip.
+             *
+             * See ZSTD_allocateLiteralsBuffer() for reference.
+             */
+            oBlockEnd = op + (ip - op);
+        }
+
+        switch(blockProperties.blockType)
+        {
+        case bt_compressed:
+            assert(dctx->isFrameDecompression == 1);
+            decodedSize = ZSTD_decompressBlock_internal(dctx, op, (size_t)(oBlockEnd-op), ip, cBlockSize, not_streaming);
+            break;
+        case bt_raw :
+            /* Use oend instead of oBlockEnd because this function is safe to overlap. It uses memmove. */
+            decodedSize = ZSTD_copyRawBlock(op, (size_t)(oend-op), ip, cBlockSize);
+            break;
+        case bt_rle :
+            decodedSize = ZSTD_setRleBlock(op, (size_t)(oBlockEnd-op), *ip, blockProperties.origSize);
+            break;
+        case bt_reserved :
+        default:
+            RETURN_ERROR(corruption_detected, "invalid block type");
+        }
+        FORWARD_IF_ERROR(decodedSize, "Block decompression failure");
+        DEBUGLOG(5, "Decompressed block of dSize = %u", (unsigned)decodedSize);
+        if (dctx->validateChecksum) {
+            XXH64_update(&dctx->xxhState, op, decodedSize);
+        }
+        if (decodedSize) /* support dst = NULL,0 */ {
+            op += decodedSize;
+        }
+        assert(ip != NULL);
+        ip += cBlockSize;
+        remainingSrcSize -= cBlockSize;
+        if (blockProperties.lastBlock) break;
+    }
+
+    if (dctx->fParams.frameContentSize != ZSTD_CONTENTSIZE_UNKNOWN) {
+        RETURN_ERROR_IF((U64)(op-ostart) != dctx->fParams.frameContentSize,
+                        corruption_detected, "");
+    }
+    if (dctx->fParams.checksumFlag) { /* Frame content checksum verification */
+        RETURN_ERROR_IF(remainingSrcSize<4, checksum_wrong, "");
+        if (!dctx->forceIgnoreChecksum) {
+            U32 const checkCalc = (U32)XXH64_digest(&dctx->xxhState);
+            U32 checkRead;
+            checkRead = MEM_readLE32(ip);
+            RETURN_ERROR_IF(checkRead != checkCalc, checksum_wrong, "");
+        }
+        ip += 4;
+        remainingSrcSize -= 4;
+    }
+    ZSTD_DCtx_trace_end(dctx, (U64)(op-ostart), (U64)(ip-istart), /* streaming */ 0);
+    /* Allow caller to get size read */
+    DEBUGLOG(4, "ZSTD_decompressFrame: decompressed frame of size %i, consuming %i bytes of input", (int)(op-ostart), (int)(ip - (const BYTE*)*srcPtr));
+    *srcPtr = ip;
+    *srcSizePtr = remainingSrcSize;
+    return (size_t)(op-ostart);
+}
+
+static
+ZSTD_ALLOW_POINTER_OVERFLOW_ATTR
+size_t ZSTD_decompressMultiFrame(ZSTD_DCtx* dctx,
+                                        void* dst, size_t dstCapacity,
+                                  const void* src, size_t srcSize,
+                                  const void* dict, size_t dictSize,
+                                  const ZSTD_DDict* ddict)
+{
+    void* const dststart = dst;
+    int moreThan1Frame = 0;
+
+    DEBUGLOG(5, "ZSTD_decompressMultiFrame");
+    assert(dict==NULL || ddict==NULL);  /* either dict or ddict set, not both */
+
+    if (ddict) {
+        dict = ZSTD_DDict_dictContent(ddict);
+        dictSize = ZSTD_DDict_dictSize(ddict);
+    }
+
+    while (srcSize >= ZSTD_startingInputLength(dctx->format)) {
+
+#if defined(ZSTD_LEGACY_SUPPORT) && (ZSTD_LEGACY_SUPPORT >= 1)
+        if (dctx->format == ZSTD_f_zstd1 && ZSTD_isLegacy(src, srcSize)) {
+            size_t decodedSize;
+            size_t const frameSize = ZSTD_findFrameCompressedSizeLegacy(src, srcSize);
+            if (ZSTD_isError(frameSize)) return frameSize;
+            RETURN_ERROR_IF(dctx->staticSize, memory_allocation,
+                "legacy support is not compatible with static dctx");
+
+            decodedSize = ZSTD_decompressLegacy(dst, dstCapacity, src, frameSize, dict, dictSize);
+            if (ZSTD_isError(decodedSize)) return decodedSize;
+
+            {
+                unsigned long long const expectedSize = ZSTD_getFrameContentSize(src, srcSize);
+                RETURN_ERROR_IF(expectedSize == ZSTD_CONTENTSIZE_ERROR, corruption_detected, "Corrupted frame header!");
+                if (expectedSize != ZSTD_CONTENTSIZE_UNKNOWN) {
+                    RETURN_ERROR_IF(expectedSize != decodedSize, corruption_detected,
+                        "Frame header size does not match decoded size!");
+                }
+            }
+
+            assert(decodedSize <= dstCapacity);
+            dst = (BYTE*)dst + decodedSize;
+            dstCapacity -= decodedSize;
+
+            src = (const BYTE*)src + frameSize;
+            srcSize -= frameSize;
+
+            continue;
+        }
+#endif
+
+        if (dctx->format == ZSTD_f_zstd1 && srcSize >= 4) {
+            U32 const magicNumber = MEM_readLE32(src);
+            DEBUGLOG(5, "reading magic number %08X", (unsigned)magicNumber);
+            if ((magicNumber & ZSTD_MAGIC_SKIPPABLE_MASK) == ZSTD_MAGIC_SKIPPABLE_START) {
+                /* skippable frame detected : skip it */
+                size_t const skippableSize = readSkippableFrameSize(src, srcSize);
+                FORWARD_IF_ERROR(skippableSize, "invalid skippable frame");
+                assert(skippableSize <= srcSize);
+
+                src = (const BYTE *)src + skippableSize;
+                srcSize -= skippableSize;
+                continue; /* check next frame */
+        }   }
+
+        if (ddict) {
+            /* we were called from ZSTD_decompress_usingDDict */
+            FORWARD_IF_ERROR(ZSTD_decompressBegin_usingDDict(dctx, ddict), "");
+        } else {
+            /* this will initialize correctly with no dict if dict == NULL, so
+             * use this in all cases but ddict */
+            FORWARD_IF_ERROR(ZSTD_decompressBegin_usingDict(dctx, dict, dictSize), "");
+        }
+        ZSTD_checkContinuity(dctx, dst, dstCapacity);
+
+        {   const size_t res = ZSTD_decompressFrame(dctx, dst, dstCapacity,
+                                                    &src, &srcSize);
+            RETURN_ERROR_IF(
+                (ZSTD_getErrorCode(res) == ZSTD_error_prefix_unknown)
+             && (moreThan1Frame==1),
+                srcSize_wrong,
+                "At least one frame successfully completed, "
+                "but following bytes are garbage: "
+                "it's more likely to be a srcSize error, "
+                "specifying more input bytes than size of frame(s). "
+                "Note: one could be unlucky, it might be a corruption error instead, "
+                "happening right at the place where we expect zstd magic bytes. "
+                "But this is _much_ less likely than a srcSize field error.");
+            if (ZSTD_isError(res)) return res;
+            assert(res <= dstCapacity);
+            if (res != 0)
+                dst = (BYTE*)dst + res;
+            dstCapacity -= res;
+        }
+        moreThan1Frame = 1;
+    }  /* while (srcSize >= ZSTD_frameHeaderSize_prefix) */
+
+    RETURN_ERROR_IF(srcSize, srcSize_wrong, "input not entirely consumed");
+
+    return (size_t)((BYTE*)dst - (BYTE*)dststart);
+}
+
+size_t ZSTD_decompress_usingDict(ZSTD_DCtx* dctx,
+                                 void* dst, size_t dstCapacity,
+                           const void* src, size_t srcSize,
+                           const void* dict, size_t dictSize)
+{
+    return ZSTD_decompressMultiFrame(dctx, dst, dstCapacity, src, srcSize, dict, dictSize, NULL);
+}
+
+static ZSTD_DDict const* ZSTD_getDDict(ZSTD_DCtx* dctx)
+{
+    switch (dctx->dictUses) {
+    default:
+        assert(0 /* Impossible */);
+        ZSTD_FALLTHROUGH;
+    case ZSTD_dont_use:
+        ZSTD_clearDict(dctx);
+        return NULL;
+    case ZSTD_use_indefinitely:
+        return dctx->ddict;
+    case ZSTD_use_once:
+        dctx->dictUses = ZSTD_dont_use;
+        return dctx->ddict;
+    }
+}
+
+size_t ZSTD_decompressDCtx(ZSTD_DCtx* dctx, void* dst, size_t dstCapacity, const void* src, size_t srcSize)
+{
+    return ZSTD_decompress_usingDDict(dctx, dst, dstCapacity, src, srcSize, ZSTD_getDDict(dctx));
+}
+
+static size_t ZSTD_refDictContent(ZSTD_DCtx* dctx, const void* dict, size_t dictSize)
+{
+    dctx->dictEnd = dctx->previousDstEnd;
+    dctx->virtualStart = (const char*)dict - ((const char*)(dctx->previousDstEnd) - (const char*)(dctx->prefixStart));
+    dctx->prefixStart = dict;
+    dctx->previousDstEnd = (const char*)dict + dictSize;
+#ifdef FUZZING_BUILD_MODE_UNSAFE_FOR_PRODUCTION
+    dctx->dictContentBeginForFuzzing = dctx->prefixStart;
+    dctx->dictContentEndForFuzzing = dctx->previousDstEnd;
+#endif
+    return 0;
+}
+
+
+/*! ZSTD_loadDEntropy() :
+ *  dict : must point at beginning of a valid zstd dictionary.
+ * @return : size of entropy tables read */
+size_t
+ZSTD_loadDEntropy(ZSTD_entropyDTables_t* entropy,
+                  const void* const dict, size_t const dictSize)
+{
+    const BYTE* dictPtr = (const BYTE*)dict;
+    const BYTE* const dictEnd = dictPtr + dictSize;
+
+    RETURN_ERROR_IF(dictSize <= 8, dictionary_corrupted, "dict is too small");
+    assert(MEM_readLE32(dict) == ZSTD_MAGIC_DICTIONARY);   /* dict must be valid */
+    dictPtr += 8;   /* skip header = magic + dictID */
+
+    ZSTD_STATIC_ASSERT(offsetof(ZSTD_entropyDTables_t, OFTable) == offsetof(ZSTD_entropyDTables_t, LLTable) + sizeof(entropy->LLTable));
+    ZSTD_STATIC_ASSERT(offsetof(ZSTD_entropyDTables_t, MLTable) == offsetof(ZSTD_entropyDTables_t, OFTable) + sizeof(entropy->OFTable));
+    ZSTD_STATIC_ASSERT(sizeof(entropy->LLTable) + sizeof(entropy->OFTable) + sizeof(entropy->MLTable) >= HUF_DECOMPRESS_WORKSPACE_SIZE);
+    {   void* const workspace = &entropy->LLTable;   /* use fse tables as temporary workspace; implies fse tables are grouped together */
+        size_t const workspaceSize = sizeof(entropy->LLTable) + sizeof(entropy->OFTable) + sizeof(entropy->MLTable);
+#ifdef HUF_FORCE_DECOMPRESS_X1
+        /* in minimal huffman, we always use X1 variants */
+        size_t const hSize = HUF_readDTableX1_wksp(entropy->hufTable,
+                                                dictPtr, dictEnd - dictPtr,
+                                                workspace, workspaceSize, /* flags */ 0);
+#else
+        size_t const hSize = HUF_readDTableX2_wksp(entropy->hufTable,
+                                                dictPtr, (size_t)(dictEnd - dictPtr),
+                                                workspace, workspaceSize, /* flags */ 0);
+#endif
+        RETURN_ERROR_IF(HUF_isError(hSize), dictionary_corrupted, "");
+        dictPtr += hSize;
+    }
+
+    {   short offcodeNCount[MaxOff+1];
+        unsigned offcodeMaxValue = MaxOff, offcodeLog;
+        size_t const offcodeHeaderSize = FSE_readNCount(offcodeNCount, &offcodeMaxValue, &offcodeLog, dictPtr, (size_t)(dictEnd-dictPtr));
+        RETURN_ERROR_IF(FSE_isError(offcodeHeaderSize), dictionary_corrupted, "");
+        RETURN_ERROR_IF(offcodeMaxValue > MaxOff, dictionary_corrupted, "");
+        RETURN_ERROR_IF(offcodeLog > OffFSELog, dictionary_corrupted, "");
+        ZSTD_buildFSETable( entropy->OFTable,
+                            offcodeNCount, offcodeMaxValue,
+                            OF_base, OF_bits,
+                            offcodeLog,
+                            entropy->workspace, sizeof(entropy->workspace),
+                            /* bmi2 */0);
+        dictPtr += offcodeHeaderSize;
+    }
+
+    {   short matchlengthNCount[MaxML+1];
+        unsigned matchlengthMaxValue = MaxML, matchlengthLog;
+        size_t const matchlengthHeaderSize = FSE_readNCount(matchlengthNCount, &matchlengthMaxValue, &matchlengthLog, dictPtr, (size_t)(dictEnd-dictPtr));
+        RETURN_ERROR_IF(FSE_isError(matchlengthHeaderSize), dictionary_corrupted, "");
+        RETURN_ERROR_IF(matchlengthMaxValue > MaxML, dictionary_corrupted, "");
+        RETURN_ERROR_IF(matchlengthLog > MLFSELog, dictionary_corrupted, "");
+        ZSTD_buildFSETable( entropy->MLTable,
+                            matchlengthNCount, matchlengthMaxValue,
+                            ML_base, ML_bits,
+                            matchlengthLog,
+                            entropy->workspace, sizeof(entropy->workspace),
+                            /* bmi2 */ 0);
+        dictPtr += matchlengthHeaderSize;
+    }
+
+    {   short litlengthNCount[MaxLL+1];
+        unsigned litlengthMaxValue = MaxLL, litlengthLog;
+        size_t const litlengthHeaderSize = FSE_readNCount(litlengthNCount, &litlengthMaxValue, &litlengthLog, dictPtr, (size_t)(dictEnd-dictPtr));
+        RETURN_ERROR_IF(FSE_isError(litlengthHeaderSize), dictionary_corrupted, "");
+        RETURN_ERROR_IF(litlengthMaxValue > MaxLL, dictionary_corrupted, "");
+        RETURN_ERROR_IF(litlengthLog > LLFSELog, dictionary_corrupted, "");
+        ZSTD_buildFSETable( entropy->LLTable,
+                            litlengthNCount, litlengthMaxValue,
+                            LL_base, LL_bits,
+                            litlengthLog,
+                            entropy->workspace, sizeof(entropy->workspace),
+                            /* bmi2 */ 0);
+        dictPtr += litlengthHeaderSize;
+    }
+
+    RETURN_ERROR_IF(dictPtr+12 > dictEnd, dictionary_corrupted, "");
+    {   int i;
+        size_t const dictContentSize = (size_t)(dictEnd - (dictPtr+12));
+        for (i=0; i<3; i++) {
+            U32 const rep = MEM_readLE32(dictPtr); dictPtr += 4;
+            RETURN_ERROR_IF(rep==0 || rep > dictContentSize,
+                            dictionary_corrupted, "");
+            entropy->rep[i] = rep;
+    }   }
+
+    return (size_t)(dictPtr - (const BYTE*)dict);
+}
+
+static size_t ZSTD_decompress_insertDictionary(ZSTD_DCtx* dctx, const void* dict, size_t dictSize)
+{
+    if (dictSize < 8) return ZSTD_refDictContent(dctx, dict, dictSize);
+    {   U32 const magic = MEM_readLE32(dict);
+        if (magic != ZSTD_MAGIC_DICTIONARY) {
+            return ZSTD_refDictContent(dctx, dict, dictSize);   /* pure content mode */
+    }   }
+    dctx->dictID = MEM_readLE32((const char*)dict + ZSTD_FRAMEIDSIZE);
+
+    /* load entropy tables */
+    {   size_t const eSize = ZSTD_loadDEntropy(&dctx->entropy, dict, dictSize);
+        RETURN_ERROR_IF(ZSTD_isError(eSize), dictionary_corrupted, "");
+        dict = (const char*)dict + eSize;
+        dictSize -= eSize;
+    }
+    dctx->litEntropy = dctx->fseEntropy = 1;
+
+    /* reference dictionary content */
+    return ZSTD_refDictContent(dctx, dict, dictSize);
+}
+
+size_t ZSTD_decompressBegin(ZSTD_DCtx* dctx)
+{
+    assert(dctx != NULL);
+#if ZSTD_TRACE
+    dctx->traceCtx = (ZSTD_trace_decompress_begin != NULL) ? ZSTD_trace_decompress_begin(dctx) : 0;
+#endif
+    dctx->expected = ZSTD_startingInputLength(dctx->format);  /* dctx->format must be properly set */
+    dctx->stage = ZSTDds_getFrameHeaderSize;
+    dctx->processedCSize = 0;
+    dctx->decodedSize = 0;
+    dctx->previousDstEnd = NULL;
+    dctx->prefixStart = NULL;
+    dctx->virtualStart = NULL;
+    dctx->dictEnd = NULL;
+    dctx->entropy.hufTable[0] = (HUF_DTable)((ZSTD_HUFFDTABLE_CAPACITY_LOG)*0x1000001);  /* cover both little and big endian */
+    dctx->litEntropy = dctx->fseEntropy = 0;
+    dctx->dictID = 0;
+    dctx->bType = bt_reserved;
+    dctx->isFrameDecompression = 1;
+    ZSTD_STATIC_ASSERT(sizeof(dctx->entropy.rep) == sizeof(repStartValue));
+    ZSTD_memcpy(dctx->entropy.rep, repStartValue, sizeof(repStartValue));  /* initial repcodes */
+    dctx->LLTptr = dctx->entropy.LLTable;
+    dctx->MLTptr = dctx->entropy.MLTable;
+    dctx->OFTptr = dctx->entropy.OFTable;
+    dctx->HUFptr = dctx->entropy.hufTable;
+    return 0;
+}
+
+size_t ZSTD_decompressBegin_usingDict(ZSTD_DCtx* dctx, const void* dict, size_t dictSize)
+{
+    FORWARD_IF_ERROR( ZSTD_decompressBegin(dctx) , "");
+    if (dict && dictSize)
+        RETURN_ERROR_IF(
+            ZSTD_isError(ZSTD_decompress_insertDictionary(dctx, dict, dictSize)),
+            dictionary_corrupted, "");
+    return 0;
+}
+
+
+/* ======   ZSTD_DDict   ====== */
+
+size_t ZSTD_decompressBegin_usingDDict(ZSTD_DCtx* dctx, const ZSTD_DDict* ddict)
+{
+    DEBUGLOG(4, "ZSTD_decompressBegin_usingDDict");
+    assert(dctx != NULL);
+    if (ddict) {
+        const char* const dictStart = (const char*)ZSTD_DDict_dictContent(ddict);
+        size_t const dictSize = ZSTD_DDict_dictSize(ddict);
+        const void* const dictEnd = dictStart + dictSize;
+        dctx->ddictIsCold = (dctx->dictEnd != dictEnd);
+        DEBUGLOG(4, "DDict is %s",
+                    dctx->ddictIsCold ? "~cold~" : "hot!");
+    }
+    FORWARD_IF_ERROR( ZSTD_decompressBegin(dctx) , "");
+    if (ddict) {   /* NULL ddict is equivalent to no dictionary */
+        ZSTD_copyDDictParameters(dctx, ddict);
+    }
+    return 0;
+}
+
+/*! ZSTD_decompress_usingDDict() :
+*   Decompression using a pre-digested Dictionary
+*   Use dictionary without significant overhead. */
+size_t ZSTD_decompress_usingDDict(ZSTD_DCtx* dctx,
+                                  void* dst, size_t dstCapacity,
+                            const void* src, size_t srcSize,
+                            const ZSTD_DDict* ddict)
+{
+    /* pass content and size in case legacy frames are encountered */
+    return ZSTD_decompressMultiFrame(dctx, dst, dstCapacity, src, srcSize,
+                                     NULL, 0,
+                                     ddict);
+}
diff --git a/src/commonlib/bsd/zstd/decompress/zstd_decompress_block.c b/src/commonlib/bsd/zstd/decompress/zstd_decompress_block.c
new file mode 100644
index 0000000000..3a963792a4
--- /dev/null
+++ b/src/commonlib/bsd/zstd/decompress/zstd_decompress_block.c
@@ -0,0 +1,2188 @@
+/* SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0-only */
+
+/*
+ * Copyright (c) Meta Platforms, Inc. and affiliates.
+ * All rights reserved.
+ *
+ * This source code is licensed under both the BSD-style license (found in the
+ * LICENSE file in the root directory of this source tree) and the GPLv2 (found
+ * in the COPYING file in the root directory of this source tree).
+ * You may select, at your option, one of the above-listed licenses.
+ */
+
+/* zstd_decompress_block :
+ * this module takes care of decompressing _compressed_ block */
+
+/*-*******************************************************
+*  Dependencies
+*********************************************************/
+#include "../common/zstd_deps.h"   /* ZSTD_memcpy, ZSTD_memmove, ZSTD_memset */
+#include "../common/zstd_compiler.h"    /* prefetch */
+#include "../common/cpu.h"         /* bmi2 */
+#include "../common/mem.h"         /* low level memory routines */
+#define FSE_STATIC_LINKING_ONLY
+#include "../common/fse.h"
+#include "../common/huf.h"
+#include "../common/zstd_internal.h"
+#include "zstd_decompress_internal.h"   /* ZSTD_DCtx */
+#include "zstd_ddict.h"  /* ZSTD_DDictDictContent */
+#include "zstd_decompress_block.h"
+#include "../common/zstd_bits.h"  /* ZSTD_highbit32 */
+
+/*_*******************************************************
+*  Macros
+**********************************************************/
+
+/* These two optional macros force the use one way or another of the two
+ * ZSTD_decompressSequences implementations. You can't force in both directions
+ * at the same time.
+ */
+#if defined(ZSTD_FORCE_DECOMPRESS_SEQUENCES_SHORT) && \
+    defined(ZSTD_FORCE_DECOMPRESS_SEQUENCES_LONG)
+#error "Cannot force the use of the short and the long ZSTD_decompressSequences variants!"
+#endif
+
+
+/*_*******************************************************
+*  Memory operations
+**********************************************************/
+static void ZSTD_copy4(void* dst, const void* src) { ZSTD_memcpy(dst, src, 4); }
+
+
+/*-*************************************************************
+ *   Block decoding
+ ***************************************************************/
+
+static size_t ZSTD_blockSizeMax(ZSTD_DCtx const* dctx)
+{
+    size_t const blockSizeMax = dctx->isFrameDecompression ? dctx->fParams.blockSizeMax : ZSTD_BLOCKSIZE_MAX;
+    assert(blockSizeMax <= ZSTD_BLOCKSIZE_MAX);
+    return blockSizeMax;
+}
+
+/*! ZSTD_getcBlockSize() :
+ *  Provides the size of compressed block from block header `src` */
+size_t ZSTD_getcBlockSize(const void* src, size_t srcSize,
+                          blockProperties_t* bpPtr)
+{
+    RETURN_ERROR_IF(srcSize < ZSTD_blockHeaderSize, srcSize_wrong, "");
+
+    {   U32 const cBlockHeader = MEM_readLE24(src);
+        U32 const cSize = cBlockHeader >> 3;
+        bpPtr->lastBlock = cBlockHeader & 1;
+        bpPtr->blockType = (blockType_e)((cBlockHeader >> 1) & 3);
+        bpPtr->origSize = cSize;   /* only useful for RLE */
+        if (bpPtr->blockType == bt_rle) return 1;
+        RETURN_ERROR_IF(bpPtr->blockType == bt_reserved, corruption_detected, "");
+        return cSize;
+    }
+}
+
+/* Allocate buffer for literals, either overlapping current dst, or split between dst and litExtraBuffer, or stored entirely within litExtraBuffer */
+static void ZSTD_allocateLiteralsBuffer(ZSTD_DCtx* dctx, void* const dst, const size_t dstCapacity, const size_t litSize,
+    const streaming_operation streaming, const size_t expectedWriteSize, const unsigned splitImmediately)
+{
+    size_t const blockSizeMax = ZSTD_blockSizeMax(dctx);
+    assert(litSize <= blockSizeMax);
+    assert(dctx->isFrameDecompression || streaming == not_streaming);
+    assert(expectedWriteSize <= blockSizeMax);
+    if (streaming == not_streaming && dstCapacity > blockSizeMax + WILDCOPY_OVERLENGTH + litSize + WILDCOPY_OVERLENGTH) {
+        /* If we aren't streaming, we can just put the literals after the output
+         * of the current block. We don't need to worry about overwriting the
+         * extDict of our window, because it doesn't exist.
+         * So if we have space after the end of the block, just put it there.
+         */
+        dctx->litBuffer = (BYTE*)dst + blockSizeMax + WILDCOPY_OVERLENGTH;
+        dctx->litBufferEnd = dctx->litBuffer + litSize;
+        dctx->litBufferLocation = ZSTD_in_dst;
+    } else if (litSize <= ZSTD_LITBUFFEREXTRASIZE) {
+        /* Literals fit entirely within the extra buffer, put them there to avoid
+         * having to split the literals.
+         */
+        dctx->litBuffer = dctx->litExtraBuffer;
+        dctx->litBufferEnd = dctx->litBuffer + litSize;
+        dctx->litBufferLocation = ZSTD_not_in_dst;
+    } else {
+        assert(blockSizeMax > ZSTD_LITBUFFEREXTRASIZE);
+        /* Literals must be split between the output block and the extra lit
+         * buffer. We fill the extra lit buffer with the tail of the literals,
+         * and put the rest of the literals at the end of the block, with
+         * WILDCOPY_OVERLENGTH of buffer room to allow for overreads.
+         * This MUST not write more than our maxBlockSize beyond dst, because in
+         * streaming mode, that could overwrite part of our extDict window.
+         */
+        if (splitImmediately) {
+            /* won't fit in litExtraBuffer, so it will be split between end of dst and extra buffer */
+            dctx->litBuffer = (BYTE*)dst + expectedWriteSize - litSize + ZSTD_LITBUFFEREXTRASIZE - WILDCOPY_OVERLENGTH;
+            dctx->litBufferEnd = dctx->litBuffer + litSize - ZSTD_LITBUFFEREXTRASIZE;
+        } else {
+            /* initially this will be stored entirely in dst during huffman decoding, it will partially be shifted to litExtraBuffer after */
+            dctx->litBuffer = (BYTE*)dst + expectedWriteSize - litSize;
+            dctx->litBufferEnd = (BYTE*)dst + expectedWriteSize;
+        }
+        dctx->litBufferLocation = ZSTD_split;
+        assert(dctx->litBufferEnd <= (BYTE*)dst + expectedWriteSize);
+    }
+}
+
+/*! ZSTD_decodeLiteralsBlock() :
+ * Where it is possible to do so without being stomped by the output during decompression, the literals block will be stored
+ * in the dstBuffer.  If there is room to do so, it will be stored in full in the excess dst space after where the current
+ * block will be output.  Otherwise it will be stored at the end of the current dst blockspace, with a small portion being
+ * stored in dctx->litExtraBuffer to help keep it "ahead" of the current output write.
+ *
+ * @return : nb of bytes read from src (< srcSize )
+ *  note : symbol not declared but exposed for fullbench */
+static size_t ZSTD_decodeLiteralsBlock(ZSTD_DCtx* dctx,
+                          const void* src, size_t srcSize,   /* note : srcSize < BLOCKSIZE */
+                          void* dst, size_t dstCapacity, const streaming_operation streaming)
+{
+    DEBUGLOG(5, "ZSTD_decodeLiteralsBlock");
+    RETURN_ERROR_IF(srcSize < MIN_CBLOCK_SIZE, corruption_detected, "");
+
+    {   const BYTE* const istart = (const BYTE*) src;
+        SymbolEncodingType_e const litEncType = (SymbolEncodingType_e)(istart[0] & 3);
+        size_t const blockSizeMax = ZSTD_blockSizeMax(dctx);
+
+        switch(litEncType)
+        {
+        case set_repeat:
+            DEBUGLOG(5, "set_repeat flag : re-using stats from previous compressed literals block");
+            RETURN_ERROR_IF(dctx->litEntropy==0, dictionary_corrupted, "");
+            ZSTD_FALLTHROUGH;
+
+        case set_compressed:
+            RETURN_ERROR_IF(srcSize < 5, corruption_detected, "srcSize >= MIN_CBLOCK_SIZE == 2; here we need up to 5 for case 3");
+            {   size_t lhSize, litSize, litCSize;
+                U32 singleStream=0;
+                U32 const lhlCode = (istart[0] >> 2) & 3;
+                U32 const lhc = MEM_readLE32(istart);
+                size_t hufSuccess;
+                size_t expectedWriteSize = MIN(blockSizeMax, dstCapacity);
+                int const flags = 0
+                    | (ZSTD_DCtx_get_bmi2(dctx) ? HUF_flags_bmi2 : 0)
+                    | (dctx->disableHufAsm ? HUF_flags_disableAsm : 0);
+                switch(lhlCode)
+                {
+                case 0: case 1: default:   /* note : default is impossible, since lhlCode into [0..3] */
+                    /* 2 - 2 - 10 - 10 */
+                    singleStream = !lhlCode;
+                    lhSize = 3;
+                    litSize  = (lhc >> 4) & 0x3FF;
+                    litCSize = (lhc >> 14) & 0x3FF;
+                    break;
+                case 2:
+                    /* 2 - 2 - 14 - 14 */
+                    lhSize = 4;
+                    litSize  = (lhc >> 4) & 0x3FFF;
+                    litCSize = lhc >> 18;
+                    break;
+                case 3:
+                    /* 2 - 2 - 18 - 18 */
+                    lhSize = 5;
+                    litSize  = (lhc >> 4) & 0x3FFFF;
+                    litCSize = (lhc >> 22) + ((size_t)istart[4] << 10);
+                    break;
+                }
+                RETURN_ERROR_IF(litSize > 0 && dst == NULL, dstSize_tooSmall, "NULL not handled");
+                RETURN_ERROR_IF(litSize > blockSizeMax, corruption_detected, "");
+                if (!singleStream)
+                    RETURN_ERROR_IF(litSize < MIN_LITERALS_FOR_4_STREAMS, literals_headerWrong,
+                        "Not enough literals (%zu) for the 4-streams mode (min %u)",
+                        litSize, MIN_LITERALS_FOR_4_STREAMS);
+                RETURN_ERROR_IF(litCSize + lhSize > srcSize, corruption_detected, "");
+                RETURN_ERROR_IF(expectedWriteSize < litSize , dstSize_tooSmall, "");
+                ZSTD_allocateLiteralsBuffer(dctx, dst, dstCapacity, litSize, streaming, expectedWriteSize, 0);
+
+                /* prefetch huffman table if cold */
+                if (dctx->ddictIsCold && (litSize > 768 /* heuristic */)) {
+                    PREFETCH_AREA(dctx->HUFptr, sizeof(dctx->entropy.hufTable));
+                }
+
+                if (litEncType==set_repeat) {
+                    if (singleStream) {
+                        hufSuccess = HUF_decompress1X_usingDTable(
+                            dctx->litBuffer, litSize, istart+lhSize, litCSize,
+                            dctx->HUFptr, flags);
+                    } else {
+                        assert(litSize >= MIN_LITERALS_FOR_4_STREAMS);
+                        hufSuccess = HUF_decompress4X_usingDTable(
+                            dctx->litBuffer, litSize, istart+lhSize, litCSize,
+                            dctx->HUFptr, flags);
+                    }
+                } else {
+                    if (singleStream) {
+#if defined(HUF_FORCE_DECOMPRESS_X2)
+                        hufSuccess = HUF_decompress1X_DCtx_wksp(
+                            dctx->entropy.hufTable, dctx->litBuffer, litSize,
+                            istart+lhSize, litCSize, dctx->workspace,
+                            sizeof(dctx->workspace), flags);
+#else
+                        hufSuccess = HUF_decompress1X1_DCtx_wksp(
+                            dctx->entropy.hufTable, dctx->litBuffer, litSize,
+                            istart+lhSize, litCSize, dctx->workspace,
+                            sizeof(dctx->workspace), flags);
+#endif
+                    } else {
+                        hufSuccess = HUF_decompress4X_hufOnly_wksp(
+                            dctx->entropy.hufTable, dctx->litBuffer, litSize,
+                            istart+lhSize, litCSize, dctx->workspace,
+                            sizeof(dctx->workspace), flags);
+                    }
+                }
+                if (dctx->litBufferLocation == ZSTD_split)
+                {
+                    assert(litSize > ZSTD_LITBUFFEREXTRASIZE);
+                    ZSTD_memcpy(dctx->litExtraBuffer, dctx->litBufferEnd - ZSTD_LITBUFFEREXTRASIZE, ZSTD_LITBUFFEREXTRASIZE);
+                    ZSTD_memmove(dctx->litBuffer + ZSTD_LITBUFFEREXTRASIZE - WILDCOPY_OVERLENGTH, dctx->litBuffer, litSize - ZSTD_LITBUFFEREXTRASIZE);
+                    dctx->litBuffer += ZSTD_LITBUFFEREXTRASIZE - WILDCOPY_OVERLENGTH;
+                    dctx->litBufferEnd -= WILDCOPY_OVERLENGTH;
+                    assert(dctx->litBufferEnd <= (BYTE*)dst + blockSizeMax);
+                }
+
+                RETURN_ERROR_IF(HUF_isError(hufSuccess), corruption_detected, "");
+
+                dctx->litPtr = dctx->litBuffer;
+                dctx->litSize = litSize;
+                dctx->litEntropy = 1;
+                if (litEncType==set_compressed) dctx->HUFptr = dctx->entropy.hufTable;
+                return litCSize + lhSize;
+            }
+
+        case set_basic:
+            {   size_t litSize, lhSize;
+                U32 const lhlCode = ((istart[0]) >> 2) & 3;
+                size_t expectedWriteSize = MIN(blockSizeMax, dstCapacity);
+                switch(lhlCode)
+                {
+                case 0: case 2: default:   /* note : default is impossible, since lhlCode into [0..3] */
+                    lhSize = 1;
+                    litSize = istart[0] >> 3;
+                    break;
+                case 1:
+                    lhSize = 2;
+                    litSize = MEM_readLE16(istart) >> 4;
+                    break;
+                case 3:
+                    lhSize = 3;
+                    RETURN_ERROR_IF(srcSize<3, corruption_detected, "srcSize >= MIN_CBLOCK_SIZE == 2; here we need lhSize = 3");
+                    litSize = MEM_readLE24(istart) >> 4;
+                    break;
+                }
+
+                RETURN_ERROR_IF(litSize > 0 && dst == NULL, dstSize_tooSmall, "NULL not handled");
+                RETURN_ERROR_IF(litSize > blockSizeMax, corruption_detected, "");
+                RETURN_ERROR_IF(expectedWriteSize < litSize, dstSize_tooSmall, "");
+                ZSTD_allocateLiteralsBuffer(dctx, dst, dstCapacity, litSize, streaming, expectedWriteSize, 1);
+                if (lhSize+litSize+WILDCOPY_OVERLENGTH > srcSize) {  /* risk reading beyond src buffer with wildcopy */
+                    RETURN_ERROR_IF(litSize+lhSize > srcSize, corruption_detected, "");
+                    if (dctx->litBufferLocation == ZSTD_split)
+                    {
+                        ZSTD_memcpy(dctx->litBuffer, istart + lhSize, litSize - ZSTD_LITBUFFEREXTRASIZE);
+                        ZSTD_memcpy(dctx->litExtraBuffer, istart + lhSize + litSize - ZSTD_LITBUFFEREXTRASIZE, ZSTD_LITBUFFEREXTRASIZE);
+                    }
+                    else
+                    {
+                        ZSTD_memcpy(dctx->litBuffer, istart + lhSize, litSize);
+                    }
+                    dctx->litPtr = dctx->litBuffer;
+                    dctx->litSize = litSize;
+                    return lhSize+litSize;
+                }
+                /* direct reference into compressed stream */
+                dctx->litPtr = istart+lhSize;
+                dctx->litSize = litSize;
+                dctx->litBufferEnd = dctx->litPtr + litSize;
+                dctx->litBufferLocation = ZSTD_not_in_dst;
+                return lhSize+litSize;
+            }
+
+        case set_rle:
+            {   U32 const lhlCode = ((istart[0]) >> 2) & 3;
+                size_t litSize, lhSize;
+                size_t expectedWriteSize = MIN(blockSizeMax, dstCapacity);
+                switch(lhlCode)
+                {
+                case 0: case 2: default:   /* note : default is impossible, since lhlCode into [0..3] */
+                    lhSize = 1;
+                    litSize = istart[0] >> 3;
+                    break;
+                case 1:
+                    lhSize = 2;
+                    RETURN_ERROR_IF(srcSize<3, corruption_detected, "srcSize >= MIN_CBLOCK_SIZE == 2; here we need lhSize+1 = 3");
+                    litSize = MEM_readLE16(istart) >> 4;
+                    break;
+                case 3:
+                    lhSize = 3;
+                    RETURN_ERROR_IF(srcSize<4, corruption_detected, "srcSize >= MIN_CBLOCK_SIZE == 2; here we need lhSize+1 = 4");
+                    litSize = MEM_readLE24(istart) >> 4;
+                    break;
+                }
+                RETURN_ERROR_IF(litSize > 0 && dst == NULL, dstSize_tooSmall, "NULL not handled");
+                RETURN_ERROR_IF(litSize > blockSizeMax, corruption_detected, "");
+                RETURN_ERROR_IF(expectedWriteSize < litSize, dstSize_tooSmall, "");
+                ZSTD_allocateLiteralsBuffer(dctx, dst, dstCapacity, litSize, streaming, expectedWriteSize, 1);
+                if (dctx->litBufferLocation == ZSTD_split)
+                {
+                    ZSTD_memset(dctx->litBuffer, istart[lhSize], litSize - ZSTD_LITBUFFEREXTRASIZE);
+                    ZSTD_memset(dctx->litExtraBuffer, istart[lhSize], ZSTD_LITBUFFEREXTRASIZE);
+                }
+                else
+                {
+                    ZSTD_memset(dctx->litBuffer, istart[lhSize], litSize);
+                }
+                dctx->litPtr = dctx->litBuffer;
+                dctx->litSize = litSize;
+                return lhSize+1;
+            }
+        default:
+            RETURN_ERROR(corruption_detected, "impossible");
+        }
+    }
+}
+
+/* Hidden declaration for fullbench */
+size_t ZSTD_decodeLiteralsBlock_wrapper(ZSTD_DCtx* dctx,
+                          const void* src, size_t srcSize,
+                          void* dst, size_t dstCapacity);
+size_t ZSTD_decodeLiteralsBlock_wrapper(ZSTD_DCtx* dctx,
+                          const void* src, size_t srcSize,
+                          void* dst, size_t dstCapacity)
+{
+    dctx->isFrameDecompression = 0;
+    return ZSTD_decodeLiteralsBlock(dctx, src, srcSize, dst, dstCapacity, not_streaming);
+}
+
+/* Default FSE distribution tables.
+ * These are pre-calculated FSE decoding tables using default distributions as defined in specification :
+ * https://github.com/facebook/zstd/blob/release/doc/zstd_compression_format.md#default-distributions
+ * They were generated programmatically with following method :
+ * - start from default distributions, present in /lib/common/zstd_internal.h
+ * - generate tables normally, using ZSTD_buildFSETable()
+ * - printout the content of tables
+ * - prettify output, report below, test with fuzzer to ensure it's correct */
+
+/* Default FSE distribution table for Literal Lengths */
+static const ZSTD_seqSymbol LL_defaultDTable[(1<<LL_DEFAULTNORMLOG)+1] = {
+     {  1,  1,  1, LL_DEFAULTNORMLOG},  /* header : fastMode, tableLog */
+     /* nextState, nbAddBits, nbBits, baseVal */
+     {  0,  0,  4,    0},  { 16,  0,  4,    0},
+     { 32,  0,  5,    1},  {  0,  0,  5,    3},
+     {  0,  0,  5,    4},  {  0,  0,  5,    6},
+     {  0,  0,  5,    7},  {  0,  0,  5,    9},
+     {  0,  0,  5,   10},  {  0,  0,  5,   12},
+     {  0,  0,  6,   14},  {  0,  1,  5,   16},
+     {  0,  1,  5,   20},  {  0,  1,  5,   22},
+     {  0,  2,  5,   28},  {  0,  3,  5,   32},
+     {  0,  4,  5,   48},  { 32,  6,  5,   64},
+     {  0,  7,  5,  128},  {  0,  8,  6,  256},
+     {  0, 10,  6, 1024},  {  0, 12,  6, 4096},
+     { 32,  0,  4,    0},  {  0,  0,  4,    1},
+     {  0,  0,  5,    2},  { 32,  0,  5,    4},
+     {  0,  0,  5,    5},  { 32,  0,  5,    7},
+     {  0,  0,  5,    8},  { 32,  0,  5,   10},
+     {  0,  0,  5,   11},  {  0,  0,  6,   13},
+     { 32,  1,  5,   16},  {  0,  1,  5,   18},
+     { 32,  1,  5,   22},  {  0,  2,  5,   24},
+     { 32,  3,  5,   32},  {  0,  3,  5,   40},
+     {  0,  6,  4,   64},  { 16,  6,  4,   64},
+     { 32,  7,  5,  128},  {  0,  9,  6,  512},
+     {  0, 11,  6, 2048},  { 48,  0,  4,    0},
+     { 16,  0,  4,    1},  { 32,  0,  5,    2},
+     { 32,  0,  5,    3},  { 32,  0,  5,    5},
+     { 32,  0,  5,    6},  { 32,  0,  5,    8},
+     { 32,  0,  5,    9},  { 32,  0,  5,   11},
+     { 32,  0,  5,   12},  {  0,  0,  6,   15},
+     { 32,  1,  5,   18},  { 32,  1,  5,   20},
+     { 32,  2,  5,   24},  { 32,  2,  5,   28},
+     { 32,  3,  5,   40},  { 32,  4,  5,   48},
+     {  0, 16,  6,65536},  {  0, 15,  6,32768},
+     {  0, 14,  6,16384},  {  0, 13,  6, 8192},
+};   /* LL_defaultDTable */
+
+/* Default FSE distribution table for Offset Codes */
+static const ZSTD_seqSymbol OF_defaultDTable[(1<<OF_DEFAULTNORMLOG)+1] = {
+    {  1,  1,  1, OF_DEFAULTNORMLOG},  /* header : fastMode, tableLog */
+    /* nextState, nbAddBits, nbBits, baseVal */
+    {  0,  0,  5,    0},     {  0,  6,  4,   61},
+    {  0,  9,  5,  509},     {  0, 15,  5,32765},
+    {  0, 21,  5,2097149},   {  0,  3,  5,    5},
+    {  0,  7,  4,  125},     {  0, 12,  5, 4093},
+    {  0, 18,  5,262141},    {  0, 23,  5,8388605},
+    {  0,  5,  5,   29},     {  0,  8,  4,  253},
+    {  0, 14,  5,16381},     {  0, 20,  5,1048573},
+    {  0,  2,  5,    1},     { 16,  7,  4,  125},
+    {  0, 11,  5, 2045},     {  0, 17,  5,131069},
+    {  0, 22,  5,4194301},   {  0,  4,  5,   13},
+    { 16,  8,  4,  253},     {  0, 13,  5, 8189},
+    {  0, 19,  5,524285},    {  0,  1,  5,    1},
+    { 16,  6,  4,   61},     {  0, 10,  5, 1021},
+    {  0, 16,  5,65533},     {  0, 28,  5,268435453},
+    {  0, 27,  5,134217725}, {  0, 26,  5,67108861},
+    {  0, 25,  5,33554429},  {  0, 24,  5,16777213},
+};   /* OF_defaultDTable */
+
+
+/* Default FSE distribution table for Match Lengths */
+static const ZSTD_seqSymbol ML_defaultDTable[(1<<ML_DEFAULTNORMLOG)+1] = {
+    {  1,  1,  1, ML_DEFAULTNORMLOG},  /* header : fastMode, tableLog */
+    /* nextState, nbAddBits, nbBits, baseVal */
+    {  0,  0,  6,    3},  {  0,  0,  4,    4},
+    { 32,  0,  5,    5},  {  0,  0,  5,    6},
+    {  0,  0,  5,    8},  {  0,  0,  5,    9},
+    {  0,  0,  5,   11},  {  0,  0,  6,   13},
+    {  0,  0,  6,   16},  {  0,  0,  6,   19},
+    {  0,  0,  6,   22},  {  0,  0,  6,   25},
+    {  0,  0,  6,   28},  {  0,  0,  6,   31},
+    {  0,  0,  6,   34},  {  0,  1,  6,   37},
+    {  0,  1,  6,   41},  {  0,  2,  6,   47},
+    {  0,  3,  6,   59},  {  0,  4,  6,   83},
+    {  0,  7,  6,  131},  {  0,  9,  6,  515},
+    { 16,  0,  4,    4},  {  0,  0,  4,    5},
+    { 32,  0,  5,    6},  {  0,  0,  5,    7},
+    { 32,  0,  5,    9},  {  0,  0,  5,   10},
+    {  0,  0,  6,   12},  {  0,  0,  6,   15},
+    {  0,  0,  6,   18},  {  0,  0,  6,   21},
+    {  0,  0,  6,   24},  {  0,  0,  6,   27},
+    {  0,  0,  6,   30},  {  0,  0,  6,   33},
+    {  0,  1,  6,   35},  {  0,  1,  6,   39},
+    {  0,  2,  6,   43},  {  0,  3,  6,   51},
+    {  0,  4,  6,   67},  {  0,  5,  6,   99},
+    {  0,  8,  6,  259},  { 32,  0,  4,    4},
+    { 48,  0,  4,    4},  { 16,  0,  4,    5},
+    { 32,  0,  5,    7},  { 32,  0,  5,    8},
+    { 32,  0,  5,   10},  { 32,  0,  5,   11},
+    {  0,  0,  6,   14},  {  0,  0,  6,   17},
+    {  0,  0,  6,   20},  {  0,  0,  6,   23},
+    {  0,  0,  6,   26},  {  0,  0,  6,   29},
+    {  0,  0,  6,   32},  {  0, 16,  6,65539},
+    {  0, 15,  6,32771},  {  0, 14,  6,16387},
+    {  0, 13,  6, 8195},  {  0, 12,  6, 4099},
+    {  0, 11,  6, 2051},  {  0, 10,  6, 1027},
+};   /* ML_defaultDTable */
+
+
+static void ZSTD_buildSeqTable_rle(ZSTD_seqSymbol* dt, U32 baseValue, U8 nbAddBits)
+{
+    void* ptr = dt;
+    ZSTD_seqSymbol_header* const DTableH = (ZSTD_seqSymbol_header*)ptr;
+    ZSTD_seqSymbol* const cell = dt + 1;
+
+    DTableH->tableLog = 0;
+    DTableH->fastMode = 0;
+
+    cell->nbBits = 0;
+    cell->nextState = 0;
+    assert(nbAddBits < 255);
+    cell->nbAdditionalBits = nbAddBits;
+    cell->baseValue = baseValue;
+}
+
+
+/* ZSTD_buildFSETable() :
+ * generate FSE decoding table for one symbol (ll, ml or off)
+ * cannot fail if input is valid =>
+ * all inputs are presumed validated at this stage */
+FORCE_INLINE_TEMPLATE
+void ZSTD_buildFSETable_body(ZSTD_seqSymbol* dt,
+            const short* normalizedCounter, unsigned maxSymbolValue,
+            const U32* baseValue, const U8* nbAdditionalBits,
+            unsigned tableLog, void* wksp, size_t wkspSize)
+{
+    ZSTD_seqSymbol* const tableDecode = dt+1;
+    U32 const maxSV1 = maxSymbolValue + 1;
+    U32 const tableSize = 1 << tableLog;
+
+    U16* symbolNext = (U16*)wksp;
+    BYTE* spread = (BYTE*)(symbolNext + MaxSeq + 1);
+    U32 highThreshold = tableSize - 1;
+
+
+    /* Sanity Checks */
+    assert(maxSymbolValue <= MaxSeq);
+    assert(tableLog <= MaxFSELog);
+    assert(wkspSize >= ZSTD_BUILD_FSE_TABLE_WKSP_SIZE);
+    (void)wkspSize;
+    /* Init, lay down lowprob symbols */
+    {   ZSTD_seqSymbol_header DTableH;
+        DTableH.tableLog = tableLog;
+        DTableH.fastMode = 1;
+        {   S16 const largeLimit= (S16)(1 << (tableLog-1));
+            U32 s;
+            for (s=0; s<maxSV1; s++) {
+                if (normalizedCounter[s]==-1) {
+                    tableDecode[highThreshold--].baseValue = s;
+                    symbolNext[s] = 1;
+                } else {
+                    if (normalizedCounter[s] >= largeLimit) DTableH.fastMode=0;
+                    assert(normalizedCounter[s]>=0);
+                    symbolNext[s] = (U16)normalizedCounter[s];
+        }   }   }
+        ZSTD_memcpy(dt, &DTableH, sizeof(DTableH));
+    }
+
+    /* Spread symbols */
+    assert(tableSize <= 512);
+    /* Specialized symbol spreading for the case when there are
+     * no low probability (-1 count) symbols. When compressing
+     * small blocks we avoid low probability symbols to hit this
+     * case, since header decoding speed matters more.
+     */
+    if (highThreshold == tableSize - 1) {
+        size_t const tableMask = tableSize-1;
+        size_t const step = FSE_TABLESTEP(tableSize);
+        /* First lay down the symbols in order.
+         * We use a uint64_t to lay down 8 bytes at a time. This reduces branch
+         * misses since small blocks generally have small table logs, so nearly
+         * all symbols have counts <= 8. We ensure we have 8 bytes at the end of
+         * our buffer to handle the over-write.
+         */
+        {
+            U64 const add = 0x0101010101010101ull;
+            size_t pos = 0;
+            U64 sv = 0;
+            U32 s;
+            for (s=0; s<maxSV1; ++s, sv += add) {
+                int i;
+                int const n = normalizedCounter[s];
+                MEM_write64(spread + pos, sv);
+                for (i = 8; i < n; i += 8) {
+                    MEM_write64(spread + pos + i, sv);
+                }
+                assert(n>=0);
+                pos += (size_t)n;
+            }
+        }
+        /* Now we spread those positions across the table.
+         * The benefit of doing it in two stages is that we avoid the
+         * variable size inner loop, which caused lots of branch misses.
+         * Now we can run through all the positions without any branch misses.
+         * We unroll the loop twice, since that is what empirically worked best.
+         */
+        {
+            size_t position = 0;
+            size_t s;
+            size_t const unroll = 2;
+            assert(tableSize % unroll == 0); /* FSE_MIN_TABLELOG is 5 */
+            for (s = 0; s < (size_t)tableSize; s += unroll) {
+                size_t u;
+                for (u = 0; u < unroll; ++u) {
+                    size_t const uPosition = (position + (u * step)) & tableMask;
+                    tableDecode[uPosition].baseValue = spread[s + u];
+                }
+                position = (position + (unroll * step)) & tableMask;
+            }
+            assert(position == 0);
+        }
+    } else {
+        U32 const tableMask = tableSize-1;
+        U32 const step = FSE_TABLESTEP(tableSize);
+        U32 s, position = 0;
+        for (s=0; s<maxSV1; s++) {
+            int i;
+            int const n = normalizedCounter[s];
+            for (i=0; i<n; i++) {
+                tableDecode[position].baseValue = s;
+                position = (position + step) & tableMask;
+                while (UNLIKELY(position > highThreshold)) position = (position + step) & tableMask;   /* lowprob area */
+        }   }
+        assert(position == 0); /* position must reach all cells once, otherwise normalizedCounter is incorrect */
+    }
+
+    /* Build Decoding table */
+    {
+        U32 u;
+        for (u=0; u<tableSize; u++) {
+            U32 const symbol = tableDecode[u].baseValue;
+            U32 const nextState = symbolNext[symbol]++;
+            tableDecode[u].nbBits = (BYTE) (tableLog - ZSTD_highbit32(nextState) );
+            tableDecode[u].nextState = (U16) ( (nextState << tableDecode[u].nbBits) - tableSize);
+            assert(nbAdditionalBits[symbol] < 255);
+            tableDecode[u].nbAdditionalBits = nbAdditionalBits[symbol];
+            tableDecode[u].baseValue = baseValue[symbol];
+        }
+    }
+}
+
+/* Avoids the FORCE_INLINE of the _body() function. */
+static void ZSTD_buildFSETable_body_default(ZSTD_seqSymbol* dt,
+            const short* normalizedCounter, unsigned maxSymbolValue,
+            const U32* baseValue, const U8* nbAdditionalBits,
+            unsigned tableLog, void* wksp, size_t wkspSize)
+{
+    ZSTD_buildFSETable_body(dt, normalizedCounter, maxSymbolValue,
+            baseValue, nbAdditionalBits, tableLog, wksp, wkspSize);
+}
+
+#if DYNAMIC_BMI2
+BMI2_TARGET_ATTRIBUTE static void ZSTD_buildFSETable_body_bmi2(ZSTD_seqSymbol* dt,
+            const short* normalizedCounter, unsigned maxSymbolValue,
+            const U32* baseValue, const U8* nbAdditionalBits,
+            unsigned tableLog, void* wksp, size_t wkspSize)
+{
+    ZSTD_buildFSETable_body(dt, normalizedCounter, maxSymbolValue,
+            baseValue, nbAdditionalBits, tableLog, wksp, wkspSize);
+}
+#endif
+
+void ZSTD_buildFSETable(ZSTD_seqSymbol* dt,
+            const short* normalizedCounter, unsigned maxSymbolValue,
+            const U32* baseValue, const U8* nbAdditionalBits,
+            unsigned tableLog, void* wksp, size_t wkspSize, int bmi2)
+{
+#if DYNAMIC_BMI2
+    if (bmi2) {
+        ZSTD_buildFSETable_body_bmi2(dt, normalizedCounter, maxSymbolValue,
+                baseValue, nbAdditionalBits, tableLog, wksp, wkspSize);
+        return;
+    }
+#endif
+    (void)bmi2;
+    ZSTD_buildFSETable_body_default(dt, normalizedCounter, maxSymbolValue,
+            baseValue, nbAdditionalBits, tableLog, wksp, wkspSize);
+}
+
+
+/*! ZSTD_buildSeqTable() :
+ * @return : nb bytes read from src,
+ *           or an error code if it fails */
+static size_t ZSTD_buildSeqTable(ZSTD_seqSymbol* DTableSpace, const ZSTD_seqSymbol** DTablePtr,
+                                 SymbolEncodingType_e type, unsigned max, U32 maxLog,
+                                 const void* src, size_t srcSize,
+                                 const U32* baseValue, const U8* nbAdditionalBits,
+                                 const ZSTD_seqSymbol* defaultTable, U32 flagRepeatTable,
+                                 int ddictIsCold, int nbSeq, U32* wksp, size_t wkspSize,
+                                 int bmi2)
+{
+    switch(type)
+    {
+    case set_rle :
+        RETURN_ERROR_IF(!srcSize, srcSize_wrong, "");
+        RETURN_ERROR_IF((*(const BYTE*)src) > max, corruption_detected, "");
+        {   U32 const symbol = *(const BYTE*)src;
+            U32 const baseline = baseValue[symbol];
+            U8 const nbBits = nbAdditionalBits[symbol];
+            ZSTD_buildSeqTable_rle(DTableSpace, baseline, nbBits);
+        }
+        *DTablePtr = DTableSpace;
+        return 1;
+    case set_basic :
+        *DTablePtr = defaultTable;
+        return 0;
+    case set_repeat:
+        RETURN_ERROR_IF(!flagRepeatTable, corruption_detected, "");
+        /* prefetch FSE table if used */
+        if (ddictIsCold && (nbSeq > 24 /* heuristic */)) {
+            const void* const pStart = *DTablePtr;
+            size_t const pSize = sizeof(ZSTD_seqSymbol) * (SEQSYMBOL_TABLE_SIZE(maxLog));
+            PREFETCH_AREA(pStart, pSize);
+        }
+        return 0;
+    case set_compressed :
+        {   unsigned tableLog;
+            S16 norm[MaxSeq+1];
+            size_t const headerSize = FSE_readNCount(norm, &max, &tableLog, src, srcSize);
+            RETURN_ERROR_IF(FSE_isError(headerSize), corruption_detected, "");
+            RETURN_ERROR_IF(tableLog > maxLog, corruption_detected, "");
+            ZSTD_buildFSETable(DTableSpace, norm, max, baseValue, nbAdditionalBits, tableLog, wksp, wkspSize, bmi2);
+            *DTablePtr = DTableSpace;
+            return headerSize;
+        }
+    default :
+        assert(0);
+        RETURN_ERROR(GENERIC, "impossible");
+    }
+}
+
+size_t ZSTD_decodeSeqHeaders(ZSTD_DCtx* dctx, int* nbSeqPtr,
+                             const void* src, size_t srcSize)
+{
+    const BYTE* const istart = (const BYTE*)src;
+    const BYTE* const iend = istart + srcSize;
+    const BYTE* ip = istart;
+    int nbSeq;
+    DEBUGLOG(5, "ZSTD_decodeSeqHeaders");
+
+    /* check */
+    RETURN_ERROR_IF(srcSize < MIN_SEQUENCES_SIZE, srcSize_wrong, "");
+
+    /* SeqHead */
+    nbSeq = *ip++;
+    if (nbSeq > 0x7F) {
+        if (nbSeq == 0xFF) {
+            RETURN_ERROR_IF(ip+2 > iend, srcSize_wrong, "");
+            nbSeq = MEM_readLE16(ip) + LONGNBSEQ;
+            ip+=2;
+        } else {
+            RETURN_ERROR_IF(ip >= iend, srcSize_wrong, "");
+            nbSeq = ((nbSeq-0x80)<<8) + *ip++;
+        }
+    }
+    *nbSeqPtr = nbSeq;
+
+    if (nbSeq == 0) {
+        /* No sequence : section ends immediately */
+        RETURN_ERROR_IF(ip != iend, corruption_detected,
+            "extraneous data present in the Sequences section");
+        return (size_t)(ip - istart);
+    }
+
+    /* FSE table descriptors */
+    RETURN_ERROR_IF(ip+1 > iend, srcSize_wrong, ""); /* minimum possible size: 1 byte for symbol encoding types */
+    RETURN_ERROR_IF(*ip & 3, corruption_detected, ""); /* The last field, Reserved, must be all-zeroes. */
+    {   SymbolEncodingType_e const LLtype = (SymbolEncodingType_e)(*ip >> 6);
+        SymbolEncodingType_e const OFtype = (SymbolEncodingType_e)((*ip >> 4) & 3);
+        SymbolEncodingType_e const MLtype = (SymbolEncodingType_e)((*ip >> 2) & 3);
+        ip++;
+
+        /* Build DTables */
+        {   size_t const llhSize = ZSTD_buildSeqTable(dctx->entropy.LLTable, &dctx->LLTptr,
+                                                      LLtype, MaxLL, LLFSELog,
+                                                      ip, iend-ip,
+                                                      LL_base, LL_bits,
+                                                      LL_defaultDTable, dctx->fseEntropy,
+                                                      dctx->ddictIsCold, nbSeq,
+                                                      dctx->workspace, sizeof(dctx->workspace),
+                                                      ZSTD_DCtx_get_bmi2(dctx));
+            RETURN_ERROR_IF(ZSTD_isError(llhSize), corruption_detected, "ZSTD_buildSeqTable failed");
+            ip += llhSize;
+        }
+
+        {   size_t const ofhSize = ZSTD_buildSeqTable(dctx->entropy.OFTable, &dctx->OFTptr,
+                                                      OFtype, MaxOff, OffFSELog,
+                                                      ip, iend-ip,
+                                                      OF_base, OF_bits,
+                                                      OF_defaultDTable, dctx->fseEntropy,
+                                                      dctx->ddictIsCold, nbSeq,
+                                                      dctx->workspace, sizeof(dctx->workspace),
+                                                      ZSTD_DCtx_get_bmi2(dctx));
+            RETURN_ERROR_IF(ZSTD_isError(ofhSize), corruption_detected, "ZSTD_buildSeqTable failed");
+            ip += ofhSize;
+        }
+
+        {   size_t const mlhSize = ZSTD_buildSeqTable(dctx->entropy.MLTable, &dctx->MLTptr,
+                                                      MLtype, MaxML, MLFSELog,
+                                                      ip, iend-ip,
+                                                      ML_base, ML_bits,
+                                                      ML_defaultDTable, dctx->fseEntropy,
+                                                      dctx->ddictIsCold, nbSeq,
+                                                      dctx->workspace, sizeof(dctx->workspace),
+                                                      ZSTD_DCtx_get_bmi2(dctx));
+            RETURN_ERROR_IF(ZSTD_isError(mlhSize), corruption_detected, "ZSTD_buildSeqTable failed");
+            ip += mlhSize;
+        }
+    }
+
+    return ip-istart;
+}
+
+
+typedef struct {
+    size_t litLength;
+    size_t matchLength;
+    size_t offset;
+} seq_t;
+
+typedef struct {
+    size_t state;
+    const ZSTD_seqSymbol* table;
+} ZSTD_fseState;
+
+typedef struct {
+    BIT_DStream_t DStream;
+    ZSTD_fseState stateLL;
+    ZSTD_fseState stateOffb;
+    ZSTD_fseState stateML;
+    size_t prevOffset[ZSTD_REP_NUM];
+} seqState_t;
+
+/*! ZSTD_overlapCopy8() :
+ *  Copies 8 bytes from ip to op and updates op and ip where ip <= op.
+ *  If the offset is < 8 then the offset is spread to at least 8 bytes.
+ *
+ *  Precondition: *ip <= *op
+ *  Postcondition: *op - *op >= 8
+ */
+HINT_INLINE void ZSTD_overlapCopy8(BYTE** op, BYTE const** ip, size_t offset) {
+    assert(*ip <= *op);
+    if (offset < 8) {
+        /* close range match, overlap */
+        static const U32 dec32table[] = { 0, 1, 2, 1, 4, 4, 4, 4 };   /* added */
+        static const int dec64table[] = { 8, 8, 8, 7, 8, 9,10,11 };   /* subtracted */
+        int const sub2 = dec64table[offset];
+        (*op)[0] = (*ip)[0];
+        (*op)[1] = (*ip)[1];
+        (*op)[2] = (*ip)[2];
+        (*op)[3] = (*ip)[3];
+        *ip += dec32table[offset];
+        ZSTD_copy4(*op+4, *ip);
+        *ip -= sub2;
+    } else {
+        ZSTD_copy8(*op, *ip);
+    }
+    *ip += 8;
+    *op += 8;
+    assert(*op - *ip >= 8);
+}
+
+/*! ZSTD_safecopy() :
+ *  Specialized version of memcpy() that is allowed to READ up to WILDCOPY_OVERLENGTH past the input buffer
+ *  and write up to 16 bytes past oend_w (op >= oend_w is allowed).
+ *  This function is only called in the uncommon case where the sequence is near the end of the block. It
+ *  should be fast for a single long sequence, but can be slow for several short sequences.
+ *
+ *  @param ovtype controls the overlap detection
+ *         - ZSTD_no_overlap: The source and destination are guaranteed to be at least WILDCOPY_VECLEN bytes apart.
+ *         - ZSTD_overlap_src_before_dst: The src and dst may overlap and may be any distance apart.
+ *           The src buffer must be before the dst buffer.
+ */
+static void ZSTD_safecopy(BYTE* op, const BYTE* const oend_w, BYTE const* ip, ptrdiff_t length, ZSTD_overlap_e ovtype) {
+    ptrdiff_t const diff = op - ip;
+    BYTE* const oend = op + length;
+
+    assert((ovtype == ZSTD_no_overlap && (diff <= -8 || diff >= 8 || op >= oend_w)) ||
+           (ovtype == ZSTD_overlap_src_before_dst && diff >= 0));
+
+    if (length < 8) {
+        /* Handle short lengths. */
+        while (op < oend) *op++ = *ip++;
+        return;
+    }
+    if (ovtype == ZSTD_overlap_src_before_dst) {
+        /* Copy 8 bytes and ensure the offset >= 8 when there can be overlap. */
+        assert(length >= 8);
+        ZSTD_overlapCopy8(&op, &ip, diff);
+        length -= 8;
+        assert(op - ip >= 8);
+        assert(op <= oend);
+    }
+
+    if (oend <= oend_w) {
+        /* No risk of overwrite. */
+        ZSTD_wildcopy(op, ip, length, ovtype);
+        return;
+    }
+    if (op <= oend_w) {
+        /* Wildcopy until we get close to the end. */
+        assert(oend > oend_w);
+        ZSTD_wildcopy(op, ip, oend_w - op, ovtype);
+        ip += oend_w - op;
+        op += oend_w - op;
+    }
+    /* Handle the leftovers. */
+    while (op < oend) *op++ = *ip++;
+}
+
+/* ZSTD_safecopyDstBeforeSrc():
+ * This version allows overlap with dst before src, or handles the non-overlap case with dst after src
+ * Kept separate from more common ZSTD_safecopy case to avoid performance impact to the safecopy common case */
+static void ZSTD_safecopyDstBeforeSrc(BYTE* op, const BYTE* ip, ptrdiff_t length) {
+    ptrdiff_t const diff = op - ip;
+    BYTE* const oend = op + length;
+
+    if (length < 8 || diff > -8) {
+        /* Handle short lengths, close overlaps, and dst not before src. */
+        while (op < oend) *op++ = *ip++;
+        return;
+    }
+
+    if (op <= oend - WILDCOPY_OVERLENGTH && diff < -WILDCOPY_VECLEN) {
+        ZSTD_wildcopy(op, ip, oend - WILDCOPY_OVERLENGTH - op, ZSTD_no_overlap);
+        ip += oend - WILDCOPY_OVERLENGTH - op;
+        op += oend - WILDCOPY_OVERLENGTH - op;
+    }
+
+    /* Handle the leftovers. */
+    while (op < oend) *op++ = *ip++;
+}
+
+/* ZSTD_execSequenceEnd():
+ * This version handles cases that are near the end of the output buffer. It requires
+ * more careful checks to make sure there is no overflow. By separating out these hard
+ * and unlikely cases, we can speed up the common cases.
+ *
+ * NOTE: This function needs to be fast for a single long sequence, but doesn't need
+ * to be optimized for many small sequences, since those fall into ZSTD_execSequence().
+ */
+FORCE_NOINLINE
+ZSTD_ALLOW_POINTER_OVERFLOW_ATTR
+size_t ZSTD_execSequenceEnd(BYTE* op,
+    BYTE* const oend, seq_t sequence,
+    const BYTE** litPtr, const BYTE* const litLimit,
+    const BYTE* const prefixStart, const BYTE* const virtualStart, const BYTE* const dictEnd)
+{
+    BYTE* const oLitEnd = op + sequence.litLength;
+    size_t const sequenceLength = sequence.litLength + sequence.matchLength;
+    const BYTE* const iLitEnd = *litPtr + sequence.litLength;
+    const BYTE* match = oLitEnd - sequence.offset;
+    BYTE* const oend_w = oend - WILDCOPY_OVERLENGTH;
+
+    /* bounds checks : careful of address space overflow in 32-bit mode */
+    RETURN_ERROR_IF(sequenceLength > (size_t)(oend - op), dstSize_tooSmall, "last match must fit within dstBuffer");
+    RETURN_ERROR_IF(sequence.litLength > (size_t)(litLimit - *litPtr), corruption_detected, "try to read beyond literal buffer");
+    assert(op < op + sequenceLength);
+    assert(oLitEnd < op + sequenceLength);
+
+    /* copy literals */
+    ZSTD_safecopy(op, oend_w, *litPtr, sequence.litLength, ZSTD_no_overlap);
+    op = oLitEnd;
+    *litPtr = iLitEnd;
+
+    /* copy Match */
+    if (sequence.offset > (size_t)(oLitEnd - prefixStart)) {
+        /* offset beyond prefix */
+        RETURN_ERROR_IF(sequence.offset > (size_t)(oLitEnd - virtualStart), corruption_detected, "");
+        match = dictEnd - (prefixStart - match);
+        if (match + sequence.matchLength <= dictEnd) {
+            ZSTD_memmove(oLitEnd, match, sequence.matchLength);
+            return sequenceLength;
+        }
+        /* span extDict & currentPrefixSegment */
+        {   size_t const length1 = dictEnd - match;
+        ZSTD_memmove(oLitEnd, match, length1);
+        op = oLitEnd + length1;
+        sequence.matchLength -= length1;
+        match = prefixStart;
+        }
+    }
+    ZSTD_safecopy(op, oend_w, match, sequence.matchLength, ZSTD_overlap_src_before_dst);
+    return sequenceLength;
+}
+
+/* ZSTD_execSequenceEndSplitLitBuffer():
+ * This version is intended to be used during instances where the litBuffer is still split.  It is kept separate to avoid performance impact for the good case.
+ */
+FORCE_NOINLINE
+ZSTD_ALLOW_POINTER_OVERFLOW_ATTR
+size_t ZSTD_execSequenceEndSplitLitBuffer(BYTE* op,
+    BYTE* const oend, const BYTE* const oend_w, seq_t sequence,
+    const BYTE** litPtr, const BYTE* const litLimit,
+    const BYTE* const prefixStart, const BYTE* const virtualStart, const BYTE* const dictEnd)
+{
+    BYTE* const oLitEnd = op + sequence.litLength;
+    size_t const sequenceLength = sequence.litLength + sequence.matchLength;
+    const BYTE* const iLitEnd = *litPtr + sequence.litLength;
+    const BYTE* match = oLitEnd - sequence.offset;
+
+
+    /* bounds checks : careful of address space overflow in 32-bit mode */
+    RETURN_ERROR_IF(sequenceLength > (size_t)(oend - op), dstSize_tooSmall, "last match must fit within dstBuffer");
+    RETURN_ERROR_IF(sequence.litLength > (size_t)(litLimit - *litPtr), corruption_detected, "try to read beyond literal buffer");
+    assert(op < op + sequenceLength);
+    assert(oLitEnd < op + sequenceLength);
+
+    /* copy literals */
+    RETURN_ERROR_IF(op > *litPtr && op < *litPtr + sequence.litLength, dstSize_tooSmall, "output should not catch up to and overwrite literal buffer");
+    ZSTD_safecopyDstBeforeSrc(op, *litPtr, sequence.litLength);
+    op = oLitEnd;
+    *litPtr = iLitEnd;
+
+    /* copy Match */
+    if (sequence.offset > (size_t)(oLitEnd - prefixStart)) {
+        /* offset beyond prefix */
+        RETURN_ERROR_IF(sequence.offset > (size_t)(oLitEnd - virtualStart), corruption_detected, "");
+        match = dictEnd - (prefixStart - match);
+        if (match + sequence.matchLength <= dictEnd) {
+            ZSTD_memmove(oLitEnd, match, sequence.matchLength);
+            return sequenceLength;
+        }
+        /* span extDict & currentPrefixSegment */
+        {   size_t const length1 = dictEnd - match;
+        ZSTD_memmove(oLitEnd, match, length1);
+        op = oLitEnd + length1;
+        sequence.matchLength -= length1;
+        match = prefixStart;
+        }
+    }
+    ZSTD_safecopy(op, oend_w, match, sequence.matchLength, ZSTD_overlap_src_before_dst);
+    return sequenceLength;
+}
+
+HINT_INLINE
+ZSTD_ALLOW_POINTER_OVERFLOW_ATTR
+size_t ZSTD_execSequence(BYTE* op,
+    BYTE* const oend, seq_t sequence,
+    const BYTE** litPtr, const BYTE* const litLimit,
+    const BYTE* const prefixStart, const BYTE* const virtualStart, const BYTE* const dictEnd)
+{
+    BYTE* const oLitEnd = op + sequence.litLength;
+    size_t const sequenceLength = sequence.litLength + sequence.matchLength;
+    BYTE* const oMatchEnd = op + sequenceLength;   /* risk : address space overflow (32-bits) */
+    BYTE* const oend_w = oend - WILDCOPY_OVERLENGTH;   /* risk : address space underflow on oend=NULL */
+    const BYTE* const iLitEnd = *litPtr + sequence.litLength;
+    const BYTE* match = oLitEnd - sequence.offset;
+
+    assert(op != NULL /* Precondition */);
+    assert(oend_w < oend /* No underflow */);
+
+#if defined(__aarch64__)
+    /* prefetch sequence starting from match that will be used for copy later */
+    PREFETCH_L1(match);
+#endif
+    /* Handle edge cases in a slow path:
+     *   - Read beyond end of literals
+     *   - Match end is within WILDCOPY_OVERLIMIT of oend
+     *   - 32-bit mode and the match length overflows
+     */
+    if (UNLIKELY(
+        iLitEnd > litLimit ||
+        oMatchEnd > oend_w ||
+        (MEM_32bits() && (size_t)(oend - op) < sequenceLength + WILDCOPY_OVERLENGTH)))
+        return ZSTD_execSequenceEnd(op, oend, sequence, litPtr, litLimit, prefixStart, virtualStart, dictEnd);
+
+    /* Assumptions (everything else goes into ZSTD_execSequenceEnd()) */
+    assert(op <= oLitEnd /* No overflow */);
+    assert(oLitEnd < oMatchEnd /* Non-zero match & no overflow */);
+    assert(oMatchEnd <= oend /* No underflow */);
+    assert(iLitEnd <= litLimit /* Literal length is in bounds */);
+    assert(oLitEnd <= oend_w /* Can wildcopy literals */);
+    assert(oMatchEnd <= oend_w /* Can wildcopy matches */);
+
+    /* Copy Literals:
+     * Split out litLength <= 16 since it is nearly always true. +1.6% on gcc-9.
+     * We likely don't need the full 32-byte wildcopy.
+     */
+    assert(WILDCOPY_OVERLENGTH >= 16);
+    ZSTD_copy16(op, (*litPtr));
+    if (UNLIKELY(sequence.litLength > 16)) {
+        ZSTD_wildcopy(op + 16, (*litPtr) + 16, sequence.litLength - 16, ZSTD_no_overlap);
+    }
+    op = oLitEnd;
+    *litPtr = iLitEnd;   /* update for next sequence */
+
+    /* Copy Match */
+    if (sequence.offset > (size_t)(oLitEnd - prefixStart)) {
+        /* offset beyond prefix -> go into extDict */
+        RETURN_ERROR_IF(UNLIKELY(sequence.offset > (size_t)(oLitEnd - virtualStart)), corruption_detected, "");
+        match = dictEnd + (match - prefixStart);
+        if (match + sequence.matchLength <= dictEnd) {
+            ZSTD_memmove(oLitEnd, match, sequence.matchLength);
+            return sequenceLength;
+        }
+        /* span extDict & currentPrefixSegment */
+        {   size_t const length1 = dictEnd - match;
+        ZSTD_memmove(oLitEnd, match, length1);
+        op = oLitEnd + length1;
+        sequence.matchLength -= length1;
+        match = prefixStart;
+        }
+    }
+    /* Match within prefix of 1 or more bytes */
+    assert(op <= oMatchEnd);
+    assert(oMatchEnd <= oend_w);
+    assert(match >= prefixStart);
+    assert(sequence.matchLength >= 1);
+
+    /* Nearly all offsets are >= WILDCOPY_VECLEN bytes, which means we can use wildcopy
+     * without overlap checking.
+     */
+    if (LIKELY(sequence.offset >= WILDCOPY_VECLEN)) {
+        /* We bet on a full wildcopy for matches, since we expect matches to be
+         * longer than literals (in general). In silesia, ~10% of matches are longer
+         * than 16 bytes.
+         */
+        ZSTD_wildcopy(op, match, (ptrdiff_t)sequence.matchLength, ZSTD_no_overlap);
+        return sequenceLength;
+    }
+    assert(sequence.offset < WILDCOPY_VECLEN);
+
+    /* Copy 8 bytes and spread the offset to be >= 8. */
+    ZSTD_overlapCopy8(&op, &match, sequence.offset);
+
+    /* If the match length is > 8 bytes, then continue with the wildcopy. */
+    if (sequence.matchLength > 8) {
+        assert(op < oMatchEnd);
+        ZSTD_wildcopy(op, match, (ptrdiff_t)sequence.matchLength - 8, ZSTD_overlap_src_before_dst);
+    }
+    return sequenceLength;
+}
+
+HINT_INLINE
+ZSTD_ALLOW_POINTER_OVERFLOW_ATTR
+size_t ZSTD_execSequenceSplitLitBuffer(BYTE* op,
+    BYTE* const oend, const BYTE* const oend_w, seq_t sequence,
+    const BYTE** litPtr, const BYTE* const litLimit,
+    const BYTE* const prefixStart, const BYTE* const virtualStart, const BYTE* const dictEnd)
+{
+    BYTE* const oLitEnd = op + sequence.litLength;
+    size_t const sequenceLength = sequence.litLength + sequence.matchLength;
+    BYTE* const oMatchEnd = op + sequenceLength;   /* risk : address space overflow (32-bits) */
+    const BYTE* const iLitEnd = *litPtr + sequence.litLength;
+    const BYTE* match = oLitEnd - sequence.offset;
+
+    assert(op != NULL /* Precondition */);
+    assert(oend_w < oend /* No underflow */);
+    /* Handle edge cases in a slow path:
+     *   - Read beyond end of literals
+     *   - Match end is within WILDCOPY_OVERLIMIT of oend
+     *   - 32-bit mode and the match length overflows
+     */
+    if (UNLIKELY(
+            iLitEnd > litLimit ||
+            oMatchEnd > oend_w ||
+            (MEM_32bits() && (size_t)(oend - op) < sequenceLength + WILDCOPY_OVERLENGTH)))
+        return ZSTD_execSequenceEndSplitLitBuffer(op, oend, oend_w, sequence, litPtr, litLimit, prefixStart, virtualStart, dictEnd);
+
+    /* Assumptions (everything else goes into ZSTD_execSequenceEnd()) */
+    assert(op <= oLitEnd /* No overflow */);
+    assert(oLitEnd < oMatchEnd /* Non-zero match & no overflow */);
+    assert(oMatchEnd <= oend /* No underflow */);
+    assert(iLitEnd <= litLimit /* Literal length is in bounds */);
+    assert(oLitEnd <= oend_w /* Can wildcopy literals */);
+    assert(oMatchEnd <= oend_w /* Can wildcopy matches */);
+
+    /* Copy Literals:
+     * Split out litLength <= 16 since it is nearly always true. +1.6% on gcc-9.
+     * We likely don't need the full 32-byte wildcopy.
+     */
+    assert(WILDCOPY_OVERLENGTH >= 16);
+    ZSTD_copy16(op, (*litPtr));
+    if (UNLIKELY(sequence.litLength > 16)) {
+        ZSTD_wildcopy(op+16, (*litPtr)+16, sequence.litLength-16, ZSTD_no_overlap);
+    }
+    op = oLitEnd;
+    *litPtr = iLitEnd;   /* update for next sequence */
+
+    /* Copy Match */
+    if (sequence.offset > (size_t)(oLitEnd - prefixStart)) {
+        /* offset beyond prefix -> go into extDict */
+        RETURN_ERROR_IF(UNLIKELY(sequence.offset > (size_t)(oLitEnd - virtualStart)), corruption_detected, "");
+        match = dictEnd + (match - prefixStart);
+        if (match + sequence.matchLength <= dictEnd) {
+            ZSTD_memmove(oLitEnd, match, sequence.matchLength);
+            return sequenceLength;
+        }
+        /* span extDict & currentPrefixSegment */
+        {   size_t const length1 = dictEnd - match;
+            ZSTD_memmove(oLitEnd, match, length1);
+            op = oLitEnd + length1;
+            sequence.matchLength -= length1;
+            match = prefixStart;
+    }   }
+    /* Match within prefix of 1 or more bytes */
+    assert(op <= oMatchEnd);
+    assert(oMatchEnd <= oend_w);
+    assert(match >= prefixStart);
+    assert(sequence.matchLength >= 1);
+
+    /* Nearly all offsets are >= WILDCOPY_VECLEN bytes, which means we can use wildcopy
+     * without overlap checking.
+     */
+    if (LIKELY(sequence.offset >= WILDCOPY_VECLEN)) {
+        /* We bet on a full wildcopy for matches, since we expect matches to be
+         * longer than literals (in general). In silesia, ~10% of matches are longer
+         * than 16 bytes.
+         */
+        ZSTD_wildcopy(op, match, (ptrdiff_t)sequence.matchLength, ZSTD_no_overlap);
+        return sequenceLength;
+    }
+    assert(sequence.offset < WILDCOPY_VECLEN);
+
+    /* Copy 8 bytes and spread the offset to be >= 8. */
+    ZSTD_overlapCopy8(&op, &match, sequence.offset);
+
+    /* If the match length is > 8 bytes, then continue with the wildcopy. */
+    if (sequence.matchLength > 8) {
+        assert(op < oMatchEnd);
+        ZSTD_wildcopy(op, match, (ptrdiff_t)sequence.matchLength-8, ZSTD_overlap_src_before_dst);
+    }
+    return sequenceLength;
+}
+
+
+static void
+ZSTD_initFseState(ZSTD_fseState* DStatePtr, BIT_DStream_t* bitD, const ZSTD_seqSymbol* dt)
+{
+    const void* ptr = dt;
+    const ZSTD_seqSymbol_header* const DTableH = (const ZSTD_seqSymbol_header*)ptr;
+    DStatePtr->state = BIT_readBits(bitD, DTableH->tableLog);
+    DEBUGLOG(6, "ZSTD_initFseState : val=%u using %u bits",
+                (U32)DStatePtr->state, DTableH->tableLog);
+    BIT_reloadDStream(bitD);
+    DStatePtr->table = dt + 1;
+}
+
+FORCE_INLINE_TEMPLATE void
+ZSTD_updateFseStateWithDInfo(ZSTD_fseState* DStatePtr, BIT_DStream_t* bitD, U16 nextState, U32 nbBits)
+{
+    size_t const lowBits = BIT_readBits(bitD, nbBits);
+    DStatePtr->state = nextState + lowBits;
+}
+
+/* We need to add at most (ZSTD_WINDOWLOG_MAX_32 - 1) bits to read the maximum
+ * offset bits. But we can only read at most STREAM_ACCUMULATOR_MIN_32
+ * bits before reloading. This value is the maximum number of bytes we read
+ * after reloading when we are decoding long offsets.
+ */
+#define LONG_OFFSETS_MAX_EXTRA_BITS_32                       \
+    (ZSTD_WINDOWLOG_MAX_32 > STREAM_ACCUMULATOR_MIN_32       \
+        ? ZSTD_WINDOWLOG_MAX_32 - STREAM_ACCUMULATOR_MIN_32  \
+        : 0)
+
+typedef enum { ZSTD_lo_isRegularOffset, ZSTD_lo_isLongOffset=1 } ZSTD_longOffset_e;
+
+/**
+ * ZSTD_decodeSequence():
+ * @p longOffsets : tells the decoder to reload more bit while decoding large offsets
+ *                  only used in 32-bit mode
+ * @return : Sequence (litL + matchL + offset)
+ */
+FORCE_INLINE_TEMPLATE seq_t
+ZSTD_decodeSequence(seqState_t* seqState, const ZSTD_longOffset_e longOffsets, const int isLastSeq)
+{
+    seq_t seq;
+    /*
+     * ZSTD_seqSymbol is a 64 bits wide structure.
+     * It can be loaded in one operation
+     * and its fields extracted by simply shifting or bit-extracting on aarch64.
+     * GCC doesn't recognize this and generates more unnecessary ldr/ldrb/ldrh
+     * operations that cause performance drop. This can be avoided by using this
+     * ZSTD_memcpy hack.
+     */
+#if defined(__aarch64__) && (defined(__GNUC__) && !defined(__clang__))
+    ZSTD_seqSymbol llDInfoS, mlDInfoS, ofDInfoS;
+    ZSTD_seqSymbol* const llDInfo = &llDInfoS;
+    ZSTD_seqSymbol* const mlDInfo = &mlDInfoS;
+    ZSTD_seqSymbol* const ofDInfo = &ofDInfoS;
+    ZSTD_memcpy(llDInfo, seqState->stateLL.table + seqState->stateLL.state, sizeof(ZSTD_seqSymbol));
+    ZSTD_memcpy(mlDInfo, seqState->stateML.table + seqState->stateML.state, sizeof(ZSTD_seqSymbol));
+    ZSTD_memcpy(ofDInfo, seqState->stateOffb.table + seqState->stateOffb.state, sizeof(ZSTD_seqSymbol));
+#else
+    const ZSTD_seqSymbol* const llDInfo = seqState->stateLL.table + seqState->stateLL.state;
+    const ZSTD_seqSymbol* const mlDInfo = seqState->stateML.table + seqState->stateML.state;
+    const ZSTD_seqSymbol* const ofDInfo = seqState->stateOffb.table + seqState->stateOffb.state;
+#endif
+    seq.matchLength = mlDInfo->baseValue;
+    seq.litLength = llDInfo->baseValue;
+    {   U32 const ofBase = ofDInfo->baseValue;
+        BYTE const llBits = llDInfo->nbAdditionalBits;
+        BYTE const mlBits = mlDInfo->nbAdditionalBits;
+        BYTE const ofBits = ofDInfo->nbAdditionalBits;
+        BYTE const totalBits = llBits+mlBits+ofBits;
+
+        U16 const llNext = llDInfo->nextState;
+        U16 const mlNext = mlDInfo->nextState;
+        U16 const ofNext = ofDInfo->nextState;
+        U32 const llnbBits = llDInfo->nbBits;
+        U32 const mlnbBits = mlDInfo->nbBits;
+        U32 const ofnbBits = ofDInfo->nbBits;
+
+        assert(llBits <= MaxLLBits);
+        assert(mlBits <= MaxMLBits);
+        assert(ofBits <= MaxOff);
+        /*
+         * As gcc has better branch and block analyzers, sometimes it is only
+         * valuable to mark likeliness for clang, it gives around 3-4% of
+         * performance.
+         */
+
+        /* sequence */
+        {   size_t offset;
+            if (ofBits > 1) {
+                ZSTD_STATIC_ASSERT(ZSTD_lo_isLongOffset == 1);
+                ZSTD_STATIC_ASSERT(LONG_OFFSETS_MAX_EXTRA_BITS_32 == 5);
+                ZSTD_STATIC_ASSERT(STREAM_ACCUMULATOR_MIN_32 > LONG_OFFSETS_MAX_EXTRA_BITS_32);
+                ZSTD_STATIC_ASSERT(STREAM_ACCUMULATOR_MIN_32 - LONG_OFFSETS_MAX_EXTRA_BITS_32 >= MaxMLBits);
+                if (MEM_32bits() && longOffsets && (ofBits >= STREAM_ACCUMULATOR_MIN_32)) {
+                    /* Always read extra bits, this keeps the logic simple,
+                     * avoids branches, and avoids accidentally reading 0 bits.
+                     */
+                    U32 const extraBits = LONG_OFFSETS_MAX_EXTRA_BITS_32;
+                    offset = ofBase + (BIT_readBitsFast(&seqState->DStream, ofBits - extraBits) << extraBits);
+                    BIT_reloadDStream(&seqState->DStream);
+                    offset += BIT_readBitsFast(&seqState->DStream, extraBits);
+                } else {
+                    offset = ofBase + BIT_readBitsFast(&seqState->DStream, ofBits/*>0*/);   /* <=  (ZSTD_WINDOWLOG_MAX-1) bits */
+                    if (MEM_32bits()) BIT_reloadDStream(&seqState->DStream);
+                }
+                seqState->prevOffset[2] = seqState->prevOffset[1];
+                seqState->prevOffset[1] = seqState->prevOffset[0];
+                seqState->prevOffset[0] = offset;
+            } else {
+                U32 const ll0 = (llDInfo->baseValue == 0);
+                if (LIKELY((ofBits == 0))) {
+                    offset = seqState->prevOffset[ll0];
+                    seqState->prevOffset[1] = seqState->prevOffset[!ll0];
+                    seqState->prevOffset[0] = offset;
+                } else {
+                    offset = ofBase + ll0 + BIT_readBitsFast(&seqState->DStream, 1);
+                    {   size_t temp = (offset==3) ? seqState->prevOffset[0] - 1 : seqState->prevOffset[offset];
+                        temp -= !temp; /* 0 is not valid: input corrupted => force offset to -1 => corruption detected at execSequence */
+                        if (offset != 1) seqState->prevOffset[2] = seqState->prevOffset[1];
+                        seqState->prevOffset[1] = seqState->prevOffset[0];
+                        seqState->prevOffset[0] = offset = temp;
+            }   }   }
+            seq.offset = offset;
+        }
+
+        if (mlBits > 0)
+            seq.matchLength += BIT_readBitsFast(&seqState->DStream, mlBits/*>0*/);
+
+        if (MEM_32bits() && (mlBits+llBits >= STREAM_ACCUMULATOR_MIN_32-LONG_OFFSETS_MAX_EXTRA_BITS_32))
+            BIT_reloadDStream(&seqState->DStream);
+        if (MEM_64bits() && UNLIKELY(totalBits >= STREAM_ACCUMULATOR_MIN_64-(LLFSELog+MLFSELog+OffFSELog)))
+            BIT_reloadDStream(&seqState->DStream);
+        /* Ensure there are enough bits to read the rest of data in 64-bit mode. */
+        ZSTD_STATIC_ASSERT(16+LLFSELog+MLFSELog+OffFSELog < STREAM_ACCUMULATOR_MIN_64);
+
+        if (llBits > 0)
+            seq.litLength += BIT_readBitsFast(&seqState->DStream, llBits/*>0*/);
+
+        if (MEM_32bits())
+            BIT_reloadDStream(&seqState->DStream);
+
+        DEBUGLOG(6, "seq: litL=%u, matchL=%u, offset=%u",
+                    (U32)seq.litLength, (U32)seq.matchLength, (U32)seq.offset);
+
+        if (!isLastSeq) {
+            /* don't update FSE state for last Sequence */
+            ZSTD_updateFseStateWithDInfo(&seqState->stateLL, &seqState->DStream, llNext, llnbBits);    /* <=  9 bits */
+            ZSTD_updateFseStateWithDInfo(&seqState->stateML, &seqState->DStream, mlNext, mlnbBits);    /* <=  9 bits */
+            if (MEM_32bits()) BIT_reloadDStream(&seqState->DStream);    /* <= 18 bits */
+            ZSTD_updateFseStateWithDInfo(&seqState->stateOffb, &seqState->DStream, ofNext, ofnbBits);  /* <=  8 bits */
+            BIT_reloadDStream(&seqState->DStream);
+        }
+    }
+
+    return seq;
+}
+
+#if defined(FUZZING_BUILD_MODE_UNSAFE_FOR_PRODUCTION) && defined(FUZZING_ASSERT_VALID_SEQUENCE)
+#if DEBUGLEVEL >= 1
+static int ZSTD_dictionaryIsActive(ZSTD_DCtx const* dctx, BYTE const* prefixStart, BYTE const* oLitEnd)
+{
+    size_t const windowSize = dctx->fParams.windowSize;
+    /* No dictionary used. */
+    if (dctx->dictContentEndForFuzzing == NULL) return 0;
+    /* Dictionary is our prefix. */
+    if (prefixStart == dctx->dictContentBeginForFuzzing) return 1;
+    /* Dictionary is not our ext-dict. */
+    if (dctx->dictEnd != dctx->dictContentEndForFuzzing) return 0;
+    /* Dictionary is not within our window size. */
+    if ((size_t)(oLitEnd - prefixStart) >= windowSize) return 0;
+    /* Dictionary is active. */
+    return 1;
+}
+#endif
+
+static void ZSTD_assertValidSequence(
+        ZSTD_DCtx const* dctx,
+        BYTE const* op, BYTE const* oend,
+        seq_t const seq,
+        BYTE const* prefixStart, BYTE const* virtualStart)
+{
+#if DEBUGLEVEL >= 1
+    if (dctx->isFrameDecompression) {
+        size_t const windowSize = dctx->fParams.windowSize;
+        size_t const sequenceSize = seq.litLength + seq.matchLength;
+        BYTE const* const oLitEnd = op + seq.litLength;
+        DEBUGLOG(6, "Checking sequence: litL=%u matchL=%u offset=%u",
+                (U32)seq.litLength, (U32)seq.matchLength, (U32)seq.offset);
+        assert(op <= oend);
+        assert((size_t)(oend - op) >= sequenceSize);
+        assert(sequenceSize <= ZSTD_blockSizeMax(dctx));
+        if (ZSTD_dictionaryIsActive(dctx, prefixStart, oLitEnd)) {
+            size_t const dictSize = (size_t)((char const*)dctx->dictContentEndForFuzzing - (char const*)dctx->dictContentBeginForFuzzing);
+            /* Offset must be within the dictionary. */
+            assert(seq.offset <= (size_t)(oLitEnd - virtualStart));
+            assert(seq.offset <= windowSize + dictSize);
+        } else {
+            /* Offset must be within our window. */
+            assert(seq.offset <= windowSize);
+        }
+    }
+#else
+    (void)dctx, (void)op, (void)oend, (void)seq, (void)prefixStart, (void)virtualStart;
+#endif
+}
+#endif
+
+#ifndef ZSTD_FORCE_DECOMPRESS_SEQUENCES_LONG
+
+
+FORCE_INLINE_TEMPLATE size_t
+DONT_VECTORIZE
+ZSTD_decompressSequences_bodySplitLitBuffer( ZSTD_DCtx* dctx,
+                               void* dst, size_t maxDstSize,
+                         const void* seqStart, size_t seqSize, int nbSeq,
+                         const ZSTD_longOffset_e isLongOffset)
+{
+    const BYTE* ip = (const BYTE*)seqStart;
+    const BYTE* const iend = ip + seqSize;
+    BYTE* const ostart = (BYTE*)dst;
+    BYTE* const oend = ZSTD_maybeNullPtrAdd(ostart, maxDstSize);
+    BYTE* op = ostart;
+    const BYTE* litPtr = dctx->litPtr;
+    const BYTE* litBufferEnd = dctx->litBufferEnd;
+    const BYTE* const prefixStart = (const BYTE*) (dctx->prefixStart);
+    const BYTE* const vBase = (const BYTE*) (dctx->virtualStart);
+    const BYTE* const dictEnd = (const BYTE*) (dctx->dictEnd);
+    DEBUGLOG(5, "ZSTD_decompressSequences_bodySplitLitBuffer (%i seqs)", nbSeq);
+
+    /* Literals are split between internal buffer & output buffer */
+    if (nbSeq) {
+        seqState_t seqState;
+        dctx->fseEntropy = 1;
+        { U32 i; for (i=0; i<ZSTD_REP_NUM; i++) seqState.prevOffset[i] = dctx->entropy.rep[i]; }
+        RETURN_ERROR_IF(
+            ERR_isError(BIT_initDStream(&seqState.DStream, ip, iend-ip)),
+            corruption_detected, "");
+        ZSTD_initFseState(&seqState.stateLL, &seqState.DStream, dctx->LLTptr);
+        ZSTD_initFseState(&seqState.stateOffb, &seqState.DStream, dctx->OFTptr);
+        ZSTD_initFseState(&seqState.stateML, &seqState.DStream, dctx->MLTptr);
+        assert(dst != NULL);
+
+        ZSTD_STATIC_ASSERT(
+                BIT_DStream_unfinished < BIT_DStream_completed &&
+                BIT_DStream_endOfBuffer < BIT_DStream_completed &&
+                BIT_DStream_completed < BIT_DStream_overflow);
+
+        /* decompress without overrunning litPtr begins */
+        {   seq_t sequence = {0,0,0};  /* some static analyzer believe that @sequence is not initialized (it necessarily is, since for(;;) loop as at least one iteration) */
+            /* Align the decompression loop to 32 + 16 bytes.
+                *
+                * zstd compiled with gcc-9 on an Intel i9-9900k shows 10% decompression
+                * speed swings based on the alignment of the decompression loop. This
+                * performance swing is caused by parts of the decompression loop falling
+                * out of the DSB. The entire decompression loop should fit in the DSB,
+                * when it can't we get much worse performance. You can measure if you've
+                * hit the good case or the bad case with this perf command for some
+                * compressed file test.zst:
+                *
+                *   perf stat -e cycles -e instructions -e idq.all_dsb_cycles_any_uops \
+                *             -e idq.all_mite_cycles_any_uops -- ./zstd -tq test.zst
+                *
+                * If you see most cycles served out of the MITE you've hit the bad case.
+                * If you see most cycles served out of the DSB you've hit the good case.
+                * If it is pretty even then you may be in an okay case.
+                *
+                * This issue has been reproduced on the following CPUs:
+                *   - Kabylake: Macbook Pro (15-inch, 2019) 2.4 GHz Intel Core i9
+                *               Use Instruments->Counters to get DSB/MITE cycles.
+                *               I never got performance swings, but I was able to
+                *               go from the good case of mostly DSB to half of the
+                *               cycles served from MITE.
+                *   - Coffeelake: Intel i9-9900k
+                *   - Coffeelake: Intel i7-9700k
+                *
+                * I haven't been able to reproduce the instability or DSB misses on any
+                * of the following CPUS:
+                *   - Haswell
+                *   - Broadwell: Intel(R) Xeon(R) CPU E5-2680 v4 @ 2.40GH
+                *   - Skylake
+                *
+                * Alignment is done for each of the three major decompression loops:
+                *   - ZSTD_decompressSequences_bodySplitLitBuffer - presplit section of the literal buffer
+                *   - ZSTD_decompressSequences_bodySplitLitBuffer - postsplit section of the literal buffer
+                *   - ZSTD_decompressSequences_body
+                * Alignment choices are made to minimize large swings on bad cases and influence on performance
+                * from changes external to this code, rather than to overoptimize on the current commit.
+                *
+                * If you are seeing performance stability this script can help test.
+                * It tests on 4 commits in zstd where I saw performance change.
+                *
+                *   https://gist.github.com/terrelln/9889fc06a423fd5ca6e99351564473f4
+                */
+#if defined(__GNUC__) && defined(__x86_64__)
+            __asm__(".p2align 6");
+#  if __GNUC__ >= 7
+	    /* good for gcc-7, gcc-9, and gcc-11 */
+            __asm__("nop");
+            __asm__(".p2align 5");
+            __asm__("nop");
+            __asm__(".p2align 4");
+#    if __GNUC__ == 8 || __GNUC__ == 10
+	    /* good for gcc-8 and gcc-10 */
+            __asm__("nop");
+            __asm__(".p2align 3");
+#    endif
+#  endif
+#endif
+
+            /* Handle the initial state where litBuffer is currently split between dst and litExtraBuffer */
+            for ( ; nbSeq; nbSeq--) {
+                sequence = ZSTD_decodeSequence(&seqState, isLongOffset, nbSeq==1);
+                if (litPtr + sequence.litLength > dctx->litBufferEnd) break;
+                {   size_t const oneSeqSize = ZSTD_execSequenceSplitLitBuffer(op, oend, litPtr + sequence.litLength - WILDCOPY_OVERLENGTH, sequence, &litPtr, litBufferEnd, prefixStart, vBase, dictEnd);
+#if defined(FUZZING_BUILD_MODE_UNSAFE_FOR_PRODUCTION) && defined(FUZZING_ASSERT_VALID_SEQUENCE)
+                    assert(!ZSTD_isError(oneSeqSize));
+                    ZSTD_assertValidSequence(dctx, op, oend, sequence, prefixStart, vBase);
+#endif
+                    if (UNLIKELY(ZSTD_isError(oneSeqSize)))
+                        return oneSeqSize;
+                    DEBUGLOG(6, "regenerated sequence size : %u", (U32)oneSeqSize);
+                    op += oneSeqSize;
+            }   }
+            DEBUGLOG(6, "reached: (litPtr + sequence.litLength > dctx->litBufferEnd)");
+
+            /* If there are more sequences, they will need to read literals from litExtraBuffer; copy over the remainder from dst and update litPtr and litEnd */
+            if (nbSeq > 0) {
+                const size_t leftoverLit = dctx->litBufferEnd - litPtr;
+                DEBUGLOG(6, "There are %i sequences left, and %zu/%zu literals left in buffer", nbSeq, leftoverLit, sequence.litLength);
+                if (leftoverLit) {
+                    RETURN_ERROR_IF(leftoverLit > (size_t)(oend - op), dstSize_tooSmall, "remaining lit must fit within dstBuffer");
+                    ZSTD_safecopyDstBeforeSrc(op, litPtr, leftoverLit);
+                    sequence.litLength -= leftoverLit;
+                    op += leftoverLit;
+                }
+                litPtr = dctx->litExtraBuffer;
+                litBufferEnd = dctx->litExtraBuffer + ZSTD_LITBUFFEREXTRASIZE;
+                dctx->litBufferLocation = ZSTD_not_in_dst;
+                {   size_t const oneSeqSize = ZSTD_execSequence(op, oend, sequence, &litPtr, litBufferEnd, prefixStart, vBase, dictEnd);
+#if defined(FUZZING_BUILD_MODE_UNSAFE_FOR_PRODUCTION) && defined(FUZZING_ASSERT_VALID_SEQUENCE)
+                    assert(!ZSTD_isError(oneSeqSize));
+                    ZSTD_assertValidSequence(dctx, op, oend, sequence, prefixStart, vBase);
+#endif
+                    if (UNLIKELY(ZSTD_isError(oneSeqSize)))
+                        return oneSeqSize;
+                    DEBUGLOG(6, "regenerated sequence size : %u", (U32)oneSeqSize);
+                    op += oneSeqSize;
+                }
+                nbSeq--;
+            }
+        }
+
+        if (nbSeq > 0) {
+            /* there is remaining lit from extra buffer */
+
+#if defined(__GNUC__) && defined(__x86_64__)
+            __asm__(".p2align 6");
+            __asm__("nop");
+#  if __GNUC__ != 7
+            /* worse for gcc-7 better for gcc-8, gcc-9, and gcc-10 and clang */
+            __asm__(".p2align 4");
+            __asm__("nop");
+            __asm__(".p2align 3");
+#  elif __GNUC__ >= 11
+            __asm__(".p2align 3");
+#  else
+            __asm__(".p2align 5");
+            __asm__("nop");
+            __asm__(".p2align 3");
+#  endif
+#endif
+
+            for ( ; nbSeq ; nbSeq--) {
+                seq_t const sequence = ZSTD_decodeSequence(&seqState, isLongOffset, nbSeq==1);
+                size_t const oneSeqSize = ZSTD_execSequence(op, oend, sequence, &litPtr, litBufferEnd, prefixStart, vBase, dictEnd);
+#if defined(FUZZING_BUILD_MODE_UNSAFE_FOR_PRODUCTION) && defined(FUZZING_ASSERT_VALID_SEQUENCE)
+                assert(!ZSTD_isError(oneSeqSize));
+                ZSTD_assertValidSequence(dctx, op, oend, sequence, prefixStart, vBase);
+#endif
+                if (UNLIKELY(ZSTD_isError(oneSeqSize)))
+                    return oneSeqSize;
+                DEBUGLOG(6, "regenerated sequence size : %u", (U32)oneSeqSize);
+                op += oneSeqSize;
+            }
+        }
+
+        /* check if reached exact end */
+        DEBUGLOG(5, "ZSTD_decompressSequences_bodySplitLitBuffer: after decode loop, remaining nbSeq : %i", nbSeq);
+        RETURN_ERROR_IF(nbSeq, corruption_detected, "");
+        DEBUGLOG(5, "bitStream : start=%p, ptr=%p, bitsConsumed=%u", seqState.DStream.start, seqState.DStream.ptr, seqState.DStream.bitsConsumed);
+        RETURN_ERROR_IF(!BIT_endOfDStream(&seqState.DStream), corruption_detected, "");
+        /* save reps for next block */
+        { U32 i; for (i=0; i<ZSTD_REP_NUM; i++) dctx->entropy.rep[i] = (U32)(seqState.prevOffset[i]); }
+    }
+
+    /* last literal segment */
+    if (dctx->litBufferLocation == ZSTD_split) {
+        /* split hasn't been reached yet, first get dst then copy litExtraBuffer */
+        size_t const lastLLSize = (size_t)(litBufferEnd - litPtr);
+        DEBUGLOG(6, "copy last literals from segment : %u", (U32)lastLLSize);
+        RETURN_ERROR_IF(lastLLSize > (size_t)(oend - op), dstSize_tooSmall, "");
+        if (op != NULL) {
+            ZSTD_memmove(op, litPtr, lastLLSize);
+            op += lastLLSize;
+        }
+        litPtr = dctx->litExtraBuffer;
+        litBufferEnd = dctx->litExtraBuffer + ZSTD_LITBUFFEREXTRASIZE;
+        dctx->litBufferLocation = ZSTD_not_in_dst;
+    }
+    /* copy last literals from internal buffer */
+    {   size_t const lastLLSize = (size_t)(litBufferEnd - litPtr);
+        DEBUGLOG(6, "copy last literals from internal buffer : %u", (U32)lastLLSize);
+        RETURN_ERROR_IF(lastLLSize > (size_t)(oend-op), dstSize_tooSmall, "");
+        if (op != NULL) {
+            ZSTD_memcpy(op, litPtr, lastLLSize);
+            op += lastLLSize;
+    }   }
+
+    DEBUGLOG(6, "decoded block of size %u bytes", (U32)(op - ostart));
+    return (size_t)(op - ostart);
+}
+
+FORCE_INLINE_TEMPLATE size_t
+DONT_VECTORIZE
+ZSTD_decompressSequences_body(ZSTD_DCtx* dctx,
+    void* dst, size_t maxDstSize,
+    const void* seqStart, size_t seqSize, int nbSeq,
+    const ZSTD_longOffset_e isLongOffset)
+{
+    const BYTE* ip = (const BYTE*)seqStart;
+    const BYTE* const iend = ip + seqSize;
+    BYTE* const ostart = (BYTE*)dst;
+    BYTE* const oend = dctx->litBufferLocation == ZSTD_not_in_dst ? ZSTD_maybeNullPtrAdd(ostart, maxDstSize) : dctx->litBuffer;
+    BYTE* op = ostart;
+    const BYTE* litPtr = dctx->litPtr;
+    const BYTE* const litEnd = litPtr + dctx->litSize;
+    const BYTE* const prefixStart = (const BYTE*)(dctx->prefixStart);
+    const BYTE* const vBase = (const BYTE*)(dctx->virtualStart);
+    const BYTE* const dictEnd = (const BYTE*)(dctx->dictEnd);
+    DEBUGLOG(5, "ZSTD_decompressSequences_body: nbSeq = %d", nbSeq);
+
+    /* Regen sequences */
+    if (nbSeq) {
+        seqState_t seqState;
+        dctx->fseEntropy = 1;
+        { U32 i; for (i = 0; i < ZSTD_REP_NUM; i++) seqState.prevOffset[i] = dctx->entropy.rep[i]; }
+        RETURN_ERROR_IF(
+            ERR_isError(BIT_initDStream(&seqState.DStream, ip, iend - ip)),
+            corruption_detected, "");
+        ZSTD_initFseState(&seqState.stateLL, &seqState.DStream, dctx->LLTptr);
+        ZSTD_initFseState(&seqState.stateOffb, &seqState.DStream, dctx->OFTptr);
+        ZSTD_initFseState(&seqState.stateML, &seqState.DStream, dctx->MLTptr);
+        assert(dst != NULL);
+
+#if defined(__GNUC__) && defined(__x86_64__)
+            __asm__(".p2align 6");
+            __asm__("nop");
+#  if __GNUC__ >= 7
+            __asm__(".p2align 5");
+            __asm__("nop");
+            __asm__(".p2align 3");
+#  else
+            __asm__(".p2align 4");
+            __asm__("nop");
+            __asm__(".p2align 3");
+#  endif
+#endif
+
+        for ( ; nbSeq ; nbSeq--) {
+            seq_t const sequence = ZSTD_decodeSequence(&seqState, isLongOffset, nbSeq==1);
+            size_t const oneSeqSize = ZSTD_execSequence(op, oend, sequence, &litPtr, litEnd, prefixStart, vBase, dictEnd);
+#if defined(FUZZING_BUILD_MODE_UNSAFE_FOR_PRODUCTION) && defined(FUZZING_ASSERT_VALID_SEQUENCE)
+            assert(!ZSTD_isError(oneSeqSize));
+            ZSTD_assertValidSequence(dctx, op, oend, sequence, prefixStart, vBase);
+#endif
+            if (UNLIKELY(ZSTD_isError(oneSeqSize)))
+                return oneSeqSize;
+            DEBUGLOG(6, "regenerated sequence size : %u", (U32)oneSeqSize);
+            op += oneSeqSize;
+        }
+
+        /* check if reached exact end */
+        assert(nbSeq == 0);
+        RETURN_ERROR_IF(!BIT_endOfDStream(&seqState.DStream), corruption_detected, "");
+        /* save reps for next block */
+        { U32 i; for (i=0; i<ZSTD_REP_NUM; i++) dctx->entropy.rep[i] = (U32)(seqState.prevOffset[i]); }
+    }
+
+    /* last literal segment */
+    {   size_t const lastLLSize = (size_t)(litEnd - litPtr);
+        DEBUGLOG(6, "copy last literals : %u", (U32)lastLLSize);
+        RETURN_ERROR_IF(lastLLSize > (size_t)(oend-op), dstSize_tooSmall, "");
+        if (op != NULL) {
+            ZSTD_memcpy(op, litPtr, lastLLSize);
+            op += lastLLSize;
+    }   }
+
+    DEBUGLOG(6, "decoded block of size %u bytes", (U32)(op - ostart));
+    return (size_t)(op - ostart);
+}
+
+static size_t
+ZSTD_decompressSequences_default(ZSTD_DCtx* dctx,
+                                 void* dst, size_t maxDstSize,
+                           const void* seqStart, size_t seqSize, int nbSeq,
+                           const ZSTD_longOffset_e isLongOffset)
+{
+    return ZSTD_decompressSequences_body(dctx, dst, maxDstSize, seqStart, seqSize, nbSeq, isLongOffset);
+}
+
+static size_t
+ZSTD_decompressSequencesSplitLitBuffer_default(ZSTD_DCtx* dctx,
+                                               void* dst, size_t maxDstSize,
+                                         const void* seqStart, size_t seqSize, int nbSeq,
+                                         const ZSTD_longOffset_e isLongOffset)
+{
+    return ZSTD_decompressSequences_bodySplitLitBuffer(dctx, dst, maxDstSize, seqStart, seqSize, nbSeq, isLongOffset);
+}
+#endif /* ZSTD_FORCE_DECOMPRESS_SEQUENCES_LONG */
+
+#ifndef ZSTD_FORCE_DECOMPRESS_SEQUENCES_SHORT
+
+FORCE_INLINE_TEMPLATE
+
+size_t ZSTD_prefetchMatch(size_t prefetchPos, seq_t const sequence,
+                   const BYTE* const prefixStart, const BYTE* const dictEnd)
+{
+    prefetchPos += sequence.litLength;
+    {   const BYTE* const matchBase = (sequence.offset > prefetchPos) ? dictEnd : prefixStart;
+        /* note : this operation can overflow when seq.offset is really too large, which can only happen when input is corrupted.
+         * No consequence though : memory address is only used for prefetching, not for dereferencing */
+        const BYTE* const match = ZSTD_wrappedPtrSub(ZSTD_wrappedPtrAdd(matchBase, prefetchPos), sequence.offset);
+        PREFETCH_L1(match); PREFETCH_L1(match+CACHELINE_SIZE);   /* note : it's safe to invoke PREFETCH() on any memory address, including invalid ones */
+    }
+    return prefetchPos + sequence.matchLength;
+}
+
+/* This decoding function employs prefetching
+ * to reduce latency impact of cache misses.
+ * It's generally employed when block contains a significant portion of long-distance matches
+ * or when coupled with a "cold" dictionary */
+FORCE_INLINE_TEMPLATE size_t
+ZSTD_decompressSequencesLong_body(
+                               ZSTD_DCtx* dctx,
+                               void* dst, size_t maxDstSize,
+                         const void* seqStart, size_t seqSize, int nbSeq,
+                         const ZSTD_longOffset_e isLongOffset)
+{
+    const BYTE* ip = (const BYTE*)seqStart;
+    const BYTE* const iend = ip + seqSize;
+    BYTE* const ostart = (BYTE*)dst;
+    BYTE* const oend = dctx->litBufferLocation == ZSTD_in_dst ? dctx->litBuffer : ZSTD_maybeNullPtrAdd(ostart, maxDstSize);
+    BYTE* op = ostart;
+    const BYTE* litPtr = dctx->litPtr;
+    const BYTE* litBufferEnd = dctx->litBufferEnd;
+    const BYTE* const prefixStart = (const BYTE*) (dctx->prefixStart);
+    const BYTE* const dictStart = (const BYTE*) (dctx->virtualStart);
+    const BYTE* const dictEnd = (const BYTE*) (dctx->dictEnd);
+
+    /* Regen sequences */
+    if (nbSeq) {
+#define STORED_SEQS 8
+#define STORED_SEQS_MASK (STORED_SEQS-1)
+#define ADVANCED_SEQS STORED_SEQS
+        seq_t sequences[STORED_SEQS];
+        int const seqAdvance = MIN(nbSeq, ADVANCED_SEQS);
+        seqState_t seqState;
+        int seqNb;
+        size_t prefetchPos = (size_t)(op-prefixStart); /* track position relative to prefixStart */
+
+        dctx->fseEntropy = 1;
+        { int i; for (i=0; i<ZSTD_REP_NUM; i++) seqState.prevOffset[i] = dctx->entropy.rep[i]; }
+        assert(dst != NULL);
+        assert(iend >= ip);
+        RETURN_ERROR_IF(
+            ERR_isError(BIT_initDStream(&seqState.DStream, ip, iend-ip)),
+            corruption_detected, "");
+        ZSTD_initFseState(&seqState.stateLL, &seqState.DStream, dctx->LLTptr);
+        ZSTD_initFseState(&seqState.stateOffb, &seqState.DStream, dctx->OFTptr);
+        ZSTD_initFseState(&seqState.stateML, &seqState.DStream, dctx->MLTptr);
+
+        /* prepare in advance */
+        for (seqNb=0; seqNb<seqAdvance; seqNb++) {
+            seq_t const sequence = ZSTD_decodeSequence(&seqState, isLongOffset, seqNb == nbSeq-1);
+            prefetchPos = ZSTD_prefetchMatch(prefetchPos, sequence, prefixStart, dictEnd);
+            sequences[seqNb] = sequence;
+        }
+
+        /* decompress without stomping litBuffer */
+        for (; seqNb < nbSeq; seqNb++) {
+            seq_t sequence = ZSTD_decodeSequence(&seqState, isLongOffset, seqNb == nbSeq-1);
+
+            if (dctx->litBufferLocation == ZSTD_split && litPtr + sequences[(seqNb - ADVANCED_SEQS) & STORED_SEQS_MASK].litLength > dctx->litBufferEnd) {
+                /* lit buffer is reaching split point, empty out the first buffer and transition to litExtraBuffer */
+                const size_t leftoverLit = dctx->litBufferEnd - litPtr;
+                if (leftoverLit)
+                {
+                    RETURN_ERROR_IF(leftoverLit > (size_t)(oend - op), dstSize_tooSmall, "remaining lit must fit within dstBuffer");
+                    ZSTD_safecopyDstBeforeSrc(op, litPtr, leftoverLit);
+                    sequences[(seqNb - ADVANCED_SEQS) & STORED_SEQS_MASK].litLength -= leftoverLit;
+                    op += leftoverLit;
+                }
+                litPtr = dctx->litExtraBuffer;
+                litBufferEnd = dctx->litExtraBuffer + ZSTD_LITBUFFEREXTRASIZE;
+                dctx->litBufferLocation = ZSTD_not_in_dst;
+                {   size_t const oneSeqSize = ZSTD_execSequence(op, oend, sequences[(seqNb - ADVANCED_SEQS) & STORED_SEQS_MASK], &litPtr, litBufferEnd, prefixStart, dictStart, dictEnd);
+#if defined(FUZZING_BUILD_MODE_UNSAFE_FOR_PRODUCTION) && defined(FUZZING_ASSERT_VALID_SEQUENCE)
+                    assert(!ZSTD_isError(oneSeqSize));
+                    ZSTD_assertValidSequence(dctx, op, oend, sequences[(seqNb - ADVANCED_SEQS) & STORED_SEQS_MASK], prefixStart, dictStart);
+#endif
+                    if (ZSTD_isError(oneSeqSize)) return oneSeqSize;
+
+                    prefetchPos = ZSTD_prefetchMatch(prefetchPos, sequence, prefixStart, dictEnd);
+                    sequences[seqNb & STORED_SEQS_MASK] = sequence;
+                    op += oneSeqSize;
+            }   }
+            else
+            {
+                /* lit buffer is either wholly contained in first or second split, or not split at all*/
+                size_t const oneSeqSize = dctx->litBufferLocation == ZSTD_split ?
+                    ZSTD_execSequenceSplitLitBuffer(op, oend, litPtr + sequences[(seqNb - ADVANCED_SEQS) & STORED_SEQS_MASK].litLength - WILDCOPY_OVERLENGTH, sequences[(seqNb - ADVANCED_SEQS) & STORED_SEQS_MASK], &litPtr, litBufferEnd, prefixStart, dictStart, dictEnd) :
+                    ZSTD_execSequence(op, oend, sequences[(seqNb - ADVANCED_SEQS) & STORED_SEQS_MASK], &litPtr, litBufferEnd, prefixStart, dictStart, dictEnd);
+#if defined(FUZZING_BUILD_MODE_UNSAFE_FOR_PRODUCTION) && defined(FUZZING_ASSERT_VALID_SEQUENCE)
+                assert(!ZSTD_isError(oneSeqSize));
+                ZSTD_assertValidSequence(dctx, op, oend, sequences[(seqNb - ADVANCED_SEQS) & STORED_SEQS_MASK], prefixStart, dictStart);
+#endif
+                if (ZSTD_isError(oneSeqSize)) return oneSeqSize;
+
+                prefetchPos = ZSTD_prefetchMatch(prefetchPos, sequence, prefixStart, dictEnd);
+                sequences[seqNb & STORED_SEQS_MASK] = sequence;
+                op += oneSeqSize;
+            }
+        }
+        RETURN_ERROR_IF(!BIT_endOfDStream(&seqState.DStream), corruption_detected, "");
+
+        /* finish queue */
+        seqNb -= seqAdvance;
+        for ( ; seqNb<nbSeq ; seqNb++) {
+            seq_t *sequence = &(sequences[seqNb&STORED_SEQS_MASK]);
+            if (dctx->litBufferLocation == ZSTD_split && litPtr + sequence->litLength > dctx->litBufferEnd) {
+                const size_t leftoverLit = dctx->litBufferEnd - litPtr;
+                if (leftoverLit) {
+                    RETURN_ERROR_IF(leftoverLit > (size_t)(oend - op), dstSize_tooSmall, "remaining lit must fit within dstBuffer");
+                    ZSTD_safecopyDstBeforeSrc(op, litPtr, leftoverLit);
+                    sequence->litLength -= leftoverLit;
+                    op += leftoverLit;
+                }
+                litPtr = dctx->litExtraBuffer;
+                litBufferEnd = dctx->litExtraBuffer + ZSTD_LITBUFFEREXTRASIZE;
+                dctx->litBufferLocation = ZSTD_not_in_dst;
+                {   size_t const oneSeqSize = ZSTD_execSequence(op, oend, *sequence, &litPtr, litBufferEnd, prefixStart, dictStart, dictEnd);
+#if defined(FUZZING_BUILD_MODE_UNSAFE_FOR_PRODUCTION) && defined(FUZZING_ASSERT_VALID_SEQUENCE)
+                    assert(!ZSTD_isError(oneSeqSize));
+                    ZSTD_assertValidSequence(dctx, op, oend, sequences[seqNb&STORED_SEQS_MASK], prefixStart, dictStart);
+#endif
+                    if (ZSTD_isError(oneSeqSize)) return oneSeqSize;
+                    op += oneSeqSize;
+                }
+            }
+            else
+            {
+                size_t const oneSeqSize = dctx->litBufferLocation == ZSTD_split ?
+                    ZSTD_execSequenceSplitLitBuffer(op, oend, litPtr + sequence->litLength - WILDCOPY_OVERLENGTH, *sequence, &litPtr, litBufferEnd, prefixStart, dictStart, dictEnd) :
+                    ZSTD_execSequence(op, oend, *sequence, &litPtr, litBufferEnd, prefixStart, dictStart, dictEnd);
+#if defined(FUZZING_BUILD_MODE_UNSAFE_FOR_PRODUCTION) && defined(FUZZING_ASSERT_VALID_SEQUENCE)
+                assert(!ZSTD_isError(oneSeqSize));
+                ZSTD_assertValidSequence(dctx, op, oend, sequences[seqNb&STORED_SEQS_MASK], prefixStart, dictStart);
+#endif
+                if (ZSTD_isError(oneSeqSize)) return oneSeqSize;
+                op += oneSeqSize;
+            }
+        }
+
+        /* save reps for next block */
+        { U32 i; for (i=0; i<ZSTD_REP_NUM; i++) dctx->entropy.rep[i] = (U32)(seqState.prevOffset[i]); }
+    }
+
+    /* last literal segment */
+    if (dctx->litBufferLocation == ZSTD_split) { /* first deplete literal buffer in dst, then copy litExtraBuffer */
+        size_t const lastLLSize = litBufferEnd - litPtr;
+        RETURN_ERROR_IF(lastLLSize > (size_t)(oend - op), dstSize_tooSmall, "");
+        if (op != NULL) {
+            ZSTD_memmove(op, litPtr, lastLLSize);
+            op += lastLLSize;
+        }
+        litPtr = dctx->litExtraBuffer;
+        litBufferEnd = dctx->litExtraBuffer + ZSTD_LITBUFFEREXTRASIZE;
+    }
+    {   size_t const lastLLSize = litBufferEnd - litPtr;
+        RETURN_ERROR_IF(lastLLSize > (size_t)(oend-op), dstSize_tooSmall, "");
+        if (op != NULL) {
+            ZSTD_memmove(op, litPtr, lastLLSize);
+            op += lastLLSize;
+        }
+    }
+
+    return (size_t)(op - ostart);
+}
+
+static size_t
+ZSTD_decompressSequencesLong_default(ZSTD_DCtx* dctx,
+                                 void* dst, size_t maxDstSize,
+                           const void* seqStart, size_t seqSize, int nbSeq,
+                           const ZSTD_longOffset_e isLongOffset)
+{
+    return ZSTD_decompressSequencesLong_body(dctx, dst, maxDstSize, seqStart, seqSize, nbSeq, isLongOffset);
+}
+#endif /* ZSTD_FORCE_DECOMPRESS_SEQUENCES_SHORT */
+
+
+
+#if DYNAMIC_BMI2
+
+#ifndef ZSTD_FORCE_DECOMPRESS_SEQUENCES_LONG
+static BMI2_TARGET_ATTRIBUTE size_t
+DONT_VECTORIZE
+ZSTD_decompressSequences_bmi2(ZSTD_DCtx* dctx,
+                                 void* dst, size_t maxDstSize,
+                           const void* seqStart, size_t seqSize, int nbSeq,
+                           const ZSTD_longOffset_e isLongOffset)
+{
+    return ZSTD_decompressSequences_body(dctx, dst, maxDstSize, seqStart, seqSize, nbSeq, isLongOffset);
+}
+static BMI2_TARGET_ATTRIBUTE size_t
+DONT_VECTORIZE
+ZSTD_decompressSequencesSplitLitBuffer_bmi2(ZSTD_DCtx* dctx,
+                                 void* dst, size_t maxDstSize,
+                           const void* seqStart, size_t seqSize, int nbSeq,
+                           const ZSTD_longOffset_e isLongOffset)
+{
+    return ZSTD_decompressSequences_bodySplitLitBuffer(dctx, dst, maxDstSize, seqStart, seqSize, nbSeq, isLongOffset);
+}
+#endif /* ZSTD_FORCE_DECOMPRESS_SEQUENCES_LONG */
+
+#ifndef ZSTD_FORCE_DECOMPRESS_SEQUENCES_SHORT
+static BMI2_TARGET_ATTRIBUTE size_t
+ZSTD_decompressSequencesLong_bmi2(ZSTD_DCtx* dctx,
+                                 void* dst, size_t maxDstSize,
+                           const void* seqStart, size_t seqSize, int nbSeq,
+                           const ZSTD_longOffset_e isLongOffset)
+{
+    return ZSTD_decompressSequencesLong_body(dctx, dst, maxDstSize, seqStart, seqSize, nbSeq, isLongOffset);
+}
+#endif /* ZSTD_FORCE_DECOMPRESS_SEQUENCES_SHORT */
+
+#endif /* DYNAMIC_BMI2 */
+
+#ifndef ZSTD_FORCE_DECOMPRESS_SEQUENCES_LONG
+static size_t
+ZSTD_decompressSequences(ZSTD_DCtx* dctx, void* dst, size_t maxDstSize,
+                   const void* seqStart, size_t seqSize, int nbSeq,
+                   const ZSTD_longOffset_e isLongOffset)
+{
+    DEBUGLOG(5, "ZSTD_decompressSequences");
+#if DYNAMIC_BMI2
+    if (ZSTD_DCtx_get_bmi2(dctx)) {
+        return ZSTD_decompressSequences_bmi2(dctx, dst, maxDstSize, seqStart, seqSize, nbSeq, isLongOffset);
+    }
+#endif
+    return ZSTD_decompressSequences_default(dctx, dst, maxDstSize, seqStart, seqSize, nbSeq, isLongOffset);
+}
+static size_t
+ZSTD_decompressSequencesSplitLitBuffer(ZSTD_DCtx* dctx, void* dst, size_t maxDstSize,
+                                 const void* seqStart, size_t seqSize, int nbSeq,
+                                 const ZSTD_longOffset_e isLongOffset)
+{
+    DEBUGLOG(5, "ZSTD_decompressSequencesSplitLitBuffer");
+#if DYNAMIC_BMI2
+    if (ZSTD_DCtx_get_bmi2(dctx)) {
+        return ZSTD_decompressSequencesSplitLitBuffer_bmi2(dctx, dst, maxDstSize, seqStart, seqSize, nbSeq, isLongOffset);
+    }
+#endif
+    return ZSTD_decompressSequencesSplitLitBuffer_default(dctx, dst, maxDstSize, seqStart, seqSize, nbSeq, isLongOffset);
+}
+#endif /* ZSTD_FORCE_DECOMPRESS_SEQUENCES_LONG */
+
+
+#ifndef ZSTD_FORCE_DECOMPRESS_SEQUENCES_SHORT
+/* ZSTD_decompressSequencesLong() :
+ * decompression function triggered when a minimum share of offsets is considered "long",
+ * aka out of cache.
+ * note : "long" definition seems overloaded here, sometimes meaning "wider than bitstream register", and sometimes meaning "farther than memory cache distance".
+ * This function will try to mitigate main memory latency through the use of prefetching */
+static size_t
+ZSTD_decompressSequencesLong(ZSTD_DCtx* dctx,
+                             void* dst, size_t maxDstSize,
+                             const void* seqStart, size_t seqSize, int nbSeq,
+                             const ZSTD_longOffset_e isLongOffset)
+{
+    DEBUGLOG(5, "ZSTD_decompressSequencesLong");
+#if DYNAMIC_BMI2
+    if (ZSTD_DCtx_get_bmi2(dctx)) {
+        return ZSTD_decompressSequencesLong_bmi2(dctx, dst, maxDstSize, seqStart, seqSize, nbSeq, isLongOffset);
+    }
+#endif
+  return ZSTD_decompressSequencesLong_default(dctx, dst, maxDstSize, seqStart, seqSize, nbSeq, isLongOffset);
+}
+#endif /* ZSTD_FORCE_DECOMPRESS_SEQUENCES_SHORT */
+
+
+/**
+ * @returns The total size of the history referenceable by zstd, including
+ * both the prefix and the extDict. At @p op any offset larger than this
+ * is invalid.
+ */
+static size_t ZSTD_totalHistorySize(BYTE* op, BYTE const* virtualStart)
+{
+    return (size_t)(op - virtualStart);
+}
+
+typedef struct {
+    unsigned longOffsetShare;
+    unsigned maxNbAdditionalBits;
+} ZSTD_OffsetInfo;
+
+/* ZSTD_getOffsetInfo() :
+ * condition : offTable must be valid
+ * @return : "share" of long offsets (arbitrarily defined as > (1<<23))
+ *           compared to maximum possible of (1<<OffFSELog),
+ *           as well as the maximum number additional bits required.
+ */
+static ZSTD_OffsetInfo
+ZSTD_getOffsetInfo(const ZSTD_seqSymbol* offTable, int nbSeq)
+{
+    ZSTD_OffsetInfo info = {0, 0};
+    /* If nbSeq == 0, then the offTable is uninitialized, but we have
+     * no sequences, so both values should be 0.
+     */
+    if (nbSeq != 0) {
+        const void* ptr = offTable;
+        U32 const tableLog = ((const ZSTD_seqSymbol_header*)ptr)[0].tableLog;
+        const ZSTD_seqSymbol* table = offTable + 1;
+        U32 const max = 1 << tableLog;
+        U32 u;
+        DEBUGLOG(5, "ZSTD_getLongOffsetsShare: (tableLog=%u)", tableLog);
+
+        assert(max <= (1 << OffFSELog));  /* max not too large */
+        for (u=0; u<max; u++) {
+            info.maxNbAdditionalBits = MAX(info.maxNbAdditionalBits, table[u].nbAdditionalBits);
+            if (table[u].nbAdditionalBits > 22) info.longOffsetShare += 1;
+        }
+
+        assert(tableLog <= OffFSELog);
+        info.longOffsetShare <<= (OffFSELog - tableLog);  /* scale to OffFSELog */
+    }
+
+    return info;
+}
+
+/**
+ * @returns The maximum offset we can decode in one read of our bitstream, without
+ * reloading more bits in the middle of the offset bits read. Any offsets larger
+ * than this must use the long offset decoder.
+ */
+static size_t ZSTD_maxShortOffset(void)
+{
+    if (MEM_64bits()) {
+        /* We can decode any offset without reloading bits.
+         * This might change if the max window size grows.
+         */
+        ZSTD_STATIC_ASSERT(ZSTD_WINDOWLOG_MAX <= 31);
+        return (size_t)-1;
+    } else {
+        /* The maximum offBase is (1 << (STREAM_ACCUMULATOR_MIN + 1)) - 1.
+         * This offBase would require STREAM_ACCUMULATOR_MIN extra bits.
+         * Then we have to subtract ZSTD_REP_NUM to get the maximum possible offset.
+         */
+        size_t const maxOffbase = ((size_t)1 << (STREAM_ACCUMULATOR_MIN + 1)) - 1;
+        size_t const maxOffset = maxOffbase - ZSTD_REP_NUM;
+        assert(ZSTD_highbit32((U32)maxOffbase) == STREAM_ACCUMULATOR_MIN);
+        return maxOffset;
+    }
+}
+
+size_t
+ZSTD_decompressBlock_internal(ZSTD_DCtx* dctx,
+                              void* dst, size_t dstCapacity,
+                        const void* src, size_t srcSize, const streaming_operation streaming)
+{   /* blockType == blockCompressed */
+    const BYTE* ip = (const BYTE*)src;
+    DEBUGLOG(5, "ZSTD_decompressBlock_internal (cSize : %u)", (unsigned)srcSize);
+
+    /* Note : the wording of the specification
+     * allows compressed block to be sized exactly ZSTD_blockSizeMax(dctx).
+     * This generally does not happen, as it makes little sense,
+     * since an uncompressed block would feature same size and have no decompression cost.
+     * Also, note that decoder from reference libzstd before < v1.5.4
+     * would consider this edge case as an error.
+     * As a consequence, avoid generating compressed blocks of size ZSTD_blockSizeMax(dctx)
+     * for broader compatibility with the deployed ecosystem of zstd decoders */
+    RETURN_ERROR_IF(srcSize > ZSTD_blockSizeMax(dctx), srcSize_wrong, "");
+
+    /* Decode literals section */
+    {   size_t const litCSize = ZSTD_decodeLiteralsBlock(dctx, src, srcSize, dst, dstCapacity, streaming);
+        DEBUGLOG(5, "ZSTD_decodeLiteralsBlock : cSize=%u, nbLiterals=%zu", (U32)litCSize, dctx->litSize);
+        if (ZSTD_isError(litCSize)) return litCSize;
+        ip += litCSize;
+        srcSize -= litCSize;
+    }
+
+    /* Build Decoding Tables */
+    {
+        /* Compute the maximum block size, which must also work when !frame and fParams are unset.
+         * Additionally, take the min with dstCapacity to ensure that the totalHistorySize fits in a size_t.
+         */
+        size_t const blockSizeMax = MIN(dstCapacity, ZSTD_blockSizeMax(dctx));
+        size_t const totalHistorySize = ZSTD_totalHistorySize(ZSTD_maybeNullPtrAdd((BYTE*)dst, blockSizeMax), (BYTE const*)dctx->virtualStart);
+        /* isLongOffset must be true if there are long offsets.
+         * Offsets are long if they are larger than ZSTD_maxShortOffset().
+         * We don't expect that to be the case in 64-bit mode.
+         *
+         * We check here to see if our history is large enough to allow long offsets.
+         * If it isn't, then we can't possible have (valid) long offsets. If the offset
+         * is invalid, then it is okay to read it incorrectly.
+         *
+         * If isLongOffsets is true, then we will later check our decoding table to see
+         * if it is even possible to generate long offsets.
+         */
+        ZSTD_longOffset_e isLongOffset = (ZSTD_longOffset_e)(MEM_32bits() && (totalHistorySize > ZSTD_maxShortOffset()));
+        /* These macros control at build-time which decompressor implementation
+         * we use. If neither is defined, we do some inspection and dispatch at
+         * runtime.
+         */
+#if !defined(ZSTD_FORCE_DECOMPRESS_SEQUENCES_SHORT) && \
+    !defined(ZSTD_FORCE_DECOMPRESS_SEQUENCES_LONG)
+        int usePrefetchDecoder = dctx->ddictIsCold;
+#else
+        /* Set to 1 to avoid computing offset info if we don't need to.
+         * Otherwise this value is ignored.
+         */
+        int usePrefetchDecoder = 1;
+#endif
+        int nbSeq;
+        size_t const seqHSize = ZSTD_decodeSeqHeaders(dctx, &nbSeq, ip, srcSize);
+        if (ZSTD_isError(seqHSize)) return seqHSize;
+        ip += seqHSize;
+        srcSize -= seqHSize;
+
+        RETURN_ERROR_IF((dst == NULL || dstCapacity == 0) && nbSeq > 0, dstSize_tooSmall, "NULL not handled");
+        RETURN_ERROR_IF(MEM_64bits() && sizeof(size_t) == sizeof(void*) && (size_t)(-1) - (size_t)dst < (size_t)(1 << 20), dstSize_tooSmall,
+                "invalid dst");
+
+        /* If we could potentially have long offsets, or we might want to use the prefetch decoder,
+         * compute information about the share of long offsets, and the maximum nbAdditionalBits.
+         * NOTE: could probably use a larger nbSeq limit
+         */
+        if (isLongOffset || (!usePrefetchDecoder && (totalHistorySize > (1u << 24)) && (nbSeq > 8))) {
+            ZSTD_OffsetInfo const info = ZSTD_getOffsetInfo(dctx->OFTptr, nbSeq);
+            if (isLongOffset && info.maxNbAdditionalBits <= STREAM_ACCUMULATOR_MIN) {
+                /* If isLongOffset, but the maximum number of additional bits that we see in our table is small
+                 * enough, then we know it is impossible to have too long an offset in this block, so we can
+                 * use the regular offset decoder.
+                 */
+                isLongOffset = ZSTD_lo_isRegularOffset;
+            }
+            if (!usePrefetchDecoder) {
+                U32 const minShare = MEM_64bits() ? 7 : 20; /* heuristic values, correspond to 2.73% and 7.81% */
+                usePrefetchDecoder = (info.longOffsetShare >= minShare);
+            }
+        }
+
+        dctx->ddictIsCold = 0;
+
+#if !defined(ZSTD_FORCE_DECOMPRESS_SEQUENCES_SHORT) && \
+    !defined(ZSTD_FORCE_DECOMPRESS_SEQUENCES_LONG)
+        if (usePrefetchDecoder) {
+#else
+        (void)usePrefetchDecoder;
+        {
+#endif
+#ifndef ZSTD_FORCE_DECOMPRESS_SEQUENCES_SHORT
+            return ZSTD_decompressSequencesLong(dctx, dst, dstCapacity, ip, srcSize, nbSeq, isLongOffset);
+#endif
+        }
+
+#ifndef ZSTD_FORCE_DECOMPRESS_SEQUENCES_LONG
+        /* else */
+        if (dctx->litBufferLocation == ZSTD_split)
+            return ZSTD_decompressSequencesSplitLitBuffer(dctx, dst, dstCapacity, ip, srcSize, nbSeq, isLongOffset);
+        else
+            return ZSTD_decompressSequences(dctx, dst, dstCapacity, ip, srcSize, nbSeq, isLongOffset);
+#endif
+    }
+}
+
+
+ZSTD_ALLOW_POINTER_OVERFLOW_ATTR
+void ZSTD_checkContinuity(ZSTD_DCtx* dctx, const void* dst, size_t dstSize)
+{
+    if (dst != dctx->previousDstEnd && dstSize > 0) {   /* not contiguous */
+        dctx->dictEnd = dctx->previousDstEnd;
+        dctx->virtualStart = (const char*)dst - ((const char*)(dctx->previousDstEnd) - (const char*)(dctx->prefixStart));
+        dctx->prefixStart = dst;
+        dctx->previousDstEnd = dst;
+    }
+}
diff --git a/src/commonlib/bsd/zstd/decompress/zstd_decompress_block.h b/src/commonlib/bsd/zstd/decompress/zstd_decompress_block.h
new file mode 100644
index 0000000000..d8ece22cfb
--- /dev/null
+++ b/src/commonlib/bsd/zstd/decompress/zstd_decompress_block.h
@@ -0,0 +1,69 @@
+/* SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0-only */
+
+/*
+ * Copyright (c) Meta Platforms, Inc. and affiliates.
+ * All rights reserved.
+ *
+ * This source code is licensed under both the BSD-style license (found in the
+ * LICENSE file in the root directory of this source tree) and the GPLv2 (found
+ * in the COPYING file in the root directory of this source tree).
+ * You may select, at your option, one of the above-listed licenses.
+ */
+
+
+#ifndef ZSTD_DEC_BLOCK_H
+#define ZSTD_DEC_BLOCK_H
+
+/*-*******************************************************
+ *  Dependencies
+ *********************************************************/
+#include "../common/zstd_deps.h"   /* size_t */
+#include "../zstd.h"    /* DCtx, and some public functions */
+#include "../common/zstd_internal.h"  /* blockProperties_t, and some public functions */
+#include "zstd_decompress_internal.h"  /* ZSTD_seqSymbol */
+
+
+/* ===   Prototypes   === */
+
+/* note: prototypes already published within `zstd.h` :
+ * ZSTD_decompressBlock()
+ */
+
+/* note: prototypes already published within `zstd_internal.h` :
+ * ZSTD_getcBlockSize()
+ * ZSTD_decodeSeqHeaders()
+ */
+
+
+ /* Streaming state is used to inform allocation of the literal buffer */
+typedef enum {
+    not_streaming = 0,
+    is_streaming = 1
+} streaming_operation;
+
+/* ZSTD_decompressBlock_internal() :
+ * decompress block, starting at `src`,
+ * into destination buffer `dst`.
+ * @return : decompressed block size,
+ *           or an error code (which can be tested using ZSTD_isError())
+ */
+size_t ZSTD_decompressBlock_internal(ZSTD_DCtx* dctx,
+                               void* dst, size_t dstCapacity,
+                         const void* src, size_t srcSize, const streaming_operation streaming);
+
+/* ZSTD_buildFSETable() :
+ * generate FSE decoding table for one symbol (ll, ml or off)
+ * this function must be called with valid parameters only
+ * (dt is large enough, normalizedCounter distribution total is a power of 2, max is within range, etc.)
+ * in which case it cannot fail.
+ * The workspace must be 4-byte aligned and at least ZSTD_BUILD_FSE_TABLE_WKSP_SIZE bytes, which is
+ * defined in zstd_decompress_internal.h.
+ * Internal use only.
+ */
+void ZSTD_buildFSETable(ZSTD_seqSymbol* dt,
+             const short* normalizedCounter, unsigned maxSymbolValue,
+             const U32* baseValue, const U8* nbAdditionalBits,
+                   unsigned tableLog, void* wksp, size_t wkspSize,
+                   int bmi2);
+
+#endif /* ZSTD_DEC_BLOCK_H */
diff --git a/src/commonlib/bsd/zstd/decompress/zstd_decompress_internal.h b/src/commonlib/bsd/zstd/decompress/zstd_decompress_internal.h
new file mode 100644
index 0000000000..ae1d750378
--- /dev/null
+++ b/src/commonlib/bsd/zstd/decompress/zstd_decompress_internal.h
@@ -0,0 +1,240 @@
+/* SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0-only */
+
+/*
+ * Copyright (c) Meta Platforms, Inc. and affiliates.
+ * All rights reserved.
+ *
+ * This source code is licensed under both the BSD-style license (found in the
+ * LICENSE file in the root directory of this source tree) and the GPLv2 (found
+ * in the COPYING file in the root directory of this source tree).
+ * You may select, at your option, one of the above-listed licenses.
+ */
+
+
+/* zstd_decompress_internal:
+ * objects and definitions shared within lib/decompress modules */
+
+ #ifndef ZSTD_DECOMPRESS_INTERNAL_H
+ #define ZSTD_DECOMPRESS_INTERNAL_H
+
+
+/*-*******************************************************
+ *  Dependencies
+ *********************************************************/
+#include "../common/mem.h"             /* BYTE, U16, U32 */
+#include "../common/zstd_internal.h"   /* constants : MaxLL, MaxML, MaxOff, LLFSELog, etc. */
+
+
+
+/*-*******************************************************
+ *  Constants
+ *********************************************************/
+static UNUSED_ATTR const U32 LL_base[MaxLL+1] = {
+                 0,    1,    2,     3,     4,     5,     6,      7,
+                 8,    9,   10,    11,    12,    13,    14,     15,
+                16,   18,   20,    22,    24,    28,    32,     40,
+                48,   64, 0x80, 0x100, 0x200, 0x400, 0x800, 0x1000,
+                0x2000, 0x4000, 0x8000, 0x10000 };
+
+static UNUSED_ATTR const U32 OF_base[MaxOff+1] = {
+                 0,        1,       1,       5,     0xD,     0x1D,     0x3D,     0x7D,
+                 0xFD,   0x1FD,   0x3FD,   0x7FD,   0xFFD,   0x1FFD,   0x3FFD,   0x7FFD,
+                 0xFFFD, 0x1FFFD, 0x3FFFD, 0x7FFFD, 0xFFFFD, 0x1FFFFD, 0x3FFFFD, 0x7FFFFD,
+                 0xFFFFFD, 0x1FFFFFD, 0x3FFFFFD, 0x7FFFFFD, 0xFFFFFFD, 0x1FFFFFFD, 0x3FFFFFFD, 0x7FFFFFFD };
+
+static UNUSED_ATTR const U8 OF_bits[MaxOff+1] = {
+                     0,  1,  2,  3,  4,  5,  6,  7,
+                     8,  9, 10, 11, 12, 13, 14, 15,
+                    16, 17, 18, 19, 20, 21, 22, 23,
+                    24, 25, 26, 27, 28, 29, 30, 31 };
+
+static UNUSED_ATTR const U32 ML_base[MaxML+1] = {
+                     3,  4,  5,    6,     7,     8,     9,    10,
+                    11, 12, 13,   14,    15,    16,    17,    18,
+                    19, 20, 21,   22,    23,    24,    25,    26,
+                    27, 28, 29,   30,    31,    32,    33,    34,
+                    35, 37, 39,   41,    43,    47,    51,    59,
+                    67, 83, 99, 0x83, 0x103, 0x203, 0x403, 0x803,
+                    0x1003, 0x2003, 0x4003, 0x8003, 0x10003 };
+
+
+/*-*******************************************************
+ *  Decompression types
+ *********************************************************/
+ typedef struct {
+     U32 fastMode;
+     U32 tableLog;
+ } ZSTD_seqSymbol_header;
+
+ typedef struct {
+     U16  nextState;
+     BYTE nbAdditionalBits;
+     BYTE nbBits;
+     U32  baseValue;
+ } ZSTD_seqSymbol;
+
+ #define SEQSYMBOL_TABLE_SIZE(log)   (1 + (1 << (log)))
+
+#define ZSTD_BUILD_FSE_TABLE_WKSP_SIZE (sizeof(S16) * (MaxSeq + 1) + (1u << MaxFSELog) + sizeof(U64))
+#define ZSTD_BUILD_FSE_TABLE_WKSP_SIZE_U32 ((ZSTD_BUILD_FSE_TABLE_WKSP_SIZE + sizeof(U32) - 1) / sizeof(U32))
+#define ZSTD_HUFFDTABLE_CAPACITY_LOG 12
+
+typedef struct {
+    ZSTD_seqSymbol LLTable[SEQSYMBOL_TABLE_SIZE(LLFSELog)];    /* Note : Space reserved for FSE Tables */
+    ZSTD_seqSymbol OFTable[SEQSYMBOL_TABLE_SIZE(OffFSELog)];   /* is also used as temporary workspace while building hufTable during DDict creation */
+    ZSTD_seqSymbol MLTable[SEQSYMBOL_TABLE_SIZE(MLFSELog)];    /* and therefore must be at least HUF_DECOMPRESS_WORKSPACE_SIZE large */
+    HUF_DTable hufTable[HUF_DTABLE_SIZE(ZSTD_HUFFDTABLE_CAPACITY_LOG)];  /* can accommodate HUF_decompress4X */
+    U32 rep[ZSTD_REP_NUM];
+    U32 workspace[ZSTD_BUILD_FSE_TABLE_WKSP_SIZE_U32];
+} ZSTD_entropyDTables_t;
+
+typedef enum { ZSTDds_getFrameHeaderSize, ZSTDds_decodeFrameHeader,
+               ZSTDds_decodeBlockHeader, ZSTDds_decompressBlock,
+               ZSTDds_decompressLastBlock, ZSTDds_checkChecksum,
+               ZSTDds_decodeSkippableHeader, ZSTDds_skipFrame } ZSTD_dStage;
+
+typedef enum { zdss_init=0, zdss_loadHeader,
+               zdss_read, zdss_load, zdss_flush } ZSTD_dStreamStage;
+
+typedef enum {
+    ZSTD_use_indefinitely = -1,  /* Use the dictionary indefinitely */
+    ZSTD_dont_use = 0,           /* Do not use the dictionary (if one exists free it) */
+    ZSTD_use_once = 1            /* Use the dictionary once and set to ZSTD_dont_use */
+} ZSTD_dictUses_e;
+
+/* Hashset for storing references to multiple ZSTD_DDict within ZSTD_DCtx */
+typedef struct {
+    const ZSTD_DDict** ddictPtrTable;
+    size_t ddictPtrTableSize;
+    size_t ddictPtrCount;
+} ZSTD_DDictHashSet;
+
+#ifndef ZSTD_DECODER_INTERNAL_BUFFER
+#  define ZSTD_DECODER_INTERNAL_BUFFER  (1 << 16)
+#endif
+
+#define ZSTD_LBMIN 64
+#define ZSTD_LBMAX (128 << 10)
+
+/* extra buffer, compensates when dst is not large enough to store litBuffer */
+#define ZSTD_LITBUFFEREXTRASIZE  BOUNDED(ZSTD_LBMIN, ZSTD_DECODER_INTERNAL_BUFFER, ZSTD_LBMAX)
+
+typedef enum {
+    ZSTD_not_in_dst = 0,  /* Stored entirely within litExtraBuffer */
+    ZSTD_in_dst = 1,           /* Stored entirely within dst (in memory after current output write) */
+    ZSTD_split = 2            /* Split between litExtraBuffer and dst */
+} ZSTD_litLocation_e;
+
+struct ZSTD_DCtx_s
+{
+    const ZSTD_seqSymbol* LLTptr;
+    const ZSTD_seqSymbol* MLTptr;
+    const ZSTD_seqSymbol* OFTptr;
+    const HUF_DTable* HUFptr;
+    ZSTD_entropyDTables_t entropy;
+    U32 workspace[HUF_DECOMPRESS_WORKSPACE_SIZE_U32];   /* space needed when building huffman tables */
+    const void* previousDstEnd;   /* detect continuity */
+    const void* prefixStart;      /* start of current segment */
+    const void* virtualStart;     /* virtual start of previous segment if it was just before current one */
+    const void* dictEnd;          /* end of previous segment */
+    size_t expected;
+    ZSTD_FrameHeader fParams;
+    U64 processedCSize;
+    U64 decodedSize;
+    blockType_e bType;            /* used in ZSTD_decompressContinue(), store blockType between block header decoding and block decompression stages */
+    ZSTD_dStage stage;
+    U32 litEntropy;
+    U32 fseEntropy;
+    XXH64_state_t xxhState;
+    size_t headerSize;
+    ZSTD_format_e format;
+    ZSTD_forceIgnoreChecksum_e forceIgnoreChecksum;   /* User specified: if == 1, will ignore checksums in compressed frame. Default == 0 */
+    U32 validateChecksum;         /* if == 1, will validate checksum. Is == 1 if (fParams.checksumFlag == 1) and (forceIgnoreChecksum == 0). */
+    const BYTE* litPtr;
+    ZSTD_customMem customMem;
+    size_t litSize;
+    size_t rleSize;
+    size_t staticSize;
+    int isFrameDecompression;
+#if DYNAMIC_BMI2
+    int bmi2;                     /* == 1 if the CPU supports BMI2 and 0 otherwise. CPU support is determined dynamically once per context lifetime. */
+#endif
+
+    /* dictionary */
+    const ZSTD_DDict* ddict;     /* set by ZSTD_initDStream_usingDDict(), or ZSTD_DCtx_refDDict() */
+    U32 dictID;
+    int ddictIsCold;             /* if == 1 : dictionary is "new" for working context, and presumed "cold" (not in cpu cache) */
+    ZSTD_dictUses_e dictUses;
+    ZSTD_refMultipleDDicts_e refMultipleDDicts;     /* User specified: if == 1, will allow references to multiple DDicts. Default == 0 (disabled) */
+    int disableHufAsm;
+    int maxBlockSizeParam;
+
+    /* streaming */
+    ZSTD_dStreamStage streamStage;
+    char*  inBuff;
+    size_t inBuffSize;
+    size_t inPos;
+    size_t maxWindowSize;
+    char*  outBuff;
+    size_t outBuffSize;
+    size_t outStart;
+    size_t outEnd;
+    size_t lhSize;
+#if defined(ZSTD_LEGACY_SUPPORT) && (ZSTD_LEGACY_SUPPORT>=1)
+    void* legacyContext;
+    U32 previousLegacyVersion;
+    U32 legacyVersion;
+#endif
+    U32 hostageByte;
+    int noForwardProgress;
+    ZSTD_bufferMode_e outBufferMode;
+    ZSTD_outBuffer expectedOutBuffer;
+
+    /* workspace */
+    BYTE* litBuffer;
+    const BYTE* litBufferEnd;
+    ZSTD_litLocation_e litBufferLocation;
+    BYTE litExtraBuffer[ZSTD_LITBUFFEREXTRASIZE + WILDCOPY_OVERLENGTH]; /* literal buffer can be split between storage within dst and within this scratch buffer */
+    BYTE headerBuffer[ZSTD_FRAMEHEADERSIZE_MAX];
+
+    size_t oversizedDuration;
+
+#ifdef FUZZING_BUILD_MODE_UNSAFE_FOR_PRODUCTION
+    void const* dictContentBeginForFuzzing;
+    void const* dictContentEndForFuzzing;
+#endif
+
+    /* Tracing */
+#if ZSTD_TRACE
+    ZSTD_TraceCtx traceCtx;
+#endif
+};  /* typedef'd to ZSTD_DCtx within "zstd.h" */
+
+MEM_STATIC int ZSTD_DCtx_get_bmi2(const struct ZSTD_DCtx_s *dctx) {
+#if DYNAMIC_BMI2
+    return dctx->bmi2;
+#else
+    (void)dctx;
+    return 0;
+#endif
+}
+
+/*-*******************************************************
+ *  Shared internal functions
+ *********************************************************/
+
+/*! ZSTD_loadDEntropy() :
+ *  dict : must point at beginning of a valid zstd dictionary.
+ * @return : size of dictionary header (size of magic number + dict ID + entropy tables) */
+size_t ZSTD_loadDEntropy(ZSTD_entropyDTables_t* entropy,
+                   const void* const dict, size_t const dictSize);
+
+/*! ZSTD_checkContinuity() :
+ *  check if next `dst` follows previous position, where decompression ended.
+ *  If yes, do nothing (continue on current segment).
+ *  If not, classify previous segment as "external dictionary", and start a new segment.
+ *  This function cannot fail. */
+void ZSTD_checkContinuity(ZSTD_DCtx* dctx, const void* dst, size_t dstSize);
+
+
+#endif /* ZSTD_DECOMPRESS_INTERNAL_H */
diff --git a/src/commonlib/bsd/zstd/zdict.h b/src/commonlib/bsd/zstd/zdict.h
new file mode 100644
index 0000000000..9befe96c1a
--- /dev/null
+++ b/src/commonlib/bsd/zstd/zdict.h
@@ -0,0 +1,483 @@
+/* SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0-only */
+
+/*
+ * Copyright (c) Meta Platforms, Inc. and affiliates.
+ * All rights reserved.
+ *
+ * This source code is licensed under both the BSD-style license (found in the
+ * LICENSE file in the root directory of this source tree) and the GPLv2 (found
+ * in the COPYING file in the root directory of this source tree).
+ * You may select, at your option, one of the above-listed licenses.
+ */
+
+#ifndef ZSTD_ZDICT_H
+#define ZSTD_ZDICT_H
+
+
+/*======  Dependencies  ======*/
+#include <stddef.h>  /* size_t */
+
+#if defined (__cplusplus)
+extern "C" {
+#endif
+
+/* =====   ZDICTLIB_API : control library symbols visibility   ===== */
+#ifndef ZDICTLIB_VISIBLE
+   /* Backwards compatibility with old macro name */
+#  ifdef ZDICTLIB_VISIBILITY
+#    define ZDICTLIB_VISIBLE ZDICTLIB_VISIBILITY
+#  elif defined(__GNUC__) && (__GNUC__ >= 4) && !defined(__MINGW32__)
+#    define ZDICTLIB_VISIBLE __attribute__ ((visibility ("default")))
+#  else
+#    define ZDICTLIB_VISIBLE
+#  endif
+#endif
+
+#ifndef ZDICTLIB_HIDDEN
+#  if defined(__GNUC__) && (__GNUC__ >= 4) && !defined(__MINGW32__)
+#    define ZDICTLIB_HIDDEN __attribute__ ((visibility ("hidden")))
+#  else
+#    define ZDICTLIB_HIDDEN
+#  endif
+#endif
+
+#if defined(ZSTD_DLL_EXPORT) && (ZSTD_DLL_EXPORT==1)
+#  define ZDICTLIB_API __declspec(dllexport) ZDICTLIB_VISIBLE
+#elif defined(ZSTD_DLL_IMPORT) && (ZSTD_DLL_IMPORT==1)
+#  define ZDICTLIB_API __declspec(dllimport) ZDICTLIB_VISIBLE /* It isn't required but allows to generate better code, saving a function pointer load from the IAT and an indirect jump.*/
+#else
+#  define ZDICTLIB_API ZDICTLIB_VISIBLE
+#endif
+
+/*******************************************************************************
+ * Zstd dictionary builder
+ *
+ * FAQ
+ * ===
+ * Why should I use a dictionary?
+ * ------------------------------
+ *
+ * Zstd can use dictionaries to improve compression ratio of small data.
+ * Traditionally small files don't compress well because there is very little
+ * repetition in a single sample, since it is small. But, if you are compressing
+ * many similar files, like a bunch of JSON records that share the same
+ * structure, you can train a dictionary on ahead of time on some samples of
+ * these files. Then, zstd can use the dictionary to find repetitions that are
+ * present across samples. This can vastly improve compression ratio.
+ *
+ * When is a dictionary useful?
+ * ----------------------------
+ *
+ * Dictionaries are useful when compressing many small files that are similar.
+ * The larger a file is, the less benefit a dictionary will have. Generally,
+ * we don't expect dictionary compression to be effective past 100KB. And the
+ * smaller a file is, the more we would expect the dictionary to help.
+ *
+ * How do I use a dictionary?
+ * --------------------------
+ *
+ * Simply pass the dictionary to the zstd compressor with
+ * `ZSTD_CCtx_loadDictionary()`. The same dictionary must then be passed to
+ * the decompressor, using `ZSTD_DCtx_loadDictionary()`. There are other
+ * more advanced functions that allow selecting some options, see zstd.h for
+ * complete documentation.
+ *
+ * What is a zstd dictionary?
+ * --------------------------
+ *
+ * A zstd dictionary has two pieces: Its header, and its content. The header
+ * contains a magic number, the dictionary ID, and entropy tables. These
+ * entropy tables allow zstd to save on header costs in the compressed file,
+ * which really matters for small data. The content is just bytes, which are
+ * repeated content that is common across many samples.
+ *
+ * What is a raw content dictionary?
+ * ---------------------------------
+ *
+ * A raw content dictionary is just bytes. It doesn't have a zstd dictionary
+ * header, a dictionary ID, or entropy tables. Any buffer is a valid raw
+ * content dictionary.
+ *
+ * How do I train a dictionary?
+ * ----------------------------
+ *
+ * Gather samples from your use case. These samples should be similar to each
+ * other. If you have several use cases, you could try to train one dictionary
+ * per use case.
+ *
+ * Pass those samples to `ZDICT_trainFromBuffer()` and that will train your
+ * dictionary. There are a few advanced versions of this function, but this
+ * is a great starting point. If you want to further tune your dictionary
+ * you could try `ZDICT_optimizeTrainFromBuffer_cover()`. If that is too slow
+ * you can try `ZDICT_optimizeTrainFromBuffer_fastCover()`.
+ *
+ * If the dictionary training function fails, that is likely because you
+ * either passed too few samples, or a dictionary would not be effective
+ * for your data. Look at the messages that the dictionary trainer printed,
+ * if it doesn't say too few samples, then a dictionary would not be effective.
+ *
+ * How large should my dictionary be?
+ * ----------------------------------
+ *
+ * A reasonable dictionary size, the `dictBufferCapacity`, is about 100KB.
+ * The zstd CLI defaults to a 110KB dictionary. You likely don't need a
+ * dictionary larger than that. But, most use cases can get away with a
+ * smaller dictionary. The advanced dictionary builders can automatically
+ * shrink the dictionary for you, and select the smallest size that doesn't
+ * hurt compression ratio too much. See the `shrinkDict` parameter.
+ * A smaller dictionary can save memory, and potentially speed up
+ * compression.
+ *
+ * How many samples should I provide to the dictionary builder?
+ * ------------------------------------------------------------
+ *
+ * We generally recommend passing ~100x the size of the dictionary
+ * in samples. A few thousand should suffice. Having too few samples
+ * can hurt the dictionaries effectiveness. Having more samples will
+ * only improve the dictionaries effectiveness. But having too many
+ * samples can slow down the dictionary builder.
+ *
+ * How do I determine if a dictionary will be effective?
+ * -----------------------------------------------------
+ *
+ * Simply train a dictionary and try it out. You can use zstd's built in
+ * benchmarking tool to test the dictionary effectiveness.
+ *
+ *   # Benchmark levels 1-3 without a dictionary
+ *   zstd -b1e3 -r /path/to/my/files
+ *   # Benchmark levels 1-3 with a dictionary
+ *   zstd -b1e3 -r /path/to/my/files -D /path/to/my/dictionary
+ *
+ * When should I retrain a dictionary?
+ * -----------------------------------
+ *
+ * You should retrain a dictionary when its effectiveness drops. Dictionary
+ * effectiveness drops as the data you are compressing changes. Generally, we do
+ * expect dictionaries to "decay" over time, as your data changes, but the rate
+ * at which they decay depends on your use case. Internally, we regularly
+ * retrain dictionaries, and if the new dictionary performs significantly
+ * better than the old dictionary, we will ship the new dictionary.
+ *
+ * I have a raw content dictionary, how do I turn it into a zstd dictionary?
+ * -------------------------------------------------------------------------
+ *
+ * If you have a raw content dictionary, e.g. by manually constructing it, or
+ * using a third-party dictionary builder, you can turn it into a zstd
+ * dictionary by using `ZDICT_finalizeDictionary()`. You'll also have to
+ * provide some samples of the data. It will add the zstd header to the
+ * raw content, which contains a dictionary ID and entropy tables, which
+ * will improve compression ratio, and allow zstd to write the dictionary ID
+ * into the frame, if you so choose.
+ *
+ * Do I have to use zstd's dictionary builder?
+ * -------------------------------------------
+ *
+ * No! You can construct dictionary content however you please, it is just
+ * bytes. It will always be valid as a raw content dictionary. If you want
+ * a zstd dictionary, which can improve compression ratio, use
+ * `ZDICT_finalizeDictionary()`.
+ *
+ * What is the attack surface of a zstd dictionary?
+ * ------------------------------------------------
+ *
+ * Zstd is heavily fuzz tested, including loading fuzzed dictionaries, so
+ * zstd should never crash, or access out-of-bounds memory no matter what
+ * the dictionary is. However, if an attacker can control the dictionary
+ * during decompression, they can cause zstd to generate arbitrary bytes,
+ * just like if they controlled the compressed data.
+ *
+ ******************************************************************************/
+
+
+/*! ZDICT_trainFromBuffer():
+ *  Train a dictionary from an array of samples.
+ *  Redirect towards ZDICT_optimizeTrainFromBuffer_fastCover() single-threaded, with d=8, steps=4,
+ *  f=20, and accel=1.
+ *  Samples must be stored concatenated in a single flat buffer `samplesBuffer`,
+ *  supplied with an array of sizes `samplesSizes`, providing the size of each sample, in order.
+ *  The resulting dictionary will be saved into `dictBuffer`.
+ * @return: size of dictionary stored into `dictBuffer` (<= `dictBufferCapacity`)
+ *          or an error code, which can be tested with ZDICT_isError().
+ *  Note:  Dictionary training will fail if there are not enough samples to construct a
+ *         dictionary, or if most of the samples are too small (< 8 bytes being the lower limit).
+ *         If dictionary training fails, you should use zstd without a dictionary, as the dictionary
+ *         would've been ineffective anyways. If you believe your samples would benefit from a dictionary
+ *         please open an issue with details, and we can look into it.
+ *  Note: ZDICT_trainFromBuffer()'s memory usage is about 6 MB.
+ *  Tips: In general, a reasonable dictionary has a size of ~ 100 KB.
+ *        It's possible to select smaller or larger size, just by specifying `dictBufferCapacity`.
+ *        In general, it's recommended to provide a few thousands samples, though this can vary a lot.
+ *        It's recommended that total size of all samples be about ~x100 times the target size of dictionary.
+ */
+ZDICTLIB_API size_t ZDICT_trainFromBuffer(void* dictBuffer, size_t dictBufferCapacity,
+                                    const void* samplesBuffer,
+                                    const size_t* samplesSizes, unsigned nbSamples);
+
+typedef struct {
+    int      compressionLevel;   /**< optimize for a specific zstd compression level; 0 means default */
+    unsigned notificationLevel;  /**< Write log to stderr; 0 = none (default); 1 = errors; 2 = progression; 3 = details; 4 = debug; */
+    unsigned dictID;             /**< force dictID value; 0 means auto mode (32-bits random value)
+                                  *   NOTE: The zstd format reserves some dictionary IDs for future use.
+                                  *         You may use them in private settings, but be warned that they
+                                  *         may be used by zstd in a public dictionary registry in the future.
+                                  *         These dictionary IDs are:
+                                  *           - low range  : <= 32767
+                                  *           - high range : >= (2^31)
+                                  */
+} ZDICT_params_t;
+
+/*! ZDICT_finalizeDictionary():
+ * Given a custom content as a basis for dictionary, and a set of samples,
+ * finalize dictionary by adding headers and statistics according to the zstd
+ * dictionary format.
+ *
+ * Samples must be stored concatenated in a flat buffer `samplesBuffer`,
+ * supplied with an array of sizes `samplesSizes`, providing the size of each
+ * sample in order. The samples are used to construct the statistics, so they
+ * should be representative of what you will compress with this dictionary.
+ *
+ * The compression level can be set in `parameters`. You should pass the
+ * compression level you expect to use in production. The statistics for each
+ * compression level differ, so tuning the dictionary for the compression level
+ * can help quite a bit.
+ *
+ * You can set an explicit dictionary ID in `parameters`, or allow us to pick
+ * a random dictionary ID for you, but we can't guarantee no collisions.
+ *
+ * The dstDictBuffer and the dictContent may overlap, and the content will be
+ * appended to the end of the header. If the header + the content doesn't fit in
+ * maxDictSize the beginning of the content is truncated to make room, since it
+ * is presumed that the most profitable content is at the end of the dictionary,
+ * since that is the cheapest to reference.
+ *
+ * `maxDictSize` must be >= max(dictContentSize, ZDICT_DICTSIZE_MIN).
+ *
+ * @return: size of dictionary stored into `dstDictBuffer` (<= `maxDictSize`),
+ *          or an error code, which can be tested by ZDICT_isError().
+ * Note: ZDICT_finalizeDictionary() will push notifications into stderr if
+ *       instructed to, using notificationLevel>0.
+ * NOTE: This function currently may fail in several edge cases including:
+ *         * Not enough samples
+ *         * Samples are uncompressible
+ *         * Samples are all exactly the same
+ */
+ZDICTLIB_API size_t ZDICT_finalizeDictionary(void* dstDictBuffer, size_t maxDictSize,
+                                const void* dictContent, size_t dictContentSize,
+                                const void* samplesBuffer, const size_t* samplesSizes, unsigned nbSamples,
+                                ZDICT_params_t parameters);
+
+
+/*======   Helper functions   ======*/
+ZDICTLIB_API unsigned ZDICT_getDictID(const void* dictBuffer, size_t dictSize);  /**< extracts dictID; @return zero if error (not a valid dictionary) */
+ZDICTLIB_API size_t ZDICT_getDictHeaderSize(const void* dictBuffer, size_t dictSize);  /* returns dict header size; returns a ZSTD error code on failure */
+ZDICTLIB_API unsigned ZDICT_isError(size_t errorCode);
+ZDICTLIB_API const char* ZDICT_getErrorName(size_t errorCode);
+
+#if defined (__cplusplus)
+}
+#endif
+
+#endif   /* ZSTD_ZDICT_H */
+
+#if defined(ZDICT_STATIC_LINKING_ONLY) && !defined(ZSTD_ZDICT_H_STATIC)
+#define ZSTD_ZDICT_H_STATIC
+
+#if defined (__cplusplus)
+extern "C" {
+#endif
+
+/* This can be overridden externally to hide static symbols. */
+#ifndef ZDICTLIB_STATIC_API
+#  if defined(ZSTD_DLL_EXPORT) && (ZSTD_DLL_EXPORT==1)
+#    define ZDICTLIB_STATIC_API __declspec(dllexport) ZDICTLIB_VISIBLE
+#  elif defined(ZSTD_DLL_IMPORT) && (ZSTD_DLL_IMPORT==1)
+#    define ZDICTLIB_STATIC_API __declspec(dllimport) ZDICTLIB_VISIBLE
+#  else
+#    define ZDICTLIB_STATIC_API ZDICTLIB_VISIBLE
+#  endif
+#endif
+
+/* ====================================================================================
+ * The definitions in this section are considered experimental.
+ * They should never be used with a dynamic library, as they may change in the future.
+ * They are provided for advanced usages.
+ * Use them only in association with static linking.
+ * ==================================================================================== */
+
+#define ZDICT_DICTSIZE_MIN    256
+/* Deprecated: Remove in v1.6.0 */
+#define ZDICT_CONTENTSIZE_MIN 128
+
+/*! ZDICT_cover_params_t:
+ *  k and d are the only required parameters.
+ *  For others, value 0 means default.
+ */
+typedef struct {
+    unsigned k;                  /* Segment size : constraint: 0 < k : Reasonable range [16, 2048+] */
+    unsigned d;                  /* dmer size : constraint: 0 < d <= k : Reasonable range [6, 16] */
+    unsigned steps;              /* Number of steps : Only used for optimization : 0 means default (40) : Higher means more parameters checked */
+    unsigned nbThreads;          /* Number of threads : constraint: 0 < nbThreads : 1 means single-threaded : Only used for optimization : Ignored if ZSTD_MULTITHREAD is not defined */
+    double splitPoint;           /* Percentage of samples used for training: Only used for optimization : the first nbSamples * splitPoint samples will be used to training, the last nbSamples * (1 - splitPoint) samples will be used for testing, 0 means default (1.0), 1.0 when all samples are used for both training and testing */
+    unsigned shrinkDict;         /* Train dictionaries to shrink in size starting from the minimum size and selects the smallest dictionary that is shrinkDictMaxRegression% worse than the largest dictionary. 0 means no shrinking and 1 means shrinking  */
+    unsigned shrinkDictMaxRegression; /* Sets shrinkDictMaxRegression so that a smaller dictionary can be at worse shrinkDictMaxRegression% worse than the max dict size dictionary. */
+    ZDICT_params_t zParams;
+} ZDICT_cover_params_t;
+
+typedef struct {
+    unsigned k;                  /* Segment size : constraint: 0 < k : Reasonable range [16, 2048+] */
+    unsigned d;                  /* dmer size : constraint: 0 < d <= k : Reasonable range [6, 16] */
+    unsigned f;                  /* log of size of frequency array : constraint: 0 < f <= 31 : 1 means default(20)*/
+    unsigned steps;              /* Number of steps : Only used for optimization : 0 means default (40) : Higher means more parameters checked */
+    unsigned nbThreads;          /* Number of threads : constraint: 0 < nbThreads : 1 means single-threaded : Only used for optimization : Ignored if ZSTD_MULTITHREAD is not defined */
+    double splitPoint;           /* Percentage of samples used for training: Only used for optimization : the first nbSamples * splitPoint samples will be used to training, the last nbSamples * (1 - splitPoint) samples will be used for testing, 0 means default (0.75), 1.0 when all samples are used for both training and testing */
+    unsigned accel;              /* Acceleration level: constraint: 0 < accel <= 10, higher means faster and less accurate, 0 means default(1) */
+    unsigned shrinkDict;         /* Train dictionaries to shrink in size starting from the minimum size and selects the smallest dictionary that is shrinkDictMaxRegression% worse than the largest dictionary. 0 means no shrinking and 1 means shrinking  */
+    unsigned shrinkDictMaxRegression; /* Sets shrinkDictMaxRegression so that a smaller dictionary can be at worse shrinkDictMaxRegression% worse than the max dict size dictionary. */
+
+    ZDICT_params_t zParams;
+} ZDICT_fastCover_params_t;
+
+/*! ZDICT_trainFromBuffer_cover():
+ *  Train a dictionary from an array of samples using the COVER algorithm.
+ *  Samples must be stored concatenated in a single flat buffer `samplesBuffer`,
+ *  supplied with an array of sizes `samplesSizes`, providing the size of each sample, in order.
+ *  The resulting dictionary will be saved into `dictBuffer`.
+ * @return: size of dictionary stored into `dictBuffer` (<= `dictBufferCapacity`)
+ *          or an error code, which can be tested with ZDICT_isError().
+ *          See ZDICT_trainFromBuffer() for details on failure modes.
+ *  Note: ZDICT_trainFromBuffer_cover() requires about 9 bytes of memory for each input byte.
+ *  Tips: In general, a reasonable dictionary has a size of ~ 100 KB.
+ *        It's possible to select smaller or larger size, just by specifying `dictBufferCapacity`.
+ *        In general, it's recommended to provide a few thousands samples, though this can vary a lot.
+ *        It's recommended that total size of all samples be about ~x100 times the target size of dictionary.
+ */
+ZDICTLIB_STATIC_API size_t ZDICT_trainFromBuffer_cover(
+          void *dictBuffer, size_t dictBufferCapacity,
+    const void *samplesBuffer, const size_t *samplesSizes, unsigned nbSamples,
+          ZDICT_cover_params_t parameters);
+
+/*! ZDICT_optimizeTrainFromBuffer_cover():
+ * The same requirements as above hold for all the parameters except `parameters`.
+ * This function tries many parameter combinations and picks the best parameters.
+ * `*parameters` is filled with the best parameters found,
+ * dictionary constructed with those parameters is stored in `dictBuffer`.
+ *
+ * All of the parameters d, k, steps are optional.
+ * If d is non-zero then we don't check multiple values of d, otherwise we check d = {6, 8}.
+ * if steps is zero it defaults to its default value.
+ * If k is non-zero then we don't check multiple values of k, otherwise we check steps values in [50, 2000].
+ *
+ * @return: size of dictionary stored into `dictBuffer` (<= `dictBufferCapacity`)
+ *          or an error code, which can be tested with ZDICT_isError().
+ *          On success `*parameters` contains the parameters selected.
+ *          See ZDICT_trainFromBuffer() for details on failure modes.
+ * Note: ZDICT_optimizeTrainFromBuffer_cover() requires about 8 bytes of memory for each input byte and additionally another 5 bytes of memory for each byte of memory for each thread.
+ */
+ZDICTLIB_STATIC_API size_t ZDICT_optimizeTrainFromBuffer_cover(
+          void* dictBuffer, size_t dictBufferCapacity,
+    const void* samplesBuffer, const size_t* samplesSizes, unsigned nbSamples,
+          ZDICT_cover_params_t* parameters);
+
+/*! ZDICT_trainFromBuffer_fastCover():
+ *  Train a dictionary from an array of samples using a modified version of COVER algorithm.
+ *  Samples must be stored concatenated in a single flat buffer `samplesBuffer`,
+ *  supplied with an array of sizes `samplesSizes`, providing the size of each sample, in order.
+ *  d and k are required.
+ *  All other parameters are optional, will use default values if not provided
+ *  The resulting dictionary will be saved into `dictBuffer`.
+ * @return: size of dictionary stored into `dictBuffer` (<= `dictBufferCapacity`)
+ *          or an error code, which can be tested with ZDICT_isError().
+ *          See ZDICT_trainFromBuffer() for details on failure modes.
+ *  Note: ZDICT_trainFromBuffer_fastCover() requires 6 * 2^f bytes of memory.
+ *  Tips: In general, a reasonable dictionary has a size of ~ 100 KB.
+ *        It's possible to select smaller or larger size, just by specifying `dictBufferCapacity`.
+ *        In general, it's recommended to provide a few thousands samples, though this can vary a lot.
+ *        It's recommended that total size of all samples be about ~x100 times the target size of dictionary.
+ */
+ZDICTLIB_STATIC_API size_t ZDICT_trainFromBuffer_fastCover(void *dictBuffer,
+                    size_t dictBufferCapacity, const void *samplesBuffer,
+                    const size_t *samplesSizes, unsigned nbSamples,
+                    ZDICT_fastCover_params_t parameters);
+
+/*! ZDICT_optimizeTrainFromBuffer_fastCover():
+ * The same requirements as above hold for all the parameters except `parameters`.
+ * This function tries many parameter combinations (specifically, k and d combinations)
+ * and picks the best parameters. `*parameters` is filled with the best parameters found,
+ * dictionary constructed with those parameters is stored in `dictBuffer`.
+ * All of the parameters d, k, steps, f, and accel are optional.
+ * If d is non-zero then we don't check multiple values of d, otherwise we check d = {6, 8}.
+ * if steps is zero it defaults to its default value.
+ * If k is non-zero then we don't check multiple values of k, otherwise we check steps values in [50, 2000].
+ * If f is zero, default value of 20 is used.
+ * If accel is zero, default value of 1 is used.
+ *
+ * @return: size of dictionary stored into `dictBuffer` (<= `dictBufferCapacity`)
+ *          or an error code, which can be tested with ZDICT_isError().
+ *          On success `*parameters` contains the parameters selected.
+ *          See ZDICT_trainFromBuffer() for details on failure modes.
+ * Note: ZDICT_optimizeTrainFromBuffer_fastCover() requires about 6 * 2^f bytes of memory for each thread.
+ */
+ZDICTLIB_STATIC_API size_t ZDICT_optimizeTrainFromBuffer_fastCover(void* dictBuffer,
+                    size_t dictBufferCapacity, const void* samplesBuffer,
+                    const size_t* samplesSizes, unsigned nbSamples,
+                    ZDICT_fastCover_params_t* parameters);
+
+typedef struct {
+    unsigned selectivityLevel;   /* 0 means default; larger => select more => larger dictionary */
+    ZDICT_params_t zParams;
+} ZDICT_legacy_params_t;
+
+/*! ZDICT_trainFromBuffer_legacy():
+ *  Train a dictionary from an array of samples.
+ *  Samples must be stored concatenated in a single flat buffer `samplesBuffer`,
+ *  supplied with an array of sizes `samplesSizes`, providing the size of each sample, in order.
+ *  The resulting dictionary will be saved into `dictBuffer`.
+ * `parameters` is optional and can be provided with values set to 0 to mean "default".
+ * @return: size of dictionary stored into `dictBuffer` (<= `dictBufferCapacity`)
+ *          or an error code, which can be tested with ZDICT_isError().
+ *          See ZDICT_trainFromBuffer() for details on failure modes.
+ *  Tips: In general, a reasonable dictionary has a size of ~ 100 KB.
+ *        It's possible to select smaller or larger size, just by specifying `dictBufferCapacity`.
+ *        In general, it's recommended to provide a few thousands samples, though this can vary a lot.
+ *        It's recommended that total size of all samples be about ~x100 times the target size of dictionary.
+ *  Note: ZDICT_trainFromBuffer_legacy() will send notifications into stderr if instructed to, using notificationLevel>0.
+ */
+ZDICTLIB_STATIC_API size_t ZDICT_trainFromBuffer_legacy(
+    void* dictBuffer, size_t dictBufferCapacity,
+    const void* samplesBuffer, const size_t* samplesSizes, unsigned nbSamples,
+    ZDICT_legacy_params_t parameters);
+
+
+/* Deprecation warnings */
+/* It is generally possible to disable deprecation warnings from compiler,
+   for example with -Wno-deprecated-declarations for gcc
+   or _CRT_SECURE_NO_WARNINGS in Visual.
+   Otherwise, it's also possible to manually define ZDICT_DISABLE_DEPRECATE_WARNINGS */
+#ifdef ZDICT_DISABLE_DEPRECATE_WARNINGS
+#  define ZDICT_DEPRECATED(message) /* disable deprecation warnings */
+#else
+#  define ZDICT_GCC_VERSION (__GNUC__ * 100 + __GNUC_MINOR__)
+#  if defined (__cplusplus) && (__cplusplus >= 201402) /* C++14 or greater */
+#    define ZDICT_DEPRECATED(message) [[deprecated(message)]]
+#  elif defined(__clang__) || (ZDICT_GCC_VERSION >= 405)
+#    define ZDICT_DEPRECATED(message) __attribute__((deprecated(message)))
+#  elif (ZDICT_GCC_VERSION >= 301)
+#    define ZDICT_DEPRECATED(message) __attribute__((deprecated))
+#  elif defined(_MSC_VER)
+#    define ZDICT_DEPRECATED(message) __declspec(deprecated(message))
+#  else
+#    pragma message("WARNING: You need to implement ZDICT_DEPRECATED for this compiler")
+#    define ZDICT_DEPRECATED(message)
+#  endif
+#endif /* ZDICT_DISABLE_DEPRECATE_WARNINGS */
+
+ZDICT_DEPRECATED("use ZDICT_finalizeDictionary() instead")
+ZDICTLIB_STATIC_API
+size_t ZDICT_addEntropyTablesFromBuffer(void* dictBuffer, size_t dictContentSize, size_t dictBufferCapacity,
+                                  const void* samplesBuffer, const size_t* samplesSizes, unsigned nbSamples);
+
+#if defined (__cplusplus)
+}
+#endif
+
+#endif   /* ZSTD_ZDICT_H_STATIC */
diff --git a/src/commonlib/bsd/zstd/zstd.h b/src/commonlib/bsd/zstd/zstd.h
new file mode 100644
index 0000000000..d88412c8dc
--- /dev/null
+++ b/src/commonlib/bsd/zstd/zstd.h
@@ -0,0 +1,2646 @@
+/* SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0-only */
+
+/*
+ * Copyright (c) Meta Platforms, Inc. and affiliates.
+ * All rights reserved.
+ *
+ * This source code is licensed under both the BSD-style license (found in the
+ * LICENSE file in the root directory of this source tree) and the GPLv2 (found
+ * in the COPYING file in the root directory of this source tree).
+ * You may select, at your option, one of the above-listed licenses.
+ */
+
+#ifndef ZSTD_H_235446
+#define ZSTD_H_235446
+
+
+/* ======   Dependencies   ======*/
+#include <stddef.h>   /* size_t */
+
+#include "zstd_errors.h" /* list of errors */
+#if defined(ZSTD_STATIC_LINKING_ONLY) && !defined(ZSTD_H_ZSTD_STATIC_LINKING_ONLY)
+#include <limits.h>   /* INT_MAX */
+#endif /* ZSTD_STATIC_LINKING_ONLY */
+
+#if defined (__cplusplus)
+extern "C" {
+#endif
+
+/* =====   ZSTDLIB_API : control library symbols visibility   ===== */
+#ifndef ZSTDLIB_VISIBLE
+   /* Backwards compatibility with old macro name */
+#  ifdef ZSTDLIB_VISIBILITY
+#    define ZSTDLIB_VISIBLE ZSTDLIB_VISIBILITY
+#  elif defined(__GNUC__) && (__GNUC__ >= 4) && !defined(__MINGW32__)
+#    define ZSTDLIB_VISIBLE __attribute__ ((visibility ("default")))
+#  else
+#    define ZSTDLIB_VISIBLE
+#  endif
+#endif
+
+#ifndef ZSTDLIB_HIDDEN
+#  if defined(__GNUC__) && (__GNUC__ >= 4) && !defined(__MINGW32__)
+#    define ZSTDLIB_HIDDEN __attribute__ ((visibility ("hidden")))
+#  else
+#    define ZSTDLIB_HIDDEN
+#  endif
+#endif
+
+#if defined(ZSTD_DLL_EXPORT) && (ZSTD_DLL_EXPORT==1)
+#  define ZSTDLIB_API __declspec(dllexport) ZSTDLIB_VISIBLE
+#elif defined(ZSTD_DLL_IMPORT) && (ZSTD_DLL_IMPORT==1)
+#  define ZSTDLIB_API __declspec(dllimport) ZSTDLIB_VISIBLE /* It isn't required but allows to generate better code, saving a function pointer load from the IAT and an indirect jump.*/
+#else
+#  define ZSTDLIB_API ZSTDLIB_VISIBLE
+#endif
+
+/* Deprecation warnings :
+ * Should these warnings be a problem, it is generally possible to disable them,
+ * typically with -Wno-deprecated-declarations for gcc or _CRT_SECURE_NO_WARNINGS in Visual.
+ * Otherwise, it's also possible to define ZSTD_DISABLE_DEPRECATE_WARNINGS.
+ */
+#ifdef ZSTD_DISABLE_DEPRECATE_WARNINGS
+#  define ZSTD_DEPRECATED(message) /* disable deprecation warnings */
+#else
+#  if defined (__cplusplus) && (__cplusplus >= 201402) /* C++14 or greater */
+#    define ZSTD_DEPRECATED(message) [[deprecated(message)]]
+#  elif (defined(GNUC) && (GNUC > 4 || (GNUC == 4 && GNUC_MINOR >= 5))) || defined(__clang__) || defined(__IAR_SYSTEMS_ICC__)
+#    define ZSTD_DEPRECATED(message) __attribute__((deprecated(message)))
+#  elif defined(__GNUC__) && (__GNUC__ >= 3)
+#    define ZSTD_DEPRECATED(message) __attribute__((deprecated))
+#  elif defined(_MSC_VER)
+#    define ZSTD_DEPRECATED(message) __declspec(deprecated(message))
+#  else
+#    pragma message("WARNING: You need to implement ZSTD_DEPRECATED for this compiler")
+#    define ZSTD_DEPRECATED(message)
+#  endif
+#endif /* ZSTD_DISABLE_DEPRECATE_WARNINGS */
+
+
+/*******************************************************************************
+  Introduction
+
+  zstd, short for Zstandard, is a fast lossless compression algorithm, targeting
+  real-time compression scenarios at zlib-level and better compression ratios.
+  The zstd compression library provides in-memory compression and decompression
+  functions.
+
+  The library supports regular compression levels from 1 up to ZSTD_maxCLevel(),
+  which is currently 22. Levels >= 20, labeled `--ultra`, should be used with
+  caution, as they require more memory. The library also offers negative
+  compression levels, which extend the range of speed vs. ratio preferences.
+  The lower the level, the faster the speed (at the cost of compression).
+
+  Compression can be done in:
+    - a single step (described as Simple API)
+    - a single step, reusing a context (described as Explicit context)
+    - unbounded multiple steps (described as Streaming compression)
+
+  The compression ratio achievable on small data can be highly improved using
+  a dictionary. Dictionary compression can be performed in:
+    - a single step (described as Simple dictionary API)
+    - a single step, reusing a dictionary (described as Bulk-processing
+      dictionary API)
+
+  Advanced experimental functions can be accessed using
+  `#define ZSTD_STATIC_LINKING_ONLY` before including zstd.h.
+
+  Advanced experimental APIs should never be used with a dynamically-linked
+  library. They are not "stable"; their definitions or signatures may change in
+  the future. Only static linking is allowed.
+*******************************************************************************/
+
+/*------   Version   ------*/
+#define ZSTD_VERSION_MAJOR    1
+#define ZSTD_VERSION_MINOR    5
+#define ZSTD_VERSION_RELEASE  7
+#define ZSTD_VERSION_NUMBER  (ZSTD_VERSION_MAJOR *100*100 + ZSTD_VERSION_MINOR *100 + ZSTD_VERSION_RELEASE)
+
+/*! ZSTD_versionNumber() :
+ *  Return runtime library version, the value is (MAJOR*100*100 + MINOR*100 + RELEASE). */
+ZSTDLIB_API unsigned ZSTD_versionNumber(void);
+
+#define ZSTD_LIB_VERSION ZSTD_VERSION_MAJOR.ZSTD_VERSION_MINOR.ZSTD_VERSION_RELEASE
+#define ZSTD_QUOTE(str) #str
+#define ZSTD_EXPAND_AND_QUOTE(str) ZSTD_QUOTE(str)
+#define ZSTD_VERSION_STRING ZSTD_EXPAND_AND_QUOTE(ZSTD_LIB_VERSION)
+
+/*! ZSTD_versionString() :
+ *  Return runtime library version, like "1.4.5". Requires v1.3.0+. */
+ZSTDLIB_API const char* ZSTD_versionString(void);
+
+/* *************************************
+ *  Default constant
+ ***************************************/
+#ifndef ZSTD_CLEVEL_DEFAULT
+#  define ZSTD_CLEVEL_DEFAULT 3
+#endif
+
+/* *************************************
+ *  Constants
+ ***************************************/
+
+/* All magic numbers are supposed read/written to/from files/memory using little-endian convention */
+#define ZSTD_MAGICNUMBER            0xFD2FB528    /* valid since v0.8.0 */
+#define ZSTD_MAGIC_DICTIONARY       0xEC30A437    /* valid since v0.7.0 */
+#define ZSTD_MAGIC_SKIPPABLE_START  0x184D2A50    /* all 16 values, from 0x184D2A50 to 0x184D2A5F, signal the beginning of a skippable frame */
+#define ZSTD_MAGIC_SKIPPABLE_MASK   0xFFFFFFF0
+
+#define ZSTD_BLOCKSIZELOG_MAX  17
+#define ZSTD_BLOCKSIZE_MAX     (1<<ZSTD_BLOCKSIZELOG_MAX)
+
+
+/***************************************
+*  Simple Core API
+***************************************/
+/*! ZSTD_compress() :
+ *  Compresses `src` content as a single zstd compressed frame into already allocated `dst`.
+ *  NOTE: Providing `dstCapacity >= ZSTD_compressBound(srcSize)` guarantees that zstd will have
+ *        enough space to successfully compress the data.
+ *  @return : compressed size written into `dst` (<= `dstCapacity),
+ *            or an error code if it fails (which can be tested using ZSTD_isError()). */
+ZSTDLIB_API size_t ZSTD_compress( void* dst, size_t dstCapacity,
+                            const void* src, size_t srcSize,
+                                  int compressionLevel);
+
+/*======  Decompression helper functions  ======*/
+
+/*! ZSTD_getFrameContentSize() : requires v1.3.0+
+ * `src` should point to the start of a ZSTD encoded frame.
+ * `srcSize` must be at least as large as the frame header.
+ *           hint : any size >= `ZSTD_frameHeaderSize_max` is large enough.
+ * @return : - decompressed size of `src` frame content, if known
+ *           - ZSTD_CONTENTSIZE_UNKNOWN if the size cannot be determined
+ *           - ZSTD_CONTENTSIZE_ERROR if an error occurred (e.g. invalid magic number, srcSize too small)
+ *  note 1 : a 0 return value means the frame is valid but "empty".
+ *           When invoking this method on a skippable frame, it will return 0.
+ *  note 2 : decompressed size is an optional field, it may not be present (typically in streaming mode).
+ *           When `return==ZSTD_CONTENTSIZE_UNKNOWN`, data to decompress could be any size.
+ *           In which case, it's necessary to use streaming mode to decompress data.
+ *           Optionally, application can rely on some implicit limit,
+ *           as ZSTD_decompress() only needs an upper bound of decompressed size.
+ *           (For example, data could be necessarily cut into blocks <= 16 KB).
+ *  note 3 : decompressed size is always present when compression is completed using single-pass functions,
+ *           such as ZSTD_compress(), ZSTD_compressCCtx() ZSTD_compress_usingDict() or ZSTD_compress_usingCDict().
+ *  note 4 : decompressed size can be very large (64-bits value),
+ *           potentially larger than what local system can handle as a single memory segment.
+ *           In which case, it's necessary to use streaming mode to decompress data.
+ *  note 5 : If source is untrusted, decompressed size could be wrong or intentionally modified.
+ *           Always ensure return value fits within application's authorized limits.
+ *           Each application can set its own limits.
+ *  note 6 : This function replaces ZSTD_getDecompressedSize() */
+#define ZSTD_CONTENTSIZE_UNKNOWN (0ULL - 1)
+#define ZSTD_CONTENTSIZE_ERROR   (0ULL - 2)
+ZSTDLIB_API unsigned long long ZSTD_getFrameContentSize(const void *src, size_t srcSize);
+
+/*! ZSTD_getDecompressedSize() (obsolete):
+ *  This function is now obsolete, in favor of ZSTD_getFrameContentSize().
+ *  Both functions work the same way, but ZSTD_getDecompressedSize() blends
+ *  "empty", "unknown" and "error" results to the same return value (0),
+ *  while ZSTD_getFrameContentSize() gives them separate return values.
+ * @return : decompressed size of `src` frame content _if known and not empty_, 0 otherwise. */
+ZSTD_DEPRECATED("Replaced by ZSTD_getFrameContentSize")
+ZSTDLIB_API unsigned long long ZSTD_getDecompressedSize(const void* src, size_t srcSize);
+
+/*! ZSTD_findFrameCompressedSize() : Requires v1.4.0+
+ * `src` should point to the start of a ZSTD frame or skippable frame.
+ * `srcSize` must be >= first frame size
+ * @return : the compressed size of the first frame starting at `src`,
+ *           suitable to pass as `srcSize` to `ZSTD_decompress` or similar,
+ *           or an error code if input is invalid
+ *  Note 1: this method is called _find*() because it's not enough to read the header,
+ *          it may have to scan through the frame's content, to reach its end.
+ *  Note 2: this method also works with Skippable Frames. In which case,
+ *          it returns the size of the complete skippable frame,
+ *          which is always equal to its content size + 8 bytes for headers. */
+ZSTDLIB_API size_t ZSTD_findFrameCompressedSize(const void* src, size_t srcSize);
+
+
+/*======  Compression helper functions  ======*/
+
+/*! ZSTD_compressBound() :
+ * maximum compressed size in worst case single-pass scenario.
+ * When invoking `ZSTD_compress()`, or any other one-pass compression function,
+ * it's recommended to provide @dstCapacity >= ZSTD_compressBound(srcSize)
+ * as it eliminates one potential failure scenario,
+ * aka not enough room in dst buffer to write the compressed frame.
+ * Note : ZSTD_compressBound() itself can fail, if @srcSize >= ZSTD_MAX_INPUT_SIZE .
+ *        In which case, ZSTD_compressBound() will return an error code
+ *        which can be tested using ZSTD_isError().
+ *
+ * ZSTD_COMPRESSBOUND() :
+ * same as ZSTD_compressBound(), but as a macro.
+ * It can be used to produce constants, which can be useful for static allocation,
+ * for example to size a static array on stack.
+ * Will produce constant value 0 if srcSize is too large.
+ */
+#define ZSTD_MAX_INPUT_SIZE ((sizeof(size_t)==8) ? 0xFF00FF00FF00FF00ULL : 0xFF00FF00U)
+#define ZSTD_COMPRESSBOUND(srcSize)   (((size_t)(srcSize) >= ZSTD_MAX_INPUT_SIZE) ? 0 : (srcSize) + ((srcSize)>>8) + (((srcSize) < (128<<10)) ? (((128<<10) - (srcSize)) >> 11) /* margin, from 64 to 0 */ : 0))  /* this formula ensures that bound(A) + bound(B) <= bound(A+B) as long as A and B >= 128 KB */
+ZSTDLIB_API size_t ZSTD_compressBound(size_t srcSize); /*!< maximum compressed size in worst case single-pass scenario */
+
+
+/*======  Error helper functions  ======*/
+/* ZSTD_isError() :
+ * Most ZSTD_* functions returning a size_t value can be tested for error,
+ * using ZSTD_isError().
+ * @return 1 if error, 0 otherwise
+ */
+ZSTDLIB_API unsigned     ZSTD_isError(size_t result);      /*!< tells if a `size_t` function result is an error code */
+ZSTDLIB_API ZSTD_ErrorCode ZSTD_getErrorCode(size_t functionResult); /* convert a result into an error code, which can be compared to error enum list */
+ZSTDLIB_API const char*  ZSTD_getErrorName(size_t result); /*!< provides readable string from a function result */
+ZSTDLIB_API int          ZSTD_minCLevel(void);             /*!< minimum negative compression level allowed, requires v1.4.0+ */
+ZSTDLIB_API int          ZSTD_maxCLevel(void);             /*!< maximum compression level available */
+ZSTDLIB_API int          ZSTD_defaultCLevel(void);         /*!< default compression level, specified by ZSTD_CLEVEL_DEFAULT, requires v1.5.0+ */
+
+
+/***************************************
+*  Explicit context
+***************************************/
+/*= Compression context
+ *  When compressing many times,
+ *  it is recommended to allocate a compression context just once,
+ *  and reuse it for each successive compression operation.
+ *  This will make the workload easier for system's memory.
+ *  Note : re-using context is just a speed / resource optimization.
+ *         It doesn't change the compression ratio, which remains identical.
+ *  Note 2: For parallel execution in multi-threaded environments,
+ *         use one different context per thread .
+ */
+typedef struct ZSTD_CCtx_s ZSTD_CCtx;
+ZSTDLIB_API ZSTD_CCtx* ZSTD_createCCtx(void);
+ZSTDLIB_API size_t     ZSTD_freeCCtx(ZSTD_CCtx* cctx);  /* compatible with NULL pointer */
+
+/*! ZSTD_compressCCtx() :
+ *  Same as ZSTD_compress(), using an explicit ZSTD_CCtx.
+ *  Important : in order to mirror `ZSTD_compress()` behavior,
+ *  this function compresses at the requested compression level,
+ *  __ignoring any other advanced parameter__ .
+ *  If any advanced parameter was set using the advanced API,
+ *  they will all be reset. Only @compressionLevel remains.
+ */
+ZSTDLIB_API size_t ZSTD_compressCCtx(ZSTD_CCtx* cctx,
+                                     void* dst, size_t dstCapacity,
+                               const void* src, size_t srcSize,
+                                     int compressionLevel);
+
+/*= Decompression context
+ *  When decompressing many times,
+ *  it is recommended to allocate a context only once,
+ *  and reuse it for each successive compression operation.
+ *  This will make workload friendlier for system's memory.
+ *  Use one context per thread for parallel execution. */
+typedef struct ZSTD_DCtx_s ZSTD_DCtx;
+ZSTDLIB_API ZSTD_DCtx* ZSTD_createDCtx(void);
+ZSTDLIB_API size_t     ZSTD_freeDCtx(ZSTD_DCtx* dctx);  /* accept NULL pointer */
+
+/*! ZSTD_decompressDCtx() :
+ *  Same as ZSTD_decompress(),
+ *  requires an allocated ZSTD_DCtx.
+ *  Compatible with sticky parameters (see below).
+ */
+ZSTDLIB_API size_t ZSTD_decompressDCtx(ZSTD_DCtx* dctx,
+                                       void* dst, size_t dstCapacity,
+                                 const void* src, size_t srcSize);
+
+
+/*********************************************
+*  Advanced compression API (Requires v1.4.0+)
+**********************************************/
+
+/* API design :
+ *   Parameters are pushed one by one into an existing context,
+ *   using ZSTD_CCtx_set*() functions.
+ *   Pushed parameters are sticky : they are valid for next compressed frame, and any subsequent frame.
+ *   "sticky" parameters are applicable to `ZSTD_compress2()` and `ZSTD_compressStream*()` !
+ *   __They do not apply to one-shot variants such as ZSTD_compressCCtx()__ .
+ *
+ *   It's possible to reset all parameters to "default" using ZSTD_CCtx_reset().
+ *
+ *   This API supersedes all other "advanced" API entry points in the experimental section.
+ *   In the future, we expect to remove API entry points from experimental which are redundant with this API.
+ */
+
+
+/* Compression strategies, listed from fastest to strongest */
+typedef enum { ZSTD_fast=1,
+               ZSTD_dfast=2,
+               ZSTD_greedy=3,
+               ZSTD_lazy=4,
+               ZSTD_lazy2=5,
+               ZSTD_btlazy2=6,
+               ZSTD_btopt=7,
+               ZSTD_btultra=8,
+               ZSTD_btultra2=9
+               /* note : new strategies _might_ be added in the future.
+                         Only the order (from fast to strong) is guaranteed */
+} ZSTD_strategy;
+
+typedef enum {
+
+    /* compression parameters
+     * Note: When compressing with a ZSTD_CDict these parameters are superseded
+     * by the parameters used to construct the ZSTD_CDict.
+     * See ZSTD_CCtx_refCDict() for more info (superseded-by-cdict). */
+    ZSTD_c_compressionLevel=100, /* Set compression parameters according to pre-defined cLevel table.
+                              * Note that exact compression parameters are dynamically determined,
+                              * depending on both compression level and srcSize (when known).
+                              * Default level is ZSTD_CLEVEL_DEFAULT==3.
+                              * Special: value 0 means default, which is controlled by ZSTD_CLEVEL_DEFAULT.
+                              * Note 1 : it's possible to pass a negative compression level.
+                              * Note 2 : setting a level does not automatically set all other compression parameters
+                              *   to default. Setting this will however eventually dynamically impact the compression
+                              *   parameters which have not been manually set. The manually set
+                              *   ones will 'stick'. */
+    /* Advanced compression parameters :
+     * It's possible to pin down compression parameters to some specific values.
+     * In which case, these values are no longer dynamically selected by the compressor */
+    ZSTD_c_windowLog=101,    /* Maximum allowed back-reference distance, expressed as power of 2.
+                              * This will set a memory budget for streaming decompression,
+                              * with larger values requiring more memory
+                              * and typically compressing more.
+                              * Must be clamped between ZSTD_WINDOWLOG_MIN and ZSTD_WINDOWLOG_MAX.
+                              * Special: value 0 means "use default windowLog".
+                              * Note: Using a windowLog greater than ZSTD_WINDOWLOG_LIMIT_DEFAULT
+                              *       requires explicitly allowing such size at streaming decompression stage. */
+    ZSTD_c_hashLog=102,      /* Size of the initial probe table, as a power of 2.
+                              * Resulting memory usage is (1 << (hashLog+2)).
+                              * Must be clamped between ZSTD_HASHLOG_MIN and ZSTD_HASHLOG_MAX.
+                              * Larger tables improve compression ratio of strategies <= dFast,
+                              * and improve speed of strategies > dFast.
+                              * Special: value 0 means "use default hashLog". */
+    ZSTD_c_chainLog=103,     /* Size of the multi-probe search table, as a power of 2.
+                              * Resulting memory usage is (1 << (chainLog+2)).
+                              * Must be clamped between ZSTD_CHAINLOG_MIN and ZSTD_CHAINLOG_MAX.
+                              * Larger tables result in better and slower compression.
+                              * This parameter is useless for "fast" strategy.
+                              * It's still useful when using "dfast" strategy,
+                              * in which case it defines a secondary probe table.
+                              * Special: value 0 means "use default chainLog". */
+    ZSTD_c_searchLog=104,    /* Number of search attempts, as a power of 2.
+                              * More attempts result in better and slower compression.
+                              * This parameter is useless for "fast" and "dFast" strategies.
+                              * Special: value 0 means "use default searchLog". */
+    ZSTD_c_minMatch=105,     /* Minimum size of searched matches.
+                              * Note that Zstandard can still find matches of smaller size,
+                              * it just tweaks its search algorithm to look for this size and larger.
+                              * Larger values increase compression and decompression speed, but decrease ratio.
+                              * Must be clamped between ZSTD_MINMATCH_MIN and ZSTD_MINMATCH_MAX.
+                              * Note that currently, for all strategies < btopt, effective minimum is 4.
+                              *                    , for all strategies > fast, effective maximum is 6.
+                              * Special: value 0 means "use default minMatchLength". */
+    ZSTD_c_targetLength=106, /* Impact of this field depends on strategy.
+                              * For strategies btopt, btultra & btultra2:
+                              *     Length of Match considered "good enough" to stop search.
+                              *     Larger values make compression stronger, and slower.
+                              * For strategy fast:
+                              *     Distance between match sampling.
+                              *     Larger values make compression faster, and weaker.
+                              * Special: value 0 means "use default targetLength". */
+    ZSTD_c_strategy=107,     /* See ZSTD_strategy enum definition.
+                              * The higher the value of selected strategy, the more complex it is,
+                              * resulting in stronger and slower compression.
+                              * Special: value 0 means "use default strategy". */
+
+    ZSTD_c_targetCBlockSize=130, /* v1.5.6+
+                                  * Attempts to fit compressed block size into approximately targetCBlockSize.
+                                  * Bound by ZSTD_TARGETCBLOCKSIZE_MIN and ZSTD_TARGETCBLOCKSIZE_MAX.
+                                  * Note that it's not a guarantee, just a convergence target (default:0).
+                                  * No target when targetCBlockSize == 0.
+                                  * This is helpful in low bandwidth streaming environments to improve end-to-end latency,
+                                  * when a client can make use of partial documents (a prominent example being Chrome).
+                                  * Note: this parameter is stable since v1.5.6.
+                                  * It was present as an experimental parameter in earlier versions,
+                                  * but it's not recommended using it with earlier library versions
+                                  * due to massive performance regressions.
+                                  */
+    /* LDM mode parameters */
+    ZSTD_c_enableLongDistanceMatching=160, /* Enable long distance matching.
+                                     * This parameter is designed to improve compression ratio
+                                     * for large inputs, by finding large matches at long distance.
+                                     * It increases memory usage and window size.
+                                     * Note: enabling this parameter increases default ZSTD_c_windowLog to 128 MB
+                                     * except when expressly set to a different value.
+                                     * Note: will be enabled by default if ZSTD_c_windowLog >= 128 MB and
+                                     * compression strategy >= ZSTD_btopt (== compression level 16+) */
+    ZSTD_c_ldmHashLog=161,   /* Size of the table for long distance matching, as a power of 2.
+                              * Larger values increase memory usage and compression ratio,
+                              * but decrease compression speed.
+                              * Must be clamped between ZSTD_HASHLOG_MIN and ZSTD_HASHLOG_MAX
+                              * default: windowlog - 7.
+                              * Special: value 0 means "automatically determine hashlog". */
+    ZSTD_c_ldmMinMatch=162,  /* Minimum match size for long distance matcher.
+                              * Larger/too small values usually decrease compression ratio.
+                              * Must be clamped between ZSTD_LDM_MINMATCH_MIN and ZSTD_LDM_MINMATCH_MAX.
+                              * Special: value 0 means "use default value" (default: 64). */
+    ZSTD_c_ldmBucketSizeLog=163, /* Log size of each bucket in the LDM hash table for collision resolution.
+                              * Larger values improve collision resolution but decrease compression speed.
+                              * The maximum value is ZSTD_LDM_BUCKETSIZELOG_MAX.
+                              * Special: value 0 means "use default value" (default: 3). */
+    ZSTD_c_ldmHashRateLog=164, /* Frequency of inserting/looking up entries into the LDM hash table.
+                              * Must be clamped between 0 and (ZSTD_WINDOWLOG_MAX - ZSTD_HASHLOG_MIN).
+                              * Default is MAX(0, (windowLog - ldmHashLog)), optimizing hash table usage.
+                              * Larger values improve compression speed.
+                              * Deviating far from default value will likely result in a compression ratio decrease.
+                              * Special: value 0 means "automatically determine hashRateLog". */
+
+    /* frame parameters */
+    ZSTD_c_contentSizeFlag=200, /* Content size will be written into frame header _whenever known_ (default:1)
+                              * Content size must be known at the beginning of compression.
+                              * This is automatically the case when using ZSTD_compress2(),
+                              * For streaming scenarios, content size must be provided with ZSTD_CCtx_setPledgedSrcSize() */
+    ZSTD_c_checksumFlag=201, /* A 32-bits checksum of content is written at end of frame (default:0) */
+    ZSTD_c_dictIDFlag=202,   /* When applicable, dictionary's ID is written into frame header (default:1) */
+
+    /* multi-threading parameters */
+    /* These parameters are only active if multi-threading is enabled (compiled with build macro ZSTD_MULTITHREAD).
+     * Otherwise, trying to set any other value than default (0) will be a no-op and return an error.
+     * In a situation where it's unknown if the linked library supports multi-threading or not,
+     * setting ZSTD_c_nbWorkers to any value >= 1 and consulting the return value provides a quick way to check this property.
+     */
+    ZSTD_c_nbWorkers=400,    /* Select how many threads will be spawned to compress in parallel.
+                              * When nbWorkers >= 1, triggers asynchronous mode when invoking ZSTD_compressStream*() :
+                              * ZSTD_compressStream*() consumes input and flush output if possible, but immediately gives back control to caller,
+                              * while compression is performed in parallel, within worker thread(s).
+                              * (note : a strong exception to this rule is when first invocation of ZSTD_compressStream2() sets ZSTD_e_end :
+                              *  in which case, ZSTD_compressStream2() delegates to ZSTD_compress2(), which is always a blocking call).
+                              * More workers improve speed, but also increase memory usage.
+                              * Default value is `0`, aka "single-threaded mode" : no worker is spawned,
+                              * compression is performed inside Caller's thread, and all invocations are blocking */
+    ZSTD_c_jobSize=401,      /* Size of a compression job. This value is enforced only when nbWorkers >= 1.
+                              * Each compression job is completed in parallel, so this value can indirectly impact the nb of active threads.
+                              * 0 means default, which is dynamically determined based on compression parameters.
+                              * Job size must be a minimum of overlap size, or ZSTDMT_JOBSIZE_MIN (= 512 KB), whichever is largest.
+                              * The minimum size is automatically and transparently enforced. */
+    ZSTD_c_overlapLog=402,   /* Control the overlap size, as a fraction of window size.
+                              * The overlap size is an amount of data reloaded from previous job at the beginning of a new job.
+                              * It helps preserve compression ratio, while each job is compressed in parallel.
+                              * This value is enforced only when nbWorkers >= 1.
+                              * Larger values increase compression ratio, but decrease speed.
+                              * Possible values range from 0 to 9 :
+                              * - 0 means "default" : value will be determined by the library, depending on strategy
+                              * - 1 means "no overlap"
+                              * - 9 means "full overlap", using a full window size.
+                              * Each intermediate rank increases/decreases load size by a factor 2 :
+                              * 9: full window;  8: w/2;  7: w/4;  6: w/8;  5:w/16;  4: w/32;  3:w/64;  2:w/128;  1:no overlap;  0:default
+                              * default value varies between 6 and 9, depending on strategy */
+
+    /* note : additional experimental parameters are also available
+     * within the experimental section of the API.
+     * At the time of this writing, they include :
+     * ZSTD_c_rsyncable
+     * ZSTD_c_format
+     * ZSTD_c_forceMaxWindow
+     * ZSTD_c_forceAttachDict
+     * ZSTD_c_literalCompressionMode
+     * ZSTD_c_srcSizeHint
+     * ZSTD_c_enableDedicatedDictSearch
+     * ZSTD_c_stableInBuffer
+     * ZSTD_c_stableOutBuffer
+     * ZSTD_c_blockDelimiters
+     * ZSTD_c_validateSequences
+     * ZSTD_c_blockSplitterLevel
+     * ZSTD_c_splitAfterSequences
+     * ZSTD_c_useRowMatchFinder
+     * ZSTD_c_prefetchCDictTables
+     * ZSTD_c_enableSeqProducerFallback
+     * ZSTD_c_maxBlockSize
+     * Because they are not stable, it's necessary to define ZSTD_STATIC_LINKING_ONLY to access them.
+     * note : never ever use experimentalParam? names directly;
+     *        also, the enums values themselves are unstable and can still change.
+     */
+     ZSTD_c_experimentalParam1=500,
+     ZSTD_c_experimentalParam2=10,
+     ZSTD_c_experimentalParam3=1000,
+     ZSTD_c_experimentalParam4=1001,
+     ZSTD_c_experimentalParam5=1002,
+     /* was ZSTD_c_experimentalParam6=1003; is now ZSTD_c_targetCBlockSize */
+     ZSTD_c_experimentalParam7=1004,
+     ZSTD_c_experimentalParam8=1005,
+     ZSTD_c_experimentalParam9=1006,
+     ZSTD_c_experimentalParam10=1007,
+     ZSTD_c_experimentalParam11=1008,
+     ZSTD_c_experimentalParam12=1009,
+     ZSTD_c_experimentalParam13=1010,
+     ZSTD_c_experimentalParam14=1011,
+     ZSTD_c_experimentalParam15=1012,
+     ZSTD_c_experimentalParam16=1013,
+     ZSTD_c_experimentalParam17=1014,
+     ZSTD_c_experimentalParam18=1015,
+     ZSTD_c_experimentalParam19=1016,
+     ZSTD_c_experimentalParam20=1017
+} ZSTD_cParameter;
+
+typedef struct {
+    size_t error;
+    int lowerBound;
+    int upperBound;
+} ZSTD_bounds;
+
+/*! ZSTD_cParam_getBounds() :
+ *  All parameters must belong to an interval with lower and upper bounds,
+ *  otherwise they will either trigger an error or be automatically clamped.
+ * @return : a structure, ZSTD_bounds, which contains
+ *         - an error status field, which must be tested using ZSTD_isError()
+ *         - lower and upper bounds, both inclusive
+ */
+ZSTDLIB_API ZSTD_bounds ZSTD_cParam_getBounds(ZSTD_cParameter cParam);
+
+/*! ZSTD_CCtx_setParameter() :
+ *  Set one compression parameter, selected by enum ZSTD_cParameter.
+ *  All parameters have valid bounds. Bounds can be queried using ZSTD_cParam_getBounds().
+ *  Providing a value beyond bound will either clamp it, or trigger an error (depending on parameter).
+ *  Setting a parameter is generally only possible during frame initialization (before starting compression).
+ *  Exception : when using multi-threading mode (nbWorkers >= 1),
+ *              the following parameters can be updated _during_ compression (within same frame):
+ *              => compressionLevel, hashLog, chainLog, searchLog, minMatch, targetLength and strategy.
+ *              new parameters will be active for next job only (after a flush()).
+ * @return : an error code (which can be tested using ZSTD_isError()).
+ */
+ZSTDLIB_API size_t ZSTD_CCtx_setParameter(ZSTD_CCtx* cctx, ZSTD_cParameter param, int value);
+
+/*! ZSTD_CCtx_setPledgedSrcSize() :
+ *  Total input data size to be compressed as a single frame.
+ *  Value will be written in frame header, unless if explicitly forbidden using ZSTD_c_contentSizeFlag.
+ *  This value will also be controlled at end of frame, and trigger an error if not respected.
+ * @result : 0, or an error code (which can be tested with ZSTD_isError()).
+ *  Note 1 : pledgedSrcSize==0 actually means zero, aka an empty frame.
+ *           In order to mean "unknown content size", pass constant ZSTD_CONTENTSIZE_UNKNOWN.
+ *           ZSTD_CONTENTSIZE_UNKNOWN is default value for any new frame.
+ *  Note 2 : pledgedSrcSize is only valid once, for the next frame.
+ *           It's discarded at the end of the frame, and replaced by ZSTD_CONTENTSIZE_UNKNOWN.
+ *  Note 3 : Whenever all input data is provided and consumed in a single round,
+ *           for example with ZSTD_compress2(),
+ *           or invoking immediately ZSTD_compressStream2(,,,ZSTD_e_end),
+ *           this value is automatically overridden by srcSize instead.
+ */
+ZSTDLIB_API size_t ZSTD_CCtx_setPledgedSrcSize(ZSTD_CCtx* cctx, unsigned long long pledgedSrcSize);
+
+typedef enum {
+    ZSTD_reset_session_only = 1,
+    ZSTD_reset_parameters = 2,
+    ZSTD_reset_session_and_parameters = 3
+} ZSTD_ResetDirective;
+
+/*! ZSTD_CCtx_reset() :
+ *  There are 2 different things that can be reset, independently or jointly :
+ *  - The session : will stop compressing current frame, and make CCtx ready to start a new one.
+ *                  Useful after an error, or to interrupt any ongoing compression.
+ *                  Any internal data not yet flushed is cancelled.
+ *                  Compression parameters and dictionary remain unchanged.
+ *                  They will be used to compress next frame.
+ *                  Resetting session never fails.
+ *  - The parameters : changes all parameters back to "default".
+ *                  This also removes any reference to any dictionary or external sequence producer.
+ *                  Parameters can only be changed between 2 sessions (i.e. no compression is currently ongoing)
+ *                  otherwise the reset fails, and function returns an error value (which can be tested using ZSTD_isError())
+ *  - Both : similar to resetting the session, followed by resetting parameters.
+ */
+ZSTDLIB_API size_t ZSTD_CCtx_reset(ZSTD_CCtx* cctx, ZSTD_ResetDirective reset);
+
+
+/***********************************************
+*  Advanced decompression API (Requires v1.4.0+)
+************************************************/
+
+/* The advanced API pushes parameters one by one into an existing DCtx context.
+ * Parameters are sticky, and remain valid for all following frames
+ * using the same DCtx context.
+ * It's possible to reset parameters to default values using ZSTD_DCtx_reset().
+ * Note : This API is compatible with existing ZSTD_decompressDCtx() and ZSTD_decompressStream().
+ *        Therefore, no new decompression function is necessary.
+ */
+
+typedef enum {
+
+    ZSTD_d_windowLogMax=100, /* Select a size limit (in power of 2) beyond which
+                              * the streaming API will refuse to allocate memory buffer
+                              * in order to protect the host from unreasonable memory requirements.
+                              * This parameter is only useful in streaming mode, since no internal buffer is allocated in single-pass mode.
+                              * By default, a decompression context accepts window sizes <= (1 << ZSTD_WINDOWLOG_LIMIT_DEFAULT).
+                              * Special: value 0 means "use default maximum windowLog". */
+
+    /* note : additional experimental parameters are also available
+     * within the experimental section of the API.
+     * At the time of this writing, they include :
+     * ZSTD_d_format
+     * ZSTD_d_stableOutBuffer
+     * ZSTD_d_forceIgnoreChecksum
+     * ZSTD_d_refMultipleDDicts
+     * ZSTD_d_disableHuffmanAssembly
+     * ZSTD_d_maxBlockSize
+     * Because they are not stable, it's necessary to define ZSTD_STATIC_LINKING_ONLY to access them.
+     * note : never ever use experimentalParam? names directly
+     */
+     ZSTD_d_experimentalParam1=1000,
+     ZSTD_d_experimentalParam2=1001,
+     ZSTD_d_experimentalParam3=1002,
+     ZSTD_d_experimentalParam4=1003,
+     ZSTD_d_experimentalParam5=1004,
+     ZSTD_d_experimentalParam6=1005
+
+} ZSTD_dParameter;
+
+/*! ZSTD_dParam_getBounds() :
+ *  All parameters must belong to an interval with lower and upper bounds,
+ *  otherwise they will either trigger an error or be automatically clamped.
+ * @return : a structure, ZSTD_bounds, which contains
+ *         - an error status field, which must be tested using ZSTD_isError()
+ *         - both lower and upper bounds, inclusive
+ */
+ZSTDLIB_API ZSTD_bounds ZSTD_dParam_getBounds(ZSTD_dParameter dParam);
+
+/*! ZSTD_DCtx_setParameter() :
+ *  Set one compression parameter, selected by enum ZSTD_dParameter.
+ *  All parameters have valid bounds. Bounds can be queried using ZSTD_dParam_getBounds().
+ *  Providing a value beyond bound will either clamp it, or trigger an error (depending on parameter).
+ *  Setting a parameter is only possible during frame initialization (before starting decompression).
+ * @return : 0, or an error code (which can be tested using ZSTD_isError()).
+ */
+ZSTDLIB_API size_t ZSTD_DCtx_setParameter(ZSTD_DCtx* dctx, ZSTD_dParameter param, int value);
+
+/*! ZSTD_DCtx_reset() :
+ *  Return a DCtx to clean state.
+ *  Session and parameters can be reset jointly or separately.
+ *  Parameters can only be reset when no active frame is being decompressed.
+ * @return : 0, or an error code, which can be tested with ZSTD_isError()
+ */
+ZSTDLIB_API size_t ZSTD_DCtx_reset(ZSTD_DCtx* dctx, ZSTD_ResetDirective reset);
+
+
+/****************************
+*  Streaming
+****************************/
+
+typedef struct ZSTD_inBuffer_s {
+  const void* src;    /**< start of input buffer */
+  size_t size;        /**< size of input buffer */
+  size_t pos;         /**< position where reading stopped. Will be updated. Necessarily 0 <= pos <= size */
+} ZSTD_inBuffer;
+
+typedef struct ZSTD_outBuffer_s {
+  void*  dst;         /**< start of output buffer */
+  size_t size;        /**< size of output buffer */
+  size_t pos;         /**< position where writing stopped. Will be updated. Necessarily 0 <= pos <= size */
+} ZSTD_outBuffer;
+
+/**************************
+*  Simple dictionary API
+***************************/
+/*! ZSTD_compress_usingDict() :
+ *  Compression at an explicit compression level using a Dictionary.
+ *  A dictionary can be any arbitrary data segment (also called a prefix),
+ *  or a buffer with specified information (see zdict.h).
+ *  Note : This function loads the dictionary, resulting in significant startup delay.
+ *         It's intended for a dictionary used only once.
+ *  Note 2 : When `dict == NULL || dictSize < 8` no dictionary is used. */
+ZSTDLIB_API size_t ZSTD_compress_usingDict(ZSTD_CCtx* ctx,
+                                           void* dst, size_t dstCapacity,
+                                     const void* src, size_t srcSize,
+                                     const void* dict,size_t dictSize,
+                                           int compressionLevel);
+
+/*! ZSTD_decompress_usingDict() :
+ *  Decompression using a known Dictionary.
+ *  Dictionary must be identical to the one used during compression.
+ *  Note : This function loads the dictionary, resulting in significant startup delay.
+ *         It's intended for a dictionary used only once.
+ *  Note : When `dict == NULL || dictSize < 8` no dictionary is used. */
+ZSTDLIB_API size_t ZSTD_decompress_usingDict(ZSTD_DCtx* dctx,
+                                             void* dst, size_t dstCapacity,
+                                       const void* src, size_t srcSize,
+                                       const void* dict,size_t dictSize);
+
+
+/***********************************
+ *  Bulk processing dictionary API
+ **********************************/
+typedef struct ZSTD_CDict_s ZSTD_CDict;
+
+/*! ZSTD_createCDict() :
+ *  When compressing multiple messages or blocks using the same dictionary,
+ *  it's recommended to digest the dictionary only once, since it's a costly operation.
+ *  ZSTD_createCDict() will create a state from digesting a dictionary.
+ *  The resulting state can be used for future compression operations with very limited startup cost.
+ *  ZSTD_CDict can be created once and shared by multiple threads concurrently, since its usage is read-only.
+ * @dictBuffer can be released after ZSTD_CDict creation, because its content is copied within CDict.
+ *  Note 1 : Consider experimental function `ZSTD_createCDict_byReference()` if you prefer to not duplicate @dictBuffer content.
+ *  Note 2 : A ZSTD_CDict can be created from an empty @dictBuffer,
+ *      in which case the only thing that it transports is the @compressionLevel.
+ *      This can be useful in a pipeline featuring ZSTD_compress_usingCDict() exclusively,
+ *      expecting a ZSTD_CDict parameter with any data, including those without a known dictionary. */
+ZSTDLIB_API ZSTD_CDict* ZSTD_createCDict(const void* dictBuffer, size_t dictSize,
+                                         int compressionLevel);
+
+/*! ZSTD_freeCDict() :
+ *  Function frees memory allocated by ZSTD_createCDict().
+ *  If a NULL pointer is passed, no operation is performed. */
+ZSTDLIB_API size_t      ZSTD_freeCDict(ZSTD_CDict* CDict);
+
+/*! ZSTD_compress_usingCDict() :
+ *  Compression using a digested Dictionary.
+ *  Recommended when same dictionary is used multiple times.
+ *  Note : compression level is _decided at dictionary creation time_,
+ *     and frame parameters are hardcoded (dictID=yes, contentSize=yes, checksum=no) */
+ZSTDLIB_API size_t ZSTD_compress_usingCDict(ZSTD_CCtx* cctx,
+                                            void* dst, size_t dstCapacity,
+                                      const void* src, size_t srcSize,
+                                      const ZSTD_CDict* cdict);
+
+
+typedef struct ZSTD_DDict_s ZSTD_DDict;
+
+/*! ZSTD_createDDict() :
+ *  Create a digested dictionary, ready to start decompression operation without startup delay.
+ *  dictBuffer can be released after DDict creation, as its content is copied inside DDict. */
+ZSTDLIB_API ZSTD_DDict* ZSTD_createDDict(const void* dictBuffer, size_t dictSize);
+
+/*! ZSTD_freeDDict() :
+ *  Function frees memory allocated with ZSTD_createDDict()
+ *  If a NULL pointer is passed, no operation is performed. */
+ZSTDLIB_API size_t      ZSTD_freeDDict(ZSTD_DDict* ddict);
+
+/*! ZSTD_decompress_usingDDict() :
+ *  Decompression using a digested Dictionary.
+ *  Recommended when same dictionary is used multiple times. */
+ZSTDLIB_API size_t ZSTD_decompress_usingDDict(ZSTD_DCtx* dctx,
+                                              void* dst, size_t dstCapacity,
+                                        const void* src, size_t srcSize,
+                                        const ZSTD_DDict* ddict);
+
+
+/********************************
+ *  Dictionary helper functions
+ *******************************/
+
+/*! ZSTD_getDictID_fromDict() : Requires v1.4.0+
+ *  Provides the dictID stored within dictionary.
+ *  if @return == 0, the dictionary is not conformant with Zstandard specification.
+ *  It can still be loaded, but as a content-only dictionary. */
+ZSTDLIB_API unsigned ZSTD_getDictID_fromDict(const void* dict, size_t dictSize);
+
+/*! ZSTD_getDictID_fromCDict() : Requires v1.5.0+
+ *  Provides the dictID of the dictionary loaded into `cdict`.
+ *  If @return == 0, the dictionary is not conformant to Zstandard specification, or empty.
+ *  Non-conformant dictionaries can still be loaded, but as content-only dictionaries. */
+ZSTDLIB_API unsigned ZSTD_getDictID_fromCDict(const ZSTD_CDict* cdict);
+
+/*! ZSTD_getDictID_fromDDict() : Requires v1.4.0+
+ *  Provides the dictID of the dictionary loaded into `ddict`.
+ *  If @return == 0, the dictionary is not conformant to Zstandard specification, or empty.
+ *  Non-conformant dictionaries can still be loaded, but as content-only dictionaries. */
+ZSTDLIB_API unsigned ZSTD_getDictID_fromDDict(const ZSTD_DDict* ddict);
+
+/*! ZSTD_getDictID_fromFrame() : Requires v1.4.0+
+ *  Provides the dictID required to decompressed the frame stored within `src`.
+ *  If @return == 0, the dictID could not be decoded.
+ *  This could for one of the following reasons :
+ *  - The frame does not require a dictionary to be decoded (most common case).
+ *  - The frame was built with dictID intentionally removed. Whatever dictionary is necessary is a hidden piece of information.
+ *    Note : this use case also happens when using a non-conformant dictionary.
+ *  - `srcSize` is too small, and as a result, the frame header could not be decoded (only possible if `srcSize < ZSTD_FRAMEHEADERSIZE_MAX`).
+ *  - This is not a Zstandard frame.
+ *  When identifying the exact failure cause, it's possible to use ZSTD_getFrameHeader(), which will provide a more precise error code. */
+ZSTDLIB_API unsigned ZSTD_getDictID_fromFrame(const void* src, size_t srcSize);
+
+
+/*******************************************************************************
+ * Advanced dictionary and prefix API (Requires v1.4.0+)
+ *
+ * This API allows dictionaries to be used with ZSTD_compress2(),
+ * ZSTD_compressStream2(), and ZSTD_decompressDCtx().
+ * Dictionaries are sticky, they remain valid when same context is reused,
+ * they only reset when the context is reset
+ * with ZSTD_reset_parameters or ZSTD_reset_session_and_parameters.
+ * In contrast, Prefixes are single-use.
+ ******************************************************************************/
+
+
+/*! ZSTD_CCtx_loadDictionary() : Requires v1.4.0+
+ *  Create an internal CDict from `dict` buffer.
+ *  Decompression will have to use same dictionary.
+ * @result : 0, or an error code (which can be tested with ZSTD_isError()).
+ *  Special: Loading a NULL (or 0-size) dictionary invalidates previous dictionary,
+ *           meaning "return to no-dictionary mode".
+ *  Note 1 : Dictionary is sticky, it will be used for all future compressed frames,
+ *           until parameters are reset, a new dictionary is loaded, or the dictionary
+ *           is explicitly invalidated by loading a NULL dictionary.
+ *  Note 2 : Loading a dictionary involves building tables.
+ *           It's also a CPU consuming operation, with non-negligible impact on latency.
+ *           Tables are dependent on compression parameters, and for this reason,
+ *           compression parameters can no longer be changed after loading a dictionary.
+ *  Note 3 :`dict` content will be copied internally.
+ *           Use experimental ZSTD_CCtx_loadDictionary_byReference() to reference content instead.
+ *           In such a case, dictionary buffer must outlive its users.
+ *  Note 4 : Use ZSTD_CCtx_loadDictionary_advanced()
+ *           to precisely select how dictionary content must be interpreted.
+ *  Note 5 : This method does not benefit from LDM (long distance mode).
+ *           If you want to employ LDM on some large dictionary content,
+ *           prefer employing ZSTD_CCtx_refPrefix() described below.
+ */
+ZSTDLIB_API size_t ZSTD_CCtx_loadDictionary(ZSTD_CCtx* cctx, const void* dict, size_t dictSize);
+
+/*! ZSTD_CCtx_refCDict() : Requires v1.4.0+
+ *  Reference a prepared dictionary, to be used for all future compressed frames.
+ *  Note that compression parameters are enforced from within CDict,
+ *  and supersede any compression parameter previously set within CCtx.
+ *  The parameters ignored are labelled as "superseded-by-cdict" in the ZSTD_cParameter enum docs.
+ *  The ignored parameters will be used again if the CCtx is returned to no-dictionary mode.
+ *  The dictionary will remain valid for future compressed frames using same CCtx.
+ * @result : 0, or an error code (which can be tested with ZSTD_isError()).
+ *  Special : Referencing a NULL CDict means "return to no-dictionary mode".
+ *  Note 1 : Currently, only one dictionary can be managed.
+ *           Referencing a new dictionary effectively "discards" any previous one.
+ *  Note 2 : CDict is just referenced, its lifetime must outlive its usage within CCtx. */
+ZSTDLIB_API size_t ZSTD_CCtx_refCDict(ZSTD_CCtx* cctx, const ZSTD_CDict* cdict);
+
+/*! ZSTD_CCtx_refPrefix() : Requires v1.4.0+
+ *  Reference a prefix (single-usage dictionary) for next compressed frame.
+ *  A prefix is **only used once**. Tables are discarded at end of frame (ZSTD_e_end).
+ *  Decompression will need same prefix to properly regenerate data.
+ *  Compressing with a prefix is similar in outcome as performing a diff and compressing it,
+ *  but performs much faster, especially during decompression (compression speed is tunable with compression level).
+ *  This method is compatible with LDM (long distance mode).
+ * @result : 0, or an error code (which can be tested with ZSTD_isError()).
+ *  Special: Adding any prefix (including NULL) invalidates any previous prefix or dictionary
+ *  Note 1 : Prefix buffer is referenced. It **must** outlive compression.
+ *           Its content must remain unmodified during compression.
+ *  Note 2 : If the intention is to diff some large src data blob with some prior version of itself,
+ *           ensure that the window size is large enough to contain the entire source.
+ *           See ZSTD_c_windowLog.
+ *  Note 3 : Referencing a prefix involves building tables, which are dependent on compression parameters.
+ *           It's a CPU consuming operation, with non-negligible impact on latency.
+ *           If there is a need to use the same prefix multiple times, consider loadDictionary instead.
+ *  Note 4 : By default, the prefix is interpreted as raw content (ZSTD_dct_rawContent).
+ *           Use experimental ZSTD_CCtx_refPrefix_advanced() to alter dictionary interpretation. */
+ZSTDLIB_API size_t ZSTD_CCtx_refPrefix(ZSTD_CCtx* cctx,
+                                 const void* prefix, size_t prefixSize);
+
+/*! ZSTD_DCtx_loadDictionary() : Requires v1.4.0+
+ *  Create an internal DDict from dict buffer, to be used to decompress all future frames.
+ *  The dictionary remains valid for all future frames, until explicitly invalidated, or
+ *  a new dictionary is loaded.
+ * @result : 0, or an error code (which can be tested with ZSTD_isError()).
+ *  Special : Adding a NULL (or 0-size) dictionary invalidates any previous dictionary,
+ *            meaning "return to no-dictionary mode".
+ *  Note 1 : Loading a dictionary involves building tables,
+ *           which has a non-negligible impact on CPU usage and latency.
+ *           It's recommended to "load once, use many times", to amortize the cost
+ *  Note 2 :`dict` content will be copied internally, so `dict` can be released after loading.
+ *           Use ZSTD_DCtx_loadDictionary_byReference() to reference dictionary content instead.
+ *  Note 3 : Use ZSTD_DCtx_loadDictionary_advanced() to take control of
+ *           how dictionary content is loaded and interpreted.
+ */
+ZSTDLIB_API size_t ZSTD_DCtx_loadDictionary(ZSTD_DCtx* dctx, const void* dict, size_t dictSize);
+
+/*! ZSTD_DCtx_refDDict() : Requires v1.4.0+
+ *  Reference a prepared dictionary, to be used to decompress next frames.
+ *  The dictionary remains active for decompression of future frames using same DCtx.
+ *
+ *  If called with ZSTD_d_refMultipleDDicts enabled, repeated calls of this function
+ *  will store the DDict references in a table, and the DDict used for decompression
+ *  will be determined at decompression time, as per the dict ID in the frame.
+ *  The memory for the table is allocated on the first call to refDDict, and can be
+ *  freed with ZSTD_freeDCtx().
+ *
+ *  If called with ZSTD_d_refMultipleDDicts disabled (the default), only one dictionary
+ *  will be managed, and referencing a dictionary effectively "discards" any previous one.
+ *
+ * @result : 0, or an error code (which can be tested with ZSTD_isError()).
+ *  Special: referencing a NULL DDict means "return to no-dictionary mode".
+ *  Note 2 : DDict is just referenced, its lifetime must outlive its usage from DCtx.
+ */
+ZSTDLIB_API size_t ZSTD_DCtx_refDDict(ZSTD_DCtx* dctx, const ZSTD_DDict* ddict);
+
+/*! ZSTD_DCtx_refPrefix() : Requires v1.4.0+
+ *  Reference a prefix (single-usage dictionary) to decompress next frame.
+ *  This is the reverse operation of ZSTD_CCtx_refPrefix(),
+ *  and must use the same prefix as the one used during compression.
+ *  Prefix is **only used once**. Reference is discarded at end of frame.
+ *  End of frame is reached when ZSTD_decompressStream() returns 0.
+ * @result : 0, or an error code (which can be tested with ZSTD_isError()).
+ *  Note 1 : Adding any prefix (including NULL) invalidates any previously set prefix or dictionary
+ *  Note 2 : Prefix buffer is referenced. It **must** outlive decompression.
+ *           Prefix buffer must remain unmodified up to the end of frame,
+ *           reached when ZSTD_decompressStream() returns 0.
+ *  Note 3 : By default, the prefix is treated as raw content (ZSTD_dct_rawContent).
+ *           Use ZSTD_CCtx_refPrefix_advanced() to alter dictMode (Experimental section)
+ *  Note 4 : Referencing a raw content prefix has almost no cpu nor memory cost.
+ *           A full dictionary is more costly, as it requires building tables.
+ */
+ZSTDLIB_API size_t ZSTD_DCtx_refPrefix(ZSTD_DCtx* dctx,
+                                 const void* prefix, size_t prefixSize);
+
+/* ===   Memory management   === */
+
+/*! ZSTD_sizeof_*() : Requires v1.4.0+
+ *  These functions give the _current_ memory usage of selected object.
+ *  Note that object memory usage can evolve (increase or decrease) over time. */
+ZSTDLIB_API size_t ZSTD_sizeof_CCtx(const ZSTD_CCtx* cctx);
+ZSTDLIB_API size_t ZSTD_sizeof_DCtx(const ZSTD_DCtx* dctx);
+ZSTDLIB_API size_t ZSTD_sizeof_CDict(const ZSTD_CDict* cdict);
+ZSTDLIB_API size_t ZSTD_sizeof_DDict(const ZSTD_DDict* ddict);
+
+#if defined (__cplusplus)
+}
+#endif
+
+#endif  /* ZSTD_H_235446 */
+
+
+/* **************************************************************************************
+ *   ADVANCED AND EXPERIMENTAL FUNCTIONS
+ ****************************************************************************************
+ * The definitions in the following section are considered experimental.
+ * They are provided for advanced scenarios.
+ * They should never be used with a dynamic library, as prototypes may change in the future.
+ * Use them only in association with static linking.
+ * ***************************************************************************************/
+
+#if defined(ZSTD_STATIC_LINKING_ONLY) && !defined(ZSTD_H_ZSTD_STATIC_LINKING_ONLY)
+#define ZSTD_H_ZSTD_STATIC_LINKING_ONLY
+
+#if defined (__cplusplus)
+extern "C" {
+#endif
+
+/* This can be overridden externally to hide static symbols. */
+#ifndef ZSTDLIB_STATIC_API
+#  if defined(ZSTD_DLL_EXPORT) && (ZSTD_DLL_EXPORT==1)
+#    define ZSTDLIB_STATIC_API __declspec(dllexport) ZSTDLIB_VISIBLE
+#  elif defined(ZSTD_DLL_IMPORT) && (ZSTD_DLL_IMPORT==1)
+#    define ZSTDLIB_STATIC_API __declspec(dllimport) ZSTDLIB_VISIBLE
+#  else
+#    define ZSTDLIB_STATIC_API ZSTDLIB_VISIBLE
+#  endif
+#endif
+
+/****************************************************************************************
+ *   experimental API (static linking only)
+ ****************************************************************************************
+ * The following symbols and constants
+ * are not planned to join "stable API" status in the near future.
+ * They can still change in future versions.
+ * Some of them are planned to remain in the static_only section indefinitely.
+ * Some of them might be removed in the future (especially when redundant with existing stable functions)
+ * ***************************************************************************************/
+
+#define ZSTD_FRAMEHEADERSIZE_PREFIX(format) ((format) == ZSTD_f_zstd1 ? 5 : 1)   /* minimum input size required to query frame header size */
+#define ZSTD_FRAMEHEADERSIZE_MIN(format)    ((format) == ZSTD_f_zstd1 ? 6 : 2)
+#define ZSTD_FRAMEHEADERSIZE_MAX   18   /* can be useful for static allocation */
+#define ZSTD_SKIPPABLEHEADERSIZE    8
+
+/* compression parameter bounds */
+#define ZSTD_WINDOWLOG_MAX_32    30
+#define ZSTD_WINDOWLOG_MAX_64    31
+#define ZSTD_WINDOWLOG_MAX     ((int)(sizeof(size_t) == 4 ? ZSTD_WINDOWLOG_MAX_32 : ZSTD_WINDOWLOG_MAX_64))
+#define ZSTD_WINDOWLOG_MIN       10
+#define ZSTD_HASHLOG_MAX       ((ZSTD_WINDOWLOG_MAX < 30) ? ZSTD_WINDOWLOG_MAX : 30)
+#define ZSTD_HASHLOG_MIN          6
+#define ZSTD_CHAINLOG_MAX_32     29
+#define ZSTD_CHAINLOG_MAX_64     30
+#define ZSTD_CHAINLOG_MAX      ((int)(sizeof(size_t) == 4 ? ZSTD_CHAINLOG_MAX_32 : ZSTD_CHAINLOG_MAX_64))
+#define ZSTD_CHAINLOG_MIN        ZSTD_HASHLOG_MIN
+#define ZSTD_SEARCHLOG_MAX      (ZSTD_WINDOWLOG_MAX-1)
+#define ZSTD_SEARCHLOG_MIN        1
+#define ZSTD_MINMATCH_MAX         7   /* only for ZSTD_fast, other strategies are limited to 6 */
+#define ZSTD_MINMATCH_MIN         3   /* only for ZSTD_btopt+, faster strategies are limited to 4 */
+#define ZSTD_TARGETLENGTH_MAX    ZSTD_BLOCKSIZE_MAX
+#define ZSTD_TARGETLENGTH_MIN     0   /* note : comparing this constant to an unsigned results in a tautological test */
+#define ZSTD_STRATEGY_MIN        ZSTD_fast
+#define ZSTD_STRATEGY_MAX        ZSTD_btultra2
+#define ZSTD_BLOCKSIZE_MAX_MIN (1 << 10) /* The minimum valid max blocksize. Maximum blocksizes smaller than this make compressBound() inaccurate. */
+
+
+#define ZSTD_OVERLAPLOG_MIN       0
+#define ZSTD_OVERLAPLOG_MAX       9
+
+#define ZSTD_WINDOWLOG_LIMIT_DEFAULT 27   /* by default, the streaming decoder will refuse any frame
+                                           * requiring larger than (1<<ZSTD_WINDOWLOG_LIMIT_DEFAULT) window size,
+                                           * to preserve host's memory from unreasonable requirements.
+                                           * This limit can be overridden using ZSTD_DCtx_setParameter(,ZSTD_d_windowLogMax,).
+                                           * The limit does not apply for one-pass decoders (such as ZSTD_decompress()), since no additional memory is allocated */
+
+
+/* LDM parameter bounds */
+#define ZSTD_LDM_HASHLOG_MIN      ZSTD_HASHLOG_MIN
+#define ZSTD_LDM_HASHLOG_MAX      ZSTD_HASHLOG_MAX
+#define ZSTD_LDM_MINMATCH_MIN        4
+#define ZSTD_LDM_MINMATCH_MAX     4096
+#define ZSTD_LDM_BUCKETSIZELOG_MIN   1
+#define ZSTD_LDM_BUCKETSIZELOG_MAX   8
+#define ZSTD_LDM_HASHRATELOG_MIN     0
+#define ZSTD_LDM_HASHRATELOG_MAX (ZSTD_WINDOWLOG_MAX - ZSTD_HASHLOG_MIN)
+
+/* Advanced parameter bounds */
+#define ZSTD_TARGETCBLOCKSIZE_MIN   1340 /* suitable to fit into an ethernet / wifi / 4G transport frame */
+#define ZSTD_TARGETCBLOCKSIZE_MAX   ZSTD_BLOCKSIZE_MAX
+#define ZSTD_SRCSIZEHINT_MIN        0
+#define ZSTD_SRCSIZEHINT_MAX        INT_MAX
+
+
+/* ---  Advanced types  --- */
+
+typedef struct ZSTD_CCtx_params_s ZSTD_CCtx_params;
+
+typedef struct {
+    unsigned int offset;      /* The offset of the match. (NOT the same as the offset code)
+                               * If offset == 0 and matchLength == 0, this sequence represents the last
+                               * literals in the block of litLength size.
+                               */
+
+    unsigned int litLength;   /* Literal length of the sequence. */
+    unsigned int matchLength; /* Match length of the sequence. */
+
+                              /* Note: Users of this API may provide a sequence with matchLength == litLength == offset == 0.
+                               * In this case, we will treat the sequence as a marker for a block boundary.
+                               */
+
+    unsigned int rep;         /* Represents which repeat offset is represented by the field 'offset'.
+                               * Ranges from [0, 3].
+                               *
+                               * Repeat offsets are essentially previous offsets from previous sequences sorted in
+                               * recency order. For more detail, see doc/zstd_compression_format.md
+                               *
+                               * If rep == 0, then 'offset' does not contain a repeat offset.
+                               * If rep > 0:
+                               *  If litLength != 0:
+                               *      rep == 1 --> offset == repeat_offset_1
+                               *      rep == 2 --> offset == repeat_offset_2
+                               *      rep == 3 --> offset == repeat_offset_3
+                               *  If litLength == 0:
+                               *      rep == 1 --> offset == repeat_offset_2
+                               *      rep == 2 --> offset == repeat_offset_3
+                               *      rep == 3 --> offset == repeat_offset_1 - 1
+                               *
+                               * Note: This field is optional. ZSTD_generateSequences() will calculate the value of
+                               * 'rep', but repeat offsets do not necessarily need to be calculated from an external
+                               * sequence provider perspective. For example, ZSTD_compressSequences() does not
+                               * use this 'rep' field at all (as of now).
+                               */
+} ZSTD_Sequence;
+
+typedef struct {
+    unsigned windowLog;       /**< largest match distance : larger == more compression, more memory needed during decompression */
+    unsigned chainLog;        /**< fully searched segment : larger == more compression, slower, more memory (useless for fast) */
+    unsigned hashLog;         /**< dispatch table : larger == faster, more memory */
+    unsigned searchLog;       /**< nb of searches : larger == more compression, slower */
+    unsigned minMatch;        /**< match length searched : larger == faster decompression, sometimes less compression */
+    unsigned targetLength;    /**< acceptable match size for optimal parser (only) : larger == more compression, slower */
+    ZSTD_strategy strategy;   /**< see ZSTD_strategy definition above */
+} ZSTD_compressionParameters;
+
+typedef struct {
+    int contentSizeFlag; /**< 1: content size will be in frame header (when known) */
+    int checksumFlag;    /**< 1: generate a 32-bits checksum using XXH64 algorithm at end of frame, for error detection */
+    int noDictIDFlag;    /**< 1: no dictID will be saved into frame header (dictID is only useful for dictionary compression) */
+} ZSTD_frameParameters;
+
+typedef struct {
+    ZSTD_compressionParameters cParams;
+    ZSTD_frameParameters fParams;
+} ZSTD_parameters;
+
+typedef enum {
+    ZSTD_dct_auto = 0,       /* dictionary is "full" when starting with ZSTD_MAGIC_DICTIONARY, otherwise it is "rawContent" */
+    ZSTD_dct_rawContent = 1, /* ensures dictionary is always loaded as rawContent, even if it starts with ZSTD_MAGIC_DICTIONARY */
+    ZSTD_dct_fullDict = 2    /* refuses to load a dictionary if it does not respect Zstandard's specification, starting with ZSTD_MAGIC_DICTIONARY */
+} ZSTD_dictContentType_e;
+
+typedef enum {
+    ZSTD_dlm_byCopy = 0,  /**< Copy dictionary content internally */
+    ZSTD_dlm_byRef = 1    /**< Reference dictionary content -- the dictionary buffer must outlive its users. */
+} ZSTD_dictLoadMethod_e;
+
+typedef enum {
+    ZSTD_f_zstd1 = 0,           /* zstd frame format, specified in zstd_compression_format.md (default) */
+    ZSTD_f_zstd1_magicless = 1  /* Variant of zstd frame format, without initial 4-bytes magic number.
+                                 * Useful to save 4 bytes per generated frame.
+                                 * Decoder cannot recognise automatically this format, requiring this instruction. */
+} ZSTD_format_e;
+
+typedef enum {
+    /* Note: this enum controls ZSTD_d_forceIgnoreChecksum */
+    ZSTD_d_validateChecksum = 0,
+    ZSTD_d_ignoreChecksum = 1
+} ZSTD_forceIgnoreChecksum_e;
+
+typedef enum {
+    /* Note: this enum controls ZSTD_d_refMultipleDDicts */
+    ZSTD_rmd_refSingleDDict = 0,
+    ZSTD_rmd_refMultipleDDicts = 1
+} ZSTD_refMultipleDDicts_e;
+
+typedef enum {
+    /* Note: this enum and the behavior it controls are effectively internal
+     * implementation details of the compressor. They are expected to continue
+     * to evolve and should be considered only in the context of extremely
+     * advanced performance tuning.
+     *
+     * Zstd currently supports the use of a CDict in three ways:
+     *
+     * - The contents of the CDict can be copied into the working context. This
+     *   means that the compression can search both the dictionary and input
+     *   while operating on a single set of internal tables. This makes
+     *   the compression faster per-byte of input. However, the initial copy of
+     *   the CDict's tables incurs a fixed cost at the beginning of the
+     *   compression. For small compressions (< 8 KB), that copy can dominate
+     *   the cost of the compression.
+     *
+     * - The CDict's tables can be used in-place. In this model, compression is
+     *   slower per input byte, because the compressor has to search two sets of
+     *   tables. However, this model incurs no start-up cost (as long as the
+     *   working context's tables can be reused). For small inputs, this can be
+     *   faster than copying the CDict's tables.
+     *
+     * - The CDict's tables are not used at all, and instead we use the working
+     *   context alone to reload the dictionary and use params based on the source
+     *   size. See ZSTD_compress_insertDictionary() and ZSTD_compress_usingDict().
+     *   This method is effective when the dictionary sizes are very small relative
+     *   to the input size, and the input size is fairly large to begin with.
+     *
+     * Zstd has a simple internal heuristic that selects which strategy to use
+     * at the beginning of a compression. However, if experimentation shows that
+     * Zstd is making poor choices, it is possible to override that choice with
+     * this enum.
+     */
+    ZSTD_dictDefaultAttach = 0, /* Use the default heuristic. */
+    ZSTD_dictForceAttach   = 1, /* Never copy the dictionary. */
+    ZSTD_dictForceCopy     = 2, /* Always copy the dictionary. */
+    ZSTD_dictForceLoad     = 3  /* Always reload the dictionary */
+} ZSTD_dictAttachPref_e;
+
+typedef enum {
+  ZSTD_lcm_auto = 0,          /**< Automatically determine the compression mode based on the compression level.
+                               *   Negative compression levels will be uncompressed, and positive compression
+                               *   levels will be compressed. */
+  ZSTD_lcm_huffman = 1,       /**< Always attempt Huffman compression. Uncompressed literals will still be
+                               *   emitted if Huffman compression is not profitable. */
+  ZSTD_lcm_uncompressed = 2   /**< Always emit uncompressed literals. */
+} ZSTD_literalCompressionMode_e;
+
+typedef enum {
+  /* Note: This enum controls features which are conditionally beneficial.
+   * Zstd can take a decision on whether or not to enable the feature (ZSTD_ps_auto),
+   * but setting the switch to ZSTD_ps_enable or ZSTD_ps_disable force enable/disable the feature.
+   */
+  ZSTD_ps_auto = 0,         /* Let the library automatically determine whether the feature shall be enabled */
+  ZSTD_ps_enable = 1,       /* Force-enable the feature */
+  ZSTD_ps_disable = 2       /* Do not use the feature */
+} ZSTD_ParamSwitch_e;
+#define ZSTD_paramSwitch_e ZSTD_ParamSwitch_e  /* old name */
+
+/***************************************
+*  Frame header and size functions
+***************************************/
+
+/*! ZSTD_frameHeaderSize() :
+ *  srcSize must be large enough, aka >= ZSTD_FRAMEHEADERSIZE_PREFIX.
+ * @return : size of the Frame Header,
+ *           or an error code (if srcSize is too small) */
+ZSTDLIB_STATIC_API size_t ZSTD_frameHeaderSize(const void* src, size_t srcSize);
+
+typedef enum { ZSTD_frame, ZSTD_skippableFrame } ZSTD_FrameType_e;
+#define ZSTD_frameType_e ZSTD_FrameType_e /* old name */
+typedef struct {
+    unsigned long long frameContentSize; /* if == ZSTD_CONTENTSIZE_UNKNOWN, it means this field is not available. 0 means "empty" */
+    unsigned long long windowSize;       /* can be very large, up to <= frameContentSize */
+    unsigned blockSizeMax;
+    ZSTD_FrameType_e frameType;          /* if == ZSTD_skippableFrame, frameContentSize is the size of skippable content */
+    unsigned headerSize;
+    unsigned dictID;                     /* for ZSTD_skippableFrame, contains the skippable magic variant [0-15] */
+    unsigned checksumFlag;
+    unsigned _reserved1;
+    unsigned _reserved2;
+} ZSTD_FrameHeader;
+#define ZSTD_frameHeader ZSTD_FrameHeader /* old name */
+
+/*! ZSTD_getFrameHeader() :
+ *  decode Frame Header into `zfhPtr`, or requires larger `srcSize`.
+ * @return : 0 => header is complete, `zfhPtr` is correctly filled,
+ *          >0 => `srcSize` is too small, @return value is the wanted `srcSize` amount, `zfhPtr` is not filled,
+ *           or an error code, which can be tested using ZSTD_isError() */
+ZSTDLIB_STATIC_API size_t ZSTD_getFrameHeader(ZSTD_FrameHeader* zfhPtr, const void* src, size_t srcSize);
+/*! ZSTD_getFrameHeader_advanced() :
+ *  same as ZSTD_getFrameHeader(),
+ *  with added capability to select a format (like ZSTD_f_zstd1_magicless) */
+ZSTDLIB_STATIC_API size_t ZSTD_getFrameHeader_advanced(ZSTD_FrameHeader* zfhPtr, const void* src, size_t srcSize, ZSTD_format_e format);
+
+/*! ZSTD_DECOMPRESS_MARGIN() :
+ * Similar to ZSTD_decompressionMargin(), but instead of computing the margin from
+ * the compressed frame, compute it from the original size and the blockSizeLog.
+ * See ZSTD_decompressionMargin() for details.
+ *
+ * WARNING: This macro does not support multi-frame input, the input must be a single
+ * zstd frame. If you need that support use the function, or implement it yourself.
+ *
+ * @param originalSize The original uncompressed size of the data.
+ * @param blockSize    The block size == MIN(windowSize, ZSTD_BLOCKSIZE_MAX).
+ *                     Unless you explicitly set the windowLog smaller than
+ *                     ZSTD_BLOCKSIZELOG_MAX you can just use ZSTD_BLOCKSIZE_MAX.
+ */
+#define ZSTD_DECOMPRESSION_MARGIN(originalSize, blockSize) ((size_t)(                                              \
+        ZSTD_FRAMEHEADERSIZE_MAX                                                              /* Frame header */ + \
+        4                                                                                         /* checksum */ + \
+        ((originalSize) == 0 ? 0 : 3 * (((originalSize) + (blockSize) - 1) / blockSize)) /* 3 bytes per block */ + \
+        (blockSize)                                                                    /* One block of margin */   \
+    ))
+
+typedef enum {
+  ZSTD_sf_noBlockDelimiters = 0,         /* ZSTD_Sequence[] has no block delimiters, just sequences */
+  ZSTD_sf_explicitBlockDelimiters = 1    /* ZSTD_Sequence[] contains explicit block delimiters */
+} ZSTD_SequenceFormat_e;
+#define ZSTD_sequenceFormat_e ZSTD_SequenceFormat_e /* old name */
+
+/*! ZSTD_sequenceBound() :
+ * `srcSize` : size of the input buffer
+ *  @return : upper-bound for the number of sequences that can be generated
+ *            from a buffer of srcSize bytes
+ *
+ *  note : returns number of sequences - to get bytes, multiply by sizeof(ZSTD_Sequence).
+ */
+ZSTDLIB_STATIC_API size_t ZSTD_sequenceBound(size_t srcSize);
+
+/*! ZSTD_generateSequences() :
+ * WARNING: This function is meant for debugging and informational purposes ONLY!
+ * Its implementation is flawed, and it will be deleted in a future version.
+ * It is not guaranteed to succeed, as there are several cases where it will give
+ * up and fail. You should NOT use this function in production code.
+ *
+ * This function is deprecated, and will be removed in a future version.
+ *
+ * Generate sequences using ZSTD_compress2(), given a source buffer.
+ *
+ * @param zc The compression context to be used for ZSTD_compress2(). Set any
+ *           compression parameters you need on this context.
+ * @param outSeqs The output sequences buffer of size @p outSeqsSize
+ * @param outSeqsCapacity The size of the output sequences buffer.
+ *                    ZSTD_sequenceBound(srcSize) is an upper bound on the number
+ *                    of sequences that can be generated.
+ * @param src The source buffer to generate sequences from of size @p srcSize.
+ * @param srcSize The size of the source buffer.
+ *
+ * Each block will end with a dummy sequence
+ * with offset == 0, matchLength == 0, and litLength == length of last literals.
+ * litLength may be == 0, and if so, then the sequence of (of: 0 ml: 0 ll: 0)
+ * simply acts as a block delimiter.
+ *
+ * @returns The number of sequences generated, necessarily less than
+ *          ZSTD_sequenceBound(srcSize), or an error code that can be checked
+ *          with ZSTD_isError().
+ */
+ZSTD_DEPRECATED("For debugging only, will be replaced by ZSTD_extractSequences()")
+ZSTDLIB_STATIC_API size_t
+ZSTD_generateSequences(ZSTD_CCtx* zc,
+                       ZSTD_Sequence* outSeqs, size_t outSeqsCapacity,
+                       const void* src, size_t srcSize);
+
+/*! ZSTD_mergeBlockDelimiters() :
+ * Given an array of ZSTD_Sequence, remove all sequences that represent block delimiters/last literals
+ * by merging them into the literals of the next sequence.
+ *
+ * As such, the final generated result has no explicit representation of block boundaries,
+ * and the final last literals segment is not represented in the sequences.
+ *
+ * The output of this function can be fed into ZSTD_compressSequences() with CCtx
+ * setting of ZSTD_c_blockDelimiters as ZSTD_sf_noBlockDelimiters
+ * @return : number of sequences left after merging
+ */
+ZSTDLIB_STATIC_API size_t ZSTD_mergeBlockDelimiters(ZSTD_Sequence* sequences, size_t seqsSize);
+
+/*! ZSTD_compressSequences() :
+ * Compress an array of ZSTD_Sequence, associated with @src buffer, into dst.
+ * @src contains the entire input (not just the literals).
+ * If @srcSize > sum(sequence.length), the remaining bytes are considered all literals
+ * If a dictionary is included, then the cctx should reference the dict (see: ZSTD_CCtx_refCDict(), ZSTD_CCtx_loadDictionary(), etc.).
+ * The entire source is compressed into a single frame.
+ *
+ * The compression behavior changes based on cctx params. In particular:
+ *    If ZSTD_c_blockDelimiters == ZSTD_sf_noBlockDelimiters, the array of ZSTD_Sequence is expected to contain
+ *    no block delimiters (defined in ZSTD_Sequence). Block boundaries are roughly determined based on
+ *    the block size derived from the cctx, and sequences may be split. This is the default setting.
+ *
+ *    If ZSTD_c_blockDelimiters == ZSTD_sf_explicitBlockDelimiters, the array of ZSTD_Sequence is expected to contain
+ *    valid block delimiters (defined in ZSTD_Sequence). Behavior is undefined if no block delimiters are provided.
+ *
+ *    When ZSTD_c_blockDelimiters == ZSTD_sf_explicitBlockDelimiters, it's possible to decide generating repcodes
+ *    using the advanced parameter ZSTD_c_repcodeResolution. Repcodes will improve compression ratio, though the benefit
+ *    can vary greatly depending on Sequences. On the other hand, repcode resolution is an expensive operation.
+ *    By default, it's disabled at low (<10) compression levels, and enabled above the threshold (>=10).
+ *    ZSTD_c_repcodeResolution makes it possible to directly manage this processing in either direction.
+ *
+ *    If ZSTD_c_validateSequences == 0, this function blindly accepts the Sequences provided. Invalid Sequences cause undefined
+ *    behavior. If ZSTD_c_validateSequences == 1, then the function will detect invalid Sequences (see doc/zstd_compression_format.md for
+ *    specifics regarding offset/matchlength requirements) and then bail out and return an error.
+ *
+ *    In addition to the two adjustable experimental params, there are other important cctx params.
+ *    - ZSTD_c_minMatch MUST be set as less than or equal to the smallest match generated by the match finder. It has a minimum value of ZSTD_MINMATCH_MIN.
+ *    - ZSTD_c_compressionLevel accordingly adjusts the strength of the entropy coder, as it would in typical compression.
+ *    - ZSTD_c_windowLog affects offset validation: this function will return an error at higher debug levels if a provided offset
+ *      is larger than what the spec allows for a given window log and dictionary (if present). See: doc/zstd_compression_format.md
+ *
+ * Note: Repcodes are, as of now, always re-calculated within this function, ZSTD_Sequence.rep is effectively unused.
+ * Dev Note: Once ability to ingest repcodes become available, the explicit block delims mode must respect those repcodes exactly,
+ *         and cannot emit an RLE block that disagrees with the repcode history.
+ * @return : final compressed size, or a ZSTD error code.
+ */
+ZSTDLIB_STATIC_API size_t
+ZSTD_compressSequences(ZSTD_CCtx* cctx,
+                       void* dst, size_t dstCapacity,
+                 const ZSTD_Sequence* inSeqs, size_t inSeqsSize,
+                 const void* src, size_t srcSize);
+
+
+/*! ZSTD_compressSequencesAndLiterals() :
+ * This is a variant of ZSTD_compressSequences() which,
+ * instead of receiving (src,srcSize) as input parameter, receives (literals,litSize),
+ * aka all the literals, already extracted and laid out into a single continuous buffer.
+ * This can be useful if the process generating the sequences also happens to generate the buffer of literals,
+ * thus skipping an extraction + caching stage.
+ * It's a speed optimization, useful when the right conditions are met,
+ * but it also features the following limitations:
+ * - Only supports explicit delimiter mode
+ * - Currently does not support Sequences validation (so input Sequences are trusted)
+ * - Not compatible with frame checksum, which must be disabled
+ * - If any block is incompressible, will fail and return an error
+ * - @litSize must be == sum of all @.litLength fields in @inSeqs. Any discrepancy will generate an error.
+ * - @litBufCapacity is the size of the underlying buffer into which literals are written, starting at address @literals.
+ *   @litBufCapacity must be at least 8 bytes larger than @litSize.
+ * - @decompressedSize must be correct, and correspond to the sum of all Sequences. Any discrepancy will generate an error.
+ * @return : final compressed size, or a ZSTD error code.
+ */
+ZSTDLIB_STATIC_API size_t
+ZSTD_compressSequencesAndLiterals(ZSTD_CCtx* cctx,
+                                  void* dst, size_t dstCapacity,
+                            const ZSTD_Sequence* inSeqs, size_t nbSequences,
+                            const void* literals, size_t litSize, size_t litBufCapacity,
+                            size_t decompressedSize);
+
+
+/*! ZSTD_writeSkippableFrame() :
+ * Generates a zstd skippable frame containing data given by src, and writes it to dst buffer.
+ *
+ * Skippable frames begin with a 4-byte magic number. There are 16 possible choices of magic number,
+ * ranging from ZSTD_MAGIC_SKIPPABLE_START to ZSTD_MAGIC_SKIPPABLE_START+15.
+ * As such, the parameter magicVariant controls the exact skippable frame magic number variant used,
+ * so the magic number used will be ZSTD_MAGIC_SKIPPABLE_START + magicVariant.
+ *
+ * Returns an error if destination buffer is not large enough, if the source size is not representable
+ * with a 4-byte unsigned int, or if the parameter magicVariant is greater than 15 (and therefore invalid).
+ *
+ * @return : number of bytes written or a ZSTD error.
+ */
+ZSTDLIB_STATIC_API size_t ZSTD_writeSkippableFrame(void* dst, size_t dstCapacity,
+                                             const void* src, size_t srcSize,
+                                                   unsigned magicVariant);
+
+/*! ZSTD_isSkippableFrame() :
+ *  Tells if the content of `buffer` starts with a valid Frame Identifier for a skippable frame.
+ */
+ZSTDLIB_STATIC_API unsigned ZSTD_isSkippableFrame(const void* buffer, size_t size);
+
+
+
+/***************************************
+*  Memory management
+***************************************/
+
+/*! ZSTD_estimate*() :
+ *  These functions make it possible to estimate memory usage
+ *  of a future {D,C}Ctx, before its creation.
+ *  This is useful in combination with ZSTD_initStatic(),
+ *  which makes it possible to employ a static buffer for ZSTD_CCtx* state.
+ *
+ *  ZSTD_estimateCCtxSize() will provide a memory budget large enough
+ *  to compress data of any size using one-shot compression ZSTD_compressCCtx() or ZSTD_compress2()
+ *  associated with any compression level up to max specified one.
+ *  The estimate will assume the input may be arbitrarily large,
+ *  which is the worst case.
+ *
+ *  Note that the size estimation is specific for one-shot compression,
+ *  it is not valid for streaming (see ZSTD_estimateCStreamSize*())
+ *  nor other potential ways of using a ZSTD_CCtx* state.
+ *
+ *  When srcSize can be bound by a known and rather "small" value,
+ *  this knowledge can be used to provide a tighter budget estimation
+ *  because the ZSTD_CCtx* state will need less memory for small inputs.
+ *  This tighter estimation can be provided by employing more advanced functions
+ *  ZSTD_estimateCCtxSize_usingCParams(), which can be used in tandem with ZSTD_getCParams(),
+ *  and ZSTD_estimateCCtxSize_usingCCtxParams(), which can be used in tandem with ZSTD_CCtxParams_setParameter().
+ *  Both can be used to estimate memory using custom compression parameters and arbitrary srcSize limits.
+ *
+ *  Note : only single-threaded compression is supported.
+ *  ZSTD_estimateCCtxSize_usingCCtxParams() will return an error code if ZSTD_c_nbWorkers is >= 1.
+ */
+ZSTDLIB_STATIC_API size_t ZSTD_estimateCCtxSize(int maxCompressionLevel);
+ZSTDLIB_STATIC_API size_t ZSTD_estimateCCtxSize_usingCParams(ZSTD_compressionParameters cParams);
+ZSTDLIB_STATIC_API size_t ZSTD_estimateCCtxSize_usingCCtxParams(const ZSTD_CCtx_params* params);
+ZSTDLIB_STATIC_API size_t ZSTD_estimateDCtxSize(void);
+
+/*! ZSTD_estimate?DictSize() :
+ *  ZSTD_estimateCDictSize() will bet that src size is relatively "small", and content is copied, like ZSTD_createCDict().
+ *  ZSTD_estimateCDictSize_advanced() makes it possible to control compression parameters precisely, like ZSTD_createCDict_advanced().
+ *  Note : dictionaries created by reference (`ZSTD_dlm_byRef`) are logically smaller.
+ */
+ZSTDLIB_STATIC_API size_t ZSTD_estimateCDictSize(size_t dictSize, int compressionLevel);
+ZSTDLIB_STATIC_API size_t ZSTD_estimateCDictSize_advanced(size_t dictSize, ZSTD_compressionParameters cParams, ZSTD_dictLoadMethod_e dictLoadMethod);
+ZSTDLIB_STATIC_API size_t ZSTD_estimateDDictSize(size_t dictSize, ZSTD_dictLoadMethod_e dictLoadMethod);
+
+/*! ZSTD_initStatic*() :
+ *  Initialize an object using a pre-allocated fixed-size buffer.
+ *  workspace: The memory area to emplace the object into.
+ *             Provided pointer *must be 8-bytes aligned*.
+ *             Buffer must outlive object.
+ *  workspaceSize: Use ZSTD_estimate*Size() to determine
+ *                 how large workspace must be to support target scenario.
+ * @return : pointer to object (same address as workspace, just different type),
+ *           or NULL if error (size too small, incorrect alignment, etc.)
+ *  Note : zstd will never resize nor malloc() when using a static buffer.
+ *         If the object requires more memory than available,
+ *         zstd will just error out (typically ZSTD_error_memory_allocation).
+ *  Note 2 : there is no corresponding "free" function.
+ *           Since workspace is allocated externally, it must be freed externally too.
+ *  Note 3 : cParams : use ZSTD_getCParams() to convert a compression level
+ *           into its associated cParams.
+ *  Limitation 1 : currently not compatible with internal dictionary creation, triggered by
+ *                 ZSTD_CCtx_loadDictionary(), ZSTD_initCStream_usingDict() or ZSTD_initDStream_usingDict().
+ *  Limitation 2 : static cctx currently not compatible with multi-threading.
+ *  Limitation 3 : static dctx is incompatible with legacy support.
+ */
+ZSTDLIB_STATIC_API ZSTD_CCtx*    ZSTD_initStaticCCtx(void* workspace, size_t workspaceSize);
+
+ZSTDLIB_STATIC_API ZSTD_DCtx*    ZSTD_initStaticDCtx(void* workspace, size_t workspaceSize);
+
+ZSTDLIB_STATIC_API const ZSTD_CDict* ZSTD_initStaticCDict(
+                                        void* workspace, size_t workspaceSize,
+                                        const void* dict, size_t dictSize,
+                                        ZSTD_dictLoadMethod_e dictLoadMethod,
+                                        ZSTD_dictContentType_e dictContentType,
+                                        ZSTD_compressionParameters cParams);
+
+ZSTDLIB_STATIC_API const ZSTD_DDict* ZSTD_initStaticDDict(
+                                        void* workspace, size_t workspaceSize,
+                                        const void* dict, size_t dictSize,
+                                        ZSTD_dictLoadMethod_e dictLoadMethod,
+                                        ZSTD_dictContentType_e dictContentType);
+
+
+/*! Custom memory allocation :
+ *  These prototypes make it possible to pass your own allocation/free functions.
+ *  ZSTD_customMem is provided at creation time, using ZSTD_create*_advanced() variants listed below.
+ *  All allocation/free operations will be completed using these custom variants instead of regular <stdlib.h> ones.
+ */
+typedef void* (*ZSTD_allocFunction) (void* opaque, size_t size);
+typedef void  (*ZSTD_freeFunction) (void* opaque, void* address);
+typedef struct { ZSTD_allocFunction customAlloc; ZSTD_freeFunction customFree; void* opaque; } ZSTD_customMem;
+static
+#ifdef __GNUC__
+__attribute__((__unused__))
+#endif
+
+#if defined(__clang__) && __clang_major__ >= 5
+#pragma clang diagnostic push
+#pragma clang diagnostic ignored "-Wzero-as-null-pointer-constant"
+#endif
+ZSTD_customMem const ZSTD_defaultCMem = { NULL, NULL, NULL };  /**< this constant defers to stdlib's functions */
+#if defined(__clang__) && __clang_major__ >= 5
+#pragma clang diagnostic pop
+#endif
+
+ZSTDLIB_STATIC_API ZSTD_CCtx*    ZSTD_createCCtx_advanced(ZSTD_customMem customMem);
+ZSTDLIB_STATIC_API ZSTD_DCtx*    ZSTD_createDCtx_advanced(ZSTD_customMem customMem);
+
+ZSTDLIB_STATIC_API ZSTD_CDict* ZSTD_createCDict_advanced(const void* dict, size_t dictSize,
+                                                  ZSTD_dictLoadMethod_e dictLoadMethod,
+                                                  ZSTD_dictContentType_e dictContentType,
+                                                  ZSTD_compressionParameters cParams,
+                                                  ZSTD_customMem customMem);
+
+/*! Thread pool :
+ *  These prototypes make it possible to share a thread pool among multiple compression contexts.
+ *  This can limit resources for applications with multiple threads where each one uses
+ *  a threaded compression mode (via ZSTD_c_nbWorkers parameter).
+ *  ZSTD_createThreadPool creates a new thread pool with a given number of threads.
+ *  Note that the lifetime of such pool must exist while being used.
+ *  ZSTD_CCtx_refThreadPool assigns a thread pool to a context (use NULL argument value
+ *  to use an internal thread pool).
+ *  ZSTD_freeThreadPool frees a thread pool, accepts NULL pointer.
+ */
+typedef struct POOL_ctx_s ZSTD_threadPool;
+ZSTDLIB_STATIC_API ZSTD_threadPool* ZSTD_createThreadPool(size_t numThreads);
+ZSTDLIB_STATIC_API void ZSTD_freeThreadPool (ZSTD_threadPool* pool);  /* accept NULL pointer */
+ZSTDLIB_STATIC_API size_t ZSTD_CCtx_refThreadPool(ZSTD_CCtx* cctx, ZSTD_threadPool* pool);
+
+
+/*
+ * This API is temporary and is expected to change or disappear in the future!
+ */
+ZSTDLIB_STATIC_API ZSTD_CDict* ZSTD_createCDict_advanced2(
+    const void* dict, size_t dictSize,
+    ZSTD_dictLoadMethod_e dictLoadMethod,
+    ZSTD_dictContentType_e dictContentType,
+    const ZSTD_CCtx_params* cctxParams,
+    ZSTD_customMem customMem);
+
+ZSTDLIB_STATIC_API ZSTD_DDict* ZSTD_createDDict_advanced(
+    const void* dict, size_t dictSize,
+    ZSTD_dictLoadMethod_e dictLoadMethod,
+    ZSTD_dictContentType_e dictContentType,
+    ZSTD_customMem customMem);
+
+
+/***************************************
+*  Advanced compression functions
+***************************************/
+
+/*! ZSTD_createCDict_byReference() :
+ *  Create a digested dictionary for compression
+ *  Dictionary content is just referenced, not duplicated.
+ *  As a consequence, `dictBuffer` **must** outlive CDict,
+ *  and its content must remain unmodified throughout the lifetime of CDict.
+ *  note: equivalent to ZSTD_createCDict_advanced(), with dictLoadMethod==ZSTD_dlm_byRef */
+ZSTDLIB_STATIC_API ZSTD_CDict* ZSTD_createCDict_byReference(const void* dictBuffer, size_t dictSize, int compressionLevel);
+
+/*! ZSTD_getCParams() :
+ * @return ZSTD_compressionParameters structure for a selected compression level and estimated srcSize.
+ * `estimatedSrcSize` value is optional, select 0 if not known */
+ZSTDLIB_STATIC_API ZSTD_compressionParameters ZSTD_getCParams(int compressionLevel, unsigned long long estimatedSrcSize, size_t dictSize);
+
+/*! ZSTD_getParams() :
+ *  same as ZSTD_getCParams(), but @return a full `ZSTD_parameters` object instead of sub-component `ZSTD_compressionParameters`.
+ *  All fields of `ZSTD_frameParameters` are set to default : contentSize=1, checksum=0, noDictID=0 */
+ZSTDLIB_STATIC_API ZSTD_parameters ZSTD_getParams(int compressionLevel, unsigned long long estimatedSrcSize, size_t dictSize);
+
+/*! ZSTD_checkCParams() :
+ *  Ensure param values remain within authorized range.
+ * @return 0 on success, or an error code (can be checked with ZSTD_isError()) */
+ZSTDLIB_STATIC_API size_t ZSTD_checkCParams(ZSTD_compressionParameters params);
+
+/*! ZSTD_adjustCParams() :
+ *  optimize params for a given `srcSize` and `dictSize`.
+ * `srcSize` can be unknown, in which case use ZSTD_CONTENTSIZE_UNKNOWN.
+ * `dictSize` must be `0` when there is no dictionary.
+ *  cPar can be invalid : all parameters will be clamped within valid range in the @return struct.
+ *  This function never fails (wide contract) */
+ZSTDLIB_STATIC_API ZSTD_compressionParameters ZSTD_adjustCParams(ZSTD_compressionParameters cPar, unsigned long long srcSize, size_t dictSize);
+
+/*! ZSTD_CCtx_setCParams() :
+ *  Set all parameters provided within @p cparams into the working @p cctx.
+ *  Note : if modifying parameters during compression (MT mode only),
+ *         note that changes to the .windowLog parameter will be ignored.
+ * @return 0 on success, or an error code (can be checked with ZSTD_isError()).
+ *         On failure, no parameters are updated.
+ */
+ZSTDLIB_STATIC_API size_t ZSTD_CCtx_setCParams(ZSTD_CCtx* cctx, ZSTD_compressionParameters cparams);
+
+/*! ZSTD_CCtx_setFParams() :
+ *  Set all parameters provided within @p fparams into the working @p cctx.
+ * @return 0 on success, or an error code (can be checked with ZSTD_isError()).
+ */
+ZSTDLIB_STATIC_API size_t ZSTD_CCtx_setFParams(ZSTD_CCtx* cctx, ZSTD_frameParameters fparams);
+
+/*! ZSTD_CCtx_setParams() :
+ *  Set all parameters provided within @p params into the working @p cctx.
+ * @return 0 on success, or an error code (can be checked with ZSTD_isError()).
+ */
+ZSTDLIB_STATIC_API size_t ZSTD_CCtx_setParams(ZSTD_CCtx* cctx, ZSTD_parameters params);
+
+/*! ZSTD_compress_advanced() :
+ *  Note : this function is now DEPRECATED.
+ *         It can be replaced by ZSTD_compress2(), in combination with ZSTD_CCtx_setParameter() and other parameter setters.
+ *  This prototype will generate compilation warnings. */
+ZSTD_DEPRECATED("use ZSTD_compress2")
+ZSTDLIB_STATIC_API
+size_t ZSTD_compress_advanced(ZSTD_CCtx* cctx,
+                              void* dst, size_t dstCapacity,
+                        const void* src, size_t srcSize,
+                        const void* dict,size_t dictSize,
+                              ZSTD_parameters params);
+
+/*! ZSTD_compress_usingCDict_advanced() :
+ *  Note : this function is now DEPRECATED.
+ *         It can be replaced by ZSTD_compress2(), in combination with ZSTD_CCtx_loadDictionary() and other parameter setters.
+ *  This prototype will generate compilation warnings. */
+ZSTD_DEPRECATED("use ZSTD_compress2 with ZSTD_CCtx_loadDictionary")
+ZSTDLIB_STATIC_API
+size_t ZSTD_compress_usingCDict_advanced(ZSTD_CCtx* cctx,
+                                              void* dst, size_t dstCapacity,
+                                        const void* src, size_t srcSize,
+                                        const ZSTD_CDict* cdict,
+                                              ZSTD_frameParameters fParams);
+
+
+/*! ZSTD_CCtx_loadDictionary_byReference() :
+ *  Same as ZSTD_CCtx_loadDictionary(), but dictionary content is referenced, instead of being copied into CCtx.
+ *  It saves some memory, but also requires that `dict` outlives its usage within `cctx` */
+ZSTDLIB_STATIC_API size_t ZSTD_CCtx_loadDictionary_byReference(ZSTD_CCtx* cctx, const void* dict, size_t dictSize);
+
+/*! ZSTD_CCtx_loadDictionary_advanced() :
+ *  Same as ZSTD_CCtx_loadDictionary(), but gives finer control over
+ *  how to load the dictionary (by copy ? by reference ?)
+ *  and how to interpret it (automatic ? force raw mode ? full mode only ?) */
+ZSTDLIB_STATIC_API size_t ZSTD_CCtx_loadDictionary_advanced(ZSTD_CCtx* cctx, const void* dict, size_t dictSize, ZSTD_dictLoadMethod_e dictLoadMethod, ZSTD_dictContentType_e dictContentType);
+
+/*! ZSTD_CCtx_refPrefix_advanced() :
+ *  Same as ZSTD_CCtx_refPrefix(), but gives finer control over
+ *  how to interpret prefix content (automatic ? force raw mode (default) ? full mode only ?) */
+ZSTDLIB_STATIC_API size_t ZSTD_CCtx_refPrefix_advanced(ZSTD_CCtx* cctx, const void* prefix, size_t prefixSize, ZSTD_dictContentType_e dictContentType);
+
+/* ===   experimental parameters   === */
+/* these parameters can be used with ZSTD_setParameter()
+ * they are not guaranteed to remain supported in the future */
+
+ /* Enables rsyncable mode,
+  * which makes compressed files more rsync friendly
+  * by adding periodic synchronization points to the compressed data.
+  * The target average block size is ZSTD_c_jobSize / 2.
+  * It's possible to modify the job size to increase or decrease
+  * the granularity of the synchronization point.
+  * Once the jobSize is smaller than the window size,
+  * it will result in compression ratio degradation.
+  * NOTE 1: rsyncable mode only works when multithreading is enabled.
+  * NOTE 2: rsyncable performs poorly in combination with long range mode,
+  * since it will decrease the effectiveness of synchronization points,
+  * though mileage may vary.
+  * NOTE 3: Rsyncable mode limits maximum compression speed to ~400 MB/s.
+  * If the selected compression level is already running significantly slower,
+  * the overall speed won't be significantly impacted.
+  */
+ #define ZSTD_c_rsyncable ZSTD_c_experimentalParam1
+
+/* Select a compression format.
+ * The value must be of type ZSTD_format_e.
+ * See ZSTD_format_e enum definition for details */
+#define ZSTD_c_format ZSTD_c_experimentalParam2
+
+/* Force back-reference distances to remain < windowSize,
+ * even when referencing into Dictionary content (default:0) */
+#define ZSTD_c_forceMaxWindow ZSTD_c_experimentalParam3
+
+/* Controls whether the contents of a CDict
+ * are used in place, or copied into the working context.
+ * Accepts values from the ZSTD_dictAttachPref_e enum.
+ * See the comments on that enum for an explanation of the feature. */
+#define ZSTD_c_forceAttachDict ZSTD_c_experimentalParam4
+
+/* Controlled with ZSTD_ParamSwitch_e enum.
+ * Default is ZSTD_ps_auto.
+ * Set to ZSTD_ps_disable to never compress literals.
+ * Set to ZSTD_ps_enable to always compress literals. (Note: uncompressed literals
+ * may still be emitted if huffman is not beneficial to use.)
+ *
+ * By default, in ZSTD_ps_auto, the library will decide at runtime whether to use
+ * literals compression based on the compression parameters - specifically,
+ * negative compression levels do not use literal compression.
+ */
+#define ZSTD_c_literalCompressionMode ZSTD_c_experimentalParam5
+
+/* User's best guess of source size.
+ * Hint is not valid when srcSizeHint == 0.
+ * There is no guarantee that hint is close to actual source size,
+ * but compression ratio may regress significantly if guess considerably underestimates */
+#define ZSTD_c_srcSizeHint ZSTD_c_experimentalParam7
+
+/* Controls whether the new and experimental "dedicated dictionary search
+ * structure" can be used. This feature is still rough around the edges, be
+ * prepared for surprising behavior!
+ *
+ * How to use it:
+ *
+ * When using a CDict, whether to use this feature or not is controlled at
+ * CDict creation, and it must be set in a CCtxParams set passed into that
+ * construction (via ZSTD_createCDict_advanced2()). A compression will then
+ * use the feature or not based on how the CDict was constructed; the value of
+ * this param, set in the CCtx, will have no effect.
+ *
+ * However, when a dictionary buffer is passed into a CCtx, such as via
+ * ZSTD_CCtx_loadDictionary(), this param can be set on the CCtx to control
+ * whether the CDict that is created internally can use the feature or not.
+ *
+ * What it does:
+ *
+ * Normally, the internal data structures of the CDict are analogous to what
+ * would be stored in a CCtx after compressing the contents of a dictionary.
+ * To an approximation, a compression using a dictionary can then use those
+ * data structures to simply continue what is effectively a streaming
+ * compression where the simulated compression of the dictionary left off.
+ * Which is to say, the search structures in the CDict are normally the same
+ * format as in the CCtx.
+ *
+ * It is possible to do better, since the CDict is not like a CCtx: the search
+ * structures are written once during CDict creation, and then are only read
+ * after that, while the search structures in the CCtx are both read and
+ * written as the compression goes along. This means we can choose a search
+ * structure for the dictionary that is read-optimized.
+ *
+ * This feature enables the use of that different structure.
+ *
+ * Note that some of the members of the ZSTD_compressionParameters struct have
+ * different semantics and constraints in the dedicated search structure. It is
+ * highly recommended that you simply set a compression level in the CCtxParams
+ * you pass into the CDict creation call, and avoid messing with the cParams
+ * directly.
+ *
+ * Effects:
+ *
+ * This will only have any effect when the selected ZSTD_strategy
+ * implementation supports this feature. Currently, that's limited to
+ * ZSTD_greedy, ZSTD_lazy, and ZSTD_lazy2.
+ *
+ * Note that this means that the CDict tables can no longer be copied into the
+ * CCtx, so the dict attachment mode ZSTD_dictForceCopy will no longer be
+ * usable. The dictionary can only be attached or reloaded.
+ *
+ * In general, you should expect compression to be faster--sometimes very much
+ * so--and CDict creation to be slightly slower. Eventually, we will probably
+ * make this mode the default.
+ */
+#define ZSTD_c_enableDedicatedDictSearch ZSTD_c_experimentalParam8
+
+/* ZSTD_c_stableInBuffer
+ * Experimental parameter.
+ * Default is 0 == disabled. Set to 1 to enable.
+ *
+ * Tells the compressor that input data presented with ZSTD_inBuffer
+ * will ALWAYS be the same between calls.
+ * Technically, the @src pointer must never be changed,
+ * and the @pos field can only be updated by zstd.
+ * However, it's possible to increase the @size field,
+ * allowing scenarios where more data can be appended after compressions starts.
+ * These conditions are checked by the compressor,
+ * and compression will fail if they are not respected.
+ * Also, data in the ZSTD_inBuffer within the range [src, src + pos)
+ * MUST not be modified during compression or it will result in data corruption.
+ *
+ * When this flag is enabled zstd won't allocate an input window buffer,
+ * because the user guarantees it can reference the ZSTD_inBuffer until
+ * the frame is complete. But, it will still allocate an output buffer
+ * large enough to fit a block (see ZSTD_c_stableOutBuffer). This will also
+ * avoid the memcpy() from the input buffer to the input window buffer.
+ *
+ * NOTE: So long as the ZSTD_inBuffer always points to valid memory, using
+ * this flag is ALWAYS memory safe, and will never access out-of-bounds
+ * memory. However, compression WILL fail if conditions are not respected.
+ *
+ * WARNING: The data in the ZSTD_inBuffer in the range [src, src + pos) MUST
+ * not be modified during compression or it will result in data corruption.
+ * This is because zstd needs to reference data in the ZSTD_inBuffer to find
+ * matches. Normally zstd maintains its own window buffer for this purpose,
+ * but passing this flag tells zstd to rely on user provided buffer instead.
+ */
+#define ZSTD_c_stableInBuffer ZSTD_c_experimentalParam9
+
+/* ZSTD_c_stableOutBuffer
+ * Experimental parameter.
+ * Default is 0 == disabled. Set to 1 to enable.
+ *
+ * Tells he compressor that the ZSTD_outBuffer will not be resized between
+ * calls. Specifically: (out.size - out.pos) will never grow. This gives the
+ * compressor the freedom to say: If the compressed data doesn't fit in the
+ * output buffer then return ZSTD_error_dstSizeTooSmall. This allows us to
+ * always decompress directly into the output buffer, instead of decompressing
+ * into an internal buffer and copying to the output buffer.
+ *
+ * When this flag is enabled zstd won't allocate an output buffer, because
+ * it can write directly to the ZSTD_outBuffer. It will still allocate the
+ * input window buffer (see ZSTD_c_stableInBuffer).
+ *
+ * Zstd will check that (out.size - out.pos) never grows and return an error
+ * if it does. While not strictly necessary, this should prevent surprises.
+ */
+#define ZSTD_c_stableOutBuffer ZSTD_c_experimentalParam10
+
+/* ZSTD_c_blockDelimiters
+ * Default is 0 == ZSTD_sf_noBlockDelimiters.
+ *
+ * For use with sequence compression API: ZSTD_compressSequences().
+ *
+ * Designates whether or not the given array of ZSTD_Sequence contains block delimiters
+ * and last literals, which are defined as sequences with offset == 0 and matchLength == 0.
+ * See the definition of ZSTD_Sequence for more specifics.
+ */
+#define ZSTD_c_blockDelimiters ZSTD_c_experimentalParam11
+
+/* ZSTD_c_validateSequences
+ * Default is 0 == disabled. Set to 1 to enable sequence validation.
+ *
+ * For use with sequence compression API: ZSTD_compressSequences*().
+ * Designates whether or not provided sequences are validated within ZSTD_compressSequences*()
+ * during function execution.
+ *
+ * When Sequence validation is disabled (default), Sequences are compressed as-is,
+ * so they must correct, otherwise it would result in a corruption error.
+ *
+ * Sequence validation adds some protection, by ensuring that all values respect boundary conditions.
+ * If a Sequence is detected invalid (see doc/zstd_compression_format.md for
+ * specifics regarding offset/matchlength requirements) then the function will bail out and
+ * return an error.
+ */
+#define ZSTD_c_validateSequences ZSTD_c_experimentalParam12
+
+/* ZSTD_c_blockSplitterLevel
+ * note: this parameter only influences the first splitter stage,
+ *       which is active before producing the sequences.
+ *       ZSTD_c_splitAfterSequences controls the next splitter stage,
+ *       which is active after sequence production.
+ *       Note that both can be combined.
+ * Allowed values are between 0 and ZSTD_BLOCKSPLITTER_LEVEL_MAX included.
+ * 0 means "auto", which will select a value depending on current ZSTD_c_strategy.
+ * 1 means no splitting.
+ * Then, values from 2 to 6 are sorted in increasing cpu load order.
+ *
+ * Note that currently the first block is never split,
+ * to ensure expansion guarantees in presence of incompressible data.
+ */
+#define ZSTD_BLOCKSPLITTER_LEVEL_MAX 6
+#define ZSTD_c_blockSplitterLevel ZSTD_c_experimentalParam20
+
+/* ZSTD_c_splitAfterSequences
+ * This is a stronger splitter algorithm,
+ * based on actual sequences previously produced by the selected parser.
+ * It's also slower, and as a consequence, mostly used for high compression levels.
+ * While the post-splitter does overlap with the pre-splitter,
+ * both can nonetheless be combined,
+ * notably with ZSTD_c_blockSplitterLevel at ZSTD_BLOCKSPLITTER_LEVEL_MAX,
+ * resulting in higher compression ratio than just one of them.
+ *
+ * Default is ZSTD_ps_auto.
+ * Set to ZSTD_ps_disable to never use block splitter.
+ * Set to ZSTD_ps_enable to always use block splitter.
+ *
+ * By default, in ZSTD_ps_auto, the library will decide at runtime whether to use
+ * block splitting based on the compression parameters.
+ */
+#define ZSTD_c_splitAfterSequences ZSTD_c_experimentalParam13
+
+/* ZSTD_c_useRowMatchFinder
+ * Controlled with ZSTD_ParamSwitch_e enum.
+ * Default is ZSTD_ps_auto.
+ * Set to ZSTD_ps_disable to never use row-based matchfinder.
+ * Set to ZSTD_ps_enable to force usage of row-based matchfinder.
+ *
+ * By default, in ZSTD_ps_auto, the library will decide at runtime whether to use
+ * the row-based matchfinder based on support for SIMD instructions and the window log.
+ * Note that this only pertains to compression strategies: greedy, lazy, and lazy2
+ */
+#define ZSTD_c_useRowMatchFinder ZSTD_c_experimentalParam14
+
+/* ZSTD_c_deterministicRefPrefix
+ * Default is 0 == disabled. Set to 1 to enable.
+ *
+ * Zstd produces different results for prefix compression when the prefix is
+ * directly adjacent to the data about to be compressed vs. when it isn't.
+ * This is because zstd detects that the two buffers are contiguous and it can
+ * use a more efficient match finding algorithm. However, this produces different
+ * results than when the two buffers are non-contiguous. This flag forces zstd
+ * to always load the prefix in non-contiguous mode, even if it happens to be
+ * adjacent to the data, to guarantee determinism.
+ *
+ * If you really care about determinism when using a dictionary or prefix,
+ * like when doing delta compression, you should select this option. It comes
+ * at a speed penalty of about ~2.5% if the dictionary and data happened to be
+ * contiguous, and is free if they weren't contiguous. We don't expect that
+ * intentionally making the dictionary and data contiguous will be worth the
+ * cost to memcpy() the data.
+ */
+#define ZSTD_c_deterministicRefPrefix ZSTD_c_experimentalParam15
+
+/* ZSTD_c_prefetchCDictTables
+ * Controlled with ZSTD_ParamSwitch_e enum. Default is ZSTD_ps_auto.
+ *
+ * In some situations, zstd uses CDict tables in-place rather than copying them
+ * into the working context. (See docs on ZSTD_dictAttachPref_e above for details).
+ * In such situations, compression speed is seriously impacted when CDict tables are
+ * "cold" (outside CPU cache). This parameter instructs zstd to prefetch CDict tables
+ * when they are used in-place.
+ *
+ * For sufficiently small inputs, the cost of the prefetch will outweigh the benefit.
+ * For sufficiently large inputs, zstd will by default memcpy() CDict tables
+ * into the working context, so there is no need to prefetch. This parameter is
+ * targeted at a middle range of input sizes, where a prefetch is cheap enough to be
+ * useful but memcpy() is too expensive. The exact range of input sizes where this
+ * makes sense is best determined by careful experimentation.
+ *
+ * Note: for this parameter, ZSTD_ps_auto is currently equivalent to ZSTD_ps_disable,
+ * but in the future zstd may conditionally enable this feature via an auto-detection
+ * heuristic for cold CDicts.
+ * Use ZSTD_ps_disable to opt out of prefetching under any circumstances.
+ */
+#define ZSTD_c_prefetchCDictTables ZSTD_c_experimentalParam16
+
+/* ZSTD_c_enableSeqProducerFallback
+ * Allowed values are 0 (disable) and 1 (enable). The default setting is 0.
+ *
+ * Controls whether zstd will fall back to an internal sequence producer if an
+ * external sequence producer is registered and returns an error code. This fallback
+ * is block-by-block: the internal sequence producer will only be called for blocks
+ * where the external sequence producer returns an error code. Fallback parsing will
+ * follow any other cParam settings, such as compression level, the same as in a
+ * normal (fully-internal) compression operation.
+ *
+ * The user is strongly encouraged to read the full Block-Level Sequence Producer API
+ * documentation (below) before setting this parameter. */
+#define ZSTD_c_enableSeqProducerFallback ZSTD_c_experimentalParam17
+
+/* ZSTD_c_maxBlockSize
+ * Allowed values are between 1KB and ZSTD_BLOCKSIZE_MAX (128KB).
+ * The default is ZSTD_BLOCKSIZE_MAX, and setting to 0 will set to the default.
+ *
+ * This parameter can be used to set an upper bound on the blocksize
+ * that overrides the default ZSTD_BLOCKSIZE_MAX. It cannot be used to set upper
+ * bounds greater than ZSTD_BLOCKSIZE_MAX or bounds lower than 1KB (will make
+ * compressBound() inaccurate). Only currently meant to be used for testing.
+ */
+#define ZSTD_c_maxBlockSize ZSTD_c_experimentalParam18
+
+/* ZSTD_c_repcodeResolution
+ * This parameter only has an effect if ZSTD_c_blockDelimiters is
+ * set to ZSTD_sf_explicitBlockDelimiters (may change in the future).
+ *
+ * This parameter affects how zstd parses external sequences,
+ * provided via the ZSTD_compressSequences*() API
+ * or from an external block-level sequence producer.
+ *
+ * If set to ZSTD_ps_enable, the library will check for repeated offsets within
+ * external sequences, even if those repcodes are not explicitly indicated in
+ * the "rep" field. Note that this is the only way to exploit repcode matches
+ * while using compressSequences*() or an external sequence producer, since zstd
+ * currently ignores the "rep" field of external sequences.
+ *
+ * If set to ZSTD_ps_disable, the library will not exploit repeated offsets in
+ * external sequences, regardless of whether the "rep" field has been set. This
+ * reduces sequence compression overhead by about 25% while sacrificing some
+ * compression ratio.
+ *
+ * The default value is ZSTD_ps_auto, for which the library will enable/disable
+ * based on compression level (currently: level<10 disables, level>=10 enables).
+ */
+#define ZSTD_c_repcodeResolution ZSTD_c_experimentalParam19
+#define ZSTD_c_searchForExternalRepcodes ZSTD_c_experimentalParam19 /* older name */
+
+
+/*! ZSTD_CCtx_getParameter() :
+ *  Get the requested compression parameter value, selected by enum ZSTD_cParameter,
+ *  and store it into int* value.
+ * @return : 0, or an error code (which can be tested with ZSTD_isError()).
+ */
+ZSTDLIB_STATIC_API size_t ZSTD_CCtx_getParameter(const ZSTD_CCtx* cctx, ZSTD_cParameter param, int* value);
+
+
+/*! ZSTD_CCtx_params :
+ *  Quick howto :
+ *  - ZSTD_createCCtxParams() : Create a ZSTD_CCtx_params structure
+ *  - ZSTD_CCtxParams_setParameter() : Push parameters one by one into
+ *                                     an existing ZSTD_CCtx_params structure.
+ *                                     This is similar to
+ *                                     ZSTD_CCtx_setParameter().
+ *  - ZSTD_CCtx_setParametersUsingCCtxParams() : Apply parameters to
+ *                                    an existing CCtx.
+ *                                    These parameters will be applied to
+ *                                    all subsequent frames.
+ *  - ZSTD_compressStream2() : Do compression using the CCtx.
+ *  - ZSTD_freeCCtxParams() : Free the memory, accept NULL pointer.
+ *
+ *  This can be used with ZSTD_estimateCCtxSize_advanced_usingCCtxParams()
+ *  for static allocation of CCtx for single-threaded compression.
+ */
+ZSTDLIB_STATIC_API ZSTD_CCtx_params* ZSTD_createCCtxParams(void);
+ZSTDLIB_STATIC_API size_t ZSTD_freeCCtxParams(ZSTD_CCtx_params* params);  /* accept NULL pointer */
+
+/*! ZSTD_CCtxParams_reset() :
+ *  Reset params to default values.
+ */
+ZSTDLIB_STATIC_API size_t ZSTD_CCtxParams_reset(ZSTD_CCtx_params* params);
+
+/*! ZSTD_CCtxParams_init() :
+ *  Initializes the compression parameters of cctxParams according to
+ *  compression level. All other parameters are reset to their default values.
+ */
+ZSTDLIB_STATIC_API size_t ZSTD_CCtxParams_init(ZSTD_CCtx_params* cctxParams, int compressionLevel);
+
+/*! ZSTD_CCtxParams_init_advanced() :
+ *  Initializes the compression and frame parameters of cctxParams according to
+ *  params. All other parameters are reset to their default values.
+ */
+ZSTDLIB_STATIC_API size_t ZSTD_CCtxParams_init_advanced(ZSTD_CCtx_params* cctxParams, ZSTD_parameters params);
+
+/*! ZSTD_CCtxParams_setParameter() : Requires v1.4.0+
+ *  Similar to ZSTD_CCtx_setParameter.
+ *  Set one compression parameter, selected by enum ZSTD_cParameter.
+ *  Parameters must be applied to a ZSTD_CCtx using
+ *  ZSTD_CCtx_setParametersUsingCCtxParams().
+ * @result : a code representing success or failure (which can be tested with
+ *           ZSTD_isError()).
+ */
+ZSTDLIB_STATIC_API size_t ZSTD_CCtxParams_setParameter(ZSTD_CCtx_params* params, ZSTD_cParameter param, int value);
+
+/*! ZSTD_CCtxParams_getParameter() :
+ * Similar to ZSTD_CCtx_getParameter.
+ * Get the requested value of one compression parameter, selected by enum ZSTD_cParameter.
+ * @result : 0, or an error code (which can be tested with ZSTD_isError()).
+ */
+ZSTDLIB_STATIC_API size_t ZSTD_CCtxParams_getParameter(const ZSTD_CCtx_params* params, ZSTD_cParameter param, int* value);
+
+/*! ZSTD_CCtx_setParametersUsingCCtxParams() :
+ *  Apply a set of ZSTD_CCtx_params to the compression context.
+ *  This can be done even after compression is started,
+ *    if nbWorkers==0, this will have no impact until a new compression is started.
+ *    if nbWorkers>=1, new parameters will be picked up at next job,
+ *       with a few restrictions (windowLog, pledgedSrcSize, nbWorkers, jobSize, and overlapLog are not updated).
+ */
+ZSTDLIB_STATIC_API size_t ZSTD_CCtx_setParametersUsingCCtxParams(
+        ZSTD_CCtx* cctx, const ZSTD_CCtx_params* params);
+
+
+/***************************************
+*  Advanced decompression functions
+***************************************/
+
+/*! ZSTD_isFrame() :
+ *  Tells if the content of `buffer` starts with a valid Frame Identifier.
+ *  Note : Frame Identifier is 4 bytes. If `size < 4`, @return will always be 0.
+ *  Note 2 : Legacy Frame Identifiers are considered valid only if Legacy Support is enabled.
+ *  Note 3 : Skippable Frame Identifiers are considered valid. */
+ZSTDLIB_STATIC_API unsigned ZSTD_isFrame(const void* buffer, size_t size);
+
+/*! ZSTD_createDDict_byReference() :
+ *  Create a digested dictionary, ready to start decompression operation without startup delay.
+ *  Dictionary content is referenced, and therefore stays in dictBuffer.
+ *  It is important that dictBuffer outlives DDict,
+ *  it must remain read accessible throughout the lifetime of DDict */
+ZSTDLIB_STATIC_API ZSTD_DDict* ZSTD_createDDict_byReference(const void* dictBuffer, size_t dictSize);
+
+/*! ZSTD_DCtx_loadDictionary_byReference() :
+ *  Same as ZSTD_DCtx_loadDictionary(),
+ *  but references `dict` content instead of copying it into `dctx`.
+ *  This saves memory if `dict` remains around.,
+ *  However, it's imperative that `dict` remains accessible (and unmodified) while being used, so it must outlive decompression. */
+ZSTDLIB_STATIC_API size_t ZSTD_DCtx_loadDictionary_byReference(ZSTD_DCtx* dctx, const void* dict, size_t dictSize);
+
+/*! ZSTD_DCtx_loadDictionary_advanced() :
+ *  Same as ZSTD_DCtx_loadDictionary(),
+ *  but gives direct control over
+ *  how to load the dictionary (by copy ? by reference ?)
+ *  and how to interpret it (automatic ? force raw mode ? full mode only ?). */
+ZSTDLIB_STATIC_API size_t ZSTD_DCtx_loadDictionary_advanced(ZSTD_DCtx* dctx, const void* dict, size_t dictSize, ZSTD_dictLoadMethod_e dictLoadMethod, ZSTD_dictContentType_e dictContentType);
+
+/*! ZSTD_DCtx_refPrefix_advanced() :
+ *  Same as ZSTD_DCtx_refPrefix(), but gives finer control over
+ *  how to interpret prefix content (automatic ? force raw mode (default) ? full mode only ?) */
+ZSTDLIB_STATIC_API size_t ZSTD_DCtx_refPrefix_advanced(ZSTD_DCtx* dctx, const void* prefix, size_t prefixSize, ZSTD_dictContentType_e dictContentType);
+
+/*! ZSTD_DCtx_setMaxWindowSize() :
+ *  Refuses allocating internal buffers for frames requiring a window size larger than provided limit.
+ *  This protects a decoder context from reserving too much memory for itself (potential attack scenario).
+ *  This parameter is only useful in streaming mode, since no internal buffer is allocated in single-pass mode.
+ *  By default, a decompression context accepts all window sizes <= (1 << ZSTD_WINDOWLOG_LIMIT_DEFAULT)
+ * @return : 0, or an error code (which can be tested using ZSTD_isError()).
+ */
+ZSTDLIB_STATIC_API size_t ZSTD_DCtx_setMaxWindowSize(ZSTD_DCtx* dctx, size_t maxWindowSize);
+
+/*! ZSTD_DCtx_getParameter() :
+ *  Get the requested decompression parameter value, selected by enum ZSTD_dParameter,
+ *  and store it into int* value.
+ * @return : 0, or an error code (which can be tested with ZSTD_isError()).
+ */
+ZSTDLIB_STATIC_API size_t ZSTD_DCtx_getParameter(ZSTD_DCtx* dctx, ZSTD_dParameter param, int* value);
+
+/* ZSTD_d_format
+ * experimental parameter,
+ * allowing selection between ZSTD_format_e input compression formats
+ */
+#define ZSTD_d_format ZSTD_d_experimentalParam1
+/* ZSTD_d_stableOutBuffer
+ * Experimental parameter.
+ * Default is 0 == disabled. Set to 1 to enable.
+ *
+ * Tells the decompressor that the ZSTD_outBuffer will ALWAYS be the same
+ * between calls, except for the modifications that zstd makes to pos (the
+ * caller must not modify pos). This is checked by the decompressor, and
+ * decompression will fail if it ever changes. Therefore the ZSTD_outBuffer
+ * MUST be large enough to fit the entire decompressed frame. This will be
+ * checked when the frame content size is known. The data in the ZSTD_outBuffer
+ * in the range [dst, dst + pos) MUST not be modified during decompression
+ * or you will get data corruption.
+ *
+ * When this flag is enabled zstd won't allocate an output buffer, because
+ * it can write directly to the ZSTD_outBuffer, but it will still allocate
+ * an input buffer large enough to fit any compressed block. This will also
+ * avoid the memcpy() from the internal output buffer to the ZSTD_outBuffer.
+ * If you need to avoid the input buffer allocation use the buffer-less
+ * streaming API.
+ *
+ * NOTE: So long as the ZSTD_outBuffer always points to valid memory, using
+ * this flag is ALWAYS memory safe, and will never access out-of-bounds
+ * memory. However, decompression WILL fail if you violate the preconditions.
+ *
+ * WARNING: The data in the ZSTD_outBuffer in the range [dst, dst + pos) MUST
+ * not be modified during decompression or you will get data corruption. This
+ * is because zstd needs to reference data in the ZSTD_outBuffer to regenerate
+ * matches. Normally zstd maintains its own buffer for this purpose, but passing
+ * this flag tells zstd to use the user provided buffer.
+ */
+#define ZSTD_d_stableOutBuffer ZSTD_d_experimentalParam2
+
+/* ZSTD_d_forceIgnoreChecksum
+ * Experimental parameter.
+ * Default is 0 == disabled. Set to 1 to enable
+ *
+ * Tells the decompressor to skip checksum validation during decompression, regardless
+ * of whether checksumming was specified during compression. This offers some
+ * slight performance benefits, and may be useful for debugging.
+ * Param has values of type ZSTD_forceIgnoreChecksum_e
+ */
+#define ZSTD_d_forceIgnoreChecksum ZSTD_d_experimentalParam3
+
+/* ZSTD_d_refMultipleDDicts
+ * Experimental parameter.
+ * Default is 0 == disabled. Set to 1 to enable
+ *
+ * If enabled and dctx is allocated on the heap, then additional memory will be allocated
+ * to store references to multiple ZSTD_DDict. That is, multiple calls of ZSTD_refDDict()
+ * using a given ZSTD_DCtx, rather than overwriting the previous DDict reference, will instead
+ * store all references. At decompression time, the appropriate dictID is selected
+ * from the set of DDicts based on the dictID in the frame.
+ *
+ * Usage is simply calling ZSTD_refDDict() on multiple dict buffers.
+ *
+ * Param has values of byte ZSTD_refMultipleDDicts_e
+ *
+ * WARNING: Enabling this parameter and calling ZSTD_DCtx_refDDict(), will trigger memory
+ * allocation for the hash table. ZSTD_freeDCtx() also frees this memory.
+ * Memory is allocated as per ZSTD_DCtx::customMem.
+ *
+ * Although this function allocates memory for the table, the user is still responsible for
+ * memory management of the underlying ZSTD_DDict* themselves.
+ */
+#define ZSTD_d_refMultipleDDicts ZSTD_d_experimentalParam4
+
+/* ZSTD_d_disableHuffmanAssembly
+ * Set to 1 to disable the Huffman assembly implementation.
+ * The default value is 0, which allows zstd to use the Huffman assembly
+ * implementation if available.
+ *
+ * This parameter can be used to disable Huffman assembly at runtime.
+ * If you want to disable it at compile time you can define the macro
+ * ZSTD_DISABLE_ASM.
+ */
+#define ZSTD_d_disableHuffmanAssembly ZSTD_d_experimentalParam5
+
+/* ZSTD_d_maxBlockSize
+ * Allowed values are between 1KB and ZSTD_BLOCKSIZE_MAX (128KB).
+ * The default is ZSTD_BLOCKSIZE_MAX, and setting to 0 will set to the default.
+ *
+ * Forces the decompressor to reject blocks whose content size is
+ * larger than the configured maxBlockSize. When maxBlockSize is
+ * larger than the windowSize, the windowSize is used instead.
+ * This saves memory on the decoder when you know all blocks are small.
+ *
+ * This option is typically used in conjunction with ZSTD_c_maxBlockSize.
+ *
+ * WARNING: This causes the decoder to reject otherwise valid frames
+ * that have block sizes larger than the configured maxBlockSize.
+ */
+#define ZSTD_d_maxBlockSize ZSTD_d_experimentalParam6
+
+
+/*! ZSTD_DCtx_setFormat() :
+ *  This function is REDUNDANT. Prefer ZSTD_DCtx_setParameter().
+ *  Instruct the decoder context about what kind of data to decode next.
+ *  This instruction is mandatory to decode data without a fully-formed header,
+ *  such ZSTD_f_zstd1_magicless for example.
+ * @return : 0, or an error code (which can be tested using ZSTD_isError()). */
+ZSTD_DEPRECATED("use ZSTD_DCtx_setParameter() instead")
+ZSTDLIB_STATIC_API
+size_t ZSTD_DCtx_setFormat(ZSTD_DCtx* dctx, ZSTD_format_e format);
+
+
+/********************************************************************
+*  Advanced streaming functions
+*  Warning : most of these functions are now redundant with the Advanced API.
+*  Once Advanced API reaches "stable" status,
+*  redundant functions will be deprecated, and then at some point removed.
+********************************************************************/
+
+typedef struct {
+    unsigned long long ingested;   /* nb input bytes read and buffered */
+    unsigned long long consumed;   /* nb input bytes actually compressed */
+    unsigned long long produced;   /* nb of compressed bytes generated and buffered */
+    unsigned long long flushed;    /* nb of compressed bytes flushed : not provided; can be tracked from caller side */
+    unsigned currentJobID;         /* MT only : latest started job nb */
+    unsigned nbActiveWorkers;      /* MT only : nb of workers actively compressing at probe time */
+} ZSTD_frameProgression;
+
+/* ZSTD_getFrameProgression() :
+ * tells how much data has been ingested (read from input)
+ * consumed (input actually compressed) and produced (output) for current frame.
+ * Note : (ingested - consumed) is amount of input data buffered internally, not yet compressed.
+ * Aggregates progression inside active worker threads.
+ */
+ZSTDLIB_STATIC_API ZSTD_frameProgression ZSTD_getFrameProgression(const ZSTD_CCtx* cctx);
+
+/*! ZSTD_toFlushNow() :
+ *  Tell how many bytes are ready to be flushed immediately.
+ *  Useful for multithreading scenarios (nbWorkers >= 1).
+ *  Probe the oldest active job, defined as oldest job not yet entirely flushed,
+ *  and check its output buffer.
+ * @return : amount of data stored in oldest job and ready to be flushed immediately.
+ *  if @return == 0, it means either :
+ *  + there is no active job (could be checked with ZSTD_frameProgression()), or
+ *  + oldest job is still actively compressing data,
+ *    but everything it has produced has also been flushed so far,
+ *    therefore flush speed is limited by production speed of oldest job
+ *    irrespective of the speed of concurrent (and newer) jobs.
+ */
+ZSTDLIB_STATIC_API size_t ZSTD_toFlushNow(ZSTD_CCtx* cctx);
+
+
+/* ********************* BLOCK-LEVEL SEQUENCE PRODUCER API *********************
+ *
+ * *** OVERVIEW ***
+ * The Block-Level Sequence Producer API allows users to provide their own custom
+ * sequence producer which libzstd invokes to process each block. The produced list
+ * of sequences (literals and matches) is then post-processed by libzstd to produce
+ * valid compressed blocks.
+ *
+ * This block-level offload API is a more granular complement of the existing
+ * frame-level offload API compressSequences() (introduced in v1.5.1). It offers
+ * an easier migration story for applications already integrated with libzstd: the
+ * user application continues to invoke the same compression functions
+ * ZSTD_compress2() or ZSTD_compressStream2() as usual, and transparently benefits
+ * from the specific advantages of the external sequence producer. For example,
+ * the sequence producer could be tuned to take advantage of known characteristics
+ * of the input, to offer better speed / ratio, or could leverage hardware
+ * acceleration not available within libzstd itself.
+ *
+ * See contrib/externalSequenceProducer for an example program employing the
+ * Block-Level Sequence Producer API.
+ *
+ * *** USAGE ***
+ * The user is responsible for implementing a function of type
+ * ZSTD_sequenceProducer_F. For each block, zstd will pass the following
+ * arguments to the user-provided function:
+ *
+ *   - sequenceProducerState: a pointer to a user-managed state for the sequence
+ *     producer.
+ *
+ *   - outSeqs, outSeqsCapacity: an output buffer for the sequence producer.
+ *     outSeqsCapacity is guaranteed >= ZSTD_sequenceBound(srcSize). The memory
+ *     backing outSeqs is managed by the CCtx.
+ *
+ *   - src, srcSize: an input buffer for the sequence producer to parse.
+ *     srcSize is guaranteed to be <= ZSTD_BLOCKSIZE_MAX.
+ *
+ *   - dict, dictSize: a history buffer, which may be empty, which the sequence
+ *     producer may reference as it parses the src buffer. Currently, zstd will
+ *     always pass dictSize == 0 into external sequence producers, but this will
+ *     change in the future.
+ *
+ *   - compressionLevel: a signed integer representing the zstd compression level
+ *     set by the user for the current operation. The sequence producer may choose
+ *     to use this information to change its compression strategy and speed/ratio
+ *     tradeoff. Note: the compression level does not reflect zstd parameters set
+ *     through the advanced API.
+ *
+ *   - windowSize: a size_t representing the maximum allowed offset for external
+ *     sequences. Note that sequence offsets are sometimes allowed to exceed the
+ *     windowSize if a dictionary is present, see doc/zstd_compression_format.md
+ *     for details.
+ *
+ * The user-provided function shall return a size_t representing the number of
+ * sequences written to outSeqs. This return value will be treated as an error
+ * code if it is greater than outSeqsCapacity. The return value must be non-zero
+ * if srcSize is non-zero. The ZSTD_SEQUENCE_PRODUCER_ERROR macro is provided
+ * for convenience, but any value greater than outSeqsCapacity will be treated as
+ * an error code.
+ *
+ * If the user-provided function does not return an error code, the sequences
+ * written to outSeqs must be a valid parse of the src buffer. Data corruption may
+ * occur if the parse is not valid. A parse is defined to be valid if the
+ * following conditions hold:
+ *   - The sum of matchLengths and literalLengths must equal srcSize.
+ *   - All sequences in the parse, except for the final sequence, must have
+ *     matchLength >= ZSTD_MINMATCH_MIN. The final sequence must have
+ *     matchLength >= ZSTD_MINMATCH_MIN or matchLength == 0.
+ *   - All offsets must respect the windowSize parameter as specified in
+ *     doc/zstd_compression_format.md.
+ *   - If the final sequence has matchLength == 0, it must also have offset == 0.
+ *
+ * zstd will only validate these conditions (and fail compression if they do not
+ * hold) if the ZSTD_c_validateSequences cParam is enabled. Note that sequence
+ * validation has a performance cost.
+ *
+ * If the user-provided function returns an error, zstd will either fall back
+ * to an internal sequence producer or fail the compression operation. The user can
+ * choose between the two behaviors by setting the ZSTD_c_enableSeqProducerFallback
+ * cParam. Fallback compression will follow any other cParam settings, such as
+ * compression level, the same as in a normal compression operation.
+ *
+ * The user shall instruct zstd to use a particular ZSTD_sequenceProducer_F
+ * function by calling
+ *         ZSTD_registerSequenceProducer(cctx,
+ *                                       sequenceProducerState,
+ *                                       sequenceProducer)
+ * This setting will persist until the next parameter reset of the CCtx.
+ *
+ * The sequenceProducerState must be initialized by the user before calling
+ * ZSTD_registerSequenceProducer(). The user is responsible for destroying the
+ * sequenceProducerState.
+ *
+ * *** LIMITATIONS ***
+ * This API is compatible with all zstd compression APIs which respect advanced parameters.
+ * However, there are three limitations:
+ *
+ * First, the ZSTD_c_enableLongDistanceMatching cParam is not currently supported.
+ * COMPRESSION WILL FAIL if it is enabled and the user tries to compress with a block-level
+ * external sequence producer.
+ *   - Note that ZSTD_c_enableLongDistanceMatching is auto-enabled by default in some
+ *     cases (see its documentation for details). Users must explicitly set
+ *     ZSTD_c_enableLongDistanceMatching to ZSTD_ps_disable in such cases if an external
+ *     sequence producer is registered.
+ *   - As of this writing, ZSTD_c_enableLongDistanceMatching is disabled by default
+ *     whenever ZSTD_c_windowLog < 128MB, but that's subject to change. Users should
+ *     check the docs on ZSTD_c_enableLongDistanceMatching whenever the Block-Level Sequence
+ *     Producer API is used in conjunction with advanced settings (like ZSTD_c_windowLog).
+ *
+ * Second, history buffers are not currently supported. Concretely, zstd will always pass
+ * dictSize == 0 to the external sequence producer (for now). This has two implications:
+ *   - Dictionaries are not currently supported. Compression will *not* fail if the user
+ *     references a dictionary, but the dictionary won't have any effect.
+ *   - Stream history is not currently supported. All advanced compression APIs, including
+ *     streaming APIs, work with external sequence producers, but each block is treated as
+ *     an independent chunk without history from previous blocks.
+ *
+ * Third, multi-threading within a single compression is not currently supported. In other words,
+ * COMPRESSION WILL FAIL if ZSTD_c_nbWorkers > 0 and an external sequence producer is registered.
+ * Multi-threading across compressions is fine: simply create one CCtx per thread.
+ *
+ * Long-term, we plan to overcome all three limitations. There is no technical blocker to
+ * overcoming them. It is purely a question of engineering effort.
+ */
+
+#define ZSTD_SEQUENCE_PRODUCER_ERROR ((size_t)(-1))
+
+typedef size_t (*ZSTD_sequenceProducer_F) (
+  void* sequenceProducerState,
+  ZSTD_Sequence* outSeqs, size_t outSeqsCapacity,
+  const void* src, size_t srcSize,
+  const void* dict, size_t dictSize,
+  int compressionLevel,
+  size_t windowSize
+);
+
+/*! ZSTD_registerSequenceProducer() :
+ * Instruct zstd to use a block-level external sequence producer function.
+ *
+ * The sequenceProducerState must be initialized by the caller, and the caller is
+ * responsible for managing its lifetime. This parameter is sticky across
+ * compressions. It will remain set until the user explicitly resets compression
+ * parameters.
+ *
+ * Sequence producer registration is considered to be an "advanced parameter",
+ * part of the "advanced API". This means it will only have an effect on compression
+ * APIs which respect advanced parameters, such as compress2() and compressStream2().
+ * Older compression APIs such as compressCCtx(), which predate the introduction of
+ * "advanced parameters", will ignore any external sequence producer setting.
+ *
+ * The sequence producer can be "cleared" by registering a NULL function pointer. This
+ * removes all limitations described above in the "LIMITATIONS" section of the API docs.
+ *
+ * The user is strongly encouraged to read the full API documentation (above) before
+ * calling this function. */
+ZSTDLIB_STATIC_API void
+ZSTD_registerSequenceProducer(
+  ZSTD_CCtx* cctx,
+  void* sequenceProducerState,
+  ZSTD_sequenceProducer_F sequenceProducer
+);
+
+/*! ZSTD_CCtxParams_registerSequenceProducer() :
+ * Same as ZSTD_registerSequenceProducer(), but operates on ZSTD_CCtx_params.
+ * This is used for accurate size estimation with ZSTD_estimateCCtxSize_usingCCtxParams(),
+ * which is needed when creating a ZSTD_CCtx with ZSTD_initStaticCCtx().
+ *
+ * If you are using the external sequence producer API in a scenario where ZSTD_initStaticCCtx()
+ * is required, then this function is for you. Otherwise, you probably don't need it.
+ *
+ * See tests/zstreamtest.c for example usage. */
+ZSTDLIB_STATIC_API void
+ZSTD_CCtxParams_registerSequenceProducer(
+  ZSTD_CCtx_params* params,
+  void* sequenceProducerState,
+  ZSTD_sequenceProducer_F sequenceProducer
+);
+
+
+/*********************************************************************
+*  Buffer-less and synchronous inner streaming functions (DEPRECATED)
+*
+*  This API is deprecated, and will be removed in a future version.
+*  It allows streaming (de)compression with user allocated buffers.
+*  However, it is hard to use, and not as well tested as the rest of
+*  our API.
+*
+*  Please use the normal streaming API instead: ZSTD_compressStream2,
+*  and ZSTD_decompressStream.
+*  If there is functionality that you need, but it doesn't provide,
+*  please open an issue on our GitHub.
+********************************************************************* */
+
+/**
+  Buffer-less streaming compression (synchronous mode)
+
+  A ZSTD_CCtx object is required to track streaming operations.
+  Use ZSTD_createCCtx() / ZSTD_freeCCtx() to manage resource.
+  ZSTD_CCtx object can be reused multiple times within successive compression operations.
+
+  Start by initializing a context.
+  Use ZSTD_compressBegin(), or ZSTD_compressBegin_usingDict() for dictionary compression.
+
+  Then, consume your input using ZSTD_compressContinue().
+  There are some important considerations to keep in mind when using this advanced function :
+  - ZSTD_compressContinue() has no internal buffer. It uses externally provided buffers only.
+  - Interface is synchronous : input is consumed entirely and produces 1+ compressed blocks.
+  - Caller must ensure there is enough space in `dst` to store compressed data under worst case scenario.
+    Worst case evaluation is provided by ZSTD_compressBound().
+    ZSTD_compressContinue() doesn't guarantee recover after a failed compression.
+  - ZSTD_compressContinue() presumes prior input ***is still accessible and unmodified*** (up to maximum distance size, see WindowLog).
+    It remembers all previous contiguous blocks, plus one separated memory segment (which can itself consists of multiple contiguous blocks)
+  - ZSTD_compressContinue() detects that prior input has been overwritten when `src` buffer overlaps.
+    In which case, it will "discard" the relevant memory section from its history.
+
+  Finish a frame with ZSTD_compressEnd(), which will write the last block(s) and optional checksum.
+  It's possible to use srcSize==0, in which case, it will write a final empty block to end the frame.
+  Without last block mark, frames are considered unfinished (hence corrupted) by compliant decoders.
+
+  `ZSTD_CCtx` object can be reused (ZSTD_compressBegin()) to compress again.
+*/
+
+/*=====   Buffer-less streaming compression functions  =====*/
+ZSTD_DEPRECATED("The buffer-less API is deprecated in favor of the normal streaming API. See docs.")
+ZSTDLIB_STATIC_API size_t ZSTD_compressBegin(ZSTD_CCtx* cctx, int compressionLevel);
+ZSTD_DEPRECATED("The buffer-less API is deprecated in favor of the normal streaming API. See docs.")
+ZSTDLIB_STATIC_API size_t ZSTD_compressBegin_usingDict(ZSTD_CCtx* cctx, const void* dict, size_t dictSize, int compressionLevel);
+ZSTD_DEPRECATED("The buffer-less API is deprecated in favor of the normal streaming API. See docs.")
+ZSTDLIB_STATIC_API size_t ZSTD_compressBegin_usingCDict(ZSTD_CCtx* cctx, const ZSTD_CDict* cdict); /**< note: fails if cdict==NULL */
+
+ZSTD_DEPRECATED("This function will likely be removed in a future release. It is misleading and has very limited utility.")
+ZSTDLIB_STATIC_API
+size_t ZSTD_copyCCtx(ZSTD_CCtx* cctx, const ZSTD_CCtx* preparedCCtx, unsigned long long pledgedSrcSize); /**<  note: if pledgedSrcSize is not known, use ZSTD_CONTENTSIZE_UNKNOWN */
+
+ZSTD_DEPRECATED("The buffer-less API is deprecated in favor of the normal streaming API. See docs.")
+ZSTDLIB_STATIC_API size_t ZSTD_compressContinue(ZSTD_CCtx* cctx, void* dst, size_t dstCapacity, const void* src, size_t srcSize);
+ZSTD_DEPRECATED("The buffer-less API is deprecated in favor of the normal streaming API. See docs.")
+ZSTDLIB_STATIC_API size_t ZSTD_compressEnd(ZSTD_CCtx* cctx, void* dst, size_t dstCapacity, const void* src, size_t srcSize);
+
+/* The ZSTD_compressBegin_advanced() and ZSTD_compressBegin_usingCDict_advanced() are now DEPRECATED and will generate a compiler warning */
+ZSTD_DEPRECATED("use advanced API to access custom parameters")
+ZSTDLIB_STATIC_API
+size_t ZSTD_compressBegin_advanced(ZSTD_CCtx* cctx, const void* dict, size_t dictSize, ZSTD_parameters params, unsigned long long pledgedSrcSize); /**< pledgedSrcSize : If srcSize is not known at init time, use ZSTD_CONTENTSIZE_UNKNOWN */
+ZSTD_DEPRECATED("use advanced API to access custom parameters")
+ZSTDLIB_STATIC_API
+size_t ZSTD_compressBegin_usingCDict_advanced(ZSTD_CCtx* const cctx, const ZSTD_CDict* const cdict, ZSTD_frameParameters const fParams, unsigned long long const pledgedSrcSize);   /* compression parameters are already set within cdict. pledgedSrcSize must be correct. If srcSize is not known, use macro ZSTD_CONTENTSIZE_UNKNOWN */
+/**
+  Buffer-less streaming decompression (synchronous mode)
+
+  A ZSTD_DCtx object is required to track streaming operations.
+  Use ZSTD_createDCtx() / ZSTD_freeDCtx() to manage it.
+  A ZSTD_DCtx object can be reused multiple times.
+
+  First typical operation is to retrieve frame parameters, using ZSTD_getFrameHeader().
+  Frame header is extracted from the beginning of compressed frame, so providing only the frame's beginning is enough.
+  Data fragment must be large enough to ensure successful decoding.
+ `ZSTD_frameHeaderSize_max` bytes is guaranteed to always be large enough.
+  result  : 0 : successful decoding, the `ZSTD_frameHeader` structure is correctly filled.
+           >0 : `srcSize` is too small, please provide at least result bytes on next attempt.
+           errorCode, which can be tested using ZSTD_isError().
+
+  It fills a ZSTD_FrameHeader structure with important information to correctly decode the frame,
+  such as the dictionary ID, content size, or maximum back-reference distance (`windowSize`).
+  Note that these values could be wrong, either because of data corruption, or because a 3rd party deliberately spoofs false information.
+  As a consequence, check that values remain within valid application range.
+  For example, do not allocate memory blindly, check that `windowSize` is within expectation.
+  Each application can set its own limits, depending on local restrictions.
+  For extended interoperability, it is recommended to support `windowSize` of at least 8 MB.
+
+  ZSTD_decompressContinue() needs previous data blocks during decompression, up to `windowSize` bytes.
+  ZSTD_decompressContinue() is very sensitive to contiguity,
+  if 2 blocks don't follow each other, make sure that either the compressor breaks contiguity at the same place,
+  or that previous contiguous segment is large enough to properly handle maximum back-reference distance.
+  There are multiple ways to guarantee this condition.
+
+  The most memory efficient way is to use a round buffer of sufficient size.
+  Sufficient size is determined by invoking ZSTD_decodingBufferSize_min(),
+  which can return an error code if required value is too large for current system (in 32-bits mode).
+  In a round buffer methodology, ZSTD_decompressContinue() decompresses each block next to previous one,
+  up to the moment there is not enough room left in the buffer to guarantee decoding another full block,
+  which maximum size is provided in `ZSTD_frameHeader` structure, field `blockSizeMax`.
+  At which point, decoding can resume from the beginning of the buffer.
+  Note that already decoded data stored in the buffer should be flushed before being overwritten.
+
+  There are alternatives possible, for example using two or more buffers of size `windowSize` each, though they consume more memory.
+
+  Finally, if you control the compression process, you can also ignore all buffer size rules,
+  as long as the encoder and decoder progress in "lock-step",
+  aka use exactly the same buffer sizes, break contiguity at the same place, etc.
+
+  Once buffers are setup, start decompression, with ZSTD_decompressBegin().
+  If decompression requires a dictionary, use ZSTD_decompressBegin_usingDict() or ZSTD_decompressBegin_usingDDict().
+
+  Then use ZSTD_nextSrcSizeToDecompress() and ZSTD_decompressContinue() alternatively.
+  ZSTD_nextSrcSizeToDecompress() tells how many bytes to provide as 'srcSize' to ZSTD_decompressContinue().
+  ZSTD_decompressContinue() requires this _exact_ amount of bytes, or it will fail.
+
+  result of ZSTD_decompressContinue() is the number of bytes regenerated within 'dst' (necessarily <= dstCapacity).
+  It can be zero : it just means ZSTD_decompressContinue() has decoded some metadata item.
+  It can also be an error code, which can be tested with ZSTD_isError().
+
+  A frame is fully decoded when ZSTD_nextSrcSizeToDecompress() returns zero.
+  Context can then be reset to start a new decompression.
+
+  Note : it's possible to know if next input to present is a header or a block, using ZSTD_nextInputType().
+  This information is not required to properly decode a frame.
+
+  == Special case : skippable frames ==
+
+  Skippable frames allow integration of user-defined data into a flow of concatenated frames.
+  Skippable frames will be ignored (skipped) by decompressor.
+  The format of skippable frames is as follows :
+  a) Skippable frame ID - 4 Bytes, Little endian format, any value from 0x184D2A50 to 0x184D2A5F
+  b) Frame Size - 4 Bytes, Little endian format, unsigned 32-bits
+  c) Frame Content - any content (User Data) of length equal to Frame Size
+  For skippable frames ZSTD_getFrameHeader() returns zfhPtr->frameType==ZSTD_skippableFrame.
+  For skippable frames ZSTD_decompressContinue() always returns 0 : it only skips the content.
+*/
+
+/*=====   Buffer-less streaming decompression functions  =====*/
+
+ZSTDLIB_STATIC_API size_t ZSTD_decodingBufferSize_min(unsigned long long windowSize, unsigned long long frameContentSize);  /**< when frame content size is not known, pass in frameContentSize == ZSTD_CONTENTSIZE_UNKNOWN */
+
+ZSTDLIB_STATIC_API size_t ZSTD_decompressBegin(ZSTD_DCtx* dctx);
+ZSTDLIB_STATIC_API size_t ZSTD_decompressBegin_usingDict(ZSTD_DCtx* dctx, const void* dict, size_t dictSize);
+ZSTDLIB_STATIC_API size_t ZSTD_decompressBegin_usingDDict(ZSTD_DCtx* dctx, const ZSTD_DDict* ddict);
+
+/* misc */
+ZSTD_DEPRECATED("This function will likely be removed in the next minor release. It is misleading and has very limited utility.")
+ZSTDLIB_STATIC_API void   ZSTD_copyDCtx(ZSTD_DCtx* dctx, const ZSTD_DCtx* preparedDCtx);
+typedef enum { ZSTDnit_frameHeader, ZSTDnit_blockHeader, ZSTDnit_block, ZSTDnit_lastBlock, ZSTDnit_checksum, ZSTDnit_skippableFrame } ZSTD_nextInputType_e;
+ZSTDLIB_STATIC_API ZSTD_nextInputType_e ZSTD_nextInputType(ZSTD_DCtx* dctx);
+
+
+
+
+/* ========================================= */
+/**       Block level API (DEPRECATED)       */
+/* ========================================= */
+
+/*!
+
+    This API is deprecated in favor of the regular compression API.
+    You can get the frame header down to 2 bytes by setting:
+      - ZSTD_c_format = ZSTD_f_zstd1_magicless
+      - ZSTD_c_contentSizeFlag = 0
+      - ZSTD_c_checksumFlag = 0
+      - ZSTD_c_dictIDFlag = 0
+
+    This API is not as well tested as our normal API, so we recommend not using it.
+    We will be removing it in a future version. If the normal API doesn't provide
+    the functionality you need, please open a GitHub issue.
+
+    Block functions produce and decode raw zstd blocks, without frame metadata.
+    Frame metadata cost is typically ~12 bytes, which can be non-negligible for very small blocks (< 100 bytes).
+    But users will have to take in charge needed metadata to regenerate data, such as compressed and content sizes.
+
+    A few rules to respect :
+    - Compressing and decompressing require a context structure
+      + Use ZSTD_createCCtx() and ZSTD_createDCtx()
+    - It is necessary to init context before starting
+      + compression : any ZSTD_compressBegin*() variant, including with dictionary
+      + decompression : any ZSTD_decompressBegin*() variant, including with dictionary
+    - Block size is limited, it must be <= ZSTD_getBlockSize() <= ZSTD_BLOCKSIZE_MAX == 128 KB
+      + If input is larger than a block size, it's necessary to split input data into multiple blocks
+      + For inputs larger than a single block, consider using regular ZSTD_compress() instead.
+        Frame metadata is not that costly, and quickly becomes negligible as source size grows larger than a block.
+    - When a block is considered not compressible enough, ZSTD_compressBlock() result will be 0 (zero) !
+      ===> In which case, nothing is produced into `dst` !
+      + User __must__ test for such outcome and deal directly with uncompressed data
+      + A block cannot be declared incompressible if ZSTD_compressBlock() return value was != 0.
+        Doing so would mess up with statistics history, leading to potential data corruption.
+      + ZSTD_decompressBlock() _doesn't accept uncompressed data as input_ !!
+      + In case of multiple successive blocks, should some of them be uncompressed,
+        decoder must be informed of their existence in order to follow proper history.
+        Use ZSTD_insertBlock() for such a case.
+*/
+
+/*=====   Raw zstd block functions  =====*/
+ZSTD_DEPRECATED("The block API is deprecated in favor of the normal compression API. See docs.")
+ZSTDLIB_STATIC_API size_t ZSTD_getBlockSize   (const ZSTD_CCtx* cctx);
+ZSTD_DEPRECATED("The block API is deprecated in favor of the normal compression API. See docs.")
+ZSTDLIB_STATIC_API size_t ZSTD_compressBlock  (ZSTD_CCtx* cctx, void* dst, size_t dstCapacity, const void* src, size_t srcSize);
+ZSTD_DEPRECATED("The block API is deprecated in favor of the normal compression API. See docs.")
+ZSTDLIB_STATIC_API size_t ZSTD_insertBlock    (ZSTD_DCtx* dctx, const void* blockStart, size_t blockSize);  /**< insert uncompressed block into `dctx` history. Useful for multi-blocks decompression. */
+
+#if defined (__cplusplus)
+}
+#endif
+
+#endif   /* ZSTD_H_ZSTD_STATIC_LINKING_ONLY */
diff --git a/src/commonlib/bsd/zstd/zstd_errors.h b/src/commonlib/bsd/zstd/zstd_errors.h
new file mode 100644
index 0000000000..658c9ef4bd
--- /dev/null
+++ b/src/commonlib/bsd/zstd/zstd_errors.h
@@ -0,0 +1,109 @@
+/* SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0-only */
+
+/*
+ * Copyright (c) Meta Platforms, Inc. and affiliates.
+ * All rights reserved.
+ *
+ * This source code is licensed under both the BSD-style license (found in the
+ * LICENSE file in the root directory of this source tree) and the GPLv2 (found
+ * in the COPYING file in the root directory of this source tree).
+ * You may select, at your option, one of the above-listed licenses.
+ */
+
+#ifndef ZSTD_ERRORS_H_398273423
+#define ZSTD_ERRORS_H_398273423
+
+#if defined (__cplusplus)
+extern "C" {
+#endif
+
+/* =====   ZSTDERRORLIB_API : control library symbols visibility   ===== */
+#ifndef ZSTDERRORLIB_VISIBLE
+   /* Backwards compatibility with old macro name */
+#  ifdef ZSTDERRORLIB_VISIBILITY
+#    define ZSTDERRORLIB_VISIBLE ZSTDERRORLIB_VISIBILITY
+#  elif defined(__GNUC__) && (__GNUC__ >= 4) && !defined(__MINGW32__)
+#    define ZSTDERRORLIB_VISIBLE __attribute__ ((visibility ("default")))
+#  else
+#    define ZSTDERRORLIB_VISIBLE
+#  endif
+#endif
+
+#ifndef ZSTDERRORLIB_HIDDEN
+#  if defined(__GNUC__) && (__GNUC__ >= 4) && !defined(__MINGW32__)
+#    define ZSTDERRORLIB_HIDDEN __attribute__ ((visibility ("hidden")))
+#  else
+#    define ZSTDERRORLIB_HIDDEN
+#  endif
+#endif
+
+#if defined(ZSTD_DLL_EXPORT) && (ZSTD_DLL_EXPORT==1)
+#  define ZSTDERRORLIB_API __declspec(dllexport) ZSTDERRORLIB_VISIBLE
+#elif defined(ZSTD_DLL_IMPORT) && (ZSTD_DLL_IMPORT==1)
+#  define ZSTDERRORLIB_API __declspec(dllimport) ZSTDERRORLIB_VISIBLE /* It isn't required but allows to generate better code, saving a function pointer load from the IAT and an indirect jump.*/
+#else
+#  define ZSTDERRORLIB_API ZSTDERRORLIB_VISIBLE
+#endif
+
+/*-*********************************************
+ *  Error codes list
+ *-*********************************************
+ *  Error codes _values_ are pinned down since v1.3.1 only.
+ *  Therefore, don't rely on values if you may link to any version < v1.3.1.
+ *
+ *  Only values < 100 are considered stable.
+ *
+ *  note 1 : this API shall be used with static linking only.
+ *           dynamic linking is not yet officially supported.
+ *  note 2 : Prefer relying on the enum than on its value whenever possible
+ *           This is the only supported way to use the error list < v1.3.1
+ *  note 3 : ZSTD_isError() is always correct, whatever the library version.
+ **********************************************/
+typedef enum {
+  ZSTD_error_no_error = 0,
+  ZSTD_error_GENERIC  = 1,
+  ZSTD_error_prefix_unknown                = 10,
+  ZSTD_error_version_unsupported           = 12,
+  ZSTD_error_frameParameter_unsupported    = 14,
+  ZSTD_error_frameParameter_windowTooLarge = 16,
+  ZSTD_error_corruption_detected = 20,
+  ZSTD_error_checksum_wrong      = 22,
+  ZSTD_error_literals_headerWrong = 24,
+  ZSTD_error_dictionary_corrupted      = 30,
+  ZSTD_error_dictionary_wrong          = 32,
+  ZSTD_error_dictionaryCreation_failed = 34,
+  ZSTD_error_parameter_unsupported   = 40,
+  ZSTD_error_parameter_combination_unsupported = 41,
+  ZSTD_error_parameter_outOfBound    = 42,
+  ZSTD_error_tableLog_tooLarge       = 44,
+  ZSTD_error_maxSymbolValue_tooLarge = 46,
+  ZSTD_error_maxSymbolValue_tooSmall = 48,
+  ZSTD_error_cannotProduce_uncompressedBlock = 49,
+  ZSTD_error_stabilityCondition_notRespected = 50,
+  ZSTD_error_stage_wrong       = 60,
+  ZSTD_error_init_missing      = 62,
+  ZSTD_error_memory_allocation = 64,
+  ZSTD_error_workSpace_tooSmall= 66,
+  ZSTD_error_dstSize_tooSmall = 70,
+  ZSTD_error_srcSize_wrong    = 72,
+  ZSTD_error_dstBuffer_null   = 74,
+  ZSTD_error_noForwardProgress_destFull = 80,
+  ZSTD_error_noForwardProgress_inputEmpty = 82,
+  /* following error codes are __NOT STABLE__, they can be removed or changed in future versions */
+  ZSTD_error_frameIndex_tooLarge = 100,
+  ZSTD_error_seekableIO          = 102,
+  ZSTD_error_dstBuffer_wrong     = 104,
+  ZSTD_error_srcBuffer_wrong     = 105,
+  ZSTD_error_sequenceProducer_failed = 106,
+  ZSTD_error_externalSequences_invalid = 107,
+  ZSTD_error_maxCode = 120  /* never EVER use this value directly, it can change in future versions! Use ZSTD_isError() instead */
+} ZSTD_ErrorCode;
+
+ZSTDERRORLIB_API const char* ZSTD_getErrorString(ZSTD_ErrorCode code);   /**< Same as ZSTD_getErrorName, but using a `ZSTD_ErrorCode` enum argument */
+
+
+#if defined (__cplusplus)
+}
+#endif
+
+#endif /* ZSTD_ERRORS_H_398273423 */
diff --git a/util/cbfstool/Makefile.mk b/util/cbfstool/Makefile.mk
index 8577874044..d3f07f9777 100644
--- a/util/cbfstool/Makefile.mk
+++ b/util/cbfstool/Makefile.mk
@@ -12,6 +12,34 @@ compressionobj += lzma.o
 compressionobj += LzFind.o
 compressionobj += LzmaDec.o
 compressionobj += LzmaEnc.o
+# ZSTD
+# common
+compressionobj += debug.o
+compressionobj += entropy_common.o
+compressionobj += error_private.o
+compressionobj += fse_decompress.o
+compressionobj += zstd_common.o
+# compress
+compressionobj += fse_compress.o
+compressionobj += hist.o
+compressionobj += huf_compress.o
+compressionobj += zstd_compress.o
+compressionobj += zstd_compress_literals.o
+compressionobj += zstd_compress_sequences.o
+compressionobj += zstd_compress_superblock.o
+compressionobj += zstd_double_fast.o
+compressionobj += zstd_fast.o
+compressionobj += zstd_lazy.o
+compressionobj += zstd_ldm.o
+compressionobj += zstd_preSplit.o
+compressionobj += zstd_opt.o
+# xxhash.o Already included for LZ4
+# decompress
+compressionobj += huf_decompress.o
+compressionobj += zstd_ddict.o
+compressionobj += zstd_decompress_block.o
+compressionobj += zstd_decompress.o
+#compressionobj += huf_decomppress_amd64.o
 
 cbfsobj :=
 cbfsobj += cbfstool.o
@@ -132,6 +160,7 @@ TOOLCPPFLAGS += -I$(VBOOT_SOURCE)/host/lib/include
 # have right now.
 TOOLCPPFLAGS += -I$(top)/src
 TOOLCPPFLAGS += -I$(top)/src/vendorcode/intel/edk2/uefi_2.4/MdePkg/Include
+TOOLCPPFLAGS += -I$(top)/src/commonlib/bsd/zstd/
 
 TOOLLDFLAGS ?=
 
@@ -147,6 +176,7 @@ TOOLCFLAGS+=-std=c11
 endif
 
 LZ4CFLAGS ?= -Wno-strict-prototypes
+ZSTDCPPFLAGS ?= -DZSTD_DISABLE_ASM=1
 
 VBOOT_HOSTLIB = $(VBOOT_HOST_BUILD)/libvboot_host.a
 
@@ -189,6 +219,10 @@ $(objutil)/cbfstool/%.o: $(top)/src/commonlib/bsd/%.c
 	printf "    HOSTCC     $(subst $(objutil)/,,$(@))\n"
 	$(HOSTCC) $(TOOLCPPFLAGS) $(TOOLCFLAGS) $(HOSTCFLAGS) -c -o $@ $<
 
+$(objutil)/cbfstool/%.o: $(top)/src/commonlib/bsd/zstd/*/%.c
+	printf "    HOSTCC     $(subst $(objutil)/,,$(@))\n"
+	$(HOSTCC) $(TOOLCPPFLAGS) $(TOOLCFLAGS) $(HOSTCFLAGS) $(ZSTDCPPFLAGS) -c -o $@ $<
+
 $(objutil)/cbfstool/%.o: $(top)/util/cbfstool/lz4/lib/%.c
 	printf "    HOSTCC     $(subst $(objutil)/,,$(@))\n"
 	$(HOSTCC) $(TOOLCPPFLAGS) $(TOOLCFLAGS) $(HOSTCFLAGS) $(LZ4CFLAGS) -c -o $@ $<
diff --git a/util/cbfstool/cbfs.h b/util/cbfstool/cbfs.h
index 3336e08930..cb903b1ba3 100644
--- a/util/cbfstool/cbfs.h
+++ b/util/cbfstool/cbfs.h
@@ -25,6 +25,7 @@ static const struct typedesc_t types_cbfs_compression[] = {
 	{CBFS_COMPRESS_NONE, "none"},
 	{CBFS_COMPRESS_LZMA, "LZMA"},
 	{CBFS_COMPRESS_LZ4, "LZ4"},
+	{CBFS_COMPRESS_ZSTD, "ZSTD"},
 	{0, NULL},
 };
 
diff --git a/util/cbfstool/compress.c b/util/cbfstool/compress.c
index 96df1a7499..d2cc5dd6b2 100644
--- a/util/cbfstool/compress.c
+++ b/util/cbfstool/compress.c
@@ -6,9 +6,11 @@
 #include <stdlib.h>
 #include "common.h"
 #include "lz4/lib/lz4frame.h"
+#include <zstd.h>
 #include <commonlib/bsd/compression.h>
 
-static int lz4_compress(char *in, int in_len, char *out, int *out_len)
+static int
+lz4_compress(char *in, int in_len, char *out, int *out_len)
 {
 	LZ4F_preferences_t prefs = {
 		.compressionLevel = 20,
@@ -53,6 +55,52 @@ static int lzma_decompress(char *in, int in_len, char *out, unused int out_len,
 {
 	return do_lzma_uncompress(out, out_len, in, in_len, actual_size);
 }
+
+static int zstd_compress(char *in, int in_len, char *out, int *out_len)
+{
+	size_t worst_size = ZSTD_compressBound(in_len);
+	size_t ret;
+
+	void *bounce = malloc(worst_size);
+	if (!bounce)
+		return -1;
+	ret = ZSTD_compress(bounce, worst_size, in, in_len, ZSTD_maxCLevel());
+	if (ZSTD_isError(ret)) {
+		ERROR("ZSTD_compress (v%s) returned %zu (%s)\n",
+		      ZSTD_versionString(), ret, ZSTD_getErrorName(ret));
+		free(bounce);
+		return -2;
+	}
+	if (ret >= (size_t)in_len) {
+		free(bounce);
+		return -3;
+	}
+	*out_len = (int)ret;
+
+	memcpy(out, bounce, *out_len);
+	free(bounce);
+	return 0;
+}
+
+static int zstd_decompress(char *in, int in_len, char *out, int out_len,
+			   size_t *actual_size)
+{
+	ZSTD_DCtx* dctx = ZSTD_createDCtx();
+	size_t ret = ZSTD_decompressDCtx(dctx, out, out_len, in, in_len);
+	ZSTD_freeDCtx(dctx);
+
+	if (ret == 0)
+		return -1;
+	if (ZSTD_isError(ret)) {
+		ERROR("ZSTD_decompress (v%s) returned %zu (%s)\n",
+		      ZSTD_versionString(), ret, ZSTD_getErrorName(ret));
+		return -2;
+	}
+	if (actual_size != NULL)
+		*actual_size = ret;
+	return 0;
+}
+
 static int none_compress(char *in, int in_len, char *out, int *out_len)
 {
 	memcpy(out, in, in_len);
@@ -82,6 +130,9 @@ comp_func_ptr compression_function(enum cbfs_compression algo)
 	case CBFS_COMPRESS_LZ4:
 		compress = lz4_compress;
 		break;
+	case CBFS_COMPRESS_ZSTD:
+		compress = zstd_compress;
+		break;
 	default:
 		ERROR("Unknown compression algorithm %d!\n", algo);
 		return NULL;
@@ -102,6 +153,9 @@ decomp_func_ptr decompression_function(enum cbfs_compression algo)
 	case CBFS_COMPRESS_LZ4:
 		decompress = lz4_decompress;
 		break;
+	case CBFS_COMPRESS_ZSTD:
+		decompress = zstd_decompress;
+		break;
 	default:
 		ERROR("Unknown compression algorithm %d!\n", algo);
 		return NULL;

From 4ca5e9c8c6406e4e175896cbf4947c3ea3d52811 Mon Sep 17 00:00:00 2001
From: Patrick Rudolph <patrick.rudolph@9elements.com>
Date: Sat, 22 Nov 2025 17:08:13 +0100
Subject: [PATCH 2875/3886] rules.h: Add ENV_RAMSTAGE_LOADER

Define ENV_RAMSTAGE_LOADER in rules.h similar to ENV_PAYLOAD_LOADER
to simplify the current code and avoid code duplication when adding
zstd support.

Change-Id: I8c049c640b11c6f0b51e37dd2c368bb786ca9b0f
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90153
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
---
 src/include/rules.h |  8 ++++++++
 src/lib/cbfs.c      | 14 +++-----------
 2 files changed, 11 insertions(+), 11 deletions(-)

diff --git a/src/include/rules.h b/src/include/rules.h
index 673138bfe6..053cd6bc09 100644
--- a/src/include/rules.h
+++ b/src/include/rules.h
@@ -267,6 +267,14 @@
 #define ENV_PAYLOAD_LOADER ENV_RAMSTAGE
 #endif
 
+#if CONFIG(POSTCAR_STAGE)
+#define ENV_RAMSTAGE_LOADER ENV_POSTCAR
+#elif CONFIG(SEPARATE_ROMSTAGE)
+#define ENV_RAMSTAGE_LOADER ENV_SEPARATE_ROMSTAGE
+#else
+#define ENV_RAMSTAGE_LOADER ENV_BOOTBLOCK
+#endif
+
 #define ENV_ROMSTAGE_OR_BEFORE \
 	(ENV_DECOMPRESSOR || ENV_BOOTBLOCK || ENV_SEPARATE_ROMSTAGE || \
 	(ENV_SEPARATE_VERSTAGE && !CONFIG(VBOOT_STARTS_IN_ROMSTAGE)))
diff --git a/src/lib/cbfs.c b/src/lib/cbfs.c
index 0c47359260..4ec65a864c 100644
--- a/src/lib/cbfs.c
+++ b/src/lib/cbfs.c
@@ -150,17 +150,9 @@ static inline bool cbfs_lzma_enabled(void)
 	/* Payload loader (ramstage) always needs LZMA. */
 	if (ENV_PAYLOAD_LOADER)
 		return true;
-	/* Only other use of LZMA is ramstage compression. */
-	if (!CONFIG(COMPRESS_RAMSTAGE_LZMA))
-		return false;
-	/* If there is a postcar, it loads the ramstage. */
-	if (CONFIG(POSTCAR_STAGE))
-		return ENV_POSTCAR;
-	/* If there is no postcar but a separate romstage, it loads the ramstage. */
-	if (CONFIG(SEPARATE_ROMSTAGE))
-		return ENV_SEPARATE_ROMSTAGE;
-	/* Otherwise, the combined bootblock+romstage loads the ramstage. */
-	return ENV_BOOTBLOCK;
+	if (ENV_RAMSTAGE_LOADER && CONFIG(COMPRESS_RAMSTAGE_LZMA))
+		return true;
+	return false;
 }
 
 static bool cbfs_file_hash_mismatch(const void *buffer, size_t size,

From 2d99da12a9c1189d78517b5d700ba92276bf1640 Mon Sep 17 00:00:00 2001
From: Arthur Heymans <arthur@aheymans.xyz>
Date: Tue, 22 Nov 2022 16:33:29 +0100
Subject: [PATCH 2876/3886] commonlib/bsd: Add zstd support

This adds the option to compress ramstage and payloads with zstd.

zstd compressed ramstages are typically +5% bigger than lzma compressed
ramstages. The decompressor .text section grows by 20KiB and the
decompressor needs 16KiB more heap than the lzma decompressor.

To use less heap inside the zstd decompressor the build time define
ZSTD_DECODER_INTERNAL_BUFFER is used.

Quote:
 The build macro `ZSTD_DECODER_INTERNAL_BUFFER` can be set to control
 the amount of extra memory used during decompression to store
 literals. This defaults to 64kB.  Reducing this value reduces the
 memory footprint of `ZSTD_DCtx` decompression contexts, but might
 also result in a small decompression speed cost

TEST=Booted on Lenovo X220 with zstd ramstage showed no disadvantage
     over a bigger internal buffer used.
TEST=Booted on Lenovo X220. The zstd decompressor is twice as fast
     as the lzma decompressor.
     cbmem -t shows:
   - finished ZSTD decompress (ignore for x86)         79,444 (24,494)
   - finished LZMA decompress (ignore for x86)         94,971 (45,545)

TEST=Booted on QEMU Q35, QEMU aarch64 virt, QEMU riscv RV64 with
     zstd compressed ramstage.

Change-Id: Ic1b1f53327c598d07bd83d4391e8012d41696a16
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69893
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 Makefile.mk                                   |  7 ++-
 payloads/Kconfig                              |  6 +++
 src/Kconfig                                   | 13 ++++++
 src/commonlib/Makefile.mk                     |  2 +
 .../bsd/include/commonlib/bsd/compression.h   |  2 +-
 src/commonlib/bsd/zstd/Makefile.mk            | 43 +++++++++++++++++++
 .../bsd/zstd/decompress/zstd_decompress.c     |  2 +-
 src/commonlib/bsd/zstd_wrapper.c              | 18 ++++++++
 .../include/commonlib/timestamp_serialized.h  |  4 ++
 src/lib/cbfs.c                                | 27 ++++++++++++
 src/lib/selfboot.c                            | 13 ++++++
 tests/lib/cbfs-lookup-test.c                  |  8 ++++
 tests/lib/cbfs-verification-test.c            |  6 +++
 13 files changed, 147 insertions(+), 4 deletions(-)
 create mode 100644 src/commonlib/bsd/zstd/Makefile.mk
 create mode 100644 src/commonlib/bsd/zstd_wrapper.c

diff --git a/Makefile.mk b/Makefile.mk
index 75787b32d4..cab60b33a4 100644
--- a/Makefile.mk
+++ b/Makefile.mk
@@ -455,6 +455,8 @@ cbfs-files-handler= \
 CBFS_COMPRESS_FLAG:=none
 ifeq ($(CONFIG_COMPRESS_RAMSTAGE_LZMA),y)
 CBFS_COMPRESS_FLAG:=LZMA
+else ifeq ($(CONFIG_COMPRESS_RAMSTAGE_ZSTD),y)
+CBFS_COMPRESS_FLAG:=ZSTD
 endif
 ifeq ($(CONFIG_COMPRESS_RAMSTAGE_LZ4),y)
 CBFS_COMPRESS_FLAG:=LZ4
@@ -463,9 +465,10 @@ endif
 CBFS_PAYLOAD_COMPRESS_FLAG:=none
 ifeq ($(CONFIG_COMPRESSED_PAYLOAD_LZMA),y)
 CBFS_PAYLOAD_COMPRESS_FLAG:=LZMA
-endif
-ifeq ($(CONFIG_COMPRESSED_PAYLOAD_LZ4),y)
+else ifeq ($(CONFIG_COMPRESSED_PAYLOAD_LZ4),y)
 CBFS_PAYLOAD_COMPRESS_FLAG:=LZ4
+else ifeq ($(CONFIG_COMPRESSED_PAYLOAD_ZSTD),y)
+CBFS_PAYLOAD_COMPRESS_FLAG:=ZSTD
 endif
 
 CBFS_SECONDARY_PAYLOAD_COMPRESS_FLAG:=none
diff --git a/payloads/Kconfig b/payloads/Kconfig
index be902a1b4b..e30b1ec76c 100644
--- a/payloads/Kconfig
+++ b/payloads/Kconfig
@@ -86,6 +86,12 @@ config COMPRESSED_PAYLOAD_LZMA
 	  In order to reduce the size payloads take up in the ROM chip
 	  coreboot can compress them using the LZMA algorithm.
 
+config COMPRESSED_PAYLOAD_ZSTD
+	bool "Use ZSTD compression for payloads"
+	help
+	  In order to reduce the size payloads take up in the ROM chip
+	  coreboot can compress them using the ZSTD algorithm.
+
 config COMPRESSED_PAYLOAD_LZ4
 	bool "Use LZ4 compression for payloads"
 	help
diff --git a/src/Kconfig b/src/Kconfig
index a7a34b26a5..2b5a2241cc 100644
--- a/src/Kconfig
+++ b/src/Kconfig
@@ -202,10 +202,16 @@ config MB_COMPRESS_RAMSTAGE_LZ4
 	help
 	  Select this in a mainboard to use LZ4 compression by default
 
+config MB_COMPRESS_RAMSTAGE_ZSTD
+	bool
+	help
+	  Select this in a mainboard to use ZSTD compression by default
+
 choice
 	prompt "Ramstage compression"
 	depends on HAVE_RAMSTAGE && !UNCOMPRESSED_RAMSTAGE
 	default COMPRESS_RAMSTAGE_LZ4 if MB_COMPRESS_RAMSTAGE_LZ4
+	default COMPRESS_RAMSTAGE_ZSTD if MB_COMPRESS_RAMSTAGE_ZSTD
 	default COMPRESS_RAMSTAGE_LZMA
 
 config COMPRESS_RAMSTAGE_LZMA
@@ -226,6 +232,13 @@ config COMPRESS_RAMSTAGE_LZ4
 
 	  If you're not sure, stick with LZMA.
 
+config COMPRESS_RAMSTAGE_ZSTD
+	bool "Compress ramstage with ZSTD"
+	help
+	  Compress ramstage with ZSTD.
+	  This is faster than LZMA but uses more BSS.
+	  However it decompresses faster on slower CPUs and is suited for
+	  platforms with high speed SPI interfaces, but limited computing power.
 endchoice
 
 config COMPRESS_PRERAM_STAGES
diff --git a/src/commonlib/Makefile.mk b/src/commonlib/Makefile.mk
index 44f63e1ea6..b4bc1b8fae 100644
--- a/src/commonlib/Makefile.mk
+++ b/src/commonlib/Makefile.mk
@@ -1,6 +1,7 @@
 ## SPDX-License-Identifier: GPL-2.0-only
 
 subdirs-y += storage
+subdirs-y += bsd/zstd
 
 bootblock-y += mem_pool.c
 verstage-y += mem_pool.c
@@ -58,6 +59,7 @@ ramstage-y += bsd/lz4_wrapper.c
 postcar-y += bsd/lz4_wrapper.c
 
 all-y += list.c
+all-y += bsd/zstd_wrapper.c
 
 ramstage-y += sort.c
 
diff --git a/src/commonlib/bsd/include/commonlib/bsd/compression.h b/src/commonlib/bsd/include/commonlib/bsd/compression.h
index 1f70fa4c60..b13bc4c8b6 100644
--- a/src/commonlib/bsd/include/commonlib/bsd/compression.h
+++ b/src/commonlib/bsd/include/commonlib/bsd/compression.h
@@ -19,6 +19,6 @@ size_t ulz4fn(const void *src, size_t srcn, void *dst, size_t dstn);
 size_t ulz4f(const void *src, void *dst);
 
 /* Decompresses ZSTD image */
-size_t uzstdfn(const void *src, size_t srcn, void *dst, size_t dstn);
+size_t uzstdn(const void *src, size_t srcn, void *dst, size_t dstn);
 
 #endif	/* _COMMONLIB_COMPRESSION_H_ */
diff --git a/src/commonlib/bsd/zstd/Makefile.mk b/src/commonlib/bsd/zstd/Makefile.mk
new file mode 100644
index 0000000000..d04ad31e98
--- /dev/null
+++ b/src/commonlib/bsd/zstd/Makefile.mk
@@ -0,0 +1,43 @@
+/* SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0-only */
+
+zstd_support=n
+ifeq ($(CONFIG_COMPRESS_RAMSTAGE_ZSTD),y)
+zstd_support=y
+endif
+ifeq ($(CONFIG_COMPRESSED_PAYLOAD_ZSTD),y)
+zstd_support=y
+endif
+
+ifeq ($(zstd_support),y)
+all-y += decompress/huf_decompress.c
+all-y += decompress/zstd_ddict.c
+all-y += decompress/zstd_decompress_block.c
+all-y += decompress/zstd_decompress.c
+
+all-y += common/entropy_common.c
+all-y += common/fse_decompress.c
+
+CPPFLAGS_common += -DZSTD_DISABLE_ASM=1
+# Measured on Intel Sandy Bridge i5-2540M at 800Mhz:
+# Setting                                      code size reduction    time loss
+# -DHUF_FORCE_DECOMPRESS_X1=1                  6.4 KiB                6%
+# -DHUF_FORCE_DECOMPRESS_X2=1                  5.4 KiB                7%
+# -DZSTD_FORCE_DECOMPRESS_SEQUENCES_SHORT=1    8.1 KiB                19%
+# -DZSTD_FORCE_DECOMPRESS_SEQUENCES_LONG=1     7.8 KiB                15%
+
+CPPFLAGS_common += -DHUF_FORCE_DECOMPRESS_X1=1
+CPPFLAGS_common += -DZSTD_FORCE_DECOMPRESS_SEQUENCES_SHORT=1
+CPPFLAGS_common += -DZSTD_STRIP_ERROR_STRINGS=1
+
+# Huffman fast decode needs 64bit and LE
+CPPFLAGS_x86_32 += -DHUF_DISABLE_FAST_DECODE=1
+# Measured on Intel Sandy Bridge i5-2540M at 800Mhz (x86_64 only):
+# Setting                                      code size reduction    time loss
+# -DHUF_DISABLE_FAST_DECODE=1                  2.3 KiB                5%
+
+CPPFLAGS_common += -DDYNAMIC_BMI2=0 -DSTATIC_BMI2=0 -DZSTD_DECODER_INTERNAL_BUFFER=2048
+endif
+
+CPPFLAGS_common += -I$(src)/commonlib/bsd/zstd
+CPPFLAGS_common += -I$(src)/commonlib/bsd/zstd/common
+CPPFLAGS_common += -I$(src)/commonlib/bsd/zstd/decompress
diff --git a/src/commonlib/bsd/zstd/decompress/zstd_decompress.c b/src/commonlib/bsd/zstd/decompress/zstd_decompress.c
index e24795d15e..e87776a68c 100644
--- a/src/commonlib/bsd/zstd/decompress/zstd_decompress.c
+++ b/src/commonlib/bsd/zstd/decompress/zstd_decompress.c
@@ -667,7 +667,7 @@ size_t ZSTD_decompressMultiFrame(ZSTD_DCtx* dctx,
         {   const size_t res = ZSTD_decompressFrame(dctx, dst, dstCapacity,
                                                     &src, &srcSize);
             RETURN_ERROR_IF(
-                (ZSTD_getErrorCode(res) == ZSTD_error_prefix_unknown)
+                (ERR_getErrorCode(res) == ZSTD_error_prefix_unknown)
              && (moreThan1Frame==1),
                 srcSize_wrong,
                 "At least one frame successfully completed, "
diff --git a/src/commonlib/bsd/zstd_wrapper.c b/src/commonlib/bsd/zstd_wrapper.c
new file mode 100644
index 0000000000..8905120635
--- /dev/null
+++ b/src/commonlib/bsd/zstd_wrapper.c
@@ -0,0 +1,18 @@
+/* SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0-only */
+
+#include <assert.h>
+#include <commonlib/bsd/compression.h>
+#include <stdint.h>
+#include <stddef.h>
+#define ZSTD_STATIC_LINKING_ONLY 1
+#include <zstd.h>
+#undef ZSTD_STATIC_LINKING_ONLY
+#include <zstd_decompress_internal.h>
+
+size_t uzstdn(const void *src, size_t srcn, void *dst, size_t dstn)
+{
+	static ZSTD_DCtx dctx __aligned(8);
+	if (!ZSTD_initStaticDCtx(&dctx, sizeof(dctx)))
+		return 0;
+	return ZSTD_decompressDCtx(&dctx, dst, dstn, src, srcn);
+}
diff --git a/src/commonlib/include/commonlib/timestamp_serialized.h b/src/commonlib/include/commonlib/timestamp_serialized.h
index 2a159f64b8..3999b35069 100644
--- a/src/commonlib/include/commonlib/timestamp_serialized.h
+++ b/src/commonlib/include/commonlib/timestamp_serialized.h
@@ -37,6 +37,8 @@ enum timestamp_id {
 	TS_ULZMA_END = 16,
 	TS_ULZ4F_START = 17,
 	TS_ULZ4F_END = 18,
+	TS_UZSTDF_START = 19,
+	TS_UZSTDF_END = 20,
 	TS_DEVICE_INIT_CHIPS = 30,
 	TS_DEVICE_ENUMERATE = 31,
 	TS_DEVICE_CONFIGURE = 40,
@@ -236,6 +238,8 @@ static const struct timestamp_id_to_name {
 	TS_NAME_DEF(TS_ULZMA_END, 0, "finished LZMA decompress (ignore for x86)"),
 	TS_NAME_DEF(TS_ULZ4F_START, TS_ULZ4F_END, "starting LZ4 decompress (ignore for x86)"),
 	TS_NAME_DEF(TS_ULZ4F_END, 0, "finished LZ4 decompress (ignore for x86)"),
+	TS_NAME_DEF(TS_UZSTDF_START, TS_UZSTDF_END, "starting ZSTD decompress (ignore for x86)"),
+	TS_NAME_DEF(TS_UZSTDF_END, 0, "finished ZSTD decompress (ignore for x86)"),
 	TS_NAME_DEF(TS_DEVICE_INIT_CHIPS, TS_DEVICE_ENUMERATE, "early chipset initialization"),
 	TS_NAME_DEF(TS_DEVICE_ENUMERATE, TS_DEVICE_CONFIGURE, "device enumeration"),
 	TS_NAME_DEF(TS_DEVICE_CONFIGURE, TS_DEVICE_ENABLE,  "device configuration"),
diff --git a/src/lib/cbfs.c b/src/lib/cbfs.c
index 4ec65a864c..1dd9288bff 100644
--- a/src/lib/cbfs.c
+++ b/src/lib/cbfs.c
@@ -155,6 +155,15 @@ static inline bool cbfs_lzma_enabled(void)
 	return false;
 }
 
+static inline bool cbfs_zstd_enabled(void)
+{
+	if (ENV_PAYLOAD_LOADER && CONFIG(COMPRESSED_PAYLOAD_ZSTD))
+		return true;
+	if (ENV_RAMSTAGE_LOADER && CONFIG(COMPRESS_RAMSTAGE_ZSTD))
+		return true;
+	return false;
+}
+
 static bool cbfs_file_hash_mismatch(const void *buffer, size_t size,
 				    const union cbfs_mdata *mdata, bool skip_verification)
 {
@@ -267,6 +276,24 @@ static size_t cbfs_load_and_decompress(const struct region_device *rdev, void *b
 
 		rdev_munmap(rdev, map);
 
+		return out_size;
+	case CBFS_COMPRESS_ZSTD:
+		if (!cbfs_zstd_enabled())
+			return 0;
+
+		map = rdev_mmap_full(rdev);
+		if (map == NULL)
+			return 0;
+
+		if (!cbfs_file_hash_mismatch(map, in_size, mdata, skip_verification)) {
+			/* Note: timestamp not useful for memory-mapped media (x86) */
+			timestamp_add_now(TS_UZSTDF_START);
+			out_size = uzstdn(map, in_size, buffer, buffer_size);
+			timestamp_add_now(TS_UZSTDF_END);
+		}
+
+		rdev_munmap(rdev, map);
+
 		return out_size;
 
 	default:
diff --git a/src/lib/selfboot.c b/src/lib/selfboot.c
index e21c493701..5a2321815e 100644
--- a/src/lib/selfboot.c
+++ b/src/lib/selfboot.c
@@ -87,6 +87,19 @@ static int load_one_segment(uint8_t *dest,
 			return 0;
 		break;
 	}
+	case CBFS_COMPRESS_ZSTD: {
+		if (!CONFIG(COMPRESSED_PAYLOAD_ZSTD))
+			return 0;
+
+		printk(BIOS_DEBUG, "using ZSTD\n");
+		timestamp_add_now(TS_UZSTDF_START);
+		len = uzstdn(src, len, dest, memsz);
+		timestamp_add_now(TS_UZSTDF_END);
+		if (!len) /* Decompression Error. */
+			return 0;
+		break;
+	}
+
 	case CBFS_COMPRESS_NONE: {
 		printk(BIOS_DEBUG, "it's not compressed!\n");
 		memcpy(dest, src, len);
diff --git a/tests/lib/cbfs-lookup-test.c b/tests/lib/cbfs-lookup-test.c
index 75628683b6..d6cc5d95a2 100644
--- a/tests/lib/cbfs-lookup-test.c
+++ b/tests/lib/cbfs-lookup-test.c
@@ -62,6 +62,14 @@ size_t ulzman(const void *src, size_t srcn, void *dst, size_t dstn)
 	return dstn;
 }
 
+size_t uzstdn(const void *src, size_t srcn, void *dst, size_t dstn)
+{
+	check_expected(srcn);
+	check_expected(dstn);
+	memcpy(dst, src, dstn);
+	return dstn;
+}
+
 size_t ulz4fn(const void *src, size_t srcn, void *dst, size_t dstn)
 {
 	check_expected(srcn);
diff --git a/tests/lib/cbfs-verification-test.c b/tests/lib/cbfs-verification-test.c
index b1a39bcaac..8abc36c053 100644
--- a/tests/lib/cbfs-verification-test.c
+++ b/tests/lib/cbfs-verification-test.c
@@ -52,6 +52,12 @@ size_t ulzman(const void *src, size_t srcn, void *dst, size_t dstn)
 	return 0;
 }
 
+size_t uzstdn(const void *src, size_t srcn, void *dst, size_t dstn)
+{
+	fail_msg("Unexpected call to %s", __func__);
+	return 0;
+}
+
 size_t ulz4fn(const void *src, size_t srcn, void *dst, size_t dstn)
 {
 	fail_msg("Unexpected call to %s", __func__);

From 35be1ab679a4a9579749f311cce242f3255c98cd Mon Sep 17 00:00:00 2001
From: Patrick Rudolph <patrick.rudolph@9elements.com>
Date: Sat, 20 Sep 2025 10:33:15 +0200
Subject: [PATCH 2877/3886] configs: Build test ramstage zstd compressed

Build test the zstd code on qemu x86 and qemu aarch64.

Change-Id: Ib1f10b983492e01f74c7218e03e04615a41e7312
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89277
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
---
 configs/config.emulation_qemu_aarch64_zstd | 3 +++
 configs/config.emulation_qemu_zstd         | 3 +++
 2 files changed, 6 insertions(+)
 create mode 100644 configs/config.emulation_qemu_aarch64_zstd
 create mode 100644 configs/config.emulation_qemu_zstd

diff --git a/configs/config.emulation_qemu_aarch64_zstd b/configs/config.emulation_qemu_aarch64_zstd
new file mode 100644
index 0000000000..c1cf7c02c5
--- /dev/null
+++ b/configs/config.emulation_qemu_aarch64_zstd
@@ -0,0 +1,3 @@
+CONFIG_VENDOR_EMULATION=y
+CONFIG_BOARD_EMULATION_QEMU_AARCH64=y
+CONFIG_COMPRESS_RAMSTAGE_ZSTD=y
diff --git a/configs/config.emulation_qemu_zstd b/configs/config.emulation_qemu_zstd
new file mode 100644
index 0000000000..4b0a6feea9
--- /dev/null
+++ b/configs/config.emulation_qemu_zstd
@@ -0,0 +1,3 @@
+CONFIG_VENDOR_EMULATION=y
+CONFIG_BOARD_EMULATION_QEMU_X86_Q35=y
+CONFIG_COMPRESS_RAMSTAGE_ZSTD=y

From 7c4d9e0862ee8078c83adaf625fe09dc3d8f2da1 Mon Sep 17 00:00:00 2001
From: Alicja Michalska <alicja.michalska@9elements.com>
Date: Thu, 18 Dec 2025 20:52:51 +0100
Subject: [PATCH 2878/3886] mb/google/*: Update Kconfig names with all known
 board names

In addition to adding all currently-known names for the boards, add SoC
names to baseboards to make finding boards based on SoC family easier.

Change-Id: I389f68f09409ce3eb51422dbcfe7e80d463a1594
Signed-off-by: Alicja Michalska <alicja.michalska@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90555
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
---
 src/mainboard/google/asurada/Kconfig.name     |  4 +-
 src/mainboard/google/auron/Kconfig.name       |  2 +-
 src/mainboard/google/beltino/Kconfig.name     |  2 +-
 src/mainboard/google/bluey/Kconfig.name       |  2 +-
 src/mainboard/google/brox/Kconfig.name        |  2 +-
 src/mainboard/google/brya/Kconfig.name        |  4 +-
 src/mainboard/google/butterfly/Kconfig.name   |  2 +-
 src/mainboard/google/cherry/Kconfig.name      |  6 +--
 src/mainboard/google/corsola/Kconfig.name     | 31 +++++++++-----
 src/mainboard/google/cyan/Kconfig.name        |  2 +-
 src/mainboard/google/daisy/Kconfig.name       |  2 +-
 src/mainboard/google/dedede/Kconfig.name      | 40 ++++++++++++++++---
 src/mainboard/google/drallion/Kconfig.name    |  4 +-
 src/mainboard/google/eve/Kconfig.name         |  2 +-
 src/mainboard/google/fatcat/Kconfig.name      | 32 +++++++--------
 src/mainboard/google/fizz/Kconfig.name        |  2 +-
 src/mainboard/google/foster/Kconfig.name      |  2 +-
 src/mainboard/google/gale/Kconfig.name        |  2 +-
 src/mainboard/google/geralt/Kconfig.name      |  4 +-
 src/mainboard/google/glados/Kconfig.name      |  2 +-
 src/mainboard/google/gru/Kconfig.name         |  2 +-
 src/mainboard/google/guybrush/Kconfig.name    |  2 +-
 src/mainboard/google/hatch/Kconfig.name       |  2 +-
 src/mainboard/google/herobrine/Kconfig.name   | 10 ++---
 src/mainboard/google/jecht/Kconfig.name       |  2 +-
 src/mainboard/google/kahlee/Kconfig.name      |  2 +-
 src/mainboard/google/kukui/Kconfig.name       | 16 ++++----
 src/mainboard/google/link/Kconfig.name        |  2 +-
 src/mainboard/google/mistral/Kconfig.name     |  2 +-
 src/mainboard/google/myst/Kconfig.name        |  2 +-
 src/mainboard/google/nyan/Kconfig.name        |  2 +-
 src/mainboard/google/nyan_big/Kconfig.name    |  2 +-
 src/mainboard/google/nyan_blaze/Kconfig.name  |  2 +-
 src/mainboard/google/oak/Kconfig.name         |  2 +-
 src/mainboard/google/ocelot/Kconfig.name      | 22 +++++-----
 src/mainboard/google/octopus/Kconfig.name     |  2 +-
 src/mainboard/google/parrot/Kconfig.name      |  2 +-
 src/mainboard/google/peach_pit/Kconfig.name   |  2 +-
 src/mainboard/google/poppy/Kconfig.name       |  2 +-
 src/mainboard/google/puff/Kconfig.name        |  2 +-
 src/mainboard/google/rambi/Kconfig.name       |  2 +-
 src/mainboard/google/rauru/Kconfig.name       |  6 +--
 src/mainboard/google/reef/Kconfig.name        |  2 +-
 src/mainboard/google/rex/Kconfig.name         | 20 +++++-----
 src/mainboard/google/sarien/Kconfig.name      |  2 +-
 src/mainboard/google/skyrim/Kconfig.name      |  2 +-
 src/mainboard/google/skywalker/Kconfig.name   |  6 +--
 src/mainboard/google/slippy/Kconfig.name      |  2 +-
 src/mainboard/google/smaug/Kconfig.name       |  2 +-
 src/mainboard/google/storm/Kconfig.name       |  2 +-
 src/mainboard/google/stout/Kconfig.name       |  2 +-
 src/mainboard/google/trogdor/Kconfig.name     | 16 +++++---
 src/mainboard/google/veyron/Kconfig.name      |  2 +-
 .../google/veyron_mickey/Kconfig.name         |  2 +-
 .../google/veyron_rialto/Kconfig.name         |  2 +-
 src/mainboard/google/volteer/Kconfig.name     |  2 +-
 src/mainboard/google/zork/Kconfig.name        |  2 +-
 57 files changed, 176 insertions(+), 129 deletions(-)

diff --git a/src/mainboard/google/asurada/Kconfig.name b/src/mainboard/google/asurada/Kconfig.name
index 278655180e..159b11e380 100644
--- a/src/mainboard/google/asurada/Kconfig.name
+++ b/src/mainboard/google/asurada/Kconfig.name
@@ -1,12 +1,12 @@
 ## SPDX-License-Identifier: GPL-2.0-only
 
-comment "Asurada"
+comment "Asurada (MediaTek Kompanio 820 (MT8192))"
 
 config BOARD_GOOGLE_ASURADA
 	bool "->  Asurada"
 
 config BOARD_GOOGLE_HAYATO
-	bool "->  Hayato"
+	bool "->  Hayato (ASUS Chromebook Flip CM3 (CM3200))"
 
 config BOARD_GOOGLE_SPHERION
 	bool "->  Spherion (Acer Chromebook 514 (CB514-2H, CB514-2HT))"
diff --git a/src/mainboard/google/auron/Kconfig.name b/src/mainboard/google/auron/Kconfig.name
index 1db2149b4c..953228e73c 100644
--- a/src/mainboard/google/auron/Kconfig.name
+++ b/src/mainboard/google/auron/Kconfig.name
@@ -1,6 +1,6 @@
 ## SPDX-License-Identifier: GPL-2.0-only
 
-comment "Auron"
+comment "Auron (Intel Broadwell (5th Gen))"
 
 config BOARD_GOOGLE_AURON_PAINE
 	bool "->  Auron_Paine (Acer C740 Chromebook)"
diff --git a/src/mainboard/google/beltino/Kconfig.name b/src/mainboard/google/beltino/Kconfig.name
index a794330c63..fe9dc27814 100644
--- a/src/mainboard/google/beltino/Kconfig.name
+++ b/src/mainboard/google/beltino/Kconfig.name
@@ -1,6 +1,6 @@
 ## SPDX-License-Identifier: GPL-2.0-only
 
-comment "Beltino"
+comment "Beltino (Intel Haswell (4th Gen))"
 
 config BOARD_GOOGLE_MCCLOUD
 	bool "->  Mccloud (Acer Chromebox CXI)"
diff --git a/src/mainboard/google/bluey/Kconfig.name b/src/mainboard/google/bluey/Kconfig.name
index 3925717a65..274c1e5042 100644
--- a/src/mainboard/google/bluey/Kconfig.name
+++ b/src/mainboard/google/bluey/Kconfig.name
@@ -1,6 +1,6 @@
 ## SPDX-License-Identifier: GPL-2.0-only
 
-comment "Bluey"
+comment "Bluey (Qualcomm Snapdragon X Plus (X1P-42-100))"
 
 config BOARD_GOOGLE_BLUEY
 	bool "->  Bluey"
diff --git a/src/mainboard/google/brox/Kconfig.name b/src/mainboard/google/brox/Kconfig.name
index ca231025fc..4c73eebcf3 100644
--- a/src/mainboard/google/brox/Kconfig.name
+++ b/src/mainboard/google/brox/Kconfig.name
@@ -1,6 +1,6 @@
 ## SPDX-License-Identifier: GPL-2.0-only
 
-comment "Brox"
+comment "Brox (Intel RaptorLake (13th Gen))"
 
 config BOARD_GOOGLE_BROX
 	bool "->  Brox"
diff --git a/src/mainboard/google/brya/Kconfig.name b/src/mainboard/google/brya/Kconfig.name
index 2565a426ef..c4a5c06dc7 100644
--- a/src/mainboard/google/brya/Kconfig.name
+++ b/src/mainboard/google/brya/Kconfig.name
@@ -1,6 +1,6 @@
 ## SPDX-License-Identifier: GPL-2.0-only
 
-comment "Brya"
+comment "Brya (Intel AlderLake/RaptorLake/TwinLake (12 - 13th Gen))"
 
 config BOARD_GOOGLE_AGAH
 	bool "->  Agah"
@@ -189,7 +189,7 @@ config BOARD_GOOGLE_TEREID
 	bool "->  Tereid"
 
 config BOARD_GOOGLE_TIVVIKS
-	bool "-> Tivviks"
+	bool "->  Tivviks"
 
 config BOARD_GOOGLE_TRULO
 	bool "->  Trulo"
diff --git a/src/mainboard/google/butterfly/Kconfig.name b/src/mainboard/google/butterfly/Kconfig.name
index fdde138279..e02eeb9609 100644
--- a/src/mainboard/google/butterfly/Kconfig.name
+++ b/src/mainboard/google/butterfly/Kconfig.name
@@ -1,6 +1,6 @@
 ## SPDX-License-Identifier: GPL-2.0-only
 
-comment "Butterfly"
+comment "Butterfly (Intel SandyBridge (2nd Gen))"
 
 config BOARD_GOOGLE_BUTTERFLY
 	bool "->  Butterfly (HP Pavilion Chromebook 14)"
diff --git a/src/mainboard/google/cherry/Kconfig.name b/src/mainboard/google/cherry/Kconfig.name
index 666bce4bf0..bef53bab40 100644
--- a/src/mainboard/google/cherry/Kconfig.name
+++ b/src/mainboard/google/cherry/Kconfig.name
@@ -1,12 +1,12 @@
 ## SPDX-License-Identifier: GPL-2.0-only
 
-comment "Cherry"
+comment "Cherry (MediaTek Kompanio 1200 (MT8195))"
 
 config BOARD_GOOGLE_CHERRY
 	bool "->  Cherry"
 
 config BOARD_GOOGLE_DOJO
-	bool "->  Dojo"
+	bool "->  Dojo (HP Chromebook x360 (13b-ca0002sa))"
 
 config BOARD_GOOGLE_TOMATO
-	bool "->  Tomato"
+	bool "->  Tomato (Acer Chromebook Spin 513 (CP513-2H))"
diff --git a/src/mainboard/google/corsola/Kconfig.name b/src/mainboard/google/corsola/Kconfig.name
index 5de50c3533..774f07649e 100644
--- a/src/mainboard/google/corsola/Kconfig.name
+++ b/src/mainboard/google/corsola/Kconfig.name
@@ -1,6 +1,6 @@
 ## SPDX-License-Identifier: GPL-2.0-only
 
-comment "Kingler"
+comment "Kingler (MediaTek Kompanio 520 (MT8186))"
 
 config BOARD_GOOGLE_KINGLER
 	bool "->  Kingler"
@@ -12,18 +12,27 @@ config BOARD_GOOGLE_PONYTA
 	bool "->  Ponyta"
 
 config BOARD_GOOGLE_SQUIRTLE
-	bool "->  Squirtle"
+	bool "->  Squirtle (Acer Chromebook Spin 311 (R724T))"
 
 config BOARD_GOOGLE_STEELIX
-	bool "->  Steelix"
+	bool "->  Steelix/Magneton (see help text for details)"
+	help
+		The "Steelix" board supports the following devices:
+		- Lenovo 300e Yoga Chromebook Gen 4 (Steelix, convertible)
+		- Lenovo IdeaPad Slim 3 Chromebook (14M868) (Magneton, clamshell)
 
 config BOARD_GOOGLE_VOLTORB
-	bool "->  Voltorb"
+	bool "->  Voltorb (Acer Chromebook 311 (C723/C732T))"
 
-comment "Krabby"
+comment "Krabby (MediaTek Kompanio 520 (MT8186))"
 
 config BOARD_GOOGLE_CHINCHOU
-	bool "->  Chinchou"
+	bool "->  Chinchou/Chinochou360 (see help text for details)"
+	help
+		The "Chinochou" board supports the following devices:
+		- Asus Chromebook CZ1104CM2A/CZ1204CM2A
+		- Asus Chromebook CZ1104FM2A/CZ1204FM2A/CZ1104CM2A/CZ1204CM2A
+		- Asus Chromebook CZ1104FM2A/CZ1204FM2A Flip
 
 config BOARD_GOOGLE_KRABBY
 	bool "->  Krabby"
@@ -35,15 +44,19 @@ config BOARD_GOOGLE_SKITTY
 	bool "->  Skitty"
 
 config BOARD_GOOGLE_TENTACRUEL
-	bool "->  Tentacruel"
+	bool "->  Tentacruel/Tentacool (see help text for details)"
+	help
+		The "Tentacruel" board supports the following devices:
+		- ASUS Chromebook CM14 Flip (CM1402F) (Tentacruel, convertible)
+		- ASUS Chromebook CM14 (CM1402C) (Tentacool, clamshell)
 
 config BOARD_GOOGLE_VELUZA
 	bool "->  Veluza"
 
-comment "Staryu"
+comment "Staryu (MediaTek Kompanio 528 (MT8186T))"
 
 config BOARD_GOOGLE_STARMIE
-	bool "->  Starmie"
+	bool "->  Starmie (ASUS Chromebook Enterprise CM30 (CM3001))"
 
 config BOARD_GOOGLE_WUGTRIO
 	bool "->  Wugtrio"
diff --git a/src/mainboard/google/cyan/Kconfig.name b/src/mainboard/google/cyan/Kconfig.name
index 6edc464919..7400aee7d6 100644
--- a/src/mainboard/google/cyan/Kconfig.name
+++ b/src/mainboard/google/cyan/Kconfig.name
@@ -1,6 +1,6 @@
 ## SPDX-License-Identifier: GPL-2.0-only
 
-comment "Cyan"
+comment "Cyan (Intel Braswell)"
 
 config BOARD_GOOGLE_BANON
 	bool "->  Banon (Acer Chromebook 15 (CB3-532))"
diff --git a/src/mainboard/google/daisy/Kconfig.name b/src/mainboard/google/daisy/Kconfig.name
index f5152a1ec1..cb16bceac0 100644
--- a/src/mainboard/google/daisy/Kconfig.name
+++ b/src/mainboard/google/daisy/Kconfig.name
@@ -1,6 +1,6 @@
 ## SPDX-License-Identifier: GPL-2.0-only
 
-comment "Daisy"
+comment "Daisy (Samsung Exynos 5250)"
 
 config BOARD_GOOGLE_DAISY
 	bool "->  Daisy (Samsung Chromebook (2012))"
diff --git a/src/mainboard/google/dedede/Kconfig.name b/src/mainboard/google/dedede/Kconfig.name
index fd130ecb8d..1b1c467950 100644
--- a/src/mainboard/google/dedede/Kconfig.name
+++ b/src/mainboard/google/dedede/Kconfig.name
@@ -1,9 +1,16 @@
 ## SPDX-License-Identifier: GPL-2.0-only
 
-comment "Dedede"
+comment "Dedede (Intel JasperLake)"
 
 config BOARD_GOOGLE_BEADRIX
-	bool "->  Beadrix"
+	bool "->  Beadrix (Multiple devices - See help text)"
+	help
+		The "Beadrix" board supports the following devces:
+		- DINATECH Gen1 Chromebook SG20JL1C
+		- Multilaser Chromebook M11C-PC919
+		- Evolve III Chromebook 11 E1
+		- Positivo Chromebook N2320
+		- Allied Chromebook 11 N5100E
 
 config BOARD_GOOGLE_BLIPPER
 	bool "->  Blipper (Lenovo 3i-15 Chromebook)"
@@ -57,10 +64,26 @@ config BOARD_GOOGLE_GOOEY
 	bool "->  Gooey"
 
 config BOARD_GOOGLE_HABOKI
-	bool "->  HABOKI"
+	bool "->  Haboki"
 
 config BOARD_GOOGLE_KRACKO
-	bool "->  Kracko"
+	bool "->  Kracko/Kracko360 (Multiple devices - See help text)"
+	help
+		The "Kracko" board is for "clamshell" form factor.
+		The "Kracko360" board is for "convertible" form factor.
+		They support the following devices:
+		- ADVAN Chromebook 116J
+		- Centerm Chromebook M610
+		- CTL Chromebook NL72
+		- CTL Chromebook NL72T
+		- Edxis Chromebook 11
+		- LG Chromebook 11TC50Q/11TQ50Q
+		- Poin2 Chromebook 11B
+		- Poin2 Chromebook 11E
+		- Zyrex Chromebook M432-64
+		- Multilaser Chromebook M11HC-PC916
+		- Positivo Chromebook N2310
+		- Positivo Chromebook N2312
 
 config BOARD_GOOGLE_LALALA
 	bool "->  Lalala"
@@ -78,7 +101,14 @@ config BOARD_GOOGLE_METAKNIGHT
 	bool "->  Metaknight (NEC Chromebook Y3)"
 
 config BOARD_GOOGLE_PIRIKA
-	bool "->  Pirika"
+	bool "->  Pirika (Multiple devices - See help text)"
+	help
+		The Drawcia board supports the following devices:
+		- Axioo Chromebook P14
+		- CTL Chromebook Enterprise
+		- Gateway Chromebook 14
+		- Arai Nimbus S1 Chromebook Enterprise
+		- Edxis E-Lite Chromebook 14
 
 config BOARD_GOOGLE_SASUKE
 	bool "->  Sasuke (Samsung Galaxy Chromebook Go)"
diff --git a/src/mainboard/google/drallion/Kconfig.name b/src/mainboard/google/drallion/Kconfig.name
index eed2505bcf..3b3f67041e 100644
--- a/src/mainboard/google/drallion/Kconfig.name
+++ b/src/mainboard/google/drallion/Kconfig.name
@@ -1,6 +1,6 @@
 ## SPDX-License-Identifier: GPL-2.0-only
 
-comment "Drallion"
+comment "Drallion (Intel CometLake (10th Gen) with ISH)"
 
 config BOARD_GOOGLE_DRALLION
-	bool "->  Drallion"
+	bool "->  Drallion/Drallion360 (Dell Latitude 7410 Chromebook Enterprise)"
diff --git a/src/mainboard/google/eve/Kconfig.name b/src/mainboard/google/eve/Kconfig.name
index 59d691c045..62e50ff793 100644
--- a/src/mainboard/google/eve/Kconfig.name
+++ b/src/mainboard/google/eve/Kconfig.name
@@ -1,6 +1,6 @@
 ## SPDX-License-Identifier: GPL-2.0-only
 
-comment "Eve"
+comment "Eve (Intel KabyLake (7th Gen))"
 
 config BOARD_GOOGLE_EVE
 	bool "->  Eve (Google Pixelbook)"
diff --git a/src/mainboard/google/fatcat/Kconfig.name b/src/mainboard/google/fatcat/Kconfig.name
index 61582c5102..fbd244e25d 100644
--- a/src/mainboard/google/fatcat/Kconfig.name
+++ b/src/mainboard/google/fatcat/Kconfig.name
@@ -1,48 +1,48 @@
 ## SPDX-License-Identifier: GPL-2.0-only
 
-comment "Fatcat"
+comment "Fatcat (Intel PantherLake (Ultra 3rd Gen))"
 
 config BOARD_GOOGLE_FATCAT
-	bool "-> Fatcat"
+	bool "->  Fatcat"
 
 config BOARD_GOOGLE_FATCAT4ES
-	bool "-> Fatcat4ES"
+	bool "->  Fatcat4ES"
 
 config BOARD_GOOGLE_FATCATISH
-	bool "-> Fatcat_ish"
+	bool "->  Fatcat_ish"
 
 config BOARD_GOOGLE_FATCATITE
-	bool "-> Fatcatite"
+	bool "->  Fatcatite"
 
 config BOARD_GOOGLE_FATCATITE4ES
-	bool "-> Fatcatite4ES"
+	bool "->  Fatcatite4ES"
 
 config BOARD_GOOGLE_FATCATNUVO
-	bool "-> Fatcatnuvo"
+	bool "->  Fatcatnuvo"
 
 config BOARD_GOOGLE_FATCATNUVO4ES
-	bool "-> Fatcatnuvo4ES"
+	bool "->  Fatcatnuvo4ES"
 
 config BOARD_GOOGLE_FELINO
-	bool "-> Felino"
+	bool "->  Felino"
 
 config BOARD_GOOGLE_FELINO4ES
-	bool "-> Felino4ES"
+	bool "->  Felino4ES"
 
 config BOARD_GOOGLE_FRANCKA
-	bool "-> Francka"
+	bool "->  Francka"
 
 config BOARD_GOOGLE_KINMEN4ES
-	bool "-> Kinmen4ES"
+	bool "->  Kinmen4ES"
 
 config BOARD_GOOGLE_KINMEN
-	bool "-> Kinmen"
+	bool "->  Kinmen"
 
 config BOARD_GOOGLE_LAPIS
-	bool "-> Lapis"
+	bool "->  Lapis"
 
 config BOARD_GOOGLE_MOONSTONE
-	bool "-> Moonstone"
+	bool "->  Moonstone"
 
 config BOARD_GOOGLE_RUBY
-	bool "-> Ruby"
+	bool "->  Ruby"
diff --git a/src/mainboard/google/fizz/Kconfig.name b/src/mainboard/google/fizz/Kconfig.name
index 928afd8122..15c82802c5 100644
--- a/src/mainboard/google/fizz/Kconfig.name
+++ b/src/mainboard/google/fizz/Kconfig.name
@@ -1,6 +1,6 @@
 ## SPDX-License-Identifier: GPL-2.0-only
 
-comment "Fizz"
+comment "Fizz (Intel KabyLake/Kabylake-R (7th/8th Gen))"
 
 config BOARD_GOOGLE_FIZZ
 	bool "->  Fizz (Multiple devices - See help text)"
diff --git a/src/mainboard/google/foster/Kconfig.name b/src/mainboard/google/foster/Kconfig.name
index 6a22b74832..12bc11bb37 100644
--- a/src/mainboard/google/foster/Kconfig.name
+++ b/src/mainboard/google/foster/Kconfig.name
@@ -1,6 +1,6 @@
 ## SPDX-License-Identifier: GPL-2.0-only
 
-comment "Foster"
+comment "Foster (Nvidia Tegra X1 (T210))"
 
 config BOARD_GOOGLE_FOSTER
 	bool "->  Foster"
diff --git a/src/mainboard/google/gale/Kconfig.name b/src/mainboard/google/gale/Kconfig.name
index 56d3181fad..a43fd963cd 100644
--- a/src/mainboard/google/gale/Kconfig.name
+++ b/src/mainboard/google/gale/Kconfig.name
@@ -1,6 +1,6 @@
 ## SPDX-License-Identifier: GPL-2.0-only
 
-comment "Gale"
+comment "Gale (Qualcomm IPQ4019)"
 
 config BOARD_GOOGLE_GALE
 	bool "->  Gale (Google WiFi)"
diff --git a/src/mainboard/google/geralt/Kconfig.name b/src/mainboard/google/geralt/Kconfig.name
index 4195d6f3fd..285fd637c6 100644
--- a/src/mainboard/google/geralt/Kconfig.name
+++ b/src/mainboard/google/geralt/Kconfig.name
@@ -1,9 +1,9 @@
 ## SPDX-License-Identifier: GPL-2.0-only
 
-comment "Geralt"
+comment "Geralt (MediaTek Kompanio 838 (MT8188))"
 
 config BOARD_GOOGLE_GERALT
 	bool "->  Geralt"
 
 config BOARD_GOOGLE_CIRI
-	bool "->  Ciri"
+	bool "->  Ciri (Lenovo Chromebook Duet Gen9 (11M889))"
diff --git a/src/mainboard/google/glados/Kconfig.name b/src/mainboard/google/glados/Kconfig.name
index 57711d40be..50d5b0d9a5 100644
--- a/src/mainboard/google/glados/Kconfig.name
+++ b/src/mainboard/google/glados/Kconfig.name
@@ -1,6 +1,6 @@
 ## SPDX-License-Identifier: GPL-2.0-only
 
-comment "Glados"
+comment "Glados (Intel Skylake (6th Gen))"
 
 config BOARD_GOOGLE_ASUKA
 	bool "->  Asuka (Dell Chromebook 13 3380)"
diff --git a/src/mainboard/google/gru/Kconfig.name b/src/mainboard/google/gru/Kconfig.name
index f72a350816..e6b55b7e1a 100644
--- a/src/mainboard/google/gru/Kconfig.name
+++ b/src/mainboard/google/gru/Kconfig.name
@@ -1,6 +1,6 @@
 ## SPDX-License-Identifier: GPL-2.0-only
 
-comment "Gru"
+comment "Gru (Rockchip RK3399)"
 
 config BOARD_GOOGLE_KEVIN
 	bool "->  Kevin (Samsung Chromebook Plus)"
diff --git a/src/mainboard/google/guybrush/Kconfig.name b/src/mainboard/google/guybrush/Kconfig.name
index fc1f864475..b62ee3154a 100644
--- a/src/mainboard/google/guybrush/Kconfig.name
+++ b/src/mainboard/google/guybrush/Kconfig.name
@@ -1,6 +1,6 @@
 ## SPDX-License-Identifier: GPL-2.0-only
 
-comment "Guybrush"
+comment "Guybrush (AMD Ryzen Mobile 5000 (Cezanne))"
 
 config BOARD_GOOGLE_DEWATT
 	bool "->  Dewatt (Acer Chromebook Spin 514)"
diff --git a/src/mainboard/google/hatch/Kconfig.name b/src/mainboard/google/hatch/Kconfig.name
index 57441dc820..2dd8ef88a0 100644
--- a/src/mainboard/google/hatch/Kconfig.name
+++ b/src/mainboard/google/hatch/Kconfig.name
@@ -1,6 +1,6 @@
 ## SPDX-License-Identifier: GPL-2.0-only
 
-comment "Hatch"
+comment "Hatch (Intel CometLake (10th Gen))"
 
 config BOARD_GOOGLE_AKEMI
 	bool "->  Akemi (IdeaPad Flex 5/5i Chromebook)"
diff --git a/src/mainboard/google/herobrine/Kconfig.name b/src/mainboard/google/herobrine/Kconfig.name
index 71b93c2d35..7e9ef66d62 100644
--- a/src/mainboard/google/herobrine/Kconfig.name
+++ b/src/mainboard/google/herobrine/Kconfig.name
@@ -1,6 +1,6 @@
 ## SPDX-License-Identifier: GPL-2.0-only
 
-comment "Herobrine"
+comment "Herobrine (Qualcomm Snapdragon 7c+ Gen3 (SC7280))"
 
 config BOARD_GOOGLE_HEROBRINE
 	bool "->  Herobrine"
@@ -15,16 +15,16 @@ config BOARD_GOOGLE_PIGLIN
 	bool "->  Piglin"
 
 config BOARD_GOOGLE_HOGLIN
-	bool "-> Hoglin"
+	bool "->  Hoglin"
 
 config BOARD_GOOGLE_VILLAGER
-	bool "-> Villager"
+	bool "->  Villager"
 
 config BOARD_GOOGLE_EVOKER
-	bool "-> Evoker"
+	bool "->  Evoker"
 
 config BOARD_GOOGLE_ZOGLIN
-	bool "-> Zoglin"
+	bool "->  Zoglin"
 
 config BOARD_GOOGLE_ZOMBIE
 	bool "->  Zombie"
diff --git a/src/mainboard/google/jecht/Kconfig.name b/src/mainboard/google/jecht/Kconfig.name
index 2da82b422d..8528d020ec 100644
--- a/src/mainboard/google/jecht/Kconfig.name
+++ b/src/mainboard/google/jecht/Kconfig.name
@@ -1,6 +1,6 @@
 ## SPDX-License-Identifier: GPL-2.0-only
 
-comment "Jecht"
+comment "Jecht (Intel Broadwell (5th Gen))"
 
 config BOARD_GOOGLE_GUADO
 	bool "->  Guado (ASUS Chromebox CN62)"
diff --git a/src/mainboard/google/kahlee/Kconfig.name b/src/mainboard/google/kahlee/Kconfig.name
index b102307bd2..46f1b763a8 100644
--- a/src/mainboard/google/kahlee/Kconfig.name
+++ b/src/mainboard/google/kahlee/Kconfig.name
@@ -1,6 +1,6 @@
 ## SPDX-License-Identifier: GPL-2.0-only
 
-comment "Kahlee"
+comment "Kahlee (AMD StoneyRidge)"
 
 config BOARD_GOOGLE_ALEENA
 	bool "->  Aleena/Kasumi (Acer Chromebook  315 (CB315-2H), 311 (C721) / Spin 311 (R721T))"
diff --git a/src/mainboard/google/kukui/Kconfig.name b/src/mainboard/google/kukui/Kconfig.name
index d7f54f6d50..425429834a 100644
--- a/src/mainboard/google/kukui/Kconfig.name
+++ b/src/mainboard/google/kukui/Kconfig.name
@@ -1,6 +1,6 @@
 ## SPDX-License-Identifier: GPL-2.0-only
 
-comment "Kukui"
+comment "Kukui (MediaTek Kompanio 500 (MT8183))"
 
 config BOARD_GOOGLE_KUKUI
 	bool "->  Kukui"
@@ -12,7 +12,7 @@ config BOARD_GOOGLE_KODAMA
 	bool "->  Kodama (Lenovo 10e Chromebook Tablet)"
 
 config BOARD_GOOGLE_KAKADU
-	bool "->  Kakadu"
+	bool "->  Kakadu (ASUS Chromebook Detachable CM3)"
 
 config BOARD_GOOGLE_FLAPJACK
 	bool "->  Flapjack"
@@ -20,7 +20,7 @@ config BOARD_GOOGLE_FLAPJACK
 config BOARD_GOOGLE_KATSU
 	bool "->  Katsu (ASUS Chromebook Detachable CZ1)"
 
-comment "Jacuzzi"
+comment "Jacuzzi (MediaTek Kompanio 500 (MT8183))"
 
 config BOARD_GOOGLE_JACUZZI
 	bool "->  Jacuzzi"
@@ -29,7 +29,7 @@ config BOARD_GOOGLE_JUNIPER
 	bool "->  Juniper (Acer Chromebook Spin 311 (CP311-3H))"
 
 config BOARD_GOOGLE_KAPPA
-	bool "->  Kappa"
+	bool "->  Kappa (HP Chromebook 11a)"
 
 config BOARD_GOOGLE_DAMU
 	bool "->  Damu (ASUS Chromebook Flip CM3 (CM3200))"
@@ -41,7 +41,7 @@ config BOARD_GOOGLE_STERN
 	bool "->  Stern"
 
 config BOARD_GOOGLE_WILLOW
-	bool "->  Willow"
+	bool "->  Willow (Acer Chromebook 311 (C722/C722T))"
 
 config BOARD_GOOGLE_ESCHE
 	bool "->  Esche (HP Chromebook 11MK G9 EE)"
@@ -50,16 +50,16 @@ config BOARD_GOOGLE_BURNET
 	bool "->  Burnet (HP Chromebook x360 11MK G3 EE)"
 
 config BOARD_GOOGLE_FENNEL
-	bool "->  Fennel"
+	bool "->  Fennel (Lenovo IdeaPad 3 Chromebook)"
 
 config BOARD_GOOGLE_COZMO
 	bool "->  Cozmo (Acer Chromebook 314 (CB314-2H/CB314-2HT))"
 
 config BOARD_GOOGLE_MAKOMO
-	bool "->  Makomo"
+	bool "->  Makomo (Lenovo 100e Chromebook (2nd Gen))"
 
 config BOARD_GOOGLE_MUNNA
 	bool "->  Munna"
 
 config BOARD_GOOGLE_PICO
-	bool "->  Pico"
+	bool "->  Pico (Acer Chromebook Spin 311)"
diff --git a/src/mainboard/google/link/Kconfig.name b/src/mainboard/google/link/Kconfig.name
index 87d548bd64..d53ffa10bb 100644
--- a/src/mainboard/google/link/Kconfig.name
+++ b/src/mainboard/google/link/Kconfig.name
@@ -1,6 +1,6 @@
 ## SPDX-License-Identifier: GPL-2.0-only
 
-comment "Link"
+comment "Link (Intel IvyBridge (3rd Gen))"
 
 config BOARD_GOOGLE_LINK
 	bool "->  Link (Google Chromebook Pixel (2013))"
diff --git a/src/mainboard/google/mistral/Kconfig.name b/src/mainboard/google/mistral/Kconfig.name
index b8f6fa2d9f..0c7517356a 100644
--- a/src/mainboard/google/mistral/Kconfig.name
+++ b/src/mainboard/google/mistral/Kconfig.name
@@ -1,6 +1,6 @@
 ## SPDX-License-Identifier: GPL-2.0-only
 
-comment "Mistral"
+comment "Mistral (Qualcomm Dragonwing QCS405)"
 
 config BOARD_GOOGLE_MISTRAL
 	bool "->  Mistral"
diff --git a/src/mainboard/google/myst/Kconfig.name b/src/mainboard/google/myst/Kconfig.name
index 56fcc1924f..da8bb4b4e7 100644
--- a/src/mainboard/google/myst/Kconfig.name
+++ b/src/mainboard/google/myst/Kconfig.name
@@ -1,6 +1,6 @@
 ## SPDX-License-Identifier: GPL-2.0-only
 
-comment "Myst"
+comment "Myst (AMD Ryzen Mobile 7000 (Phoenix))"
 
 config BOARD_GOOGLE_MYST
 	bool "->  Myst"
diff --git a/src/mainboard/google/nyan/Kconfig.name b/src/mainboard/google/nyan/Kconfig.name
index 8bd2621b5b..db1dd42242 100644
--- a/src/mainboard/google/nyan/Kconfig.name
+++ b/src/mainboard/google/nyan/Kconfig.name
@@ -1,6 +1,6 @@
 ## SPDX-License-Identifier: GPL-2.0-only
 
-comment "Nyan"
+comment "Nyan (NVIDIA Tegra K1 (CD570M))"
 
 config BOARD_GOOGLE_NYAN
 	bool "->  Nyan"
diff --git a/src/mainboard/google/nyan_big/Kconfig.name b/src/mainboard/google/nyan_big/Kconfig.name
index dc841b15a5..bda75aa648 100644
--- a/src/mainboard/google/nyan_big/Kconfig.name
+++ b/src/mainboard/google/nyan_big/Kconfig.name
@@ -1,6 +1,6 @@
 ## SPDX-License-Identifier: GPL-2.0-only
 
-comment "Nyan Big"
+comment "Nyan Big (Nvidia Tegra K1 (T124))"
 
 config BOARD_GOOGLE_NYAN_BIG
 	bool "->  Nyan Big (Acer Chromebook 13 (CB5-311))"
diff --git a/src/mainboard/google/nyan_blaze/Kconfig.name b/src/mainboard/google/nyan_blaze/Kconfig.name
index aae2fb7b3d..a16805580a 100644
--- a/src/mainboard/google/nyan_blaze/Kconfig.name
+++ b/src/mainboard/google/nyan_blaze/Kconfig.name
@@ -1,6 +1,6 @@
 ## SPDX-License-Identifier: GPL-2.0-only
 
-comment "Nyan Blaze"
+comment "Nyan Blaze (NVIDIA Tegra K1 (CD570M))"
 
 config BOARD_GOOGLE_NYAN_BLAZE
 	bool "->  Nyan Blaze (HP Chromebook 14 G3)"
diff --git a/src/mainboard/google/oak/Kconfig.name b/src/mainboard/google/oak/Kconfig.name
index ceba037655..9829b55c32 100644
--- a/src/mainboard/google/oak/Kconfig.name
+++ b/src/mainboard/google/oak/Kconfig.name
@@ -1,6 +1,6 @@
 ## SPDX-License-Identifier: GPL-2.0-only
 
-comment "Oak"
+comment "Oak (MediaTek Kompanio 500 (MT8173))"
 
 config BOARD_GOOGLE_OAK
 	bool "->  Oak"
diff --git a/src/mainboard/google/ocelot/Kconfig.name b/src/mainboard/google/ocelot/Kconfig.name
index a57bc43c45..8e5badc67d 100644
--- a/src/mainboard/google/ocelot/Kconfig.name
+++ b/src/mainboard/google/ocelot/Kconfig.name
@@ -1,33 +1,33 @@
 ## SPDX-License-Identifier: GPL-2.0-only
 
-comment "Ocelot"
+comment "Ocelot (Intel WildcatLake (Ultra 3rd Gen))"
 
 config BOARD_GOOGLE_KODKOD
-	bool "-> Kodkod"
+	bool "->  Kodkod"
 
 config BOARD_GOOGLE_MATSU
-	bool "-> Matsu"
+	bool "->  Matsu"
 
 config BOARD_GOOGLE_OCELOT
-	bool "-> Ocelot"
+	bool "->  Ocelot"
 
 config BOARD_GOOGLE_OCELOTITE
-	bool "-> Ocelotite"
+	bool "->  Ocelotite"
 
 config BOARD_GOOGLE_OCELOTMCHP
-	bool "-> Ocelotmchp"
+	bool "->  Ocelotmchp"
 
 config BOARD_GOOGLE_OJAL
-	bool "-> Ojal"
+	bool "->  Ojal"
 
 config BOARD_GOOGLE_OCELOT4ES
-	bool "-> Ocelot4ES"
+	bool "->  Ocelot4ES"
 
 config BOARD_GOOGLE_OCELOTITE4ES
-	bool "-> Ocelotite4ES"
+	bool "->  Ocelotite4ES"
 
 config BOARD_GOOGLE_OCELOTMCHP4ES
-	bool "-> Ocelotmchp4ES"
+	bool "->  Ocelotmchp4ES"
 
 config BOARD_GOOGLE_OCICAT
-	bool "-> Ocicat"
+	bool "->  Ocicat"
diff --git a/src/mainboard/google/octopus/Kconfig.name b/src/mainboard/google/octopus/Kconfig.name
index 7519a2e7bf..90bd4ab449 100644
--- a/src/mainboard/google/octopus/Kconfig.name
+++ b/src/mainboard/google/octopus/Kconfig.name
@@ -1,6 +1,6 @@
 ## SPDX-License-Identifier: GPL-2.0-only
 
-comment "Octopus"
+comment "Octopus (Intel GeminiLake)"
 
 config BOARD_GOOGLE_AMPTON
 	bool "->  Ampton (ASUS Chromebook Flip C214)"
diff --git a/src/mainboard/google/parrot/Kconfig.name b/src/mainboard/google/parrot/Kconfig.name
index bbaa6cf828..c8155e2679 100644
--- a/src/mainboard/google/parrot/Kconfig.name
+++ b/src/mainboard/google/parrot/Kconfig.name
@@ -1,6 +1,6 @@
 ## SPDX-License-Identifier: GPL-2.0-only
 
-comment "Parrot"
+comment "Parrot (Intel SandyBridge (2nd Gen))"
 
 config BOARD_GOOGLE_PARROT
 	bool "->  Parrot (Acer C7/C710 Chromebook)"
diff --git a/src/mainboard/google/peach_pit/Kconfig.name b/src/mainboard/google/peach_pit/Kconfig.name
index 29eddb5594..dc0ab31134 100644
--- a/src/mainboard/google/peach_pit/Kconfig.name
+++ b/src/mainboard/google/peach_pit/Kconfig.name
@@ -1,6 +1,6 @@
 ## SPDX-License-Identifier: GPL-2.0-only
 
-comment "Peach Pit"
+comment "Peach Pit (Samsung Exynos 5420)"
 
 config BOARD_GOOGLE_PEACH_PIT
 	bool "->  Peach Pit (Samsung Chromebook 2 11\")"
diff --git a/src/mainboard/google/poppy/Kconfig.name b/src/mainboard/google/poppy/Kconfig.name
index 7999d77dc3..3566de21ef 100644
--- a/src/mainboard/google/poppy/Kconfig.name
+++ b/src/mainboard/google/poppy/Kconfig.name
@@ -1,6 +1,6 @@
 ## SPDX-License-Identifier: GPL-2.0-only
 
-comment "Poppy"
+comment "Poppy (Intel KabyLake/KabyLake-R (7th/8th Gen))"
 
 config BOARD_GOOGLE_ATLAS
 	bool "->  Atlas (Google Pixelbook Go)"
diff --git a/src/mainboard/google/puff/Kconfig.name b/src/mainboard/google/puff/Kconfig.name
index d8a997e7fb..947e91057d 100644
--- a/src/mainboard/google/puff/Kconfig.name
+++ b/src/mainboard/google/puff/Kconfig.name
@@ -1,6 +1,6 @@
 ## SPDX-License-Identifier: GPL-2.0-only
 
-comment "Puff"
+comment "Puff (Intel CometLake (10th Gen))"
 
 config BOARD_GOOGLE_AMBASSADOR
 	bool "->  Ambassador (Meet Compute System [Intel 10th Gen])"
diff --git a/src/mainboard/google/rambi/Kconfig.name b/src/mainboard/google/rambi/Kconfig.name
index cd63c425dc..07324384bb 100644
--- a/src/mainboard/google/rambi/Kconfig.name
+++ b/src/mainboard/google/rambi/Kconfig.name
@@ -1,6 +1,6 @@
 ## SPDX-License-Identifier: GPL-2.0-only
 
-comment "Rambi"
+comment "Rambi (Intel Baytrail)"
 
 config BOARD_GOOGLE_BANJO
 	bool "->  Banjo (Acer Chromebook 15 (CB3-531))"
diff --git a/src/mainboard/google/rauru/Kconfig.name b/src/mainboard/google/rauru/Kconfig.name
index f09ee43e15..cac699c553 100644
--- a/src/mainboard/google/rauru/Kconfig.name
+++ b/src/mainboard/google/rauru/Kconfig.name
@@ -1,12 +1,12 @@
 ## SPDX-License-Identifier: GPL-2.0-only
 
-comment "Rauru"
+comment "Rauru (MediaTek Kompanio Ultra 910 (MT8196))"
 
 config BOARD_GOOGLE_HYLIA
-	bool "->  Hylia"
+	bool "->  Hylia (Acer Chromebook Plus Spin 514 (CP514-5HN/CPE594-2N))"
 
 config BOARD_GOOGLE_NAVI
-	bool "->  Navi"
+	bool "->  Navi (Lenovo Chromebook Plus (14M9610))"
 
 config BOARD_GOOGLE_RAURU
 	bool "->  Rauru"
diff --git a/src/mainboard/google/reef/Kconfig.name b/src/mainboard/google/reef/Kconfig.name
index e392c926cc..c8d176c2b8 100644
--- a/src/mainboard/google/reef/Kconfig.name
+++ b/src/mainboard/google/reef/Kconfig.name
@@ -1,6 +1,6 @@
 ## SPDX-License-Identifier: GPL-2.0-only
 
-comment "Reef"
+comment "Reef (Intel ApolloLake)"
 
 config BOARD_GOOGLE_REEF
 	bool "->  Reef/Electro (Acer Chromebook Spin 11 R751T)"
diff --git a/src/mainboard/google/rex/Kconfig.name b/src/mainboard/google/rex/Kconfig.name
index 96aa4c63f1..0d1da6f015 100644
--- a/src/mainboard/google/rex/Kconfig.name
+++ b/src/mainboard/google/rex/Kconfig.name
@@ -1,12 +1,12 @@
 ## SPDX-License-Identifier: GPL-2.0-only
 
-comment "Rex"
+comment "Rex (Intel MeteorLake (Ultra 1st Gen))"
 
 config BOARD_GOOGLE_DEKU
-	bool "-> Deku"
+	bool "->  Deku"
 
 config BOARD_GOOGLE_DEKU4ES
-	bool "-> Deku4ES"
+	bool "->  Deku4ES"
 
 config BOARD_GOOGLE_KARIS
 	bool "->  Karis (Acer Chromebook Plus Spin 714)"
@@ -15,25 +15,25 @@ config BOARD_GOOGLE_KARIS4ES
 	bool "->  Karis4ES"
 
 config BOARD_GOOGLE_OVIS
-	bool "-> Ovis"
+	bool "->  Ovis"
 
 config BOARD_GOOGLE_OVIS4ES
-	bool "-> Ovis4ES"
+	bool "->  Ovis4ES"
 
 config BOARD_GOOGLE_REX0
-	bool "-> Rex 0"
+	bool "->  Rex 0"
 
 config BOARD_GOOGLE_REX_EC_ISH
-	bool "-> Rex EC ISH"
+	bool "->  Rex EC ISH"
 
 config BOARD_GOOGLE_REX4ES
-	bool "-> Rex4ES"
+	bool "->  Rex4ES"
 
 config BOARD_GOOGLE_REX4ES_EC_ISH
-	bool "-> Rex4ES EC ISH"
+	bool "->  Rex4ES EC ISH"
 
 config BOARD_GOOGLE_REX64
-	bool "-> Rex 64"
+	bool "->  Rex 64"
 
 config BOARD_GOOGLE_SCREEBO
 	bool "->  Screebo (ASUS ExpertBook CX54 Chromebook Plus (CX5403))"
diff --git a/src/mainboard/google/sarien/Kconfig.name b/src/mainboard/google/sarien/Kconfig.name
index ad31cb1285..817fd6d278 100644
--- a/src/mainboard/google/sarien/Kconfig.name
+++ b/src/mainboard/google/sarien/Kconfig.name
@@ -1,6 +1,6 @@
 ## SPDX-License-Identifier: GPL-2.0-only
 
-comment "Sarien"
+comment "Sarien (Intel WhiskeyLake (8th Gen))"
 
 config BOARD_GOOGLE_ARCADA
 	bool "->  Arcada (Latitude 5300 2-in-1 Chromebook Enterprise)"
diff --git a/src/mainboard/google/skyrim/Kconfig.name b/src/mainboard/google/skyrim/Kconfig.name
index 5a9668c598..12d28eee97 100644
--- a/src/mainboard/google/skyrim/Kconfig.name
+++ b/src/mainboard/google/skyrim/Kconfig.name
@@ -1,6 +1,6 @@
 ## SPDX-License-Identifier: GPL-2.0-only
 
-comment "Skyrim"
+comment "Skyrim (AMD Ryzen Mobile 7000 (Mendocino))"
 
 config BOARD_GOOGLE_CRYSTALDRIFT
 	bool "->  Crystaldrift (SPC Chromebook V1)"
diff --git a/src/mainboard/google/skywalker/Kconfig.name b/src/mainboard/google/skywalker/Kconfig.name
index 6c67574e94..258c8bd633 100644
--- a/src/mainboard/google/skywalker/Kconfig.name
+++ b/src/mainboard/google/skywalker/Kconfig.name
@@ -1,6 +1,6 @@
 ## SPDX-License-Identifier: GPL-2.0-only OR MIT
 
-comment "Skywalker"
+comment "Skywalker (MediaTek Kompanio 540 (MT8189))"
 
 config BOARD_GOOGLE_ANAKIN
 	bool "->  Anakin"
@@ -18,7 +18,7 @@ config BOARD_GOOGLE_OBIWAN
 	bool "->  Obiwan"
 
 config BOARD_GOOGLE_PADME
-	bool "-> Padme"
+	bool "->  Padme"
 
 config BOARD_GOOGLE_SKYWALKER
 	bool "->  Skywalker"
@@ -27,4 +27,4 @@ config BOARD_GOOGLE_TARKIN
 	bool "->  Tarkin"
 
 config BOARD_GOOGLE_YODA
-	bool "-> Yoda"
+	bool "->  Yoda"
diff --git a/src/mainboard/google/slippy/Kconfig.name b/src/mainboard/google/slippy/Kconfig.name
index f258a2f9a4..fb07f75ed7 100644
--- a/src/mainboard/google/slippy/Kconfig.name
+++ b/src/mainboard/google/slippy/Kconfig.name
@@ -1,6 +1,6 @@
 ## SPDX-License-Identifier: GPL-2.0-only
 
-comment "Slippy"
+comment "Slippy (Intel Haswell (4th Gen))"
 
 config BOARD_GOOGLE_FALCO
 	bool "->  Falco (HP Chromebook 14)"
diff --git a/src/mainboard/google/smaug/Kconfig.name b/src/mainboard/google/smaug/Kconfig.name
index 169a179aab..5273f92f5a 100644
--- a/src/mainboard/google/smaug/Kconfig.name
+++ b/src/mainboard/google/smaug/Kconfig.name
@@ -1,6 +1,6 @@
 ## SPDX-License-Identifier: GPL-2.0-only
 
-comment "Smaug"
+comment "Smaug (Nvidia Tegra X1 (T210))"
 
 config BOARD_GOOGLE_SMAUG
 	bool "->  Smaug (Google Pixel C)"
diff --git a/src/mainboard/google/storm/Kconfig.name b/src/mainboard/google/storm/Kconfig.name
index d2f74da3e8..b252f99465 100644
--- a/src/mainboard/google/storm/Kconfig.name
+++ b/src/mainboard/google/storm/Kconfig.name
@@ -1,6 +1,6 @@
 ## SPDX-License-Identifier: GPL-2.0-only
 
-comment "Storm"
+comment "Storm (Qualcomm IPQ8064)"
 
 config BOARD_GOOGLE_STORM
 	bool "->  Storm (OnHub Router TGR1900)"
diff --git a/src/mainboard/google/stout/Kconfig.name b/src/mainboard/google/stout/Kconfig.name
index f3d61533cf..a1fbee03ea 100644
--- a/src/mainboard/google/stout/Kconfig.name
+++ b/src/mainboard/google/stout/Kconfig.name
@@ -1,6 +1,6 @@
 ## SPDX-License-Identifier: GPL-2.0-only
 
-comment "Stout"
+comment "Stout (Intel SandyBridge (2nd Gen))"
 
 config BOARD_GOOGLE_STOUT
 	bool "->  Stout (Lenovo Thinkpad X131e Chromebook)"
diff --git a/src/mainboard/google/trogdor/Kconfig.name b/src/mainboard/google/trogdor/Kconfig.name
index c3a00ab2aa..a8d41ef028 100644
--- a/src/mainboard/google/trogdor/Kconfig.name
+++ b/src/mainboard/google/trogdor/Kconfig.name
@@ -1,6 +1,6 @@
 ## SPDX-License-Identifier: GPL-2.0-only
 
-comment "Trogdor"
+comment "Trogdor (Qualcomm Snapdragon 7c (SC7180))"
 
 config BOARD_GOOGLE_BUBS
 	bool "->  Bubs"
@@ -12,10 +12,10 @@ config BOARD_GOOGLE_GELARSHIE
 	bool "->  Gelarshie"
 
 config BOARD_GOOGLE_HOMESTAR
-	bool "->  Homestar"
+	bool "->  Homestar (Lenovo IdeaPad Duet 5 Chromebook)"
 
 config BOARD_GOOGLE_KINGOFTOWN
-	bool "->  Kingoftown"
+	bool "->  Kingoftown (HP Fortis 11 G9 Q Chromebook)"
 
 config BOARD_GOOGLE_LAZOR
 	bool "->  Lazor (Acer Chromebook Spin 513, CP513-1H/1HL, R841T/LT)"
@@ -27,16 +27,20 @@ config BOARD_GOOGLE_MRBLAND
 	bool "->  Mrbland"
 
 config BOARD_GOOGLE_PAZQUEL
-	bool "->  Pazquel"
+	bool "->  Pazquel (see help text for details)"
+	help
+		The "Pazquel" board supports the following devices:
+		- Orbic Chromebook 4G
+		- Libera-Merdeka Chromebook C100/C110/C120/C150
 
 config BOARD_GOOGLE_POMPOM
-	bool "->  Pompom"
+	bool "->  Pompom (Dynabook Chromebook C1)"
 
 config BOARD_GOOGLE_QUACKINGSTICK
 	bool "->  Quackingstick (Acer Chromebook Tab 510 / Enterprise Tab 510)"
 
 config BOARD_GOOGLE_WORMDINGLER
-	bool "->  Wormdingler"
+	bool "->  Wormdingler (Lenovo IdeaPad Duet 3 Chromebook)"
 
 config BOARD_GOOGLE_TROGDOR
 	bool "->  Trogdor"
diff --git a/src/mainboard/google/veyron/Kconfig.name b/src/mainboard/google/veyron/Kconfig.name
index 7e174a0931..952e9a8047 100644
--- a/src/mainboard/google/veyron/Kconfig.name
+++ b/src/mainboard/google/veyron/Kconfig.name
@@ -1,6 +1,6 @@
 ## SPDX-License-Identifier: GPL-2.0-only
 
-comment "Veyron"
+comment "Veyron (Rockchip RK3288)"
 
 config BOARD_GOOGLE_VEYRON_JAQ
 	bool "->  Veyron_Jaq (Haier Chromebook 11)"
diff --git a/src/mainboard/google/veyron_mickey/Kconfig.name b/src/mainboard/google/veyron_mickey/Kconfig.name
index 207b447532..ff62fd1389 100644
--- a/src/mainboard/google/veyron_mickey/Kconfig.name
+++ b/src/mainboard/google/veyron_mickey/Kconfig.name
@@ -1,6 +1,6 @@
 ## SPDX-License-Identifier: GPL-2.0-only
 
-comment "Veyron Mickey"
+comment "Veyron Mickey (Rockchip RK3288)"
 
 config BOARD_GOOGLE_VEYRON_MICKEY
 	bool "->  Veyron_Mickey (Asus Chromebit CS10)"
diff --git a/src/mainboard/google/veyron_rialto/Kconfig.name b/src/mainboard/google/veyron_rialto/Kconfig.name
index 490752ea4d..dd17d28871 100644
--- a/src/mainboard/google/veyron_rialto/Kconfig.name
+++ b/src/mainboard/google/veyron_rialto/Kconfig.name
@@ -1,6 +1,6 @@
 ## SPDX-License-Identifier: GPL-2.0-only
 
-comment "Veyron Rialto"
+comment "Veyron Rialto (Rockchip RK3288)"
 
 config BOARD_GOOGLE_VEYRON_RIALTO
 	bool "->  Veyron_Rialto"
diff --git a/src/mainboard/google/volteer/Kconfig.name b/src/mainboard/google/volteer/Kconfig.name
index c3a2401bc9..fcae344309 100644
--- a/src/mainboard/google/volteer/Kconfig.name
+++ b/src/mainboard/google/volteer/Kconfig.name
@@ -1,6 +1,6 @@
 ## SPDX-License-Identifier: GPL-2.0-only
 
-comment "Volteer"
+comment "Volteer (Intel TigerLake (11th Gen))"
 
 config BOARD_GOOGLE_CHRONICLER
 	bool "->  Chronicler (FMV Chromebook 14F)"
diff --git a/src/mainboard/google/zork/Kconfig.name b/src/mainboard/google/zork/Kconfig.name
index 43e1232792..035fd7380c 100644
--- a/src/mainboard/google/zork/Kconfig.name
+++ b/src/mainboard/google/zork/Kconfig.name
@@ -1,6 +1,6 @@
 ## SPDX-License-Identifier: GPL-2.0-only
 
-comment "Zork"
+comment "Zork (AMD Ryzen Mobile 3000 (Picasso))"
 
 config BOARD_GOOGLE_BERKNIP
 	bool "->  Berknip (HP Pro c645 Chromebook Enterprise)"

From 59d438f5c7a0174c4fedc6a18ee3b1205c9fb1e0 Mon Sep 17 00:00:00 2001
From: Kapil Porwal <kapilporwal@google.com>
Date: Fri, 19 Dec 2025 16:46:33 +0530
Subject: [PATCH 2879/3886] mb/google/bluey: Remove GSCVD region from Bluey and
 BlueyH variants

BUG=b:452872947
TEST=Build all the variants of baseboard Google/Bluey.

Change-Id: I1ac76d8fcefbc5f27373723dbabda109ca042fa5
Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90562
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/google/bluey/Kconfig            |  4 ++
 src/mainboard/google/bluey/chromeos-nogsc.fmd | 41 +++++++++++++++++++
 2 files changed, 45 insertions(+)
 create mode 100644 src/mainboard/google/bluey/chromeos-nogsc.fmd

diff --git a/src/mainboard/google/bluey/Kconfig b/src/mainboard/google/bluey/Kconfig
index 8c90202643..c185938caf 100644
--- a/src/mainboard/google/bluey/Kconfig
+++ b/src/mainboard/google/bluey/Kconfig
@@ -176,4 +176,8 @@ config MAINBOARD_GPIO_PIN_FOR_GSC_AP_INTERRUPT
 	  used for the interrupt line from the Google Security Chip (GSC) to the
 	  Application Processor (AP).
 
+config FMDFILE
+	default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/chromeos-nogsc.fmd" if BOARD_GOOGLE_MODEL_BLUEY
+	default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/chromeos.fmd"
+
 endif # BOARD_GOOGLE_BLUEY_COMMON
diff --git a/src/mainboard/google/bluey/chromeos-nogsc.fmd b/src/mainboard/google/bluey/chromeos-nogsc.fmd
new file mode 100644
index 0000000000..aa6b996b3a
--- /dev/null
+++ b/src/mainboard/google/bluey/chromeos-nogsc.fmd
@@ -0,0 +1,41 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
+FLASH@0x0 CONFIG_ROM_SIZE {
+	WP_RO 12M {
+		RO_SECTION {
+			BOOTBLOCK 512K
+			FMAP 4K
+			COREBOOT(CBFS)
+			GBB 0x2f00
+			RO_FRID 0x100
+		}
+		RO_VPD(PRESERVE) 16K
+	}
+
+	RW_MISC 184K {
+		UNIFIED_MRC_CACHE(PRESERVE) 128K {
+			RECOVERY_MRC_CACHE 64K
+			RW_MRC_CACHE 64K
+		}
+		RW_ELOG(PRESERVE) 4K
+		RW_SHARED 4K {
+			SHARED_DATA
+		}
+		RW_VPD(PRESERVE) 32K
+		RW_NVRAM(PRESERVE) 16K
+	}
+
+	RW_SECTION_A 4608K {
+		VBLOCK_A 8K
+		FW_MAIN_A(CBFS)
+		RW_FWID_A 256
+	}
+
+	RW_SECTION_B 4608K {
+		VBLOCK_B 8K
+		FW_MAIN_B(CBFS)
+		RW_FWID_B 256
+	}
+
+	RW_LEGACY(CBFS)
+}

From fa80ab014665884a1342f95bdfdef7e4c53db83f Mon Sep 17 00:00:00 2001
From: Sergii Dmytruk <sergii.dmytruk@3mdeb.com>
Date: Tue, 9 Dec 2025 16:22:10 +0200
Subject: [PATCH 2880/3886] src/Kconfig: add MAINBOARD_NEEDS_CMOS_OPTIONS
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

The addition provides a way to select USE_OPTION_TABLE for a mainboard
which depends on the CMOS backend for options.  This is needed to
support update mechanism based on Top Swap that permits recovery via a
CMOS reset (see [0]).  The indirection is necessary because
USE_OPTION_TABLE is part of a `choice`.

[0]: https://mail.coreboot.org/archives/list/coreboot@coreboot.org/thread/C6JN2PB7K7D67EG7OIKB6BBERZU5YV35/

Change-Id: I9e8f044077a5158650627a305c352cc9de578293
Signed-off-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90433
Reviewed-by: Michał Kopeć <michal.kopec@3mdeb.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Filip Lewiński <filip.lewinski@3mdeb.com>
Reviewed-by: Filip Gołaś <filip.golas@3mdeb.com>
---
 src/Kconfig | 8 +++++++-
 1 file changed, 7 insertions(+), 1 deletion(-)

diff --git a/src/Kconfig b/src/Kconfig
index 2b5a2241cc..6c59e4fa5b 100644
--- a/src/Kconfig
+++ b/src/Kconfig
@@ -151,7 +151,7 @@ choice
 	prompt "Option backend to use"
 	default USE_CBFS_FILE_OPTION_BACKEND if HAVE_CBFS_FILE_OPTION_BACKEND
 	default USE_MAINBOARD_SPECIFIC_OPTION_BACKEND if HAVE_MAINBOARD_SPECIFIC_OPTION_BACKEND
-	default USE_OPTION_TABLE if NVRAMCUI_SECONDARY_PAYLOAD
+	default USE_OPTION_TABLE if NVRAMCUI_SECONDARY_PAYLOAD || MAINBOARD_NEEDS_CMOS_OPTIONS
 	default USE_UEFI_VARIABLE_STORE if DRIVERS_EFI_VARIABLE_STORE && \
 		PAYLOAD_EDK2 && SMMSTORE_V2
 
@@ -904,6 +904,12 @@ config CMOS_LAYOUT_FILE
 	default "src/mainboard/\$(MAINBOARDDIR)/cmos.layout"
 	depends on HAVE_OPTION_TABLE
 
+config MAINBOARD_NEEDS_CMOS_OPTIONS
+	bool
+	help
+	  Select this option if a mainboard depends on storing options in CMOS
+	  for the implementation of some feature.
+
 config PCI_IO_CFG_EXT
 	bool
 	default n

From f773a0faaccc8d2aa5192f923fe44527f20ee04e Mon Sep 17 00:00:00 2001
From: Sergii Dmytruk <sergii.dmytruk@3mdeb.com>
Date: Tue, 9 Dec 2025 16:29:55 +0200
Subject: [PATCH 2881/3886] cpu/intel/fit/Makefile.mk: make FIT in TOPSWAP
 point at MCU in COREBOOT_TS
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

This is a correction of CB:89570 (commit 04ea4724e2d0 ("Makefile.mk:
separate bootblocks into BOOTBLOCK and TOPSWAP")) which has FITs in both
BOOTBLOCK and TOPSWAP point at microcode in COREBOOT region.

This can be tested by comparing outputs of
    build/util/cbfstool/ifittool -f build/coreboot.rom -r TOPSWAP -D
and
    build/util/cbfstool/ifittool -f build/coreboot.rom -r BOOTBLOCK -D
with microcode addresses as shown by
    uefitool build/coreboot.rom
The addresses in two regions must not be identical and their last six
hex digits must match what uefitool shows in "Base:" field (not
"Offset:").

Change-Id: Ie37aee7a26be18d1a4d8993afd2a2484c38c0b1e
Signed-off-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90434
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Filip Gołaś <filip.golas@3mdeb.com>
Reviewed-by: Michał Kopeć <michal.kopec@3mdeb.com>
Reviewed-by: Filip Lewiński <filip.lewinski@3mdeb.com>
---
 src/cpu/intel/fit/Makefile.mk | 6 +++++-
 1 file changed, 5 insertions(+), 1 deletion(-)

diff --git a/src/cpu/intel/fit/Makefile.mk b/src/cpu/intel/fit/Makefile.mk
index 2729c0a6ae..1594f45a4e 100644
--- a/src/cpu/intel/fit/Makefile.mk
+++ b/src/cpu/intel/fit/Makefile.mk
@@ -16,6 +16,10 @@ intel_fit-align := 16
 ifeq ($(CONFIG_INTEL_TOP_SWAP_SEPARATE_REGIONS),y)
 regions-for-file-intel_fit = BOOTBLOCK
 regions-for-file-intel_fit_ts = TOPSWAP
+
+TS_MCU_REGION = COREBOOT_TS
+else
+TS_MCU_REGION = COREBOOT
 endif
 
 $(call add_intermediate, set_fit_ptr, $(IFITTOOL))
@@ -45,7 +49,7 @@ $(call add_intermediate, add_ts_mcu_fit, set_ts_fit_ptr $(IFITTOOL))
 ifneq ($(FIT_ENTRY),)
 	$(IFITTOOL) -f $< -A -n $(FIT_ENTRY) -t 1 -s $(CONFIG_CPU_INTEL_NUM_FIT_ENTRIES) $(TS_OPTIONS) -r $(TS_FIT_REGION)
 endif # FIT_ENTRY
-	$(IFITTOOL) -f $< -a -n cpu_microcode_blob.bin -t 1 -s $(CONFIG_CPU_INTEL_NUM_FIT_ENTRIES) $(TS_OPTIONS) -r $(TS_FIT_REGION) -R COREBOOT
+	$(IFITTOOL) -f $< -a -n cpu_microcode_blob.bin -t 1 -s $(CONFIG_CPU_INTEL_NUM_FIT_ENTRIES) $(TS_OPTIONS) -r $(TS_FIT_REGION) -R $(TS_MCU_REGION)
 
 cbfs-files-y += intel_fit_ts
 intel_fit_ts-file := fit_table.c:struct

From cbac0d7a257629e977a1d625c83e7a2a4b1a84bb Mon Sep 17 00:00:00 2001
From: Sergii Dmytruk <sergii.dmytruk@3mdeb.com>
Date: Tue, 9 Dec 2025 16:39:41 +0200
Subject: [PATCH 2882/3886] Makefile.mk,cpu/intel/fit/Makefile.mk: introduce
 CBFS_REGIONS
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Take advantage of cbfstool's ability to operate on multiple regions and
introduce a variable with a list of main CBFS regions: it's just
"COREBOOT" in most cases, but becomes "COREBOOT,COREBOOT_TS" when Top
Swap update mechanism is enabled (see [0]).

This is meant to simplify Makefiles by avoiding extra branches in
existing and future changes.

[0]: https://mail.coreboot.org/archives/list/coreboot@coreboot.org/thread/C6JN2PB7K7D67EG7OIKB6BBERZU5YV35/

Change-Id: If537d0d21a2867fafc2241ea9a0b4c0c6ca290a8
Signed-off-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90435
Reviewed-by: Filip Lewiński <filip.lewinski@3mdeb.com>
Reviewed-by: Filip Gołaś <filip.golas@3mdeb.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michał Kopeć <michal.kopec@3mdeb.com>
---
 Makefile.mk                   | 20 +++++++++++---------
 src/cpu/intel/fit/Makefile.mk |  5 +----
 2 files changed, 12 insertions(+), 13 deletions(-)

diff --git a/Makefile.mk b/Makefile.mk
index cab60b33a4..347ffc626f 100644
--- a/Makefile.mk
+++ b/Makefile.mk
@@ -974,21 +974,23 @@ $(objcbfs)/%.elf: $(objcbfs)/%.debug $(objcbfs)/%.map
 # 4) replace all '*' characters with spaces
 extract_nth=$(subst *,$(spc),$(patsubst -%-,%,$(word $(1), $(subst |,- -,-$(2)-))))
 
+CBFS_REGIONS := COREBOOT
+
+ifeq ($(CONFIG_INTEL_ADD_TOP_SWAP_BOOTBLOCK),y)
+ifneq ($(CONFIG_INTEL_TOP_SWAP_SEPARATE_REGIONS),y)
+TS_OPTIONS := -j $(CONFIG_INTEL_TOP_SWAP_BOOTBLOCK_SIZE)
+else
+CBFS_REGIONS := COREBOOT,COREBOOT_TS
+endif
+endif
+
 # regions-for-file - Returns a cbfstool regions parameter
 # $(call regions-for-file,$(filename))
 # returns "REGION1,REGION2,..."
 #
 # This is the default implementation. When using a boot strategy employing
 # multiple CBFSes in fmap regions, override it.
-regions-for-file ?= $(if $(value regions-for-file-$(1)), $(regions-for-file-$(1)), COREBOOT)
-
-ifeq ($(CONFIG_INTEL_ADD_TOP_SWAP_BOOTBLOCK),y)
-ifneq ($(CONFIG_INTEL_TOP_SWAP_SEPARATE_REGIONS),y)
-TS_OPTIONS := -j $(CONFIG_INTEL_TOP_SWAP_BOOTBLOCK_SIZE)
-else
-regions-for-file = $(if $(value regions-for-file-$(1)), $(regions-for-file-$(1)), COREBOOT,COREBOOT_TS)
-endif
-endif
+regions-for-file ?= $(if $(value regions-for-file-$(1)), $(regions-for-file-$(1)), $(CBFS_REGIONS))
 
 ifeq ($(CONFIG_CBFS_AUTOGEN_ATTRIBUTES),y)
 	cbfs-autogen-attributes=-g
diff --git a/src/cpu/intel/fit/Makefile.mk b/src/cpu/intel/fit/Makefile.mk
index 1594f45a4e..4a01449e4e 100644
--- a/src/cpu/intel/fit/Makefile.mk
+++ b/src/cpu/intel/fit/Makefile.mk
@@ -69,10 +69,7 @@ pbp.bin-type := raw
 
 $(call add_intermediate, add_pbp_fit, set_fit_ptr $(IFITTOOL))
 	@printf "    UPDATE-FIT Platform Boot Policy binary\n"
-	$(IFITTOOL) -f $< -a -n pbp.bin -t 4 -s $(CONFIG_CPU_INTEL_NUM_FIT_ENTRIES) -r COREBOOT
-ifeq ($(CONFIG_INTEL_TOP_SWAP_SEPARATE_REGIONS),y)
-	$(IFITTOOL) -f $< -a -n pbp.bin -t 4 -s $(CONFIG_CPU_INTEL_NUM_FIT_ENTRIES) -r COREBOOT_TS
-endif
+	$(IFITTOOL) -f $< -a -n pbp.bin -t 4 -s $(CONFIG_CPU_INTEL_NUM_FIT_ENTRIES) -r $(CBFS_REGIONS)
 
 endif # CONFIG_HAVE_PBP_BIN
 

From 739808011af70f0ad283ddc76b6ca88610521b4d Mon Sep 17 00:00:00 2001
From: Sergii Dmytruk <sergii.dmytruk@3mdeb.com>
Date: Tue, 9 Dec 2025 16:45:53 +0200
Subject: [PATCH 2883/3886] Makefile.mk: don't add bootblock after other files
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

This is a correction of CB:89570 (commit 04ea4724e2d0 ("Makefile.mk:
separate bootblocks into BOOTBLOCK and TOPSWAP")).  It wasn't obvious
that CBFS verification depends on bootblock being added first (otherwise
cbfstool considers CBFS verification to be disabled because anchor is
part of a bootblock).  Correct this and add a comment for anyone else
who might edit this code in the future.

The issue manifested itself in build failing to perform CBFS
verification via cbfstool when the firmware was built with
CBFS_VERIFICATION enabled.

Change-Id: If775480394270fc05206cde0707c511b126265d3
Signed-off-by: Filip Gołaś <filip.golas@3mdeb.com>
Signed-off-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90436
Reviewed-by: Filip Lewiński <filip.lewinski@3mdeb.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michał Kopeć <michal.kopec@3mdeb.com>
---
 Makefile.mk | 16 +++++++---------
 1 file changed, 7 insertions(+), 9 deletions(-)

diff --git a/Makefile.mk b/Makefile.mk
index 347ffc626f..3a20cffd62 100644
--- a/Makefile.mk
+++ b/Makefile.mk
@@ -1296,9 +1296,16 @@ $(shell rm -f $(obj)/coreboot.pre)
 ifneq ($(CONFIG_UPDATE_IMAGE),y)
 $(obj)/coreboot.pre: $$(prebuilt-files) $(CBFSTOOL) $(obj)/fmap.fmap $(obj)/fmap.desc $(objcbfs)/bootblock.bin
 	$(CBFSTOOL) $@.tmp create -M $(obj)/fmap.fmap -r $(shell cat $(obj)/fmap.desc)
+# The bootblock must exist in the image before we call `prebuild-files`,
+# otherwise their hashes won't be added into the CBFS header and CBFS
+# verification will fail.
 	printf "    BOOTBLOCK\n"
 ifneq ($(CONFIG_INTEL_TOP_SWAP_SEPARATE_REGIONS),y)
 	$(call add_bootblock,$@.tmp,$(objcbfs)/bootblock.bin)
+else
+	@printf "    PREP       place bootblocks in $(BB_FIT_REGION) and $(TS_FIT_REGION)\n"
+	@printf "    $(BB_FIT_REGION),$(TS_FIT_REGION)\n"
+	$(CBFSTOOL) $@.tmp add -r $(BB_FIT_REGION),$(TS_FIT_REGION) $(bootblock_add_params)
 endif # ifneq ($(CONFIG_INTEL_TOP_SWAP_SEPARATE_REGIONS),y)
 	$(prebuild-files) true
 	mv $@.tmp $@
@@ -1329,15 +1336,6 @@ add_intermediate = \
 	$(1): $(obj)/coreboot.pre $(2) | $(INTERMEDIATE) \
 	$(eval INTERMEDIATE+=$(1)) $(eval PHONY+=$(1))
 
-ifeq ($(CONFIG_INTEL_TOP_SWAP_SEPARATE_REGIONS),y)
-$(call add_intermediate, prep_bb_regions, $(CBFSTOOL))
-	@printf "    PREP       place bootblocks in BOOTBLOCK and TOPSWAP\n"
-	@printf "    BOOTBLOCK\n"
-	$(CBFSTOOL) $< add -r $(BB_FIT_REGION) $(bootblock_add_params)
-	@printf "    TOPSWAP\n"
-	$(CBFSTOOL) $< add -r $(TS_FIT_REGION) $(bootblock_add_params)
-endif
-
 $(obj)/coreboot.rom: $(obj)/coreboot.pre $(CBFSTOOL) $(IFITTOOL) $$(INTERMEDIATE)
 	@printf "    CBFS       $(subst $(obj)/,,$(@))\n"
 # The full ROM may be larger than the CBFS part, so create an empty

From 7c7feca2588271c7fa4e3bd33e23eacab80ba2c5 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Filip=20Go=C5=82a=C5=9B?= <filip.golas@3mdeb.com>
Date: Wed, 10 Dec 2025 16:44:24 +0200
Subject: [PATCH 2884/3886] CBFS verification: support Top Swap redundancy
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Separating the bootblock into two copies (in BOOTBLOCK and TOPSWAP fmap
regions) breaks the CBFS verification as TSPI CRTM knows nothing about
the new regions and looks for bootblock in a hard-coded COREBOOT fmap
region.

Introduce and use cbfs_unverified_area_type_alloc() which is an
extension of cbfs_unverified_area_alloc(), very similar to how
cbfs_ro_type_map() is an extension of cbfs_ro_map().  This allows to
specify a region of the bootblock file and skip verification because
bootblock serves as a container of hashes and is not verified itself.

The branching is done on the state of RTC BUC to always use the current
bootblock.  Somewhat confusingly, the measurement always uses BOOTBLOCK
region because with active Top Swap that's the way to access a
memory-mapped TOPSWAP region.

Makefile.mk now verifies both COREBOOT and COREBOOT_TS regions.
cbfstool needed a few updates as well:
 - recognize both "BOOTBLOCK" and "TOPSWAP" regions
 - recognize both "COREBOOT" and "COREBOOT_TS" regions
 - reset metadata cache before processing each region as cache may now
   be invalid

SMM doesn't link with vboot functions, so cbfs_file_hash_mismatch() has
to skip verification in SMM due to the use of CMOS options backend.

This is a part of the bootblock redundancy feature proposed
on the mailing list:
https://mail.coreboot.org/archives/list/coreboot@coreboot.org/thread/C6JN2PB7K7D67EG7OIKB6BBERZU5YV35/

Tested by successfully booting into Protectli VP6670 with Top Swap and
CBFS Verification features enabled and Top Swap state being toggled.

Change-Id: Ia75e714ae84d8c0ae09b27495e3056313b109999
Signed-off-by: Filip Gołaś <filip.golas@3mdeb.com>
Signed-off-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89691
Reviewed-by: Michał Kopeć <michal.kopec@3mdeb.com>
Reviewed-by: Filip Lewiński <filip.lewinski@3mdeb.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 Makefile.mk                     |  6 ++++--
 src/include/cbfs.h              | 18 +++++++++++-----
 src/lib/cbfs.c                  | 21 ++++++++++++++++--
 src/security/tpm/tspi/crtm.c    | 27 ++++++++++++++++++++++-
 util/cbfstool/cbfs_sections.h   |  2 ++
 util/cbfstool/cbfstool.c        | 38 ++++++++++++++++++++++++---------
 util/cbfstool/platform_fixups.c |  6 ++++--
 7 files changed, 96 insertions(+), 22 deletions(-)

diff --git a/Makefile.mk b/Makefile.mk
index 3a20cffd62..a823a115a4 100644
--- a/Makefile.mk
+++ b/Makefile.mk
@@ -984,6 +984,8 @@ CBFS_REGIONS := COREBOOT,COREBOOT_TS
 endif
 endif
 
+CBFS_REGION_COUNT := $(words $(subst $(comma),$(spc),$(CBFS_REGIONS)))
+
 # regions-for-file - Returns a cbfstool regions parameter
 # $(call regions-for-file,$(filename))
 # returns "REGION1,REGION2,..."
@@ -1356,8 +1358,8 @@ endif # CONFIG_CPU_INTEL_FIRMWARE_INTERFACE_TABLE
 	$(CBFSTOOL) $@ layout
 	@printf "    CBFSPRINT  $(subst $(obj)/,,$(@))\n\n"
 ifeq ($(CONFIG_CBFS_VERIFICATION),y)
-	line=$$($(CBFSTOOL) $@ print -kv 2>/dev/null | grep -F '[CBFS VERIFICATION (COREBOOT)]') ;\
-	if ! printf "$$line" | grep -q 'fully valid'; then \
+	line=$$($(CBFSTOOL) $@ print -kv -r $(CBFS_REGIONS) 2>/dev/null | grep -F '[CBFS VERIFICATION') ;\
+	if [ "$$(printf "$$line" | grep -c 'fully valid')" -ne $(CBFS_REGION_COUNT) ]; then \
 		echo "CBFS verification error: $$line" ;\
 		exit 1 ;\
 	fi
diff --git a/src/include/cbfs.h b/src/include/cbfs.h
index 27a285e51d..f7067f9009 100644
--- a/src/include/cbfs.h
+++ b/src/include/cbfs.h
@@ -201,7 +201,8 @@ void *_cbfs_alloc(const char *name, cbfs_allocator_t allocator, void *arg,
 		  size_t *size_out, bool force_ro, enum cbfs_type *type);
 
 void *_cbfs_unverified_area_alloc(const char *area, const char *name,
-				  cbfs_allocator_t allocator, void *arg, size_t *size_out);
+				  cbfs_allocator_t allocator, void *arg, size_t *size_out,
+				  enum cbfs_type *type);
 
 struct _cbfs_default_allocator_arg {
 	void *buf;
@@ -242,7 +243,14 @@ static inline void *cbfs_unverified_area_alloc(const char *area, const char *nam
 					       cbfs_allocator_t allocator, void *arg,
 					       size_t *size_out)
 {
-	return _cbfs_unverified_area_alloc(area, name, allocator, arg, size_out);
+	return _cbfs_unverified_area_alloc(area, name, allocator, arg, size_out, NULL);
+}
+
+static inline void *cbfs_unverified_area_type_alloc(const char *area, const char *name,
+						    cbfs_allocator_t allocator, void *arg,
+						    size_t *size_out, enum cbfs_type *type)
+{
+	return _cbfs_unverified_area_alloc(area, name, allocator, arg, size_out, type);
 }
 
 static inline void *cbfs_map(const char *name, size_t *size_out)
@@ -268,7 +276,7 @@ static inline void *cbfs_ro_type_map(const char *name, size_t *size_out, enum cb
 static inline void *cbfs_unverified_area_map(const char *area, const char *name,
 					     size_t *size_out)
 {
-	return _cbfs_unverified_area_alloc(area, name, NULL, NULL, size_out);
+	return _cbfs_unverified_area_alloc(area, name, NULL, NULL, size_out, NULL);
 }
 
 static inline size_t _cbfs_load(const char *name, void *buf, size_t size, bool force_ro,
@@ -307,7 +315,7 @@ static inline size_t cbfs_unverified_area_load(const char *area, const char *nam
 					       void *buf, size_t size)
 {
 	struct _cbfs_default_allocator_arg arg = { .buf = buf, .buf_size = size };
-	if (_cbfs_unverified_area_alloc(area, name, _cbfs_default_allocator, &arg, &size))
+	if (_cbfs_unverified_area_alloc(area, name, _cbfs_default_allocator, &arg, &size, NULL))
 		return size;
 	else
 		return 0;
@@ -341,7 +349,7 @@ static inline void *cbfs_unverified_area_cbmem_alloc(const char *area, const cha
 						     uint32_t cbmem_id, size_t *size_out)
 {
 	return _cbfs_unverified_area_alloc(area, name, _cbfs_cbmem_allocator,
-					   (void *)(uintptr_t)cbmem_id, size_out);
+					   (void *)(uintptr_t)cbmem_id, size_out, NULL);
 }
 
 static inline size_t cbfs_get_size(const char *name)
diff --git a/src/lib/cbfs.c b/src/lib/cbfs.c
index 1dd9288bff..0c602474b3 100644
--- a/src/lib/cbfs.c
+++ b/src/lib/cbfs.c
@@ -173,7 +173,12 @@ static bool cbfs_file_hash_mismatch(const void *buffer, size_t size,
 
 	const struct vb2_hash *hash = NULL;
 
-	if (CONFIG(CBFS_VERIFICATION) && !skip_verification) {
+	/*
+	 * Skipping this block in SMM because vboot library isn't linked to SMM stage.  This is
+	 * an issue only if using a CMOS options backend, then SMM refers to an option and tries
+	 * to verify cmos.layout here.
+	 */
+	if (CONFIG(CBFS_VERIFICATION) && !ENV_SMM && !skip_verification) {
 		hash = cbfs_file_hash(mdata);
 		if (!hash) {
 			ERROR("'%s' does not have a file hash!\n", mdata->h.filename);
@@ -546,7 +551,8 @@ void *_cbfs_alloc(const char *name, cbfs_allocator_t allocator, void *arg,
 }
 
 void *_cbfs_unverified_area_alloc(const char *area, const char *name,
-				  cbfs_allocator_t allocator, void *arg, size_t *size_out)
+				  cbfs_allocator_t allocator, void *arg, size_t *size_out,
+				  enum cbfs_type *type)
 {
 	struct region_device area_rdev, file_rdev;
 	union cbfs_mdata mdata;
@@ -562,6 +568,17 @@ void *_cbfs_unverified_area_alloc(const char *area, const char *name,
 		return NULL;
 	}
 
+	if (type) {
+		const enum cbfs_type real_type = be32toh(mdata.h.type);
+		if (*type == CBFS_TYPE_QUERY)
+			*type = real_type;
+		else if (*type != real_type) {
+			ERROR("'%s' type mismatch (is %u, expected %u)\n",
+			      mdata.h.filename, real_type, *type);
+			return NULL;
+		}
+	}
+
 	if (rdev_chain(&file_rdev, &area_rdev, data_offset, be32toh(mdata.h.len)))
 		return NULL;
 
diff --git a/src/security/tpm/tspi/crtm.c b/src/security/tpm/tspi/crtm.c
index 4e0a9b727a..def2fc3513 100644
--- a/src/security/tpm/tspi/crtm.c
+++ b/src/security/tpm/tspi/crtm.c
@@ -9,6 +9,10 @@
 #include <stdio.h>
 #include <string.h>
 
+/* This include is available as <intelblocks/rtc.h> only if CONFIG_SOC_INTEL_COMMON_BLOCK is
+   set, which is not guaranteed for this file. */
+#include <soc/intel/common/block/include/intelblocks/rtc.h>
+
 static int tpm_log_initialized;
 static inline int tpm_log_available(void)
 {
@@ -72,7 +76,28 @@ static tpm_result_t tspi_init_crtm(void)
 		/* Mapping measures the file. We know we can safely map here because
 		   bootblock-as-a-file is only used on x86, where we don't need cache to map. */
 		enum cbfs_type type = CBFS_TYPE_BOOTBLOCK;
-		void *mapping = cbfs_ro_type_map("bootblock", NULL, &type);
+		void *mapping = NULL;
+
+		if (CONFIG(INTEL_TOP_SWAP_SEPARATE_REGIONS)) {
+			enum ts_config top_swap = get_rtc_buc_top_swap_status();
+			if (top_swap == TS_ENABLE)
+				printk(BIOS_INFO,
+				       "CRTM Top Swap: Measuring bootblock in TOPSWAP (will be logged as BOOTBLOCK).\n");
+			else
+				printk(BIOS_INFO,
+				       "CRTM Top Swap: Measuring bootblock in BOOTBLOCK.\n");
+
+			/*
+			 * Whether Top Swap is active or not, FMAP always refers to the same
+			 * memory ranges but the contents of BOOTBLOCK and TOPSWAP are swapped.
+			 * Hence always using BOOTBLOCK region to access the active bootblock.
+			 */
+			mapping = cbfs_unverified_area_type_alloc("BOOTBLOCK", "bootblock",
+								  NULL, NULL, NULL, &type);
+		} else {
+			mapping = cbfs_ro_type_map("bootblock", NULL, &type);
+		}
+
 		if (!mapping) {
 			printk(BIOS_INFO,
 			       "TSPI: Couldn't measure bootblock into CRTM!\n");
diff --git a/util/cbfstool/cbfs_sections.h b/util/cbfstool/cbfs_sections.h
index 99a4761b64..c3479bbfd2 100644
--- a/util/cbfstool/cbfs_sections.h
+++ b/util/cbfstool/cbfs_sections.h
@@ -10,7 +10,9 @@
 
 #define SECTION_NAME_FMAP		"FMAP"
 #define SECTION_NAME_PRIMARY_CBFS	"COREBOOT"
+#define SECTION_NAME_TOPSWAP_CBFS	"COREBOOT_TS"
 #define SECTION_NAME_BOOTBLOCK		"BOOTBLOCK"
+#define SECTION_NAME_TOPSWAP		"TOPSWAP"
 
 #define SECTION_ANNOTATION_CBFS		"CBFS"
 
diff --git a/util/cbfstool/cbfstool.c b/util/cbfstool/cbfstool.c
index 5555b57364..68dbd32984 100644
--- a/util/cbfstool/cbfstool.c
+++ b/util/cbfstool/cbfstool.c
@@ -135,6 +135,18 @@ struct mh_cache {
 	bool initialized;
 };
 
+static bool is_main_cbfs_region(const char *region_name)
+{
+	return strcmp(region_name, SECTION_NAME_PRIMARY_CBFS) == 0 ||
+		strcmp(region_name, SECTION_NAME_TOPSWAP_CBFS) == 0;
+}
+
+static bool is_topswap_region(const char *region_name)
+{
+	return strcmp(region_name, SECTION_NAME_TOPSWAP_CBFS) == 0 ||
+		strcmp(region_name, SECTION_NAME_TOPSWAP) == 0;
+}
+
 static struct mh_cache *get_mh_cache(void)
 {
 	static struct mh_cache mhc;
@@ -148,22 +160,24 @@ static struct mh_cache *get_mh_cache(void)
 	if (!fmap)
 		goto no_metadata_hash;
 
+	const char *bootblock_region = SECTION_NAME_BOOTBLOCK;
+	if (is_topswap_region(param.region_name))
+		bootblock_region = SECTION_NAME_TOPSWAP;
+
 	/* Find the metadata_hash container. If there is a "BOOTBLOCK" FMAP section, it's
 	   there. If not, it's a normal file in the primary CBFS section. */
 	size_t offset, size;
 	struct buffer buffer;
-	if (fmap_find_area(fmap, SECTION_NAME_BOOTBLOCK)) {
-		if (!partitioned_file_read_region(&buffer, param.image_file,
-						  SECTION_NAME_BOOTBLOCK))
+	if (fmap_find_area(fmap, bootblock_region)) {
+		if (!partitioned_file_read_region(&buffer, param.image_file, bootblock_region))
 			goto no_metadata_hash;
-		mhc.region = SECTION_NAME_BOOTBLOCK;
+		mhc.region = bootblock_region;
 		offset = 0;
 		size = buffer.size;
 	} else {
 		struct cbfs_image cbfs;
 		struct cbfs_file *mh_container;
-		if (!partitioned_file_read_region(&buffer, param.image_file,
-						  SECTION_NAME_PRIMARY_CBFS))
+		if (!partitioned_file_read_region(&buffer, param.image_file, SECTION_NAME_PRIMARY_CBFS))
 			goto no_metadata_hash;
 		mhc.region = SECTION_NAME_PRIMARY_CBFS;
 		if (cbfs_image_from_buffer(&cbfs, &buffer, param.headeroffset))
@@ -245,7 +259,7 @@ static int update_anchor(struct mh_cache *mhc, uint8_t *fmap_hash)
    will recalculate and update the metadata hash in the bootblock if needed. */
 static int maybe_update_metadata_hash(struct cbfs_image *cbfs)
 {
-	if (strcmp(param.region_name, SECTION_NAME_PRIMARY_CBFS))
+	if (!is_main_cbfs_region(param.region_name))
 		return 0;  /* Metadata hash only embedded in primary CBFS. */
 
 	struct mh_cache *mhc = get_mh_cache();
@@ -268,6 +282,7 @@ static int maybe_update_metadata_hash(struct cbfs_image *cbfs)
 static int maybe_update_fmap_hash(void)
 {
 	if (strcmp(param.region_name, SECTION_NAME_BOOTBLOCK) &&
+	    strcmp(param.region_name, SECTION_NAME_TOPSWAP) &&
 	    strcmp(param.region_name, SECTION_NAME_FMAP) &&
 	    param.type != CBFS_TYPE_BOOTBLOCK &&
 	    param.type != CBFS_TYPE_AMDFW)
@@ -1603,7 +1618,7 @@ static int cbfs_print(void)
 				vb2_digest_size(real_hash.algo));
 		printf("[METADATA HASH]\t%s:%s",
 		       vb2_get_hash_algorithm_name(real_hash.algo), hash_str);
-		if (!strcmp(param.region_name, SECTION_NAME_PRIMARY_CBFS)) {
+		if (is_main_cbfs_region(param.region_name)) {
 			if (!memcmp(mhc->cbfs_hash.raw, real_hash.raw,
 				    vb2_digest_size(real_hash.algo))) {
 				printf(":valid");
@@ -2364,6 +2379,10 @@ int main(int argc, char **argv)
 		strcpy(region_name_scratch, param.region_name);
 		param.region_name = strtok(region_name_scratch, ",");
 		for (unsigned region = 0; region < num_regions; ++region) {
+			// Reset metadata cache in case region uses anchor from a different
+			// location.
+			get_mh_cache()->initialized = false;
+
 			if (!param.region_name) {
 				ERROR("Encountered illegal degenerate region name in -r list\n");
 				ERROR("The image will be left unmodified.\n");
@@ -2371,8 +2390,7 @@ int main(int argc, char **argv)
 				return 1;
 			}
 
-			if (strcmp(param.region_name, SECTION_NAME_PRIMARY_CBFS)
-									== 0)
+			if (is_main_cbfs_region(param.region_name))
 				seen_primary_cbfs = true;
 
 			param.image_region = image_regions + region;
diff --git a/util/cbfstool/platform_fixups.c b/util/cbfstool/platform_fixups.c
index 7e29cd7e2b..97fdd2e15b 100644
--- a/util/cbfstool/platform_fixups.c
+++ b/util/cbfstool/platform_fixups.c
@@ -312,12 +312,14 @@ static int mediatek_fixup(struct buffer *buffer, unused size_t offset)
 platform_fixup_func platform_fixups_probe(struct buffer *buffer, size_t offset,
 					  const char *region_name)
 {
-	if (!strcmp(region_name, SECTION_NAME_BOOTBLOCK)) {
+	if (!strcmp(region_name, SECTION_NAME_BOOTBLOCK) ||
+	    !strcmp(region_name, SECTION_NAME_TOPSWAP)) {
 		if (qualcomm_probe(buffer, offset))
 			return qualcomm_fixup;
 		else if (mediatek_probe(buffer))
 			return mediatek_fixup;
-	} else if (!strcmp(region_name, SECTION_NAME_PRIMARY_CBFS)) {
+	} else if (!strcmp(region_name, SECTION_NAME_PRIMARY_CBFS) ||
+		   !strcmp(region_name, SECTION_NAME_TOPSWAP_CBFS)) {
 		/* TODO: add fixups for primary CBFS bootblock platforms, if needed */
 	} else {
 		ERROR("%s called for unexpected FMAP region %s!\n", __func__, region_name);

From 56a7ae4389d201f69377740fa0858748d684f5f7 Mon Sep 17 00:00:00 2001
From: Jarried Lin <jarried.lin@mediatek.corp-partner.google.com>
Date: Thu, 18 Dec 2025 14:24:31 +0800
Subject: [PATCH 2885/3886] soc/mediatek/mt8196: Notify MCUPM to support MTE

Before CPU resume, it is necessary to reinitialize the MTE-related
settings of booker in MCUPM to prevent the loss of booker
configurations after resume.

BUG=b:467186613
TEST=Build pass, Verify S/R OK on Navi and Sapphire.

Change-Id: Ieaf4c2ea0f8a5c372a5dbf4d0f6c44fbd978e6a6
Signed-off-by: Jarried Lin <jarried.lin@mediatek.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90546
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
---
 src/soc/mediatek/mt8196/booker.c                 | 4 ++++
 src/soc/mediatek/mt8196/include/soc/mcupm_plat.h | 1 +
 2 files changed, 5 insertions(+)

diff --git a/src/soc/mediatek/mt8196/booker.c b/src/soc/mediatek/mt8196/booker.c
index 13a0248653..2525043f5f 100644
--- a/src/soc/mediatek/mt8196/booker.c
+++ b/src/soc/mediatek/mt8196/booker.c
@@ -4,6 +4,7 @@
 #include <device/mmio.h>
 #include <soc/addressmap.h>
 #include <soc/booker.h>
+#include <soc/mcupm_plat.h>
 
 #define REG_READ_ONLY_HASH_VALUE	(MCUCFG_BASE + 0x059C)
 #define REG_MCUSYS_RESERVED_REG2	(MCUCFG_BASE + 0xFFE8)
@@ -61,6 +62,9 @@ void booker_mte_init(uint64_t mte_tag_addr)
 {
 	int i;
 
+	/* Notify MCUPM to configure MTE on resume path. */
+	setbits32p(MTE_ENABLE_REG, 0xF);
+
 	printk(BIOS_DEBUG, "%s: MTE tag addr %#llx\n", __func__, mte_tag_addr);
 
 	/* Setting MTU TAG */
diff --git a/src/soc/mediatek/mt8196/include/soc/mcupm_plat.h b/src/soc/mediatek/mt8196/include/soc/mcupm_plat.h
index 6ce58e4799..37d62c96df 100644
--- a/src/soc/mediatek/mt8196/include/soc/mcupm_plat.h
+++ b/src/soc/mediatek/mt8196/include/soc/mcupm_plat.h
@@ -92,5 +92,6 @@
 
 #define ABNORMALBOOT_REG			GPR_BASE_ADDR_MCU(1)
 #define WARMBOOT_REG				GPR_BASE_ADDR_MCU(23)
+#define MTE_ENABLE_REG				GPR_BASE_ADDR_MCU(25)
 
 #endif /* __SOC_MEDIATEK_MT8196_INCLUDE_SOC_MCUPM_PLAT_H__ */

From 7e7ba6fb11d4d8d241116d12eb5215854294ac40 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Filip=20Lewi=C5=84ski?= <filip.lewinski@3mdeb.com>
Date: Mon, 8 Dec 2025 14:39:57 +0100
Subject: [PATCH 2886/3886] security/lockdown/lockdown.c: option to lock
 COREBOOT and BOOTBLOCK
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Add an option to lock the regions BOOTBLOCK and COREBOOT, leaving the
regions TOPSWAP and COREBOOT_TS for updates in an Intel Top Swap
redundancy scenario.

This means that the user can now write and choose to boot from the
update regions, selecting the attempt_slot_b CMOS option, and there is
a protected golden copy of the entire firmware, that cannot be
overwritten and can be reverted to by resetting CMOS.

This is part of an ongoing implementation of a redundancy feature
proposed on the mailing list:
https://mail.coreboot.org/archives/list/coreboot@coreboot.org/thread/C6JN2PB7K7D67EG7OIKB6BBERZU5YV35/

Change-Id: Ia6dea22c41e2fc778af6ca7049b72c92686ec85f
Signed-off-by: Filip Lewiński <filip.lewinski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90413
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com>
---
 src/security/lockdown/Kconfig       | 12 ++++++++++++
 src/security/lockdown/lockdown.c    | 20 ++++++++++++++++++++
 src/soc/intel/common/Kconfig.common | 14 ++++++++++++++
 3 files changed, 46 insertions(+)

diff --git a/src/security/lockdown/Kconfig b/src/security/lockdown/Kconfig
index 8de7979904..95a768a148 100644
--- a/src/security/lockdown/Kconfig
+++ b/src/security/lockdown/Kconfig
@@ -73,6 +73,18 @@ config BOOTMEDIA_LOCK_WPRO_VBOOT_RO
 	  is either triggered by coreboot (when INTEL_CHIPSET_LOCKDOWN is set) or
 	  has to be triggered later (e.g. by the payload or the OS).
 
+config BOOTMEDIA_LOCK_TOPSWAP
+	bool "Write-protect the COREBOOT & BOOTBLOCK regions"
+	depends on TOP_SWAP_REDUNDANCY
+	depends on BOOTMEDIA_LOCK_CONTROLLER
+	help
+	  Select this if you want to write-protect the BOOTBLOCK and COREBOOT
+	  (Slot A) regions as specified in the Top Swap FMAP. You will be able to
+	  write to the TOPSWAP and COREBOOT_TS (Slot B) regions and set the
+	  attempt_slot_b CMOS option to run updated firmware. The BOOTBLOCK and
+	  COREBOOT regions will remain a read-only golden copy, which you can
+	  then revert to by resetting CMOS.
+
 endchoice
 
 config BOOTMEDIA_LOCK_IN_VERSTAGE
diff --git a/src/security/lockdown/lockdown.c b/src/security/lockdown/lockdown.c
index c2e2ac3501..6a75111f6b 100644
--- a/src/security/lockdown/lockdown.c
+++ b/src/security/lockdown/lockdown.c
@@ -27,6 +27,9 @@ void boot_device_security_lockdown(void)
 		} else if (CONFIG(BOOTMEDIA_LOCK_WPRO_VBOOT_RO)) {
 			printk(BIOS_DEBUG, "'WP_RO only'");
 			lock_type = CTRLR_WP;
+		} else if (CONFIG(BOOTMEDIA_LOCK_TOPSWAP)) {
+			printk(BIOS_DEBUG, "'COREBOOT + BOOTBLOCK'");
+			lock_type = CTRLR_WP;
 		}
 		printk(BIOS_DEBUG, " using CTRL...\n");
 	} else {
@@ -45,6 +48,11 @@ void boot_device_security_lockdown(void)
 			printk(BIOS_ERR, "BM-LOCKDOWN: Could not find region 'WP_RO'\n");
 		else
 			rdev = &dev;
+	} else if (CONFIG(BOOTMEDIA_LOCK_TOPSWAP)) {
+		if (fmap_locate_area_as_rdev("COREBOOT", &dev) < 0)
+			printk(BIOS_ERR, "BM-LOCKDOWN: Could not find region 'COREBOOT'\n");
+		else
+			rdev = &dev;
 	} else {
 		rdev = boot_device_ro();
 	}
@@ -53,6 +61,18 @@ void boot_device_security_lockdown(void)
 		printk(BIOS_INFO, "BM-LOCKDOWN: Enabled bootmedia protection\n");
 	else
 		printk(BIOS_ERR, "BM-LOCKDOWN: Failed to enable bootmedia protection\n");
+
+	if (CONFIG(BOOTMEDIA_LOCK_TOPSWAP)) {
+		/*
+		 * Additionally set a protected range for the BOOTBLOCK region
+		 */
+		if (fmap_locate_area_as_rdev("BOOTBLOCK", &dev) < 0)
+			printk(BIOS_ERR, "BM-LOCKDOWN: Could not find region 'BOOTBLOCK'\n");
+		else if (boot_device_wp_region(&dev, lock_type) >= 0)
+			printk(BIOS_INFO, "BM-LOCKDOWN: Enabled bootmedia protection for BOOTBLOCK\n");
+		else
+			printk(BIOS_ERR, "BM-LOCKDOWN: Failed to enable bootmedia protection for BOOTBLOCK\n");
+	}
 }
 
 static void lock(void *unused)
diff --git a/src/soc/intel/common/Kconfig.common b/src/soc/intel/common/Kconfig.common
index 964a564303..a1a2f39cfb 100644
--- a/src/soc/intel/common/Kconfig.common
+++ b/src/soc/intel/common/Kconfig.common
@@ -66,6 +66,20 @@ config INTEL_TOP_SWAP_OPTION_CONTROL
 	  option. Note that the option must be present in the board's cmos.layout.
 	  file.
 
+config TOP_SWAP_REDUNDANCY
+	bool "Toggle the Intel Top Swap - based redundancy"
+	depends on HAVE_OPTION_TABLE && INTEL_HAS_TOP_SWAP
+	select INTEL_ADD_TOP_SWAP_BOOTBLOCK
+	select MAINBOARD_NEEDS_CMOS_OPTIONS
+	select INTEL_TOP_SWAP_SEPARATE_REGIONS
+	select INTEL_TOP_SWAP_OPTION_CONTROL
+	help
+	  Toggle the Intel Top Swap based redundancy, where the BOOTBLOCK and COREBOOT
+	  regions form a read-only golden copy and TOPSWAP and COREBOOT_TS are an
+	  update partition. CMOS option "attempt_top_swap" decides which of the slots
+	  gets booted, which means the platform can be reverted to the known-good copy
+	  via CMOS reset.
+
 endif
 
 config SOC_INTEL_COMMON

From 003ea8511527967dd2a5beeb50d9761b904cf5ad Mon Sep 17 00:00:00 2001
From: Yidi Lin <yidilin@google.com>
Date: Mon, 15 Dec 2025 21:10:06 +0800
Subject: [PATCH 2887/3886] soc/mediatek/mt8196: Support logo display on
 DISP_PATH_DUAL_MIPI path

The mtk_ddp_ovlsys_start function is updated to take edid and path
as arguments. This allows the function to configure the framebuffer
address and overlay for DISP_PATH_DUAL_MIPI path.

BUG=b:319511268
TEST=cherry pick CB:90504 and manual enable BMP_LOGO related configs.
     The logo is drawn in the ramstage.

Change-Id: I60809f7062907617f2af1badcad9f53477911020
Signed-off-by: Yidi Lin <yidilin@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90537
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Chen-Tsung Hsieh <chentsung@google.com>
---
 src/soc/mediatek/common/display.c             |  7 ++++---
 src/soc/mediatek/common/include/soc/display.h |  3 ++-
 src/soc/mediatek/mt8196/ddp.c                 | 14 +++++++++++++-
 3 files changed, 19 insertions(+), 5 deletions(-)

diff --git a/src/soc/mediatek/common/display.c b/src/soc/mediatek/common/display.c
index d1880e4299..1f7277a0e6 100644
--- a/src/soc/mediatek/common/display.c
+++ b/src/soc/mediatek/common/display.c
@@ -78,7 +78,8 @@ static void panel_configure_backlight(struct panel_description *panel,
 
 static void display_logo(struct panel_description *panel,
 			 uintptr_t fb_addr,
-			 const struct edid *edid)
+			 const struct edid *edid,
+			 enum disp_path_sel path)
 {
 	memset((void *)fb_addr, 0, edid->bytes_per_line * edid->y_resolution);
 
@@ -90,7 +91,7 @@ static void display_logo(struct panel_description *panel,
 	};
 	render_logo_to_framebuffer(&config);
 
-	mtk_ddp_ovlsys_start(fb_addr);
+	mtk_ddp_ovlsys_start(fb_addr, edid, path);
 
 	panel_configure_backlight(panel, true);
 }
@@ -209,7 +210,7 @@ int mtk_display_init(void)
 		fb_set_dual_pipe_flag(info, true);
 
 	if (CONFIG(BMP_LOGO))
-		display_logo(panel, fb_addr, &edid);
+		display_logo(panel, fb_addr, &edid, panel->disp_path);
 
 	return 0;
 }
diff --git a/src/soc/mediatek/common/include/soc/display.h b/src/soc/mediatek/common/include/soc/display.h
index ca8782280e..c71d15bb66 100644
--- a/src/soc/mediatek/common/include/soc/display.h
+++ b/src/soc/mediatek/common/include/soc/display.h
@@ -37,6 +37,7 @@ void mtk_ddp_soc_mode_set(u32 fmt, u32 bpp, u32 width, u32 height, u32 vrefresh,
 			  enum disp_path_sel path, struct dsc_config *dsc_config);
 void mtk_ddp_mode_set(const struct edid *edid, enum disp_path_sel path,
 		      struct dsc_config *dsc_config);
-void mtk_ddp_ovlsys_start(uintptr_t fb_addr);
+void mtk_ddp_ovlsys_start(uintptr_t fb_addr, const struct edid *edid,
+			  enum disp_path_sel path);
 
 #endif
diff --git a/src/soc/mediatek/mt8196/ddp.c b/src/soc/mediatek/mt8196/ddp.c
index ba317d4e79..012c6c9b3b 100644
--- a/src/soc/mediatek/mt8196/ddp.c
+++ b/src/soc/mediatek/mt8196/ddp.c
@@ -695,10 +695,22 @@ void mtk_ddp_soc_mode_set(u32 fmt, u32 bpp, u32 width, u32 height, u32 vrefresh,
 	ovlsys_layer_config(fmt, bpp, width, height, path);
 }
 
-void mtk_ddp_ovlsys_start(uintptr_t fb_addr)
+void mtk_ddp_ovlsys_start(uintptr_t fb_addr, const struct edid *edid,
+			  enum disp_path_sel path)
 {
+	uint32_t offset;
+
 	write32(&ovl_exdma2_reg->ovl_addr, fb_addr);
 	setbits32(&ovl_exdma2_reg->ovl_en, BIT(0));
 	setbits32(&ovl_exdma2_reg->ovl_l_en, BIT(0));
 	setbits32(&ovl_blenders[0]->bld_l_en, BIT(0));
+
+	if (!DUAL_PIPE(path))
+		return;
+
+	offset = edid->x_resolution * edid->framebuffer_bits_per_pixel / 8 / 2;
+	write32(&ovl1_exdma2_reg->ovl_addr, fb_addr + offset);
+	setbits32(&ovl1_exdma2_reg->ovl_en, BIT(0));
+	setbits32(&ovl1_exdma2_reg->ovl_l_en, BIT(0));
+	setbits32(&ovl1_blenders[0]->bld_l_en, BIT(0));
 }

From 0e217cf1d3ebfea1b17782867775e37cd5689def Mon Sep 17 00:00:00 2001
From: Yidi Lin <yidilin@google.com>
Date: Thu, 18 Dec 2025 20:17:19 +0800
Subject: [PATCH 2888/3886] soc/mediatek/mt8196: Increase FRAMEBUFFER to 32MiB

Increase FRAMEBUFFER from 24MiB to 32MiB to support UHD display panel.

BUG=b:319511268
TEST=emerge-tanjiro coreboot

Change-Id: Ib9cf14328d1b5d56246d4cc1ecfd3613af008d00
Signed-off-by: Yidi Lin <yidilin@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90549
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Chen-Tsung Hsieh <chentsung@google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
---
 src/soc/mediatek/mt8196/include/soc/memlayout.ld | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/soc/mediatek/mt8196/include/soc/memlayout.ld b/src/soc/mediatek/mt8196/include/soc/memlayout.ld
index 8c64d661db..2bd3a26b71 100644
--- a/src/soc/mediatek/mt8196/include/soc/memlayout.ld
+++ b/src/soc/mediatek/mt8196/include/soc/memlayout.ld
@@ -73,5 +73,5 @@ SECTIONS
 	RESV_MEMORY_GPUEB(0xA0000000, 2M)
 	/* Reserved memory for the dedicated secured memory allocator of GPU Mali firmware */
 	GPU_SEC_BUF(0xA2000000, 16M)
-	FRAMEBUFFER(0xBEC00000, 24M)
+	FRAMEBUFFER(0xBEC00000, 32M)
 }

From ac170631d56f8632f713d1d9f0e7867a03f4add3 Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Wed, 10 Dec 2025 08:38:50 +0000
Subject: [PATCH 2889/3886] mb/starlabs/starlite: Fix ddr5 entry

This fixes the duplicate ddr6 entry which should have been ddr5.

Change-Id: I3bbee8a2fbacc7fa057e225fcfe307877b4f2716
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90442
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
---
 src/mainboard/starlabs/starlite_adl/variants/mk_v/romstage.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/mainboard/starlabs/starlite_adl/variants/mk_v/romstage.c b/src/mainboard/starlabs/starlite_adl/variants/mk_v/romstage.c
index 235a8b4565..13c31ea809 100644
--- a/src/mainboard/starlabs/starlite_adl/variants/mk_v/romstage.c
+++ b/src/mainboard/starlabs/starlite_adl/variants/mk_v/romstage.c
@@ -31,7 +31,7 @@ void mainboard_memory_init_params(FSPM_UPD *mupd)
 				.dq0	= {	3,	2,	1,	0,	7,	4,	6,	5	},
 				.dq1	= {	8,	10,	11,	9,	14,	13,	12,	15	},
 			},
-			.ddr6 = {
+			.ddr5 = {
 				.dq0	= {	8,	9,	10,	11,	12,	13,	14,	15	},
 				.dq1	= {	7,	6,	5,	4,	3,	2,	1,	0	},
 			},

From 84ff3d3d125d34e17fa247c6d5821c981ab53ba7 Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Thu, 30 Oct 2025 16:55:15 +0000
Subject: [PATCH 2890/3886] ec/starlabs/merlin: Add charge LED brightness
 control

Add support for controlling charge LED brightness similar to the
existing power LED brightness control. This includes:
- New Kconfig option EC_STARLABS_CHARGE_LED
- Charge LED CFR option in cfr.h
- Implementation in ite.c using shared led_brightness array
- ECRAM_CHARGE_LED register definition

Refactor LED brightness enum values into shared led_brightness array
for reuse between power and charge LED controls.
EC changes for charge LED brightness

TEST=build/boot starlabs/lite_adl and verify LED control via CFR

Change-Id: I0f243d666e1fdc7d6df9859bb1cdcf460b6029ec
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Signed-off-by: Ali Hamid <ali@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90563
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
---
 src/ec/starlabs/merlin/Kconfig                |  8 +++++-
 src/ec/starlabs/merlin/cfr.h                  | 24 ++++++++++++++----
 src/ec/starlabs/merlin/ite.c                  | 25 ++++++++++++++++---
 src/ec/starlabs/merlin/variants/glk/ecdefs.h  |  1 +
 src/ec/starlabs/merlin/variants/glkr/ecdefs.h |  1 +
 src/ec/starlabs/merlin/variants/kbl/ecdefs.h  |  1 +
 .../starlabs/merlin/variants/merlin/ecdefs.h  |  1 +
 7 files changed, 52 insertions(+), 9 deletions(-)

diff --git a/src/ec/starlabs/merlin/Kconfig b/src/ec/starlabs/merlin/Kconfig
index c21ac68a0a..e650c81772 100644
--- a/src/ec/starlabs/merlin/Kconfig
+++ b/src/ec/starlabs/merlin/Kconfig
@@ -94,6 +94,12 @@ config EC_STARLABS_POWER_LED
 	bool "Enable lowering the brightess of the Power LED"
 	default y
 	help
-	  Select the in the mainboard supports reducing the LED brightness
+	  Select if the mainboard supports reducing the power LED brightness
+
+config EC_STARLABS_CHARGE_LED
+	bool "Enable lowering the brightess of the Charge LED"
+	default y
+	help
+	  Select if the mainboard supports reducing the charge LED brightness
 
 endif
diff --git a/src/ec/starlabs/merlin/cfr.h b/src/ec/starlabs/merlin/cfr.h
index 51b3adad1a..170ec7a0dd 100644
--- a/src/ec/starlabs/merlin/cfr.h
+++ b/src/ec/starlabs/merlin/cfr.h
@@ -98,6 +98,13 @@ static const struct sm_object lid_switch = SM_DECLARE_ENUM({
 			SM_ENUM_VALUE_END				},
 });
 
+const struct sm_enum_value led_brightness[] = {
+	{ "Normal",	LED_NORMAL	},
+	{ "Reduced",	LED_REDUCED	},
+	{ "Off",	LED_OFF		},
+	SM_ENUM_VALUE_END
+};
+
 /*
  * Power LED Brightness
  */
@@ -106,9 +113,16 @@ static const struct sm_object power_led = SM_DECLARE_ENUM({
 	.ui_name	= "Power LED Brightness",
 	.ui_helptext	= "Control the maximum brightness of the power LED",
 	.default_value	= LED_NORMAL,
-	.values		= (const struct sm_enum_value[]) {
-			{ "Normal",		LED_NORMAL	},
-			{ "Reduced",		LED_REDUCED	},
-			{ "Off",		LED_OFF		},
-			SM_ENUM_VALUE_END			},
+	.values		= led_brightness,
+});
+
+/*
+ * Charge LED Brightness
+ */
+static const struct sm_object charge_led = SM_DECLARE_ENUM({
+	.opt_name	= "charge_led",
+	.ui_name	= "Charge LED Brightness",
+	.ui_helptext	= "Control the maximum brightness of the charge LED",
+	.default_value	= LED_NORMAL,
+	.values		= led_brightness,
 });
diff --git a/src/ec/starlabs/merlin/ite.c b/src/ec/starlabs/merlin/ite.c
index c239b061ad..953c9e3de6 100644
--- a/src/ec/starlabs/merlin/ite.c
+++ b/src/ec/starlabs/merlin/ite.c
@@ -345,7 +345,7 @@ static void merlin_init(struct device *dev)
 	 * Default:	0
 	 *
 	 */
-	const uint8_t power_led[] = {
+	const uint8_t led_brightness[] = {
 		LED_NORMAL,
 		LED_REDUCED,
 		LED_OFF
@@ -355,8 +355,27 @@ static void merlin_init(struct device *dev)
 		ec_write(ECRAM_POWER_LED,
 			get_ec_value_from_option("power_led",
 				LED_NORMAL,
-				power_led,
-				ARRAY_SIZE(power_led),
+				led_brightness,
+				ARRAY_SIZE(led_brightness),
+				UINT_MAX,
+				UINT_MAX));
+
+	/*
+	 * Charge LED Brightness
+	 *
+	 * Setting:	charge_led
+	 *
+	 * Values:	0, 1, 2
+	 * Default:	0
+	 *
+	 */
+
+	if (CONFIG(EC_STARLABS_CHARGE_LED))
+		ec_write(ECRAM_CHARGE_LED,
+			get_ec_value_from_option("charge_led",
+				LED_NORMAL,
+				led_brightness,
+				ARRAY_SIZE(led_brightness),
 				UINT_MAX,
 				UINT_MAX));
 }
diff --git a/src/ec/starlabs/merlin/variants/glk/ecdefs.h b/src/ec/starlabs/merlin/variants/glk/ecdefs.h
index ed518f400a..d5bfc037d3 100644
--- a/src/ec/starlabs/merlin/variants/glk/ecdefs.h
+++ b/src/ec/starlabs/merlin/variants/glk/ecdefs.h
@@ -19,6 +19,7 @@
 #define ECRAM_KBL_TIMEOUT		0x1a
 #define ECRAM_FN_LOCK_STATE		0x2c
 #define ECRAM_FN_CTRL_REVERSE		0x2d
+#define ECRAM_CHARGE_LED		dead_code_t(uint8_t)
 #define ECRAM_MAX_CHARGE		dead_code_t(uint8_t)
 #define ECRAM_FAN_MODE			dead_code_t(uint8_t)
 #define ECRAM_CHARGING_SPEED		dead_code_t(uint8_t)
diff --git a/src/ec/starlabs/merlin/variants/glkr/ecdefs.h b/src/ec/starlabs/merlin/variants/glkr/ecdefs.h
index 6d469b2785..3836820895 100644
--- a/src/ec/starlabs/merlin/variants/glkr/ecdefs.h
+++ b/src/ec/starlabs/merlin/variants/glkr/ecdefs.h
@@ -22,6 +22,7 @@
 #define ECRAM_KBL_TIMEOUT		0x12
 #define ECRAM_FN_LOCK_STATE		0x15
 #define ECRAM_FN_CTRL_REVERSE		0x13
+#define ECRAM_CHARGE_LED		dead_code_t(uint8_t)
 #define ECRAM_MAX_CHARGE		dead_code_t(uint8_t)
 #define ECRAM_FAN_MODE			dead_code_t(uint8_t)
 #define ECRAM_CHARGING_SPEED		dead_code_t(uint8_t)
diff --git a/src/ec/starlabs/merlin/variants/kbl/ecdefs.h b/src/ec/starlabs/merlin/variants/kbl/ecdefs.h
index b0f743f711..206ccf2715 100644
--- a/src/ec/starlabs/merlin/variants/kbl/ecdefs.h
+++ b/src/ec/starlabs/merlin/variants/kbl/ecdefs.h
@@ -20,6 +20,7 @@
 #define ECRAM_FN_LOCK_STATE		0x2c
 #define ECRAM_FAN_MODE			0x42
 #define ECRAM_FN_CTRL_REVERSE		0x43
+#define ECRAM_CHARGE_LED		dead_code_t(uint8_t)
 #define ECRAM_MAX_CHARGE		dead_code_t(uint8_t)
 #define ECRAM_CHARGING_SPEED		dead_code_t(uint8_t)
 #define ECRAM_LID_SWITCH		dead_code_t(uint8_t)
diff --git a/src/ec/starlabs/merlin/variants/merlin/ecdefs.h b/src/ec/starlabs/merlin/variants/merlin/ecdefs.h
index 4fab635f3d..f924ad0fbf 100644
--- a/src/ec/starlabs/merlin/variants/merlin/ecdefs.h
+++ b/src/ec/starlabs/merlin/variants/merlin/ecdefs.h
@@ -19,6 +19,7 @@
 #define ECRAM_TRACKPAD_STATE		0x0c
 #define ECRAM_FN_LOCK_STATE		0x0f
 #define ECRAM_FN_CTRL_REVERSE		0x17
+#define ECRAM_CHARGE_LED		0x18
 #define ECRAM_MAX_CHARGE		0x1a
 #define ECRAM_FAN_MODE			0x1b
 #define ECRAM_CHARGING_SPEED		0x1d

From ab2c69c4f306d0ebd3baa49dd1389b99f1b751f7 Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Mon, 1 Dec 2025 18:11:06 -0600
Subject: [PATCH 2891/3886] mb/starlabs/starbook: Add CFR options for
 power/charge LED brightness

Add CFR options to expose EC controls to set the brightness of the
power and charge LEDs (normal/dim/off).

TEST=build/boot starbook_mtl, verify LED control via CFR

Change-Id: I7e1fe4efaab4327c8b95b108a9014e50058d6ed4
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90564
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
---
 src/mainboard/starlabs/starbook/cfr.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/src/mainboard/starlabs/starbook/cfr.c b/src/mainboard/starlabs/starbook/cfr.c
index cddc9af16f..69e48d1023 100644
--- a/src/mainboard/starlabs/starbook/cfr.c
+++ b/src/mainboard/starlabs/starbook/cfr.c
@@ -38,6 +38,8 @@ static struct sm_obj_form power = {
 		#if CONFIG(EC_STARLABS_CHARGING_SPEED)
 		&charging_speed,
 		#endif
+		&power_led,
+		&charge_led,
 		&power_on_after_fail_bool,
 		NULL
 	},

From 951c28c1bf3538af255d0ba4ff5f05d303b14580 Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Mon, 1 Dec 2025 18:14:45 -0600
Subject: [PATCH 2892/3886] mb/starlabs/starfighter: Add CFR options for
 power/charge LED brightness

Add CFR options to expose EC controls to set the brightness of the
power and charge LEDs (normal/dim/off).

TEST=build/boot starfighter_mtl, verify LED control via CFR

Change-Id: I2af8372f923f92af62e48da77d4bddb87ab1eba0
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90565
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/starlabs/starfighter/cfr.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/src/mainboard/starlabs/starfighter/cfr.c b/src/mainboard/starlabs/starfighter/cfr.c
index 166a9dbb81..ff3567f860 100644
--- a/src/mainboard/starlabs/starfighter/cfr.c
+++ b/src/mainboard/starlabs/starfighter/cfr.c
@@ -37,6 +37,8 @@ static struct sm_obj_form power = {
 		#if CONFIG(EC_STARLABS_CHARGING_SPEED)
 		&charging_speed,
 		#endif
+		&power_led,
+		&charge_led,
 		&power_on_after_fail_bool,
 		NULL
 	},

From 975e48faaf7d716867d824bfc5e71790c1af3038 Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Mon, 1 Dec 2025 17:58:48 -0600
Subject: [PATCH 2893/3886] mb/starlabs/starlite_adl: Add CFR option for charge
 LED brightness

Add a CFR option to expose the newly-added EC control to set the charge
LED brightness (normal/dim/off).

TEST=build/boot starlabs/lite_adl, verify charge LED control via CFR

Change-Id: I090437e8de2fd65bfad93a2037fd9346347e9fc1
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Signed-off-by: Ali Hamid <ali@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90566
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/starlabs/starlite_adl/cfr.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/src/mainboard/starlabs/starlite_adl/cfr.c b/src/mainboard/starlabs/starlite_adl/cfr.c
index 2ed505a17f..da0b77bd94 100644
--- a/src/mainboard/starlabs/starlite_adl/cfr.c
+++ b/src/mainboard/starlabs/starlite_adl/cfr.c
@@ -48,6 +48,7 @@ static struct sm_obj_form power = {
 		&charging_speed,
 		#endif
 		&power_led,
+		&charge_led,
 		&power_on_after_fail_bool,
 		NULL
 	},

From 695041a9bf54493afa89ae17a5be6024ce37a9f7 Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Sat, 29 Nov 2025 17:56:28 -0600
Subject: [PATCH 2894/3886] mb/starlabs/*: Increase size of SMMSTORE region to
 512KB

The previous default size of 256KB provided for only 64KB of actual
space for EFI variables, and after accounting for fragmentation, did
not provide enough free space for applying updates, such as for the
UEFI revocation database (DBX). Increasing it to 512KB allows for
192KB space for variables, and allows the UEFI DBX to be updated
properly via fwupd.

TEST=build/boot starlite_adl, verify UEFI DBX able to be successfully
updated via fwupd.

Change-Id: I0fd28e38f5d3ad1e4db33fa3ab075929044ac831
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90284
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
---
 src/mainboard/starlabs/byte_adl/variants/mk_ii/board.fmd    | 6 +++---
 src/mainboard/starlabs/lite/board.fmd                       | 4 ++--
 src/mainboard/starlabs/starbook/variants/adl/board.fmd      | 6 +++---
 src/mainboard/starlabs/starbook/variants/adl_n/board.fmd    | 6 +++---
 src/mainboard/starlabs/starbook/variants/cml/board.fmd      | 6 +++---
 src/mainboard/starlabs/starbook/variants/kbl/board.fmd      | 6 +++---
 src/mainboard/starlabs/starbook/variants/mtl/board.fmd      | 6 +++---
 src/mainboard/starlabs/starbook/variants/rpl/board.fmd      | 6 +++---
 src/mainboard/starlabs/starbook/variants/tgl/board.fmd      | 6 +++---
 src/mainboard/starlabs/starfighter/variants/mtl/board.fmd   | 6 +++---
 src/mainboard/starlabs/starfighter/variants/rpl/board.fmd   | 6 +++---
 src/mainboard/starlabs/starlite_adl/variants/mk_v/board.fmd | 6 +++---
 12 files changed, 35 insertions(+), 35 deletions(-)

diff --git a/src/mainboard/starlabs/byte_adl/variants/mk_ii/board.fmd b/src/mainboard/starlabs/byte_adl/variants/mk_ii/board.fmd
index 3c64b27134..2197262237 100644
--- a/src/mainboard/starlabs/byte_adl/variants/mk_ii/board.fmd
+++ b/src/mainboard/starlabs/byte_adl/variants/mk_ii/board.fmd
@@ -6,9 +6,9 @@ FLASH	0x1000000 {
 	SI_BIOS 0xa00000 {
 		EC@0x0			0x20000
 		RW_MRC_CACHE@0x20000	0x10000
-		SMMSTORE@0x30000	0x40000
-		CONSOLE@0x70000		0x20000
-		FMAP@0x90000		0x1000
+		SMMSTORE@0x30000	0x80000
+		CONSOLE@0xB0000		0x20000
+		FMAP@0xD0000		0x1000
 		COREBOOT(CBFS)
 	}
 }
diff --git a/src/mainboard/starlabs/lite/board.fmd b/src/mainboard/starlabs/lite/board.fmd
index 5e16badf5c..065ea619bd 100644
--- a/src/mainboard/starlabs/lite/board.fmd
+++ b/src/mainboard/starlabs/lite/board.fmd
@@ -44,7 +44,7 @@
 # the header.
 FLASH 8M {
 	OBBP@0x382000 {
-		OBB@0x0			0x2ae000 {
+		OBB@0x0			0x2ee000 {
 			FMAP@0xe000			0x10000
 			COREBOOT(CBFS)@0x1e000		0x210000
 			FPF_STATUS@0x22e000		0x10000
@@ -53,7 +53,7 @@ FLASH 8M {
 				RW_MRC_CACHE@0x10000		0x10000
 				RW_VAR_MRC_CACHE@0x20000	0x10000
 			}
-			SMMSTORE@0x26e000		0x40000
+			SMMSTORE@0x26e000		0x80000
 		}
 	}
 }
diff --git a/src/mainboard/starlabs/starbook/variants/adl/board.fmd b/src/mainboard/starlabs/starbook/variants/adl/board.fmd
index b652a36fe6..7495d43cec 100644
--- a/src/mainboard/starlabs/starbook/variants/adl/board.fmd
+++ b/src/mainboard/starlabs/starbook/variants/adl/board.fmd
@@ -6,9 +6,9 @@ FLASH	0x2000000 {
 	SI_BIOS 0x1000000 {
 		EC@0x0			0x20000
 		RW_MRC_CACHE@0x20000	0x10000
-		SMMSTORE@0x30000	0x40000
-		CONSOLE@0x70000		0x20000
-		FMAP@0x90000		0x1000
+		SMMSTORE@0x30000	0x80000
+		CONSOLE@0xB0000		0x20000
+		FMAP@0xD0000		0x1000
 		COREBOOT(CBFS)
 	}
 }
diff --git a/src/mainboard/starlabs/starbook/variants/adl_n/board.fmd b/src/mainboard/starlabs/starbook/variants/adl_n/board.fmd
index bc72a6098d..9cf12adf81 100644
--- a/src/mainboard/starlabs/starbook/variants/adl_n/board.fmd
+++ b/src/mainboard/starlabs/starbook/variants/adl_n/board.fmd
@@ -6,9 +6,9 @@ FLASH	0x1000000 {
 	SI_BIOS 0xa00000 {
 		EC@0x0			0x20000
 		RW_MRC_CACHE@0x20000	0x10000
-		SMMSTORE@0x30000	0x40000
-		CONSOLE@0x70000		0x20000
-		FMAP@0x90000		0x1000
+		SMMSTORE@0x30000	0x80000
+		CONSOLE@0xB0000		0x20000
+		FMAP@0xD0000		0x1000
 		COREBOOT(CBFS)
 	}
 }
diff --git a/src/mainboard/starlabs/starbook/variants/cml/board.fmd b/src/mainboard/starlabs/starbook/variants/cml/board.fmd
index 9018104edd..747141d188 100644
--- a/src/mainboard/starlabs/starbook/variants/cml/board.fmd
+++ b/src/mainboard/starlabs/starbook/variants/cml/board.fmd
@@ -6,9 +6,9 @@ FLASH 16M {
 	BIOS@0x400000 0xC00000 {
 		EC@0x0 0x20000
 		RW_MRC_CACHE@0x20000 0x10000
-		SMMSTORE@0x30000 0x40000
-		CONSOLE@0x70000 0x20000
-		FMAP@0x90000 0x200
+		SMMSTORE@0x30000 0x80000
+		CONSOLE@0xB0000 0x20000
+		FMAP@0xD0000 0x200
 		COREBOOT(CBFS)
 	}
 }
diff --git a/src/mainboard/starlabs/starbook/variants/kbl/board.fmd b/src/mainboard/starlabs/starbook/variants/kbl/board.fmd
index ef63457460..c9eee557ca 100644
--- a/src/mainboard/starlabs/starbook/variants/kbl/board.fmd
+++ b/src/mainboard/starlabs/starbook/variants/kbl/board.fmd
@@ -1,9 +1,9 @@
 FLASH 8M {
 	BIOS@0x200000 0x600000 {
 		RW_MRC_CACHE@0x0 0x10000
-		SMMSTORE@0x10000 0x40000
-		CONSOLE@0x50000 0x20000
-		FMAP@0x70000 0x200
+		SMMSTORE@0x10000 0x80000
+		CONSOLE@0x90000 0x20000
+		FMAP@0xB0000 0x200
 		COREBOOT(CBFS)
 	}
 }
diff --git a/src/mainboard/starlabs/starbook/variants/mtl/board.fmd b/src/mainboard/starlabs/starbook/variants/mtl/board.fmd
index cfa449253d..c1691514ab 100644
--- a/src/mainboard/starlabs/starbook/variants/mtl/board.fmd
+++ b/src/mainboard/starlabs/starbook/variants/mtl/board.fmd
@@ -6,9 +6,9 @@ FLASH	0x2000000 {
 	SI_BIOS 0xe00000 {
 		EC@0x0			0x20000
 		RW_MRC_CACHE@0x20000	0x10000
-		SMMSTORE@0x30000	0x40000
-		CONSOLE@0x70000		0x20000
-		FMAP@0x90000		0x1000
+		SMMSTORE@0x30000	0x80000
+		CONSOLE@0xB0000		0x20000
+		FMAP@0xD0000		0x1000
 		COREBOOT(CBFS)
 	}
 }
diff --git a/src/mainboard/starlabs/starbook/variants/rpl/board.fmd b/src/mainboard/starlabs/starbook/variants/rpl/board.fmd
index 6dcecabde7..b921fa1f2b 100644
--- a/src/mainboard/starlabs/starbook/variants/rpl/board.fmd
+++ b/src/mainboard/starlabs/starbook/variants/rpl/board.fmd
@@ -6,9 +6,9 @@ FLASH	0x2000000 {
 	SI_BIOS 0x1000000 {
 		EC@0x0			0x20000
 		RW_MRC_CACHE@0x20000	0x10000
-		SMMSTORE@0x30000	0x40000
-		CONSOLE@0x70000		0x20000
-		FMAP@0x90000		0x1000
+		SMMSTORE@0x30000	0x80000
+		CONSOLE@0xB0000		0x20000
+		FMAP@0xD0000		0x1000
 		COREBOOT(CBFS)
 	}
 }
diff --git a/src/mainboard/starlabs/starbook/variants/tgl/board.fmd b/src/mainboard/starlabs/starbook/variants/tgl/board.fmd
index e7405bee77..26e341f50b 100644
--- a/src/mainboard/starlabs/starbook/variants/tgl/board.fmd
+++ b/src/mainboard/starlabs/starbook/variants/tgl/board.fmd
@@ -6,9 +6,9 @@ FLASH	0x1000000 {
 	SI_BIOS	0xb00000 {
 		EC@0x0			0x20000
 		RW_MRC_CACHE@0x20000	0x10000
-		SMMSTORE@0x30000	0x40000
-		CONSOLE@0x70000		0x20000
-		FMAP@0x90000		0x1000
+		SMMSTORE@0x30000	0x80000
+		CONSOLE@0xB0000		0x20000
+		FMAP@0xD0000		0x1000
 		COREBOOT(CBFS)
 	}
 }
diff --git a/src/mainboard/starlabs/starfighter/variants/mtl/board.fmd b/src/mainboard/starlabs/starfighter/variants/mtl/board.fmd
index 1c11c433a2..ad7674988f 100644
--- a/src/mainboard/starlabs/starfighter/variants/mtl/board.fmd
+++ b/src/mainboard/starlabs/starfighter/variants/mtl/board.fmd
@@ -6,9 +6,9 @@ FLASH	0x2000000 {
 	SI_BIOS 0x1000000 {
 		EC@0x0			0x20000
 		RW_MRC_CACHE@0x20000	0x10000
-		SMMSTORE@0x30000	0x40000
-		CONSOLE@0x70000		0x20000
-		FMAP@0x90000		0x1000
+		SMMSTORE@0x30000	0x80000
+		CONSOLE@0xB0000		0x20000
+		FMAP@0xD0000		0x1000
 		COREBOOT(CBFS)
 	}
 }
diff --git a/src/mainboard/starlabs/starfighter/variants/rpl/board.fmd b/src/mainboard/starlabs/starfighter/variants/rpl/board.fmd
index 7f89c336ca..1990e9f88d 100644
--- a/src/mainboard/starlabs/starfighter/variants/rpl/board.fmd
+++ b/src/mainboard/starlabs/starfighter/variants/rpl/board.fmd
@@ -6,9 +6,9 @@ FLASH	0x2000000 {
 	SI_BIOS 0x1000000 {
 		EC@0x0			0x20000
 		RW_MRC_CACHE@0x20000	0x10000
-		SMMSTORE@0x30000	0x40000
-		CONSOLE@0x70000		0x20000
-		FMAP@0x90000		0x1000
+		SMMSTORE@0x30000	0x80000
+		CONSOLE@0xB0000		0x20000
+		FMAP@0xD0000		0x1000
 		COREBOOT(CBFS)
 	}
 }
diff --git a/src/mainboard/starlabs/starlite_adl/variants/mk_v/board.fmd b/src/mainboard/starlabs/starlite_adl/variants/mk_v/board.fmd
index bc72a6098d..9cf12adf81 100644
--- a/src/mainboard/starlabs/starlite_adl/variants/mk_v/board.fmd
+++ b/src/mainboard/starlabs/starlite_adl/variants/mk_v/board.fmd
@@ -6,9 +6,9 @@ FLASH	0x1000000 {
 	SI_BIOS 0xa00000 {
 		EC@0x0			0x20000
 		RW_MRC_CACHE@0x20000	0x10000
-		SMMSTORE@0x30000	0x40000
-		CONSOLE@0x70000		0x20000
-		FMAP@0x90000		0x1000
+		SMMSTORE@0x30000	0x80000
+		CONSOLE@0xB0000		0x20000
+		FMAP@0xD0000		0x1000
 		COREBOOT(CBFS)
 	}
 }

From 080ca011fe10565af8779abf1789e6f04b57e986 Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Thu, 18 Dec 2025 12:12:38 -0600
Subject: [PATCH 2895/3886] Documentation: Finalize 25.12 release notes

This adds a few items which were merged after the preliminary release
notes were merged, and updates the statistics for actual release tag.

Change-Id: I3b59568a67a3caa553c5f409edfed3053c1d4b7d
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90553
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
---
 .../releases/coreboot-25.12-relnotes.md       | 67 ++++++++++++++++---
 1 file changed, 56 insertions(+), 11 deletions(-)

diff --git a/Documentation/releases/coreboot-25.12-relnotes.md b/Documentation/releases/coreboot-25.12-relnotes.md
index 894d8f9da7..d49c9dbce3 100644
--- a/Documentation/releases/coreboot-25.12-relnotes.md
+++ b/Documentation/releases/coreboot-25.12-relnotes.md
@@ -1,9 +1,9 @@
-Upcoming release - coreboot 25.12
+coreboot 25.12 release
 ========================================================================
 
 The coreboot project is pleased to announce the release of coreboot
 25.12, continuing our commitment to advancing open-source firmware
-development. This release incorporates over 680 commits from more than
+development. This release incorporates over 750 commits from more than
 110 contributors, including numerous first-time authors.
 
 Key improvements include:
@@ -84,6 +84,14 @@ configuration (30b43839448) and VCM type and address settings
 configuration under modern operating systems, particularly Windows,
 as proper SSDB and PLD configuration is required for full functionality.
 
+DSM (Device Specific Method) generation has been refactored into
+per-UUID functions (ea099e8b8c9, c8f89e00e4c), with new support for
+CVF (Computer Vision Framework) DSM and I2C V2 DSM functions
+(a64b93562d0, 1532eb60ee7). The driver now supports ACPI device type
+selection (ae0d2324021) and ROM type/address configuration for camera
+sensors (6459a2007a5), improving compatibility with various camera
+implementations.
+
 
 ### soc/qualcomm/x1p42100: Expanded platform support and debug capabilities
 
@@ -103,6 +111,15 @@ layout refinements (c3afc13a0a5) optimize BL31 region placement and
 TZ Application memory alignment, improving overall platform memory
 utilization and security boundaries.
 
+The platform now includes CMD-DB (Command Database) driver support
+(01bc527afa2), enabling resource address and configuration data
+lookup for hardware accelerators. The CMD-DB region is properly mapped
+as non-cacheable in MMU (a4cc1784860, 2277edff88b), ensuring correct
+access patterns for shared resource management. ARM64 architecture
+improvements include distinct PRERAM and POSTRAM stack regions
+(641f7ac677b, 1b599a88449), with PRERAM stack relocated to BSRAM
+memory (4d53aa77042) for improved memory utilization.
+
 
 ### soc/intel: LPCAMM (Low Power Compression Attached Memory Module) support
 
@@ -135,6 +152,23 @@ Measurement) initialization support has been added
 (33fc33c132c), improving security and system reliability.
 
 
+### include/acpi: Comprehensive APEI (Advanced Platform Error Interface) infrastructure
+
+Extensive APEI struct definitions have been added to support advanced
+error reporting capabilities (679ea61d4de, b689671e79d, 7a41dc416be,
+5251284e392). The implementation includes structs for Machine Check
+Exception (MCE), Non-Maskable Interrupt (NMI), and PCIe AER (Advanced
+Error Reporting) error sources, providing a foundation for BERT (Boot
+Error Record Table), HEST (Hardware Error Source Table), and EINJ
+(Error Injection Table) implementations.
+
+These additions enable platforms to properly report hardware errors
+to operating systems, supporting firmware-first error handling models
+and improving system reliability diagnostics. The struct definitions
+follow ACPI specification standards and include proper validation
+(847d91b82e5, b70309350f8).
+
+
 ### commonlib: Code consolidation and endian handling improvements
 
 The `<endian.h>` header implementations from both coreboot and
@@ -191,8 +225,19 @@ Additional coreboot changes
 * Intel FSP UPD header typedef additions (2ce4e094690)
 * Azalia verb table implementation rework for improved maintainability
   (31fc5b06a6b) across multiple platforms
+* Azalia driver timing fixes including proper 521us delay after RESET#
+  de-assertion (ecf202b8e4a) and link-reset improvements
+  (6e074550a5c, 152914272c1)
 * Intel touch driver enhancements for new devices with improved I2C
   speed handling (f1708cf21a2, fce489e9e5c, 1af54d9784b)
+* Generic graphics driver support extended to non-VGA devices
+  (0f1ae4ae5f1), expanding compatibility beyond traditional VGA
+  displays
+* MediaTek ARMv9 MTE (Memory Tagging Extension) tag memory support
+  added to bootmem (3d5135fdd07, 9203cc827f9), enabling proper memory
+  tagging for security-enhanced platforms
+* Parallel charging infrastructure and support for Google Bluey platforms
+  (de87ea0efad, 896984e800a), enabling faster charging capabilities
 * Qualcomm USB Type-C support with PHY configuration and repeater support
   (8ffa58723a2, 45cedbb9922, 155041ad4cf, b18dfde22a7)
 * SoundWire drivers for Cirrus Logic CS35L56 and CS42L43 codecs
@@ -264,15 +309,15 @@ Platform Updates
 
 Statistics from the 25.09 to the 25.12 release
 --------------------------------------------
-* Total Commits: 687
-* Average Commits per day: 8.79
-* Total lines added: 57757
-* Average lines added per commit: 84.07
-* Number of patches adding more than 100 lines: 69
-* Average lines added per small commit: 42.00
-* Total lines removed: 9190
-* Average lines removed per commit: 13.38
-* Total difference between added and removed: 48567
+* Total Commits: 757
+* Average Commits per day: 8.94
+* Total lines added: 62219
+* Average lines added per commit: 82.19
+* Number of patches adding more than 100 lines: 77
+* Average lines added per small commit: 42.02
+* Total lines removed: 9669
+* Average lines removed per commit: 12.77
+* Total difference between added and removed: 52550
 * Total authors: 106
 * New authors: 21
 

From 188cd88ac7d6f7af4b0a2ca832e096c1e9d8bf6f Mon Sep 17 00:00:00 2001
From: Payne Lin <payne.lin@mediatek.corp-partner.google.com>
Date: Fri, 19 Dec 2025 15:38:38 +0800
Subject: [PATCH 2896/3886] soc/mediatek/mt8196: Correct MIPI register control

Configuring pll_con1 is wrong. Change it to voltage_sel.

BUG=b:424782827
TEST=Build pass, boot ok.
Verify display output on the following platforms:
- 8196 Navi: eDP path.
- 8189 Skywalker: eDP path.
- 8189 Padme: single MIPI path (without DSC).
- 8196 Sapphire: dual MIPI path (with DSC).

Change-Id: I300af87f3b7850cb994bc01c0572279ba18efac0
Signed-off-by: Payne Lin <payne.lin@mediatek.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90557
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Chen-Tsung Hsieh <chentsung@google.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/soc/mediatek/mt8196/dsi.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/soc/mediatek/mt8196/dsi.c b/src/soc/mediatek/mt8196/dsi.c
index 6d6705986b..0ea12b2931 100644
--- a/src/soc/mediatek/mt8196/dsi.c
+++ b/src/soc/mediatek/mt8196/dsi.c
@@ -19,10 +19,10 @@ void mtk_dsi_configure_mipi_tx(struct mipi_tx_regs *mipi_tx_reg, u32 data_rate,
 
 	/* Select different voltage when different data rate */
 	if (data_rate < (u32)2500 * MHz) {
-		clrsetbits32(&mipi_tx_reg->pll_con1, RG_DSI_PRD_REF_SEL, RG_DSI_PRD_REF_MINI);
+		clrsetbits32(&mipi_tx_reg->voltage_sel, RG_DSI_PRD_REF_SEL, RG_DSI_PRD_REF_MINI);
 		write32(&mipi_tx_reg->cdphy_preserved, 0xFFFF00F0);
 	} else {
-		clrsetbits32(&mipi_tx_reg->pll_con1, RG_DSI_PRD_REF_SEL, RG_DSI_PRD_REF_DEF);
+		clrsetbits32(&mipi_tx_reg->voltage_sel, RG_DSI_PRD_REF_SEL, RG_DSI_PRD_REF_DEF);
 		write32(&mipi_tx_reg->cdphy_preserved, 0xFFFF0030);
 	}
 

From de4148888c9c5bd24d9a754d15145d70a6db4127 Mon Sep 17 00:00:00 2001
From: Felix Singer <felixsinger@posteo.net>
Date: Sat, 20 Dec 2025 10:02:30 +0100
Subject: [PATCH 2897/3886] tests: Disable generation of lcov HTML

The issues still appears even after commit 65833355ca36 ("tests: Disable
gcov warnings"). So, disable the HTML generation completely until the
issue is figured out.

Change-Id: I683889ff8a0769697154079f99fe1d6ff9773281
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90578
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
---
 tests/Makefile.mk | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/tests/Makefile.mk b/tests/Makefile.mk
index 08ba3dc3cb..9e3f86a138 100644
--- a/tests/Makefile.mk
+++ b/tests/Makefile.mk
@@ -149,8 +149,8 @@ clean-junit.xml-unit-tests:
 ifeq ($(COV),1)
 coverage-report:
 	lcov -o $(testobj)/tests.info -c -d $(testobj) --exclude '$(testsrc)/*'
-	genhtml --ignore-errors inconsistent,corrupt -q -o $(testobj)/$(coverage_dir) -t "coreboot unit tests" \
-	-s $(testobj)/tests.info
+	# TODO: fix inconsistent and corrupt error reports
+	# genhtml --ignore-errors inconsistent,corrupt -q -o $(testobj)/$(coverage_dir) -t "coreboot unit tests" -s $(testobj)/tests.info
 
 clean-coverage-report:
 	rm -Rf $(testobj)/$(coverage_dir)

From bceb2c83ad537a16c4aeddaefc36e3985774d344 Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Fri, 19 Dec 2025 15:25:02 -0600
Subject: [PATCH 2898/3886] mb/{google/intel}: Fix/add missing MIPI camera SSDB
 lanes_used/link_used

Ensure all mipi_camera sensor configurations have both ssdb.lanes_used
and ssdb.link_used defined, and that these values correctly match the
corresponding (known good) CIO2 IPU port configuration:

- ssdb.lanes_used must match cio2_lanes_used = {x} for CAMx
- ssdb.link_used must match cio2_prt[x] for CAMx

Change-Id: Ifbf22c69d29c71138b7f59f08782d90425a09e30
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90571
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
---
 src/mainboard/google/brya/variants/anraggar/overridetree.cb   | 1 +
 src/mainboard/google/brya/variants/brya0/overridetree.cb      | 4 ++--
 src/mainboard/google/brya/variants/meliks/overridetree.cb     | 2 +-
 src/mainboard/google/brya/variants/pirrha/overridetree.cb     | 2 +-
 src/mainboard/google/brya/variants/redrix/overridetree.cb     | 4 ++--
 src/mainboard/google/brya/variants/redrix4es/overridetree.cb  | 4 ++--
 src/mainboard/google/brya/variants/skolas/overridetree.cb     | 4 ++--
 src/mainboard/google/brya/variants/skolas4es/overridetree.cb  | 2 +-
 src/mainboard/google/brya/variants/teliks/overridetree.cb     | 1 +
 src/mainboard/google/brya/variants/telith/overridetree.cb     | 1 +
 src/mainboard/google/brya/variants/xivu/overridetree.cb       | 2 +-
 .../google/dedede/variants/waddledoo/overridetree.cb          | 3 ++-
 src/mainboard/google/fatcat/variants/fatcat/overridetree.cb   | 2 ++
 src/mainboard/google/rex/variants/kanix/overridetree.cb       | 2 +-
 src/mainboard/google/rex/variants/karis/overridetree.cb       | 2 +-
 src/mainboard/google/rex/variants/rex0/overridetree.cb        | 4 ++--
 src/mainboard/google/rex/variants/screebo/overridetree.cb     | 2 +-
 src/mainboard/intel/adlrvp/devicetree.cb                      | 2 ++
 src/mainboard/intel/adlrvp/devicetree_m.cb                    | 2 ++
 src/mainboard/intel/adlrvp/devicetree_n.cb                    | 2 ++
 .../intel/jasperlake_rvp/variants/jslrvp/devicetree.cb        | 3 ++-
 .../intel/mtlrvp/variants/baseboard/mtlrvp_p/devicetree.cb    | 2 ++
 src/mainboard/intel/ptlrvp/variants/ptlrvp/overridetree.cb    | 2 ++
 .../intel/ptlrvp/variants/ptlrvp_chromeec/overridetree.cb     | 2 ++
 24 files changed, 38 insertions(+), 19 deletions(-)

diff --git a/src/mainboard/google/brya/variants/anraggar/overridetree.cb b/src/mainboard/google/brya/variants/anraggar/overridetree.cb
index 877eec4700..5b71e31795 100644
--- a/src/mainboard/google/brya/variants/anraggar/overridetree.cb
+++ b/src/mainboard/google/brya/variants/anraggar/overridetree.cb
@@ -270,6 +270,7 @@ chip soc/intel/alderlake
 				register "device_type" = "INTEL_ACPI_CAMERA_SENSOR"
 
 				register "ssdb.lanes_used" = "4"
+				register "ssdb.link_used" = "1"
 				register "ssdb.platform" = "PLAT_ADL"
 				register "ssdb.vcm_type" = "VCM_DW9714"
 				register "vcm_address" = "0x0C"
diff --git a/src/mainboard/google/brya/variants/brya0/overridetree.cb b/src/mainboard/google/brya/variants/brya0/overridetree.cb
index 3139af5218..40f75629cf 100644
--- a/src/mainboard/google/brya/variants/brya0/overridetree.cb
+++ b/src/mainboard/google/brya/variants/brya0/overridetree.cb
@@ -543,7 +543,7 @@ chip soc/intel/alderlake
 				register "device_type" = "INTEL_ACPI_CAMERA_SENSOR"
 
 				register "ssdb.lanes_used" = "4"
-				register "ssdb.link_used" = "0"
+				register "ssdb.link_used" = "2"
 				register "ssdb.platform" = "PLAT_ADL"
 				register "ssdb.vcm_type" = "VCM_DW9808"
 				register "vcm_address" = "0x0C"
@@ -653,7 +653,7 @@ chip soc/intel/alderlake
 				register "device_type" = "INTEL_ACPI_CAMERA_SENSOR"
 
 				register "ssdb.lanes_used" = "4"
-				register "ssdb.link_used" = "0"
+				register "ssdb.link_used" = "2"
 				register "ssdb.platform" = "PLAT_ADL"
 				register "ssdb.vcm_type" = "VCM_DW9808"
 				register "vcm_address" = "0x0C"
diff --git a/src/mainboard/google/brya/variants/meliks/overridetree.cb b/src/mainboard/google/brya/variants/meliks/overridetree.cb
index 26cc775217..1e11eafa90 100644
--- a/src/mainboard/google/brya/variants/meliks/overridetree.cb
+++ b/src/mainboard/google/brya/variants/meliks/overridetree.cb
@@ -264,7 +264,7 @@ chip soc/intel/alderlake
 				register "device_type" = "INTEL_ACPI_CAMERA_SENSOR"
 
 				register "ssdb.lanes_used" = "4"
-				register "ssdb.link_used" = "1"
+				register "ssdb.link_used" = "2"
 				register "ssdb.platform" = "PLAT_ADL"
 				register "ssdb.vcm_type" = "VCM_DW9714"
 				register "vcm_address" = "0x0C"
diff --git a/src/mainboard/google/brya/variants/pirrha/overridetree.cb b/src/mainboard/google/brya/variants/pirrha/overridetree.cb
index 48f317157d..561ab72473 100644
--- a/src/mainboard/google/brya/variants/pirrha/overridetree.cb
+++ b/src/mainboard/google/brya/variants/pirrha/overridetree.cb
@@ -303,7 +303,7 @@ chip soc/intel/alderlake
 				register "device_type" = "INTEL_ACPI_CAMERA_SENSOR"
 
 				register "ssdb.lanes_used" = "4"
-				register "ssdb.link_used" = "1"
+				register "ssdb.link_used" = "2"
 				register "ssdb.platform" = "PLAT_ADL"
 				register "ssdb.vcm_type" = "VCM_DW9714"
 				register "vcm_address" = "0x0C"
diff --git a/src/mainboard/google/brya/variants/redrix/overridetree.cb b/src/mainboard/google/brya/variants/redrix/overridetree.cb
index 9f79c6ab21..822babaead 100644
--- a/src/mainboard/google/brya/variants/redrix/overridetree.cb
+++ b/src/mainboard/google/brya/variants/redrix/overridetree.cb
@@ -420,7 +420,7 @@ chip soc/intel/alderlake
 				register "device_type" = "INTEL_ACPI_CAMERA_SENSOR"
 
 				register "ssdb.lanes_used" = "2"
-				register "ssdb.link_used" = "1"
+				register "ssdb.link_used" = "2"
 				register "ssdb.platform" = "PLAT_ADL"
 				register "ssdb.rom_type" = "ROM_EEPROM_CAT24C64"
 				register "rom_address" = "0x50"
@@ -463,7 +463,7 @@ chip soc/intel/alderlake
 				register "max_dstate_for_probe" = "ACPI_DEVICE_SLEEP_D3_COLD"
 
 				register "ssdb.lanes_used" = "2"
-				register "ssdb.link_used" = "1"
+				register "ssdb.link_used" = "2"
 				register "ssdb.platform" = "PLAT_ADL"
 				register "ssdb.rom_type" = "ROM_EEPROM_CAT24C64"
 				register "rom_address" = "0x50"
diff --git a/src/mainboard/google/brya/variants/redrix4es/overridetree.cb b/src/mainboard/google/brya/variants/redrix4es/overridetree.cb
index d36f91e414..4ebc017eab 100644
--- a/src/mainboard/google/brya/variants/redrix4es/overridetree.cb
+++ b/src/mainboard/google/brya/variants/redrix4es/overridetree.cb
@@ -350,7 +350,7 @@ chip soc/intel/alderlake
 				register "device_type" = "INTEL_ACPI_CAMERA_SENSOR"
 
 				register "ssdb.lanes_used" = "2"
-				register "ssdb.link_used" = "1"
+				register "ssdb.link_used" = "2"
 				register "ssdb.platform" = "PLAT_ADL"
 				register "ssdb.rom_type" = "ROM_EEPROM_CAT24C64"
 				register "rom_address" = "0x50"
@@ -396,7 +396,7 @@ chip soc/intel/alderlake
 				register "max_dstate_for_probe" = "ACPI_DEVICE_SLEEP_D3_COLD"
 
 				register "ssdb.lanes_used" = "2"
-				register "ssdb.link_used" = "1"
+				register "ssdb.link_used" = "2"
 				register "ssdb.platform" = "PLAT_ADL"
 				register "ssdb.rom_type" = "ROM_EEPROM_CAT24C64"
 				register "rom_address" = "0x50"
diff --git a/src/mainboard/google/brya/variants/skolas/overridetree.cb b/src/mainboard/google/brya/variants/skolas/overridetree.cb
index 0f5a6cf651..ac0e5f51da 100644
--- a/src/mainboard/google/brya/variants/skolas/overridetree.cb
+++ b/src/mainboard/google/brya/variants/skolas/overridetree.cb
@@ -542,7 +542,7 @@ chip soc/intel/alderlake
 				register "device_type" = "INTEL_ACPI_CAMERA_SENSOR"
 
 				register "ssdb.lanes_used" = "4"
-				register "ssdb.link_used" = "0"
+				register "ssdb.link_used" = "2"
 				register "ssdb.platform" = "PLAT_ADL"
 				register "ssdb.vcm_type" = "VCM_DW9808"
 				register "vcm_address" = "0x0C"
@@ -652,7 +652,7 @@ chip soc/intel/alderlake
 				register "device_type" = "INTEL_ACPI_CAMERA_SENSOR"
 
 				register "ssdb.lanes_used" = "4"
-				register "ssdb.link_used" = "0"
+				register "ssdb.link_used" = "2"
 				register "ssdb.platform" = "PLAT_ADL"
 				register "ssdb.vcm_type" = "VCM_DW9808"
 				register "vcm_address" = "0x0C"
diff --git a/src/mainboard/google/brya/variants/skolas4es/overridetree.cb b/src/mainboard/google/brya/variants/skolas4es/overridetree.cb
index 95a27df342..b4e505c305 100644
--- a/src/mainboard/google/brya/variants/skolas4es/overridetree.cb
+++ b/src/mainboard/google/brya/variants/skolas4es/overridetree.cb
@@ -383,7 +383,7 @@ chip soc/intel/alderlake
 				register "device_type" = "INTEL_ACPI_CAMERA_SENSOR"
 
 				register "ssdb.lanes_used" = "4"
-				register "ssdb.link_used" = "0"
+				register "ssdb.link_used" = "2"
 				register "ssdb.platform" = "PLAT_ADL"
 				register "ssdb.vcm_type" = "VCM_DW9808"
 				register "vcm_address" = "0x0C"
diff --git a/src/mainboard/google/brya/variants/teliks/overridetree.cb b/src/mainboard/google/brya/variants/teliks/overridetree.cb
index 121f432af1..9e4f90c0ab 100644
--- a/src/mainboard/google/brya/variants/teliks/overridetree.cb
+++ b/src/mainboard/google/brya/variants/teliks/overridetree.cb
@@ -287,6 +287,7 @@ chip soc/intel/alderlake
 				register "device_type" = "INTEL_ACPI_CAMERA_SENSOR"
 
 				register "ssdb.lanes_used" = "4"
+				register "ssdb.link_used" = "1"
 				register "ssdb.platform" = "PLAT_ADL"
 				register "ssdb.vcm_type" = "VCM_DW9714"
 				register "vcm_address" = "0x0C"
diff --git a/src/mainboard/google/brya/variants/telith/overridetree.cb b/src/mainboard/google/brya/variants/telith/overridetree.cb
index 7b5ebee441..1a6982d1d2 100644
--- a/src/mainboard/google/brya/variants/telith/overridetree.cb
+++ b/src/mainboard/google/brya/variants/telith/overridetree.cb
@@ -413,6 +413,7 @@ chip soc/intel/alderlake
 				register "device_type" = "INTEL_ACPI_CAMERA_SENSOR"
 
 				register "ssdb.lanes_used" = "4"
+				register "ssdb.link_used" = "1"
 				register "ssdb.platform" = "PLAT_ADL"
 				register "ssdb.vcm_type" = "VCM_DW9714"
 				register "vcm_address" = "0x0C"
diff --git a/src/mainboard/google/brya/variants/xivu/overridetree.cb b/src/mainboard/google/brya/variants/xivu/overridetree.cb
index 5b1dc9fd3d..364f720374 100644
--- a/src/mainboard/google/brya/variants/xivu/overridetree.cb
+++ b/src/mainboard/google/brya/variants/xivu/overridetree.cb
@@ -253,7 +253,7 @@ chip soc/intel/alderlake
 				register "device_type" = "INTEL_ACPI_CAMERA_SENSOR"
 
 				register "ssdb.lanes_used" = "4"
-				register "ssdb.link_used" = "1"
+				register "ssdb.link_used" = "2"
 				register "ssdb.platform" = "PLAT_ADL"
 				register "ssdb.vcm_type" = "VCM_DW9714"
 				register "vcm_address" = "0x0C"
diff --git a/src/mainboard/google/dedede/variants/waddledoo/overridetree.cb b/src/mainboard/google/dedede/variants/waddledoo/overridetree.cb
index 228a1720a6..321b05eda5 100644
--- a/src/mainboard/google/dedede/variants/waddledoo/overridetree.cb
+++ b/src/mainboard/google/dedede/variants/waddledoo/overridetree.cb
@@ -146,7 +146,7 @@ chip soc/intel/jasperlake
 				register "device_type" = "INTEL_ACPI_CAMERA_SENSOR"
 
 				register "ssdb.lanes_used" = "4"
-				register "ssdb.link_used" = "1"
+				register "ssdb.link_used" = "2"
 				register "ssdb.platform" = "PLAT_JSL"
 				register "ssdb.vcm_type" = "VCM_DW9808"
 				register "vcm_address" = "0x0C"
@@ -221,6 +221,7 @@ chip soc/intel/jasperlake
 				register "has_power_resource" = "true"
 
 				register "ssdb.lanes_used" = "1"
+				register "ssdb.link_used" = "0"
 				register "num_freq_entries" = "1"
 				register "link_freq[0]" = "180000000"
 				register "remote_name" = ""IPU0""
diff --git a/src/mainboard/google/fatcat/variants/fatcat/overridetree.cb b/src/mainboard/google/fatcat/variants/fatcat/overridetree.cb
index f520410847..f95d9e8255 100644
--- a/src/mainboard/google/fatcat/variants/fatcat/overridetree.cb
+++ b/src/mainboard/google/fatcat/variants/fatcat/overridetree.cb
@@ -665,6 +665,7 @@ chip soc/intel/pantherlake
 				register "ssdb.rom_type" = "ROM_EEPROM_CAT24C16"
 				register "rom_address" = "0x50"
 				register "ssdb.lanes_used" = "4"
+				register "ssdb.link_used" = "0"
 				register "ssdb.platform" = "PLAT_PTL"
 				register "num_freq_entries" = "1"
 				register "link_freq[0]" = "560 * MHz" # 560 MHz
@@ -770,6 +771,7 @@ chip soc/intel/pantherlake
 				register "ssdb.rom_type" = "ROM_EEPROM_CAT24C16"
 				register "rom_address" = "0x50"
 				register "ssdb.lanes_used" = "2"
+				register "ssdb.link_used" = "2"
 				register "ssdb.platform" = "PLAT_PTL"
 				register "num_freq_entries" = "1"
 				register "link_freq[0]" = "560 * MHz" # 560 MHz
diff --git a/src/mainboard/google/rex/variants/kanix/overridetree.cb b/src/mainboard/google/rex/variants/kanix/overridetree.cb
index a9feef6b16..2b110cead7 100644
--- a/src/mainboard/google/rex/variants/kanix/overridetree.cb
+++ b/src/mainboard/google/rex/variants/kanix/overridetree.cb
@@ -509,7 +509,7 @@ chip soc/intel/meteorlake
 				register "has_power_resource" = "true"
 
 				register "ssdb.lanes_used" = "2"
-				register "ssdb.link_used" = "1"
+				register "ssdb.link_used" = "4"
 				register "ssdb.platform" = "PLAT_MTL"
 				register "ssdb.rom_type" = "ROM_EEPROM_CAT24C64"
 				register "rom_address" = "0x50"
diff --git a/src/mainboard/google/rex/variants/karis/overridetree.cb b/src/mainboard/google/rex/variants/karis/overridetree.cb
index 580bb9d033..f16560841d 100644
--- a/src/mainboard/google/rex/variants/karis/overridetree.cb
+++ b/src/mainboard/google/rex/variants/karis/overridetree.cb
@@ -464,7 +464,7 @@ chip soc/intel/meteorlake
 				register "has_power_resource" = "true"
 
 				register "ssdb.lanes_used" = "2"
-				register "ssdb.link_used" = "1"
+				register "ssdb.link_used" = "4"
 				register "ssdb.platform" = "PLAT_MTL"
 				register "ssdb.rom_type" = "ROM_EEPROM_CAT24C64"
 				register "rom_address" = "0x50"
diff --git a/src/mainboard/google/rex/variants/rex0/overridetree.cb b/src/mainboard/google/rex/variants/rex0/overridetree.cb
index c82d773ff0..af20b62edf 100644
--- a/src/mainboard/google/rex/variants/rex0/overridetree.cb
+++ b/src/mainboard/google/rex/variants/rex0/overridetree.cb
@@ -469,7 +469,7 @@ chip soc/intel/meteorlake
 				register "device_type" = "INTEL_ACPI_CAMERA_SENSOR"
 
 				register "ssdb.lanes_used" = "4"
-				register "ssdb.link_used" = "0"
+				register "ssdb.link_used" = "4"
 				register "ssdb.platform" = "PLAT_MTL"
 				register "ssdb.vcm_type" = "VCM_DW9714"
 				register "vcm_address" = "0x0C"
@@ -627,7 +627,7 @@ chip soc/intel/meteorlake
 				register "has_power_resource" = "true"
 
 				register "ssdb.lanes_used" = "2"
-				register "ssdb.link_used" = "1"
+				register "ssdb.link_used" = "0"
 				register "ssdb.platform" = "PLAT_MTL"
 				register "ssdb.rom_type" = "ROM_EEPROM_CAT24C64"
 				register "rom_address" = "0x50"
diff --git a/src/mainboard/google/rex/variants/screebo/overridetree.cb b/src/mainboard/google/rex/variants/screebo/overridetree.cb
index b1e8ff7ce1..3d730a5820 100644
--- a/src/mainboard/google/rex/variants/screebo/overridetree.cb
+++ b/src/mainboard/google/rex/variants/screebo/overridetree.cb
@@ -515,7 +515,7 @@ chip soc/intel/meteorlake
 				register "chip_name" = ""Ov 08X40 Camera""
 				register "device_type" = "INTEL_ACPI_CAMERA_SENSOR"
 				register "ssdb.lanes_used" = "4"
-				register "ssdb.link_used" = "1"
+				register "ssdb.link_used" = "4"
 				register "ssdb.platform" = "PLAT_MTL"
 				register "ssdb.rom_type" = "ROM_EEPROM_CAT24C64"
 				register "rom_address" = "0x50"
diff --git a/src/mainboard/intel/adlrvp/devicetree.cb b/src/mainboard/intel/adlrvp/devicetree.cb
index 5c12bb3b80..5451156ad1 100644
--- a/src/mainboard/intel/adlrvp/devicetree.cb
+++ b/src/mainboard/intel/adlrvp/devicetree.cb
@@ -354,6 +354,7 @@ chip soc/intel/alderlake
 				register "device_type" = "INTEL_ACPI_CAMERA_SENSOR"
 
 				register "ssdb.lanes_used" = "2"
+				register "ssdb.link_used" = "2"
 				register "ssdb.platform" = "PLAT_ADL"
 				register "ssdb.vcm_type" = "VCM_DW9714"
 				register "vcm_address" = "0x0C"
@@ -409,6 +410,7 @@ chip soc/intel/alderlake
 				register "device_type" = "INTEL_ACPI_CAMERA_SENSOR"
 
 				register "ssdb.lanes_used" = "2"
+				register "ssdb.link_used" = "1"
 				register "ssdb.platform" = "PLAT_ADL"
 				register "num_freq_entries" = "1"
 				register "link_freq[0]" = "450000000"
diff --git a/src/mainboard/intel/adlrvp/devicetree_m.cb b/src/mainboard/intel/adlrvp/devicetree_m.cb
index 7d197b0eca..6886babeb2 100644
--- a/src/mainboard/intel/adlrvp/devicetree_m.cb
+++ b/src/mainboard/intel/adlrvp/devicetree_m.cb
@@ -288,6 +288,7 @@ chip soc/intel/alderlake
 				register "device_type" = "INTEL_ACPI_CAMERA_SENSOR"
 
 				register "ssdb.lanes_used" = "2"
+				register "ssdb.link_used" = "2"
 				register "ssdb.platform" = "PLAT_ADL"
 				register "ssdb.vcm_type" = "VCM_DW9714"
 				register "vcm_address" = "0x0C"
@@ -343,6 +344,7 @@ chip soc/intel/alderlake
 				register "device_type" = "INTEL_ACPI_CAMERA_SENSOR"
 
 				register "ssdb.lanes_used" = "2"
+				register "ssdb.link_used" = "1"
 				register "ssdb.platform" = "PLAT_ADL"
 				register "num_freq_entries" = "1"
 				register "link_freq[0]" = "450000000"
diff --git a/src/mainboard/intel/adlrvp/devicetree_n.cb b/src/mainboard/intel/adlrvp/devicetree_n.cb
index 73b6828a38..5207d553a9 100644
--- a/src/mainboard/intel/adlrvp/devicetree_n.cb
+++ b/src/mainboard/intel/adlrvp/devicetree_n.cb
@@ -296,6 +296,7 @@ chip soc/intel/alderlake
 				register "device_type" = "INTEL_ACPI_CAMERA_SENSOR"
 
 				register "ssdb.lanes_used" = "2"
+				register "ssdb.link_used" = "2"
 				register "ssdb.platform" = "PLAT_ADL"
 				register "ssdb.vcm_type" = "VCM_DW9714"
 				register "vcm_address" = "0x0C"
@@ -351,6 +352,7 @@ chip soc/intel/alderlake
 				register "device_type" = "INTEL_ACPI_CAMERA_SENSOR"
 
 				register "ssdb.lanes_used" = "2"
+				register "ssdb.link_used" = "1"
 				register "ssdb.platform" = "PLAT_ADL"
 				register "num_freq_entries" = "1"
 				register "link_freq[0]" = "450000000"
diff --git a/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb b/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb
index d1fe840129..fadd309dab 100644
--- a/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb
+++ b/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb
@@ -378,6 +378,7 @@ chip soc/intel/jasperlake
 				register "has_power_resource" = "true"
 
 				register "ssdb.lanes_used" = "2"
+				register "ssdb.link_used" = "0"
 				register "ssdb.platform" = "PLAT_JSL"
 				register "num_freq_entries" = "1"
 				register "link_freq[0]" = "360000000"
@@ -415,7 +416,7 @@ chip soc/intel/jasperlake
 				register "device_type" = "INTEL_ACPI_CAMERA_SENSOR"
 
 				register "ssdb.lanes_used" = "2"
-				register "ssdb.link_used" = "1"
+				register "ssdb.link_used" = "2"
 				register "ssdb.platform" = "PLAT_JSL"
 				register "ssdb.vcm_type" = "VCM_DW9714"
 				register "vcm_address" = "0x0C"
diff --git a/src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/devicetree.cb b/src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/devicetree.cb
index a01364dde1..995e765fff 100644
--- a/src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/devicetree.cb
+++ b/src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/devicetree.cb
@@ -441,6 +441,7 @@ chip soc/intel/meteorlake
 				register "device_type" = "INTEL_ACPI_CAMERA_SENSOR"
 
 				register "ssdb.lanes_used" = "4"
+				register "ssdb.link_used" = "4"
 				register "ssdb.platform" = "PLAT_MTL"
 				register "num_freq_entries" = "1"
 				register "link_freq[0]" = "560000000"
@@ -484,6 +485,7 @@ chip soc/intel/meteorlake
 				register "ssdb.rom_type" = "ROM_EEPROM_CAT24C16"
 				register "rom_address" = "0x50"
 				register "ssdb.lanes_used" = "4"
+				register "ssdb.link_used" = "0"
 				register "ssdb.platform" = "PLAT_MTL"
 				register "num_freq_entries" = "1"
 				register "link_freq[0]" = "560000000"
diff --git a/src/mainboard/intel/ptlrvp/variants/ptlrvp/overridetree.cb b/src/mainboard/intel/ptlrvp/variants/ptlrvp/overridetree.cb
index 73294ec6f1..0ffdd6e629 100644
--- a/src/mainboard/intel/ptlrvp/variants/ptlrvp/overridetree.cb
+++ b/src/mainboard/intel/ptlrvp/variants/ptlrvp/overridetree.cb
@@ -665,6 +665,7 @@ chip soc/intel/pantherlake
 				register "ssdb.rom_type" = "ROM_EEPROM_CAT24C16"
 				register "rom_address" = "0x50"
 				register "ssdb.lanes_used" = "4"
+				register "ssdb.link_used" = "0"
 				register "ssdb.platform" = "PLAT_PTL"
 				register "num_freq_entries" = "1"
 				register "link_freq[0]" = "560 * MHz" # 560 MHz
@@ -770,6 +771,7 @@ chip soc/intel/pantherlake
 				register "ssdb.rom_type" = "ROM_EEPROM_CAT24C16"
 				register "rom_address" = "0x50"
 				register "ssdb.lanes_used" = "2"
+				register "ssdb.link_used" = "2"
 				register "ssdb.platform" = "PLAT_PTL"
 				register "num_freq_entries" = "1"
 				register "link_freq[0]" = "560 * MHz" # 560 MHz
diff --git a/src/mainboard/intel/ptlrvp/variants/ptlrvp_chromeec/overridetree.cb b/src/mainboard/intel/ptlrvp/variants/ptlrvp_chromeec/overridetree.cb
index 2c7782f841..d6ac1a333a 100644
--- a/src/mainboard/intel/ptlrvp/variants/ptlrvp_chromeec/overridetree.cb
+++ b/src/mainboard/intel/ptlrvp/variants/ptlrvp_chromeec/overridetree.cb
@@ -665,6 +665,7 @@ chip soc/intel/pantherlake
 				register "ssdb.rom_type" = "ROM_EEPROM_CAT24C16"
 				register "rom_address" = "0x50"
 				register "ssdb.lanes_used" = "4"
+				register "ssdb.link_used" = "0"
 				register "ssdb.platform" = "PLAT_PTL"
 				register "num_freq_entries" = "1"
 				register "link_freq[0]" = "560 * MHz" # 560 MHz
@@ -770,6 +771,7 @@ chip soc/intel/pantherlake
 				register "ssdb.rom_type" = "ROM_EEPROM_CAT24C16"
 				register "rom_address" = "0x50"
 				register "ssdb.lanes_used" = "2"
+				register "ssdb.link_used" = "2"
 				register "ssdb.platform" = "PLAT_PTL"
 				register "num_freq_entries" = "1"
 				register "link_freq[0]" = "560 * MHz" # 560 MHz

From c5eecee5e9120b915f3f616b9bbdd3e8d51ad80e Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Fri, 19 Dec 2025 18:06:56 -0600
Subject: [PATCH 2899/3886] mb/google/rex: Add IPUA device and sensor names

Add missing configuration items for rex variants to have functional
MIPI cameras under Windows/mainline Linux:

- Add IPUA device to graphics device configuration
- Add sensor_name register to sensor device configurations

Screebo was missing the gfx/generic configuration for all other display
outputs present in other variants, so add that as well.

TEST=build/boot Win11/Linux on karis and screebo, verify MIPI camera
functional under both OSes using the standard driver stack.

Change-Id: I14ec0efd88c43ca94ebde2be4652775bcb6d73c3
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90573
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
---
 .../google/rex/variants/kanix/overridetree.cb |  8 ++++-
 .../google/rex/variants/karis/overridetree.cb |  7 ++++-
 .../google/rex/variants/rex0/overridetree.cb  |  9 +++++-
 .../rex/variants/screebo/overridetree.cb      | 30 +++++++++++++++++++
 4 files changed, 51 insertions(+), 3 deletions(-)

diff --git a/src/mainboard/google/rex/variants/kanix/overridetree.cb b/src/mainboard/google/rex/variants/kanix/overridetree.cb
index 2b110cead7..37f3d7ca0a 100644
--- a/src/mainboard/google/rex/variants/kanix/overridetree.cb
+++ b/src/mainboard/google/rex/variants/kanix/overridetree.cb
@@ -152,7 +152,7 @@ chip soc/intel/meteorlake
 	device domain 0 on
 		device ref igpu on
 			chip drivers/gfx/generic
-				register "device_count" = "6"
+				register "device_count" = "7"
 				# DDIA for eDP
 				register "device[0].name" = ""LCD0""
 				register "device[0].type" = "panel"
@@ -170,6 +170,11 @@ chip soc/intel/meteorlake
 				register "device[4].pld" = "ACPI_PLD_TYPE_C(LEFT, RIGHT, ACPI_PLD_GROUP(2, 1))"
 				# TCP3 (DP-4) unused
 				register "device[5].name" = ""DD05""
+				# IPUA for IPUs
+				register "device[6].name" = ""IPUA""
+				register "device[6].non_vga_device" = "true"
+				register "device[6].addr" = "0x3480"
+
 				device generic 0 on end
 			end
 		end # Integrated Graphics Device
@@ -505,6 +510,7 @@ chip soc/intel/meteorlake
 				register "acpi_uid" = "0"
 				register "acpi_name" = ""CAM0""
 				register "chip_name" = ""Hi-556 Camera""
+				register "sensor_name" = ""CJFLE25""
 				register "device_type" = "INTEL_ACPI_CAMERA_SENSOR"
 				register "has_power_resource" = "true"
 
diff --git a/src/mainboard/google/rex/variants/karis/overridetree.cb b/src/mainboard/google/rex/variants/karis/overridetree.cb
index f16560841d..c24c7c7cd7 100644
--- a/src/mainboard/google/rex/variants/karis/overridetree.cb
+++ b/src/mainboard/google/rex/variants/karis/overridetree.cb
@@ -130,7 +130,7 @@ chip soc/intel/meteorlake
 	device domain 0 on
 		device ref igpu on
 			chip drivers/gfx/generic
-				register "device_count" = "6"
+				register "device_count" = "7"
 				# DDIA for eDP
 				register "device[0].name" = ""LCD0""
 				register "device[0].type" = "panel"
@@ -148,6 +148,10 @@ chip soc/intel/meteorlake
 				register "device[4].pld" = "ACPI_PLD_TYPE_C(LEFT, RIGHT, ACPI_PLD_GROUP(2, 1))"
 				# TCP3 (DP-4) unused
 				register "device[5].name" = ""DD05""
+				# IPUA for IPUs
+				register "device[6].name" = ""IPUA""
+				register "device[6].non_vga_device" = "true"
+				register "device[6].addr" = "0x3480"
 				device generic 0 on end
 			end
 		end # Integrated Graphics Device
@@ -460,6 +464,7 @@ chip soc/intel/meteorlake
 				register "acpi_uid" = "0"
 				register "acpi_name" = ""CAM0""
 				register "chip_name" = ""Hi-556 Camera""
+				register "sensor_name" = ""CJFLE25""
 				register "device_type" = "INTEL_ACPI_CAMERA_SENSOR"
 				register "has_power_resource" = "true"
 
diff --git a/src/mainboard/google/rex/variants/rex0/overridetree.cb b/src/mainboard/google/rex/variants/rex0/overridetree.cb
index af20b62edf..d26dd567ee 100644
--- a/src/mainboard/google/rex/variants/rex0/overridetree.cb
+++ b/src/mainboard/google/rex/variants/rex0/overridetree.cb
@@ -148,7 +148,7 @@ chip soc/intel/meteorlake
 	device domain 0 on
 		device ref igpu on
 			chip drivers/gfx/generic
-				register "device_count" = "6"
+				register "device_count" = "7"
 				# DDIA for eDP
 				register "device[0].name" = ""LCD0""
 				register "device[0].type" = "panel"
@@ -167,6 +167,11 @@ chip soc/intel/meteorlake
 				register "device[4].pld" = "ACPI_PLD_TYPE_C(RIGHT, LEFT, ACPI_PLD_GROUP(2, 1))"
 				# TCP3 (DP-4) is unused for any ports but still enumerated in the kernel, so GFX device is added for TCP3
 				register "device[5].name" = ""DD05""
+				# IPUA for IPUs
+				register "device[6].name" = ""IPUA""
+				register "device[6].non_vga_device" = "true"
+				register "device[6].addr" = "0x3480"
+
 				device generic 0 on end
 			end
 		end # Integrated Graphics Device
@@ -466,6 +471,7 @@ chip soc/intel/meteorlake
 				register "acpi_uid" = "0"
 				register "acpi_name" = ""CAM0""
 				register "chip_name" = ""Ov 13b10 Camera""
+				register "sensor_name" = ""09B13U""
 				register "device_type" = "INTEL_ACPI_CAMERA_SENSOR"
 
 				register "ssdb.lanes_used" = "4"
@@ -623,6 +629,7 @@ chip soc/intel/meteorlake
 				register "acpi_uid" = "0"
 				register "acpi_name" = ""CAM1""
 				register "chip_name" = ""Hi-556 Camera""
+				register "sensor_name" = ""CJFLE25""
 				register "device_type" = "INTEL_ACPI_CAMERA_SENSOR"
 				register "has_power_resource" = "true"
 
diff --git a/src/mainboard/google/rex/variants/screebo/overridetree.cb b/src/mainboard/google/rex/variants/screebo/overridetree.cb
index 3d730a5820..60d28bcaa5 100644
--- a/src/mainboard/google/rex/variants/screebo/overridetree.cb
+++ b/src/mainboard/google/rex/variants/screebo/overridetree.cb
@@ -152,6 +152,35 @@ chip soc/intel/meteorlake
 	}"
 
 	device domain 0 on
+		device ref igpu on
+			chip drivers/gfx/generic
+				register "device_count" = "7"
+				# DDIA for eDP
+				register "device[0].name" = ""LCD0""
+				# Internal panel on the first port of the graphics chip
+				register "device[0].type" = "panel"
+				# DDIB for HDMI
+				register "device[1].name" = ""DD01""
+				# TCP0 (DP-1) for port C0
+				register "device[2].name" = ""DD02""
+				register "device[2].use_pld" = "true"
+				register "device[2].pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(1, 1))"
+				# TCP1 (DP-2) is unused for any ports but still enumerated in the kernel
+				register "device[3].name" = ""DD03""
+				# TCP2 (DP-3) for port C1
+				register "device[4].name" = ""DD04""
+				register "device[4].use_pld" = "true"
+				register "device[4].pld" = "ACPI_PLD_TYPE_C(RIGHT, RIGHT, ACPI_PLD_GROUP(2, 1))"
+				# TCP3 (DP-4) is unused for any ports but still enumerated in the kernel
+				register "device[5].name" = ""DD05""
+				# IPUA for IPUs
+				register "device[6].name" = ""IPUA""
+				register "device[6].non_vga_device" = "true"
+				register "device[6].addr" = "0x3480"
+
+				device generic 0 on end
+			end
+		end # Integrated Graphics Device
 		device ref dtt on
 			chip drivers/intel/dptf
 				## sensor information
@@ -513,6 +542,7 @@ chip soc/intel/meteorlake
 				register "acpi_uid" = "0"
 				register "acpi_name" = ""CAM0""
 				register "chip_name" = ""Ov 08X40 Camera""
+				register "sensor_name" = ""CJFME55""
 				register "device_type" = "INTEL_ACPI_CAMERA_SENSOR"
 				register "ssdb.lanes_used" = "4"
 				register "ssdb.link_used" = "4"

From 82c06da5843f1a9cd3f779b72b7436b1b7b17990 Mon Sep 17 00:00:00 2001
From: Felix Singer <felixsinger@posteo.net>
Date: Mon, 22 Dec 2025 07:10:53 +0000
Subject: [PATCH 2900/3886] 3rdparty/fsp: Update to upstream master

Updating from commit id 9623d524500c:
2025-08-21 11:29:54 -0700 - (BirchStream FSP (0041D92))

to commit id a5b3d0e056ad:
2025-12-22 09:38:25 +0800 - (Renaming directory back to "IoT" to fix the corrupted path)

This brings in 29 new commits:
a5b3d0e056ad Renaming directory back to "IoT" to fix the corrupted path
b221ba5eb8fa Renaming directory back to "IoT" to fix the corrupted path
2e4673109868 ECG BTL-S Hybrid MR2 (6311_03) FSP
07e258cd90b1 ECG BTL-S Hybrid MR2 (6311_03) FSP
8701f48b18f0 Edge Platforms ARL -S MR3 (5303_41) FSP
19e14bfd1fe6 Edge Platforms ARL-U/H MR3 (5272_44) FSP
48af2c8e8a27 Edge Platforms MTL-U/H_MTL-PS MR4 (5272_44) FSP
4da2c4207396 Edge Platforms ADL-N/ASL/TWL IPU2026.1 (v6457_50)
3eda9a327426 NEX AZB IPU 2025.2 (6033_00) FSP
066a84c5950a Edge Platforms ADL -PS IPU 2026.1 (6311_00) FSP
c18800c791d6 Edge Platforms ADL -PS IPU 2025.4 (6074_01) FSP
4e19ab2857bd Edge Platforms ADL -S IPU 2026.1 (6311_00) FSP
cd05b3f8bd07 Edge Platforms ADL -S IPU 2025.4 (6074_00) FSP
2348ab42fd74 Edge Platforms ADL -P IPU 2026.1 (6311_00) FSP
b392cfd566f2 Edge Platforms ADL -P IPU 2026.1 (6311_00) FSP
2fcf87972e49 Modify folder name
975246e2ae82 Edge Platforms RPL -S/S Refresh IPU 2026.1 (6311_00) FSP
a53f7ccb4b71 Edge Platforms RPL -P IPU 2026.1 (6311_00) FSP
77028f7f3b07 Edge Platforms ADL -PS IPU 2026.1 (6311_00) FSP
7ac503b829e6 Edge Platforms ADL -S IPU 2026.1 (6311_00) FSP
3ffd2a70fb83 Edge Platforms ADL -P IPU 2026.1 (6311_00) FSP
ba2bddbc0418 IPU2026.1
239368c7d743 Edge Platforms TGL-UP3/H IPU 2026.1 (8063_03) FSP
41d3ae12bdb6 Merge branch 'master' of https://github.com/intel/FSP
8340338aaee7 Edge Platforms RPL-PS IPU2026.1 (6311_00) FSP
7c4aaf2266e8 ECG ARL-S MR2 (5192_41) FSP
bb073b44232f ECG ARL-UH MR2 (5204_40) FSP
5d0424c89ddd IoT TWL MR1/ASL MR4 (6247_00)
e1ce5bb0748a IoT TWL MR1/ASL MR4 (6247_00)

Change-Id: Ia8084c7f8025936e694644579eeef4da37c4fe89
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90336
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
---
 3rdparty/fsp | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/3rdparty/fsp b/3rdparty/fsp
index 9623d52450..a5b3d0e056 160000
--- a/3rdparty/fsp
+++ b/3rdparty/fsp
@@ -1 +1 @@
-Subproject commit 9623d524500c140a6b11d2c727cb282b54962f09
+Subproject commit a5b3d0e056ad713f0055334427bc424f91aa6602

From 206025754f0b39627ebba7a5d7305668d65d9d9e Mon Sep 17 00:00:00 2001
From: Felix Singer <felixsinger@posteo.net>
Date: Mon, 22 Dec 2025 18:46:38 +0100
Subject: [PATCH 2901/3886] libpayload/tests: Remove unrecognized flag
 --ignore-errors inconsistent

That parameter was mistakenly added here while trying to silent lcov
complaints. Drop it again since it's not supported here.

Change-Id: I77bed4ebb7d3ef6daea39c812bacfcad7a72aee7
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90597
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
---
 payloads/libpayload/tests/Makefile.mk | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/payloads/libpayload/tests/Makefile.mk b/payloads/libpayload/tests/Makefile.mk
index 9ab8c3b71c..a6cee5f480 100644
--- a/payloads/libpayload/tests/Makefile.mk
+++ b/payloads/libpayload/tests/Makefile.mk
@@ -273,7 +273,7 @@ clean-junit.xml-unit-tests:
 
 ifeq ($(COV),1)
 coverage-report:
-	lcov --ignore-errors inconsistent -o $(testobj)/tests.info -c -d $(testobj) --exclude '$(testsrc)/*'
+	lcov -o $(testobj)/tests.info -c -d $(testobj) --exclude '$(testsrc)/*'
 	genhtml -q -o $(coverage-dir) -t "coreboot unit tests" -s $(testobj)/tests.info
 
 clean-coverage-report:

From ba5b5ea406c72570552d9b69946d669420b879c3 Mon Sep 17 00:00:00 2001
From: Yidi Lin <yidilin@google.com>
Date: Thu, 18 Dec 2025 17:03:24 +0800
Subject: [PATCH 2902/3886] soc/mediatek/mt8196: Move DPM and SPM
 initialization

Move dpm_init() and spm_init() from mainboard_init() in rauru to
soc_init() in mt8196. This centralizes the power management
initialization within the SoC-specific code.

BUG=none
TEST=Build pass, boot ok.

Change-Id: Ic2914fd0fc85032c96ce076416e9b9c46fe19e0d
Signed-off-by: Yidi Lin <yidilin@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90550
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Chen-Tsung Hsieh <chentsung@google.com>
---
 src/mainboard/google/rauru/mainboard.c |  8 --------
 src/soc/mediatek/mt8196/soc.c          | 14 +++++++++++++-
 2 files changed, 13 insertions(+), 9 deletions(-)

diff --git a/src/mainboard/google/rauru/mainboard.c b/src/mainboard/google/rauru/mainboard.c
index d0ed3ad7f7..93489426b8 100644
--- a/src/mainboard/google/rauru/mainboard.c
+++ b/src/mainboard/google/rauru/mainboard.c
@@ -7,13 +7,11 @@
 #include <soc/addressmap.h>
 #include <soc/bl31.h>
 #include <soc/display.h>
-#include <soc/dpm_v2.h>
 #include <soc/gpio_common.h>
 #include <soc/i2c.h>
 #include <soc/msdc.h>
 #include <soc/mt6373.h>
 #include <soc/pcie.h>
-#include <soc/spm_common.h>
 #include <soc/storage.h>
 #include <soc/usb.h>
 #include <variants.h>
@@ -128,12 +126,6 @@ static void mainboard_init(struct device *dev)
 	if (CONFIG(RAURU_SDCARD_INIT))
 		mtk_msdc_configure_sdcard();
 
-	if (dpm_init())
-		printk(BIOS_ERR, "dpm init failed, DVFS may not work\n");
-
-	if (spm_init())
-		printk(BIOS_ERR, "spm init failed, Suspend may not work\n");
-
 	if (CONFIG(ARM64_USE_ARM_TRUSTED_FIRMWARE))
 		register_reset_to_bl31(GPIO_AP_EC_WARM_RST_REQ.id, true);
 }
diff --git a/src/soc/mediatek/mt8196/soc.c b/src/soc/mediatek/mt8196/soc.c
index bacbe0c2c5..24077a0fbc 100644
--- a/src/soc/mediatek/mt8196/soc.c
+++ b/src/soc/mediatek/mt8196/soc.c
@@ -5,6 +5,7 @@
 #include <device/pci.h>
 #include <soc/booker.h>
 #include <soc/dcc.h>
+#include <soc/dpm_v2.h>
 #include <soc/dramc_info.h>
 #include <soc/emi.h>
 #include <soc/gpueb.h>
@@ -14,6 +15,7 @@
 #include <soc/mtk_fsp.h>
 #include <soc/pcie.h>
 #include <soc/pi_image.h>
+#include <soc/spm.h>
 #include <soc/sspm.h>
 #include <soc/storage.h>
 #include <soc/symbols.h>
@@ -54,7 +56,7 @@ static void mte_setup(void)
 	booker_mte_init(mte_start);
 }
 
-static void soc_init(struct device *dev)
+static void fsp_init(void)
 {
 	uint32_t storage_type = mainboard_get_storage_type();
 
@@ -63,8 +65,18 @@ static void soc_init(struct device *dev)
 	mtk_fsp_add_param(FSP_PARAM_TYPE_STORAGE, sizeof(storage_type), &storage_type);
 	pi_image_add_mtk_fsp_params();
 	mtk_fsp_load_and_run();
+}
 
+static void soc_init(struct device *dev)
+{
 	mtk_mmu_disable_l2c_sram();
+
+	if (dpm_init())
+		printk(BIOS_ERR, "dpm init failed, DVFS may not work\n");
+	if (spm_init())
+		printk(BIOS_ERR, "spm init failed, Suspend may not work\n");
+
+	fsp_init();
 	sspm_init();
 	gpueb_init();
 	mcupm_init();

From 61c9450d62aec2746ce1b4c24b9e7ca67cbd223b Mon Sep 17 00:00:00 2001
From: Yu-Ping Wu <yupingso@chromium.org>
Date: Fri, 19 Dec 2025 15:27:51 +0800
Subject: [PATCH 2903/3886] soc/mediatek/common: Pass dsi_regs to
 mtk_dsi_cphy_timing()

Pass dsi_regs to mtk_dsi_cphy_timing() to be consistent with other DSI
APIs and mtk_dsi_dphy_timing(). This also supports C-PHY with dual
channel, although there is currently no such a device.

BUG=b:424782827
TEST=emerge-tanjiro coreboot
BRANCH=none

Change-Id: I81805aa181c46fb29c70d18553dbf0c0c06c2888
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90558
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Chen-Tsung Hsieh <chentsung@google.com>
---
 src/soc/mediatek/common/dsi_common.c             |  3 +--
 src/soc/mediatek/common/include/soc/dsi_common.h |  3 ++-
 src/soc/mediatek/common/mtk_mipi_cphy.c          | 11 ++++++-----
 3 files changed, 9 insertions(+), 8 deletions(-)

diff --git a/src/soc/mediatek/common/dsi_common.c b/src/soc/mediatek/common/dsi_common.c
index 008817ade9..3ff8c5b049 100644
--- a/src/soc/mediatek/common/dsi_common.c
+++ b/src/soc/mediatek/common/dsi_common.c
@@ -481,8 +481,7 @@ int mtk_dsi_init(u32 mode_flags, u32 format, u32 lanes, const struct edid *edid,
 		mtk_dsi_reset(dsi);
 		struct mtk_phy_timing phy_timing = {};
 		if (CONFIG(MEDIATEK_DSI_CPHY) && is_cphy)
-			/* Dual channel is not implemented for CPHY. */
-			mtk_dsi_cphy_timing(data_rate, &phy_timing);
+			mtk_dsi_cphy_timing(dsi, data_rate, &phy_timing);
 		else
 			mtk_dsi_dphy_timing(dsi, data_rate, &phy_timing);
 
diff --git a/src/soc/mediatek/common/include/soc/dsi_common.h b/src/soc/mediatek/common/include/soc/dsi_common.h
index 57961d10bb..626e8414b6 100644
--- a/src/soc/mediatek/common/include/soc/dsi_common.h
+++ b/src/soc/mediatek/common/include/soc/dsi_common.h
@@ -174,7 +174,8 @@ void mtk_dsi_override_phy_timing(struct mtk_phy_timing *timing);
 void mtk_dsi_cphy_enable(struct mipi_tx_regs *mipi_tx_reg);
 void mtk_dsi_cphy_enable_cmdq_6byte(struct dsi_regs *dsi_reg);
 void mtk_dsi_cphy_lane_sel_setting(struct mipi_tx_regs *mipi_tx_reg);
-void mtk_dsi_cphy_timing(u32 data_rate, struct mtk_phy_timing *timing);
+void mtk_dsi_cphy_timing(struct dsi_regs *dsi_reg, u32 data_rate,
+			 struct mtk_phy_timing *timing);
 void mtk_dsi_cphy_vdo_timing(const u32 lanes, const struct edid *edid,
 			     const struct mtk_phy_timing *phy_timing,
 			     const u32 bytes_per_pixel, const u32 hbp, const u32 hfp,
diff --git a/src/soc/mediatek/common/mtk_mipi_cphy.c b/src/soc/mediatek/common/mtk_mipi_cphy.c
index 3e78376951..ecf7915f67 100644
--- a/src/soc/mediatek/common/mtk_mipi_cphy.c
+++ b/src/soc/mediatek/common/mtk_mipi_cphy.c
@@ -42,7 +42,8 @@ void mtk_dsi_cphy_enable_cmdq_6byte(struct dsi_regs *dsi_reg)
 	clrbits32(&dsi_reg->dsi_cmd_type1_hs, CMD_CPHY_6BYTE_EN);
 }
 
-void mtk_dsi_cphy_timing(u32 data_rate, struct mtk_phy_timing *timing)
+void mtk_dsi_cphy_timing(struct dsi_regs *dsi_reg, u32 data_rate,
+			 struct mtk_phy_timing *timing)
 {
 	u32 cycle_time, value;
 
@@ -72,14 +73,14 @@ void mtk_dsi_cphy_timing(u32 data_rate, struct mtk_phy_timing *timing)
 
 	value = timing->lpx | timing->da_hs_prepare << 8 |
 		  timing->da_hs_zero << 16 | timing->da_hs_trail << 24;
-	write32(&dsi0->dsi_phy_timecon0, value);
+	write32(&dsi_reg->dsi_phy_timecon0, value);
 
 	value = timing->ta_go | timing->ta_sure << 8 |
 		  timing->ta_get << 16 | timing->da_hs_exit << 24;
-	write32(&dsi0->dsi_phy_timecon1, value);
+	write32(&dsi_reg->dsi_phy_timecon1, value);
 
-	write32(&dsi0->dsi_cphy_con0, 0x012C0003);
-	write32(&dsi0->dsi_bllp_wc, 16 * 3);
+	write32(&dsi_reg->dsi_cphy_con0, 0x012C0003);
+	write32(&dsi_reg->dsi_bllp_wc, 16 * 3);
 }
 
 void mtk_dsi_cphy_vdo_timing(const u32 lanes,

From 7d50f632133e28d00c4e217cde9f8ef50737b05e Mon Sep 17 00:00:00 2001
From: Yu-Ping Wu <yupingso@chromium.org>
Date: Fri, 19 Dec 2025 16:07:31 +0800
Subject: [PATCH 2904/3886] soc/mediatek: Drop mtk_ddp_soc_mode_set()

We'd like to replace dsc_cfg->pic_width with edid->mode.ha in MT8196's
dsc_configure_registers() and then deprecate the 'pic_width' field. To
do that, we will first need to pass the edid struct pointer from
mtk_ddp_mode_set() all the way to that function.

Currently mtk_ddp_mode_set() is in the MediaTek common code, which calls
SoC's mtk_ddp_soc_mode_set(), but the edid isn't passed. To simplify the
edid pointer passing, drop mtk_ddp_soc_mode_set() and replace it with
SoC's mtk_ddp_mode_set(). To minimize the duplicate code of calculating
vrefresh, introduce mtk_get_vrefresh() to the display API, and reference
it from SoC's code.

BUG=b:424782827
TEST=emerge-tanjiro coreboot
BRANCH=none

Change-Id: Ifb84c6b954dde2f25c3ac491a5392b7725c13a43
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90559
Reviewed-by: Chen-Tsung Hsieh <chentsung@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
---
 src/soc/mediatek/common/display.c             | 34 ++++++++-----------
 src/soc/mediatek/common/include/soc/display.h |  4 +--
 src/soc/mediatek/mt8186/ddp.c                 | 11 ++++--
 src/soc/mediatek/mt8188/ddp.c                 | 11 ++++--
 src/soc/mediatek/mt8189/ddp.c                 | 11 ++++--
 src/soc/mediatek/mt8195/ddp.c                 | 11 ++++--
 src/soc/mediatek/mt8196/ddp.c                 | 11 ++++--
 7 files changed, 57 insertions(+), 36 deletions(-)

diff --git a/src/soc/mediatek/common/display.c b/src/soc/mediatek/common/display.c
index 1f7277a0e6..52d6d808f7 100644
--- a/src/soc/mediatek/common/display.c
+++ b/src/soc/mediatek/common/display.c
@@ -184,12 +184,13 @@ int mtk_display_init(void)
 	name = edid.ascii_string;
 	if (name[0] == '\0')
 		name = "unknown name";
-	printk(BIOS_INFO, "%s: '%s %s' %dx%d@%dHz\n", __func__,
-	       edid.manufacturer_name, name, edid.mode.ha, edid.mode.va,
-	       edid.mode.refresh);
 
 	edid_set_framebuffer_bits_per_pixel(&edid, 32, 0);
 
+	printk(BIOS_INFO, "%s: '%s %s' %dx%d@%dHz bpp %u\n", __func__,
+	       edid.manufacturer_name, name, edid.mode.ha, edid.mode.va,
+	       edid.mode.refresh, edid.framebuffer_bits_per_pixel / 8);
+
 	mtk_ddp_mode_set(&edid, panel->disp_path, dsc_config_var);
 
 	if (panel->disp_path == DISP_PATH_EDP) {
@@ -215,28 +216,23 @@ int mtk_display_init(void)
 	return 0;
 }
 
-void mtk_ddp_mode_set(const struct edid *edid, enum disp_path_sel path,
-		      struct dsc_config *dsc_config)
+u32 mtk_get_vrefresh(const struct edid *edid)
 {
-	u32 fmt = OVL_INFMT_RGBA8888;
-	u32 bpp = edid->framebuffer_bits_per_pixel / 8;
 	u32 width = edid->mode.ha;
 	u32 height = edid->mode.va;
 	u32 vrefresh = edid->mode.refresh;
 
-	printk(BIOS_DEBUG, "%s: display resolution: %ux%u@%u bpp %u\n", __func__, width, height,
-	       vrefresh, bpp);
+	if (vrefresh)
+		return vrefresh;
 
-	if (!vrefresh) {
-		if (!width || !height)
-			vrefresh = 60;
-		else
-			vrefresh = edid->mode.pixel_clock * 1000 /
-				   ((width + edid->mode.hbl) * (height + edid->mode.vbl));
+	if (!width || !height)
+		vrefresh = 60;
+	else
+		vrefresh = edid->mode.pixel_clock * 1000 /
+			   ((width + edid->mode.hbl) * (height + edid->mode.vbl));
 
-		printk(BIOS_WARNING, "%s: vrefresh is not provided; using %u\n", __func__,
-		       vrefresh);
-	}
+	printk(BIOS_WARNING, "%s: vrefresh is not provided; using %u\n", __func__,
+	       vrefresh);
 
-	mtk_ddp_soc_mode_set(fmt, bpp, width, height, vrefresh, path, dsc_config);
+	return vrefresh;
 }
diff --git a/src/soc/mediatek/common/include/soc/display.h b/src/soc/mediatek/common/include/soc/display.h
index c71d15bb66..62ea9b0c23 100644
--- a/src/soc/mediatek/common/include/soc/display.h
+++ b/src/soc/mediatek/common/include/soc/display.h
@@ -4,6 +4,7 @@
 #define __SOC_MEDIATEK_COMMON_DISPLAY_H__
 
 #include <commonlib/coreboot_tables.h>
+#include <edid.h>
 #include <mipi/panel.h>
 #include <stdbool.h>
 
@@ -33,8 +34,7 @@ void mtk_display_disable_secure_mode(void);
 int mtk_display_init(void);
 
 void mtk_ddp_init(void);
-void mtk_ddp_soc_mode_set(u32 fmt, u32 bpp, u32 width, u32 height, u32 vrefresh,
-			  enum disp_path_sel path, struct dsc_config *dsc_config);
+u32 mtk_get_vrefresh(const struct edid *edid);
 void mtk_ddp_mode_set(const struct edid *edid, enum disp_path_sel path,
 		      struct dsc_config *dsc_config);
 void mtk_ddp_ovlsys_start(uintptr_t fb_addr, const struct edid *edid,
diff --git a/src/soc/mediatek/mt8186/ddp.c b/src/soc/mediatek/mt8186/ddp.c
index df796fcba4..f1d17bc502 100644
--- a/src/soc/mediatek/mt8186/ddp.c
+++ b/src/soc/mediatek/mt8186/ddp.c
@@ -142,10 +142,15 @@ void mtk_ddp_init(void)
 	write32((void *)(SMI_LARB0 + SMI_LARB_PORT_L0_OVL_RDMA0), 0);
 }
 
-void mtk_ddp_soc_mode_set(u32 fmt, u32 bpp, u32 width, u32 height, u32 vrefresh,
-			  enum disp_path_sel path, struct dsc_config *dsc_config)
+void mtk_ddp_mode_set(const struct edid *edid, enum disp_path_sel path,
+		      struct dsc_config *dsc_config)
 {
+	u32 bpp = edid->framebuffer_bits_per_pixel / 8;
+	u32 width = edid->mode.ha;
+	u32 height = edid->mode.va;
+	u32 vrefresh = mtk_get_vrefresh(edid);
+
 	main_disp_path_setup(width, height, vrefresh);
 	rdma_start();
-	ovl_layer_config(fmt, bpp, width, height);
+	ovl_layer_config(OVL_INFMT_RGBA8888, bpp, width, height);
 }
diff --git a/src/soc/mediatek/mt8188/ddp.c b/src/soc/mediatek/mt8188/ddp.c
index dfc0de3217..b5d1227111 100644
--- a/src/soc/mediatek/mt8188/ddp.c
+++ b/src/soc/mediatek/mt8188/ddp.c
@@ -146,10 +146,15 @@ void mtk_ddp_init(void)
 	write32p(SMI_LARB0 + SMI_LARB_PORT_L0_OVL_RDMA0, 0);
 }
 
-void mtk_ddp_soc_mode_set(u32 fmt, u32 bpp, u32 width, u32 height, u32 vrefresh,
-			  enum disp_path_sel path, struct dsc_config *dsc_config)
+void mtk_ddp_mode_set(const struct edid *edid, enum disp_path_sel path,
+		      struct dsc_config *dsc_config)
 {
+	u32 bpp = edid->framebuffer_bits_per_pixel / 8;
+	u32 width = edid->mode.ha;
+	u32 height = edid->mode.va;
+	u32 vrefresh = mtk_get_vrefresh(edid);
+
 	main_disp_path_setup(width, height, vrefresh, path);
 	rdma_start();
-	ovl_layer_config(fmt, bpp, width, height);
+	ovl_layer_config(OVL_INFMT_RGBA8888, bpp, width, height);
 }
diff --git a/src/soc/mediatek/mt8189/ddp.c b/src/soc/mediatek/mt8189/ddp.c
index 6959fdbc1c..ec633a911e 100644
--- a/src/soc/mediatek/mt8189/ddp.c
+++ b/src/soc/mediatek/mt8189/ddp.c
@@ -138,10 +138,15 @@ void mtk_ddp_init(void)
 	       __func__, read32(&smi_larb0->port_l0_ovl_rdma[0]));
 }
 
-void mtk_ddp_soc_mode_set(u32 fmt, u32 bpp, u32 width, u32 height, u32 vrefresh,
-			  enum disp_path_sel path, struct dsc_config *dsc_config)
+void mtk_ddp_mode_set(const struct edid *edid, enum disp_path_sel path,
+		      struct dsc_config *dsc_config)
 {
+	u32 bpp = edid->framebuffer_bits_per_pixel / 8;
+	u32 width = edid->mode.ha;
+	u32 height = edid->mode.va;
+	u32 vrefresh = mtk_get_vrefresh(edid);
+
 	main_disp_path_setup(width, height, vrefresh, path);
 	rdma_start();
-	ovl_layer_config(fmt, bpp, width, height);
+	ovl_layer_config(OVL_INFMT_RGBA8888, bpp, width, height);
 }
diff --git a/src/soc/mediatek/mt8195/ddp.c b/src/soc/mediatek/mt8195/ddp.c
index 28fc34b68d..e84be64021 100644
--- a/src/soc/mediatek/mt8195/ddp.c
+++ b/src/soc/mediatek/mt8195/ddp.c
@@ -151,11 +151,16 @@ void mtk_ddp_init(void)
 	write32((void *)(SMI_LARB0 + SMI_LARB_PORT_L0_OVL_RDMA0), 0);
 }
 
-void mtk_ddp_soc_mode_set(u32 fmt, u32 bpp, u32 width, u32 height, u32 vrefresh,
-			  enum disp_path_sel path, struct dsc_config *dsc_config)
+void mtk_ddp_mode_set(const struct edid *edid, enum disp_path_sel path,
+		      struct dsc_config *dsc_config)
 {
+	u32 bpp = edid->framebuffer_bits_per_pixel / 8;
+	u32 width = edid->mode.ha;
+	u32 height = edid->mode.va;
+	u32 vrefresh = mtk_get_vrefresh(edid);
+
 	main_disp_path_setup(width, height, vrefresh);
 	rdma_start();
-	ovl_layer_config(fmt, bpp, width, height);
+	ovl_layer_config(OVL_INFMT_RGBA8888, bpp, width, height);
 	ovl_bgclr_in_sel(1);
 }
diff --git a/src/soc/mediatek/mt8196/ddp.c b/src/soc/mediatek/mt8196/ddp.c
index 012c6c9b3b..78255fb856 100644
--- a/src/soc/mediatek/mt8196/ddp.c
+++ b/src/soc/mediatek/mt8196/ddp.c
@@ -685,14 +685,19 @@ void mtk_ddp_init(void)
 	disp_clock_on();
 }
 
-void mtk_ddp_soc_mode_set(u32 fmt, u32 bpp, u32 width, u32 height, u32 vrefresh,
-			  enum disp_path_sel path, struct dsc_config *dsc_config)
+void mtk_ddp_mode_set(const struct edid *edid, enum disp_path_sel path,
+		      struct dsc_config *dsc_config)
 {
+	u32 bpp = edid->framebuffer_bits_per_pixel / 8;
+	u32 width = edid->mode.ha;
+	u32 height = edid->mode.va;
+	u32 vrefresh = mtk_get_vrefresh(edid);
+
 	if (width > 0x1FFF || height > 0x1FFF)
 		printk(BIOS_WARNING, "%s: w/h: %d/%d exceed hw limit %u\n", __func__,
 		       width, height, 0x1FFF);
 	main_disp_path_setup(width, height, vrefresh, path, dsc_config);
-	ovlsys_layer_config(fmt, bpp, width, height, path);
+	ovlsys_layer_config(OVL_INFMT_RGBA8888, bpp, width, height, path);
 }
 
 void mtk_ddp_ovlsys_start(uintptr_t fb_addr, const struct edid *edid,

From 456403d9ba38bf156ae6c1d3dc072f30a523785c Mon Sep 17 00:00:00 2001
From: Yu-Ping Wu <yupingso@chromium.org>
Date: Fri, 19 Dec 2025 16:22:06 +0800
Subject: [PATCH 2905/3886] soc/mediatek/mt8196: Stop using
 dsc_config.pic_width

The pic_width and pic_height in the dsc_config struct are equivalent to
edid.mode.ha and edid.mode.va. The duplicate information should be
removed from the panel_serializable_data struct, by removing from
dsc_config. To do that, replace references of dsc_config.pic_width with
edid.mode.ha in the MT8196 code.

BUG=b:424782827
TEST=emerge-tanjiro coreboot
BRANCH=none

Change-Id: Id1014886851a999ccdfec7ec86df2e7341ba9ffd
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90560
Reviewed-by: Chen-Tsung Hsieh <chentsung@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
---
 src/soc/mediatek/mt8196/ddp.c | 25 ++++++++++++++-----------
 1 file changed, 14 insertions(+), 11 deletions(-)

diff --git a/src/soc/mediatek/mt8196/ddp.c b/src/soc/mediatek/mt8196/ddp.c
index 78255fb856..5c4366a80e 100644
--- a/src/soc/mediatek/mt8196/ddp.c
+++ b/src/soc/mediatek/mt8196/ddp.c
@@ -69,8 +69,10 @@ static const struct disp_pipe_regs disp_pipe1_regs = {
 };
 
 static void dsc_configure_registers(struct disp_dsc_regs *reg, u16 w, u16 h,
-				    const struct dsc_config *dsc_cfg)
+				    const struct dsc_config *dsc_cfg,
+				    const struct edid *edid)
 {
+	u32 pic_width = edid->mode.ha;
 	u32 init_delay_limit, init_delay_height;
 	u32 pic_group_width, pic_height_ext_num;
 	u32 slice_group_width;
@@ -84,11 +86,11 @@ static void dsc_configure_registers(struct disp_dsc_regs *reg, u16 w, u16 h,
 	if (dsc_cfg->bits_per_component == 0xA)
 		dsc_cfg_mode = 0x828;
 
-	assert(dsc_cfg->pic_width > 0);
-	assert(dsc_cfg->pic_width >= dsc_cfg->slice_width);
+	assert(pic_width > 0);
+	assert(pic_width >= dsc_cfg->slice_width);
 	assert(dsc_cfg->slice_width > 0);
-	slice_mode = dsc_cfg->pic_width / dsc_cfg->slice_width - 1;
-	pic_group_width = DIV_ROUND_UP(dsc_cfg->pic_width, 3);
+	slice_mode = pic_width / dsc_cfg->slice_width - 1;
+	pic_group_width = DIV_ROUND_UP(pic_width, 3);
 	pic_height_ext_num = DIV_ROUND_UP(h, dsc_cfg->slice_height);
 	slice_group_width = DIV_ROUND_UP(dsc_cfg->slice_width, 3);
 	pad_num = ALIGN_PADDING(dsc_cfg->slice_chunk_size * (slice_mode + 1), 3);
@@ -139,7 +141,7 @@ static void dsc_configure_registers(struct disp_dsc_regs *reg, u16 w, u16 h,
 	val = pad_num;
 	clrsetbits32(&reg->dsc_pad, mask, val);
 
-	val = dsc_cfg->slice_width | dsc_cfg->pic_width << 16;
+	val = dsc_cfg->slice_width | pic_width << 16;
 	write32(&reg->dsc_enc_width, val);
 
 	mask = DSC_PIC_PREPAD_HEIGHT_SEL | DSC_PIC_PREPAD_WIDTH_SEL;
@@ -288,7 +290,8 @@ static void dsc_configure_registers(struct disp_dsc_regs *reg, u16 w, u16 h,
 }
 
 static void dsc_config(struct disp_dsc_regs *reg, u16 w, u16 h,
-		       const struct dsc_config *dsc_cfg)
+		       const struct dsc_config *dsc_cfg,
+		       const struct edid *edid)
 {
 	bool dsc_enable;
 
@@ -304,7 +307,7 @@ static void dsc_config(struct disp_dsc_regs *reg, u16 w, u16 h,
 		return;
 	}
 
-	dsc_configure_registers(reg, w, h, dsc_cfg);
+	dsc_configure_registers(reg, w, h, dsc_cfg, edid);
 }
 
 static void blender_config(struct blender *reg, u16 width, u16 height,
@@ -581,7 +584,7 @@ static void disp_config_blender(struct blender *const blenders[], size_t size, u
 }
 
 static void main_disp_path_setup(u16 width, u16 height, u32 vrefresh, enum disp_path_sel path,
-				 const struct dsc_config *dsc_cfg)
+				 const struct dsc_config *dsc_cfg, const struct edid *edid)
 {
 	u16 w = width;
 	size_t num_pipe = DUAL_PIPE(path) ? 2 : 1;
@@ -617,7 +620,7 @@ static void main_disp_path_setup(u16 width, u16 height, u32 vrefresh, enum disp_
 		postmask_start(pipes[i].postmask);
 		dither_config(pipes[i].dither, w, height);
 		dither_start(pipes[i].dither);
-		dsc_config(pipes[i].dsc, w, height, dsc_cfg);
+		dsc_config(pipes[i].dsc, w, height, dsc_cfg, edid);
 		dsc_start(pipes[i].dsc);
 	}
 
@@ -696,7 +699,7 @@ void mtk_ddp_mode_set(const struct edid *edid, enum disp_path_sel path,
 	if (width > 0x1FFF || height > 0x1FFF)
 		printk(BIOS_WARNING, "%s: w/h: %d/%d exceed hw limit %u\n", __func__,
 		       width, height, 0x1FFF);
-	main_disp_path_setup(width, height, vrefresh, path, dsc_config);
+	main_disp_path_setup(width, height, vrefresh, path, dsc_config, edid);
 	ovlsys_layer_config(OVL_INFMT_RGBA8888, bpp, width, height, path);
 }
 

From e6c3250912da6bff5c5bc310e775abc6efa689ce Mon Sep 17 00:00:00 2001
From: Yu-Ping Wu <yupingso@chromium.org>
Date: Fri, 19 Dec 2025 15:51:39 +0800
Subject: [PATCH 2906/3886] mipi/panel: Remove pic_width and pic_height from
 dsc_config

The pic_width and pic_height fields of dsc_config are equivalent to
edid.mode.ha and edid.mode.va, respectively. To remove duplicate
information in panel_serializable_data, remove these two fields from
dsc_config.

BUG=b:424782827
TEST=emerge-tanjiro coreboot
BRANCH=none

Change-Id: I7f1dd4b431a610fa928b29da420b0c0e0bef5fcc
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90561
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Chen-Tsung Hsieh <chentsung@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/drivers/mipi/panel-BOE_NS130069_M00.c | 2 --
 src/include/mipi/panel.h                  | 8 --------
 2 files changed, 10 deletions(-)

diff --git a/src/drivers/mipi/panel-BOE_NS130069_M00.c b/src/drivers/mipi/panel-BOE_NS130069_M00.c
index 2e2accebfa..cf36af8648 100644
--- a/src/drivers/mipi/panel-BOE_NS130069_M00.c
+++ b/src/drivers/mipi/panel-BOE_NS130069_M00.c
@@ -576,8 +576,6 @@ struct panel_serializable_data BOE_NS130069_M00 = {
 		.convert_rgb = 1,
 		.simple_422 = false,
 		.bits_per_pixel = 8 << 4,
-		.pic_height = 2190,
-		.pic_width = 3504,
 		.slice_height = 30,
 		.slice_width = 876,
 		.slice_chunk_size = 876,
diff --git a/src/include/mipi/panel.h b/src/include/mipi/panel.h
index d306f06fb4..e2123a6e22 100644
--- a/src/include/mipi/panel.h
+++ b/src/include/mipi/panel.h
@@ -85,14 +85,6 @@ struct dsc_config {
 	 * @slice_height: Slice height in pixels
 	 */
 	u16 slice_height;
-	/*
-	 * @pic_width: Width of the input display frame in pixels
-	 */
-	u16 pic_width;
-	/*
-	 * @pic_height: Vertical height of the input display frame
-	 */
-	u16 pic_height;
 	/*
 	 * @rc_tgt_offset_high:
 	 * Offset to bits/group used by RC to determine QP adjustment

From 94b326469baf5b2a993e37f6c3acf50fe16b4951 Mon Sep 17 00:00:00 2001
From: Venkateshwar S <vens@qualcomm.corp-partner.google.com>
Date: Sun, 21 Dec 2025 22:38:26 -0800
Subject: [PATCH 2907/3886] mb/google/bluey: Increase FW_MAIN_A/B slot size to
 8.5MB

This patch increases the size of the FW_MAIN_A and FW_MAIN_B slots to
8.5MB to accommodate APDP, Ramdump and ADSP-lite images. A 5MB
estimated size of QTEE image is also taken into account to avoid future
resizing.

Size required for QTEE:
  Current size -> 2776K, Estimated size -> 5120K (5MB)
  Additional size needed -> 5120K-2776K = 2344K

Size required for new images:
  Ramdump	- 449K
  APDP		- 0.7K
  ramdump_meta	- 0.1K
  apdp_meta	- 1.4K
  ADSP_Lite	- 1192K
  Total		= 1643K

Additional size needed (QTEE + new images):
  2344K+1643K = 3987K

Current Layout of FW_MAIN_A/B slots:
  Total size	- 4608K (4.5MB)
  Used size	- 4126K
  Free size	- 482K

Additional size needed (excluding free size):
  3987K-482K = 3505K

Total size of FW_MAIN_A/B slots:
  4608K+3505K = 8133K

An additional buffer of 591K is included in the final size to
provide room for increase in size of other blobs. So,

Final size of FW_MAIN_A/B slots:
  8133K+591K = 8704K (8.5MB).

TEST=Create an image.serial.bin and ensure it boots on X1P42100.

Change-Id: I3b3ba5c4bf8b5d3830174a890ea7cd089e3f274f
Signed-off-by: Venkateshwar S <vens@qualcomm.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90594
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/google/bluey/chromeos-nogsc.fmd | 4 ++--
 src/mainboard/google/bluey/chromeos.fmd       | 4 ++--
 2 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/src/mainboard/google/bluey/chromeos-nogsc.fmd b/src/mainboard/google/bluey/chromeos-nogsc.fmd
index aa6b996b3a..6ffe1d335c 100644
--- a/src/mainboard/google/bluey/chromeos-nogsc.fmd
+++ b/src/mainboard/google/bluey/chromeos-nogsc.fmd
@@ -25,13 +25,13 @@ FLASH@0x0 CONFIG_ROM_SIZE {
 		RW_NVRAM(PRESERVE) 16K
 	}
 
-	RW_SECTION_A 4608K {
+	RW_SECTION_A 8704K {
 		VBLOCK_A 8K
 		FW_MAIN_A(CBFS)
 		RW_FWID_A 256
 	}
 
-	RW_SECTION_B 4608K {
+	RW_SECTION_B 8704K {
 		VBLOCK_B 8K
 		FW_MAIN_B(CBFS)
 		RW_FWID_B 256
diff --git a/src/mainboard/google/bluey/chromeos.fmd b/src/mainboard/google/bluey/chromeos.fmd
index 98f03b5851..01a2331b22 100644
--- a/src/mainboard/google/bluey/chromeos.fmd
+++ b/src/mainboard/google/bluey/chromeos.fmd
@@ -26,13 +26,13 @@ FLASH@0x0 CONFIG_ROM_SIZE {
 		RW_NVRAM(PRESERVE) 16K
 	}
 
-	RW_SECTION_A 4608K {
+	RW_SECTION_A 8704K {
 		VBLOCK_A 8K
 		FW_MAIN_A(CBFS)
 		RW_FWID_A 256
 	}
 
-	RW_SECTION_B 4608K {
+	RW_SECTION_B 8704K {
 		VBLOCK_B 8K
 		FW_MAIN_B(CBFS)
 		RW_FWID_B 256

From bb3f40627d8368daf1c27c40ee7d3bb267c67eab Mon Sep 17 00:00:00 2001
From: Angel Pons <th3fanbus@gmail.com>
Date: Sun, 21 Dec 2025 19:14:17 +0100
Subject: [PATCH 2908/3886] util/autoport: Fix style issue in generated code

Checkpatch emits the following warning about autoport-generated code:
WARNING: space prohibited between function name and open parenthesis '('

So, simply get rid of that space.

Change-Id: If52e3d56c6b254efb61c70c8e482014dd4208172
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90584
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Nicholas <nic.c3.14@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
---
 util/autoport/ec_fixme.go | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/util/autoport/ec_fixme.go b/util/autoport/ec_fixme.go
index e0a6554016..17c431c65e 100644
--- a/util/autoport/ec_fixme.go
+++ b/util/autoport/ec_fixme.go
@@ -55,7 +55,7 @@ Method(_PTS,1)
 	MainboardInit += `
 		printk(BIOS_DEBUG, "Replaying EC dump ...");
 		for (i = 0; i < 256; i++)
-			ec_write (i, dmp[i]);
+			ec_write(i, dmp[i]);
 		printk(BIOS_DEBUG, "done\n");
 	}
 `

From dc68f5b265e4c6d96547f6e6da31763a91b6eddc Mon Sep 17 00:00:00 2001
From: Jeremy Compostella <jeremy.compostella@intel.com>
Date: Thu, 6 Nov 2025 11:28:09 -0800
Subject: [PATCH 2909/3886] soc/intel/pantherlake: Let common code set PL1 to
 TDP

Update PL1 override values from a fixed value to zero, indicating that
the platform should use the default TDP value. This change allows the
common code to dynamically set PL1 according to the specific TDP SKU,
improving flexibility and ensuring correct power limit configuration
across different hardware variants.

Previously, PL1 was hardcoded to 15 for some SKUs, which could lead to
instabilities for SKUs with different TDP requirements.

TEST=No instability was observed on certain Fatcat SKUs.

Change-Id: Ibfb6b52aa15ad66740abc39f6f869dfa5e90de3c
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89934
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Guvendik, Bora <bora.guvendik@intel.com>
Reviewed-by: Ryu, Jamie M <jamie.m.ryu@intel.com>
Reviewed-by: Kim, Wonkyu <wonkyu.kim@intel.com>
---
 src/soc/intel/pantherlake/chipset_ptl.cb | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/src/soc/intel/pantherlake/chipset_ptl.cb b/src/soc/intel/pantherlake/chipset_ptl.cb
index e646c5dc4e..ccd727d6cd 100644
--- a/src/soc/intel/pantherlake/chipset_ptl.cb
+++ b/src/soc/intel/pantherlake/chipset_ptl.cb
@@ -3,7 +3,7 @@ chip soc/intel/pantherlake
 	device cpu_cluster 0 on end
 
 	register "power_limits_config[PTL_CORE_1]" = "{
-		.tdp_pl1_override = 15,
+		.tdp_pl1_override = 0, /* Use TDP */
 		.tdp_pl2_override = 55,
 		.tdp_pl4 = 163,
 		.tdp_pl4_fastvmode = 150,
@@ -24,7 +24,7 @@ chip soc/intel/pantherlake
 	}"
 
 	register "power_limits_config[PTL_CORE_2]" = "{
-		.tdp_pl1_override = 15,
+		.tdp_pl1_override = 0,  /* Use TDP */
 		.tdp_pl2_override = 55,
 		.tdp_pl4 = 163,
 		.tdp_pl4_fastvmode = 150,
@@ -37,7 +37,7 @@ chip soc/intel/pantherlake
 	}"
 
 	register "power_limits_config[PTL_CORE_3]" = "{
-		.tdp_pl1_override = 25,
+		.tdp_pl1_override = 0,  /* Use TDP */
 		.tdp_pl2_override = 65,
 		.tdp_pl4 = 175,
 		.tdp_pl4_fastvmode = 160,
@@ -58,7 +58,7 @@ chip soc/intel/pantherlake
 	}"
 
 	register "power_limits_config[PTL_CORE_4]" = "{
-		.tdp_pl1_override = 25,
+		.tdp_pl1_override = 0,  /* Use TDP */
 		.tdp_pl2_override = 65,
 		.tdp_pl4 = 160,
 		.tdp_pl4_fastvmode = 140

From 1dfa80f02cbfd9ce49e18a9e4e18799d7c0b642c Mon Sep 17 00:00:00 2001
From: Jeremy Compostella <jeremy.compostella@intel.com>
Date: Fri, 21 Nov 2025 12:13:28 -0800
Subject: [PATCH 2910/3886] soc/intel/pantherlake: Add configurable TDP support

This commit introduces a mechanism to configure the Thermal Design Power
(TDP) for Panther Lake, allowing board designers to override the default
TDP reported by hardware and select the value that matches their
specific board requirements.

Previously, the TDP value was determined solely by the hardware, which
limited flexibility for platforms that support multiple TDP options. By
adding a new field to the `soc_intel_pantherlake_config` structure and
implementing the `soc_get_cpu_tdp()` function, this change enables
boards to opt out of the default TDP and specify a custom value.

BUG=b:465698900

Change-Id: I6e401c2c7d7d0cda24fa07ec024813874fac3ed5
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90150
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/soc/intel/pantherlake/Makefile.mk           |  2 ++
 src/soc/intel/pantherlake/chip.h                |  9 +++++++++
 src/soc/intel/pantherlake/romstage/fsp_params.c |  3 ++-
 src/soc/intel/pantherlake/systemagent.c         |  6 ++++--
 src/soc/intel/pantherlake/tdp.c                 | 12 ++++++++++++
 src/soc/intel/pantherlake/tdp.h                 | 10 ++++++++++
 6 files changed, 39 insertions(+), 3 deletions(-)
 create mode 100644 src/soc/intel/pantherlake/tdp.c
 create mode 100644 src/soc/intel/pantherlake/tdp.h

diff --git a/src/soc/intel/pantherlake/Makefile.mk b/src/soc/intel/pantherlake/Makefile.mk
index 6476bf6e36..ab118c5055 100644
--- a/src/soc/intel/pantherlake/Makefile.mk
+++ b/src/soc/intel/pantherlake/Makefile.mk
@@ -24,6 +24,7 @@ romstage-y += espi.c
 romstage-y += meminit.c
 romstage-y += pcie_rp.c
 romstage-y += reset.c
+romstage-y += tdp.c
 
 ramstage-y += acpi.c
 ramstage-y += cbfs_preload.c
@@ -43,6 +44,7 @@ ramstage-y += retimer.c
 ramstage-y += soundwire.c
 ramstage-y += systemagent.c
 ramstage-y += tcss.c
+ramstage-y += tdp.c
 ramstage-y += xhci.c
 ramstage-$(CONFIG_DRIVERS_INTEL_TOUCH) += touch.c
 
diff --git a/src/soc/intel/pantherlake/chip.h b/src/soc/intel/pantherlake/chip.h
index d383d63fa5..1301813aaf 100644
--- a/src/soc/intel/pantherlake/chip.h
+++ b/src/soc/intel/pantherlake/chip.h
@@ -485,6 +485,15 @@ struct soc_intel_pantherlake_config {
 	uint16_t ps2_threshold[NUM_VR_DOMAINS];
 	uint16_t ps3_threshold[NUM_VR_DOMAINS];
 
+	/*
+	 * Thermal Design Power setting.
+	 *
+	 * Certain Panther Lake SKUs are compatible with multiple TDP options. For these
+	 * SKUs, the following field can be set to choose the TDP that best fits the
+	 * board's power and thermal requirements.
+	 */
+	enum soc_intel_pantherlake_cpu_tdps tdp;
+
 	/*
 	 * SerialIO device mode selection:
 	 * PchSerialIoDisabled,
diff --git a/src/soc/intel/pantherlake/romstage/fsp_params.c b/src/soc/intel/pantherlake/romstage/fsp_params.c
index 63a3f3b013..46458af5ce 100644
--- a/src/soc/intel/pantherlake/romstage/fsp_params.c
+++ b/src/soc/intel/pantherlake/romstage/fsp_params.c
@@ -14,6 +14,7 @@
 #include <soc/msr.h>
 #include <soc/pcie.h>
 #include <soc/romstage.h>
+#include <tdp.h>
 #include <static.h>
 
 #include "ux.h"
@@ -321,7 +322,7 @@ static const struct soc_intel_pantherlake_power_map *get_map(const struct soc_in
 		return NULL;
 	}
 
-	uint8_t tdp = get_cpu_tdp();
+	enum soc_intel_pantherlake_cpu_tdps tdp = soc_get_cpu_tdp();
 	for (size_t i = 0; i < ARRAY_SIZE(cpuid_to_ptl); i++) {
 		const struct soc_intel_pantherlake_power_map *current = &cpuid_to_ptl[i];
 		if (current->cpu_id == sa_pci_id && current->cpu_tdp == tdp)
diff --git a/src/soc/intel/pantherlake/systemagent.c b/src/soc/intel/pantherlake/systemagent.c
index 82e5d244c7..c1a081cb1b 100644
--- a/src/soc/intel/pantherlake/systemagent.c
+++ b/src/soc/intel/pantherlake/systemagent.c
@@ -16,6 +16,7 @@
 #include <soc/soc_chip.h>
 #include <soc/systemagent.h>
 #include <static.h>
+#include <tdp.h>
 
 /*
  * SoC implementation
@@ -145,7 +146,7 @@ static void configure_tdp(struct device *dev)
 	struct soc_power_limits_config *soc_config;
 	struct device *sa;
 	uint16_t sa_pci_id;
-	u8 tdp;
+	enum soc_intel_pantherlake_cpu_tdps tdp;
 	size_t i;
 	bool config_tdp = false;
 	struct soc_intel_pantherlake_config *config;
@@ -161,7 +162,7 @@ static void configure_tdp(struct device *dev)
 		return;
 	}
 
-	tdp = get_cpu_tdp();
+	tdp = soc_get_cpu_tdp();
 
 	/*
 	 * Choose power limits configuration based on the CPU SA PCI ID and
@@ -174,6 +175,7 @@ static void configure_tdp(struct device *dev)
 			if (config->enable_fast_vmode[VR_DOMAIN_IA] &&
 			    soc_config->tdp_pl4_fastvmode)
 				soc_config->tdp_pl4 = soc_config->tdp_pl4_fastvmode;
+			soc_config->tdp_pl1_override = tdp;
 			set_power_limits(MOBILE_SKU_PL1_TIME_SEC, soc_config);
 			config_tdp = true;
 			printk(BIOS_DEBUG, "Configured power limits for SA PCI ID: 0x%4x\n",
diff --git a/src/soc/intel/pantherlake/tdp.c b/src/soc/intel/pantherlake/tdp.c
new file mode 100644
index 0000000000..e73370a69f
--- /dev/null
+++ b/src/soc/intel/pantherlake/tdp.c
@@ -0,0 +1,12 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <device/pci.h>
+#include <soc/pci_devs.h>
+#include <static.h>
+#include <tdp.h>
+
+enum soc_intel_pantherlake_cpu_tdps soc_get_cpu_tdp(void)
+{
+	const struct soc_intel_pantherlake_config *config = config_of_soc();
+	return config->tdp || get_cpu_tdp();
+}
diff --git a/src/soc/intel/pantherlake/tdp.h b/src/soc/intel/pantherlake/tdp.h
new file mode 100644
index 0000000000..46f5188a24
--- /dev/null
+++ b/src/soc/intel/pantherlake/tdp.h
@@ -0,0 +1,10 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef _SOC_PANTHERLAKE_TDP_H_
+#define _SOC_PANTHERLAKE_TDP_H_
+
+#include <chip.h>
+
+enum soc_intel_pantherlake_cpu_tdps soc_get_cpu_tdp(void);
+
+#endif /* _SOC_PANTHERLAKE_TDP_H_ */

From 3f00ecb05c3aabacc89b860bf63fc2356f2c6711 Mon Sep 17 00:00:00 2001
From: Jeremy Compostella <jeremy.compostella@intel.com>
Date: Thu, 4 Dec 2025 15:28:54 -0800
Subject: [PATCH 2911/3886] soc/intel/pantherlake: Add ChromeOS board-specific
 TDP setting

This commit introduces ChromeOS-specific logic to the Panther Lake SoC
TDP selection. It addresses the need to correctly set the CPU TDP to 15
W without having to set the desired_tdp flag in each mainboard device
tree.

BUG=b:465698900

Change-Id: Ibaee530159f7e3b94aac16ab50b749cb161cee10
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90373
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
---
 src/soc/intel/pantherlake/tdp.c | 13 +++++++++++++
 1 file changed, 13 insertions(+)

diff --git a/src/soc/intel/pantherlake/tdp.c b/src/soc/intel/pantherlake/tdp.c
index e73370a69f..63b3072499 100644
--- a/src/soc/intel/pantherlake/tdp.c
+++ b/src/soc/intel/pantherlake/tdp.c
@@ -7,6 +7,19 @@
 
 enum soc_intel_pantherlake_cpu_tdps soc_get_cpu_tdp(void)
 {
+	if (CONFIG(MAINBOARD_HAS_CHROMEOS)) {
+		const unsigned int variable_tdp_mch_ids[] = {
+			PCI_DID_INTEL_PTL_U_ID_1,
+			PCI_DID_INTEL_PTL_U_ID_2,
+			PCI_DID_INTEL_PTL_U_ID_3
+		};
+		uint16_t mch_id = pci_read_config16(_PCI_DEV(ROOT, 0), PCI_DEVICE_ID);
+
+		for (size_t i = 0; i < ARRAY_SIZE(variable_tdp_mch_ids); i++)
+			if (variable_tdp_mch_ids[i] == mch_id)
+				return TDP_15W;
+	}
+
 	const struct soc_intel_pantherlake_config *config = config_of_soc();
 	return config->tdp || get_cpu_tdp();
 }

From 75333ea7c8497457bab92ce1df01d06a6408caaa Mon Sep 17 00:00:00 2001
From: Kapil Porwal <kapilporwal@google.com>
Date: Mon, 22 Dec 2025 19:19:33 +0530
Subject: [PATCH 2912/3886] mb/google/bluey: Refactor is_pd_sync_required
 function

BUG=none
TEST=Verify boot on Google/Quenbi.

Change-Id: Ic2f779d963105ef24b9cae3747ac7cc78ec9ae8b
Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90596
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/google/bluey/romstage.c | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/src/mainboard/google/bluey/romstage.c b/src/mainboard/google/bluey/romstage.c
index e21777b715..dbfda5511e 100644
--- a/src/mainboard/google/bluey/romstage.c
+++ b/src/mainboard/google/bluey/romstage.c
@@ -55,11 +55,11 @@ static bool is_pd_sync_required(void)
 		EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN));
 	uint64_t ec_events = google_chromeec_get_events_b();
 
-	if (!(ec_events & manual_pwron_event_mask) &&
-		(ec_events & EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_CONNECTED)))
-		return true;
+	if (!(ec_events & EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_CONNECTED)))
+		return false;
 
-	if (google_chromeec_is_below_critical_threshold() || !google_chromeec_is_battery_present())
+	if (!(ec_events & manual_pwron_event_mask) ||
+		google_chromeec_is_below_critical_threshold() || !google_chromeec_is_battery_present())
 		return true;
 
 	return false;

From 7d38a96c44c9d97550f7f8e1ad379490fed6d037 Mon Sep 17 00:00:00 2001
From: Frank Wu <frank_wu@compal.corp-partner.google.com>
Date: Mon, 22 Dec 2025 18:45:19 +0800
Subject: [PATCH 2913/3886] mb/google/skywalker: Create variant Vader

Create the variant Vader.

BUG=b:470833369
TEST=emerge-skywalker coreboot
BRANCH=skywalker

Change-Id: I92ace678b9b9206c36ed147426699cef6510b210
Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90595
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Chen-Tsung Hsieh <chentsung@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
---
 src/mainboard/google/skywalker/Kconfig      | 2 ++
 src/mainboard/google/skywalker/Kconfig.name | 3 +++
 2 files changed, 5 insertions(+)

diff --git a/src/mainboard/google/skywalker/Kconfig b/src/mainboard/google/skywalker/Kconfig
index 6e8848af94..6556acae99 100644
--- a/src/mainboard/google/skywalker/Kconfig
+++ b/src/mainboard/google/skywalker/Kconfig
@@ -10,6 +10,7 @@ config BOARD_GOOGLE_SKYWALKER_COMMON
 		 BOARD_GOOGLE_PADME || \
 		 BOARD_GOOGLE_SKYWALKER || \
 		 BOARD_GOOGLE_TARKIN || \
+		 BOARD_GOOGLE_VADER || \
 		 BOARD_GOOGLE_YODA
 
 if BOARD_GOOGLE_SKYWALKER_COMMON
@@ -59,6 +60,7 @@ config MAINBOARD_PART_NUMBER
 	default "Padme" if BOARD_GOOGLE_PADME
 	default "Skywalker" if BOARD_GOOGLE_SKYWALKER
 	default "Tarkin" if BOARD_GOOGLE_TARKIN
+	default "Vader" if BOARD_GOOGLE_VADER
 	default "Yoda" if BOARD_GOOGLE_YODA
 
 config BOOT_DEVICE_SPI_FLASH_BUS
diff --git a/src/mainboard/google/skywalker/Kconfig.name b/src/mainboard/google/skywalker/Kconfig.name
index 258c8bd633..6f787c72b9 100644
--- a/src/mainboard/google/skywalker/Kconfig.name
+++ b/src/mainboard/google/skywalker/Kconfig.name
@@ -26,5 +26,8 @@ config BOARD_GOOGLE_SKYWALKER
 config BOARD_GOOGLE_TARKIN
 	bool "->  Tarkin"
 
+config BOARD_GOOGLE_VADER
+	bool "->  Vader"
+
 config BOARD_GOOGLE_YODA
 	bool "->  Yoda"

From 331e93cbd23b5000e97b96592300bb615f913bed Mon Sep 17 00:00:00 2001
From: Felix Singer <felixsinger@posteo.net>
Date: Tue, 23 Dec 2025 18:53:22 +0100
Subject: [PATCH 2914/3886] libpayload/tests: Disable generation of lcov HTML

Commit de4148888c9c ("tests: Disable generation of lcov HTML") only
disabled the HTML generation for the coreboot tests, but not for
libpayload tests. So do it here as well.

Change-Id: I35458345c81de8b9936a17bb6fb5670b29a6d05e
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90608
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 payloads/libpayload/tests/Makefile.mk | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/payloads/libpayload/tests/Makefile.mk b/payloads/libpayload/tests/Makefile.mk
index a6cee5f480..6b6c78d835 100644
--- a/payloads/libpayload/tests/Makefile.mk
+++ b/payloads/libpayload/tests/Makefile.mk
@@ -274,7 +274,8 @@ clean-junit.xml-unit-tests:
 ifeq ($(COV),1)
 coverage-report:
 	lcov -o $(testobj)/tests.info -c -d $(testobj) --exclude '$(testsrc)/*'
-	genhtml -q -o $(coverage-dir) -t "coreboot unit tests" -s $(testobj)/tests.info
+	# TODO: figure out issues with inconsistent and corrupt data
+	# genhtml -q -o $(coverage-dir) -t "coreboot unit tests" -s $(testobj)/tests.info
 
 clean-coverage-report:
 	rm -Rf $(coverage-dir)

From 531c24cd0a53f2b9383af12b9f64c8f63a3e954b Mon Sep 17 00:00:00 2001
From: Zhaoming Luo <zhml@posteo.com>
Date: Mon, 22 Dec 2025 21:36:56 +0800
Subject: [PATCH 2915/3886] Documentation: Fix typo in 'particularly'

Correct 'particullary' to 'particularly'.

Change-Id: I6a4b78db143298b1b60106031fdd5d698ccf1e32
Signed-off-by: Zhaoming Luo <zhml@posteo.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90605
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
---
 Documentation/getting_started/architecture.md | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/Documentation/getting_started/architecture.md b/Documentation/getting_started/architecture.md
index 8910d775f7..1f360d0486 100644
--- a/Documentation/getting_started/architecture.md
+++ b/Documentation/getting_started/architecture.md
@@ -41,7 +41,7 @@ The bootblock loads the romstage or the verstage if verified boot is enabled.
 
 ### Cache-As-Ram
 The *Cache-As-Ram*, also called Non-Eviction mode, or *CAR* allows to use the
-CPU cache like regular SRAM. This is particullary useful for high level
+CPU cache like regular SRAM. This is particularly useful for high level
 languages like `C`, which need RAM for heap and stack.
 
 The CAR needs to be activated using vendor specific CPU instructions.

From c093b52c20501a5ae3ddb5651b1effb5fc6598f6 Mon Sep 17 00:00:00 2001
From: Payne Lin <payne.lin@mediatek.corp-partner.google.com>
Date: Wed, 24 Dec 2025 15:47:37 +0800
Subject: [PATCH 2916/3886] soc/mediatek: Correct BIAS_ON value to get bias
 ready

Fix the value of BIAS_POWER_ON in the MT8189 dptx_reg.h file,
by changing it from 0x01 to 0x03. The MT8189 needs to enable one
more power register bit to make bias work rather than timeout.

BUG=b:461384417
TEST=Boot up can see develop mode.
BRANCH=skywalker

Signed-off-by: Payne Lin <payne.lin@mediatek.corp-partner.google.com>
Change-Id: I345b23af0b5802e71d6d7bcd3fe806aaa71cc3cc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90613
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
---
 src/soc/mediatek/common/dp/include/soc/dptx_reg_v2.h | 1 -
 src/soc/mediatek/mt8189/include/soc/dptx_reg.h       | 1 +
 src/soc/mediatek/mt8196/include/soc/dptx_reg.h       | 1 +
 3 files changed, 2 insertions(+), 1 deletion(-)

diff --git a/src/soc/mediatek/common/dp/include/soc/dptx_reg_v2.h b/src/soc/mediatek/common/dp/include/soc/dptx_reg_v2.h
index da0654ab9d..d1f4f411ef 100644
--- a/src/soc/mediatek/common/dp/include/soc/dptx_reg_v2.h
+++ b/src/soc/mediatek/common/dp/include/soc/dptx_reg_v2.h
@@ -157,7 +157,6 @@
 #define REG_3F44_DP_ENC_4P_3				0x3F44
 #define PHY_PWR_STATE_OW_EN_DP_ENC_4P_3			BIT(2)
 #define PHY_PWR_STATE_OW_EN_DP_ENC_4P_3_MASK		BIT(2)
-#define BIAS_POWER_ON					(0x01 << 3)
 #define PHY_PWR_STATE_OW_VALUE_DP_ENC_4P_3_MASK		GENMASK(4, 3)
 #define REG_3F80_DP_ENC_4P_3				0x3F80
 #define PSR_PATGEN_AVT_EN_FLDMASK			0x20
diff --git a/src/soc/mediatek/mt8189/include/soc/dptx_reg.h b/src/soc/mediatek/mt8189/include/soc/dptx_reg.h
index af2e6a131e..b65d6c2bed 100644
--- a/src/soc/mediatek/mt8189/include/soc/dptx_reg.h
+++ b/src/soc/mediatek/mt8189/include/soc/dptx_reg.h
@@ -5,6 +5,7 @@
 
 #include <soc/dptx_reg_v2.h>
 
+#define BIAS_POWER_ON				(0x03 << 3)
 #define DP_PHY_DIG_TX_CTL_0			0x1444
 #define RGS_AUX_LDO_EN_READY_MASK		BIT(0)
 #define DRIVING_FORCE				0x18
diff --git a/src/soc/mediatek/mt8196/include/soc/dptx_reg.h b/src/soc/mediatek/mt8196/include/soc/dptx_reg.h
index df7a29630a..a26328dd24 100644
--- a/src/soc/mediatek/mt8196/include/soc/dptx_reg.h
+++ b/src/soc/mediatek/mt8196/include/soc/dptx_reg.h
@@ -5,6 +5,7 @@
 
 #include <soc/dptx_reg_v2.h>
 
+#define BIAS_POWER_ON					(0x01 << 3)
 #define DP_PHY_DIG_TX_CTL_0				0x1474
 #define RGS_AUX_LDO_EN_READY_MASK			BIT(1)
 #define DRIVING_FORCE					0x30

From aeb9dcf2fab17ebcb7ddc2f28c39ccd3ab8169d0 Mon Sep 17 00:00:00 2001
From: Yidi Lin <yidilin@google.com>
Date: Wed, 24 Dec 2025 15:23:28 +0800
Subject: [PATCH 2917/3886] libpayload: Add new memory type CB_MEM_TAG

Add new memory type CB_MEM_TAG to coreboot_tables.h. This definition was
missing when CB:90470 was instroduced.

Change-Id: I76990706649bc1a4e45478760446dff40e871d77
Signed-off-by: Yidi Lin <yidilin@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90612
Reviewed-by: Chen-Tsung Hsieh <chentsung@google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 payloads/libpayload/include/coreboot_tables.h | 1 +
 1 file changed, 1 insertion(+)

diff --git a/payloads/libpayload/include/coreboot_tables.h b/payloads/libpayload/include/coreboot_tables.h
index 2f5b9be228..89b0dbc0a4 100644
--- a/payloads/libpayload/include/coreboot_tables.h
+++ b/payloads/libpayload/include/coreboot_tables.h
@@ -121,6 +121,7 @@ struct cb_memory_range {
 #define CB_MEM_NVS          4
 #define CB_MEM_UNUSABLE     5
 #define CB_MEM_VENDOR_RSVD  6
+#define CB_MEM_TAG          7
 #define CB_MEM_TABLE       16
 
 struct cb_memory {

From f24a2f35bfa3c3adb1b11c17ddc1e5ce0d6110fd Mon Sep 17 00:00:00 2001
From: Walter Sonius <walterav1984@gmail.com>
Date: Thu, 25 Dec 2025 11:33:35 +0100
Subject: [PATCH 2918/3886] mb/asrock: Correct vendor name ASROCK to ASRock

Both ASRock H110 Pro BTC+ and ASRock Q1900-ITX have their vendor name
spelled as ASRock listed by Memtest86+ when ran on their OEM BIOS. This
patch will restore that vendor name casing behaviour when Memtest86+ is
run from a corebooted port of these mainboards. Cannot verify for the
current mainboards in the repository but this casing is also consistent
with the casing used on the vendor website: www.asrock.com

Change-Id: Icca8a0c0cba4e093a64cc26996de1fb34ee60089
Signed-off-by: Walter Sonius <walterav1984@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90623
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
---
 src/mainboard/asrock/Kconfig      | 2 +-
 src/mainboard/asrock/Kconfig.name | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/mainboard/asrock/Kconfig b/src/mainboard/asrock/Kconfig
index 3fe439728d..ddbe9f5b0e 100644
--- a/src/mainboard/asrock/Kconfig
+++ b/src/mainboard/asrock/Kconfig
@@ -12,6 +12,6 @@ endchoice
 source "src/mainboard/asrock/*/Kconfig"
 
 config MAINBOARD_VENDOR
-	default "ASROCK"
+	default "ASRock"
 
 endif # VENDOR_ASROCK
diff --git a/src/mainboard/asrock/Kconfig.name b/src/mainboard/asrock/Kconfig.name
index a04cd2707b..c19475ee00 100644
--- a/src/mainboard/asrock/Kconfig.name
+++ b/src/mainboard/asrock/Kconfig.name
@@ -1,4 +1,4 @@
 ## SPDX-License-Identifier: GPL-2.0-only
 
 config VENDOR_ASROCK
-	bool "ASROCK"
+	bool "ASRock"

From ffac7d90dae961967c503da51e349e7ec8c619a6 Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Tue, 23 Dec 2025 16:17:41 +0000
Subject: [PATCH 2919/3886] soc/intel/cnvi: Correct error values for _RST

The saved error values were reversed, so correct these.

This isn't a functional change, as the value isn't used in ACPI.

Change-Id: I9d3abcb4b17c36d33f2660e5d20fd5e6fb15fc34
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90606
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
---
 src/soc/intel/common/block/cnvi/cnvi.c | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/src/soc/intel/common/block/cnvi/cnvi.c b/src/soc/intel/common/block/cnvi/cnvi.c
index 9314c989ed..d7c07819de 100644
--- a/src/soc/intel/common/block/cnvi/cnvi.c
+++ b/src/soc/intel/common/block/cnvi/cnvi.c
@@ -205,12 +205,12 @@ static void cnvw_fill_ssdt(const struct device *dev)
  *						}
  *						Else
  *						{
- *							PRRS = CNVI_PLDR_NOT_COMPLETE
+ *							PRRS = CNVI_PLDR_TIMEOUT
  *						}
  *					}
  *					Else
  *					{
- *						PRRS = CNVI_PLDR_TIMEOUT
+ *						PRRS = CNVI_PLDR_NOT_COMPLETE
  *					}
  *				}
  *				Release (\_SB.PCI0.CNMT)
@@ -363,13 +363,13 @@ static void cnvw_fill_ssdt(const struct device *dev)
 						}
 						acpigen_write_else();
 						{
-							acpigen_write_store_int_to_namestr(CNVI_PLDR_NOT_COMPLETE, "PRRS");
+							acpigen_write_store_int_to_namestr(CNVI_PLDR_TIMEOUT, "PRRS");
 						}
 						acpigen_pop_len();
 					}
 					acpigen_write_else();
 					{
-						acpigen_write_store_int_to_namestr(CNVI_PLDR_TIMEOUT, "PRRS");
+						acpigen_write_store_int_to_namestr(CNVI_PLDR_NOT_COMPLETE, "PRRS");
 					}
 					acpigen_pop_len();
 				}

From ea045bd322c0925f7e3ed463246e3164976f256f Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Tue, 23 Dec 2025 16:19:52 +0000
Subject: [PATCH 2920/3886] soc/intel/cnvi: Re-enable Bluetooth on reset
 timeout

The current code left Bluetooth disabled if it times out during reset.
Following the flow of the reference code, re-enable it to avoid it
ending up "stuck" off.

Change-Id: Ib1c49f28ec13068d9d7e59841ae35d1d26c30770
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90607
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/soc/intel/common/block/cnvi/cnvi.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/src/soc/intel/common/block/cnvi/cnvi.c b/src/soc/intel/common/block/cnvi/cnvi.c
index d7c07819de..817895af7d 100644
--- a/src/soc/intel/common/block/cnvi/cnvi.c
+++ b/src/soc/intel/common/block/cnvi/cnvi.c
@@ -206,6 +206,7 @@ static void cnvw_fill_ssdt(const struct device *dev)
  *						Else
  *						{
  *							PRRS = CNVI_PLDR_TIMEOUT
+ *							\_SB.PCI0.BTRK (One)
  *						}
  *					}
  *					Else
@@ -364,6 +365,8 @@ static void cnvw_fill_ssdt(const struct device *dev)
 						acpigen_write_else();
 						{
 							acpigen_write_store_int_to_namestr(CNVI_PLDR_TIMEOUT, "PRRS");
+							acpigen_emit_namestring("\\_SB.PCI0.BTRK");
+							acpigen_emit_byte(1);
 						}
 						acpigen_pop_len();
 					}

From 4631f94e51aab5312c14ecaf29f0669b55fc1277 Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Tue, 23 Dec 2025 20:13:56 +0000
Subject: [PATCH 2921/3886] drivers/usb/intel_bluetooth: Advertise D2 for S0W

Bluetooth only signal wake while in USB suspend (D2). It is not possible
for it to wake when in D3 (low-power mode) so D3 is incorrect.

Change-Id: I1c2052507dfae235140e667b9a5580b4a7a8cb5d
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90609
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/drivers/usb/acpi/intel_bluetooth.c | 24 ++----------------------
 1 file changed, 2 insertions(+), 22 deletions(-)

diff --git a/src/drivers/usb/acpi/intel_bluetooth.c b/src/drivers/usb/acpi/intel_bluetooth.c
index 4c882cde9d..e9488d3968 100644
--- a/src/drivers/usb/acpi/intel_bluetooth.c
+++ b/src/drivers/usb/acpi/intel_bluetooth.c
@@ -50,29 +50,9 @@ void acpi_device_intel_bt(const struct acpi_gpio *enable_gpio,
 			  bool audio_offload)
 {
 /*
- *	Name (_S0W, 3)
+ *	Name (_S0W, 2)
  */
-	if (get_uint_option("bluetooth_rtd3", 1))
-		acpigen_write_name_integer("_S0W", ACPI_DEVICE_SLEEP_D3_HOT);
-	else
-		acpigen_write_name_integer("_S0W", ACPI_DEVICE_SLEEP_D0);
-
-/*
- *	Name (_DSD, Package (0x02)
- *	{
- *		ToUUID ("6211e2c0-58a3-4af3-90e1-927a4e0c55a4")
- *		Package (0x01)
- *		{
- *			Package (0x02)
- *			{
- *				"HotPlugSupportInD3",
- *				One
- *			}
- *		}
- *	})
- *
- */
-	acpi_device_add_hotplug_support_in_d3(NULL);
+	acpigen_write_name_integer("_S0W", ACPI_DEVICE_SLEEP_D2);
 
 /*
  *	Name (RDLY, 0x69)

From 091ac1005987a2c523341d08a9e0f82b3e622037 Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Tue, 23 Dec 2025 20:17:21 +0000
Subject: [PATCH 2922/3886] soc/intel/cnvi: Correct S-state level for CNVP

This power resource is valid in S5, so correct the level that is
set. This makes it match the reference code, and the CNVi Bluetooth
power resource.

Change-Id: I430cafafc0326dc189a337bf2b67cf200afc4f17
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90610
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/soc/intel/common/block/cnvi/cnvi.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/soc/intel/common/block/cnvi/cnvi.c b/src/soc/intel/common/block/cnvi/cnvi.c
index 817895af7d..80fed3a23d 100644
--- a/src/soc/intel/common/block/cnvi/cnvi.c
+++ b/src/soc/intel/common/block/cnvi/cnvi.c
@@ -120,7 +120,7 @@ static void cnvw_fill_ssdt(const struct device *dev)
 	acpigen_write_name_integer("WFDL", 50);
 
 /*
- *	PowerResource (CNVP, 0x00, 0x0000)
+ *	PowerResource (CNVP, 0x05, 0x0000)
  *	{
  *		Method (_STA, 0, NotSerialized)  // _STA: Status
  *		{
@@ -220,7 +220,7 @@ static void cnvw_fill_ssdt(const struct device *dev)
  *	}
  *
  */
-	acpigen_write_power_res("CNVP", 0, 0, NULL, 0);
+	acpigen_write_power_res("CNVP", 5, 0, NULL, 0);
 	{
 		acpigen_write_method("_STA", 0);
 		{

From 7c3d45d94fc4a44d0b6766bb59a5d082514e7fd8 Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Tue, 23 Dec 2025 20:18:50 +0000
Subject: [PATCH 2923/3886] drivers/usb/intel_bluetooth: Correct S-state level
 for power resource

This power resource is valid in S5, so correct the advertised level.

Change-Id: I208182a7633c03d818a5b8892d305e3bcd5b835f
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90611
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
---
 src/drivers/usb/acpi/intel_bluetooth.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/drivers/usb/acpi/intel_bluetooth.c b/src/drivers/usb/acpi/intel_bluetooth.c
index e9488d3968..2ccb13bfe8 100644
--- a/src/drivers/usb/acpi/intel_bluetooth.c
+++ b/src/drivers/usb/acpi/intel_bluetooth.c
@@ -108,7 +108,7 @@ void acpi_device_intel_bt(const struct acpi_gpio *enable_gpio,
 
 	acpigen_write_dsm_uuid_arr(uuid_callbacks, ARRAY_SIZE(uuid_callbacks));
 /*
- *	PowerResource (BTRT, 0, 0)
+ *	PowerResource (BTRT, 0x05, 0)
  *	{
  *		Method (_STA, 0, NotSerialized)
  *		{
@@ -139,7 +139,7 @@ void acpi_device_intel_bt(const struct acpi_gpio *enable_gpio,
  *		}
  *	}
  */
-	acpigen_write_power_res("BTRT", 0, 0, NULL, 0);
+	acpigen_write_power_res("BTRT", 5, 0, NULL, 0);
 	{
 		acpigen_write_method("_STA", 0);
 		{

From 06c83d473b2682203fcf9ce8f64c399abff9e3a6 Mon Sep 17 00:00:00 2001
From: Subrata Banik <subratabanik@google.com>
Date: Wed, 24 Dec 2025 08:49:36 +0000
Subject: [PATCH 2924/3886] ec/google/chromeec: Add function to read battery
 state of charge

Implement google_chromeec_read_batt_state_of_charge() to retrieve the
current battery percentage from the Embedded Controller.

The function uses the CHARGE_STATE_CMD_GET_STATE host command to fetch
the State of Charge (SoC) as calculated by the EC's fuel gauge logic.
This provides a high-level percentage (0-100) suitable for power
management decisions or UI display.

Change-Id: Iec88476214088476214088476214088476214088
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90614
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
---
 src/ec/google/chromeec/ec.c | 24 ++++++++++++++++++++++++
 src/ec/google/chromeec/ec.h |  8 ++++++++
 2 files changed, 32 insertions(+)

diff --git a/src/ec/google/chromeec/ec.c b/src/ec/google/chromeec/ec.c
index 03ae01c03d..d7e956068c 100644
--- a/src/ec/google/chromeec/ec.c
+++ b/src/ec/google/chromeec/ec.c
@@ -1860,3 +1860,27 @@ void platform_do_early_poweroff(void)
 	google_chromeec_reboot(EC_REBOOT_COLD_AP_OFF, 0);
 	halt();
 }
+
+/*
+ * Reads the current battery charge percentage.
+ *
+ * This function communicates with the Embedded Controller (EC) via a host
+ * command to retrieve the "State of Charge" (SoC) as calculated by the battery fuel gauge.
+ *
+ * Return: 0 on success, -1 on failure (communication error or EC rejection).
+ * Return Value (state): Pointer to a uint32_t where the battery state of charge
+ * (0-100) will be stored.
+ */
+int google_chromeec_read_batt_state_of_charge(uint32_t *state)
+{
+	struct ec_params_charge_state params;
+	struct ec_response_charge_state resp;
+
+	params.cmd = CHARGE_STATE_CMD_GET_STATE;
+
+	if (ec_cmd_charge_state(PLAT_EC, &params, &resp) < 0)
+		return -1;
+
+	*state = resp.get_state.batt_state_of_charge;
+	return 0;
+}
diff --git a/src/ec/google/chromeec/ec.h b/src/ec/google/chromeec/ec.h
index 2f29b9d21c..e4120dabeb 100644
--- a/src/ec/google/chromeec/ec.h
+++ b/src/ec/google/chromeec/ec.h
@@ -538,4 +538,12 @@ bool chipset_emi_write_bytes(u16 port, size_t length, u8 *msg, u8 *csum);
  */
 void chipset_ioport_range(uint16_t *base, size_t *size);
 
+/*
+ * Reads the current battery charge percentage.
+ *
+ * @param state		Pointer to a uint32_t where the battery state of charge (0-100) will be
+ *			stored.
+ */
+int google_chromeec_read_batt_state_of_charge(uint32_t *state);
+
 #endif /* _EC_GOOGLE_CHROMEEC_EC_H */

From 02b3674198cc68745a80fc1f8d2c564103f17ce6 Mon Sep 17 00:00:00 2001
From: Subrata Banik <subratabanik@google.com>
Date: Wed, 24 Dec 2025 08:53:58 +0000
Subject: [PATCH 2925/3886] ec/google/chromeec: Add SoC calculation from
 battery dynamic info

Implement google_chromeec_read_batt_state_of_charge_raw() to
calculate the battery percentage using raw capacity metrics.

Unlike the standard charge state command, this function retrieves data
via EC_CMD_BATTERY_GET_DYNAMIC. It manually calculates the State of
Charge (SoC) by comparing remaining_capacity against full_capacity.

This provides a fallback mechanism for platforms where the high-level
CHARGE_STATE_CMD_GET_STATE command is not implemented or when working
directly with the fuel gauge's dynamic data cache.

Includes:
- Zero-capacity check to prevent division by zero.
- 100% clamping to handle fuel gauge rounding/calibration drift.

Change-Id: I86d6313884762140884762140884762140884762
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90615
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/ec/google/chromeec/ec.c | 34 ++++++++++++++++++++++++++++++++++
 src/ec/google/chromeec/ec.h |  9 +++++++++
 2 files changed, 43 insertions(+)

diff --git a/src/ec/google/chromeec/ec.c b/src/ec/google/chromeec/ec.c
index d7e956068c..70ad5eee7c 100644
--- a/src/ec/google/chromeec/ec.c
+++ b/src/ec/google/chromeec/ec.c
@@ -1884,3 +1884,37 @@ int google_chromeec_read_batt_state_of_charge(uint32_t *state)
 	*state = resp.get_state.batt_state_of_charge;
 	return 0;
 }
+
+/*
+ * Calculates SoC from dynamic battery data.
+ *
+ * This function fetches "dynamic" battery metrics (voltage, current, and capacity)
+ * and manually calculates the percentage. This is often used when the high-level
+ * "Get Charge State" command is unavailable.
+ *
+ * Return: 0 on success, -1 on communication failure or invalid battery data.
+ * Return Value (state): Pointer to store the calculated State of Charge (0-100%).
+ */
+int google_chromeec_read_batt_state_of_charge_raw(uint32_t *state)
+{
+	struct ec_params_battery_dynamic_info params = {
+		.index = 0,
+	};
+	struct ec_response_battery_dynamic_info resp;
+
+	if (ec_cmd_battery_get_dynamic(PLAT_EC, &params, &resp) != 0)
+		return -1;
+
+	if (resp.full_capacity <= 0)
+		return -1;
+
+	uint32_t soc = (uint32_t)resp.remaining_capacity * 100 / (uint32_t)resp.full_capacity;
+
+	/* Clamp the value to 100% (some fuel gauges report slight overflows) */
+	if (soc > 100)
+		soc = 100;
+
+	*state = soc;
+
+	return 0;
+}
diff --git a/src/ec/google/chromeec/ec.h b/src/ec/google/chromeec/ec.h
index e4120dabeb..ffda39b5c1 100644
--- a/src/ec/google/chromeec/ec.h
+++ b/src/ec/google/chromeec/ec.h
@@ -546,4 +546,13 @@ void chipset_ioport_range(uint16_t *base, size_t *size);
  */
 int google_chromeec_read_batt_state_of_charge(uint32_t *state);
 
+/*
+ * Reads the current battery charge percentage from EC dynamic info CMD.
+ * This is often used when the high-level "Get Charge State" command is unavailable".
+ *
+ * @param state		Pointer to a uint32_t where the battery state of charge (0-100) will be
+ *			stored.
+ */
+int google_chromeec_read_batt_state_of_charge_raw(uint32_t *state);
+
 #endif /* _EC_GOOGLE_CHROMEEC_EC_H */

From bab8ca2bd001657b9d4ad5945a88d81e83a50ef7 Mon Sep 17 00:00:00 2001
From: Subrata Banik <subratabanik@google.com>
Date: Wed, 24 Dec 2025 17:39:17 +0000
Subject: [PATCH 2926/3886] ec/google/chromeec: Refactor Battery SoC
 calculation

On certain platforms, such as Qualcomm X1P42100 (Hamoa), the AP cannot
successfully execute the standard CHARGE_STATE_CMD_GET_STATE host
command while in the S0 power state. This is typically due to hardware
arbitration or access restrictions to the battery fuel gauge bus during
active operating states.

This patch introduces a mechanism to fallback to manual State of Charge
(SoC) calculation using dynamic battery metrics:

1. Add EC_GOOGLE_CHROMEEC_BATTERY_SOC_DYNAMIC Kconfig: Allows platforms
   to opt-in to manual SoC calculation.
2. Refactor existing logic: The standard command is moved to an internal
   static helper google_chromeec_read_batt_state_of_charge_cmd().
3. Unified API: google_chromeec_read_batt_state_of_charge() now switches
   between the standard command and the raw/dynamic calculation at
   compile-time based on the Kconfig selection.

By using ec_cmd_battery_get_dynamic(), the AP retrieves cached telemetry
from the EC. This avoids triggering synchronous bus transactions to the
battery, ensuring SoC data is available even when direct fuel gauge
access is restricted.

BUG=none
BRANCH=none
TEST=Build for Hamoa and verify SoC is correctly calculated via the
dynamic info path. Verify standard platforms still use the charge
state command path.

Change-Id: I4928017362140884762140884762140884762140
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90618
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
---
 src/ec/google/chromeec/Kconfig | 16 ++++++++++++++++
 src/ec/google/chromeec/ec.c    | 28 +++++++++++++++++++++++++---
 src/ec/google/chromeec/ec.h    |  9 ---------
 3 files changed, 41 insertions(+), 12 deletions(-)

diff --git a/src/ec/google/chromeec/Kconfig b/src/ec/google/chromeec/Kconfig
index 9213e24302..0239a08904 100644
--- a/src/ec/google/chromeec/Kconfig
+++ b/src/ec/google/chromeec/Kconfig
@@ -234,6 +234,22 @@ config EC_GOOGLE_CHROMEEC_LPC_GENERIC_MEMORY_SIZE
 	hex
 	default 0x10000
 
+config EC_GOOGLE_CHROMEEC_BATTERY_SOC_DYNAMIC
+	bool
+	default n
+	help
+	  Enable this option to calculate the battery State of Charge (SoC)
+	  manually using remaining and full capacity metrics.
+
+	  On certain platforms, such as Qualcomm X1P42100 (Hamoa), the AP
+	  cannot use the standard CHARGE_STATE_CMD_GET_STATE host command
+	  while in the S0 power state due to hardware arbitration or
+	  access restrictions to the battery fuel gauge.
+
+	  Selecting this option forces the use of ec_cmd_battery_get_dynamic(),
+	  which retrieves cached telemetry from the EC rather than triggering
+	  a synchronous bus transaction to the battery.
+
 endif # EC_GOOGLE_CHROMEEC
 
 source "src/ec/google/chromeec/*/Kconfig"
diff --git a/src/ec/google/chromeec/ec.c b/src/ec/google/chromeec/ec.c
index 70ad5eee7c..f4da831006 100644
--- a/src/ec/google/chromeec/ec.c
+++ b/src/ec/google/chromeec/ec.c
@@ -1862,7 +1862,7 @@ void platform_do_early_poweroff(void)
 }
 
 /*
- * Reads the current battery charge percentage.
+ * Reads the current battery charge percentage using CHARGE_STATE_CMD_GET_STATE CMD.
  *
  * This function communicates with the Embedded Controller (EC) via a host
  * command to retrieve the "State of Charge" (SoC) as calculated by the battery fuel gauge.
@@ -1871,7 +1871,7 @@ void platform_do_early_poweroff(void)
  * Return Value (state): Pointer to a uint32_t where the battery state of charge
  * (0-100) will be stored.
  */
-int google_chromeec_read_batt_state_of_charge(uint32_t *state)
+static int google_chromeec_read_batt_state_of_charge_cmd(uint32_t *state)
 {
 	struct ec_params_charge_state params;
 	struct ec_response_charge_state resp;
@@ -1895,7 +1895,7 @@ int google_chromeec_read_batt_state_of_charge(uint32_t *state)
  * Return: 0 on success, -1 on communication failure or invalid battery data.
  * Return Value (state): Pointer to store the calculated State of Charge (0-100%).
  */
-int google_chromeec_read_batt_state_of_charge_raw(uint32_t *state)
+static int google_chromeec_read_batt_state_of_charge_raw(uint32_t *state)
 {
 	struct ec_params_battery_dynamic_info params = {
 		.index = 0,
@@ -1918,3 +1918,25 @@ int google_chromeec_read_batt_state_of_charge_raw(uint32_t *state)
 
 	return 0;
 }
+
+/*
+ * Reads the current battery charge percentage.
+ *
+ * This function communicates with the Embedded Controller (EC) via a host
+ * command to retrieve the "State of Charge" (SoC) as calculated by the battery fuel gauge.
+ *
+ * Return: 0 on success, -1 on failure (communication error or EC rejection).
+ * Return Value (state): Pointer to a uint32_t where the battery state of charge
+ * (0-100) will be stored.
+ */
+int google_chromeec_read_batt_state_of_charge(uint32_t *state)
+{
+	int ret;
+
+	if (CONFIG(EC_GOOGLE_CHROMEEC_BATTERY_SOC_DYNAMIC))
+		ret = google_chromeec_read_batt_state_of_charge_raw(state);
+	else
+		ret = google_chromeec_read_batt_state_of_charge_cmd(state);
+
+	return ret;
+}
diff --git a/src/ec/google/chromeec/ec.h b/src/ec/google/chromeec/ec.h
index ffda39b5c1..e4120dabeb 100644
--- a/src/ec/google/chromeec/ec.h
+++ b/src/ec/google/chromeec/ec.h
@@ -546,13 +546,4 @@ void chipset_ioport_range(uint16_t *base, size_t *size);
  */
 int google_chromeec_read_batt_state_of_charge(uint32_t *state);
 
-/*
- * Reads the current battery charge percentage from EC dynamic info CMD.
- * This is often used when the high-level "Get Charge State" command is unavailable".
- *
- * @param state		Pointer to a uint32_t where the battery state of charge (0-100) will be
- *			stored.
- */
-int google_chromeec_read_batt_state_of_charge_raw(uint32_t *state);
-
 #endif /* _EC_GOOGLE_CHROMEEC_EC_H */

From 3bebadd347e83629aacdcbb4afbee69b2d57e7f7 Mon Sep 17 00:00:00 2001
From: Subrata Banik <subratabanik@google.com>
Date: Wed, 24 Dec 2025 17:54:08 +0000
Subject: [PATCH 2927/3886] mb/google/bluey: Enable dynamic SoC calculation and
 log battery level

Enable EC_GOOGLE_CHROMEEC_BATTERY_SOC_DYNAMIC for the Quenbi and Quartz
models. These Qualcomm-based boards require State of Charge (SoC) to be
calculated from dynamic battery metrics because the standard charge
state command is restricted during certain active power states.

Additionally, add platform_dump_battery_soc_information() to romstage
to log the battery percentage early in the boot process. This helps
with debugging power-related issues during the early boot sequence
when serial console is enabled.

Details:
- Select EC_GOOGLE_CHROMEEC_BATTERY_SOC_DYNAMIC for Quenbi and Quartz.
- Call the SoC dump in platform_romstage_main() if CONSOLE_SERIAL is on.

BUG=none
TEST=Boot Quenbi/Quartz and verify "Battery state-of-charge X" appears
in the romstage serial console logs.

Change-Id: I6184762140884762140884762140884762140884
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90619
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/google/bluey/Kconfig    |  2 ++
 src/mainboard/google/bluey/romstage.c | 12 ++++++++++++
 2 files changed, 14 insertions(+)

diff --git a/src/mainboard/google/bluey/Kconfig b/src/mainboard/google/bluey/Kconfig
index c185938caf..e5665ea752 100644
--- a/src/mainboard/google/bluey/Kconfig
+++ b/src/mainboard/google/bluey/Kconfig
@@ -31,6 +31,7 @@ config BOARD_GOOGLE_MODEL_QUENBI
 	def_bool n
 	select BOARD_GOOGLE_BASEBOARD_BLUEY
 	select BOARD_ROMSIZE_KB_32768
+	select EC_GOOGLE_CHROMEEC_BATTERY_SOC_DYNAMIC
 	select MAINBOARD_HAS_CHROME_EC
 	select MAINBOARD_HAS_FINGERPRINT_VIA_SPI
 	select MAINBOARD_HAS_GOOGLE_TPM
@@ -39,6 +40,7 @@ config BOARD_GOOGLE_MODEL_QUARTZ
 	def_bool n
 	select BOARD_GOOGLE_BASEBOARD_BLUEY
 	select BOARD_ROMSIZE_KB_32768
+	select EC_GOOGLE_CHROMEEC_BATTERY_SOC_DYNAMIC
 	select MAINBOARD_HAS_CHROME_EC
 	select MAINBOARD_HAS_FINGERPRINT_VIA_SPI
 	select MAINBOARD_HAS_GOOGLE_TPM
diff --git a/src/mainboard/google/bluey/romstage.c b/src/mainboard/google/bluey/romstage.c
index dbfda5511e..3ada667376 100644
--- a/src/mainboard/google/bluey/romstage.c
+++ b/src/mainboard/google/bluey/romstage.c
@@ -77,11 +77,23 @@ int qclib_mainboard_override(struct qclib_cb_if_table *table)
 	return 0;
 }
 
+static void platform_dump_battery_soc_information(void)
+{
+	uint32_t batt_pct;
+	if (google_chromeec_read_batt_state_of_charge(&batt_pct))
+		printk(BIOS_WARNING, "Failed to get battery level\n");
+	else
+		printk(BIOS_INFO, "Battery state-of-charge %d\n", batt_pct);
+}
+
 void platform_romstage_main(void)
 {
 	/* Watchdog must be checked first to avoid erasing watchdog info later. */
 	check_wdog();
 
+	if (CONFIG(EC_GOOGLE_CHROMEEC) && CONFIG(CONSOLE_SERIAL))
+		platform_dump_battery_soc_information();
+
 	shrm_fw_load_reset();
 
 	/* QCLib: DDR init & train */

From a27a7f0c111326b78f7a3bfb6828be8a2fe98e6f Mon Sep 17 00:00:00 2001
From: Eren Peng <peng.eren@inventec.corp-partner.google.com>
Date: Tue, 23 Dec 2025 13:59:14 +0800
Subject: [PATCH 2928/3886] mb/google/trulo/var/kaladin: Decrease G2 touch stop
 delay time to 150 ms

We found that our UI resume time will exceed using G2 touch panel. After discussing with vendor they suggested to reduce the stop delay time to 150ms. We can get pass result after this modification. Please see b/468147191 for more details.

BUG=b:468147191
TEST=Pass UI Resume test with G2 touch panel

Change-Id: Iec78e27c4716e3442babad4f377efccb26773183
Signed-off-by: Eren Peng <peng.eren@inventec.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90599
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
---
 src/mainboard/google/brya/variants/kaladin/overridetree.cb | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/mainboard/google/brya/variants/kaladin/overridetree.cb b/src/mainboard/google/brya/variants/kaladin/overridetree.cb
index a31ed720c5..8f7f8e2be5 100644
--- a/src/mainboard/google/brya/variants/kaladin/overridetree.cb
+++ b/src/mainboard/google/brya/variants/kaladin/overridetree.cb
@@ -552,7 +552,7 @@ chip soc/intel/alderlake
 				register "generic.reset_delay_ms" = "70"
 				register "generic.reset_off_delay_ms" = "2"
 				register "generic.stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C4)"
-				register "generic.stop_delay_ms" = "280"
+				register "generic.stop_delay_ms" = "150"
 				register "generic.stop_off_delay_ms" = "2"
 				register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C0)"
 				register "generic.enable_delay_ms" = "1"
@@ -571,7 +571,7 @@ chip soc/intel/alderlake
 				register "generic.reset_delay_ms" = "70"
 				register "generic.reset_off_delay_ms" = "2"
 				register "generic.stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C4)"
-				register "generic.stop_delay_ms" = "280"
+				register "generic.stop_delay_ms" = "150"
 				register "generic.stop_off_delay_ms" = "2"
 				register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C0)"
 				register "generic.enable_delay_ms" = "1"

From d912ae91b0a8174a93d7701ae1c620df6fd45029 Mon Sep 17 00:00:00 2001
From: Kapil Porwal <kapilporwal@google.com>
Date: Wed, 24 Dec 2025 16:40:54 +0530
Subject: [PATCH 2929/3886] mb/google/bluey: Configure GPIOs for USB camera

Configure and enable the GPIOs required for the USB camera. GPIO 10
(RESET_L) and GPIO 206 (ENABLE) are set as outputs and driven high
during mainboard initialization to ensure the camera is powered on
and ready for use by the OS.

Schematics version: 0.2

BUG=b:453773922
TEST=Verify detection of USB camera using `lsusb` in the OS.

Change-Id: I1f7afcf730f37b1a2e36e3230ae9774508465691
Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90616
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
---
 src/mainboard/google/bluey/board.h     | 4 ++++
 src/mainboard/google/bluey/mainboard.c | 7 +++++++
 2 files changed, 11 insertions(+)

diff --git a/src/mainboard/google/bluey/board.h b/src/mainboard/google/bluey/board.h
index 40e63791dc..3260b283c7 100644
--- a/src/mainboard/google/bluey/board.h
+++ b/src/mainboard/google/bluey/board.h
@@ -40,6 +40,10 @@
 #define GPIO_SD_CD_L		GPIO(71)
 #endif
 
+/* USB Camera specific GPIOs */
+#define GPIO_USB_CAM_RESET_L	GPIO(10)
+#define GPIO_USB_CAM_ENABLE	GPIO(206)
+
 void setup_chromeos_gpios(void);
 bool is_off_mode(void);
 void configure_parallel_charging(void);
diff --git a/src/mainboard/google/bluey/mainboard.c b/src/mainboard/google/bluey/mainboard.c
index 7b31a8cba6..d8f4c453a5 100644
--- a/src/mainboard/google/bluey/mainboard.c
+++ b/src/mainboard/google/bluey/mainboard.c
@@ -42,8 +42,15 @@ static bool is_low_power_boot(void)
 	return false;
 }
 
+static void enable_usb_camera(void)
+{
+	gpio_output(GPIO_USB_CAM_RESET_L, 1);
+	gpio_output(GPIO_USB_CAM_ENABLE, 1);
+}
+
 static void setup_usb(void)
 {
+	enable_usb_camera();
 	setup_usb_host0();
 }
 

From 4a07174d0e2d267a48e68ad86660825453d29cee Mon Sep 17 00:00:00 2001
From: Xiang W <wxjstz@126.com>
Date: Mon, 22 Dec 2025 22:35:04 +0800
Subject: [PATCH 2930/3886] util/cbfstool: Fix RISC-V relocations

The RISC-V relocations are not correct. Resolved by referring to
binutils-gdb/blob/master/include/elf/riscv.h

Change-Id: I38306f511c96be75192e222e86526a87714126ea
Signed-off-by: Xiang W <wangxiang@iscas.ac.cn>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90600
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 util/cbfstool/elf.h | 103 ++++++++++++++++++++++++++------------------
 1 file changed, 62 insertions(+), 41 deletions(-)

diff --git a/util/cbfstool/elf.h b/util/cbfstool/elf.h
index e2d0421929..b47e080e67 100644
--- a/util/cbfstool/elf.h
+++ b/util/cbfstool/elf.h
@@ -2714,48 +2714,69 @@ typedef Elf32_Addr Elf32_Conflict;
 #define R_M32R_NUM		256	/* Keep this the last entry. */
 
 
-/* RISC-V relocation types */
+/* RISC-V relocations  */
 #define R_RISCV_NONE		0
-#define R_RISCV_32		2
-#define R_RISCV_REL32		3
-#define R_RISCV_JAL		4
-#define R_RISCV_HI20		5
-#define R_RISCV_LO12_I		6
-#define R_RISCV_LO12_S		7
-#define R_RISCV_PCREL_LO12_I	8
-#define R_RISCV_PCREL_LO12_S	9
-#define R_RISCV_BRANCH		10
-#define R_RISCV_CALL		11
-#define R_RISCV_PCREL_HI20	12
-#define R_RISCV_CALL_PLT	13
-#define R_RISCV_64		18
-#define R_RISCV_GOT_HI20	22
-#define R_RISCV_GOT_LO12	23
-#define R_RISCV_COPY		24
-#define R_RISCV_JUMP_SLOT	25
-/* TLS relocations */
-#define R_RISCV_TPREL_HI20	30
-#define R_RISCV_TPREL_LO12_I	31
-#define R_RISCV_TPREL_LO12_S	32
-#define R_RISCV_TLS_DTPMOD32	38
-#define R_RISCV_TLS_DTPREL32	39
-#define R_RISCV_TLS_DTPMOD64	40
-#define R_RISCV_TLS_DTPREL64	41
-#define R_RISCV_TLS_GD		42
-#define R_RISCV_TLS_DTPREL_HI16	44
-#define R_RISCV_TLS_DTPREL_LO16	45
-#define R_RISCV_TLS_GOTTPREL	46
-#define R_RISCV_TLS_TPREL32	47
-#define R_RISCV_TLS_TPREL64	48
-#define R_RISCV_TLS_GOT_HI20	51
-#define R_RISCV_TLS_GOT_LO12	52
-#define R_RISCV_TLS_GD_HI20	53
-#define R_RISCV_TLS_GD_LO12	54
-#define R_RISCV_GLOB_DAT	57
-#define R_RISCV_ADD32		58
-#define R_RISCV_ADD64		59
-#define R_RISCV_SUB32		60
-#define R_RISCV_SUB64		61
+#define R_RISCV_32		1
+#define R_RISCV_64		2
+#define R_RISCV_RELATIVE	3
+#define R_RISCV_COPY		4
+#define R_RISCV_JUMP_SLOT	5
+#define R_RISCV_TLS_DTPMOD32	6
+#define R_RISCV_TLS_DTPMOD64	7
+#define R_RISCV_TLS_DTPREL32	8
+#define R_RISCV_TLS_DTPREL64	9
+#define R_RISCV_TLS_TPREL32	10
+#define R_RISCV_TLS_TPREL64	11
+#define R_RISCV_TLSDESC		12
+
+#define R_RISCV_BRANCH		16
+#define R_RISCV_JAL		17
+#define R_RISCV_CALL		18
+#define R_RISCV_CALL_PLT	19
+#define R_RISCV_GOT_HI20	20
+#define R_RISCV_TLS_GOT_HI20	21
+#define R_RISCV_TLS_GD_HI20	22
+#define R_RISCV_PCREL_HI20	23
+#define R_RISCV_PCREL_LO12_I	24
+#define R_RISCV_PCREL_LO12_S	25
+#define R_RISCV_HI20		26
+#define R_RISCV_LO12_I		27
+#define R_RISCV_LO12_S		28
+#define R_RISCV_TPREL_HI20	29
+#define R_RISCV_TPREL_LO12_I	30
+#define R_RISCV_TPREL_LO12_S	31
+#define R_RISCV_TPREL_ADD	32
+#define R_RISCV_ADD8		33
+#define R_RISCV_ADD16		34
+#define R_RISCV_ADD32		35
+#define R_RISCV_ADD64		36
+#define R_RISCV_SUB8		37
+#define R_RISCV_SUB16		38
+#define R_RISCV_SUB32		39
+#define R_RISCV_SUB64		40
+#define R_RISCV_ALIGN		43
+#define R_RISCV_RVC_BRANCH	44
+#define R_RISCV_RVC_JUMP	45
+#define R_RISCV_RVC_LUI		46
+#define R_RISCV_GPREL_I		47
+#define R_RISCV_GPREL_S		48
+#define R_RISCV_TPREL_I		49
+#define R_RISCV_TPREL_S		50
+#define R_RISCV_RELAX		51
+#define R_RISCV_SUB6		52
+#define R_RISCV_SET6		53
+#define R_RISCV_SET8		54
+#define R_RISCV_SET16		55
+#define R_RISCV_SET32		56
+#define R_RISCV_32_PCREL	57
+#define R_RISCV_IRELATIVE	58
+
+#define R_RISCV_SET_ULEB128	60
+#define R_RISCV_SUB_ULEB128	61
+#define R_RISCV_TLSDESC_HI20	62
+#define R_RISCV_TLSDESC_LOAD_LO12	63
+#define R_RISCV_TLSDESC_ADD_LO12	64
+#define R_RISCV_TLSDESC_CALL	65
 
 #define EM_RISCV	0xF3
 

From e3fc4a1f693648c928bbcc63841caa8e98e970ed Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Sat, 27 Dec 2025 10:49:11 -0600
Subject: [PATCH 2931/3886] ec/starlabs/merlin: Reorganize Kconfig and guard
 options properly

Reorganize the Kconfig file to improve structure and ensure proper
dependencies, to prevent options from showing in menuconfig. Drop
text string from EC_STARLABS_MERLIN as it should only be selected
at the mainboard level. Ensure all config options are only available
when one of the 3 Starlabs EC types is selected by the mainboard.

TEST=use menuconfig to build for Lenovo T440p, verify Merlin EC option
not shown.

Change-Id: I3f961342de25a22a8ebe1ae03dcf09c6ac2a0fb8
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90627
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nicholas <nic.c3.14@gmail.com>
---
 src/ec/starlabs/merlin/Kconfig | 20 ++++++++++++--------
 1 file changed, 12 insertions(+), 8 deletions(-)

diff --git a/src/ec/starlabs/merlin/Kconfig b/src/ec/starlabs/merlin/Kconfig
index e650c81772..0d2c6378b8 100644
--- a/src/ec/starlabs/merlin/Kconfig
+++ b/src/ec/starlabs/merlin/Kconfig
@@ -1,5 +1,12 @@
 ## SPDX-License-Identifier: GPL-2.0-only
 
+config EC_STARLABS_MERLIN
+	bool
+	default n
+	help
+	  Use open source embedded controller firmware. Both firmwares have the
+	  same features but differ in licensing and compilers.
+
 config EC_STARLABS_NUVOTON
 	bool
 	select EC_ACPI
@@ -18,6 +25,8 @@ config EC_STARLABS_ITE
 	  KBL - 3.12 or later
 	  And open-source Merlin firmware version 1.00 or later
 
+if EC_STARLABS_MERLIN || EC_STARLABS_ITE || EC_STARLABS_NUVOTON
+
 config EC_STARLABS_ADD_ITE_BIN
 	bool "Add Star Labs EC binary file"
 	default n
@@ -63,13 +72,6 @@ config EC_STARLABS_BATTERY_OEM
 	string
 	default "Unknown"
 
-config EC_STARLABS_MERLIN
-	bool "Use open-source Merlin EC Firmware"
-	default n
-	help
-	  Use open source embedded controller firmware. Both firmwares have the
-	  same features but differ in licensing and compilers.
-
 if EC_STARLABS_MERLIN
 
 config EC_STARLABS_MAX_CHARGE
@@ -102,4 +104,6 @@ config EC_STARLABS_CHARGE_LED
 	help
 	  Select if the mainboard supports reducing the charge LED brightness
 
-endif
+endif # EC_STARLABS_MERLIN
+
+endif # EC_STARLABS_MERLIN || EC_STARLABS_ITE || EC_STARLABS_NUVOTON

From a3236ef1109fc11811b525185f5caa074c21a4d8 Mon Sep 17 00:00:00 2001
From: Maximilian Brune <maximilian.brune@9elements.com>
Date: Wed, 27 Aug 2025 20:23:10 +0200
Subject: [PATCH 2932/3886] arch/x86/acpi_bert_storage.c: Fix array size
 calculation

The naming of the parameters was quite confusing which caused them to be
used incorrectly. For example the cper_ia32x64_ctx_sz_bytype function
was given the register size in bytes, but it sill multiplied it by 8,
thinking that it got the number of registers instead.

Fix the parameter names to make it more obvious what is the number of
register array entries and what is the actual size in bytes of the
array.

Change-Id: I17a0fadba57ee8ede996eead4cdfb20f1ab3031e
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90477
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/arch/x86/acpi_bert_storage.c         | 17 ++++++++++-------
 src/arch/x86/include/arch/bert_storage.h |  2 +-
 src/include/cper.h                       |  4 ++--
 3 files changed, 13 insertions(+), 10 deletions(-)

diff --git a/src/arch/x86/acpi_bert_storage.c b/src/arch/x86/acpi_bert_storage.c
index 8b19403a5d..b271cffc66 100644
--- a/src/arch/x86/acpi_bert_storage.c
+++ b/src/arch/x86/acpi_bert_storage.c
@@ -324,14 +324,14 @@ acpi_hest_generic_data_v300_t *bert_append_genproc(
  *   CPER_IA32X64_CTX_32BIT_DBG
  *   CPER_IA32X64_CTX_64BIT_DBG
  *   CPER_IA32X64_CTX_MEMMAPPED
- * num is the number of bytes eventually used to fill the context's register
+ * array_size_bytes is the size (in bytes) eventually used to fill the context's register
  *   array, e.g. 4 MSRs * sizeof(msr_t)
  *
  * status and entry data_length values are updated.
  */
 cper_ia32x64_context_t *new_cper_ia32x64_ctx(
 		acpi_generic_error_status_t *status,
-		cper_ia32x64_proc_error_section_t *x86err, int type, int num)
+		cper_ia32x64_proc_error_section_t *x86err, int type, int array_size_bytes)
 {
 	size_t size;
 	cper_ia32x64_context_t *ctx;
@@ -355,7 +355,7 @@ cper_ia32x64_context_t *new_cper_ia32x64_ctx(
 		return NULL;
 	}
 
-	size = cper_ia32x64_ctx_sz_bytype(type, num);
+	size = cper_ia32x64_ctx_sz_bytype(type, array_size_bytes);
 	ctx = bert_allocate_storage(size);
 	if (!ctx) {
 		printk(BIOS_ERR, "New IA32X64 %s context entry would exceed available region\n",
@@ -366,7 +366,7 @@ cper_ia32x64_context_t *new_cper_ia32x64_ctx(
 	revise_error_sizes(status, size);
 
 	ctx->type = type;
-	ctx->array_size = num;
+	ctx->array_size = array_size_bytes;
 	cper_bump_ia32x64_ctx_count(x86err);
 
 	return ctx;
@@ -553,13 +553,16 @@ cper_ia32x64_context_t *cper_new_ia32x64_context_msr(
 	int i;
 	msr_t *dest;
 
-	ctx = new_cper_ia32x64_ctx(status, x86err, CPER_IA32X64_CTX_MSR, num);
+	ctx = new_cper_ia32x64_ctx(status, x86err, CPER_IA32X64_CTX_MSR, num * sizeof(msr_t));
 	if (!ctx)
 		return NULL;
 
-	/* already filled ctx->type = CPER_IA32X64_CTX_MSR; */
+	/*
+	 * already filled:
+	 *   - ctx->type = CPER_IA32X64_CTX_MSR
+	 *   - ctx->array_size = num * sizeof(msr_t)
+	 */
 	ctx->msr_addr = addr;
-	ctx->array_size = num * sizeof(msr_t);
 
 	dest = (msr_t *)((u8 *)(ctx + 1)); /* point to the Register Array */
 
diff --git a/src/arch/x86/include/arch/bert_storage.h b/src/arch/x86/include/arch/bert_storage.h
index d979d64000..eb5db7f9cb 100644
--- a/src/arch/x86/include/arch/bert_storage.h
+++ b/src/arch/x86/include/arch/bert_storage.h
@@ -91,7 +91,7 @@ static inline acpi_hest_generic_data_v300_t *acpi_hest_generic_data3(
 /* Add a context to an existing IA32/X64-type error entry */
 cper_ia32x64_context_t *new_cper_ia32x64_ctx(
 		acpi_generic_error_status_t *status,
-		cper_ia32x64_proc_error_section_t *x86err, int type, int num);
+		cper_ia32x64_proc_error_section_t *x86err, int type, int array_size);
 
 /* Helper to add an MSR context to an existing IA32/X64-type error entry */
 cper_ia32x64_context_t *cper_new_ia32x64_context_msr(
diff --git a/src/include/cper.h b/src/include/cper.h
index 50e858a219..d0f7b30581 100644
--- a/src/include/cper.h
+++ b/src/include/cper.h
@@ -459,7 +459,7 @@ static inline cper_timestamp_t cper_timestamp(int precise)
  *   CPER_IA32X64_CTX_MEMMAPPED
  * num is the number of items in the context's register array
  */
-static inline size_t cper_ia32x64_ctx_sz_bytype(int type, int arr_num)
+static inline size_t cper_ia32x64_ctx_sz_bytype(int type, int array_size)
 {
 	size_t sz = sizeof(cper_ia32x64_context_t);
 
@@ -476,7 +476,7 @@ static inline size_t cper_ia32x64_ctx_sz_bytype(int type, int arr_num)
 	case CPER_IA32X64_CTX_MEMMAPPED:
 	default:
 		/* Table N.13: "size ... is determined by (Array Size / 8)" */
-		return ALIGN_UP(sz + arr_num * 8, 16);
+		return ALIGN_UP(sz + array_size, 16);
 	}
 }
 

From 2b9653cf34070d85a46ed6a9a03e3a6da1ba49e2 Mon Sep 17 00:00:00 2001
From: Maximilian Brune <maximilian.brune@9elements.com>
Date: Wed, 27 Aug 2025 20:32:19 +0200
Subject: [PATCH 2933/3886] arch/x86/acpi_bert_storage.c: rename check ->
 proc_err_info

The name check is a bit confusing, since it is not a check structure.
The check structure is below it.

Change-Id: I000e9e5f2ce8210fce76ef81b4242150d02fceed
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90478
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
---
 src/arch/x86/acpi_bert_storage.c | 12 ++++++------
 1 file changed, 6 insertions(+), 6 deletions(-)

diff --git a/src/arch/x86/acpi_bert_storage.c b/src/arch/x86/acpi_bert_storage.c
index b271cffc66..e9b9fc563a 100644
--- a/src/arch/x86/acpi_bert_storage.c
+++ b/src/arch/x86/acpi_bert_storage.c
@@ -386,7 +386,7 @@ cper_ia32x64_proc_error_info_t *new_cper_ia32x64_check(
 		cper_ia32x64_proc_error_section_t *x86err,
 		enum cper_x86_check_type type)
 {
-	cper_ia32x64_proc_error_info_t *check;
+	cper_ia32x64_proc_error_info_t *proc_err_info;
 	static const char * const check_names[] = {
 			"cache",
 			"TLB",
@@ -409,19 +409,19 @@ cper_ia32x64_proc_error_info_t *new_cper_ia32x64_check(
 		return NULL;
 	}
 
-	check = bert_allocate_storage(sizeof(*check));
-	if (!check) {
+	proc_err_info = bert_allocate_storage(sizeof(*proc_err_info));
+	if (!proc_err_info) {
 		printk(BIOS_ERR, "New IA32X64 %s check entry would exceed available region\n",
 				check_names[type]);
 		return NULL;
 	}
 
-	revise_error_sizes(status, sizeof(*check));
+	revise_error_sizes(status, sizeof(*proc_err_info));
 
-	guidcpy(&check->type, &check_guids[type]);
+	guidcpy(&proc_err_info->type, &check_guids[type]);
 	cper_bump_ia32x64_chk_count(x86err);
 
-	return check;
+	return proc_err_info;
 }
 
 /* Helper to append an ACPI Generic Error Data Entry plus a CPER IA32/X64

From a1e9cd3669373725e70cf31630e7581578b53aa4 Mon Sep 17 00:00:00 2001
From: Venkateshwar S <vens@qualcomm.corp-partner.google.com>
Date: Mon, 29 Dec 2025 21:57:20 -0800
Subject: [PATCH 2934/3886] mb/google/bluey: Configure QUPV3_2_SE4 for ADSP I2C
 access

Load I2C firmware to QUPV3_2_SE4 Serial Engine and configure it in
GSI mode to enable ADSP-controlled access to charger and fuel
gauge.

Test=Create an image.serial.bin and ensure it boots on X1P42100.

Change-Id: I58bfe5c65f3dbd2790512c5e013fa7b91cae2933
Signed-off-by: Venkateshwar S <vens@qualcomm.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90647
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
---
 src/mainboard/google/bluey/mainboard.c | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/src/mainboard/google/bluey/mainboard.c b/src/mainboard/google/bluey/mainboard.c
index d8f4c453a5..e18f492764 100644
--- a/src/mainboard/google/bluey/mainboard.c
+++ b/src/mainboard/google/bluey/mainboard.c
@@ -112,6 +112,10 @@ static void mainboard_init(struct device *dev)
 	qupv3_se_fw_load_and_init(QUPV3_1_SE0, SE_PROTOCOL_I2C, MIXED); /* Touch I2C */
 	qupv3_se_fw_load_and_init(QUPV3_1_SE6, SE_PROTOCOL_UART, FIFO); /* BT UART */
 	qupv3_se_fw_load_and_init(QUPV3_0_SE0, SE_PROTOCOL_I2C, MIXED); /* Trackpad I2C */
+
+	/* ADSP I2C (Charger/Fuel gauge) */
+	qupv3_se_fw_load_and_init(QUPV3_2_SE4, SE_PROTOCOL_I2C, GSI);
+
 	if (!CONFIG(MAINBOARD_NO_USB_A_PORT))
 		qupv3_se_fw_load_and_init(QUPV3_0_SE1, SE_PROTOCOL_I2C, MIXED); /* USB-A retimer */
 	qupv3_se_fw_load_and_init(QUPV3_0_SE5, SE_PROTOCOL_I2C, MIXED); /* eUSB repeater */

From 4063a4c3f1090f3b3dc05ebf25e2b77be78d0c7a Mon Sep 17 00:00:00 2001
From: mikelee <mike.lee@lcfc.corp-partner.google.com>
Date: Wed, 31 Dec 2025 15:31:36 +0800
Subject: [PATCH 2935/3886] mb/google/skywalker: Create variant Mace

Create the variant Mace.

BUG=None
TEST=emerge-skywalker coreboot
BRANCH=None

Change-Id: If016e1812d4005a5fd49fac635dc4d93fae3be5d
Signed-off-by: mikelee <mike.lee@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90660
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/google/skywalker/Kconfig      | 2 ++
 src/mainboard/google/skywalker/Kconfig.name | 3 +++
 2 files changed, 5 insertions(+)

diff --git a/src/mainboard/google/skywalker/Kconfig b/src/mainboard/google/skywalker/Kconfig
index 6556acae99..19cfab5d9a 100644
--- a/src/mainboard/google/skywalker/Kconfig
+++ b/src/mainboard/google/skywalker/Kconfig
@@ -6,6 +6,7 @@ config BOARD_GOOGLE_SKYWALKER_COMMON
 		 BOARD_GOOGLE_BAZE || \
 		 BOARD_GOOGLE_DOOKU || \
 		 BOARD_GOOGLE_GROGU || \
+		 BOARD_GOOGLE_MACE || \
 		 BOARD_GOOGLE_OBIWAN || \
 		 BOARD_GOOGLE_PADME || \
 		 BOARD_GOOGLE_SKYWALKER || \
@@ -56,6 +57,7 @@ config MAINBOARD_PART_NUMBER
 	default "Baze" if BOARD_GOOGLE_BAZE
 	default "Dooku" if BOARD_GOOGLE_DOOKU
 	default "Grogu" if BOARD_GOOGLE_GROGU
+	default "Mace" if BOARD_GOOGLE_MACE
 	default "Obiwan" if BOARD_GOOGLE_OBIWAN
 	default "Padme" if BOARD_GOOGLE_PADME
 	default "Skywalker" if BOARD_GOOGLE_SKYWALKER
diff --git a/src/mainboard/google/skywalker/Kconfig.name b/src/mainboard/google/skywalker/Kconfig.name
index 6f787c72b9..aa5b6550bf 100644
--- a/src/mainboard/google/skywalker/Kconfig.name
+++ b/src/mainboard/google/skywalker/Kconfig.name
@@ -14,6 +14,9 @@ config BOARD_GOOGLE_DOOKU
 config BOARD_GOOGLE_GROGU
 	bool "->  Grogu"
 
+config BOARD_GOOGLE_MACE
+	bool "->  Mace"
+
 config BOARD_GOOGLE_OBIWAN
 	bool "->  Obiwan"
 

From 25d159a7ecaef0c4966c5b64c86ae2157648a917 Mon Sep 17 00:00:00 2001
From: Vince Liu <vince-wl.liu@mediatek.corp-partner.google.com>
Date: Tue, 30 Dec 2025 17:24:57 +0800
Subject: [PATCH 2936/3886] mb/google/skywalker: Use FW_CONFIG for storage and
 dual init support

Replace AUXADC with FW_CONFIG for storage type detection, and allow
unprovisioned CBI to initialize both eMMC and UFS, providing greater
flexibility for ODMs.

BUG=b:469517374
TEST=boot successfully with both UFS and eMMC SKUs
BRANCH=skywalker

Signed-off-by: Vince Liu <vince-wl.liu@mediatek.corp-partner.google.com>
Change-Id: I400d0a452a5c25b5f429b99bf0b62591ac6cbe1f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90649
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
---
 src/mainboard/google/skywalker/mainboard.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/src/mainboard/google/skywalker/mainboard.c b/src/mainboard/google/skywalker/mainboard.c
index e219861b63..a0a89fc215 100644
--- a/src/mainboard/google/skywalker/mainboard.c
+++ b/src/mainboard/google/skywalker/mainboard.c
@@ -124,7 +124,9 @@ static void mainboard_init(struct device *dev)
 {
 	mt6359p_init_pmif_arb();
 
-	if (mainboard_get_storage_type() == STORAGE_EMMC) {
+	if (!fw_config_is_provisioned()) {
+		mtk_msdc_configure_emmc(true);
+	} else if (fw_config_probe(FW_CONFIG(STORAGE, STORAGE_EMMC))) {
 		mtk_msdc_configure_emmc(true);
 		mtcmos_ufs_power_off();
 	}

From b354b49d58f87da1bcbc6de073c254bba3708af8 Mon Sep 17 00:00:00 2001
From: Yang Wu <wuyang5@huaqin.corp-partner.google.com>
Date: Tue, 30 Dec 2025 21:29:05 +0800
Subject: [PATCH 2937/3886] libpayload: Increase SYSINFO_MAX_GPIOS to 10

Some boards require exposing more GPIOs to the payload via sysinfo.
Increase the maximum number of supported GPIO entries accordingly.
For example Padme will pass 9 GPIOs to payload.

BUG=b:461907110
TEST=Boot firmware and check GPIO counts in sysinfo.
BRANCH=None

Change-Id: Idb90896b82b56f65c3d46e53b36238717de0a6d1
Signed-off-by: Yang Wu <wuyang5@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90654
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
---
 payloads/libpayload/include/sysinfo.h | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/payloads/libpayload/include/sysinfo.h b/payloads/libpayload/include/sysinfo.h
index f18ad62308..23e2d55409 100644
--- a/payloads/libpayload/include/sysinfo.h
+++ b/payloads/libpayload/include/sysinfo.h
@@ -34,8 +34,8 @@
 
 /* Maximum number of memory range definitions. */
 #define SYSINFO_MAX_MEM_RANGES 32
-/* Allow a maximum of 8 GPIOs */
-#define SYSINFO_MAX_GPIOS 8
+/* Allow a maximum of 10 GPIOs */
+#define SYSINFO_MAX_GPIOS 10
 
 /* Up to 10 MAC addresses */
 #define SYSINFO_MAX_MACS 10

From 49d34a6f6cc5ff6e912146d30f4ab254748ea606 Mon Sep 17 00:00:00 2001
From: Yang Wu <wuyang5@huaqin.corp-partner.google.com>
Date: Tue, 30 Dec 2025 10:08:42 +0800
Subject: [PATCH 2938/3886] mb/google/skywalker: Add MIPI panel GPIOs via
 lb_gpio

Add MIPI panel related GPIOs to lb_gpio so Depthcharge can manage panel
reset and power signals when needed.

The following GPIOs are added:
- panel_resx (GPIO_EN_PP3300_EDP_X)
- mipi_iovcc_en (GPIO_EN_PP6000_MIPI_DISP)
- mipi_tp_rstn (GPIO_TCHSCR_RST_1V8_L)

This allows Depthcharge to release reset and disable IOVCC in the
required order to meet the panel power-off timing specification.

[1] Preliminary+specification+TL121BVMS07+-00+V01+20250721.pdf

BUG=b:461907110
TEST=Boot Padme and check cbmem log is correct.
BRANCH=skywalker

Change-Id: I7f73e41bc4814e8a5ca3579d235001cfafb77bf9
Signed-off-by: Yang Wu <wuyang5@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90646
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/google/skywalker/chromeos.c | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/src/mainboard/google/skywalker/chromeos.c b/src/mainboard/google/skywalker/chromeos.c
index eace485648..bbb8fadcb5 100644
--- a/src/mainboard/google/skywalker/chromeos.c
+++ b/src/mainboard/google/skywalker/chromeos.c
@@ -97,6 +97,16 @@ void fill_lb_gpios(struct lb_gpios *gpios)
 		{GPIO_EDP_BL_EN_1V8.id, ACTIVE_HIGH, -1, "backlight enable"},
 	};
 	lb_add_gpios(gpios, edp_pwm_backlight_gpios, ARRAY_SIZE(edp_pwm_backlight_gpios));
+
+	if (CONFIG(BOARD_GOOGLE_PADME)) {
+		/* Panel power control GPIOs for Depthcharge power-off sequence */
+		struct lb_gpio mipi_panel_gpios[] = {
+			{GPIO_EN_PP3300_EDP_X.id, ACTIVE_LOW, -1, "panel_resx"},
+			{GPIO_EN_PP6000_MIPI_DISP.id, ACTIVE_HIGH, -1, "mipi_iovcc_en"},
+			{GPIO_TCHSCR_RST_1V8_L.id, ACTIVE_LOW, -1, "mipi_tp_rstn"},
+		};
+		lb_add_gpios(gpios, mipi_panel_gpios, ARRAY_SIZE(mipi_panel_gpios));
+	}
 }
 
 int cr50_plat_irq_status(void)

From 40eca2934fb458cdd3d0102097ad80e20620107e Mon Sep 17 00:00:00 2001
From: Yidi Lin <yidilin@google.com>
Date: Wed, 31 Dec 2025 16:23:16 +0800
Subject: [PATCH 2939/3886] soc/mediatek/common: Track firmware splash screen
 rendering completion

Add timestamp, TS_FIRMWARE_SPLASH_RENDERED, to precisely mark the moment
the firmware splash screen has finished displaying.

TEST=check cbmem log

Change-Id: I5c5c61e03486a5939fdb2753c35326d53277c2b2
Signed-off-by: Yidi Lin <yidilin@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90661
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Chen-Tsung Hsieh <chentsung@google.com>
---
 src/soc/mediatek/common/display.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/src/soc/mediatek/common/display.c b/src/soc/mediatek/common/display.c
index 52d6d808f7..08139dfc3d 100644
--- a/src/soc/mediatek/common/display.c
+++ b/src/soc/mediatek/common/display.c
@@ -14,6 +14,7 @@
 #include <soc/mtcmos.h>
 #include <stdio.h>
 #include <symbols.h>
+#include <timestamp.h>
 
 static struct panel_serializable_data *get_mipi_cmd_from_cbfs(struct panel_description *desc)
 {
@@ -94,6 +95,8 @@ static void display_logo(struct panel_description *panel,
 	mtk_ddp_ovlsys_start(fb_addr, edid, path);
 
 	panel_configure_backlight(panel, true);
+
+	timestamp_add_now(TS_FIRMWARE_SPLASH_RENDERED);
 }
 
 int mtk_display_init(void)

From 7273a5b9326397d6962cab998b1baacd84efb1a8 Mon Sep 17 00:00:00 2001
From: Keith Hui <buurin@gmail.com>
Date: Fri, 24 Oct 2025 15:50:16 -0400
Subject: [PATCH 2940/3886] mb/asus/p8x7x-series: Move CONFIG_SUPERIO_PNP_BASE
 to sio/nuvoton

sio/nuvoton will soon make use of this for common code. Move the
definition there; mainboard will only set it.

To mitigate possible conflicts in case of multiple SIO chips on
the same mainboard, rename Kconfig to add _NUVOTON_.
Change all existing references to match.

Change-Id: I8e0516411c74b162c31142b02bf5c45e4ca30a1d
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89741
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/asus/p8x7x-series/Kconfig                     | 3 +--
 .../asus/p8x7x-series/variants/p8c_ws/early_init.c          | 6 +++---
 .../asus/p8x7x-series/variants/p8h77-v/early_init.c         | 6 +++---
 .../asus/p8x7x-series/variants/p8z77-m/early_init.c         | 6 +++---
 .../asus/p8x7x-series/variants/p8z77-m_pro/early_init.c     | 2 +-
 .../asus/p8x7x-series/variants/p8z77-v/early_init.c         | 6 +++---
 .../asus/p8x7x-series/variants/p8z77-v_lx2/early_init.c     | 6 +++---
 src/superio/nuvoton/common/Kconfig                          | 6 ++++++
 8 files changed, 23 insertions(+), 18 deletions(-)

diff --git a/src/mainboard/asus/p8x7x-series/Kconfig b/src/mainboard/asus/p8x7x-series/Kconfig
index cfff67a0dc..ee4ee3eeb2 100644
--- a/src/mainboard/asus/p8x7x-series/Kconfig
+++ b/src/mainboard/asus/p8x7x-series/Kconfig
@@ -106,8 +106,7 @@ config CMOS_DEFAULT_FILE
 config CMOS_LAYOUT_FILE
 	default "src/mainboard/\$(MAINBOARDDIR)/variants/\$(CONFIG_VARIANT_DIR)/cmos.layout"
 
-config SUPERIO_PNP_BASE
-	hex
+config SUPERIO_NUVOTON_PNP_BASE
 	default 0x2e
 
 endif
diff --git a/src/mainboard/asus/p8x7x-series/variants/p8c_ws/early_init.c b/src/mainboard/asus/p8x7x-series/variants/p8c_ws/early_init.c
index f192e22f3c..ae3a3633f6 100644
--- a/src/mainboard/asus/p8x7x-series/variants/p8c_ws/early_init.c
+++ b/src/mainboard/asus/p8x7x-series/variants/p8c_ws/early_init.c
@@ -5,9 +5,9 @@
 #include <superio/nuvoton/common/nuvoton.h>
 #include <superio/nuvoton/nct6776/nct6776.h>
 
-#define GLOBAL_DEV PNP_DEV(CONFIG_SUPERIO_PNP_BASE, 0)
-#define SERIAL_DEV PNP_DEV(CONFIG_SUPERIO_PNP_BASE, NCT6776_SP1)
-#define ACPI_DEV   PNP_DEV(CONFIG_SUPERIO_PNP_BASE, NCT6776_ACPI)
+#define GLOBAL_DEV PNP_DEV(CONFIG_SUPERIO_NUVOTON_PNP_BASE, 0)
+#define SERIAL_DEV PNP_DEV(CONFIG_SUPERIO_NUVOTON_PNP_BASE, NCT6776_SP1)
+#define ACPI_DEV   PNP_DEV(CONFIG_SUPERIO_NUVOTON_PNP_BASE, NCT6776_ACPI)
 
 void bootblock_mainboard_early_init(void)
 {
diff --git a/src/mainboard/asus/p8x7x-series/variants/p8h77-v/early_init.c b/src/mainboard/asus/p8x7x-series/variants/p8h77-v/early_init.c
index a7f7e9f077..69a2f4544c 100644
--- a/src/mainboard/asus/p8x7x-series/variants/p8h77-v/early_init.c
+++ b/src/mainboard/asus/p8x7x-series/variants/p8h77-v/early_init.c
@@ -5,9 +5,9 @@
 #include <superio/nuvoton/common/nuvoton.h>
 #include <superio/nuvoton/nct6779d/nct6779d.h>
 
-#define GLOBAL_DEV PNP_DEV(CONFIG_SUPERIO_PNP_BASE, 0)
-#define SERIAL_DEV PNP_DEV(CONFIG_SUPERIO_PNP_BASE, NCT6779D_SP1)
-#define ACPI_DEV   PNP_DEV(CONFIG_SUPERIO_PNP_BASE, NCT6779D_ACPI)
+#define GLOBAL_DEV PNP_DEV(CONFIG_SUPERIO_NUVOTON_PNP_BASE, 0)
+#define SERIAL_DEV PNP_DEV(CONFIG_SUPERIO_NUVOTON_PNP_BASE, NCT6779D_SP1)
+#define ACPI_DEV   PNP_DEV(CONFIG_SUPERIO_NUVOTON_PNP_BASE, NCT6779D_ACPI)
 
 void bootblock_mainboard_early_init(void)
 {
diff --git a/src/mainboard/asus/p8x7x-series/variants/p8z77-m/early_init.c b/src/mainboard/asus/p8x7x-series/variants/p8z77-m/early_init.c
index 7e4647c6e2..3c6853eef4 100644
--- a/src/mainboard/asus/p8x7x-series/variants/p8z77-m/early_init.c
+++ b/src/mainboard/asus/p8x7x-series/variants/p8z77-m/early_init.c
@@ -10,9 +10,9 @@
 
 #include <option.h>
 
-#define SERIAL_DEV PNP_DEV(CONFIG_SUPERIO_PNP_BASE, NCT6779D_SP1)
-#define GPIO0_DEV  PNP_DEV(CONFIG_SUPERIO_PNP_BASE, NCT6779D_WDT1_GPIO01_V)
-#define ACPI_DEV   PNP_DEV(CONFIG_SUPERIO_PNP_BASE, NCT6779D_ACPI)
+#define SERIAL_DEV PNP_DEV(CONFIG_SUPERIO_NUVOTON_PNP_BASE, NCT6779D_SP1)
+#define GPIO0_DEV  PNP_DEV(CONFIG_SUPERIO_NUVOTON_PNP_BASE, NCT6779D_WDT1_GPIO01_V)
+#define ACPI_DEV   PNP_DEV(CONFIG_SUPERIO_NUVOTON_PNP_BASE, NCT6779D_ACPI)
 
 void bootblock_mainboard_early_init(void)
 {
diff --git a/src/mainboard/asus/p8x7x-series/variants/p8z77-m_pro/early_init.c b/src/mainboard/asus/p8x7x-series/variants/p8z77-m_pro/early_init.c
index 81d9a3a9c8..c3ccf1bbde 100644
--- a/src/mainboard/asus/p8x7x-series/variants/p8z77-m_pro/early_init.c
+++ b/src/mainboard/asus/p8x7x-series/variants/p8z77-m_pro/early_init.c
@@ -11,7 +11,7 @@
 #include <northbridge/intel/sandybridge/raminit.h>
 #include <northbridge/intel/sandybridge/pei_data.h>
 
-#define SERIAL_DEV PNP_DEV(CONFIG_SUPERIO_PNP_BASE, NCT6779D_SP1)
+#define SERIAL_DEV PNP_DEV(CONFIG_SUPERIO_NUVOTON_PNP_BASE, NCT6779D_SP1)
 
 void bootblock_mainboard_early_init(void)
 {
diff --git a/src/mainboard/asus/p8x7x-series/variants/p8z77-v/early_init.c b/src/mainboard/asus/p8x7x-series/variants/p8z77-v/early_init.c
index f693fbcb18..c2285a7254 100644
--- a/src/mainboard/asus/p8x7x-series/variants/p8z77-v/early_init.c
+++ b/src/mainboard/asus/p8x7x-series/variants/p8z77-v/early_init.c
@@ -5,9 +5,9 @@
 #include <superio/nuvoton/common/nuvoton.h>
 #include <superio/nuvoton/nct6779d/nct6779d.h>
 
-#define GLOBAL_DEV PNP_DEV(CONFIG_SUPERIO_PNP_BASE, 0)
-#define SERIAL_DEV PNP_DEV(CONFIG_SUPERIO_PNP_BASE, NCT6779D_SP1)
-#define ACPI_DEV   PNP_DEV(CONFIG_SUPERIO_PNP_BASE, NCT6779D_ACPI)
+#define GLOBAL_DEV PNP_DEV(CONFIG_SUPERIO_NUVOTON_PNP_BASE, 0)
+#define SERIAL_DEV PNP_DEV(CONFIG_SUPERIO_NUVOTON_PNP_BASE, NCT6779D_SP1)
+#define ACPI_DEV   PNP_DEV(CONFIG_SUPERIO_NUVOTON_PNP_BASE, NCT6779D_ACPI)
 
 void bootblock_mainboard_early_init(void)
 {
diff --git a/src/mainboard/asus/p8x7x-series/variants/p8z77-v_lx2/early_init.c b/src/mainboard/asus/p8x7x-series/variants/p8z77-v_lx2/early_init.c
index a7f7e9f077..69a2f4544c 100644
--- a/src/mainboard/asus/p8x7x-series/variants/p8z77-v_lx2/early_init.c
+++ b/src/mainboard/asus/p8x7x-series/variants/p8z77-v_lx2/early_init.c
@@ -5,9 +5,9 @@
 #include <superio/nuvoton/common/nuvoton.h>
 #include <superio/nuvoton/nct6779d/nct6779d.h>
 
-#define GLOBAL_DEV PNP_DEV(CONFIG_SUPERIO_PNP_BASE, 0)
-#define SERIAL_DEV PNP_DEV(CONFIG_SUPERIO_PNP_BASE, NCT6779D_SP1)
-#define ACPI_DEV   PNP_DEV(CONFIG_SUPERIO_PNP_BASE, NCT6779D_ACPI)
+#define GLOBAL_DEV PNP_DEV(CONFIG_SUPERIO_NUVOTON_PNP_BASE, 0)
+#define SERIAL_DEV PNP_DEV(CONFIG_SUPERIO_NUVOTON_PNP_BASE, NCT6779D_SP1)
+#define ACPI_DEV   PNP_DEV(CONFIG_SUPERIO_NUVOTON_PNP_BASE, NCT6779D_ACPI)
 
 void bootblock_mainboard_early_init(void)
 {
diff --git a/src/superio/nuvoton/common/Kconfig b/src/superio/nuvoton/common/Kconfig
index 376ae16422..2525c5d445 100644
--- a/src/superio/nuvoton/common/Kconfig
+++ b/src/superio/nuvoton/common/Kconfig
@@ -21,3 +21,9 @@ config HAVE_SHARED_PS2_PORT
 	  port. This one port usually works for keyboards only. Add the nvram option
 	  "swap_keyboard_and_mouse" to cmos.layout to allow changing this port into a
 	  mouse port.
+
+config SUPERIO_NUVOTON_PNP_BASE
+	hex
+	depends on SUPERIO_NUVOTON_COMMON_PRE_RAM
+	help
+	  Set the base port of the super I/O chip.

From 02c57577f3ed6be160ea7afe1f139d06994a852f Mon Sep 17 00:00:00 2001
From: Keith Hui <buurin@gmail.com>
Date: Thu, 23 Oct 2025 16:48:13 -0400
Subject: [PATCH 2941/3886] superio/nuvoton: Add common ACPI ASL code

This commit gives the Nuvoton super I/O chip family a common ACPI
ASL code, based on nct6776 with the addition of a suspend (_PTS)
hook that disables keyboard wakeup when shutting down and records
the power state for an alternate power loss resume logic, both to
be completed by subsequent patches. This code is not active until
included by a mainboard's ASL code, and the suspend hook needs to
be invoked from there as well.

This common code supports pretty much all the nct???? super I/O chips
in tree except nct5104d, nct6687d, npcd378, wpcm450.

Change-Id: I7d8cf66e69688d1c53e4c313358174883710b374
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89740
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
---
 src/superio/nuvoton/common/acpi/superio.asl | 214 ++++++++++++++++++++
 1 file changed, 214 insertions(+)
 create mode 100644 src/superio/nuvoton/common/acpi/superio.asl

diff --git a/src/superio/nuvoton/common/acpi/superio.asl b/src/superio/nuvoton/common/acpi/superio.asl
new file mode 100644
index 0000000000..9e49cf5b9e
--- /dev/null
+++ b/src/superio/nuvoton/common/acpi/superio.asl
@@ -0,0 +1,214 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+/*
+ * Include this file into a mainboard's DSDT _SB device tree and it will
+ * expose the NCT677x SuperIO and some of its functionality.
+ *
+ * It allows the change of IO ports, IRQs and DMA settings on logical
+ * devices, disabling and reenabling logical devices.
+ *
+ *   LDN		State
+ * NCT677X_PP		Implemented, untested
+ * NCT677x_SP1		Implemented, untested
+ * NCT677x_SP2		Implemented, untested
+ * NCT677x_KBC		Implemented, untested
+ * 0x308 GPIO		Implemented, untested
+ * 0xb HWM		Implemented, untested
+ *
+ * Controllable through preprocessor defines:
+ *
+ * SIO identities
+ * SUPERIO_DEV		Device identifier for this SIO (e.g. SIO0; required)
+ * SUPERIO_CHIP_NAME	Chip name (@)
+ * SUPERIO_FULL_CHIP_NAME	Unicode device name (@)
+ * SUPERIO_PNP_BASE	I/O address of the first PnP configuration register (@)
+ * Items with @ are required if multiple SIO chips are being used.
+ *
+ * Functionality exposed if defined:
+ * NCT677X_SHOW_PP	Parallel port
+ * NCT677X_SHOW_SP1	Serial port 1
+ * NCT677X_SHOW_SP2	Serial port 2
+ * NCT677X_SHOW_KBC	Keyboard controller
+ * NCT677X_SHOW_GPIO	GPIO by I/O support
+ * NCT677X_SHOW_HWM	Hardware monitor
+ */
+#include <superio/nuvoton/common/nuvoton.h>
+
+/* Get SUPERIO_PNP_BASE from Kconfig if not redefined */
+#ifndef SUPERIO_PNP_BASE
+#define SUPERIO_PNP_BASE CONFIG_SUPERIO_NUVOTON_PNP_BASE
+#endif
+
+#include <superio/acpi/pnp.asl>
+
+#undef PNP_DEFAULT_PSC
+#define PNP_DEFAULT_PSC Return (0) /* no power management */
+
+#define ENABLE_KEYBOARD_WAKEUP SKWK
+#define POWER_LOSS_LAST_STATE  PLSF
+
+Device(SUPERIO_DEV) {
+	Name (_HID, EisaId("PNP0A05"))
+	Name (_STR, Unicode(SUPERIO_FULL_CHIP_NAME))
+	Name (_UID, SUPERIO_UID(SUPERIO_DEV,))
+
+	/* SuperIO configuration ports */
+	OperationRegion (CREG, SystemIO, SUPERIO_PNP_BASE, 2)
+	Field (CREG, ByteAcc, NoLock, Preserve)
+	{
+		PNP_ADDR_REG,	8,
+		PNP_DATA_REG,	8,
+	}
+	IndexField (PNP_ADDR_REG, PNP_DATA_REG, ByteAcc, NoLock, Preserve)
+	{
+		Offset (0x07),
+		PNP_LOGICAL_DEVICE,	8, /* Logical device selector */
+
+		Offset (0x30),
+		PNP_DEVICE_ACTIVE,	1, /* Logical device activation */
+		ACT1,			1, /* Logical device activation */
+		ACT2,			1, /* Logical device activation */
+		ACT3,			1, /* Logical device activation */
+		ACT4,			1, /* Logical device activation */
+		ACT5,			1, /* Logical device activation */
+		ACT6,			1, /* Logical device activation */
+		ACT7,			1, /* Logical device activation */
+
+		Offset (0x60),
+		PNP_IO0_HIGH_BYTE,	8, /* First I/O port base - high byte */
+		PNP_IO0_LOW_BYTE,	8, /* First I/O port base - low byte */
+		Offset (0x62),
+		PNP_IO1_HIGH_BYTE,	8, /* Second I/O port base - high byte */
+		PNP_IO1_LOW_BYTE,	8, /* Second I/O port base - low byte */
+		Offset (0x64),
+		PNP_IO2_HIGH_BYTE,	8, /* Third I/O port base - high byte */
+		PNP_IO2_LOW_BYTE,	8, /* Third I/O port base - low byte */
+		Offset (0x70),
+		PNP_IRQ0,		8, /* First IRQ */
+		Offset (0x72),
+		PNP_IRQ1,		8, /* Second IRQ */
+		Offset (0x74),
+		PNP_DMA0,		8, /* DRQ */
+
+		Offset (0xe0),		   /* Config register 0xe0 etc. */
+		,6,
+		ENABLE_KEYBOARD_WAKEUP,	1,
+		Offset (0xe6),
+		,4,
+		POWER_LOSS_LAST_STATE,	1,
+		Offset (0xf2),
+		SPME,			1, /* Enable PME */
+		,7,
+		OPT3,			8,
+		OPT4,			8,
+		,8,
+		OPT6,			8,
+		OPT7,			8
+	}
+
+	Method (_CRS)
+	{
+		/* Announce the used I/O ports to the OS */
+		Return (ResourceTemplate () {
+			IO (Decode16, SUPERIO_PNP_BASE, SUPERIO_PNP_BASE, 1, 2)
+		})
+	}
+
+	Method (SIOS, 1, NotSerialized)
+	{
+		ENTER_CONFIG_MODE(NCT677X_ACPI)
+		if (Arg0 == 5)
+		{
+			ENABLE_KEYBOARD_WAKEUP = 0
+			/* Log "power off" state */
+			POWER_LOSS_LAST_STATE = 1
+		}
+		EXIT_CONFIG_MODE()
+	}
+
+	Method (SIOW, 1, NotSerialized)
+	{
+	}
+
+	#undef PNP_ENTER_MAGIC_1ST
+	#undef PNP_ENTER_MAGIC_2ND
+	#undef PNP_ENTER_MAGIC_3RD
+	#undef PNP_ENTER_MAGIC_4TH
+	#undef PNP_EXIT_MAGIC_1ST
+	#undef PNP_EXIT_SPECIAL_REG
+	#undef PNP_EXIT_SPECIAL_VAL
+	#define PNP_ENTER_MAGIC_1ST	0x87
+	#define PNP_ENTER_MAGIC_2ND	0x87
+	#define PNP_EXIT_MAGIC_1ST	0xaa
+	#include <superio/acpi/pnp_config.asl>
+
+#ifdef NCT677X_SHOW_PP
+	#undef SUPERIO_PNP_HID
+	#undef SUPERIO_PNP_LDN
+	#undef SUPERIO_PNP_IO0
+	#undef SUPERIO_PNP_IRQ0
+	#undef SUPERIO_PNP_DMA
+	/*
+	 * The extra code required to dynamically reflect ECP in the HID
+	 * isn't currently justified, so the HID is hardcoded as not
+	 * using ECP. "PNP0401" would indicate ECP.
+	 */
+	#define SUPERIO_PNP_HID "PNP0400"
+	#define SUPERIO_PNP_LDN NCT677X_PP
+	#define SUPERIO_PNP_IO0 0x08, 0x08
+	#define SUPERIO_PNP_IRQ0
+	#define SUPERIO_PNP_DMA
+	#include <superio/acpi/pnp_generic.asl>
+#endif
+
+#undef SUPERIO_UART_DDN
+#undef SUPERIO_UART_PM_REG
+
+#ifdef NCT677X_SHOW_SP1
+	#undef SUPERIO_UART_LDN
+	#define SUPERIO_UART_LDN NCT677X_SP1
+	#include <superio/acpi/pnp_uart.asl>
+#endif
+
+#ifdef NCT677X_SHOW_SP2
+	#undef SUPERIO_UART_LDN
+	#define SUPERIO_UART_LDN NCT677X_SP2
+	#include <superio/acpi/pnp_uart.asl>
+#endif
+
+#ifdef NCT677X_SHOW_KBC
+	#undef SUPERIO_KBC_LDN
+	#undef SUPERIO_KBC_PS2M
+	#undef SUPERIO_KBC_PS2LDN
+	#define SUPERIO_KBC_LDN NCT677X_KBC
+	#define SUPERIO_KBC_PS2M
+	#include <superio/acpi/pnp_kbc.asl>
+#endif
+
+#undef SUPERIO_PNP_HID
+#undef SUPERIO_PNP_DMA
+
+#ifdef NCT677X_SHOW_HWM
+	#undef SUPERIO_PNP_LDN
+	#undef SUPERIO_PNP_IO0
+	#undef SUPERIO_PNP_IO1
+	#undef SUPERIO_PNP_IRQ0
+	#define SUPERIO_PNP_LDN NCT677X_HWM_FPLED
+	#define SUPERIO_PNP_IO0 0x08, 0x08
+	#define SUPERIO_PNP_IO1 0x08, 0x08
+	#define SUPERIO_PNP_IRQ0
+	#include <superio/acpi/pnp_generic.asl>
+#endif
+
+#ifdef NCT677X_SHOW_GPIO
+	#undef SUPERIO_PNP_LDN
+	#undef SUPERIO_PNP_IO0
+	#undef SUPERIO_PNP_IO1
+	#undef SUPERIO_PNP_IRQ0
+	#undef PNP_DEVICE_ACTIVE
+	#define PNP_DEVICE_ACTIVE ACT3
+	#define SUPERIO_PNP_LDN 8
+	#define SUPERIO_PNP_IO0 0x08, 0x08
+	#include <superio/acpi/pnp_generic.asl>
+#endif
+}

From bc240baba5faa5574ee7d441c4b3a669fcb900b4 Mon Sep 17 00:00:00 2001
From: Ivan Kuzneczov <ivan.kuzneczov@hardenedvault.net>
Date: Wed, 31 Dec 2025 02:33:22 +0000
Subject: [PATCH 2942/3886] Documentation: Add method for GRUB2 to load seabios
 from drive

Confirmed on an image with GRUB2 payload and without seabios as
secondary payload.

Signed-off-by: Ivan Kuzneczov <ivan.kuzneczov@hardenedvault.net>
Change-Id: I093a9b9e8cabe6b21ec9d755a1592438209a86c6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90658
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
---
 Documentation/payloads.md | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/Documentation/payloads.md b/Documentation/payloads.md
index 76ff2cd7e7..4c494ab5a9 100644
--- a/Documentation/payloads.md
+++ b/Documentation/payloads.md
@@ -23,6 +23,12 @@ When chainloaded from GRUB2, the following menuentry could be used:
         module /vgaroms/seavgabios.bin
     }
 
+GRUB2 loading seabios from drive via command prompt is also possible:
+
+    multiboot (usb0,msdos1)/seabios/bios.bin.elf
+    module (usb0,msdos1)/seabios/vgabios.bin name=vgaroms/seavgabios.bin
+    boot
+
 ## edk2
 
 [edk2](https://github.com/tianocore/tianocore.github.io/wiki/Getting-Started-with-EDK-II) is an open-source modern, feature-rich,

From 091e8140ea364be638f062666059657a32f2024e Mon Sep 17 00:00:00 2001
From: Yunlong Jia <yunlong.jia@ecs.corp-partner.google.com>
Date: Wed, 31 Dec 2025 08:47:20 +0000
Subject: [PATCH 2943/3886] spd/lp5: Add SPD for RS1G32LO5D2FDB-23BT

Add RS1G32LO5D2FDB-23BT in the memory_parts.json and re-generate
the SPD.

BUG=b:472596025
TEST=util/spd_tools/bin/spd_gen spd/lp5/memory_parts.json lp5

Change-Id: Ic249e6216c927b5080873928509b32587a8a53f6
Signed-off-by: Yunlong Jia <yunlong.jia@ecs.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90662
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
---
 spd/lp5/memory_parts.json                      | 11 +++++++++++
 spd/lp5/set-0/parts_spd_manifest.generated.txt |  1 +
 spd/lp5/set-1/parts_spd_manifest.generated.txt |  1 +
 3 files changed, 13 insertions(+)

diff --git a/spd/lp5/memory_parts.json b/spd/lp5/memory_parts.json
index bb725fcb73..40a8f65ec2 100644
--- a/spd/lp5/memory_parts.json
+++ b/spd/lp5/memory_parts.json
@@ -423,6 +423,17 @@
             "ranksPerChannel": 2,
             "speedMbps": 6400
         }
+    },
+    {
+        "name": "RS1G32LO5D2FDB-23BT",
+        "attribs": {
+            "densityPerDieGb": 16,
+            "diesPerPackage": 2,
+            "bitWidthPerChannel": 16,
+            "ranksPerChannel": 1,
+            "speedMbps": 8533,
+            "lp5x": true
+        }
     }
     ]
 }
diff --git a/spd/lp5/set-0/parts_spd_manifest.generated.txt b/spd/lp5/set-0/parts_spd_manifest.generated.txt
index 7d3c3f378a..3976379d4a 100644
--- a/spd/lp5/set-0/parts_spd_manifest.generated.txt
+++ b/spd/lp5/set-0/parts_spd_manifest.generated.txt
@@ -41,3 +41,4 @@ MT62F1G32D2DS-020 WT:D,spd-11.hex
 K3KL8L80EM-MGCV,spd-11.hex
 MT62F1G32D2DS-031RF WT:C,spd-3.hex
 MT62F2G32D4DS-031RF WT:C,spd-6.hex
+RS1G32LO5D2FDB-23BT,spd-11.hex
diff --git a/spd/lp5/set-1/parts_spd_manifest.generated.txt b/spd/lp5/set-1/parts_spd_manifest.generated.txt
index 7d3c3f378a..3976379d4a 100644
--- a/spd/lp5/set-1/parts_spd_manifest.generated.txt
+++ b/spd/lp5/set-1/parts_spd_manifest.generated.txt
@@ -41,3 +41,4 @@ MT62F1G32D2DS-020 WT:D,spd-11.hex
 K3KL8L80EM-MGCV,spd-11.hex
 MT62F1G32D2DS-031RF WT:C,spd-3.hex
 MT62F2G32D4DS-031RF WT:C,spd-6.hex
+RS1G32LO5D2FDB-23BT,spd-11.hex

From 9b5d98583889f9d6ba829c196f3ebc24a72a723e Mon Sep 17 00:00:00 2001
From: Pierce Chou <chou.pierce@inventec.corp-partner.google.com>
Date: Tue, 16 Dec 2025 10:36:57 +0800
Subject: [PATCH 2944/3886] mb/google/ocelot/var/ocicat: Update audio settings

Ocicat use ALC3247, and confirm with vendor,
That ALC3247 driver is mapping to ALC236 not AL256.

- Follow ocelot setting, add Audio settings
- Update ALC236 Verb table
- Enable hda codec

BUG=b:469132497
TEST=Flash and boot on DUT, audio works normally

Change-Id: Id60dcaadfefafb499b0555a81192b03b77ad9030
Signed-off-by: Pierce Chou <chou.pierce@inventec.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90518
Reviewed-by: Pranava Y N <pranavayn@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 .../google/ocelot/variants/ocicat/hda_verb.c  | 135 +++++++++---------
 .../ocelot/variants/ocicat/overridetree.cb    |   2 +
 .../google/ocelot/variants/ocicat/variant.c   |  21 +++
 3 files changed, 89 insertions(+), 69 deletions(-)

diff --git a/src/mainboard/google/ocelot/variants/ocicat/hda_verb.c b/src/mainboard/google/ocelot/variants/ocicat/hda_verb.c
index 2f703b78ee..bb978b8120 100644
--- a/src/mainboard/google/ocelot/variants/ocicat/hda_verb.c
+++ b/src/mainboard/google/ocelot/variants/ocicat/hda_verb.c
@@ -4,15 +4,16 @@
 
 const u32 cim_verb_data[] = {
 	/* coreboot specific header */
-	0x10ec0256,	/* Codec Vendor / Device ID: Realtek ALC256 */
-	0x10ec12ac,	/* Subsystem ID */
-	0x00000013,	/* Number of jacks (NID entries) */
+	0x10ec0236,	// Codec Vendor / Device ID: Realtek ALC236
+	0x103C8C60,	// Subsystem ID
+	0x00000016,	// Number of jacks (NID entries)
 
 	AZALIA_RESET(0x1),
-	/* NID 0x01, HDA Codec Subsystem ID Verb Table */
-	AZALIA_SUBVENDOR(0, 0x10ec12ac),
+	/* NID 0x01, HDA Codec Subsystem ID Verb table */
+	AZALIA_SUBVENDOR(0, 0x103C8C60),
 
 	/* Pin Widget Verb Table */
+
 	/*
 	 * DMIC
 	 * Requirement is to use PCH DMIC. Hence,
@@ -20,105 +21,101 @@ const u32 cim_verb_data[] = {
 	 * AZALIA_PIN_CFG(0, 0x12, 0x90A60130),
 	 * AZALIA_PIN_CFG(0, 0x13, 0x40000000),
 	 */
+
 	/* Pin widget 0x14 - Front (Port-D) */
 	AZALIA_PIN_CFG(0, 0x14, 0x90170110),
 	/* Pin widget 0x18 - NPC */
 	AZALIA_PIN_CFG(0, 0x18, 0x411111F0),
 	/* Pin widget 0x19 - MIC2 (Port-F) */
-	AZALIA_PIN_CFG(0, 0x19, 0x04A11040),
+	AZALIA_PIN_CFG(0, 0x19, 0x03A11020),
 	/* Pin widget 0x1A - LINE1 (Port-C) */
 	AZALIA_PIN_CFG(0, 0x1a, 0x411111F0),
 	/* Pin widget 0x1B - NPC */
 	AZALIA_PIN_CFG(0, 0x1b, 0x411111F0),
 	/* Pin widget 0x1D - BEEP-IN */
-	AZALIA_PIN_CFG(0, 0x1d, 0x40610041),
+	AZALIA_PIN_CFG(0, 0x1d, 0x40600001),
 	/* Pin widget 0x1E - NPC */
 	AZALIA_PIN_CFG(0, 0x1e, 0x411111F0),
 	/* Pin widget 0x21 - HP1-OUT (Port-I) */
-	AZALIA_PIN_CFG(0, 0x21, 0x04211020),
+	AZALIA_PIN_CFG(0, 0x21, 0x03211040),
+
 	/*
 	 * Widget node 0x20 - 1
-	 * Codec hidden reset and speaker power 2W/4ohm
-	 */
-	0x0205001A,
-	0x0204C003,
-	0x02050038,
-	0x02047901,
-	/*
-	 * Widget node 0x20 - 2
-	 * Class D power on Reset
 	 */
 	0x0205003C,
 	0x02040354,
 	0x0205003C,
 	0x02040314,
 	/*
-	 * Widget node 0x20 - 3
-	 * Disable AGC and set AGC limit to -1.5dB
+	 * Widget node 0x20 - 2
+	 * Set JD2 pull high
 	 */
-	0x02050016,
-	0x02040C50,
-	0x02050012,
-	0x0204EBC1,
-	/*
-	 * Widget node 0x20 - 4
-	 * Set AGC Post gain +1.5dB then Enable AGC
-	 */
-	0x02050013,
-	0x02044023,
-	0x02050016,
-	0x02040E50,
-	/*
-	 * Widget node 0x20 - 5
-	 * Silence detector enabling + Set EAPD to verb control
-	 */
-	0x02050037,
-	0x0204FE15,
-	0x02050010,
-	0x02040020,
-	/*
-	 * Widget node 0x20 - 6
-	 * Silence data mode Threshold (-90dB)
-	 */
-	0x02050030,
-	0x0204A000,
 	0x0205001B,
 	0x02040A4B,
+	0x0205000B,
+	0x02047778,
 	/*
-	 * Widget node 0x20 - 7
-	 * Default setting-1
+	 * Widget node 0x20 - 3
 	 */
-	0x05750003,
-	0x05740DA3,
 	0x02050046,
 	0x02040004,
-	/*
-	 * Widget node 0x20 - 8
-	 * support 1 pin detect two port
-	 */
-	0x02050009,
-	0x0204E003,
-	0x0205000A,
-	0x02047770,
-	/*
-	 * Widget node 0x20 - 9
-	 * To set LDO1/LDO2 as default
-	 */
-	0x02050008,
-	0x02046A0C,
-	0x02050008,
-	0x02046A0C,
+	0x05750003,
+	0x057409A3,
+	/* disable EQ first */
+	0x05350000,
+	0x0534201A,
+	/* Left Channel */
+	0x0535001d,
+	0x05340800,
+	0x0535001e,
+	0x05340800,
+	0x05350003,
+	0x05341F7B,
+	0x05350004,
+	0x05340000,
+	/* Right Channel */
+	0x05450000,
+	0x05442000,
+	0x0545001d,
+	0x05440800,
+	0x0545001e,
+	0x05440800,
+	0x05450003,
+	0x05441F7B,
+	0x05450004,
+	0x05440000,
+	/* enable EQ */
+	0x05350000,
+	0x0534E01A,
+	/* 2.2W/4ohm */
+	0x02050038,
+	0x02046901,
+	/* Disable AGC and set AGC limit to 0dB */
+	0x02050016,
+	0x02044C50,
+	0x02050012,
+	0x0204EBC0,
+	/* Set AGC Front and Post gain 0dB then Enable AGC */
+	0x02050013,
+	0x0204401F,
+	0x02050016,
+	0x02044E50,
+	/* Headphone Pop */
+	0x05750007,
+	0x057412B2,
+	0x05750007,	/* Padding */
+	0x057412B2,	/* Padding */
 };
 
 const u32 pc_beep_verbs[] = {
 	/* Dos beep path - 1 */
-	0x01470C00,
 	0x02050036,
 	0x02047151,
-	0x01470740,
+	0x02050010,
+	0x02040020,
 	/* Dos beep path - 2 */
-	0x0143b000,
-	0x01470C02,
+	0x0143B000,
+	0x01470740,
 	0x01470C02,
 	0x01470C02,
 };
diff --git a/src/mainboard/google/ocelot/variants/ocicat/overridetree.cb b/src/mainboard/google/ocelot/variants/ocicat/overridetree.cb
index ba43e1589e..e1f32ada9b 100644
--- a/src/mainboard/google/ocelot/variants/ocicat/overridetree.cb
+++ b/src/mainboard/google/ocelot/variants/ocicat/overridetree.cb
@@ -17,6 +17,8 @@ fw_config
 end
 
 chip soc/intel/pantherlake
+        # HD Audio
+        register "pch_hda_audio_link_hda_enable" = "true"
 
 	register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Type C port - various configurations - TCP0
 	register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Type C port - various configurations - TCP1
diff --git a/src/mainboard/google/ocelot/variants/ocicat/variant.c b/src/mainboard/google/ocelot/variants/ocicat/variant.c
index 0bfbdf05ed..a7154dada0 100644
--- a/src/mainboard/google/ocelot/variants/ocicat/variant.c
+++ b/src/mainboard/google/ocelot/variants/ocicat/variant.c
@@ -14,6 +14,11 @@ void variant_update_soc_memory_init_params(FSPM_UPD *memupd)
 {
 	FSP_M_CONFIG *m_cfg = &memupd->FspmConfig;
 
+	/* HDA Audio */
+	printk(BIOS_INFO, "Overriding HDA SDI lanes.\n");
+	m_cfg->PchHdaSdiEnable[0] = true;
+	m_cfg->PchHdaSdiEnable[1] = false;
+
 	/* Override FSP-M SaGv frequency and gear for DDR5 boards */
 	m_cfg->SaGvFreq[0] = 3200;
 	m_cfg->SaGvGear[0] = GEAR_4;
@@ -46,3 +51,19 @@ void variant_update_soc_memory_init_params(FSPM_UPD *memupd)
 	memcpy(m_cfg->PhyClockToCkdDimm, phy_clock_to_ckd_dimm,
 		sizeof(phy_clock_to_ckd_dimm));
 }
+
+/*
+ * HDA verb table loading is supported based on the firmware configuration.
+ *
+ * This function determines if the current platform has an HDA codec enabled by
+ * examining the `FW_CONFIG` value. Specifically, it checks if the
+ * `FW_CONFIG` includes the `AUDIO_ALC256_HDA` value, which is used to identify
+ * Fatcat SKUs with HDA codec support.
+ *
+ * Return true if the `FW_CONFIG` indicates HDA support (i.e., contains
+ * `AUDIO_ALC256_HDA`), false otherwise.
+ */
+bool mainboard_is_hda_codec_enabled(void)
+{
+	return true;
+}

From c3ff1addde6f92211934beed50261eccd8b8028b Mon Sep 17 00:00:00 2001
From: Pierce Chou <chou.pierce@inventec.corp-partner.google.com>
Date: Tue, 16 Dec 2025 13:13:32 +0800
Subject: [PATCH 2945/3886] mb/google/ocelot/var/ocicat: Add WIFI SAR table

- Add WIFI SAR table for intel WIFI SAR table
- Follow new UFSC definitions to rename WIFI config

BUG=b:469226622
TEST=Build and flash to DUT, check that SAR table is
loaded by cbmem -1 | grep sar

Change-Id: Iba3c4588c969a74dd83d176124addfa2d115edbd
Signed-off-by: Pierce Chou <chou.pierce@inventec.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90520
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Pranava Y N <pranavayn@google.com>
---
 .../ocelot/variants/ocicat/overridetree.cb       | 16 ++++++++--------
 .../google/ocelot/variants/ocicat/variant.c      |  5 +++++
 2 files changed, 13 insertions(+), 8 deletions(-)

diff --git a/src/mainboard/google/ocelot/variants/ocicat/overridetree.cb b/src/mainboard/google/ocelot/variants/ocicat/overridetree.cb
index e1f32ada9b..03f782fad3 100644
--- a/src/mainboard/google/ocelot/variants/ocicat/overridetree.cb
+++ b/src/mainboard/google/ocelot/variants/ocicat/overridetree.cb
@@ -1,9 +1,4 @@
 fw_config
-	field WIFI 2 4
-		option WIFI_NONE			0
-		option WIFI_CNVI_7			1
-		option WIFI_PCIE_7			2
-	end
 	field STORAGE_TYPE 12 14
 		option STORAGE_TYPE_UNKNOWN		0
 		option STORAGE_TYPE_NVME_GEN4		1
@@ -14,6 +9,11 @@ fw_config
 		option TOUCH_ELAN_TOP	1
 		option TOUCH_ELAN_DBTS	2
 	end
+	field WIFI_INTERFACE 26 27
+		option WIFI_INTERFACE_UNKNOWN		0
+		option WIFI_INTERFACE_CNVI_7		1
+		option WIFI_INTERFACE_PCIE_7		2
+	end
 end
 
 chip soc/intel/pantherlake
@@ -328,7 +328,7 @@ chip soc/intel/pantherlake
 						register "type" = "UPC_TYPE_INTERNAL"
 						register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B09)"
 						device ref usb2_port8 on
-							probe WIFI WIFI_PCIE_7
+                                                       probe WIFI_INTERFACE WIFI_INTERFACE_PCIE_7
 	                                	end
 
 					end
@@ -365,7 +365,7 @@ chip soc/intel/pantherlake
 		end # Gen4 M.2 SSD
 
 		device ref pcie_rp5 on
-			probe WIFI WIFI_PCIE_7
+			probe WIFI_INTERFACE WIFI_INTERFACE_PCIE_7
 			register "pcie_rp[PCIE_RP(5)]" = "{
 			.clk_src = 0,
 			.clk_req = 0,
@@ -384,7 +384,7 @@ chip soc/intel/pantherlake
 		end # CNVi
 
 		device ref cnvi_bluetooth on
-			probe WIFI WIFI_CNVI_7
+			probe WIFI_INTERFACE WIFI_INTERFACE_CNVI_7
 			chip soc/intel/common/block/cnvi
 				register "wake" = "GPE0_PME_B0"
 				device generic 0 on end
diff --git a/src/mainboard/google/ocelot/variants/ocicat/variant.c b/src/mainboard/google/ocelot/variants/ocicat/variant.c
index a7154dada0..733cf6bf3b 100644
--- a/src/mainboard/google/ocelot/variants/ocicat/variant.c
+++ b/src/mainboard/google/ocelot/variants/ocicat/variant.c
@@ -10,6 +10,11 @@
 #include <soc/gpio_soc_defs.h>
 #include <drivers/intel/touch/chip.h>
 
+const char *get_wifi_sar_cbfs_filename(void)
+{
+	return get_wifi_sar_fw_config_filename(FW_CONFIG_FIELD(WIFI_INTERFACE));
+}
+
 void variant_update_soc_memory_init_params(FSPM_UPD *memupd)
 {
 	FSP_M_CONFIG *m_cfg = &memupd->FspmConfig;

From b8680d53ac426b8352a1ae6f0cb72780a0d8d82f Mon Sep 17 00:00:00 2001
From: Pierce Chou <chou.pierce@inventec.corp-partner.google.com>
Date: Tue, 23 Dec 2025 09:53:05 +0800
Subject: [PATCH 2946/3886] mb/google/ocelot/var/ocicat: Add fw_config
 definitions with UFSC

Enable Unified Firmware and Secondary Source Configuration (UFSC)
support for ocicat.
UFSC standardizes the bitfields and bitmap definitions for firmware
configuration. Update overridetree.cb with new UFSC definitions and
enable EC_GOOGLE_CHROMEEC_FW_CONFIG_FROM_UFSC.

BUG=b:471067114
TEST=Ensure the probed fw_config matches the written configuration.

Change-Id: I6be36f6cec2b7e25b7e6170f12e71ae3fabf283e
Signed-off-by: Pierce Chou <chou.pierce@inventec.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90598
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Pranava Y N <pranavayn@google.com>
---
 src/mainboard/google/ocelot/Kconfig           |  3 +-
 .../ocelot/variants/ocicat/overridetree.cb    | 29 +++++++++++++------
 2 files changed, 21 insertions(+), 11 deletions(-)

diff --git a/src/mainboard/google/ocelot/Kconfig b/src/mainboard/google/ocelot/Kconfig
index 1576db3671..f83e19aa6a 100644
--- a/src/mainboard/google/ocelot/Kconfig
+++ b/src/mainboard/google/ocelot/Kconfig
@@ -98,8 +98,6 @@ config BOARD_GOOGLE_MODEL_OJAL
 config BOARD_GOOGLE_MODEL_OCICAT
 	def_bool n
 	select BOARD_GOOGLE_BASEBOARD_OCELOT
-	select DRIVERS_GENERIC_BAYHUB_LV2
-	select DRIVERS_GENERIC_MAX98357A
 	select DRIVERS_INTEL_TOUCH
 	select FSP_UGOP_EARLY_SIGN_OF_LIFE
 	select SPD_CACHE_ENABLE
@@ -137,6 +135,7 @@ config BOARD_GOOGLE_OJAL
 
 config BOARD_GOOGLE_OCICAT
 	select BOARD_GOOGLE_MODEL_OCICAT
+	select EC_GOOGLE_CHROMEEC_FW_CONFIG_FROM_UFSC
 
 if BOARD_GOOGLE_OCELOT_COMMON
 
diff --git a/src/mainboard/google/ocelot/variants/ocicat/overridetree.cb b/src/mainboard/google/ocelot/variants/ocicat/overridetree.cb
index 03f782fad3..52ada4b77c 100644
--- a/src/mainboard/google/ocelot/variants/ocicat/overridetree.cb
+++ b/src/mainboard/google/ocelot/variants/ocicat/overridetree.cb
@@ -1,18 +1,26 @@
 fw_config
+	field AUDIO_CODEC 0 2
+		option AUDIO_CODEC_UNKNOWN	0
+		option AUDIO_CODEC_ALC3247	1
+	end
 	field STORAGE_TYPE 12 14
-		option STORAGE_TYPE_UNKNOWN		0
-		option STORAGE_TYPE_NVME_GEN4		1
-		option STORAGE_UFS			2
+		option STORAGE_TYPE_UNKNOWN	0
+		option STORAGE_TYPE_NVME_GEN4	1
+		option STORAGE_UFS		2
 	end
 	field TOUCHSCREEN 17 18
 		option TOUCHSCREEN_UNKNOWN	0
-		option TOUCH_ELAN_TOP	1
-		option TOUCH_ELAN_DBTS	2
+		option TOUCH_ELAN_TOP		1
+		option TOUCH_ELAN_DBTS		2
+	end
+	field SENSOR_HUB 23 23
+		option ISH_ABSENT		0
+		option ISH_PRESENT		1
 	end
 	field WIFI_INTERFACE 26 27
-		option WIFI_INTERFACE_UNKNOWN		0
-		option WIFI_INTERFACE_CNVI_7		1
-		option WIFI_INTERFACE_PCIE_7		2
+		option WIFI_INTERFACE_UNKNOWN	0
+		option WIFI_INTERFACE_CNVI_7	1
+		option WIFI_INTERFACE_PCIE_7	2
 	end
 end
 
@@ -464,11 +472,14 @@ chip soc/intel/pantherlake
 
 		device ref smbus on end
 		device ref hda on
+			probe AUDIO_CODEC AUDIO_CODEC_ALC3247
 			chip drivers/sof
 				register "spkr_tplg" = "max98360a"
 				register "jack_tplg" = "rt5682"
 				register "mic_tplg" = "_2ch_pdm0"
-				device generic 0 on end
+				device generic 0 on
+					probe AUDIO_CODEC AUDIO_CODEC_ALC3247
+				end
 			end
 		end
 	end

From 56013ce0ff12546997b85b8334544a6bf4d15043 Mon Sep 17 00:00:00 2001
From: Venkateshwar S <vens@qualcomm.corp-partner.google.com>
Date: Tue, 30 Dec 2025 02:05:55 -0800
Subject: [PATCH 2947/3886] mainboard/google/bluey: Skip SHRM firmware
 load/reset in ramdump mode
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

The SHRM firmware load and reset sequence currently runs
unconditionally during the boot process. This causes issues during RAM
dump collection, where the contents of the SHRM region must remain
intact for post‑crash analysis.

This patch adds a Dload‑mode check (which indicates RAM‑dump mode) and
skips shrm_fw_load_reset() when that bit is set. This prevents
unintended SHRM resets during RAM dump capture and ensures the firmware
load/reset sequence only runs during a normal cold boot.

A RAM dump is a debug image used after a crash to preserve system
memory for post‑crash analysis.

Test=Create an image.serial.bin and ensure it boots on X1P42100.

Change-Id: Ie3d1ff9462a48d21f1daae1f80322ea397731be5
Signed-off-by: Venkateshwar S <vens@qualcomm.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90651
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
---
 src/mainboard/google/bluey/romstage.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/src/mainboard/google/bluey/romstage.c b/src/mainboard/google/bluey/romstage.c
index 3ada667376..06cd5626bd 100644
--- a/src/mainboard/google/bluey/romstage.c
+++ b/src/mainboard/google/bluey/romstage.c
@@ -94,7 +94,8 @@ void platform_romstage_main(void)
 	if (CONFIG(EC_GOOGLE_CHROMEEC) && CONFIG(CONSOLE_SERIAL))
 		platform_dump_battery_soc_information();
 
-	shrm_fw_load_reset();
+	if (!qclib_check_dload_mode())
+		shrm_fw_load_reset();
 
 	/* QCLib: DDR init & train */
 	qclib_load_and_run();

From fe0e14d716ffab43784f13b9ac8fae6f13672645 Mon Sep 17 00:00:00 2001
From: Venkateshwar S <vens@qualcomm.corp-partner.google.com>
Date: Tue, 30 Dec 2025 02:08:15 -0800
Subject: [PATCH 2948/3886] soc/qualcomm/x1p42100: Skip SHRM meta firmware load
 in ramdump mode

QCLib passes SHRM metadata to TME for authentication and to bring SHRM
out of reset. In RAM dump mode, this sequence is unnecessary because
the system is preserving state for post-crash analysis.

This patch adds a RAM-dump-mode check and ensures:
- SHRM metadata is not loaded or populated into the interface table
  when RAM dump mode is detected, preventing QCLib from sending it to
  TME.

Test=Create an image.serial.bin and verify it boots on X1P42100.

Change-Id: I921a2b99543ee462433bec8e8471ad836cabc5dd
Signed-off-by: Venkateshwar S <vens@qualcomm.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90652
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
---
 src/soc/qualcomm/x1p42100/qclib.c | 18 ++++++++++--------
 1 file changed, 10 insertions(+), 8 deletions(-)

diff --git a/src/soc/qualcomm/x1p42100/qclib.c b/src/soc/qualcomm/x1p42100/qclib.c
index c67b3591f0..6baabccb20 100644
--- a/src/soc/qualcomm/x1p42100/qclib.c
+++ b/src/soc/qualcomm/x1p42100/qclib.c
@@ -47,15 +47,17 @@ int qclib_soc_override(struct qclib_cb_if_table *table)
 	}
 	qclib_add_if_table_entry(QCLIB_TE_CPR_SETTINGS, _cpr_settings, data_size, 0);
 
-	/* Attempt to load shrm_meta Blob */
-	data_size = cbfs_load(qclib_file(QCLIB_CBFS_SHRM_META),
-			_qc_blob_meta, REGION_SIZE(qc_blob_meta));
-	if (!data_size) {
-		printk(BIOS_ERR, "[%s] /shrm_meta failed\n", __func__);
-		return -1;
-	}
+	if (!qclib_check_dload_mode())	{
+		/* Attempt to load shrm_meta Blob */
+		data_size = cbfs_load(qclib_file(QCLIB_CBFS_SHRM_META),
+				_qc_blob_meta, REGION_SIZE(qc_blob_meta));
+		if (!data_size) {
+			printk(BIOS_ERR, "[%s] /shrm_meta failed\n", __func__);
+			return -1;
+		}
 
-	qclib_add_if_table_entry(QCLIB_TE_SHRM_META_SETTINGS, _qc_blob_meta, data_size, 0);
+		qclib_add_if_table_entry(QCLIB_TE_SHRM_META_SETTINGS, _qc_blob_meta, data_size, 0);
+	}
 
 	/* hook for platform specific policy configuration */
 	if (qclib_mainboard_override(table)) {

From 7896d94c76589c83b9474eb1ba343e37c92f5c0d Mon Sep 17 00:00:00 2001
From: Venkateshwar S <vens@qualcomm.corp-partner.google.com>
Date: Tue, 30 Dec 2025 00:36:39 -0800
Subject: [PATCH 2949/3886] soc/qualcomm/x1p42100: Avoid reserving display
 buffer region

The display buffer was previously reserved as unavailable by coreboot,
which prevented the kernel from mapping it. When the splash driver
released the buffer, the kernel later crashed on access because the
region was never mapped.

This patch removes the reservation so the kernel can map the display
buffer and reuse it safely.

TEST=Create an image.serial.bin and ensure it boots on X1P42100.
Check that the display memory region is mapped by kernel in UART logs:

[    0.000000][    T0]   node   0: [mem 0x00000000e36a0000-
						0x00000000f7bfffff]

Change-Id: I507d48713690bac3030f81a29c7e123fd3a03b95
Signed-off-by: Venkateshwar S <vens@qualcomm.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90648
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
---
 src/soc/qualcomm/x1p42100/soc.c | 1 -
 1 file changed, 1 deletion(-)

diff --git a/src/soc/qualcomm/x1p42100/soc.c b/src/soc/qualcomm/x1p42100/soc.c
index d1762237d5..78fa43a175 100644
--- a/src/soc/qualcomm/x1p42100/soc.c
+++ b/src/soc/qualcomm/x1p42100/soc.c
@@ -51,7 +51,6 @@ static void soc_read_resources(struct device *dev)
 	reserved_ram_range(dev, index++, (uintptr_t)_dram_wlan, REGION_SIZE(dram_wlan));
 	reserved_ram_range(dev, index++, (uintptr_t)_dram_pil, REGION_SIZE(dram_pil));
 	reserved_ram_range(dev, index++, (uintptr_t)_dram_ta, REGION_SIZE(dram_ta));
-	reserved_ram_range(dev, index++, (uintptr_t)_dram_display, REGION_SIZE(dram_display));
 
 	/* ACDB carveout region located at 0xFF800000 - (n*5.5 +1+32+3) where n is size of DDR */
 	reserved_ram_range(dev, index++, (uintptr_t)(_dram_llcc_lpi - calc_acdb_carveout_size()),

From b8402a8dfc658f5b6aef7ca04e2dcadccf816c48 Mon Sep 17 00:00:00 2001
From: Venkateshwar S <vens@qualcomm.corp-partner.google.com>
Date: Tue, 30 Dec 2025 02:27:20 -0800
Subject: [PATCH 2950/3886] src/qualcomm/common: Remove display buffer region
 declarations

The display buffer reservation logic has been removed, so the related
symbol declarations are no longer needed.

TEST=Create an image.serial.bin and ensure it boots on X1P42100.

Change-Id: I873fdcff4071e0d2cf683017557abdfdb13e8b16
Signed-off-by: Venkateshwar S <vens@qualcomm.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90653
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
---
 src/soc/qualcomm/common/include/soc/symbols_common.h | 1 -
 1 file changed, 1 deletion(-)

diff --git a/src/soc/qualcomm/common/include/soc/symbols_common.h b/src/soc/qualcomm/common/include/soc/symbols_common.h
index ee2d3510b6..847225216a 100644
--- a/src/soc/qualcomm/common/include/soc/symbols_common.h
+++ b/src/soc/qualcomm/common/include/soc/symbols_common.h
@@ -48,7 +48,6 @@ DECLARE_REGION(dram_llcc_lpi)
 DECLARE_REGION(dram_ta)
 DECLARE_REGION(dram_pdp)
 DECLARE_REGION(dram_pil)
-DECLARE_REGION(dram_display)
 
 /*
  * DDR_SPACE (2 GB) aka `_dram`:  0x80000000 - 0x100000000

From 4030fc5f917ca4148ab16d65d7ace13f15b48f83 Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Mon, 29 Dec 2025 10:07:33 -0600
Subject: [PATCH 2951/3886] device/Kconfig: Gate early libgfxinit default on
 ChromeOS

Early libgfxinit is currently only used for ChromeOS ESOL features, so
only auto-enable MAINBOARD_USE_EARLY_LIBGFXINIT when both
MAINBOARD_HAS_EARLY_LIBGFXINIT and CHROMEOS are enabled, preventing
unnecessary Ada toolchain requirements for non-ChromeOS builds.

TEST=build/boot google/yaviks w/o CHROMEOS support, verify ADA/gnat
not needed to compile.

Change-Id: Ieec2a15783ce57015579d14aba0f67783c79b02c
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90636
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
---
 src/device/Kconfig | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/device/Kconfig b/src/device/Kconfig
index f185ecb4c3..39aa7dd193 100644
--- a/src/device/Kconfig
+++ b/src/device/Kconfig
@@ -126,7 +126,7 @@ endchoice
 
 choice
 	prompt "Early (romstage) graphics initialization"
-	default MAINBOARD_USE_EARLY_LIBGFXINIT if MAINBOARD_HAS_EARLY_LIBGFXINIT
+	default MAINBOARD_USE_EARLY_LIBGFXINIT if MAINBOARD_HAS_EARLY_LIBGFXINIT && CHROMEOS
 	default NO_EARLY_GFX_INIT
 
 config NO_EARLY_GFX_INIT

From 3d980dae22274e3d3f806a2ca9b60cfe5b9ca6b9 Mon Sep 17 00:00:00 2001
From: Yanqiong Huang <huangyanqiong@huaqin.corp-partner.google.com>
Date: Thu, 18 Dec 2025 19:19:07 +0800
Subject: [PATCH 2952/3886] mb/google/nissa/var/rull: Add 3 DDR modules to RAM
 id table

Add HYNIX H9JCNNNCP3MLYR-N6E and MICRON MT62F1G32D4DR-031 WT:B as id 5,
and add SAMSUNG K3LKBKB0BM-MGCP as id 6, resulting in the list below:

DRAM Part Name                 ID to assign
MT62F512M32D2DR-031 WT:B       0 (0000)
H9JCNNNBK3MLYR-N6E             0 (0000)
K3KL8L80CM-MGCT                1 (0001)
H58G56BK7BX068                 1 (0001)
K3KL9L90CM-MGCT                2 (0010)
H58G66BK8BX067                 3 (0011)
H58G56BK8BX068                 4 (0100)
MT62F1G32D2DS-023 WT:B         4 (0100)
H58G56CK8BX146                 4 (0100)
H9JCNNNCP3MLYR-N6E             5 (0101)
MT62F1G32D4DR-031 WT:B         5 (0101)
K3LKBKB0BM-MGCP                6 (0110)

BUG=b:470691660
TEST=Use part_id_gen to generate related settings

Change-Id: Id37f83e54f5be12087010c8045b6dfe407820f48
Signed-off-by: Yanqiong Huang <huangyanqiong@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90548
Reviewed-by: Qinghong Zeng <zengqinghong@huaqin.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
---
 src/mainboard/google/brya/variants/rull/memory/Makefile.mk     | 2 ++
 .../google/brya/variants/rull/memory/dram_id.generated.txt     | 3 +++
 .../google/brya/variants/rull/memory/mem_parts_used.txt        | 3 +++
 3 files changed, 8 insertions(+)

diff --git a/src/mainboard/google/brya/variants/rull/memory/Makefile.mk b/src/mainboard/google/brya/variants/rull/memory/Makefile.mk
index ae7be6dcd1..682003b9af 100644
--- a/src/mainboard/google/brya/variants/rull/memory/Makefile.mk
+++ b/src/mainboard/google/brya/variants/rull/memory/Makefile.mk
@@ -9,3 +9,5 @@ SPD_SOURCES += spd/lp5/set-0/spd-7.hex      # ID = 1(0b0001)  Parts = K3KL8L80CM
 SPD_SOURCES += spd/lp5/set-0/spd-8.hex      # ID = 2(0b0010)  Parts = K3KL9L90CM-MGCT
 SPD_SOURCES += spd/lp5/set-0/spd-10.hex      # ID = 3(0b0011)  Parts = H58G66BK8BX067
 SPD_SOURCES += spd/lp5/set-0/spd-11.hex      # ID = 4(0b0100)  Parts = H58G56BK8BX068, MT62F1G32D2DS-023 WT:B, H58G56CK8BX146
+SPD_SOURCES += spd/lp5/set-0/spd-2.hex      # ID = 5(0b0101)  Parts = H9JCNNNCP3MLYR-N6E, MT62F1G32D4DR-031 WT:B
+SPD_SOURCES += spd/lp5/set-0/spd-3.hex      # ID = 6(0b0110)  Parts = K3LKBKB0BM-MGCP
diff --git a/src/mainboard/google/brya/variants/rull/memory/dram_id.generated.txt b/src/mainboard/google/brya/variants/rull/memory/dram_id.generated.txt
index 6a8d4b9db2..3f8483a688 100644
--- a/src/mainboard/google/brya/variants/rull/memory/dram_id.generated.txt
+++ b/src/mainboard/google/brya/variants/rull/memory/dram_id.generated.txt
@@ -13,3 +13,6 @@ H58G66BK8BX067                 3 (0011)
 H58G56BK8BX068                 4 (0100)
 MT62F1G32D2DS-023 WT:B         4 (0100)
 H58G56CK8BX146                 4 (0100)
+H9JCNNNCP3MLYR-N6E             5 (0101)
+MT62F1G32D4DR-031 WT:B         5 (0101)
+K3LKBKB0BM-MGCP                6 (0110)
diff --git a/src/mainboard/google/brya/variants/rull/memory/mem_parts_used.txt b/src/mainboard/google/brya/variants/rull/memory/mem_parts_used.txt
index 4946ff0ab9..4b0c83cb1d 100644
--- a/src/mainboard/google/brya/variants/rull/memory/mem_parts_used.txt
+++ b/src/mainboard/google/brya/variants/rull/memory/mem_parts_used.txt
@@ -18,3 +18,6 @@ H58G66BK8BX067
 H58G56BK8BX068
 MT62F1G32D2DS-023 WT:B
 H58G56CK8BX146
+H9JCNNNCP3MLYR-N6E
+MT62F1G32D4DR-031 WT:B
+K3LKBKB0BM-MGCP

From 19deb55f0237c917876b992a5da37c4c4f57b8a0 Mon Sep 17 00:00:00 2001
From: Keith Hui <buurin@gmail.com>
Date: Sun, 28 Dec 2025 19:37:25 -0500
Subject: [PATCH 2953/3886] mb/asrock/fatal1ty_z87_professional: Temporarily
 refactor nuvoton_pnp_*()

As the pair of non-ramstage Nuvoton SIO config mode entry/exit functions
see wider use, they are being moved to sio/nuvoton/common/.

This mainboard carries 2 local copies. This preparatory patch moves it
out of smihandler.c into a temporary C file to prevent build breakage.
It is to be removed when the shared copy is in place.

WARNING: Disassembly of compiled SMM code shows a possible stack issue.
Do not flash a binary with this patch applied but without the final
shared version above.

Change-Id: I685ebe6c2bb638d815ccf1fcdd1d73edc176c69e
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90655
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
---
 .../fatal1ty_z87_professional/Makefile.mk     |  2 ++
 .../fatal1ty_z87_professional/mainboard.c     | 18 --------------
 .../fatal1ty_z87_professional/nuvoton.c       | 24 +++++++++++++++++++
 .../fatal1ty_z87_professional/smihandler.c    | 18 --------------
 4 files changed, 26 insertions(+), 36 deletions(-)
 create mode 100644 src/mainboard/asrock/fatal1ty_z87_professional/nuvoton.c

diff --git a/src/mainboard/asrock/fatal1ty_z87_professional/Makefile.mk b/src/mainboard/asrock/fatal1ty_z87_professional/Makefile.mk
index 93f729d787..de5aa51b34 100644
--- a/src/mainboard/asrock/fatal1ty_z87_professional/Makefile.mk
+++ b/src/mainboard/asrock/fatal1ty_z87_professional/Makefile.mk
@@ -4,3 +4,5 @@ bootblock-y += bootblock.c
 bootblock-y += gpio.c
 romstage-y += gpio.c
 ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads
+smm-y += nuvoton.c
+ramstage-y += nuvoton.c
diff --git a/src/mainboard/asrock/fatal1ty_z87_professional/mainboard.c b/src/mainboard/asrock/fatal1ty_z87_professional/mainboard.c
index 1e62d65d2e..8e30e3c61c 100644
--- a/src/mainboard/asrock/fatal1ty_z87_professional/mainboard.c
+++ b/src/mainboard/asrock/fatal1ty_z87_professional/mainboard.c
@@ -10,24 +10,6 @@
 #include <southbridge/intel/lynxpoint/pch.h>
 
 #define GPIO1_DEV PNP_DEV(0x2e, NCT6776_WDT1_GPIO01A_V)
-#define NUVOTON_ENTRY_KEY 0x87
-#define NUVOTON_EXIT_KEY 0xAA
-
-/* Enable configuration: pass entry key '0x87' into index port dev
- * two times. */
-void nuvoton_pnp_enter_conf_state(pnp_devfn_t dev)
-{
-	u16 port = dev >> 8;
-	outb(NUVOTON_ENTRY_KEY, port);
-	outb(NUVOTON_ENTRY_KEY, port);
-}
-
-/* Disable configuration: pass exit key '0xAA' into index port dev. */
-void nuvoton_pnp_exit_conf_state(pnp_devfn_t dev)
-{
-	u16 port = dev >> 8;
-	outb(NUVOTON_EXIT_KEY, port);
-}
 
 static void turn_off_leds(void *unused)
 {
diff --git a/src/mainboard/asrock/fatal1ty_z87_professional/nuvoton.c b/src/mainboard/asrock/fatal1ty_z87_professional/nuvoton.c
new file mode 100644
index 0000000000..56453329cb
--- /dev/null
+++ b/src/mainboard/asrock/fatal1ty_z87_professional/nuvoton.c
@@ -0,0 +1,24 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <device/pnp_ops.h>
+#include <superio/nuvoton/common/nuvoton.h>
+#include <superio/nuvoton/nct6776/nct6776.h>
+
+#define NUVOTON_ENTRY_KEY 0x87
+#define NUVOTON_EXIT_KEY 0xAA
+
+/* Enable configuration: pass entry key '0x87' into index port dev
+ * two times. */
+void nuvoton_pnp_enter_conf_state(pnp_devfn_t dev)
+{
+	u16 port = dev >> 8;
+	outb(NUVOTON_ENTRY_KEY, port);
+	outb(NUVOTON_ENTRY_KEY, port);
+}
+
+/* Disable configuration: pass exit key '0xAA' into index port dev. */
+void nuvoton_pnp_exit_conf_state(pnp_devfn_t dev)
+{
+	u16 port = dev >> 8;
+	outb(NUVOTON_EXIT_KEY, port);
+}
diff --git a/src/mainboard/asrock/fatal1ty_z87_professional/smihandler.c b/src/mainboard/asrock/fatal1ty_z87_professional/smihandler.c
index 6736c15bcd..5ecf42409c 100644
--- a/src/mainboard/asrock/fatal1ty_z87_professional/smihandler.c
+++ b/src/mainboard/asrock/fatal1ty_z87_professional/smihandler.c
@@ -7,24 +7,6 @@
 #include <superio/nuvoton/nct6776/nct6776.h>
 
 #define GPIO1_DEV PNP_DEV(0x2e, NCT6776_WDT1_GPIO01A_V)
-#define NUVOTON_ENTRY_KEY 0x87
-#define NUVOTON_EXIT_KEY 0xAA
-
-/* Enable configuration: pass entry key '0x87' into index port dev
- * two times. */
-void nuvoton_pnp_enter_conf_state(pnp_devfn_t dev)
-{
-	u16 port = dev >> 8;
-	outb(NUVOTON_ENTRY_KEY, port);
-	outb(NUVOTON_ENTRY_KEY, port);
-}
-
-/* Disable configuration: pass exit key '0xAA' into index port dev. */
-void nuvoton_pnp_exit_conf_state(pnp_devfn_t dev)
-{
-	u16 port = dev >> 8;
-	outb(NUVOTON_EXIT_KEY, port);
-}
 
 void mainboard_smi_sleep(u8 slp_typ)
 {

From 0c2a3002d9fcffc9b22d1c39fc27ff8ebf9875bc Mon Sep 17 00:00:00 2001
From: Keith Hui <buurin@gmail.com>
Date: Sun, 28 Dec 2025 19:50:37 -0500
Subject: [PATCH 2954/3886] mb/asrock/z87_extreme4: Temporarily refactor
 nuvoton_pnp_*_conf_state()

As the pair of non-ramstage Nuvoton SIO config mode entry/exit functions
see wider use, they are being moved to sio/nuvoton/common.

This mainboard carries 2 local copies. This preparatory patch moves them
out of smihandler.c and mainboard.c into a temporary C file to prevent
build breakage. It is to be removed when the shared copy is in place.

WARNING: Disassembly of	compiled SMM code shows	a possible stack issue.
Do not flash a binary with this patch applied but without the final
shared version above.

Change-Id: I7a5394478281ac3b92d257e2f0201264b95bb4e5
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90656
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
---
 src/mainboard/asrock/z87_extreme4/Makefile.mk |  2 ++
 src/mainboard/asrock/z87_extreme4/mainboard.c | 18 --------------
 src/mainboard/asrock/z87_extreme4/nuvoton.c   | 24 +++++++++++++++++++
 .../asrock/z87_extreme4/smihandler.c          | 18 --------------
 4 files changed, 26 insertions(+), 36 deletions(-)
 create mode 100644 src/mainboard/asrock/z87_extreme4/nuvoton.c

diff --git a/src/mainboard/asrock/z87_extreme4/Makefile.mk b/src/mainboard/asrock/z87_extreme4/Makefile.mk
index c3cf55d397..58368c333e 100644
--- a/src/mainboard/asrock/z87_extreme4/Makefile.mk
+++ b/src/mainboard/asrock/z87_extreme4/Makefile.mk
@@ -4,3 +4,5 @@ bootblock-y += bootblock.c
 bootblock-y += gpio.c
 romstage-y += gpio.c
 ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads
+ramstage-y += nuvoton.c
+smm-y += nuvoton.c
diff --git a/src/mainboard/asrock/z87_extreme4/mainboard.c b/src/mainboard/asrock/z87_extreme4/mainboard.c
index 1e62d65d2e..8e30e3c61c 100644
--- a/src/mainboard/asrock/z87_extreme4/mainboard.c
+++ b/src/mainboard/asrock/z87_extreme4/mainboard.c
@@ -10,24 +10,6 @@
 #include <southbridge/intel/lynxpoint/pch.h>
 
 #define GPIO1_DEV PNP_DEV(0x2e, NCT6776_WDT1_GPIO01A_V)
-#define NUVOTON_ENTRY_KEY 0x87
-#define NUVOTON_EXIT_KEY 0xAA
-
-/* Enable configuration: pass entry key '0x87' into index port dev
- * two times. */
-void nuvoton_pnp_enter_conf_state(pnp_devfn_t dev)
-{
-	u16 port = dev >> 8;
-	outb(NUVOTON_ENTRY_KEY, port);
-	outb(NUVOTON_ENTRY_KEY, port);
-}
-
-/* Disable configuration: pass exit key '0xAA' into index port dev. */
-void nuvoton_pnp_exit_conf_state(pnp_devfn_t dev)
-{
-	u16 port = dev >> 8;
-	outb(NUVOTON_EXIT_KEY, port);
-}
 
 static void turn_off_leds(void *unused)
 {
diff --git a/src/mainboard/asrock/z87_extreme4/nuvoton.c b/src/mainboard/asrock/z87_extreme4/nuvoton.c
new file mode 100644
index 0000000000..56453329cb
--- /dev/null
+++ b/src/mainboard/asrock/z87_extreme4/nuvoton.c
@@ -0,0 +1,24 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <device/pnp_ops.h>
+#include <superio/nuvoton/common/nuvoton.h>
+#include <superio/nuvoton/nct6776/nct6776.h>
+
+#define NUVOTON_ENTRY_KEY 0x87
+#define NUVOTON_EXIT_KEY 0xAA
+
+/* Enable configuration: pass entry key '0x87' into index port dev
+ * two times. */
+void nuvoton_pnp_enter_conf_state(pnp_devfn_t dev)
+{
+	u16 port = dev >> 8;
+	outb(NUVOTON_ENTRY_KEY, port);
+	outb(NUVOTON_ENTRY_KEY, port);
+}
+
+/* Disable configuration: pass exit key '0xAA' into index port dev. */
+void nuvoton_pnp_exit_conf_state(pnp_devfn_t dev)
+{
+	u16 port = dev >> 8;
+	outb(NUVOTON_EXIT_KEY, port);
+}
diff --git a/src/mainboard/asrock/z87_extreme4/smihandler.c b/src/mainboard/asrock/z87_extreme4/smihandler.c
index d6ebcef9a0..462316a692 100644
--- a/src/mainboard/asrock/z87_extreme4/smihandler.c
+++ b/src/mainboard/asrock/z87_extreme4/smihandler.c
@@ -7,24 +7,6 @@
 #include <superio/nuvoton/nct6776/nct6776.h>
 
 #define GPIO1_DEV PNP_DEV(0x2e, NCT6776_WDT1_GPIO01A_V)
-#define NUVOTON_ENTRY_KEY 0x87
-#define NUVOTON_EXIT_KEY 0xAA
-
-/* Enable configuration: pass entry key '0x87' into index port dev
- * two times. */
-void nuvoton_pnp_enter_conf_state(pnp_devfn_t dev)
-{
-	u16 port = dev >> 8;
-	outb(NUVOTON_ENTRY_KEY, port);
-	outb(NUVOTON_ENTRY_KEY, port);
-}
-
-/* Disable configuration: pass exit key '0xAA' into index port dev. */
-void nuvoton_pnp_exit_conf_state(pnp_devfn_t dev)
-{
-	u16 port = dev >> 8;
-	outb(NUVOTON_EXIT_KEY, port);
-}
 
 void mainboard_smi_sleep(u8 slp_typ)
 {

From 573c37a5182290e5ea3c4f8a6b1b8c855cfe509f Mon Sep 17 00:00:00 2001
From: Keith Hui <buurin@gmail.com>
Date: Sun, 28 Dec 2025 21:40:13 -0500
Subject: [PATCH 2955/3886] sio/nuvoton/common: Refactor
 nuvoton_pnp_*_config_state()

Move the pair of non-ramstage Nuvoton SIO PNP config mode entry/exit
functions from early_serial.c into nuvoton.h as inline functions for
both pre-RAM and SMM code use. Availability is limited to
__SIMPLE_DEVICE__ environments, or if this symbol is defined such as
when mainboards specifically request it.

Cuts outdated comment from early_serial.c and transplant its key parts
to nuvoton.h.

Remove the temporarily refactored local copies from
mb/asrock/{z87_extreme4,fatal1ty_z87_professional}.

Build tested on these two Asrock boards and asus/p8x7x-series.

Change-Id: I0238f006dd86742f937e9dcd6134ed7be566677c
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90657
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
---
 .../fatal1ty_z87_professional/Makefile.mk     |  2 --
 .../fatal1ty_z87_professional/nuvoton.c       | 24 -------------
 src/mainboard/asrock/z87_extreme4/Makefile.mk |  2 --
 src/mainboard/asrock/z87_extreme4/nuvoton.c   | 24 -------------
 src/superio/nuvoton/common/early_serial.c     | 34 -------------------
 src/superio/nuvoton/common/nuvoton.h          | 28 +++++++++++++--
 6 files changed, 26 insertions(+), 88 deletions(-)
 delete mode 100644 src/mainboard/asrock/fatal1ty_z87_professional/nuvoton.c
 delete mode 100644 src/mainboard/asrock/z87_extreme4/nuvoton.c

diff --git a/src/mainboard/asrock/fatal1ty_z87_professional/Makefile.mk b/src/mainboard/asrock/fatal1ty_z87_professional/Makefile.mk
index de5aa51b34..93f729d787 100644
--- a/src/mainboard/asrock/fatal1ty_z87_professional/Makefile.mk
+++ b/src/mainboard/asrock/fatal1ty_z87_professional/Makefile.mk
@@ -4,5 +4,3 @@ bootblock-y += bootblock.c
 bootblock-y += gpio.c
 romstage-y += gpio.c
 ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads
-smm-y += nuvoton.c
-ramstage-y += nuvoton.c
diff --git a/src/mainboard/asrock/fatal1ty_z87_professional/nuvoton.c b/src/mainboard/asrock/fatal1ty_z87_professional/nuvoton.c
deleted file mode 100644
index 56453329cb..0000000000
--- a/src/mainboard/asrock/fatal1ty_z87_professional/nuvoton.c
+++ /dev/null
@@ -1,24 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <device/pnp_ops.h>
-#include <superio/nuvoton/common/nuvoton.h>
-#include <superio/nuvoton/nct6776/nct6776.h>
-
-#define NUVOTON_ENTRY_KEY 0x87
-#define NUVOTON_EXIT_KEY 0xAA
-
-/* Enable configuration: pass entry key '0x87' into index port dev
- * two times. */
-void nuvoton_pnp_enter_conf_state(pnp_devfn_t dev)
-{
-	u16 port = dev >> 8;
-	outb(NUVOTON_ENTRY_KEY, port);
-	outb(NUVOTON_ENTRY_KEY, port);
-}
-
-/* Disable configuration: pass exit key '0xAA' into index port dev. */
-void nuvoton_pnp_exit_conf_state(pnp_devfn_t dev)
-{
-	u16 port = dev >> 8;
-	outb(NUVOTON_EXIT_KEY, port);
-}
diff --git a/src/mainboard/asrock/z87_extreme4/Makefile.mk b/src/mainboard/asrock/z87_extreme4/Makefile.mk
index 58368c333e..c3cf55d397 100644
--- a/src/mainboard/asrock/z87_extreme4/Makefile.mk
+++ b/src/mainboard/asrock/z87_extreme4/Makefile.mk
@@ -4,5 +4,3 @@ bootblock-y += bootblock.c
 bootblock-y += gpio.c
 romstage-y += gpio.c
 ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads
-ramstage-y += nuvoton.c
-smm-y += nuvoton.c
diff --git a/src/mainboard/asrock/z87_extreme4/nuvoton.c b/src/mainboard/asrock/z87_extreme4/nuvoton.c
deleted file mode 100644
index 56453329cb..0000000000
--- a/src/mainboard/asrock/z87_extreme4/nuvoton.c
+++ /dev/null
@@ -1,24 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <device/pnp_ops.h>
-#include <superio/nuvoton/common/nuvoton.h>
-#include <superio/nuvoton/nct6776/nct6776.h>
-
-#define NUVOTON_ENTRY_KEY 0x87
-#define NUVOTON_EXIT_KEY 0xAA
-
-/* Enable configuration: pass entry key '0x87' into index port dev
- * two times. */
-void nuvoton_pnp_enter_conf_state(pnp_devfn_t dev)
-{
-	u16 port = dev >> 8;
-	outb(NUVOTON_ENTRY_KEY, port);
-	outb(NUVOTON_ENTRY_KEY, port);
-}
-
-/* Disable configuration: pass exit key '0xAA' into index port dev. */
-void nuvoton_pnp_exit_conf_state(pnp_devfn_t dev)
-{
-	u16 port = dev >> 8;
-	outb(NUVOTON_EXIT_KEY, port);
-}
diff --git a/src/superio/nuvoton/common/early_serial.c b/src/superio/nuvoton/common/early_serial.c
index f86e7a27d0..f0162a8f9d 100644
--- a/src/superio/nuvoton/common/early_serial.c
+++ b/src/superio/nuvoton/common/early_serial.c
@@ -2,21 +2,6 @@
 
 /*
  * A generic romstage (pre-ram) driver for Nuvoton variant Super I/O chips.
- *
- * The following is derived directly from the vendor Nuvoton's data-sheets:
- *
- * To toggle between `configuration mode` and `normal operation mode` as to
- * manipulate the various LDN's in Nuvoton Super I/O's we are required to
- * pass magic numbers `passwords keys`.
- *
- *  NUVOTON_ENTRY_KEY :=  enable  configuration : 0x87
- *  NUVOTON_EXIT_KEY  :=  disable configuration : 0xAA
- *
- * To modify a LDN's configuration register, we use the index port to select
- * the index of the LDN and then write to the data port to alter the
- * parameters. A default index, data port pair is 0x4E, 0x4F respectively, a
- * user modified pair is 0x2E, 0x2F respectively.
- *
  */
 
 #include <arch/io.h>
@@ -25,25 +10,6 @@
 #include <stdint.h>
 #include "nuvoton.h"
 
-#define NUVOTON_ENTRY_KEY 0x87
-#define NUVOTON_EXIT_KEY 0xAA
-
-/* Enable configuration: pass entry key '0x87' into index port dev
- * two times. */
-void nuvoton_pnp_enter_conf_state(pnp_devfn_t dev)
-{
-	u16 port = dev >> 8;
-	outb(NUVOTON_ENTRY_KEY, port);
-	outb(NUVOTON_ENTRY_KEY, port);
-}
-
-/* Disable configuration: pass exit key '0xAA' into index port dev. */
-void nuvoton_pnp_exit_conf_state(pnp_devfn_t dev)
-{
-	u16 port = dev >> 8;
-	outb(NUVOTON_EXIT_KEY, port);
-}
-
 /* Bring up early serial debugging output before the RAM is initialized. */
 void nuvoton_enable_serial(pnp_devfn_t dev, u16 iobase)
 {
diff --git a/src/superio/nuvoton/common/nuvoton.h b/src/superio/nuvoton/common/nuvoton.h
index 0243c69b3e..77eafeb240 100644
--- a/src/superio/nuvoton/common/nuvoton.h
+++ b/src/superio/nuvoton/common/nuvoton.h
@@ -7,8 +7,32 @@
 #include <device/pnp_type.h>
 #include <stdint.h>
 
-void nuvoton_pnp_enter_conf_state(pnp_devfn_t dev);
-void nuvoton_pnp_exit_conf_state(pnp_devfn_t dev);
+#if ENV_PNP_SIMPLE_DEVICE
+#include <device/pnp_ops.h>
+
+/*
+ * To toggle between `configuration mode` and `normal operation mode` as to
+ * manipulate the various LDN's in Nuvoton Super I/O's we are required to
+ * pass magic numbers `passwords keys`.
+ */
+#define NUVOTON_ENTRY_KEY 0x87
+#define NUVOTON_EXIT_KEY 0xAA
+
+static __always_inline void nuvoton_pnp_enter_conf_state(pnp_devfn_t dev)
+{
+	u16 port = dev >> 8;
+	outb(NUVOTON_ENTRY_KEY, port);
+	outb(NUVOTON_ENTRY_KEY, port);
+}
+
+static __always_inline void nuvoton_pnp_exit_conf_state(pnp_devfn_t dev)
+{
+	u16 port = dev >> 8;
+	outb(NUVOTON_EXIT_KEY, port);
+}
+
+#endif /* SIMPLE_DEVICE */
+
 void nuvoton_enable_serial(pnp_devfn_t dev, u16 iobase);
 #endif
 

From 273e84976bdad6ac60682746e7069857019d1b6a Mon Sep 17 00:00:00 2001
From: Keith Hui <buurin@gmail.com>
Date: Tue, 28 Jan 2025 10:11:40 -0500
Subject: [PATCH 2956/3886] mb/asus/p8z77-v: Apply vendor PCH interrupt mapping

Got this information from Bill Xie while troubleshooting CB:85413.
Apply the differences from vendor to coreboot.

Change-Id: I56f4314eca101cdfcac12594115d373472d1e1db
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86191
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Bill XIE <persmule@hardenedlinux.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 .../p8x7x-series/variants/p8z77-v/early_init.c   | 16 ++++++++++++++++
 1 file changed, 16 insertions(+)

diff --git a/src/mainboard/asus/p8x7x-series/variants/p8z77-v/early_init.c b/src/mainboard/asus/p8x7x-series/variants/p8z77-v/early_init.c
index c2285a7254..e2ab6e0d01 100644
--- a/src/mainboard/asus/p8x7x-series/variants/p8z77-v/early_init.c
+++ b/src/mainboard/asus/p8x7x-series/variants/p8z77-v/early_init.c
@@ -2,6 +2,7 @@
 
 #include <bootblock_common.h>
 #include <device/pnp_ops.h>
+#include <southbridge/intel/bd82x6x/pch.h>
 #include <superio/nuvoton/common/nuvoton.h>
 #include <superio/nuvoton/nct6779d/nct6779d.h>
 
@@ -9,6 +10,21 @@
 #define SERIAL_DEV PNP_DEV(CONFIG_SUPERIO_NUVOTON_PNP_BASE, NCT6779D_SP1)
 #define ACPI_DEV   PNP_DEV(CONFIG_SUPERIO_NUVOTON_PNP_BASE, NCT6779D_ACPI)
 
+void mainboard_late_rcba_config(void)
+{
+	RCBA32(D31IP) = (INTC << D31IP_TTIP) | (INTB << D31IP_SIP2) |
+			(INTC << D31IP_SMIP) | (INTB << D31IP_SIP);
+	RCBA32(D22IP) = (INTB << D22IP_KTIP)   | (INTC << D22IP_IDERIP) |
+			(INTB << D22IP_MEI2IP) | (INTA << D22IP_MEI1IP);
+
+	DIR_ROUTE(D31IR, PIRQA, PIRQC, PIRQD, PIRQA);
+	DIR_ROUTE(D29IR, PIRQH, PIRQD, PIRQA, PIRQC);
+	DIR_ROUTE(D27IR, PIRQG, PIRQB, PIRQC, PIRQD);
+	DIR_ROUTE(D26IR, PIRQA, PIRQF, PIRQC, PIRQD);
+	DIR_ROUTE(D25IR, PIRQE, PIRQF, PIRQG, PIRQH);
+	DIR_ROUTE(D22IR, PIRQA, PIRQD, PIRQC, PIRQB);
+}
+
 void bootblock_mainboard_early_init(void)
 {
 	nuvoton_pnp_enter_conf_state(GLOBAL_DEV);

From 69668852903b97ef053164de27814804e59a0634 Mon Sep 17 00:00:00 2001
From: Yang Wu <wuyang5@huaqin.corp-partner.google.com>
Date: Wed, 31 Dec 2025 21:13:30 +0800
Subject: [PATCH 2957/3886] mb/google/skywalker: Extend MIPI panel delay to
 meet T3 timing

Measured on Padme, the T3 (AVEE-to-RESET) timing in the current MIPI
panel power-on sequence is only ~120us, which is significantly shorter
than the panel specification requirement (>=3ms). This may cause panel
initialization instability due to RESET being asserted too early after
AVEE is enabled.

Increase the delay between AVEE enable and panel reset from 1ms to 5ms
to satisfy the panel T3 (AVEE-to-RESET) timing requirement.

IL79900A Power on off sequence V1.pdf

BUG=b:451746079
TEST=Boot Padme and confirm panel power-on timing is correct.
BRANCH=skywalker

Change-Id: Ided93c34f7c6695a2928c23eea679f32a0ee9a17
Signed-off-by: Yang Wu <wuyang5@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90664
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
---
 src/mainboard/google/skywalker/panel.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/mainboard/google/skywalker/panel.c b/src/mainboard/google/skywalker/panel.c
index 32d684217e..5856cf4044 100644
--- a/src/mainboard/google/skywalker/panel.c
+++ b/src/mainboard/google/skywalker/panel.c
@@ -60,7 +60,7 @@ void mipi_panel_power_on(void)
 		mdelay(10);
 	}
 	gpio_output(GPIO_EN_PP3300_EDP_X, 0);
-	mdelay(1);
+	mdelay(5);
 	gpio_output(GPIO_EN_PP3300_EDP_X, 1);
 	mdelay(1);
 	gpio_output(GPIO_TCHSCR_RST_1V8_L, 0);

From 6f394ce50daf6daf879ac8d1134668d809aaf752 Mon Sep 17 00:00:00 2001
From: Yidi Lin <yidilin@google.com>
Date: Sat, 3 Jan 2026 11:07:15 +0800
Subject: [PATCH 2958/3886] coreboot_tables: Update CB_MEM_TAG and LB_MEM_TAG
 values to 17

Update the values of CB_MEM_TAG and LB_MEM_TAG from 7 to 17. This change
is necessary to avoid conflicts with the ACPI System Address Map
Interfaces specification.

Change-Id: I802cd724b8f330a9f814fb952ab824cfc23c0e67
Signed-off-by: Yidi Lin <yidilin@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90676
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 payloads/libpayload/include/coreboot_tables.h     | 2 +-
 src/commonlib/include/commonlib/coreboot_tables.h | 8 ++++++--
 2 files changed, 7 insertions(+), 3 deletions(-)

diff --git a/payloads/libpayload/include/coreboot_tables.h b/payloads/libpayload/include/coreboot_tables.h
index 89b0dbc0a4..01d86c272c 100644
--- a/payloads/libpayload/include/coreboot_tables.h
+++ b/payloads/libpayload/include/coreboot_tables.h
@@ -121,8 +121,8 @@ struct cb_memory_range {
 #define CB_MEM_NVS          4
 #define CB_MEM_UNUSABLE     5
 #define CB_MEM_VENDOR_RSVD  6
-#define CB_MEM_TAG          7
 #define CB_MEM_TABLE       16
+#define CB_MEM_TAG         17
 
 struct cb_memory {
 	u32 tag;
diff --git a/src/commonlib/include/commonlib/coreboot_tables.h b/src/commonlib/include/commonlib/coreboot_tables.h
index 251e2c4491..817ca0e4f2 100644
--- a/src/commonlib/include/commonlib/coreboot_tables.h
+++ b/src/commonlib/include/commonlib/coreboot_tables.h
@@ -143,8 +143,12 @@ struct lb_memory_range {
 #define LB_MEM_NVS		 4	/* ACPI NVS Memory */
 #define LB_MEM_UNUSABLE		 5	/* Unusable address space */
 #define LB_MEM_VENDOR_RSVD	 6	/* Vendor Reserved */
-#define LB_MEM_TAG		 7	/* Armv9 tag storage for MTE */
-#define LB_MEM_TABLE		16    /* Ram configuration tables are kept in */
+/*
+ * The memory type [1 ... 16) needs to match
+ * https://uefi.org/htmlspecs/ACPI_Spec_6_4_html/15_System_Address_Map_Interfaces/Sys_Address_Map_Interfaces.html
+ */
+#define LB_MEM_TABLE		16	/* Ram configuration tables are kept in */
+#define LB_MEM_TAG		17	/* Armv9 tag storage for MTE */
 #define LB_MEM_SOFT_RESERVED	0xefffffff /* Specific purpose memory */
 };
 

From eb814f3b12f791eb36a80350f79ee9a1fabfa960 Mon Sep 17 00:00:00 2001
From: Yidi Lin <yidilin@google.com>
Date: Sat, 3 Jan 2026 11:28:37 +0800
Subject: [PATCH 2959/3886] lib/bootmem: Remove forward declaration of
 bootmem_range_string

This commit removes the forward declaration of the static function
`bootmem_range_string` by reordering the definition of
`bootmem_range_string` and the `type_strings` array.

Change-Id: I533660cd06f64011b861656b729eadee07803bf0
Signed-off-by: Yidi Lin <yidilin@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90677
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
---
 src/lib/bootmem.c | 66 +++++++++++++++++++++++------------------------
 1 file changed, 32 insertions(+), 34 deletions(-)

diff --git a/src/lib/bootmem.c b/src/lib/bootmem.c
index dbd8450f06..416f1287c6 100644
--- a/src/lib/bootmem.c
+++ b/src/lib/bootmem.c
@@ -14,7 +14,38 @@ static int table_written;
 static struct memranges bootmem;
 static struct memranges bootmem_os;
 
-static const char *bootmem_range_string(const enum bootmem_type tag);
+struct range_strings {
+	enum bootmem_type tag;
+	const char *str;
+};
+
+static const struct range_strings type_strings[] = {
+	{ BM_MEM_RAM, "RAM" },
+	{ BM_MEM_RESERVED, "RESERVED" },
+	{ BM_MEM_ACPI, "ACPI" },
+	{ BM_MEM_NVS, "NVS" },
+	{ BM_MEM_UNUSABLE, "UNUSABLE" },
+	{ BM_MEM_VENDOR_RSVD, "VENDOR RESERVED" },
+	{ BM_MEM_BL31, "BL31" },
+	{ BM_MEM_OPENSBI, "OPENSBI" },
+	{ BM_MEM_TABLE, "CONFIGURATION TABLES" },
+	{ BM_MEM_SOFT_RESERVED, "SOFT RESERVED" },
+	{ BM_MEM_RAMSTAGE, "RAMSTAGE" },
+	{ BM_MEM_PAYLOAD, "PAYLOAD" },
+	{ BM_MEM_TAG, "TAG STORAGE" },
+};
+
+static const char *bootmem_range_string(const enum bootmem_type tag)
+{
+	int i;
+
+	for (i = 0; i < ARRAY_SIZE(type_strings); i++) {
+		if (type_strings[i].tag == tag)
+			return type_strings[i].str;
+	}
+
+	return "UNKNOWN!";
+}
 
 static int bootmem_is_initialized(void)
 {
@@ -150,39 +181,6 @@ void bootmem_write_memory_table(struct lb_memory *mem)
 	table_written = 1;
 }
 
-struct range_strings {
-	enum bootmem_type tag;
-	const char *str;
-};
-
-static const struct range_strings type_strings[] = {
-	{ BM_MEM_RAM, "RAM" },
-	{ BM_MEM_RESERVED, "RESERVED" },
-	{ BM_MEM_ACPI, "ACPI" },
-	{ BM_MEM_NVS, "NVS" },
-	{ BM_MEM_UNUSABLE, "UNUSABLE" },
-	{ BM_MEM_VENDOR_RSVD, "VENDOR RESERVED" },
-	{ BM_MEM_BL31, "BL31" },
-	{ BM_MEM_OPENSBI, "OPENSBI" },
-	{ BM_MEM_TABLE, "CONFIGURATION TABLES" },
-	{ BM_MEM_SOFT_RESERVED, "SOFT RESERVED" },
-	{ BM_MEM_RAMSTAGE, "RAMSTAGE" },
-	{ BM_MEM_PAYLOAD, "PAYLOAD" },
-	{ BM_MEM_TAG, "TAG STORAGE" },
-};
-
-static const char *bootmem_range_string(const enum bootmem_type tag)
-{
-	int i;
-
-	for (i = 0; i < ARRAY_SIZE(type_strings); i++) {
-		if (type_strings[i].tag == tag)
-			return type_strings[i].str;
-	}
-
-	return "UNKNOWN!";
-}
-
 void bootmem_dump_ranges(void)
 {
 	int i;

From 999dd8905ad3f3889438a3784e3fc03e791ac2d5 Mon Sep 17 00:00:00 2001
From: Yidi Lin <yidilin@google.com>
Date: Sat, 3 Jan 2026 11:33:45 +0800
Subject: [PATCH 2960/3886] lib/bootmem: Replace conditional return with assert
 in bootmem_add_range_from

Promote the condition where new_tag equals from_tag from a runtime error
to an assertion, indicating it as a critical programming error that
should not occur.

Change-Id: I1fe93b7ee0593d27f70ab3702ad4feae85857ea3
Signed-off-by: Yidi Lin <yidilin@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90678
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/lib/bootmem.c | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/src/lib/bootmem.c b/src/lib/bootmem.c
index 416f1287c6..b6be5820d2 100644
--- a/src/lib/bootmem.c
+++ b/src/lib/bootmem.c
@@ -144,8 +144,7 @@ void bootmem_add_range(uint64_t start, uint64_t size,
 int bootmem_add_range_from(uint64_t start, uint64_t size, const enum bootmem_type new_tag,
 			   const enum bootmem_type from_tag)
 {
-	if (new_tag == from_tag)
-		return -1;
+	assert(new_tag != from_tag);
 
 	if (!bootmem_region_targets_type(start, size, from_tag)) {
 		printk(BIOS_ERR, "%s: Failed to add the range [%#llx, %#llx)"

From dc162f84bec26b0022b91a744ca065881820fdd4 Mon Sep 17 00:00:00 2001
From: Swathi Tamilselvan <tswathi@qualcomm.corp-partner.google.com>
Date: Wed, 10 Dec 2025 16:31:35 +0530
Subject: [PATCH 2961/3886] soc/qualcomm/common: Add RPMh driver support
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Add RPMh driver support, introducing the core driver that provides
an interface to the RPMh protocol for managing ARC/VRM/BCM type
resource requests. This includes basic TCS (Trigger Command Sets)
handling and helper functions for sending RPMh requests.

RPMh (Resource Power Manager – hardware) is a protocol that enables
processors (e.g., APSS, LPASS) to send power-related commands to the
RPMh hardware block. Dynamic management of power and clocks for shared
resources is handled either directly by hardware or by RPM.

Key features include:
- Core infrastructure for submitting TCS (Trigger Command Sets)
commands to the RPMh.
- Regulator driver using RPMh for LDOs and SMPS control.
- BCM (Bus Clock Manager) voting for clock resources.

Test=Create an image.serial.bin and ensure it boots on X1P42100.

Change-Id: I1f85459c68d0256e15765b0716856dc928080df9
Signed-off-by: Swathi Tamilselvan <tswathi@qualcomm.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90466
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
---
 src/soc/qualcomm/common/include/soc/rpmh.h    |  25 +
 .../qualcomm/common/include/soc/rpmh_bcm.h    |  17 +
 .../common/include/soc/rpmh_internal.h        | 220 ++++++++
 .../common/include/soc/rpmh_regulator.h       | 220 ++++++++
 .../qualcomm/common/include/soc/rpmh_rsc.h    |  87 +++
 src/soc/qualcomm/common/include/soc/tcs.h     |  72 +++
 src/soc/qualcomm/common/rpmh.c                | 408 ++++++++++++++
 src/soc/qualcomm/common/rpmh_bcm.c            |  59 ++
 src/soc/qualcomm/common/rpmh_regulator.c      | 458 ++++++++++++++++
 src/soc/qualcomm/common/rpmh_rsc.c            | 511 ++++++++++++++++++
 src/soc/qualcomm/x1p42100/Makefile.mk         |   1 +
 11 files changed, 2078 insertions(+)
 create mode 100644 src/soc/qualcomm/common/include/soc/rpmh.h
 create mode 100644 src/soc/qualcomm/common/include/soc/rpmh_bcm.h
 create mode 100644 src/soc/qualcomm/common/include/soc/rpmh_internal.h
 create mode 100644 src/soc/qualcomm/common/include/soc/rpmh_regulator.h
 create mode 100644 src/soc/qualcomm/common/include/soc/rpmh_rsc.h
 create mode 100644 src/soc/qualcomm/common/include/soc/tcs.h
 create mode 100644 src/soc/qualcomm/common/rpmh.c
 create mode 100644 src/soc/qualcomm/common/rpmh_bcm.c
 create mode 100644 src/soc/qualcomm/common/rpmh_regulator.c
 create mode 100644 src/soc/qualcomm/common/rpmh_rsc.c

diff --git a/src/soc/qualcomm/common/include/soc/rpmh.h b/src/soc/qualcomm/common/include/soc/rpmh.h
new file mode 100644
index 0000000000..5b7d76de0b
--- /dev/null
+++ b/src/soc/qualcomm/common/include/soc/rpmh.h
@@ -0,0 +1,25 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef __SOC_QUALCOMM_RPMH_H__
+#define __SOC_QUALCOMM_RPMH_H__
+
+#include <device/device.h>
+#include <soc/tcs.h>
+
+int rpmh_write(enum rpmh_state state, const struct tcs_cmd *cmd, u32 n);
+
+int rpmh_write_async(enum rpmh_state state, const struct tcs_cmd *cmd, u32 n);
+
+int rpmh_write_batch(enum rpmh_state state, const struct tcs_cmd *cmd, u32 *n);
+
+void rpmh_invalidate(void);
+
+int rpmh_write_sleep_and_wake(void);
+
+int rpmh_mode_solver_set(bool enable);
+
+int rpmh_init_fast_path(struct tcs_cmd *cmd, int n);
+
+int rpmh_update_fast_path(struct tcs_cmd *cmd, int n, u32 update_mask);
+
+#endif /* __SOC_QUALCOMM_RPMH_H__ */
diff --git a/src/soc/qualcomm/common/include/soc/rpmh_bcm.h b/src/soc/qualcomm/common/include/soc/rpmh_bcm.h
new file mode 100644
index 0000000000..e359a26fcb
--- /dev/null
+++ b/src/soc/qualcomm/common/include/soc/rpmh_bcm.h
@@ -0,0 +1,17 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef __SOC_QUALCOMM_RPMH_BCM_H__
+#define __SOC_QUALCOMM_RPMH_BCM_H__
+
+#include <types.h>
+
+/**
+ * rpmh_bcm_vote() - Send BCM (Bus Clock Manager) vote to RPMh
+ * @resource_name: BCM resource name
+ * @vote_value: Vote value to send
+ *
+ * Return: 0 on success, negative error code on failure
+ */
+int rpmh_bcm_vote(const char *resource_name, u32 vote_value);
+
+#endif /* __SOC_QUALCOMM_RPMH_BCM_H__ */
diff --git a/src/soc/qualcomm/common/include/soc/rpmh_internal.h b/src/soc/qualcomm/common/include/soc/rpmh_internal.h
new file mode 100644
index 0000000000..23cc3a7456
--- /dev/null
+++ b/src/soc/qualcomm/common/include/soc/rpmh_internal.h
@@ -0,0 +1,220 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef __SOC_QUALCOMM_RPMH_INTERNAL_H__
+#define __SOC_QUALCOMM_RPMH_INTERNAL_H__
+
+#include <types.h>
+#include <soc/tcs.h>
+
+#define MAX_NAME_LENGTH			20
+
+#define USECS_1S		1000000
+#define USECS_100MS		100000
+#define USECS_10MS		10000
+#define USECS_100US		100
+#define USECS_5US		5
+#define LOOP_DELAY_US		1
+#define LOOP_DELAY_10US		10
+
+/* DRV Channel IDs */
+enum {
+	CH0,
+	CH1,
+	MAX_CHANNEL,
+};
+
+#define TCS_TYPE_NR			5
+#define MAX_CMDS_PER_TCS		16
+#define MAX_TCS_PER_TYPE		3
+#define MAX_TCS_NR			(MAX_TCS_PER_TYPE * TCS_TYPE_NR)
+#define MAX_TCS_SLOTS			(MAX_CMDS_PER_TCS * MAX_TCS_PER_TYPE)
+
+#define SOLVER_PRESENT			1
+#define HW_CHANNEL_PRESENT		2
+
+#define	CMD_DB_MAX_RESOURCES		250
+
+/* TCS types */
+enum {
+	ACTIVE_TCS,
+	SLEEP_TCS,
+	WAKE_TCS,
+	CONTROL_TCS,
+	FAST_PATH_TCS,
+};
+
+/* RSC register offsets */
+enum {
+	RSC_DRV_TCS_OFFSET,
+	RSC_DRV_CMD_OFFSET,
+	DRV_SOLVER_CONFIG,
+	DRV_PRNT_CHLD_CONFIG,
+	RSC_DRV_IRQ_ENABLE,
+	RSC_DRV_IRQ_STATUS,
+	RSC_DRV_IRQ_CLEAR,
+	RSC_DRV_CMD_WAIT_FOR_CMPL,
+	RSC_DRV_CONTROL,
+	RSC_DRV_STATUS,
+	RSC_DRV_CMD_ENABLE,
+	RSC_DRV_CMD_MSGID,
+	RSC_DRV_CMD_ADDR,
+	RSC_DRV_CMD_DATA,
+	RSC_DRV_CMD_STATUS,
+	RSC_DRV_CMD_RESP_DATA,
+	RSC_DRV_CHN_TCS_TRIGGER,
+	RSC_DRV_CHN_TCS_COMPLETE,
+	RSC_DRV_CHN_SEQ_BUSY,
+	RSC_DRV_CHN_SEQ_PC,
+	RSC_DRV_CHN_UPDATE,
+	RSC_DRV_CHN_BUSY,
+	RSC_DRV_CHN_EN,
+};
+
+/* DRV TCS Configuration Information Register */
+#define DRV_NUM_TCS_MASK		0x3F
+#define DRV_NUM_TCS_SHIFT		6
+#define DRV_NCPT_MASK			0x1F
+#define DRV_NCPT_SHIFT			27
+
+struct rsc_drv;
+
+/**
+ * struct cache_req: the request object for caching
+ *
+ * @addr: the address of the resource
+ * @sleep_val: the sleep vote
+ * @wake_val: the wake vote
+ */
+struct cache_req {
+	u32 addr;
+	u32 sleep_val;
+	u32 wake_val;
+};
+
+/**
+ * struct tcs_group: group of Trigger Command Sets (TCS) to send state requests
+ * to the controller
+ *
+ * @drv:       The controller.
+ * @type:      Type of the TCS in this group - active, sleep, wake.
+ * @mask:      Mask of the TCSes relative to all the TCSes in the RSC.
+ * @offset:    Start of the TCS group relative to the TCSes in the RSC.
+ * @num_tcs:   Number of TCSes in this type.
+ * @ncpt:      Number of commands in each TCS.
+ * @req:       Requests that are sent from the TCS.
+ * @slots:     Bitmap indicating which slots are occupied.
+ */
+struct tcs_group {
+	struct rsc_drv *drv;
+	int type;
+	u32 mask;
+	u32 offset;
+	int num_tcs;
+	int ncpt;
+	const struct tcs_request *req[MAX_TCS_PER_TYPE];
+	u32 slots[MAX_TCS_SLOTS / 32];
+};
+
+/**
+ * struct rpmh_request: the message to be sent to rpmh-rsc
+ *
+ * @msg: the request
+ * @cmd: the payload that will be part of the @msg
+ */
+struct rpmh_request {
+	struct tcs_request msg;
+	struct tcs_cmd cmd[MAX_RPMH_PAYLOAD];
+};
+
+/**
+ * struct rpmh_ctrlr: our representation of the controller
+ *
+ * @dirty: was the cache updated since flush
+ * @in_solver_mode: Controller is busy in solver mode
+ * @flags: Controller specific flags
+ * @batch_cache: Cache sleep and wake requests sent as batch
+ * @non_batch_cache_idx: Index for non-batch cache
+ * @non_batch_cache: Cache for non-batch requests
+ */
+struct rpmh_ctrlr {
+	bool dirty;
+	bool in_solver_mode;
+	u32 flags;
+	struct rpmh_request batch_cache[RPMH_ACTIVE_ONLY_STATE];
+	u32 non_batch_cache_idx;
+	struct cache_req *non_batch_cache;
+};
+
+/**
+ * struct drv_channel: our representation of the drv channels
+ *
+ * @tcs:                TCS groups
+ * @drv:                DRV containing the channel
+ * @initialized:        Whether channel is initialized
+ */
+struct drv_channel {
+	struct tcs_group tcs[TCS_TYPE_NR];
+	struct rsc_drv *drv;
+	bool initialized;
+};
+
+/**
+ * struct rsc_drv: the Direct Resource Voter (DRV) of the
+ * Resource State Coordinator controller (RSC)
+ *
+ * @name:               Controller identifier
+ * @base:               Start address of the DRV registers in this controller
+ * @tcs_base:           Start address of the TCS registers in this controller
+ * @tcs_distance:       Distance between two TCSes
+ * @id:                 Instance id in the controller (Direct Resource Voter)
+ * @num_tcs:            Number of TCSes in this DRV
+ * @num_channels:       Number of channels in this DRV
+ * @in_solver_mode:     Controller is busy in solver mode
+ * @initialized:        Whether DRV is initialized
+ * @tcs:                TCS groups
+ * @ch:                 DRV channels
+ * @tcs_in_use:         S/W state of the TCS bitmap
+ * @client:             Handle to the DRV's client
+ * @dev:                RSC device
+ * @regs:               Register offsets for RSC controller
+ */
+struct rsc_drv {
+	char name[MAX_NAME_LENGTH];
+	void *base;
+	void *tcs_base;
+	u32 tcs_distance;
+	unsigned int id;
+	int num_tcs;
+	int num_channels;
+	bool in_solver_mode;
+	bool initialized;
+	struct tcs_group tcs[TCS_TYPE_NR];
+	struct drv_channel ch[MAX_CHANNEL];
+	u32 tcs_in_use[(MAX_TCS_NR + 31) / 32];
+	struct rpmh_ctrlr client;
+	struct device *dev;
+	u32 *regs;
+};
+
+extern bool rpmh_standalone;
+
+int rpmh_rsc_send_data(struct rsc_drv *drv, const struct tcs_request *msg, int ch);
+int rpmh_rsc_write_ctrl_data(struct rsc_drv *drv,
+			     const struct tcs_request *msg,
+			     int ch);
+void rpmh_rsc_invalidate(struct rsc_drv *drv, int ch);
+int rpmh_rsc_mode_solver_set(struct rsc_drv *drv, bool enable);
+int rpmh_rsc_get_channel(struct rsc_drv *drv);
+int rpmh_rsc_switch_channel(struct rsc_drv *drv, int ch);
+int rpmh_rsc_drv_enable(struct rsc_drv *drv, bool enable);
+
+int rpmh_flush(struct rpmh_ctrlr *ctrlr, int ch);
+
+int rpmh_rsc_init_fast_path(struct rsc_drv *drv, const struct tcs_request *msg, int ch);
+int rpmh_rsc_update_fast_path(struct rsc_drv *drv,
+			      const struct tcs_request *msg,
+			      u32 update_mask, int ch);
+
+void rpmh_set_rsc_drv(struct rsc_drv *drv);
+
+#endif /* __SOC_QUALCOMM_RPMH_INTERNAL_H__ */
diff --git a/src/soc/qualcomm/common/include/soc/rpmh_regulator.h b/src/soc/qualcomm/common/include/soc/rpmh_regulator.h
new file mode 100644
index 0000000000..310cd4c7ef
--- /dev/null
+++ b/src/soc/qualcomm/common/include/soc/rpmh_regulator.h
@@ -0,0 +1,220 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef __SOC_QUALCOMM_RPMH_REGULATOR_H__
+#define __SOC_QUALCOMM_RPMH_REGULATOR_H__
+
+#include <types.h>
+#include <device/device.h>
+
+#define RPMH_ARC_LEVEL_SIZE             2
+#define RPMH_ARC_MAX_LEVELS             32
+#define RPMH_REGULATOR_LEVEL_OFF        0
+
+/* Min and max limits of VRM resource request parameters */
+#define RPMH_VRM_MIN_UV                 0
+#define RPMH_VRM_MAX_UV                 8191000
+#define RPMH_VRM_STEP_UV                1000
+#define RPMH_VRM_HEADROOM_MIN_UV        0
+#define RPMH_VRM_HEADROOM_MAX_UV        511000
+
+#define RPMH_VRM_MODE_MIN               0
+#define RPMH_VRM_MODE_MAX               7
+
+/* XOB and PBS voting registers are found in the VRM hardware module */
+#define CMD_DB_HW_XOB                   CMD_DB_HW_VRM
+#define CMD_DB_HW_PBS                   CMD_DB_HW_VRM
+
+/* Voltage unknown placeholder */
+#define VOLTAGE_UNKNOWN                 1
+
+/**
+ * enum rpmh_regulator_type - supported RPMh accelerator types
+ * @RPMH_REGULATOR_TYPE_VRM:	RPMh VRM accelerator which supports voting on
+ *				enable, voltage, mode, and headroom voltage of
+ *				LDO, SMPS, VS, and BOB type PMIC regulators.
+ * @RPMH_REGULATOR_TYPE_ARC:	RPMh ARC accelerator which supports voting on
+ *				the CPR managed voltage level of LDO and SMPS
+ *				type PMIC regulators.
+ * @RPMH_REGULATOR_TYPE_XOB:	RPMh XOB accelerator which supports voting on
+ *				the enable state of PMIC regulators.
+ * @RPMH_REGULATOR_TYPE_PBS:	RPMh PBS accelerator which supports voting on
+ *				the enable state of PBS resources.
+ * @RPMH_REGULATOR_TYPE_BCM:	RPMh BCM (Bus Clock Manager) accelerator which
+ *				supports voting on bandwidth and clock frequency
+ *				requirements for interconnect and bus resources.
+ */
+enum rpmh_regulator_type {
+	RPMH_REGULATOR_TYPE_VRM,
+	RPMH_REGULATOR_TYPE_ARC,
+	RPMH_REGULATOR_TYPE_XOB,
+	RPMH_REGULATOR_TYPE_PBS,
+	RPMH_REGULATOR_TYPE_BCM,
+};
+
+/**
+ * enum rpmh_regulator_reg_index - RPMh accelerator register indices
+ * @RPMH_REGULATOR_REG_VRM_VOLTAGE:	VRM voltage voting register index
+ * @RPMH_REGULATOR_REG_ARC_LEVEL:	ARC voltage level voting register index
+ * @RPMH_REGULATOR_REG_PBS_ENABLE:	PBS enable voting register index
+ * @RPMH_REGULATOR_REG_VRM_ENABLE:	VRM enable voltage voting register index
+ * @RPMH_REGULATOR_REG_ARC_PSEUDO_ENABLE: Place-holder for enable aggregation
+ * @RPMH_REGULATOR_REG_XOB_ENABLE:	XOB enable voting register index
+ * @RPMH_REGULATOR_REG_ENABLE:		Common enable index
+ * @RPMH_REGULATOR_REG_VRM_MODE:	VRM regulator mode voting register index
+ * @RPMH_REGULATOR_REG_VRM_HEADROOM:	VRM headroom voltage voting register index
+ * @RPMH_REGULATOR_REG_MAX:		Maximum number of registers
+ */
+enum rpmh_regulator_reg_index {
+	RPMH_REGULATOR_REG_VRM_VOLTAGE		= 0,
+	RPMH_REGULATOR_REG_ARC_LEVEL		= 0,
+	RPMH_REGULATOR_REG_PBS_ENABLE		= 0,
+	RPMH_REGULATOR_REG_VRM_ENABLE		= 1,
+	RPMH_REGULATOR_REG_ARC_PSEUDO_ENABLE	= 1,
+	RPMH_REGULATOR_REG_XOB_ENABLE		= 1,
+	RPMH_REGULATOR_REG_ENABLE		= 1,
+	RPMH_REGULATOR_REG_VRM_MODE		= 2,
+	RPMH_REGULATOR_REG_VRM_HEADROOM		= 3,
+	RPMH_REGULATOR_REG_MAX			= 4,
+};
+
+/**
+ * struct rpmh_regulator_request - internal request structure
+ */
+struct rpmh_regulator_request {
+	u32 reg[RPMH_REGULATOR_REG_MAX];
+	u32 valid;
+};
+
+/**
+ * struct rpmh_vreg - individual rpmh regulator data structure
+ * @resource_name:      Name of rpmh regulator resource
+ * @addr:               Base address of the regulator resource within an RPMh accelerator
+ * @type:               RPMh accelerator type for this regulator resource
+ * @level:              Mapping from ARC resource specific voltage levels to consumer levels
+ * @level_count:        The number of valid entries in the level array
+ * @req_active:         Active set RPMh accelerator register request
+ * @req_sleep:          Sleep set RPMh accelerator register request
+ */
+
+struct rpmh_vreg {
+	const char *resource_name;
+	u32 addr;
+	enum rpmh_regulator_type type;
+	u32 level[RPMH_ARC_MAX_LEVELS];
+	int level_count;
+	struct rpmh_regulator_request req_active;
+	struct rpmh_regulator_request req_sleep;
+};
+
+
+/**
+ * rpmh_regulator_init() - initialize an rpmh regulator
+ * @vreg:		Pointer to the rpmh regulator structure to initialize
+ * @dev:		Device pointer for RPMh communication
+ * @resource_name:	Name of the RPMh resource (e.g., "ldoa1")
+ * @type:		Type of regulator (VRM, ARC, XOB, PBS)
+ *
+ * This function initializes an RPMh regulator by looking up its address
+ * in the command DB and loading any necessary configuration data.
+ *
+ * Return: 0 on success, -1 on failure
+ */
+int rpmh_regulator_init(struct rpmh_vreg *vreg, const char *resource_name,
+			enum rpmh_regulator_type type);
+
+/**
+ * rpmh_regulator_vrm_set_voltage() - set the voltage of a VRM regulator
+ * @vreg:	Pointer to the rpmh regulator
+ * @min_uv:	Minimum voltage in microvolts
+ * @max_uv:	Maximum voltage in microvolts
+ * @set_active:	Set in active state
+ * @set_sleep:	Set in sleep state
+ *
+ * This function sets the voltage for a VRM type regulator. The actual
+ * voltage set will be the minimum value that satisfies min_uv.
+ *
+ * Return: 0 on success, -1 on failure
+ */
+int rpmh_regulator_vrm_set_voltage(struct rpmh_vreg *vreg, int min_uv, int max_uv,
+				   bool set_active, bool set_sleep);
+
+/**
+ * rpmh_regulator_vrm_set_mode() - set the mode of a VRM regulator
+ * @vreg:	Pointer to the rpmh regulator
+ * @mode:	PMIC mode value (use RPMH_REGULATOR_MODE_* defines)
+ * @set_active:	Set in active state
+ * @set_sleep:	Set in sleep state
+ *
+ * This function sets the operating mode for a VRM type regulator.
+ * The mode value should be one of the RPMH_REGULATOR_MODE_PMIC*_* defines
+ * appropriate for the regulator type.
+ *
+ * Return: 0 on success, -1 on failure
+ */
+int rpmh_regulator_vrm_set_mode(struct rpmh_vreg *vreg, u32 mode,
+				bool set_active, bool set_sleep);
+
+/**
+ * rpmh_regulator_enable() - enable a regulator
+ * @vreg:	Pointer to the rpmh regulator
+ * @set_active:	Set in active state
+ * @set_sleep:	Set in sleep state
+ *
+ * This function enables the regulator. Works for VRM, ARC, XOB, and PBS types.
+ *
+ * Return: 0 on success, -1 on failure
+ */
+int rpmh_regulator_enable(struct rpmh_vreg *vreg, bool set_active, bool set_sleep);
+
+/**
+ * rpmh_regulator_disable() - disable a regulator
+ * @vreg:	Pointer to the rpmh regulator
+ * @set_active:	Set in active state
+ * @set_sleep:	Set in sleep state
+ *
+ * This function disables the regulator. Works for VRM, ARC, XOB, and PBS types.
+ *
+ * Return: 0 on success, -1 on failure
+ */
+int rpmh_regulator_disable(struct rpmh_vreg *vreg, bool set_active, bool set_sleep);
+
+/**
+ * rpmh_regulator_arc_set_level() - set the voltage level of an ARC regulator
+ * @vreg:	Pointer to the rpmh regulator
+ * @level:	ARC voltage level (0 to level_count-1)
+ * @set_active:	Set in active state
+ * @set_sleep:	Set in sleep state
+ *
+ * This function sets the voltage level for an ARC type regulator.
+ * The level is an index into the voltage level table loaded from command DB.
+ *
+ * Return: 0 on success, -1 on failure
+ */
+int rpmh_regulator_arc_set_level(struct rpmh_vreg *vreg, u32 level,
+				  bool set_active, bool set_sleep);
+
+/**
+ * rpmh_regulator_arc_get_level() - get the current voltage level of an ARC regulator
+ * @vreg:	Pointer to the rpmh regulator
+ *
+ * This function returns the cached ARC voltage level that was last set.
+ * Note: This returns the requested level, not necessarily the actual hardware level,
+ * as there's no way to read back from RPMh hardware.
+ *
+ * Return: ARC voltage level (0 to level_count-1) on success, -1 on failure
+ */
+int rpmh_regulator_arc_get_level(struct rpmh_vreg *vreg);
+
+/**
+ * rpmh_regulator_arc_get_voltage_level() - get the voltage level value for an ARC level
+ * @vreg:	Pointer to the rpmh regulator
+ * @level:	ARC level index
+ *
+ * This function returns the actual voltage level value (vlvl) that corresponds
+ * to the given ARC hardware level (hlvl).
+ *
+ * Return: voltage level value on success, 0 on failure
+ */
+u32 rpmh_regulator_arc_get_voltage_level(struct rpmh_vreg *vreg, u32 level);
+
+#endif /* __SOC_QUALCOMM_RPMH_REGULATOR_H__ */
diff --git a/src/soc/qualcomm/common/include/soc/rpmh_rsc.h b/src/soc/qualcomm/common/include/soc/rpmh_rsc.h
new file mode 100644
index 0000000000..cfe7d601ae
--- /dev/null
+++ b/src/soc/qualcomm/common/include/soc/rpmh_rsc.h
@@ -0,0 +1,87 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef __SOC_QUALCOMM_RPMH_RSC_H__
+#define __SOC_QUALCOMM_RPMH_RSC_H__
+
+#include <types.h>
+#include <soc/rpmh_internal.h>
+
+u32 rpmh_rsc_reg_offset_ver_2_7[] = {
+	[RSC_DRV_TCS_OFFSET]		= 672,
+	[RSC_DRV_CMD_OFFSET]		= 20,
+	[DRV_SOLVER_CONFIG]		= 0x04,
+	[DRV_PRNT_CHLD_CONFIG]		= 0x0C,
+	[RSC_DRV_IRQ_ENABLE]		= 0x00,
+	[RSC_DRV_IRQ_STATUS]		= 0x04,
+	[RSC_DRV_IRQ_CLEAR]		= 0x08,
+	[RSC_DRV_CMD_WAIT_FOR_CMPL]	= 0x10,
+	[RSC_DRV_CONTROL]		= 0x14,
+	[RSC_DRV_STATUS]		= 0x18,
+	[RSC_DRV_CMD_ENABLE]		= 0x1C,
+	[RSC_DRV_CMD_MSGID]		= 0x30,
+	[RSC_DRV_CMD_ADDR]		= 0x34,
+	[RSC_DRV_CMD_DATA]		= 0x38,
+	[RSC_DRV_CMD_STATUS]		= 0x3C,
+	[RSC_DRV_CMD_RESP_DATA]		= 0x40,
+	[RSC_DRV_CHN_SEQ_BUSY]		= 0x0,
+	[RSC_DRV_CHN_SEQ_PC]		= 0x0,
+	[RSC_DRV_CHN_TCS_TRIGGER]	= 0x0,
+	[RSC_DRV_CHN_TCS_COMPLETE]	= 0x0,
+	[RSC_DRV_CHN_UPDATE]		= 0x0,
+	[RSC_DRV_CHN_BUSY]		= 0x0,
+	[RSC_DRV_CHN_EN]		= 0x0,
+};
+
+u32 rpmh_rsc_reg_offset_ver_3_0[] = {
+	[RSC_DRV_TCS_OFFSET]		= 672,
+	[RSC_DRV_CMD_OFFSET]		= 24,
+	[DRV_SOLVER_CONFIG]		= 0x04,
+	[DRV_PRNT_CHLD_CONFIG]		= 0x0C,
+	[RSC_DRV_IRQ_ENABLE]		= 0x00,
+	[RSC_DRV_IRQ_STATUS]		= 0x04,
+	[RSC_DRV_IRQ_CLEAR]		= 0x08,
+	[RSC_DRV_CMD_WAIT_FOR_CMPL]	= 0x20,
+	[RSC_DRV_CONTROL]		= 0x24,
+	[RSC_DRV_STATUS]		= 0x28,
+	[RSC_DRV_CMD_ENABLE]		= 0x2C,
+	[RSC_DRV_CMD_MSGID]		= 0x34,
+	[RSC_DRV_CMD_ADDR]		= 0x38,
+	[RSC_DRV_CMD_DATA]		= 0x3C,
+	[RSC_DRV_CMD_STATUS]		= 0x40,
+	[RSC_DRV_CMD_RESP_DATA]		= 0x44,
+	[RSC_DRV_CHN_SEQ_BUSY]		= 0x464,
+	[RSC_DRV_CHN_SEQ_PC]		= 0x468,
+	[RSC_DRV_CHN_TCS_TRIGGER]	= 0x490,
+	[RSC_DRV_CHN_TCS_COMPLETE]	= 0x494,
+	[RSC_DRV_CHN_UPDATE]		= 0x498,
+	[RSC_DRV_CHN_BUSY]		= 0x49C,
+	[RSC_DRV_CHN_EN]		= 0x4A0,
+};
+
+u32 rpmh_rsc_reg_offset_ver_3_0_hw_channel[] = {
+	[RSC_DRV_TCS_OFFSET]		= 336,
+	[RSC_DRV_CMD_OFFSET]		= 24,
+	[DRV_SOLVER_CONFIG]		= 0x04,
+	[DRV_PRNT_CHLD_CONFIG]		= 0x0C,
+	[RSC_DRV_IRQ_ENABLE]		= 0x00,
+	[RSC_DRV_IRQ_STATUS]		= 0x04,
+	[RSC_DRV_IRQ_CLEAR]		= 0x08,
+	[RSC_DRV_CMD_WAIT_FOR_CMPL]	= 0x20,
+	[RSC_DRV_CONTROL]		= 0x24,
+	[RSC_DRV_STATUS]		= 0x28,
+	[RSC_DRV_CMD_ENABLE]		= 0x2C,
+	[RSC_DRV_CMD_MSGID]		= 0x34,
+	[RSC_DRV_CMD_ADDR]		= 0x38,
+	[RSC_DRV_CMD_DATA]		= 0x3C,
+	[RSC_DRV_CMD_STATUS]		= 0x40,
+	[RSC_DRV_CMD_RESP_DATA]		= 0x44,
+	[RSC_DRV_CHN_SEQ_BUSY]		= 0x464,
+	[RSC_DRV_CHN_SEQ_PC]		= 0x468,
+	[RSC_DRV_CHN_TCS_TRIGGER]	= 0x490,
+	[RSC_DRV_CHN_TCS_COMPLETE]	= 0x494,
+	[RSC_DRV_CHN_UPDATE]		= 0x498,
+	[RSC_DRV_CHN_BUSY]		= 0x49C,
+	[RSC_DRV_CHN_EN]		= 0x4A0,
+};
+
+#endif /* __SOC_QUALCOMM_RPMH_RSC_H__ */
diff --git a/src/soc/qualcomm/common/include/soc/tcs.h b/src/soc/qualcomm/common/include/soc/tcs.h
new file mode 100644
index 0000000000..260e010862
--- /dev/null
+++ b/src/soc/qualcomm/common/include/soc/tcs.h
@@ -0,0 +1,72 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef __SOC_QUALCOMM_TCS_H__
+#define __SOC_QUALCOMM_TCS_H__
+
+#include <types.h>
+
+#define MAX_RPMH_PAYLOAD	16
+
+/**
+ * rpmh_state: state for the request
+ *
+ * RPMH_SLEEP_STATE:       State of the resource when the processor subsystem
+ *                         is powered down. There is no client using the
+ *                         resource actively.
+ * RPMH_WAKE_ONLY_STATE:   Resume resource state to the value previously
+ *                         requested before the processor was powered down.
+ * RPMH_ACTIVE_ONLY_STATE: Active or AMC mode requests. Resource state
+ *                         is aggregated immediately.
+ */
+enum rpmh_state {
+	RPMH_SLEEP_STATE,
+	RPMH_WAKE_ONLY_STATE,
+	RPMH_ACTIVE_ONLY_STATE,
+};
+
+/**
+ * struct tcs_cmd: an individual request to RPMH.
+ *
+ * @addr: the address of the resource slv_id:18:16 | offset:0:15
+ * @data: the resource state request
+ * @wait: ensure that this command is complete before returning.
+ */
+struct tcs_cmd {
+	u32 addr;
+	u32 data;
+	u32 wait;
+};
+
+/**
+ * struct tcs_request: A set of tcs_cmds sent together in a TCS
+ *
+ * @state:          state for the request.
+ * @wait_for_compl: wait until we get a response from the h/w accelerator
+ * @num_cmds:       the number of @cmds in this request
+ * @cmds:           an array of tcs_cmds
+ */
+struct tcs_request {
+	enum rpmh_state state;
+	u32 wait_for_compl;
+	u32 num_cmds;
+	struct tcs_cmd *cmds;
+};
+
+#define BCM_TCS_CMD_COMMIT_SHFT		30
+#define BCM_TCS_CMD_COMMIT_MASK		0x40000000
+#define BCM_TCS_CMD_VALID_SHFT		29
+#define BCM_TCS_CMD_VALID_MASK		0x20000000
+#define BCM_TCS_CMD_VOTE_X_SHFT		14
+#define BCM_TCS_CMD_VOTE_MASK		0x3fff
+#define BCM_TCS_CMD_VOTE_Y_SHFT		0
+#define BCM_TCS_CMD_VOTE_Y_MASK		0xfffc000
+
+/* Construct a Bus Clock Manager (BCM) specific TCS command */
+#define BCM_TCS_CMD(commit, valid, vote_x, vote_y)               \
+	cpu_to_le32(                                                 \
+		(((uint32_t)(commit) & 0x1) << BCM_TCS_CMD_COMMIT_SHFT) | \
+		(((uint32_t)(valid)  & 0x1) << BCM_TCS_CMD_VALID_SHFT)  | \
+		(((uint32_t)(vote_x) & BCM_TCS_CMD_VOTE_MASK) << BCM_TCS_CMD_VOTE_X_SHFT) | \
+		(((uint32_t)(vote_y) & BCM_TCS_CMD_VOTE_MASK) << BCM_TCS_CMD_VOTE_Y_SHFT)   \
+	)
+#endif /* __SOC_QUALCOMM_TCS_H__ */
diff --git a/src/soc/qualcomm/common/rpmh.c b/src/soc/qualcomm/common/rpmh.c
new file mode 100644
index 0000000000..bd348a07a9
--- /dev/null
+++ b/src/soc/qualcomm/common/rpmh.c
@@ -0,0 +1,408 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <console/console.h>
+#include <delay.h>
+#include <device/device.h>
+#include <string.h>
+#include <soc/rpmh.h>
+#include <soc/cmd_db.h>
+#include <soc/rpmh_internal.h>
+
+#define RPMH_TIMEOUT_MS			10000
+
+#define DEFINE_RPMH_MSG_ONSTACK(s, name)		\
+	struct rpmh_request name = {			\
+		.msg = {				\
+			.state = s,			\
+			.cmds = name.cmd,		\
+			.num_cmds = 0,			\
+			.wait_for_compl = 1,		\
+		},					\
+		.cmd = { { 0 } },			\
+	}
+
+#define ctrlr_to_drv(ctrlr) \
+	((struct rsc_drv *)((char *)(ctrlr) - offsetof(struct rsc_drv, client)))
+
+bool rpmh_standalone;
+
+static struct rsc_drv *g_rsc_drv = NULL;
+
+static struct rpmh_ctrlr *get_rpmh_ctrlr(void)
+{
+	return g_rsc_drv ? &g_rsc_drv->client : NULL;
+}
+
+void rpmh_set_rsc_drv(struct rsc_drv *drv)
+{
+	g_rsc_drv = drv;
+}
+
+static int check_ctrlr_state(struct rpmh_ctrlr *ctrlr, enum rpmh_state state)
+{
+	if (state != RPMH_ACTIVE_ONLY_STATE)
+		return 0;
+
+	if (!(ctrlr->flags & SOLVER_PRESENT))
+		return 0;
+
+	if (ctrlr->in_solver_mode)
+		return -1;
+
+	return 0;
+}
+
+static struct cache_req *get_non_batch_cache_req(struct rpmh_ctrlr *ctrlr, u32 addr)
+{
+	struct cache_req *req = ctrlr->non_batch_cache;
+	unsigned int i;
+
+	if (ctrlr->non_batch_cache_idx >= CMD_DB_MAX_RESOURCES)
+		return NULL;
+
+	for (i = 0; i < ctrlr->non_batch_cache_idx; i++) {
+		req = &ctrlr->non_batch_cache[i];
+		if (req->addr == addr)
+			return req;
+	}
+
+	req = &ctrlr->non_batch_cache[ctrlr->non_batch_cache_idx];
+	req->sleep_val = req->wake_val = UINT_MAX;
+	ctrlr->non_batch_cache_idx++;
+
+	return req;
+}
+
+static struct cache_req *cache_rpm_request(struct rpmh_ctrlr *ctrlr,
+					   enum rpmh_state state,
+					   struct tcs_cmd *cmd)
+{
+	struct cache_req *req;
+	u32 old_sleep_val, old_wake_val;
+
+	req = get_non_batch_cache_req(ctrlr, cmd->addr);
+	if (!req)
+		return NULL;
+
+	req->addr = cmd->addr;
+	old_sleep_val = req->sleep_val;
+	old_wake_val = req->wake_val;
+
+	switch (state) {
+	case RPMH_ACTIVE_ONLY_STATE:
+	case RPMH_WAKE_ONLY_STATE:
+		req->wake_val = cmd->data;
+		break;
+	case RPMH_SLEEP_STATE:
+		req->sleep_val = cmd->data;
+		break;
+	}
+
+	ctrlr->dirty |= (req->sleep_val != old_sleep_val ||
+			 req->wake_val != old_wake_val) &&
+			 req->sleep_val != UINT_MAX &&
+			 req->wake_val != UINT_MAX;
+
+	return req;
+}
+
+static int __rpmh_write(enum rpmh_state state, struct rpmh_request *rpm_msg)
+{
+	struct rpmh_ctrlr *ctrlr = get_rpmh_ctrlr();
+	int ret = -1;
+	struct cache_req *req;
+	int i, ch;
+
+	if (rpmh_standalone)
+		return 0;
+
+	if (!ctrlr)
+		return -1;
+
+	for (i = 0; i < rpm_msg->msg.num_cmds; i++) {
+		req = cache_rpm_request(ctrlr, state, &rpm_msg->msg.cmds[i]);
+		if (!req)
+			return -1;
+	}
+
+	if (state == RPMH_ACTIVE_ONLY_STATE) {
+		ch = rpmh_rsc_get_channel(ctrlr_to_drv(ctrlr));
+		if (ch < 0)
+			return ch;
+
+		ret = rpmh_rsc_send_data(ctrlr_to_drv(ctrlr), &rpm_msg->msg, ch);
+	} else {
+		ret = 0;
+	}
+
+	return ret;
+}
+
+static int __fill_rpmh_msg(struct rpmh_request *req, enum rpmh_state state,
+		const struct tcs_cmd *cmd, u32 num_cmds)
+{
+	if (!cmd || !num_cmds || num_cmds > MAX_RPMH_PAYLOAD)
+		return -1;
+
+	memcpy(req->cmd, cmd, num_cmds * sizeof(*cmd));
+
+	req->msg.state = state;
+	req->msg.cmds = req->cmd;
+	req->msg.num_cmds = num_cmds;
+
+	return 0;
+}
+
+int rpmh_write_async(enum rpmh_state state, const struct tcs_cmd *cmd, u32 n)
+{
+	DEFINE_RPMH_MSG_ONSTACK(state, rpm_msg);
+	struct rpmh_ctrlr *ctrlr = get_rpmh_ctrlr();
+	int ret;
+
+	if (rpmh_standalone)
+		return 0;
+
+	if (!ctrlr)
+		return -1;
+
+	rpm_msg.msg.wait_for_compl = 0;
+	ret = check_ctrlr_state(ctrlr, state);
+	if (ret)
+		return ret;
+
+	ret = __fill_rpmh_msg(&rpm_msg, state, cmd, n);
+	if (ret)
+		return ret;
+
+	return __rpmh_write(state, &rpm_msg);
+}
+
+int rpmh_write(enum rpmh_state state, const struct tcs_cmd *cmd, u32 n)
+{
+	DEFINE_RPMH_MSG_ONSTACK(state, rpm_msg);
+	struct rpmh_ctrlr *ctrlr = get_rpmh_ctrlr();
+	int ret;
+
+	if (rpmh_standalone)
+		return 0;
+
+	if (!ctrlr)
+		return -1;
+
+	ret = check_ctrlr_state(ctrlr, state);
+	if (ret)
+		return ret;
+
+	ret = __fill_rpmh_msg(&rpm_msg, state, cmd, n);
+	if (ret)
+		return ret;
+
+	ret = __rpmh_write(state, &rpm_msg);
+
+	return ret;
+}
+
+static int flush_batch(struct rpmh_ctrlr *ctrlr, int ch)
+{
+	int ret;
+
+	/* Send Sleep/Wake requests to the controller */
+	ret = rpmh_rsc_write_ctrl_data(ctrlr_to_drv(ctrlr),
+				       &ctrlr->batch_cache[RPMH_SLEEP_STATE].msg, ch);
+	if (ret)
+		return ret;
+
+	return rpmh_rsc_write_ctrl_data(ctrlr_to_drv(ctrlr),
+					&ctrlr->batch_cache[RPMH_WAKE_ONLY_STATE].msg, ch);
+}
+
+int rpmh_write_batch(enum rpmh_state state, const struct tcs_cmd *cmd, u32 *n)
+{
+	DEFINE_RPMH_MSG_ONSTACK(state, rpm_msg);
+	struct rpmh_ctrlr *ctrlr = get_rpmh_ctrlr();
+	int ret, ch;
+
+	if (rpmh_standalone)
+		return 0;
+
+	if (!ctrlr)
+		return -1;
+
+	ret = check_ctrlr_state(ctrlr, state);
+	if (ret)
+		return ret;
+
+	if (state == RPMH_ACTIVE_ONLY_STATE) {
+		ret = __fill_rpmh_msg(&rpm_msg, state, cmd, *n);
+		if (ret)
+			return ret;
+	} else {
+		memset(&ctrlr->batch_cache[state], 0, sizeof(struct rpmh_request));
+		ret = __fill_rpmh_msg(&ctrlr->batch_cache[state], state, cmd, *n);
+		ctrlr->dirty = 1;
+		return ret;
+	}
+
+	ch = rpmh_rsc_get_channel(ctrlr_to_drv(ctrlr));
+	if (ch < 0)
+		return ch;
+
+	ret = rpmh_rsc_send_data(ctrlr_to_drv(ctrlr), &rpm_msg.msg, ch);
+	if (ret) {
+		printk(BIOS_ERR, "RPMH: Error sending message addr=%#x\n",
+		       rpm_msg.msg.cmds[0].addr);
+		return ret;
+	}
+
+	return 0;
+}
+
+static int is_req_valid(struct cache_req *req)
+{
+	return (req->sleep_val != UINT_MAX &&
+		req->wake_val != UINT_MAX &&
+		req->sleep_val != req->wake_val);
+}
+
+static int send_single(struct rpmh_ctrlr *ctrlr, enum rpmh_state state,
+		       u32 addr, u32 data, int ch)
+{
+	DEFINE_RPMH_MSG_ONSTACK(state, rpm_msg);
+
+	/* Wake sets are always complete and sleep sets are not */
+	rpm_msg.msg.wait_for_compl = (state == RPMH_WAKE_ONLY_STATE);
+	rpm_msg.cmd[0].addr = addr;
+	rpm_msg.cmd[0].data = data;
+	rpm_msg.msg.num_cmds = 1;
+
+	return rpmh_rsc_write_ctrl_data(ctrlr_to_drv(ctrlr), &rpm_msg.msg, ch);
+}
+
+int rpmh_flush(struct rpmh_ctrlr *ctrlr, int ch)
+{
+	struct cache_req *p;
+	int ret = 0, i;
+
+	if (!ctrlr->dirty) {
+		printk(BIOS_DEBUG, "RPMH: Skipping flush, TCS has latest data\n");
+		return 0;
+	}
+
+	/* Invalidate the TCSes first to avoid stale data */
+	rpmh_rsc_invalidate(ctrlr_to_drv(ctrlr), ch);
+
+	/* First flush the cached batch requests */
+	ret = flush_batch(ctrlr, ch);
+	if (ret)
+		return ret;
+
+	for (i = 0; i < ctrlr->non_batch_cache_idx; i++) {
+		p = &ctrlr->non_batch_cache[i];
+		if (!is_req_valid(p)) {
+			printk(BIOS_DEBUG, "RPMH: skipping req: a:%#x s:%#x w:%#x\n",
+				 p->addr, p->sleep_val, p->wake_val);
+			continue;
+		}
+		ret = send_single(ctrlr, RPMH_SLEEP_STATE, p->addr,
+				  p->sleep_val, ch);
+		if (ret)
+			return ret;
+		ret = send_single(ctrlr, RPMH_WAKE_ONLY_STATE, p->addr,
+				  p->wake_val, ch);
+		if (ret)
+			return ret;
+	}
+
+	ctrlr->dirty = 0;
+	return ret;
+}
+
+int rpmh_write_sleep_and_wake(void)
+{
+	struct rpmh_ctrlr *ctrlr = get_rpmh_ctrlr();
+	int ch, ret;
+
+	if (!ctrlr)
+		return -1;
+
+	ch = rpmh_rsc_get_channel(ctrlr_to_drv(ctrlr));
+	if (ch < 0)
+		return ch;
+
+	ret = rpmh_flush(ctrlr, ch);
+	if (ret || !(ctrlr->flags & HW_CHANNEL_PRESENT))
+		return ret;
+
+	return rpmh_rsc_switch_channel(ctrlr_to_drv(ctrlr), ch);
+}
+
+void rpmh_invalidate(void)
+{
+	struct rpmh_ctrlr *ctrlr = get_rpmh_ctrlr();
+
+	if (rpmh_standalone || !ctrlr)
+		return;
+
+	memset(&ctrlr->batch_cache[RPMH_SLEEP_STATE], 0, sizeof(struct rpmh_request));
+	memset(&ctrlr->batch_cache[RPMH_WAKE_ONLY_STATE], 0, sizeof(struct rpmh_request));
+	ctrlr->dirty = 1;
+}
+
+int rpmh_mode_solver_set(bool enable)
+{
+	struct rpmh_ctrlr *ctrlr = get_rpmh_ctrlr();
+	int ret;
+
+	if (rpmh_standalone || !ctrlr)
+		return 0;
+
+	if (!(ctrlr->flags & SOLVER_PRESENT))
+		return -1;
+
+	ret = rpmh_rsc_mode_solver_set(ctrlr_to_drv(ctrlr), enable);
+	if (!ret)
+		ctrlr->in_solver_mode = enable;
+
+	return ret;
+}
+
+int rpmh_init_fast_path(struct tcs_cmd *cmd, int n)
+{
+	struct rpmh_ctrlr *ctrlr = get_rpmh_ctrlr();
+	struct tcs_request req;
+	int ch;
+
+	if (rpmh_standalone || !ctrlr)
+		return 0;
+
+	ch = rpmh_rsc_get_channel(ctrlr_to_drv(ctrlr));
+	if (ch < 0)
+		return ch;
+
+	req.cmds = cmd;
+	req.num_cmds = n;
+	req.wait_for_compl = 0;
+
+	return rpmh_rsc_init_fast_path(ctrlr_to_drv(ctrlr), &req, ch);
+}
+
+int rpmh_update_fast_path(struct tcs_cmd *cmd, int n, u32 update_mask)
+{
+	struct rpmh_ctrlr *ctrlr = get_rpmh_ctrlr();
+	struct tcs_request req;
+	int ch;
+
+	if (rpmh_standalone || !ctrlr)
+		return 0;
+
+	ch = rpmh_rsc_get_channel(ctrlr_to_drv(ctrlr));
+	if (ch < 0)
+		return ch;
+
+	req.cmds = cmd;
+	req.num_cmds = n;
+	req.wait_for_compl = 0;
+
+	return rpmh_rsc_update_fast_path(ctrlr_to_drv(ctrlr), &req,
+					 update_mask, ch);
+}
diff --git a/src/soc/qualcomm/common/rpmh_bcm.c b/src/soc/qualcomm/common/rpmh_bcm.c
new file mode 100644
index 0000000000..01de7ffd88
--- /dev/null
+++ b/src/soc/qualcomm/common/rpmh_bcm.c
@@ -0,0 +1,59 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+#include <device/device.h>
+#include <console/console.h>
+#include <soc/cmd_db.h>
+#include <soc/rpmh.h>
+#include <soc/rpmh_bcm.h>
+#include <soc/tcs.h>
+
+/**
+ * rpmh_bcm_vote() - Send BCM (Bus Clock Manager) vote to RPMh
+ * @dev: Device pointer for RPMh communication
+ * @resource_name: BCM resource name (e.g., "MM0", "SH0")
+ * @vote_value: Vote value to send
+ *
+ * This function sends a BCM vote to RPMh to enable bandwidth/clock requirements.
+ * It looks up the resource address from Command DB and sends the vote via TCS command.
+ *
+ * Return: 0 on success, negative error code on failure
+ */
+int rpmh_bcm_vote(const char *resource_name, u32 vote_value)
+{
+	u32 bcm_addr;
+	struct tcs_cmd cmd;
+	int rc;
+
+	if (!resource_name) {
+		printk(BIOS_ERR, "BCM: Invalid parameters\n");
+		return -1;
+	}
+
+	/* Get the RPMh address for the BCM resource from Command DB */
+	bcm_addr = cmd_db_read_addr(resource_name);
+	if (!bcm_addr) {
+		printk(BIOS_ERR, "BCM: Could not find RPMh address for resource %s\n",
+		       resource_name);
+		return -1;
+	}
+
+	printk(BIOS_DEBUG, "BCM: Found address 0x%08X for resource %s\n",
+	       bcm_addr, resource_name);
+
+	/* Prepare TCS command */
+	cmd.addr = bcm_addr;
+	cmd.data = vote_value;
+	cmd.wait = true;
+
+	/* Send BCM vote via RPMh in active-only state */
+	rc = rpmh_write(RPMH_ACTIVE_ONLY_STATE, &cmd, 1);
+	if (rc) {
+		printk(BIOS_ERR, "BCM: Failed to send vote for %s (addr=0x%08X, val=0x%08X): %d\n",
+		       resource_name, bcm_addr, vote_value, rc);
+		return rc;
+	}
+
+	printk(BIOS_INFO, "BCM: Successfully voted for %s (addr=0x%08X, val=0x%08X)\n",
+	       resource_name, bcm_addr, vote_value);
+
+	return 0;
+}
diff --git a/src/soc/qualcomm/common/rpmh_regulator.c b/src/soc/qualcomm/common/rpmh_regulator.c
new file mode 100644
index 0000000000..c273333349
--- /dev/null
+++ b/src/soc/qualcomm/common/rpmh_regulator.c
@@ -0,0 +1,458 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <console/console.h>
+#include <delay.h>
+#include <device/device.h>
+#include <string.h>
+#include <types.h>
+#include <soc/rpmh.h>
+#include <soc/cmd_db.h>
+#include <soc/rpmh_regulator.h>
+
+/**
+ * rpmh_regulator_load_arc_level_mapping() - load the RPMh ARC resource's
+ *		voltage level mapping from command db
+ * @vreg:	Pointer to the rpmh regulator
+ *
+ * Return: 0 on success, -1 on failure
+ */
+static int rpmh_regulator_load_arc_level_mapping(struct rpmh_vreg *vreg)
+{
+	size_t len = 0;
+	int i, j;
+	const u8 *buf;
+
+	buf = cmd_db_read_aux_data(vreg->resource_name, &len);
+	if (!buf) {
+		printk(BIOS_ERR, "RPMH_REG: Could not retrieve ARC aux data for %s\n",
+		       vreg->resource_name);
+		return -1;
+	}
+
+	if (len == 0) {
+		printk(BIOS_ERR, "RPMH_REG: ARC level mapping data missing for %s\n",
+		       vreg->resource_name);
+		return -1;
+	}
+
+	if (len > RPMH_ARC_MAX_LEVELS * RPMH_ARC_LEVEL_SIZE) {
+		printk(BIOS_ERR, "RPMH_REG: Too many ARC levels defined for %s: %zu > %d\n",
+		       vreg->resource_name, len, RPMH_ARC_MAX_LEVELS * RPMH_ARC_LEVEL_SIZE);
+		return -1;
+	}
+
+	if (len % RPMH_ARC_LEVEL_SIZE) {
+		printk(BIOS_ERR, "RPMH_REG: Invalid ARC aux data size for %s: %zu\n",
+		       vreg->resource_name, len);
+		return -1;
+	}
+
+	vreg->level_count = len / RPMH_ARC_LEVEL_SIZE;
+
+	for (i = 0; i < vreg->level_count; i++) {
+		vreg->level[i] = 0;
+		for (j = 0; j < RPMH_ARC_LEVEL_SIZE; j++)
+			vreg->level[i] |= buf[i * RPMH_ARC_LEVEL_SIZE + j] << (8 * j);
+
+		/* The AUX data may be zero padded - ignore 0 valued entries at the end */
+		if (i > 0 && vreg->level[i] == 0) {
+			vreg->level_count = i;
+			break;
+		}
+
+		printk(BIOS_DEBUG, "RPMH_REG: %s ARC hlvl=%2d --> vlvl=%4u\n",
+		       vreg->resource_name, i, vreg->level[i]);
+	}
+
+	return 0;
+}
+
+/**
+ * rpmh_regulator_send_request() - send the RPMh request
+ * @vreg:	Pointer to the rpmh regulator
+ * @req:	Request to send
+ * @state:	RPMh state (active/sleep)
+ * @wait:	Whether to wait for completion
+ *
+ * Return: 0 on success, -1 on failure
+ */
+static int rpmh_regulator_send_request(struct rpmh_vreg *vreg,
+				       struct rpmh_regulator_request *req,
+				       enum rpmh_state state, bool wait)
+{
+	struct tcs_cmd cmd[RPMH_REGULATOR_REG_MAX];
+	int i, j = 0;
+	int rc;
+
+	/* Build command array from valid registers */
+	for (i = 0; i < RPMH_REGULATOR_REG_MAX; i++) {
+		if (req->valid & BIT(i)) {
+			cmd[j].addr = vreg->addr + i * 4;
+			cmd[j].data = req->reg[i];
+			cmd[j].wait = true;
+			j++;
+		}
+	}
+	if (j == 0)
+		return 0;
+
+	/* Send the request */
+	if (wait)
+		rc = rpmh_write(state, cmd, j);
+	else
+		rc = rpmh_write_async(state, cmd, j);
+
+	if (rc) {
+		printk(BIOS_ERR, "RPMH_REG: Failed to send %s request for %s, rc=%d\n",
+		       state == RPMH_ACTIVE_ONLY_STATE ? "active" : "sleep",
+		       vreg->resource_name, rc);
+		return rc;
+	}
+
+	printk(BIOS_DEBUG, "RPMH_REG: Sent %s request for %s\n",
+	       state == RPMH_ACTIVE_ONLY_STATE ? "active" : "sleep",
+	       vreg->resource_name);
+
+	return 0;
+}
+
+/**
+ * rpmh_regulator_vrm_set_voltage() - set the voltage of a VRM regulator
+ * @vreg:	Pointer to the rpmh regulator
+ * @min_uv:	Minimum voltage in microvolts
+ * @max_uv:	Maximum voltage in microvolts
+ * @set_active:	Set in active state
+ * @set_sleep:	Set in sleep state
+ *
+ * Return: 0 on success, -1 on failure
+ */
+int rpmh_regulator_vrm_set_voltage(struct rpmh_vreg *vreg, int min_uv, int max_uv,
+				   bool set_active, bool set_sleep)
+{
+	int mv;
+	int rc = 0;
+
+	if (!vreg || vreg->type != RPMH_REGULATOR_TYPE_VRM)
+		return -1;
+
+	if (min_uv < RPMH_VRM_MIN_UV || max_uv > RPMH_VRM_MAX_UV) {
+		printk(BIOS_ERR, "RPMH_REG: Voltage range %d-%d uV out of bounds for %s\n",
+		       min_uv, max_uv, vreg->resource_name);
+		return -1;
+	}
+
+	mv = DIV_ROUND_UP(min_uv, 1000);
+	if (mv * 1000 > max_uv) {
+		printk(BIOS_ERR, "RPMH_REG: No set points available in range %d-%d uV for %s\n",
+		       min_uv, max_uv, vreg->resource_name);
+		return -1;
+	}
+
+	if (set_active) {
+		vreg->req_active.reg[RPMH_REGULATOR_REG_VRM_VOLTAGE] = mv;
+		vreg->req_active.valid |= BIT(RPMH_REGULATOR_REG_VRM_VOLTAGE);
+		rc = rpmh_regulator_send_request(vreg, &vreg->req_active,
+						 RPMH_ACTIVE_ONLY_STATE, true);
+		if (rc)
+			return rc;
+	}
+
+	if (set_sleep) {
+		vreg->req_sleep.reg[RPMH_REGULATOR_REG_VRM_VOLTAGE] = mv;
+		vreg->req_sleep.valid |= BIT(RPMH_REGULATOR_REG_VRM_VOLTAGE);
+		rc = rpmh_regulator_send_request(vreg, &vreg->req_sleep,
+						 RPMH_SLEEP_STATE, false);
+	}
+
+	return rc;
+}
+
+/**
+ * rpmh_regulator_vrm_set_mode() - set the mode of a VRM regulator
+ * @vreg:	Pointer to the rpmh regulator
+ * @mode:	PMIC mode value
+ * @set_active:	Set in active state
+ * @set_sleep:	Set in sleep state
+ *
+ * Return: 0 on success, -1 on failure
+ */
+int rpmh_regulator_vrm_set_mode(struct rpmh_vreg *vreg, u32 mode,
+				bool set_active, bool set_sleep)
+{
+	int rc = 0;
+
+	if (!vreg || vreg->type != RPMH_REGULATOR_TYPE_VRM)
+		return -1;
+
+	if (mode < RPMH_VRM_MODE_MIN || mode > RPMH_VRM_MODE_MAX) {
+		printk(BIOS_ERR, "RPMH_REG: Mode %u out of range for %s\n",
+		       mode, vreg->resource_name);
+		return -1;
+	}
+
+	if (set_active) {
+		vreg->req_active.reg[RPMH_REGULATOR_REG_VRM_MODE] = mode;
+		vreg->req_active.valid |= BIT(RPMH_REGULATOR_REG_VRM_MODE);
+		rc = rpmh_regulator_send_request(vreg, &vreg->req_active,
+						 RPMH_ACTIVE_ONLY_STATE, true);
+		if (rc)
+			return rc;
+	}
+
+	if (set_sleep) {
+		vreg->req_sleep.reg[RPMH_REGULATOR_REG_VRM_MODE] = mode;
+		vreg->req_sleep.valid |= BIT(RPMH_REGULATOR_REG_VRM_MODE);
+		rc = rpmh_regulator_send_request(vreg, &vreg->req_sleep,
+						 RPMH_SLEEP_STATE, false);
+	}
+
+	return rc;
+}
+
+/**
+ * rpmh_regulator_enable() - enable a regulator
+ * @vreg:	Pointer to the rpmh regulator
+ * @set_active:	Set in active state
+ * @set_sleep:	Set in sleep state
+ *
+ * Return: 0 on success, -1 on failure
+ */
+int rpmh_regulator_enable(struct rpmh_vreg *vreg, bool set_active, bool set_sleep)
+{
+	int rc = 0;
+	int reg_index;
+
+	if (!vreg)
+		return -1;
+
+	/* Determine the correct enable register based on type */
+	switch (vreg->type) {
+	case RPMH_REGULATOR_TYPE_VRM:
+	case RPMH_REGULATOR_TYPE_ARC:
+	case RPMH_REGULATOR_TYPE_XOB:
+		reg_index = RPMH_REGULATOR_REG_ENABLE;
+		break;
+	case RPMH_REGULATOR_TYPE_PBS:
+		reg_index = RPMH_REGULATOR_REG_PBS_ENABLE;
+		break;
+	default:
+		return -1;
+	}
+
+	if (set_active) {
+		vreg->req_active.reg[reg_index] = 1;
+		vreg->req_active.valid |= BIT(reg_index);
+		rc = rpmh_regulator_send_request(vreg, &vreg->req_active,
+						 RPMH_ACTIVE_ONLY_STATE, true);
+		if (rc)
+			return rc;
+	}
+
+	if (set_sleep) {
+		vreg->req_sleep.reg[reg_index] = 1;
+		vreg->req_sleep.valid |= BIT(reg_index);
+		rc = rpmh_regulator_send_request(vreg, &vreg->req_sleep,
+						 RPMH_SLEEP_STATE, false);
+	}
+
+	return rc;
+}
+
+/**
+ * rpmh_regulator_disable() - disable a regulator
+ * @vreg:	Pointer to the rpmh regulator
+ * @set_active:	Set in active state
+ * @set_sleep:	Set in sleep state
+ *
+ * Return: 0 on success, -1 on failure
+ */
+int rpmh_regulator_disable(struct rpmh_vreg *vreg, bool set_active, bool set_sleep)
+{
+	int rc = 0;
+	int reg_index;
+
+	if (!vreg)
+		return -1;
+
+	/* Determine the correct enable register based on type */
+	switch (vreg->type) {
+	case RPMH_REGULATOR_TYPE_VRM:
+	case RPMH_REGULATOR_TYPE_ARC:
+	case RPMH_REGULATOR_TYPE_XOB:
+		reg_index = RPMH_REGULATOR_REG_ENABLE;
+		break;
+	case RPMH_REGULATOR_TYPE_PBS:
+		reg_index = RPMH_REGULATOR_REG_PBS_ENABLE;
+		break;
+	default:
+		return -1;
+	}
+
+	if (set_active) {
+		vreg->req_active.reg[reg_index] = 0;
+		vreg->req_active.valid |= BIT(reg_index);
+		rc = rpmh_regulator_send_request(vreg, &vreg->req_active,
+						 RPMH_ACTIVE_ONLY_STATE, true);
+		if (rc)
+			return rc;
+	}
+
+	if (set_sleep) {
+		vreg->req_sleep.reg[reg_index] = 0;
+		vreg->req_sleep.valid |= BIT(reg_index);
+		rc = rpmh_regulator_send_request(vreg, &vreg->req_sleep,
+						 RPMH_SLEEP_STATE, false);
+	}
+
+	return rc;
+}
+
+/**
+ * rpmh_regulator_arc_set_level() - set the voltage level of an ARC regulator
+ * @vreg:	Pointer to the rpmh regulator
+ * @level:	ARC voltage level (0 to level_count-1)
+ * @set_active:	Set in active state
+ * @set_sleep:	Set in sleep state
+ *
+ * Return: 0 on success, -1 on failure
+ */
+int rpmh_regulator_arc_set_level(struct rpmh_vreg *vreg, u32 level,
+				  bool set_active, bool set_sleep)
+{
+	int rc = 0;
+
+	if (!vreg || vreg->type != RPMH_REGULATOR_TYPE_ARC)
+		return -1;
+
+	if (level >= vreg->level_count) {
+		printk(BIOS_ERR, "RPMH_REG: Level %u out of range for %s (max %d)\n",
+		       level, vreg->resource_name, vreg->level_count - 1);
+		return -1;
+	}
+
+	if (set_active) {
+		vreg->req_active.reg[RPMH_REGULATOR_REG_ARC_LEVEL] = level;
+		vreg->req_active.valid |= BIT(RPMH_REGULATOR_REG_ARC_LEVEL);
+		rc = rpmh_regulator_send_request(vreg, &vreg->req_active,
+						 RPMH_ACTIVE_ONLY_STATE, true);
+		if (rc)
+			return rc;
+	}
+
+	if (set_sleep) {
+		vreg->req_sleep.reg[RPMH_REGULATOR_REG_ARC_LEVEL] = level;
+		vreg->req_sleep.valid |= BIT(RPMH_REGULATOR_REG_ARC_LEVEL);
+		rc = rpmh_regulator_send_request(vreg, &vreg->req_sleep,
+						 RPMH_SLEEP_STATE, false);
+	}
+
+	return rc;
+}
+
+/**
+ * rpmh_regulator_arc_get_level() - get the current voltage level of an ARC regulator
+ * @vreg:	Pointer to the rpmh regulator
+ *
+ * This function returns the cached ARC voltage level that was last set.
+ * Note: This returns the requested level, not necessarily the actual hardware level,
+ * as there's no way to read back from RPMh hardware.
+ *
+ * Return: ARC voltage level (0 to level_count-1) on success, -1 on failure
+ */
+int rpmh_regulator_arc_get_level(struct rpmh_vreg *vreg)
+{
+	if (!vreg || vreg->type != RPMH_REGULATOR_TYPE_ARC)
+		return -1;
+
+	/* Return the active set level if valid, otherwise return 0 */
+	if (vreg->req_active.valid & BIT(RPMH_REGULATOR_REG_ARC_LEVEL))
+		return vreg->req_active.reg[RPMH_REGULATOR_REG_ARC_LEVEL];
+
+	return 0;
+}
+
+/**
+ * rpmh_regulator_arc_get_voltage_level() - get the voltage level value for an ARC level
+ * @vreg:	Pointer to the rpmh regulator
+ * @level:	ARC level index
+ *
+ * This function returns the actual voltage level value (vlvl) that corresponds
+ * to the given ARC hardware level (hlvl).
+ *
+ * Return: voltage level value on success, 0 on failure
+ */
+u32 rpmh_regulator_arc_get_voltage_level(struct rpmh_vreg *vreg, u32 level)
+{
+	if (!vreg || vreg->type != RPMH_REGULATOR_TYPE_ARC)
+		return 0;
+
+	if (level >= vreg->level_count)
+		return 0;
+
+	return vreg->level[level];
+}
+
+/**
+ * rpmh_regulator_init() - initialize an rpmh regulator
+ * @vreg:		Pointer to the rpmh regulator structure to initialize
+ * @dev:		Device pointer for RPMh communication
+ * @resource_name:	Name of the RPMh resource
+ * @type:		Type of regulator (VRM, ARC, XOB, PBS)
+ *
+ * Return: 0 on success, -1 on failure
+ */
+int rpmh_regulator_init(struct rpmh_vreg *vreg, const char *resource_name,
+			enum rpmh_regulator_type type)
+{
+	enum cmd_db_hw_type hw_type;
+	int rc;
+
+	if (!vreg || !resource_name)
+		return -1;
+
+	memset(vreg, 0, sizeof(*vreg));
+
+	vreg->resource_name = resource_name;
+	vreg->type = type;
+
+	/* Get the RPMh address for this resource */
+	vreg->addr = cmd_db_read_addr(resource_name);
+	if (!vreg->addr) {
+		printk(BIOS_ERR, "RPMH_REG: Could not find RPMh address for %s\n",
+		       resource_name);
+		return -1;
+	}
+
+	/* Verify the slave ID matches the expected type */
+	hw_type = cmd_db_read_slave_id(resource_name);
+	if (hw_type == CMD_DB_HW_INVALID) {
+		printk(BIOS_ERR, "RPMH_REG: Could not find slave ID for %s\n",
+		       resource_name);
+		return -1;
+	}
+
+	/* Validate hardware type matches regulator type */
+	if ((type == RPMH_REGULATOR_TYPE_ARC && hw_type != CMD_DB_HW_ARC) ||
+	    (type == RPMH_REGULATOR_TYPE_VRM && hw_type != CMD_DB_HW_VRM) ||
+	    (type == RPMH_REGULATOR_TYPE_XOB && hw_type != CMD_DB_HW_XOB) ||
+	    (type == RPMH_REGULATOR_TYPE_BCM && hw_type != CMD_DB_HW_BCM) ||
+	    (type == RPMH_REGULATOR_TYPE_PBS && hw_type != CMD_DB_HW_PBS)) {
+		printk(BIOS_ERR, "RPMH_REG: Hardware type mismatch for %s\n",
+		       resource_name);
+		return -1;
+	}
+
+	/* Load ARC level mapping if this is an ARC regulator */
+	if (type == RPMH_REGULATOR_TYPE_ARC) {
+		rc = rpmh_regulator_load_arc_level_mapping(vreg);
+		if (rc) {
+			printk(BIOS_ERR, "RPMH_REG: Failed to load ARC level mapping for %s\n",
+			       resource_name);
+			return rc;
+		}
+	}
+	printk(BIOS_INFO, "RPMH_REG: Initialized %s at addr=0x%05X\n",
+	       resource_name, vreg->addr);
+
+	return 0;
+}
diff --git a/src/soc/qualcomm/common/rpmh_rsc.c b/src/soc/qualcomm/common/rpmh_rsc.c
new file mode 100644
index 0000000000..e93d4454eb
--- /dev/null
+++ b/src/soc/qualcomm/common/rpmh_rsc.c
@@ -0,0 +1,511 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <console/console.h>
+#include <delay.h>
+#include <device/mmio.h>
+#include <string.h>
+#include <timer.h>
+#include <soc/cmd_db.h>
+#include <soc/tcs.h>
+#include <soc/rpmh_internal.h>
+
+#define TCS_AMC_MODE_ENABLE		BIT(16)
+#define TCS_AMC_MODE_TRIGGER		BIT(24)
+
+/* TCS CMD register bit mask */
+#define CMD_MSGID_LEN			8
+#define CMD_MSGID_RESP_REQ		BIT(8)
+#define CMD_MSGID_WRITE			BIT(16)
+#define CMD_STATUS_ISSUED		BIT(8)
+#define CMD_STATUS_COMPL		BIT(16)
+
+/* Offsets for DRV channel status register */
+#define CH0_CHN_BUSY			BIT(0)
+#define CH1_CHN_BUSY			BIT(1)
+#define CH0_WAKE_TCS_STATUS		BIT(0)
+#define CH0_SLEEP_TCS_STATUS		BIT(1)
+#define CH1_WAKE_TCS_STATUS		BIT(2)
+#define CH1_SLEEP_TCS_STATUS		BIT(3)
+#define CH_CLEAR_STATUS			BIT(31)
+
+static inline void *tcs_reg_addr(const struct rsc_drv *drv, int reg, int tcs_id)
+{
+	if (!drv->tcs_distance)
+		return drv->tcs_base + drv->regs[RSC_DRV_TCS_OFFSET] * tcs_id + reg;
+
+	return drv->tcs_base + drv->tcs_distance * tcs_id + reg;
+}
+
+static inline void *tcs_cmd_addr(const struct rsc_drv *drv, int reg, int tcs_id, int cmd_id)
+{
+	return tcs_reg_addr(drv, reg, tcs_id) + drv->regs[RSC_DRV_CMD_OFFSET] * cmd_id;
+}
+
+static u32 read_tcs_cmd(const struct rsc_drv *drv, int reg, int tcs_id, int cmd_id)
+{
+	return read32(tcs_cmd_addr(drv, reg, tcs_id, cmd_id));
+}
+
+static u32 read_tcs_reg(const struct rsc_drv *drv, int reg, int tcs_id)
+{
+	return read32(tcs_reg_addr(drv, reg, tcs_id));
+}
+
+static void write_tcs_cmd(const struct rsc_drv *drv, int reg, int tcs_id,
+			  int cmd_id, u32 data)
+{
+	write32(tcs_cmd_addr(drv, reg, tcs_id, cmd_id), data);
+}
+
+static void write_tcs_reg(const struct rsc_drv *drv, int reg, int tcs_id, u32 data)
+{
+	write32(tcs_reg_addr(drv, reg, tcs_id), data);
+}
+
+static void write_tcs_reg_sync(const struct rsc_drv *drv, int reg, int tcs_id, u32 data)
+{
+	struct stopwatch sw;
+
+	write32(tcs_reg_addr(drv, reg, tcs_id), data);
+
+	/* Wait until we read back the same value */
+	stopwatch_init_usecs_expire(&sw, USECS_1S);
+	while (read32(tcs_reg_addr(drv, reg, tcs_id)) != data) {
+		if (stopwatch_expired(&sw)) {
+			printk(BIOS_ERR, "%s: error writing %#x to %d:%#x\n", drv->name,
+			       data, tcs_id, reg);
+			break;
+		}
+		udelay(LOOP_DELAY_US);
+	}
+}
+
+static void tcs_invalidate(struct rsc_drv *drv, int type, int ch)
+{
+	int m;
+	struct tcs_group *tcs = &drv->ch[ch].tcs[type];
+
+	/* Check if already empty */
+	if (tcs->slots[0] == 0)
+		return;
+
+	for (m = tcs->offset; m < tcs->offset + tcs->num_tcs; m++) {
+		write_tcs_reg_sync(drv, drv->regs[RSC_DRV_CMD_ENABLE], m, 0);
+		write_tcs_reg_sync(drv, drv->regs[RSC_DRV_CMD_WAIT_FOR_CMPL], m, 0);
+	}
+
+	memset(tcs->slots, 0, sizeof(tcs->slots));
+}
+
+int rpmh_rsc_get_channel(struct rsc_drv *drv)
+{
+	int chn_update, chn_busy;
+
+	if (drv->num_channels == 1)
+		return CH0;
+
+	/* Select Unused channel */
+	do {
+		chn_update = read32(drv->base + drv->regs[RSC_DRV_CHN_UPDATE]);
+		chn_busy = read32(drv->base + drv->regs[RSC_DRV_CHN_BUSY]);
+	} while (chn_busy != chn_update);
+
+	if (chn_busy & CH0_CHN_BUSY)
+		return CH1;
+	else if (chn_busy & CH1_CHN_BUSY)
+		return CH0;
+	else
+		return -1;
+}
+
+void rpmh_rsc_invalidate(struct rsc_drv *drv, int ch)
+{
+	tcs_invalidate(drv, SLEEP_TCS, ch);
+	tcs_invalidate(drv, WAKE_TCS, ch);
+}
+
+static struct tcs_group *get_tcs_for_msg(struct rsc_drv *drv,
+					 enum rpmh_state state,
+					 int ch)
+{
+	int type;
+	struct tcs_group *tcs;
+
+	switch (state) {
+	case RPMH_ACTIVE_ONLY_STATE:
+		type = ACTIVE_TCS;
+		break;
+	case RPMH_WAKE_ONLY_STATE:
+		type = WAKE_TCS;
+		break;
+	case RPMH_SLEEP_STATE:
+		type = SLEEP_TCS;
+		break;
+	default:
+		return NULL;
+	}
+
+	tcs = &drv->ch[ch].tcs[type];
+	if (state == RPMH_ACTIVE_ONLY_STATE && !tcs->num_tcs)
+		tcs = &drv->ch[ch].tcs[WAKE_TCS];
+
+	return tcs;
+}
+
+static void __tcs_set_trigger(struct rsc_drv *drv, int tcs_id, bool trigger)
+{
+	u32 enable;
+	u32 reg = drv->regs[RSC_DRV_CONTROL];
+
+	enable = read_tcs_reg(drv, reg, tcs_id);
+	enable &= ~TCS_AMC_MODE_TRIGGER;
+	write_tcs_reg_sync(drv, reg, tcs_id, enable);
+	enable &= ~TCS_AMC_MODE_ENABLE;
+	write_tcs_reg_sync(drv, reg, tcs_id, enable);
+
+	if (trigger) {
+		enable = TCS_AMC_MODE_ENABLE;
+		write_tcs_reg_sync(drv, reg, tcs_id, enable);
+		enable |= TCS_AMC_MODE_TRIGGER;
+		write_tcs_reg(drv, reg, tcs_id, enable);
+	}
+}
+
+static void __tcs_buffer_write(struct rsc_drv *drv, int tcs_id, int cmd_id,
+			       const struct tcs_request *msg)
+{
+	u32 msgid;
+	u32 cmd_msgid = CMD_MSGID_LEN | CMD_MSGID_WRITE;
+	u32 cmd_enable = 0;
+	u32 cmd_complete;
+	struct tcs_cmd *cmd;
+	int i, j;
+
+	cmd_msgid |= msg->wait_for_compl ? CMD_MSGID_RESP_REQ : 0;
+	cmd_complete = read_tcs_reg(drv, drv->regs[RSC_DRV_CMD_WAIT_FOR_CMPL], tcs_id);
+
+	for (i = 0, j = cmd_id; i < msg->num_cmds; i++, j++) {
+		cmd = &msg->cmds[i];
+		cmd_enable |= BIT(j);
+		cmd_complete |= cmd->wait << j;
+		msgid = cmd_msgid;
+		msgid |= cmd->wait ? CMD_MSGID_RESP_REQ : 0;
+
+		write_tcs_cmd(drv, drv->regs[RSC_DRV_CMD_MSGID], tcs_id, j, msgid);
+		write_tcs_cmd(drv, drv->regs[RSC_DRV_CMD_ADDR], tcs_id, j, cmd->addr);
+		write_tcs_cmd(drv, drv->regs[RSC_DRV_CMD_DATA], tcs_id, j, cmd->data);
+	}
+
+	write_tcs_reg(drv, drv->regs[RSC_DRV_CMD_WAIT_FOR_CMPL], tcs_id, cmd_complete);
+	cmd_enable |= read_tcs_reg(drv, drv->regs[RSC_DRV_CMD_ENABLE], tcs_id);
+	write_tcs_reg(drv, drv->regs[RSC_DRV_CMD_ENABLE], tcs_id, cmd_enable);
+}
+
+static int check_for_req_inflight(struct rsc_drv *drv, struct tcs_group *tcs,
+				  const struct tcs_request *msg)
+{
+	u32 curr_enabled;
+	u32 addr;
+	int j, k;
+	int i = tcs->offset;
+
+	for (; i < tcs->offset + tcs->num_tcs; i++) {
+		if (!(drv->tcs_in_use[i / 32] & BIT(i % 32)))
+			continue;
+
+		curr_enabled = read_tcs_reg(drv, drv->regs[RSC_DRV_CMD_ENABLE], i);
+
+		for (j = 0; j < tcs->ncpt; j++) {
+			if (!(curr_enabled & BIT(j)))
+				continue;
+
+			addr = read_tcs_cmd(drv, drv->regs[RSC_DRV_CMD_ADDR], i, j);
+			for (k = 0; k < msg->num_cmds; k++) {
+				if (cmd_db_match_resource_addr(msg->cmds[k].addr, addr))
+					return -1;
+			}
+		}
+	}
+
+	return 0;
+}
+
+static int find_free_tcs(struct tcs_group *tcs)
+{
+	const struct rsc_drv *drv = tcs->drv;
+	struct stopwatch sw;
+	int i;
+	u32 sts;
+
+	for (i = tcs->offset; i < tcs->offset + tcs->num_tcs; i++) {
+		if (drv->tcs_in_use[i / 32] & BIT(i % 32))
+			continue;
+
+		stopwatch_init_usecs_expire(&sw, USECS_100US);
+		while (1) {
+			sts = read_tcs_reg(drv, drv->regs[RSC_DRV_STATUS], i);
+			if (sts)
+				return i;
+			if (stopwatch_expired(&sw))
+				return -1;
+			udelay(LOOP_DELAY_US);
+		}
+	}
+
+	return -1;
+}
+
+static int claim_tcs_for_req(struct rsc_drv *drv, struct tcs_group *tcs,
+			     const struct tcs_request *msg)
+{
+	int ret;
+
+	ret = check_for_req_inflight(drv, tcs, msg);
+	if (ret)
+		return ret;
+
+	return find_free_tcs(tcs);
+}
+
+int rpmh_rsc_send_data(struct rsc_drv *drv, const struct tcs_request *msg, int ch)
+{
+	struct tcs_group *tcs;
+	struct stopwatch sw;
+	int tcs_id;
+	u32 status;
+
+	tcs = get_tcs_for_msg(drv, msg->state, ch);
+	if (!tcs)
+		return -1;
+
+	/* Controller is busy in 'solver' mode */
+	if (drv->in_solver_mode) {
+		printk(BIOS_ERR, "RPMH RSC: Cannot send ACTIVE request in solver mode\n");
+		return -1;
+	}
+
+	/* Wait for a free tcs with hardware status verification */
+	stopwatch_init_usecs_expire(&sw, USECS_100MS);
+	while (1) {
+		tcs_id = claim_tcs_for_req(drv, tcs, msg);
+		if (tcs_id >= 0) {
+			/* Double-check hardware status register */
+			status = read_tcs_reg(drv, drv->regs[RSC_DRV_STATUS], tcs_id);
+			if (status) {  /* 1 = IDLE, 0 = BUSY */
+				break;
+			}
+			/* TCS claimed but hardware still busy, retry */
+			printk(BIOS_DEBUG, "RPMH RSC: TCS %d claimed but HW busy, retrying\n", tcs_id);
+		}
+		if (stopwatch_expired(&sw)) {
+			printk(BIOS_ERR, "RPMH RSC: No free TCS available (timeout after 100ms)\n");
+			return -1;
+		}
+		udelay(LOOP_DELAY_10US);
+	}
+
+	tcs->req[tcs_id - tcs->offset] = msg;
+	drv->tcs_in_use[tcs_id / 32] |= BIT(tcs_id % 32);
+
+	write_tcs_reg_sync(drv, drv->regs[RSC_DRV_CMD_ENABLE], tcs_id, 0);
+	write_tcs_reg_sync(drv, drv->regs[RSC_DRV_CMD_WAIT_FOR_CMPL], tcs_id, 0);
+
+	__tcs_buffer_write(drv, tcs_id, 0, msg);
+	__tcs_set_trigger(drv, tcs_id, 1);
+
+	/* Poll for completion if wait_for_compl is set */
+	if (msg->wait_for_compl) {
+		stopwatch_init_usecs_expire(&sw, USECS_10MS);
+		while (1) {
+			u32 sts = read_tcs_reg(drv, drv->regs[RSC_DRV_STATUS], tcs_id);
+			if (sts)
+				break;
+			if (stopwatch_expired(&sw)) {
+				printk(BIOS_ERR, "RPMH RSC: TCS %d timeout\n", tcs_id);
+				return -1;
+			}
+			udelay(LOOP_DELAY_US);
+		}
+	}
+
+	drv->tcs_in_use[tcs_id / 32] &= ~BIT(tcs_id % 32);
+
+	return 0;
+}
+
+static int find_slots(struct tcs_group *tcs, const struct tcs_request *msg,
+		      int *tcs_id, int *cmd_id)
+{
+	int slot, offset;
+	int i = 0;
+	int slots_needed = msg->num_cmds;
+
+	/* Find contiguous slots */
+	do {
+		slot = 0;
+		for (i = 0; i < tcs->ncpt * tcs->num_tcs; i++) {
+			if (tcs->slots[i / 32] & BIT(i % 32)) {
+				slot = 0;
+			} else {
+				slot++;
+				if (slot >= slots_needed)
+					break;
+			}
+		}
+		if (slot < slots_needed)
+			return -1;
+
+		i = i - slot + 1;
+	} while (i + slots_needed - 1 >= ((i / tcs->ncpt) + 1) * tcs->ncpt);
+
+	/* Mark slots as used */
+	for (slot = i; slot < i + slots_needed; slot++)
+		tcs->slots[slot / 32] |= BIT(slot % 32);
+
+	offset = i / tcs->ncpt;
+	*tcs_id = offset + tcs->offset;
+	*cmd_id = i % tcs->ncpt;
+
+	return 0;
+}
+
+int rpmh_rsc_write_ctrl_data(struct rsc_drv *drv, const struct tcs_request *msg, int ch)
+{
+	struct tcs_group *tcs;
+	int tcs_id = 0, cmd_id = 0;
+	int ret;
+
+	if (!msg->num_cmds)
+		return 0;
+
+	tcs = get_tcs_for_msg(drv, msg->state, ch);
+	if (!tcs)
+		return -1;
+
+	ret = find_slots(tcs, msg, &tcs_id, &cmd_id);
+	if (!ret)
+		__tcs_buffer_write(drv, tcs_id, cmd_id, msg);
+
+	return ret;
+}
+
+int rpmh_rsc_mode_solver_set(struct rsc_drv *drv, bool enable)
+{
+	drv->in_solver_mode = enable;
+	return 0;
+}
+
+int rpmh_rsc_switch_channel(struct rsc_drv *drv, int ch)
+{
+	struct stopwatch sw;
+	u32 sts;
+	u32 mask = (ch == 0) ? CH0_WAKE_TCS_STATUS : CH1_WAKE_TCS_STATUS;
+
+	write32(drv->base + drv->regs[RSC_DRV_CHN_UPDATE], BIT(ch));
+
+	stopwatch_init_usecs_expire(&sw, USECS_100US);
+	while (1) {
+		sts = read32(drv->base + drv->regs[RSC_DRV_CHN_TCS_COMPLETE]);
+		if (sts & mask)
+			break;
+		if (stopwatch_expired(&sw))
+			return -1;
+		udelay(LOOP_DELAY_US);
+	}
+
+	write32(drv->base + drv->regs[RSC_DRV_CHN_TCS_COMPLETE], CH_CLEAR_STATUS);
+
+	return 0;
+}
+
+int rpmh_rsc_drv_enable(struct rsc_drv *drv, bool enable)
+{
+	int ret = 0, ch;
+	u32 chn_en;
+
+	chn_en = read32(drv->base + drv->regs[RSC_DRV_CHN_EN]);
+	if (chn_en == enable)
+		return -1;
+
+	if (enable) {
+		ch = 0;
+		ret = rpmh_flush(&drv->client, ch);
+		if (ret)
+			return ret;
+
+		write32(drv->base + drv->regs[RSC_DRV_CHN_EN], enable);
+		ret = rpmh_rsc_switch_channel(drv, ch);
+	} else {
+		ch = rpmh_rsc_get_channel(drv);
+		if (ch < 0)
+			return ch;
+
+		ret = rpmh_flush(&drv->client, ch);
+		if (ret)
+			return ret;
+
+		ret = rpmh_rsc_switch_channel(drv, ch);
+		if (ret)
+			return ret;
+
+		write32(drv->base + drv->regs[RSC_DRV_CHN_UPDATE], 0);
+		write32(drv->base + drv->regs[RSC_DRV_CHN_EN], enable);
+	}
+
+	return ret;
+}
+
+int rpmh_rsc_init_fast_path(struct rsc_drv *drv, const struct tcs_request *msg, int ch)
+{
+	int tcs_id;
+
+	if (!drv->ch[ch].tcs[FAST_PATH_TCS].num_tcs)
+		return -1;
+
+	tcs_id = drv->ch[ch].tcs[FAST_PATH_TCS].offset;
+	__tcs_buffer_write(drv, tcs_id, 0, msg);
+
+	return 0;
+}
+
+int rpmh_rsc_update_fast_path(struct rsc_drv *drv,
+			      const struct tcs_request *msg,
+			      u32 mask, int ch)
+{
+	struct stopwatch sw;
+	int i;
+	u32 sts;
+	int tcs_id;
+	struct tcs_cmd *cmd;
+
+	if (!drv->ch[ch].tcs[FAST_PATH_TCS].num_tcs)
+		return -1;
+
+	tcs_id = drv->ch[ch].tcs[FAST_PATH_TCS].offset;
+
+	/* Ensure the TCS is free before writing */
+	stopwatch_init_usecs_expire(&sw, USECS_5US);
+	while (1) {
+		sts = read_tcs_reg(drv, drv->regs[RSC_DRV_STATUS], tcs_id);
+		if (sts)
+			break;
+		if (stopwatch_expired(&sw)) {
+			printk(BIOS_ERR, "Fast-path TCS is too busy\n");
+			return -1;
+		}
+		udelay(LOOP_DELAY_US);
+	}
+
+	/* Update only the data fields */
+	for (i = 0; i < msg->num_cmds; i++) {
+		if (!(mask & BIT(i)))
+			continue;
+		cmd = &msg->cmds[i];
+		write_tcs_cmd(drv, drv->regs[RSC_DRV_CMD_DATA], tcs_id, i, cmd->data);
+	}
+
+	/* Trigger the TCS */
+	__tcs_set_trigger(drv, tcs_id, 1);
+
+	return 0;
+}
diff --git a/src/soc/qualcomm/x1p42100/Makefile.mk b/src/soc/qualcomm/x1p42100/Makefile.mk
index abf5971e20..46965a5375 100644
--- a/src/soc/qualcomm/x1p42100/Makefile.mk
+++ b/src/soc/qualcomm/x1p42100/Makefile.mk
@@ -53,6 +53,7 @@ ramstage-y += ../common/spmi.c
 ramstage-$(CONFIG_PCI) += pcie.c
 ramstage-y += cpucp_load_reset.c
 ramstage-y += ../common/cmd_db.c
+ramstage-y += ../common/rpmh.c ../common/rpmh_bcm.c ../common/rpmh_regulator.c ../common/rpmh_rsc.c
 
 ################################################################################
 

From 02e6f2a21486613b1acbc1f4a028588c4cc617a0 Mon Sep 17 00:00:00 2001
From: Swathi Tamilselvan <tswathi@qualcomm.corp-partner.google.com>
Date: Wed, 10 Dec 2025 22:40:07 +0530
Subject: [PATCH 2962/3886] soc/qualcomm/x1p42100: Add API to intialize RPMh
 resources for display

Add API to initialize RPMh resources for display. It includes CMD-DB
initialization, enable the MMCX power rail and cast a vote for the MM0
Bus Clock Manager (BCM) resource to enable display clocks.

Test=1. Create an image.serial.bin and ensure it boots on X1P42100.
2. Verified MMCX rail enablement and MM0 BCM vote using ARC and
BCM AOP dump with API invoking changes hooked up with follow-on
commits.
Serial Log:
[INFO ]  RPMH_REG: Initialized mmcx.lvl at addr=0x30080
[INFO ]  ARC regulator initialized successfully
[DEBUG]  RPMH_REG: Sent active request for mmcx.lvl
[INFO ]  ARC level was set successfully
[DEBUG]  BCM: Found address 0x00050024 for resource MM0
[INFO ]  BCM: Successfully voted for MM0 (addr=0x00050024, val=0x60004001)
[INFO ]  BCM vote for MM0 sent successfully

Change-Id: I1997ce7a1ced4504d6a3170e5f2ddd4f52e0763d
Signed-off-by: Swathi Tamilselvan <tswathi@qualcomm.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90467
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/soc/qualcomm/x1p42100/Makefile.mk         |   2 +
 src/soc/qualcomm/x1p42100/display/disp.c      |  76 ++++++++
 .../x1p42100/include/soc/addressmap.h         |   6 +
 .../x1p42100/include/soc/rpmh_config.h        |  42 +++++
 src/soc/qualcomm/x1p42100/rpmh_rsc_init.c     | 165 ++++++++++++++++++
 5 files changed, 291 insertions(+)
 create mode 100644 src/soc/qualcomm/x1p42100/display/disp.c
 create mode 100644 src/soc/qualcomm/x1p42100/include/soc/rpmh_config.h
 create mode 100644 src/soc/qualcomm/x1p42100/rpmh_rsc_init.c

diff --git a/src/soc/qualcomm/x1p42100/Makefile.mk b/src/soc/qualcomm/x1p42100/Makefile.mk
index 46965a5375..4a51a20dd6 100644
--- a/src/soc/qualcomm/x1p42100/Makefile.mk
+++ b/src/soc/qualcomm/x1p42100/Makefile.mk
@@ -54,6 +54,8 @@ ramstage-$(CONFIG_PCI) += pcie.c
 ramstage-y += cpucp_load_reset.c
 ramstage-y += ../common/cmd_db.c
 ramstage-y += ../common/rpmh.c ../common/rpmh_bcm.c ../common/rpmh_regulator.c ../common/rpmh_rsc.c
+ramstage-y += rpmh_rsc_init.c
+ramstage-y += display/disp.c
 
 ################################################################################
 
diff --git a/src/soc/qualcomm/x1p42100/display/disp.c b/src/soc/qualcomm/x1p42100/display/disp.c
new file mode 100644
index 0000000000..f09adab34f
--- /dev/null
+++ b/src/soc/qualcomm/x1p42100/display/disp.c
@@ -0,0 +1,76 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <device/device.h>
+#include <console/console.h>
+#include <timer.h>
+#include <soc/addressmap.h>
+#include <soc/cmd_db.h>
+#include <soc/rpmh.h>
+#include <soc/rpmh_bcm.h>
+#include <soc/rpmh_config.h>
+#include <soc/rpmh_regulator.h>
+
+/**
+ * display_rpmh_init() - Initialize RPMh for display power management
+ *
+ * Initializes the RPMh (Resource Power Manager-Hardened) subsystem for display:
+ * - Waits for AOP boot
+ * - Initializes Command DB and RPMh RSC (Resource State Coordinator)
+ * - Configures MMCX ARC regulator for display power rail
+ * - Votes for MM0 BCM (Bus Clock Manager) for display bus clocks
+ *
+ * Return: CB_SUCCESS on success, CB_ERR on failure
+ */
+enum cb_err display_rpmh_init(void)
+{
+	enum cb_err ret;
+	struct rpmh_vreg arc_reg;
+	int rc;
+	volatile u32 *boot_cookie = (volatile u32 *)AOP_BOOT_COOKIE_ADDR;
+
+	if (!wait_us(AOP_BOOT_TIMEOUT_US, *boot_cookie == AOP_BOOT_COOKIE)) {
+		printk(BIOS_ERR, "AOP not booted after %dus (cookie: 0x%x, expected: 0x%x)\n",
+			AOP_BOOT_TIMEOUT_US, *boot_cookie, AOP_BOOT_COOKIE);
+		return CB_ERR;
+	}
+
+	printk(BIOS_INFO, "AOP boot detected (cookie: 0x%x)\n", *boot_cookie);
+
+	ret = cmd_db_init(CMD_DB_BASE_ADDR, CMD_DB_SIZE);
+	if (ret != CB_SUCCESS) {
+		printk(BIOS_ERR, "Failed to initialize Command DB\n");
+		return CB_ERR;
+	}
+
+	rc = rpmh_rsc_init();
+	if (rc) {
+		printk(BIOS_ERR, "Failed to initialize RPMh RSC\n");
+		return CB_ERR;
+	}
+
+	rc = rpmh_regulator_init(&arc_reg, "mmcx.lvl", RPMH_REGULATOR_TYPE_ARC);
+	if (rc) {
+		printk(BIOS_ERR, "Failed to initialize display power rail mmcx ARC regulator\n");
+		return CB_ERR;
+	}
+
+	printk(BIOS_INFO, "ARC regulator initialized successfully\n");
+
+	rc = rpmh_regulator_arc_set_level(&arc_reg, RPMH_REGULATOR_LEVEL_MIN_MM0, true, false);
+	if (rc) {
+		printk(BIOS_ERR, "Failed to set ARC level\n");
+		return CB_ERR;
+	}
+
+	printk(BIOS_INFO, "ARC level was set successfully\n");
+
+	rc = rpmh_bcm_vote("MM0", BCM_MM0_VOTE_VALUE);
+	if (rc) {
+		printk(BIOS_ERR, "Failed to send BCM vote for display bus clock manager MM0\n");
+		return CB_ERR;
+	}
+
+	printk(BIOS_INFO, "BCM vote for MM0 sent successfully\n");
+
+	return CB_SUCCESS;
+}
diff --git a/src/soc/qualcomm/x1p42100/include/soc/addressmap.h b/src/soc/qualcomm/x1p42100/include/soc/addressmap.h
index 1c309a06d4..8b22662e92 100644
--- a/src/soc/qualcomm/x1p42100/include/soc/addressmap.h
+++ b/src/soc/qualcomm/x1p42100/include/soc/addressmap.h
@@ -18,6 +18,12 @@
 #define DISP_PLL1_BASE			0xAF01000
 #define DISP_CC_BASE			0xAF08000
 
+#define RPMH_BASE                       0x17520000
+#define CMD_DB_BASE_ADDR                0x81c60000
+#define CMD_DB_SIZE                     0x20000
+
+#define AOP_BOOT_COOKIE_ADDR            0xC3F0040
+
 #define CBMEM_TOP			0xC7800000
 /* X1P42100 NCC0 PLL CONFIG ADDRESSES */
 #define NCC0_NCC_CMU_NCC_PLL_CFG	0x199A2010
diff --git a/src/soc/qualcomm/x1p42100/include/soc/rpmh_config.h b/src/soc/qualcomm/x1p42100/include/soc/rpmh_config.h
new file mode 100644
index 0000000000..c1f9c4630c
--- /dev/null
+++ b/src/soc/qualcomm/x1p42100/include/soc/rpmh_config.h
@@ -0,0 +1,42 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef _SOC_QUALCOMM_X1P42100_RPMH_CONFIG_H_
+#define _SOC_QUALCOMM_X1P42100_RPMH_CONFIG_H_
+
+#include <types.h>
+
+/*
+ * X1P42100 RPMh RSC Configuration
+ */
+
+#define RPMH_RSC_DRV_ID			2
+
+#define RPMH_TCS_OFFSET			0xd00
+#define RPMH_TCS_DISTANCE		0x2a0
+
+/* TCS Configuration */
+#define RPMH_NUM_ACTIVE_TCS		2
+#define RPMH_NUM_SLEEP_TCS		3
+#define RPMH_NUM_WAKE_TCS		3
+#define RPMH_NUM_CONTROL_TCS		0
+#define RPMH_NUM_FAST_PATH_TCS		0
+
+#define RPMH_NUM_CHANNELS		1
+
+#define RPMH_HW_SOLVER_SUPPORTED	true
+#define RPMH_HW_CHANNEL_MODE		false
+
+#define RPMH_RSC_NAME			"apps_rsc"
+
+#define RPMH_REGULATOR_LEVEL_MIN_MM0	1
+#define RPMH_REGULATOR_LEVEL_TURBO_MM0	6
+
+#define BCM_MM0_VOTE_VALUE		0x60004001
+
+#define AOP_BOOT_COOKIE			0xA0C00C1E
+#define AOP_BOOT_TIMEOUT_US		200000
+
+int rpmh_rsc_init(void);
+enum cb_err display_rpmh_init(void);
+
+#endif /* _SOC_QUALCOMM_X1P42100_RPMH_CONFIG_H_ */
diff --git a/src/soc/qualcomm/x1p42100/rpmh_rsc_init.c b/src/soc/qualcomm/x1p42100/rpmh_rsc_init.c
new file mode 100644
index 0000000000..7ddb3ac10d
--- /dev/null
+++ b/src/soc/qualcomm/x1p42100/rpmh_rsc_init.c
@@ -0,0 +1,165 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+#include <device/device.h>
+#include <console/console.h>
+#include <device/device.h>
+#include <device/mmio.h>
+#include <string.h>
+#include <soc/addressmap.h>
+#include <soc/rpmh_config.h>
+#include <soc/rpmh_internal.h>
+#include <soc/rpmh_rsc.h>
+
+static struct rsc_drv rsc_driver;
+static struct cache_req non_batch_cache[CMD_DB_MAX_RESOURCES];
+
+/**
+ * rpmh_rsc_init - Initialize the RPMh RSC driver
+ *
+ * Initializes the RPMh Resource State Coordinator driver with platform-specific configuration.
+ * Configuration is read from soc/rpmh_config.h for this chipset.
+ *
+ * Return: 0 on success, -1 on failure
+ */
+int rpmh_rsc_init(void)
+{
+	struct rsc_drv *drv = &rsc_driver;
+	u32 rsc_id, major_rsc_version, minor_rsc_version, config, max_tcs, ncpt;
+	int offset;
+	u32 solver_config;
+
+	/* Check if already initialized */
+	if (drv->initialized) {
+		printk(BIOS_INFO, "RPMH RSC: Already initialized, skipping re-initialization\n");
+		return 0;
+	}
+
+	memset(drv, 0, sizeof(*drv));
+
+	/* Set configuration from chipset-specific header */
+	drv->base = (void *)RPMH_BASE;
+	drv->tcs_base = (void *)(RPMH_BASE + RPMH_TCS_OFFSET);
+	drv->tcs_distance = RPMH_TCS_DISTANCE;
+	drv->id = RPMH_RSC_DRV_ID;
+	drv->num_channels = RPMH_NUM_CHANNELS;
+	strncpy(drv->name, RPMH_RSC_NAME, sizeof(drv->name) - 1);
+
+	/* Read hardware version */
+	rsc_id = read32(drv->base);
+	major_rsc_version = (rsc_id >> 16) & 0xFF;
+	minor_rsc_version = (rsc_id >> 8) & 0xFF;
+
+	/* Select register offsets based on version and HW channel mode */
+	if (RPMH_HW_CHANNEL_MODE && major_rsc_version >= 3) {
+		drv->regs = rpmh_rsc_reg_offset_ver_3_0_hw_channel;
+		printk(BIOS_INFO, "RPMH RSC: Using v3.0 HW channel register offsets\n");
+	} else if (major_rsc_version >= 3) {
+		drv->regs = rpmh_rsc_reg_offset_ver_3_0;
+		printk(BIOS_INFO, "RPMH RSC: Using v3.0 register offsets\n");
+	} else {
+		drv->regs = rpmh_rsc_reg_offset_ver_2_7;
+		printk(BIOS_INFO, "RPMH RSC: Using v2.7 register offsets\n");
+	}
+
+	/* Read TCS configuration from hardware */
+	config = read32(drv->base + drv->regs[DRV_PRNT_CHLD_CONFIG]);
+	max_tcs = (config >> (DRV_NUM_TCS_SHIFT * drv->id)) & DRV_NUM_TCS_MASK;
+	ncpt = (config >> DRV_NCPT_SHIFT) & DRV_NCPT_MASK;
+
+	/* Configure TCS groups for Channel 0 - explicit approach */
+	offset = 0;
+	drv->num_tcs = 0;
+
+	if (RPMH_NUM_ACTIVE_TCS > 0) {
+		drv->ch[CH0].tcs[ACTIVE_TCS].drv = drv;
+		drv->ch[CH0].tcs[ACTIVE_TCS].type = ACTIVE_TCS;
+		drv->ch[CH0].tcs[ACTIVE_TCS].num_tcs = RPMH_NUM_ACTIVE_TCS;
+		drv->ch[CH0].tcs[ACTIVE_TCS].ncpt = ncpt;
+		drv->ch[CH0].tcs[ACTIVE_TCS].offset = offset;
+		drv->ch[CH0].tcs[ACTIVE_TCS].mask = ((1 << RPMH_NUM_ACTIVE_TCS) - 1) << offset;
+		offset += RPMH_NUM_ACTIVE_TCS;
+		drv->num_tcs += RPMH_NUM_ACTIVE_TCS;
+		printk(BIOS_DEBUG, "RPMH RSC: ACTIVE TCS: %d TCSes at offset %d (mask=0x%x)\n",
+		       RPMH_NUM_ACTIVE_TCS, drv->ch[CH0].tcs[ACTIVE_TCS].offset,
+		       drv->ch[CH0].tcs[ACTIVE_TCS].mask);
+	}
+
+	if (RPMH_NUM_SLEEP_TCS > 0) {
+		drv->ch[CH0].tcs[SLEEP_TCS].drv = drv;
+		drv->ch[CH0].tcs[SLEEP_TCS].type = SLEEP_TCS;
+		drv->ch[CH0].tcs[SLEEP_TCS].num_tcs = RPMH_NUM_SLEEP_TCS;
+		drv->ch[CH0].tcs[SLEEP_TCS].ncpt = ncpt;
+		drv->ch[CH0].tcs[SLEEP_TCS].offset = offset;
+		drv->ch[CH0].tcs[SLEEP_TCS].mask = ((1 << RPMH_NUM_SLEEP_TCS) - 1) << offset;
+		offset += RPMH_NUM_SLEEP_TCS;
+		drv->num_tcs += RPMH_NUM_SLEEP_TCS;
+		printk(BIOS_DEBUG, "RPMH RSC: SLEEP TCS: %d TCSes at offset %d (mask=0x%x)\n",
+		       RPMH_NUM_SLEEP_TCS, drv->ch[CH0].tcs[SLEEP_TCS].offset,
+		       drv->ch[CH0].tcs[SLEEP_TCS].mask);
+	}
+
+	if (RPMH_NUM_WAKE_TCS > 0) {
+		drv->ch[CH0].tcs[WAKE_TCS].drv = drv;
+		drv->ch[CH0].tcs[WAKE_TCS].type = WAKE_TCS;
+		drv->ch[CH0].tcs[WAKE_TCS].num_tcs = RPMH_NUM_WAKE_TCS;
+		drv->ch[CH0].tcs[WAKE_TCS].ncpt = ncpt;
+		drv->ch[CH0].tcs[WAKE_TCS].offset = offset;
+		drv->ch[CH0].tcs[WAKE_TCS].mask = ((1 << RPMH_NUM_WAKE_TCS) - 1) << offset;
+		offset += RPMH_NUM_WAKE_TCS;
+		drv->num_tcs += RPMH_NUM_WAKE_TCS;
+		printk(BIOS_DEBUG, "RPMH RSC: WAKE TCS: %d TCSes at offset %d (mask=0x%x)\n",
+		       RPMH_NUM_WAKE_TCS, drv->ch[CH0].tcs[WAKE_TCS].offset,
+		       drv->ch[CH0].tcs[WAKE_TCS].mask);
+	}
+
+	/* Check if total TCS count exceeds hardware limit */
+	if (drv->num_tcs > max_tcs) {
+		printk(BIOS_ERR, "RPMH RSC: TCS config exceeds hardware limit (configured: %d, max: %d)\n",
+				drv->num_tcs, max_tcs);
+		return -1;
+	}
+
+	drv->ch[CH0].drv = drv;
+	drv->ch[CH0].initialized = true;
+	drv->client.non_batch_cache = non_batch_cache;
+	drv->client.non_batch_cache_idx = 0;
+
+	for (int i = 0; i < CMD_DB_MAX_RESOURCES; i++) {
+		non_batch_cache[i].addr = 0;
+		non_batch_cache[i].sleep_val = UINT_MAX;
+		non_batch_cache[i].wake_val = UINT_MAX;
+	}
+
+	/* Initialize TCS in-use bitmap */
+	memset(drv->tcs_in_use, 0, sizeof(drv->tcs_in_use));
+
+	/* Detect solver mode from hardware */
+	solver_config = read32(drv->base + drv->regs[DRV_SOLVER_CONFIG]);
+	solver_config = (solver_config >> 24) & 0x1;
+
+	if (solver_config || RPMH_HW_SOLVER_SUPPORTED) {
+		drv->client.flags |= SOLVER_PRESENT;
+		printk(BIOS_INFO, "RPMH RSC: Hardware solver mode supported\n");
+
+		if (RPMH_HW_CHANNEL_MODE) {
+			drv->client.flags |= HW_CHANNEL_PRESENT;
+			drv->in_solver_mode = true;
+			drv->client.in_solver_mode = true;
+			printk(BIOS_INFO, "RPMH RSC: HW channel mode enabled\n");
+		} else {
+			drv->in_solver_mode = false;
+			drv->client.in_solver_mode = false;
+			printk(BIOS_INFO, "RPMH RSC: Software control mode\n");
+		}
+	} else {
+		printk(BIOS_INFO, "RPMH RSC: Hardware solver mode not supported\n");
+	}
+
+	drv->initialized = true;
+
+	rpmh_set_rsc_drv(drv);
+
+	printk(BIOS_INFO, "RPMH RSC: Initialized %s (drv-%d) at 0x%lx Version %d.%d\n",
+	       drv->name, drv->id, (uintptr_t)drv->base, major_rsc_version, minor_rsc_version);
+
+	return 0;
+}

From e1e7b9b20374fc3b1406d43e7b1ab2b0859f919f Mon Sep 17 00:00:00 2001
From: Swathi Tamilselvan <tswathi@qualcomm.corp-partner.google.com>
Date: Mon, 15 Dec 2025 14:54:16 +0530
Subject: [PATCH 2963/3886] soc/qualcomm/x1p42100: Add API to enable display
 clocks

Add API to enable the essential display clocks required for display
subsystem initialization.

Test=1. Build and boot on X1P42100.

Change-Id: Ifc634f2c00eb933bf03b898e132ab5bf137149f8
Signed-off-by: Swathi Tamilselvan <tswathi@qualcomm.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90468
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
---
 src/soc/qualcomm/x1p42100/clock.c             | 67 +++++++++++++++++++
 src/soc/qualcomm/x1p42100/display/disp.c      | 56 ++++++++++++++++
 src/soc/qualcomm/x1p42100/include/soc/clock.h |  7 ++
 3 files changed, 130 insertions(+)

diff --git a/src/soc/qualcomm/x1p42100/clock.c b/src/soc/qualcomm/x1p42100/clock.c
index 377f529a08..c2566c5d5b 100644
--- a/src/soc/qualcomm/x1p42100/clock.c
+++ b/src/soc/qualcomm/x1p42100/clock.c
@@ -294,6 +294,26 @@ static u32 *usb_sec_cbcr[USB_SEC_CLK_COUNT] = {
 	[USB_SEC_SYS_NOC_USB_AXI_CBCR] = &gcc->gcc_sys_noc_usb_axi_cbcr,
 };
 
+static u32 *disp_gdsc[MAX_DISP_GDSC] = {
+	[DISP_CC_CORE_GDSC] = &disp_cc->mdss_core_gdscr,
+};
+
+static u32 *mdss_cbcr[MDSS_CLK_COUNT] = {
+	[GCC_DISP_AHB_CBCR] = &gcc->gcc_disp_ahb_cbcr,
+	[GCC_DISP_XO_CBCR] = &gcc->gcc_disp_xo_cbcr,
+	[GCC_DISP_HF_AXI_CBCR] = &gcc->gcc_disp_hf_axi_cbcr,
+	[DISP_CC_MDSS_AHB_CBCR] = &disp_cc->mdss_ahb_cbcr,
+	[DISP_CC_MDSS_MDP_CBCR] = &disp_cc->mdss_mdp_cbcr,
+	[DISP_CC_MDSS_VSYNC_CBCR] = &disp_cc->mdss_vsync_cbcr,
+	[DISP_CC_MDSS_RSCC_AHB_CBCR] = &disp_cc->mdss_rscc_ahb_cbcr,
+	[DISP_CC_MDSS_RSCC_VSYNC_CBCR] = &disp_cc->mdss_rscc_vsync_cbcr,
+	[DISP_CC_XO_CBCR] = &disp_cc->xo_cbcr,
+	[DISP_CC_MDSS_DPTX3_PIXEL0_CBCR] = &disp_cc->mdss_dptx3_pixel0_cbcr,
+	[DISP_CC_MDSS_DPTX3_LINK_CBCR] = &disp_cc->mdss_dptx3_link_cbcr,
+	[DISP_CC_MDSS_DPTX3_AUX_CBCR] = &disp_cc->mdss_dptx3_aux_cbcr,
+	[DISP_CC_MDSS_DPTX3_LINK_INTF_CBCR] = &disp_cc->mdss_dptx3_link_intf_cbcr,
+};
+
 static struct clock_freq_config pcie_core_cfg[] = {
 	{
 		.hz = 100 * MHz,
@@ -500,6 +520,14 @@ enum cb_err clock_enable_usb_gdsc(enum clk_usb_gdsc gdsc_type)
 	return enable_and_poll_gdsc_status(usb_gdsc[gdsc_type]);
 }
 
+enum cb_err clock_enable_disp_gdsc(enum clk_disp_gdsc gdsc_type)
+{
+	if (gdsc_type >= MAX_DISP_GDSC)
+		return CB_ERR;
+
+	return enable_and_poll_gdsc_status(disp_gdsc[gdsc_type]);
+}
+
 enum cb_err usb_clock_enable(enum clk_usb clk_type)
 {
 	if (clk_type >= USB_CLK_COUNT)
@@ -623,6 +651,45 @@ static enum cb_err pll_init_and_set(struct x1p42100_ncc0_clock *ncc0, u32 l_val)
 	return CB_SUCCESS;
 }
 
+enum cb_err disp_pll_init_and_set(struct x1p42100_disp_pll_clock *disp_pll, u32 l_val, u32 alpha_val)
+{
+	int ret;
+	struct alpha_pll_reg_val_config disp_pll_cfg = {0};
+
+	disp_pll_cfg.reg_l = &disp_pll->pll_l;
+	disp_pll_cfg.l_val = l_val;
+
+	disp_pll_cfg.reg_alpha = &disp_pll->pll_alpha;
+	disp_pll_cfg.alpha_val = alpha_val;
+
+	disp_pll_cfg.reg_user_ctl = &disp_pll->pll_user_ctl;
+	disp_pll_cfg.user_ctl_val = 0x1;
+
+	clock_configure_enable_gpll(&disp_pll_cfg, false, 0);
+
+	disp_pll_cfg.reg_mode = &disp_pll->pll_mode;
+	disp_pll_cfg.reg_opmode = &disp_pll->pll_opmode;
+	ret = lucidole_pll_enable(&disp_pll_cfg);
+	if (ret != CB_SUCCESS)
+		return CB_ERR;
+
+	return CB_SUCCESS;
+}
+
+enum cb_err mdss_clock_enable(enum clk_mdss clk_type)
+{
+	if (clk_type >= MDSS_CLK_COUNT)
+		return CB_ERR;
+
+	/* Enable clock */
+	return clock_enable(mdss_cbcr[clk_type]);
+}
+
+void enable_disp_clock_tcsr(void)
+{
+	write32(TCSR_GCC_EDP_CLKREF_EN_ADDR, 0x1);
+}
+
 static void speed_up_boot_cpu(void)
 {
 	/* 1363.2 MHz */
diff --git a/src/soc/qualcomm/x1p42100/display/disp.c b/src/soc/qualcomm/x1p42100/display/disp.c
index f09adab34f..f4a999ec80 100644
--- a/src/soc/qualcomm/x1p42100/display/disp.c
+++ b/src/soc/qualcomm/x1p42100/display/disp.c
@@ -4,12 +4,68 @@
 #include <console/console.h>
 #include <timer.h>
 #include <soc/addressmap.h>
+#include <soc/clock.h>
 #include <soc/cmd_db.h>
 #include <soc/rpmh.h>
 #include <soc/rpmh_bcm.h>
 #include <soc/rpmh_config.h>
 #include <soc/rpmh_regulator.h>
 
+static struct clock_freq_config disp_cc_mdss_ahb_cfg[] = {
+	{
+		.hz = SRC_XO_HZ,        /* 19.2MHz */
+		.src = SRC_XO_19_2MHZ_AHB,
+		.div = QCOM_CLOCK_DIV(1),
+	},
+	{
+		.hz = CLK_37_5MHZ,
+		.src = SRC_DISP_CC_PLL1_MAIN_AHB,
+		.div = QCOM_CLOCK_DIV(16),
+	},
+	{
+		.hz = CLK_75MHZ,
+		.src = SRC_DISP_CC_PLL1_MAIN_AHB,
+		.div = QCOM_CLOCK_DIV(8),
+	},
+};
+
+static struct clock_freq_config disp_cc_mdss_mdp_cfg[] = {
+	{
+		.hz = CLK_575MHZ,
+		.src = SRC_DISP_CC_PLL0_MAIN_MDP,
+		.div = QCOM_CLOCK_DIV(3),
+	},
+	{
+		.hz = CLK_400MHZ,
+		.src = SRC_DISP_CC_PLL1_MAIN_MDP,
+		.div = QCOM_CLOCK_DIV(1.5),
+	},
+};
+
+void enable_mdss_clk(void)
+{
+	/*
+	 * Display clock initialization sequence
+	 * 1. Enable GCC clocks (AHB, AXI) - GCC clocks that are required for display
+	 * 2. Enable GDSC (power domain) - powers up the display subsystem
+	 * 3. Initialize display PLLs - required to use clock sources from disp_cc domain
+	 * 4. Configure and enable disp_cc clocks - enable display clocks
+	 */
+	mdss_clock_enable(GCC_DISP_AHB_CBCR);
+	clock_enable_disp_gdsc(DISP_CC_CORE_GDSC);
+	mdss_clock_enable(GCC_DISP_HF_AXI_CBCR);
+	disp_pll_init_and_set(apss_disp_pll0, L_VAL_1725MHz, DISP_PLL0_ALPHA_VAL);
+	disp_pll_init_and_set(apss_disp_pll1, L_VAL_600MHz, DISP_PLL1_ALPHA_VAL);
+	clock_configure(&disp_cc->mdss_ahb_rcg,
+		disp_cc_mdss_ahb_cfg, CLK_75MHZ, ARRAY_SIZE(disp_cc_mdss_ahb_cfg));
+	mdss_clock_enable(DISP_CC_MDSS_AHB_CBCR);
+	clock_configure(&disp_cc->mdss_mdp_rcg,
+		disp_cc_mdss_mdp_cfg, CLK_575MHZ, ARRAY_SIZE(disp_cc_mdss_mdp_cfg));
+	mdss_clock_enable(DISP_CC_MDSS_MDP_CBCR);
+	mdss_clock_enable(DISP_CC_MDSS_VSYNC_CBCR);
+	enable_disp_clock_tcsr();
+}
+
 /**
  * display_rpmh_init() - Initialize RPMh for display power management
  *
diff --git a/src/soc/qualcomm/x1p42100/include/soc/clock.h b/src/soc/qualcomm/x1p42100/include/soc/clock.h
index da082f66bd..73378ce59e 100644
--- a/src/soc/qualcomm/x1p42100/include/soc/clock.h
+++ b/src/soc/qualcomm/x1p42100/include/soc/clock.h
@@ -16,6 +16,7 @@
 #define CLK_400MHZ		(400 * MHz)
 #define CLK_75MHZ		(75 * MHz)
 #define CLK_575MHZ		(575 * MHz)
+#define CLK_37_5MHZ		(37.5 * MHz)
 
 /* CPU PLL*/
 #define L_VAL_1363P2MHz		0x47
@@ -745,14 +746,20 @@ void clock_enable_qup(int qup);
 void clock_configure_dfsr(int qup);
 void clock_configure_pcie(void);
 void clock_configure_usb(void);
+void enable_disp_clock_tcsr(void);
+void enable_mdss_clk(void);
 enum cb_err clock_enable_gdsc(enum clk_gdsc gdsc_type);
 enum cb_err clock_enable_pcie(enum clk_pcie clk_type);
 enum cb_err clock_configure_mux(enum clk_pcie clk_type, u32 src_type);
 enum cb_err usb_clock_configure_mux(enum clk_pipe_usb clk_type, u32 src_type);
 enum cb_err usb_clock_enable(enum clk_usb clk_type);
 enum cb_err clock_enable_usb_gdsc(enum clk_usb_gdsc gdsc_type);
+enum cb_err clock_enable_disp_gdsc(enum clk_disp_gdsc gdsc_type);
 enum cb_err usb_prim_clock_enable(enum clk_usb_prim clk_type);
 enum cb_err usb_sec_clock_enable(enum clk_usb_sec clk_type);
+enum cb_err mdss_clock_enable(enum clk_mdss clk_type);
+enum cb_err disp_pll_init_and_set(struct x1p42100_disp_pll_clock *disp_pll,
+		u32 l_val, u32 alpha_val);
 void clock_configure_dfsr_table_x1p42100(int qup, struct clock_freq_config *clk_cfg,
 		uint32_t num_perfs);
 

From 0c26c4494d754cbb649a1789b15208267f9253df Mon Sep 17 00:00:00 2001
From: Swathi Tamilselvan <tswathi@qualcomm.corp-partner.google.com>
Date: Mon, 15 Dec 2025 16:00:33 +0530
Subject: [PATCH 2964/3886] mainboard/google/bluey: Enable display clocks and
 MMCX power rail
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Add support to enable MMCX power rail and vote for MM0 BCM resource
required for display. This change includes support to enable display
clocks.

TEST= 1. Create an image.serial.bin and ensure it boots on X1P42100.
2. Verified MMCX rail enablement and MM0 BCM vote using ARC and
BCM AOP dump.
Serial Log:
[INFO ]  RPMH_REG: Initialized mmcx.lvl at addr=0x30080
[INFO ]  ARC regulator initialized successfully
[DEBUG]  RPMH_REG: Sent active request for mmcx.lvl
[INFO ]  ARC level has been set successfully
[DEBUG]  BCM: Found address 0x00050024 for resource MM0
[INFO ]  BCM: Successfully voted for MM0 (addr=0x00050024, val=0x60004001)
[INFO ]  BCM vote for MM0 sent successfully
3. Verified if the clocks are enabled by taking clock dump. Clock
enablement is verified by dumping the 31st bit of the corresponding
clock’s CBCR register. A value of 0 in bit 31 indicates that the clock
is ON. The register details are part of HRD-X1P42100-S1 document.
https://docs.qualcomm.com/bundle/resource/topics/HRD-X1P42100-S1/

Change-Id: I89715fb4e3a6122388068a819e24cb409e204155
Signed-off-by: Swathi Tamilselvan <tswathi@qualcomm.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90507
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/google/bluey/mainboard.c | 8 +++++++-
 1 file changed, 7 insertions(+), 1 deletion(-)

diff --git a/src/mainboard/google/bluey/mainboard.c b/src/mainboard/google/bluey/mainboard.c
index e18f492764..9f958a1862 100644
--- a/src/mainboard/google/bluey/mainboard.c
+++ b/src/mainboard/google/bluey/mainboard.c
@@ -9,10 +9,12 @@
 #include <device/device.h>
 #include <ec/google/chromeec/ec.h>
 #include <gpio.h>
+#include <soc/clock.h>
 #include <soc/pcie.h>
 #include <soc/qupv3_config_common.h>
 #include <soc/qup_se_handlers_common.h>
 #include "board.h"
+#include <soc/rpmh_config.h>
 #include <soc/usb/usb.h>
 
 /*
@@ -87,7 +89,11 @@ static void display_startup(void)
 		return;
 	}
 
-	/* TODO: add logic for display init */
+	/* Initialize RPMh subsystem and display power rails */
+	if (display_rpmh_init() != CB_SUCCESS)
+		return;
+
+	enable_mdss_clk();
 }
 
 static void mainboard_init(struct device *dev)

From f8c10eda36bde8e8ce06242d2f8551dd866ece02 Mon Sep 17 00:00:00 2001
From: Yunlong Jia <yunlong.jia@ecs.corp-partner.google.com>
Date: Wed, 31 Dec 2025 09:02:47 +0000
Subject: [PATCH 2965/3886] mb/google/nissa/var/gothrax: Add Rayson parts to
 RAM ID table

Add the support RAM parts for gothrax.
Here is the ram part number list:
DRAM Part Name                 ID to assign
MT62F512M32D2DR-031 WT:B       0 (0000)
H58G56AK6BX069                 1 (0001)
K3LKBKB0BM-MGCP                2 (0010)
H9JCNNNBK3MLYR-N6E             0 (0000)
H9JCNNNCP3MLYR-N6E             3 (0011)
K3KL8L80CM-MGCT                4 (0100)
RS1G32LO5D2FDB-23BT            5 (0101)

BUG=b:472596025
BRANCH=None
TEST=emerge-nissa coreboot

Signed-off-by: Yunlong Jia <yunlong.jia@ecs.corp-partner.google.com>
Change-Id: Iff12898dd6fb08a7e932de6e1902886a6f251761
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90663
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
---
 src/mainboard/google/brya/variants/gothrax/memory/Makefile.mk    | 1 +
 .../google/brya/variants/gothrax/memory/dram_id.generated.txt    | 1 +
 .../google/brya/variants/gothrax/memory/mem_parts_used.txt       | 1 +
 3 files changed, 3 insertions(+)

diff --git a/src/mainboard/google/brya/variants/gothrax/memory/Makefile.mk b/src/mainboard/google/brya/variants/gothrax/memory/Makefile.mk
index c323ea6ae6..44065b51d0 100644
--- a/src/mainboard/google/brya/variants/gothrax/memory/Makefile.mk
+++ b/src/mainboard/google/brya/variants/gothrax/memory/Makefile.mk
@@ -9,3 +9,4 @@ SPD_SOURCES += spd/lp5/set-0/spd-3.hex      # ID = 1(0b0001)  Parts = H58G56AK6B
 SPD_SOURCES += spd/lp5/set-0/spd-3.hex      # ID = 2(0b0010)  Parts = K3LKBKB0BM-MGCP
 SPD_SOURCES += spd/lp5/set-0/spd-2.hex      # ID = 3(0b0011)  Parts = H9JCNNNCP3MLYR-N6E
 SPD_SOURCES += spd/lp5/set-0/spd-7.hex      # ID = 4(0b0100)  Parts = K3KL8L80CM-MGCT
+SPD_SOURCES += spd/lp5/set-0/spd-11.hex      # ID = 5(0b0101)  Parts = RS1G32LO5D2FDB-23BT
diff --git a/src/mainboard/google/brya/variants/gothrax/memory/dram_id.generated.txt b/src/mainboard/google/brya/variants/gothrax/memory/dram_id.generated.txt
index 8892ad8cb6..9848a35a35 100644
--- a/src/mainboard/google/brya/variants/gothrax/memory/dram_id.generated.txt
+++ b/src/mainboard/google/brya/variants/gothrax/memory/dram_id.generated.txt
@@ -10,3 +10,4 @@ K3LKBKB0BM-MGCP                2 (0010)
 H9JCNNNBK3MLYR-N6E             0 (0000)
 H9JCNNNCP3MLYR-N6E             3 (0011)
 K3KL8L80CM-MGCT                4 (0100)
+RS1G32LO5D2FDB-23BT            5 (0101)
diff --git a/src/mainboard/google/brya/variants/gothrax/memory/mem_parts_used.txt b/src/mainboard/google/brya/variants/gothrax/memory/mem_parts_used.txt
index bb85c55f8b..baf0ab19af 100644
--- a/src/mainboard/google/brya/variants/gothrax/memory/mem_parts_used.txt
+++ b/src/mainboard/google/brya/variants/gothrax/memory/mem_parts_used.txt
@@ -16,3 +16,4 @@ K3LKBKB0BM-MGCP,
 H9JCNNNBK3MLYR-N6E,
 H9JCNNNCP3MLYR-N6E,
 K3KL8L80CM-MGCT,
+RS1G32LO5D2FDB-23BT,

From b2b1eb3c5a252dd5831a5fa39b45e771c810c88e Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Micha=C5=82=20=C5=BBygowski?= <michal.zygowski@3mdeb.com>
Date: Mon, 6 Oct 2025 14:16:36 +0200
Subject: [PATCH 2966/3886] soc/amd/common/block/smn: Add simple SMN I/O
 accessors
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Add PCI I/O-based SMN accessors. These accessors can be used for
early workarounds when the PCI ECAM MMCONF is not working yet.
An example of such workaround is the patching of PCI ECAM MMCONF
base address in Turin SoC, which has to be done via SMN, but it
cannot use PCI ECAM MMCONF to access SMN yet.

Change-Id: I5e0faaa48e4d7b4479e3af9b795ad2a879f569fd
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89471
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
---
 .../amd/common/block/include/amdblocks/smn.h  |  8 +++++++
 src/soc/amd/common/block/smn/smn.c            | 22 +++++++++++++++++++
 2 files changed, 30 insertions(+)

diff --git a/src/soc/amd/common/block/include/amdblocks/smn.h b/src/soc/amd/common/block/include/amdblocks/smn.h
index 0268926bbe..ad6972114e 100644
--- a/src/soc/amd/common/block/include/amdblocks/smn.h
+++ b/src/soc/amd/common/block/include/amdblocks/smn.h
@@ -9,4 +9,12 @@ uint32_t smn_read32(uint32_t reg);
 uint64_t smn_read64(uint32_t reg);
 void smn_write32(uint32_t reg, uint32_t val);
 
+#if defined(__SIMPLE_DEVICE__)
+
+uint32_t smn_io_read32(uint32_t reg);
+uint64_t smn_io_read64(uint32_t reg);
+void smn_io_write32(uint32_t reg, uint32_t val);
+
+#endif
+
 #endif /* AMD_BLOCK_SMN_H */
diff --git a/src/soc/amd/common/block/smn/smn.c b/src/soc/amd/common/block/smn/smn.c
index caf6a41004..41396701e2 100644
--- a/src/soc/amd/common/block/smn/smn.c
+++ b/src/soc/amd/common/block/smn/smn.c
@@ -25,3 +25,25 @@ void smn_write32(uint32_t reg, uint32_t val)
 	pci_write_config32(SOC_GNB_DEV, SMN_INDEX_ADDR, reg);
 	pci_write_config32(SOC_GNB_DEV, SMN_DATA_ADDR, val);
 }
+
+
+#if defined(__SIMPLE_DEVICE__)
+
+uint32_t smn_io_read32(uint32_t reg)
+{
+	pci_io_write_config32(SOC_GNB_DEV, SMN_INDEX_ADDR, reg);
+	return pci_io_read_config32(SOC_GNB_DEV, SMN_DATA_ADDR);
+}
+
+uint64_t smn_io_read64(uint32_t reg)
+{
+	return smn_io_read32(reg) | (uint64_t)smn_io_read32(reg + 4) << 32;
+}
+
+void smn_io_write32(uint32_t reg, uint32_t val)
+{
+	pci_io_write_config32(SOC_GNB_DEV, SMN_INDEX_ADDR, reg);
+	pci_io_write_config32(SOC_GNB_DEV, SMN_DATA_ADDR, val);
+}
+
+#endif

From ba0483c94a118f32c750d8ebfbed9efd0b58810f Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Micha=C5=82=20=C5=BBygowski?= <michal.zygowski@3mdeb.com>
Date: Thu, 4 Dec 2025 14:49:52 +0100
Subject: [PATCH 2967/3886] soc/amd/common/Makefile.mk: Strip quotes from
 AMDFW_CONFIG_FILE
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Strip quotes from CONFIG_AMDFW_CONFIG_FILE, otherwise the IF condition
may not catch the case when CONFIG_AMDFW_CONFIG_FILE is an empty string.

TEST=Omit PSP blobs when building coreboot for Gigabyte MZ33-AR1 by
clearing the AMDFW_CONFIG_FILE path.

Change-Id: I1ecf61844c03c89b3429e23936172f79c8d4b2f4
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90367
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
---
 src/soc/amd/common/Makefile.mk | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/soc/amd/common/Makefile.mk b/src/soc/amd/common/Makefile.mk
index 5d41968493..dbf655737f 100644
--- a/src/soc/amd/common/Makefile.mk
+++ b/src/soc/amd/common/Makefile.mk
@@ -11,7 +11,7 @@ ifneq ($(V),)
 OPT_DEBUG_AMDFWTOOL = --debug
 endif
 
-ifneq ($(CONFIG_AMDFW_CONFIG_FILE), )
+ifneq ($(call strip_quotes, $(CONFIG_AMDFW_CONFIG_FILE)),)
 FIRMWARE_LOCATION=$(shell grep -e FIRMWARE_LOCATION $(CONFIG_AMDFW_CONFIG_FILE) | awk '{print $$2}')
 
 # Add all the files listed in the config file to the dependency list
@@ -77,7 +77,7 @@ amdfwread-range-cmd = $(shell ( \
 ))
 endif # ifeq ($(CONFIG_VBOOT_GSCVD),y)
 
-endif # ifneq ($(CONFIG_AMDFW_CONFIG_FILE), )
+endif # ifneq ($(call strip_quotes, $(CONFIG_AMDFW_CONFIG_FILE)),)
 
 MAINBOARD_BLOBS_DIR := $(call strip_quotes, $(CONFIG_APCB_BLOBS_DIR))
 

From cf280eaa7f6cb6b2de17f8e879e2cb6b73965798 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Micha=C5=82=20=C5=BBygowski?= <michal.zygowski@3mdeb.com>
Date: Thu, 4 Dec 2025 14:52:21 +0100
Subject: [PATCH 2968/3886] amdblocks/root_complex.h: Add new IOHC base
 addresses
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Starting with Turin there are 8 IOHCs per SoC. Add new definitions
for the missing IOHCs. Based on Turin C1 PPR (doc 57238).

Change-Id: I31e93e680e3f0ba03d2595f632d6827b4e3042b8
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90368
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/soc/amd/common/block/include/amdblocks/root_complex.h | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/src/soc/amd/common/block/include/amdblocks/root_complex.h b/src/soc/amd/common/block/include/amdblocks/root_complex.h
index bfabf973a7..c60872aa2a 100644
--- a/src/soc/amd/common/block/include/amdblocks/root_complex.h
+++ b/src/soc/amd/common/block/include/amdblocks/root_complex.h
@@ -11,6 +11,11 @@
 #define SMN_IOHC_MISC_BASE_13D1	0x13d10000
 #define SMN_IOHC_MISC_BASE_13E1	0x13e10000
 
+#define SMN_IOHC_MISC_BASE_1D41	0x1d410000
+#define SMN_IOHC_MISC_BASE_1D51	0x1d510000
+#define SMN_IOHC_MISC_BASE_1D61	0x1d610000
+#define SMN_IOHC_MISC_BASE_1D71	0x1d710000
+
 #define IOHC_MMIO_EN	BIT(0)
 
 #define NON_PCI_RES_IDX_AUTO	0

From 17b36286c894dbaa72b9d278c47a5ffd429d3f92 Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Mon, 29 Dec 2025 08:39:03 -0600
Subject: [PATCH 2969/3886] mb/google/hatch/var/kindred: Drop VBT for KLED
 variant

The KLED VBT file is misconfigured and results in an error under Linux:

    [drm] ERROR VBT has malformed LFP data table pointers

Inspecting the VBT using the Intel BMP tool reveals invalid data for
many of the panel definitions, as well as other settings.

KLED works perfectly fine with the kindred VBT, so use that instead.

TEST=build/boot Win11/Linux on KLED, verify display output works
properly.

Change-Id: I09aaa5c17517633fdae508239ecf8e72e3990e33
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90637
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 .../google/hatch/variants/kindred/Makefile.mk    |   2 --
 .../google/hatch/variants/kindred/kled-data.vbt  | Bin 4612 -> 0 bytes
 .../google/hatch/variants/kindred/variant.c      |  11 -----------
 3 files changed, 13 deletions(-)
 delete mode 100644 src/mainboard/google/hatch/variants/kindred/kled-data.vbt

diff --git a/src/mainboard/google/hatch/variants/kindred/Makefile.mk b/src/mainboard/google/hatch/variants/kindred/Makefile.mk
index 767e119dbc..1676fd9798 100644
--- a/src/mainboard/google/hatch/variants/kindred/Makefile.mk
+++ b/src/mainboard/google/hatch/variants/kindred/Makefile.mk
@@ -12,5 +12,3 @@ SPD_SOURCES += 16G_3200   # 0b111
 bootblock-y += gpio.c
 ramstage-y += gpio.c
 ramstage-y += variant.c
-
-$(call add_vbt_to_cbfs, vbt-kled.bin, kled-data.vbt)
diff --git a/src/mainboard/google/hatch/variants/kindred/kled-data.vbt b/src/mainboard/google/hatch/variants/kindred/kled-data.vbt
deleted file mode 100644
index f07cb69c062a52918f8fbbf02c6d9474579ef699..0000000000000000000000000000000000000000
GIT binary patch
literal 0
HcmV?d00001

literal 4612
zcmeHKU2GIp6h5=l{kt=>ot+Zdu2>Jyz;2;sw!n(D#M$l^yL8KLyQL}7qy=_?hK1Jt
zXfc?sNuxX{*#|UeQ2IhtUc@Kk8@?D46D2XxCnF{%D85MK#el45?o59y!7dn33}@%u
zbMBdYzd7gro~`d|>&0y6u2ihE9c{{i4rlynDsQE>WI8*Li1o$>+EVFwC;kYJz_|bB
z6@Z)|)XEWEk0cL|=L?~pFu|s<Yk1F4A-^G!A3HccJc5~c5@UP!<_r1J-Q)QjX8WFr
zp^2%mwuzxa4tGo(+LIq`K?2gLHAXfyZQO(y+0aan9@$K)-V%wnY<^N<iS~H9E0avc
zdXwoLnC`(uG8@Zg+q>FQyD-y}?nt&Jd)pHVn+qd8JaS}oX#at648_CPOy6kapxkAQ
z508#CVXRQV9<$9D_T<O%qc7xhO$swX&V#2)01%u|ZGZrOGy`}RJXHYJV*t=YL~qGr
z>D-`#W2@jG+gcB}0^DR51TS*c0GzWUb^rVTsH#WvT1Gd0o-_ee0ZoP1kUn8GtGAoc
zhaJ2F3dj|+Ez*yO(4uxT64pm`0WF0$Q>|vuVK<Y^x=Hw#X54hY3y~tZ@e+O2jED=t
zBmkeF!*OpNq{R>%6&>)ZxCI)jE`aVu$a+=SM|_0%YbS&6h%XagCB9DVbTOzVt|eYg
z+(`Tcag4Z=cqj1y@er|V0&bKYMWC4=DhjsrTN2bNI39-LDcgR^wtIi2Nhe~qlx)e3
z6%^&N+YL9%Uk0FD_G~phFbILd77{j6hb>cFiekpD_mVWns^6}c%ibJS9ejb@tMV)n
z`vT@RUb#FQ<AbWnHL#s_qv&a!UcqD82~a+*h%gDvPutBVO`ctt+_3CDa0RVb?$+5h
zi{-!hCTN}xkILdjH-n4rYr?Ub|E6Y+nYzT!8dq9i_R(O~AC?bC;Lb*1MF)K2Etc@o
zW2$FxmDRWI?ktZ#M{CyMp@YK!BvpnE2tfc6P!G#s5HdW+^4OR40yir&Awo63-WT*-
zq=xDUd~A^sz&xNWWB3G!`x(B$w9|}z$nYzs{lM5S4E>U}T4Ie7W+g2zv0(|{l(hFH
z_OXQDO4`p7`%S`HSz9Nw%`!eKYlmd^qKxm#+D9_`RL1XR?W)YK%eYd}HY#kZf_oKh
zLSa)1o>8<<6!w{dmlf@Ig^4~4`?RNgtlftPecH=D_L@&=(40lbC86l|@f^i7D%1JY
z?~u8?Ca5Hx)obZCymextQ-XB_$SC$ZmPVMVMu_yUz)*3SH6(S>DeGdS`Jy9#X@p!Y
z7%^C*2aZK8gg|skv{EZ_6RJ#vR!XpLABElkC%Zv6^pTo5AE=|L%ahJvMF^AF9aIf<
z0fJC+-T}e~8zwJx2iF+=C+B?-N-mCIxXxAJL&wvGzUN%CVVs{wa9Np>+~=%hB=@cC
zJKGI)`nHli7v@No`29+*R5A`nn@Tf-!8$`ndoE};t4chRm5c65q6oDXXGYGgCWHnv
zb^t<fmUu2B&p4+mSP$=nXD)V6uhKJbFP}pYfv3^3;i?2dZ!j(lPUrMMx0N@VK8Um&
ziSBkyas<UfaAE~fTnWNV2AAuy9-oh*MEj9^D7v@s^<XaY+plUzOEK{LmPVt$aegjD
zsJ48de?Uv`i?9KMMW`86RsXyXbdZ`pq_$-SGP@7w3p;in%Kr~4R)Bw3u6qSs+b>Wq
zf7UL466f`W_J5$47m;HTt&hU%+sMfzW%oPj0?WaA;VmFXX8TcI%*nNgnsfn<&C!FQ
XT9YyR=jFc3jpngs9ssn<?jijNQ1;p)

diff --git a/src/mainboard/google/hatch/variants/kindred/variant.c b/src/mainboard/google/hatch/variants/kindred/variant.c
index cf23608f67..e379419c0f 100644
--- a/src/mainboard/google/hatch/variants/kindred/variant.c
+++ b/src/mainboard/google/hatch/variants/kindred/variant.c
@@ -5,7 +5,6 @@
 #include <soc/pci_devs.h>
 #include <ec/google/chromeec/ec.h>
 #include <sar.h>
-#include <drivers/intel/gma/opregion.h>
 #include <static.h>
 
 void variant_devtree_update(void)
@@ -45,13 +44,3 @@ const char *get_wifi_sar_cbfs_filename(void)
 		return "wifi_sar-kled.hex";
 	return WIFI_SAR_CBFS_DEFAULT_FILENAME;
 }
-
-const char *mainboard_vbt_filename(void)
-{
-	uint32_t sku_id = google_chromeec_get_board_sku();
-
-	if (sku_id == 1 || sku_id == 2 || sku_id == 3 || sku_id == 4)
-		return "vbt-kled.bin";
-	else
-		return "vbt.bin";
-}

From 4decc72c23ed8a0d00a5681e5b4500ee4c7ac8f2 Mon Sep 17 00:00:00 2001
From: Cliff Huang <cliff.huang@intel.com>
Date: Mon, 29 Dec 2025 18:09:45 -0800
Subject: [PATCH 2970/3886] drivers/intel/touch: Change ELAN device name for
 Google's Rex touch device

Change Google's Rex touch device name from TH_SENSOR_GOOGLE to
TH_SENSOR_ELAN_REX to better reflect the specific vendor and platform
combination. This provides clearer identification and avoids generic
naming that could cause confusion with other Google touch
implementations.

BUG=none
TEST=This change cannot be tested in isolation as it only contains
naming changes. Testing requires hardware that supports Rex touchscreen
functionality, such as: Fatcat board with Google's specialized cable
connected to a Rex touchscreen. Verify that the new naming convention
works correctly with change:
https://review.coreboot.org/c/coreboot/+/89181 (This change uses the new
naming convention introduced here). Touch functionality should work
identically to before, with only the internal naming updated.

Signed-off-by: Cliff Huang <cliff.huang@intel.com>
Change-Id: I40bb33dee14e9a567ad9dfcf956f3a9cca26dcad
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90645
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kim, Kyoung Il <kyoung.il.kim@intel.com>
---
 src/drivers/intel/touch/chip.h  | 6 +++++-
 src/drivers/intel/touch/elan.h  | 9 +++++----
 src/drivers/intel/touch/touch.c | 2 +-
 3 files changed, 11 insertions(+), 6 deletions(-)

diff --git a/src/drivers/intel/touch/chip.h b/src/drivers/intel/touch/chip.h
index 83b5cd7d37..6e2696ff3f 100644
--- a/src/drivers/intel/touch/chip.h
+++ b/src/drivers/intel/touch/chip.h
@@ -178,8 +178,12 @@ struct intel_thc_hidspi_info {
 enum intel_touch_device {
 	TH_SENSOR_NONE,
 	TH_SENSOR_WACOM,    /* BOM22 for SPI only */
+	/*
+	 * TH_SENSOR_ELAN: the ELAN device for Intel's RVPs (default for ELAN)
+	 * TH_SENSOR_ELAN_REX: the devece used in Google Rex; requires a special cable for Intel's RVP
+	 */
 	TH_SENSOR_ELAN,     /* BOM36 for SPI and BOM37 for I2C */
-	TH_SENSOR_GOOGLE,   /* ELAN9006 for SPI and ELAN6918 for I2C */
+	TH_SENSOR_ELAN_REX, /* ELAN9006 for SPI and ELAN6918 for I2C */
 	TH_SENSOR_HYNITRON, /* NYITRON for I2C only  */
 	TH_SENSOR_GENERIC,  /* for device properity thru devicetree */
 };
diff --git a/src/drivers/intel/touch/elan.h b/src/drivers/intel/touch/elan.h
index 4f7b2a1ee0..baaa56880a 100644
--- a/src/drivers/intel/touch/elan.h
+++ b/src/drivers/intel/touch/elan.h
@@ -32,19 +32,20 @@ static const struct drivers_intel_touch_config elan_touch_config = {
 
 /*
  * ELAN9006 is used for HID-SPI interface, while ELAN6918 is used for HID-I2C
- * interface.
+ * interface; This is Google Rex's touch device and requires a special cable
+ * in Intel's RVP and fatcat.
  */
 
-static const struct drivers_intel_touch_config google_touch_config = {
+static const struct drivers_intel_touch_config elan_rex_touch_config = {
 	.sensor_dev_name = "ELAN Touch Sensor Device",
-	.dev_hidi2c = {	/* Google's I2C-based touch */
+	.dev_hidi2c = {	/* Google Rex's I2C-based touch */
 		.hid				= "ELAN6918",
 		.cid				= "PNP0C50",
 		.intf.hidi2c.addr		= 0x10,
 		.intf.hidi2c.descriptor_address	= 0x1,
 		.intf.hidi2c.connection_speed	= I2C_SPEED_FAST, /* fast mode */
 	},
-	.dev_hidspi = { /* Google's SPI-based touch */
+	.dev_hidspi = { /* Google Rex's SPI-based touch */
 		.hid						= "ELAN9006",
 		.cid						= "PNP0C51",
 		.intf.hidspi.connection_speed			= (32 * MHz), /* unit: Hz */
diff --git a/src/drivers/intel/touch/touch.c b/src/drivers/intel/touch/touch.c
index 85dd7f9159..03738741b8 100644
--- a/src/drivers/intel/touch/touch.c
+++ b/src/drivers/intel/touch/touch.c
@@ -43,7 +43,7 @@ static const struct drivers_intel_touch_config *get_driver_config(const struct d
 	switch (config->connected_device) {
 	case TH_SENSOR_WACOM:    return &wacom_touch_config;
 	case TH_SENSOR_ELAN:     return &elan_touch_config;
-	case TH_SENSOR_GOOGLE:   return &google_touch_config;
+	case TH_SENSOR_ELAN_REX: return &elan_rex_touch_config;
 	case TH_SENSOR_HYNITRON: return &hynitron_touch_config;
 	case TH_SENSOR_GENERIC:  return config;
 	case TH_SENSOR_NONE:     return NULL;

From 82f9c593ab1e25d27ece3ac775e1d209030ce3c4 Mon Sep 17 00:00:00 2001
From: Ziang Wang <wangziang.ok@bytedance.com>
Date: Mon, 20 Oct 2025 20:07:50 +0800
Subject: [PATCH 2971/3886] payloads/libpayload: Add support for RISC-V 64-bit
 architecture

This patch adds config ARCH_RISCV_RV64 to support build of riscv64
payloads. New files under arch/riscv contain:
- Basic ldscript and payload entry point.
- Functions for riscv64 io and cache operations.
- Default timer code based on mtime delegation.
- Default cb_header_ptr passing with device tree to payload.

Change-Id: Ieb3d456d5edda87a3a4886ccfc17a7824c630427
Signed-off-by: Ziang Wang <wangziang.ok@bytedance.com>
Signed-off-by: Dong Wei <weidong.wd@bytedance.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89646
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 payloads/libpayload/Kconfig                   |  10 ++
 payloads/libpayload/Makefile                  |   2 +
 payloads/libpayload/Makefile.mk               |   1 +
 payloads/libpayload/arch/riscv/Kconfig        |   4 +
 payloads/libpayload/arch/riscv/Makefile.mk    |   7 ++
 payloads/libpayload/arch/riscv/cache.c        |  13 +++
 payloads/libpayload/arch/riscv/coreboot.c     |  34 ++++++
 payloads/libpayload/arch/riscv/head.S         |  24 ++++
 .../libpayload/arch/riscv/libpayload.ldscript |  65 +++++++++++
 payloads/libpayload/arch/riscv/main.c         |  53 +++++++++
 payloads/libpayload/arch/riscv/sysinfo.c      |  70 ++++++++++++
 payloads/libpayload/arch/riscv/timer.c        |  53 +++++++++
 payloads/libpayload/arch/riscv/util.S         |  34 ++++++
 payloads/libpayload/arch/riscv/virtual.c      |  36 ++++++
 payloads/libpayload/drivers/Makefile.mk       |   1 +
 payloads/libpayload/drivers/timer/Kconfig     |   6 +
 .../drivers/timer/riscv64_arch_timer.c        |  16 +++
 payloads/libpayload/include/riscv/arch/asm.h  |  23 ++++
 .../libpayload/include/riscv/arch/cache.h     |  21 ++++
 payloads/libpayload/include/riscv/arch/io.h   | 106 ++++++++++++++++++
 .../libpayload/include/riscv/arch/types.h     |  33 ++++++
 .../libpayload/include/riscv/arch/virtual.h   |  14 +++
 src/arch/riscv/boot.c                         |  73 +++++++++++-
 23 files changed, 693 insertions(+), 6 deletions(-)
 create mode 100644 payloads/libpayload/arch/riscv/Kconfig
 create mode 100644 payloads/libpayload/arch/riscv/Makefile.mk
 create mode 100644 payloads/libpayload/arch/riscv/cache.c
 create mode 100644 payloads/libpayload/arch/riscv/coreboot.c
 create mode 100644 payloads/libpayload/arch/riscv/head.S
 create mode 100644 payloads/libpayload/arch/riscv/libpayload.ldscript
 create mode 100644 payloads/libpayload/arch/riscv/main.c
 create mode 100644 payloads/libpayload/arch/riscv/sysinfo.c
 create mode 100644 payloads/libpayload/arch/riscv/timer.c
 create mode 100644 payloads/libpayload/arch/riscv/util.S
 create mode 100644 payloads/libpayload/arch/riscv/virtual.c
 create mode 100644 payloads/libpayload/drivers/timer/riscv64_arch_timer.c
 create mode 100644 payloads/libpayload/include/riscv/arch/asm.h
 create mode 100644 payloads/libpayload/include/riscv/arch/cache.h
 create mode 100644 payloads/libpayload/include/riscv/arch/io.h
 create mode 100644 payloads/libpayload/include/riscv/arch/types.h
 create mode 100644 payloads/libpayload/include/riscv/arch/virtual.h

diff --git a/payloads/libpayload/Kconfig b/payloads/libpayload/Kconfig
index 44d656bcac..9ad454181f 100644
--- a/payloads/libpayload/Kconfig
+++ b/payloads/libpayload/Kconfig
@@ -127,6 +127,15 @@ config ARCH_ARM64
         help
           Support the ARM64 architecture
 
+config ARCH_RISCV_RV64
+        bool "RISCV64"
+        depends on GPL
+        depends on EXPERIMENTAL
+        help
+          Support the RISC-V 64-bit architecture
+          Please note that support for riscv64 payload is experimental at this time, may have
+          fundamental change in the future.
+
 config ARCH_MOCK
         bool "Mock architecture (for unit tests)"
         help
@@ -523,3 +532,4 @@ source "arch/arm/Kconfig"
 source "arch/arm64/Kconfig"
 source "arch/x86/Kconfig"
 source "arch/mock/Kconfig"
+source "arch/riscv/Kconfig"
diff --git a/payloads/libpayload/Makefile b/payloads/libpayload/Makefile
index a8c2641dc6..6ac1e90d26 100644
--- a/payloads/libpayload/Makefile
+++ b/payloads/libpayload/Makefile
@@ -111,6 +111,7 @@ ARCHDIR-$(CONFIG_LP_ARCH_ARM)     := arm
 ARCHDIR-$(CONFIG_LP_ARCH_ARM64)   := arm64
 ARCHDIR-$(CONFIG_LP_ARCH_X86)     := x86
 ARCHDIR-$(CONFIG_LP_ARCH_MOCK)    := mock
+ARCHDIR-$(CONFIG_LP_ARCH_RISCV_RV64)    := riscv
 
 ARCH-y := $(ARCHDIR-y)
 
@@ -121,6 +122,7 @@ ARCH-$(CONFIG_LP_ARCH_ARM64)   := arm64
 ARCH-$(CONFIG_LP_ARCH_X86_32)  := x86_32
 ARCH-$(CONFIG_LP_ARCH_X86_64)  := x86_64
 ARCH-$(CONFIG_LP_ARCH_MOCK)    := mock
+ARCH-$(CONFIG_LP_ARCH_RISCV_RV64)    := riscv
 
 # Five cases where we don't need fully populated $(obj) lists:
 # 1. when no .config exists
diff --git a/payloads/libpayload/Makefile.mk b/payloads/libpayload/Makefile.mk
index 08249c2648..f7c2c8bda0 100644
--- a/payloads/libpayload/Makefile.mk
+++ b/payloads/libpayload/Makefile.mk
@@ -41,6 +41,7 @@ ARCHDIR-$(CONFIG_LP_ARCH_ARM)     := arm
 ARCHDIR-$(CONFIG_LP_ARCH_ARM64)   := arm64
 ARCHDIR-$(CONFIG_LP_ARCH_X86)     := x86
 ARCHDIR-$(CONFIG_LP_ARCH_MOCK)    := mock
+ARCHDIR-$(CONFIG_LP_ARCH_RISCV_RV64)    := riscv
 DESTDIR ?= install
 
 real-target: lib
diff --git a/payloads/libpayload/arch/riscv/Kconfig b/payloads/libpayload/arch/riscv/Kconfig
new file mode 100644
index 0000000000..03960ab1da
--- /dev/null
+++ b/payloads/libpayload/arch/riscv/Kconfig
@@ -0,0 +1,4 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
+config ARCH_RISCV_RV64
+	select LITTLE_ENDIAN
diff --git a/payloads/libpayload/arch/riscv/Makefile.mk b/payloads/libpayload/arch/riscv/Makefile.mk
new file mode 100644
index 0000000000..cb835bbfcb
--- /dev/null
+++ b/payloads/libpayload/arch/riscv/Makefile.mk
@@ -0,0 +1,7 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
+libc-y += head.S
+libc-y += main.c sysinfo.c
+libc-y += timer.c coreboot.c cache.c util.S virtual.c
+
+CFLAGS += -mcmodel=medany
diff --git a/payloads/libpayload/arch/riscv/cache.c b/payloads/libpayload/arch/riscv/cache.c
new file mode 100644
index 0000000000..d5dcb5e2a2
--- /dev/null
+++ b/payloads/libpayload/arch/riscv/cache.c
@@ -0,0 +1,13 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <arch/cache.h>
+
+void tlb_invalidate_all(void)
+{
+	asm volatile ("sfence.vma" : : : "memory");
+}
+
+void dcache_clean_invalidate_all(void)
+{
+
+}
diff --git a/payloads/libpayload/arch/riscv/coreboot.c b/payloads/libpayload/arch/riscv/coreboot.c
new file mode 100644
index 0000000000..acd3e85fb1
--- /dev/null
+++ b/payloads/libpayload/arch/riscv/coreboot.c
@@ -0,0 +1,34 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <libpayload-config.h>
+#include <libpayload.h>
+#include <coreboot_tables.h>
+
+/*
+ * This pointer is no longer set in head.S by default like in other arch, payloads should have
+ * their own ways to init it from any source before using it.
+ * e.g. If run after OpenSBI, this could be retrieved from fdt node.
+ *      If run directly after Ramstage, could be from arg0.
+ */
+void *cb_header_ptr;
+
+/* == Architecture specific == */
+
+int cb_parse_arch_specific(struct cb_record *rec, struct sysinfo_t *info)
+{
+	switch (rec->tag) {
+	default:
+		return 0;
+	}
+	return 1;
+}
+
+int get_coreboot_info(struct sysinfo_t *info)
+{
+	return cb_parse_header(cb_header_ptr, 1, info);
+}
+
+void *get_cb_header_ptr(void)
+{
+	return cb_header_ptr;
+}
diff --git a/payloads/libpayload/arch/riscv/head.S b/payloads/libpayload/arch/riscv/head.S
new file mode 100644
index 0000000000..aebbff979d
--- /dev/null
+++ b/payloads/libpayload/arch/riscv/head.S
@@ -0,0 +1,24 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <arch/asm.h>
+
+/*
+ * Our entry point
+ */
+ENTRY(_entry)
+
+	/* Setup new stack */
+	lla t0, 1f
+	ld sp, 0(t0)
+	//mov sp, x1
+
+	/* Let's rock. */
+	j start_main
+
+	ret
+ENDPROC(_entry)
+
+.section .entry, "ax", %progbits
+.align 4
+1:
+.quad	_stack
diff --git a/payloads/libpayload/arch/riscv/libpayload.ldscript b/payloads/libpayload/arch/riscv/libpayload.ldscript
new file mode 100644
index 0000000000..168f61397a
--- /dev/null
+++ b/payloads/libpayload/arch/riscv/libpayload.ldscript
@@ -0,0 +1,65 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+OUTPUT_ARCH(riscv)
+
+ENTRY(_entry)
+
+SECTIONS
+{
+	. = CONFIG_LP_BASE_ADDRESS;
+
+	. = ALIGN(16);
+	_start = .;
+
+	.text : {
+		_text = .;
+		*(.text._entry)
+		*(.text)
+		*(.text.*)
+		_etext = .;
+	}
+
+	.rodata : {
+		_rodata = .;
+		*(.rodata)
+		*(.rodata.*)
+		_erodata = .;
+	}
+
+	.data : {
+		_data = .;
+		*(.data)
+		*(.data.*)
+		_edata = .;
+	}
+
+	.bss : {
+		_bss = .;
+		*(.sbss)
+		*(.sbss.*)
+		*(.bss)
+		*(.bss.*)
+		*(COMMON)
+		_ebss = .;
+
+		/* Stack and heap */
+
+		. = ALIGN(16);
+		_heap = .;
+		. += CONFIG_LP_HEAP_SIZE;
+		. = ALIGN(16);
+		_eheap = .;
+
+		_estack = .;
+		. += CONFIG_LP_STACK_SIZE;
+		. = ALIGN(16);
+		_stack = .;
+	}
+
+	_end = .;
+
+	/DISCARD/ : {
+		*(.comment)
+		*(.note*)
+	}
+}
diff --git a/payloads/libpayload/arch/riscv/main.c b/payloads/libpayload/arch/riscv/main.c
new file mode 100644
index 0000000000..d0b400c8f2
--- /dev/null
+++ b/payloads/libpayload/arch/riscv/main.c
@@ -0,0 +1,53 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <libpayload.h>
+#include <endian.h>
+#include <commonlib/device_tree.h>
+
+uint64_t boot_hartid;
+/**
+ * This is our C entry function - set up the system and jump into the payload entry point.
+ * Unlike other archs, we do not save a0~a2 from previous stage as global variables in head.S,
+ * but pass them to start_main directly as arg0, arg1, arg2 instead.
+ *
+ * arg0 is the preferred boot hart id.
+ * arg1 is a pointer to the DTB.
+ * This interface is static no matter whether previous stage is OpenSBI or coreboot Ramstage.
+ *
+ * arg2 is reserved for possible future usage.
+ */
+void start_main(uint64_t arg0, uint64_t arg1, uint64_t arg2);
+void start_main(uint64_t arg0, uint64_t arg1, uint64_t arg2)
+{
+	extern int main(int argc, char **argv);
+	extern void *cb_header_ptr;
+
+	/* cbtable pointer is stored in the dtb passed by previous stage */
+	boot_hartid = arg0;
+	const void *dtb = (const void *)arg1;
+	if (dtb && fdt_is_valid(dtb)) {
+		/* Look for the "coreboot-table" node in the DTB */
+		u32 node_offset = fdt_find_node_by_path(dtb, "/chosen", NULL, NULL);
+		if (node_offset) {
+			struct fdt_property prop;
+			if (fdt_read_prop(dtb, node_offset, "coreboot-table", &prop)) {
+				/* Extract the coreboot table pointer from the property */
+				cb_header_ptr = (void *)be64dec(prop.data);
+			}
+		}
+	}
+
+	/* Gather system information. */
+	lib_get_sysinfo();
+
+#if !CONFIG(LP_SKIP_CONSOLE_INIT)
+	console_init();
+#endif
+
+	/*
+	 * Go to the entry point.
+	 * In the future we may care about the return value.
+	 */
+	main(0, NULL);
+	printf("Unexpected return from payload\n");
+}
diff --git a/payloads/libpayload/arch/riscv/sysinfo.c b/payloads/libpayload/arch/riscv/sysinfo.c
new file mode 100644
index 0000000000..353ede174e
--- /dev/null
+++ b/payloads/libpayload/arch/riscv/sysinfo.c
@@ -0,0 +1,70 @@
+/*
+ *
+ * Copyright (C) 2008 Advanced Micro Devices, Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#include <libpayload-config.h>
+#include <libpayload.h>
+#include <coreboot_tables.h>
+
+/**
+ * This is a global structure that is used through the library - we set it
+ * up initially with some dummy values - hopefully they will be overridden.
+ */
+struct sysinfo_t lib_sysinfo = {
+	.cpu_khz = 200,
+};
+
+int lib_get_sysinfo(void)
+{
+	int ret;
+
+	/* Get the CPU speed (for delays). */
+	lib_sysinfo.cpu_khz = get_cpu_speed();
+
+	/* Get information from the coreboot tables,
+	 * if they exist */
+
+	ret = get_coreboot_info(&lib_sysinfo);
+
+	if (!lib_sysinfo.n_memranges) {
+		/* If we can't get a good memory range, use the default. */
+		lib_sysinfo.n_memranges = 1;
+
+		lib_sysinfo.memrange[0].base = 0;
+		lib_sysinfo.memrange[0].size = 1024 * 1024;
+		lib_sysinfo.memrange[0].type = CB_MEM_RAM;
+	}
+
+	return ret;
+}
+
+void lib_sysinfo_get_memranges(struct memrange **ranges,
+			       uint64_t *nranges)
+{
+	*ranges = &lib_sysinfo.memrange[0];
+	*nranges = lib_sysinfo.n_memranges;
+}
diff --git a/payloads/libpayload/arch/riscv/timer.c b/payloads/libpayload/arch/riscv/timer.c
new file mode 100644
index 0000000000..1177e09802
--- /dev/null
+++ b/payloads/libpayload/arch/riscv/timer.c
@@ -0,0 +1,53 @@
+/*
+ *
+ * Copyright (C) 2008 Advanced Micro Devices, Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+/**
+ * @file riscv64/timer.c
+ * RISCV64 specific timer routines
+ */
+
+#include <libpayload.h>
+
+/**
+ * @ingroup arch
+ * Global variable containing the speed of the processor in KHz.
+ */
+u32 cpu_khz;
+
+/**
+ * Calculate the speed of the processor for use in delays.
+ *
+ * @return The CPU speed in kHz.
+ */
+unsigned int get_cpu_speed(void)
+{
+	/* FIXME */
+	cpu_khz = 1000000U;
+
+	return cpu_khz;
+}
diff --git a/payloads/libpayload/arch/riscv/util.S b/payloads/libpayload/arch/riscv/util.S
new file mode 100644
index 0000000000..3b15abc21d
--- /dev/null
+++ b/payloads/libpayload/arch/riscv/util.S
@@ -0,0 +1,34 @@
+/*
+ *
+ * Copyright (C) 2012 Google, Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#include <arch/asm.h>
+
+/* This function puts the system into a halt. */
+ENTRY(halt)
+	j halt
+ENDPROC(halt)
diff --git a/payloads/libpayload/arch/riscv/virtual.c b/payloads/libpayload/arch/riscv/virtual.c
new file mode 100644
index 0000000000..9450ac0d86
--- /dev/null
+++ b/payloads/libpayload/arch/riscv/virtual.c
@@ -0,0 +1,36 @@
+/*
+ *
+ * Copyright (C) 2008 coresystems GmbH
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#include <unistd.h>
+
+unsigned long virtual_offset = 0;
+
+int getpagesize(void)
+{
+	return 4096;
+}
diff --git a/payloads/libpayload/drivers/Makefile.mk b/payloads/libpayload/drivers/Makefile.mk
index 23471b83c4..63daf67cdb 100644
--- a/payloads/libpayload/drivers/Makefile.mk
+++ b/payloads/libpayload/drivers/Makefile.mk
@@ -64,6 +64,7 @@ libc-y += timer/generic.c
 endif
 libc-$(CONFIG_LP_TIMER_RDTSC) += timer/rdtsc.c
 libc-$(CONFIG_LP_TIMER_ARM64_ARCH) += timer/arm64_arch_timer.c
+libc-$(CONFIG_LP_TIMER_RISCV64_ARCH) += timer/riscv64_arch_timer.c
 
 # Video console drivers
 libc-$(CONFIG_LP_VIDEO_CONSOLE) += video/video.c
diff --git a/payloads/libpayload/drivers/timer/Kconfig b/payloads/libpayload/drivers/timer/Kconfig
index 406457af8e..1932a136da 100644
--- a/payloads/libpayload/drivers/timer/Kconfig
+++ b/payloads/libpayload/drivers/timer/Kconfig
@@ -36,6 +36,12 @@ config TIMER_ARM64_ARCH
 	help
 	  The cntfrq register needs to have been pre-initialized.
 
+config TIMER_RISCV64_ARCH
+	bool "Architecture Timer for RISCV64 platforms"
+	depends on ARCH_RISCV_RV64
+	help
+	  Payloads usually run in S-Mode, which has a time CSR for timer implementation.
+
 config TIMER_RK3288
 	bool "Timer for Rockchip RK3288"
 
diff --git a/payloads/libpayload/drivers/timer/riscv64_arch_timer.c b/payloads/libpayload/drivers/timer/riscv64_arch_timer.c
new file mode 100644
index 0000000000..515ae47658
--- /dev/null
+++ b/payloads/libpayload/drivers/timer/riscv64_arch_timer.c
@@ -0,0 +1,16 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <libpayload.h>
+
+uint64_t timer_hz(void)
+{
+	/* FIXME */
+	return 1000000;
+}
+
+uint64_t timer_raw_value(void)
+{
+	uint64_t value;
+	asm volatile ("csrr %0, time" : "=r" (value));
+	return value;
+}
diff --git a/payloads/libpayload/include/riscv/arch/asm.h b/payloads/libpayload/include/riscv/arch/asm.h
new file mode 100644
index 0000000000..5d8eae20e2
--- /dev/null
+++ b/payloads/libpayload/include/riscv/arch/asm.h
@@ -0,0 +1,23 @@
+/*
+ *
+ * Copyright 2013 Google Inc.
+ *
+ */
+
+#ifndef __RISCV64_ASM_H
+#define __RISCV64_ASM_H
+
+#define ENDPROC(name) \
+	.type name, %function; \
+	END(name)
+
+#define ENTRY(name) \
+	.section .text.name, "ax", %progbits; \
+	.global name; \
+	.align 2; \
+	name:
+
+#define END(name) \
+	.size name, .-name
+
+#endif	/* __RISCV64_ASM_H */
diff --git a/payloads/libpayload/include/riscv/arch/cache.h b/payloads/libpayload/include/riscv/arch/cache.h
new file mode 100644
index 0000000000..d47b05dd41
--- /dev/null
+++ b/payloads/libpayload/include/riscv/arch/cache.h
@@ -0,0 +1,21 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef RISCV64_CACHE_H
+#define RISCV64_CACHE_H
+
+#include <stddef.h>
+#include <stdint.h>
+
+/* tlb invalidate all */
+void tlb_invalidate_all(void);
+
+void dcache_clean_invalidate_all(void);
+
+/* Invalidate all of the instruction cache for PE to PoU. */
+static inline void icache_invalidate_all(void)
+{
+	__asm__ __volatile__("fence.i\n\t");
+}
+
+
+#endif /* RISCV64_CACHE_H */
diff --git a/payloads/libpayload/include/riscv/arch/io.h b/payloads/libpayload/include/riscv/arch/io.h
new file mode 100644
index 0000000000..b586204bfe
--- /dev/null
+++ b/payloads/libpayload/include/riscv/arch/io.h
@@ -0,0 +1,106 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef _ARCH_IO_H
+#define _ARCH_IO_H
+
+#include <stdint.h>
+#include <arch/cache.h>
+
+#define fence_i_r() __asm__ __volatile__("fence i,r" : : : "memory")
+#define fence_ow_ow() __asm__ __volatile__("fence ow,ow" : : : "memory")
+
+/*
+ * readb/w/l writeb/w/l are deprecated. use read8/16/32 and write8/16/32
+ * instead for future development.
+ */
+
+static inline uint8_t readb(volatile const void *_a)
+{
+	return *(volatile const uint8_t *)_a;
+	fence_i_r();
+}
+
+static inline uint16_t readw(volatile const void *_a)
+{
+	return *(volatile const uint16_t *)_a;
+	fence_i_r();
+}
+
+static inline uint32_t readl(volatile const void *_a)
+{
+	return *(volatile const uint32_t *)_a;
+	fence_i_r();
+}
+
+static inline void writeb(uint8_t _v, volatile void *_a)
+{
+	fence_ow_ow();
+	*(volatile uint8_t *)_a = _v;
+}
+
+static inline void writew(uint16_t _v, volatile void *_a)
+{
+	fence_ow_ow();
+	*(volatile uint16_t *)_a = _v;
+}
+
+static inline void writel(uint32_t _v, volatile void *_a)
+{
+	fence_ow_ow();
+	*(volatile uint32_t *)_a = _v;
+}
+
+/*
+ * TODO: make the existing code use read8/16/32 and write8/16/32 then remove
+ * readb/w/l and writeb/w/l.
+ */
+
+static inline uint8_t read8(volatile const void *addr)
+{
+	return *(volatile uint8_t *)addr;
+	fence_i_r();
+}
+
+static inline uint16_t read16(volatile const void *addr)
+{
+	return *(volatile uint16_t *)addr;
+	fence_i_r();
+}
+
+static inline uint32_t read32(volatile const void *addr)
+{
+	return *(volatile uint32_t *)addr;
+	fence_i_r();
+}
+
+static inline uint64_t read64(volatile const void *addr)
+{
+	return *(volatile uint64_t *)addr;
+	fence_i_r();
+}
+
+static inline void write8(volatile void *addr, uint8_t val)
+{
+	fence_ow_ow();
+	*(volatile uint8_t *)addr = val;
+}
+
+static inline void write16(volatile void *addr, uint16_t val)
+{
+	fence_ow_ow();
+	*(volatile uint16_t *)addr = val;
+}
+
+static inline void write32(volatile void *addr, uint32_t val)
+{
+	fence_ow_ow();
+	*(volatile uint32_t *)addr = val;
+}
+
+static inline void write64(volatile void *addr, uint64_t val)
+{
+	fence_ow_ow();
+	*(volatile uint64_t *)addr = val;
+}
+
+#endif
diff --git a/payloads/libpayload/include/riscv/arch/types.h b/payloads/libpayload/include/riscv/arch/types.h
new file mode 100644
index 0000000000..044e047f37
--- /dev/null
+++ b/payloads/libpayload/include/riscv/arch/types.h
@@ -0,0 +1,33 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef _ARCH_TYPES_H
+#define _ARCH_TYPES_H
+
+typedef unsigned char uint8_t;
+typedef unsigned char u8;
+typedef signed char int8_t;
+typedef signed char s8;
+
+typedef unsigned short uint16_t;
+typedef unsigned short u16;
+typedef signed short int16_t;
+typedef signed short s16;
+
+typedef unsigned int uint32_t;
+typedef unsigned int u32;
+typedef signed int int32_t;
+typedef signed int s32;
+
+typedef unsigned long long uint64_t;
+typedef unsigned long long u64;
+typedef signed long long int64_t;
+typedef signed long long s64;
+
+typedef long time_t;
+typedef long suseconds_t;
+
+#ifndef NULL
+#define NULL ((void *)0)
+#endif
+
+#endif
diff --git a/payloads/libpayload/include/riscv/arch/virtual.h b/payloads/libpayload/include/riscv/arch/virtual.h
new file mode 100644
index 0000000000..4b107787d2
--- /dev/null
+++ b/payloads/libpayload/include/riscv/arch/virtual.h
@@ -0,0 +1,14 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef _ARCH_VIRTUAL_H
+#define _ARCH_VIRTUAL_H
+
+extern unsigned long virtual_offset;
+
+#define virt_to_phys(virt) ((unsigned long) (virt) + virtual_offset)
+#define phys_to_virt(phys) ((void *) ((unsigned long) (phys) - virtual_offset))
+
+#define virt_to_bus(addr) virt_to_phys(addr)
+#define bus_to_virt(addr) phys_to_virt(addr)
+
+#endif
diff --git a/src/arch/riscv/boot.c b/src/arch/riscv/boot.c
index 6f744d3211..7d1cb3e92d 100644
--- a/src/arch/riscv/boot.c
+++ b/src/arch/riscv/boot.c
@@ -8,12 +8,58 @@
 #include <mcall.h>
 #include <cbfs.h>
 #include <console/console.h>
+#include <commonlib/device_tree.h>
+#include <cbmem.h>
 
 struct arch_prog_run_args {
 	struct prog *prog;
 	struct prog *opensbi;
 };
 
+/*
+ * At the moment devicetree is the default handoff format to the payload instead of
+ * coreboot tables (on RISC-V only). That may change in the future, but for now we will put a
+ * reference to the coreboot tables inside the FDT (similar to what we do in ACPI).
+ */
+static void *add_coreboot_table_to_fdt(void *fdt)
+{
+	if (!fdt || !fdt_is_valid(fdt)) {
+		printk(BIOS_ERR, "Invalid FDT provided\n");
+		return fdt;
+	}
+
+	void *coreboot_table = cbmem_find(CBMEM_ID_CBTABLE);
+	if (!coreboot_table) {
+		printk(BIOS_ERR, "coreboot table not found in CBMEM\n");
+		return fdt;
+	}
+
+	struct device_tree *tree = fdt_unflatten(fdt);
+	if (!tree) {
+		printk(BIOS_ERR, "Failed to unflatten FDT\n");
+		return fdt;
+	}
+
+	struct device_tree_node *chosen_node = dt_find_node_by_path(tree, "/chosen", NULL, NULL, 1);
+	if (!chosen_node) {
+		printk(BIOS_ERR, "Failed to find or create /chosen node\n");
+		return fdt;
+	}
+
+	printk(BIOS_INFO, "Adding cbtable@%p to fdt\n", coreboot_table);
+	dt_add_u64_prop(chosen_node, "coreboot-table", (uint64_t)(uintptr_t)coreboot_table);
+
+	size_t next_size = dt_flat_size(tree);
+	void *next_fdt = malloc(next_size);
+	if (!next_fdt) {
+		printk(BIOS_ERR, "Failed to allocate memory for next-stage FDT\n");
+		return fdt;
+	}
+
+	dt_flatten(tree, next_fdt);
+	return next_fdt;
+}
+
 /*
  * A pointer to the Flattened Device Tree passed to coreboot by the boot ROM.
  * Presumably this FDT is also in ROM.
@@ -51,14 +97,29 @@ void arch_prog_run(struct prog *prog)
 
 	args.prog = prog;
 
-	/* In case of OpenSBI we have to load it before resuming all HARTs */
-	if (ENV_RAMSTAGE && CONFIG(RISCV_OPENSBI)) {
-		struct prog sbi = PROG_INIT(PROG_OPENSBI, CONFIG_CBFS_PREFIX"/opensbi");
+	if (ENV_RAMSTAGE) {
+		int hart_count = CONFIG_MAX_CPUS;
+		if (CONFIG(RISCV_GET_HART_COUNT_AT_RUNTIME))
+			hart_count = smp_get_hart_count();
 
-		if (!selfload_check(&sbi, BM_MEM_OPENSBI))
-			die("OpenSBI load failed");
+		/* Embed coreboot table pointer into fdt, so that payload can find it. */
+		void *fdt = HLS()->fdt;
+		void *next_fdt = add_coreboot_table_to_fdt(fdt);
 
-		args.opensbi = &sbi;
+		/* Update per hart's fdt with "coreboot-table" node embedded */
+		for (int i = 0; i < hart_count; i++) {
+			OTHER_HLS(i)->fdt = next_fdt;
+		}
+
+		/* In case of OpenSBI we have to load it before resuming all HARTs */
+		if (CONFIG(RISCV_OPENSBI)) {
+			struct prog sbi = PROG_INIT(PROG_OPENSBI, CONFIG_CBFS_PREFIX"/opensbi");
+
+			if (!selfload_check(&sbi, BM_MEM_OPENSBI))
+				die("OpenSBI load failed");
+
+			args.opensbi = &sbi;
+		}
 	}
 
 	smp_resume((void (*)(void *))do_arch_prog_run, &args);

From 14a7a2315e722ef83b567d1918d7990eb83a451c Mon Sep 17 00:00:00 2001
From: Yidi Lin <yidilin@google.com>
Date: Wed, 31 Dec 2025 15:22:27 +0800
Subject: [PATCH 2972/3886] soc/mediatek/mt8196: Call fsp_init via boot state

Refactor fsp_init to be called as a boot state entry
(BS_DEV_INIT, BS_ON_ENTRY) instead of directly from soc_init. This
ensures fsp initialization occurs at the appropriate boot stage.

This change is necessary for FW logo rendering in the ramstage. fsp_init
must be run before FW display starts rendering the logo.

BUG=b:471111147
TEST=Check FW logo

Change-Id: I41b32229d4c582d84afac5c336eb98b1b1274ba8
Signed-off-by: Yidi Lin <yidilin@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90686
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Chen-Tsung Hsieh <chentsung@google.com>
---
 src/soc/mediatek/mt8196/soc.c | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/src/soc/mediatek/mt8196/soc.c b/src/soc/mediatek/mt8196/soc.c
index 24077a0fbc..e988a76926 100644
--- a/src/soc/mediatek/mt8196/soc.c
+++ b/src/soc/mediatek/mt8196/soc.c
@@ -1,6 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
 #include <bootmem.h>
+#include <bootstate.h>
 #include <device/device.h>
 #include <device/pci.h>
 #include <soc/booker.h>
@@ -56,7 +57,7 @@ static void mte_setup(void)
 	booker_mte_init(mte_start);
 }
 
-static void fsp_init(void)
+static void fsp_init(void *arg)
 {
 	uint32_t storage_type = mainboard_get_storage_type();
 
@@ -67,6 +68,8 @@ static void fsp_init(void)
 	mtk_fsp_load_and_run();
 }
 
+BOOT_STATE_INIT_ENTRY(BS_DEV_INIT, BS_ON_ENTRY, fsp_init, NULL);
+
 static void soc_init(struct device *dev)
 {
 	mtk_mmu_disable_l2c_sram();
@@ -76,7 +79,6 @@ static void soc_init(struct device *dev)
 	if (spm_init())
 		printk(BIOS_ERR, "spm init failed, Suspend may not work\n");
 
-	fsp_init();
 	sspm_init();
 	gpueb_init();
 	mcupm_init();

From e393fd00a4a06d305afbec244c38f98491ce5b1d Mon Sep 17 00:00:00 2001
From: Maximilian Brune <maximilian.brune@9elements.com>
Date: Wed, 27 Aug 2025 21:12:43 +0200
Subject: [PATCH 2973/3886] include/cper.h: Update cper_ia32x64_context_t

Use flexible array member cper_ia32x64_context to simplify the struct
usage.

Change-Id: I729cb914031b55b2b58bc9e459ee0ea15c7626e8
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90479
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/arch/x86/acpi_bert_storage.c | 6 ++----
 src/include/cper.h               | 2 +-
 2 files changed, 3 insertions(+), 5 deletions(-)

diff --git a/src/arch/x86/acpi_bert_storage.c b/src/arch/x86/acpi_bert_storage.c
index e9b9fc563a..321f66ac54 100644
--- a/src/arch/x86/acpi_bert_storage.c
+++ b/src/arch/x86/acpi_bert_storage.c
@@ -550,8 +550,6 @@ cper_ia32x64_context_t *cper_new_ia32x64_context_msr(
 		cper_ia32x64_proc_error_section_t *x86err, u32 addr, int num)
 {
 	cper_ia32x64_context_t *ctx;
-	int i;
-	msr_t *dest;
 
 	ctx = new_cper_ia32x64_ctx(status, x86err, CPER_IA32X64_CTX_MSR, num * sizeof(msr_t));
 	if (!ctx)
@@ -564,9 +562,9 @@ cper_ia32x64_context_t *cper_new_ia32x64_context_msr(
 	 */
 	ctx->msr_addr = addr;
 
-	dest = (msr_t *)((u8 *)(ctx + 1)); /* point to the Register Array */
+	msr_t *dest = (msr_t *)(ctx->register_array); /* point to the Register Array */
 
-	for (i = 0 ; i < num ; i++)
+	for (int i = 0 ; i < num ; i++)
 		*(dest + i) = rdmsr(addr + i);
 	return ctx;
 }
diff --git a/src/include/cper.h b/src/include/cper.h
index d0f7b30581..4dec2a2247 100644
--- a/src/include/cper.h
+++ b/src/include/cper.h
@@ -289,7 +289,7 @@ typedef struct cper_ia32x64_context {
 	u16 array_size;
 	u32 msr_addr;
 	u64 mmap_addr;
-	/* N bytes of register array */
+	u8 register_array[]; /* N bytes of register array */
 } __packed cper_ia32x64_context_t;
 
 /* IA32/X64 Processor Context Information, Types field (Table N.13) */

From b9145e15888934992eed5dc70e5b4aaeb9103e77 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Micha=C5=82=20=C5=BBygowski?= <michal.zygowski@3mdeb.com>
Date: Fri, 5 Dec 2025 11:07:24 +0100
Subject: [PATCH 2974/3886] util/amdfwtool: Remove duplicated AMD_TA_IKEK
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

The AMD_TA_IKEK occurrs twice in the amd_psp_fw_table, but the tool
will only add it once anyways, so remove redundant entry.

Change-Id: I7fd13552edf98d7adc749726c8bba46124aed495
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90389
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
---
 util/amdfwtool/amdfwtool.c | 1 -
 1 file changed, 1 deletion(-)

diff --git a/util/amdfwtool/amdfwtool.c b/util/amdfwtool/amdfwtool.c
index 9e9ada79a7..bac1c5bdbf 100644
--- a/util/amdfwtool/amdfwtool.c
+++ b/util/amdfwtool/amdfwtool.c
@@ -255,7 +255,6 @@ amd_fw_entry amd_psp_fw_table[] = {
 	{ .type = AMD_FW_AMF_WLAN, .inst = 2, .level = PSP_LVL2 | PSP_LVL2_AB },
 	{ .type = AMD_FW_AMF_WLAN, .inst = 3, .level = PSP_LVL2 | PSP_LVL2_AB },
 	{ .type = AMD_FW_AMF_MFD, .level = PSP_LVL2 | PSP_LVL2_AB },
-	{ .type = AMD_TA_IKEK, .level = PSP_BOTH | PSP_LVL2_AB, .skip_hashing = true },
 	{ .type = AMD_FW_MPCCX, .subprog = 0, .level = PSP_LVL2 | PSP_LVL2_AB },
 	{ .type = AMD_FW_MPCCX, .subprog = 1, .level = PSP_LVL2 | PSP_LVL2_AB },
 	{ .type = AMD_FW_LSDMA, .level = PSP_LVL2 | PSP_LVL2_AB },

From 6b52f82df270bfce1ac99249f8fb8f7bdf11c597 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Micha=C5=82=20=C5=BBygowski?= <michal.zygowski@3mdeb.com>
Date: Fri, 5 Dec 2025 11:03:57 +0100
Subject: [PATCH 2975/3886] util/amdfwtool: Remove AMD_FW_GFXIMU_2 entry
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

AMD_FW_GFXIMU_2 entry has the same type value as AMD_FW_SRAM_FW_EXT.
The tool may integrate one of these blobs incorrectly, because
it searches for the first entry of given type in the amd_psp_fw_table.

AMD_FW_GFXIMU_2 could have been added by mistake, because there is no
board that actually defines PSP_GFX_IMMU_FILE_2 in fw.cfg file.

Change-Id: I7e1f38c77156d06e9e6d801bdfa9b9eefcbb374e
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90388
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 util/amdfwtool/amdfwtool.c  | 1 -
 util/amdfwtool/amdfwtool.h  | 1 -
 util/amdfwtool/data_parse.c | 4 ----
 3 files changed, 6 deletions(-)

diff --git a/util/amdfwtool/amdfwtool.c b/util/amdfwtool/amdfwtool.c
index bac1c5bdbf..4184a60b74 100644
--- a/util/amdfwtool/amdfwtool.c
+++ b/util/amdfwtool/amdfwtool.c
@@ -266,7 +266,6 @@ amd_fw_entry amd_psp_fw_table[] = {
 	{ .type = AMD_FW_GFXIMU_0, .subprog = 1, .level = PSP_BOTH | PSP_LVL2_AB },
 	{ .type = AMD_FW_GFXIMU_1, .subprog = 0, .level = PSP_BOTH | PSP_LVL2_AB },
 	{ .type = AMD_FW_GFXIMU_1, .subprog = 1, .level = PSP_BOTH | PSP_LVL2_AB },
-	{ .type = AMD_FW_GFXIMU_2, .level = PSP_BOTH | PSP_LVL2_AB },
 	{ .type = AMD_FW_SRAM_FW_EXT, .level = PSP_LVL2 | PSP_LVL2_AB },
 	{ .type = AMD_FW_UMSMU, .level = PSP_LVL2 | PSP_LVL2_AB },
 	{ .type = AMD_FW_S3IMG, .level = PSP_LVL2 | PSP_LVL2_AB },
diff --git a/util/amdfwtool/amdfwtool.h b/util/amdfwtool/amdfwtool.h
index dbc1c4adc0..fe3f72b85d 100644
--- a/util/amdfwtool/amdfwtool.h
+++ b/util/amdfwtool/amdfwtool.h
@@ -118,7 +118,6 @@ typedef enum _amd_fw_type {
 	AMD_FW_MINIMSMU = 0x9a,
 	AMD_FW_GFXIMU_0 = 0x9b,
 	AMD_FW_GFXIMU_1 = 0x9c,
-	AMD_FW_GFXIMU_2 = 0x9d,
 	AMD_FW_SRAM_FW_EXT = 0x9d,
 	AMD_FW_UMSMU = 0xa2,
 	AMD_FW_S3IMG = 0xa0,
diff --git a/util/amdfwtool/data_parse.c b/util/amdfwtool/data_parse.c
index 13922d63c9..2ea37efd67 100644
--- a/util/amdfwtool/data_parse.c
+++ b/util/amdfwtool/data_parse.c
@@ -407,10 +407,6 @@ static uint8_t find_register_fw_filename_psp_dir(char *fw_name, char *filename,
 		fw_type = AMD_FW_GFXIMU_1;
 		instance = 0;
 		subprog = 1;
-	} else if (strcmp(fw_name, "PSP_GFX_IMMU_FILE_2") == 0) {
-		fw_type = AMD_FW_GFXIMU_2;
-		instance = 0;
-		subprog = 0;
 	} else if (strcmp(fw_name, "MINIMSMU_FILE_INS1") == 0) {
 		fw_type = AMD_FW_MINIMSMU;
 		instance = 1;

From 7ed7abbd92b84c97461742eee888a261ba200140 Mon Sep 17 00:00:00 2001
From: Fabio Baltieri <fabiobaltieri@google.com>
Date: Wed, 24 Dec 2025 14:18:39 +0000
Subject: [PATCH 2976/3886] acpigen_ps2_keybd: map screenlock

This is going to be used by some devices, map the next available
extended code to it.

Change-Id: Ib4fc6c33e10f273a73f3a6ca40deeefa3ab70f20
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90617
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/acpi/acpigen_ps2_keybd.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/src/acpi/acpigen_ps2_keybd.c b/src/acpi/acpigen_ps2_keybd.c
index f8b58d739b..38af89bfda 100644
--- a/src/acpi/acpigen_ps2_keybd.c
+++ b/src/acpi/acpigen_ps2_keybd.c
@@ -179,6 +179,8 @@ static uint32_t rest_of_keymaps[] = {
 	KEYMAP(0x3a, KEY_CAPSLOCK),
 	/* Insert Key */
 	KEYMAP(0xd2, KEY_INSERT),
+	/* Screen Lock */
+	KEYMAP(0xab, KEY_SCREENLOCK),
 };
 
 static void ssdt_generate_physmap(struct acpi_dp *dp, uint8_t num_top_row_keys,

From ae48ff8c0b677a12b724540cc2ad2269a8df3b0c Mon Sep 17 00:00:00 2001
From: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Date: Fri, 12 Dec 2025 13:30:00 +0800
Subject: [PATCH 2977/3886] drivers/wwan/fm: Use _EVT method to enhance GPIO
 event handling

Currently _Exx suppots the wake pin under 255, for Caboc it's wake pin
is 325 which is out of range.

This CL change to use _EVT method to enhance GPIO event handling.

BUG=b:463410386
TEST=Compiled and tested on google/redrix and google/caboc:
1. emerge-brya coreboot, emerge-brox coreboot
2. Check /proc/interrupts has ACPI:Event
2. Wait for WWAN device to enter suspended state
3. Insert SIM card and modem is able to wake up WWAN device

Change-Id: Ifbb83ab48bbe4876269010adb2710641bdc879a5
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90492
Reviewed-by: Kevin Chiu <kevin.chiu.17802@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/drivers/wwan/fm/acpi_fm350gl.c | 23 ++++++++++++-----------
 1 file changed, 12 insertions(+), 11 deletions(-)

diff --git a/src/drivers/wwan/fm/acpi_fm350gl.c b/src/drivers/wwan/fm/acpi_fm350gl.c
index 564ac03cfc..07054e33cb 100644
--- a/src/drivers/wwan/fm/acpi_fm350gl.c
+++ b/src/drivers/wwan/fm/acpi_fm350gl.c
@@ -285,18 +285,19 @@ wwan_fm350gl_acpi_event_method(const struct device *dev,
 	if (CONFIG(GENERIC_GPIO_LIB))
 		pin = gpio_acpi_pin(pin);
 
-	if (pin > 0xff) {
-		printk(BIOS_ERR, "%s: pins above 0xFF are unsupported (pin %u)\n",
-		       __func__, pin);
-		return;
+	if (pin <= 0xff) {
+		snprintf(name, sizeof(name), "_%c%02X",
+			wake_gpio->irq.mode == ACPI_IRQ_EDGE_TRIGGERED ? 'E' : 'L', pin);
+		acpigen_write_method_serialized(name, 0);
+		acpigen_notify(acpi_device_path(dev), 0x02); /* NOTIFY_DEVICE_WAKE */
+		acpigen_write_method_end();
+	} else {
+		acpigen_write_method_serialized("_EVT", 1);
+		acpigen_write_if_lequal_op_int(ARG0_OP, pin);
+		acpigen_notify(acpi_device_path(dev), 0x02); /* NOTIFY_DEVICE_WAKE */
+		acpigen_pop_len();
+		acpigen_write_method_end();
 	}
-
-	snprintf(name, sizeof(name), "_%c%02X",
-		 wake_gpio->irq.mode == ACPI_IRQ_EDGE_TRIGGERED ? 'E' : 'L', pin);
-
-	acpigen_write_method_serialized(name, 0);
-	acpigen_notify(acpi_device_path(dev), 0x02); /* NOTIFY_DEVICE_WAKE */
-	acpigen_write_method_end();
 }
 
 static void wwan_fm350gl_acpi_gpio_events(const struct device *dev)

From b7ad850fd6166e4caaec5415a409b75cb0c89622 Mon Sep 17 00:00:00 2001
From: Subrata Banik <subratabanik@google.com>
Date: Tue, 6 Jan 2026 09:13:10 +0530
Subject: [PATCH 2978/3886] mb/google/bluey: Add percentage symbol to battery
 level log

Update the battery state-of-charge print statement in romstage to
include a percentage symbol. This makes the log output more
readable and consistent with battery level reporting.

Use '%%' to correctly escape and print the literal '%' sign in
the printk statement.

BUG=None
TEST=Boot Bluey and verify romstage logs show "Battery
state-of-charge 95%" instead of "Battery state-of-charge 95".

Change-Id: I97b533567b56bfaba41508e35a6f324f0dbf331e
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90684
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/google/bluey/romstage.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/mainboard/google/bluey/romstage.c b/src/mainboard/google/bluey/romstage.c
index 06cd5626bd..1c6660112e 100644
--- a/src/mainboard/google/bluey/romstage.c
+++ b/src/mainboard/google/bluey/romstage.c
@@ -83,7 +83,7 @@ static void platform_dump_battery_soc_information(void)
 	if (google_chromeec_read_batt_state_of_charge(&batt_pct))
 		printk(BIOS_WARNING, "Failed to get battery level\n");
 	else
-		printk(BIOS_INFO, "Battery state-of-charge %d\n", batt_pct);
+		printk(BIOS_INFO, "Battery state-of-charge %d%%\n", batt_pct);
 }
 
 void platform_romstage_main(void)

From b00d2ad5c20b9f3234a33cef018320824749476d Mon Sep 17 00:00:00 2001
From: Sowmya V <v.sowmya@intel.com>
Date: Tue, 2 Dec 2025 14:05:46 +0530
Subject: [PATCH 2979/3886] vc/intel/fsp/fsp2_0/pantherlake: Update PTL FSP
 headers to FSP 3442.07
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Update Panther lake FSP headers from version 3373.03 to 3442.07

FspmUpd.h: Add below upds
* Vdd2HVoltage
* Vdd1Voltage
* Vdd2LVoltage
* VddqVoltage

FspsUpd.h: Add below upds
* UfsInlineEncryption
* MaxActiveDisplays

MemInfoHob.h:
* FailingChannelMask - Limp Home mode failing channel bitmask

BUG=b:463516609
TEST=Able to build google/fatcat with the latest header changes

Change-Id: Ifd9d3476626f4028ea01eddef23b3b61f5e76d17
Signed-off-by: Sowmya V <v.sowmya@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90332
Reviewed-by: Pranava Y N <pranavayn@google.com>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 .../intel/fsp/fsp2_0/pantherlake/FspmUpd.h    | 33 ++++++++++++++++---
 .../intel/fsp/fsp2_0/pantherlake/FspsUpd.h    | 22 ++++++++++---
 .../intel/fsp/fsp2_0/pantherlake/MemInfoHob.h |  4 ++-
 3 files changed, 50 insertions(+), 9 deletions(-)

diff --git a/src/vendorcode/intel/fsp/fsp2_0/pantherlake/FspmUpd.h b/src/vendorcode/intel/fsp/fsp2_0/pantherlake/FspmUpd.h
index 5c26bcd685..ac166e6ccf 100644
--- a/src/vendorcode/intel/fsp/fsp2_0/pantherlake/FspmUpd.h
+++ b/src/vendorcode/intel/fsp/fsp2_0/pantherlake/FspmUpd.h
@@ -2463,12 +2463,12 @@ typedef struct {
   UINT8                       DlvrRfiEnable;
 
 /** Offset 0x0949 - Pcore VR Hysteresis time window
-  Enable/Disable DLVR RFI frequency hopping. 0: Disable; <b>1: Enable</b>.
+  0 is default. Range of PcoreHysteresisWindow from 1ms to 50ms.
 **/
   UINT8                       PcoreHysteresisWindow;
 
 /** Offset 0x094A - Ecore VR Hysteresis time window
-  Enable/Disable DLVR RFI frequency hopping. 0: Disable; <b>1: Enable</b>.
+  0 is default. Range of EcoreHysteresisWindow from 1ms to 50ms.
 **/
   UINT8                       EcoreHysteresisWindow;
 
@@ -2793,7 +2793,8 @@ typedef struct {
   Initialise SOL Init, BIT0 - (0 : Disable VGA Support, 1 : Enable VGA Support),,
   BIT1 - (0 : VGA Text Mode 3, 1 : VGA Graphics Mode 12), BIT2 - (0 : VGA Exit Supported,
   1: NO VGA Exit), BIT3 - (0 : VGA Init During Display Init, 1 - VGA Init During
-  MRC Cold Boot), BIT4 - (0 : Enable Progress Bar, 1 : Disable Progress Bar)
+  MRC Cold Boot), BIT4 - (0 : Enable Progress Bar, 1 : Disable Progress Bar), BIT5
+  - (0 : VGA Mode 12 16 Color Support, 1 : VGA Mode 12 Monochrome Black and White Support)
   0:VGA Disable, 1:Mode 3 VGA, 2:Mode 12 VGA
 **/
   UINT8                       VgaInitControl;
@@ -3121,7 +3122,31 @@ typedef struct {
 
 /** Offset 0x0B31 - Reserved
 **/
-  UINT8                       Reserved93[55];
+  UINT8                       Reserved93[17];
+
+/** Offset 0x0B42 - VDD2 Voltage
+  Voltage is multiple of 5mV where 0 means Auto.
+**/
+  UINT16                      Vdd2HVoltage;
+
+/** Offset 0x0B44 - VDD1 Voltage
+  Voltage is multiple of 5mV where 0 means Auto.
+**/
+  UINT16                      Vdd1Voltage;
+
+/** Offset 0x0B46 - VDD2L Voltage Override
+  Voltage is multiple of 5mV where 0 means Auto.
+**/
+  UINT16                      Vdd2LVoltage;
+
+/** Offset 0x0B48 - VDDQ Voltage Override
+  Voltage is multiple of 5mV where 0 means Auto.
+**/
+  UINT16                      VddqVoltage;
+
+/** Offset 0x0B4A - Reserved
+**/
+  UINT8                       Reserved94[30];
 } FSP_M_CONFIG;
 
 /** Fsp M UPD Configuration
diff --git a/src/vendorcode/intel/fsp/fsp2_0/pantherlake/FspsUpd.h b/src/vendorcode/intel/fsp/fsp2_0/pantherlake/FspsUpd.h
index b5194418b1..ae0ffe29dd 100644
--- a/src/vendorcode/intel/fsp/fsp2_0/pantherlake/FspsUpd.h
+++ b/src/vendorcode/intel/fsp/fsp2_0/pantherlake/FspsUpd.h
@@ -458,9 +458,17 @@ typedef struct {
 **/
   UINT8                       UfsEnable[2];
 
-/** Offset 0x014D - Reserved
+/** Offset 0x014D - UFS Inline Encryption enable/disable
+  Enable/Disable UFS Inline Encryption feature, One byte for each Controller - (1,0)
+  to enable Inline Encryption for controller 0 and (0, 1) to enable Inline Encryption
+  for controller 1
+  $EN_DIS
 **/
-  UINT8                       Reserved12[4];
+  UINT8                       UfsInlineEncryption[2];
+
+/** Offset 0x014F - Reserved
+**/
+  UINT8                       Reserved12[2];
 
 /** Offset 0x0151 - Enable/Disable PCIe tunneling for USB4
   Enable/Disable PCIe tunneling for USB4, default is enable
@@ -2026,9 +2034,15 @@ typedef struct {
 **/
   UINT8                       LidStatus;
 
-/** Offset 0x1401 - Reserved
+/** Offset 0x1401 - Select MaxActiveDisplays
+  Max Active Display : 0 - Default VBT, 1 - 1 display, 2 - 2 displays, Maximum supported
+  is 2 displays only
 **/
-  UINT8                       Reserved50[67];
+  UINT8                       MaxActiveDisplays;
+
+/** Offset 0x1402 - Reserved
+**/
+  UINT8                       Reserved50[66];
 
 /** Offset 0x1444 - Address of PCH_DEVICE_INTERRUPT_CONFIG table.
   The address of the table of PCH_DEVICE_INTERRUPT_CONFIG.
diff --git a/src/vendorcode/intel/fsp/fsp2_0/pantherlake/MemInfoHob.h b/src/vendorcode/intel/fsp/fsp2_0/pantherlake/MemInfoHob.h
index c89cf2cab1..e50c114e41 100644
--- a/src/vendorcode/intel/fsp/fsp2_0/pantherlake/MemInfoHob.h
+++ b/src/vendorcode/intel/fsp/fsp2_0/pantherlake/MemInfoHob.h
@@ -312,7 +312,8 @@ typedef struct _PPR_RESULT_COLUMNS_HOB {
   - DIMM_INFO: Added SerialNumber, TotalWidth and DataWidth
   - DIMM_INFO: Removed SpdModuleMemoryBusWidth
   - MFG ID fields: use HOB_MANUFACTURER_ID_CODE instead of UINT16 for easier parsing
-
+  <b>Revision 4:</b>
+  - Added FailingChannelMask
 **/
 typedef struct {
   UINT8             Revision;
@@ -363,6 +364,7 @@ typedef struct {
   UINT8             MaxRankCapacity;                   ///< Maximum possible rank capacity in [GB]
   UINT16            PprFailingChannelBitMask;          ///< PPR failing channel mask
   BOOLEAN           PprTargetedStatus[PPR_REQUEST_MAX]; ///< PPR status of each Targeted PPR request (0 = Targeted PPR was successful, 1 = PPR failed)
+  UINT8             FailingChannelMask;                 ///< Limp Home mode failing channel bitmask
 } MEMORY_INFO_DATA_HOB;
 
 /**

From 7deb82d7444be2860e0e50b49dbb67986c459459 Mon Sep 17 00:00:00 2001
From: Kirubakaran E <kirue@qualcomm.corp-partner.google.com>
Date: Tue, 6 Jan 2026 20:54:08 -0800
Subject: [PATCH 2980/3886] mb/google/bluey: Configure QUPV3_0_SE3 and
 QUPV3_0_SE7 for USB-C0 and USB-C1 Retimer I2C access

Load I2C firmware to QUPV3_0_SE3 and QUPV3_0_SE7 Serial Engines and
configure both in MIXED mode to enable I2C access for USB-C0 and USB-C1
retimers.

Test=
1. Created image.serial.bin and verified successful boot on X1P42100.
2. Read the corresponding QUP SE firmware revision read-only register
   and confirmed that the protocol field (bits 8-15) matches the
   programmed value. Register details are in HRD-X1P42100-S1
   documentation:
   https://docs.qualcomm.com/bundle/resource/topics/HRD-X1P42100-S1/
   Example:If programmed as I2C, the register value read is 0x00000303,
   where 3 denotes the I2C protocol.

Change-Id: I337329628ac04246ab579e062a802a028cb4c560
Signed-off-by: Kirubakaran E <kirue@qualcomm.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90690
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/google/bluey/mainboard.c | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/src/mainboard/google/bluey/mainboard.c b/src/mainboard/google/bluey/mainboard.c
index 9f958a1862..b93b4188db 100644
--- a/src/mainboard/google/bluey/mainboard.c
+++ b/src/mainboard/google/bluey/mainboard.c
@@ -122,6 +122,12 @@ static void mainboard_init(struct device *dev)
 	/* ADSP I2C (Charger/Fuel gauge) */
 	qupv3_se_fw_load_and_init(QUPV3_2_SE4, SE_PROTOCOL_I2C, GSI);
 
+	/* USB-C0 Re-Timer I2C */
+	qupv3_se_fw_load_and_init(QUPV3_0_SE3, SE_PROTOCOL_I2C, MIXED);
+
+	/* USB-C1 Re-Timer I2C */
+	qupv3_se_fw_load_and_init(QUPV3_0_SE7, SE_PROTOCOL_I2C, MIXED);
+
 	if (!CONFIG(MAINBOARD_NO_USB_A_PORT))
 		qupv3_se_fw_load_and_init(QUPV3_0_SE1, SE_PROTOCOL_I2C, MIXED); /* USB-A retimer */
 	qupv3_se_fw_load_and_init(QUPV3_0_SE5, SE_PROTOCOL_I2C, MIXED); /* eUSB repeater */

From 1da7c31810638eb300017a61781f00f7ceef540a Mon Sep 17 00:00:00 2001
From: Maximilian Brune <maximilian.brune@9elements.com>
Date: Fri, 28 Nov 2025 15:31:28 +0100
Subject: [PATCH 2981/3886] include/cpu/x86/msr.h: Add MCA related MSRs

They are needed in a later patch which is not yet upstream.

source: AMD64 Architecture Programmers Manual Rev 3.42

Change-Id: I4f5bb5533d8f0e1765749d24ef0b22805ad1554a
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90480
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/include/cpu/x86/msr.h             | 15 +++++++++++++++
 src/security/intel/txt/txt_register.h |  4 +---
 2 files changed, 16 insertions(+), 3 deletions(-)

diff --git a/src/include/cpu/x86/msr.h b/src/include/cpu/x86/msr.h
index a5226fb0b6..2fdb064608 100644
--- a/src/include/cpu/x86/msr.h
+++ b/src/include/cpu/x86/msr.h
@@ -40,9 +40,12 @@
 #define IA32_SMM_MONITOR_CTL_MSR	0x9B
 #define SMBASE_RO_MSR			0x98
 #define  IA32_SMM_MONITOR_VALID		(1 << 0)
+#define IA32_SYSENTER_EIP		0x176
 #define IA32_MCG_CAP			0x179
 #define  MCG_CTL_P			(1 << 8)
 #define  MCA_BANKS_MASK			0xff
+#define IA32_MCG_STATUS			0x17A
+#define  MCG_STAT_EIPV			(1 << 1)
 #define IA32_PERF_STATUS		0x198
 #define IA32_PERF_CTL			0x199
 #define IA32_THERM_INTERRUPT		0x19b
@@ -74,6 +77,8 @@
 #define  MCA_STATUS_HI_ADDRV		(1UL << (58 - 32))
 #define  MCA_STATUS_HI_PCC		(1UL << (57 - 32))
 #define  MCA_STATUS_HI_COREID_VAL	(1UL << (56 - 32))
+#define  MCA_STATUS_HI_TCC		(1UL << (55 - 32))
+#define  MCA_STATUS_HI_SYNDV		(1UL << (53 - 32))
 #define  MCA_STATUS_HI_CECC		(1UL << (46 - 32))
 #define  MCA_STATUS_HI_UECC		(1UL << (45 - 32))
 #define  MCA_STATUS_HI_DEFERRED		(1UL << (44 - 32))
@@ -172,6 +177,16 @@ static inline int mca_pcc(msr_t msr)
 	return !!(msr.hi & MCA_STATUS_HI_PCC);
 }
 
+static inline int mca_tcc(msr_t msr)
+{
+	return !!(msr.hi & MCA_STATUS_HI_TCC);
+}
+
+static inline int mca_syndv(msr_t msr)
+{
+	return !!(msr.hi & MCA_STATUS_HI_SYNDV);
+}
+
 static inline int mca_idv(msr_t msr)
 {
 	return !!(msr.hi & MCA_STATUS_HI_COREID_VAL);
diff --git a/src/security/intel/txt/txt_register.h b/src/security/intel/txt/txt_register.h
index a00084511f..588fef1387 100644
--- a/src/security/intel/txt/txt_register.h
+++ b/src/security/intel/txt/txt_register.h
@@ -3,6 +3,7 @@
 #ifndef SECURITY_INTEL_TXT_REGISTER_H_
 #define SECURITY_INTEL_TXT_REGISTER_H_
 
+#include <cpu/x86/msr.h>
 #include <types.h>
 
 /*
@@ -162,9 +163,6 @@
 #define ACM_FORMAT_SIZE_128KB (128 * KiB / 4)
 #define ACM_FORMAT_SIZE_256KB (256 * KiB / 4)
 
-/* MSRs */
-#define IA32_MCG_STATUS 0x17a
-
 /* DPR register layout, either in PCI config space or TXT MMIO space */
 union dpr_register {
 	struct {

From 3ded43722ac626cd15927cabdcb5db78f313628d Mon Sep 17 00:00:00 2001
From: Maximilian Brune <maximilian.brune@9elements.com>
Date: Fri, 28 Nov 2025 16:33:10 +0100
Subject: [PATCH 2982/3886] soc/amd/cmn/block/acpi/ivrs: Use less PCI accesses

Refactor code to use less redundant PCI accesses to decrease boot time.

Change-Id: Ic2bb610ebf22dd43580ac94360d905b1c782224a
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90641
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/soc/amd/common/block/acpi/ivrs.c | 15 +++++++--------
 1 file changed, 7 insertions(+), 8 deletions(-)

diff --git a/src/soc/amd/common/block/acpi/ivrs.c b/src/soc/amd/common/block/acpi/ivrs.c
index 2301158a0a..48c3965926 100644
--- a/src/soc/amd/common/block/acpi/ivrs.c
+++ b/src/soc/amd/common/block/acpi/ivrs.c
@@ -305,6 +305,7 @@ static unsigned long acpi_fill_ivrs(acpi_ivrs_t *ivrs, unsigned long current)
 	uint64_t mmio_x18_value;
 	uint64_t mmio_x4000_value;
 	uint32_t cap_offset_0;
+	uint32_t cap_offset_c;
 	uint32_t cap_offset_10;
 	struct acpi_ivrs_ivhd *ivhd;
 	struct device *iommu_dev;
@@ -342,6 +343,8 @@ static unsigned long acpi_fill_ivrs(acpi_ivrs_t *ivrs, unsigned long current)
 		ivhd->iommu_base_high = pci_read_config32(iommu_dev, IOMMU_CAP_BASE_HI);
 
 		cap_offset_0 = pci_read_config32(iommu_dev, ivhd->capability_offset);
+		cap_offset_c = pci_read_config32(iommu_dev,
+						ivhd->capability_offset + 0xC);
 		cap_offset_10 = pci_read_config32(iommu_dev,
 						ivhd->capability_offset + 0x10);
 		mmio_x18_value = read64p(ivhd->iommu_base_low + 0x18);
@@ -367,10 +370,8 @@ static unsigned long acpi_fill_ivrs(acpi_ivrs_t *ivrs, unsigned long current)
 
 		ivhd->pci_segment_group = nb_dev->upstream->segment_group;
 
-		ivhd->iommu_info = pci_read_config16(iommu_dev,
-			ivhd->capability_offset + 0x10) & 0x1F;
-		ivhd->iommu_info |= (pci_read_config16(iommu_dev,
-			ivhd->capability_offset + 0xC) & 0x1F) << IOMMU_INFO_UNIT_ID_SHIFT;
+		ivhd->iommu_info = cap_offset_10 & 0x1F;
+		ivhd->iommu_info |= (cap_offset_c & 0x1F) << IOMMU_INFO_UNIT_ID_SHIFT;
 
 		ivhd->iommu_feature_info = 0;
 		ivhd->iommu_feature_info |= (mmio_x30_value & MMIO_EXT_FEATURE_HATS_MASK)
@@ -409,10 +410,8 @@ static unsigned long acpi_fill_ivrs(acpi_ivrs_t *ivrs, unsigned long current)
 			? IOMMU_FEATURE_XT_SUP : 0);
 
 		/* Enable EFR if supported */
-		ivrs->iv_info = pci_read_config32(iommu_dev,
-					ivhd->capability_offset + 0x10) & 0x007fffe0;
-		if (pci_read_config32(iommu_dev,
-					ivhd->capability_offset) & EFR_FEATURE_SUP)
+		ivrs->iv_info = cap_offset_10 & 0x007fffe0;
+		if (cap_offset_0 & EFR_FEATURE_SUP)
 			ivrs->iv_info |= IVINFO_EFR_SUPPORTED;
 
 

From c7f0697867eced9928fce3065568a267a1412b6f Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Micha=C5=82=20=C5=BBygowski?= <michal.zygowski@3mdeb.com>
Date: Mon, 6 Oct 2025 11:53:10 +0200
Subject: [PATCH 2983/3886] coreboot_tables: Add new CBMEM ID to hold the PCI
 RB aperture info
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

On AMD server systems there are multiple PCI root bridges. The root
bridge scanning in UEFI Payload is not sufficient to detect the
memory and I/O apertures properly. For example on Turin system, the
I/O aperture on the first root bridge containing the FCH may not
have any I/O resources detected on the PCI devices. This results in
the I/O decoding to be disabled on the root bridge, effectively
breaking the I/O based serial ports, e.g. on Super I/Os and BMCs.

Add new CBMEM ID to report the PCI root bridge aperture information
to the payload. The intention is to use the Universal Payload PCI Root
Bridges Info HOB that is already supported in the UEFI Payload. The HOB
will take priority over the root bridge scanning and properly report
the apertures of the PCI root bridges on AMD system.

Change-Id: If7f7dc6710f389884adfd292bc5ce77e0c37766f
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89486
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
---
 src/commonlib/bsd/include/commonlib/bsd/cbmem_id.h | 4 +++-
 src/commonlib/include/commonlib/coreboot_tables.h  | 1 +
 src/lib/coreboot_table.c                           | 1 +
 3 files changed, 5 insertions(+), 1 deletion(-)

diff --git a/src/commonlib/bsd/include/commonlib/bsd/cbmem_id.h b/src/commonlib/bsd/include/commonlib/bsd/cbmem_id.h
index 20a1099f0a..a5cb0a7f8a 100644
--- a/src/commonlib/bsd/include/commonlib/bsd/cbmem_id.h
+++ b/src/commonlib/bsd/include/commonlib/bsd/cbmem_id.h
@@ -92,6 +92,7 @@
 #define CBMEM_ID_AMD_OPENSIL	0x4153494C
 #define CBMEM_ID_PVMFW		0x666d7670
 #define CBMEM_ID_BOOT_MODE	0x444D5442
+#define CBMEM_ID_RB_INFO	0x50524249
 
 #define CBMEM_ID_TO_NAME_TABLE				 \
 	{ CBMEM_ID_ACPI,		"ACPI       " }, \
@@ -176,5 +177,6 @@
 	{ CBMEM_ID_CSE_BP_INFO,		"CSE BP INFO"}, \
 	{ CBMEM_ID_AMD_OPENSIL,		"OPENSIL DATA"}, \
 	{ CBMEM_ID_PVMFW,		"PVMFW      "}, \
-	{ CBMEM_ID_BOOT_MODE,		"BOOT MODE  "}
+	{ CBMEM_ID_BOOT_MODE,		"BOOT MODE  "}, \
+	{ CBMEM_ID_RB_INFO,		"PCI RB INFO"}
 #endif /* _CBMEM_ID_H_ */
diff --git a/src/commonlib/include/commonlib/coreboot_tables.h b/src/commonlib/include/commonlib/coreboot_tables.h
index 817ca0e4f2..fcc7761044 100644
--- a/src/commonlib/include/commonlib/coreboot_tables.h
+++ b/src/commonlib/include/commonlib/coreboot_tables.h
@@ -90,6 +90,7 @@ enum {
 	LB_TAG_EFI_FW_INFO		= 0x0045,
 	LB_TAG_CAPSULE			= 0x0046,
 	LB_TAG_CFR_ROOT			= 0x0047,
+	LB_TAG_ROOT_BRIDGE_INFO		= 0x0048,
 	/* The following options are CMOS-related */
 	LB_TAG_CMOS_OPTION_TABLE	= 0x00c8,
 	LB_TAG_OPTION			= 0x00c9,
diff --git a/src/lib/coreboot_table.c b/src/lib/coreboot_table.c
index d8ecdce868..85c5675507 100644
--- a/src/lib/coreboot_table.c
+++ b/src/lib/coreboot_table.c
@@ -274,6 +274,7 @@ static void add_cbmem_pointers(struct lb_header *header)
 		{CBMEM_ID_FMAP, LB_TAG_FMAP},
 		{CBMEM_ID_VBOOT_WORKBUF, LB_TAG_VBOOT_WORKBUF},
 		{CBMEM_ID_TYPE_C_INFO, LB_TAG_TYPE_C_INFO},
+		{CBMEM_ID_RB_INFO, LB_TAG_ROOT_BRIDGE_INFO},
 	};
 	int i;
 

From f4fe5514fed2da762958396285670aee66e9769e Mon Sep 17 00:00:00 2001
From: Ian Feng <ian_feng@compal.corp-partner.google.com>
Date: Thu, 8 Jan 2026 10:44:53 +0800
Subject: [PATCH 2984/3886] mb/google/ocelot/var/kodkod: Update gpio settings
 for NC pins

- Remove unused I2C3 pin configurations.
- Remove RST control. The ETU925 fingerprint module does not
  need to control the RST pin.

BUG=b:452542491, b:467835297
TEST=emerge-ocelot coreboot

Change-Id: Ib4db733187d1b15f89654b53c1cf98420d652546
Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90696
Reviewed-by: Pranava Y N <pranavayn@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
---
 .../google/ocelot/variants/kodkod/gpio.c       | 18 ++++++------------
 1 file changed, 6 insertions(+), 12 deletions(-)

diff --git a/src/mainboard/google/ocelot/variants/kodkod/gpio.c b/src/mainboard/google/ocelot/variants/kodkod/gpio.c
index e8884d9c43..2259bda8c7 100644
--- a/src/mainboard/google/ocelot/variants/kodkod/gpio.c
+++ b/src/mainboard/google/ocelot/variants/kodkod/gpio.c
@@ -125,8 +125,8 @@ static const struct pad_config gpio_table[] = {
 	PAD_NC(GPP_C13, NONE),
 	/* GPP_C14:     NC */
 	PAD_NC(GPP_C14, NONE),
-	/* GPP_C15:     SOC_FPS_RST# */
-	PAD_CFG_GPO_LOCK(GPP_C15, 1, LOCK_CONFIG),
+	/* GPP_C15:     NC */
+	PAD_NC(GPP_C15, NONE),
 	/* GPP_C16:     NC */
 	PAD_NC(GPP_C16, NONE),
 	/* GPP_C17:     NC */
@@ -279,10 +279,10 @@ static const struct pad_config gpio_table[] = {
 	PAD_NC(GPP_H04, NONE),
 	/* GPP_H05:     NC */
 	PAD_NC(GPP_H05, NONE),
-	/* GPP_H06:     SOC_I2C_3_SDA_iPCM */
-	PAD_CFG_NF(GPP_H06, NONE, DEEP, NF1),
-	/* GPP_H07:     SOC_I2C_3_SCL_iPCM */
-	PAD_CFG_NF(GPP_H07, NONE, DEEP, NF1),
+	/* GPP_H06:     NC */
+	PAD_NC(GPP_H06, NONE),
+	/* GPP_H07:     NC */
+	PAD_NC(GPP_H07, NONE),
 	/* GPP_H08:     UART_0_CRXD_DTXD */
 	PAD_CFG_NF(GPP_H08, NONE, DEEP, NF1),
 	/* GPP_H09:     UART_0_CTXD_DRXD */
@@ -372,10 +372,6 @@ static const struct pad_config gpio_table[] = {
 static const struct pad_config early_gpio_table[] = {
 	/* GPP_B17:     SOC_SPI_TPM_INT# */
 	PAD_CFG_GPI_APIC_LOCK(GPP_B17, NONE, LEVEL, INVERT, LOCK_CONFIG),
-	/* GPP_H06: SOC_I2C_3_SDA_iPCM */
-	PAD_CFG_NF(GPP_H06, NONE, DEEP, NF1),
-	/* GPP_H07: SOC_I2C_3_SCL_iPCM */
-	PAD_CFG_NF(GPP_H07, NONE, DEEP, NF1),
 	/* GPP_H08:     UART_0_CRXD_DTXD */
 	PAD_CFG_NF(GPP_H08, NONE, DEEP, NF1),
 	/* GPP_H09:     UART_0_CTXD_DRXD */
@@ -392,8 +388,6 @@ static const struct pad_config romstage_gpio_table[] = {
 	PAD_CFG_NF(GPP_C00, NONE, DEEP, NF1),
 	/* GPP_C01:     SPD_SOC_SMBDATA */
 	PAD_CFG_NF(GPP_C01, NONE, DEEP, NF1),
-	/* GPP_C15:     FPS_RST_N */
-	PAD_CFG_GPO(GPP_C15, 0, PLTRST),
 };
 
 const struct pad_config *variant_gpio_table(size_t *num)

From 829b8be43202b960d5be066cbd8c6ba25552a1d0 Mon Sep 17 00:00:00 2001
From: Tomasz Michalec <tmichalec@google.com>
Date: Thu, 13 Nov 2025 16:07:19 +0100
Subject: [PATCH 2985/3886] libpayload: Add bulk with timeout callback to USB

Add bulk_timeout() callback to USB controllers that allows to issue bulk
transaction with configurable timeout. This allows to peek if there is
any incoming data from USB device without needing to wait 5 seconds if
there is no data.

'finalize' argument is omitted in bulk_timeout(), because any recent
controller doesn't use it in bulk() method anyway. For OHCI and UHCI,
which are only controllers using 'finalize', issuing bulk_timeout() with
USB_MAX_PROCESSING_TIME_US timeout is the same as issuing bulk() with
'finalize' set to zero.

Change-Id: I82dbe307b566e4fc6cca314924168f7ad677efe7
Signed-off-by: Tomasz Michalec <tmichalec@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90043
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
---
 payloads/libpayload/drivers/usb/dwc2.c        | 49 ++++++++++++-------
 .../libpayload/drivers/usb/dwc2_private.h     |  1 -
 payloads/libpayload/drivers/usb/ehci.c        | 26 ++++++----
 payloads/libpayload/drivers/usb/ohci.c        | 28 ++++++++---
 payloads/libpayload/drivers/usb/uhci.c        | 40 ++++++++++-----
 payloads/libpayload/drivers/usb/xhci.c        | 24 +++++----
 .../libpayload/drivers/usb/xhci_commands.c    |  2 +-
 payloads/libpayload/drivers/usb/xhci_events.c | 15 +++---
 .../libpayload/drivers/usb/xhci_private.h     |  6 +--
 payloads/libpayload/include/usb/usb.h         | 10 ++++
 10 files changed, 134 insertions(+), 67 deletions(-)

diff --git a/payloads/libpayload/drivers/usb/dwc2.c b/payloads/libpayload/drivers/usb/dwc2.c
index e0b290f58c..5d9bd4cb59 100644
--- a/payloads/libpayload/drivers/usb/dwc2.c
+++ b/payloads/libpayload/drivers/usb/dwc2.c
@@ -152,13 +152,13 @@ static int dwc2_disconnected(hci_t *controller)
  * or an error code if the transfer failed
  */
 static int
-wait_for_complete(endpoint_t *ep, uint32_t ch_num)
+wait_for_complete(endpoint_t *ep, uint32_t ch_num, int timeout_us)
 {
 	hcint_t hcint;
 	hcchar_t hcchar;
 	hctsiz_t hctsiz;
 	dwc2_reg_t *reg = DWC2_REG(ep->dev->controller);
-	int timeout = USB_MAX_PROCESSING_TIME_US / DWC2_SLEEP_TIME_US;
+	int timeout = timeout_us / DWC2_SLEEP_TIME_US;
 
 	/*
 	 * TODO: We should take care of up to three times of transfer error
@@ -211,12 +211,12 @@ wait_for_complete(endpoint_t *ep, uint32_t ch_num)
 	hcint.d32 = ~0;
 	writel(hcint.d32, &reg->host.hchn[ch_num].hcintn);
 
-	return -HCSTAT_TIMEOUT;
+	return USB_TIMEOUT;
 }
 
 static int
 dwc2_do_xfer(endpoint_t *ep, int size, int pid, ep_dir_t dir,
-	     uint32_t ch_num, u8 *data_buf, int *short_pkt)
+	     uint32_t ch_num, u8 *data_buf, int *short_pkt, int timeout_us)
 {
 	uint32_t do_copy;
 	int ret;
@@ -279,7 +279,7 @@ dwc2_do_xfer(endpoint_t *ep, int size, int pid, ep_dir_t dir,
 		&reg->host.hchn[ch_num].hcdman);
 	writel(hcchar.d32, &reg->host.hchn[ch_num].hccharn);
 
-	ret = wait_for_complete(ep, ch_num);
+	ret = wait_for_complete(ep, ch_num, timeout_us);
 
 	if (ret >= 0) {
 		/* Calculate actual transferred length */
@@ -307,7 +307,7 @@ dwc2_do_xfer(endpoint_t *ep, int size, int pid, ep_dir_t dir,
 static int
 dwc2_split_transfer(endpoint_t *ep, int size, int pid, ep_dir_t dir,
 		    uint32_t ch_num, u8 *data_buf, split_info_t *split,
-		    int *short_pkt)
+		    int *short_pkt, int timeout_us)
 {
 	dwc2_reg_t *reg = DWC2_REG(ep->dev->controller);
 	hfnum_t hfnum;
@@ -331,7 +331,7 @@ dwc2_split_transfer(endpoint_t *ep, int size, int pid, ep_dir_t dir,
 
 	/* Handle Start-Split */
 	ret = dwc2_do_xfer(ep, dir == EPDIR_IN ? 0 : size, pid, dir, ch_num,
-			   data_buf, NULL);
+			   data_buf, NULL, timeout_us);
 	if (ret < 0)
 		goto out;
 
@@ -346,7 +346,7 @@ dwc2_split_transfer(endpoint_t *ep, int size, int pid, ep_dir_t dir,
 	/* Handle Complete-Split */
 	do {
 		ret = dwc2_do_xfer(ep, dir == EPDIR_OUT ? 0 : size, ep->toggle,
-				   dir, ch_num, data_buf, short_pkt);
+				   dir, ch_num, data_buf, short_pkt, timeout_us);
 	} while (ret == -HCSTAT_NYET);
 
 	if (dir == EPDIR_IN)
@@ -379,11 +379,11 @@ static int dwc2_need_split(usbdev_t *dev, split_info_t *split)
 
 static int
 dwc2_transfer(endpoint_t *ep, int size, int pid, ep_dir_t dir, uint32_t ch_num,
-	      u8 *src, uint8_t skip_nak)
+	      u8 *src, uint8_t skip_nak, int timeout_us)
 {
 	split_info_t split;
 	int ret, short_pkt, transferred = 0;
-	int timeout = USB_MAX_PROCESSING_TIME_US / USB_FULL_LOW_SPEED_FRAME_US;
+	int timeout = timeout_us / USB_FULL_LOW_SPEED_FRAME_US;
 
 	ep->toggle = pid;
 
@@ -393,7 +393,7 @@ dwc2_transfer(endpoint_t *ep, int size, int pid, ep_dir_t dir, uint32_t ch_num,
 nak_retry:
 			ret = dwc2_split_transfer(ep, MIN(ep->maxpacketsize,
 			      size), ep->toggle, dir, 0, src, &split,
-			      &short_pkt);
+			      &short_pkt, timeout_us);
 
 			/*
 			 * dwc2_split_transfer() waits for the next FullSpeed
@@ -403,10 +403,12 @@ nak_retry:
 			if (ret == -HCSTAT_NAK && !skip_nak && --timeout) {
 				udelay(USB_FULL_LOW_SPEED_FRAME_US / 2);
 				goto nak_retry;
+			} else if (timeout <= 0 && ret < 0) {
+				return USB_TIMEOUT;
 			}
 		} else {
 			ret = dwc2_do_xfer(ep, MIN(DMA_SIZE, size), pid, dir, 0,
-			      src, &short_pkt);
+			      src, &short_pkt, timeout_us);
 		}
 
 		if (ret < 0)
@@ -422,7 +424,7 @@ nak_retry:
 }
 
 static int
-dwc2_bulk(endpoint_t *ep, int size, u8 *src, int finalize)
+dwc2_bulk_timeout(endpoint_t *ep, int size, u8 *src, int timeout_us)
 {
 	ep_dir_t data_dir;
 
@@ -433,7 +435,13 @@ dwc2_bulk(endpoint_t *ep, int size, u8 *src, int finalize)
 	else
 		return -1;
 
-	return dwc2_transfer(ep, size, ep->toggle, data_dir, 0, src, 0);
+	return dwc2_transfer(ep, size, ep->toggle, data_dir, 0, src, 0, timeout_us);
+}
+
+static int
+dwc2_bulk(endpoint_t *ep, int size, u8 *src, int finalize)
+{
+	return dwc2_bulk_timeout(ep, size, src, USB_MAX_PROCESSING_TIME_US);
 }
 
 static int
@@ -452,19 +460,22 @@ dwc2_control(usbdev_t *dev, direction_t dir, int drlen, void *setup,
 		return -1;
 
 	/* Setup Phase */
-	if (dwc2_transfer(ep, drlen, PID_SETUP, EPDIR_OUT, 0, setup, 0) < 0)
+	if (dwc2_transfer(ep, drlen, PID_SETUP, EPDIR_OUT, 0, setup, 0,
+			  USB_MAX_PROCESSING_TIME_US) < 0)
 		return -1;
 
 	/* Data Phase */
 	ep->toggle = PID_DATA1;
 	if (dalen > 0) {
-		ret = dwc2_transfer(ep, dalen, ep->toggle, data_dir, 0, src, 0);
+		ret = dwc2_transfer(ep, dalen, ep->toggle, data_dir, 0, src, 0,
+				    USB_MAX_PROCESSING_TIME_US);
 		if (ret < 0)
 			return -1;
 	}
 
 	/* Status Phase */
-	if (dwc2_transfer(ep, 0, PID_DATA1, !data_dir, 0, NULL, 0) < 0)
+	if (dwc2_transfer(ep, 0, PID_DATA1, !data_dir, 0, NULL, 0,
+			  USB_MAX_PROCESSING_TIME_US) < 0)
 		return -1;
 
 	return ret;
@@ -482,7 +493,8 @@ dwc2_intr(endpoint_t *ep, int size, u8 *src)
 	else
 		return -1;
 
-	return dwc2_transfer(ep, size, ep->toggle, data_dir, 0, src, 1);
+	return dwc2_transfer(ep, size, ep->toggle, data_dir, 0, src, 1,
+			     USB_MAX_PROCESSING_TIME_US);
 }
 
 static u32 dwc2_intr_get_timestamp(intr_queue_t *q)
@@ -583,6 +595,7 @@ hci_t *dwc2_init(void *bar)
 	controller->init = dwc2_reinit;
 	controller->shutdown = dwc2_shutdown;
 	controller->bulk = dwc2_bulk;
+	controller->bulk_timeout = dwc2_bulk_timeout;
 	controller->control = dwc2_control;
 	controller->set_address = generic_set_address;
 	controller->finish_device_config = NULL;
diff --git a/payloads/libpayload/drivers/usb/dwc2_private.h b/payloads/libpayload/drivers/usb/dwc2_private.h
index 3616ff3d10..86c9da2fa8 100644
--- a/payloads/libpayload/drivers/usb/dwc2_private.h
+++ b/payloads/libpayload/drivers/usb/dwc2_private.h
@@ -48,7 +48,6 @@ typedef enum {
 	HCSTAT_NAK,
 	HCSTAT_NYET,
 	HCSTAT_UNKNOW,
-	HCSTAT_TIMEOUT,
 	HCSTAT_DISCONNECTED,
 } hcstat_t;
 #endif
diff --git a/payloads/libpayload/drivers/usb/ehci.c b/payloads/libpayload/drivers/usb/ehci.c
index 822fdb19a9..fe3186d5ca 100644
--- a/payloads/libpayload/drivers/usb/ehci.c
+++ b/payloads/libpayload/drivers/usb/ehci.c
@@ -249,23 +249,25 @@ static void free_qh_and_tds(ehci_qh_t *qh, qtd_t *cur)
 
 #define EHCI_SLEEP_TIME_US	50
 
-static int wait_for_tds(qtd_t *head)
+static int wait_for_tds(qtd_t *head, int timeout_us)
 {
-	/* returns the amount of bytes *not* transmitted, or -1 for error */
+	/* returns the amount of bytes *not* transmitted, USB_TIMEOUT on timeout,
+	 * or -1 for error
+	 */
 	int result = 0;
 	qtd_t *cur = head;
 	while (1) {
 		if (0) dump_td(virt_to_phys(cur));
 
 		/* wait for results */
-		int timeout = USB_MAX_PROCESSING_TIME_US / EHCI_SLEEP_TIME_US;
+		int timeout = timeout_us / EHCI_SLEEP_TIME_US;
 		while ((cur->token & QTD_ACTIVE) && !(cur->token & QTD_HALTED)
 				&& timeout--)
 			udelay(EHCI_SLEEP_TIME_US);
 		if (timeout < 0) {
 			usb_debug("Error: ehci: queue transfer "
 				"processing timed out.\n");
-			return -1;
+			return USB_TIMEOUT;
 		}
 		if (cur->token & QTD_HALTED) {
 			usb_debug("ERROR with packet\n");
@@ -319,7 +321,7 @@ static int ehci_set_async_schedule(ehci_t *ehcic, int enable)
 }
 
 static int ehci_process_async_schedule(
-		ehci_t *ehcic, ehci_qh_t *qhead, qtd_t *head)
+		ehci_t *ehcic, ehci_qh_t *qhead, qtd_t *head, int timeout_us)
 {
 	int result;
 
@@ -333,7 +335,7 @@ static int ehci_process_async_schedule(
 	if (ehci_set_async_schedule(ehcic, 1)) return -1;
 
 	/* wait for result */
-	result = wait_for_tds(head);
+	result = wait_for_tds(head, timeout_us);
 
 	/* disable async schedule */
 	ehci_set_async_schedule(ehcic, 0);
@@ -341,7 +343,7 @@ static int ehci_process_async_schedule(
 	return result;
 }
 
-static int ehci_bulk(endpoint_t *ep, int size, u8 *src, int finalize)
+static int ehci_bulk_timeout(endpoint_t *ep, int size, u8 *src, int timeout_us)
 {
 	int result = 0;
 	u8 *end = src + size;
@@ -410,7 +412,7 @@ static int ehci_bulk(endpoint_t *ep, int size, u8 *src, int finalize)
 	head->token |= (ep->toggle?QTD_TOGGLE_DATA1:0);
 
 	result = ehci_process_async_schedule(
-			EHCI_INST(ep->dev->controller), qh, head);
+			EHCI_INST(ep->dev->controller), qh, head, timeout_us);
 	if (result >= 0) {
 		result = size - result;
 		if (pid == EHCI_IN && end != src + size)
@@ -429,6 +431,11 @@ oom:
 	return -1;
 }
 
+static int ehci_bulk(endpoint_t *ep, int size, u8 *src, int finalize)
+{
+	return ehci_bulk_timeout(ep, size, src, USB_MAX_PROCESSING_TIME_US);
+}
+
 /* FIXME: Handle control transfers as 3 QHs, so the 2nd stage can be >0x4000 bytes */
 static int ehci_control(usbdev_t *dev, direction_t dir, int drlen, void *setup,
 			 int dalen, u8 *src)
@@ -530,7 +537,7 @@ static int ehci_control(usbdev_t *dev, direction_t dir, int drlen, void *setup,
 	qh->td.next_qtd = virt_to_phys(head);
 
 	result = ehci_process_async_schedule(
-			EHCI_INST(dev->controller), qh, head);
+			EHCI_INST(dev->controller), qh, head, USB_MAX_PROCESSING_TIME_US);
 	if (result >= 0) {
 		result = dalen - result;
 		if (dir == IN && data != src)
@@ -784,6 +791,7 @@ ehci_init(unsigned long physical_bar)
 	controller->init = ehci_reinit;
 	controller->shutdown = ehci_shutdown;
 	controller->bulk = ehci_bulk;
+	controller->bulk_timeout = ehci_bulk_timeout;
 	controller->control = ehci_control;
 	controller->set_address = generic_set_address;
 	controller->finish_device_config = NULL;
diff --git a/payloads/libpayload/drivers/usb/ohci.c b/payloads/libpayload/drivers/usb/ohci.c
index 79add33fe7..55bdf66826 100644
--- a/payloads/libpayload/drivers/usb/ohci.c
+++ b/payloads/libpayload/drivers/usb/ohci.c
@@ -39,6 +39,7 @@ static void ohci_stop(hci_t *controller);
 static void ohci_reset(hci_t *controller);
 static void ohci_shutdown(hci_t *controller);
 static int ohci_bulk(endpoint_t *ep, int size, u8 *data, int finalize);
+static int ohci_bulk_timeout(endpoint_t *ep, int size, u8 *data, int timeout_us);
 static int ohci_control(usbdev_t *dev, direction_t dir, int drlen, void *devreq,
 			 int dalen, u8 *data);
 static void* ohci_create_intr_queue(endpoint_t *ep, int reqsize, int reqcount, int reqtiming);
@@ -181,6 +182,7 @@ ohci_init(unsigned long physical_bar)
 	controller->init = ohci_reinit;
 	controller->shutdown = ohci_shutdown;
 	controller->bulk = ohci_bulk;
+	controller->bulk_timeout = ohci_bulk_timeout;
 	controller->control = ohci_control;
 	controller->set_address = generic_set_address;
 	controller->finish_device_config = NULL;
@@ -295,10 +297,10 @@ ohci_stop(hci_t *controller)
 #define OHCI_SLEEP_TIME_US	1000
 
 static int
-wait_for_ed(usbdev_t *dev, ed_t *head, int pages)
+wait_for_ed(usbdev_t *dev, ed_t *head, int pages, int timeout_us)
 {
 	/* wait for results */
-	int timeout = USB_MAX_PROCESSING_TIME_US / OHCI_SLEEP_TIME_US;
+	int timeout = timeout_us / OHCI_SLEEP_TIME_US;
 	while (((head->head_pointer & ~3) != head->tail_pointer) &&
 		!(head->head_pointer & 1) &&
 		((((td_t*)phys_to_virt(head->head_pointer & ~3))->config
@@ -326,7 +328,7 @@ wait_for_ed(usbdev_t *dev, ed_t *head, int pages)
 		usb_debug("HALTED!\n");
 		return -1;
 	}
-	return result;
+	return timeout <= 0 ? USB_TIMEOUT : result;
 }
 
 static void
@@ -481,7 +483,8 @@ ohci_control(usbdev_t *dev, direction_t dir, int drlen, void *setup, int dalen,
 	OHCI_INST(dev->controller)->opreg->HcCommandStatus = ControlListFilled;
 
 	int result = wait_for_ed(dev, head,
-			(dalen == 0)?0:(last_page - first_page + 1));
+			(dalen == 0)?0:(last_page - first_page + 1),
+			USB_MAX_PROCESSING_TIME_US);
 	/* Wait some frames before and one after disabling list access. */
 	mdelay(4);
 	OHCI_INST(dev->controller)->opreg->HcControl &= ~ControlListEnable;
@@ -501,7 +504,7 @@ ohci_control(usbdev_t *dev, direction_t dir, int drlen, void *setup, int dalen,
 
 /* finalize == 1: if data is of packet aligned size, add a zero length packet */
 static int
-ohci_bulk(endpoint_t *ep, int dalen, u8 *src, int finalize)
+ohci_bulk_finalize_timeout(endpoint_t *ep, int dalen, u8 *src, int finalize, int timeout_us)
 {
 	int i;
 	td_t *cur, *next;
@@ -608,7 +611,7 @@ ohci_bulk(endpoint_t *ep, int dalen, u8 *src, int finalize)
 	OHCI_INST(ep->dev->controller)->opreg->HcCommandStatus = BulkListFilled;
 
 	int result = wait_for_ed(ep->dev, head,
-			(dalen == 0)?0:(last_page - first_page + 1));
+			(dalen == 0)?0:(last_page - first_page + 1), timeout_us);
 	/* Wait some frames before and one after disabling list access. */
 	mdelay(4);
 	OHCI_INST(ep->dev->controller)->opreg->HcControl &= ~BulkListEnable;
@@ -628,6 +631,19 @@ ohci_bulk(endpoint_t *ep, int dalen, u8 *src, int finalize)
 	return result;
 }
 
+static int
+ohci_bulk_timeout(endpoint_t *ep, int dalen, u8 *src, int timeout_us)
+{
+	/* usbdev_hc bulk_timeout API doesn't have finalize argument. Assume it should be 0. */
+	return ohci_bulk_finalize_timeout(ep, dalen, src, 0, timeout_us);
+}
+
+static int
+ohci_bulk(endpoint_t *ep, int dalen, u8 *src, int finalize)
+{
+	return ohci_bulk_finalize_timeout(ep, dalen, src, finalize, USB_MAX_PROCESSING_TIME_US);
+}
+
 struct _intr_queue;
 
 struct _intrq_td {
diff --git a/payloads/libpayload/drivers/usb/uhci.c b/payloads/libpayload/drivers/usb/uhci.c
index 7590ab3c85..53fb123c8c 100644
--- a/payloads/libpayload/drivers/usb/uhci.c
+++ b/payloads/libpayload/drivers/usb/uhci.c
@@ -39,6 +39,7 @@ static void uhci_stop(hci_t *controller);
 static void uhci_reset(hci_t *controller);
 static void uhci_shutdown(hci_t *controller);
 static int uhci_bulk(endpoint_t *ep, int size, u8 *data, int finalize);
+static int uhci_bulk_timeout(endpoint_t *ep, int size, u8 *data, int timeout_us);
 static int uhci_control(usbdev_t *dev, direction_t dir, int drlen, void *devreq,
 			 int dalen, u8 *data);
 static void* uhci_create_intr_queue(endpoint_t *ep, int reqsize, int reqcount, int reqtiming);
@@ -162,6 +163,7 @@ uhci_pci_init(pcidev_t addr)
 	controller->init = uhci_reinit;
 	controller->shutdown = uhci_shutdown;
 	controller->bulk = uhci_bulk;
+	controller->bulk_timeout = uhci_bulk_timeout;
 	controller->control = uhci_control;
 	controller->set_address = generic_set_address;
 	controller->finish_device_config = NULL;
@@ -273,23 +275,23 @@ uhci_stop(hci_t *controller)
 }
 
 #define UHCI_SLEEP_TIME_US 30
-#define UHCI_TIMEOUT (USB_MAX_PROCESSING_TIME_US / UHCI_SLEEP_TIME_US)
 #define GET_TD(x) ((void *)(((unsigned long)(x))&~0xf))
 
 static td_t *
-wait_for_completed_qh(hci_t *controller, qh_t *qh)
+wait_for_completed_qh(hci_t *controller, qh_t *qh, int *timeout_us)
 {
-	int timeout = UHCI_TIMEOUT;
+	int timeout = *timeout_us / UHCI_SLEEP_TIME_US;
 	void *current = GET_TD(qh->elementlinkptr);
 	while (((qh->elementlinkptr & FLISTP_TERMINATE) == 0) && (timeout-- > 0)) {
 		if (current != GET_TD(qh->elementlinkptr)) {
 			current = GET_TD(qh->elementlinkptr);
-			timeout = UHCI_TIMEOUT;
+			timeout = *timeout_us / UHCI_SLEEP_TIME_US;
 		}
 		uhci_reg_write16(controller, USBSTS,
 				 uhci_reg_read16(controller, USBSTS) | 0);	// clear resettable registers
 		udelay(UHCI_SLEEP_TIME_US);
 	}
+	*timeout_us = timeout * UHCI_SLEEP_TIME_US;
 	return (GET_TD(qh->elementlinkptr) ==
 		0) ? 0 : GET_TD(phys_to_virt(qh->elementlinkptr));
 }
@@ -370,9 +372,10 @@ uhci_control(usbdev_t *dev, direction_t dir, int drlen, void *devreq, const int
 		TD_STATUS_ACTIVE;
 	UHCI_INST(dev->controller)->qh_data->elementlinkptr =
 		virt_to_phys(tds) & ~(FLISTP_QH | FLISTP_TERMINATE);
+	int timeout_us = USB_MAX_PROCESSING_TIME_US;
 	td_t *td = wait_for_completed_qh(dev->controller,
 					  UHCI_INST(dev->controller)->
-					  qh_data);
+					  qh_data, &timeout_us);
 	int result;
 	if (td == 0) {
 		result = dalen; /* TODO: We should return the actually transferred length. */
@@ -423,23 +426,24 @@ fill_schedule(td_t *td, endpoint_t *ep, int length, unsigned char *data,
 }
 
 static int
-run_schedule(usbdev_t *dev, td_t *td)
+run_schedule(usbdev_t *dev, td_t *td, int timeout_us)
 {
 	UHCI_INST(dev->controller)->qh_data->elementlinkptr =
 		virt_to_phys(td) & ~(FLISTP_QH | FLISTP_TERMINATE);
 	td = wait_for_completed_qh(dev->controller,
-				    UHCI_INST(dev->controller)->qh_data);
+				    UHCI_INST(dev->controller)->qh_data, &timeout_us);
 	if (td == 0) {
 		return 0;
 	} else {
 		td_dump(td);
-		return 1;
+		return timeout_us <= 0 ? USB_TIMEOUT : -2;
 	}
 }
 
 /* finalize == 1: if data is of packet aligned size, add a zero length packet */
 static int
-uhci_bulk(endpoint_t *ep, const int dalen, u8 *data, int finalize)
+uhci_bulk_finalize_timeout(endpoint_t *ep, const int dalen, u8 *data, int finalize,
+			   int timeout_us)
 {
 	int maxpsize = ep->maxpacketsize;
 	if (maxpsize == 0)
@@ -460,15 +464,29 @@ uhci_bulk(endpoint_t *ep, const int dalen, u8 *data, int finalize)
 		data += maxpsize;
 		len_left -= maxpsize;
 	}
-	if (run_schedule(ep->dev, tds) == 1) {
+	int ret = run_schedule(ep->dev, tds, timeout_us);
+	if (ret) {
 		free(tds);
-		return -1;
+		return ret;
 	}
 	ep->toggle = toggle;
 	free(tds);
 	return dalen; /* TODO: We should return the actually transferred length. */
 }
 
+static int
+uhci_bulk_timeout(endpoint_t *ep, int dalen, u8 *src, int timeout_us)
+{
+	/* usbdev_hc bulk_timeout API doesn't have finalize argument. Assume it should be 0. */
+	return uhci_bulk_finalize_timeout(ep, dalen, src, 0, timeout_us);
+}
+
+static int
+uhci_bulk(endpoint_t *ep, const int dalen, u8 *data, int finalize)
+{
+	return uhci_bulk_finalize_timeout(ep, dalen, data, finalize, USB_MAX_PROCESSING_TIME_US);
+}
+
 typedef struct {
 	qh_t *qh;
 	td_t *tds;
diff --git a/payloads/libpayload/drivers/usb/xhci.c b/payloads/libpayload/drivers/usb/xhci.c
index e9a7ead18b..2f9206efd5 100644
--- a/payloads/libpayload/drivers/usb/xhci.c
+++ b/payloads/libpayload/drivers/usb/xhci.c
@@ -40,6 +40,7 @@ static void xhci_reset(hci_t *controller);
 static void xhci_reinit(hci_t *controller);
 static void xhci_shutdown(hci_t *controller);
 static int xhci_bulk(endpoint_t *ep, int size, u8 *data, int finalize);
+static int xhci_bulk_timeout(endpoint_t *ep, int size, u8 *data, int timeout_us);
 static int xhci_control(usbdev_t *dev, direction_t dir, int drlen, void *devreq,
 			 int dalen, u8 *data);
 static void* xhci_create_intr_queue(endpoint_t *ep, int reqsize, int reqcount, int reqtiming);
@@ -168,6 +169,7 @@ xhci_init(unsigned long physical_bar)
 	controller->init		= xhci_reinit;
 	controller->shutdown		= xhci_shutdown;
 	controller->bulk		= xhci_bulk;
+	controller->bulk_timeout	= xhci_bulk_timeout;
 	controller->control		= xhci_control;
 	controller->set_address		= xhci_set_address;
 	controller->finish_device_config = xhci_finish_device_config;
@@ -705,10 +707,11 @@ xhci_control(usbdev_t *const dev, const direction_t dir,
 	int i, transferred = 0;
 	const int n_stages = 2 + !!dalen;
 	for (i = 0; i < n_stages; ++i) {
-		const int ret = xhci_wait_for_transfer(xhci, dev->address, 1);
+		const int ret = xhci_wait_for_transfer(xhci, dev->address, 1,
+						       USB_MAX_PROCESSING_TIME_US);
 		transferred += ret;
 		if (ret < 0) {
-			if (ret == TIMEOUT) {
+			if (ret == USB_TIMEOUT) {
 				xhci_debug("Stopping ID %d EP 1\n",
 					   dev->address);
 				xhci_cmd_stop_endpoint(xhci, dev->address, 1);
@@ -732,14 +735,10 @@ xhci_control(usbdev_t *const dev, const direction_t dir,
 	return transferred;
 }
 
-/* finalize == 1: if data is of packet aligned size, add a zero length packet */
 static int
-xhci_bulk(endpoint_t *const ep, const int size, u8 *const src,
-	  const int finalize)
+xhci_bulk_timeout(endpoint_t *const ep, const int size, u8 *const src,
+		  int timeout_us)
 {
-	/* finalize: Hopefully the xHCI controller always does this.
-		     We have no control over the packets. */
-
 	u8 *data = src;
 	xhci_t *const xhci = XHCI_INST(ep->dev->controller);
 	const int slot_id = ep->dev->address;
@@ -777,9 +776,9 @@ xhci_bulk(endpoint_t *const ep, const int size, u8 *const src,
 	xhci_ring_doorbell(ep);
 
 	/* Wait for transfer event */
-	const int ret = xhci_wait_for_transfer(xhci, ep->dev->address, ep_id);
+	const int ret = xhci_wait_for_transfer(xhci, ep->dev->address, ep_id, timeout_us);
 	if (ret < 0) {
-		if (ret == TIMEOUT) {
+		if (ret == USB_TIMEOUT) {
 			xhci_debug("Stopping ID %d EP %d\n",
 				   ep->dev->address, ep_id);
 			xhci_cmd_stop_endpoint(xhci, ep->dev->address, ep_id);
@@ -798,6 +797,11 @@ xhci_bulk(endpoint_t *const ep, const int size, u8 *const src,
 	return ret;
 }
 
+static int xhci_bulk(endpoint_t *ep, int size, u8 *data, int finalize)
+{
+	return xhci_bulk_timeout(ep, size, data, USB_MAX_PROCESSING_TIME_US);
+}
+
 static trb_t *
 xhci_next_trb(trb_t *cur, int *const pcs)
 {
diff --git a/payloads/libpayload/drivers/usb/xhci_commands.c b/payloads/libpayload/drivers/usb/xhci_commands.c
index a4078030c6..1cebb5432a 100644
--- a/payloads/libpayload/drivers/usb/xhci_commands.c
+++ b/payloads/libpayload/drivers/usb/xhci_commands.c
@@ -69,7 +69,7 @@ xhci_wait_for_command(xhci_t *const xhci,
 	int cc;
 
 	cc = xhci_wait_for_command_done(xhci, cmd_trb, clear_event);
-	if (cc != TIMEOUT)
+	if (cc != USB_TIMEOUT)
 		return cc;
 
 	/* Abort command on timeout */
diff --git a/payloads/libpayload/drivers/usb/xhci_events.c b/payloads/libpayload/drivers/usb/xhci_events.c
index 139ea59619..3c36a31355 100644
--- a/payloads/libpayload/drivers/usb/xhci_events.c
+++ b/payloads/libpayload/drivers/usb/xhci_events.c
@@ -232,7 +232,7 @@ xhci_wait_for_event_type(xhci_t *const xhci,
  *
  * Process events from xHCI Abort command.
  *
- * Returns CC_COMMAND_RING_STOPPED on success and TIMEOUT on failure.
+ * Returns CC_COMMAND_RING_STOPPED on success and USB_TIMEOUT on failure.
  */
 
 int
@@ -244,7 +244,7 @@ xhci_wait_for_command_aborted(xhci_t *const xhci, const trb_t *const address)
 	 * what to do then.
 	 */
 	unsigned long timeout_us = USB_MAX_PROCESSING_TIME_US; /* 5s */
-	int cc = TIMEOUT;
+	int cc = USB_TIMEOUT;
 	/*
 	 * Expects two command completion events:
 	 * The first with CC == COMMAND_ABORTED should point to address
@@ -292,7 +292,7 @@ update_and_return:
 
 /*
  * returns cc of command in question (pointed to by `address`)
- * caller should abort command if cc is TIMEOUT
+ * caller should abort command if cc is USB_TIMEOUT
  */
 int
 xhci_wait_for_command_done(xhci_t *const xhci,
@@ -300,7 +300,7 @@ xhci_wait_for_command_done(xhci_t *const xhci,
 			   const int clear_event)
 {
 	unsigned long timeout_us = USB_MAX_PROCESSING_TIME_US; /* 5s */
-	int cc = TIMEOUT;
+	int cc = USB_TIMEOUT;
 	while (xhci_wait_for_event_type(xhci, TRB_EV_CMD_CMPL, &timeout_us)) {
 		if ((xhci->er.cur->ptr_low == virt_to_phys(address)) &&
 				(xhci->er.cur->ptr_high == 0)) {
@@ -321,12 +321,11 @@ xhci_wait_for_command_done(xhci_t *const xhci,
 
 /* returns amount of bytes transferred on success, negative CC on error */
 int
-xhci_wait_for_transfer(xhci_t *const xhci, const int slot_id, const int ep_id)
+xhci_wait_for_transfer(xhci_t *const xhci, const int slot_id, const int ep_id,
+		       unsigned long timeout_us)
 {
 	xhci_spew("Waiting for transfer on ID %d EP %d\n", slot_id, ep_id);
-	/* 5s for all types of transfers */
-	unsigned long timeout_us = USB_MAX_PROCESSING_TIME_US;
-	int ret = TIMEOUT;
+	int ret = USB_TIMEOUT;
 	while (xhci_wait_for_event_type(xhci, TRB_EV_TRANSFER, &timeout_us)) {
 		if (TRB_GET(ID, xhci->er.cur) == slot_id &&
 				TRB_GET(EP, xhci->er.cur) == ep_id) {
diff --git a/payloads/libpayload/drivers/usb/xhci_private.h b/payloads/libpayload/drivers/usb/xhci_private.h
index 45c301391e..c9464ce423 100644
--- a/payloads/libpayload/drivers/usb/xhci_private.h
+++ b/payloads/libpayload/drivers/usb/xhci_private.h
@@ -45,8 +45,7 @@
 
 #define MASK(startbit, lenbit) (((1<<(lenbit))-1)<<(startbit))
 
-/* Make these high enough to not collide with negative XHCI CCs */
-#define TIMEOUT			-65
+/* Make these high enough to not collide with negative XHCI CCs and generic USB_TIMEOUT */
 #define CONTROLLER_ERROR	-66
 #define COMMUNICATION_ERROR	-67
 #define OUT_OF_MEMORY		-68
@@ -496,7 +495,8 @@ void xhci_update_event_dq(xhci_t *);
 void xhci_handle_events(xhci_t *);
 int xhci_wait_for_command_aborted(xhci_t *, const trb_t *);
 int xhci_wait_for_command_done(xhci_t *, const trb_t *, int clear_event);
-int xhci_wait_for_transfer(xhci_t *, const int slot_id, const int ep_id);
+int xhci_wait_for_transfer(xhci_t *, const int slot_id, const int ep_id,
+			   unsigned long timeout_us);
 
 void xhci_clear_trb(trb_t *, int pcs);
 
diff --git a/payloads/libpayload/include/usb/usb.h b/payloads/libpayload/include/usb/usb.h
index 43c7b4279d..f36bb5c5be 100644
--- a/payloads/libpayload/include/usb/usb.h
+++ b/payloads/libpayload/include/usb/usb.h
@@ -231,6 +231,12 @@ struct usbdev {
 
 typedef enum { OHCI = 0, UHCI = 1, EHCI = 2, XHCI = 3, DWC2 = 4} hc_type;
 
+/*
+ * Use higher value so it is less likely to conflict with error codes that
+ * controller drivers may already use.
+ */
+#define USB_TIMEOUT -65
+
 struct usbdev_hc {
 	hci_t *next;
 	uintptr_t reg_base;
@@ -255,6 +261,10 @@ struct usbdev_hc {
 	void (*shutdown) (hci_t *controller);
 
 	int (*bulk) (endpoint_t *ep, int size, u8 *data, int finalize);
+	/* bulk_timeout():		Perform bulk transfer, but timeout after
+					specified time in us. Returns
+					USB_TIMEOUT in that case. */
+	int (*bulk_timeout) (endpoint_t *ep, int size, u8 *data, int timeout_us);
 	int (*control) (usbdev_t *dev, direction_t pid, int dr_length,
 			void *devreq, int data_length, u8 *data);
 	void* (*create_intr_queue) (endpoint_t *ep, int reqsize, int reqcount, int reqtiming);

From 524ad684afd0ffc9c6cdf05d0806d61e75769f40 Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Sat, 20 Dec 2025 17:21:08 -0600
Subject: [PATCH 2986/3886] mb/google/brya/var/taeko: Fix SOF speaker topology
 selection

taeko/taeko4es use max98357a-tdm, not max98357a.

TEST=build/boot Win11 on taeko, verify speaker output functional.

Change-Id: I854a9c75ded94474ad440013dad64ee03c40d6e5
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90581
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/google/brya/variants/taeko/overridetree.cb    | 2 +-
 src/mainboard/google/brya/variants/taeko4es/overridetree.cb | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/mainboard/google/brya/variants/taeko/overridetree.cb b/src/mainboard/google/brya/variants/taeko/overridetree.cb
index ff25f7b638..0e1290f873 100644
--- a/src/mainboard/google/brya/variants/taeko/overridetree.cb
+++ b/src/mainboard/google/brya/variants/taeko/overridetree.cb
@@ -530,7 +530,7 @@ chip soc/intel/alderlake
 				end
 			end
 			chip drivers/sof
-				register "spkr_tplg" = "max98357a"
+				register "spkr_tplg" = "max98357a_tdm"
 				register "jack_tplg" = "rt5682"
 				register "mic_tplg" = "_2ch_pdm0"
 				device generic 0 on end
diff --git a/src/mainboard/google/brya/variants/taeko4es/overridetree.cb b/src/mainboard/google/brya/variants/taeko4es/overridetree.cb
index 2dc3287a05..3e978f1e00 100644
--- a/src/mainboard/google/brya/variants/taeko4es/overridetree.cb
+++ b/src/mainboard/google/brya/variants/taeko4es/overridetree.cb
@@ -390,7 +390,7 @@ chip soc/intel/alderlake
 				end
 			end
 			chip drivers/sof
-				register "spkr_tplg" = "max98357a"
+				register "spkr_tplg" = "max98357a_tdm"
 				register "jack_tplg" = "rt5682"
 				register "mic_tplg" = "_2ch_pdm0"
 				device generic 0 on end

From 2aca802e85201d6da75ffa6e7a26454770154fc8 Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Sat, 20 Dec 2025 19:16:49 -0600
Subject: [PATCH 2987/3886] mb/google/brya/acpi/cnvi_bt_reset: Fix BT
 re-enumeration under Windows

The previous implementation violated ACPI spec by attempting to
implement a reset via _ON/_OFF, which are to be used exclusively for
device power management/power state transitions. As a result, under
Windows the CNVi BT device was continually re-enumerating and unable
to be used.

Fix this by moving the reset logic out of _ON/_OFF and into _RST, where
it belongs.

TEST=build/boot Win11 on google/taeko, verify BT device is functional.

Change-Id: I1627fefbf7747129344291cc8855c15dda50cf5f
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90582
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 .../google/brya/acpi/cnvi_bt_reset.asl        | 38 +++++++++----------
 1 file changed, 18 insertions(+), 20 deletions(-)

diff --git a/src/mainboard/google/brya/acpi/cnvi_bt_reset.asl b/src/mainboard/google/brya/acpi/cnvi_bt_reset.asl
index 6e84522145..4fd2ad7449 100644
--- a/src/mainboard/google/brya/acpi/cnvi_bt_reset.asl
+++ b/src/mainboard/google/brya/acpi/cnvi_bt_reset.asl
@@ -22,7 +22,7 @@ External (\_SB.PCI0.GTXS, MethodObj)
 
 Scope (\_SB.PCI0.XHCI.RHUB.HS10)
 {
-	PowerResource (CTTR, 0x00, 0x0000)
+	PowerResource (CTTR, 0x05, 0x0000)
 	{
 		Method (_STA, 0, NotSerialized)  // _STA: Status
 		{
@@ -31,32 +31,30 @@ Scope (\_SB.PCI0.XHCI.RHUB.HS10)
 
 		Method (_ON, 0, NotSerialized)  // _ON_: Power On
 		{
-			If (LEqual (\_SB.PCI0.GTXS(BT_RESET_GPIO), 0)) {
-				\_SB.PCI0.STXS(CNV_BTEN)
-				\_SB.PCI0.STXS(CNV_BT_IF_SELECT)
-				\_SB.PCI0.STXS(BT_RESET_GPIO)
-			}
 		}
 
 		Method (_OFF, 0, NotSerialized)  // _OFF: Power Off
 		{
-			If (LEqual (\_SB.PCI0.GTXS(BT_RESET_GPIO), 1)) {
-				\_SB.PCI0.CTXS(CNV_BTEN)
-				\_SB.PCI0.CTXS(CNV_BT_IF_SELECT)
-				\_SB.PCI0.CTXS(BT_RESET_GPIO)
-				Sleep (BT_RESET_DELAY_MS)
-			}
 		}
 
+		Method (_RST, 0, NotSerialized)  // _RST: Device Reset
+		{
+			\_SB.PCI0.CTXS(CNV_BTEN)
+			\_SB.PCI0.CTXS(CNV_BT_IF_SELECT)
+			\_SB.PCI0.CTXS(BT_RESET_GPIO)
+			Sleep (BT_RESET_DELAY_MS)
+			\_SB.PCI0.STXS(CNV_BTEN)
+			\_SB.PCI0.STXS(CNV_BT_IF_SELECT)
+			\_SB.PCI0.STXS(BT_RESET_GPIO)
+			Sleep (BT_RESET_DELAY_MS)
+		}
 	}
 
-	Name (_PRR, Package (0x01)  // _PRR: Power Resource for Reset
+	Method (_PRR, 0, NotSerialized)  // _PRR: Power Resource for Reset
 	{
-		CTTR
-	})
-
-	Name (_PR0, Package (0x01)  // _PR0: Power Resources for D0
-	{
-		CTTR
-	})
+		Return (Package (0x01)
+		{
+			CTTR
+		})
+	}
 }

From 65cbf312af928fde6260db0a5cc12ad6df4642fe Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Sat, 20 Dec 2025 11:18:21 -0600
Subject: [PATCH 2988/3886] mb/google/volteer: Convert MIPI camera cfg from
 static ASL to devicetree

Convert MIPI camera configurations from static ASL files to devicetree-
based runtime ACPI generation using the mipi_camera driver. This moves
the camera IPU and device definitions from static ASL includes to
devicetree overridetree files.

Changes:
- Convert baseboard, voema, volteer, and volteer2 from static
  mipi_camera.asl files to devicetree configuration
- Move IPU0 configuration with CAM0 and CAM1 to volteer/volteer2
  variant overridetree files (baseboard devicetree not used directly)
- Remove all static ASL camera definition files (mipi_camera.asl)
- Simplify voema variant to use only 1 IPU port (CAM1 only) instead
  of 2 ports, removing unused CAM0 port definition
- Add SSDB config based on sensor name/type and CIO2 config

This, along with follow-on patches, will allow volteer variants to be
properly supported under Windows/Linux as well as ChromeOS.

Change-Id: I7bd4ef2812a3d21b6541469bc3a126498d72f5ef
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90579
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
---
 src/mainboard/google/volteer/Kconfig          |  12 +-
 src/mainboard/google/volteer/dsdt.asl         |   8 -
 .../include/baseboard/acpi/mipi_camera.asl    | 650 ------------------
 .../include/variant/acpi/mipi_camera.asl      | 340 ---------
 .../volteer/variants/voema/overridetree.cb    |  74 +-
 .../include/variant/acpi/mipi_camera.asl      |   3 -
 .../volteer/variants/volteer/overridetree.cb  | 139 +++-
 .../include/variant/acpi/mipi_camera.asl      |   3 -
 .../volteer/variants/volteer2/overridetree.cb | 139 +++-
 9 files changed, 353 insertions(+), 1015 deletions(-)
 delete mode 100644 src/mainboard/google/volteer/variants/baseboard/include/baseboard/acpi/mipi_camera.asl
 delete mode 100644 src/mainboard/google/volteer/variants/voema/include/variant/acpi/mipi_camera.asl
 delete mode 100644 src/mainboard/google/volteer/variants/volteer/include/variant/acpi/mipi_camera.asl
 delete mode 100644 src/mainboard/google/volteer/variants/volteer2/include/variant/acpi/mipi_camera.asl

diff --git a/src/mainboard/google/volteer/Kconfig b/src/mainboard/google/volteer/Kconfig
index a7537c0fd2..a32681d811 100644
--- a/src/mainboard/google/volteer/Kconfig
+++ b/src/mainboard/google/volteer/Kconfig
@@ -105,8 +105,8 @@ config BOARD_GOOGLE_TRONDO
 
 config BOARD_GOOGLE_VOEMA
 	select BOARD_GOOGLE_BASEBOARD_VOLTEER
+	select DRIVERS_INTEL_MIPI_CAMERA
 	select INTEL_GMA_HAVE_VBT
-	select VARIANT_HAS_MIPI_CAMERA
 
 config BOARD_GOOGLE_VOLET
 	select BOARD_GOOGLE_BASEBOARD_VOLTEER
@@ -114,24 +114,24 @@ config BOARD_GOOGLE_VOLET
 
 config BOARD_GOOGLE_VOLTEER
 	select BOARD_GOOGLE_BASEBOARD_VOLTEER
+	select DRIVERS_INTEL_MIPI_CAMERA
 	select INTEL_CAR_NEM
 	select SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES
-	select VARIANT_HAS_MIPI_CAMERA
 
 config BOARD_GOOGLE_VOLTEER2
 	select BOARD_GOOGLE_BASEBOARD_VOLTEER
 	select DRIVER_I2C_TPM_ACPI
 	select DRIVERS_GENESYSLOGIC_GL9755
+	select DRIVERS_INTEL_MIPI_CAMERA
 	select INTEL_GMA_HAVE_VBT
 	select SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES
-	select VARIANT_HAS_MIPI_CAMERA
 
 config BOARD_GOOGLE_VOLTEER2_TI50
 	select BOARD_GOOGLE_BASEBOARD_VOLTEER
 	select DRIVER_I2C_TPM_ACPI
 	select DRIVERS_GENESYSLOGIC_GL9755
+	select DRIVERS_INTEL_MIPI_CAMERA
 	select SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES
-	select VARIANT_HAS_MIPI_CAMERA
 
 config BOARD_GOOGLE_VOXEL
 	select BOARD_GOOGLE_BASEBOARD_VOLTEER
@@ -241,10 +241,6 @@ config VARIANT_DIR
 	default "volteer2" if BOARD_GOOGLE_VOLTEER2_TI50
 	default "voxel" if BOARD_GOOGLE_VOXEL
 
-config VARIANT_HAS_MIPI_CAMERA
-	bool
-	default n
-
 config USE_PM_ACPI_TIMER
 	default n
 
diff --git a/src/mainboard/google/volteer/dsdt.asl b/src/mainboard/google/volteer/dsdt.asl
index c200294e74..dbd36043aa 100644
--- a/src/mainboard/google/volteer/dsdt.asl
+++ b/src/mainboard/google/volteer/dsdt.asl
@@ -30,9 +30,6 @@ DefinitionBlock(
 			#include <soc/intel/tigerlake/acpi/tcss.asl>
 			#include <soc/intel/common/block/acpi/acpi/gna.asl>
 			#include <drivers/intel/gma/acpi/default_brightness_levels.asl>
-#if CONFIG(VARIANT_HAS_MIPI_CAMERA)
-			#include <soc/intel/common/block/acpi/acpi/ipu.asl>
-#endif
 		}
 		/* Mainboard hooks */
 		#include "mainboard.asl"
@@ -48,9 +45,4 @@ DefinitionBlock(
 	}
 
 	#include <southbridge/intel/common/acpi/sleepstates.asl>
-
-#if CONFIG(VARIANT_HAS_MIPI_CAMERA)
-	/* Camera */
-	#include <variant/acpi/mipi_camera.asl>
-#endif /* VARIANT_HAS_MIPI_CAMERA */
 }
diff --git a/src/mainboard/google/volteer/variants/baseboard/include/baseboard/acpi/mipi_camera.asl b/src/mainboard/google/volteer/variants/baseboard/include/baseboard/acpi/mipi_camera.asl
deleted file mode 100644
index f22b402865..0000000000
--- a/src/mainboard/google/volteer/variants/baseboard/include/baseboard/acpi/mipi_camera.asl
+++ /dev/null
@@ -1,650 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-Scope (\_SB.PCI0.IPU0)
-{
-	Name (_DSD, Package (0x02)  /* _DSD: Device-Specific Data */
-	{
-		ToUUID ("dbb8e3e6-5886-4ba6-8795-1319f52a966b"),
-		Package (0x02)
-		{
-			Package (0x02)
-			{
-				"port0",
-				"PRT0"
-			},
-			Package (0x02)
-			{
-				"port1",
-				"PRT1"
-			}
-		}
-	})
-
-	Name (PRT0, Package (0x04)
-	{
-		ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
-		Package (0x01)
-		{
-			Package (0x02)
-			{
-				"port",
-				5
-			}
-		},
-		ToUUID ("dbb8e3e6-5886-4ba6-8795-1319f52a966b"),
-		Package (0x01)
-		{
-			Package (0x02)
-			{
-				"endpoint0",
-				"EP00"
-			}
-		}
-	})
-
-	Name (PRT1, Package (0x04)
-	{
-		ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
-		Package (0x01)
-		{
-			Package (0x02)
-			{
-				"port",
-				1
-			}
-		},
-
-		ToUUID ("dbb8e3e6-5886-4ba6-8795-1319f52a966b"),
-		Package (0x01)
-		{
-			Package (0x02)
-			{
-				"endpoint0",
-				"EP10"
-			}
-		}
-	})
-}
-
-Scope (\_SB.PCI0.IPU0)
-{
-	Name (EP00, Package (0x02)
-	{
-		ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
-		Package (0x04)
-		{
-			Package (0x02)
-			{
-				"endpoint",
-				0
-			},
-			Package (0x02)
-			{
-				"clock-lanes",
-				0
-			},
-			Package (0x02)
-			{
-				"data-lanes",
-				Package (0x04)
-				{
-					1,
-					0x02,
-					0x03,
-					0x04
-				}
-			},
-			Package (0x02)
-			{
-				"remote-endpoint",
-				Package (0x03)
-				{
-					^I2C3.CAM0,
-					0,
-					0
-				}
-			}
-		}
-	})
-	Name (EP10, Package (0x02)
-	{
-		ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
-		Package (0x04)
-		{
-			Package (0x02)
-			{
-				"endpoint",
-				0
-			},
-			Package (0x02)
-			{
-				"clock-lanes",
-				0
-			},
-			Package (0x02)
-			{
-				"data-lanes",
-				Package (0x02)
-				{
-					1,
-					0x02
-				}
-			},
-			Package (0x02)
-			{
-				"remote-endpoint",
-				Package (0x03)
-				{
-					^I2C2.CAM1,
-					0,
-					0
-				}
-			}
-		}
-	})
-}
-
-Scope (\_SB.PCI0.I2C3)
-{
-	/* Reference counter to track power control by RCAM and VCM */
-	Name (REFC, 0)
-	PowerResource (RCPR, 0x00, 0x0000)
-	{
-		Name (STA, 0)
-		Method (_ON, 0, Serialized)  /* Rear camera_ON_: Power On */
-		{
-			/* Enable IMG_CLK */
-			MCON(3,1) /* Clock 3, 19.2MHz */
-
-			/* Pull RST low */
-			CTXS(GPP_F15)
-
-			/* Pull SNRPWR_EN high */
-			STXS(GPP_H14)
-
-			If (REFC == 0)
-			{
-				/* Pull PWREN high */
-				STXS(GPP_H20)
-			}
-			Sleep(2) /* reset pulse width */
-
-			REFC++
-
-			/* Pull RST high */
-			STXS(GPP_F15)
-
-			Sleep(1) /* t2 */
-
-			STA = 1
-		}
-		Method (_OFF, 0, Serialized)  /* Rear camera _OFF: Power Off */
-		{
-			/* Disable IMG_CLK */
-			Sleep(1) /* t0+t1 */
-			MCOF(3) /* Clock 3 */
-
-			/* Pull RST low */
-			CTXS(GPP_F15)
-
-			If (REFC == 1)
-			{
-				/* Pull PWREN low */
-				CTXS(GPP_H20)
-			}
-			REFC--
-
-			/* Pull SNRPWR_EN low */
-			CTXS(GPP_H14)
-
-			STA = 0
-		}
-		Method (_STA, 0, NotSerialized)
-		{
-			Return (STA)
-		}
-	}
-
-	Device (CAM0)
-	{
-		Name (_HID, "OVTI8856")
-		Name (_UID, 0)
-		Name (_DDN, "Ov 8856 Camera")  /* _DDN: DOS Device Name */
-		Method (_STA, 0, NotSerialized)
-		{
-			Return (0x0F)
-		}
-		Name (_CRS, ResourceTemplate ()  /* _CRS: Current Resource Settings */
-		{
-			I2cSerialBus (0x0010, ControllerInitiated, 0x00061A80,
-				AddressingMode7Bit, "\\_SB.PCI0.I2C3",
-				0x00, ResourceConsumer, ,
-			)
-		})
-		Name (_PR0, Package (0x01)  /* _PR0: Power Resources for D0 */
-		{
-			RCPR
-		})
-		Name (_PR3, Package (0x01)  /* _PR3: Power Resources for D3hot */
-		{
-			RCPR
-		})
-		Name (_DSD, Package (0x04)  /* _DSD: Device-Specific Data */
-		{
-			ToUUID ("dbb8e3e6-5886-4ba6-8795-1319f52a966b"),
-			Package (0x01)
-			{
-				Package (0x02)
-				{
-					"port0",
-					"PRT0"
-				}
-			},
-			ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
-			Package (0x03)
-			{
-				Package (0x02)
-				{
-					"clock-frequency",
-					0x0124F800
-				},
-				Package (0x02)
-				{
-					"lens-focus",
-					Package (0x01)
-					{
-						VCM0
-					}
-				},
-				Package (0x02)
-				{
-					"i2c-allow-low-power-probe",
-					0x01
-				}
-			}
-		})
-		Name (PRT0, Package (0x04)
-		{
-			ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
-			Package (0x01)
-			{
-				Package (0x02)
-				{
-					"port",
-					0
-				}
-			},
-			ToUUID ("dbb8e3e6-5886-4ba6-8795-1319f52a966b"),
-			Package (0x01)
-			{
-				Package (0x02)
-				{
-					"endpoint0",
-					"EP00"
-				}
-			}
-		})
-		Name (EP00, Package (0x02)
-		{
-			ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
-			Package (0x05)
-			{
-				Package (0x02)
-				{
-					"endpoint",
-					0
-				},
-				Package (0x02)
-				{
-					"clock-lanes",
-					0
-				},
-				Package (0x02)
-				{
-					"data-lanes",
-					Package (0x04)
-					{
-						1,
-						0x02,
-						0x03,
-						0x04
-					}
-				},
-				Package (0x02)
-				{
-					"link-frequencies",
-					Package (0x02)
-					{
-						0x15752A00,
-						0xABA9500
-					}
-				},
-				Package (0x02)
-				{
-					"remote-endpoint",
-					Package (0x03)
-					{
-						IPU0,
-						0,
-						0
-					}
-				}
-			}
-		})
-	}
-
-	PowerResource (VCPR, 0x00, 0x0000)
-	{
-		Name (STA, 0)
-		Method (_ON, 0, Serialized)  /* VCPR_ON_: VCM Power On */
-		{
-			If (REFC == 0)
-			{
-				/* Pull PWREN high */
-				STXS(GPP_H20)
-			}
-			REFC++
-			STA = 1
-		}
-		Method (_OFF, 0, Serialized)  /* VCPR_OFF: VCM Power Off */
-		{
-			If (REFC == 1)
-			{
-				/* Pull PWREN low */
-				CTXS(GPP_H20)
-			}
-			REFC--
-			STA = 0
-		}
-		Method (_STA, 0, NotSerialized)
-		{
-			Return (STA)
-		}
-	}
-
-	Device (VCM0)
-	{
-		Name (_HID, "PRP0001")
-		Name (_UID, 0x00)
-		Name (_DDN, "DW9768 VCM")  /* _DDN: DOS Device Name */
-		Method (_STA, 0, NotSerialized)
-		{
-			Return (0x0F)
-		}
-		Name (_CRS, ResourceTemplate ()  /* _CRS: Current Resource Settings */
-		{
-			I2cSerialBus (0x000C, ControllerInitiated, 0x00061A80,
-				AddressingMode7Bit, "\\_SB.PCI0.I2C3",
-				0x00, ResourceConsumer, ,
-			)
-		})
-		Name (_DEP, Package (0x01)  /* _DEP: Dependencies */
-		{
-			CAM0
-		})
-		Name (_PR0, Package (0x01)  /* _PR0: Power Resources for D0 */
-		{
-			VCPR
-		})
-		Name (_PR3, Package (0x01)  /* _PR3: Power Resources for D3hot */
-		{
-			VCPR
-		})
-		Name (_DSD, Package (0x02)  /* _DSD: Device-Specific Data */
-		{
-			ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
-			Package (0x02)
-			{
-				Package (0x02)
-				{
-					"compatible",
-					"dongwoon,dw9768"
-				},
-				Package (0x02)
-				{
-					"i2c-allow-low-power-probe",
-					0x01
-				}
-			}
-		})
-	}
-	Device (NVM0)
-	{
-		Name (_HID, "PRP0001")
-		Name (_UID, 0x01)
-		Name (_DDN, "AT24 EEPROM")  // _DDN: DOS Device Name
-		Method (_STA, 0, NotSerialized)
-		{
-			Return (0x0F)
-		}
-		Name (_CRS, ResourceTemplate ()  // _CRS: Current Resource Settings
-		{
-			I2cSerialBusV2 (0x0058, ControllerInitiated, 0x00061A80,
-				AddressingMode7Bit, "\\_SB.PCI0.I2C3",
-				0x00, ResourceConsumer, , Exclusive,
-				)
-		})
-		Name (_DEP, Package (0x01)  // _DEP: Dependencies
-		{
-			CAM0
-		})
-		Name (_PR0, Package (0x01)  // _PR0: Power Resources for D0
-		{
-			RCPR
-		})
-		Name (_PR3, Package (0x01)  // _PR3: Power Resources for D3hot
-		{
-			RCPR
-		})
-		Name (_DSD, Package (0x02)  // _DSD: Device-Specific Data
-		{
-			ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301") /* Device Properties for _DSD */,
-			Package (0x06)
-			{
-				Package (0x02)
-				{
-					"size",
-					0x2800
-				},
-				Package (0x02)
-				{
-					"pagesize",
-					1
-				},
-				Package (0x02)
-				{
-					"read-only",
-					1
-				},
-				Package (0x02)
-				{
-					"address-width",
-					0x10
-				},
-				Package (0x02)
-				{
-					"compatible",
-					"atmel,24c1024"
-				},
-				Package (0x02)
-				{
-					"i2c-allow-low-power-probe",
-					0x01
-				}
-			}
-		})
-	}
-}
-
-Scope (\_SB.PCI0.I2C2)
-{
-	Name (STA, 0)
-	PowerResource (FCPR, 0x00, 0x0000)
-	{
-		Method (_ON, 0, Serialized)  /* Front camera_ON_: Power On */
-		{
-			If (STA == 0)
-			{
-				/* Enable IMG_CLK */
-				MCON(2,1) /* Clock 2, 19.2MHz */
-
-				/* Pull RST low */
-				CTXS(GPP_D4)
-
-				/* Pull SNRPWR_EN high */
-				STXS(GPP_D18)
-
-				/* Pull PWREN high */
-				STXS(GPP_D17)
-				Sleep(10) /* t9 */
-
-				/* Pull RST high */
-				STXS(GPP_D4)
-				Sleep(1) /* t2 */
-
-				STA = 1
-			}
-		}
-		Method (_OFF, 0, Serialized)  /* Front camera_OFF_: Power Off */
-		{
-			If (STA == 1)
-			{
-				/* Disable IMG_CLK */
-				Sleep(1) /* t0+t1 */
-				MCOF(2) /* Clock 2 */
-
-				/* Pull RST low */
-				CTXS(GPP_D4)
-
-				/* Pull PWREN low */
-				CTXS(GPP_D17)
-
-				/* Pull SNRPWR_EN low */
-				CTXS(GPP_D18)
-
-				STA = 0
-			}
-		}
-		Method (_STA, 0, NotSerialized)
-		{
-			Return (STA)
-		}
-	}
-
-	Device (CAM1)
-	{
-		Name (_HID, "INT3474")
-		Name (_UID, 0)
-		Name (_DDN, "Ov 2740 Camera")  /* _DDN: DOS Device Name */
-		Method (_STA, 0, NotSerialized)
-		{
-			Return (0x0F)
-		}
-		Name (_CRS, ResourceTemplate ()  /* _CRS: Current Resource Settings */
-		{
-			I2cSerialBus (0x0010, ControllerInitiated, 0x00061A80,
-				AddressingMode7Bit, "\\_SB.PCI0.I2C2",
-				0x00, ResourceConsumer, ,
-			)
-		})
-		Name (_PR0, Package (0x01)  /* _PR0: Power Resources for D0 */
-		{
-			FCPR
-		})
-		Name (_PR3, Package (0x01)  /* _PR3: Power Resources for D3hot */
-		{
-			FCPR
-		})
-		Name (_DSD, Package (0x04)  /* _DSD: Device-Specific Data */
-		{
-			ToUUID ("dbb8e3e6-5886-4ba6-8795-1319f52a966b"),
-			Package (0x01)
-			{
-				Package (0x02)
-				{
-					"port0",
-					"PRT0"
-				}
-			},
-			ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
-			Package (0x02)
-			{
-				Package (0x02)
-				{
-					"clock-frequency",
-					0x0124F800
-				},
-				Package (0x02)
-				{
-					"i2c-allow-low-power-probe",
-					0x01
-				}
-			}
-		})
-		Name (PRT0, Package (0x04)
-		{
-			ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
-			Package (0x01)
-			{
-				Package (0x02)
-				{
-					"port",
-					0
-				}
-			},
-			ToUUID ("dbb8e3e6-5886-4ba6-8795-1319f52a966b"),
-			Package (0x01)
-			{
-				Package (0x02)
-				{
-					"endpoint0",
-					"EP00"
-				}
-			}
-		})
-		Name (EP00, Package (0x02)
-		{
-			ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
-			Package (0x05)
-			{
-				Package (0x02)
-				{
-					"endpoint",
-					0
-				},
-				Package (0x02)
-				{
-					"clock-lanes",
-					0
-				},
-				Package (0x02)
-				{
-					"data-lanes",
-					Package (0x02)
-					{
-						1,
-						0x02
-					}
-				},
-				Package (0x02)
-				{
-					"link-frequencies",
-					Package (0x01)
-					{
-						0x15752A00
-					}
-				},
-				Package (0x02)
-				{
-					"remote-endpoint",
-					Package (0x03)
-					{
-						IPU0,
-						1,
-						0
-					}
-				}
-			}
-		})
-	}
-}
diff --git a/src/mainboard/google/volteer/variants/voema/include/variant/acpi/mipi_camera.asl b/src/mainboard/google/volteer/variants/voema/include/variant/acpi/mipi_camera.asl
deleted file mode 100644
index e35c3bba8a..0000000000
--- a/src/mainboard/google/volteer/variants/voema/include/variant/acpi/mipi_camera.asl
+++ /dev/null
@@ -1,340 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-Scope (\_SB.PCI0.IPU0)
-{
-	Name (_DSD, Package (0x02)  /* _DSD: Device-Specific Data */
-	{
-		ToUUID ("dbb8e3e6-5886-4ba6-8795-1319f52a966b"),
-		Package (0x02)
-		{
-			Package (0x02)
-			{
-				"port0",
-				"PRT0"
-			},
-			Package (0x02)
-			{
-				"port1",
-				"PRT1"
-			}
-		}
-	})
-
-	Name (PRT0, Package (0x04)
-	{
-		ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
-		Package (0x01)
-		{
-			Package (0x02)
-			{
-				"port",
-				5
-			}
-		},
-		ToUUID ("dbb8e3e6-5886-4ba6-8795-1319f52a966b"),
-		Package (0x01)
-		{
-			Package (0x02)
-			{
-				"endpoint0",
-				"EP00"
-			}
-		}
-	})
-
-	Name (PRT1, Package (0x04)
-	{
-		ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
-		Package (0x01)
-		{
-			Package (0x02)
-			{
-				"port",
-				1
-			}
-		},
-
-		ToUUID ("dbb8e3e6-5886-4ba6-8795-1319f52a966b"),
-		Package (0x01)
-		{
-			Package (0x02)
-			{
-				"endpoint0",
-				"EP10"
-			}
-		}
-	})
-}
-
-Scope (\_SB.PCI0.IPU0)
-{
-	Name (EP10, Package (0x02)
-	{
-		ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
-		Package (0x04)
-		{
-			Package (0x02)
-			{
-				"endpoint",
-				0
-			},
-			Package (0x02)
-			{
-				"clock-lanes",
-				0
-			},
-			Package (0x02)
-			{
-				"data-lanes",
-				Package (0x02)
-				{
-					1,
-					0x02
-				}
-			},
-			Package (0x02)
-			{
-				"remote-endpoint",
-				Package (0x03)
-				{
-					^I2C2.CAM1,
-					0,
-					0
-				}
-			}
-		}
-	})
-}
-
-Scope (\_SB.PCI0.I2C2)
-{
-	Name (STA, 0)
-	PowerResource (FCPR, 0x00, 0x0000)
-	{
-		Method (_ON, 0, Serialized)  /* Front camera_ON_: Power On */
-		{
-			If (STA == 0)
-			{
-				/* Enable IMG_CLK */
-				MCON(2,1) /* Clock 2, 19.2MHz */
-
-				/* Pull RST low */
-				CTXS(GPP_D4)
-
-				/* Pull PWREN high */
-				STXS(GPP_D17)
-				Sleep(10) /* t9 */
-
-				/* Pull RST high */
-				STXS(GPP_D4)
-				Sleep(1) /* t2 */
-
-				STA = 1
-			}
-		}
-		Method (_OFF, 0, Serialized)  /* Front camera_OFF_: Power Off */
-		{
-			If (STA == 1)
-			{
-				/* Disable IMG_CLK */
-				Sleep(1) /* t0+t1 */
-				MCOF(2) /* Clock 2 */
-
-				/* Pull RST low */
-				CTXS(GPP_D4)
-
-				/* Pull PWREN low */
-				CTXS(GPP_D17)
-
-				STA = 0
-			}
-		}
-		Method (_STA, 0, NotSerialized)
-		{
-			Return (STA)
-		}
-	}
-
-	Device (CAM1)
-	{
-		Name (_HID, "INT3474")
-		Name (_UID, 0)
-		Name (_DDN, "Ov 2740 Camera")  /* _DDN: DOS Device Name */
-		Method (_STA, 0, NotSerialized)
-		{
-			Return (0x0F)
-		}
-		Name (_CRS, ResourceTemplate ()  /* _CRS: Current Resource Settings */
-		{
-			I2cSerialBus (0x0036, ControllerInitiated, 0x00061A80,
-				AddressingMode7Bit, "\\_SB.PCI0.I2C2",
-				0x00, ResourceConsumer, ,
-			)
-		})
-		Name (_PR0, Package (0x01)  /* _PR0: Power Resources for D0 */
-		{
-			FCPR
-		})
-		Name (_PR3, Package (0x01)  /* _PR3: Power Resources for D3hot */
-		{
-			FCPR
-		})
-		Name (_DSD, Package (0x04)  /* _DSD: Device-Specific Data */
-		{
-			ToUUID ("dbb8e3e6-5886-4ba6-8795-1319f52a966b"),
-			Package (0x01)
-			{
-				Package (0x02)
-				{
-					"port0",
-					"PRT0"
-				}
-			},
-			ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
-			Package (0x02)
-			{
-				Package (0x02)
-				{
-					"clock-frequency",
-					0x0124F800
-				},
-				Package (0x02)
-				{
-					"i2c-allow-low-power-probe",
-					0x01
-				}
-			}
-		})
-		Name (PRT0, Package (0x04)
-		{
-			ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
-			Package (0x01)
-			{
-				Package (0x02)
-				{
-					"port",
-					0
-				}
-			},
-			ToUUID ("dbb8e3e6-5886-4ba6-8795-1319f52a966b"),
-			Package (0x01)
-			{
-				Package (0x02)
-				{
-					"endpoint0",
-					"EP00"
-				}
-			}
-		})
-		Name (EP00, Package (0x02)
-		{
-			ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
-			Package (0x05)
-			{
-				Package (0x02)
-				{
-					"endpoint",
-					0
-				},
-				Package (0x02)
-				{
-					"clock-lanes",
-					0
-				},
-				Package (0x02)
-				{
-					"data-lanes",
-					Package (0x02)
-					{
-						1,
-						0x02
-					}
-				},
-				Package (0x02)
-				{
-					"link-frequencies",
-					Package (0x01)
-					{
-						0x15752A00
-					}
-				},
-				Package (0x02)
-				{
-					"remote-endpoint",
-					Package (0x03)
-					{
-						IPU0,
-						1,
-						0
-					}
-				}
-			}
-		})
-	}
-	Device (NVM0)
-	{
-		Name (_HID, "PRP0001")
-		Name (_UID, 0x01)
-		Name (_DDN, "AT24 EEPROM")  // _DDN: DOS Device Name
-		Method (_STA, 0, NotSerialized)
-		{
-			Return (0x0F)
-		}
-		Name (_CRS, ResourceTemplate ()  // _CRS: Current Resource Settings
-		{
-			I2cSerialBusV2 (0x0050, ControllerInitiated, 0x00061A80,
-				AddressingMode7Bit, "\\_SB.PCI0.I2C2",
-				0x00, ResourceConsumer, , Exclusive,
-				)
-		})
-		Name (_DEP, Package (0x01)  // _DEP: Dependencies
-		{
-			CAM1
-		})
-		Name (_PR0, Package (0x01)  // _PR0: Power Resources for D0
-		{
-			FCPR
-		})
-		Name (_PR3, Package (0x01)  // _PR3: Power Resources for D3hot
-		{
-			FCPR
-		})
-		Name (_DSD, Package (0x02)  // _DSD: Device-Specific Data
-		{
-			ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301") /* Device Properties for _DSD */,
-			Package (0x06)
-			{
-				Package (0x02)
-				{
-					"size",
-					0x2000
-				},
-				Package (0x02)
-				{
-					"pagesize",
-					1
-				},
-				Package (0x02)
-				{
-					"read-only",
-					1
-				},
-				Package (0x02)
-				{
-					"address-width",
-					0x10
-				},
-				Package (0x02)
-				{
-					"compatible",
-					"atmel,24c64"
-				},
-				Package (0x02)
-				{
-					"i2c-allow-low-power-probe",
-					0x01
-				}
-			}
-		})
-	}
-}
diff --git a/src/mainboard/google/volteer/variants/voema/overridetree.cb b/src/mainboard/google/volteer/variants/voema/overridetree.cb
index e4b2616807..ecb37987c7 100644
--- a/src/mainboard/google/volteer/variants/voema/overridetree.cb
+++ b/src/mainboard/google/volteer/variants/voema/overridetree.cb
@@ -9,7 +9,19 @@ chip soc/intel/tigerlake
 	register "typec_aux_bias_pads[0]" = "{.pad_auxp_dc = GPP_E10, .pad_auxn_dc = GPP_E13}"
 
 	device domain 0 on
-		device ref ipu on end # IPU
+		device ref ipu on
+			chip drivers/intel/mipi_camera
+				register "acpi_uid" = "0x50000"
+				register "acpi_name" = ""IPU0""
+				register "device_type" = "INTEL_ACPI_CAMERA_CIO2"
+
+				register "cio2_num_ports" = "1"
+				register "cio2_lanes_used" = "{2}" # 2 CSI Camera lanes are used
+				register "cio2_lane_endpoint[0]" = ""^I2C2.CAM1""
+				register "cio2_prt[0]" = "1"
+				device generic 0 on end
+			end
+		end
 		device ref i2c0 on
 			chip drivers/i2c/generic
 				register "hid" = ""10EC5682""
@@ -62,6 +74,66 @@ chip soc/intel/tigerlake
 				device i2c 10 on end
 			end
 		end
+		device ref i2c2 on
+			chip drivers/intel/mipi_camera
+				register "acpi_hid" = ""INT3474""
+				register "acpi_uid" = "0"
+				register "acpi_name" = ""CAM1""
+				register "chip_name" = ""Ov 2740 Camera""
+				register "device_type" = "INTEL_ACPI_CAMERA_SENSOR"
+				register "has_power_resource" = "true"
+
+				register "ssdb.lanes_used" = "2"
+				register "ssdb.link_used" = "1"
+				register "ssdb.platform" = "PLAT_TGL"
+				register "ssdb.rom_type" = "ROM_EEPROM_CAT24C64"
+				register "rom_address" = "0x50"
+				register "num_freq_entries" = "1"
+				register "link_freq[0]" = "360 * MHz"
+				register "remote_name" = ""IPU0""
+				register "max_dstate_for_probe" = "ACPI_DEVICE_SLEEP_D3_COLD"
+
+				#Controls
+				register "clk_panel.clks[0].clknum" = "2"
+				register "clk_panel.clks[0].freq" = "FREQ_19_2_MHZ"
+
+				register "gpio_panel.gpio[0].gpio_num" = "GPP_D4" #reset
+				register "gpio_panel.gpio[1].gpio_num" = "GPP_D17" #power enable
+
+				#_ON
+				register "on_seq.ops_cnt" = "4"
+				register "on_seq.ops[0]" = "SEQ_OPS_CLK_ENABLE(0, 0)"
+				register "on_seq.ops[1]" = "SEQ_OPS_GPIO_DISABLE(0, 0)" # RST low
+				register "on_seq.ops[2]" = "SEQ_OPS_GPIO_ENABLE(1, 10)" # PWREN high, sleep 10ms
+				register "on_seq.ops[3]" = "SEQ_OPS_GPIO_ENABLE(0, 1)" # RST high, sleep 1ms
+
+				#_OFF
+				register "off_seq.ops_cnt" = "3"
+				register "off_seq.ops[0]" = "SEQ_OPS_CLK_DISABLE(0, 1)" # Disable clock, delay 1ms
+				register "off_seq.ops[1]" = "SEQ_OPS_GPIO_DISABLE(0, 0)" # RST low
+				register "off_seq.ops[2]" = "SEQ_OPS_GPIO_DISABLE(1, 0)" # PWREN low
+
+				device i2c 36 on end
+			end
+			chip drivers/intel/mipi_camera
+				register "acpi_hid" = "ACPI_DT_NAMESPACE_HID"
+				register "acpi_uid" = "1"
+				register "acpi_name" = ""NVM0""
+				register "chip_name" = ""AT24 EEPROM""
+				register "device_type" = "INTEL_ACPI_CAMERA_NVM"
+				register "pr0" = ""\\_SB.PCI0.I2C2.CAM1.PRIC""
+
+				register "nvm_size" = "0x2000"
+				register "nvm_pagesize" = "1"
+				register "nvm_readonly" = "1"
+				register "nvm_width" = "0x10"
+				register "nvm_compat" = ""atmel,24c64""
+
+				register "max_dstate_for_probe" = "ACPI_DEVICE_SLEEP_D0"
+
+				device i2c 50 on end
+			end
+		end
 		device ref i2c5 on
 			chip drivers/i2c/generic
 				register "hid" = ""ELAN0000""
diff --git a/src/mainboard/google/volteer/variants/volteer/include/variant/acpi/mipi_camera.asl b/src/mainboard/google/volteer/variants/volteer/include/variant/acpi/mipi_camera.asl
deleted file mode 100644
index 418f2e04ba..0000000000
--- a/src/mainboard/google/volteer/variants/volteer/include/variant/acpi/mipi_camera.asl
+++ /dev/null
@@ -1,3 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <baseboard/acpi/mipi_camera.asl>
diff --git a/src/mainboard/google/volteer/variants/volteer/overridetree.cb b/src/mainboard/google/volteer/variants/volteer/overridetree.cb
index c489c2dc91..21e6c63e55 100644
--- a/src/mainboard/google/volteer/variants/volteer/overridetree.cb
+++ b/src/mainboard/google/volteer/variants/volteer/overridetree.cb
@@ -63,7 +63,21 @@ chip soc/intel/tigerlake
 			probe DB_USB USB4_GEN3
 		end
 
-		device ref ipu on end
+		device ref ipu on
+			chip drivers/intel/mipi_camera
+				register "acpi_uid" = "0x50000"
+				register "acpi_name" = ""IPU0""
+				register "device_type" = "INTEL_ACPI_CAMERA_CIO2"
+
+				register "cio2_num_ports" = "2"
+				register "cio2_lanes_used" = "{4,2}" # 4 and 2 CSI Camera lanes are used
+				register "cio2_lane_endpoint[0]" = ""^I2C3.CAM0""
+				register "cio2_lane_endpoint[1]" = ""^I2C2.CAM1""
+				register "cio2_prt[0]" = "5"
+				register "cio2_prt[1]" = "1"
+				device generic 0 on end
+			end
+		end
 		device ref i2c0 on
 			chip drivers/i2c/generic
 				register "hid" = ""10EC5682""
@@ -166,6 +180,129 @@ chip soc/intel/tigerlake
 				register "proxraw_strength" = "0"
 				device i2c 28 on end
 			end
+			chip drivers/intel/mipi_camera
+				register "acpi_hid" = ""INT3474""
+				register "acpi_uid" = "0"
+				register "acpi_name" = ""CAM1""
+				register "chip_name" = ""Ov 2740 Camera""
+				register "device_type" = "INTEL_ACPI_CAMERA_SENSOR"
+				register "has_power_resource" = "true"
+				register "low_power_probe" = "1"
+
+				register "ssdb.lanes_used" = "2"
+				register "ssdb.link_used" = "1"
+				register "ssdb.platform" = "PLAT_TGL"
+				register "num_freq_entries" = "1"
+				register "link_freq[0]" = "360 * MHz"
+				register "remote_name" = ""IPU0""
+				register "max_dstate_for_probe" = "ACPI_DEVICE_SLEEP_D3_COLD"
+
+				#Controls
+				register "clk_panel.clks[0].clknum" = "2"
+				register "clk_panel.clks[0].freq" = "FREQ_19_2_MHZ"
+
+				register "gpio_panel.gpio[0].gpio_num" = "GPP_D4" #reset
+				register "gpio_panel.gpio[1].gpio_num" = "GPP_D17" #power enable
+				register "gpio_panel.gpio[2].gpio_num" = "GPP_D18" #SNRPWR_EN
+
+				#_ON
+				register "on_seq.ops_cnt" = "5"
+				register "on_seq.ops[0]" = "SEQ_OPS_CLK_ENABLE(0, 0)"
+				register "on_seq.ops[1]" = "SEQ_OPS_GPIO_DISABLE(0, 0)" # RST low
+				register "on_seq.ops[2]" = "SEQ_OPS_GPIO_ENABLE(2, 0)" # SNRPWR_EN high
+				register "on_seq.ops[3]" = "SEQ_OPS_GPIO_ENABLE(1, 10)" # PWREN high, sleep 10ms
+				register "on_seq.ops[4]" = "SEQ_OPS_GPIO_ENABLE(0, 1)" # RST high, sleep 1ms
+
+				#_OFF
+				register "off_seq.ops_cnt" = "4"
+				register "off_seq.ops[0]" = "SEQ_OPS_CLK_DISABLE(0, 1)" # Disable clock, delay 1ms
+				register "off_seq.ops[1]" = "SEQ_OPS_GPIO_DISABLE(0, 0)" # RST low
+				register "off_seq.ops[2]" = "SEQ_OPS_GPIO_DISABLE(1, 0)" # PWREN low
+				register "off_seq.ops[3]" = "SEQ_OPS_GPIO_DISABLE(2, 0)" # SNRPWR_EN low
+
+				device i2c 10 on end
+			end
+		end
+		device ref i2c3 on
+			chip drivers/intel/mipi_camera
+				register "acpi_hid" = ""OVTI8856""
+				register "acpi_uid" = "0"
+				register "acpi_name" = ""CAM0""
+				register "chip_name" = ""Ov 8856 Camera""
+				register "device_type" = "INTEL_ACPI_CAMERA_SENSOR"
+				register "has_power_resource" = "true"
+				register "low_power_probe" = "1"
+
+				register "ssdb.lanes_used" = "4"
+				register "ssdb.link_used" = "0"
+				register "ssdb.platform" = "PLAT_TGL"
+				register "ssdb.vcm_type" = "VCM_DW9808"
+				register "vcm_address" = "0x0C"
+				register "vcm_name" = ""VCM0""
+				# placeholder; ROM type 24C1024 currently unsupported
+				# register "ssdb.rom_type" = "ROM_EEPROM_24C1024"
+				# register "rom_address" = "0x50"
+				register "num_freq_entries" = "2"
+				register "link_freq[0]" = "360 * MHz" # 360 MHz
+				register "link_freq[1]" = "180 * MHz" # 180 MHz
+				register "remote_name" = ""IPU0""
+				register "max_dstate_for_probe" = "ACPI_DEVICE_SLEEP_D3_COLD"
+
+				#Controls
+				register "clk_panel.clks[0].clknum" = "3"
+				register "clk_panel.clks[0].freq" = "FREQ_19_2_MHZ"
+
+				register "gpio_panel.gpio[0].gpio_num" = "GPP_F15" #reset
+				register "gpio_panel.gpio[1].gpio_num" = "GPP_H20" #power enable
+				register "gpio_panel.gpio[2].gpio_num" = "GPP_H14" #SNRPWR_EN
+
+				#_ON
+				register "on_seq.ops_cnt" = "5"
+				register "on_seq.ops[0]" = "SEQ_OPS_CLK_ENABLE(0, 0)"
+				register "on_seq.ops[1]" = "SEQ_OPS_GPIO_DISABLE(0, 0)" # RST low
+				register "on_seq.ops[2]" = "SEQ_OPS_GPIO_ENABLE(2, 0)" # SNRPWR_EN high
+				register "on_seq.ops[3]" = "SEQ_OPS_GPIO_ENABLE(1, 2)" # PWREN high, sleep 2ms
+				register "on_seq.ops[4]" = "SEQ_OPS_GPIO_ENABLE(0, 1)" # RST high, sleep 1ms
+
+				#_OFF
+				register "off_seq.ops_cnt" = "4"
+				register "off_seq.ops[0]" = "SEQ_OPS_CLK_DISABLE(0, 1)" # Disable clock, delay 1ms
+				register "off_seq.ops[1]" = "SEQ_OPS_GPIO_DISABLE(0, 0)" # RST low
+				register "off_seq.ops[2]" = "SEQ_OPS_GPIO_DISABLE(1, 0)" # PWREN low
+				register "off_seq.ops[3]" = "SEQ_OPS_GPIO_DISABLE(2, 0)" # SNRPWR_EN low
+
+				device i2c 10 on end
+			end
+			chip drivers/intel/mipi_camera
+				register "acpi_uid" = "2"
+				register "acpi_name" = ""VCM0""
+				register "chip_name" = ""DW9768 VCM""
+				register "device_type" = "INTEL_ACPI_CAMERA_VCM"
+
+				register "pr0" = ""\\_SB.PCI0.I2C3.CAM0.PRIC""
+				register "vcm_compat" = ""dongwoon,dw9768""
+				register "max_dstate_for_probe" = "ACPI_DEVICE_SLEEP_D0"
+
+				device i2c 0C on end
+			end
+			chip drivers/intel/mipi_camera
+				register "acpi_hid" = "ACPI_DT_NAMESPACE_HID"
+				register "acpi_uid" = "1"
+				register "acpi_name" = ""NVM0""
+				register "chip_name" = ""AT24 EEPROM""
+				register "device_type" = "INTEL_ACPI_CAMERA_NVM"
+				register "pr0" = ""\\_SB.PCI0.I2C3.CAM0.PRIC""
+
+				register "nvm_size" = "0x2800"
+				register "nvm_pagesize" = "1"
+				register "nvm_readonly" = "1"
+				register "nvm_width" = "0x10"
+				register "nvm_compat" = ""atmel,24c1024""
+
+				register "max_dstate_for_probe" = "ACPI_DEVICE_SLEEP_D0"
+
+				device i2c 58 on end
+			end
 		end
 		device ref i2c5 on
 			chip drivers/i2c/generic
diff --git a/src/mainboard/google/volteer/variants/volteer2/include/variant/acpi/mipi_camera.asl b/src/mainboard/google/volteer/variants/volteer2/include/variant/acpi/mipi_camera.asl
deleted file mode 100644
index 418f2e04ba..0000000000
--- a/src/mainboard/google/volteer/variants/volteer2/include/variant/acpi/mipi_camera.asl
+++ /dev/null
@@ -1,3 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <baseboard/acpi/mipi_camera.asl>
diff --git a/src/mainboard/google/volteer/variants/volteer2/overridetree.cb b/src/mainboard/google/volteer/variants/volteer2/overridetree.cb
index ee181c86e0..f27bb77f98 100644
--- a/src/mainboard/google/volteer/variants/volteer2/overridetree.cb
+++ b/src/mainboard/google/volteer/variants/volteer2/overridetree.cb
@@ -117,7 +117,21 @@ chip soc/intel/tigerlake
 			probe DB_USB USB4_GEN3
 		end
 
-		device ref ipu on end # IPU                           0x9A19
+		device ref ipu on
+			chip drivers/intel/mipi_camera
+				register "acpi_uid" = "0x50000"
+				register "acpi_name" = ""IPU0""
+				register "device_type" = "INTEL_ACPI_CAMERA_CIO2"
+
+				register "cio2_num_ports" = "2"
+				register "cio2_lanes_used" = "{4,2}" # 4 and 2 CSI Camera lanes are used
+				register "cio2_lane_endpoint[0]" = ""^I2C3.CAM0""
+				register "cio2_lane_endpoint[1]" = ""^I2C2.CAM1""
+				register "cio2_prt[0]" = "5"
+				register "cio2_prt[1]" = "1"
+				device generic 0 on end
+			end
+		end
 		device ref i2c0 on
 			chip drivers/i2c/generic
 				register "hid" = ""10EC5682""
@@ -225,6 +239,129 @@ chip soc/intel/tigerlake
 				register "proxraw_strength" = "0"
 				device i2c 28 on end
 			end
+			chip drivers/intel/mipi_camera
+				register "acpi_hid" = ""INT3474""
+				register "acpi_uid" = "0"
+				register "acpi_name" = ""CAM1""
+				register "chip_name" = ""Ov 2740 Camera""
+				register "device_type" = "INTEL_ACPI_CAMERA_SENSOR"
+				register "has_power_resource" = "true"
+				register "low_power_probe" = "1"
+
+				register "ssdb.lanes_used" = "2"
+				register "ssdb.link_used" = "1"
+				register "ssdb.platform" = "PLAT_TGL"
+				register "num_freq_entries" = "1"
+				register "link_freq[0]" = "360 * MHz"
+				register "remote_name" = ""IPU0""
+				register "max_dstate_for_probe" = "ACPI_DEVICE_SLEEP_D3_COLD"
+
+				#Controls
+				register "clk_panel.clks[0].clknum" = "2"
+				register "clk_panel.clks[0].freq" = "FREQ_19_2_MHZ"
+
+				register "gpio_panel.gpio[0].gpio_num" = "GPP_D4" #reset
+				register "gpio_panel.gpio[1].gpio_num" = "GPP_D17" #power enable
+				register "gpio_panel.gpio[2].gpio_num" = "GPP_D18" #SNRPWR_EN
+
+				#_ON
+				register "on_seq.ops_cnt" = "5"
+				register "on_seq.ops[0]" = "SEQ_OPS_CLK_ENABLE(0, 0)"
+				register "on_seq.ops[1]" = "SEQ_OPS_GPIO_DISABLE(0, 0)" # RST low
+				register "on_seq.ops[2]" = "SEQ_OPS_GPIO_ENABLE(2, 0)" # SNRPWR_EN high
+				register "on_seq.ops[3]" = "SEQ_OPS_GPIO_ENABLE(1, 10)" # PWREN high, sleep 10ms
+				register "on_seq.ops[4]" = "SEQ_OPS_GPIO_ENABLE(0, 1)" # RST high, sleep 1ms
+
+				#_OFF
+				register "off_seq.ops_cnt" = "4"
+				register "off_seq.ops[0]" = "SEQ_OPS_CLK_DISABLE(0, 1)" # Disable clock, delay 1ms
+				register "off_seq.ops[1]" = "SEQ_OPS_GPIO_DISABLE(0, 0)" # RST low
+				register "off_seq.ops[2]" = "SEQ_OPS_GPIO_DISABLE(1, 0)" # PWREN low
+				register "off_seq.ops[3]" = "SEQ_OPS_GPIO_DISABLE(2, 0)" # SNRPWR_EN low
+
+				device i2c 10 on end
+			end
+		end
+		device ref i2c3 on
+			chip drivers/intel/mipi_camera
+				register "acpi_hid" = ""OVTI8856""
+				register "acpi_uid" = "0"
+				register "acpi_name" = ""CAM0""
+				register "chip_name" = ""Ov 8856 Camera""
+				register "device_type" = "INTEL_ACPI_CAMERA_SENSOR"
+				register "has_power_resource" = "true"
+				register "low_power_probe" = "1"
+
+				register "ssdb.lanes_used" = "4"
+				register "ssdb.link_used" = "0"
+				register "ssdb.platform" = "PLAT_TGL"
+				register "ssdb.vcm_type" = "VCM_DW9808"
+				register "vcm_address" = "0x0C"
+				register "vcm_name" = ""VCM0""
+				# placeholder; ROM type 24C1024 currently unsupported
+				# register "ssdb.rom_type" = "ROM_EEPROM_24C1024"
+				# register "rom_address" = "0x50"
+				register "num_freq_entries" = "2"
+				register "link_freq[0]" = "360 * MHz" # 360 MHz
+				register "link_freq[1]" = "180 * MHz" # 180 MHz
+				register "remote_name" = ""IPU0""
+				register "max_dstate_for_probe" = "ACPI_DEVICE_SLEEP_D3_COLD"
+
+				#Controls
+				register "clk_panel.clks[0].clknum" = "3"
+				register "clk_panel.clks[0].freq" = "FREQ_19_2_MHZ"
+
+				register "gpio_panel.gpio[0].gpio_num" = "GPP_F15" #reset
+				register "gpio_panel.gpio[1].gpio_num" = "GPP_H20" #power enable
+				register "gpio_panel.gpio[2].gpio_num" = "GPP_H14" #SNRPWR_EN
+
+				#_ON
+				register "on_seq.ops_cnt" = "5"
+				register "on_seq.ops[0]" = "SEQ_OPS_CLK_ENABLE(0, 0)"
+				register "on_seq.ops[1]" = "SEQ_OPS_GPIO_DISABLE(0, 0)" # RST low
+				register "on_seq.ops[2]" = "SEQ_OPS_GPIO_ENABLE(2, 0)" # SNRPWR_EN high
+				register "on_seq.ops[3]" = "SEQ_OPS_GPIO_ENABLE(1, 2)" # PWREN high, sleep 2ms
+				register "on_seq.ops[4]" = "SEQ_OPS_GPIO_ENABLE(0, 1)" # RST high, sleep 1ms
+
+				#_OFF
+				register "off_seq.ops_cnt" = "4"
+				register "off_seq.ops[0]" = "SEQ_OPS_CLK_DISABLE(0, 1)" # Disable clock, delay 1ms
+				register "off_seq.ops[1]" = "SEQ_OPS_GPIO_DISABLE(0, 0)" # RST low
+				register "off_seq.ops[2]" = "SEQ_OPS_GPIO_DISABLE(1, 0)" # PWREN low
+				register "off_seq.ops[3]" = "SEQ_OPS_GPIO_DISABLE(2, 0)" # SNRPWR_EN low
+
+				device i2c 10 on end
+			end
+			chip drivers/intel/mipi_camera
+				register "acpi_uid" = "2"
+				register "acpi_name" = ""VCM0""
+				register "chip_name" = ""DW9768 VCM""
+				register "device_type" = "INTEL_ACPI_CAMERA_VCM"
+
+				register "pr0" = ""\\_SB.PCI0.I2C3.CAM0.PRIC""
+				register "vcm_compat" = ""dongwoon,dw9768""
+				register "max_dstate_for_probe" = "ACPI_DEVICE_SLEEP_D0"
+
+				device i2c 0C on end
+			end
+			chip drivers/intel/mipi_camera
+				register "acpi_hid" = "ACPI_DT_NAMESPACE_HID"
+				register "acpi_uid" = "1"
+				register "acpi_name" = ""NVM0""
+				register "chip_name" = ""AT24 EEPROM""
+				register "device_type" = "INTEL_ACPI_CAMERA_NVM"
+				register "pr0" = ""\\_SB.PCI0.I2C3.CAM0.PRIC""
+
+				register "nvm_size" = "0x2800"
+				register "nvm_pagesize" = "1"
+				register "nvm_readonly" = "1"
+				register "nvm_width" = "0x10"
+				register "nvm_compat" = ""atmel,24c1024""
+
+				register "max_dstate_for_probe" = "ACPI_DEVICE_SLEEP_D0"
+
+				device i2c 58 on end
+			end
 		end
 		device ref i2c5 on
 			chip drivers/i2c/generic

From ede97ef9da9b34ed6d30bc57d4efa94bb3738676 Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Sat, 20 Dec 2025 15:50:50 -0600
Subject: [PATCH 2989/3886] mb/google/volteer: Add IPUA device and sensor names

Add missing configuration items for volteer variants to have functional
MIPI cameras under Windows/mainline Linux:

- Add IPUA device to graphics device configuration
- Add sensor_name register to sensor device configurations

Change-Id: Icd80ccc09b9c0436978d781fefb6ab85fbe71484
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90580
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
---
 src/mainboard/google/volteer/Kconfig             |  4 ++++
 .../volteer/variants/voema/overridetree.cb       | 15 +++++++++++++++
 .../volteer/variants/volteer/overridetree.cb     | 16 ++++++++++++++++
 .../volteer/variants/volteer2/overridetree.cb    | 16 ++++++++++++++++
 4 files changed, 51 insertions(+)

diff --git a/src/mainboard/google/volteer/Kconfig b/src/mainboard/google/volteer/Kconfig
index a32681d811..872d28540e 100644
--- a/src/mainboard/google/volteer/Kconfig
+++ b/src/mainboard/google/volteer/Kconfig
@@ -105,6 +105,7 @@ config BOARD_GOOGLE_TRONDO
 
 config BOARD_GOOGLE_VOEMA
 	select BOARD_GOOGLE_BASEBOARD_VOLTEER
+	select DRIVERS_GFX_GENERIC
 	select DRIVERS_INTEL_MIPI_CAMERA
 	select INTEL_GMA_HAVE_VBT
 
@@ -114,6 +115,7 @@ config BOARD_GOOGLE_VOLET
 
 config BOARD_GOOGLE_VOLTEER
 	select BOARD_GOOGLE_BASEBOARD_VOLTEER
+	select DRIVERS_GFX_GENERIC
 	select DRIVERS_INTEL_MIPI_CAMERA
 	select INTEL_CAR_NEM
 	select SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES
@@ -122,6 +124,7 @@ config BOARD_GOOGLE_VOLTEER2
 	select BOARD_GOOGLE_BASEBOARD_VOLTEER
 	select DRIVER_I2C_TPM_ACPI
 	select DRIVERS_GENESYSLOGIC_GL9755
+	select DRIVERS_GFX_GENERIC
 	select DRIVERS_INTEL_MIPI_CAMERA
 	select INTEL_GMA_HAVE_VBT
 	select SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES
@@ -130,6 +133,7 @@ config BOARD_GOOGLE_VOLTEER2_TI50
 	select BOARD_GOOGLE_BASEBOARD_VOLTEER
 	select DRIVER_I2C_TPM_ACPI
 	select DRIVERS_GENESYSLOGIC_GL9755
+	select DRIVERS_GFX_GENERIC
 	select DRIVERS_INTEL_MIPI_CAMERA
 	select SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES
 
diff --git a/src/mainboard/google/volteer/variants/voema/overridetree.cb b/src/mainboard/google/volteer/variants/voema/overridetree.cb
index ecb37987c7..6dce086fdc 100644
--- a/src/mainboard/google/volteer/variants/voema/overridetree.cb
+++ b/src/mainboard/google/volteer/variants/voema/overridetree.cb
@@ -9,6 +9,20 @@ chip soc/intel/tigerlake
 	register "typec_aux_bias_pads[0]" = "{.pad_auxp_dc = GPP_E10, .pad_auxn_dc = GPP_E13}"
 
 	device domain 0 on
+		device ref igpu on
+			chip drivers/gfx/generic
+				register "device_count" = "2"
+				# DDIA for eDP
+				register "device[0].name" = ""LCD0""
+				register "device[0].type" = "panel"
+				# IPUA for IPU camera
+				register "device[1].name" = ""IPUA""
+				register "device[1].non_vga_device" = "true"
+				register "device[1].addr" = "0x3480"
+				device generic 0 on end
+			end
+		end
+
 		device ref ipu on
 			chip drivers/intel/mipi_camera
 				register "acpi_uid" = "0x50000"
@@ -80,6 +94,7 @@ chip soc/intel/tigerlake
 				register "acpi_uid" = "0"
 				register "acpi_name" = ""CAM1""
 				register "chip_name" = ""Ov 2740 Camera""
+				register "sensor_name" = ""CJFLE23""
 				register "device_type" = "INTEL_ACPI_CAMERA_SENSOR"
 				register "has_power_resource" = "true"
 
diff --git a/src/mainboard/google/volteer/variants/volteer/overridetree.cb b/src/mainboard/google/volteer/variants/volteer/overridetree.cb
index 21e6c63e55..9ffe08aa48 100644
--- a/src/mainboard/google/volteer/variants/volteer/overridetree.cb
+++ b/src/mainboard/google/volteer/variants/volteer/overridetree.cb
@@ -63,6 +63,20 @@ chip soc/intel/tigerlake
 			probe DB_USB USB4_GEN3
 		end
 
+		device ref igpu on
+			chip drivers/gfx/generic
+				register "device_count" = "2"
+				# DDIA for eDP
+				register "device[0].name" = ""LCD0""
+				register "device[0].type" = "panel"
+				# IPUA for IPU cameras
+				register "device[1].name" = ""IPUA""
+				register "device[1].non_vga_device" = "true"
+				register "device[1].addr" = "0x3480"
+				device generic 0 on end
+			end
+		end
+
 		device ref ipu on
 			chip drivers/intel/mipi_camera
 				register "acpi_uid" = "0x50000"
@@ -185,6 +199,7 @@ chip soc/intel/tigerlake
 				register "acpi_uid" = "0"
 				register "acpi_name" = ""CAM1""
 				register "chip_name" = ""Ov 2740 Camera""
+				register "sensor_name" = ""CJFLE23""
 				register "device_type" = "INTEL_ACPI_CAMERA_SENSOR"
 				register "has_power_resource" = "true"
 				register "low_power_probe" = "1"
@@ -229,6 +244,7 @@ chip soc/intel/tigerlake
 				register "acpi_uid" = "0"
 				register "acpi_name" = ""CAM0""
 				register "chip_name" = ""Ov 8856 Camera""
+				register "sensor_name" = ""CJAJ813""
 				register "device_type" = "INTEL_ACPI_CAMERA_SENSOR"
 				register "has_power_resource" = "true"
 				register "low_power_probe" = "1"
diff --git a/src/mainboard/google/volteer/variants/volteer2/overridetree.cb b/src/mainboard/google/volteer/variants/volteer2/overridetree.cb
index f27bb77f98..782ebcb4c1 100644
--- a/src/mainboard/google/volteer/variants/volteer2/overridetree.cb
+++ b/src/mainboard/google/volteer/variants/volteer2/overridetree.cb
@@ -117,6 +117,20 @@ chip soc/intel/tigerlake
 			probe DB_USB USB4_GEN3
 		end
 
+		device ref igpu on
+			chip drivers/gfx/generic
+				register "device_count" = "2"
+				# DDIA for eDP
+				register "device[0].name" = ""LCD0""
+				register "device[0].type" = "panel"
+				# IPUA for IPU cameras
+				register "device[1].name" = ""IPUA""
+				register "device[1].non_vga_device" = "true"
+				register "device[1].addr" = "0x3480"
+				device generic 0 on end
+			end
+		end
+
 		device ref ipu on
 			chip drivers/intel/mipi_camera
 				register "acpi_uid" = "0x50000"
@@ -244,6 +258,7 @@ chip soc/intel/tigerlake
 				register "acpi_uid" = "0"
 				register "acpi_name" = ""CAM1""
 				register "chip_name" = ""Ov 2740 Camera""
+				register "sensor_name" = ""CJFLE23""
 				register "device_type" = "INTEL_ACPI_CAMERA_SENSOR"
 				register "has_power_resource" = "true"
 				register "low_power_probe" = "1"
@@ -288,6 +303,7 @@ chip soc/intel/tigerlake
 				register "acpi_uid" = "0"
 				register "acpi_name" = ""CAM0""
 				register "chip_name" = ""Ov 8856 Camera""
+				register "sensor_name" = ""CJAJ813""
 				register "device_type" = "INTEL_ACPI_CAMERA_SENSOR"
 				register "has_power_resource" = "true"
 				register "low_power_probe" = "1"

From ceaa41c9e47cc43278af2f0c6ba7612c204f5de1 Mon Sep 17 00:00:00 2001
From: Pranava Y N <pranavayn@google.com>
Date: Thu, 8 Jan 2026 13:15:23 +0530
Subject: [PATCH 2990/3886] drv/intel/mipi_camera: Verify SSDB only for camera
 sensors

The MIPI camera driver currently validates SSDB parameters for all
devices using the driver. However, some devices (VCM/NVM) does not have
these parameters configured.

Wrap the SSDB verification logic in a check for
`INTEL_ACPI_CAMERA_SENSOR`. This prevents the driver from throwing
"Parameters not set" errors and failing to create ACPI devices for
non-sensor devices.

BUG=b:474223827
TEST=Build and boot fatcat, verify that MIPI initialization no longer
fails for non-sensor MIPI devices while still enforcing validation for
actual camera sensors.

Change-Id: I34ef416cdc9fa35fdca21e9fecaa8d7fc2914338
Signed-off-by: Pranava Y N <pranavayn@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90697
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
---
 src/drivers/intel/mipi_camera/camera.c | 11 ++++++++++-
 1 file changed, 10 insertions(+), 1 deletion(-)

diff --git a/src/drivers/intel/mipi_camera/camera.c b/src/drivers/intel/mipi_camera/camera.c
index 1b2fc692d8..79c0616ccf 100644
--- a/src/drivers/intel/mipi_camera/camera.c
+++ b/src/drivers/intel/mipi_camera/camera.c
@@ -1219,10 +1219,19 @@ static struct device_operations camera_ops = {
 
 static void camera_enable(struct device *dev)
 {
-	//Validate Camera Parameters
+	/* Validate Camera Parameters */
 	struct drivers_intel_mipi_camera_config *config = dev->chip_info;
 	bool params_error = false;
 
+	/*
+	 * Non-sensor devices (like an aggregator) don't need
+	 * SSDB validation, just assign ops and return.
+	 */
+	if (config->device_type != INTEL_ACPI_CAMERA_SENSOR) {
+		dev->ops = &camera_ops;
+		return;
+	}
+
 	if (!config->ssdb.lanes_used) {
 		printk(BIOS_ERR, "MIPI camera: SSDB lanes_used not set\n");
 		params_error = true;

From 5034f8629f646f713528a30353f96b83bd4b2a3e Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Sat, 29 Nov 2025 15:03:34 -0600
Subject: [PATCH 2991/3886] soc/intel/common: Add spinlock protection to fast
 SPI flash operations
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Add spinlock synchronization to prevent concurrent SPI flash controller
access from multiple CPUs in SMP environments. The spinlock serializes
access to the SPI controller hardware in exec_sync_hwseq_xfer().

If SMP is not enabled, spinlock functions are no-ops, so this change
is safe for both SMP and non-SMP configurations.

This resolves an issue seen on the Starlabs Starfighter MTL where
multiple SPI transaction errors occurred when reading option variables
stored in SMMSTORE:

[ERROR] SPI Transaction Error at Flash Offset 103002a HSFSTS = 0x01016022
[ERROR] SPI Transaction Error at Flash Offset 1030004 HSFSTS = 0x01006022
[ERROR] SPI Transaction Error at Flash Offset 1030000 HSFSTS = 0x3f006022
...

Change-Id: Ic3003b0a986b587622102b6f36714bcb16c3d976
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90283
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
---
 .../common/block/fast_spi/fast_spi_flash.c    | 21 +++++++++++++++++--
 1 file changed, 19 insertions(+), 2 deletions(-)

diff --git a/src/soc/intel/common/block/fast_spi/fast_spi_flash.c b/src/soc/intel/common/block/fast_spi/fast_spi_flash.c
index a7762711fa..89ae6d2cd3 100644
--- a/src/soc/intel/common/block/fast_spi/fast_spi_flash.c
+++ b/src/soc/intel/common/block/fast_spi/fast_spi_flash.c
@@ -9,6 +9,7 @@
 #include <spi_flash.h>
 #include <string.h>
 #include <timer.h>
+#include <smp/spinlock.h>
 
 /* Helper to create a FAST_SPI context on API entry. */
 #define BOILERPLATE_CREATE_CTX(ctx)		\
@@ -32,6 +33,9 @@ struct fast_spi_flash_ctx {
 	uintptr_t mmio_base;
 };
 
+/* Spinlock to protect concurrent SPI flash controller access from multiple CPUs */
+DECLARE_SPIN_LOCK(fast_spi_lock);
+
 static void _fast_spi_flash_get_ctx(struct fast_spi_flash_ctx *ctx)
 {
 	ctx->mmio_base = (uintptr_t)fast_spi_get_bar();
@@ -160,15 +164,28 @@ static int exec_sync_hwseq_xfer(struct fast_spi_flash_ctx *ctx,
 				uint32_t hsfsts_cycle, uint32_t flash_addr,
 				size_t len)
 {
+	int ret;
+
+	/* Protect SPI flash controller from concurrent access by multiple CPUs.
+	 * The spinlock serializes access to the SPI controller hardware.
+	 * If SMP is not enabled, spinlock functions are no-ops.
+	 */
+	spin_lock(&fast_spi_lock);
+
 	if (wait_for_hwseq_spi_cycle_complete(ctx) != SUCCESS) {
 		printk(BIOS_ERR, "SPI Transaction Timeout (Exceeded %d ms) due to prior"
 				" operation at Flash Offset %x\n",
 				SPIBAR_HWSEQ_XFER_TIMEOUT_MS, flash_addr);
-		return E_TIMEOUT;
+		ret = E_TIMEOUT;
+		goto unlock;
 	}
 
 	start_hwseq_xfer(ctx, hsfsts_cycle, flash_addr, len);
-	return wait_for_hwseq_xfer(ctx, flash_addr);
+	ret = wait_for_hwseq_xfer(ctx, flash_addr);
+
+unlock:
+	spin_unlock(&fast_spi_lock);
+	return ret;
 }
 
 int fast_spi_cycle_in_progress(void)

From 16cb8d0d0c9b29322f646755c62a14ce29473a04 Mon Sep 17 00:00:00 2001
From: Subrata Banik <subratabanik@google.com>
Date: Thu, 8 Jan 2026 16:41:02 +0530
Subject: [PATCH 2992/3886] mb/google/bluey: Add power sequencing for USB-C1
 retimer

This patch implements the power-on and reset sequence for the USB-C1
retimer on the Bluey mainboard.

Sequence Details:
 - romstage: Added early_setup_usb_typec to ensure all power rails
   (3.3V, 1.8V, 0.9V) are disabled and the retimer is held in reset
   early in the boot process.
 - ramstage (mainboard): Added setup_usb_typec to perform the power-up
   sequence with the required 1ms delays between rails to ensure
   hardware stability:

BUG=b:473489095
TEST=Able to detect USB devices in HS mode.

Change-Id: Ia93c0078aecdec98f3af28e73e7af5af7a3b20d8
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90699
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Pranava Y N <pranavayn@google.com>
Reviewed-by: Jayvik Desai <jayvik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
---
 src/mainboard/google/bluey/board.h     |  6 ++++++
 src/mainboard/google/bluey/mainboard.c | 14 ++++++++++++++
 src/mainboard/google/bluey/romstage.c  | 16 ++++++++++++++++
 3 files changed, 36 insertions(+)

diff --git a/src/mainboard/google/bluey/board.h b/src/mainboard/google/bluey/board.h
index 3260b283c7..3d42d89a48 100644
--- a/src/mainboard/google/bluey/board.h
+++ b/src/mainboard/google/bluey/board.h
@@ -44,6 +44,12 @@
 #define GPIO_USB_CAM_RESET_L	GPIO(10)
 #define GPIO_USB_CAM_ENABLE	GPIO(206)
 
+/* USB-C1 port specific GPIOs */
+#define GPIO_USB_C1_EN_PP3300		GPIO(186)
+#define GPIO_USB_C1_EN_PP1800		GPIO(175)
+#define GPIO_USB_C1_EN_PP0900		GPIO(188)
+#define GPIO_USB_C1_RETIMER_RESET_L	GPIO(176)
+
 void setup_chromeos_gpios(void);
 bool is_off_mode(void);
 void configure_parallel_charging(void);
diff --git a/src/mainboard/google/bluey/mainboard.c b/src/mainboard/google/bluey/mainboard.c
index b93b4188db..b37c0b1e8a 100644
--- a/src/mainboard/google/bluey/mainboard.c
+++ b/src/mainboard/google/bluey/mainboard.c
@@ -6,6 +6,7 @@
 #include <commonlib/bsd/cbmem_id.h>
 #include <commonlib/coreboot_tables.h>
 #include <console/console.h>
+#include <delay.h>
 #include <device/device.h>
 #include <ec/google/chromeec/ec.h>
 #include <gpio.h>
@@ -50,8 +51,21 @@ static void enable_usb_camera(void)
 	gpio_output(GPIO_USB_CAM_ENABLE, 1);
 }
 
+static void setup_usb_typec(void)
+{
+	gpio_output(GPIO_USB_C1_EN_PP3300, 1);
+	mdelay(1);
+	gpio_output(GPIO_USB_C1_EN_PP1800, 1);
+	mdelay(1);
+	gpio_output(GPIO_USB_C1_EN_PP0900, 1);
+	mdelay(1);
+	gpio_output(GPIO_USB_C1_RETIMER_RESET_L, 1);
+}
+
 static void setup_usb(void)
 {
+	setup_usb_typec();
+
 	enable_usb_camera();
 	setup_usb_host0();
 }
diff --git a/src/mainboard/google/bluey/romstage.c b/src/mainboard/google/bluey/romstage.c
index 1c6660112e..e0f1f05743 100644
--- a/src/mainboard/google/bluey/romstage.c
+++ b/src/mainboard/google/bluey/romstage.c
@@ -86,6 +86,19 @@ static void platform_dump_battery_soc_information(void)
 		printk(BIOS_INFO, "Battery state-of-charge %d%%\n", batt_pct);
 }
 
+static void early_setup_usb_typec(void)
+{
+	gpio_output(GPIO_USB_C1_RETIMER_RESET_L, 0);
+	gpio_output(GPIO_USB_C1_EN_PP3300, 0);
+	gpio_output(GPIO_USB_C1_EN_PP1800, 0);
+	gpio_output(GPIO_USB_C1_EN_PP0900, 0);
+}
+
+static void early_setup_usb(void)
+{
+	early_setup_usb_typec();
+}
+
 void platform_romstage_main(void)
 {
 	/* Watchdog must be checked first to avoid erasing watchdog info later. */
@@ -107,6 +120,9 @@ void platform_romstage_main(void)
 
 	qclib_rerun();
 
+	/* Setup early USB related config */
+	early_setup_usb();
+
 	/*
 	 * Enable this power rail now for FPMCU stability prior to
 	 * its reset being deasserted in ramstage. This applies

From 17a52ce94e3c4878c38fbf4d1368a7954e1a07ad Mon Sep 17 00:00:00 2001
From: Kapil Porwal <kapilporwal@google.com>
Date: Fri, 9 Jan 2026 13:23:01 +0530
Subject: [PATCH 2993/3886] soc/qualcomm/x1p42100: Add mainboard USB Type-C
 config hook

Add a function declaration for mainboard_usb_typec_configure. This
allows mainboards to implement custom logic for external components,
such as retimers or muxes, that need orientation-aware configuration.

BUG=b:473489095
TEST=Verify USB SS detection on Quartz.

Change-Id: I20d9a23da5b855a413f8358b8783f44c1632ccdf
Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90709
Reviewed-by: Pranava Y N <pranavayn@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Jayvik Desai <jayvik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/soc/qualcomm/x1p42100/include/soc/usb/usb.h | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/src/soc/qualcomm/x1p42100/include/soc/usb/usb.h b/src/soc/qualcomm/x1p42100/include/soc/usb/usb.h
index 250ae55c70..8284656cb8 100644
--- a/src/soc/qualcomm/x1p42100/include/soc/usb/usb.h
+++ b/src/soc/qualcomm/x1p42100/include/soc/usb/usb.h
@@ -155,3 +155,5 @@ void usb_update_refclk_for_core(u32 core_num, bool enable);
 void enable_vbus_ss(const struct dwc3_controller_config *config);
 /* Reads comprehensive Type-C status from PMIC */
 void usb_typec_status_check(const struct dwc3_controller_config *config);
+/* Performs mainboard-specific USB Type-C configuration */
+void mainboard_usb_typec_configure(uint8_t port_num, bool inverse_polarity);

From 657bcd32d9bfbb85cd55d2dec63f213de4cca303 Mon Sep 17 00:00:00 2001
From: Kapil Porwal <kapilporwal@google.com>
Date: Fri, 9 Jan 2026 13:25:22 +0530
Subject: [PATCH 2994/3886] mb/google/bluey: Add Kconfig for PS8820 retimer
 support

Introduce the MAINBOARD_HAS_PS8820_RETIMER Kconfig option. This will
be used to conditionally enable I2C initialization and retimer
configuration logic on Bluey variants.

BUG=b:473489095
TEST=Verify USB SS detection on Quartz.

Change-Id: I949fb16f8c46a8375b50d2b108b8edde3231f4e9
Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90710
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Jayvik Desai <jayvik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Pranava Y N <pranavayn@google.com>
---
 src/mainboard/google/bluey/Kconfig | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/src/mainboard/google/bluey/Kconfig b/src/mainboard/google/bluey/Kconfig
index e5665ea752..7e21106cbc 100644
--- a/src/mainboard/google/bluey/Kconfig
+++ b/src/mainboard/google/bluey/Kconfig
@@ -91,6 +91,12 @@ config MAINBOARD_HAS_SD_CONTROLLER
 	help
 	  Enable this option if your mainboard is equipped with SD card controller.
 
+config MAINBOARD_HAS_PS8820_RETIMER
+	bool
+	default n
+	help
+	  Enable this option if your mainboard is equipped with a PS8820 retimer.
+
 config MAINBOARD_NO_USB_A_PORT
 	bool
 	default n

From f9efe53cb0966e2b103c0a1d2e84893bf3a02233 Mon Sep 17 00:00:00 2001
From: Kapil Porwal <kapilporwal@google.com>
Date: Fri, 9 Jan 2026 13:27:03 +0530
Subject: [PATCH 2995/3886] mb/google/bluey: Implement PS8820 retimer
 configuration

Implement mainboard_usb_typec_configure to program the Parade PS8820
retimers over I2C. The function sets the USB3 mode registers for
either normal or flipped orientation based on the polarity reported
by the SoC.

Additionally, update mainboard_init to perform standard I2C
initialization for the retimer buses when this feature is enabled,
ensuring the buses are ready for transactions during the USB
sequencing.

BUG=b:473489095
TEST=Verify USB SS detection on Quartz.

Sample output:
```
firmware-shell: md 0x0a800420 8
0a800420: 000002a0 00000000 00000000 00000000    ................
0a800430: 00001203 00000000 00000000 00000000    ................
firmware-shell: md 0x0a600420 8
0a600420: 000002a0 00000000 00000000 00000000    ................
0a600430: 00001203 00000000 00000000 00000000    ................
```

Change-Id: I14f86945aeea9b83a9433edd53f5023231ca859d
Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90707
Reviewed-by: Jayvik Desai <jayvik@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Pranava Y N <pranavayn@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/google/bluey/mainboard.c | 37 +++++++++++++++++++++++---
 1 file changed, 33 insertions(+), 4 deletions(-)

diff --git a/src/mainboard/google/bluey/mainboard.c b/src/mainboard/google/bluey/mainboard.c
index b37c0b1e8a..91c0f3dfad 100644
--- a/src/mainboard/google/bluey/mainboard.c
+++ b/src/mainboard/google/bluey/mainboard.c
@@ -8,16 +8,42 @@
 #include <console/console.h>
 #include <delay.h>
 #include <device/device.h>
+#include <device/i2c_simple.h>
 #include <ec/google/chromeec/ec.h>
 #include <gpio.h>
 #include <soc/clock.h>
 #include <soc/pcie.h>
 #include <soc/qupv3_config_common.h>
+#include <soc/qupv3_i2c_common.h>
 #include <soc/qup_se_handlers_common.h>
 #include "board.h"
 #include <soc/rpmh_config.h>
 #include <soc/usb/usb.h>
 
+#define C0_RETIMER_I2C_BUS	0x03
+#define C1_RETIMER_I2C_BUS	0x07
+#define PS8820_SLAVE_ADDR	0x08
+
+#define PS8820_USB_PORT_CONN_STATUS_REG	0x00
+#define USB3_MODE_NORMAL_VAL	0x21
+#define USB3_MODE_FLIP_VAL	0x23
+
+void mainboard_usb_typec_configure(uint8_t port_num, bool inverse_polarity)
+{
+	if (!CONFIG(MAINBOARD_HAS_PS8820_RETIMER))
+		return;
+
+	/* There are only two ports (0 and 1) */
+	if (port_num > 1) {
+		printk(BIOS_WARNING, "Invalid USB Type-C port number (%d)!\n", port_num);
+		return;
+	}
+
+	uint8_t bus = port_num ? C1_RETIMER_I2C_BUS : C0_RETIMER_I2C_BUS;
+	uint8_t mode_value = inverse_polarity ? USB3_MODE_FLIP_VAL : USB3_MODE_NORMAL_VAL;
+	i2c_writeb(bus, PS8820_SLAVE_ADDR, PS8820_USB_PORT_CONN_STATUS_REG, mode_value);
+}
+
 /*
  * This function calls the underlying PMIC/EC function only once during the
  * first execution and caches the result for all subsequent calls.
@@ -136,11 +162,14 @@ static void mainboard_init(struct device *dev)
 	/* ADSP I2C (Charger/Fuel gauge) */
 	qupv3_se_fw_load_and_init(QUPV3_2_SE4, SE_PROTOCOL_I2C, GSI);
 
-	/* USB-C0 Re-Timer I2C */
-	qupv3_se_fw_load_and_init(QUPV3_0_SE3, SE_PROTOCOL_I2C, MIXED);
 
-	/* USB-C1 Re-Timer I2C */
-	qupv3_se_fw_load_and_init(QUPV3_0_SE7, SE_PROTOCOL_I2C, MIXED);
+	if (CONFIG(MAINBOARD_HAS_PS8820_RETIMER)) {
+		i2c_init(QUPV3_0_SE3, I2C_SPEED_FAST); /* USB-C0 Re-Timer I2C */
+		i2c_init(QUPV3_0_SE7, I2C_SPEED_FAST); /* USB-C1 Re-Timer I2C */
+	} else {
+		qupv3_se_fw_load_and_init(QUPV3_0_SE3, SE_PROTOCOL_I2C, MIXED); /* USB-C0 Re-Timer I2C */
+		qupv3_se_fw_load_and_init(QUPV3_0_SE7, SE_PROTOCOL_I2C, MIXED); /* USB-C1 Re-Timer I2C */
+	}
 
 	if (!CONFIG(MAINBOARD_NO_USB_A_PORT))
 		qupv3_se_fw_load_and_init(QUPV3_0_SE1, SE_PROTOCOL_I2C, MIXED); /* USB-A retimer */

From e303357cb9ccba52d07d670970b3750186fe8033 Mon Sep 17 00:00:00 2001
From: Kapil Porwal <kapilporwal@google.com>
Date: Fri, 9 Jan 2026 13:28:53 +0530
Subject: [PATCH 2996/3886] soc/qualcomm/x1p42100: Call mainboard Type-C config
 hook

Update the SoC USB driver to invoke mainboard_usb_typec_configure for
both primary and secondary ports. This is called after the QMP PHY
initialization to ensure the external signal path is correctly
muxed for the detected orientation.

BUG=b:473489095
TEST=Verify USB SS detection on Quartz.

Sample output:
```
firmware-shell: md 0x0a800420 8
0a800420: 000002a0 00000000 00000000 00000000    ................
0a800430: 00001203 00000000 00000000 00000000    ................
firmware-shell: md 0x0a600420 8
0a600420: 000002a0 00000000 00000000 00000000    ................
0a600430: 00001203 00000000 00000000 00000000    ................
```

Change-Id: Ic90a62b1f6ad62a8870c6d5333d06b6a11d26d4f
Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90711
Reviewed-by: Pranava Y N <pranavayn@google.com>
Reviewed-by: Jayvik Desai <jayvik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
---
 src/soc/qualcomm/x1p42100/usb/usb.c | 8 ++++++--
 1 file changed, 6 insertions(+), 2 deletions(-)

diff --git a/src/soc/qualcomm/x1p42100/usb/usb.c b/src/soc/qualcomm/x1p42100/usb/usb.c
index ec61ebd5be..5865a35d01 100644
--- a/src/soc/qualcomm/x1p42100/usb/usb.c
+++ b/src/soc/qualcomm/x1p42100/usb/usb.c
@@ -581,7 +581,8 @@ static void setup_usb_host(struct usb_dwc3_cfg *dwc3)
 	clock_reset_bcr(dwc3->gcc_usb4_0_dp0_phy_prim_bcr, 0);
 	udelay(10);
 	/* Initialize USB4/USB3 EDP_DP_Con PHY Configuration */
-	int ss0_ret = qmp_usb4_dp_phy_ss_init(0, get_usb_typec_polarity(&prim_config));
+	bool polarity_prim = get_usb_typec_polarity(&prim_config);
+	int ss0_ret = qmp_usb4_dp_phy_ss_init(0, polarity_prim);
 	if (ss0_ret != CB_SUCCESS) {
 		printk(BIOS_ERR, "SS0 QMP PHY initialization failed\n");
 		high_speed_only_primary = true;
@@ -590,6 +591,7 @@ static void setup_usb_host(struct usb_dwc3_cfg *dwc3)
 	enable_vbus_ss(&prim_config);
 	udelay(50);
 	usb_typec_status_check(&prim_config);
+	mainboard_usb_typec_configure(0, polarity_prim);
 
 	/* Type C port 1 - C1 */
 	/* Reset USB secondary[C1] PHY BCRs */
@@ -610,7 +612,8 @@ static void setup_usb_host(struct usb_dwc3_cfg *dwc3)
 	clock_reset_bcr(dwc3->gcc_usb4_1_dp0_phy_sec_bcr, 0);
 	udelay(10);
 	/* Initialize USB4/USB3 EDP_DP_Con PHY Configuration (secondary) */
-	int ss1_ret = qmp_usb4_dp_phy_ss_init(1, get_usb_typec_polarity(&sec_config));
+	bool polarity_sec = get_usb_typec_polarity(&sec_config);
+	int ss1_ret = qmp_usb4_dp_phy_ss_init(1, polarity_sec);
 	if (ss1_ret != CB_SUCCESS) {
 		printk(BIOS_ERR, "SS1 QMP PHY initialization failed\n");
 		high_speed_only_secondary = true;
@@ -619,6 +622,7 @@ static void setup_usb_host(struct usb_dwc3_cfg *dwc3)
 	enable_vbus_ss(&sec_config);
 	udelay(50);
 	usb_typec_status_check(&sec_config);
+	mainboard_usb_typec_configure(1, polarity_sec);
 
 	/* Initialize USB Controller for Type A */
 	setup_dwc3(dwc3->usb_host_dwc3);

From c45e153dfbf3638816d257208d1a3f5bc4dba8f4 Mon Sep 17 00:00:00 2001
From: Kapil Porwal <kapilporwal@google.com>
Date: Fri, 9 Jan 2026 13:30:00 +0530
Subject: [PATCH 2997/3886] mb/google/bluey/var/quartz: Enable PS8820 support

Select MAINBOARD_HAS_PS8820_RETIMER for the Quartz board variant.
Quartz uses external PS8820 retimers that require explicit
configuration to achieve SuperSpeed data rates.

BUG=b:473489095
TEST=Verify USB SS detection on Quartz.

Sample xHCI PORTSC register output:
```
firmware-shell: md 0x0a800420 8
0a800420: 000002a0 00000000 00000000 00000000    ................
0a800430: 00001203 00000000 00000000 00000000    ................
firmware-shell: md 0x0a600420 8
0a600420: 000002a0 00000000 00000000 00000000    ................
0a600430: 00001203 00000000 00000000 00000000    ................
```

Change-Id: Ibb801adc5f7e874a403c644a5c1b3aa592a3d067
Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90712
Reviewed-by: Jayvik Desai <jayvik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Pranava Y N <pranavayn@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
---
 src/mainboard/google/bluey/Kconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/src/mainboard/google/bluey/Kconfig b/src/mainboard/google/bluey/Kconfig
index 7e21106cbc..163650702f 100644
--- a/src/mainboard/google/bluey/Kconfig
+++ b/src/mainboard/google/bluey/Kconfig
@@ -56,6 +56,7 @@ config BOARD_GOOGLE_QUENBIH
 config BOARD_GOOGLE_QUARTZ
 	select BOARD_GOOGLE_MODEL_QUARTZ
 	select SOC_QUALCOMM_HAMOA
+	select MAINBOARD_HAS_PS8820_RETIMER
 	select MAINBOARD_NO_USB_A_PORT
 	select MAINBOARD_SUPPORTS_PARALLEL_CHARGING
 

From 18a986c5fe63a5e801e9cdd493a903d588312a0a Mon Sep 17 00:00:00 2001
From: Maximilian Brune <maximilian.brune@9elements.com>
Date: Tue, 26 Aug 2025 02:17:56 +0200
Subject: [PATCH 2998/3886] soc/amd/cmn/block/cpu/mca: Support MCA_SYND1 and
 MCA_SYND2
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

The number of MCAX register used inside an MCA BANK changed from phoenix
onwards. Since phoenix all 16 MCAX register are used inside an MCA bank.

According to spec:
The MCA_SYND register stores a syndrome associated with the error logged
in MCA_STATUS or MCA_DESTAT. The “syndrome” may include syndrome values
associated with an error correcting code or other information about the
error. The contents of this register are valid if MCA_STATUS[SYNDV] bit
is set to 1 or MCA_DESTAT[SYNDV] bit is set to 1.

source: AMD64 Architecture Programmers Manual Rev 3.42

Change-Id: I20a31776d4b031c810ef0dc6502c421ade6f4315
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90640
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
---
 src/soc/amd/common/block/cpu/mca/mcax.c           | 10 ++++++++--
 src/soc/amd/common/block/cpu/mca/mcax_bert.c      | 15 +++++++--------
 .../amd/common/block/include/amdblocks/msr_zen.h  |  5 +++++
 3 files changed, 20 insertions(+), 10 deletions(-)

diff --git a/src/soc/amd/common/block/cpu/mca/mcax.c b/src/soc/amd/common/block/cpu/mca/mcax.c
index 46c72f00a8..ad4f67e47d 100644
--- a/src/soc/amd/common/block/cpu/mca/mcax.c
+++ b/src/soc/amd/common/block/cpu/mca/mcax.c
@@ -20,14 +20,14 @@ bool mca_skip_check(void)
 /* Print the contents of the MCAX registers for a given bank */
 void mca_print_error(unsigned int bank)
 {
-	msr_t msr;
+	msr_t msr, mca_status;
 
 	printk(BIOS_WARNING, "#MC Error: core %u, bank %u %s\n", initial_lapicid(), bank,
 		mca_get_bank_name(bank));
 
 	msr = rdmsr(MCAX_CTL_MSR(bank));
 	printk(BIOS_WARNING, "   MC%u_CTL =      %08x_%08x\n", bank, msr.hi, msr.lo);
-	msr = rdmsr(MCAX_STATUS_MSR(bank));
+	msr = mca_status = rdmsr(MCAX_STATUS_MSR(bank));
 	printk(BIOS_WARNING, "   MC%u_STATUS =   %08x_%08x\n", bank, msr.hi, msr.lo);
 	msr = rdmsr(MCAX_ADDR_MSR(bank));
 	printk(BIOS_WARNING, "   MC%u_ADDR =     %08x_%08x\n", bank, msr.hi, msr.lo);
@@ -51,6 +51,12 @@ void mca_print_error(unsigned int bank)
 	printk(BIOS_WARNING, "   MC%u_MISC3 =    %08x_%08x\n", bank, msr.hi, msr.lo);
 	msr = rdmsr(MCAX_MISC4_MSR(bank));
 	printk(BIOS_WARNING, "   MC%u_MISC4 =    %08x_%08x\n", bank, msr.hi, msr.lo);
+	if (mca_syndv(mca_status)) {
+		msr = rdmsr(MCAX_SYND1_MSR(bank));
+		printk(BIOS_WARNING, "   MC%u_SYND1 =    %08x_%08x\n", bank, msr.hi, msr.lo);
+		msr = rdmsr(MCAX_SYND2_MSR(bank));
+		printk(BIOS_WARNING, "   MC%u_SYND2 =    %08x_%08x\n", bank, msr.hi, msr.lo);
+	}
 	msr = rdmsr(MCA_CTL_MASK_MSR(bank));
 	printk(BIOS_WARNING, "   MC%u_CTL_MASK = %08x_%08x\n", bank, msr.hi, msr.lo);
 }
diff --git a/src/soc/amd/common/block/cpu/mca/mcax_bert.c b/src/soc/amd/common/block/cpu/mca/mcax_bert.c
index af2bee407d..80ee534f45 100644
--- a/src/soc/amd/common/block/cpu/mca/mcax_bert.c
+++ b/src/soc/amd/common/block/cpu/mca/mcax_bert.c
@@ -10,10 +10,7 @@
 #include <types.h>
 #include "mca_common_defs.h"
 
-/* MISC4 is the last used register in the MCAX banks of Picasso */
-#define MCAX_USED_REGISTERS_PER_BANK	(MCAX_MISC4_OFFSET + 1)
-
-static inline size_t mca_report_size_reqd(void)
+static inline size_t mca_report_size_reqd(int used_registers_per_bank)
 {
 	size_t size;
 
@@ -32,8 +29,8 @@ static inline size_t mca_report_size_reqd(void)
 	size += cper_ia32x64_ctx_sz_bytype(CPER_IA32X64_CTX_MSR, 3);
 
 	/* Context of CTL, STATUS, ADDR, MISC0, CONFIG, IPID, SYND, RESERVED, DESTAT, DEADDR,
-	   MISC1, MISC2, MISC3, MISC4 */
-	size += cper_ia32x64_ctx_sz_bytype(CPER_IA32X64_CTX_MSR, MCAX_USED_REGISTERS_PER_BANK);
+	   MISC1, MISC2, MISC3, MISC4, SYND0, SYND1 */
+	size += cper_ia32x64_ctx_sz_bytype(CPER_IA32X64_CTX_MSR, used_registers_per_bank);
 
 	/* Context of CTL_MASK */
 	size += cper_ia32x64_ctx_sz_bytype(CPER_IA32X64_CTX_MSR, 1);
@@ -57,7 +54,9 @@ void build_bert_mca_error(struct mca_bank_status *mci)
 	cper_ia32x64_proc_error_info_t *chk;
 	cper_ia32x64_context_t *ctx;
 
-	if (mca_report_size_reqd() > bert_storage_remaining())
+	int used_registers_per_bank = mca_syndv(mci->sts) ? 16 : 14;
+
+	if (mca_report_size_reqd(used_registers_per_bank) > bert_storage_remaining())
 		goto failed;
 
 	status = bert_new_event(&CPER_SEC_PROC_GENERIC_GUID);
@@ -80,7 +79,7 @@ void build_bert_mca_error(struct mca_bank_status *mci)
 	if (!ctx)
 		goto failed;
 	ctx = cper_new_ia32x64_context_msr(status, x86_sec, MCAX_CTL_MSR(mci->bank),
-					   MCAX_USED_REGISTERS_PER_BANK);
+					   used_registers_per_bank);
 	if (!ctx)
 		goto failed;
 	ctx = cper_new_ia32x64_context_msr(status, x86_sec, MCA_CTL_MASK_MSR(mci->bank), 1);
diff --git a/src/soc/amd/common/block/include/amdblocks/msr_zen.h b/src/soc/amd/common/block/include/amdblocks/msr_zen.h
index 0e2d2c8fec..cde4d7bdda 100644
--- a/src/soc/amd/common/block/include/amdblocks/msr_zen.h
+++ b/src/soc/amd/common/block/include/amdblocks/msr_zen.h
@@ -24,6 +24,9 @@
 #define  MCAX_MISC2_OFFSET	0xb
 #define  MCAX_MISC3_OFFSET	0xc
 #define  MCAX_MISC4_OFFSET	0xd
+#define  MCAX_SYND1_OFFSET	0xe
+#define  MCAX_SYND2_OFFSET	0xf
+
 #define MCAX_MSR(bank, offset)	(MCAX_MSR_BASE + (bank) * MCAX_BANK_SIZE + (offset))
 #define MCAX_CTL_MSR(bank)	MCAX_MSR(bank, MCAX_CTL_OFFSET)
 #define MCAX_STATUS_MSR(bank)	MCAX_MSR(bank, MCAX_STATUS_OFFSET)
@@ -38,6 +41,8 @@
 #define MCAX_MISC2_MSR(bank)	MCAX_MSR(bank, MCAX_MISC2_OFFSET)
 #define MCAX_MISC3_MSR(bank)	MCAX_MSR(bank, MCAX_MISC3_OFFSET)
 #define MCAX_MISC4_MSR(bank)	MCAX_MSR(bank, MCAX_MISC4_OFFSET)
+#define MCAX_SYND1_MSR(bank)	MCAX_MSR(bank, MCAX_SYND1_OFFSET)
+#define MCAX_SYND2_MSR(bank)	MCAX_MSR(bank, MCAX_SYND2_OFFSET)
 
 /*
  * The MCA CTL_MASK moved to a new location in the fam 17h+ CPUs and accessing the legacy

From e705c3900967713cb315d720056506028bb1542d Mon Sep 17 00:00:00 2001
From: Yidi Lin <yidilin@google.com>
Date: Thu, 8 Jan 2026 22:23:24 +0800
Subject: [PATCH 2999/3886] libpayload/arch/arm64/mmu: Add CB_MEM_TAG to
 usedmem_ranges

CB_MEM_TAG is considered as an reserved memory. But we want to mange
this region in the payload and release this region when MTE is inactive.
Add CB_MEM_TAG memory range to usedmem_ranges to get a page table
mapping and mark it as used.

BUG=b:438666196,b:474306129
TEST=Check the tag region is wiped out in DEV mode.

Change-Id: I498407cbd44b1cc70ef769a63b8e40665ea67b28
Signed-off-by: Yidi Lin <yidilin@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90702
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 payloads/libpayload/arch/arm64/mmu.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/payloads/libpayload/arch/arm64/mmu.c b/payloads/libpayload/arch/arm64/mmu.c
index e99fa37c5d..0b7d206a58 100644
--- a/payloads/libpayload/arch/arm64/mmu.c
+++ b/payloads/libpayload/arch/arm64/mmu.c
@@ -611,6 +611,7 @@ static void mmu_extract_ranges(struct memrange *cb_ranges,
 
 		switch (cb_ranges[i].type) {
 		case CB_MEM_TABLE:
+		case CB_MEM_TAG:
 			/* Mark this memrange as used memory */
 			if (mmu_add_memrange(&usedmem_ranges, base, size,
 					     TYPE_NORMAL_MEM) == NULL)

From 292d7b9d3d4ccf852a9c20b8fafb5663bff7ff56 Mon Sep 17 00:00:00 2001
From: Yidi Lin <yidilin@google.com>
Date: Thu, 8 Jan 2026 15:08:32 +0000
Subject: [PATCH 3000/3886] Revert "soc/mediatek/mt8196: Call fsp_init via boot
 state"

This reverts commit 14a7a2315e722ef83b567d1918d7990eb83a451c.

Reason for revert: The change causes DUT failed to resume from S3.

BUG=b:474254985
TEST=Wake up DUT by power key.

Change-Id: I2f2291a12d9b440d000a28e38bb590bc77a02c8a
Signed-off-by: Yidi Lin <yidilin@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90703
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Chen-Tsung Hsieh <chentsung@google.com>
---
 src/soc/mediatek/mt8196/soc.c | 6 ++----
 1 file changed, 2 insertions(+), 4 deletions(-)

diff --git a/src/soc/mediatek/mt8196/soc.c b/src/soc/mediatek/mt8196/soc.c
index e988a76926..24077a0fbc 100644
--- a/src/soc/mediatek/mt8196/soc.c
+++ b/src/soc/mediatek/mt8196/soc.c
@@ -1,7 +1,6 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
 #include <bootmem.h>
-#include <bootstate.h>
 #include <device/device.h>
 #include <device/pci.h>
 #include <soc/booker.h>
@@ -57,7 +56,7 @@ static void mte_setup(void)
 	booker_mte_init(mte_start);
 }
 
-static void fsp_init(void *arg)
+static void fsp_init(void)
 {
 	uint32_t storage_type = mainboard_get_storage_type();
 
@@ -68,8 +67,6 @@ static void fsp_init(void *arg)
 	mtk_fsp_load_and_run();
 }
 
-BOOT_STATE_INIT_ENTRY(BS_DEV_INIT, BS_ON_ENTRY, fsp_init, NULL);
-
 static void soc_init(struct device *dev)
 {
 	mtk_mmu_disable_l2c_sram();
@@ -79,6 +76,7 @@ static void soc_init(struct device *dev)
 	if (spm_init())
 		printk(BIOS_ERR, "spm init failed, Suspend may not work\n");
 
+	fsp_init();
 	sspm_init();
 	gpueb_init();
 	mcupm_init();

From c421847fe2fef61586eb313206a4be0f2e491974 Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Mon, 29 Dec 2025 10:12:17 -0600
Subject: [PATCH 3001/3886] util/crossgcc: Fix GNAT detection for gnat-15

GCC's configure script requires gnat1, gnatbind, and gnatmake to be
available as unversioned executables in PATH when building with Ada
support. The previous detection logic only checked for gnat1 and used
a lenient searchtool check for gnatbind, which could incorrectly
enable Ada support when gnatmake was missing, causing configure to
fail with "GNAT is required to build ada".

In GNAT 15+, tools may only be available as versioned executables
(e.g., gnatbind-15, gnatmake-15), but GCC configure still requires
unversioned names. This change:

1. Adds explicit checks for gnatbind and gnatmake (unversioned)
2. Updates have_gnat() to require all three tools
3. Detects GNAT 15+ versioned tools and provides helpful error
   messages with instructions to create symlinks
4. Falls back to generic installation instructions if no GNAT tools
   are found

This prevents the configure error and provides clear guidance for
users with GNAT 15+ installations.

Change-Id: Idc16ec48612e88fc9bdd16b343ae267aa20490f3
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90635
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
---
 util/crossgcc/buildgcc | 87 ++++++++++++++++++++++++++++++++++--------
 1 file changed, 72 insertions(+), 15 deletions(-)

diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc
index cf4a8d6bce..be5493d16f 100755
--- a/util/crossgcc/buildgcc
+++ b/util/crossgcc/buildgcc
@@ -331,9 +331,38 @@ hostcc_has_gnat1() {
 	[ -x "$(${CC} -print-prog-name=gnat1)" ]
 }
 
+hostcc_has_gnatbind() {
+	# GCC configure requires unversioned gnatbind in PATH
+	# In GNAT 15+, tools may only be available as versioned (e.g., gnatbind-15)
+	# Check for unversioned first (required by configure)
+	if command -v gnatbind >/dev/null 2>&1; then
+		return 0
+	fi
+
+	# If only versioned tools exist, configure will fail
+	# So we return false to prevent Ada from being enabled
+	return 1
+}
+
+hostcc_has_gnatmake() {
+	# GCC configure requires unversioned gnatmake in PATH
+	# In GNAT 15+, tools may only be available as versioned (e.g., gnatmake-15)
+	# Check for unversioned first (required by configure)
+	if command -v gnatmake >/dev/null 2>&1; then
+		return 0
+	fi
+
+	# If only versioned tools exist, configure will fail
+	# So we return false to prevent Ada from being enabled
+	return 1
+}
+
 have_gnat() {
-	hostcc_has_gnat1 && \
-	searchtool gnatbind "Free Software Foundation" nofail > /dev/null
+	# Require all GNAT tools that configure needs
+	# Configure checks for gnatbind and gnatmake (unversioned names)
+	# Even though GNAT 15+ may only provide versioned tools or use gcc -b,
+	# the configure script still requires the unversioned names
+	hostcc_has_gnat1 && hostcc_has_gnatbind && hostcc_has_gnatmake
 }
 
 ada_requested() {
@@ -1235,23 +1264,51 @@ if [ -z "${LANGUAGES}" ]; then
 		printf "\nFound compatible Ada compiler, enabling Ada support by default.\n\n"
 		LANGUAGES="ada,${DEFAULT_LANGUAGES}"
 	else
+		# Check if versioned tools exist (GNAT 15+)
+		gcc_version=$(${CC} -dumpversion 2>/dev/null | cut -d. -f1)
+		gnatbind_ver=""
+		gnatmake_ver=""
+		gnatbind_path=""
+		gnatmake_path=""
+		if [ -n "$gcc_version" ]; then
+			gnatbind_ver="gnatbind-${gcc_version}"
+			gnatmake_ver="gnatmake-${gcc_version}"
+			gnatbind_path=$(command -v "$gnatbind_ver" 2>/dev/null)
+			gnatmake_path=$(command -v "$gnatmake_ver" 2>/dev/null)
+		fi
+
 		printf "\n${red}WARNING${NC}\n"
-		printf "No compatible Ada compiler (GNAT) found. You can continue without\n"
-		printf "Ada support, but this will limit the features of ${blue}coreboot${NC} (e.g.\n"
-		printf "native graphics initialization won't be available on most Intel\n"
-		printf "boards).\n\n"
+		if [ -n "$gnatbind_path" ] || [ -n "$gnatmake_path" ]; then
+			printf "GNAT tools are only available as versioned executables (e.g., %s, %s),\n" \
+				"${gnatbind_ver:-gnatbind-N}" "${gnatmake_ver:-gnatmake-N}"
+			printf "but GCC configure requires unversioned names (gnatbind, gnatmake).\n\n"
+			printf "To enable Ada support, create symlinks or install the unversioned tools:\n"
+			if [ -n "$gnatbind_path" ]; then
+				printf "    sudo ln -s %s /usr/local/bin/gnatbind\n" "$gnatbind_path"
+			fi
+			if [ -n "$gnatmake_path" ]; then
+				printf "    sudo ln -s %s /usr/local/bin/gnatmake\n" "$gnatmake_path"
+			fi
+			printf "\nAlternatively, disable Ada support by setting BUILD_LANGUAGES=c:\n"
+			printf "    make crossgcc-i386 BUILD_LANGUAGES=c\n\n"
+		else
+			printf "No compatible Ada compiler (GNAT) found. You can continue without\n"
+			printf "Ada support, but this will limit the features of ${blue}coreboot${NC} (e.g.\n"
+			printf "native graphics initialization won't be available on most Intel\n"
+			printf "boards).\n\n"
 
-		printf "Usually, you can install GNAT with your package management system\n"
-		printf "(the package is called \`gnat\` or \`gcc-ada\`). It has to match the\n"
-		printf "\`gcc\` package in version. If there are multiple versions of GCC in-\n"
-		printf "stalled, you can point this script to the matching version through\n"
-		printf "the \`CC\` and \`CXX\` environment variables.\n\n"
+			printf "Usually, you can install GNAT with your package management system\n"
+			printf "(the package is called \`gnat\` or \`gcc-ada\`). It has to match the\n"
+			printf "\`gcc\` package in version. If there are multiple versions of GCC in-\n"
+			printf "stalled, you can point this script to the matching version through\n"
+			printf "the \`CC\` and \`CXX\` environment variables.\n\n"
 
-		printf "e.g. on Ubuntu 14.04, if \`gcc\` is \`gcc-4.8\`:\n"
-		printf "    apt-get install gnat-4.8 && make crossgcc\n\n"
+			printf "e.g. on Ubuntu 14.04, if \`gcc\` is \`gcc-4.8\`:\n"
+			printf "    apt-get install gnat-4.8 && make crossgcc\n\n"
 
-		printf "on Ubuntu 16.04, if \`gcc\` is \`gcc-5\`:\n"
-		printf "    apt-get install gnat-5 && make crossgcc\n"
+			printf "on Ubuntu 16.04, if \`gcc\` is \`gcc-5\`:\n"
+			printf "    apt-get install gnat-5 && make crossgcc\n"
+		fi
 		timeout 30
 		LANGUAGES="${DEFAULT_LANGUAGES}"
 	fi

From 95ad0282740ea01983e623b4d2e4a882375e0942 Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Fri, 9 Jan 2026 09:59:31 -0600
Subject: [PATCH 3002/3886] drivers/smmstore: Use lookup_store() for
 memory-mapped reads

The smmstore_lookup_region() function was using
fmap_locate_area_as_rdev_rw() directly, which only provides
direct SPI access. This bypassed the optimized lookup_store()
function that uses incoherent_rdev to enable memory-mapped
reads via the read-only device while keeping direct SPI writes
via the read-write device.

Change smmstore_lookup_region() to call lookup_store() instead,
enabling memory-mapped reads for the public API and matching
the behavior of the internal implementation.

This improves read performance for EFI options and other
consumers of the SMMSTORE region device. It also fixes an issue
where direct SPI reads were crossing 4k page boundaries on older
platforms (Broadwell and earlier) causing them to fail and the
fallback option to be used, leading to a disconnect between the
user-selected option and device beahvior.

TEST=build/boot google/guado, verify all CFR options work properly
and no errors in cbmem.

Change-Id: I34947be932ede19a3fe896fe0da6373035fe6db7
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90717
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
---
 src/drivers/smmstore/store.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/drivers/smmstore/store.c b/src/drivers/smmstore/store.c
index 35887b3c7f..fa4c1e1b51 100644
--- a/src/drivers/smmstore/store.c
+++ b/src/drivers/smmstore/store.c
@@ -134,7 +134,7 @@ int smmstore_lookup_region(struct region_device *rstore)
 	if (!done) {
 		done = 1;
 
-		if (fmap_locate_area_as_rdev_rw(SMMSTORE_REGION, &rdev)) {
+		if (lookup_store(&rdev)) {
 			printk(BIOS_WARNING,
 			       "smm store: Unable to find SMM store FMAP region '%s'\n",
 				SMMSTORE_REGION);

From 8bc1372f72dc9ee83bf37e3a31377462ba8aa66d Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Tue, 6 Jan 2026 15:55:59 -0600
Subject: [PATCH 3003/3886] sb/intel/common/spi: Prevent transfers across 4KiB
 boundaries
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

The ICH SPI controller fails when a single transfer spans a 4KiB
boundary. Limit data_length in spi_ctrlr_xfer() to stay within the
current 4KiB page when with_address is true, avoiding the hardware
limitation at the platform driver level.

This fixes SPI read errors observed on SandyBridge, IvyBridge, Haswell,
and Broadwell when reading option variables stored in SMMSTORE. When
scanning the store to locate a given variable, reads would often cross
into the next 4KiB page (eg, reading 60 bytes from 0x313ff0).

TEST=build/boot stumpy, link, beltino, jecht boards, verify no SPI read
errors in cbmem, CFR options work properly.

Change-Id: I73d9c0acdbbb2faf5caff1f73049bff900774156
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90689
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/southbridge/intel/common/spi.c | 18 ++++++++++++++++--
 1 file changed, 16 insertions(+), 2 deletions(-)

diff --git a/src/southbridge/intel/common/spi.c b/src/southbridge/intel/common/spi.c
index 068062bae0..bcdcaa9158 100644
--- a/src/southbridge/intel/common/spi.c
+++ b/src/southbridge/intel/common/spi.c
@@ -619,14 +619,28 @@ static int spi_ctrlr_xfer(const struct spi_slave *slave, const void *dout,
 	 */
 	while (trans.bytesout || trans.bytesin) {
 		uint32_t data_length;
+		uint32_t max_length;
 
 		/* SPI addresses are 24 bit only */
 		writel_(trans.offset & 0x00FFFFFF, cntlr.addr);
 
 		if (trans.bytesout)
-			data_length = MIN(trans.bytesout, cntlr.databytes);
+			max_length = MIN(trans.bytesout, cntlr.databytes);
 		else
-			data_length = MIN(trans.bytesin, cntlr.databytes);
+			max_length = MIN(trans.bytesin, cntlr.databytes);
+
+		/*
+		 * Avoid transfers that cross 4KiB boundaries. The ICH SPI controller
+		 * has been observed to fail on some platforms when a single transfer
+		 * spans a 4KiB boundary (e.g., offset 0x...3ff0, len 0x3c crosses 0x...4000).
+		 */
+		if (with_address) {
+			uint32_t off_in_4k = trans.offset & 0xfff;
+			uint32_t max_to_boundary = 0x1000 - off_in_4k;
+			data_length = MIN(max_length, max_to_boundary);
+		} else {
+			data_length = max_length;
+		}
 
 		/* Program data into FDATA0 to N */
 		if (trans.bytesout) {

From a3a556f05d3005b73871b196f6cb9c837d43095b Mon Sep 17 00:00:00 2001
From: Luca Lai <luca.lai@lcfc.corp-partner.google.com>
Date: Fri, 5 Dec 2025 10:05:37 +0800
Subject: [PATCH 3004/3886] mb/google/fatcat/var/ruby: Add wifi SAR table

Based on the WiFi firmware configuration to add function for
getting WiFi SAR cbfs filename.

BUG=b:460231264
TEST=Build and check the system could boot to OS, and check the SAR table could work fine.

Change-Id: Ieec65debdc9f506e779352fcf8e54daa9296c0f7
Signed-off-by: Luca Lai <luca.lai@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90376
Reviewed-by: Derek Huang <derekhuang@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: YH Lin <yueherngl@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/google/fatcat/variants/ruby/Makefile.mk |  3 ++-
 .../google/fatcat/variants/ruby/overridetree.cb       |  4 ++++
 src/mainboard/google/fatcat/variants/ruby/variant.c   | 11 +++++++++++
 3 files changed, 17 insertions(+), 1 deletion(-)
 create mode 100644 src/mainboard/google/fatcat/variants/ruby/variant.c

diff --git a/src/mainboard/google/fatcat/variants/ruby/Makefile.mk b/src/mainboard/google/fatcat/variants/ruby/Makefile.mk
index 6c0a1ae6fb..36616963a3 100644
--- a/src/mainboard/google/fatcat/variants/ruby/Makefile.mk
+++ b/src/mainboard/google/fatcat/variants/ruby/Makefile.mk
@@ -1,8 +1,9 @@
-## SPDX-License-Identifier: GPL-2.0-only
+/* SPDX-License-Identifier: GPL-2.0-only */
 
 bootblock-y += gpio.c
 romstage-y += gpio.c
 romstage-y += memory.c
 romstage-$(CONFIG_FW_CONFIG) += fw_config.c
 ramstage-y += gpio.c
+ramstage-$(CONFIG_FW_CONFIG) += variant.c
 ramstage-$(CONFIG_FW_CONFIG) += fw_config.c
diff --git a/src/mainboard/google/fatcat/variants/ruby/overridetree.cb b/src/mainboard/google/fatcat/variants/ruby/overridetree.cb
index c85b2b13c5..e643ee9fae 100644
--- a/src/mainboard/google/fatcat/variants/ruby/overridetree.cb
+++ b/src/mainboard/google/fatcat/variants/ruby/overridetree.cb
@@ -39,6 +39,10 @@ fw_config
 		option KB_BACKLIGHT_ABSENT	0
 		option KB_BACKLIGHT_PRESENT	1
 	end
+	field AP_OEM_3BIT_FIELD0 56 58
+		option WIFI_SAR_ID0     0
+		option WIFI_SAR_ID1     1
+	end
 end
 
 chip soc/intel/pantherlake
diff --git a/src/mainboard/google/fatcat/variants/ruby/variant.c b/src/mainboard/google/fatcat/variants/ruby/variant.c
new file mode 100644
index 0000000000..8fdfd4b812
--- /dev/null
+++ b/src/mainboard/google/fatcat/variants/ruby/variant.c
@@ -0,0 +1,11 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <baseboard/variants.h>
+#include <chip.h>
+#include <sar.h>
+#include <fw_config.h>
+
+const char *get_wifi_sar_cbfs_filename(void)
+{
+	return get_wifi_sar_fw_config_filename(FW_CONFIG_FIELD(AP_OEM_3BIT_FIELD0));
+}

From a5c0307e9c8aeb613028c0790c4c10aa8e48fb4c Mon Sep 17 00:00:00 2001
From: Subrata Banik <subratabanik@google.com>
Date: Fri, 9 Jan 2026 14:35:42 +0530
Subject: [PATCH 3005/3886] commonlib/device_tree: Add
 dt_add_reserved_memory_region helper

Introduce a centralized helper function, dt_add_reserved_memory_region,
to simplify the creation of sub-nodes under /reserved-memory.

Currently, various features (such as pKVM, ramoops, and platform-
specific firmware reservations) manually handle the creation of
reserved memory nodes. This involves repetitive logic for:
 - Navigating or creating the /reserved-memory parent path.
 - Calculating cell sizes for 'reg' properties.
 - Manually adding 'no-map' or 'compatible' properties.

This helper abstracts those steps into a single call, reducing
boilerplate and the risk of cell-size mismatches across the codebase.

The function handles:
 - Node creation if the path doesn't exist.
 - Optional 'compatible' string assignment.
 - Automatic 'reg' property generation using appropriate address/size
   cells.
 - Optional 'no-map' property assignment via a boolean flag.

Change-Id: Ie58f5fdcfd1863b41c177b63ed9fc25d6d220e3a
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90713
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
---
 src/commonlib/device_tree.c                   | 29 +++++++++++++++++++
 src/commonlib/include/commonlib/device_tree.h | 15 ++++++++++
 2 files changed, 44 insertions(+)

diff --git a/src/commonlib/device_tree.c b/src/commonlib/device_tree.c
index b51f9fc31d..7d5161db23 100644
--- a/src/commonlib/device_tree.c
+++ b/src/commonlib/device_tree.c
@@ -2166,3 +2166,32 @@ bool dt_is_overlay(struct device_tree *tree)
 
 	return false;
 }
+
+struct device_tree_node *dt_add_reserved_memory_region(struct device_tree *tree,
+		      const char *name, const char *compatible, uint64_t addr, uint64_t size,
+		      bool nomap)
+{
+	uint32_t addr_cells, size_cells;
+	const char *path[] = { "reserved-memory", name, NULL };
+
+	/* Find or create the node. Using 1 for the 'create' argument. */
+	struct device_tree_node *node = dt_find_node(tree->root, path,
+						     &addr_cells, &size_cells, 1);
+	if (!node) {
+		printk(BIOS_ERR, "Failed to create reserved-memory node: %s\n", name);
+		return NULL;
+	}
+
+	/* Add the compatible string if provided */
+	if (compatible)
+		dt_add_string_prop(node, "compatible", compatible);
+
+	/* Always add the reg property */
+	dt_add_reg_prop(node, &addr, &size, 1, addr_cells, size_cells);
+
+	/* Add no-map if requested */
+	if (nomap)
+		dt_add_bin_prop(node, "no-map", NULL, 0);
+
+	return node;
+}
diff --git a/src/commonlib/include/commonlib/device_tree.h b/src/commonlib/include/commonlib/device_tree.h
index b6004fe8c4..ec4b4ffd29 100644
--- a/src/commonlib/include/commonlib/device_tree.h
+++ b/src/commonlib/include/commonlib/device_tree.h
@@ -237,4 +237,19 @@ struct device_tree_node *dt_init_reserved_memory_node(struct device_tree *tree);
 /* Check whether a devicetree is an overlay device tree */
 bool dt_is_overlay(struct device_tree *tree);
 
+/*
+ * dt_add_reserved_memory_region - Helper to add a node under `/reserved-memory`
+ * @tree: The device tree structure
+ * @name: Name of the child node (e.g., "ramoops", "pkvm-drng-seed")
+ * @compatible: Compatible string (optional, pass NULL if not needed)
+ * @addr: Physical start address
+ * @size: Size of the region
+ * @nomap: Boolean, if true adds the "no-map" property
+ *
+ * Returns the created node on success, NULL on failure.
+ */
+struct device_tree_node *dt_add_reserved_memory_region(struct device_tree *tree,
+		      const char *name, const char *compatible, uint64_t addr, uint64_t size,
+		      bool nomap);
+
 #endif /* __COMMONLIB_DEVICE_TREE_H__ */

From 9f4132712f2ab22011837a4cc5c4f26a4ba9ddb3 Mon Sep 17 00:00:00 2001
From: Jamie Chen <jamie.chen@intel.com>
Date: Tue, 6 Jan 2026 16:20:57 +0800
Subject: [PATCH 3006/3886] soc/intel/alderlake: add chipsetinit support
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Intel chipsetinit.bin is for PCH modphy initialize.
Add code to read chipsetinit.bin from CBFS and fill UPD params.

BUG=b:447290550
TEST=1. build coreboot
     2. check log to confirm load chipsetinit.bin successfully.

Change-Id: I65740f52c779daeea1a27a9e078336daee29cf3b
Signed-off-by: Jamie Chen <jamie.chen@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90687
Reviewed-by: Simon Yang <simon1.yang@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kao, Ben <ben.kao@intel.com>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
---
 src/soc/intel/alderlake/Kconfig      | 13 +++++++++++++
 src/soc/intel/alderlake/fsp_params.c | 19 +++++++++++++++++++
 2 files changed, 32 insertions(+)

diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig
index 97c2ecca70..34c9baf544 100644
--- a/src/soc/intel/alderlake/Kconfig
+++ b/src/soc/intel/alderlake/Kconfig
@@ -396,6 +396,19 @@ config CONSOLE_CBMEM_BUFFER_SIZE
 	default 0x100000 if BUILDING_WITH_DEBUG_FSP
 	default 0x40000
 
+config CHIPSETINIT_CBFS_FILE
+	string
+	depends on HAVE_CHIPSETINIT_BINARY
+	default "chipsetinit.bin"
+	help
+	  Name of the Chipset Initialization binary on the CBFS
+
+config HAVE_CHIPSETINIT_BINARY
+	bool
+	default n
+	help
+	  Select this option if you want to load the Chipset Initialization binary
+
 config FSP_TYPE_IOT
 	bool
 	default n
diff --git a/src/soc/intel/alderlake/fsp_params.c b/src/soc/intel/alderlake/fsp_params.c
index bd6f1d548a..396ea53c5a 100644
--- a/src/soc/intel/alderlake/fsp_params.c
+++ b/src/soc/intel/alderlake/fsp_params.c
@@ -664,6 +664,22 @@ static void fill_fsps_tcss_params(FSP_S_CONFIG *s_cfg,
 	s_cfg->Usb4CmMode = CONFIG(SOFTWARE_CONNECTION_MANAGER);
 }
 
+#if CONFIG(HAVE_CHIPSETINIT_BINARY)
+static void fill_fsps_chipsetinit_params(FSP_S_CONFIG *s_cfg,
+		const struct soc_intel_alderlake_config *config)
+{
+	void *data;
+	size_t size;
+
+	data = cbfs_map(CONFIG_CHIPSETINIT_CBFS_FILE, &size);
+	if (!data || size == 0)
+		return;
+
+	s_cfg->ChipsetInitBinPtr = (uint32_t)(uintptr_t)data;
+	s_cfg->ChipsetInitBinLen = (uint32_t)size;
+}
+#endif
+
 static void fill_fsps_chipset_lockdown_params(FSP_S_CONFIG *s_cfg,
 		const struct soc_intel_alderlake_config *config)
 {
@@ -1284,6 +1300,9 @@ static void soc_silicon_init_params(FSP_S_CONFIG *s_cfg,
 		fill_fsps_cpu_params,
 		fill_fsps_igd_params,
 		fill_fsps_tcss_params,
+#if CONFIG(HAVE_CHIPSETINIT_BINARY)
+		fill_fsps_chipsetinit_params,
+#endif
 		fill_fsps_chipset_lockdown_params,
 		fill_fsps_xhci_params,
 		fill_fsps_xdci_params,

From 3c3fbbaabf68781ef6422b846928601f07580aee Mon Sep 17 00:00:00 2001
From: Maximilian Brune <maximilian.brune@9elements.com>
Date: Mon, 29 Dec 2025 22:10:13 +0100
Subject: [PATCH 3007/3886] arch/x86/acpi_bert_storage.c: Remove unused
 variable

Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: I7fb8486f265be071fd59267ce120256c183d8dd6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90693
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
---
 src/arch/x86/acpi_bert_storage.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/arch/x86/acpi_bert_storage.c b/src/arch/x86/acpi_bert_storage.c
index 321f66ac54..902ddb7da5 100644
--- a/src/arch/x86/acpi_bert_storage.c
+++ b/src/arch/x86/acpi_bert_storage.c
@@ -513,10 +513,10 @@ acpi_generic_error_status_t *bert_new_event(guid_t *guid)
 {
 	size_t size;
 	acpi_generic_error_status_t *status;
-	acpi_hest_generic_data_v300_t *entry, *r;
+	acpi_hest_generic_data_v300_t *r;
 
 	size = sizeof(*status);
-	size += sizeof(*entry);
+	size += sizeof(*r);
 	size += sizeof_error_section(guid);
 
 	if (size > bert_storage_remaining()) {

From f00a2ff7b88eacc86b1c0015e806cb846887daa8 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Micha=C5=82=20=C5=BBygowski?= <michal.zygowski@3mdeb.com>
Date: Mon, 6 Oct 2025 10:45:59 +0200
Subject: [PATCH 3008/3886] arch/x86/ioapic.c: Support 8-bit IOAPIC IDs
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

AMD systems support 8-bit IOAPIC IDs. Some silicon initialization code
modules, like OpenSIL, may allocate an 8-bit ID by default. To respect
that configuration or set ID properly in coreboot, whole 8-bit ID field
has to be cleared and set.

Add new IOAPIC_8BIT_ID Kconfig option to allow setting 8-bit long IOAPIC
IDs.

TEST=Set IOAPIC IDs starting with 240 on Gigabyte MZ33-AR1.

Change-Id: Ie85b2272b0bc64a95d76c5677816941f1334901d
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89476
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
---
 src/Kconfig           |  7 +++++++
 src/arch/x86/ioapic.c | 12 ++++++++++--
 2 files changed, 17 insertions(+), 2 deletions(-)

diff --git a/src/Kconfig b/src/Kconfig
index 6c59e4fa5b..ec7dde2e53 100644
--- a/src/Kconfig
+++ b/src/Kconfig
@@ -919,6 +919,13 @@ config IOAPIC
 	default y if SMP
 	default n
 
+config IOAPIC_8BIT_ID
+	bool
+	default n
+	depends on IOAPIC
+	help
+	  Select this option if the hardware support 8bit long IOAPIC IDs.
+
 config USE_WATCHDOG_ON_BOOT
 	bool
 	default n
diff --git a/src/arch/x86/ioapic.c b/src/arch/x86/ioapic.c
index 4cde7c7f51..792ba3e65e 100644
--- a/src/arch/x86/ioapic.c
+++ b/src/arch/x86/ioapic.c
@@ -129,13 +129,21 @@ static void route_i8259_irq0(uintptr_t ioapic_base)
 static void set_ioapic_id(uintptr_t ioapic_base, u8 ioapic_id)
 {
 	int i;
+	u32 reg;
 
 	printk(BIOS_DEBUG, "IOAPIC: Initializing IOAPIC at %" PRIxPTR "\n",
 	       ioapic_base);
 	printk(BIOS_DEBUG, "IOAPIC: ID = 0x%02x\n", ioapic_id);
 
-	io_apic_write(ioapic_base, 0x00,
-		      (io_apic_read(ioapic_base, 0x00) & 0xf0ffffff) | (ioapic_id << 24));
+	reg = io_apic_read(ioapic_base, 0x00);
+
+	if (CONFIG(IOAPIC_8BIT_ID))
+		reg &= 0x00ffffff;
+	else
+		reg &= 0xf0ffffff;
+
+	reg |= (ioapic_id << 24);
+	io_apic_write(ioapic_base, 0x00, reg);
 
 	printk(BIOS_SPEW, "IOAPIC: Dumping registers\n");
 	for (i = 0; i < 3; i++)

From 5f86aba4b3795d632a3da9769eaa24a4ea0fd039 Mon Sep 17 00:00:00 2001
From: Wonkyu Kim <wonkyu.kim@intel.com>
Date: Mon, 29 Dec 2025 13:35:33 -0800
Subject: [PATCH 3009/3886] soc/intel/common: Enable high address support for
 MCHBAR in ACPI
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Increased MHBR field width in ACPI northbridge.asl from 17 to 27 bits,
allowing MCHBAR to be set above 4GB (up to 42 bits).

Reference: Section 10.3 in 850519
BUG=none
TEST=boot to OS with ACPI debug enabled and check GMHB log

Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com>
Change-Id: I885ff64598367ddadcec05926af3556024b61250
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90729
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
---
 src/soc/intel/common/block/acpi/acpi/northbridge.asl | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/src/soc/intel/common/block/acpi/acpi/northbridge.asl b/src/soc/intel/common/block/acpi/acpi/northbridge.asl
index 3b2fb85933..90c90027d0 100644
--- a/src/soc/intel/common/block/acpi/acpi/northbridge.asl
+++ b/src/soc/intel/common/block/acpi/acpi/northbridge.asl
@@ -24,7 +24,7 @@ Device (MCHC)
 		Offset(0x48),	/* MCHBAR (0:0:0:48) */
 		MHEN, 1,	/* Enable */
 		, 14,
-		MHBR, 17,	/* MCHBAR [31:15] */
+		MHBR, 27,	/* MCHBAR [41:15] */
 
 		Offset(0x60),	/* PCIEXBAR (0:0:0:60) */
 		PXEN, 1,	/* Enable */
@@ -246,6 +246,7 @@ Method (_CRS, 0, Serialized)
 Method (GMHB, 0, Serialized)
 {
 	Local0 = \_SB.PCI0.MCHC.MHBR << 15
+	Printf ("GMHB: %o", ToHexString(Local0))
 	Return (Local0)
 }
 

From 1d2b399fd76b0804d07e22da047eaaa9e5e692e2 Mon Sep 17 00:00:00 2001
From: Yidi Lin <yidilin@google.com>
Date: Mon, 12 Jan 2026 15:01:12 +0800
Subject: [PATCH 3010/3886] lib: Rename `fill_lb_framebuffer` to
 `get_lb_framebuffer`

Rename `fill_lb_framebuffer` to `get_lb_framebuffer` to better
reflect that it returns framebuffer information.

The new `get_lb_framebuffer` returns a constant pointer to the
framebuffer structure instead of filling a provided structure.
This simplifies the API and avoids an unnecessary memory copy.

The file `edid_fill_fb.c` is renamed to `framebuffer_info.c`
to better match the function it now contains.

Call sites in `coreboot_table.c` and `render_bmp.c` are
updated to use the new API.

TEST=emerge-tanjiro coreboot; check the FW logo is correctly drawn.
BUG=b:319511268

Change-Id: I8d7b20a0524b6bc9fff9e6461fa0c253345df790
Signed-off-by: Yidi Lin <yidilin@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90725
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Chen-Tsung Hsieh <chentsung@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
---
 src/include/boot/coreboot_tables.h             |  6 +++---
 src/lib/Makefile.mk                            |  2 +-
 src/lib/coreboot_table.c                       |  6 +++---
 src/lib/{edid_fill_fb.c => framebuffer_info.c} |  7 +++----
 src/lib/render_bmp.c                           | 14 ++++++--------
 5 files changed, 16 insertions(+), 19 deletions(-)
 rename src/lib/{edid_fill_fb.c => framebuffer_info.c} (97%)

diff --git a/src/include/boot/coreboot_tables.h b/src/include/boot/coreboot_tables.h
index be737b0bb9..3a5e31651c 100644
--- a/src/include/boot/coreboot_tables.h
+++ b/src/include/boot/coreboot_tables.h
@@ -33,9 +33,9 @@ void lb_efi_fw_info(struct lb_header *header);
 /* Adds LB_TAG_CAPSULE table entries. */
 void lb_efi_capsules(struct lb_header *header);
 
-/* Define this function to fill in the frame buffer returning 0 on success and
-   < 0 on error. */
-int fill_lb_framebuffer(struct lb_framebuffer *framebuffer);
+/* Define this function to get the frame buffer returning lb_framebuffer object
+   on success and NULL on error. */
+const struct lb_framebuffer *get_lb_framebuffer(void);
 
 /* Allow arch to add records. */
 void lb_arch_add_records(struct lb_header *header);
diff --git a/src/lib/Makefile.mk b/src/lib/Makefile.mk
index 9deefaf95b..d7cf8455b1 100644
--- a/src/lib/Makefile.mk
+++ b/src/lib/Makefile.mk
@@ -154,8 +154,8 @@ ramstage-$(CONFIG_BOOTSPLASH) += jpeg.c
 ramstage-$(CONFIG_COLLECT_TIMESTAMPS) += timestamp.c
 ramstage-$(CONFIG_COVERAGE) += libgcov.c
 ramstage-y += dp_aux.c
+ramstage-y += framebuffer_info.c
 ramstage-y += edid.c
-ramstage-y += edid_fill_fb.c
 ramstage-y += memrange.c
 ramstage-$(CONFIG_GENERIC_GPIO_LIB) += gpio.c
 ramstage-$(CONFIG_GENERIC_UDELAY) += timer.c
diff --git a/src/lib/coreboot_table.c b/src/lib/coreboot_table.c
index 85c5675507..6218784adc 100644
--- a/src/lib/coreboot_table.c
+++ b/src/lib/coreboot_table.c
@@ -142,13 +142,13 @@ static void lb_pcie(struct lb_header *header)
 static void lb_framebuffer(struct lb_header *header)
 {
 	struct lb_framebuffer *framebuffer;
-	struct lb_framebuffer fb = {0};
+	const struct lb_framebuffer *fb;
 
-	if (!CONFIG(LINEAR_FRAMEBUFFER) || fill_lb_framebuffer(&fb))
+	if (!CONFIG(LINEAR_FRAMEBUFFER) || !(fb = get_lb_framebuffer()))
 		return;
 
 	framebuffer = (struct lb_framebuffer *)lb_new_record(header);
-	memcpy(framebuffer, &fb, sizeof(*framebuffer));
+	memcpy(framebuffer, fb, sizeof(*framebuffer));
 	framebuffer->tag = LB_TAG_FRAMEBUFFER;
 	framebuffer->size = sizeof(*framebuffer);
 
diff --git a/src/lib/edid_fill_fb.c b/src/lib/framebuffer_info.c
similarity index 97%
rename from src/lib/edid_fill_fb.c
rename to src/lib/framebuffer_info.c
index a9ff31f5ca..f706377caa 100644
--- a/src/lib/edid_fill_fb.c
+++ b/src/lib/framebuffer_info.c
@@ -181,14 +181,13 @@ struct fb_info *fb_new_framebuffer_info_from_edid(const struct edid *edid,
 		edid->bytes_per_line, edid->framebuffer_bits_per_pixel);
 }
 
-int fill_lb_framebuffer(struct lb_framebuffer *framebuffer)
+const struct lb_framebuffer *get_lb_framebuffer(void)
 {
 	struct fb_info *i;
 
 	list_for_each(i, list, node) {
 		//TODO: Add support for advertising all framebuffers in this list
-		*framebuffer = i->fb;
-		return 0;
+		return &i->fb;
 	}
-	return -1;
+	return NULL;
 }
diff --git a/src/lib/render_bmp.c b/src/lib/render_bmp.c
index 3a7e245eca..b91015bf89 100644
--- a/src/lib/render_bmp.c
+++ b/src/lib/render_bmp.c
@@ -689,16 +689,14 @@ void render_logo_to_framebuffer(struct logo_config *config)
 
 	if (config->framebuffer_base == 0) {
 		/* Try to load from already populated framebuffer information */
-		struct lb_framebuffer framebuffer;
-		memset(&framebuffer, 0, sizeof(struct lb_framebuffer));
-		fill_lb_framebuffer(&framebuffer);
+		const struct lb_framebuffer *fb = get_lb_framebuffer();
 		/* Exit if framebuffer is still not available */
-		if (framebuffer.physical_address == 0)
+		if (!fb)
 			return;
-		config->framebuffer_base = framebuffer.physical_address;
-		config->horizontal_resolution = framebuffer.x_resolution;
-		config->vertical_resolution = framebuffer.y_resolution;
-		config->bytes_per_scanline = framebuffer.bytes_per_line;
+		config->framebuffer_base = fb->physical_address;
+		config->horizontal_resolution = fb->x_resolution;
+		config->vertical_resolution = fb->y_resolution;
+		config->bytes_per_scanline = fb->bytes_per_line;
 	}
 
 	/*

From b4fbc59c6f85b9e9899b2312efe73fdfee86ebbf Mon Sep 17 00:00:00 2001
From: Yu-Ping Wu <yupingso@chromium.org>
Date: Tue, 13 Jan 2026 11:42:18 +0800
Subject: [PATCH 3011/3886] treewide: Move mipi_panel_parse_commands() to
 commonlib

Move the MIPI panel init command parsing function
mipi_panel_parse_init_commands() and related macros and structs from
drivers/mipi/ to commonlib/mipi/, so that the function can be shared
with payloads.

In a follow-up patch, a 'poweroff' field will be added to the
panel_serializable_data struct and then passed to payloads, so that
payloads can utilize mipi_panel_parse_init_commands() to run the panel
poweroff commands.

BUG=b:474187570
TEST=emerge-jedi coreboot libpayload
BRANCH=skywalker

Change-Id: I19011669f03d060e9f030b673687cbe5965d7e2f
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90736
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Chen-Tsung Hsieh <chentsung@google.com>
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
---
 src/commonlib/Makefile.mk                     |  1 +
 src/commonlib/include/commonlib/mipi/cmd.h    | 55 +++++++++++++++++++
 .../include/commonlib}/mipi/dsi.h             |  6 +-
 src/commonlib/mipi/Makefile.mk                |  3 +
 .../mipi/panel.c => commonlib/mipi/cmd.c}     |  6 +-
 src/drivers/mipi/Makefile.mk                  |  2 -
 src/include/mipi/panel.h                      | 47 +---------------
 .../mediatek/common/include/soc/dsi_common.h  |  2 +-
 .../tegra210/include/soc/mipi_display.h       |  2 +-
 src/soc/qualcomm/sc7180/display/dsi.c         |  1 -
 src/soc/rockchip/rk3399/include/soc/mipi.h    |  2 +-
 11 files changed, 69 insertions(+), 58 deletions(-)
 create mode 100644 src/commonlib/include/commonlib/mipi/cmd.h
 rename src/{include => commonlib/include/commonlib}/mipi/dsi.h (97%)
 create mode 100644 src/commonlib/mipi/Makefile.mk
 rename src/{drivers/mipi/panel.c => commonlib/mipi/cmd.c} (94%)

diff --git a/src/commonlib/Makefile.mk b/src/commonlib/Makefile.mk
index b4bc1b8fae..f71fff4892 100644
--- a/src/commonlib/Makefile.mk
+++ b/src/commonlib/Makefile.mk
@@ -1,5 +1,6 @@
 ## SPDX-License-Identifier: GPL-2.0-only
 
+subdirs-y += mipi
 subdirs-y += storage
 subdirs-y += bsd/zstd
 
diff --git a/src/commonlib/include/commonlib/mipi/cmd.h b/src/commonlib/include/commonlib/mipi/cmd.h
new file mode 100644
index 0000000000..ebbc36ba47
--- /dev/null
+++ b/src/commonlib/include/commonlib/mipi/cmd.h
@@ -0,0 +1,55 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef __COMMONLIB_MIPI_CMD_H__
+#define __COMMONLIB_MIPI_CMD_H__
+
+#include <commonlib/bsd/cb_err.h>
+#include <commonlib/mipi/dsi.h>
+#include <stdint.h>
+
+/* Definitions for cmd in panel_init_command */
+enum panel_init_cmd {
+	PANEL_CMD_END = 0,
+	PANEL_CMD_DELAY = 1,
+	PANEL_CMD_GENERIC = 2,
+	PANEL_CMD_DCS = 3,
+};
+
+struct panel_init_command {
+	u8 cmd;
+	u8 len;
+	u8 data[];
+};
+
+#define PANEL_DELAY(delay) \
+	PANEL_CMD_DELAY, \
+	delay
+
+#define PANEL_GENERIC(...) \
+	PANEL_CMD_GENERIC, \
+	sizeof((u8[]){__VA_ARGS__}), \
+	__VA_ARGS__
+
+#define PANEL_DCS(...) \
+	PANEL_CMD_DCS, \
+	sizeof((u8[]){__VA_ARGS__}), \
+	__VA_ARGS__
+
+#define PANEL_END \
+	PANEL_CMD_END
+
+/*
+ * Callback function type for mipi_panel_parse_init_commands().
+ * @param type		MIPI DSI transaction type.
+ * @param data		panel_init_command data.
+ * @param len		panel_init_command len.
+ * @param user_data	Arbitrary user data passed from mipi_panel_parse_init_commands().
+ */
+typedef enum cb_err (*mipi_cmd_func_t)(enum mipi_dsi_transaction type, const u8 *data, u8 len,
+				       void *user_data);
+
+/* Parse a command array and call cmd_func() for each entry. Delays get handled internally. */
+enum cb_err mipi_panel_parse_init_commands(const void *buf, mipi_cmd_func_t cmd_func,
+					   void *user_data);
+
+#endif /* __COMMONLIB_MIPI_CMD_H__ */
diff --git a/src/include/mipi/dsi.h b/src/commonlib/include/commonlib/mipi/dsi.h
similarity index 97%
rename from src/include/mipi/dsi.h
rename to src/commonlib/include/commonlib/mipi/dsi.h
index 9f11490f69..b55fd9dc70 100644
--- a/src/include/mipi/dsi.h
+++ b/src/commonlib/include/commonlib/mipi/dsi.h
@@ -1,7 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
-#ifndef __MIPI_DSI_H__
-#define __MIPI_DSI_H__
+#ifndef __COMMONLIB_MIPI_DSI_H__
+#define __COMMONLIB_MIPI_DSI_H__
 
 /* MIPI DSI Processor-to-Peripheral transaction types */
 enum mipi_dsi_transaction {
@@ -109,4 +109,4 @@ enum {
 	MIPI_DCS_READ_DDB_CONTINUE	= 0xA8,
 };
 
-#endif /* __MIPI_DSI_H__ */
+#endif /* __COMMONLIB_MIPI_DSI_H__ */
diff --git a/src/commonlib/mipi/Makefile.mk b/src/commonlib/mipi/Makefile.mk
new file mode 100644
index 0000000000..e5df26b2c5
--- /dev/null
+++ b/src/commonlib/mipi/Makefile.mk
@@ -0,0 +1,3 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
+ramstage-y += cmd.c
diff --git a/src/drivers/mipi/panel.c b/src/commonlib/mipi/cmd.c
similarity index 94%
rename from src/drivers/mipi/panel.c
rename to src/commonlib/mipi/cmd.c
index 0182a8594a..be8c5e6412 100644
--- a/src/drivers/mipi/panel.c
+++ b/src/commonlib/mipi/cmd.c
@@ -1,9 +1,9 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
-#include <console/console.h>
+#include <commonlib/bsd/cb_err.h>
+#include <commonlib/bsd/stdlib.h>
+#include <commonlib/mipi/cmd.h>
 #include <delay.h>
-#include <mipi/panel.h>
-#include <types.h>
 
 enum cb_err mipi_panel_parse_init_commands(const void *buf, mipi_cmd_func_t cmd_func,
 					   void *user_data)
diff --git a/src/drivers/mipi/Makefile.mk b/src/drivers/mipi/Makefile.mk
index 92d5ebe987..e814414d82 100644
--- a/src/drivers/mipi/Makefile.mk
+++ b/src/drivers/mipi/Makefile.mk
@@ -1,7 +1,5 @@
 # SPDX-License-Identifier: GPL-2.0-only
 
-ramstage-y += panel.c
-
 panel-params-y :=
 
 panel-params-$(CONFIG_MIPI_PANEL_AUO_B101UAN08_3) += panel-AUO_B101UAN08_3
diff --git a/src/include/mipi/panel.h b/src/include/mipi/panel.h
index e2123a6e22..ae45684ecb 100644
--- a/src/include/mipi/panel.h
+++ b/src/include/mipi/panel.h
@@ -3,29 +3,15 @@
 #ifndef __MIPI_PANEL_H__
 #define __MIPI_PANEL_H__
 
+#include <commonlib/mipi/cmd.h>
 #include <edid.h>
-#include <mipi/dsi.h>
 #include <types.h>
 
-/* Definitions for cmd in panel_init_command */
-enum panel_init_cmd {
-	PANEL_CMD_END = 0,
-	PANEL_CMD_DELAY = 1,
-	PANEL_CMD_GENERIC = 2,
-	PANEL_CMD_DCS = 3,
-};
-
 /* Definitions for flags in panel_serializable_data */
 enum panel_flag {
 	PANEL_FLAG_CPHY = BIT(0),
 };
 
-struct panel_init_command {
-	u8 cmd;
-	u8 len;
-	u8 data[];
-};
-
 /* VESA Display Stream Compression DSC 1.2 constants */
 #define DSC_NUM_BUF_RANGES			15
 
@@ -215,35 +201,4 @@ struct panel_serializable_data {
 	u8 init[]; /* A packed array of panel_init_command */
 };
 
-/*
- * Callback function type for mipi_panel_parse_init_commands().
- * @param type		MIPI DSI transaction type.
- * @param data		panel_init_command data.
- * @param len		panel_init_command len.
- * @param user_data	Arbitrary user data passed from mipi_panel_parse_init_commands().
- */
-typedef enum cb_err (*mipi_cmd_func_t)(enum mipi_dsi_transaction type, const u8 *data, u8 len,
-				       void *user_data);
-
-/* Parse a command array and call cmd_func() for each entry. Delays get handled internally. */
-enum cb_err mipi_panel_parse_init_commands(const void *buf, mipi_cmd_func_t cmd_func,
-					   void *user_data);
-
-#define PANEL_DCS(...) \
-	PANEL_CMD_DCS, \
-	sizeof((u8[]){__VA_ARGS__}), \
-	__VA_ARGS__
-
-#define PANEL_GENERIC(...) \
-	PANEL_CMD_GENERIC, \
-	sizeof((u8[]){__VA_ARGS__}), \
-	__VA_ARGS__
-
-#define PANEL_DELAY(delay) \
-	PANEL_CMD_DELAY, \
-	delay
-
-#define PANEL_END \
-	PANEL_CMD_END
-
 #endif /* __MIPI_PANEL_H__ */
diff --git a/src/soc/mediatek/common/include/soc/dsi_common.h b/src/soc/mediatek/common/include/soc/dsi_common.h
index 626e8414b6..62bff790a9 100644
--- a/src/soc/mediatek/common/include/soc/dsi_common.h
+++ b/src/soc/mediatek/common/include/soc/dsi_common.h
@@ -4,8 +4,8 @@
 #define SOC_MEDIATEK_DSI_COMMON_H
 
 #include <commonlib/helpers.h>
+#include <commonlib/mipi/dsi.h>
 #include <edid.h>
-#include <mipi/dsi.h>
 #include <types.h>
 #include <soc/addressmap.h>
 #include <soc/display_dsi.h>
diff --git a/src/soc/nvidia/tegra210/include/soc/mipi_display.h b/src/soc/nvidia/tegra210/include/soc/mipi_display.h
index e5c7596b97..87591878c8 100644
--- a/src/soc/nvidia/tegra210/include/soc/mipi_display.h
+++ b/src/soc/nvidia/tegra210/include/soc/mipi_display.h
@@ -8,7 +8,7 @@
 #ifndef __SOC_MIPI_DISPLAY_H__
 #define __SOC_MIPI_DISPLAY_H__
 
-#include <mipi/dsi.h>
+#include <commonlib/mipi/dsi.h>
 
 /* MIPI DCS pixel formats */
 #define MIPI_DCS_PIXEL_FMT_24BIT	7
diff --git a/src/soc/qualcomm/sc7180/display/dsi.c b/src/soc/qualcomm/sc7180/display/dsi.c
index c1e75e1090..e5b09805c3 100644
--- a/src/soc/qualcomm/sc7180/display/dsi.c
+++ b/src/soc/qualcomm/sc7180/display/dsi.c
@@ -1,6 +1,5 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
-#include <mipi/dsi.h>
 #include <mipi/panel.h>
 #include <device/mmio.h>
 #include <console/console.h>
diff --git a/src/soc/rockchip/rk3399/include/soc/mipi.h b/src/soc/rockchip/rk3399/include/soc/mipi.h
index f5bd797850..839eb5185c 100644
--- a/src/soc/rockchip/rk3399/include/soc/mipi.h
+++ b/src/soc/rockchip/rk3399/include/soc/mipi.h
@@ -3,7 +3,7 @@
 #ifndef __RK_MIPI_H
 #define __RK_MIPI_H
 
-#include <mipi/dsi.h>
+#include <commonlib/mipi/dsi.h>
 #include <types.h>
 
 struct rk_mipi_regs {

From a6407000f1fefb064cf0953d80e256626aee7248 Mon Sep 17 00:00:00 2001
From: Yu-Ping Wu <yupingso@chromium.org>
Date: Tue, 13 Jan 2026 14:49:47 +0800
Subject: [PATCH 3012/3886] mipi/panel: Add 'poweroff' field to
 panel_serializable_data

Some payloads such as depthcharge need to run MIPI panel power-off
commands before booting to the kernel. Otherwise, the abnormal power-off
timing would prevent the pixel charge from being cleared before
power-off, leading to the risk of LCD overpotential hence resulting in
image stickiness or flicker upon restarting.

Therefore, add a 'poweroff' field to the panel_serializable_data struct,
which, in a follow-up patch, will be passed to payloads for running the
power-off commands. Each MIPI panel can define the power-off commands in
that field.

As both init and power-off commands are supported, remove "_init" from
related structs and enums.

BUG=b:474187570
TEST=emerge-jedi coreboot libpayload
BRANCH=skywalker

Change-Id: I1a7c0a14d5c197a0887a26269e4c36e498e8b7ae
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90737
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Chen-Tsung Hsieh <chentsung@google.com>
---
 src/commonlib/include/commonlib/mipi/cmd.h | 18 +++++++++---------
 src/commonlib/mipi/cmd.c                   | 18 +++++++++---------
 src/include/mipi/panel.h                   |  6 +++++-
 src/soc/mediatek/common/dsi_common.c       |  2 +-
 src/soc/qualcomm/sc7180/display/dsi.c      |  3 +--
 5 files changed, 25 insertions(+), 22 deletions(-)

diff --git a/src/commonlib/include/commonlib/mipi/cmd.h b/src/commonlib/include/commonlib/mipi/cmd.h
index ebbc36ba47..17e0aeda89 100644
--- a/src/commonlib/include/commonlib/mipi/cmd.h
+++ b/src/commonlib/include/commonlib/mipi/cmd.h
@@ -7,15 +7,15 @@
 #include <commonlib/mipi/dsi.h>
 #include <stdint.h>
 
-/* Definitions for cmd in panel_init_command */
-enum panel_init_cmd {
+/* Definitions for cmd in panel_command */
+enum panel_cmd {
 	PANEL_CMD_END = 0,
 	PANEL_CMD_DELAY = 1,
 	PANEL_CMD_GENERIC = 2,
 	PANEL_CMD_DCS = 3,
 };
 
-struct panel_init_command {
+struct panel_command {
 	u8 cmd;
 	u8 len;
 	u8 data[];
@@ -39,17 +39,17 @@ struct panel_init_command {
 	PANEL_CMD_END
 
 /*
- * Callback function type for mipi_panel_parse_init_commands().
+ * Callback function type for mipi_panel_parse_commands().
  * @param type		MIPI DSI transaction type.
- * @param data		panel_init_command data.
- * @param len		panel_init_command len.
- * @param user_data	Arbitrary user data passed from mipi_panel_parse_init_commands().
+ * @param data		panel_command data.
+ * @param len		panel_command len.
+ * @param user_data	Arbitrary user data passed from mipi_panel_parse_commands().
  */
 typedef enum cb_err (*mipi_cmd_func_t)(enum mipi_dsi_transaction type, const u8 *data, u8 len,
 				       void *user_data);
 
 /* Parse a command array and call cmd_func() for each entry. Delays get handled internally. */
-enum cb_err mipi_panel_parse_init_commands(const void *buf, mipi_cmd_func_t cmd_func,
-					   void *user_data);
+enum cb_err mipi_panel_parse_commands(const void *buf, mipi_cmd_func_t cmd_func,
+				      void *user_data);
 
 #endif /* __COMMONLIB_MIPI_CMD_H__ */
diff --git a/src/commonlib/mipi/cmd.c b/src/commonlib/mipi/cmd.c
index be8c5e6412..4e5a638d9b 100644
--- a/src/commonlib/mipi/cmd.c
+++ b/src/commonlib/mipi/cmd.c
@@ -5,26 +5,26 @@
 #include <commonlib/mipi/cmd.h>
 #include <delay.h>
 
-enum cb_err mipi_panel_parse_init_commands(const void *buf, mipi_cmd_func_t cmd_func,
-					   void *user_data)
+enum cb_err mipi_panel_parse_commands(const void *buf, mipi_cmd_func_t cmd_func,
+				      void *user_data)
 {
-	const struct panel_init_command *init = buf;
+	const struct panel_command *command = buf;
 	enum mipi_dsi_transaction type;
 
 	/*
 	 * The given commands should be in a buffer containing a packed array of
-	 * panel_init_command and each element may be in variable size so we have
+	 * panel_command and each element may be in variable size so we have
 	 * to parse and scan.
 	 */
 
-	for (; init->cmd != PANEL_CMD_END; init = (const void *)buf) {
+	for (; command->cmd != PANEL_CMD_END; command = (const void *)buf) {
 		/*
-		 * For some commands like DELAY, the init->len should not be
+		 * For some commands like DELAY, the command->len should not be
 		 * counted for buf.
 		 */
-		buf += sizeof(*init);
+		buf += sizeof(*command);
 
-		u32 cmd = init->cmd, len = init->len;
+		u32 cmd = command->cmd, len = command->len;
 
 		if (cmd == PANEL_CMD_DELAY) {
 			mdelay(len);
@@ -70,7 +70,7 @@ enum cb_err mipi_panel_parse_init_commands(const void *buf, mipi_cmd_func_t cmd_
 			return CB_ERR;
 		}
 
-		enum cb_err ret = cmd_func(type, init->data, len, user_data);
+		enum cb_err ret = cmd_func(type, command->data, len, user_data);
 		if (ret != CB_SUCCESS)
 			return ret;
 		buf += len;
diff --git a/src/include/mipi/panel.h b/src/include/mipi/panel.h
index ae45684ecb..432b43090b 100644
--- a/src/include/mipi/panel.h
+++ b/src/include/mipi/panel.h
@@ -189,6 +189,8 @@ struct dsc_config {
 	u8 dsc_version_major;
 };
 
+#define PANEL_POWEROFF_CMD_MAX_LEN 16
+
 /*
  * The data to be serialized and put into CBFS.
  * Note some fields, for example edid.mode.name, were actually pointers and
@@ -198,7 +200,9 @@ struct panel_serializable_data {
 	u32 flags; /* flags of panel_flag */
 	struct edid edid;  /* edid info of this panel */
 	struct dsc_config dsc_config; /* dsc config of this panel */
-	u8 init[]; /* A packed array of panel_init_command */
+	/* Packed arrays of panel_command */
+	u8 poweroff[PANEL_POWEROFF_CMD_MAX_LEN];
+	u8 init[];
 };
 
 #endif /* __MIPI_PANEL_H__ */
diff --git a/src/soc/mediatek/common/dsi_common.c b/src/soc/mediatek/common/dsi_common.c
index 3ff8c5b049..b2df010a48 100644
--- a/src/soc/mediatek/common/dsi_common.c
+++ b/src/soc/mediatek/common/dsi_common.c
@@ -494,7 +494,7 @@ int mtk_dsi_init(u32 mode_flags, u32 format, u32 lanes, const struct edid *edid,
 	}
 
 	if (init_commands)
-		mipi_panel_parse_init_commands(init_commands, mtk_dsi_cmdq, &mode_flags);
+		mipi_panel_parse_commands(init_commands, mtk_dsi_cmdq, &mode_flags);
 
 	for (unsigned int i = 0; i < num_dsi; i++)
 		mtk_dsi_set_mode(dsi_mipi_regs[i].dsi_reg, mode_flags);
diff --git a/src/soc/qualcomm/sc7180/display/dsi.c b/src/soc/qualcomm/sc7180/display/dsi.c
index e5b09805c3..ef219777b3 100644
--- a/src/soc/qualcomm/sc7180/display/dsi.c
+++ b/src/soc/qualcomm/sc7180/display/dsi.c
@@ -286,8 +286,7 @@ enum cb_err mdss_dsi_panel_initialize(const u8 *init_cmds)
 	/* Enable command mode before sending the commands */
 	write32(&dsi0->ctrl, ctrl_mode | 0x04);
 
-	enum cb_err ret = mipi_panel_parse_init_commands(init_cmds, mdss_dsi_send_init_cmd,
-							 NULL);
+	enum cb_err ret = mipi_panel_parse_commands(init_cmds, mdss_dsi_send_init_cmd, NULL);
 	write32(&dsi0->ctrl, ctrl_mode);
 	mdss_dsi_clear_intr();
 

From e01baafbe27692882b83a14b07b7b0f991f61a09 Mon Sep 17 00:00:00 2001
From: Maximilian Brune <maximilian.brune@9elements.com>
Date: Wed, 27 Aug 2025 21:29:25 +0200
Subject: [PATCH 3013/3886] include/cper.h: Add check information structures

It is needed in a later commit that is not upstream yet.

Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: I260dcf199178d28387e7af06c6fb0b03c97c4bb8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90692
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/include/cper.h | 47 +++++++++++++++++++++++++++++++++++++++++++++-
 1 file changed, 46 insertions(+), 1 deletion(-)

diff --git a/src/include/cper.h b/src/include/cper.h
index 4dec2a2247..1bddaa78ef 100644
--- a/src/include/cper.h
+++ b/src/include/cper.h
@@ -172,16 +172,61 @@ typedef struct cper_ia32x64_proc_error_section {
 					(I32X64SEC_VALID_CTXNUM_MAX \
 					<< I32X64SEC_VALID_CTXNUM_SH)
 
+#define I32X64_ERRTYPE_INTERNAL_UNCLASSIFIED  5
+
+struct cper_ia32x64_check_ms {
+	uint64_t validation_bits:16;
+	uint64_t err_type:3;
+	uint64_t proc_context_corrupt:1;
+	uint64_t uncorrected:1;
+	uint64_t precise_ip:1;
+	uint64_t restartable_ip:1;
+	uint64_t overflow:1;
+	uint64_t :40;
+};
+
+struct cper_ia32x64_check_tlb {
+	uint64_t validation_bits:16;
+	uint64_t transaction_type:2;
+	uint64_t operation:4;
+	uint64_t level:3;
+	uint64_t proc_context_corrupt:1;
+	uint64_t uncorrected:1;
+	uint64_t precise_ip:1;
+	uint64_t restartable_ip:1;
+	uint64_t overflow:1;
+	uint64_t :34;
+};
+
+struct cper_ia32x64_check_cache {
+	uint64_t validation_bits:16;
+	uint64_t transaction_type:2;
+	uint64_t operation:4;
+	uint64_t level:3;
+	uint64_t proc_context_corrupt:1;
+	uint64_t uncorrected:1;
+	uint64_t precise_ip:1;
+	uint64_t restartable_ip:1;
+	uint64_t overflow:1;
+	uint64_t :34;
+};
+
 /* IA32/X64 Processor Error Information Structure (Table N.8) */
 typedef struct cper_ia32x64_proc_error_info {
 	guid_t type; /* cache, tlb, bus, micro-architecture specific */
 	u64 validation;
-	u64 check_info;
+	union {
+		struct cper_ia32x64_check_ms    ms;
+		struct cper_ia32x64_check_tlb   tlb;
+		struct cper_ia32x64_check_cache cache;
+		uint64_t raw;
+	};
 	u64 target_id;
 	u64 requestor_id;
 	u64 responder_id;
 	u64 instruction_ip;
 } __packed cper_ia32x64_proc_error_info_t;
+_Static_assert(sizeof(struct cper_ia32x64_proc_error_info) == 64, "cper_ia32x64_proc_error_info size wrong");
 
 /* IA32/X64 Processor Error Information Structs, Err Struct Types (Table N.8) */
 #define X86_PROCESSOR_CACHE_CHK_ERROR_GUID		\

From f2788e963ff5668ecb642782a6f6e64adca8a58a Mon Sep 17 00:00:00 2001
From: Patrick Rudolph <patrick.rudolph@9elements.com>
Date: Wed, 17 Sep 2025 14:37:01 +0200
Subject: [PATCH 3014/3886] device: Rename PCI_EXP_SEC_CAP_ID ->
 PCI_CAP_ID_SEC_PCIE

Rename the define for "Secondary PCI Express Extended
Capability" and move it close to the other existing defines.

Cosmetic change. No functionality was changed.

Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: I3b1ce6820f508661d3241c36c90febe0c73b7a5a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90694
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
---
 src/device/pciexp_device.c   | 2 +-
 src/include/device/pci_def.h | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/device/pciexp_device.c b/src/device/pciexp_device.c
index a5f162e8ac..1b8f8ad79b 100644
--- a/src/device/pciexp_device.c
+++ b/src/device/pciexp_device.c
@@ -692,7 +692,7 @@ static void clear_lane_error_status(struct device *dev)
 	u32 reg32;
 	u16 pos;
 
-	pos = pciexp_find_extended_cap(dev, PCI_EXP_SEC_CAP_ID, 0);
+	pos = pciexp_find_extended_cap(dev, PCI_CAP_ID_SEC_PCIE, 0);
 	if (pos == 0)
 		return;
 
diff --git a/src/include/device/pci_def.h b/src/include/device/pci_def.h
index 6748b356b7..0838128057 100644
--- a/src/include/device/pci_def.h
+++ b/src/include/device/pci_def.h
@@ -204,6 +204,7 @@
 #define  PCI_CAP_ID_SSVID	0x0D	/* Bridge subsystem vendor/device ID */
 #define  PCI_CAP_ID_PCIE	0x10	/* PCI Express */
 #define  PCI_CAP_ID_MSIX	0x11	/* MSI-X */
+#define  PCI_CAP_ID_SEC_PCIE	0x19	/* Secondary PCI Express Extended Capability */
 #define PCI_CAP_LIST_NEXT	1	/* Next capability in the list */
 #define PCI_CAP_FLAGS		2	/* Capability defined flags (16 bits) */
 
@@ -481,7 +482,6 @@
 #define  PCIE_EXT_CAP_SRIOV_ID	0x0010
 
 /* Secondary PCI Express Extended Capability Structure */
-#define PCI_EXP_SEC_CAP_ID	0x19
 #define PCI_EXP_SEC_LNK_CTL3	4	/* Link Control 3 */
 #define PCI_EXP_SEC_LANE_ERR_STATUS	8	/* Lane Error Status */
 

From fbf0087918dff2cd1b914cf6ae84027428888f51 Mon Sep 17 00:00:00 2001
From: Pierce Chou <chou.pierce@inventec.corp-partner.google.com>
Date: Fri, 9 Jan 2026 13:53:19 +0800
Subject: [PATCH 3015/3886] mb/google/ocelot/var/ocicat: Use GPP_F10 for ISH

Currently, Linux is unable to load the ISH firmware,
as GPP_F10 define  lost
Update gpio pins GPP_F10 for ISH

bug=b:465776760
TEST=Flash and boot to OS on ocicat,
Verified ISH fw load in cpu console using below command.
    ~ # dmesg | grep ish
    output:
    intel_ish_ipc 0000:00:12.0: ISH loader: load firmware:
intel/ish/ish_wcl.bin

Change-Id: I4642560d3b14560e93158d1d19b496e22811600c
Signed-off-by: Pierce Chou <chou.pierce@inventec.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90708
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Pranava Y N <pranavayn@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/google/ocelot/variants/ocicat/gpio.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/mainboard/google/ocelot/variants/ocicat/gpio.c b/src/mainboard/google/ocelot/variants/ocicat/gpio.c
index 3a9a7b4ed2..25aa28c73b 100644
--- a/src/mainboard/google/ocelot/variants/ocicat/gpio.c
+++ b/src/mainboard/google/ocelot/variants/ocicat/gpio.c
@@ -242,7 +242,7 @@ static const struct pad_config gpio_table[] = {
 	/* GPP_F09:     M2_UFS_RST_N */
 	PAD_CFG_GPO(GPP_F09, 1, DEEP),
 	/* GPP_F10:     ISH_ACCEL_MB_INT_L */
-	PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_F05, NONE, DEEP, NF8),
+	PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_F10, NONE, DEEP, NF8),
 	/* GPP_F11:     NC */
 	PAD_NC(GPP_F11, NONE),
 	/* GPP_F12:     THC_I2C1_SCL_TCH_PAD */

From 94e6e5cd0d9b2df46a4c9188957c72c8cebc68a9 Mon Sep 17 00:00:00 2001
From: Avi Uday <aviuday@google.com>
Date: Tue, 13 Jan 2026 13:40:06 +0530
Subject: [PATCH 3016/3886] mb/google/ocelot: Add option to enable VGA mode 12

This commit adds a new Kconfig option to the ocelot mainboard
to enable VGA mode 12 support for early Sign of Life (eSOL).

- This option, `OCELOT_VGA_MODE12_SUPPORT`, is dependent on
  `FSP_UGOP_EARLY_SIGN_OF_LIFE`.
- It selects `ROMSTAGE_VGA` and `FSP_VGA_MODE12` to enable the
  necessary VGA components.

BUG=None
TEST=Verify VGA text rotation on ocelot RVP.

Change-Id: I71dff6e58c3e4487079c0090848ecde9da5153d7
Signed-off-by: Avi Uday <aviuday@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90731
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/google/ocelot/Kconfig | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/src/mainboard/google/ocelot/Kconfig b/src/mainboard/google/ocelot/Kconfig
index f83e19aa6a..d2a2e189e4 100644
--- a/src/mainboard/google/ocelot/Kconfig
+++ b/src/mainboard/google/ocelot/Kconfig
@@ -227,4 +227,13 @@ config OVERRIDE_DEVICETREE
 config VBOOT
 	select VBOOT_LID_SWITCH
 
+config OCELOT_VGA_MODE12_SUPPORT
+	bool "Enable VGA Mode 12 support for eSOL"
+	default n
+	depends on FSP_UGOP_EARLY_SIGN_OF_LIFE
+	select ROMSTAGE_VGA
+	select FSP_VGA_MODE12
+	help
+	  Select this if the FSP supports VGA mode 12 for eSOL.
+
 endif # BOARD_GOOGLE_OCELOT_COMMON

From e8ac9ffcd9a8e56667d18b12ad859851ad9de1a8 Mon Sep 17 00:00:00 2001
From: Uwe Poeche <uwe.poeche@siemens.com>
Date: Fri, 9 Jan 2026 08:35:59 +0100
Subject: [PATCH 3017/3886] mb/siemens/mc_ehl7: Add new board variant based on
 mc_ehl6

This new mainboard variant for the Siemens mc_ehl6 is initially based on
a direct copy of the mc_ehl6 configuration. This commit contains the
basic board setup with only minimal changes to enable the new variant.

Further specific adaptations for the mc_ehl7 hardware will be handled
in subsequent commits.

TEST=Build and boot to OS on mc_ehl7.

Change-Id: I46148492f65630175abb3ce884261d098314f2bc
Signed-off-by: Uwe Poeche <uwe.poeche@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90714
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/siemens/mc_ehl/Kconfig          |   5 +
 src/mainboard/siemens/mc_ehl/Kconfig.name     |   3 +
 .../siemens/mc_ehl/variants/mc_ehl7/Kconfig   |  43 +++
 .../mc_ehl/variants/mc_ehl7/Makefile.mk       |   8 +
 .../mc_ehl/variants/mc_ehl7/devicetree.cb     | 260 ++++++++++++++++++
 .../siemens/mc_ehl/variants/mc_ehl7/gpio.c    | 137 +++++++++
 .../mc_ehl/variants/mc_ehl7/mainboard.c       |  69 +++++
 .../siemens/mc_ehl/variants/mc_ehl7/memory.c  |  48 ++++
 .../siemens/mc_ehl/variants/mc_ehl7/post.c    |  10 +
 9 files changed, 583 insertions(+)
 create mode 100644 src/mainboard/siemens/mc_ehl/variants/mc_ehl7/Kconfig
 create mode 100644 src/mainboard/siemens/mc_ehl/variants/mc_ehl7/Makefile.mk
 create mode 100644 src/mainboard/siemens/mc_ehl/variants/mc_ehl7/devicetree.cb
 create mode 100644 src/mainboard/siemens/mc_ehl/variants/mc_ehl7/gpio.c
 create mode 100644 src/mainboard/siemens/mc_ehl/variants/mc_ehl7/mainboard.c
 create mode 100644 src/mainboard/siemens/mc_ehl/variants/mc_ehl7/memory.c
 create mode 100644 src/mainboard/siemens/mc_ehl/variants/mc_ehl7/post.c

diff --git a/src/mainboard/siemens/mc_ehl/Kconfig b/src/mainboard/siemens/mc_ehl/Kconfig
index 5aff0be1b5..3db9ad0d52 100644
--- a/src/mainboard/siemens/mc_ehl/Kconfig
+++ b/src/mainboard/siemens/mc_ehl/Kconfig
@@ -29,6 +29,9 @@ config BOARD_SIEMENS_MC_EHL5
 config BOARD_SIEMENS_MC_EHL6
 	select BOARD_SIEMENS_BASEBOARD_MC_EHL
 
+config BOARD_SIEMENS_MC_EHL7
+	select BOARD_SIEMENS_BASEBOARD_MC_EHL
+
 source "src/mainboard/siemens/mc_ehl/variants/*/Kconfig"
 
 if BOARD_SIEMENS_BASEBOARD_MC_EHL
@@ -43,6 +46,7 @@ config VARIANT_DIR
 	default "mc_ehl4" if BOARD_SIEMENS_MC_EHL4
 	default "mc_ehl5" if BOARD_SIEMENS_MC_EHL5
 	default "mc_ehl6" if BOARD_SIEMENS_MC_EHL6
+	default "mc_ehl7" if BOARD_SIEMENS_MC_EHL7
 
 config MAINBOARD_PART_NUMBER
 	default "MC EHL1" if BOARD_SIEMENS_MC_EHL1
@@ -51,6 +55,7 @@ config MAINBOARD_PART_NUMBER
 	default "MC EHL4" if BOARD_SIEMENS_MC_EHL4
 	default "MC EHL5" if BOARD_SIEMENS_MC_EHL5
 	default "MC EHL6" if BOARD_SIEMENS_MC_EHL6
+	default "MC EHL7" if BOARD_SIEMENS_MC_EHL7
 
 config DEVICETREE
 	default "variants/\$(CONFIG_VARIANT_DIR)/devicetree.cb"
diff --git a/src/mainboard/siemens/mc_ehl/Kconfig.name b/src/mainboard/siemens/mc_ehl/Kconfig.name
index 50233cea9c..ffbfc9d124 100644
--- a/src/mainboard/siemens/mc_ehl/Kconfig.name
+++ b/src/mainboard/siemens/mc_ehl/Kconfig.name
@@ -19,3 +19,6 @@ config BOARD_SIEMENS_MC_EHL5
 
 config BOARD_SIEMENS_MC_EHL6
 	bool "-> MC EHL6"
+
+config BOARD_SIEMENS_MC_EHL7
+	bool "-> MC EHL7"
diff --git a/src/mainboard/siemens/mc_ehl/variants/mc_ehl7/Kconfig b/src/mainboard/siemens/mc_ehl/variants/mc_ehl7/Kconfig
new file mode 100644
index 0000000000..7cc7c5abee
--- /dev/null
+++ b/src/mainboard/siemens/mc_ehl/variants/mc_ehl7/Kconfig
@@ -0,0 +1,43 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
+if BOARD_SIEMENS_MC_EHL7
+
+config BOARD_SPECIFIC_OPTIONS
+	def_bool y
+	select DRIVER_INTEL_I210
+	select DRIVERS_ETH_PHY_M88E1512
+	select DRIVERS_I2C_RV3028C7
+	select EHL_TSN_DRIVER
+	select MAINBOARD_HAS_TPM2
+	select MEMORY_MAPPED_TPM
+	select NC_FPGA_POST_CODE
+	select SOC_INTEL_COMMON_BLOCK_LPC_COMB_ENABLE
+	select TPM_MEASURED_BOOT
+	select TPM_MEASURED_BOOT_INIT_BOOTBLOCK
+
+config FMDFILE
+	default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/mc_ehl.fmd"
+
+config UART_FOR_CONSOLE
+	int
+	default 0
+
+config EARLY_PCI_BRIDGE_DEVICE
+	hex
+	depends on NC_FPGA_POST_CODE
+	default 0x1c
+
+config EARLY_PCI_BRIDGE_FUNCTION
+	hex
+	depends on NC_FPGA_POST_CODE
+	default 0x0
+
+config EARLY_PCI_MMIO_BASE
+	hex
+	depends on NC_FPGA_POST_CODE
+	default 0xfe800000
+
+config SOC_INTEL_ELKHARTLAKE_TCO_NO_REBOOT_EN
+	default y
+
+endif # BOARD_SIEMENS_MC_EHL7
diff --git a/src/mainboard/siemens/mc_ehl/variants/mc_ehl7/Makefile.mk b/src/mainboard/siemens/mc_ehl/variants/mc_ehl7/Makefile.mk
new file mode 100644
index 0000000000..d9050f098d
--- /dev/null
+++ b/src/mainboard/siemens/mc_ehl/variants/mc_ehl7/Makefile.mk
@@ -0,0 +1,8 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
+bootblock-y += gpio.c
+romstage-y += memory.c
+ramstage-y += gpio.c
+ramstage-y += mainboard.c
+
+all-$(CONFIG_NC_FPGA_POST_CODE) += post.c
diff --git a/src/mainboard/siemens/mc_ehl/variants/mc_ehl7/devicetree.cb b/src/mainboard/siemens/mc_ehl/variants/mc_ehl7/devicetree.cb
new file mode 100644
index 0000000000..5180770908
--- /dev/null
+++ b/src/mainboard/siemens/mc_ehl/variants/mc_ehl7/devicetree.cb
@@ -0,0 +1,260 @@
+chip soc/intel/elkhartlake
+
+	device cpu_cluster 0 on end
+
+	# GPE configuration
+	# Note that GPE events called out in ASL code rely on this
+	# route. i.e. If this route changes then the affected GPE
+	# offset bits also need to be changed.
+	register "pmc_gpe0_dw0" = "GPP_B"
+	register "pmc_gpe0_dw1" = "GPP_F"
+	register "pmc_gpe0_dw2" = "GPP_E"
+
+	# FSP configuration
+	register "SaGv" = "SaGv_Disabled"
+
+	# Enable IBECC for the complete memory
+	register "ibecc" = "{
+		.enable = 1,
+		.mode = IBECC_ALL
+	}"
+
+	# USB related UPDs
+	register "usb2_ports[0]" = "USB2_PORT_MID(OC2)"	# X125/X135
+	register "usb2_ports[1]" = "USB2_PORT_MID(OC2)"	# X125/X135
+	register "usb2_ports[2]" = "USB2_PORT_MID(OC0)"	# X145/X155
+	register "usb2_ports[3]" = "USB2_PORT_MID(OC0)"	# X145/X155
+	register "usb2_ports[4]" = "USB2_PORT_MID(OC3)"	# USB Panel
+	register "usb2_ports[5]" = "USB2_PORT_MID(OC3)"	# USB Panel
+	register "usb2_ports[6]" = "USB2_PORT_EMPTY"
+	register "usb2_ports[7]" = "USB2_PORT_EMPTY"
+	register "usb2_ports[8]" = "USB2_PORT_EMPTY"
+	register "usb2_ports[9]" = "USB2_PORT_EMPTY"
+
+	register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)"	# USB3/2 Type A port1
+	register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)"	# USB3/2 Type A port2
+	register "usb3_ports[2]" = "USB3_PORT_EMPTY"	# UNUSED
+	register "usb3_ports[3]" = "USB3_PORT_EMPTY"	# UNUSED
+
+	# Skip the CPU replacement check
+	register "SkipCpuReplacementCheck" = "1"
+
+	# PCIe root ports related UPDs
+	register "PcieClkSrcUsage[0]" = "PCIE_CLK_FREE"
+	register "PcieClkSrcUsage[1]" = "PCIE_CLK_FREE"
+	register "PcieClkSrcUsage[2]" = "PCIE_CLK_FREE"
+	register "PcieClkSrcUsage[3]" = "PCIE_CLK_NOTUSED"
+	register "PcieClkSrcUsage[4]" = "PCIE_CLK_FREE"
+	register "PcieClkSrcUsage[5]" = "PCIE_CLK_FREE"
+
+	register "PcieClkSrcClkReq[0]" = "PCIE_CLK_NOTUSED"
+	register "PcieClkSrcClkReq[1]" = "PCIE_CLK_NOTUSED"
+	register "PcieClkSrcClkReq[2]" = "PCIE_CLK_NOTUSED"
+	register "PcieClkSrcClkReq[3]" = "PCIE_CLK_NOTUSED"
+	register "PcieClkSrcClkReq[4]" = "PCIE_CLK_NOTUSED"
+	register "PcieClkSrcClkReq[5]" = "PCIE_CLK_NOTUSED"
+
+	# Disable all L1 substates for PCIe root ports
+	register "PcieRpL1Substates[0]" = "L1_SS_DISABLED"
+	register "PcieRpL1Substates[1]" = "L1_SS_DISABLED"
+	register "PcieRpL1Substates[2]" = "L1_SS_DISABLED"
+	register "PcieRpL1Substates[4]" = "L1_SS_DISABLED"
+	register "PcieRpL1Substates[6]" = "L1_SS_DISABLED"
+
+	# Disable LTR for all PCIe root ports
+	register "PcieRpLtrDisable[0]" = "true"
+	register "PcieRpLtrDisable[1]" = "true"
+	register "PcieRpLtrDisable[2]" = "true"
+	register "PcieRpLtrDisable[4]" = "true"
+	register "PcieRpLtrDisable[6]" = "true"
+
+	# Enable PCIe PTM (Precision Time Measurement) for all PCIe root ports
+	register "PciePtm[0]" = "true"
+	register "PciePtm[1]" = "true"
+	register "PciePtm[2]" = "true"
+	register "PciePtm[4]" = "true"
+	register "PciePtm[6]" = "true"
+
+	# Determine PCIe root port speed
+	register "PcieRpPcieSpeed[6]" = "2"
+
+	# Storage (SATA/SDCARD/EMMC) related UPDs
+	register "SataSalpSupport" = "0"
+	register "SataPortsEnable[1]" = "1"
+	register "SataPortsDevSlp[1]" = "0"
+	register "SataPortsSSD[1]" = "1"
+	register "SataSpeed" = "SATA_GEN2"
+
+	register "ScsEmmcHs400Enabled" = "0"
+	register "ScsEmmcDdr50Enabled" = "1"
+	register "SdCardPowerEnableActiveHigh" = "1"
+
+	# GPIO for SD card detect
+	register "sdcard_cd_gpio" = "GPP_G5"
+
+	# LPSS Serial IO (I2C/UART/GSPI) related UPDs
+	register "SerialIoI2cMode" = "{
+		[PchSerialIoIndexI2C0] = PchSerialIoDisabled,
+		[PchSerialIoIndexI2C1] = PchSerialIoPci,
+		[PchSerialIoIndexI2C2] = PchSerialIoPci,
+		[PchSerialIoIndexI2C3] = PchSerialIoDisabled,
+		[PchSerialIoIndexI2C4] = PchSerialIoPci,
+		[PchSerialIoIndexI2C5] = PchSerialIoDisabled,
+		[PchSerialIoIndexI2C6] = PchSerialIoPci,
+		[PchSerialIoIndexI2C7] = PchSerialIoDisabled,
+	}"
+
+	register "SerialIoI2cPadsTermination" = "{
+		[PchSerialIoIndexI2C1] = 1,
+		[PchSerialIoIndexI2C2] = 1,
+		[PchSerialIoIndexI2C4] = 1,
+		[PchSerialIoIndexI2C6] = 1,
+        }"
+
+	register "SerialIoUartMode" = "{
+		[PchSerialIoIndexUART0] = PchSerialIoPci,
+		[PchSerialIoIndexUART1] = PchSerialIoPci,
+		[PchSerialIoIndexUART2] = PchSerialIoPci,
+	}"
+
+	register "SerialIoUartDmaEnable" = "{
+		[PchSerialIoIndexUART0] = 1,
+		[PchSerialIoIndexUART1] = 1,
+		[PchSerialIoIndexUART2] = 1,
+	}"
+
+	# TSN GBE related UPDs
+	register "PchTsnGbeLinkSpeed" = "Tsn_1_Gbps"
+	register "PchTsnGbeSgmiiEnable" = "1"
+	register "PseDmaOwn[0]" = "Host_Owned"
+
+	# FIVR related settings
+	register "fivr" = "{
+		.fivr_config_en = true,
+		.vcc_low_high_us = 50,
+	}"
+
+	# Disable L1 prefetcher for real-time demands
+	register "L1_prefetcher_disable" = "true"
+
+	# Enable real-time tuning
+	register "realtime_tuning_enable" = "true"
+
+	device domain 0 on
+		device pci 00.0 on	end # Host Bridge
+		device pci 02.0 on	end # Integrated Graphics Device
+
+		device pci 10.0 on	    # I2C6
+			# Add dummy I2C device to limit BUS speed to 100 kHz in OS
+			chip drivers/i2c/generic
+				register "hid" = ""PRP0001""
+				register "speed" = "I2C_SPEED_STANDARD"
+				device i2c 0x7f on end
+			end
+		end
+
+		device pci 14.0 on	end # USB3.1 xHCI
+
+		device pci 15.1 on	    # I2C1
+			# Enable external RTC chip
+			chip drivers/i2c/rv3028c7
+				register "bus_speed" = "I2C_SPEED_STANDARD"
+				register "set_user_date" = "1"
+				register "user_year" = "04"
+				register "user_month" = "07"
+				register "user_day" = "01"
+				register "user_weekday" = "4"
+				register "bckup_sw_mode" = "BACKUP_SW_LEVEL"
+				register "cap_charge" = "CHARGE_OFF"
+				device i2c 0x52 on end  # RTC RV3028-C7
+			end
+			# Add dummy I2C device to limit BUS speed to 100 kHz in OS
+			chip drivers/i2c/generic
+				register "hid" = ""PRP0001""
+				register "speed" = "I2C_SPEED_STANDARD"
+				device i2c 0x7f on end
+			end
+		end
+		device pci 15.2 on	    # I2C2
+			# Add dummy I2C device to limit BUS speed to 100 kHz in OS
+			chip drivers/i2c/generic
+				register "hid" = ""PRP0001""
+				register "speed" = "I2C_SPEED_STANDARD"
+				device i2c 0x7f on end
+			end
+		end
+
+		device pci 16.0 hidden	end # Management Engine Interface 1
+
+		device pci 17.0 on      end # SATA
+
+		device pci 19.0 on	    # I2C4
+			# Add dummy I2C device to limit BUS speed to 100 kHz in OS
+			chip drivers/i2c/generic
+				register "hid" = ""PRP0001""
+				register "speed" = "I2C_SPEED_STANDARD"
+				device i2c 0x7f on end
+			end
+		end
+		device pci 19.2 on	end # UART2
+
+		device pci 1a.0 on	end # eMMC
+		device pci 1a.1 on	end # SD
+
+		device pci 1c.0 on	end # RP1 (pcie0 single VC)
+		device pci 1c.1 on	end # RP2 (pcie0 single VC)
+		device pci 1c.2 on	end # RP3 (pcie0 single VC)
+		device pci 1c.4 on	end # RP5 (pcie1 multi VC)
+		device pci 1c.6 on	end # RP7 (pcie3 multi VC)
+
+		device pci 1d.0 off	end # Intel PSE IPC (local host to PSE)
+		device pci 1d.1 on	    # Intel PSE Time-Sensitive Networking GbE 0
+			# Enable external Marvell PHY 88E1512
+			chip drivers/net/phy/m88e1512
+				register "configure_leds" = "true"
+				# LED[0]: On - 1000 Mbps Link, Off - Else
+				register "led_0_ctrl" = "7"
+				# LED[1]: On - 100 Mbps Link, Off - Else
+				register "led_1_ctrl" = "7"
+				# LED[2]: Blink - Activity, Off - No Activity
+				register "led_2_ctrl" = "4"
+				# INTn is not routed to LED[2] pin
+				register "enable_int" = "false"
+				register "downshift_cnt" = "2"
+				device mdio 0 on    # PHY address
+					ops m88e1512_ops
+				end
+			end
+		end
+
+		device pci 1e.0 on	end # UART0
+		device pci 1e.1 on	end # UART1
+		device pci 1e.4 on	    # PCH Time-Sensitive Networking GbE
+			# Enable external Marvell PHY 88E1512
+			chip drivers/net/phy/m88e1512
+				register "configure_leds" = "true"
+				# LED[0]: On - 1000 Mbps Link, Off - Else
+				register "led_0_ctrl" = "7"
+				# LED[1]: On - 100 Mbps Link, Off - Else
+				register "led_1_ctrl" = "7"
+				# LED[2]: Blink - Activity, Off - No Activity
+				register "led_2_ctrl" = "4"
+				# INTn is not routed to LED[2] pin
+				register "enable_int" = "false"
+				register "downshift_cnt" = "2"
+				device mdio 1 on    # PHY address
+					ops m88e1512_ops
+				end
+			end
+		end
+
+		device pci 1f.0 on	    # eSPI Interface
+			chip drivers/pc80/tpm
+				device pnp 0c31.0 on end
+			end
+		end
+		device pci 1f.2 hidden	end # Power Management Controller
+		device pci 1f.4	on	end # SMBus
+		device pci 1f.5 on	end # PCH SPI (flash & TPM)
+	end
+end
diff --git a/src/mainboard/siemens/mc_ehl/variants/mc_ehl7/gpio.c b/src/mainboard/siemens/mc_ehl/variants/mc_ehl7/gpio.c
new file mode 100644
index 0000000000..49f737b868
--- /dev/null
+++ b/src/mainboard/siemens/mc_ehl/variants/mc_ehl7/gpio.c
@@ -0,0 +1,137 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <baseboard/variants.h>
+#include <commonlib/helpers.h>
+
+/* Pad configuration in ramstage */
+static const struct pad_config gpio_table[] = {
+	/* Community 0 - GpioGroup GPP_B */
+	PAD_CFG_NF(GPP_B2, NONE, PLTRST, NF1),		/* PMC_VRALERT_N */
+	PAD_CFG_NF(GPP_B3, NONE, PLTRST, NF4),		/* ESPI_ALERT0_N */
+	PAD_NC(GPP_B4, NONE),				/* Not connected */
+	PAD_NC(GPP_B9, NONE),				/* Not connected */
+	PAD_NC(GPP_B10, NONE),				/* Not connected */
+	PAD_CFG_NF(GPP_B11, NONE, PLTRST, NF1),		/* PMC_ALERT_N */
+	PAD_NC(GPP_B14, NONE),				/* Not connected */
+	PAD_NC(GPP_B15, NONE),				/* Not connected */
+	PAD_NC(GPP_B18, NONE),				/* Not connected */
+	PAD_NC(GPP_B19, NONE),				/* Not connected */
+	PAD_CFG_NF(GPP_B23, NONE, PLTRST, NF2),		/* PCHHOT_N */
+
+	/* Community 0 - GpioGroup GPP_T */
+	PAD_CFG_NF(GPP_T4, NONE, DEEP, NF1),		/* PSE_GBE0_INT */
+	PAD_CFG_GPO(GPP_T5, 1, DEEP),			/* PSE_GBE0_RST_N */
+	PAD_CFG_NF(GPP_T6, NONE, DEEP, NF1),		/* PSE_GBE0_AUXTS */
+	PAD_CFG_NF(GPP_T7, NONE, DEEP, NF1),		/* PSE_GBE0_PPS */
+	PAD_CFG_NF(GPP_T12, NONE, DEEP, NF2),		/* SIO_UART0_RXD */
+	PAD_CFG_NF(GPP_T13, NONE, DEEP, NF2),		/* SIO_UART0_TXD */
+
+	/* Community 0 - GpioGroup GPP_G */
+	PAD_NC(GPP_G8, NONE),				/* Not connected */
+	PAD_NC(GPP_G9, NONE),				/* Not connected */
+	PAD_CFG_GPI(GPP_G19, UP_20K, PLTRST),		/* TPM_IRQ_N */
+
+	/* Community 1 - GpioGroup GPP_V */
+	PAD_CFG_NF(GPP_V0, UP_20K, DEEP, NF1),		/* EMMC_CMD */
+	PAD_CFG_NF(GPP_V1, UP_20K, DEEP, NF1),		/* EMMC_DATA0 */
+	PAD_CFG_NF(GPP_V2, UP_20K, DEEP, NF1),		/* EMMC_DATA1 */
+	PAD_CFG_NF(GPP_V3, UP_20K, DEEP, NF1),		/* EMMC_DATA2 */
+	PAD_CFG_NF(GPP_V4, UP_20K, DEEP, NF1),		/* EMMC_DATA3 */
+	PAD_CFG_NF(GPP_V5, UP_20K, DEEP, NF1),		/* EMMC_DATA4 */
+	PAD_CFG_NF(GPP_V6, UP_20K, DEEP, NF1),		/* EMMC_DATA5 */
+	PAD_CFG_NF(GPP_V7, UP_20K, DEEP, NF1),		/* EMMC_DATA6 */
+	PAD_CFG_NF(GPP_V8, UP_20K, DEEP, NF1),		/* EMMC_DATA7 */
+	PAD_CFG_NF(GPP_V9, DN_20K, DEEP, NF1),		/* EMMC_RCLK */
+	PAD_CFG_NF(GPP_V10, DN_20K, DEEP, NF1),		/* EMMC_CLK */
+	PAD_CFG_NF(GPP_V11, NONE, DEEP, NF1),		/* EMMC_RESET */
+
+	/* Community 1 - GpioGroup GPP_H */
+	PAD_CFG_NF(GPP_H10, NONE, DEEP, NF1),		/* PCIE_CLKREQ4_N */
+	PAD_CFG_NF(GPP_H11, NONE, DEEP, NF1),		/* PCIE_CLKREQ5_N */
+
+	/* Community 1 - GpioGroup GPP_D */
+	PAD_CFG_NF(GPP_D5, NONE, DEEP, NF1),		/* PCIE_CLKREQ0_N */
+	PAD_CFG_NF(GPP_D6, NONE, DEEP, NF1),		/* PCIE_CLKREQ1_N */
+	PAD_CFG_NF(GPP_D7, NONE, DEEP, NF1),		/* PCIE_CLKREQ2_N */
+	PAD_CFG_NF(GPP_D8, NONE, DEEP, NF1),		/* PCIE_CLKREQ3_N */
+
+	/* Community 1 - GpioGroup GPP_U */
+	PAD_CFG_NF(GPP_U0, NONE, DEEP, NF1),		/* GBE_INT */
+	PAD_CFG_GPO(GPP_U1, 1, DEEP),			/* GBE_RST_N */
+	PAD_NC(GPP_U12, NONE),				/* Not connected */
+	PAD_NC(GPP_U13, NONE),				/* Not connected */
+	PAD_NC(GPP_U16, NONE),				/* Not connected */
+	PAD_NC(GPP_U17, NONE),				/* Not connected */
+	PAD_NC(GPP_U18, NONE),				/* Not connected */
+
+	/* Community 2 - GpioGroup DSW */
+	PAD_CFG_NF(GPD1, NONE, PLTRST, NF1),		/* ACPRESENT */
+	PAD_NC(GPD9, NONE),				/* Not connected */
+	PAD_NC(GPD11, NONE),				/* Not connected */
+
+	/* Community 3 - GpioGroup GPP_S */
+	PAD_NC(GPP_S0, NONE),				/* Not connected */
+	PAD_NC(GPP_S1, NONE),				/* Not connected */
+
+	/* Community 3 - GpioGroup GPP_A */
+	PAD_CFG_NF(GPP_A0, NONE, DEEP, NF1),		/* PSE_GBE0_RGMII_TXD3 */
+	PAD_CFG_NF(GPP_A1, NONE, DEEP, NF1),		/* PSE_GBE0_RGMII_TXD2 */
+	PAD_CFG_NF(GPP_A2, NONE, DEEP, NF1),		/* PSE_GBE0_RGMII_TXD1 */
+	PAD_CFG_NF(GPP_A3, NONE, DEEP, NF1),		/* PSE_GBE0_RGMII_TXD0 */
+	PAD_CFG_NF(GPP_A4, NONE, DEEP, NF1),		/* PSE_GBE0_RGMII_TXCLK */
+	PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1),		/* PSE_GBE0_RGMII_TXCTL */
+	PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1),		/* PSE_GBE0_RGMII_RXCLK */
+	PAD_CFG_NF(GPP_A7, NONE, DEEP, NF1),		/* PSE_GBE0_RGMII_RXD3 */
+	PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1),		/* PSE_GBE0_RGMII_RXD2 */
+	PAD_CFG_NF(GPP_A9, NONE, DEEP, NF1),		/* PSE_GBE0_RGMII_RXD1 */
+	PAD_CFG_NF(GPP_A10, NONE, DEEP, NF1),		/* PSE_GBE0_RGMII_RXD0 */
+	PAD_CFG_NF(GPP_A23, NONE, DEEP, NF1),		/* PSE_GBE0_RGMII_RXCTL */
+
+	/* Community 4 - GpioGroup GPP_C */
+	PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1),		/* PSE_GBE0_MDC */
+	PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1),		/* PSE_GBE0_MDIO */
+	PAD_NC(GPP_C8, NONE),				/* Not connected */
+	PAD_CFG_NF(GPP_C12, NONE, DEEP, NF4),		/* SIO_UART1_RXD */
+	PAD_CFG_NF(GPP_C13, NONE, DEEP, NF4),		/* SIO_UART1_TXD */
+	PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1),		/* GBE_MDIO */
+	PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1),		/* GBE_MDC */
+
+	/* Community 4 - GpioGroup GPP_F */
+	PAD_NC(GPP_F1, NONE),				/* Not connected */
+	PAD_NC(GPP_F3, NONE),				/* Not connected */
+	PAD_NC(GPP_F8, NONE),				/* Not connected */
+	PAD_NC(GPP_F11, NONE),				/* Not connected */
+	PAD_NC(GPP_F12, NONE),				/* Not connected */
+	PAD_NC(GPP_F13, NONE),				/* Not connected */
+	PAD_NC(GPP_F14, NONE),				/* Not connected */
+	PAD_NC(GPP_F15, NONE),				/* Not connected */
+	PAD_NC(GPP_F16, NONE),				/* Not connected */
+	PAD_NC(GPP_F17, NONE),				/* Not connected */
+	PAD_CFG_GPO(GPP_F20, 0, DEEP),			/* LED_BIOS_DONE */
+
+	/* Community 4 - GpioGroup GPP_E */
+	PAD_NC(GPP_E15, NONE),				/* Not connected */
+	PAD_NC(GPP_E16, NONE),				/* Not connected */
+	PAD_NC(GPP_E18, NONE),				/* Not connected */
+	PAD_NC(GPP_E19, NONE),				/* Not connected */
+	PAD_NC(GPP_E23, NONE),				/* Not connected */
+
+	/* Community 5 - GpioGroup GPP_R */
+	PAD_NC(GPP_R1, NONE),				/* Not connected */
+	PAD_NC(GPP_R3, NONE),				/* Not connected */
+};
+
+/* Early pad configuration in bootblock */
+static const struct pad_config early_gpio_table[] = {};
+
+const struct pad_config *variant_gpio_table(size_t *num)
+{
+	*num = ARRAY_SIZE(gpio_table);
+	return gpio_table;
+}
+
+const struct pad_config *variant_early_gpio_table(size_t *num)
+{
+	*num = ARRAY_SIZE(early_gpio_table);
+	return early_gpio_table;
+}
diff --git a/src/mainboard/siemens/mc_ehl/variants/mc_ehl7/mainboard.c b/src/mainboard/siemens/mc_ehl/variants/mc_ehl7/mainboard.c
new file mode 100644
index 0000000000..b3846196fc
--- /dev/null
+++ b/src/mainboard/siemens/mc_ehl/variants/mc_ehl7/mainboard.c
@@ -0,0 +1,69 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <baseboard/variants.h>
+#include <bootstate.h>
+#include <device/pci_ids.h>
+#include <gpio.h>
+#include <intelblocks/pcr.h>
+#include <soc/pci_devs.h>
+#include <soc/pcr_ids.h>
+
+#define HOSTCTRL2		0x3E
+#define  HOSTCTRL2_PRESET	(1 << 15)
+#define MMC_CAP_BYP		0x810
+#define  MMC_CAP_BYP_EN		0x5A
+#define MMC_CAP_BYP_REG1	0x814
+#define  MMC_CAP_BYP_SDR50	(1 << 13)
+#define  MMC_CAP_BYP_SDR104	(1 << 14)
+#define  MMC_CAP_BYP_DDR50	(1 << 15)
+
+/* Disable SDR104 and SDR50 mode while keeping DDR50 mode enabled. */
+static void disable_sdr_modes(struct resource *res)
+{
+	write32(res2mmio(res, MMC_CAP_BYP, 0), MMC_CAP_BYP_EN);
+	clrsetbits32(res2mmio(res, MMC_CAP_BYP_REG1, 0),
+			MMC_CAP_BYP_SDR104 | MMC_CAP_BYP_SDR50,
+			MMC_CAP_BYP_DDR50);
+}
+
+void variant_mainboard_final(void)
+{
+	struct device *dev;
+
+	/* PIR8 register mapping for PCIe root ports
+	   INTA#->PIRQC#, INTB#->PIRQD#, INTC#->PIRQA#, INTD#-> PIRQB# */
+	pcr_write16(PID_ITSS, 0x3150, 0x1032);
+
+	/* Disable clock outputs 1-5 (CLKOUT) for XIO2001 PCIe to PCI Bridge. */
+	dev = dev_find_device(PCI_VID_TI, PCI_DID_TI_XIO2001, 0);
+	if (dev)
+		pci_write_config8(dev, 0xd8, 0x3e);
+
+	dev = pcidev_path_on_root(PCH_DEVFN_SDCARD);
+	if (dev) {
+		struct resource *res = probe_resource(dev, PCI_BASE_ADDRESS_0);
+		if (res) {
+			disable_sdr_modes(res);
+
+			/* Use preset driver strength from preset value
+			   registers. */
+			clrsetbits16(res2mmio(res, HOSTCTRL2, 0), 0,
+					HOSTCTRL2_PRESET);
+		}
+	}
+
+	dev = pcidev_path_on_root(PCH_DEVFN_EMMC);
+	if (dev) {
+		struct resource *res = probe_resource(dev, PCI_BASE_ADDRESS_0);
+		if (res)
+			disable_sdr_modes(res);
+	}
+}
+
+static void finalize_boot(void *unused)
+{
+	/* Set coreboot ready LED. */
+	gpio_output(GPP_F20, 1);
+}
+
+BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_BOOT, BS_ON_ENTRY, finalize_boot, NULL);
diff --git a/src/mainboard/siemens/mc_ehl/variants/mc_ehl7/memory.c b/src/mainboard/siemens/mc_ehl/variants/mc_ehl7/memory.c
new file mode 100644
index 0000000000..551583394b
--- /dev/null
+++ b/src/mainboard/siemens/mc_ehl/variants/mc_ehl7/memory.c
@@ -0,0 +1,48 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <baseboard/variants.h>
+#include <gpio.h>
+#include <soc/meminit.h>
+#include <soc/romstage.h>
+
+static const struct mb_cfg mc_ehl_lpddr4x_memcfg_cfg = {
+	.dq_map[DDR_CH0] = {
+		{0xf, 0xf0}, {0xf, 0xf0}, {0xff, 0x0}, {0x0, 0x0}, {0x0, 0x0}, {0x0, 0x0}
+	},
+
+	.dq_map[DDR_CH1] = {
+		{0xf, 0xf0}, {0xf, 0xf0}, {0xff, 0x0}, {0x0, 0x0}, {0x0, 0x0}, {0x0, 0x0}
+	},
+
+	/*
+	 * The dqs_map arrays map the ddr4 pins to the SoC pins
+	 * for both channels.
+	 *
+	 * the index = pin number on ddr4 part
+	 * the value = pin number on SoC
+	 */
+	.dqs_map[DDR_CH0] = {3, 0, 1, 2, 7, 4, 5, 6},
+	.dqs_map[DDR_CH1] = {3, 0, 1, 2, 7, 4, 5, 6},
+
+	/* Baseboard uses 100, 100 and 100 rcomp resistors */
+	.rcomp_resistor = {100, 100, 100},
+
+	.rcomp_targets = {60, 40, 30, 20, 30},
+
+	/* LPDDR4x does not allow interleaved memory */
+	.dq_pins_interleaved = 0,
+
+	/* Baseboard is using config 2 for vref_ca */
+	.vref_ca_config = 2,
+
+	/* Enable Early Command Training */
+	.ect = 1,
+
+	/* Set Board Type */
+	.UserBd = BOARD_TYPE_MOBILE,
+};
+
+const struct mb_cfg *variant_memcfg_config(void)
+{
+	return &mc_ehl_lpddr4x_memcfg_cfg;
+}
diff --git a/src/mainboard/siemens/mc_ehl/variants/mc_ehl7/post.c b/src/mainboard/siemens/mc_ehl/variants/mc_ehl7/post.c
new file mode 100644
index 0000000000..c34e2539bc
--- /dev/null
+++ b/src/mainboard/siemens/mc_ehl/variants/mc_ehl7/post.c
@@ -0,0 +1,10 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <console/console.h>
+#include <nc_fpga.h>
+#include <types.h>
+
+void mainboard_post(uint8_t value)
+{
+	nc_fpga_post(value);
+}

From ddf4748c221e2d11ee186193bdd81cb65551a93e Mon Sep 17 00:00:00 2001
From: Uwe Poeche <uwe.poeche@siemens.com>
Date: Fri, 9 Jan 2026 12:27:16 +0100
Subject: [PATCH 3018/3886] mb/siemens/mc_ehl7: Deactivate RTC

On this mainboard no RTC is assembled. Therefore, it is deactivated.

TEST=Boot into OS and verify if relevant I2C Controller is disabled and
no error in coreboot log is shown.

Change-Id: I23b4a735a09686fa2636280d7b410db59d884c49
Signed-off-by: Uwe Poeche <uwe.poeche@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90715
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
---
 .../siemens/mc_ehl/variants/mc_ehl7/Kconfig   |  1 -
 .../mc_ehl/variants/mc_ehl7/devicetree.cb     | 23 +------------------
 2 files changed, 1 insertion(+), 23 deletions(-)

diff --git a/src/mainboard/siemens/mc_ehl/variants/mc_ehl7/Kconfig b/src/mainboard/siemens/mc_ehl/variants/mc_ehl7/Kconfig
index 7cc7c5abee..6ce0b48052 100644
--- a/src/mainboard/siemens/mc_ehl/variants/mc_ehl7/Kconfig
+++ b/src/mainboard/siemens/mc_ehl/variants/mc_ehl7/Kconfig
@@ -6,7 +6,6 @@ config BOARD_SPECIFIC_OPTIONS
 	def_bool y
 	select DRIVER_INTEL_I210
 	select DRIVERS_ETH_PHY_M88E1512
-	select DRIVERS_I2C_RV3028C7
 	select EHL_TSN_DRIVER
 	select MAINBOARD_HAS_TPM2
 	select MEMORY_MAPPED_TPM
diff --git a/src/mainboard/siemens/mc_ehl/variants/mc_ehl7/devicetree.cb b/src/mainboard/siemens/mc_ehl/variants/mc_ehl7/devicetree.cb
index 5180770908..776eab22e3 100644
--- a/src/mainboard/siemens/mc_ehl/variants/mc_ehl7/devicetree.cb
+++ b/src/mainboard/siemens/mc_ehl/variants/mc_ehl7/devicetree.cb
@@ -95,7 +95,7 @@ chip soc/intel/elkhartlake
 	# LPSS Serial IO (I2C/UART/GSPI) related UPDs
 	register "SerialIoI2cMode" = "{
 		[PchSerialIoIndexI2C0] = PchSerialIoDisabled,
-		[PchSerialIoIndexI2C1] = PchSerialIoPci,
+		[PchSerialIoIndexI2C1] = PchSerialIoDisabled,
 		[PchSerialIoIndexI2C2] = PchSerialIoPci,
 		[PchSerialIoIndexI2C3] = PchSerialIoDisabled,
 		[PchSerialIoIndexI2C4] = PchSerialIoPci,
@@ -105,7 +105,6 @@ chip soc/intel/elkhartlake
 	}"
 
 	register "SerialIoI2cPadsTermination" = "{
-		[PchSerialIoIndexI2C1] = 1,
 		[PchSerialIoIndexI2C2] = 1,
 		[PchSerialIoIndexI2C4] = 1,
 		[PchSerialIoIndexI2C6] = 1,
@@ -155,26 +154,6 @@ chip soc/intel/elkhartlake
 
 		device pci 14.0 on	end # USB3.1 xHCI
 
-		device pci 15.1 on	    # I2C1
-			# Enable external RTC chip
-			chip drivers/i2c/rv3028c7
-				register "bus_speed" = "I2C_SPEED_STANDARD"
-				register "set_user_date" = "1"
-				register "user_year" = "04"
-				register "user_month" = "07"
-				register "user_day" = "01"
-				register "user_weekday" = "4"
-				register "bckup_sw_mode" = "BACKUP_SW_LEVEL"
-				register "cap_charge" = "CHARGE_OFF"
-				device i2c 0x52 on end  # RTC RV3028-C7
-			end
-			# Add dummy I2C device to limit BUS speed to 100 kHz in OS
-			chip drivers/i2c/generic
-				register "hid" = ""PRP0001""
-				register "speed" = "I2C_SPEED_STANDARD"
-				device i2c 0x7f on end
-			end
-		end
 		device pci 15.2 on	    # I2C2
 			# Add dummy I2C device to limit BUS speed to 100 kHz in OS
 			chip drivers/i2c/generic

From 093ae8eeaa9c67aa2b275daffb527efe4b2c825a Mon Sep 17 00:00:00 2001
From: Uwe Poeche <uwe.poeche@siemens.com>
Date: Fri, 9 Jan 2026 13:47:05 +0100
Subject: [PATCH 3019/3886] mb/siemens/mc_ehl7: Enable reboot after HW Watchdog
 expiry

Configure the board to perform a hardware reboot when the TCO watchdog
expires. This is achieved by using the default Kconfig option
SOC_INTEL_ELKHARTLAKE_TCO_NO_REBOOT_EN with 'n'.

TEST=Verified in the OS on mc_ehl7:
Checked IO-mapped register 0x408 Bit 0.
Without this patch, the bit is 1 (No Reboot enabled).
With this patch, the bit is 0 (Reboot on expiry enabled).

Change-Id: If3bee9db84c92480762f8a802031d2b01541dbdb
Signed-off-by: Uwe Poeche <uwe.poeche@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90716
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
---
 src/mainboard/siemens/mc_ehl/variants/mc_ehl7/Kconfig | 3 ---
 1 file changed, 3 deletions(-)

diff --git a/src/mainboard/siemens/mc_ehl/variants/mc_ehl7/Kconfig b/src/mainboard/siemens/mc_ehl/variants/mc_ehl7/Kconfig
index 6ce0b48052..6524f4855d 100644
--- a/src/mainboard/siemens/mc_ehl/variants/mc_ehl7/Kconfig
+++ b/src/mainboard/siemens/mc_ehl/variants/mc_ehl7/Kconfig
@@ -36,7 +36,4 @@ config EARLY_PCI_MMIO_BASE
 	depends on NC_FPGA_POST_CODE
 	default 0xfe800000
 
-config SOC_INTEL_ELKHARTLAKE_TCO_NO_REBOOT_EN
-	default y
-
 endif # BOARD_SIEMENS_MC_EHL7

From c09352d58d4d815735ae76594633f0ba62e327c3 Mon Sep 17 00:00:00 2001
From: Jeremy Compostella <jeremy.compostella@intel.com>
Date: Mon, 12 Jan 2026 10:40:02 -0800
Subject: [PATCH 3020/3886] soc/intel/pantherlake: Update PS1 threshold to the
 latest recommendations

Update the PS1 threshold values for VR_DOMAIN_IA, VR_DOMAIN_GT, and
VR_DOMAIN_SA from 20 A to 15 A, following the recommendations in the
Panther Lake H Platform Design Guide (Draft > 2.1). This change ensures
that power state thresholds are consistent with the most recent platform
specifications, improving accuracy and system behavior under varying
power conditions.

TEST=Fatcat device boots to OS.

Change-Id: I358d4d94c3800ff5b658cb875c90ee7409d86377
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90727
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/soc/intel/pantherlake/chipset_ptl.cb | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/src/soc/intel/pantherlake/chipset_ptl.cb b/src/soc/intel/pantherlake/chipset_ptl.cb
index ccd727d6cd..fb78b88659 100644
--- a/src/soc/intel/pantherlake/chipset_ptl.cb
+++ b/src/soc/intel/pantherlake/chipset_ptl.cb
@@ -82,11 +82,11 @@ chip soc/intel/pantherlake
 	register "tdc_time_window_ms[VR_DOMAIN_IA]" = "28000"
 
 	# Set the power state thresholds according to document 813278
-	# Panther Lake H Platform - Design Guide - Rev 2.0
+	# Panther Lake H Platform - Design Guide - Draft > 2.1
 	register "ps1_threshold" = "{
-		[VR_DOMAIN_IA] = 20 * 4,
-		[VR_DOMAIN_GT] = 20 * 4,
-		[VR_DOMAIN_SA] = 20 * 4
+		[VR_DOMAIN_IA] = 15 * 4,
+		[VR_DOMAIN_GT] = 15 * 4,
+		[VR_DOMAIN_SA] = 15 * 4
 	}"
 	register "ps2_threshold" = "{
 		[VR_DOMAIN_IA] = 5 * 4,

From 6fd865f40946fef72a600002e3168295ca884107 Mon Sep 17 00:00:00 2001
From: Patrick Rudolph <patrick.rudolph@9elements.com>
Date: Mon, 30 Jun 2025 13:02:03 +0200
Subject: [PATCH 3021/3886] drivers/amd/ftpm: Add fTPM driver for PSP emulated
 CRB TPMs

The AMD fTPM uses the CRB interface, but doesn't implement all registers
defined in the TCG specification. Add a new driver that deals with the
reduced register set.

The reduced CRB MMIO register space has:
- A START register to ring the doorbell
- An error STATUS register with only one bit
- DMA address and size register for the CRB
- No other status or control registers
- No way to read current locality (assumption is locality 0)
- No interface ID register
- No read only registers

The TPM interface also assumes that the DRTM is always using locality 0.

The fTPM needs to access the SPI flash and this is currently done using
the PSP SMI handler. Thus the fTPM will only operate after SMM has been
set up.

The fTPM needs the PSP directory files type 0x04 and type 0x54. When
the regions are missing or corrupted the fTPM won't be operational.

Based off https://github.com/teslamotors/coreboot/tree/tesla-4.12-amd

TEST=Works on AMD glinda (Fam 1Ah).

This adds the following new log messages:
[DEBUG]  PSP: Querying PSP capabilities...OK
[DEBUG]  PSP: Querying fTPM capabilities... OK
[DEBUG]  PSP: Querying fTPM capabilities... OK
[DEBUG]  TPM: CRB buffer created at 0x7b5ee000
[SPEW ]  fTPM: CRB TPM initialized successfully
[INFO ]  Initialized TPM device fTPM

...

[DEBUG]  PSP: Querying fTPM capabilities... OK
[DEBUG]  TPM2 log created at 0x7b5b1000
[DEBUG]  PSP: Querying fTPM capabilities... OK
[DEBUG]  ACPI:    * TPM2
[DEBUG]  ACPI: added table 4/32, length now 68

Change-Id: I780bdab621228e12b37f3a89868e16bc62a05e7b
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88247
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
---
 src/acpi/acpi.c                               |  13 +-
 .../bsd/include/commonlib/bsd/cbmem_id.h      |   2 +
 src/drivers/amd/ftpm/Kconfig                  |  14 +
 src/drivers/amd/ftpm/Makefile.mk              |   7 +
 src/drivers/amd/ftpm/chip.h                   |   9 +
 src/drivers/amd/ftpm/tis.c                    | 206 ++++++++++++
 src/drivers/amd/ftpm/tpm.c                    | 307 ++++++++++++++++++
 src/drivers/amd/ftpm/tpm.h                    |  31 ++
 src/security/tpm/Kconfig                      |   2 +-
 src/security/tpm/tss/tss.c                    |   2 +-
 src/soc/amd/common/block/psp/psp.c            |   4 +-
 11 files changed, 591 insertions(+), 6 deletions(-)
 create mode 100644 src/drivers/amd/ftpm/Kconfig
 create mode 100644 src/drivers/amd/ftpm/Makefile.mk
 create mode 100644 src/drivers/amd/ftpm/chip.h
 create mode 100644 src/drivers/amd/ftpm/tis.c
 create mode 100644 src/drivers/amd/ftpm/tpm.c
 create mode 100644 src/drivers/amd/ftpm/tpm.h

diff --git a/src/acpi/acpi.c b/src/acpi/acpi.c
index abdcf26160..13728c904d 100644
--- a/src/acpi/acpi.c
+++ b/src/acpi/acpi.c
@@ -27,7 +27,11 @@
 #include <device/device.h>
 #include <device/mmio.h>
 #include <device/pci.h>
+#if CONFIG(AMD_CRB_FTPM)
+#include <drivers/amd/ftpm/tpm.h>
+#else
 #include <drivers/crb/tpm.h>
+#endif
 #include <drivers/uart/pl011.h>
 #include <security/tpm/tss.h>
 #include <string.h>
@@ -260,7 +264,7 @@ static void acpi_create_tpm2(acpi_header_t *header, void *unused)
 	if (tlcl_get_family() != TPM_2)
 		return;
 
-	if (CONFIG(CRB_TPM) && !(CONFIG(SPI_TPM) || CONFIG(I2C_TPM) || CONFIG(MEMORY_MAPPED_TPM)))
+	if ((CONFIG(CRB_TPM) || CONFIG(AMD_CRB_FTPM)) && !(CONFIG(SPI_TPM) || CONFIG(I2C_TPM) || CONFIG(MEMORY_MAPPED_TPM)))
 		if (!crb_tpm_is_active())
 			return;
 
@@ -281,7 +285,12 @@ static void acpi_create_tpm2(acpi_header_t *header, void *unused)
 
 	/* Hard to detect for coreboot. Just set it to 0 */
 	tpm2->platform_class = 0;
-	if (CONFIG(CRB_TPM)) {
+
+	if (CONFIG(AMD_CRB_FTPM) && crb_tpm_is_active()) {
+		/* Must be set to 2 for AMD fTPM Support */
+		tpm2->control_area = crb_tpm_base_address() + 0x40;
+		tpm2->start_method = 2;
+	} else if (CONFIG(CRB_TPM) && crb_tpm_is_active()) {
 		/* Must be set to 7 for CRB Support */
 		tpm2->control_area = crb_tpm_base_address() + 0x40;
 		tpm2->start_method = 7;
diff --git a/src/commonlib/bsd/include/commonlib/bsd/cbmem_id.h b/src/commonlib/bsd/include/commonlib/bsd/cbmem_id.h
index a5cb0a7f8a..0431626f2c 100644
--- a/src/commonlib/bsd/include/commonlib/bsd/cbmem_id.h
+++ b/src/commonlib/bsd/include/commonlib/bsd/cbmem_id.h
@@ -67,6 +67,7 @@
 #define CBMEM_ID_TIMESTAMP	0x54494d45
 #define CBMEM_ID_TPM2_TCG_LOG	0x54504d32 /* TPM log per TPM 2.0 specification */
 #define CBMEM_ID_TPM_PPI	0x54505049
+#define CBMEM_ID_TPM2_CRB	0x43524220
 #define CBMEM_ID_VBOOT_HANDOFF	0x780074f0  /* deprecated */
 #define CBMEM_ID_VBOOT_SEL_REG	0x780074f1  /* deprecated */
 #define CBMEM_ID_VBOOT_WORKBUF	0x78007343
@@ -153,6 +154,7 @@
 	{ CBMEM_ID_TIMESTAMP,		"TIME STAMP " }, \
 	{ CBMEM_ID_TPM2_TCG_LOG,	"TPM2 TCGLOG" }, \
 	{ CBMEM_ID_TPM_PPI,		"TPM PPI    " }, \
+	{ CBMEM_ID_TPM2_CRB,		"TPM CRB    " }, \
 	{ CBMEM_ID_VBOOT_HANDOFF,	"VBOOT      " }, \
 	{ CBMEM_ID_VBOOT_SEL_REG,	"VBOOT SEL  " }, \
 	{ CBMEM_ID_VBOOT_WORKBUF,	"VBOOT WORK " }, \
diff --git a/src/drivers/amd/ftpm/Kconfig b/src/drivers/amd/ftpm/Kconfig
new file mode 100644
index 0000000000..9e9c382572
--- /dev/null
+++ b/src/drivers/amd/ftpm/Kconfig
@@ -0,0 +1,14 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
+config AMD_CRB_FTPM
+	bool
+	default n
+	depends on !CRB_TPM
+	depends on SOC_AMD_COMMON_BLOCK_PSP_GEN2
+	# The fTPM needs to access the SPI flash when ROM Armor
+	# is not being used, thus select SOC_AMD_COMMON_BLOCK_PSP_SMI.
+	select SOC_AMD_COMMON_BLOCK_PSP_SMI
+	help
+	  Mainboard has AMD fTPM with Command Response Buffer support.
+	  The fTPM is based on the CRB interface as defined by TCG,
+	  but with reduced set of registers being implemented.
diff --git a/src/drivers/amd/ftpm/Makefile.mk b/src/drivers/amd/ftpm/Makefile.mk
new file mode 100644
index 0000000000..87f649b67c
--- /dev/null
+++ b/src/drivers/amd/ftpm/Makefile.mk
@@ -0,0 +1,7 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
+ifeq ($(CONFIG_AMD_CRB_FTPM),y)
+# Currently depends on SOC_AMD_COMMON_BLOCK_PSP_SMI, that means
+# fTPM is only accepting commands after SMM has been set up.
+ramstage-y += tis.c tpm.c
+endif
diff --git a/src/drivers/amd/ftpm/chip.h b/src/drivers/amd/ftpm/chip.h
new file mode 100644
index 0000000000..7e69509269
--- /dev/null
+++ b/src/drivers/amd/ftpm/chip.h
@@ -0,0 +1,9 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef DRIVERS_AMD_FTPM_CHIP_H
+#define DRIVERS_AMD_FTPM_CHIP_H
+
+struct drivers_amd_ftpm_config {
+};
+
+#endif /* DRIVERS_AMD_FTPM_CHIP_H */
diff --git a/src/drivers/amd/ftpm/tis.c b/src/drivers/amd/ftpm/tis.c
new file mode 100644
index 0000000000..0f0dd5c899
--- /dev/null
+++ b/src/drivers/amd/ftpm/tis.c
@@ -0,0 +1,206 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <arch/mmio.h>
+#include <console/console.h>
+#include <security/tpm/tis.h>
+#include <acpi/acpigen.h>
+#include <device/device.h>
+#include <security/tpm/tss.h>
+#include <endian.h>
+#include <smbios.h>
+#include <string.h>
+
+#include "tpm.h"
+#include "chip.h"
+
+static const char *tis_get_dev_name(void)
+{
+	return "fTPM";
+}
+
+static tpm_result_t crb_tpm_sendrecv(const uint8_t *sendbuf, size_t sbuf_size, uint8_t *recvbuf,
+				     size_t *rbuf_len)
+{
+	int len = crb_tpm_process_command(sendbuf, sbuf_size, recvbuf, *rbuf_len);
+
+	if (len <= 0)
+		return TPM_CB_FAIL;
+
+	*rbuf_len = len;
+
+	return TPM_SUCCESS;
+}
+
+tis_sendrecv_fn crb_tis_probe(enum tpm_family *family)
+{
+	/* Wake TPM up (if necessary) */
+	if (crb_tpm_init())
+		return NULL;
+
+	/* CRB interface exists only in TPM2 */
+	if (family != NULL)
+		*family = TPM_2;
+
+	printk(BIOS_INFO, "Initialized TPM device %s\n", tis_get_dev_name());
+
+	return &crb_tpm_sendrecv;
+}
+
+static void tpm_start_func0_cb(void *arg)
+{
+	/* Function 1. */
+	acpigen_write_return_singleton_buffer(0x3);
+}
+static void tpm_start_func1_cb(void *arg)
+{
+	/* Just return success. fTPM is already operational. */
+	acpigen_write_return_byte(0);
+}
+
+static void (*tpm_start_callbacks[])(void *) = {
+	tpm_start_func0_cb,
+	tpm_start_func1_cb,
+};
+
+#define TPM_START_UUID   "6bbf6cab-5463-4714-b7cd-f0203c0368d4"
+
+static void crb_tpm_fill_ssdt(const struct device *dev)
+{
+	assert(dev->path.type == DEVICE_PATH_MMIO);
+	assert(dev->path.mmio.addr == crb_tpm_base_address());
+
+	/* Device */
+	acpigen_write_scope("\\_SB");
+	acpigen_write_device(acpi_device_name(dev));
+
+	acpigen_write_name_string("_HID", "MSFT0101");
+	acpigen_write_name_string("_CID", "MSFT0101");
+
+	acpi_device_write_uid(dev);
+
+	if (crb_tpm_is_active())
+		acpigen_write_STA(ACPI_STATUS_DEVICE_ALL_ON);
+	else
+		acpigen_write_STA(ACPI_STATUS_DEVICE_ALL_OFF);
+
+	/* Resources */
+	acpigen_write_name("_CRS");
+	acpigen_write_resourcetemplate_header();
+	acpigen_write_mem32fixed(1, read32(CRB_REG(CRB_REG_CMD_ADDR)),
+				 read32(CRB_REG(CRB_REG_CMD_SIZE)));
+	acpigen_write_mem32fixed(1, read32(CRB_REG(CRB_REG_RESP_ADDR)),
+				 read32(CRB_REG(CRB_REG_RESP_SIZE)));
+	acpigen_write_resourcetemplate_footer();
+
+	/*
+	 * _DSM method
+	 */
+	struct dsm_uuid ids[] = {
+		DSM_UUID(TPM_START_UUID, tpm_start_callbacks,
+			ARRAY_SIZE(tpm_start_callbacks), NULL),
+	};
+
+	acpigen_write_dsm_uuid_arr(ids, ARRAY_SIZE(ids));
+
+	acpigen_pop_len(); /* Device */
+	acpigen_pop_len(); /* Scope */
+}
+
+static const char *crb_tpm_acpi_name(const struct device *dev)
+{
+	return "TPM2";
+}
+
+#if CONFIG(GENERATE_SMBIOS_TABLES)
+static tpm_result_t tpm_get_cap(uint32_t property, uint32_t *value)
+{
+	TPMS_CAPABILITY_DATA cap_data;
+	int i;
+	tpm_result_t rc;
+
+	if (!value)
+		return TPM_CB_INVALID_ARG;
+
+	rc = tlcl2_get_capability(TPM_CAP_TPM_PROPERTIES, property, 1, &cap_data);
+
+	if (rc)
+		return rc;
+
+	for (i = 0; i < cap_data.data.tpmProperties.count; i++) {
+		if (cap_data.data.tpmProperties.tpmProperty[i].property == property) {
+			*value = cap_data.data.tpmProperties.tpmProperty[i].value;
+			return TPM_SUCCESS;
+		}
+	}
+
+	return TPM_CB_FAIL;
+}
+
+static int smbios_write_type43_tpm(struct device *dev, int *handle, unsigned long *current)
+{
+	uint32_t tpm_manuf, tpm_family;
+	uint32_t fw_ver1, fw_ver2;
+	uint8_t major_spec_ver, minor_spec_ver;
+
+	/* Vendor ID is the value returned by TPM2_GetCapabiltiy TPM_PT_MANUFACTURER */
+	if (tpm_get_cap(TPM_PT_MANUFACTURER, &tpm_manuf)) {
+		printk(BIOS_DEBUG, "TPM2_GetCap TPM_PT_MANUFACTURER failed\n");
+		return 0;
+	}
+
+	tpm_manuf = be32toh(tpm_manuf);
+
+	if (tpm_get_cap(TPM_PT_FIRMWARE_VERSION_1, &fw_ver1)) {
+		printk(BIOS_DEBUG, "TPM2_GetCap TPM_PT_FIRMWARE_VERSION_1 failed\n");
+		return 0;
+	}
+
+	if (tpm_get_cap(TPM_PT_FIRMWARE_VERSION_2, &fw_ver2)) {
+		printk(BIOS_DEBUG, "TPM2_GetCap TPM_PT_FIRMWARE_VERSION_2 failed\n");
+		return 0;
+	}
+
+	if (tpm_get_cap(TPM_PT_FAMILY_INDICATOR, &tpm_family)) {
+		printk(BIOS_DEBUG, "TPM2_GetCap TPM_PT_FAMILY_INDICATOR failed\n");
+		return 0;
+	}
+
+	tpm_family = be32toh(tpm_family);
+
+	if (!strncmp((char *)&tpm_family, "2.0", 4)) {
+		major_spec_ver = 2;
+		minor_spec_ver = 0;
+	} else {
+		printk(BIOS_ERR, "%s: Invalid TPM family\n", __func__);
+		return 0;
+	}
+
+	return smbios_write_type43(current, handle, tpm_manuf, major_spec_ver, minor_spec_ver,
+				   fw_ver1, fw_ver2, tis_get_dev_name(),
+				   SMBIOS_TPM_DEVICE_CHARACTERISTICS_NOT_SUPPORTED, 0);
+}
+#endif
+
+static struct device_operations __maybe_unused amd_crb_ops = {
+	.read_resources = noop_read_resources,
+	.set_resources = noop_set_resources,
+#if CONFIG(HAVE_ACPI_TABLES)
+	.acpi_name = crb_tpm_acpi_name,
+	.acpi_fill_ssdt = crb_tpm_fill_ssdt,
+#endif
+#if CONFIG(GENERATE_SMBIOS_TABLES)
+	.get_smbios_data	= smbios_write_type43_tpm,
+#endif
+};
+
+static void enable_dev(struct device *dev)
+{
+#if !DEVTREE_EARLY
+	dev->ops = &amd_crb_ops;
+#endif
+}
+
+struct chip_operations drivers_amd_ftpm_ops = {
+	.name = "AMD CRB fTPM",
+	.enable_dev = enable_dev
+};
diff --git a/src/drivers/amd/ftpm/tpm.c b/src/drivers/amd/ftpm/tpm.c
new file mode 100644
index 0000000000..e5ab0dea39
--- /dev/null
+++ b/src/drivers/amd/ftpm/tpm.c
@@ -0,0 +1,307 @@
+/* SPDX-License-Identifier: BSD-3-Clause */
+/*
+ * This is a driver for the AMD fTPM CRB Interface.
+ *
+ * The AMD fTPM uses the CRB interface, but doesn't implement all registers
+ * defined in the TCG specification.
+ *
+ * The reduced CRB MMIO register space has:
+ * - A START register to ring the doorbell
+ * - An error STATUS register with only one bit
+ * - DMA address and size register for the CRB
+ * - No other status or control registers
+ * - No way to read current locality (assumption is locality 0)
+ * - No interface ID register
+ * - No read only registers
+ *
+ * The TPM interface also assumes that the DRTM is always using locality 0.
+ *
+ * The fTPM needs to access the SPI flash and this is currently done using
+ * the PSP SMI handler. Thus the fTPM will only operate after SMM has been
+ * set up.
+ *
+ * The fTPM needs the PSP directory files type 0x04 and type 0x54. When
+ * the regions are missing or corrupted the fTPM won't be operational.
+ */
+
+#include <timer.h>
+#include <amdblocks/psp.h>
+#include <amdblocks/reset.h>
+#include <cbmem.h>
+#include <console/console.h>
+#include <commonlib/region.h>
+#include <device/mmio.h>
+#include <fmap.h>
+#include <string.h>
+
+#include "tpm.h"
+
+/* FMAP regions used */
+#define FMAP_NAME_PSP_NVRAM                 "PSP_NVRAM"
+#define FMAP_NAME_PSP_RPMC_NVRAM            "PSP_RPMC_NVRAM"
+
+/* Size of DMA buffer in DRAM */
+#define FTPM_CRB_SIZE                  (4 * 4096)
+
+/* Index of Count field in TPM response buffer */
+#define TPM_RSP_SIZE_BYTE 2
+
+static struct control_area {
+	uint32_t start;
+	uint32_t command_size;
+	void *command_bfr;
+	uint32_t response_size;
+	void *response_bfr;
+} control_area;
+
+/* Read Control Area Structure back  */
+static void crb_read_control_area(void)
+{
+	control_area.command_size = read32(CRB_REG(CRB_REG_CMD_SIZE));
+	control_area.command_bfr =
+		(void *)(uintptr_t)read64(CRB_REG(CRB_REG_CMD_ADDR));
+	control_area.response_size = read32(CRB_REG(CRB_REG_RESP_SIZE));
+	control_area.response_bfr =
+		(void *)(uintptr_t)read64(CRB_REG(CRB_REG_RESP_ADDR));
+}
+
+/* Wait for reg to be expected value */
+static tpm_result_t crb_wait_for_reg32(const void *addr,
+				       uint32_t timeout_ms,
+				       uint32_t mask,
+				       uint32_t expected_value)
+{
+	uint32_t reg_value;
+	struct stopwatch sw;
+
+	// Set up a timer which breaks the loop after timeout
+	stopwatch_init_msecs_expire(&sw, timeout_ms);
+
+	while (1) {
+		// Now check if the TPM is in IDLE mode
+		reg_value = read32(addr);
+
+		if ((reg_value & mask) == expected_value)
+			return TPM_SUCCESS;
+
+		if (stopwatch_expired(&sw)) {
+			printk(BIOS_ERR,
+			       "fTPM: Timed out with reg_value: %08x, mask: %08x, expected: %08x\n",
+			       reg_value, mask, expected_value);
+			return TPM_CB_TIMEOUT;
+		}
+	}
+}
+
+static int erase_region(const char *name)
+{
+	struct region_device store;
+
+	if (fmap_locate_area_as_rdev_rw(name, &store)) {
+		printk(BIOS_ERR, "fTPM: Unable to find FMAP region %s\n", name);
+		return -1;
+	}
+
+	if (rdev_eraseat(&store, 0, region_device_sz(&store))
+	    != region_device_sz(&store))
+		return -1;
+
+	printk(BIOS_NOTICE, "fTPM: Erased FMAP region %s\n", name);
+
+	return 0;
+}
+
+/*
+ * crb_tpm_init
+ *
+ * Even though the TPM does not need an initialization we check
+ * if the TPM responds and is in IDLE mode, which should be the
+ * normal bring up mode.
+ */
+tpm_result_t crb_tpm_init(void)
+{
+	bool psp_rpmc_nvram, psp_nvram, psp_dir;
+
+	/*
+	 * When recovery is required psp_ftpm_is_active() always returns false.
+	 * Thus handle recovery before checking if fTPM is usable.
+	 */
+	psp_ftpm_needs_recovery(&psp_rpmc_nvram, &psp_nvram, &psp_dir);
+
+	if (psp_rpmc_nvram) {
+		if (erase_region(FMAP_NAME_PSP_RPMC_NVRAM))
+			psp_rpmc_nvram = false;	/* Skip reset if erase failed */
+	}
+
+	if (psp_nvram) {
+		if (erase_region(FMAP_NAME_PSP_NVRAM))
+			psp_nvram = false;	/* Skip reset if erase failed */
+	}
+
+	if (psp_rpmc_nvram || psp_nvram) {
+		printk(BIOS_DEBUG, "fTPM: Reset to recover fTPM...\n");
+		cold_reset();
+	}
+
+	if (psp_dir) {
+		printk(BIOS_ERR, "fTPM: fTPM driver corrupted. Need FW update.\n");
+		return CB_ERR;
+	}
+
+	if (!psp_ftpm_is_active())
+		return CB_ERR_NOT_IMPLEMENTED;
+
+	if (ENV_HAS_CBMEM) {
+		/* setting up fTPM communication buffers in cbmem */
+		const struct cbmem_entry *entry;
+		void *buf;
+		uint32_t length = 2 * FTPM_CRB_SIZE;
+
+		/* Only allocate once */
+		entry = cbmem_entry_find(CBMEM_ID_TPM2_CRB);
+		if (entry) {
+			buf = cbmem_entry_start(entry);
+			length = cbmem_entry_size(entry);
+		} else {
+			buf = cbmem_add(CBMEM_ID_TPM2_CRB, length);
+			if (!buf) {
+				printk(BIOS_ERR, "fTPM: CBMEM CRB buffer allocation failed\n");
+				return CB_ERR;
+			}
+			printk(BIOS_DEBUG, "fTPM: CRB buffer created at %p\n", buf);
+			memset(buf, 0, length);
+		}
+
+		/* Set command/response buffers in control area */
+		write32(CRB_REG(CRB_REG_CMD_SIZE), FTPM_CRB_SIZE);
+		write64(CRB_REG(CRB_REG_CMD_ADDR), (uintptr_t)buf);
+		write32(CRB_REG(CRB_REG_RESP_SIZE), FTPM_CRB_SIZE);
+		write64(CRB_REG(CRB_REG_RESP_ADDR), (uintptr_t)buf + FTPM_CRB_SIZE);
+
+		/*
+		 * The OS will read the CRB registers to find the communication
+		 * buffers. No need to advertise it in ACPI.
+		 */
+	}
+
+	/* Read back control area structure */
+	crb_read_control_area();
+
+	/* Opt out when CRB hasn't been set up yet */
+	if (!control_area.command_size || !control_area.response_size)
+		return CB_ERR_NOT_IMPLEMENTED;
+
+	/* Good to go. */
+	printk(BIOS_SPEW, "fTPM: CRB TPM initialized successfully\n");
+
+	return TPM_SUCCESS;
+}
+
+/*
+ * crb_tpm_process_command
+ *
+ * Transfers data to and from the fTPM.
+ *
+ */
+size_t crb_tpm_process_command(const void *tpm2_command, size_t command_size,
+			       void *tpm2_response, size_t max_response)
+{
+	uint32_t rsp_size;
+	tpm_result_t rc;
+
+	if (!control_area.response_size || !control_area.command_size) {
+		printk(BIOS_ERR, "%s: Control area wasn't set up yet\n", __func__);
+		return -1;
+	}
+	if (command_size > control_area.command_size) {
+		printk(BIOS_ERR, "%s: Command size is too big: %zu > %u.\n",
+		       __func__, command_size, control_area.command_size);
+		return -1;
+	}
+
+	/* Check if CMD bit is cleared. */
+	rc = crb_wait_for_reg32(CRB_REG(CRB_REG_START), 250, CRB_REG_START_START, 0x0);
+	if (rc) {
+		printk(BIOS_ERR, "%s: Cmd Bit didn't clear\n", __func__);
+		return -1;
+	}
+
+	/* Write to Command Buffer */
+	memcpy(control_area.command_bfr, tpm2_command, command_size);
+
+	/* Clear Response buffer */
+	memset(control_area.response_bfr, 0, control_area.response_size);
+
+	/* Set Response size */
+	write32(CRB_REG(CRB_REG_RESP_SIZE), control_area.response_size);
+
+	/* Write Start Bit */
+	write8(CRB_REG(CRB_REG_START), CRB_REG_START_START);
+
+	/* Poll for Response */
+	rc = crb_wait_for_reg32(CRB_REG(CRB_REG_START), 3500, CRB_REG_START_START, 0);
+	if (rc) {
+		printk(BIOS_DEBUG, "%s: Timeout waiting for CMD processing\n", __func__);
+		return -1;
+	}
+
+	/* Check for errors */
+	rc = read32(CRB_REG(CRB_REG_STATUS));
+	if (rc & CRB_REG_STATUS_ERROR) {
+		printk(BIOS_DEBUG, "fTPM Error (%#x): Command errored.\n", rc);
+		return -1;
+	}
+
+	/* Get Response Length. Seems to be static on some platforms. */
+	uint32_t length = read32(CRB_REG(CRB_REG_RESP_SIZE));
+	assert(length <= control_area.response_size);
+
+	/* Response has to have at least 6 bytes */
+	if (length < 6) {
+		printk(BIOS_DEBUG, "fTPM Error: Invalid response length: %u\n", length);
+		return -1;
+	}
+
+	/* Get actual size from TPM packet */
+	memcpy(&rsp_size, control_area.response_bfr + TPM_RSP_SIZE_BYTE, sizeof(rsp_size));
+	rsp_size = be32_to_cpu(rsp_size);
+	if ((size_t)rsp_size > max_response) {
+		printk(BIOS_DEBUG, "fTPM Error: Response wouldn't fit into target buffer: %u > %zu\n",
+		      rsp_size, max_response);
+		return -1;
+	}
+
+	/* Copy Response */
+	length = MIN(length, MIN(max_response, rsp_size));
+	memcpy(tpm2_response, control_area.response_bfr, length);
+
+	return length;
+}
+
+/*
+ * crb_tpm_is_active
+ *
+ * Checks that CRB interface is available and active.
+ */
+bool crb_tpm_is_active(void)
+{
+	if (!psp_ftpm_is_active())
+		return false;
+
+	/* Read back control area structure */
+	crb_read_control_area();
+
+	/* Validate fields */
+	if (!control_area.command_size || !control_area.response_size ||
+	    !control_area.command_bfr || !control_area.response_bfr ||
+	    (control_area.command_bfr == (void *)-1) ||
+	    (control_area.response_bfr == (void *)-1))
+		return false;
+
+	return true;
+}
+
+uintptr_t crb_tpm_base_address(void)
+{
+	return psp_ftpm_base_address();
+}
diff --git a/src/drivers/amd/ftpm/tpm.h b/src/drivers/amd/ftpm/tpm.h
new file mode 100644
index 0000000000..aaae99eb34
--- /dev/null
+++ b/src/drivers/amd/ftpm/tpm.h
@@ -0,0 +1,31 @@
+/* SPDX-License-Identifier: BSD-3-Clause */
+/* This is a driver for a Command Response Buffer Interface
+ * as found on AMD fTPMs. It only implements a small subset
+ * of the registers defined in the TCG specification.
+ */
+
+#include <amdblocks/psp.h>
+#include <security/tpm/tis.h>
+#include <security/tpm/tss_errors.h>
+
+/* CRB hardware registers */
+#define CRB_REG_STATUS			0x44
+#define  CRB_REG_STATUS_ERROR		0x01
+#define CRB_REG_START			0x4C
+#define  CRB_REG_START_START		0x01
+#define CRB_REG_CMD_SIZE		0x58
+#define CRB_REG_CMD_ADDR		0x5C
+#define CRB_REG_RESP_SIZE		0x64
+#define CRB_REG_RESP_ADDR		0x68
+
+/* address of locality 0 (CRB) */
+#define CRB_REG(REG) ((void *)(uintptr_t)(psp_ftpm_base_address() + (REG)))
+
+tpm_result_t crb_tpm_init(void);
+size_t crb_tpm_process_command(const void *tpm2_command, size_t command_size,
+			       void *tpm2_response, size_t max_response);
+bool crb_tpm_is_active(void);
+
+tis_sendrecv_fn crb_tis_probe(enum tpm_family *family);
+
+uintptr_t crb_tpm_base_address(void);
diff --git a/src/security/tpm/Kconfig b/src/security/tpm/Kconfig
index c8eb446839..a53163dd05 100644
--- a/src/security/tpm/Kconfig
+++ b/src/security/tpm/Kconfig
@@ -22,7 +22,7 @@ config TPM1
 
 config TPM2
 	bool "TPM 2.0"
-	depends on I2C_TPM || MEMORY_MAPPED_TPM || SPI_TPM || CRB_TPM
+	depends on I2C_TPM || MEMORY_MAPPED_TPM || SPI_TPM || CRB_TPM || AMD_CRB_FTPM
 	default y if MAINBOARD_HAS_TPM2
 	help
 	  Select this option if your TPM uses the newer TPM 2.0 protocol.
diff --git a/src/security/tpm/tss/tss.c b/src/security/tpm/tss/tss.c
index 8e52de73e9..f4deb2d633 100644
--- a/src/security/tpm/tss/tss.c
+++ b/src/security/tpm/tss/tss.c
@@ -29,7 +29,7 @@ tpm_result_t tlcl_lib_init(void)
 	init_done = true;
 
 	tlcl_tis_sendrecv = NULL;
-	if (CONFIG(CRB_TPM))
+	if (CONFIG(CRB_TPM) || CONFIG(AMD_CRB_FTPM))
 		tlcl_tis_sendrecv = crb_tis_probe(&tlcl_tpm_family);
 	if (CONFIG(MEMORY_MAPPED_TPM) && tlcl_tis_sendrecv == NULL)
 		tlcl_tis_sendrecv = pc80_tis_probe(&tlcl_tpm_family);
diff --git a/src/soc/amd/common/block/psp/psp.c b/src/soc/amd/common/block/psp/psp.c
index 9ad04e1ce6..98eb0f9e84 100644
--- a/src/soc/amd/common/block/psp/psp.c
+++ b/src/soc/amd/common/block/psp/psp.c
@@ -64,7 +64,7 @@ enum cb_err psp_get_ftpm_capabilties(uint32_t *capabilities)
 		},
 	};
 
-	printk(BIOS_DEBUG, "PSP: Querying fTPM capabilities...");
+	printk(BIOS_DEBUG, "PSP: Querying fTPM capabilities... ");
 
 	cmd_status = send_psp_command(MBOX_BIOS_CMD_PSP_FTPM_QUERY, &buffer);
 
@@ -87,7 +87,7 @@ enum cb_err psp_get_hsti_state(uint32_t *state)
 		},
 	};
 
-	printk(BIOS_DEBUG, "PSP: Querying HSTI state...");
+	printk(BIOS_DEBUG, "PSP: Querying HSTI state... ");
 
 	cmd_status = send_psp_command(MBOX_BIOS_CMD_HSTI_QUERY, &buffer);
 

From b741e2274e4b3dd677ee55c4875c420cc8d3a71a Mon Sep 17 00:00:00 2001
From: Patrick Rudolph <patrick.rudolph@9elements.com>
Date: Wed, 8 Oct 2025 12:36:30 +0200
Subject: [PATCH 3022/3886] acpi: Add enums for TPM2 start method

Based on the "TCG ACPI Specification" Version 1.3 published 2021.
Add an enum for the ACPI start methods and use it instead of hardcoding
various numbers in plain code.

Change-Id: I8b66527ee7417e231fe52e0a609b8c100de522b0
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89458
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
---
 src/acpi/acpi.c         |  9 +++------
 src/include/acpi/acpi.h | 14 ++++++++++++++
 2 files changed, 17 insertions(+), 6 deletions(-)

diff --git a/src/acpi/acpi.c b/src/acpi/acpi.c
index 13728c904d..94b6309261 100644
--- a/src/acpi/acpi.c
+++ b/src/acpi/acpi.c
@@ -287,17 +287,14 @@ static void acpi_create_tpm2(acpi_header_t *header, void *unused)
 	tpm2->platform_class = 0;
 
 	if (CONFIG(AMD_CRB_FTPM) && crb_tpm_is_active()) {
-		/* Must be set to 2 for AMD fTPM Support */
 		tpm2->control_area = crb_tpm_base_address() + 0x40;
-		tpm2->start_method = 2;
+		tpm2->start_method = ACPI_TPM2_SM_ACPI_START;
 	} else if (CONFIG(CRB_TPM) && crb_tpm_is_active()) {
-		/* Must be set to 7 for CRB Support */
 		tpm2->control_area = crb_tpm_base_address() + 0x40;
-		tpm2->start_method = 7;
+		tpm2->start_method = ACPI_TPM2_SM_CRB;
 	} else {
-		/* Must be set to 0 for FIFO interface support */
 		tpm2->control_area = 0;
-		tpm2->start_method = 6;
+		tpm2->start_method = ACPI_TPM2_SM_MMIO_TIS;
 	}
 	memset(tpm2->msp, 0, sizeof(tpm2->msp));
 
diff --git a/src/include/acpi/acpi.h b/src/include/acpi/acpi.h
index 87c99a1eb3..ac00050031 100644
--- a/src/include/acpi/acpi.h
+++ b/src/include/acpi/acpi.h
@@ -243,6 +243,20 @@ typedef struct acpi_tcpa {
 	u64 lasa;
 } __packed acpi_tcpa_t;
 
+/* TCG ACPI Specification "Table 8: Start Method values for ACPI table for TPM 2.0" */
+enum acpi_tpm2_start_methods {
+	ACPI_TPM2_SM_NOT_ALLOWED = 0,
+	ACPI_TPM2_SM_LEGACY,
+	ACPI_TPM2_SM_ACPI_START,
+	ACPI_TPM2_SM_MMIO_TIS = 6,
+	ACPI_TPM2_SM_CRB,
+	ACPI_TPM2_SM_CRB_AND_ACPI_START,
+	ACPI_TPM2_SM_CRB_AND_ARM_SECURE_MONITOR = 11,
+	ACPI_TPM2_SM_FIFO_I2C,
+	ACPI_TPM2_SM_RESERVED_MMIO0,
+	ACPI_TPM2_SM_RESERVED_MMIO1,
+};
+
 typedef struct acpi_tpm2 {
 	acpi_header_t header;
 	u16 platform_class;

From 96b4754c35b2478602feef1df01069935726dc51 Mon Sep 17 00:00:00 2001
From: Bora Guvendik <bora.guvendik@intel.com>
Date: Wed, 7 Jan 2026 13:29:10 -0800
Subject: [PATCH 3023/3886] soc/intel: Add CPU ID support for Nova Lake
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Add CPUID definition and CPU table entry for Intel Nova Lake processor
(CPUID 0x300f30). This enables basic CPU initialization and
multiprocessor support for Nova Lake platforms

Reference:
- Nova Lake External Design Specification (EDS) Volume 1 (#844316)

BUG=none

Change-Id: Iea89ebfa8bae3448edfb3b757443ec9902cede5e
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90695
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Reviewed-by: Kim, Wonkyu <wonkyu.kim@intel.com>
---
 src/include/cpu/intel/cpu_ids.h          | 1 +
 src/soc/intel/common/block/cpu/mp_init.c | 1 +
 2 files changed, 2 insertions(+)

diff --git a/src/include/cpu/intel/cpu_ids.h b/src/include/cpu/intel/cpu_ids.h
index ada3bfd216..f43287226a 100644
--- a/src/include/cpu/intel/cpu_ids.h
+++ b/src/include/cpu/intel/cpu_ids.h
@@ -95,5 +95,6 @@
 #define CPUID_SNOWRIDGE_B1		0x80665
 #define CPUID_SNOWRIDGE_C0		0x80667
 #define CPUID_WILDCATLAKE		0xd0650
+#define CPUID_NOVALAKE			0x300f30
 
 #endif /* CPU_INTEL_CPU_IDS_H */
diff --git a/src/soc/intel/common/block/cpu/mp_init.c b/src/soc/intel/common/block/cpu/mp_init.c
index fdee38d254..dd8a31592e 100644
--- a/src/soc/intel/common/block/cpu/mp_init.c
+++ b/src/soc/intel/common/block/cpu/mp_init.c
@@ -32,6 +32,7 @@ static struct device_operations cpu_dev_ops = {
 };
 
 static const struct cpu_device_id cpu_table[] = {
+	{ X86_VENDOR_INTEL, CPUID_NOVALAKE, CPUID_ALL_STEPPINGS_MASK },
 	{ X86_VENDOR_INTEL, CPUID_WILDCATLAKE, CPUID_ALL_STEPPINGS_MASK },
 	{ X86_VENDOR_INTEL, CPUID_PANTHERLAKE, CPUID_ALL_STEPPINGS_MASK },
 	{ X86_VENDOR_INTEL, CPUID_LUNARLAKE_A0_1, CPUID_EXACT_MATCH_MASK },

From d62764df8779abd2a7158659849a27b4e22bcd4a Mon Sep 17 00:00:00 2001
From: Cliff Huang <cliff.huang@intel.com>
Date: Wed, 7 Jan 2026 09:54:21 -0800
Subject: [PATCH 3024/3886] soc/intel/common/block/p2sb: Add SSDT function for
 SoC-specific features
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Add weak function to fill SSDT for SoC-specific P2SB extensions. SoCs
can implement this function to fill additional P2SB-related ACPI
objects. For instance, a SoC might include the IOST ACPI interface that
uses P2SB and enable it via SSDT for debug purposes at the OS level.

BUG=none
TEST=This change cannot be tested in isolation as it only adds an empty
weak function. Testing requires SoCs to implement the function. Add the
necessary code with the same function name in the SoC to generate ACPI
objects and examine the SSDT for changes after boot.

Signed-off-by: Cliff Huang <cliff.huang@intel.com>
Change-Id: I352f13b9b05dc4b61608a33c76946883bf0d3de3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90691
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
---
 src/soc/intel/common/block/include/intelblocks/p2sb.h | 8 ++++++++
 src/soc/intel/common/block/p2sb/p2sb.c                | 8 ++++++++
 2 files changed, 16 insertions(+)

diff --git a/src/soc/intel/common/block/include/intelblocks/p2sb.h b/src/soc/intel/common/block/include/intelblocks/p2sb.h
index e587a4d25e..a431f617c7 100644
--- a/src/soc/intel/common/block/include/intelblocks/p2sb.h
+++ b/src/soc/intel/common/block/include/intelblocks/p2sb.h
@@ -3,6 +3,7 @@
 #ifndef SOC_INTEL_COMMON_BLOCK_P2SB_H
 #define SOC_INTEL_COMMON_BLOCK_P2SB_H
 
+#include <device/device.h>
 #include <stddef.h>
 #include <stdint.h>
 
@@ -68,4 +69,11 @@ void p2sb_set_ioapic_bdf(union p2sb_bdf bdf);
  */
 void p2sb_soc_get_sb_mask(uint32_t *ep_mask, size_t count);
 
+/*
+ * SoC might define this function to fill additional P2SB-related ACPI objects.
+ * For instance, the SoC might include the IOST ACPI interface to use P2SB and
+ * enable it via SSDT for debug purposes at the OS level.
+ */
+void soc_fill_p2sb_ssdt(const struct device *dev);
+
 #endif	/* SOC_INTEL_COMMON_BLOCK_P2SB_H */
diff --git a/src/soc/intel/common/block/p2sb/p2sb.c b/src/soc/intel/common/block/p2sb/p2sb.c
index fea3103026..194c18f86a 100644
--- a/src/soc/intel/common/block/p2sb/p2sb.c
+++ b/src/soc/intel/common/block/p2sb/p2sb.c
@@ -130,10 +130,18 @@ static void read_resources(struct device *dev)
 	mmio_range(dev, PCI_BASE_ADDRESS_0, P2SB_BAR, P2SB_SIZE);
 }
 
+__weak void soc_fill_p2sb_ssdt(const struct device *dev)
+{
+	/* no-op */
+}
+
 const struct device_operations p2sb_ops = {
 	.read_resources		= read_resources,
 	.set_resources		= noop_set_resources,
 	.ops_pci		= &pci_dev_ops_pci,
+#if CONFIG(HAVE_ACPI_TABLES)
+	.acpi_fill_ssdt		= soc_fill_p2sb_ssdt,
+#endif
 };
 
 static const unsigned short pci_device_ids[] = {

From 52aeb078ce69479c0efa852ba9ee7c97a09dfbc7 Mon Sep 17 00:00:00 2001
From: Cliff Huang <cliff.huang@intel.com>
Date: Wed, 19 Nov 2025 17:50:39 -0800
Subject: [PATCH 3025/3886] soc/intel/common/acpi: Add IOST device
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Add ACPI device for Intel's IO Self-Testing Software (IOST), which is an
OS tool for performing electrical margining analysis on USB4 Host and
Device Routers, DP2.1 displays, memory, UFS, and PCIe Gen4+ devices.
This ACPI device provides the necessary P2SB access interface to enable
IOST to interact with hardware registers for comprehensive IO testing
and validation. The ASL file should be included in the SoC's
southbridge.asl.

BUG=none
TEST=Build coreboot with this ASL file included in the SoC's
southbridge.asl. Boot to OS and verify IOST objects appear correctly in
the DSDT tables.

Signed-off-by: Cliff Huang <cliff.huang@intel.com>
Change-Id: I9417da8322931c2afbf75aa9062bceb52b8320d6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90128
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
---
 src/soc/intel/common/acpi/iost.asl | 81 ++++++++++++++++++++++++++++++
 1 file changed, 81 insertions(+)
 create mode 100644 src/soc/intel/common/acpi/iost.asl

diff --git a/src/soc/intel/common/acpi/iost.asl b/src/soc/intel/common/acpi/iost.asl
new file mode 100644
index 0000000000..51d934ca7a
--- /dev/null
+++ b/src/soc/intel/common/acpi/iost.asl
@@ -0,0 +1,81 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ * Device: Intel's IO Self-Testing Software (IOST)
+ * NOTE: The IOSE Name object is used to enable IOST. It is set to 0 by default,
+ * and its value can be updated in the SSDT.
+ */
+Device (IOST)
+{
+	//
+	// Intel IO Self Testing Device
+	//
+	Name (_UID, "IOST")
+	Name (_HID, "IOS0001")
+	Name (IVER, 0x00010000)
+	Name (IOSE, 0x00)
+	Method (_STA, 0, NotSerialized)
+	{
+		If (IOSE > Zero) {
+			Return (0xf)
+		}
+		Return (Zero)
+	}
+
+	/*
+	 * _DSM Device Specific Method
+	 *
+	 * Arg0: UUID : 893f00a6-660c-494e-bcfd-3043f4fb67c0
+	 * Arg1: Integer Revision Level
+	 * Arg2: Integer Function Index (0 = Return Supported Functions)
+	 * Arg3: Package Parameters
+	 */
+	Method (_DSM, 4, Serialized)
+	{
+		If ( (IOSE > Zero) && LEqual (Arg0, ToUUID ("893f00a6-660c-494e-bcfd-3043f4fb67c0")))
+		{
+			If (LEqual (0, ToInteger (Arg1)))
+			{
+				Switch (ToInteger (Arg2))
+				{
+					/* Function 0: returns a buffer containing one bit for each function index, starting with zero.
+					 * Bit 0 indicates whether there is support for any function other than function 0
+					 */
+					Case (0)
+					{
+						Return (Buffer(){0x07})
+					}
+					/* Function 1: P2SB Read
+					 * Package Details
+					 * Idx0 = PortID
+					 * Idx1 = Offset
+					 */
+					Case (1)
+					{
+						Local0 = DeRefOf (Index (Arg3, 0)) /* PordID */
+						Local1 = DeRefOf (Index (Arg3, 1)) /* offset */
+
+						Local3 = PCRR(Local0, Local1)
+						Printf ("[IOST] P2B Read: PortID: %o  Offset: %o read = %o", ToHexString(Local0), ToHexString(Local1), ToHexString(Local3))
+						Return(Local3)
+					}
+					/* Function 2: P2SB Write
+					 * Package Details
+					 * Idx0 = PortID
+					 * Idx1 = Offset
+					 * Idx2 = DataToWrite
+					 */
+					Case (2)
+					{
+						Local0 = DeRefOf (Index (Arg3, 0)) /* PordID */
+						Local1 = DeRefOf (Index (Arg3, 1)) /* offset */
+						Local2 = DeRefOf (Index (Arg3, 2)) /* data to Write */
+						Printf ("[IOST] P2B Write: PortID: %o Offset: %o with %o", ToHexString(Local0), ToHexString(Local1), ToHexString(Local2))
+						PCRW(Local0, Local1, Local2)
+						Return (0x00)
+					}
+				}
+			}
+		}
+		Return (Buffer () {0x00})
+	}
+}

From 2c58e525e8d7f07ae1a8124dd731abe0329c5b2c Mon Sep 17 00:00:00 2001
From: Cliff Huang <cliff.huang@intel.com>
Date: Fri, 14 Nov 2025 14:27:00 -0800
Subject: [PATCH 3026/3886] soc/intel/ptl: Add ACPI IOST support
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Add and enable IOST feature to support Intel's IO Self-Testing Software
(IOST), which is an OS tool for performing electrical margining analysis
on USB4 Host and Device Routers, DP2.1 displays, memory, UFS, and PCIe
Gen4+ devices. This change includes the IOST ACPI device in the SoC's
southbridge ASL and implements the SoC-specific soc_fill_p2sb_ssdt
function used by the common P2SB code to generate ACPI code for enabling
IOST in the DSDT. Additionally, the CBFS option "iost_enable" is
required to enable IOST. Command to add this option to the image:
cbfstool <coreboot_image> add-int -r COREBOOT -i 1 -n option/iost_enable
Note that this cbfstool command is an example, for its syntax format
could be changed in the future versions.

BUG=none
TEST=Build coreboot and add the CBFS option flag to the built image.
Boot to OS and verify IOST can access P2SB registers through the ACPI
interface for electrical margining tests.

Signed-off-by: Cliff Huang <cliff.huang@intel.com>
Change-Id: I6929fa3a44646c5385199a8b1e3d0b681d36c9cc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90045
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
---
 .../intel/pantherlake/acpi/southbridge.asl    |  3 ++
 src/soc/intel/pantherlake/chip.c              | 36 +++++++++++++++++++
 2 files changed, 39 insertions(+)

diff --git a/src/soc/intel/pantherlake/acpi/southbridge.asl b/src/soc/intel/pantherlake/acpi/southbridge.asl
index f2ad16b36b..fc74ce00b2 100644
--- a/src/soc/intel/pantherlake/acpi/southbridge.asl
+++ b/src/soc/intel/pantherlake/acpi/southbridge.asl
@@ -57,3 +57,6 @@
 #if CONFIG(SOC_INTEL_WILDCATLAKE)
 #include <soc/intel/common/block/acpi/acpi/ufs.asl>
 #endif
+
+/* P2B access for IOST */
+#include <soc/intel/common/acpi/iost.asl>
diff --git a/src/soc/intel/pantherlake/chip.c b/src/soc/intel/pantherlake/chip.c
index 8005240475..739cd9452a 100644
--- a/src/soc/intel/pantherlake/chip.c
+++ b/src/soc/intel/pantherlake/chip.c
@@ -1,5 +1,6 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
+#include <acpi/acpigen.h>
 #include <device/device.h>
 #include <device/pci.h>
 #include <fsp/api.h>
@@ -15,6 +16,7 @@
 #include <intelblocks/systemagent.h>
 #include <intelblocks/tcss.h>
 #include <intelblocks/xdci.h>
+#include <option.h>
 #include <soc/intel/common/reset.h>
 #include <soc/intel/common/vbt.h>
 #include <soc/iomap.h>
@@ -221,6 +223,40 @@ static void cpu_fill_ssdt(const struct device *dev)
 	generate_cpu_entries(dev);
 }
 
+/*
+ * This implements SoC-specific function used in common P2SB code to generate
+ * additional P2SB-related ACPI code.
+ */
+void soc_fill_p2sb_ssdt(const struct device *dev)
+{
+	/*
+	 * Enable IOST for debug via P2SB at OS level. The associated IOST ASL file
+	 * (i.e., src/soc/intel/common/acpi/iost.asl) is included in the SoC's
+	 * southbridge.asl. The CBFS option "iost_enable" is used to expose this
+	 * IOST interface to the OS.
+	 * Use cbfstool command to add this option to the image.
+	 */
+	if (!get_uint_option("iost_enable", 0))
+		return;
+
+	printk(BIOS_INFO, "IOST is enabled\n");
+	/*
+	 * The following generates:
+	 * Scope (\_SB.PCI0.IOST)
+	 * {
+	 *     If (CondRefOf (IOSE))
+	 *     {
+	 *         IOSE = 0x0F
+	 *     }
+	 * }
+	 */
+	acpigen_write_scope("\\_SB.PCI0.IOST");
+		acpigen_write_if_cond_ref_of("IOSE");
+			acpigen_write_store_int_to_namestr(0xf, "IOSE");
+		acpigen_write_if_end();
+	acpigen_write_scope_end();
+}
+
 static void cpu_set_north_irqs(struct device *dev)
 {
 	irq_program_non_pch();

From 5db16ea6fc8e3a45a5500876465b49d24c1068f5 Mon Sep 17 00:00:00 2001
From: Jeremy Compostella <jeremy.compostella@intel.com>
Date: Wed, 14 Jan 2026 09:08:18 -0800
Subject: [PATCH 3027/3886] soc/intel/pantherlake: Fix incorrect use of logical
 OR for TDP selection

The previous implementation used the logical OR (||) operator to select
between config->tdp and get_cpu_tdp(). In C, the || operator returns a
boolean value (0 or 1), not the value of the first true operand. This
caused the function to return incorrect TDP values.

This commit replaces the logical OR with the ternary operator (?:),
ensuring that config->tdp is returned if it is non-zero; otherwise,
get_cpu_tdp() is used. This change restores the intended behavior of
selecting the correct TDP value.

TEST=The power map is properly found and applied on a Panther Lake B005
     SoC.

Change-Id: I3a02f804510f87cb4d28bd929869570c355c5242
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90759
Reviewed-by: Guvendik, Bora <bora.guvendik@intel.com>
Reviewed-by: Kim, Wonkyu <wonkyu.kim@intel.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/soc/intel/pantherlake/tdp.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/soc/intel/pantherlake/tdp.c b/src/soc/intel/pantherlake/tdp.c
index 63b3072499..30b03366fe 100644
--- a/src/soc/intel/pantherlake/tdp.c
+++ b/src/soc/intel/pantherlake/tdp.c
@@ -21,5 +21,5 @@ enum soc_intel_pantherlake_cpu_tdps soc_get_cpu_tdp(void)
 	}
 
 	const struct soc_intel_pantherlake_config *config = config_of_soc();
-	return config->tdp || get_cpu_tdp();
+	return config->tdp ? : get_cpu_tdp();
 }

From 72af15f1de8278d46a74becb2eb63d4e28948a79 Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Tue, 13 Jan 2026 07:16:40 -0600
Subject: [PATCH 3028/3886] mb/google/zork: Fix missing comma in CFR object
 list

When CFR support was added in commit c1f0be39dae4 ("mb/google/zork:
Add CFR option menu support"), a comma was inadvertently left off
the end the first CFR object in the list, which breaks compilation.
Fix this by adding the missing comma.

TEST=build/boot zork

Change-Id: I5f13d87cbc81f440b0c14d253a6334adab45631e
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90732
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/google/zork/cfr.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/mainboard/google/zork/cfr.c b/src/mainboard/google/zork/cfr.c
index 5565d31cd8..dbf38c0dc7 100644
--- a/src/mainboard/google/zork/cfr.c
+++ b/src/mainboard/google/zork/cfr.c
@@ -7,7 +7,7 @@
 static struct sm_obj_form ec = {
 	.ui_name = "ChromeEC Embedded Controller",
 	.obj_list = (const struct sm_object *[]) {
-		&auto_fan_control
+		&auto_fan_control,
 		&ec_kb_backlight,
 		NULL
 	},

From a8737c5f868dd99b8a7c594f9b4ef3358c61131d Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Mon, 12 Jan 2026 14:43:24 -0600
Subject: [PATCH 3029/3886] mb/google/cyan: Set CBFS_SIZE default to match IFD
 BIOS size

All cyan-based boards define the size of the BIOS region in their IFD
as 6MB in size; it is likewise defined as such in chromeos.fmd. To
avoid having to override this in the board's config file when building
with a modern payload like edk2, set the default CBFS_SIZE to 6MB as
well to avoid issues with the payload not fitting.

TEST=build/boot google/edgar w/edk2 payload and default CBFS_SIZE

Change-Id: I17122aa2eb9848799c284d13d8c903ad125092b9
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90733
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/google/cyan/Kconfig | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/mainboard/google/cyan/Kconfig b/src/mainboard/google/cyan/Kconfig
index eacc8ef87d..fe4d2a1067 100644
--- a/src/mainboard/google/cyan/Kconfig
+++ b/src/mainboard/google/cyan/Kconfig
@@ -107,7 +107,7 @@ config OVERRIDE_DEVICETREE
 	default "variants/\$(CONFIG_VARIANT_DIR)/overridetree.cb"
 
 config CBFS_SIZE
-	default 0x200000
+	default 0x600000
 
 config MAINBOARD_SMBIOS_MANUFACTURER
 	string

From b890ca0648cbed6853624294af43bf687f60db0b Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Mon, 12 Jan 2026 12:45:04 -0600
Subject: [PATCH 3030/3886] mb/google/brya/var/yaviks: select USE_MTCL only if
 CHROMEOS

There is no wifi_mtcl.bin file publicly available, nor can it be
extracted from the stock Google firmware for YAVIKS, so restrict
USE_MTCL to downstream ChromeOS builds since validate_mtcl() fails
when no file is present in CBFS.

TEST=build/boot yaviks, verify no MTCL error in cbmem

Change-Id: I450db6fd8c460109aa4e491d88ec874c5f6429d0
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90734
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
---
 src/mainboard/google/brya/Kconfig | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/mainboard/google/brya/Kconfig b/src/mainboard/google/brya/Kconfig
index b871d32fa6..27f78c269b 100644
--- a/src/mainboard/google/brya/Kconfig
+++ b/src/mainboard/google/brya/Kconfig
@@ -771,7 +771,7 @@ config BOARD_GOOGLE_YAVIKS
 	select EC_GOOGLE_CHROMEEC_INCLUDE_SSFC_IN_FW_CONFIG
 	select HAVE_WWAN_POWER_SEQUENCE
 	select INTEL_GMA_HAVE_VBT
-	select USE_MTCL
+	select USE_MTCL if CHROMEOS
 
 config BOARD_GOOGLE_YAVILLA
 	select BOARD_GOOGLE_BASEBOARD_NISSA

From e6c5ee6450338071aa214957d68c37524abc8a3c Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?=E4=B8=80=E9=A2=97=E5=B0=8F=E5=9C=9F=E8=B1=86?=
 <72010312+potatoone@users.noreply.github.com>
Date: Tue, 16 Sep 2025 11:32:36 +0800
Subject: [PATCH 3031/3886] mb/google/hatch/var/kohaku: Add Samsung S-pen
 driver support

Modify the Wacom digitizer HID to support the Samsung S-pen. This allows
a different driver to attach under Windows, which adds support for the
side buttons as eraser function and air command.

TEST=build/boot kahaku, verify S-pen works under Windows/Linux

Change-Id: I60b75f7f16f6bb028ad1747e78cc49cac810fc92
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90735
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/google/hatch/variants/kohaku/overridetree.cb | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/mainboard/google/hatch/variants/kohaku/overridetree.cb b/src/mainboard/google/hatch/variants/kohaku/overridetree.cb
index 59704cafa1..d8c268d706 100644
--- a/src/mainboard/google/hatch/variants/kohaku/overridetree.cb
+++ b/src/mainboard/google/hatch/variants/kohaku/overridetree.cb
@@ -164,7 +164,7 @@ chip soc/intel/cannonlake
 		end # I2C #1
 		device ref i2c2		on
 			chip drivers/i2c/hid
-				register "generic.hid" = ""WCOM50C1""
+				register "generic.hid" = ""WCOM006C""
 				register "generic.desc" = ""WCOM Digitizer""
 				register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_C7_IRQ)"
 				register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C15)"

From 00fbc08b769613d9e0daba3dc972ee5468500629 Mon Sep 17 00:00:00 2001
From: Yidi Lin <yidilin@google.com>
Date: Tue, 13 Jan 2026 18:29:23 +0800
Subject: [PATCH 3032/3886] Reapply "soc/mediatek/mt8196: Call fsp_init via
 boot state"

This reverts commit 292d7b9d3d4ccf852a9c20b8fafb5663bff7ff56.

The resume failure is caused by the improper DEVAPC setting in fsp_init
for DM/PM and SPM. If fsp_init runs prior to dpm_init and spm_init, it
requires AP to grant the access to DM/PM and SPM from DEVAPC. The fix is
done in CB:90756.

BUG=b:474254985
TEST=Run suspend/resume test

Change-Id: Id21327f6d65d31659cdb8b4bda3b0a0510c438e8
Signed-off-by: Yidi Lin <yidilin@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90757
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Chen-Tsung Hsieh <chentsung@google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
---
 src/soc/mediatek/mt8196/soc.c | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/src/soc/mediatek/mt8196/soc.c b/src/soc/mediatek/mt8196/soc.c
index 24077a0fbc..e988a76926 100644
--- a/src/soc/mediatek/mt8196/soc.c
+++ b/src/soc/mediatek/mt8196/soc.c
@@ -1,6 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
 #include <bootmem.h>
+#include <bootstate.h>
 #include <device/device.h>
 #include <device/pci.h>
 #include <soc/booker.h>
@@ -56,7 +57,7 @@ static void mte_setup(void)
 	booker_mte_init(mte_start);
 }
 
-static void fsp_init(void)
+static void fsp_init(void *arg)
 {
 	uint32_t storage_type = mainboard_get_storage_type();
 
@@ -67,6 +68,8 @@ static void fsp_init(void)
 	mtk_fsp_load_and_run();
 }
 
+BOOT_STATE_INIT_ENTRY(BS_DEV_INIT, BS_ON_ENTRY, fsp_init, NULL);
+
 static void soc_init(struct device *dev)
 {
 	mtk_mmu_disable_l2c_sram();
@@ -76,7 +79,6 @@ static void soc_init(struct device *dev)
 	if (spm_init())
 		printk(BIOS_ERR, "spm init failed, Suspend may not work\n");
 
-	fsp_init();
 	sspm_init();
 	gpueb_init();
 	mcupm_init();

From 282c27c95c993af054b2d13ccc489e7cc77ea081 Mon Sep 17 00:00:00 2001
From: Patrick Rudolph <patrick.rudolph@9elements.com>
Date: Mon, 15 Sep 2025 16:33:10 +0200
Subject: [PATCH 3033/3886] arch/x86/acpi_bert_storage.c: Allow vendor specific
 BERT entries

Add a Kconfg option to allow the SoC to add vendor specific
BERT entries, not yet defined in the ACPI spec. The function
only has to return the size of payload data and the generic
code will allocate space on the BERT table.

The caller must fill in all BERT fields since the generic
code doesn't know anything about the BERT entry.

Change-Id: I361700098ce1a3cc6acae991456a1901d2f07fb6
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90639
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/arch/x86/Kconfig                     | 7 +++++++
 src/arch/x86/acpi_bert_storage.c         | 8 ++++++--
 src/arch/x86/include/arch/bert_storage.h | 3 +++
 3 files changed, 16 insertions(+), 2 deletions(-)

diff --git a/src/arch/x86/Kconfig b/src/arch/x86/Kconfig
index d78aa8fa30..b58907e230 100644
--- a/src/arch/x86/Kconfig
+++ b/src/arch/x86/Kconfig
@@ -459,4 +459,11 @@ config SOC_FILL_CPU_CACHE_INFO
 	default n
 	help
 	  SoC selects this if it implements soc_fill_cpu_cache_info.
+
+config SOC_BERT_SIZEOF_ERROR_SECTION
+	bool
+	default n
+	help
+	  SoC selects this if it implements soc_bert_sizeof_error_section.
+
 endif
diff --git a/src/arch/x86/acpi_bert_storage.c b/src/arch/x86/acpi_bert_storage.c
index 902ddb7da5..efa1d07849 100644
--- a/src/arch/x86/acpi_bert_storage.c
+++ b/src/arch/x86/acpi_bert_storage.c
@@ -192,6 +192,11 @@ static size_t sizeof_error_section(guid_t *guid)
 	else if (!guidcmp(guid, &CPER_SEC_FW_ERR_REC_REF_GUID))
 		return sizeof(cper_fw_err_rec_section_t);
 	/* else if ... sizeof(structures not yet defined) */
+	else if (CONFIG(SOC_BERT_SIZEOF_ERROR_SECTION)) {
+		size_t size = soc_bert_sizeof_error_section(guid);
+		if (size)
+			return size;
+	}
 
 	printk(BIOS_ERR, "Requested size of unrecognized CPER GUID\n");
 	return 0;
@@ -535,9 +540,8 @@ acpi_generic_error_status_t *bert_new_event(guid_t *guid)
 		r = bert_append_ia32x64(status);
 	else if (!guidcmp(guid, &CPER_SEC_FW_ERR_REC_REF_GUID))
 		r = bert_append_fw_err(status);
-	/* else if other types not implemented */
 	else
-		r = NULL;
+		r = bert_append_error_datasection(status, guid);
 
 	if (r)
 		return status;
diff --git a/src/arch/x86/include/arch/bert_storage.h b/src/arch/x86/include/arch/bert_storage.h
index eb5db7f9cb..41c4f1c6e5 100644
--- a/src/arch/x86/include/arch/bert_storage.h
+++ b/src/arch/x86/include/arch/bert_storage.h
@@ -50,6 +50,9 @@
  */
 void bert_errors_region(void **start, size_t *size);
 
+/* Returns the size for SoC specific GUIDs */
+size_t soc_bert_sizeof_error_section(guid_t *guid);
+
 /* Get amount of available storage left for error info */
 size_t bert_storage_remaining(void);
 /* Find if errors were added, a BERT region is present, and ACPI table needed */

From b4917ed44d049b3aa5eb865c5922e62e9394a51a Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Sat, 10 Jan 2026 08:51:56 -0600
Subject: [PATCH 3034/3886] payloads/edk2: rework serial output configuration

Make EDK2_DEBUG automatically select CONSOLE_SERIAL, require
EDK2_CBMEM_LOGGING to depend on EDK2_RELEASE, and make serial console
mutually exclusive with CBMEM logging. Revise the Kconfig text to
indicate the option is for the serial console, not serial debug output.

This prevents users from selecting options which conflict or will
result in a different result than expected. It simplifes the build
options into 4 clear choices:

- Release build
- Release build with cbmem logging
- Release build with serial console support
- Debug build with serial debugging + serial console support

TEST=build/boot google/drobit with above 4 build configurations.

Change-Id: I15bbbcfcb2d9d0b1d4c2074f2c33012ec94f6c01
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90719
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
---
 payloads/external/edk2/Kconfig | 18 +++++++++++-------
 1 file changed, 11 insertions(+), 7 deletions(-)

diff --git a/payloads/external/edk2/Kconfig b/payloads/external/edk2/Kconfig
index 7bfd486f7a..226e82d434 100644
--- a/payloads/external/edk2/Kconfig
+++ b/payloads/external/edk2/Kconfig
@@ -128,8 +128,9 @@ choice
 
 config EDK2_DEBUG
 	bool "Generate edk2 debug build"
+	select CONSOLE_SERIAL
 	help
-	  Generate a debug build.
+	  Generate a debug build. Select this if you want to enable serial debugging output.
 
 config EDK2_RELEASE
 	bool "Generate edk2 release build"
@@ -190,11 +191,12 @@ config EDK2_BOOT_TIMEOUT
 
 config EDK2_CBMEM_LOGGING
 	bool "Enable edk2 logging to CBMEM"
+	depends on EDK2_RELEASE
 	help
 	  Select this option if you want to enable edk2 logging to CBMEM.
-	  You may want to increase the default cbmem buffer size when selecting
-	  this option, especially if using a debug (vs release) build.
-	  Selecting this option will increase the payload size in CBFS by 0x10000.
+	  You will want to increase the default cbmem buffer size when selecting
+	  this option, as it will increase logging output significantly.
+	  Selecting this option will increase the payload size in CBFS by ~1MB.
 
 config EDK2_CPU_TIMER_LIB
 	bool
@@ -262,12 +264,14 @@ config EDK2_SD_MMC_TIMEOUT
 	  Most only require 10ms, but certain readers can take 1s.
 
 config EDK2_SERIAL_SUPPORT
-	bool "Support serial output"
+	bool "Enable serial console"
 	default y if EDK2_DEBUG
 	default n
+	depends on !EDK2_CBMEM_LOGGING
+	select CONSOLE_SERIAL
 	help
-	  Enable serial port output in edk2. Serial output limits the performance of edk2's
-	  FrontPage.
+	  Enable serial consule support in edk2. Serial output limits the performance of edk2's
+	  FrontPage. This option does not enable debugging output over serial. For that, use EDK2_DEBUG.
 
 config EDK2_SECURE_BOOT_SUPPORT
 	bool "Enable UEFI Secure Boot support"

From f712c965e4ce4af469d5538813685b3a93d2cc9e Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Tue, 13 Jan 2026 14:07:06 -0600
Subject: [PATCH 3035/3886] payloads/edk2: Update default MrChromebox branch
 from 2508 to 2511

Update the default MrChromebox branch to uefipayload_2511.
This branch is rebased on the latest upstream edk tag
'edk2-stable202511', and includes a number of other improvements,
such as setup menu password protection.

TEST=tested on multiple ChromeOS devices from Sandybridge through
Meteorlake.

Change-Id: I5addbcf37e0b1a1afbd731163b4419d4bd9a3747
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90747
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 payloads/external/edk2/Kconfig | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/payloads/external/edk2/Kconfig b/payloads/external/edk2/Kconfig
index 226e82d434..2f4cab5efe 100644
--- a/payloads/external/edk2/Kconfig
+++ b/payloads/external/edk2/Kconfig
@@ -86,7 +86,7 @@ config EDK2_REPOSITORY
 
 config EDK2_TAG_OR_REV
 	string "Insert a commit's SHA-1 or a branch name"
-	default "origin/uefipayload_2508" if EDK2_REPO_MRCHROMEBOX
+	default "origin/uefipayload_2511" if EDK2_REPO_MRCHROMEBOX
 	default "origin/universalpayload" if EDK2_UNIVERSAL_PAYLOAD
 	default "origin/master" if EDK2_REPO_OFFICIAL
 	default "" if EDK2_REPO_CUSTOM

From 23f0b0b313928b3740318cda500239b12b7390a0 Mon Sep 17 00:00:00 2001
From: Maximilian Brune <maximilian.brune@9elements.com>
Date: Tue, 30 Dec 2025 00:13:11 +0100
Subject: [PATCH 3036/3886] util/xcompile/xcompile: Fix clang target parameter

It updates the target variable that is used for `clang -target`.
Simply because the format was wrong. According to the documentation the
format of the so called "target triple" is:
<arch><sub>-<vendor>-<sys>-<env>
with:
arch = x86_64, i386, arm, thumb, mips, etc.
sub = for ex. on ARM: v5, v6m, v7a, v7m, etc.
vendor = pc, apple, nvidia, ibm, etc.  (can be omitted)
sys = none, linux, win32, darwin, cuda, etc.
env = eabi, gnu, android, macho, elf, etc.

In case of powerpc that causes an issue when trying to update clang to
version 21. The target parameter for clang ends up being
"powerpc64-none-unknown-linux-gnu". After testing, it turns out that in
clang version 18 that is actually a valid target parameter, although not
according to the documentation. In clang 21 however its not valid so fix
it accordingly.

Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: I958416e6c56459766794830fbeac57ac827ffdd9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90643
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
---
 util/xcompile/xcompile | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/util/xcompile/xcompile b/util/xcompile/xcompile
index 8f0d19a6a6..f88da69306 100755
--- a/util/xcompile/xcompile
+++ b/util/xcompile/xcompile
@@ -526,7 +526,7 @@ test_architecture() {
 
 	for clang_arch in $TCLIST invalid; do
 		for clang_prefix in $search $XGCCPATH "$GENERIC_COMPILER_PREFIX"; do
-			testcc "${clang_prefix}clang" "-target ${clang_arch}-none-unknown-${TABI} -c" && break 2
+			testcc "${clang_prefix}clang" "-target ${clang_arch}-none-${TABI} -c" && break 2
 		done
 	done
 
@@ -535,7 +535,7 @@ test_architecture() {
 		# but that's more of a clang limitation. Let's be optimistic
 		# that this will change in the future.
 		CLANG="${clang_prefix}clang"
-		CLANG_TARGET="-target ${clang_arch}-none-unknown-${TABI}"
+		CLANG_TARGET="-target ${clang_arch}-none-${TABI}"
 		CFLAGS_CLANG="$CLANG_TARGET $CFLAGS_CLANG"
 		CPPFLAGS_CLANG="$CLANG_TARGET $CPPFLAGS_CLANG"
 	fi

From 763911872967cb1703ad71cb93b1fcb4b5cd43cc Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Micha=C5=82=20=C5=BBygowski?= <michal.zygowski@3mdeb.com>
Date: Mon, 6 Oct 2025 11:41:21 +0200
Subject: [PATCH 3037/3886] drivers/amd/opensil: Add hooks to populate
 CBMEM_ID_MEMINFO
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Add a hooks that will populate mem_info structure with DIMM data
obtained from OpenSIL. As the memory population may be SoC-specific,
call a SoC-specific hook to fill the data.

Change-Id: I0b489c685877ac56f45e0e3abd0bd1b64549585b
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89484
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
---
 src/drivers/amd/opensil/Makefile.mk |  1 +
 src/drivers/amd/opensil/dmi.c       | 13 +++++++++++++
 src/drivers/amd/opensil/opensil.h   |  5 +++++
 3 files changed, 19 insertions(+)
 create mode 100644 src/drivers/amd/opensil/dmi.c

diff --git a/src/drivers/amd/opensil/Makefile.mk b/src/drivers/amd/opensil/Makefile.mk
index 6ed46d1f81..08918bc36d 100644
--- a/src/drivers/amd/opensil/Makefile.mk
+++ b/src/drivers/amd/opensil/Makefile.mk
@@ -7,6 +7,7 @@ subdirs-y += mpio
 romstage-y += romstage.c
 
 ramstage-y += acpi.c
+ramstage-y += dmi.c
 ramstage-y += ramstage.c
 ramstage-y += memmap.c
 
diff --git a/src/drivers/amd/opensil/dmi.c b/src/drivers/amd/opensil/dmi.c
new file mode 100644
index 0000000000..0cedb74c9b
--- /dev/null
+++ b/src/drivers/amd/opensil/dmi.c
@@ -0,0 +1,13 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <bootstate.h>
+#include "opensil.h"
+
+__weak void opensil_smbios_fill_cbmem_meminfo(void) { }
+
+static void prepare_dmi_17(void *unused)
+{
+	opensil_smbios_fill_cbmem_meminfo();
+}
+
+BOOT_STATE_INIT_ENTRY(BS_DEV_ENUMERATE, BS_ON_ENTRY, prepare_dmi_17, NULL);
diff --git a/src/drivers/amd/opensil/opensil.h b/src/drivers/amd/opensil/opensil.h
index e6efbdc80a..7cc7ad80c9 100644
--- a/src/drivers/amd/opensil/opensil.h
+++ b/src/drivers/amd/opensil/opensil.h
@@ -5,6 +5,7 @@
 
 #include <acpi/acpi.h>
 #include <device/device.h>
+#include <smbios.h>
 
 /* Set up openSIL env and call TP1 */
 void amd_opensil_silicon_init(void);
@@ -14,5 +15,9 @@ void configure_mpio(void);
 void amd_opensil_add_memmap(struct device *dev, unsigned long *idx);
 /* Fill in FADT from openSIL */
 void amd_opensil_fill_fadt_io_ports(acpi_fadt_t *fadt);
+/* Marshalls dimm info from SIL_DMI_INFO into CBMEM_ID_MEMINFO */
+void opensil_smbios_fill_cbmem_meminfo(void);
+/* Fill DIMM locators using OpenSIL DMI info, returns 0 on success */
+int opensil_smbios_fill_dimm_locator(const struct dimm_info *dimm, struct smbios_type17 *t);
 
 #endif /* OPENSIL_DRIVER_H */

From ae7b75fb0df5b3206a452d65c1bf5cd1565814fa Mon Sep 17 00:00:00 2001
From: Nicholas Chin <nic.c3.14@gmail.com>
Date: Fri, 2 Jan 2026 07:23:08 -0700
Subject: [PATCH 3038/3886] mb/lenovo/sklkbl_thinkpad/cfr.c: Fix X280 build
 error

As there is no model of the X280 with a dGPU, its devicetree does not
declare a device with a dgpu alias like the other Skylake/Kaby Lake
Thinkpad ports. This breaks the DEV_PTR(dgpu) reference in cfr.c,
causing the following build error if CONFIG_DRIVERS_OPTION_CFR is set:

In file included from src/mainboard/lenovo/sklkbl_thinkpad/cfr.c:9:
src/mainboard/lenovo/sklkbl_thinkpad/cfr.c: In function 'update_dgpu':
build/static.h:11:33: error: '_dev_dgpu_ptr' undeclared (first use in this function); did you mean '_dev_igpu_ptr'?
   11 | #define DEV_PTR(_alias)         _dev_##_alias##_ptr
      |                                 ^~~~~
src/mainboard/lenovo/sklkbl_thinkpad/cfr.c:14:31: note: in expansion of macro 'DEV_PTR'
   14 |         struct device *dgpu = DEV_PTR(dgpu);
      |                               ^~~~~~~
build/static.h:11:33: note: each undeclared identifier is reported only once for each function it appears in
   11 | #define DEV_PTR(_alias)         _dev_##_alias##_ptr
      |                                 ^~~~~
src/mainboard/lenovo/sklkbl_thinkpad/cfr.c:14:31: note: in expansion of macro 'DEV_PTR'
   14 |         struct device *dgpu = DEV_PTR(dgpu);
      |                               ^~~~~~~
make: *** [Makefile:431: build/ramstage/mainboard/lenovo/sklkbl_thinkpad/cfr.o] Error 1

Fix this by declaring a WEAK_DEV_PTR for the dgpu device, which will be
overridden by the compiled devicetree if the board variant declares a
dgpu device in its overridetree.

TEST=X280 builds successfully with the following defconfig:

CONFIG_VENDOR_LENOVO=y
CONFIG_BOARD_LENOVO_X280=y
CONFIG_DRIVERS_OPTION_CFR=y

Change-Id: I18cc18a88851bb943de8ab6d2d1fdcbf0f4aea86
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90674
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
---
 src/mainboard/lenovo/sklkbl_thinkpad/cfr.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/cfr.c b/src/mainboard/lenovo/sklkbl_thinkpad/cfr.c
index 8f282facdd..b5d979806d 100644
--- a/src/mainboard/lenovo/sklkbl_thinkpad/cfr.c
+++ b/src/mainboard/lenovo/sklkbl_thinkpad/cfr.c
@@ -8,6 +8,8 @@
 #include <soc/cfr.h>
 #include <static.h>
 
+WEAK_DEV_PTR(dgpu);
+
 /* Hide the dGPU CFR entry if dGPU not present */
 static void update_dgpu(struct sm_object *new)
 {

From 3883118ed9a2306cb942414f62587202a58c7dd5 Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Sun, 23 Nov 2025 17:28:40 -0800
Subject: [PATCH 3039/3886] mb/google/brya/var/kano: Configure cameras for
 Windows/Linux ACPI mode

Update device tree configuration to work with the newly-added Windows/
Linux ACPI device type mode (MIPI_ACPI_TYPE_WINDOWS_LINUX):

- Add IPUA device to GFX generic driver as non-VGA device (required for
  IPU enumeration in Windows/Linux mode where IPU is attached to iGPU)
- Add sensor_name ("CJFLE23" and "CJFLE25") for device identification

TEST=build/boot Win11/Linux (Arch) on google/kano, verify MIPI camera
functional under both OSes using the Intel IPU6 driver stack.

Change-Id: I9232318c30ba0eee6dcd54f7199f6995a8ffa48b
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90743
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/google/brya/variants/kano/overridetree.cb | 8 +++++++-
 1 file changed, 7 insertions(+), 1 deletion(-)

diff --git a/src/mainboard/google/brya/variants/kano/overridetree.cb b/src/mainboard/google/brya/variants/kano/overridetree.cb
index 73065130e6..89cb331799 100644
--- a/src/mainboard/google/brya/variants/kano/overridetree.cb
+++ b/src/mainboard/google/brya/variants/kano/overridetree.cb
@@ -98,7 +98,7 @@ chip soc/intel/alderlake
 	device domain 0 on
 		device ref igpu on
 			chip drivers/gfx/generic
-				register "device_count" = "6"
+				register "device_count" = "7"
 				# DDIA for eDP
 				register "device[0].name" = ""LCD0""
 				# Internal panel on the first port of the graphics chip
@@ -117,6 +117,10 @@ chip soc/intel/alderlake
 				register "device[4].pld" = "ACPI_PLD_TYPE_C(RIGHT, RIGHT, ACPI_PLD_GROUP(2, 1))"
 				# TCP3 (DP-4) is unused for any ports but still enumerated in the kernel, so GFX device is added for TCP3
 				register "device[5].name" = ""DD05""
+				# IPUA for IPUs
+				register "device[6].name" = ""IPUA""
+				register "device[6].non_vga_device" = "true"
+				register "device[6].addr" = "0x3480"
 				device generic 0 on end
 			end
 		end # Integrated Graphics Device
@@ -322,6 +326,7 @@ chip soc/intel/alderlake
 				register "acpi_uid" = "0"
 				register "acpi_name" = ""CAM0""
 				register "chip_name" = ""Ov 2740 Camera""
+				register "sensor_name" = ""CJFLE23""
 				register "device_type" = "INTEL_ACPI_CAMERA_SENSOR"
 				register "has_power_resource" = "true"
 
@@ -365,6 +370,7 @@ chip soc/intel/alderlake
 				register "acpi_uid" = "0"
 				register "acpi_name" = ""CAM0""
 				register "chip_name" = ""Hi-556 Camera""
+				register "sensor_name" = ""CJFLE25""
 				register "device_type" = "INTEL_ACPI_CAMERA_SENSOR"
 				register "has_power_resource" = "true"
 

From 139f6c3e64924daaed65145dacb0a31bf3b752d8 Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Sun, 23 Nov 2025 20:21:29 -0800
Subject: [PATCH 3040/3886] mb/google/brya/var/redrix: Configure cameras for
 Windows/Linux ACPI mode

Update device tree configuration to work with the newly-added Windows/
Linux ACPI device type mode (MIPI_ACPI_TYPE_WINDOWS_LINUX):

- Add IPUA device to GFX generic driver as non-VGA device (required for
  IPU enumeration in Windows/Linux mode where IPU is attached to iGPU)
- Add sensor_name ("S5VM17" and "CJFLE25") for device identification

TEST=build/boot Win11/Linux (Ubuntu 25.10) on google/redrix, verify MIPI
camera functional under both OSes using the Intel IPU6 driver stack.

Change-Id: Ic72a96e93706c096b3839ab4c951e1d0a725b5ce
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90744
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
---
 .../google/brya/variants/redrix/overridetree.cb    | 14 ++++++++++++--
 1 file changed, 12 insertions(+), 2 deletions(-)

diff --git a/src/mainboard/google/brya/variants/redrix/overridetree.cb b/src/mainboard/google/brya/variants/redrix/overridetree.cb
index 822babaead..3bc331129a 100644
--- a/src/mainboard/google/brya/variants/redrix/overridetree.cb
+++ b/src/mainboard/google/brya/variants/redrix/overridetree.cb
@@ -102,7 +102,7 @@ chip soc/intel/alderlake
 	device domain 0 on
 		device ref igpu on
 			chip drivers/gfx/generic
-				register "device_count" = "6"
+				register "device_count" = "7"
 				# DDIA for eDP
 				register "device[0].name" = ""LCD0""
 				# Use ChromeOS privacy screen _HID
@@ -125,12 +125,16 @@ chip soc/intel/alderlake
 				register "device[4].pld" = "ACPI_PLD_TYPE_C(RIGHT, LEFT, ACPI_PLD_GROUP(2, 1))"
 				# TCP3 (DP-4) is unused for any ports but still enumerated in the kernel, so GFX device is added for TCP3
 				register "device[5].name" = ""DD05""
+				# IPUA for IPUs
+				register "device[6].name" = ""IPUA""
+				register "device[6].non_vga_device" = "true"
+				register "device[6].addr" = "0x3480"
 				device generic 0 on
 					probe EPS PRIVACY_SCREEN
 				end
 			end
 			chip drivers/gfx/generic
-				register "device_count" = "6"
+				register "device_count" = "7"
 				# DDIA for eDP
 				register "device[0].name" = ""LCD0""
 				# Internal panel on the first port of the graphics chip
@@ -149,6 +153,10 @@ chip soc/intel/alderlake
 				register "device[4].pld" = "ACPI_PLD_TYPE_C(RIGHT, LEFT, ACPI_PLD_GROUP(2, 1))"
 				# TCP3 (DP-4) is unused for any ports but still enumerated in the kernel, so GFX device is added for TCP3
 				register "device[5].name" = ""DD05""
+				# IPUA for IPUs
+				register "device[6].name" = ""IPUA""
+				register "device[6].non_vga_device" = "true"
+				register "device[6].addr" = "0x3480"
 				device generic 0 on
 					probe EPS PRIVACY_SCREEN_ABSENT
 				end
@@ -417,6 +425,7 @@ chip soc/intel/alderlake
 				register "acpi_uid" = "0"
 				register "acpi_name" = ""CAM0""
 				register "chip_name" = ""Ov 5675 Camera""
+				register "sensor_name" = ""S5VM17""
 				register "device_type" = "INTEL_ACPI_CAMERA_SENSOR"
 
 				register "ssdb.lanes_used" = "2"
@@ -459,6 +468,7 @@ chip soc/intel/alderlake
 				register "acpi_uid" = "0"
 				register "acpi_name" = ""CAM0""
 				register "chip_name" = ""Hi-556 Camera""
+				register "sensor_name" = ""CJFLE25""
 				register "device_type" = "INTEL_ACPI_CAMERA_SENSOR"
 				register "max_dstate_for_probe" = "ACPI_DEVICE_SLEEP_D3_COLD"
 

From a306987ae44f658cea9911c3f168db38ad5fbfac Mon Sep 17 00:00:00 2001
From: Keith Hui <buurin@gmail.com>
Date: Thu, 23 May 2024 10:38:18 -0400
Subject: [PATCH 3041/3886] util/superiotool: Add experimental Nuvoton NPCD378
 support

I use this to dump SIO config on an HP Z210 CMT workstation.

It's a shotgun blast into the dark, although based on what was
done for Z220, already in tree.

Change-Id: I83184f29c11c92384f6a09b671ed9e24956e9e57
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82627
Reviewed-by: Walter Sonius <walterav1984@gmail.com>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 util/superiotool/nuvoton.c | 44 ++++++++++++++++++++++++++++++++++++++
 1 file changed, 44 insertions(+)

diff --git a/util/superiotool/nuvoton.c b/util/superiotool/nuvoton.c
index 80ba12ecdd..5f249e7463 100644
--- a/util/superiotool/nuvoton.c
+++ b/util/superiotool/nuvoton.c
@@ -907,6 +907,50 @@ static const struct superio_registers reg_table[] = {
 			{0x30,0xe0,0xe1,0xe2,0xe3,EOT},
 			{0xa0,0x20,0x04,0x05,0x01,EOT}},
 		{EOT}}},
+	{0x1c11, "NPCD378 (experimental)", {
+		{NOLDN, NULL,
+			{0x10,0x11,0x13,0x14,0x1a,0x1b,0x1c,0x1d,0x20,0x21,0x22,0x24,0x25,0x26,0x27,0x28,0x2a,0x2b,0x2c,0x2d,0x2f,EOT},
+			{NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA,EOT}},
+		{0x00, "FDC",
+			{0x30,0x60,0x61,0x70,0x74,0xf0,0xf1,0xf2,0xf4,0xf5,EOT},
+			{0x01,0x03,0xf0,0x06,0x02,0x0e,0x00,0xff,0x00,0x00,EOT}},
+		{0x01, "Parallel Port",
+			{0x30,0x60,0x61,0x70,0x74,0xf0,EOT},
+			{0x01,0x03,0x78,0x07,0x04,0x3f,EOT}},
+		{0x02, "UART A",
+			{0x30,0x60,0x61,0x70,0xf0,0xf2,0xf3,0xf4,0xf5,0xf6,0xf7,0xf8,EOT},
+			{0x01,0x03,0xf8,0x04,0x00,0x00,0x00,0xff,0xff,0x02,0x00,0x00,EOT}},
+		{0x03, "UART B",
+			{0x30,0x60,0x61,0x70,0xf0,0xf2,0xf3,0xf4,0xf5,0xf6,0xf7,0xf8,EOT},
+			{0x01,0x02,0xf8,0x03,0x00,0x00,0x00,0xff,0xff,0x02,0x00,0x00,EOT}},
+		{0x04, "LED Control",
+			{0x30,0x60,0x61,0x62,0x63,0x70,0xf0,0xf1,0xf2,EOT},
+			{0x00,0x00,0x00,0x00,0x00,0x00,NANA,NANA,NANA,EOT}},
+		{0x05, "?",
+			{0x30,0x60,0x61,0x62,0x63,0x70,0xf0,0xf1,0xf2,0xf3,EOT},
+			{0x00,0x00,0x00,0x00,0x00,0x00,0x08,0x09,0x32,0x00,EOT}},
+		{0x06, "Keyboard Controller",
+			{0x30,0x60,0x61,0x62,0x63,0x70,0x72,0xf0,EOT},
+			{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x83,EOT}},
+		{0x07, "?",
+			{0x30,0x60,0x61,0x70,0x72,0xf0,EOT},
+			{0x00,0x00,0x00,0x00,0x00,NANA,EOT}},
+		{0x08, "Hardware Monitor",
+			{0x30,0x60,0x61,0xf0,0xf1,0xf2,0xf3,0xf4,0xf5,0xf6,0xf7,0xf8,0xf9,0xfa,0xfb,0xfc,0xfd,0xfe,0xff,EOT},
+			{0x00,0x00,0x00,NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA,EOT}},
+		{0x0f, "?",
+			{0xe0,0xe1,0xe2,0xe3,0xe4,0xe5,0xe6,0xe7,0xe9,0xf0,0xf1,0xf2,0xf3,0xf4,0xf5,0xf6,0xf7,0xf8,0xf9,0xfa,0xfb,0xfc,0xfd,0xfe,0xff,EOT},
+			{NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA,EOT}},
+		{0x15, "?",
+			{0x30,0x60,0x61,0x62,0x63,0x70,0x72,0xf0,0xf1,0xf2,0xf3,0xf4,0xf5,0xf6,0xf7,0xf8,0xf9,0xfa,0xfb,0xfc,0xfd,0xfe,0xff,EOT},
+			{0x00,0x00,0x00,0x00,0x00,0x00,0x00,NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA,EOT}},
+		{0x1c, "?",
+			{0x30,0x60,0x61,0x62,0x63,0x70,0x72,0xf0,0xf1,0xf2,0xf3,0xf4,0xf5,0xf6,0xf7,0xf8,0xf9,0xfa,0xfb,0xfc,0xfd,0xfe,0xff,EOT},
+			{0x00,0x00,0x00,0x00,0x00,0x00,0x00,NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA,EOT}},
+		{0x1e, "?",
+			{0x30,0x60,0x61,0x62,0x63,0x70,0x72,0xf0,0xf1,0xf2,0xf3,0xf4,0xf5,0xf6,0xf7,0xf8,0xf9,0xfa,0xfb,0xfc,0xfd,0xfe,0xff,EOT},
+			{0x00,0x00,0x00,0x00,0x00,0x00,0x00,NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA,EOT}},
+		{EOT}}},
 	{EOT}
 };
 

From f9b917d3913685419c8615b38440962cb27781a6 Mon Sep 17 00:00:00 2001
From: Subrata Banik <subratabanik@google.com>
Date: Wed, 14 Jan 2026 18:25:27 +0000
Subject: [PATCH 3042/3886] soc/qualcomm/x1p42100: Relocate CBMEM top below XBL
 log

Relocate the CBMEM top address from a hardcoded 0xC7800000 to the
start of the XBL log region (_dram_xbl_log).

This change moves the CBMEM region from the high Linux Kernel Reserve
block down into the lower DRAM Space 0, adjacent to other firmware
reserved regions. This consolidation prevents marking CBMEM range as
`reserved` and ensures CBMEM is placed in a more stable memory location
(marked available aka System RAM).

- Remove CBMEM_TOP define from addressmap.h.
- Update cbmem_top_chipset() to return (uintptr_t)_dram_xbl_log.
- Update memlayout.ld documentation to reflect the new memory map.

BUG=none
TEST=Boot on X1P42100 platform, verify CBMEM console and tables are
accessible and correctly located via 'cbmem -l'.

w/o this patch:

```
c7800000-cb7fffff : reserved
```

w/ this patch:

```
815a0000-819fffff : System RAM
```

Change-Id: I7392bb7a62d50640696301931940a7baa00351e3
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90760
Reviewed-by: Derek Huang <derekhuang@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Jayvik Desai <jayvik@google.com>
---
 src/soc/qualcomm/x1p42100/cbmem.c                  | 2 +-
 src/soc/qualcomm/x1p42100/include/soc/addressmap.h | 1 -
 src/soc/qualcomm/x1p42100/memlayout.ld             | 4 ++--
 3 files changed, 3 insertions(+), 4 deletions(-)

diff --git a/src/soc/qualcomm/x1p42100/cbmem.c b/src/soc/qualcomm/x1p42100/cbmem.c
index 6836a3ca84..0524c67f03 100644
--- a/src/soc/qualcomm/x1p42100/cbmem.c
+++ b/src/soc/qualcomm/x1p42100/cbmem.c
@@ -6,5 +6,5 @@
 
 uintptr_t cbmem_top_chipset(void)
 {
-	return (uintptr_t)CBMEM_TOP;
+	return (uintptr_t)_dram_xbl_log;
 }
diff --git a/src/soc/qualcomm/x1p42100/include/soc/addressmap.h b/src/soc/qualcomm/x1p42100/include/soc/addressmap.h
index 8b22662e92..60649835d6 100644
--- a/src/soc/qualcomm/x1p42100/include/soc/addressmap.h
+++ b/src/soc/qualcomm/x1p42100/include/soc/addressmap.h
@@ -24,7 +24,6 @@
 
 #define AOP_BOOT_COOKIE_ADDR            0xC3F0040
 
-#define CBMEM_TOP			0xC7800000
 /* X1P42100 NCC0 PLL CONFIG ADDRESSES */
 #define NCC0_NCC_CMU_NCC_PLL_CFG	0x199A2010
 #define NCC0_NCC_CMU_NCC_CLK_CFG	0x199A2030
diff --git a/src/soc/qualcomm/x1p42100/memlayout.ld b/src/soc/qualcomm/x1p42100/memlayout.ld
index 110444a87a..1c2865a5c8 100644
--- a/src/soc/qualcomm/x1p42100/memlayout.ld
+++ b/src/soc/qualcomm/x1p42100/memlayout.ld
@@ -41,8 +41,6 @@
  * 0xD7800000    +----------------------------------------------------------+      |        |
  *               |                 Linux Kernel Reserve                     |      |        |
  * 0xC7800000    +----------------------------------------------------------+      |        |
- *               |                        CBMEM                             |      |        |
- *               +----------------------------------------------------------+      |        |
  *               |                ... Usable memory ...                     |      |        |
  * 0xA1800000    +----------------------------------------------------------+      |        |
  *               |                      RAMSTAGE                            | DRAM Space 0  |
@@ -83,6 +81,8 @@
  * 0x81A40000    +----------------------------------------------------------+      |        |
  *               |                     dram_xbl_log                         |      |        |
  * 0x81A00000    +----------------------------------------------------------+      |        |
+ *               |                        CBMEM                             |      |        |
+ *               +----------------------------------------------------------+      |        |
  *               |                ... Usable memory ...                     |      |        |
  * 0x815A0000    +----------------------------------------------------------+      |        |
  *               |                      dram_cpucp                          |      |        |

From 7351e663d2848877a243707370c34f1d8a16b688 Mon Sep 17 00:00:00 2001
From: Yunlong Jia <yunlong.jia@ecs.corp-partner.google.com>
Date: Thu, 15 Jan 2026 07:18:43 +0000
Subject: [PATCH 3043/3886] mb/google/nissa: Enable early EC SW sync & eSOL for
 gothrax/epic

`VBOOT_EARLY_EC_SYNC` enables EC software sync in romstage.
This is useful to achieve full USB-PD negotiation early in the boot
flow. It eliminates a problem where PMC is wrongly configured in
depthcharge during the EC-sync scenario which prevents USB devices
from getting detected when connected via a self-powered USB hub.

`VBOOT_EC_SYNC_ESOL` displays early sign-of-life (eSOL) during EC
firmware updates.

BUG=b:386920751,b:467506959,b:468885646
TEST=Verify detection and booting to OS from USB drive connected to
the Servo v4 debugger (self-powered hub) during the EC-sync scenario.
Verify that eSOL is displayed during EC firmware update.

Signed-off-by: Yunlong Jia <yunlong.jia@ecs.corp-partner.google.com>
Change-Id: I612b4dc13be2efaee863e6cacf8fc4c432edc313
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90762
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Derek Huang <derekhuang@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
---
 src/mainboard/google/brya/Kconfig | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/mainboard/google/brya/Kconfig b/src/mainboard/google/brya/Kconfig
index 27f78c269b..dca1ea2201 100644
--- a/src/mainboard/google/brya/Kconfig
+++ b/src/mainboard/google/brya/Kconfig
@@ -1174,8 +1174,8 @@ config VARIANT_DIR
 	default "pujjolo" if BOARD_GOOGLE_PUJJOLO
 
 config VBOOT
-	select VBOOT_EARLY_EC_SYNC if !(BOARD_GOOGLE_BASEBOARD_NISSA || BOARD_GOOGLE_BASEBOARD_TRULO) || BOARD_GOOGLE_RULL
-	select VBOOT_EC_SYNC_ESOL if BOARD_GOOGLE_RULL
+	select VBOOT_EARLY_EC_SYNC if !(BOARD_GOOGLE_BASEBOARD_NISSA || BOARD_GOOGLE_BASEBOARD_TRULO) || BOARD_GOOGLE_RULL || BOARD_GOOGLE_GOTHRAX || BOARD_GOOGLE_EPIC
+	select VBOOT_EC_SYNC_ESOL if BOARD_GOOGLE_RULL || BOARD_GOOGLE_GOTHRAX || BOARD_GOOGLE_EPIC
 	select VBOOT_LID_SWITCH
 
 config UART_FOR_CONSOLE

From b5ad97a2688bd734d352a9c2ec447c3e360e118a Mon Sep 17 00:00:00 2001
From: Yunlong Jia <yunlong.jia@ecs.corp-partner.google.com>
Date: Thu, 15 Jan 2026 07:46:25 +0000
Subject: [PATCH 3044/3886] mb/google/nissa/var/gothrax: Add wifi sar table

Add AX211 wifi sar table for gothrax wifi sar config.
Use fw_config to separate different wifi card settings.

WLAN_AX211_Intel: 1

BUG=b:454207611
Test=emerge-nissa coreboot

Signed-off-by: Yunlong Jia <yunlong.jia@ecs.corp-partner.google.com>
Change-Id: I11cf6cd61a13f5365530fc07b589d749c9459d26
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90763
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
---
 src/mainboard/google/brya/Kconfig                    | 1 +
 src/mainboard/google/brya/variants/gothrax/variant.c | 6 ++++++
 2 files changed, 7 insertions(+)

diff --git a/src/mainboard/google/brya/Kconfig b/src/mainboard/google/brya/Kconfig
index dca1ea2201..e1d64876c5 100644
--- a/src/mainboard/google/brya/Kconfig
+++ b/src/mainboard/google/brya/Kconfig
@@ -303,6 +303,7 @@ config BOARD_GOOGLE_GOTHRAX
 	select DRIVERS_I2C_SX9324
 	select DRIVERS_I2C_SX9324_SUPPORT_LEGACY_LINUX_DRIVER
 	select HAVE_WWAN_POWER_SEQUENCE
+	select CHROMEOS_WIFI_SAR if CHROMEOS
 
 config BOARD_GOOGLE_GUREN
 	select BOARD_GOOGLE_BASEBOARD_NISSA
diff --git a/src/mainboard/google/brya/variants/gothrax/variant.c b/src/mainboard/google/brya/variants/gothrax/variant.c
index 8b8822bf4f..ab134c2ba7 100644
--- a/src/mainboard/google/brya/variants/gothrax/variant.c
+++ b/src/mainboard/google/brya/variants/gothrax/variant.c
@@ -4,6 +4,7 @@
 #include <baseboard/variants.h>
 #include <console/console.h>
 #include <fw_config.h>
+#include <sar.h>
 
 void variant_update_soc_chip_config(struct soc_intel_alderlake_config *config)
 {
@@ -40,3 +41,8 @@ void variant_update_soc_chip_config(struct soc_intel_alderlake_config *config)
 		config->typec_aux_bias_pads[1].pad_auxn_dc = 0x00;
 	}
 }
+
+const char *get_wifi_sar_cbfs_filename(void)
+{
+	return get_wifi_sar_fw_config_filename(FW_CONFIG_FIELD(WLAN));
+}

From 5f76f78383c5bed3f96138a5d7156d6926ba9afd Mon Sep 17 00:00:00 2001
From: Uwe Poeche <uwe.poeche@siemens.com>
Date: Mon, 12 Jan 2026 09:47:44 +0100
Subject: [PATCH 3045/3886] mb/siemens/mc_ehl7: Deactivate GbE and PSE GbE 0

Remove the unused GbE and PSE TSN GbE device 0. These devices are not
required for the current board functionality. Removing them simplifies
the configuration.
Also PSE is not used for any other functionality, the local host
interface is deacitivated as well.

TEST=Check if all other GbE ports of mainboard still work.

Change-Id: I83c7e9731d3684a0b0a7f16b533ee3ea2989f3c6
Signed-off-by: Uwe Poeche <uwe.poeche@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90726
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 .../siemens/mc_ehl/variants/mc_ehl7/Kconfig   |  2 -
 .../mc_ehl/variants/mc_ehl7/devicetree.cb     | 38 -------------------
 2 files changed, 40 deletions(-)

diff --git a/src/mainboard/siemens/mc_ehl/variants/mc_ehl7/Kconfig b/src/mainboard/siemens/mc_ehl/variants/mc_ehl7/Kconfig
index 6524f4855d..c1c3bb2a98 100644
--- a/src/mainboard/siemens/mc_ehl/variants/mc_ehl7/Kconfig
+++ b/src/mainboard/siemens/mc_ehl/variants/mc_ehl7/Kconfig
@@ -5,8 +5,6 @@ if BOARD_SIEMENS_MC_EHL7
 config BOARD_SPECIFIC_OPTIONS
 	def_bool y
 	select DRIVER_INTEL_I210
-	select DRIVERS_ETH_PHY_M88E1512
-	select EHL_TSN_DRIVER
 	select MAINBOARD_HAS_TPM2
 	select MEMORY_MAPPED_TPM
 	select NC_FPGA_POST_CODE
diff --git a/src/mainboard/siemens/mc_ehl/variants/mc_ehl7/devicetree.cb b/src/mainboard/siemens/mc_ehl/variants/mc_ehl7/devicetree.cb
index 776eab22e3..da0ce4e292 100644
--- a/src/mainboard/siemens/mc_ehl/variants/mc_ehl7/devicetree.cb
+++ b/src/mainboard/siemens/mc_ehl/variants/mc_ehl7/devicetree.cb
@@ -186,46 +186,8 @@ chip soc/intel/elkhartlake
 		device pci 1c.4 on	end # RP5 (pcie1 multi VC)
 		device pci 1c.6 on	end # RP7 (pcie3 multi VC)
 
-		device pci 1d.0 off	end # Intel PSE IPC (local host to PSE)
-		device pci 1d.1 on	    # Intel PSE Time-Sensitive Networking GbE 0
-			# Enable external Marvell PHY 88E1512
-			chip drivers/net/phy/m88e1512
-				register "configure_leds" = "true"
-				# LED[0]: On - 1000 Mbps Link, Off - Else
-				register "led_0_ctrl" = "7"
-				# LED[1]: On - 100 Mbps Link, Off - Else
-				register "led_1_ctrl" = "7"
-				# LED[2]: Blink - Activity, Off - No Activity
-				register "led_2_ctrl" = "4"
-				# INTn is not routed to LED[2] pin
-				register "enable_int" = "false"
-				register "downshift_cnt" = "2"
-				device mdio 0 on    # PHY address
-					ops m88e1512_ops
-				end
-			end
-		end
-
 		device pci 1e.0 on	end # UART0
 		device pci 1e.1 on	end # UART1
-		device pci 1e.4 on	    # PCH Time-Sensitive Networking GbE
-			# Enable external Marvell PHY 88E1512
-			chip drivers/net/phy/m88e1512
-				register "configure_leds" = "true"
-				# LED[0]: On - 1000 Mbps Link, Off - Else
-				register "led_0_ctrl" = "7"
-				# LED[1]: On - 100 Mbps Link, Off - Else
-				register "led_1_ctrl" = "7"
-				# LED[2]: Blink - Activity, Off - No Activity
-				register "led_2_ctrl" = "4"
-				# INTn is not routed to LED[2] pin
-				register "enable_int" = "false"
-				register "downshift_cnt" = "2"
-				device mdio 1 on    # PHY address
-					ops m88e1512_ops
-				end
-			end
-		end
 
 		device pci 1f.0 on	    # eSPI Interface
 			chip drivers/pc80/tpm

From 3f5807ce101cabe88ac528690653fd4901c333cf Mon Sep 17 00:00:00 2001
From: Uwe Poeche <uwe.poeche@siemens.com>
Date: Mon, 12 Jan 2026 16:05:25 +0100
Subject: [PATCH 3046/3886] mb/siemens/mc_ehl7: Deactivate SATA interface

On this mainboard no SATA interface is assembled. Therefore, it is
deactivated.

TEST=Boot into OS and verify via lspci if relevant SATA Controller is
deactivated and no error in coreboot log is shown.

Change-Id: Iea01c30d18d81e67087ac8abef5cece0040087e5
Signed-off-by: Uwe Poeche <uwe.poeche@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90730
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 .../siemens/mc_ehl/variants/mc_ehl7/devicetree.cb      | 10 +---------
 1 file changed, 1 insertion(+), 9 deletions(-)

diff --git a/src/mainboard/siemens/mc_ehl/variants/mc_ehl7/devicetree.cb b/src/mainboard/siemens/mc_ehl/variants/mc_ehl7/devicetree.cb
index da0ce4e292..fcd6de5463 100644
--- a/src/mainboard/siemens/mc_ehl/variants/mc_ehl7/devicetree.cb
+++ b/src/mainboard/siemens/mc_ehl/variants/mc_ehl7/devicetree.cb
@@ -78,13 +78,7 @@ chip soc/intel/elkhartlake
 	# Determine PCIe root port speed
 	register "PcieRpPcieSpeed[6]" = "2"
 
-	# Storage (SATA/SDCARD/EMMC) related UPDs
-	register "SataSalpSupport" = "0"
-	register "SataPortsEnable[1]" = "1"
-	register "SataPortsDevSlp[1]" = "0"
-	register "SataPortsSSD[1]" = "1"
-	register "SataSpeed" = "SATA_GEN2"
-
+	# Storage (SDCARD/EMMC) related UPDs
 	register "ScsEmmcHs400Enabled" = "0"
 	register "ScsEmmcDdr50Enabled" = "1"
 	register "SdCardPowerEnableActiveHigh" = "1"
@@ -165,8 +159,6 @@ chip soc/intel/elkhartlake
 
 		device pci 16.0 hidden	end # Management Engine Interface 1
 
-		device pci 17.0 on      end # SATA
-
 		device pci 19.0 on	    # I2C4
 			# Add dummy I2C device to limit BUS speed to 100 kHz in OS
 			chip drivers/i2c/generic

From b7763a59735d233e47343a00c83e5f8d8b9cf36c Mon Sep 17 00:00:00 2001
From: Cliff Huang <cliff.huang@intel.com>
Date: Sun, 14 Sep 2025 23:10:47 -0700
Subject: [PATCH 3047/3886] mb/google/fatcat: Implement Google Rex touchscreen
 integration
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

This update introduces support for Google touchscreen devices
to the existing framework, enhancing compatibility with Google's
hardware interfaces. It extends the fw_config field with new
options to accommodate different connection types used by Google
touchscreens. Specifically, it adds:
- TOUCHSCREEN_LPSS_I2C_ELAN_REX for ELAN9006 interfaced via LPSS-I2C.
- TOUCHSCREEN_THC_SPI_ELAN_REX for ELAN6918 interfaced via THC-SPI.
- TOUCHSCREEN_THC_I2C_ELAN_REX for ELAN9006 interfaced via THC-I2C.

BUG=none
TEST=Connect Google's REX touchscreen with the conversion cables. Boot
to OS with fw_config setting for Google's touchscreen and verify
device enumeration in /sys/bus/hid/devices directory.

Signed-off-by: Cliff Huang <cliff.huang@intel.com>
Change-Id: I3fda0e4587d8484881c844674053a0badfc23a11
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89181
Reviewed-by: Kim, Kyoung Il <kyoung.il.kim@intel.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 .../google/fatcat/variants/fatcat/fw_config.c | 12 ++--
 .../fatcat/variants/fatcat/overridetree.cb    | 63 +++++++++++++++++++
 .../google/fatcat/variants/fatcat/variant.c   |  6 +-
 3 files changed, 75 insertions(+), 6 deletions(-)

diff --git a/src/mainboard/google/fatcat/variants/fatcat/fw_config.c b/src/mainboard/google/fatcat/variants/fatcat/fw_config.c
index d1f40ec06d..e0a59219a4 100644
--- a/src/mainboard/google/fatcat/variants/fatcat/fw_config.c
+++ b/src/mainboard/google/fatcat/variants/fatcat/fw_config.c
@@ -669,15 +669,18 @@ void fw_config_gpio_padbased_override(struct pad_config *padbased_table)
 		GPIO_PADBASED_OVERRIDE(padbased_table, touchpad_i2c_disable_pads);
 	}
 
-	if (fw_config_probe(FW_CONFIG(TOUCHSCREEN, TOUCHSCREEN_LPSS_I2C))) {
+	if (fw_config_probe(FW_CONFIG(TOUCHSCREEN, TOUCHSCREEN_LPSS_I2C)) ||
+		fw_config_probe(FW_CONFIG(TOUCHSCREEN, TOUCHSCREEN_LPSS_I2C_ELAN_REX))) {
 		GPIO_PADBASED_OVERRIDE(padbased_table, touchscreen_lpss_i2c_enable_pads);
-	} else if (fw_config_probe(FW_CONFIG(TOUCHSCREEN, TOUCHSCREEN_THC_I2C))) {
+	} else if (fw_config_probe(FW_CONFIG(TOUCHSCREEN, TOUCHSCREEN_THC_I2C)) ||
+		fw_config_probe(FW_CONFIG(TOUCHSCREEN, TOUCHSCREEN_THC_I2C_ELAN_REX))) {
 		GPIO_PADBASED_OVERRIDE(padbased_table, touchscreen_thc_i2c_enable_pads);
 		if (config->thc_wake_on_touch[0])
 			GPIO_PADBASED_OVERRIDE(padbased_table, thc0_enable_wake);
 	} else if (fw_config_probe(FW_CONFIG(TOUCHSCREEN, TOUCHSCREEN_GSPI))) {
 		GPIO_PADBASED_OVERRIDE(padbased_table, touchscreen_gspi_enable_pads);
-	} else if (fw_config_probe(FW_CONFIG(TOUCHSCREEN, TOUCHSCREEN_THC_SPI))) {
+	} else if (fw_config_probe(FW_CONFIG(TOUCHSCREEN, TOUCHSCREEN_THC_SPI)) ||
+		fw_config_probe(FW_CONFIG(TOUCHSCREEN, TOUCHSCREEN_THC_SPI_ELAN_REX))) {
 		GPIO_PADBASED_OVERRIDE(padbased_table, touchscreen_thc_spi_enable_pads);
 		if (config->thc_wake_on_touch[0])
 			GPIO_PADBASED_OVERRIDE(padbased_table, thc0_enable_wake);
@@ -708,7 +711,8 @@ void fw_config_gpio_padbased_override(struct pad_config *padbased_table)
 	 *       2. CBI selecting TS THC-SPI or TS GSPI with FSP present is invalid case.
 	 */
 	if (fw_config_probe(FW_CONFIG(TOUCHSCREEN, TOUCHSCREEN_GSPI)) ||
-		fw_config_probe(FW_CONFIG(TOUCHSCREEN, TOUCHSCREEN_THC_SPI))) {
+		fw_config_probe(FW_CONFIG(TOUCHSCREEN, TOUCHSCREEN_THC_SPI)) ||
+		fw_config_probe(FW_CONFIG(TOUCHSCREEN, TOUCHSCREEN_THC_SPI_ELAN_REX))) {
 		/*  board has TS SPI rework and not FPS support */
 	} else if (fw_config_probe(FW_CONFIG(FP, FP_PRESENT))) {
 		GPIO_PADBASED_OVERRIDE(padbased_table, fp_enable_pads);
diff --git a/src/mainboard/google/fatcat/variants/fatcat/overridetree.cb b/src/mainboard/google/fatcat/variants/fatcat/overridetree.cb
index f95d9e8255..dc744d0cd1 100644
--- a/src/mainboard/google/fatcat/variants/fatcat/overridetree.cb
+++ b/src/mainboard/google/fatcat/variants/fatcat/overridetree.cb
@@ -24,6 +24,10 @@ fw_config
 		option TOUCHSCREEN_GSPI		2
 		option TOUCHSCREEN_THC_SPI	3
 		option TOUCHSCREEN_THC_I2C	4
+		# NOTE: conversion cables are required to connect with Google touch screen
+		option TOUCHSCREEN_LPSS_I2C_ELAN_REX	5
+		option TOUCHSCREEN_THC_SPI_ELAN_REX	6
+		option TOUCHSCREEN_THC_I2C_ELAN_REX	7
 	end
 	field TOUCHPAD 11 12
 		option TOUCHPAD_NONE		0
@@ -326,6 +330,8 @@ chip soc/intel/pantherlake
 			register "thc_wake_on_touch[0]" = "true"
 			probe TOUCHSCREEN TOUCHSCREEN_THC_SPI
 			probe TOUCHSCREEN TOUCHSCREEN_THC_I2C
+			probe TOUCHSCREEN TOUCHSCREEN_THC_SPI_ELAN_REX
+			probe TOUCHSCREEN TOUCHSCREEN_THC_I2C_ELAN_REX
 			# THC0 is function 0; hence it needs to be enabled when THC1 is to be enabled.
 			probe TOUCHPAD TOUCHPAD_THC_I2C
 			chip drivers/intel/touch
@@ -345,6 +351,23 @@ chip soc/intel/pantherlake
 					probe TOUCHSCREEN TOUCHSCREEN_THC_I2C
 				end
 			end
+			chip drivers/intel/touch
+				register "name" = "INTEL_THC0_NAME"
+				register "mode" = "THC_HID_I2C_MODE"
+				register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_F08)"
+				register "enable_delay_ms" = "2"
+				register "enable_off_delay_ms" = "2"
+				register "wake_on_touch" = "true"
+				# NOTE: Use GpioInt() in _CRS and does not use GPE.
+				register "wake_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW_WAKE(GPP_VGPIO3_THC0)"
+				register "active_ltr" = "1"
+				register "idle_ltr" = "0"
+				register "connected_device" = "TH_SENSOR_ELAN_REX"
+				register "add_acpi_dma_property" = "true"
+				device generic 0 alias touch_0_i2c_google on
+					probe TOUCHSCREEN TOUCHSCREEN_THC_I2C_ELAN_REX
+				end
+			end
 			chip drivers/intel/touch
 				register "name" = "INTEL_THC0_NAME"
 				register "mode" = "THC_HID_SPI_MODE"
@@ -367,6 +390,28 @@ chip soc/intel/pantherlake
 					probe TOUCHSCREEN TOUCHSCREEN_THC_SPI
 				end
 			end
+			chip drivers/intel/touch
+				register "name" = "INTEL_THC0_NAME"
+				register "mode" = "THC_HID_SPI_MODE"
+				register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_F08)"
+				register "enable_delay_ms" = "2"
+				register "enable_off_delay_ms" = "2"
+				register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_E16)"
+				register "reset_delay_ms" = "10"
+				register "reset_off_delay_ms" = "2"
+				register "wake_on_touch" = "true"
+				# NOTE: Use GpioInt() in _CRS and does not use GPE.
+				register "wake_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW_WAKE(GPP_VGPIO3_THC0)"
+				register "active_ltr" = "1"
+				register "idle_ltr" = "0"
+				register "connected_device" = "TH_SENSOR_ELAN_REX"
+				register "soc_hidspi.write_mode" = "HIDSPI_WRITE_MODE_SINGLE"
+				register "soc_hidspi.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_E16)"
+				register "add_acpi_dma_property" = "true"
+				device generic 0 alias touch_0_spi_google on
+					probe TOUCHSCREEN TOUCHSCREEN_THC_SPI_ELAN_REX
+				end
+			end
 		end
 		device ref thc1 on
 			register "thc_wake_on_touch[1]" = "true"
@@ -902,6 +947,24 @@ chip soc/intel/pantherlake
 					probe TOUCHSCREEN TOUCHSCREEN_LPSS_I2C
 				end
 			end
+			chip drivers/i2c/hid
+				register "generic.hid" = ""ELAN9006""
+				register "generic.desc" = ""ELAN Touchscreen""
+				register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_E18_IRQ)"
+				# NOTE: pmc_gpe0_dw2 is GPP_E in baseboard devicetree.cb.
+				register "generic.wake" = "GPE0_DW2_18"
+				register "generic.probed" = "1"
+				register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_E16)"
+				register "generic.reset_delay_ms" = "20"
+				register "generic.reset_off_delay_ms" = "2"
+				register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_F08)"
+				register "generic.enable_delay_ms" = "1"
+				register "generic.has_power_resource" = "1"
+				register "hid_desc_reg_offset" = "0x01"
+				device i2c 10 on
+					probe TOUCHSCREEN TOUCHSCREEN_LPSS_I2C_ELAN_REX
+				end
+			end
 		end # I2C4
 		device ref i2c5 on
 			chip drivers/i2c/hid
diff --git a/src/mainboard/google/fatcat/variants/fatcat/variant.c b/src/mainboard/google/fatcat/variants/fatcat/variant.c
index a3d7e79e65..a8b5b4146d 100644
--- a/src/mainboard/google/fatcat/variants/fatcat/variant.c
+++ b/src/mainboard/google/fatcat/variants/fatcat/variant.c
@@ -51,9 +51,11 @@ void variant_update_soc_chip_config(struct soc_intel_pantherlake_config *config)
      * | with WOT disabled | with WOT disabled|                 |                            |
      * +===================+==================+=================+============================+
      */
-	if (fw_config_probe(FW_CONFIG(TOUCHSCREEN, TOUCHSCREEN_THC_I2C))) {
+	if (fw_config_probe(FW_CONFIG(TOUCHSCREEN, TOUCHSCREEN_THC_I2C)) ||
+		fw_config_probe(FW_CONFIG(TOUCHSCREEN, TOUCHSCREEN_THC_I2C_ELAN_REX))) {
 		config->thc_mode[0] = THC_HID_I2C_MODE;
-	} else if (fw_config_probe(FW_CONFIG(TOUCHSCREEN, TOUCHSCREEN_THC_SPI))) {
+	} else if (fw_config_probe(FW_CONFIG(TOUCHSCREEN, TOUCHSCREEN_THC_SPI)) ||
+		fw_config_probe(FW_CONFIG(TOUCHSCREEN, TOUCHSCREEN_THC_SPI_ELAN_REX))) {
 		config->thc_mode[0] = THC_HID_SPI_MODE;
 	} else if (fw_config_probe(FW_CONFIG(TOUCHSCREEN, TOUCHSCREEN_GSPI))) {
 		config->serial_io_gspi_mode[PchSerialIoIndexGSPI0] = PchSerialIoPci;

From 01d82febb2f7d784d3ac918740045772e94e777e Mon Sep 17 00:00:00 2001
From: Angel Pons <th3fanbus@gmail.com>
Date: Sun, 21 Dec 2025 20:03:36 +0100
Subject: [PATCH 3048/3886] util/autoport: Separate handling of Kconfig selects

Previously, `KconfigBool` was used to generate selects (if the option
value is true) or bool option overrides (if the option value is false).
This approach is not particularly flexible: one cannot have conditions
for selects, and bool option overrides can only disable options.

Introduce a new `KconfigStatement` map of Kconfig names to conditions.
An empty condition string means that no condition is to be added. Also
update uses of `KconfigBool` to `KconfigSelect` to preserve autoport's
current behaviour.

TEST=Generated files for HP ProBook 4740s (Sandy Bridge) do not change.

Change-Id: I88666ce0d761c1d393ac602196229ec0878fed42
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90585
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
---
 util/autoport/azalia.go      |  2 +-
 util/autoport/bd82x6x.go     |  4 ++--
 util/autoport/ec_fixme.go    |  2 +-
 util/autoport/ec_lenovo.go   |  4 ++--
 util/autoport/haswell.go     |  6 +++---
 util/autoport/lynxpoint.go   |  6 +++---
 util/autoport/main.go        | 36 +++++++++++++++++++++---------------
 util/autoport/rce823.go      |  2 +-
 util/autoport/sandybridge.go | 10 +++++-----
 9 files changed, 39 insertions(+), 33 deletions(-)

diff --git a/util/autoport/azalia.go b/util/autoport/azalia.go
index a7c8b7253b..eb28a7c2dc 100644
--- a/util/autoport/azalia.go
+++ b/util/autoport/azalia.go
@@ -11,7 +11,7 @@ type azalia struct {
 func (i azalia) Scan(ctx Context, addr PCIDevData) {
 	/* FIXME: Rework to output new verb table format, or better
 	   yet use hda-decoder to avoid duplicating functionality */
-	KconfigBool["AZALIA_USE_LEGACY_VERB_TABLE"] = true
+	KconfigSelect["AZALIA_USE_LEGACY_VERB_TABLE"] = ""
 
 	az := Create(ctx, "hda_verb.c")
 	defer az.Close()
diff --git a/util/autoport/bd82x6x.go b/util/autoport/bd82x6x.go
index a94b359b51..919c043d07 100644
--- a/util/autoport/bd82x6x.go
+++ b/util/autoport/bd82x6x.go
@@ -62,8 +62,8 @@ func (b bd82x6x) Scan(ctx Context, addr PCIDevData) {
 	inteltool := ctx.InfoSource.GetInteltool()
 	GPIO(ctx, inteltool)
 
-	KconfigBool["SOUTHBRIDGE_INTEL_"+b.variant] = true
-	KconfigBool["SERIRQ_CONTINUOUS_MODE"] = true
+	KconfigSelect["SOUTHBRIDGE_INTEL_"+b.variant] = ""
+	KconfigSelect["SERIRQ_CONTINUOUS_MODE"] = ""
 	KconfigInt["USBDEBUG_HCD_INDEX"] = 2
 	KconfigComment["USBDEBUG_HCD_INDEX"] = "FIXME: check this"
 	dmi := ctx.InfoSource.GetDMI()
diff --git a/util/autoport/ec_fixme.go b/util/autoport/ec_fixme.go
index 17c431c65e..bdb2966077 100644
--- a/util/autoport/ec_fixme.go
+++ b/util/autoport/ec_fixme.go
@@ -60,7 +60,7 @@ Method(_PTS,1)
 	}
 `
 
-	KconfigBool["EC_ACPI"] = true
+	KconfigSelect["EC_ACPI"] = ""
 	si := Create(ctx, "acpi/superio.asl")
 	defer si.Close()
 
diff --git a/util/autoport/ec_lenovo.go b/util/autoport/ec_lenovo.go
index 38257d0eda..267b64f6f5 100644
--- a/util/autoport/ec_lenovo.go
+++ b/util/autoport/ec_lenovo.go
@@ -149,8 +149,8 @@ void mainboard_smi_sleep(u8 slp_typ)
 	Add_SPDX(ec, ASL, GPL2_only)
 	ec.WriteString("#include <ec/lenovo/h8/acpi/ec.asl>\n")
 
-	KconfigBool["EC_LENOVO_PMH7"] = true
-	KconfigBool["EC_LENOVO_H8"] = true
+	KconfigSelect["EC_LENOVO_PMH7"] = ""
+	KconfigSelect["EC_LENOVO_H8"] = ""
 
 	pmh := DevTreeNode{
 		Chip: "ec/lenovo/pmh7",
diff --git a/util/autoport/haswell.go b/util/autoport/haswell.go
index 668771b754..f4f331e036 100644
--- a/util/autoport/haswell.go
+++ b/util/autoport/haswell.go
@@ -101,9 +101,9 @@ func (i haswellmc) Scan(ctx Context, addr PCIDevData) {
 
 	PutPCIDev(addr, "Host bridge")
 
-	KconfigBool["NORTHBRIDGE_INTEL_HASWELL"] = true
-	KconfigBool["HAVE_ACPI_TABLES"] = true
-	KconfigBool["HAVE_ACPI_RESUME"] = true
+	KconfigSelect["NORTHBRIDGE_INTEL_HASWELL"] = ""
+	KconfigSelect["HAVE_ACPI_TABLES"] = ""
+	KconfigSelect["HAVE_ACPI_RESUME"] = ""
 
 	DSDTIncludes = append(DSDTIncludes, DSDTInclude{
 		File: "cpu/intel/common/acpi/cpu.asl",
diff --git a/util/autoport/lynxpoint.go b/util/autoport/lynxpoint.go
index 899736ef22..681072c6b4 100644
--- a/util/autoport/lynxpoint.go
+++ b/util/autoport/lynxpoint.go
@@ -143,11 +143,11 @@ func (b lynxpoint) Scan(ctx Context, addr PCIDevData) {
 		GPIO(ctx, inteltool)
 	}
 
-	KconfigBool["SOUTHBRIDGE_INTEL_LYNXPOINT"] = true
+	KconfigSelect["SOUTHBRIDGE_INTEL_LYNXPOINT"] = ""
 	if isULT {
-		KconfigBool["INTEL_LYNXPOINT_LP"] = true
+		KconfigSelect["INTEL_LYNXPOINT_LP"] = ""
 	}
-	KconfigBool["SERIRQ_CONTINUOUS_MODE"] = true
+	KconfigSelect["SERIRQ_CONTINUOUS_MODE"] = ""
 	if isULT {
 		KconfigInt["USBDEBUG_HCD_INDEX"] = 1
 	} else {
diff --git a/util/autoport/main.go b/util/autoport/main.go
index 1246e3277c..896a81f869 100644
--- a/util/autoport/main.go
+++ b/util/autoport/main.go
@@ -130,6 +130,7 @@ var KconfigComment map[string]string = map[string]string{}
 var KconfigString map[string]string = map[string]string{}
 var KconfigHex map[string]uint32 = map[string]uint32{}
 var KconfigInt map[string]int = map[string]int{}
+var KconfigSelect map[string]string = map[string]string{}
 var ROMSizeKB = 0
 var ROMProtocol = ""
 var FlashROMSupport = ""
@@ -572,6 +573,14 @@ func makeComment(name string) string {
 	return " # " + cmt
 }
 
+func makeSelect(name string) string {
+	condition, ok := KconfigSelect[name]
+	if !ok || condition == "" {
+		return name + makeComment(name)
+	}
+	return name + " if " + condition + makeComment(name)
+}
+
 func makeKconfig(ctx Context) {
 	kc := Create(ctx, "Kconfig")
 	defer kc.Close()
@@ -581,33 +590,30 @@ func makeKconfig(ctx Context) {
 
 	fmt.Fprintf(kc, "config BOARD_SPECIFIC_OPTIONS\n\tdef_bool y\n")
 	keys := []string{}
-	for name, val := range KconfigBool {
-		if val {
-			keys = append(keys, name)
-		}
+	for name, _ := range KconfigSelect {
+		keys = append(keys, name)
 	}
 
 	sort.Strings(keys)
 
 	for _, name := range keys {
-		fmt.Fprintf(kc, "\tselect %s%s\n", name, makeComment(name))
+		fmt.Fprintf(kc, "\tselect %s\n", makeSelect(name))
 	}
 
 	keys = nil
-	for name, val := range KconfigBool {
-		if !val {
-			keys = append(keys, name)
-		}
+	for name, _ := range KconfigBool {
+		keys = append(keys, name)
 	}
 
 	sort.Strings(keys)
 
 	for _, name := range keys {
+		var mapper map[bool]rune = map[bool]rune{false: 'n', true: 'y'}
 		fmt.Fprintf(kc, `
 config %s%s
 	bool
-	default n
-`, name, makeComment(name))
+	default %c
+`, name, makeComment(name), mapper[KconfigBool[name]])
 	}
 
 	keys = nil
@@ -742,7 +748,7 @@ func main() {
 	}
 
 	if dmi.IsLaptop {
-		KconfigBool["SYSTEM_TYPE_LAPTOP"] = true
+		KconfigSelect["SYSTEM_TYPE_LAPTOP"] = ""
 	}
 	ctx.SaneVendor = sanitize(ctx.Vendor)
 	for {
@@ -767,7 +773,7 @@ func main() {
 	ScanRoot(ctx)
 
 	if IGDEnabled {
-		KconfigBool["MAINBOARD_HAS_LIBGFXINIT"] = true
+		KconfigSelect["MAINBOARD_HAS_LIBGFXINIT"] = ""
 		KconfigComment["MAINBOARD_HAS_LIBGFXINIT"] = "FIXME: check this"
 		AddRAMStageFile("gma-mainboard.ads", "CONFIG_MAINBOARD_USE_LIBGFXINIT")
 	}
@@ -851,10 +857,10 @@ func main() {
 	}
 
 	if ROMSizeKB == 0 {
-		KconfigBool["BOARD_ROMSIZE_KB_2048"] = true
+		KconfigSelect["BOARD_ROMSIZE_KB_2048"] = ""
 		KconfigComment["BOARD_ROMSIZE_KB_2048"] = "FIXME: correct this"
 	} else {
-		KconfigBool[fmt.Sprintf("BOARD_ROMSIZE_KB_%d", ROMSizeKB)] = true
+		KconfigSelect[fmt.Sprintf("BOARD_ROMSIZE_KB_%d", ROMSizeKB)] = ""
 	}
 
 	makeKconfig(ctx)
diff --git a/util/autoport/rce823.go b/util/autoport/rce823.go
index 7c921093f4..20fab4a33d 100644
--- a/util/autoport/rce823.go
+++ b/util/autoport/rce823.go
@@ -30,7 +30,7 @@ func (r rce823) Scan(ctx Context, addr PCIDevData) {
 		PutPCIChip(addr, cur)
 	}
 	PutPCIDev(addr, "Ricoh SD card reader")
-	KconfigBool["DRIVERS_RICOH_RCE822"] = true
+	KconfigSelect["DRIVERS_RICOH_RCE822"] = ""
 }
 
 func init() {
diff --git a/util/autoport/sandybridge.go b/util/autoport/sandybridge.go
index 552bd66d48..b479bfe739 100644
--- a/util/autoport/sandybridge.go
+++ b/util/autoport/sandybridge.go
@@ -62,11 +62,11 @@ func (i sandybridgemc) Scan(ctx Context, addr PCIDevData) {
 	PutPCIDev(addr, "")
 
 	/* FIXME:XX some configs are unsupported.  */
-	KconfigBool["NORTHBRIDGE_INTEL_SANDYBRIDGE"] = true
-	KconfigBool["USE_NATIVE_RAMINIT"] = true
-	KconfigBool["INTEL_INT15"] = true
-	KconfigBool["HAVE_ACPI_TABLES"] = true
-	KconfigBool["HAVE_ACPI_RESUME"] = true
+	KconfigSelect["NORTHBRIDGE_INTEL_SANDYBRIDGE"] = ""
+	KconfigSelect["USE_NATIVE_RAMINIT"] = ""
+	KconfigSelect["INTEL_INT15"] = ""
+	KconfigSelect["HAVE_ACPI_TABLES"] = ""
+	KconfigSelect["HAVE_ACPI_RESUME"] = ""
 
 	DSDTIncludes = append(DSDTIncludes, DSDTInclude{
 		File: "cpu/intel/common/acpi/cpu.asl",

From 2fc8051679320c4cb00ad54f39d5b18097d0da94 Mon Sep 17 00:00:00 2001
From: Angel Pons <th3fanbus@gmail.com>
Date: Sun, 21 Dec 2025 20:22:47 +0100
Subject: [PATCH 3049/3886] util/autoport: Factor out getting sorted Kconfig
 option names

Using generics (introduced in go 1.18) we can avoid repeating the same
code multiple times by encapsulating it into a generic function.

Change-Id: I5dc6696f8802d3fe57290121e22b2c27c545d3ef
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90586
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nicholas <nic.c3.14@gmail.com>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
---
 util/autoport/go.mod  |  1 +
 util/autoport/main.go | 53 ++++++++++++-------------------------------
 2 files changed, 15 insertions(+), 39 deletions(-)

diff --git a/util/autoport/go.mod b/util/autoport/go.mod
index 55a89cc9e1..dac59c1285 100644
--- a/util/autoport/go.mod
+++ b/util/autoport/go.mod
@@ -1 +1,2 @@
 module autoport
+go 1.18
diff --git a/util/autoport/main.go b/util/autoport/main.go
index 896a81f869..1718b4f24d 100644
--- a/util/autoport/main.go
+++ b/util/autoport/main.go
@@ -581,6 +581,15 @@ func makeSelect(name string) string {
 	return name + " if " + condition + makeComment(name)
 }
 
+func getSortedKeys[T any](strMap map[string]T) []string {
+	keys := []string{}
+	for k, _ := range strMap {
+		keys = append(keys, k)
+	}
+	sort.Strings(keys)
+	return keys
+}
+
 func makeKconfig(ctx Context) {
 	kc := Create(ctx, "Kconfig")
 	defer kc.Close()
@@ -589,25 +598,12 @@ func makeKconfig(ctx Context) {
 	fmt.Fprintf(kc, "if %s\n\n", ctx.KconfigName)
 
 	fmt.Fprintf(kc, "config BOARD_SPECIFIC_OPTIONS\n\tdef_bool y\n")
-	keys := []string{}
-	for name, _ := range KconfigSelect {
-		keys = append(keys, name)
-	}
 
-	sort.Strings(keys)
-
-	for _, name := range keys {
+	for _, name := range getSortedKeys(KconfigSelect) {
 		fmt.Fprintf(kc, "\tselect %s\n", makeSelect(name))
 	}
 
-	keys = nil
-	for name, _ := range KconfigBool {
-		keys = append(keys, name)
-	}
-
-	sort.Strings(keys)
-
-	for _, name := range keys {
+	for _, name := range getSortedKeys(KconfigBool) {
 		var mapper map[bool]rune = map[bool]rune{false: 'n', true: 'y'}
 		fmt.Fprintf(kc, `
 config %s%s
@@ -616,14 +612,7 @@ config %s%s
 `, name, makeComment(name), mapper[KconfigBool[name]])
 	}
 
-	keys = nil
-	for name, _ := range KconfigString {
-		keys = append(keys, name)
-	}
-
-	sort.Strings(keys)
-
-	for _, name := range keys {
+	for _, name := range getSortedKeys(KconfigString) {
 		fmt.Fprintf(kc, `
 config %s%s
 	string
@@ -631,14 +620,7 @@ config %s%s
 `, name, makeComment(name), KconfigString[name])
 	}
 
-	keys = nil
-	for name, _ := range KconfigHex {
-		keys = append(keys, name)
-	}
-
-	sort.Strings(keys)
-
-	for _, name := range keys {
+	for _, name := range getSortedKeys(KconfigHex) {
 		fmt.Fprintf(kc, `
 config %s%s
 	hex
@@ -646,14 +628,7 @@ config %s%s
 `, name, makeComment(name), KconfigHex[name])
 	}
 
-	keys = nil
-	for name, _ := range KconfigInt {
-		keys = append(keys, name)
-	}
-
-	sort.Strings(keys)
-
-	for _, name := range keys {
+	for _, name := range getSortedKeys(KconfigInt) {
 		fmt.Fprintf(kc, `
 config %s%s
 	int

From 94672e2b45b61729afbfb990a4b7efb80f4b79a2 Mon Sep 17 00:00:00 2001
From: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Date: Tue, 14 Oct 2025 21:43:16 +0900
Subject: [PATCH 3050/3886] sb/intel/ibexpeak: Remove 6/7 series chipset PCI
 IDs
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Support for the Ibex Peak chipset was added in commit 888d559b0373
("Support for Ibexpeak southbridge") by copy-pasting the bd82x6x
implementation and making appropriate changes. This resulted in some
of the PCI IDs for 6/7 series chipsets being left behind.

While some of these PCI IDs were removed in a commit b7d878888013
("ibexpeak/lpc: Fix PCIIDs."), there are still some that remain, we
remove those in this commit.

Change-Id: I5dc0e4fb2694eec9ef6246e0ae9211dff604d5b9
Signed-off-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89569
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
---
 src/southbridge/intel/ibexpeak/azalia.c | 2 --
 src/southbridge/intel/ibexpeak/me.c     | 1 -
 src/southbridge/intel/ibexpeak/smbus.c  | 2 --
 3 files changed, 5 deletions(-)

diff --git a/src/southbridge/intel/ibexpeak/azalia.c b/src/southbridge/intel/ibexpeak/azalia.c
index 6196096a14..6a738f356d 100644
--- a/src/southbridge/intel/ibexpeak/azalia.c
+++ b/src/southbridge/intel/ibexpeak/azalia.c
@@ -117,8 +117,6 @@ static struct device_operations azalia_ops = {
 };
 
 static const unsigned short pci_device_ids[] = {
-	0x1c20,
-	0x1e20,
 	PCI_DID_INTEL_IBEXPEAK_AUDIO,
 	0
 };
diff --git a/src/southbridge/intel/ibexpeak/me.c b/src/southbridge/intel/ibexpeak/me.c
index fbcb01dc3a..68a0ca5b3a 100644
--- a/src/southbridge/intel/ibexpeak/me.c
+++ b/src/southbridge/intel/ibexpeak/me.c
@@ -515,7 +515,6 @@ static struct device_operations device_ops = {
 };
 
 static const unsigned short pci_device_ids[] = {
-	0x1c3a,
 	PCI_DID_INTEL_IBEXPEAK_HECI1,
 	0
 };
diff --git a/src/southbridge/intel/ibexpeak/smbus.c b/src/southbridge/intel/ibexpeak/smbus.c
index 6bbd1e44f8..13886131bb 100644
--- a/src/southbridge/intel/ibexpeak/smbus.c
+++ b/src/southbridge/intel/ibexpeak/smbus.c
@@ -33,8 +33,6 @@ static struct device_operations smbus_ops = {
 };
 
 static const unsigned short pci_device_ids[] = {
-	0x1c22,
-	0x1e22,
 	PCI_DID_INTEL_IBEXPEAK_SMBUS,
 	0
 };

From 0f450a8d9cc986da99968a1854c28f07f7d9b77f Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Thu, 15 Jan 2026 20:04:01 +0000
Subject: [PATCH 3051/3886] mb/starlabs/starlite: Set card_reader fallback
 value to 0

The `card_reader` option is only available on specific boards,
so to avoid enabling a USB port that isn't connected, set the
fallback value to 0 instead of 1.

Change-Id: Ied540d6242758663db7a7a11fbefb5c4a84b942d
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90770
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/starlabs/starlite_adl/variants/mk_v/devtree.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/mainboard/starlabs/starlite_adl/variants/mk_v/devtree.c b/src/mainboard/starlabs/starlite_adl/variants/mk_v/devtree.c
index 35d289c7ad..cc8dd4a7b9 100644
--- a/src/mainboard/starlabs/starlite_adl/variants/mk_v/devtree.c
+++ b/src/mainboard/starlabs/starlite_adl/variants/mk_v/devtree.c
@@ -78,6 +78,6 @@ void devtree_update(void)
 		gna_dev->enabled = 0;
 
 	/* Enable/Disable Card Reader based on CMOS Settings */
-	if (get_uint_option("card_reader", 1) == 0)
+	if (get_uint_option("card_reader", 0) == 0)
 		cfg->usb2_ports[3].enable = 0;
 }

From d94d4b8a2500d96685b2bd94e9e16887072fbd79 Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Fri, 2 Jan 2026 16:40:02 +0000
Subject: [PATCH 3052/3886] mb/starlabs/starlite_adl: Add trace length for the
 card reader

Add the trace length for the card reader USB port, and based on this
value adjust the macro used accordingly.

Change-Id: I1c7661f492b9193b75ed39abb2f5d14614cfc213
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90675
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 .../starlabs/starlite_adl/variants/mk_v/devicetree.cb         | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/mainboard/starlabs/starlite_adl/variants/mk_v/devicetree.cb b/src/mainboard/starlabs/starlite_adl/variants/mk_v/devicetree.cb
index 10680827c6..b0080bd292 100644
--- a/src/mainboard/starlabs/starlite_adl/variants/mk_v/devicetree.cb
+++ b/src/mainboard/starlabs/starlite_adl/variants/mk_v/devicetree.cb
@@ -85,8 +85,8 @@ chip soc/intel/alderlake
 			# Internal Bluetooth			1874 mil
 			register "usb2_ports[9]"		= "USB2_PORT_SHORT(OC_SKIP)"
 
-			# Card Reader
-			register "usb2_ports[3]"		= "USB2_PORT_MID(OC_SKIP)"
+			# Card Reader				3926 mil
+			register "usb2_ports[3]"		= "USB2_PORT_SHORT(OC_SKIP)"
 
 			chip drivers/usb/acpi
 				device ref xhci_root_hub on

From 8cfc71d9e07e79d9be262e35a97e2bd204324e90 Mon Sep 17 00:00:00 2001
From: Yu-Ping Wu <yupingso@chromium.org>
Date: Tue, 13 Jan 2026 11:48:42 +0800
Subject: [PATCH 3053/3886] libpayload: Pass panel power-off commands to
 payloads

Introduce the lb_panel_poweroff/cb_panel_poweroff structs to pass the
panel power-off commands from coreboot to payloads.

Also add mipi_panel_parse_commands() to libpayload libc, so that
payloads can utilize it to parse the power-off commands.

BUG=b:474187570
TEST=emerge-jedi coreboot libpayload
BRANCH=skywalker

Change-Id: I652178c8075a1f3aee356502e682ef9a4f3d1cf8
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90738
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Chen-Tsung Hsieh <chentsung@google.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
---
 payloads/libpayload/include/coreboot_tables.h     | 9 +++++++++
 payloads/libpayload/include/libpayload.h          | 1 +
 payloads/libpayload/include/sysinfo.h             | 1 +
 payloads/libpayload/libc/Makefile.mk              | 1 +
 payloads/libpayload/libc/coreboot.c               | 8 ++++++++
 src/commonlib/include/commonlib/coreboot_tables.h | 9 +++++++++
 6 files changed, 29 insertions(+)

diff --git a/payloads/libpayload/include/coreboot_tables.h b/payloads/libpayload/include/coreboot_tables.h
index 01d86c272c..36ec6e9125 100644
--- a/payloads/libpayload/include/coreboot_tables.h
+++ b/payloads/libpayload/include/coreboot_tables.h
@@ -85,6 +85,7 @@ enum {
 	CB_TAG_TYPE_C_INFO		= 0x0042,
 	CB_TAG_ACPI_RSDP                = 0x0043,
 	CB_TAG_PCIE			= 0x0044,
+	CB_TAG_PANEL_POWEROFF		= 0x0049,
 	CB_TAG_CMOS_OPTION_TABLE	= 0x00c8,
 	CB_TAG_OPTION			= 0x00c9,
 	CB_TAG_OPTION_ENUM		= 0x00ca,
@@ -446,6 +447,14 @@ struct cb_acpi_rsdp {
 	cb_uint64_t rsdp_pointer; /* Address of the ACPI RSDP */
 };
 
+struct cb_panel_poweroff {
+	uint32_t tag;
+	uint32_t size;
+
+	/* MIPI DSI poweroff commands from panel_serializable_data. */
+	uint8_t cmd[];
+};
+
 enum boot_mode_t {
 	CB_BOOT_MODE_NORMAL,
 	CB_BOOT_MODE_LOW_BATTERY,
diff --git a/payloads/libpayload/include/libpayload.h b/payloads/libpayload/include/libpayload.h
index 86429144ec..6125fe0285 100644
--- a/payloads/libpayload/include/libpayload.h
+++ b/payloads/libpayload/include/libpayload.h
@@ -47,6 +47,7 @@
 #include <cbgfx.h>
 #if CONFIG(LP_GPL)
 #include <commonlib/helpers.h>
+#include <commonlib/mipi/cmd.h>
 #else
 #include <commonlib/bsd/helpers.h>
 #endif
diff --git a/payloads/libpayload/include/sysinfo.h b/payloads/libpayload/include/sysinfo.h
index 23e2d55409..324233170e 100644
--- a/payloads/libpayload/include/sysinfo.h
+++ b/payloads/libpayload/include/sysinfo.h
@@ -180,6 +180,7 @@ struct sysinfo_t {
 	enum boot_mode_t boot_mode;
 
 	uintptr_t memory_info;
+	uintptr_t cb_panel_poweroff;
 };
 
 extern struct sysinfo_t lib_sysinfo;
diff --git a/payloads/libpayload/libc/Makefile.mk b/payloads/libpayload/libc/Makefile.mk
index 063118a925..45152f135c 100644
--- a/payloads/libpayload/libc/Makefile.mk
+++ b/payloads/libpayload/libc/Makefile.mk
@@ -52,5 +52,6 @@ libc-srcs += $(coreboottop)/src/commonlib/bsd/string.c
 ifeq ($(CONFIG_LP_GPL),y)
 libc-srcs += $(coreboottop)/src/commonlib/device_tree.c
 libc-srcs += $(coreboottop)/src/commonlib/list.c
+libc-srcs += $(coreboottop)/src/commonlib/mipi/cmd.c
 endif
 endif
diff --git a/payloads/libpayload/libc/coreboot.c b/payloads/libpayload/libc/coreboot.c
index b1be37c19e..bd05d7c04a 100644
--- a/payloads/libpayload/libc/coreboot.c
+++ b/payloads/libpayload/libc/coreboot.c
@@ -301,6 +301,11 @@ static void cb_parse_rsdp(void *ptr, struct sysinfo_t *info)
 	info->acpi_rsdp = cb_acpi_rsdp->rsdp_pointer;
 }
 
+static void cb_parse_panel_poweroff(unsigned char *ptr, struct sysinfo_t *info)
+{
+	info->cb_panel_poweroff = virt_to_phys(ptr);
+}
+
 int cb_parse_header(void *addr, int len, struct sysinfo_t *info)
 {
 	struct cb_header *header;
@@ -447,6 +452,9 @@ int cb_parse_header(void *addr, int len, struct sysinfo_t *info)
 		case CB_TAG_PCIE:
 			cb_parse_pcie(ptr, info);
 			break;
+		case CB_TAG_PANEL_POWEROFF:
+			cb_parse_panel_poweroff(ptr, info);
+			break;
 		case CB_TAG_BOOT_MODE:
 			cb_parse_boot_mode(ptr, info);
 			break;
diff --git a/src/commonlib/include/commonlib/coreboot_tables.h b/src/commonlib/include/commonlib/coreboot_tables.h
index fcc7761044..ed5d52f0b5 100644
--- a/src/commonlib/include/commonlib/coreboot_tables.h
+++ b/src/commonlib/include/commonlib/coreboot_tables.h
@@ -91,6 +91,7 @@ enum {
 	LB_TAG_CAPSULE			= 0x0046,
 	LB_TAG_CFR_ROOT			= 0x0047,
 	LB_TAG_ROOT_BRIDGE_INFO		= 0x0048,
+	LB_TAG_PANEL_POWEROFF		= 0x0049,
 	/* The following options are CMOS-related */
 	LB_TAG_CMOS_OPTION_TABLE	= 0x00c8,
 	LB_TAG_OPTION			= 0x00c9,
@@ -629,6 +630,14 @@ struct lb_cfr {
 	/* struct lb_cfr_option_form		forms[] */
 };
 
+struct lb_panel_poweroff {
+	uint32_t tag;
+	uint32_t size;
+
+	/* MIPI DSI poweroff commands from panel_serializable_data. */
+	uint8_t cmd[];
+};
+
 enum boot_mode_t {
 	LB_BOOT_MODE_NORMAL,
 	LB_BOOT_MODE_LOW_BATTERY,

From 03b47f947fef5e584c5e0ec4cb739934cffd8d47 Mon Sep 17 00:00:00 2001
From: Yu-Ping Wu <yupingso@chromium.org>
Date: Tue, 13 Jan 2026 16:29:10 +0800
Subject: [PATCH 3054/3886] soc/mediatek: Add mtk_get_mipi_panel_data() API

Introduce mtk_get_mipi_panel_data() API for the mainboard code to get
the MIPI panel data.

BUG=b:474187570
TEST=emerge-jedi coreboot
BRANCH=skywalker

Change-Id: Ibd3bccb7ce164a4ad3d6cb36345514240495e62f
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90739
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Chen-Tsung Hsieh <chentsung@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/soc/mediatek/common/display.c             | 9 +++++++--
 src/soc/mediatek/common/include/soc/display.h | 2 ++
 2 files changed, 9 insertions(+), 2 deletions(-)

diff --git a/src/soc/mediatek/common/display.c b/src/soc/mediatek/common/display.c
index 08139dfc3d..9d2c873838 100644
--- a/src/soc/mediatek/common/display.c
+++ b/src/soc/mediatek/common/display.c
@@ -16,6 +16,8 @@
 #include <symbols.h>
 #include <timestamp.h>
 
+static struct panel_serializable_data *mipi_data;
+
 static struct panel_serializable_data *get_mipi_cmd_from_cbfs(struct panel_description *desc)
 {
 	/*
@@ -136,8 +138,6 @@ int mtk_display_init(void)
 			return -1;
 		}
 	} else {
-		struct panel_serializable_data *mipi_data = NULL;
-
 		if (panel->get_edid) {
 			if (panel->get_edid(&edid) < 0)
 				return -1;
@@ -239,3 +239,8 @@ u32 mtk_get_vrefresh(const struct edid *edid)
 
 	return vrefresh;
 }
+
+const struct panel_serializable_data *mtk_get_mipi_panel_data(void)
+{
+	return mipi_data;
+}
diff --git a/src/soc/mediatek/common/include/soc/display.h b/src/soc/mediatek/common/include/soc/display.h
index 62ea9b0c23..3e3b4a2164 100644
--- a/src/soc/mediatek/common/include/soc/display.h
+++ b/src/soc/mediatek/common/include/soc/display.h
@@ -40,4 +40,6 @@ void mtk_ddp_mode_set(const struct edid *edid, enum disp_path_sel path,
 void mtk_ddp_ovlsys_start(uintptr_t fb_addr, const struct edid *edid,
 			  enum disp_path_sel path);
 
+const struct panel_serializable_data *mtk_get_mipi_panel_data(void);
+
 #endif

From c0998983d0002741aaa2e3068e75fba189ed754a Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Wed, 14 Jan 2026 13:49:47 -0600
Subject: [PATCH 3055/3886] ec/google/chromeec: Fix uninitialized buffer in
 cbi_get_uint32()

Commit e59c5abd13e6 ("ec/google/chromeec: Add
EC_GOOGLE_CHROMEEC_FW_CONFIG_FROM_UFSC") refactored cbi_get_uint32() to
write directly to the caller's buffer instead of using a local variable.
This caused uninitialized memory (containing garbage addresses) to be
passed to the EC as the return buffer during CBI reads.

In the case of google/zork, the call to
google_chromeec_cbi_get_board_version() returned garbage data (e.g.,
0xae6ccd05 vs 0x5)  which caused incorrect code paths to be taken:

- variant_override_gpio_table() selected wrong GPIO tables based on
  invalid board version comparisons
- variant_touchscreen_update() skipped touchscreen GPIO configuration
  because variant_uses_v3_6_schematics() returned true for garbage
  values
- variant_uses_codec_gpi() returned wrong value, preventing
  headphone jack interrupt setup

These misconfigurations caused input devices (touchpad, touchscreen,
trackpoint) to be non-functional, despite being detected by the OS.

The fix restores the original behavior by using a local variable
initialized to 0, ensuring a clean buffer is always passed to the EC.

TEST=build/boot google/zork, verify board version is read correctly,
all input devices functional under Linux/Windows.

Change-Id: Ia7be0bcc588075ab5c994edc3d68e979cc01ac79
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90761
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/ec/google/chromeec/ec.c | 7 ++++++-
 1 file changed, 6 insertions(+), 1 deletion(-)

diff --git a/src/ec/google/chromeec/ec.c b/src/ec/google/chromeec/ec.c
index f4da831006..ee04d4a669 100644
--- a/src/ec/google/chromeec/ec.c
+++ b/src/ec/google/chromeec/ec.c
@@ -841,7 +841,12 @@ static int cbi_read(void *buf, size_t bufsize, uint32_t tag, bool check_size)
 
 static int cbi_get_uint32(uint32_t *id, uint32_t tag)
 {
-	return cbi_read(id, sizeof(*id), tag, true);
+	uint32_t r = 0;
+	int rv = cbi_read(&r, sizeof(r), tag, true);
+	if (rv)
+		return rv;
+	*id = r;
+	return 0;
 }
 
 int google_chromeec_cbi_get_sku_id(uint32_t *id)

From 4374bbd37b026972c24c000f3fdce73410b98d0b Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Wed, 14 Jan 2026 16:44:10 -0600
Subject: [PATCH 3056/3886] payloads/ipxe: Update and use the stable version

Recent changes to iPXE related to UEFI SecureBoot handling are causing
builds to break, so update the "stable" tag to the last commit in
December 2025 and use that by default until things are sorted out in
the master branch.

TEST=build samsung/stumpy with iPXE for edk2

Change-Id: I5ccdbbf35273cf1e963b913327ffa94df46a1497
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90771
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 payloads/external/iPXE/Kconfig  | 6 +++---
 payloads/external/iPXE/Makefile | 2 +-
 2 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/payloads/external/iPXE/Kconfig b/payloads/external/iPXE/Kconfig
index 14f8898f4e..31686c8916 100644
--- a/payloads/external/iPXE/Kconfig
+++ b/payloads/external/iPXE/Kconfig
@@ -53,15 +53,15 @@ if BUILD_IPXE
 
 choice
 	prompt "iPXE version"
-	default IPXE_MASTER
+	default IPXE_STABLE
 
 config IPXE_STABLE
-	bool "2022.1"
+	bool "2025.12"
 	help
 	  iPXE uses a rolling release with no stable version, for
 	  reproducibility, use the last commit of a given month as the
 	  'stable' version.
-	  This is iPXE from the end of January, 2022.
+	  This is iPXE from the end of December, 2025.
 
 config IPXE_MASTER
 	bool "master"
diff --git a/payloads/external/iPXE/Makefile b/payloads/external/iPXE/Makefile
index a58d5f79ce..284d4275b4 100644
--- a/payloads/external/iPXE/Makefile
+++ b/payloads/external/iPXE/Makefile
@@ -2,7 +2,7 @@
 
 # 2022.1 - Last commit of January 2022
 # When updating, change the name both here and in payloads/external/iPXE/Kconfig
-STABLE_COMMIT_ID=6ba671acd922ee046b257c5119b8a0f64d275473
+STABLE_COMMIT_ID=7c39c04a537ce29dccc6f2bae9749d1d371429c1
 
 TAG-$(CONFIG_IPXE_MASTER)=origin/master
 TAG-$(CONFIG_IPXE_STABLE)=$(STABLE_COMMIT_ID)

From 3b18467e8a91a1b8e1d612da0b602c87665806e5 Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Wed, 14 Jan 2026 17:04:41 -0600
Subject: [PATCH 3057/3886] payloads/ipxe: Unconditionally restore config files
 post-build

Replace backup file mechanism with git restore to fix restoration
bugs and simplify the build system. Files are now always restored
after build completion, ensuring a clean git state regardless of
which configuration options modify the config files.

TEST=build samsung/stumpy with iPXE for edk2 twice in a row without
failure due to dirty repo state.

Change-Id: I9c88f5ca5e5a0172f7c0a94e4edfe0192340d1e2
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90772
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 payloads/external/iPXE/Makefile | 13 +------------
 1 file changed, 1 insertion(+), 12 deletions(-)

diff --git a/payloads/external/iPXE/Makefile b/payloads/external/iPXE/Makefile
index 284d4275b4..a9fb43f846 100644
--- a/payloads/external/iPXE/Makefile
+++ b/payloads/external/iPXE/Makefile
@@ -42,15 +42,10 @@ checkout: fetch
 
 config: checkout
 ifeq ($(CONSOLE_SERIAL),yy)
-	cp "$(project_dir)/src/config/console.h" "$(project_dir)/src/config/console.h.cb"
-	cp "$(project_dir)/src/config/serial.h" "$(project_dir)/src/config/serial.h.cb"
 	sed -i'' 's|//#define\s*CONSOLE_SERIAL.*|#define CONSOLE_SERIAL|' "$(project_dir)/src/config/console.h"
 	sed -i'' 's|#define\s*COMCONSOLE.*|#define COMCONSOLE $(IPXE_UART)|' "$(project_dir)/src/config/serial.h"
 	sed -i'' 's|#define\s*COMSPEED.*|#define COMSPEED $(CONFIG_TTYS0_BAUD)|'  "$(project_dir)/src/config/serial.h"
 endif
-ifneq ($(filter y,$(CONFIG_HAS_SCRIPT) $(CONFIG_IPXE_NO_PROMPT)),)
-	cp "$(project_dir)/src/config/general.h" "$(project_dir)/src/config/general.h.cb"
-endif
 ifeq ($(CONFIG_HAS_SCRIPT),y)
 	sed -i'' 's|//#define\s*IMAGE_SCRIPT.*|#define IMAGE_SCRIPT|' "$(project_dir)/src/config/general.h"
 endif
@@ -73,13 +68,7 @@ else
 	$(MAKE) -C $(project_dir)/src $(IPXE_BUILD_TARGET) $(PXE_MAKE_OPTS)
 endif
 	cp $(project_dir)/src/$(IPXE_BUILD_TARGET) $(project_dir)/ipxe.rom
-ifeq ($(CONSOLE_SERIAL),yy)
-	cp "$(project_dir)/src/config/console.h.cb" "$(project_dir)/src/config/console.h"
-	cp "$(project_dir)/src/config/serial.h.cb" "$(project_dir)/src/config/serial.h"
-endif
-ifneq ($(filter y,$(CONFIG_HAS_SCRIPT) $(CONFIG_IPXE_NO_PROMPT)),)
-	cp "$(project_dir)/src/config/general.h.cb" "$(project_dir)/src/config/general.h"
-endif
+	cd $(project_dir) && git restore src/config/console.h src/config/serial.h src/config/general.h
 
 clean:
 	test -d $(project_dir) && $(MAKE) -C $(project_dir)/src veryclean || exit 0

From d5fb4becd5890ad584e7488948c4ad84a192907b Mon Sep 17 00:00:00 2001
From: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Date: Fri, 16 Jan 2026 15:18:29 +0800
Subject: [PATCH 3058/3886] mb/google/nissa/var/yavilla: Update DTT parameters

This CL update max TDP from 6W to 7W as requested by thermal team.

Increase tdp_pl1_override value from 6 W to 7 W.
Increase PL1 max power value from 6 W to 7 W.

The settings has been verified by thermal team.

BUG=b:476292154, b:476292156
TEST=emerge-nissa coreboot chromeos-bootimage
     verified test result by thermal team

Change-Id: Iaedfb2caec589dd5f5be5cc872e302d55fa51dd6
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90774
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
---
 .../google/brya/variants/yavilla/overridetree.cb          | 8 +++++++-
 1 file changed, 7 insertions(+), 1 deletion(-)

diff --git a/src/mainboard/google/brya/variants/yavilla/overridetree.cb b/src/mainboard/google/brya/variants/yavilla/overridetree.cb
index 588919da54..8ed08cc0d3 100644
--- a/src/mainboard/google/brya/variants/yavilla/overridetree.cb
+++ b/src/mainboard/google/brya/variants/yavilla/overridetree.cb
@@ -113,6 +113,12 @@ chip soc/intel/alderlake
 		.configure_ext_fivr = 1,
 	}"
 
+	register "power_limits_config[ADL_N_041_6W_CORE]" = "{
+		.tdp_pl1_override = 7,
+		.tdp_pl2_override = 25,
+		.tdp_pl4 = 78,
+	}"
+
 	# Intel Common SoC Config
 	#+-------------------+---------------------------+
 	#| Field             |  Value                    |
@@ -202,7 +208,7 @@ chip soc/intel/alderlake
 				register "controls.power_limits" = "{
 					.pl1 = {
 							.min_power = 3000,
-							.max_power = 6000,
+							.max_power = 7000,
 							.time_window_min = 28 * MSECS_PER_SEC,
 							.time_window_max = 32 * MSECS_PER_SEC,
 							.granularity = 200

From cacc11de4f8ca1f5c65b9cfa53fe042e05c6e88b Mon Sep 17 00:00:00 2001
From: Maximilian Brune <maximilian.brune@9elements.com>
Date: Wed, 7 Jan 2026 22:12:09 +0100
Subject: [PATCH 3059/3886] include/cpu/x86/msr.h: Update return types from int
 -> bool

For all functions which check flags, return a bool type instead of an
int type.

Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: I39f0e2f392ec999f7622ed28c5755dd4d0eecf42
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90776
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
---
 src/include/cpu/x86/msr.h | 30 +++++++++++++++---------------
 1 file changed, 15 insertions(+), 15 deletions(-)

diff --git a/src/include/cpu/x86/msr.h b/src/include/cpu/x86/msr.h
index 2fdb064608..f4f33b40f6 100644
--- a/src/include/cpu/x86/msr.h
+++ b/src/include/cpu/x86/msr.h
@@ -142,77 +142,77 @@ static inline void mca_clear_status(void)
 
 /* Helpers for interpreting MC[i]_STATUS */
 
-static inline int mca_valid(msr_t msr)
+static inline bool mca_valid(msr_t msr)
 {
 	return !!(msr.hi & MCA_STATUS_HI_VAL);
 }
 
-static inline int mca_over(msr_t msr)
+static inline bool mca_over(msr_t msr)
 {
 	return !!(msr.hi & MCA_STATUS_HI_OVERFLOW);
 }
 
-static inline int mca_uc(msr_t msr)
+static inline bool mca_uc(msr_t msr)
 {
 	return !!(msr.hi & MCA_STATUS_HI_UC);
 }
 
-static inline int mca_en(msr_t msr)
+static inline bool mca_en(msr_t msr)
 {
 	return !!(msr.hi & MCA_STATUS_HI_EN);
 }
 
-static inline int mca_miscv(msr_t msr)
+static inline bool mca_miscv(msr_t msr)
 {
 	return !!(msr.hi & MCA_STATUS_HI_MISCV);
 }
 
-static inline int mca_addrv(msr_t msr)
+static inline bool mca_addrv(msr_t msr)
 {
 	return !!(msr.hi & MCA_STATUS_HI_ADDRV);
 }
 
-static inline int mca_pcc(msr_t msr)
+static inline bool mca_pcc(msr_t msr)
 {
 	return !!(msr.hi & MCA_STATUS_HI_PCC);
 }
 
-static inline int mca_tcc(msr_t msr)
+static inline bool mca_tcc(msr_t msr)
 {
 	return !!(msr.hi & MCA_STATUS_HI_TCC);
 }
 
-static inline int mca_syndv(msr_t msr)
+static inline bool mca_syndv(msr_t msr)
 {
 	return !!(msr.hi & MCA_STATUS_HI_SYNDV);
 }
 
-static inline int mca_idv(msr_t msr)
+static inline bool mca_idv(msr_t msr)
 {
 	return !!(msr.hi & MCA_STATUS_HI_COREID_VAL);
 }
 
-static inline int mca_cecc(msr_t msr)
+static inline bool mca_cecc(msr_t msr)
 {
 	return !!(msr.hi & MCA_STATUS_HI_CECC);
 }
 
-static inline int mca_uecc(msr_t msr)
+static inline bool mca_uecc(msr_t msr)
 {
 	return !!(msr.hi & MCA_STATUS_HI_UECC);
 }
 
-static inline int mca_defd(msr_t msr)
+static inline bool mca_defd(msr_t msr)
 {
 	return !!(msr.hi & MCA_STATUS_HI_DEFERRED);
 }
 
-static inline int mca_poison(msr_t msr)
+static inline bool mca_poison(msr_t msr)
 {
 	return !!(msr.hi & MCA_STATUS_HI_POISON);
 }
 
-static inline int mca_sublink(msr_t msr)
+static inline bool mca_sublink(msr_t msr)
 {
 	return !!(msr.hi & MCA_STATUS_HI_SUBLINK);
 }

From a12663fd88c04f4afceb20ee06bb5416747d082c Mon Sep 17 00:00:00 2001
From: Patrick Rudolph <patrick.rudolph@9elements.com>
Date: Tue, 30 Sep 2025 15:11:01 +0200
Subject: [PATCH 3060/3886] drivers/spi: Allow SoC to provide the SPI flash CS
 index

On AMD platforms the PSP can boot from different SPI CS lines
and do a recovery boot in case the default CS0 isn't usable.

Allow the SoC to provide the current boot_device CS line by
adding a new weak function.

Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: Ic9ed54b7979405d433f22458265f09701cda842e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90777
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
---
 src/drivers/spi/boot_device_rw_nommap.c | 7 ++++++-
 src/drivers/spi/cbfs_spi.c              | 7 ++++++-
 src/include/boot_device.h               | 3 +++
 3 files changed, 15 insertions(+), 2 deletions(-)

diff --git a/src/drivers/spi/boot_device_rw_nommap.c b/src/drivers/spi/boot_device_rw_nommap.c
index 58efc87fe9..86581600d1 100644
--- a/src/drivers/spi/boot_device_rw_nommap.c
+++ b/src/drivers/spi/boot_device_rw_nommap.c
@@ -8,6 +8,11 @@
 static struct spi_flash sfg;
 static bool sfg_init_done;
 
+__weak int boot_device_spi_cs(void)
+{
+	return 0;	/* Default to chip select 0 */
+}
+
 static ssize_t spi_readat(const struct region_device *rd, void *b,
 				size_t offset, size_t size)
 {
@@ -47,7 +52,7 @@ static const struct region_device spi_rw =
 static void boot_device_rw_init(void)
 {
 	const int bus = CONFIG_BOOT_DEVICE_SPI_FLASH_BUS;
-	const int cs = 0;
+	const int cs = boot_device_spi_cs();
 
 	if (sfg_init_done == true)
 		return;
diff --git a/src/drivers/spi/cbfs_spi.c b/src/drivers/spi/cbfs_spi.c
index 15a18b72e4..5f3b5ca40a 100644
--- a/src/drivers/spi/cbfs_spi.c
+++ b/src/drivers/spi/cbfs_spi.c
@@ -17,6 +17,11 @@
 static struct spi_flash spi_flash_info;
 static bool spi_flash_init_done;
 
+__weak int boot_device_spi_cs(void)
+{
+	return 0;	/* Default to chip select 0 */
+}
+
 /*
  * SPI speed logging for big transfers available with BIOS_DEBUG. The format is:
  *
@@ -82,7 +87,7 @@ static struct mmap_helper_region_device mdev =
 void boot_device_init(void)
 {
 	int bus = CONFIG_BOOT_DEVICE_SPI_FLASH_BUS;
-	int cs = 0;
+	int cs = boot_device_spi_cs();
 
 	if (spi_flash_init_done == true)
 		return;
diff --git a/src/include/boot_device.h b/src/include/boot_device.h
index 883f37c8c8..1a44aefc03 100644
--- a/src/include/boot_device.h
+++ b/src/include/boot_device.h
@@ -27,6 +27,9 @@ enum bootdev_prot_type {
  * most likely not to work so don't rely on such semantics.
  */
 
+/* Return the chip select index used for probing the SPI flash. */
+int boot_device_spi_cs(void);
+
 /* Return the region_device for the read-only boot device. This is the root
    device for all CBFS boot devices. */
 const struct region_device *boot_device_ro(void);

From cf2c2555f45fa1982de01bc74b759922be6a3e1b Mon Sep 17 00:00:00 2001
From: Uwe Poeche <uwe.poeche@siemens.com>
Date: Wed, 1 Oct 2025 10:21:59 +0200
Subject: [PATCH 3061/3886] mb/siemens/mc_ehl8: Add new board variant based on
 mc_ehl1

This mainboard is based on mc_ehl1. As a first step, it contains a copy
of the mc_ehl1 directory with minimal changes.
Special adaptations for mc_ehl8 mainboard will follow in separate
commits.

TEST=Built siemens/mc_ehl8 successfully.

Change-Id: Icf8e90e7d3ed58ea4500cb6132fef37e32c5a4c2
Signed-off-by: Uwe Poeche <uwe.poeche@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90764
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/siemens/mc_ehl/Kconfig          |   5 +
 src/mainboard/siemens/mc_ehl/Kconfig.name     |   3 +
 .../siemens/mc_ehl/variants/mc_ehl8/Kconfig   |  42 ++++
 .../mc_ehl/variants/mc_ehl8/Makefile.mk       |   7 +
 .../mc_ehl/variants/mc_ehl8/devicetree.cb     | 191 ++++++++++++++++++
 .../siemens/mc_ehl/variants/mc_ehl8/gpio.c    | 178 ++++++++++++++++
 .../siemens/mc_ehl/variants/mc_ehl8/memory.c  |  58 ++++++
 .../siemens/mc_ehl/variants/mc_ehl8/post.c    |  10 +
 8 files changed, 494 insertions(+)
 create mode 100644 src/mainboard/siemens/mc_ehl/variants/mc_ehl8/Kconfig
 create mode 100644 src/mainboard/siemens/mc_ehl/variants/mc_ehl8/Makefile.mk
 create mode 100644 src/mainboard/siemens/mc_ehl/variants/mc_ehl8/devicetree.cb
 create mode 100644 src/mainboard/siemens/mc_ehl/variants/mc_ehl8/gpio.c
 create mode 100644 src/mainboard/siemens/mc_ehl/variants/mc_ehl8/memory.c
 create mode 100644 src/mainboard/siemens/mc_ehl/variants/mc_ehl8/post.c

diff --git a/src/mainboard/siemens/mc_ehl/Kconfig b/src/mainboard/siemens/mc_ehl/Kconfig
index 3db9ad0d52..25715ad9f8 100644
--- a/src/mainboard/siemens/mc_ehl/Kconfig
+++ b/src/mainboard/siemens/mc_ehl/Kconfig
@@ -32,6 +32,9 @@ config BOARD_SIEMENS_MC_EHL6
 config BOARD_SIEMENS_MC_EHL7
 	select BOARD_SIEMENS_BASEBOARD_MC_EHL
 
+config BOARD_SIEMENS_MC_EHL8
+	select BOARD_SIEMENS_BASEBOARD_MC_EHL
+
 source "src/mainboard/siemens/mc_ehl/variants/*/Kconfig"
 
 if BOARD_SIEMENS_BASEBOARD_MC_EHL
@@ -47,6 +50,7 @@ config VARIANT_DIR
 	default "mc_ehl5" if BOARD_SIEMENS_MC_EHL5
 	default "mc_ehl6" if BOARD_SIEMENS_MC_EHL6
 	default "mc_ehl7" if BOARD_SIEMENS_MC_EHL7
+	default "mc_ehl8" if BOARD_SIEMENS_MC_EHL8
 
 config MAINBOARD_PART_NUMBER
 	default "MC EHL1" if BOARD_SIEMENS_MC_EHL1
@@ -56,6 +60,7 @@ config MAINBOARD_PART_NUMBER
 	default "MC EHL5" if BOARD_SIEMENS_MC_EHL5
 	default "MC EHL6" if BOARD_SIEMENS_MC_EHL6
 	default "MC EHL7" if BOARD_SIEMENS_MC_EHL7
+	default "MC EHL8" if BOARD_SIEMENS_MC_EHL8
 
 config DEVICETREE
 	default "variants/\$(CONFIG_VARIANT_DIR)/devicetree.cb"
diff --git a/src/mainboard/siemens/mc_ehl/Kconfig.name b/src/mainboard/siemens/mc_ehl/Kconfig.name
index ffbfc9d124..57eba04f0a 100644
--- a/src/mainboard/siemens/mc_ehl/Kconfig.name
+++ b/src/mainboard/siemens/mc_ehl/Kconfig.name
@@ -22,3 +22,6 @@ config BOARD_SIEMENS_MC_EHL6
 
 config BOARD_SIEMENS_MC_EHL7
 	bool "-> MC EHL7"
+
+config BOARD_SIEMENS_MC_EHL8
+	bool "-> MC EHL8"
diff --git a/src/mainboard/siemens/mc_ehl/variants/mc_ehl8/Kconfig b/src/mainboard/siemens/mc_ehl/variants/mc_ehl8/Kconfig
new file mode 100644
index 0000000000..d07cd32ef8
--- /dev/null
+++ b/src/mainboard/siemens/mc_ehl/variants/mc_ehl8/Kconfig
@@ -0,0 +1,42 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
+if BOARD_SIEMENS_MC_EHL8
+
+config BOARD_SPECIFIC_OPTIONS
+	def_bool y
+	select DRIVERS_I2C_RX6110SA
+	select DRIVERS_I2C_PI608GP
+	select DRIVER_INTEL_I210
+	select INTEL_LPSS_UART_FOR_CONSOLE
+	select NC_FPGA_POST_CODE
+	select MAINBOARD_HAS_TPM2
+	select MEMORY_MAPPED_TPM
+	select TPM_MEASURED_BOOT
+	select TPM_MEASURED_BOOT_INIT_BOOTBLOCK
+
+config FMDFILE
+	default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/mc_ehl.fmd"
+
+config UART_FOR_CONSOLE
+	int
+	default 2
+
+config EARLY_PCI_BRIDGE_DEVICE
+	hex
+	depends on NC_FPGA_POST_CODE
+	default 0x1c
+
+config EARLY_PCI_BRIDGE_FUNCTION
+	hex
+	depends on NC_FPGA_POST_CODE
+	default 0x2
+
+config EARLY_PCI_MMIO_BASE
+	hex
+	depends on NC_FPGA_POST_CODE
+	default 0xfe800000
+
+config SOC_INTEL_ELKHARTLAKE_TCO_NO_REBOOT_EN
+	default y
+
+endif # BOARD_SIEMENS_MC_EHL8
diff --git a/src/mainboard/siemens/mc_ehl/variants/mc_ehl8/Makefile.mk b/src/mainboard/siemens/mc_ehl/variants/mc_ehl8/Makefile.mk
new file mode 100644
index 0000000000..2b78a7a75f
--- /dev/null
+++ b/src/mainboard/siemens/mc_ehl/variants/mc_ehl8/Makefile.mk
@@ -0,0 +1,7 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
+bootblock-y += gpio.c
+romstage-y += memory.c
+ramstage-y += gpio.c
+
+all-$(CONFIG_NC_FPGA_POST_CODE) += post.c
diff --git a/src/mainboard/siemens/mc_ehl/variants/mc_ehl8/devicetree.cb b/src/mainboard/siemens/mc_ehl/variants/mc_ehl8/devicetree.cb
new file mode 100644
index 0000000000..6e85734887
--- /dev/null
+++ b/src/mainboard/siemens/mc_ehl/variants/mc_ehl8/devicetree.cb
@@ -0,0 +1,191 @@
+chip soc/intel/elkhartlake
+
+	device cpu_cluster 0 on end
+
+	# GPE configuration
+	# Note that GPE events called out in ASL code rely on this
+	# route. i.e. If this route changes then the affected GPE
+	# offset bits also need to be changed.
+	register "pmc_gpe0_dw0" = "GPP_B"
+	register "pmc_gpe0_dw1" = "GPP_F"
+	register "pmc_gpe0_dw2" = "GPP_E"
+
+	# FSP configuration
+	register "SaGv" = "SaGv_Disabled"
+
+	# Enable IBECC for the complete memory
+	register "ibecc" = "{
+		.enable = 1,
+		.mode = IBECC_ALL
+	}"
+
+	# USB related UPDs
+	register "usb2_ports[0]" = "USB2_PORT_SHORT(OC_SKIP)"	# USB3/2 Type A port 1
+	register "usb2_ports[1]" = "USB2_PORT_SHORT(OC_SKIP)"	# USB3/2 Type A Port 2
+	register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)"	# Onboard USB
+	register "usb2_ports[3]" = "USB2_PORT_EMPTY"		# Port is unused
+	register "usb2_ports[4]" = "USB2_PORT_EMPTY"		# Port is unused
+	register "usb2_ports[5]" = "USB2_PORT_EMPTY"		# Port is unused
+	register "usb2_ports[6]" = "USB2_PORT_EMPTY"		# Port is unused
+	register "usb2_ports[7]" = "USB2_PORT_EMPTY"		# Port is unused
+	register "usb2_ports[8]" = "USB2_PORT_EMPTY"		# Port is unused
+	register "usb2_ports[9]" = "USB2_PORT_EMPTY"		# Port is unused
+
+	register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)"	# USB3/2 Type A port1
+	register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)"	# USB3/2 Type A port2
+	register "usb3_ports[2]" = "USB3_PORT_EMPTY"		# Port is not used
+	register "usb3_ports[3]" = "USB3_PORT_EMPTY"		# Port is not used
+
+	# Skip the CPU replacement check
+	register "SkipCpuReplacementCheck" = "1"
+
+	# PCIe root ports related UPDs
+	register "PcieClkSrcUsage[0]" = "PCIE_CLK_FREE"
+	register "PcieClkSrcUsage[1]" = "PCIE_CLK_FREE"
+	register "PcieClkSrcUsage[2]" = "PCIE_CLK_FREE"
+	register "PcieClkSrcUsage[3]" = "PCIE_CLK_NOTUSED"
+	register "PcieClkSrcUsage[4]" = "PCIE_CLK_NOTUSED"
+	register "PcieClkSrcUsage[5]" = "PCIE_CLK_NOTUSED"
+
+	register "PcieClkSrcClkReq[0]" = "PCIE_CLK_NOTUSED"
+	register "PcieClkSrcClkReq[1]" = "PCIE_CLK_NOTUSED"
+	register "PcieClkSrcClkReq[2]" = "PCIE_CLK_NOTUSED"
+	register "PcieClkSrcClkReq[3]" = "PCIE_CLK_NOTUSED"
+	register "PcieClkSrcClkReq[4]" = "PCIE_CLK_NOTUSED"
+	register "PcieClkSrcClkReq[5]" = "PCIE_CLK_NOTUSED"
+
+	# Disable all L1 substates for PCIe root ports
+	register "PcieRpL1Substates[0]" = "L1_SS_DISABLED"
+	register "PcieRpL1Substates[1]" = "L1_SS_DISABLED"
+	register "PcieRpL1Substates[2]" = "L1_SS_DISABLED"
+	register "PcieRpL1Substates[3]" = "L1_SS_DISABLED"
+	register "PcieRpL1Substates[6]" = "L1_SS_DISABLED"
+
+	# Disable LTR for all PCIe root ports
+	register "PcieRpLtrDisable[0]" = "true"
+	register "PcieRpLtrDisable[1]" = "true"
+	register "PcieRpLtrDisable[2]" = "true"
+	register "PcieRpLtrDisable[3]" = "true"
+	register "PcieRpLtrDisable[6]" = "true"
+
+	# Storage (SATA/SDCARD/EMMC) related UPDs
+	register "SataSalpSupport" = "0"
+	register "SataPortsEnable[0]" = "1"
+	register "SataPortsEnable[1]" = "1"
+	register "SataPortsDevSlp[0]" = "0"
+	register "SataPortsDevSlp[1]" = "0"
+	register "SataPortsSSD[0]" = "1"
+	register "SataPortsSSD[1]" = "1"
+	register "SataSpeed" = "SATA_GEN2"
+
+	register "ScsEmmcHs400Enabled" = "0"
+	register "ScsEmmcDdr50Enabled" = "1"
+	register "SdCardPowerEnableActiveHigh" = "1"
+
+	# LPSS Serial IO (I2C/UART/GSPI) related UPDs
+	register "SerialIoI2cMode" = "{
+		[PchSerialIoIndexI2C0] = PchSerialIoDisabled,
+		[PchSerialIoIndexI2C1] = PchSerialIoPci,
+		[PchSerialIoIndexI2C2] = PchSerialIoDisabled,
+		[PchSerialIoIndexI2C3] = PchSerialIoDisabled,
+		[PchSerialIoIndexI2C4] = PchSerialIoPci,
+		[PchSerialIoIndexI2C5] = PchSerialIoDisabled,
+		[PchSerialIoIndexI2C6] = PchSerialIoDisabled,
+		[PchSerialIoIndexI2C7] = PchSerialIoDisabled,
+	}"
+
+	register "SerialIoI2cPadsTermination" = "{
+		[PchSerialIoIndexI2C1] = 1,
+		[PchSerialIoIndexI2C4] = 1,
+	}"
+
+	register "SerialIoUartMode" = "{
+		[PchSerialIoIndexUART0] = PchSerialIoPci,
+		[PchSerialIoIndexUART1] = PchSerialIoPci,
+		[PchSerialIoIndexUART2] = PchSerialIoSkipInit,
+	}"
+
+	register "SerialIoUartDmaEnable" = "{
+		[PchSerialIoIndexUART0] = 1,
+		[PchSerialIoIndexUART1] = 1,
+		[PchSerialIoIndexUART2] = 1,
+	}"
+
+	# TSN GBE related UPDs
+	register "PchTsnGbeLinkSpeed" = "Tsn_2_5_Gbps"
+	register "PchTsnGbeSgmiiEnable" = "1"
+
+	# FIVR related settings
+	register "fivr" = "{
+		.fivr_config_en = true,
+		.vcc_low_high_us = 50,
+	}"
+
+	# Disable L1 prefetcher
+	register "L1_prefetcher_disable" = "true"
+
+	# Enable real-time tuning
+	register "realtime_tuning_enable" = "true"
+
+	device domain 0 on
+		device pci 00.0 on	end # Host Bridge
+		device pci 02.0 on	end # Integrated Graphics Device
+
+		device pci 14.0 on	end # USB3.1 xHCI
+
+		device pci 15.0 off	end # I2C0
+		device pci 15.1 on	end # I2C1
+
+		device pci 16.0 hidden	end # Management Engine Interface 1
+
+		device pci 17.0 on	end # SATA
+
+		device pci 19.0 on	end # I2C4
+		device pci 19.2 on	end # UART2
+
+		device pci 1a.0 on	end # eMMC
+
+		device pci 1c.0 on	end # RP1 (pcie0 single VC)
+		device pci 1c.1 on	end # RP2 (pcie0 single VC)
+		device pci 1c.2 on	end # RP3 (pcie0 single VC)
+		device pci 1c.3 on	end # RP4 (pcie0 single VC)
+		device pci 1c.6 on	end # RP7 (pcie3 multi VC)
+
+		device pci 1e.0 on	end # UART0
+		device pci 1e.1 on	end # UART1
+
+
+		device pci 1f.0 on	    # eSPI Interface
+			chip drivers/pc80/tpm
+				device pnp 0c31.0 on end
+			end
+		end
+		device pci 1f.2 hidden	end # Power Management Controller
+		device pci 1f.4	on	    # SMBus
+			# Enable external RTC chip
+			chip drivers/i2c/rx6110sa
+				register "bus_speed" = "I2C_SPEED_STANDARD"
+				register "pmon_sampling" = "PMON_SAMPL_256_MS"
+				register "bks_on" = "0"
+				register "bks_off" = "1"
+				register "iocut_en" = "1"
+				register "set_user_date" = "1"
+				register "user_year" = "04"
+				register "user_month" = "07"
+				register "user_day" = "01"
+				register "user_weekday" = "4"
+				device i2c 0x32 on end  # RTC RX6110 SA
+			end
+			# PI7C9X2G608GP PCIe switch configuration
+			chip drivers/i2c/pi608gp
+				register "gen2_3p5_enable" = "true"
+				register "gen2_3p5_amp" = "AMP_LVL_MV(425)"
+				register "gen2_3p5_deemph" = "DEEMPH_LVL_MV(6, 0)"
+				device i2c 0x6f on
+					ops pi608gp_ops
+				end
+			end
+		end
+		device pci 1f.5 on	end # PCH SPI (flash & TPM)
+	end
+end
diff --git a/src/mainboard/siemens/mc_ehl/variants/mc_ehl8/gpio.c b/src/mainboard/siemens/mc_ehl/variants/mc_ehl8/gpio.c
new file mode 100644
index 0000000000..ea814a09ac
--- /dev/null
+++ b/src/mainboard/siemens/mc_ehl/variants/mc_ehl8/gpio.c
@@ -0,0 +1,178 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <baseboard/variants.h>
+#include <commonlib/helpers.h>
+
+/* Pad configuration in ramstage */
+static const struct pad_config gpio_table[] = {
+	/* Community 0 - GpioGroup GPP_B */
+	PAD_CFG_NF(GPP_B2, NONE, PLTRST, NF1),		/* PMC_VRALERT_N */
+	PAD_CFG_NF(GPP_B3, NONE, PLTRST, NF4),		/* ESPI_ALERT0_N */
+	PAD_CFG_NF(GPP_B4, NONE, PLTRST, NF4),		/* ESPI_ALERT1_N */
+	PAD_NC(GPP_B9, NONE),				/* Not connected */
+	PAD_NC(GPP_B10, NONE),				/* Not connected */
+	PAD_CFG_NF(GPP_B11, NONE, PLTRST, NF1),		/* PMC_ALERT_N */
+	PAD_NC(GPP_B14, NONE),				/* Not connected */
+	PAD_CFG_NF(GPP_B15, NONE, PLTRST, NF5),		/* ESPI_CS1_N */
+	PAD_NC(GPP_B18, NONE),				/* Not connected */
+	PAD_NC(GPP_B19, NONE),				/* Not connected */
+	PAD_NC(GPP_B20, NONE),				/* Not connected */
+	PAD_NC(GPP_B21, NONE),				/* Not connected */
+	PAD_NC(GPP_B22, NONE),				/* Not connected */
+	PAD_NC(GPP_B23, NONE),				/* Not connected */
+
+	/* Community 0 - GpioGroup GPP_T */
+	PAD_CFG_NF(GPP_T4, UP_20K, DEEP, NF1),		/* PSE_GBE0_INT */
+	PAD_CFG_NF(GPP_T5, DN_20K, DEEP, NF1),		/* PSE_GBE0_RST_N */
+	PAD_CFG_NF(GPP_T6, NONE, DEEP, NF1),		/* PSE_GBE0_AUXTS */
+	PAD_CFG_NF(GPP_T7, NONE, DEEP, NF1),		/* PSE_GBE0_PPS */
+	PAD_CFG_NF(GPP_T12, NONE, DEEP, NF2),		/* SIO_UART0_RXD */
+	PAD_CFG_NF(GPP_T13, NONE, DEEP, NF2),		/* SIO_UART0_TXD */
+
+	/* Community 0 - GpioGroup GPP_G */
+	PAD_NC(GPP_G8, NONE),				/* Not connected */
+	PAD_NC(GPP_G9, NONE),				/* Not connected */
+	PAD_NC(GPP_G12, NONE),				/* Not connected */
+	PAD_CFG_NF(GPP_G15, NONE, DEEP, NF1),		/* ESPI_IO_0 */
+	PAD_CFG_NF(GPP_G16, NONE, DEEP, NF1),		/* ESPI_IO_1 */
+	PAD_CFG_NF(GPP_G17, NONE, DEEP, NF1),		/* ESPI_IO_2 */
+	PAD_CFG_NF(GPP_G18, NONE, DEEP, NF1),		/* ESPI_IO_3 */
+	PAD_CFG_GPI(GPP_G19, UP_20K, PLTRST),		/* TPM_IRQ_N */
+	PAD_CFG_NF(GPP_G20, NONE, DEEP, NF1),		/* ESPI_CSO_N */
+	PAD_CFG_NF(GPP_G21, NONE, DEEP, NF1),		/* ESPI_CLK */
+	PAD_CFG_NF(GPP_G22, NONE, DEEP, NF1),		/* ESPI_RST0_N */
+
+	/* Community 1 - GpioGroup GPP_V */
+	PAD_CFG_NF(GPP_V0, UP_20K, DEEP, NF1),		/* EMMC_CMD */
+	PAD_CFG_NF(GPP_V1, UP_20K, DEEP, NF1),		/* EMMC_DATA0 */
+	PAD_CFG_NF(GPP_V2, UP_20K, DEEP, NF1),		/* EMMC_DATA1 */
+	PAD_CFG_NF(GPP_V3, UP_20K, DEEP, NF1),		/* EMMC_DATA2 */
+	PAD_CFG_NF(GPP_V4, UP_20K, DEEP, NF1),		/* EMMC_DATA3 */
+	PAD_CFG_NF(GPP_V5, UP_20K, DEEP, NF1),		/* EMMC_DATA4 */
+	PAD_CFG_NF(GPP_V6, UP_20K, DEEP, NF1),		/* EMMC_DATA5 */
+	PAD_CFG_NF(GPP_V7, UP_20K, DEEP, NF1),		/* EMMC_DATA6 */
+	PAD_CFG_NF(GPP_V8, UP_20K, DEEP, NF1),		/* EMMC_DATA7 */
+	PAD_CFG_NF(GPP_V9, DN_20K, DEEP, NF1),		/* EMMC_RCLK */
+	PAD_CFG_NF(GPP_V10, DN_20K, DEEP, NF1),		/* EMMC_CLK */
+	PAD_CFG_NF(GPP_V11, NONE, DEEP, NF1),		/* EMMC_RESET_N */
+
+	/* Community 1 - GpioGroup GPP_H */
+	PAD_CFG_NF(GPP_H0, DN_20K, DEEP, NF1),		/* PSE_GBE1_INT */
+	PAD_CFG_NF(GPP_H1, DN_20K, DEEP, NF1),		/* PSE_GBE1_RST_N */
+	PAD_CFG_NF(GPP_H2, NONE, DEEP, NF1),		/* PSE_GBE1_AUXTS */
+	PAD_CFG_NF(GPP_H3, NONE, DEEP, NF1),		/* PSE_GBE1_PPS */
+	PAD_CFG_NF(GPP_H8, UP_20K, DEEP, NF1),		/* SIO_I2C4_SDA */
+	PAD_CFG_NF(GPP_H9, UP_20K, DEEP, NF1),		/* SIO_I2C4_SCL */
+
+	/* Community 1 - GpioGroup GPP_D */
+	PAD_CFG_GPO(GPP_D16, 0, DEEP),			/* EMMC_PWR_EN_N */
+
+	/* Community 1 - GpioGroup GPP_U */
+	PAD_CFG_NF(GPP_U0, DN_20K, DEEP, NF1),		/* GBE_INT */
+	PAD_CFG_NF(GPP_U1, DN_20K, DEEP, NF1),		/* GBE_RST_N */
+	PAD_CFG_NF(GPP_U2, NONE, DEEP, NF1),		/* GBE_PPS */
+	PAD_CFG_NF(GPP_U3, NONE, DEEP, NF1),		/* GBE_AUXTS */
+	PAD_NC(GPP_U12, NONE),				/* Not connected */
+	PAD_NC(GPP_U13, NONE),				/* Not connected */
+	PAD_NC(GPP_U16, NONE),				/* Not connected */
+	PAD_NC(GPP_U17, NONE),				/* Not connected */
+	PAD_NC(GPP_U18, NONE),				/* Not connected */
+	PAD_CFG_GPO(GPP_U19, 1, DEEP),			/* UPD_REQ_N */
+
+	/* Community 2 - GpioGroup DSW */
+	PAD_CFG_NF(GPD4, NONE, PLTRST, NF1),		/* SLP_S3 */
+	PAD_CFG_NF(GPD5, NONE, PLTRST, NF1),		/* SLP_S4 */
+	PAD_NC(GPD7, NONE),				/* Not connected */
+	PAD_CFG_NF(GPD10, NONE, PLTRST, NF1),		/* SLP_S5 */
+
+	/* Community 3 - GpioGroup GPP_S */
+	PAD_NC(GPP_S0, NONE),				/* Not connected */
+	PAD_NC(GPP_S1, NONE),				/* Not connected */
+
+	/* Community 3 - GpioGroup GPP_A */
+	PAD_CFG_NF(GPP_A0, NONE, DEEP, NF1),		/* PSE_GBE0_RGMII_TXD3 */
+	PAD_CFG_NF(GPP_A1, NONE, DEEP, NF1),		/* PSE_GBE0_RGMII_TXD2 */
+	PAD_CFG_NF(GPP_A2, NONE, DEEP, NF1),		/* PSE_GBE0_RGMII_TXD1 */
+	PAD_CFG_NF(GPP_A3, NONE, DEEP, NF1),		/* PSE_GBE0_RGMII_TXD0 */
+	PAD_CFG_NF(GPP_A4, NONE, DEEP, NF1),		/* PSE_GBE0_RGMII_TXCLK */
+	PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1),		/* PSE_GBE0_RGMII_TXCTL */
+	PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1),		/* PSE_GBE0_RGMII_RXCLK */
+	PAD_CFG_NF(GPP_A7, NONE, DEEP, NF1),		/* PSE_GBE0_RGMII_RXD3 */
+	PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1),		/* PSE_GBE0_RGMII_RXD2 */
+	PAD_CFG_NF(GPP_A9, NONE, DEEP, NF1),		/* PSE_GBE0_RGMII_RXD1 */
+	PAD_CFG_NF(GPP_A10, NONE, DEEP, NF1),		/* PSE_GBE0_RGMII_RXD0 */
+	PAD_CFG_NF(GPP_A23, NONE, DEEP, NF1),		/* PSE_GBE0_RGMII_RXCTL */
+
+	/* Community 4 - GpioGroup GPP_C */
+	PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1),		/* PSE_GBE0_MDC */
+	PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1),		/* PSE_GBE0_MDIO */
+	PAD_NC(GPP_C5, NONE),				/* Not connected */
+	PAD_CFG_NF(GPP_C6, NONE, DEEP, NF1),		/* PSE_GBE1_MDC */
+	PAD_CFG_NF(GPP_C7, NONE, DEEP, NF1),		/* PSE_GBE1_MDIO */
+	PAD_NC(GPP_C8, NONE),				/* Not connected */
+	PAD_CFG_NF(GPP_C12, NONE, DEEP, NF4),		/* SIO_UART1_RXD */
+	PAD_CFG_NF(GPP_C13, NONE, DEEP, NF4),		/* SIO_UART1_TXD */
+	PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1),		/* GBE_MDIO */
+	PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1),		/* GBE_MDC */
+	PAD_CFG_NF(GPP_C18, NONE, DEEP, NF4),		/* SIO_I2C1_SDA */
+	PAD_CFG_NF(GPP_C19, NONE, DEEP, NF4),		/* SIO_I2C1_SCL */
+
+	/* Community 4 - GpioGroup GPP_F */
+	PAD_NC(GPP_F0, NONE),				/* Not connected */
+	PAD_NC(GPP_F1, NONE),				/* Not connected */
+	PAD_NC(GPP_F2, NONE),				/* Not connected */
+	PAD_NC(GPP_F3, NONE),				/* Not connected */
+	PAD_NC(GPP_F4, NONE),				/* Not connected */
+	PAD_NC(GPP_F5, NONE),				/* Not connected */
+	PAD_NC(GPP_F7, NONE),				/* Not connected */
+	PAD_NC(GPP_F8, NONE),				/* Not connected */
+	PAD_NC(GPP_F10, NONE),				/* Not connected */
+	PAD_NC(GPP_F11, NONE),				/* Not connected */
+	PAD_NC(GPP_F12, NONE),				/* Not connected */
+	PAD_NC(GPP_F13, NONE),				/* Not connected */
+	PAD_NC(GPP_F14, NONE),				/* Not connected */
+	PAD_NC(GPP_F15, NONE),				/* Not connected */
+	PAD_NC(GPP_F16, NONE),				/* Not connected */
+	PAD_NC(GPP_F17, NONE),				/* Not connected */
+	PAD_NC(GPP_F20, NONE),				/* Not connected */
+	PAD_NC(GPP_F21, NONE),				/* Not connected */
+
+	/* Community 4 - GpioGroup GPP_E */
+	PAD_CFG_NF(GPP_E0, NONE, DEEP, NF1),		/* SATA_LED_N */
+	PAD_CFG_NF(GPP_E3, NONE, DEEP, NF1),		/* DDI1_HPD */
+	PAD_CFG_NF(GPP_E5, NONE, DEEP, NF1),		/* DDI1_DDC_SDA */
+	PAD_NC(GPP_E6, NONE),				/* Not connected */
+	PAD_CFG_NF(GPP_E7, NONE, DEEP, NF1),		/* DDI1_DDC_SCL */
+	PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1),		/* DDI0_HPD */
+	PAD_NC(GPP_E15, NONE),				/* Not connected */
+	PAD_NC(GPP_E16, NONE),				/* Not connected */
+	PAD_CFG_NF(GPP_E18, NONE, DEEP, NF1),		/* DDI0_DDC_SDA */
+	PAD_CFG_NF(GPP_E19, NONE, DEEP, NF1),		/* DDI0_DDC_SCL */
+	PAD_NC(GPP_E23, NONE),				/* Not connected */
+
+	/* Community 5 - GpioGroup GPP_R */
+	PAD_NC(GPP_R1, NONE),				/* Not connected */
+	PAD_NC(GPP_R2, NONE),				/* Not connected */
+	PAD_NC(GPP_R3, NONE),				/* Not connected */
+};
+
+/* Early pad configuration in bootblock */
+static const struct pad_config early_gpio_table[] = {
+	PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1),		/* SMB_CLK */
+	PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1),		/* SMB_DATA */
+	PAD_CFG_NF(GPP_C2, NONE, DEEP, NF2),		/* SMB_ALERT_N */
+	PAD_CFG_NF(GPP_C20, NONE, DEEP, NF4),		/* SIO_UART2_RXD */
+	PAD_CFG_NF(GPP_C21, NONE, DEEP, NF4),		/* SIO_UART2_TXD */
+};
+
+const struct pad_config *variant_gpio_table(size_t *num)
+{
+	*num = ARRAY_SIZE(gpio_table);
+	return gpio_table;
+}
+
+const struct pad_config *variant_early_gpio_table(size_t *num)
+{
+	*num = ARRAY_SIZE(early_gpio_table);
+	return early_gpio_table;
+}
diff --git a/src/mainboard/siemens/mc_ehl/variants/mc_ehl8/memory.c b/src/mainboard/siemens/mc_ehl/variants/mc_ehl8/memory.c
new file mode 100644
index 0000000000..a800d30ef1
--- /dev/null
+++ b/src/mainboard/siemens/mc_ehl/variants/mc_ehl8/memory.c
@@ -0,0 +1,58 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <baseboard/variants.h>
+#include <gpio.h>
+#include <soc/meminit.h>
+#include <soc/romstage.h>
+
+static const struct mb_cfg mc_ehl_lpddr4x_memcfg_cfg = {
+	.dq_map[DDR_CH0] = {
+		{0xf, 0xf0},
+		{0xf, 0xf0},
+		{0xff, 0x0},
+		{0x0, 0x0},
+		{0x0, 0x0},
+		{0x0, 0x0}
+	},
+
+	.dq_map[DDR_CH1] = {
+		{0xf, 0xf0},
+		{0xf, 0xf0},
+		{0xff, 0x0},
+		{0x0, 0x0},
+		{0x0, 0x0},
+		{0x0, 0x0}
+	},
+
+	/*
+	 * The dqs_map arrays map the ddr4 pins to the SoC pins
+	 * for both channels.
+	 *
+	 * the index = pin number on ddr4 part
+	 * the value = pin number on SoC
+	 */
+	.dqs_map[DDR_CH0] = {3, 0, 1, 2, 7, 4, 5, 6},
+	.dqs_map[DDR_CH1] = {3, 0, 1, 2, 7, 4, 5, 6},
+
+	/* Baseboard uses 100, 100 and 100 rcomp resistors */
+	.rcomp_resistor = {100, 100, 100},
+
+	.rcomp_targets = {60, 40, 30, 20, 30},
+
+	/* LPDDR4x does not allow interleaved memory */
+	.dq_pins_interleaved = 0,
+
+	/* Baseboard is using config 2 for vref_ca */
+	.vref_ca_config = 2,
+
+	/* Enable Early Command Training */
+	.ect = 1,
+
+	/* Set Board Type */
+	.UserBd = BOARD_TYPE_MOBILE,
+};
+
+const struct mb_cfg *variant_memcfg_config(void)
+{
+	return &mc_ehl_lpddr4x_memcfg_cfg;
+}
diff --git a/src/mainboard/siemens/mc_ehl/variants/mc_ehl8/post.c b/src/mainboard/siemens/mc_ehl/variants/mc_ehl8/post.c
new file mode 100644
index 0000000000..c34e2539bc
--- /dev/null
+++ b/src/mainboard/siemens/mc_ehl/variants/mc_ehl8/post.c
@@ -0,0 +1,10 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <console/console.h>
+#include <nc_fpga.h>
+#include <types.h>
+
+void mainboard_post(uint8_t value)
+{
+	nc_fpga_post(value);
+}

From d81025700805831b4cc36f6b34a3e63c6dc9a501 Mon Sep 17 00:00:00 2001
From: Uwe Poeche <uwe.poeche@siemens.com>
Date: Tue, 7 Oct 2025 08:26:16 +0200
Subject: [PATCH 3062/3886] mb/siemens/mc_ehl8: Configure PCIe root ports

This patch updates the PCIe root port settings, as the PCIe topology
differs from the mc_ehl1 mainboard.

TEST=Booted into OS and verifed that all relevant PCIe devices are
detected.

Change-Id: I0953a139b63080489128cc0a0dc865b65632b575
Signed-off-by: Uwe Poeche <uwe.poeche@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90765
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 .../mc_ehl/variants/mc_ehl8/devicetree.cb     | 22 ++++++++++++++-----
 1 file changed, 16 insertions(+), 6 deletions(-)

diff --git a/src/mainboard/siemens/mc_ehl/variants/mc_ehl8/devicetree.cb b/src/mainboard/siemens/mc_ehl/variants/mc_ehl8/devicetree.cb
index 6e85734887..b4fca918f0 100644
--- a/src/mainboard/siemens/mc_ehl/variants/mc_ehl8/devicetree.cb
+++ b/src/mainboard/siemens/mc_ehl/variants/mc_ehl8/devicetree.cb
@@ -55,19 +55,29 @@ chip soc/intel/elkhartlake
 	register "PcieClkSrcClkReq[5]" = "PCIE_CLK_NOTUSED"
 
 	# Disable all L1 substates for PCIe root ports
-	register "PcieRpL1Substates[0]" = "L1_SS_DISABLED"
-	register "PcieRpL1Substates[1]" = "L1_SS_DISABLED"
 	register "PcieRpL1Substates[2]" = "L1_SS_DISABLED"
 	register "PcieRpL1Substates[3]" = "L1_SS_DISABLED"
+	register "PcieRpL1Substates[4]" = "L1_SS_DISABLED"
+	register "PcieRpL1Substates[5]" = "L1_SS_DISABLED"
 	register "PcieRpL1Substates[6]" = "L1_SS_DISABLED"
 
 	# Disable LTR for all PCIe root ports
-	register "PcieRpLtrDisable[0]" = "true"
-	register "PcieRpLtrDisable[1]" = "true"
 	register "PcieRpLtrDisable[2]" = "true"
 	register "PcieRpLtrDisable[3]" = "true"
+	register "PcieRpLtrDisable[4]" = "true"
+	register "PcieRpLtrDisable[5]" = "true"
 	register "PcieRpLtrDisable[6]" = "true"
 
+        # Enable PCIe PTM (Precision Time Measurement) for all PCIe root ports
+        register "PciePtm[2]" = "true"
+        register "PciePtm[3]" = "true"
+        register "PciePtm[4]" = "true"
+        register "PciePtm[5]" = "true"
+        register "PciePtm[6]" = "true"
+
+        # Determine PCIe root port speed
+        register "PcieRpPcieSpeed[5]" = "2"
+
 	# Storage (SATA/SDCARD/EMMC) related UPDs
 	register "SataSalpSupport" = "0"
 	register "SataPortsEnable[0]" = "1"
@@ -145,10 +155,10 @@ chip soc/intel/elkhartlake
 
 		device pci 1a.0 on	end # eMMC
 
-		device pci 1c.0 on	end # RP1 (pcie0 single VC)
-		device pci 1c.1 on	end # RP2 (pcie0 single VC)
 		device pci 1c.2 on	end # RP3 (pcie0 single VC)
 		device pci 1c.3 on	end # RP4 (pcie0 single VC)
+		device pci 1c.4 on	end # RP5 (pcie1 multi VC)
+		device pci 1c.5 on	end # RP6 (pcie2 multi VC)
 		device pci 1c.6 on	end # RP7 (pcie3 multi VC)
 
 		device pci 1e.0 on	end # UART0

From 483c3e51ae4eaabf844033f01c045ddfe1a16da4 Mon Sep 17 00:00:00 2001
From: Uwe Poeche <uwe.poeche@siemens.com>
Date: Thu, 9 Oct 2025 13:13:34 +0200
Subject: [PATCH 3063/3886] mb/siemens/mc_ehl8: Configure I2C and SMB devices

On this board, different I2C controllers must be activated and a
different RTC chip is used compared to mc_ehl1.

TEST=Booted into OS and verified that all relevant devices are detected.

Change-Id: If2990b7d8d599c6e5f5841d8018d2a3f00dbc515
Signed-off-by: Uwe Poeche <uwe.poeche@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90766
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 .../siemens/mc_ehl/variants/mc_ehl8/Kconfig   |  2 +-
 .../mc_ehl/variants/mc_ehl8/devicetree.cb     | 23 ++++++++++---------
 2 files changed, 13 insertions(+), 12 deletions(-)

diff --git a/src/mainboard/siemens/mc_ehl/variants/mc_ehl8/Kconfig b/src/mainboard/siemens/mc_ehl/variants/mc_ehl8/Kconfig
index d07cd32ef8..b0941d7ed1 100644
--- a/src/mainboard/siemens/mc_ehl/variants/mc_ehl8/Kconfig
+++ b/src/mainboard/siemens/mc_ehl/variants/mc_ehl8/Kconfig
@@ -4,7 +4,7 @@ if BOARD_SIEMENS_MC_EHL8
 
 config BOARD_SPECIFIC_OPTIONS
 	def_bool y
-	select DRIVERS_I2C_RX6110SA
+	select DRIVERS_I2C_RV3028C7
 	select DRIVERS_I2C_PI608GP
 	select DRIVER_INTEL_I210
 	select INTEL_LPSS_UART_FOR_CONSOLE
diff --git a/src/mainboard/siemens/mc_ehl/variants/mc_ehl8/devicetree.cb b/src/mainboard/siemens/mc_ehl/variants/mc_ehl8/devicetree.cb
index b4fca918f0..34cf91baa2 100644
--- a/src/mainboard/siemens/mc_ehl/variants/mc_ehl8/devicetree.cb
+++ b/src/mainboard/siemens/mc_ehl/variants/mc_ehl8/devicetree.cb
@@ -95,18 +95,19 @@ chip soc/intel/elkhartlake
 	# LPSS Serial IO (I2C/UART/GSPI) related UPDs
 	register "SerialIoI2cMode" = "{
 		[PchSerialIoIndexI2C0] = PchSerialIoDisabled,
-		[PchSerialIoIndexI2C1] = PchSerialIoPci,
-		[PchSerialIoIndexI2C2] = PchSerialIoDisabled,
+		[PchSerialIoIndexI2C1] = PchSerialIoDisabled,
+		[PchSerialIoIndexI2C2] = PchSerialIoPci,
 		[PchSerialIoIndexI2C3] = PchSerialIoDisabled,
 		[PchSerialIoIndexI2C4] = PchSerialIoPci,
 		[PchSerialIoIndexI2C5] = PchSerialIoDisabled,
-		[PchSerialIoIndexI2C6] = PchSerialIoDisabled,
+		[PchSerialIoIndexI2C6] = PchSerialIoPci,
 		[PchSerialIoIndexI2C7] = PchSerialIoDisabled,
 	}"
 
 	register "SerialIoI2cPadsTermination" = "{
-		[PchSerialIoIndexI2C1] = 1,
+		[PchSerialIoIndexI2C2] = 1,
 		[PchSerialIoIndexI2C4] = 1,
+		[PchSerialIoIndexI2C6] = 1,
 	}"
 
 	register "SerialIoUartMode" = "{
@@ -141,10 +142,12 @@ chip soc/intel/elkhartlake
 		device pci 00.0 on	end # Host Bridge
 		device pci 02.0 on	end # Integrated Graphics Device
 
+		device pci 10.0 on	end # I2C6
+
 		device pci 14.0 on	end # USB3.1 xHCI
 
 		device pci 15.0 off	end # I2C0
-		device pci 15.1 on	end # I2C1
+		device pci 15.2 on	end # I2C2
 
 		device pci 16.0 hidden	end # Management Engine Interface 1
 
@@ -173,18 +176,16 @@ chip soc/intel/elkhartlake
 		device pci 1f.2 hidden	end # Power Management Controller
 		device pci 1f.4	on	    # SMBus
 			# Enable external RTC chip
-			chip drivers/i2c/rx6110sa
+			chip drivers/i2c/rv3028c7
 				register "bus_speed" = "I2C_SPEED_STANDARD"
-				register "pmon_sampling" = "PMON_SAMPL_256_MS"
-				register "bks_on" = "0"
-				register "bks_off" = "1"
-				register "iocut_en" = "1"
 				register "set_user_date" = "1"
 				register "user_year" = "04"
 				register "user_month" = "07"
 				register "user_day" = "01"
 				register "user_weekday" = "4"
-				device i2c 0x32 on end  # RTC RX6110 SA
+				register "bckup_sw_mode" = "BACKUP_SW_LEVEL"
+				register "cap_charge" = "CHARGE_OFF"
+				device i2c 0x52 on end  # RTC RV3028-C7
 			end
 			# PI7C9X2G608GP PCIe switch configuration
 			chip drivers/i2c/pi608gp

From d420e1fb8735a08592cb80c07889ad323c6dc380 Mon Sep 17 00:00:00 2001
From: Uwe Poeche <uwe.poeche@siemens.com>
Date: Thu, 13 Nov 2025 10:57:45 +0100
Subject: [PATCH 3064/3886] mb/siemens/mc_ehl8: Switch from LPSS UART to legacy
 8250 I/O UART

Replace the memory-mapped LPSS UART2 with I/O port-mapped legacy
8250 UART for the serial console which is placed on mainboard.

- Removing INTEL_LPSS_UART_FOR_CONSOLE activates the
  DRIVERS_UART_8250IO switch by default.
- Change UART_FOR_CONSOLE from 2 to 0 (COM1 at I/O 0x3F8).
- Add SOC_INTEL_COMMON_BLOCK_LPC_COMB_ENABLE (to enable COM2 at I/O
  0x2F8).
- Sort Kconfig switches alphabetically.

TEST=Built and booted on mc_ehl8
- Verifed boot log on COM1.
- Verifed functionality in OS via:
1) stty -F /dev/ttySx 115200 cs8 -cstopb -parenb
2) sending: echo "teststring" > /dev/ttySx
3) receiving: cat /dev/ttySx

Change-Id: I72b2c0e745b40beab862ee3b68fdb6bfc54ed9ed
Signed-off-by: Uwe Poeche <uwe.poeche@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90767
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
---
 src/mainboard/siemens/mc_ehl/variants/mc_ehl8/Kconfig | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/src/mainboard/siemens/mc_ehl/variants/mc_ehl8/Kconfig b/src/mainboard/siemens/mc_ehl/variants/mc_ehl8/Kconfig
index b0941d7ed1..4160e7bc22 100644
--- a/src/mainboard/siemens/mc_ehl/variants/mc_ehl8/Kconfig
+++ b/src/mainboard/siemens/mc_ehl/variants/mc_ehl8/Kconfig
@@ -4,13 +4,13 @@ if BOARD_SIEMENS_MC_EHL8
 
 config BOARD_SPECIFIC_OPTIONS
 	def_bool y
-	select DRIVERS_I2C_RV3028C7
-	select DRIVERS_I2C_PI608GP
 	select DRIVER_INTEL_I210
-	select INTEL_LPSS_UART_FOR_CONSOLE
+	select DRIVERS_I2C_PI608GP
+	select DRIVERS_I2C_RV3028C7
 	select NC_FPGA_POST_CODE
 	select MAINBOARD_HAS_TPM2
 	select MEMORY_MAPPED_TPM
+	select SOC_INTEL_COMMON_BLOCK_LPC_COMB_ENABLE
 	select TPM_MEASURED_BOOT
 	select TPM_MEASURED_BOOT_INIT_BOOTBLOCK
 
@@ -19,7 +19,7 @@ config FMDFILE
 
 config UART_FOR_CONSOLE
 	int
-	default 2
+	default 0
 
 config EARLY_PCI_BRIDGE_DEVICE
 	hex

From 532543027ae43ec2b7f4a74d44b1017f194332a4 Mon Sep 17 00:00:00 2001
From: Uwe Poeche <uwe.poeche@siemens.com>
Date: Thu, 15 Jan 2026 14:03:03 +0100
Subject: [PATCH 3065/3886] mb/siemens/{mc_ehl6,mc_ehl7}: Configure GPIO GPP_G5
 (SD CD) pull-up

On mc_ehl6/7 mainboards, the internal GPIO pull-up is required for the
SD card "Card Detect" signal to function properly.
This patch updates the GPIO configuration accordingly.

TEST=Booted mc_ehl6 and verified the voltage level at the
relevant pin before and after the patch.

Change-Id: I96a381f100dd9886ced030434316125d60a13a72
Signed-off-by: Uwe Poeche <uwe.poeche@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90769
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/siemens/mc_ehl/variants/mc_ehl6/gpio.c | 1 +
 src/mainboard/siemens/mc_ehl/variants/mc_ehl7/gpio.c | 1 +
 2 files changed, 2 insertions(+)

diff --git a/src/mainboard/siemens/mc_ehl/variants/mc_ehl6/gpio.c b/src/mainboard/siemens/mc_ehl/variants/mc_ehl6/gpio.c
index 49f737b868..4ec42c02cf 100644
--- a/src/mainboard/siemens/mc_ehl/variants/mc_ehl6/gpio.c
+++ b/src/mainboard/siemens/mc_ehl/variants/mc_ehl6/gpio.c
@@ -27,6 +27,7 @@ static const struct pad_config gpio_table[] = {
 	PAD_CFG_NF(GPP_T13, NONE, DEEP, NF2),		/* SIO_UART0_TXD */
 
 	/* Community 0 - GpioGroup GPP_G */
+	PAD_CFG_NF(GPP_G5, UP_20K, DEEP, NF1),          /* SD Card Detect */
 	PAD_NC(GPP_G8, NONE),				/* Not connected */
 	PAD_NC(GPP_G9, NONE),				/* Not connected */
 	PAD_CFG_GPI(GPP_G19, UP_20K, PLTRST),		/* TPM_IRQ_N */
diff --git a/src/mainboard/siemens/mc_ehl/variants/mc_ehl7/gpio.c b/src/mainboard/siemens/mc_ehl/variants/mc_ehl7/gpio.c
index 49f737b868..18997f7c0f 100644
--- a/src/mainboard/siemens/mc_ehl/variants/mc_ehl7/gpio.c
+++ b/src/mainboard/siemens/mc_ehl/variants/mc_ehl7/gpio.c
@@ -27,6 +27,7 @@ static const struct pad_config gpio_table[] = {
 	PAD_CFG_NF(GPP_T13, NONE, DEEP, NF2),		/* SIO_UART0_TXD */
 
 	/* Community 0 - GpioGroup GPP_G */
+	PAD_CFG_NF(GPP_G5, UP_20K, DEEP, NF1),		/* SD Card Detect */
 	PAD_NC(GPP_G8, NONE),				/* Not connected */
 	PAD_NC(GPP_G9, NONE),				/* Not connected */
 	PAD_CFG_GPI(GPP_G19, UP_20K, PLTRST),		/* TPM_IRQ_N */

From 18ffcafa61727955dd11a7fc1d5c8d76db8fccf4 Mon Sep 17 00:00:00 2001
From: Kapil Porwal <kapilporwal@google.com>
Date: Wed, 14 Jan 2026 17:50:26 +0530
Subject: [PATCH 3066/3886] mb/google/bluey/quartz: Adjust PS8820 init sequence

List of changes:
- Increase the delay between romstage and ramstage GPIO init sequence.
- Delay the USB host initialization to meet the timing requirements.

BUG=b:475214332
TEST=Verify USB 3.0 storage key detection on Google/Quartz.

Change-Id: Ib6044b1e65fe0fe2fde5b688a9491d6e3fc75727
Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90758
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/google/bluey/mainboard.c | 11 +++++++++++
 src/mainboard/google/bluey/romstage.c  |  6 +++---
 2 files changed, 14 insertions(+), 3 deletions(-)

diff --git a/src/mainboard/google/bluey/mainboard.c b/src/mainboard/google/bluey/mainboard.c
index 91c0f3dfad..6551976f55 100644
--- a/src/mainboard/google/bluey/mainboard.c
+++ b/src/mainboard/google/bluey/mainboard.c
@@ -2,6 +2,7 @@
 
 #include <boot/coreboot_tables.h>
 #include <bootmode.h>
+#include <bootstate.h>
 #include <cbmem.h>
 #include <commonlib/bsd/cbmem_id.h>
 #include <commonlib/coreboot_tables.h>
@@ -93,9 +94,19 @@ static void setup_usb(void)
 	setup_usb_typec();
 
 	enable_usb_camera();
+}
+
+static void setup_usb_late(void *unused)
+{
+	/* Skip USB initialization if boot mode is "low-battery" or "off-mode charging"*/
+	if (is_low_power_boot())
+		return;
+
 	setup_usb_host0();
 }
 
+BOOT_STATE_INIT_ENTRY(BS_DEV_INIT, BS_ON_EXIT, setup_usb_late, NULL);
+
 void lb_add_boot_mode(struct lb_header *header)
 {
 	if (!CONFIG(EC_GOOGLE_CHROMEEC))
diff --git a/src/mainboard/google/bluey/romstage.c b/src/mainboard/google/bluey/romstage.c
index e0f1f05743..aeb1eeda6b 100644
--- a/src/mainboard/google/bluey/romstage.c
+++ b/src/mainboard/google/bluey/romstage.c
@@ -101,6 +101,9 @@ static void early_setup_usb(void)
 
 void platform_romstage_main(void)
 {
+	/* Setup early USB related config */
+	early_setup_usb();
+
 	/* Watchdog must be checked first to avoid erasing watchdog info later. */
 	check_wdog();
 
@@ -120,9 +123,6 @@ void platform_romstage_main(void)
 
 	qclib_rerun();
 
-	/* Setup early USB related config */
-	early_setup_usb();
-
 	/*
 	 * Enable this power rail now for FPMCU stability prior to
 	 * its reset being deasserted in ramstage. This applies

From a974b7668e21d138a3103f903a59e4504d98dd3b Mon Sep 17 00:00:00 2001
From: Ulysse Ballesteros <ulysseballesteros@gmail.com>
Date: Thu, 30 Oct 2025 11:14:04 +0100
Subject: [PATCH 3067/3886] soc/intel/*: Disable InternalGfx w/o iGPU to
 prevent FSP-M/S crash

Add verification to ensure that the integrated GPU is available,
avoiding crashes in FSP-M and FSP-S. The problem was first identified
on Skylake systems where the iGPU is missing or disabled, particularly
when VT-D is enabled, which can cause FSP-S to hang during boot.
Enabling SGX hides the issue, but it also leads to unstable
virtualization.

Apply the fix to Alderlake, Cannonlake, and Tigerlake SoCs in addition
to Skylake.

TEST=Build and boot to OS (Windows, Proxmox). Check to verify
functions work. (Skylake H110 + Xeon E3-1245 V5, E3-1260L V5,
i7-6700K, i3-7100)

Change-Id: I394f46ed5a277218a8dd587705eaecabe59fd110
Signed-off-by: Ulysse Ballesteros <ulysseballesteros@gmail.com>
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89821
Reviewed-by: Walter Sonius <walterav1984@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
---
 src/soc/intel/alderlake/romstage/fsp_params.c  | 16 ++++++++++++++--
 src/soc/intel/cannonlake/romstage/fsp_params.c | 16 ++++++++++------
 src/soc/intel/skylake/chip.c                   | 14 +++++++++++++-
 src/soc/intel/skylake/romstage/fsp_params.c    | 17 +++++++++++++----
 src/soc/intel/tigerlake/romstage/fsp_params.c  | 14 ++++++++++++--
 5 files changed, 62 insertions(+), 15 deletions(-)

diff --git a/src/soc/intel/alderlake/romstage/fsp_params.c b/src/soc/intel/alderlake/romstage/fsp_params.c
index 730b1f82b2..4bb2980b2b 100644
--- a/src/soc/intel/alderlake/romstage/fsp_params.c
+++ b/src/soc/intel/alderlake/romstage/fsp_params.c
@@ -2,6 +2,7 @@
 
 #include <assert.h>
 #include <console/console.h>
+#include <device/pci.h>
 #include <cpu/x86/msr.h>
 #include <cpu/intel/common/common.h>
 #include <cpu/intel/cpu_ids.h>
@@ -152,9 +153,19 @@ static void fill_fspm_igd_params(FSP_M_CONFIG *m_cfg,
 		[DDI_PORT_3] = {&m_cfg->DdiPort3Ddc, &m_cfg->DdiPort3Hpd},
 		[DDI_PORT_4] = {&m_cfg->DdiPort4Ddc, &m_cfg->DdiPort4Hpd},
 	};
-	m_cfg->InternalGfx = get_uint_option("igd_enabled", !CONFIG(SOC_INTEL_DISABLE_IGD)) && is_devfn_enabled(SA_DEVFN_IGD);
-	if (m_cfg->InternalGfx) {
+
+	bool igd_enabled = get_uint_option("igd_enabled", !CONFIG(SOC_INTEL_DISABLE_IGD))
+					   && is_devfn_enabled(SA_DEVFN_IGD);
+
+	/* Probe for no IGD and disable InternalGfx to prevent a crash in FSP-M. */
+	if (igd_enabled && pci_read_config16(SA_DEV_IGD, PCI_VENDOR_ID) == 0xffff) {
+		printk(BIOS_ERR, "igd_enabled is set, but IGD is not present. Disabling IGD.\n");
+		igd_enabled = false;
+	}
+
+	if (igd_enabled) {
 		/* IGD is enabled, set IGD stolen size to 60MB. */
+		m_cfg->InternalGfx = 1;
 		m_cfg->IgdDvmt50PreAlloc = get_uint_option("igd_dvmt_prealloc", IGD_SM_60MB);
 		m_cfg->ApertureSize = get_uint_option("igd_aperture_size", IGD_AP_SZ_256MB);
 		/* DP port config */
@@ -168,6 +179,7 @@ static void fill_fspm_igd_params(FSP_M_CONFIG *m_cfg,
 		}
 	} else {
 		/* IGD is disabled, skip IGD init in FSP. */
+		m_cfg->InternalGfx = 0;
 		m_cfg->IgdDvmt50PreAlloc = 0;
 		/* DP port config */
 		m_cfg->DdiPortAConfig = 0;
diff --git a/src/soc/intel/cannonlake/romstage/fsp_params.c b/src/soc/intel/cannonlake/romstage/fsp_params.c
index 38dfdd8922..c86da261d2 100644
--- a/src/soc/intel/cannonlake/romstage/fsp_params.c
+++ b/src/soc/intel/cannonlake/romstage/fsp_params.c
@@ -30,12 +30,16 @@ void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version)
 
 	m_cfg->HyperThreading = get_uint_option("hyper_threading", CONFIG(FSP_HYPERTHREADING));
 
-	/*
-	 * Probe for no IGD and disable InternalGfx and panel power to prevent a
-	 * crash in FSP-M.
-	 */
-	const bool igd_on = get_uint_option("igd_enabled", !CONFIG(SOC_INTEL_DISABLE_IGD)) && is_devfn_enabled(SA_DEVFN_IGD);
-	if (igd_on && pci_read_config16(SA_DEV_IGD, PCI_VENDOR_ID) != 0xffff) {
+	bool igd_enabled = get_uint_option("igd_enabled", !CONFIG(SOC_INTEL_DISABLE_IGD))
+			&& is_devfn_enabled(SA_DEVFN_IGD);
+
+	/* Probe for no IGD and disable InternalGfx and panel power to prevent a crash in FSP-M. */
+	if (igd_enabled && pci_read_config16(SA_DEV_IGD, PCI_VENDOR_ID) == 0xffff) {
+		printk(BIOS_ERR, "igd_enabled is set, but IGD is not present. Disabling IGD.\n");
+		igd_enabled = false;
+	}
+
+	if (igd_enabled) {
 		/* Set IGD stolen size to 64MB. */
 		m_cfg->InternalGfx = 1;
 		m_cfg->IgdDvmt50PreAlloc = get_uint_option("igd_dvmt_prealloc", IGD_SM_64MB);
diff --git a/src/soc/intel/skylake/chip.c b/src/soc/intel/skylake/chip.c
index 0061c10ae8..a884035f59 100644
--- a/src/soc/intel/skylake/chip.c
+++ b/src/soc/intel/skylake/chip.c
@@ -5,6 +5,7 @@
 #include <acpi/acpi.h>
 #include <console/console.h>
 #include <device/device.h>
+#include <device/pci.h>
 #include <device/pci_ids.h>
 #include <fsp/util.h>
 #include <gpio.h>
@@ -491,7 +492,18 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
 
 	/* Enable VT-d and X2APIC */
 	if (soc_vtd_enabled()) {
-		params->VtdBaseAddress[0] = GFXVT_BASE_ADDRESS;
+		/*
+		* Probe for no IGD and set VtdBaseAddress accordingly to prevent a
+		* crash in FSP-S.
+		*/
+		const struct device *igd_dev = pcidev_path_on_root(SA_DEVFN_IGD);
+		if (igd_dev && pci_read_config16(igd_dev, PCI_VENDOR_ID) != 0xffff) {
+			printk(BIOS_DEBUG, "iGPU present - GFXVT_BASE_ADDRESS set\n");
+			params->VtdBaseAddress[0] = GFXVT_BASE_ADDRESS;
+		} else {
+			printk(BIOS_DEBUG, "No iGPU - GFXVT_BASE_ADDRESS disabled\n");
+			params->VtdBaseAddress[0] = 0;
+		}
 		params->VtdBaseAddress[1] = VTVC0_BASE_ADDRESS;
 		params->X2ApicOptOut = 0;
 		tconfig->VtdDisable = 0;
diff --git a/src/soc/intel/skylake/romstage/fsp_params.c b/src/soc/intel/skylake/romstage/fsp_params.c
index 3ca8a48472..5d59ff18c3 100644
--- a/src/soc/intel/skylake/romstage/fsp_params.c
+++ b/src/soc/intel/skylake/romstage/fsp_params.c
@@ -1,6 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
 #include <assert.h>
+#include <device/pci.h>
 #include <cpu/x86/msr.h>
 #include <fsp/util.h>
 #include <intelblocks/cpulib.h>
@@ -104,7 +105,14 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg,
 static void soc_primary_gfx_config_params(FSP_M_CONFIG *m_cfg,
 				const struct soc_intel_skylake_config *config)
 {
-	m_cfg->InternalGfx = get_uint_option("igd_enabled", !CONFIG(SOC_INTEL_DISABLE_IGD)) && is_devfn_enabled(SA_DEVFN_IGD);
+	bool igd_enabled = get_uint_option("igd_enabled", !CONFIG(SOC_INTEL_DISABLE_IGD))
+			&& is_devfn_enabled(SA_DEVFN_IGD);
+
+	/* Probe for no IGD and disable InternalGfx to prevent a crash in FSP-M. */
+	if (igd_enabled && pci_read_config16(SA_DEV_IGD, PCI_VENDOR_ID) == 0xffff) {
+		printk(BIOS_ERR, "igd_enabled is set, but IGD is not present. Disabling IGD.\n");
+		igd_enabled = false;
+	}
 
 	/*
 	 * If iGPU is enabled, set IGD stolen size to 64MB. The FBC
@@ -116,12 +124,13 @@ static void soc_primary_gfx_config_params(FSP_M_CONFIG *m_cfg,
 	 *
 	 * If disabled, don't reserve memory for it.
 	 */
-	if (m_cfg->InternalGfx) {
-		/* IGD is enabled, set IGD stolen size to 64MB. */
+	if (igd_enabled) {
+		/* Set IGD stolen size to 64MB. */
+		m_cfg->InternalGfx = 1;
 		m_cfg->IgdDvmt50PreAlloc = get_uint_option("igd_dvmt_prealloc", IGD_SM_64MB);
 		m_cfg->ApertureSize = get_uint_option("igd_aperture_size", IGD_AP_SZ_256MB);
 	} else {
-		/* IGD is disabled, skip IGD init in FSP. */
+		m_cfg->InternalGfx = 0;
 		m_cfg->IgdDvmt50PreAlloc = 0;
 	}
 
diff --git a/src/soc/intel/tigerlake/romstage/fsp_params.c b/src/soc/intel/tigerlake/romstage/fsp_params.c
index 3e171b198a..0f6c80cfec 100644
--- a/src/soc/intel/tigerlake/romstage/fsp_params.c
+++ b/src/soc/intel/tigerlake/romstage/fsp_params.c
@@ -6,6 +6,7 @@
 #include <cpu/intel/cpu_ids.h>
 #include <cpu/x86/msr.h>
 #include <device/device.h>
+#include <device/pci.h>
 #include <fsp/util.h>
 #include <gpio.h>
 #include <intelblocks/cpulib.h>
@@ -27,14 +28,23 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg,
 
 	m_cfg->HyperThreading = get_uint_option("hyper_threading", CONFIG(FSP_HYPERTHREADING));
 
-	m_cfg->InternalGfx = get_uint_option("igd_enabled", !CONFIG(SOC_INTEL_DISABLE_IGD)) && is_devfn_enabled(SA_DEVFN_IGD);
+	bool igd_enabled = get_uint_option("igd_enabled", !CONFIG(SOC_INTEL_DISABLE_IGD))
+			&& is_devfn_enabled(SA_DEVFN_IGD);
 
-	if (m_cfg->InternalGfx) {
+	/* Probe for no IGD and disable InternalGfx to prevent a crash in FSP-M. */
+	if (igd_enabled && pci_read_config16(SA_DEV_IGD, PCI_VENDOR_ID) == 0xffff) {
+		printk(BIOS_ERR, "igd_enabled is set, but IGD is not present. Disabling IGD.\n");
+		igd_enabled = false;
+	}
+
+	if (igd_enabled) {
 		/* IGD is enabled, set IGD stolen size to 60MB. */
+		m_cfg->InternalGfx = 1;
 		m_cfg->IgdDvmt50PreAlloc = get_uint_option("igd_dvmt_prealloc", IGD_SM_60MB);
 		m_cfg->ApertureSize = get_uint_option("igd_aperture_size", IGD_AP_SZ_256MB);
 	} else {
 		/* IGD is disabled, skip IGD init in FSP. */
+		m_cfg->InternalGfx = 0;
 		m_cfg->IgdDvmt50PreAlloc = 0;
 	}
 

From 0ee48a475c8da08fc8e42faefc00a249015b8890 Mon Sep 17 00:00:00 2001
From: Yu-Ping Wu <yupingso@chromium.org>
Date: Tue, 13 Jan 2026 14:50:14 +0800
Subject: [PATCH 3068/3886] drivers/mipi: Add power-off commands for
 TM_TL121BVMS07_00C

Add DSI power-off commands for TM_TL121BVMS07_00C, so that payloads can
run it to properly disable the display.

Also refactor the init commands using MIPI_DCS_* macros to improve
readability.

BUG=b:474187570
TEST=emerge-jedi coreboot libpayload
BRANCH=skywalker

Change-Id: I0e7da1d23c658d7f3594cbb651c229057810319c
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90740
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Chen-Tsung Hsieh <chentsung@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/drivers/mipi/panel-TM_TL121BVMS07_00C.c | 11 +++++++++--
 1 file changed, 9 insertions(+), 2 deletions(-)

diff --git a/src/drivers/mipi/panel-TM_TL121BVMS07_00C.c b/src/drivers/mipi/panel-TM_TL121BVMS07_00C.c
index e69d8ebc54..cbc93804c8 100644
--- a/src/drivers/mipi/panel-TM_TL121BVMS07_00C.c
+++ b/src/drivers/mipi/panel-TM_TL121BVMS07_00C.c
@@ -29,11 +29,18 @@ struct panel_serializable_data TM_TL121BVMS07_00C = {
 		PANEL_DCS(0xFF, 0x5A, 0xA5, 0x07),
 		PANEL_DCS(0X29, 0x00),
 		PANEL_DCS(0xFF, 0x5A, 0xA5, 0x00),
-		PANEL_DCS(0x11),
+		PANEL_DCS(MIPI_DCS_EXIT_SLEEP_MODE),
 		PANEL_DELAY(120),
-		PANEL_DCS(0x29),
+		PANEL_DCS(MIPI_DCS_SET_DISPLAY_ON),
 		PANEL_DELAY(20),
 		PANEL_END,
 	},
+	.poweroff = {
+		PANEL_DCS(MIPI_DCS_SET_DISPLAY_OFF),
+		PANEL_DELAY(20),
+		PANEL_DCS(MIPI_DCS_ENTER_SLEEP_MODE),
+		PANEL_DELAY(120),
+		PANEL_END,
+	},
 	.flags = PANEL_FLAG_CPHY,
 };

From d110cf46697fddfe953a3a7ad4b01b4ea39ce009 Mon Sep 17 00:00:00 2001
From: Yu-Ping Wu <yupingso@chromium.org>
Date: Fri, 16 Jan 2026 08:38:02 +0800
Subject: [PATCH 3069/3886] commonlib/mipi/cmd: Add
 mipi_panel_get_commands_len()

Introduce a helper function mipi_panel_get_commands_len() to calculate
the MIPI panel commands array length.

BUG=b:474187570
TEST=emerge-jedi coreboot
BRANCH=skywalker

Change-Id: I3fef37144f6856057b44415caf578629a35fe573
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90773
Reviewed-by: Chen-Tsung Hsieh <chentsung@google.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/commonlib/include/commonlib/mipi/cmd.h |  7 +++++
 src/commonlib/mipi/cmd.c                   | 33 ++++++++++++++++++++++
 2 files changed, 40 insertions(+)

diff --git a/src/commonlib/include/commonlib/mipi/cmd.h b/src/commonlib/include/commonlib/mipi/cmd.h
index 17e0aeda89..ad3c5a7fb4 100644
--- a/src/commonlib/include/commonlib/mipi/cmd.h
+++ b/src/commonlib/include/commonlib/mipi/cmd.h
@@ -5,6 +5,7 @@
 
 #include <commonlib/bsd/cb_err.h>
 #include <commonlib/mipi/dsi.h>
+#include <stddef.h>
 #include <stdint.h>
 
 /* Definitions for cmd in panel_command */
@@ -52,4 +53,10 @@ typedef enum cb_err (*mipi_cmd_func_t)(enum mipi_dsi_transaction type, const u8
 enum cb_err mipi_panel_parse_commands(const void *buf, mipi_cmd_func_t cmd_func,
 				      void *user_data);
 
+/*
+ * Parse a command array and calculate the array length, including the trailing
+ * PANEL_CMD_END. If the array begins with PANEL_CMD_END, 0 will be returned.
+ */
+size_t mipi_panel_get_commands_len(const void *buf);
+
 #endif /* __COMMONLIB_MIPI_CMD_H__ */
diff --git a/src/commonlib/mipi/cmd.c b/src/commonlib/mipi/cmd.c
index 4e5a638d9b..fa52d21c08 100644
--- a/src/commonlib/mipi/cmd.c
+++ b/src/commonlib/mipi/cmd.c
@@ -78,3 +78,36 @@ enum cb_err mipi_panel_parse_commands(const void *buf, mipi_cmd_func_t cmd_func,
 
 	return CB_SUCCESS;
 }
+
+size_t mipi_panel_get_commands_len(const void *buf)
+{
+	const void *const buf_start = buf;
+	const struct panel_command *command = buf;
+
+	if (command->cmd == PANEL_CMD_END)
+		return 0;
+
+	for (; command->cmd != PANEL_CMD_END; command = buf) {
+		buf += sizeof(*command);
+
+		switch (command->cmd) {
+		case PANEL_CMD_DELAY:
+			/*
+			 * For PANEL_CMD_DELAY, the command->len should not be
+			 * counted for buf.
+			 */
+			break;
+		case PANEL_CMD_GENERIC:
+		case PANEL_CMD_DCS:
+			buf += command->len;
+			break;
+		default:
+			printk(BIOS_ERR, "%s: Unknown command code: %d.\n",
+			       __func__, command->cmd);
+			return 0;
+		}
+	}
+
+	/* Add 1 byte for PANEL_CMD_END. */
+	return buf - buf_start + 1;
+}

From 5af56ddf92766c42402f00c9f21a04a72c8bf4a7 Mon Sep 17 00:00:00 2001
From: Yu-Ping Wu <yupingso@chromium.org>
Date: Thu, 15 Jan 2026 16:59:06 +0800
Subject: [PATCH 3070/3886] mb/google/skywalker: Implement lb_board() to pass
 LB_TAG_PANEL_POWEROFF

To allow payloads to run MIPI panel power-off commands, create a new
LB_TAG_PANEL_POWEROFF record and pass it to payloads.

BUG=b:474187570
TEST=emerge-jedi coreboot
BRANCH=skywalker

Change-Id: Ie11e1e78129188cc26d56764449fbafafa8fa316
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90768
Reviewed-by: Chen-Tsung Hsieh <chentsung@google.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/google/skywalker/mainboard.c | 24 ++++++++++++++++++++++
 1 file changed, 24 insertions(+)

diff --git a/src/mainboard/google/skywalker/mainboard.c b/src/mainboard/google/skywalker/mainboard.c
index a0a89fc215..a36e3fa7a2 100644
--- a/src/mainboard/google/skywalker/mainboard.c
+++ b/src/mainboard/google/skywalker/mainboard.c
@@ -1,6 +1,10 @@
 /* SPDX-License-Identifier: GPL-2.0-only OR MIT */
 
+#include <boot/coreboot_tables.h>
 #include <bootmode.h>
+#include <commonlib/coreboot_tables.h>
+#include <commonlib/helpers.h>
+#include <commonlib/mipi/cmd.h>
 #include <device/device.h>
 #include <device/mmio.h>
 #include <fw_config.h>
@@ -166,3 +170,23 @@ struct chip_operations mainboard_ops = {
 	.name = CONFIG_MAINBOARD_PART_NUMBER,
 	.enable_dev = mainboard_enable,
 };
+
+void lb_board(struct lb_header *header)
+{
+	const struct panel_serializable_data *mipi_data = mtk_get_mipi_panel_data();
+
+	if (!mipi_data)
+		return;
+
+	size_t cmd_len = mipi_panel_get_commands_len(mipi_data->poweroff);
+
+	if (!cmd_len)
+		return;
+
+	struct lb_panel_poweroff *panel_poweroff =
+		(struct lb_panel_poweroff *)lb_new_record(header);
+	panel_poweroff->tag = LB_TAG_PANEL_POWEROFF;
+	panel_poweroff->size = ALIGN_UP(sizeof(*panel_poweroff) + cmd_len,
+					LB_ENTRY_ALIGN);
+	memcpy(panel_poweroff->cmd, mipi_data->poweroff, cmd_len);
+}

From d7d4b67c6a7ec4e904abe0f1234cff494414d427 Mon Sep 17 00:00:00 2001
From: Yu-Ping Wu <yupingso@chromium.org>
Date: Mon, 19 Jan 2026 14:37:29 +0800
Subject: [PATCH 3071/3886] commonlib/mipi/cmd: Remove unnecessary 'const void
 *' cast

The 'buf' variable is already 'const void *'.

Change-Id: I0d52f7386853bf353df637085be0f38f787bf6d5
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90797
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Chen-Tsung Hsieh <chentsung@google.com>
---
 src/commonlib/mipi/cmd.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/commonlib/mipi/cmd.c b/src/commonlib/mipi/cmd.c
index fa52d21c08..8c59a83b6e 100644
--- a/src/commonlib/mipi/cmd.c
+++ b/src/commonlib/mipi/cmd.c
@@ -17,7 +17,7 @@ enum cb_err mipi_panel_parse_commands(const void *buf, mipi_cmd_func_t cmd_func,
 	 * to parse and scan.
 	 */
 
-	for (; command->cmd != PANEL_CMD_END; command = (const void *)buf) {
+	for (; command->cmd != PANEL_CMD_END; command = buf) {
 		/*
 		 * For some commands like DELAY, the command->len should not be
 		 * counted for buf.

From b9bd92484715f4deaf31ca451e8a25c6960f218d Mon Sep 17 00:00:00 2001
From: Patrick Rudolph <patrick.rudolph@9elements.com>
Date: Wed, 7 Jan 2026 00:43:39 +0100
Subject: [PATCH 3072/3886] soc/amd/common/block/spi: Implement
 boot_device_spi_cs()

The PSP can choose the SPI flash to boot from. One such case
would be a corrupted EFS or invalid PSP directory tables.
Read the active SPI CS index from register SPI_ALT_CS_REG and
use it in boot_device_spi_cs().

Register name is taken from Linux kernel.

TEST=Booted on AMD/glinda with EFS on SPI CS0 corrupted. Will
     boot from SPI CS2 and log shows:

     spi_init: Booting from SPI CS2

Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: I2c806d4d1563aa2403e84dec9f8768081e5e208a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90778
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
---
 src/soc/amd/common/block/spi/fch_spi_ctrl.c | 23 ++++++++++++++++++---
 1 file changed, 20 insertions(+), 3 deletions(-)

diff --git a/src/soc/amd/common/block/spi/fch_spi_ctrl.c b/src/soc/amd/common/block/spi/fch_spi_ctrl.c
index c4ec4cc9b8..79c916ff34 100644
--- a/src/soc/amd/common/block/spi/fch_spi_ctrl.c
+++ b/src/soc/amd/common/block/spi/fch_spi_ctrl.c
@@ -1,16 +1,24 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
-#include <console/console.h>
-#include <spi_flash.h>
-#include <soc/pci_devs.h>
 #include <amdblocks/lpc.h>
 #include <amdblocks/smi.h>
 #include <amdblocks/spi.h>
+#include <console/console.h>
+#include <boot_device.h>
 #include <device/pci_ops.h>
 #include <lib.h>
+#include <soc/pci_devs.h>
+#include <spi_flash.h>
 #include <timer.h>
 #include <types.h>
 
+/*
+ * Default SPI CS line. When PSP fails to boot from CS0 it will
+ * attempt to boot from other CS lines as well. Keep track of the
+ * boot source for DUAL SPI access support.
+ */
+static uint8_t default_cs;
+
 #define GRANULARITY_TEST_4k		0x0000f000		/* bits 15-12 */
 #define WORD_TO_DWORD_UPPER(x)		((x << 16) & 0xffff0000)
 
@@ -18,6 +26,8 @@
 #define SPI_RESTRICTED_CMD1		0x04
 #define SPI_RESTRICTED_CMD2		0x08
 #define SPI_CNTRL1			0x0c
+#define SPI_ALT_CS_REG			0x1d
+#define   SPI_ALT_CS_REG_MASK		0x03
 #define SPI_CMD_CODE			0x45
 #define SPI_CMD_TRIGGER			0x47
 #define   SPI_CMD_TRIGGER_EXECUTE	BIT(7)
@@ -114,6 +124,13 @@ static int execute_command(void)
 void spi_init(void)
 {
 	printk(BIOS_DEBUG, "%s: SPI BAR at 0x%08lx\n", __func__, spi_get_bar());
+	default_cs = spi_read8(SPI_ALT_CS_REG) & SPI_ALT_CS_REG_MASK;
+	printk(BIOS_DEBUG, "%s: Booting from SPI CS%d\n", __func__, default_cs);
+}
+
+int boot_device_spi_cs(void)
+{
+	return default_cs;
 }
 
 static uint8_t cmd_code;

From 225e635ea1739468af7c84fbedb6ff288c37dd39 Mon Sep 17 00:00:00 2001
From: Patrick Rudolph <patrick.rudolph@9elements.com>
Date: Mon, 21 Jul 2025 15:26:15 +0200
Subject: [PATCH 3073/3886] soc/amd/common/block/spi: Operate on multiple SPI
 flashes

On AMD glinda up to 3 CS# lines are available. Drive the correct
SPI flash chip select using register 0x1d when necessary. This
allows to modifiy the contents of the "backup" SPI flash when
booting from the primary SPI flash.

TEST=Can access backup SPI flash on AMD Glinda SoC.

Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: I446ef54a27c7a29155948cef9219cdef7b52b776
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90779
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
---
 src/soc/amd/common/block/spi/fch_spi_ctrl.c | 21 +++++++++++++++++++++
 1 file changed, 21 insertions(+)

diff --git a/src/soc/amd/common/block/spi/fch_spi_ctrl.c b/src/soc/amd/common/block/spi/fch_spi_ctrl.c
index 79c916ff34..114c733244 100644
--- a/src/soc/amd/common/block/spi/fch_spi_ctrl.c
+++ b/src/soc/amd/common/block/spi/fch_spi_ctrl.c
@@ -134,6 +134,7 @@ int boot_device_spi_cs(void)
 }
 
 static uint8_t cmd_code;
+static uint8_t alt_cs;
 static uint8_t tx_byte_count;
 static uint8_t rx_byte_count;
 static uint8_t fifo[SPI_FIFO_DEPTH];
@@ -144,6 +145,7 @@ void fch_spi_backup_registers(void)
 	if (ENV_SMM && (spi_read8(SPI_MISC_CNTRL) & SPI_SEMAPHORE_BIOS_LOCKED))
 		return;
 
+	alt_cs = spi_read8(SPI_ALT_CS_REG);
 	cmd_code = spi_read8(SPI_CMD_CODE);
 	tx_byte_count = spi_read8(SPI_TX_BYTE_COUNT);
 	rx_byte_count = spi_read8(SPI_RX_BYTE_COUNT);
@@ -158,6 +160,7 @@ void fch_spi_restore_registers(void)
 	if (ENV_SMM && (spi_read8(SPI_MISC_CNTRL) & SPI_SEMAPHORE_BIOS_LOCKED))
 		return;
 
+	spi_write8(SPI_ALT_CS_REG, alt_cs);
 	spi_write8(SPI_CMD_CODE, cmd_code);
 	spi_write8(SPI_TX_BYTE_COUNT, tx_byte_count);
 	spi_write8(SPI_RX_BYTE_COUNT, rx_byte_count);
@@ -350,6 +353,16 @@ static int spi_ctrlr_claim_bus(const struct spi_slave *slave)
 			spi_write8(SPI_MISC_CNTRL, reg8 | SPI_SEMAPHORE_BIOS_LOCKED);
 	}
 
+	/* Set chip select line */
+	if (slave->cs <= 3) {
+		reg8 = spi_read8(SPI_ALT_CS_REG);
+		if ((reg8 & SPI_ALT_CS_REG_MASK) != slave->cs) {
+			reg8 &= ~SPI_ALT_CS_REG_MASK;
+			reg8 |= slave->cs;
+			spi_write8(SPI_ALT_CS_REG, reg8);
+		}
+	}
+
 	return 0;
 }
 
@@ -358,6 +371,14 @@ static void spi_ctrlr_release_bus(const struct spi_slave *slave)
 {
 	uint8_t reg8;
 
+	/* Reset chip select line */
+	reg8 = spi_read8(SPI_ALT_CS_REG);
+	if ((reg8 & SPI_ALT_CS_REG_MASK) != default_cs) {
+		reg8 &= ~SPI_ALT_CS_REG_MASK;
+		reg8 |= default_cs;
+		spi_write8(SPI_ALT_CS_REG, reg8);
+	}
+
 	if (ENV_RAMSTAGE && CONFIG(SOC_AMD_COMMON_BLOCK_PSP_SMI)) {
 		reg8 = spi_read8(SPI_MISC_CNTRL);
 		spi_write8(SPI_MISC_CNTRL, reg8 & ~SPI_SEMAPHORE_BIOS_LOCKED);

From fc20f238f678b9c157a4aa96aefab63de13c737b Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Sun, 18 Jan 2026 20:06:16 +0000
Subject: [PATCH 3074/3886] mb/starlabs/*: Select DRIVERS_EFI_FW_INFO

Select DRIVERS_EFI_FW_INFO as to allow updating with EFI
capsules.

Change-Id: I6f0198cea69397be58693c8d48cf7855a1179771
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90790
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
---
 src/mainboard/starlabs/common/Kconfig | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/src/mainboard/starlabs/common/Kconfig b/src/mainboard/starlabs/common/Kconfig
index 07239c8904..a59bc86dcf 100644
--- a/src/mainboard/starlabs/common/Kconfig
+++ b/src/mainboard/starlabs/common/Kconfig
@@ -4,6 +4,9 @@ if VENDOR_STARLABS
 
 menu "Star Labs Settings"
 
+config DRIVERS_EFI_FW_INFO
+	default y
+
 config MB_COMMON_DIR
 	string
 	default "starlabs/common"

From f070e0add87f9a8bfaafecba2e62ad7d513caf36 Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Sun, 18 Jan 2026 20:21:10 +0000
Subject: [PATCH 3075/3886] mb/starlabs/byte_adl: Fix WOL

The GPIO used for WOL was not configured to support WOL, so configure
this and adjust devicetree accordingly. Also, set the supported state
to S3, as coreboot disables this in S5.

Change-Id: Iaaac1aac3319473fe9e04f44043bf300620915cc
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90791
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 .../starlabs/byte_adl/variants/mk_ii/devicetree.cb          | 6 ++++--
 src/mainboard/starlabs/byte_adl/variants/mk_ii/gpio.c       | 2 +-
 2 files changed, 5 insertions(+), 3 deletions(-)

diff --git a/src/mainboard/starlabs/byte_adl/variants/mk_ii/devicetree.cb b/src/mainboard/starlabs/byte_adl/variants/mk_ii/devicetree.cb
index 40635bde30..ec5d3c03e9 100644
--- a/src/mainboard/starlabs/byte_adl/variants/mk_ii/devicetree.cb
+++ b/src/mainboard/starlabs/byte_adl/variants/mk_ii/devicetree.cb
@@ -155,7 +155,8 @@ chip soc/intel/alderlake
 
 			}"
 			chip drivers/pcie/generic
-				register "wake_gpe" = "GPE0_PME_B0"
+				register "wake_gpe" = "GPE0_LAN_WAK"
+				register "wake_deepest" = "ACPI_S3"
 				device generic 0 on end
 			end
 			smbios_slot_desc				"SlotTypePciExpressGen4x1"
@@ -172,7 +173,8 @@ chip soc/intel/alderlake
 				.PcieRpL1Substates			= L1_SS_L1_2,
 			}"
 			chip drivers/pcie/generic
-				register "wake_gpe" = "GPE0_PME_B0"
+				register "wake_gpe" = "GPE0_LAN_WAK"
+				register "wake_deepest" = "ACPI_S3"
 				device generic 0 on end
 			end
 			smbios_slot_desc				"SlotTypePciExpressGen3X4"
diff --git a/src/mainboard/starlabs/byte_adl/variants/mk_ii/gpio.c b/src/mainboard/starlabs/byte_adl/variants/mk_ii/gpio.c
index bddabb14db..0c0173cb40 100644
--- a/src/mainboard/starlabs/byte_adl/variants/mk_ii/gpio.c
+++ b/src/mainboard/starlabs/byte_adl/variants/mk_ii/gpio.c
@@ -20,6 +20,7 @@ const struct pad_config gpio_table[] = {
 	/* General Purpose I/O Deep */
 	PAD_CFG_NF(GPD0, NONE, DEEP, NF1),				/* Battery Low */
 	PAD_CFG_NF(GPD1, NONE, DEEP, NF1),				/* Charger Connected */
+	PAD_CFG_NF(GPD2, NATIVE, PWROK, NF1),				/* LAN Wake */
 	PAD_CFG_NF(GPD3, UP_20K, DEEP, NF1),				/* Power Button */
 	PAD_CFG_NF(GPD4, NONE, DEEP, NF1),				/* Sleep S3 */
 	PAD_CFG_NF(GPD5, NONE, DEEP, NF1),				/* Sleep S4 */
@@ -99,7 +100,6 @@ const struct pad_config gpio_table[] = {
 	PAD_CFG_GPO(GPP_F7, 0, PLTRST),					/* MCRO LDO		[ Disabled / Bypass   ] */
 	PAD_CFG_GPO(GPD7, 0, PLTRST),					/* RTC Clock Delay	[ Disabled / 95ms     ] */
 
-	PAD_NC(GPD2, NONE),
 	PAD_NC(GPD6, NONE),
 	PAD_NC(GPD9, NONE),
 	PAD_NC(GPD11, NONE),

From 40dbe0807da361951c567cec8192061743ae5a75 Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Fri, 19 Dec 2025 20:38:31 +0000
Subject: [PATCH 3076/3886] Documentation/mb: Add missing entry for
 starfighter_mtl

Change-Id: I6d7dfe2ab0eb1f4c79dfc5f87ddb8666b79a535b
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90569
Reviewed-by: Nicholas <nic.c3.14@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 Documentation/mainboard/index.md              |  1 +
 .../mainboard/starlabs/starfighter_mtl.md     | 92 +++++++++++++++++++
 2 files changed, 93 insertions(+)
 create mode 100644 Documentation/mainboard/starlabs/starfighter_mtl.md

diff --git a/Documentation/mainboard/index.md b/Documentation/mainboard/index.md
index bbfe831fc9..de731f3048 100644
--- a/Documentation/mainboard/index.md
+++ b/Documentation/mainboard/index.md
@@ -360,6 +360,7 @@ StarBook Mk VII (N200) <starlabs/starbook_adl_n.md>
 StarBook Mk VII (165H) <starlabs/starbook_mtl.md>
 Byte Mk II <starlabs/byte_adl.md>
 StarFighter Mk I <starlabs/starfighter_rpl.md>
+StarFighter Mk II <starlabs/starfighter_mtl.md>
 
 Building coreboot <starlabs/common/building.md>
 Flashing devices <starlabs/common/flashing.md>
diff --git a/Documentation/mainboard/starlabs/starfighter_mtl.md b/Documentation/mainboard/starlabs/starfighter_mtl.md
new file mode 100644
index 0000000000..2164b698c5
--- /dev/null
+++ b/Documentation/mainboard/starlabs/starfighter_mtl.md
@@ -0,0 +1,92 @@
+# StarFighter Mk I
+
+## Specs
+
+- CPU (full processor specs available at <https://ark.intel.com>)
+    - Intel 125H (Meteor Lake)
+    - Intel 285H (Arrow Lake)
+- EC
+    - ITE IT5570E
+    - Backlit keyboard, with standard PS/2 keycodes and SCI hotkeys
+    - Battery
+    - USB-C PD Charger
+    - Suspend / resume
+- GPU
+    - Intel® Iris® Xe Graphics
+    - GOP driver is recommended, VBT is provided
+    - eDP 16-inch 3840x2400 or 2560x1600 LCD
+    - HDMI video
+    - USB-C DisplayPort video
+- Memory
+    - 32 or 64GB LPDDR5 on-board memory
+- Networking
+    - AX210 2230 WiFi / Bluetooth
+- Sound
+    - Realtek ALC235
+    - Internal speakers
+    - Removable microphone
+    - Combined headphone / microphone 3.5-mm jack
+    - HDMI audio
+    - USB-C DisplayPort audio
+- Storage
+    - 2 x M.2 PCIe SSD
+    - RTS5129 MicroSD card reader
+- USB
+    - 1920x1080 removable CCD camera
+    - 2 x Thunderbolt 4.0 (left)
+    - USB 3.1 Gen 2 Type-A (left)
+    - USB 3.1 Gen 2 Type-A (right)
+    - USB 3.1 Gen 1 Type-A (right)
+
+## Building coreboot
+
+Please follow the [Star Labs build instructions](common/building.md) to build
+coreboot, using `config.starlabs_starfighter_mtl` as config file.
+
+### Preliminaries
+
+Prior to building coreboot the following files are required:
+* Intel Flash Descriptor file (descriptor.bin)
+* Intel Management Engine firmware (me.bin)
+* ITE Embedded Controller firmware (ec.bin)
+
+The files listed below are optional:
+- Splash screen image in Windows 3.1 BMP format (Logo.bmp)
+
+These files exist in the correct location in the StarLabsLtd/blobs repo on
+GitHub which is used in place of the standard 3rdparty/blobs repo.
+
+### Build
+
+The following commands will build a working image:
+
+
+```bash
+make distclean
+make defconfig KBUILD_DEFCONFIG=configs/config.starlabs_starfighter_mtl
+make
+```
+
+## Flashing coreboot
+
+```{eval-rst}
++---------------------+------------+
+| Type                | Value      |
++=====================+============+
+| Socketed flash      | no         |
++---------------------+------------+
+| Vendor              | Winbond    |
++---------------------+------------+
+| Model               | W25Q256.V  |
++---------------------+------------+
+| Size                | 32 MiB     |
++---------------------+------------+
+| Package             | SOIC-8     |
++---------------------+------------+
+| Internal flashing   | yes        |
++---------------------+------------+
+| External flashing   | yes        |
++---------------------+------------+
+```
+
+Please see [here](common/flashing.md) for instructions on how to flash with fwupd.

From 4427a34b6bcfc7f812edf19b9cdba566e98bc691 Mon Sep 17 00:00:00 2001
From: Pranava Y N <pranavayn@google.com>
Date: Sun, 18 Jan 2026 21:35:57 +0530
Subject: [PATCH 3077/3886] drivers/intel/fsp2_0: Fix string length handling in
 timestamp printing
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

The current implementation uses '%*s' which treats the calculated
str_len as a minimum field width. If the underlying string buffer is not
null-terminated, printk will continue reading past the buffer until it
encounters a null byte.

Switch to '%.*s' to correctly use the precision field, which specifies
the maximum number of characters to be printed from the string.

BUG=None
TEST=Able to dump FSP performance data with `DISPLAY_FSP_TIMESTAMPS`
Kconfig selected and meeting the FSP prerequisites. Verify that the
performance data table is printed correctly.

```
[INFO ]  +---------------------------------------------------+
[INFO ]  |------ FSP Performance Timestamp Table Dump -------|
[INFO ]  +---------------------------------------------------+
[INFO ]  | Perf-ID	Timestamp(us)		String/GUID |
[INFO ]  +---------------------------------------------------+
[INFO ]      0	         1242275		SEC/52c05b14-0b98-496c-bc3b04b50211d680
[INFO ]     50	         1242282		PEI/52c05b14-0b98-496c-bc3b04b50211d680
[INFO ]     40	         1242284		PreMem/52c05b14-0b98-496c-bc3b04b50211d680
```

Change-Id: Id95bd34b9c7d45d2c363339eb18adc5ac731c72b
Signed-off-by: Pranava Y N <pranavayn@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90788
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
---
 src/drivers/intel/fsp2_0/fsp_timestamp.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/drivers/intel/fsp2_0/fsp_timestamp.c b/src/drivers/intel/fsp2_0/fsp_timestamp.c
index 872cf9149e..65a6060f57 100644
--- a/src/drivers/intel/fsp2_0/fsp_timestamp.c
+++ b/src/drivers/intel/fsp2_0/fsp_timestamp.c
@@ -51,7 +51,7 @@ static void print_guid_record(const struct generic_event_record *rec)
 static void print_string_record(const struct generic_event_record *rec)
 {
 	size_t str_len = rec->header.length - offsetof(struct generic_event_record, string);
-	printk(BIOS_INFO, "%5x\t%16llu\t\t%*s/",
+	printk(BIOS_INFO, "%5x\t%16llu\t\t%.*s/",
 	       rec->progress_id, TIMESTAMP_TO_MICRO(rec->timestamp), (int)str_len, rec->string);
 	fsp_print_guid(BIOS_INFO, rec->guid);
 	printk(BIOS_INFO, "\n");

From e64507638e5cb88132bfc9beed269095f4feff62 Mon Sep 17 00:00:00 2001
From: Yu-Ping Wu <yupingso@chromium.org>
Date: Mon, 19 Jan 2026 23:26:53 +0800
Subject: [PATCH 3078/3886] tests/lib/ux_locales-test: Avoid double quotes in
 CMUnitTest.name

From the Jenkins result of CB:90798, it appears that the generated
junit-tests_lib_ux_locales-test(tests).xml is not a valid XML file
possibly due to incorrect quotes handling by cmocka.

Therefore, in the UX_LOCALES_GET_TEXT_TEST macro definition, replace
`#_expect` with `_expect`, so that the `name` field of the CMUnitTest
struct won't contain double quotes.

Change-Id: Idfec437ae627208031854694e66ca79e22132385
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90801
Reviewed-by: Jakub "Kuba" Czapiga <czapiga@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 tests/lib/ux_locales-test.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/tests/lib/ux_locales-test.c b/tests/lib/ux_locales-test.c
index 4edac5c9d2..8d643e6e11 100644
--- a/tests/lib/ux_locales-test.c
+++ b/tests/lib/ux_locales-test.c
@@ -191,7 +191,7 @@ static void test_ux_locales_null_terminated(void **state)
 #define UX_LOCALES_GET_TEXT_TEST(_msg_id, _lang_id, _expect)                               \
 	((struct CMUnitTest) {                                                                 \
 		.name = "test_ux_locales_get_text(msg_id=" #_msg_id ", lang_id=" #_lang_id          \
-			", expect=" #_expect ")",                                              \
+			", expect=" _expect ")",                                              \
 		.test_func = test_ux_locales_get_text,                                         \
 		.setup_func = setup_default,                                                   \
 		.teardown_func = teardown_unmap,                                               \

From d246e2ca7e7ae4bb04bfec204f20b785dcb3da0a Mon Sep 17 00:00:00 2001
From: Yu-Ping Wu <yupingso@chromium.org>
Date: Fri, 9 Jan 2026 17:31:59 +0800
Subject: [PATCH 3079/3886] tests/Makefile.common: Fix inverted
 USE_SYSTEM_CMOCKA condition

"-I$(cmockasrc)/include" should be added to TEST_CFLAGS if we are
building cmocka from source (i.e., USE_SYSTEM_CMOCKA is NOT 1). Fix the
condition in Makefile.common.

Change-Id: I957066fb24f03712a5b4b396aa9e04f3861940ee
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90798
Reviewed-by: Hsuan-ting Chen <roccochen@google.com>
Reviewed-by: Jakub "Kuba" Czapiga <czapiga@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 tests/Makefile.common | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/tests/Makefile.common b/tests/Makefile.common
index a8bb19c4f1..cfb6fe945e 100644
--- a/tests/Makefile.common
+++ b/tests/Makefile.common
@@ -157,7 +157,7 @@ $($(1)-sysobjs): $(testobj)/$(1)/%.o: $$$$*.c $$($(1)-config-file)
 
 # Link against Cmocka if not disabled
 ifeq ($(strip $(filter-out 0 n no,$($(1)-no_test_framework))),)
-ifneq ($(USE_SYSTEM_CMOCKA),)
+ifneq ($(USE_SYSTEM_CMOCKA),1)
 $($(1)-objs): TEST_CFLAGS += -I$(cmockasrc)/include
 $($(1)-bin): TEST_LDFLAGS += -L$(cmockaobj)/src -Wl,-rpath=$(cmockaobj)/src
 $($(1)-bin): TEST_CFLAGS += -I$(cmockasrc)/include

From fcd716d9a272461da1fdbaf1c048eb5a52c7896b Mon Sep 17 00:00:00 2001
From: Sowmya Aralguppe <sowmya.aralguppe@intel.com>
Date: Wed, 14 Jan 2026 13:58:56 +0530
Subject: [PATCH 3080/3886] mb/google/ocelot: Limit Power Limit when battery is
 missing

Ensure the board can boot by limiting the power limits if the battery
is missing. This addresses the factory use case for Wildcat Lake
processors.

BUG=b:None
TEST= Use cutoff at-shutdown and reboot
The device should boot with reduced power limits value and the log
is as shown below
[INFO ]  Battery not connected, booting with reduced PL values
[INFO ]  Overriding power limits PL1 (mW) (10000, 15000) PL2 (mW) (35000, 35000) PL4 (W) (45)

Change-Id: Iadb9c4c8450e6a55dd9fc644785742cc7aafd671
Signed-off-by: Sowmya Aralguppe <sowmya.aralguppe@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90755
Reviewed-by: Pranava Y N <pranavayn@google.com>
Reviewed-by: Avi Uday <aviuday@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 .../variants/baseboard/ocelot/ramstage.c      | 53 +++++++++++++++++--
 1 file changed, 50 insertions(+), 3 deletions(-)

diff --git a/src/mainboard/google/ocelot/variants/baseboard/ocelot/ramstage.c b/src/mainboard/google/ocelot/variants/baseboard/ocelot/ramstage.c
index 43a82d12c3..e68010d3b7 100644
--- a/src/mainboard/google/ocelot/variants/baseboard/ocelot/ramstage.c
+++ b/src/mainboard/google/ocelot/variants/baseboard/ocelot/ramstage.c
@@ -3,6 +3,51 @@
 #include <baseboard/variants.h>
 #include <ec/google/chromeec/ec.h>
 
+/*
+ * SKU_ID, TDP (Watts), pl1_min (milliWatts), pl1_max (milliWatts),
+ * pl2_min (milliWatts), pl2_max (milliWatts), pl4 (milliWatts)
+ */
+/* Define a macro for the common power limit values for WCL */
+#define COMMON_WCL_POWER_LIMITS	\
+	.pl1_min_power = 10000,		\
+	.pl1_max_power = 15000,		\
+	.pl2_min_power = 35000,		\
+	.pl2_max_power = 35000,		\
+	.pl4_power = 45000
+
+const struct cpu_tdp_power_limits power_optimized_limits[] = {
+	{
+		.mch_id = PCI_DID_INTEL_WCL_ID_1,
+		.cpu_tdp = TDP_15W,
+		.power_limits_index = WCL_CORE,
+		COMMON_WCL_POWER_LIMITS
+	},
+	{
+		.mch_id = PCI_DID_INTEL_WCL_ID_2,
+		.cpu_tdp = TDP_15W,
+		.power_limits_index = WCL_CORE,
+		COMMON_WCL_POWER_LIMITS
+	},
+	{
+		.mch_id = PCI_DID_INTEL_WCL_ID_3,
+		.cpu_tdp = TDP_15W,
+		.power_limits_index = WCL_CORE,
+		COMMON_WCL_POWER_LIMITS
+	},
+	{
+		.mch_id = PCI_DID_INTEL_WCL_ID_4,
+		.cpu_tdp = TDP_15W,
+		.power_limits_index = WCL_CORE,
+		COMMON_WCL_POWER_LIMITS
+	},
+	{
+		.mch_id = PCI_DID_INTEL_WCL_ID_5,
+		.cpu_tdp = TDP_15W,
+		.power_limits_index = WCL_CORE,
+		COMMON_WCL_POWER_LIMITS
+	},
+};
+
 /*
  * Placeholder to check if variant has support for barrel jack for powering
  * on the device.
@@ -21,7 +66,9 @@ void baseboard_devtree_update(void)
 	if (variant_is_barrel_charger_present())
 		return;
 
-	/* TODO: Add power limit override code for Wildcat Lake */
-	if (!google_chromeec_is_battery_present())
-		printk(BIOS_DEBUG, "TODO: Add support for power optimized boot configuration limits\n");
+	if (!google_chromeec_is_battery_present()) {
+		printk(BIOS_INFO, "Battery not connected, booting with reduced PL values\n");
+		variant_update_cpu_power_limits(power_optimized_limits,
+						ARRAY_SIZE(power_optimized_limits));
+	}
 }

From 9f8094575e1ed24e9003a03202006a83f511b688 Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Tue, 20 Jan 2026 11:44:22 +0000
Subject: [PATCH 3081/3886] soc/intel/meteorlake: Include Arrow Lake microcode
 binaries

Include the ARL-U A1 and ARL-S/HX B0 microode binaries.

Change-Id: I6ba458892f89b956cd8a1f1b8600c1ce1bc72a65
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90809
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
---
 src/soc/intel/meteorlake/Makefile.mk | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/src/soc/intel/meteorlake/Makefile.mk b/src/soc/intel/meteorlake/Makefile.mk
index ab4e8a7f56..2ef53f5395 100644
--- a/src/soc/intel/meteorlake/Makefile.mk
+++ b/src/soc/intel/meteorlake/Makefile.mk
@@ -62,7 +62,10 @@ CPPFLAGS_common += -I$(src)/soc/intel/meteorlake
 CPPFLAGS_common += -I$(src)/soc/intel/meteorlake/include
 
 ifeq ($(CONFIG_SOC_INTEL_METEORLAKE_U_H),y)
-cpu_microcode_bins += 3rdparty/intel-microcode/intel-ucode/06-aa-04
+cpu_microcode_bins += \
+	3rdparty/intel-microcode/intel-ucode/06-aa-04 \
+	3rdparty/intel-microcode/intel-ucode/06-b5-00 \
+	3rdparty/intel-microcode/intel-ucode/06-c6-02
 endif
 
 endif

From a198e7b8d63fbd3735cdb7093dee6473d3821db6 Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Tue, 20 Jan 2026 13:21:13 +0000
Subject: [PATCH 3082/3886] mb/starlabs/*: Use inline DEV_PTR calls

Remove the intermediate struct device's, and replace with the DEV_PTR
macro. This isn't a functional change, just cleaner.

Change-Id: I1a6a596a4d4215f6b670a8a7f7749a4f9bd391b0
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90820
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
---
 .../starlabs/byte_adl/variants/mk_ii/devtree.c      |  7 ++-----
 .../starlabs/starbook/variants/adl/devtree.c        |  4 +---
 .../starlabs/starbook/variants/adl_n/devtree.c      |  4 +---
 .../starlabs/starbook/variants/cml/devtree.c        |  4 +---
 .../starlabs/starbook/variants/kbl/devtree.c        |  4 +---
 .../starlabs/starbook/variants/mtl/devtree.c        |  7 ++-----
 .../starlabs/starbook/variants/rpl/devtree.c        | 10 +++-------
 .../starlabs/starbook/variants/tgl/devtree.c        | 13 ++++---------
 .../starlabs/starfighter/variants/rpl/devtree.c     | 13 ++++---------
 .../starlabs/starlite_adl/variants/mk_v/devtree.c   | 13 ++++---------
 10 files changed, 23 insertions(+), 56 deletions(-)

diff --git a/src/mainboard/starlabs/byte_adl/variants/mk_ii/devtree.c b/src/mainboard/starlabs/byte_adl/variants/mk_ii/devtree.c
index b9746623fe..0e8d04df79 100644
--- a/src/mainboard/starlabs/byte_adl/variants/mk_ii/devtree.c
+++ b/src/mainboard/starlabs/byte_adl/variants/mk_ii/devtree.c
@@ -22,9 +22,6 @@ void devtree_update(void)
 	struct soc_power_limits_config *soc_conf_8core =
 		&cfg->power_limits_config[ADL_N_041_15W_CORE];
 
-	struct device *wifi_dev = pcidev_on_root(0x14, 3);
-	struct device *gna_dev = pcidev_on_root(0x08, 0);
-
 	uint8_t performance_scale = 100;
 
 	/* Set PL4 to 1.0C */
@@ -59,7 +56,7 @@ void devtree_update(void)
 
 	/* Enable/Disable WiFi based on CMOS settings */
 	if (get_uint_option("wifi", 1) == 0)
-		wifi_dev->enabled = 0;
+		DEV_PTR(cnvi_wifi)->enabled = 0;
 
 	/* Enable/Disable Bluetooth based on CMOS settings */
 	if (get_uint_option("bluetooth", 1) == 0)
@@ -67,5 +64,5 @@ void devtree_update(void)
 
 	/* Enable/Disable GNA based on CMOS settings */
 	if (get_uint_option("gna", 0) == 0)
-		gna_dev->enabled = 0;
+		DEV_PTR(gna)->enabled = 0;
 }
diff --git a/src/mainboard/starlabs/starbook/variants/adl/devtree.c b/src/mainboard/starlabs/starbook/variants/adl/devtree.c
index 22b66d0d9f..2deb69f8e6 100644
--- a/src/mainboard/starlabs/starbook/variants/adl/devtree.c
+++ b/src/mainboard/starlabs/starbook/variants/adl/devtree.c
@@ -23,8 +23,6 @@ void devtree_update(void)
 	struct soc_power_limits_config *soc_conf_12core =
 		&cfg->power_limits_config[ADL_P_682_28W_CORE];
 
-	struct device *gna_dev = pcidev_on_root(0x08, 0);
-
 	uint8_t performance_scale = 100;
 
 	/* Set PL4 to 1.0C */
@@ -75,5 +73,5 @@ void devtree_update(void)
 
 	/* Enable/Disable GNA based on CMOS settings */
 	if (get_uint_option("gna", 0) == 0)
-		gna_dev->enabled = 0;
+		DEV_PTR(gna)->enabled = 0;
 }
diff --git a/src/mainboard/starlabs/starbook/variants/adl_n/devtree.c b/src/mainboard/starlabs/starbook/variants/adl_n/devtree.c
index 437a73c1bb..bd90e07c07 100644
--- a/src/mainboard/starlabs/starbook/variants/adl_n/devtree.c
+++ b/src/mainboard/starlabs/starbook/variants/adl_n/devtree.c
@@ -20,8 +20,6 @@ void devtree_update(void)
 	struct soc_power_limits_config *soc_conf_4core =
 		&cfg->power_limits_config[ADL_N_041_6W_CORE];
 
-	struct device *gna_dev = pcidev_on_root(0x08, 0);
-
 	uint8_t performance_scale = 100;
 
 	/* Set PL4 to 1.0C */
@@ -63,5 +61,5 @@ void devtree_update(void)
 
 	/* Enable/Disable GNA based on CMOS settings */
 	if (get_uint_option("gna", 0) == 0)
-		gna_dev->enabled = 0;
+		DEV_PTR(gna)->enabled = 0;
 }
diff --git a/src/mainboard/starlabs/starbook/variants/cml/devtree.c b/src/mainboard/starlabs/starbook/variants/cml/devtree.c
index d9bafcabd5..990b3c6143 100644
--- a/src/mainboard/starlabs/starbook/variants/cml/devtree.c
+++ b/src/mainboard/starlabs/starbook/variants/cml/devtree.c
@@ -19,8 +19,6 @@ void devtree_update(void)
 
 	struct soc_power_limits_config *soc_conf = &cfg->power_limits_config;
 
-	struct device *wifi_dev = pcidev_on_root(0x14, 3);
-
 	uint8_t performance_scale = 100;
 
 	/* Set PL4 to 1.0C */
@@ -50,7 +48,7 @@ void devtree_update(void)
 
 	/* Enable/Disable WiFi based on CMOS settings */
 	if (get_uint_option("wifi", 1) == 0)
-		wifi_dev->enabled = 0;
+		DEV_PTR(cnvi_wifi)->enabled = 0;
 
 	/* Enable/Disable Bluetooth based on CMOS settings */
 	if (get_uint_option("bluetooth", 1) == 0)
diff --git a/src/mainboard/starlabs/starbook/variants/kbl/devtree.c b/src/mainboard/starlabs/starbook/variants/kbl/devtree.c
index c648be9da7..56978fff11 100644
--- a/src/mainboard/starlabs/starbook/variants/kbl/devtree.c
+++ b/src/mainboard/starlabs/starbook/variants/kbl/devtree.c
@@ -19,8 +19,6 @@ void devtree_update(void)
 
 	struct soc_power_limits_config *soc_conf = &cfg->power_limits_config;
 
-	struct device *wifi_dev = pcidev_on_root(0x1c, 5);
-
 	uint8_t performance_scale = 100;
 
 	/* Set PL4 to 1.0C */
@@ -50,7 +48,7 @@ void devtree_update(void)
 
 	/* Enable/Disable WiFi based on CMOS settings */
 	if (get_uint_option("wifi", 1) == 0)
-		wifi_dev->enabled = 0;
+		DEV_PTR(pcie_rp5)->enabled = 0;
 
 	/* Enable/Disable Bluetooth based on CMOS settings */
 	if (get_uint_option("bluetooth", 1) == 0)
diff --git a/src/mainboard/starlabs/starbook/variants/mtl/devtree.c b/src/mainboard/starlabs/starbook/variants/mtl/devtree.c
index 296027e9e8..66c8179810 100644
--- a/src/mainboard/starlabs/starbook/variants/mtl/devtree.c
+++ b/src/mainboard/starlabs/starbook/variants/mtl/devtree.c
@@ -20,9 +20,6 @@ void devtree_update(void)
 	struct soc_power_limits_config *soc_conf_20core =
 		&cfg->power_limits_config[MTL_P_682_482_CORE];
 
-	struct device *gna_dev = pcidev_on_root(0x08, 0);
-	struct device *vpu_dev = pcidev_on_root(0x0b, 0);
-
 	uint8_t performance_scale = 100;
 
 	/* Set PL4 to 1.0C */
@@ -64,9 +61,9 @@ void devtree_update(void)
 
 	/* Enable/Disable GNA based on CMOS settings */
 	if (get_uint_option("gna", 0) == 0)
-		gna_dev->enabled = 0;
+		DEV_PTR(gna)->enabled = 0;
 
 	/* Enable/Disable VPU based on CMOS settings */
 	if (get_uint_option("vpu", 0) == 0)
-		vpu_dev->enabled = 0;
+		DEV_PTR(vpu)->enabled = 0;
 }
diff --git a/src/mainboard/starlabs/starbook/variants/rpl/devtree.c b/src/mainboard/starlabs/starbook/variants/rpl/devtree.c
index 32ba845ba8..3485fdbb31 100644
--- a/src/mainboard/starlabs/starbook/variants/rpl/devtree.c
+++ b/src/mainboard/starlabs/starbook/variants/rpl/devtree.c
@@ -23,10 +23,6 @@ void devtree_update(void)
 	struct soc_power_limits_config *soc_conf_12core =
 		&cfg->power_limits_config[RPL_P_682_482_282_28W_CORE];
 
-	struct device *tbt_pci_dev = pcidev_on_root(0x07, 0);
-	struct device *tbt_dma_dev = pcidev_on_root(0x0d, 2);
-	struct device *gna_dev = pcidev_on_root(0x08, 0);
-
 	uint8_t performance_scale = 100;
 
 	/* Set PL4 to 1.0C */
@@ -77,11 +73,11 @@ void devtree_update(void)
 
 	/* Enable/Disable Thunderbolt based on CMOS settings */
 	if (get_uint_option("thunderbolt", 1) == 0) {
-		tbt_pci_dev->enabled = 0;
-		tbt_dma_dev->enabled = 0;
+		DEV_PTR(tbt_pcie_rp0)->enabled = 0;
+		DEV_PTR(tcss_dma0)->enabled = 0;
 	}
 
 	/* Enable/Disable GNA based on CMOS settings */
 	if (get_uint_option("gna", 0) == 0)
-		gna_dev->enabled = 0;
+		DEV_PTR(gna)->enabled = 0;
 }
diff --git a/src/mainboard/starlabs/starbook/variants/tgl/devtree.c b/src/mainboard/starlabs/starbook/variants/tgl/devtree.c
index d83c2b55a7..7bfd6a560b 100644
--- a/src/mainboard/starlabs/starbook/variants/tgl/devtree.c
+++ b/src/mainboard/starlabs/starbook/variants/tgl/devtree.c
@@ -23,11 +23,6 @@ void devtree_update(void)
 	struct soc_power_limits_config *soc_conf_4core =
 		&cfg->power_limits_config[POWER_LIMITS_U_4_CORE];
 
-	struct device *wifi_dev = pcidev_on_root(0x14, 3);
-	struct device *tbt_pci_dev = pcidev_on_root(0x07, 0);
-	struct device *tbt_dma_dev = pcidev_on_root(0x0d, 2);
-	struct device *gna_dev = pcidev_on_root(0x08, 0);
-
 	uint8_t performance_scale = 100;
 
 	/* Set PL4 to 1.0C */
@@ -62,7 +57,7 @@ void devtree_update(void)
 
 	/* Enable/Disable WiFi based on CMOS settings */
 	if (get_uint_option("wifi", 1) == 0)
-		wifi_dev->enabled = 0;
+		DEV_PTR(cnvi_wifi)->enabled = 0;
 
 	/* Enable/Disable Bluetooth based on CMOS settings */
 	if (get_uint_option("bluetooth", 1) == 0)
@@ -79,11 +74,11 @@ void devtree_update(void)
 	if (get_uint_option("thunderbolt", 1) == 0) {
 		cfg->UsbTcPortEn = 0;
 		cfg->TcssXhciEn = 0;
-		tbt_pci_dev->enabled = 0;
-		tbt_dma_dev->enabled = 0;
+		DEV_PTR(tbt_pcie_rp0)->enabled = 0;
+		DEV_PTR(tbt_dma0)->enabled = 0;
 	}
 
 	/* Enable/Disable GNA based on CMOS settings */
 	if (get_uint_option("gna", 0) == 0)
-		gna_dev->enabled = 0;
+		DEV_PTR(gna)->enabled = 0;
 }
diff --git a/src/mainboard/starlabs/starfighter/variants/rpl/devtree.c b/src/mainboard/starlabs/starfighter/variants/rpl/devtree.c
index fe9d9117dc..b094c7c2fb 100644
--- a/src/mainboard/starlabs/starfighter/variants/rpl/devtree.c
+++ b/src/mainboard/starlabs/starfighter/variants/rpl/devtree.c
@@ -23,11 +23,6 @@ void devtree_update(void)
 	struct soc_power_limits_config *soc_conf_14core =
 		&cfg->power_limits_config[RPL_P_682_642_482_45W_CORE];
 
-	struct device *tbt_pci_dev_0 = pcidev_on_root(0x07, 0);
-	struct device *tbt_pci_dev_1 = pcidev_on_root(0x07, 1);
-	struct device *tbt_dma_dev = pcidev_on_root(0x0d, 2);
-	struct device *gna_dev = pcidev_on_root(0x08, 0);
-
 	uint8_t performance_scale = 100;
 
 	/* Set PL4 to 1.0C */
@@ -70,12 +65,12 @@ void devtree_update(void)
 
 	/* Enable/Disable Thunderbolt based on CMOS settings */
 	if (get_uint_option("thunderbolt", 1) == 0) {
-		tbt_pci_dev_0->enabled = 0;
-		tbt_pci_dev_1->enabled = 0;
-		tbt_dma_dev->enabled = 0;
+		DEV_PTR(tbt_pcie_rp0)->enabled = 0;
+		DEV_PTR(tbt_pcie_rp1)->enabled = 0;
+		DEV_PTR(tcss_dma0)->enabled = 0;
 	}
 
 	/* Enable/Disable GNA based on CMOS settings */
 	if (get_uint_option("gna", 0) == 0)
-		gna_dev->enabled = 0;
+		DEV_PTR(gna)->enabled = 0;
 }
diff --git a/src/mainboard/starlabs/starlite_adl/variants/mk_v/devtree.c b/src/mainboard/starlabs/starlite_adl/variants/mk_v/devtree.c
index cc8dd4a7b9..1f1dd8fd28 100644
--- a/src/mainboard/starlabs/starlite_adl/variants/mk_v/devtree.c
+++ b/src/mainboard/starlabs/starlite_adl/variants/mk_v/devtree.c
@@ -20,11 +20,6 @@ void devtree_update(void)
 	struct soc_power_limits_config *soc_conf_4core =
 		&cfg->power_limits_config[ADL_N_041_6W_CORE];
 
-	struct device *wifi_dev = pcidev_on_root(0x14, 3);
-	struct device *touchscreen_dev = pcidev_on_root(0x15, 2);
-	struct device *accelerometer_dev = pcidev_on_root(0x15, 0);
-	struct device *gna_dev = pcidev_on_root(0x08, 0);
-
 	uint8_t performance_scale = 100;
 
 	/* Set PL4 to 1.0C */
@@ -55,7 +50,7 @@ void devtree_update(void)
 
 	/* Enable/Disable WiFi based on CMOS settings */
 	if (get_uint_option("wifi", 1) == 0)
-		wifi_dev->enabled = 0;
+		DEV_PTR(cnvi_wifi)->enabled = 0;
 
 	/* Enable/Disable Bluetooth based on CMOS settings */
 	if (get_uint_option("bluetooth", 1) == 0)
@@ -67,15 +62,15 @@ void devtree_update(void)
 
 	/* Enable/Disable Touchscreen based on CMOS settings */
 	if (get_uint_option("touchscreen", 1) == 0)
-		touchscreen_dev->enabled = 0;
+		DEV_PTR(i2c2)->enabled = 0;
 
 	/* Enable/Disable Accelerometer based on CMOS settings */
 	if (get_uint_option("accelerometer", 1) == 0)
-		accelerometer_dev->enabled = 0;
+		DEV_PTR(i2c0)->enabled = 0;
 
 	/* Enable/Disable GNA based on CMOS settings */
 	if (get_uint_option("gna", 0) == 0)
-		gna_dev->enabled = 0;
+		DEV_PTR(gna)->enabled = 0;
 
 	/* Enable/Disable Card Reader based on CMOS Settings */
 	if (get_uint_option("card_reader", 0) == 0)

From cb08e29ba79b1f935f43375d13d6983327de1b79 Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Mon, 27 Oct 2025 19:45:07 +0000
Subject: [PATCH 3083/3886] mb/starlabs/*: Move powercap configuration to
 common dir

Move the code that configures power limits, tcc and other power related
settings into common code. The end result is the same, but the PL4 is
set by reading the battery capacity, rather than being hardcoded.

This patch also appends `_group` to each form group, to avoid conflicts
with objects now visible with the extra headers.

Change-Id: I41235039bc984686fa43f5c712e836d0b8d5d24a
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89775
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/starlabs/byte_adl/Kconfig       |  7 ++-
 src/mainboard/starlabs/byte_adl/cfr.c         | 24 +++++-----
 .../byte_adl/variants/mk_ii/devtree.c         | 41 +---------------
 .../starlabs/common/include/common/cfr.h      |  1 +
 .../starlabs/common/include/common/powercap.h |  6 ++-
 .../starlabs/common/powercap/powercap.c       | 48 ++++++++++++++++++-
 src/mainboard/starlabs/lite/Kconfig           |  8 ++++
 src/mainboard/starlabs/lite/cfr.c             | 28 +++++------
 src/mainboard/starlabs/lite/devtree.c         | 31 +-----------
 src/mainboard/starlabs/starbook/Kconfig       | 11 +++++
 src/mainboard/starlabs/starbook/cfr.c         | 28 +++++------
 .../starlabs/starbook/variants/adl/devtree.c  | 42 +---------------
 .../starbook/variants/adl_n/devtree.c         | 34 +------------
 .../starlabs/starbook/variants/cml/devtree.c  | 33 +------------
 .../starlabs/starbook/variants/kbl/devtree.c  | 33 +------------
 .../starlabs/starbook/variants/mtl/devtree.c  | 34 +------------
 .../starlabs/starbook/variants/rpl/devtree.c  | 42 +---------------
 .../starlabs/starbook/variants/tgl/devtree.c  | 42 +---------------
 src/mainboard/starlabs/starfighter/Kconfig    |  8 ++++
 src/mainboard/starlabs/starfighter/cfr.c      | 28 +++++------
 .../starfighter/variants/mtl/devtree.c        | 34 +------------
 .../starfighter/variants/rpl/devtree.c        | 42 +---------------
 src/mainboard/starlabs/starlite_adl/Kconfig   |  8 ++++
 src/mainboard/starlabs/starlite_adl/cfr.c     | 24 +++++-----
 .../starlite_adl/variants/mk_v/devtree.c      | 35 +-------------
 25 files changed, 171 insertions(+), 501 deletions(-)

diff --git a/src/mainboard/starlabs/byte_adl/Kconfig b/src/mainboard/starlabs/byte_adl/Kconfig
index 04bdcc8ee2..d8524a9ceb 100644
--- a/src/mainboard/starlabs/byte_adl/Kconfig
+++ b/src/mainboard/starlabs/byte_adl/Kconfig
@@ -85,8 +85,7 @@ config ME_BIN_PATH
 
 config PL4_WATTS
 	int
-	default 65 if BOARD_STARLABS_BYTE_TWL
-	default 36
+	default 65
 
 config POWER_STATE_DEFAULT_ON_AFTER_FAILURE
 	default n
@@ -98,6 +97,10 @@ config EDK2_BOOTSPLASH_FILE
 config SOC_INTEL_CSE_SEND_EOP_EARLY
 	default n
 
+config TJ_MAX
+	int
+	default 105
+
 config UART_FOR_CONSOLE
 	default 0
 
diff --git a/src/mainboard/starlabs/byte_adl/cfr.c b/src/mainboard/starlabs/byte_adl/cfr.c
index 5a29170778..3a9162d1cb 100644
--- a/src/mainboard/starlabs/byte_adl/cfr.c
+++ b/src/mainboard/starlabs/byte_adl/cfr.c
@@ -8,7 +8,7 @@
 #include <variants.h>
 #include <common/cfr.h>
 
-static struct sm_obj_form performance = {
+static struct sm_obj_form performance_group = {
 	.ui_name = "Performance",
 	.obj_list = (const struct sm_object *[]) {
 		&bluetooth_rtd3,
@@ -18,7 +18,7 @@ static struct sm_obj_form performance = {
 	},
 };
 
-static struct sm_obj_form processor = {
+static struct sm_obj_form processor_group = {
 	.ui_name = "Processor",
 	.obj_list = (const struct sm_object *[]) {
 		&me_state,
@@ -29,7 +29,7 @@ static struct sm_obj_form processor = {
 	},
 };
 
-static struct sm_obj_form power = {
+static struct sm_obj_form power_group = {
 	.ui_name = "Power",
 	.obj_list = (const struct sm_object *[]) {
 		&power_on_after_fail_bool,
@@ -37,7 +37,7 @@ static struct sm_obj_form power = {
 	},
 };
 
-static struct sm_obj_form devices = {
+static struct sm_obj_form devices_group = {
 	.ui_name = "Devices",
 	.obj_list = (const struct sm_object *[]) {
 		&bluetooth,
@@ -47,7 +47,7 @@ static struct sm_obj_form devices = {
 	},
 };
 
-static struct sm_obj_form pci = {
+static struct sm_obj_form pci_group = {
 	.ui_name = "PCI",
 	.obj_list = (const struct sm_object *[]) {
 		&pciexp_clk_pm,
@@ -57,7 +57,7 @@ static struct sm_obj_form pci = {
 	},
 };
 
-static struct sm_obj_form coreboot = {
+static struct sm_obj_form coreboot_group = {
 	.ui_name = "coreboot",
 	.obj_list = (const struct sm_object *[]) {
 		&debug_level,
@@ -66,12 +66,12 @@ static struct sm_obj_form coreboot = {
 };
 
 static struct sm_obj_form *sm_root[] = {
-	&performance,
-	&processor,
-	&power,
-	&devices,
-	&pci,
-	&coreboot,
+	&performance_group,
+	&processor_group,
+	&power_group,
+	&devices_group,
+	&pci_group,
+	&coreboot_group,
 	NULL
 };
 
diff --git a/src/mainboard/starlabs/byte_adl/variants/mk_ii/devtree.c b/src/mainboard/starlabs/byte_adl/variants/mk_ii/devtree.c
index 0e8d04df79..aaa5fdafae 100644
--- a/src/mainboard/starlabs/byte_adl/variants/mk_ii/devtree.c
+++ b/src/mainboard/starlabs/byte_adl/variants/mk_ii/devtree.c
@@ -10,49 +10,10 @@
 #include <variants.h>
 #include <common/powercap.h>
 
-#define TJ_MAX		105
-#define TCC(temp)	(TJ_MAX - temp)
-
 void devtree_update(void)
 {
 	config_t *cfg = config_of_soc();
-
-	struct soc_power_limits_config *soc_conf_4core =
-		&cfg->power_limits_config[ADL_N_041_6W_CORE];
-	struct soc_power_limits_config *soc_conf_8core =
-		&cfg->power_limits_config[ADL_N_041_15W_CORE];
-
-	uint8_t performance_scale = 100;
-
-	/* Set PL4 to 1.0C */
-	soc_conf_4core->tdp_pl4				= CONFIG_PL4_WATTS;
-
-	/* Set PL1 to 50% of PL2 */
-	soc_conf_4core->tdp_pl1_override = (soc_conf_4core->tdp_pl2_override / 2) & ~1;
-	soc_conf_8core->tdp_pl1_override = (soc_conf_8core->tdp_pl2_override / 2) & ~1;
-
-	/* Scale PL1 & PL2 based on CMOS settings */
-	switch (get_power_profile(PP_POWER_SAVER)) {
-	case PP_POWER_SAVER:
-		performance_scale			-= 50;
-		cfg->tcc_offset				= TCC(70);
-		break;
-	case PP_BALANCED:
-		performance_scale			-= 25;
-		cfg->tcc_offset				= TCC(80);
-		break;
-	case PP_PERFORMANCE:
-		/* Use the Intel defaults */
-		cfg->tcc_offset				= TCC(90);
-		break;
-	}
-
-	soc_conf_4core->tdp_pl1_override = (soc_conf_4core->tdp_pl1_override * performance_scale) / 100;
-	soc_conf_4core->tdp_pl2_override = (soc_conf_4core->tdp_pl2_override * performance_scale) / 100;
-
-	soc_conf_8core->tdp_pl1_override = (soc_conf_8core->tdp_pl1_override * performance_scale) / 100;
-	soc_conf_8core->tdp_pl2_override = (soc_conf_8core->tdp_pl2_override * performance_scale) / 100;
-
+	update_power_limits(cfg);
 
 	/* Enable/Disable WiFi based on CMOS settings */
 	if (get_uint_option("wifi", 1) == 0)
diff --git a/src/mainboard/starlabs/common/include/common/cfr.h b/src/mainboard/starlabs/common/include/common/cfr.h
index 4a081c3c31..faf9887b1f 100644
--- a/src/mainboard/starlabs/common/include/common/cfr.h
+++ b/src/mainboard/starlabs/common/include/common/cfr.h
@@ -4,6 +4,7 @@
 #define _STARLABS_CMN_CFR_H_
 
 #include <drivers/option/cfr_frontend.h>
+#include <soc/soc_chip.h>
 #include <common/powercap.h>
 
 void cfr_card_reader_update(struct sm_object *new_obj);
diff --git a/src/mainboard/starlabs/common/include/common/powercap.h b/src/mainboard/starlabs/common/include/common/powercap.h
index aa1d68f418..a9ea99916c 100644
--- a/src/mainboard/starlabs/common/include/common/powercap.h
+++ b/src/mainboard/starlabs/common/include/common/powercap.h
@@ -3,6 +3,10 @@
 #ifndef _STARLABS_CMN_POWERCAP_H_
 #define _STARLABS_CMN_POWERCAP_H_
 
+#include <soc/soc_chip.h>
+
+#define TCC(temp)	(CONFIG_TJ_MAX - temp)
+
 enum cmos_power_profile {
 	PP_POWER_SAVER	= 0,
 	PP_BALANCED	= 1,
@@ -10,6 +14,6 @@ enum cmos_power_profile {
 };
 #define NUM_POWER_PROFILES 3
 
-enum cmos_power_profile get_power_profile(enum cmos_power_profile fallback);
+void update_power_limits(config_t *cfg);
 
 #endif
diff --git a/src/mainboard/starlabs/common/powercap/powercap.c b/src/mainboard/starlabs/common/powercap/powercap.c
index e19e6ec403..a1eeb019cf 100644
--- a/src/mainboard/starlabs/common/powercap/powercap.c
+++ b/src/mainboard/starlabs/common/powercap/powercap.c
@@ -1,10 +1,56 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
 #include <option.h>
+#include <types.h>
 #include <common/powercap.h>
 
-enum cmos_power_profile get_power_profile(enum cmos_power_profile fallback)
+static enum cmos_power_profile get_power_profile(enum cmos_power_profile fallback)
 {
 	const unsigned int power_profile = get_uint_option("power_profile", fallback);
 	return power_profile < NUM_POWER_PROFILES ? power_profile : fallback;
 }
+
+
+void update_power_limits(config_t *cfg)
+{
+	uint8_t performance_scale = 100;
+
+	/* Scale PL1 & PL2 based on CMOS settings */
+	switch (get_power_profile(PP_POWER_SAVER)) {
+	case PP_POWER_SAVER:
+		performance_scale -= 50;
+		cfg->tcc_offset = TCC(80);
+		break;
+	case PP_BALANCED:
+		performance_scale -= 25;
+		cfg->tcc_offset = TCC(90);
+		break;
+	case PP_PERFORMANCE:
+		/* Use the Intel defaults */
+		cfg->tcc_offset = TCC(100);
+		break;
+	}
+
+	struct soc_power_limits_config *limits =
+		(struct soc_power_limits_config *)&cfg->power_limits_config;
+	size_t limit_count = sizeof(cfg->power_limits_config) /
+			     sizeof(struct soc_power_limits_config);
+
+	for (size_t i = 0; i < limit_count; i++) {
+		struct soc_power_limits_config *entry = &limits[i];
+
+		entry->tdp_pl4 = (uint16_t)CONFIG_PL4_WATTS;
+
+		if (!entry->tdp_pl2_override)
+			continue;
+
+		/* Set PL1 to 50% of PL2 */
+		entry->tdp_pl1_override = (entry->tdp_pl2_override / 2) & ~1;
+
+		if (performance_scale == 100)
+			continue;
+
+		entry->tdp_pl1_override = ((entry->tdp_pl1_override * performance_scale) / 100);
+		entry->tdp_pl2_override = ((entry->tdp_pl2_override * performance_scale) / 100);
+	}
+}
diff --git a/src/mainboard/starlabs/lite/Kconfig b/src/mainboard/starlabs/lite/Kconfig
index 8ea2101f69..e68e84b397 100644
--- a/src/mainboard/starlabs/lite/Kconfig
+++ b/src/mainboard/starlabs/lite/Kconfig
@@ -83,6 +83,14 @@ config MAINBOARD_SMBIOS_PRODUCT_NAME
 config POWER_STATE_DEFAULT_ON_AFTER_FAILURE
 	default n
 
+config TJ_MAX
+	int
+	default 100
+
+config PL4_WATTS
+	int
+	default 45
+
 config TRACKPAD_INTERRUPT
 	hex
 	default 0x1 if BOARD_STARLABS_LITE_GLK
diff --git a/src/mainboard/starlabs/lite/cfr.c b/src/mainboard/starlabs/lite/cfr.c
index f9e42146cf..db3702fb79 100644
--- a/src/mainboard/starlabs/lite/cfr.c
+++ b/src/mainboard/starlabs/lite/cfr.c
@@ -8,7 +8,7 @@
 #include <variants.h>
 #include <common/cfr.h>
 
-static struct sm_obj_form performance = {
+static struct sm_obj_form performance_group = {
 	.ui_name = "Performance",
 	.obj_list = (const struct sm_object *[]) {
 		&power_profile,
@@ -16,7 +16,7 @@ static struct sm_obj_form performance = {
 	},
 };
 
-static struct sm_obj_form processor = {
+static struct sm_obj_form processor_group = {
 	.ui_name = "Processor",
 	.obj_list = (const struct sm_object *[]) {
 		&s0ix_enable,
@@ -25,7 +25,7 @@ static struct sm_obj_form processor = {
 	},
 };
 
-static struct sm_obj_form power = {
+static struct sm_obj_form power_group = {
 	.ui_name = "Power",
 	.obj_list = (const struct sm_object *[]) {
 		&power_on_after_fail_bool,
@@ -33,7 +33,7 @@ static struct sm_obj_form power = {
 	},
 };
 
-static struct sm_obj_form keyboard = {
+static struct sm_obj_form keyboard_group = {
 	.ui_name = "Keyboard",
 	.obj_list = (const struct sm_object *[]) {
 		&kbl_timeout,
@@ -42,7 +42,7 @@ static struct sm_obj_form keyboard = {
 	},
 };
 
-static struct sm_obj_form devices = {
+static struct sm_obj_form devices_group = {
 	.ui_name = "Devices",
 	.obj_list = (const struct sm_object *[]) {
 		&bluetooth,
@@ -54,7 +54,7 @@ static struct sm_obj_form devices = {
 	},
 };
 
-static struct sm_obj_form pci = {
+static struct sm_obj_form pci_group = {
 	.ui_name = "PCI",
 	.obj_list = (const struct sm_object *[]) {
 		#if CONFIG(SOC_INTEL_ALDERLAKE)
@@ -66,7 +66,7 @@ static struct sm_obj_form pci = {
 	},
 };
 
-static struct sm_obj_form coreboot = {
+static struct sm_obj_form coreboot_group = {
 	.ui_name = "coreboot",
 	.obj_list = (const struct sm_object *[]) {
 		&debug_level,
@@ -75,13 +75,13 @@ static struct sm_obj_form coreboot = {
 };
 
 static struct sm_obj_form *sm_root[] = {
-	&performance,
-	&processor,
-	&power,
-	&keyboard,
-	&devices,
-	&pci,
-	&coreboot,
+	&performance_group,
+	&processor_group,
+	&power_group,
+	&keyboard_group,
+	&devices_group,
+	&pci_group,
+	&coreboot_group,
 	NULL
 };
 
diff --git a/src/mainboard/starlabs/lite/devtree.c b/src/mainboard/starlabs/lite/devtree.c
index b86c38b208..afbd1bba11 100644
--- a/src/mainboard/starlabs/lite/devtree.c
+++ b/src/mainboard/starlabs/lite/devtree.c
@@ -15,38 +15,9 @@ void devtree_update(void)
 {
 	config_t *cfg = config_of_soc();
 
-	struct soc_power_limits_config *soc_conf =
-		&cfg->power_limits_config;
-
 	struct device *wifi_dev = pcidev_on_root(0x0c, 0);
 
-	uint8_t performance_scale = 100;
-
-	/* Set PL4 to 1.0C */
-	soc_conf->tdp_pl4			= 31;
-
-	/* Set PL1 to 50% of PL2 */
-	soc_conf->tdp_pl1_override = (soc_conf->tdp_pl2_override / 2) & ~1;
-
-	/* Scale PL1 & PL2 based on CMOS settings */
-	switch (get_power_profile(PP_POWER_SAVER)) {
-	case PP_POWER_SAVER:
-		performance_scale -= 25;
-		cfg->tcc_offset			= 15;
-		break;
-	case PP_BALANCED:
-		/* Use the Intel defaults */
-		cfg->tcc_offset			= 10;
-		break;
-	case PP_PERFORMANCE:
-		performance_scale += 25;
-		cfg->tcc_offset			= 5;
-		break;
-	}
-
-	soc_conf->tdp_pl1_override = (soc_conf->tdp_pl1_override * performance_scale) / 100;
-	soc_conf->tdp_pl2_override = (soc_conf->tdp_pl2_override * performance_scale) / 100;
-
+	update_power_limits(cfg);
 
 	/* Enable/Disable WiFi based on CMOS settings */
 	if (get_uint_option("wifi", 1) == 0)
diff --git a/src/mainboard/starlabs/starbook/Kconfig b/src/mainboard/starlabs/starbook/Kconfig
index 7a7ac3919e..063a7c6410 100644
--- a/src/mainboard/starlabs/starbook/Kconfig
+++ b/src/mainboard/starlabs/starbook/Kconfig
@@ -197,6 +197,17 @@ config POWER_STATE_DEFAULT_ON_AFTER_FAILURE
 config SOC_INTEL_CSE_SEND_EOP_EARLY
 	default n
 
+config TJ_MAX
+	int
+	default 100 if BOARD_STARLABS_LABTOP_KBL || BOARD_STARLABS_LABTOP_CML || BOARD_STARLABS_STARBOOK_TGL
+	default 105 if BOARD_STARLABS_STARBOOK_ADL_N
+	default 110
+
+config PL4_WATTS
+	int
+	default 45 if BOARD_STARLABS_LABTOP_KBL || BOARD_STARLABS_LABTOP_CML
+	default 65
+
 config TME_KEY_REGENERATION_ON_WARM_BOOT
 	default n
 
diff --git a/src/mainboard/starlabs/starbook/cfr.c b/src/mainboard/starlabs/starbook/cfr.c
index 69e48d1023..a499d3ed08 100644
--- a/src/mainboard/starlabs/starbook/cfr.c
+++ b/src/mainboard/starlabs/starbook/cfr.c
@@ -7,7 +7,7 @@
 #include <intelblocks/cfr.h>
 #include <common/cfr.h>
 
-static struct sm_obj_form performance = {
+static struct sm_obj_form performance_group = {
 	.ui_name = "Performance",
 	.obj_list = (const struct sm_object *[]) {
 		&bluetooth_rtd3,
@@ -17,7 +17,7 @@ static struct sm_obj_form performance = {
 	},
 };
 
-static struct sm_obj_form processor = {
+static struct sm_obj_form processor_group = {
 	.ui_name = "Processor",
 	.obj_list = (const struct sm_object *[]) {
 		&me_state,
@@ -31,7 +31,7 @@ static struct sm_obj_form processor = {
 	},
 };
 
-static struct sm_obj_form power = {
+static struct sm_obj_form power_group = {
 	.ui_name = "Power",
 	.obj_list = (const struct sm_object *[]) {
 		&max_charge,
@@ -45,7 +45,7 @@ static struct sm_obj_form power = {
 	},
 };
 
-static struct sm_obj_form keyboard = {
+static struct sm_obj_form keyboard_group = {
 	.ui_name = "Keyboard",
 	.obj_list = (const struct sm_object *[]) {
 		&kbl_timeout,
@@ -54,7 +54,7 @@ static struct sm_obj_form keyboard = {
 	},
 };
 
-static struct sm_obj_form devices = {
+static struct sm_obj_form devices_group = {
 	.ui_name = "Devices",
 	.obj_list = (const struct sm_object *[]) {
 		&bluetooth,
@@ -84,7 +84,7 @@ static struct sm_obj_form devices = {
 	},
 };
 
-static struct sm_obj_form pci = {
+static struct sm_obj_form pci_group = {
 	.ui_name = "PCI",
 	.obj_list = (const struct sm_object *[]) {
 		#if CONFIG(BOARD_STARLABS_STARBOOK_ADL)
@@ -103,7 +103,7 @@ static struct sm_obj_form pci = {
 	},
 };
 
-static struct sm_obj_form coreboot = {
+static struct sm_obj_form coreboot_group = {
 	.ui_name = "coreboot",
 	.obj_list = (const struct sm_object *[]) {
 		&debug_level,
@@ -112,13 +112,13 @@ static struct sm_obj_form coreboot = {
 };
 
 static struct sm_obj_form *sm_root[] = {
-	&performance,
-	&processor,
-	&power,
-	&keyboard,
-	&devices,
-	&pci,
-	&coreboot,
+	&performance_group,
+	&processor_group,
+	&power_group,
+	&keyboard_group,
+	&devices_group,
+	&pci_group,
+	&coreboot_group,
 	NULL
 };
 
diff --git a/src/mainboard/starlabs/starbook/variants/adl/devtree.c b/src/mainboard/starlabs/starbook/variants/adl/devtree.c
index 2deb69f8e6..3379e02dae 100644
--- a/src/mainboard/starlabs/starbook/variants/adl/devtree.c
+++ b/src/mainboard/starlabs/starbook/variants/adl/devtree.c
@@ -10,50 +10,10 @@
 #include <variants.h>
 #include <common/powercap.h>
 
-#define TJ_MAX		110
-#define TCC(temp)	(TJ_MAX - temp)
-
 void devtree_update(void)
 {
 	config_t *cfg = config_of_soc();
-
-	struct soc_power_limits_config *soc_conf_10core =
-		&cfg->power_limits_config[ADL_P_282_442_482_28W_CORE];
-
-	struct soc_power_limits_config *soc_conf_12core =
-		&cfg->power_limits_config[ADL_P_682_28W_CORE];
-
-	uint8_t performance_scale = 100;
-
-	/* Set PL4 to 1.0C */
-	soc_conf_10core->tdp_pl4			= 65;
-	soc_conf_12core->tdp_pl4			= 65;
-
-	/* Set PL1 to 50% of PL2 */
-	soc_conf_10core->tdp_pl1_override = (soc_conf_10core->tdp_pl2_override / 2) & ~1;
-	soc_conf_12core->tdp_pl1_override = (soc_conf_12core->tdp_pl2_override / 2) & ~1;
-
-	/* Scale PL1 & PL2 based on CMOS settings */
-	switch (get_power_profile(PP_POWER_SAVER)) {
-	case PP_POWER_SAVER:
-		performance_scale			-= 50;
-		cfg->tcc_offset				= TCC(80);
-		break;
-	case PP_BALANCED:
-		performance_scale			-= 25;
-		cfg->tcc_offset				= TCC(90);
-		break;
-	case PP_PERFORMANCE:
-		/* Use the Intel defaults */
-		cfg->tcc_offset				= TCC(100);
-		break;
-	}
-
-	soc_conf_10core->tdp_pl1_override = (soc_conf_10core->tdp_pl1_override * performance_scale) / 100;
-	soc_conf_10core->tdp_pl2_override = (soc_conf_10core->tdp_pl2_override * performance_scale) / 100;
-
-	soc_conf_12core->tdp_pl1_override = (soc_conf_12core->tdp_pl1_override * performance_scale) / 100;
-	soc_conf_12core->tdp_pl2_override = (soc_conf_12core->tdp_pl2_override * performance_scale) / 100;
+	update_power_limits(cfg);
 
 	/* Enable/Disable Bluetooth based on CMOS settings */
 	if (get_uint_option("bluetooth", 1) == 0)
diff --git a/src/mainboard/starlabs/starbook/variants/adl_n/devtree.c b/src/mainboard/starlabs/starbook/variants/adl_n/devtree.c
index bd90e07c07..1b01e25cb0 100644
--- a/src/mainboard/starlabs/starbook/variants/adl_n/devtree.c
+++ b/src/mainboard/starlabs/starbook/variants/adl_n/devtree.c
@@ -10,42 +10,10 @@
 #include <variants.h>
 #include <common/powercap.h>
 
-#define TJ_MAX		105
-#define TCC(temp)	(TJ_MAX - temp)
-
 void devtree_update(void)
 {
 	config_t *cfg = config_of_soc();
-
-	struct soc_power_limits_config *soc_conf_4core =
-		&cfg->power_limits_config[ADL_N_041_6W_CORE];
-
-	uint8_t performance_scale = 100;
-
-	/* Set PL4 to 1.0C */
-	soc_conf_4core->tdp_pl4			= 65;
-
-	/* Set PL1 to 50% of PL2 */
-	soc_conf_4core->tdp_pl1_override = (soc_conf_4core->tdp_pl2_override / 2) & ~1;
-
-	/* Scale PL1 & PL2 based on CMOS settings */
-	switch (get_power_profile(PP_POWER_SAVER)) {
-	case PP_POWER_SAVER:
-		performance_scale			-= 50;
-		cfg->tcc_offset				= TCC(80);
-		break;
-	case PP_BALANCED:
-		performance_scale			-= 25;
-		cfg->tcc_offset				= TCC(90);
-		break;
-	case PP_PERFORMANCE:
-		/* Use the Intel defaults */
-		cfg->tcc_offset				= TCC(100);
-		break;
-	}
-
-	soc_conf_4core->tdp_pl1_override = (soc_conf_4core->tdp_pl1_override * performance_scale) / 100;
-	soc_conf_4core->tdp_pl2_override = (soc_conf_4core->tdp_pl2_override * performance_scale) / 100;
+	update_power_limits(cfg);
 
 	/* Enable/Disable Bluetooth based on CMOS settings */
 	if (get_uint_option("bluetooth", 1) == 0)
diff --git a/src/mainboard/starlabs/starbook/variants/cml/devtree.c b/src/mainboard/starlabs/starbook/variants/cml/devtree.c
index 990b3c6143..980a472abc 100644
--- a/src/mainboard/starlabs/starbook/variants/cml/devtree.c
+++ b/src/mainboard/starlabs/starbook/variants/cml/devtree.c
@@ -10,41 +10,10 @@
 #include <variants.h>
 #include <common/powercap.h>
 
-#define TJ_MAX		100
-#define TCC(temp)	(TJ_MAX - temp)
-
 void devtree_update(void)
 {
 	config_t *cfg = config_of_soc();
-
-	struct soc_power_limits_config *soc_conf = &cfg->power_limits_config;
-
-	uint8_t performance_scale = 100;
-
-	/* Set PL4 to 1.0C */
-	soc_conf->tdp_pl4			= 45;
-
-	/* Set PL1 to 50% of PL2 */
-	soc_conf->tdp_pl1_override = (soc_conf->tdp_pl2_override / 2) & ~1;
-
-	/* Scale PL1 & PL2 based on CMOS settings */
-	switch (get_power_profile(PP_POWER_SAVER)) {
-	case PP_POWER_SAVER:
-		performance_scale		-= 50;
-		cfg->tcc_offset			= TCC(80);
-		break;
-	case PP_BALANCED:
-		performance_scale		-= 25;
-		cfg->tcc_offset			= TCC(90);
-		break;
-	case PP_PERFORMANCE:
-		/* Use the Intel defaults */
-		cfg->tcc_offset			= TCC(100);
-		break;
-	}
-
-	soc_conf->tdp_pl1_override = (soc_conf->tdp_pl1_override * performance_scale) / 100;
-	soc_conf->tdp_pl2_override = (soc_conf->tdp_pl2_override * performance_scale) / 100;
+	update_power_limits(cfg);
 
 	/* Enable/Disable WiFi based on CMOS settings */
 	if (get_uint_option("wifi", 1) == 0)
diff --git a/src/mainboard/starlabs/starbook/variants/kbl/devtree.c b/src/mainboard/starlabs/starbook/variants/kbl/devtree.c
index 56978fff11..2dd0f995ab 100644
--- a/src/mainboard/starlabs/starbook/variants/kbl/devtree.c
+++ b/src/mainboard/starlabs/starbook/variants/kbl/devtree.c
@@ -10,41 +10,10 @@
 #include <variants.h>
 #include <common/powercap.h>
 
-#define TJ_MAX		100
-#define TCC(temp)	(TJ_MAX - temp)
-
 void devtree_update(void)
 {
 	config_t *cfg = config_of_soc();
-
-	struct soc_power_limits_config *soc_conf = &cfg->power_limits_config;
-
-	uint8_t performance_scale = 100;
-
-	/* Set PL4 to 1.0C */
-	soc_conf->tdp_pl4			= 45;
-
-	/* Set PL1 to 50% of PL2 */
-	soc_conf->tdp_pl1_override = (soc_conf->tdp_pl2_override / 2) & ~1;
-
-	/* Scale PL1 & PL2 based on CMOS settings */
-	switch (get_power_profile(PP_POWER_SAVER)) {
-	case PP_POWER_SAVER:
-		performance_scale		-= 50;
-		cfg->tcc_offset			= TCC(80);
-		break;
-	case PP_BALANCED:
-		performance_scale		-= 25;
-		cfg->tcc_offset			= TCC(90);
-		break;
-	case PP_PERFORMANCE:
-		/* Use the Intel defaults */
-		cfg->tcc_offset			= TCC(100);
-		break;
-	}
-
-	soc_conf->tdp_pl1_override = (soc_conf->tdp_pl1_override * performance_scale) / 100;
-	soc_conf->tdp_pl2_override = (soc_conf->tdp_pl2_override * performance_scale) / 100;
+	update_power_limits(cfg);
 
 	/* Enable/Disable WiFi based on CMOS settings */
 	if (get_uint_option("wifi", 1) == 0)
diff --git a/src/mainboard/starlabs/starbook/variants/mtl/devtree.c b/src/mainboard/starlabs/starbook/variants/mtl/devtree.c
index 66c8179810..0b2cd1b959 100644
--- a/src/mainboard/starlabs/starbook/variants/mtl/devtree.c
+++ b/src/mainboard/starlabs/starbook/variants/mtl/devtree.c
@@ -10,42 +10,10 @@
 #include <variants.h>
 #include <common/powercap.h>
 
-#define TJ_MAX		110
-#define TCC(temp)	(TJ_MAX - temp)
-
 void devtree_update(void)
 {
 	config_t *cfg = config_of_soc();
-
-	struct soc_power_limits_config *soc_conf_20core =
-		&cfg->power_limits_config[MTL_P_682_482_CORE];
-
-	uint8_t performance_scale = 100;
-
-	/* Set PL4 to 1.0C */
-	soc_conf_20core->tdp_pl4			= 65;
-
-	/* Set PL1 to 50% of PL2 */
-	soc_conf_20core->tdp_pl1_override = (soc_conf_20core->tdp_pl2_override / 2) & ~1;
-
-	/* Scale PL1 & PL2 based on CMOS settings */
-	switch (get_power_profile(PP_POWER_SAVER)) {
-	case PP_POWER_SAVER:
-		performance_scale			-= 50;
-		cfg->tcc_offset				= TCC(80);
-		break;
-	case PP_BALANCED:
-		performance_scale			-= 25;
-		cfg->tcc_offset				= TCC(90);
-		break;
-	case PP_PERFORMANCE:
-		/* Use the Intel defaults */
-		cfg->tcc_offset				= TCC(100);
-		break;
-	}
-
-	soc_conf_20core->tdp_pl1_override = (soc_conf_20core->tdp_pl1_override * performance_scale) / 100;
-	soc_conf_20core->tdp_pl2_override = (soc_conf_20core->tdp_pl2_override * performance_scale) / 100;
+	update_power_limits(cfg);
 
 	/* Enable/Disable Bluetooth based on CMOS settings */
 	if (get_uint_option("bluetooth", 1) == 0)
diff --git a/src/mainboard/starlabs/starbook/variants/rpl/devtree.c b/src/mainboard/starlabs/starbook/variants/rpl/devtree.c
index 3485fdbb31..fe9ec1b3e2 100644
--- a/src/mainboard/starlabs/starbook/variants/rpl/devtree.c
+++ b/src/mainboard/starlabs/starbook/variants/rpl/devtree.c
@@ -10,50 +10,10 @@
 #include <variants.h>
 #include <common/powercap.h>
 
-#define TJ_MAX		110
-#define TCC(temp)	(TJ_MAX - temp)
-
 void devtree_update(void)
 {
 	config_t *cfg = config_of_soc();
-
-	struct soc_power_limits_config *soc_conf_6core =
-		&cfg->power_limits_config[RPL_P_282_242_142_15W_CORE];
-
-	struct soc_power_limits_config *soc_conf_12core =
-		&cfg->power_limits_config[RPL_P_682_482_282_28W_CORE];
-
-	uint8_t performance_scale = 100;
-
-	/* Set PL4 to 1.0C */
-	soc_conf_6core->tdp_pl4				= 65;
-	soc_conf_12core->tdp_pl4			= 65;
-
-	/* Set PL1 to 50% of PL2 */
-	soc_conf_6core->tdp_pl1_override = (soc_conf_6core->tdp_pl2_override / 2) & ~1;
-	soc_conf_12core->tdp_pl1_override = (soc_conf_12core->tdp_pl2_override / 2) & ~1;
-
-	/* Scale PL1 & PL2 based on CMOS settings */
-	switch (get_power_profile(PP_POWER_SAVER)) {
-	case PP_POWER_SAVER:
-		performance_scale			-= 50;
-		cfg->tcc_offset				= TCC(80);
-		break;
-	case PP_BALANCED:
-		performance_scale			-= 25;
-		cfg->tcc_offset				= TCC(90);
-		break;
-	case PP_PERFORMANCE:
-		/* Use the Intel defaults */
-		cfg->tcc_offset				= TCC(100);
-		break;
-	}
-
-	soc_conf_6core->tdp_pl1_override = (soc_conf_6core->tdp_pl1_override * performance_scale) / 100;
-	soc_conf_6core->tdp_pl2_override = (soc_conf_6core->tdp_pl2_override * performance_scale) / 100;
-
-	soc_conf_12core->tdp_pl1_override = (soc_conf_12core->tdp_pl1_override * performance_scale) / 100;
-	soc_conf_12core->tdp_pl2_override = (soc_conf_12core->tdp_pl2_override * performance_scale) / 100;
+	update_power_limits(cfg);
 
 	/* Enable/Disable Bluetooth based on CMOS settings */
 	if (get_uint_option("bluetooth", 1) == 0)
diff --git a/src/mainboard/starlabs/starbook/variants/tgl/devtree.c b/src/mainboard/starlabs/starbook/variants/tgl/devtree.c
index 7bfd6a560b..796624e1c6 100644
--- a/src/mainboard/starlabs/starbook/variants/tgl/devtree.c
+++ b/src/mainboard/starlabs/starbook/variants/tgl/devtree.c
@@ -10,50 +10,10 @@
 #include <variants.h>
 #include <common/powercap.h>
 
-#define TJ_MAX		100
-#define TCC(temp)	(TJ_MAX - temp)
-
 void devtree_update(void)
 {
 	config_t *cfg = config_of_soc();
-
-	struct soc_power_limits_config *soc_conf_2core =
-		&cfg->power_limits_config[POWER_LIMITS_U_2_CORE];
-
-	struct soc_power_limits_config *soc_conf_4core =
-		&cfg->power_limits_config[POWER_LIMITS_U_4_CORE];
-
-	uint8_t performance_scale = 100;
-
-	/* Set PL4 to 1.0C */
-	soc_conf_2core->tdp_pl4				= 65;
-	soc_conf_4core->tdp_pl4				= 65;
-
-	/* Set PL1 to 50% of PL2 */
-	soc_conf_2core->tdp_pl1_override = (soc_conf_2core->tdp_pl2_override / 2) & ~1;
-	soc_conf_4core->tdp_pl1_override = (soc_conf_4core->tdp_pl2_override / 2) & ~1;
-
-	/* Scale PL1 & PL2 based on CMOS settings */
-	switch (get_power_profile(PP_POWER_SAVER)) {
-	case PP_POWER_SAVER:
-		performance_scale			-= 50;
-		cfg->tcc_offset				= TCC(80);
-		break;
-	case PP_BALANCED:
-		performance_scale			-= 25;
-		cfg->tcc_offset				= TCC(90);
-		break;
-	case PP_PERFORMANCE:
-		/* Use the Intel defaults */
-		cfg->tcc_offset				= TCC(100);
-		break;
-	}
-
-	soc_conf_2core->tdp_pl1_override = (soc_conf_2core->tdp_pl1_override * performance_scale) / 100;
-	soc_conf_2core->tdp_pl2_override = (soc_conf_2core->tdp_pl2_override * performance_scale) / 100;
-
-	soc_conf_4core->tdp_pl1_override = (soc_conf_4core->tdp_pl1_override * performance_scale) / 100;
-	soc_conf_4core->tdp_pl2_override = (soc_conf_4core->tdp_pl2_override * performance_scale) / 100;
+	update_power_limits(cfg);
 
 	/* Enable/Disable WiFi based on CMOS settings */
 	if (get_uint_option("wifi", 1) == 0)
diff --git a/src/mainboard/starlabs/starfighter/Kconfig b/src/mainboard/starlabs/starfighter/Kconfig
index 1e12366501..5709ced88c 100644
--- a/src/mainboard/starlabs/starfighter/Kconfig
+++ b/src/mainboard/starlabs/starfighter/Kconfig
@@ -122,6 +122,14 @@ config SOC_INTEL_CSE_SEND_EOP_EARLY
 config TME_KEY_REGENERATION_ON_WARM_BOOT
 	default n
 
+config TJ_MAX
+	int
+	default 110
+
+config PL4_WATTS
+	int
+	default 80
+
 config TPM_PIRQ
 	depends on MAINBOARD_HAS_TPM2
 	default 0x3d if BOARD_STARLABS_STARFIGHTER_MTL
diff --git a/src/mainboard/starlabs/starfighter/cfr.c b/src/mainboard/starlabs/starfighter/cfr.c
index ff3567f860..146ffd6913 100644
--- a/src/mainboard/starlabs/starfighter/cfr.c
+++ b/src/mainboard/starlabs/starfighter/cfr.c
@@ -8,7 +8,7 @@
 #include <variants.h>
 #include <common/cfr.h>
 
-static struct sm_obj_form performance = {
+static struct sm_obj_form performance_group = {
 	.ui_name = "Performance",
 	.obj_list = (const struct sm_object *[]) {
 		&bluetooth_rtd3,
@@ -18,7 +18,7 @@ static struct sm_obj_form performance = {
 	},
 };
 
-static struct sm_obj_form processor = {
+static struct sm_obj_form processor_group = {
 	.ui_name = "Processor",
 	.obj_list = (const struct sm_object *[]) {
 		&me_state,
@@ -30,7 +30,7 @@ static struct sm_obj_form processor = {
 	},
 };
 
-static struct sm_obj_form power = {
+static struct sm_obj_form power_group = {
 	.ui_name = "Power",
 	.obj_list = (const struct sm_object *[]) {
 		&max_charge,
@@ -44,7 +44,7 @@ static struct sm_obj_form power = {
 	},
 };
 
-static struct sm_obj_form keyboard = {
+static struct sm_obj_form keyboard_group = {
 	.ui_name = "Keyboard",
 	.obj_list = (const struct sm_object *[]) {
 		&kbl_timeout,
@@ -53,7 +53,7 @@ static struct sm_obj_form keyboard = {
 	},
 };
 
-static struct sm_obj_form devices = {
+static struct sm_obj_form devices_group = {
 	.ui_name = "Devices",
 	.obj_list = (const struct sm_object *[]) {
 		#if CONFIG(SOC_INTEL_TIGERLAKE) || CONFIG(SOC_INTEL_ALDERLAKE) || CONFIG(SOC_INTEL_RAPTORLAKE)
@@ -73,7 +73,7 @@ static struct sm_obj_form devices = {
 	},
 };
 
-static struct sm_obj_form pci = {
+static struct sm_obj_form pci_group = {
 	.ui_name = "PCI",
 	.obj_list = (const struct sm_object *[]) {
 		#if CONFIG(SOC_INTEL_COMMON_BLOCK_ASPM)
@@ -88,7 +88,7 @@ static struct sm_obj_form pci = {
 	},
 };
 
-static struct sm_obj_form coreboot = {
+static struct sm_obj_form coreboot_group = {
 	.ui_name = "coreboot",
 	.obj_list = (const struct sm_object *[]) {
 		&debug_level,
@@ -97,13 +97,13 @@ static struct sm_obj_form coreboot = {
 };
 
 static struct sm_obj_form *sm_root[] = {
-	&performance,
-	&processor,
-	&power,
-	&keyboard,
-	&devices,
-	&pci,
-	&coreboot,
+	&performance_group,
+	&processor_group,
+	&power_group,
+	&keyboard_group,
+	&devices_group,
+	&pci_group,
+	&coreboot_group,
 	NULL
 };
 
diff --git a/src/mainboard/starlabs/starfighter/variants/mtl/devtree.c b/src/mainboard/starlabs/starfighter/variants/mtl/devtree.c
index a983bba747..c4b0da67fd 100644
--- a/src/mainboard/starlabs/starfighter/variants/mtl/devtree.c
+++ b/src/mainboard/starlabs/starfighter/variants/mtl/devtree.c
@@ -10,42 +10,10 @@
 #include <variants.h>
 #include <common/powercap.h>
 
-#define TJ_MAX		110
-#define TCC(temp)	(TJ_MAX - temp)
-
 void devtree_update(void)
 {
 	config_t *cfg = config_of_soc();
-
-	struct soc_power_limits_config *soc_conf_20core =
-		&cfg->power_limits_config[MTL_P_682_482_CORE];
-
-	uint8_t performance_scale = 100;
-
-	/* Set PL4 to 1.0C */
-	soc_conf_20core->tdp_pl4			= 65;
-
-	/* Set PL1 to 50% of PL2 */
-	soc_conf_20core->tdp_pl1_override = (soc_conf_20core->tdp_pl2_override / 2) & ~1;
-
-	/* Scale PL1 & PL2 based on CMOS settings */
-	switch (get_power_profile(PP_POWER_SAVER)) {
-	case PP_POWER_SAVER:
-		performance_scale			-= 50;
-		cfg->tcc_offset				= TCC(80);
-		break;
-	case PP_BALANCED:
-		performance_scale			-= 25;
-		cfg->tcc_offset				= TCC(90);
-		break;
-	case PP_PERFORMANCE:
-		/* Use the Intel defaults */
-		cfg->tcc_offset				= TCC(100);
-		break;
-	}
-
-	soc_conf_20core->tdp_pl1_override = (soc_conf_20core->tdp_pl1_override * performance_scale) / 100;
-	soc_conf_20core->tdp_pl2_override = (soc_conf_20core->tdp_pl2_override * performance_scale) / 100;
+	update_power_limits(cfg);
 
 	/* Enable/Disable Webcam based on CMOS settings */
 	if (get_uint_option("webcam", 1) == 0)
diff --git a/src/mainboard/starlabs/starfighter/variants/rpl/devtree.c b/src/mainboard/starlabs/starfighter/variants/rpl/devtree.c
index b094c7c2fb..aea5d89b40 100644
--- a/src/mainboard/starlabs/starfighter/variants/rpl/devtree.c
+++ b/src/mainboard/starlabs/starfighter/variants/rpl/devtree.c
@@ -10,50 +10,10 @@
 #include <variants.h>
 #include <common/powercap.h>
 
-#define TJ_MAX		110
-#define TCC(temp)	(TJ_MAX - temp)
-
 void devtree_update(void)
 {
 	config_t *cfg = config_of_soc();
-
-	struct soc_power_limits_config *soc_conf_6core =
-		&cfg->power_limits_config[RPL_P_282_242_142_15W_CORE];
-
-	struct soc_power_limits_config *soc_conf_14core =
-		&cfg->power_limits_config[RPL_P_682_642_482_45W_CORE];
-
-	uint8_t performance_scale = 100;
-
-	/* Set PL4 to 1.0C */
-	soc_conf_6core->tdp_pl4				= 65;
-	soc_conf_14core->tdp_pl4			= 65;
-
-	/* Set PL1 to 50% of PL2 */
-	soc_conf_6core->tdp_pl1_override = (soc_conf_6core->tdp_pl2_override / 2) & ~1;
-	soc_conf_14core->tdp_pl1_override = (soc_conf_14core->tdp_pl2_override / 2) & ~1;
-
-	/* Scale PL1 & PL2 based on CMOS settings */
-	switch (get_power_profile(PP_POWER_SAVER)) {
-	case PP_POWER_SAVER:
-		performance_scale			-= 50;
-		cfg->tcc_offset				= TCC(80);
-		break;
-	case PP_BALANCED:
-		performance_scale			-= 25;
-		cfg->tcc_offset				= TCC(90);
-		break;
-	case PP_PERFORMANCE:
-		/* Use the Intel defaults */
-		cfg->tcc_offset				= TCC(100);
-		break;
-	}
-
-	soc_conf_6core->tdp_pl1_override = (soc_conf_6core->tdp_pl1_override * performance_scale) / 100;
-	soc_conf_6core->tdp_pl2_override = (soc_conf_6core->tdp_pl2_override * performance_scale) / 100;
-
-	soc_conf_14core->tdp_pl1_override = (soc_conf_14core->tdp_pl1_override * performance_scale) / 100;
-	soc_conf_14core->tdp_pl2_override = (soc_conf_14core->tdp_pl2_override * performance_scale) / 100;
+	update_power_limits(cfg);
 
 	/* Enable/Disable Bluetooth based on CMOS settings */
 	if (get_uint_option("bluetooth", 1) == 0)
diff --git a/src/mainboard/starlabs/starlite_adl/Kconfig b/src/mainboard/starlabs/starlite_adl/Kconfig
index 6e66d653b0..00c2a4ecb5 100644
--- a/src/mainboard/starlabs/starlite_adl/Kconfig
+++ b/src/mainboard/starlabs/starlite_adl/Kconfig
@@ -100,6 +100,14 @@ config EDK2_BOOTSPLASH_FILE
 config SOC_INTEL_CSE_SEND_EOP_EARLY
 	default n
 
+config TJ_MAX
+	int
+	default 105
+
+config PL4_WATTS
+	int
+	default 37
+
 config UART_FOR_CONSOLE
 	default 0
 
diff --git a/src/mainboard/starlabs/starlite_adl/cfr.c b/src/mainboard/starlabs/starlite_adl/cfr.c
index da0b77bd94..7bbe25d61f 100644
--- a/src/mainboard/starlabs/starlite_adl/cfr.c
+++ b/src/mainboard/starlabs/starlite_adl/cfr.c
@@ -19,7 +19,7 @@ void cfr_card_reader_update(struct sm_object *new_obj)
 		new_obj->sm_bool.flags = CFR_OPTFLAG_SUPPRESS;
 }
 
-static struct sm_obj_form performance = {
+static struct sm_obj_form performance_group = {
 	.ui_name = "Performance",
 	.obj_list = (const struct sm_object *[]) {
 		&bluetooth_rtd3,
@@ -29,7 +29,7 @@ static struct sm_obj_form performance = {
 	},
 };
 
-static struct sm_obj_form processor = {
+static struct sm_obj_form processor_group = {
 	.ui_name = "Processor",
 	.obj_list = (const struct sm_object *[]) {
 		&me_state,
@@ -40,7 +40,7 @@ static struct sm_obj_form processor = {
 	},
 };
 
-static struct sm_obj_form power = {
+static struct sm_obj_form power_group = {
 	.ui_name = "Power",
 	.obj_list = (const struct sm_object *[]) {
 		&max_charge,
@@ -54,7 +54,7 @@ static struct sm_obj_form power = {
 	},
 };
 
-static struct sm_obj_form devices = {
+static struct sm_obj_form devices_group = {
 	.ui_name = "Devices",
 	.obj_list = (const struct sm_object *[]) {
 		&accelerometer,
@@ -75,7 +75,7 @@ static struct sm_obj_form devices = {
 	},
 };
 
-static struct sm_obj_form pci = {
+static struct sm_obj_form pci_group = {
 	.ui_name = "PCI",
 	.obj_list = (const struct sm_object *[]) {
 		#if CONFIG(SOC_INTEL_COMMON_BLOCK_ASPM)
@@ -87,7 +87,7 @@ static struct sm_obj_form pci = {
 	},
 };
 
-static struct sm_obj_form coreboot = {
+static struct sm_obj_form coreboot_group = {
 	.ui_name = "coreboot",
 	.obj_list = (const struct sm_object *[]) {
 		&debug_level,
@@ -96,12 +96,12 @@ static struct sm_obj_form coreboot = {
 };
 
 static struct sm_obj_form *sm_root[] = {
-	&performance,
-	&processor,
-	&power,
-	&devices,
-	&pci,
-	&coreboot,
+	&performance_group,
+	&processor_group,
+	&power_group,
+	&devices_group,
+	&pci_group,
+	&coreboot_group,
 	NULL
 };
 
diff --git a/src/mainboard/starlabs/starlite_adl/variants/mk_v/devtree.c b/src/mainboard/starlabs/starlite_adl/variants/mk_v/devtree.c
index 1f1dd8fd28..4a13543bf6 100644
--- a/src/mainboard/starlabs/starlite_adl/variants/mk_v/devtree.c
+++ b/src/mainboard/starlabs/starlite_adl/variants/mk_v/devtree.c
@@ -10,43 +10,10 @@
 #include <variants.h>
 #include <common/powercap.h>
 
-#define TJ_MAX		105
-#define TCC(temp)	(TJ_MAX - temp)
-
 void devtree_update(void)
 {
 	config_t *cfg = config_of_soc();
-
-	struct soc_power_limits_config *soc_conf_4core =
-		&cfg->power_limits_config[ADL_N_041_6W_CORE];
-
-	uint8_t performance_scale = 100;
-
-	/* Set PL4 to 1.0C */
-	soc_conf_4core->tdp_pl4				= 37;
-
-	/* Set PL1 to 50% of PL2 */
-	soc_conf_4core->tdp_pl1_override = (soc_conf_4core->tdp_pl2_override / 2) & ~1;
-
-	/* Scale PL1 & PL2 based on CMOS settings */
-	switch (get_power_profile(PP_POWER_SAVER)) {
-	case PP_POWER_SAVER:
-		performance_scale			-= 50;
-		cfg->tcc_offset				= TCC(70);
-		break;
-	case PP_BALANCED:
-		performance_scale			-= 25;
-		cfg->tcc_offset				= TCC(80);
-		break;
-	case PP_PERFORMANCE:
-		/* Use the Intel defaults */
-		cfg->tcc_offset				= TCC(90);
-		break;
-	}
-
-	soc_conf_4core->tdp_pl1_override = (soc_conf_4core->tdp_pl1_override * performance_scale) / 100;
-	soc_conf_4core->tdp_pl2_override = (soc_conf_4core->tdp_pl2_override * performance_scale) / 100;
-
+	update_power_limits(cfg);
 
 	/* Enable/Disable WiFi based on CMOS settings */
 	if (get_uint_option("wifi", 1) == 0)

From 9c19c973f6e5fd20dcc2a6474fb9dbcb966d92a4 Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Tue, 20 Jan 2026 14:05:28 +0000
Subject: [PATCH 3084/3886] mb/starlabs/starlite_adl: Adjust FMAP to match
 descriptor

Adjust the FMAP to match a newer version of the descriptor generated
with mFIT.

Change-Id: Id2eeec5269e8988e425e497f797645fa940922b3
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90822
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
---
 src/mainboard/starlabs/starlite_adl/variants/mk_v/board.fmd | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/mainboard/starlabs/starlite_adl/variants/mk_v/board.fmd b/src/mainboard/starlabs/starlite_adl/variants/mk_v/board.fmd
index 9cf12adf81..2197262237 100644
--- a/src/mainboard/starlabs/starlite_adl/variants/mk_v/board.fmd
+++ b/src/mainboard/starlabs/starlite_adl/variants/mk_v/board.fmd
@@ -1,7 +1,7 @@
 FLASH	0x1000000 {
 	SI_ALL	0x600000 {
 		SI_DESC			0x1000
-		SI_ME			0x412000
+		SI_ME			0x411000
 	}
 	SI_BIOS 0xa00000 {
 		EC@0x0			0x20000

From b2c24afcf55853bdede7d7bf7832978258db2493 Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Tue, 20 Jan 2026 14:06:30 +0000
Subject: [PATCH 3085/3886] mb/starlabs/starfighter/mtl: Adjust FMAP to match
 descriptor

Adjust the FMAP to match a newer version of the descriptor generated
with mFIT.

Change-Id: I546697f5c3352358a715f8783a7eda650c771c78
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90823
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/starlabs/starfighter/variants/mtl/board.fmd | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/mainboard/starlabs/starfighter/variants/mtl/board.fmd b/src/mainboard/starlabs/starfighter/variants/mtl/board.fmd
index ad7674988f..e88eaf2d0e 100644
--- a/src/mainboard/starlabs/starfighter/variants/mtl/board.fmd
+++ b/src/mainboard/starlabs/starfighter/variants/mtl/board.fmd
@@ -1,7 +1,7 @@
 FLASH	0x2000000 {
 	SI_ALL	0x1000000 {
 		SI_DESC			0x4000
-		SI_ME			0x80f000
+		SI_ME			0xbb1000
 	}
 	SI_BIOS 0x1000000 {
 		EC@0x0			0x20000

From 60c8496afe6e43901c774ac180965125c805fbc4 Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Fri, 9 Jan 2026 18:33:32 -0600
Subject: [PATCH 3086/3886] ec/starlabs/merlin: Add retry to get_ec_version()

Occasionally when reading the EC version from ECRAM, the major
version fails to read and returns zero. To avoid having an incorrect
version reported, retry up to 10x with a 10ms delay between retries.

TEST=build/boot various Starlabs hardware, update the EC firmware,
verify the EC version is reported correctly every time.

Change-Id: I78d921e7230e8e180041097672661e744f70dde2
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90834
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/ec/starlabs/merlin/ite.c | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/src/ec/starlabs/merlin/ite.c b/src/ec/starlabs/merlin/ite.c
index 953c9e3de6..ec4c9a65ab 100644
--- a/src/ec/starlabs/merlin/ite.c
+++ b/src/ec/starlabs/merlin/ite.c
@@ -1,6 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
 #include <console/console.h>
+#include <delay.h>
 #include <device/device.h>
 #include <device/pnp.h>
 #include <ec/acpi/ec.h>
@@ -17,6 +18,9 @@
 
 uint16_t ec_get_version(void)
 {
+	for (int i = 0; i < 10 && ec_read(ECRAM_MAJOR_VERSION) == 0; i++)
+		mdelay(10);
+
 	return (ec_read(ECRAM_MAJOR_VERSION) << 8) | ec_read(ECRAM_MINOR_VERSION);
 }
 

From 6118dbe0a3fcc775090698fc961b865a7f93d355 Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Tue, 20 Jan 2026 14:26:12 +0000
Subject: [PATCH 3087/3886] mb/starlabs/*: Set bluetooth_rdt3 to disabled by
 default

Change-Id: I78e526722446110821256698922c2a39eab24c9f
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90835
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
---
 src/mainboard/starlabs/common/include/common/cfr.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/mainboard/starlabs/common/include/common/cfr.h b/src/mainboard/starlabs/common/include/common/cfr.h
index faf9887b1f..1b89642133 100644
--- a/src/mainboard/starlabs/common/include/common/cfr.h
+++ b/src/mainboard/starlabs/common/include/common/cfr.h
@@ -28,7 +28,7 @@ static const struct sm_object bluetooth_rtd3 = SM_DECLARE_BOOL({
 	.ui_name	= "Bluetooth Runtime-D3",
 	.ui_helptext	= "Enable or disable Bluetooth power optimization.\n"
 			  "Recommended to disable when booting Windows.",
-	.default_value	= true,
+	.default_value	= false,
 });
 
 static const struct sm_object card_reader = SM_DECLARE_BOOL({

From 80d48a628843535fdcb56a5cae03f40b76c9566b Mon Sep 17 00:00:00 2001
From: alokagarwal <alok.agarwal@intel.com>
Date: Thu, 8 Jan 2026 21:05:16 +0530
Subject: [PATCH 3088/3886] vc/intel/fsp/fsp2_0/ptl: Expose all the UPDs

As Panther Lake code is moving to a new phase, the full FSP headers,
including all the UPDs, can now be published. This CL is not tied to the
FSP update; it only provides the full list of UPDs for the current FSP
version 3442.07.

Details:
- FspmUpd.h : Expose all UPDs
- FspsUpd.h : Expose all UPDs

BUG=b:474393325
TEST=Build fatcat without any errors.

Change-Id: If02f9bf8d920497b0dcb52f5652839fae7fd0919
Signed-off-by: Alok Agarwal <alok.agarwal@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90704
Reviewed-by: <srinivas.kulkarni@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Guvendik, Bora <bora.guvendik@intel.com>
Reviewed-by: Kim, Wonkyu <wonkyu.kim@intel.com>
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
Reviewed-by: Pranava Y N <pranavayn@google.com>
Reviewed-by: Sowmya, V <v.sowmya@intel.com>
Reviewed-by: Zhixing Ma <zhixing.ma@intel.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
---
 .../intel/fsp/fsp2_0/pantherlake/FspmUpd.h    | 1829 +++++++++++++++--
 .../intel/fsp/fsp2_0/pantherlake/FspsUpd.h    | 1681 ++++++++++++++-
 2 files changed, 3246 insertions(+), 264 deletions(-)

diff --git a/src/vendorcode/intel/fsp/fsp2_0/pantherlake/FspmUpd.h b/src/vendorcode/intel/fsp/fsp2_0/pantherlake/FspmUpd.h
index ac166e6ccf..cb221b9e14 100644
--- a/src/vendorcode/intel/fsp/fsp2_0/pantherlake/FspmUpd.h
+++ b/src/vendorcode/intel/fsp/fsp2_0/pantherlake/FspmUpd.h
@@ -93,9 +93,11 @@ typedef struct {
 **/
   UINT32                      SerialIoUartDebugCtsPinMux;
 
-/** Offset 0x0074 - Reserved
+/** Offset 0x0074 - SerialIo Uart PowerGating
+  Select SerialIo Uart Powergating mode
+  0:Disabled, 1:Enabled, 2:Auto
 **/
-  UINT8                       Reserved1;
+  UINT8                       SerialIoUartPowerGating;
 
 /** Offset 0x0075 - DCI Enable
   Determine if to enable DCI debug from host
@@ -110,9 +112,28 @@ typedef struct {
 **/
   UINT8                       DciDbcMode;
 
-/** Offset 0x0077 - Reserved
+/** Offset 0x0077 - DCI Clock Enable
+  Enable/Disable DCI clock in lowest power state
+  $EN_DIS
 **/
-  UINT8                       Reserved2[3];
+  UINT8                       DciClkEnable;
+
+/** Offset 0x0078 - Keep Early Trace
+  Trace is activated by default. When enable, keep early trace data and keep tracing,
+  may block s0ix.\n
+  When disabled will abandon trace data and stop tracing which allows enter s0ix\n
+  \n
+  noted:enable this option will not enable TraceHub; When probe is connected, keep
+  early trace will then be configured by tool, this option will not take effect.
+  $EN_DIS
+**/
+  UINT8                       KeepEarlyTrace;
+
+/** Offset 0x0079 - Enable/Disable MemoryOverlap check
+  Enable(Default): Enable MemoryOverlap check, Disable: Disable MemoryOverlap check
+  $EN_DIS
+**/
+  UINT8                       MemMapOverlapCheckSupport;
 
 /** Offset 0x007A - Memory Test on Warm Boot
   Run Base Memory Test on Warm Boot
@@ -122,7 +143,7 @@ typedef struct {
 
 /** Offset 0x007B - Reserved
 **/
-  UINT8                       Reserved3[5];
+  UINT8                       Reserved1[5];
 
 /** Offset 0x0080 - Platform Reserved Memory Size
   The minimum platform memory size required to pass control into DXE
@@ -137,7 +158,7 @@ typedef struct {
 
 /** Offset 0x008A - Reserved
 **/
-  UINT8                       Reserved4[6];
+  UINT8                       Reserved2[6];
 
 /** Offset 0x0090 - Memory SPD Pointer Controller 0 Channel 0 Dimm 0
   Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00
@@ -316,9 +337,19 @@ typedef struct {
 **/
   UINT8                       LowerBasicMemTestSize;
 
-/** Offset 0x01AD - Reserved
+/** Offset 0x01AD - EccGranularity32BEn
+  Reduce BasicMemTest size. 0: Disabled (default), regular BasicMemTest. 1: Enabled,
+  shorter BasicMemTest (faster boot)
+  $EN_DIS
 **/
-  UINT8                       Reserved5[2];
+  UINT8                       EccGranularity32BEn;
+
+/** Offset 0x01AE - EccCorrectionMode
+  Reduce BasicMemTest size. 0: Disabled (default), regular BasicMemTest. 1: Enabled,
+  shorter BasicMemTest (faster boot)
+  $EN_DIS
+**/
+  UINT8                       EccCorrectionMode;
 
 /** Offset 0x01AF - CaVrefHigh
   DDR5 CA Sweep High Vref Value for DDR5 OC
@@ -350,9 +381,13 @@ typedef struct {
 **/
   UINT8                       DFETap2StepSize;
 
-/** Offset 0x01B5 - Reserved
+/** Offset 0x01B5 - IbeccEccInjControl
+  IBECC Error Injection Control
+  0: No Error Injection, 1:Inject Correctable Error Address match, 3:Inject Correctable
+  Error on insertion counter, 5: Inject Uncorrectable Error Address match, 7:Inject
+  Uncorrectable Error on insertion counter
 **/
-  UINT8                       Reserved6;
+  UINT8                       IbeccEccInjControl;
 
 /** Offset 0x01B6 - VDD2 override
   VDD2 override for DDR5 OC; 0 - Auto
@@ -473,9 +508,17 @@ typedef struct {
 **/
   UINT16                      tCCD_L_WR;
 
-/** Offset 0x01E2 - Reserved
+/** Offset 0x01E2 - Periodic COMP
+  Enable/disable Periodic Compensation
+  $EN_DIS
 **/
-  UINT8                       Reserved7[2];
+  UINT8                       EnPeriodicComp;
+
+/** Offset 0x01E3 - LPMode4 Support
+  LPMode4 Options
+  0: Disable, 1:Enable, 2:Dynamic Threshold 2, 3:Dynamic Threshold 3
+**/
+  UINT8                       LpMode4;
 
 /** Offset 0x01E4 - LPMode Support
   Bit[0]: Enable Lpmode0p5 (Idle_enable), Bit[1]: Enable Lpmode2 (Powerdown_enable),
@@ -483,9 +526,17 @@ typedef struct {
 **/
   UINT8                       LpMode;
 
-/** Offset 0x01E5 - Reserved
+/** Offset 0x01E5 - Opportunistic Read
+  Enables/Disable Opportunistic Read (Def= Enable)
+  $EN_DIS
 **/
-  UINT8                       Reserved8[2];
+  UINT8                       OpportunisticRead;
+
+/** Offset 0x01E6 - Cycle Bypass Support
+  Enables/Disable Cycle Bypass Support(Def=Disable)
+  $EN_DIS
+**/
+  UINT8                       Disable2CycleBypass;
 
 /** Offset 0x01E7 - MRC OCSafeMode
   OverClocking Safe Mode for tCL
@@ -493,9 +544,13 @@ typedef struct {
 **/
   UINT8                       OCSafeMode;
 
-/** Offset 0x01E8 - Reserved
+/** Offset 0x01E8 - DQ Vref Ctrl Offset
+  Offset to be applied to DDRDATA7CH1_CR_DDRCRVREFADJUST1.Ch0VrefCtl
+  0xF4:-12,0xF5:-11, 0xF6:-10, 0xF7:-9, 0xF8:-8, 0xF9:-7, 0xFA:-6, 0xFB:-5, 0xFC:-4,
+  0xFD:-3, 0xFE:-2, 0xFF:-1, 0:0, 1:+1, 2:+2, 3:+3, 4:+4, 5:+5, 6:+6, 7:+7, 8:+8,
+  9:+9, 10:+10, 11:+11, 12:+12
 **/
-  UINT8                       Reserved9;
+  UINT8                       VrefCtlOffset;
 
 /** Offset 0x01E9 - Dqs Pins Interleaved Setting
   Indicates DqPinsInterleaved setting: board-dependent
@@ -536,9 +591,10 @@ typedef struct {
 **/
   UINT8                       ProbelessTrace;
 
-/** Offset 0x01EF - Reserved
+/** Offset 0x01EF - IbeccEccInjCount
+  Number of memory transactions between ECC error injection
 **/
-  UINT8                       Reserved10;
+  UINT8                       IbeccEccInjCount;
 
 /** Offset 0x01F0 - DDR Frequency Limit
   Maximum Memory Frequency Selections in Mhz. Options are 1067, 1333, 1600, 1867,
@@ -676,9 +732,11 @@ typedef struct {
 **/
   UINT8                       TXDQSDCC;
 
-/** Offset 0x0213 - Reserved
+/** Offset 0x0213 - Rx DQS Duty Cycle Correction
+  Enables/Disable Rx DQS Duty Cycle Correction
+  $EN_DIS
 **/
-  UINT8                       Reserved11;
+  UINT8                       RXDQSDCC;
 
 /** Offset 0x0214 - Ch Hash Override
   Select if Channel Hash setting values will be taken from input parameters or automatically
@@ -687,9 +745,17 @@ typedef struct {
 **/
   UINT8                       ChHashOverride;
 
-/** Offset 0x0215 - Reserved
+/** Offset 0x0215 - Voltage Readout
+  Enables/Disable Voltage Readout for VCCClk and PBias
+  $EN_DIS
 **/
-  UINT8                       Reserved12[2];
+  UINT8                       VoltageReadout;
+
+/** Offset 0x0216 - DQS Rise/Fall
+  Enables/Disable DQS Rise/Fall
+  $EN_DIS
+**/
+  UINT8                       DQSRF;
 
 /** Offset 0x0217 - DQS Rise/Fall
   Enables/Disable DQS Rise/Fall
@@ -697,9 +763,17 @@ typedef struct {
 **/
   UINT8                       RDDQSODTT;
 
-/** Offset 0x0218 - Reserved
+/** Offset 0x0218 - PreTraining
+  Enables/Disable PreTraining
+  $EN_DIS
 **/
-  UINT8                       Reserved13[2];
+  UINT8                       PRETRAIN;
+
+/** Offset 0x0219 - DUNIT Configuration
+  Enables/Disable Dunit Configuration
+  $EN_DIS
+**/
+  UINT8                       DUNITC;
 
 /** Offset 0x021A - Functional Duty Cycle Correction for DDR5 CLK
   Enable/Disable Functional Duty Cycle Correction for DDR5 CLK
@@ -729,9 +803,11 @@ typedef struct {
 **/
   UINT8                       DQDQSSWZ;
 
-/** Offset 0x021F - Reserved
+/** Offset 0x021F - LP5 Dca Training
+  Enable/Disable LP5 Dca Training
+  $EN_DIS
 **/
-  UINT8                       Reserved14;
+  UINT8                       DCCLP5READDCA;
 
 /** Offset 0x0220 - Functional Duty Cycle Correction for Data DQ
   Enable/Disable Functional Duty Cycle Correction for Data DQ
@@ -739,9 +815,39 @@ typedef struct {
 **/
   UINT8                       FUNCDCCDQ;
 
-/** Offset 0x0221 - Reserved
+/** Offset 0x0221 - SubCh Hash Override
+  Select if SubChannel Hash setting values will be taken from input parameters or
+  automatically taken from POR values depending on DRAM type detected. NOTE: ONLY
+  if Memory interleaved Mode
+  $EN_DIS
 **/
-  UINT8                       Reserved15[5];
+  UINT8                       SubChHashOverride;
+
+/** Offset 0x0222 - DDR5 Auto Precharge Enable
+  Auto Precharge Enable for DDR5: <b>O=Auto</b>, 1=Disable, 2=Enable
+  $EN_DIS
+**/
+  UINT8                       Ddr5AutoPrechargeEnable;
+
+/** Offset 0x0223 - Lp5 SplitACT Enable
+  SplitACT enable for LP5
+  0:Auto, 1:Disable, 2:Enable
+**/
+  UINT8                       Lp5SplitACTEnable;
+
+/** Offset 0x0224 - CCC Half Frequency
+  CCC Half Frequency (CccGear4) Mode: 0 = Auto (Default), 1 = Disable, 2 = GroupGv0
+  (SaGv0 only), 3 = GroupGv1 (Up to SaGv1), 4 = GroupGv2 (Up to SaGv2), 5 = GroupGv3
+  (Up to SaGv3)
+  0: Auto, 1: Disable, 2: GroupGv0, 3: GroupGv1, 4: GroupGv2, 5: GroupGv3
+**/
+  UINT8                       CccHalfFrequency;
+
+/** Offset 0x0225 - DIMM Non-Target ODT Training
+  Enables/Disable DIMM Non-Target ODT Training
+  $EN_DIS
+**/
+  UINT8                       DIMMNTODT;
 
 /** Offset 0x0226 - Unmatched Rx Calibration
   Enable/Disable Rx Unmatched Calibration
@@ -749,9 +855,60 @@ typedef struct {
 **/
   UINT8                       RXUNMATCHEDCAL;
 
-/** Offset 0x0227 - Reserved
+/** Offset 0x0227 - Hard Post Package Repair
+  Deprecated
+  $EN_DIS
 **/
-  UINT8                       Reserved16[10];
+  UINT8                       PPR;
+
+/** Offset 0x0228 - PPR Test Type
+  Deprecated
+**/
+  UINT8                       PprTestType;
+
+/** Offset 0x0229 - PPR Run Once
+  When Eanble, PPR will run only once and then is disabled at next training cycle
+  $EN_DIS
+**/
+  UINT8                       PprRunOnce;
+
+/** Offset 0x022A - PPR Run During Fastboot
+  Deprecated
+  $EN_DIS
+**/
+  UINT8                       PprRunAtFastboot;
+
+/** Offset 0x022B - PPR Repair Type
+  PPR Repair Type: 0:Do not Repair (Default), 1:Soft Repair, 2:Hard Repair
+  0:Do not Repair (Default), 1:Soft Repair, 2:Hard Repair
+**/
+  UINT8                       PprRepairType;
+
+/** Offset 0x022C - PPR Error Injection
+  When Eanble, PPR will inject bad rows during testing
+  $EN_DIS
+**/
+  UINT8                       PprErrorInjection;
+
+/** Offset 0x022D - PPR Repair Controller
+  Deprecated
+**/
+  UINT8                       PprRepairController;
+
+/** Offset 0x022E - PPR Repair Channel
+  Deprecated
+**/
+  UINT8                       PprRepairChannel;
+
+/** Offset 0x022F - PPR Repair Dimm
+  Deprecated
+**/
+  UINT8                       PprRepairDimm;
+
+/** Offset 0x0230 - PPR Repair Rank
+  Deprecated
+**/
+  UINT8                       PprRepairRank;
 
 /** Offset 0x0231 - Memory Slice Hash LSB Bit
   Memory Slice (Controller) Hash LSB bit. Valid values are 0..7 for BITS 6..13; used
@@ -766,9 +923,25 @@ typedef struct {
 **/
   UINT16                      MsHashMask;
 
-/** Offset 0x0234 - Reserved
+/** Offset 0x0234 - PPR Repair Row
+  Deprecated
 **/
-  UINT8                      Reserved17[13];
+  UINT32                      PprRepairRow;
+
+/** Offset 0x0238 - PPR Repair Physical Address Low
+  Deprecated
+**/
+  UINT32                      PprRepairPhysicalAddrLow;
+
+/** Offset 0x023C - PPR Repair Physical Address High
+  Deprecated
+**/
+  UINT32                      PprRepairPhysicalAddrHigh;
+
+/** Offset 0x0240 - PPR Repair BankGroup
+  Deprecated
+**/
+  UINT8                       PprRepairBankGroup;
 
 /** Offset 0x0241 - LVR Auto Trim
   Enable/disable LVR Auto Trim
@@ -788,9 +961,23 @@ typedef struct {
 **/
   UINT8                       WRTRETRAIN;
 
-/** Offset 0x0244 - Reserved
+/** Offset 0x0244 - DCC Phase Clk Calibration
+  Enable/disable DCC Phase Clk Calibration
+  $EN_DIS
 **/
-  UINT8                       Reserved18[3];
+  UINT8                       PHASECLKCAL;
+
+/** Offset 0x0245 - DCC Tline Clk Calibration
+  Enable/disable DCC Tline Clk Calibration
+  $EN_DIS
+**/
+  UINT8                       TLINECLKCAL;
+
+/** Offset 0x0246 - DCC Tline Serializer Calibration
+  Enable/disable DCC PI Serializer Calibratio
+  $EN_DIS
+**/
+  UINT8                       DCCPISERIALCAL;
 
 /** Offset 0x0247 - RDDQODTT
   Enable/disable Read DQ ODT Training
@@ -1000,9 +1187,11 @@ typedef struct {
 **/
   UINT8                       TAT;
 
-/** Offset 0x026A - Reserved
+/** Offset 0x026A - Rmt Even Odd
+  Enables/Disable Rmt Even Odd
+  $EN_DIS
 **/
-  UINT8                       Reserved19;
+  UINT8                       RMTEVENODD;
 
 /** Offset 0x026B - DIMM SPD Alias Test
   Enables/Disable DIMM SPD Alias Test
@@ -1028,9 +1217,17 @@ typedef struct {
 **/
   UINT8                       EccSupport;
 
-/** Offset 0x026F - Reserved
+/** Offset 0x026F - DLL DCC Calibration
+  Enables/Disable DLL DCC Calibration
+  $EN_DIS
 **/
-  UINT8                       Reserved20[2];
+  UINT8                       DLLDCC;
+
+/** Offset 0x0270 - DLL BW Select Calibration
+  Enables/Disable DLL BW Select Calibration
+  $EN_DIS
+**/
+  UINT8                       DLLBWSEL;
 
 /** Offset 0x0271 - Ibecc
   In-Band ECC Support
@@ -1044,9 +1241,11 @@ typedef struct {
 **/
   UINT8                       IbeccParity;
 
-/** Offset 0x0273 - Reserved
+/** Offset 0x0273 - MsHashEnable
+  Controller Hash Enable: 0=Disable, <b>1=Enable</b>
+  $EN_DIS
 **/
-  UINT8                       Reserved21;
+  UINT8                       MsHashEnable;
 
 /** Offset 0x0274 - IbeccOperationMode
   In-Band ECC Operation Mode
@@ -1062,7 +1261,7 @@ typedef struct {
 
 /** Offset 0x027D - Reserved
 **/
-  UINT8                       Reserved22;
+  UINT8                       Reserved3;
 
 /** Offset 0x027E - IbeccProtectedRegionBases
   IBECC Protected Region Bases per IBECC instance
@@ -1135,9 +1334,17 @@ typedef struct {
 **/
   UINT8                       ExitOnFailure;
 
-/** Offset 0x02A8 - Reserved
+/** Offset 0x02A8 - Wck Pad DCC Calibration
+  Enable/disable Wck Pad DCC Calibration
+  $EN_DIS
 **/
-  UINT8                       Reserved23[2];
+  UINT8                       WCKPADDCCCAL;
+
+/** Offset 0x02A9 - DCC PI Code LUT Calibration
+  Enable/Disable DCC PI Code LUT Calibration
+  $EN_DIS
+**/
+  UINT8                       DCCPICODELUT;
 
 /** Offset 0x02AA - Read Voltage Centering 1D
   Enable/Disable Read Voltage Centering 1D
@@ -1223,9 +1430,11 @@ typedef struct {
 **/
   UINT8                       RowPressEn;
 
-/** Offset 0x02B8 - Reserved
+/** Offset 0x02B8 - DBI feature
+  Enables/Disable DBI feature
+  $EN_DIS
 **/
-  UINT8                       Reserved24;
+  UINT8                       DBI;
 
 /** Offset 0x02B9 - DDR5 MR7 WICA support
   Enable if DDR5 DRAM Device supports MR7 WICA 0.5 tCK offset alignment
@@ -1252,9 +1461,10 @@ typedef struct {
 **/
   UINT16                      ChHashMask;
 
-/** Offset 0x02BE - Reserved
+/** Offset 0x02BE - CccPinsInterleaved
+  Interleaving mode of CCC pins which depends on board routing: <b>0=Disable</b>, 1=Enable
 **/
-  UINT8                       Reserved25;
+  UINT8                       CccPinsInterleaved;
 
 /** Offset 0x02BF - Throttler CKEMin Timer
   Timer value for CKEMin, range[255;0]. Req'd min of SC_ROUND_T + BYTE_LENGTH (4).
@@ -1333,7 +1543,12 @@ typedef struct {
 
 /** Offset 0x02CB - Reserved
 **/
-  UINT8                       Reserved26[5];
+  UINT8                       Reserved4;
+
+/** Offset 0x02CC - IbeccEccInjAddrBase
+  Address to match against for ECC error injection. Example: 1 = 32MB, 2 = 64MB
+**/
+  UINT32                      IbeccEccInjAddrBase;
 
 /** Offset 0x02D0 - DDR Phy Safe Mode Support
   DdrSafeMode[0]: Basic PM Features, DdrSafeMode[1]: Spine Gating, DdrSafeMode[2]:
@@ -1353,9 +1568,56 @@ typedef struct {
 **/
   UINT8                       CleanMemory;
 
-/** Offset 0x02D6 - Reserved
+/** Offset 0x02D6 - Tseg Retry Count
+  Tseg Retry count will increase based on TSEG Region Fail count
+  0: Default, 1:3
 **/
-  UINT8                       Reserved27[8];
+  UINT8                       RetryCount;
+
+/** Offset 0x02D7 - Mrc Ppr Status
+   Get Mrc PPR Status after PPR Recovery flow will get Trigger
+  0: PASS, 1: FAIL(Default)
+**/
+  UINT8                       MrcPprStatus;
+
+/** Offset 0x02D8 - Tseg Memory Test Status
+   If enabled, PPR Recovery flow will get Trigger
+  0: PASS, 1: FAIL(Default)
+**/
+  UINT8                       TsegMemoryTestStatus;
+
+/** Offset 0x02D9 - Ppr Recovery Status Enable
+  0: Disabled(Default), 1: Enabled.  If enabled, PPR Recovery flow will get Trigger.
+  $EN_DIS
+**/
+  UINT8                       PprRecoveryStatusEnable;
+
+/** Offset 0x02DA - Safe Loading Bios Enable State
+  0: Disabled(Default), 1: Enabled. If enabled, Memory diagnostic will perform for
+  TSEG Region.
+  $EN_DIS
+**/
+  UINT8                       SafeLoadingBiosEnableState;
+
+/** Offset 0x02DB - BDAT test type
+  When BdatEnable is set to TRUE, this option selects the type of data which will
+  be populated in the BIOS Data ACPI Tables: <b>0=RMT</b>, 1=RMT Per Bit, 2=Margin 2D.
+  0:RMT per Rank, 1:RMT per Bit, 2:Margin2D
+**/
+  UINT8                       MrcBdatTestType;
+
+/** Offset 0x02DC - MrcBdatEnable
+  0: Disabled(Default), 1: Enabled. This field enables the generation of the BIOS
+  DATA ACPI Tables: <b>0=FALSE</b>, 1=TRUE.
+  $EN_DIS
+**/
+  UINT8                       MrcBdatEnable;
+
+/** Offset 0x02DD - DisableMrcRetraining
+  0: Disabled(Default), 1: Enabled. Enable/Disable DisableMrcRetraining
+  $EN_DIS
+**/
+  UINT8                       DisableMrcRetraining;
 
 /** Offset 0x02DE - RMTLoopCount
   Specifies the Loop Count to be used during Rank Margin Tool Testing. 0 - AUTO
@@ -1391,7 +1653,7 @@ typedef struct {
 
 /** Offset 0x02E7 - Reserved
 **/
-  UINT8                       Reserved28;
+  UINT8                       Reserved5;
 
 /** Offset 0x02E8 - Margin limit check L2
   Margin limit check L2 threshold: <b>100=Default</b>
@@ -1404,9 +1666,12 @@ typedef struct {
 **/
   UINT8                       ExtendedBankHashing;
 
-/** Offset 0x02EB - Reserved
+/** Offset 0x02EB - DRFM Blast Radius Configuration
+  Row Hammer DRFM Blast Radius Configuration determines number of victim rows around
+  aggressor row targeted to send the DRFM sequence to: <b>2=BlastRadius 2</b>, 3=BlastRadius
+  3, 4=BlastRadius 4
 **/
-  UINT8                       Reserved29;
+  UINT8                       DrfmBrc;
 
 /** Offset 0x02EC - LP5 Command Pins Mapping
   BitMask where bits [3:0] are Controller 0 Channel [3:0] and bits [7:4] are Controller
@@ -1426,9 +1691,73 @@ typedef struct {
 **/
   UINT8                       MrcTimeMeasure;
 
-/** Offset 0x02EF - Reserved
+/** Offset 0x02EF - DVFSQ Enabled
+  Enable/Disable DVFSQ
+  $EN_DIS
 **/
-  UINT8                       Reserved30[43];
+  UINT8                       DvfsqEnabled;
+
+/** Offset 0x02F0 - E-DVFSC Enabled
+  Eanble/Disable DVFSC
+  $EN_DIS
+**/
+  UINT8                       DvfscEnabled;
+
+/** Offset 0x02F1 - Ddr5 Dca Training
+  Enable/Disable DDR5 Dca Training
+  $EN_DIS
+**/
+  UINT8                       DCCDDR5READDCA;
+
+/** Offset 0x02F2 - PPR Run WCHMATS8
+  Run WCHMATS8 in Post Package Repair flow
+**/
+  UINT8                       PprRunWCHMATS8;
+
+/** Offset 0x02F3 - PPR Run Retention
+  Run Data Retention in Post Package Repair flow
+**/
+  UINT8                       PprRunRetention;
+
+/** Offset 0x02F4 - PPR Run XMarch
+  Run XMarch in Post Package Repair flow
+**/
+  UINT8                       PprRunXMarch;
+
+/** Offset 0x02F5 - PPR Run XMarchG
+  Run XMarchG in Post Package Repair flow
+**/
+  UINT8                       PprRunXMarchG;
+
+/** Offset 0x02F6 - PPR Run YMarchShort
+  Run YMarchShort in Post Package Repair flow
+**/
+  UINT8                       PprRunYMarchShort;
+
+/** Offset 0x02F7 - PPR Run YMarchLong
+  Run YMarchLong in Post Package Repair flow
+**/
+  UINT8                       PprRunYMarchLong;
+
+/** Offset 0x02F8 - PPR Run Mmrw
+  Run Mmrw in Post Package Repair flow
+**/
+  UINT8                       PprRunMmrw;
+
+/** Offset 0x02F9 - PPR Test Disabled
+  Don't run any test in Post Package Repair flow
+**/
+  UINT8                       PprTestDisabled;
+
+/** Offset 0x02FA - PPR Entry Info
+  PPR Repair Info
+**/
+  UINT8                       PprEntryInfo[16];
+
+/** Offset 0x030A - PPR Entry Address
+  PPR Repair Memory Address
+**/
+  UINT8                       PprEntryAddress[16];
 
 /** Offset 0x031A - Read Vref Decap Training*
   Enable/Disable Read Timing Centering Training with SR stress*
@@ -1454,9 +1783,15 @@ typedef struct {
 **/
   UINT8                       IsWckIdleExitEnabled;
 
-/** Offset 0x031E - Reserved
+/** Offset 0x031E - LP5 Safe Speed
+  Enable / Disable LP5 Safe Speed feature
+  $EN_DIS
 **/
-  UINT8                       Reserved31[17];
+  UINT8                       Lp5SafeSpeed;
+
+/** Offset 0x031F - Reserved
+**/
+  UINT8                       Reserved6[16];
 
 /** Offset 0x032F - Board Type
   MrcBoardType, Options are 0=Mobile/Mobile Halo, 1=Desktop/DT Halo, 5=ULT/ULX/Mobile
@@ -1478,9 +1813,11 @@ typedef struct {
 **/
   UINT8                       TxtImplemented;
 
-/** Offset 0x0341 - Reserved
+/** Offset 0x0341 - PCIE Resizable BAR Support
+  Enable/Disable PCIE Resizable BAR Support.0: Disable; 1: Enable; 2: Auto(Default).
+  $EN_DIS
 **/
-  UINT8                       Reserved32;
+  UINT8                       PcieResizableBarSupport;
 
 /** Offset 0x0342 - Skip external display device scanning
   Enable: Do not scan for external display device, Disable (Default): Scan external
@@ -1608,7 +1945,7 @@ typedef struct {
 
 /** Offset 0x04D6 - Reserved
 **/
-  UINT8                       Reserved33[2];
+  UINT8                       Reserved7[2];
 
 /** Offset 0x04D8 - DMIC<N> ClkA Pin Muxing (N - DMIC number)
   Determines DMIC<N> ClkA Pin muxing. See  GPIO_*_MUXING_DMIC<N>_CLKA_*
@@ -1623,7 +1960,7 @@ typedef struct {
 
 /** Offset 0x04E1 - Reserved
 **/
-  UINT8                       Reserved34[3];
+  UINT8                       Reserved8[3];
 
 /** Offset 0x04E4 - DMIC<N> Data Pin Muxing
   Determines DMIC<N> Data Pin muxing. See GPIO_*_MUXING_DMIC<N>_DATA_*
@@ -1635,9 +1972,35 @@ typedef struct {
 **/
   UINT8                       PchHdaAudioLinkSspEnable[7];
 
-/** Offset 0x04F3 - Reserved
+/** Offset 0x04F3 - PCH Hda Disc Bt Off Enabled
+  Hda Disc Bt Off Enabled
 **/
-  UINT8                       Reserved35[117];
+  UINT8                       PchHdaDiscBtOffEnabled;
+
+/** Offset 0x04F4 - PCH HDA Discrete BT Offload Ssp Link
+  Discrete BT Offload Ssp Link
+**/
+  UINT32                      PchHdaDiscBtOffSspLink;
+
+/** Offset 0x04F8 - SSP<N> Sclk Pin Muxing (N - SSP Number)
+  Determines SSP<N> Sclk Pin muxing. See GPIOV2_*_MUXING_I2S*_SCLK
+**/
+  UINT32                      PchHdaAudioLinkSspSclkPinMux[7];
+
+/** Offset 0x0514 - SSP<N> Sfmr Pin Muxing (N - SSP Number)
+  Determines SSP<N> Sfmr Pin muxing. See GPIOV2_*_MUXING_I2S*_SFMR
+**/
+  UINT32                      PchHdaAudioLinkSspSfmrPinMux[7];
+
+/** Offset 0x0530 - SSP<N> Txd Pin Muxing (N - SSP Number)
+  Determines SSP<N> Txd Pin muxing. See GPIOV2_*_MUXING_I2S*_TXD
+**/
+  UINT32                      PchHdaAudioLinkSspTxdPinMux[7];
+
+/** Offset 0x054C - SSP<N> Rxd Pin Muxing (N - SSP Number)
+  Determines SSP<N> Rxd Pin muxing. See GPIOV2_*_MUXING_I2S*_RXD
+**/
+  UINT32                      PchHdaAudioLinkSspRxdPinMux[7];
 
 /** Offset 0x0568 - Enable HD Audio SoundWire#N Link
   Enable/disable HD Audio SNDW#N link. Muxed with HDA.
@@ -1656,9 +2019,41 @@ typedef struct {
 **/
   UINT8                       PchHdaIDispLinkTmode;
 
-/** Offset 0x056F - Reserved
+/** Offset 0x056F - Sndw Multilane enablement
+  SoundWire Multiline enablement. Default is DISABLE. 0: DISABLE, 1: Two lines enabled,
+  2: Three lines enabled, 3: Four Lines enabled.
+  $EN_DIS
 **/
-  UINT8                       Reserved36[45];
+  UINT8                       PchHdAudioSndwMultilaneEnable[2];
+
+/** Offset 0x0571 - Reserved
+**/
+  UINT8                       Reserved9[3];
+
+/** Offset 0x0574 - SoundWire<N> Clk Pin Muxing (N - SoundWire number)
+  Determines SoundWire<N> Clk Pin muxing. See  GPIOV2_*_MUXING_SNDW<N>_CLK*
+**/
+  UINT32                      PchHdaAudioLinkMultilaneClkPinMux[2];
+
+/** Offset 0x057C - SoundWire<N> Multilane Data0 Pin Muxing (N - SoundWire number)
+  Determines SoundWire<N> Multilane Clk Pin muxing. See  GPIOV2_*_MUXING_SNDW<N>_DATA0*
+**/
+  UINT32                      PchHdaAudioLinkMultilaneData0PinMux[2];
+
+/** Offset 0x0584 - SoundWire<N> Multilane Data1 Pin Muxing (N - SoundWire number)
+  Determines SoundWire<N> Multilane Clk Pin muxing. See  GPIOV2_*_MUXING_SNDW<N>_DATA1*
+**/
+  UINT32                      PchHdaAudioLinkMultilaneData1PinMux[2];
+
+/** Offset 0x058C - SoundWire<N> Multilane Data2 Pin Muxing (N - SoundWire number)
+  Determines SoundWire<N> Multilane Clk Pin muxing. See  GPIOV2_*_MUXING_SNDW<N>_DATA2*
+**/
+  UINT32                      PchHdaAudioLinkMultilaneData2PinMux[2];
+
+/** Offset 0x0594 - SoundWire<N> Multilane Data3 Pin Muxing (N - SoundWire number)
+  Determines SoundWire<N> Multilane Clk Pin muxing. See  GPIOV2_*_MUXING_SNDW<N>_DATA3*
+**/
+  UINT32                      PchHdaAudioLinkMultilaneData3PinMux[2];
 
 /** Offset 0x059C - iDisplay Audio Codec disconnection
   0: Not disconnected, enumerable, 1: Disconnected SDI, not enumerable.
@@ -1666,9 +2061,20 @@ typedef struct {
 **/
   UINT8                       PchHdaIDispCodecDisconnect;
 
-/** Offset 0x059D - Reserved
+/** Offset 0x059D - Sndw<N> Interface for Multilanes (N - SoundWire number)
+  0: Not disconnected, enumerable, 1: Disconnected SDI, not enumerable.
+  0: Sndw0, 1: Sndw1, 2: Sndw2, 3: Sndw3, 4: Sndw4, 5: Sndw5
 **/
-  UINT8                       Reserved37[5];
+  UINT8                       PchHdAudioSndwMultilaneSndwInterface[2];
+
+/** Offset 0x059F - Reserved
+**/
+  UINT8                       Reserved10;
+
+/** Offset 0x05A0 - Audio Sub System IDs
+  Set default Audio Sub System IDs. If its set to 0 then value from Strap is used.
+**/
+  UINT16                      ResetWaitTimer;
 
 /** Offset 0x05A2 - HDA Power/Clock Gating (PGD/CGD)
   Enable/Disable HD Audio Power and Clock Gating(POR: Enable). 0: PLATFORM_POR, 1:
@@ -1677,18 +2083,22 @@ typedef struct {
 **/
   UINT8                       PchHdaTestPowerClockGating;
 
-/** Offset 0x05A3 - Reserved
+/** Offset 0x05A3 - Low Frequency Link Clock Source (LFLCS)
+  0: POR (Enable), 1: Enable (XTAL), 2: Disable (Audio PLL).
+  0: POR (Enable), 1: Enable (XTAL), 2: Disable (Audio PLL)
 **/
-  UINT8                       Reserved38;
+  UINT8                       PchHdaTestLowFreqLinkClkSrc;
 
 /** Offset 0x05A4 - Audio Sub System IDs
   Set default Audio Sub System IDs. If its set to 0 then value from Strap is used.
 **/
   UINT32                      PchHdaSubSystemIds;
 
-/** Offset 0x05A8 - Reserved
+/** Offset 0x05A8 - SoundWire clock source select
+  Select clock source for the SoundWire controllers. 0: XTAL, 1: Audio PLL.
+  $EN_DIS
 **/
-  UINT8                       Reserved39;
+  UINT8                       PchHdaSndwClockSourceSelect;
 
 /** Offset 0x05A9 - PCH LPC Enhance the port 8xh decoding
   Original LPC only decodes one byte of port 80h.
@@ -1708,7 +2118,12 @@ typedef struct {
 
 /** Offset 0x05CE - Reserved
 **/
-  UINT8                       Reserved40[46];
+  UINT8                       Reserved11[14];
+
+/** Offset 0x05DC - Clk Req GPIO Pin
+  Select Clk Req Pin. Refer to GPIO_*_MUXING_SRC_CLKREQ_x* for possible values.
+**/
+  UINT32                      PcieClkReqGpioMux[8];
 
 /** Offset 0x05FC - Enable PCIE RP Mask
   Enable/disable PCIE Root Ports. 0: disable, 1: enable. One bit for each port, bit0
@@ -1724,7 +2139,7 @@ typedef struct {
 
 /** Offset 0x0601 - Reserved
 **/
-  UINT8                       Reserved41[3];
+  UINT8                       Reserved12[3];
 
 /** Offset 0x0604 - Serial Io Uart Debug Mmio Base
   Select SerialIo Uart default MMIO resource in SEC/PEI phase when PcdLpssUartMode
@@ -1799,9 +2214,13 @@ typedef struct {
 **/
   UINT8                       WdtDisableAndLock;
 
-/** Offset 0x061A - Reserved
+/** Offset 0x061A
 **/
-  UINT8                       Reserved42[2];
+  UINT8                       FabricGVDisable;
+
+/** Offset 0x061B - Reserved
+**/
+  UINT8                       Reserved13;
 
 /** Offset 0x061C - HECI Timeouts
   0: Disable, 1: Enable (Default) timeout check for HECI
@@ -1852,9 +2271,18 @@ typedef struct {
 **/
   UINT8                       SkipMbpHob;
 
-/** Offset 0x0624 - Reserved
+/** Offset 0x0624 - HECI Communication
+  Test, 0: POR, 1: enable, 2: disable, Disables HECI communication causing ME to enter
+  error state.
+  $EN_DIS
 **/
-  UINT8                       Reserved43[2];
+  UINT8                       HeciCommunication;
+
+/** Offset 0x0625 - HECI3 Interface Communication
+  Test, 0: POR, 1: enable, 2: disable, Adds or Removes HECI3 Device from PCI space.
+  $EN_DIS
+**/
+  UINT8                       HeciCommunication3;
 
 /** Offset 0x0626 - ISA Serial Base selection
   Select ISA Serial Base address. Default is 0x3F8.
@@ -1873,9 +2301,47 @@ typedef struct {
 **/
   UINT16                      PostCodeOutputPort;
 
-/** Offset 0x062A - Reserved
+/** Offset 0x062A - Enable/Disable I2cPostcode
+  Enable (Default): Postcode via I2C, Disable: Postcode via Port80
+  $EN_DIS
 **/
-  UINT8                       Reserved44[26];
+  UINT8                       I2cPostCodeEnable;
+
+/** Offset 0x062B - Reserved
+**/
+  UINT8                       Reserved14[5];
+
+/** Offset 0x0630 - FSPM Validation Pointer
+  Point to FSPM Validation configuration structure
+**/
+  UINT64                      FspmValidationPtr;
+
+/** Offset 0x0638 - Extended BIOS Support
+  Enable/Disable Extended BIOS Region Support. Default is DISABLE. 0: DISABLE, 1: ENABLE
+  $EN_DIS
+**/
+  UINT8                       ExtendedBiosDecodeRange;
+
+/** Offset 0x0639 - Extented BIOS Direct Read Decode enable
+  Enable/Disable access to bigger than 16MB BIOS Region through Direct Memory Reads.
+  0: disabled (default), 1: enabled
+  $EN_DIS
+**/
+  UINT8                       PchSpiExtendedBiosDecodeRangeEnable;
+
+/** Offset 0x063A - Reserved
+**/
+  UINT8                       Reserved15[2];
+
+/** Offset 0x063C - Extended BIOS Direct Read Decode Range base
+  Bits of 31:16 of a memory address that'll be a base for Extended BIOS Direct Read Decode.
+**/
+  UINT32                      PchSpiExtendedBiosDecodeRangeBase;
+
+/** Offset 0x0640 - Extended BIOS Direct Read Decode Range limit
+  Bits of 31:16 of a memory address that'll be a limit for Extended BIOS Direct Read Decode.
+**/
+  UINT32                      PchSpiExtendedBiosDecodeRangeLimit;
 
 /** Offset 0x0644 - Enable SMBus
   Enable/disable SMBus controller.
@@ -1896,7 +2362,7 @@ typedef struct {
 
 /** Offset 0x0647 - Reserved
 **/
-  UINT8                       Reserved45;
+  UINT8                       Reserved16;
 
 /** Offset 0x0648 - SMBUS Base Address
   SMBUS Base Address (IO space).
@@ -1911,7 +2377,7 @@ typedef struct {
 
 /** Offset 0x064B - Reserved
 **/
-  UINT8                       Reserved46[13];
+  UINT8                       Reserved17[13];
 
 /** Offset 0x0658 - Smbus dynamic power gating
   Disable or Enable Smbus dynamic power gating.
@@ -1932,9 +2398,51 @@ typedef struct {
 **/
   UINT8                       SaOcSupport;
 
-/** Offset 0x065B - Reserved
+/** Offset 0x065B - VF Point Count
+  Number of supported Voltage & Frequency Point Offset
 **/
-  UINT8                       Reserved47[18];
+  UINT8                       VfPointCount[10];
+
+/** Offset 0x0665 - ProcessVmaxLimit
+  Disabling Process Vmax Limit will allow user to set any voltage
+**/
+  UINT8                       ProcessVmaxLimit;
+
+/** Offset 0x0666 - CorePllCurrentRefTuningOffset
+  Core PLL Current Reference Tuning Offset. <b>0: No offset</b>. Range 0-15
+**/
+  UINT8                       CorePllCurrentRefTuningOffset;
+
+/** Offset 0x0667 - RingPllCurrentRefTuningOffset
+  Ring PLL Current Reference Tuning Offset. <b>0: No offset</b>. Range 0-15
+**/
+  UINT8                       RingPllCurrentRefTuningOffset;
+
+/** Offset 0x0668 - IaAtomPllCurrentRefTuningOffset
+  IaAtom PLL Current Reference Tuning Offset. <b>0: No offset</b>. Range 0-15
+**/
+  UINT8                       IaAtomPllCurrentRefTuningOffset;
+
+/** Offset 0x0669 - CoreMinRatio
+  equest Core Min Ratio. Limit Core minimum ratio for extreme overclocking. Default
+  0 indicates no request
+**/
+  UINT8                       CoreMinRatio;
+
+/** Offset 0x066A - CoreMiNegativeTemperatureReportingnRatio
+  Negative Temperature Reporting Enable. <b>0: Disable</b>, 1: enable
+**/
+  UINT8                       NegativeTemperatureReporting;
+
+/** Offset 0x066B - PcorePowerDensityThrottle
+  Power Density Throttle control allows user to disable P-core
+**/
+  UINT8                       PcorePowerDensityThrottle;
+
+/** Offset 0x066C - EcorePowerDensityThrottle
+  Power Density Throttle control allows user to disable P-core
+**/
+  UINT8                       EcorePowerDensityThrottle;
 
 /** Offset 0x066D - Over clocking support
   Over clocking support; <b>0: Disable</b>; 1: Enable
@@ -1942,9 +2450,12 @@ typedef struct {
 **/
   UINT8                       OcSupport;
 
-/** Offset 0x066E - Reserved
+/** Offset 0x066E - UnderVolt Protection
+  When UnderVolt Protection is enabled, user will be not be able to program under
+  voltage in OS runtime. 0: Disabled; <b>1: Enabled</b>
+  $EN_DIS
 **/
-  UINT8                       Reserved48;
+  UINT8                       UnderVoltProtection;
 
 /** Offset 0x066F - Realtime Memory Timing
   0(Default): Disabled, 1: Enabled. When enabled, it will allow the system to perform
@@ -2005,9 +2516,18 @@ typedef struct {
 **/
   UINT8                       Lfsr1Mask;
 
-/** Offset 0x067B - Reserved
+/** Offset 0x067B - Row Hammer DRAM Refresh Management Mode
+  Row Hammer Adaptive Refresh Management Level: 0-RFM (default), 1-ARFMLevel A, 2-ARFMLevel
+  B, 3-ARFMLevel C, 4-Disable ARFM and RFM
+  0: RFM, 1: ARFM Level A, 2: ARFM Level B, 3: ARFM Level C, 4: ARFM and RFM Disabled
 **/
-  UINT8                       Reserved49[2];
+  UINT8                       DramRfmMode;
+
+/** Offset 0x067C - Row Hammer Targeted Row Refresh Mode
+  Row Hammer Targeted Row Refresh: 0-DRFM, 1-pTRR (default), 2-Disable DRFM and pTRR
+  0: DRFM, 1: pTRR, 2: Targeted Row Refresh Disabled
+**/
+  UINT8                       TargetedRowRefreshMode;
 
 /** Offset 0x067D - TjMax Offset
   TjMax offset.Specified value here is clipped by pCode (125 - TjMax Offset) to support
@@ -2015,9 +2535,27 @@ typedef struct {
 **/
   UINT8                       TjMaxOffset;
 
-/** Offset 0x067E - Reserved
+/** Offset 0x067E - Per-Atom-Cluster VF Offset
+  Array used to specifies the selected Atom Core Cluster Offset Voltage. This voltage
+  is specified in millivolts.
 **/
-  UINT8                      Reserved50[48];
+  UINT16                      PerAtomClusterVoltageOffset[8];
+
+/** Offset 0x068E - Per-Atom-Cluster VF Offset Prefix
+  Sets the PerAtomCLusterVoltageOffset value as positive or negative for the selected
+  Core; <b>0: Positive </b>; 1: Negative.
+**/
+  UINT8                       PerAtomClusterVoltageOffsetPrefix[8];
+
+/** Offset 0x0696 - Per-Atom-Cluster Voltage Mode
+  Array used to specifies the selected Atom Core ClusterVoltage Mode.
+**/
+  UINT8                       PerAtomClusterVoltageMode[8];
+
+/** Offset 0x069E - Per-Atom-Cluster Voltage Override
+  Array used to specifies the selected Atom Core Cluster Voltage Override.
+**/
+  UINT16                      PerAtomClusterVoltageOverride[8];
 
 /** Offset 0x06AE - Core VF Point Offset
   Array used to specifies the Core Voltage Offset applied to the each selected VF
@@ -2037,9 +2575,28 @@ typedef struct {
 **/
   UINT8                       CoreVfPointRatio[15];
 
-/** Offset 0x06EA - Reserved
+/** Offset 0x06EA - Core VF Configuration Scope
+  Allows both all-core VF curve or per-core VF curve configuration; <b>0: All-core</b>;
+  1: Per-core.
+  0:All-core, 1:Per-core
 **/
-  UINT8                       Reserved51[26];
+  UINT8                       CoreVfConfigScope;
+
+/** Offset 0x06EB - Reserved
+**/
+  UINT8                       Reserved18;
+
+/** Offset 0x06EC - Per-core VF Offset
+  Array used to specifies the selected Core Offset Voltage. This voltage is specified
+  in millivolts.
+**/
+  UINT16                      PerCoreVoltageOffset[8];
+
+/** Offset 0x06FC - Per-core VF Offset Prefix
+  Sets the PerCoreVoltageOffset value as positive or negative for the selected Core;
+  <b>0: Positive </b>; 1: Negative.
+**/
+  UINT8                       PerCoreVoltageOffsetPrefix[8];
 
 /** Offset 0x0704 - Per Core Max Ratio override
   Enable or disable Per Core PState OC supported by writing OCMB 0x1D to program new
@@ -2048,18 +2605,30 @@ typedef struct {
 **/
   UINT8                       PerCoreRatioOverride;
 
-/** Offset 0x0705 - Reserved
+/** Offset 0x0705 - Per-core Voltage Mode
+  Array used to specifies the selected Core Voltage Mode.
 **/
-  UINT8                       Reserved52[25];
+  UINT8                       PerCoreVoltageMode[8];
+
+/** Offset 0x070D - Reserved
+**/
+  UINT8                       Reserved19;
+
+/** Offset 0x070E - Per-core Voltage Override
+  Array used to specifies the selected Core Voltage Override.
+**/
+  UINT16                      PerCoreVoltageOverride[8];
 
 /** Offset 0x071E - Per Core Current Max Ratio
   Array for the Per Core Max Ratio
 **/
   UINT8                       PerCoreRatio[8];
 
-/** Offset 0x0726 - Reserved
+/** Offset 0x0726 - Atom Cluster Max Ratio
+  Array for Atom Cluster Max Ratio, 4 ATOM cores are in the same Cluster and their
+  max core ratio will be aligned.
 **/
-  UINT8                       Reserved53[8];
+  UINT8                       AtomClusterRatio[8];
 
 /** Offset 0x072E - Pvd Ratio Threshold for SOC/CPU die
   Array of Pvd Ratio Threshold for SOC/CPU die is the threshold value for input ratio
@@ -2070,9 +2639,53 @@ typedef struct {
 **/
   UINT8                       PvdRatioThreshold;
 
-/** Offset 0x072F - Reserved
+/** Offset 0x072F - Pvd Mode SOC/CPU die
+  Array of PVD Mode. Value from 0 to 3 for SOC/CPU. 0x0 = div-1 (VCO = Output clock),
+  0x1 = div-2 (VCO = 2x Output clock), 0x2 = div-4 (VCO = 4x Output clock), 0x3 =
+  div-8 (VCO = 8x Output clock).
 **/
-  UINT8                       Reserved54[65];
+  UINT8                       PvdMode;
+
+/** Offset 0x0730 - FLL Overclock Mode
+  Select FLL Mode Value from 0 to 3. 0x0 = no overclocking, 0x1 = ratio overclocking
+  with nominal (0.5-1x) reference clock frequency, 0x2 = BCLK overclocking with elevated
+  (1-3x) reference clock frequency, 0x3 = BCLK overclocking with extreme elevated
+  (3-5x) reference clock frequency and ratio limited to 63.
+**/
+  UINT8                       FllOverclockMode;
+
+/** Offset 0x0731 - Reserved
+**/
+  UINT8                       Reserved20;
+
+/** Offset 0x0732 - Ring VF Point Offset
+  Array used to specifies the Ring Voltage Offset applied to the each selected VF
+  Point. This voltage is specified in millivolts.
+**/
+  UINT16                      RingVfPointOffset[15];
+
+/** Offset 0x0750 - Ring VF Point Offset Prefix
+  Sets the RingVfPointOffset value as positive or negative for corresponding core
+  VF Point; <b>0: Positive </b>; 1: Negative.
+**/
+  UINT8                       RingVfPointOffsetPrefix[15];
+
+/** Offset 0x075F - Ring VF Point Ratio
+  Array for the each selected Ring VF Point to display the ration.
+**/
+  UINT8                       RingVfPointRatio[15];
+
+/** Offset 0x076E - Soc Die SSC enable
+  Enable/Disable Soc-Die SSC Configuration. 0(Default)=Disable, 1=Enable
+  $EN_DIS
+**/
+  UINT8                       SocDieSscEnable;
+
+/** Offset 0x076F - Core Operating Point Reporting
+  Enables Core Operating point reporting. <b>0: Disable</b>; 1: Enable
+  0:Disable, 1:Enable
+**/
+  UINT8                       CoreOpPointReportingEn;
 
 /** Offset 0x0770 - CPU BCLK OC Frequency
   CPU BCLK OC Frequency in KHz units. 98000000Hz = 98MHz <b>0 - Auto</b>. Range is
@@ -2080,9 +2693,23 @@ typedef struct {
 **/
   UINT32                      CpuBclkOcFrequency;
 
-/** Offset 0x0774 - Reserved
+/** Offset 0x0774 - SOC BCLK OC Frequency
+  SOC BCLK OC Frequency in KHz units. 98000000Hz = 98MHz <b>0 - Auto</b>. Range is
+  40Mhz-1000Mhz.
 **/
-  UINT8                      Reserved55[13];
+  UINT32                      SocBclkOcFrequency;
+
+/** Offset 0x0778 - Bitmask of disable cores
+  Core mask is a bitwise indication of which core should be disabled. <b>0x00=Default</b>;
+  Bit 0 - core 0, bit 7 - core 7.
+**/
+  UINT64                      DisablePerCoreMask;
+
+/** Offset 0x0780 - Granular Ratio Override
+  Enable or disable OC Granular Ratio Override. <b>0: Disable</b>, 1: enable
+  $EN_DIS
+**/
+  UINT8                       GranularRatioOverride;
 
 /** Offset 0x0781 - Avx2 Voltage Guardband Scaling Factor
   AVX2 Voltage Guardband Scale factor applied to AVX2 workloads. Range is 0-200 in
@@ -2097,7 +2724,7 @@ typedef struct {
 
 /** Offset 0x0783 - Reserved
 **/
-  UINT8                       Reserved56[5];
+  UINT8                       Reserved21[5];
 
 /** Offset 0x0788 - Enable PCH ISH Controller
   0: Disable, 1: Enable (Default) ISH Controller
@@ -2107,7 +2734,7 @@ typedef struct {
 
 /** Offset 0x0789 - Reserved
 **/
-  UINT8                       Reserved57;
+  UINT8                       Reserved22;
 
 /** Offset 0x078A - BiosSize
   The size of the BIOS region of the IFWI. Used if FspmUpd->FspmConfig.BiosGuard !=
@@ -2140,9 +2767,24 @@ typedef struct {
 **/
   UINT8                       SkipStopPbet;
 
-/** Offset 0x0790 - Reserved
+/** Offset 0x0790 - Reset Auxiliary content
+  Reset Auxiliary content, <b>0: Disabled</b>, 1: Enabled
+  $EN_DIS
 **/
-  UINT8                       Reserved58[3];
+  UINT8                       ResetAux;
+
+/** Offset 0x0791 - TseEnable
+  Enable/Disable. 0: Disable, Enable/Disable Tse feature, 1: enable
+  $EN_DIS
+**/
+  UINT8                       TseEnable;
+
+/** Offset 0x0792 - Enable or Disable TDX
+  Configure Trust Domain Extension (TDX) to isolate VMs from Virtual-Machine Manager
+  (VMM)/hypervisor <b>0: Disable</b>; 1: Enable.
+  $EN_DIS
+**/
+  UINT8                       TdxEnable;
 
 /** Offset 0x0793 - MKTME Key-Id Bits Override Enable
   Configure Trust Domain Extension (TDX) to isolate VMs from Virtual-Machine Manager
@@ -2153,7 +2795,7 @@ typedef struct {
 
 /** Offset 0x0794 - Reserved
 **/
-  UINT8                       Reserved59[4];
+  UINT8                       Reserved23[4];
 
 /** Offset 0x0798 - TME Exclude Base Address
   TME Exclude Base Address.
@@ -2165,9 +2807,26 @@ typedef struct {
 **/
   UINT64                      TmeExcludeSize;
 
-/** Offset 0x07A8 - Reserved
+/** Offset 0x07A8 - TdxActmModuleAddr
+  Base address of Tdx Actm module, used for launching the Actm
 **/
-  UINT8                      Reserved60[14];
+  UINT64                      TdxActmModuleAddr;
+
+/** Offset 0x07B0 - TdxActmModuleSize
+  size of Tdx Actm module, used for launching the Actm
+**/
+  UINT32                      TdxActmModuleSize;
+
+/** Offset 0x07B4 - TdxSeamldrSvn
+  TdxSeamldrSvn
+**/
+  UINT8                       TdxSeamldrSvn;
+
+/** Offset 0x07B5 - Boot max frequency
+  Enable Boot Maximum Frequency in CPU strap. 0: Disable; <b>1: Enable</b>
+  $EN_DIS
+**/
+  UINT8                       BootMaxFrequency;
 
 /** Offset 0x07B6 - BIST on Reset
   Enable/Disable BIST (Built-In Self Test) on reset. <b>0: Disable</b>; 1: Enable.
@@ -2175,9 +2834,11 @@ typedef struct {
 **/
   UINT8                       BistOnReset;
 
-/** Offset 0x07B7 - Reserved
+/** Offset 0x07B7 - Reduce XeCores
+  Enable/Disable Reduce XeCores. <b>0: Disable(strap=1) </b>; 1: Enable(strap=0.
+  $EN_DIS
 **/
-  UINT8                       Reserved61;
+  UINT8                       ReduceXecores;
 
 /** Offset 0x07B8 - Enable or Disable VMX
   Enable or Disable VMX, When enabled, a VMM can utilize the additional hardware capabilities
@@ -2245,9 +2906,29 @@ typedef struct {
 **/
   UINT8                       ActiveCoreCount;
 
-/** Offset 0x07C2 - Reserved
+/** Offset 0x07C2 - Number of active small cores
+  Number of E-cores to enable in each processor package. Note: Number of P-Cores and
+  E-Cores are looked at together. When both are {0,0
+  0:Disable all small cores, 1:1, 2:2, 3:3, 0xFF:Active all small cores
 **/
-  UINT8                       Reserved62[6];
+  UINT8                       ActiveSmallCoreCount;
+
+/** Offset 0x07C3 - Number of LP Atom cores
+  Number of LP E-cores to enable in LP. 0: Disable all LP Atom cores; 1: 1; 2: 2;
+  <b>0xFF: Active all LP Atom cores</b>
+  0:Disable all LP Atom cores, 1:1, 2:2, 0xFF:Active all cores
+**/
+  UINT8                       ActiveLpAtomCoreCount;
+
+/** Offset 0x07C4 - DFD Enable
+  Enable or Disable DFD. <b>0: Disable</b>, 1:Enable
+  $EN_DIS
+**/
+  UINT8                       DfdEnable;
+
+/** Offset 0x07C5 - Reserved
+**/
+  UINT8                       Reserved24[3];
 
 /** Offset 0x07C8 - PrmrrSize
   Enable/Disable. 0: Disable, define default value of PrmrrSize , 1: enable
@@ -2275,7 +2956,351 @@ typedef struct {
 
 /** Offset 0x07D2 - Reserved
 **/
-  UINT8                       Reserved63[98];
+  UINT8                       Reserved25[2];
+
+/** Offset 0x07D4 - Platform PL1 power
+  Platform Power Limit 1 Power in Milli Watts. BIOS will round to the nearest 1/8W
+  when programming. Value set 120 = 15W. Any value can be programmed between Max
+  and Min Power Limits. This setting will act as the new PL1 value for the Package
+  RAPL algorithm. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit. Valid Range
+  0 to 32767.
+**/
+  UINT32                      PsysPowerLimit1Power;
+
+/** Offset 0x07D8 - PlatformAtxTelemetryUnit Mode
+  Enable/Disable PlatformAtxTelemetryUnit Mode.  <b>0: Disable</b> ; 1:Enable
+  $EN_DIS
+**/
+  UINT32                      PlatformAtxTelemetryUnit;
+
+/** Offset 0x07DC - Platform PL1 power
+   Short term Power Limit value for custom cTDP level. Units are 125 milliwatt.
+**/
+  UINT16                      CustomPowerLimit1;
+
+/** Offset 0x07DE - Platform PL1 power
+   Short term Power Limit value for custom cTDP level. Units are 125 milliwatt.
+**/
+  UINT16                      CustomPowerLimit2;
+
+/** Offset 0x07E0 - Platform PL2 power
+  Platform Power Limit 2 Power in Milli Watts. BIOS will round to the nearest 1/8W
+  when programming. Value set 120 = 15W. Any value can be programmed between Max
+  and Min Power Limits. This setting will act as the new Max Turbo Power (PL2) value
+  for the Package RAPL algorithm. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.
+  Valid Range 0 to 32767.
+**/
+  UINT32                      PsysPowerLimit2Power;
+
+/** Offset 0x07E4 - Vsys Max System battery volatge
+  Vsys Max defined in 1/1000 increments. Range is 0-65535. For a 1.25 voltage, enter
+  1250. <b>Default =0xFF</b>.
+**/
+  UINT16                      VsysMax;
+
+/** Offset 0x07E6 - ThETA Ibatt Feature
+  Enable or Disable ThETA Ibatt Feature. <b>0: Disable</b>; 1: Enable.
+  $EN_DIS
+**/
+  UINT8                       ThETAIbattEnable;
+
+/** Offset 0x07E7 - Reserved
+**/
+  UINT8                       Reserved26;
+
+/** Offset 0x07E8 - ISYS Current Limit L1
+  This field indicated the current limitiation of L1. Indicate current limit for which
+  dependency is on AC/DC mode before PSYS.Units of measurements are 1/8 A
+**/
+  UINT16                      IsysCurrentLimitL1;
+
+/** Offset 0x07EA - ISYS Current Limit L1 Tau
+  This Specifies the time window used to calculate average current for ISYS_L1. The
+  units of measuremnts are specified in PACKAGE_POWER_SKU[TIME_UNIT]
+**/
+  UINT8                       IsysCurrentL1Tau;
+
+/** Offset 0x07EB - Reserved
+**/
+  UINT8                       Reserved27;
+
+/** Offset 0x07EC - ISYS Current Limit L2
+  This bits enables disables ISYS_CURRENT_LIMIT_L2 algorithm.Indicate current limit
+  for which dependency is on AC/DC mode before PSYS. Units of measurements are 1/8 A
+**/
+  UINT16                      IsysCurrentLimitL2;
+
+/** Offset 0x07EE - ISYS Current Limit L1 Enable
+  This bits enables disables ISYS_CURRENT_LIMIT_L1 algorithm. It control loop based
+  on the system power source AC or DC mode. <b>0: Disable</b>; 1: Enable.
+  $EN_DIS
+**/
+  UINT8                       IsysCurrentLimitL1Enable;
+
+/** Offset 0x07EF - ISYS Current Limit L2 Enable
+  This bits enables disables ISYS_CURRENT_LIMIT_L2 algorithm. It control loop based
+  on the system power source AC or DC mode. <b>0: Disable</b>; 1: Enable.
+  $EN_DIS
+**/
+  UINT8                       IsysCurrentLimitL2Enable;
+
+/** Offset 0x07F0 - Package PL4 boost configuration
+  Configure Power Limit 4 Boost in Watts. Valid Range 0 to 63000 in step size of 125
+  mWatt. The value 0 means disable.
+**/
+  UINT16                      PowerLimit4Boost;
+
+/** Offset 0x07F2 - Skin Temperature Target
+  Target temperature is limit to which the control mechanism is regulating.It is defined
+  in 1/2 C increments.Range is 0-255. Temperature Range is 0-122.5 C.<b>0: Auto</b>.
+**/
+  UINT8                       SkinTargetTemp[3];
+
+/** Offset 0x07F5 - Skin Control Temperature Enable MMIO
+  Enables the skin temperature control for MMIO register. <b>0: Disable</b>; 1: Enable.
+  $EN_DIS
+**/
+  UINT8                       SkinTempControlEnable[3];
+
+/** Offset 0x07F8 - Skin Temperature Loop Gain
+  Sets the aggressiveness of control loop where 0 is graceful, favors performance
+  on expense of temperature overshoots and 7 is for aggressive, favors tight regulation
+  over performance. Range is 0-7.<b>0: Auto</b>.
+**/
+  UINT8                       SkinControlLoopGain[3];
+
+/** Offset 0x07FB - Skin Temperature Override Enable
+  When set, Pcode will use TEMPERATURE_OVERRIDE values instead of reading from corresponding
+  sensor.. <b>0: Disable</b>; 1: Enable.
+  $EN_DIS
+**/
+  UINT8                       SkinTempOverrideEnable[3];
+
+/** Offset 0x07FE - Skin Temperature Minimum Performance Level
+  Minimum Performance level below which the STC limit will not throttle. 0 - all levels
+  of throttling allowed incl. survivability actions. 256 - no throttling allowed.<b>0: Auto</b>.
+**/
+  UINT8                       SkinMinPerformanceLevel[3];
+
+/** Offset 0x0801 - Skin Temperature Override
+  Allows SW to override the input temperature. Pcode will use this value instead of
+  the sensor temperature. EC control is not impacted. Units: 0.5C. Values are 0 to
+  255 which represents 0C-122.5C range.<b>0: Auto</b>.
+**/
+  UINT8                       SkinTempOverride[3];
+
+/** Offset 0x0804 - Skin Temperature Control Enable
+  Enables Skin Temperature Control Sensors Feature. <b>0: Disable</b>; 1: Enable.
+  $EN_DIS
+**/
+  UINT8                       SkinTempControl;
+
+/** Offset 0x0805 - AC or DC Power State
+  AC or DC power State; <b>0: DC</b>; 1: AC
+  0:DC, 1:AC
+**/
+  UINT8                       AcDcPowerState;
+
+/** Offset 0x0806 - Enable or Disable VR Thermal Alert
+  Enable or Disable VR Thermal Alert; <b>0: Disable</b>; 1: Enable.
+  $EN_DIS
+**/
+  UINT8                       DisableVrThermalAlert;
+
+/** Offset 0x0807 - Enable or Disable Thermal Monitor
+  Enable or Disable Thermal Monitor; 0: Disable; <b>1: Enable</b>
+  $EN_DIS
+**/
+  UINT8                       ThermalMonitor;
+
+/** Offset 0x0808 - Configuration for boot TDP selection
+  Assured Power (cTDP) Mode as Nominal/Level1/Level2/Deactivate Base Power (TDP) selection.
+  Deactivate option will set MSR to Nominal and MMIO to Zero. <b>0: Base Power (TDP)
+  Nominal</b>; 1: Base Power (TDP) Down; 2: Base Power (TDP) Up;0xFF : Deactivate
+**/
+  UINT8                       ConfigTdpLevel;
+
+/** Offset 0x0809 - ConfigTdp mode settings Lock
+  Assured Power (cTDP) Mode Lock sets the Lock bits on TURBO_ACTIVATION_RATIO and
+  CONFIG_TDP_CONTROL. Note: When CTDP (Assured Power) Lock is enabled Custom ConfigTDP
+  Count will be forced to 1 and Custom ConfigTDP Boot Index will be forced to 0.
+  <b>0: Disable</b>; 1: Enable
+  $EN_DIS
+**/
+  UINT8                       ConfigTdpLock;
+
+/** Offset 0x080A - Load Configurable TDP SSDT
+  Enables Assured Power (cTDP) control via runtime ACPI BIOS methods. This 'BIOS only'
+  feature does not require EC or driver support. <b>0: Disable</b>; 1: Enable.
+  $EN_DIS
+**/
+  UINT8                       ConfigTdpBios;
+
+/** Offset 0x080B - CustomTurboActivationRatio
+  Turbo Activation Ratio for custom cTDP level
+  $EN_DIS
+**/
+  UINT8                       CustomTurboActivationRatio;
+
+/** Offset 0x080C - CustomPowerLimit1Time
+  Short term Power Limit time window value for custom cTDP level.
+  $EN_DIS
+**/
+  UINT8                       CustomPowerLimit1Time;
+
+/** Offset 0x080D - PL1 Enable value
+  Enable/Disable Platform Power Limit 1 programming. If this option is enabled, it
+  activates the PL1 value to be used by the processor to limit the average power
+  of given time window. <b>0: Disable</b>; 1: Enable.
+  $EN_DIS
+**/
+  UINT8                       PsysPowerLimit1;
+
+/** Offset 0x080E - PL1 timewindow
+  Platform Power Limit 1 Time Window value in seconds. The value may vary from 0 to
+  128. 0 = default values. Indicates the time window over which Platform Processor
+  Base Power (TDP) value should be maintained. Valid values(Unit in seconds) 0 to
+  8 , 10 , 12 ,14 , 16 , 20 , 24 , 28 , 32 , 40 , 48 , 56 , 64 , 80 , 96 , 112 , 128
+**/
+  UINT8                       PsysPowerLimit1Time;
+
+/** Offset 0x080F - PL2 Enable Value
+  Enable/Disable Platform Power Limit 2 programming. If this option is disabled, BIOS
+  will program the default values for Platform Power Limit 2. <b>0: Disable</b>;
+  1: Enable.
+  $EN_DIS
+**/
+  UINT8                       PsysPowerLimit2;
+
+/** Offset 0x0810 - Package PL3 time window
+  Power Limit 3 Time Window value in Milli seconds. Indicates the time window over
+  which Power Limit 3 value should be maintained. If the value is 0, BIOS leaves
+  the hardware default value. Valid value: <b>0</b>, 3-8, 10, 12, 14, 16, 20, 24,
+  28, 32, 40, 48, 56, 64.
+**/
+  UINT8                       PowerLimit3Time;
+
+/** Offset 0x0811 - Package Long duration turbo mode time
+  Power Limit 1 Time Window value in seconds. The value may vary from 0 to 128. 0
+  = default value (28 sec for Mobile and 8 sec for Desktop). Defines time window
+  which Processor Base Power (TDP) value should be maintained. Valid values(Unit
+  in seconds) 0 to 8 , 10 , 12 ,14 , 16 , 20 , 24 , 28 , 32 , 40 , 48 , 56 , 64 ,
+  80 , 96 , 112 , 128
+**/
+  UINT8                       PowerLimit1Time;
+
+/** Offset 0x0812 - Reserved
+**/
+  UINT8                       Reserved28[2];
+
+/** Offset 0x0814 - Package Long duration turbo mode power limit
+  Power Limit 1 in Milli Watts. BIOS will round to the nearest 1/8W when programming.
+  Value set 120 = 15W. 0 = no custom override. Overclocking SKU: Value must be between
+  Max and Min Power Limits. Other SKUs: This value must be between Min Power Limit
+  and Processor Base Power (TDP) Limit. If value is 0, BIOS will program Processor
+  Base Power (TDP) value. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit. Valid
+  Range 0 to 32767.
+**/
+  UINT32                      PowerLimit1;
+
+/** Offset 0x0818 - Package Short duration turbo mode power limit
+  Power Limit 2 in Milli Watts. BIOS will round to the nearest 1/8W when programming.
+  Value set 120 = 15W. If the value is 0, BIOS will program this value as 1.25*Processor
+  Base Power (TDP). Processor applies control policies such that the package power
+  does not exceed this limit. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.
+  Valid Range 0 to 32767.
+**/
+  UINT32                      PowerLimit2Power;
+
+/** Offset 0x081C - Package PL3 power limit
+  Power Limit 3 in Milli Watts. BIOS will round to the nearest 1/8W when programming.
+  Value set 120 = 15W. XE SKU: Any value can be programmed. Overclocking SKU: Value
+  must be between Max and Min Power Limits. Other SKUs: This value must be between
+  Min Power Limit and Processor Base Power (TDP) Limit. If the value is 0, BIOS leaves
+  the hardware default value. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.
+  Valid Range 0 to 32767.
+**/
+  UINT32                      PowerLimit3;
+
+/** Offset 0x0820 - Package PL4 power limit
+  Power Limit 4 in Milli Watts. BIOS will round to the nearest 1/8W when programming.
+  Value set 120 = 15W. If the value is 0, BIOS leaves default value. Units are based
+  on POWER_MGMT_CONFIG.CustomPowerUnit. Valid Range 0 to 32767.
+**/
+  UINT32                      PowerLimit4;
+
+/** Offset 0x0824 - Short term Power Limit value for custom cTDP level 1
+  Power Limit 1 in Milli Watts. BIOS will round to the nearest 1/8W when programming.
+  Value set 120 = 15W. 0 = no custom override. Overclocking SKU: Value must be between
+  Max and Min Power Limits. Other SKUs: This value must be between Min Power Limit
+  and Processor Base Power (TDP) Limit. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.
+  Valid Range 0 to 32767.
+**/
+  UINT32                      Custom1PowerLimit1;
+
+/** Offset 0x0828 - Long term Power Limit value for custom cTDP level 1
+  Power Limit 2 value in Milli Watts. BIOS will round to the nearest 1/8W when programming.
+  Value set 120 = 15W. 0 = no custom override. Processor applies control policies
+  such that the package power does not exceed this limit. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.
+  Valid Range 0 to 32767.
+**/
+  UINT32                      Custom1PowerLimit2;
+
+/** Offset 0x082C - Enable Configurable TDP
+  Applies Assured Power (cTDP) initialization settings based on non-Assured Power
+  (cTDP) or Assured Power (cTDP). Default is 1: Applies to Assured Power (cTDP) ;
+  if 0 then applies non-Assured Power (cTDP) and BIOS will bypass Assured Power (cTDP)
+  initialization flow
+  $EN_DIS
+**/
+  UINT8                       ApplyConfigTdp;
+
+/** Offset 0x082D - Dual Tau Boost
+  Enable Dual Tau Boost feature. This is only applicable for Desktop 35W/65W/125W
+  sku. When DPTF is enabled this feature is ignored. <b>0: Disable</b>; 1: Enable
+  $EN_DIS
+**/
+  UINT8                       DualTauBoost;
+
+/** Offset 0x082E - Tcc Offset Lock
+  Tcc Offset Lock for Runtime Average Temperature Limit (RATL) to lock temperature
+  target; <b>1:Enabled </b>; 0: Disabled.
+  $EN_DIS
+**/
+  UINT8                       TccOffsetLock;
+
+/** Offset 0x082F - Package PL3 Duty Cycle
+  Specify the duty cycle in percentage that the CPU is required to maintain over the
+  configured time window. Range is 0-100.
+**/
+  UINT8                       PowerLimit3DutyCycle;
+
+/** Offset 0x0830 - Package PL3 Lock
+  Power Limit 3 Lock. When enabled PL3 configurations are locked during OS. When disabled
+  PL3 configuration can be changed during OS. <b>0: Disable</b> ; 1:Enable
+  $EN_DIS
+**/
+  UINT8                       PowerLimit3Lock;
+
+/** Offset 0x0831 - Package PL4 Lock
+  Power Limit 4 Lock. When enabled PL4 configurations are locked during OS. When disabled
+  PL4 configuration can be changed during OS. <b>0: Disable</b> ; 1:Enable
+  $EN_DIS
+**/
+  UINT8                       PowerLimit4Lock;
+
+/** Offset 0x0832 - Short Duration Turbo Mode
+  Enable/Disable Power Limit 2 override. If this option is disabled, BIOS will program
+  the default values for Power Limit 2. 0: Disable; <b>1: Enable</b>
+  $EN_DIS
+**/
+  UINT8                       PowerLimit2;
+
+/** Offset 0x0833 - Response Mode
+  Enable/Disable Response Mode.  <b>0: Disable</b> ; 1:Enable
+  $EN_DIS
+**/
+  UINT8                       ResponseMode;
 
 /** Offset 0x0834 - SinitMemorySize
   Enable/Disable. 0: Disable, define default value of SinitMemorySize , 1: enable
@@ -2340,9 +3365,18 @@ typedef struct {
 **/
   UINT8                       AcousticNoiseMitigation;
 
-/** Offset 0x086E - Reserved
+/** Offset 0x086E - RfiMitigation
+  Enable or Disable RFI Mitigation. <b>0: Disable - DCM is the IO_N default</b>; 1:
+  Enable - Enable IO_N DCM/CCM switching as RFI mitigation.
+  $EN_DIS
 **/
-  UINT8                       Reserved64[2];
+  UINT8                       RfiMitigation;
+
+/** Offset 0x086F - Platform Psys slope correction
+  PSYS Slope defined in 1/100 increments. <b>0 - Auto</b> Specified in 1/100 increment
+  values. Range is 0-200. 125 = 1.25
+**/
+  UINT8                       PsysSlope;
 
 /** Offset 0x0870 - Platform Power Pmax
   PSYS PMax power, defined in 1/8 Watt increments. <b>0 - Auto</b> Specified in 1/8
@@ -2394,7 +3428,14 @@ typedef struct {
 
 /** Offset 0x08BA - Reserved
 **/
-  UINT8                       Reserved65[26];
+  UINT8                       Reserved29[2];
+
+/** Offset 0x08BC - Imon offset correction
+  IMON Offset is an 32-bit signed value (2's complement). Units 1/1000, Range is [-128000,
+  127999]. For an offset of 25.348, enter 25348. <b>0: Auto</b>. [0] for IA, [1]
+  for GT, [2] for SA, [3] through [5] are Reserved.
+**/
+  UINT32                      ImonOffset[6];
 
 /** Offset 0x08D4 - Icc Max limit
   Voltage Regulator Current Limit (Icc Max). This value represents the Maximum instantaneous
@@ -2404,9 +3445,34 @@ typedef struct {
 **/
   UINT16                      IccMax[6];
 
-/** Offset 0x08E0 - Reserved
+/** Offset 0x08E0 - VR Fast Vmode VoltageLimit support
+  Voltage Regulator Fast VoltageLimit .
 **/
-  UINT8                      Reserved66[42];
+  UINT16                      VrVoltageLimit[6];
+
+/** Offset 0x08EC - Imon slope correction
+  IMON Slope defined in 1/100 increments. Range is 0-200. For a 1.25 slope, enter
+  125. <b>0: Auto</b>. [0] for IA, [1] for GT, [2] for SA, [3] through [5] are Reserved.
+**/
+  UINT16                      ImonSlope[6];
+
+/** Offset 0x08F8 - Power State 3 enable/disable
+  PS3 Enable/Disable. 0 - Disabled, 1 - Enabled. [0] for IA, [1] for GT, [2] for SA,
+  [3] through [5] are Reserved.
+**/
+  UINT8                       Ps3Enable[6];
+
+/** Offset 0x08FE - Power State 4 enable/disable
+  PS4 Enable/Disable. 0 - Disabled, 1 - Enabled. [0] for IA, [1] for GT, [2] for SA,
+  [3] through [5] are Reserved.
+**/
+  UINT8                       Ps4Enable[6];
+
+/** Offset 0x0904 - Enable/Disable BIOS configuration of VR
+  VR Config Enable. [0] for IA, [1] for GT, [2] for SA, [3] through [5] are Reserved.
+  <b>0: Disable</b>; 1: Enable.
+**/
+  UINT8                       VrConfigEnable[6];
 
 /** Offset 0x090A - Thermal Design Current enable/disable
   Thermal Design Current enable/disable; <b>0: Disable</b>; 1: Enable. [0] for IA,
@@ -2414,9 +3480,11 @@ typedef struct {
 **/
   UINT8                       TdcEnable[6];
 
-/** Offset 0x0910 - Reserved
+/** Offset 0x0910 - Thermal Design Current Lock
+  Thermal Design Current Lock; <b>0: Disable</b>; 1: Enable. [0] for IA, [1] for GT,
+  [2] for SA, [3] for atom, [4]-[5] are Reserved.
 **/
-  UINT8                       Reserved67[6];
+  UINT8                       TdcLock[6];
 
 /** Offset 0x0916 - Disable Fast Slew Rate for Deep Package C States for VR domains
   This option needs to be configured to reduce acoustic noise during deeper C states.
@@ -2438,7 +3506,14 @@ typedef struct {
 
 /** Offset 0x0922 - Reserved
 **/
-  UINT8                       Reserved68[6];
+  UINT8                       Reserved30[2];
+
+/** Offset 0x0924 - Platform Psys offset correction
+  PSYS Offset defined in 1/1000 increments. <b>0 - Auto</b> This is an 32-bit signed
+  value (2's complement). Units 1/1000, Range is [-128000, 127999]. For an offset
+  of 25.348, enter 25348.
+**/
+  UINT32                      PsysOffset;
 
 /** Offset 0x0928 - Thermal Design Current time window
   Auto = 0 is default. Range is from 1ms to 448s. <b>0: Auto</b>. [0] for IA, [1]
@@ -2452,9 +3527,17 @@ typedef struct {
 **/
   UINT8                       TdcMode[6];
 
-/** Offset 0x0946 - Reserved
+/** Offset 0x0946 - DLVR RFI Enable
+  Enable/Disable DLVR RFI frequency hopping. 0: Disable; <b>1: Enable</b>.
+  $EN_DIS
 **/
-  UINT8                       Reserved69[2];
+  UINT8                       FivrSpectrumEnable;
+
+/** Offset 0x0947 - DLVR RFI Spread Spectrum Percentage
+  DLVR SSC in percentage with multiple of 0.25%. 0 = 0%, 10 = 4%. 0x00: 0% , <b>0x02:
+  0.5%</b>, 0x04: 1% , 0x08: 2% ,0x10: 4%; u3.2 value from 0% - 4%.
+**/
+  UINT8                       DlvrSpreadSpectrumPercentage;
 
 /** Offset 0x0948 - DLVR RFI Enable
   Enable/Disable DLVR RFI frequency hopping. 0: Disable; <b>1: Enable</b>.
@@ -2474,7 +3557,53 @@ typedef struct {
 
 /** Offset 0x094B - Reserved
 **/
-  UINT8                       Reserved70[11];
+  UINT8                       Reserved31;
+
+/** Offset 0x094C - DLVR RFI Frequency
+  DLVR RFI Frequency in MHz. <b>0: 2227 MHz</b> , 1: 2140MHZ.
+**/
+  UINT16                      DlvrRfiFrequency;
+
+/** Offset 0x094E - DLVR PHASE_SSC Enable
+  Enable/Disable DLVR PHASE_SSC. <b>0: Disable.</b> 1:Enable.
+  $EN_DIS
+**/
+  UINT8                       VrPowerDeliveryDesign;
+
+/** Offset 0x094F - DLVR PHASE_SSC Enable
+  Enable/Disable DLVR PHASE_SSC. <b>0: Disable.</b> 1:Enable.
+  $EN_DIS
+**/
+  UINT8                       DlvrPhaseSsc;
+
+/** Offset 0x0950 - Vsys Critical
+  PCODE MMIO Mailbox: Vsys Critical. <b>0: Disable</b>; 1: Enable Range is 0-255.
+**/
+  UINT8                       EnableVsysCritical;
+
+/** Offset 0x0951 - Assertion Deglitch Mantissa
+  Assertion Deglitch Mantissa, Range is 0-255
+**/
+  UINT8                       VsysAssertionDeglitchMantissa;
+
+/** Offset 0x0952 - Assertion Deglitch Exponent
+  Assertion Deglitch Exponent, Range is 0-255
+**/
+  UINT8                       VsysAssertionDeglitchExponent;
+
+/** Offset 0x0953 - De assertion Deglitch Mantissa
+  De assertion Deglitch Mantissa, Range is 0-255
+**/
+  UINT8                       VsysDeassertionDeglitchMantissa;
+
+/** Offset 0x0954 - De assertion Deglitch Exponent
+  De assertion Deglitch Exponent, Range is 0-255
+**/
+  UINT8                       VsysDeassertionDeglitchExponent;
+
+/** Offset 0x0955 - Reserved
+**/
+  UINT8                       Reserved32;
 
 /** Offset 0x0956 - VR Fast Vmode ICC Limit support
   Voltage Regulator Fast Vmode ICC Limit. A value of 400 = 100A. A value of 0 corresponds
@@ -2499,7 +3628,44 @@ typedef struct {
 
 /** Offset 0x096E - Reserved
 **/
-  UINT8                       Reserved71[28];
+  UINT8                       Reserved33[2];
+
+/** Offset 0x0970 - Vsys Full Scale
+  Vsys Full Scale, Range is 0-255000mV
+**/
+  UINT32                      VsysFullScale;
+
+/** Offset 0x0974 - Vsys Critical Threshold
+  Vsys Critical Threshold, Range is 0-255000mV
+**/
+  UINT32                      VsysCriticalThreshold;
+
+/** Offset 0x0978 - Psys Full Scale
+  Psys Full Scale, Range is 0-255000mV
+**/
+  UINT32                      PsysFullScale;
+
+/** Offset 0x097C - Psys Critical Threshold
+  Psys Critical Threshold, Range is 0-255000mV
+**/
+  UINT32                      PsysCriticalThreshold;
+
+/** Offset 0x0980 - Reserved
+**/
+  UINT8                       Reserved34[8];
+
+/** Offset 0x0988 - IOE Debug Enable
+  Enable/Disable IOE Debug. When enabled, IOE D2D Dfx link will keep up and clock
+  is enabled
+  $EN_DIS
+**/
+  UINT8                       IoeDebugEn;
+
+/** Offset 0x0989 - Pmode Clock Enable
+  Enable/Disable PMODE clock. When enabled, Pmode clock will toggle for XDP use
+  $EN_DIS
+**/
+  UINT8                       PmodeClkEn;
 
 /** Offset 0x098A - PCH Port80 Route
   Control where the Port 80h cycles are sent, 0: LPC; 1: PCI.
@@ -2514,9 +3680,21 @@ typedef struct {
 **/
   UINT8                       GpioOverride;
 
-/** Offset 0x098C - Reserved
+/** Offset 0x098C - Pmc Privacy Consent
+  Enable/Disable Pmc Privacy Consent
+  $EN_DIS
 **/
-  UINT8                       Reserved72[4];
+  UINT8                       PmcPrivacyConsent;
+
+/** Offset 0x098D - DMI ME UMA Root Space Check
+  DMI IOSF Root Space attribute check for RS3 for cycles targeting MEUMA.
+  0: POR, 1: enable, 2: disable
+**/
+  UINT8                       PchTestDmiMeUmaRootSpaceCheck;
+
+/** Offset 0x098E - Reserved
+**/
+  UINT8                       Reserved35[2];
 
 /** Offset 0x0990 - PMR Size
   Size of PMR memory buffer. 0x400000 for normal boot and 0x200000 for S3 boot
@@ -2540,9 +3718,11 @@ typedef struct {
 **/
   UINT8                       VtdDisable;
 
-/** Offset 0x0997 - Reserved
+/** Offset 0x0997 - State of Vtd Capabilities
+  0x0=(No operation), BIT0 = 1 (Defeature Nested Support), BIT1 = 1 (Defeature Posted
+  Interrupt Support)
 **/
-  UINT8                       Reserved73;
+  UINT8                       VtdCapabilityControl;
 
 /** Offset 0x0998 - Base addresses for VT-d function MMIO access
   Base addresses for VT-d MMIO access per VT-d engine
@@ -2551,7 +3731,17 @@ typedef struct {
 
 /** Offset 0x09BC - Reserved
 **/
-  UINT8                       Reserved74[20];
+  UINT8                       Reserved36[4];
+
+/** Offset 0x09C0 - MMIO Size
+  Size of MMIO space reserved for devices. 0(Default)=Auto, non-Zero=size in MB
+**/
+  UINT64                      MchBar;
+
+/** Offset 0x09C8 - MMIO Size
+  Size of MMIO space reserved for devices. 0(Default)=Auto, non-Zero=size in MB
+**/
+  UINT64                      RegBar;
 
 /** Offset 0x09D0 - MMIO Size
   Size of MMIO space reserved for devices. 0(Default)=Auto, non-Zero=size in MB
@@ -2564,9 +3754,50 @@ typedef struct {
 **/
   UINT16                      MmioSizeAdjustment;
 
-/** Offset 0x09D4 - Reserved
+/** Offset 0x09D4 - Temporary address for ApicLocalAddress
+  The reference code will use this as Temporary address space
 **/
-  UINT8                      Reserved75[36];
+  UINT32                      ApicLocalAddress;
+
+/** Offset 0x09D8 - Temporary address for NvmeHcPeiMmioBase
+  The reference code will use this as Temporary address space
+**/
+  UINT32                      NvmeHcPeiMmioBase;
+
+/** Offset 0x09DC - Temporary address for NvmeHcPeiMmioLimit
+  The reference code will use this as Temporary address space
+**/
+  UINT32                      NvmeHcPeiMmioLimit;
+
+/** Offset 0x09E0 - Temporary address for AhciPeiMmioBase
+  The reference code will use this as Temporary address space
+**/
+  UINT32                      AhciPeiMmioBase;
+
+/** Offset 0x09E4 - Temporary address for AhciPeiMmioLimit
+  The reference code will use this as Temporary address space
+**/
+  UINT32                      AhciPeiMmioLimit;
+
+/** Offset 0x09E8 - Temporary address for EcExtraIoBase
+  The reference code will use this as Temporary address space
+**/
+  UINT16                      EcExtraIoBase;
+
+/** Offset 0x09EA - Temporary address for SioBaseAddress
+  The reference code will use this as Temporary address space
+**/
+  UINT16                      SioBaseAddress;
+
+/** Offset 0x09EC - Temporary CfgBar address for VMD
+  The reference code will use this as Temporary address space
+**/
+  UINT32                      VmdCfgBarBar;
+
+/** Offset 0x09F0 - System Agent SafBar
+  Address of System Agent SafBar
+**/
+  UINT64                      SafBar;
 
 /** Offset 0x09F8 - Enable above 4GB MMIO resource support
   Enable/disable above 4GB MMIO resource support
@@ -2582,7 +3813,20 @@ typedef struct {
 
 /** Offset 0x09FA - Reserved
 **/
-  UINT8                       Reserved76[10];
+  UINT8                       Reserved37[2];
+
+/** Offset 0x09FC - StreamTracer Mode
+  Disable: Disable StreamTracer, Advanced Tracing: StreamTracer size 512MB - Recommended
+  when all groups in high verbosity are traced in 'red', Auto: StreamTracer size
+  8MB - Recommended when using up to 8 groups red or up to 16 groups in green in
+  med verbosity, User input: Allow User to enter a size in the range of 64KB-512MB
+  0: Disable (Default), 524288: Advanced Tracing , 8192: Auto , 3: User input
+**/
+  UINT32                      StreamTracerMode;
+
+/** Offset 0x0A00
+**/
+  UINT32                      StreamTracerSize;
 
 /** Offset 0x0A04 - Enable/Disable CrashLog Device
   Enable or Disable CrashLog/Telemetry Device  0- Disable, <b>1- Enable</b>
@@ -2590,9 +3834,39 @@ typedef struct {
 **/
   UINT32                      CpuCrashLogDevice;
 
-/** Offset 0x0A08 - Reserved
+/** Offset 0x0A08 - StreamTracer physical address
+  StreamTracer physical address
 **/
-  UINT8                      Reserved77[20];
+  UINT64                      StreamTracerBase;
+
+/** Offset 0x0A10 - Temporary MemBar1 address for VMD
+  StreamTracer physical address
+**/
+  UINT32                      VmdMemBar1Bar;
+
+/** Offset 0x0A14 - Temporary MemBar2 address for VMD
+  StreamTracer physical address
+**/
+  UINT32                      VmdMemBar2Bar;
+
+/** Offset 0x0A18 - Skip override boot mode When Fw Update.
+  When set to TRUE and boot mode is BOOT_ON_FLASH_UPDATE, skip setting boot mode to
+  BOOT_WITH_FULL_CONFIGURATION in PEI memory init.
+  $EN_DIS
+**/
+  UINT8                       SiSkipOverrideBootModeWhenFwUpdate;
+
+/** Offset 0x0A19 - Reserved
+**/
+  UINT8                       Reserved38;
+
+/** Offset 0x0A1A - Static Content at 4GB Location
+  0 (Default): No Allocation, 0x20:32MB, 0x40:64MB, 0x80:128MB, 0x100:256MB, 0x200:512MB,
+  0x400:1GB, 0x800:2GB, 0xC00:3GB, 0x1000:4GB, 0x2000:8GB
+  0: No Allocation, 0x20:32MB, 0x40:64MB, 0x80:128MB, 0x100:256MB, 0x200:512MB, 0x400:1GB,
+  0x800:2GB, 0xC00:3GB, 0x1000:4GB, 0x2000:8GB
+**/
+  UINT16                      StaticContentSizeAt4Gb;
 
 /** Offset 0x0A1C - Platform Debug Option
   Enabled Trace active: TraceHub is enabled and trace is active, blocks s0ix.\n
@@ -2607,9 +3881,14 @@ typedef struct {
 **/
   UINT8                       PlatformDebugOption;
 
-/** Offset 0x0A1D - Reserved
+/** Offset 0x0A1D - TXT CMOS Offset
+  CMOS Offset for TXT policy data. Default 0x2A
 **/
-  UINT8                       Reserved78[14];
+  UINT8                       CmosTxtOffset;
+
+/** Offset 0x0A1E - Reserved
+**/
+  UINT8                       Reserved39[13];
 
 /** Offset 0x0A2B - Program GPIOs for LFP on DDI port-A device
   0=Disabled,1(Default)=eDP, 2=MIPI DSI
@@ -2617,9 +3896,10 @@ typedef struct {
 **/
   UINT8                       DdiPortAConfig;
 
-/** Offset 0x0A2C - Reserved
+/** Offset 0x0A2C - HgSubSystemId
+  Hybrid Graphics SubSystemId
 **/
-  UINT8                      Reserved79[2];
+  UINT16                      HgSubSystemId;
 
 /** Offset 0x0A2E - Program GPIOs for LFP on DDI port-B device
   0(Default)=Disabled,1=eDP, 2=MIPI DSI
@@ -2711,9 +3991,15 @@ typedef struct {
 **/
   UINT8                       DdiPort4Ddc;
 
-/** Offset 0x0A3D - Reserved
+/** Offset 0x0A3D - Oem T12 Dealy Override
+  Oem T12 Dealy Override. 0(Default)=Disable  1=Enable
+  $EN_DIS
 **/
-  UINT8                       Reserved80[3];
+  UINT8                       OemT12DelayOverride;
+
+/** Offset 0x0A3E - Reserved
+**/
+  UINT8                       Reserved40[2];
 
 /** Offset 0x0A40 - Temporary MMIO address for GMADR
   The reference code will use this as Temporary MMIO address space to access GMADR
@@ -2730,9 +4016,12 @@ typedef struct {
 **/
   UINT64                      GttMmAdr;
 
-/** Offset 0x0A50 - Reserved
+/** Offset 0x0A50 - Delta T12 Power Cycle Delay required in ms
+  Select the value for delay required. 0= No delay, 0xFFFF(Default) = Auto calculate
+  T12 Delay to max 500ms
+  0 : No Delay, 0xFFFF : Auto Calulate T12 Delay
 **/
-  UINT8                      Reserved81[2];
+  UINT16                      DeltaT12PowerCycleDelay;
 
 /** Offset 0x0A52 - Enable/Disable Memory Bandwidth Compression
   0=Disable, 1(Default)=Enable
@@ -2762,7 +4051,7 @@ typedef struct {
 
 /** Offset 0x0A56 - Reserved
 **/
-  UINT8                       Reserved82[2];
+  UINT8                       Reserved41[2];
 
 /** Offset 0x0A58 - Intel Graphics VBT (Video BIOS Table) Size
   Size of Internal Graphics VBT Image
@@ -2771,7 +4060,7 @@ typedef struct {
 
 /** Offset 0x0A5C - Reserved
 **/
-  UINT8                       Reserved83[4];
+  UINT8                       Reserved42[4];
 
 /** Offset 0x0A60 - Graphics Configuration Ptr
   Points to VBT
@@ -2831,9 +4120,11 @@ typedef struct {
 **/
   UINT8                       TcssXhciEn;
 
-/** Offset 0x0A83 - Reserved
+/** Offset 0x0A83 - IomUsbCDpConfig
+  Set IomUsbCDpConfig expect 4 values from 0 to 3
+  0:Disabled, 1:IOM_DP, 2:IOM_HDMI, 3: IOM_EDP
 **/
-  UINT8                       Reserved84[4];
+  UINT8                       IomUsbCDpConfig[4];
 
 /** Offset 0x0A87 - TCSS Type C Port 0
   Set TCSS Type C Port 0 Type, Options are 0=DISABLE, 1=DP_ONLY, 2=NO_TBT, 3=NO_PCIE,
@@ -2863,9 +4154,11 @@ typedef struct {
 **/
   UINT8                       TcssPort3;
 
-/** Offset 0x0A8B - Reserved
+/** Offset 0x0A8B - TCSS Platform Configuration
+  Set TCSS Platform Configuration - Retimer Map, TCP0 - Bits[1:0], TCP1 - Bits[3:2],
+  TCP2 - Bits[5:4], TCP3 - Bits[7:6]; 0=Retimerless, 1=Retimer
 **/
-  UINT8                       Reserved85;
+  UINT8                       TcssPlatConf;
 
 /** Offset 0x0A8C - TypeC port GPIO setting
   GPIO Pin number for Type C Aux orientation setting, use the GpioPad that is defined
@@ -2931,9 +4224,11 @@ typedef struct {
 **/
   UINT8                       InternalGraphics;
 
-/** Offset 0x0AC9 - Reserved
+/** Offset 0x0AC9 - Asynchronous ODT
+  This option configures the Memory Controler Asynchronous ODT control
+  0:Enabled, 1:Disabled
 **/
-  UINT8                       Reserved86;
+  UINT8                       AsyncOdtDis;
 
 /** Offset 0x0ACA - DLL Weak Lock Support
   Enables/Disable DLL Weak Lock Support
@@ -2943,7 +4238,7 @@ typedef struct {
 
 /** Offset 0x0ACB - Reserved
 **/
-  UINT8                       Reserved87;
+  UINT8                       Reserved43;
 
 /** Offset 0x0ACC - Rx DQS Delay Comp Support
   Enables/Disable Rx DQS Delay Comp Support
@@ -2953,7 +4248,7 @@ typedef struct {
 
 /** Offset 0x0ACD - Reserved
 **/
-  UINT8                       Reserved88[2];
+  UINT8                       Reserved44[2];
 
 /** Offset 0x0ACF - Mrc Failure On Unsupported Dimm
   Enables/Disable Mrc Failure On Unsupported Dimm
@@ -2961,9 +4256,11 @@ typedef struct {
 **/
   UINT8                       MrcFailureOnUnsupportedDimm;
 
-/** Offset 0x0AD0 - Reserved
+/** Offset 0x0AD0 - Fore Single Rank config
+  Enables/Disable Fore Single Rank config
+  $EN_DIS
 **/
-  UINT8                      Reserved89[4];
+  UINT32                      ForceSingleRank;
 
 /** Offset 0x0AD4 - DynamicMemoryBoost
   Enable/Disable Dynamic Memory Boost Feature. Only valid if SpdProfileSelected is
@@ -2979,9 +4276,55 @@ typedef struct {
 **/
   UINT32                      RealtimeMemoryFrequency;
 
-/** Offset 0x0ADC - Reserved
+/** Offset 0x0ADC - SelfRefresh IdleTimer
+  SelfRefresh IdleTimer, Default is 256
 **/
-  UINT8                      Reserved90[9];
+  UINT16                      SrefCfgIdleTmr;
+
+/** Offset 0x0ADE - MC Register Offset
+  Apply user offsets to select MC registers(Def=Disable)
+  $EN_DIS
+**/
+  UINT8                       MCREGOFFSET;
+
+/** Offset 0x0ADF - CA Vref Ctl Offset
+  Offset to be applied to DDRDATA7CH1_CR_DDRCRVREFADJUST1.CAVref
+  0xF4:-12,0xF5:-11, 0xF6:-10, 0xF7:-9, 0xF8:-8, 0xF9:-7, 0xFA:-6, 0xFB:-5, 0xFC:-4,
+  0xFD:-3, 0xFE:-2, 0xFF:-1, 0:0, 1:+1, 2:+2, 3:+3, 4:+4, 5:+5, 6:+6, 7:+7, 8:+8,
+  9:+9, 10:+10, 11:+11, 12:+12
+**/
+  UINT8                       CAVrefCtlOffset;
+
+/** Offset 0x0AE0 - Clk PI Code Offset
+  Offset to be applied to DDRCLKCH0_CR_DDRCRCLKPICODE.PiSettingRank[0-3]
+  0xFA:-6, 0xFB:-5, 0xFC:-4, 0xFD:-3, 0xFE:-2, 0xFF:-1, 0:0, 1:+1, 2:+2, 3:+3, 4:+4,
+  5:+5, 6:+6
+**/
+  UINT8                       ClkPiCodeOffset;
+
+/** Offset 0x0AE1 - RcvEn Offset
+  Offset to be applied to DDRDATACH0_CR_DDRCRDATAOFFSETTRAIN.RcvEn
+  0xFD:-3, 0xFE:-2, 0xFF:-1, 0:0, 1:+1, 2:+2, 3:+3
+**/
+  UINT8                       RcvEnOffset;
+
+/** Offset 0x0AE2 - Rx Dqs Offset
+  Offset to be applied to DDRDATACHX_CR_DDRCRDATAOFFSETTRAIN.RxDqsOffset
+  0xFD:-3, 0xFE:-2, 0xFF:-1, 0:0, 1:+1, 2:+2, 3:+3
+**/
+  UINT8                       RxDqsOffset;
+
+/** Offset 0x0AE3 - Tx Dq Offset
+  Offset to be applied to DDRDATACH0_CR_DDRCRDATAOFFSETTRAIN.TxDqOffset
+  0xFD:-3, 0xFE:-2, 0xFF:-1, 0:0, 1:+1, 2:+2, 3:+3
+**/
+  UINT8                       TxDqOffset;
+
+/** Offset 0x0AE4 - Tx Dqs Offset
+  Offset to be applied to DDRDATACH0_CR_DDRCRDATAOFFSETTRAIN.TxDqsOffset
+  0xFD:-3, 0xFE:-2, 0xFF:-1, 0:0, 1:+1, 2:+2, 3:+3
+**/
+  UINT8                       TxDqsOffset;
 
 /** Offset 0x0AE5 - Vref Offset
   Offset to be applied to DDRDATACH0_CR_DDRCRDATAOFFSETTRAIN.VrefOffset
@@ -2990,9 +4333,15 @@ typedef struct {
 **/
   UINT8                       VrefOffset;
 
-/** Offset 0x0AE6 - Reserved
+/** Offset 0x0AE6 - Controller mask
+  Controller mask to apply on parameter offset
 **/
-  UINT8                       Reserved91[2];
+  UINT8                       CntrlrMask;
+
+/** Offset 0x0AE7 - Channel  mask
+  Channel  mask to apply on parameter offset
+**/
+  UINT8                       ChMask;
 
 /** Offset 0x0AE8 - tRRSG Delta
   Delay between Read-to-Read commands in the same Bank Group. 0 - Auto. Signed TAT
@@ -3106,9 +4455,158 @@ typedef struct {
 **/
   UINT8                       tRWDD;
 
-/** Offset 0x0AF8 - Reserved
+/** Offset 0x0AF8 - MRC Interpreter
+  Select CMOS location match of DD01 or Ctrl-Break key or force entry
+  0:CMOS, 1:Break, 2:Force
 **/
-  UINT8                       Reserved92[41];
+  UINT8                       Interpreter;
+
+/** Offset 0x0AF9 - ODT mode
+  ODT mode
+  0:Default, 1:Vtt, 2:Vddq, 3:Vss, 4:Max
+**/
+  UINT8                       IoOdtMode;
+
+/** Offset 0x0AFA - PerBankRefresh
+  Control of Per Bank Refresh feature for LPDDR DRAMs
+  $EN_DIS
+**/
+  UINT8                       PerBankRefresh;
+
+/** Offset 0x0AFB - Mimic WC display pattern in IPQ
+  Using for Disable/Enable Mimic WC display pattern in IPQ: 0:Disable, 1:Enable 1
+  ACT resources usage, 3:Enable 2 ACT resources usage, 3:Enable 3 ACT resources usage,0xf:
+  Enable 4 ACT resources usage
+  1:1, 3:3, 0xf:0xf, 0:Auto
+**/
+  UINT8                       MimicWcDisaplayInIpq;
+
+/** Offset 0x0AFC - Fake SAGV
+  Fake SAGV: 0:Disabled, 1:Enabled
+  $EN_DIS
+**/
+  UINT32                      FakeSagv;
+
+/** Offset 0x0B00 - Lock DPR register
+  Lock DPR register. <b>0: Platform POR </b>; 1: Enable; 2: Disable
+  0:Platform POR, 1: Enable, 2: Disable
+**/
+  UINT32                      DprLock;
+
+/** Offset 0x0B04 - Board Stack Up
+  Board Stack Up: <b>0=Typical</b>, 1=Freq Limited
+  0:Typical, 1:Freq Limited
+**/
+  UINT8                       BoardStackUp;
+
+/** Offset 0x0B05 - PPR ForceRepair
+  When Eanble, PPR will force repair some rows many times (90)
+  $EN_DIS
+**/
+  UINT8                       PprForceRepair;
+
+/** Offset 0x0B06 - PPR Repair Bank
+  Deprecated
+**/
+  UINT8                       PprRepairBank;
+
+/** Offset 0x0B07 - Board Topology
+  Board Topology: <b>0=Daisy Chain</b>, 1=Tee.
+  0:Daisy Chain, 1:Tee
+**/
+  UINT8                       BoardTopology;
+
+/** Offset 0x0B08 - SubCh Hash Interleaved Bit
+  Select the MC Enhanced Channel interleave bit, to set different address bit for
+  sub channel selection than bit-6
+  0:BIT6, 1:BIT7, 2:BIT8, 3:BIT9, 4:BIT10, 5:BIT11, 6:BIT12, 7:BIT13
+**/
+  UINT8                       SubChHashInterleaveBit;
+
+/** Offset 0x0B09 - Reserved
+**/
+  UINT8                       Reserved45;
+
+/** Offset 0x0B0A - SubCh Hash Mask
+  Set the BIT(s) to be included in the XOR function. NOTE BIT mask corresponds to
+  BITS [19:6] Default is 0x834
+**/
+  UINT16                      SubChHashMask;
+
+/** Offset 0x0B0C - Force CKD in Bypass Mode
+  Enable/Disable Force CKD in Bypass Mode
+  $EN_DIS
+**/
+  UINT8                       ForceCkdBypass;
+
+/** Offset 0x0B0D - Reserved
+**/
+  UINT8                       Reserved46[3];
+
+/** Offset 0x0B10 - Disable Zq
+  Enable/Disable Zq Calibration: 0:Enabled, 1:Disabled
+  $EN_DIS
+**/
+  UINT32                      DisableZq;
+
+/** Offset 0x0B14 - Replicate SAGV
+  Replicate SAGV: 0:Disabled, 1:Enabled
+  $EN_DIS
+**/
+  UINT32                      ReplicateSagv;
+
+/** Offset 0x0B18 - Adjust wck mode
+  Adjust wck mode: 0:safe mode, 1:manual mode, 2:dynamic mode, 3:Default
+  0:safe mode, 1:manual mode, 2:dynamic mode, 3:Default
+**/
+  UINT8                       AdjustWckMode;
+
+/** Offset 0x0B19 - Control MC/PMA telemetry
+  Control MC/PMA telemetry: 0: Default, 1: Enable, 2: Disable
+  0: Default, 1: Enable, 2: Disable
+**/
+  UINT8                       TelemetryControl;
+
+/** Offset 0x0B1A - PHclk\Qclk SPINE gating Control
+  PHclk\Qclk SPINE gating Control: 0:Disabled, 1:Enabled
+  $EN_DIS
+**/
+  UINT8                       SpineAndPhclkGateControl;
+
+/** Offset 0x0B1B - SpineGating per lpmode
+  SpineGatePerLpmode[0]:Lpmode0.5, SpineGatePerLpmode[1]:Lpmode2, SpineGatePerLpmode[2]:Lpmode3,
+  SpineGatePerLpmode[3]:Lpmode4
+**/
+  UINT8                       SpineGatePerLpmode;
+
+/** Offset 0x0B1C - PhClkGating control per lpmode
+  PhclkGatePerLpmode[0]:Lpmode0.5, PhclkGatePerLpmode[1]:Lpmode1, PhclkGatePerLpmode[2]:Lpmode2,
+  PhclkGatePerLpmode[3]:Lpmode3, PhclkGatePerLpmode[4]:Lpmode4
+**/
+  UINT8                       PhclkGatePerLpmode;
+
+/** Offset 0x0B1D - DFI Control after cold boot
+  Disable Switch DFI Control to MC after cold boot: 0(Default)=switch DFI to MC, 1=Keep
+  with PHY/MPTU
+  $EN_DIS
+**/
+  UINT8                       DisableSwitchDfiToMc;
+
+/** Offset 0x0B1E - Enable/Disable SmbusPostcode
+  Disable (Default): Postcode via Port80, Enable: Postcode via Smbus
+  $EN_DIS
+**/
+  UINT8                       SmbusPostCodeEnable;
+
+/** Offset 0x0B1F - SmbusPostcode Address
+  Slave address for Smbus postcode device
+**/
+  UINT8                       SmbusPostCodeAddress;
+
+/** Offset 0x0B20 - SmbusPostcode Command
+  Command value for Smbus postcode device
+**/
+  UINT8                       SmbusPostCodeCommand;
 
 /** Offset 0x0B21 - Channel to CKD QCK Mapping
   Specify Channel to CKD QCK Mapping for CH0D0/CH0D1/CH1D0&CH1D1
@@ -3120,9 +4618,16 @@ typedef struct {
 **/
   UINT8                       PhyClockToCkdDimm[8];
 
-/** Offset 0x0B31 - Reserved
+/** Offset 0x0B31 - CKD Address Table
+  Specify CKD Address table for all DIMMs
 **/
-  UINT8                       Reserved93[17];
+  UINT8                       CkdAddressTable[16];
+
+/** Offset 0x0B41 - Single VDD2 Rail
+  LP5x VDD2 rail: 0: Dual rail (E-DVFSC is possible), 1: Single rail(No E-DVFSC; VDD2L == VDD2H)
+  $EN_DIS
+**/
+  UINT8                       SingleVdd2Rail;
 
 /** Offset 0x0B42 - VDD2 Voltage
   Voltage is multiple of 5mV where 0 means Auto.
@@ -3146,7 +4651,7 @@ typedef struct {
 
 /** Offset 0x0B4A - Reserved
 **/
-  UINT8                       Reserved94[30];
+  UINT8                       Reserved47[30];
 } FSP_M_CONFIG;
 
 /** Fsp M UPD Configuration
diff --git a/src/vendorcode/intel/fsp/fsp2_0/pantherlake/FspsUpd.h b/src/vendorcode/intel/fsp/fsp2_0/pantherlake/FspsUpd.h
index ae0ffe29dd..be67c19c80 100644
--- a/src/vendorcode/intel/fsp/fsp2_0/pantherlake/FspsUpd.h
+++ b/src/vendorcode/intel/fsp/fsp2_0/pantherlake/FspsUpd.h
@@ -104,9 +104,24 @@ typedef struct {
 **/
   UINT64                      BiosGuardModulePtr;
 
-/** Offset 0x0080 - Reserved
+/** Offset 0x0080 - EcProvisionEav
+  EcProvisionEav function pointer. \n
+  @code typedef EFI_STATUS (EFIAPI *EC_PROVISION_EAV) (IN UINT32 Eav, OUT UINT8
+  *ReturnValue); @endcode
 **/
-  UINT8                      Reserved1[17];
+  UINT64                      EcProvisionEav;
+
+/** Offset 0x0088 - EcBiosGuardCmdLock
+  EcBiosGuardCmdLock function pointer. \n
+  @code typedef EFI_STATUS (EFIAPI *EC_CMD_LOCK) (OUT UINT8 *ReturnValue); @endcode
+**/
+  UINT64                      EcBiosGuardCmdLock;
+
+/** Offset 0x0090 - PCH eSPI Host and Device BME enabled
+  PCH eSPI Host and Device BME enabled
+  $EN_DIS
+**/
+  UINT8                       PchEspiBmeHostDeviceEnabled;
 
 /** Offset 0x0091 - PCH eSPI Link Configuration Lock (SBLCL)
   Enable/Disable lock of communication through SET_CONFIG/GET_CONFIG to eSPI target
@@ -127,9 +142,27 @@ typedef struct {
 **/
   UINT8                       PchEspiLgmrEnable;
 
-/** Offset 0x0094 - Reserved
+/** Offset 0x0094 - PCH eSPI PmHAE
+  This option enables or disables espi lgmr
+  $EN_DIS
 **/
-  UINT8                       Reserved2[4];
+  UINT8                       PchEspiPmHAE;
+
+/** Offset 0x0095 - PCH eSPI HideNonFatalErrors
+  This option enables or disables espi lgmr
+  $EN_DIS
+**/
+  UINT8                       PchEspiHideNonFatalErrors;
+
+/** Offset 0x0096 - PCH eSPI NmiEnableCs1
+  Set this bit to enable eSPI NMI VW events to be processed by the SOC
+  $EN_DIS
+**/
+  UINT8                       PchEspiNmiEnableCs1;
+
+/** Offset 0x0097 - Reserved
+**/
+  UINT8                       Reserved1;
 
 /** Offset 0x0098 - CpuBistData
   Pointer CPU BIST Data
@@ -151,7 +184,16 @@ typedef struct {
 
 /** Offset 0x00A9 - Reserved
 **/
-  UINT8                       Reserved3[7];
+  UINT8                       Reserved2[3];
+
+/** Offset 0x00AC - StreamTracer Mode
+  Disable: Disable StreamTracer, Advanced Tracing: StreamTracer size 512MB - Recommended
+  when all groups in high verbosity are traced in 'red', Auto: StreamTracer size
+  8MB - Recommended when using up to 8 groups red or up to 16 groups in green in
+  med verbosity, User input: Allow User to enter a size in the range of 64KB-512MB
+  0: Disable (Default), 524288: Advanced Tracing , 8192: Auto , 3: User input
+**/
+  UINT32                      StreamTracerMode;
 
 /** Offset 0x00B0 - MicrocodeRegionBase
   Memory Base of Microcode Updates
@@ -192,9 +234,12 @@ typedef struct {
 **/
   UINT8                       AvxDisable;
 
-/** Offset 0x00C4 - Reserved
+/** Offset 0x00C4 - X2ApicEnable
+  Enable/Disable X2APIC Operating Mode. When this option is configured as 'Enabled',
+  'VT-d' option must be 'Enabled'.
+  $EN_DIS
 **/
-  UINT8                       Reserved4;
+  UINT8                       X2ApicEnable;
 
 /** Offset 0x00C5 - P-state ratios for max 16 version of custom P-state table
   P-state ratios for max 16 version of custom P-state table. This table is used for
@@ -287,9 +332,17 @@ typedef struct {
 **/
   UINT8                       PkgCStateLimit;
 
-/** Offset 0x00E1 - Reserved
+/** Offset 0x00E1 - ForcePr Demotion Algorithm configuration
+  ForcePr Demotion Algorithm configuration. 0: Disable;<b> 1: Enable</b>
+  0: Disable, 1: Enable
 **/
-  UINT8                       Reserved5[2];
+  UINT8                       ForcePrDemotion;
+
+/** Offset 0x00E2 - VrAlert Demotion Algorithm configuration
+  VrAlert Demotion Algorithm configuration. 0: Disable;<b> 1: Enable</b>
+  0: Disable, 1: Enable
+**/
+  UINT8                       VrAlertDemotion;
 
 /** Offset 0x00E3 - Interrupt Redirection Mode Select
   Interrupt Redirection Mode Select for Logical Interrupts. 0: Fixed priority; 1:
@@ -303,9 +356,12 @@ typedef struct {
 **/
   UINT8                       TurboMode;
 
-/** Offset 0x00E5 - Reserved
+/** Offset 0x00E5 - Power Floor PCIe Gen Downgrade
+  SoC can downgrade PCIe gen speed to lower SoC floor power (Default enabled).  0:
+  Disable: Reduction in PCIe gen speed will not be used by SoC., <b>1: Enable </b>
+  $EN_DIS
 **/
-  UINT8                       Reserved6;
+  UINT8                       PowerFloorPcieGenDowngrade;
 
 /** Offset 0x00E6 - P-state ratios for custom P-state table
   P-state ratios for custom P-state table. NumberOfEntries has valid range between
@@ -325,9 +381,12 @@ typedef struct {
 **/
   UINT8                       MaxRatio;
 
-/** Offset 0x0110 - Reserved
+/** Offset 0x0110 - Boot frequency
+  Select the performance state that the BIOS will set starting from reset vector.
+  0: Maximum battery performance. 1: Maximum non-turbo performance. <b>2: Turbo performance </b>
+  0:0, 1:1, 2:2
 **/
-  UINT8                       Reserved7;
+  UINT8                       BootFrequency;
 
 /** Offset 0x0111 - Turbo settings Lock
   Enable/Disable locking of Package Power Limit settings. When enabled, PACKAGE_POWER_LIMIT
@@ -337,9 +396,41 @@ typedef struct {
 **/
   UINT8                       TurboPowerLimitLock;
 
-/** Offset 0x0112 - Reserved
+/** Offset 0x0112 - FastMsrHwpReq
+  0: Disable; <b> 1: Enable;</b>
+  $EN_DIS
 **/
-  UINT8                       Reserved8[33];
+  UINT8                       EnableFastMsrHwpReq;
+
+/** Offset 0x0113 - Turbo Ratio Limit Ratio array
+  Performance-core Turbo Ratio Limit Ratio0-7 (TRLR) defines the turbo ratio (max
+  is 85 in normal mode and 120 in core extension mode). Ratio[0]: This Turbo Ratio
+  Limit Ratio0 must be greater than or equal all other ratio values. If this value
+  is invalid, thn set all other active cores to minimum. Otherwise, align the Ratio
+  Limit to 0. Please check each active cores. Ratio[1~7]: This Turbo Ratio Limit
+  Ratio1 must be <= to Turbo Ratio Limit Ratio0~6.
+**/
+  UINT8                       TurboRatioLimitRatio[8];
+
+/** Offset 0x011B - Turbo Ratio Limit Num Core array
+  Performance-core Turbo Ratio Limit Core0~7 defines the core range, the turbo ratio
+  is defined in Turbo Ratio Limit Ratio0~7. If value is zero, this entry is ignored.
+**/
+  UINT8                       TurboRatioLimitNumCore[8];
+
+/** Offset 0x0123 - ATOM Turbo Ratio Limit Ratio array
+  Efficient-core Turbo Ratio Limit Ratio0-7 defines the turbo ratio (max is 85 irrespective
+  of the core extension mode), the core range is defined in E-core Turbo Ratio Limit
+  CoreCount0-7.
+**/
+  UINT8                       AtomTurboRatioLimitRatio[8];
+
+/** Offset 0x012B - ATOM Turbo Ratio Limit Num Core array
+  Efficient-core Turbo Ratio Limit CoreCount0-7 defines the core range, the turbo
+  ratio is defined in E-core Turbo Ratio Limit Ratio0-7. If value is zero, this entry
+  is ignored.
+**/
+  UINT8                       AtomTurboRatioLimitNumCore[8];
 
 /** Offset 0x0133 - Race To Halt
   Enable/Disable Race To Halt feature. RTH will dynamically increase CPU frequency
@@ -373,9 +464,11 @@ typedef struct {
 **/
   UINT8                       MaxRingRatioLimit;
 
-/** Offset 0x0138 - Reserved
+/** Offset 0x0138 - Resource Priority Feature
+  Enable/Disable Resource Priority Feature. Enable/Disable; 0: Disable, <b>1: Enable </b>
+  $EN_DIS
 **/
-  UINT8                       Reserved9;
+  UINT8                       EnableRp;
 
 /** Offset 0x0139 - Enable or Disable HWP
   Enable/Disable Intel(R) Speed Shift Technology support. Enabling will expose the
@@ -406,9 +499,42 @@ typedef struct {
 **/
   UINT8                       EnableHwpAutoEppGrouping;
 
-/** Offset 0x013D - Reserved
+/** Offset 0x013D - Dynamic Efficiency Control
+  Enable or Disable SoC to control energy efficiency targets autonomously, regardless
+  of EPP, EPB and other SW inputs. 0: Disable; </b>1: Enable <b>
+  $EN_DIS
 **/
-  UINT8                       Reserved10[5];
+  UINT8                       EnableDynamicEfficiencyControl;
+
+/** Offset 0x013E - Misc Power Management MSR Lock
+  Enable/Disable HWP Lock support in Misc Power Management MSR. 0: Disable, <b>1:
+  Enable </b>
+  $EN_DIS
+**/
+  UINT8                       HwpLock;
+
+/** Offset 0x013F - Power Floor Managment for SOC
+  Option to disable Power Floor Managment for SOC. Disabling this might effectively
+  raise power floor of the SoC and may lead to stability issues. 0: Disable, <b>1:
+  Enable </b>
+  $EN_DIS
+**/
+  UINT8                       PowerFloorManagement;
+
+/** Offset 0x0140 - Power Floor Disaplay Disconnect
+  SoC can disconnect secondary/external display to lower SoC floor power (Default
+  disabled).  0: Disable: Display disconnect will not be used by SoC., </b>1: Enable <b>
+  $EN_DIS
+**/
+  UINT8                       PowerFloorDisplayDisconnect;
+
+/** Offset 0x0141 - Memory size per thread allocated for Processor Trace
+  Memory size per thread for Processor Trace. Processor Trace requires 2^N alignment
+  and size in bytes per thread, from 4KB to 128MB.\n
+  <b> 0xff:none </b>, 0:4k, 0x1:8k, 0x2:16k, 0x3:32k, 0x4:64k, 0x5:128k, 0x6:256k,
+  0x7:512k, 0x8:1M, 0x9:2M, 0xa:4M. 0xb:8M, 0xc:16M, 0xd:32M, 0xe:64M, 0xf:128M
+**/
+  UINT8                       ProcessorTraceMemSize;
 
 /** Offset 0x0142 - Enable or Disable MLC Streamer Prefetcher
   Enable or Disable MLC Streamer Prefetcher; 0: Disable; <b>1: Enable</b>.
@@ -447,9 +573,25 @@ typedef struct {
 **/
   UINT8                       ProcessorTraceEnable;
 
-/** Offset 0x0148 - Reserved
+/** Offset 0x0148 - Processor trace enabled for Bsp only or all cores
+  Processor trace enabled for Bsp only or all cores; <b>0: all cores</b>; 1: Bsp only.
+  0: all cores, 1: Bsp only
 **/
-  UINT8                       Reserved11[3];
+  UINT8                       ProcessorTraceBspOnly;
+
+/** Offset 0x0149 - Enable/Disable processor trace Timing Packet
+  Enable/Disable collocting processor trace performance (CYC, TSC); <b>0: Disable</b>;
+  1: Enable.
+  $EN_DIS
+**/
+  UINT8                       ProcessorTraceTimingPacket;
+
+/** Offset 0x014A - Enable or Disable Three Strike Counter
+  Enable (default): Three Strike counter will be incremented. Disable: Prevents Three
+  Strike counter from incrementing; 0: Disable; <b>1: Enable</b>
+  $EN_DIS
+**/
+  UINT8                       ThreeStrikeCounter;
 
 /** Offset 0x014B - UFS enable/disable
   Enable/Disable UFS controller, One byte for each Controller - (1,0) to enable controller
@@ -466,9 +608,12 @@ typedef struct {
 **/
   UINT8                       UfsInlineEncryption[2];
 
-/** Offset 0x014F - Reserved
+/** Offset 0x014F - UFS Connection Status
+  UFS Connection Status, One byte for each Controller - (1,0) to UFS connected to
+  controller 0 and (0,1) to UFS connected to controller 1
+  $EN_DIS
 **/
-  UINT8                       Reserved12[2];
+  UINT8                       UfsDeviceConnected[2];
 
 /** Offset 0x0151 - Enable/Disable PCIe tunneling for USB4
   Enable/Disable PCIe tunneling for USB4, default is enable
@@ -478,7 +623,7 @@ typedef struct {
 
 /** Offset 0x0152 - Reserved
 **/
-  UINT8                       Reserved13[2];
+  UINT8                       Reserved3[2];
 
 /** Offset 0x0154 - ITBTForcePowerOn Timeout value
   ITBTForcePowerOn value. Specified increment values in miliseconds. Range is 0-1000.
@@ -504,7 +649,12 @@ typedef struct {
 
 /** Offset 0x015D - Reserved
 **/
-  UINT8                       Reserved14[19];
+  UINT8                       Reserved4[11];
+
+/** Offset 0x0168 - FSPS Validation
+  Point to FSPS Validation configuration structure
+**/
+  UINT64                      FspsValidationPtr;
 
 /** Offset 0x0170 - IEH Mode
   Integrated Error Handler Mode, 0: Bypass, 1: Enable
@@ -563,7 +713,7 @@ typedef struct {
 
 /** Offset 0x017B - Reserved
 **/
-  UINT8                       Reserved15;
+  UINT8                       Reserved5;
 
 /** Offset 0x017C - ISH GP GPIO Pin Muxing
   Determines ISH GP GPIO Pin muxing. See GPIO_*_MUXING_ISH_GP_x_GPIO_*. 'x' are GP_NUMBER
@@ -746,9 +896,11 @@ typedef struct {
 **/
   UINT8                       PchIshPdtUnlock;
 
-/** Offset 0x025C - Reserved
+/** Offset 0x025C - PCH ISH MSI Interrupts
+  0: False; 1: True.
+  $EN_DIS
 **/
-  UINT8                       Reserved16;
+  UINT8                       PchIshMsiInterrupt;
 
 /** Offset 0x025D - End of Post message
   Test, Send End of Post message. Disable(0x0): Disable EOP message, Send in PEI(0x1):
@@ -778,9 +930,44 @@ typedef struct {
 **/
   UINT8                       MeUnconfigOnRtcClear;
 
-/** Offset 0x0261 - Reserved
+/** Offset 0x0261 - CSE Data Resilience Support
+  0: Disable CSE Data Resilience Support. <b>1: Enable CSE Data Resilience Support.</b>
+  2: Enable CSE Data Resilience but defer to DXE.
+  $EN_DIS
 **/
-  UINT8                       Reserved17[22];
+  UINT8                       CseDataResilience;
+
+/** Offset 0x0262 - PSE EOM Flow Control
+  0: Disable PSE EOM Flow. <b>1: Enable PSE EOM Flow.</b>
+  $EN_DIS
+**/
+  UINT8                       PseEomFlowEnable;
+
+/** Offset 0x0263 - ISH I3C SDA Pin Muxing
+  Select ISH I3C SDA Pin muxing. Refer to GPIO_*_MUXING_ISH_I3Cx_SDA_* for possible values.
+**/
+  UINT8                       IshI3cSdaPinMuxing[8];
+
+/** Offset 0x026B - ISH I3C SCL Pin Muxing
+  Select ISH I3C SCL Pin muxing. Refer to GPIO_*_MUXING_ISH_I3Cx_SCL_* for possible values.
+**/
+  UINT8                       IshI3cSclPinMuxing[8];
+
+/** Offset 0x0273 - ISH I3C SDA Pad termination
+  0x0: Hardware default, 0x1: None, 0x13: 1kOhm weak pull-up, 0x15: 5kOhm weak pull-up,
+  0x19: 20kOhm weak pull-up - Enable/disable SerialIo I2C#N Sda pads termination
+  respectively. #N-byte for each controller, byte0 for I2C0 Sda, byte1 for I2C1 Sda,
+  and so on.
+**/
+  UINT8                       IshI3cSdaPadTermination[2];
+
+/** Offset 0x0275 - ISH I3C SCL Pad termination
+  0x0: Hardware default, 0x1: None, 0x13: 1kOhm weak pull-up, 0x15: 5kOhm weak pull-up,
+  0x19: 20kOhm weak pull-up - Enable/disable SerialIo I2C#N Scl pads termination
+  respectively. #N-byte for each controller, byte0 for I2C0 Scl, byte1 for I2C1 Scl,
+  and so on.
+**/
+  UINT8                       IshI3cSclPadTermination[2];
 
 /** Offset 0x0277 - Enable PCH ISH I3C pins assigned
   Set if ISH I3C native pins are to be enabled by BIOS. 0: Disable; 1: Enable.
@@ -789,7 +976,7 @@ typedef struct {
 
 /** Offset 0x0279 - Reserved
 **/
-  UINT8                       Reserved18[3];
+  UINT8                       Reserved6[3];
 
 /** Offset 0x027C - Power button debounce configuration
   Debounce time for PWRBTN in microseconds. For values not supported by HW, they will
@@ -972,9 +1159,11 @@ typedef struct {
 **/
   UINT8                       PmcLpmS0ixSubStateEnableMask;
 
-/** Offset 0x029C - Reserved
+/** Offset 0x029C - PCH PMC ER Debug mode
+  Disable/Enable Energy Reporting Debug Mode.
+  $EN_DIS
 **/
-  UINT8                       Reserved19;
+  UINT8                       PchPmErDebugMode;
 
 /** Offset 0x029D - PMC C10 dynamic threshold dajustment enable
   Set if you want to enable PMC C10 dynamic threshold adjustment. Only works on supported SKUs
@@ -1143,9 +1332,11 @@ typedef struct {
 **/
   UINT8                       PcieRpAspm[28];
 
-/** Offset 0x053C - Reserved
+/** Offset 0x053C - HostL0sTxDis
+  Disable Host L0 transmission state
+  $EN_DIS
 **/
-  UINT8                       Reserved20[28];
+  UINT8                       HostL0sTxDis[28];
 
 /** Offset 0x0558 - PCIE RP L1 Substates
   The L1 Substates configuration of the root port (see: PCH_PCIE_L1SUBSTATES_CONTROL).
@@ -1169,9 +1360,677 @@ typedef struct {
 **/
   UINT8                       PcieEqOverrideDefault[12];
 
-/** Offset 0x05B8 - Reserved
+/** Offset 0x05B8 - PCIE RP choose EQ method
+  Choose PCIe EQ method
+  0: HardwareEq, 1: FixedEq
 **/
-  UINT8                       Reserved21[1525];
+  UINT8                       PcieGen3EqMethod[12];
+
+/** Offset 0x05C4 - PCIE RP choose EQ mode
+  Choose PCIe EQ mode
+  0: PresetEq, 1: CoefficientEq
+**/
+  UINT8                       PcieGen3EqMode[12];
+
+/** Offset 0x05D0 - PCIE RP EQ local transmitter override
+  Enable/Disable local transmitter override
+  $EN_DIS
+**/
+  UINT8                       PcieGen3EqLocalTxOverrideEn[12];
+
+/** Offset 0x05DC - PCI RP number of valid list entries
+  Select number of presets or coefficients depending on the mode
+**/
+  UINT8                       PcieGen3EqPh3NoOfPresetOrCoeff[12];
+
+/** Offset 0x05E8 - PCIE RP pre-cursor coefficient list
+  Provide a list of pre-cursor coefficients to be used during phase 3 EQ
+**/
+  UINT8                       PcieGen3EqPh3PreCursor0List[12];
+
+/** Offset 0x05F4 - PCIE RP post-cursor coefficient list
+  Provide a list of post-cursor coefficients to be used during phase 3 EQ
+**/
+  UINT8                       PcieGen3EqPh3PostCursor0List[12];
+
+/** Offset 0x0600 - PCIE RP pre-cursor coefficient list
+  Provide a list of pre-cursor coefficients to be used during phase 3 EQ
+**/
+  UINT8                       PcieGen3EqPh3PreCursor1List[12];
+
+/** Offset 0x060C - PCIE RP post-cursor coefficient list
+  Provide a list of post-cursor coefficients to be used during phase 3 EQ
+**/
+  UINT8                       PcieGen3EqPh3PostCursor1List[12];
+
+/** Offset 0x0618 - PCIE RP pre-cursor coefficient list
+  Provide a list of pre-cursor coefficients to be used during phase 3 EQ
+**/
+  UINT8                       PcieGen3EqPh3PreCursor2List[12];
+
+/** Offset 0x0624 - PCIE RP post-cursor coefficient list
+  Provide a list of post-cursor coefficients to be used during phase 3 EQ
+**/
+  UINT8                       PcieGen3EqPh3PostCursor2List[12];
+
+/** Offset 0x0630 - PCIR RP pre-cursor coefficient list
+  Provide a list of pre-cursor coefficients to be used during phase 3 EQ
+**/
+  UINT8                       PcieGen3EqPh3PreCursor3List[12];
+
+/** Offset 0x063C - PCIE RP post-cursor coefficient list
+  Provide a list of post-cursor coefficients to be used during phase 3 EQ
+**/
+  UINT8                       PcieGen3EqPh3PostCursor3List[12];
+
+/** Offset 0x0648 - PCIE RP pre-cursor coefficient list
+  Provide a list of pre-cursor coefficients to be used during phase 3 EQ
+**/
+  UINT8                       PcieGen3EqPh3PreCursor4List[12];
+
+/** Offset 0x0654 - PCIE RP post-cursor coefficient list
+  Provide a list of post-cursor coefficients to be used during phase 3 EQ
+**/
+  UINT8                       PcieGen3EqPh3PostCursor4List[12];
+
+/** Offset 0x0660 - PCIE RP pre-cursor coefficient list
+  Provide a list of pre-cursor coefficients to be used during phase 3 EQ
+**/
+  UINT8                       PcieGen3EqPh3PreCursor5List[12];
+
+/** Offset 0x066C - PCIE RP post-cursor coefficient list
+  Provide a list of post-cursor coefficients to be used during phase 3 EQ
+**/
+  UINT8                       PcieGen3EqPh3PostCursor5List[12];
+
+/** Offset 0x0678 - PCIE RP pre-cursor coefficient list
+  Provide a list of pre-cursor coefficients to be used during phase 3 EQ
+**/
+  UINT8                       PcieGen3EqPh3PreCursor6List[12];
+
+/** Offset 0x0684 - PCIe post-cursor coefficient list
+  Provide a list of post-cursor coefficients to be used during phase 3 EQ
+**/
+  UINT8                       PcieGen3EqPh3PostCursor6List[12];
+
+/** Offset 0x0690 - PCIE RP pre-cursor coefficient list
+  Provide a list of pre-cursor coefficients to be used during phase 3 EQ
+**/
+  UINT8                       PcieGen3EqPh3PreCursor7List[12];
+
+/** Offset 0x069C - PCIE RP post-cursor coefficient list
+  Provide a list of post-cursor coefficients to be used during phase 3 EQ
+**/
+  UINT8                       PcieGen3EqPh3PostCursor7List[12];
+
+/** Offset 0x06A8 - PCIE RP pre-cursor coefficient list
+  Provide a list of pre-cursor coefficients to be used during phase 3 EQ
+**/
+  UINT8                       PcieGen3EqPh3PreCursor8List[12];
+
+/** Offset 0x06B4 - PCIE RP post-cursor coefficient list
+  Provide a list of post-cursor coefficients to be used during phase 3 EQ
+**/
+  UINT8                       PcieGen3EqPh3PostCursor8List[12];
+
+/** Offset 0x06C0 - PCIE RP pre-cursor coefficient list
+  Provide a list of pre-cursor coefficients to be used during phase 3 EQ
+**/
+  UINT8                       PcieGen3EqPh3PreCursor9List[12];
+
+/** Offset 0x06CC - PCIE RP post-cursor coefficient list
+  Provide a list of post-cursor coefficients to be used during phase 3 EQ
+**/
+  UINT8                       PcieGen3EqPh3PostCursor9List[12];
+
+/** Offset 0x06D8 - PCIE RP preset list
+  Provide a list of presets to be used during phase 3 EQ
+**/
+  UINT8                       PcieGen3EqPh3Preset0List[12];
+
+/** Offset 0x06E4 - PCIe preset list
+  Provide a list of presets to be used during phase 3 EQ
+**/
+  UINT8                       PcieGen3EqPh3Preset1List[12];
+
+/** Offset 0x06F0 - PCIE RP preset list
+  Provide a list of presets to be used during phase 3 EQ
+**/
+  UINT8                       PcieGen3EqPh3Preset2List[12];
+
+/** Offset 0x06FC - PCIE RP preset list
+  Provide a list of presets to be used during phase 3 EQ
+**/
+  UINT8                       PcieGen3EqPh3Preset3List[12];
+
+/** Offset 0x0708 - PCIE RP preset list
+  Provide a list of presets to be used during phase 3 EQ
+**/
+  UINT8                       PcieGen3EqPh3Preset4List[12];
+
+/** Offset 0x0714 - PCIE RP preset list
+  Provide a list of presets to be used during phase 3 EQ
+**/
+  UINT8                       PcieGen3EqPh3Preset5List[12];
+
+/** Offset 0x0720 - PCIE RP preset list
+  Provide a list of presets to be used during phase 3 EQ
+**/
+  UINT8                       PcieGen3EqPh3Preset6List[12];
+
+/** Offset 0x072C - PCIE RP preset list
+  Provide a list of presets to be used during phase 3 EQ
+**/
+  UINT8                       PcieGen3EqPh3Preset7List[12];
+
+/** Offset 0x0738 - PCIE RP preset list
+  Provide a list of presets to be used during phase 3 EQ
+**/
+  UINT8                       PcieGen3EqPh3Preset8List[12];
+
+/** Offset 0x0744 - PCIE RP preset list
+  Provide a list of presets to be used during phase 3 EQ
+**/
+  UINT8                       PcieGen3EqPh3Preset9List[12];
+
+/** Offset 0x0750 - PCIE RP preset list
+  Provide a list of presets to be used during phase 3 EQ
+**/
+  UINT8                       PcieGen3EqPh3Preset10List[12];
+
+/** Offset 0x075C - PCIe EQ phase 1 downstream transmitter port preset
+  Allows to select the downstream port preset value that will be used during phase
+  1 of equalization
+**/
+  UINT8                       PcieGen3EqPh1DpTxPreset[12];
+
+/** Offset 0x0768 - PCIE RP EQ phase 1 upstream tranmitter port preset
+  Allows to select the upstream port preset value that will be used during phase 1
+  of equalization
+**/
+  UINT8                       PcieGen3EqPh1UpTxPreset[12];
+
+/** Offset 0x0774 - PCIE RP EQ phase 2 local transmitter override preset
+  Allows to select the value of the preset used during phase 2 local transmitter override
+**/
+  UINT8                       PcieGen3EqPh2LocalTxOverridePreset[12];
+
+/** Offset 0x0780 - PCIE RP choose EQ method
+  Choose PCIe EQ method
+  0: HardwareEq, 1: FixedEq
+**/
+  UINT8                       PcieGen4EqMethod[12];
+
+/** Offset 0x078C - PCIE RP choose EQ mode
+  Choose PCIe EQ mode
+  0: PresetEq, 1: CoefficientEq
+**/
+  UINT8                       PcieGen4EqMode[12];
+
+/** Offset 0x0798 - PCIE RP EQ local transmitter override
+  Enable/Disable local transmitter override
+  $EN_DIS
+**/
+  UINT8                       PcieGen4EqLocalTxOverrideEn[12];
+
+/** Offset 0x07A4 - PCI RP number of valid list entries
+  Select number of presets or coefficients depending on the mode
+**/
+  UINT8                       PcieGen4EqPh3NoOfPresetOrCoeff[12];
+
+/** Offset 0x07B0 - PCIE RP pre-cursor coefficient list
+  Provide a list of pre-cursor coefficients to be used during phase 3 EQ
+**/
+  UINT8                       PcieGen4EqPh3PreCursor0List[12];
+
+/** Offset 0x07BC - PCIE RP post-cursor coefficient list
+  Provide a list of post-cursor coefficients to be used during phase 3 EQ
+**/
+  UINT8                       PcieGen4EqPh3PostCursor0List[12];
+
+/** Offset 0x07C8 - PCIE RP pre-cursor coefficient list
+  Provide a list of pre-cursor coefficients to be used during phase 3 EQ
+**/
+  UINT8                       PcieGen4EqPh3PreCursor1List[12];
+
+/** Offset 0x07D4 - PCIE RP post-cursor coefficient list
+  Provide a list of post-cursor coefficients to be used during phase 3 EQ
+**/
+  UINT8                       PcieGen4EqPh3PostCursor1List[12];
+
+/** Offset 0x07E0 - PCIE RP pre-cursor coefficient list
+  Provide a list of pre-cursor coefficients to be used during phase 3 EQ
+**/
+  UINT8                       PcieGen4EqPh3PreCursor2List[12];
+
+/** Offset 0x07EC - PCIE RP post-cursor coefficient list
+  Provide a list of post-cursor coefficients to be used during phase 3 EQ
+**/
+  UINT8                       PcieGen4EqPh3PostCursor2List[12];
+
+/** Offset 0x07F8 - PCIR RP pre-cursor coefficient list
+  Provide a list of pre-cursor coefficients to be used during phase 3 EQ
+**/
+  UINT8                       PcieGen4EqPh3PreCursor3List[12];
+
+/** Offset 0x0804 - PCIE RP post-cursor coefficient list
+  Provide a list of post-cursor coefficients to be used during phase 3 EQ
+**/
+  UINT8                       PcieGen4EqPh3PostCursor3List[12];
+
+/** Offset 0x0810 - PCIE RP pre-cursor coefficient list
+  Provide a list of pre-cursor coefficients to be used during phase 3 EQ
+**/
+  UINT8                       PcieGen4EqPh3PreCursor4List[12];
+
+/** Offset 0x081C - PCIE RP post-cursor coefficient list
+  Provide a list of post-cursor coefficients to be used during phase 3 EQ
+**/
+  UINT8                       PcieGen4EqPh3PostCursor4List[12];
+
+/** Offset 0x0828 - PCIE RP pre-cursor coefficient list
+  Provide a list of pre-cursor coefficients to be used during phase 3 EQ
+**/
+  UINT8                       PcieGen4EqPh3PreCursor5List[12];
+
+/** Offset 0x0834 - PCIE RP post-cursor coefficient list
+  Provide a list of post-cursor coefficients to be used during phase 3 EQ
+**/
+  UINT8                       PcieGen4EqPh3PostCursor5List[12];
+
+/** Offset 0x0840 - PCIE RP pre-cursor coefficient list
+  Provide a list of pre-cursor coefficients to be used during phase 3 EQ
+**/
+  UINT8                       PcieGen4EqPh3PreCursor6List[12];
+
+/** Offset 0x084C - PCIe post-cursor coefficient list
+  Provide a list of post-cursor coefficients to be used during phase 3 EQ
+**/
+  UINT8                       PcieGen4EqPh3PostCursor6List[12];
+
+/** Offset 0x0858 - PCIE RP pre-cursor coefficient list
+  Provide a list of pre-cursor coefficients to be used during phase 3 EQ
+**/
+  UINT8                       PcieGen4EqPh3PreCursor7List[12];
+
+/** Offset 0x0864 - PCIE RP post-cursor coefficient list
+  Provide a list of post-cursor coefficients to be used during phase 3 EQ
+**/
+  UINT8                       PcieGen4EqPh3PostCursor7List[12];
+
+/** Offset 0x0870 - PCIE RP pre-cursor coefficient list
+  Provide a list of pre-cursor coefficients to be used during phase 3 EQ
+**/
+  UINT8                       PcieGen4EqPh3PreCursor8List[12];
+
+/** Offset 0x087C - PCIE RP post-cursor coefficient list
+  Provide a list of post-cursor coefficients to be used during phase 3 EQ
+**/
+  UINT8                       PcieGen4EqPh3PostCursor8List[12];
+
+/** Offset 0x0888 - PCIE RP pre-cursor coefficient list
+  Provide a list of pre-cursor coefficients to be used during phase 3 EQ
+**/
+  UINT8                       PcieGen4EqPh3PreCursor9List[12];
+
+/** Offset 0x0894 - PCIE RP post-cursor coefficient list
+  Provide a list of post-cursor coefficients to be used during phase 3 EQ
+**/
+  UINT8                       PcieGen4EqPh3PostCursor9List[12];
+
+/** Offset 0x08A0 - PCIE RP preset list
+  Provide a list of presets to be used during phase 3 EQ
+**/
+  UINT8                       PcieGen4EqPh3Preset0List[12];
+
+/** Offset 0x08AC - PCIe preset list
+  Provide a list of presets to be used during phase 3 EQ
+**/
+  UINT8                       PcieGen4EqPh3Preset1List[12];
+
+/** Offset 0x08B8 - PCIE RP preset list
+  Provide a list of presets to be used during phase 3 EQ
+**/
+  UINT8                       PcieGen4EqPh3Preset2List[12];
+
+/** Offset 0x08C4 - PCIE RP preset list
+  Provide a list of presets to be used during phase 3 EQ
+**/
+  UINT8                       PcieGen4EqPh3Preset3List[12];
+
+/** Offset 0x08D0 - PCIE RP preset list
+  Provide a list of presets to be used during phase 3 EQ
+**/
+  UINT8                       PcieGen4EqPh3Preset4List[12];
+
+/** Offset 0x08DC - PCIE RP preset list
+  Provide a list of presets to be used during phase 3 EQ
+**/
+  UINT8                       PcieGen4EqPh3Preset5List[12];
+
+/** Offset 0x08E8 - PCIE RP preset list
+  Provide a list of presets to be used during phase 3 EQ
+**/
+  UINT8                       PcieGen4EqPh3Preset6List[12];
+
+/** Offset 0x08F4 - PCIE RP preset list
+  Provide a list of presets to be used during phase 3 EQ
+**/
+  UINT8                       PcieGen4EqPh3Preset7List[12];
+
+/** Offset 0x0900 - PCIE RP preset list
+  Provide a list of presets to be used during phase 3 EQ
+**/
+  UINT8                       PcieGen4EqPh3Preset8List[12];
+
+/** Offset 0x090C - PCIE RP preset list
+  Provide a list of presets to be used during phase 3 EQ
+**/
+  UINT8                       PcieGen4EqPh3Preset9List[12];
+
+/** Offset 0x0918 - PCIE RP preset list
+  Provide a list of presets to be used during phase 3 EQ
+**/
+  UINT8                       PcieGen4EqPh3Preset10List[12];
+
+/** Offset 0x0924 - PCIe EQ phase 1 downstream transmitter port preset
+  Allows to select the downstream port preset value that will be used during phase
+  1 of equalization
+**/
+  UINT8                       PcieGen4EqPh1DpTxPreset[12];
+
+/** Offset 0x0930 - PCIE RP EQ phase 1 upstream tranmitter port preset
+  Allows to select the upstream port preset value that will be used during phase 1
+  of equalization
+**/
+  UINT8                       PcieGen4EqPh1UpTxPreset[12];
+
+/** Offset 0x093C - PCIE RP EQ phase 2 local transmitter override preset
+  Allows to select the value of the preset used during phase 2 local transmitter override
+**/
+  UINT8                       PcieGen4EqPh2LocalTxOverridePreset[12];
+
+/** Offset 0x0948 - PCIE RP choose EQ method
+  Choose PCIe EQ method
+  0: HardwareEq, 1: FixedEq
+**/
+  UINT8                       PcieGen5EqMethod[12];
+
+/** Offset 0x0954 - PCIE RP choose EQ mode
+  Choose PCIe EQ mode
+  0: PresetEq, 1: CoefficientEq
+**/
+  UINT8                       PcieGen5EqMode[12];
+
+/** Offset 0x0960 - PCIE RP EQ local transmitter override
+  Enable/Disable local transmitter override
+  $EN_DIS
+**/
+  UINT8                       PcieGen5EqLocalTxOverrideEn[12];
+
+/** Offset 0x096C - PCI RP number of valid list entries
+  Select number of presets or coefficients depending on the mode
+**/
+  UINT8                       PcieGen5EqPh3NoOfPresetOrCoeff[12];
+
+/** Offset 0x0978 - PCIE RP pre-cursor coefficient list
+  Provide a list of pre-cursor coefficients to be used during phase 3 EQ
+**/
+  UINT8                       PcieGen5EqPh3PreCursor0List[12];
+
+/** Offset 0x0984 - PCIE RP post-cursor coefficient list
+  Provide a list of post-cursor coefficients to be used during phase 3 EQ
+**/
+  UINT8                       PcieGen5EqPh3PostCursor0List[12];
+
+/** Offset 0x0990 - PCIE RP pre-cursor coefficient list
+  Provide a list of pre-cursor coefficients to be used during phase 3 EQ
+**/
+  UINT8                       PcieGen5EqPh3PreCursor1List[12];
+
+/** Offset 0x099C - PCIE RP post-cursor coefficient list
+  Provide a list of post-cursor coefficients to be used during phase 3 EQ
+**/
+  UINT8                       PcieGen5EqPh3PostCursor1List[12];
+
+/** Offset 0x09A8 - PCIE RP pre-cursor coefficient list
+  Provide a list of pre-cursor coefficients to be used during phase 3 EQ
+**/
+  UINT8                       PcieGen5EqPh3PreCursor2List[12];
+
+/** Offset 0x09B4 - PCIE RP post-cursor coefficient list
+  Provide a list of post-cursor coefficients to be used during phase 3 EQ
+**/
+  UINT8                       PcieGen5EqPh3PostCursor2List[12];
+
+/** Offset 0x09C0 - PCIR RP pre-cursor coefficient list
+  Provide a list of pre-cursor coefficients to be used during phase 3 EQ
+**/
+  UINT8                       PcieGen5EqPh3PreCursor3List[12];
+
+/** Offset 0x09CC - PCIE RP post-cursor coefficient list
+  Provide a list of post-cursor coefficients to be used during phase 3 EQ
+**/
+  UINT8                       PcieGen5EqPh3PostCursor3List[12];
+
+/** Offset 0x09D8 - PCIE RP pre-cursor coefficient list
+  Provide a list of pre-cursor coefficients to be used during phase 3 EQ
+**/
+  UINT8                       PcieGen5EqPh3PreCursor4List[12];
+
+/** Offset 0x09E4 - PCIE RP post-cursor coefficient list
+  Provide a list of post-cursor coefficients to be used during phase 3 EQ
+**/
+  UINT8                       PcieGen5EqPh3PostCursor4List[12];
+
+/** Offset 0x09F0 - PCIE RP pre-cursor coefficient list
+  Provide a list of pre-cursor coefficients to be used during phase 3 EQ
+**/
+  UINT8                       PcieGen5EqPh3PreCursor5List[12];
+
+/** Offset 0x09FC - PCIE RP post-cursor coefficient list
+  Provide a list of post-cursor coefficients to be used during phase 3 EQ
+**/
+  UINT8                       PcieGen5EqPh3PostCursor5List[12];
+
+/** Offset 0x0A08 - PCIE RP pre-cursor coefficient list
+  Provide a list of pre-cursor coefficients to be used during phase 3 EQ
+**/
+  UINT8                       PcieGen5EqPh3PreCursor6List[12];
+
+/** Offset 0x0A14 - PCIe post-cursor coefficient list
+  Provide a list of post-cursor coefficients to be used during phase 3 EQ
+**/
+  UINT8                       PcieGen5EqPh3PostCursor6List[12];
+
+/** Offset 0x0A20 - PCIE RP pre-cursor coefficient list
+  Provide a list of pre-cursor coefficients to be used during phase 3 EQ
+**/
+  UINT8                       PcieGen5EqPh3PreCursor7List[12];
+
+/** Offset 0x0A2C - PCIE RP post-cursor coefficient list
+  Provide a list of post-cursor coefficients to be used during phase 3 EQ
+**/
+  UINT8                       PcieGen5EqPh3PostCursor7List[12];
+
+/** Offset 0x0A38 - PCIE RP pre-cursor coefficient list
+  Provide a list of pre-cursor coefficients to be used during phase 3 EQ
+**/
+  UINT8                       PcieGen5EqPh3PreCursor8List[12];
+
+/** Offset 0x0A44 - PCIE RP post-cursor coefficient list
+  Provide a list of post-cursor coefficients to be used during phase 3 EQ
+**/
+  UINT8                       PcieGen5EqPh3PostCursor8List[12];
+
+/** Offset 0x0A50 - PCIE RP pre-cursor coefficient list
+  Provide a list of pre-cursor coefficients to be used during phase 3 EQ
+**/
+  UINT8                       PcieGen5EqPh3PreCursor9List[12];
+
+/** Offset 0x0A5C - PCIE RP post-cursor coefficient list
+  Provide a list of post-cursor coefficients to be used during phase 3 EQ
+**/
+  UINT8                       PcieGen5EqPh3PostCursor9List[12];
+
+/** Offset 0x0A68 - PCIE RP preset list
+  Provide a list of presets to be used during phase 3 EQ
+**/
+  UINT8                       PcieGen5EqPh3Preset0List[12];
+
+/** Offset 0x0A74 - PCIe preset list
+  Provide a list of presets to be used during phase 3 EQ
+**/
+  UINT8                       PcieGen5EqPh3Preset1List[12];
+
+/** Offset 0x0A80 - PCIE RP preset list
+  Provide a list of presets to be used during phase 3 EQ
+**/
+  UINT8                       PcieGen5EqPh3Preset2List[12];
+
+/** Offset 0x0A8C - PCIE RP preset list
+  Provide a list of presets to be used during phase 3 EQ
+**/
+  UINT8                       PcieGen5EqPh3Preset3List[12];
+
+/** Offset 0x0A98 - PCIE RP preset list
+  Provide a list of presets to be used during phase 3 EQ
+**/
+  UINT8                       PcieGen5EqPh3Preset4List[12];
+
+/** Offset 0x0AA4 - PCIE RP preset list
+  Provide a list of presets to be used during phase 3 EQ
+**/
+  UINT8                       PcieGen5EqPh3Preset5List[12];
+
+/** Offset 0x0AB0 - PCIE RP preset list
+  Provide a list of presets to be used during phase 3 EQ
+**/
+  UINT8                       PcieGen5EqPh3Preset6List[12];
+
+/** Offset 0x0ABC - PCIE RP preset list
+  Provide a list of presets to be used during phase 3 EQ
+**/
+  UINT8                       PcieGen5EqPh3Preset7List[12];
+
+/** Offset 0x0AC8 - PCIE RP preset list
+  Provide a list of presets to be used during phase 3 EQ
+**/
+  UINT8                       PcieGen5EqPh3Preset8List[12];
+
+/** Offset 0x0AD4 - PCIE RP preset list
+  Provide a list of presets to be used during phase 3 EQ
+**/
+  UINT8                       PcieGen5EqPh3Preset9List[12];
+
+/** Offset 0x0AE0 - PCIE RP preset list
+  Provide a list of presets to be used during phase 3 EQ
+**/
+  UINT8                       PcieGen5EqPh3Preset10List[12];
+
+/** Offset 0x0AEC - PCIe EQ phase 1 downstream transmitter port preset
+  Allows to select the downstream port preset value that will be used during phase
+  1 of equalization
+**/
+  UINT8                       PcieGen5EqPh1DpTxPreset[12];
+
+/** Offset 0x0AF8 - PCIE RP EQ phase 1 upstream tranmitter port preset
+  Allows to select the upstream port preset value that will be used during phase 1
+  of equalization
+**/
+  UINT8                       PcieGen5EqPh1UpTxPreset[12];
+
+/** Offset 0x0B04 - PCIE RP EQ phase 2 local transmitter override preset
+  Allows to select the value of the preset used during phase 2 local transmitter override
+**/
+  UINT8                       PcieGen5EqPh2LocalTxOverridePreset[12];
+
+/** Offset 0x0B10 - Phase3 RP Gen3 EQ enable
+  Phase3 Gen3 EQ enable. Disabled(0x0)(Default): Disable phase 3, Enabled(0x1): Enable phase 3
+  0:Disable, 1:Enable, 2:Auto
+**/
+  UINT8                       PcieRpGen3EqPh3Bypass[12];
+
+/** Offset 0x0B1C - Phase3 RP Gen4 EQ enable
+  Phase3 Gen4 EQ enable. Disabled(0x0)(Default): Disable phase 3, Enabled(0x1): Enable phase 3
+  0:Disable, 1:Enable, 2:Auto
+**/
+  UINT8                       PcieRpGen4EqPh3Bypass[12];
+
+/** Offset 0x0B28 - Phase3 RP Gen5 EQ enable
+  Phase3 Gen5 EQ enable. Disabled(0x0)(Default): Disable phase 3, Enabled(0x1): Enable phase 3
+  0:Disable, 1:Enable, 2:Auto
+**/
+  UINT8                       PcieRpGen5EqPh3Bypass[12];
+
+/** Offset 0x0B34 - Phase2-3 RP Gen3 EQ enable
+  Phase2-3 Gen3 EQ enable. Disabled(0x0)(Default): Disable Phase2-3, Enabled(0x1):
+  Enable Phase2-3
+  0:Disable, 1:Enable, 2:Auto
+**/
+  UINT8                       PcieRpGen3EqPh23Bypass[12];
+
+/** Offset 0x0B40 - Phase2-3 RP Gen4 EQ enable
+  Phase2-3 Gen4 EQ enable. Disabled(0x0)(Default): Disable Phase2-3, Enabled(0x1):
+  Enable Phase2-3
+  0:Disable, 1:Enable, 2:Auto
+**/
+  UINT8                       PcieRpGen4EqPh23Bypass[12];
+
+/** Offset 0x0B4C - Phase2-3 RP Gen5 EQ enable
+  Phase2-3 Gen5 EQ enable. Disabled(0x0)(Default): Disable Phase2-3, Enabled(0x1):
+  Enable Phase2-3
+  0:Disable, 1:Enable, 2:Auto
+**/
+  UINT8                       PcieRpGen5EqPh23Bypass[12];
+
+/** Offset 0x0B58 - PCET Timer
+  Preset/Coefficient Evaluation Timeout Gen3 PCET Timer. See PCIE_GEN3_PCET. Default
+  is 0x0(2ms)
+**/
+  UINT8                       PcieGen3PcetTimer[12];
+
+/** Offset 0x0B64 - Gen4 PCET Timer
+  Preset/Coefficient Evaluation Timeout - Gen4 PCET Timer. See PCIE_GEN4_PCET. Default
+  is 0x0(2ms)
+**/
+  UINT8                       PcieGen4PcetTimer[12];
+
+/** Offset 0x0B70 - Gen5 PCET Timer
+  Preset/Coefficient Evaluation Timeout - Gen5 PCET Timer. See PCIE_GEN5_PCET. Default
+  is 0x0(2ms)
+**/
+  UINT8                       PcieGen5PcetTimer[12];
+
+/** Offset 0x0B7C - TS Lock Timer for Gen3
+  Training Sequence Wait Latency For Presets/Coefficients Evaluation - Gen3 TS Lock
+  Timer. See PCIE_GEN3_TS_LOCK_TIMER. Default is 0x0
+**/
+  UINT8                       PcieGen3TsLockTimer[12];
+
+/** Offset 0x0B88 - PTS Lock Timer for Gen4
+  Training Sequence Wait Latency For Presets/Coefficients Evaluation - Gen4 TS Lock
+  Timer. See PCIE_GEN4_TS_LCOK_TIMER. Default is 0x0
+**/
+  UINT8                       PcieGen4TsLockTimer[12];
+
+/** Offset 0x0B94 - PTS Lock Timer for Gen5
+  Training Sequence Wait Latency For Presets/Coefficients Evaluation - Gen5 TS Lock
+  Timer. See PCIE_GEN5_TS_LCOK_TIMER. Default is 0x0
+**/
+  UINT8                       PcieGen5TsLockTimer[12];
+
+/** Offset 0x0BA0 - PCIE Secure Register Lock
+  Describes whether Secure Register Lock is enaled or disabled. When it will be enbaled,
+  load PcieRpSetSecuredRegisterLock recipe. 0: Disable(Default); 1: Enable
+  $EN_DIS
+**/
+  UINT8                       PcieSetSecuredRegisterLock;
+
+/** Offset 0x0BA1 - Enable/Disable ASPM Optionality Compliance
+  Enable/Disable ASPM Optionality Compliance.
+**/
+  UINT8                       PcieRpTestAspmOc[12];
 
 /** Offset 0x0BAD - PCIE RP Enable Peer Memory Write
   This member describes whether Peer Memory Writes are enabled on the platform.
@@ -1199,9 +2058,12 @@ typedef struct {
 **/
   UINT8                       PcieRpFunctionSwap;
 
-/** Offset 0x0BC7 - Reserved
+/** Offset 0x0BC7 - PCIe RootPort Clock Gating
+  Describes whether the PCI Express Clock Gating for each root port is enabled by
+  platform modules. 0: Disable; 1: Enable(Default).
+  $EN_DIS
 **/
-  UINT8                       Reserved22[12];
+  UINT8                       PcieClockGating[12];
 
 /** Offset 0x0BD3 - PCIe RootPort Power Gating
   Describes whether the PCI Express Power Gating for each root port is enabled by
@@ -1210,9 +2072,36 @@ typedef struct {
 **/
   UINT8                       PciePowerGating[12];
 
-/** Offset 0x0BDF - Reserved
+/** Offset 0x0BDF - PCIe RootPort VISA Clock Gating
+  Describes whether the PCI Express VISA Clock Gating. 0: Disable; 1: Enable(Default).
+  $EN_DIS
 **/
-  UINT8                       Reserved23[49];
+  UINT8                       PcieVisaClockGating[12];
+
+/** Offset 0x0BEB - PCIe RootPort AutoPower Gating
+  Describes the Auto Power Gating for per controller. 0: Disable; 1: Enable(Default).
+  $EN_DIS
+**/
+  UINT8                       PcieAutoPowerGating[12];
+
+/** Offset 0x0BF7 - PCIe RootPort PHY AutoPower Gating
+  Describes the PHY Auto Power Gating for per controller. 0: Disable; 1: Enable(Default).
+  $EN_DIS
+**/
+  UINT8                       PciePhyAutoPowerGating;
+
+/** Offset 0x0BF8 - FOMS Control Policy
+  Choose the Foms Control Policy, <b>Default = 0 </b>
+  0: Auto, 1: Gen3 Foms, 2: Gen4 Foms, 3: Gen3 and Gen4 Foms
+**/
+  UINT8                       PcieFomsCp[12];
+
+/** Offset 0x0C04 - EqPhBypass Control Policy
+  PCIe Equalization Phase Enable Control, <b>Disabled</b>       (0x0) : Disable Phase
+  (Default), Enabled (0x1) : Enable Phase
+  0: Auto, 1: Gen3 Foms, 2: Gen4 Foms, 3: Gen3 and Gen4 Foms
+**/
+  UINT8                       PcieEqPhBypass[12];
 
 /** Offset 0x0C10 - PCIE RP Ltr Max Snoop Latency
   Latency Tolerance Reporting, Max Snoop Latency.
@@ -1276,9 +2165,34 @@ typedef struct {
 **/
   UINT8                       PchPciePort8xhDecodePortIndex;
 
-/** Offset 0x0D8E - Reserved
+/** Offset 0x0D8E - PCIE RP LTR Override Spec Compliant
+  Override LTR based on Ep capability.
 **/
-  UINT8                       Reserved24[114];
+  UINT8                       PcieRpLtrOverrideSpecCompliant[28];
+
+/** Offset 0x0DAA - PCIe AER _OSC Setting
+  Enable/Disable Global PCIe Advanced Error Reporting
+  0:Disable, 1:Enable
+**/
+  UINT8                       GlobalPcieAer;
+
+/** Offset 0x0DAB - PCIe TBT Performance Boost Bitmap
+  Bitmap of TBT performance boost enabled PCIe controllers to which discrete TBT controllers
+  connect. Bit0: PXPA, Bit1: PXPB, Bit2: PXPC, Bit3: PXPD, Bit4: PXPE
+**/
+  UINT8                       PcieTbtPerfBoost;
+
+/** Offset 0x0DAC - Serial IO SPI CLK Pin Muxing
+  Select SerialIo LPSS SPI CS pin muxing. Refer to GPIO_*_MUXING_SERIALIO_SPIx_CLK*
+  for possible values.
+**/
+  UINT32                      SerialIoLpssSpiClkPinMux[7];
+
+/** Offset 0x0DC8 - Serial IO SPI CS Pin Muxing
+  Select SerialIo  LPSS SPI CS pin muxing. Refer to GPIO_*_MUXING_SERIALIO_SPIx_CS*
+  for possible values.
+**/
+  UINT32                      SerialIoLpssSpiCsPinMux[14];
 
 /** Offset 0x0E00 - SPIn Device Mode
   Selects SPI operation mode. N represents controller index: SPI0, SPI1, ... Available
@@ -1288,7 +2202,27 @@ typedef struct {
 
 /** Offset 0x0E07 - Reserved
 **/
-  UINT8                       Reserved25[85];
+  UINT8                       Reserved7;
+
+/** Offset 0x0E08 - LPSS SPI MOSI Pin Muxing
+  Select LPSS SPI MOSI pin muxing. Refer to GPIO_*_MUXING_LPSS_SPIx_MOSI* for possible values.
+**/
+  UINT32                      SerialIoLpssSpiMosiPinMux[7];
+
+/** Offset 0x0E24 - LPSS SPI MISO Pin Muxing
+  Select Lpss SPI MISO pin muxing. Refer to GPIO_*_MUXING_LPSS_SPIx_MISO* for possible values.
+**/
+  UINT32                      SerialIoLpssSpiMisoPinMux[7];
+
+/** Offset 0x0E40 - SPI<N> Chip Select Polarity
+  Sets polarity for each chip Select. Available options: 0:LpssSpiCsActiveLow, 1:LpssSpiCsActiveHigh
+**/
+  UINT8                       SerialIoLpssSpiCsPolarity[14];
+
+/** Offset 0x0E4E - SPI<N> Chip Select Enable
+  0:Disabled, 1:Enabled. Enables GPIO for CS0 or CS1 if it is Enabled
+**/
+  UINT8                       SerialIoLpssSpiCsEnable[14];
 
 /** Offset 0x0E5C - SPIn Default Chip Select Mode HW/SW
   Sets Default CS Mode Hardware or Software. N represents controller index: SPI0,
@@ -1311,7 +2245,7 @@ typedef struct {
 
 /** Offset 0x0E71 - Reserved
 **/
-  UINT8                       Reserved26[3];
+  UINT8                       Reserved8[3];
 
 /** Offset 0x0E74 - Default BaudRate for each Serial IO UART
   Set default BaudRate Supported from 0 - default to 6000000
@@ -1351,7 +2285,7 @@ typedef struct {
 
 /** Offset 0x0EBA - Reserved
 **/
-  UINT8                       Reserved27[2];
+  UINT8                       Reserved9[2];
 
 /** Offset 0x0EBC - SerialIoUartRtsPinMuxPolicy
   Select SerialIo Uart Rts pin muxing. Refer to GPIO_*_MUXING_SERIALIO_UARTx_RTS*
@@ -1377,9 +2311,11 @@ typedef struct {
 **/
   UINT8                       SerialIoUartDbg2[7];
 
-/** Offset 0x0F17 - Reserved
+/** Offset 0x0F17 - Serial IO UART PG DBG2 table
+  Enable or disable Serial Io UART PG DBG2 table, default is Disable; <b>0: Disable;</b>
+  1: Enable.
 **/
-  UINT8                       Reserved28[7];
+  UINT8                       SerialIoUartPgDbg2[7];
 
 /** Offset 0x0F1E - I2Cn Device Mode
   Selects I2c operation mode. N represents controller index: I2c0, I2c1, ... Available
@@ -1389,7 +2325,7 @@ typedef struct {
 
 /** Offset 0x0F26 - Reserved
 **/
-  UINT8                       Reserved29[2];
+  UINT8                       Reserved10[2];
 
 /** Offset 0x0F28 - Serial IO I2C SDA Pin Muxing
   Select SerialIo I2c Sda pin muxing. Refer to GPIO_*_MUXING_SERIALIO_I2Cx_SDA* for
@@ -1418,7 +2354,54 @@ typedef struct {
 
 /** Offset 0x0F73 - Reserved
 **/
-  UINT8                       Reserved30[48];
+  UINT8                       Reserved11;
+
+/** Offset 0x0F74 - Serial IO I3C SDA Pin Muxing
+  Select SerialIo I3c Sda pin muxing. Refer to GPIO_*_MUXING_SERIALIO_I3Cx_SDA* for
+  possible values.
+**/
+  UINT32                      SerialIoI3cSdaPinMux[3];
+
+/** Offset 0x0F80 - Serial IO I3C SDA Pad Termination
+  0x0: Hardware default, 0x1: None, 0x13: 1kOhm weak pull-up, 0x15: 5kOhm weak pull-up,
+  0x19: 20kOhm weak pull-up - Enable/disable SerialIo I3C0,I3C1,... pads termination
+  respectively. One byte for each controller, byte0 for I3C0, byte1 for I3C1, and so on.
+**/
+  UINT8                       SerialIoI3cSdaPadTermination[3];
+
+/** Offset 0x0F83 - Reserved
+**/
+  UINT8                       Reserved12;
+
+/** Offset 0x0F84 - Serial IO I3C SCL Pin Muxing
+  Select SerialIo I3c Scl pin muxing. Refer to GPIO_*_MUXING_SERIALIO_I3Cx_SCL* for
+  possible values.
+**/
+  UINT32                      SerialIoI3cSclPinMux[3];
+
+/** Offset 0x0F90 - Serial IO I3C SCL Pad Termination
+  0x0: Hardware default, 0x1: None, 0x13: 1kOhm weak pull-up, 0x15: 5kOhm weak pull-up,
+  0x19: 20kOhm weak pull-up - Enable/disable SerialIo I3C0,I3C1,... pads termination
+  respectively. One byte for each controller, byte0 for I3C0, byte1 for I3C1, and so on.
+**/
+  UINT8                       SerialIoI3cSclPadTermination[3];
+
+/** Offset 0x0F93 - Reserved
+**/
+  UINT8                       Reserved13;
+
+/** Offset 0x0F94 - Serial IO I3C SCL FB Pin Muxing
+  Select SerialIo I3c SclFb pin muxing. Refer to GPIO_*_MUXING_SERIALIO_I3Cx_SCL FB*
+  for possible values.
+**/
+  UINT32                      SerialIoI3cSclFbPinMux[3];
+
+/** Offset 0x0FA0 - Serial IO I3C SCL FB Pad Termination
+  0x0: Hardware default, 0x1: None, 0x13: 1kOhm weak pull-up, 0x15: 5kOhm weak pull-up,
+  0x19: 20kOhm weak pull-up - Enable/disable SerialIo I3C0,I3C1,... pads termination
+  respectively. One byte for each controller, byte0 for I3C0, byte1 for I3C1, and so on.
+**/
+  UINT8                       SerialIoI3cSclFbPadTermination[3];
 
 /** Offset 0x0FA3 - Enable VMD controller
   Enable/disable to VMD controller.0: Disable; 1: Enable(Default)
@@ -1438,9 +2421,10 @@ typedef struct {
 **/
   UINT8                       VmdPort[31];
 
-/** Offset 0x0FC4 - Reserved
+/** Offset 0x0FC4 - VMD Port Bus
+  VMD Root port bus number.
 **/
-  UINT8                       Reserved31[31];
+  UINT8                       VmdPortBus[31];
 
 /** Offset 0x0FE3 - VMD Port Device
   VMD Root port device number.
@@ -1454,16 +2438,17 @@ typedef struct {
 
 /** Offset 0x1021 - Reserved
 **/
-  UINT8                       Reserved32[7];
+  UINT8                       Reserved14[7];
 
 /** Offset 0x1028 - VMD Variable
   VMD Variable Pointer.
 **/
   UINT64                      VmdVariablePtr;
 
-/** Offset 0x1030 - Reserved
+/** Offset 0x1030 - Temporary CfgBar address for VMD
+  VMD Variable Pointer.
 **/
-  UINT8                      Reserved33[4];
+  UINT32                      VmdCfgBarBase;
 
 /** Offset 0x1034 - Temporary MemBar1 address for VMD
   VMD Variable Pointer.
@@ -1481,9 +2466,15 @@ typedef struct {
 **/
   UINT8                       D3HotEnable;
 
-/** Offset 0x103D - Reserved
+/** Offset 0x103D - TCSS TBT Performance Boost Bitmap
+  Bitmap of TBT performance boost enabled TCSS PCIe root ports. Bit0: TCSS port0,
+  Bit1: TCSS port1, Bit2: TCSS port2, Bit3: TCSS port3
 **/
-  UINT8                       Reserved34[3];
+  UINT8                       TcssTbtPerfBoost;
+
+/** Offset 0x103E - Reserved
+**/
+  UINT8                       Reserved15[2];
 
 /** Offset 0x1040 - TypeC port GPIO setting
   GPIO Ping number for Type C Aux orientation setting, use the GpioPad that is defined
@@ -1508,9 +2499,17 @@ typedef struct {
 **/
   UINT8                       TcCstateLimit;
 
-/** Offset 0x107C - Reserved
+/** Offset 0x107C - TC Notify Igd
+  Tc Notify Igd
 **/
-  UINT8                       Reserved35[2];
+  UINT8                       TcNotifyIgd;
+
+/** Offset 0x107D - TCSS CPU USB PDO Programming
+  Enable/disable PDO programming for TCSS CPU USB in PEI phase. Disabling will allow
+  for programming during later phase. 1: enable, 0: disable
+  $EN_DIS
+**/
+  UINT8                       TcssCpuUsbPdoProgramming;
 
 /** Offset 0x107E - Enable/Disable PMC-PD Solution
   This policy will enable/disable PMC-PD Solution vs EC-TCPC Solution
@@ -1520,7 +2519,7 @@ typedef struct {
 
 /** Offset 0x107F - Reserved
 **/
-  UINT8                       Reserved36;
+  UINT8                       Reserved16;
 
 /** Offset 0x1080 - TCSS Aux Orientation Override Enable
   Bits 0, 2, ... 10 control override enables, bits 1, 3, ... 11 control overrides
@@ -1594,9 +2593,11 @@ typedef struct {
 **/
   UINT8                       SaPcieItbtRpLtrConfigLock[4];
 
-/** Offset 0x10B6 - Reserved
+/** Offset 0x10B6 - Type C Port x Convert to TypeA
+  Enable / Disable(default) Type C Port x Convert to TypeA
+  $EN_DIS
 **/
-  UINT8                       Reserved37[4];
+  UINT8                       EnableTcssCovTypeA[4];
 
 /** Offset 0x10BA - Touch Host Controller Assignment
   Assign THC 0x0:ThcAssignmentNone, 0x1:ThcAssignmentThc0, 0x2:ThcAssignmentThc1
@@ -1620,9 +2621,276 @@ typedef struct {
 **/
   UINT8                       ThcWakeOnTouch[2];
 
-/** Offset 0x10C8 - Reserved
+/** Offset 0x10C8 - Touch Host Controller Active Ltr
+  Expose Active Ltr for OS driver to set
 **/
-  UINT8                      Reserved38[337];
+  UINT32                      ThcActiveLtr[2];
+
+/** Offset 0x10D0 - Touch Host Controller Idle Ltr
+  Expose Idle Ltr for OS driver to set
+**/
+  UINT32                      ThcIdleLtr[2];
+
+/** Offset 0x10D8 - Touch Host Controller Timestamp timer behavior in D0i2
+  Timestamp timer behavior in D0i2. 1 = Timer resets to 0 when entering D0i2 0 = Timer
+  is paused instead of reset to 0 when entering D0i2
+**/
+  UINT8                       TimestampTimerMode[2];
+
+/** Offset 0x10DA - Reserved
+**/
+  UINT8                       Reserved17[2];
+
+/** Offset 0x10DC - Touch Host Controller Display Frame Sync Period
+  Period of the emulated display frame sync [ms] The minimum period is 2ms, maximum
+  period is 100ms
+**/
+  UINT32                      DisplayFrameSyncPeriod[2];
+
+/** Offset 0x10E4 - Touch Host Controller ResetPad
+  ResetPad
+**/
+  UINT32                      ThcResetPad[2];
+
+/** Offset 0x10EC - Touch Host Controller ResetPad Trigger
+  Hid Over Spi Reset Pad Trigger 0x0:Low, 0x1:High
+**/
+  UINT32                      ThcResetPadTrigger[2];
+
+/** Offset 0x10F4 - Touch Host Controller DYSync
+  Based on this setting GPIO for given THC will be in native mode
+**/
+  UINT8                       ThcDsyncPad[2];
+
+/** Offset 0x10F6 - Reserved
+**/
+  UINT8                       Reserved18[2];
+
+/** Offset 0x10F8 - Touch Host Controller Hid Over Spi Connection Speed
+  Hid Over Spi Connection Speed - SPI Frequency
+**/
+  UINT32                      ThcHidSpiConnectionSpeed[2];
+
+/** Offset 0x1100 - Touch Host Controller Hid Over Spi Limit PacketSize
+  When set, limits SPI read & write packet size to 64B. Otherwise, THC uses Max Soc
+  packet size for SPI Read and Write 0x0- Max Soc Packet Size,  0x11 - 64 Bytes
+**/
+  UINT32                      ThcHidSpiLimitPacketSize[2];
+
+/** Offset 0x1108 - Touch Host Controller Hid Over Spi Limit PacketSize
+  Minimum amount of delay the THC/QUICKSPI driver must wait between end of write operation
+  and begin of read operation. This value shall be in 10us multiples 0x0: Disabled,
+  1-65535 (0xFFFF) - up to 655350 us
+**/
+  UINT32                      ThcPerformanceLimitation[2];
+
+/** Offset 0x1110 - Touch Host Controller Hid Over Spi Input Report Header Address
+  Hid Over Spi Input Report Header Address
+**/
+  UINT32                      ThcHidSpiInputReportHeaderAddress[2];
+
+/** Offset 0x1118 - Touch Host Controller Hid Over Spi Input Report Body Address
+  Hid Over Spi Input Report Body Address
+**/
+  UINT32                      ThcHidSpiInputReportBodyAddress[2];
+
+/** Offset 0x1120 - Touch Host Controller Hid Over Spi Output Report Address
+  Hid Over Spi Output Report Address
+**/
+  UINT32                      ThcHidSpiOutputReportAddress[2];
+
+/** Offset 0x1128 - Touch Host Controller Hid Over Spi Read Opcode
+  Hid Over Spi Read Opcode
+**/
+  UINT32                      ThcHidSpiReadOpcode[2];
+
+/** Offset 0x1130 - Touch Host Controller Hid Over Spi Write Opcode
+  Hid Over Spi Write Opcode
+**/
+  UINT32                      ThcHidSpiWriteOpcode[2];
+
+/** Offset 0x1138 - Touch Host Controller Hid Over Spi Flags
+  Hid Over Spi Flags 0x0:Single SPI Mode, 0x4000:Dual SPI Mode, 0x8000:Quad SPI Mode
+**/
+  UINT32                      ThcHidSpiFlags[2];
+
+/** Offset 0x1140 - Touch Host Controller Reset Sequencing Delay [ms]
+  Policy control for reset sequencing delay (ACPI _INI, _RST) default 300ms
+**/
+  UINT16                      ThcResetSequencingDelay[2];
+
+/** Offset 0x1144 - Touch Host Controller Hid Over I2c Device Address
+  Hid Over I2c Device Address
+**/
+  UINT32                      ThcHidI2cDeviceAddress[2];
+
+/** Offset 0x114C - Touch Host Controller Hid Over I2c Connection Speed
+  Hid Over I2c Connection Speed [Hz]
+**/
+  UINT32                      ThcHidI2cConnectionSpeed[2];
+
+/** Offset 0x1154 - Touch Host Controller Hid Over I2c Addressing Mode
+  Hid Over I2c Addressing Mode - 0x1: The connection uses 10-bit addressing. 0x0:
+  The connection uses 7-bit addressing.
+**/
+  UINT8                       ThcHidI2cAddressingMode[2];
+
+/** Offset 0x1156 - Reserved
+**/
+  UINT8                       Reserved19[2];
+
+/** Offset 0x1158 - Touch Host Controller Hid Over I2c Device Descriptor Address
+  Hid Over I2c Device Descriptor Address
+**/
+  UINT32                      ThcHidI2cDeviceDescriptorAddress[2];
+
+/** Offset 0x1160 - Touch Host Controller Hid Over I2c Serial Clock Line High Period
+  Hid Over I2c Device Descriptor Address
+**/
+  UINT32                      ThcHidI2cStandardModeSerialClockLineHighPeriod[2];
+
+/** Offset 0x1168 - Touch Host Controller Hid Over I2c Standard Mode Serial Clock Line Low Period
+  Hid Over I2c Device Descriptor Address
+**/
+  UINT32                      ThcHidI2cStandardModeSerialClockLineLowPeriod[2];
+
+/** Offset 0x1170 - Touch Host Controller Hid Over I2c Standard Mode Serial Data Line Transmit Hold Period
+  Hid Over I2c Device Descriptor Address
+**/
+  UINT32                      ThcHidI2cStandardModeSerialDataLineTransmitHoldPeriod[2];
+
+/** Offset 0x1178 - Touch Host Controller Hid Over I2c Standard Mode Serial Data Line Receive Hold Period
+  Hid Over I2c Device Descriptor Address
+**/
+  UINT32                      ThcHidI2cStandardModeSerialDataLineReceiveHoldPeriod[2];
+
+/** Offset 0x1180 - Touch Host Controller Hid Over I2c Fast Mode Serial Clock Line High Period
+  Hid Over I2c Device Descriptor Address
+**/
+  UINT32                      ThcHidI2cFastModeSerialClockLineHighPeriod[2];
+
+/** Offset 0x1188 - Touch Host Controller Hid Over I2c Fast Mode Serial Clock Line Low Period
+  Hid Over I2c Device Descriptor Address
+**/
+  UINT32                      ThcHidI2cFastModeSerialClockLineLowPeriod[2];
+
+/** Offset 0x1190 - Touch Host Controller Hid Over I2c Fast Mode Serial Data Line Transmit Hold Period
+  Hid Over I2c Device Descriptor Address
+**/
+  UINT32                      ThcHidI2cFastModeSerialDataLineTransmitHoldPeriod[2];
+
+/** Offset 0x1198 - Touch Host Controller Hid Over I2c Fast Mode Serial Data Line Receive Hold Period
+  Hid Over I2c Device Descriptor Address
+**/
+  UINT32                      ThcHidI2cFastModeSerialDataLineReceiveHoldPeriod[2];
+
+/** Offset 0x11A0 - Touch Host Controller Hid Over I2c Maximum Length Of Suppressed Spikes In Std Mode Fast Mode And Fast Mode Plus
+  Hid Over I2c Device Descriptor Address
+**/
+  UINT32                      ThcHidI2cMaxSuppressedSpikesSMFMFMP[2];
+
+/** Offset 0x11A8 - Touch Host Controller Hid Over I2c Fast Mode Plus Serial Clock Line High Period
+  Hid Over I2c Device Descriptor Address
+**/
+  UINT32                      ThcHidI2cFastModePlusSerialClockLineHighPeriod[2];
+
+/** Offset 0x11B0 - Touch Host Controller Hid Over I2c Fast Mode Plus Serial Clock Line Low Period
+  Hid Over I2c Device Descriptor Address
+**/
+  UINT32                      ThcHidI2cFastModePlusSerialClockLineLowPeriod[2];
+
+/** Offset 0x11B8 - Touch Host Controller Hid Over I2c Fast Mode Plus Serial Data Line Transmit Hold Period
+  Hid Over I2c Device Descriptor Address
+**/
+  UINT32                      ThcHidI2cFastModePlusSerialDataLineTransmitHoldPeriod[2];
+
+/** Offset 0x11C0 - Touch Host Controller Hid Over I2c Fast Mode Plus Serial Data Line Receive Hold Period
+  Hid Over I2c Device Descriptor Address
+**/
+  UINT32                      ThcHidI2cFastModePlusSerialDataLineReceiveHoldPeriod[2];
+
+/** Offset 0x11C8 - Touch Host Controller Hid Over I2c High Speed Mode Plus Serial Clock Line High Period
+  Hid Over I2c Device Descriptor Address
+**/
+  UINT32                      ThcHidI2cHighSpeedModePlusSerialClockLineHighPeriod[2];
+
+/** Offset 0x11D0 - Touch Host Controller Hid Over I2c High Speed Mode Plus Serial Clock Line Low Period
+  Hid Over I2c Device Descriptor Address
+**/
+  UINT32                      ThcHidI2cHighSpeedModePlusSerialClockLineLowPeriod[2];
+
+/** Offset 0x11D8 - Touch Host Controller Hid Over I2c High Speed Mode Plus Serial Data Line Transmit Hold Period
+  Hid Over I2c Device Descriptor Address
+**/
+  UINT32                      ThcHidI2cHighSpeedModePlusSerialDataLineTransmitHoldPeriod[2];
+
+/** Offset 0x11E0 - Touch Host Controller Hid Over I2c High Speed Mode Plus Serial Data Line Receive Hold Period
+  Hid Over I2c Device Descriptor Address
+**/
+  UINT32                      ThcHidI2cHighSpeedModePlusSerialDataLineReceiveHoldPeriod[2];
+
+/** Offset 0x11E8 - Touch Host Controller Hid Over I2c Maximum Length Of Suppressed Spikes In High Speed Mode
+  Hid Over I2c Device Descriptor Address
+**/
+  UINT32                      ThcHidI2cMaximumLengthOfSuppressedSpikesInHighSpeedMode[2];
+
+/** Offset 0x11F0 - THC Wake On Touch GPIO resource Edge or Level
+  Definition of GPIO resource configuration of Edge or Level
+**/
+  UINT8                       ThcWotEdgeLevel[2];
+
+/** Offset 0x11F2 - THC Wake On Touch GPIO resource of Active Level
+  Definition of GPIO resource configuration of Active Level
+**/
+  UINT8                       ThcWotActiveLevel[2];
+
+/** Offset 0x11F4 - THC Wake On Touch GPIO resource of pin configuration
+  Definition of GPIO resource configuration of pin configuration
+**/
+  UINT8                       ThcWotPinConfig[2];
+
+/** Offset 0x11F6 - THC customized SubSytem ID for Port
+  Definition of GPIO resource configuration of pin configuration
+**/
+  UINT16                      ThcCustomizedSsid[2];
+
+/** Offset 0x11FA - THC Sets Customized SubSytem Vendor ID for Port
+  Definition of GPIO resource configuration of pin configuration
+**/
+  UINT16                      ThcCustomizedSvid[2];
+
+/** Offset 0x11FE - Reserved
+**/
+  UINT8                       Reserved20[2];
+
+/** Offset 0x1200 - USB 3.1 Speed Selection
+  Choose USB 3.1 Port Speed Selection. Each bit represents a port. 1: Gen1, 0: Gen2
+**/
+  UINT32                      Usb31PortSpeed;
+
+/** Offset 0x1204 - Touch Host Controller Hid Over I2c Maximum Frame Size Enable
+  Choose USB 3.1 Port Speed Selection. Each bit represents a port. 1: Gen1, 0: Gen2
+**/
+  UINT8                       ThcHidI2cMaxFrameSize[2];
+
+/** Offset 0x1206 - Touch Host Controller Hid Over I2c Maximum Frame Size Value
+  Choose USB 3.1 Port Speed Selection. Each bit represents a port. 1: Gen1, 0: Gen2
+**/
+  UINT16                      ThcHidI2cMaxFrameSizeValue[2];
+
+/** Offset 0x120A - Touch Host Controller Hid Over I2c Interrupt Delay Enable
+  Choose USB 3.1 Port Speed Selection. Each bit represents a port. 1: Gen1, 0: Gen2
+**/
+  UINT8                       ThcHidI2cIntDelay[2];
+
+/** Offset 0x120C - Touch Host Controller Hid Over I2c Interrupt Delay Value
+  Choose USB 3.1 Port Speed Selection. Each bit represents a port. 1: Gen1, 0: Gen2
+**/
+  UINT16                      ThcHidI2cIntDelayValue[2];
+
+/** Offset 0x1210 - Reserved
+**/
+  UINT8                       Reserved21[9];
 
 /** Offset 0x1219 - PCHHOT# pin
   Enable PCHHOT# pin assertion when temperature is higher than PchHotLevel. 0: disable, 1: enable
@@ -1683,7 +2951,47 @@ typedef struct {
 
 /** Offset 0x122A - Reserved
 **/
-  UINT8                      Reserved39[34];
+  UINT8                      Reserved22[2];
+
+/** Offset 0x122C - PCH TSN MAC Address High Bits
+  Set TSN MAC Address High.
+**/
+  UINT32                      PchTsn1MacAddressHigh;
+
+/** Offset 0x1230 - PCH TSN MAC Address Low Bits
+  Set TSN MAC Address Low.
+**/
+  UINT32                      PchTsn1MacAddressLow;
+
+/** Offset 0x1234 - PCH TSN2 MAC Address High Bits
+  Set TSN2 MAC Address High.
+**/
+  UINT32                      PchTsn2MacAddressHigh;
+
+/** Offset 0x1238 - PCH TSN2 MAC Address Low Bits
+  Set TSN2 MAC Address Low.
+**/
+  UINT32                      PchTsn2MacAddressLow;
+
+/** Offset 0x123C - PCH TSN3 MAC Address High Bits
+  Set TSN3 MAC Address High.
+**/
+  UINT32                      PchTsn3MacAddressHigh;
+
+/** Offset 0x1240 - PCH TSN3 MAC Address Low Bits
+  Set TSN3 MAC Address Low.
+**/
+  UINT32                      PchTsn3MacAddressLow;
+
+/** Offset 0x1244 - PCH TSN4 MAC Address High Bits
+  Set TSN4 MAC Address High.
+**/
+  UINT32                      PchTsn4MacAddressHigh;
+
+/** Offset 0x1248 - PCH TSN MAC4 Address Low Bits
+  Set TSN MAC4 Address Low.
+**/
+  UINT32                      PchTsn4MacAddressLow;
 
 /** Offset 0x124C - Enable USB2 ports
   Enable/disable per USB2 ports. One byte for each port, byte0 for port0, byte1 for
@@ -1710,9 +3018,11 @@ typedef struct {
 **/
   UINT8                       UsbPdoProgramming;
 
-/** Offset 0x1268 - Reserved
+/** Offset 0x1268 - USB Audio Offload enable
+  Enable/Disable USB Audio Offload capabilites. 0: disabled, 1: enabled (default)
+  $EN_DIS
 **/
-  UINT8                       Reserved40;
+  UINT8                       PchXhciUaolEnable;
 
 /** Offset 0x1269 - PCH USB OverCurrent mapping enable
   1: Will program USB OC pin mapping in xHCI controller memory, 0: Will clear OC pin
@@ -1737,9 +3047,15 @@ typedef struct {
 **/
   UINT8                       PchUsbLtrOverrideEnable;
 
-/** Offset 0x1285 - Reserved
+/** Offset 0x1285 - USB DWB enable
+  Enable/Disable USB DWB. 0: disabled, 1: enabled (default)
+  $EN_DIS
 **/
-  UINT8                       Reserved41[3];
+  UINT8                       PchXhciDwbEnable;
+
+/** Offset 0x1286 - Reserved
+**/
+  UINT8                       Reserved23[2];
 
 /** Offset 0x1288 - xHCI High Idle Time LTR override
   Value used for overriding LTR recommendation for xHCI High Idle Time LTR setting
@@ -1897,9 +3213,21 @@ typedef struct {
 **/
   UINT8                       Usb3HsioTxRate0UniqTran[10];
 
-/** Offset 0x13AD - Reserved
+/** Offset 0x13AD - PCIe Fia Programming
+  Load Fia configuration if enable. 0: Disable; 1: Enable(Default).
+  $EN_DIS
 **/
-  UINT8                       Reserved42[4];
+  UINT8                       PcieFiaProgramming;
+
+/** Offset 0x13AE - Enable SSE Device
+  Test, 0: POR, 1: enable, 2: disable, Enable/Disable SSE/SSE++ Devices from PCI config space
+  $EN_DIS
+**/
+  UINT8                       SseCommunication;
+
+/** Offset 0x13AF - Reserved
+**/
+  UINT8                       Reserved24[2];
 
 /** Offset 0x13B1 - Enable/Disable NPU Device
   Enable(Default): Enable NPU Device, Disable: Disable NPU Device
@@ -1919,9 +3247,11 @@ typedef struct {
 **/
   UINT8                       PchLanLtrEnable;
 
-/** Offset 0x13B4 - Reserved
+/** Offset 0x13B4 - PCH Lan WOL Fast Support
+  Enables bit B_PCH_ACPI_GPE0_EN_127_96_PME_B0 during PchLanSxCallback in PchLanSxSmm.
+  $EN_DIS
 **/
-  UINT8                       Reserved43;
+  UINT8                       PchLanWOLFastSupport;
 
 /** Offset 0x13B5 - Skip Ssid Programming.
   When set to TRUE, silicon code will not do any SSID programming and platform code
@@ -1942,9 +3272,15 @@ typedef struct {
 **/
   UINT16                      SiCustomizedSsid;
 
-/** Offset 0x13BA - Reserved
+/** Offset 0x13BA - CAN Configurations
+  Enable/Disable CAN Controllers.0: Disable, <b>1: Enable</b>
+  $EN_DIS
 **/
-  UINT8                       Reserved44[6];
+  UINT8                       PchCanEnable[2];
+
+/** Offset 0x13BC - Reserved
+**/
+  UINT8                       Reserved25[4];
 
 /** Offset 0x13C0 - SVID SDID table Poniter.
   The address of the table of SVID SDID to customize each SVID SDID entry. This is
@@ -1958,9 +3294,15 @@ typedef struct {
 **/
   UINT16                      SiNumberOfSsidTableEntry;
 
-/** Offset 0x13CA - Reserved
+/** Offset 0x13CA - Skip DFX.
+  Skip DFX.
+  $EN_DIS
 **/
-  UINT8                       Reserved45[10];
+  UINT8                       DfxSkipBiosDone;
+
+/** Offset 0x13CB - Reserved
+**/
+  UINT8                       Reserved26[9];
 
 /** Offset 0x13D4 - LogoPixelHeight Address
   Address of LogoPixelHeight
@@ -1974,7 +3316,7 @@ typedef struct {
 
 /** Offset 0x13DC - Reserved
 **/
-  UINT8                       Reserved46[4];
+  UINT8                       Reserved27[4];
 
 /** Offset 0x13E0 - Blt Buffer Address
   Address of Blt buffer
@@ -1992,9 +3334,11 @@ typedef struct {
 **/
   UINT8                       SkipFspGop;
 
-/** Offset 0x13F1 - Reserved
+/** Offset 0x13F1 - Enable/Disable Media Configuration
+  Enable(Default): Configure Media for use, Disable: Skip Media Configuration
+  $EN_DIS
 **/
-  UINT8                       Reserved47;
+  UINT8                       ConfigureMedia;
 
 /** Offset 0x13F2 - Enable/Disable IGFX RenderStandby
   Enable(Default): Enable IGFX RenderStandby, Disable: Disable IGFX RenderStandby
@@ -2002,9 +3346,23 @@ typedef struct {
 **/
   UINT8                       RenderStandby;
 
-/** Offset 0x13F3 - Reserved
+/** Offset 0x13F3 - Enable/Disable GT Configuration
+  Enable(Default): Configure GT for use, Disable: Skip GT Configuration
+  $EN_DIS
 **/
-  UINT8                       Reserved48[3];
+  UINT8                       ConfigureGT;
+
+/** Offset 0x13F4 - Enable RC1p GT frequency request to PMA (provided all other conditions are met)
+  0(Default)=Disable, 1=Enable
+  $EN_DIS
+**/
+  UINT8                       RC1pGtFreqEnable;
+
+/** Offset 0x13F5 - Enable RC1p Media frequency request to PMA (provided all other conditions are met)
+  0(Default)=Disable, 1=Enable
+  $EN_DIS
+**/
+  UINT8                       RC1pMediaFreqEnable;
 
 /** Offset 0x13F6 - Enable/Disable PavpEnable
   Enable(Default): Enable PavpEnable, Disable: Disable PavpEnable
@@ -2019,9 +3377,21 @@ typedef struct {
 **/
   UINT8                       PeiGraphicsPeimInit;
 
-/** Offset 0x13F8 - Reserved
+/** Offset 0x13F8 - Enable/Disable IGFX Media Standby
+  Enable(Default): Enable IGFX Media Standby, Disable: Disable IGFX MediaStandby
+  $EN_DIS
 **/
-  UINT8                       Reserved49[4];
+  UINT8                       MediaStandby;
+
+/** Offset 0x13F9 - Enable/Disable Gfx Workstation
+  Enable(Default): Is a workstation, Disable: Is not a workstation
+  $EN_DIS
+**/
+  UINT8                       Dev2IsGfxWorkstation;
+
+/** Offset 0x13FA - Reserved
+**/
+  UINT8                       Reserved28[2];
 
 /** Offset 0x13FC - Intel Graphics VBT (Video BIOS Table) Size
   Size of Internal Graphics VBT Image
@@ -2042,7 +3412,21 @@ typedef struct {
 
 /** Offset 0x1402 - Reserved
 **/
-  UINT8                       Reserved50[66];
+  UINT8                       Reserved29[2];
+
+/** Offset 0x1404 - HorizontalResolution for PEI Logo
+  HorizontalResolution from PEIm Gfx for PEI Logo
+**/
+  UINT32                      HorizontalResolution;
+
+/** Offset 0x1408 - VerticalResolution for PEI Logo
+  VerticalResolution from PEIm Gfx for PEI Logo
+**/
+  UINT32                      VerticalResolution;
+
+/** Offset 0x140C - Reserved
+**/
+  UINT8                       Reserved30[56];
 
 /** Offset 0x1444 - Address of PCH_DEVICE_INTERRUPT_CONFIG table.
   The address of the table of PCH_DEVICE_INTERRUPT_CONFIG.
@@ -2076,9 +3460,33 @@ typedef struct {
 **/
   UINT8                       TcoIrqEnable;
 
-/** Offset 0x144D - Reserved
+/** Offset 0x144D - PMC ADR enable
+  Enable/disable asynchronous DRAM refresh
+  $EN_DIS
 **/
-  UINT8                       Reserved51[5];
+  UINT8                       PmcAdrEn;
+
+/** Offset 0x144E - PMC ADR timer configuration enable
+  Enable/disable ADR timer configuration
+  $EN_DIS
+**/
+  UINT8                       PmcAdrTimerEn;
+
+/** Offset 0x144F - PMC ADR phase 1 timer value
+  Enable/disable ADR timer configuration
+**/
+  UINT8                       PmcAdrTimer1Val;
+
+/** Offset 0x1450 - PMC ADR phase 1 timer multiplier value
+  Specify the multiplier value for phase 1 ADR timer
+**/
+  UINT8                       PmcAdrMultiplier1Val;
+
+/** Offset 0x1451 - PMC ADR host reset partition enable
+  Specify whether PMC should set ADR_RST_STS bit after receiving Reset_Warn_Ack DMI message
+  $EN_DIS
+**/
+  UINT8                       PmcAdrHostPartitionReset;
 
 /** Offset 0x1452 - Mask to enable the usage of external V1p05 VR rail in specific S0ix or Sx states
   Enable External V1P05 Rail in: BIT0:S0i1/S0i2, BIT1:S0i3, BIT2:S3, BIT3:S4, BIT5:S5
@@ -2112,7 +3520,7 @@ typedef struct {
 
 /** Offset 0x1459 - Reserved
 **/
-  UINT8                       Reserved52;
+  UINT8                       Reserved31;
 
 /** Offset 0x145A - External Vnn Voltage Value that will be used in S0ix/Sx states
   Value is given in 2.5mV increments (0=0mV, 1=2.5mV, 2=5mV...), Default is set to 420
@@ -2173,7 +3581,7 @@ typedef struct {
 
 /** Offset 0x1467 - Reserved
 **/
-  UINT8                       Reserved53;
+  UINT8                       Reserved32;
 
 /** Offset 0x1468 - External V1P05 Icc Max Value
   Granularity of this setting is 1mA and maximal possible value is 500mA
@@ -2213,9 +3621,11 @@ typedef struct {
 **/
   UINT8                       PchLegacyIoLowLatency;
 
-/** Offset 0x1472 - Reserved
+/** Offset 0x1472 - PCH P2SB
+  PCH P2SB
+  $EN_DIS
 **/
-  UINT8                       Reserved54;
+  UINT8                       SvTestUnhideP2sb;
 
 /** Offset 0x1473 - PCH Unlock SideBand access
   The SideBand PortID mask for certain end point (e.g. PSFx) will be locked before
@@ -2282,9 +3692,19 @@ typedef struct {
 **/
   UINT8                       CnviBtAudioOffload;
 
-/** Offset 0x147D - Reserved
+/** Offset 0x147D - WWAN Coex
+  WWAN Coex is getting updated from UEFI variable
 **/
-  UINT8                       Reserved55[3];
+  UINT8                       CnviWwanCoex;
+
+/** Offset 0x147E - Skip BtPreInit
+  BtPreInit can be skipped if SkipBtPreInit is enabled
+**/
+  UINT8                       SkipBtPreInit;
+
+/** Offset 0x147F - Reserved
+**/
+  UINT8                       Reserved33;
 
 /** Offset 0x1480 - CNVi RF_RESET pin muxing
   Select CNVi RF_RESET# pin depending on board routing. LP/P/M: GPP_A8 = 0x2942E408(default)
@@ -2299,9 +3719,11 @@ typedef struct {
 **/
   UINT32                      CnviClkreqPinMux;
 
-/** Offset 0x1488 - Reserved
+/** Offset 0x1488 - CNVi BT Audio OffOffloadInterfaceload
+  Enable/Disable BT Audio OffloadInterface, Default is ENABLE. 0: DISABLE, 1: ENABLE
+  $EN_DIS
 **/
-  UINT8                       Reserved56;
+  UINT8                       CnviBtAudioOffloadInterface;
 
 /** Offset 0x1489 - Enable Device 4
   Enable/disable Device 4
@@ -2316,9 +3738,10 @@ typedef struct {
 **/
   UINT8                       SkipPamLock;
 
-/** Offset 0x148B - Reserved
+/** Offset 0x148B - TCSS LSx OE Enable
+  Bits 0, 1, ... max Type C Rettimerless port LSx OE enables
 **/
-  UINT8                       Reserved57;
+  UINT8                       TcssLsxOe;
 
 /** Offset 0x148C - PCH HDA Verb Table Entry Number
   Number of Entries in Verb Table.
@@ -2327,7 +3750,7 @@ typedef struct {
 
 /** Offset 0x148D - Reserved
 **/
-  UINT8                       Reserved58[3];
+  UINT8                       Reserved34[3];
 
 /** Offset 0x1490 - PCH HDA Verb Table Pointer
   Pointer to Array of pointers to Verb Table.
@@ -2359,9 +3782,11 @@ typedef struct {
 **/
   UINT8                       PchHdaMicPrivacyMode;
 
-/** Offset 0x149C - Reserved
+/** Offset 0x149C - HD Audio Microphone Privacy Deglitch
+  HD Audio Microphone Privacy Deglitch: 0: Disable, 1: Enable
+  $EN_DIS
 **/
-  UINT8                       Reserved59;
+  UINT8                       PchHdaMicPrivacyDeglitch;
 
 /** Offset 0x149D - HD Audio Microphone Privacy applied for SoundWire Link number 0 in HW Mode
   HD Audio Microphone Privacy applied for SoundWire Link number 0 in HW Mode: 0: Disable, 1: Enable
@@ -2401,7 +3826,17 @@ typedef struct {
 
 /** Offset 0x14A3 - Reserved
 **/
-  UINT8                       Reserved60[13];
+  UINT8                       Reserved35;
+
+/** Offset 0x14A4 - HD Audio Microphone Privacy Timeout. Indicates the time-out duration to wait before forcing the actual microphone privacy DMA data zeroing.
+  HD Audio Microphone Privacy Timeout. Indicates the time-out duration to wait before
+  forcing the actual microphone privacy DMA data zeroing.
+**/
+  UINT32                      PchHdaMicPrivacyTimeout;
+
+/** Offset 0x14A8 - Reserved
+**/
+  UINT8                       Reserved36[8];
 
 /** Offset 0x14B0 - Pointer to ChipsetInit Binary
   ChipsetInit Binary Pointer.
@@ -2415,7 +3850,49 @@ typedef struct {
 
 /** Offset 0x14BC - Reserved
 **/
-  UINT8                       Reserved61[36];
+  UINT8                       Reserved37[4];
+
+/** Offset 0x14C0 - Pointer to NPHY Binary
+  Nphy Binary Pointer.
+**/
+  UINT64                      NphyBinPtr;
+
+/** Offset 0x14C8 - Length of NPHY Binary
+  Nphy Binary Length.
+**/
+  UINT32                      NphyBinLen;
+
+/** Offset 0x14CC - Reserved
+**/
+  UINT8                       Reserved38[4];
+
+/** Offset 0x14D0 - Pointer to SYNPS PHY Binary
+  Synps Binary Pointer.
+**/
+  UINT64                      SynpsPhyBinPtr;
+
+/** Offset 0x14D8 - Length of SYNPS PHY Binary
+  Synps Binary Length.
+**/
+  UINT32                      SynpsPhyBinLen;
+
+/** Offset 0x14DC - Skip setting BIOS_DONE When Fw Update.
+  When set to TRUE and boot mode is BOOT_ON_FLASH_UPDATE,skip setting BIOS_DONE MSR
+  at EndofPei. Note: BIOS_DONE MSR should be set in later phase before executing
+  3rd party code if SiSkipBiosDoneWhenFwUpdate set to TRUE.
+  $EN_DIS
+**/
+  UINT8                       SiSkipBiosDoneWhenFwUpdate;
+
+/** Offset 0x14DD - PMC WDT enable
+  Enable/disable PMC WDT configuration
+  $EN_DIS
+**/
+  UINT8                       PmcWdtTimerEn;
+
+/** Offset 0x14DE - Reserved
+**/
+  UINT8                       Reserved39[2];
 } FSP_S_CONFIG;
 
 /** Fsp S UPD Configuration

From 63ec633ccddd7f1600d19df274a4ef91c9be864b Mon Sep 17 00:00:00 2001
From: Appukuttan V K <appukuttan.vk@intel.com>
Date: Tue, 6 Jan 2026 22:02:23 +0530
Subject: [PATCH 3089/3886] mb/google/ocelot: Update sagv_freq_mhz as per
 platform POR config

Update the SaGV frequency registers in the devicetree as per
platform Plan of Record (POR) configuration:

 - sagv_freq_mhz[1]: 3200 MHz -> 4800 MHz
 - sagv_freq_mhz[2]: 6000 MHz -> 6400 MHz
 - sagv_freq_mhz[3]: 6400 MHz -> 7467 MHz

The current frequency points were configured lower than the
platform's expected specifications.

BUG=None
TEST=Boot ocelot and verify that the system boots and MRC training
is successful for each SAGV point.

 [SPEW ]  Requested/actual ratio 72/72, Frequency=2400,
		GearMode=1, RefClk=33MHz, tCK=3333333fs
 [SPEW ]  Requested/actual ratio 144/144, Frequency=4800,
	        GearMode=1, RefClk=33MHz, tCK=1666667fs
 [SPEW ]  Requested/actual ratio 192/192, Frequency=6400,
                GearMode=1, RefClk=33MHz, tCK=1250000fs
 [SPEW ]  Requested/actual ratio 224/224, Frequency=7467,
                GearMode=1, RefClk=33MHz, tCK=1071429fs

Change-Id: I7beab13bd9188aa47a45bc4a265aba75f00eded8
Signed-off-by: Appukuttan V K <appukuttan.vk@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90688
Reviewed-by: Avi Uday <aviuday@google.com>
Reviewed-by: P, Usha <usha.p@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Pranava Y N <pranavayn@google.com>
---
 .../google/ocelot/variants/baseboard/ocelot/devicetree.cb   | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/src/mainboard/google/ocelot/variants/baseboard/ocelot/devicetree.cb b/src/mainboard/google/ocelot/variants/baseboard/ocelot/devicetree.cb
index e2ea33173b..9391ac9d37 100644
--- a/src/mainboard/google/ocelot/variants/baseboard/ocelot/devicetree.cb
+++ b/src/mainboard/google/ocelot/variants/baseboard/ocelot/devicetree.cb
@@ -35,13 +35,13 @@ chip soc/intel/pantherlake
 	register "sagv_freq_mhz[0]" = "2400"
 	register "sagv_gear[0]" = "GEAR_4"
 
-	register "sagv_freq_mhz[1]" = "3200"
+	register "sagv_freq_mhz[1]" = "4800"
 	register "sagv_gear[1]" = "GEAR_4"
 
-	register "sagv_freq_mhz[2]" = "6000"
+	register "sagv_freq_mhz[2]" = "6400"
 	register "sagv_gear[2]" = "GEAR_4"
 
-	register "sagv_freq_mhz[3]" = "6400"
+	register "sagv_freq_mhz[3]" = "7467"
 	register "sagv_gear[3]" = "GEAR_4"
 
 	# Enable s0ix

From edae16f6f255c7194c51481b952801ea35640112 Mon Sep 17 00:00:00 2001
From: Pierce Chou <chou.pierce@inventec.corp-partner.google.com>
Date: Wed, 14 Jan 2026 10:13:31 +0800
Subject: [PATCH 3090/3886] mb/google/ocelot/var/ocicat: Add wake support for
 touchscreen

This commit introduces support for touch functionalities on the
ocicat board. Changes include:

- Support for touchscreen devices in THC-I2C
- Wake support from S0ix state for touchscreen
- PMC GPE DW0 is reconfigured to GPP_F for Touchscreen in
variant.c for wake support

BUG=b:444942125
TEST= Build Ocicat and Test wake from S0ix state via touchscreen inputs.

Change-Id: Icf6fb0e170a64a5aec05590450a3bd40ab95cbf3
Signed-off-by: Pierce Chou <chou.pierce@inventec.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90750
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Pranava Y N <pranavayn@google.com>
Reviewed-by: Avi Uday <aviuday@google.com>
---
 .../ocelot/variants/ocicat/overridetree.cb    |  8 +++++++-
 .../google/ocelot/variants/ocicat/variant.c   | 19 +++++++++++++++++++
 2 files changed, 26 insertions(+), 1 deletion(-)

diff --git a/src/mainboard/google/ocelot/variants/ocicat/overridetree.cb b/src/mainboard/google/ocelot/variants/ocicat/overridetree.cb
index 52ada4b77c..61a9c72b96 100644
--- a/src/mainboard/google/ocelot/variants/ocicat/overridetree.cb
+++ b/src/mainboard/google/ocelot/variants/ocicat/overridetree.cb
@@ -246,6 +246,7 @@ chip soc/intel/pantherlake
 
 		device ref thc0 on
 			register "thc_wake_on_touch[0]" = "true"
+			register "thc_mode[0]" = "THC_HID_I2C_MODE"
 			# THC0 is function 0; hence it needs to be enabled when THC1 is to be enabled.
 			chip drivers/intel/touch
 				register "name" = "INTEL_THC0_NAME"
@@ -265,6 +266,7 @@ chip soc/intel/pantherlake
 		end
 		device ref thc1 on
 			register "thc_wake_on_touch[1]" = "true"
+			register "thc_mode[1]" = "THC_HID_I2C_MODE"
 			chip drivers/intel/touch
 				register "name" = "INTEL_THC1_NAME"
 				register "mode" = "THC_HID_I2C_MODE"
@@ -273,7 +275,7 @@ chip soc/intel/pantherlake
 				register "wake_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW_WAKE(GPP_VGPIO3_THC1)"
 				register "active_ltr" = "1"
 				register "idle_ltr" = "0"
-				register "connected_device" = "TH_SENSOR_HYNITRON"
+				register "connected_device" = "TH_SENSOR_ELAN"
 				register "add_acpi_dma_property" = "true"
 				device generic 0 alias touch_1_i2c_hynitron on end
 			end
@@ -434,6 +436,8 @@ chip soc/intel/pantherlake
 				register "generic.hid" = ""ELAN2513""
 				register "generic.desc" = ""ELAN Touchscreen""
 				register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_F18_IRQ)"
+				# NOTE: pmc_gpe0_dw0 will be overridden to GPP_F in variant.c.
+				register "generic.wake" = "GPE0_DW0_18"
 				register "generic.detect" = "1"
 				register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_F16)"
 				register "generic.reset_delay_ms" = "20"
@@ -454,6 +458,8 @@ chip soc/intel/pantherlake
 				register "generic.hid" = ""ELAN2513""
 				register "generic.desc" = ""ELAN Touchscreen""
 				register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_F18_IRQ)"
+				# NOTE: pmc_gpe0_dw0 will be overridden to GPP_F in variant.c.
+				register "generic.wake" = "GPE0_DW0_18"
 				register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_F16)"
 				register "generic.reset_delay_ms" = "20"
 				register "generic.reset_off_delay_ms" = "2"
diff --git a/src/mainboard/google/ocelot/variants/ocicat/variant.c b/src/mainboard/google/ocelot/variants/ocicat/variant.c
index 733cf6bf3b..935327f255 100644
--- a/src/mainboard/google/ocelot/variants/ocicat/variant.c
+++ b/src/mainboard/google/ocelot/variants/ocicat/variant.c
@@ -15,6 +15,25 @@ const char *get_wifi_sar_cbfs_filename(void)
 	return get_wifi_sar_fw_config_filename(FW_CONFIG_FIELD(WIFI_INTERFACE));
 }
 
+void variant_update_soc_chip_config(struct soc_intel_pantherlake_config *config)
+{
+	/* Touchscreen and Touchpad WOT support:
+	* +===================+==================+=================+========================+
+	* | Touchscreen       | Touchpad         | PMC_GPE0_DW0    | WOT                    |
+	* +===================+==================+=================+========================+
+	* | THC-SPI/THC-I2C   | THC-I2C          | VGPIO           | TS, TP                 |
+	* +===================+==================+=================+========================+
+	* | THC-SPI/THC-I2C   | LPSS-I2C         | GPP_F18         | TP                     |
+	* +===================+==================+=================+========================+
+	*/
+
+	config->thc_mode[0] = THC_HID_I2C_MODE;
+	config->thc_mode[1] = THC_HID_I2C_MODE;
+
+	/* touchscreen: GPP_F18: GPE0_DW0_18 */
+	config->pmc_gpe0_dw0 = GPP_F;
+}
+
 void variant_update_soc_memory_init_params(FSPM_UPD *memupd)
 {
 	FSP_M_CONFIG *m_cfg = &memupd->FspmConfig;

From 9e865fb880ec9857d90babcc2693c549a6c2b826 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Micha=C5=82=20=C5=BBygowski?= <michal.zygowski@3mdeb.com>
Date: Tue, 9 Sep 2025 10:09:32 +0200
Subject: [PATCH 3091/3886] amdblocks/acpi/ivrs: Fix IVRS generation for
 multiple IOMMUs
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

More complex systems, such as servers, have multiple IOMMUs. For
example, Turin CPUs have a total of 4 IOMMUs per socket. Abort IVHD
generation only if IOMMU is not present on domain 0. For other domains
simply continue the loop, so that other domains have their IOMMUs
described properly in the IVRS. To keep simple systems working as
before, IVHD generation is aborted, if IOMMU is not present in domain 0.

TEST=See IOMMUs on domains 1,3,4,6 being skipped during IVHD generation
instead of IVHD generation being aborted on domain 1 on
Gigabyte MZ33-AR1 console log.

Change-Id: Icd3a51621908dc3ee5c85aa1e5814f3b3ac69007
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89111
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/soc/amd/common/block/acpi/ivrs.c | 20 ++++++++++++++------
 1 file changed, 14 insertions(+), 6 deletions(-)

diff --git a/src/soc/amd/common/block/acpi/ivrs.c b/src/soc/amd/common/block/acpi/ivrs.c
index 48c3965926..c3af6285a6 100644
--- a/src/soc/amd/common/block/acpi/ivrs.c
+++ b/src/soc/amd/common/block/acpi/ivrs.c
@@ -171,7 +171,7 @@ static unsigned long acpi_ivhd_misc(unsigned long current, struct device *dev)
 	/*
 	 * Add all possible PCI devices in the domain that can generate transactions
 	 * processed by IOMMU. Start with device <bus>:01.0
-	*/
+	 */
 	current = ivhd_dev_range(current, PCI_DEVFN(0, 3) | (dev->downstream->secondary << 8),
 				 0xff | (dev->downstream->subordinate << 8), 0);
 
@@ -311,6 +311,7 @@ static unsigned long acpi_fill_ivrs(acpi_ivrs_t *ivrs, unsigned long current)
 	struct device *iommu_dev;
 	struct device *nb_dev;
 	struct device *dev = NULL;
+	unsigned int domain;
 
 	if (ivrs == NULL) {
 		printk(BIOS_WARNING, "%s: ivrs is NULL\n", __func__);
@@ -322,15 +323,22 @@ static unsigned long acpi_fill_ivrs(acpi_ivrs_t *ivrs, unsigned long current)
 	while ((dev = dev_find_path(dev, DEVICE_PATH_DOMAIN)) != NULL) {
 		nb_dev = pcidev_path_behind(dev->downstream, PCI_DEVFN(0, 0));
 		iommu_dev = pcidev_path_behind(dev->downstream, PCI_DEVFN(0, 2));
+		domain = dev_get_domain_id(dev);
 		if (!nb_dev) {
-			printk(BIOS_WARNING, "%s: Northbridge device not present!\n", __func__);
-			printk(BIOS_WARNING, "%s: IVRS table not generated...\n", __func__);
-			return (unsigned long)ivrs;
+			printk(BIOS_WARNING, "%s: Northbridge device not present on domain %u!\n", __func__, domain);
+			if (domain == 0) {
+				printk(BIOS_WARNING, "%s: IVRS table not generated...\n", __func__);
+				return (unsigned long)ivrs;
+			}
+			continue;
 		}
 
 		if (!iommu_dev) {
-			printk(BIOS_WARNING, "%s: IOMMU device not found\n", __func__);
-			return (unsigned long)ivrs;
+			printk(BIOS_WARNING, "%s: IOMMU device not found on domain %u\n", __func__, dev_get_domain_id(dev));
+			if (domain == 0)
+				return (unsigned long)ivrs;
+
+			continue;
 		}
 
 		ivhd->type = IVHD_BLOCK_TYPE_LEGACY__FIXED;

From 96d5c3dd54b08070e7557459c7aeb304eaf8ad21 Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Tue, 20 Jan 2026 14:28:15 +0000
Subject: [PATCH 3092/3886] ec/starlabs/merlin: Set the default changing speed
 to 1.0C

Change-Id: I0aed42d85bbcebb2eba329d818b8e7b153a9f3b1
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90836
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/ec/starlabs/merlin/cfr.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/ec/starlabs/merlin/cfr.h b/src/ec/starlabs/merlin/cfr.h
index 170ec7a0dd..760c41afb6 100644
--- a/src/ec/starlabs/merlin/cfr.h
+++ b/src/ec/starlabs/merlin/cfr.h
@@ -75,7 +75,7 @@ static const struct sm_object charging_speed = SM_DECLARE_ENUM({
 	.ui_name	= "Charging Speed",
 	.ui_helptext	= "Set the maximum speed to charge the battery. Charging faster"
 		  " will increase heat and battery wear.",
-	.default_value	= SPEED_0_5C,
+	.default_value	= SPEED_1_0C,
 	.values		= (const struct sm_enum_value[]) {
 			{ "1.0C",		SPEED_1_0C	},
 			{ "0.5C",		SPEED_0_5C	},

From 53d31a4152f16d49f63c491bf89de15790d588bd Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Tue, 20 Jan 2026 14:34:27 +0000
Subject: [PATCH 3093/3886] mb/starlabs/*: Adjust the default power profile

If the board has a fan, set the default profile to Performance. If not,
use Balanced.

Change-Id: I8adb22f38a8aec55ed86a3aa29e8abfde5670867
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90837
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/starlabs/common/include/common/cfr.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/mainboard/starlabs/common/include/common/cfr.h b/src/mainboard/starlabs/common/include/common/cfr.h
index 1b89642133..58c4ec2a8e 100644
--- a/src/mainboard/starlabs/common/include/common/cfr.h
+++ b/src/mainboard/starlabs/common/include/common/cfr.h
@@ -101,7 +101,7 @@ static const struct sm_object power_profile = SM_DECLARE_ENUM({
 	.opt_name	= "power_profile",
 	.ui_name	= "Power Profile",
 	.ui_helptext	= "Select whether to maximize performance, battery life or both.",
-	.default_value	= 1,
+	.default_value	= CONFIG(EC_STARLABS_FAN) ? PP_PERFORMANCE : PP_BALANCED,
 	.values		= (const struct sm_enum_value[]) {
 			{ "Power Saver",	PP_POWER_SAVER	},
 			{ "Balanced",		PP_BALANCED	},

From 7d4e2c6150841b3279ed10722253c31c4d43d9e4 Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Tue, 20 Jan 2026 14:47:57 +0000
Subject: [PATCH 3094/3886] mb/starlabs/*: Default to ASPM_L0S_L1 over
 ASPM_AUTO

Set the default for ASPM to ASPM_L0S_L1 rather than ASPM_AUTO, as
using AUTO won't always enable ASPM for some SSDs (Western Digital).

Test=build and flash starbook/mtl; check new default is ASPM_L0S_L1
in edk2 menu.

Change-Id: If66dcabe5eca717565e0378ab36db8a4cb220d43
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90838
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/starlabs/byte_adl/cfr.c              |  1 +
 src/mainboard/starlabs/common/cfr/cfr.c            | 13 +++++++++++++
 src/mainboard/starlabs/common/include/common/cfr.h |  1 +
 src/mainboard/starlabs/lite/cfr.c                  |  1 +
 src/mainboard/starlabs/starbook/cfr.c              |  1 +
 src/mainboard/starlabs/starfighter/cfr.c           |  1 +
 src/mainboard/starlabs/starlite_adl/cfr.c          |  1 +
 7 files changed, 19 insertions(+)

diff --git a/src/mainboard/starlabs/byte_adl/cfr.c b/src/mainboard/starlabs/byte_adl/cfr.c
index 3a9162d1cb..9936025c25 100644
--- a/src/mainboard/starlabs/byte_adl/cfr.c
+++ b/src/mainboard/starlabs/byte_adl/cfr.c
@@ -77,5 +77,6 @@ static struct sm_obj_form *sm_root[] = {
 
 void mb_cfr_setup_menu(struct lb_cfr *cfr_root)
 {
+	starlabs_cfr_register_overrides();
 	cfr_write_setup_menu(cfr_root, sm_root);
 }
diff --git a/src/mainboard/starlabs/common/cfr/cfr.c b/src/mainboard/starlabs/common/cfr/cfr.c
index 78a41814e5..70899d21b1 100644
--- a/src/mainboard/starlabs/common/cfr/cfr.c
+++ b/src/mainboard/starlabs/common/cfr/cfr.c
@@ -1,9 +1,22 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
 #include <drivers/option/cfr_frontend.h>
+#include <intelblocks/pcie_rp.h>
 #include <common/cfr.h>
 
 void __weak cfr_card_reader_update(struct sm_object *new_obj)
 {
 	(void)new_obj;
 }
+
+static const struct cfr_default_override starlabs_cfr_overrides[] = {
+	CFR_OVERRIDE_ENUM("pciexp_aspm", ASPM_L0S_L1),
+	CFR_OVERRIDE_END
+};
+
+void starlabs_cfr_register_overrides(void)
+{
+	if (!CONFIG(DRIVERS_OPTION_CFR))
+		return;
+	cfr_register_overrides(starlabs_cfr_overrides);
+}
diff --git a/src/mainboard/starlabs/common/include/common/cfr.h b/src/mainboard/starlabs/common/include/common/cfr.h
index 58c4ec2a8e..4613b94fbd 100644
--- a/src/mainboard/starlabs/common/include/common/cfr.h
+++ b/src/mainboard/starlabs/common/include/common/cfr.h
@@ -8,6 +8,7 @@
 #include <common/powercap.h>
 
 void cfr_card_reader_update(struct sm_object *new_obj);
+void starlabs_cfr_register_overrides(void);
 
 static const struct sm_object accelerometer = SM_DECLARE_BOOL({
 	.opt_name	= "accelerometer",
diff --git a/src/mainboard/starlabs/lite/cfr.c b/src/mainboard/starlabs/lite/cfr.c
index db3702fb79..ae1cfdbbd3 100644
--- a/src/mainboard/starlabs/lite/cfr.c
+++ b/src/mainboard/starlabs/lite/cfr.c
@@ -87,5 +87,6 @@ static struct sm_obj_form *sm_root[] = {
 
 void mb_cfr_setup_menu(struct lb_cfr *cfr_root)
 {
+	starlabs_cfr_register_overrides();
 	cfr_write_setup_menu(cfr_root, sm_root);
 }
diff --git a/src/mainboard/starlabs/starbook/cfr.c b/src/mainboard/starlabs/starbook/cfr.c
index a499d3ed08..ab5f84e663 100644
--- a/src/mainboard/starlabs/starbook/cfr.c
+++ b/src/mainboard/starlabs/starbook/cfr.c
@@ -124,5 +124,6 @@ static struct sm_obj_form *sm_root[] = {
 
 void mb_cfr_setup_menu(struct lb_cfr *cfr_root)
 {
+	starlabs_cfr_register_overrides();
 	cfr_write_setup_menu(cfr_root, sm_root);
 }
diff --git a/src/mainboard/starlabs/starfighter/cfr.c b/src/mainboard/starlabs/starfighter/cfr.c
index 146ffd6913..01488d4865 100644
--- a/src/mainboard/starlabs/starfighter/cfr.c
+++ b/src/mainboard/starlabs/starfighter/cfr.c
@@ -109,5 +109,6 @@ static struct sm_obj_form *sm_root[] = {
 
 void mb_cfr_setup_menu(struct lb_cfr *cfr_root)
 {
+	starlabs_cfr_register_overrides();
 	cfr_write_setup_menu(cfr_root, sm_root);
 }
diff --git a/src/mainboard/starlabs/starlite_adl/cfr.c b/src/mainboard/starlabs/starlite_adl/cfr.c
index 7bbe25d61f..6416dc4a77 100644
--- a/src/mainboard/starlabs/starlite_adl/cfr.c
+++ b/src/mainboard/starlabs/starlite_adl/cfr.c
@@ -107,5 +107,6 @@ static struct sm_obj_form *sm_root[] = {
 
 void mb_cfr_setup_menu(struct lb_cfr *cfr_root)
 {
+	starlabs_cfr_register_overrides();
 	cfr_write_setup_menu(cfr_root, sm_root);
 }

From 5ad87a4de9f98dd1ccf981c1dbc0abba0ec56a13 Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Wed, 5 Nov 2025 09:48:45 +0000
Subject: [PATCH 3095/3886] soc/intel/{adl,mtl,ptl): Hook Intel TME up to the
 option table

This makes it runtime configurable; disabling it can save around
100ms boot time.

Change-Id: I9cddb07fc2e7caf754fa8d665249536c4885a4fe
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89918
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/soc/intel/alderlake/cpu.c                  |  3 ++-
 src/soc/intel/alderlake/romstage/fsp_params.c  |  2 +-
 .../common/block/include/intelblocks/cfr.h     | 18 ++++++++++++++++++
 src/soc/intel/meteorlake/cpu.c                 |  3 ++-
 src/soc/intel/meteorlake/romstage/fsp_params.c |  2 +-
 src/soc/intel/pantherlake/cpu.c                |  3 ++-
 .../intel/pantherlake/romstage/fsp_params.c    |  3 ++-
 src/soc/intel/tigerlake/romstage/fsp_params.c  |  2 +-
 8 files changed, 29 insertions(+), 7 deletions(-)

diff --git a/src/soc/intel/alderlake/cpu.c b/src/soc/intel/alderlake/cpu.c
index c2efff3419..615bd43c31 100644
--- a/src/soc/intel/alderlake/cpu.c
+++ b/src/soc/intel/alderlake/cpu.c
@@ -20,6 +20,7 @@
 #include <intelblocks/mp_init.h>
 #include <intelblocks/msr.h>
 #include <intelblocks/acpi.h>
+#include <option.h>
 #include <soc/cpu.h>
 #include <soc/msr.h>
 #include <soc/pci_devs.h>
@@ -140,7 +141,7 @@ void soc_core_init(struct device *cpu)
 	/* Enable Turbo */
 	enable_turbo();
 
-	if (CONFIG(INTEL_TME) && is_tme_supported())
+	if (get_uint_option("intel_tme", CONFIG(INTEL_TME)) && is_tme_supported())
 		set_tme_core_activate();
 }
 
diff --git a/src/soc/intel/alderlake/romstage/fsp_params.c b/src/soc/intel/alderlake/romstage/fsp_params.c
index 4bb2980b2b..d6224658ae 100644
--- a/src/soc/intel/alderlake/romstage/fsp_params.c
+++ b/src/soc/intel/alderlake/romstage/fsp_params.c
@@ -226,7 +226,7 @@ static void fill_fspm_security_params(FSP_M_CONFIG *m_cfg,
 {
 	/* Disable BIOS Guard */
 	m_cfg->BiosGuard = 0;
-	m_cfg->TmeEnable = CONFIG(INTEL_TME) && is_tme_supported();
+	m_cfg->TmeEnable = get_uint_option("intel_tme", CONFIG(INTEL_TME)) && is_tme_supported();
 }
 
 static void fill_fspm_uart_params(FSP_M_CONFIG *m_cfg,
diff --git a/src/soc/intel/common/block/include/intelblocks/cfr.h b/src/soc/intel/common/block/include/intelblocks/cfr.h
index 7828e1f359..15dcacab23 100644
--- a/src/soc/intel/common/block/include/intelblocks/cfr.h
+++ b/src/soc/intel/common/block/include/intelblocks/cfr.h
@@ -8,6 +8,7 @@
 #define SOC_INTEL_CMN_CFR_H
 
 #include <drivers/option/cfr_frontend.h>
+#include <cpu/intel/common/common.h>
 #include <intelblocks/pcie_rp.h>
 #include <intelblocks/pmclib.h>
 
@@ -133,4 +134,21 @@ static const struct sm_object pciexp_speed = SM_DECLARE_ENUM({
 				SM_ENUM_VALUE_END		},
 });
 
+/* TME */
+static void update_intel_tme(struct sm_object *new)
+{
+	if (!is_tme_supported())
+		new->sm_bool.flags |= CFR_OPTFLAG_SUPPRESS;
+}
+
+static const struct sm_object intel_tme = SM_DECLARE_BOOL({
+	.opt_name	= "intel_tme",
+	.ui_name	= "Total Memory Encryption",
+	.ui_helptext	= "Enable TME (Total Memory Encryption). When enabled, all data stored in"
+			  " system memory is encrypted to prevent unauthorized access or data theft."
+			  " Disabling TME decreases boot time by around 100ms",
+	.default_value	= CONFIG(INTEL_TME),
+}, WITH_CALLBACK(update_intel_tme));
+
+
 #endif /* SOC_INTEL_CMN_CFR_H */
diff --git a/src/soc/intel/meteorlake/cpu.c b/src/soc/intel/meteorlake/cpu.c
index b4854cb6ef..05fe9a9756 100644
--- a/src/soc/intel/meteorlake/cpu.c
+++ b/src/soc/intel/meteorlake/cpu.c
@@ -15,6 +15,7 @@
 #include <intelblocks/cpulib.h>
 #include <intelblocks/mp_init.h>
 #include <intelblocks/msr.h>
+#include <option.h>
 #include <soc/cpu.h>
 #include <soc/msr.h>
 #include <soc/pci_devs.h>
@@ -142,7 +143,7 @@ void soc_core_init(struct device *cpu)
 	/* Set core type in struct cpu_info */
 	set_dev_core_type();
 
-	if (CONFIG(INTEL_TME) && is_tme_supported())
+	if (get_uint_option("intel_tme", CONFIG(INTEL_TME)) && is_tme_supported())
 		set_tme_core_activate();
 
 	if (CONFIG(DROP_CPU_FEATURE_PROGRAM_IN_FSP)) {
diff --git a/src/soc/intel/meteorlake/romstage/fsp_params.c b/src/soc/intel/meteorlake/romstage/fsp_params.c
index cec8304281..d6c0b04782 100644
--- a/src/soc/intel/meteorlake/romstage/fsp_params.c
+++ b/src/soc/intel/meteorlake/romstage/fsp_params.c
@@ -198,7 +198,7 @@ static void fill_fspm_cpu_params(FSP_M_CONFIG *m_cfg,
 
 static void fill_tme_params(FSP_M_CONFIG *m_cfg)
 {
-	m_cfg->TmeEnable = CONFIG(INTEL_TME) && is_tme_supported();
+	m_cfg->TmeEnable = get_uint_option("intel_tme", CONFIG(INTEL_TME)) && is_tme_supported();
 	if (!m_cfg->TmeEnable || acpi_is_wakeup_s3())
 		return;
 	m_cfg->GenerateNewTmeKey = CONFIG(TME_KEY_REGENERATION_ON_WARM_BOOT) &&
diff --git a/src/soc/intel/pantherlake/cpu.c b/src/soc/intel/pantherlake/cpu.c
index f821507749..40b216d697 100644
--- a/src/soc/intel/pantherlake/cpu.c
+++ b/src/soc/intel/pantherlake/cpu.c
@@ -16,6 +16,7 @@
 #include <intelblocks/mp_init.h>
 #include <intelblocks/msr.h>
 #include <intelblocks/pmclib.h>
+#include <option.h>
 #include <smbios.h>
 #include <soc/cpu.h>
 #include <soc/msr.h>
@@ -141,7 +142,7 @@ void soc_core_init(struct device *cpu)
 	/* Set core type in struct cpu_info */
 	set_dev_core_type();
 
-	if (CONFIG(INTEL_TME) && is_tme_supported())
+	if (get_uint_option("intel_tme", CONFIG(INTEL_TME)) && is_tme_supported())
 		set_tme_core_activate();
 
 	if (CONFIG(DROP_CPU_FEATURE_PROGRAM_IN_FSP)) {
diff --git a/src/soc/intel/pantherlake/romstage/fsp_params.c b/src/soc/intel/pantherlake/romstage/fsp_params.c
index 46458af5ce..5ec92bb80f 100644
--- a/src/soc/intel/pantherlake/romstage/fsp_params.c
+++ b/src/soc/intel/pantherlake/romstage/fsp_params.c
@@ -10,6 +10,7 @@
 #include <fsp/util.h>
 #include <intelbasecode/ramtop.h>
 #include <intelblocks/cpulib.h>
+#include <option.h>
 #include <soc/iomap.h>
 #include <soc/msr.h>
 #include <soc/pcie.h>
@@ -112,7 +113,7 @@ static void fill_fspm_cpu_params(FSP_M_CONFIG *m_cfg,
 
 static void fill_tme_params(FSP_M_CONFIG *m_cfg)
 {
-	m_cfg->TmeEnable = CONFIG(INTEL_TME) && is_tme_supported();
+	m_cfg->TmeEnable = get_uint_option("intel_tme", CONFIG(INTEL_TME)) && is_tme_supported();
 	if (!m_cfg->TmeEnable || acpi_is_wakeup_s3())
 		return;
 	m_cfg->GenerateNewTmeKey = CONFIG(TME_KEY_REGENERATION_ON_WARM_BOOT);
diff --git a/src/soc/intel/tigerlake/romstage/fsp_params.c b/src/soc/intel/tigerlake/romstage/fsp_params.c
index 0f6c80cfec..6f8c5eb9e6 100644
--- a/src/soc/intel/tigerlake/romstage/fsp_params.c
+++ b/src/soc/intel/tigerlake/romstage/fsp_params.c
@@ -220,7 +220,7 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg,
 			m_cfg->CpuPcieRpEnableMask |= 1 << i;
 	}
 
-	m_cfg->TmeEnable = CONFIG(INTEL_TME) && is_tme_supported();
+	m_cfg->TmeEnable = get_uint_option("intel_tme", CONFIG(INTEL_TME)) && is_tme_supported();
 
 	/* crashLog config */
 	m_cfg->CpuCrashLogDevice = CONFIG(SOC_INTEL_CRASHLOG) && is_devfn_enabled(SA_DEVFN_TMT);

From 90c1d8654c4a70a5dcf1e7203ffc309f75fa4d7d Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Wed, 5 Nov 2025 10:01:42 +0000
Subject: [PATCH 3096/3886] mb/starlabs/*: Expose TME CFR option

Change-Id: I806b8af593626dc3125435ba56ce18dfcd7f6946
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89920
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
---
 src/mainboard/starlabs/byte_adl/cfr.c     | 10 ++++++++++
 src/mainboard/starlabs/lite/cfr.c         | 10 ++++++++++
 src/mainboard/starlabs/starbook/cfr.c     |  9 +++++++++
 src/mainboard/starlabs/starfighter/cfr.c  |  9 +++++++++
 src/mainboard/starlabs/starlite_adl/cfr.c |  9 +++++++++
 5 files changed, 47 insertions(+)

diff --git a/src/mainboard/starlabs/byte_adl/cfr.c b/src/mainboard/starlabs/byte_adl/cfr.c
index 9936025c25..e80108ba42 100644
--- a/src/mainboard/starlabs/byte_adl/cfr.c
+++ b/src/mainboard/starlabs/byte_adl/cfr.c
@@ -47,6 +47,15 @@ static struct sm_obj_form devices_group = {
 	},
 };
 
+static struct sm_obj_form security_group = {
+	.ui_name = "Security",
+	.obj_list = (const struct sm_object *[]) {
+		&intel_tme,
+		NULL
+	},
+};
+
+
 static struct sm_obj_form pci_group = {
 	.ui_name = "PCI",
 	.obj_list = (const struct sm_object *[]) {
@@ -70,6 +79,7 @@ static struct sm_obj_form *sm_root[] = {
 	&processor_group,
 	&power_group,
 	&devices_group,
+	&security_group,
 	&pci_group,
 	&coreboot_group,
 	NULL
diff --git a/src/mainboard/starlabs/lite/cfr.c b/src/mainboard/starlabs/lite/cfr.c
index ae1cfdbbd3..81d236ea86 100644
--- a/src/mainboard/starlabs/lite/cfr.c
+++ b/src/mainboard/starlabs/lite/cfr.c
@@ -54,6 +54,15 @@ static struct sm_obj_form devices_group = {
 	},
 };
 
+static struct sm_obj_form security_group = {
+	.ui_name = "Security",
+	.obj_list = (const struct sm_object *[]) {
+		&intel_tme,
+		NULL
+	},
+};
+
+
 static struct sm_obj_form pci_group = {
 	.ui_name = "PCI",
 	.obj_list = (const struct sm_object *[]) {
@@ -80,6 +89,7 @@ static struct sm_obj_form *sm_root[] = {
 	&power_group,
 	&keyboard_group,
 	&devices_group,
+	&security_group,
 	&pci_group,
 	&coreboot_group,
 	NULL
diff --git a/src/mainboard/starlabs/starbook/cfr.c b/src/mainboard/starlabs/starbook/cfr.c
index ab5f84e663..d317d2e531 100644
--- a/src/mainboard/starlabs/starbook/cfr.c
+++ b/src/mainboard/starlabs/starbook/cfr.c
@@ -84,6 +84,14 @@ static struct sm_obj_form devices_group = {
 	},
 };
 
+static struct sm_obj_form security_group = {
+	.ui_name = "Security",
+	.obj_list = (const struct sm_object *[]) {
+		&intel_tme,
+		NULL
+	},
+};
+
 static struct sm_obj_form pci_group = {
 	.ui_name = "PCI",
 	.obj_list = (const struct sm_object *[]) {
@@ -117,6 +125,7 @@ static struct sm_obj_form *sm_root[] = {
 	&power_group,
 	&keyboard_group,
 	&devices_group,
+	&security_group,
 	&pci_group,
 	&coreboot_group,
 	NULL
diff --git a/src/mainboard/starlabs/starfighter/cfr.c b/src/mainboard/starlabs/starfighter/cfr.c
index 01488d4865..e925fa731c 100644
--- a/src/mainboard/starlabs/starfighter/cfr.c
+++ b/src/mainboard/starlabs/starfighter/cfr.c
@@ -73,6 +73,14 @@ static struct sm_obj_form devices_group = {
 	},
 };
 
+static struct sm_obj_form security_group = {
+	.ui_name = "Security",
+	.obj_list = (const struct sm_object *[]) {
+		&intel_tme,
+		NULL
+	},
+};
+
 static struct sm_obj_form pci_group = {
 	.ui_name = "PCI",
 	.obj_list = (const struct sm_object *[]) {
@@ -102,6 +110,7 @@ static struct sm_obj_form *sm_root[] = {
 	&power_group,
 	&keyboard_group,
 	&devices_group,
+	&security_group,
 	&pci_group,
 	&coreboot_group,
 	NULL
diff --git a/src/mainboard/starlabs/starlite_adl/cfr.c b/src/mainboard/starlabs/starlite_adl/cfr.c
index 6416dc4a77..62370cfc2d 100644
--- a/src/mainboard/starlabs/starlite_adl/cfr.c
+++ b/src/mainboard/starlabs/starlite_adl/cfr.c
@@ -75,6 +75,14 @@ static struct sm_obj_form devices_group = {
 	},
 };
 
+static struct sm_obj_form security_group = {
+	.ui_name = "Security",
+	.obj_list = (const struct sm_object *[]) {
+		&intel_tme,
+		NULL
+	},
+};
+
 static struct sm_obj_form pci_group = {
 	.ui_name = "PCI",
 	.obj_list = (const struct sm_object *[]) {
@@ -100,6 +108,7 @@ static struct sm_obj_form *sm_root[] = {
 	&processor_group,
 	&power_group,
 	&devices_group,
+	&security_group,
 	&pci_group,
 	&coreboot_group,
 	NULL

From d216ea151c1b14a2d7ce74dc5a65ca7895188d91 Mon Sep 17 00:00:00 2001
From: Subrata Banik <subratabanik@google.com>
Date: Mon, 19 Jan 2026 10:44:30 +0530
Subject: [PATCH 3097/3886] mb/google/bluey: Change ADSP I2C transfer mode to
 MIXED

Update QUPV3_2_SE4 (ADSP I2C) configuration to use MIXED mode
instead of GSI. This allows the I2C controller for the charger
and fuel gauge to handle both GSI (DMA) and non-GSI transfers,
ensuring better compatibility during different boot stages.

BUG=b:472358270
BRANCH=None
TEST=TBD.

Change-Id: Ie2ed3cd6991c3d98b7902c1331e68ec5a4f35d92
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90796
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jayvik Desai <jayvik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
---
 src/mainboard/google/bluey/mainboard.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/mainboard/google/bluey/mainboard.c b/src/mainboard/google/bluey/mainboard.c
index 6551976f55..ea0e8a4851 100644
--- a/src/mainboard/google/bluey/mainboard.c
+++ b/src/mainboard/google/bluey/mainboard.c
@@ -171,7 +171,7 @@ static void mainboard_init(struct device *dev)
 	qupv3_se_fw_load_and_init(QUPV3_0_SE0, SE_PROTOCOL_I2C, MIXED); /* Trackpad I2C */
 
 	/* ADSP I2C (Charger/Fuel gauge) */
-	qupv3_se_fw_load_and_init(QUPV3_2_SE4, SE_PROTOCOL_I2C, GSI);
+	qupv3_se_fw_load_and_init(QUPV3_2_SE4, SE_PROTOCOL_I2C, MIXED);
 
 
 	if (CONFIG(MAINBOARD_HAS_PS8820_RETIMER)) {

From a7a627d8f50ac9b9428a4183377babf6ebd77289 Mon Sep 17 00:00:00 2001
From: Subrata Banik <subratabanik@google.com>
Date: Tue, 20 Jan 2026 16:19:18 +0530
Subject: [PATCH 3098/3886] ec/google/chromeec: Add helper to set LED RGB
 colors

This patch adds google_chromeec_set_lightbar_rgb() to allow mainboards
to manually control the individual LED colors. This is useful for
providing visual feedback during early boot or platform-specific
events, such as low-battery warnings.

TEST=Build and boot google/fatcat.

Change-Id: I146006511ea727787ea496b0674b67fa950ce8f2
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90807
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
---
 src/ec/google/chromeec/ec.c | 36 ++++++++++++++++++++++++++++++++++++
 src/ec/google/chromeec/ec.h | 16 ++++++++++++++++
 2 files changed, 52 insertions(+)

diff --git a/src/ec/google/chromeec/ec.c b/src/ec/google/chromeec/ec.c
index ee04d4a669..b9d53e7788 100644
--- a/src/ec/google/chromeec/ec.c
+++ b/src/ec/google/chromeec/ec.c
@@ -1945,3 +1945,39 @@ int google_chromeec_read_batt_state_of_charge(uint32_t *state)
 
 	return ret;
 }
+
+/*
+ * Set the RGB color of a specific LED on the Lightbar.
+ *
+ * This function communicates with the Embedded Controller (EC)
+ * to update the color of an individual LED.
+ *
+ * led: The index of the LED to be updated.
+ * red: Red intensity value (0x00 - 0xff).
+ * green: Green intensity value (0x00 - 0xff).
+ * blue: Blue intensity value (0x00 - 0xff).
+ * Return: 0 on success, or a non-zero error code from the EC host command.
+ */
+int google_chromeec_set_lightbar_rgb(unsigned int led, int red, int green,
+			 int blue)
+{
+	const struct ec_params_lightbar req = {
+		.cmd = LIGHTBAR_CMD_SET_RGB,
+		.set_rgb = {
+			.led   = led,
+			.red   = red,
+			.green = green,
+			.blue  = blue
+		}
+	};
+
+	struct chromeec_command cmd = {
+		.cmd_code = EC_CMD_LIGHTBAR_CMD,
+		.cmd_size_out = 0,
+		.cmd_data_out = NULL,
+		.cmd_size_in = sizeof(req),
+		.cmd_data_in = &req,
+	};
+
+	return google_chromeec_command(&cmd);
+}
diff --git a/src/ec/google/chromeec/ec.h b/src/ec/google/chromeec/ec.h
index e4120dabeb..e5a4b0647d 100644
--- a/src/ec/google/chromeec/ec.h
+++ b/src/ec/google/chromeec/ec.h
@@ -546,4 +546,20 @@ void chipset_ioport_range(uint16_t *base, size_t *size);
  */
 int google_chromeec_read_batt_state_of_charge(uint32_t *state);
 
+/*
+ * Set the RGB color of a specific LED on the Lightbar.
+ *
+ * This function communicates with the Embedded Controller (EC)
+ * to update the color of an individual LED.
+ *
+ * @param led: The index of the LED to be updated.
+ * @param red: Red intensity value (0x00 - 0xff).
+ * @param green: Green intensity value (0x00 - 0xff).
+ * @param blue: Blue intensity value (0x00 - 0xff).
+ *
+ * @return 0 on success, or a non-zero error code from the EC host command.
+ */
+int google_chromeec_set_lightbar_rgb(unsigned int led, int red, int green,
+			 int blue);
+
 #endif /* _EC_GOOGLE_CHROMEEC_EC_H */

From e8e3fc9cf7dcf71e9f6ffe701176167268c2aa2a Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Micha=C5=82=20=C5=BBygowski?= <michal.zygowski@3mdeb.com>
Date: Thu, 4 Dec 2025 15:36:43 +0100
Subject: [PATCH 3099/3886] vendorcode/amd/opensil/turin_poc: Add turin_poc as
 a copy of genoa_poc
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Add a copy of genoa_poc OpenSIL directory with all genoa occurrences
changed to turin. Submodule has been omitted. Adjustment for Turin
OpenSIL will be made in subsequent patch.

Change-Id: I71e3b85f162971d6497783d4631a33780dc0e560
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90369
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 .../amd/opensil/turin_poc/Makefile.mk         |  18 ++
 src/vendorcode/amd/opensil/turin_poc/acpi.c   |  24 +++
 src/vendorcode/amd/opensil/turin_poc/filter.h |  23 ++
 src/vendorcode/amd/opensil/turin_poc/memmap.c |  57 +++++
 .../opensil/turin_poc/meson_cross.template    |  35 +++
 .../amd/opensil/turin_poc/mpio/Makefile.mk    |   5 +
 .../amd/opensil/turin_poc/mpio/chip.c         | 202 ++++++++++++++++++
 .../amd/opensil/turin_poc/mpio/chip.h         |  71 ++++++
 .../opensil/turin_poc/opensil_config.template |   5 +
 .../amd/opensil/turin_poc/opensil_console.c   |  44 ++++
 .../amd/opensil/turin_poc/opensil_console.h   |   9 +
 .../amd/opensil/turin_poc/ramstage.c          | 180 ++++++++++++++++
 .../amd/opensil/turin_poc/romstage.c          |  17 ++
 13 files changed, 690 insertions(+)
 create mode 100644 src/vendorcode/amd/opensil/turin_poc/Makefile.mk
 create mode 100644 src/vendorcode/amd/opensil/turin_poc/acpi.c
 create mode 100644 src/vendorcode/amd/opensil/turin_poc/filter.h
 create mode 100644 src/vendorcode/amd/opensil/turin_poc/memmap.c
 create mode 100644 src/vendorcode/amd/opensil/turin_poc/meson_cross.template
 create mode 100644 src/vendorcode/amd/opensil/turin_poc/mpio/Makefile.mk
 create mode 100644 src/vendorcode/amd/opensil/turin_poc/mpio/chip.c
 create mode 100644 src/vendorcode/amd/opensil/turin_poc/mpio/chip.h
 create mode 100644 src/vendorcode/amd/opensil/turin_poc/opensil_config.template
 create mode 100644 src/vendorcode/amd/opensil/turin_poc/opensil_console.c
 create mode 100644 src/vendorcode/amd/opensil/turin_poc/opensil_console.h
 create mode 100644 src/vendorcode/amd/opensil/turin_poc/ramstage.c
 create mode 100644 src/vendorcode/amd/opensil/turin_poc/romstage.c

diff --git a/src/vendorcode/amd/opensil/turin_poc/Makefile.mk b/src/vendorcode/amd/opensil/turin_poc/Makefile.mk
new file mode 100644
index 0000000000..62bd00bf91
--- /dev/null
+++ b/src/vendorcode/amd/opensil/turin_poc/Makefile.mk
@@ -0,0 +1,18 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
+subdirs-y += mpio
+
+CPPFLAGS_common += -I$(opensil_dir)/Include -I$(opensil_dir)/xUSL -I$(opensil_dir)/xUSL/Include -I$(opensil_dir)/xUSL/FCH -I$(opensil_dir)/xUSL/FCH/Common -I$(opensil_dir)/xSIM -I$(opensil_dir)/xPRF
+
+romstage-y += opensil_console.c
+romstage-y += romstage.c
+
+ramstage-y += acpi.c
+ramstage-y += memmap.c
+ramstage-y += opensil_console.c
+ramstage-y += ramstage.c
+
+$(obj)/romstage/vendorcode/amd/opensil/turin_poc/opensil_console.o: CFLAGS_romstage += -D_MSC_EXTENSIONS=0 -DHAS_STRING_H=1 -Wno-unknown-pragmas
+$(obj)/romstage/vendorcode/amd/opensil/turin_poc/romstage.o: CFLAGS_romstage += -D_MSC_EXTENSIONS=0 -DHAS_STRING_H=1 -Wno-unknown-pragmas
+
+$(obj)/ramstage/vendorcode/amd/opensil/turin_poc/opensil_console.o: CFLAGS_ramstage += -D_MSC_EXTENSIONS=0 -DHAS_STRING_H=1 -Wno-unknown-pragmas
diff --git a/src/vendorcode/amd/opensil/turin_poc/acpi.c b/src/vendorcode/amd/opensil/turin_poc/acpi.c
new file mode 100644
index 0000000000..fcdf167c12
--- /dev/null
+++ b/src/vendorcode/amd/opensil/turin_poc/acpi.c
@@ -0,0 +1,24 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <acpi/acpi.h>
+#include <Sil-api.h>
+#include <SilCommon.h>
+#include <xSIM-api.h>
+#include <FCH/Common/FchCommonCfg.h>
+
+#include "../opensil.h"
+
+void opensil_fill_fadt(acpi_fadt_t *fadt)
+{
+	FCHHWACPI_INPUT_BLK *blk = SilFindStructure(SilId_FchHwAcpiP,  0);
+
+	fadt->pm1a_evt_blk = blk->AcpiPm1EvtBlkAddr;
+	fadt->pm1a_cnt_blk = blk->AcpiPm1CntBlkAddr;
+	fadt->pm_tmr_blk = blk->AcpiPmTmrBlkAddr;
+	fadt->gpe0_blk = blk->AcpiGpe0BlkAddr;
+}
+
+unsigned long add_opensil_acpi_table(unsigned long current, acpi_rsdp_t *rsdp)
+{
+	return current;
+}
diff --git a/src/vendorcode/amd/opensil/turin_poc/filter.h b/src/vendorcode/amd/opensil/turin_poc/filter.h
new file mode 100644
index 0000000000..f0817f7502
--- /dev/null
+++ b/src/vendorcode/amd/opensil/turin_poc/filter.h
@@ -0,0 +1,23 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+/* Keep this in sync with openSIL SilCommon.h file */
+#define DEBUG_FILTER_APOB       0x00000001UL
+#define DEBUG_FILTER_NBIO       0x00000002UL
+#define DEBUG_FILTER_CCX        0x00000004UL
+#define DEBUG_FILTER_SMU        0x00000008UL
+#define DEBUG_FILTER_DF         0x00000010UL
+#define DEBUG_FILTER_MEM        0x00000040UL
+#define DEBUG_FILTER_FCH        0x00000080UL
+#define DEBUG_FILTER_RAS        0x00000100UL
+
+#define SIL_DEBUG(topic) (CONFIG(OPENSIL_DEBUG_##topic) ? DEBUG_FILTER_##topic : 0)
+
+#define SIL_DEBUG_MODULE_FILTER ( \
+	  SIL_DEBUG(APOB) | \
+	  SIL_DEBUG(NBIO) | \
+	  SIL_DEBUG(CCX) | \
+	  SIL_DEBUG(SMU) | \
+	  SIL_DEBUG(DF) | \
+	  SIL_DEBUG(MEM) | \
+	  SIL_DEBUG(FCH) | \
+	  SIL_DEBUG(RAS) )
diff --git a/src/vendorcode/amd/opensil/turin_poc/memmap.c b/src/vendorcode/amd/opensil/turin_poc/memmap.c
new file mode 100644
index 0000000000..eed1be7e5f
--- /dev/null
+++ b/src/vendorcode/amd/opensil/turin_poc/memmap.c
@@ -0,0 +1,57 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <SilCommon.h>
+#include <Sil-api.h> // needed above ApobCmn.h
+#include <ApobCmn.h>
+#include <xPRF-api.h>
+
+#include "../opensil.h"
+
+_Static_assert(sizeof(uint32_t) == sizeof(((MEMORY_HOLE_DESCRIPTOR){0}).Type),
+	"Unexpected size of MEMORY_HOLE_TYPES in the MEMORY_HOLE_DESCRIPTOR "
+	"struct which doesn't match the code in drivers/amd/opensil/memmap.c");
+
+const char *opensil_get_hole_info_type(uint32_t type)
+{
+	const struct hole_type {
+		MEMORY_HOLE_TYPES type;
+		const char *string;
+	} types[] = {
+		{UMA, "UMA"},
+		{MMIO, "MMIO"},
+		{PrivilegedDRAM, "PrivilegedDRAM"},
+		{Reserved1TbRemap, "Reserved1TbRemap"},
+		{ReservedSLink, "ReservedSLink"},
+		{ReservedSLinkAlignment, "ReservedSLinkAlignment"},
+		{ReservedDrtm, "ReservedDrtm"},
+		{ReservedCvip, "ReservedCvip"},
+		{ReservedSmuFeatures, "ReservedSmuFeatures"},
+		{ReservedFwtpm, "ReservedFwtpm"},
+		{ReservedMpioC20, "ReservedMpioC20"},
+		{ReservedNbif, "ReservedNbif"},
+		{ReservedCxl, "ReservedCxl"},
+		{ReservedCxlAlignment, "ReservedCxlAlignment"},
+		{ReservedCpuTmr, "ReservedCpuTmr"},
+		{ReservedRasEinj, "ReservedRasEinj"},
+		{MaxMemoryHoleTypes, "MaxMemoryHoleTypes"},
+	};
+
+	int i;
+	MEMORY_HOLE_TYPES enum_type = (MEMORY_HOLE_TYPES)type; // Cast int to enum
+	for (i = 0; i < ARRAY_SIZE(types); i++)
+		if (enum_type == types[i].type)
+			return types[i].string;
+	return "Unknown type";
+}
+
+void opensil_get_hole_info(uint32_t *n_holes, uint64_t *top_of_mem, void **hole_info)
+{
+        SIL_STATUS status = xPrfGetSystemMemoryMap(n_holes, top_of_mem, hole_info);
+	SIL_STATUS_report("xPrfGetSystemMemoryMap", status);
+	// Make sure hole_info does not get initialized to something odd by xPRF on failure
+	if (status != SilPass) {
+		*hole_info = NULL;
+		*n_holes = 0;
+		*top_of_mem = 0;
+	}
+}
diff --git a/src/vendorcode/amd/opensil/turin_poc/meson_cross.template b/src/vendorcode/amd/opensil/turin_poc/meson_cross.template
new file mode 100644
index 0000000000..6473b65225
--- /dev/null
+++ b/src/vendorcode/amd/opensil/turin_poc/meson_cross.template
@@ -0,0 +1,35 @@
+[binaries]
+c = '##COMPILER##'
+ar = '##AR##'
+nasm = '##NASM##'
+
+[built-in options]
+c_args = ['-nostdinc',
+          '-I##OBJPATH##',
+          '-I##COREBOOT_DIR##/src/include',
+          '-I##COREBOOT_DIR##/src/arch/x86/include',
+          '-I##COREBOOT_DIR##/src/commonlib/include',
+          '-I##COREBOOT_DIR##/src/commonlib/bsd/include',
+          '-include', '##COREBOOT_DIR##/src/include/kconfig.h',
+          '-include', '##OBJPATH##/config.h',
+          '-include', '##COREBOOT_DIR##/src/commonlib/bsd/include/commonlib/bsd/compiler.h',
+          '-include', '##OPENSIL_DIR##/../filter.h',
+          '-DHAS_STRING_H=1',
+          # openSIL isn't compatible with coreboot's assert implementation, so use special case
+          '-D_PORTING_H_=1',
+          '-DSIL_DEBUG_ENABLE=##SIL_DEBUG_ENABLE##',
+          # openSIL uses coreboot assert which uses printk which warns about unused-param
+          '-Wno-unused-parameter',
+          # ubiquitous problem in openSIL
+          '-Wno-missing-field-initializers',
+          ##CLANG_ARGS##
+         ]
+
+[host_machine]
+system = 'linux'
+cpu_family = '##CPU_FAMILY##'
+cpu = '##CPU##'
+endian = 'little'
+
+[properties]
+is32bit = ##IS32BIT##
diff --git a/src/vendorcode/amd/opensil/turin_poc/mpio/Makefile.mk b/src/vendorcode/amd/opensil/turin_poc/mpio/Makefile.mk
new file mode 100644
index 0000000000..fafdc5935f
--- /dev/null
+++ b/src/vendorcode/amd/opensil/turin_poc/mpio/Makefile.mk
@@ -0,0 +1,5 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
+ramstage-y += chip.c
+
+$(obj)/ramstage/vendorcode/amd/opensil/turin_poc/mpio/chip.o: CFLAGS_ramstage += -D_MSC_EXTENSIONS=0 -DHAS_STRING_H=1 -Wno-unknown-pragmas
diff --git a/src/vendorcode/amd/opensil/turin_poc/mpio/chip.c b/src/vendorcode/amd/opensil/turin_poc/mpio/chip.c
new file mode 100644
index 0000000000..587ab81e02
--- /dev/null
+++ b/src/vendorcode/amd/opensil/turin_poc/mpio/chip.c
@@ -0,0 +1,202 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <device/device.h>
+#include <device/pci_def.h>
+#include <Mpio/Common/MpioStructs.h>
+#include <Mpio/MpioClass-api.h>
+#include <NBIO/NbioClass-api.h>
+#include <RcMgr/DfX/RcManager4-api.h>
+#include <vendorcode/amd/opensil/opensil.h>
+#include <xSIM-api.h>
+
+#include "chip.h"
+
+static void mpio_params_config(void)
+{
+	MPIOCLASS_INPUT_BLK *mpio_data = SilFindStructure(SilId_MpioClass, 0);
+	mpio_data->CfgDxioClockGating                  = 1;
+	mpio_data->PcieDxioTimingControlEnable         = 0;
+	mpio_data->PCIELinkReceiverDetectionPolling    = 0;
+	mpio_data->PCIELinkResetToTrainingTime         = 0;
+	mpio_data->PCIELinkL0Polling                   = 0;
+	mpio_data->PCIeExactMatchEnable                = 0;
+	mpio_data->DxioPhyValid                        = 1;
+	mpio_data->DxioPhyProgramming                  = 1;
+	mpio_data->CfgSkipPspMessage                   = 1;
+	mpio_data->DxioSaveRestoreModes                = 0xff;
+	mpio_data->AmdAllowCompliance                  = 0;
+	mpio_data->AmdAllowCompliance                  = 0xff;
+	mpio_data->SrisEnableMode                      = 0xff;
+	mpio_data->SrisSkipInterval                    = 0;
+	mpio_data->SrisSkpIntervalSel                  = 1;
+	mpio_data->SrisCfgType                         = 0;
+	mpio_data->SrisAutoDetectMode                  = 0xff;
+	mpio_data->SrisAutodetectFactor                = 0;
+	mpio_data->SrisLowerSkpOsGenSup                = 0;
+	mpio_data->SrisLowerSkpOsRcvSup                = 0;
+	mpio_data->AmdCxlOnAllPorts                    = 1;
+	mpio_data->CxlCorrectableErrorLogging          = 1;
+	mpio_data->CxlUnCorrectableErrorLogging        = 1;
+	  // This is also available in Nbio. How to handle duplicate entries?
+	mpio_data->CfgAEREnable                        = 1;
+	mpio_data->CfgMcCapEnable                      = 0;
+	mpio_data->CfgRcvErrEnable                     = 0;
+	mpio_data->EarlyBmcLinkTraining                = 1;
+	mpio_data->SurpriseDownFeature                 = 1;
+	mpio_data->LcMultAutoSpdChgOnLastRateEnable    = 0;
+	mpio_data->AmdRxMarginEnabled                  = 1;
+	mpio_data->CfgPcieCVTestWA                     = 1;
+	mpio_data->CfgPcieAriSupport                   = 1;
+	mpio_data->CfgNbioCTOtoSC                      = 0;
+	mpio_data->CfgNbioCTOIgnoreError               = 1;
+	mpio_data->CfgNbioSsid                         = 0;
+	mpio_data->CfgIommuSsid                        = 0;
+	mpio_data->CfgPspccpSsid                       = 0;
+	mpio_data->CfgNtbccpSsid                       = 0;
+	mpio_data->CfgNbifF0Ssid                       = 0;
+	mpio_data->CfgNtbSsid                          = 0;
+	mpio_data->AmdPcieSubsystemDeviceID            = 0x1453;
+	mpio_data->AmdPcieSubsystemVendorID            = 0x1022;
+	mpio_data->GppAtomicOps                        = 1;
+	mpio_data->GfxAtomicOps                        = 1;
+	mpio_data->AmdNbioReportEdbErrors              = 0;
+	mpio_data->OpnSpare                            = 0;
+	mpio_data->AmdPreSilCtrl0                      = 0;
+	mpio_data->MPIOAncDataSupport                  = 1;
+	mpio_data->AfterResetDelay                     = 0;
+	mpio_data->CfgEarlyLink                        = 0;
+	mpio_data->AmdCfgExposeUnusedPciePorts         = 1; // Show all ports
+	mpio_data->CfgForcePcieGenSpeed                = 0;
+	mpio_data->CfgSataPhyTuning                    = 0;
+	mpio_data->PcieLinkComplianceModeAllPorts      = 0;
+	mpio_data->AmdMCTPEnable                       = 0;
+	mpio_data->SbrBrokenLaneAvoidanceSup           = 1;
+	mpio_data->AutoFullMarginSup                   = 1;
+	  // A getter and setter, both are needed for this PCD.
+	mpio_data->AmdPciePresetMask8GtAllPort         = 0xffffffff;
+	  // A getter and setter, both are needed for this PCD.
+	mpio_data->AmdPciePresetMask16GtAllPort        = 0xffffffff;
+	  // A getter and setter, both are needed for this PCD.
+	mpio_data->AmdPciePresetMask32GtAllPort        = 0xffffffff;
+	mpio_data->PcieLinkAspmAllPort                 = 0xff;
+
+	mpio_data->SyncHeaderByPass                    = 1;
+	mpio_data->CxlTempGen5AdvertAltPtcl            = 0;
+
+	/* TODO handle this differently on multisocket */
+	mpio_data->PcieTopologyData.PlatformData[0].Flags = DESCRIPTOR_TERMINATE_LIST;
+	mpio_data->PcieTopologyData.PlatformData[0].PciePortList = mpio_data->PcieTopologyData.PortList;
+}
+
+static void nbio_params_config(void)
+{
+	NBIOCLASS_DATA_BLOCK *nbio_data = SilFindStructure(SilId_NbioClass, 0);
+	NBIOCLASS_INPUT_BLK *input = &nbio_data->NbioInputBlk;
+	input->CfgHdAudioEnable           = false;
+	input->EsmEnableAllRootPorts      = false;
+	input->EsmTargetSpeed             = 16;
+	input->CfgRxMarginPersistenceMode = 1;
+	input->CfgDxioFrequencyVetting    = false;
+	input->CfgSkipPspMessage          = 1;
+	input->CfgEarlyTrainTwoPcieLinks  = false;
+	input->EarlyBmcLinkTraining       = true;
+	input->EdpcEnable                 = 0;
+	input->PcieAerReportMechanism     = 2;
+	input->SevSnpSupport              = false;
+}
+
+static void setup_bmc_lanes(uint8_t lane, uint8_t socket)
+{
+	DFX_RCMGR_INPUT_BLK *rc_mgr_input_block = SilFindStructure(SilId_RcManager,  0);
+	rc_mgr_input_block->BmcSocket = socket;
+	rc_mgr_input_block->EarlyBmcLinkLaneNum = lane;
+
+	NBIOCLASS_DATA_BLOCK *nbio_data = SilFindStructure(SilId_NbioClass, 0);
+	NBIOCLASS_INPUT_BLK *nbio_input = &nbio_data->NbioInputBlk;
+	nbio_input->EarlyBmcLinkSocket         = socket;
+	nbio_input->EarlyBmcLinkLaneNum        = lane;
+	nbio_input->EarlyBmcLinkDie            = 0;
+
+	MPIOCLASS_INPUT_BLK *mpio_data = SilFindStructure(SilId_MpioClass, 0);
+	mpio_data->EarlyBmcLinkSocket                  = socket;
+	mpio_data->EarlyBmcLinkLaneNum                 = lane;
+	mpio_data->EarlyBmcLinkDie                     = 0;
+}
+
+void opensil_mpio_per_device_config(struct device *dev)
+{
+	/* Cache *mpio_data from SilFindStructure */
+	static MPIOCLASS_INPUT_BLK *mpio_data = NULL;
+	if (mpio_data == NULL) {
+		mpio_data = SilFindStructure(SilId_MpioClass, 0);
+	}
+
+	static uint32_t slot_num;
+	const uint32_t domain = dev_get_domain_id(dev);
+	const uint32_t devfn = dev->path.pci.devfn;
+	const struct drivers_amd_opensil_mpio_config *const config = dev->chip_info;
+	printk(BIOS_DEBUG, "Setting MPIO port for domain 0x%x, PCI %d:%d\n",
+	       domain, PCI_SLOT(devfn), PCI_FUNC(devfn));
+
+	if (config->type == IFTYPE_UNUSED) {
+		if (is_dev_enabled(dev)) {
+			printk(BIOS_WARNING, "Unused MPIO chip, disabling PCI device.\n");
+			dev->enabled = false;
+		} else {
+			printk(BIOS_DEBUG, "Unused MPIO chip, skipping.\n");
+		}
+		return;
+	}
+
+	if (config->bmc) {
+		setup_bmc_lanes(config->start_lane, 0); // TODO support multiple sockets
+		return;
+	}
+
+	static int mpio_port = 0;
+	MPIO_PORT_DESCRIPTOR port = { .Flags = DESCRIPTOR_TERMINATE_LIST };
+	if (config->type == IFTYPE_PCIE) {
+		const MPIO_ENGINE_DATA engine_data =
+			MPIO_ENGINE_DATA_INITIALIZER(MpioPcieEngine,
+						     config->start_lane, config->end_lane,
+						     config->hotplug == HotplugDisabled ? 0 : 1,
+						     config->gpio_group);
+		port.EngineData = engine_data;
+		const MPIO_PORT_DATA port_data =
+			MPIO_PORT_DATA_INITIALIZER_PCIE(is_dev_enabled(dev) ?
+								MpioPortEnabled : MpioPortDisabled,
+							PCI_SLOT(devfn),
+							PCI_FUNC(devfn),
+							config->hotplug,
+							config->speed,
+							0, // No backup PCIe speed
+							config->aspm,
+							config->aspm_l1_1,
+							config->aspm_l1_2,
+							config->clock_pm);
+		port.Port = port_data;
+	} else if (config->type == IFTYPE_SATA) {
+		const MPIO_ENGINE_DATA engine_data =
+			MPIO_ENGINE_DATA_INITIALIZER(MpioSATAEngine,
+						     config->start_lane, config->end_lane,
+						     0, // meaningless field
+						     config->gpio_group);
+		port.EngineData = engine_data;
+		const MPIO_PORT_DATA port_data = { .PortPresent = 1 };
+		port.Port = port_data;
+
+	}
+	port.Port.AlwaysExpose = 1;
+	port.Port.SlotNum = ++slot_num;
+	mpio_data->PcieTopologyData.PortList[mpio_port] = port;
+	/* Update TERMINATE list */
+	if (mpio_port > 0)
+		mpio_data->PcieTopologyData.PortList[mpio_port - 1].Flags = 0;
+	mpio_port++;
+}
+
+void opensil_mpio_global_config(void)
+{
+	mpio_params_config();
+	nbio_params_config();
+}
diff --git a/src/vendorcode/amd/opensil/turin_poc/mpio/chip.h b/src/vendorcode/amd/opensil/turin_poc/mpio/chip.h
new file mode 100644
index 0000000000..ce5468cbde
--- /dev/null
+++ b/src/vendorcode/amd/opensil/turin_poc/mpio/chip.h
@@ -0,0 +1,71 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef OPENSIL_TURIN_POC_MPIO_CHIP_H
+#define OPENSIL_TURIN_POC_MPIO_CHIP_H
+
+#include <stdint.h>
+
+/*
+ * TURIN MPIO mapping
+ * P0 -> [0-15]
+ * G0 -> [16-31]
+ * P1 -> [32-47]
+ * G1 -> [48-63]
+ * P2 -> [64-79]
+ * G2 -> [80-95]
+ * P3 -> [96-111]
+ * G3 -> [112-127]
+ * P4 -> [128-131]
+ * P5 -> [132-136]
+ */
+
+enum mpio_type {
+	IFTYPE_UNUSED,
+	IFTYPE_PCIE,
+	IFTYPE_SATA,
+};
+
+/* Sync with PCIE_HOTPLUG_TYPE */
+enum mpio_hotplug {
+	HotplugDisabled,                             ///< Hotplug disable
+	Basic,                                       ///< Basic Hotplug
+	ServerExpress,                               ///< Server Hotplug Express Module
+	Enhanced,                                    ///< Enhanced
+	Inboard,                                     ///< Inboard
+	ServerEntSSD,                                ///< Server Hotplug Enterprise SSD
+	UBM,                                         ///< UBM Backplane
+	OCP,                                         ///< OCP NIC 3.0
+};
+
+enum pcie_link_speed {
+	MaxSupported,
+	Gen1,
+	Gen2,
+	Gen3,
+	Gen4,
+	Gen5,
+};
+
+/* Sync with PCIE_ASPM_TYPE */
+enum pcie_aspm {
+	aspm_disabled,
+	L0s,
+	L1,
+	L0sL1,
+};
+
+struct drivers_amd_opensil_mpio_config {
+	enum mpio_type type;
+	uint8_t start_lane;
+	uint8_t end_lane;
+	uint8_t gpio_group;
+	enum mpio_hotplug hotplug;
+	enum pcie_link_speed speed;
+	enum pcie_aspm aspm;
+	uint8_t aspm_l1_1 : 1;
+	uint8_t aspm_l1_2 : 1;
+	uint8_t clock_pm : 1;
+	uint8_t bmc : 1;
+};
+
+#endif /* OPENSIL_TURIN_POC_MPIO_CHIP_H */
diff --git a/src/vendorcode/amd/opensil/turin_poc/opensil_config.template b/src/vendorcode/amd/opensil/turin_poc/opensil_config.template
new file mode 100644
index 0000000000..2ddd3b4ec1
--- /dev/null
+++ b/src/vendorcode/amd/opensil/turin_poc/opensil_config.template
@@ -0,0 +1,5 @@
+CONFIG_PLAT_APOB_ADDRESS=##APOB_BASE##
+CONFIG_PSP_BIOS_BIN_BASE=##BIOS_ENTRY_BASE##
+CONFIG_PSP_BIOS_BIN_SIZE=##BIOS_ENTRY_SIZE##
+CONFIG_PLAT_NUMBER_SOCKETS=1
+CONFIG_SOC_F19M10=y
diff --git a/src/vendorcode/amd/opensil/turin_poc/opensil_console.c b/src/vendorcode/amd/opensil/turin_poc/opensil_console.c
new file mode 100644
index 0000000000..35e5eeb2b4
--- /dev/null
+++ b/src/vendorcode/amd/opensil/turin_poc/opensil_console.c
@@ -0,0 +1,44 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <stdint.h>
+#include <stdio.h>
+#include <string.h>
+#include <console/console.h>
+#include "opensil_console.h"
+#include <SilCommon.h>
+
+static int translate_opensil_debug_level(size_t MsgLevel)
+{
+	switch (MsgLevel) {
+	case SIL_TRACE_ERROR:
+		return BIOS_ERR;
+	case SIL_TRACE_WARNING:
+		return BIOS_WARNING;
+	case SIL_TRACE_ENTRY:
+	case SIL_TRACE_EXIT:
+		return BIOS_SPEW;
+	case SIL_TRACE_INFO:
+		return BIOS_DEBUG;
+	default:
+		return BIOS_NEVER;
+	}
+}
+
+void HostDebugService(size_t MsgLevel, const char *SilPrefix, const char *Message,
+				 const char *Function, size_t Line, ...)
+{
+	if (!CONFIG(OPENSIL_DEBUG_OUTPUT))
+		return;
+
+	const int loglevel = translate_opensil_debug_level(MsgLevel);
+
+	/* print fomatted prefix */
+	if (CONFIG(OPENSIL_DEBUG_PREFIX))
+		printk(loglevel, "%s%s:%zu:", SilPrefix, Function, Line);
+
+	/* print formatted message */
+	va_list args;
+	va_start(args, Line);
+	vprintk(loglevel, Message, args);
+	va_end(args);
+}
diff --git a/src/vendorcode/amd/opensil/turin_poc/opensil_console.h b/src/vendorcode/amd/opensil/turin_poc/opensil_console.h
new file mode 100644
index 0000000000..d3ffb6857f
--- /dev/null
+++ b/src/vendorcode/amd/opensil/turin_poc/opensil_console.h
@@ -0,0 +1,9 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef _VENDORCODE_AND_OPENSIL_CONSOLE
+#define _VENDORCODE_AND_OPENSIL_CONSOLE
+
+void HostDebugService(size_t MsgLevel, const char *SilPrefix, const char *Message,
+		      const char *Function, size_t Line, ...);
+
+#endif
diff --git a/src/vendorcode/amd/opensil/turin_poc/ramstage.c b/src/vendorcode/amd/opensil/turin_poc/ramstage.c
new file mode 100644
index 0000000000..f4474f0be5
--- /dev/null
+++ b/src/vendorcode/amd/opensil/turin_poc/ramstage.c
@@ -0,0 +1,180 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <FCH/Common/FchCommonCfg.h>
+#include <FCH/Common/FchCore/FchSata/FchSata.h>
+#include <RcMgr/DfX/RcManager4-api.h>
+#include <amdblocks/reset.h>
+#include <bootstate.h>
+#include <cbmem.h>
+#include <cpu/cpu.h>
+#include <device/device.h>
+#include <soc/soc_chip.h>
+#include <static.h>
+#include <stdio.h>
+#include <xSIM-api.h>
+
+#include "opensil_console.h"
+#include "../opensil.h"
+
+void SIL_STATUS_report(const char *function, const int status)
+{
+	const int log_level = status == SilPass ? BIOS_DEBUG : BIOS_ERR;
+	const char *error_string = "Unknown error";
+
+	const struct error_string_entry {
+		SIL_STATUS status;
+		const char *string;
+	} errors[] = {
+		{SilPass, "SilPass"},
+		{SilUnsupportedHardware, "SilUnsupportedHardware"},
+		{SilUnsupported, "SilUnsupported"},
+		{SilInvalidParameter, "SilInvalidParameter"},
+		{SilAborted, "SilAborted"},
+		{SilOutOfResources, "SilOutOfResources"},
+		{SilNotFound, "SilNotFound"},
+		{SilOutOfBounds, "SilOutOfBounds"},
+		{SilDeviceError, "SilDeviceError"},
+		{SilResetRequestColdImm, "SilResetRequestColdImm"},
+		{SilResetRequestColdDef, "SilResetRequestColdDef"},
+		{SilResetRequestWarmImm, "SilResetRequestWarmImm"},
+		{SilResetRequestWarmDef, "SilResetRequestWarmDef"},
+	};
+
+	int i;
+	for (i = 0; i < ARRAY_SIZE(errors); i++) {
+		if (errors[i].status == status)
+			error_string = errors[i].string;
+	}
+	printk(log_level, "%s returned %d (%s)\n", function, status, error_string);
+}
+
+static void setup_rc_manager_default(void)
+{
+	DFX_RCMGR_INPUT_BLK *rc_mgr_input_block = SilFindStructure(SilId_RcManager,  0);
+	/* Let openSIL distribute the resources to the different PCI roots */
+	rc_mgr_input_block->SetRcBasedOnNv = false;
+
+	/* Currently 1P is the only supported configuration */
+	rc_mgr_input_block->SocketNumber = 1;
+	rc_mgr_input_block->RbsPerSocket = 4; /* PCI root bridges per socket */
+	rc_mgr_input_block->McptEnable = true;
+	rc_mgr_input_block->PciExpressBaseAddress = CONFIG_ECAM_MMCONF_BASE_ADDRESS;
+	rc_mgr_input_block->BottomMmioReservedForPrimaryRb = 4ull * GiB - 32 * MiB;
+	rc_mgr_input_block->MmioSizePerRbForNonPciDevice = 16 * MiB;
+	/* MmioAbove4GLimit will be adjusted down in openSIL */
+	rc_mgr_input_block->MmioAbove4GLimit = POWER_OF_2(cpu_phys_address_size());
+	rc_mgr_input_block->Above4GMmioSizePerRbForNonPciDevice = 0;
+}
+
+#define NUM_XHCI_CONTROLLERS 2
+static void configure_usb(void)
+{
+	const struct soc_amd_turin_poc_config *soc_config = config_of_soc();
+	const struct soc_usb_config *usb = &soc_config->usb;
+
+	FCHUSB_INPUT_BLK *fch_usb_data = SilFindStructure(SilId_FchUsb, 0);
+	fch_usb_data->Xhci0Enable = usb->xhci0_enable;
+	fch_usb_data->Xhci1Enable = usb->xhci1_enable;
+	fch_usb_data->Xhci2Enable = false; /* there's no XHCI2 on this SoC */
+	for (int i = 0; i < NUM_XHCI_CONTROLLERS; i++) {
+		memcpy(&fch_usb_data->XhciOCpinSelect[i].Usb20OcPin, &usb->usb2_oc_pins[i],
+		       sizeof(fch_usb_data->XhciOCpinSelect[i].Usb20OcPin));
+		memcpy(&fch_usb_data->XhciOCpinSelect[i].Usb31OcPin, &usb->usb3_oc_pins[i],
+		       sizeof(fch_usb_data->XhciOCpinSelect[i].Usb31OcPin));
+	}
+	fch_usb_data->XhciOcPolarityCfgLow = usb->polarity_cfg_low;
+	fch_usb_data->Usb3PortForceGen1 = usb->usb3_force_gen1.raw;
+
+	/* Instead of overwriting the whole OemUsbConfigurationTable, only copy the relevant
+	   fields to the pre-populated data structure */
+	fch_usb_data->OemUsbConfigurationTable.Usb31PhyEnable = usb->usb31_phy_enable;
+	if (usb->usb31_phy_enable)
+		memcpy(&fch_usb_data->OemUsbConfigurationTable.Usb31PhyPort, usb->usb31_phy,
+		       sizeof(fch_usb_data->OemUsbConfigurationTable.Usb31PhyPort));
+	fch_usb_data->OemUsbConfigurationTable.Usb31PhyEnable = usb->s1_usb31_phy_enable;
+	if (usb->s1_usb31_phy_enable)
+		memcpy(&fch_usb_data->OemUsbConfigurationTable.S1Usb31PhyPort, usb->s1_usb31_phy,
+		       sizeof(fch_usb_data->OemUsbConfigurationTable.S1Usb31PhyPort));
+}
+
+#define NUM_SATA_CONTROLLERS 4
+static void configure_sata(void)
+{
+	FCHSATA_INPUT_BLK *fch_sata_data = SilFindStructure(SilId_FchSata, 0);
+	FCH_SATA2 *fch_sata_defaults = GetFchSataData();
+	for (int i = 0; i < NUM_SATA_CONTROLLERS; i++) {
+		fch_sata_data[i] = fch_sata_defaults[i];
+		fch_sata_data[i].SataSetMaxGen2 = false;
+		fch_sata_data[i].SataMsiEnable = true;
+		fch_sata_data[i].SataEspPort = 0xFF;
+		fch_sata_data[i].SataRasSupport = true;
+		fch_sata_data[i].SataDevSlpPort1Num = 1;
+		fch_sata_data[i].SataMsiEnable = true;
+		fch_sata_data[i].SataControllerAutoShutdown = true;
+		fch_sata_data[i].SataRxPolarity = 0xFF;
+	}
+}
+
+void setup_opensil(void)
+{
+	const SIL_STATUS debug_ret = SilDebugSetup(HostDebugService);
+	SIL_STATUS_report("SilDebugSetup", debug_ret);
+	const size_t mem_req = xSimQueryMemoryRequirements();
+	void *buf = cbmem_add(CBMEM_ID_AMD_OPENSIL, mem_req);
+	assert(buf);
+	/* We run all openSIL timepoints in the same stage so using TP1 as argument is fine. */
+	const SIL_STATUS assign_mem_ret = xSimAssignMemoryTp1(buf, mem_req);
+	SIL_STATUS_report("xSimAssignMemory", assign_mem_ret);
+
+	setup_rc_manager_default();
+	configure_usb();
+	configure_sata();
+}
+
+static void opensil_entry(SIL_TIMEPOINT timepoint)
+{
+	SIL_STATUS ret;
+	SIL_TIMEPOINT tp = (uintptr_t)timepoint;
+
+	switch (tp) {
+	case SIL_TP1:
+		ret = InitializeSiTp1();
+		break;
+	case SIL_TP2:
+		ret = InitializeSiTp2();
+		break;
+	case SIL_TP3:
+		ret = InitializeSiTp3();
+		break;
+	default:
+		printk(BIOS_ERR, "Unknown openSIL timepoint\n");
+		return;
+	}
+	char opensil_function[16];
+	snprintf(opensil_function, sizeof(opensil_function), "InitializeSiTp%d", tp + 1);
+	SIL_STATUS_report(opensil_function, ret);
+	if (ret == SilResetRequestColdImm || ret == SilResetRequestColdDef) {
+		printk(BIOS_INFO, "openSIL requested a cold reset");
+		do_cold_reset();
+	} else if (ret == SilResetRequestWarmImm || ret == SilResetRequestWarmDef) {
+		printk(BIOS_INFO, "openSIL requested a warm reset");
+		do_warm_reset();
+	}
+}
+
+void opensil_xSIM_timepoint_1(void)
+{
+	opensil_entry(SIL_TP1);
+}
+
+void opensil_xSIM_timepoint_2(void)
+{
+	opensil_entry(SIL_TP2);
+}
+
+void opensil_xSIM_timepoint_3(void)
+{
+	opensil_entry(SIL_TP3);
+}
+
+/* TODO: also call timepoints 2 and 3 from coreboot. Are they NOOP? */
diff --git a/src/vendorcode/amd/opensil/turin_poc/romstage.c b/src/vendorcode/amd/opensil/turin_poc/romstage.c
new file mode 100644
index 0000000000..5b871f6025
--- /dev/null
+++ b/src/vendorcode/amd/opensil/turin_poc/romstage.c
@@ -0,0 +1,17 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <console/console.h>
+#include "opensil_console.h"
+#include <xSIM-api.h>
+#include <xPRF-api.h>
+
+#include "../opensil.h"
+
+uintptr_t opensil_get_low_usable_dram_address(void)
+{
+	SilDebugSetup(HostDebugService);
+	uintptr_t low_usable_dram_addr = xPrfGetLowUsableDramAddress(0);
+	printk(BIOS_DEBUG, "xPrfGetLowUsableDramAddress: 0x%lx\n", low_usable_dram_addr);
+
+	return low_usable_dram_addr;
+}

From 0750412241b256d653d555cdda3e51ddb49a884c Mon Sep 17 00:00:00 2001
From: Yu-Ping Wu <yupingso@chromium.org>
Date: Wed, 21 Jan 2026 17:25:06 +0800
Subject: [PATCH 3100/3886] soc/mediatek/mt8196: Fix missing read_resources for
 non-NVMe SKUs

The following error will be shown on non-NVMe SKUs.

 [ERROR]  DOMAIN: 00000000 missing read_resources

That's because when mainboard_needs_pcie_init() returns false, dev->ops
will be NULL, causing the '!curdev->ops || !curdev->ops->read_resources'
check to fail in device/device.c read_resources().

To prevent the misleading error message from showing up, for non-NVMe
SKUs, assign 'noop_domain_ops' to dev->ops.

BUG=none
TEST=emerge-tanjiro coreboot
BRANCH=rauru

Change-Id: If0f81aadda3fbde99f4df794cbdd885a607c9625
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90843
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Chen-Tsung Hsieh <chentsung@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/soc/mediatek/mt8196/soc.c | 11 +++++++++--
 1 file changed, 9 insertions(+), 2 deletions(-)

diff --git a/src/soc/mediatek/mt8196/soc.c b/src/soc/mediatek/mt8196/soc.c
index e988a76926..c739998383 100644
--- a/src/soc/mediatek/mt8196/soc.c
+++ b/src/soc/mediatek/mt8196/soc.c
@@ -104,15 +104,22 @@ static struct device_operations pci_domain_ops = {
 	.enable = &mtk_pcie_domain_enable,
 };
 
+static struct device_operations noop_domain_ops = {
+	.read_resources = &noop_read_resources,
+	.set_resources = &noop_set_resources,
+};
+
 static void enable_soc_dev(struct device *dev)
 {
 	if (dev->path.type == DEVICE_PATH_CPU_CLUSTER) {
 		dev->ops = &soc_ops;
 	} else if (dev->path.type == DEVICE_PATH_DOMAIN) {
-		if (mainboard_needs_pcie_init())
+		if (mainboard_needs_pcie_init()) {
 			dev->ops = &pci_domain_ops;
-		else
+		} else {
 			printk(BIOS_DEBUG, "Skip setting PCIe ops\n");
+			dev->ops = &noop_domain_ops;
+		}
 	}
 }
 

From 87731a704ae30549575a1c3d3c7b7858971147a5 Mon Sep 17 00:00:00 2001
From: Yu-Ping Wu <yupingso@chromium.org>
Date: Wed, 21 Jan 2026 17:31:39 +0800
Subject: [PATCH 3101/3886] soc/mediatek/common/dp: Print unexpected eDP
 pattern in error log

BUG=none
TEST=emerge-tanjiro coreboot
BRANCH=rauru

Change-Id: Ib7f06a8da0f6ae89fa9ac2189f6c38b35362a609
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90844
Reviewed-by: Chen-Tsung Hsieh <chentsung@google.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/soc/mediatek/common/dp/dptx_v2.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/soc/mediatek/common/dp/dptx_v2.c b/src/soc/mediatek/common/dp/dptx_v2.c
index 5b917a501a..81cfa76681 100644
--- a/src/soc/mediatek/common/dp/dptx_v2.c
+++ b/src/soc/mediatek/common/dp/dptx_v2.c
@@ -41,7 +41,7 @@ static void mtk_edp_pattern(struct mtk_dp *mtk_dp, u8 lane_count, u8 pattern)
 		break;
 	case DPTX_PATTERN_UNKNOWN:
 	default:
-		printk(BIOS_ERR, "Set default or unknown pattern\n");
+		printk(BIOS_ERR, "Set default or unknown pattern %d\n", pattern);
 		mtk_dp_mask(mtk_dp, REG_3400_DP_TRANS_P0, 0x0, PATTERN_EN_DP_TRANS_4P_MASK);
 		return;
 	}

From ee2cbba939b362d644bf8ce7c8b6adb57b1f2d14 Mon Sep 17 00:00:00 2001
From: Chen-Tsung Hsieh <chentsung@chromium.org>
Date: Thu, 22 Jan 2026 05:05:32 +0000
Subject: [PATCH 3102/3886] soc/mediatek/mt8196: Remove unused MTE_TAG_ADDR
 macro

The MTE_TAG_ADDR macro is no longer used after the changes in CB:90144.
Remove the unused definition.

BUG=b:438666196
TEST=util/abuild/abuild -x -t GOOGLE_SAPPHIRE -a --clean
BRANCH=none

Change-Id: Ic71fa22292793162de882d3c764e7805301250c5
Signed-off-by: Chen-Tsung Hsieh <chentsung@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90864
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
---
 src/soc/mediatek/mt8196/include/soc/booker.h | 2 --
 1 file changed, 2 deletions(-)

diff --git a/src/soc/mediatek/mt8196/include/soc/booker.h b/src/soc/mediatek/mt8196/include/soc/booker.h
index 25c2d140af..ea819429fd 100644
--- a/src/soc/mediatek/mt8196/include/soc/booker.h
+++ b/src/soc/mediatek/mt8196/include/soc/booker.h
@@ -5,8 +5,6 @@
 
 #include <stdint.h>
 
-#define MTE_TAG_ADDR 0x460E80000
-
 void booker_init(void);
 void booker_mte_init(uint64_t mte_tag_addr);
 

From 4222a1ffd612c12e52528aa84cf6a5289998234c Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Fri, 16 Jan 2026 17:26:58 -0600
Subject: [PATCH 3103/3886] util/chromeos/crosfirmware.sh: Refactor dependency
 checking

Refactor exit_if_dependencies_are_missing() to check all dependencies
in a single pass using an associative array, collect any missing ones,
and report them all together before exiting. This provides better UX
by showing all missing dependencies at once rather than exiting after
the first one.

This replaces the previous approach that would exit immediately upon
finding the first missing dependency, often causing users to run the
script several times to identify and install all missing dependencies.

Change-Id: Ieb03756b24fd2aa1af2c0ffaed717d06c9e85cbb
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90785
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
---
 util/chromeos/crosfirmware.sh | 47 ++++++++++++++++++++---------------
 1 file changed, 27 insertions(+), 20 deletions(-)

diff --git a/util/chromeos/crosfirmware.sh b/util/chromeos/crosfirmware.sh
index 673f3b38a5..ab17c22ad6 100755
--- a/util/chromeos/crosfirmware.sh
+++ b/util/chromeos/crosfirmware.sh
@@ -5,27 +5,34 @@
 # On some systems, `parted` and `debugfs` are located in /sbin.
 export PATH="$PATH:/sbin"
 
-exit_if_uninstalled() {
-	local cmd_name="$1"
-	local deb_pkg_name="$2"
-
-	if type "$cmd_name" >/dev/null 2>&1; then
-		return
-	fi
-
-	printf '`%s` was not found. ' "$cmd_name" >&2
-	printf 'On Debian-based systems, it can be installed\n' >&2
-	printf 'by running `apt install %s`.\n' "$deb_pkg_name" >&2
-
-	exit 1
-}
-
 exit_if_dependencies_are_missing() {
-	exit_if_uninstalled "uudecode" "sharutils"
-	exit_if_uninstalled "debugfs" "e2fsprogs"
-	exit_if_uninstalled "parted" "parted"
-	exit_if_uninstalled "curl" "curl"
-	exit_if_uninstalled "unzip" "unzip"
+	local missing_deps=()
+	local -A deps_map=(
+		["uudecode"]="sharutils"
+		["debugfs"]="e2fsprogs"
+		["parted"]="parted"
+		["curl"]="curl"
+		["unzip"]="unzip"
+	)
+
+	# Check all dependencies at once
+	for cmd_name in "${!deps_map[@]}"; do
+		if ! type "$cmd_name" >/dev/null 2>&1; then
+			missing_deps+=("$cmd_name:${deps_map[$cmd_name]}")
+		fi
+	done
+
+	# Exit if any dependencies are missing
+	if [ ${#missing_deps[@]} -gt 0 ]; then
+		printf 'The following required commands were not found:\n' >&2
+		for dep_info in "${missing_deps[@]}"; do
+			cmd_name="${dep_info%%:*}"
+			deb_pkg_name="${dep_info##*:}"
+			printf '  - `%s`\n' "$cmd_name" >&2
+			printf '    On Debian-based systems, install with: `apt install %s`\n' "$deb_pkg_name" >&2
+		done
+		exit 1
+	fi
 }
 
 get_inventory() {

From 369c47d00eaad5ff8e06d310647c9a847ce29c7b Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Fri, 16 Jan 2026 17:29:19 -0600
Subject: [PATCH 3104/3886] util/chromeos/crosfirmware.sh: Add 7z as a
 dependency

Many newer ChromeOS recovery shellballs require 7z to decompress, so
add it as a dependency.

Change-Id: Ibe0391567736a39c31914c573b154d8ed7de617b
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90786
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
---
 util/chromeos/crosfirmware.sh | 1 +
 1 file changed, 1 insertion(+)

diff --git a/util/chromeos/crosfirmware.sh b/util/chromeos/crosfirmware.sh
index ab17c22ad6..999b7c201f 100755
--- a/util/chromeos/crosfirmware.sh
+++ b/util/chromeos/crosfirmware.sh
@@ -13,6 +13,7 @@ exit_if_dependencies_are_missing() {
 		["parted"]="parted"
 		["curl"]="curl"
 		["unzip"]="unzip"
+		["7z"]="p7zip"
 	)
 
 	# Check all dependencies at once

From 36f0b1257009e6acd314d319226afdc2fe7f234c Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Fri, 16 Jan 2026 17:32:22 -0600
Subject: [PATCH 3105/3886] util/chromeos/crosfirmware.sh: Exit if shellball
 extraction fails

Test if shellball extraction fails, and if it does, show the output of
the command and then exit, as nothing more can be done.

Change-Id: I0cd7416c988d11e019bfd0b4cd52af8811e6d1e2
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90787
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
---
 util/chromeos/crosfirmware.sh | 6 +++++-
 1 file changed, 5 insertions(+), 1 deletion(-)

diff --git a/util/chromeos/crosfirmware.sh b/util/chromeos/crosfirmware.sh
index 999b7c201f..3be613de19 100755
--- a/util/chromeos/crosfirmware.sh
+++ b/util/chromeos/crosfirmware.sh
@@ -103,7 +103,11 @@ extract_coreboot() {
 
 	echo "Extracting coreboot image"
 	if ! sh $_shellball --unpack $_unpacked >/dev/null 2>&1; then
-		sh $_shellball --sb_extract $_unpacked >/dev/null 2>&1
+		if ! sh $_shellball --sb_extract $_unpacked >$_unpacked/sb_extract.log 2>&1; then
+			echo "Failed to extract shellball image"
+			cat $_unpacked/sb_extract.log
+			exit 1
+		fi
 	fi
 
 	if [ -d $_unpacked/models/ ]; then

From 82a2e328dca6ac4b5336cd282b7ddb0032ecd88a Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Tue, 20 Jan 2026 14:20:41 +0000
Subject: [PATCH 3106/3886] mb/starlabs/starfighter/mtl: Fix 64GB spd binary

This somehow lost a few bytes when initially addded, so restore
the whole binary that was originally generated with spd_tools.

Change-Id: I7aa828c8e358a0d40597a265a8fc54e01ff105e8
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90824
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 .../starlabs/starfighter/spd/64gb-mtl.spd.hex | 23 +++++++++++++------
 1 file changed, 16 insertions(+), 7 deletions(-)

diff --git a/src/mainboard/starlabs/starfighter/spd/64gb-mtl.spd.hex b/src/mainboard/starlabs/starfighter/spd/64gb-mtl.spd.hex
index d8a75d2182..ee280c8ca2 100644
--- a/src/mainboard/starlabs/starfighter/spd/64gb-mtl.spd.hex
+++ b/src/mainboard/starlabs/starfighter/spd/64gb-mtl.spd.hex
@@ -9,15 +9,24 @@
 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 20 00 00 00
-20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20
-20 20 20 20 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 7F 00 00 00 00 00 00 00
 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 20 00 00 00 20 20 20 20 20 20 20
+20 20 20 20 20 20 20 20 20 20 20 20 20 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00

From 57bfc9184bcf2116c430410a84d90720153baa48 Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Tue, 20 Jan 2026 15:03:41 +0000
Subject: [PATCH 3107/3886] mb/starlabs/starfighter: Make the memory speed
 configurable

Let the user chose between 5500, 6400 and 7500MT/s.

Change-Id: I91171f252e83e409904031109ee084115f6b3708
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90825
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/starlabs/starfighter/cfr.c      |  1 +
 .../starfighter/spd/16gb-5500.spd.hex         | 32 +++++++++++++++++++
 .../spd/{16gb.spd.hex => 16gb-6400.spd.hex}   |  0
 .../starfighter/spd/16gb-7500.spd.hex         | 32 +++++++++++++++++++
 .../starfighter/spd/32gb-5500.spd.hex         | 32 +++++++++++++++++++
 .../spd/{32gb.spd.hex => 32gb-6400.spd.hex}   |  0
 .../starfighter/spd/32gb-7500.spd.hex         | 32 +++++++++++++++++++
 .../starfighter/spd/32gb-mtl-5500.spd.hex     | 32 +++++++++++++++++++
 ...32gb-mtl.spd.hex => 32gb-mtl-6400.spd.hex} |  0
 .../starfighter/spd/32gb-mtl-7500.spd.hex     | 32 +++++++++++++++++++
 .../starfighter/spd/64gb-5500.spd.hex         | 32 +++++++++++++++++++
 .../starfighter/spd/64gb-6400.spd.hex         | 32 +++++++++++++++++++
 .../spd/{64gb.spd.hex => 64gb-7500.spd.hex}   |  0
 .../starfighter/spd/64gb-mtl-5500.spd.hex     | 32 +++++++++++++++++++
 .../starfighter/spd/64gb-mtl-6400.spd.hex     | 32 +++++++++++++++++++
 ...64gb-mtl.spd.hex => 64gb-mtl-7500.spd.hex} |  0
 .../starlabs/starfighter/spd/Makefile.mk      | 24 +++++++++++---
 .../starfighter/variants/mtl/romstage.c       | 17 +++++++---
 .../starfighter/variants/rpl/romstage.c       | 19 ++++++++---
 19 files changed, 367 insertions(+), 14 deletions(-)
 create mode 100644 src/mainboard/starlabs/starfighter/spd/16gb-5500.spd.hex
 rename src/mainboard/starlabs/starfighter/spd/{16gb.spd.hex => 16gb-6400.spd.hex} (100%)
 create mode 100644 src/mainboard/starlabs/starfighter/spd/16gb-7500.spd.hex
 create mode 100644 src/mainboard/starlabs/starfighter/spd/32gb-5500.spd.hex
 rename src/mainboard/starlabs/starfighter/spd/{32gb.spd.hex => 32gb-6400.spd.hex} (100%)
 create mode 100644 src/mainboard/starlabs/starfighter/spd/32gb-7500.spd.hex
 create mode 100644 src/mainboard/starlabs/starfighter/spd/32gb-mtl-5500.spd.hex
 rename src/mainboard/starlabs/starfighter/spd/{32gb-mtl.spd.hex => 32gb-mtl-6400.spd.hex} (100%)
 create mode 100644 src/mainboard/starlabs/starfighter/spd/32gb-mtl-7500.spd.hex
 create mode 100644 src/mainboard/starlabs/starfighter/spd/64gb-5500.spd.hex
 create mode 100644 src/mainboard/starlabs/starfighter/spd/64gb-6400.spd.hex
 rename src/mainboard/starlabs/starfighter/spd/{64gb.spd.hex => 64gb-7500.spd.hex} (100%)
 create mode 100644 src/mainboard/starlabs/starfighter/spd/64gb-mtl-5500.spd.hex
 create mode 100644 src/mainboard/starlabs/starfighter/spd/64gb-mtl-6400.spd.hex
 rename src/mainboard/starlabs/starfighter/spd/{64gb-mtl.spd.hex => 64gb-mtl-7500.spd.hex} (100%)

diff --git a/src/mainboard/starlabs/starfighter/cfr.c b/src/mainboard/starlabs/starfighter/cfr.c
index e925fa731c..45df94c424 100644
--- a/src/mainboard/starlabs/starfighter/cfr.c
+++ b/src/mainboard/starlabs/starfighter/cfr.c
@@ -12,6 +12,7 @@ static struct sm_obj_form performance_group = {
 	.ui_name = "Performance",
 	.obj_list = (const struct sm_object *[]) {
 		&bluetooth_rtd3,
+		&memory_speed,
 		&fan_mode,
 		&power_profile,
 		NULL
diff --git a/src/mainboard/starlabs/starfighter/spd/16gb-5500.spd.hex b/src/mainboard/starlabs/starfighter/spd/16gb-5500.spd.hex
new file mode 100644
index 0000000000..77a62517e3
--- /dev/null
+++ b/src/mainboard/starlabs/starfighter/spd/16gb-5500.spd.hex
@@ -0,0 +1,32 @@
+23 10 13 0E 15 1A B5 08 00 40 00 00 0A 01 00 00
+48 00 0B FF 92 55 05 00 AE 00 90 A8 90 90 06 C0
+03 08 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 16 36 16 36
+16 36 16 36 00 00 16 36 16 36 16 36 16 36 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 9C 00 00 00 00 4B 7F 50 69 9A
+11 01 40 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 D8 53
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+80 2C 25 20 02 F0 E6 A8 9B 38 41 54 46 31 47 36
+34 41 5A 2D 33 47 32 45 31 20 20 20 20 31 80 2C
+45 48 4D 30 30 30 30 33 37 30 33 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
diff --git a/src/mainboard/starlabs/starfighter/spd/16gb.spd.hex b/src/mainboard/starlabs/starfighter/spd/16gb-6400.spd.hex
similarity index 100%
rename from src/mainboard/starlabs/starfighter/spd/16gb.spd.hex
rename to src/mainboard/starlabs/starfighter/spd/16gb-6400.spd.hex
diff --git a/src/mainboard/starlabs/starfighter/spd/16gb-7500.spd.hex b/src/mainboard/starlabs/starfighter/spd/16gb-7500.spd.hex
new file mode 100644
index 0000000000..110d974afa
--- /dev/null
+++ b/src/mainboard/starlabs/starfighter/spd/16gb-7500.spd.hex
@@ -0,0 +1,32 @@
+23 10 13 0E 15 1A B5 08 00 40 00 00 0A 01 00 00
+48 00 08 FF 92 55 05 00 AA 00 90 A8 90 90 06 C0
+03 08 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 16 36 16 36
+16 36 16 36 00 00 16 36 16 36 16 36 16 36 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 9C 00 00 00 00 46 7F 42 69 9A
+11 01 40 00 00 00 00 00 00 00 00 00 00 00 00 00
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+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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+00 00 00 00 00 00 00 00 00 00 00 00 00 00 D8 53
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+80 2C 25 20 02 F0 E6 A8 9B 38 41 54 46 31 47 36
+34 41 5A 2D 33 47 32 45 31 20 20 20 20 31 80 2C
+45 48 4D 30 30 30 30 33 37 30 33 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
diff --git a/src/mainboard/starlabs/starfighter/spd/32gb-5500.spd.hex b/src/mainboard/starlabs/starfighter/spd/32gb-5500.spd.hex
new file mode 100644
index 0000000000..09f6a03464
--- /dev/null
+++ b/src/mainboard/starlabs/starfighter/spd/32gb-5500.spd.hex
@@ -0,0 +1,32 @@
+23 10 13 0E 16 22 B5 08 00 40 00 00 0A 01 00 00
+48 00 0B FF 92 55 05 00 AE 00 90 A8 90 C0 08 60
+04 08 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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+00 00 00 00 00 00 9C 00 00 00 00 4B 7F 50 69 9A
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+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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+80 2C 25 20 02 F0 E6 A8 9B 38 41 54 46 31 47 36
+34 41 5A 2D 33 47 32 45 31 20 20 20 20 31 80 2C
+45 48 4D 30 30 30 30 33 37 30 33 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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diff --git a/src/mainboard/starlabs/starfighter/spd/32gb.spd.hex b/src/mainboard/starlabs/starfighter/spd/32gb-6400.spd.hex
similarity index 100%
rename from src/mainboard/starlabs/starfighter/spd/32gb.spd.hex
rename to src/mainboard/starlabs/starfighter/spd/32gb-6400.spd.hex
diff --git a/src/mainboard/starlabs/starfighter/spd/32gb-7500.spd.hex b/src/mainboard/starlabs/starfighter/spd/32gb-7500.spd.hex
new file mode 100644
index 0000000000..c946476aa6
--- /dev/null
+++ b/src/mainboard/starlabs/starfighter/spd/32gb-7500.spd.hex
@@ -0,0 +1,32 @@
+23 10 13 0E 16 22 B5 08 00 40 00 00 0A 01 00 00
+48 00 08 FF 92 55 05 00 AA 00 90 A8 90 C0 08 60
+04 08 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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diff --git a/src/mainboard/starlabs/starfighter/spd/32gb-mtl-5500.spd.hex b/src/mainboard/starlabs/starfighter/spd/32gb-mtl-5500.spd.hex
new file mode 100644
index 0000000000..de89ca1b80
--- /dev/null
+++ b/src/mainboard/starlabs/starfighter/spd/32gb-mtl-5500.spd.hex
@@ -0,0 +1,32 @@
+23 10 13 0E 16 22 B5 08 00 40 00 00 0A 01 00 00
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diff --git a/src/mainboard/starlabs/starfighter/spd/32gb-mtl.spd.hex b/src/mainboard/starlabs/starfighter/spd/32gb-mtl-6400.spd.hex
similarity index 100%
rename from src/mainboard/starlabs/starfighter/spd/32gb-mtl.spd.hex
rename to src/mainboard/starlabs/starfighter/spd/32gb-mtl-6400.spd.hex
diff --git a/src/mainboard/starlabs/starfighter/spd/32gb-mtl-7500.spd.hex b/src/mainboard/starlabs/starfighter/spd/32gb-mtl-7500.spd.hex
new file mode 100644
index 0000000000..8f4c71530a
--- /dev/null
+++ b/src/mainboard/starlabs/starfighter/spd/32gb-mtl-7500.spd.hex
@@ -0,0 +1,32 @@
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diff --git a/src/mainboard/starlabs/starfighter/spd/64gb-5500.spd.hex b/src/mainboard/starlabs/starfighter/spd/64gb-5500.spd.hex
new file mode 100644
index 0000000000..c0ecc15077
--- /dev/null
+++ b/src/mainboard/starlabs/starfighter/spd/64gb-5500.spd.hex
@@ -0,0 +1,32 @@
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+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
diff --git a/src/mainboard/starlabs/starfighter/spd/64gb-6400.spd.hex b/src/mainboard/starlabs/starfighter/spd/64gb-6400.spd.hex
new file mode 100644
index 0000000000..bdeb4c2501
--- /dev/null
+++ b/src/mainboard/starlabs/starfighter/spd/64gb-6400.spd.hex
@@ -0,0 +1,32 @@
+23 10 15 0E 16 2A F9 08 00 40 00 00 09 01 00 00
+48 00 0A FF 92 55 05 00 AA 00 90 A8 90 C0 08 60
+04 08 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 16 36 16 36
+16 36 16 36 00 00 16 36 16 36 16 36 16 36 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 9C 00 00 00 00 00 7F 00 69 9A
+11 01 40 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 D8 53
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+80 2C 25 20 02 F0 E6 A8 9B 38 41 54 46 31 47 36
+34 41 5A 2D 33 47 32 45 31 20 20 20 20 31 80 2C
+45 48 4D 30 30 30 30 33 37 30 33 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
diff --git a/src/mainboard/starlabs/starfighter/spd/64gb.spd.hex b/src/mainboard/starlabs/starfighter/spd/64gb-7500.spd.hex
similarity index 100%
rename from src/mainboard/starlabs/starfighter/spd/64gb.spd.hex
rename to src/mainboard/starlabs/starfighter/spd/64gb-7500.spd.hex
diff --git a/src/mainboard/starlabs/starfighter/spd/64gb-mtl-5500.spd.hex b/src/mainboard/starlabs/starfighter/spd/64gb-mtl-5500.spd.hex
new file mode 100644
index 0000000000..c2934a2c6e
--- /dev/null
+++ b/src/mainboard/starlabs/starfighter/spd/64gb-mtl-5500.spd.hex
@@ -0,0 +1,32 @@
+23 10 15 0E 16 2A F9 08 00 40 00 00 09 01 00 00
+48 00 0B FF 92 55 05 00 AE 00 90 A8 90 C0 08 60
+04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 4B 00 50 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 7F 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 20 00 00 00 20 20 20 20 20 20 20
+20 20 20 20 20 20 20 20 20 20 20 20 20 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
diff --git a/src/mainboard/starlabs/starfighter/spd/64gb-mtl-6400.spd.hex b/src/mainboard/starlabs/starfighter/spd/64gb-mtl-6400.spd.hex
new file mode 100644
index 0000000000..a3ca8d3afd
--- /dev/null
+++ b/src/mainboard/starlabs/starfighter/spd/64gb-mtl-6400.spd.hex
@@ -0,0 +1,32 @@
+23 10 15 0E 16 2A F9 08 00 40 00 00 09 01 00 00
+48 00 0A FF 92 55 05 00 AA 00 90 A8 90 C0 08 60
+04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 7F 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 20 00 00 00 20 20 20 20 20 20 20
+20 20 20 20 20 20 20 20 20 20 20 20 20 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
diff --git a/src/mainboard/starlabs/starfighter/spd/64gb-mtl.spd.hex b/src/mainboard/starlabs/starfighter/spd/64gb-mtl-7500.spd.hex
similarity index 100%
rename from src/mainboard/starlabs/starfighter/spd/64gb-mtl.spd.hex
rename to src/mainboard/starlabs/starfighter/spd/64gb-mtl-7500.spd.hex
diff --git a/src/mainboard/starlabs/starfighter/spd/Makefile.mk b/src/mainboard/starlabs/starfighter/spd/Makefile.mk
index ee9a117ed2..4bce4845b9 100644
--- a/src/mainboard/starlabs/starfighter/spd/Makefile.mk
+++ b/src/mainboard/starlabs/starfighter/spd/Makefile.mk
@@ -1,10 +1,24 @@
 ## SPDX-License-Identifier: GPL-2.0-only
 
 ifeq ($(CONFIG_BOARD_STARLABS_STARFIGHTER_RPL),y)
-SPD_SOURCES = 16gb # 13
-SPD_SOURCES += 32gb # 0
-SPD_SOURCES += 64gb # 8
+# RPL memory configs (selected by straps) with runtime speed selection.
+# CBFS index order is (per config): 5500, 6400, 7500.
+SPD_SOURCES = 16gb-5500
+SPD_SOURCES += 16gb-6400
+SPD_SOURCES += 16gb-7500
+SPD_SOURCES += 32gb-5500
+SPD_SOURCES += 32gb-6400
+SPD_SOURCES += 32gb-7500
+SPD_SOURCES += 64gb-5500
+SPD_SOURCES += 64gb-6400
+SPD_SOURCES += 64gb-7500
 else
-SPD_SOURCES = 32gb-mtl # 13
-SPD_SOURCES += 64gb-mtl # 0
+# MTL memory configs (selected by straps) with runtime speed selection.
+# CBFS index order is (per config): 5500, 6400, 7500.
+SPD_SOURCES = 32gb-mtl-5500
+SPD_SOURCES += 32gb-mtl-6400
+SPD_SOURCES += 32gb-mtl-7500
+SPD_SOURCES += 64gb-mtl-5500
+SPD_SOURCES += 64gb-mtl-6400
+SPD_SOURCES += 64gb-mtl-7500
 endif
diff --git a/src/mainboard/starlabs/starfighter/variants/mtl/romstage.c b/src/mainboard/starlabs/starfighter/variants/mtl/romstage.c
index 8281dd0ebb..486912cbfe 100644
--- a/src/mainboard/starlabs/starfighter/variants/mtl/romstage.c
+++ b/src/mainboard/starlabs/starfighter/variants/mtl/romstage.c
@@ -6,16 +6,23 @@
 #include <types.h>
 #include <variants.h>
 
-static uint8_t strap_to_cbfs_index(uint8_t strap)
+static uint8_t strap_to_memcfg_index(uint8_t strap)
 {
 	switch (strap) {
-	case 13:	// 32GB
+	case 13: /* 32GB */
 		return 0;
-	default:	// 64GB
+	default: /* 64GB */
 		return 1;
 	}
 }
 
+static uint8_t memcfg_and_speed_to_cbfs_index(uint8_t memcfg, unsigned int speed)
+{
+	if (speed > 2)
+		speed = 2;
+	return (uint8_t)(memcfg * 3 + speed);
+}
+
 void mainboard_memory_init_params(FSPM_UPD *mupd)
 {
 	const struct mb_cfg mem_config = {
@@ -82,7 +89,9 @@ void mainboard_memory_init_params(FSPM_UPD *mupd)
 
 	const struct mem_spd lpddr5_spd_info = {
 		.topo = MEM_TOPO_MEMORY_DOWN,
-		.cbfs_index = strap_to_cbfs_index(get_memory_config_straps()),
+		.cbfs_index = memcfg_and_speed_to_cbfs_index(
+			strap_to_memcfg_index(get_memory_config_straps()),
+			get_uint_option("memory_speed", 1)),
 	};
 
 	memcfg_init(mupd, &mem_config, &lpddr5_spd_info, half_populated);
diff --git a/src/mainboard/starlabs/starfighter/variants/rpl/romstage.c b/src/mainboard/starlabs/starfighter/variants/rpl/romstage.c
index 34e61728c4..4242560688 100644
--- a/src/mainboard/starlabs/starfighter/variants/rpl/romstage.c
+++ b/src/mainboard/starlabs/starfighter/variants/rpl/romstage.c
@@ -40,18 +40,25 @@ static uint8_t get_memory_config_straps(void)
 	return (uint8_t)gpio_base2_value(spd_id, ARRAY_SIZE(spd_id));
 }
 
-static uint8_t strap_to_cbfs_index(uint8_t strap)
+static uint8_t strap_to_memcfg_index(uint8_t strap)
 {
 	switch (strap) {
-	case 0:	// 32GB
+	case 0: /* 32GB */
 		return 1;
-	case 8:	// 64GB
+	case 8: /* 64GB */
 		return 2;
-	default:// 16GB
+	default: /* 16GB */
 		return 0;
 	}
 }
 
+static uint8_t memcfg_and_speed_to_cbfs_index(uint8_t memcfg, unsigned int speed)
+{
+	if (speed > 2)
+		speed = 2;
+	return (uint8_t)(memcfg * 3 + speed);
+}
+
 void mainboard_memory_init_params(FSPM_UPD *mupd)
 {
 	const struct mb_cfg mem_config = {
@@ -118,7 +125,9 @@ void mainboard_memory_init_params(FSPM_UPD *mupd)
 
 	const struct mem_spd lpddr5_spd_info = {
 		.topo = MEM_TOPO_MEMORY_DOWN,
-		.cbfs_index = strap_to_cbfs_index(get_memory_config_straps()),
+		.cbfs_index = memcfg_and_speed_to_cbfs_index(
+			strap_to_memcfg_index(get_memory_config_straps()),
+			get_uint_option("memory_speed", 1)),
 	};
 
 	memcfg_init(mupd, &mem_config, &lpddr5_spd_info, half_populated);

From b3e8bd41254d2059f4555e7f794a7f48b617743d Mon Sep 17 00:00:00 2001
From: Swathi Tamilselvan <tswathi@qualcomm.corp-partner.google.com>
Date: Tue, 20 Jan 2026 12:48:00 +0530
Subject: [PATCH 3108/3886] soc/qualcomm/x1p42100: Add API support for audio
 clock configuration

Add API support to enable LPASS core clocks and vote for LP0 BCM
resource required for LPASS. This change includes support to enable
audio clocks.

LPASS is Low Power Audio Subsystem that runs audio and voice
processing on a dedicated DSP. This enables low-power audio operation
while the main CPUs remain in low-power states.

Test=1. Create an image.serial.bin and ensure it boots on X1P42100.

Change-Id: If7684bee10d127866acac80e6aeefadaa177dc1f
Signed-off-by: Swathi Tamilselvan <tswathi@qualcomm.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90851
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
---
 src/soc/qualcomm/x1p42100/Makefile.mk         |   1 +
 .../x1p42100/include/soc/addressmap.h         |   7 +
 src/soc/qualcomm/x1p42100/include/soc/clock.h | 187 +++++++++++++++---
 src/soc/qualcomm/x1p42100/include/soc/lpass.h |  27 +++
 src/soc/qualcomm/x1p42100/lpass.c             | 147 ++++++++++++++
 5 files changed, 343 insertions(+), 26 deletions(-)
 create mode 100644 src/soc/qualcomm/x1p42100/include/soc/lpass.h
 create mode 100644 src/soc/qualcomm/x1p42100/lpass.c

diff --git a/src/soc/qualcomm/x1p42100/Makefile.mk b/src/soc/qualcomm/x1p42100/Makefile.mk
index 4a51a20dd6..2881e90350 100644
--- a/src/soc/qualcomm/x1p42100/Makefile.mk
+++ b/src/soc/qualcomm/x1p42100/Makefile.mk
@@ -56,6 +56,7 @@ ramstage-y += ../common/cmd_db.c
 ramstage-y += ../common/rpmh.c ../common/rpmh_bcm.c ../common/rpmh_regulator.c ../common/rpmh_rsc.c
 ramstage-y += rpmh_rsc_init.c
 ramstage-y += display/disp.c
+ramstage-y += lpass.c
 
 ################################################################################
 
diff --git a/src/soc/qualcomm/x1p42100/include/soc/addressmap.h b/src/soc/qualcomm/x1p42100/include/soc/addressmap.h
index 60649835d6..dc45a668d6 100644
--- a/src/soc/qualcomm/x1p42100/include/soc/addressmap.h
+++ b/src/soc/qualcomm/x1p42100/include/soc/addressmap.h
@@ -18,6 +18,13 @@
 #define DISP_PLL1_BASE			0xAF01000
 #define DISP_CC_BASE			0xAF08000
 
+/* LPASS BASE ADDRESSES */
+#define LPASS_BASE			0x06000000
+#define LPASS_AUDIO_CC_PLL_BASE		(LPASS_BASE + 0x00BC0000)
+#define LPASS_AON_CC_BASE		(LPASS_BASE + 0x00E08000)
+#define LPASS_AON_CC_PLL_CM_BASE	(LPASS_BASE + 0x00E01000)
+#define LPASS_CORE_GDSC_REG_BASE	(LPASS_BASE + 0x01E00000)
+
 #define RPMH_BASE                       0x17520000
 #define CMD_DB_BASE_ADDR                0x81c60000
 #define CMD_DB_SIZE                     0x20000
diff --git a/src/soc/qualcomm/x1p42100/include/soc/clock.h b/src/soc/qualcomm/x1p42100/include/soc/clock.h
index 73378ce59e..95258eaa85 100644
--- a/src/soc/qualcomm/x1p42100/include/soc/clock.h
+++ b/src/soc/qualcomm/x1p42100/include/soc/clock.h
@@ -60,6 +60,14 @@ enum clk_ctl_gpll_user_ctl_x1p42100 {
 	PLL_POST_DIV_ODD_SHFT_X1P42100 = 14,
 };
 
+enum clk_ctl_lpass_aon_cc_pll_user_ctl_x1p42100 {
+	AON_CC_PLL_PLLOUT_MAIN_SHFT_X1P42100 = 0,
+	AON_CC_PLL_PLLOUT_EVEN_SHFT_X1P42100 = 1,
+	AON_CC_PLL_PLLOUT_ODD_SHFT_X1P42100 = 2,
+	AON_CC_PLL_POST_DIV_EVEN_SHFT_X1P42100 = 10,
+	AON_CC_PLL_POST_DIV_ODD_SHFT_X1P42100 = 14,
+};
+
 enum clk_pll_src {
 	SRC_XO_19_2MHZ = 0,
 	SRC_GPLL0_MAIN_600MHZ = 1,
@@ -193,6 +201,99 @@ struct x1p42100_disp_pll_clock {
 	u32 pll_user_ctl_u;
 };
 
+/* LPASS AON CC PLL register structure */
+struct x1p42100_lpass_aon_cc_pll_clock {
+	u32 pll_mode;
+	u32 pll_opmode;
+	u32 pll_state;
+	u32 pll_status;
+	u32 pll_l_val;
+	u32 pll_alpha_val;
+	u32 pll_user_ctl;
+	u32 pll_user_ctl_u;
+	u32 pll_config_ctl;
+	u32 pll_config_ctl_u;
+	u32 pll_config_ctl_u1;
+	u32 pll_test_ctl;
+	u32 pll_test_ctl_u;
+	u32 pll_test_ctl_u1;
+	u32 pll_test_ctl_u2;
+};
+
+/* LPASS Audio CC register structure */
+struct x1p42100_lpass_audio_cc {
+	u8 _res0[0x28018];
+	u32 codec_ext_mclk0_cbcr;
+	u8 _res1[0xffc];
+	u32 codec_ext_mclk1_cbcr;
+	u8 _res2[0x10b0];
+	u32 wsa_mclk_2x_cbcr;
+	u8 _res3[0x4];
+	u32 wsa_mclk_cbcr;
+	u8 _res4[0x18];
+	u32 tx_mclk_2x_wsa_cbcr;
+	u32 tx_mclk_wsa_cbcr;
+	u8 _res5[0x2f08];
+	u32 wsa2_mclk_2x_cbcr;
+	u32 wsa2_mclk_cbcr;
+	u32 tx_mclk_wsa2_cbcr;
+	u32 tx_mclk_2x_wsa2_cbcr;
+	u8 _res6[0xff0];
+	u32 codec_mem_cbcr;
+	u32 codec_mem0_cbcr;
+	u32 codec_mem0_sregr;
+	u32 codec_mem0_cfg_sregr;
+	u32 codec_mem1_cbcr;
+	u32 codec_mem1_sregr;
+	u32 codec_mem1_cfg_sregr;
+	u32 codec_mem2_cbcr;
+	u32 codec_mem2_sregr;
+	u32 codec_mem2_cfg_sregr;
+	u32 codec_mem3_cbcr;
+	u32 codec_mem3_sregr;
+	u32 codec_mem3_cfg_sregr;
+};
+
+check_member(x1p42100_lpass_audio_cc, codec_ext_mclk0_cbcr, 0x28018);
+check_member(x1p42100_lpass_audio_cc, codec_ext_mclk1_cbcr, 0x29018);
+check_member(x1p42100_lpass_audio_cc, wsa_mclk_2x_cbcr, 0x2A0CC);
+check_member(x1p42100_lpass_audio_cc, wsa_mclk_cbcr, 0x2A0D4);
+check_member(x1p42100_lpass_audio_cc, tx_mclk_2x_wsa_cbcr, 0x2A0F0);
+check_member(x1p42100_lpass_audio_cc, wsa2_mclk_2x_cbcr, 0x2D000);
+check_member(x1p42100_lpass_audio_cc, codec_mem_cbcr, 0x2E000);
+
+/* LPASS Core GDSC register structure */
+struct x1p42100_lpass_core_gdsc {
+	u32 core_hm_gdscr;
+	u8 _res0[0xB4];
+	u32 lpass_core_gds_hm_ready;
+	u8 _res1[0x8F44];
+	u32 lpass_top_cc_lpass_core_sway_ahb_ls_cbcr;
+};
+
+check_member(x1p42100_lpass_core_gdsc, lpass_core_gds_hm_ready, 0x000B8);
+check_member(x1p42100_lpass_core_gdsc, lpass_top_cc_lpass_core_sway_ahb_ls_cbcr, 0x09000);
+
+/* LPASS AON CC register structure */
+struct x1p42100_lpass_aon_cc {
+	u8 _res0[0x9060];
+	u32 va_mem0_cbcr;
+	u8 _res1[0x2c];
+	u32 lpass_audio_hm_gdscr;
+	u8 _res2[0x8F78];
+	u32 va_2x_cbcr;
+	u8 _res3[0x4];
+	u32 va_cbcr;
+	u8 _res4[0xffc];
+	u32 tx_mclk_cbcr;
+};
+
+check_member(x1p42100_lpass_aon_cc, va_mem0_cbcr, 0x9060);
+check_member(x1p42100_lpass_aon_cc, lpass_audio_hm_gdscr, 0x9090);
+check_member(x1p42100_lpass_aon_cc, va_2x_cbcr, 0x1200C);
+check_member(x1p42100_lpass_aon_cc, va_cbcr, 0x12014);
+check_member(x1p42100_lpass_aon_cc, tx_mclk_cbcr, 0x13014);
+
 struct x1p42100_disp_cc {
 	uint8_t _res0[0x00C];
 	uint32_t mdss_mdp_cbcr;
@@ -414,80 +515,82 @@ struct x1p42100_gcc {
 	u32 gcc_aggre_usb3_prim_axi_cbcr;
 	u8  _res36[0x42004 - 0x39094];
 	struct qupv3_clock qup_wrap0_s[8];
-	u8 _res37[0x4b000 - 0x429c4];
+	u8 _res37[0x47000 - 0x429c4];
+	u32 lpass_cfg_noc_sway_cbcr;
+	u8 _res38[0x4b000 - 0x47004];
 	u32 qspi_bcr;
 	u32 qspi_cnoc_ahb_cbcr;
 	u32 qspi_core_cbcr;
 	struct clock_rcg qspi_core;
-	u8 _res38[0x50000 - 0x4b014];
+	u8 _res39[0x50000 - 0x4b014];
 	u32 gcc_usb3_phy_prim_bcr;
 	u32 gcc_usb3phy_phy_prim_bcr;
-	u8 _res39[0x50010 - 0x50008];
+	u8 _res40[0x50010 - 0x50008];
 	u32 gcc_usb4_0_dp0_phy_prim_bcr;
-	u8 _res40[0x52000 - 0x50014];
+	u8 _res41[0x52000 - 0x50014];
 	u32 apcs_clk_br_en;
-	u8 _res41[0x52008 - 0x52004];
+	u8 _res42[0x52008 - 0x52004];
 	u32 apcs_clk_br_en1;
-	u8 _res42[0x52010 - 0x5200c];
+	u8 _res43[0x52010 - 0x5200c];
 	u32 apcs_clk_br_en2;
-	u8 _res43[0x52018 - 0x52014];
+	u8 _res44[0x52018 - 0x52014];
 	u32 apcs_clk_br_en3;
-	u8 _res44[0x52020 - 0x5201c];
+	u8 _res45[0x52020 - 0x5201c];
 	u32 apcs_clk_br_en4;
-	u8 _res45[0x52028 - 0x52024];
+	u8 _res46[0x52028 - 0x52024];
 	u32 apcs_clk_br_en5;
-	u8 _res46[0x52030 - 0x5202c];
+	u8 _res47[0x52030 - 0x5202c];
 	u32 apcs_pll_br_en;
-	u8 _res47[0x54000 - 0x52034];
+	u8 _res48[0x54000 - 0x52034];
 	u32 usb3_uniphy_mp1_bcr;
 	u32 usb3uniphy_phy_mp1_bcr;
 	u32 gcc_usb3_mp_ss1_phy_bcr;
 	u32 gcc_usb3_mp_ss1_phy_gdscr;
-	u8 _res48[0x8e000 - 0x54010];
+	u8 _res49[0x8e000 - 0x54010];
 	u32 pcie_6_phy_gdscr;
-	u8 _res49[0xa1000 - 0x8e004];
+	u8 _res50[0xa1000 - 0x8e004];
 	u32 gcc_usb30_sec_bcr;
 	u32 gcc_usb30_sec_gdscr;
-	u8 _res50[0xa1018 - 0xa1008];
+	u8 _res51[0xa1018 - 0xa1008];
 	u32 gcc_usb30_sec_master_cbcr;
-	u8 _res51[0xa1024 - 0xa101c];
+	u8 _res52[0xa1024 - 0xa101c];
 	u32 gcc_usb30_sec_sleep_cbcr;
 	u32 gcc_usb30_sec_mock_utmi_cbcr;
 	struct clock_rcg usb30_sec_master_rcg;
-	u8 _res52[0xa1060 - 0xa1034];
+	u8 _res53[0xa1060 - 0xa1034];
 	u32 gcc_usb3_sec_phy_aux_cbcr;
 	u32 gcc_usb3_sec_phy_com_aux_cbcr;
 	u32 gcc_usb3_sec_phy_pipe_cbcr;
 	u32 gcc_usb3_sec_phy_pipe_muxr;
-	u8 _res53[0xa108c - 0xa1070];
+	u8 _res54[0xa108c - 0xa1070];
 	u32 gcc_cfg_noc_usb3_sec_axi_cbcr;
 	u32 gcc_aggre_usb3_sec_axi_cbcr;
-	u8 _res54[0xa2000 - 0xa1094];
+	u8 _res55[0xa2000 - 0xa1094];
 	u32 gcc_usb30_tert_bcr;
 	u32 gcc_usb30_tert_gdscr;
-	u8 _res55[0xa2018 - 0xa2008];
+	u8 _res56[0xa2018 - 0xa2008];
 	u32 gcc_usb30_tert_master_cbcr;
-	u8 _res56[0xa2024 - 0xa201c];
+	u8 _res57[0xa2024 - 0xa201c];
 	u32 gcc_usb30_tert_sleep_cbcr;
 	u32 gcc_usb30_tert_mock_utmi_cbcr;
-	u8 _res57[0xa2034 - 0xa202c];
+	u8 _res58[0xa2034 - 0xa202c];
 	u32 gcc_usb30_tert_master_m;
 	u32 gcc_usb30_tert_master_n;
 	u32 gcc_usb30_tert_master_d;
-	u8 _res58[0xa2060 - 0xa2040];
+	u8 _res59[0xa2060 - 0xa2040];
 	u32 gcc_usb3_tert_phy_aux_cbcr;
 	u32 gcc_usb3_tert_phy_com_aux_cbcr;
 	u32 gcc_usb3_tert_phy_pipe_cbcr;
 	u32 gcc_usb3_tert_phy_pipe_muxr;
-	u8 _res59[0xa208c - 0xa2070];
+	u8 _res60[0xa208c - 0xa2070];
 	u32 gcc_cfg_noc_usb3_tert_axi_cbcr;
 	u32 gcc_aggre_usb3_tert_axi_cbcr;
-	u8 _res60[0xa3000 - 0xa2094];
+	u8 _res61[0xa3000 - 0xa2094];
 	u32 gcc_usb3_phy_tert_bcr;
 	u32 gcc_usb3phy_phy_tert_bcr;
-	u8 _res61[0xa3010 - 0xa3008];
+	u8 _res62[0xa3010 - 0xa3008];
 	u32 gcc_usb4_2_dp0_phy_tert_bcr;
-	u8 _res62[0xac01c - 0xa3014];
+	u8 _res63[0xac01c - 0xa3014];
 	u32 pcie_6a_phy_bcr;
 };
 
@@ -536,6 +639,7 @@ check_member(x1p42100_gcc, gcc_aggre_usb_noc_axi_cbcr, 0x2d034);
 check_member(x1p42100_gcc, gcc_aggre_noc_usb_south_axi_cbcr, 0x2d174);
 check_member(x1p42100_gcc, gcc_aggre_noc_usb_north_axi_cbcr, 0x2d17c);
 check_member(x1p42100_gcc, qup_wrap0_s, 0x42004);
+check_member(x1p42100_gcc, lpass_cfg_noc_sway_cbcr, 0x47000);
 check_member(x1p42100_gcc, qspi_bcr, 0x4b000);
 check_member(x1p42100_gcc, apcs_clk_br_en, 0x52000);
 check_member(x1p42100_gcc, apcs_clk_br_en1, 0x52008);
@@ -735,6 +839,29 @@ enum clk_usb_phy_src_sel {
 		USB_PHY_XO_SRC_SEL = 2,
 };
 
+enum clk_lpass {
+	LPASS_CODEC_MEM_CBCR,
+	LPASS_CODEC_MEM0_CBCR,
+	LPASS_CODEC_MEM1_CBCR,
+	LPASS_CODEC_MEM2_CBCR,
+	LPASS_CODEC_MEM3_CBCR,
+	LPASS_EXT_MCLK0_CBCR,
+	LPASS_EXT_MCLK1_CBCR,
+	LPASS_TX_MCLK_CBCR,
+	LPASS_TX_MCLK_2X_WSA_CBCR,
+	LPASS_TX_MCLK_WSA_CBCR,
+	LPASS_WSA_MCLK_2X_CBCR,
+	LPASS_WSA_MCLK_CBCR,
+	LPASS_TX_MCLK_2X_WSA2_CBCR,
+	LPASS_TX_MCLK_WSA2_CBCR,
+	LPASS_WSA2_MCLK_2X_CBCR,
+	LPASS_WSA2_MCLK_CBCR,
+	LPASS_VA_MEM0_CBCR,
+	LPASS_VA_CBCR,
+	LPASS_VA_2X_CBCR,
+	LPASS_CLK_COUNT
+};
+
 enum subsystem_reset {
 	AOP_RESET_SHFT,
 	CORE_SW_RESET,
@@ -760,6 +887,8 @@ enum cb_err usb_sec_clock_enable(enum clk_usb_sec clk_type);
 enum cb_err mdss_clock_enable(enum clk_mdss clk_type);
 enum cb_err disp_pll_init_and_set(struct x1p42100_disp_pll_clock *disp_pll,
 		u32 l_val, u32 alpha_val);
+enum cb_err lpass_init(void);
+
 void clock_configure_dfsr_table_x1p42100(int qup, struct clock_freq_config *clk_cfg,
 		uint32_t num_perfs);
 
@@ -778,6 +907,12 @@ static struct x1p42100_qupv3_wrap *const qup_wrap0_clk = (void *)GCC_QUPV3_WRAP0
 static struct x1p42100_qupv3_wrap *const qup_wrap1_clk = (void *)GCC_QUPV3_WRAP1_BASE;
 static struct x1p42100_qupv3_wrap *const qup_wrap2_clk = (void *)GCC_QUPV3_WRAP2_BASE;
 
+/* Static pointers to LPASS register blocks */
+static struct x1p42100_lpass_audio_cc *const lpass_audio_cc = (void *)LPASS_AUDIO_CC_PLL_BASE;
+static struct x1p42100_lpass_aon_cc *const lpass_aon_cc = (void *)LPASS_AON_CC_BASE;
+static struct x1p42100_lpass_aon_cc_pll_clock *const lpass_aon_cc_pll = (void *)LPASS_AON_CC_PLL_CM_BASE;
+static struct x1p42100_lpass_core_gdsc *const lpass_core_gdsc = (void *)LPASS_CORE_GDSC_REG_BASE;
+
 /* Does nothing */
 #define clock_reset_aop() do {} while (0)
 /* Does nothing */
diff --git a/src/soc/qualcomm/x1p42100/include/soc/lpass.h b/src/soc/qualcomm/x1p42100/include/soc/lpass.h
new file mode 100644
index 0000000000..79439e4ba7
--- /dev/null
+++ b/src/soc/qualcomm/x1p42100/include/soc/lpass.h
@@ -0,0 +1,27 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef _SOC_QUALCOMM_X1P42100_LPASS_H_
+#define _SOC_QUALCOMM_X1P42100_LPASS_H_
+
+#include <types.h>
+
+/* LPASS AON CC PLL Settings */
+#define HAL_CLK_LPASS_AON_CC_PLL_L_VALUE	0x00000020
+#define HAL_CLK_LPASS_AON_CC_PLL_ALPHA_VALUE	0x00000000
+#define HAL_CLK_LPASS_AON_CC_PLL_CAL_L_VALUE	0x00000044
+#define HAL_CLK_LPASS_AON_CC_PLL_CONFIG_CTL	0x20485699
+#define HAL_CLK_LPASS_AON_CC_PLL_CONFIG_CTL_U	0x00182261
+#define HAL_CLK_LPASS_AON_CC_PLL_CONFIG_CTL_U1	0x82AA299C
+#define HAL_CLK_LPASS_AON_CC_PLL_TEST_CTL	0x00000000
+#define HAL_CLK_LPASS_AON_CC_PLL_TEST_CTL_U	0x00000003
+#define HAL_CLK_LPASS_AON_CC_PLL_TEST_CTL_U1	0x00009000
+#define HAL_CLK_LPASS_AON_CC_PLL_TEST_CTL_U2	0x00000034
+#define HAL_CLK_LPASS_AON_CC_PLL_USER_CTL	0x00E00041
+#define HAL_CLK_LPASS_AON_CC_PLL_USER_CTL_U	0x00000105
+
+#define LPASS_CORE_HM_READY			BIT(0)
+#define HW_CTL					BIT(1)
+#define GDSC_ENABLE_BIT				0
+
+#define BCM_LP0_VOTE_VALUE			0x60004001
+#endif /* _SOC_QUALCOMM_X1P42100_LPASS_H_ */
diff --git a/src/soc/qualcomm/x1p42100/lpass.c b/src/soc/qualcomm/x1p42100/lpass.c
new file mode 100644
index 0000000000..437a888cb0
--- /dev/null
+++ b/src/soc/qualcomm/x1p42100/lpass.c
@@ -0,0 +1,147 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <console/console.h>
+#include <device/mmio.h>
+#include <soc/clock.h>
+#include <soc/lpass.h>
+#include <soc/rpmh_bcm.h>
+#include <timer.h>
+
+static enum cb_err lpass_aon_cc_pll_enable(void)
+{
+	struct alpha_pll_reg_val_config pll_cfg = {0};
+
+	pll_cfg.reg_mode = &lpass_aon_cc_pll->pll_mode;
+	pll_cfg.reg_l = &lpass_aon_cc_pll->pll_l_val;
+	pll_cfg.l_val = HAL_CLK_LPASS_AON_CC_PLL_L_VALUE;
+
+	pll_cfg.reg_alpha = &lpass_aon_cc_pll->pll_alpha_val;
+	pll_cfg.alpha_val = HAL_CLK_LPASS_AON_CC_PLL_ALPHA_VALUE;
+
+	pll_cfg.reg_cal_l = &lpass_aon_cc_pll->pll_l_val;
+	pll_cfg.cal_l_val = HAL_CLK_LPASS_AON_CC_PLL_CAL_L_VALUE;
+
+	pll_cfg.reg_config_ctl = &lpass_aon_cc_pll->pll_config_ctl;
+	pll_cfg.config_ctl_val = HAL_CLK_LPASS_AON_CC_PLL_CONFIG_CTL;
+	pll_cfg.reg_config_ctl_hi = &lpass_aon_cc_pll->pll_config_ctl_u;
+	pll_cfg.config_ctl_hi_val = HAL_CLK_LPASS_AON_CC_PLL_CONFIG_CTL_U;
+	pll_cfg.reg_config_ctl_hi1 = &lpass_aon_cc_pll->pll_config_ctl_u1;
+	pll_cfg.config_ctl_hi1_val = HAL_CLK_LPASS_AON_CC_PLL_CONFIG_CTL_U1;
+
+	pll_cfg.reg_user_ctl = &lpass_aon_cc_pll->pll_user_ctl;
+	pll_cfg.user_ctl_val = HAL_CLK_LPASS_AON_CC_PLL_USER_CTL;
+	pll_cfg.reg_user_ctl_hi = &lpass_aon_cc_pll->pll_user_ctl_u;
+	pll_cfg.user_ctl_hi_val = HAL_CLK_LPASS_AON_CC_PLL_USER_CTL_U;
+
+	pll_cfg.reg_opmode = &lpass_aon_cc_pll->pll_opmode;
+
+	if (clock_configure_enable_gpll(&pll_cfg, false, 0) != CB_SUCCESS) {
+		printk(BIOS_ERR, "LPASS: AON CC PLL configuration failed\n");
+		return CB_ERR;
+	}
+
+	write32(&lpass_aon_cc_pll->pll_test_ctl, HAL_CLK_LPASS_AON_CC_PLL_TEST_CTL);
+	write32(&lpass_aon_cc_pll->pll_test_ctl_u, HAL_CLK_LPASS_AON_CC_PLL_TEST_CTL_U);
+	write32(&lpass_aon_cc_pll->pll_test_ctl_u1, HAL_CLK_LPASS_AON_CC_PLL_TEST_CTL_U1);
+	write32(&lpass_aon_cc_pll->pll_test_ctl_u2, HAL_CLK_LPASS_AON_CC_PLL_TEST_CTL_U2);
+
+	if (lucidole_pll_enable(&pll_cfg) != CB_SUCCESS) {
+		printk(BIOS_ERR, "LPASS: AON CC PLL enable failed\n");
+		return CB_ERR;
+	}
+
+	setbits32(&lpass_aon_cc_pll->pll_user_ctl, (BIT(AON_CC_PLL_PLLOUT_EVEN_SHFT_X1P42100) |
+				BIT(AON_CC_PLL_PLLOUT_ODD_SHFT_X1P42100)));
+
+	return CB_SUCCESS;
+}
+
+static enum cb_err lpass_setup_core_infrastructure(void)
+{
+
+	if (clock_enable(&gcc->lpass_cfg_noc_sway_cbcr) != CB_SUCCESS) {
+		printk(BIOS_ERR, "LPASS: Failed to enable CFG NOC SWAY clock\n");
+		return CB_ERR;
+	}
+
+	setbits32(&lpass_core_gdsc->lpass_top_cc_lpass_core_sway_ahb_ls_cbcr, HW_CTL);
+
+	if (enable_and_poll_gdsc_status(&lpass_core_gdsc->core_hm_gdscr) != CB_SUCCESS) {
+		printk(BIOS_ERR, "LPASS: Failed to enable Core HM GDSC\n");
+		return CB_ERR;
+	}
+
+	if (!wait_us(1000000, read32(&lpass_core_gdsc->lpass_core_gds_hm_ready) & LPASS_CORE_HM_READY)) {
+		printk(BIOS_ERR, "LPASS: Core HM ready timeout\n");
+		return CB_ERR;
+	}
+
+	return CB_SUCCESS;
+}
+
+static u32 *lpass_cbcr[LPASS_CLK_COUNT] = {
+	[LPASS_CODEC_MEM_CBCR] = &lpass_audio_cc->codec_mem_cbcr,
+	[LPASS_CODEC_MEM0_CBCR] = &lpass_audio_cc->codec_mem0_cbcr,
+	[LPASS_CODEC_MEM1_CBCR] = &lpass_audio_cc->codec_mem1_cbcr,
+	[LPASS_CODEC_MEM2_CBCR] = &lpass_audio_cc->codec_mem2_cbcr,
+	[LPASS_CODEC_MEM3_CBCR] = &lpass_audio_cc->codec_mem3_cbcr,
+	[LPASS_EXT_MCLK0_CBCR] = &lpass_audio_cc->codec_ext_mclk0_cbcr,
+	[LPASS_EXT_MCLK1_CBCR] = &lpass_audio_cc->codec_ext_mclk1_cbcr,
+	[LPASS_TX_MCLK_CBCR] = &lpass_aon_cc->tx_mclk_cbcr,
+	[LPASS_TX_MCLK_2X_WSA_CBCR] = &lpass_audio_cc->tx_mclk_2x_wsa_cbcr,
+	[LPASS_TX_MCLK_WSA_CBCR] = &lpass_audio_cc->tx_mclk_wsa_cbcr,
+	[LPASS_WSA_MCLK_2X_CBCR] = &lpass_audio_cc->wsa_mclk_2x_cbcr,
+	[LPASS_WSA_MCLK_CBCR] = &lpass_audio_cc->wsa_mclk_cbcr,
+	[LPASS_TX_MCLK_2X_WSA2_CBCR] = &lpass_audio_cc->tx_mclk_2x_wsa2_cbcr,
+	[LPASS_TX_MCLK_WSA2_CBCR] = &lpass_audio_cc->tx_mclk_wsa2_cbcr,
+	[LPASS_WSA2_MCLK_2X_CBCR] = &lpass_audio_cc->wsa2_mclk_2x_cbcr,
+	[LPASS_WSA2_MCLK_CBCR] = &lpass_audio_cc->wsa2_mclk_cbcr,
+	[LPASS_VA_MEM0_CBCR] = &lpass_aon_cc->va_mem0_cbcr,
+	[LPASS_VA_CBCR] = &lpass_aon_cc->va_cbcr,
+	[LPASS_VA_2X_CBCR] = &lpass_aon_cc->va_2x_cbcr,
+};
+
+static enum cb_err lpass_audio_clocks_enable(void)
+{
+	for (size_t i = 0; i < LPASS_CLK_COUNT; i++) {
+		if (clock_enable(lpass_cbcr[i]) != CB_SUCCESS) {
+			printk(BIOS_ERR, "LPASS: Failed to enable audio clock\n");
+			return CB_ERR;
+		}
+	}
+
+	return CB_SUCCESS;
+}
+
+enum cb_err lpass_init(void)
+{
+	int rc;
+	rc = rpmh_bcm_vote("LP0", BCM_LP0_VOTE_VALUE);
+	if (rc) {
+		printk(BIOS_ERR, "LPASS: Failed to send BCM vote for LPASS bus clock manager LP0\n");
+		return CB_ERR;
+	}
+
+	if (enable_and_poll_gdsc_status(&lpass_aon_cc->lpass_audio_hm_gdscr) != CB_SUCCESS) {
+		printk(BIOS_ERR, "LPASS: Failed to enable Core HM GDSC\n");
+		return CB_ERR;
+	}
+
+	if (lpass_setup_core_infrastructure() != CB_SUCCESS) {
+		printk(BIOS_ERR, "LPASS: Failed to setup core infrastructure\n");
+		return CB_ERR;
+	}
+
+	if (lpass_aon_cc_pll_enable() != CB_SUCCESS) {
+		printk(BIOS_ERR, "LPASS: Failed to enable AON CC PLL\n");
+		return CB_ERR;
+	}
+
+	if (lpass_audio_clocks_enable() != CB_SUCCESS) {
+		printk(BIOS_ERR, "LPASS: Failed to enable audio clocks\n");
+		return CB_ERR;
+	}
+
+	printk(BIOS_INFO, "LPASS: BCM vote for LP0 and LPASS Init completed successfully\n");
+	return CB_SUCCESS;
+}

From dec1dfe1601d26a6abc6bde0904c7fbb7ed719df Mon Sep 17 00:00:00 2001
From: Swathi Tamilselvan <tswathi@qualcomm.corp-partner.google.com>
Date: Tue, 20 Jan 2026 16:32:00 +0530
Subject: [PATCH 3109/3886] mb/google/bluey: Add support to invoke LPASS Init
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Add support in mainboard to invoke LPASS Initialization.

Test=1. Create an image.serial.bin and ensure it boots on X1P42100.
2. Verified LP0 BCM vote using serial logs.
Serial Log:
[DEBUG]  BCM: Found address 0x00050048 for resource LP0
[INFO ]  BCM: Successfully voted for LP0 (addr=0x00050048, val=0x60004001)
3. Verified if the clocks are enabled by taking clock dump. Clock
enablement is verified by dumping the 31st bit of the corresponding
clock’s CBCR register. A value of 0 in bit 31 indicates that the clock
is ON. The register details are part of HRD-X1P42100-S1 document.
https://docs.qualcomm.com/bundle/resource/topics/HRD-X1P42100-S1/

Change-Id: Icdcb8176639d4c6d24ab6cd2741d7e44e2370eb0
Signed-off-by: Swathi Tamilselvan <tswathi@qualcomm.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90852
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
---
 src/mainboard/google/bluey/mainboard.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/src/mainboard/google/bluey/mainboard.c b/src/mainboard/google/bluey/mainboard.c
index ea0e8a4851..ad02b2ea3c 100644
--- a/src/mainboard/google/bluey/mainboard.c
+++ b/src/mainboard/google/bluey/mainboard.c
@@ -203,6 +203,8 @@ static void mainboard_init(struct device *dev)
 	setup_usb();
 
 	display_startup();
+
+	lpass_init();
 }
 
 static void mainboard_enable(struct device *dev)

From f84a676cc7f522c166f0ef852544784d42e6ee7d Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Wed, 21 Jan 2026 21:46:19 +0000
Subject: [PATCH 3110/3886] src/lib/smbios: Advertise UEFI support for EDK2

fwupd checks SMBIOS Type 0 BIOS Characteristics Extension Byte 2 bit 3
(UEFI Specification Supported) when deciding if UEFI capsule updates are
supported.

Set the flag when coreboot is built with the EDK2 payload.

Change-Id: I4d24deeca88cde5411225f8d113704f5a04e8a34
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90860
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
---
 src/include/smbios.h | 1 +
 src/lib/smbios.c     | 3 +++
 2 files changed, 4 insertions(+)

diff --git a/src/include/smbios.h b/src/include/smbios.h
index b9dbc0bdf6..103e85b9af 100644
--- a/src/include/smbios.h
+++ b/src/include/smbios.h
@@ -123,6 +123,7 @@ int smbios_write_type8(unsigned long *current, int *handle,
 
 #define BIOS_EXT1_CHARACTERISTICS_ACPI		(1 << 0)
 #define BIOS_EXT2_CHARACTERISTICS_TARGET	(1 << 2)
+#define BIOS_EXT2_CHARACTERISTICS_UEFI_SUPPORT	(1 << 3)
 
 #define BIOS_MEMORY_ECC_SINGLE_BIT_CORRECTING	(1 << 3)
 #define BIOS_MEMORY_ECC_DOUBLE_BIT_CORRECTING	(1 << 4)
diff --git a/src/lib/smbios.c b/src/lib/smbios.c
index 7da3e2ad15..35b4d7765f 100644
--- a/src/lib/smbios.c
+++ b/src/lib/smbios.c
@@ -412,6 +412,9 @@ static int smbios_write_type0(unsigned long *current, int handle)
 		t->bios_characteristics_ext1 = BIOS_EXT1_CHARACTERISTICS_ACPI;
 
 	t->bios_characteristics_ext2 = BIOS_EXT2_CHARACTERISTICS_TARGET;
+	if (CONFIG(PAYLOAD_EDK2))
+		t->bios_characteristics_ext2 |= BIOS_EXT2_CHARACTERISTICS_UEFI_SUPPORT;
+
 	const int len = smbios_full_table_len(&t->header, t->eos);
 	*current += len;
 	return len;

From 56922d914ba7687fb41434b7806b4b56affb5f2d Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Micha=C5=82=20=C5=BBygowski?= <michal.zygowski@3mdeb.com>
Date: Wed, 21 Jan 2026 15:19:32 +0100
Subject: [PATCH 3111/3886] soc/amd/common/block/lpc: Report ESPI1 MMIO
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

ESPI1 MMIO is reported in ACPI already, but the resource allocator
must also know about it to avoid the allocation of resources in that
range.

TEST=Boot Gigabyte MZ33-AR1 and verify that ESPI1 address (0xfec30000)
is reported for PCI device 00:00.14.3 in coreboot logs:
dev: PCI: 00:00:14.3, index: 0x3, base: 0xfec30000, size: 0x1000

Change-Id: Ic4024e6aa37bd7568dcecbd7cae29be9ae587a7f
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90853
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
---
 src/soc/amd/common/block/include/amdblocks/espi.h | 1 +
 src/soc/amd/common/block/lpc/lpc.c                | 4 ++++
 2 files changed, 5 insertions(+)

diff --git a/src/soc/amd/common/block/include/amdblocks/espi.h b/src/soc/amd/common/block/include/amdblocks/espi.h
index b7ab06ee55..5781dea3af 100644
--- a/src/soc/amd/common/block/include/amdblocks/espi.h
+++ b/src/soc/amd/common/block/include/amdblocks/espi.h
@@ -7,6 +7,7 @@
 
 /* eSPI MMIO base lives at an offset of 0x10000 from the address in SPI BAR. */
 #define ESPI_OFFSET_FROM_BAR			0x10000
+#define ESPI1_OFFSET_FROM_BAR			0x20000
 
 #define ESPI_DECODE				0x40
 /* more bits defined in soc/common/amd/blocks/lpc/espi_def.h */
diff --git a/src/soc/amd/common/block/lpc/lpc.c b/src/soc/amd/common/block/lpc/lpc.c
index 2392d5f3e8..1aa81f66ca 100644
--- a/src/soc/amd/common/block/lpc/lpc.c
+++ b/src/soc/amd/common/block/lpc/lpc.c
@@ -123,6 +123,10 @@ static void lpc_read_resources(struct device *dev)
 	/* Add a memory resource for the eSPI MMIO */
 	mmio_range(dev, idx++, SPI_BASE_ADDRESS + ESPI_OFFSET_FROM_BAR, 4 * KiB);
 
+	/* Add a memory resource for the eSPI1 MMIO */
+	if (CONFIG(SOC_AMD_COMMON_BLOCK_HAS_ESPI1))
+		mmio_range(dev, idx++, SPI_BASE_ADDRESS + ESPI1_OFFSET_FROM_BAR, 4 * KiB);
+
 	/* FCH IOAPIC */
 	mmio_range(dev, idx++, IO_APIC_ADDR, 4 * KiB);
 

From 68551a79ce8fb36543664feb86c7ec1134dcfa89 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Micha=C5=82=20=C5=BBygowski?= <michal.zygowski@3mdeb.com>
Date: Tue, 8 Jul 2025 19:13:46 +0200
Subject: [PATCH 3112/3886] soc/amd/turin_poc: Adjust sources for Turin SOC
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Update the SOC code based on the PPR for C1 stepping, doc 57238.

1. Turin CPU has less USB ports than Genoa, so the chip structure has
   to reflect that. The number of ports has been reduced to match the
   hardware capabilities.
2. Added early FCH initialization: legacy ISA devices, eSPI, I/O
   decoding, UARTs, SMBus and SPI.
3. Updated AOAC device numbers.
4. Updated MMIO and I/O base addresses for CPU internal devices.
5. Added reserved RAM and MMIO reporting.
6. Adjusted root complex layout to match Turin IOHCs base addresses
   and fabric IDs.
7. Extended chipset.cb devicetree to match the layout of devices on a
   single socket Turin system.

Change-Id: I5272c1f2cd2aa259569d0bc6fa5c4073907b1673
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88708
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
---
 src/soc/amd/turin_poc/Kconfig                 | 102 ++++-
 src/soc/amd/turin_poc/Makefile.mk             |  27 +-
 src/soc/amd/turin_poc/acpi.c                  |   4 +-
 src/soc/amd/turin_poc/acpi/mmio.asl           | 231 +++++++++++
 src/soc/amd/turin_poc/acpi/pci_int_defs.asl   |  36 +-
 src/soc/amd/turin_poc/acpi/resources.asl      |  68 ++++
 src/soc/amd/turin_poc/acpi/soc.asl            |  11 +-
 src/soc/amd/turin_poc/chip.c                  |   3 +
 src/soc/amd/turin_poc/chip.h                  |  19 +-
 src/soc/amd/turin_poc/chipset.cb              | 382 ++++++++++--------
 src/soc/amd/turin_poc/cpu.c                   |   5 +-
 src/soc/amd/turin_poc/domain.c                |  39 +-
 src/soc/amd/turin_poc/early_fch.c             |  77 +++-
 src/soc/amd/turin_poc/fch.c                   |  78 +++-
 src/soc/amd/turin_poc/gpio.c                  |   1 +
 .../turin_poc/include/soc/amd_pci_int_defs.h  |  24 +-
 src/soc/amd/turin_poc/include/soc/aoac_defs.h |   8 +-
 src/soc/amd/turin_poc/include/soc/cpu.h       |   5 +-
 .../amd/turin_poc/include/soc/data_fabric.h   |  22 +-
 src/soc/amd/turin_poc/include/soc/gpio.h      |  91 +++--
 src/soc/amd/turin_poc/include/soc/iomap.h     |  28 +-
 src/soc/amd/turin_poc/include/soc/msr.h       |   4 +-
 src/soc/amd/turin_poc/include/soc/smi.h       |   3 +-
 src/soc/amd/turin_poc/include/soc/smu.h       |  10 +-
 .../amd/turin_poc/include/soc/southbridge.h   |   9 +-
 src/soc/amd/turin_poc/include/soc/xhci.h      |  17 +
 src/soc/amd/turin_poc/mca.c                   |  28 +-
 src/soc/amd/turin_poc/root_complex.c          |  65 ++-
 src/soc/amd/turin_poc/smihandler.c            |   1 +
 src/soc/amd/turin_poc/uart.c                  |   4 +
 30 files changed, 1103 insertions(+), 299 deletions(-)
 create mode 100644 src/soc/amd/turin_poc/acpi/resources.asl
 create mode 100644 src/soc/amd/turin_poc/include/soc/xhci.h

diff --git a/src/soc/amd/turin_poc/Kconfig b/src/soc/amd/turin_poc/Kconfig
index 55af8c71e6..8eadb04933 100644
--- a/src/soc/amd/turin_poc/Kconfig
+++ b/src/soc/amd/turin_poc/Kconfig
@@ -10,23 +10,39 @@ config SOC_SPECIFIC_OPTIONS
 	select ACPI_SOC_NVS
 	select ARCH_X86
 	select DEFAULT_X2APIC
+	select BOOT_DEVICE_SUPPORTS_WRITES if BOOT_DEVICE_SPI_FLASH
+	select CACHE_MRC_SETTINGS
+	select DRIVERS_USB_ACPI
+	select DRIVERS_USB_PCI_XHCI
+	select GENERIC_GPIO_LIB
 	select HAVE_ACPI_TABLES
+	select HAVE_CF9_RESET
+	select HAVE_EM100_SUPPORT
 	select HAVE_X86_64_SUPPORT
-	select HAVE_SMI_HANDLER
+	select HAVE_SMI_HANDLER if !NO_SMM
+	select IDT_IN_EVERY_STAGE
+	select PARALLEL_MP_AP_WORK
+	select PROVIDES_ROM_SHARING
+	select RTC
 	select SOC_AMD_COMMON
 	select SOC_AMD_COMMON_BLOCK_ACPI
 	select SOC_AMD_COMMON_BLOCK_ACPIMMIO
+	select SOC_AMD_COMMON_BLOCK_ACPIMMIO_PM_IO_ACCESS
 	select SOC_AMD_COMMON_BLOCK_ACPI_CPU_POWER_STATE
 	select SOC_AMD_COMMON_BLOCK_ACPI_IVRS
 	select SOC_AMD_COMMON_BLOCK_ACPI_MADT
 	select SOC_AMD_COMMON_BLOCK_AOAC
+	select SOC_AMD_COMMON_BLOCK_APOB
 	select SOC_AMD_COMMON_BLOCK_BANKED_GPIOS
-	select SOC_AMD_COMMON_BLOCK_CPUFREQ_FAM17H_19H
+	select SOC_AMD_COMMON_BLOCK_CPUFREQ_FAM1AH
 	select SOC_AMD_COMMON_BLOCK_DATA_FABRIC
 	select SOC_AMD_COMMON_BLOCK_DATA_FABRIC_DOMAIN
 	select SOC_AMD_COMMON_BLOCK_DATA_FABRIC_MULTI_PCI_SEGMENT
 	select SOC_AMD_COMMON_BLOCK_DATA_FABRIC_EXTENDED_MMIO
 	select SOC_AMD_COMMON_BLOCK_HAS_ESPI
+	select SOC_AMD_COMMON_BLOCK_HAS_ESPI_ALERT_ENABLE
+	select SOC_AMD_COMMON_BLOCK_ESPI_EXTENDED_DECODE_RANGES
+	select SOC_AMD_COMMON_BLOCK_ESPI_RETAIN_PORT80_EN
 	select SOC_AMD_COMMON_BLOCK_I2C
 	select SOC_AMD_COMMON_BLOCK_I3C
 	select SOC_AMD_COMMON_BLOCK_IOMMU
@@ -35,8 +51,11 @@ config SOC_SPECIFIC_OPTIONS
 	select SOC_AMD_COMMON_BLOCK_NONCAR
 	select SOC_AMD_COMMON_BLOCK_PCI
 	select SOC_AMD_COMMON_BLOCK_PCI_MMCONF
+	select SOC_AMD_COMMON_BLOCK_PM
 	select SOC_AMD_COMMON_BLOCK_PSP_GEN2
+	select SOC_AMD_COMMON_BLOCK_PSP_SMI
 	select SOC_AMD_COMMON_BLOCK_PSP_SPL
+	select SOC_AMD_COMMON_BLOCK_SMBUS
 	select SOC_AMD_COMMON_BLOCK_SMI
 	select SOC_AMD_COMMON_BLOCK_SMM
 	select SOC_AMD_COMMON_BLOCK_SMU
@@ -47,8 +66,15 @@ config SOC_SPECIFIC_OPTIONS
 	select SOC_AMD_COMMON_BLOCK_UART
 	select SOC_AMD_COMMON_BLOCK_UCODE
 	select SOC_AMD_COMMON_BLOCK_USE_ESPI
+	select SOC_AMD_COMMON_BLOCK_XHCI
 	select SOC_AMD_OPENSIL
 	select OPENSIL_DRIVER
+	select DRAM_SUPPORT_DDR5
+	select SSE2
+	select X86_AMD_FIXED_MTRRS
+	select X86_INIT_NEED_1_SIPI
+	select VBOOT_X86_SHA256_ACCELERATION if VBOOT
+	select UDK_2017_BINDING
 
 config USE_X86_64_SUPPORT
 	default y
@@ -73,7 +99,11 @@ config EARLY_RESERVED_DRAM_BASE
 
 config EARLYRAM_BSP_STACK_SIZE
 	hex
-	default 0x1000
+	default 0x10000
+
+config STACK_SIZE
+	hex
+	default 0x10000
 
 config MAX_CPUS
 	int
@@ -81,14 +111,18 @@ config MAX_CPUS
 
 config PSP_APOB_DRAM_ADDRESS
 	hex
-	default 0x7001000
+	default 0x7010000
 	help
 	  Location in DRAM where the PSP will copy the AGESA PSP Output
 	  Block.
 
 config PSP_APOB_DRAM_SIZE
 	hex
-	default 0x20000
+	default 0xd0000
+
+config MRC_SETTINGS_CACHE_SIZE
+	hex
+	default 0xd0000
 
 config PRERAM_CBMEM_CONSOLE_SIZE
 	hex
@@ -106,7 +140,7 @@ config C_ENV_BOOTBLOCK_SIZE
 
 config ROMSTAGE_ADDR
 	hex
-	default 0x7050000
+	default 0x7150000
 	help
 	  Sets the address in DRAM where romstage should be loaded.
 
@@ -124,6 +158,14 @@ config ECAM_MMCONF_BUS_NUMBER
 	int
 	default 256
 
+config DISABLE_KEYBOARD_RESET_PIN
+	bool
+	help
+	  Instruct the SoC to not use the state of GPIO_129 as keyboard reset.
+
+config CPU_PT_ROM_MAP_GB
+	default 1024
+
 menu "PSP Configuration Options"
 
 config AMDFW_CONFIG_FILE
@@ -141,7 +183,7 @@ config PSP_INIT_ESPI
 	  Select to initialize the eSPI controller in the PSP Stage 2 Boot
 	  Loader.
 
-config	PSP_UNLOCK_SECURE_DEBUG
+config PSP_UNLOCK_SECURE_DEBUG
 	bool
 	default y
 
@@ -171,6 +213,11 @@ config PSP_SOFTFUSE_BITS
 	          0=SoC MMIO UART, 1=IO port 0x3F8
 
 	  See #57299 (NDA) for additional bit definitions.
+
+config PSPV2_MBOX_CMD_OFFSET
+	hex
+	default 0x10970
+
 endmenu
 
 config CONSOLE_UART_BASE_ADDRESS
@@ -179,6 +226,7 @@ config CONSOLE_UART_BASE_ADDRESS
 	default 0xfedc9000 if UART_FOR_CONSOLE = 0
 	default 0xfedca000 if UART_FOR_CONSOLE = 1
 	default 0xfedce000 if UART_FOR_CONSOLE = 2
+	default 0xfedcf000 if UART_FOR_CONSOLE = 3
 
 config SMM_TSEG_SIZE
 	hex
@@ -208,4 +256,44 @@ config ACPI_BERT_SIZE
 	  Specify the amount of DRAM reserved for gathering the data used to
 	  generate the ACPI table.
 
+config ASYNC_FILE_LOADING
+	bool "Loads files from SPI asynchronously"
+	select COOP_MULTITASKING
+	select SOC_AMD_COMMON_BLOCK_LPC_SPI_DMA
+	select CBFS_PRELOAD
+	help
+	  When enabled, the platform will use the LPC SPI DMA controller to
+	  asynchronously load contents from the SPI ROM. This will improve
+	  boot time because the CPUs can be performing useful work while the
+	  SPI contents are being preloaded.
+
+config CBFS_CACHE_SIZE
+	hex
+	default 0x40000 if CBFS_PRELOAD
+
+config VBOOT
+	select VBOOT_STARTS_IN_BOOTBLOCK
+	select VBOOT_VBNV_CMOS
+	select VBOOT_VBNV_CMOS_BACKUP_TO_FLASH
+
+config RO_REGION_ONLY
+	string
+	depends on VBOOT_SLOTS_RW_AB || VBOOT_SLOTS_RW_A
+	default "apu/amdfw"
+
+config DISABLE_SPI_FLASH_ROM_SHARING
+	def_bool n
+	help
+	  Instruct the chipset to not honor the EGPIO67_SPI_ROM_REQ pin
+	  which indicates a board level ROM transaction request. This
+	  removes arbitration with board and assumes the chipset controls
+	  the SPI flash bus entirely.
+
+config SERIRQ_CONTINUOUS_MODE
+	bool
+	default n
+	help
+	  Set this option to y for serial IRQ in continuous mode.
+	  Otherwise it is in quiet mode.
+
 endif # SOC_AMD_TURIN_POC
diff --git a/src/soc/amd/turin_poc/Makefile.mk b/src/soc/amd/turin_poc/Makefile.mk
index ab4d40f257..68144574c2 100644
--- a/src/soc/amd/turin_poc/Makefile.mk
+++ b/src/soc/amd/turin_poc/Makefile.mk
@@ -32,6 +32,7 @@ ifeq ($(call int-gt, $(CONFIG_ROM_SIZE) 0x1000000), 1)
 CBFSTOOL_ADD_CMD_OPTIONS+= --mmap 0:0xff000000:0x1000000
 endif
 
+ifneq ($(call strip_quotes, $(CONFIG_AMDFW_CONFIG_FILE)),)
 #
 # PSP Directory Table items
 #
@@ -79,6 +80,14 @@ PSP_ELF_FILE=$(objcbfs)/bootblock_fixed_data.elf
 PSP_BIOSBIN_SIZE=$(shell $(READELF_bootblock) -Wl $(PSP_ELF_FILE) | grep LOAD | awk '{print $$5}')
 PSP_BIOSBIN_DEST=$(shell $(READELF_bootblock) -Wl $(PSP_ELF_FILE) | grep LOAD | awk '{print $$3}')
 
+ifneq ($(CONFIG_SOC_AMD_COMMON_BLOCK_APOB_NV_DISABLE),y)
+# type = 0x63 - construct APOB NV base/size from flash map
+# The flashmap section used for this is expected to be named RW_MRC_CACHE
+# Size should be 0xD0000
+APOB_NV_SIZE=$(call get_fmap_value,FMAP_SECTION_RW_MRC_CACHE_SIZE)
+APOB_NV_BASE=$(call get_fmap_value,FMAP_SECTION_RW_MRC_CACHE_START)
+endif # !CONFIG_SOC_AMD_COMMON_BLOCK_APOB_NV_DISABLE
+
 # Helper function to return a value with given bit set
 # Soft Fuse type = 0xb - See #57299 (NDA) for bit definitions.
 set-bit=$(call int-shift-left, 1 $(call _toint,$1))
@@ -104,6 +113,9 @@ OPT_PSP_BIOSBIN_FILE=$(call add_opt_prefix, $(PSP_BIOSBIN_FILE), --bios-bin)
 OPT_PSP_BIOSBIN_DEST=$(call add_opt_prefix, $(PSP_BIOSBIN_DEST), --bios-bin-dest)
 OPT_PSP_BIOSBIN_SIZE=$(call add_opt_prefix, $(PSP_BIOSBIN_SIZE), --bios-uncomp-size)
 
+OPT_APOB_NV_SIZE=$(call add_opt_prefix, $(APOB_NV_SIZE), --apob-nv-size)
+OPT_APOB_NV_BASE=$(call add_opt_prefix, $(APOB_NV_BASE), --apob-nv-base)
+
 OPT_EFS_SPI_READ_MODE=$(call add_opt_prefix, $(CONFIG_EFS_SPI_READ_MODE), --spi-read-mode)
 OPT_EFS_SPI_SPEED=$(call add_opt_prefix, $(CONFIG_EFS_SPI_SPEED), --spi-speed)
 OPT_EFS_SPI_MICRON_FLAG=$(call add_opt_prefix, $(CONFIG_EFS_SPI_MICRON_FLAG), --spi-micron-flag)
@@ -112,14 +124,22 @@ OPT_PSP_SOFTFUSE=$(call add_opt_prefix, $(PSP_SOFTFUSE), --soft-fuse)
 OPT_WHITELIST_FILE=$(call add_opt_prefix, $(PSP_WHITELIST_FILE), --whitelist)
 OPT_SPL_TABLE_FILE=$(call add_opt_prefix, $(SPL_TABLE_FILE), --spl-table)
 
+OPT_UCODE_FILES=$(foreach i, $(shell seq $(words $(amd_microcode_bins))), \
+	$(call add_opt_prefix, $(word $(i), $(amd_microcode_bins)), \
+	--instance $(shell printf "%x" $$(($(i)-1))) --ucode))
+
 AMDFW_COMMON_ARGS=$(OPT_PSP_APCB_FILES) \
 		$(OPT_APOB_ADDR) \
+		$(OPT_APOB_NV_SIZE) \
+		$(OPT_APOB_NV_BASE) \
+		$(OPT_UCODE_FILES) \
 		$(OPT_DEBUG_AMDFWTOOL) \
 		$(OPT_PSP_BIOSBIN_FILE) \
 		$(OPT_PSP_BIOSBIN_DEST) \
 		$(OPT_PSP_BIOSBIN_SIZE) \
 		$(OPT_PSP_SOFTFUSE) \
 		--use-pspsecureos \
+		--load-s0i3 \
 		$(OPT_TOKEN_UNLOCK) \
 		$(OPT_WHITELIST_FILE) \
 		$(OPT_SPL_TABLE_FILE) \
@@ -127,11 +147,12 @@ AMDFW_COMMON_ARGS=$(OPT_PSP_APCB_FILES) \
 		$(OPT_EFS_SPI_SPEED) \
 		$(OPT_EFS_SPI_MICRON_FLAG) \
 		--config $(CONFIG_AMDFW_CONFIG_FILE) \
-		--flashsize 0x1000000
+		--flashsize $(call strip_quotes, $(CONFIG_ROM_SIZE))
 
 $(obj)/amdfw.rom:	$(call strip_quotes, $(PSP_BIOSBIN_FILE)) \
 			$$(PSP_APCB_FILES) \
 			$(DEP_FILES) \
+			$(UCODE_FILES) \
 			$(AMDFWTOOL) \
 			$(obj)/fmap_config.h \
 			$(objcbfs)/bootblock_fixed_data.elf # this target also creates the .map file
@@ -157,4 +178,8 @@ $(PSP_BIOSBIN_FILE): $(PSP_ELF_FILE) $(AMDCOMPRESS)
 	$(AMDCOMPRESS) --infile $(PSP_ELF_FILE) --outfile $@ --compress \
 		--maxsize $(PSP_BIOSBIN_SIZE)
 
+else
+# Set FIRMWARE_LOCATION to get the microcode files
+FIRMWARE_LOCATION=3rdparty/amd_firmwares/Firmwares/Turin
+endif # ifneq ($(call strip_quotes, $(CONFIG_AMDFW_CONFIG_FILE)),)
 endif
diff --git a/src/soc/amd/turin_poc/acpi.c b/src/soc/amd/turin_poc/acpi.c
index 9091050ba5..224f2464a9 100644
--- a/src/soc/amd/turin_poc/acpi.c
+++ b/src/soc/amd/turin_poc/acpi.c
@@ -6,7 +6,6 @@
 #include <amdblocks/acpi.h>
 #include <amdblocks/acpimmio.h>
 #include <amdblocks/cpu.h>
-#include <arch/ioapic.h>
 #include <device/device.h>
 #include <drivers/amd/opensil/opensil.h>
 
@@ -40,6 +39,7 @@ unsigned long soc_acpi_write_tables(const struct device *device, unsigned long c
 				    struct acpi_rsdp *rsdp)
 {
 	/* IVRS */
+	printk(BIOS_DEBUG, "ACPI:   * IVRS\n");
 	current = acpi_add_ivrs_table(current, rsdp);
 
 	return current;
@@ -54,7 +54,7 @@ const acpi_cstate_t cstate_cfg_table[] = {
 	},
 	[1] = {
 		.ctype = 2,
-		.latency = 0x12,
+		.latency = 0x64,
 		.power = 0,
 	},
 };
diff --git a/src/soc/amd/turin_poc/acpi/mmio.asl b/src/soc/amd/turin_poc/acpi/mmio.asl
index 9b5e1d2d2b..6ec247f788 100644
--- a/src/soc/amd/turin_poc/acpi/mmio.asl
+++ b/src/soc/amd/turin_poc/acpi/mmio.asl
@@ -33,6 +33,7 @@ Device (GPIO)
 				Shared, , , IRQR)
 			{ 0 }
 			Memory32Fixed (ReadWrite, ACPIMMIO_GPIO0_BASE, 0x400)
+			Memory32Fixed (ReadWrite, ACPIMMIO_RGPIO_BASE, 0x2C)
 		}
 		CreateDWordField (Local0, IRQR._INT, IRQN)
 		If (PICM) {
@@ -43,6 +44,7 @@ Device (GPIO)
 		If (IRQN == 0x1f || IRQN == 0) {
 			Return (ResourceTemplate() {
 				Memory32Fixed (ReadWrite, ACPIMMIO_GPIO0_BASE, 0x400)
+				Memory32Fixed (ReadWrite, ACPIMMIO_RGPIO_BASE, 0x2C)
 			})
 		} Else {
 			Return (Local0)
@@ -68,6 +70,7 @@ Device (FUR0)
 				Exclusive, , , IRQR)
 			{ 0 }
 			Memory32Fixed (ReadWrite, APU_UART0_BASE, 0x1000)
+			Memory32Fixed (ReadWrite, APU_DMA0_BASE, 0x1000)
 		}
 		CreateDWordField (Local0, IRQR._INT, IRQN)
 		If (PICM) {
@@ -78,6 +81,7 @@ Device (FUR0)
 		If (IRQN == 0x1f) {
 			Return (ResourceTemplate() {
 				Memory32Fixed (ReadWrite, APU_UART0_BASE, 0x1000)
+				Memory32Fixed (ReadWrite, APU_DMA0_BASE, 0x1000)
 			})
 		} Else {
 			Return (Local0)
@@ -105,6 +109,7 @@ Device (FUR1) {
 				Exclusive, , , IRQR)
 			{ 0 }
 			Memory32Fixed (ReadWrite, APU_UART1_BASE, 0x1000)
+			Memory32Fixed (ReadWrite, APU_DMA1_BASE, 0x1000)
 		}
 		CreateDWordField (Local0, IRQR._INT, IRQN)
 		If (PICM) {
@@ -115,6 +120,7 @@ Device (FUR1) {
 		If (IRQN == 0x1f) {
 			Return (ResourceTemplate() {
 				Memory32Fixed (ReadWrite, APU_UART1_BASE, 0x1000)
+				Memory32Fixed (ReadWrite, APU_DMA1_BASE, 0x1000)
 			})
 		} Else {
 			Return (Local0)
@@ -142,6 +148,7 @@ Device (FUR2) {
 				Exclusive, , , IRQR)
 			{ 0 }
 			Memory32Fixed (ReadWrite, APU_UART2_BASE, 0x1000)
+			Memory32Fixed (ReadWrite, APU_DMA2_BASE, 0x1000)
 		}
 		CreateDWordField (Local0, IRQR._INT, IRQN)
 		If (PICM) {
@@ -152,6 +159,7 @@ Device (FUR2) {
 		If (IRQN == 0x1f) {
 			Return (ResourceTemplate() {
 				Memory32Fixed (ReadWrite, APU_UART2_BASE, 0x1000)
+				Memory32Fixed (ReadWrite, APU_DMA2_BASE, 0x1000)
 			})
 		} Else {
 			Return (Local0)
@@ -167,6 +175,45 @@ Device (FUR2) {
 	AOAC_DEVICE(FCH_AOAC_DEV_UART2, 0)
 }
 
+Device (FUR3) {
+	Name (_HID, "AMDI0020")
+	Name (_UID, 0x3)
+	Method (_CRS, 0) {
+		Local0 = ResourceTemplate() {
+			Interrupt (
+				ResourceConsumer,
+				Edge,
+				ActiveHigh,
+				Exclusive, , , IRQR)
+			{ 0 }
+			Memory32Fixed (ReadWrite, APU_UART3_BASE, 0x1000)
+			Memory32Fixed (ReadWrite, APU_DMA3_BASE, 0x1000)
+		}
+		CreateDWordField (Local0, IRQR._INT, IRQN)
+		If (PICM) {
+			IRQN = IUA3
+		} Else {
+			IRQN = PUA3
+		}
+		If (IRQN == 0x1f) {
+			Return (ResourceTemplate() {
+				Memory32Fixed (ReadWrite, APU_UART3_BASE, 0x1000)
+				Memory32Fixed (ReadWrite, APU_DMA3_BASE, 0x1000)
+			})
+		} Else {
+			Return (Local0)
+		}
+	}
+
+	Name (STAT, 0x0)
+	Method (_STA, 0x0, NotSerialized)
+	{
+		Return (STAT)
+	}
+
+	AOAC_DEVICE(FCH_AOAC_DEV_UART3, 0)
+}
+
 Device (I2C0) {
 	Name (_HID, "AMDI0010")
 	Name (_UID, 0x0)
@@ -412,3 +459,187 @@ Device (MISC)
 		Return (0x0B)
 	}
 }
+
+Device (I3C0)
+{
+	Name (STAT, 0x0)
+
+	/* Only return I3C controller HID "AMDI0015" when device is enabled in devicetree */
+	Method (_HID, 0x0) {
+		If (STAT) {
+			Return ("AMDI0015")
+		} Else {
+			Return ("AMDI0016")
+		}
+	}
+	Name (_UID, 0x0)
+	Method (_CRS, 0) {
+		Local0 = ResourceTemplate() {
+			Interrupt (
+				ResourceConsumer,
+				Edge,
+				ActiveHigh,
+				Exclusive, , , IRQR)
+			{ 0 }
+			Memory32Fixed (ReadWrite, APU_I3C0_BASE, 0x1000)
+		}
+		CreateDWordField (Local0, IRQR._INT, IRQN)
+		If (PICM) {
+			IRQN = II20
+		} Else {
+			IRQN = PI20
+		}
+		If (IRQN == 0x1f) {
+			Return (ResourceTemplate() {
+				Memory32Fixed (ReadWrite, APU_I3C0_BASE, 0x1000)
+			})
+		} Else {
+			Return (Local0)
+		}
+	}
+
+	Method (_STA, 0x0, NotSerialized)
+	{
+		Return (STAT)
+	}
+
+	AOAC_DEVICE(FCH_AOAC_DEV_I3C0, 0)
+}
+
+Device (I3C1)
+{
+	Name (STAT, 0x0)
+
+	/* Only return I3C controller HID "AMDI0015" when device is enabled in devicetree */
+	Method (_HID, 0x0) {
+		If (STAT) {
+			Return ("AMDI0015")
+		} Else {
+			Return ("AMDI0016")
+		}
+	}
+	Name (_UID, 0x1)
+	Method (_CRS, 0) {
+		Local0 = ResourceTemplate() {
+			Interrupt (
+				ResourceConsumer,
+				Edge,
+				ActiveHigh,
+				Exclusive, , , IRQR)
+			{ 0 }
+			Memory32Fixed (ReadWrite, APU_I3C1_BASE, 0x1000)
+		}
+		CreateDWordField (Local0, IRQR._INT, IRQN)
+		If (PICM) {
+			IRQN = II21
+		} Else {
+			IRQN = PI21
+		}
+		If (IRQN == 0x1f) {
+			Return (ResourceTemplate() {
+				Memory32Fixed (ReadWrite, APU_I3C1_BASE, 0x1000)
+			})
+		} Else {
+			Return (Local0)
+		}
+	}
+
+	Method (_STA, 0x0, NotSerialized)
+	{
+		Return (STAT)
+	}
+
+	AOAC_DEVICE(FCH_AOAC_DEV_I3C1, 0)
+}
+
+Device (I3C2)
+{
+	Name (STAT, 0x0)
+
+	/* Only return I3C controller HID "AMDI0015" when device is enabled in devicetree */
+	Method (_HID, 0x0) {
+		If (STAT) {
+			Return ("AMDI0015")
+		} Else {
+			Return ("AMDI0016")
+		}
+	}
+	Name (_UID, 0x2)
+	Method (_CRS, 0) {
+		Local0 = ResourceTemplate() {
+			Interrupt (
+				ResourceConsumer,
+				Edge,
+				ActiveHigh,
+				Exclusive, , , IRQR)
+			{ 0 }
+			Memory32Fixed (ReadWrite, APU_I3C2_BASE, 0x1000)
+		}
+		CreateDWordField (Local0, IRQR._INT, IRQN)
+		If (PICM) {
+			IRQN = II22
+		} Else {
+			IRQN = PI22
+		}
+		If (IRQN == 0x1f) {
+			Return (ResourceTemplate() {
+				Memory32Fixed (ReadWrite, APU_I3C2_BASE, 0x1000)
+			})
+		} Else {
+			Return (Local0)
+		}
+	}
+
+	Method (_STA, 0x0, NotSerialized)
+	{
+		Return (STAT)
+	}
+
+	AOAC_DEVICE(FCH_AOAC_DEV_I3C2, 0)
+}
+
+Device (I3C3)
+{
+	Name (STAT, 0x0)
+
+	/* Only return I3C controller HID "AMDI0015" when device is enabled in devicetree */
+	Method (_HID, 0x0) {
+		If (STAT) {
+			Return ("AMDI0015")
+		} Else {
+			Return ("AMDI0016")
+		}
+	}
+	Name (_UID, 0x3)
+	Method (_CRS, 0) {
+		Local0 = ResourceTemplate() {
+			Interrupt (
+				ResourceConsumer,
+				Edge,
+				ActiveHigh,
+				Exclusive, , , IRQR)
+			{ 0 }
+			Memory32Fixed (ReadWrite, APU_I3C3_BASE, 0x1000)
+		}
+		CreateDWordField (Local0, IRQR._INT, IRQN)
+		If (PICM) {
+			IRQN = II23
+		} Else {
+			IRQN = PI23
+		}
+		If (IRQN == 0x1f) {
+			Return (ResourceTemplate() {
+				Memory32Fixed (ReadWrite, APU_I3C3_BASE, 0x1000)
+			})
+		} Else {
+			Return (Local0)
+		}
+	}
+
+	Method (_STA, 0x0, NotSerialized)
+	{
+		Return (STAT)
+	}
+
+	AOAC_DEVICE(FCH_AOAC_DEV_I3C3, 0)
+}
diff --git a/src/soc/amd/turin_poc/acpi/pci_int_defs.asl b/src/soc/amd/turin_poc/acpi/pci_int_defs.asl
index 22455c5cae..14b2f7db44 100644
--- a/src/soc/amd/turin_poc/acpi/pci_int_defs.asl
+++ b/src/soc/amd/turin_poc/acpi/pci_int_defs.asl
@@ -21,17 +21,30 @@ IndexField(PRQI, PRQD, ByteAcc, NoLock, Preserve) {
 	PIRG, 0x00000008,	/* Index 6: INTG */
 	PIRH, 0x00000008,	/* Index 7: INTH */
 
-	Offset (0x10),
+	Offset (0xc),
+	SIRA, 0x00000008,	/* Index 0xc: Serial IRQ A */
+	SIRB, 0x00000008,	/* Index 0xd: Serial IRQ B */
+	SIRC, 0x00000008,	/* Index 0xe: Serial IRQ C */
+	SIRD, 0x00000008,	/* Index 0xf: Serial IRQ D */
 	PSCI, 0x00000008,	/* Index 0x10: SCI */
 	PSB0, 0x00000008,	/* Index 0x11: SMBUS0 */
 	PASF, 0x00000008,	/* Index 0x12: ASF */
+	PHDA, 0x00000008,	/* Index 0x12: HDA */
 
 	Offset (0x16),
 	PPMN, 0x00000008,	/* Index 0x16: PerMon */
+	PSDC, 0x00000008,	/* Index 0x17: SD */
 
 	Offset (0x1a),
 	PSIO, 0x00000008,	/* Index 0x1A: SDIO */
 
+	Offset (0x30),
+	PUS1, 0x00000008,	/* Index 0x30: USB EMU */
+	Offset (0x34),
+	PUS3, 0x00000008,	/* Index 0x34: XHCI0 */
+	Offset (0x41),
+	PSAT, 0x00000008,	/* Index 0x41: SATA */
+
 	Offset (0x50),
 	PGP0, 0x00000008,	/* Index 0x50: GPP0 */
 	PGP1, 0x00000008,	/* Index 0x51: GPP1 */
@@ -64,27 +77,40 @@ IndexField(PRQI, PRQD, ByteAcc, NoLock, Preserve) {
 	IORG, 0x00000008,	/* Index 0x86: INTG */
 	IORH, 0x00000008,	/* Index 0x87: INTH */
 
-	Offset (0x90),
+	Offset (0x8c),
+	ISIA, 0x00000008,	/* Index 0x8c: Serial IRQ A */
+	ISIB, 0x00000008,	/* Index 0x8d: Serial IRQ B */
+	ISIC, 0x00000008,	/* Index 0x8e: Serial IRQ C */
+	ISID, 0x00000008,	/* Index 0x8f: Serial IRQ D */
 	ISCI, 0x00000008,	/* Index 0x90: SCI */
 	ISB0, 0x00000008,	/* Index 0x91: SMBUS0 */
 	IASF, 0x00000008,	/* Index 0x92: ASF */
+	IHDA, 0x00000008,	/* Index 0x93: HDA */
 
 	Offset (0x96),
 	IPMN, 0x00000008,	/* Index 0x96: PerMon */
+	ISDC, 0x00000008,	/* Index 0x97: SD */
 
 	Offset (0x9a),
 	ISIO, 0x00000008,	/* Index 0x9A: SDIO */
 
-	Offset (0xD0),
+	Offset (0xb0),
+	IUS1, 0x00000008,	/* Index 0xb0: USB EMU */
+	Offset (0xb4),
+	IUS3, 0x00000008,	/* Index 0xb4: XHCI0 */
+	Offset (0xc1),
+	ISAT, 0x00000008,	/* Index 0xc1: SATA */
+
+	Offset (0xd0),
 	IGP0, 0x00000008,	/* Index 0xD0: GPP0 */
 	IGP1, 0x00000008,	/* Index 0xD1: GPP1 */
 	IGP2, 0x00000008,	/* Index 0xD2: GPP2 */
 	IGP3, 0x00000008,	/* Index 0xD3: GPP3 */
 
-	Offset (0xE2),
+	Offset (0xe2),
 	IGPI, 0x00000008,	/* Index 0xE2: GPIO */
 
-	Offset (0xF0),
+	Offset (0xf0),
 	II20, 0x00000008,	/* Index 0xF0: I2C0/I3C0 */
 	II21, 0x00000008,	/* Index 0xF1: I2C1/I3C1 */
 	II22, 0x00000008,	/* Index 0xF2: I2C2/I3C2 */
diff --git a/src/soc/amd/turin_poc/acpi/resources.asl b/src/soc/amd/turin_poc/acpi/resources.asl
new file mode 100644
index 0000000000..98437690b5
--- /dev/null
+++ b/src/soc/amd/turin_poc/acpi/resources.asl
@@ -0,0 +1,68 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+/* PCI Device Resource Consumption */
+Device (PDRC) {
+	Name (_HID, EISAID("PNP0C02"))
+	Name (_UID, 0x700)
+	Name (_STA, 0x0F)
+	Name (_CRS, ResourceTemplate ()
+	{
+		IO (Decode16, 0x0010, 0x0010, 0x00, 0x10, )
+		IO (Decode16, 0x0022, 0x0022, 0x00, 0x1e, )
+		IO (Decode16, 0x0063, 0x0063, 0x00, 0x01, )
+		IO (Decode16, 0x0065, 0x0065, 0x00, 0x01, )
+		IO (Decode16, 0x0067, 0x0067, 0x00, 0x09, )
+		IO (Decode16, 0x0072, 0x0072, 0x00, 0x0E, )
+		IO (Decode16, 0x0080, 0x0080, 0x00, 0x01, )
+		IO (Decode16, 0x0084, 0x0084, 0x00, 0x03, )
+		IO (Decode16, 0x0088, 0x0088, 0x00, 0x01, )
+		IO (Decode16, 0x008c, 0x008c, 0x00, 0x03, )
+		IO (Decode16, 0x0090, 0x0090, 0x00, 0x10, )
+		IO (Decode16, 0x00a2, 0x00a2, 0x00, 0x1e, )
+		IO (Decode16, 0x00b1, 0x00b1, 0x00, 0x01, )
+		IO (Decode16, 0x00e0, 0x00e0, 0x00, 0x10, )
+		/* ACPI */
+		IO (Decode16, 0x0400, 0x0400, 0x00, 0xa0, )
+		/* DMA */
+		IO (Decode16, 0x040b, 0x040b, 0x00, 0x01, )
+		/* INTR edge control */
+		IO (Decode16, 0x04d0, 0x04d0, 0x00, 0x02, )
+		/* DMA */
+		IO (Decode16, 0x04d6, 0x04d6, 0x00, 0x01, )
+		IO (Decode16, 0x0900, 0x0900, 0x00, 0x10, )
+		IO (Decode16, 0x0910, 0x0910, 0x00, 0x10, )
+		/* SMBUS */
+		IO (Decode16, 0x0b00, 0x0b00, 0x00, 0x10, )
+		/* SMBUS ASF */
+		IO (Decode16, 0x0b20, 0x0b20, 0x00, 0x20, )
+		/* PCI interrupt router */
+		IO (Decode16, 0x0c00, 0x0c00, 0x00, 0x02, )
+		/* PCI ERR */
+		IO (Decode16, 0x0c14, 0x0c14, 0x00, 0x01, )
+		IO (Decode16, 0x0c50, 0x0c50, 0x00, 0x02, )
+		IO (Decode16, 0x0c52, 0x0c52, 0x00, 0x01, )
+		IO (Decode16, 0x0c6c, 0x0c6c, 0x00, 0x01, )
+		/* ISA MISC */
+		IO (Decode16, 0x0c6f, 0x0c6f, 0x00, 0x01, )
+		IO (Decode16, 0x0cd0, 0x0cd0, 0x00, 0x02, )
+		/* PMIO2 */
+		IO (Decode16, 0x0cd2, 0x0cd2, 0x00, 0x02, )
+		/* BIOSRAM */
+		IO (Decode16, 0x0cd4, 0x0cd4, 0x00, 0x02, )
+		/* PMIO */
+		IO (Decode16, 0x0cd6, 0x0cd6, 0x00, 0x02, )
+		/* AB INDX */
+		IO (Decode16, 0x0cd8, 0x0cd8, 0x00, 0x08, )
+		/* ACPI PMA CNTL BLK */
+		IO (Decode16, 0xfe00, 0xfe00, 0x00, 0xff, )
+		Memory32Fixed (ReadWrite, 0xfee00000, 0x00001000, )
+		/* Remainder of remote GPIO up to GPIO0 bank */
+		Memory32Fixed (ReadWrite, 0xfed8122c, 0x000002d4, )
+		/* ACPI MMIO above GPIO banks */
+		Memory32Fixed (ReadWrite, 0xfed81a00, 0x0000e600, )
+		/* Watchdog */
+		Memory32Fixed (ReadWrite, 0xfeb00000, 0x00000010, )
+		/* ROM */
+		Memory32Fixed (ReadWrite, 0xff000000, 0x01000000, )
+	})
+}
diff --git a/src/soc/amd/turin_poc/acpi/soc.asl b/src/soc/amd/turin_poc/acpi/soc.asl
index 75344dc325..5d18024705 100644
--- a/src/soc/amd/turin_poc/acpi/soc.asl
+++ b/src/soc/amd/turin_poc/acpi/soc.asl
@@ -19,6 +19,15 @@ Scope(\_SB) {
 	ROOT_BRIDGE(S0B1)
 	ROOT_BRIDGE(S0B2)
 	ROOT_BRIDGE(S0B3)
+	ROOT_BRIDGE(S0B4)
+	ROOT_BRIDGE(S0B5)
+	ROOT_BRIDGE(S0B6)
+	ROOT_BRIDGE(S0B7)
+
+	Scope(S0B0) {
+		#include "resources.asl"
+		#include <soc/amd/common/acpi/lpc.asl>
+	} /* End S0B0 scope */
 } /* End \_SB scope */
 
 #include <soc/amd/common/acpi/alib.asl>
@@ -34,6 +43,4 @@ Scope(\_SB) {
  */
 Method (PNOT)
 {
-	/* Report AC/DC state to ALIB using WAL1() */
-	\WAL1 ()
 }
diff --git a/src/soc/amd/turin_poc/chip.c b/src/soc/amd/turin_poc/chip.c
index 344617d52e..ee5ad5e0a0 100644
--- a/src/soc/amd/turin_poc/chip.c
+++ b/src/soc/amd/turin_poc/chip.c
@@ -2,6 +2,7 @@
 
 #include <amdblocks/acpi.h>
 #include <amdblocks/data_fabric.h>
+#include <cpu/x86/mtrr.h>
 #include <device/device.h>
 #include <drivers/amd/opensil/opensil.h>
 #include <soc/southbridge.h>
@@ -10,6 +11,8 @@ static void soc_init(void *chip_info)
 {
 	default_dev_ops_root.write_acpi_tables = soc_acpi_write_tables;
 
+	display_mtrrs();
+
 	amd_opensil_silicon_init();
 
 	data_fabric_print_mmio_conf();
diff --git a/src/soc/amd/turin_poc/chip.h b/src/soc/amd/turin_poc/chip.h
index f08f348f15..1bfe6e6c92 100644
--- a/src/soc/amd/turin_poc/chip.h
+++ b/src/soc/amd/turin_poc/chip.h
@@ -9,6 +9,11 @@
 #include <soc/iomap.h>
 #include <types.h>
 
+#define MAX_DOMAINS	8
+
+static const unsigned int domain_to_rb_index[MAX_DOMAINS] = { 2, 7, 3, 6, 4, 1, 5, 0 };
+static const unsigned int domain_to_logical_rb[MAX_DOMAINS] = { 4, 5, 6, 7, 3, 2, 1, 0 };
+
 struct usb31_phy_settings {
 	uint8_t rx_ana_iq_phase_adjust;
 	uint8_t rx_eq_delta_iq_ovrd_en;
@@ -30,33 +35,23 @@ struct soc_usb_config {
 	struct {
 		uint8_t port0 : 4;
 		uint8_t port1 : 4;
-		uint8_t port2 : 4;
-		uint8_t port3 : 4;
-		uint8_t port4 : 4;
-		uint8_t port5 : 4;
-		uint8_t port6 : 4;
-		uint8_t port7 : 4;
 	} usb2_oc_pins[2];
 	struct {
 		uint8_t port0 : 4;
 		uint8_t port1 : 4;
-		uint8_t port2 : 4;
-		uint8_t port3 : 4;
 	}  usb3_oc_pins[2];
 	bool polarity_cfg_low;
 	union {
 		struct {
 			uint8_t port0 : 2;
 			uint8_t port1 : 2;
-			uint8_t port2 : 2; /* Broken in OpenSIL */
-			uint8_t port3 : 2; /* Broken in OpenSIL */
 		};
 		uint8_t raw;
 	} usb3_force_gen1;
 	bool usb31_phy_enable;
-	struct usb31_phy_settings usb31_phy[8];
+	struct usb31_phy_settings usb31_phy[2];
 	bool s1_usb31_phy_enable;
-	struct usb31_phy_settings s1_usb31_phy[8];
+	struct usb31_phy_settings s1_usb31_phy[2];
 };
 
 struct soc_amd_turin_poc_config {
diff --git a/src/soc/amd/turin_poc/chipset.cb b/src/soc/amd/turin_poc/chipset.cb
index 399d3530fc..f8f4888658 100644
--- a/src/soc/amd/turin_poc/chipset.cb
+++ b/src/soc/amd/turin_poc/chipset.cb
@@ -4,14 +4,14 @@ chip soc/amd/turin_poc
 	device cpu_cluster 0 on ops amd_cpu_bus_ops end
 
 	# OC pins
-	register "usb.usb2_oc_pins[0]" = "{ 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf }"
-	register "usb.usb2_oc_pins[1]" = "{ 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf }"
-	register "usb.usb3_oc_pins[0]" = "{ 0xf, 0xf, 0xf, 0xf }"
-	register "usb.usb3_oc_pins[1]" = "{ 0xf, 0xf, 0xf, 0xf }"
+	register "usb.usb2_oc_pins[0]" = "{ 0xf, 0xf }"
+	register "usb.usb2_oc_pins[1]" = "{ 0xf, 0xf }"
+	register "usb.usb3_oc_pins[0]" = "{ 0xf, 0xf }"
+	register "usb.usb3_oc_pins[1]" = "{ 0xf, 0xf }"
 
 	device domain 0 on
 		ops turin_pci_domain_ops
-		device pci 00.0 alias gnb_0 on end
+		device pci 00.0 alias gnb_0 on ops turin_root_complex_operations end
 		device pci 00.2 alias iommu_0 off ops amd_iommu_ops end
 		device pci 00.3 alias rcec_0 off end
 
@@ -47,69 +47,19 @@ chip soc/amd/turin_poc
 		end
 
 		device pci 03.0 on end # Dummy device function, do not disable
-		chip drivers/amd/opensil/mpio
-			device pci 03.1 alias gpp_bridge_0_0_b off end
-		end
-		chip drivers/amd/opensil/mpio
-			device pci 03.2 alias gpp_bridge_0_1_b off end
-		end
-		chip drivers/amd/opensil/mpio
-			device pci 03.3 alias gpp_bridge_0_2_b off end
-		end
-		chip drivers/amd/opensil/mpio
-			device pci 03.4 alias gpp_bridge_0_3_b off end
-		end
-		chip drivers/amd/opensil/mpio
-			device pci 03.5 alias gpp_bridge_0_4_b off end
-		end
-		chip drivers/amd/opensil/mpio
-			device pci 03.6 alias gpp_bridge_0_5_b off end
-		end
-		chip drivers/amd/opensil/mpio
-			device pci 03.7 alias gpp_bridge_0_6_b off end
-		end
-
 		device pci 04.0 on end # Dummy device function, do not disable
-		chip drivers/amd/opensil/mpio
-			device pci 04.1 alias gpp_bridge_0_7_b off end
-		end
-		chip drivers/amd/opensil/mpio
-			device pci 04.2 alias gpp_bridge_0_8_b off end
-		end
-
 		device pci 05.0 on end # Dummy device function, do not disable
-		chip drivers/amd/opensil/mpio
-			device pci 05.1 alias gpp_bridge_0_0_c off end
-		end
-		chip drivers/amd/opensil/mpio
-			device pci 05.2 alias gpp_bridge_0_1_c off end
-		end
-		chip drivers/amd/opensil/mpio
-			device pci 05.3 alias gpp_bridge_0_2_c off end
-		end
-		chip drivers/amd/opensil/mpio
-			device pci 05.4 alias gpp_bridge_0_3_c off end
-		end
 
 		device pci 07.0 on end # Dummy device function, do not disable
-		device pci 07.1 alias gpp_bridge_0_a off # Internal GPP Bridge 0 to Bus B0
-			device pci 0.0 on end # Dummy PCIe function
-			device pci 0.1 off end
-			device pci 0.2 alias primary_NTB_0 off end # Primary PCIe Non-TransparentBridge
-			device pci 0.3 alias secondry_NTB_0 off end # Secondary vNTB
-			device pci 0.4 alias xhci_0 off end # USB
-			device pci 0.5 alias mp0_0 off end # PSP (MP0)
-			device pci 0.6 alias acp_0 off end # Audio Processor (ACP)
-			device pci 0.7 alias hda_0 off end # Audio Processor HD Audio Controller (main AZ)
-		end
-		device pci 07.2 alias gpp_bridge_0_b off # Internal GPP Bridge 1 to Bus C0
-			device pci 0.0 alias sata_0_0 off end # first SATA controller; AHCI mode
-			device pci 0.1 alias sata_0_1 off end # second SATA controller; AHCI mode
+		device pci 07.1 alias gpp_bridge_0_a on # Internal GPP Bridge 0 to Bus C0
+			device pci 00.0 alias nbif_0 on end # Dummy PCIe function
+			device pci 00.1 alias sdxi_1 on end # Smart Data Accelerator Interface
+			device pci 00.2 alias primary_NTB_1 off end # Primary PCIe Non-TransparentBridge
+			device pci 00.3 alias secondry_NTB_1 off end # Secondary vNTB
 		end
 
 		device pci 14.0 alias smbus on end # primary FCH function
 		device pci 14.3 alias lpc_bridge on ops amd_lpc_ops end
-		device pci 14.6 alias sdhci off end
 
 		device pci 18.0 alias data_fabric_0 on end
 		device pci 18.1 alias data_fabric_1 on end
@@ -123,8 +73,7 @@ chip soc/amd/turin_poc
 
 	device domain 1 on
 		ops turin_pci_domain_ops
-		device pci 00.0 alias gnb_1 on end
-		device pci 00.2 alias iommu_1 off ops amd_iommu_ops end
+		device pci 00.0 alias gnb_1 on ops turin_root_complex_operations  end
 		device pci 00.3 alias rcec_1 off end
 
 		device pci 01.0 on end # Dummy device function, do not disable
@@ -157,54 +106,12 @@ chip soc/amd/turin_poc
 		chip drivers/amd/opensil/mpio
 			device pci 02.2 alias gpp_bridge_1_8_a off end
 		end
-
-		device pci 03.0 on end # Dummy device function, do not disable
-		chip drivers/amd/opensil/mpio
-			device pci 03.1 alias gpp_bridge_1_0_b off end
-		end
-		chip drivers/amd/opensil/mpio
-			device pci 03.2 alias gpp_bridge_1_1_b off end
-		end
-		chip drivers/amd/opensil/mpio
-			device pci 03.3 alias gpp_bridge_1_2_b off end
-		end
-		chip drivers/amd/opensil/mpio
-			device pci 03.4 alias gpp_bridge_1_3_b off end
-		end
-		chip drivers/amd/opensil/mpio
-			device pci 03.5 alias gpp_bridge_1_4_b off end
-		end
-		chip drivers/amd/opensil/mpio
-			device pci 03.6 alias gpp_bridge_1_5_b off end
-		end
-		chip drivers/amd/opensil/mpio
-			device pci 03.7 alias gpp_bridge_1_6_b off end
-		end
-
-		device pci 04.0 on end # Dummy device function, do not disable
-		chip drivers/amd/opensil/mpio
-			device pci 04.1 alias gpp_bridge_1_7_b off end
-		end
-		chip drivers/amd/opensil/mpio
-			device pci 04.2 alias gpp_bridge_1_8_b off end
-		end
-
-		device pci 05.0 on end # Dummy device function, do not disable
-
-		device pci 07.0 on end # Dummy device function, do not disable
-		device pci 07.1 alias gpp_bridge_1_a off
-			device pci 0.0 on end # Dummy PCIe function
-			device pci 0.1 off end #SDXI
-			device pci 0.2 alias primary_NTB_1 off end # Primary PCIe Non-TransparentBridge
-			device pci 0.3 alias secondry_NTB_1 off end # Secondary vNTB
-		end
 	end
 
 	device domain 2 on
 		ops turin_pci_domain_ops
-		device pci 00.0 alias gnb_2 on end
+		device pci 00.0 alias gnb_2 on ops turin_root_complex_operations end
 		device pci 00.2 alias iommu_2 off ops amd_iommu_ops end
-		device pci 00.3 alias rcec_2 off end
 
 		device pci 01.0 on end # Dummy device function, do not disable
 		chip drivers/amd/opensil/mpio
@@ -238,52 +145,36 @@ chip soc/amd/turin_poc
 		end
 
 		device pci 03.0 on end # Dummy device function, do not disable
-		chip drivers/amd/opensil/mpio
-			device pci 03.1 alias gpp_bridge_2_0_b off end
-		end
-		chip drivers/amd/opensil/mpio
-			device pci 03.2 alias gpp_bridge_2_1_b off end
-		end
-		chip drivers/amd/opensil/mpio
-			device pci 03.3 alias gpp_bridge_2_2_b off end
-		end
-		chip drivers/amd/opensil/mpio
-			device pci 03.4 alias gpp_bridge_2_3_b off end
-		end
-		chip drivers/amd/opensil/mpio
-			device pci 03.5 alias gpp_bridge_2_4_b off end
-		end
-		chip drivers/amd/opensil/mpio
-			device pci 03.6 alias gpp_bridge_2_5_b off end
-		end
-		chip drivers/amd/opensil/mpio
-			device pci 03.7 alias gpp_bridge_2_6_b off end
-		end
-
 		device pci 04.0 on end # Dummy device function, do not disable
-		chip drivers/amd/opensil/mpio
-			device pci 04.1 alias gpp_bridge_2_7_b off end
-		end
-		chip drivers/amd/opensil/mpio
-			device pci 04.2 alias gpp_bridge_2_8_b off end
-		end
 
 		device pci 05.0 on end # Dummy device function, do not disable
+		chip drivers/amd/opensil/mpio
+			device pci 05.1 alias gpp_bridge_2_0_c off end
+		end
+		chip drivers/amd/opensil/mpio
+			device pci 05.2 alias gpp_bridge_2_1_c off end
+		end
+		chip drivers/amd/opensil/mpio
+			device pci 05.3 alias gpp_bridge_2_2_c off end
+		end
 
 		device pci 07.0 on end # Dummy device function, do not disable
-		device pci 07.1 alias gpp_bridge_2_a off
-			device pci 0.0 on end # Dummy PCIe function
-			device pci 0.1 off end
-			device pci 0.2 alias primary_NTB_2 off end # Primary PCIe Non-TransparentBridge
-			device pci 0.3 alias secondry_NTB_2 off end # Secondary vNTB
+		device pci 07.1 alias gpp_bridge_2_a on # Internal GPP Bridge 0 to Bus C1
+			device pci 00.0 alias nbif_2 on end # Dummy PCIe function
+			device pci 00.1 alias sdxi_2 on end # Smart Data Accelerator Interface
+			device pci 00.3 alias secondry_NTB_2 off end # Secondary vNTB
+			device pci 00.4 alias xhci_0 off end # USB
+			device pci 00.7 alias hda off end # HD Audio Controller (AZ)
+		end
+		device pci 07.2 alias gpp_bridge_2_b on # Internal GPP Bridge 0 to Bus D1
+			device pci 00.0 alias sata_2_0 off end # first SATA controller; AHCI mode
+			device pci 00.1 alias sata_2_1 off end # second SATA controller; AHCI mode
 		end
 	end
 
 	device domain 3 on
 		ops turin_pci_domain_ops
-		device pci 00.0 alias gnb_3 on end
-		device pci 00.2 alias iommu_3 off ops amd_iommu_ops end
-		device pci 00.3 alias rcec_3 off end
+		device pci 00.0 alias gnb_3 on ops turin_root_complex_operations end
 
 		device pci 01.0 on end # Dummy device function, do not disable
 		chip drivers/amd/opensil/mpio
@@ -315,66 +206,221 @@ chip soc/amd/turin_poc
 		chip drivers/amd/opensil/mpio
 			device pci 02.2 alias gpp_bridge_3_8_a off end
 		end
+	end
+
+	device domain 4 on
+		ops turin_pci_domain_ops
+		device pci 00.0 alias gnb_4 on ops turin_root_complex_operations end
+
+		device pci 01.0 on end # Dummy device function, do not disable
+		chip drivers/amd/opensil/mpio
+			device pci 01.1 alias gpp_bridge_4_0_a off end
+		end
+		chip drivers/amd/opensil/mpio
+			device pci 01.2 alias gpp_bridge_4_1_a off end
+		end
+		chip drivers/amd/opensil/mpio
+			device pci 01.3 alias gpp_bridge_4_2_a off end
+		end
+		chip drivers/amd/opensil/mpio
+			device pci 01.4 alias gpp_bridge_4_3_a off end
+		end
+		chip drivers/amd/opensil/mpio
+			device pci 01.5 alias gpp_bridge_4_4_a off end
+		end
+		chip drivers/amd/opensil/mpio
+			device pci 01.6 alias gpp_bridge_4_5_a off end
+		end
+		chip drivers/amd/opensil/mpio
+			device pci 01.7 alias gpp_bridge_4_6_a off end
+		end
+
+		device pci 02.0 on end # Dummy device function, do not disable
+		chip drivers/amd/opensil/mpio
+			device pci 02.1 alias gpp_bridge_4_7_a off end
+		end
+		chip drivers/amd/opensil/mpio
+			device pci 02.2 alias gpp_bridge_4_8_a off end
+		end
+	end
+
+	device domain 5 on
+		ops turin_pci_domain_ops
+		device pci 00.0 alias gnb_5 on ops turin_root_complex_operations end
+		device pci 00.2 alias iommu_5 off ops amd_iommu_ops end
+
+		device pci 01.0 on end # Dummy device function, do not disable
+		chip drivers/amd/opensil/mpio
+			device pci 01.1 alias gpp_bridge_5_0_a off end
+		end
+		chip drivers/amd/opensil/mpio
+			device pci 01.2 alias gpp_bridge_5_1_a off end
+		end
+		chip drivers/amd/opensil/mpio
+			device pci 01.3 alias gpp_bridge_5_2_a off end
+		end
+		chip drivers/amd/opensil/mpio
+			device pci 01.4 alias gpp_bridge_5_3_a off end
+		end
+		chip drivers/amd/opensil/mpio
+			device pci 01.5 alias gpp_bridge_5_4_a off end
+		end
+		chip drivers/amd/opensil/mpio
+			device pci 01.6 alias gpp_bridge_5_5_a off end
+		end
+		chip drivers/amd/opensil/mpio
+			device pci 01.7 alias gpp_bridge_5_6_a off end
+		end
+
+		device pci 02.0 on end # Dummy device function, do not disable
+		chip drivers/amd/opensil/mpio
+			device pci 02.1 alias gpp_bridge_5_7_a off end
+		end
+		chip drivers/amd/opensil/mpio
+			device pci 02.2 alias gpp_bridge_5_8_a off end
+		end
 
 		device pci 03.0 on end # Dummy device function, do not disable
 		chip drivers/amd/opensil/mpio
-			device pci 03.1 alias gpp_bridge_3_0_b off end
+			device pci 03.1 alias gpp_bridge_5_0_b off end
 		end
 		chip drivers/amd/opensil/mpio
-			device pci 03.2 alias gpp_bridge_3_1_b off end
+			device pci 03.2 alias gpp_bridge_5_1_b off end
 		end
 		chip drivers/amd/opensil/mpio
-			device pci 03.3 alias gpp_bridge_3_2_b off end
+			device pci 03.3 alias gpp_bridge_5_2_b off end
 		end
 		chip drivers/amd/opensil/mpio
-			device pci 03.4 alias gpp_bridge_3_3_b off end
+			device pci 03.4 alias gpp_bridge_5_3_b off end
 		end
 		chip drivers/amd/opensil/mpio
-			device pci 03.5 alias gpp_bridge_3_4_b off end
+			device pci 03.5 alias gpp_bridge_5_4_b off end
 		end
 		chip drivers/amd/opensil/mpio
-			device pci 03.6 alias gpp_bridge_3_5_b off end
+			device pci 03.6 alias gpp_bridge_5_5_b off end
 		end
 		chip drivers/amd/opensil/mpio
-			device pci 03.7 alias gpp_bridge_3_6_b off end
+			device pci 03.7 alias gpp_bridge_5_6_b off end
 		end
 
 		device pci 04.0 on end # Dummy device function, do not disable
 		chip drivers/amd/opensil/mpio
-			device pci 04.1 alias gpp_bridge_3_7_b off end
-		end
-		chip drivers/amd/opensil/mpio
-			device pci 04.2 alias gpp_bridge_3_8_b off end
+			device pci 04.1 alias gpp_bridge_5_7_b off end
 		end
 
 		device pci 05.0 on end # Dummy device function, do not disable
 		chip drivers/amd/opensil/mpio
-			device pci 05.1 alias gpp_bridge_3_0_c off end
+			device pci 05.1 alias gpp_bridge_5_0_c off end
 		end
 		chip drivers/amd/opensil/mpio
-			device pci 05.2 alias gpp_bridge_3_1_c off end
+			device pci 05.2 alias gpp_bridge_5_1_c off end
 		end
 		chip drivers/amd/opensil/mpio
-			device pci 05.3 alias gpp_bridge_3_2_c off end
-		end
-		chip drivers/amd/opensil/mpio
-			device pci 05.4 alias gpp_bridge_3_3_c off end
+			device pci 05.3 alias gpp_bridge_5_2_c off end
 		end
 
 		device pci 07.0 on end # Dummy device function, do not disable
-		device pci 07.1 alias gpp_bridge_3_a off
-			device pci 0.0 on end # Dummy PCIe function
-			device pci 0.1 off end #SDXI
-			device pci 0.2 alias primary_NTB_3 off end # Primary PCIe Non-TransparentBridge
-			device pci 0.3 alias secondry_NTB_3 off end # Secondary vNTB
-			device pci 0.4 alias xhci_3 off end # USB
-			device pci 0.5 alias mp0_3 off end # PSP (MP0)
+		device pci 07.1 alias gpp_bridge_3_a on # Internal GPP Bridge 0 to Bus C2
+			device pci 00.0 alias nbif_3 on end # Dummy PCIe function
+			device pci 00.1 alias sdxi_3 on end # Smart Data Accelerator Interface
+			device pci 00.2 alias primary_NTB_3 off end # Primary PCIe Non-TransparentBridge
+			device pci 00.3 alias secondry_NTB_3 off end # Secondary vNTB
+			device pci 00.5 alias asp off end # PSP (MP0)
+		end
+	end
+
+	device domain 6 on
+		ops turin_pci_domain_ops
+		device pci 00.0 alias gnb_6 on ops turin_root_complex_operations end
+		device pci 00.3 alias rcec_6 off end
+
+		device pci 01.0 on end # Dummy device function, do not disable
+		chip drivers/amd/opensil/mpio
+			device pci 01.1 alias gpp_bridge_6_0_a off end
+		end
+		chip drivers/amd/opensil/mpio
+			device pci 01.2 alias gpp_bridge_6_1_a off end
+		end
+		chip drivers/amd/opensil/mpio
+			device pci 01.3 alias gpp_bridge_6_2_a off end
+		end
+		chip drivers/amd/opensil/mpio
+			device pci 01.4 alias gpp_bridge_6_3_a off end
+		end
+		chip drivers/amd/opensil/mpio
+			device pci 01.5 alias gpp_bridge_6_4_a off end
+		end
+		chip drivers/amd/opensil/mpio
+			device pci 01.6 alias gpp_bridge_6_5_a off end
+		end
+		chip drivers/amd/opensil/mpio
+			device pci 01.7 alias gpp_bridge_6_6_a off end
 		end
 
-		device pci 07.2 alias gpp_bridge_3_b off
-			device pci 0.0 alias sata_3_0 off end # first SATA controller; AHCI mode
-			device pci 0.1 alias sata_3_1 off end # second SATA controller; AHCI mode
+		device pci 02.0 on end # Dummy device function, do not disable
+		chip drivers/amd/opensil/mpio
+			device pci 02.1 alias gpp_bridge_6_7_a off end
 		end
+		chip drivers/amd/opensil/mpio
+			device pci 02.2 alias gpp_bridge_6_8_a off end
+		end
+	end
+
+	device domain 7 on
+		ops turin_pci_domain_ops
+		device pci 00.0 alias gnb_7 on ops turin_root_complex_operations end
+		device pci 00.2 alias iommu_7 off ops amd_iommu_ops end
+		device pci 00.3 alias rcec_7 off end
+
+		device pci 01.0 on end # Dummy device function, do not disable
+		chip drivers/amd/opensil/mpio
+			device pci 01.1 alias gpp_bridge_7_0_a off end
+		end
+		chip drivers/amd/opensil/mpio
+			device pci 01.2 alias gpp_bridge_7_1_a off end
+		end
+		chip drivers/amd/opensil/mpio
+			device pci 01.3 alias gpp_bridge_7_2_a off end
+		end
+		chip drivers/amd/opensil/mpio
+			device pci 01.4 alias gpp_bridge_7_3_a off end
+		end
+		chip drivers/amd/opensil/mpio
+			device pci 01.5 alias gpp_bridge_7_4_a off end
+		end
+		chip drivers/amd/opensil/mpio
+			device pci 01.6 alias gpp_bridge_7_5_a off end
+		end
+		chip drivers/amd/opensil/mpio
+			device pci 01.7 alias gpp_bridge_7_6_a off end
+		end
+
+		device pci 02.0 on end # Dummy device function, do not disable
+		chip drivers/amd/opensil/mpio
+			device pci 02.1 alias gpp_bridge_7_7_a off end
+		end
+		chip drivers/amd/opensil/mpio
+			device pci 02.2 alias gpp_bridge_7_8_a off end
+		end
+
+		device pci 03.0 on end # Dummy device function, do not disable
+		device pci 04.0 on end # Dummy device function, do not disable
+		device pci 05.0 on end # Dummy device function, do not disable
+
+		device pci 07.0 on end # Dummy device function, do not disable
+		device pci 07.1 alias gpp_bridge_7_a on # Internal GPP Bridge 0 to Bus C3
+			device pci 00.0 alias nbif_4 on end # Dummy PCIe function
+			device pci 00.1 alias sdxi_4 on end # Smart Data Accelerator Interface
+			device pci 00.2 alias primary_NTB_4 off end # Primary PCIe Non-TransparentBridge
+			device pci 00.3 alias secondry_NTB_4 off end # Secondary vNTB
+			device pci 00.4 alias xhci_1 off end # USB
+		end
+
+		device pci 07.2 alias gpp_bridge_7_b on # Internal GPP Bridge 0 to Bus D3
+			device pci 00.0 alias sata_7_0 off end # first SATA controller; AHCI mode
+			device pci 00.1 alias sata_7_1 off end # second SATA controller; AHCI mode
+		end
+
 	end
 
 	device mmio 0xfedc2000 alias i2c_0 off ops soc_amd_i2c_mmio_ops end
diff --git a/src/soc/amd/turin_poc/cpu.c b/src/soc/amd/turin_poc/cpu.c
index aedd0ac6cf..fc1ad627eb 100644
--- a/src/soc/amd/turin_poc/cpu.c
+++ b/src/soc/amd/turin_poc/cpu.c
@@ -10,8 +10,9 @@ static struct device_operations cpu_dev_ops = {
 };
 
 static struct cpu_device_id cpu_table[] = {
-	{ X86_VENDOR_AMD, TURIN_A0_CPUID, CPUID_ALL_STEPPINGS_MASK },
-	{ X86_VENDOR_AMD, TURIN_B0_CPUID, CPUID_ALL_STEPPINGS_MASK },
+	{ X86_VENDOR_AMD, TURIN_Ax_CPUID, CPUID_ALL_STEPPINGS_MASK },
+	{ X86_VENDOR_AMD, TURIN_Bx_CPUID, CPUID_ALL_STEPPINGS_MASK },
+	{ X86_VENDOR_AMD, TURIN_Cx_CPUID, CPUID_ALL_STEPPINGS_MASK },
 	CPU_TABLE_END
 };
 
diff --git a/src/soc/amd/turin_poc/domain.c b/src/soc/amd/turin_poc/domain.c
index 40177d7dcc..6991fdc527 100644
--- a/src/soc/amd/turin_poc/domain.c
+++ b/src/soc/amd/turin_poc/domain.c
@@ -1,23 +1,56 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
 #include <acpi/acpigen_pci.h>
+#include <amdblocks/acpimmio_map.h>
 #include <amdblocks/ioapic.h>
 #include <amdblocks/data_fabric.h>
+#include <amdblocks/iomap.h>
 #include <amdblocks/memmap.h>
 #include <amdblocks/root_complex.h>
 #include <amdblocks/smn.h>
 #include <arch/ioapic.h>
 #include <console/console.h>
+#include <cpu/cpu.h>
 #include <device/device.h>
 #include <drivers/amd/opensil/opensil.h>
+#include <soc/iomap.h>
 #include <types.h>
 
 #define IOHC_IOAPIC_BASE_ADDR_LO 0x2f0
 
+/*
+ * 12GiB of DF reserved space at the top of physical address space. The
+ * address is not fixed and depends on SME state, because it can reduce the
+ * available physical address space.
+ */
+#define DATA_FABRIC_RESERVED_BASE \
+	(POWER_OF_2(cpu_phys_address_size()) - DF_RESERVED_TOP_12GB_MMIO_SIZE)
+#define DATA_FABRIC_RESERVED_SIZE	DF_RESERVED_TOP_12GB_MMIO_SIZE
+
+/*
+ * 64KiB of ACPI EINJ buffer, reserve it. Reads return FFs and cause errors in
+ * memtest86 if not reserved, and needless to say, crashes in operating
+ * systems too.
+ */
+#define ACPI_EINJ_RESERVED_BASE		(4ull * GiB)
+#define ACPI_EINJ_RESERVED_SIZE		(64 * KiB)
+
 void read_soc_memmap_resources(struct device *domain, unsigned long *idx)
 {
 	read_lower_soc_memmap_resources(domain, idx);
 
+	if (is_domain0(domain)) {
+		reserved_ram_range(domain, (*idx)++, ACPI_EINJ_RESERVED_BASE,
+						     ACPI_EINJ_RESERVED_SIZE);
+
+		mmio_range(domain, (*idx)++, IOMMU_RESERVED_MMIO_BASE, 12ULL * GiB);
+		mmio_range(domain, (*idx)++, DATA_FABRIC_RESERVED_BASE,
+					     DATA_FABRIC_RESERVED_SIZE);
+
+		mmio_range(domain, (*idx)++, AMD_SB_ACPI_MMIO_ADDR, 0x2000);
+		mmio_range(domain, (*idx)++, ALINK_AHB_ADDRESS, 0x20000);
+	}
+
 	amd_opensil_add_memmap(domain, idx);
 }
 
@@ -48,11 +81,15 @@ static void turin_domain_set_resources(struct device *domain)
 static const char *turin_domain_acpi_name(const struct device *domain)
 {
 	const unsigned int domain_id = dev_get_domain_id(domain);
-	const char *domain_acpi_names[4] = {
+	const char *domain_acpi_names[8] = {
 		"S0B0",
 		"S0B1",
 		"S0B2",
 		"S0B3",
+		"S0B4",
+		"S0B5",
+		"S0B6",
+		"S0B7",
 	};
 
 	if (domain_id < ARRAY_SIZE(domain_acpi_names))
diff --git a/src/soc/amd/turin_poc/early_fch.c b/src/soc/amd/turin_poc/early_fch.c
index d82ebcbcf8..5bcbca0834 100644
--- a/src/soc/amd/turin_poc/early_fch.c
+++ b/src/soc/amd/turin_poc/early_fch.c
@@ -1,19 +1,73 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
+#define __SIMPLE_DEVICE__
+
 #include <amdblocks/espi.h>
 #include <amdblocks/lpc.h>
 #include <amdblocks/acpimmio.h>
 #include <amdblocks/aoac.h>
+#include <amdblocks/i2c.h>
 #include <amdblocks/pmlib.h>
+#include <amdblocks/smbus.h>
+#include <amdblocks/smn.h>
+#include <amdblocks/spi.h>
 #include <amdblocks/uart.h>
+#include <device/pci.h>
 #include <soc/southbridge.h>
 #include <soc/uart.h>
+#include <soc/i2c.h>
+
+#define SMN_D18F0_BASE		0x49000000
+
+static void df_set_pci_mmconf(void)
+{
+	uint32_t reg;
+	uint64_t mmconf_base = CONFIG_ECAM_MMCONF_BASE_ADDRESS;
+	uint64_t mmconf_limit = mmconf_base + CONFIG_ECAM_MMCONF_LENGTH;
+
+	mmconf_limit--;
+	mmconf_limit &= 0xfff00000; /* Address bits [19:0] are fixed to be FFFFF */
+	mmconf_base |= 1; /* Range enable */
+
+	/*
+	 * We have to use I/O PCI access to SMN index/data, because MMCONF
+	 * will not work with our MMCONF address until this function returns.
+	 */
+	reg = smn_io_read32(SMN_D18F0_BASE + 0xc10);
+	reg &= ~1; /* Disable MMCONF range first */
+	smn_io_write32(SMN_D18F0_BASE + 0xc10, reg);
+
+	/* Now repeat the order in which ABL configured the MMCONF */
+	reg = mmconf_limit >> 32;
+	smn_io_write32(SMN_D18F0_BASE + 0xc1c, reg);
+	reg = mmconf_limit & 0xffffffff;
+	smn_io_write32(SMN_D18F0_BASE + 0xc18, reg);
+	reg = mmconf_base >> 32;
+	smn_io_write32(SMN_D18F0_BASE + 0xc14, reg);
+	reg = mmconf_base & 0xffffffff;
+	smn_io_write32(SMN_D18F0_BASE + 0xc10, reg);
+}
 
 /* Before console init */
 void fch_pre_init(void)
 {
+	/*
+	 * Before we can proceed with any initialization that touches PCI, we
+	 * have to ensure our PCI MMCONF base matches the register in DF.
+	 */
+	df_set_pci_mmconf();
+	/*
+	 * Enable_acpimmio_decode_pm04 to enable the ACPIMMIO decode which is
+	 * needed to access the GPIO registers.
+	 */
+	enable_acpimmio_decode_pm04();
+	/* Setup SPI base by calling lpc_early_init before setting up eSPI. */
+	lpc_early_init();
+	fch_spi_early_init();
+	fch_smbus_init();
 	fch_enable_cf9_io();
-
+	fch_enable_legacy_io();
+	fch_disable_legacy_dma_io();
 	enable_aoac_devices();
 	/*
 	 * On reset Range_0 defaults to enabled. We want to start with a clean
@@ -24,10 +78,29 @@ void fch_pre_init(void)
 	if (CONFIG(AMD_SOC_CONSOLE_UART))
 		set_uart_config(CONFIG_UART_FOR_CONSOLE);
 
-	configure_espi_with_mb_hook();
+	/* disable the keyboard reset function before mainboard GPIO setup */
+	if (CONFIG(DISABLE_KEYBOARD_RESET_PIN))
+		fch_disable_kb_rst();
+
+	/*
+	 * Skip eSPI configuration. The EFS/PSP DIR already contains eSPI configuration
+	 * so x86 does not need to configure it. Running configure_espi_with_mb_hook
+	 * and resetting eSPI causes the slave/AST2600 to stop printing output on serial
+	 * port. Boards may still configure I/O decodes early, if needed.
+	 *
+	 * configure_espi_with_mb_hook();
+	 */
 }
 
 /* After console init */
 void fch_early_init(void)
 {
+	reset_i2c_peripherals();
+	pm_set_power_failure_state();
+	fch_print_pmxc0_status();
+	i2c_soc_early_init();
+	show_spi_speeds_and_modes();
+
+	if (CONFIG(DISABLE_SPI_FLASH_ROM_SHARING))
+		lpc_disable_spi_rom_sharing();
 }
diff --git a/src/soc/amd/turin_poc/fch.c b/src/soc/amd/turin_poc/fch.c
index 46f97db8ea..a55abf2718 100644
--- a/src/soc/amd/turin_poc/fch.c
+++ b/src/soc/amd/turin_poc/fch.c
@@ -37,8 +37,23 @@ static const struct irq_idx_name irq_association[] = {
 	{ PIRQ_SCI,	"SCI" },
 	{ PIRQ_SMBUS,	"SMBUS" },
 	{ PIRQ_ASF,	"ASF" },
+	{ PIRQ_HDA,	"HDA" },
+	{ PIRQ_GBE0,	"GBE0" },
+	{ PIRQ_GBE1,	"GBE1" },
 	{ PIRQ_PMON,	"PerMon" },
+	{ PIRQ_SD,	"SD" },
 	{ PIRQ_SDIO,	"SDIO" },
+	{ PIRQ_CIR,	"CIR" },
+	{ PIRQ_GPIOA,	"GPIOa" },
+	{ PIRQ_GPIOB,	"GPIOb" },
+	{ PIRQ_GPIOC,	"GPIOc" },
+	{ PIRQ_USB_EMU,	"USB_EMU" },
+	{ PIRQ_USB_DR0,	"USB_DR0" },
+	{ PIRQ_USB_DR1,	"USB_DR1" },
+	{ PIRQ_XHCI0,	"XHCI0" },
+	{ PIRQ_SSIC,	"USB_SSIC" },
+	{ PIRQ_SATA,	"SATA" },
+	{ PIRQ_UFS,	"UFS" },
 	{ PIRQ_GPP0,	"GPP0" },
 	{ PIRQ_GPP1,	"GPP1" },
 	{ PIRQ_GPP2,	"GPP2" },
@@ -64,23 +79,62 @@ const struct irq_idx_name *sb_get_apic_reg_association(size_t *size)
 	return irq_association;
 }
 
-static void set_pci_irqs(void)
-{
-	/* Write PCI_INTR regs 0xC00/0xC01 */
-	write_pci_int_table();
-
-	/* TODO: PIRQ configuration */
-}
-
 static void fch_init_acpi_ports(void)
 {
-	/* Configure and enable APMC SMI Command Port */
-	pm_write16(PM_ACPI_SMI_CMD, APM_CNT);
-	configure_smi(SMITYPE_SMI_CMD_PORT, SMI_MODE_SMI);
+	uint32_t reg32;
+	uint8_t reg8;
+
+	if (CONFIG(HAVE_SMI_HANDLER)) {
+		/* Configure and enable APMC SMI Command Port */
+		pm_write16(PM_ACPI_SMI_CMD, APM_CNT);
+		configure_smi(SMITYPE_SMI_CMD_PORT, SMI_MODE_SMI);
+
+		/* SMI on SlpTyp requires sending SMI before completion
+		  response of the I/O write. */
+		reg32 = pm_read32(PM_PCI_CTRL);
+		reg32 |= FORCE_SLPSTATE_RETRY;
+		/* Ths bit should be cleared in case of SlpType SMI trapping */
+		reg32 &= ~FORCE_STPCLK_RETRY;
+		pm_write32(PM_PCI_CTRL, reg32);
+
+		/* Disable SlpTyp feature */
+		reg8 = pm_read8(PM_RST_CTRL1);
+		reg8 &= ~SLPTYPE_CONTROL_EN;
+		pm_write8(PM_RST_CTRL1, reg8);
+
+		configure_smi(SMITYPE_SLP_TYP, SMI_MODE_SMI);
+	} else {
+		pm_write16(PM_ACPI_SMI_CMD, 0);
+	}
+
+	/* Decode ACPI registers and enable standard features */
+	pm_write8(PM_ACPI_CONF, PM_ACPI_DECODE_STD |
+				PM_ACPI_GLOBAL_EN |
+				PM_ACPI_RTC_EN_EN |
+				PM_ACPI_TIMER_EN_EN);
+}
+
+static void fch_clk_output_48Mhz(void)
+{
+	uint32_t ctrl = misc_read32(MISC_CLK_CNTL0);
+	/* Enable BP_X48M0 Clock Output */
+	ctrl |= BP_X48M0_OUTPUT_EN;
+	misc_write32(MISC_CLK_CNTL0, ctrl);
+}
+
+static void fch_pci_int_vw_mode(void)
+{
+	pm_write32(0xa8, 0x80ffcef8);
 }
 
 void fch_init(void *chip_info)
 {
-	set_pci_irqs();
 	fch_init_acpi_ports();
+	fch_clk_output_48Mhz();
+
+	/* Write PCI_INTR regs 0xC00/0xC01 */
+	write_pci_int_table();
+	fch_pci_int_vw_mode();
+
+	fch_enable_ioapic_decode();
 }
diff --git a/src/soc/amd/turin_poc/gpio.c b/src/soc/amd/turin_poc/gpio.c
index c38719bf3f..72d0b2b0a4 100644
--- a/src/soc/amd/turin_poc/gpio.c
+++ b/src/soc/amd/turin_poc/gpio.c
@@ -20,6 +20,7 @@ static const struct soc_amd_event gpio_event_table[] = {
 	{ GPIO_23, GEVENT_16 },
 	{ GPIO_24, GEVENT_14 },
 	{ GPIO_26, GEVENT_15 },
+	{ GPIO_28, GEVENT_18 },
 	{ GPIO_76, GEVENT_11 },
 	{ GPIO_86, GEVENT_9 },
 	{ GPIO_89, GEVENT_0 },
diff --git a/src/soc/amd/turin_poc/include/soc/amd_pci_int_defs.h b/src/soc/amd/turin_poc/include/soc/amd_pci_int_defs.h
index f093247735..82915109a7 100644
--- a/src/soc/amd/turin_poc/include/soc/amd_pci_int_defs.h
+++ b/src/soc/amd/turin_poc/include/soc/amd_pci_int_defs.h
@@ -28,11 +28,29 @@
 #define PIRQ_SCI	0x10	/* SCI IRQ */
 #define PIRQ_SMBUS	0x11	/* SMBUS0 */
 #define PIRQ_ASF	0x12	/* ASF */
-/* 0x13-0x15 reserved */
+#define PIRQ_HDA	0x13	/* HDA */
+#define PIRQ_GBE0	0x14	/* GBE0 */
+#define PIRQ_GBE1	0x15	/* GBE1 */
 #define PIRQ_PMON	0x16	/* Performance Monitor */
-/* 0x17-0x19 reserved */
+#define PIRQ_SD		0x17	/* SD */
+/* 0x18-0x19 reserved */
 #define PIRQ_SDIO	0x1a	/* SDIO */
-/* 0x1b-0x49 reserved */
+/* 0x1b-0x1f reserved */
+#define PIRQ_CIR	0x20	/* CIR */
+#define PIRQ_GPIOA	0x21	/* GPIOa */
+#define PIRQ_GPIOB	0x22	/* GPIOb */
+#define PIRQ_GPIOC	0x23	/* GPIOc */
+/* 0x24-0x2f reserved */
+#define PIRQ_USB_EMU	0x30	/* USB Emulation */
+#define PIRQ_USB_DR0	0x31	/* USB Dual Role 1 */
+#define PIRQ_USB_DR1	0x32	/* USB Dual Role 2 */
+/* 0x33 reserved */
+#define PIRQ_XHCI0	0x34	/* XHCI0 */
+#define PIRQ_SSIC	0x35	/* USB SSIC */
+/* 0x36-0x40 reserved */
+#define PIRQ_SATA	0x41	/* SATA */
+#define PIRQ_UFS	0x42	/* UFS */
+/* 0x43-0x4f reserved */
 #define PIRQ_GPP0	0x50	/* GPPInt0 */
 #define PIRQ_GPP1	0x51	/* GPPInt1 */
 #define PIRQ_GPP2	0x52	/* GPPInt2 */
diff --git a/src/soc/amd/turin_poc/include/soc/aoac_defs.h b/src/soc/amd/turin_poc/include/soc/aoac_defs.h
index 156ee34962..2ee168ca59 100644
--- a/src/soc/amd/turin_poc/include/soc/aoac_defs.h
+++ b/src/soc/amd/turin_poc/include/soc/aoac_defs.h
@@ -18,7 +18,13 @@
 #define FCH_AOAC_DEV_I3C3		15
 #define FCH_AOAC_DEV_UART2		16
 #define FCH_AOAC_DEV_AMBA		17
+/* Bits 18-19 reserved */
+#define FCH_AOAC_DEV_UART4		20
 #define FCH_AOAC_DEV_I3C0		21
-#define FCH_AOAC_DEV_ESPI		27
+#define FCH_AOAC_DEV_ESPI1		22
+/* Bits 23-25 reserved */
+#define FCH_AOAC_DEV_UART3		26
+#define FCH_AOAC_DEV_ESPI		27 /* RO */
+#define FCH_AOAC_DEV_CPU		31
 
 #endif /* AMD_TURIN_POC_AOAC_DEFS_H */
diff --git a/src/soc/amd/turin_poc/include/soc/cpu.h b/src/soc/amd/turin_poc/include/soc/cpu.h
index eada9233fa..618ecf81d6 100644
--- a/src/soc/amd/turin_poc/include/soc/cpu.h
+++ b/src/soc/amd/turin_poc/include/soc/cpu.h
@@ -3,7 +3,8 @@
 #ifndef AMD_TURIN_POC_CPU_H
 #define AMD_TURIN_POC_CPU_H
 
-#define TURIN_A0_CPUID		CPUID_FROM_FMS(0x19, 0x10, 0)
-#define TURIN_B0_CPUID		CPUID_FROM_FMS(0x19, 0x11, 0)
+#define TURIN_Ax_CPUID		CPUID_FROM_FMS(0x1a, 0x0, 0)
+#define TURIN_Bx_CPUID		CPUID_FROM_FMS(0x1a, 0x1, 0)
+#define TURIN_Cx_CPUID		CPUID_FROM_FMS(0x1a, 0x2, 0)
 
 #endif /* AMD_TURIN_POC_CPU_H */
diff --git a/src/soc/amd/turin_poc/include/soc/data_fabric.h b/src/soc/amd/turin_poc/include/soc/data_fabric.h
index 503dc39afb..590ada3660 100644
--- a/src/soc/amd/turin_poc/include/soc/data_fabric.h
+++ b/src/soc/amd/turin_poc/include/soc/data_fabric.h
@@ -23,7 +23,7 @@ union df_vga_en {
 #define DF_PCI_CFG_BASE0		DF_REG_ID(0, 0xc80)
 #define DF_PCI_CFG_LIMIT0		DF_REG_ID(0, 0xc84)
 
-#define DF_PCI_CFG_MAP_COUNT		8
+#define DF_PCI_CFG_MAP_COUNT		16
 
 #define DF_PCI_CFG_REG_OFFSET(instance)	((instance) * 2 * sizeof(uint32_t))
 #define DF_PCI_CFG_BASE(reg)		(DF_PCI_CFG_BASE0 + DF_PCI_CFG_REG_OFFSET(reg))
@@ -54,7 +54,7 @@ union df_pci_cfg_limit {
 #define DF_IO_BASE0			DF_REG_ID(0, 0xd00)
 #define DF_IO_LIMIT0			DF_REG_ID(0, 0xd04)
 
-#define DF_IO_REG_COUNT			8
+#define DF_IO_REG_COUNT			16
 
 #define DF_IO_REG_OFFSET(instance)	((instance) * 2 * sizeof(uint32_t))
 #define DF_IO_BASE(reg)			(DF_IO_BASE0 + DF_IO_REG_OFFSET(reg))
@@ -93,13 +93,13 @@ union df_io_limit {
 #define   DF_MMIO_EXT_ADDR_SHIFT	48
 
 #define DF_MMIO_REG_SET_SIZE		4
-#define DF_MMIO_REG_SET_COUNT		16
+#define DF_MMIO_REG_SET_COUNT		32
 
 union df_mmio_control {
 	struct {
 		uint32_t re		:  1; /* [ 0.. 0] */
 		uint32_t we		:  1; /* [ 1.. 1] */
-		uint32_t		:  1; /* [ 2.. 2] */
+		uint32_t cpu_dis	:  1; /* [ 2.. 2] */
 		uint32_t np		:  1; /* [ 3.. 3] */
 		uint32_t		: 12; /* [ 4..15] */
 		uint32_t dst_fabric_id	: 12; /* [16..27] */
@@ -124,13 +124,13 @@ union df_mmio_addr_ext {
 
 union df_ficaa {
 	struct {
-		uint32_t cfg_inst_acc_en :  1; /* [ 0.. 0] */
-		uint32_t reg_num         : 10; /* [10.. 1] */
-		uint32_t func_num        :  3; /* [13..11] */
-		uint32_t b64_en          :  1; /* [14..14] */
-		uint32_t                 :  1; /* [15..15] */
-		uint32_t inst_id         :  8; /* [23..16] */
-		uint32_t                 :  8; /* [31..24] */
+		uint32_t cfg_inst_acc_en	:  1; /* [ 0.. 0] */
+		uint32_t reg_num		: 10; /* [10.. 1] */
+		uint32_t func_num		:  3; /* [13..11] */
+		uint32_t b64_en			:  1; /* [14..14] */
+		uint32_t			:  1; /* [15..15] */
+		uint32_t inst_id		:  9; /* [24..16] */
+		uint32_t			:  7; /* [31..25] */
 	};
 	uint32_t raw;
 };
diff --git a/src/soc/amd/turin_poc/include/soc/gpio.h b/src/soc/amd/turin_poc/include/soc/gpio.h
index 613fea7f25..d2890aa50b 100644
--- a/src/soc/amd/turin_poc/include/soc/gpio.h
+++ b/src/soc/amd/turin_poc/include/soc/gpio.h
@@ -25,7 +25,6 @@
 #define GPIO_4				4
 #define GPIO_5				5
 #define GPIO_6				6
-#define GPIO_7				7
 #define GPIO_12				12
 #define GPIO_13				13
 #define GPIO_14				14
@@ -38,15 +37,29 @@
 #define GPIO_23				23
 #define GPIO_24				24
 #define GPIO_26				26
+#define GPIO_27				27
+#define GPIO_28				28
+#define GPIO_29				29
+#define GPIO_30				30
+#define GPIO_31				31
+#define GPIO_32				32
+#define GPIO_40				40
+#define GPIO_42				42
+#define GPIO_70				70
 
 /* Bank 1: GPIO_64 - GPIO_127 */
 #define GPIO_74				74
 #define GPIO_75				75
 #define GPIO_76				76
+#define GPIO_84				84
+#define GPIO_85				85
 #define GPIO_86				86
 #define GPIO_87				87
 #define GPIO_88				88
 #define GPIO_89				89
+#define GPIO_90				90
+#define GPIO_91				91
+#define GPIO_92				92
 #define GPIO_104			104
 #define GPIO_105			105
 #define GPIO_106			106
@@ -54,6 +67,8 @@
 #define GPIO_108			108
 #define GPIO_109			109
 #define GPIO_110			110
+#define GPIO_113			113
+#define GPIO_114			114
 #define GPIO_115			115
 #define GPIO_116			116
 #define GPIO_117			117
@@ -69,6 +84,7 @@
 
 /* Bank 2: GPIO_128 - GPIO_191 */
 #define GPIO_129			129
+#define GPIO_130			130
 #define GPIO_131			131
 #define GPIO_132			132
 #define GPIO_133			133
@@ -78,8 +94,11 @@
 #define GPIO_137			137
 #define GPIO_138			138
 #define GPIO_139			139
+#define GPIO_140			140
 #define GPIO_141			141
 #define GPIO_142			142
+#define GPIO_143			143
+#define GPIO_144			144
 #define GPIO_145			145
 #define GPIO_146			146
 #define GPIO_147			147
@@ -96,16 +115,13 @@
 #define GPIO_259			259
 #define GPIO_260			260
 #define GPIO_261			261
-#define GPIO_262			262
-#define GPIO_263			263
 #define GPIO_264			264
 #define GPIO_265			265
 #define GPIO_266			266
 
 /* IOMUX function names and values */
 #define GPIO_0_IOMUX_PWR_BTN_L 0
-#define GPIO_0_IOMUX_GPIO_PU1PD0 1
-#define GPIO_0_IOMUX_GPIOxx 2
+#define GPIO_0_IOMUX_GPIOxx 1
 #define GPIO_1_IOMUX_SYS_RESET_L 0
 #define GPIO_1_IOMUX_GPIOxx 1
 #define GPIO_2_IOMUX_WAKE_L 0
@@ -121,12 +137,10 @@
 #define GPIO_12_IOMUX_PWRGD_OUT 0
 #define GPIO_12_IOMUX_GPIOxx 1
 #define GPIO_13_IOMUX_I2C4_SCL 0
-#define GPIO_13_IOMUX_CLK_48_24_0 1
-#define GPIO_13_IOMUX_GPIOxx 2
+#define GPIO_13_IOMUX_GPIOxx 1
 #define GPIO_14_IOMUX_I2C4_SDA 0
-#define GPIO_14_IOMUX_S0A3 1
-#define GPIO_14_IOMUX_GPIOxx 2
-#define GPIO_16_IOMUX_USB_1O_OC_L 0
+#define GPIO_14_IOMUX_GPIOxx 1
+#define GPIO_16_IOMUX_USB10_OC_L 0
 #define GPIO_16_IOMUX_GPIOxx 1
 #define GPIO_17_IOMUX_USB11_OC_L 0
 #define GPIO_17_IOMUX_GPIOxx 1
@@ -136,35 +150,52 @@
 #define GPIO_20_IOMUX_I2C5_SDA 0
 #define GPIO_20_IOMUX_SMBUS1_SDA 1
 #define GPIO_20_IOMUX_GPIOxx 2
-#define GPIO_21_IOMUX_GPIOxx 0
-#define GPIO_22_IOMUX_GPIOxx 0
+#define GPIO_21_IOMUX_GPIOxx 2
+#define GPIO_22_IOMUX_GPIOxx 2
 #define GPIO_23_IOMUX_ESPI_RST_OUT_L 0
 #define GPIO_23_IOMUX_GPIOxx 1
 #define GPIO_24_IOMUX_SMERR_L 0
 #define GPIO_24_IOMUX_GPIOxx 1
 #define GPIO_26_IOMUX_PCIE_RST1_L 0
 #define GPIO_26_IOMUX_GPIOxx 1
+#define GPIO_27_IOMUX_GPIOxx 1
+#define GPIO_28_IOMUX_X48M_OUT 0
+#define GPIO_29_IOMUX_GPIOxx 0
+#define GPIO_30_IOMUX_GPIOxx 0
+#define GPIO_31_IOMUX_GPIOxx 0
+#define GPIO_32_IOMUX_GPIOxx 0
+#define GPIO_40_IOMUX_GPIOxx 0
+#define GPIO_42_IOMUX_GPIOxx 0
+#define GPIO_70_IOMUX_GPIOxx 0
 #define GPIO_74_IOMUX_ESPI_CLK2 0
-#define GPIO_74_IOMUX_GPIOxx 1
+#define GPIO_74_IOMUX_GPIOxx 2
 #define GPIO_75_IOMUX_ESPI_CLK1 0
-#define GPIO_75_IOMUX_GPIOxx 1
+#define GPIO_75_IOMUX_GPIOxx 2
 #define GPIO_76_IOMUX_GPIOxx 0
 #define GPIO_76_IOMUX_SPI_TPM_CS_L 1
-#define GPIO_86_IOMUX_NMI_SYNC_FLOOD_L 0
-#define GPIO_87_IOMUX_GPIOxx 0
-#define GPIO_88_IOMUX_GPIOxx 0
+#define GPIO_84_IOMUX_GPIOxx 1
+#define GPIO_85_IOMUX_GPIOxx 1
+#define GPIO_86_IOMUX_GPIOxx 1
+#define GPIO_86_IOMUX_LPC_SMI_L 2
+#define GPIO_87_IOMUX_GPIOxx 2
+#define GPIO_88_IOMUX_GPIOxx 2
 #define GPIO_89_IOMUX_GENINT_L 0
 #define GPIO_89_IOMUX_PM_INTR_L 1
 #define GPIO_89_IOMUX_GPIOxx 2
-#define GPIO_104_IOMUX_GPIOxx 0
-#define GPIO_105_IOMUX_GPIOxx 0
-#define GPIO_106_IOMUX_GPIOxx 0
-#define GPIO_107_IOMUX_GPIOxx 0
+#define GPIO_90_IOMUX_GPIOxx 2
+#define GPIO_91_IOMUX_GPIOxx 1
+#define GPIO_92_IOMUX_GPIOxx 3
+#define GPIO_104_IOMUX_GPIOxx 3
+#define GPIO_105_IOMUX_GPIOxx 3
+#define GPIO_106_IOMUX_GPIOxx 3
+#define GPIO_107_IOMUX_GPIOxx 3
 #define GPIO_108_IOMUX_ESPI0_ALERT_D1 0
-#define GPIO_108_IOMUX_GPIOxx 1
-#define GPIO_109_IOMUX_GPIOxx 0
+#define GPIO_108_IOMUX_GPIOxx 2
+#define GPIO_109_IOMUX_GPIOxx 2
 #define GPIO_110_IOMUX_ESPI1_ALERT_D1 0
 #define GPIO_110_IOMUX_GPIOxx 1
+#define GPIO_113_IOMUX_GPIOxx 2
+#define GPIO_114_IOMUX_GPIOxx 2
 #define GPIO_115_IOMUX_GPIOxx 0
 #define GPIO_115_IOMUX_CLK_REQ11_L 1
 #define GPIO_116_IOMUX_GPIOxx 0
@@ -174,7 +205,7 @@
 #define GPIO_118_IOMUX_SPI_CS0_L 0
 #define GPIO_118_IOMUX_GPIOxx 1
 #define GPIO_119_IOMUX_SPI_CS1_L 0
-#define GPIO_119_IOMUX_GPIOxx 1
+#define GPIO_119_IOMUX_GPIOxx 2
 #define GPIO_120_IOMUX_ESPI0_DATA0 0
 #define GPIO_120_IOMUX_GPIOxx 1
 #define GPIO_121_IOMUX_ESPI0_DATA1 0
@@ -192,8 +223,9 @@
 #define GPIO_129_IOMUX_ESPI_RSTIN_L 0
 #define GPIO_129_IOMUX_KBRST_L 1
 #define GPIO_129_IOMUX_GPIOxx 2
+#define GPIO_130_IOMUX_GPIOxx 1
 #define GPIO_131_IOMUX_ESPI1_DATA0 0
-#define GPIO_131_IOMUX_GPIOxx 1
+#define GPIO_131_IOMUX_GPIOxx 3
 #define GPIO_132_IOMUX_ESPI1_DATA1 0
 #define GPIO_132_IOMUX_GPIOxx 1
 #define GPIO_133_IOMUX_ESPI1_DATA2 0
@@ -212,10 +244,15 @@
 #define GPIO_138_IOMUX_GPIOxx 1
 #define GPIO_139_IOMUX_UART0_INTR 0
 #define GPIO_139_IOMUX_GPIOxx 1
+#define GPIO_140_IOMUX_UART3_RXD 0
+#define GPIO_140_IOMUX_GPIOxx 2
 #define GPIO_141_IOMUX_UART1_RXD 0
 #define GPIO_141_IOMUX_GPIOxx 1
 #define GPIO_142_IOMUX_UART1_TXD 0
-#define GPIO_142_IOMUX_GPIOxx 1
+#define GPIO_142_IOMUX_UART3_TXD 1
+#define GPIO_142_IOMUX_GPIOxx 2
+#define GPIO_143_IOMUX_GPIOxx 1
+#define GPIO_144_IOMUX_GPIOxx 1
 #define GPIO_145_IOMUX_I3C0_SCL_SPD0_SCL 0
 #define GPIO_145_IOMUX_I2C0_SCL_SPD0_SCL 1
 #define GPIO_145_IOMUX_SMBUS0_SCL 2
@@ -258,8 +295,6 @@
 #define GPIO_260_IOMUX_GPIOxx 1
 #define GPIO_261_IOMUX_SGPIO_LOAD 0
 #define GPIO_261_IOMUX_GPIOxx 1
-#define GPIO_262_IOMUX_GPIOxx 0
-#define GPIO_263_IOMUX_GPIOxx 0
 #define GPIO_264_IOMUX_USB00_OC_L 0
 #define GPIO_264_IOMUX_GPIOxx 1
 #define GPIO_265_IOMUX_USB01_OC_L 0
diff --git a/src/soc/amd/turin_poc/include/soc/iomap.h b/src/soc/amd/turin_poc/include/soc/iomap.h
index f1d692121f..d85597e051 100644
--- a/src/soc/amd/turin_poc/include/soc/iomap.h
+++ b/src/soc/amd/turin_poc/include/soc/iomap.h
@@ -8,17 +8,20 @@
 #define I2C_CTRLR_COUNT			(I2C_MASTER_DEV_COUNT + I2C_PERIPHERAL_DEV_COUNT)
 #define I3C_CTRLR_COUNT			4
 
+#define ACPIMMIO_RGPIO_BASE		0xfed81200
+
 #define SPI_BASE_ADDRESS		0xfec10000
 
-/* @Todo : Check these values for Turin */
-
-/* I/O Ranges */
-#define ACPI_IO_BASE			0x0400
-#define  ACPI_CSTATE_CONTROL		(ACPI_IO_BASE + 0x10)
+#define FCH_WATCHDOG_BASE		0xfeb00000
 
 /* FCH AL2AHB Registers */
 #define ALINK_AHB_ADDRESS		0xfedc0000
 
+#define APU_DMA0_BASE			0xfedc7000
+#define APU_DMA1_BASE			0xfedc8000
+#define APU_DMA2_BASE			0xfedcc000
+#define APU_DMA3_BASE			0xfedcd000
+
 #define APU_I2C0_BASE			0xfedc2000
 #define APU_I2C1_BASE			0xfedc3000
 #define APU_I2C2_BASE			0xfedc4000
@@ -29,10 +32,25 @@
 #define APU_UART0_BASE			0xfedc9000
 #define APU_UART1_BASE			0xfedca000
 #define APU_UART2_BASE			0xfedce000
+#define APU_UART3_BASE			0xfedcf000
+#define APU_UART4_BASE			0xfedd1000
 
 #define APU_I3C0_BASE			0xfedd2000
 #define APU_I3C1_BASE			0xfedd3000
 #define APU_I3C2_BASE			0xfedd4000
 #define APU_I3C3_BASE			0xfedd6000
 
+/* I/O Ranges */
+#define ACPI_IO_BASE			0x0400
+#define  ACPI_PM_EVT_BLK		(ACPI_IO_BASE + 0x00)
+#define   ACPI_PM1_STS			(ACPI_PM_EVT_BLK + 0x00)
+#define   ACPI_PM1_EN			(ACPI_PM_EVT_BLK + 0x02)
+#define  ACPI_PM1_CNT_BLK		(ACPI_IO_BASE + 0x04)
+#define  ACPI_PM_TMR_BLK		(ACPI_IO_BASE + 0x08)
+#define  ACPI_CSTATE_CONTROL		(ACPI_IO_BASE + 0x10)
+#define  ACPI_GPE0_BLK			(ACPI_IO_BASE + 0x20)
+#define   ACPI_GPE0_STS			(ACPI_GPE0_BLK + 0x00)
+#define   ACPI_GPE0_EN			(ACPI_GPE0_BLK + 0x04)
+#define SMB_BASE_ADDR			0x0b00
+
 #endif /* AMD_TURIN_POC_IOMAP_H */
diff --git a/src/soc/amd/turin_poc/include/soc/msr.h b/src/soc/amd/turin_poc/include/soc/msr.h
index ba2c25f997..a1773b2269 100644
--- a/src/soc/amd/turin_poc/include/soc/msr.h
+++ b/src/soc/amd/turin_poc/include/soc/msr.h
@@ -8,8 +8,8 @@
 /* MSRC001_00[6B:64] P-state [7:0] bit definitions */
 union pstate_msr {
 	struct {
-		uint64_t cpu_fid_0_7	:  8; /* [ 0.. 7] */
-		uint64_t cpu_dfs_id	:  6; /* [ 8..13] */
+		uint64_t cpu_fid_0_11	: 12; /* [ 0..11] */
+		uint64_t		:  2; /* [12..13] */
 		uint64_t cpu_vid_0_7	:  8; /* [14..21] */
 		uint64_t idd_value	:  8; /* [22..29] */
 		uint64_t idd_div	:  2; /* [30..31] */
diff --git a/src/soc/amd/turin_poc/include/soc/smi.h b/src/soc/amd/turin_poc/include/soc/smi.h
index df56b6750f..7712860531 100644
--- a/src/soc/amd/turin_poc/include/soc/smi.h
+++ b/src/soc/amd/turin_poc/include/soc/smi.h
@@ -78,7 +78,8 @@
 /* 31 Reserved */
 #define SMITYPE_WAKE_L2			32
 #define SMITYPE_PSP			33
-/* 34-35 Reserved */
+#define SMITYPE_PSP2			34
+#define SMITYPE_PSP3			35
 #define SMITYPE_ESPI_SCI_B		36
 #define SMITYPE_ESPI1_SYS_EVT_B		37
 #define SMITYPE_ESPI1_WAKE_PME		38
diff --git a/src/soc/amd/turin_poc/include/soc/smu.h b/src/soc/amd/turin_poc/include/soc/smu.h
index dd34044264..e18fc8e3b0 100644
--- a/src/soc/amd/turin_poc/include/soc/smu.h
+++ b/src/soc/amd/turin_poc/include/soc/smu.h
@@ -1,11 +1,11 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
-#ifndef AMD_GENOA_POC_SMU_H
-#define AMD_GENOA_POC_SMU_H
+#ifndef AMD_TURIN_POC_SMU_H
+#define AMD_TURIN_POC_SMU_H
 
 /* SMU mailbox register offsets in SMN */
-#define SMN_SMU_MESG_ID		0x3b10530
-#define SMN_SMU_MESG_RESP	0x3b1057c
+#define SMN_SMU_MESG_ID		0x3b10930
+#define SMN_SMU_MESG_RESP	0x3b1097c
 #define SMN_SMU_MESG_ARGS_BASE	0x3b109c4
 
 #define SMU_NUM_ARGS		6
@@ -20,4 +20,4 @@ enum smu_message_id {
  */
 void smu_sx_entry(void);
 
-#endif /* AMD_GENOA_POC_SMU_H */
+#endif /* AMD_TURIN_POC_SMU_H */
diff --git a/src/soc/amd/turin_poc/include/soc/southbridge.h b/src/soc/amd/turin_poc/include/soc/southbridge.h
index 1027a58455..8447b32be7 100644
--- a/src/soc/amd/turin_poc/include/soc/southbridge.h
+++ b/src/soc/amd/turin_poc/include/soc/southbridge.h
@@ -1,7 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
-#ifndef AMD_GENOA_POC_SOUTHBRIDGE_H
-#define AMD_GENOA_POC_SOUTHBRIDGE_H
+#ifndef AMD_TURIN_POC_SOUTHBRIDGE_H
+#define AMD_TURIN_POC_SOUTHBRIDGE_H
 
 #include <soc/iomap.h>
 
@@ -9,6 +9,7 @@
 #define PM_ISACONTROL			0x04
 #define   ABCLKGATEEN			BIT(16)
 #define PM_PCI_CTRL			0x08
+#define   FORCE_STPCLK_RETRY		BIT(24)
 #define   FORCE_SLPSTATE_RETRY		BIT(25)
 #define PWR_RESET_CFG			0x10
 #define   TOGGLE_ALL_PWR_GOOD		(1 << 1)
@@ -72,8 +73,6 @@
 #define   PM_ACPI_RTC_WAKE_EN		BIT(29)
 #define   PM_ACPI_USE_GATED_ALINK_CLK	BIT(30)
 #define   PM_ACPI_DELAY_GPP_OFF_TIME	BIT(31)
-#define PM_SPI_PAD_PU_PD		0x90
-#define   PM_ESPI_CS_USE_DATA2		BIT(16)
 #define PM_LPC_GATING			0xec
 #define   PM_LPC_AB_NO_BYPASS_EN	BIT(2)
 #define   PM_LPC_A20_EN			BIT(1)
@@ -119,4 +118,4 @@ void fch_pre_init(void);
 void fch_early_init(void);
 void fch_init(void *chip_info);
 
-#endif /* AMD_GENOA_POC_SOUTHBRIDGE_H */
+#endif /* AMD_TURIN_POC_SOUTHBRIDGE_H */
diff --git a/src/soc/amd/turin_poc/include/soc/xhci.h b/src/soc/amd/turin_poc/include/soc/xhci.h
new file mode 100644
index 0000000000..4645a629d2
--- /dev/null
+++ b/src/soc/amd/turin_poc/include/soc/xhci.h
@@ -0,0 +1,17 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef AMD_TURIN_XHCI_H
+#define AMD_TURIN_XHCI_H
+
+#include <static.h>
+
+#define SOC_XHCI_0 DEV_PTR(xhci_0)
+#define SOC_XHCI_1 DEV_PTR(xhci_1)
+#define SOC_XHCI_2 NULL
+#define SOC_XHCI_3 NULL
+#define SOC_XHCI_4 NULL
+#define SOC_XHCI_5 NULL
+#define SOC_XHCI_6 NULL
+#define SOC_XHCI_7 NULL
+
+#endif /* AMD_TURIN_XHCI_H */
diff --git a/src/soc/amd/turin_poc/mca.c b/src/soc/amd/turin_poc/mca.c
index 9a6df2b53e..460d9afee2 100644
--- a/src/soc/amd/turin_poc/mca.c
+++ b/src/soc/amd/turin_poc/mca.c
@@ -4,7 +4,11 @@
 #include <cpu/x86/msr.h>
 #include <types.h>
 
-/* TODO: Check if non-core MCA banks are same for all cores */
+/*
+ * Non-core MCA banks are not the same for all cores.
+ * Refer to "Table 56: Non-core MCA Bank to Block Mapping"
+ * in Turin C1 PPR (doc 57238).
+ */
 static const char *const mca_bank_name[] = {
 	[0]  = "Load-store unit",
 	[1]  = "Instruction fetch unit",
@@ -22,22 +26,22 @@ static const char *const mca_bank_name[] = {
 	[13] = "L3 cache unit",
 	[14] = "L3 cache unit",
 	[15] = "Microprocessor5 Management Controller",
-	[16] = "Parameter Block",
-	[17] = "GMI Controller",
-	[18] = "GMI Controller",
-	[19] = "High Speed Interface Unit (GMI)",
-	[20] = "High Speed Interface Unit (GMI)",
+	[16] = "GMI Controller (PCS_GMI)",
+	[17] = "GMI Controller (PCS_GMI)",
+	[18] = "High Speed Interface Unit (KPX_GMI)",
+	[19] = "High Speed Interface Unit (KPX_GMI)",
+	[20] = "MPDMA",
 	[21] = "Unified Memory Controller",
 	[22] = "Unified Memory Controller",
 	[23] = "Coherent Station",
 	[24] = "Coherent Station",
-	[25] = "Northbridge IO Unit",
-	[26] = "PCIe Root Port",
-	[27] = "PCIe Root Port",
-	[28] = "Power Management, Interrupts, Etc.",
+	[25] = "PCIE",
+	[26] = "SATA",
+	[27] = "Northbridge IO Unit",
+	[28] = "NBIF",
 	[29] = "SMU",
-	[30] = "XGMI Controller",
-	[31] = "High Speed Interface Unit (XGMI)",
+	[30] = "Power Management, Interrupts, Etc.",
+	[31] = "High Speed Interface Unit (SERDES)",
 };
 
 bool mca_has_expected_bank_count(void)
diff --git a/src/soc/amd/turin_poc/root_complex.c b/src/soc/amd/turin_poc/root_complex.c
index 3171febe9f..ffff6d1c32 100644
--- a/src/soc/amd/turin_poc/root_complex.c
+++ b/src/soc/amd/turin_poc/root_complex.c
@@ -2,24 +2,52 @@
 
 #include <amdblocks/ioapic.h>
 #include <amdblocks/root_complex.h>
+#include <device/device.h>
+#include <device/pci.h>
 #include <types.h>
 
+/*
+ * The order of IOHCs here is not random. They are sorted so that:
+ * 1. The First IOHC is the one with primary FCH. We want the LPC/SMBUS
+ *    devices be on bus 0.
+ * 2. The rest of IOHCs are listed in an order so that ECAM MMIO region is one
+ *    continuous block for all domains.
+ *
+ * AGESA/OpenSIL sets up the PCI configuration decoding ranges in line with
+ * this.
+ */
 static const struct domain_iohc_info iohc_info[] = {
 	[0] = {
-		.fabric_id = 0x22,
-		.misc_smn_base = SMN_IOHC_MISC_BASE_13C1,
+		.fabric_id = 0x24,
+		.misc_smn_base = SMN_IOHC_MISC_BASE_13D1,
 	},
 	[1] = {
-		.fabric_id = 0x23,
-		.misc_smn_base = SMN_IOHC_MISC_BASE_13B1,
+		.fabric_id = 0x25,
+		.misc_smn_base = SMN_IOHC_MISC_BASE_1D61,
 	},
 	[2] = {
-		.fabric_id = 0x21,
+		.fabric_id = 0x26,
 		.misc_smn_base = SMN_IOHC_MISC_BASE_13E1,
 	},
 	[3] = {
+		.fabric_id = 0x27,
+		.misc_smn_base = SMN_IOHC_MISC_BASE_1D51,
+	},
+	[4] = {
+		.fabric_id = 0x23,
+		.misc_smn_base = SMN_IOHC_MISC_BASE_1D41,
+	},
+	[5] = {
+		.fabric_id = 0x22,
+		.misc_smn_base = SMN_IOHC_MISC_BASE_13C1,
+	},
+	[6] = {
+		.fabric_id = 0x21,
+		.misc_smn_base = SMN_IOHC_MISC_BASE_1D71,
+	},
+	[7] = {
 		.fabric_id = 0x20,
-		.misc_smn_base = SMN_IOHC_MISC_BASE_13D1,
+		.misc_smn_base = SMN_IOHC_MISC_BASE_13B1,
 	},
 };
 
@@ -33,15 +61,18 @@ static const struct non_pci_mmio_reg non_pci_mmio[] = {
 	{ 0x2d8, 0xfffffff00000ull,   1 * MiB, NON_PCI_RES_IDX_AUTO },
 	{ 0x2e0, 0xfffffff00000ull,   1 * MiB, NON_PCI_RES_IDX_AUTO },
 	{ 0x2e8, 0xfffffff00000ull,   1 * MiB, NON_PCI_RES_IDX_AUTO },
-	/* The hardware has a 256 byte alignment requirement for the IOAPIC MMIO base, but we
-	   tell the FSP to configure a 4k-aligned base address and this is reported as 4 KiB
-	   resource. */
-	{ 0x2f0, 0xffffffffff00ull,   4 * KiB, IOMMU_IOAPIC_IDX },
+	/*
+	 * The hardware has a 256 byte alignment requirement for the IOAPIC
+	 * MMIO base, but OpenSIL configures 64k-aligned base address and this
+	 * is reported as 256 byte resource.
+	 */
+	{ 0x2f0, 0xffffffffff00ull,	  256, IOMMU_IOAPIC_IDX },
 	{ 0x2f8, 0xfffffff00000ull,   1 * MiB, NON_PCI_RES_IDX_AUTO },
 	{ 0x300, 0xfffffff00000ull,   1 * MiB, NON_PCI_RES_IDX_AUTO },
 	{ 0x308, 0xfffffffff000ull,   4 * KiB, NON_PCI_RES_IDX_AUTO },
 	{ 0x310, 0xfffffff00000ull,   1 * MiB, NON_PCI_RES_IDX_AUTO },
 	{ 0x318, 0xfffffff80000ull, 512 * KiB, NON_PCI_RES_IDX_AUTO },
+	{ 0x338, 0xfffffff00000ull,   1 * MiB, NON_PCI_RES_IDX_AUTO },
 };
 
 const struct non_pci_mmio_reg *get_iohc_non_pci_mmio_regs(size_t *count)
@@ -49,3 +80,17 @@ const struct non_pci_mmio_reg *get_iohc_non_pci_mmio_regs(size_t *count)
 	*count = ARRAY_SIZE(non_pci_mmio);
 	return non_pci_mmio;
 }
+
+static const char *gnb_acpi_name(const struct device *dev)
+{
+	return "GNB";
+}
+
+struct device_operations turin_root_complex_operations = {
+	/* The root complex has no PCI BARs implemented, so there's no need to call
+	   pci_dev_read_resources for it */
+	.read_resources		= noop_read_resources,
+	.set_resources		= noop_set_resources,
+	.enable_resources	= pci_dev_enable_resources,
+	.acpi_name		= gnb_acpi_name,
+};
diff --git a/src/soc/amd/turin_poc/smihandler.c b/src/soc/amd/turin_poc/smihandler.c
index 1eb051317b..80185a843d 100644
--- a/src/soc/amd/turin_poc/smihandler.c
+++ b/src/soc/amd/turin_poc/smihandler.c
@@ -61,6 +61,7 @@ static void fch_slp_typ_handler(void)
 		/* Do not send SMI before AcpiPm1CntBlkx00[SlpTyp] */
 		pci_ctrl = pm_read32(PM_PCI_CTRL);
 		pci_ctrl &= ~FORCE_SLPSTATE_RETRY;
+		pci_ctrl |= FORCE_STPCLK_RETRY;
 		pm_write32(PM_PCI_CTRL, pci_ctrl);
 
 		/* Enable SlpTyp */
diff --git a/src/soc/amd/turin_poc/uart.c b/src/soc/amd/turin_poc/uart.c
index 19f7746bc8..c90485318f 100644
--- a/src/soc/amd/turin_poc/uart.c
+++ b/src/soc/amd/turin_poc/uart.c
@@ -24,6 +24,10 @@ static const struct soc_uart_ctrlr_info uart_info[] = {
 			PAD_NF(GPIO_137, UART2_RXD, PULL_NONE),
 			PAD_NF(GPIO_135, UART2_TXD, PULL_NONE),
 		} },
+	[3] =	{ APU_UART2_BASE, FCH_AOAC_DEV_UART3, "FUR3", {
+			PAD_NF(GPIO_140, UART3_RXD, PULL_NONE),
+			PAD_NF(GPIO_142, UART3_TXD, PULL_NONE),
+		} },
 };
 
 const struct soc_uart_ctrlr_info *soc_get_uart_ctrlr_info(size_t *num_ctrlrs)

From cb25e6cb72df99f7bbe7a65a0287b09ab1bdbbb6 Mon Sep 17 00:00:00 2001
From: Maximilian Brune <maximilian.brune@9elements.com>
Date: Fri, 28 Nov 2025 21:50:52 +0100
Subject: [PATCH 3113/3886] mb/amd/birman_plus: Increase flash size to 64M

Update it as per schematics.

Since the commit wasn't actually tested with the phoenix SOC, keep the
BIOS region in the first 16M.

Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: I6138d37be1b56178ce989996109157671f6973b1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90265
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/amd/birman_plus/board_phoenix.fmd    | 4 ++--
 src/mainboard/amd/birman_plus/chromeos_glinda.fmd  | 4 ++--
 src/mainboard/amd/birman_plus/chromeos_phoenix.fmd | 4 ++--
 3 files changed, 6 insertions(+), 6 deletions(-)

diff --git a/src/mainboard/amd/birman_plus/board_phoenix.fmd b/src/mainboard/amd/birman_plus/board_phoenix.fmd
index 4f5598cd77..1335409418 100644
--- a/src/mainboard/amd/birman_plus/board_phoenix.fmd
+++ b/src/mainboard/amd/birman_plus/board_phoenix.fmd
@@ -1,5 +1,5 @@
-FLASH 16M {
-	BIOS {
+FLASH 64M {
+	BIOS 16M {
 		EC_SIG 4K
 		FMAP 4K
 		COREBOOT(CBFS)
diff --git a/src/mainboard/amd/birman_plus/chromeos_glinda.fmd b/src/mainboard/amd/birman_plus/chromeos_glinda.fmd
index 9cc4fbd050..de5bcc788f 100644
--- a/src/mainboard/amd/birman_plus/chromeos_glinda.fmd
+++ b/src/mainboard/amd/birman_plus/chromeos_glinda.fmd
@@ -1,5 +1,5 @@
-FLASH 16M {
-	SI_BIOS {
+FLASH 64M {
+	SI_BIOS 16M {
 		WP_RO 8M {
 			EC_SIG 4K
 			RO_VPD(PRESERVE) 16K
diff --git a/src/mainboard/amd/birman_plus/chromeos_phoenix.fmd b/src/mainboard/amd/birman_plus/chromeos_phoenix.fmd
index 9cc4fbd050..de5bcc788f 100644
--- a/src/mainboard/amd/birman_plus/chromeos_phoenix.fmd
+++ b/src/mainboard/amd/birman_plus/chromeos_phoenix.fmd
@@ -1,5 +1,5 @@
-FLASH 16M {
-	SI_BIOS {
+FLASH 64M {
+	SI_BIOS 16M {
 		WP_RO 8M {
 			EC_SIG 4K
 			RO_VPD(PRESERVE) 16K

From f65f674343a2ef16501f0a40218f94082fa49e86 Mon Sep 17 00:00:00 2001
From: Maximilian Brune <maximilian.brune@9elements.com>
Date: Fri, 28 Nov 2025 21:51:50 +0100
Subject: [PATCH 3114/3886] mb/amd/birman: Increase flash size to 32M

Update as per schematics.

Since the commit wasn't actually tested on the mainboard, keep the BIOS
region in the first 16M.

Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: I6d3cdbec82539007c6a0923c1f1415882dd9f2c1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90266
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
---
 src/mainboard/amd/birman/board_glinda.fmd     | 4 ++--
 src/mainboard/amd/birman/board_phoenix.fmd    | 4 ++--
 src/mainboard/amd/birman/chromeos_glinda.fmd  | 4 ++--
 src/mainboard/amd/birman/chromeos_phoenix.fmd | 4 ++--
 4 files changed, 8 insertions(+), 8 deletions(-)

diff --git a/src/mainboard/amd/birman/board_glinda.fmd b/src/mainboard/amd/birman/board_glinda.fmd
index 4f5598cd77..01340430cd 100644
--- a/src/mainboard/amd/birman/board_glinda.fmd
+++ b/src/mainboard/amd/birman/board_glinda.fmd
@@ -1,5 +1,5 @@
-FLASH 16M {
-	BIOS {
+FLASH 32M {
+	BIOS 16M {
 		EC_SIG 4K
 		FMAP 4K
 		COREBOOT(CBFS)
diff --git a/src/mainboard/amd/birman/board_phoenix.fmd b/src/mainboard/amd/birman/board_phoenix.fmd
index 4f5598cd77..01340430cd 100644
--- a/src/mainboard/amd/birman/board_phoenix.fmd
+++ b/src/mainboard/amd/birman/board_phoenix.fmd
@@ -1,5 +1,5 @@
-FLASH 16M {
-	BIOS {
+FLASH 32M {
+	BIOS 16M {
 		EC_SIG 4K
 		FMAP 4K
 		COREBOOT(CBFS)
diff --git a/src/mainboard/amd/birman/chromeos_glinda.fmd b/src/mainboard/amd/birman/chromeos_glinda.fmd
index 9cc4fbd050..bf10c06c3b 100644
--- a/src/mainboard/amd/birman/chromeos_glinda.fmd
+++ b/src/mainboard/amd/birman/chromeos_glinda.fmd
@@ -1,5 +1,5 @@
-FLASH 16M {
-	SI_BIOS {
+FLASH 32M {
+	SI_BIOS 16M {
 		WP_RO 8M {
 			EC_SIG 4K
 			RO_VPD(PRESERVE) 16K
diff --git a/src/mainboard/amd/birman/chromeos_phoenix.fmd b/src/mainboard/amd/birman/chromeos_phoenix.fmd
index 9cc4fbd050..bf10c06c3b 100644
--- a/src/mainboard/amd/birman/chromeos_phoenix.fmd
+++ b/src/mainboard/amd/birman/chromeos_phoenix.fmd
@@ -1,5 +1,5 @@
-FLASH 16M {
-	SI_BIOS {
+FLASH 32M {
+	SI_BIOS 16M {
 		WP_RO 8M {
 			EC_SIG 4K
 			RO_VPD(PRESERVE) 16K

From f97a933140fc30a1bad53396beb9bd3b6d4fb72c Mon Sep 17 00:00:00 2001
From: Maximilian Brune <maximilian.brune@9elements.com>
Date: Fri, 28 Nov 2025 21:52:27 +0100
Subject: [PATCH 3115/3886] mb/amd/crater/Kconfig: Decrease flash size to 16M

Update because the board by default has 16M flash.

TEST=build and run on the crater mainboard

Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: I7ecb7721c523d8995e124b61715afac2090b3235
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90267
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
---
 src/mainboard/amd/crater/Kconfig | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/mainboard/amd/crater/Kconfig b/src/mainboard/amd/crater/Kconfig
index b2fc3d63e0..0861a216f7 100644
--- a/src/mainboard/amd/crater/Kconfig
+++ b/src/mainboard/amd/crater/Kconfig
@@ -2,7 +2,7 @@
 
 config BOARD_AMD_CRATER_COMMON
 	def_bool n
-	select BOARD_ROMSIZE_KB_32768
+	select BOARD_ROMSIZE_KB_16384
 	select EC_ACPI
 	select SOC_AMD_COMMON_BLOCK_USE_ESPI if !SOC_AMD_COMMON_BLOCK_SIMNOW_BUILD
 	select DRIVERS_PCIE_RTD3_DEVICE

From 4cc705e56d474fb79db0403b5bf8c4135ba50ef2 Mon Sep 17 00:00:00 2001
From: Maximilian Brune <maximilian.brune@9elements.com>
Date: Fri, 28 Nov 2025 21:52:58 +0100
Subject: [PATCH 3116/3886] mb/amd/mayan: Increase flash size to 32M

Update as per schematics.

Since the commit wasn't actually tested on the mainboard, keep the
BIOS region in the first 16M.

Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: I0f1ae9d410804380d5465dcae35cc5965515506f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90268
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
---
 src/mainboard/amd/mayan/board.fmd    | 4 ++--
 src/mainboard/amd/mayan/chromeos.fmd | 4 ++--
 2 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/src/mainboard/amd/mayan/board.fmd b/src/mainboard/amd/mayan/board.fmd
index 2600ec75a2..6ba6b4d68f 100644
--- a/src/mainboard/amd/mayan/board.fmd
+++ b/src/mainboard/amd/mayan/board.fmd
@@ -1,5 +1,5 @@
-FLASH 16M {
-	BIOS {
+FLASH 32M {
+	BIOS 16M {
 		EC 4K
 		FMAP 4K
 		COREBOOT(CBFS)
diff --git a/src/mainboard/amd/mayan/chromeos.fmd b/src/mainboard/amd/mayan/chromeos.fmd
index b77203f589..b819c9c3cc 100644
--- a/src/mainboard/amd/mayan/chromeos.fmd
+++ b/src/mainboard/amd/mayan/chromeos.fmd
@@ -1,5 +1,5 @@
-FLASH 16M {
-	SI_BIOS {
+FLASH 32M {
+	SI_BIOS 16M {
 		WP_RO 8M {
 			EC 4K
 			RO_VPD(PRESERVE) 16K

From f8a32a1cfa4aaa01a1b75b17f6e47d6ae3055d26 Mon Sep 17 00:00:00 2001
From: Maximilian Brune <maximilian.brune@9elements.com>
Date: Tue, 20 Jan 2026 18:23:35 +0100
Subject: [PATCH 3117/3886] include/fmap.h: Require FMAP_FLASH_SIZE ==
 CONFIG_ROM_SIZE

In our current tree this is always the case. The coreboot code (as far
as I know) doesn't have a hard requirement on that. But if these values
differ then it is usually always a mistake made by the programmer and it
is hard to catch since the value don't really depend on each other.
So until a time in which there comes a platform which needs a flashmap
that doesn't cover the whole flash, this check is introduced.

For that purpose we need to replace the default .config file for tests,
because otherwise the check won't match.

The config file that is used now is based on the fact that we use the
same mainboard for the `.config` as for the `fmap_config.h` in
`tests/include/tests/lib/fmap/fmap_config.h`

Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: I8bc05a17a2630516ede949660b4fc428f199f3ab
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90264
Reviewed-by: Jakub "Kuba" Czapiga <czapiga@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/include/fmap.h                    | 8 ++++++++
 tests/Makefile.common                 | 2 +-
 tests/include/tests/lib/fmap_config.h | 1 +
 3 files changed, 10 insertions(+), 1 deletion(-)

diff --git a/src/include/fmap.h b/src/include/fmap.h
index 900bfff542..1fadaef3c5 100644
--- a/src/include/fmap.h
+++ b/src/include/fmap.h
@@ -13,6 +13,14 @@
 	#error "FMAP must always start flash address 0"
 #endif
 
+/* This is usually the case. And it can to lead to confusion if one them is updated without the
+ * other. There is however no code that has a hard dependency on this check. So if there comes
+ * a platform at some point, which has a Flashmap which doesn't cover the whole flash, we can
+ * remove the check again. */
+#if FMAP_SECTION_FLASH_SIZE != CONFIG_ROM_SIZE
+	#error "ROM_SIZE must always be equal to FMAP flash size"
+#endif
+
 /* Return the name of the boot region. Falls back to COREBOOT, if not overridden
  * by any multi-slot mechanism (e.g Intel Top Swap, vboot). */
 const char *cbfs_fmap_region_hint(void);
diff --git a/tests/Makefile.common b/tests/Makefile.common
index cfb6fe945e..085e4cffc4 100644
--- a/tests/Makefile.common
+++ b/tests/Makefile.common
@@ -18,7 +18,7 @@ CMAKE := cmake
 OBJCOPY ?= objcopy
 OBJDUMP ?= objdump
 
-TEST_DEFAULT_CONFIG ?= $(top)/configs/config.emulation_qemu_x86_i440fx
+TEST_DEFAULT_CONFIG ?= $(top)/configs/config.google_octopus_spi_flash_console
 TEST_DOTCONFIG := $(testobj)/.config
 TEST_KCONFIG_AUTOHEADER := $(testobj)/config.src.h
 TEST_KCONFIG_AUTOCONFIG := $(testobj)/auto.conf
diff --git a/tests/include/tests/lib/fmap_config.h b/tests/include/tests/lib/fmap_config.h
index 5b3540020b..690ee19fca 100644
--- a/tests/include/tests/lib/fmap_config.h
+++ b/tests/include/tests/lib/fmap_config.h
@@ -8,5 +8,6 @@
  * Keeps the build tests from failing since fmap.h needs fmap_config.h
  */
 #define FMAP_SECTION_FLASH_START 0
+#define FMAP_SECTION_FLASH_SIZE 0x1000000
 
 #endif

From 6127a1d19dc6fe61395f0acfefe75173e3cbda14 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Micha=C5=82=20=C5=BBygowski?= <michal.zygowski@3mdeb.com>
Date: Tue, 16 Sep 2025 08:20:15 +0200
Subject: [PATCH 3118/3886] amdblock/lpc: Add SoC hook to set up SPI TPM
 decoding
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Some SoCs may require additional programming to get the SPI TPM
work properly. This hook is especially needed if mainboard selects
TPM_MEASURED_BOOT_INIT_BOOTBLOCK and TPM is initialized before any
vendor silicon initialization code runs (FSP or OpenSIL).

Change-Id: I90dbcbfb554ac3cfbcf23d708c3440d27959c632
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89191
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
---
 src/soc/amd/common/block/include/amdblocks/lpc.h | 1 +
 src/soc/amd/common/block/lpc/lpc_util.c          | 4 ++++
 2 files changed, 5 insertions(+)

diff --git a/src/soc/amd/common/block/include/amdblocks/lpc.h b/src/soc/amd/common/block/include/amdblocks/lpc.h
index f85c4676cc..1106e3483a 100644
--- a/src/soc/amd/common/block/include/amdblocks/lpc.h
+++ b/src/soc/amd/common/block/include/amdblocks/lpc.h
@@ -140,6 +140,7 @@ void lpc_enable_sio_decode(const bool addr);
 uintptr_t lpc_spibase(void);
 void lpc_tpm_decode(void);
 void lpc_tpm_decode_spi(void);
+void soc_lpc_tpm_decode_spi(void);
 void lpc_enable_rom(void);
 void lpc_enable_spi_prefetch(void);
 uint32_t lpc_get_rom2_region(size_t *bios_size);
diff --git a/src/soc/amd/common/block/lpc/lpc_util.c b/src/soc/amd/common/block/lpc/lpc_util.c
index b796f3faa4..d41ce0cff1 100644
--- a/src/soc/amd/common/block/lpc/lpc_util.c
+++ b/src/soc/amd/common/block/lpc/lpc_util.c
@@ -220,6 +220,8 @@ void lpc_tpm_decode(void)
 	pci_write_config32(_LPCB_DEV, LPC_TRUSTED_PLATFORM_MODULE, value);
 }
 
+void __weak soc_lpc_tpm_decode_spi(void) { }
+
 /*
  * Enable FCH to decode TPM associated Memory and IO regions to SPI
  *
@@ -236,6 +238,8 @@ void lpc_tpm_decode_spi(void)
 					SPI_BASE_ADDRESS_REGISTER);
 	pci_write_config32(_LPCB_DEV, SPI_BASE_ADDRESS_REGISTER, spibase
 					| ROUTE_TPM_2_SPI);
+
+	soc_lpc_tpm_decode_spi();
 }
 
 /*

From c8386195e174dd1b8a3f7fdde4e579b62d8e5176 Mon Sep 17 00:00:00 2001
From: Jeremy Compostella <jeremy.compostella@intel.com>
Date: Tue, 20 Jan 2026 13:26:29 -0800
Subject: [PATCH 3119/3886] vc/intel/fsp/fsp2_0/wcl: Export TccOffsetLock UPD

This commit exposes the TccOffsetLock UPD option in the FSP-M UPD
structure for Wildcat Lake platforms. Since Panther Lake, the FSP locks
the TCC (Thermal Control Circuit) MSR by default, which can interfere
with Linux-based thermal management systems that expect to configure
this register from the operating system.

By making TccOffsetLock available to coreboot, firmware integrators can
now prevent the FSP from locking the TCC MSR, thereby allowing the OS to
manage thermal parameters as needed.

BUG=b:474002582

Change-Id: I934dec88f88179c7859c6e1a35ea22c24bcfcbde
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90839
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Pranava Y N <pranavayn@google.com>
---
 .../intel/fsp/fsp2_0/wildcatlake/FspmUpd.h    | 77 +++++++++++--------
 1 file changed, 44 insertions(+), 33 deletions(-)

diff --git a/src/vendorcode/intel/fsp/fsp2_0/wildcatlake/FspmUpd.h b/src/vendorcode/intel/fsp/fsp2_0/wildcatlake/FspmUpd.h
index 661948e325..2c5c2af641 100644
--- a/src/vendorcode/intel/fsp/fsp2_0/wildcatlake/FspmUpd.h
+++ b/src/vendorcode/intel/fsp/fsp2_0/wildcatlake/FspmUpd.h
@@ -1,6 +1,6 @@
 /** @file
 
-Copyright (c) 2025, Intel Corporation. All rights reserved.<BR>
+Copyright (c) 2026, Intel Corporation. All rights reserved.<BR>
 
 Redistribution and use in source and binary forms, with or without modification,
 are permitted provided that the following conditions are met:
@@ -2275,7 +2275,18 @@ typedef struct {
 
 /** Offset 0x07D2 - Reserved
 **/
-  UINT8                       Reserved63[98];
+  UINT8                       Reserved63[92];
+
+/** Offset 0x082E - Tcc Offset Lock
+  Tcc Offset Lock for Runtime Average Temperature Limit (RATL) to lock temperature
+  target; <b>1:Enabled </b>; 0: Disabled.
+  $EN_DIS
+**/
+  UINT8                       TccOffsetLock;
+
+/** Offset 0x082F - Reserved
+**/
+  UINT8                       Reserved64[5];
 
 /** Offset 0x0834 - SinitMemorySize
   Enable/Disable. 0: Disable, define default value of SinitMemorySize , 1: enable
@@ -2342,7 +2353,7 @@ typedef struct {
 
 /** Offset 0x086E - Reserved
 **/
-  UINT8                       Reserved64[2];
+  UINT8                       Reserved65[2];
 
 /** Offset 0x0870 - Platform Power Pmax
   PSYS PMax power, defined in 1/8 Watt increments. <b>0 - Auto</b> Specified in 1/8
@@ -2394,7 +2405,7 @@ typedef struct {
 
 /** Offset 0x08BA - Reserved
 **/
-  UINT8                       Reserved65[26];
+  UINT8                       Reserved66[26];
 
 /** Offset 0x08D4 - Icc Max limit
   Voltage Regulator Current Limit (Icc Max). This value represents the Maximum instantaneous
@@ -2406,7 +2417,7 @@ typedef struct {
 
 /** Offset 0x08E0 - Reserved
 **/
-  UINT8                      Reserved66[42];
+  UINT8                      Reserved67[42];
 
 /** Offset 0x090A - Thermal Design Current enable/disable
   Thermal Design Current enable/disable; <b>0: Disable</b>; 1: Enable. [0] for IA,
@@ -2416,7 +2427,7 @@ typedef struct {
 
 /** Offset 0x0910 - Reserved
 **/
-  UINT8                       Reserved67[6];
+  UINT8                       Reserved68[6];
 
 /** Offset 0x0916 - Disable Fast Slew Rate for Deep Package C States for VR domains
   This option needs to be configured to reduce acoustic noise during deeper C states.
@@ -2438,7 +2449,7 @@ typedef struct {
 
 /** Offset 0x0922 - Reserved
 **/
-  UINT8                       Reserved68[6];
+  UINT8                       Reserved69[6];
 
 /** Offset 0x0928 - Thermal Design Current time window
   Auto = 0 is default. Range is from 1ms to 448s. <b>0: Auto</b>. [0] for IA, [1]
@@ -2454,7 +2465,7 @@ typedef struct {
 
 /** Offset 0x0946 - Reserved
 **/
-  UINT8                       Reserved69[2];
+  UINT8                       Reserved70[2];
 
 /** Offset 0x0948 - DLVR RFI Enable
   Enable/Disable DLVR RFI frequency hopping. 0: Disable; <b>1: Enable</b>.
@@ -2474,7 +2485,7 @@ typedef struct {
 
 /** Offset 0x094B - Reserved
 **/
-  UINT8                       Reserved70[11];
+  UINT8                       Reserved71[11];
 
 /** Offset 0x0956 - VR Fast Vmode ICC Limit support
   Voltage Regulator Fast Vmode ICC Limit. A value of 400 = 100A. A value of 0 corresponds
@@ -2499,7 +2510,7 @@ typedef struct {
 
 /** Offset 0x096E - Reserved
 **/
-  UINT8                       Reserved71[28];
+  UINT8                       Reserved72[28];
 
 /** Offset 0x098A - PCH Port80 Route
   Control where the Port 80h cycles are sent, 0: LPC; 1: PCI.
@@ -2516,7 +2527,7 @@ typedef struct {
 
 /** Offset 0x098C - Reserved
 **/
-  UINT8                       Reserved72[4];
+  UINT8                       Reserved73[4];
 
 /** Offset 0x0990 - PMR Size
   Size of PMR memory buffer. 0x400000 for normal boot and 0x200000 for S3 boot
@@ -2542,7 +2553,7 @@ typedef struct {
 
 /** Offset 0x0997 - Reserved
 **/
-  UINT8                       Reserved73;
+  UINT8                       Reserved74;
 
 /** Offset 0x0998 - Base addresses for VT-d function MMIO access
   Base addresses for VT-d MMIO access per VT-d engine
@@ -2551,7 +2562,7 @@ typedef struct {
 
 /** Offset 0x09BC - Reserved
 **/
-  UINT8                       Reserved74[20];
+  UINT8                       Reserved75[20];
 
 /** Offset 0x09D0 - MMIO Size
   Size of MMIO space reserved for devices. 0(Default)=Auto, non-Zero=size in MB
@@ -2566,7 +2577,7 @@ typedef struct {
 
 /** Offset 0x09D4 - Reserved
 **/
-  UINT8                      Reserved75[36];
+  UINT8                      Reserved76[36];
 
 /** Offset 0x09F8 - Enable above 4GB MMIO resource support
   Enable/disable above 4GB MMIO resource support
@@ -2582,7 +2593,7 @@ typedef struct {
 
 /** Offset 0x09FA - Reserved
 **/
-  UINT8                       Reserved76[10];
+  UINT8                       Reserved77[10];
 
 /** Offset 0x0A04 - Enable/Disable CrashLog Device
   Enable or Disable CrashLog/Telemetry Device  0- Disable, <b>1- Enable</b>
@@ -2592,7 +2603,7 @@ typedef struct {
 
 /** Offset 0x0A08 - Reserved
 **/
-  UINT8                      Reserved77[20];
+  UINT8                      Reserved78[20];
 
 /** Offset 0x0A1C - Platform Debug Option
   Enabled Trace active: TraceHub is enabled and trace is active, blocks s0ix.\n
@@ -2609,7 +2620,7 @@ typedef struct {
 
 /** Offset 0x0A1D - Reserved
 **/
-  UINT8                       Reserved78[14];
+  UINT8                       Reserved79[14];
 
 /** Offset 0x0A2B - Program GPIOs for LFP on DDI port-A device
   0=Disabled,1(Default)=eDP, 2=MIPI DSI
@@ -2619,7 +2630,7 @@ typedef struct {
 
 /** Offset 0x0A2C - Reserved
 **/
-  UINT8                      Reserved79[2];
+  UINT8                      Reserved80[2];
 
 /** Offset 0x0A2E - Program GPIOs for LFP on DDI port-B device
   0(Default)=Disabled,1=eDP, 2=MIPI DSI
@@ -2713,7 +2724,7 @@ typedef struct {
 
 /** Offset 0x0A3D - Reserved
 **/
-  UINT8                       Reserved80[3];
+  UINT8                       Reserved81[3];
 
 /** Offset 0x0A40 - Temporary MMIO address for GMADR
   The reference code will use this as Temporary MMIO address space to access GMADR
@@ -2732,7 +2743,7 @@ typedef struct {
 
 /** Offset 0x0A50 - Reserved
 **/
-  UINT8                      Reserved81[2];
+  UINT8                      Reserved82[2];
 
 /** Offset 0x0A52 - Enable/Disable Memory Bandwidth Compression
   0=Disable, 1(Default)=Enable
@@ -2762,7 +2773,7 @@ typedef struct {
 
 /** Offset 0x0A56 - Reserved
 **/
-  UINT8                       Reserved82[2];
+  UINT8                       Reserved83[2];
 
 /** Offset 0x0A58 - Intel Graphics VBT (Video BIOS Table) Size
   Size of Internal Graphics VBT Image
@@ -2771,7 +2782,7 @@ typedef struct {
 
 /** Offset 0x0A5C - Reserved
 **/
-  UINT8                       Reserved83[4];
+  UINT8                       Reserved84[4];
 
 /** Offset 0x0A60 - Graphics Configuration Ptr
   Points to VBT
@@ -2832,7 +2843,7 @@ typedef struct {
 
 /** Offset 0x0A83 - Reserved
 **/
-  UINT8                       Reserved84[4];
+  UINT8                       Reserved85[4];
 
 /** Offset 0x0A87 - TCSS Type C Port 0
   Set TCSS Type C Port 0 Type, Options are 0=DISABLE, 1=DP_ONLY, 2=NO_TBT, 3=NO_PCIE,
@@ -2864,7 +2875,7 @@ typedef struct {
 
 /** Offset 0x0A8B - Reserved
 **/
-  UINT8                       Reserved85;
+  UINT8                       Reserved86;
 
 /** Offset 0x0A8C - TypeC port GPIO setting
   GPIO Pin number for Type C Aux orientation setting, use the GpioPad that is defined
@@ -2932,7 +2943,7 @@ typedef struct {
 
 /** Offset 0x0AC9 - Reserved
 **/
-  UINT8                       Reserved86;
+  UINT8                       Reserved87;
 
 /** Offset 0x0ACA - DLL Weak Lock Support
   Enables/Disable DLL Weak Lock Support
@@ -2942,7 +2953,7 @@ typedef struct {
 
 /** Offset 0x0ACB - Reserved
 **/
-  UINT8                       Reserved87;
+  UINT8                       Reserved88;
 
 /** Offset 0x0ACC - Rx DQS Delay Comp Support
   Enables/Disable Rx DQS Delay Comp Support
@@ -2952,7 +2963,7 @@ typedef struct {
 
 /** Offset 0x0ACD - Reserved
 **/
-  UINT8                       Reserved88[2];
+  UINT8                       Reserved89[2];
 
 /** Offset 0x0ACF - Mrc Failure On Unsupported Dimm
   Enables/Disable Mrc Failure On Unsupported Dimm
@@ -2962,7 +2973,7 @@ typedef struct {
 
 /** Offset 0x0AD0 - Reserved
 **/
-  UINT8                      Reserved89[4];
+  UINT8                      Reserved90[4];
 
 /** Offset 0x0AD4 - DynamicMemoryBoost
   Enable/Disable Dynamic Memory Boost Feature. Only valid if SpdProfileSelected is
@@ -2980,7 +2991,7 @@ typedef struct {
 
 /** Offset 0x0ADC - Reserved
 **/
-  UINT8                      Reserved90[9];
+  UINT8                      Reserved91[9];
 
 /** Offset 0x0AE5 - Vref Offset
   Offset to be applied to DDRDATACH0_CR_DDRCRDATAOFFSETTRAIN.VrefOffset
@@ -2991,7 +3002,7 @@ typedef struct {
 
 /** Offset 0x0AE6 - Reserved
 **/
-  UINT8                       Reserved91[2];
+  UINT8                       Reserved92[2];
 
 /** Offset 0x0AE8 - tRRSG Delta
   Delay between Read-to-Read commands in the same Bank Group. 0 - Auto. Signed TAT
@@ -3107,7 +3118,7 @@ typedef struct {
 
 /** Offset 0x0AF8 - Reserved
 **/
-  UINT8                       Reserved92[41];
+  UINT8                       Reserved93[41];
 
 /** Offset 0x0B21 - Channel to CKD QCK Mapping
   Specify Channel to CKD QCK Mapping for CH0D0/CH0D1/CH1D0&CH1D1
@@ -3121,7 +3132,7 @@ typedef struct {
 
 /** Offset 0x0B31 - Reserved
 **/
-  UINT8                       Reserved93[17];
+  UINT8                       Reserved94[17];
 
 /** Offset 0x0B42 - VDD2 Voltage
   Voltage is multiple of 5mV where 0 means Auto.
@@ -3145,7 +3156,7 @@ typedef struct {
 
 /** Offset 0x0B4A - Reserved
 **/
-  UINT8                       Reserved94[30];
+  UINT8                       Reserved95[30];
 } FSP_M_CONFIG;
 
 /** Fsp M UPD Configuration

From c852840f11871a5bf8e42be6df79db9fa02a376b Mon Sep 17 00:00:00 2001
From: Jeremy Compostella <jeremy.compostella@intel.com>
Date: Fri, 9 Jan 2026 08:07:27 -0800
Subject: [PATCH 3120/3886] soc/intel/pantherlake: Disable TCC MSR lock in FSP

Since Panther Lake, the FSP locks the TCC (Thermal Control Circuit) MSR
by default. However, Linux-based thermal management systems typically
configure this register from the operating system rather than the
firmware. Locking the TCC MSR in firmware prevents the OS from adjusting
thermal parameters as needed, potentially impacting system thermal
management and flexibility.

This commit explicitly sets the TccOffsetLock field to 0 in the FSP-M
configuration, ensuring that the TCC MSR remains unlocked after firmware
initialization.

BUG=b:474002582
TEST=MSR 0x1A2 is writable from the OS, as indicated by the successful
     operation of
     /sys/bus/pci/devices/0000:00:04/tcc_offset_degree_celsius on a
     Fatcat device.

Change-Id: I445bc1408018d3de82919e46c8a368d93bbb1a77
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90718
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
Reviewed-by: Guvendik, Bora <bora.guvendik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Pranava Y N <pranavayn@google.com>
---
 src/soc/intel/pantherlake/romstage/fsp_params.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/src/soc/intel/pantherlake/romstage/fsp_params.c b/src/soc/intel/pantherlake/romstage/fsp_params.c
index 5ec92bb80f..d6f628b36a 100644
--- a/src/soc/intel/pantherlake/romstage/fsp_params.c
+++ b/src/soc/intel/pantherlake/romstage/fsp_params.c
@@ -313,6 +313,7 @@ static void fill_fspm_thermal_params(FSP_M_CONFIG *m_cfg,
 				     const struct soc_intel_pantherlake_config *config)
 {
 	m_cfg->TccActivationOffset = config->tcc_offset;
+	m_cfg->TccOffsetLock = 0;
 }
 
 static const struct soc_intel_pantherlake_power_map *get_map(const struct soc_intel_pantherlake_config *config)

From df44756c8a9a6b9d476729f15965eebd3921678b Mon Sep 17 00:00:00 2001
From: "P, Usha" <usha.p@intel.com>
Date: Fri, 26 Sep 2025 13:49:39 +0530
Subject: [PATCH 3121/3886] mb/google/ocelot: Disable EC software sync for
 Microchip EC

This patch disables EC software sync specifically for the Microchip EC
on the ocelot board. This change selects
`GBB_FLAG_DISABLE_EC_SOFTWARE_SYNC` for boards w/ microchip EC
(EC_GOOGLE_CHROMEEC_MEC) like ocelot.

This allows other ocelot variants (Nuvoton, ITE EC AIC) to potentially
enable EC software sync, which is not compatible with the Microchip EC.

TEST= Verified EC software sync functionality on a Nuvoton AIC ocelot
variant.
Change-Id: Ibcd6b0231a5390a9843419da86acee54811ec3d7
Signed-off-by: P, Usha <usha.p@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89357
Reviewed-by: Pranava Y N <pranavayn@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Avi Uday <aviuday@google.com>
---
 src/mainboard/google/ocelot/Kconfig | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/mainboard/google/ocelot/Kconfig b/src/mainboard/google/ocelot/Kconfig
index d2a2e189e4..b20ef17289 100644
--- a/src/mainboard/google/ocelot/Kconfig
+++ b/src/mainboard/google/ocelot/Kconfig
@@ -145,7 +145,7 @@ config BASEBOARD_DIR
 
 config CHROMEOS
 	select EC_GOOGLE_CHROMEEC_SWITCHES
-	select GBB_FLAG_DISABLE_EC_SOFTWARE_SYNC
+	select GBB_FLAG_DISABLE_EC_SOFTWARE_SYNC if EC_GOOGLE_CHROMEEC_MEC
 	select GBB_FLAG_FORCE_DEV_BOOT_USB
 	select GBB_FLAG_FORCE_MANUAL_RECOVERY
 	select HAS_RECOVERY_MRC_CACHE

From cd8e9cd717ccac68adf7eaeee446c87179f6f511 Mon Sep 17 00:00:00 2001
From: Alicja Michalska <alicja.michalska@9elements.com>
Date: Wed, 21 Jan 2026 18:05:10 +0100
Subject: [PATCH 3122/3886] soc/intel/pantherlake: Allow access to eSPI 4e
 address in bootblock

Some Intel development boards have SuperIO located at address 4e instead
of "default" 2e.

In order to correctly initialize the SIO/EC, we need to allow access to
that address in bootblock.
For further information refer to #854345 (Intel CNDA).

TEST: Build/boot intel/pantherlake_crb (out-of-tree, pending clearance).
Make sure that RS232 is working and SIO ACPI tables are correct.

Change-Id: I7944a48738fe0146cdf94635a01153a5d2331b24
Signed-off-by: Alicja Michalska <alicja.michalska@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90854
Reviewed-by: Pranava Y N <pranavayn@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
---
 src/soc/intel/pantherlake/bootblock/pcd.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/soc/intel/pantherlake/bootblock/pcd.c b/src/soc/intel/pantherlake/bootblock/pcd.c
index 50e6ebd73d..bd87dfa82a 100644
--- a/src/soc/intel/pantherlake/bootblock/pcd.c
+++ b/src/soc/intel/pantherlake/bootblock/pcd.c
@@ -48,8 +48,8 @@ static void pcd_die_config_pwrmbase(void)
 
 static void pcd_die_early_iorange_init(void)
 {
-	uint16_t io_enables = LPC_IOE_SUPERIO_2E_2F | LPC_IOE_KBC_60_64 |
-		LPC_IOE_EC_62_66 | LPC_IOE_LGE_200;
+	uint16_t io_enables = LPC_IOE_SUPERIO_2E_2F | LPC_IOE_EC_4E_4F |
+		LPC_IOE_KBC_60_64 | LPC_IOE_EC_62_66 | LPC_IOE_LGE_200;
 
 	/* IO Decode Range */
 	if (CONFIG(DRIVERS_UART_8250IO))

From d19cb011294d33cf06d5fe508ff186d0dee97af0 Mon Sep 17 00:00:00 2001
From: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
Date: Wed, 21 Jan 2026 14:46:37 +0800
Subject: [PATCH 3123/3886] mb/google/fatcat/moonstone: Remove RTD3 config for
 SSD

The Moonstone hardware design does not have a power load switch for
the SSD. Without it, the platform cannot cut off the main power rail
to the device to enter D3cold.
Therefore, remove the RTD3 chip driver and its associated GPIO
configurations (enable/reset) in the overridetree to align with the
hardware capability. The system will support D3hot instead of D3cold.

BUG=460038237
TEST=Build and boot to OS on Moonstone, verify SSD still functions
correctly and power state transitions align with HW design.

Change-Id: I8fd12d2f629977f939d11f26aef21552a947c5e3
Signed-off-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90841
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Pranava Y N <pranavayn@google.com>
---
 .../google/fatcat/variants/moonstone/overridetree.cb       | 7 -------
 1 file changed, 7 deletions(-)

diff --git a/src/mainboard/google/fatcat/variants/moonstone/overridetree.cb b/src/mainboard/google/fatcat/variants/moonstone/overridetree.cb
index 17d461248c..16847cc41f 100644
--- a/src/mainboard/google/fatcat/variants/moonstone/overridetree.cb
+++ b/src/mainboard/google/fatcat/variants/moonstone/overridetree.cb
@@ -390,13 +390,6 @@ chip soc/intel/pantherlake
 			.clk_req = 1,
 			.flags = PCIE_RP_CLK_REQ_DETECT | PCIE_RP_LTR | PCIE_RP_AER,
 			}"
-			chip soc/intel/common/block/pcie/rtd3
-				register "is_storage" = "true"
-				register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B16)"
-				register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_E03)"
-				register "srcclk_pin" = "1"
-				device generic 0 on end
-			end
 		end # Gen5 M.2 SSD
 		device ref cnvi_wifi on
 			chip drivers/wifi/generic

From f650bf95ab1f2171ef8a53802876b2afa91f878f Mon Sep 17 00:00:00 2001
From: Bora Guvendik <bora.guvendik@intel.com>
Date: Tue, 13 Jan 2026 12:28:25 -0800
Subject: [PATCH 3124/3886] soc/intel: Add Nova Lake device IDs

This patch adds Nova Lake specific device IDs to the header files and
driver-specific code.

Note: Device IDs D750h - D75Fh are intentionally omitted and will be
added in a future patch once validation is complete.

Reference:
- Nova Lake External Design Specification (EDS) Volume 1 (#844316)

BUG=none

Change-Id: I00900c4f796b8bcc40f2bc09917172c71039c8a6
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90748
Reviewed-by: Kim, Wonkyu <wonkyu.kim@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/drivers/intel/ish/ish.c                   |   1 +
 src/drivers/intel/touch/touch.c               |   4 +
 src/include/device/pci_ids.h                  | 104 ++++++++++++++++++
 src/soc/intel/common/block/cnvi/cnvi.c        |   5 +
 src/soc/intel/common/block/cse/cse.c          |   1 +
 src/soc/intel/common/block/dsp/dsp.c          |   8 ++
 .../intel/common/block/graphics/graphics.c    |   5 +
 src/soc/intel/common/block/hda/hda.c          |   8 ++
 src/soc/intel/common/block/i2c/i2c.c          |   6 +
 src/soc/intel/common/block/ipu/ipu.c          |   1 +
 src/soc/intel/common/block/lpc/lpc.c          |  32 ++++++
 src/soc/intel/common/block/p2sb/p2sb.c        |   1 +
 src/soc/intel/common/block/p2sb/p2sb2.c       |   1 +
 src/soc/intel/common/block/pcie/pcie.c        |  14 +++
 src/soc/intel/common/block/pmc/pmc.c          |   1 +
 src/soc/intel/common/block/spi/spi.c          |   4 +
 src/soc/intel/common/block/sram/sram.c        |   2 +
 .../common/block/systemagent/systemagent.c    |   5 +
 .../intel/common/block/tracehub/tracehub.c    |   1 +
 src/soc/intel/common/block/uart/uart.c        |   6 +
 src/soc/intel/common/block/usb4/usb4.c        |   1 +
 src/soc/intel/common/block/usb4/xhci.c        |   1 +
 src/soc/intel/common/block/xdci/xdci.c        |   1 +
 src/soc/intel/common/block/xhci/xhci.c        |   1 +
 24 files changed, 214 insertions(+)

diff --git a/src/drivers/intel/ish/ish.c b/src/drivers/intel/ish/ish.c
index 9cf6b7c0e5..fc153fba3a 100644
--- a/src/drivers/intel/ish/ish.c
+++ b/src/drivers/intel/ish/ish.c
@@ -85,6 +85,7 @@ static const struct device_operations pci_ish_device_ops = {
 };
 
 static const unsigned short pci_device_ids[] = {
+	PCI_DID_INTEL_NVL_ISHB,
 	PCI_DID_INTEL_WCL_ISHB,
 	PCI_DID_INTEL_PTL_H_ISHB,
 	PCI_DID_INTEL_PTL_U_H_ISHB,
diff --git a/src/drivers/intel/touch/touch.c b/src/drivers/intel/touch/touch.c
index 03738741b8..0d27ca3936 100644
--- a/src/drivers/intel/touch/touch.c
+++ b/src/drivers/intel/touch/touch.c
@@ -626,6 +626,10 @@ static const struct device_operations pci_thc_device_ops = {
 };
 
 static const unsigned short pci_device_ids[] = {
+	PCI_DID_INTEL_NVL_THC0_1,
+	PCI_DID_INTEL_NVL_THC0_2,
+	PCI_DID_INTEL_NVL_THC1_1,
+	PCI_DID_INTEL_NVL_THC1_2,
 	PCI_DID_INTEL_MTL_THC0_SPI,
 	PCI_DID_INTEL_MTL_THC1_SPI,
 	PCI_DID_INTEL_PTL_U_H_THC0_I2C,
diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h
index a3c3e58056..ed3ba38d99 100644
--- a/src/include/device/pci_ids.h
+++ b/src/include/device/pci_ids.h
@@ -2190,6 +2190,7 @@
 #define PCI_DID_INTEL_PTL_H_ISHB	0xe445
 #define PCI_DID_INTEL_PTL_U_H_ISHB	0xe345
 #define PCI_DID_INTEL_WCL_ISHB		0x4d45
+#define PCI_DID_INTEL_NVL_ISHB		0xd354
 
 /* Intel 82371FB (PIIX) */
 #define PCI_DID_INTEL_82371FB_ISA		0x122e
@@ -3349,6 +3350,38 @@
 #define PCI_DID_INTEL_WCL_ESPI_29			0x4d1d
 #define PCI_DID_INTEL_WCL_ESPI_30			0x4d1e
 #define PCI_DID_INTEL_WCL_ESPI_31			0x4d1f
+#define PCI_DID_INTEL_NVL_ESPI_0			0xd300
+#define PCI_DID_INTEL_NVL_ESPI_1			0xd301
+#define PCI_DID_INTEL_NVL_ESPI_2			0xd302
+#define PCI_DID_INTEL_NVL_ESPI_3			0xd303
+#define PCI_DID_INTEL_NVL_ESPI_4			0xd304
+#define PCI_DID_INTEL_NVL_ESPI_5			0xd305
+#define PCI_DID_INTEL_NVL_ESPI_6			0xd306
+#define PCI_DID_INTEL_NVL_ESPI_7			0xd307
+#define PCI_DID_INTEL_NVL_ESPI_8			0xd308
+#define PCI_DID_INTEL_NVL_ESPI_9			0xd309
+#define PCI_DID_INTEL_NVL_ESPI_10			0xd30a
+#define PCI_DID_INTEL_NVL_ESPI_11			0xd30b
+#define PCI_DID_INTEL_NVL_ESPI_12			0xd30c
+#define PCI_DID_INTEL_NVL_ESPI_13			0xd30d
+#define PCI_DID_INTEL_NVL_ESPI_14			0xd30e
+#define PCI_DID_INTEL_NVL_ESPI_15			0xd30f
+#define PCI_DID_INTEL_NVL_ESPI_16			0xd310
+#define PCI_DID_INTEL_NVL_ESPI_17			0xd311
+#define PCI_DID_INTEL_NVL_ESPI_18			0xd312
+#define PCI_DID_INTEL_NVL_ESPI_19			0xd313
+#define PCI_DID_INTEL_NVL_ESPI_20			0xd314
+#define PCI_DID_INTEL_NVL_ESPI_21			0xd315
+#define PCI_DID_INTEL_NVL_ESPI_22			0xd316
+#define PCI_DID_INTEL_NVL_ESPI_23			0xd317
+#define PCI_DID_INTEL_NVL_ESPI_24			0xd318
+#define PCI_DID_INTEL_NVL_ESPI_25			0xd319
+#define PCI_DID_INTEL_NVL_ESPI_26			0xd31a
+#define PCI_DID_INTEL_NVL_ESPI_27			0xd31b
+#define PCI_DID_INTEL_NVL_ESPI_28			0xd31c
+#define PCI_DID_INTEL_NVL_ESPI_29			0xd31d
+#define PCI_DID_INTEL_NVL_ESPI_30			0xd31e
+#define PCI_DID_INTEL_NVL_ESPI_31			0xd31f
 
 /* Intel PCIE device ids  */
 #define PCI_DID_INTEL_LPT_H_PCIE_RP1			0x8c10
@@ -3829,6 +3862,21 @@
 #define PCI_DID_INTEL_WCL_PCIE_RP5                      0x4d61
 #define PCI_DID_INTEL_WCL_PCIE_RP6                      0x4d5c
 
+#define PCI_DID_INTEL_NVL_PCIE_RP1			0xd338
+#define PCI_DID_INTEL_NVL_PCIE_RP2			0xd339
+#define PCI_DID_INTEL_NVL_PCIE_RP3			0xd33a
+#define PCI_DID_INTEL_NVL_PCIE_RP4			0xd33b
+#define PCI_DID_INTEL_NVL_PCIE_RP5			0xd33c
+#define PCI_DID_INTEL_NVL_PCIE_RP6			0xd33d
+#define PCI_DID_INTEL_NVL_PCIE_RP7			0xd33e
+#define PCI_DID_INTEL_NVL_PCIE_RP8			0xd33f
+#define PCI_DID_INTEL_NVL_PCIE_RP9			0xd361
+#define PCI_DID_INTEL_NVL_PCIE_RP10			0xd35c
+#define PCI_DID_INTEL_NVL_PCIE_RP11			0xd365
+#define PCI_DID_INTEL_NVL_PCIE_RP12			0xd366
+#define PCI_DID_INTEL_NVL_PCIE_RP13			0xd367
+#define PCI_DID_INTEL_NVL_PCIE_RP14			0xd368
+
 /* Intel SATA device Ids */
 #define PCI_DID_INTEL_LPT_H_DESKTOP_SATA_IDE			0x8c00
 #define PCI_DID_INTEL_LPT_H_DESKTOP_SATA_AHCI			0x8c02
@@ -3954,6 +4002,7 @@
 #define PCI_DID_INTEL_PTL_H_PMC			0xe421
 #define PCI_DID_INTEL_PTL_U_H_PMC		0xe321
 #define PCI_DID_INTEL_WCL_PMC			0x4d21
+#define PCI_DID_INTEL_NVL_PMC			0xd321
 
 /* Intel I2C device Ids */
 #define PCI_DID_INTEL_LPT_LP_I2C0		0x9c61
@@ -4119,6 +4168,13 @@
 #define PCI_DID_INTEL_WCL_I2C4			0x4d50
 #define PCI_DID_INTEL_WCL_I2C5			0x4d51
 
+#define PCI_DID_INTEL_NVL_I2C0			0xd378
+#define PCI_DID_INTEL_NVL_I2C1			0xd379
+#define PCI_DID_INTEL_NVL_I2C2			0xd37a
+#define PCI_DID_INTEL_NVL_I2C3			0xd37b
+#define PCI_DID_INTEL_NVL_I2C4			0xd350
+#define PCI_DID_INTEL_NVL_I2C5			0xd351
+
 /* Intel UART device Ids */
 #define PCI_DID_INTEL_LPT_LP_UART0		0x9c63
 #define PCI_DID_INTEL_LPT_LP_UART1		0x9c64
@@ -4222,6 +4278,10 @@
 #define PCI_DID_INTEL_WCL_UART1			0x4d26
 #define PCI_DID_INTEL_WCL_UART2			0x4d52
 
+#define PCI_DID_INTEL_NVL_UART0			0xd325
+#define PCI_DID_INTEL_NVL_UART1			0xd326
+#define PCI_DID_INTEL_NVL_UART2			0xd352
+
 /* Intel SPI device Ids */
 #define PCI_DID_INTEL_LPT_LP_GSPI0		0x9c65
 #define PCI_DID_INTEL_LPT_LP_GSPI1		0x9c66
@@ -4349,6 +4409,11 @@
 #define PCI_DID_INTEL_WCL_SPI1			0x4d30
 #define PCI_DID_INTEL_WCL_SPI2			0x4d46
 
+#define PCI_DID_INTEL_NVL_HWSEQ_SPI		0xd323
+#define PCI_DID_INTEL_NVL_SPI0			0xd327
+#define PCI_DID_INTEL_NVL_SPI1			0xd330
+#define PCI_DID_INTEL_NVL_SPI2			0xd347
+
 /* Intel IGD device Ids */
 #define PCI_DID_INTEL_SKL_GT1F_DT2			0x1902
 #define PCI_DID_INTEL_SKL_GT1_SULTM			0x1906
@@ -4522,6 +4587,11 @@
 #define PCI_DID_INTEL_PTL_H_GT2_4			0xb08f
 #define PCI_DID_INTEL_WCL_GT2_1				0xfd80
 #define PCI_DID_INTEL_WCL_GT2_2				0xfd81
+#define PCI_DID_INTEL_NVL_GT2_1				0xd741
+#define PCI_DID_INTEL_NVL_GT2_2				0xd742
+#define PCI_DID_INTEL_NVL_GT2_3				0xd743
+#define PCI_DID_INTEL_NVL_GT2_4				0xd744
+#define PCI_DID_INTEL_NVL_GT2_5				0xd745
 
 /* Intel Northbridge Ids */
 #define PCI_DID_INTEL_APL_NB			0x5af0
@@ -4691,6 +4761,11 @@
 #define PCI_DID_INTEL_WCL_ID_3			0xfd02
 #define PCI_DID_INTEL_WCL_ID_4			0xfd03
 #define PCI_DID_INTEL_WCL_ID_5			0xfd04
+#define PCI_DID_INTEL_NVL_ID_1			0xd701
+#define PCI_DID_INTEL_NVL_ID_2			0xd702
+#define PCI_DID_INTEL_NVL_ID_3			0xd704
+#define PCI_DID_INTEL_NVL_ID_4			0xd705
+#define PCI_DID_INTEL_NVL_ID_5			0xd70e
 
 /* Intel SMBUS device Ids */
 #define PCI_DID_INTEL_LPT_H_SMBUS			0x8c22
@@ -4777,6 +4852,8 @@
 #define PCI_DID_INTEL_SNR_XHCI			0x18d0
 #define PCI_DID_INTEL_WCL_XHCI			0x4d7d
 #define PCI_DID_INTEL_WCL_TCSS_XHCI		0x4d31
+#define PCI_DID_INTEL_NVL_XHCI			0xd37d
+#define PCI_DID_INTEL_NVL_TCSS_XHCI		0xd331
 
 /* Intel P2SB device Ids */
 #define PCI_DID_INTEL_APL_P2SB			0x5a92
@@ -4815,6 +4892,8 @@
 #define PCI_DID_INTEL_SNR_P2SB			0x18dd
 #define PCI_DID_INTEL_WCL_P2SB			0x4d20
 #define PCI_DID_INTEL_WCL_P2SB2			0x4d4c
+#define PCI_DID_INTEL_NVL_P2SB			0xd320
+#define PCI_DID_INTEL_NVL_P2SB2			0xd34c
 
 /* Intel SRAM device Ids */
 #define PCI_DID_INTEL_APL_SRAM			0x5aec
@@ -4836,6 +4915,7 @@
 #define PCI_DID_INTEL_PTL_H_SRAM		0xe47f
 #define PCI_DID_INTEL_PTL_U_H_SRAM		0xe37f
 #define PCI_DID_INTEL_WCL_SRAM			0x4d7f
+#define PCI_DID_INTEL_NVL_SRAM			0xd37e
 
 /* Intel AUDIO device Ids */
 #define PCI_DID_INTEL_LPT_H_AUDIO		0x8c20
@@ -4932,6 +5012,15 @@
 #define PCI_DID_INTEL_WCL_AUDIO_7		0x4d2e
 #define PCI_DID_INTEL_WCL_AUDIO_8		0x4d2f
 
+#define PCI_DID_INTEL_NVL_AUDIO_1		0xd328
+#define PCI_DID_INTEL_NVL_AUDIO_2		0xd329
+#define PCI_DID_INTEL_NVL_AUDIO_3		0xd32a
+#define PCI_DID_INTEL_NVL_AUDIO_4		0xd32b
+#define PCI_DID_INTEL_NVL_AUDIO_5		0xd32c
+#define PCI_DID_INTEL_NVL_AUDIO_6		0xd32d
+#define PCI_DID_INTEL_NVL_AUDIO_7		0xd32e
+#define PCI_DID_INTEL_NVL_AUDIO_8		0xd32f
+
 /* Intel HECI/ME device Ids */
 #define PCI_DID_INTEL_LPT_H_MEI			0x8c3a
 #define PCI_DID_INTEL_LPT_H_MEI_9		0x8cba
@@ -4989,6 +5078,7 @@
 #define PCI_DID_INTEL_PTL_U_H_CSE0		0xe370
 #define PCI_DID_INTEL_SNR_HECI1			0x18d3
 #define PCI_DID_INTEL_WCL_CSE0			0x4d70
+#define PCI_DID_INTEL_NVL_CSE0			0xd370
 
 /* Intel XDCI device Ids */
 #define PCI_DID_INTEL_APL_XDCI			0x5aaa
@@ -5017,6 +5107,7 @@
 #define PCI_DID_INTEL_PTL_H_XDCI		0xe47e
 #define PCI_DID_INTEL_PTL_U_H_XDCI		0xe37e
 #define PCI_DID_INTEL_WCL_XDCI		0x4d7e
+#define PCI_DID_INTEL_NVL_XDCI			0xd37f
 
 /* Intel SD device Ids */
 #define PCI_DID_INTEL_LPT_LP_SD			0x9c35
@@ -5078,6 +5169,7 @@
 #define PCI_DID_INTEL_PTL_TBT_DMA0		0xe433
 #define PCI_DID_INTEL_PTL_TBT_DMA1		0xe434
 #define PCI_DID_INTEL_WCL_TBT_DMA0		0x4d33
+#define PCI_DID_INTEL_NVL_TBT_DMA0		0xd333
 
 /* Intel WIFI Ids */
 #define PCI_DID_1000_SERIES_WIFI		0x0084
@@ -5120,6 +5212,7 @@
 #define PCI_DID_INTEL_RPL_IPU			0xa75d
 #define PCI_DID_INTEL_LNL_IPU			0x645d
 #define PCI_DID_INTEL_PTL_IPU			0xb05d
+#define PCI_DID_INTEL_NVL_IPU			0xd719
 
 /* Intel Dynamic Tuning Technology Device */
 #define PCI_DID_INTEL_CML_DTT			0x1903
@@ -5199,6 +5292,11 @@
 #define PCI_DID_INTEL_WCL_CNVI_WIFI_2		0x4d42
 #define PCI_DID_INTEL_WCL_CNVI_WIFI_3		0x4d43
 #define PCI_DID_INTEL_WCL_CNVI_BT		0x4d76
+#define PCI_DID_INTEL_NVL_CNVI_WIFI_0		0xd340
+#define PCI_DID_INTEL_NVL_CNVI_WIFI_1		0xd341
+#define PCI_DID_INTEL_NVL_CNVI_WIFI_2		0xd342
+#define PCI_DID_INTEL_NVL_CNVI_WIFI_3		0xd343
+#define PCI_DID_INTEL_NVL_CNVI_BT		0xd346
 
 /* Platform Security Engine */
 #define PCI_DID_INTEL_LNL_PSE0			0xa862
@@ -5224,6 +5322,7 @@
 #define PCI_DID_INTEL_RPP_S_PMC_CRASHLOG_SRAM		0x7a27
 #define PCI_DID_INTEL_PTL_PUNIT_CRASHLOG_SRAM		0xb07d
 #define PCI_DID_INTEL_WCL_PUNIT_CRASHLOG_SRAM		0xfd7d
+#define PCI_DID_INTEL_NVL_PUNIT_CRASHLOG_SRAM		0xd70d
 
 /* Intel Trace Hub */
 #define PCI_DID_INTEL_MTL_TRACEHUB			0x7e24
@@ -5234,6 +5333,7 @@
 #define PCI_DID_INTEL_PTL_H_TRACEHUB			0xe424
 #define PCI_DID_INTEL_PTL_U_H_TRACEHUB			0xe324
 #define PCI_DID_INTEL_WCL_TRACEHUB			0x4d24
+#define PCI_DID_INTEL_NVL_TRACEHUB			0xd324
 
 /* Intel Ethernet Controller device Ids */
 #define PCI_DID_INTEL_EHL_GBE_HOST		0x4B32
@@ -5265,6 +5365,10 @@
 #define PCI_DID_INTEL_ARP_S_THC0_2	0x7f59
 #define PCI_DID_INTEL_ARP_S_THC1_1	0x7f5a
 #define PCI_DID_INTEL_ARP_S_THC1_2	0x7f5b
+#define PCI_DID_INTEL_NVL_THC0_1	0xd348
+#define PCI_DID_INTEL_NVL_THC0_2	0xd349
+#define PCI_DID_INTEL_NVL_THC1_1	0xd34a
+#define PCI_DID_INTEL_NVL_THC1_2	0xd34b
 
 #define PCI_VID_COMPUTONE		0x8e0e
 #define PCI_DID_COMPUTONE_IP2EX		0x0291
diff --git a/src/soc/intel/common/block/cnvi/cnvi.c b/src/soc/intel/common/block/cnvi/cnvi.c
index 80fed3a23d..0511fd20c0 100644
--- a/src/soc/intel/common/block/cnvi/cnvi.c
+++ b/src/soc/intel/common/block/cnvi/cnvi.c
@@ -473,6 +473,10 @@ static struct device_operations cnvi_wifi_ops = {
 };
 
 static const unsigned short wifi_pci_device_ids[] = {
+	PCI_DID_INTEL_NVL_CNVI_WIFI_0,
+	PCI_DID_INTEL_NVL_CNVI_WIFI_1,
+	PCI_DID_INTEL_NVL_CNVI_WIFI_2,
+	PCI_DID_INTEL_NVL_CNVI_WIFI_3,
 	PCI_DID_INTEL_WCL_CNVI_WIFI_0,
 	PCI_DID_INTEL_WCL_CNVI_WIFI_1,
 	PCI_DID_INTEL_WCL_CNVI_WIFI_2,
@@ -858,6 +862,7 @@ static struct device_operations cnvi_bt_ops = {
 };
 
 static const unsigned short bt_pci_device_ids[] = {
+	PCI_DID_INTEL_NVL_CNVI_BT,
 	PCI_DID_INTEL_WCL_CNVI_BT,
 	PCI_DID_INTEL_PTL_H_CNVI_BT,
 	PCI_DID_INTEL_PTL_U_H_CNVI_BT,
diff --git a/src/soc/intel/common/block/cse/cse.c b/src/soc/intel/common/block/cse/cse.c
index d02bb85b37..d60b9b5195 100644
--- a/src/soc/intel/common/block/cse/cse.c
+++ b/src/soc/intel/common/block/cse/cse.c
@@ -1527,6 +1527,7 @@ struct device_operations cse_ops = {
 };
 
 static const unsigned short pci_device_ids[] = {
+	PCI_DID_INTEL_NVL_CSE0,
 	PCI_DID_INTEL_WCL_CSE0,
 	PCI_DID_INTEL_PTL_H_CSE0,
 	PCI_DID_INTEL_PTL_U_H_CSE0,
diff --git a/src/soc/intel/common/block/dsp/dsp.c b/src/soc/intel/common/block/dsp/dsp.c
index 9155a2a7b7..6656042674 100644
--- a/src/soc/intel/common/block/dsp/dsp.c
+++ b/src/soc/intel/common/block/dsp/dsp.c
@@ -14,6 +14,14 @@ static struct device_operations dsp_dev_ops = {
 };
 
 static const unsigned short pci_device_ids[] = {
+	PCI_DID_INTEL_NVL_AUDIO_1,
+	PCI_DID_INTEL_NVL_AUDIO_2,
+	PCI_DID_INTEL_NVL_AUDIO_3,
+	PCI_DID_INTEL_NVL_AUDIO_4,
+	PCI_DID_INTEL_NVL_AUDIO_5,
+	PCI_DID_INTEL_NVL_AUDIO_6,
+	PCI_DID_INTEL_NVL_AUDIO_7,
+	PCI_DID_INTEL_NVL_AUDIO_8,
 	PCI_DID_INTEL_WCL_AUDIO_1,
 	PCI_DID_INTEL_WCL_AUDIO_2,
 	PCI_DID_INTEL_WCL_AUDIO_3,
diff --git a/src/soc/intel/common/block/graphics/graphics.c b/src/soc/intel/common/block/graphics/graphics.c
index 12f29b567b..14893869a0 100644
--- a/src/soc/intel/common/block/graphics/graphics.c
+++ b/src/soc/intel/common/block/graphics/graphics.c
@@ -361,6 +361,11 @@ const struct device_operations graphics_ops = {
 };
 
 static const unsigned short pci_device_ids[] = {
+	PCI_DID_INTEL_NVL_GT2_1,
+	PCI_DID_INTEL_NVL_GT2_2,
+	PCI_DID_INTEL_NVL_GT2_3,
+	PCI_DID_INTEL_NVL_GT2_4,
+	PCI_DID_INTEL_NVL_GT2_5,
 	PCI_DID_INTEL_WCL_GT2_1,
 	PCI_DID_INTEL_WCL_GT2_2,
 	PCI_DID_INTEL_PTL_U_GT2_1,
diff --git a/src/soc/intel/common/block/hda/hda.c b/src/soc/intel/common/block/hda/hda.c
index f5e22bc6d9..e779dee312 100644
--- a/src/soc/intel/common/block/hda/hda.c
+++ b/src/soc/intel/common/block/hda/hda.c
@@ -30,6 +30,14 @@ struct device_operations hda_ops = {
 };
 
 static const unsigned short pci_device_ids[] = {
+	PCI_DID_INTEL_NVL_AUDIO_1,
+	PCI_DID_INTEL_NVL_AUDIO_2,
+	PCI_DID_INTEL_NVL_AUDIO_3,
+	PCI_DID_INTEL_NVL_AUDIO_4,
+	PCI_DID_INTEL_NVL_AUDIO_5,
+	PCI_DID_INTEL_NVL_AUDIO_6,
+	PCI_DID_INTEL_NVL_AUDIO_7,
+	PCI_DID_INTEL_NVL_AUDIO_8,
 	PCI_DID_INTEL_WCL_AUDIO_1,
 	PCI_DID_INTEL_WCL_AUDIO_2,
 	PCI_DID_INTEL_WCL_AUDIO_3,
diff --git a/src/soc/intel/common/block/i2c/i2c.c b/src/soc/intel/common/block/i2c/i2c.c
index 2c0e010ccb..161e61fc47 100644
--- a/src/soc/intel/common/block/i2c/i2c.c
+++ b/src/soc/intel/common/block/i2c/i2c.c
@@ -174,6 +174,12 @@ struct device_operations i2c_dev_ops = {
 };
 
 static const unsigned short pci_device_ids[] = {
+	PCI_DID_INTEL_NVL_I2C0,
+	PCI_DID_INTEL_NVL_I2C1,
+	PCI_DID_INTEL_NVL_I2C2,
+	PCI_DID_INTEL_NVL_I2C3,
+	PCI_DID_INTEL_NVL_I2C4,
+	PCI_DID_INTEL_NVL_I2C5,
 	PCI_DID_INTEL_WCL_I2C0,
 	PCI_DID_INTEL_WCL_I2C1,
 	PCI_DID_INTEL_WCL_I2C2,
diff --git a/src/soc/intel/common/block/ipu/ipu.c b/src/soc/intel/common/block/ipu/ipu.c
index 989da2e76a..a0acc6332d 100644
--- a/src/soc/intel/common/block/ipu/ipu.c
+++ b/src/soc/intel/common/block/ipu/ipu.c
@@ -12,6 +12,7 @@ struct device_operations ipu_pci_ops = {
 };
 
 static const uint16_t pci_device_ids[] = {
+	PCI_DID_INTEL_NVL_IPU,
 	PCI_DID_INTEL_PTL_IPU,
 	PCI_DID_INTEL_LNL_IPU,
 	PCI_DID_INTEL_RPL_IPU,
diff --git a/src/soc/intel/common/block/lpc/lpc.c b/src/soc/intel/common/block/lpc/lpc.c
index 391a0182f2..99c628e12c 100644
--- a/src/soc/intel/common/block/lpc/lpc.c
+++ b/src/soc/intel/common/block/lpc/lpc.c
@@ -151,6 +151,38 @@ struct device_operations lpc_ops = {
 };
 
 static const unsigned short pci_device_ids[] = {
+	PCI_DID_INTEL_NVL_ESPI_0,
+	PCI_DID_INTEL_NVL_ESPI_1,
+	PCI_DID_INTEL_NVL_ESPI_2,
+	PCI_DID_INTEL_NVL_ESPI_3,
+	PCI_DID_INTEL_NVL_ESPI_4,
+	PCI_DID_INTEL_NVL_ESPI_5,
+	PCI_DID_INTEL_NVL_ESPI_6,
+	PCI_DID_INTEL_NVL_ESPI_7,
+	PCI_DID_INTEL_NVL_ESPI_8,
+	PCI_DID_INTEL_NVL_ESPI_9,
+	PCI_DID_INTEL_NVL_ESPI_10,
+	PCI_DID_INTEL_NVL_ESPI_11,
+	PCI_DID_INTEL_NVL_ESPI_12,
+	PCI_DID_INTEL_NVL_ESPI_13,
+	PCI_DID_INTEL_NVL_ESPI_14,
+	PCI_DID_INTEL_NVL_ESPI_15,
+	PCI_DID_INTEL_NVL_ESPI_16,
+	PCI_DID_INTEL_NVL_ESPI_17,
+	PCI_DID_INTEL_NVL_ESPI_18,
+	PCI_DID_INTEL_NVL_ESPI_19,
+	PCI_DID_INTEL_NVL_ESPI_20,
+	PCI_DID_INTEL_NVL_ESPI_21,
+	PCI_DID_INTEL_NVL_ESPI_22,
+	PCI_DID_INTEL_NVL_ESPI_23,
+	PCI_DID_INTEL_NVL_ESPI_24,
+	PCI_DID_INTEL_NVL_ESPI_25,
+	PCI_DID_INTEL_NVL_ESPI_26,
+	PCI_DID_INTEL_NVL_ESPI_27,
+	PCI_DID_INTEL_NVL_ESPI_28,
+	PCI_DID_INTEL_NVL_ESPI_29,
+	PCI_DID_INTEL_NVL_ESPI_30,
+	PCI_DID_INTEL_NVL_ESPI_31,
 	PCI_DID_INTEL_WCL_ESPI_0,
 	PCI_DID_INTEL_WCL_ESPI_1,
 	PCI_DID_INTEL_WCL_ESPI_2,
diff --git a/src/soc/intel/common/block/p2sb/p2sb.c b/src/soc/intel/common/block/p2sb/p2sb.c
index 194c18f86a..64600b197c 100644
--- a/src/soc/intel/common/block/p2sb/p2sb.c
+++ b/src/soc/intel/common/block/p2sb/p2sb.c
@@ -145,6 +145,7 @@ const struct device_operations p2sb_ops = {
 };
 
 static const unsigned short pci_device_ids[] = {
+	PCI_DID_INTEL_NVL_P2SB,
 	PCI_DID_INTEL_WCL_P2SB,
 	PCI_DID_INTEL_PTL_H_P2SB,
 	PCI_DID_INTEL_PTL_U_H_P2SB,
diff --git a/src/soc/intel/common/block/p2sb/p2sb2.c b/src/soc/intel/common/block/p2sb/p2sb2.c
index 2627a7182c..1223f7339a 100644
--- a/src/soc/intel/common/block/p2sb/p2sb2.c
+++ b/src/soc/intel/common/block/p2sb/p2sb2.c
@@ -37,6 +37,7 @@ struct device_operations p2sb2_ops = {
 };
 
 static const unsigned short pci_device_ids[] = {
+	PCI_DID_INTEL_NVL_P2SB2,
 	PCI_DID_INTEL_WCL_P2SB2,
 	PCI_DID_INTEL_PTL_H_P2SB2,
 	PCI_DID_INTEL_PTL_U_H_P2SB2,
diff --git a/src/soc/intel/common/block/pcie/pcie.c b/src/soc/intel/common/block/pcie/pcie.c
index 18b938e280..4b64f85b8a 100644
--- a/src/soc/intel/common/block/pcie/pcie.c
+++ b/src/soc/intel/common/block/pcie/pcie.c
@@ -67,6 +67,20 @@ struct device_operations pcie_rp_ops = {
 };
 
 static const unsigned short pcie_device_ids[] = {
+	PCI_DID_INTEL_NVL_PCIE_RP1,
+	PCI_DID_INTEL_NVL_PCIE_RP2,
+	PCI_DID_INTEL_NVL_PCIE_RP3,
+	PCI_DID_INTEL_NVL_PCIE_RP4,
+	PCI_DID_INTEL_NVL_PCIE_RP5,
+	PCI_DID_INTEL_NVL_PCIE_RP6,
+	PCI_DID_INTEL_NVL_PCIE_RP7,
+	PCI_DID_INTEL_NVL_PCIE_RP8,
+	PCI_DID_INTEL_NVL_PCIE_RP9,
+	PCI_DID_INTEL_NVL_PCIE_RP10,
+	PCI_DID_INTEL_NVL_PCIE_RP11,
+	PCI_DID_INTEL_NVL_PCIE_RP12,
+	PCI_DID_INTEL_NVL_PCIE_RP13,
+	PCI_DID_INTEL_NVL_PCIE_RP14,
 	PCI_DID_INTEL_WCL_PCIE_RP1,
 	PCI_DID_INTEL_WCL_PCIE_RP2,
 	PCI_DID_INTEL_WCL_PCIE_RP3,
diff --git a/src/soc/intel/common/block/pmc/pmc.c b/src/soc/intel/common/block/pmc/pmc.c
index 09c08cdbb5..80db323ac6 100644
--- a/src/soc/intel/common/block/pmc/pmc.c
+++ b/src/soc/intel/common/block/pmc/pmc.c
@@ -111,6 +111,7 @@ struct device_operations pmc_ops = {
 };
 
 static const unsigned short pci_device_ids[] = {
+	PCI_DID_INTEL_NVL_PMC,
 	PCI_DID_INTEL_WCL_PMC,
 	PCI_DID_INTEL_PTL_H_PMC,
 	PCI_DID_INTEL_PTL_U_H_PMC,
diff --git a/src/soc/intel/common/block/spi/spi.c b/src/soc/intel/common/block/spi/spi.c
index 1ac0de0d7c..680e14e035 100644
--- a/src/soc/intel/common/block/spi/spi.c
+++ b/src/soc/intel/common/block/spi/spi.c
@@ -123,6 +123,10 @@ struct device_operations spi_dev_ops = {
 };
 
 static const unsigned short pci_device_ids[] = {
+	PCI_DID_INTEL_NVL_HWSEQ_SPI,
+	PCI_DID_INTEL_NVL_SPI0,
+	PCI_DID_INTEL_NVL_SPI1,
+	PCI_DID_INTEL_NVL_SPI2,
 	PCI_DID_INTEL_WCL_HWSEQ_SPI,
 	PCI_DID_INTEL_WCL_SPI0,
 	PCI_DID_INTEL_WCL_SPI1,
diff --git a/src/soc/intel/common/block/sram/sram.c b/src/soc/intel/common/block/sram/sram.c
index ba2ed8616f..cc51bcd084 100644
--- a/src/soc/intel/common/block/sram/sram.c
+++ b/src/soc/intel/common/block/sram/sram.c
@@ -33,6 +33,8 @@ static const struct device_operations device_ops = {
 };
 
 static const unsigned short pci_device_ids[] = {
+	PCI_DID_INTEL_NVL_SRAM,
+	PCI_DID_INTEL_NVL_PUNIT_CRASHLOG_SRAM,
 	PCI_DID_INTEL_WCL_SRAM,
 	PCI_DID_INTEL_WCL_PUNIT_CRASHLOG_SRAM,
 	PCI_DID_INTEL_PTL_H_SRAM,
diff --git a/src/soc/intel/common/block/systemagent/systemagent.c b/src/soc/intel/common/block/systemagent/systemagent.c
index 749e9c6ad9..7ea802ae06 100644
--- a/src/soc/intel/common/block/systemagent/systemagent.c
+++ b/src/soc/intel/common/block/systemagent/systemagent.c
@@ -425,6 +425,11 @@ struct device_operations systemagent_ops = {
 };
 
 static const unsigned short systemagent_ids[] = {
+	PCI_DID_INTEL_NVL_ID_1,
+	PCI_DID_INTEL_NVL_ID_2,
+	PCI_DID_INTEL_NVL_ID_3,
+	PCI_DID_INTEL_NVL_ID_4,
+	PCI_DID_INTEL_NVL_ID_5,
 	PCI_DID_INTEL_WCL_ID_1,
 	PCI_DID_INTEL_WCL_ID_2,
 	PCI_DID_INTEL_WCL_ID_3,
diff --git a/src/soc/intel/common/block/tracehub/tracehub.c b/src/soc/intel/common/block/tracehub/tracehub.c
index dc8c3fd2d6..1341779630 100644
--- a/src/soc/intel/common/block/tracehub/tracehub.c
+++ b/src/soc/intel/common/block/tracehub/tracehub.c
@@ -42,6 +42,7 @@ static struct device_operations dev_ops = {
 };
 
 static const unsigned short pci_device_ids[] = {
+	PCI_DID_INTEL_NVL_TRACEHUB,
 	PCI_DID_INTEL_WCL_TRACEHUB,
 	PCI_DID_INTEL_PTL_H_TRACEHUB,
 	PCI_DID_INTEL_PTL_U_H_TRACEHUB,
diff --git a/src/soc/intel/common/block/uart/uart.c b/src/soc/intel/common/block/uart/uart.c
index 8133551a27..0e9132d4c1 100644
--- a/src/soc/intel/common/block/uart/uart.c
+++ b/src/soc/intel/common/block/uart/uart.c
@@ -308,6 +308,7 @@ static const char *uart_acpi_hid(const struct device *dev)
 static const char *uart_acpi_name(const struct device *dev)
 {
 	switch (dev->device) {
+	case PCI_DID_INTEL_NVL_UART0:
 	case PCI_DID_INTEL_WCL_UART0:
 	case PCI_DID_INTEL_PTL_H_UART0:
 	case PCI_DID_INTEL_PTL_U_H_UART0:
@@ -319,6 +320,7 @@ static const char *uart_acpi_name(const struct device *dev)
 	case PCI_DID_INTEL_SPT_H_UART0:
 	case PCI_DID_INTEL_CNP_H_UART0:
 		return "UAR0";
+	case PCI_DID_INTEL_NVL_UART1:
 	case PCI_DID_INTEL_WCL_UART1:
 	case PCI_DID_INTEL_PTL_H_UART1:
 	case PCI_DID_INTEL_PTL_U_H_UART1:
@@ -330,6 +332,7 @@ static const char *uart_acpi_name(const struct device *dev)
 	case PCI_DID_INTEL_SPT_H_UART1:
 	case PCI_DID_INTEL_CNP_H_UART1:
 		return "UAR1";
+	case PCI_DID_INTEL_NVL_UART2:
 	case PCI_DID_INTEL_WCL_UART2:
 	case PCI_DID_INTEL_PTL_H_UART2:
 	case PCI_DID_INTEL_PTL_U_H_UART2:
@@ -360,6 +363,9 @@ struct device_operations uart_ops = {
 };
 
 static const unsigned short pci_device_ids[] = {
+	PCI_DID_INTEL_NVL_UART0,
+	PCI_DID_INTEL_NVL_UART1,
+	PCI_DID_INTEL_NVL_UART2,
 	PCI_DID_INTEL_WCL_UART0,
 	PCI_DID_INTEL_WCL_UART1,
 	PCI_DID_INTEL_WCL_UART2,
diff --git a/src/soc/intel/common/block/usb4/usb4.c b/src/soc/intel/common/block/usb4/usb4.c
index 9d176a3695..1daaf86fbb 100644
--- a/src/soc/intel/common/block/usb4/usb4.c
+++ b/src/soc/intel/common/block/usb4/usb4.c
@@ -52,6 +52,7 @@ static void tbt_dma_fill_ssdt(const struct device *dev)
 #endif
 
 static const unsigned short pci_device_ids[] = {
+	PCI_DID_INTEL_NVL_TBT_DMA0,
 	PCI_DID_INTEL_WCL_TBT_DMA0,
 	PCI_DID_INTEL_PTL_TBT_DMA0,
 	PCI_DID_INTEL_PTL_TBT_DMA1,
diff --git a/src/soc/intel/common/block/usb4/xhci.c b/src/soc/intel/common/block/usb4/xhci.c
index a23845820a..ac455f284c 100644
--- a/src/soc/intel/common/block/usb4/xhci.c
+++ b/src/soc/intel/common/block/usb4/xhci.c
@@ -26,6 +26,7 @@ static struct device_operations usb4_xhci_ops = {
 };
 
 static const unsigned short pci_device_ids[] = {
+	PCI_DID_INTEL_NVL_TCSS_XHCI,
 	PCI_DID_INTEL_WCL_TCSS_XHCI,
 	PCI_DID_INTEL_PTL_H_TCSS_XHCI,
 	PCI_DID_INTEL_PTL_U_H_TCSS_XHCI,
diff --git a/src/soc/intel/common/block/xdci/xdci.c b/src/soc/intel/common/block/xdci/xdci.c
index ed6a15b363..6916d8c3f5 100644
--- a/src/soc/intel/common/block/xdci/xdci.c
+++ b/src/soc/intel/common/block/xdci/xdci.c
@@ -28,6 +28,7 @@ struct device_operations usb_xdci_ops = {
 };
 
 static const unsigned short pci_device_ids[] = {
+	PCI_DID_INTEL_NVL_XDCI,
 	PCI_DID_INTEL_WCL_XDCI,
 	PCI_DID_INTEL_PTL_H_XDCI,
 	PCI_DID_INTEL_PTL_U_H_XDCI,
diff --git a/src/soc/intel/common/block/xhci/xhci.c b/src/soc/intel/common/block/xhci/xhci.c
index 8350c3650b..d12792dbb8 100644
--- a/src/soc/intel/common/block/xhci/xhci.c
+++ b/src/soc/intel/common/block/xhci/xhci.c
@@ -131,6 +131,7 @@ struct device_operations usb_xhci_ops = {
 };
 
 static const unsigned short pci_device_ids[] = {
+	PCI_DID_INTEL_NVL_XHCI,
 	PCI_DID_INTEL_WCL_XHCI,
 	PCI_DID_INTEL_PTL_H_XHCI,
 	PCI_DID_INTEL_PTL_U_H_XHCI,

From 71296476a84a43f0ca872ccda5a063e8432aa9e1 Mon Sep 17 00:00:00 2001
From: Maximilian Brune <maximilian.brune@9elements.com>
Date: Tue, 20 Jan 2026 17:06:18 +0100
Subject: [PATCH 3125/3886] tests/lib/coreboot_table-test.c: Add
 lb_string_platform_blob_version

A later patch changes the .config file which we use for our tests.
However that causes the PLATFORM_USES_FSP2_0 option to be enabled, which
in turn causes build errors in our tests, because the function is
obviously not defined in our tests. Create a stub function of sorts like
we do for other coreboot table entries.

It also moves the declaration of the `lb_string_platform_blob_version`
function to coreboot_tables.h, since it doesn't belong in the FSP header
file. Because of that we can also remove the
`if (CONFIG_PLATFORM_USES_FSP2_0)`
check, which makes the code a bit cleaner.

Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: I7721dfe4d287b2274a383bb7e5337b85a0f3f148
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90830
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jakub "Kuba" Czapiga <czapiga@google.com>
---
 src/drivers/intel/fsp2_0/include/fsp/util.h |  1 -
 src/include/boot/coreboot_tables.h          |  2 ++
 src/lib/coreboot_table.c                    |  5 -----
 tests/lib/coreboot_table-test.c             | 19 +++++++++++++++++++
 4 files changed, 21 insertions(+), 6 deletions(-)

diff --git a/src/drivers/intel/fsp2_0/include/fsp/util.h b/src/drivers/intel/fsp2_0/include/fsp/util.h
index ce6666a453..88b0b6a22c 100644
--- a/src/drivers/intel/fsp2_0/include/fsp/util.h
+++ b/src/drivers/intel/fsp2_0/include/fsp/util.h
@@ -166,7 +166,6 @@ void display_fsp_error_info_hob(const void *hob);
 void fsp_get_version(char *buf);
 /* fsp_verify_upd_header_signature calls die() on signature mismatch */
 void fsp_verify_upd_header_signature(uint64_t upd_signature, uint64_t expected_signature);
-void lb_string_platform_blob_version(struct lb_header *header);
 void report_fspt_output(void);
 void soc_validate_fspm_header(const struct fsp_header *hdr);
 /*
diff --git a/src/include/boot/coreboot_tables.h b/src/include/boot/coreboot_tables.h
index 3a5e31651c..ec56c15923 100644
--- a/src/include/boot/coreboot_tables.h
+++ b/src/include/boot/coreboot_tables.h
@@ -24,6 +24,8 @@ void lb_add_console(uint16_t consoletype, void *data);
 
 enum cb_err fill_lb_pcie(struct lb_pcie *pcie);
 
+void lb_string_platform_blob_version(struct lb_header *header);
+
 /* Define this in mainboard.c to add board-specific table entries. */
 void lb_board(struct lb_header *header);
 
diff --git a/src/lib/coreboot_table.c b/src/lib/coreboot_table.c
index 6218784adc..5aa0e92d15 100644
--- a/src/lib/coreboot_table.c
+++ b/src/lib/coreboot_table.c
@@ -29,11 +29,6 @@
 #if CONFIG(USE_OPTION_TABLE)
 #include <option_table.h>
 #endif
-#if CONFIG(PLATFORM_USES_FSP2_0)
-#include <fsp/util.h>
-#else
-void lb_string_platform_blob_version(struct lb_header *header);
-#endif
 
 __weak enum cb_err fill_lb_pcie(struct lb_pcie *pcie)
 {
diff --git a/tests/lib/coreboot_table-test.c b/tests/lib/coreboot_table-test.c
index 9547ee07a6..2197b95631 100644
--- a/tests/lib/coreboot_table-test.c
+++ b/tests/lib/coreboot_table-test.c
@@ -176,6 +176,8 @@ const unsigned int coreboot_minor_revision = 13;
 const char coreboot_compile_time[] = "13:58:22";
 const char coreboot_dmi_date[] = "03/31/2021";
 
+const uint8_t platform_blob_version[] = "3.2.1";
+
 const struct bcd_date coreboot_build_date = {
 	.century = 0x20,
 	.year = 0x20,
@@ -228,6 +230,18 @@ enum cb_err fill_lb_serial(struct lb_serial *serial)
 	return CB_SUCCESS;
 }
 
+void lb_string_platform_blob_version(struct lb_header *header)
+{
+	struct lb_string *rec;
+	size_t len;
+
+	rec = (struct lb_string *)lb_new_record(header);
+	rec->tag = LB_TAG_PLATFORM_BLOB_VERSION;
+	len = sizeof(platform_blob_version);
+	rec->size = ALIGN_UP(sizeof(*rec) + len, 8);
+	memcpy(rec->string, platform_blob_version, len);
+}
+
 struct cbfs_boot_device cbfs_boot_dev = {
 	.rdev = REGION_DEV_INIT(NULL, 0, 0x1000),
 	.mcache = (void *)0x1000,
@@ -464,6 +478,11 @@ static void test_write_tables(void **state)
 			const struct lb_acpi_rsdp *acpi_rsdp = (struct lb_acpi_rsdp *)record;
 			assert_int_equal(ebda_base, acpi_rsdp->rsdp_pointer);
 			break;
+		case LB_TAG_PLATFORM_BLOB_VERSION:
+			uint32_t platform_blob_version_size =
+				ALIGN_UP(sizeof(struct lb_string) + sizeof(platform_blob_version), 8);
+			assert_int_equal(platform_blob_version_size, record->size);
+			break;
 		default:
 			fail_msg("Unexpected tag found in record. Tag ID: 0x%x", record->tag);
 		}

From cbca308a056be421566803f241e6d7d7f0e32286 Mon Sep 17 00:00:00 2001
From: Maximilian Brune <maximilian.brune@9elements.com>
Date: Tue, 20 Jan 2026 17:20:30 +0100
Subject: [PATCH 3126/3886] include/console/console.h: Enable console for
 ENV_TEST

`tests/stubs/console.c` also implements printk for our test functions.

Change-Id: Ic6ad8832515b90f4706cb9c5b9d9525a25485992
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90831
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
---
 src/include/console/console.h | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/src/include/console/console.h b/src/include/console/console.h
index 8d1a5c5dde..927b1d6ef0 100644
--- a/src/include/console/console.h
+++ b/src/include/console/console.h
@@ -45,7 +45,8 @@ static inline int get_console_loglevel(void)
 	((ENV_BOOTBLOCK && CONFIG(BOOTBLOCK_CONSOLE)) || \
 	 (ENV_POSTCAR && CONFIG(POSTCAR_CONSOLE)) || \
 	 ENV_SEPARATE_VERSTAGE || ENV_SEPARATE_ROMSTAGE || ENV_RAMSTAGE || \
-	 ENV_LIBAGESA || (ENV_SMM && CONFIG(DEBUG_SMI)))
+	 ENV_LIBAGESA || (ENV_SMM && CONFIG(DEBUG_SMI)) || \
+	 ENV_TEST)
 
 #if __CONSOLE_ENABLE__
 int get_log_level(void);

From 177c2b86246361227ac9ece54322182c4c76d28b Mon Sep 17 00:00:00 2001
From: Jeremy Compostella <jeremy.compostella@intel.com>
Date: Thu, 22 Jan 2026 14:53:54 -0800
Subject: [PATCH 3127/3886] ec/google/chromeec/acpi: Fix typo in sensor event
 comment

Correct a spelling error in the comment within the EC0 device block,
changing "reaading" to "reading".

Change-Id: I5cc57cad86f72be96e1465a1e8de9b9850adf7c1
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90869
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
---
 src/ec/google/chromeec/acpi/ec.asl | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/ec/google/chromeec/acpi/ec.asl b/src/ec/google/chromeec/acpi/ec.asl
index ebba0faffd..93b04718ec 100644
--- a/src/ec/google/chromeec/acpi/ec.asl
+++ b/src/ec/google/chromeec/acpi/ec.asl
@@ -589,7 +589,7 @@ Device (EC0)
 				\_SB.DPTF.TEVT (Local0)
 #endif
 
-				/* Keep reaading sensor ID for event */
+				/* Keep reading sensor ID for event */
 				Local0 = ^PATI
 			}
 

From 472b2928f3e68b898fb4339ab51c5b474f65705a Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Micha=C5=82=20=C5=BBygowski?= <michal.zygowski@3mdeb.com>
Date: Fri, 5 Dec 2025 11:26:48 +0100
Subject: [PATCH 3128/3886] util/amdfwtool: Use enum values for address mode
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Replace hardcoded values of address mode with its corresponding
enum value to increase code readability.

Change-Id: Ib2d97f36aa19235a312558e397f97e2607476e61
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90391
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 util/amdfwtool/amdfwread.c | 9 +++++----
 util/amdfwtool/amdfwtool.c | 2 +-
 2 files changed, 6 insertions(+), 5 deletions(-)

diff --git a/util/amdfwtool/amdfwread.c b/util/amdfwtool/amdfwread.c
index 46884f1e48..4dde162cd3 100644
--- a/util/amdfwtool/amdfwread.c
+++ b/util/amdfwtool/amdfwread.c
@@ -269,7 +269,7 @@ static int amdfw_bios_dir_walk(FILE *fw, uint32_t bios_offset, uint32_t cookie,
 	size_t num_current_entries = 0;
 	bios_directory_hdr header;
 	uint32_t l2_dir_offset = 0;
-	uint64_t dir_mode = 0;
+	uint64_t dir_mode = AMD_ADDR_PHYSICAL;
 	char indent[MAX_INDENTATION_LEN] = {0};
 
 	if (read_bios_directory(fw, bios_offset, cookie, &header,
@@ -287,7 +287,7 @@ static int amdfw_bios_dir_walk(FILE *fw, uint32_t bios_offset, uint32_t cookie,
 		uint64_t mode = current_entries[i].address_mode;
 		uint64_t addr = current_entries[i].source;
 
-		if (dir_mode < 2)
+		if (dir_mode < AMD_ADDR_REL_TAB)
 			mode = dir_mode;
 
 		if (type == AMD_BIOS_APOB || type == AMD_BIOS_PSP_SHARED_MEM)
@@ -386,7 +386,7 @@ static int amdfw_psp_dir_walk(FILE *fw, uint32_t psp_offset, uint32_t cookie, ui
 	uint32_t bios_dir_offset = 0;
 	uint32_t ish_dir_offset = 0;
 	ish_directory_table ish_dir;
-	uint64_t dir_mode = 0;
+	uint64_t dir_mode = AMD_ADDR_PHYSICAL;
 	char indent[MAX_INDENTATION_LEN] = {0};
 
 	if (read_psp_directory(fw, psp_offset, cookie, &header,
@@ -404,7 +404,8 @@ static int amdfw_psp_dir_walk(FILE *fw, uint32_t psp_offset, uint32_t cookie, ui
 		uint64_t mode = current_entries[i].address_mode;
 		uint64_t addr = current_entries[i].addr;
 		uint32_t dir_size = 0;
-		if (dir_mode < 2)
+
+		if (dir_mode < AMD_ADDR_REL_TAB)
 			mode = dir_mode;
 
 		if (type == AMD_PSP_FUSE_CHAIN)
diff --git a/util/amdfwtool/amdfwtool.c b/util/amdfwtool/amdfwtool.c
index 4184a60b74..6c1ec632a6 100644
--- a/util/amdfwtool/amdfwtool.c
+++ b/util/amdfwtool/amdfwtool.c
@@ -1088,7 +1088,7 @@ static void integrate_psp_firmwares(context *ctx,
 			pspdir->entries[count].rsvd = 0;
 			pspdir->entries[count].size = 0xFFFFFFFF;
 			pspdir->entries[count].addr = fw_table[i].other;
-			pspdir->entries[count].address_mode = 0;
+			pspdir->entries[count].address_mode = AMD_ADDR_PHYSICAL;
 			count++;
 		} else if (fw_table[i].type == AMD_FW_PSP_NVRAM ||
 			   fw_table[i].type == AMD_RPMC_NVRAM) {

From c377682973a77466988d992d0221789accfa2865 Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Thu, 22 Jan 2026 14:02:49 -0600
Subject: [PATCH 3129/3886] util/inteltool: Add support for Arrow Lake H

Add PCI IDs necessary to support Intel Core Ultra 9 285H (Arrow Lake-H
platform). Arrow Lake is a Meteor Lake variant, so handle the same as
Meteor Lake-P. Add a missing PCI ID for MTL-P as well.

TEST=dump GPIOs on Starlabs Starfighter with Core Ultra 125H (MTL) and
285H (ARL) CPUs.

Change-Id: I14b74227ce808a7b4269741b7e2c5f23326bced4
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90868
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
---
 util/inteltool/gpio.c        | 2 ++
 util/inteltool/gpio_groups.c | 1 +
 util/inteltool/inteltool.c   | 6 ++++++
 util/inteltool/inteltool.h   | 7 +++++++
 util/inteltool/pcr.c         | 1 +
 5 files changed, 17 insertions(+)

diff --git a/util/inteltool/gpio.c b/util/inteltool/gpio.c
index ff21d2452b..2a893a2daf 100644
--- a/util/inteltool/gpio.c
+++ b/util/inteltool/gpio.c
@@ -1133,6 +1133,7 @@ int print_gpios(struct pci_dev *sb, int show_all, int show_diffs)
 	case PCI_DEVICE_ID_INTEL_CORE_MTL_ID_P_3:
 	case PCI_DEVICE_ID_INTEL_CORE_MTL_ID_P_4:
 	case PCI_DEVICE_ID_INTEL_CORE_MTL_ID_P_5:
+	case PCI_DEVICE_ID_INTEL_CORE_ARL_ID_H_1:
 	case PCI_DEVICE_ID_INTEL_MTL_0:
 	case PCI_DEVICE_ID_INTEL_MTL_1:
 	case PCI_DEVICE_ID_INTEL_MTL_2:
@@ -1141,6 +1142,7 @@ int print_gpios(struct pci_dev *sb, int show_all, int show_diffs)
 	case PCI_DEVICE_ID_INTEL_MTL_5:
 	case PCI_DEVICE_ID_INTEL_MTL_6:
 	case PCI_DEVICE_ID_INTEL_MTL_7:
+	case PCI_DEVICE_ID_INTEL_ARL_1:
 		print_gpio_groups(sb);
 		return 0;
 	case PCI_DEVICE_ID_INTEL_82371XX:
diff --git a/util/inteltool/gpio_groups.c b/util/inteltool/gpio_groups.c
index fb50905b25..23757ba630 100644
--- a/util/inteltool/gpio_groups.c
+++ b/util/inteltool/gpio_groups.c
@@ -264,6 +264,7 @@ const struct gpio_community *const *get_gpio_communities(struct pci_dev *const s
 	case PCI_DEVICE_ID_INTEL_MTL_5:
 	case PCI_DEVICE_ID_INTEL_MTL_6:
 	case PCI_DEVICE_ID_INTEL_MTL_7:
+	case PCI_DEVICE_ID_INTEL_ARL_1:
 		*community_count = ARRAY_SIZE(meteorlake_pch_communities);
 		*pad_stepping = 16;
 		return meteorlake_pch_communities;
diff --git a/util/inteltool/inteltool.c b/util/inteltool/inteltool.c
index d58b850717..5bd9a05949 100644
--- a/util/inteltool/inteltool.c
+++ b/util/inteltool/inteltool.c
@@ -204,6 +204,8 @@ static const struct {
 	  "14th generation (Meteor Lake P family) Core Processor"},
 	{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_MTL_ID_P_5,
 	  "14th generation (Meteor Lake P family) Core Processor"},
+	{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_ARL_ID_H_1,
+	  "14th generation (Arrow Lake H family) Core Processor"},
 
 	{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ELKHART_LAKE_1,
 	  "Elkhart Lake Processor" },
@@ -465,6 +467,8 @@ static const struct {
 	{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_JSL, "Jasper Lake" },
 	{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ADL_N, "Alder Lake-N"},
 	{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_RPL_P, "Raptor Lake" },
+	{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_MTL_P, "Meteor Lake-P"},
+	{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ARL_H, "Arrow Lake-H"},
 
 	/* Intel GPUs */
 	{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_G35_EXPRESS,
@@ -643,6 +647,8 @@ static const struct {
 	  "Intel(R) MeteorLake-P GT2" },
 	{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_MTL_P_GT2_4,
 	  "Intel(R) MeteorLake-P GT2" },
+	{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ARL_H_GT2_1,
+	  "Intel(R) ArrowLake-H GT2" },
 	{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EHL_GT1_1,
 	  "Intel(R) Elkhart Lake GT1" },
 	{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EHL_GT1_2,
diff --git a/util/inteltool/inteltool.h b/util/inteltool/inteltool.h
index f0ddef283d..c279d02e87 100644
--- a/util/inteltool/inteltool.h
+++ b/util/inteltool/inteltool.h
@@ -258,6 +258,8 @@ static inline uint32_t inl(unsigned port)
 #define PCI_DEVICE_ID_INTEL_MTL_6		0x7e06
 #define PCI_DEVICE_ID_INTEL_MTL_7		0x7e07
 
+#define PCI_DEVICE_ID_INTEL_ARL_1		0x7702
+
 #define PCI_DEVICE_ID_INTEL_82810		0x7120
 #define PCI_DEVICE_ID_INTEL_82810_DC	0x7122
 #define PCI_DEVICE_ID_INTEL_82810E_DC	0x7124
@@ -321,6 +323,9 @@ static inline uint32_t inl(unsigned port)
 #define PCI_DEVICE_ID_INTEL_RPL_P		0x519d
 #define PCI_DEVICE_ID_INTEL_ADL_N		0x5481
 
+#define PCI_DEVICE_ID_INTEL_MTL_P		0x7e27
+#define PCI_DEVICE_ID_INTEL_ARL_H		0x7727
+
 #define PCI_DEVICE_ID_INTEL_EHL			0x4b00
 #define PCI_DEVICE_ID_INTEL_JSL			0x4d87
 
@@ -420,6 +425,7 @@ static inline uint32_t inl(unsigned port)
 #define PCI_DEVICE_ID_INTEL_CORE_MTL_ID_M	0x7D00 /* Meteorlake M */
 #define PCI_DEVICE_ID_INTEL_CORE_MTL_ID_P_1	0x7D01 /* Meteorlake P */
 #define PCI_DEVICE_ID_INTEL_CORE_MTL_ID_P_2	0x7D02 /* Meteorlake P */
+#define PCI_DEVICE_ID_INTEL_CORE_ARL_ID_H_1	0x7D06 /* Arrowlake H */
 #define PCI_DEVICE_ID_INTEL_CORE_MTL_ID_P_3	0x7d14 /* Meteorlake P */
 #define PCI_DEVICE_ID_INTEL_CORE_MTL_ID_P_4	0x7d15 /* Meteorlake P */
 #define PCI_DEVICE_ID_INTEL_CORE_MTL_ID_P_5	0x7d16 /* Meteorlake P */
@@ -521,6 +527,7 @@ static inline uint32_t inl(unsigned port)
 #define PCI_DEVICE_ID_INTEL_MTL_P_GT2_2		0x7d50
 #define PCI_DEVICE_ID_INTEL_MTL_P_GT2_3		0x7d55
 #define PCI_DEVICE_ID_INTEL_MTL_P_GT2_4		0x7d60
+#define PCI_DEVICE_ID_INTEL_ARL_H_GT2_1		0x7d51
 #define PCI_DEVICE_ID_INTEL_RPL_H_IRIS_XE	0xa7a0
 
 #if !defined(__DARWIN__) && !defined(__FreeBSD__)
diff --git a/util/inteltool/pcr.c b/util/inteltool/pcr.c
index 6594561257..6d70905021 100644
--- a/util/inteltool/pcr.c
+++ b/util/inteltool/pcr.c
@@ -188,6 +188,7 @@ void pcr_init(struct pci_dev *const sb)
 	case PCI_DEVICE_ID_INTEL_MTL_5:
 	case PCI_DEVICE_ID_INTEL_MTL_6:
 	case PCI_DEVICE_ID_INTEL_MTL_7:
+	case PCI_DEVICE_ID_INTEL_ARL_1:
 		sbbar_phys = 0xe0000000;
 		use_p2sb = false;
 		break;

From 6c7f734f7bceeba3f75d45a18ec9f74254687ae6 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Micha=C5=82=20=C5=BBygowski?= <michal.zygowski@3mdeb.com>
Date: Sun, 18 Jan 2026 17:53:45 +0100
Subject: [PATCH 3130/3886] util/amdfwtool: Fix a bug clearing two bits of soft
 fuse value
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

The PSP soft fuse is a 64bit value which does not use address mode
bits. Those address mode bits are also part of the soft fuse value,
thus must not be hardcoded to 0.

Change-Id: I5a3e078800653d15baf1939fdce11a60031b9978
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90789
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 util/amdfwtool/amdfwtool.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/util/amdfwtool/amdfwtool.c b/util/amdfwtool/amdfwtool.c
index 6c1ec632a6..af24697bca 100644
--- a/util/amdfwtool/amdfwtool.c
+++ b/util/amdfwtool/amdfwtool.c
@@ -1088,7 +1088,7 @@ static void integrate_psp_firmwares(context *ctx,
 			pspdir->entries[count].rsvd = 0;
 			pspdir->entries[count].size = 0xFFFFFFFF;
 			pspdir->entries[count].addr = fw_table[i].other;
-			pspdir->entries[count].address_mode = AMD_ADDR_PHYSICAL;
+			pspdir->entries[count].address_mode = fw_table[i].other >> 62;
 			count++;
 		} else if (fw_table[i].type == AMD_FW_PSP_NVRAM ||
 			   fw_table[i].type == AMD_RPMC_NVRAM) {

From c9cbd45cbed1438762174d45a8341bf645fc8721 Mon Sep 17 00:00:00 2001
From: Felix Held <felix-coreboot@felixheld.de>
Date: Fri, 23 Jan 2026 17:08:16 +0100
Subject: [PATCH 3131/3886] soc/amd/glinda,picasso/xhci: use XHCI_GEVENT define

The other AMD SoCs already use the XHCI_GEVENT define and since it's
defined as GEVENT_31, this won't change the behavior.

Change-Id: I895f453497f6e03e1aff237ba6d6ec1ebecfaaaf
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90876
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
---
 src/soc/amd/glinda/xhci.c  | 9 +++++----
 src/soc/amd/picasso/xhci.c | 5 +++--
 2 files changed, 8 insertions(+), 6 deletions(-)

diff --git a/src/soc/amd/glinda/xhci.c b/src/soc/amd/glinda/xhci.c
index b67bb5a060..64eb72c8d8 100644
--- a/src/soc/amd/glinda/xhci.c
+++ b/src/soc/amd/glinda/xhci.c
@@ -4,6 +4,7 @@
 
 #include <amdblocks/gpio.h>
 #include <amdblocks/smi.h>
+#include <amdblocks/xhci.h>
 #include <bootstate.h>
 #include <device/device.h>
 #include <device/pci_ids.h>
@@ -14,25 +15,25 @@
 static const struct sci_source xhci_sci_sources[] = {
 	{
 		.scimap = SMITYPE_XHC0_PME,
-		.gpe = GEVENT_31,
+		.gpe = XHCI_GEVENT,
 		.direction = SMI_SCI_LVL_HIGH,
 		.level = SMI_SCI_EDG
 	},
 	{
 		.scimap = SMITYPE_XHC1_PME,
-		.gpe = GEVENT_31,
+		.gpe = XHCI_GEVENT,
 		.direction = SMI_SCI_LVL_HIGH,
 		.level = SMI_SCI_EDG
 	},
 	{
 		.scimap = SMITYPE_XHC3_PME,
-		.gpe = GEVENT_31,
+		.gpe = XHCI_GEVENT,
 		.direction = SMI_SCI_LVL_HIGH,
 		.level = SMI_SCI_EDG
 	},
 	{
 		.scimap = SMITYPE_XHC4_PME,
-		.gpe = GEVENT_31,
+		.gpe = XHCI_GEVENT,
 		.direction = SMI_SCI_LVL_HIGH,
 		.level = SMI_SCI_EDG
 	}
diff --git a/src/soc/amd/picasso/xhci.c b/src/soc/amd/picasso/xhci.c
index a238916b71..1258234df4 100644
--- a/src/soc/amd/picasso/xhci.c
+++ b/src/soc/amd/picasso/xhci.c
@@ -2,6 +2,7 @@
 
 #include <amdblocks/gpio.h>
 #include <amdblocks/smi.h>
+#include <amdblocks/xhci.h>
 #include <bootstate.h>
 #include <device/device.h>
 #include <drivers/usb/pci_xhci/pci_xhci.h>
@@ -12,13 +13,13 @@
 static const struct sci_source xhci_sci_sources[] = {
 	{
 		.scimap = SMITYPE_XHC0_PME,
-		.gpe = GEVENT_31,
+		.gpe = XHCI_GEVENT,
 		.direction = SMI_SCI_LVL_HIGH,
 		.level = SMI_SCI_EDG
 	},
 	{
 		.scimap = SMITYPE_XHC1_PME,
-		.gpe = GEVENT_31,
+		.gpe = XHCI_GEVENT,
 		.direction = SMI_SCI_LVL_HIGH,
 		.level = SMI_SCI_EDG
 	}

From 09b8b5a33a88fb20b4cf0b55d008d3bf718ead97 Mon Sep 17 00:00:00 2001
From: Patrick Rudolph <patrick.rudolph@9elements.com>
Date: Sun, 4 Jan 2026 12:25:20 +0100
Subject: [PATCH 3132/3886] mb/lenovo/*: Add CBFS_SIZE for some boards

Add a default CBFS_SIZE for some boards to make sure they use
the whole BIOS region by default.

Change-Id: Ia032a9d5b3ba271390cc5f35ee734a1bbb1b90a4
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90721
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
---
 src/mainboard/lenovo/haswell/Kconfig        | 3 +++
 src/mainboard/lenovo/t420/Kconfig           | 3 +++
 src/mainboard/lenovo/t420s/Kconfig          | 3 +++
 src/mainboard/lenovo/t430/Kconfig           | 3 +++
 src/mainboard/lenovo/t430s/Kconfig          | 3 +++
 src/mainboard/lenovo/t520/Kconfig           | 3 +++
 src/mainboard/lenovo/t530/Kconfig           | 3 +++
 src/mainboard/lenovo/x131e/Kconfig          | 3 +++
 src/mainboard/lenovo/x1_carbon_gen1/Kconfig | 3 +++
 src/mainboard/lenovo/x220/Kconfig           | 3 +++
 src/mainboard/lenovo/x230/Kconfig           | 4 ++++
 11 files changed, 34 insertions(+)

diff --git a/src/mainboard/lenovo/haswell/Kconfig b/src/mainboard/lenovo/haswell/Kconfig
index 46da23cfd2..8803717024 100644
--- a/src/mainboard/lenovo/haswell/Kconfig
+++ b/src/mainboard/lenovo/haswell/Kconfig
@@ -51,6 +51,9 @@ config VARIANT_DIR
 config DEVICETREE
 	default "variants/\$(CONFIG_VARIANT_DIR)/devicetree.cb"
 
+config CBFS_SIZE
+	default 0x700000
+
 config FMDFILE
 	default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/vboot-rwab.fmd" if VBOOT
 
diff --git a/src/mainboard/lenovo/t420/Kconfig b/src/mainboard/lenovo/t420/Kconfig
index 1b9ddd6e4c..54d1cda106 100644
--- a/src/mainboard/lenovo/t420/Kconfig
+++ b/src/mainboard/lenovo/t420/Kconfig
@@ -44,6 +44,9 @@ config VBOOT
 config VBOOT_SLOTS_RW_A
 	default y
 
+config CBFS_SIZE
+	default 0x300000
+
 config FMDFILE
 	default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/vboot-rwa.fmd" if VBOOT
 
diff --git a/src/mainboard/lenovo/t420s/Kconfig b/src/mainboard/lenovo/t420s/Kconfig
index 21bbd87431..bbfc9d0ef5 100644
--- a/src/mainboard/lenovo/t420s/Kconfig
+++ b/src/mainboard/lenovo/t420s/Kconfig
@@ -42,6 +42,9 @@ config VBOOT
 config VBOOT_SLOTS_RW_A
 	default y
 
+config CBFS_SIZE
+	default 0x300000
+
 config FMDFILE
 	default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/vboot-rwa.fmd" if VBOOT
 
diff --git a/src/mainboard/lenovo/t430/Kconfig b/src/mainboard/lenovo/t430/Kconfig
index 20726edb50..fe1d5fcd7b 100644
--- a/src/mainboard/lenovo/t430/Kconfig
+++ b/src/mainboard/lenovo/t430/Kconfig
@@ -43,6 +43,9 @@ config VBOOT
 config VBOOT_SLOTS_RW_AB
 	default y
 
+config CBFS_SIZE
+	default 0x700000
+
 config FMDFILE
 	default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/vboot-rwab.fmd" if VBOOT
 
diff --git a/src/mainboard/lenovo/t430s/Kconfig b/src/mainboard/lenovo/t430s/Kconfig
index 10ce88c6f1..1e80628384 100644
--- a/src/mainboard/lenovo/t430s/Kconfig
+++ b/src/mainboard/lenovo/t430s/Kconfig
@@ -45,6 +45,9 @@ config VBOOT
 config VBOOT_SLOTS_RW_AB
 	default y
 
+config CBFS_SIZE
+	default 0xB00000
+
 config FMDFILE
 	default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/vboot-rwab.fmd" if VBOOT
 
diff --git a/src/mainboard/lenovo/t520/Kconfig b/src/mainboard/lenovo/t520/Kconfig
index a93c859615..ed424ed0a7 100644
--- a/src/mainboard/lenovo/t520/Kconfig
+++ b/src/mainboard/lenovo/t520/Kconfig
@@ -60,6 +60,9 @@ config MAINBOARD_DIR
 config OVERRIDE_DEVICETREE
 	default "variants/\$(CONFIG_VARIANT_DIR)/overridetree.cb"
 
+config CBFS_SIZE
+	default 0x300000
+
 config FMDFILE
 	default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/vboot-rwa.fmd" if VBOOT
 
diff --git a/src/mainboard/lenovo/t530/Kconfig b/src/mainboard/lenovo/t530/Kconfig
index 801e931fbd..a825e1186b 100644
--- a/src/mainboard/lenovo/t530/Kconfig
+++ b/src/mainboard/lenovo/t530/Kconfig
@@ -50,6 +50,9 @@ config VBOOT
 config VBOOT_SLOTS_RW_AB
 	default y
 
+config CBFS_SIZE
+	default 0x700000
+
 config FMDFILE
 	default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/vboot-rwab.fmd" if VBOOT
 
diff --git a/src/mainboard/lenovo/x131e/Kconfig b/src/mainboard/lenovo/x131e/Kconfig
index df435e9cfb..c59660adf1 100644
--- a/src/mainboard/lenovo/x131e/Kconfig
+++ b/src/mainboard/lenovo/x131e/Kconfig
@@ -36,6 +36,9 @@ config VBOOT
 config VBOOT_SLOTS_RW_AB
 	default y
 
+config CBFS_SIZE
+	default 0x700000
+
 config FMDFILE
 	default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/vboot-rwab.fmd" if VBOOT
 
diff --git a/src/mainboard/lenovo/x1_carbon_gen1/Kconfig b/src/mainboard/lenovo/x1_carbon_gen1/Kconfig
index 902b92d5d3..39daee8b0d 100644
--- a/src/mainboard/lenovo/x1_carbon_gen1/Kconfig
+++ b/src/mainboard/lenovo/x1_carbon_gen1/Kconfig
@@ -43,6 +43,9 @@ config VBOOT
 config VBOOT_SLOTS_RW_AB
 	default y
 
+config CBFS_SIZE
+	default 0x700000
+
 config FMDFILE
 	default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/vboot-rwab.fmd" if VBOOT
 
diff --git a/src/mainboard/lenovo/x220/Kconfig b/src/mainboard/lenovo/x220/Kconfig
index 453afd4bef..3b4c6ce0ea 100644
--- a/src/mainboard/lenovo/x220/Kconfig
+++ b/src/mainboard/lenovo/x220/Kconfig
@@ -49,6 +49,9 @@ config VARIANT_DIR
 	default "x220" if BOARD_LENOVO_X220 || BOARD_LENOVO_X220I
 	default "x1" if BOARD_LENOVO_X1
 
+config CBFS_SIZE
+	default 0x300000
+
 config FMDFILE
 	default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/vboot-rwa.fmd" if VBOOT
 
diff --git a/src/mainboard/lenovo/x230/Kconfig b/src/mainboard/lenovo/x230/Kconfig
index 81049412df..2980c91b3a 100644
--- a/src/mainboard/lenovo/x230/Kconfig
+++ b/src/mainboard/lenovo/x230/Kconfig
@@ -45,6 +45,10 @@ config VBOOT
 config VBOOT_SLOTS_RW_AB
 	default y
 
+config CBFS_SIZE
+	default 0x700000 if BOARD_LENOVO_X230 || BOARD_LENOVO_X230T || BOARD_LENOVO_X230_EDP
+	default 0xB00000
+
 config FMDFILE
 	default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/vboot-rwab.fmd" if VBOOT
 

From deeb884c8dbc639bb0e95087acea5e1d44d2e5be Mon Sep 17 00:00:00 2001
From: Maximilian Brune <maximilian.brune@9elements.com>
Date: Tue, 20 Jan 2026 18:17:39 +0100
Subject: [PATCH 3133/3886] Makefile.mk: Remove RISC-V workaround

The issue has been fixed since binutils version 2.43

Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: I9d8802aa0908dd2838199399e739b13c345702f3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90815
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 Makefile.mk | 5 -----
 1 file changed, 5 deletions(-)

diff --git a/Makefile.mk b/Makefile.mk
index a823a115a4..e83a304ca6 100644
--- a/Makefile.mk
+++ b/Makefile.mk
@@ -614,12 +614,7 @@ LDFLAGS_common += -nostdlib
 LDFLAGS_common += --nmagic
 LDFLAGS_common += -static
 LDFLAGS_common += -z noexecstack
-
-# Workaround for RISC-V linker bug, merge back into above line when fixed.
-# https://sourceware.org/bugzilla/show_bug.cgi?id=27180
-ifneq ($(CONFIG_ARCH_RISCV),y)
 LDFLAGS_common += --emit-relocs
-endif
 
 ifeq ($(CONFIG_WARNINGS_ARE_ERRORS),y)
 CFLAGS_common += -Werror

From 8dd881ea47e0f39e2afdbab0b8992138bb454ff3 Mon Sep 17 00:00:00 2001
From: Maximilian Brune <maximilian.brune@9elements.com>
Date: Sat, 29 Nov 2025 06:34:52 +0100
Subject: [PATCH 3134/3886] Makefile.mk: Remove "crt0" dead code
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Also removes some dead code below which uses a dongle.py binary.

Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: Ia9b31a79f7637d31bbd824a8f6ad9137df429711
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90818
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 Documentation/POSTCODES                               | 2 +-
 Documentation/acronyms.md                             | 1 -
 Makefile.mk                                           | 7 -------
 src/arch/x86/Kconfig                                  | 2 +-
 src/commonlib/include/commonlib/console/post_codes.h  | 2 +-
 src/soc/amd/common/block/cpu/car/cache_as_ram.S       | 2 +-
 src/soc/intel/common/block/cpu/car/cache_as_ram_fsp.S | 2 +-
 7 files changed, 5 insertions(+), 13 deletions(-)

diff --git a/Documentation/POSTCODES b/Documentation/POSTCODES
index 0e67dd173c..8240375e11 100644
--- a/Documentation/POSTCODES
+++ b/Documentation/POSTCODES
@@ -5,7 +5,7 @@ coreboot POST Codes
 This is an (incomplete) list of POST codes emitted by coreboot v4.
 
 0x10 Entry into protected mode
-0x01 Entry into 'crt0.s' reset code jumps to here
+0x01 Entry into 'entry16.S' reset code jumps to here
 0x11 Start copying coreboot to RAM with decompression if compressed
 0x12 Copy/decompression finished jumping to RAM
 0x80 Entry into coreboot in RAM
diff --git a/Documentation/acronyms.md b/Documentation/acronyms.md
index 199a7da78c..a52d206636 100644
--- a/Documentation/acronyms.md
+++ b/Documentation/acronyms.md
@@ -204,7 +204,6 @@ Spec](https://uefi.org/specifications) for details, or run the tool
 * CRLF - Carriage Return, Line Feed - \\r\\n - The standard window EOL
   (End-of-Line) marker.
 * crt0 - [**C Run Time 0**](https://en.wikipedia.org/wiki/Crt0)
-* crt0s - crt0 Source code
 * CRT - [**Cathode Ray Tube**](https://en.wikipedia.org/wiki/Cathode-ray_tube)
 * CSE - Intel: Converged Security Engine
 * CSI - MIPI: [**Camera Serial
diff --git a/Makefile.mk b/Makefile.mk
index e83a304ca6..92098ba1b7 100644
--- a/Makefile.mk
+++ b/Makefile.mk
@@ -822,13 +822,6 @@ clean-abuild:
 
 #######################################################################
 # Development utilities
-printcrt0s:
-	@echo crt0s=$(crt0s)
-	@echo ldscripts=$(ldscripts)
-
-update:
-	dongle.py -c /dev/term/1 $(obj)/coreboot.rom EOF
-
 check-style:
 	grep "^# DESCR:" util/lint/check-style | sed "s,.*DESCR: *,,"
 	echo "========"
diff --git a/src/arch/x86/Kconfig b/src/arch/x86/Kconfig
index b58907e230..8e6babceb3 100644
--- a/src/arch/x86/Kconfig
+++ b/src/arch/x86/Kconfig
@@ -185,7 +185,7 @@ config BOOTBLOCK_DEBUG_SPINLOOP
 	bool
 	default n
 	help
-	  Add a spin (JMP .) in bootblock_crt0.S during early bootblock to wait
+	  Add a spin (JMP .) in entry32.S during early bootblock to wait
 	  for a JTAG debugger to break into the execution sequence.
 
 config HAVE_CMOS_DEFAULT
diff --git a/src/commonlib/include/commonlib/console/post_codes.h b/src/commonlib/include/commonlib/console/post_codes.h
index d581bc487f..b0f9565e35 100644
--- a/src/commonlib/include/commonlib/console/post_codes.h
+++ b/src/commonlib/include/commonlib/console/post_codes.h
@@ -34,7 +34,7 @@
 #define POSTCODE_CODE_CLEAR				0x00
 
 /**
- * \brief  Entry into 'crt0.s'. reset code jumps to here
+ * \brief  Entry into 'entry16.S'. reset code jumps to here
  *
  * First instruction that gets executed after the reset vector jumps.
  * This indicates that the reset vector points to the correct code segment.
diff --git a/src/soc/amd/common/block/cpu/car/cache_as_ram.S b/src/soc/amd/common/block/cpu/car/cache_as_ram.S
index 8d41826bfd..9411ad0a6f 100644
--- a/src/soc/amd/common/block/cpu/car/cache_as_ram.S
+++ b/src/soc/amd/common/block/cpu/car/cache_as_ram.S
@@ -3,7 +3,7 @@
 /******************************************************************************
  * $Workfile:: cache_as_ram.S
  *
- * Description: CAR setup called from bootblock_crt0.S.
+ * Description: CAR setup called from entry32.S.
  *
  ******************************************************************************
  */
diff --git a/src/soc/intel/common/block/cpu/car/cache_as_ram_fsp.S b/src/soc/intel/common/block/cpu/car/cache_as_ram_fsp.S
index ed735dbce3..1e55039a3c 100644
--- a/src/soc/intel/common/block/cpu/car/cache_as_ram_fsp.S
+++ b/src/soc/intel/common/block/cpu/car/cache_as_ram_fsp.S
@@ -90,7 +90,7 @@ CAR_init_done:
 	or	%rsi, %rdi
 	andl	$0xfffffff0, %esp
 #else
-	/* Restore the timestamp from bootblock_crt0.S (ebp:mm1) */
+	/* Restore the timestamp from entry32.S (ebp:mm1) */
 	push	%ebp
 	movd	%mm1, %eax
 	push	%eax

From aa77ddb44aa4f400d0ed17b5c3eb929ca00d7419 Mon Sep 17 00:00:00 2001
From: Chen-Tsung Hsieh <chentsung@chromium.org>
Date: Fri, 23 Jan 2026 08:42:23 +0000
Subject: [PATCH 3135/3886] soc/mediatek/common: Combine dsi_cmdq_size register
 writes

Combine the size calculation and the CMDQ_SIZE_SEL bit setting into a
single write32 call for dsi->dsi_cmdq_size to optimize register access.

BUG=b:474187570
TEST=util/abuild/abuild -x -t GOOGLE_SKYWALKER -a --clean
BRANCH=skywalker

Change-Id: Idd08c8fab4120878c53fb94bf0e3cddb9a7eb513
Signed-off-by: Chen-Tsung Hsieh <chentsung@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90874
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
---
 src/soc/mediatek/common/dsi_common.c | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/src/soc/mediatek/common/dsi_common.c b/src/soc/mediatek/common/dsi_common.c
index b2df010a48..6f8d640845 100644
--- a/src/soc/mediatek/common/dsi_common.c
+++ b/src/soc/mediatek/common/dsi_common.c
@@ -421,8 +421,7 @@ static enum cb_err mtk_dsi_cmdq(enum mipi_dsi_transaction type, const u8 *data,
 		}
 		buffer_to_fifo32_prefix(tx_buf, prefix, prefsz, prefsz + len, &dsi->dsi_cmdq[0],
 					4, 4);
-		write32(&dsi->dsi_cmdq_size, DIV_ROUND_UP(prefsz + len, 4));
-		setbits32(&dsi->dsi_cmdq_size, CMDQ_SIZE_SEL);
+		write32(&dsi->dsi_cmdq_size, DIV_ROUND_UP(prefsz + len, 4) | CMDQ_SIZE_SEL);
 	}
 
 	mtk_dsi_enable_and_start(is_dsi_dual_channel);

From 97d9c985ce6b30b25edbabe641b2665ab2fd560d Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Fri, 23 Jan 2026 11:22:07 -0600
Subject: [PATCH 3136/3886] soc/intel/{mtl,ptl}/fsp_params: Program
 PcieRpDetectTimeoutMs
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

This UPD is programmed for ADL, but not MTL and PTL. Add it to the
latter two so it functions as expected when set in devicetree for a
given PCIe root port.

TEST=build/boot Starlabs Starfighter MTL, verify Samsung NVMe drive
reliably detected in PCH-attached socket when timeout increased.

Change-Id: Iea744fed987d413c6487559005d668329a05fff4
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90877
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
---
 src/soc/intel/meteorlake/fsp_params.c  | 1 +
 src/soc/intel/pantherlake/fsp_params.c | 1 +
 2 files changed, 2 insertions(+)

diff --git a/src/soc/intel/meteorlake/fsp_params.c b/src/soc/intel/meteorlake/fsp_params.c
index 61be03ad47..5e7bdc53ab 100644
--- a/src/soc/intel/meteorlake/fsp_params.c
+++ b/src/soc/intel/meteorlake/fsp_params.c
@@ -641,6 +641,7 @@ static void fill_fsps_pcie_params(FSP_S_CONFIG *s_cfg,
 		s_cfg->PcieRpHotPlug[i] = !!(rp_cfg->flags & PCIE_RP_HOTPLUG)
 				|| CONFIG(SOC_INTEL_COMPLIANCE_TEST_MODE);
 		s_cfg->PcieRpClkReqDetect[i] = !!(rp_cfg->flags & PCIE_RP_CLK_REQ_DETECT);
+		s_cfg->PcieRpDetectTimeoutMs[i] = rp_cfg->pcie_rp_detect_timeout_ms;
 		configure_pch_rp_power_management(s_cfg, rp_cfg, i);
 	}
 	s_cfg->PcieComplianceTestMode = CONFIG(SOC_INTEL_COMPLIANCE_TEST_MODE);
diff --git a/src/soc/intel/pantherlake/fsp_params.c b/src/soc/intel/pantherlake/fsp_params.c
index 0133e72c00..2fbcbea5b9 100644
--- a/src/soc/intel/pantherlake/fsp_params.c
+++ b/src/soc/intel/pantherlake/fsp_params.c
@@ -639,6 +639,7 @@ static void fill_fsps_pcie_params(FSP_S_CONFIG *s_cfg,
 		s_cfg->PcieRpHotPlug[i] =
 			!!(rp_cfg->flags & PCIE_RP_HOTPLUG) || CONFIG(SOC_INTEL_COMPLIANCE_TEST_MODE);
 		s_cfg->PcieRpClkReqDetect[i] = !!(rp_cfg->flags & PCIE_RP_CLK_REQ_DETECT);
+		s_cfg->PcieRpDetectTimeoutMs[i] = rp_cfg->pcie_rp_detect_timeout_ms;
 		if (rp_cfg->pcie_rp_aspm)
 			s_cfg->PcieRpAspm[i] = get_aspm_control(rp_cfg->pcie_rp_aspm);
 	}

From 673ce1845e7b78fb21bdfbaac73fca306bff3c68 Mon Sep 17 00:00:00 2001
From: Patrick Rudolph <patrick.rudolph@9elements.com>
Date: Sun, 11 Jan 2026 09:44:29 +0100
Subject: [PATCH 3137/3886] ec/lenovo/h8: Cache EC version string

When APM_CNT_ACPI_DISABLE is issued during LPC init it will
enable SMI's when the EC asserts the GPE_EC_SCI GPIO, looking like:

[NOTE ]  coreboot-25.12 x86_64 smm starting (log level: 6)...
[DEBUG]  GPI (mask 0002)

This happens on all ec_read() calls whenever bits in the status
register change, causing lots of unnecessary SMIs at boot.

Cache the EC version string when it's first read and use the
cached version when writing SMBIOS tables.
While on it introduce defines for registers and drop function
from global scope.

TEST=Seen less SMIs during boot. Version string is still correctly
     shown in dmidecode.

Change-Id: I514c628947c4e14f2379f7e2f265f28a9c7086d6
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90722
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
---
 src/ec/lenovo/h8/h8.c | 56 +++++++++++++++++++++++--------------------
 src/ec/lenovo/h8/h8.h |  9 ++++++-
 2 files changed, 38 insertions(+), 27 deletions(-)

diff --git a/src/ec/lenovo/h8/h8.c b/src/ec/lenovo/h8/h8.c
index acf5ce5408..564ba85b89 100644
--- a/src/ec/lenovo/h8/h8.c
+++ b/src/ec/lenovo/h8/h8.c
@@ -81,6 +81,34 @@ static void f1_to_f12_as_primary(int on)
 		ec_clr_bit(0x3b, 3);
 }
 
+static u8 h8_build_id_and_function_spec_version(char *buf, u8 buf_len)
+{
+	static char str[16 + 1]; /* 16 ASCII chars + \0 */
+	u8 i, c;
+
+	if (!str[0]) {
+		/* Build ID */
+		for (i = 0; i < 8; i++) {
+			c = ec_read(H8_EC_BUILD_ID + i);
+			if (c < 0x20 || c > 0x7f) {
+				i = snprintf(str, sizeof(str), "*INVALID");
+				break;
+			}
+			str[i] = c;
+		}
+
+		/* Lenovo EC firmware function specification version */
+		i += snprintf(str + i, sizeof(str) - i, "-%u.%u",
+			ec_read(H8_EC_FUNC_MAJOR_VER), ec_read(H8_EC_FUNC_MINOR_VER));
+	} else
+		i = strlen(str);
+
+	i = MIN(buf_len, i);
+	memcpy(buf, str, i);
+
+	return i;
+}
+
 static void h8_log_ec_version(void)
 {
 	char ecfw[17];
@@ -90,8 +118,8 @@ static void h8_log_ec_version(void)
 	len = h8_build_id_and_function_spec_version(ecfw, sizeof(ecfw) - 1);
 	ecfw[len] = 0;
 
-	fwvh = ec_read(0xe9);
-	fwvl = ec_read(0xe8);
+	fwvh = ec_read(H8_EC_FIRMWARE_MAJOR_VER);
+	fwvl = ec_read(H8_EC_FIRMWARE_MINOR_VER);
 
 	printk(BIOS_INFO, "H8: EC Firmware ID %s, Version %d.%d%d%c\n", ecfw,
 	       fwvh >> 4, fwvh & 0x0f, fwvl >> 4, 0x41 + (fwvl & 0xf));
@@ -162,30 +190,6 @@ int h8_ultrabay_device_present(void)
 	return ec_read(H8_STATUS1) & 0x5 ? 0 : 1;
 }
 
-u8 h8_build_id_and_function_spec_version(char *buf, u8 buf_len)
-{
-	u8 i, c;
-	char str[16 + 1]; /* 16 ASCII chars + \0 */
-
-	/* Build ID */
-	for (i = 0; i < 8; i++) {
-		c = ec_read(0xf0 + i);
-		if (c < 0x20 || c > 0x7f) {
-			i = snprintf(str, sizeof(str), "*INVALID");
-			break;
-		}
-		str[i] = c;
-	}
-
-	/* EC firmware function specification version */
-	i += snprintf(str + i, sizeof(str) - i, "-%u.%u", ec_read(0xef), ec_read(0xeb));
-
-	i = MIN(buf_len, i);
-	memcpy(buf, str, i);
-
-	return i;
-}
-
 #if CONFIG(GENERATE_SMBIOS_TABLES)
 static void h8_smbios_strings(struct device *dev, struct smbios_type11 *t)
 {
diff --git a/src/ec/lenovo/h8/h8.h b/src/ec/lenovo/h8/h8.h
index 40816117b1..88d7b07136 100644
--- a/src/ec/lenovo/h8/h8.h
+++ b/src/ec/lenovo/h8/h8.h
@@ -20,7 +20,6 @@ void h8_usb_power_enable(int on);
 void h8_enable_event(int event);
 void h8_disable_event(int event);
 int h8_ultrabay_device_present(void);
-u8 h8_build_id_and_function_spec_version(char *buf, u8 buf_len);
 void h8_usb_always_on(void);
 
 int h8_get_fn_key(void);
@@ -141,4 +140,12 @@ void h8_mb_init(void);
 #define H8_EVENT_FN_F5			0x64
 #define H8_EVENT_FN_F6			0x65
 
+#define H8_EC_FIRMWARE_MINOR_VER	0xe8
+#define H8_EC_FIRMWARE_MAJOR_VER	0xe9
+
+#define H8_EC_FUNC_MINOR_VER		0xeb
+#define H8_EC_FUNC_MAJOR_VER		0xef
+
+#define H8_EC_BUILD_ID			0xf0
+
 #endif /* EC_LENOVO_H8_H */

From e98bc0e02ab2f4f2a5189090536e46c544b0bb5e Mon Sep 17 00:00:00 2001
From: Patrick Rudolph <patrick.rudolph@9elements.com>
Date: Sun, 11 Jan 2026 11:37:06 +0100
Subject: [PATCH 3138/3886] ec/lenovo/h8: Properly advertised used I/O

Properly advertise I/O ports decoded by H8 and PMH7. Therefore
implement read_resources() and set_resources() in coreboot and
advertise the ports using ACPI.

TEST=I/O ports are properly seen as fixed and assigned in
     coreboot and the OS.

Change-Id: Iae1b72d2d565750020f2943804165b9d5d2efdfb
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90723
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/ec/lenovo/h8/acpi/ec.asl | 49 ++++++++++++++++++++++++++++++++++++
 src/ec/lenovo/h8/h8.c        | 11 ++++++++
 src/ec/lenovo/pmh7/pmh7.c    | 21 ++++++++++------
 src/ec/lenovo/pmh7/pmh7.h    |  2 --
 4 files changed, 74 insertions(+), 9 deletions(-)

diff --git a/src/ec/lenovo/h8/acpi/ec.asl b/src/ec/lenovo/h8/acpi/ec.asl
index bc54d3b422..fe39c19761 100644
--- a/src/ec/lenovo/h8/acpi/ec.asl
+++ b/src/ec/lenovo/h8/acpi/ec.asl
@@ -335,3 +335,52 @@ Device(EC)
 #include "systemstatus.asl"
 #include "thinkpad.asl"
 }
+
+#if CONFIG(EC_LENOVO_H8)
+// EC SMM interface
+Device(ECMM)
+{
+	Name (_HID, EISAID("PNP0C02"))
+	Name (_UID, 10)
+
+	Name (_CRS, ResourceTemplate() {
+		IO (Decode16, 0x1600, 0x1600, 1, 1)
+		IO (Decode16, 0x1604, 0x1604, 1, 1)
+	})
+}
+
+// EC Gravity sensor interface
+Device(ECGS)
+{
+	Name (_HID, EISAID("PNP0C02"))
+	Name (_UID, 11)
+
+	Name (_CRS, ResourceTemplate() {
+		IO (Decode16, 0x1602, 0x1602, 1, 1)
+		IO (Decode16, 0x1606, 0x1606, 1, 1)
+	})
+}
+
+// Battery two wire interface
+Device(TWRI)
+{
+	Name (_HID, EISAID("PNP0C02"))
+	Name (_UID, 12)
+
+	Name (_CRS, ResourceTemplate() {
+		IO (Decode16, 0x1610, 0x1610, 16, 16)
+	})
+}
+#endif
+
+#if CONFIG(EC_LENOVO_PMH7)
+Device(PMH7)
+{
+	Name (_HID, EISAID("PNP0C02"))
+	Name (_UID, 13)
+
+	Name (_CRS, ResourceTemplate() {
+		IO (Decode16, 0x15e0, 0x15e0, 16, 16)
+	})
+}
+#endif
diff --git a/src/ec/lenovo/h8/h8.c b/src/ec/lenovo/h8/h8.c
index 564ba85b89..1ea3ccfa40 100644
--- a/src/ec/lenovo/h8/h8.c
+++ b/src/ec/lenovo/h8/h8.c
@@ -213,6 +213,15 @@ static const char *h8_acpi_name(const struct device *dev)
 }
 #endif
 
+static void h8_read_resources(struct device *dev)
+{
+	static const u16 ports[] = {0x60, 0x64, 0x62, 0x66, 0x1600, 0x1604, 0x1602, 0x1606};
+	for (int i = 0; i < ARRAY_SIZE(ports); i++)
+		fixed_io_range_flags(dev, ports[i], ports[i], 1, IORESOURCE_ASSIGNED);
+
+	fixed_io_range_flags(dev, 0x1610, 0x1610, 16, IORESOURCE_ASSIGNED);
+}
+
 struct device_operations h8_dev_ops = {
 #if CONFIG(GENERATE_SMBIOS_TABLES)
 	.get_smbios_strings = h8_smbios_strings,
@@ -221,6 +230,8 @@ struct device_operations h8_dev_ops = {
 	.acpi_fill_ssdt = h8_ssdt_generator,
 	.acpi_name = h8_acpi_name,
 #endif
+	.read_resources	= h8_read_resources,
+	.set_resources	= noop_set_resources,
 	.init = h8_init,
 };
 
diff --git a/src/ec/lenovo/pmh7/pmh7.c b/src/ec/lenovo/pmh7/pmh7.c
index 95502f3d88..00d34edb56 100644
--- a/src/ec/lenovo/pmh7/pmh7.c
+++ b/src/ec/lenovo/pmh7/pmh7.c
@@ -101,17 +101,23 @@ void pmh7_register_write(int reg, int val)
 	outb(val, EC_LENOVO_PMH7_DATA);
 }
 
+#if ENV_RAMSTAGE
+static void pmh7_read_resources(struct device *dev)
+{
+	fixed_io_range_flags(dev, EC_LENOVO_PMH7_BASE, EC_LENOVO_PMH7_BASE,
+			     16, IORESOURCE_ASSIGNED);
+}
+
+struct device_operations pmh7_dev_ops = {
+	.read_resources	= pmh7_read_resources,
+	.set_resources	= noop_set_resources,
+};
+
 static void enable_dev(struct device *dev)
 {
 	const struct ec_lenovo_pmh7_config *conf = dev->chip_info;
-	struct resource *resource;
 
-	resource = new_resource(dev, EC_LENOVO_PMH7_INDEX);
-	resource->base = EC_LENOVO_PMH7_BASE;
-	resource->size = 16;
-	resource->align = 5;
-	resource->gran = 5;
-	resource->flags = IORESOURCE_IO | IORESOURCE_FIXED | IORESOURCE_ASSIGNED;
+	dev->ops = &pmh7_dev_ops;
 
 	pmh7_backlight_enable(conf->backlight_enable);
 	pmh7_dock_event_enable(conf->dock_event_enable);
@@ -129,3 +135,4 @@ struct chip_operations ec_lenovo_pmh7_ops = {
 	.name = "Lenovo Power Management Hardware Hub 7",
 	.enable_dev = enable_dev,
 };
+#endif
diff --git a/src/ec/lenovo/pmh7/pmh7.h b/src/ec/lenovo/pmh7/pmh7.h
index 61dc1137d3..b06e79920d 100644
--- a/src/ec/lenovo/pmh7/pmh7.h
+++ b/src/ec/lenovo/pmh7/pmh7.h
@@ -5,8 +5,6 @@
 
 #include <stdbool.h>
 
-#define EC_LENOVO_PMH7_INDEX 0x77
-
 #define EC_LENOVO_PMH7_BASE 0x15e0
 #define EC_LENOVO_PMH7_ADDR_L (EC_LENOVO_PMH7_BASE + 0x0c)
 #define EC_LENOVO_PMH7_ADDR_H (EC_LENOVO_PMH7_BASE + 0x0d)

From bb299bb530f1bd01e346f6ba6cd6f59b2bacb7cc Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Fri, 23 Jan 2026 12:20:11 -0600
Subject: [PATCH 3139/3886] mb/starlabs/starfighter/mtl: Add detection delay to
 PCH-attached SSD
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Some SSDs connected to the PCH-attached PCIe root port/m.2 socket need
a small delay in order to be reliably detected. Add a 15ms delay (the
default is 0) to ensure this.

TEST=build/boot Starfighter MTL 125H/285H with Samsung 970 EVO plus,
WD SN720, and Intel Optane P1600x SSDs in outer SSD socket. Ensure
all drives detected and bootable after both cold and warm resets.

Change-Id: I16ec0a313fc7cccb2807593c07db04cdbb59c979
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90880
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
---
 src/mainboard/starlabs/starfighter/variants/mtl/devicetree.cb | 1 +
 1 file changed, 1 insertion(+)

diff --git a/src/mainboard/starlabs/starfighter/variants/mtl/devicetree.cb b/src/mainboard/starlabs/starfighter/variants/mtl/devicetree.cb
index f83df3e27a..23ad639cc2 100644
--- a/src/mainboard/starlabs/starfighter/variants/mtl/devicetree.cb
+++ b/src/mainboard/starlabs/starfighter/variants/mtl/devicetree.cb
@@ -241,6 +241,7 @@ chip soc/intel/meteorlake
 				.flags					= PCIE_RP_LTR | PCIE_RP_AER,
 				.pcie_rp_aspm				= ASPM_L0S_L1,
 				.PcieRpL1Substates			= L1_SS_L1_2,
+				.pcie_rp_detect_timeout_ms		= 15,
 			}"
 
 			smbios_slot_desc				"SlotTypeM2Socket3"

From 76149f25c64175dfa397e45e7541f1acbd9c6b2d Mon Sep 17 00:00:00 2001
From: Maximilian Brune <maximilian.brune@9elements.com>
Date: Sat, 29 Nov 2025 00:05:03 +0100
Subject: [PATCH 3140/3886] treewide: Rename FMAP_ROM_SIZE -> FMAP_FLASH_SIZE

Its actually the size FMAP flash region so the name is more appropriate.

Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: I152b66abedb68f1ab809d918502efe096e9dde59
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90811
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 Makefile.mk                   | 6 +++---
 util/cbfstool/default-x86.fmd | 4 ++--
 util/cbfstool/default.fmd     | 4 ++--
 util/ifdtool/ifdtool.c        | 2 +-
 4 files changed, 8 insertions(+), 8 deletions(-)

diff --git a/Makefile.mk b/Makefile.mk
index 92098ba1b7..e2b49b36fe 100644
--- a/Makefile.mk
+++ b/Makefile.mk
@@ -1099,7 +1099,7 @@ endif # ifeq($(CONFIG_HAVE_IFD_BIN),y)
 endif # ifneq($(CONFIG_IFD_CHIPSET),)
 
 # entire flash
-FMAP_ROM_SIZE := $(CONFIG_ROM_SIZE)
+FMAP_FLASH_SIZE := $(CONFIG_ROM_SIZE)
 # entire "BIOS" region (everything directly of concern to the host system)
 FMAP_BIOS_BASE := $(call int-align, $(call int-subtract, $(CONFIG_ROM_SIZE) $(CONFIG_CBFS_SIZE)), 0x10000)
 FMAP_BIOS_SIZE := $(call int-align-down, $(shell echo $(CONFIG_CBFS_SIZE) | tr A-F a-f), 0x10000)
@@ -1186,7 +1186,7 @@ else # ifeq ($(CONFIG_ARCH_X86),y)
 
 DEFAULT_FLASHMAP:=$(top)/util/cbfstool/default.fmd
 # entire flash
-FMAP_ROM_SIZE := $(CONFIG_ROM_SIZE)
+FMAP_FLASH_SIZE := $(CONFIG_ROM_SIZE)
 # entire "BIOS" region (everything directly of concern to the host system)
 FMAP_BIOS_BASE := 0
 FMAP_BIOS_SIZE := $(CONFIG_CBFS_SIZE)
@@ -1232,7 +1232,7 @@ FMAP_CBFS_SIZE := $(call int-subtract,$(FMAP_BIOS_SIZE) $(FMAP_CBFS_BASE))
 endif # ifeq ($(CONFIG_ARCH_X86),y)
 
 $(obj)/fmap.fmd: $(top)/Makefile.mk $(DEFAULT_FLASHMAP) $(obj)/config.h
-	sed -e "s,##ROM_SIZE##,$(call _tohex,$(FMAP_ROM_SIZE))," \
+	sed -e "s,##FLASH_SIZE##,$(call _tohex,$(FMAP_FLASH_SIZE))," \
 	    -e "s,##BIOS_BASE##,$(call _tohex,$(FMAP_BIOS_BASE))," \
 	    -e "s,##BIOS_SIZE##,$(call _tohex,$(FMAP_BIOS_SIZE))," \
 	    -e "s,##FMAP_BASE##,$(call _tohex,$(FMAP_FMAP_BASE))," \
diff --git a/util/cbfstool/default-x86.fmd b/util/cbfstool/default-x86.fmd
index 795e025f9f..d0e17b194e 100644
--- a/util/cbfstool/default-x86.fmd
+++ b/util/cbfstool/default-x86.fmd
@@ -1,5 +1,5 @@
 # layout for firmware residing at top of 4GB address space
-# +-------------+ <-- 4GB - ROM_SIZE / start of flash
+# +-------------+ <-- 4GB - FLASH_SIZE / start of flash
 # | unspecified |
 # +-------------+ <-- 4GB - BIOS_SIZE
 # | FMAP        |
@@ -7,7 +7,7 @@
 # | CBFS        |
 # +-------------+ <-- 4GB / end of flash
 
-FLASH ##ROM_SIZE## {
+FLASH ##FLASH_SIZE## {
 	BIOS@##BIOS_BASE## ##BIOS_SIZE## {
 		##CONSOLE_ENTRY##
 		##MRC_CACHE_ENTRY##
diff --git a/util/cbfstool/default.fmd b/util/cbfstool/default.fmd
index d20789f404..97cf441445 100644
--- a/util/cbfstool/default.fmd
+++ b/util/cbfstool/default.fmd
@@ -7,9 +7,9 @@
 # | FMAP        |
 # +-------------+ <-- BIOS_BASE + 128K + FMAP_SIZE
 # | CBFS        |
-# +-------------+ <-- ROM_SIZE
+# +-------------+ <-- FLASH_SIZE
 
-FLASH ##ROM_SIZE## {
+FLASH ##FLASH_SIZE## {
 	BIOS@##BIOS_BASE## ##BIOS_SIZE## {
 		BOOTBLOCK 128K
 		FMAP@##FMAP_BASE## ##FMAP_SIZE##
diff --git a/util/ifdtool/ifdtool.c b/util/ifdtool/ifdtool.c
index 75238c73b2..0592785bf6 100644
--- a/util/ifdtool/ifdtool.c
+++ b/util/ifdtool/ifdtool.c
@@ -1094,7 +1094,7 @@ static void create_fmap_template(char *image, int size, const char *layout_fname
 		exit(EXIT_FAILURE);
 	}
 
-	char *bbuf = "FLASH ##ROM_SIZE## {\n";
+	char *bbuf = "FLASH ##FLASH_SIZE## {\n";
 	if (write(layout_fd, bbuf, strlen(bbuf)) < 0) {
 		perror("Could not write to file");
 		exit(EXIT_FAILURE);

From 5cae481856dd9c89eeecc6ff4cb6157dad84f6a5 Mon Sep 17 00:00:00 2001
From: Maximilian Brune <maximilian.brune@9elements.com>
Date: Sat, 29 Nov 2025 00:13:26 +0100
Subject: [PATCH 3141/3886] Makefile.mk: Use same FMAP_FLASH_SIZE for all
 architectures

For both x86 and non-x86 its the same anyway, so factor it out.

Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: I30e6d1da8a663cd79d59d55446eda2b70269f118
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90812
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
---
 Makefile.mk | 5 ++---
 1 file changed, 2 insertions(+), 3 deletions(-)

diff --git a/Makefile.mk b/Makefile.mk
index e2b49b36fe..14f9b835d7 100644
--- a/Makefile.mk
+++ b/Makefile.mk
@@ -1085,6 +1085,8 @@ prebuild-files = $(foreach region,$(all-regions), \
 # If no FMD file (Flashmap) is supplied by mainboard, fall back to a default
 ifeq ($(CONFIG_FMDFILE),)
 
+FMAP_FLASH_SIZE := $(CONFIG_ROM_SIZE)
+
 ifeq ($(CONFIG_ARCH_X86),y)
 
 DEFAULT_FLASHMAP:=$(top)/util/cbfstool/default-x86.fmd
@@ -1098,8 +1100,6 @@ $(DEFAULT_FLASHMAP): $(call strip_quotes,$(CONFIG_IFD_BIN_PATH)) $(IFDTOOL)
 endif # ifeq($(CONFIG_HAVE_IFD_BIN),y)
 endif # ifneq($(CONFIG_IFD_CHIPSET),)
 
-# entire flash
-FMAP_FLASH_SIZE := $(CONFIG_ROM_SIZE)
 # entire "BIOS" region (everything directly of concern to the host system)
 FMAP_BIOS_BASE := $(call int-align, $(call int-subtract, $(CONFIG_ROM_SIZE) $(CONFIG_CBFS_SIZE)), 0x10000)
 FMAP_BIOS_SIZE := $(call int-align-down, $(shell echo $(CONFIG_CBFS_SIZE) | tr A-F a-f), 0x10000)
@@ -1186,7 +1186,6 @@ else # ifeq ($(CONFIG_ARCH_X86),y)
 
 DEFAULT_FLASHMAP:=$(top)/util/cbfstool/default.fmd
 # entire flash
-FMAP_FLASH_SIZE := $(CONFIG_ROM_SIZE)
 # entire "BIOS" region (everything directly of concern to the host system)
 FMAP_BIOS_BASE := 0
 FMAP_BIOS_SIZE := $(CONFIG_CBFS_SIZE)

From 23410a873a323fd0ca6a804fa555d05abf3087e6 Mon Sep 17 00:00:00 2001
From: Yu-Ping Wu <yupingso@chromium.org>
Date: Fri, 23 Jan 2026 15:29:48 +0800
Subject: [PATCH 3142/3886] assert.h: Remove printk dependency for ENV_TEST

With the current implementation of assert() for ENV_TEST, the printk()
function must be linked. As we are already using cmocka's mock_assert()
implementation for unit tests, those printk() calls within
assert-related macros should be changed to no-ops.

Also, disable __build_time_assert() for ENV_TEST.

Change-Id: Ia9bea29a32362d68dff89bb7bbf417126ac31fb7
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90870
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/include/assert.h | 26 ++++++++++++++------------
 1 file changed, 14 insertions(+), 12 deletions(-)

diff --git a/src/include/assert.h b/src/include/assert.h
index 0e09eef392..19d041010f 100644
--- a/src/include/assert.h
+++ b/src/include/assert.h
@@ -22,7 +22,7 @@
 #define __ASSERT_LINE__ __LINE__
 #endif
 
-#ifndef _PORTING_H_	/* TODO: Isolate AGESA properly. */
+#if !ENV_TEST && !defined(_PORTING_H_)	/* TODO: Isolate AGESA properly. */
 #define __build_time_assert(x) \
 	(__builtin_constant_p(x) ? ((x) ? 1 : dead_code_t(int)) : 0)
 #else
@@ -34,11 +34,13 @@ void mock_assert(const int result, const char *const expression,
 		const char *const file, const int line);
 
 #if ENV_TEST
-#define MOCK_ASSERT(result, expression) \
+#define _ASSERT_MSG(...)
+#define _MOCK_ASSERT(result, expression) \
 	mock_assert((result), (expression), __ASSERT_FILE__, __ASSERT_LINE__)
-#else
-#define MOCK_ASSERT(result, expression)
-#endif
+#else /* ENV_TEST */
+#define _ASSERT_MSG(...) printk(BIOS_EMERG, __VA_ARGS__)
+#define _MOCK_ASSERT(result, expression)
+#endif /* ENV_TEST */
 
 /*
  * assert() should be used to test stuff that the programmer *knows* to be true.
@@ -54,30 +56,30 @@ void mock_assert(const int result, const char *const expression,
  */
 #define ASSERT(x) {							\
 	if (!__build_time_assert(x) && !(x)) {				\
-		printk(BIOS_EMERG,					\
+		_ASSERT_MSG(						\
 			"ASSERTION ERROR: file '%s', line %d\n",	\
 			__ASSERT_FILE__, __ASSERT_LINE__);		\
-		MOCK_ASSERT(!!(x), #x);					\
+		_MOCK_ASSERT(!!(x), #x);					\
 		if (CONFIG(FATAL_ASSERTS))				\
 			hlt();						\
 	}								\
 }
 #define ASSERT_MSG(x, msg) {						\
 	if (!__build_time_assert(x) && !(x)) {				\
-		printk(BIOS_EMERG,					\
+		_ASSERT_MSG(						\
 			"ASSERTION ERROR: file '%s', line %d\n",	\
 			__ASSERT_FILE__, __ASSERT_LINE__);		\
-		printk(BIOS_EMERG, "%s", msg);				\
-		MOCK_ASSERT(!!(x), (msg));				\
+		_ASSERT_MSG("%s", msg);					\
+		_MOCK_ASSERT(!!(x), (msg));					\
 		if (CONFIG(FATAL_ASSERTS))				\
 			hlt();						\
 	}								\
 }
 #define BUG() {								\
-	printk(BIOS_EMERG,						\
+	_ASSERT_MSG(							\
 		"ERROR: BUG ENCOUNTERED at file '%s', line %d\n",	\
 		__ASSERT_FILE__, __ASSERT_LINE__);			\
-	MOCK_ASSERT(0, "BUG ENCOUNTERED");				\
+	_MOCK_ASSERT(0, "BUG ENCOUNTERED");				\
 	if (CONFIG(FATAL_ASSERTS))					\
 		hlt();							\
 }

From 54e7b5734f915860e55a1e6240986261b29e84e6 Mon Sep 17 00:00:00 2001
From: Subrata Banik <subratabanik@google.com>
Date: Sun, 25 Jan 2026 07:52:55 +0000
Subject: [PATCH 3143/3886] soc/qualcomm/x1p42100: Add 75MHz configuration for
 QSPI core

Add a new frequency entry to the QSPI core clock configuration table
to support 75MHz (75 * 4 = 300MHz).

This is achieved by using the GPLL0 600MHz source with a divisor of 2.

Providing a 300MHz core clock allows for more granular control over
the physical bus speed (SCK). Specifically, it enables a stable 75MHz
SPI bus frequency via a clean 1/4 divider, which is an optimization
target for improving boot times on Bluey/Quenbi platforms.

BUG=b:478226455
TEST=Verified that 'clock_configure_qspi' can correctly look up and
set the 300MHz frequency in romstage.

Change-Id: I5320a68ff50a0d79daa2fc855b18b0f3ae819bbe
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90886
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Derek Huang <derekhuang@google.com>
---
 src/soc/qualcomm/x1p42100/clock.c | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/src/soc/qualcomm/x1p42100/clock.c b/src/soc/qualcomm/x1p42100/clock.c
index c2566c5d5b..eba4987217 100644
--- a/src/soc/qualcomm/x1p42100/clock.c
+++ b/src/soc/qualcomm/x1p42100/clock.c
@@ -28,6 +28,11 @@ static struct clock_freq_config qspi_core_cfg[] = {
 		.src = SRC_GPLL0_MAIN_600MHZ,
 		.div = QCOM_CLOCK_DIV(3),
 	},
+	{
+		.hz = 300 * MHz,
+		.src = SRC_GPLL0_MAIN_600MHZ,
+		.div = QCOM_CLOCK_DIV(2),
+	},
 	{
 		.hz = 400 * MHz,
 		.src = SRC_GPLL0_MAIN_600MHZ,

From c31c194228f5370f91825d7beef6878ddd1dae99 Mon Sep 17 00:00:00 2001
From: Subrata Banik <subratabanik@google.com>
Date: Sun, 25 Jan 2026 07:54:41 +0000
Subject: [PATCH 3144/3886] soc/qualcomm/x1p42100: Increase SPI bus frequency
 to 75MHz

Boost the SPI bus clock frequency from 50MHz to 75MHz in the
bootblock early initialization.

This increase reduces the latency for loading subsequent stages
(romstage/ramstage) from the SPI flash. Since the QSPI core
can now be configured to 300MHz, this 75MHz bus speed
maintains a stable 1:4 integer divider ratio, ensuring optimal
signal integrity and timing margins for the flash interface.

BUG=b:478226455
TEST=Verified successful boot on Bluey. Observed a reduction (10ms)
in 'read SPI' duration in the console logs and confirmed that the
vboot hash verification passes consistently.

Change-Id: Idea0dbdd435cbbfe22a756d2b94b1cdfa3c70ffe
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90887
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Derek Huang <derekhuang@google.com>
---
 src/soc/qualcomm/x1p42100/bootblock.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/soc/qualcomm/x1p42100/bootblock.c b/src/soc/qualcomm/x1p42100/bootblock.c
index d106912de7..44641397d2 100644
--- a/src/soc/qualcomm/x1p42100/bootblock.c
+++ b/src/soc/qualcomm/x1p42100/bootblock.c
@@ -5,7 +5,7 @@
 #include <soc/qspi_common.h>
 #include <soc/qupv3_config_common.h>
 
-#define SPI_BUS_CLOCK_FREQ (50 * MHz)
+#define SPI_BUS_CLOCK_FREQ (75 * MHz)
 
 void bootblock_soc_early_init(void)
 {

From 4fa14338efa95c25d83176fd6afaef1c42d22d41 Mon Sep 17 00:00:00 2001
From: Subrata Banik <subratabanik@google.com>
Date: Sun, 25 Jan 2026 07:55:47 +0000
Subject: [PATCH 3145/3886] soc/qualcomm/x1p42100: Align and expand DMA and
 stack regions

Fix the 4K alignment for PRERAM_DMA_COHERENT and adjust the post-RAM
memory layout to ensure page-aligned boundaries.

- Shift PRERAM_DMA_COHERENT from 0x14857000 to 0x14858000. This 4K
  alignment is required for the MMU to correctly apply uncached
  attributes without overlapping adjacent regions.
- Increase POSTRAM_STACK from 16K to 32K to provide more headroom
  for complex ramstage operations.
- Shift and expand POSTRAM_DMA_COHERENT to 0x8000C000 (16K). This
  ensures the coherent region starts on a 4K boundary after the
  expanded stack, preventing cache coherency issues.

This alignment fix resolves intermittent SPI DMA failures and hash
mismatches observed when the DMA engine was handed unaligned
buffer addresses.

BUG=b:477842629
TEST=Verified successful boot on Bluey; confirmed SPI read
stability and vboot verification pass.

Change-Id: Ic5f813e4722d732c122186897abf845e4060db37
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90888
Reviewed-by: Derek Huang <derekhuang@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/soc/qualcomm/x1p42100/memlayout.ld | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/src/soc/qualcomm/x1p42100/memlayout.ld b/src/soc/qualcomm/x1p42100/memlayout.ld
index 1c2865a5c8..c3d79b8890 100644
--- a/src/soc/qualcomm/x1p42100/memlayout.ld
+++ b/src/soc/qualcomm/x1p42100/memlayout.ld
@@ -215,7 +215,7 @@ SECTIONS
 	TTB(0x14842000, 56K)
 	PRERAM_STACK(0x14850000, 16K)
 	VBOOT2_WORK(0x14854000, 12K)
-	PRERAM_DMA_COHERENT(0x14857000, 8K)
+	PRERAM_DMA_COHERENT(0x14858000, 8K)
 	REGION(qclib_serial_log, 0x1485B000, 4K, 4K)
 	CBFS_MCACHE(0x1485C000,16K)
 	FMAP_CACHE(0x14860400, 2K)
@@ -236,8 +236,8 @@ SECTIONS
 	REGION(shrm, 0x24040000, 128K , 4K)
 
 	DRAM_START(0x80000000)
-	POSTRAM_STACK(0x80000000, 16K)
-	POSTRAM_DMA_COHERENT(0x80004000, 8K)
+	POSTRAM_STACK(0x80000000, 32K)
+	POSTRAM_DMA_COHERENT(0x8000C000, 16K)
 	REGION(dram_ncc, 0x80A00000, 0x400000, 4K)
 	REGION(dram_cpucp, 0x80E00000, 0x7A0000, 4K)
 

From c4be70f6ff5379bcaeb7f0d2f17b140c70fc12cf Mon Sep 17 00:00:00 2001
From: Yu-Ping Wu <yupingso@chromium.org>
Date: Fri, 9 Jan 2026 16:58:14 +0800
Subject: [PATCH 3146/3886] commonlib/list: Support circular list

In some use cases, we want to add items to the linked list and then
iterate over them with the insertion order. With the current API, the
call site needs to either use the inefficient list_append() function to
append items to the end of the list, or manually maintain a "tail"
node pointer.

To support that use case and make the change backward compatible, add a
helper list_init() function to initialize the list as a circular linked
list. list_init() is automatically called within list_insert_after() and
list_append(). In list_insert_before(), an assertion is added to avoid
an insertion before the head node (which should be invalid). The
implementation ensures that the list is initialized as a circular one
whenever the first element is added. That also allows all call sites to
be auto-upgraded to the "circular list" implementation without any
modification.

Modify list_for_each() to support circular lists, and improve
list_append() efficiency by inserting the new node before the
placeholder head node. Also add a few assertions in the implementation.

Add a new test case to test iterating over an empty list.

Note that '(uintptr_t)ptr + (uintptr_t)offsetof(typeof(*(ptr)), member)'
was used instead of the simpler '&((ptr)->member)' because GCC9+ assumes
that the address can never be NULL. See commit 88991caf00d3
("include/list.h: Add support for GCC9+) for details. Now, with the
new list_for_each() implementation, that pointer value can never be
NULL.

Change-Id: I8451f711d4e522e239c241b3943e00070896dec9
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90799
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/commonlib/include/commonlib/list.h | 21 ++++++--
 src/commonlib/list.c                   | 24 +++++++--
 tests/commonlib/list-test.c            | 70 ++++++++++++++++++--------
 3 files changed, 84 insertions(+), 31 deletions(-)

diff --git a/src/commonlib/include/commonlib/list.h b/src/commonlib/include/commonlib/list.h
index 970d68ea49..7cd3460f8a 100644
--- a/src/commonlib/include/commonlib/list.h
+++ b/src/commonlib/include/commonlib/list.h
@@ -17,14 +17,25 @@ void list_remove(struct list_node *node);
 // Insert list_node node after list_node after in a doubly linked list.
 void list_insert_after(struct list_node *node, struct list_node *after);
 // Insert list_node node before list_node before in a doubly linked list.
+// `before` must not be the placeholder head node.
 void list_insert_before(struct list_node *node, struct list_node *before);
-// Appends the node to the end of the list.
+// Append the node to the end of the list.
 void list_append(struct list_node *node, struct list_node *head);
 
-#define list_for_each(ptr, head, member)                                      \
-	for ((ptr) = container_of((head).next, typeof(*(ptr)), member);       \
-		(uintptr_t)ptr + (uintptr_t)offsetof(typeof(*(ptr)), member); \
-		(ptr) = container_of((ptr)->member.next,                      \
+/*
+ * Explanation of `ptr` initialization:
+ * 1. head.next != NULL: This means the list isn't empty. As the implementation ensures that
+ *    list_init() is called when the very first element is added, we can safely assume that
+ *    the list is circular, and hence set `ptr` to the 1st element.
+ * 2. head.next == NULL: This means the list is empty, and list_init() hasn't been called.
+ *    As the `head` arg might be const, we cannot simply call list_init() here. Instead, we set
+ *    `ptr` to a special value such that `&(ptr->member) == &head`, causing the loop to
+ *    terminate immediately.
+ */
+#define list_for_each(ptr, head, member) \
+	for ((ptr) = container_of((head).next ?: &(head), typeof(*(ptr)), member); \
+		(&((ptr)->member) != &(head)); \
+		(ptr) = container_of((ptr)->member.next, \
 			typeof(*(ptr)), member))
 
 #endif /* __COMMONLIB_LIST_H__ */
diff --git a/src/commonlib/list.c b/src/commonlib/list.c
index b1030c8263..9cbb554b41 100644
--- a/src/commonlib/list.c
+++ b/src/commonlib/list.c
@@ -1,10 +1,22 @@
 /* Taken from depthcharge: src/base/list.c */
 /* SPDX-License-Identifier: GPL-2.0-or-later */
 
+#include <assert.h>
 #include <commonlib/list.h>
 
+// Initialize a circular list, with `head` being a placeholder head node.
+static void list_init(struct list_node *head)
+{
+	if (!head->next) {
+		assert(!head->prev);
+		head->next = head->prev = head;
+	}
+}
+
 void list_remove(struct list_node *node)
 {
+	/* Cannot remove the head node. */
+	assert(node->prev && node->next);
 	if (node->prev)
 		node->prev->next = node->next;
 	if (node->next)
@@ -13,6 +25,9 @@ void list_remove(struct list_node *node)
 
 void list_insert_after(struct list_node *node, struct list_node *after)
 {
+	/* Check uninitialized head node. */
+	if (after->prev == NULL)
+		list_init(after);
 	node->next = after->next;
 	node->prev = after;
 	after->next = node;
@@ -22,6 +37,8 @@ void list_insert_after(struct list_node *node, struct list_node *after)
 
 void list_insert_before(struct list_node *node, struct list_node *before)
 {
+	/* `before` cannot be an uninitialized head node. */
+	assert(before->prev)
 	node->prev = before->prev;
 	node->next = before;
 	before->prev = node;
@@ -31,8 +48,7 @@ void list_insert_before(struct list_node *node, struct list_node *before)
 
 void list_append(struct list_node *node, struct list_node *head)
 {
-	while (head->next)
-		head = head->next;
-
-	list_insert_after(node, head);
+	list_init(head);
+	/* With a circular list, we just need to insert before the head. */
+	list_insert_before(node, head);
 }
diff --git a/tests/commonlib/list-test.c b/tests/commonlib/list-test.c
index 4ca48a468f..eeeeded059 100644
--- a/tests/commonlib/list-test.c
+++ b/tests/commonlib/list-test.c
@@ -1,9 +1,10 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
-#include <tests/test.h>
+#include <commonlib/list.h>
 #include <stdlib.h>
 #include <string.h>
-#include <commonlib/list.h>
+#include <tests/test.h>
+#include <types.h>
 
 struct test_container {
 	int value;
@@ -11,10 +12,20 @@ struct test_container {
 	struct list_node list_node;
 };
 
-void test_list_insert_after(void **state)
+static void test_list_empty(void **state)
+{
+	struct list_node head = {};
+	struct test_container *node;
+
+	list_for_each(node, head, list_node) {
+		assert_true(false);
+	}
+}
+
+static void test_list_insert_after(void **state)
 {
 	int i = 0;
-	struct list_node root = { .prev = NULL, .next = NULL };
+	struct list_node head = {};
 	struct test_container *c1 = (struct test_container *)malloc(sizeof(*c1));
 	struct test_container *c2 = (struct test_container *)malloc(sizeof(*c2));
 	struct test_container *c3 = (struct test_container *)malloc(sizeof(*c2));
@@ -29,11 +40,11 @@ void test_list_insert_after(void **state)
 	c2->value = values[1];
 	c3->value = values[2];
 
-	list_insert_after(&c1->list_node, &root);
+	list_insert_after(&c1->list_node, &head);
 	list_insert_after(&c2->list_node, &c1->list_node);
 	list_insert_after(&c3->list_node, &c2->list_node);
 
-	list_for_each(ptr, root, list_node) {
+	list_for_each(ptr, head, list_node) {
 		assert_int_equal(values[i], ptr->value);
 		i++;
 	}
@@ -45,10 +56,10 @@ void test_list_insert_after(void **state)
 	free(c1);
 }
 
-void test_list_insert_before(void **state)
+static void test_list_insert_before(void **state)
 {
 	int i = 0;
-	struct list_node root = { .prev = NULL, .next = NULL };
+	struct list_node head = {};
 	struct test_container *c1 = (struct test_container *)malloc(sizeof(*c1));
 	struct test_container *c2 = (struct test_container *)malloc(sizeof(*c2));
 	struct test_container *c3 = (struct test_container *)malloc(sizeof(*c2));
@@ -63,12 +74,11 @@ void test_list_insert_before(void **state)
 	c2->value = values[1];
 	c3->value = values[2];
 
-	list_insert_after(&c3->list_node, &root);
+	list_insert_after(&c3->list_node, &head);
 	list_insert_before(&c2->list_node, &c3->list_node);
 	list_insert_before(&c1->list_node, &c2->list_node);
 
-
-	list_for_each(ptr, root, list_node) {
+	list_for_each(ptr, head, list_node) {
 		assert_int_equal(values[i], ptr->value);
 		i++;
 	}
@@ -80,19 +90,27 @@ void test_list_insert_before(void **state)
 	free(c1);
 }
 
-void test_list_remove(void **state)
+static void test_list_insert_before_head(void **state)
 {
-	struct list_node root = { .prev = NULL, .next = NULL };
+	struct list_node head = {};
+	struct test_container c = {};
+
+	expect_assert_failure(list_insert_before(&c.list_node, &head));
+}
+
+static void test_list_remove(void **state)
+{
+	struct list_node head = {};
 	struct test_container *c1 = (struct test_container *)malloc(sizeof(*c1));
 	struct test_container *c2 = (struct test_container *)malloc(sizeof(*c2));
 	struct test_container *ptr;
 	int len;
 
-	list_insert_after(&c1->list_node, &root);
+	list_insert_after(&c1->list_node, &head);
 	list_insert_after(&c2->list_node, &c1->list_node);
 
 	len = 0;
-	list_for_each(ptr, root, list_node) {
+	list_for_each(ptr, head, list_node) {
 		len++;
 	}
 	assert_int_equal(2, len);
@@ -100,14 +118,14 @@ void test_list_remove(void **state)
 	list_remove(&c1->list_node);
 
 	len = 0;
-	list_for_each(ptr, root, list_node) {
+	list_for_each(ptr, head, list_node) {
 		len++;
 	}
 	assert_int_equal(1, len);
 
 	list_remove(&c2->list_node);
 	len = 0;
-	list_for_each(ptr, root, list_node) {
+	list_for_each(ptr, head, list_node) {
 		len++;
 	}
 	assert_int_equal(0, len);
@@ -116,20 +134,26 @@ void test_list_remove(void **state)
 	free(c1);
 }
 
-void test_list_append(void **state)
+static void test_list_remove_head(void **state)
+{
+	struct list_node head = {};
+	expect_assert_failure(list_remove(&head));
+}
+
+static void test_list_append(void **state)
 {
 	size_t idx;
 	struct test_container *node;
-	struct list_node root = {};
+	struct list_node head = {};
 	struct test_container nodes[] = {
 		{1}, {2}, {3}
 	};
 
 	for (idx = 0; idx < ARRAY_SIZE(nodes); ++idx)
-		list_append(&nodes[idx].list_node, &root);
+		list_append(&nodes[idx].list_node, &head);
 
 	idx = 0;
-	list_for_each(node, root, list_node) {
+	list_for_each(node, head, list_node) {
 		assert_ptr_equal(node, &nodes[idx]);
 		idx++;
 	}
@@ -138,12 +162,14 @@ void test_list_append(void **state)
 int main(void)
 {
 	const struct CMUnitTest tests[] = {
+		cmocka_unit_test(test_list_empty),
 		cmocka_unit_test(test_list_insert_after),
 		cmocka_unit_test(test_list_insert_before),
+		cmocka_unit_test(test_list_insert_before_head),
 		cmocka_unit_test(test_list_remove),
+		cmocka_unit_test(test_list_remove_head),
 		cmocka_unit_test(test_list_append),
 	};
 
-
 	return cb_run_group_tests(tests, NULL, NULL);
 }

From 4a5567071d9229595c1fbcf769a32b0bce1a7e8d Mon Sep 17 00:00:00 2001
From: Subrata Banik <subratabanik@google.com>
Date: Tue, 27 Jan 2026 17:13:57 +0000
Subject: [PATCH 3147/3886] Revert "commonlib/list: Support circular list"

This reverts commit c4be70f6ff5379bcaeb7f0d2f17b140c70fc12cf.

Reason for revert: The CL caused a hang in Depthcharge on
Google/Quartz.

BUG=b:479143030
TEST=Verify boot on Google/Quartz.

Change-Id: I38087d0b2dd218dfb32a02c343b199708bb47d49
Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90956
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/commonlib/include/commonlib/list.h | 21 ++------
 src/commonlib/list.c                   | 24 ++-------
 tests/commonlib/list-test.c            | 70 ++++++++------------------
 3 files changed, 31 insertions(+), 84 deletions(-)

diff --git a/src/commonlib/include/commonlib/list.h b/src/commonlib/include/commonlib/list.h
index 7cd3460f8a..970d68ea49 100644
--- a/src/commonlib/include/commonlib/list.h
+++ b/src/commonlib/include/commonlib/list.h
@@ -17,25 +17,14 @@ void list_remove(struct list_node *node);
 // Insert list_node node after list_node after in a doubly linked list.
 void list_insert_after(struct list_node *node, struct list_node *after);
 // Insert list_node node before list_node before in a doubly linked list.
-// `before` must not be the placeholder head node.
 void list_insert_before(struct list_node *node, struct list_node *before);
-// Append the node to the end of the list.
+// Appends the node to the end of the list.
 void list_append(struct list_node *node, struct list_node *head);
 
-/*
- * Explanation of `ptr` initialization:
- * 1. head.next != NULL: This means the list isn't empty. As the implementation ensures that
- *    list_init() is called when the very first element is added, we can safely assume that
- *    the list is circular, and hence set `ptr` to the 1st element.
- * 2. head.next == NULL: This means the list is empty, and list_init() hasn't been called.
- *    As the `head` arg might be const, we cannot simply call list_init() here. Instead, we set
- *    `ptr` to a special value such that `&(ptr->member) == &head`, causing the loop to
- *    terminate immediately.
- */
-#define list_for_each(ptr, head, member) \
-	for ((ptr) = container_of((head).next ?: &(head), typeof(*(ptr)), member); \
-		(&((ptr)->member) != &(head)); \
-		(ptr) = container_of((ptr)->member.next, \
+#define list_for_each(ptr, head, member)                                      \
+	for ((ptr) = container_of((head).next, typeof(*(ptr)), member);       \
+		(uintptr_t)ptr + (uintptr_t)offsetof(typeof(*(ptr)), member); \
+		(ptr) = container_of((ptr)->member.next,                      \
 			typeof(*(ptr)), member))
 
 #endif /* __COMMONLIB_LIST_H__ */
diff --git a/src/commonlib/list.c b/src/commonlib/list.c
index 9cbb554b41..b1030c8263 100644
--- a/src/commonlib/list.c
+++ b/src/commonlib/list.c
@@ -1,22 +1,10 @@
 /* Taken from depthcharge: src/base/list.c */
 /* SPDX-License-Identifier: GPL-2.0-or-later */
 
-#include <assert.h>
 #include <commonlib/list.h>
 
-// Initialize a circular list, with `head` being a placeholder head node.
-static void list_init(struct list_node *head)
-{
-	if (!head->next) {
-		assert(!head->prev);
-		head->next = head->prev = head;
-	}
-}
-
 void list_remove(struct list_node *node)
 {
-	/* Cannot remove the head node. */
-	assert(node->prev && node->next);
 	if (node->prev)
 		node->prev->next = node->next;
 	if (node->next)
@@ -25,9 +13,6 @@ void list_remove(struct list_node *node)
 
 void list_insert_after(struct list_node *node, struct list_node *after)
 {
-	/* Check uninitialized head node. */
-	if (after->prev == NULL)
-		list_init(after);
 	node->next = after->next;
 	node->prev = after;
 	after->next = node;
@@ -37,8 +22,6 @@ void list_insert_after(struct list_node *node, struct list_node *after)
 
 void list_insert_before(struct list_node *node, struct list_node *before)
 {
-	/* `before` cannot be an uninitialized head node. */
-	assert(before->prev)
 	node->prev = before->prev;
 	node->next = before;
 	before->prev = node;
@@ -48,7 +31,8 @@ void list_insert_before(struct list_node *node, struct list_node *before)
 
 void list_append(struct list_node *node, struct list_node *head)
 {
-	list_init(head);
-	/* With a circular list, we just need to insert before the head. */
-	list_insert_before(node, head);
+	while (head->next)
+		head = head->next;
+
+	list_insert_after(node, head);
 }
diff --git a/tests/commonlib/list-test.c b/tests/commonlib/list-test.c
index eeeeded059..4ca48a468f 100644
--- a/tests/commonlib/list-test.c
+++ b/tests/commonlib/list-test.c
@@ -1,10 +1,9 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
-#include <commonlib/list.h>
+#include <tests/test.h>
 #include <stdlib.h>
 #include <string.h>
-#include <tests/test.h>
-#include <types.h>
+#include <commonlib/list.h>
 
 struct test_container {
 	int value;
@@ -12,20 +11,10 @@ struct test_container {
 	struct list_node list_node;
 };
 
-static void test_list_empty(void **state)
-{
-	struct list_node head = {};
-	struct test_container *node;
-
-	list_for_each(node, head, list_node) {
-		assert_true(false);
-	}
-}
-
-static void test_list_insert_after(void **state)
+void test_list_insert_after(void **state)
 {
 	int i = 0;
-	struct list_node head = {};
+	struct list_node root = { .prev = NULL, .next = NULL };
 	struct test_container *c1 = (struct test_container *)malloc(sizeof(*c1));
 	struct test_container *c2 = (struct test_container *)malloc(sizeof(*c2));
 	struct test_container *c3 = (struct test_container *)malloc(sizeof(*c2));
@@ -40,11 +29,11 @@ static void test_list_insert_after(void **state)
 	c2->value = values[1];
 	c3->value = values[2];
 
-	list_insert_after(&c1->list_node, &head);
+	list_insert_after(&c1->list_node, &root);
 	list_insert_after(&c2->list_node, &c1->list_node);
 	list_insert_after(&c3->list_node, &c2->list_node);
 
-	list_for_each(ptr, head, list_node) {
+	list_for_each(ptr, root, list_node) {
 		assert_int_equal(values[i], ptr->value);
 		i++;
 	}
@@ -56,10 +45,10 @@ static void test_list_insert_after(void **state)
 	free(c1);
 }
 
-static void test_list_insert_before(void **state)
+void test_list_insert_before(void **state)
 {
 	int i = 0;
-	struct list_node head = {};
+	struct list_node root = { .prev = NULL, .next = NULL };
 	struct test_container *c1 = (struct test_container *)malloc(sizeof(*c1));
 	struct test_container *c2 = (struct test_container *)malloc(sizeof(*c2));
 	struct test_container *c3 = (struct test_container *)malloc(sizeof(*c2));
@@ -74,11 +63,12 @@ static void test_list_insert_before(void **state)
 	c2->value = values[1];
 	c3->value = values[2];
 
-	list_insert_after(&c3->list_node, &head);
+	list_insert_after(&c3->list_node, &root);
 	list_insert_before(&c2->list_node, &c3->list_node);
 	list_insert_before(&c1->list_node, &c2->list_node);
 
-	list_for_each(ptr, head, list_node) {
+
+	list_for_each(ptr, root, list_node) {
 		assert_int_equal(values[i], ptr->value);
 		i++;
 	}
@@ -90,27 +80,19 @@ static void test_list_insert_before(void **state)
 	free(c1);
 }
 
-static void test_list_insert_before_head(void **state)
+void test_list_remove(void **state)
 {
-	struct list_node head = {};
-	struct test_container c = {};
-
-	expect_assert_failure(list_insert_before(&c.list_node, &head));
-}
-
-static void test_list_remove(void **state)
-{
-	struct list_node head = {};
+	struct list_node root = { .prev = NULL, .next = NULL };
 	struct test_container *c1 = (struct test_container *)malloc(sizeof(*c1));
 	struct test_container *c2 = (struct test_container *)malloc(sizeof(*c2));
 	struct test_container *ptr;
 	int len;
 
-	list_insert_after(&c1->list_node, &head);
+	list_insert_after(&c1->list_node, &root);
 	list_insert_after(&c2->list_node, &c1->list_node);
 
 	len = 0;
-	list_for_each(ptr, head, list_node) {
+	list_for_each(ptr, root, list_node) {
 		len++;
 	}
 	assert_int_equal(2, len);
@@ -118,14 +100,14 @@ static void test_list_remove(void **state)
 	list_remove(&c1->list_node);
 
 	len = 0;
-	list_for_each(ptr, head, list_node) {
+	list_for_each(ptr, root, list_node) {
 		len++;
 	}
 	assert_int_equal(1, len);
 
 	list_remove(&c2->list_node);
 	len = 0;
-	list_for_each(ptr, head, list_node) {
+	list_for_each(ptr, root, list_node) {
 		len++;
 	}
 	assert_int_equal(0, len);
@@ -134,26 +116,20 @@ static void test_list_remove(void **state)
 	free(c1);
 }
 
-static void test_list_remove_head(void **state)
-{
-	struct list_node head = {};
-	expect_assert_failure(list_remove(&head));
-}
-
-static void test_list_append(void **state)
+void test_list_append(void **state)
 {
 	size_t idx;
 	struct test_container *node;
-	struct list_node head = {};
+	struct list_node root = {};
 	struct test_container nodes[] = {
 		{1}, {2}, {3}
 	};
 
 	for (idx = 0; idx < ARRAY_SIZE(nodes); ++idx)
-		list_append(&nodes[idx].list_node, &head);
+		list_append(&nodes[idx].list_node, &root);
 
 	idx = 0;
-	list_for_each(node, head, list_node) {
+	list_for_each(node, root, list_node) {
 		assert_ptr_equal(node, &nodes[idx]);
 		idx++;
 	}
@@ -162,14 +138,12 @@ static void test_list_append(void **state)
 int main(void)
 {
 	const struct CMUnitTest tests[] = {
-		cmocka_unit_test(test_list_empty),
 		cmocka_unit_test(test_list_insert_after),
 		cmocka_unit_test(test_list_insert_before),
-		cmocka_unit_test(test_list_insert_before_head),
 		cmocka_unit_test(test_list_remove),
-		cmocka_unit_test(test_list_remove_head),
 		cmocka_unit_test(test_list_append),
 	};
 
+
 	return cb_run_group_tests(tests, NULL, NULL);
 }

From a1e602f8ca6c09ddbbe3bf9f44001a79cd350596 Mon Sep 17 00:00:00 2001
From: Subrata Banik <subratabanik@google.com>
Date: Tue, 27 Jan 2026 19:16:26 +0530
Subject: [PATCH 3148/3886] mb/google/bluey: Reduce WP_RO size to 8MB for SPI
 compatibility

The previous 12MB WP_RO size is an invalid range for the SPI controller.
Hardware write-protection requires power-of-two or specific
block-aligned boundaries, making 12MB unenforceable.

Reduce WP_RO to 8MB to ensure hardware WP can be correctly enabled.

The reclaimed space is assigned to RW_UNUSED.

BUG=b:479139462
TEST=Build and verify FMAP layout on Bluey; confirm hardware WP
enforcement.

Change-Id: I4515eab3941913942fc5994e7094986e2edbd6d6
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90952
Reviewed-by: Jayvik Desai <jayvik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Avi Uday <aviuday@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/google/bluey/chromeos.fmd | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/src/mainboard/google/bluey/chromeos.fmd b/src/mainboard/google/bluey/chromeos.fmd
index 01a2331b22..b70b49811d 100644
--- a/src/mainboard/google/bluey/chromeos.fmd
+++ b/src/mainboard/google/bluey/chromeos.fmd
@@ -1,7 +1,7 @@
 ## SPDX-License-Identifier: GPL-2.0-only
 
 FLASH@0x0 CONFIG_ROM_SIZE {
-	WP_RO 12M {
+	WP_RO 8M {
 		RO_SECTION {
 			BOOTBLOCK 512K
 			FMAP 4K
@@ -38,5 +38,7 @@ FLASH@0x0 CONFIG_ROM_SIZE {
 		RW_FWID_B 256
 	}
 
+	RW_UNUSED 4M
+
 	RW_LEGACY(CBFS)
 }

From 50099def6fdb69386dc15e11f475d2ec304c2232 Mon Sep 17 00:00:00 2001
From: Subrata Banik <subratabanik@google.com>
Date: Mon, 26 Jan 2026 13:39:32 +0000
Subject: [PATCH 3149/3886] soc/qualcomm/x1p42100: Relocate CBMEM top to PIL
 region base

The current CBMEM top is situated at the base of 'dram_xbl_log'
(0x81A00000), leaving only 4.4MB of usable memory below it. This
space has become insufficient for the growing size requirements of
the coreboot configuration tables and boot services.

Relocate the CBMEM top to the base of the PIL region (0x866C0000).
This move increases the available contiguous memory for CBMEM
allocation from 4.4MB to 7.3MB, ensuring sufficient headroom for
the tables and reducing fragmentation for the OS and runtime services.

Changes:
- Update cbmem_top_chipset() to return _dram_pil as the new boundary.
- Update memlayout.ld documentation to reflect CBMEM's new position
  directly below the PIL region.

TEST=Verified CBMEM initialization on Bluey; confirmed coreboot
tables are correctly allocated at the new high-memory boundary and
no overlaps occur with reserved regions.

Change-Id: I26d95b952634ce06ed2171c75bc6a129c15ec3b8
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90912
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Avi Uday <aviuday@google.com>
---
 src/soc/qualcomm/x1p42100/cbmem.c      | 2 +-
 src/soc/qualcomm/x1p42100/memlayout.ld | 4 ++--
 2 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/src/soc/qualcomm/x1p42100/cbmem.c b/src/soc/qualcomm/x1p42100/cbmem.c
index 0524c67f03..568f23ab74 100644
--- a/src/soc/qualcomm/x1p42100/cbmem.c
+++ b/src/soc/qualcomm/x1p42100/cbmem.c
@@ -6,5 +6,5 @@
 
 uintptr_t cbmem_top_chipset(void)
 {
-	return (uintptr_t)_dram_xbl_log;
+	return (uintptr_t)_dram_pil;
 }
diff --git a/src/soc/qualcomm/x1p42100/memlayout.ld b/src/soc/qualcomm/x1p42100/memlayout.ld
index c3d79b8890..2c06eccd24 100644
--- a/src/soc/qualcomm/x1p42100/memlayout.ld
+++ b/src/soc/qualcomm/x1p42100/memlayout.ld
@@ -51,6 +51,8 @@
  * 0x91380000    +----------------------------------------------------------+      |        |
  *               |                       dram_pil                           |      |        |
  * 0x866C0000    +----------------------------------------------------------+      |        |
+ *               |                        CBMEM                             |      |        |
+ *               +----------------------------------------------------------+      |        |
  *               |                ... Usable memory ...                     |      |        |
  * 0x85F80000    +----------------------------------------------------------+      |        |
  *               |                       dram_wlan                          |      |        |
@@ -81,8 +83,6 @@
  * 0x81A40000    +----------------------------------------------------------+      |        |
  *               |                     dram_xbl_log                         |      |        |
  * 0x81A00000    +----------------------------------------------------------+      |        |
- *               |                        CBMEM                             |      |        |
- *               +----------------------------------------------------------+      |        |
  *               |                ... Usable memory ...                     |      |        |
  * 0x815A0000    +----------------------------------------------------------+      |        |
  *               |                      dram_cpucp                          |      |        |

From 81af46e68b695d529892145c3406ab80fc8316b7 Mon Sep 17 00:00:00 2001
From: Maximilian Brune <maximilian.brune@9elements.com>
Date: Wed, 16 Apr 2025 20:58:00 +0200
Subject: [PATCH 3150/3886] vc/amd/fsp: Add SMBIOS Type 19 and 20

TEST=Boot glinda based mainboard and see Type 19 and 20 entries using
     dmidecode tool.

Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: I9a0abab9a5324f83659180a3842a8b5d9c6b3820
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87586
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
---
 src/vendorcode/amd/fsp/cezanne/soc_dmi_info.h |  2 +
 src/vendorcode/amd/fsp/common/dmi_info.h      | 52 +++++++++++++++++++
 src/vendorcode/amd/fsp/glinda/soc_dmi_info.h  |  3 +-
 .../amd/fsp/mendocino/soc_dmi_info.h          |  2 +
 src/vendorcode/amd/fsp/phoenix/soc_dmi_info.h |  2 +
 src/vendorcode/amd/fsp/picasso/soc_dmi_info.h |  2 +
 src/vendorcode/amd/fsp/renoir/soc_dmi_info.h  |  2 +
 7 files changed, 64 insertions(+), 1 deletion(-)

diff --git a/src/vendorcode/amd/fsp/cezanne/soc_dmi_info.h b/src/vendorcode/amd/fsp/cezanne/soc_dmi_info.h
index 47500defa3..cc18977cf5 100644
--- a/src/vendorcode/amd/fsp/cezanne/soc_dmi_info.h
+++ b/src/vendorcode/amd/fsp/cezanne/soc_dmi_info.h
@@ -10,6 +10,8 @@
 #define AGESA_STRUCT_SOCKET_COUNT         2   ///< Number of sockets in AGESA FSP DMI T17 table
 #define AGESA_STRUCT_CHANNELS_PER_SOCKET  8   ///< Channels per socket in AGESA FSP DMI T17 table
 #define AGESA_STRUCT_DIMMS_PER_CHANNEL    4   ///< DIMMs per channel in AGESA FSP DMI T17 table
+#define AGESA_STRUCT_T19_REGION_SUPPORTED 3   ///< Max SMBIOS T19 Memory Region count
+#define AGESA_STRUCT_T20_REGION_SUPPORTED 1   ///< Max SMBIOS T20 Memory Region count
 #define AGESA_STRUCT_PART_NUMBER_SIZE     21
 
 #define SMBIOS_3_2_SUPPORT                1
diff --git a/src/vendorcode/amd/fsp/common/dmi_info.h b/src/vendorcode/amd/fsp/common/dmi_info.h
index e38a44ed94..8879b4b3a1 100644
--- a/src/vendorcode/amd/fsp/common/dmi_info.h
+++ b/src/vendorcode/amd/fsp/common/dmi_info.h
@@ -185,8 +185,60 @@ typedef struct {
 #endif
 } __packed TYPE17_DMI_INFO;
 
+/// DMI Type 19 - Memory Array Mapped Address
+typedef struct {
+  OUT UINT32                    StartingAddr;           ///< The physical address, in kilobytes,
+                                                        ///< of a range of memory mapped to the
+                                                        ///< specified physical memory array.
+  OUT UINT32                    EndingAddr;             ///< The physical ending address of the
+                                                        ///< last kilobyte of a range of addresses
+                                                        ///< mapped to the specified physical memory array.
+  OUT UINT16                    MemoryArrayHandle;      ///< The handle, or instance number, associated
+                                                        ///< with the physical memory array to which this
+                                                        ///< address range is mapped.
+  OUT UINT8                     PartitionWidth;         ///< Identifies the number of memory devices that
+                                                        ///< form a single row of memory for the address
+                                                        ///< partition defined by this structure.
+  OUT UINT64                    ExtStartingAddr;        ///< The physical address, in bytes, of a range of
+                                                        ///< memory mapped to the specified Physical Memory Array.
+  OUT UINT64                    ExtEndingAddr;          ///< The physical address, in bytes, of a range of
+                                                        ///< memory mapped to the specified Physical Memory Array.
+} __packed TYPE19_DMI_INFO;
+
+///DMI Type 20 - Memory Device Mapped Address
+typedef struct {
+  OUT UINT32                    StartingAddr;           ///< The physical address, in kilobytes, of a range
+                                                        ///< of memory mapped to the referenced Memory Device.
+  OUT UINT32                    EndingAddr;             ///< The handle, or instance number, associated with
+                                                        ///< the Memory Device structure to which this address
+                                                        ///< range is mapped.
+  OUT UINT16                    MemoryDeviceHandle;     ///< The handle, or instance number, associated with
+                                                        ///< the Memory Device structure to which this address
+                                                        ///< range is mapped.
+  OUT UINT16                    MemoryArrayMappedAddressHandle; ///< The handle, or instance number, associated
+                                                        ///< with the Memory Array Mapped Address structure to
+                                                        ///< which this device address range is mapped.
+  OUT UINT8                     PartitionRowPosition;   ///< Identifies the position of the referenced Memory
+                                                        ///< Device in a row of the address partition.
+  OUT UINT8                     InterleavePosition;     ///< The position of the referenced Memory Device in
+                                                        ///< an interleave.
+  OUT UINT8                     InterleavedDataDepth;   ///< The maximum number of consecutive rows from the
+                                                        ///< referenced Memory Device that are accessed in a
+                                                        ///< single interleaved transfer.
+  OUT UINT64                    ExtStartingAddr;        ///< The physical address, in bytes, of a range of
+                                                        ///< memory mapped to the referenced Memory Device.
+  OUT UINT64                    ExtEndingAddr;          ///< The physical ending address, in bytes, of the last of
+                                                        ///< a range of addresses mapped to the referenced Memory Device.
+} __packed TYPE20_DMI_INFO;
+
 /// Collection of pointers to the DMI records
 typedef struct {
   OUT TYPE16_DMI_INFO           T16;                          ///< Type 16 struc
   OUT TYPE17_DMI_INFO           T17[AGESA_STRUCT_SOCKET_COUNT][AGESA_STRUCT_CHANNELS_PER_SOCKET][AGESA_STRUCT_DIMMS_PER_CHANNEL]; ///< Type 17 struc
+#ifdef AGESA_STRUCT_T19_REGION_SUPPORTED
+  OUT TYPE19_DMI_INFO           T19[AGESA_STRUCT_T19_REGION_SUPPORTED];
+#endif
+#ifdef AGESA_STRUCT_T20_REGION_SUPPORTED
+  OUT TYPE20_DMI_INFO           T20[AGESA_STRUCT_SOCKET_COUNT][AGESA_STRUCT_CHANNELS_PER_SOCKET][AGESA_STRUCT_DIMMS_PER_CHANNEL][AGESA_STRUCT_T20_REGION_SUPPORTED]; ///< Type 20 struc
+#endif
 } DMI_INFO;
diff --git a/src/vendorcode/amd/fsp/glinda/soc_dmi_info.h b/src/vendorcode/amd/fsp/glinda/soc_dmi_info.h
index 15c7b63a71..85381fd691 100644
--- a/src/vendorcode/amd/fsp/glinda/soc_dmi_info.h
+++ b/src/vendorcode/amd/fsp/glinda/soc_dmi_info.h
@@ -2,7 +2,6 @@
 
 /*
  * These definitions are used to describe memory modules physical layout
- * TODO: Update for Glinda
  */
 
 #ifndef SOC_DMI_INFO_H
@@ -11,6 +10,8 @@
 #define AGESA_STRUCT_SOCKET_COUNT         4   ///< Number of sockets in AGESA FSP DMI T17 table
 #define AGESA_STRUCT_CHANNELS_PER_SOCKET  16   ///< Channels per socket in AGESA FSP DMI T17 table
 #define AGESA_STRUCT_DIMMS_PER_CHANNEL    2   ///< DIMMs per channel in AGESA FSP DMI T17 table
+#define AGESA_STRUCT_T19_REGION_SUPPORTED 3   ///< Max SMBIOS T19 Memory Region count
+#define AGESA_STRUCT_T20_REGION_SUPPORTED 3   ///< Max SMBIOS T20 Memory Region count
 #define AGESA_STRUCT_PART_NUMBER_SIZE     31
 
 #define SMBIOS_3_2_SUPPORT                1
diff --git a/src/vendorcode/amd/fsp/mendocino/soc_dmi_info.h b/src/vendorcode/amd/fsp/mendocino/soc_dmi_info.h
index bf35aea3e5..4c3776e458 100644
--- a/src/vendorcode/amd/fsp/mendocino/soc_dmi_info.h
+++ b/src/vendorcode/amd/fsp/mendocino/soc_dmi_info.h
@@ -10,6 +10,8 @@
 #define AGESA_STRUCT_SOCKET_COUNT         4   ///< Number of sockets in AGESA FSP DMI T17 table
 #define AGESA_STRUCT_CHANNELS_PER_SOCKET  12  ///< Channels per socket in AGESA FSP DMI T17 table
 #define AGESA_STRUCT_DIMMS_PER_CHANNEL    2   ///< DIMMs per channel in AGESA FSP DMI T17 table
+#define AGESA_STRUCT_T19_REGION_SUPPORTED 3   ///< Max SMBIOS T19 Memory Region count
+#define AGESA_STRUCT_T20_REGION_SUPPORTED 1   ///< Max SMBIOS T20 Memory Region count
 #define AGESA_STRUCT_PART_NUMBER_SIZE     21
 
 #define SMBIOS_3_2_SUPPORT                1
diff --git a/src/vendorcode/amd/fsp/phoenix/soc_dmi_info.h b/src/vendorcode/amd/fsp/phoenix/soc_dmi_info.h
index bf35aea3e5..4c3776e458 100644
--- a/src/vendorcode/amd/fsp/phoenix/soc_dmi_info.h
+++ b/src/vendorcode/amd/fsp/phoenix/soc_dmi_info.h
@@ -10,6 +10,8 @@
 #define AGESA_STRUCT_SOCKET_COUNT         4   ///< Number of sockets in AGESA FSP DMI T17 table
 #define AGESA_STRUCT_CHANNELS_PER_SOCKET  12  ///< Channels per socket in AGESA FSP DMI T17 table
 #define AGESA_STRUCT_DIMMS_PER_CHANNEL    2   ///< DIMMs per channel in AGESA FSP DMI T17 table
+#define AGESA_STRUCT_T19_REGION_SUPPORTED 3   ///< Max SMBIOS T19 Memory Region count
+#define AGESA_STRUCT_T20_REGION_SUPPORTED 1   ///< Max SMBIOS T20 Memory Region count
 #define AGESA_STRUCT_PART_NUMBER_SIZE     21
 
 #define SMBIOS_3_2_SUPPORT                1
diff --git a/src/vendorcode/amd/fsp/picasso/soc_dmi_info.h b/src/vendorcode/amd/fsp/picasso/soc_dmi_info.h
index 94a43f55b0..c9063ac640 100644
--- a/src/vendorcode/amd/fsp/picasso/soc_dmi_info.h
+++ b/src/vendorcode/amd/fsp/picasso/soc_dmi_info.h
@@ -10,6 +10,8 @@
 #define AGESA_STRUCT_SOCKET_COUNT         1   ///< Number of sockets in AGESA FSP DMI T17 table
 #define AGESA_STRUCT_CHANNELS_PER_SOCKET  4   ///< Channels per socket in AGESA FSP DMI T17 table
 #define AGESA_STRUCT_DIMMS_PER_CHANNEL    4   ///< DIMMs per channel in AGESA FSP DMI T17 table
+#define AGESA_STRUCT_T19_REGION_SUPPORTED 3   ///< Max SMBIOS T19 Memory Region count
+#define AGESA_STRUCT_T20_REGION_SUPPORTED 1   ///< Max SMBIOS T20 Memory Region count
 #define AGESA_STRUCT_PART_NUMBER_SIZE     21
 
 #endif /* SOC_DMI_INFO_H */
diff --git a/src/vendorcode/amd/fsp/renoir/soc_dmi_info.h b/src/vendorcode/amd/fsp/renoir/soc_dmi_info.h
index 762320cdc3..701c91f166 100644
--- a/src/vendorcode/amd/fsp/renoir/soc_dmi_info.h
+++ b/src/vendorcode/amd/fsp/renoir/soc_dmi_info.h
@@ -10,6 +10,8 @@
 #define AGESA_STRUCT_SOCKET_COUNT         2   ///< Number of sockets in AGESA FSP DMI T17 table
 #define AGESA_STRUCT_CHANNELS_PER_SOCKET  8   ///< Channels per socket in AGESA FSP DMI T17 table
 #define AGESA_STRUCT_DIMMS_PER_CHANNEL    4   ///< DIMMs per channel in AGESA FSP DMI T17 table
+#define AGESA_STRUCT_T19_REGION_SUPPORTED 3   ///< Max SMBIOS T19 Memory Region count
+#define AGESA_STRUCT_T20_REGION_SUPPORTED 1   ///< Max SMBIOS T20 Memory Region count
 #define AGESA_STRUCT_PART_NUMBER_SIZE     21 //TODO check
 
 #define SMBIOS_3_2_SUPPORT                1

From 6cb3e3e4a6d02b4a2a1580e3ffeaef36c07abdcd Mon Sep 17 00:00:00 2001
From: Luca Lai <luca.lai@lcfc.corp-partner.google.com>
Date: Tue, 27 Jan 2026 11:28:26 +0800
Subject: [PATCH 3151/3886] mb/fatcat/var/ruby: Change touchscreen HID

Checked with the SED team and confirmed that the HID name needs
to be changed to "GT 7936".

BUG=b:478990702
BRANCH=none
TEST=Build the image and boot to the OS, then check that
the touchscreen HID name has changed to "GT 7936"
in the diagnostics app.

Change-Id: Id0ce797b121c4a7bcf7bf15bfc81e9b079ebb3c4
Signed-off-by: Luca Lai <luca.lai@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90941
Reviewed-by: YH Lin <yueherngl@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Pranava Y N <pranavayn@google.com>
---
 src/mainboard/google/fatcat/variants/ruby/overridetree.cb | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/mainboard/google/fatcat/variants/ruby/overridetree.cb b/src/mainboard/google/fatcat/variants/ruby/overridetree.cb
index e643ee9fae..0ad94b8912 100644
--- a/src/mainboard/google/fatcat/variants/ruby/overridetree.cb
+++ b/src/mainboard/google/fatcat/variants/ruby/overridetree.cb
@@ -337,7 +337,7 @@ chip soc/intel/pantherlake
 		end # I2C4
 		device ref i2c5 on
 			chip drivers/i2c/hid
-				register "generic.hid" = ""GT7936L""
+				register "generic.hid" = ""GT 7936""
 				register "generic.desc" = ""Goodix Touchscreen""
 				register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_F18_IRQ)"
 				register "generic.detect" = "1"
@@ -355,7 +355,7 @@ chip soc/intel/pantherlake
 				device i2c 0x14 on end
 			end
 			chip drivers/i2c/hid
-				register "generic.hid" = ""GT7936L""
+				register "generic.hid" = ""GT 7936""
 				register "generic.desc" = ""Goodix Touchscreen""
 				register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_F18_IRQ)"
 				register "generic.detect" = "1"

From 47a24d1d512f965d3323f512bdea7bb6d6762d9d Mon Sep 17 00:00:00 2001
From: Varun Upadhyay <varun.upadhyay@intel.com>
Date: Tue, 9 Dec 2025 09:44:48 +0530
Subject: [PATCH 3152/3886] mb/google/ocelot: Add support for
 AUDIO_MAX98360_ALC5682I_I2S

This change adds support for I2S codec in the device tree and enables
it based on the fw_config based on WCL_GPIO_Implementation Rev0p7.

RDC Doc no: 836031

BUG=b:465888555
TEST=Boot on google ocelot board and Enable I2C Codec for Audio.
Check Mic and Speaker functionality

Change-Id: I51fb849bf365108be1ff59d65069329e5fd08824
Signed-off-by: Varun Upadhyay <varun.upadhyay@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90427
Reviewed-by: P, Usha <usha.p@intel.com>
Reviewed-by: Avi Uday <aviuday@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 .../google/ocelot/variants/ocelot/fw_config.c | 61 ++++++++++---------
 .../ocelot/variants/ocelot/overridetree.cb    | 31 +++++++++-
 2 files changed, 61 insertions(+), 31 deletions(-)

diff --git a/src/mainboard/google/ocelot/variants/ocelot/fw_config.c b/src/mainboard/google/ocelot/variants/ocelot/fw_config.c
index 818be9b9aa..d9f68ab505 100644
--- a/src/mainboard/google/ocelot/variants/ocelot/fw_config.c
+++ b/src/mainboard/google/ocelot/variants/ocelot/fw_config.c
@@ -12,37 +12,36 @@
 #define GPIO_CONFIGURE_PADS(t) gpio_configure_pads(t, ARRAY_SIZE(t))
 
 static const struct pad_config i2s_enable_pads[] = {
-	/* I2S_MCLK1_OUT */
+	/* GPP_D09:	I2S_MCLK1_OUT */
 	PAD_CFG_NF(GPP_D09, NONE, DEEP, NF2),
-	/* I2S0_SCLK_HDR */
-	PAD_CFG_NF(GPP_D10, NONE, DEEP, NF1),
-	/* I2S0_SFRM_HDR */
-	PAD_CFG_NF(GPP_D11, NONE, DEEP, NF1),
-	/* I2S0_TXD_HDR */
-	PAD_CFG_NF(GPP_D12, NONE, DEEP, NF1),
-	/* I2S0_RXD_HDR */
-	PAD_CFG_NF(GPP_D13, NONE, DEEP, NF1),
-	/* I2S1_TXD_HDR */
-	PAD_CFG_NF(GPP_S00, NONE, DEEP, NF1),
-	/* I2S1_RXD_HDR */
-	PAD_CFG_NF(GPP_S01, NONE, DEEP, NF1),
-	/* I2S1_SCLK_HDR */
-	PAD_CFG_NF(GPP_S02, NONE, DEEP, NF1),
-	/* I2S1_SFRM_HDR */
-	PAD_CFG_NF(GPP_S03, NONE, DEEP, NF1),
-	/* I2S2_SCLK_HDR */
-	PAD_CFG_NF(GPP_S04, NONE, DEEP, NF1),
-	/* I2S2_SFRM_HDR */
-	PAD_CFG_NF(GPP_S05, NONE, DEEP, NF1),
-	/* I2S2_TXD_HDR */
-	PAD_NC(GPP_S06, NONE),
-	/* I2S2_RXD_HDR */
-	PAD_NC(GPP_S07, NONE),
-
-	/* DMIC_CLK */
-	PAD_NC(GPP_D16, NONE),
-	/* DMIC_DATA */
-	PAD_NC(GPP_D17, NONE),
+	/* GPP_D10:     I2S0_SCLK_HDR */
+	PAD_CFG_NF(GPP_D10, NONE, DEEP, NF2),
+	/* GPP_D11:     I2S0_SFRM_HDR */
+	PAD_CFG_NF(GPP_D11, NONE, DEEP, NF2),
+	/* GPP_D12:     I2S0_TXD_HDR */
+	PAD_CFG_NF(GPP_D12, NONE, DEEP, NF2),
+	/* GPP_D13:     I2S0_RXD_HDR */
+	PAD_CFG_NF(GPP_D13, NONE, DEEP, NF2),
+	/* GPP_S00:     I2S1_TXD_HDR */
+	PAD_CFG_NF(GPP_S00, NONE, DEEP, NF6),
+	/* GPP_S01:     I2S1_RXD_HDR */
+	PAD_CFG_NF(GPP_S01, NONE, DEEP, NF6),
+	/* GPP_S02:     I2S1_SCLK_HDR */
+	PAD_CFG_NF(GPP_S02, NONE, DEEP, NF6),
+	/* GPP_S03:     I2S1_SFRM_HDR */
+	PAD_CFG_NF(GPP_S03, NONE, DEEP, NF6),
+	/* GPP_S04:     I2S2_SCLK_HDR */
+	PAD_CFG_NF(GPP_S04, NONE, DEEP, NF6),
+	/* GPP_S05:     I2S2_SFRM_HDR */
+	PAD_CFG_NF(GPP_S05, NONE, DEEP, NF6),
+	/* GPP_S06:     DMIC1_CLK (HDR) */
+	PAD_CFG_NF(GPP_S06, NONE, DEEP, NF5),
+	 /* GPP_S07:    DMIC1_DATA (HDR) */
+	PAD_CFG_NF(GPP_S07, NONE, DEEP, NF5),
+	/* GPP_D16:     DMIC_CLK */
+	PAD_CFG_NF(GPP_D16, NONE, DEEP, NF3),
+	/* GPP_D17:     DMIC_DATA */
+	PAD_CFG_NF(GPP_D17, NONE, DEEP, NF3),
 };
 
 static const struct pad_config hda_enable_pads[] = {
@@ -93,6 +92,8 @@ static const struct pad_config sndw_alc721_enable_pads[] = {
 };
 
 static const struct pad_config audio_disable_pads[] = {
+	/* GPP_D09:     I2S_MCLK1_OUT */
+	PAD_NC(GPP_D09, NONE),
 	/* GPP_D10:     HDA_BCLK (HDR) */
 	PAD_NC(GPP_D10, NONE),
 	/* GPP_D11:     HDA_SYNC (HDR) */
diff --git a/src/mainboard/google/ocelot/variants/ocelot/overridetree.cb b/src/mainboard/google/ocelot/variants/ocelot/overridetree.cb
index 117e7d8610..d7bd320ccd 100644
--- a/src/mainboard/google/ocelot/variants/ocelot/overridetree.cb
+++ b/src/mainboard/google/ocelot/variants/ocelot/overridetree.cb
@@ -92,7 +92,7 @@ chip soc/intel/pantherlake
 		[PchSerialIoIndexI2C0]  = PchSerialIoPci,
 		[PchSerialIoIndexI2C1]  = PchSerialIoPci,
 		[PchSerialIoIndexI2C2]  = PchSerialIoDisabled,
-		[PchSerialIoIndexI2C3]  = PchSerialIoDisabled,
+		[PchSerialIoIndexI2C3]  = PchSerialIoPci,
 		[PchSerialIoIndexI2C4]  = PchSerialIoDisabled,
 		[PchSerialIoIndexI2C5]  = PchSerialIoPci,
 	}"
@@ -108,6 +108,7 @@ chip soc/intel/pantherlake
 	#| Field             |  Value                    |
 	#+-------------------+---------------------------+
 	#| I2C1              | TPM(cr50)                 |
+	#| I2C3              | Audio                     |
 	#| I2C5              | Touchpad                  |
 	#+-------------------+---------------------------+
 	register "common_soc_config" = "{
@@ -118,6 +119,10 @@ chip soc/intel/pantherlake
 			.speed = I2C_SPEED_FAST,
 			.early_init = 1,
 		},
+		.i2c[3] = {
+			.speed = I2C_SPEED_FAST,
+			.early_init = 1,
+		},
 		.i2c[5] = {
 			.speed = I2C_SPEED_FAST,
 		},
@@ -532,6 +537,22 @@ chip soc/intel/pantherlake
 				device i2c 50 on end
 			end
 		end
+		device ref i2c3 on
+			chip drivers/i2c/generic
+				register "hid" = ""RTL5682""
+				register "name" = ""RT58""
+				register "desc" = ""Headset Codec""
+				register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_F17)"
+				# Set the jd_src to RT5668_JD1 for jack detection
+				register "property_count" = "1"
+				register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER"
+				register "property_list[0].name" = ""realtek,jd-src""
+				register "property_list[0].integer" = "1"
+				device i2c 1a on
+					probe AUDIO AUDIO_MAX98360_ALC5682I_I2S
+				end
+			end
+		end #I2C3
 		device ref i2c5 on
 			chip drivers/i2c/hid
 				register "generic.hid" = ""HFW68H""
@@ -586,6 +607,14 @@ chip soc/intel/pantherlake
 					end
 				end
 			end
+		        chip drivers/generic/max98357a
+				register "hid" = ""MX98360A""
+				register "sdmode_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A15)"
+				register "sdmode_delay" = "5"
+				device generic 0 on
+					probe AUDIO AUDIO_MAX98360_ALC5682I_I2S
+				end
+			end
 		end
 	end
 end

From db0f677fd10be05edc7e0d13e36edd643f63784b Mon Sep 17 00:00:00 2001
From: Rui Zhou <zhourui@huaqin.corp-partner.google.com>
Date: Wed, 14 Jan 2026 14:09:18 +0800
Subject: [PATCH 3153/3886] mb/google/brox/var/lotso: Add RAM ID for
 K3KL8L80CM-MGCT

Add RAM ID for K3KL8L80CM-MGCT. And importing a single RAM device,
so use mb_get_channel_disable_mask to distinguish it.

BUG=b/468889066
BRANCH=None
TEST=boot to kernel success, and the log shows that the RAM ID is correct.

Change-Id: Idc1e890ab826ec008031f54e0fc445fa5ee62978
Signed-off-by: Rui Zhou <zhourui@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90752
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
---
 src/mainboard/google/brox/Kconfig                   |  1 +
 src/mainboard/google/brox/variants/lotso/memory.c   | 13 +++++++++++++
 .../google/brox/variants/lotso/memory/Makefile.mk   |  2 +-
 .../variants/lotso/memory/dram_id.generated.txt     |  3 ++-
 .../brox/variants/lotso/memory/mem_parts_used.txt   |  3 ++-
 5 files changed, 19 insertions(+), 3 deletions(-)

diff --git a/src/mainboard/google/brox/Kconfig b/src/mainboard/google/brox/Kconfig
index cec63f53be..44db591f32 100644
--- a/src/mainboard/google/brox/Kconfig
+++ b/src/mainboard/google/brox/Kconfig
@@ -81,6 +81,7 @@ config BOARD_GOOGLE_BROX_EC_ISH
 config BOARD_GOOGLE_LOTSO
 	select BOARD_GOOGLE_BASEBOARD_BROX
 	select CHROMEOS_WIFI_SAR if CHROMEOS
+	select ENFORCE_MEM_CHANNEL_DISABLE
 	select MAINBOARD_HAS_GOOGLE_STRAUSS_KEYBOARD
 	select USE_UNIFIED_AP_FIRMWARE_FOR_UFS_AND_NON_UFS
 
diff --git a/src/mainboard/google/brox/variants/lotso/memory.c b/src/mainboard/google/brox/variants/lotso/memory.c
index 84b9f4a70d..0997707e9f 100644
--- a/src/mainboard/google/brox/variants/lotso/memory.c
+++ b/src/mainboard/google/brox/variants/lotso/memory.c
@@ -99,6 +99,19 @@ bool variant_is_half_populated(void)
 	return gpio_get(GPP_S0);
 }
 
+uint8_t mb_get_channel_disable_mask(void)
+{
+	/*
+	 * GPP_S0 High -> One RAM Chip
+	 * GPP_S0 Low  -> Two RAM Chip
+	 * Disable all other channels except first two on each controller
+	 */
+	if (gpio_get(GPP_S0))
+		return (BIT(2) | BIT(3));
+
+	return 0;
+}
+
 void variant_get_spd_info(struct mem_spd *spd_info)
 {
 	spd_info->topo = MEM_TOPO_MEMORY_DOWN;
diff --git a/src/mainboard/google/brox/variants/lotso/memory/Makefile.mk b/src/mainboard/google/brox/variants/lotso/memory/Makefile.mk
index 64f4e227ba..e38115911f 100644
--- a/src/mainboard/google/brox/variants/lotso/memory/Makefile.mk
+++ b/src/mainboard/google/brox/variants/lotso/memory/Makefile.mk
@@ -7,4 +7,4 @@ SPD_SOURCES =
 SPD_SOURCES += spd/lp5/set-0/spd-9.hex      # ID = 0(0b0000)  Parts = K3KL6L60GM-MGCT
 SPD_SOURCES += spd/lp5/set-0/spd-1.hex      # ID = 1(0b0001)  Parts = H9JCNNNBK3MLYR-N6E
 SPD_SOURCES += spd/lp5/set-0/spd-11.hex      # ID = 2(0b0010)  Parts = K3KL8L80DM-MGCU, MT62F1G32D2DS-023 WT:C, H58G56BK8BX068, H58G56CK8BX146, K3KL8L80EM-MGCU
-SPD_SOURCES += spd/lp5/set-0/spd-7.hex      # ID = 3(0b0011)  Parts = H58G56BK7BX068
+SPD_SOURCES += spd/lp5/set-0/spd-7.hex      # ID = 3(0b0011)  Parts = H58G56BK7BX068, K3KL8L80CM-MGCT
diff --git a/src/mainboard/google/brox/variants/lotso/memory/dram_id.generated.txt b/src/mainboard/google/brox/variants/lotso/memory/dram_id.generated.txt
index a4824fd008..c27f7926ca 100644
--- a/src/mainboard/google/brox/variants/lotso/memory/dram_id.generated.txt
+++ b/src/mainboard/google/brox/variants/lotso/memory/dram_id.generated.txt
@@ -9,6 +9,7 @@ H9JCNNNBK3MLYR-N6E             1 (0001)
 K3KL8L80DM-MGCU                2 (0010)
 MT62F1G32D2DS-023 WT:C         2 (0010)
 H58G56BK8BX068                 2 (0010)
-H58G56BK7BX068                 3 (0011)
 H58G56CK8BX146                 2 (0010)
 K3KL8L80EM-MGCU                2 (0010)
+H58G56BK7BX068                 3 (0011)
+K3KL8L80CM-MGCT                3 (0011)
diff --git a/src/mainboard/google/brox/variants/lotso/memory/mem_parts_used.txt b/src/mainboard/google/brox/variants/lotso/memory/mem_parts_used.txt
index dac8c9957c..7df5ad3b41 100644
--- a/src/mainboard/google/brox/variants/lotso/memory/mem_parts_used.txt
+++ b/src/mainboard/google/brox/variants/lotso/memory/mem_parts_used.txt
@@ -10,10 +10,11 @@
 
 # Part Name
 K3KL6L60GM-MGCT
+K3KL8L80CM-MGCT
 H9JCNNNBK3MLYR-N6E
 K3KL8L80DM-MGCU
 MT62F1G32D2DS-023 WT:C
 H58G56BK8BX068
-H58G56BK7BX068
 H58G56CK8BX146
 K3KL8L80EM-MGCU
+H58G56BK7BX068

From 58aed45731b3a8b04f44ccd901ee531bfdd089be Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Sun, 25 Jan 2026 17:46:17 -0600
Subject: [PATCH 3154/3886] mb/google/dedede: Remove alias for shared_ram from
 devicetree

The alias isn't referenced anywhere, so remove it in preparation of
adding a chipset devicetree using the same alias in a subsequent patch.

TEST=build google/dedede (dexi)

Change-Id: I0745eab9b0947b790f64383549e205bd906ba555
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90896
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/google/dedede/variants/baseboard/devicetree.cb | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb
index be057ea57d..94e0bae07c 100644
--- a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb
+++ b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb
@@ -360,7 +360,7 @@ chip soc/intel/jasperlake
 			end
 		end # USB xHCI
 		device pci 14.1 off end # USB xDCI (OTG)
-		device pci 14.2 alias shared_ram on end # PMC SRAM
+		device pci 14.2 on  end # PMC SRAM
 		device pci 14.3 on
 			chip drivers/wifi/generic
 				register "wake" = "GPE0_PME_B0"

From e1e79dc53b29f779258d033cec6d457df0d67990 Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Sun, 25 Jan 2026 17:50:20 -0600
Subject: [PATCH 3155/3886] mb/google/dedede: Rework I2C enablement

In order to keep coreboot and FSP in sync for which i2c ports are
enabled, disable all I2C ports in the baseboard, in both the PCI
devices and the SerialIoI2cMode register. Each variant enables only the
ports it uses by overriding the SerialIoI2cMode register index for
those ports, and enabling the PCI device(s) and defining the attached
devices. References to i2c ports which were off/disabled are removed
from all variants, as they are redundant.

TEST=build google/dedede (dexi), verify SerialIoI2cMode in static.c
enables only the single port used (i2c4)

Change-Id: I7fcab382cc0eaf4fb0bc9d8095587018b4e226b1
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90897
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
---
 .../dedede/variants/awasuki/overridetree.cb   | 13 +++---------
 .../dedede/variants/baseboard/devicetree.cb   | 20 +++++++++----------
 .../dedede/variants/beadrix/overridetree.cb   | 12 ++++-------
 .../dedede/variants/blipper/overridetree.cb   | 13 +++---------
 .../dedede/variants/boten/overridetree.cb     | 14 +++++--------
 .../dedede/variants/boxy/overridetree.cb      |  6 ++----
 .../dedede/variants/bugzzy/overridetree.cb    |  7 +++++++
 .../dedede/variants/cappy2/overridetree.cb    |  6 ++++++
 .../dedede/variants/corori/overridetree.cb    | 12 +----------
 .../dedede/variants/cret/overridetree.cb      | 13 +++---------
 .../dedede/variants/dexi/overridetree.cb      |  6 ++----
 .../dedede/variants/dibbi/overridetree.cb     |  6 ++----
 .../dedede/variants/dita/overridetree.cb      |  6 ++----
 .../dedede/variants/drawcia/overridetree.cb   |  6 ++++++
 .../dedede/variants/driblee/overridetree.cb   | 13 ++----------
 .../dedede/variants/galtic/overridetree.cb    | 10 +++-------
 .../dedede/variants/gooey/overridetree.cb     | 14 +++++--------
 .../dedede/variants/haboki/overridetree.cb    |  6 ++++++
 .../dedede/variants/kracko/overridetree.cb    | 14 +++++--------
 .../dedede/variants/lalala/overridetree.cb    |  6 ++++++
 .../dedede/variants/lantis/overridetree.cb    | 13 +++---------
 .../dedede/variants/madoo/overridetree.cb     | 13 +++---------
 .../dedede/variants/magolor/overridetree.cb   |  6 ++++++
 .../variants/metaknight/overridetree.cb       | 13 ++++--------
 .../dedede/variants/pirika/overridetree.cb    | 10 +++-------
 .../dedede/variants/sasuke/overridetree.cb    |  7 +++++++
 .../dedede/variants/sasukette/overridetree.cb |  6 ++++++
 .../dedede/variants/shotzo/overridetree.cb    |  6 ++++--
 .../dedede/variants/storo/overridetree.cb     | 13 +++++-------
 .../dedede/variants/taranza/overridetree.cb   |  6 ++----
 .../dedede/variants/waddledee/overridetree.cb |  6 ++++++
 .../dedede/variants/waddledoo/overridetree.cb |  7 +++++++
 32 files changed, 139 insertions(+), 170 deletions(-)

diff --git a/src/mainboard/google/dedede/variants/awasuki/overridetree.cb b/src/mainboard/google/dedede/variants/awasuki/overridetree.cb
index 76b7033f54..f791468b2b 100644
--- a/src/mainboard/google/dedede/variants/awasuki/overridetree.cb
+++ b/src/mainboard/google/dedede/variants/awasuki/overridetree.cb
@@ -53,14 +53,9 @@ chip soc/intel/jasperlake
 	}"
 
 	# SerialIO device mode selection
-	register "SerialIoI2cMode" = "{
-		[PchSerialIoIndexI2C0]  = PchSerialIoPci,
-		[PchSerialIoIndexI2C1]  = PchSerialIoDisabled,
-		[PchSerialIoIndexI2C2]  = PchSerialIoPci,
-		[PchSerialIoIndexI2C3]  = PchSerialIoDisabled,
-		[PchSerialIoIndexI2C4]  = PchSerialIoPci,
-		[PchSerialIoIndexI2C5]  = PchSerialIoDisabled,
-	}"
+	register "SerialIoI2cMode[PchSerialIoIndexI2C0]" = "PchSerialIoPci"
+	register "SerialIoI2cMode[PchSerialIoIndexI2C2]" = "PchSerialIoPci"
+	register "SerialIoI2cMode[PchSerialIoIndexI2C4]" = "PchSerialIoPci"
 
 	# Power limit config
 	register "power_limits_config[JSL_N4500_6W_CORE]" = "{
@@ -191,7 +186,6 @@ chip soc/intel/jasperlake
 				device i2c 15 on end
 			end
 		end # I2C 0
-		device pci 15.1 off end # I2C 1
 		device pci 15.2 on
 			probe TOUCHSCREEN TOUCHSCREEN_PRESENT
 			chip drivers/i2c/generic
@@ -213,7 +207,6 @@ chip soc/intel/jasperlake
 				device i2c 10 on end
 			end
 		end # I2C 2
-		device pci 15.3 off end # I2C 3
 		device pci 19.0 on
 			chip drivers/i2c/rt5645
 				register "hid" = ""10EC5650""
diff --git a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb
index 94e0bae07c..2ce85b2813 100644
--- a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb
+++ b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb
@@ -80,11 +80,11 @@ chip soc/intel/jasperlake
 	register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)"	# USB3/1 Type-A Port A1
 
 	register "SerialIoI2cMode" = "{
-		[PchSerialIoIndexI2C0]  = PchSerialIoPci,
-		[PchSerialIoIndexI2C1]  = PchSerialIoPci,
-		[PchSerialIoIndexI2C2]  = PchSerialIoPci,
-		[PchSerialIoIndexI2C3]  = PchSerialIoPci,
-		[PchSerialIoIndexI2C4]  = PchSerialIoPci,
+		[PchSerialIoIndexI2C0]  = PchSerialIoDisabled,
+		[PchSerialIoIndexI2C1]  = PchSerialIoDisabled,
+		[PchSerialIoIndexI2C2]  = PchSerialIoDisabled,
+		[PchSerialIoIndexI2C3]  = PchSerialIoDisabled,
+		[PchSerialIoIndexI2C4]  = PchSerialIoDisabled,
 		[PchSerialIoIndexI2C5]  = PchSerialIoDisabled,
 	}"
 
@@ -368,16 +368,16 @@ chip soc/intel/jasperlake
 			end
 		end # CNVi wifi
 		device pci 14.5 on  end # SDCard
-		device pci 15.0 on  end # I2C 0
-		device pci 15.1 on  end # I2C 1
-		device pci 15.2 on  end # I2C 2
-		device pci 15.3 on  end # I2C 3
+		device pci 15.0 off end # I2C 0
+		device pci 15.1 off end # I2C 1
+		device pci 15.2 off end # I2C 2
+		device pci 15.3 off end # I2C 3
 		device pci 16.0 on  end # HECI 1
 		device pci 16.1 off end # HECI 2
 		device pci 16.4 off end # HECI 3
 		device pci 16.5 off end # HECI 4
 		device pci 17.0 off end # SATA
-		device pci 19.0 on  end # I2C 4
+		device pci 19.0 off end # I2C 4
 		device pci 19.1 off end # I2C 5
 		device pci 19.2 on  end # UART 2
 		device pci 1a.0 on  end # eMMC
diff --git a/src/mainboard/google/dedede/variants/beadrix/overridetree.cb b/src/mainboard/google/dedede/variants/beadrix/overridetree.cb
index c4e550c172..cba95da235 100644
--- a/src/mainboard/google/dedede/variants/beadrix/overridetree.cb
+++ b/src/mainboard/google/dedede/variants/beadrix/overridetree.cb
@@ -54,14 +54,10 @@ chip soc/intel/jasperlake
 		},
 	}"
 
-	register "SerialIoI2cMode" = "{
-		[PchSerialIoIndexI2C0]  = PchSerialIoPci,
-		[PchSerialIoIndexI2C1]  = PchSerialIoDisabled,
-		[PchSerialIoIndexI2C2]  = PchSerialIoPci,
-		[PchSerialIoIndexI2C3]  = PchSerialIoDisabled,
-		[PchSerialIoIndexI2C4]  = PchSerialIoPci,
-		[PchSerialIoIndexI2C5]  = PchSerialIoPci,
-	}"
+	register "SerialIoI2cMode[PchSerialIoIndexI2C0]" = "PchSerialIoPci"
+	register "SerialIoI2cMode[PchSerialIoIndexI2C2]" = "PchSerialIoPci"
+	register "SerialIoI2cMode[PchSerialIoIndexI2C4]" = "PchSerialIoPci"
+	register "SerialIoI2cMode[PchSerialIoIndexI2C5]" = "PchSerialIoPci"
 
 	device domain 0 on
 		device pci 04.0 on
diff --git a/src/mainboard/google/dedede/variants/blipper/overridetree.cb b/src/mainboard/google/dedede/variants/blipper/overridetree.cb
index 4b42f0e3aa..db0bdc2049 100644
--- a/src/mainboard/google/dedede/variants/blipper/overridetree.cb
+++ b/src/mainboard/google/dedede/variants/blipper/overridetree.cb
@@ -50,14 +50,9 @@ chip soc/intel/jasperlake
 	register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)"	# UF Camera
 	register "usb2_ports[6]" = "USB2_PORT_EMPTY"	# Not Used
 
-	register "SerialIoI2cMode" = "{
-		[PchSerialIoIndexI2C0]  = PchSerialIoPci,
-		[PchSerialIoIndexI2C1]  = PchSerialIoDisabled,
-		[PchSerialIoIndexI2C2]  = PchSerialIoPci,
-		[PchSerialIoIndexI2C3]  = PchSerialIoDisabled,
-		[PchSerialIoIndexI2C4]  = PchSerialIoPci,
-		[PchSerialIoIndexI2C5]  = PchSerialIoDisabled,
-	}"
+	register "SerialIoI2cMode[PchSerialIoIndexI2C0]" = "PchSerialIoPci"
+	register "SerialIoI2cMode[PchSerialIoIndexI2C2]" = "PchSerialIoPci"
+	register "SerialIoI2cMode[PchSerialIoIndexI2C4]" = "PchSerialIoPci"
 
 	register "tcc_offset" = "10"    # TCC of 95C
 
@@ -126,7 +121,6 @@ chip soc/intel/jasperlake
 				device i2c 0x2c on end
 			end
 		end # I2C 0
-		device pci 15.1 off  end # I2C 1
 		device pci 15.2 on
 			chip drivers/i2c/hid
 				register "generic.hid" = ""GTCH7503""
@@ -164,7 +158,6 @@ chip soc/intel/jasperlake
 				device i2c 10 on end
 			end
 		end # I2C 2
-		device pci 15.3 off  end # I2C 3
 		device pci 19.0 on
 			chip drivers/i2c/generic
 				register "hid" = ""10EC5682""
diff --git a/src/mainboard/google/dedede/variants/boten/overridetree.cb b/src/mainboard/google/dedede/variants/boten/overridetree.cb
index 3e0e7b32fc..56b2d935bc 100644
--- a/src/mainboard/google/dedede/variants/boten/overridetree.cb
+++ b/src/mainboard/google/dedede/variants/boten/overridetree.cb
@@ -73,14 +73,11 @@ chip soc/intel/jasperlake
 	register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)"	# UF Camera
 	register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)"	# WF Camera
 
-	register "SerialIoI2cMode" = "{
-		[PchSerialIoIndexI2C0]  = PchSerialIoPci,
-		[PchSerialIoIndexI2C1]  = PchSerialIoPci,
-		[PchSerialIoIndexI2C2]  = PchSerialIoPci,
-		[PchSerialIoIndexI2C3]  = PchSerialIoDisabled,
-		[PchSerialIoIndexI2C4]  = PchSerialIoPci,
-		[PchSerialIoIndexI2C5]  = PchSerialIoPci,
-	}"
+	register "SerialIoI2cMode[PchSerialIoIndexI2C0]" = "PchSerialIoPci"
+	register "SerialIoI2cMode[PchSerialIoIndexI2C1]" = "PchSerialIoPci"
+	register "SerialIoI2cMode[PchSerialIoIndexI2C2]" = "PchSerialIoPci"
+	register "SerialIoI2cMode[PchSerialIoIndexI2C4]" = "PchSerialIoPci"
+	register "SerialIoI2cMode[PchSerialIoIndexI2C5]" = "PchSerialIoPci"
 
 	# Enable Acoustic noise mitigation and set slew rate to 1/8
 	# Rest of the parameters are 0 by default.
@@ -258,7 +255,6 @@ chip soc/intel/jasperlake
 				device i2c 10 on end
 			end
 		end # I2C 2
-		device pci 15.3 off  end # I2C 3
 		device pci 19.0 on
 			chip drivers/i2c/generic
 				register "hid" = ""10EC5682""
diff --git a/src/mainboard/google/dedede/variants/boxy/overridetree.cb b/src/mainboard/google/dedede/variants/boxy/overridetree.cb
index 36eadcbd1f..11c7ae399e 100644
--- a/src/mainboard/google/dedede/variants/boxy/overridetree.cb
+++ b/src/mainboard/google/dedede/variants/boxy/overridetree.cb
@@ -33,6 +33,8 @@ chip soc/intel/jasperlake
 		},
 	}"
 
+	register "SerialIoI2cMode[PchSerialIoIndexI2C4]" = "PchSerialIoPci"
+
 	# Power limit config
 	register "power_limits_config[JSL_N4500_6W_CORE]" = "{
 		.tdp_pl1_override = 6,
@@ -192,10 +194,6 @@ chip soc/intel/jasperlake
 				end
 			end
 		end # USB xHCI
-		device pci 15.0 off end # I2C 0
-		device pci 15.1 off end # I2C 1
-		device pci 15.2 off end # I2C 2
-		device pci 15.3 off end # I2C 3
 		device pci 19.0 on
 			chip drivers/i2c/generic
 				register "hid" = ""10EC5682""
diff --git a/src/mainboard/google/dedede/variants/bugzzy/overridetree.cb b/src/mainboard/google/dedede/variants/bugzzy/overridetree.cb
index 6c399f8768..a1303d7a4f 100644
--- a/src/mainboard/google/dedede/variants/bugzzy/overridetree.cb
+++ b/src/mainboard/google/dedede/variants/bugzzy/overridetree.cb
@@ -86,6 +86,13 @@ chip soc/intel/jasperlake
 			.fall_time_ns = 8,
 		},
 	}"
+
+	register "SerialIoI2cMode[PchSerialIoIndexI2C0]" = "PchSerialIoPci"
+	register "SerialIoI2cMode[PchSerialIoIndexI2C1]" = "PchSerialIoPci"
+	register "SerialIoI2cMode[PchSerialIoIndexI2C2]" = "PchSerialIoPci"
+	register "SerialIoI2cMode[PchSerialIoIndexI2C3]" = "PchSerialIoPci"
+	register "SerialIoI2cMode[PchSerialIoIndexI2C4]" = "PchSerialIoPci"
+
 	device domain 0 on
 		device pci 04.0 on
 			chip drivers/intel/dptf
diff --git a/src/mainboard/google/dedede/variants/cappy2/overridetree.cb b/src/mainboard/google/dedede/variants/cappy2/overridetree.cb
index e4e39f331d..2b361a3d93 100644
--- a/src/mainboard/google/dedede/variants/cappy2/overridetree.cb
+++ b/src/mainboard/google/dedede/variants/cappy2/overridetree.cb
@@ -41,6 +41,12 @@ chip soc/intel/jasperlake
 		},
 	}"
 
+	register "SerialIoI2cMode[PchSerialIoIndexI2C0]" = "PchSerialIoPci"
+	register "SerialIoI2cMode[PchSerialIoIndexI2C1]" = "PchSerialIoPci"
+	register "SerialIoI2cMode[PchSerialIoIndexI2C2]" = "PchSerialIoPci"
+	register "SerialIoI2cMode[PchSerialIoIndexI2C3]" = "PchSerialIoPci"
+	register "SerialIoI2cMode[PchSerialIoIndexI2C4]" = "PchSerialIoPci"
+
 	register "disable_external_bypass_vr" = "1"    # Does not support external vnn power rail
 	register "tcc_offset" = "10"    # TCC of 95C
 
diff --git a/src/mainboard/google/dedede/variants/corori/overridetree.cb b/src/mainboard/google/dedede/variants/corori/overridetree.cb
index ed4a0976a1..59afb06e93 100644
--- a/src/mainboard/google/dedede/variants/corori/overridetree.cb
+++ b/src/mainboard/google/dedede/variants/corori/overridetree.cb
@@ -17,14 +17,7 @@ chip soc/intel/jasperlake
 	register "usb3_ports[1]" = "USB3_PORT_EMPTY"	    # None
 	register "usb3_ports[3]" = "USB3_PORT_EMPTY"	    # None
 
-	register "SerialIoI2cMode" = "{
-		[PchSerialIoIndexI2C0]  = PchSerialIoPci,
-		[PchSerialIoIndexI2C1]  = PchSerialIoDisabled,
-		[PchSerialIoIndexI2C2]  = PchSerialIoDisabled,
-		[PchSerialIoIndexI2C3]  = PchSerialIoDisabled,
-		[PchSerialIoIndexI2C4]  = PchSerialIoPci,
-		[PchSerialIoIndexI2C5]  = PchSerialIoDisabled,
-	}"
+	register "SerialIoI2cMode[PchSerialIoIndexI2C0]" = "PchSerialIoPci"
 
 	# Intel Common SoC Config
 	#+-------------------+---------------------------+
@@ -120,9 +113,6 @@ chip soc/intel/jasperlake
 				device i2c 15 on end
 			end
 		end #I2C 0
-		device pci 15.1 off end # I2C 1
-		device pci 15.2 off end # I2C 2
-		device pci 15.3 off end # I2C 3
 		device pci 19.0 on
 			chip drivers/i2c/generic
 				register "hid" = ""10EC5682""
diff --git a/src/mainboard/google/dedede/variants/cret/overridetree.cb b/src/mainboard/google/dedede/variants/cret/overridetree.cb
index 1c834f411d..f1a00ffb20 100644
--- a/src/mainboard/google/dedede/variants/cret/overridetree.cb
+++ b/src/mainboard/google/dedede/variants/cret/overridetree.cb
@@ -18,14 +18,9 @@ chip soc/intel/jasperlake
 	register "usb3_ports[1]" = "USB3_PORT_EMPTY"	    # None
 	register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)"	# LTE
 
-	register "SerialIoI2cMode" = "{
-		[PchSerialIoIndexI2C0]  = PchSerialIoPci,
-		[PchSerialIoIndexI2C1]  = PchSerialIoDisabled,
-		[PchSerialIoIndexI2C2]  = PchSerialIoPci,
-		[PchSerialIoIndexI2C3]  = PchSerialIoDisabled,
-		[PchSerialIoIndexI2C4]  = PchSerialIoPci,
-		[PchSerialIoIndexI2C5]  = PchSerialIoDisabled,
-	}"
+	register "SerialIoI2cMode[PchSerialIoIndexI2C0]" = "PchSerialIoPci"
+	register "SerialIoI2cMode[PchSerialIoIndexI2C2]" = "PchSerialIoPci"
+	register "SerialIoI2cMode[PchSerialIoIndexI2C4]" = "PchSerialIoPci"
 
 	# Intel Common SoC Config
 	#+-------------------+---------------------------+
@@ -155,7 +150,6 @@ chip soc/intel/jasperlake
 				device i2c 2c on end
 			end
 		end #I2C 0
-		device pci 15.1 off  end # I2C 1
 		device pci 15.2 on
 			chip drivers/i2c/hid
 				register "generic.hid" = ""WDHT0002""
@@ -246,7 +240,6 @@ chip soc/intel/jasperlake
 				device i2c 40 on end
 			end
 		end # I2C 2
-		device pci 15.3 off  end # I2C 3
 		device pci 1c.7 on end
 		device pci 19.0 on
 			chip drivers/i2c/da7219
diff --git a/src/mainboard/google/dedede/variants/dexi/overridetree.cb b/src/mainboard/google/dedede/variants/dexi/overridetree.cb
index f53a11a89e..38a2d520a8 100644
--- a/src/mainboard/google/dedede/variants/dexi/overridetree.cb
+++ b/src/mainboard/google/dedede/variants/dexi/overridetree.cb
@@ -25,6 +25,8 @@ chip soc/intel/jasperlake
 		},
 	}"
 
+	register "SerialIoI2cMode[PchSerialIoIndexI2C4]" = "PchSerialIoPci"
+
 	# Power limit config
 	register "power_limits_config[JSL_N4500_6W_CORE]" = "{
 		.tdp_pl1_override = 6,
@@ -261,10 +263,6 @@ chip soc/intel/jasperlake
 				end
 			end
 		end # USB xHCI
-		device pci 15.0 off end # I2C 0
-		device pci 15.1 off end # I2C 1
-		device pci 15.2 off end # I2C 2
-		device pci 15.3 off end # I2C 3
 		device pci 19.0 on
 			chip drivers/i2c/generic
 				register "hid" = ""RTL5682""
diff --git a/src/mainboard/google/dedede/variants/dibbi/overridetree.cb b/src/mainboard/google/dedede/variants/dibbi/overridetree.cb
index c7d6afb495..eb05d24c94 100644
--- a/src/mainboard/google/dedede/variants/dibbi/overridetree.cb
+++ b/src/mainboard/google/dedede/variants/dibbi/overridetree.cb
@@ -25,6 +25,8 @@ chip soc/intel/jasperlake
 		},
 	}"
 
+	register "SerialIoI2cMode[PchSerialIoIndexI2C4]" = "PchSerialIoPci"
+
 	# Power limit config
 	register "power_limits_config[JSL_N4500_6W_CORE]" = "{
 		.tdp_pl1_override = 6,
@@ -228,10 +230,6 @@ chip soc/intel/jasperlake
 				end
 			end
 		end # USB xHCI
-		device pci 15.0 off end # I2C 0
-		device pci 15.1 off end # I2C 1
-		device pci 15.2 off end # I2C 2
-		device pci 15.3 off end # I2C 3
 		device pci 19.0 on
 			chip drivers/i2c/generic
 				register "hid" = ""RTL5682""
diff --git a/src/mainboard/google/dedede/variants/dita/overridetree.cb b/src/mainboard/google/dedede/variants/dita/overridetree.cb
index f53a11a89e..38a2d520a8 100644
--- a/src/mainboard/google/dedede/variants/dita/overridetree.cb
+++ b/src/mainboard/google/dedede/variants/dita/overridetree.cb
@@ -25,6 +25,8 @@ chip soc/intel/jasperlake
 		},
 	}"
 
+	register "SerialIoI2cMode[PchSerialIoIndexI2C4]" = "PchSerialIoPci"
+
 	# Power limit config
 	register "power_limits_config[JSL_N4500_6W_CORE]" = "{
 		.tdp_pl1_override = 6,
@@ -261,10 +263,6 @@ chip soc/intel/jasperlake
 				end
 			end
 		end # USB xHCI
-		device pci 15.0 off end # I2C 0
-		device pci 15.1 off end # I2C 1
-		device pci 15.2 off end # I2C 2
-		device pci 15.3 off end # I2C 3
 		device pci 19.0 on
 			chip drivers/i2c/generic
 				register "hid" = ""RTL5682""
diff --git a/src/mainboard/google/dedede/variants/drawcia/overridetree.cb b/src/mainboard/google/dedede/variants/drawcia/overridetree.cb
index c84f9487fe..3ba688fb67 100644
--- a/src/mainboard/google/dedede/variants/drawcia/overridetree.cb
+++ b/src/mainboard/google/dedede/variants/drawcia/overridetree.cb
@@ -67,6 +67,12 @@ chip soc/intel/jasperlake
 		},
 	}"
 
+	register "SerialIoI2cMode[PchSerialIoIndexI2C0]" = "PchSerialIoPci"
+	register "SerialIoI2cMode[PchSerialIoIndexI2C1]" = "PchSerialIoPci"
+	register "SerialIoI2cMode[PchSerialIoIndexI2C2]" = "PchSerialIoPci"
+	register "SerialIoI2cMode[PchSerialIoIndexI2C3]" = "PchSerialIoPci"
+	register "SerialIoI2cMode[PchSerialIoIndexI2C4]" = "PchSerialIoPci"
+
 	register "tcc_offset" = "20"	# TCC of 85C
 
 	# Enable Acoustic noise mitigation and set slew rate to 1/4
diff --git a/src/mainboard/google/dedede/variants/driblee/overridetree.cb b/src/mainboard/google/dedede/variants/driblee/overridetree.cb
index 3c9c92c98e..a703ada882 100644
--- a/src/mainboard/google/dedede/variants/driblee/overridetree.cb
+++ b/src/mainboard/google/dedede/variants/driblee/overridetree.cb
@@ -9,14 +9,8 @@ chip soc/intel/jasperlake
 	register "usb3_ports[1]" = "USB3_PORT_EMPTY"	    # None
 	register "usb3_ports[3]" = "USB3_PORT_EMPTY"	    # None
 
-	register "SerialIoI2cMode" = "{
-		[PchSerialIoIndexI2C0]  = PchSerialIoPci,
-		[PchSerialIoIndexI2C1]  = PchSerialIoDisabled,
-		[PchSerialIoIndexI2C2]  = PchSerialIoDisabled,
-		[PchSerialIoIndexI2C3]  = PchSerialIoDisabled,
-		[PchSerialIoIndexI2C4]  = PchSerialIoPci,
-		[PchSerialIoIndexI2C5]  = PchSerialIoDisabled,
-	}"
+	register "SerialIoI2cMode[PchSerialIoIndexI2C0]" = "PchSerialIoPci"
+	register "SerialIoI2cMode[PchSerialIoIndexI2C4]" = "PchSerialIoPci"
 
 	# Intel Common SoC Config
 	#+-------------------+---------------------------+
@@ -119,9 +113,6 @@ chip soc/intel/jasperlake
 				device i2c 2c on end
 			end
 		end #I2C 0
-		device pci 15.1 off end # I2C 1
-		device pci 15.2 off end # I2C 2
-		device pci 15.3 off end # I2C 3
 		device pci 19.0 on
 			chip drivers/i2c/cs42l42
 				register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_D16)"
diff --git a/src/mainboard/google/dedede/variants/galtic/overridetree.cb b/src/mainboard/google/dedede/variants/galtic/overridetree.cb
index 0ef9cdb5da..3a5597c3f4 100644
--- a/src/mainboard/google/dedede/variants/galtic/overridetree.cb
+++ b/src/mainboard/google/dedede/variants/galtic/overridetree.cb
@@ -59,13 +59,9 @@ chip soc/intel/jasperlake
 		},
 	}"
 
-	register "SerialIoI2cMode" = "{
-		[PchSerialIoIndexI2C0]  = PchSerialIoPci,
-		[PchSerialIoIndexI2C1]  = PchSerialIoDisabled,
-		[PchSerialIoIndexI2C2]  = PchSerialIoPci,
-		[PchSerialIoIndexI2C3]  = PchSerialIoDisabled,
-		[PchSerialIoIndexI2C4]  = PchSerialIoPci,
-	}"
+	register "SerialIoI2cMode[PchSerialIoIndexI2C0]" = "PchSerialIoPci"
+	register "SerialIoI2cMode[PchSerialIoIndexI2C2]" = "PchSerialIoPci"
+	register "SerialIoI2cMode[PchSerialIoIndexI2C4]" = "PchSerialIoPci"
 
 	# USB Port Configuration
 	register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)"     # Camera
diff --git a/src/mainboard/google/dedede/variants/gooey/overridetree.cb b/src/mainboard/google/dedede/variants/gooey/overridetree.cb
index 728ab919e1..d7e9d47241 100644
--- a/src/mainboard/google/dedede/variants/gooey/overridetree.cb
+++ b/src/mainboard/google/dedede/variants/gooey/overridetree.cb
@@ -49,14 +49,11 @@ chip soc/intel/jasperlake
 	register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)"	# UF Camera
 	register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)"	# WF Camera
 
-	register "SerialIoI2cMode" = "{
-		[PchSerialIoIndexI2C0]  = PchSerialIoPci,
-		[PchSerialIoIndexI2C1]  = PchSerialIoPci,
-		[PchSerialIoIndexI2C2]  = PchSerialIoPci,
-		[PchSerialIoIndexI2C3]  = PchSerialIoDisabled,
-		[PchSerialIoIndexI2C4]  = PchSerialIoPci,
-		[PchSerialIoIndexI2C5]  = PchSerialIoPci,
-	}"
+	register "SerialIoI2cMode[PchSerialIoIndexI2C0]" = "PchSerialIoPci"
+	register "SerialIoI2cMode[PchSerialIoIndexI2C1]" = "PchSerialIoPci"
+	register "SerialIoI2cMode[PchSerialIoIndexI2C2]" = "PchSerialIoPci"
+	register "SerialIoI2cMode[PchSerialIoIndexI2C4]" = "PchSerialIoPci"
+	register "SerialIoI2cMode[PchSerialIoIndexI2C5]" = "PchSerialIoPci"
 
 	register "SerialIoGSpiMode[PchSerialIoIndexGSPI0]" = "PchSerialIoDisabled" # Disable GSPI0
 	register "SerialIoGSpiCsMode[PchSerialIoIndexGSPI0]" = "0"
@@ -237,7 +234,6 @@ chip soc/intel/jasperlake
 				device i2c 10 on end
 			end
 		end # I2C 2
-		device pci 15.3 off  end # I2C 3
 		device pci 19.0 on
 			chip drivers/i2c/generic
 				register "hid" = ""10EC5682""
diff --git a/src/mainboard/google/dedede/variants/haboki/overridetree.cb b/src/mainboard/google/dedede/variants/haboki/overridetree.cb
index 92b3bb2c48..030b143204 100644
--- a/src/mainboard/google/dedede/variants/haboki/overridetree.cb
+++ b/src/mainboard/google/dedede/variants/haboki/overridetree.cb
@@ -35,6 +35,12 @@ chip soc/intel/jasperlake
 		},
 	}"
 
+	register "SerialIoI2cMode[PchSerialIoIndexI2C0]" = "PchSerialIoPci"
+	register "SerialIoI2cMode[PchSerialIoIndexI2C1]" = "PchSerialIoPci"
+	register "SerialIoI2cMode[PchSerialIoIndexI2C2]" = "PchSerialIoPci"
+	register "SerialIoI2cMode[PchSerialIoIndexI2C3]" = "PchSerialIoPci"
+	register "SerialIoI2cMode[PchSerialIoIndexI2C4]" = "PchSerialIoPci"
+
 	register "tcc_offset" = "20"	# TCC of 85C
 
 	register "SerialIoGSpiMode[PchSerialIoIndexGSPI0]" = "PchSerialIoDisabled" # Disable GSPI0
diff --git a/src/mainboard/google/dedede/variants/kracko/overridetree.cb b/src/mainboard/google/dedede/variants/kracko/overridetree.cb
index e4d9ad966e..388850570b 100644
--- a/src/mainboard/google/dedede/variants/kracko/overridetree.cb
+++ b/src/mainboard/google/dedede/variants/kracko/overridetree.cb
@@ -11,14 +11,11 @@ chip soc/intel/jasperlake
 	register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)"     # Camera
 	register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)"     # WF Camera
 
-	register "SerialIoI2cMode" = "{
-		[PchSerialIoIndexI2C0]  = PchSerialIoPci,
-		[PchSerialIoIndexI2C1]  = PchSerialIoPci,
-		[PchSerialIoIndexI2C2]  = PchSerialIoPci,
-		[PchSerialIoIndexI2C3]  = PchSerialIoDisabled,
-		[PchSerialIoIndexI2C4]  = PchSerialIoPci,
-		[PchSerialIoIndexI2C5]  = PchSerialIoPci,
-	}"
+	register "SerialIoI2cMode[PchSerialIoIndexI2C0]" = "PchSerialIoPci"
+	register "SerialIoI2cMode[PchSerialIoIndexI2C1]" = "PchSerialIoPci"
+	register "SerialIoI2cMode[PchSerialIoIndexI2C2]" = "PchSerialIoPci"
+	register "SerialIoI2cMode[PchSerialIoIndexI2C4]" = "PchSerialIoPci"
+	register "SerialIoI2cMode[PchSerialIoIndexI2C5]" = "PchSerialIoPci"
 
 	# Intel Common SoC Config
 	#+-------------------+---------------------------+
@@ -244,7 +241,6 @@ chip soc/intel/jasperlake
                         end
 
 		end # I2C 2
-		device pci 15.3 off  end #I2C 3
 		device pci 19.0 on
 			chip drivers/i2c/generic
 				register "hid" = ""10EC5682""
diff --git a/src/mainboard/google/dedede/variants/lalala/overridetree.cb b/src/mainboard/google/dedede/variants/lalala/overridetree.cb
index 9609011a0c..90620d6c7d 100644
--- a/src/mainboard/google/dedede/variants/lalala/overridetree.cb
+++ b/src/mainboard/google/dedede/variants/lalala/overridetree.cb
@@ -56,6 +56,12 @@ chip soc/intel/jasperlake
 		},
 	}"
 
+	register "SerialIoI2cMode[PchSerialIoIndexI2C0]" = "PchSerialIoPci"
+	register "SerialIoI2cMode[PchSerialIoIndexI2C1]" = "PchSerialIoPci"
+	register "SerialIoI2cMode[PchSerialIoIndexI2C2]" = "PchSerialIoPci"
+	register "SerialIoI2cMode[PchSerialIoIndexI2C3]" = "PchSerialIoPci"
+	register "SerialIoI2cMode[PchSerialIoIndexI2C4]" = "PchSerialIoPci"
+
 	# Power limit config
 	register "power_limits_config[JSL_N4500_6W_CORE]" = "{
 		.tdp_pl1_override = 7,
diff --git a/src/mainboard/google/dedede/variants/lantis/overridetree.cb b/src/mainboard/google/dedede/variants/lantis/overridetree.cb
index 5f6ed2368b..c21ccf2643 100644
--- a/src/mainboard/google/dedede/variants/lantis/overridetree.cb
+++ b/src/mainboard/google/dedede/variants/lantis/overridetree.cb
@@ -15,14 +15,9 @@ chip soc/intel/jasperlake
 	# USB Port Configuration
 	register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)"     # Camera
 
-	register "SerialIoI2cMode" = "{
-		[PchSerialIoIndexI2C0]  = PchSerialIoPci,
-		[PchSerialIoIndexI2C1]  = PchSerialIoDisabled,
-		[PchSerialIoIndexI2C2]  = PchSerialIoPci,
-		[PchSerialIoIndexI2C3]  = PchSerialIoDisabled,
-		[PchSerialIoIndexI2C4]  = PchSerialIoPci,
-		[PchSerialIoIndexI2C5]  = PchSerialIoDisabled,
-	}"
+	register "SerialIoI2cMode[PchSerialIoIndexI2C0]" = "PchSerialIoPci"
+	register "SerialIoI2cMode[PchSerialIoIndexI2C2]" = "PchSerialIoPci"
+	register "SerialIoI2cMode[PchSerialIoIndexI2C4]" = "PchSerialIoPci"
 
 	# Intel Common SoC Config
 	#+-------------------+---------------------------+
@@ -180,7 +175,6 @@ chip soc/intel/jasperlake
 				device i2c 15 on end
 			end
 		end #I2C 0
-		device pci 15.1 off  end #I2C 1
 		device pci 15.2 on
 			chip drivers/i2c/generic
 				register "hid" = ""ELAN0001""
@@ -240,7 +234,6 @@ chip soc/intel/jasperlake
 				device i2c 0x5d on end
 			end
 		end # I2C 2
-		device pci 15.3 off  end #I2C 3
 		device pci 1c.7 on
 			chip drivers/wifi/generic
 				register "wake" = "GPE0_DW2_03"
diff --git a/src/mainboard/google/dedede/variants/madoo/overridetree.cb b/src/mainboard/google/dedede/variants/madoo/overridetree.cb
index 437c60a5cd..c69b482ef0 100644
--- a/src/mainboard/google/dedede/variants/madoo/overridetree.cb
+++ b/src/mainboard/google/dedede/variants/madoo/overridetree.cb
@@ -3,14 +3,9 @@ chip soc/intel/jasperlake
 	# USB Port Configuration
 	register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)"	# Camera
 
-	register "SerialIoI2cMode" = "{
-		[PchSerialIoIndexI2C0]  = PchSerialIoPci,
-		[PchSerialIoIndexI2C1]  = PchSerialIoDisabled,
-		[PchSerialIoIndexI2C2]  = PchSerialIoPci,
-		[PchSerialIoIndexI2C3]  = PchSerialIoDisabled,
-		[PchSerialIoIndexI2C4]  = PchSerialIoPci,
-		[PchSerialIoIndexI2C5]  = PchSerialIoDisabled,
-	}"
+	register "SerialIoI2cMode[PchSerialIoIndexI2C0]" = "PchSerialIoPci"
+	register "SerialIoI2cMode[PchSerialIoIndexI2C2]" = "PchSerialIoPci"
+	register "SerialIoI2cMode[PchSerialIoIndexI2C4]" = "PchSerialIoPci"
 
 	# Intel Common SoC Config
 	#+-------------------+---------------------------+
@@ -114,7 +109,6 @@ chip soc/intel/jasperlake
 				device i2c 15 on end
 			end
 		end #I2C 0
-		device pci 15.1 off  end # I2C 1
 		device pci 15.2 on
 			chip drivers/i2c/hid
 				register "generic.hid" = ""GDIX0000""
@@ -132,7 +126,6 @@ chip soc/intel/jasperlake
 				device i2c 0x5d on end
 			end
 		end # I2C 2
-		device pci 15.3 off  end # I2C 3
 		device pci 1c.7 on
 			chip drivers/wifi/generic
 				register "wake" = "GPE0_DW2_03"
diff --git a/src/mainboard/google/dedede/variants/magolor/overridetree.cb b/src/mainboard/google/dedede/variants/magolor/overridetree.cb
index a09adeeff2..c32429dc24 100644
--- a/src/mainboard/google/dedede/variants/magolor/overridetree.cb
+++ b/src/mainboard/google/dedede/variants/magolor/overridetree.cb
@@ -95,6 +95,12 @@ chip soc/intel/jasperlake
 		},
 	}"
 
+	register "SerialIoI2cMode[PchSerialIoIndexI2C0]" = "PchSerialIoPci"
+	register "SerialIoI2cMode[PchSerialIoIndexI2C1]" = "PchSerialIoPci"
+	register "SerialIoI2cMode[PchSerialIoIndexI2C2]" = "PchSerialIoPci"
+	register "SerialIoI2cMode[PchSerialIoIndexI2C3]" = "PchSerialIoPci"
+	register "SerialIoI2cMode[PchSerialIoIndexI2C4]" = "PchSerialIoPci"
+
 	# Power limit config
 	register "power_limits_config[JSL_N4500_6W_CORE]" = "{
 		.tdp_pl1_override = 7,
diff --git a/src/mainboard/google/dedede/variants/metaknight/overridetree.cb b/src/mainboard/google/dedede/variants/metaknight/overridetree.cb
index d50fb7c59d..c116cccdae 100644
--- a/src/mainboard/google/dedede/variants/metaknight/overridetree.cb
+++ b/src/mainboard/google/dedede/variants/metaknight/overridetree.cb
@@ -62,14 +62,10 @@ chip soc/intel/jasperlake
 		},
 	}"
 
-	register "SerialIoI2cMode" = "{
-		[PchSerialIoIndexI2C0]  = PchSerialIoPci,
-		[PchSerialIoIndexI2C1]  = PchSerialIoPci,
-		[PchSerialIoIndexI2C2]  = PchSerialIoPci,
-		[PchSerialIoIndexI2C3]  = PchSerialIoDisabled,
-		[PchSerialIoIndexI2C4]  = PchSerialIoPci,
-		[PchSerialIoIndexI2C5]  = PchSerialIoDisabled,
-	}"
+	register "SerialIoI2cMode[PchSerialIoIndexI2C0]" = "PchSerialIoPci"
+	register "SerialIoI2cMode[PchSerialIoIndexI2C1]" = "PchSerialIoPci"
+	register "SerialIoI2cMode[PchSerialIoIndexI2C2]" = "PchSerialIoPci"
+	register "SerialIoI2cMode[PchSerialIoIndexI2C4]" = "PchSerialIoPci"
 
 	# Power limit config
 	register "power_limits_config[JSL_N4500_6W_CORE]" = "{
@@ -243,7 +239,6 @@ chip soc/intel/jasperlake
 				device i2c 15 on end
 			end
 		end # I2C 2
-		device pci 15.3 off  end # I2C 3
 		device pci 19.0 on
 			chip drivers/i2c/generic
 				register "hid" = ""10EC5682""
diff --git a/src/mainboard/google/dedede/variants/pirika/overridetree.cb b/src/mainboard/google/dedede/variants/pirika/overridetree.cb
index cf1f95e722..d413e060e0 100644
--- a/src/mainboard/google/dedede/variants/pirika/overridetree.cb
+++ b/src/mainboard/google/dedede/variants/pirika/overridetree.cb
@@ -46,13 +46,9 @@ chip soc/intel/jasperlake
 		},
 	}"
 
-	register "SerialIoI2cMode" = "{
-		[PchSerialIoIndexI2C0]  = PchSerialIoPci,
-		[PchSerialIoIndexI2C1]  = PchSerialIoDisabled,
-		[PchSerialIoIndexI2C2]  = PchSerialIoPci,
-		[PchSerialIoIndexI2C3]  = PchSerialIoDisabled,
-		[PchSerialIoIndexI2C4]  = PchSerialIoPci,
-	}"
+	register "SerialIoI2cMode[PchSerialIoIndexI2C0]" = "PchSerialIoPci"
+	register "SerialIoI2cMode[PchSerialIoIndexI2C2]" = "PchSerialIoPci"
+	register "SerialIoI2cMode[PchSerialIoIndexI2C4]" = "PchSerialIoPci"
 
 	# USB Port Configuration
 	register "usb2_ports[0]" = "{
diff --git a/src/mainboard/google/dedede/variants/sasuke/overridetree.cb b/src/mainboard/google/dedede/variants/sasuke/overridetree.cb
index 0da00caef2..6f72562fe9 100644
--- a/src/mainboard/google/dedede/variants/sasuke/overridetree.cb
+++ b/src/mainboard/google/dedede/variants/sasuke/overridetree.cb
@@ -77,6 +77,13 @@ chip soc/intel/jasperlake
 			.fall_time_ns = 8,
 		},
 	}"
+
+	register "SerialIoI2cMode[PchSerialIoIndexI2C0]" = "PchSerialIoPci"
+	register "SerialIoI2cMode[PchSerialIoIndexI2C1]" = "PchSerialIoPci"
+	register "SerialIoI2cMode[PchSerialIoIndexI2C2]" = "PchSerialIoPci"
+	register "SerialIoI2cMode[PchSerialIoIndexI2C3]" = "PchSerialIoPci"
+	register "SerialIoI2cMode[PchSerialIoIndexI2C4]" = "PchSerialIoPci"
+
 	device domain 0 on
 		device pci 04.0 on
 			chip drivers/intel/dptf
diff --git a/src/mainboard/google/dedede/variants/sasukette/overridetree.cb b/src/mainboard/google/dedede/variants/sasukette/overridetree.cb
index ba262b6282..aa61b8e11d 100644
--- a/src/mainboard/google/dedede/variants/sasukette/overridetree.cb
+++ b/src/mainboard/google/dedede/variants/sasukette/overridetree.cb
@@ -59,6 +59,12 @@ chip soc/intel/jasperlake
 		},
 	}"
 
+	register "SerialIoI2cMode[PchSerialIoIndexI2C0]" = "PchSerialIoPci"
+	register "SerialIoI2cMode[PchSerialIoIndexI2C1]" = "PchSerialIoPci"
+	register "SerialIoI2cMode[PchSerialIoIndexI2C2]" = "PchSerialIoPci"
+	register "SerialIoI2cMode[PchSerialIoIndexI2C3]" = "PchSerialIoPci"
+	register "SerialIoI2cMode[PchSerialIoIndexI2C4]" = "PchSerialIoPci"
+
 	# USB Port Configuration
 	register "usb2_ports[2]" = "{
 		.enable = 1,
diff --git a/src/mainboard/google/dedede/variants/shotzo/overridetree.cb b/src/mainboard/google/dedede/variants/shotzo/overridetree.cb
index 0935457092..7a821d7f8f 100644
--- a/src/mainboard/google/dedede/variants/shotzo/overridetree.cb
+++ b/src/mainboard/google/dedede/variants/shotzo/overridetree.cb
@@ -38,6 +38,10 @@ chip soc/intel/jasperlake
 		},
 	}"
 
+	register "SerialIoI2cMode[PchSerialIoIndexI2C1]" = "PchSerialIoPci"
+	register "SerialIoI2cMode[PchSerialIoIndexI2C2]" = "PchSerialIoPci"
+	register "SerialIoI2cMode[PchSerialIoIndexI2C4]" = "PchSerialIoPci"
+
 	register "disable_external_bypass_vr" = "1"    # Does not support external vnn power rail
 
 	# Power limit config
@@ -183,7 +187,6 @@ chip soc/intel/jasperlake
 				end
 			end
 		end # USB xHCI
-		device pci 15.0 off end # I2C 0
 		device pci 15.2 on
 			chip drivers/i2c/hid
 				register "generic.hid" = ""ILTK0001""
@@ -200,7 +203,6 @@ chip soc/intel/jasperlake
 				device i2c 41 on end
 			end
 		end # I2C 2
-		device pci 15.3 off  end #I2C 3
 		device pci 1c.7 on
 			chip drivers/wifi/generic
 				register "wake" = "GPE0_DW2_03"
diff --git a/src/mainboard/google/dedede/variants/storo/overridetree.cb b/src/mainboard/google/dedede/variants/storo/overridetree.cb
index c22c796f68..f893829dc0 100644
--- a/src/mainboard/google/dedede/variants/storo/overridetree.cb
+++ b/src/mainboard/google/dedede/variants/storo/overridetree.cb
@@ -73,14 +73,11 @@ chip soc/intel/jasperlake
 		.pre_emp_bit   = USB2_HALF_BIT_PRE_EMP,
 	}" # WWAN
 
-	register "SerialIoI2cMode" = "{
-		[PchSerialIoIndexI2C0] = PchSerialIoPci,
-		[PchSerialIoIndexI2C1] = PchSerialIoDisabled,
-		[PchSerialIoIndexI2C2] = PchSerialIoPci,
-		[PchSerialIoIndexI2C3] = PchSerialIoPci,
-		[PchSerialIoIndexI2C4] = PchSerialIoPci,
-		[PchSerialIoIndexI2C5] = PchSerialIoPci,
-	}"
+	register "SerialIoI2cMode[PchSerialIoIndexI2C0]" = "PchSerialIoPci"
+	register "SerialIoI2cMode[PchSerialIoIndexI2C2]" = "PchSerialIoPci"
+	register "SerialIoI2cMode[PchSerialIoIndexI2C3]" = "PchSerialIoPci"
+	register "SerialIoI2cMode[PchSerialIoIndexI2C4]" = "PchSerialIoPci"
+	register "SerialIoI2cMode[PchSerialIoIndexI2C5]" = "PchSerialIoPci"
 
 	# Power limit config
 	register "power_limits_config[JSL_N4500_6W_CORE]" = "{
diff --git a/src/mainboard/google/dedede/variants/taranza/overridetree.cb b/src/mainboard/google/dedede/variants/taranza/overridetree.cb
index f53a11a89e..38a2d520a8 100644
--- a/src/mainboard/google/dedede/variants/taranza/overridetree.cb
+++ b/src/mainboard/google/dedede/variants/taranza/overridetree.cb
@@ -25,6 +25,8 @@ chip soc/intel/jasperlake
 		},
 	}"
 
+	register "SerialIoI2cMode[PchSerialIoIndexI2C4]" = "PchSerialIoPci"
+
 	# Power limit config
 	register "power_limits_config[JSL_N4500_6W_CORE]" = "{
 		.tdp_pl1_override = 6,
@@ -261,10 +263,6 @@ chip soc/intel/jasperlake
 				end
 			end
 		end # USB xHCI
-		device pci 15.0 off end # I2C 0
-		device pci 15.1 off end # I2C 1
-		device pci 15.2 off end # I2C 2
-		device pci 15.3 off end # I2C 3
 		device pci 19.0 on
 			chip drivers/i2c/generic
 				register "hid" = ""RTL5682""
diff --git a/src/mainboard/google/dedede/variants/waddledee/overridetree.cb b/src/mainboard/google/dedede/variants/waddledee/overridetree.cb
index c177a8b32e..4fdddd18cc 100644
--- a/src/mainboard/google/dedede/variants/waddledee/overridetree.cb
+++ b/src/mainboard/google/dedede/variants/waddledee/overridetree.cb
@@ -54,6 +54,12 @@ chip soc/intel/jasperlake
 		},
 	}"
 
+	register "SerialIoI2cMode[PchSerialIoIndexI2C0]" = "PchSerialIoPci"
+	register "SerialIoI2cMode[PchSerialIoIndexI2C1]" = "PchSerialIoPci"
+	register "SerialIoI2cMode[PchSerialIoIndexI2C2]" = "PchSerialIoPci"
+	register "SerialIoI2cMode[PchSerialIoIndexI2C3]" = "PchSerialIoPci"
+	register "SerialIoI2cMode[PchSerialIoIndexI2C4]" = "PchSerialIoPci"
+
 	device domain 0 on
 		device pci 05.0 on end # IPU - MIPI Camera
 		device pci 14.0 on
diff --git a/src/mainboard/google/dedede/variants/waddledoo/overridetree.cb b/src/mainboard/google/dedede/variants/waddledoo/overridetree.cb
index 321b05eda5..8a1d5556c1 100644
--- a/src/mainboard/google/dedede/variants/waddledoo/overridetree.cb
+++ b/src/mainboard/google/dedede/variants/waddledoo/overridetree.cb
@@ -49,6 +49,13 @@ chip soc/intel/jasperlake
 			}
 		},
 	}"
+
+	register "SerialIoI2cMode[PchSerialIoIndexI2C0]" = "PchSerialIoPci"
+	register "SerialIoI2cMode[PchSerialIoIndexI2C1]" = "PchSerialIoPci"
+	register "SerialIoI2cMode[PchSerialIoIndexI2C2]" = "PchSerialIoPci"
+	register "SerialIoI2cMode[PchSerialIoIndexI2C3]" = "PchSerialIoPci"
+	register "SerialIoI2cMode[PchSerialIoIndexI2C4]" = "PchSerialIoPci"
+
 	device domain 0 on
 		device pci 05.0 on # IPU - MIPI Camera
 			chip drivers/intel/mipi_camera

From a09f541e0349486262527347a0b487374c47a380 Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Sun, 25 Jan 2026 18:28:33 -0600
Subject: [PATCH 3156/3886] mb/google/dedede: Disable PCIe RP8 by default

All variants which use a discrete (vs CNVi) WiFi module enable
RP8 (or RP7) in their overridetree, so enabling RP8 in the baseboard
is superfluous. Additionally, disabling it in the baseboard makes
things cleaner when switching to using chipset devicetree references
in a subsequent patch.

Change-Id: I591508e5c41f2019a6360e08c89b0a4982178a07
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90898
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
---
 src/mainboard/google/dedede/variants/baseboard/devicetree.cb | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb
index 2ce85b2813..05c77da3e5 100644
--- a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb
+++ b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb
@@ -389,7 +389,7 @@ chip soc/intel/jasperlake
 		device pci 1c.5 off end # PCI Express Root Port 6
 		device pci 1c.6 off end # PCI Express Root Port 7
 		# External PCIe port 4 is mapped to PCIe Root port 8
-		device pci 1c.7 on  end # PCI Express Root Port 8 - hosts M.2 E-key WLAN
+		device pci 1c.7 off end # PCI Express Root Port 8 - hosts M.2 E-key WLAN
 		device pci 1e.0 off end # UART 0
 		device pci 1e.1 off end # UART 1
 		device pci 1e.2 on

From 0d183076401d6314664f1eb0b69d7fefa9afda52 Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Mon, 26 Jan 2026 09:47:11 -0600
Subject: [PATCH 3157/3886] device/pciexp: Make aspm_type_str pointer const

Fix checkpatch warning by changing aspm_type_str array to use
'static const char * const' instead of 'static const char *'.

Change-Id: Id1082447e309b840c965326a74c4ab00f3a1536c
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90914
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
---
 src/device/pciexp_device.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/device/pciexp_device.c b/src/device/pciexp_device.c
index 1b8f8ad79b..ec90a22b74 100644
--- a/src/device/pciexp_device.c
+++ b/src/device/pciexp_device.c
@@ -569,7 +569,7 @@ static int pciexp_aspm_latency(struct device *root, unsigned int root_cap,
 static void pciexp_enable_aspm(struct device *root, unsigned int root_cap,
 					 struct device *endp, unsigned int endp_cap)
 {
-	const char *aspm_type_str[] = { "None", "L0s", "L1", "L0s and L1" };
+	static const char * const aspm_type_str[] = { "None", "L0s", "L1", "L0s and L1" };
 	enum aspm_type apmc = PCIE_ASPM_NONE;
 	int exit_latency, ok_latency;
 	u16 lnkctl;

From a2a868f199c53f96f71a0cc85f4667cad4186f33 Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Mon, 26 Jan 2026 09:41:42 -0600
Subject: [PATCH 3158/3886] device/pciexp: Enable ASPM on root ports without
 endpoints

Program ASPM on PCIe root ports when no endpoint device is connected
at boot. This ensures proper power management for TBT ports that often
do not have devices connected at boot.

Add pciexp_enable_aspm_root_port_only() to program ASPM based on the
root port's Link Capabilities, and call it from pciexp_scan_bus() when
no children are detected on a root port.

TEST=build/boot Starlabs Starfighter MTL, verify ASPM enabled on TBT
ports even when no devices attached via lspci:
  LnkCtrl: ASPM L1 Enabled

Change-Id: I1da6d36afcbe18411c01ceabf8b903c4ae13cd73
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90913
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
---
 src/device/pciexp_device.c | 49 ++++++++++++++++++++++++++++++++++++++
 1 file changed, 49 insertions(+)

diff --git a/src/device/pciexp_device.c b/src/device/pciexp_device.c
index ec90a22b74..3c2f06e013 100644
--- a/src/device/pciexp_device.c
+++ b/src/device/pciexp_device.c
@@ -563,6 +563,42 @@ static int pciexp_aspm_latency(struct device *root, unsigned int root_cap,
 	return (endp_lat > root_lat) ? endp_lat : root_lat;
 }
 
+/*
+ * Enable ASPM on PCIe root port when no endpoint is connected.
+ * This programs ASPM based on the root port's own capabilities.
+ */
+static void pciexp_enable_aspm_root_port_only(struct device *root, unsigned int root_cap)
+{
+	static const char * const aspm_type_str[] = { "None", "L0s", "L1", "L0s and L1" };
+	enum aspm_type apmc = PCIE_ASPM_NONE;
+	u16 lnkctl;
+	u32 lnkcap;
+
+	/* Read root port's ASPM support from Link Capabilities */
+	lnkcap = pci_read_config32(root, root_cap + PCI_EXP_LNKCAP);
+
+	/* Extract ASPM support bits (11:10) */
+	u32 aspm_support = (lnkcap & PCI_EXP_LNKCAP_ASPMS) >> 10;
+
+	/* Map ASPM support to control value:
+	 * 00 = No ASPM -> apmc = 0 (NONE)
+	 * 01 = L0s supported -> apmc = 1 (L0S)
+	 * 10 = L1 supported -> apmc = 2 (L1)
+	 * 11 = L0s and L1 supported -> apmc = 3 (BOTH)
+	 */
+	apmc = (enum aspm_type)aspm_support;
+
+	if (apmc != PCIE_ASPM_NONE) {
+		/* Set ASPM control in root port's Link Control register */
+		lnkctl = pci_read_config16(root, root_cap + PCI_EXP_LNKCTL);
+		/* Clear existing ASPM bits (0:1) and set new value */
+		lnkctl = (lnkctl & ~0x3) | apmc;
+		pci_write_config16(root, root_cap + PCI_EXP_LNKCTL, lnkctl);
+		printk(BIOS_INFO, "%s: ASPM enabled %s (no endpoint)\n",
+		       dev_path(root), aspm_type_str[apmc]);
+	}
+}
+
 /*
  * Enable ASPM on PCIe root port and endpoint.
  */
@@ -843,6 +879,8 @@ void pciexp_scan_bus(struct bus *bus, unsigned int min_devfn,
 {
 	struct device *child;
 	unsigned int max_payload;
+	bool has_children = false;
+	unsigned int root_cap;
 
 	pciexp_enable_ltr(bus->dev);
 
@@ -862,9 +900,20 @@ void pciexp_scan_bus(struct bus *bus, unsigned int min_devfn,
 		    (child->path.pci.devfn > max_devfn)) {
 			continue;
 		}
+		has_children = true;
 		pciexp_tune_dev(child);
 	}
 
+	/*
+	 * If no endpoint is connected and this is a root port, program ASPM
+	 * based on the root port's own capabilities.
+	 */
+	if (!has_children && pcie_is_root_port(bus->dev) && CONFIG(PCIEXP_ASPM)) {
+		root_cap = pci_find_capability(bus->dev, PCI_CAP_ID_PCIE);
+		if (root_cap)
+			pciexp_enable_aspm_root_port_only(bus->dev, root_cap);
+	}
+
 	/*
 	 * Now the root port's Max Payload Size should be set to the highest
 	 * possible value supported by all devices under a given root port.

From 7ce04e929137f661b5aaa1bdab5f11abe420aa89 Mon Sep 17 00:00:00 2001
From: Vladimir Epifantsev <volatilefield@outlook.com>
Date: Mon, 8 Sep 2025 00:11:43 +0200
Subject: [PATCH 3159/3886] util/inteltool: improve support for Comet Lake-U/H
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Add support for MCH, spi and bios_cntrl, LPC/eSPI, GPIO, EPBAR, DMIBAR
and add product description.

References:
* 10th Generation Intel® Core™ Processors, Datasheet Volume 1 of 2
* 10th Generation Intel® Core™ Processors, Datasheet Volume 2 of 2
* Intel® 400 Series Chipset Family Platform Controller Hub, Datasheet
  Volume 1 of 2
* Intel® 400 Series Chipset Family Platform Controller Hub, Datasheet
  Volume 2 of 2

Change-Id: I9ae2447d2f122b9c05bcd50c16c1f19330ee9656
Signed-off-by: Vladimir Epifantsev <volatilefield@outlook.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89098
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
---
 util/inteltool/gpio.c        |  1 +
 util/inteltool/gpio_groups.c |  1 +
 util/inteltool/inteltool.c   | 29 ++++++++++--
 util/inteltool/inteltool.h   | 12 +++++
 util/inteltool/lpc.c         | 17 +++++++
 util/inteltool/memory.c      |  3 ++
 util/inteltool/pcie.c        | 53 +++++++++++++++++++++
 util/inteltool/pcr.c         |  1 +
 util/inteltool/rootcmplx.c   |  1 +
 util/inteltool/spi.c         | 89 ++++++++++++++++++++++++++++++------
 10 files changed, 191 insertions(+), 16 deletions(-)

diff --git a/util/inteltool/gpio.c b/util/inteltool/gpio.c
index 2a893a2daf..07f39593a0 100644
--- a/util/inteltool/gpio.c
+++ b/util/inteltool/gpio.c
@@ -1118,6 +1118,7 @@ int print_gpios(struct pci_dev *sb, int show_all, int show_diffs)
 	case PCI_DEVICE_ID_INTEL_B760:
 	case PCI_DEVICE_ID_INTEL_HM770:
 	case PCI_DEVICE_ID_INTEL_WM790:
+	case PCI_DEVICE_ID_INTEL_HM470:
 	case PCI_DEVICE_ID_INTEL_C262:
 	case PCI_DEVICE_ID_INTEL_C266:
 	case PCI_DEVICE_ID_INTEL_ADL_P:
diff --git a/util/inteltool/gpio_groups.c b/util/inteltool/gpio_groups.c
index 23757ba630..c8fbdb4439 100644
--- a/util/inteltool/gpio_groups.c
+++ b/util/inteltool/gpio_groups.c
@@ -186,6 +186,7 @@ const struct gpio_community *const *get_gpio_communities(struct pci_dev *const s
 	case PCI_DEVICE_ID_INTEL_QM370:
 	case PCI_DEVICE_ID_INTEL_HM370:
 	case PCI_DEVICE_ID_INTEL_CM246:
+	case PCI_DEVICE_ID_INTEL_HM470:
 		*community_count = ARRAY_SIZE(cannonlake_pch_h_communities);
 		*pad_stepping = 16;
 		return cannonlake_pch_h_communities;
diff --git a/util/inteltool/inteltool.c b/util/inteltool/inteltool.c
index 5bd9a05949..0ed9b8331c 100644
--- a/util/inteltool/inteltool.c
+++ b/util/inteltool/inteltool.c
@@ -145,11 +145,17 @@ static const struct {
 	{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_10TH_GEN_U,
 	  "10th generation (Icelake family) Core Processor (Mobile)" },
 	{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_CML_U1,
-	  "10th generation (Comet Lake family) Core Processor (Mobile)" },
+	  "10th generation (Comet Lake-U family) Core Processor (Mobile)" },
 	{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_CML_U2,
-	  "10th generation (Comet Lake family) Core Processor (Mobile)" },
+	  "10th generation (Comet Lake-U family) Core Processor (Mobile)" },
 	{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_CML_U3,
-	  "10th generation (Comet Lake family) Core Processor (Mobile)" },
+	  "10th generation (Comet Lake-U family) Core Processor (Mobile)" },
+	{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_CML_H_8_2,
+	  "10th generation (Comet Lake-H family) Core Processor (Mobile)" },
+	{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_CML_H_6_2,
+	  "10th generation (Comet Lake-H family) Core Processor (Mobile)" },
+	{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_CML_H_4_2,
+	  "10th generation (Comet Lake-H family) Core Processor (Mobile)" },
 	{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_HEWITTLAKE,
 	  "Xeon E7 v4/Xeon E5 v4/Xeon E3 v4/Xeon D (Hewitt Lake)" },
 	{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SAPPHIRERAPIDS_SP,
@@ -435,6 +441,7 @@ static const struct {
 	{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_GLK_LPC, "Gemini Lake" },
 	{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_H510, "H510" },
 	{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_H570, "H570" },
+	{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_HM470, "HM470" },
 	{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_Z590, "Z590" },
 	{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_Q570, "Q570" },
 	{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_B560, "B560" },
@@ -617,6 +624,22 @@ static const struct {
 	  "Intel(R) UHD Graphics for 11th Gen Intel(R) Processors" },
 	{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_TGL_GT2_ULT_2,
 	  "Intel(R) UHD Graphics for 11th Gen Intel(R) Processors" },
+	{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CML_GT1_S_1,
+	  "Intel(R) CometLake-S GT1" },
+	{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CML_GT1_S_2,
+	  "Intel(R) CometLake-S GT1" },
+	{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CML_GT2_S_G0,
+	  "Intel(R) CometLake-S GT2" },
+	{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CML_GT2_S_P0,
+	  "Intel(R) CometLake-S GT2" },
+	{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CML_GT1_H_1,
+	  "Intel(R) CometLake-H GT1" },
+	{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CML_GT1_H_2,
+	  "Intel(R) CometLake-H GT1" },
+	{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CML_GT2_H_R0,
+	  "Intel(R) CometLake-H GT2" },
+	{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CML_GT2_H_R1,
+	  "Intel(R) CometLake-H GT2" },
 	{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ADL_S_GT1,
 	  "Intel(R) AlderLake-S GT1" },
 	{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ADL_S_GT1_2,
diff --git a/util/inteltool/inteltool.h b/util/inteltool/inteltool.h
index c279d02e87..a9419e3431 100644
--- a/util/inteltool/inteltool.h
+++ b/util/inteltool/inteltool.h
@@ -224,6 +224,7 @@ static inline uint32_t inl(unsigned port)
 #define PCI_DEVICE_ID_INTEL_WM590		0x4389
 #define PCI_DEVICE_ID_INTEL_QM580		0x438a
 #define PCI_DEVICE_ID_INTEL_HM570		0x438b
+#define PCI_DEVICE_ID_INTEL_HM470		0x068d
 #define PCI_DEVICE_ID_INTEL_C252		0x438c
 #define PCI_DEVICE_ID_INTEL_C256		0x438d
 #define PCI_DEVICE_ID_INTEL_W580		0x438f
@@ -399,6 +400,9 @@ static inline uint32_t inl(unsigned port)
 #define PCI_DEVICE_ID_INTEL_CORE_CML_U1		0x9b51 /* Cometlake U (Mobile) */
 #define PCI_DEVICE_ID_INTEL_CORE_CML_U2		0x9b61 /* Cometlake U (Mobile) */
 #define PCI_DEVICE_ID_INTEL_CORE_CML_U3		0x9b71 /* Cometlake U (Mobile) */
+#define PCI_DEVICE_ID_INTEL_CORE_CML_H_8_2	0x9b44 /* Cometlake H 8+2 (Mobile) */
+#define PCI_DEVICE_ID_INTEL_CORE_CML_H_6_2	0x9b54 /* Cometlake H 6+2 (Mobile) */
+#define PCI_DEVICE_ID_INTEL_CORE_CML_H_4_2	0x9b64 /* Cometlake H 4+2 (Mobile) */
 #define PCI_DEVICE_ID_INTEL_CORE_TGL_ID_U_2	0x9a04 /* Tigerlake UP3 2 Cores */
 #define PCI_DEVICE_ID_INTEL_CORE_TGL_ID_U_4	0x9a14 /* Tigerlake UP3 4 Cores */
 #define PCI_DEVICE_ID_INTEL_CORE_TGL_ID_Y_2	0x9a02 /* Tigerlake UP4 2 Cores */
@@ -506,6 +510,14 @@ static inline uint32_t inl(unsigned port)
 #define PCI_DEVICE_ID_INTEL_TGL_GT1_2		0x9A68
 #define PCI_DEVICE_ID_INTEL_TGL_GT2_ULT_1	0x9A78
 #define PCI_DEVICE_ID_INTEL_TGL_GT2_ULT_2	0x9A70
+#define PCI_DEVICE_ID_INTEL_CML_GT1_S_1		0x9BA5
+#define PCI_DEVICE_ID_INTEL_CML_GT1_S_2		0x9BA8
+#define PCI_DEVICE_ID_INTEL_CML_GT2_S_G0	0x9BC8
+#define PCI_DEVICE_ID_INTEL_CML_GT2_S_P0	0x9BC5
+#define PCI_DEVICE_ID_INTEL_CML_GT1_H_1		0x9BA4
+#define PCI_DEVICE_ID_INTEL_CML_GT1_H_2		0x9BA2
+#define PCI_DEVICE_ID_INTEL_CML_GT2_H_R0	0x9BC2
+#define PCI_DEVICE_ID_INTEL_CML_GT2_H_R1	0x9BC4
 /* Elkhart Lake */
 #define PCI_DEVICE_ID_INTEL_EHL_GT1_1		0x4541
 #define PCI_DEVICE_ID_INTEL_EHL_GT1_2		0x4551
diff --git a/util/inteltool/lpc.c b/util/inteltool/lpc.c
index 4ce06ae5b9..9fbec66402 100644
--- a/util/inteltool/lpc.c
+++ b/util/inteltool/lpc.c
@@ -150,6 +150,23 @@ int print_lpc(struct pci_dev *sb, struct pci_access *pacc)
 			cfg_registers_size = ARRAY_SIZE(sunrise_lpc_cfg_registers);
 		}
 		break;
+	case PCI_DEVICE_ID_INTEL_HM470:
+		dev = pci_get_dev(pacc, sb->domain, sb->bus, sb->dev, 0);
+		if (!dev) {
+			printf("LPC/eSPI interface not found.\n");
+			return 1;
+		}
+		bc = pci_read_long(dev, SUNRISE_LPC_BC);
+		if (bc & (1 << 2)) {
+			printf("Device 0:1f.0 is eSPI (BC.LPC_ESPI=1)\n\n");
+			cfg_registers = alderlake_espi_cfg_registers;
+			cfg_registers_size = ARRAY_SIZE(alderlake_espi_cfg_registers);
+		} else {
+			printf("Device 0:1f.0 is LPC (BC.LPC_ESPI=0)\n\n");
+			cfg_registers = sunrise_lpc_cfg_registers;
+			cfg_registers_size = ARRAY_SIZE(sunrise_lpc_cfg_registers);
+		}
+		break;
 	case PCI_DEVICE_ID_INTEL_ADL_N:
 		dev = pci_get_dev(pacc, sb->domain, sb->bus, sb->dev, 0);
 		if (!dev) {
diff --git a/util/inteltool/memory.c b/util/inteltool/memory.c
index bb7ad60617..608a95533a 100644
--- a/util/inteltool/memory.c
+++ b/util/inteltool/memory.c
@@ -229,6 +229,9 @@ int print_mchbar(struct pci_dev *nb, struct pci_access *pacc, const char *dump_s
 	case PCI_DEVICE_ID_INTEL_CORE_CML_U1:
 	case PCI_DEVICE_ID_INTEL_CORE_CML_U2:
 	case PCI_DEVICE_ID_INTEL_CORE_CML_U3:
+	case PCI_DEVICE_ID_INTEL_CORE_CML_H_8_2:
+	case PCI_DEVICE_ID_INTEL_CORE_CML_H_6_2:
+	case PCI_DEVICE_ID_INTEL_CORE_CML_H_4_2:
 		mchbar_phys = pci_read_long(nb, 0x48);
 		mchbar_phys |= ((uint64_t)pci_read_long(nb, 0x4c)) << 32;
 		mchbar_phys &= 0x0000007fffff8000UL; /* 38:15 */
diff --git a/util/inteltool/pcie.c b/util/inteltool/pcie.c
index 32afa714fc..06a09df3ca 100644
--- a/util/inteltool/pcie.c
+++ b/util/inteltool/pcie.c
@@ -227,6 +227,35 @@ static const io_register_t alderlake_dmi_registers[] = {
 	{ 0x1D4, 4, "DMICEMSK"  }, // DMI Correctable Error Mask
 };
 
+/* 10th Generation Intel® Core™ Processors, Datasheet Volume 2 of 2, ID 615211 */
+static const io_register_t cometlake_dmi_registers[] = {
+	{ 0x00, 4, "DMIVCECH"    }, // DMI Virtual Channel Enhanced Capability
+	{ 0x04, 4, "DMIPVCCAP1"  }, // DMI Port VC Capability Register 1
+	{ 0x08, 4, "DMIPVCCAP2"  }, // DMI Port VC Capability Register 2
+	{ 0x0C, 2, "DMIPVCCTL"   }, // DMI Port VC Control
+	{ 0x10, 4, "DMIVC0RCAP"  }, // DMI VC0 Resource Capability
+	{ 0x14, 4, "DMIVC0RCTL"  }, // DMI VC0 Resource Control
+	{ 0x1A, 2, "DMIVC0RSTS"  }, // DMI VC0 Resource Status
+	{ 0x1C, 4, "DMIVC1RCAP"  }, // DMI VC1 Resource Capability
+	{ 0x20, 4, "DMIVC1RCTL"  }, // DMI VC1 Resource Control
+	{ 0x26, 2, "DMIVC1RSTS"  }, // DMI VC1 Resource Status
+	{ 0x34, 4, "DMIVCMRCAP"  }, // DMI VCm Resource Capability
+	{ 0x38, 4, "DMIVCMRCTL"  }, // DMI VCm Resource Control
+	{ 0x3E, 2, "DMIVCMRSTS"  }, // DMI VCm Resource Status
+	{ 0x40, 4, "DMIRCLDECH"  }, // DMI Root Complex Link Declaration
+	{ 0x44, 4, "DMIESD"      }, // DMI Element Self Description
+	{ 0x50, 4, "DMILE1D"     }, // DMI Link Entry 1 Description
+	{ 0x58, 4, "DMILE1A"     }, // DMI Link Entry 1 Address
+	{ 0x5C, 4, "DMILUE1A"    }, // DMI Link Upper Entry 1 Address
+	{ 0x60, 4, "DMILE2D"     }, // DMI Link Entry 2 Description
+	{ 0x68, 4, "DMILE2A"     }, // DMI Link Entry 2 Address
+	{ 0x84, 4, "LCAP"        }, // Link Capabilities
+	{ 0x88, 2, "LCTL"        }, // Link Control
+	{ 0x8A, 2, "LSTS"        }, // DMI Link Status
+	{ 0x98, 2, "LCTL2"       }, // Link Control 2
+	{ 0x9A, 2, "LSTS2"       }, // Link Status 2
+};
+
 /*
  * Egress Port Root Complex MMIO configuration space
  */
@@ -292,6 +321,12 @@ int print_epbar(struct pci_dev *nb)
 	case PCI_DEVICE_ID_INTEL_CORE_ADL_ID_N_0_8:
 	case PCI_DEVICE_ID_INTEL_CORE_ADL_ID_N_0_4:
 	case PCI_DEVICE_ID_INTEL_CORE_ADL_ID_N_0_4_1:
+	case PCI_DEVICE_ID_INTEL_CORE_CML_U1:
+	case PCI_DEVICE_ID_INTEL_CORE_CML_U2:
+	case PCI_DEVICE_ID_INTEL_CORE_CML_U3:
+	case PCI_DEVICE_ID_INTEL_CORE_CML_H_8_2:
+	case PCI_DEVICE_ID_INTEL_CORE_CML_H_6_2:
+	case PCI_DEVICE_ID_INTEL_CORE_CML_H_4_2:
 		epbar_phys = pci_read_long(nb, 0x40) & 0xfffffffe;
 		epbar_phys |= ((uint64_t)pci_read_long(nb, 0x44)) << 32;
 		break;
@@ -433,6 +468,18 @@ int print_dmibar(struct pci_dev *nb)
 		dmibar_phys |= ((uint64_t)pci_read_long(nb, 0x6c)) << 32;
 		dmibar_phys &= 0x0000007ffffff000UL; /* 38:12 */
 		break;
+	case PCI_DEVICE_ID_INTEL_CORE_CML_U1:
+	case PCI_DEVICE_ID_INTEL_CORE_CML_U2:
+	case PCI_DEVICE_ID_INTEL_CORE_CML_U3:
+	case PCI_DEVICE_ID_INTEL_CORE_CML_H_8_2:
+	case PCI_DEVICE_ID_INTEL_CORE_CML_H_6_2:
+	case PCI_DEVICE_ID_INTEL_CORE_CML_H_4_2:
+		dmi_registers = cometlake_dmi_registers;
+		size = ARRAY_SIZE(cometlake_dmi_registers);
+		dmibar_phys = pci_read_long(nb, 0x68);
+		dmibar_phys |= ((uint64_t)pci_read_long(nb, 0x6c)) << 32;
+		dmibar_phys &= 0x0000007ffffff000UL; /* 38:12 */
+		break;
 	case PCI_DEVICE_ID_INTEL_CORE_ADL_ID_N_0_8:
 	case PCI_DEVICE_ID_INTEL_CORE_ADL_ID_N_0_4:
 	case PCI_DEVICE_ID_INTEL_CORE_ADL_ID_N_0_4_1:
@@ -555,6 +602,12 @@ int print_pciexbar(struct pci_dev *nb)
 	case PCI_DEVICE_ID_INTEL_CORE_ADL_ID_N_0_8:
 	case PCI_DEVICE_ID_INTEL_CORE_ADL_ID_N_0_4:
 	case PCI_DEVICE_ID_INTEL_CORE_ADL_ID_N_0_4_1:
+	case PCI_DEVICE_ID_INTEL_CORE_CML_U1:
+	case PCI_DEVICE_ID_INTEL_CORE_CML_U2:
+	case PCI_DEVICE_ID_INTEL_CORE_CML_U3:
+	case PCI_DEVICE_ID_INTEL_CORE_CML_H_8_2:
+	case PCI_DEVICE_ID_INTEL_CORE_CML_H_6_2:
+	case PCI_DEVICE_ID_INTEL_CORE_CML_H_4_2:
 		pciexbar_reg = pci_read_long(nb, 0x60);
 		pciexbar_reg |= ((uint64_t)pci_read_long(nb, 0x64)) << 32;
 		break;
diff --git a/util/inteltool/pcr.c b/util/inteltool/pcr.c
index 6d70905021..8654e32a89 100644
--- a/util/inteltool/pcr.c
+++ b/util/inteltool/pcr.c
@@ -141,6 +141,7 @@ void pcr_init(struct pci_dev *const sb)
 	case PCI_DEVICE_ID_INTEL_C252:
 	case PCI_DEVICE_ID_INTEL_C256:
 	case PCI_DEVICE_ID_INTEL_W580:
+	case PCI_DEVICE_ID_INTEL_HM470:
 	case PCI_DEVICE_ID_INTEL_CANNONPOINT_LP_U_PREM:
 	case PCI_DEVICE_ID_INTEL_COMETPOINT_LP_U_PREM:
 	case PCI_DEVICE_ID_INTEL_COMETPOINT_LP_U_BASE:
diff --git a/util/inteltool/rootcmplx.c b/util/inteltool/rootcmplx.c
index 87fa38ffbc..a11cf5f2e8 100644
--- a/util/inteltool/rootcmplx.c
+++ b/util/inteltool/rootcmplx.c
@@ -125,6 +125,7 @@ int print_rcba(struct pci_dev *sb)
 	case PCI_DEVICE_ID_INTEL_ICH4M:
 	case PCI_DEVICE_ID_INTEL_ICH5:
 	case PCI_DEVICE_ID_INTEL_ADL_N:
+	case PCI_DEVICE_ID_INTEL_HM470:
 		printf("This southbridge does not have RCBA.\n");
 		return 1;
 	default:
diff --git a/util/inteltool/spi.c b/util/inteltool/spi.c
index cba43ed10e..9c3d2f12f5 100644
--- a/util/inteltool/spi.c
+++ b/util/inteltool/spi.c
@@ -171,6 +171,53 @@ static const io_register_t elkhart_spi_bar_registers[] = {
 	{ 0x198, 4, "CSXE_WPR0 - Write Protected Range 0" },
 };
 
+/* Intel® 400 Series Chipset Family Platform Controller Hub, 620855-002 */
+static const io_register_t cometlake_spi_bar_registers[] = {
+	{ 0x00, 4, "BFPREG - BIOS Flash Primary Region" },
+	{ 0x04, 2, "HSFSTS - Hardware Sequencing Flash Status" },
+	{ 0x06, 2, "HSFCTL - Hardware Sequencing Flash Control" },
+	{ 0x08, 4, "FADDR - Flash Address" },
+	{ 0x0c, 4, "DLOCK - Discrete Lock Bits" },
+	{ 0x10, 4, "FDATA0 - Flash Data 0" },
+	{ 0x14, 4, "FDATA1 - Flash Data 1" },
+	{ 0x18, 4, "FDATA2 - Flash Data 2" },
+	{ 0x1c, 4, "FDATA3 - Flash Data 3" },
+	{ 0x20, 4, "FDATA4 - Flash Data 4" },
+	{ 0x24, 4, "FDATA5 - Flash Data 5" },
+	{ 0x28, 4, "FDATA6 - Flash Data 6" },
+	{ 0x2c, 4, "FDATA7 - Flash Data 7" },
+	{ 0x30, 4, "FDATA8 - Flash Data 8" },
+	{ 0x34, 4, "FDATA9 - Flash Data 9" },
+	{ 0x38, 4, "FDATA10 - Flash Data 10" },
+	{ 0x3c, 4, "FDATA11 - Flash Data 11" },
+	{ 0x40, 4, "FDATA12 - Flash Data 12" },
+	{ 0x44, 4, "FDATA13 - Flash Data 13" },
+	{ 0x48, 4, "FDATA14 - Flash Data 14" },
+	{ 0x4c, 4, "FDATA15 - Flash Data 15" },
+	{ 0x50, 4, "FRACC - Flash Region Access Permissions" },
+	{ 0x54, 4, "FREG0 - Flash Region 0" },
+	{ 0x58, 4, "FREG1 - Flash Region 1" },
+	{ 0x5c, 4, "FREG2 - Flash Region 2" },
+	{ 0x60, 4, "FREG3 - Flash Region 3" },
+	{ 0x64, 4, "FREG4 - Flash Region 4" },
+	{ 0x68, 4, "FREG5 - Flash Region 5" },
+	{ 0x84, 4, "FPR0 - Flash Protected Range 0" },
+	{ 0x88, 4, "FPR1 - Flash Protected Range 1" },
+	{ 0x8c, 4, "FPR2 - Flash Protected Range 2" },
+	{ 0x90, 4, "FPR3 - Flash Protected Range 3" },
+	{ 0x94, 4, "FPR4 - Flash Protected Range 4" },
+	{ 0x98, 4, "GPR0 - Global Protected Range 0" },
+	{ 0xb0, 4, "SFRACC - Secondary Flash Region Access Permissions" },
+	{ 0xb4, 4, "FDOC - Flash Descriptor Observability Control" },
+	{ 0xb8, 4, "FDOD - Flash Descriptor Observability Data" },
+	{ 0xc0, 4, "AFC - Additional Flash Control" },
+	{ 0xc4, 4, "SFDP0_VSCC0 - Vendor Specific Component Capabilities for Component 0" },
+	{ 0xc8, 4, "SFDP1_VSCC1 - Vendor Specific Component Capabilities for Component 1" },
+	{ 0xcc, 4, "PTINX - Parameter Table Index" },
+	{ 0xd0, 4, "PTDATA - Parameter Table Data" },
+	{ 0xd4, 4, "SBRS - SPI Bus Requester Status" },
+};
+
 static int print_bioscntl(struct pci_dev *sb)
 {
 	int i, size = 0;
@@ -303,6 +350,7 @@ static int print_bioscntl(struct pci_dev *sb)
 		size = ARRAY_SIZE(pch_bios_cntl_registers);
 		break;
 	case PCI_DEVICE_ID_INTEL_ADL_N:
+	case PCI_DEVICE_ID_INTEL_HM470:
 		bios_cntl = pci_read_byte(sb, 0xdc);
 		bios_cntl_register = adl_pch_bios_cntl_registers;
 		size = ARRAY_SIZE(adl_pch_bios_cntl_registers);
@@ -330,13 +378,29 @@ static int print_bioscntl(struct pci_dev *sb)
 	return 0;
 }
 
+static int get_espibar_phys(struct pci_dev *sb, struct pci_access *pacc, uint8_t func, uint8_t offset, uint32_t mask, uint32_t *addr) {
+	struct pci_dev *spidev;
+
+	if (!(spidev = pci_get_dev(pacc, sb->domain, sb->bus, sb->dev, func))) {
+		fprintf(stderr, "Error: no spi device 0:31.%x\n", func);
+		return 1;
+	}
+
+	*addr = pci_read_long(spidev, offset) & mask;
+	if (!*addr) {
+		fprintf(stderr, "Error: no valid bar 0 of device 0:31.%x found %x\n", func, *addr);
+		return 1;
+	}
+
+	return 0;
+}
+
 static int print_spibar(struct pci_dev *sb, struct pci_access *pacc) {
 	int i, size = 0, rcba_size = 0x4000;
 	volatile uint8_t *rcba;
 	uint32_t rcba_phys;
 	const io_register_t *spi_register = NULL;
 	uint32_t spibaroffset;
-	struct pci_dev *spidev;
 
 	printf("\n============= SPI Bar ==============\n\n");
 
@@ -461,23 +525,22 @@ static int print_spibar(struct pci_dev *sb, struct pci_access *pacc) {
 		break;
 	case PCI_DEVICE_ID_INTEL_EHL:
 		/* the southbridge is the eSPI controller, we need to get the SPI flash controller */
-		if (!(spidev = pci_get_dev(pacc, sb->domain, sb->bus, sb->dev, 5))) {
-			perror("Error: no spi device 0:31.5\n");
-			return 1;
-		}
-
-		rcba_phys = ((uint64_t)pci_read_long(spidev, 0x10) & 0xfffff000);
-		rcba_size = 4096;
-		if (!rcba_phys) {
-			fprintf(stderr, "Error: no valid bar 0 of device 0:31.5 found %x %x\n", rcba_phys, rcba_size);
-			return 1;
-		}
-
 		/* this is not rcba, but we keep it to use common code */
+		if (get_espibar_phys(sb, pacc, 5, 0x10, 0xfffff000, &rcba_phys))
+			return 1;
+		rcba_size = 4096;
 		spibaroffset = 0;
 		spi_register = elkhart_spi_bar_registers;
 		size = ARRAY_SIZE(elkhart_spi_bar_registers);
 		break;
+	case PCI_DEVICE_ID_INTEL_HM470:
+		if (get_espibar_phys(sb, pacc, 5, 0x10, 0xfffff000, &rcba_phys))
+			return 1;
+		rcba_size = 4096;
+		spibaroffset = 0;
+		spi_register = cometlake_spi_bar_registers;
+		size = ARRAY_SIZE(cometlake_spi_bar_registers);
+		break;
 	case PCI_DEVICE_ID_INTEL_ICH:
 	case PCI_DEVICE_ID_INTEL_ICH0:
 	case PCI_DEVICE_ID_INTEL_ICH2:

From 4d1d27fcf3e30a4d443c58bea1d8088e8e38b706 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Micha=C5=82=20=C5=BBygowski?= <michal.zygowski@3mdeb.com>
Date: Tue, 8 Jul 2025 20:46:36 +0200
Subject: [PATCH 3160/3886] vendorcode/amd/opensil: Add Turin OpenSIL
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Add Turin OpenSIL driver and submodule pointing to turin_poc branch
of github.com/openSIL/openSIL repository.

Change-Id: Idd6d4e78a055926061de330da620c943b42a50a7
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88711
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
---
 .gitmodules                                   |   4 +
 src/soc/amd/turin_poc/Kconfig                 |   1 +
 src/vendorcode/amd/opensil/Kconfig            |   8 +
 src/vendorcode/amd/opensil/Kconfig.debug      |  30 +++
 src/vendorcode/amd/opensil/Makefile.mk        |   7 +-
 .../amd/opensil/turin_poc/Makefile.mk         |   8 +-
 src/vendorcode/amd/opensil/turin_poc/acpi.c   |   4 +-
 src/vendorcode/amd/opensil/turin_poc/filter.h |  28 +-
 src/vendorcode/amd/opensil/turin_poc/memmap.c |   7 +-
 .../opensil/turin_poc/meson_cross.template    |   2 +
 .../amd/opensil/turin_poc/mpio/Makefile.mk    |   2 +-
 .../amd/opensil/turin_poc/mpio/chip.c         | 106 +++++---
 .../amd/opensil/turin_poc/mpio/chip.h         |  12 +-
 src/vendorcode/amd/opensil/turin_poc/opensil  |   1 +
 .../opensil/turin_poc/opensil_config.template |   2 +-
 .../amd/opensil/turin_poc/opensil_console.c   |  31 ++-
 .../amd/opensil/turin_poc/opensil_console.h   |   6 +-
 .../amd/opensil/turin_poc/ramstage.c          | 241 ++++++++++++++++--
 18 files changed, 411 insertions(+), 89 deletions(-)
 create mode 160000 src/vendorcode/amd/opensil/turin_poc/opensil

diff --git a/.gitmodules b/.gitmodules
index 4fa82999dc..7a8d618619 100644
--- a/.gitmodules
+++ b/.gitmodules
@@ -70,3 +70,7 @@
 [submodule "3rdparty/open-power-signing-utils"]
 	path = 3rdparty/open-power-signing-utils
 	url = https://review.coreboot.org/open-power-signing-utils.git
+[submodule "src/vendorcode/amd/opensil/turin_poc/opensil"]
+	path = src/vendorcode/amd/opensil/turin_poc/opensil
+	url = https://github.com/openSIL/openSIL.git
+	branch = turin_poc
diff --git a/src/soc/amd/turin_poc/Kconfig b/src/soc/amd/turin_poc/Kconfig
index 8eadb04933..afdedfd94a 100644
--- a/src/soc/amd/turin_poc/Kconfig
+++ b/src/soc/amd/turin_poc/Kconfig
@@ -68,6 +68,7 @@ config SOC_SPECIFIC_OPTIONS
 	select SOC_AMD_COMMON_BLOCK_USE_ESPI
 	select SOC_AMD_COMMON_BLOCK_XHCI
 	select SOC_AMD_OPENSIL
+	select SOC_AMD_OPENSIL_TURIN_POC
 	select OPENSIL_DRIVER
 	select DRAM_SUPPORT_DDR5
 	select SSE2
diff --git a/src/vendorcode/amd/opensil/Kconfig b/src/vendorcode/amd/opensil/Kconfig
index 11308a7f73..735d6e1feb 100644
--- a/src/vendorcode/amd/opensil/Kconfig
+++ b/src/vendorcode/amd/opensil/Kconfig
@@ -15,10 +15,17 @@ config SOC_AMD_OPENSIL_GENOA_POC
 	  Select this on SoCs that use the Genoa proof of concept version of
 	  openSIL.
 
+config SOC_AMD_OPENSIL_TURIN_POC
+	bool
+	help
+	  Select this on SoCs that use the Turin proof of concept version of
+	  openSIL.
+
 config AMD_OPENSIL_PATH
 	string "Path to openSIL source"
 	depends on !SOC_AMD_OPENSIL_STUB
 	default "$(top)/src/vendorcode/amd/opensil/genoa_poc/opensil" if SOC_AMD_OPENSIL_GENOA_POC
+	default "$(top)/src/vendorcode/amd/opensil/turin_poc/opensil" if SOC_AMD_OPENSIL_TURIN_POC
 	help
 	  Set to the path of the openSIL directory containing meson.build.
 	  example
@@ -26,6 +33,7 @@ config AMD_OPENSIL_PATH
 config AMD_OPENSIL_MPIO_CHIP_H_FILE
 	string "Location of specific MPIO chip.h implementation"
 	default "$(top)/src/vendorcode/amd/opensil/genoa_poc/mpio/chip.h" if SOC_AMD_OPENSIL_GENOA_POC
+	default "$(top)/src/vendorcode/amd/opensil/turin_poc/mpio/chip.h" if SOC_AMD_OPENSIL_TURIN_POC
 	default "$(top)/src/vendorcode/amd/opensil/stub/mpio/chip.h"
 	help
 	  Set to the location of the MPIO chip.h in the selected openSIL
diff --git a/src/vendorcode/amd/opensil/Kconfig.debug b/src/vendorcode/amd/opensil/Kconfig.debug
index 859122b2a8..14b57662c6 100644
--- a/src/vendorcode/amd/opensil/Kconfig.debug
+++ b/src/vendorcode/amd/opensil/Kconfig.debug
@@ -66,6 +66,36 @@ config OPENSIL_DEBUG_RAS
 	help
 	  Enable printing RAS related messages.
 
+config OPENSIL_DEBUG_MPIO
+	bool "Enable MPIO messages"
+	default y
+	help
+	  Enable printing MPIO related messages.
+
+config OPENSIL_DEBUG_CXL
+	bool "Enable CXL messages"
+	default y
+	help
+	  Enable printing CXL related messages.
+
+config OPENSIL_DEBUG_SDXI
+	bool "Enable SDXI messages"
+	default y
+	help
+	  Enable printing SDXI related messages.
+
+config OPENSIL_DEBUG_RCMGR
+	bool "Enable RC MGR messages"
+	default y
+	help
+	  Enable printing Resource Manager related messages.
+
+config OPENSIL_DEBUG_XUSL_CMN
+	bool "Enable xUSL CommonLib messages"
+	default y
+	help
+	  Enable printing xUSL CommonLib related messages.
+
 endif # OPENSIL_DEBUG_OUTPUT
 
 endif # SOC_AMD_OPENSIL
diff --git a/src/vendorcode/amd/opensil/Makefile.mk b/src/vendorcode/amd/opensil/Makefile.mk
index 5c881f9bc6..beebaf5782 100644
--- a/src/vendorcode/amd/opensil/Makefile.mk
+++ b/src/vendorcode/amd/opensil/Makefile.mk
@@ -15,6 +15,7 @@ endif
 opensil_dir := $(call strip_quotes,$(CONFIG_AMD_OPENSIL_PATH))
 
 subdirs-$(CONFIG_SOC_AMD_OPENSIL_GENOA_POC) += genoa_poc
+subdirs-$(CONFIG_SOC_AMD_OPENSIL_TURIN_POC) += turin_poc
 
 ifeq ($(CONFIG_ARCH_RAMSTAGE_X86_32),y)
 cpu_family_string="x86"
@@ -63,7 +64,11 @@ $(OBJPATH)/$(OPENSIL_CONFIG): $(opensil_dir)/../opensil_config.template
 		$< > $@
 
 $(OBJPATH)/$(OPENSIL_CONFIG).h: $(OBJPATH)/$(OPENSIL_CONFIG) $(obj)/config.h $(objutil)/kconfig/conf
-	cd $(opensil_dir); KCONFIG_CONFIG=$(OBJPATH)/$(OPENSIL_CONFIG) KCONFIG_AUTOHEADER=$@ $(PYTHON) util/kconfig/lib/genconfig.py Kconfig
+	cd $(opensil_dir); \
+		KCONFIG_CONFIG=$(OBJPATH)/$(OPENSIL_CONFIG) \
+		KCONFIG_AUTOHEADER=$@ \
+		$(PYTHON) util/kconfig/lib/genconfig.py \
+			--config-out $(OBJPATH)/$(OPENSIL_CONFIG) Kconfig
 
 # meson handles ccache on its own
 OPENSIL_COMPILER=$(filter-out $(CCACHE), $(CC_ramstage))
diff --git a/src/vendorcode/amd/opensil/turin_poc/Makefile.mk b/src/vendorcode/amd/opensil/turin_poc/Makefile.mk
index 62bd00bf91..c203476502 100644
--- a/src/vendorcode/amd/opensil/turin_poc/Makefile.mk
+++ b/src/vendorcode/amd/opensil/turin_poc/Makefile.mk
@@ -1,5 +1,7 @@
 ## SPDX-License-Identifier: GPL-2.0-only
 
+CFLAGS_opensil = -D_MSC_EXTENSIONS=0 -DHAS_STRING_H=1 -Wno-unknown-pragmas
+
 subdirs-y += mpio
 
 CPPFLAGS_common += -I$(opensil_dir)/Include -I$(opensil_dir)/xUSL -I$(opensil_dir)/xUSL/Include -I$(opensil_dir)/xUSL/FCH -I$(opensil_dir)/xUSL/FCH/Common -I$(opensil_dir)/xSIM -I$(opensil_dir)/xPRF
@@ -12,7 +14,7 @@ ramstage-y += memmap.c
 ramstage-y += opensil_console.c
 ramstage-y += ramstage.c
 
-$(obj)/romstage/vendorcode/amd/opensil/turin_poc/opensil_console.o: CFLAGS_romstage += -D_MSC_EXTENSIONS=0 -DHAS_STRING_H=1 -Wno-unknown-pragmas
-$(obj)/romstage/vendorcode/amd/opensil/turin_poc/romstage.o: CFLAGS_romstage += -D_MSC_EXTENSIONS=0 -DHAS_STRING_H=1 -Wno-unknown-pragmas
+$(obj)/romstage/vendorcode/amd/opensil/turin_poc/opensil_console.o: CFLAGS_romstage += $(CFLAGS_opensil)
+$(obj)/romstage/vendorcode/amd/opensil/turin_poc/romstage.o: CFLAGS_romstage += $(CFLAGS_opensil)
 
-$(obj)/ramstage/vendorcode/amd/opensil/turin_poc/opensil_console.o: CFLAGS_ramstage += -D_MSC_EXTENSIONS=0 -DHAS_STRING_H=1 -Wno-unknown-pragmas
+$(obj)/ramstage/vendorcode/amd/opensil/turin_poc/opensil_console.o: CFLAGS_ramstage += $(CFLAGS_opensil)
diff --git a/src/vendorcode/amd/opensil/turin_poc/acpi.c b/src/vendorcode/amd/opensil/turin_poc/acpi.c
index fcdf167c12..dc172e3311 100644
--- a/src/vendorcode/amd/opensil/turin_poc/acpi.c
+++ b/src/vendorcode/amd/opensil/turin_poc/acpi.c
@@ -4,13 +4,13 @@
 #include <Sil-api.h>
 #include <SilCommon.h>
 #include <xSIM-api.h>
-#include <FCH/Common/FchCommonCfg.h>
+#include <FCH/FchClass-api.h>
 
 #include "../opensil.h"
 
 void opensil_fill_fadt(acpi_fadt_t *fadt)
 {
-	FCHHWACPI_INPUT_BLK *blk = SilFindStructure(SilId_FchHwAcpiP,  0);
+	FCHHWACPI_INPUT_BLK *blk = SilFindStructure(SilId_FchHwAcpiP, 0);
 
 	fadt->pm1a_evt_blk = blk->AcpiPm1EvtBlkAddr;
 	fadt->pm1a_cnt_blk = blk->AcpiPm1CntBlkAddr;
diff --git a/src/vendorcode/amd/opensil/turin_poc/filter.h b/src/vendorcode/amd/opensil/turin_poc/filter.h
index f0817f7502..84f1db1f38 100644
--- a/src/vendorcode/amd/opensil/turin_poc/filter.h
+++ b/src/vendorcode/amd/opensil/turin_poc/filter.h
@@ -1,14 +1,19 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
 /* Keep this in sync with openSIL SilCommon.h file */
-#define DEBUG_FILTER_APOB       0x00000001UL
-#define DEBUG_FILTER_NBIO       0x00000002UL
-#define DEBUG_FILTER_CCX        0x00000004UL
-#define DEBUG_FILTER_SMU        0x00000008UL
-#define DEBUG_FILTER_DF         0x00000010UL
-#define DEBUG_FILTER_MEM        0x00000040UL
-#define DEBUG_FILTER_FCH        0x00000080UL
-#define DEBUG_FILTER_RAS        0x00000100UL
+#define DEBUG_FILTER_APOB	0x00000001UL
+#define DEBUG_FILTER_NBIO	0x00000002UL
+#define DEBUG_FILTER_CCX	0x00000004UL
+#define DEBUG_FILTER_SMU	0x00000008UL
+#define DEBUG_FILTER_DF		0x00000010UL
+#define DEBUG_FILTER_MPIO	0x00000020UL
+#define DEBUG_FILTER_MEM	0x00000040UL
+#define DEBUG_FILTER_FCH	0x00000080UL
+#define DEBUG_FILTER_RAS	0x00000100UL
+#define DEBUG_FILTER_CXL	0x00000200UL
+#define DEBUG_FILTER_SDXI	0x00000400UL
+#define DEBUG_FILTER_RCMGR	0x00000800UL
+#define DEBUG_FILTER_XUSL_CMN	0x00001000UL
 
 #define SIL_DEBUG(topic) (CONFIG(OPENSIL_DEBUG_##topic) ? DEBUG_FILTER_##topic : 0)
 
@@ -18,6 +23,11 @@
 	  SIL_DEBUG(CCX) | \
 	  SIL_DEBUG(SMU) | \
 	  SIL_DEBUG(DF) | \
+	  SIL_DEBUG(MPIO) | \
 	  SIL_DEBUG(MEM) | \
 	  SIL_DEBUG(FCH) | \
-	  SIL_DEBUG(RAS) )
+	  SIL_DEBUG(RAS) | \
+	  SIL_DEBUG(CXL) | \
+	  SIL_DEBUG(SDXI) | \
+	  SIL_DEBUG(RCMGR) | \
+	  SIL_DEBUG(XUSL_CMN) )
diff --git a/src/vendorcode/amd/opensil/turin_poc/memmap.c b/src/vendorcode/amd/opensil/turin_poc/memmap.c
index eed1be7e5f..cf95b312e5 100644
--- a/src/vendorcode/amd/opensil/turin_poc/memmap.c
+++ b/src/vendorcode/amd/opensil/turin_poc/memmap.c
@@ -1,8 +1,9 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
 #include <SilCommon.h>
-#include <Sil-api.h> // needed above ApobCmn.h
-#include <ApobCmn.h>
+#include <Sil-api.h>
+#include <opensil_config.h> // needed above ApobCmn.h
+#include <APOB/Common/ApobCmn.h>
 #include <xPRF-api.h>
 
 #include "../opensil.h"
@@ -46,7 +47,7 @@ const char *opensil_get_hole_info_type(uint32_t type)
 
 void opensil_get_hole_info(uint32_t *n_holes, uint64_t *top_of_mem, void **hole_info)
 {
-        SIL_STATUS status = xPrfGetSystemMemoryMap(n_holes, top_of_mem, hole_info);
+	SIL_STATUS status = xPrfGetSystemMemoryMap(n_holes, top_of_mem, hole_info);
 	SIL_STATUS_report("xPrfGetSystemMemoryMap", status);
 	// Make sure hole_info does not get initialized to something odd by xPRF on failure
 	if (status != SilPass) {
diff --git a/src/vendorcode/amd/opensil/turin_poc/meson_cross.template b/src/vendorcode/amd/opensil/turin_poc/meson_cross.template
index 6473b65225..b8fdf618fa 100644
--- a/src/vendorcode/amd/opensil/turin_poc/meson_cross.template
+++ b/src/vendorcode/amd/opensil/turin_poc/meson_cross.template
@@ -22,6 +22,8 @@ c_args = ['-nostdinc',
           '-Wno-unused-parameter',
           # ubiquitous problem in openSIL
           '-Wno-missing-field-initializers',
+          # remove after https://github.com/openSIL/openSIL/pull/39 is merged
+          '-Wno-unused-but-set-variable',
           ##CLANG_ARGS##
          ]
 
diff --git a/src/vendorcode/amd/opensil/turin_poc/mpio/Makefile.mk b/src/vendorcode/amd/opensil/turin_poc/mpio/Makefile.mk
index fafdc5935f..8ee80c97b0 100644
--- a/src/vendorcode/amd/opensil/turin_poc/mpio/Makefile.mk
+++ b/src/vendorcode/amd/opensil/turin_poc/mpio/Makefile.mk
@@ -2,4 +2,4 @@
 
 ramstage-y += chip.c
 
-$(obj)/ramstage/vendorcode/amd/opensil/turin_poc/mpio/chip.o: CFLAGS_ramstage += -D_MSC_EXTENSIONS=0 -DHAS_STRING_H=1 -Wno-unknown-pragmas
+$(obj)/ramstage/vendorcode/amd/opensil/turin_poc/mpio/chip.o: CFLAGS_ramstage += $(CFLAGS_opensil)
diff --git a/src/vendorcode/amd/opensil/turin_poc/mpio/chip.c b/src/vendorcode/amd/opensil/turin_poc/mpio/chip.c
index 587ab81e02..3586245b54 100644
--- a/src/vendorcode/amd/opensil/turin_poc/mpio/chip.c
+++ b/src/vendorcode/amd/opensil/turin_poc/mpio/chip.c
@@ -2,18 +2,38 @@
 
 #include <device/device.h>
 #include <device/pci_def.h>
+#include <opensil_config.h>
+#include <CCX/Common/CcxApic.h>
+#include <Cxl/CxlClass-api.h>
 #include <Mpio/Common/MpioStructs.h>
 #include <Mpio/MpioClass-api.h>
-#include <NBIO/NbioClass-api.h>
+#include <Nbio/NbioClass-api.h>
 #include <RcMgr/DfX/RcManager4-api.h>
 #include <vendorcode/amd/opensil/opensil.h>
 #include <xSIM-api.h>
+#include <static.h>
 
 #include "chip.h"
 
 static void mpio_params_config(void)
 {
 	MPIOCLASS_INPUT_BLK *mpio_data = SilFindStructure(SilId_MpioClass, 0);
+	struct device *gnb = DEV_PTR(gnb_0);
+	struct device *iommu = DEV_PTR(iommu_0);
+	struct device *psp = DEV_PTR(asp);
+	struct device *nbif = DEV_PTR(nbif_0);
+
+	mpio_data->CfgNbioSsid   = gnb->subsystem_vendor |
+				  ((uint32_t)gnb->subsystem_device << 16);
+	mpio_data->CfgIommuSsid  = iommu->subsystem_vendor |
+				  ((uint32_t)iommu->subsystem_device << 16);
+	mpio_data->CfgPspccpSsid = psp->subsystem_vendor |
+				  ((uint32_t)psp->subsystem_device << 16);
+	mpio_data->CfgNbifF0Ssid = nbif->subsystem_vendor |
+				  ((uint32_t)nbif->subsystem_device << 16);
+	mpio_data->CfgNtbSsid    = 0; // Not implemented in OpenSIL
+	mpio_data->CfgNtbccpSsid = 0; // Not implemented in OpenSIL
+
 	mpio_data->CfgDxioClockGating                  = 1;
 	mpio_data->PcieDxioTimingControlEnable         = 0;
 	mpio_data->PCIELinkReceiverDetectionPolling    = 0;
@@ -24,13 +44,12 @@ static void mpio_params_config(void)
 	mpio_data->DxioPhyProgramming                  = 1;
 	mpio_data->CfgSkipPspMessage                   = 1;
 	mpio_data->DxioSaveRestoreModes                = 0xff;
-	mpio_data->AmdAllowCompliance                  = 0;
-	mpio_data->AmdAllowCompliance                  = 0xff;
+	mpio_data->AmdAllowCompliance                  = 0xf;
 	mpio_data->SrisEnableMode                      = 0xff;
 	mpio_data->SrisSkipInterval                    = 0;
 	mpio_data->SrisSkpIntervalSel                  = 1;
 	mpio_data->SrisCfgType                         = 0;
-	mpio_data->SrisAutoDetectMode                  = 0xff;
+	mpio_data->SrisAutoDetectMode                  = 0xf;
 	mpio_data->SrisAutodetectFactor                = 0;
 	mpio_data->SrisLowerSkpOsGenSup                = 0;
 	mpio_data->SrisLowerSkpOsRcvSup                = 0;
@@ -45,28 +64,21 @@ static void mpio_params_config(void)
 	mpio_data->SurpriseDownFeature                 = 1;
 	mpio_data->LcMultAutoSpdChgOnLastRateEnable    = 0;
 	mpio_data->AmdRxMarginEnabled                  = 1;
-	mpio_data->CfgPcieCVTestWA                     = 1;
+	mpio_data->CfgPcieCVTestWA                     = 0;
 	mpio_data->CfgPcieAriSupport                   = 1;
 	mpio_data->CfgNbioCTOtoSC                      = 0;
 	mpio_data->CfgNbioCTOIgnoreError               = 1;
-	mpio_data->CfgNbioSsid                         = 0;
-	mpio_data->CfgIommuSsid                        = 0;
-	mpio_data->CfgPspccpSsid                       = 0;
-	mpio_data->CfgNtbccpSsid                       = 0;
-	mpio_data->CfgNbifF0Ssid                       = 0;
-	mpio_data->CfgNtbSsid                          = 0;
 	mpio_data->AmdPcieSubsystemDeviceID            = 0x1453;
 	mpio_data->AmdPcieSubsystemVendorID            = 0x1022;
 	mpio_data->GppAtomicOps                        = 1;
 	mpio_data->GfxAtomicOps                        = 1;
 	mpio_data->AmdNbioReportEdbErrors              = 0;
 	mpio_data->OpnSpare                            = 0;
-	mpio_data->AmdPreSilCtrl0                      = 0;
 	mpio_data->MPIOAncDataSupport                  = 1;
 	mpio_data->AfterResetDelay                     = 0;
 	mpio_data->CfgEarlyLink                        = 0;
 	mpio_data->AmdCfgExposeUnusedPciePorts         = 1; // Show all ports
-	mpio_data->CfgForcePcieGenSpeed                = 0;
+	mpio_data->CfgForcePcieGenSpeed                = 0xff;
 	mpio_data->CfgSataPhyTuning                    = 0;
 	mpio_data->PcieLinkComplianceModeAllPorts      = 0;
 	mpio_data->AmdMCTPEnable                       = 0;
@@ -79,30 +91,64 @@ static void mpio_params_config(void)
 	  // A getter and setter, both are needed for this PCD.
 	mpio_data->AmdPciePresetMask32GtAllPort        = 0xffffffff;
 	mpio_data->PcieLinkAspmAllPort                 = 0xff;
-
 	mpio_data->SyncHeaderByPass                    = 1;
 	mpio_data->CxlTempGen5AdvertAltPtcl            = 0;
+	mpio_data->CfgSevSnpSupport                    = 0;
+	mpio_data->CfgSevTioSupport                    = 0;
+	mpio_data->PcieIdeCapSup                       = 0;
+	mpio_data->Master7bitSteeringTag               = 1;
 
 	/* TODO handle this differently on multisocket */
 	mpio_data->PcieTopologyData.PlatformData[0].Flags = DESCRIPTOR_TERMINATE_LIST;
 	mpio_data->PcieTopologyData.PlatformData[0].PciePortList = mpio_data->PcieTopologyData.PortList;
 }
 
+static void cxl_params_config(void)
+{
+	CXLCLASS_DATA_BLK *cxl_data = SilFindStructure(SilId_CxlClass, 0);
+	CXLCLASS_INPUT_BLK *input = &cxl_data->CxlInputBlock;
+	input->AmdPcieAerReportMechanism  = 1;
+}
+
 static void nbio_params_config(void)
 {
 	NBIOCLASS_DATA_BLOCK *nbio_data = SilFindStructure(SilId_NbioClass, 0);
-	NBIOCLASS_INPUT_BLK *input = &nbio_data->NbioInputBlk;
-	input->CfgHdAudioEnable           = false;
-	input->EsmEnableAllRootPorts      = false;
-	input->EsmTargetSpeed             = 16;
-	input->CfgRxMarginPersistenceMode = 1;
-	input->CfgDxioFrequencyVetting    = false;
-	input->CfgSkipPspMessage          = 1;
-	input->CfgEarlyTrainTwoPcieLinks  = false;
-	input->EarlyBmcLinkTraining       = true;
-	input->EdpcEnable                 = 0;
-	input->PcieAerReportMechanism     = 2;
-	input->SevSnpSupport              = false;
+	NBIO_CONFIG_DATA *input = &nbio_data->NbioConfigData;
+	input->EsmEnableAllRootPorts        = false;
+	input->EsmTargetSpeed               = 16;
+	input->CfgRxMarginPersistenceMode   = 1;
+	input->SevSnpSupport                = false;
+	input->AerEnRccDev0                 = false;
+	input->CfgAEREnable                 = true;
+	input->AtomicRoutingEnStrap5        = true;
+	input->CfgSriovEnDev0F1             = true;
+	input->CfgAriEnDev0F1               = true;
+	input->CfgAerEnDev0F1               = true;
+	input->CfgAcsEnDev0F1               = true;
+	input->CfgAtsEnDev0F1               = true;
+	input->CfgPasidEnDev0F1             = true;
+	input->CfgRtrEnDev0F1               = true;
+	input->CfgPriEnDev0F1               = true;
+	input->CfgPwrEnDev0F1               = true;
+	input->AtcEnable                    = true;
+	input->NbifDev0F1AtomicRequestEn    = true;
+	input->AcsEnRccDev0                 = true;
+	input->AcsP2pReq                    = true;
+	input->AcsSourceVal                 = true;
+	input->RccDev0E2EPrefix             = true;
+	input->RccDev0ExtendedFmtSupported  = true;
+	input->CfgSyshubMgcgClkGating       = 1;
+	input->IoApicIdPreDefineEn          = true;
+	/* Up to 16 IOAPICs for 2 sockets (8 per socket) */
+	input->IoApicIdBase                 = 240;
+	input->IommuAvicSupport             = true;
+
+	if (CONFIG(XAPIC_ONLY) || CONFIG(X2APIC_LATE_WORKAROUND))
+		input->AmdApicMode = xApicMode;
+	else if (CONFIG(X2APIC_ONLY))
+		input->AmdApicMode = x2ApicMode;
+	else
+		input->AmdApicMode = ApicAutoMode;
 }
 
 static void setup_bmc_lanes(uint8_t lane, uint8_t socket)
@@ -111,16 +157,11 @@ static void setup_bmc_lanes(uint8_t lane, uint8_t socket)
 	rc_mgr_input_block->BmcSocket = socket;
 	rc_mgr_input_block->EarlyBmcLinkLaneNum = lane;
 
-	NBIOCLASS_DATA_BLOCK *nbio_data = SilFindStructure(SilId_NbioClass, 0);
-	NBIOCLASS_INPUT_BLK *nbio_input = &nbio_data->NbioInputBlk;
-	nbio_input->EarlyBmcLinkSocket         = socket;
-	nbio_input->EarlyBmcLinkLaneNum        = lane;
-	nbio_input->EarlyBmcLinkDie            = 0;
-
 	MPIOCLASS_INPUT_BLK *mpio_data = SilFindStructure(SilId_MpioClass, 0);
 	mpio_data->EarlyBmcLinkSocket                  = socket;
 	mpio_data->EarlyBmcLinkLaneNum                 = lane;
 	mpio_data->EarlyBmcLinkDie                     = 0;
+	mpio_data->EarlyBmcLinkTraining                = true;
 }
 
 void opensil_mpio_per_device_config(struct device *dev)
@@ -198,5 +239,6 @@ void opensil_mpio_per_device_config(struct device *dev)
 void opensil_mpio_global_config(void)
 {
 	mpio_params_config();
+	cxl_params_config();
 	nbio_params_config();
 }
diff --git a/src/vendorcode/amd/opensil/turin_poc/mpio/chip.h b/src/vendorcode/amd/opensil/turin_poc/mpio/chip.h
index ce5468cbde..db6a094ed4 100644
--- a/src/vendorcode/amd/opensil/turin_poc/mpio/chip.h
+++ b/src/vendorcode/amd/opensil/turin_poc/mpio/chip.h
@@ -8,13 +8,13 @@
 /*
  * TURIN MPIO mapping
  * P0 -> [0-15]
- * G0 -> [16-31]
+ * P3 -> [16-31]
  * P1 -> [32-47]
- * G1 -> [48-63]
- * P2 -> [64-79]
- * G2 -> [80-95]
- * P3 -> [96-111]
- * G3 -> [112-127]
+ * P2 -> [48-63]
+ * G1 -> [64-79]
+ * G3 -> [80-95]
+ * G0 -> [96-111]
+ * G2 -> [112-127]
  * P4 -> [128-131]
  * P5 -> [132-136]
  */
diff --git a/src/vendorcode/amd/opensil/turin_poc/opensil b/src/vendorcode/amd/opensil/turin_poc/opensil
new file mode 160000
index 0000000000..a65485ffa7
--- /dev/null
+++ b/src/vendorcode/amd/opensil/turin_poc/opensil
@@ -0,0 +1 @@
+Subproject commit a65485ffa7bddec696576323c6fc839ea5bb081d
diff --git a/src/vendorcode/amd/opensil/turin_poc/opensil_config.template b/src/vendorcode/amd/opensil/turin_poc/opensil_config.template
index 2ddd3b4ec1..1bbc650990 100644
--- a/src/vendorcode/amd/opensil/turin_poc/opensil_config.template
+++ b/src/vendorcode/amd/opensil/turin_poc/opensil_config.template
@@ -2,4 +2,4 @@ CONFIG_PLAT_APOB_ADDRESS=##APOB_BASE##
 CONFIG_PSP_BIOS_BIN_BASE=##BIOS_ENTRY_BASE##
 CONFIG_PSP_BIOS_BIN_SIZE=##BIOS_ENTRY_SIZE##
 CONFIG_PLAT_NUMBER_SOCKETS=1
-CONFIG_SOC_F19M10=y
+CONFIG_SOC_F1AM00=y
diff --git a/src/vendorcode/amd/opensil/turin_poc/opensil_console.c b/src/vendorcode/amd/opensil/turin_poc/opensil_console.c
index 35e5eeb2b4..7a7d451f72 100644
--- a/src/vendorcode/amd/opensil/turin_poc/opensil_console.c
+++ b/src/vendorcode/amd/opensil/turin_poc/opensil_console.c
@@ -14,11 +14,13 @@ static int translate_opensil_debug_level(size_t MsgLevel)
 		return BIOS_ERR;
 	case SIL_TRACE_WARNING:
 		return BIOS_WARNING;
-	case SIL_TRACE_ENTRY:
-	case SIL_TRACE_EXIT:
-		return BIOS_SPEW;
 	case SIL_TRACE_INFO:
 		return BIOS_DEBUG;
+	case SIL_TRACE_ENTRY:
+	case SIL_TRACE_EXIT:
+	case SIL_TRACE_RAW:
+	case SIL_TRACE_VERBOSE:
+		return BIOS_SPEW;
 	default:
 		return BIOS_NEVER;
 	}
@@ -32,9 +34,26 @@ void HostDebugService(size_t MsgLevel, const char *SilPrefix, const char *Messag
 
 	const int loglevel = translate_opensil_debug_level(MsgLevel);
 
-	/* print fomatted prefix */
-	if (CONFIG(OPENSIL_DEBUG_PREFIX))
-		printk(loglevel, "%s%s:%zu:", SilPrefix, Function, Line);
+	/* print formatted prefix */
+	if (CONFIG(OPENSIL_DEBUG_PREFIX)) {
+		switch (MsgLevel) {
+		case SIL_TRACE_RAW: break; // Raw print do nothing
+		case SIL_TRACE_ENTRY:
+			printk(loglevel, "%s Enter %s:%zu:", SilPrefix, Function, Line);
+			break;
+		case SIL_TRACE_EXIT:
+			printk(loglevel, "%s Exit %s:%zu:", SilPrefix, Function, Line);
+			break;
+		case SIL_TRACE_ERROR:
+		case SIL_TRACE_WARNING:
+		case SIL_TRACE_INFO:
+		case SIL_TRACE_VERBOSE:
+		/* fallthrough */
+		default:
+			printk(loglevel, "%s%s:%zu:", SilPrefix, Function, Line);
+			break;
+		}
+	}
 
 	/* print formatted message */
 	va_list args;
diff --git a/src/vendorcode/amd/opensil/turin_poc/opensil_console.h b/src/vendorcode/amd/opensil/turin_poc/opensil_console.h
index d3ffb6857f..424f002d37 100644
--- a/src/vendorcode/amd/opensil/turin_poc/opensil_console.h
+++ b/src/vendorcode/amd/opensil/turin_poc/opensil_console.h
@@ -1,7 +1,9 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
-#ifndef _VENDORCODE_AND_OPENSIL_CONSOLE
-#define _VENDORCODE_AND_OPENSIL_CONSOLE
+#ifndef _VENDORCODE_AMD_OPENSIL_CONSOLE
+#define _VENDORCODE_AMD_OPENSIL_CONSOLE
+
+#include <types.h>
 
 void HostDebugService(size_t MsgLevel, const char *SilPrefix, const char *Message,
 		      const char *Function, size_t Line, ...);
diff --git a/src/vendorcode/amd/opensil/turin_poc/ramstage.c b/src/vendorcode/amd/opensil/turin_poc/ramstage.c
index f4474f0be5..f206ef5f58 100644
--- a/src/vendorcode/amd/opensil/turin_poc/ramstage.c
+++ b/src/vendorcode/amd/opensil/turin_poc/ramstage.c
@@ -1,13 +1,25 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
-#include <FCH/Common/FchCommonCfg.h>
-#include <FCH/Common/FchCore/FchSata/FchSata.h>
+/* opensil_config.h needed for PROJ_MAX_* defines */
+#include <opensil_config.h>
+#include <CCX/CcxClass-api.h>
+#include <CCX/Common/CcxApic.h>
+#include <DF/DfClass-api.h>
+#include <FCH/FchClass-api.h>
+#include <FCH/FchHwAcpi-api.h>
+#include <FCH/FchIsa-api.h>
+#include <FCH/Common/FchCore/FchSata/FchSataBlk.h>
+#include <Mpio/MpioClass-api.h>
 #include <RcMgr/DfX/RcManager4-api.h>
+#include <Sdxi/SdxiClass-api.h>
 #include <amdblocks/reset.h>
 #include <bootstate.h>
 #include <cbmem.h>
 #include <cpu/cpu.h>
+#include <cpu/x86/smm.h>
 #include <device/device.h>
+#include <soc/aoac_defs.h>
+#include <soc/iomap.h>
 #include <soc/soc_chip.h>
 #include <static.h>
 #include <stdio.h>
@@ -16,6 +28,64 @@
 #include "opensil_console.h"
 #include "../opensil.h"
 
+
+#define TURIN_USB_STRUCT_MAJOR_VERSION	0xd
+#define TURIN_USB_STRUCT_MINOR_VERSION	0x13
+
+#define TURIN_USB_PORT_PER_CONTROLLER		2
+#define TURIN_USB_CONTROLLERS_PER_SOCKET	2
+#define TURIN_NUM_USB_PORTS	\
+	(TURIN_USB_PORT_PER_CONTROLLER * TURIN_USB_CONTROLLERS_PER_SOCKET)
+
+/*
+ * Structures copied from Genoa POC code, because Turin POC does not define these.
+ * It appears the USB structures are identical for Turin and Genoa.
+ */
+typedef struct {
+	uint8_t COMPDSTUNE;
+	uint8_t SQRXTUNE;
+	uint8_t TXFSLSTUNE;
+	uint8_t TXPREEMPAMPTUNE;
+	uint8_t TXPREEMPPULSETUNE;
+	uint8_t TXRISETUNE;
+	uint8_t TXVREFTUNE;
+	uint8_t TXHSXVTUNE;
+	uint8_t TXRESTUNE;
+} __packed FCH_USB20_PHY;
+
+typedef struct {
+	uint8_t RX_ANA_IQ_PHASE_ADJUST;
+	uint8_t RX_EQ_DELTA_IQ_OVRD_EN;
+	uint8_t RX_EQ_DELTA_IQ_OVRD_VAL;
+	uint8_t RX_IQ_PHASE_ADJUST;
+	uint8_t TX_VBOOST_LVL_EN;
+	uint8_t TX_VBOOST_LVL;
+	uint8_t RX_VREF_CTRL_EN;
+	uint8_t RX_VREF_CTRL;
+	uint8_t TX_VBOOST_LVL_EN_X;
+	uint8_t TX_VBOOST_LVL_X;
+	uint8_t RX_VREF_CTRL_EN_X;
+	uint8_t RX_VREF_CTRL_X;
+} __packed FCH_USB31_PHY;
+
+typedef struct {
+	uint8_t		Version_Major;
+	uint8_t		Version_Minor;
+	uint8_t		TableLength;
+	uint8_t		Reserved0;
+	uint8_t		Usb20PhyEnable;
+	FCH_USB20_PHY	Usb20PhyPort[TURIN_NUM_USB_PORTS];
+	uint8_t		Reserved1;
+	uint8_t		S1Usb20PhyEnable;
+	FCH_USB20_PHY	S1Usb20PhyPort[TURIN_NUM_USB_PORTS];
+	uint8_t		Usb31PhyEnable;
+	FCH_USB31_PHY	Usb31PhyPort[TURIN_NUM_USB_PORTS];
+	uint8_t		S1Usb31PhyEnable;
+	FCH_USB31_PHY	S1Usb31PhyPort[TURIN_NUM_USB_PORTS];
+} __packed FCH_USB_OEM_PLATFORM_TABLE;
+
+static FCH_USB_OEM_PLATFORM_TABLE usb_config = { 0 };
+
 void SIL_STATUS_report(const char *function, const int status)
 {
 	const int log_level = status == SilPass ? BIOS_DEBUG : BIOS_ERR;
@@ -42,30 +112,52 @@ void SIL_STATUS_report(const char *function, const int status)
 
 	int i;
 	for (i = 0; i < ARRAY_SIZE(errors); i++) {
-		if (errors[i].status == status)
+		if (errors[i].status == status) {
 			error_string = errors[i].string;
+			break;
+		}
 	}
 	printk(log_level, "%s returned %d (%s)\n", function, status, error_string);
 }
 
 static void setup_rc_manager_default(void)
 {
-	DFX_RCMGR_INPUT_BLK *rc_mgr_input_block = SilFindStructure(SilId_RcManager,  0);
+	DFX_RCMGR_INPUT_BLK *rc_mgr_input_block = SilFindStructure(SilId_RcManager, 0);
+
 	/* Let openSIL distribute the resources to the different PCI roots */
 	rc_mgr_input_block->SetRcBasedOnNv = false;
 
 	/* Currently 1P is the only supported configuration */
 	rc_mgr_input_block->SocketNumber = 1;
-	rc_mgr_input_block->RbsPerSocket = 4; /* PCI root bridges per socket */
+	rc_mgr_input_block->RbsPerSocket = 8; /* PCI root bridges per socket */
 	rc_mgr_input_block->McptEnable = true;
 	rc_mgr_input_block->PciExpressBaseAddress = CONFIG_ECAM_MMCONF_BASE_ADDRESS;
 	rc_mgr_input_block->BottomMmioReservedForPrimaryRb = 4ull * GiB - 32 * MiB;
 	rc_mgr_input_block->MmioSizePerRbForNonPciDevice = 16 * MiB;
-	/* MmioAbove4GLimit will be adjusted down in openSIL */
-	rc_mgr_input_block->MmioAbove4GLimit = POWER_OF_2(cpu_phys_address_size());
+	/*
+	 * Turin has 52 bits of available physical address space without SME
+	 * enabled. To avoid using 5-level paging (which we do not support yet
+	 * in coreboot and UEFI payload) required to cover MMIO above 48 bits
+	 * of address space (since 4-level paging can cover only 48 bits of
+	 * physical address space), limit the MMIO to maximum of 48 bits.
+	 * MmioAbove4GLimit will be adjusted down in openSIL if needed.
+	 */
+	rc_mgr_input_block->MmioAbove4GLimit = POWER_OF_2(MIN(48, cpu_phys_address_size()));
 	rc_mgr_input_block->Above4GMmioSizePerRbForNonPciDevice = 0;
 }
 
+static void setup_data_fabric_default(void)
+{
+	DFCLASS_INPUT_BLK *df_input_block = SilFindStructure(SilId_DfClass, 0);
+
+	if (!df_input_block) {
+		printk(BIOS_ERR, "OpenSIL: Data Fabric block not found\n");
+		return;
+	}
+
+	df_input_block->AmdPciExpressBaseAddress = CONFIG_ECAM_MMCONF_BASE_ADDRESS;
+}
+
 #define NUM_XHCI_CONTROLLERS 2
 static void configure_usb(void)
 {
@@ -73,6 +165,7 @@ static void configure_usb(void)
 	const struct soc_usb_config *usb = &soc_config->usb;
 
 	FCHUSB_INPUT_BLK *fch_usb_data = SilFindStructure(SilId_FchUsb, 0);
+
 	fch_usb_data->Xhci0Enable = usb->xhci0_enable;
 	fch_usb_data->Xhci1Enable = usb->xhci1_enable;
 	fch_usb_data->Xhci2Enable = false; /* there's no XHCI2 on this SoC */
@@ -85,25 +178,37 @@ static void configure_usb(void)
 	fch_usb_data->XhciOcPolarityCfgLow = usb->polarity_cfg_low;
 	fch_usb_data->Usb3PortForceGen1 = usb->usb3_force_gen1.raw;
 
-	/* Instead of overwriting the whole OemUsbConfigurationTable, only copy the relevant
-	   fields to the pre-populated data structure */
-	fch_usb_data->OemUsbConfigurationTable.Usb31PhyEnable = usb->usb31_phy_enable;
-	if (usb->usb31_phy_enable)
-		memcpy(&fch_usb_data->OemUsbConfigurationTable.Usb31PhyPort, usb->usb31_phy,
-		       sizeof(fch_usb_data->OemUsbConfigurationTable.Usb31PhyPort));
-	fch_usb_data->OemUsbConfigurationTable.Usb31PhyEnable = usb->s1_usb31_phy_enable;
-	if (usb->s1_usb31_phy_enable)
-		memcpy(&fch_usb_data->OemUsbConfigurationTable.S1Usb31PhyPort, usb->s1_usb31_phy,
-		       sizeof(fch_usb_data->OemUsbConfigurationTable.S1Usb31PhyPort));
+	memset(&usb_config, 0, sizeof(usb_config));
+
+	usb_config.Version_Major = TURIN_USB_STRUCT_MAJOR_VERSION;
+	usb_config.Version_Minor = TURIN_USB_STRUCT_MINOR_VERSION;
+	usb_config.TableLength = sizeof(FCH_USB_OEM_PLATFORM_TABLE);
+
+	usb_config.Usb31PhyEnable = usb->usb31_phy_enable;
+	memcpy(usb_config.Usb31PhyPort, usb->usb31_phy, sizeof(usb_config.Usb31PhyPort));
+
+	usb_config.S1Usb31PhyEnable = usb->s1_usb31_phy_enable;
+	memcpy(usb_config.S1Usb31PhyPort, usb->s1_usb31_phy, sizeof(usb_config.S1Usb31PhyPort));
+
+	fch_usb_data->OemUsbConfigurationTable = (uintptr_t)&usb_config;
 }
 
 #define NUM_SATA_CONTROLLERS 4
 static void configure_sata(void)
 {
 	FCHSATA_INPUT_BLK *fch_sata_data = SilFindStructure(SilId_FchSata, 0);
-	FCH_SATA2 *fch_sata_defaults = GetFchSataData();
+	FCHSATA_INPUT_BLK *fch_sata_defaults = FchSataGetInputBlk();
+	struct device *sata[NUM_SATA_CONTROLLERS] = {
+		DEV_PTR(sata_2_0),
+		DEV_PTR(sata_2_1),
+		DEV_PTR(sata_7_0),
+		DEV_PTR(sata_7_1)
+	};
+
 	for (int i = 0; i < NUM_SATA_CONTROLLERS; i++) {
 		fch_sata_data[i] = fch_sata_defaults[i];
+		fch_sata_data[i].SataAhciSsid = (sata[i])->subsystem_vendor |
+						((uint32_t)((sata[i])->subsystem_device) << 16);
 		fch_sata_data[i].SataSetMaxGen2 = false;
 		fch_sata_data[i].SataMsiEnable = true;
 		fch_sata_data[i].SataEspPort = 0xFF;
@@ -115,6 +220,93 @@ static void configure_sata(void)
 	}
 }
 
+static void configure_fch_isa(void)
+{
+	FCHISA_INPUT_BLK *fch_isa_data = SilFindStructure(SilId_FchIsa, 0);
+	struct device *lpc = DEV_PTR(lpc_bridge);
+
+	fch_isa_data->LpcConfig.LpcSsid = lpc->subsystem_vendor |
+					  ((uint32_t)lpc->subsystem_device << 16);
+
+	/* Keep defaults that were set by either EFS or coreboot */
+	fch_isa_data->SpiConfig.SpiSpeed = 0;
+	fch_isa_data->SpiConfig.SpiTpmSpeed = 0;
+	fch_isa_data->SpiConfig.WriteSpeed = 0;
+}
+
+#define FCH_DEV_ENABLE(dev, aoac_bit) \
+	fch_data->FchRunTime.FchDeviceEnableMap |= ((DEV_PTR(dev))->enabled ? aoac_bit : 0)
+
+static void configure_fch_acpi(void)
+{
+	FCHHWACPI_INPUT_BLK *fch_hwacpi_data = SilFindStructure(SilId_FchHwAcpiP, 0);
+	FCHCLASS_INPUT_BLK *fch_data = SilFindStructure(SilId_FchClass, 0);
+	struct device *smb = DEV_PTR(smbus);
+
+	fch_data->Smbus.SmbusSsid = smb->subsystem_vendor |
+				    ((uint32_t)smb->subsystem_device << 16);
+
+	fch_data->FchBldCfg.CfgSioPmeBaseAddress = 0;
+	fch_data->FchBldCfg.CfgAcpiPm1EvtBlkAddr = ACPI_PM_EVT_BLK;
+	fch_data->FchBldCfg.CfgAcpiPm1CntBlkAddr = ACPI_PM1_CNT_BLK;
+	fch_data->FchBldCfg.CfgAcpiPmTmrBlkAddr = ACPI_PM_TMR_BLK;
+	fch_data->FchBldCfg.CfgCpuControlBlkAddr = ACPI_CSTATE_CONTROL;
+	fch_data->FchBldCfg.CfgAcpiGpe0BlkAddr = ACPI_GPE0_BLK;
+	fch_data->FchBldCfg.CfgSmiCmdPortAddr = APM_CNT;
+
+	fch_data->CfgIoApicIdPreDefEnable = true;
+	fch_data->FchIoApicId = 128;
+
+	fch_data->WdtEnable = false;
+
+	/* Servers usually don't have KBC on SIO */
+	fch_data->Misc.NoneSioKbcSupport = true;
+
+	fch_hwacpi_data->PwrFailShadow = (CONFIG_MAINBOARD_POWER_FAILURE_STATE == 2) ?
+						3 : CONFIG_MAINBOARD_POWER_FAILURE_STATE;
+
+	fch_data->FchRunTime.FchDeviceEnableMap = 0;
+	FCH_DEV_ENABLE(i2c_0, FCH_AOAC_DEV_I2C0);
+	FCH_DEV_ENABLE(i2c_1, FCH_AOAC_DEV_I2C1);
+	FCH_DEV_ENABLE(i2c_2, FCH_AOAC_DEV_I2C2);
+	FCH_DEV_ENABLE(i2c_3, FCH_AOAC_DEV_I2C3);
+	FCH_DEV_ENABLE(i2c_4, FCH_AOAC_DEV_I2C4);
+	FCH_DEV_ENABLE(i2c_5, FCH_AOAC_DEV_I2C5);
+	FCH_DEV_ENABLE(uart_0, FCH_AOAC_DEV_UART0);
+	FCH_DEV_ENABLE(uart_1, FCH_AOAC_DEV_UART1);
+	FCH_DEV_ENABLE(uart_2, FCH_AOAC_DEV_UART2);
+	FCH_DEV_ENABLE(i3c_0, FCH_AOAC_DEV_I3C0);
+	FCH_DEV_ENABLE(i3c_1, FCH_AOAC_DEV_I3C1);
+	FCH_DEV_ENABLE(i3c_2, FCH_AOAC_DEV_I3C2);
+	FCH_DEV_ENABLE(i3c_3, FCH_AOAC_DEV_I3C3);
+}
+
+static void configure_sdxi(void)
+{
+	MPIOCLASS_INPUT_BLK *mpio_data = SilFindStructure(SilId_MpioClass, 0);
+	SDXICLASS_INPUT_BLK *sdxi_data = SilFindStructure(SilId_SdxiClass, 0);
+
+	mpio_data->AmdFabricSdxi = true;
+	sdxi_data->AmdFabricSdxi = true;
+}
+
+static void configure_ccx(void)
+{
+	CCXCLASS_DATA_BLK *ccx_data = SilFindStructure(SilId_CcxClass, 0);
+
+	if (CONFIG(XAPIC_ONLY) || CONFIG(X2APIC_LATE_WORKAROUND))
+		ccx_data->CcxInputBlock.AmdApicMode = xApicMode;
+	else if (CONFIG(X2APIC_ONLY))
+		ccx_data->CcxInputBlock.AmdApicMode = x2ApicMode;
+	else
+		ccx_data->CcxInputBlock.AmdApicMode = ApicAutoMode;
+
+	ccx_data->CcxInputBlock.EnableAvx512 = 1;
+	ccx_data->CcxInputBlock.EnableSvmX2AVIC = 1;
+	ccx_data->CcxInputBlock.EnableSvmAVIC = true;
+	ccx_data->CcxInputBlock.AmdCStateIoBaseAddress = ACPI_CSTATE_CONTROL;
+}
+
 void setup_opensil(void)
 {
 	const SIL_STATUS debug_ret = SilDebugSetup(HostDebugService);
@@ -127,8 +319,13 @@ void setup_opensil(void)
 	SIL_STATUS_report("xSimAssignMemory", assign_mem_ret);
 
 	setup_rc_manager_default();
+	setup_data_fabric_default();
+	configure_ccx();
+	configure_fch_isa();
+	configure_fch_acpi();
 	configure_usb();
 	configure_sata();
+	configure_sdxi();
 }
 
 static void opensil_entry(SIL_TIMEPOINT timepoint)
@@ -138,13 +335,13 @@ static void opensil_entry(SIL_TIMEPOINT timepoint)
 
 	switch (tp) {
 	case SIL_TP1:
-		ret = InitializeSiTp1();
+		ret = InitializeAMDSiTp1();
 		break;
 	case SIL_TP2:
-		ret = InitializeSiTp2();
+		ret = InitializeAMDSiTp2();
 		break;
 	case SIL_TP3:
-		ret = InitializeSiTp3();
+		ret = InitializeAMDSiTp3();
 		break;
 	default:
 		printk(BIOS_ERR, "Unknown openSIL timepoint\n");
@@ -176,5 +373,3 @@ void opensil_xSIM_timepoint_3(void)
 {
 	opensil_entry(SIL_TP3);
 }
-
-/* TODO: also call timepoints 2 and 3 from coreboot. Are they NOOP? */

From 90a5942254e50a85f022e3f2bfaf99efe68a0812 Mon Sep 17 00:00:00 2001
From: Luca Lai <luca.lai@lcfc.corp-partner.google.com>
Date: Mon, 26 Jan 2026 10:28:53 +0800
Subject: [PATCH 3161/3886] mb/fatcat/var/ruby: Remove rtd3 setting

I checked with the EE team. The previous status was neither D3hot
nor D3cold; it was in idle state, with power consumption around 1W.

With the locally tested BIOS that includes this change, the system
now enters D3hot and the power consumption is reduced to about 0.4W,
achieving the power-saving goal.

BUG=b:475990377
BRANCH=none
TEST=Build and boot to OS, check the code change could obtain
power saving.

Change-Id: Ib407e68dc70509e4431d87993597cd096dc0d9bc
Signed-off-by: Luca Lai <luca.lai@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90907
Reviewed-by: YH Lin <yueherngl@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/google/fatcat/variants/ruby/overridetree.cb | 7 -------
 1 file changed, 7 deletions(-)

diff --git a/src/mainboard/google/fatcat/variants/ruby/overridetree.cb b/src/mainboard/google/fatcat/variants/ruby/overridetree.cb
index 0ad94b8912..f2a4e75198 100644
--- a/src/mainboard/google/fatcat/variants/ruby/overridetree.cb
+++ b/src/mainboard/google/fatcat/variants/ruby/overridetree.cb
@@ -265,13 +265,6 @@ chip soc/intel/pantherlake
 			.clk_req = 6,
 			.flags = PCIE_RP_CLK_REQ_DETECT | PCIE_RP_LTR | PCIE_RP_AER,
 			}"
-			chip soc/intel/common/block/pcie/rtd3
-				register "is_storage" = "true"
-				register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B16)"
-				register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B09)"
-				register "srcclk_pin" = "6"
-				device generic 0 on end
-			end
 		end # Gen4 M.2 SSD
 
 		device ref cnvi_wifi on

From 4a71e5fe6643b3e2b0c4b1bc21ed4a5d9fe62d80 Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Sun, 25 Jan 2026 15:38:47 -0600
Subject: [PATCH 3162/3886] tree: Remove Ice Lake PCI ID remnants

Commit ad6e3c847f4b ("tree: Drop Intel Ice Lake support") removed most
of the Ice Lake PCI IDs, but missed the ones with the ICP prefix
(Ice Point? Ice Lake Point?). Remove all PCI_DID_INTEL_ICP* defines
and references in common block drivers.

Change-Id: I9d33c69d174130aa781a00441fca367e0a67bcb4
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90904
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
---
 src/include/device/pci_ids.h                  | 35 -------------------
 .../intel/common/block/fast_spi/fast_spi.c    |  1 -
 src/soc/intel/common/block/i2c/i2c.c          |  6 ----
 src/soc/intel/common/block/pcie/pcie.c        | 16 ---------
 src/soc/intel/common/block/pmc/pmc.c          |  1 -
 src/soc/intel/common/block/sata/sata.c        |  1 -
 src/soc/intel/common/block/smbus/smbus.c      |  1 -
 src/soc/intel/common/block/spi/spi.c          |  3 --
 src/soc/intel/common/block/uart/uart.c        |  3 --
 src/soc/intel/common/block/xdci/xdci.c        |  1 -
 src/soc/intel/common/block/xhci/xhci.c        |  1 -
 11 files changed, 69 deletions(-)

diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h
index ed3ba38d99..d990b86a02 100644
--- a/src/include/device/pci_ids.h
+++ b/src/include/device/pci_ids.h
@@ -3525,23 +3525,6 @@
 #define PCI_DID_INTEL_CNL_LP_PCIE_RP15			0x9db6
 #define PCI_DID_INTEL_CNL_LP_PCIE_RP16			0x9db7
 
-#define PCI_DID_INTEL_ICP_LP_PCIE_RP1			0x34b8
-#define PCI_DID_INTEL_ICP_LP_PCIE_RP2			0x34b9
-#define PCI_DID_INTEL_ICP_LP_PCIE_RP3			0x34ba
-#define PCI_DID_INTEL_ICP_LP_PCIE_RP4			0x34bb
-#define PCI_DID_INTEL_ICP_LP_PCIE_RP5			0x34bc
-#define PCI_DID_INTEL_ICP_LP_PCIE_RP6			0x34bd
-#define PCI_DID_INTEL_ICP_LP_PCIE_RP7			0x34be
-#define PCI_DID_INTEL_ICP_LP_PCIE_RP8			0x34bf
-#define PCI_DID_INTEL_ICP_LP_PCIE_RP9			0x34b0
-#define PCI_DID_INTEL_ICP_LP_PCIE_RP10			0x34b1
-#define PCI_DID_INTEL_ICP_LP_PCIE_RP11			0x34b2
-#define PCI_DID_INTEL_ICP_LP_PCIE_RP12			0x34b3
-#define PCI_DID_INTEL_ICP_LP_PCIE_RP13			0x34b4
-#define PCI_DID_INTEL_ICP_LP_PCIE_RP14			0x34b5
-#define PCI_DID_INTEL_ICP_LP_PCIE_RP15			0x34b6
-#define PCI_DID_INTEL_ICP_LP_PCIE_RP16			0x34b7
-
 #define PCI_DID_INTEL_TGP_LP_PCIE_RP1			0xa0b8
 #define PCI_DID_INTEL_TGP_LP_PCIE_RP2			0xa0b9
 #define PCI_DID_INTEL_TGP_LP_PCIE_RP3			0xa0ba
@@ -3930,7 +3913,6 @@
 #define PCI_DID_INTEL_CNP_H_SATA		0xa352
 #define PCI_DID_INTEL_CNP_H_HALO_SATA		0xa353
 #define PCI_DID_INTEL_CNP_LP_SATA		0x9dd3
-#define PCI_DID_INTEL_ICP_U_SATA		0x34d3
 #define PCI_DID_INTEL_CMP_SATA			0x02d5
 #define PCI_DID_INTEL_CMP_PREMIUM_SATA		0x02d7
 #define PCI_DID_INTEL_CMP_LP_SATA		0x02d3
@@ -3980,7 +3962,6 @@
 #define PCI_DID_INTEL_GLK_PMC			0x3194
 #define PCI_DID_INTEL_CNL_PMC			0x9da1
 #define PCI_DID_INTEL_CNP_H_PMC			0xa321
-#define PCI_DID_INTEL_ICP_PMC			0x34a1
 #define PCI_DID_INTEL_CMP_PMC			0x02a1
 #define PCI_DID_INTEL_CMP_H_PMC			0x06a1
 #define PCI_DID_INTEL_TGP_PMC			0xa0a1
@@ -4043,12 +4024,6 @@
 #define PCI_DID_INTEL_CNP_H_I2C1		0xa369
 #define PCI_DID_INTEL_CNP_H_I2C2		0xa36a
 #define PCI_DID_INTEL_CNP_H_I2C3		0xa36b
-#define PCI_DID_INTEL_ICP_I2C0			0x34e8
-#define PCI_DID_INTEL_ICP_I2C1			0x34e9
-#define PCI_DID_INTEL_ICP_I2C2			0x34ea
-#define PCI_DID_INTEL_ICP_I2C3			0x34eb
-#define PCI_DID_INTEL_ICP_I2C4			0x34c5
-#define PCI_DID_INTEL_ICP_I2C5			0x34c6
 #define PCI_DID_INTEL_CMP_I2C0			0x02e8
 #define PCI_DID_INTEL_CMP_I2C1			0x02e9
 #define PCI_DID_INTEL_CMP_I2C2			0x02ea
@@ -4201,9 +4176,6 @@
 #define PCI_DID_INTEL_CNP_H_UART0		0xa328
 #define PCI_DID_INTEL_CNP_H_UART1		0xa329
 #define PCI_DID_INTEL_CNP_H_UART2		0xa347
-#define PCI_DID_INTEL_ICP_UART0			0x34a8
-#define PCI_DID_INTEL_ICP_UART1			0x34a9
-#define PCI_DID_INTEL_ICP_UART2			0x34c7
 #define PCI_DID_INTEL_CMP_UART0			0x02a8
 #define PCI_DID_INTEL_CMP_UART1			0x02a9
 #define PCI_DID_INTEL_CMP_UART2			0x02c7
@@ -4306,10 +4278,6 @@
 #define PCI_DID_INTEL_CNP_H_SPI1		0xa32b
 #define PCI_DID_INTEL_CNP_H_SPI2		0xa37b
 #define PCI_DID_INTEL_CNP_H_HWSEQ_SPI		0xa324
-#define PCI_DID_INTEL_ICP_SPI0			0x34aa
-#define PCI_DID_INTEL_ICP_SPI1			0x34ab
-#define PCI_DID_INTEL_ICP_SPI2			0x34fb
-#define PCI_DID_INTEL_ICP_HWSEQ_SPI		0x34a4
 #define PCI_DID_INTEL_CMP_SPI0			0x02aa
 #define PCI_DID_INTEL_CMP_SPI1			0x02ab
 #define PCI_DID_INTEL_CMP_SPI2			0x02fb
@@ -4781,7 +4749,6 @@
 #define PCI_DID_INTEL_LWB_SMBUS_SUPER			0xa223
 #define PCI_DID_INTEL_CNL_SMBUS				0x9da3
 #define PCI_DID_INTEL_CNP_H_SMBUS			0xa323
-#define PCI_DID_INTEL_ICP_LP_SMBUS			0x34a3
 #define PCI_DID_INTEL_CMP_SMBUS				0x02a3
 #define PCI_DID_INTEL_CMP_H_SMBUS			0x06a3
 #define PCI_DID_INTEL_TGP_LP_SMBUS			0xa0a3
@@ -4822,7 +4789,6 @@
 #define PCI_DID_INTEL_UPT_H_XHCI		0xa2af
 #define PCI_DID_INTEL_CNL_LP_XHCI		0x9ded
 #define PCI_DID_INTEL_CNP_H_XHCI		0xa36d
-#define PCI_DID_INTEL_ICP_LP_XHCI		0x34ed
 #define PCI_DID_INTEL_CMP_LP_XHCI		0x02ed
 #define PCI_DID_INTEL_CMP_H_XHCI		0x06ed
 #define PCI_DID_INTEL_TGP_LP_XHCI		0xa0ed
@@ -5086,7 +5052,6 @@
 #define PCI_DID_INTEL_SPT_LP_XDCI		0x9d30
 #define PCI_DID_INTEL_CNL_LP_XDCI		0x9dee
 #define PCI_DID_INTEL_CNP_H_XDCI		0xa36e
-#define PCI_DID_INTEL_ICP_LP_XDCI		0x34ee
 #define PCI_DID_INTEL_CMP_LP_XDCI		0x02ee
 #define PCI_DID_INTEL_CMP_H_XDCI		0x06ee
 #define PCI_DID_INTEL_TGP_LP_XDCI		0xa0ee
diff --git a/src/soc/intel/common/block/fast_spi/fast_spi.c b/src/soc/intel/common/block/fast_spi/fast_spi.c
index 627ab28e9b..a939369ecd 100644
--- a/src/soc/intel/common/block/fast_spi/fast_spi.c
+++ b/src/soc/intel/common/block/fast_spi/fast_spi.c
@@ -572,7 +572,6 @@ static const unsigned short pci_device_ids[] = {
 	PCI_DID_INTEL_CMP_H_HWSEQ_SPI,
 	PCI_DID_INTEL_CNL_HWSEQ_SPI,
 	PCI_DID_INTEL_CNP_H_HWSEQ_SPI,
-	PCI_DID_INTEL_ICP_HWSEQ_SPI,
 	PCI_DID_INTEL_JSP_HWSEQ_SPI,
 	PCI_DID_INTEL_LWB_SPI,
 	PCI_DID_INTEL_LWB_SPI_SUPER,
diff --git a/src/soc/intel/common/block/i2c/i2c.c b/src/soc/intel/common/block/i2c/i2c.c
index 161e61fc47..7609b217a3 100644
--- a/src/soc/intel/common/block/i2c/i2c.c
+++ b/src/soc/intel/common/block/i2c/i2c.c
@@ -248,12 +248,6 @@ static const unsigned short pci_device_ids[] = {
 	PCI_DID_INTEL_CNP_H_I2C1,
 	PCI_DID_INTEL_CNP_H_I2C2,
 	PCI_DID_INTEL_CNP_H_I2C3,
-	PCI_DID_INTEL_ICP_I2C0,
-	PCI_DID_INTEL_ICP_I2C1,
-	PCI_DID_INTEL_ICP_I2C2,
-	PCI_DID_INTEL_ICP_I2C3,
-	PCI_DID_INTEL_ICP_I2C4,
-	PCI_DID_INTEL_ICP_I2C5,
 	PCI_DID_INTEL_CMP_I2C0,
 	PCI_DID_INTEL_CMP_I2C1,
 	PCI_DID_INTEL_CMP_I2C2,
diff --git a/src/soc/intel/common/block/pcie/pcie.c b/src/soc/intel/common/block/pcie/pcie.c
index 4b64f85b8a..31e70d6edc 100644
--- a/src/soc/intel/common/block/pcie/pcie.c
+++ b/src/soc/intel/common/block/pcie/pcie.c
@@ -249,22 +249,6 @@ static const unsigned short pcie_device_ids[] = {
 	PCI_DID_INTEL_CNP_H_PCIE_RP22,
 	PCI_DID_INTEL_CNP_H_PCIE_RP23,
 	PCI_DID_INTEL_CNP_H_PCIE_RP24,
-	PCI_DID_INTEL_ICP_LP_PCIE_RP1,
-	PCI_DID_INTEL_ICP_LP_PCIE_RP2,
-	PCI_DID_INTEL_ICP_LP_PCIE_RP3,
-	PCI_DID_INTEL_ICP_LP_PCIE_RP4,
-	PCI_DID_INTEL_ICP_LP_PCIE_RP5,
-	PCI_DID_INTEL_ICP_LP_PCIE_RP6,
-	PCI_DID_INTEL_ICP_LP_PCIE_RP7,
-	PCI_DID_INTEL_ICP_LP_PCIE_RP8,
-	PCI_DID_INTEL_ICP_LP_PCIE_RP9,
-	PCI_DID_INTEL_ICP_LP_PCIE_RP10,
-	PCI_DID_INTEL_ICP_LP_PCIE_RP11,
-	PCI_DID_INTEL_ICP_LP_PCIE_RP12,
-	PCI_DID_INTEL_ICP_LP_PCIE_RP13,
-	PCI_DID_INTEL_ICP_LP_PCIE_RP14,
-	PCI_DID_INTEL_ICP_LP_PCIE_RP15,
-	PCI_DID_INTEL_ICP_LP_PCIE_RP16,
 	PCI_DID_INTEL_CMP_LP_PCIE_RP1,
 	PCI_DID_INTEL_CMP_LP_PCIE_RP2,
 	PCI_DID_INTEL_CMP_LP_PCIE_RP3,
diff --git a/src/soc/intel/common/block/pmc/pmc.c b/src/soc/intel/common/block/pmc/pmc.c
index 80db323ac6..0b7a9495ce 100644
--- a/src/soc/intel/common/block/pmc/pmc.c
+++ b/src/soc/intel/common/block/pmc/pmc.c
@@ -129,7 +129,6 @@ static const unsigned short pci_device_ids[] = {
 	PCI_DID_INTEL_APL_PMC,
 	PCI_DID_INTEL_GLK_PMC,
 	PCI_DID_INTEL_CNP_H_PMC,
-	PCI_DID_INTEL_ICP_PMC,
 	PCI_DID_INTEL_CMP_PMC,
 	PCI_DID_INTEL_CMP_H_PMC,
 	PCI_DID_INTEL_TGP_PMC,
diff --git a/src/soc/intel/common/block/sata/sata.c b/src/soc/intel/common/block/sata/sata.c
index f406096c85..0f85faed50 100644
--- a/src/soc/intel/common/block/sata/sata.c
+++ b/src/soc/intel/common/block/sata/sata.c
@@ -60,7 +60,6 @@ static const unsigned short pci_device_ids[] = {
 	PCI_DID_INTEL_CNP_H_SATA,
 	PCI_DID_INTEL_CNP_H_HALO_SATA,
 	PCI_DID_INTEL_CNP_LP_SATA,
-	PCI_DID_INTEL_ICP_U_SATA,
 	PCI_DID_INTEL_CMP_SATA,
 	PCI_DID_INTEL_CMP_PREMIUM_SATA,
 	PCI_DID_INTEL_CMP_LP_SATA,
diff --git a/src/soc/intel/common/block/smbus/smbus.c b/src/soc/intel/common/block/smbus/smbus.c
index dba5ed29d8..ebaf655499 100644
--- a/src/soc/intel/common/block/smbus/smbus.c
+++ b/src/soc/intel/common/block/smbus/smbus.c
@@ -66,7 +66,6 @@ static const unsigned short pci_device_ids[] = {
 	PCI_DID_INTEL_EBG_SMBUS,
 	PCI_DID_INTEL_LWB_SMBUS_SUPER,
 	PCI_DID_INTEL_LWB_SMBUS,
-	PCI_DID_INTEL_ICP_LP_SMBUS,
 	PCI_DID_INTEL_CMP_SMBUS,
 	PCI_DID_INTEL_CMP_H_SMBUS,
 	PCI_DID_INTEL_TGP_LP_SMBUS,
diff --git a/src/soc/intel/common/block/spi/spi.c b/src/soc/intel/common/block/spi/spi.c
index 680e14e035..9ac9719c7a 100644
--- a/src/soc/intel/common/block/spi/spi.c
+++ b/src/soc/intel/common/block/spi/spi.c
@@ -164,9 +164,6 @@ static const unsigned short pci_device_ids[] = {
 	PCI_DID_INTEL_CNP_H_SPI0,
 	PCI_DID_INTEL_CNP_H_SPI1,
 	PCI_DID_INTEL_CNP_H_SPI2,
-	PCI_DID_INTEL_ICP_SPI0,
-	PCI_DID_INTEL_ICP_SPI1,
-	PCI_DID_INTEL_ICP_SPI2,
 	PCI_DID_INTEL_CMP_SPI0,
 	PCI_DID_INTEL_CMP_SPI1,
 	PCI_DID_INTEL_CMP_SPI2,
diff --git a/src/soc/intel/common/block/uart/uart.c b/src/soc/intel/common/block/uart/uart.c
index 0e9132d4c1..2b2c8c28fc 100644
--- a/src/soc/intel/common/block/uart/uart.c
+++ b/src/soc/intel/common/block/uart/uart.c
@@ -402,9 +402,6 @@ static const unsigned short pci_device_ids[] = {
 	PCI_DID_INTEL_CNP_H_UART0,
 	PCI_DID_INTEL_CNP_H_UART1,
 	PCI_DID_INTEL_CNP_H_UART2,
-	PCI_DID_INTEL_ICP_UART0,
-	PCI_DID_INTEL_ICP_UART1,
-	PCI_DID_INTEL_ICP_UART2,
 	PCI_DID_INTEL_CMP_UART0,
 	PCI_DID_INTEL_CMP_UART1,
 	PCI_DID_INTEL_CMP_UART2,
diff --git a/src/soc/intel/common/block/xdci/xdci.c b/src/soc/intel/common/block/xdci/xdci.c
index 6916d8c3f5..3ead495010 100644
--- a/src/soc/intel/common/block/xdci/xdci.c
+++ b/src/soc/intel/common/block/xdci/xdci.c
@@ -39,7 +39,6 @@ static const unsigned short pci_device_ids[] = {
 	PCI_DID_INTEL_CNL_LP_XDCI,
 	PCI_DID_INTEL_GLK_XDCI,
 	PCI_DID_INTEL_CNP_H_XDCI,
-	PCI_DID_INTEL_ICP_LP_XDCI,
 	PCI_DID_INTEL_CMP_LP_XDCI,
 	PCI_DID_INTEL_CMP_H_XDCI,
 	PCI_DID_INTEL_TGP_LP_XDCI,
diff --git a/src/soc/intel/common/block/xhci/xhci.c b/src/soc/intel/common/block/xhci/xhci.c
index d12792dbb8..5eb73ed562 100644
--- a/src/soc/intel/common/block/xhci/xhci.c
+++ b/src/soc/intel/common/block/xhci/xhci.c
@@ -145,7 +145,6 @@ static const unsigned short pci_device_ids[] = {
 	PCI_DID_INTEL_LWB_XHCI,
 	PCI_DID_INTEL_LWB_XHCI_SUPER,
 	PCI_DID_INTEL_CNP_H_XHCI,
-	PCI_DID_INTEL_ICP_LP_XHCI,
 	PCI_DID_INTEL_CMP_LP_XHCI,
 	PCI_DID_INTEL_CMP_H_XHCI,
 	PCI_DID_INTEL_TGP_LP_XHCI,

From 23f97be6102e121903b8e356be8e61dc139d979a Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Sun, 25 Jan 2026 16:31:26 -0600
Subject: [PATCH 3163/3886] soc/intel/jasperlake: Add initial chipset.cb
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Similar to other Intel SoCs, create a chipset.cb for Jasperlake
giving alias names to all known PCI devices. Taken from comments in
existing JSL board devicetrees, cross-referenced against the publicly
available JSL EDS.

At the same time, remove the usb2_lte device aliases in the BOTEN and
DRAWCIA dedede variants, and replace their references with the new
usb2_port4 alias, since we can only have a single alias per device.

TEST=build boten and drawcia dedede variants

Change-Id: I32552dbe0ab5305ea44b5e89432603884cf6589f
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90899
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-by: Jakub "Kuba" Czapiga <czapiga@google.com>
---
 .../dedede/variants/boten/overridetree.cb     |   2 +-
 .../dedede/variants/drawcia/overridetree.cb   |   2 +-
 .../google/dedede/variants/drawcia/ramstage.c |   2 +-
 src/soc/intel/jasperlake/Kconfig              |   4 +
 src/soc/intel/jasperlake/chipset.cb           | 100 ++++++++++++++++++
 5 files changed, 107 insertions(+), 3 deletions(-)
 create mode 100644 src/soc/intel/jasperlake/chipset.cb

diff --git a/src/mainboard/google/dedede/variants/boten/overridetree.cb b/src/mainboard/google/dedede/variants/boten/overridetree.cb
index 56b2d935bc..a1c33fa809 100644
--- a/src/mainboard/google/dedede/variants/boten/overridetree.cb
+++ b/src/mainboard/google/dedede/variants/boten/overridetree.cb
@@ -156,7 +156,7 @@ chip soc/intel/jasperlake
 						register "reset_off_delay_ms" = "10"
 						register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A10)"
 						register "enable_delay_ms" = "20"
-						device usb 2.3 alias usb2_lte on end
+						device usb 2.3 on end
 					end
 					chip drivers/usb/acpi
 						register "desc" = ""UFCamera""
diff --git a/src/mainboard/google/dedede/variants/drawcia/overridetree.cb b/src/mainboard/google/dedede/variants/drawcia/overridetree.cb
index 3ba688fb67..12e45d9308 100644
--- a/src/mainboard/google/dedede/variants/drawcia/overridetree.cb
+++ b/src/mainboard/google/dedede/variants/drawcia/overridetree.cb
@@ -163,7 +163,7 @@ chip soc/intel/jasperlake
 						register "reset_off_delay_ms" = "20"
 						register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A10)"
 						register "enable_delay_ms" = "20"
-						device usb 2.3 alias lte_usb2 on
+						device usb 2.3 on
 							probe DB_PORTS DB_PORTS_1A_HDMI_LTE
 						end
 					end
diff --git a/src/mainboard/google/dedede/variants/drawcia/ramstage.c b/src/mainboard/google/dedede/variants/drawcia/ramstage.c
index be1b253219..543d7457a8 100644
--- a/src/mainboard/google/dedede/variants/drawcia/ramstage.c
+++ b/src/mainboard/google/dedede/variants/drawcia/ramstage.c
@@ -18,7 +18,7 @@ static void ext_vr_update(void)
 
 static void update_lte_device_drawcia(void)
 {
-	struct device *lte_usb2 = DEV_PTR(lte_usb2);
+	struct device *lte_usb2 = DEV_PTR(usb2_port4);
 	struct drivers_usb_acpi_config *config;
 	struct acpi_gpio lte_reset_gpio = ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_H0);
 
diff --git a/src/soc/intel/jasperlake/Kconfig b/src/soc/intel/jasperlake/Kconfig
index 727e9609ce..e80028ae80 100644
--- a/src/soc/intel/jasperlake/Kconfig
+++ b/src/soc/intel/jasperlake/Kconfig
@@ -105,6 +105,10 @@ config IFD_CHIPSET
 	string
 	default "jsl"
 
+config CHIPSET_DEVICETREE
+	string
+	default "soc/intel/jasperlake/chipset.cb"
+
 config IED_REGION_SIZE
 	hex
 	default 0x400000
diff --git a/src/soc/intel/jasperlake/chipset.cb b/src/soc/intel/jasperlake/chipset.cb
new file mode 100644
index 0000000000..f713d22595
--- /dev/null
+++ b/src/soc/intel/jasperlake/chipset.cb
@@ -0,0 +1,100 @@
+chip soc/intel/jasperlake
+
+	device cpu_cluster 0 on end
+
+	device domain 0 on
+		device pci 00.0 alias system_agent	on  end
+		device pci 02.0 alias igpu		off end
+		device pci 04.0 alias dptf		off end
+		device pci 05.0 alias ipu		off end
+		device pci 08.0 alias gna		off end
+		device pci 09.0 alias north_tracehub	off end
+		device pci 12.0 alias ish		off end
+		device pci 12.5 alias ufs_scs		off end
+		device pci 12.6 alias gspi2		off end
+		device pci 14.0 alias south_xhci	off
+			chip drivers/usb/acpi
+				register "type" = "UPC_TYPE_HUB"
+				device usb 0.0 alias xhci_root_hub off
+					chip drivers/usb/acpi
+						device usb 2.0 alias usb2_port1 off end
+					end
+					chip drivers/usb/acpi
+						device usb 2.1 alias usb2_port2 off end
+					end
+					chip drivers/usb/acpi
+						device usb 2.2 alias usb2_port3 off end
+					end
+					chip drivers/usb/acpi
+						device usb 2.3 alias usb2_port4 off end
+					end
+					chip drivers/usb/acpi
+						device usb 2.4 alias usb2_port5 off end
+					end
+					chip drivers/usb/acpi
+						device usb 2.5 alias usb2_port6 off end
+					end
+					chip drivers/usb/acpi
+						device usb 2.6 alias usb2_port7 off end
+					end
+					chip drivers/usb/acpi
+						device usb 2.7 alias usb2_port8 off end
+					end
+					chip drivers/usb/acpi
+						device usb 3.0 alias usb3_port1 off end
+					end
+					chip drivers/usb/acpi
+						device usb 3.1 alias usb3_port2 off end
+					end
+					chip drivers/usb/acpi
+						device usb 3.2 alias usb3_port3 off end
+					end
+					chip drivers/usb/acpi
+						device usb 3.3 alias usb3_port4 off end
+					end
+					chip drivers/usb/acpi
+						device usb 3.4 alias usb3_port5 off end
+					end
+					chip drivers/usb/acpi
+						device usb 3.5 alias usb3_port6 off end
+					end
+				end
+			end
+		end
+		device pci 14.1 alias south_xdci	off end
+		device pci 14.2 alias shared_ram	off end
+		device pci 14.3 alias cnvi_wifi		off end
+		device pci 14.5 alias sdxc		off end
+		device pci 15.0 alias i2c0		off end
+		device pci 15.1 alias i2c1		off end
+		device pci 15.2 alias i2c2		off end
+		device pci 15.3 alias i2c3		off end
+		device pci 16.0 alias heci1		off end
+		device pci 16.1 alias heci2		off end
+		device pci 16.4 alias heci3		off end
+		device pci 17.0 alias sata		off end
+		device pci 19.0 alias i2c4		off end
+		device pci 19.1 alias i2c5		off end
+		device pci 19.2 alias uart2		off end
+		device pci 1a.0 alias emmc		off end
+		device pci 1c.0 alias pcie_rp1		off end
+		device pci 1c.1 alias pcie_rp2		off end
+		device pci 1c.2 alias pcie_rp3		off end
+		device pci 1c.3 alias pcie_rp4		off end
+		device pci 1c.4 alias pcie_rp5		off end
+		device pci 1c.5 alias pcie_rp6		off end
+		device pci 1c.6 alias pcie_rp7		off end
+		device pci 1c.7 alias pcie_rp8		off end
+		device pci 1e.0 alias uart0		off end
+		device pci 1e.1 alias uart1		off end
+		device pci 1e.2 alias gspi0		off end
+		device pci 1e.3 alias gspi1		off end
+		device pci 1f.0 alias pch_espi		on  end
+		device pci 1f.1 alias p2sb		hidden end
+		device pci 1f.2 alias pmc		hidden end
+		device pci 1f.3 alias hda		off end
+		device pci 1f.4 alias smbus		off end
+		device pci 1f.5 alias fast_spi		on end
+		device pci 1f.7 alias south_tracehub	off end
+	end
+end

From c7b016bb7f964574c86741ba375d8ada94cdd575 Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Sun, 25 Jan 2026 17:16:20 -0600
Subject: [PATCH 3164/3886] mb/google/dedede: Use aliases in
 device/overridetrees

Convert all PCI device and USB port references in dedede baseboard
devicetree and variant overridetrees to use aliases from the Jasperlake
chipset.cb instead of direct device/function numbers. This improves
maintainability by using symbolic names, and reduces file size by
eliminating entries which match those in the chipset or baseboard
devicetrees.

TEST=Build all dedede variants

Change-Id: I00c8f79ab040cd634ea94d4d596128ef3d6f7e73
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90900
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
---
 .../dedede/variants/awasuki/overridetree.cb   |  54 ++++------
 .../dedede/variants/baseboard/devicetree.cb   | 102 ++++++------------
 .../dedede/variants/beadrix/overridetree.cb   |  30 +++---
 .../dedede/variants/blipper/overridetree.cb   |  28 ++---
 .../dedede/variants/boten/overridetree.cb     |  42 ++++----
 .../dedede/variants/boxy/overridetree.cb      |  41 ++++---
 .../dedede/variants/bugzzy/overridetree.cb    |  41 ++++---
 .../dedede/variants/cappy2/overridetree.cb    |  30 +++---
 .../dedede/variants/corori/overridetree.cb    |  41 +++----
 .../dedede/variants/cret/overridetree.cb      |  42 ++++----
 .../dedede/variants/dexi/overridetree.cb      |  49 +++++----
 .../dedede/variants/dibbi/overridetree.cb     |  48 ++++-----
 .../dedede/variants/dita/overridetree.cb      |  49 +++++----
 .../dedede/variants/drawcia/overridetree.cb   |  44 ++++----
 .../dedede/variants/driblee/overridetree.cb   |  43 +++-----
 .../dedede/variants/galtic/overridetree.cb    |  24 ++---
 .../dedede/variants/gooey/overridetree.cb     |  47 ++++----
 .../dedede/variants/haboki/overridetree.cb    |  35 +++---
 .../dedede/variants/kracko/overridetree.cb    |  42 ++++----
 .../dedede/variants/lalala/overridetree.cb    |  33 +++---
 .../dedede/variants/lantis/overridetree.cb    |  36 +++----
 .../dedede/variants/madoo/overridetree.cb     |  36 +++----
 .../dedede/variants/magolor/overridetree.cb   |  30 +++---
 .../variants/metaknight/overridetree.cb       |  24 ++---
 .../dedede/variants/pirika/overridetree.cb    |  24 ++---
 .../dedede/variants/sasuke/overridetree.cb    |  26 +++--
 .../dedede/variants/sasukette/overridetree.cb |  25 +++--
 .../dedede/variants/shotzo/overridetree.cb    |  46 ++++----
 .../dedede/variants/storo/overridetree.cb     |  37 ++++---
 .../dedede/variants/taranza/overridetree.cb   |  49 +++++----
 .../dedede/variants/waddledee/overridetree.cb |  30 +++---
 .../dedede/variants/waddledoo/overridetree.cb |  30 +++---
 32 files changed, 573 insertions(+), 685 deletions(-)

diff --git a/src/mainboard/google/dedede/variants/awasuki/overridetree.cb b/src/mainboard/google/dedede/variants/awasuki/overridetree.cb
index f791468b2b..570403f81f 100644
--- a/src/mainboard/google/dedede/variants/awasuki/overridetree.cb
+++ b/src/mainboard/google/dedede/variants/awasuki/overridetree.cb
@@ -84,7 +84,7 @@ chip soc/intel/jasperlake
 	register "SdCardPowerEnableActiveHigh" = "0"
 
 	device domain 0 on
-		device pci 04.0 on
+		device ref dptf on
 			chip drivers/intel/dptf
 				## sensor information
 				register "options.tsr[0].desc" = ""Ambient""
@@ -134,48 +134,30 @@ chip soc/intel/jasperlake
 				}"
 				device generic 0 on end
 			end
-		end # SA Thermal device
-		device pci 14.0 on
+		end
+		device ref south_xhci on
 			chip drivers/usb/acpi
-				device usb 0.0 on
-					chip drivers/usb/acpi
-						device usb 2.1 off end
-					end
-					chip drivers/usb/acpi
-						device usb 2.3 off end
-					end
-					chip drivers/usb/acpi
-						device usb 2.4 off end
-					end
+				device ref xhci_root_hub on
 					chip drivers/usb/acpi
 						register "desc" = ""User Facing Camera""
 						register "type" = "UPC_TYPE_INTERNAL"
 						register "has_power_resource" = "true"
 						register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D15)"
 						register "enable_delay_ms" = "20"
-						device usb 2.5 on end
-					end
-					chip drivers/usb/acpi
-						device usb 2.6 off end
-					end
-					chip drivers/usb/acpi
-						device usb 3.1 off end
-					end
-					chip drivers/usb/acpi
-						device usb 3.3 off end
+						device ref usb2_port6 on end
 					end
 				end
 			end
-		end # USB xHCI
-		device pci 14.3 on
+		end
+		device ref cnvi_wifi on
 			chip drivers/wifi/generic
 				register "wake" = "GPE0_PME_B0"
 				register "enable_cnvi_ddr_rfim" = "true"
 				register "add_acpi_dma_property" = "true"
 				device generic 0 on end
 			end
-		end # CNVi wifi
-		device pci 15.0 on
+		end
+		device ref i2c0 on
 			chip drivers/i2c/hid
 				register "generic.hid" = ""PNP0C50""
 				register "generic.desc" = ""PIXART Touchpad""
@@ -185,8 +167,8 @@ chip soc/intel/jasperlake
 				register "hid_desc_reg_offset" = "0x01"
 				device i2c 15 on end
 			end
-		end # I2C 0
-		device pci 15.2 on
+		end
+		device ref i2c2 on
 			probe TOUCHSCREEN TOUCHSCREEN_PRESENT
 			chip drivers/i2c/generic
 				register "hid" = ""ELAN0001""
@@ -206,8 +188,8 @@ chip soc/intel/jasperlake
 				register "has_power_resource" = "true"
 				device i2c 10 on end
 			end
-		end # I2C 2
-		device pci 19.0 on
+		end
+		device ref i2c4 on
 			chip drivers/i2c/rt5645
 				register "hid" = ""10EC5650""
 				register "name" = ""RT58""
@@ -217,20 +199,20 @@ chip soc/intel/jasperlake
 				register "jd_mode" = "2"
 				device i2c 1a on end
 			end
-		end # I2C 4
-		device pci 1c.7 on
+		end
+		device ref pcie_rp8 on
 			chip drivers/wifi/generic
 				register "wake" = "GPE0_DW2_03"
 				device pci 00.0 on end
 			end
-		end # PCI Express Root Port 8 - WLAN
-		device pci 1f.3 on
+		end
+		device ref hda on
 			chip drivers/sof
 				register "spkr_tplg" = "rt5650_sp"
 				register "jack_tplg" = "rt5650_hp"
 				register "mic_tplg" = "_2ch_pdm0"
 				device generic 0 on end
 			end
-		end # Intel HDA/cAVS
+		end
 	end
 end
diff --git a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb
index 05c77da3e5..240c3e6c4b 100644
--- a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb
+++ b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb
@@ -228,11 +228,10 @@ chip soc/intel/jasperlake
 	register "xhci_lfps_sampling_offtime_ms" = "9"
 
 	device domain 0 on
-		device pci 00.0 on end # Host Bridge
-		device pci 02.0 on
+		device ref igpu on
 			register "gfx" = "GMA_DEFAULT_PANEL(0)"
-		end # Integrated Graphics Device
-		device pci 04.0 on
+		end
+		device ref dptf on
 			# Default DPTF Policy for all Dedede boards if not overridden
 			chip drivers/intel/dptf
 				## Passive Policy
@@ -283,132 +282,96 @@ chip soc/intel/jasperlake
 
 				device generic 0 on end
 			end
-		end # SA Thermal device
-		device pci 05.0 off end # IPU
-		device pci 08.0 on  end # GNA
-		device pci 09.0 off end # Intel Trace Hub
-		device pci 12.6 off end # GSPI 2
-		device pci 14.0 on
+		end
+		device ref gna on end
+		device ref south_xhci on
 			chip drivers/usb/acpi
 				register "desc" = ""Root Hub""
 				register "type" = "UPC_TYPE_HUB"
-				device usb 0.0 on
+				device ref xhci_root_hub on
 					chip drivers/usb/acpi
 						register "desc" = ""Left Type-C Port""
 						register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
 						register "group" = "ACPI_PLD_GROUP(1, 1)"
-						device usb 2.0 on end
+						device ref usb2_port1 on end
 					end
 					chip drivers/usb/acpi
 						register "desc" = ""Right Type-C Port""
 						register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
 						register "group" = "ACPI_PLD_GROUP(2, 1)"
-						device usb 2.1 on end
+						device ref usb2_port2 on end
 					end
 					chip drivers/usb/acpi
 						register "desc" = ""Left Type-A Port""
 						register "type" = "UPC_TYPE_A"
 						register "group" = "ACPI_PLD_GROUP(1, 2)"
-						device usb 2.2 on end
+						device ref usb2_port3 on end
 					end
 					chip drivers/usb/acpi
 						register "desc" = ""Right Type-A Port""
 						register "type" = "UPC_TYPE_A"
 						register "group" = "ACPI_PLD_GROUP(2, 2)"
-						device usb 2.3 on end
-					end
-					chip drivers/usb/acpi
-						device usb 2.4 off end
-					end
-					chip drivers/usb/acpi
-						device usb 2.5 off end
-					end
-					chip drivers/usb/acpi
-						device usb 2.6 off end
+						device ref usb2_port4 on end
 					end
 					chip drivers/usb/acpi
 						register "desc" = ""Bluetooth""
 						register "type" = "UPC_TYPE_INTERNAL"
 						register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_H19)"
-						device usb 2.7 on end
+						device ref usb2_port8 on end
 					end
 					chip drivers/usb/acpi
 						register "desc" = ""Left Type-C Port""
 						register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
 						register "group" = "ACPI_PLD_GROUP(1, 1)"
-						device usb 3.0 on end
+						device ref usb3_port1 on end
 					end
 					chip drivers/usb/acpi
 						register "desc" = ""Right Type-C Port""
 						register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
 						register "group" = "ACPI_PLD_GROUP(2, 1)"
-						device usb 3.1 on end
+						device ref usb3_port2 on end
 					end
 					chip drivers/usb/acpi
 						register "desc" = ""Left Type-A Port""
 						register "type" = "UPC_TYPE_USB3_A"
 						register "group" = "ACPI_PLD_GROUP(1, 2)"
-						device usb 3.2 on end
+						device ref usb3_port3 on end
 					end
 					chip drivers/usb/acpi
 						register "desc" = ""Right Type-A Port""
 						register "type" = "UPC_TYPE_USB3_A"
 						register "group" = "ACPI_PLD_GROUP(2, 2)"
-						device usb 3.3 on end
+						device ref usb3_port4 on end
 					end
 				end
 			end
-		end # USB xHCI
-		device pci 14.1 off end # USB xDCI (OTG)
-		device pci 14.2 on  end # PMC SRAM
-		device pci 14.3 on
+		end
+		device ref shared_ram on end
+		device ref cnvi_wifi on
 			chip drivers/wifi/generic
 				register "wake" = "GPE0_PME_B0"
 				device generic 0 on end
 			end
-		end # CNVi wifi
-		device pci 14.5 on  end # SDCard
-		device pci 15.0 off end # I2C 0
-		device pci 15.1 off end # I2C 1
-		device pci 15.2 off end # I2C 2
-		device pci 15.3 off end # I2C 3
-		device pci 16.0 on  end # HECI 1
-		device pci 16.1 off end # HECI 2
-		device pci 16.4 off end # HECI 3
-		device pci 16.5 off end # HECI 4
-		device pci 17.0 off end # SATA
-		device pci 19.0 off end # I2C 4
-		device pci 19.1 off end # I2C 5
-		device pci 19.2 on  end # UART 2
-		device pci 1a.0 on  end # eMMC
-		device pci 1c.0 off end # PCI Express Root Port 1
-		device pci 1c.1 off end # PCI Express Root Port 2
-		device pci 1c.2 off end # PCI Express Root Port 3
-		device pci 1c.3 off end # PCI Express Root Port 4
-		device pci 1c.4 off end # PCI Express Root Port 5
-		device pci 1c.5 off end # PCI Express Root Port 6
-		device pci 1c.6 off end # PCI Express Root Port 7
-		# External PCIe port 4 is mapped to PCIe Root port 8
-		device pci 1c.7 off end # PCI Express Root Port 8 - hosts M.2 E-key WLAN
-		device pci 1e.0 off end # UART 0
-		device pci 1e.1 off end # UART 1
-		device pci 1e.2 on
+		end
+		device ref sdxc on end
+		device ref heci1 on end
+		device ref i2c4 on end
+		device ref uart2 on end
+		device ref emmc on end
+		device ref gspi0 on
 			chip drivers/spi/acpi
 				register "hid" = "ACPI_DT_NAMESPACE_HID"
 				register "compat_string" = ""google,cr50""
 				register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_B4_IRQ)"
 				device spi 0 on end
 			end
-		end # GSPI 0
-		device pci 1e.3 off end # GSPI 1
-		device pci 1f.0 on
+		end
+		device ref pch_espi on
 			chip ec/google/chromeec
 				device pnp 0c09.0 on end
 			end
-		end # eSPI Interface
-		device pci 1f.1 on  end # P2SB
-		device pci 1f.2 hidden end # Power Management Controller
-		device pci 1f.3 on
+		end
+		device ref hda on
 			chip drivers/sof
 				register "spkr_tplg" = "rt1015"
 				register "jack_tplg" = "rt5682"
@@ -427,9 +390,6 @@ chip soc/intel/jasperlake
 					probe AUDIO_AMP MAX98360
 				end
 			end
-		end # Intel HDA/cAVS
-		device pci 1f.4 off end # SMBus
-		device pci 1f.5 on  end # PCH SPI
-		device pci 1f.7 off end # Intel Trace Hub
+		end
 	end
 end
diff --git a/src/mainboard/google/dedede/variants/beadrix/overridetree.cb b/src/mainboard/google/dedede/variants/beadrix/overridetree.cb
index cba95da235..a1c95148ba 100644
--- a/src/mainboard/google/dedede/variants/beadrix/overridetree.cb
+++ b/src/mainboard/google/dedede/variants/beadrix/overridetree.cb
@@ -60,7 +60,7 @@ chip soc/intel/jasperlake
 	register "SerialIoI2cMode[PchSerialIoIndexI2C5]" = "PchSerialIoPci"
 
 	device domain 0 on
-		device pci 04.0 on
+		device ref dptf on
 			# Default DPTF Policy for all Dedede boards if not overridden
 			chip drivers/intel/dptf
 				register "options.tsr[0].desc" = ""Memory""
@@ -100,10 +100,10 @@ chip soc/intel/jasperlake
 				device generic 0 on end
 			end
 		end
-		device pci 05.0 off end # IPU - MIPI Camera
-		device pci 14.0 on
+		device ref ipu off end
+		device ref south_xhci on
 			chip drivers/usb/acpi
-				device usb 0.0 on
+				device ref xhci_root_hub on
 					chip drivers/usb/acpi
 						register "desc" = ""Right Type-C Port""
 						register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
@@ -117,7 +117,7 @@ chip soc/intel/jasperlake
 						register "desc" = ""Right Type-C Port""
 						register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
 						register "group" = "ACPI_PLD_GROUP(2, 1)"
-						device usb 3.1 on
+						device ref usb3_port2 on
 							probe DB_PORTS DB_PORTS_1C_LTE
 							probe DB_PORTS DB_PORTS_1C
 						end
@@ -135,15 +135,15 @@ chip soc/intel/jasperlake
 						register "reset_off_delay_ms" = "20"
 						register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A10)"
 						register "enable_delay_ms" = "20"
-						device usb 3.3 on
+						device ref usb3_port4 on
 							probe DB_PORTS DB_PORTS_1C_LTE
 							probe DB_PORTS DB_PORTS_LTE
 						end
 					end
 				end
 			end
-		end # USB xHCI
-		device pci 15.0 on
+		end
+		device ref i2c0 on
 			chip drivers/i2c/hid
 				register "generic.hid" = ""PIXA2635""
 				register "generic.desc" = ""PIXA Touchpad""
@@ -153,8 +153,8 @@ chip soc/intel/jasperlake
 				register "hid_desc_reg_offset" = "0x01"
 				device i2c 15 on end
 			end
-		end # I2C 0
-		device pci 19.0 on
+		end
+		device ref i2c4 on
 			chip drivers/i2c/generic
 				register "hid" = ""10EC5682""
 				register "name" = ""RT58""
@@ -182,8 +182,8 @@ chip soc/intel/jasperlake
 					probe AUDIO_CODEC_SOURCE AUDIO_CODEC_ALC5682I_VS
 				end
 			end
-		end # I2C 4
-		device pci 19.1 on
+		end
+		device ref i2c5 on
 			chip drivers/i2c/sx9324
 				register "desc" = ""SAR Proximity Sensor""
 				register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_E11_IRQ)"
@@ -239,13 +239,13 @@ chip soc/intel/jasperlake
 					probe DB_PORTS DB_PORTS_LTE
 				end
 			end
-		end # I2C 5
-		device pci 1f.3 on
+		end
+		device ref hda on
 			chip drivers/generic/max98357a
 				register "hid" = ""MX98360A""
 				register "sdmode_gpio" =  "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D17)"
 				device generic 0 on end
 			end
-		end # Intel HDA
+		end
 	end
 end
diff --git a/src/mainboard/google/dedede/variants/blipper/overridetree.cb b/src/mainboard/google/dedede/variants/blipper/overridetree.cb
index db0bdc2049..535c0f6934 100644
--- a/src/mainboard/google/dedede/variants/blipper/overridetree.cb
+++ b/src/mainboard/google/dedede/variants/blipper/overridetree.cb
@@ -63,7 +63,7 @@ chip soc/intel/jasperlake
 	register "FastPkgCRampDisable" = "1"
 
 	device domain 0 on
-		device pci 04.0 on
+		device ref dptf on
 			chip drivers/intel/dptf
 				## Passive Policy
 				register "policies.passive" = "{
@@ -89,19 +89,19 @@ chip soc/intel/jasperlake
 						.granularity = 1000,}"
 				device generic 0 on end
 			end
-		end # SA Thermal device
-		device pci 14.0 on
+		end
+		device ref south_xhci on
 			chip drivers/usb/acpi
-				device usb 0.0 on
+				device ref xhci_root_hub on
 					chip drivers/usb/acpi
 						register "desc" = ""UFCamera""
 						register "type" = "UPC_TYPE_INTERNAL"
-						device usb 2.5 on end
+						device ref usb2_port6 on end
 					end
 				end
 			end
-		end # USB xHCI
-		device pci 15.0 on
+		end
+		device ref i2c0 on
 			chip drivers/i2c/generic
 				register "hid" = ""ELAN0000""
 				register "desc" = ""ELAN Touchpad""
@@ -120,8 +120,8 @@ chip soc/intel/jasperlake
 				register "hid_desc_reg_offset" = "0x20"
 				device i2c 0x2c on end
 			end
-		end # I2C 0
-		device pci 15.2 on
+		end
+		device ref i2c2 on
 			chip drivers/i2c/hid
 				register "generic.hid" = ""GTCH7503""
 				register "generic.desc" = ""G2 Touchscreen""
@@ -157,8 +157,8 @@ chip soc/intel/jasperlake
 				register "has_power_resource" = "true"
 				device i2c 10 on end
 			end
-		end # I2C 2
-		device pci 19.0 on
+		end
+		device ref i2c4 on
 			chip drivers/i2c/generic
 				register "hid" = ""10EC5682""
 				register "name" = ""RT58""
@@ -186,12 +186,12 @@ chip soc/intel/jasperlake
 					probe AUDIO_CODEC_SOURCE AUDIO_CODEC_ALC5682I_VS
 				end
 			end
-		end # I2C 4
-		device pci 1f.3 on
+		end
+		device ref hda on
 			chip drivers/generic/alc1015
 				register "sdb" =  "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D17)"
 				device generic 0 on end
 			end
-		end # Intel HDA
+		end
 	end
 end
diff --git a/src/mainboard/google/dedede/variants/boten/overridetree.cb b/src/mainboard/google/dedede/variants/boten/overridetree.cb
index a1c33fa809..5e3614c0b4 100644
--- a/src/mainboard/google/dedede/variants/boten/overridetree.cb
+++ b/src/mainboard/google/dedede/variants/boten/overridetree.cb
@@ -89,7 +89,7 @@ chip soc/intel/jasperlake
 	register "xhci_lfps_sampling_offtime_ms" = "0"
 
 	device domain 0 on
-		device pci 04.0 on
+		device ref dptf on
 			chip drivers/intel/dptf
 				## Passive Policy
 				register "policies.passive" = "{
@@ -136,17 +136,17 @@ chip soc/intel/jasperlake
 
 				device generic 0 on end
 			end
-		end # SA Thermal device
-		device pci 14.0 on
+		end
+		device ref south_xhci on
 			chip drivers/usb/acpi
 				register "desc" = ""Root Hub""
 				register "type" = "UPC_TYPE_HUB"
-				device usb 0.0 on
+				device ref xhci_root_hub on
 					chip drivers/usb/acpi
 						register "desc" = ""Right Type-A Port""
 						register "type" = "UPC_TYPE_A"
 						register "group" = "ACPI_PLD_GROUP(2, 1)"
-						device usb 2.1 on end
+						device ref usb2_port2 on end
 					end
 					chip drivers/usb/acpi
 						register "desc" = ""LTE""
@@ -156,33 +156,33 @@ chip soc/intel/jasperlake
 						register "reset_off_delay_ms" = "10"
 						register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A10)"
 						register "enable_delay_ms" = "20"
-						device usb 2.3 on end
+						device ref usb2_port4 on end
 					end
 					chip drivers/usb/acpi
 						register "desc" = ""UFCamera""
 						register "type" = "UPC_TYPE_INTERNAL"
-						device usb 2.5 on end
+						device ref usb2_port6 on end
 					end
 					chip drivers/usb/acpi
 						register "desc" = ""WFCamera""
 						register "type" = "UPC_TYPE_INTERNAL"
-						device usb 2.6 on end
+						device ref usb2_port7 on end
 					end
 					chip drivers/usb/acpi
 						register "desc" = ""Right Type-A Port""
 						register "type" = "UPC_TYPE_USB3_A"
 						register "group" = "ACPI_PLD_GROUP(2, 1)"
-						device usb 3.1 on end
+						device ref usb3_port2 on end
 					end
 					chip drivers/usb/acpi
 						register "desc" = ""LTE""
 						register "type" = "UPC_TYPE_INTERNAL"
-						device usb 3.3 on end
+						device ref usb3_port4 on end
 					end
 				end
 			end
-		end # USB xHCI
-		device pci 15.0 on
+		end
+		device ref i2c0 on
 			chip drivers/i2c/generic
 				register "hid" = ""ELAN0000""
 				register "desc" = ""ELAN Touchpad""
@@ -201,8 +201,8 @@ chip soc/intel/jasperlake
 				register "hid_desc_reg_offset" = "0x20"
 				device i2c 0x2c on end
 			end
-		end # I2C 0
-		device pci 15.2 on
+		end
+		device ref i2c2 on
 			chip drivers/generic/gpio_keys
 				register "name" = ""PENH""
 				register "gpio" = "ACPI_GPIO_INPUT_ACTIVE_LOW(GPP_C12)"
@@ -254,8 +254,8 @@ chip soc/intel/jasperlake
 				register "hid_desc_reg_offset" = "0x01"
 				device i2c 10 on end
 			end
-		end # I2C 2
-		device pci 19.0 on
+		end
+		device ref i2c4 on
 			chip drivers/i2c/generic
 				register "hid" = ""10EC5682""
 				register "name" = ""RT58""
@@ -301,8 +301,8 @@ chip soc/intel/jasperlake
 					probe AUDIO_AMP UNPROVISIONED
 				end
 			end
-		end # I2C 4
-		device pci 19.1 on
+		end
+		device ref i2c5 on
 			chip drivers/i2c/sx9324
 				register "desc" = ""SAR Proximity Sensor""
 				register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_E11_IRQ)"
@@ -355,14 +355,14 @@ chip soc/intel/jasperlake
 				register "reg_irq_cfg2" = "0x00"
 				device i2c 28 on end
 			end
-		end # I2C 5
-		device pci 1f.3 on
+		end
+		device ref hda on
 			chip drivers/generic/alc1015
 				register "sdb" =  "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D17)"
 				device generic 0 on
 					probe AUDIO_AMP RT1015P_AUTO
 				end
 			end
-		end # Intel HDA
+		end
 	end
 end
diff --git a/src/mainboard/google/dedede/variants/boxy/overridetree.cb b/src/mainboard/google/dedede/variants/boxy/overridetree.cb
index 11c7ae399e..f3fb01df4b 100644
--- a/src/mainboard/google/dedede/variants/boxy/overridetree.cb
+++ b/src/mainboard/google/dedede/variants/boxy/overridetree.cb
@@ -90,7 +90,7 @@ chip soc/intel/jasperlake
 					      USB_PORT_WAKE_ENABLE(4)"
 
 	device domain 0 on
-		device pci 04.0 on
+		device ref dptf on
 			chip drivers/intel/dptf
 				## Passive Policy
 				register "policies.passive" = "{
@@ -139,62 +139,62 @@ chip soc/intel/jasperlake
 
 				device generic 0 on end
 			end
-		end # SA Thermal device
-		device pci 14.0 on
+		end
+		device ref south_xhci on
 			chip drivers/usb/acpi
-				device usb 0.0 on
+				device ref xhci_root_hub on
 					chip drivers/usb/acpi
 						register "desc" = ""USB2 Type-C Port C0""
 						register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
 						register "group" = "ACPI_PLD_GROUP(1, 1)"
-						device usb 2.0 on end
+						device ref usb2_port1 on end
 					end
 					chip drivers/usb/acpi
 						register "desc" = ""USB2 Type-A Port A0""
 						register "type" = "UPC_TYPE_A"
 						register "group" = "ACPI_PLD_GROUP(1, 3)"
-						device usb 2.1 on end
+						device ref usb2_port2 on end
 					end
 					chip drivers/usb/acpi
 						register "desc" = ""USB2 Type-A Port A1""
 						register "type" = "UPC_TYPE_A"
 						register "group" = "ACPI_PLD_GROUP(1, 2)"
-						device usb 2.2 on end
+						device ref usb2_port3 on end
 					end
 					chip drivers/usb/acpi
 						register "desc" = ""USB2 Type-C Port C1""
 						register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
 						register "group" = "ACPI_PLD_GROUP(2, 1)"
-						device usb 2.3 on end
+						device ref usb2_port4 on end
 					end
 					chip drivers/usb/acpi
 						register "desc" = ""USB3 Type-C Port C0""
 						register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
 						register "group" = "ACPI_PLD_GROUP(1, 1)"
-						device usb 3.0 on end
+						device ref usb3_port1 on end
 					end
 					chip drivers/usb/acpi
 						register "desc" = ""USB3 Type-C Port C1""
 						register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
 						register "group" = "ACPI_PLD_GROUP(2, 1)"
-						device usb 3.1 on end
+						device ref usb3_port2 on end
 					end
 					chip drivers/usb/acpi
 						register "desc" = ""USB3 Type-A Port A0""
 						register "type" = "UPC_TYPE_USB3_A"
 						register "group" = "ACPI_PLD_GROUP(1, 3)"
-						device usb 3.2 on end
+						device ref usb3_port3 on end
 					end
 					chip drivers/usb/acpi
 						register "desc" = ""USB3 Type-A Port A1""
 						register "type" = "UPC_TYPE_USB3_A"
 						register "group" = "ACPI_PLD_GROUP(1, 2)"
-						device usb 3.3 on end
+						device ref usb3_port4 on end
 					end
 				end
 			end
-		end # USB xHCI
-		device pci 19.0 on
+		end
+		device ref i2c4 on
 			chip drivers/i2c/generic
 				register "hid" = ""10EC5682""
 				register "name" = ""RT58""
@@ -221,8 +221,8 @@ chip soc/intel/jasperlake
 					probe AUDIO_CODEC_SOURCE AUDIO_CODEC_ALC5682I_VS
 				end
 			end
-		end # I2C 4
-		device pci 1c.2 on
+		end
+		device ref pcie_rp3 on
 			chip drivers/net
 				register "customized_leds" = "0x07af"
 				register "wake" = "GPE0_DW0_03" # GPP_B3
@@ -230,14 +230,13 @@ chip soc/intel/jasperlake
 				register "device_index" = "0"
 				device pci 00.0 on end
 			end
-		end # PCI Express Root Port 3 - RTL8111H LAN
-		device pci 1c.6 on
+		end
+		device ref pcie_rp7 on
 			chip drivers/wifi/generic
 				register "wake" = "GPE0_DW2_03"
 				device pci 00.0 on  end
 			end
-		end # PCI Express Root Port 7 - WLAN
-		device pci 1c.7 off end # PCI Express Root Port 8
-		device pci 1f.3 on end # Intel HDA
+		end
+		device ref hda on end
 	end
 end
diff --git a/src/mainboard/google/dedede/variants/bugzzy/overridetree.cb b/src/mainboard/google/dedede/variants/bugzzy/overridetree.cb
index a1303d7a4f..441707e940 100644
--- a/src/mainboard/google/dedede/variants/bugzzy/overridetree.cb
+++ b/src/mainboard/google/dedede/variants/bugzzy/overridetree.cb
@@ -94,7 +94,7 @@ chip soc/intel/jasperlake
 	register "SerialIoI2cMode[PchSerialIoIndexI2C4]" = "PchSerialIoPci"
 
 	device domain 0 on
-		device pci 04.0 on
+		device ref dptf on
 			chip drivers/intel/dptf
 				register "options.tsr[0].desc" = ""Memory""
 				register "options.tsr[1].desc" = ""CPU""
@@ -138,8 +138,8 @@ chip soc/intel/jasperlake
 				}"
 				device generic 0 on end
 			end
-		end # SA Thermal device
-		device pci 05.0 on # IPU - MIPI Camera
+		end
+		device ref ipu on
 			chip drivers/intel/mipi_camera
 				register "acpi_uid" = "0x50000"
 				register "acpi_name" = ""IPU0""
@@ -153,16 +153,16 @@ chip soc/intel/jasperlake
 				device generic 0 on end
 			end
 		end
-		device pci 14.0 on
+		device ref south_xhci on
 			chip drivers/usb/acpi
-				device usb 0.0 on
+				device ref xhci_root_hub on
 					chip drivers/usb/acpi
 						register "desc" = ""UFCamera""
 						register "type" = "UPC_TYPE_INTERNAL"
 						register "has_power_resource" = "true"
 						register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D13)"
 						register "enable_delay_ms" = "20"
-						device usb 2.5 on end
+						device ref usb2_port6 on end
 					end
 					chip drivers/usb/acpi
 						register "desc" = ""LTE""
@@ -172,14 +172,14 @@ chip soc/intel/jasperlake
 						register "reset_off_delay_ms" = "20"
 						register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A10)"
 						register "enable_delay_ms" = "20"
-						device usb 3.3 on
+						device ref usb3_port4 on
 							probe DB_PORTS DB_PORTS_1C_1A_LTE
 						end
 					end
 				end
 			end
-		end # USB xHCI
-		device pci 15.0 on
+		end
+		device ref i2c0 on
 			chip drivers/i2c/generic
 				register "hid" = ""ELAN0000""
 				register "desc" = ""ELAN Touchpad""
@@ -197,8 +197,8 @@ chip soc/intel/jasperlake
 				register "hid_desc_reg_offset" = "0xE"
 				device i2c 40 on end
 			end
-		end # I2C 0
-		device pci 15.1 on
+		end
+		device ref i2c1 on
 			chip drivers/i2c/hid
 				register "generic.hid" = ""WCOM014B""
 				register "generic.desc" = ""WCOM Digitizer""
@@ -222,8 +222,8 @@ chip soc/intel/jasperlake
 					probe DB_PORTS DB_PORTS_1C_1A_LTE
 				end
 			end
-		end # I2C #1
-		device pci 15.2 on
+		end
+		device ref i2c2 on
 			chip drivers/i2c/hid
 				register "generic.hid" = ""HX121A""
 				register "generic.desc" = ""HX Touchscreen""
@@ -236,8 +236,8 @@ chip soc/intel/jasperlake
 				register "hid_desc_reg_offset" = "0x1"
 				device i2c 0x4F on end
 			end
-		end # I2C #2
-		device pci 15.3 on
+		end
+		device ref i2c3 on
 			chip drivers/intel/mipi_camera
 				register "acpi_hid" = ""OVTI8856""
 				register "acpi_uid" = "0"
@@ -310,9 +310,8 @@ chip soc/intel/jasperlake
 
 				device i2c 50 on end
 			end
-		end # I2C 3
-		device pci 1c.7 off end # PCI Express Root Port 8
-		device pci 19.0 on
+		end
+		device ref i2c4 on
 			chip drivers/i2c/da7219
 				register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_D16)"
 				register "btn_cfg" = "50"
@@ -330,13 +329,13 @@ chip soc/intel/jasperlake
 				register "mic_amp_in_sel" = ""diff""
 				device i2c 1a on end
 			end
-		end #I2C 4
-		device pci 1f.3 on
+		end
+		device ref hda on
 			chip drivers/generic/max98357a
 				register "hid" = ""MX98360A""
 				register "sdmode_gpio" =  "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D17)"
 				device generic 0 on end
 			end
-		end # Intel HDA
+		end
 	end
 end
diff --git a/src/mainboard/google/dedede/variants/cappy2/overridetree.cb b/src/mainboard/google/dedede/variants/cappy2/overridetree.cb
index 2b361a3d93..59c7f9fd1c 100644
--- a/src/mainboard/google/dedede/variants/cappy2/overridetree.cb
+++ b/src/mainboard/google/dedede/variants/cappy2/overridetree.cb
@@ -77,7 +77,7 @@ chip soc/intel/jasperlake
 	}" # Camera
 
 	device domain 0 on
-		device pci 04.0 on
+		device ref dptf on
 			chip drivers/intel/dptf
 				## Passive Policy
 				register "policies.passive" = "{
@@ -112,22 +112,22 @@ chip soc/intel/jasperlake
 				}"
 				device generic 0 on end
 			end
-		end # SA Thermal device
-		device pci 14.0 on
+		end
+		device ref south_xhci on
 			chip drivers/usb/acpi
-				device usb 0.0 on
+				device ref xhci_root_hub on
 					chip drivers/usb/acpi
 						register "desc" = ""UFCamera""
 						register "type" = "UPC_TYPE_INTERNAL"
 						register "has_power_resource" = "true"
 						register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D15)"
 						register "enable_delay_ms" = "20"
-						device usb 2.5 on end
+						device ref usb2_port6 on end
 					end
 				end
 			end
-		end # USB xHCI
-		device pci 15.0 on
+		end
+		device ref i2c0 on
 			chip drivers/i2c/hid
 				register "generic.hid" = ""SYNA0A00""
 				register "generic.desc" = ""SYNA Touchpad""
@@ -172,8 +172,8 @@ chip soc/intel/jasperlake
 				register "detect" = "1"
 				device i2c 15 on end
 			end
-		end #I2C 0
-		device pci 19.0 on
+		end
+		device ref i2c4 on
 			chip drivers/i2c/generic
 				register "hid" = ""10EC5682""
 				register "name" = ""RT58""
@@ -219,13 +219,13 @@ chip soc/intel/jasperlake
 					probe AUDIO_CODEC_SOURCE AUDIO_CODEC_CS42l42
 				end
  			end
-		end #I2C 4
-		device pci 1f.0 on
+		end
+		device ref pch_espi on
 			chip drivers/pc80/tpm
 				device pnp 0c31.0 on end # Discrete TPM
-			end # chip drivers/pc80/tpm
-		end # PCH eSPI
-		device pci 1f.3 on
+			end
+		end
+		device ref hda on
 		       chip drivers/generic/alc1015
 				register "sdb" =  "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D17)"
 				device generic 0 on
@@ -239,6 +239,6 @@ chip soc/intel/jasperlake
 					probe AUDIO_AMP MAX98360
 				end
 			end
-		end # Intel HDA
+		end
 	end
 end
diff --git a/src/mainboard/google/dedede/variants/corori/overridetree.cb b/src/mainboard/google/dedede/variants/corori/overridetree.cb
index 59afb06e93..76aadb44dd 100644
--- a/src/mainboard/google/dedede/variants/corori/overridetree.cb
+++ b/src/mainboard/google/dedede/variants/corori/overridetree.cb
@@ -44,7 +44,7 @@ chip soc/intel/jasperlake
 	register "SerialIoGSpiCsMode[PchSerialIoIndexGSPI0]" = "0"
 
 	device domain 0 on
-		device pci 04.0 on
+		device ref dptf on
 			chip drivers/intel/dptf
 				## Passive Policy
 				register "policies.passive" = "{
@@ -79,31 +79,19 @@ chip soc/intel/jasperlake
 				}"
 				device generic 0 on end
 			end
-		end # SA Thermal device
-		device pci 14.0 on
+		end
+		device ref south_xhci on
 			chip drivers/usb/acpi
-				device usb 0.0 on
-					chip drivers/usb/acpi
-						device usb 2.1 off end
-					end
-					chip drivers/usb/acpi
-						device usb 2.3 off end
-					end
+				device ref xhci_root_hub on
 					chip drivers/usb/acpi
 						register "desc" = ""Camera (UFC)""
 						register "type" = "UPC_TYPE_INTERNAL"
-						device usb 2.5 on end
-					end
-					chip drivers/usb/acpi
-						device usb 3.1 off end
-					end
-					chip drivers/usb/acpi
-						device usb 3.3 off end
+						device ref usb2_port6 on end
 					end
 				end
 			end
-		end # USB xHCI
-		device pci 15.0 on
+		end
+		device ref i2c0 on
 			chip drivers/i2c/generic
 				register "hid" = ""ELAN0000""
 				register "desc" = ""ELAN Touchpad""
@@ -112,8 +100,8 @@ chip soc/intel/jasperlake
 				register "detect" = "1"
 				device i2c 15 on end
 			end
-		end #I2C 0
-		device pci 19.0 on
+		end
+		device ref i2c4 on
 			chip drivers/i2c/generic
 				register "hid" = ""10EC5682""
 				register "name" = ""RT58""
@@ -143,19 +131,18 @@ chip soc/intel/jasperlake
 					probe AUDIO_CODEC_SOURCE AUDIO_CODEC_ALC5682I_VS
 				end
 			end
-		end #I2C 4
-		device pci 1e.2 off end # GSPI 0
-		device pci 1f.0 on
+		end
+		device ref pch_espi on
 			chip drivers/pc80/tpm
 				device pnp 0c31.0 on end # Discrete TPM
 			end # chip drivers/pc80/tpm
-		end # PCH eSPI
-		device pci 1f.3 on
+		end
+		device ref hda on
 			chip drivers/generic/max98357a
 				register "hid" = ""MX98360A""
 				register "sdmode_gpio" =  "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D17)"
 				device generic 0 on end
 			end
-		end # Intel HDA
+		end
 	end
 end
diff --git a/src/mainboard/google/dedede/variants/cret/overridetree.cb b/src/mainboard/google/dedede/variants/cret/overridetree.cb
index f1a00ffb20..aaf7321b90 100644
--- a/src/mainboard/google/dedede/variants/cret/overridetree.cb
+++ b/src/mainboard/google/dedede/variants/cret/overridetree.cb
@@ -52,7 +52,7 @@ chip soc/intel/jasperlake
 		},
 	}"
 	device domain 0 on
-		device pci 04.0 on
+		device ref dptf on
 			chip drivers/intel/dptf
 				## Passive Policy
 				register "policies.passive" = "{
@@ -87,32 +87,26 @@ chip soc/intel/jasperlake
 				}"
 				device generic 0 on end
 			end
-		end # SA Thermal device
-		device pci 14.0 on
+		end
+		device ref south_xhci on
 			chip drivers/usb/acpi
-				device usb 0.0 on
-					chip drivers/usb/acpi
-						device usb 2.1 off end
-					end
+				device ref xhci_root_hub on
 					chip drivers/usb/acpi
 						register "desc" = ""LTE""
 						register "type" = "UPC_TYPE_INTERNAL"
-						device usb 2.3 on
+						device ref usb2_port4 on
 							probe LTE LTE_PRESENT
 						end
 					end
 					chip drivers/usb/acpi
 						register "desc" = ""Camera (UFC)""
 						register "type" = "UPC_TYPE_INTERNAL"
-						device usb 2.5 on end
+						device ref usb2_port6 on end
 					end
 					chip drivers/usb/acpi
 						register "desc" = ""Camera (WFC)""
 						register "type" = "UPC_TYPE_INTERNAL"
-						device usb 2.6 on end
-					end
-					chip drivers/usb/acpi
-						device usb 3.1 off end
+						device ref usb2_port7 on end
 					end
 					chip drivers/usb/acpi
 						register "desc" = ""LTE""
@@ -124,14 +118,14 @@ chip soc/intel/jasperlake
 						register "enable_gpio" =
 							"ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A10)"
 						register "enable_delay_ms" = "20"
-						device usb 3.3 on
+						device ref usb3_port4 on
 							probe LTE LTE_PRESENT
 						end
 					end
 				end
 			end
-		end # USB xHCI
-		device pci 15.0 on
+		end
+		device ref i2c0 on
 			chip drivers/i2c/generic
 				register "hid" = ""ELAN0000""
 				register "desc" = ""ELAN Touchpad""
@@ -149,8 +143,8 @@ chip soc/intel/jasperlake
 				register "hid_desc_reg_offset" = "0x20"
 				device i2c 2c on end
 			end
-		end #I2C 0
-		device pci 15.2 on
+		end
+		device ref i2c2 on
 			chip drivers/i2c/hid
 				register "generic.hid" = ""WDHT0002""
 				register "generic.desc" = ""WDT Touchscreen""
@@ -239,9 +233,9 @@ chip soc/intel/jasperlake
 				register "hid_desc_reg_offset" = "0x01"
 				device i2c 40 on end
 			end
-		end # I2C 2
-		device pci 1c.7 on end
-		device pci 19.0 on
+		end
+		device ref pcie_rp8 on end
+		device ref i2c4 on
 			chip drivers/i2c/da7219
 				register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_D16)"
 				register "btn_cfg" = "50"
@@ -280,13 +274,13 @@ chip soc/intel/jasperlake
 					probe AUDIO_CODEC_SOURCE AUDIO_CODEC_CS42l42
 				end
 			end
-		end #I2C 4
-		device pci 1f.3 on
+		end
+		device ref hda on
 			chip drivers/generic/max98357a
 				register "hid" = ""MX98360A""
 				register "sdmode_gpio" =  "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D17)"
 				device generic 0 on end
 			end
-		end # Intel HDA
+		end
 	end
 end
diff --git a/src/mainboard/google/dedede/variants/dexi/overridetree.cb b/src/mainboard/google/dedede/variants/dexi/overridetree.cb
index 38a2d520a8..54910d5f4c 100644
--- a/src/mainboard/google/dedede/variants/dexi/overridetree.cb
+++ b/src/mainboard/google/dedede/variants/dexi/overridetree.cb
@@ -135,7 +135,7 @@ chip soc/intel/jasperlake
 					      USB_PORT_WAKE_ENABLE(6)"
 
 	device domain 0 on
-		device pci 04.0 on
+		device ref dptf on
 			chip drivers/intel/dptf
 				## Passive Policy
 				register "policies.passive" = "{
@@ -184,86 +184,86 @@ chip soc/intel/jasperlake
 
 				device generic 0 on end
 			end
-		end # SA Thermal device
-		device pci 14.0 on
+		end
+		device ref south_xhci on
 			chip drivers/usb/acpi
-				device usb 0.0 on
+				device ref xhci_root_hub on
 					chip drivers/usb/acpi
 						register "desc" = ""USB2 Type-C Port C0""
 						register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
 						register "group" = "ACPI_PLD_GROUP(2, 1)"
-						device usb 2.0 on end
+						device ref usb2_port1 on end
 					end
 					chip drivers/usb/acpi
 						register "desc" = ""USB2 Type-A Port A0""
 						register "type" = "UPC_TYPE_A"
 						register "group" = "ACPI_PLD_GROUP(2, 2)"
-						device usb 2.1 on end
+						device ref usb2_port2 on end
 					end
 					chip drivers/usb/acpi
 						register "desc" = ""USB2 Type-A Port A1""
 						register "type" = "UPC_TYPE_A"
 						register "group" = "ACPI_PLD_GROUP(2, 3)"
-						device usb 2.2 on end
+						device ref usb2_port3 on end
 					end
 					chip drivers/usb/acpi
 						register "desc" = ""USB2 Type-A Port A2""
 						register "type" = "UPC_TYPE_A"
 						register "group" = "ACPI_PLD_GROUP(1, 3)"
-						device usb 2.3 on end
+						device ref usb2_port4 on end
 					end
 					chip drivers/usb/acpi
 						register "desc" = ""USB2 Type-A Port A3""
 						register "type" = "UPC_TYPE_A"
 						register "group" = "ACPI_PLD_GROUP(1, 2)"
-						device usb 2.4 on end
+						device ref usb2_port5 on end
 					end
 					chip drivers/usb/acpi
 						register "desc" = ""USB2 Type-A Port A4""
 						register "type" = "UPC_TYPE_A"
 						register "group" = "ACPI_PLD_GROUP(1, 1)"
-						device usb 2.6 on end
+						device ref usb2_port7 on end
 					end
 					chip drivers/usb/acpi
 						register "desc" = ""USB3 Type-C Port C0""
 						register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
 						register "group" = "ACPI_PLD_GROUP(2, 1)"
-						device usb 3.0 on end
+						device ref usb3_port1 on end
 					end
 					chip drivers/usb/acpi
 						register "desc" = ""USB3 Type-A Port A4""
 						register "type" = "UPC_TYPE_USB3_A"
 						register "group" = "ACPI_PLD_GROUP(1, 1)"
-						device usb 3.1 on end
+						device ref usb3_port2 on end
 					end
 					chip drivers/usb/acpi
 						register "desc" = ""USB3 Type-A Port A0""
 						register "type" = "UPC_TYPE_USB3_A"
 						register "group" = "ACPI_PLD_GROUP(2, 2)"
-						device usb 3.2 on end
+						device ref usb3_port3 on end
 					end
 					chip drivers/usb/acpi
 						register "desc" = ""USB3 Type-A Port A1""
 						register "type" = "UPC_TYPE_USB3_A"
 						register "group" = "ACPI_PLD_GROUP(2, 3)"
-						device usb 3.3 on end
+						device ref usb3_port4 on end
 					end
 					chip drivers/usb/acpi
 						register "desc" = ""USB3 Type-A Port A3""
 						register "type" = "UPC_TYPE_USB3_A"
 						register "group" = "ACPI_PLD_GROUP(1, 2)"
-						device usb 3.4 on end
+						device ref usb3_port5 on end
 					end
 					chip drivers/usb/acpi
 						register "desc" = ""USB3 Type-A Port A2""
 						register "type" = "UPC_TYPE_USB3_A"
 						register "group" = "ACPI_PLD_GROUP(1, 3)"
-						device usb 3.5 on end
+						device ref usb3_port6 on end
 					end
 				end
 			end
-		end # USB xHCI
-		device pci 19.0 on
+		end
+		device ref i2c4 on
 			chip drivers/i2c/generic
 				register "hid" = ""RTL5682""
 				register "name" = ""RT58""
@@ -275,8 +275,8 @@ chip soc/intel/jasperlake
 				register "property_list[0].integer" = "1"
 				device i2c 1a on end
 			end
-		end # I2C 4
-		device pci 1c.2 on
+		end
+		device ref pcie_rp3 on
 			chip drivers/net
 				register "customized_leds" = "0x05af"
 				register "wake" = "GPE0_DW0_03" # GPP_B3
@@ -284,14 +284,13 @@ chip soc/intel/jasperlake
 				register "device_index" = "0"
 				device pci 00.0 on end
 			end
-		end # PCI Express Root Port 3 - RTL8111H LAN
-		device pci 1c.6 on
+		end
+		device ref pcie_rp7 on
 			chip drivers/wifi/generic
 				register "wake" = "GPE0_DW2_03"
 				device pci 00.0 on  end
 			end
-		end # PCI Express Root Port 7 - WLAN
-		device pci 1c.7 off end # PCI Express Root Port 8
-		device pci 1f.3 on end # Intel HDA
+		end
+		device ref hda on end
 	end
 end
diff --git a/src/mainboard/google/dedede/variants/dibbi/overridetree.cb b/src/mainboard/google/dedede/variants/dibbi/overridetree.cb
index eb05d24c94..1c6ee0706e 100644
--- a/src/mainboard/google/dedede/variants/dibbi/overridetree.cb
+++ b/src/mainboard/google/dedede/variants/dibbi/overridetree.cb
@@ -111,7 +111,7 @@ chip soc/intel/jasperlake
 	register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC_SKIP)"	# USB3/1 Type-A Port A3
 
 	device domain 0 on
-		device pci 04.0 on
+		device ref dptf on
 			chip drivers/intel/dptf
 				## Passive Policy
 				register "policies.passive" = "{
@@ -160,77 +160,74 @@ chip soc/intel/jasperlake
 
 				device generic 0 on end
 			end
-		end # SA Thermal device
-		device pci 14.0 on
+		end
+		device ref south_xhci on
 			chip drivers/usb/acpi
-				device usb 0.0 on
+				device ref xhci_root_hub on
 					chip drivers/usb/acpi
 						register "desc" = ""USB2 Type-C Port C0""
 						register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
 						register "group" = "ACPI_PLD_GROUP(1, 1)"
-						device usb 2.0 on end
+						device ref usb2_port1 on end
 					end
 					chip drivers/usb/acpi
 						register "desc" = ""USB2 Type-A Port A0""
 						register "type" = "UPC_TYPE_A"
 						register "group" = "ACPI_PLD_GROUP(1, 2)"
-						device usb 2.1 on end
+						device ref usb2_port2 on end
 					end
 					chip drivers/usb/acpi
 						register "desc" = ""USB2 Type-A Port A1""
 						register "type" = "UPC_TYPE_A"
 						register "group" = "ACPI_PLD_GROUP(1, 3)"
-						device usb 2.2 on end
+						device ref usb2_port3 on end
 					end
 					chip drivers/usb/acpi
 						register "desc" = ""USB2 Type-A Port A2""
 						register "type" = "UPC_TYPE_A"
 						register "group" = "ACPI_PLD_GROUP(1, 4)"
-						device usb 2.3 on end
+						device ref usb2_port4 on end
 					end
 					chip drivers/usb/acpi
 						register "desc" = ""USB2 Type-A Port A3""
 						register "type" = "UPC_TYPE_A"
 						register "group" = "ACPI_PLD_GROUP(1, 5)"
-						device usb 2.4 on end
+						device ref usb2_port5 on end
 					end
 					chip drivers/usb/acpi
 						register "desc" = ""USB3 Type-C Port C0""
 						register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
 						register "group" = "ACPI_PLD_GROUP(1, 1)"
-						device usb 3.0 on end
-					end
-					chip drivers/usb/acpi
-						device usb 3.1 off end
+						device ref usb3_port1 on end
 					end
 					chip drivers/usb/acpi
 						register "desc" = ""USB3 Type-A Port A0""
 						register "type" = "UPC_TYPE_USB3_A"
 						register "group" = "ACPI_PLD_GROUP(1, 2)"
-						device usb 3.2 on end
+						device ref usb3_port3 on end
 					end
 					chip drivers/usb/acpi
 						register "desc" = ""USB3 Type-A Port A1""
 						register "type" = "UPC_TYPE_USB3_A"
 						register "group" = "ACPI_PLD_GROUP(1, 3)"
-						device usb 3.3 on end
+						device ref usb3_port4 on end
 					end
 					chip drivers/usb/acpi
 						register "desc" = ""USB3 Type-A Port A3""
 						register "type" = "UPC_TYPE_USB3_A"
 						register "group" = "ACPI_PLD_GROUP(1, 5)"
-						device usb 3.4 on end
+						device ref usb3_port5 on end
 					end
 					chip drivers/usb/acpi
 						register "desc" = ""USB3 Type-A Port A2""
 						register "type" = "UPC_TYPE_USB3_A"
 						register "group" = "ACPI_PLD_GROUP(1, 4)"
-						device usb 3.5 on end
+						device ref usb3_port6 on end
 					end
 				end
 			end
-		end # USB xHCI
-		device pci 19.0 on
+		end
+		device ref i2c4 on
 			chip drivers/i2c/generic
 				register "hid" = ""RTL5682""
 				register "name" = ""RT58""
@@ -242,8 +239,8 @@ chip soc/intel/jasperlake
 				register "property_list[0].integer" = "1"
 				device i2c 1a on end
 			end
-		end # I2C 4
-		device pci 1c.2 on
+		end
+		device ref pcie_rp3 on
 			chip drivers/net
 				register "customized_leds" = "0x05af"
 				register "wake" = "GPE0_DW0_03" # GPP_B3
@@ -251,14 +248,13 @@ chip soc/intel/jasperlake
 				register "device_index" = "0"
 				device pci 00.0 on end
 			end
-		end # PCI Express Root Port 3 - RTL8111H LAN
-		device pci 1c.6 on
+		end
+		device ref pcie_rp7 on
 			chip drivers/wifi/generic
 				register "wake" = "GPE0_DW2_03"
 				device pci 00.0 on  end
 			end
-		end # PCI Express Root Port 7 - WLAN
-		device pci 1c.7 off end # PCI Express Root Port 8
-		device pci 1f.3 on end # Intel HDA
+		end
+		device ref hda on end
 	end
 end
diff --git a/src/mainboard/google/dedede/variants/dita/overridetree.cb b/src/mainboard/google/dedede/variants/dita/overridetree.cb
index 38a2d520a8..54910d5f4c 100644
--- a/src/mainboard/google/dedede/variants/dita/overridetree.cb
+++ b/src/mainboard/google/dedede/variants/dita/overridetree.cb
@@ -135,7 +135,7 @@ chip soc/intel/jasperlake
 					      USB_PORT_WAKE_ENABLE(6)"
 
 	device domain 0 on
-		device pci 04.0 on
+		device ref dptf on
 			chip drivers/intel/dptf
 				## Passive Policy
 				register "policies.passive" = "{
@@ -184,86 +184,86 @@ chip soc/intel/jasperlake
 
 				device generic 0 on end
 			end
-		end # SA Thermal device
-		device pci 14.0 on
+		end
+		device ref south_xhci on
 			chip drivers/usb/acpi
-				device usb 0.0 on
+				device ref xhci_root_hub on
 					chip drivers/usb/acpi
 						register "desc" = ""USB2 Type-C Port C0""
 						register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
 						register "group" = "ACPI_PLD_GROUP(2, 1)"
-						device usb 2.0 on end
+						device ref usb2_port1 on end
 					end
 					chip drivers/usb/acpi
 						register "desc" = ""USB2 Type-A Port A0""
 						register "type" = "UPC_TYPE_A"
 						register "group" = "ACPI_PLD_GROUP(2, 2)"
-						device usb 2.1 on end
+						device ref usb2_port2 on end
 					end
 					chip drivers/usb/acpi
 						register "desc" = ""USB2 Type-A Port A1""
 						register "type" = "UPC_TYPE_A"
 						register "group" = "ACPI_PLD_GROUP(2, 3)"
-						device usb 2.2 on end
+						device ref usb2_port3 on end
 					end
 					chip drivers/usb/acpi
 						register "desc" = ""USB2 Type-A Port A2""
 						register "type" = "UPC_TYPE_A"
 						register "group" = "ACPI_PLD_GROUP(1, 3)"
-						device usb 2.3 on end
+						device ref usb2_port4 on end
 					end
 					chip drivers/usb/acpi
 						register "desc" = ""USB2 Type-A Port A3""
 						register "type" = "UPC_TYPE_A"
 						register "group" = "ACPI_PLD_GROUP(1, 2)"
-						device usb 2.4 on end
+						device ref usb2_port5 on end
 					end
 					chip drivers/usb/acpi
 						register "desc" = ""USB2 Type-A Port A4""
 						register "type" = "UPC_TYPE_A"
 						register "group" = "ACPI_PLD_GROUP(1, 1)"
-						device usb 2.6 on end
+						device ref usb2_port7 on end
 					end
 					chip drivers/usb/acpi
 						register "desc" = ""USB3 Type-C Port C0""
 						register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
 						register "group" = "ACPI_PLD_GROUP(2, 1)"
-						device usb 3.0 on end
+						device ref usb3_port1 on end
 					end
 					chip drivers/usb/acpi
 						register "desc" = ""USB3 Type-A Port A4""
 						register "type" = "UPC_TYPE_USB3_A"
 						register "group" = "ACPI_PLD_GROUP(1, 1)"
-						device usb 3.1 on end
+						device ref usb3_port2 on end
 					end
 					chip drivers/usb/acpi
 						register "desc" = ""USB3 Type-A Port A0""
 						register "type" = "UPC_TYPE_USB3_A"
 						register "group" = "ACPI_PLD_GROUP(2, 2)"
-						device usb 3.2 on end
+						device ref usb3_port3 on end
 					end
 					chip drivers/usb/acpi
 						register "desc" = ""USB3 Type-A Port A1""
 						register "type" = "UPC_TYPE_USB3_A"
 						register "group" = "ACPI_PLD_GROUP(2, 3)"
-						device usb 3.3 on end
+						device ref usb3_port4 on end
 					end
 					chip drivers/usb/acpi
 						register "desc" = ""USB3 Type-A Port A3""
 						register "type" = "UPC_TYPE_USB3_A"
 						register "group" = "ACPI_PLD_GROUP(1, 2)"
-						device usb 3.4 on end
+						device ref usb3_port5 on end
 					end
 					chip drivers/usb/acpi
 						register "desc" = ""USB3 Type-A Port A2""
 						register "type" = "UPC_TYPE_USB3_A"
 						register "group" = "ACPI_PLD_GROUP(1, 3)"
-						device usb 3.5 on end
+						device ref usb3_port6 on end
 					end
 				end
 			end
-		end # USB xHCI
-		device pci 19.0 on
+		end
+		device ref i2c4 on
 			chip drivers/i2c/generic
 				register "hid" = ""RTL5682""
 				register "name" = ""RT58""
@@ -275,8 +275,8 @@ chip soc/intel/jasperlake
 				register "property_list[0].integer" = "1"
 				device i2c 1a on end
 			end
-		end # I2C 4
-		device pci 1c.2 on
+		end
+		device ref pcie_rp3 on
 			chip drivers/net
 				register "customized_leds" = "0x05af"
 				register "wake" = "GPE0_DW0_03" # GPP_B3
@@ -284,14 +284,13 @@ chip soc/intel/jasperlake
 				register "device_index" = "0"
 				device pci 00.0 on end
 			end
-		end # PCI Express Root Port 3 - RTL8111H LAN
-		device pci 1c.6 on
+		end
+		device ref pcie_rp7 on
 			chip drivers/wifi/generic
 				register "wake" = "GPE0_DW2_03"
 				device pci 00.0 on  end
 			end
-		end # PCI Express Root Port 7 - WLAN
-		device pci 1c.7 off end # PCI Express Root Port 8
-		device pci 1f.3 on end # Intel HDA
+		end
+		device ref hda on end
 	end
 end
diff --git a/src/mainboard/google/dedede/variants/drawcia/overridetree.cb b/src/mainboard/google/dedede/variants/drawcia/overridetree.cb
index 12e45d9308..8e13098ccc 100644
--- a/src/mainboard/google/dedede/variants/drawcia/overridetree.cb
+++ b/src/mainboard/google/dedede/variants/drawcia/overridetree.cb
@@ -82,7 +82,7 @@ chip soc/intel/jasperlake
 	register "FastPkgCRampDisable" = "1"
 
 	device domain 0 on
-		device pci 05.0 on # IPU - MIPI Camera
+		device ref ipu on
 			chip drivers/intel/mipi_camera
 				register "acpi_uid" = "0x50000"
 				register "acpi_name" = ""IPU0""
@@ -97,7 +97,7 @@ chip soc/intel/jasperlake
 			end
 		end
 
-		device pci 04.0 on
+		device ref dptf on
 			chip drivers/intel/dptf
 				# Default DPTF Policy for all drawcia boards if not overridden
 				register "options.tsr[0].desc" = ""Memory""
@@ -150,10 +150,10 @@ chip soc/intel/jasperlake
 
 				device generic 0 on end
 			end
-		end # SA Thermal device
-		device pci 14.0 on
+		end
+		device ref south_xhci on
 			chip drivers/usb/acpi
-				device usb 0.0 on
+				device ref xhci_root_hub on
 					chip drivers/usb/acpi
 						register "desc" = ""LTE""
 						register "type" = "UPC_TYPE_INTERNAL"
@@ -163,7 +163,7 @@ chip soc/intel/jasperlake
 						register "reset_off_delay_ms" = "20"
 						register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A10)"
 						register "enable_delay_ms" = "20"
-						device usb 2.3 on
+						device ref usb2_port4 on
 							probe DB_PORTS DB_PORTS_1A_HDMI_LTE
 						end
 					end
@@ -171,7 +171,7 @@ chip soc/intel/jasperlake
 						register "desc" = ""Right Type-A Port""
 						register "type" = "UPC_TYPE_A"
 						register "group" = "ACPI_PLD_GROUP(2, 2)"
-						device usb 2.3 on
+						device ref usb2_port4 on
 							probe DB_PORTS DB_PORTS_1A_HDMI
 							probe DB_PORTS DB_PORTS_1C_1A
 						end
@@ -179,13 +179,13 @@ chip soc/intel/jasperlake
 					chip drivers/usb/acpi
 						register "desc" = ""Camera""
 						register "type" = "UPC_TYPE_INTERNAL"
-						device usb 2.5 on end
+						device ref usb2_port6 on end
 					end
 					chip drivers/usb/acpi
 						register "desc" = ""LTE""
 						register "type" = "UPC_TYPE_INTERNAL"
 						register "group" = "ACPI_PLD_GROUP(2, 2)"
-						device usb 3.3 on
+						device ref usb3_port4 on
 							probe DB_PORTS DB_PORTS_1A_HDMI_LTE
 						end
 					end
@@ -193,15 +193,15 @@ chip soc/intel/jasperlake
 						register "desc" = ""Right Type-A Port""
 						register "type" = "UPC_TYPE_USB3_A"
 						register "group" = "ACPI_PLD_GROUP(2, 2)"
-						device usb 3.3 on
+						device ref usb3_port4 on
 							probe DB_PORTS DB_PORTS_1A_HDMI
 							probe DB_PORTS DB_PORTS_1C_1A
 						end
 					end
 				end
 			end
-		end # USB xHCI
-		device pci 15.0 on
+		end
+		device ref i2c0 on
 			chip drivers/i2c/generic
 				register "hid" = ""ELAN0000""
 				register "desc" = ""ELAN Touchpad""
@@ -220,8 +220,8 @@ chip soc/intel/jasperlake
 				register "hid_desc_reg_offset" = "0x20"
 				device i2c 0x2c on end
 			end
-		end #I2C 0
-		device pci 15.2 on
+		end
+		device ref i2c2 on
                         chip drivers/generic/gpio_keys
 				register "name" = ""PENH""
 				register "gpio" = "ACPI_GPIO_INPUT_ACTIVE_LOW(GPP_C12)"
@@ -296,8 +296,8 @@ chip soc/intel/jasperlake
 				register "hid_desc_reg_offset" = "0x20"
 				device i2c 2c alias wdht0002 on end
 			end
-		end # I2C 2
-		device pci 15.3 on
+		end
+		device ref i2c3 on
 			chip drivers/intel/mipi_camera
 				register "acpi_hid" = ""OVTI8856""
 				register "acpi_uid" = "0"
@@ -395,8 +395,8 @@ chip soc/intel/jasperlake
 				register "off_seq.ops[0]" = "SEQ_OPS_GPIO_DISABLE(0, 0)"
 				device i2c 50 on end
 			end
-		end # I2C 3
-		device pci 19.0 on
+		end
+		device ref i2c4 on
 			chip drivers/i2c/generic
 				register "hid" = ""10EC5682""
 				register "name" = ""RT58""
@@ -426,19 +426,19 @@ chip soc/intel/jasperlake
 					probe AUDIO_CODEC_SOURCE AUDIO_CODEC_ALC5682I_VS
 				end
 			end
-		end #I2C 4
-		device pci 1c.7 on
+		end
+		device ref pcie_rp8 on
 			chip drivers/wifi/generic
 				register "wake" = "GPE0_DW2_03"
 				device pci 00.0 on end
 			end
 		end
-		device pci 1f.3 on
+		device ref hda on
 			chip drivers/generic/max98357a
 				register "hid" = ""MX98360A""
 				register "sdmode_gpio" =  "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D17)"
 				device generic 0 on end
 			end
-		end # Intel HDA
+		end
 	end
 end
diff --git a/src/mainboard/google/dedede/variants/driblee/overridetree.cb b/src/mainboard/google/dedede/variants/driblee/overridetree.cb
index a703ada882..23d1875054 100644
--- a/src/mainboard/google/dedede/variants/driblee/overridetree.cb
+++ b/src/mainboard/google/dedede/variants/driblee/overridetree.cb
@@ -35,7 +35,7 @@ chip soc/intel/jasperlake
 	register "SerialIoGSpiCsMode[PchSerialIoIndexGSPI0]" = "0"
 
 	device domain 0 on
-		device pci 04.0 on
+		device ref dptf on
 			chip drivers/intel/dptf
 				## Passive Policy
 				register "policies.passive" = "{
@@ -70,31 +70,19 @@ chip soc/intel/jasperlake
 				}"
 				device generic 0 on end
 			end
-		end # SA Thermal device
-		device pci 14.0 on
+		end
+		device ref south_xhci on
 			chip drivers/usb/acpi
-				device usb 0.0 on
-					chip drivers/usb/acpi
-						device usb 2.1 off end
-					end
-					chip drivers/usb/acpi
-						device usb 2.3 off end
-					end
+				device ref xhci_root_hub on
 					chip drivers/usb/acpi
 						register "desc" = ""Camera (UFC)""
 						register "type" = "UPC_TYPE_INTERNAL"
-						device usb 2.5 on end
-					end
-					chip drivers/usb/acpi
-						device usb 3.1 off end
-					end
-					chip drivers/usb/acpi
-						device usb 3.3 off end
+						device ref usb2_port6 on end
 					end
 				end
 			end
-		end # USB xHCI
-		device pci 15.0 on
+		end
+		device ref i2c0 on
 			chip drivers/i2c/generic
 				register "hid" = ""ELAN0000""
 				register "desc" = ""ELAN Touchpad""
@@ -112,8 +100,8 @@ chip soc/intel/jasperlake
 				register "hid_desc_reg_offset" = "0x20"
 				device i2c 2c on end
 			end
-		end #I2C 0
-		device pci 19.0 on
+		end
+		device ref i2c4 on
 			chip drivers/i2c/cs42l42
 				register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_D16)"
 				register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_H16)"
@@ -130,19 +118,18 @@ chip soc/intel/jasperlake
 				register "hs_bias_sense_disable" = "true"
 				device i2c 48 on end
 			end
-		end #I2C 4
-		device pci 1e.2 off end # GSPI 0
-		device pci 1f.0 on
+		end
+		device ref pch_espi on
 			chip drivers/pc80/tpm
 				device pnp 0c31.0 on end # Discrete TPM
-			end # chip drivers/pc80/tpm
-		end # PCH eSPI
-		device pci 1f.3 on
+			end
+		end
+		device ref hda on
 			chip drivers/generic/max98357a
 				register "hid" = ""MX98360A""
 				register "sdmode_gpio" =  "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D17)"
 				device generic 0 on end
 			end
-		end # Intel HDA
+		end
 	end
 end
diff --git a/src/mainboard/google/dedede/variants/galtic/overridetree.cb b/src/mainboard/google/dedede/variants/galtic/overridetree.cb
index 3a5597c3f4..189029b5cd 100644
--- a/src/mainboard/google/dedede/variants/galtic/overridetree.cb
+++ b/src/mainboard/google/dedede/variants/galtic/overridetree.cb
@@ -69,7 +69,7 @@ chip soc/intel/jasperlake
 	register "tcc_offset" = "8"     # TCC of 97C
 
 	device domain 0 on
-		device pci 04.0 on
+		device ref dptf on
 			# Default DPTF Policy for all Dedede boards if not overridden
 			chip drivers/intel/dptf
 				## Passive Policy
@@ -120,20 +120,20 @@ chip soc/intel/jasperlake
 
 				device generic 0 on end
 			end
-		end # SA Thermal device
-		device pci 14.0 on
+		end
+		device ref south_xhci on
 			chip drivers/usb/acpi
-				device usb 0.0 on
+				device ref xhci_root_hub on
 					chip drivers/usb/acpi
 						register "desc" = ""Camera""
 						register "type" = "UPC_TYPE_INTERNAL"
-						device usb 2.5 on end
+						device ref usb2_port6 on end
 					end
 				end
 			end
-		end # USB xHCI
+		end
 
-		device pci 15.0 on
+		device ref i2c0 on
 			chip drivers/i2c/generic
 				register "hid" = ""ELAN0000""
 				register "desc" = ""ELAN Touchpad""
@@ -150,7 +150,7 @@ chip soc/intel/jasperlake
 				device i2c 15 alias elan2702 on end
 			end
 		end
-		device pci 15.2 on
+		device ref i2c2 on
 			chip drivers/i2c/generic
 				register "hid" = ""ELAN0001""
 				register "desc" = ""ELAN Touchscreen""
@@ -183,8 +183,8 @@ chip soc/intel/jasperlake
 					probe TOUCHSCREEN_SOURCE TOUCHSCREEN_ELAN9008
 				end
 			end
-		end # I2C 2
-		device pci 19.0 on
+		end
+		device ref i2c4 on
 			chip drivers/i2c/generic
 				register "hid" = ""10EC5682""
 				register "name" = ""RT58""
@@ -231,13 +231,13 @@ chip soc/intel/jasperlake
 				end
 			end
 		end
-		device pci 1f.3 on
+		device ref hda on
 			chip drivers/generic/alc1015
 				register "sdb" =  "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D17)"
 				device generic 0 on
 					probe AUDIO_AMP RT1015P_AUTO
 				end
 			end
-		end # Intel HDA
+		end
 	end
 end
diff --git a/src/mainboard/google/dedede/variants/gooey/overridetree.cb b/src/mainboard/google/dedede/variants/gooey/overridetree.cb
index d7e9d47241..0a73b9c471 100644
--- a/src/mainboard/google/dedede/variants/gooey/overridetree.cb
+++ b/src/mainboard/google/dedede/variants/gooey/overridetree.cb
@@ -68,7 +68,7 @@ chip soc/intel/jasperlake
 	register "xhci_lfps_sampling_offtime_ms" = "0"
 
 	device domain 0 on
-		device pci 04.0 on
+		device ref dptf on
 			chip drivers/intel/dptf
 				## Passive Policy
 				register "policies.passive" = "{
@@ -115,17 +115,17 @@ chip soc/intel/jasperlake
 
 				device generic 0 on end
 			end
-		end # SA Thermal device
-		device pci 14.0 on
+		end
+		device ref south_xhci on
 			chip drivers/usb/acpi
 				register "desc" = ""Root Hub""
 				register "type" = "UPC_TYPE_HUB"
-				device usb 0.0 on
+				device ref xhci_root_hub on
 					chip drivers/usb/acpi
 						register "desc" = ""Right Type-A Port""
 						register "type" = "UPC_TYPE_A"
 						register "group" = "ACPI_PLD_GROUP(2, 1)"
-						device usb 2.1 on end
+						device ref usb2_port2 on end
 					end
 					chip drivers/usb/acpi
 						register "desc" = ""LTE""
@@ -135,33 +135,33 @@ chip soc/intel/jasperlake
 						register "reset_off_delay_ms" = "10"
 						register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A10)"
 						register "enable_delay_ms" = "20"
-						device usb 2.3 on end
+						device ref usb2_port4 on end
 					end
 					chip drivers/usb/acpi
 						register "desc" = ""UFCamera""
 						register "type" = "UPC_TYPE_INTERNAL"
-						device usb 2.5 on end
+						device ref usb2_port6 on end
 					end
 					chip drivers/usb/acpi
 						register "desc" = ""WFCamera""
 						register "type" = "UPC_TYPE_INTERNAL"
-						device usb 2.6 on end
+						device ref usb2_port7 on end
 					end
 					chip drivers/usb/acpi
 						register "desc" = ""Right Type-A Port""
 						register "type" = "UPC_TYPE_USB3_A"
 						register "group" = "ACPI_PLD_GROUP(2, 1)"
-						device usb 3.1 on end
+						device ref usb3_port2 on end
 					end
 					chip drivers/usb/acpi
 						register "desc" = ""LTE""
 						register "type" = "UPC_TYPE_INTERNAL"
-						device usb 3.3 on end
+						device ref usb3_port4 on end
 					end
 				end
 			end
-		end # USB xHCI
-		device pci 15.0 on
+		end
+		device ref i2c0 on
 			chip drivers/i2c/generic
 				register "hid" = ""ELAN0000""
 				register "desc" = ""ELAN Touchpad""
@@ -180,8 +180,8 @@ chip soc/intel/jasperlake
 				register "hid_desc_reg_offset" = "0x20"
 				device i2c 0x2c on end
 			end
-		end # I2C 0
-		device pci 15.2 on
+		end
+		device ref i2c2 on
 			chip drivers/generic/gpio_keys
 				register "name" = ""PENH""
 				register "gpio" = "ACPI_GPIO_INPUT_ACTIVE_LOW(GPP_C12)"
@@ -233,8 +233,8 @@ chip soc/intel/jasperlake
 				register "hid_desc_reg_offset" = "0x01"
 				device i2c 10 on end
 			end
-		end # I2C 2
-		device pci 19.0 on
+		end
+		device ref i2c4 on
 			chip drivers/i2c/generic
 				register "hid" = ""10EC5682""
 				register "name" = ""RT58""
@@ -280,8 +280,8 @@ chip soc/intel/jasperlake
 					probe AUDIO_AMP UNPROVISIONED
 				end
 			end
-		end # I2C 4
-		device pci 19.1 on
+		end
+		device ref i2c5 on
 			chip drivers/i2c/sx9324
 				register "desc" = ""SAR Proximity Sensor""
 				register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_E11_IRQ)"
@@ -335,19 +335,18 @@ chip soc/intel/jasperlake
 				device i2c 28 on end
 			end
 		end # I2C 5
-		device pci 1f.0 on
+		device ref pch_espi on
 			chip drivers/pc80/tpm
 				device pnp 0c31.0 on end # Discrete TPM
-			end # chip drivers/pc80/tpm
-		end # PCH eSPI
-		device pci 1e.2 off end # GSPI 0
-		device pci 1f.3 on
+			end
+		end
+		device ref hda on
 			chip drivers/generic/alc1015
 				register "sdb" =  "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D17)"
 				device generic 0 on
 					probe AUDIO_AMP RT1015P_AUTO
 				end
 			end
-		end # Intel HDA
+		end
 	end
 end
diff --git a/src/mainboard/google/dedede/variants/haboki/overridetree.cb b/src/mainboard/google/dedede/variants/haboki/overridetree.cb
index 030b143204..7146bd899f 100644
--- a/src/mainboard/google/dedede/variants/haboki/overridetree.cb
+++ b/src/mainboard/google/dedede/variants/haboki/overridetree.cb
@@ -53,7 +53,7 @@ chip soc/intel/jasperlake
 	register "FastPkgCRampDisable" = "1"
 
 	device domain 0 on
-		device pci 05.0 on # IPU - MIPI Camera
+		device ref ipu on
 			chip drivers/intel/mipi_camera
 				register "acpi_uid" = "0x50000"
 				register "acpi_name" = ""IPU0""
@@ -68,7 +68,7 @@ chip soc/intel/jasperlake
 			end
 		end
 
-		device pci 04.0 on
+		device ref dptf on
 			chip drivers/intel/dptf
 				# Default DPTF Policy for all drawcia boards if not overridden
 				register "options.tsr[0].desc" = ""Memory""
@@ -122,7 +122,7 @@ chip soc/intel/jasperlake
 				device generic 0 on end
 			end
 		end # SA Thermal device
-		device pci 14.0 on
+		device ref south_xhci on
 			chip drivers/usb/acpi
 				device usb 0.0 on
 					chip drivers/usb/acpi
@@ -132,8 +132,8 @@ chip soc/intel/jasperlake
 					end
 				end
 			end
-		end # USB xHCI
-		device pci 15.0 on
+		end
+		device ref i2c0 on
 			chip drivers/i2c/generic
 				register "hid" = ""ELAN0000""
 				register "desc" = ""ELAN Touchpad""
@@ -142,8 +142,8 @@ chip soc/intel/jasperlake
 				register "detect" = "1"
 				device i2c 15 on end
 			end
-		end #I2C 0
-		device pci 15.2 on
+		end
+		device ref i2c2 on
                         chip drivers/generic/gpio_keys
 				register "name" = ""PENH""
 				register "gpio" = "ACPI_GPIO_INPUT_ACTIVE_LOW(GPP_C12)"
@@ -210,8 +210,8 @@ chip soc/intel/jasperlake
 				register "hid_desc_reg_offset" = "0x01"
 				device i2c 15 on end
 			end
-		end # I2C 2
-		device pci 15.3 on
+		end
+		device ref i2c3 on
 			chip drivers/intel/mipi_camera
 				register "acpi_hid" = ""OVTI8856""
 				register "acpi_uid" = "0"
@@ -284,8 +284,8 @@ chip soc/intel/jasperlake
 
 				device i2c 50 on end
 			end
-		end # I2C 3
-		device pci 19.0 on
+		end
+		device ref i2c4 on
 			chip drivers/i2c/generic
 				register "hid" = ""10EC5682""
 				register "name" = ""RT58""
@@ -298,19 +298,18 @@ chip soc/intel/jasperlake
 				register "property_list[0].integer" = "1"
 				device i2c 1a on end
 			end
-		end #I2C 4
-		device pci 1f.0 on
+		end
+		device ref pch_espi on
 			chip drivers/pc80/tpm
 				device pnp 0c31.0 on end # Discrete TPM
-			end # chip drivers/pc80/tpm
-		end # PCH eSPI
-		device pci 1e.2 off end # GSPI 0
-		device pci 1f.3 on
+			end
+		end
+		device ref hda on
 			chip drivers/generic/max98357a
 				register "hid" = ""MX98360A""
 				register "sdmode_gpio" =  "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D17)"
 				device generic 0 on end
 			end
-		end # Intel HDA
+		end
 	end
 end
diff --git a/src/mainboard/google/dedede/variants/kracko/overridetree.cb b/src/mainboard/google/dedede/variants/kracko/overridetree.cb
index 388850570b..c45ccdc428 100644
--- a/src/mainboard/google/dedede/variants/kracko/overridetree.cb
+++ b/src/mainboard/google/dedede/variants/kracko/overridetree.cb
@@ -65,7 +65,7 @@ chip soc/intel/jasperlake
 	register "tcc_offset" = "20"	# TCC of 85C
 
 	device domain 0 on
-		device pci 04.0 on
+		device ref dptf on
 			chip drivers/intel/dptf
 				# Default DPTF Policy for all drawcia boards if not overridden
 				register "options.tsr[0].desc" = ""Memory""
@@ -113,10 +113,10 @@ chip soc/intel/jasperlake
 				}"
 				device generic 0 alias dptf_policy on end
 			end
-		end # SA Thermal device
-		device pci 14.0 on
+		end
+		device ref south_xhci on
 			chip drivers/usb/acpi
-				device usb 0.0 on
+				device ref xhci_root_hub on
 					chip drivers/usb/acpi
 						register "desc" = ""LTE""
 						register "type" = "UPC_TYPE_INTERNAL"
@@ -126,7 +126,7 @@ chip soc/intel/jasperlake
 						register "reset_off_delay_ms" = "20"
 						register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A10)"
 						register "enable_delay_ms" = "20"
-						device usb 2.3 on
+						device ref usb2_port4 on
 							probe DB_PORTS DB_PORTS_1C_LTE
 							probe DB_PORTS DB_PORTS_LTE
 						end
@@ -135,7 +135,7 @@ chip soc/intel/jasperlake
 						register "desc" = ""Right Type-C Port""
 						register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
 						register "group" = "ACPI_PLD_GROUP(2, 1)"
-						device usb 2.1 on
+						device ref usb2_port2 on
 							probe DB_PORTS DB_PORTS_1C_1A
 							probe DB_PORTS DB_PORTS_1C_LTE
 						end
@@ -144,25 +144,25 @@ chip soc/intel/jasperlake
 						register "desc" = ""Right Type-A Port""
 						register "type" = "UPC_TYPE_A"
 						register "group" = "ACPI_PLD_GROUP(2, 2)"
-						device usb 2.3 on
+						device ref usb2_port4 on
 							probe DB_PORTS DB_PORTS_1C_1A
 						end
 					end
 					chip drivers/usb/acpi
 						register "desc" = ""UFCamera""
 						register "type" = "UPC_TYPE_INTERNAL"
-						device usb 2.5 on end
+						device ref usb2_port6 on end
 					end
 					chip drivers/usb/acpi
 						register "desc" = ""WFCamera""
 						register "type" = "UPC_TYPE_INTERNAL"
-						device usb 2.6 on end
+						device ref usb2_port7 on end
 					end
 					chip drivers/usb/acpi
 						register "desc" = ""Right Type-C Port""
 						register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
 						register "group" = "ACPI_PLD_GROUP(2, 1)"
-						device usb 3.1 on
+						device ref usb3_port2 on
 							probe DB_PORTS DB_PORTS_1C_1A
 							probe DB_PORTS DB_PORTS_1C_LTE
 						end
@@ -171,7 +171,7 @@ chip soc/intel/jasperlake
 						register "desc" = ""LTE""
 						register "type" = "UPC_TYPE_INTERNAL"
 						register "group" = "ACPI_PLD_GROUP(2, 2)"
-						device usb 3.3 on
+						device ref usb3_port4 on
 							probe DB_PORTS DB_PORTS_1C_LTE
 							probe DB_PORTS DB_PORTS_LTE
 						end
@@ -180,14 +180,14 @@ chip soc/intel/jasperlake
 						register "desc" = ""Right Type-A Port""
 						register "type" = "UPC_TYPE_USB3_A"
 						register "group" = "ACPI_PLD_GROUP(2, 2)"
-						device usb 3.3 on
+						device ref usb3_port4 on
 							probe DB_PORTS DB_PORTS_1C_1A
 						end
 					end
 				end
 			end
 		end # USB xHCI
-		device pci 15.0 on
+		device ref i2c0 on
 			chip drivers/i2c/generic
 				register "hid" = ""ELAN0000""
 				register "desc" = ""ELAN Touchpad""
@@ -196,8 +196,8 @@ chip soc/intel/jasperlake
 				register "detect" = "1"
 				device i2c 15 on end
 			end
-		end #I2C 0
-		device pci 15.2 on
+		end
+		device ref i2c2 on
 			chip drivers/i2c/generic
 				register "hid" = ""ELAN0001""
 				register "desc" = ""ELAN Touchscreen""
@@ -240,8 +240,8 @@ chip soc/intel/jasperlake
                                 device i2c 40 on end
                         end
 
-		end # I2C 2
-		device pci 19.0 on
+		end
+		device ref i2c4 on
 			chip drivers/i2c/generic
 				register "hid" = ""10EC5682""
 				register "name" = ""RT58""
@@ -270,8 +270,8 @@ chip soc/intel/jasperlake
 					probe AUDIO_CODEC_SOURCE AUDIO_CODEC_ALC5682I_VS
 				end
 			end
-		end #I2C 4
-		device pci 19.1 on
+		end
+		device ref i2c5 on
 			chip drivers/i2c/sx9324
 				register "desc" = ""SAR Proximity Sensor""
 				register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_E11_IRQ)"
@@ -324,12 +324,12 @@ chip soc/intel/jasperlake
 				device i2c 28 on end
 			end
 		end # I2C 5
-		device pci 1f.3 on
+		device ref hda on
 			chip drivers/generic/max98357a
 				register "hid" = ""MX98360A""
 				register "sdmode_gpio" =  "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D17)"
 				device generic 0 on end
 			end
-		end # Intel HDA
+		end
 	end
 end
diff --git a/src/mainboard/google/dedede/variants/lalala/overridetree.cb b/src/mainboard/google/dedede/variants/lalala/overridetree.cb
index 90620d6c7d..26569c52ca 100644
--- a/src/mainboard/google/dedede/variants/lalala/overridetree.cb
+++ b/src/mainboard/google/dedede/variants/lalala/overridetree.cb
@@ -87,7 +87,7 @@ chip soc/intel/jasperlake
 	register "FastPkgCRampDisable" = "1"
 
 	device domain 0 on
-		device pci 04.0 on
+		device ref dptf on
 			chip drivers/intel/dptf
 				register "options.tsr[0].desc" = ""Memory""
 				register "options.tsr[1].desc" = ""Ambient""
@@ -121,8 +121,8 @@ chip soc/intel/jasperlake
 
 				device generic 0 on end
 			end
-		end # SA Thermal device
-		device pci 05.0 on # IPU - MIPI Camera
+		end
+		device ref ipu on
 			chip drivers/intel/mipi_camera
 				register "acpi_uid" = "0x50000"
 				register "acpi_name" = ""IPU0""
@@ -135,18 +135,18 @@ chip soc/intel/jasperlake
 				device generic 0 on end
 			end
 		end
-		device pci 14.0 on
+		device ref south_xhci on
 			chip drivers/usb/acpi
-				device usb 0.0 on
+				device ref xhci_root_hub on
 					chip drivers/usb/acpi
 						register "desc" = ""Camera""
 						register "type" = "UPC_TYPE_INTERNAL"
-						device usb 2.5 on end
+						device ref usb2_port6 on end
 					end
 				end
 			end
-		end # USB xHCI
-		device pci 15.0 on
+		end
+		device ref i2c0 on
 			chip drivers/i2c/hid
 				register "generic.hid" = ""SYNA0000""
 				register "generic.cid" = ""ACPI0C50""
@@ -165,8 +165,8 @@ chip soc/intel/jasperlake
 				register "detect" = "1"
 				device i2c 15 on end
 			end
-		end # I2C 0
-		device pci 15.2 on
+		end
+		device ref i2c2 on
 			chip drivers/i2c/hid
 				register "generic.hid" = ""ELAN6915""
 				register "generic.desc" = ""ELAN Touchscreen""
@@ -209,7 +209,7 @@ chip soc/intel/jasperlake
 				device i2c 39 on end
 			end
 		end # I2C 2
-		device pci 15.3 on # I2C 3
+		device ref i2c3 on
 			chip drivers/intel/mipi_camera
 				register "acpi_hid" = ""OVTI5675""
 				register "acpi_uid" = "0"
@@ -285,7 +285,7 @@ chip soc/intel/jasperlake
 				device i2c 50 on end
 			end
 		end
-		device pci 19.0 on
+		device ref i2c4 on
 			chip drivers/i2c/generic
 				register "hid" = ""10EC5682""
 				register "name" = ""RT58""
@@ -310,14 +310,13 @@ chip soc/intel/jasperlake
 				device i2c 29 on end
 			end
 		end
-		device pci 1f.0 on
+		device ref pch_espi on
 			chip drivers/pc80/tpm
 				device pnp 0c31.0 on end # Discrete TPM
 			end # chip drivers/pc80/tpm
-		end # PCH eSPI
-		device pci 1e.2 off end # GSPI 0
-		device pci 1f.3 on end # Intel HDA
-		device pci 1c.7 on
+		end
+		device ref hda on end
+		device ref pcie_rp8 on
 			chip drivers/wifi/generic
 				register "wake" = "GPE0_DW2_03"
 				device pci 00.0 on  end
diff --git a/src/mainboard/google/dedede/variants/lantis/overridetree.cb b/src/mainboard/google/dedede/variants/lantis/overridetree.cb
index c21ccf2643..21e15d43ee 100644
--- a/src/mainboard/google/dedede/variants/lantis/overridetree.cb
+++ b/src/mainboard/google/dedede/variants/lantis/overridetree.cb
@@ -90,7 +90,7 @@ chip soc/intel/jasperlake
 	register "FastPkgCRampDisable" = "1"
 
 	device domain 0 on
-		device pci 04.0 on
+		device ref dptf on
 			chip drivers/intel/dptf
 				register "options.tsr[0].desc" = ""Memory""
 				register "options.tsr[1].desc" = ""Ambient""
@@ -141,31 +141,31 @@ chip soc/intel/jasperlake
 
 				device generic 0 on end
 			end
-		end # SA Thermal device
-		device pci 14.0 on
+		end
+		device ref south_xhci on
 			chip drivers/usb/acpi
-				device usb 0.0 on
+				device ref xhci_root_hub on
 					chip drivers/usb/acpi
 						register "desc" = ""Discrete Bluetooth""
 						register "type" = "UPC_TYPE_INTERNAL"
 						register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_H19)"
-						device usb 2.4 on end
+						device ref usb2_port5 on end
 					end
 					chip drivers/usb/acpi
 						register "desc" = ""Camera""
 						register "type" = "UPC_TYPE_INTERNAL"
-						device usb 2.5 on end
+						device ref usb2_port6 on end
 					end
 					chip drivers/usb/acpi
 						register "desc" = ""Integrated Bluetooth""
 						register "type" = "UPC_TYPE_INTERNAL"
 						register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_H19)"
-						device usb 2.7 on end
+						device ref usb2_port8 on end
 					end
 				end
 			end
-		end # USB xHCI
-		device pci 15.0 on
+		end
+		device ref i2c0 on
 			chip drivers/i2c/generic
 				register "hid" = ""ELAN0000""
 				register "desc" = ""ELAN Touchpad""
@@ -174,8 +174,8 @@ chip soc/intel/jasperlake
 				register "detect" = "1"
 				device i2c 15 on end
 			end
-		end #I2C 0
-		device pci 15.2 on
+		end
+		device ref i2c2 on
 			chip drivers/i2c/generic
 				register "hid" = ""ELAN0001""
 				register "desc" = ""ELAN Touchscreen""
@@ -233,14 +233,14 @@ chip soc/intel/jasperlake
 				register "hid_desc_reg_offset" = "0x01"
 				device i2c 0x5d on end
 			end
-		end # I2C 2
-		device pci 1c.7 on
+		end
+		device ref pcie_rp8 on
 			chip drivers/wifi/generic
 				register "wake" = "GPE0_DW2_03"
 				device pci 00.0 on  end
 			end
-		end # PCI Express Root Port 8 - WLAN
-		device pci 19.0 on
+		end
+		device ref i2c4 on
 			chip drivers/i2c/generic
 				register "hid" = ""10EC5682""
 				register "name" = ""RT58""
@@ -268,13 +268,13 @@ chip soc/intel/jasperlake
 					probe AUDIO_CODEC_SOURCE AUDIO_CODEC_ALC5682I_VS
 				end
 			end
-		end #I2C 4
-		device pci 1f.3 on
+		end
+		device ref hda on
 			chip drivers/generic/max98357a
 				register "hid" = ""MX98360A""
 				register "sdmode_gpio" =  "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D17)"
 				device generic 0 on end
 			end
-		end # Intel HDA
+		end
 	end
 end
diff --git a/src/mainboard/google/dedede/variants/madoo/overridetree.cb b/src/mainboard/google/dedede/variants/madoo/overridetree.cb
index c69b482ef0..801b947f1e 100644
--- a/src/mainboard/google/dedede/variants/madoo/overridetree.cb
+++ b/src/mainboard/google/dedede/variants/madoo/overridetree.cb
@@ -57,7 +57,7 @@ chip soc/intel/jasperlake
 	register "SlowSlewRate" = "2"
 
 	device domain 0 on
-		device pci 04.0 on
+		device ref dptf on
 			chip drivers/intel/dptf
 				register "policies.passive" = "{
 					[0] = DPTF_PASSIVE(CPU, CPU, 65, 1000),
@@ -81,25 +81,19 @@ chip soc/intel/jasperlake
 						.granularity = 1000,}"
 				device generic 0 on end
 			end
-		end # SA Thermal device
-		device pci 14.0 on
+		end
+		device ref south_xhci on
 			chip drivers/usb/acpi
-				device usb 0.0 on
-					chip drivers/usb/acpi
-						device usb 2.2 off end
-					end
+				device ref xhci_root_hub on
 					chip drivers/usb/acpi
 						register "desc" = ""Camera""
 						register "type" = "UPC_TYPE_INTERNAL"
-						device usb 2.5 on end
-					end
-					chip drivers/usb/acpi
-						device usb 3.2 off end
+						device ref usb2_port6 on end
 					end
 				end
 			end
 		end # USB xHCI
-		device pci 15.0 on
+		device ref i2c0 on
 			chip drivers/i2c/generic
 				register "hid" = ""ELAN0000""
 				register "desc" = ""ELAN Touchpad""
@@ -108,8 +102,8 @@ chip soc/intel/jasperlake
 				register "detect" = "1"
 				device i2c 15 on end
 			end
-		end #I2C 0
-		device pci 15.2 on
+		end
+		device ref i2c2 on
 			chip drivers/i2c/hid
 				register "generic.hid" = ""GDIX0000""
 				register "generic.desc" = ""Goodix Touchscreen""
@@ -125,14 +119,14 @@ chip soc/intel/jasperlake
 				register "hid_desc_reg_offset" = "0x01"
 				device i2c 0x5d on end
 			end
-		end # I2C 2
-		device pci 1c.7 on
+		end
+		device ref pcie_rp8 on
 			chip drivers/wifi/generic
 				register "wake" = "GPE0_DW2_03"
 				device pci 00.0 on  end
 			end
-		end # PCI Express Root Port 8 - WLAN
-		device pci 19.0 on
+		end
+		device ref i2c4 on
 			chip drivers/i2c/generic
 				register "hid" = ""10EC5682""
 				register "name" = ""RT58""
@@ -145,13 +139,13 @@ chip soc/intel/jasperlake
 				register "property_list[0].integer" = "1"
 				device i2c 1a on end
 			end
-		end #I2C 4
-		device pci 1f.3 on
+		end
+		device ref hda on
 			chip drivers/generic/max98357a
 				register "hid" = ""MX98360A""
 				register "sdmode_gpio" =  "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D17)"
 				device generic 0 on end
 			end
-		end # Intel HDA
+		end
 	end
 end
diff --git a/src/mainboard/google/dedede/variants/magolor/overridetree.cb b/src/mainboard/google/dedede/variants/magolor/overridetree.cb
index c32429dc24..45cd9971ca 100644
--- a/src/mainboard/google/dedede/variants/magolor/overridetree.cb
+++ b/src/mainboard/google/dedede/variants/magolor/overridetree.cb
@@ -126,7 +126,7 @@ chip soc/intel/jasperlake
 	register "FastPkgCRampDisable" = "1"
 
 	device domain 0 on
-		device pci 04.0 on
+		device ref dptf on
 			chip drivers/intel/dptf
 				register "options.tsr[0].desc" = ""Memory""
 				register "options.tsr[1].desc" = ""Ambient""
@@ -160,8 +160,8 @@ chip soc/intel/jasperlake
 
 				device generic 0 on end
 			end
-		end # SA Thermal device
-		device pci 05.0 on # IPU - MIPI Camera
+		end
+		device ref ipu on
 			chip drivers/intel/mipi_camera
 				register "acpi_uid" = "0x50000"
 				register "acpi_name" = ""IPU0""
@@ -174,7 +174,7 @@ chip soc/intel/jasperlake
 				device generic 0 on end
 			end
 		end
-		device pci 14.0 on
+		device ref south_xhci on
 			chip drivers/usb/acpi
 				device usb 0.0 on
 					chip drivers/usb/acpi
@@ -184,8 +184,8 @@ chip soc/intel/jasperlake
 					end
 				end
 			end
-		end # USB xHCI
-		device pci 15.0 on
+		end
+		device ref i2c0 on
 			chip drivers/i2c/hid
 				register "generic.hid" = ""SYNA0000""
 				register "generic.cid" = ""ACPI0C50""
@@ -204,8 +204,8 @@ chip soc/intel/jasperlake
 				register "detect" = "1"
 				device i2c 15 on end
 			end
-		end # I2C 0
-		device pci 15.2 on
+		end
+		device ref i2c2 on
 			chip drivers/generic/gpio_keys
 				register "name" = ""PENH""
 				register "gpio" = "ACPI_GPIO_INPUT_ACTIVE_LOW(GPP_C12)"
@@ -342,8 +342,8 @@ chip soc/intel/jasperlake
 					probe TS_SOURCE TS_RAYD_0001
 				end
 			end
-		end # I2C 2
-		device pci 15.3 on # I2C 3
+		end
+		device ref i2c3 on
 			chip drivers/intel/mipi_camera
 				register "acpi_hid" = ""OVTI5675""
 				register "acpi_uid" = "0"
@@ -470,7 +470,7 @@ chip soc/intel/jasperlake
 				device i2c 50 on end
 			end
 		end
-		device pci 19.0 on
+		device ref i2c4 on
 			chip drivers/i2c/generic
 				register "hid" = ""10EC5682""
 				register "name" = ""RT58""
@@ -536,19 +536,19 @@ chip soc/intel/jasperlake
 				end
 			end
 		end
-		device pci 1f.3 on
+		device ref hda on
 			chip drivers/generic/alc1015
 				register "sdb" =  "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D17)"
 				device generic 0 on
 					probe AUDIO_AMP RT1015P_AUTO
 				end
 			end
-		end # Intel HDA
-		device pci 1c.7 on
+		end
+		device ref pcie_rp8 on
 			chip drivers/wifi/generic
 				register "wake" = "GPE0_DW2_03"
 				device pci 00.0 on  end
 			end
-		end # PCI Express Root Port 8 - WLAN
+		end
 	end
 end
diff --git a/src/mainboard/google/dedede/variants/metaknight/overridetree.cb b/src/mainboard/google/dedede/variants/metaknight/overridetree.cb
index c116cccdae..631fb5c5df 100644
--- a/src/mainboard/google/dedede/variants/metaknight/overridetree.cb
+++ b/src/mainboard/google/dedede/variants/metaknight/overridetree.cb
@@ -84,7 +84,7 @@ chip soc/intel/jasperlake
 	}"
 
 	device domain 0 on
-		device pci 04.0 on
+		device ref dptf on
 			chip drivers/intel/dptf
 				register "options.tsr[0].desc" = ""Memory""
 				register "options.tsr[1].desc" = ""CPU""
@@ -118,10 +118,10 @@ chip soc/intel/jasperlake
 
 				device generic 0 on end
 			end
-		end # SA Thermal device
-		device pci 14.0 on
+		end
+		device ref south_xhci on
 			chip drivers/usb/acpi
-				device usb 0.0 on
+				device ref xhci_root_hub on
 					chip drivers/usb/acpi
 						register "desc" = ""LTE""
 						register "type" = "UPC_TYPE_INTERNAL"
@@ -171,8 +171,8 @@ chip soc/intel/jasperlake
 					end
 				end
 			end
-		end # USB xHCI
-		device pci 15.0 on
+		end
+		device ref i2c0 on
 			chip drivers/i2c/hid
 				register "generic.hid" = ""SYNA0000""
 				register "generic.cid" = ""ACPI0C50""
@@ -191,8 +191,8 @@ chip soc/intel/jasperlake
 				register "detect" = "1"
 				device i2c 15 on end
 			end
-		end # I2C 0
-		device pci 15.2 on
+		end
+		device ref i2c2 on
 			chip drivers/generic/gpio_keys
 				register "name" = ""PENH""
 				register "gpio" = "ACPI_GPIO_INPUT_ACTIVE_LOW(GPP_C12)"
@@ -238,8 +238,8 @@ chip soc/intel/jasperlake
 				register "hid_desc_reg_offset" = "0x01"
 				device i2c 15 on end
 			end
-		end # I2C 2
-		device pci 19.0 on
+		end
+		device ref i2c4 on
 			chip drivers/i2c/generic
 				register "hid" = ""10EC5682""
 				register "name" = ""RT58""
@@ -285,13 +285,13 @@ chip soc/intel/jasperlake
 				end
 			end
 		end
-		device pci 1f.3 on
+		device ref hda on
 			chip drivers/generic/alc1015
 				register "sdb" =  "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D17)"
 				device generic 0 on
 					probe AUDIO_AMP RT1015P_AUTO
 				end
 			end
-		end # Intel HDA
+		end
 	end
 end
diff --git a/src/mainboard/google/dedede/variants/pirika/overridetree.cb b/src/mainboard/google/dedede/variants/pirika/overridetree.cb
index d413e060e0..01f724c5fa 100644
--- a/src/mainboard/google/dedede/variants/pirika/overridetree.cb
+++ b/src/mainboard/google/dedede/variants/pirika/overridetree.cb
@@ -78,7 +78,7 @@ chip soc/intel/jasperlake
 	register "tcc_offset" = "8"     # TCC of 97C
 
 	device domain 0 on
-		device pci 04.0 on
+		device ref dptf on
 			# Default DPTF Policy for all Dedede boards if not overridden
 			chip drivers/intel/dptf
 				## Passive Policy
@@ -119,20 +119,20 @@ chip soc/intel/jasperlake
 
 				device generic 0 on end
 			end
-		end # SA Thermal device
-		device pci 14.0 on
+		end
+		device ref south_xhci on
 			chip drivers/usb/acpi
-				device usb 0.0 on
+				device ref xhci_root_hub on
 					chip drivers/usb/acpi
 						register "desc" = ""Camera""
 						register "type" = "UPC_TYPE_INTERNAL"
-						device usb 2.5 on end
+						device ref usb2_port6 on end
 					end
 				end
 			end
-		end # USB xHCI
+		end
 
-		device pci 15.0 on
+		device ref i2c0 on
 			chip drivers/i2c/generic
 				register "hid" = ""ELAN0000""
 				register "desc" = ""ELAN Touchpad""
@@ -152,7 +152,7 @@ chip soc/intel/jasperlake
 				device i2c 0x2c on end
 			end
 		end
-		device pci 15.2 on
+		device ref i2c2 on
 			chip drivers/i2c/generic
 				register "hid" = ""ELAN0001""
 				register "desc" = ""ELAN Touchscreen""
@@ -165,8 +165,8 @@ chip soc/intel/jasperlake
 				register "has_power_resource" = "true"
 				device i2c 10 on end
 			end
-		end # I2C 2
-		device pci 19.0 on
+		end
+		device ref i2c4 on
 			chip drivers/i2c/generic
 				register "hid" = ""10EC5682""
 				register "name" = ""RT58""
@@ -226,13 +226,13 @@ chip soc/intel/jasperlake
 				end
 			end
 		end
-		device pci 1f.3 on
+		device ref hda on
 			chip drivers/generic/alc1015
 				register "sdb" =  "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D17)"
 				device generic 0 on
 					probe AUDIO_AMP RT1015P_AUTO
 				end
 			end
-		end # Intel HDA
+		end
 	end
 end
diff --git a/src/mainboard/google/dedede/variants/sasuke/overridetree.cb b/src/mainboard/google/dedede/variants/sasuke/overridetree.cb
index 6f72562fe9..4be52ff3d2 100644
--- a/src/mainboard/google/dedede/variants/sasuke/overridetree.cb
+++ b/src/mainboard/google/dedede/variants/sasuke/overridetree.cb
@@ -85,7 +85,7 @@ chip soc/intel/jasperlake
 	register "SerialIoI2cMode[PchSerialIoIndexI2C4]" = "PchSerialIoPci"
 
 	device domain 0 on
-		device pci 04.0 on
+		device ref dptf on
 			chip drivers/intel/dptf
 				register "options.tsr[0].desc" = ""Charger""
 				register "options.tsr[1].desc" = ""Vcore""
@@ -123,8 +123,8 @@ chip soc/intel/jasperlake
 				}"
 				device generic 0 on end
 			end
-		end # SA Thermal device
-		device pci 14.0 on
+		end
+		device ref south_xhci on
 			chip drivers/usb/acpi
 				device usb 0.0 on
 					chip drivers/usb/acpi
@@ -133,7 +133,7 @@ chip soc/intel/jasperlake
 						register "has_power_resource" = "true"
 						register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D13)"
 						register "enable_delay_ms" = "20"
-						device usb 2.5 on end
+						device ref usb2_port6 on end
 					end
 					chip drivers/usb/acpi
 						register "desc" = ""LTE""
@@ -143,12 +143,12 @@ chip soc/intel/jasperlake
 						register "reset_off_delay_ms" = "20"
 						register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A10)"
 						register "enable_delay_ms" = "20"
-						device usb 3.3 on end
+						device ref usb3_port4 on end
 					end
 				end
 			end
-		end # USB xHCI
-		device pci 15.0 on
+		end
+		device ref i2c0 on
 			chip drivers/i2c/generic
 				register "hid" = ""ELAN0000""
 				register "desc" = ""ELAN Touchpad""
@@ -166,10 +166,8 @@ chip soc/intel/jasperlake
 				register "hid_desc_reg_offset" = "0xE"
 				device i2c 40 on end
 			end
-		end # I2C 0
-		device pci 15.2 on end
-		device pci 1c.7 off end # PCI Express Root Port 8
-		device pci 19.0 on
+		end
+		device ref i2c4 on
 			chip drivers/i2c/da7219
 				register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_D16)"
 				register "btn_cfg" = "50"
@@ -187,13 +185,13 @@ chip soc/intel/jasperlake
 				register "mic_amp_in_sel" = ""diff""
 				device i2c 1a on end
 			end
-		end #I2C 4
-		device pci 1f.3 on
+		end
+		device ref hda on
 			chip drivers/generic/max98357a
 				register "hid" = ""MX98360A""
 				register "sdmode_gpio" =  "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D17)"
 				device generic 0 on end
 			end
-		end # Intel HDA
+		end
 	end
 end
diff --git a/src/mainboard/google/dedede/variants/sasukette/overridetree.cb b/src/mainboard/google/dedede/variants/sasukette/overridetree.cb
index aa61b8e11d..90a7a10199 100644
--- a/src/mainboard/google/dedede/variants/sasukette/overridetree.cb
+++ b/src/mainboard/google/dedede/variants/sasukette/overridetree.cb
@@ -96,7 +96,7 @@ chip soc/intel/jasperlake
 	register "xhci_lfps_sampling_offtime_ms" = "0"
 
 	device domain 0 on
-		device pci 04.0 on
+		device ref dptf on
 			chip drivers/intel/dptf
 				## Passive Policy
 				register "policies.passive" = "{
@@ -131,8 +131,8 @@ chip soc/intel/jasperlake
 				}"
 				device generic 0 on end
 			end
-		end # SA Thermal device
-		device pci 14.0 on
+		end
+		device ref south_xhci on
 			chip drivers/usb/acpi
 				device usb 0.0 on
 					chip drivers/usb/acpi
@@ -141,7 +141,7 @@ chip soc/intel/jasperlake
 						register "has_power_resource" = "true"
 						register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D15)"
 						register "enable_delay_ms" = "20"
-						device usb 2.5 on end
+						device ref usb2_port6 on end
 					end
 					chip drivers/usb/acpi
 						register "desc" = ""LTE""
@@ -151,12 +151,12 @@ chip soc/intel/jasperlake
 						register "reset_off_delay_ms" = "20"
 						register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A10)"
 						register "enable_delay_ms" = "20"
-						device usb 3.3 on end
+						device ref usb3_port4 on end
 					end
 				end
 			end
-		end # USB xHCI
-		device pci 15.0 on
+		end
+		device ref i2c0 on
 			chip drivers/i2c/hid
 				register "generic.hid" = ""SYNA0A00""
 				register "generic.desc" = ""SYNA Touchpad""
@@ -201,8 +201,8 @@ chip soc/intel/jasperlake
 				register "detect" = "1"
 				device i2c 15 on end
 			end
-		end #I2C 0
-		device pci 19.0 on
+		end
+		device ref i2c4 on
 			chip drivers/i2c/generic
 				register "hid" = ""10EC5682""
 				register "name" = ""RT58""
@@ -230,13 +230,12 @@ chip soc/intel/jasperlake
 					probe AUDIO_CODEC_SOURCE AUDIO_CODEC_ALC5682I_VS
 				end
 			end
-		end #I2C 4
-		device pci 1c.7 off end # PCI Express Root Port 8
-		device pci 1f.3 on
+		end
+		device ref hda on
 			chip drivers/generic/alc1015
 				register "sdb" =  "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D17)"
 				device generic 0 on end
 			end
-		end # Intel HDA
+		end
 	end
 end
diff --git a/src/mainboard/google/dedede/variants/shotzo/overridetree.cb b/src/mainboard/google/dedede/variants/shotzo/overridetree.cb
index 7a821d7f8f..b32e39b1c9 100644
--- a/src/mainboard/google/dedede/variants/shotzo/overridetree.cb
+++ b/src/mainboard/google/dedede/variants/shotzo/overridetree.cb
@@ -67,7 +67,7 @@ chip soc/intel/jasperlake
 	register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)"     # Lan
 
 	device domain 0 on
-		device pci 04.0 on
+		device ref dptf on
 			chip drivers/intel/dptf
 				# Default DPTF Policy for all drawcia boards if not overridden
 				register "options.tsr[0].desc" = ""Ambient""
@@ -111,83 +111,83 @@ chip soc/intel/jasperlake
 
 				device generic 0 on end
 			end
-		end # SA Thermal device
-		device pci 14.0 on
+		end
+		device ref south_xhci on
 			chip drivers/usb/acpi
-				device usb 0.0 on
+				device ref xhci_root_hub on
 					chip drivers/usb/acpi
 						register "desc" = ""USB2 Type-C Port C0""
 						register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
 						register "group" = "ACPI_PLD_GROUP(1, 1)"
-						device usb 2.0 on end
+						device ref usb2_port1 on end
 					end
 					chip drivers/usb/acpi
 						register "desc" = ""USB2 Type-A Port A2""
 						register "type" = "UPC_TYPE_A"
 						register "group" = "ACPI_PLD_GROUP(2, 1)"
-						device usb 2.1 on end
+						device ref usb2_port2 on end
 					end
 					chip drivers/usb/acpi
 						register "desc" = ""USB2 Type-A Port A0""
 						register "type" = "UPC_TYPE_A"
 						register "group" = "ACPI_PLD_GROUP(2, 2)"
-						device usb 2.2 on end
+						device ref usb2_port3 on end
 					end
 					chip drivers/usb/acpi
 						register "desc" = ""USB2 Type-A Port A1""
 						register "type" = "UPC_TYPE_A"
 						register "group" = "ACPI_PLD_GROUP(2, 3)"
-						device usb 2.3 on end
+						device ref usb2_port4 on end
 					end
 					chip drivers/usb/acpi
 						register "desc" = ""USB2 Type-A Port A3""
 						register "type" = "UPC_TYPE_A"
 						register "group" = "ACPI_PLD_GROUP(2, 4)"
-						device usb 2.4 on end
+						device ref usb2_port5 on end
 					end
 					chip drivers/usb/acpi
 						register "desc" = ""Camera""
 						register "type" = "UPC_TYPE_INTERNAL"
-						device usb 2.5 on end
+						device ref usb2_port6 on end
 					end
 					chip drivers/usb/acpi
 						register "desc" = ""LAN""
 						register "type" = "UPC_TYPE_INTERNAL"
-						device usb 2.6 on end
+						device ref usb2_port7 on end
 					end
 					chip drivers/usb/acpi
 						register "desc" = ""Bluetooth""
 						register "type" = "UPC_TYPE_INTERNAL"
 						register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_H19)"
-						device usb 2.7 on end
+						device ref usb2_port8 on end
 					end
 					chip drivers/usb/acpi
 						register "desc" = ""USB3 Type-C Port C0""
 						register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
 						register "group" = "ACPI_PLD_GROUP(1, 1)"
-						device usb 3.0 on end
+						device ref usb3_port1 on end
 					end
 					chip drivers/usb/acpi
 						register "desc" = ""LAN""
 						register "type" = "UPC_TYPE_INTERNAL"
-						device usb 3.1 on end
+						device ref usb3_port2 on end
 					end
 					chip drivers/usb/acpi
 						register "desc" = ""USB3 Type-A Port A0""
 						register "type" = "UPC_TYPE_USB3_A"
 						register "group" = "ACPI_PLD_GROUP(2, 1)"
-						device usb 3.2 on end
+						device ref usb3_port3 on end
 					end
 					chip drivers/usb/acpi
 						register "desc" = ""USB3 Type-A Port A1""
 						register "type" = "UPC_TYPE_USB3_A"
 						register "group" = "ACPI_PLD_GROUP(2, 2)"
-						device usb 3.3 on end
+						device ref usb3_port4 on end
 					end
 				end
 			end
 		end # USB xHCI
-		device pci 15.2 on
+		device ref i2c2 on
 			chip drivers/i2c/hid
 				register "generic.hid" = ""ILTK0001""
 				register "generic.desc" = ""ILITEK Touchscreen""
@@ -202,14 +202,14 @@ chip soc/intel/jasperlake
 				register "hid_desc_reg_offset" = "0x01"
 				device i2c 41 on end
 			end
-		end # I2C 2
-		device pci 1c.7 on
+		end
+		device ref pcie_rp8 on
 			chip drivers/wifi/generic
 				register "wake" = "GPE0_DW2_03"
 				device pci 00.0 on  end
 			end
-		end # PCI Express Root Port 8 - WLAN
-		device pci 19.0 on
+		end
+		device ref i2c4 on
 			chip drivers/i2c/generic
 				register "hid" = ""RTL5682""
 				register "name" = ""RT58""
@@ -222,12 +222,12 @@ chip soc/intel/jasperlake
 				device i2c 1a on end
 			end
 		end #I2C 4
-		device pci 1f.3 on
+		device ref hda on
 			chip drivers/generic/alc1015
 				register "hid" = ""RTL1019""
 				register "sdb" =  "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D17)"
 				device generic 0 on end
 			end
-		end # Intel HDA
+		end
 	end
 end
diff --git a/src/mainboard/google/dedede/variants/storo/overridetree.cb b/src/mainboard/google/dedede/variants/storo/overridetree.cb
index f893829dc0..729aff50a2 100644
--- a/src/mainboard/google/dedede/variants/storo/overridetree.cb
+++ b/src/mainboard/google/dedede/variants/storo/overridetree.cb
@@ -100,7 +100,7 @@ chip soc/intel/jasperlake
 	register "xhci_lfps_sampling_offtime_ms" = "0"
 
 	device domain 0 on
-		device pci 04.0 on
+		device ref dptf on
 			chip drivers/intel/dptf
 				## Passive Policy
 				register "policies.passive" = "{
@@ -135,8 +135,8 @@ chip soc/intel/jasperlake
 				}"
 				device generic 0 on end
 			end
-		end # SA Thermal device
-		device pci 05.0 on # IPU - MIPI Camera
+		end
+		device ref ipu on
 			chip drivers/intel/mipi_camera
 				register "acpi_uid" = "0x50000"
 				register "acpi_name" = ""IPU0""
@@ -150,9 +150,9 @@ chip soc/intel/jasperlake
 				device generic 0 on end
 			end
 		end
-		device pci 14.0 on
+		device ref south_xhci on
 			chip drivers/usb/acpi
-				device usb 0.0 on
+				device ref xhci_root_hub on
 					chip drivers/usb/acpi
 						register "desc" = ""User Facing Camera""
 						register "type" = "UPC_TYPE_INTERNAL"
@@ -179,8 +179,8 @@ chip soc/intel/jasperlake
 					end
 				end
 			end
-		end # USB xHCI
-		device pci 15.0 on
+		end
+		device ref i2c0 on
 			chip drivers/i2c/generic
 				register "hid" = ""ELAN0000""
 				register "desc" = ""ELAN Touchpad""
@@ -189,8 +189,8 @@ chip soc/intel/jasperlake
 				register "detect" = "1"
 				device i2c 15 on end
 			end
-		end #I2C 0
-		device pci 15.2 on
+		end
+		device ref i2c2 on
 			chip drivers/generic/gpio_keys
 				register "name" = ""PENH""
 				register "gpio" = "ACPI_GPIO_INPUT_ACTIVE_LOW(GPP_C12)"
@@ -216,8 +216,8 @@ chip soc/intel/jasperlake
 				register "hid_desc_reg_offset" = "0x01"
 				device i2c 10 on end
 			end
-		end # I2C 2
-		device pci 15.3 on
+		end
+		device ref i2c3 on
 			chip drivers/intel/mipi_camera
 				register "acpi_hid" = ""OVTI8856""
 				register "acpi_uid" = "0"
@@ -290,8 +290,8 @@ chip soc/intel/jasperlake
 
 				device i2c 50 on end
 			end
-		end # I2C 3
-		device pci 19.0 on
+		end
+		device ref i2c4 on
 			chip drivers/i2c/generic
 				register "hid" = ""10EC5682""
 				register "name" = ""RT58""
@@ -319,14 +319,14 @@ chip soc/intel/jasperlake
 					probe AUDIO_CODEC_SOURCE AUDIO_CODEC_ALC5682I_VS
 				end
 			end
-		end # I2C 4
-		device pci 1f.3 on
+		end
+		device ref hda on
 			chip drivers/generic/alc1015
 				register "sdb" =  "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D17)"
 				device generic 0 on end
 			end
-		end # Intel HDA
-		device pci 19.1 on
+		end
+		device ref i2c5 on
 			chip drivers/i2c/sx9324
 				register "desc" = ""SAR Proximity Sensor""
 				register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_E11_IRQ)"
@@ -379,7 +379,6 @@ chip soc/intel/jasperlake
 				register "reg_irq_cfg2" = "0x01"
 				device i2c 28 on end
 			end
-		end # I2C 5
-		device pci 1c.7 off end # PCI Express Root Port 8
+		end
 	end
 end
diff --git a/src/mainboard/google/dedede/variants/taranza/overridetree.cb b/src/mainboard/google/dedede/variants/taranza/overridetree.cb
index 38a2d520a8..54910d5f4c 100644
--- a/src/mainboard/google/dedede/variants/taranza/overridetree.cb
+++ b/src/mainboard/google/dedede/variants/taranza/overridetree.cb
@@ -135,7 +135,7 @@ chip soc/intel/jasperlake
 					      USB_PORT_WAKE_ENABLE(6)"
 
 	device domain 0 on
-		device pci 04.0 on
+		device ref dptf on
 			chip drivers/intel/dptf
 				## Passive Policy
 				register "policies.passive" = "{
@@ -184,86 +184,86 @@ chip soc/intel/jasperlake
 
 				device generic 0 on end
 			end
-		end # SA Thermal device
-		device pci 14.0 on
+		end
+		device ref south_xhci on
 			chip drivers/usb/acpi
-				device usb 0.0 on
+				device ref xhci_root_hub on
 					chip drivers/usb/acpi
 						register "desc" = ""USB2 Type-C Port C0""
 						register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
 						register "group" = "ACPI_PLD_GROUP(2, 1)"
-						device usb 2.0 on end
+						device ref usb2_port1 on end
 					end
 					chip drivers/usb/acpi
 						register "desc" = ""USB2 Type-A Port A0""
 						register "type" = "UPC_TYPE_A"
 						register "group" = "ACPI_PLD_GROUP(2, 2)"
-						device usb 2.1 on end
+						device ref usb2_port2 on end
 					end
 					chip drivers/usb/acpi
 						register "desc" = ""USB2 Type-A Port A1""
 						register "type" = "UPC_TYPE_A"
 						register "group" = "ACPI_PLD_GROUP(2, 3)"
-						device usb 2.2 on end
+						device ref usb2_port3 on end
 					end
 					chip drivers/usb/acpi
 						register "desc" = ""USB2 Type-A Port A2""
 						register "type" = "UPC_TYPE_A"
 						register "group" = "ACPI_PLD_GROUP(1, 3)"
-						device usb 2.3 on end
+						device ref usb2_port4 on end
 					end
 					chip drivers/usb/acpi
 						register "desc" = ""USB2 Type-A Port A3""
 						register "type" = "UPC_TYPE_A"
 						register "group" = "ACPI_PLD_GROUP(1, 2)"
-						device usb 2.4 on end
+						device ref usb2_port5 on end
 					end
 					chip drivers/usb/acpi
 						register "desc" = ""USB2 Type-A Port A4""
 						register "type" = "UPC_TYPE_A"
 						register "group" = "ACPI_PLD_GROUP(1, 1)"
-						device usb 2.6 on end
+						device ref usb2_port7 on end
 					end
 					chip drivers/usb/acpi
 						register "desc" = ""USB3 Type-C Port C0""
 						register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
 						register "group" = "ACPI_PLD_GROUP(2, 1)"
-						device usb 3.0 on end
+						device ref usb3_port1 on end
 					end
 					chip drivers/usb/acpi
 						register "desc" = ""USB3 Type-A Port A4""
 						register "type" = "UPC_TYPE_USB3_A"
 						register "group" = "ACPI_PLD_GROUP(1, 1)"
-						device usb 3.1 on end
+						device ref usb3_port2 on end
 					end
 					chip drivers/usb/acpi
 						register "desc" = ""USB3 Type-A Port A0""
 						register "type" = "UPC_TYPE_USB3_A"
 						register "group" = "ACPI_PLD_GROUP(2, 2)"
-						device usb 3.2 on end
+						device ref usb3_port3 on end
 					end
 					chip drivers/usb/acpi
 						register "desc" = ""USB3 Type-A Port A1""
 						register "type" = "UPC_TYPE_USB3_A"
 						register "group" = "ACPI_PLD_GROUP(2, 3)"
-						device usb 3.3 on end
+						device ref usb3_port4 on end
 					end
 					chip drivers/usb/acpi
 						register "desc" = ""USB3 Type-A Port A3""
 						register "type" = "UPC_TYPE_USB3_A"
 						register "group" = "ACPI_PLD_GROUP(1, 2)"
-						device usb 3.4 on end
+						device ref usb3_port5 on end
 					end
 					chip drivers/usb/acpi
 						register "desc" = ""USB3 Type-A Port A2""
 						register "type" = "UPC_TYPE_USB3_A"
 						register "group" = "ACPI_PLD_GROUP(1, 3)"
-						device usb 3.5 on end
+						device ref usb3_port6 on end
 					end
 				end
 			end
-		end # USB xHCI
-		device pci 19.0 on
+		end
+		device ref i2c4 on
 			chip drivers/i2c/generic
 				register "hid" = ""RTL5682""
 				register "name" = ""RT58""
@@ -275,8 +275,8 @@ chip soc/intel/jasperlake
 				register "property_list[0].integer" = "1"
 				device i2c 1a on end
 			end
-		end # I2C 4
-		device pci 1c.2 on
+		end
+		device ref pcie_rp3 on
 			chip drivers/net
 				register "customized_leds" = "0x05af"
 				register "wake" = "GPE0_DW0_03" # GPP_B3
@@ -284,14 +284,13 @@ chip soc/intel/jasperlake
 				register "device_index" = "0"
 				device pci 00.0 on end
 			end
-		end # PCI Express Root Port 3 - RTL8111H LAN
-		device pci 1c.6 on
+		end
+		device ref pcie_rp7 on
 			chip drivers/wifi/generic
 				register "wake" = "GPE0_DW2_03"
 				device pci 00.0 on  end
 			end
-		end # PCI Express Root Port 7 - WLAN
-		device pci 1c.7 off end # PCI Express Root Port 8
-		device pci 1f.3 on end # Intel HDA
+		end
+		device ref hda on end
 	end
 end
diff --git a/src/mainboard/google/dedede/variants/waddledee/overridetree.cb b/src/mainboard/google/dedede/variants/waddledee/overridetree.cb
index 4fdddd18cc..7356e95625 100644
--- a/src/mainboard/google/dedede/variants/waddledee/overridetree.cb
+++ b/src/mainboard/google/dedede/variants/waddledee/overridetree.cb
@@ -61,26 +61,26 @@ chip soc/intel/jasperlake
 	register "SerialIoI2cMode[PchSerialIoIndexI2C4]" = "PchSerialIoPci"
 
 	device domain 0 on
-		device pci 05.0 on end # IPU - MIPI Camera
-		device pci 14.0 on
+		device ref ipu on end
+		device ref south_xhci on
 			chip drivers/usb/acpi
-				device usb 0.0 on
+				device ref xhci_root_hub on
 					chip drivers/usb/acpi
 						register "desc" = ""Discrete Bluetooth""
 						register "type" = "UPC_TYPE_INTERNAL"
 						register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_H19)"
-						device usb 2.4 on end
+						device ref usb2_port5 on end
 					end
 					chip drivers/usb/acpi
 						register "desc" = ""Integrated Bluetooth""
 						register "type" = "UPC_TYPE_INTERNAL"
 						register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_H19)"
-						device usb 2.7 on end
+						device ref usb2_port8 on end
 					end
 				end
 			end
-		end # USB xHCI
-		device pci 15.0 on
+		end
+		device ref i2c0 on
 			chip drivers/i2c/hid
 				register "generic.hid" = ""SYNA0000""
 				register "generic.cid" = ""ACPI0C50""
@@ -92,7 +92,7 @@ chip soc/intel/jasperlake
 				device i2c 0x2c on end
 			end
 		end
-		device pci 15.2 on
+		device ref i2c2 on
 			chip drivers/i2c/hid
 				register "generic.hid" = ""SIS6496""
 				register "generic.desc" = ""SIS Touchscreen""
@@ -125,8 +125,8 @@ chip soc/intel/jasperlake
 				register "hid_desc_reg_offset" = "0x01"
 				device i2c 0x5d on end
 			end
-		end # I2C 2
-		device pci 15.3 on
+		end
+		device ref i2c3 on
 			chip drivers/i2c/gpiomux/mux
 				register "mux_gpio_count" = "1"
 				register "mux_gpio[0]" = "ACPI_GPIO_OUTPUT(GPP_E5)"
@@ -139,8 +139,8 @@ chip soc/intel/jasperlake
 					end
 				end # I2C MUX
 			end
-		end # I2C 3
-		device pci 19.0 on
+		end
+		device ref i2c4 on
 			chip drivers/i2c/generic
 				register "hid" = ""10EC5682""
 				register "name" = ""RT58""
@@ -165,12 +165,12 @@ chip soc/intel/jasperlake
 				device i2c 29 on end
 			end
 		end
-		device pci 1c.7 on
+		device ref pcie_rp8 on
 			chip drivers/wifi/generic
 				register "wake" = "GPE0_DW2_03"
 				device pci 00.0 on  end
 			end
-		end # PCI Express Root Port 8 - WLAN
-		device pci 1f.3 on end # Intel HDA
+		end
+		device ref hda on end
 	end
 end
diff --git a/src/mainboard/google/dedede/variants/waddledoo/overridetree.cb b/src/mainboard/google/dedede/variants/waddledoo/overridetree.cb
index 8a1d5556c1..9b9d308019 100644
--- a/src/mainboard/google/dedede/variants/waddledoo/overridetree.cb
+++ b/src/mainboard/google/dedede/variants/waddledoo/overridetree.cb
@@ -57,7 +57,7 @@ chip soc/intel/jasperlake
 	register "SerialIoI2cMode[PchSerialIoIndexI2C4]" = "PchSerialIoPci"
 
 	device domain 0 on
-		device pci 05.0 on # IPU - MIPI Camera
+		device ref ipu on
 			chip drivers/intel/mipi_camera
 				register "acpi_uid" = "0x50000"
 				register "acpi_name" = ""IPU0""
@@ -72,9 +72,9 @@ chip soc/intel/jasperlake
 				device generic 0 on end
 			end
 		end
-		device pci 14.0 on
+		device ref south_xhci on
 			chip drivers/usb/acpi
-				device usb 0.0 on
+				device ref xhci_root_hub on
 					chip drivers/usb/acpi
 						register "desc" = ""Discrete Bluetooth""
 						register "type" = "UPC_TYPE_INTERNAL"
@@ -94,8 +94,8 @@ chip soc/intel/jasperlake
 					end
 				end
 			end
-		end # USB xHCI
-		device pci 15.0 on
+		end
+		device ref i2c0 on
 			chip drivers/i2c/generic
 				register "hid" = ""ELAN0000""
 				register "desc" = ""ELAN Touchpad""
@@ -104,8 +104,8 @@ chip soc/intel/jasperlake
 				register "detect" = "1"
 				device i2c 15 on end
 			end
-		end #I2C 0
-		device pci 15.2 on
+		end
+		device ref i2c2 on
 			chip drivers/i2c/hid
 				register "generic.hid" = ""SIS6496""
 				register "generic.desc" = ""SIS Touchscreen""
@@ -143,8 +143,8 @@ chip soc/intel/jasperlake
 				register "hid_desc_reg_offset" = "0x01"
 				device i2c 10 on end
 			end
-		end # I2C 2
-		device pci 15.3 on #I2C #3 CAM0 CAM1 and VCM0
+		end
+		device ref i2c3 on
 			chip drivers/intel/mipi_camera
 				register "acpi_hid" = ""OVTI8856""
 				register "acpi_uid" = "0"
@@ -259,13 +259,13 @@ chip soc/intel/jasperlake
 				device i2c 36 on end
 			end
 		end
-		device pci 1c.7 on
+		device ref pcie_rp8 on
 			chip drivers/wifi/generic
 				register "wake" = "GPE0_DW2_03"
 				device pci 00.0 on  end
 			end
-		end # PCI Express Root Port 8 - WLAN
-		device pci 19.0 on
+		end
+		device ref i2c4 on
 			chip drivers/i2c/da7219
 				register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_D16)"
 				register "btn_cfg" = "50"
@@ -283,13 +283,13 @@ chip soc/intel/jasperlake
 				register "mic_amp_in_sel" = ""diff""
 				device i2c 1a on end
 			end
-		end #I2C 4
-		device pci 1f.3 on
+		end
+		device ref hda on
 			chip drivers/generic/max98357a
 				register "hid" = ""MX98360A""
 				register "sdmode_gpio" =  "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D17)"
 				device generic 0 on end
 			end
-		end # Intel HDA
+		end
 	end
 end

From 5f666a5f688782662c87be3052f113d1f8c7355f Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Sun, 25 Jan 2026 18:35:13 -0600
Subject: [PATCH 3165/3886] mb/google/dedede/var/cret: Drop unused PCIe RP8

CRET uses CNVi WiFi, not discrete, and has nothing attached to this
port, so don't enable it.

TEST=build/boot CRET

Change-Id: Iac9e01c6ecd4f3f32cd1c39a87a10530a36b40a4
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90901
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/google/dedede/variants/cret/overridetree.cb | 1 -
 1 file changed, 1 deletion(-)

diff --git a/src/mainboard/google/dedede/variants/cret/overridetree.cb b/src/mainboard/google/dedede/variants/cret/overridetree.cb
index aaf7321b90..3156c9096f 100644
--- a/src/mainboard/google/dedede/variants/cret/overridetree.cb
+++ b/src/mainboard/google/dedede/variants/cret/overridetree.cb
@@ -234,7 +234,6 @@ chip soc/intel/jasperlake
 				device i2c 40 on end
 			end
 		end
-		device ref pcie_rp8 on end
 		device ref i2c4 on
 			chip drivers/i2c/da7219
 				register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_D16)"

From 438d1b1c1ad23c75279667daa14975c8a6650cec Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Sun, 25 Jan 2026 17:18:02 -0600
Subject: [PATCH 3166/3886] mb/intel/jasperlake_rvp: Use aliases in devicetree
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Convert all PCI device and USB port references in the jasperlake_rvp
devicetree to use device aliases from the Jasperlake chipset.cb instead
of direct device/function numbers. This improves maintainability by
using symbolic names, and reduces file size by eliminating entries
which match those in the chipset devicetree.

Additionally, the p2sb device reference is dropped, as the correct state
(hidden) is set by the chipset devicetree.

TEST=Build jslrvp

Change-Id: I04fd2d1655f08fb0671deeeb55a3e88eb97b7f44
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90902
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 .../variants/jslrvp/devicetree.cb             | 98 +++++++------------
 1 file changed, 38 insertions(+), 60 deletions(-)

diff --git a/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb b/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb
index fadd309dab..4b95f52b36 100644
--- a/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb
+++ b/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb
@@ -195,9 +195,8 @@ chip soc/intel/jasperlake
 	register "xhci_lfps_sampling_offtime_ms" = "9"
 
 	device domain 0 on
-		device pci 00.0 on  end # Host Bridge
-		device pci 02.0 on  end # Integrated Graphics Device
-		device pci 04.0 on
+		device ref igpu on end
+		device ref dptf on
 			chip drivers/intel/dptf
 				register "policies.passive[0]" = "DPTF_PASSIVE(CPU, CPU, 95, 1000)"
 				register "policies.critical[0]" = "DPTF_CRITICAL(CPU, 119, SHUTDOWN)"
@@ -216,9 +215,9 @@ chip soc/intel/jasperlake
 					.granularity = 1000,}"
 				device generic 0 on end
 			end
-		end # SA Thermal device
+		end
 
-		device pci 05.0 on
+		device ref ipu on
 			chip drivers/intel/mipi_camera
 				register "acpi_uid" = "0x50000"
 				register "acpi_name" = ""IPU0""
@@ -233,97 +232,92 @@ chip soc/intel/jasperlake
 				device generic 0 on end
 			end
 		end
-		device pci 12.0 off end # Thermal Subsystem
-		device pci 12.5 off end # UFS SCS
-		device pci 12.6 off end # GSPI #2
-		device pci 14.0 on
+		device ref south_xhci on
 			chip drivers/usb/acpi
 				register "desc" = ""Root Hub""
 				register "type" = "UPC_TYPE_HUB"
-				device usb 0.0 on
+				device ref xhci_root_hub on
 					chip drivers/usb/acpi
 						register "desc" = ""USB3/2 Type-A Left Lower""
 						register "type" = "UPC_TYPE_A"
-						device usb 2.0 on end
+						device ref usb2_port1 on end
 					end
 					chip drivers/usb/acpi
 						register "desc" = ""WWAN""
 						register "type" = "UPC_TYPE_INTERNAL"
-						device usb 2.1 on end
+						device ref usb2_port2 on end
 					end
 					chip drivers/usb/acpi
 						register "desc" = ""Bluetooth""
 						register "type" = "UPC_TYPE_INTERNAL"
-						device usb 2.2 on end
+						device ref usb2_port3 on end
 					end
 					chip drivers/usb/acpi
 						register "desc" = ""USB C Connector 1""
 						register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
-						device usb 2.3 on end
+						device ref usb2_port4 on end
 					end
 					chip drivers/usb/acpi
 						register "desc" = ""USB C Connector 2""
 						register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
-						device usb 2.4 on end
+						device ref usb2_port5 on end
 					end
 					chip drivers/usb/acpi
 						register "desc" = ""USB C Connector 3""
 						register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
-						device usb 2.5 on end
+						device ref usb2_port6 on end
 					end
 					chip drivers/usb/acpi
 						register "desc" = ""USB C Connector 4""
 						register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
-						device usb 2.6 on end
+						device ref usb2_port7 on end
 					end
 					chip drivers/usb/acpi
 						register "desc" = ""USB3/2 Type-A Left Upper""
 						register "type" = "UPC_TYPE_A"
-						device usb 2.7 on end
+						device ref usb2_port8 on end
 					end
 					chip drivers/usb/acpi
 						register "desc" = ""USB3/2 Type-A Left Lower""
 						register "type" = "UPC_TYPE_A"
-						device usb 3.0 on end
+						device ref usb3_port1 on end
 					end
 					chip drivers/usb/acpi
 						register "desc" = ""USB3/2 Type-A Left Upper""
 						register "type" = "UPC_TYPE_A"
-						device usb 3.1 on end
+						device ref usb3_port2 on end
 					end
 					chip drivers/usb/acpi
 						register "desc" = ""WLAN""
 						register "type" = "UPC_TYPE_INTERNAL"
-						device usb 3.2 on end
+						device ref usb3_port3 on end
 					end
 					chip drivers/usb/acpi
 						register "desc" = ""USB3 Port Unused1""
 						register "type" = "UPC_TYPE_INTERNAL"
-						device usb 3.3 on end
+						device ref usb3_port4 on end
 					end
 					chip drivers/usb/acpi
 						register "desc" = ""USB3 Port Unused2""
 						register "type" = "UPC_TYPE_INTERNAL"
-						device usb 3.4 on end
+						device ref usb3_port5 on end
 					end
 					chip drivers/usb/acpi
 						register "desc" = ""USB3 Port Unused3""
 						register "type" = "UPC_TYPE_INTERNAL"
-						device usb 3.5 on end
+						device ref usb3_port6 on end
 					end
 				end
 			end
-		end # USB xHCI
-		device pci 14.1 off end # USB xDCI (OTG)
-		device pci 14.2 off end # PMC SRAM
-		device pci 14.3 on
+		end
+		device ref cnvi_wifi on
 			chip drivers/wifi/generic
 				register "wake" = "GPE0_PME_B0"
 				device generic 0 on end
 			end
-		end # CNVi wifi
-		device pci 14.5 on  end # SDCard
-		device pci 15.0 on
+		end
+		device ref sdxc on end
+		device ref i2c0 on
 			chip drivers/i2c/max98373
 				register "vmon_slot_no" = "4"
 				register "imon_slot_no" = "5"
@@ -357,18 +351,9 @@ chip soc/intel/jasperlake
 				register "mic_amp_in_sel" = ""diff""
 				device i2c 1a on end
 			end
-		end # I2C #0 Audio
-		device pci 15.1 off end # I2C #1
-		device pci 15.2 off end # I2C #2
-		device pci 15.3 off end # I2C #3
-		device pci 16.0 on  end # Management Engine Interface 1
-		device pci 16.1 off end # Management Engine Interface 2
-		device pci 16.2 off end # Management Engine IDE-R
-		device pci 16.3 off end # Management Engine KT Redirection
-		device pci 16.4 off end # Management Engine Interface 3
-		device pci 16.5 off end # Management Engine Interface 4
-		device pci 17.0 off end # SATA
-		device pci 19.0 on # I2C #4 Cam 0
+		end
+		device ref heci1 on end
+		device ref i2c4 on
 			chip drivers/intel/mipi_camera
 				register "acpi_hid" = ""OVTI2740""
 				register "acpi_uid" = "0"
@@ -407,7 +392,7 @@ chip soc/intel/jasperlake
 				device i2c 10 on end
 			end
 		end
-		device pci 19.1 on # I2C #5 Cam 1 and VCM
+		device ref i2c5 on
 			chip drivers/intel/mipi_camera
 				register "acpi_hid" = ""OVTI5675""
 				register "acpi_uid" = "0"
@@ -467,27 +452,20 @@ chip soc/intel/jasperlake
 			end
 		end
 
-		device pci 19.2 on  end # UART #2
-		device pci 1a.0 on  end # eMMC
-		device pci 1c.1 on  end # PCI Express Port 2 - M.2 E-key WLAN
-		device pci 1c.4 on  end # PCI Express Port 5 - NVMe
-		device pci 1e.0 on  end # UART #0
-		device pci 1e.1 off end # UART #1
-		device pci 1e.2 off end # GSPI #0
-		device pci 1e.3 on
+		device ref uart2 on end
+		device ref emmc on end
+		device ref pcie_rp2 on end
+		device ref pcie_rp5 on end
+		device ref uart0 on end
+		device ref gspi1 on
 			chip drivers/spi/acpi
 				register "hid" = "ACPI_DT_NAMESPACE_HID"
 				register "compat_string" = ""google,cr50""
 				register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_H13_IRQ)"
 				device spi 0 on end
 			end
-		end # GSPI #1
-		device pci 1f.0 on  end # eSPI Interface
-		device pci 1f.1 on  end # P2SB
-		device pci 1f.2 hidden end # Power Management Controller
-		device pci 1f.3 on  end # Intel HDA
-		device pci 1f.4 on  end # SMBus
-		device pci 1f.5 on  end # PCH SPI
-		device pci 1f.6 off end # GbE
+		end
+		device ref hda on end
+		device ref smbus on end
 	end
 end

From 6bf998765ccc85f1d99bef6be1ea6ca7740baa81 Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Tue, 27 Jan 2026 20:58:18 +0000
Subject: [PATCH 3167/3886] mb/starlabs/starfighter/mtl: Correct option name to
 control wireless

This board used the older "wireless" option, which no longer exists to
control wireless. Update it to check "wifi".

Change-Id: I8ddec94ea729790c9d13cd54516b8802df0e77aa
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90957
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/starlabs/starfighter/variants/mtl/romstage.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/mainboard/starlabs/starfighter/variants/mtl/romstage.c b/src/mainboard/starlabs/starfighter/variants/mtl/romstage.c
index 486912cbfe..4a50059cd5 100644
--- a/src/mainboard/starlabs/starfighter/variants/mtl/romstage.c
+++ b/src/mainboard/starlabs/starfighter/variants/mtl/romstage.c
@@ -100,7 +100,7 @@ void mainboard_memory_init_params(FSPM_UPD *mupd)
 	mupd->FspmConfig.VtdDisable = !vtd;
 
 	/* Enable/Disable Wireless (RP09) based on CMOS settings */
-	if (get_uint_option("wireless", 1) == 0)
+	if (get_uint_option("wifi", 1) == 0)
 		mupd->FspmConfig.PcieRpEnableMask &= ~(1 << 8);
 
 	/* Enable/Disable Thunderbolt based on CMOS settings */

From 90b819b2793c82a33747aeb883de04d80487e14c Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Tue, 27 Jan 2026 20:59:28 +0000
Subject: [PATCH 3168/3886] mb/starlabs/starfighter/mtl: Add missing control
 for Bluetooth

This board was missing the control of Bluetooth; add it so it
matches all the other Star Labs boards.

Change-Id: I11e39b4c02095b762717ff041a654838fd4c5897
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90958
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/starlabs/starfighter/variants/mtl/devtree.c | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/src/mainboard/starlabs/starfighter/variants/mtl/devtree.c b/src/mainboard/starlabs/starfighter/variants/mtl/devtree.c
index c4b0da67fd..5ac632b4b7 100644
--- a/src/mainboard/starlabs/starfighter/variants/mtl/devtree.c
+++ b/src/mainboard/starlabs/starfighter/variants/mtl/devtree.c
@@ -15,6 +15,10 @@ void devtree_update(void)
 	config_t *cfg = config_of_soc();
 	update_power_limits(cfg);
 
+	/* Enable/Disable Bluetooth based on CMOS settings */
+	if (get_uint_option("bluetooth", 1) == 0)
+		cfg->usb2_ports[9].enable = 0;
+
 	/* Enable/Disable Webcam based on CMOS settings */
 	if (get_uint_option("webcam", 1) == 0)
 		cfg->usb2_ports[CONFIG_CCD_PORT].enable = 0;

From 7ee1bdf9b30bd53e4e3e22e7cf9e0ae1c3bc5aa1 Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Sun, 25 Jan 2026 17:21:56 -0600
Subject: [PATCH 3169/3886] mb/purism/librem_jsl: Use device aliases in
 devicetree

Convert all PCI device and USB port references in the librem_jsl
devicetree to use device aliases from the Jasperlake chipset.cb instead
of direct device/function numbers. This improves maintainability by
using symbolic names, and reduces file size by eliminating entries
which match those in the chipset devicetree.

Additionally, the p2sb device reference is dropped, as the correct state
(hidden) is set by the chipset devicetree.

TEST=Build librem_jsl

Change-Id: Iba2959156ccede68bceb46f8458676bc7a88247a
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90903
Reviewed-by: Jonathon Hall <jonathon.hall@puri.sm>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/purism/librem_jsl/devicetree.cb | 74 ++++++-------------
 1 file changed, 21 insertions(+), 53 deletions(-)

diff --git a/src/mainboard/purism/librem_jsl/devicetree.cb b/src/mainboard/purism/librem_jsl/devicetree.cb
index 82cac1239a..a8528f3459 100644
--- a/src/mainboard/purism/librem_jsl/devicetree.cb
+++ b/src/mainboard/purism/librem_jsl/devicetree.cb
@@ -43,13 +43,10 @@ chip soc/intel/jasperlake
 	register "PchHdaAudioLinkHdaEnable" = "1"
 
 	device domain 0 on
-		device pci 00.0 on  end	# Host Bridge
-		device pci 02.0 on  end	# Integrated Graphics Device
-		device pci 04.0 on  end # SA Thermal device
-		device pci 05.0 on  end	# IPU
-		device pci 09.0 off end	# Intel Trace Hub
-		device pci 12.6 off end	# GSPI 2
-		device pci 14.0 on	# USB xHCI
+		device ref igpu on end
+		device ref dptf on end
+		device ref ipu on end
+		device ref south_xhci on
 			register "usb2_ports[0]" = "USB2_PORT_MID(OC_SKIP)" # Fingerprint reader
 			register "usb2_ports[1]" = "USB2_PORT_MID(OC_SKIP)" # microSD
 			register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # Type-C 1
@@ -64,70 +61,66 @@ chip soc/intel/jasperlake
 			chip drivers/usb/acpi
 				register "desc" = ""Root Hub""
 				register "type" = "UPC_TYPE_HUB"
-				device usb 0.0 on
+				device ref xhci_root_hub on
 					chip drivers/usb/acpi
 						register "desc" = ""Fingerprint Reader""
 						register "type" = "UPC_TYPE_INTERNAL"
-						device usb 2.0 on end
+						device ref usb2_port1 on end
 					end
 					chip drivers/usb/acpi
 						register "desc" = ""microSD Card Reader""
 						register "type" = "UPC_TYPE_INTERNAL"
-						device usb 2.1 on end
+						device ref usb2_port2 on end
 					end
 					chip drivers/usb/acpi
 						register "desc" = ""Type-C Port 1""
 						register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
 						register "group" = "ACPI_PLD_GROUP(0, 0)"
-						device usb 2.2 on end
+						device ref usb2_port3 on end
 					end
 					chip drivers/usb/acpi
 						register "desc" = ""Type-C Port 2""
 						register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
 						register "group" = "ACPI_PLD_GROUP(0, 1)"
-						device usb 2.3 on end
+						device ref usb2_port4 on end
 					end
 					chip drivers/usb/acpi
 						register "desc" = ""Cameras""
 						register "type" = "UPC_TYPE_INTERNAL"
-						device usb 2.5 on end
+						device ref usb2_port6 on end
 					end
 					chip drivers/usb/acpi
 						register "desc" = ""Keyboard Dock""
 						register "type" = "UPC_TYPE_PROPRIETARY"
-						device usb 2.6 on end
+						device ref usb2_port7 on end
 					end
 					chip drivers/usb/acpi
 						register "desc" = ""Bluetooth""
 						register "type" = "UPC_TYPE_INTERNAL"
-						device usb 2.7 on end
+						device ref usb2_port8 on end
 					end
 					chip drivers/usb/acpi
 						register "desc" = ""Type-C Port 2""
 						register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
 						register "group" = "ACPI_PLD_GROUP(0, 1)"
-						device usb 3.0 on end
+						device ref usb3_port1 on end
 					end
 					chip drivers/usb/acpi
 						register "desc" = ""Type-C Port 1""
 						register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
 						register "group" = "ACPI_PLD_GROUP(0, 0)"
-						device usb 3.1 on end
+						device ref usb3_port2 on end
 					end
 				end
 			end
 		end
-		device pci 14.1 off end	# USB xDCI (OTG)
-		device pci 14.2 on  end	# PMC SRAM
-		device pci 14.3 on	# CNVi wifi
+		device ref shared_ram on end
+		device ref cnvi_wifi on
 			chip drivers/wifi/generic
 				device generic 0 on end
 			end
 		end
-		device pci 14.5 off end	# SD card
-		device pci 15.0 off end	# I2C 0
-		device pci 15.1 off end	# I2C 1
-		device pci 15.2 on	# I2C 2
+		device ref i2c2 on
 			chip drivers/i2c/hid
 				register "generic.hid" = ""GXTP7380""
 				register "generic.cid" = ""PNP0C50""
@@ -138,7 +131,7 @@ chip soc/intel/jasperlake
 				device i2c 5d on end
 			end
 		end
-		device pci 15.3 on	# I2C 3
+		device ref i2c3 on
 			chip drivers/i2c/generic
 				register "hid" = ""MXC6655""
 				register "cid" = ""MXC6655""
@@ -147,37 +140,12 @@ chip soc/intel/jasperlake
 				device i2c 15 on end
 			end
 		end
-		device pci 16.0 off end	# HECI 1
-		device pci 16.1 off end	# HECI 2
-		device pci 16.4 off end	# HECI 3
-		device pci 16.5 off end	# HECI 4
-		device pci 17.0 off end	# SATA
-		device pci 19.0 on  end	# I2C 4
-		device pci 19.1 off end	# I2C 5
-		device pci 19.2 off end	# UART 2
-		device pci 1a.0 off end	# eMMC
-		device pci 1c.0 off end	# PCI Express Root Port 1
-		device pci 1c.1 off end	# PCI Express Root Port 2
-		device pci 1c.2 on	# PCI Express Root Port 3 - M.2 M-key, PCIe only
+		device ref i2c4 on end
+		device ref pcie_rp3 on
 			register "PcieClkSrcUsage[0]" = "2"
 			register "PcieClkSrcClkReq[0]" = "0"
 			smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M.2/M 2280" "SlotDataBusWidth2X"
 		end
-		device pci 1c.3 off end	# PCI Express Root Port 4
-		device pci 1c.4 off end	# PCI Express Root Port 5
-		device pci 1c.5 off end	# PCI Express Root Port 6
-		device pci 1c.6 off end	# PCI Express Root Port 7
-		device pci 1c.7 off end	# PCI Express Root Port 8
-		device pci 1e.0 off end	# UART 0
-		device pci 1e.1 off end	# UART 1
-		device pci 1e.2 off end	# GSPI 0
-		device pci 1e.3 off end	# GSPI 1
-		device pci 1f.0 on  end	# eSPI Interface
-		device pci 1f.1 off end	# P2SB
-		device pci 1f.2 hidden end	# Power Management Controller
-		device pci 1f.3 on  end	# Intel HDA/cAVS
-		device pci 1f.4 off end	# SMBus
-		device pci 1f.5 on  end	# PCH SPI
-		device pci 1f.7 off end	# Intel Trace Hub
+		device ref hda on end
 	end
 end

From a1ef551f4a71d83c824bf2a02dbda126861ecb50 Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Sun, 25 Jan 2026 15:26:47 -0600
Subject: [PATCH 3170/3886] soc/intel: Use chipset.cb for PCIe root port ops
 linking
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Move PCIe root port operations linking from PCI Device ID matching
to chipset.cb files for all Intel SoCs that have them, matching the
approach used by Skylake.

Remove corresponding DIDs from pcie.c for these SoCs; keep DID
matching only for SoCs without chipset.cb files. Some of these
will be removed/cleaned up in subsequent patches.

This standardizes the approach across Intel SoCs and makes the
PCIe root port configuration explicit in devicetree, and prevents
the endless proliferation of DIDs in the common PCIe driver code.

Change-Id: I8586b6efb8dbe164bc2a1d68b7131ffa22b00001
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90905
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-by: Jakub "Kuba" Czapiga <czapiga@google.com>
---
 src/soc/intel/alderlake/chipset.cb        |  24 +-
 src/soc/intel/alderlake/chipset_pch_s.cb  |  56 ++--
 src/soc/intel/apollolake/chipset_apl.cb   |  12 +-
 src/soc/intel/apollolake/chipset_glk.cb   |  12 +-
 src/soc/intel/cannonlake/chipset.cb       |  32 +--
 src/soc/intel/cannonlake/chipset_pch_h.cb |  48 ++--
 src/soc/intel/common/block/pcie/pcie.c    | 331 ----------------------
 src/soc/intel/jasperlake/chipset.cb       |  16 +-
 src/soc/intel/meteorlake/chipset.cb       |  24 +-
 src/soc/intel/pantherlake/chipset_ptl.cb  |  24 +-
 src/soc/intel/pantherlake/chipset_wcl.cb  |  12 +-
 src/soc/intel/tigerlake/chipset.cb        |  24 +-
 src/soc/intel/tigerlake/chipset_pch_h.cb  |  48 ++--
 13 files changed, 166 insertions(+), 497 deletions(-)

diff --git a/src/soc/intel/alderlake/chipset.cb b/src/soc/intel/alderlake/chipset.cb
index 355ef2e6e2..e2b4570a6b 100644
--- a/src/soc/intel/alderlake/chipset.cb
+++ b/src/soc/intel/alderlake/chipset.cb
@@ -248,18 +248,18 @@ chip soc/intel/alderlake
 		device pci 19.2 alias uart2 off end
 		# eMMC device is applicable only for ADL-N
 		device pci 1a.0 alias emmc off end
-		device pci 1c.0 alias pcie_rp1 off end
-		device pci 1c.1 alias pcie_rp2 off end
-		device pci 1c.2 alias pcie_rp3 off end
-		device pci 1c.3 alias pcie_rp4 off end
-		device pci 1c.4 alias pcie_rp5 off end
-		device pci 1c.5 alias pcie_rp6 off end
-		device pci 1c.6 alias pcie_rp7 off end
-		device pci 1c.7 alias pcie_rp8 off end
-		device pci 1d.0 alias pcie_rp9 off end
-		device pci 1d.1 alias pcie_rp10 off end
-		device pci 1d.2 alias pcie_rp11 off end
-		device pci 1d.3 alias pcie_rp12 off end
+		device pci 1c.0 alias pcie_rp1 off ops pcie_rp_ops end
+		device pci 1c.1 alias pcie_rp2 off ops pcie_rp_ops end
+		device pci 1c.2 alias pcie_rp3 off ops pcie_rp_ops end
+		device pci 1c.3 alias pcie_rp4 off ops pcie_rp_ops end
+		device pci 1c.4 alias pcie_rp5 off ops pcie_rp_ops end
+		device pci 1c.5 alias pcie_rp6 off ops pcie_rp_ops end
+		device pci 1c.6 alias pcie_rp7 off ops pcie_rp_ops end
+		device pci 1c.7 alias pcie_rp8 off ops pcie_rp_ops end
+		device pci 1d.0 alias pcie_rp9 off ops pcie_rp_ops end
+		device pci 1d.1 alias pcie_rp10 off ops pcie_rp_ops end
+		device pci 1d.2 alias pcie_rp11 off ops pcie_rp_ops end
+		device pci 1d.3 alias pcie_rp12 off ops pcie_rp_ops end
 		device pci 1e.0 alias uart0 off end
 		device pci 1e.1 alias uart1 off end
 		device pci 1e.2 alias gspi0 off end
diff --git a/src/soc/intel/alderlake/chipset_pch_s.cb b/src/soc/intel/alderlake/chipset_pch_s.cb
index 6bcfab1f45..06b50f6844 100644
--- a/src/soc/intel/alderlake/chipset_pch_s.cb
+++ b/src/soc/intel/alderlake/chipset_pch_s.cb
@@ -377,34 +377,34 @@ chip soc/intel/alderlake
 		device pci 19.0 alias i2c4 off end
 		device pci 19.1 alias i2c5 off end
 		device pci 19.2 alias uart2 off end
-		device pci 1a.0 alias pcie_rp25 off end
-		device pci 1a.1 alias pcie_rp26 off end
-		device pci 1a.2 alias pcie_rp27 off end
-		device pci 1a.3 alias pcie_rp28 off end
-		device pci 1b.0 alias pcie_rp17 off end
-		device pci 1b.1 alias pcie_rp18 off end
-		device pci 1b.2 alias pcie_rp19 off end
-		device pci 1b.3 alias pcie_rp20 off end
-		device pci 1b.4 alias pcie_rp21 off end
-		device pci 1b.5 alias pcie_rp22 off end
-		device pci 1b.6 alias pcie_rp23 off end
-		device pci 1b.7 alias pcie_rp24 off end
-		device pci 1c.0 alias pcie_rp1 off end
-		device pci 1c.1 alias pcie_rp2 off end
-		device pci 1c.2 alias pcie_rp3 off end
-		device pci 1c.3 alias pcie_rp4 off end
-		device pci 1c.4 alias pcie_rp5 off end
-		device pci 1c.5 alias pcie_rp6 off end
-		device pci 1c.6 alias pcie_rp7 off end
-		device pci 1c.7 alias pcie_rp8 off end
-		device pci 1d.0 alias pcie_rp9 off end
-		device pci 1d.1 alias pcie_rp10 off end
-		device pci 1d.2 alias pcie_rp11 off end
-		device pci 1d.3 alias pcie_rp12 off end
-		device pci 1d.4 alias pcie_rp13 off end
-		device pci 1d.5 alias pcie_rp14 off end
-		device pci 1d.6 alias pcie_rp15 off end
-		device pci 1d.7 alias pcie_rp16 off end
+		device pci 1a.0 alias pcie_rp25 off ops pcie_rp_ops end
+		device pci 1a.1 alias pcie_rp26 off ops pcie_rp_ops end
+		device pci 1a.2 alias pcie_rp27 off ops pcie_rp_ops end
+		device pci 1a.3 alias pcie_rp28 off ops pcie_rp_ops end
+		device pci 1b.0 alias pcie_rp17 off ops pcie_rp_ops end
+		device pci 1b.1 alias pcie_rp18 off ops pcie_rp_ops end
+		device pci 1b.2 alias pcie_rp19 off ops pcie_rp_ops end
+		device pci 1b.3 alias pcie_rp20 off ops pcie_rp_ops end
+		device pci 1b.4 alias pcie_rp21 off ops pcie_rp_ops end
+		device pci 1b.5 alias pcie_rp22 off ops pcie_rp_ops end
+		device pci 1b.6 alias pcie_rp23 off ops pcie_rp_ops end
+		device pci 1b.7 alias pcie_rp24 off ops pcie_rp_ops end
+		device pci 1c.0 alias pcie_rp1 off ops pcie_rp_ops end
+		device pci 1c.1 alias pcie_rp2 off ops pcie_rp_ops end
+		device pci 1c.2 alias pcie_rp3 off ops pcie_rp_ops end
+		device pci 1c.3 alias pcie_rp4 off ops pcie_rp_ops end
+		device pci 1c.4 alias pcie_rp5 off ops pcie_rp_ops end
+		device pci 1c.5 alias pcie_rp6 off ops pcie_rp_ops end
+		device pci 1c.6 alias pcie_rp7 off ops pcie_rp_ops end
+		device pci 1c.7 alias pcie_rp8 off ops pcie_rp_ops end
+		device pci 1d.0 alias pcie_rp9 off ops pcie_rp_ops end
+		device pci 1d.1 alias pcie_rp10 off ops pcie_rp_ops end
+		device pci 1d.2 alias pcie_rp11 off ops pcie_rp_ops end
+		device pci 1d.3 alias pcie_rp12 off ops pcie_rp_ops end
+		device pci 1d.4 alias pcie_rp13 off ops pcie_rp_ops end
+		device pci 1d.5 alias pcie_rp14 off ops pcie_rp_ops end
+		device pci 1d.6 alias pcie_rp15 off ops pcie_rp_ops end
+		device pci 1d.7 alias pcie_rp16 off ops pcie_rp_ops end
 		device pci 1e.0 alias uart0 off end
 		device pci 1e.1 alias uart1 off end
 		device pci 1e.2 alias gspi0 off end
diff --git a/src/soc/intel/apollolake/chipset_apl.cb b/src/soc/intel/apollolake/chipset_apl.cb
index 03a67765ec..a39461d6de 100644
--- a/src/soc/intel/apollolake/chipset_apl.cb
+++ b/src/soc/intel/apollolake/chipset_apl.cb
@@ -16,12 +16,12 @@ chip soc/intel/apollolake
 		device pci 0f.2 alias heci3		off	end # HECI3
 		device pci 11.0 alias ish		off	end # SensorHub
 		device pci 12.0 alias sata		off	end # SATA
-		device pci 13.0 alias pcie_rp01		off	end # PCIE Express Root Port 1
-		device pci 13.1 alias pcie_rp02		off	end # PCIE Express Root Port 2
-		device pci 13.2 alias pcie_rp03		off	end # PCIE Express Root Port 3
-		device pci 13.3 alias pcie_rp04		off	end # PCIE Express Root Port 4
-		device pci 14.0 alias pcie_rp05		off	end # PCIE Express Root Port 5
-		device pci 14.1 alias pcie_rp06		off	end # PCIE Express Root Port 6
+		device pci 13.0 alias pcie_rp01		off ops pcie_rp_ops	end # PCIE Express Root Port 1
+		device pci 13.1 alias pcie_rp02		off ops pcie_rp_ops	end # PCIE Express Root Port 2
+		device pci 13.2 alias pcie_rp03		off ops pcie_rp_ops	end # PCIE Express Root Port 3
+		device pci 13.3 alias pcie_rp04		off ops pcie_rp_ops	end # PCIE Express Root Port 4
+		device pci 14.0 alias pcie_rp05		off ops pcie_rp_ops	end # PCIE Express Root Port 5
+		device pci 14.1 alias pcie_rp06		off ops pcie_rp_ops	end # PCIE Express Root Port 6
 		device pci 15.0 alias xhci		off	end # XHCI
 		device pci 15.1 alias xdci		off	end # XDCI
 		device pci 16.0 alias i2c0		off	end # I2C0
diff --git a/src/soc/intel/apollolake/chipset_glk.cb b/src/soc/intel/apollolake/chipset_glk.cb
index c6f2db1fe1..1fcc37e800 100644
--- a/src/soc/intel/apollolake/chipset_glk.cb
+++ b/src/soc/intel/apollolake/chipset_glk.cb
@@ -17,12 +17,12 @@ chip soc/intel/apollolake
 		device pci 0f.2 alias heci3		off	end # HECI3
 		device pci 11.0 alias ish		off	end # SensorHub
 		device pci 12.0 alias sata		off	end # SATA
-		device pci 13.0 alias pcie_rp01		off	end # PCIE Express Root Port 1
-		device pci 13.1 alias pcie_rp02		off	end # PCIE Express Root Port 2
-		device pci 13.2 alias pcie_rp03		off	end # PCIE Express Root Port 3
-		device pci 13.3 alias pcie_rp04		off	end # PCIE Express Root Port 4
-		device pci 14.0 alias pcie_rp05		off	end # PCIE Express Root Port 5
-		device pci 14.1 alias pcie_rp06		off	end # PCIE Express Root Port 6
+		device pci 13.0 alias pcie_rp01		off ops pcie_rp_ops	end # PCIE Express Root Port 1
+		device pci 13.1 alias pcie_rp02		off ops pcie_rp_ops	end # PCIE Express Root Port 2
+		device pci 13.2 alias pcie_rp03		off ops pcie_rp_ops	end # PCIE Express Root Port 3
+		device pci 13.3 alias pcie_rp04		off ops pcie_rp_ops	end # PCIE Express Root Port 4
+		device pci 14.0 alias pcie_rp05		off ops pcie_rp_ops	end # PCIE Express Root Port 5
+		device pci 14.1 alias pcie_rp06		off ops pcie_rp_ops	end # PCIE Express Root Port 6
 		device pci 15.0 alias xhci		off	end # XHCI
 		device pci 15.1 alias xdci		off	end # XDCI
 		device pci 16.0 alias i2c0		off	end # I2C0
diff --git a/src/soc/intel/cannonlake/chipset.cb b/src/soc/intel/cannonlake/chipset.cb
index b33aadfd32..eb0a0bcb92 100644
--- a/src/soc/intel/cannonlake/chipset.cb
+++ b/src/soc/intel/cannonlake/chipset.cb
@@ -97,22 +97,22 @@ chip soc/intel/cannonlake
 		device pci 19.1 alias i2c5         off	end	# I2C #5
 		device pci 19.2 alias uart2        off	end	# UART #2
 		device pci 1a.0 alias emmc         off	end	# eMMC
-		device pci 1c.0 alias pcie_rp1     off	end	# PCI Express Port 1
-		device pci 1c.1 alias pcie_rp2     off	end	# PCI Express Port 2
-		device pci 1c.2 alias pcie_rp3     off	end	# PCI Express Port 3
-		device pci 1c.3 alias pcie_rp4     off	end	# PCI Express Port 4
-		device pci 1c.4 alias pcie_rp5     off	end	# PCI Express Port 5
-		device pci 1c.5 alias pcie_rp6     off	end	# PCI Express Port 6
-		device pci 1c.6 alias pcie_rp7     off	end	# PCI Express Port 7
-		device pci 1c.7 alias pcie_rp8     off	end	# PCI Express Port 8
-		device pci 1d.0 alias pcie_rp9     off	end	# PCI Express Port 9
-		device pci 1d.1 alias pcie_rp10    off	end	# PCI Express Port 10
-		device pci 1d.2 alias pcie_rp11    off	end	# PCI Express Port 11
-		device pci 1d.3 alias pcie_rp12    off	end	# PCI Express Port 12
-		device pci 1d.4 alias pcie_rp13    off	end	# PCI Express Port 13
-		device pci 1d.5 alias pcie_rp14    off	end	# PCI Express Port 14
-		device pci 1d.6 alias pcie_rp15    off	end	# PCI Express Port 15
-		device pci 1d.7 alias pcie_rp16    off	end	# PCI Express Port 16
+		device pci 1c.0 alias pcie_rp1     off ops pcie_rp_ops	end	# PCI Express Port 1
+		device pci 1c.1 alias pcie_rp2     off ops pcie_rp_ops	end	# PCI Express Port 2
+		device pci 1c.2 alias pcie_rp3     off ops pcie_rp_ops	end	# PCI Express Port 3
+		device pci 1c.3 alias pcie_rp4     off ops pcie_rp_ops	end	# PCI Express Port 4
+		device pci 1c.4 alias pcie_rp5     off ops pcie_rp_ops	end	# PCI Express Port 5
+		device pci 1c.5 alias pcie_rp6     off ops pcie_rp_ops	end	# PCI Express Port 6
+		device pci 1c.6 alias pcie_rp7     off ops pcie_rp_ops	end	# PCI Express Port 7
+		device pci 1c.7 alias pcie_rp8     off ops pcie_rp_ops	end	# PCI Express Port 8
+		device pci 1d.0 alias pcie_rp9     off ops pcie_rp_ops	end	# PCI Express Port 9
+		device pci 1d.1 alias pcie_rp10    off ops pcie_rp_ops	end	# PCI Express Port 10
+		device pci 1d.2 alias pcie_rp11    off ops pcie_rp_ops	end	# PCI Express Port 11
+		device pci 1d.3 alias pcie_rp12    off ops pcie_rp_ops	end	# PCI Express Port 12
+		device pci 1d.4 alias pcie_rp13    off ops pcie_rp_ops	end	# PCI Express Port 13
+		device pci 1d.5 alias pcie_rp14    off ops pcie_rp_ops	end	# PCI Express Port 14
+		device pci 1d.6 alias pcie_rp15    off ops pcie_rp_ops	end	# PCI Express Port 15
+		device pci 1d.7 alias pcie_rp16    off ops pcie_rp_ops	end	# PCI Express Port 16
 		device pci 1e.0 alias uart0        off	end	# UART #0
 		device pci 1e.1 alias uart1        off	end	# UART #1
 		device pci 1e.2 alias gspi0        off	end	# GSPI #0
diff --git a/src/soc/intel/cannonlake/chipset_pch_h.cb b/src/soc/intel/cannonlake/chipset_pch_h.cb
index 3904697b11..fa7660b5af 100644
--- a/src/soc/intel/cannonlake/chipset_pch_h.cb
+++ b/src/soc/intel/cannonlake/chipset_pch_h.cb
@@ -123,30 +123,30 @@ chip soc/intel/cannonlake
 			ops uart_ops
 		end
 		device pci 1a.0 alias emmc         off	end	# eMMC
-		device pci 1b.0 alias pcie_rp17    off	end	# PCI Express Port 17
-		device pci 1b.1 alias pcie_rp18    off	end	# PCI Express Port 18
-		device pci 1b.2 alias pcie_rp19    off	end	# PCI Express Port 19
-		device pci 1b.3 alias pcie_rp20    off	end	# PCI Express Port 20
-		device pci 1b.4 alias pcie_rp21    off	end	# PCI Express Port 21
-		device pci 1b.5 alias pcie_rp22    off	end	# PCI Express Port 22
-		device pci 1b.6 alias pcie_rp23    off	end	# PCI Express Port 23
-		device pci 1b.7 alias pcie_rp24    off	end	# PCI Express Port 24
-		device pci 1c.0 alias pcie_rp1     off	end	# PCI Express Port 1
-		device pci 1c.1 alias pcie_rp2     off	end	# PCI Express Port 2
-		device pci 1c.2 alias pcie_rp3     off	end	# PCI Express Port 3
-		device pci 1c.3 alias pcie_rp4     off	end	# PCI Express Port 4
-		device pci 1c.4 alias pcie_rp5     off	end	# PCI Express Port 5
-		device pci 1c.5 alias pcie_rp6     off	end	# PCI Express Port 6
-		device pci 1c.6 alias pcie_rp7     off	end	# PCI Express Port 7
-		device pci 1c.7 alias pcie_rp8     off	end	# PCI Express Port 8
-		device pci 1d.0 alias pcie_rp9     off	end	# PCI Express Port 9
-		device pci 1d.1 alias pcie_rp10    off	end	# PCI Express Port 10
-		device pci 1d.2 alias pcie_rp11    off	end	# PCI Express Port 11
-		device pci 1d.3 alias pcie_rp12    off	end	# PCI Express Port 12
-		device pci 1d.4 alias pcie_rp13    off	end	# PCI Express Port 13
-		device pci 1d.5 alias pcie_rp14    off	end	# PCI Express Port 14
-		device pci 1d.6 alias pcie_rp15    off	end	# PCI Express Port 15
-		device pci 1d.7 alias pcie_rp16    off	end	# PCI Express Port 16
+		device pci 1b.0 alias pcie_rp17    off ops pcie_rp_ops	end	# PCI Express Port 17
+		device pci 1b.1 alias pcie_rp18    off ops pcie_rp_ops	end	# PCI Express Port 18
+		device pci 1b.2 alias pcie_rp19    off ops pcie_rp_ops	end	# PCI Express Port 19
+		device pci 1b.3 alias pcie_rp20    off ops pcie_rp_ops	end	# PCI Express Port 20
+		device pci 1b.4 alias pcie_rp21    off ops pcie_rp_ops	end	# PCI Express Port 21
+		device pci 1b.5 alias pcie_rp22    off ops pcie_rp_ops	end	# PCI Express Port 22
+		device pci 1b.6 alias pcie_rp23    off ops pcie_rp_ops	end	# PCI Express Port 23
+		device pci 1b.7 alias pcie_rp24    off ops pcie_rp_ops	end	# PCI Express Port 24
+		device pci 1c.0 alias pcie_rp1     off ops pcie_rp_ops	end	# PCI Express Port 1
+		device pci 1c.1 alias pcie_rp2     off ops pcie_rp_ops	end	# PCI Express Port 2
+		device pci 1c.2 alias pcie_rp3     off ops pcie_rp_ops	end	# PCI Express Port 3
+		device pci 1c.3 alias pcie_rp4     off ops pcie_rp_ops	end	# PCI Express Port 4
+		device pci 1c.4 alias pcie_rp5     off ops pcie_rp_ops	end	# PCI Express Port 5
+		device pci 1c.5 alias pcie_rp6     off ops pcie_rp_ops	end	# PCI Express Port 6
+		device pci 1c.6 alias pcie_rp7     off ops pcie_rp_ops	end	# PCI Express Port 7
+		device pci 1c.7 alias pcie_rp8     off ops pcie_rp_ops	end	# PCI Express Port 8
+		device pci 1d.0 alias pcie_rp9     off ops pcie_rp_ops	end	# PCI Express Port 9
+		device pci 1d.1 alias pcie_rp10    off ops pcie_rp_ops	end	# PCI Express Port 10
+		device pci 1d.2 alias pcie_rp11    off ops pcie_rp_ops	end	# PCI Express Port 11
+		device pci 1d.3 alias pcie_rp12    off ops pcie_rp_ops	end	# PCI Express Port 12
+		device pci 1d.4 alias pcie_rp13    off ops pcie_rp_ops	end	# PCI Express Port 13
+		device pci 1d.5 alias pcie_rp14    off ops pcie_rp_ops	end	# PCI Express Port 14
+		device pci 1d.6 alias pcie_rp15    off ops pcie_rp_ops	end	# PCI Express Port 15
+		device pci 1d.7 alias pcie_rp16    off ops pcie_rp_ops	end	# PCI Express Port 16
 		device pci 1e.0 alias uart0        off	end	# UART #0
 		device pci 1e.1 alias uart1        off	end	# UART #1
 		device pci 1e.2 alias gspi0        off	end	# GSPI #0
diff --git a/src/soc/intel/common/block/pcie/pcie.c b/src/soc/intel/common/block/pcie/pcie.c
index 31e70d6edc..ccddb8026f 100644
--- a/src/soc/intel/common/block/pcie/pcie.c
+++ b/src/soc/intel/common/block/pcie/pcie.c
@@ -81,34 +81,6 @@ static const unsigned short pcie_device_ids[] = {
 	PCI_DID_INTEL_NVL_PCIE_RP12,
 	PCI_DID_INTEL_NVL_PCIE_RP13,
 	PCI_DID_INTEL_NVL_PCIE_RP14,
-	PCI_DID_INTEL_WCL_PCIE_RP1,
-	PCI_DID_INTEL_WCL_PCIE_RP2,
-	PCI_DID_INTEL_WCL_PCIE_RP3,
-	PCI_DID_INTEL_WCL_PCIE_RP4,
-	PCI_DID_INTEL_WCL_PCIE_RP5,
-	PCI_DID_INTEL_WCL_PCIE_RP6,
-	PCI_DID_INTEL_PTL_H_PCIE_RP1,
-	PCI_DID_INTEL_PTL_H_PCIE_RP2,
-	PCI_DID_INTEL_PTL_H_PCIE_RP3,
-	PCI_DID_INTEL_PTL_H_PCIE_RP4,
-	PCI_DID_INTEL_PTL_H_PCIE_RP5,
-	PCI_DID_INTEL_PTL_H_PCIE_RP6,
-	PCI_DID_INTEL_PTL_H_PCIE_RP7,
-	PCI_DID_INTEL_PTL_H_PCIE_RP8,
-	PCI_DID_INTEL_PTL_H_PCIE_RP9,
-	PCI_DID_INTEL_PTL_H_PCIE_RP10,
-	PCI_DID_INTEL_PTL_U_H_PCIE_RP1,
-	PCI_DID_INTEL_PTL_U_H_PCIE_RP2,
-	PCI_DID_INTEL_PTL_U_H_PCIE_RP3,
-	PCI_DID_INTEL_PTL_U_H_PCIE_RP4,
-	PCI_DID_INTEL_PTL_U_H_PCIE_RP5,
-	PCI_DID_INTEL_PTL_U_H_PCIE_RP6,
-	PCI_DID_INTEL_PTL_U_H_PCIE_RP7,
-	PCI_DID_INTEL_PTL_U_H_PCIE_RP8,
-	PCI_DID_INTEL_PTL_U_H_PCIE_RP9,
-	PCI_DID_INTEL_PTL_U_H_PCIE_RP10,
-	PCI_DID_INTEL_PTL_U_H_PCIE_RP11,
-	PCI_DID_INTEL_PTL_U_H_PCIE_RP12,
 	PCI_DID_INTEL_LNL_PCIE_RP1,
 	PCI_DID_INTEL_LNL_PCIE_RP2,
 	PCI_DID_INTEL_LNL_PCIE_RP3,
@@ -117,218 +89,6 @@ static const unsigned short pcie_device_ids[] = {
 	PCI_DID_INTEL_LNL_PCIE_RP6,
 	PCI_DID_INTEL_LNL_PCIE_RP7,
 	PCI_DID_INTEL_LNL_PCIE_RP8,
-	PCI_DID_INTEL_RPL_P_PCIE_RP1,
-	PCI_DID_INTEL_RPL_P_PCIE_RP2,
-	PCI_DID_INTEL_RPL_P_PCIE_RP3,
-	PCI_DID_INTEL_RPL_P_PCIE_RP4,
-	PCI_DID_INTEL_MTL_SOC_PCIE_RP1,
-	PCI_DID_INTEL_MTL_SOC_PCIE_RP2,
-	PCI_DID_INTEL_MTL_SOC_PCIE_RP3,
-	PCI_DID_INTEL_MTL_SOC_PCIE_RP4,
-	PCI_DID_INTEL_MTL_SOC_PCIE_RP5,
-	PCI_DID_INTEL_MTL_SOC_PCIE_RP6,
-	PCI_DID_INTEL_MTL_SOC_PCIE_RP7,
-	PCI_DID_INTEL_MTL_SOC_PCIE_RP8,
-	PCI_DID_INTEL_MTL_SOC_PCIE_RP9,
-	PCI_DID_INTEL_MTL_IOE_P_PCIE_RP10,
-	PCI_DID_INTEL_MTL_IOE_P_PCIE_RP11,
-	PCI_DID_INTEL_MTL_IOE_P_PCIE_RP12,
-	PCI_DID_INTEL_ARL_SOC_PCIE_RP1,
-	PCI_DID_INTEL_ARL_SOC_PCIE_RP2,
-	PCI_DID_INTEL_ARL_SOC_PCIE_RP3,
-	PCI_DID_INTEL_ARL_SOC_PCIE_RP4,
-	PCI_DID_INTEL_ARL_SOC_PCIE_RP5,
-	PCI_DID_INTEL_ARL_SOC_PCIE_RP6,
-	PCI_DID_INTEL_ARL_SOC_PCIE_RP7,
-	PCI_DID_INTEL_ARL_SOC_PCIE_RP8,
-	PCI_DID_INTEL_ARL_SOC_PCIE_RP9,
-	PCI_DID_INTEL_ARL_S_PCIE_RP13,
-	PCI_DID_INTEL_ARL_S_PCIE_RP14,
-	PCI_DID_INTEL_ARL_S_PCIE_RP15,
-	PCI_DID_INTEL_ARP_S_PCIE_RP1,
-	PCI_DID_INTEL_ARP_S_PCIE_RP2,
-	PCI_DID_INTEL_ARP_S_PCIE_RP3,
-	PCI_DID_INTEL_ARP_S_PCIE_RP4,
-	PCI_DID_INTEL_ARP_S_PCIE_RP5,
-	PCI_DID_INTEL_ARP_S_PCIE_RP6,
-	PCI_DID_INTEL_ARP_S_PCIE_RP7,
-	PCI_DID_INTEL_ARP_S_PCIE_RP8,
-	PCI_DID_INTEL_ARP_S_PCIE_RP9,
-	PCI_DID_INTEL_ARP_S_PCIE_RP10,
-	PCI_DID_INTEL_ARP_S_PCIE_RP11,
-	PCI_DID_INTEL_ARP_S_PCIE_RP12,
-	PCI_DID_INTEL_ARP_S_PCIE_RP13,
-	PCI_DID_INTEL_ARP_S_PCIE_RP14,
-	PCI_DID_INTEL_ARP_S_PCIE_RP15,
-	PCI_DID_INTEL_ARP_S_PCIE_RP16,
-	PCI_DID_INTEL_ARP_S_PCIE_RP17,
-	PCI_DID_INTEL_ARP_S_PCIE_RP18,
-	PCI_DID_INTEL_ARP_S_PCIE_RP19,
-	PCI_DID_INTEL_ARP_S_PCIE_RP20,
-	PCI_DID_INTEL_ARP_S_PCIE_RP21,
-	PCI_DID_INTEL_ARP_S_PCIE_RP22,
-	PCI_DID_INTEL_ARP_S_PCIE_RP23,
-	PCI_DID_INTEL_ARP_S_PCIE_RP24,
-	PCI_DID_INTEL_LWB_PCIE_RP1,
-	PCI_DID_INTEL_LWB_PCIE_RP2,
-	PCI_DID_INTEL_LWB_PCIE_RP3,
-	PCI_DID_INTEL_LWB_PCIE_RP4,
-	PCI_DID_INTEL_LWB_PCIE_RP5,
-	PCI_DID_INTEL_LWB_PCIE_RP6,
-	PCI_DID_INTEL_LWB_PCIE_RP7,
-	PCI_DID_INTEL_LWB_PCIE_RP8,
-	PCI_DID_INTEL_LWB_PCIE_RP9,
-	PCI_DID_INTEL_LWB_PCIE_RP10,
-	PCI_DID_INTEL_LWB_PCIE_RP11,
-	PCI_DID_INTEL_LWB_PCIE_RP12,
-	PCI_DID_INTEL_LWB_PCIE_RP13,
-	PCI_DID_INTEL_LWB_PCIE_RP14,
-	PCI_DID_INTEL_LWB_PCIE_RP15,
-	PCI_DID_INTEL_LWB_PCIE_RP16,
-	PCI_DID_INTEL_LWB_PCIE_RP17,
-	PCI_DID_INTEL_LWB_PCIE_RP18,
-	PCI_DID_INTEL_LWB_PCIE_RP19,
-	PCI_DID_INTEL_LWB_PCIE_RP20,
-	PCI_DID_INTEL_LWB_PCIE_RP1_SUPER,
-	PCI_DID_INTEL_LWB_PCIE_RP2_SUPER,
-	PCI_DID_INTEL_LWB_PCIE_RP3_SUPER,
-	PCI_DID_INTEL_LWB_PCIE_RP4_SUPER,
-	PCI_DID_INTEL_LWB_PCIE_RP5_SUPER,
-	PCI_DID_INTEL_LWB_PCIE_RP6_SUPER,
-	PCI_DID_INTEL_LWB_PCIE_RP7_SUPER,
-	PCI_DID_INTEL_LWB_PCIE_RP8_SUPER,
-	PCI_DID_INTEL_LWB_PCIE_RP9_SUPER,
-	PCI_DID_INTEL_LWB_PCIE_RP10_SUPER,
-	PCI_DID_INTEL_LWB_PCIE_RP11_SUPER,
-	PCI_DID_INTEL_LWB_PCIE_RP12_SUPER,
-	PCI_DID_INTEL_LWB_PCIE_RP13_SUPER,
-	PCI_DID_INTEL_LWB_PCIE_RP14_SUPER,
-	PCI_DID_INTEL_LWB_PCIE_RP15_SUPER,
-	PCI_DID_INTEL_LWB_PCIE_RP16_SUPER,
-	PCI_DID_INTEL_LWB_PCIE_RP17_SUPER,
-	PCI_DID_INTEL_LWB_PCIE_RP18_SUPER,
-	PCI_DID_INTEL_LWB_PCIE_RP19_SUPER,
-	PCI_DID_INTEL_LWB_PCIE_RP20_SUPER,
-	PCI_DID_INTEL_CNL_LP_PCIE_RP1,
-	PCI_DID_INTEL_CNL_LP_PCIE_RP2,
-	PCI_DID_INTEL_CNL_LP_PCIE_RP3,
-	PCI_DID_INTEL_CNL_LP_PCIE_RP4,
-	PCI_DID_INTEL_CNL_LP_PCIE_RP5,
-	PCI_DID_INTEL_CNL_LP_PCIE_RP6,
-	PCI_DID_INTEL_CNL_LP_PCIE_RP7,
-	PCI_DID_INTEL_CNL_LP_PCIE_RP8,
-	PCI_DID_INTEL_CNL_LP_PCIE_RP9,
-	PCI_DID_INTEL_CNL_LP_PCIE_RP10,
-	PCI_DID_INTEL_CNL_LP_PCIE_RP11,
-	PCI_DID_INTEL_CNL_LP_PCIE_RP12,
-	PCI_DID_INTEL_CNL_LP_PCIE_RP13,
-	PCI_DID_INTEL_CNL_LP_PCIE_RP14,
-	PCI_DID_INTEL_CNL_LP_PCIE_RP15,
-	PCI_DID_INTEL_CNL_LP_PCIE_RP16,
-	PCI_DID_INTEL_CNP_H_PCIE_RP1,
-	PCI_DID_INTEL_CNP_H_PCIE_RP2,
-	PCI_DID_INTEL_CNP_H_PCIE_RP3,
-	PCI_DID_INTEL_CNP_H_PCIE_RP4,
-	PCI_DID_INTEL_CNP_H_PCIE_RP5,
-	PCI_DID_INTEL_CNP_H_PCIE_RP6,
-	PCI_DID_INTEL_CNP_H_PCIE_RP7,
-	PCI_DID_INTEL_CNP_H_PCIE_RP8,
-	PCI_DID_INTEL_CNP_H_PCIE_RP9,
-	PCI_DID_INTEL_CNP_H_PCIE_RP10,
-	PCI_DID_INTEL_CNP_H_PCIE_RP11,
-	PCI_DID_INTEL_CNP_H_PCIE_RP12,
-	PCI_DID_INTEL_CNP_H_PCIE_RP13,
-	PCI_DID_INTEL_CNP_H_PCIE_RP14,
-	PCI_DID_INTEL_CNP_H_PCIE_RP15,
-	PCI_DID_INTEL_CNP_H_PCIE_RP16,
-	PCI_DID_INTEL_CNP_H_PCIE_RP17,
-	PCI_DID_INTEL_CNP_H_PCIE_RP18,
-	PCI_DID_INTEL_CNP_H_PCIE_RP19,
-	PCI_DID_INTEL_CNP_H_PCIE_RP20,
-	PCI_DID_INTEL_CNP_H_PCIE_RP21,
-	PCI_DID_INTEL_CNP_H_PCIE_RP22,
-	PCI_DID_INTEL_CNP_H_PCIE_RP23,
-	PCI_DID_INTEL_CNP_H_PCIE_RP24,
-	PCI_DID_INTEL_CMP_LP_PCIE_RP1,
-	PCI_DID_INTEL_CMP_LP_PCIE_RP2,
-	PCI_DID_INTEL_CMP_LP_PCIE_RP3,
-	PCI_DID_INTEL_CMP_LP_PCIE_RP4,
-	PCI_DID_INTEL_CMP_LP_PCIE_RP5,
-	PCI_DID_INTEL_CMP_LP_PCIE_RP6,
-	PCI_DID_INTEL_CMP_LP_PCIE_RP7,
-	PCI_DID_INTEL_CMP_LP_PCIE_RP8,
-	PCI_DID_INTEL_CMP_LP_PCIE_RP9,
-	PCI_DID_INTEL_CMP_LP_PCIE_RP10,
-	PCI_DID_INTEL_CMP_LP_PCIE_RP11,
-	PCI_DID_INTEL_CMP_LP_PCIE_RP12,
-	PCI_DID_INTEL_CMP_LP_PCIE_RP13,
-	PCI_DID_INTEL_CMP_LP_PCIE_RP14,
-	PCI_DID_INTEL_CMP_LP_PCIE_RP15,
-	PCI_DID_INTEL_CMP_LP_PCIE_RP16,
-	PCI_DID_INTEL_CMP_H_PCIE_RP1,
-	PCI_DID_INTEL_CMP_H_PCIE_RP2,
-	PCI_DID_INTEL_CMP_H_PCIE_RP3,
-	PCI_DID_INTEL_CMP_H_PCIE_RP4,
-	PCI_DID_INTEL_CMP_H_PCIE_RP5,
-	PCI_DID_INTEL_CMP_H_PCIE_RP6,
-	PCI_DID_INTEL_CMP_H_PCIE_RP7,
-	PCI_DID_INTEL_CMP_H_PCIE_RP8,
-	PCI_DID_INTEL_CMP_H_PCIE_RP9,
-	PCI_DID_INTEL_CMP_H_PCIE_RP10,
-	PCI_DID_INTEL_CMP_H_PCIE_RP11,
-	PCI_DID_INTEL_CMP_H_PCIE_RP12,
-	PCI_DID_INTEL_CMP_H_PCIE_RP13,
-	PCI_DID_INTEL_CMP_H_PCIE_RP14,
-	PCI_DID_INTEL_CMP_H_PCIE_RP15,
-	PCI_DID_INTEL_CMP_H_PCIE_RP16,
-	PCI_DID_INTEL_CMP_H_PCIE_RP17,
-	PCI_DID_INTEL_CMP_H_PCIE_RP18,
-	PCI_DID_INTEL_CMP_H_PCIE_RP19,
-	PCI_DID_INTEL_CMP_H_PCIE_RP20,
-	PCI_DID_INTEL_CMP_H_PCIE_RP21,
-	PCI_DID_INTEL_CMP_H_PCIE_RP22,
-	PCI_DID_INTEL_CMP_H_PCIE_RP23,
-	PCI_DID_INTEL_CMP_H_PCIE_RP24,
-	PCI_DID_INTEL_TGP_LP_PCIE_RP1,
-	PCI_DID_INTEL_TGP_LP_PCIE_RP2,
-	PCI_DID_INTEL_TGP_LP_PCIE_RP3,
-	PCI_DID_INTEL_TGP_LP_PCIE_RP4,
-	PCI_DID_INTEL_TGP_LP_PCIE_RP5,
-	PCI_DID_INTEL_TGP_LP_PCIE_RP6,
-	PCI_DID_INTEL_TGP_LP_PCIE_RP7,
-	PCI_DID_INTEL_TGP_LP_PCIE_RP8,
-	PCI_DID_INTEL_TGP_LP_PCIE_RP9,
-	PCI_DID_INTEL_TGP_LP_PCIE_RP10,
-	PCI_DID_INTEL_TGP_LP_PCIE_RP11,
-	PCI_DID_INTEL_TGP_LP_PCIE_RP12,
-	PCI_DID_INTEL_TGP_LP_PCIE_RP13,
-	PCI_DID_INTEL_TGP_LP_PCIE_RP14,
-	PCI_DID_INTEL_TGP_LP_PCIE_RP15,
-	PCI_DID_INTEL_TGP_LP_PCIE_RP16,
-	PCI_DID_INTEL_TGP_H_PCIE_RP1,
-	PCI_DID_INTEL_TGP_H_PCIE_RP2,
-	PCI_DID_INTEL_TGP_H_PCIE_RP3,
-	PCI_DID_INTEL_TGP_H_PCIE_RP4,
-	PCI_DID_INTEL_TGP_H_PCIE_RP5,
-	PCI_DID_INTEL_TGP_H_PCIE_RP6,
-	PCI_DID_INTEL_TGP_H_PCIE_RP7,
-	PCI_DID_INTEL_TGP_H_PCIE_RP8,
-	PCI_DID_INTEL_TGP_H_PCIE_RP9,
-	PCI_DID_INTEL_TGP_H_PCIE_RP10,
-	PCI_DID_INTEL_TGP_H_PCIE_RP11,
-	PCI_DID_INTEL_TGP_H_PCIE_RP12,
-	PCI_DID_INTEL_TGP_H_PCIE_RP13,
-	PCI_DID_INTEL_TGP_H_PCIE_RP14,
-	PCI_DID_INTEL_TGP_H_PCIE_RP15,
-	PCI_DID_INTEL_TGP_H_PCIE_RP16,
-	PCI_DID_INTEL_TGP_H_PCIE_RP17,
-	PCI_DID_INTEL_TGP_H_PCIE_RP18,
-	PCI_DID_INTEL_TGP_H_PCIE_RP19,
-	PCI_DID_INTEL_TGP_H_PCIE_RP20,
-	PCI_DID_INTEL_TGP_H_PCIE_RP21,
-	PCI_DID_INTEL_TGP_H_PCIE_RP22,
-	PCI_DID_INTEL_TGP_H_PCIE_RP23,
-	PCI_DID_INTEL_TGP_H_PCIE_RP24,
 	PCI_DID_INTEL_MCC_PCIE_RP1,
 	PCI_DID_INTEL_MCC_PCIE_RP2,
 	PCI_DID_INTEL_MCC_PCIE_RP3,
@@ -336,97 +96,6 @@ static const unsigned short pcie_device_ids[] = {
 	PCI_DID_INTEL_MCC_PCIE_RP5,
 	PCI_DID_INTEL_MCC_PCIE_RP6,
 	PCI_DID_INTEL_MCC_PCIE_RP7,
-	PCI_DID_INTEL_JSP_PCIE_RP1,
-	PCI_DID_INTEL_JSP_PCIE_RP2,
-	PCI_DID_INTEL_JSP_PCIE_RP3,
-	PCI_DID_INTEL_JSP_PCIE_RP4,
-	PCI_DID_INTEL_JSP_PCIE_RP5,
-	PCI_DID_INTEL_JSP_PCIE_RP6,
-	PCI_DID_INTEL_JSP_PCIE_RP7,
-	PCI_DID_INTEL_JSP_PCIE_RP8,
-	PCI_DID_INTEL_ADL_P_PCIE_RP1,
-	PCI_DID_INTEL_ADL_P_PCIE_RP2,
-	PCI_DID_INTEL_ADL_P_PCIE_RP3,
-	PCI_DID_INTEL_ADP_P_PCIE_RP1,
-	PCI_DID_INTEL_ADP_P_PCIE_RP2,
-	PCI_DID_INTEL_ADP_P_PCIE_RP3,
-	PCI_DID_INTEL_ADP_P_PCIE_RP4,
-	PCI_DID_INTEL_ADP_P_PCIE_RP5,
-	PCI_DID_INTEL_ADP_P_PCIE_RP6,
-	PCI_DID_INTEL_ADP_P_PCIE_RP7,
-	PCI_DID_INTEL_ADP_P_PCIE_RP8,
-	PCI_DID_INTEL_ADP_P_PCIE_RP9,
-	PCI_DID_INTEL_ADP_P_PCIE_RP10,
-	PCI_DID_INTEL_ADP_P_PCIE_RP11,
-	PCI_DID_INTEL_ADP_P_PCIE_RP12,
-	PCI_DID_INTEL_ADP_S_PCIE_RP1,
-	PCI_DID_INTEL_ADP_S_PCIE_RP2,
-	PCI_DID_INTEL_ADP_S_PCIE_RP3,
-	PCI_DID_INTEL_ADP_S_PCIE_RP4,
-	PCI_DID_INTEL_ADP_S_PCIE_RP5,
-	PCI_DID_INTEL_ADP_S_PCIE_RP6,
-	PCI_DID_INTEL_ADP_S_PCIE_RP7,
-	PCI_DID_INTEL_ADP_S_PCIE_RP8,
-	PCI_DID_INTEL_ADP_S_PCIE_RP9,
-	PCI_DID_INTEL_ADP_S_PCIE_RP10,
-	PCI_DID_INTEL_ADP_S_PCIE_RP11,
-	PCI_DID_INTEL_ADP_S_PCIE_RP12,
-	PCI_DID_INTEL_ADP_S_PCIE_RP13,
-	PCI_DID_INTEL_ADP_S_PCIE_RP14,
-	PCI_DID_INTEL_ADP_S_PCIE_RP15,
-	PCI_DID_INTEL_ADP_S_PCIE_RP16,
-	PCI_DID_INTEL_ADP_S_PCIE_RP17,
-	PCI_DID_INTEL_ADP_S_PCIE_RP18,
-	PCI_DID_INTEL_ADP_S_PCIE_RP19,
-	PCI_DID_INTEL_ADP_S_PCIE_RP20,
-	PCI_DID_INTEL_ADP_S_PCIE_RP21,
-	PCI_DID_INTEL_ADP_S_PCIE_RP22,
-	PCI_DID_INTEL_ADP_S_PCIE_RP23,
-	PCI_DID_INTEL_ADP_S_PCIE_RP24,
-	PCI_DID_INTEL_ADP_S_PCIE_RP25,
-	PCI_DID_INTEL_ADP_S_PCIE_RP26,
-	PCI_DID_INTEL_ADP_S_PCIE_RP27,
-	PCI_DID_INTEL_ADP_S_PCIE_RP28,
-	PCI_DID_INTEL_ADP_M_N_PCIE_RP1,
-	PCI_DID_INTEL_ADP_M_N_PCIE_RP2,
-	PCI_DID_INTEL_ADP_M_N_PCIE_RP3,
-	PCI_DID_INTEL_ADP_M_N_PCIE_RP4,
-	PCI_DID_INTEL_ADP_M_PCIE_RP5,
-	PCI_DID_INTEL_ADP_M_PCIE_RP6,
-	PCI_DID_INTEL_ADP_M_N_PCIE_RP7,
-	PCI_DID_INTEL_ADP_M_PCIE_RP8,
-	PCI_DID_INTEL_ADP_M_N_PCIE_RP9,
-	PCI_DID_INTEL_ADP_M_N_PCIE_RP10,
-	PCI_DID_INTEL_ADP_N_PCIE_RP11,
-	PCI_DID_INTEL_ADP_N_PCIE_RP12,
-	PCI_DID_INTEL_RPP_S_PCIE_RP1,
-	PCI_DID_INTEL_RPP_S_PCIE_RP2,
-	PCI_DID_INTEL_RPP_S_PCIE_RP3,
-	PCI_DID_INTEL_RPP_S_PCIE_RP4,
-	PCI_DID_INTEL_RPP_S_PCIE_RP5,
-	PCI_DID_INTEL_RPP_S_PCIE_RP6,
-	PCI_DID_INTEL_RPP_S_PCIE_RP7,
-	PCI_DID_INTEL_RPP_S_PCIE_RP8,
-	PCI_DID_INTEL_RPP_S_PCIE_RP9,
-	PCI_DID_INTEL_RPP_S_PCIE_RP10,
-	PCI_DID_INTEL_RPP_S_PCIE_RP11,
-	PCI_DID_INTEL_RPP_S_PCIE_RP12,
-	PCI_DID_INTEL_RPP_S_PCIE_RP13,
-	PCI_DID_INTEL_RPP_S_PCIE_RP14,
-	PCI_DID_INTEL_RPP_S_PCIE_RP15,
-	PCI_DID_INTEL_RPP_S_PCIE_RP16,
-	PCI_DID_INTEL_RPP_S_PCIE_RP17,
-	PCI_DID_INTEL_RPP_S_PCIE_RP18,
-	PCI_DID_INTEL_RPP_S_PCIE_RP19,
-	PCI_DID_INTEL_RPP_S_PCIE_RP20,
-	PCI_DID_INTEL_RPP_S_PCIE_RP21,
-	PCI_DID_INTEL_RPP_S_PCIE_RP22,
-	PCI_DID_INTEL_RPP_S_PCIE_RP23,
-	PCI_DID_INTEL_RPP_S_PCIE_RP24,
-	PCI_DID_INTEL_RPP_S_PCIE_RP25,
-	PCI_DID_INTEL_RPP_S_PCIE_RP26,
-	PCI_DID_INTEL_RPP_S_PCIE_RP27,
-	PCI_DID_INTEL_RPP_S_PCIE_RP28,
 	0
 };
 
diff --git a/src/soc/intel/jasperlake/chipset.cb b/src/soc/intel/jasperlake/chipset.cb
index f713d22595..aa25ff5e8e 100644
--- a/src/soc/intel/jasperlake/chipset.cb
+++ b/src/soc/intel/jasperlake/chipset.cb
@@ -77,14 +77,14 @@ chip soc/intel/jasperlake
 		device pci 19.1 alias i2c5		off end
 		device pci 19.2 alias uart2		off end
 		device pci 1a.0 alias emmc		off end
-		device pci 1c.0 alias pcie_rp1		off end
-		device pci 1c.1 alias pcie_rp2		off end
-		device pci 1c.2 alias pcie_rp3		off end
-		device pci 1c.3 alias pcie_rp4		off end
-		device pci 1c.4 alias pcie_rp5		off end
-		device pci 1c.5 alias pcie_rp6		off end
-		device pci 1c.6 alias pcie_rp7		off end
-		device pci 1c.7 alias pcie_rp8		off end
+		device pci 1c.0 alias pcie_rp1		off ops pcie_rp_ops end
+		device pci 1c.1 alias pcie_rp2		off ops pcie_rp_ops end
+		device pci 1c.2 alias pcie_rp3		off ops pcie_rp_ops end
+		device pci 1c.3 alias pcie_rp4		off ops pcie_rp_ops end
+		device pci 1c.4 alias pcie_rp5		off ops pcie_rp_ops end
+		device pci 1c.5 alias pcie_rp6		off ops pcie_rp_ops end
+		device pci 1c.6 alias pcie_rp7		off ops pcie_rp_ops end
+		device pci 1c.7 alias pcie_rp8		off ops pcie_rp_ops end
 		device pci 1e.0 alias uart0		off end
 		device pci 1e.1 alias uart1		off end
 		device pci 1e.2 alias gspi0		off end
diff --git a/src/soc/intel/meteorlake/chipset.cb b/src/soc/intel/meteorlake/chipset.cb
index 7b26670ff8..6851b5769f 100644
--- a/src/soc/intel/meteorlake/chipset.cb
+++ b/src/soc/intel/meteorlake/chipset.cb
@@ -31,13 +31,13 @@ chip soc/intel/meteorlake
 
 	device domain 0 on
 		device pci 00.0 alias system_agent on end
-		device pci 01.0 alias pcie_rp12 off end
+		device pci 01.0 alias pcie_rp12 off ops pcie_rp_ops end
 		device pci 02.0 alias igpu off end
 		device pci 04.0 alias dtt off end
 		device pci 05.0 alias ipu off end
-		device pci 06.0 alias pcie_rp9 off end
-		device pci 06.1 alias pcie_rp10 off end
-		device pci 06.2 alias pcie_rp11 off end
+		device pci 06.0 alias pcie_rp9 off ops pcie_rp_ops end
+		device pci 06.1 alias pcie_rp10 off ops pcie_rp_ops end
+		device pci 06.2 alias pcie_rp11 off ops pcie_rp_ops end
 		device pci 07.0 alias tbt_pcie_rp0 off
 			chip soc/intel/common/block/usb4
 				use tcss_dma0 as usb4_port
@@ -169,14 +169,14 @@ chip soc/intel/meteorlake
 		device pci 19.0 alias i2c4 off end
 		device pci 19.1 alias i2c5 off end
 		device pci 19.2 alias uart2 off end
-		device pci 1c.0 alias pcie_rp1 off end
-		device pci 1c.1 alias pcie_rp2 off end
-		device pci 1c.2 alias pcie_rp3 off end
-		device pci 1c.3 alias pcie_rp4 off end
-		device pci 1c.4 alias pcie_rp5 off end
-		device pci 1c.5 alias pcie_rp6 off end
-		device pci 1c.6 alias pcie_rp7 off end
-		device pci 1c.7 alias pcie_rp8 off end
+		device pci 1c.0 alias pcie_rp1 off ops pcie_rp_ops end
+		device pci 1c.1 alias pcie_rp2 off ops pcie_rp_ops end
+		device pci 1c.2 alias pcie_rp3 off ops pcie_rp_ops end
+		device pci 1c.3 alias pcie_rp4 off ops pcie_rp_ops end
+		device pci 1c.4 alias pcie_rp5 off ops pcie_rp_ops end
+		device pci 1c.5 alias pcie_rp6 off ops pcie_rp_ops end
+		device pci 1c.6 alias pcie_rp7 off ops pcie_rp_ops end
+		device pci 1c.7 alias pcie_rp8 off ops pcie_rp_ops end
 		device pci 1e.0 alias uart0 off end
 		device pci 1e.1 alias uart1 off end
 		device pci 1e.2 alias gspi0 off end
diff --git a/src/soc/intel/pantherlake/chipset_ptl.cb b/src/soc/intel/pantherlake/chipset_ptl.cb
index fb78b88659..31a898182f 100644
--- a/src/soc/intel/pantherlake/chipset_ptl.cb
+++ b/src/soc/intel/pantherlake/chipset_ptl.cb
@@ -112,10 +112,10 @@ chip soc/intel/pantherlake
 		device pci 02.0 alias igpu on end
 		device pci 04.0 alias dtt off end
 		device pci 05.0 alias ipu off end
-		device pci 06.0 alias pcie_rp9 off end
-		device pci 06.1 alias pcie_rp10 off end
-		device pci 06.2 alias pcie_rp11 off end
-		device pci 06.3 alias pcie_rp12 off end
+		device pci 06.0 alias pcie_rp9 off ops pcie_rp_ops end
+		device pci 06.1 alias pcie_rp10 off ops pcie_rp_ops end
+		device pci 06.2 alias pcie_rp11 off ops pcie_rp_ops end
+		device pci 06.3 alias pcie_rp12 off ops pcie_rp_ops end
 		device pci 07.0 alias tbt_pcie_rp0 off
 			chip soc/intel/common/block/usb4
 				use tcss_dma0 as usb4_port
@@ -229,14 +229,14 @@ chip soc/intel/pantherlake
 		device pci 19.0 alias i2c4 off end
 		device pci 19.1 alias i2c5 off end
 		device pci 19.2 alias uart2 off end
-		device pci 1c.0 alias pcie_rp1 off end
-		device pci 1c.1 alias pcie_rp2 off end
-		device pci 1c.2 alias pcie_rp3 off end
-		device pci 1c.3 alias pcie_rp4 off end
-		device pci 1c.4 alias pcie_rp5 off end
-		device pci 1c.5 alias pcie_rp6 off end
-		device pci 1c.6 alias pcie_rp7 off end
-		device pci 1c.7 alias pcie_rp8 off end
+		device pci 1c.0 alias pcie_rp1 off ops pcie_rp_ops end
+		device pci 1c.1 alias pcie_rp2 off ops pcie_rp_ops end
+		device pci 1c.2 alias pcie_rp3 off ops pcie_rp_ops end
+		device pci 1c.3 alias pcie_rp4 off ops pcie_rp_ops end
+		device pci 1c.4 alias pcie_rp5 off ops pcie_rp_ops end
+		device pci 1c.5 alias pcie_rp6 off ops pcie_rp_ops end
+		device pci 1c.6 alias pcie_rp7 off ops pcie_rp_ops end
+		device pci 1c.7 alias pcie_rp8 off ops pcie_rp_ops end
 		device pci 1e.0 alias uart0 off end
 		device pci 1e.1 alias uart1 off end
 		device pci 1e.2 alias gspi0 off end
diff --git a/src/soc/intel/pantherlake/chipset_wcl.cb b/src/soc/intel/pantherlake/chipset_wcl.cb
index 31abe5be94..2236d930e2 100644
--- a/src/soc/intel/pantherlake/chipset_wcl.cb
+++ b/src/soc/intel/pantherlake/chipset_wcl.cb
@@ -20,8 +20,8 @@ chip soc/intel/pantherlake
 		device pci 00.0 alias system_agent on end
 		device pci 02.0 alias igpu on end
 		device pci 04.0 alias dtt off end
-		device pci 06.0 alias pcie_rp5 off end
-		device pci 06.1 alias pcie_rp6 off end
+		device pci 06.0 alias pcie_rp5 off ops pcie_rp_ops end
+		device pci 06.1 alias pcie_rp6 off ops pcie_rp_ops end
 		device pci 07.0 alias tbt_pcie_rp0 off
 			chip soc/intel/common/block/usb4
 				use tcss_dma0 as usb4_port
@@ -116,10 +116,10 @@ chip soc/intel/pantherlake
 		device pci 19.0 alias i2c4 off end
 		device pci 19.1 alias i2c5 off end
 		device pci 19.2 alias uart2 off end
-		device pci 1c.0 alias pcie_rp1 off end
-		device pci 1c.1 alias pcie_rp2 off end
-		device pci 1c.2 alias pcie_rp3 off end
-		device pci 1c.3 alias pcie_rp4 off end
+		device pci 1c.0 alias pcie_rp1 off ops pcie_rp_ops end
+		device pci 1c.1 alias pcie_rp2 off ops pcie_rp_ops end
+		device pci 1c.2 alias pcie_rp3 off ops pcie_rp_ops end
+		device pci 1c.3 alias pcie_rp4 off ops pcie_rp_ops end
 		device pci 1e.0 alias uart0 off end
 		device pci 1e.1 alias uart1 off end
 		device pci 1e.2 alias gspi0 off end
diff --git a/src/soc/intel/tigerlake/chipset.cb b/src/soc/intel/tigerlake/chipset.cb
index f0576ad5e6..bdf0138229 100644
--- a/src/soc/intel/tigerlake/chipset.cb
+++ b/src/soc/intel/tigerlake/chipset.cb
@@ -129,18 +129,18 @@ chip soc/intel/tigerlake
 		device pci 19.0 alias i2c4 off end
 		device pci 19.1 alias i2c5 off end
 		device pci 19.2 alias uart2 off end
-		device pci 1c.0 alias pcie_rp1 off end
-		device pci 1c.1 alias pcie_rp2 off end
-		device pci 1c.2 alias pcie_rp3 off end
-		device pci 1c.3 alias pcie_rp4 off end
-		device pci 1c.4 alias pcie_rp5 off end
-		device pci 1c.5 alias pcie_rp6 off end
-		device pci 1c.6 alias pcie_rp7 off end
-		device pci 1c.7 alias pcie_rp8 off end
-		device pci 1d.0 alias pcie_rp9 off end
-		device pci 1d.1 alias pcie_rp10 off end
-		device pci 1d.2 alias pcie_rp11 off end
-		device pci 1d.3 alias pcie_rp12 off end
+		device pci 1c.0 alias pcie_rp1 off ops pcie_rp_ops end
+		device pci 1c.1 alias pcie_rp2 off ops pcie_rp_ops end
+		device pci 1c.2 alias pcie_rp3 off ops pcie_rp_ops end
+		device pci 1c.3 alias pcie_rp4 off ops pcie_rp_ops end
+		device pci 1c.4 alias pcie_rp5 off ops pcie_rp_ops end
+		device pci 1c.5 alias pcie_rp6 off ops pcie_rp_ops end
+		device pci 1c.6 alias pcie_rp7 off ops pcie_rp_ops end
+		device pci 1c.7 alias pcie_rp8 off ops pcie_rp_ops end
+		device pci 1d.0 alias pcie_rp9 off ops pcie_rp_ops end
+		device pci 1d.1 alias pcie_rp10 off ops pcie_rp_ops end
+		device pci 1d.2 alias pcie_rp11 off ops pcie_rp_ops end
+		device pci 1d.3 alias pcie_rp12 off ops pcie_rp_ops end
 		device pci 1e.0 alias uart0 off end
 		device pci 1e.1 alias uart1 off end
 		device pci 1e.2 alias gspi0 off end
diff --git a/src/soc/intel/tigerlake/chipset_pch_h.cb b/src/soc/intel/tigerlake/chipset_pch_h.cb
index 40f613ff4a..e2c7022546 100644
--- a/src/soc/intel/tigerlake/chipset_pch_h.cb
+++ b/src/soc/intel/tigerlake/chipset_pch_h.cb
@@ -151,30 +151,30 @@ chip soc/intel/tigerlake
 		device pci 19.0 alias i2c4 off end
 		device pci 19.1 alias i2c5 off end
 		device pci 19.2 alias uart2 off end
-		device pci 1b.0 alias pcie_rp17 off end
-		device pci 1b.1 alias pcie_rp18 off end
-		device pci 1b.2 alias pcie_rp19 off end
-		device pci 1b.3 alias pcie_rp20 off end
-		device pci 1b.4 alias pcie_rp21 off end
-		device pci 1b.5 alias pcie_rp22 off end
-		device pci 1b.6 alias pcie_rp23 off end
-		device pci 1b.7 alias pcie_rp24 off end
-		device pci 1c.0 alias pcie_rp1 off end
-		device pci 1c.1 alias pcie_rp2 off end
-		device pci 1c.2 alias pcie_rp3 off end
-		device pci 1c.3 alias pcie_rp4 off end
-		device pci 1c.4 alias pcie_rp5 off end
-		device pci 1c.5 alias pcie_rp6 off end
-		device pci 1c.6 alias pcie_rp7 off end
-		device pci 1c.7 alias pcie_rp8 off end
-		device pci 1d.0 alias pcie_rp9 off end
-		device pci 1d.1 alias pcie_rp10 off end
-		device pci 1d.2 alias pcie_rp11 off end
-		device pci 1d.3 alias pcie_rp12 off end
-		device pci 1d.4 alias pcie_rp13 off end
-		device pci 1d.5 alias pcie_rp14 off end
-		device pci 1d.6 alias pcie_rp15 off end
-		device pci 1d.7 alias pcie_rp16 off end
+		device pci 1b.0 alias pcie_rp17 off ops pcie_rp_ops end
+		device pci 1b.1 alias pcie_rp18 off ops pcie_rp_ops end
+		device pci 1b.2 alias pcie_rp19 off ops pcie_rp_ops end
+		device pci 1b.3 alias pcie_rp20 off ops pcie_rp_ops end
+		device pci 1b.4 alias pcie_rp21 off ops pcie_rp_ops end
+		device pci 1b.5 alias pcie_rp22 off ops pcie_rp_ops end
+		device pci 1b.6 alias pcie_rp23 off ops pcie_rp_ops end
+		device pci 1b.7 alias pcie_rp24 off ops pcie_rp_ops end
+		device pci 1c.0 alias pcie_rp1 off ops pcie_rp_ops end
+		device pci 1c.1 alias pcie_rp2 off ops pcie_rp_ops end
+		device pci 1c.2 alias pcie_rp3 off ops pcie_rp_ops end
+		device pci 1c.3 alias pcie_rp4 off ops pcie_rp_ops end
+		device pci 1c.4 alias pcie_rp5 off ops pcie_rp_ops end
+		device pci 1c.5 alias pcie_rp6 off ops pcie_rp_ops end
+		device pci 1c.6 alias pcie_rp7 off ops pcie_rp_ops end
+		device pci 1c.7 alias pcie_rp8 off ops pcie_rp_ops end
+		device pci 1d.0 alias pcie_rp9 off ops pcie_rp_ops end
+		device pci 1d.1 alias pcie_rp10 off ops pcie_rp_ops end
+		device pci 1d.2 alias pcie_rp11 off ops pcie_rp_ops end
+		device pci 1d.3 alias pcie_rp12 off ops pcie_rp_ops end
+		device pci 1d.4 alias pcie_rp13 off ops pcie_rp_ops end
+		device pci 1d.5 alias pcie_rp14 off ops pcie_rp_ops end
+		device pci 1d.6 alias pcie_rp15 off ops pcie_rp_ops end
+		device pci 1d.7 alias pcie_rp16 off ops pcie_rp_ops end
 		device pci 1e.0 alias uart0 off end
 		device pci 1e.1 alias uart1 off end
 		device pci 1e.2 alias gspi0 off end

From d80482400f88a187739c44eb9f4bfb13a2d34f54 Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Mon, 26 Jan 2026 13:03:59 +0000
Subject: [PATCH 3171/3886] drivers/option/cfr: Fix numeric default override

CFR default overrides use SM_OBJ_* kinds, but
write_numeric_option() compared them to CFR_TAG_OPTION_*,
so enum/number/bool overrides were always skipped.

Compare kinds against the expected SM_OBJ_* for each numeric
tag, then apply the override.

Change-Id: I02046974a7b0a3ef32973689833e1b0d38a5d6f4
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90911
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/drivers/option/cfr.c | 19 ++++++++++++++++---
 1 file changed, 16 insertions(+), 3 deletions(-)

diff --git a/src/drivers/option/cfr.c b/src/drivers/option/cfr.c
index d5390231d6..1a5f1d67d7 100644
--- a/src/drivers/option/cfr.c
+++ b/src/drivers/option/cfr.c
@@ -123,6 +123,21 @@ static uint32_t sm_write_enum_value(char *current, const struct sm_enum_value *e
 	return enum_val->size;
 }
 
+
+static bool override_matches_numeric_tag(enum sm_object_kind override_kind, uint32_t tag)
+{
+	switch (tag) {
+	case CFR_TAG_OPTION_ENUM:
+		return override_kind == SM_OBJ_ENUM;
+	case CFR_TAG_OPTION_NUMBER:
+		return override_kind == SM_OBJ_NUMBER;
+	case CFR_TAG_OPTION_BOOL:
+		return override_kind == SM_OBJ_BOOL;
+	default:
+		return false;
+	}
+}
+
 static uint32_t write_numeric_option(char *current, uint32_t tag, const uint64_t object_id,
 		const char *opt_name, const char *ui_name, const char *ui_helptext,
 		uint32_t flags, uint32_t default_value, uint32_t min, uint32_t max, uint32_t step,
@@ -135,10 +150,8 @@ static uint32_t write_numeric_option(char *current, uint32_t tag, const uint64_t
 	/* Check for mainboard override of default value */
 	const struct cfr_default_override *ovr = find_override(opt_name);
 	if (ovr) {
-		if (ovr->kind != tag)
+		if (!override_matches_numeric_tag(ovr->kind, tag))
 			printk(BIOS_WARNING, "CFR: override for option '%s' has mismatched type; skipping.\n", opt_name);
-		else if (tag == CFR_TAG_OPTION_BOOL)
-			default_value = ovr->bool_value;
 		else
 			default_value = ovr->uint_value;
 	}

From 7d9fb0c1876434e45dfd88afa268931654ee97fa Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Sun, 25 Jan 2026 18:56:22 -0600
Subject: [PATCH 3172/3886] soc/intel: Use chipset.cb for I2C device ops
 linking
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Move I2C device operations linking from PCI Device ID matching
to chipset.cb files for all Intel SoCs that have them, matching the
approach used by Skylake.

Remove corresponding DIDs from i2c.c for these SoCs; keep DID
matching only for SoCs without chipset.cb files.

This standardizes the approach across Intel SoCs and makes the
I2C controller configuration explicit in devicetree, and prevents
the endless proliferation of DIDs in the common I2C driver code.

Change-Id: Ib68dd19c7c94d4cb6b41a1caf092b77f463c1c74
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90906
Reviewed-by: Jakub "Kuba" Czapiga <czapiga@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
---
 src/soc/intel/alderlake/chipset.cb        |  16 +--
 src/soc/intel/alderlake/chipset_pch_s.cb  |  12 +--
 src/soc/intel/apollolake/chipset_apl.cb   |  16 +--
 src/soc/intel/apollolake/chipset_glk.cb   |  16 +--
 src/soc/intel/cannonlake/chipset.cb       |  12 +--
 src/soc/intel/cannonlake/chipset_pch_h.cb |  12 +--
 src/soc/intel/common/block/i2c/i2c.c      | 119 ----------------------
 src/soc/intel/jasperlake/chipset.cb       |  12 +--
 src/soc/intel/meteorlake/chipset.cb       |  12 +--
 src/soc/intel/pantherlake/chipset_ptl.cb  |  12 +--
 src/soc/intel/pantherlake/chipset_wcl.cb  |  12 +--
 src/soc/intel/tigerlake/chipset.cb        |  12 +--
 src/soc/intel/tigerlake/chipset_pch_h.cb  |  14 +--
 13 files changed, 79 insertions(+), 198 deletions(-)

diff --git a/src/soc/intel/alderlake/chipset.cb b/src/soc/intel/alderlake/chipset.cb
index e2b4570a6b..dcd5ebc400 100644
--- a/src/soc/intel/alderlake/chipset.cb
+++ b/src/soc/intel/alderlake/chipset.cb
@@ -172,8 +172,8 @@ chip soc/intel/alderlake
 		device pci 0d.2 alias tcss_dma0 off end
 		device pci 0d.3 alias tcss_dma1 off end
 		device pci 0e.0 alias vmd off end
-		device pci 10.0 alias i2c6 off end
-		device pci 10.1 alias i2c7 off end
+		device pci 10.0 alias i2c6 off ops i2c_dev_ops end
+		device pci 10.1 alias i2c7 off ops i2c_dev_ops end
 		device pci 10.6 alias thc0 off end
 		device pci 10.7 alias thc1 off end
 		device pci 12.0 alias ish off end
@@ -232,10 +232,10 @@ chip soc/intel/alderlake
 		device pci 14.1 alias usb_otg off end
 		device pci 14.2 alias shared_sram off end
 		device pci 14.3 alias cnvi_wifi off end
-		device pci 15.0 alias i2c0 off end
-		device pci 15.1 alias i2c1 off end
-		device pci 15.2 alias i2c2 off end
-		device pci 15.3 alias i2c3 off end
+		device pci 15.0 alias i2c0 off ops i2c_dev_ops end
+		device pci 15.1 alias i2c1 off ops i2c_dev_ops end
+		device pci 15.2 alias i2c2 off ops i2c_dev_ops end
+		device pci 15.3 alias i2c3 off ops i2c_dev_ops end
 		device pci 16.0 alias heci1 on  end
 		device pci 16.1 alias heci2 off end
 		device pci 16.2 alias ide_r off end
@@ -243,8 +243,8 @@ chip soc/intel/alderlake
 		device pci 16.4 alias heci3 off end
 		device pci 16.5 alias heci4 off end
 		device pci 17.0 alias sata off end
-		device pci 19.0 alias i2c4 off end
-		device pci 19.1 alias i2c5 off end
+		device pci 19.0 alias i2c4 off ops i2c_dev_ops end
+		device pci 19.1 alias i2c5 off ops i2c_dev_ops end
 		device pci 19.2 alias uart2 off end
 		# eMMC device is applicable only for ADL-N
 		device pci 1a.0 alias emmc off end
diff --git a/src/soc/intel/alderlake/chipset_pch_s.cb b/src/soc/intel/alderlake/chipset_pch_s.cb
index 06b50f6844..a1a056bcf2 100644
--- a/src/soc/intel/alderlake/chipset_pch_s.cb
+++ b/src/soc/intel/alderlake/chipset_pch_s.cb
@@ -363,10 +363,10 @@ chip soc/intel/alderlake
 		device pci 14.1 alias xdci off end
 		device pci 14.2 alias shared_sram off end
 		device pci 14.3 alias cnvi_wifi off end
-		device pci 15.0 alias i2c0 off end
-		device pci 15.1 alias i2c1 off end
-		device pci 15.2 alias i2c2 off end
-		device pci 15.3 alias i2c3 off end
+		device pci 15.0 alias i2c0 off ops i2c_dev_ops end
+		device pci 15.1 alias i2c1 off ops i2c_dev_ops end
+		device pci 15.2 alias i2c2 off ops i2c_dev_ops end
+		device pci 15.3 alias i2c3 off ops i2c_dev_ops end
 		device pci 16.0 alias heci1 on  end
 		device pci 16.1 alias heci2 off end
 		device pci 16.2 alias ide_r off end
@@ -374,8 +374,8 @@ chip soc/intel/alderlake
 		device pci 16.4 alias heci3 off end
 		device pci 16.5 alias heci4 off end
 		device pci 17.0 alias sata off end
-		device pci 19.0 alias i2c4 off end
-		device pci 19.1 alias i2c5 off end
+		device pci 19.0 alias i2c4 off ops i2c_dev_ops end
+		device pci 19.1 alias i2c5 off ops i2c_dev_ops end
 		device pci 19.2 alias uart2 off end
 		device pci 1a.0 alias pcie_rp25 off ops pcie_rp_ops end
 		device pci 1a.1 alias pcie_rp26 off ops pcie_rp_ops end
diff --git a/src/soc/intel/apollolake/chipset_apl.cb b/src/soc/intel/apollolake/chipset_apl.cb
index a39461d6de..7184a0c401 100644
--- a/src/soc/intel/apollolake/chipset_apl.cb
+++ b/src/soc/intel/apollolake/chipset_apl.cb
@@ -24,14 +24,14 @@ chip soc/intel/apollolake
 		device pci 14.1 alias pcie_rp06		off ops pcie_rp_ops	end # PCIE Express Root Port 6
 		device pci 15.0 alias xhci		off	end # XHCI
 		device pci 15.1 alias xdci		off	end # XDCI
-		device pci 16.0 alias i2c0		off	end # I2C0
-		device pci 16.1 alias i2c1		off	end # I2C1
-		device pci 16.2 alias i2c2		off	end # I2C2
-		device pci 16.3 alias i2c3		off	end # I2C3
-		device pci 17.0 alias i2c4		off	end # I2C4
-		device pci 17.1 alias i2c5		off	end # I2C5
-		device pci 17.2 alias i2c6		off	end # I2C6
-		device pci 17.3 alias i2c7		off	end # I2C7
+		device pci 16.0 alias i2c0		off ops i2c_dev_ops end # I2C0
+		device pci 16.1 alias i2c1		off ops i2c_dev_ops end # I2C1
+		device pci 16.2 alias i2c2		off ops i2c_dev_ops end # I2C2
+		device pci 16.3 alias i2c3		off ops i2c_dev_ops end # I2C3
+		device pci 17.0 alias i2c4		off ops i2c_dev_ops end # I2C4
+		device pci 17.1 alias i2c5		off ops i2c_dev_ops end # I2C5
+		device pci 17.2 alias i2c6		off ops i2c_dev_ops end # I2C6
+		device pci 17.3 alias i2c7		off ops i2c_dev_ops end # I2C7
 		device pci 18.0 alias uart0		off	end # UART0
 		device pci 18.1 alias uart1		off	end # UART1
 		device pci 18.2 alias uart2		off	end # UART2
diff --git a/src/soc/intel/apollolake/chipset_glk.cb b/src/soc/intel/apollolake/chipset_glk.cb
index 1fcc37e800..963ed40339 100644
--- a/src/soc/intel/apollolake/chipset_glk.cb
+++ b/src/soc/intel/apollolake/chipset_glk.cb
@@ -25,14 +25,14 @@ chip soc/intel/apollolake
 		device pci 14.1 alias pcie_rp06		off ops pcie_rp_ops	end # PCIE Express Root Port 6
 		device pci 15.0 alias xhci		off	end # XHCI
 		device pci 15.1 alias xdci		off	end # XDCI
-		device pci 16.0 alias i2c0		off	end # I2C0
-		device pci 16.1 alias i2c1		off	end # I2C1
-		device pci 16.2 alias i2c2		off	end # I2C2
-		device pci 16.3 alias i2c3		off	end # I2C3
-		device pci 17.0 alias i2c4		off	end # I2C4
-		device pci 17.1 alias i2c5		off	end # I2C5
-		device pci 17.2 alias i2c6		off	end # I2C6
-		device pci 17.3 alias i2c7		off	end # I2C7
+		device pci 16.0 alias i2c0		off ops i2c_dev_ops end # I2C0
+		device pci 16.1 alias i2c1		off ops i2c_dev_ops end # I2C1
+		device pci 16.2 alias i2c2		off ops i2c_dev_ops end # I2C2
+		device pci 16.3 alias i2c3		off ops i2c_dev_ops end # I2C3
+		device pci 17.0 alias i2c4		off ops i2c_dev_ops end # I2C4
+		device pci 17.1 alias i2c5		off ops i2c_dev_ops end # I2C5
+		device pci 17.2 alias i2c6		off ops i2c_dev_ops end # I2C6
+		device pci 17.3 alias i2c7		off ops i2c_dev_ops end # I2C7
 		device pci 18.0 alias uart0		off	end # UART0
 		device pci 18.1 alias uart1		off	end # UART1
 		device pci 18.2 alias uart2		off	end # UART2
diff --git a/src/soc/intel/cannonlake/chipset.cb b/src/soc/intel/cannonlake/chipset.cb
index eb0a0bcb92..acdac57a77 100644
--- a/src/soc/intel/cannonlake/chipset.cb
+++ b/src/soc/intel/cannonlake/chipset.cb
@@ -82,10 +82,10 @@ chip soc/intel/cannonlake
 		device pci 14.2 alias shared_sram  off  end	# Shared SRAM
 		device pci 14.3 alias cnvi_wifi    off	end	# CNVi Wifi
 		device pci 14.5 alias sdxc         off	end	# SDCard
-		device pci 15.0 alias i2c0         off	end	# I2C #0
-		device pci 15.1 alias i2c1         off	end	# I2C #1
-		device pci 15.2 alias i2c2         off	end	# I2C #2
-		device pci 15.3 alias i2c3         off	end	# I2C #3
+		device pci 15.0 alias i2c0         off ops i2c_dev_ops end	# I2C #0
+		device pci 15.1 alias i2c1         off ops i2c_dev_ops end	# I2C #1
+		device pci 15.2 alias i2c2         off ops i2c_dev_ops end	# I2C #2
+		device pci 15.3 alias i2c3         off ops i2c_dev_ops end	# I2C #3
 		device pci 16.0 alias heci1        on	end	# Management Engine Interface 1
 		device pci 16.1 alias heci2        off	end	# Management Engine Interface 2
 		device pci 16.2 alias csme_ider    off	end	# Management Engine IDE-R
@@ -93,8 +93,8 @@ chip soc/intel/cannonlake
 		device pci 16.4 alias heci3        off	end	# Management Engine Interface 3
 		device pci 16.5 alias heci4        off	end	# Management Engine Interface 4
 		device pci 17.0 alias sata         off	end	# SATA
-		device pci 19.0 alias i2c4         off	end	# I2C #4
-		device pci 19.1 alias i2c5         off	end	# I2C #5
+		device pci 19.0 alias i2c4         off ops i2c_dev_ops end	# I2C #4
+		device pci 19.1 alias i2c5         off ops i2c_dev_ops end	# I2C #5
 		device pci 19.2 alias uart2        off	end	# UART #2
 		device pci 1a.0 alias emmc         off	end	# eMMC
 		device pci 1c.0 alias pcie_rp1     off ops pcie_rp_ops	end	# PCI Express Port 1
diff --git a/src/soc/intel/cannonlake/chipset_pch_h.cb b/src/soc/intel/cannonlake/chipset_pch_h.cb
index fa7660b5af..eeeab7b7ad 100644
--- a/src/soc/intel/cannonlake/chipset_pch_h.cb
+++ b/src/soc/intel/cannonlake/chipset_pch_h.cb
@@ -106,10 +106,10 @@ chip soc/intel/cannonlake
 		device pci 14.2 alias shared_sram  off  end	# Shared SRAM
 		device pci 14.3 alias cnvi_wifi    off	end	# CNVi Wifi
 		device pci 14.5 alias sdxc         off	end	# SDCard
-		device pci 15.0 alias i2c0         off	end	# I2C #0
-		device pci 15.1 alias i2c1         off	end	# I2C #1
-		device pci 15.2 alias i2c2         off	end	# I2C #2
-		device pci 15.3 alias i2c3         off	end	# I2C #3
+		device pci 15.0 alias i2c0         off ops i2c_dev_ops end	# I2C #0
+		device pci 15.1 alias i2c1         off ops i2c_dev_ops end	# I2C #1
+		device pci 15.2 alias i2c2         off ops i2c_dev_ops end	# I2C #2
+		device pci 15.3 alias i2c3         off ops i2c_dev_ops end	# I2C #3
 		device pci 16.0 alias heci1        on	end	# Management Engine Interface 1
 		device pci 16.1 alias heci2        off	end	# Management Engine Interface 2
 		device pci 16.2 alias csme_ider    off	end	# Management Engine IDE-R
@@ -117,8 +117,8 @@ chip soc/intel/cannonlake
 		device pci 16.4 alias heci3        off	end	# Management Engine Interface 3
 		device pci 16.5 alias heci4        off	end	# Management Engine Interface 4
 		device pci 17.0 alias sata         off	end	# SATA
-		device pci 19.0 alias i2c4         off	end	# I2C #4
-		device pci 19.1 alias i2c5         off	end	# I2C #5
+		device pci 19.0 alias i2c4         off ops i2c_dev_ops end	# I2C #4
+		device pci 19.1 alias i2c5         off ops i2c_dev_ops end	# I2C #5
 		device pci 19.2 alias uart2        off		# UART #2
 			ops uart_ops
 		end
diff --git a/src/soc/intel/common/block/i2c/i2c.c b/src/soc/intel/common/block/i2c/i2c.c
index 7609b217a3..8018ee573d 100644
--- a/src/soc/intel/common/block/i2c/i2c.c
+++ b/src/soc/intel/common/block/i2c/i2c.c
@@ -180,99 +180,12 @@ static const unsigned short pci_device_ids[] = {
 	PCI_DID_INTEL_NVL_I2C3,
 	PCI_DID_INTEL_NVL_I2C4,
 	PCI_DID_INTEL_NVL_I2C5,
-	PCI_DID_INTEL_WCL_I2C0,
-	PCI_DID_INTEL_WCL_I2C1,
-	PCI_DID_INTEL_WCL_I2C2,
-	PCI_DID_INTEL_WCL_I2C3,
-	PCI_DID_INTEL_WCL_I2C4,
-	PCI_DID_INTEL_WCL_I2C5,
-	PCI_DID_INTEL_PTL_H_I2C0,
-	PCI_DID_INTEL_PTL_H_I2C1,
-	PCI_DID_INTEL_PTL_H_I2C2,
-	PCI_DID_INTEL_PTL_H_I2C3,
-	PCI_DID_INTEL_PTL_H_I2C4,
-	PCI_DID_INTEL_PTL_H_I2C5,
-	PCI_DID_INTEL_PTL_U_H_I2C0,
-	PCI_DID_INTEL_PTL_U_H_I2C1,
-	PCI_DID_INTEL_PTL_U_H_I2C2,
-	PCI_DID_INTEL_PTL_U_H_I2C3,
-	PCI_DID_INTEL_PTL_U_H_I2C4,
-	PCI_DID_INTEL_PTL_U_H_I2C5,
 	PCI_DID_INTEL_LNL_I2C0,
 	PCI_DID_INTEL_LNL_I2C1,
 	PCI_DID_INTEL_LNL_I2C2,
 	PCI_DID_INTEL_LNL_I2C3,
 	PCI_DID_INTEL_LNL_I2C4,
 	PCI_DID_INTEL_LNL_I2C5,
-	PCI_DID_INTEL_MTL_I2C0,
-	PCI_DID_INTEL_MTL_I2C1,
-	PCI_DID_INTEL_MTL_I2C2,
-	PCI_DID_INTEL_MTL_I2C3,
-	PCI_DID_INTEL_MTL_I2C4,
-	PCI_DID_INTEL_MTL_I2C5,
-	PCI_DID_INTEL_ARL_I2C0,
-	PCI_DID_INTEL_ARL_I2C1,
-	PCI_DID_INTEL_ARL_I2C2,
-	PCI_DID_INTEL_ARL_I2C3,
-	PCI_DID_INTEL_ARL_I2C4,
-	PCI_DID_INTEL_ARL_I2C5,
-	PCI_DID_INTEL_ARP_S_I2C0,
-	PCI_DID_INTEL_ARP_S_I2C1,
-	PCI_DID_INTEL_ARP_S_I2C2,
-	PCI_DID_INTEL_ARP_S_I2C3,
-	PCI_DID_INTEL_ARP_S_I2C4,
-	PCI_DID_INTEL_ARP_S_I2C5,
-	PCI_DID_INTEL_APL_I2C0,
-	PCI_DID_INTEL_APL_I2C1,
-	PCI_DID_INTEL_APL_I2C2,
-	PCI_DID_INTEL_APL_I2C3,
-	PCI_DID_INTEL_APL_I2C4,
-	PCI_DID_INTEL_APL_I2C5,
-	PCI_DID_INTEL_APL_I2C6,
-	PCI_DID_INTEL_APL_I2C7,
-	PCI_DID_INTEL_CNL_I2C0,
-	PCI_DID_INTEL_CNL_I2C1,
-	PCI_DID_INTEL_CNL_I2C2,
-	PCI_DID_INTEL_CNL_I2C3,
-	PCI_DID_INTEL_CNL_I2C4,
-	PCI_DID_INTEL_CNL_I2C5,
-	PCI_DID_INTEL_GLK_I2C0,
-	PCI_DID_INTEL_GLK_I2C1,
-	PCI_DID_INTEL_GLK_I2C2,
-	PCI_DID_INTEL_GLK_I2C3,
-	PCI_DID_INTEL_GLK_I2C4,
-	PCI_DID_INTEL_GLK_I2C5,
-	PCI_DID_INTEL_GLK_I2C6,
-	PCI_DID_INTEL_GLK_I2C7,
-	PCI_DID_INTEL_CNP_H_I2C0,
-	PCI_DID_INTEL_CNP_H_I2C1,
-	PCI_DID_INTEL_CNP_H_I2C2,
-	PCI_DID_INTEL_CNP_H_I2C3,
-	PCI_DID_INTEL_CMP_I2C0,
-	PCI_DID_INTEL_CMP_I2C1,
-	PCI_DID_INTEL_CMP_I2C2,
-	PCI_DID_INTEL_CMP_I2C3,
-	PCI_DID_INTEL_CMP_I2C4,
-	PCI_DID_INTEL_CMP_I2C5,
-	PCI_DID_INTEL_CMP_H_I2C0,
-	PCI_DID_INTEL_CMP_H_I2C1,
-	PCI_DID_INTEL_CMP_H_I2C2,
-	PCI_DID_INTEL_CMP_H_I2C3,
-	PCI_DID_INTEL_TGP_I2C0,
-	PCI_DID_INTEL_TGP_I2C1,
-	PCI_DID_INTEL_TGP_I2C2,
-	PCI_DID_INTEL_TGP_I2C3,
-	PCI_DID_INTEL_TGP_I2C4,
-	PCI_DID_INTEL_TGP_I2C5,
-	PCI_DID_INTEL_TGP_I2C6,
-	PCI_DID_INTEL_TGP_I2C7,
-	PCI_DID_INTEL_TGP_H_I2C0,
-	PCI_DID_INTEL_TGP_H_I2C1,
-	PCI_DID_INTEL_TGP_H_I2C2,
-	PCI_DID_INTEL_TGP_H_I2C3,
-	PCI_DID_INTEL_TGP_H_I2C4,
-	PCI_DID_INTEL_TGP_H_I2C5,
-	PCI_DID_INTEL_TGP_H_I2C6,
 	PCI_DID_INTEL_MCC_I2C0,
 	PCI_DID_INTEL_MCC_I2C1,
 	PCI_DID_INTEL_MCC_I2C2,
@@ -281,38 +194,6 @@ static const unsigned short pci_device_ids[] = {
 	PCI_DID_INTEL_MCC_I2C5,
 	PCI_DID_INTEL_MCC_I2C6,
 	PCI_DID_INTEL_MCC_I2C7,
-	PCI_DID_INTEL_JSP_I2C0,
-	PCI_DID_INTEL_JSP_I2C1,
-	PCI_DID_INTEL_JSP_I2C2,
-	PCI_DID_INTEL_JSP_I2C3,
-	PCI_DID_INTEL_JSP_I2C4,
-	PCI_DID_INTEL_JSP_I2C5,
-	PCI_DID_INTEL_ADP_P_I2C0,
-	PCI_DID_INTEL_ADP_P_I2C1,
-	PCI_DID_INTEL_ADP_P_I2C2,
-	PCI_DID_INTEL_ADP_P_I2C3,
-	PCI_DID_INTEL_ADP_P_I2C4,
-	PCI_DID_INTEL_ADP_P_I2C5,
-	PCI_DID_INTEL_ADP_P_I2C6,
-	PCI_DID_INTEL_ADP_P_I2C7,
-	PCI_DID_INTEL_ADP_S_I2C0,
-	PCI_DID_INTEL_ADP_S_I2C1,
-	PCI_DID_INTEL_ADP_S_I2C2,
-	PCI_DID_INTEL_ADP_S_I2C3,
-	PCI_DID_INTEL_ADP_S_I2C4,
-	PCI_DID_INTEL_ADP_S_I2C5,
-	PCI_DID_INTEL_ADP_M_N_I2C0,
-	PCI_DID_INTEL_ADP_M_N_I2C1,
-	PCI_DID_INTEL_ADP_M_N_I2C2,
-	PCI_DID_INTEL_ADP_M_N_I2C3,
-	PCI_DID_INTEL_ADP_M_N_I2C4,
-	PCI_DID_INTEL_ADP_M_N_I2C5,
-	PCI_DID_INTEL_RPP_S_I2C0,
-	PCI_DID_INTEL_RPP_S_I2C1,
-	PCI_DID_INTEL_RPP_S_I2C2,
-	PCI_DID_INTEL_RPP_S_I2C3,
-	PCI_DID_INTEL_RPP_S_I2C4,
-	PCI_DID_INTEL_RPP_S_I2C5,
 	0,
 };
 
diff --git a/src/soc/intel/jasperlake/chipset.cb b/src/soc/intel/jasperlake/chipset.cb
index aa25ff5e8e..1a85aa8e40 100644
--- a/src/soc/intel/jasperlake/chipset.cb
+++ b/src/soc/intel/jasperlake/chipset.cb
@@ -65,16 +65,16 @@ chip soc/intel/jasperlake
 		device pci 14.2 alias shared_ram	off end
 		device pci 14.3 alias cnvi_wifi		off end
 		device pci 14.5 alias sdxc		off end
-		device pci 15.0 alias i2c0		off end
-		device pci 15.1 alias i2c1		off end
-		device pci 15.2 alias i2c2		off end
-		device pci 15.3 alias i2c3		off end
+		device pci 15.0 alias i2c0		off ops i2c_dev_ops end
+		device pci 15.1 alias i2c1		off ops i2c_dev_ops end
+		device pci 15.2 alias i2c2		off ops i2c_dev_ops end
+		device pci 15.3 alias i2c3		off ops i2c_dev_ops end
 		device pci 16.0 alias heci1		off end
 		device pci 16.1 alias heci2		off end
 		device pci 16.4 alias heci3		off end
 		device pci 17.0 alias sata		off end
-		device pci 19.0 alias i2c4		off end
-		device pci 19.1 alias i2c5		off end
+		device pci 19.0 alias i2c4		off ops i2c_dev_ops end
+		device pci 19.1 alias i2c5		off ops i2c_dev_ops end
 		device pci 19.2 alias uart2		off end
 		device pci 1a.0 alias emmc		off end
 		device pci 1c.0 alias pcie_rp1		off ops pcie_rp_ops end
diff --git a/src/soc/intel/meteorlake/chipset.cb b/src/soc/intel/meteorlake/chipset.cb
index 6851b5769f..57c82b3b61 100644
--- a/src/soc/intel/meteorlake/chipset.cb
+++ b/src/soc/intel/meteorlake/chipset.cb
@@ -153,10 +153,10 @@ chip soc/intel/meteorlake
 		device pci 14.2 alias pmc_shared_sram off end
 		device pci 14.3 alias cnvi_wifi off end
 		device pci 14.5 alias ieh off end
-		device pci 15.0 alias i2c0 off end
-		device pci 15.1 alias i2c1 off end
-		device pci 15.2 alias i2c2 off end
-		device pci 15.3 alias i2c3 off end
+		device pci 15.0 alias i2c0 off ops i2c_dev_ops end
+		device pci 15.1 alias i2c1 off ops i2c_dev_ops end
+		device pci 15.2 alias i2c2 off ops i2c_dev_ops end
+		device pci 15.3 alias i2c3 off ops i2c_dev_ops end
 		device pci 15.4 alias i3c off end
 		device pci 16.0 alias heci1 on end
 		device pci 16.1 alias heci2 off end
@@ -166,8 +166,8 @@ chip soc/intel/meteorlake
 		device pci 18.0 alias eheci1 off end
 		device pci 18.1 alias eheci2 off end
 		device pci 18.2 alias eheci3 off end
-		device pci 19.0 alias i2c4 off end
-		device pci 19.1 alias i2c5 off end
+		device pci 19.0 alias i2c4 off ops i2c_dev_ops end
+		device pci 19.1 alias i2c5 off ops i2c_dev_ops end
 		device pci 19.2 alias uart2 off end
 		device pci 1c.0 alias pcie_rp1 off ops pcie_rp_ops end
 		device pci 1c.1 alias pcie_rp2 off ops pcie_rp_ops end
diff --git a/src/soc/intel/pantherlake/chipset_ptl.cb b/src/soc/intel/pantherlake/chipset_ptl.cb
index 31a898182f..e45558b4ec 100644
--- a/src/soc/intel/pantherlake/chipset_ptl.cb
+++ b/src/soc/intel/pantherlake/chipset_ptl.cb
@@ -215,10 +215,10 @@ chip soc/intel/pantherlake
 		device pci 14.3 alias cnvi_wifi off end
 		device pci 14.7 alias cnvi_bluetooth off end
 		device pci 14.5 alias ieh off end
-		device pci 15.0 alias i2c0 off end
-		device pci 15.1 alias i2c1 off end
-		device pci 15.2 alias i2c2 off end
-		device pci 15.3 alias i2c3 off end
+		device pci 15.0 alias i2c0 off ops i2c_dev_ops end
+		device pci 15.1 alias i2c1 off ops i2c_dev_ops end
+		device pci 15.2 alias i2c2 off ops i2c_dev_ops end
+		device pci 15.3 alias i2c3 off ops i2c_dev_ops end
 		device pci 16.0 alias heci1 on end
 		device pci 16.1 alias heci2 off end
 		device pci 16.4 alias heci3 off end
@@ -226,8 +226,8 @@ chip soc/intel/pantherlake
 		device pci 18.0 alias eheci1 off end
 		device pci 18.1 alias eheci2 off end
 		device pci 18.2 alias eheci3 off end
-		device pci 19.0 alias i2c4 off end
-		device pci 19.1 alias i2c5 off end
+		device pci 19.0 alias i2c4 off ops i2c_dev_ops end
+		device pci 19.1 alias i2c5 off ops i2c_dev_ops end
 		device pci 19.2 alias uart2 off end
 		device pci 1c.0 alias pcie_rp1 off ops pcie_rp_ops end
 		device pci 1c.1 alias pcie_rp2 off ops pcie_rp_ops end
diff --git a/src/soc/intel/pantherlake/chipset_wcl.cb b/src/soc/intel/pantherlake/chipset_wcl.cb
index 2236d930e2..3d4f641260 100644
--- a/src/soc/intel/pantherlake/chipset_wcl.cb
+++ b/src/soc/intel/pantherlake/chipset_wcl.cb
@@ -101,10 +101,10 @@ chip soc/intel/pantherlake
 		device pci 14.3 alias cnvi_wifi off end
 		device pci 14.7 alias cnvi_bluetooth off end
 		device pci 14.5 alias ieh off end
-		device pci 15.0 alias i2c0 off end
-		device pci 15.1 alias i2c1 off end
-		device pci 15.2 alias i2c2 off end
-		device pci 15.3 alias i2c3 off end
+		device pci 15.0 alias i2c0 off ops i2c_dev_ops end
+		device pci 15.1 alias i2c1 off ops i2c_dev_ops end
+		device pci 15.2 alias i2c2 off ops i2c_dev_ops end
+		device pci 15.3 alias i2c3 off ops i2c_dev_ops end
 		device pci 16.0 alias heci1 on end
 		device pci 16.1 alias heci2 off end
 		device pci 16.4 alias heci3 off end
@@ -113,8 +113,8 @@ chip soc/intel/pantherlake
 		device pci 18.0 alias eheci1 off end
 		device pci 18.1 alias eheci2 off end
 		device pci 18.2 alias eheci3 off end
-		device pci 19.0 alias i2c4 off end
-		device pci 19.1 alias i2c5 off end
+		device pci 19.0 alias i2c4 off ops i2c_dev_ops end
+		device pci 19.1 alias i2c5 off ops i2c_dev_ops end
 		device pci 19.2 alias uart2 off end
 		device pci 1c.0 alias pcie_rp1 off ops pcie_rp_ops end
 		device pci 1c.1 alias pcie_rp2 off ops pcie_rp_ops end
diff --git a/src/soc/intel/tigerlake/chipset.cb b/src/soc/intel/tigerlake/chipset.cb
index bdf0138229..38cfc0dca1 100644
--- a/src/soc/intel/tigerlake/chipset.cb
+++ b/src/soc/intel/tigerlake/chipset.cb
@@ -115,10 +115,10 @@ chip soc/intel/tigerlake
 		device pci 14.1 alias south_xdci off end
 		device pci 14.2 alias shared_ram off end
 		device pci 14.3 alias cnvi_wifi off end
-		device pci 15.0 alias i2c0 off end
-		device pci 15.1 alias i2c1 off end
-		device pci 15.2 alias i2c2 off end
-		device pci 15.3 alias i2c3 off end
+		device pci 15.0 alias i2c0 off ops i2c_dev_ops end
+		device pci 15.1 alias i2c1 off ops i2c_dev_ops end
+		device pci 15.2 alias i2c2 off ops i2c_dev_ops end
+		device pci 15.3 alias i2c3 off ops i2c_dev_ops end
 		device pci 16.0 alias heci1 off end
 		device pci 16.1 alias heci2 off end
 		device pci 16.2 alias csme1 off end
@@ -126,8 +126,8 @@ chip soc/intel/tigerlake
 		device pci 16.4 alias heci3 off end
 		device pci 16.5 alias heci4 off end
 		device pci 17.0 alias sata off end
-		device pci 19.0 alias i2c4 off end
-		device pci 19.1 alias i2c5 off end
+		device pci 19.0 alias i2c4 off ops i2c_dev_ops end
+		device pci 19.1 alias i2c5 off ops i2c_dev_ops end
 		device pci 19.2 alias uart2 off end
 		device pci 1c.0 alias pcie_rp1 off ops pcie_rp_ops end
 		device pci 1c.1 alias pcie_rp2 off ops pcie_rp_ops end
diff --git a/src/soc/intel/tigerlake/chipset_pch_h.cb b/src/soc/intel/tigerlake/chipset_pch_h.cb
index e2c7022546..a43778794c 100644
--- a/src/soc/intel/tigerlake/chipset_pch_h.cb
+++ b/src/soc/intel/tigerlake/chipset_pch_h.cb
@@ -63,7 +63,7 @@ chip soc/intel/tigerlake
 		device pci 10.6 alias thc0 off end
 		device pci 10.7 alias thc1 off end
 		device pci 11.0 alias uart3 off end
-		device pci 11.3 alias i2c6 off end
+		device pci 11.3 alias i2c6 off ops i2c_dev_ops end
 		device pci 12.0 alias ish off end
 		device pci 12.6 alias gspi2 off end
 		device pci 13.0 alias gspi3 off end
@@ -137,10 +137,10 @@ chip soc/intel/tigerlake
 		device pci 14.1 alias south_xdci off end
 		device pci 14.2 alias shared_ram off end
 		device pci 14.3 alias cnvi_wifi off end
-		device pci 15.0 alias i2c0 off end
-		device pci 15.1 alias i2c1 off end
-		device pci 15.2 alias i2c2 off end
-		device pci 15.3 alias i2c3 off end
+		device pci 15.0 alias i2c0 off ops i2c_dev_ops end
+		device pci 15.1 alias i2c1 off ops i2c_dev_ops end
+		device pci 15.2 alias i2c2 off ops i2c_dev_ops end
+		device pci 15.3 alias i2c3 off ops i2c_dev_ops end
 		device pci 16.0 alias heci1 off end
 		device pci 16.1 alias heci2 off end
 		device pci 16.2 alias csme1 off end
@@ -148,8 +148,8 @@ chip soc/intel/tigerlake
 		device pci 16.4 alias heci3 off end
 		device pci 16.5 alias heci4 off end
 		device pci 17.0 alias sata off end
-		device pci 19.0 alias i2c4 off end
-		device pci 19.1 alias i2c5 off end
+		device pci 19.0 alias i2c4 off ops i2c_dev_ops end
+		device pci 19.1 alias i2c5 off ops i2c_dev_ops end
 		device pci 19.2 alias uart2 off end
 		device pci 1b.0 alias pcie_rp17 off ops pcie_rp_ops end
 		device pci 1b.1 alias pcie_rp18 off ops pcie_rp_ops end

From fafa37d2bdd7403c71eaefb4c865d5c8017e68cc Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Sun, 25 Jan 2026 19:05:49 -0600
Subject: [PATCH 3173/3886] soc/intel: Use chipset.cb for SATA device ops
 linking

Move SATA device operations linking from PCI Device ID matching
to chipset.cb files for all Intel SoCs that have them, matching the
approach used by Skylake.

Remove corresponding DIDs from sata.c for these SoCs; keep DID
matching only for SoCs without chipset.cb files.

Add `select SOC_INTEL_COMMON_BLOCK_SATA` to Apollolake SoC so that
the common block code is included, which it was not previously, even
though the APL/GLK PCI DIDs were included in the list. The net
effect is that the `SATA` ACPI device is now added to SSDT for
APL/GLK boards when they have SATA enabled.

This standardizes the approach across Intel SoCs and makes the
SATA controller configuration explicit in devicetree, and prevents
the endless proliferation of DIDs in the common driver code.

Change-Id: I4c296a88c4da5f91d1039877ec858857496527f0
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90915
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jakub "Kuba" Czapiga <czapiga@google.com>
---
 src/soc/intel/alderlake/chipset.cb        |  2 +-
 src/soc/intel/alderlake/chipset_pch_s.cb  |  2 +-
 src/soc/intel/apollolake/Kconfig          |  1 +
 src/soc/intel/apollolake/chipset_apl.cb   |  2 +-
 src/soc/intel/apollolake/chipset_glk.cb   |  2 +-
 src/soc/intel/cannonlake/chipset.cb       |  2 +-
 src/soc/intel/cannonlake/chipset_pch_h.cb |  2 +-
 src/soc/intel/common/block/sata/sata.c    | 43 -----------------------
 src/soc/intel/jasperlake/chipset.cb       |  2 +-
 src/soc/intel/meteorlake/chipset.cb       |  2 +-
 src/soc/intel/tigerlake/chipset.cb        |  2 +-
 src/soc/intel/tigerlake/chipset_pch_h.cb  |  2 +-
 12 files changed, 11 insertions(+), 53 deletions(-)

diff --git a/src/soc/intel/alderlake/chipset.cb b/src/soc/intel/alderlake/chipset.cb
index dcd5ebc400..1758d9df74 100644
--- a/src/soc/intel/alderlake/chipset.cb
+++ b/src/soc/intel/alderlake/chipset.cb
@@ -242,7 +242,7 @@ chip soc/intel/alderlake
 		device pci 16.3 alias kt off end
 		device pci 16.4 alias heci3 off end
 		device pci 16.5 alias heci4 off end
-		device pci 17.0 alias sata off end
+		device pci 17.0 alias sata off ops sata_ops end
 		device pci 19.0 alias i2c4 off ops i2c_dev_ops end
 		device pci 19.1 alias i2c5 off ops i2c_dev_ops end
 		device pci 19.2 alias uart2 off end
diff --git a/src/soc/intel/alderlake/chipset_pch_s.cb b/src/soc/intel/alderlake/chipset_pch_s.cb
index a1a056bcf2..28dbc9e458 100644
--- a/src/soc/intel/alderlake/chipset_pch_s.cb
+++ b/src/soc/intel/alderlake/chipset_pch_s.cb
@@ -373,7 +373,7 @@ chip soc/intel/alderlake
 		device pci 16.3 alias kt off end
 		device pci 16.4 alias heci3 off end
 		device pci 16.5 alias heci4 off end
-		device pci 17.0 alias sata off end
+		device pci 17.0 alias sata off ops sata_ops end
 		device pci 19.0 alias i2c4 off ops i2c_dev_ops end
 		device pci 19.1 alias i2c5 off ops i2c_dev_ops end
 		device pci 19.2 alias uart2 off end
diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig
index ef5d4f6b8a..be87a8c10d 100644
--- a/src/soc/intel/apollolake/Kconfig
+++ b/src/soc/intel/apollolake/Kconfig
@@ -66,6 +66,7 @@ config SOC_INTEL_APOLLOLAKE
 	select SOC_INTEL_COMMON_BLOCK_PMC_DISCOVERABLE
 	select SOC_INTEL_COMMON_BLOCK_SRAM
 	select SOC_INTEL_COMMON_BLOCK_SA
+	select SOC_INTEL_COMMON_BLOCK_SATA
 	select SOC_INTEL_COMMON_BLOCK_SCS
 	select SOC_INTEL_COMMON_BLOCK_XHCI_ELOG
 	select SOC_INTEL_COMMON_BLOCK_SMM
diff --git a/src/soc/intel/apollolake/chipset_apl.cb b/src/soc/intel/apollolake/chipset_apl.cb
index 7184a0c401..10d2b04cfe 100644
--- a/src/soc/intel/apollolake/chipset_apl.cb
+++ b/src/soc/intel/apollolake/chipset_apl.cb
@@ -15,7 +15,7 @@ chip soc/intel/apollolake
 		device pci 0f.1 alias heci2		off	end # HECI2
 		device pci 0f.2 alias heci3		off	end # HECI3
 		device pci 11.0 alias ish		off	end # SensorHub
-		device pci 12.0 alias sata		off	end # SATA
+		device pci 12.0 alias sata		off ops sata_ops end # SATA
 		device pci 13.0 alias pcie_rp01		off ops pcie_rp_ops	end # PCIE Express Root Port 1
 		device pci 13.1 alias pcie_rp02		off ops pcie_rp_ops	end # PCIE Express Root Port 2
 		device pci 13.2 alias pcie_rp03		off ops pcie_rp_ops	end # PCIE Express Root Port 3
diff --git a/src/soc/intel/apollolake/chipset_glk.cb b/src/soc/intel/apollolake/chipset_glk.cb
index 963ed40339..7d1bb35ba4 100644
--- a/src/soc/intel/apollolake/chipset_glk.cb
+++ b/src/soc/intel/apollolake/chipset_glk.cb
@@ -16,7 +16,7 @@ chip soc/intel/apollolake
 		device pci 0f.1 alias heci2		off	end # HECI2
 		device pci 0f.2 alias heci3		off	end # HECI3
 		device pci 11.0 alias ish		off	end # SensorHub
-		device pci 12.0 alias sata		off	end # SATA
+		device pci 12.0 alias sata		off ops sata_ops end # SATA
 		device pci 13.0 alias pcie_rp01		off ops pcie_rp_ops	end # PCIE Express Root Port 1
 		device pci 13.1 alias pcie_rp02		off ops pcie_rp_ops	end # PCIE Express Root Port 2
 		device pci 13.2 alias pcie_rp03		off ops pcie_rp_ops	end # PCIE Express Root Port 3
diff --git a/src/soc/intel/cannonlake/chipset.cb b/src/soc/intel/cannonlake/chipset.cb
index acdac57a77..d55036e7fa 100644
--- a/src/soc/intel/cannonlake/chipset.cb
+++ b/src/soc/intel/cannonlake/chipset.cb
@@ -92,7 +92,7 @@ chip soc/intel/cannonlake
 		device pci 16.3 alias csme_ktr     off	end	# Management Engine KT Redirection
 		device pci 16.4 alias heci3        off	end	# Management Engine Interface 3
 		device pci 16.5 alias heci4        off	end	# Management Engine Interface 4
-		device pci 17.0 alias sata         off	end	# SATA
+		device pci 17.0 alias sata         off ops sata_ops end	# SATA
 		device pci 19.0 alias i2c4         off ops i2c_dev_ops end	# I2C #4
 		device pci 19.1 alias i2c5         off ops i2c_dev_ops end	# I2C #5
 		device pci 19.2 alias uart2        off	end	# UART #2
diff --git a/src/soc/intel/cannonlake/chipset_pch_h.cb b/src/soc/intel/cannonlake/chipset_pch_h.cb
index eeeab7b7ad..fb9c67ca46 100644
--- a/src/soc/intel/cannonlake/chipset_pch_h.cb
+++ b/src/soc/intel/cannonlake/chipset_pch_h.cb
@@ -116,7 +116,7 @@ chip soc/intel/cannonlake
 		device pci 16.3 alias csme_ktr     off	end	# Management Engine KT Redirection
 		device pci 16.4 alias heci3        off	end	# Management Engine Interface 3
 		device pci 16.5 alias heci4        off	end	# Management Engine Interface 4
-		device pci 17.0 alias sata         off	end	# SATA
+		device pci 17.0 alias sata         off ops sata_ops end	# SATA
 		device pci 19.0 alias i2c4         off ops i2c_dev_ops end	# I2C #4
 		device pci 19.1 alias i2c5         off ops i2c_dev_ops end	# I2C #5
 		device pci 19.2 alias uart2        off		# UART #2
diff --git a/src/soc/intel/common/block/sata/sata.c b/src/soc/intel/common/block/sata/sata.c
index 0f85faed50..dd92b9d7ec 100644
--- a/src/soc/intel/common/block/sata/sata.c
+++ b/src/soc/intel/common/block/sata/sata.c
@@ -35,13 +35,6 @@ struct device_operations sata_ops = {
 };
 
 static const unsigned short pci_device_ids[] = {
-	PCI_DID_INTEL_MTL_SATA,
-	PCI_DID_INTEL_ARL_SATA,
-	PCI_DID_INTEL_ARP_S_SATA_1,
-	PCI_DID_INTEL_ARP_S_SATA_2,
-	PCI_DID_INTEL_RPP_P_SATA_1,
-	PCI_DID_INTEL_RPP_P_SATA_2,
-	PCI_DID_INTEL_RPP_S_SATA,
 	PCI_DID_INTEL_LWB_SATA_AHCI,
 	PCI_DID_INTEL_LWB_SSATA_AHCI,
 	PCI_DID_INTEL_LWB_SATA_RAID,
@@ -54,43 +47,7 @@ static const unsigned short pci_device_ids[] = {
 	PCI_DID_INTEL_LWB_SATA_ALT_RST,
 	PCI_DID_INTEL_LWB_SSATA_ALT,
 	PCI_DID_INTEL_LWB_SSATA_ALT_RST,
-	PCI_DID_INTEL_CNL_SATA,
-	PCI_DID_INTEL_CNL_PREMIUM_SATA,
-	PCI_DID_INTEL_CNP_CMP_COMPAT_SATA,
-	PCI_DID_INTEL_CNP_H_SATA,
-	PCI_DID_INTEL_CNP_H_HALO_SATA,
-	PCI_DID_INTEL_CNP_LP_SATA,
-	PCI_DID_INTEL_CMP_SATA,
-	PCI_DID_INTEL_CMP_PREMIUM_SATA,
-	PCI_DID_INTEL_CMP_LP_SATA,
-	PCI_DID_INTEL_CMP_H_SATA,
-	PCI_DID_INTEL_CMP_H_HALO_SATA,
-	PCI_DID_INTEL_CMP_H_PREMIUM_SATA,
-	PCI_DID_INTEL_TGP_LP_SATA,
-	PCI_DID_INTEL_TGP_SATA,
-	PCI_DID_INTEL_TGP_PREMIUM_SATA,
-	PCI_DID_INTEL_TGP_COMPAT_SATA,
-	PCI_DID_INTEL_TGP_H_SATA,
 	PCI_DID_INTEL_MCC_AHCI_SATA,
-	PCI_DID_INTEL_JSP_SATA_1,
-	PCI_DID_INTEL_JSP_SATA_2,
-	PCI_DID_INTEL_ADP_P_SATA_1,
-	PCI_DID_INTEL_ADP_P_SATA_2,
-	PCI_DID_INTEL_ADP_P_SATA_3,
-	PCI_DID_INTEL_ADP_P_SATA_4,
-	PCI_DID_INTEL_ADP_P_SATA_5,
-	PCI_DID_INTEL_ADP_P_SATA_6,
-	PCI_DID_INTEL_ADP_S_SATA_1,
-	PCI_DID_INTEL_ADP_S_SATA_2,
-	PCI_DID_INTEL_ADP_S_SATA_3,
-	PCI_DID_INTEL_ADP_S_SATA_4,
-	PCI_DID_INTEL_ADP_S_SATA_5,
-	PCI_DID_INTEL_ADP_S_SATA_6,
-	PCI_DID_INTEL_ADP_M_SATA_1,
-	PCI_DID_INTEL_ADP_M_SATA_2,
-	PCI_DID_INTEL_ADP_M_SATA_3,
-	PCI_DID_INTEL_APL_SATA,
-	PCI_DID_INTEL_GLK_SATA,
 	0
 };
 
diff --git a/src/soc/intel/jasperlake/chipset.cb b/src/soc/intel/jasperlake/chipset.cb
index 1a85aa8e40..4c7b8e8cd6 100644
--- a/src/soc/intel/jasperlake/chipset.cb
+++ b/src/soc/intel/jasperlake/chipset.cb
@@ -72,7 +72,7 @@ chip soc/intel/jasperlake
 		device pci 16.0 alias heci1		off end
 		device pci 16.1 alias heci2		off end
 		device pci 16.4 alias heci3		off end
-		device pci 17.0 alias sata		off end
+		device pci 17.0 alias sata		off ops sata_ops end
 		device pci 19.0 alias i2c4		off ops i2c_dev_ops end
 		device pci 19.1 alias i2c5		off ops i2c_dev_ops end
 		device pci 19.2 alias uart2		off end
diff --git a/src/soc/intel/meteorlake/chipset.cb b/src/soc/intel/meteorlake/chipset.cb
index 57c82b3b61..01ab3c134f 100644
--- a/src/soc/intel/meteorlake/chipset.cb
+++ b/src/soc/intel/meteorlake/chipset.cb
@@ -162,7 +162,7 @@ chip soc/intel/meteorlake
 		device pci 16.1 alias heci2 off end
 		device pci 16.4 alias heci3 off end
 		device pci 16.5 alias heci4 off end
-		device pci 17.0 alias sata off end
+		device pci 17.0 alias sata off ops sata_ops end
 		device pci 18.0 alias eheci1 off end
 		device pci 18.1 alias eheci2 off end
 		device pci 18.2 alias eheci3 off end
diff --git a/src/soc/intel/tigerlake/chipset.cb b/src/soc/intel/tigerlake/chipset.cb
index 38cfc0dca1..a75057a4e9 100644
--- a/src/soc/intel/tigerlake/chipset.cb
+++ b/src/soc/intel/tigerlake/chipset.cb
@@ -125,7 +125,7 @@ chip soc/intel/tigerlake
 		device pci 16.3 alias csme2 off end
 		device pci 16.4 alias heci3 off end
 		device pci 16.5 alias heci4 off end
-		device pci 17.0 alias sata off end
+		device pci 17.0 alias sata off ops sata_ops end
 		device pci 19.0 alias i2c4 off ops i2c_dev_ops end
 		device pci 19.1 alias i2c5 off ops i2c_dev_ops end
 		device pci 19.2 alias uart2 off end
diff --git a/src/soc/intel/tigerlake/chipset_pch_h.cb b/src/soc/intel/tigerlake/chipset_pch_h.cb
index a43778794c..45fd63403c 100644
--- a/src/soc/intel/tigerlake/chipset_pch_h.cb
+++ b/src/soc/intel/tigerlake/chipset_pch_h.cb
@@ -147,7 +147,7 @@ chip soc/intel/tigerlake
 		device pci 16.3 alias csme2 off end
 		device pci 16.4 alias heci3 off end
 		device pci 16.5 alias heci4 off end
-		device pci 17.0 alias sata off end
+		device pci 17.0 alias sata off ops sata_ops end
 		device pci 19.0 alias i2c4 off ops i2c_dev_ops end
 		device pci 19.1 alias i2c5 off ops i2c_dev_ops end
 		device pci 19.2 alias uart2 off end

From d1e1d36fff09b5242246d183bf8f745fcebeb35e Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Sun, 25 Jan 2026 19:08:51 -0600
Subject: [PATCH 3174/3886] soc/intel: Use chipset.cb for UART device ops
 linking

Move UART device operations linking from PCI Device ID matching
to chipset.cb files for all Intel SoCs that have them, matching the
approach used by Skylake.

Remove corresponding DIDs from uart.c for these SoCs; keep DID
matching only for SoCs without chipset.cb files.

This standardizes the approach across Intel SoCs and makes the
UART controller configuration explicit in devicetree, and prevents
the endless proliferation of DIDs in the common driver code.

Change-Id: Id26dad7997d64bcaad53fa39be23e52cb47dcc1d
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90916
Reviewed-by: Jakub "Kuba" Czapiga <czapiga@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/soc/intel/alderlake/chipset.cb        |  6 +-
 src/soc/intel/alderlake/chipset_pch_s.cb  |  8 +--
 src/soc/intel/apollolake/chipset_apl.cb   |  8 +--
 src/soc/intel/apollolake/chipset_glk.cb   |  8 +--
 src/soc/intel/cannonlake/chipset.cb       |  6 +-
 src/soc/intel/cannonlake/chipset_pch_h.cb |  4 +-
 src/soc/intel/common/block/uart/uart.c    | 71 -----------------------
 src/soc/intel/jasperlake/chipset.cb       |  6 +-
 src/soc/intel/meteorlake/chipset.cb       |  6 +-
 src/soc/intel/pantherlake/chipset_ptl.cb  |  6 +-
 src/soc/intel/pantherlake/chipset_wcl.cb  |  6 +-
 src/soc/intel/tigerlake/chipset.cb        |  6 +-
 src/soc/intel/tigerlake/chipset_pch_h.cb  |  8 +--
 13 files changed, 39 insertions(+), 110 deletions(-)

diff --git a/src/soc/intel/alderlake/chipset.cb b/src/soc/intel/alderlake/chipset.cb
index 1758d9df74..4c925b4677 100644
--- a/src/soc/intel/alderlake/chipset.cb
+++ b/src/soc/intel/alderlake/chipset.cb
@@ -245,7 +245,7 @@ chip soc/intel/alderlake
 		device pci 17.0 alias sata off ops sata_ops end
 		device pci 19.0 alias i2c4 off ops i2c_dev_ops end
 		device pci 19.1 alias i2c5 off ops i2c_dev_ops end
-		device pci 19.2 alias uart2 off end
+		device pci 19.2 alias uart2 off ops uart_ops end
 		# eMMC device is applicable only for ADL-N
 		device pci 1a.0 alias emmc off end
 		device pci 1c.0 alias pcie_rp1 off ops pcie_rp_ops end
@@ -260,8 +260,8 @@ chip soc/intel/alderlake
 		device pci 1d.1 alias pcie_rp10 off ops pcie_rp_ops end
 		device pci 1d.2 alias pcie_rp11 off ops pcie_rp_ops end
 		device pci 1d.3 alias pcie_rp12 off ops pcie_rp_ops end
-		device pci 1e.0 alias uart0 off end
-		device pci 1e.1 alias uart1 off end
+		device pci 1e.0 alias uart0 off ops uart_ops end
+		device pci 1e.1 alias uart1 off ops uart_ops end
 		device pci 1e.2 alias gspi0 off end
 		device pci 1e.3 alias gspi1 off end
 		device pci 1f.0 alias pch_espi on end
diff --git a/src/soc/intel/alderlake/chipset_pch_s.cb b/src/soc/intel/alderlake/chipset_pch_s.cb
index 28dbc9e458..90395a9cf6 100644
--- a/src/soc/intel/alderlake/chipset_pch_s.cb
+++ b/src/soc/intel/alderlake/chipset_pch_s.cb
@@ -277,7 +277,7 @@ chip soc/intel/alderlake
 		device pci 09.0 alias north_tracehub off end
 		device pci 0a.0 alias crashlog on end
 		device pci 0e.0 alias vmd off end
-		device pci 11.0 alias uart3 off end
+		device pci 11.0 alias uart3 off ops uart_ops end
 		device pci 12.0 alias ish off end
 		device pci 12.6 alias gspi2 off end
 		device pci 13.0 alias gspi3 off end
@@ -376,7 +376,7 @@ chip soc/intel/alderlake
 		device pci 17.0 alias sata off ops sata_ops end
 		device pci 19.0 alias i2c4 off ops i2c_dev_ops end
 		device pci 19.1 alias i2c5 off ops i2c_dev_ops end
-		device pci 19.2 alias uart2 off end
+		device pci 19.2 alias uart2 off ops uart_ops end
 		device pci 1a.0 alias pcie_rp25 off ops pcie_rp_ops end
 		device pci 1a.1 alias pcie_rp26 off ops pcie_rp_ops end
 		device pci 1a.2 alias pcie_rp27 off ops pcie_rp_ops end
@@ -405,8 +405,8 @@ chip soc/intel/alderlake
 		device pci 1d.5 alias pcie_rp14 off ops pcie_rp_ops end
 		device pci 1d.6 alias pcie_rp15 off ops pcie_rp_ops end
 		device pci 1d.7 alias pcie_rp16 off ops pcie_rp_ops end
-		device pci 1e.0 alias uart0 off end
-		device pci 1e.1 alias uart1 off end
+		device pci 1e.0 alias uart0 off ops uart_ops end
+		device pci 1e.1 alias uart1 off ops uart_ops end
 		device pci 1e.2 alias gspi0 off end
 		device pci 1e.3 alias gspi1 off end
 		device pci 1f.0 alias pch_espi on end
diff --git a/src/soc/intel/apollolake/chipset_apl.cb b/src/soc/intel/apollolake/chipset_apl.cb
index 10d2b04cfe..f0ffffc269 100644
--- a/src/soc/intel/apollolake/chipset_apl.cb
+++ b/src/soc/intel/apollolake/chipset_apl.cb
@@ -32,10 +32,10 @@ chip soc/intel/apollolake
 		device pci 17.1 alias i2c5		off ops i2c_dev_ops end # I2C5
 		device pci 17.2 alias i2c6		off ops i2c_dev_ops end # I2C6
 		device pci 17.3 alias i2c7		off ops i2c_dev_ops end # I2C7
-		device pci 18.0 alias uart0		off	end # UART0
-		device pci 18.1 alias uart1		off	end # UART1
-		device pci 18.2 alias uart2		off	end # UART2
-		device pci 18.3 alias uart3		off	end # UART3
+		device pci 18.0 alias uart0		off ops uart_ops end # UART0
+		device pci 18.1 alias uart1		off ops uart_ops end # UART1
+		device pci 18.2 alias uart2		off ops uart_ops end # UART2
+		device pci 18.3 alias uart3		off ops uart_ops end # UART3
 		device pci 19.0 alias spi0		off	end # SPI0
 		device pci 19.1 alias spi1		off	end # SPI1
 		device pci 19.2 alias spi2		off	end # SPI3
diff --git a/src/soc/intel/apollolake/chipset_glk.cb b/src/soc/intel/apollolake/chipset_glk.cb
index 7d1bb35ba4..8e534e4e2f 100644
--- a/src/soc/intel/apollolake/chipset_glk.cb
+++ b/src/soc/intel/apollolake/chipset_glk.cb
@@ -33,10 +33,10 @@ chip soc/intel/apollolake
 		device pci 17.1 alias i2c5		off ops i2c_dev_ops end # I2C5
 		device pci 17.2 alias i2c6		off ops i2c_dev_ops end # I2C6
 		device pci 17.3 alias i2c7		off ops i2c_dev_ops end # I2C7
-		device pci 18.0 alias uart0		off	end # UART0
-		device pci 18.1 alias uart1		off	end # UART1
-		device pci 18.2 alias uart2		off	end # UART2
-		device pci 18.3 alias uart3		off	end # UART3
+		device pci 18.0 alias uart0		off ops uart_ops end # UART0
+		device pci 18.1 alias uart1		off ops uart_ops end # UART1
+		device pci 18.2 alias uart2		off ops uart_ops end # UART2
+		device pci 18.3 alias uart3		off ops uart_ops end # UART3
 		device pci 19.0 alias spi0		off	end # SPI0
 		device pci 19.1 alias spi1		off	end # SPI1
 		device pci 19.2 alias spi2		off	end # SPI3
diff --git a/src/soc/intel/cannonlake/chipset.cb b/src/soc/intel/cannonlake/chipset.cb
index d55036e7fa..20a7250794 100644
--- a/src/soc/intel/cannonlake/chipset.cb
+++ b/src/soc/intel/cannonlake/chipset.cb
@@ -95,7 +95,7 @@ chip soc/intel/cannonlake
 		device pci 17.0 alias sata         off ops sata_ops end	# SATA
 		device pci 19.0 alias i2c4         off ops i2c_dev_ops end	# I2C #4
 		device pci 19.1 alias i2c5         off ops i2c_dev_ops end	# I2C #5
-		device pci 19.2 alias uart2        off	end	# UART #2
+		device pci 19.2 alias uart2        off ops uart_ops end	# UART #2
 		device pci 1a.0 alias emmc         off	end	# eMMC
 		device pci 1c.0 alias pcie_rp1     off ops pcie_rp_ops	end	# PCI Express Port 1
 		device pci 1c.1 alias pcie_rp2     off ops pcie_rp_ops	end	# PCI Express Port 2
@@ -113,8 +113,8 @@ chip soc/intel/cannonlake
 		device pci 1d.5 alias pcie_rp14    off ops pcie_rp_ops	end	# PCI Express Port 14
 		device pci 1d.6 alias pcie_rp15    off ops pcie_rp_ops	end	# PCI Express Port 15
 		device pci 1d.7 alias pcie_rp16    off ops pcie_rp_ops	end	# PCI Express Port 16
-		device pci 1e.0 alias uart0        off	end	# UART #0
-		device pci 1e.1 alias uart1        off	end	# UART #1
+		device pci 1e.0 alias uart0        off ops uart_ops end	# UART #0
+		device pci 1e.1 alias uart1        off ops uart_ops end	# UART #1
 		device pci 1e.2 alias gspi0        off	end	# GSPI #0
 		device pci 1e.3 alias gspi1        off	end	# GSPI #1
 		device pci 1f.0 alias lpc_espi     on	end	# LPC Interface
diff --git a/src/soc/intel/cannonlake/chipset_pch_h.cb b/src/soc/intel/cannonlake/chipset_pch_h.cb
index fb9c67ca46..76648c0ca0 100644
--- a/src/soc/intel/cannonlake/chipset_pch_h.cb
+++ b/src/soc/intel/cannonlake/chipset_pch_h.cb
@@ -147,8 +147,8 @@ chip soc/intel/cannonlake
 		device pci 1d.5 alias pcie_rp14    off ops pcie_rp_ops	end	# PCI Express Port 14
 		device pci 1d.6 alias pcie_rp15    off ops pcie_rp_ops	end	# PCI Express Port 15
 		device pci 1d.7 alias pcie_rp16    off ops pcie_rp_ops	end	# PCI Express Port 16
-		device pci 1e.0 alias uart0        off	end	# UART #0
-		device pci 1e.1 alias uart1        off	end	# UART #1
+		device pci 1e.0 alias uart0        off ops uart_ops end	# UART #0
+		device pci 1e.1 alias uart1        off ops uart_ops end	# UART #1
 		device pci 1e.2 alias gspi0        off	end	# GSPI #0
 		device pci 1e.3 alias gspi1        off	end	# GSPI #1
 		device pci 1f.0 alias lpc_espi     on	end	# LPC Interface
diff --git a/src/soc/intel/common/block/uart/uart.c b/src/soc/intel/common/block/uart/uart.c
index 2b2c8c28fc..f16d337e64 100644
--- a/src/soc/intel/common/block/uart/uart.c
+++ b/src/soc/intel/common/block/uart/uart.c
@@ -366,83 +366,12 @@ static const unsigned short pci_device_ids[] = {
 	PCI_DID_INTEL_NVL_UART0,
 	PCI_DID_INTEL_NVL_UART1,
 	PCI_DID_INTEL_NVL_UART2,
-	PCI_DID_INTEL_WCL_UART0,
-	PCI_DID_INTEL_WCL_UART1,
-	PCI_DID_INTEL_WCL_UART2,
-	PCI_DID_INTEL_PTL_H_UART0,
-	PCI_DID_INTEL_PTL_H_UART1,
-	PCI_DID_INTEL_PTL_H_UART2,
-	PCI_DID_INTEL_PTL_U_H_UART0,
-	PCI_DID_INTEL_PTL_U_H_UART1,
-	PCI_DID_INTEL_PTL_U_H_UART2,
 	PCI_DID_INTEL_LNL_UART0,
 	PCI_DID_INTEL_LNL_UART1,
 	PCI_DID_INTEL_LNL_UART2,
-	PCI_DID_INTEL_MTL_UART0,
-	PCI_DID_INTEL_MTL_UART1,
-	PCI_DID_INTEL_MTL_UART2,
-	PCI_DID_INTEL_ARL_UART0,
-	PCI_DID_INTEL_ARL_UART1,
-	PCI_DID_INTEL_ARL_UART2,
-	PCI_DID_INTEL_ARP_S_UART0,
-	PCI_DID_INTEL_ARP_S_UART1,
-	PCI_DID_INTEL_ARP_S_UART2,
-	PCI_DID_INTEL_ARP_S_UART3,
-	PCI_DID_INTEL_APL_UART0,
-	PCI_DID_INTEL_APL_UART1,
-	PCI_DID_INTEL_APL_UART2,
-	PCI_DID_INTEL_APL_UART3,
-	PCI_DID_INTEL_CNL_UART0,
-	PCI_DID_INTEL_CNL_UART1,
-	PCI_DID_INTEL_CNL_UART2,
-	PCI_DID_INTEL_GLK_UART0,
-	PCI_DID_INTEL_GLK_UART1,
-	PCI_DID_INTEL_GLK_UART2,
-	PCI_DID_INTEL_GLK_UART3,
-	PCI_DID_INTEL_CNP_H_UART0,
-	PCI_DID_INTEL_CNP_H_UART1,
-	PCI_DID_INTEL_CNP_H_UART2,
-	PCI_DID_INTEL_CMP_UART0,
-	PCI_DID_INTEL_CMP_UART1,
-	PCI_DID_INTEL_CMP_UART2,
-	PCI_DID_INTEL_CMP_H_UART0,
-	PCI_DID_INTEL_CMP_H_UART1,
-	PCI_DID_INTEL_CMP_H_UART2,
-	PCI_DID_INTEL_TGP_UART0,
-	PCI_DID_INTEL_TGP_UART1,
-	PCI_DID_INTEL_TGP_UART2,
-	PCI_DID_INTEL_TGP_H_UART0,
-	PCI_DID_INTEL_TGP_H_UART1,
-	PCI_DID_INTEL_TGP_H_UART2,
-	PCI_DID_INTEL_TGP_H_UART3,
 	PCI_DID_INTEL_MCC_UART0,
 	PCI_DID_INTEL_MCC_UART1,
 	PCI_DID_INTEL_MCC_UART2,
-	PCI_DID_INTEL_JSP_UART0,
-	PCI_DID_INTEL_JSP_UART1,
-	PCI_DID_INTEL_JSP_UART2,
-	PCI_DID_INTEL_ADP_S_UART0,
-	PCI_DID_INTEL_ADP_S_UART1,
-	PCI_DID_INTEL_ADP_S_UART2,
-	PCI_DID_INTEL_ADP_S_UART3,
-	PCI_DID_INTEL_ADP_S_UART4,
-	PCI_DID_INTEL_ADP_S_UART5,
-	PCI_DID_INTEL_ADP_S_UART6,
-	PCI_DID_INTEL_ADP_P_UART0,
-	PCI_DID_INTEL_ADP_P_UART1,
-	PCI_DID_INTEL_ADP_P_UART2,
-	PCI_DID_INTEL_ADP_P_UART3,
-	PCI_DID_INTEL_ADP_P_UART4,
-	PCI_DID_INTEL_ADP_P_UART5,
-	PCI_DID_INTEL_ADP_P_UART6,
-	PCI_DID_INTEL_ADP_M_N_UART0,
-	PCI_DID_INTEL_ADP_M_N_UART1,
-	PCI_DID_INTEL_ADP_M_N_UART2,
-	PCI_DID_INTEL_ADP_M_N_UART3,
-	PCI_DID_INTEL_RPP_S_UART0,
-	PCI_DID_INTEL_RPP_S_UART1,
-	PCI_DID_INTEL_RPP_S_UART2,
-	PCI_DID_INTEL_RPP_S_UART3,
 	0,
 };
 
diff --git a/src/soc/intel/jasperlake/chipset.cb b/src/soc/intel/jasperlake/chipset.cb
index 4c7b8e8cd6..49cb3d2e98 100644
--- a/src/soc/intel/jasperlake/chipset.cb
+++ b/src/soc/intel/jasperlake/chipset.cb
@@ -75,7 +75,7 @@ chip soc/intel/jasperlake
 		device pci 17.0 alias sata		off ops sata_ops end
 		device pci 19.0 alias i2c4		off ops i2c_dev_ops end
 		device pci 19.1 alias i2c5		off ops i2c_dev_ops end
-		device pci 19.2 alias uart2		off end
+		device pci 19.2 alias uart2		off ops uart_ops end
 		device pci 1a.0 alias emmc		off end
 		device pci 1c.0 alias pcie_rp1		off ops pcie_rp_ops end
 		device pci 1c.1 alias pcie_rp2		off ops pcie_rp_ops end
@@ -85,8 +85,8 @@ chip soc/intel/jasperlake
 		device pci 1c.5 alias pcie_rp6		off ops pcie_rp_ops end
 		device pci 1c.6 alias pcie_rp7		off ops pcie_rp_ops end
 		device pci 1c.7 alias pcie_rp8		off ops pcie_rp_ops end
-		device pci 1e.0 alias uart0		off end
-		device pci 1e.1 alias uart1		off end
+		device pci 1e.0 alias uart0		off ops uart_ops end
+		device pci 1e.1 alias uart1		off ops uart_ops end
 		device pci 1e.2 alias gspi0		off end
 		device pci 1e.3 alias gspi1		off end
 		device pci 1f.0 alias pch_espi		on  end
diff --git a/src/soc/intel/meteorlake/chipset.cb b/src/soc/intel/meteorlake/chipset.cb
index 01ab3c134f..8abfa1261d 100644
--- a/src/soc/intel/meteorlake/chipset.cb
+++ b/src/soc/intel/meteorlake/chipset.cb
@@ -168,7 +168,7 @@ chip soc/intel/meteorlake
 		device pci 18.2 alias eheci3 off end
 		device pci 19.0 alias i2c4 off ops i2c_dev_ops end
 		device pci 19.1 alias i2c5 off ops i2c_dev_ops end
-		device pci 19.2 alias uart2 off end
+		device pci 19.2 alias uart2 off ops uart_ops end
 		device pci 1c.0 alias pcie_rp1 off ops pcie_rp_ops end
 		device pci 1c.1 alias pcie_rp2 off ops pcie_rp_ops end
 		device pci 1c.2 alias pcie_rp3 off ops pcie_rp_ops end
@@ -177,8 +177,8 @@ chip soc/intel/meteorlake
 		device pci 1c.5 alias pcie_rp6 off ops pcie_rp_ops end
 		device pci 1c.6 alias pcie_rp7 off ops pcie_rp_ops end
 		device pci 1c.7 alias pcie_rp8 off ops pcie_rp_ops end
-		device pci 1e.0 alias uart0 off end
-		device pci 1e.1 alias uart1 off end
+		device pci 1e.0 alias uart0 off ops uart_ops end
+		device pci 1e.1 alias uart1 off ops uart_ops end
 		device pci 1e.2 alias gspi0 off end
 		device pci 1e.3 alias gspi1 off end
 		device pci 1e.4 alias tsn_gbe1 off end
diff --git a/src/soc/intel/pantherlake/chipset_ptl.cb b/src/soc/intel/pantherlake/chipset_ptl.cb
index e45558b4ec..4540ce7a08 100644
--- a/src/soc/intel/pantherlake/chipset_ptl.cb
+++ b/src/soc/intel/pantherlake/chipset_ptl.cb
@@ -228,7 +228,7 @@ chip soc/intel/pantherlake
 		device pci 18.2 alias eheci3 off end
 		device pci 19.0 alias i2c4 off ops i2c_dev_ops end
 		device pci 19.1 alias i2c5 off ops i2c_dev_ops end
-		device pci 19.2 alias uart2 off end
+		device pci 19.2 alias uart2 off ops uart_ops end
 		device pci 1c.0 alias pcie_rp1 off ops pcie_rp_ops end
 		device pci 1c.1 alias pcie_rp2 off ops pcie_rp_ops end
 		device pci 1c.2 alias pcie_rp3 off ops pcie_rp_ops end
@@ -237,8 +237,8 @@ chip soc/intel/pantherlake
 		device pci 1c.5 alias pcie_rp6 off ops pcie_rp_ops end
 		device pci 1c.6 alias pcie_rp7 off ops pcie_rp_ops end
 		device pci 1c.7 alias pcie_rp8 off ops pcie_rp_ops end
-		device pci 1e.0 alias uart0 off end
-		device pci 1e.1 alias uart1 off end
+		device pci 1e.0 alias uart0 off ops uart_ops end
+		device pci 1e.1 alias uart1 off ops uart_ops end
 		device pci 1e.2 alias gspi0 off end
 		device pci 1e.3 alias gspi1 off end
 		device pci 1f.0 alias soc_espi on end
diff --git a/src/soc/intel/pantherlake/chipset_wcl.cb b/src/soc/intel/pantherlake/chipset_wcl.cb
index 3d4f641260..b2ec967c75 100644
--- a/src/soc/intel/pantherlake/chipset_wcl.cb
+++ b/src/soc/intel/pantherlake/chipset_wcl.cb
@@ -115,13 +115,13 @@ chip soc/intel/pantherlake
 		device pci 18.2 alias eheci3 off end
 		device pci 19.0 alias i2c4 off ops i2c_dev_ops end
 		device pci 19.1 alias i2c5 off ops i2c_dev_ops end
-		device pci 19.2 alias uart2 off end
+		device pci 19.2 alias uart2 off ops uart_ops end
 		device pci 1c.0 alias pcie_rp1 off ops pcie_rp_ops end
 		device pci 1c.1 alias pcie_rp2 off ops pcie_rp_ops end
 		device pci 1c.2 alias pcie_rp3 off ops pcie_rp_ops end
 		device pci 1c.3 alias pcie_rp4 off ops pcie_rp_ops end
-		device pci 1e.0 alias uart0 off end
-		device pci 1e.1 alias uart1 off end
+		device pci 1e.0 alias uart0 off ops uart_ops end
+		device pci 1e.1 alias uart1 off ops uart_ops end
 		device pci 1e.2 alias gspi0 off end
 		device pci 1e.3 alias gspi1 off end
 		device pci 1f.0 alias soc_espi on end
diff --git a/src/soc/intel/tigerlake/chipset.cb b/src/soc/intel/tigerlake/chipset.cb
index a75057a4e9..4258988603 100644
--- a/src/soc/intel/tigerlake/chipset.cb
+++ b/src/soc/intel/tigerlake/chipset.cb
@@ -128,7 +128,7 @@ chip soc/intel/tigerlake
 		device pci 17.0 alias sata off ops sata_ops end
 		device pci 19.0 alias i2c4 off ops i2c_dev_ops end
 		device pci 19.1 alias i2c5 off ops i2c_dev_ops end
-		device pci 19.2 alias uart2 off end
+		device pci 19.2 alias uart2 off ops uart_ops end
 		device pci 1c.0 alias pcie_rp1 off ops pcie_rp_ops end
 		device pci 1c.1 alias pcie_rp2 off ops pcie_rp_ops end
 		device pci 1c.2 alias pcie_rp3 off ops pcie_rp_ops end
@@ -141,8 +141,8 @@ chip soc/intel/tigerlake
 		device pci 1d.1 alias pcie_rp10 off ops pcie_rp_ops end
 		device pci 1d.2 alias pcie_rp11 off ops pcie_rp_ops end
 		device pci 1d.3 alias pcie_rp12 off ops pcie_rp_ops end
-		device pci 1e.0 alias uart0 off end
-		device pci 1e.1 alias uart1 off end
+		device pci 1e.0 alias uart0 off ops uart_ops end
+		device pci 1e.1 alias uart1 off ops uart_ops end
 		device pci 1e.2 alias gspi0 off end
 		device pci 1e.3 alias gspi1 off end
 		device pci 1f.0 alias pch_espi on end
diff --git a/src/soc/intel/tigerlake/chipset_pch_h.cb b/src/soc/intel/tigerlake/chipset_pch_h.cb
index 45fd63403c..c980f62f1c 100644
--- a/src/soc/intel/tigerlake/chipset_pch_h.cb
+++ b/src/soc/intel/tigerlake/chipset_pch_h.cb
@@ -62,7 +62,7 @@ chip soc/intel/tigerlake
 		device pci 0e.0 alias vmd off end
 		device pci 10.6 alias thc0 off end
 		device pci 10.7 alias thc1 off end
-		device pci 11.0 alias uart3 off end
+		device pci 11.0 alias uart3 off ops uart_ops end
 		device pci 11.3 alias i2c6 off ops i2c_dev_ops end
 		device pci 12.0 alias ish off end
 		device pci 12.6 alias gspi2 off end
@@ -150,7 +150,7 @@ chip soc/intel/tigerlake
 		device pci 17.0 alias sata off ops sata_ops end
 		device pci 19.0 alias i2c4 off ops i2c_dev_ops end
 		device pci 19.1 alias i2c5 off ops i2c_dev_ops end
-		device pci 19.2 alias uart2 off end
+		device pci 19.2 alias uart2 off ops uart_ops end
 		device pci 1b.0 alias pcie_rp17 off ops pcie_rp_ops end
 		device pci 1b.1 alias pcie_rp18 off ops pcie_rp_ops end
 		device pci 1b.2 alias pcie_rp19 off ops pcie_rp_ops end
@@ -175,8 +175,8 @@ chip soc/intel/tigerlake
 		device pci 1d.5 alias pcie_rp14 off ops pcie_rp_ops end
 		device pci 1d.6 alias pcie_rp15 off ops pcie_rp_ops end
 		device pci 1d.7 alias pcie_rp16 off ops pcie_rp_ops end
-		device pci 1e.0 alias uart0 off end
-		device pci 1e.1 alias uart1 off end
+		device pci 1e.0 alias uart0 off ops uart_ops end
+		device pci 1e.1 alias uart1 off ops uart_ops end
 		device pci 1e.2 alias gspi0 off end
 		device pci 1e.3 alias gspi1 off end
 		device pci 1f.0 alias pch_espi on end

From e519cacd26de2b2cc60fa5528efc8e2c1636c00d Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Sun, 25 Jan 2026 19:11:20 -0600
Subject: [PATCH 3175/3886] soc/intel: Use chipset.cb for GSPI device ops
 linking

Move GSPI/SPI device operations linking from PCI Device ID matching
to chipset.cb files for all Intel SoCs that have them, matching the
approach used by Skylake.

Remove corresponding DIDs from spi.c for these SoCs; keep DID
matching only for SoCs without chipset.cb files.

This standardizes the approach across Intel SoCs and makes the
GSPI/SPI controller configuration explicit in devicetree, and prevents
the endless proliferation of DIDs in the common driver code.

Change-Id: Ia379cff36a5b277d89cad757edc094a5d786a51b
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90917
Reviewed-by: Jakub "Kuba" Czapiga <czapiga@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/soc/intel/alderlake/chipset.cb        |  8 +--
 src/soc/intel/alderlake/chipset_pch_s.cb  |  8 +--
 src/soc/intel/apollolake/chipset_apl.cb   |  6 +-
 src/soc/intel/apollolake/chipset_glk.cb   |  6 +-
 src/soc/intel/cannonlake/chipset.cb       |  6 +-
 src/soc/intel/cannonlake/chipset_pch_h.cb |  6 +-
 src/soc/intel/common/block/spi/spi.c      | 76 -----------------------
 src/soc/intel/jasperlake/chipset.cb       |  6 +-
 src/soc/intel/meteorlake/chipset.cb       |  6 +-
 src/soc/intel/pantherlake/chipset_ptl.cb  |  6 +-
 src/soc/intel/pantherlake/chipset_wcl.cb  |  6 +-
 src/soc/intel/tigerlake/chipset.cb        |  8 +--
 src/soc/intel/tigerlake/chipset_pch_h.cb  |  8 +--
 13 files changed, 40 insertions(+), 116 deletions(-)

diff --git a/src/soc/intel/alderlake/chipset.cb b/src/soc/intel/alderlake/chipset.cb
index 4c925b4677..36685783a2 100644
--- a/src/soc/intel/alderlake/chipset.cb
+++ b/src/soc/intel/alderlake/chipset.cb
@@ -177,9 +177,9 @@ chip soc/intel/alderlake
 		device pci 10.6 alias thc0 off end
 		device pci 10.7 alias thc1 off end
 		device pci 12.0 alias ish off end
-		device pci 12.6 alias gspi2 off end
+		device pci 12.6 alias gspi2 off ops spi_dev_ops end
 		device pci 12.7 alias ufs off end
-		device pci 13.0 alias gspi3 off end
+		device pci 13.0 alias gspi3 off ops spi_dev_ops end
 		device pci 14.0 alias xhci off
 			chip drivers/usb/acpi
 				register "type" = "UPC_TYPE_HUB"
@@ -262,8 +262,8 @@ chip soc/intel/alderlake
 		device pci 1d.3 alias pcie_rp12 off ops pcie_rp_ops end
 		device pci 1e.0 alias uart0 off ops uart_ops end
 		device pci 1e.1 alias uart1 off ops uart_ops end
-		device pci 1e.2 alias gspi0 off end
-		device pci 1e.3 alias gspi1 off end
+		device pci 1e.2 alias gspi0 off ops spi_dev_ops end
+		device pci 1e.3 alias gspi1 off ops spi_dev_ops end
 		device pci 1f.0 alias pch_espi on end
 		device pci 1f.1 alias p2sb hidden end
 		device pci 1f.2 alias pmc hidden end
diff --git a/src/soc/intel/alderlake/chipset_pch_s.cb b/src/soc/intel/alderlake/chipset_pch_s.cb
index 90395a9cf6..a7f2b64399 100644
--- a/src/soc/intel/alderlake/chipset_pch_s.cb
+++ b/src/soc/intel/alderlake/chipset_pch_s.cb
@@ -279,8 +279,8 @@ chip soc/intel/alderlake
 		device pci 0e.0 alias vmd off end
 		device pci 11.0 alias uart3 off ops uart_ops end
 		device pci 12.0 alias ish off end
-		device pci 12.6 alias gspi2 off end
-		device pci 13.0 alias gspi3 off end
+		device pci 12.6 alias gspi2 off ops spi_dev_ops end
+		device pci 13.0 alias gspi3 off ops spi_dev_ops end
 		device pci 14.0 alias xhci off
 			chip drivers/usb/acpi
 				register "type" = "UPC_TYPE_HUB"
@@ -407,8 +407,8 @@ chip soc/intel/alderlake
 		device pci 1d.7 alias pcie_rp16 off ops pcie_rp_ops end
 		device pci 1e.0 alias uart0 off ops uart_ops end
 		device pci 1e.1 alias uart1 off ops uart_ops end
-		device pci 1e.2 alias gspi0 off end
-		device pci 1e.3 alias gspi1 off end
+		device pci 1e.2 alias gspi0 off ops spi_dev_ops end
+		device pci 1e.3 alias gspi1 off ops spi_dev_ops end
 		device pci 1f.0 alias pch_espi on end
 		device pci 1f.1 alias p2sb hidden end
 		device pci 1f.2 alias pmc hidden end
diff --git a/src/soc/intel/apollolake/chipset_apl.cb b/src/soc/intel/apollolake/chipset_apl.cb
index f0ffffc269..2766ef8d16 100644
--- a/src/soc/intel/apollolake/chipset_apl.cb
+++ b/src/soc/intel/apollolake/chipset_apl.cb
@@ -36,9 +36,9 @@ chip soc/intel/apollolake
 		device pci 18.1 alias uart1		off ops uart_ops end # UART1
 		device pci 18.2 alias uart2		off ops uart_ops end # UART2
 		device pci 18.3 alias uart3		off ops uart_ops end # UART3
-		device pci 19.0 alias spi0		off	end # SPI0
-		device pci 19.1 alias spi1		off	end # SPI1
-		device pci 19.2 alias spi2		off	end # SPI3
+		device pci 19.0 alias spi0		off ops spi_dev_ops end # SPI0
+		device pci 19.1 alias spi1		off ops spi_dev_ops end # SPI1
+		device pci 19.2 alias spi2		off ops spi_dev_ops end # SPI3
 		device pci 1a.0 alias pwm		off	end # PWM
 		device pci 1b.0 alias sdcard		off	end # SD Card
 		device pci 1c.0 alias emmc		off	end # eMMC
diff --git a/src/soc/intel/apollolake/chipset_glk.cb b/src/soc/intel/apollolake/chipset_glk.cb
index 8e534e4e2f..3255407abb 100644
--- a/src/soc/intel/apollolake/chipset_glk.cb
+++ b/src/soc/intel/apollolake/chipset_glk.cb
@@ -37,9 +37,9 @@ chip soc/intel/apollolake
 		device pci 18.1 alias uart1		off ops uart_ops end # UART1
 		device pci 18.2 alias uart2		off ops uart_ops end # UART2
 		device pci 18.3 alias uart3		off ops uart_ops end # UART3
-		device pci 19.0 alias spi0		off	end # SPI0
-		device pci 19.1 alias spi1		off	end # SPI1
-		device pci 19.2 alias spi2		off	end # SPI3
+		device pci 19.0 alias spi0		off ops spi_dev_ops end # SPI0
+		device pci 19.1 alias spi1		off ops spi_dev_ops end # SPI1
+		device pci 19.2 alias spi2		off ops spi_dev_ops end # SPI3
 		device pci 1a.0 alias pwm		off	end # PWM
 		device pci 1c.0 alias emmc		off	end # eMMC
 		device pci 1d.0 alias ufs		off	end # UFS
diff --git a/src/soc/intel/cannonlake/chipset.cb b/src/soc/intel/cannonlake/chipset.cb
index 20a7250794..2fd801051a 100644
--- a/src/soc/intel/cannonlake/chipset.cb
+++ b/src/soc/intel/cannonlake/chipset.cb
@@ -15,7 +15,7 @@ chip soc/intel/cannonlake
 		device pci 08.0 alias gna          off	end	# Gaussian mixture model, Neural network accelerator
 		device pci 12.0 alias thermal      off	end	# Thermal Subsystem
 		device pci 12.5 alias ufs          off	end	# UFS SCS
-		device pci 12.6 alias gspi2        off	end	# GSPI #2
+		device pci 12.6 alias gspi2        off ops spi_dev_ops end	# GSPI #2
 		device pci 13.0 alias ish          off	end	# ISH
 		device pci 14.0 alias xhci         off		# USB xHCI
 			chip drivers/usb/acpi
@@ -115,8 +115,8 @@ chip soc/intel/cannonlake
 		device pci 1d.7 alias pcie_rp16    off ops pcie_rp_ops	end	# PCI Express Port 16
 		device pci 1e.0 alias uart0        off ops uart_ops end	# UART #0
 		device pci 1e.1 alias uart1        off ops uart_ops end	# UART #1
-		device pci 1e.2 alias gspi0        off	end	# GSPI #0
-		device pci 1e.3 alias gspi1        off	end	# GSPI #1
+		device pci 1e.2 alias gspi0        off ops spi_dev_ops end	# GSPI #0
+		device pci 1e.3 alias gspi1        off ops spi_dev_ops end	# GSPI #1
 		device pci 1f.0 alias lpc_espi     on	end	# LPC Interface
 		device pci 1f.1 alias p2sb      hidden	end	# P2SB
 		device pci 1f.2 alias pmc       hidden	end	# Power Management Controller
diff --git a/src/soc/intel/cannonlake/chipset_pch_h.cb b/src/soc/intel/cannonlake/chipset_pch_h.cb
index 76648c0ca0..b00e556a2e 100644
--- a/src/soc/intel/cannonlake/chipset_pch_h.cb
+++ b/src/soc/intel/cannonlake/chipset_pch_h.cb
@@ -15,7 +15,7 @@ chip soc/intel/cannonlake
 		device pci 08.0 alias gna          off	end	# Gaussian mixture model, Neural network accelerator
 		device pci 12.0 alias thermal      off	end	# Thermal Subsystem
 		device pci 12.5 alias ufs          off	end	# UFS SCS
-		device pci 12.6 alias gspi2        off	end	# GSPI #2
+		device pci 12.6 alias gspi2        off ops spi_dev_ops end	# GSPI #2
 		device pci 13.0 alias ish          off	end	# ISH
 		device pci 14.0 alias xhci         off		# USB xHCI
 			chip drivers/usb/acpi
@@ -149,8 +149,8 @@ chip soc/intel/cannonlake
 		device pci 1d.7 alias pcie_rp16    off ops pcie_rp_ops	end	# PCI Express Port 16
 		device pci 1e.0 alias uart0        off ops uart_ops end	# UART #0
 		device pci 1e.1 alias uart1        off ops uart_ops end	# UART #1
-		device pci 1e.2 alias gspi0        off	end	# GSPI #0
-		device pci 1e.3 alias gspi1        off	end	# GSPI #1
+		device pci 1e.2 alias gspi0        off ops spi_dev_ops end	# GSPI #0
+		device pci 1e.3 alias gspi1        off ops spi_dev_ops end	# GSPI #1
 		device pci 1f.0 alias lpc_espi     on	end	# LPC Interface
 		device pci 1f.1 alias p2sb      hidden	end	# P2SB
 		device pci 1f.2 alias pmc       hidden	end	# Power Management Controller
diff --git a/src/soc/intel/common/block/spi/spi.c b/src/soc/intel/common/block/spi/spi.c
index 9ac9719c7a..5c75a2240b 100644
--- a/src/soc/intel/common/block/spi/spi.c
+++ b/src/soc/intel/common/block/spi/spi.c
@@ -127,88 +127,12 @@ static const unsigned short pci_device_ids[] = {
 	PCI_DID_INTEL_NVL_SPI0,
 	PCI_DID_INTEL_NVL_SPI1,
 	PCI_DID_INTEL_NVL_SPI2,
-	PCI_DID_INTEL_WCL_HWSEQ_SPI,
-	PCI_DID_INTEL_WCL_SPI0,
-	PCI_DID_INTEL_WCL_SPI1,
-	PCI_DID_INTEL_WCL_SPI2,
-	PCI_DID_INTEL_PTL_H_HWSEQ_SPI,
-	PCI_DID_INTEL_PTL_H_SPI0,
-	PCI_DID_INTEL_PTL_H_SPI1,
-	PCI_DID_INTEL_PTL_H_SPI2,
-	PCI_DID_INTEL_PTL_U_H_HWSEQ_SPI,
-	PCI_DID_INTEL_PTL_U_H_SPI0,
-	PCI_DID_INTEL_PTL_U_H_SPI1,
-	PCI_DID_INTEL_PTL_U_H_SPI2,
 	PCI_DID_INTEL_LNL_GSPI0,
 	PCI_DID_INTEL_LNL_GSPI1,
 	PCI_DID_INTEL_LNL_GSPI2,
-	PCI_DID_INTEL_MTL_GSPI0,
-	PCI_DID_INTEL_MTL_GSPI1,
-	PCI_DID_INTEL_MTL_GSPI2,
-	PCI_DID_INTEL_ARL_GSPI0,
-	PCI_DID_INTEL_ARL_GSPI1,
-	PCI_DID_INTEL_ARL_GSPI2,
-	PCI_DID_INTEL_ARP_S_GSPI0,
-	PCI_DID_INTEL_ARP_S_GSPI1,
-	PCI_DID_INTEL_ARP_S_GSPI2,
-	PCI_DID_INTEL_ARP_S_GSPI3,
-	PCI_DID_INTEL_APL_SPI0,
-	PCI_DID_INTEL_APL_SPI1,
-	PCI_DID_INTEL_APL_SPI2,
-	PCI_DID_INTEL_GLK_SPI0,
-	PCI_DID_INTEL_GLK_SPI1,
-	PCI_DID_INTEL_GLK_SPI2,
-	PCI_DID_INTEL_CNL_SPI0,
-	PCI_DID_INTEL_CNL_SPI1,
-	PCI_DID_INTEL_CNL_SPI2,
-	PCI_DID_INTEL_CNP_H_SPI0,
-	PCI_DID_INTEL_CNP_H_SPI1,
-	PCI_DID_INTEL_CNP_H_SPI2,
-	PCI_DID_INTEL_CMP_SPI0,
-	PCI_DID_INTEL_CMP_SPI1,
-	PCI_DID_INTEL_CMP_SPI2,
-	PCI_DID_INTEL_CMP_H_SPI0,
-	PCI_DID_INTEL_CMP_H_SPI1,
-	PCI_DID_INTEL_CMP_H_SPI2,
-	PCI_DID_INTEL_TGP_GSPI0,
-	PCI_DID_INTEL_TGP_GSPI1,
-	PCI_DID_INTEL_TGP_GSPI2,
-	PCI_DID_INTEL_TGP_GSPI3,
-	PCI_DID_INTEL_TGP_GSPI4,
-	PCI_DID_INTEL_TGP_GSPI5,
-	PCI_DID_INTEL_TGP_GSPI6,
-	PCI_DID_INTEL_TGP_H_SPI0,
-	PCI_DID_INTEL_TGP_H_GSPI0,
-	PCI_DID_INTEL_TGP_H_GSPI1,
-	PCI_DID_INTEL_TGP_H_GSPI2,
-	PCI_DID_INTEL_TGP_H_GSPI3,
 	PCI_DID_INTEL_MCC_GSPI0,
 	PCI_DID_INTEL_MCC_GSPI1,
 	PCI_DID_INTEL_MCC_GSPI2,
-	PCI_DID_INTEL_JSP_SPI0,
-	PCI_DID_INTEL_JSP_SPI1,
-	PCI_DID_INTEL_JSP_SPI2,
-	PCI_DID_INTEL_ADP_P_SPI0,
-	PCI_DID_INTEL_ADP_P_SPI1,
-	PCI_DID_INTEL_ADP_P_SPI2,
-	PCI_DID_INTEL_ADP_P_SPI3,
-	PCI_DID_INTEL_ADP_P_SPI4,
-	PCI_DID_INTEL_ADP_P_SPI5,
-	PCI_DID_INTEL_ADP_P_SPI6,
-	PCI_DID_INTEL_ADP_S_SPI0,
-	PCI_DID_INTEL_ADP_S_SPI1,
-	PCI_DID_INTEL_ADP_S_SPI2,
-	PCI_DID_INTEL_ADP_S_SPI3,
-	PCI_DID_INTEL_ADP_S_SPI4,
-	PCI_DID_INTEL_ADP_S_SPI5,
-	PCI_DID_INTEL_ADP_S_SPI6,
-	PCI_DID_INTEL_ADP_M_N_SPI0,
-	PCI_DID_INTEL_ADP_M_N_SPI1,
-	PCI_DID_INTEL_ADP_M_SPI2,
-	PCI_DID_INTEL_RPP_S_SPI0,
-	PCI_DID_INTEL_RPP_S_SPI1,
-	PCI_DID_INTEL_RPP_S_SPI2,
-	PCI_DID_INTEL_RPP_S_SPI3,
 	PCI_DID_INTEL_DNV_SPI,
 	0
 };
diff --git a/src/soc/intel/jasperlake/chipset.cb b/src/soc/intel/jasperlake/chipset.cb
index 49cb3d2e98..6d50296019 100644
--- a/src/soc/intel/jasperlake/chipset.cb
+++ b/src/soc/intel/jasperlake/chipset.cb
@@ -11,7 +11,7 @@ chip soc/intel/jasperlake
 		device pci 09.0 alias north_tracehub	off end
 		device pci 12.0 alias ish		off end
 		device pci 12.5 alias ufs_scs		off end
-		device pci 12.6 alias gspi2		off end
+		device pci 12.6 alias gspi2		off ops spi_dev_ops end
 		device pci 14.0 alias south_xhci	off
 			chip drivers/usb/acpi
 				register "type" = "UPC_TYPE_HUB"
@@ -87,8 +87,8 @@ chip soc/intel/jasperlake
 		device pci 1c.7 alias pcie_rp8		off ops pcie_rp_ops end
 		device pci 1e.0 alias uart0		off ops uart_ops end
 		device pci 1e.1 alias uart1		off ops uart_ops end
-		device pci 1e.2 alias gspi0		off end
-		device pci 1e.3 alias gspi1		off end
+		device pci 1e.2 alias gspi0		off ops spi_dev_ops end
+		device pci 1e.3 alias gspi1		off ops spi_dev_ops end
 		device pci 1f.0 alias pch_espi		on  end
 		device pci 1f.1 alias p2sb		hidden end
 		device pci 1f.2 alias pmc		hidden end
diff --git a/src/soc/intel/meteorlake/chipset.cb b/src/soc/intel/meteorlake/chipset.cb
index 8abfa1261d..1efa776ec0 100644
--- a/src/soc/intel/meteorlake/chipset.cb
+++ b/src/soc/intel/meteorlake/chipset.cb
@@ -94,7 +94,7 @@ chip soc/intel/meteorlake
 		device pci 10.0 alias thc0 off end
 		device pci 10.1 alias thc1 off end
 		device pci 12.0 alias ish off end
-		device pci 12.6 alias gspi2 off end
+		device pci 12.6 alias gspi2 off ops spi_dev_ops end
 		device pci 12.7 alias ufs off end
 		device pci 13.0 alias ioe_p2sb hidden end
 		device pci 13.1 alias ieh2 off end
@@ -179,8 +179,8 @@ chip soc/intel/meteorlake
 		device pci 1c.7 alias pcie_rp8 off ops pcie_rp_ops end
 		device pci 1e.0 alias uart0 off ops uart_ops end
 		device pci 1e.1 alias uart1 off ops uart_ops end
-		device pci 1e.2 alias gspi0 off end
-		device pci 1e.3 alias gspi1 off end
+		device pci 1e.2 alias gspi0 off ops spi_dev_ops end
+		device pci 1e.3 alias gspi1 off ops spi_dev_ops end
 		device pci 1e.4 alias tsn_gbe1 off end
 		device pci 1e.5 alias tsn_gbe2 off end
 		device pci 1f.0 alias soc_espi on end
diff --git a/src/soc/intel/pantherlake/chipset_ptl.cb b/src/soc/intel/pantherlake/chipset_ptl.cb
index 4540ce7a08..99962c56b0 100644
--- a/src/soc/intel/pantherlake/chipset_ptl.cb
+++ b/src/soc/intel/pantherlake/chipset_ptl.cb
@@ -170,7 +170,7 @@ chip soc/intel/pantherlake
 		device pci 10.1 alias thc1 off end
 		device pci 12.0 alias ish off end
 		device pci 12.1 alias p2sb2 hidden end
-		device pci 12.6 alias gspi0a off end
+		device pci 12.6 alias gspi0a off ops spi_dev_ops end
 		device pci 13.0 alias heci_1 off end
 		device pci 13.1 alias heci_2 off end
 		device pci 13.2 alias heci_3 off end
@@ -239,8 +239,8 @@ chip soc/intel/pantherlake
 		device pci 1c.7 alias pcie_rp8 off ops pcie_rp_ops end
 		device pci 1e.0 alias uart0 off ops uart_ops end
 		device pci 1e.1 alias uart1 off ops uart_ops end
-		device pci 1e.2 alias gspi0 off end
-		device pci 1e.3 alias gspi1 off end
+		device pci 1e.2 alias gspi0 off ops spi_dev_ops end
+		device pci 1e.3 alias gspi1 off ops spi_dev_ops end
 		device pci 1f.0 alias soc_espi on end
 		device pci 1f.1 alias p2sb hidden end
 		device pci 1f.2 alias pmc hidden end
diff --git a/src/soc/intel/pantherlake/chipset_wcl.cb b/src/soc/intel/pantherlake/chipset_wcl.cb
index b2ec967c75..cdd57f5a88 100644
--- a/src/soc/intel/pantherlake/chipset_wcl.cb
+++ b/src/soc/intel/pantherlake/chipset_wcl.cb
@@ -56,7 +56,7 @@ chip soc/intel/pantherlake
 		device pci 10.1 alias thc1 off end
 		device pci 12.0 alias ish off end
 		device pci 12.1 alias p2sb2 hidden end
-		device pci 12.6 alias gspi0a off end
+		device pci 12.6 alias gspi0a off ops spi_dev_ops end
 		device pci 13.0 alias heci_1 off end
 		device pci 13.1 alias heci_2 off end
 		device pci 13.2 alias heci_3 off end
@@ -122,8 +122,8 @@ chip soc/intel/pantherlake
 		device pci 1c.3 alias pcie_rp4 off ops pcie_rp_ops end
 		device pci 1e.0 alias uart0 off ops uart_ops end
 		device pci 1e.1 alias uart1 off ops uart_ops end
-		device pci 1e.2 alias gspi0 off end
-		device pci 1e.3 alias gspi1 off end
+		device pci 1e.2 alias gspi0 off ops spi_dev_ops end
+		device pci 1e.3 alias gspi1 off ops spi_dev_ops end
 		device pci 1f.0 alias soc_espi on end
 		device pci 1f.1 alias p2sb hidden end
 		device pci 1f.2 alias pmc hidden end
diff --git a/src/soc/intel/tigerlake/chipset.cb b/src/soc/intel/tigerlake/chipset.cb
index 4258988603..abecd82f61 100644
--- a/src/soc/intel/tigerlake/chipset.cb
+++ b/src/soc/intel/tigerlake/chipset.cb
@@ -61,8 +61,8 @@ chip soc/intel/tigerlake
 		device pci 10.6 alias thc0 off end
 		device pci 10.7 alias thc1 off end
 		device pci 12.0 alias ish off end
-		device pci 12.6 alias gspi2 off end
-		device pci 13.0 alias gspi3 off end
+		device pci 12.6 alias gspi2 off ops spi_dev_ops end
+		device pci 13.0 alias gspi3 off ops spi_dev_ops end
 		device pci 14.0 alias south_xhci off
 			chip drivers/usb/acpi
 				register "type" = "UPC_TYPE_HUB"
@@ -143,8 +143,8 @@ chip soc/intel/tigerlake
 		device pci 1d.3 alias pcie_rp12 off ops pcie_rp_ops end
 		device pci 1e.0 alias uart0 off ops uart_ops end
 		device pci 1e.1 alias uart1 off ops uart_ops end
-		device pci 1e.2 alias gspi0 off end
-		device pci 1e.3 alias gspi1 off end
+		device pci 1e.2 alias gspi0 off ops spi_dev_ops end
+		device pci 1e.3 alias gspi1 off ops spi_dev_ops end
 		device pci 1f.0 alias pch_espi on end
 		device pci 1f.1 alias p2sb off end
 		device pci 1f.2 alias pmc hidden end
diff --git a/src/soc/intel/tigerlake/chipset_pch_h.cb b/src/soc/intel/tigerlake/chipset_pch_h.cb
index c980f62f1c..d0a3df588e 100644
--- a/src/soc/intel/tigerlake/chipset_pch_h.cb
+++ b/src/soc/intel/tigerlake/chipset_pch_h.cb
@@ -65,8 +65,8 @@ chip soc/intel/tigerlake
 		device pci 11.0 alias uart3 off ops uart_ops end
 		device pci 11.3 alias i2c6 off ops i2c_dev_ops end
 		device pci 12.0 alias ish off end
-		device pci 12.6 alias gspi2 off end
-		device pci 13.0 alias gspi3 off end
+		device pci 12.6 alias gspi2 off ops spi_dev_ops end
+		device pci 13.0 alias gspi3 off ops spi_dev_ops end
 		device pci 14.0 alias south_xhci off
 			chip drivers/usb/acpi
 				register "type" = "UPC_TYPE_HUB"
@@ -177,8 +177,8 @@ chip soc/intel/tigerlake
 		device pci 1d.7 alias pcie_rp16 off ops pcie_rp_ops end
 		device pci 1e.0 alias uart0 off ops uart_ops end
 		device pci 1e.1 alias uart1 off ops uart_ops end
-		device pci 1e.2 alias gspi0 off end
-		device pci 1e.3 alias gspi1 off end
+		device pci 1e.2 alias gspi0 off ops spi_dev_ops end
+		device pci 1e.3 alias gspi1 off ops spi_dev_ops end
 		device pci 1f.0 alias pch_espi on end
 		device pci 1f.1 alias p2sb off end
 		device pci 1f.2 alias pmc hidden end

From 038829feb36b351013a119769c05e2ef996911bc Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Sun, 25 Jan 2026 20:11:20 -0600
Subject: [PATCH 3176/3886] soc/intel: Use chipset.cb for SMBUS device ops
 linking

Move SMBUS device operations linking from PCI Device ID matching
to chipset.cb files for all Intel SoCs that have them, matching the
approach used by Skylake.

Remove corresponding DIDs from smbus.c for these SoCs; keep DID
matching only for SoCs without chipset.cb files.

This standardizes the approach across Intel SoCs and makes the
SMBUS controller configuration explicit in devicetree, and prevents
the endless proliferation of DIDs in the common driver code.

Change-Id: I1c742836d923eb8f521bdbd7fa8260c82c1156ac
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90918
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jakub "Kuba" Czapiga <czapiga@google.com>
---
 src/soc/intel/alderlake/chipset.cb        |  2 +-
 src/soc/intel/alderlake/chipset_pch_s.cb  |  2 +-
 src/soc/intel/apollolake/chipset_apl.cb   |  2 +-
 src/soc/intel/apollolake/chipset_glk.cb   |  2 +-
 src/soc/intel/cannonlake/chipset.cb       |  2 +-
 src/soc/intel/cannonlake/chipset_pch_h.cb |  2 +-
 src/soc/intel/common/block/smbus/smbus.c  | 21 ---------------------
 src/soc/intel/jasperlake/chipset.cb       |  2 +-
 src/soc/intel/meteorlake/chipset.cb       |  2 +-
 src/soc/intel/pantherlake/chipset_ptl.cb  |  2 +-
 src/soc/intel/pantherlake/chipset_wcl.cb  |  2 +-
 src/soc/intel/tigerlake/chipset.cb        |  2 +-
 src/soc/intel/tigerlake/chipset_pch_h.cb  |  2 +-
 13 files changed, 12 insertions(+), 33 deletions(-)

diff --git a/src/soc/intel/alderlake/chipset.cb b/src/soc/intel/alderlake/chipset.cb
index 36685783a2..c8b4b4283e 100644
--- a/src/soc/intel/alderlake/chipset.cb
+++ b/src/soc/intel/alderlake/chipset.cb
@@ -268,7 +268,7 @@ chip soc/intel/alderlake
 		device pci 1f.1 alias p2sb hidden end
 		device pci 1f.2 alias pmc hidden end
 		device pci 1f.3 alias hda off end
-		device pci 1f.4 alias smbus off end
+		device pci 1f.4 alias smbus off ops smbus_ops end
 		device pci 1f.5 alias fast_spi on end
 		device pci 1f.6 alias gbe off end
 		device pci 1f.7 alias south_tracehub off end
diff --git a/src/soc/intel/alderlake/chipset_pch_s.cb b/src/soc/intel/alderlake/chipset_pch_s.cb
index a7f2b64399..fc575bc583 100644
--- a/src/soc/intel/alderlake/chipset_pch_s.cb
+++ b/src/soc/intel/alderlake/chipset_pch_s.cb
@@ -413,7 +413,7 @@ chip soc/intel/alderlake
 		device pci 1f.1 alias p2sb hidden end
 		device pci 1f.2 alias pmc hidden end
 		device pci 1f.3 alias hda off end
-		device pci 1f.4 alias smbus off end
+		device pci 1f.4 alias smbus off ops smbus_ops end
 		device pci 1f.5 alias fast_spi on end
 		device pci 1f.6 alias gbe off end
 		device pci 1f.7 alias south_tracehub off end
diff --git a/src/soc/intel/apollolake/chipset_apl.cb b/src/soc/intel/apollolake/chipset_apl.cb
index 2766ef8d16..8ec70cc8a1 100644
--- a/src/soc/intel/apollolake/chipset_apl.cb
+++ b/src/soc/intel/apollolake/chipset_apl.cb
@@ -44,6 +44,6 @@ chip soc/intel/apollolake
 		device pci 1c.0 alias emmc		off	end # eMMC
 		device pci 1e.0 alias sdio		off	end # SDIO
 		device pci 1f.0 alias lpc_espi		on	end # LPC
-		device pci 1f.1 alias smbus		off	end # SMBUS
+		device pci 1f.1 alias smbus		off ops smbus_ops end # SMBUS
 	end
 end
diff --git a/src/soc/intel/apollolake/chipset_glk.cb b/src/soc/intel/apollolake/chipset_glk.cb
index 3255407abb..688197a49b 100644
--- a/src/soc/intel/apollolake/chipset_glk.cb
+++ b/src/soc/intel/apollolake/chipset_glk.cb
@@ -45,6 +45,6 @@ chip soc/intel/apollolake
 		device pci 1d.0 alias ufs		off	end # UFS
 		device pci 1e.0 alias sdio		off	end # SDIO
 		device pci 1f.0 alias lpc_espi		on	end # LPC
-		device pci 1f.1 alias smbus		on	end # SMBUS
+		device pci 1f.1 alias smbus		on ops smbus_ops end # SMBUS
 	end
 end
diff --git a/src/soc/intel/cannonlake/chipset.cb b/src/soc/intel/cannonlake/chipset.cb
index 2fd801051a..12a93eee3b 100644
--- a/src/soc/intel/cannonlake/chipset.cb
+++ b/src/soc/intel/cannonlake/chipset.cb
@@ -121,7 +121,7 @@ chip soc/intel/cannonlake
 		device pci 1f.1 alias p2sb      hidden	end	# P2SB
 		device pci 1f.2 alias pmc       hidden	end	# Power Management Controller
 		device pci 1f.3 alias hda          off	end	# Intel HDA
-		device pci 1f.4 alias smbus        off	end	# SMBus
+		device pci 1f.4 alias smbus        off ops smbus_ops end	# SMBus
 		device pci 1f.5 alias fast_spi     on	end	# PCH SPI
 		device pci 1f.6 alias gbe          off	end	# GbE
 		device pci 1f.7 alias tracehub     off	end	# TraceHub
diff --git a/src/soc/intel/cannonlake/chipset_pch_h.cb b/src/soc/intel/cannonlake/chipset_pch_h.cb
index b00e556a2e..17944a472f 100644
--- a/src/soc/intel/cannonlake/chipset_pch_h.cb
+++ b/src/soc/intel/cannonlake/chipset_pch_h.cb
@@ -155,7 +155,7 @@ chip soc/intel/cannonlake
 		device pci 1f.1 alias p2sb      hidden	end	# P2SB
 		device pci 1f.2 alias pmc       hidden	end	# Power Management Controller
 		device pci 1f.3 alias hda          off	end	# Intel HDA
-		device pci 1f.4 alias smbus        off	end	# SMBus
+		device pci 1f.4 alias smbus        off ops smbus_ops end	# SMBus
 		device pci 1f.5 alias fast_spi     on	end	# PCH SPI
 		device pci 1f.6 alias gbe          off	end	# GbE
 		device pci 1f.7 alias tracehub     off	end	# TraceHub
diff --git a/src/soc/intel/common/block/smbus/smbus.c b/src/soc/intel/common/block/smbus/smbus.c
index ebaf655499..573aea5b8e 100644
--- a/src/soc/intel/common/block/smbus/smbus.c
+++ b/src/soc/intel/common/block/smbus/smbus.c
@@ -49,32 +49,11 @@ struct device_operations smbus_ops = {
 };
 
 static const unsigned short pci_device_ids[] = {
-	PCI_DID_INTEL_WCL_SMBUS,
-	PCI_DID_INTEL_PTL_H_SMBUS,
-	PCI_DID_INTEL_PTL_U_H_SMBUS,
 	PCI_DID_INTEL_LNL_SMBUS,
-	PCI_DID_INTEL_MTL_SMBUS,
-	PCI_DID_INTEL_ARL_SMBUS,
-	PCI_DID_INTEL_ARL_S_SMBUS,
-	PCI_DID_INTEL_ARP_S_SMBUS,
-	PCI_DID_INTEL_RPP_P_SMBUS,
-	PCI_DID_INTEL_RPP_S_SMBUS,
-	PCI_DID_INTEL_APL_SMBUS,
-	PCI_DID_INTEL_GLK_SMBUS,
-	PCI_DID_INTEL_CNL_SMBUS,
-	PCI_DID_INTEL_CNP_H_SMBUS,
 	PCI_DID_INTEL_EBG_SMBUS,
 	PCI_DID_INTEL_LWB_SMBUS_SUPER,
 	PCI_DID_INTEL_LWB_SMBUS,
-	PCI_DID_INTEL_CMP_SMBUS,
-	PCI_DID_INTEL_CMP_H_SMBUS,
-	PCI_DID_INTEL_TGP_LP_SMBUS,
-	PCI_DID_INTEL_TGP_H_SMBUS,
 	PCI_DID_INTEL_MCC_SMBUS,
-	PCI_DID_INTEL_JSP_SMBUS,
-	PCI_DID_INTEL_ADP_P_SMBUS,
-	PCI_DID_INTEL_ADP_S_SMBUS,
-	PCI_DID_INTEL_ADP_M_N_SMBUS,
 	PCI_DID_INTEL_DNV_SMBUS_LEGACY,
 	0
 };
diff --git a/src/soc/intel/jasperlake/chipset.cb b/src/soc/intel/jasperlake/chipset.cb
index 6d50296019..83dda97454 100644
--- a/src/soc/intel/jasperlake/chipset.cb
+++ b/src/soc/intel/jasperlake/chipset.cb
@@ -93,7 +93,7 @@ chip soc/intel/jasperlake
 		device pci 1f.1 alias p2sb		hidden end
 		device pci 1f.2 alias pmc		hidden end
 		device pci 1f.3 alias hda		off end
-		device pci 1f.4 alias smbus		off end
+		device pci 1f.4 alias smbus		off ops smbus_ops end
 		device pci 1f.5 alias fast_spi		on end
 		device pci 1f.7 alias south_tracehub	off end
 	end
diff --git a/src/soc/intel/meteorlake/chipset.cb b/src/soc/intel/meteorlake/chipset.cb
index 1efa776ec0..d1ca7e0781 100644
--- a/src/soc/intel/meteorlake/chipset.cb
+++ b/src/soc/intel/meteorlake/chipset.cb
@@ -187,7 +187,7 @@ chip soc/intel/meteorlake
 		device pci 1f.1 alias p2sb hidden end
 		device pci 1f.2 alias pmc hidden end
 		device pci 1f.3 alias hda off end
-		device pci 1f.4 alias smbus off end
+		device pci 1f.4 alias smbus off ops smbus_ops end
 		device pci 1f.5 alias fast_spi on end
 		device pci 1f.6 alias gbe off end
 		device pci 1f.7 alias npk off end
diff --git a/src/soc/intel/pantherlake/chipset_ptl.cb b/src/soc/intel/pantherlake/chipset_ptl.cb
index 99962c56b0..5de54b59f5 100644
--- a/src/soc/intel/pantherlake/chipset_ptl.cb
+++ b/src/soc/intel/pantherlake/chipset_ptl.cb
@@ -245,7 +245,7 @@ chip soc/intel/pantherlake
 		device pci 1f.1 alias p2sb hidden end
 		device pci 1f.2 alias pmc hidden end
 		device pci 1f.3 alias hda off end
-		device pci 1f.4 alias smbus off end
+		device pci 1f.4 alias smbus off ops smbus_ops end
 		device pci 1f.5 alias fast_spi on end
 		device pci 1f.6 alias gbe off end
 		device pci 1f.7 alias npk off end
diff --git a/src/soc/intel/pantherlake/chipset_wcl.cb b/src/soc/intel/pantherlake/chipset_wcl.cb
index cdd57f5a88..fbe7420005 100644
--- a/src/soc/intel/pantherlake/chipset_wcl.cb
+++ b/src/soc/intel/pantherlake/chipset_wcl.cb
@@ -128,7 +128,7 @@ chip soc/intel/pantherlake
 		device pci 1f.1 alias p2sb hidden end
 		device pci 1f.2 alias pmc hidden end
 		device pci 1f.3 alias hda off end
-		device pci 1f.4 alias smbus off end
+		device pci 1f.4 alias smbus off ops smbus_ops end
 		device pci 1f.5 alias fast_spi on end
 		device pci 1f.6 alias gbe off end
 		device pci 1f.7 alias npk off end
diff --git a/src/soc/intel/tigerlake/chipset.cb b/src/soc/intel/tigerlake/chipset.cb
index abecd82f61..67fe7fbeb5 100644
--- a/src/soc/intel/tigerlake/chipset.cb
+++ b/src/soc/intel/tigerlake/chipset.cb
@@ -149,7 +149,7 @@ chip soc/intel/tigerlake
 		device pci 1f.1 alias p2sb off end
 		device pci 1f.2 alias pmc hidden end
 		device pci 1f.3 alias hda off end
-		device pci 1f.4 alias smbus off end
+		device pci 1f.4 alias smbus off ops smbus_ops end
 		device pci 1f.5 alias fast_spi on end
 		device pci 1f.6 alias gbe off end
 		device pci 1f.7 alias tracehub off end
diff --git a/src/soc/intel/tigerlake/chipset_pch_h.cb b/src/soc/intel/tigerlake/chipset_pch_h.cb
index d0a3df588e..9271488015 100644
--- a/src/soc/intel/tigerlake/chipset_pch_h.cb
+++ b/src/soc/intel/tigerlake/chipset_pch_h.cb
@@ -183,7 +183,7 @@ chip soc/intel/tigerlake
 		device pci 1f.1 alias p2sb off end
 		device pci 1f.2 alias pmc hidden end
 		device pci 1f.3 alias hda off end
-		device pci 1f.4 alias smbus off end
+		device pci 1f.4 alias smbus off ops smbus_ops end
 		device pci 1f.5 alias fast_spi on end
 		device pci 1f.6 alias gbe off end
 		device pci 1f.7 alias thermal off end

From f2d9c137e6c65d8e0a4eb52f9b535355e47430d5 Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Sun, 25 Jan 2026 20:49:26 -0600
Subject: [PATCH 3177/3886] soc/intel: Use chipset.cb for HDA device ops
 linking

Move HDA device operations linking from PCI Device ID matching
to chipset.cb files for all Intel SoCs that have them, matching the
approach used by Skylake.

Remove corresponding DIDs from hda.c for these SoCs; keep DID
matching only for SoCs without chipset.cb files.

Add 'Select SOC_INTEL_COMMON_BLOCK_HDA` to Apollolake/Geminilake
so those platforms can make use of the common driver. Since no
APL/GLK boards currently select `SOC_INTEL_COMMON_BLOCK_HDA_VERB`
the addition is a no-op.

This standardizes the approach across Intel SoCs and makes the
HDA controller configuration explicit in devicetree, and prevents
the endless proliferation of DIDs in the common HDA driver code.

Change-Id: I0b3af4c2a441d4897341ee6c2cc5d75d70a6ebc4
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90919
Reviewed-by: Jakub "Kuba" Czapiga <czapiga@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/soc/intel/alderlake/chipset.cb        |  2 +-
 src/soc/intel/alderlake/chipset_pch_s.cb  |  2 +-
 src/soc/intel/apollolake/Kconfig          |  1 +
 src/soc/intel/apollolake/chipset_apl.cb   |  2 +-
 src/soc/intel/apollolake/chipset_glk.cb   |  2 +-
 src/soc/intel/cannonlake/chipset.cb       |  2 +-
 src/soc/intel/cannonlake/chipset_pch_h.cb |  2 +-
 src/soc/intel/common/block/hda/hda.c      | 68 -----------------------
 src/soc/intel/jasperlake/chipset.cb       |  2 +-
 src/soc/intel/meteorlake/chipset.cb       |  2 +-
 src/soc/intel/pantherlake/chipset_ptl.cb  |  2 +-
 src/soc/intel/pantherlake/chipset_wcl.cb  |  2 +-
 src/soc/intel/tigerlake/chipset.cb        |  2 +-
 src/soc/intel/tigerlake/chipset_pch_h.cb  |  2 +-
 14 files changed, 13 insertions(+), 80 deletions(-)

diff --git a/src/soc/intel/alderlake/chipset.cb b/src/soc/intel/alderlake/chipset.cb
index c8b4b4283e..b942157c4d 100644
--- a/src/soc/intel/alderlake/chipset.cb
+++ b/src/soc/intel/alderlake/chipset.cb
@@ -267,7 +267,7 @@ chip soc/intel/alderlake
 		device pci 1f.0 alias pch_espi on end
 		device pci 1f.1 alias p2sb hidden end
 		device pci 1f.2 alias pmc hidden end
-		device pci 1f.3 alias hda off end
+		device pci 1f.3 alias hda off ops hda_ops end
 		device pci 1f.4 alias smbus off ops smbus_ops end
 		device pci 1f.5 alias fast_spi on end
 		device pci 1f.6 alias gbe off end
diff --git a/src/soc/intel/alderlake/chipset_pch_s.cb b/src/soc/intel/alderlake/chipset_pch_s.cb
index fc575bc583..36ca14755d 100644
--- a/src/soc/intel/alderlake/chipset_pch_s.cb
+++ b/src/soc/intel/alderlake/chipset_pch_s.cb
@@ -412,7 +412,7 @@ chip soc/intel/alderlake
 		device pci 1f.0 alias pch_espi on end
 		device pci 1f.1 alias p2sb hidden end
 		device pci 1f.2 alias pmc hidden end
-		device pci 1f.3 alias hda off end
+		device pci 1f.3 alias hda off ops hda_ops end
 		device pci 1f.4 alias smbus off ops smbus_ops end
 		device pci 1f.5 alias fast_spi on end
 		device pci 1f.6 alias gbe off end
diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig
index be87a8c10d..18e8466cff 100644
--- a/src/soc/intel/apollolake/Kconfig
+++ b/src/soc/intel/apollolake/Kconfig
@@ -61,6 +61,7 @@ config SOC_INTEL_APOLLOLAKE
 	select SOC_INTEL_COMMON_BLOCK_GPIO_DUAL_ROUTE_SUPPORT
 	select SOC_INTEL_COMMON_BLOCK_GPIO_MULTI_ACPI_DEVICES
 	select SOC_INTEL_COMMON_BLOCK_GPIO_IOSTANDBY
+	select SOC_INTEL_COMMON_BLOCK_HDA
 	select SOC_INTEL_COMMON_BLOCK_HECI1_DISABLE_USING_PCR
 	select SOC_INTEL_COMMON_PCH_CLIENT
 	select SOC_INTEL_COMMON_BLOCK_PMC_DISCOVERABLE
diff --git a/src/soc/intel/apollolake/chipset_apl.cb b/src/soc/intel/apollolake/chipset_apl.cb
index 8ec70cc8a1..5784265855 100644
--- a/src/soc/intel/apollolake/chipset_apl.cb
+++ b/src/soc/intel/apollolake/chipset_apl.cb
@@ -10,7 +10,7 @@ chip soc/intel/apollolake
 		device pci 0d.1 alias pmc		off	end # PMC
 		device pci 0d.2 alias fast_spi		off	end # SPI
 		device pci 0d.3 alias sram		off	end # Shared SRAM
-		device pci 0e.0 alias hda		off	end # HDA
+		device pci 0e.0 alias hda		off ops hda_ops end # HDA
 		device pci 0f.0 alias heci1		off	end # HECI1
 		device pci 0f.1 alias heci2		off	end # HECI2
 		device pci 0f.2 alias heci3		off	end # HECI3
diff --git a/src/soc/intel/apollolake/chipset_glk.cb b/src/soc/intel/apollolake/chipset_glk.cb
index 688197a49b..2a4defe7c7 100644
--- a/src/soc/intel/apollolake/chipset_glk.cb
+++ b/src/soc/intel/apollolake/chipset_glk.cb
@@ -11,7 +11,7 @@ chip soc/intel/apollolake
 		device pci 0d.1 alias pmc		off	end # PMC
 		device pci 0d.2 alias fast_spi		off	end # SPI
 		device pci 0d.3 alias sram		off	end # Shared SRAM
-		device pci 0e.0 alias hda		off	end # HDA
+		device pci 0e.0 alias hda		off ops hda_ops end # HDA
 		device pci 0f.0 alias heci1		off	end # HECI1
 		device pci 0f.1 alias heci2		off	end # HECI2
 		device pci 0f.2 alias heci3		off	end # HECI3
diff --git a/src/soc/intel/cannonlake/chipset.cb b/src/soc/intel/cannonlake/chipset.cb
index 12a93eee3b..e0f20ae8a8 100644
--- a/src/soc/intel/cannonlake/chipset.cb
+++ b/src/soc/intel/cannonlake/chipset.cb
@@ -120,7 +120,7 @@ chip soc/intel/cannonlake
 		device pci 1f.0 alias lpc_espi     on	end	# LPC Interface
 		device pci 1f.1 alias p2sb      hidden	end	# P2SB
 		device pci 1f.2 alias pmc       hidden	end	# Power Management Controller
-		device pci 1f.3 alias hda          off	end	# Intel HDA
+		device pci 1f.3 alias hda          off ops hda_ops end	# Intel HDA
 		device pci 1f.4 alias smbus        off ops smbus_ops end	# SMBus
 		device pci 1f.5 alias fast_spi     on	end	# PCH SPI
 		device pci 1f.6 alias gbe          off	end	# GbE
diff --git a/src/soc/intel/cannonlake/chipset_pch_h.cb b/src/soc/intel/cannonlake/chipset_pch_h.cb
index 17944a472f..240054d3bf 100644
--- a/src/soc/intel/cannonlake/chipset_pch_h.cb
+++ b/src/soc/intel/cannonlake/chipset_pch_h.cb
@@ -154,7 +154,7 @@ chip soc/intel/cannonlake
 		device pci 1f.0 alias lpc_espi     on	end	# LPC Interface
 		device pci 1f.1 alias p2sb      hidden	end	# P2SB
 		device pci 1f.2 alias pmc       hidden	end	# Power Management Controller
-		device pci 1f.3 alias hda          off	end	# Intel HDA
+		device pci 1f.3 alias hda          off ops hda_ops end	# Intel HDA
 		device pci 1f.4 alias smbus        off ops smbus_ops end	# SMBus
 		device pci 1f.5 alias fast_spi     on	end	# PCH SPI
 		device pci 1f.6 alias gbe          off	end	# GbE
diff --git a/src/soc/intel/common/block/hda/hda.c b/src/soc/intel/common/block/hda/hda.c
index e779dee312..66ad97dd12 100644
--- a/src/soc/intel/common/block/hda/hda.c
+++ b/src/soc/intel/common/block/hda/hda.c
@@ -38,30 +38,6 @@ static const unsigned short pci_device_ids[] = {
 	PCI_DID_INTEL_NVL_AUDIO_6,
 	PCI_DID_INTEL_NVL_AUDIO_7,
 	PCI_DID_INTEL_NVL_AUDIO_8,
-	PCI_DID_INTEL_WCL_AUDIO_1,
-	PCI_DID_INTEL_WCL_AUDIO_2,
-	PCI_DID_INTEL_WCL_AUDIO_3,
-	PCI_DID_INTEL_WCL_AUDIO_4,
-	PCI_DID_INTEL_WCL_AUDIO_5,
-	PCI_DID_INTEL_WCL_AUDIO_6,
-	PCI_DID_INTEL_WCL_AUDIO_7,
-	PCI_DID_INTEL_WCL_AUDIO_8,
-	PCI_DID_INTEL_PTL_H_AUDIO_1,
-	PCI_DID_INTEL_PTL_H_AUDIO_2,
-	PCI_DID_INTEL_PTL_H_AUDIO_3,
-	PCI_DID_INTEL_PTL_H_AUDIO_4,
-	PCI_DID_INTEL_PTL_H_AUDIO_5,
-	PCI_DID_INTEL_PTL_H_AUDIO_6,
-	PCI_DID_INTEL_PTL_H_AUDIO_7,
-	PCI_DID_INTEL_PTL_H_AUDIO_8,
-	PCI_DID_INTEL_PTL_U_H_AUDIO_1,
-	PCI_DID_INTEL_PTL_U_H_AUDIO_2,
-	PCI_DID_INTEL_PTL_U_H_AUDIO_3,
-	PCI_DID_INTEL_PTL_U_H_AUDIO_4,
-	PCI_DID_INTEL_PTL_U_H_AUDIO_5,
-	PCI_DID_INTEL_PTL_U_H_AUDIO_6,
-	PCI_DID_INTEL_PTL_U_H_AUDIO_7,
-	PCI_DID_INTEL_PTL_U_H_AUDIO_8,
 	PCI_DID_INTEL_LNL_AUDIO_1,
 	PCI_DID_INTEL_LNL_AUDIO_2,
 	PCI_DID_INTEL_LNL_AUDIO_3,
@@ -70,54 +46,10 @@ static const unsigned short pci_device_ids[] = {
 	PCI_DID_INTEL_LNL_AUDIO_6,
 	PCI_DID_INTEL_LNL_AUDIO_7,
 	PCI_DID_INTEL_LNL_AUDIO_8,
-	PCI_DID_INTEL_MTL_AUDIO_1,
-	PCI_DID_INTEL_MTL_AUDIO_2,
-	PCI_DID_INTEL_MTL_AUDIO_3,
-	PCI_DID_INTEL_MTL_AUDIO_4,
-	PCI_DID_INTEL_MTL_AUDIO_5,
-	PCI_DID_INTEL_MTL_AUDIO_6,
-	PCI_DID_INTEL_MTL_AUDIO_7,
-	PCI_DID_INTEL_MTL_AUDIO_8,
-	PCI_DID_INTEL_ARL_AUDIO,
-	PCI_DID_INTEL_ARP_S_AUDIO,
-	PCI_DID_INTEL_RPP_P_AUDIO,
-	PCI_DID_INTEL_RPP_S_AUDIO_1,
-	PCI_DID_INTEL_RPP_S_AUDIO_2,
-	PCI_DID_INTEL_RPP_S_AUDIO_3,
-	PCI_DID_INTEL_RPP_S_AUDIO_4,
-	PCI_DID_INTEL_RPP_S_AUDIO_5,
-	PCI_DID_INTEL_RPP_S_AUDIO_6,
-	PCI_DID_INTEL_RPP_S_AUDIO_7,
-	PCI_DID_INTEL_RPP_S_AUDIO_8,
-	PCI_DID_INTEL_APL_AUDIO,
-	PCI_DID_INTEL_GLK_AUDIO,
 	PCI_DID_INTEL_LWB_AUDIO,
 	PCI_DID_INTEL_LWB_AUDIO_SUPER,
-	PCI_DID_INTEL_CNL_AUDIO,
-	PCI_DID_INTEL_CNP_H_AUDIO,
-	PCI_DID_INTEL_CMP_AUDIO,
-	PCI_DID_INTEL_CMP_H_AUDIO,
 	PCI_DID_INTEL_BSW_AUDIO,
-	PCI_DID_INTEL_TGL_AUDIO,
-	PCI_DID_INTEL_TGL_H_AUDIO,
 	PCI_DID_INTEL_MCC_AUDIO,
-	PCI_DID_INTEL_JSP_AUDIO,
-	PCI_DID_INTEL_ADP_P_AUDIO,
-	PCI_DID_INTEL_ADP_S_AUDIO_1,
-	PCI_DID_INTEL_ADP_S_AUDIO_2,
-	PCI_DID_INTEL_ADP_S_AUDIO_3,
-	PCI_DID_INTEL_ADP_S_AUDIO_4,
-	PCI_DID_INTEL_ADP_S_AUDIO_5,
-	PCI_DID_INTEL_ADP_S_AUDIO_6,
-	PCI_DID_INTEL_ADP_S_AUDIO_7,
-	PCI_DID_INTEL_ADP_S_AUDIO_8,
-	PCI_DID_INTEL_ADP_M_N_AUDIO_1,
-	PCI_DID_INTEL_ADP_M_N_AUDIO_2,
-	PCI_DID_INTEL_ADP_M_N_AUDIO_3,
-	PCI_DID_INTEL_ADP_M_N_AUDIO_4,
-	PCI_DID_INTEL_ADP_M_N_AUDIO_5,
-	PCI_DID_INTEL_ADP_M_N_AUDIO_6,
-	PCI_DID_INTEL_ADP_M_N_AUDIO_7,
 	0
 };
 
diff --git a/src/soc/intel/jasperlake/chipset.cb b/src/soc/intel/jasperlake/chipset.cb
index 83dda97454..ca18683d8b 100644
--- a/src/soc/intel/jasperlake/chipset.cb
+++ b/src/soc/intel/jasperlake/chipset.cb
@@ -92,7 +92,7 @@ chip soc/intel/jasperlake
 		device pci 1f.0 alias pch_espi		on  end
 		device pci 1f.1 alias p2sb		hidden end
 		device pci 1f.2 alias pmc		hidden end
-		device pci 1f.3 alias hda		off end
+		device pci 1f.3 alias hda		off ops hda_ops end
 		device pci 1f.4 alias smbus		off ops smbus_ops end
 		device pci 1f.5 alias fast_spi		on end
 		device pci 1f.7 alias south_tracehub	off end
diff --git a/src/soc/intel/meteorlake/chipset.cb b/src/soc/intel/meteorlake/chipset.cb
index d1ca7e0781..a1b995c5c9 100644
--- a/src/soc/intel/meteorlake/chipset.cb
+++ b/src/soc/intel/meteorlake/chipset.cb
@@ -186,7 +186,7 @@ chip soc/intel/meteorlake
 		device pci 1f.0 alias soc_espi on end
 		device pci 1f.1 alias p2sb hidden end
 		device pci 1f.2 alias pmc hidden end
-		device pci 1f.3 alias hda off end
+		device pci 1f.3 alias hda off ops hda_ops end
 		device pci 1f.4 alias smbus off ops smbus_ops end
 		device pci 1f.5 alias fast_spi on end
 		device pci 1f.6 alias gbe off end
diff --git a/src/soc/intel/pantherlake/chipset_ptl.cb b/src/soc/intel/pantherlake/chipset_ptl.cb
index 5de54b59f5..e2277d319c 100644
--- a/src/soc/intel/pantherlake/chipset_ptl.cb
+++ b/src/soc/intel/pantherlake/chipset_ptl.cb
@@ -244,7 +244,7 @@ chip soc/intel/pantherlake
 		device pci 1f.0 alias soc_espi on end
 		device pci 1f.1 alias p2sb hidden end
 		device pci 1f.2 alias pmc hidden end
-		device pci 1f.3 alias hda off end
+		device pci 1f.3 alias hda off ops hda_ops end
 		device pci 1f.4 alias smbus off ops smbus_ops end
 		device pci 1f.5 alias fast_spi on end
 		device pci 1f.6 alias gbe off end
diff --git a/src/soc/intel/pantherlake/chipset_wcl.cb b/src/soc/intel/pantherlake/chipset_wcl.cb
index fbe7420005..0cb6e6634e 100644
--- a/src/soc/intel/pantherlake/chipset_wcl.cb
+++ b/src/soc/intel/pantherlake/chipset_wcl.cb
@@ -127,7 +127,7 @@ chip soc/intel/pantherlake
 		device pci 1f.0 alias soc_espi on end
 		device pci 1f.1 alias p2sb hidden end
 		device pci 1f.2 alias pmc hidden end
-		device pci 1f.3 alias hda off end
+		device pci 1f.3 alias hda off ops hda_ops end
 		device pci 1f.4 alias smbus off ops smbus_ops end
 		device pci 1f.5 alias fast_spi on end
 		device pci 1f.6 alias gbe off end
diff --git a/src/soc/intel/tigerlake/chipset.cb b/src/soc/intel/tigerlake/chipset.cb
index 67fe7fbeb5..40932489da 100644
--- a/src/soc/intel/tigerlake/chipset.cb
+++ b/src/soc/intel/tigerlake/chipset.cb
@@ -148,7 +148,7 @@ chip soc/intel/tigerlake
 		device pci 1f.0 alias pch_espi on end
 		device pci 1f.1 alias p2sb off end
 		device pci 1f.2 alias pmc hidden end
-		device pci 1f.3 alias hda off end
+		device pci 1f.3 alias hda off ops hda_ops end
 		device pci 1f.4 alias smbus off ops smbus_ops end
 		device pci 1f.5 alias fast_spi on end
 		device pci 1f.6 alias gbe off end
diff --git a/src/soc/intel/tigerlake/chipset_pch_h.cb b/src/soc/intel/tigerlake/chipset_pch_h.cb
index 9271488015..3761527edb 100644
--- a/src/soc/intel/tigerlake/chipset_pch_h.cb
+++ b/src/soc/intel/tigerlake/chipset_pch_h.cb
@@ -182,7 +182,7 @@ chip soc/intel/tigerlake
 		device pci 1f.0 alias pch_espi on end
 		device pci 1f.1 alias p2sb off end
 		device pci 1f.2 alias pmc hidden end
-		device pci 1f.3 alias hda off end
+		device pci 1f.3 alias hda off ops hda_ops end
 		device pci 1f.4 alias smbus off ops smbus_ops end
 		device pci 1f.5 alias fast_spi on end
 		device pci 1f.6 alias gbe off end

From b6e80702a1c32c370b2f946669fbba8abca34b9f Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Sun, 25 Jan 2026 20:55:07 -0600
Subject: [PATCH 3178/3886] soc/intel: Use chipset.cb for XHCI device ops
 linking

Move XHCI device operations linking from PCI Device ID matching
to chipset.cb files for all Intel SoCs that have them, matching the
approach used by Skylake.

Remove corresponding DIDs from xhci.c for these SoCs; keep DID
matching only for SoCs without chipset.cb files.

This standardizes the approach across Intel SoCs and makes the
XHCI controller configuration explicit in devicetree, and prevents
the endless proliferation of DIDs in the common driver code.

Change-Id: I4a0551a0fc5a233153c62d5bb7b0b2f3596a81ac
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90920
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jakub "Kuba" Czapiga <czapiga@google.com>
---
 src/soc/intel/alderlake/chipset.cb        |  2 +-
 src/soc/intel/alderlake/chipset_pch_s.cb  |  2 +-
 src/soc/intel/apollolake/chipset_apl.cb   |  2 +-
 src/soc/intel/apollolake/chipset_glk.cb   |  2 +-
 src/soc/intel/cannonlake/chipset.cb       |  2 +-
 src/soc/intel/cannonlake/chipset_pch_h.cb |  2 +-
 src/soc/intel/common/block/xhci/xhci.c    | 19 -------------------
 src/soc/intel/jasperlake/chipset.cb       |  2 +-
 src/soc/intel/meteorlake/chipset.cb       |  2 +-
 src/soc/intel/pantherlake/chipset_ptl.cb  |  2 +-
 src/soc/intel/pantherlake/chipset_wcl.cb  |  2 +-
 src/soc/intel/tigerlake/chipset.cb        |  2 +-
 src/soc/intel/tigerlake/chipset_pch_h.cb  |  2 +-
 13 files changed, 12 insertions(+), 31 deletions(-)

diff --git a/src/soc/intel/alderlake/chipset.cb b/src/soc/intel/alderlake/chipset.cb
index b942157c4d..3d2ced5f00 100644
--- a/src/soc/intel/alderlake/chipset.cb
+++ b/src/soc/intel/alderlake/chipset.cb
@@ -180,7 +180,7 @@ chip soc/intel/alderlake
 		device pci 12.6 alias gspi2 off ops spi_dev_ops end
 		device pci 12.7 alias ufs off end
 		device pci 13.0 alias gspi3 off ops spi_dev_ops end
-		device pci 14.0 alias xhci off
+		device pci 14.0 alias xhci off ops usb_xhci_ops
 			chip drivers/usb/acpi
 				register "type" = "UPC_TYPE_HUB"
 				device usb 0.0 alias xhci_root_hub off
diff --git a/src/soc/intel/alderlake/chipset_pch_s.cb b/src/soc/intel/alderlake/chipset_pch_s.cb
index 36ca14755d..6e4247817a 100644
--- a/src/soc/intel/alderlake/chipset_pch_s.cb
+++ b/src/soc/intel/alderlake/chipset_pch_s.cb
@@ -281,7 +281,7 @@ chip soc/intel/alderlake
 		device pci 12.0 alias ish off end
 		device pci 12.6 alias gspi2 off ops spi_dev_ops end
 		device pci 13.0 alias gspi3 off ops spi_dev_ops end
-		device pci 14.0 alias xhci off
+		device pci 14.0 alias xhci off ops usb_xhci_ops
 			chip drivers/usb/acpi
 				register "type" = "UPC_TYPE_HUB"
 				device usb 0.0 alias xhci_root_hub off
diff --git a/src/soc/intel/apollolake/chipset_apl.cb b/src/soc/intel/apollolake/chipset_apl.cb
index 5784265855..5abba624bf 100644
--- a/src/soc/intel/apollolake/chipset_apl.cb
+++ b/src/soc/intel/apollolake/chipset_apl.cb
@@ -22,7 +22,7 @@ chip soc/intel/apollolake
 		device pci 13.3 alias pcie_rp04		off ops pcie_rp_ops	end # PCIE Express Root Port 4
 		device pci 14.0 alias pcie_rp05		off ops pcie_rp_ops	end # PCIE Express Root Port 5
 		device pci 14.1 alias pcie_rp06		off ops pcie_rp_ops	end # PCIE Express Root Port 6
-		device pci 15.0 alias xhci		off	end # XHCI
+		device pci 15.0 alias xhci		off ops usb_xhci_ops end # XHCI
 		device pci 15.1 alias xdci		off	end # XDCI
 		device pci 16.0 alias i2c0		off ops i2c_dev_ops end # I2C0
 		device pci 16.1 alias i2c1		off ops i2c_dev_ops end # I2C1
diff --git a/src/soc/intel/apollolake/chipset_glk.cb b/src/soc/intel/apollolake/chipset_glk.cb
index 2a4defe7c7..9a8732dd94 100644
--- a/src/soc/intel/apollolake/chipset_glk.cb
+++ b/src/soc/intel/apollolake/chipset_glk.cb
@@ -23,7 +23,7 @@ chip soc/intel/apollolake
 		device pci 13.3 alias pcie_rp04		off ops pcie_rp_ops	end # PCIE Express Root Port 4
 		device pci 14.0 alias pcie_rp05		off ops pcie_rp_ops	end # PCIE Express Root Port 5
 		device pci 14.1 alias pcie_rp06		off ops pcie_rp_ops	end # PCIE Express Root Port 6
-		device pci 15.0 alias xhci		off	end # XHCI
+		device pci 15.0 alias xhci		off ops usb_xhci_ops end # XHCI
 		device pci 15.1 alias xdci		off	end # XDCI
 		device pci 16.0 alias i2c0		off ops i2c_dev_ops end # I2C0
 		device pci 16.1 alias i2c1		off ops i2c_dev_ops end # I2C1
diff --git a/src/soc/intel/cannonlake/chipset.cb b/src/soc/intel/cannonlake/chipset.cb
index e0f20ae8a8..5b94869d87 100644
--- a/src/soc/intel/cannonlake/chipset.cb
+++ b/src/soc/intel/cannonlake/chipset.cb
@@ -17,7 +17,7 @@ chip soc/intel/cannonlake
 		device pci 12.5 alias ufs          off	end	# UFS SCS
 		device pci 12.6 alias gspi2        off ops spi_dev_ops end	# GSPI #2
 		device pci 13.0 alias ish          off	end	# ISH
-		device pci 14.0 alias xhci         off		# USB xHCI
+		device pci 14.0 alias xhci         off ops usb_xhci_ops		# USB xHCI
 			chip drivers/usb/acpi
 				register "type" = "UPC_TYPE_HUB"
 				device usb 0.0 alias xhci_root_hub off
diff --git a/src/soc/intel/cannonlake/chipset_pch_h.cb b/src/soc/intel/cannonlake/chipset_pch_h.cb
index 240054d3bf..9d96061bf1 100644
--- a/src/soc/intel/cannonlake/chipset_pch_h.cb
+++ b/src/soc/intel/cannonlake/chipset_pch_h.cb
@@ -17,7 +17,7 @@ chip soc/intel/cannonlake
 		device pci 12.5 alias ufs          off	end	# UFS SCS
 		device pci 12.6 alias gspi2        off ops spi_dev_ops end	# GSPI #2
 		device pci 13.0 alias ish          off	end	# ISH
-		device pci 14.0 alias xhci         off		# USB xHCI
+		device pci 14.0 alias xhci         off ops usb_xhci_ops		# USB xHCI
 			chip drivers/usb/acpi
 				register "type" = "UPC_TYPE_HUB"
 				device usb 0.0 alias xhci_root_hub off
diff --git a/src/soc/intel/common/block/xhci/xhci.c b/src/soc/intel/common/block/xhci/xhci.c
index 5eb73ed562..a7b56e8d5c 100644
--- a/src/soc/intel/common/block/xhci/xhci.c
+++ b/src/soc/intel/common/block/xhci/xhci.c
@@ -132,29 +132,10 @@ struct device_operations usb_xhci_ops = {
 
 static const unsigned short pci_device_ids[] = {
 	PCI_DID_INTEL_NVL_XHCI,
-	PCI_DID_INTEL_WCL_XHCI,
-	PCI_DID_INTEL_PTL_H_XHCI,
-	PCI_DID_INTEL_PTL_U_H_XHCI,
 	PCI_DID_INTEL_LNL_XHCI,
-	PCI_DID_INTEL_MTL_XHCI,
-	PCI_DID_INTEL_ARL_XHCI,
-	PCI_DID_INTEL_ARP_S_XHCI,
-	PCI_DID_INTEL_APL_XHCI,
-	PCI_DID_INTEL_CNL_LP_XHCI,
-	PCI_DID_INTEL_GLK_XHCI,
 	PCI_DID_INTEL_LWB_XHCI,
 	PCI_DID_INTEL_LWB_XHCI_SUPER,
-	PCI_DID_INTEL_CNP_H_XHCI,
-	PCI_DID_INTEL_CMP_LP_XHCI,
-	PCI_DID_INTEL_CMP_H_XHCI,
-	PCI_DID_INTEL_TGP_LP_XHCI,
-	PCI_DID_INTEL_TGP_H_XHCI,
 	PCI_DID_INTEL_MCC_XHCI,
-	PCI_DID_INTEL_JSP_XHCI,
-	PCI_DID_INTEL_ADP_P_XHCI,
-	PCI_DID_INTEL_ADP_S_XHCI,
-	PCI_DID_INTEL_ADP_M_XHCI,
-	PCI_DID_INTEL_RPP_S_XHCI,
 	PCI_DID_INTEL_SNR_XHCI,
 	0
 };
diff --git a/src/soc/intel/jasperlake/chipset.cb b/src/soc/intel/jasperlake/chipset.cb
index ca18683d8b..c6cc992ae6 100644
--- a/src/soc/intel/jasperlake/chipset.cb
+++ b/src/soc/intel/jasperlake/chipset.cb
@@ -12,7 +12,7 @@ chip soc/intel/jasperlake
 		device pci 12.0 alias ish		off end
 		device pci 12.5 alias ufs_scs		off end
 		device pci 12.6 alias gspi2		off ops spi_dev_ops end
-		device pci 14.0 alias south_xhci	off
+		device pci 14.0 alias south_xhci	off ops usb_xhci_ops
 			chip drivers/usb/acpi
 				register "type" = "UPC_TYPE_HUB"
 				device usb 0.0 alias xhci_root_hub off
diff --git a/src/soc/intel/meteorlake/chipset.cb b/src/soc/intel/meteorlake/chipset.cb
index a1b995c5c9..df62835b56 100644
--- a/src/soc/intel/meteorlake/chipset.cb
+++ b/src/soc/intel/meteorlake/chipset.cb
@@ -100,7 +100,7 @@ chip soc/intel/meteorlake
 		device pci 13.1 alias ieh2 off end
 		device pci 13.2 alias pmc2 hidden end
 		device pci 13.3 alias ioe_shared_sram off end
-		device pci 14.0 alias xhci off
+		device pci 14.0 alias xhci off ops usb_xhci_ops
 			chip drivers/usb/acpi
 				register "type" = "UPC_TYPE_HUB"
 				device usb 0.0 alias xhci_root_hub off
diff --git a/src/soc/intel/pantherlake/chipset_ptl.cb b/src/soc/intel/pantherlake/chipset_ptl.cb
index e2277d319c..82dc449d80 100644
--- a/src/soc/intel/pantherlake/chipset_ptl.cb
+++ b/src/soc/intel/pantherlake/chipset_ptl.cb
@@ -174,7 +174,7 @@ chip soc/intel/pantherlake
 		device pci 13.0 alias heci_1 off end
 		device pci 13.1 alias heci_2 off end
 		device pci 13.2 alias heci_3 off end
-		device pci 14.0 alias xhci on
+		device pci 14.0 alias xhci on ops usb_xhci_ops
 			chip drivers/usb/acpi
 				register "type" = "UPC_TYPE_HUB"
 				device usb 0.0 alias xhci_root_hub off
diff --git a/src/soc/intel/pantherlake/chipset_wcl.cb b/src/soc/intel/pantherlake/chipset_wcl.cb
index 0cb6e6634e..ccc5948d1f 100644
--- a/src/soc/intel/pantherlake/chipset_wcl.cb
+++ b/src/soc/intel/pantherlake/chipset_wcl.cb
@@ -60,7 +60,7 @@ chip soc/intel/pantherlake
 		device pci 13.0 alias heci_1 off end
 		device pci 13.1 alias heci_2 off end
 		device pci 13.2 alias heci_3 off end
-		device pci 14.0 alias xhci on
+		device pci 14.0 alias xhci on ops usb_xhci_ops
 			chip drivers/usb/acpi
 				register "type" = "UPC_TYPE_HUB"
 				device usb 0.0 alias xhci_root_hub off
diff --git a/src/soc/intel/tigerlake/chipset.cb b/src/soc/intel/tigerlake/chipset.cb
index 40932489da..9594917ef8 100644
--- a/src/soc/intel/tigerlake/chipset.cb
+++ b/src/soc/intel/tigerlake/chipset.cb
@@ -63,7 +63,7 @@ chip soc/intel/tigerlake
 		device pci 12.0 alias ish off end
 		device pci 12.6 alias gspi2 off ops spi_dev_ops end
 		device pci 13.0 alias gspi3 off ops spi_dev_ops end
-		device pci 14.0 alias south_xhci off
+		device pci 14.0 alias south_xhci off ops usb_xhci_ops
 			chip drivers/usb/acpi
 				register "type" = "UPC_TYPE_HUB"
 				device usb 0.0 alias xhci_root_hub off
diff --git a/src/soc/intel/tigerlake/chipset_pch_h.cb b/src/soc/intel/tigerlake/chipset_pch_h.cb
index 3761527edb..8b0355a443 100644
--- a/src/soc/intel/tigerlake/chipset_pch_h.cb
+++ b/src/soc/intel/tigerlake/chipset_pch_h.cb
@@ -67,7 +67,7 @@ chip soc/intel/tigerlake
 		device pci 12.0 alias ish off end
 		device pci 12.6 alias gspi2 off ops spi_dev_ops end
 		device pci 13.0 alias gspi3 off ops spi_dev_ops end
-		device pci 14.0 alias south_xhci off
+		device pci 14.0 alias south_xhci off ops usb_xhci_ops
 			chip drivers/usb/acpi
 				register "type" = "UPC_TYPE_HUB"
 				device usb 0.0 alias xhci_root_hub off

From 32563645a9323ca3116443693a23fa25beb6474f Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Sun, 25 Jan 2026 20:58:42 -0600
Subject: [PATCH 3179/3886] soc/intel: Use chipset.cb for XDCI device ops
 linking

Move XDCI device operations linking from PCI Device ID matching
to chipset.cb files for all Intel SoCs that have them, matching the
approach used by Skylake.

Remove corresponding DIDs from xdci.c for these SoCs; keep DID
matching only for SoCs without chipset.cb files.

This standardizes the approach across Intel SoCs and makes the
XDCI controller configuration explicit in devicetree, and prevents
the endless proliferation of DIDs in the common driver code.

Change-Id: Ie8f8b5a952d072ecd1721bc8537734e85769b09d
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90921
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jakub "Kuba" Czapiga <czapiga@google.com>
---
 src/soc/intel/alderlake/chipset.cb        |  2 +-
 src/soc/intel/alderlake/chipset_pch_s.cb  |  2 +-
 src/soc/intel/apollolake/chipset_apl.cb   |  2 +-
 src/soc/intel/apollolake/chipset_glk.cb   |  2 +-
 src/soc/intel/cannonlake/chipset.cb       |  2 +-
 src/soc/intel/cannonlake/chipset_pch_h.cb |  2 +-
 src/soc/intel/common/block/xdci/xdci.c    | 19 -------------------
 src/soc/intel/jasperlake/chipset.cb       |  2 +-
 src/soc/intel/meteorlake/chipset.cb       |  2 +-
 src/soc/intel/pantherlake/chipset_ptl.cb  |  2 +-
 src/soc/intel/tigerlake/chipset.cb        |  2 +-
 src/soc/intel/tigerlake/chipset_pch_h.cb  |  2 +-
 12 files changed, 11 insertions(+), 30 deletions(-)

diff --git a/src/soc/intel/alderlake/chipset.cb b/src/soc/intel/alderlake/chipset.cb
index 3d2ced5f00..487b4ca961 100644
--- a/src/soc/intel/alderlake/chipset.cb
+++ b/src/soc/intel/alderlake/chipset.cb
@@ -168,7 +168,7 @@ chip soc/intel/alderlake
 				end
 			end
 		end
-		device pci 0d.1 alias tcss_xdci off end
+		device pci 0d.1 alias tcss_xdci off ops usb_xdci_ops end
 		device pci 0d.2 alias tcss_dma0 off end
 		device pci 0d.3 alias tcss_dma1 off end
 		device pci 0e.0 alias vmd off end
diff --git a/src/soc/intel/alderlake/chipset_pch_s.cb b/src/soc/intel/alderlake/chipset_pch_s.cb
index 6e4247817a..6d7be6f10d 100644
--- a/src/soc/intel/alderlake/chipset_pch_s.cb
+++ b/src/soc/intel/alderlake/chipset_pch_s.cb
@@ -360,7 +360,7 @@ chip soc/intel/alderlake
 				end
 			end
 		end
-		device pci 14.1 alias xdci off end
+		device pci 14.1 alias xdci off ops usb_xdci_ops end
 		device pci 14.2 alias shared_sram off end
 		device pci 14.3 alias cnvi_wifi off end
 		device pci 15.0 alias i2c0 off ops i2c_dev_ops end
diff --git a/src/soc/intel/apollolake/chipset_apl.cb b/src/soc/intel/apollolake/chipset_apl.cb
index 5abba624bf..f8bb1b0fd5 100644
--- a/src/soc/intel/apollolake/chipset_apl.cb
+++ b/src/soc/intel/apollolake/chipset_apl.cb
@@ -23,7 +23,7 @@ chip soc/intel/apollolake
 		device pci 14.0 alias pcie_rp05		off ops pcie_rp_ops	end # PCIE Express Root Port 5
 		device pci 14.1 alias pcie_rp06		off ops pcie_rp_ops	end # PCIE Express Root Port 6
 		device pci 15.0 alias xhci		off ops usb_xhci_ops end # XHCI
-		device pci 15.1 alias xdci		off	end # XDCI
+		device pci 15.1 alias xdci		off ops usb_xdci_ops end # XDCI
 		device pci 16.0 alias i2c0		off ops i2c_dev_ops end # I2C0
 		device pci 16.1 alias i2c1		off ops i2c_dev_ops end # I2C1
 		device pci 16.2 alias i2c2		off ops i2c_dev_ops end # I2C2
diff --git a/src/soc/intel/apollolake/chipset_glk.cb b/src/soc/intel/apollolake/chipset_glk.cb
index 9a8732dd94..818954dd52 100644
--- a/src/soc/intel/apollolake/chipset_glk.cb
+++ b/src/soc/intel/apollolake/chipset_glk.cb
@@ -24,7 +24,7 @@ chip soc/intel/apollolake
 		device pci 14.0 alias pcie_rp05		off ops pcie_rp_ops	end # PCIE Express Root Port 5
 		device pci 14.1 alias pcie_rp06		off ops pcie_rp_ops	end # PCIE Express Root Port 6
 		device pci 15.0 alias xhci		off ops usb_xhci_ops end # XHCI
-		device pci 15.1 alias xdci		off	end # XDCI
+		device pci 15.1 alias xdci		off ops usb_xdci_ops end # XDCI
 		device pci 16.0 alias i2c0		off ops i2c_dev_ops end # I2C0
 		device pci 16.1 alias i2c1		off ops i2c_dev_ops end # I2C1
 		device pci 16.2 alias i2c2		off ops i2c_dev_ops end # I2C2
diff --git a/src/soc/intel/cannonlake/chipset.cb b/src/soc/intel/cannonlake/chipset.cb
index 5b94869d87..a8d5d3133f 100644
--- a/src/soc/intel/cannonlake/chipset.cb
+++ b/src/soc/intel/cannonlake/chipset.cb
@@ -78,7 +78,7 @@ chip soc/intel/cannonlake
 				end
 			end
 		end
-		device pci 14.1 alias xdci         off	end	# USB xDCI (OTG)
+		device pci 14.1 alias xdci         off ops usb_xdci_ops end	# USB xDCI (OTG)
 		device pci 14.2 alias shared_sram  off  end	# Shared SRAM
 		device pci 14.3 alias cnvi_wifi    off	end	# CNVi Wifi
 		device pci 14.5 alias sdxc         off	end	# SDCard
diff --git a/src/soc/intel/cannonlake/chipset_pch_h.cb b/src/soc/intel/cannonlake/chipset_pch_h.cb
index 9d96061bf1..89411e7cbc 100644
--- a/src/soc/intel/cannonlake/chipset_pch_h.cb
+++ b/src/soc/intel/cannonlake/chipset_pch_h.cb
@@ -102,7 +102,7 @@ chip soc/intel/cannonlake
 				end
 			end
 		end
-		device pci 14.1 alias xdci         off	end	# USB xDCI (OTG)
+		device pci 14.1 alias xdci         off ops usb_xdci_ops end	# USB xDCI (OTG)
 		device pci 14.2 alias shared_sram  off  end	# Shared SRAM
 		device pci 14.3 alias cnvi_wifi    off	end	# CNVi Wifi
 		device pci 14.5 alias sdxc         off	end	# SDCard
diff --git a/src/soc/intel/common/block/xdci/xdci.c b/src/soc/intel/common/block/xdci/xdci.c
index 3ead495010..28f8231e7b 100644
--- a/src/soc/intel/common/block/xdci/xdci.c
+++ b/src/soc/intel/common/block/xdci/xdci.c
@@ -29,26 +29,7 @@ struct device_operations usb_xdci_ops = {
 
 static const unsigned short pci_device_ids[] = {
 	PCI_DID_INTEL_NVL_XDCI,
-	PCI_DID_INTEL_WCL_XDCI,
-	PCI_DID_INTEL_PTL_H_XDCI,
-	PCI_DID_INTEL_PTL_U_H_XDCI,
-	PCI_DID_INTEL_MTL_XDCI,
-	PCI_DID_INTEL_ARL_XDCI,
-	PCI_DID_INTEL_ARP_S_XDCI,
-	PCI_DID_INTEL_APL_XDCI,
-	PCI_DID_INTEL_CNL_LP_XDCI,
-	PCI_DID_INTEL_GLK_XDCI,
-	PCI_DID_INTEL_CNP_H_XDCI,
-	PCI_DID_INTEL_CMP_LP_XDCI,
-	PCI_DID_INTEL_CMP_H_XDCI,
-	PCI_DID_INTEL_TGP_LP_XDCI,
-	PCI_DID_INTEL_TGP_H_XDCI,
 	PCI_DID_INTEL_MCC_XDCI,
-	PCI_DID_INTEL_JSP_XDCI,
-	PCI_DID_INTEL_ADP_P_XDCI,
-	PCI_DID_INTEL_ADP_S_XDCI,
-	PCI_DID_INTEL_ADP_M_XDCI,
-	PCI_DID_INTEL_RPP_S_XDCI,
 	0
 };
 
diff --git a/src/soc/intel/jasperlake/chipset.cb b/src/soc/intel/jasperlake/chipset.cb
index c6cc992ae6..4288b425fe 100644
--- a/src/soc/intel/jasperlake/chipset.cb
+++ b/src/soc/intel/jasperlake/chipset.cb
@@ -61,7 +61,7 @@ chip soc/intel/jasperlake
 				end
 			end
 		end
-		device pci 14.1 alias south_xdci	off end
+		device pci 14.1 alias south_xdci	off ops usb_xdci_ops end
 		device pci 14.2 alias shared_ram	off end
 		device pci 14.3 alias cnvi_wifi		off end
 		device pci 14.5 alias sdxc		off end
diff --git a/src/soc/intel/meteorlake/chipset.cb b/src/soc/intel/meteorlake/chipset.cb
index df62835b56..ef023c1e23 100644
--- a/src/soc/intel/meteorlake/chipset.cb
+++ b/src/soc/intel/meteorlake/chipset.cb
@@ -87,7 +87,7 @@ chip soc/intel/meteorlake
 				end
 			end
 		end
-		device pci 0d.1 alias tcss_xdci off end
+		device pci 0d.1 alias tcss_xdci off ops usb_xdci_ops end
 		device pci 0d.2 alias tcss_dma0 off end
 		device pci 0d.3 alias tcss_dma1 off end
 		device pci 0e.0 alias vmd off end
diff --git a/src/soc/intel/pantherlake/chipset_ptl.cb b/src/soc/intel/pantherlake/chipset_ptl.cb
index 82dc449d80..debb0a2bae 100644
--- a/src/soc/intel/pantherlake/chipset_ptl.cb
+++ b/src/soc/intel/pantherlake/chipset_ptl.cb
@@ -162,7 +162,7 @@ chip soc/intel/pantherlake
 				end
 			end
 		end
-		device pci 0d.1 alias tcss_xdci off end
+		device pci 0d.1 alias tcss_xdci off ops usb_xdci_ops end
 		device pci 0d.2 alias tcss_dma0 off end
 		device pci 0d.3 alias tcss_dma1 off end
 		device pci 0e.0 alias vmd off end
diff --git a/src/soc/intel/tigerlake/chipset.cb b/src/soc/intel/tigerlake/chipset.cb
index 9594917ef8..9e33123c73 100644
--- a/src/soc/intel/tigerlake/chipset.cb
+++ b/src/soc/intel/tigerlake/chipset.cb
@@ -112,7 +112,7 @@ chip soc/intel/tigerlake
 				end
 			end
 		end
-		device pci 14.1 alias south_xdci off end
+		device pci 14.1 alias south_xdci off ops usb_xdci_ops end
 		device pci 14.2 alias shared_ram off end
 		device pci 14.3 alias cnvi_wifi off end
 		device pci 15.0 alias i2c0 off ops i2c_dev_ops end
diff --git a/src/soc/intel/tigerlake/chipset_pch_h.cb b/src/soc/intel/tigerlake/chipset_pch_h.cb
index 8b0355a443..fe98239693 100644
--- a/src/soc/intel/tigerlake/chipset_pch_h.cb
+++ b/src/soc/intel/tigerlake/chipset_pch_h.cb
@@ -134,7 +134,7 @@ chip soc/intel/tigerlake
 				end
 			end
 		end
-		device pci 14.1 alias south_xdci off end
+		device pci 14.1 alias south_xdci off ops usb_xdci_ops end
 		device pci 14.2 alias shared_ram off end
 		device pci 14.3 alias cnvi_wifi off end
 		device pci 15.0 alias i2c0 off ops i2c_dev_ops end

From 0d947e59cbbd45c7bdad5c1978f391b309bcd4db Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Sun, 25 Jan 2026 21:01:41 -0600
Subject: [PATCH 3180/3886] soc/intel: Use chipset.cb for CNVI WiFi device ops
 linking

Move CNVI WiFi device operations linking from PCI Device ID matching
to chipset.cb files for all Intel SoCs that have them.

Remove corresponding DIDs from cnvi.c for these SoCs; keep DID
matching only for SoCs without chipset.cb files.

Remove the static declaration from cnvi_wifi_ops so the symbol is
exported and visible outside of cnvi.c.

This standardizes the approach across Intel SoCs and makes the
CNVI WiFi controller configuration explicit in devicetree, and prevents
the endless proliferation of DIDs in the common driver code.

Change-Id: I82a2b20a8b967d1a3d5a80ae477def260c366be7
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90922
Reviewed-by: Jakub "Kuba" Czapiga <czapiga@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/soc/intel/alderlake/chipset.cb        |  2 +-
 src/soc/intel/alderlake/chipset_pch_s.cb  |  2 +-
 src/soc/intel/apollolake/chipset_glk.cb   |  2 +-
 src/soc/intel/cannonlake/chipset.cb       |  2 +-
 src/soc/intel/cannonlake/chipset_pch_h.cb |  2 +-
 src/soc/intel/common/block/cnvi/cnvi.c    | 53 +----------------------
 src/soc/intel/jasperlake/chipset.cb       |  2 +-
 src/soc/intel/meteorlake/chipset.cb       |  2 +-
 src/soc/intel/pantherlake/chipset_ptl.cb  |  2 +-
 src/soc/intel/pantherlake/chipset_wcl.cb  |  2 +-
 src/soc/intel/tigerlake/chipset.cb        |  2 +-
 src/soc/intel/tigerlake/chipset_pch_h.cb  |  2 +-
 12 files changed, 12 insertions(+), 63 deletions(-)

diff --git a/src/soc/intel/alderlake/chipset.cb b/src/soc/intel/alderlake/chipset.cb
index 487b4ca961..a18da51a89 100644
--- a/src/soc/intel/alderlake/chipset.cb
+++ b/src/soc/intel/alderlake/chipset.cb
@@ -231,7 +231,7 @@ chip soc/intel/alderlake
 		end
 		device pci 14.1 alias usb_otg off end
 		device pci 14.2 alias shared_sram off end
-		device pci 14.3 alias cnvi_wifi off end
+		device pci 14.3 alias cnvi_wifi off ops cnvi_wifi_ops end
 		device pci 15.0 alias i2c0 off ops i2c_dev_ops end
 		device pci 15.1 alias i2c1 off ops i2c_dev_ops end
 		device pci 15.2 alias i2c2 off ops i2c_dev_ops end
diff --git a/src/soc/intel/alderlake/chipset_pch_s.cb b/src/soc/intel/alderlake/chipset_pch_s.cb
index 6d7be6f10d..962a46617b 100644
--- a/src/soc/intel/alderlake/chipset_pch_s.cb
+++ b/src/soc/intel/alderlake/chipset_pch_s.cb
@@ -362,7 +362,7 @@ chip soc/intel/alderlake
 		end
 		device pci 14.1 alias xdci off ops usb_xdci_ops end
 		device pci 14.2 alias shared_sram off end
-		device pci 14.3 alias cnvi_wifi off end
+		device pci 14.3 alias cnvi_wifi off ops cnvi_wifi_ops end
 		device pci 15.0 alias i2c0 off ops i2c_dev_ops end
 		device pci 15.1 alias i2c1 off ops i2c_dev_ops end
 		device pci 15.2 alias i2c2 off ops i2c_dev_ops end
diff --git a/src/soc/intel/apollolake/chipset_glk.cb b/src/soc/intel/apollolake/chipset_glk.cb
index 818954dd52..ab5ca0cf36 100644
--- a/src/soc/intel/apollolake/chipset_glk.cb
+++ b/src/soc/intel/apollolake/chipset_glk.cb
@@ -6,7 +6,7 @@ chip soc/intel/apollolake
 		device pci 00.2 alias npk		off	end # NorthPeak
 		device pci 02.0 alias igd		off	end # Integrated Graphics Device
 		device pci 03.0 alias gmm		off	end # GMM
-		device pci 0c.0 alias cnvi		off	end # CNVi
+		device pci 0c.0 alias cnvi		off ops cnvi_wifi_ops end # CNVi
 		device pci 0d.0 alias p2sb		off	end # P2SB
 		device pci 0d.1 alias pmc		off	end # PMC
 		device pci 0d.2 alias fast_spi		off	end # SPI
diff --git a/src/soc/intel/cannonlake/chipset.cb b/src/soc/intel/cannonlake/chipset.cb
index a8d5d3133f..fafb02bf50 100644
--- a/src/soc/intel/cannonlake/chipset.cb
+++ b/src/soc/intel/cannonlake/chipset.cb
@@ -80,7 +80,7 @@ chip soc/intel/cannonlake
 		end
 		device pci 14.1 alias xdci         off ops usb_xdci_ops end	# USB xDCI (OTG)
 		device pci 14.2 alias shared_sram  off  end	# Shared SRAM
-		device pci 14.3 alias cnvi_wifi    off	end	# CNVi Wifi
+		device pci 14.3 alias cnvi_wifi    off ops cnvi_wifi_ops end	# CNVi Wifi
 		device pci 14.5 alias sdxc         off	end	# SDCard
 		device pci 15.0 alias i2c0         off ops i2c_dev_ops end	# I2C #0
 		device pci 15.1 alias i2c1         off ops i2c_dev_ops end	# I2C #1
diff --git a/src/soc/intel/cannonlake/chipset_pch_h.cb b/src/soc/intel/cannonlake/chipset_pch_h.cb
index 89411e7cbc..2ce5269274 100644
--- a/src/soc/intel/cannonlake/chipset_pch_h.cb
+++ b/src/soc/intel/cannonlake/chipset_pch_h.cb
@@ -104,7 +104,7 @@ chip soc/intel/cannonlake
 		end
 		device pci 14.1 alias xdci         off ops usb_xdci_ops end	# USB xDCI (OTG)
 		device pci 14.2 alias shared_sram  off  end	# Shared SRAM
-		device pci 14.3 alias cnvi_wifi    off	end	# CNVi Wifi
+		device pci 14.3 alias cnvi_wifi    off ops cnvi_wifi_ops end	# CNVi Wifi
 		device pci 14.5 alias sdxc         off	end	# SDCard
 		device pci 15.0 alias i2c0         off ops i2c_dev_ops end	# I2C #0
 		device pci 15.1 alias i2c1         off ops i2c_dev_ops end	# I2C #1
diff --git a/src/soc/intel/common/block/cnvi/cnvi.c b/src/soc/intel/common/block/cnvi/cnvi.c
index 0511fd20c0..214bd0890e 100644
--- a/src/soc/intel/common/block/cnvi/cnvi.c
+++ b/src/soc/intel/common/block/cnvi/cnvi.c
@@ -462,7 +462,7 @@ static void cnvw_fill_ssdt(const struct device *dev)
 	acpigen_write_scope_end();
 }
 
-static struct device_operations cnvi_wifi_ops = {
+struct device_operations cnvi_wifi_ops = {
 	.read_resources		= pci_dev_read_resources,
 	.set_resources		= pci_dev_set_resources,
 	.enable_resources	= pci_dev_enable_resources,
@@ -477,61 +477,10 @@ static const unsigned short wifi_pci_device_ids[] = {
 	PCI_DID_INTEL_NVL_CNVI_WIFI_1,
 	PCI_DID_INTEL_NVL_CNVI_WIFI_2,
 	PCI_DID_INTEL_NVL_CNVI_WIFI_3,
-	PCI_DID_INTEL_WCL_CNVI_WIFI_0,
-	PCI_DID_INTEL_WCL_CNVI_WIFI_1,
-	PCI_DID_INTEL_WCL_CNVI_WIFI_2,
-	PCI_DID_INTEL_WCL_CNVI_WIFI_3,
-	PCI_DID_INTEL_PTL_H_CNVI_WIFI_0,
-	PCI_DID_INTEL_PTL_H_CNVI_WIFI_1,
-	PCI_DID_INTEL_PTL_H_CNVI_WIFI_2,
-	PCI_DID_INTEL_PTL_H_CNVI_WIFI_3,
-	PCI_DID_INTEL_PTL_U_H_CNVI_WIFI_0,
-	PCI_DID_INTEL_PTL_U_H_CNVI_WIFI_1,
-	PCI_DID_INTEL_PTL_U_H_CNVI_WIFI_2,
-	PCI_DID_INTEL_PTL_U_H_CNVI_WIFI_3,
 	PCI_DID_INTEL_LNL_CNVI_WIFI_0,
 	PCI_DID_INTEL_LNL_CNVI_WIFI_1,
 	PCI_DID_INTEL_LNL_CNVI_WIFI_2,
 	PCI_DID_INTEL_LNL_CNVI_WIFI_3,
-	PCI_DID_INTEL_MTL_CNVI_WIFI_0,
-	PCI_DID_INTEL_MTL_CNVI_WIFI_1,
-	PCI_DID_INTEL_MTL_CNVI_WIFI_2,
-	PCI_DID_INTEL_MTL_CNVI_WIFI_3,
-	PCI_DID_INTEL_ARL_CNVI_WIFI,
-	PCI_DID_INTEL_ARP_S_CNVI_WIFI,
-	PCI_DID_INTEL_CML_LP_CNVI_WIFI,
-	PCI_DID_INTEL_CML_H_CNVI_WIFI,
-	PCI_DID_INTEL_CNL_LP_CNVI_WIFI,
-	PCI_DID_INTEL_CNL_H_CNVI_WIFI,
-	PCI_DID_INTEL_GLK_CNVI_WIFI,
-	PCI_DID_INTEL_JSL_CNVI_WIFI_0,
-	PCI_DID_INTEL_JSL_CNVI_WIFI_1,
-	PCI_DID_INTEL_JSL_CNVI_WIFI_2,
-	PCI_DID_INTEL_JSL_CNVI_WIFI_3,
-	PCI_DID_INTEL_TGL_CNVI_WIFI_0,
-	PCI_DID_INTEL_TGL_CNVI_WIFI_1,
-	PCI_DID_INTEL_TGL_CNVI_WIFI_2,
-	PCI_DID_INTEL_TGL_CNVI_WIFI_3,
-	PCI_DID_INTEL_TGL_H_CNVI_WIFI_0,
-	PCI_DID_INTEL_TGL_H_CNVI_WIFI_1,
-	PCI_DID_INTEL_TGL_H_CNVI_WIFI_2,
-	PCI_DID_INTEL_TGL_H_CNVI_WIFI_3,
-	PCI_DID_INTEL_ADL_P_CNVI_WIFI_0,
-	PCI_DID_INTEL_ADL_P_CNVI_WIFI_1,
-	PCI_DID_INTEL_ADL_P_CNVI_WIFI_2,
-	PCI_DID_INTEL_ADL_P_CNVI_WIFI_3,
-	PCI_DID_INTEL_ADL_S_CNVI_WIFI_0,
-	PCI_DID_INTEL_ADL_S_CNVI_WIFI_1,
-	PCI_DID_INTEL_ADL_S_CNVI_WIFI_2,
-	PCI_DID_INTEL_ADL_S_CNVI_WIFI_3,
-	PCI_DID_INTEL_ADL_N_CNVI_WIFI_0,
-	PCI_DID_INTEL_ADL_N_CNVI_WIFI_1,
-	PCI_DID_INTEL_ADL_N_CNVI_WIFI_2,
-	PCI_DID_INTEL_ADL_N_CNVI_WIFI_3,
-	PCI_DID_INTEL_RPL_S_CNVI_WIFI_0,
-	PCI_DID_INTEL_RPL_S_CNVI_WIFI_1,
-	PCI_DID_INTEL_RPL_S_CNVI_WIFI_2,
-	PCI_DID_INTEL_RPL_S_CNVI_WIFI_3,
 	0
 };
 
diff --git a/src/soc/intel/jasperlake/chipset.cb b/src/soc/intel/jasperlake/chipset.cb
index 4288b425fe..278ba50050 100644
--- a/src/soc/intel/jasperlake/chipset.cb
+++ b/src/soc/intel/jasperlake/chipset.cb
@@ -63,7 +63,7 @@ chip soc/intel/jasperlake
 		end
 		device pci 14.1 alias south_xdci	off ops usb_xdci_ops end
 		device pci 14.2 alias shared_ram	off end
-		device pci 14.3 alias cnvi_wifi		off end
+		device pci 14.3 alias cnvi_wifi		off ops cnvi_wifi_ops end
 		device pci 14.5 alias sdxc		off end
 		device pci 15.0 alias i2c0		off ops i2c_dev_ops end
 		device pci 15.1 alias i2c1		off ops i2c_dev_ops end
diff --git a/src/soc/intel/meteorlake/chipset.cb b/src/soc/intel/meteorlake/chipset.cb
index ef023c1e23..3488a0f684 100644
--- a/src/soc/intel/meteorlake/chipset.cb
+++ b/src/soc/intel/meteorlake/chipset.cb
@@ -151,7 +151,7 @@ chip soc/intel/meteorlake
 		end
 		device pci 14.1 alias usb_otg off end
 		device pci 14.2 alias pmc_shared_sram off end
-		device pci 14.3 alias cnvi_wifi off end
+		device pci 14.3 alias cnvi_wifi off ops cnvi_wifi_ops end
 		device pci 14.5 alias ieh off end
 		device pci 15.0 alias i2c0 off ops i2c_dev_ops end
 		device pci 15.1 alias i2c1 off ops i2c_dev_ops end
diff --git a/src/soc/intel/pantherlake/chipset_ptl.cb b/src/soc/intel/pantherlake/chipset_ptl.cb
index debb0a2bae..d2521efc78 100644
--- a/src/soc/intel/pantherlake/chipset_ptl.cb
+++ b/src/soc/intel/pantherlake/chipset_ptl.cb
@@ -212,7 +212,7 @@ chip soc/intel/pantherlake
 			end
 		end
 		device pci 14.2 alias pmc_shared_sram off end
-		device pci 14.3 alias cnvi_wifi off end
+		device pci 14.3 alias cnvi_wifi off ops cnvi_wifi_ops end
 		device pci 14.7 alias cnvi_bluetooth off end
 		device pci 14.5 alias ieh off end
 		device pci 15.0 alias i2c0 off ops i2c_dev_ops end
diff --git a/src/soc/intel/pantherlake/chipset_wcl.cb b/src/soc/intel/pantherlake/chipset_wcl.cb
index ccc5948d1f..465ad05ad9 100644
--- a/src/soc/intel/pantherlake/chipset_wcl.cb
+++ b/src/soc/intel/pantherlake/chipset_wcl.cb
@@ -98,7 +98,7 @@ chip soc/intel/pantherlake
 			end
 		end
 		device pci 14.2 alias pmc_shared_sram off end
-		device pci 14.3 alias cnvi_wifi off end
+		device pci 14.3 alias cnvi_wifi off ops cnvi_wifi_ops end
 		device pci 14.7 alias cnvi_bluetooth off end
 		device pci 14.5 alias ieh off end
 		device pci 15.0 alias i2c0 off ops i2c_dev_ops end
diff --git a/src/soc/intel/tigerlake/chipset.cb b/src/soc/intel/tigerlake/chipset.cb
index 9e33123c73..725f8296a3 100644
--- a/src/soc/intel/tigerlake/chipset.cb
+++ b/src/soc/intel/tigerlake/chipset.cb
@@ -114,7 +114,7 @@ chip soc/intel/tigerlake
 		end
 		device pci 14.1 alias south_xdci off ops usb_xdci_ops end
 		device pci 14.2 alias shared_ram off end
-		device pci 14.3 alias cnvi_wifi off end
+		device pci 14.3 alias cnvi_wifi off ops cnvi_wifi_ops end
 		device pci 15.0 alias i2c0 off ops i2c_dev_ops end
 		device pci 15.1 alias i2c1 off ops i2c_dev_ops end
 		device pci 15.2 alias i2c2 off ops i2c_dev_ops end
diff --git a/src/soc/intel/tigerlake/chipset_pch_h.cb b/src/soc/intel/tigerlake/chipset_pch_h.cb
index fe98239693..28adb940e4 100644
--- a/src/soc/intel/tigerlake/chipset_pch_h.cb
+++ b/src/soc/intel/tigerlake/chipset_pch_h.cb
@@ -136,7 +136,7 @@ chip soc/intel/tigerlake
 		end
 		device pci 14.1 alias south_xdci off ops usb_xdci_ops end
 		device pci 14.2 alias shared_ram off end
-		device pci 14.3 alias cnvi_wifi off end
+		device pci 14.3 alias cnvi_wifi off ops cnvi_wifi_ops end
 		device pci 15.0 alias i2c0 off ops i2c_dev_ops end
 		device pci 15.1 alias i2c1 off ops i2c_dev_ops end
 		device pci 15.2 alias i2c2 off ops i2c_dev_ops end

From b4b4d6c730711880f29d3c0467d99c18ad7ccc8e Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Sun, 25 Jan 2026 21:07:41 -0600
Subject: [PATCH 3181/3886] soc/intel: Use chipset.cb for SDXC device ops
 linking

Move SDXC device operations linking from PCI Device ID matching
to chipset.cb files for all Intel SoCs that have them, matching the
approach used by Skylake.

Remove corresponding DIDs from sd.c for these SoCs; keep DID
matching only for SoCs without chipset.cb files.

This standardizes the approach across Intel SoCs and makes the
SDXC controller configuration explicit in devicetree, and prevents
the endless proliferation of DIDs in the common driver code.

Change-Id: Ifee16988d0e5625a7b3c2be51ab70d2c8471747a
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90923
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jakub "Kuba" Czapiga <czapiga@google.com>
---
 src/soc/intel/apollolake/chipset_apl.cb   | 2 +-
 src/soc/intel/cannonlake/chipset.cb       | 2 +-
 src/soc/intel/cannonlake/chipset_pch_h.cb | 2 +-
 src/soc/intel/common/block/scs/sd.c       | 6 ------
 src/soc/intel/jasperlake/chipset.cb       | 2 +-
 5 files changed, 4 insertions(+), 10 deletions(-)

diff --git a/src/soc/intel/apollolake/chipset_apl.cb b/src/soc/intel/apollolake/chipset_apl.cb
index f8bb1b0fd5..fc2ec2822d 100644
--- a/src/soc/intel/apollolake/chipset_apl.cb
+++ b/src/soc/intel/apollolake/chipset_apl.cb
@@ -40,7 +40,7 @@ chip soc/intel/apollolake
 		device pci 19.1 alias spi1		off ops spi_dev_ops end # SPI1
 		device pci 19.2 alias spi2		off ops spi_dev_ops end # SPI3
 		device pci 1a.0 alias pwm		off	end # PWM
-		device pci 1b.0 alias sdcard		off	end # SD Card
+		device pci 1b.0 alias sdcard		off ops sd_ops end # SD Card
 		device pci 1c.0 alias emmc		off	end # eMMC
 		device pci 1e.0 alias sdio		off	end # SDIO
 		device pci 1f.0 alias lpc_espi		on	end # LPC
diff --git a/src/soc/intel/cannonlake/chipset.cb b/src/soc/intel/cannonlake/chipset.cb
index fafb02bf50..ff68963c3e 100644
--- a/src/soc/intel/cannonlake/chipset.cb
+++ b/src/soc/intel/cannonlake/chipset.cb
@@ -81,7 +81,7 @@ chip soc/intel/cannonlake
 		device pci 14.1 alias xdci         off ops usb_xdci_ops end	# USB xDCI (OTG)
 		device pci 14.2 alias shared_sram  off  end	# Shared SRAM
 		device pci 14.3 alias cnvi_wifi    off ops cnvi_wifi_ops end	# CNVi Wifi
-		device pci 14.5 alias sdxc         off	end	# SDCard
+		device pci 14.5 alias sdxc         off ops sd_ops end	# SDCard
 		device pci 15.0 alias i2c0         off ops i2c_dev_ops end	# I2C #0
 		device pci 15.1 alias i2c1         off ops i2c_dev_ops end	# I2C #1
 		device pci 15.2 alias i2c2         off ops i2c_dev_ops end	# I2C #2
diff --git a/src/soc/intel/cannonlake/chipset_pch_h.cb b/src/soc/intel/cannonlake/chipset_pch_h.cb
index 2ce5269274..de36773c50 100644
--- a/src/soc/intel/cannonlake/chipset_pch_h.cb
+++ b/src/soc/intel/cannonlake/chipset_pch_h.cb
@@ -105,7 +105,7 @@ chip soc/intel/cannonlake
 		device pci 14.1 alias xdci         off ops usb_xdci_ops end	# USB xDCI (OTG)
 		device pci 14.2 alias shared_sram  off  end	# Shared SRAM
 		device pci 14.3 alias cnvi_wifi    off ops cnvi_wifi_ops end	# CNVi Wifi
-		device pci 14.5 alias sdxc         off	end	# SDCard
+		device pci 14.5 alias sdxc         off ops sd_ops end	# SDCard
 		device pci 15.0 alias i2c0         off ops i2c_dev_ops end	# I2C #0
 		device pci 15.1 alias i2c1         off ops i2c_dev_ops end	# I2C #1
 		device pci 15.2 alias i2c2         off ops i2c_dev_ops end	# I2C #2
diff --git a/src/soc/intel/common/block/scs/sd.c b/src/soc/intel/common/block/scs/sd.c
index eee02009f1..84eac7ef75 100644
--- a/src/soc/intel/common/block/scs/sd.c
+++ b/src/soc/intel/common/block/scs/sd.c
@@ -49,14 +49,8 @@ struct device_operations sd_ops = {
 };
 
 static const unsigned short pci_device_ids[] = {
-	PCI_DID_INTEL_APL_SD,
-	PCI_DID_INTEL_CNL_SD,
 	PCI_DID_INTEL_GLK_SD,
-	PCI_DID_INTEL_CNP_H_SD,
-	PCI_DID_INTEL_CMP_SD,
-	PCI_DID_INTEL_CMP_H_SD,
 	PCI_DID_INTEL_MCC_SD,
-	PCI_DID_INTEL_JSP_SD,
 	0
 };
 
diff --git a/src/soc/intel/jasperlake/chipset.cb b/src/soc/intel/jasperlake/chipset.cb
index 278ba50050..cbd5d2efc9 100644
--- a/src/soc/intel/jasperlake/chipset.cb
+++ b/src/soc/intel/jasperlake/chipset.cb
@@ -64,7 +64,7 @@ chip soc/intel/jasperlake
 		device pci 14.1 alias south_xdci	off ops usb_xdci_ops end
 		device pci 14.2 alias shared_ram	off end
 		device pci 14.3 alias cnvi_wifi		off ops cnvi_wifi_ops end
-		device pci 14.5 alias sdxc		off end
+		device pci 14.5 alias sdxc		off ops sd_ops end
 		device pci 15.0 alias i2c0		off ops i2c_dev_ops end
 		device pci 15.1 alias i2c1		off ops i2c_dev_ops end
 		device pci 15.2 alias i2c2		off ops i2c_dev_ops end

From 8a8b0df24dc911e9f73528f5a95aabc5fc4100b5 Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Fri, 23 Jan 2026 11:34:47 -0600
Subject: [PATCH 3182/3886] soc/intel/pantherlake/fsp_params: Use common PCIe
 RP power management
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Select SOC_INTEL_COMMON_BLOCK_ASPM and use the SoC common code for
programming PCIe root port power management. This adds programming of
PCIe RP clock PM and port speed, as well as allows for user override
via setup options for all fields. Remove the now-unused static methods
get_l1_substate_control() and get_aspm_control().

Additionally, check the port enable status before declaring the root
port config struct, to be consistent with ADL and MTL.

Change-Id: Ic30d714e609612ea46d34252c7c1d799652a9c2b
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90879
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/soc/intel/pantherlake/Kconfig      |  1 +
 src/soc/intel/pantherlake/fsp_params.c | 49 ++------------------------
 2 files changed, 4 insertions(+), 46 deletions(-)

diff --git a/src/soc/intel/pantherlake/Kconfig b/src/soc/intel/pantherlake/Kconfig
index bf02cde32f..59369a6a46 100644
--- a/src/soc/intel/pantherlake/Kconfig
+++ b/src/soc/intel/pantherlake/Kconfig
@@ -62,6 +62,7 @@ config SOC_INTEL_PANTHERLAKE_BASE
 	select SOC_INTEL_COMMON_BLOCK_ACPI_LPIT
 	select SOC_INTEL_COMMON_BLOCK_ACPI_PEP
 	select SOC_INTEL_COMMON_BLOCK_ACPI_PEP_LPM_REQ
+	select SOC_INTEL_COMMON_BLOCK_ASPM
 	select SOC_INTEL_COMMON_BLOCK_CAR
 	select SOC_INTEL_COMMON_BLOCK_CHIP_CONFIG
 	select SOC_INTEL_COMMON_BLOCK_CNVI
diff --git a/src/soc/intel/pantherlake/fsp_params.c b/src/soc/intel/pantherlake/fsp_params.c
index 2fbcbea5b9..d447879475 100644
--- a/src/soc/intel/pantherlake/fsp_params.c
+++ b/src/soc/intel/pantherlake/fsp_params.c
@@ -9,6 +9,7 @@
 #include <fsp/fsp_debug_event.h>
 #include <fsp/fsp_gop_blt.h>
 #include <fsp/ppi/mp_service_ppi.h>
+#include <intelblocks/aspm.h>
 #include <intelblocks/irq.h>
 #include <intelblocks/mp_init.h>
 #include <intelblocks/pmclib.h>
@@ -59,47 +60,6 @@ static const pci_devfn_t gspi_dev[] = {
 	PCI_DEVFN_GSPI2
 };
 
-/*
- * Chip config parameter PcieRpL1Substates uses (UPD value + 1)
- * because UPD value of 0 for PcieRpL1Substates means disabled for FSP.
- * In order to ensure that mainboard setting does not disable L1 substates
- * incorrectly, chip config parameter values are offset by 1 with 0 meaning
- * use FSP UPD default. get_l1_substate_control() ensures that the right UPD
- * value is set in fsp_params.
- * 0: Use FSP UPD default
- * 1: Disable L1 substates
- * 2: Use L1.1
- * 3: Use L1.2 (FSP UPD default)
- */
-static int get_l1_substate_control(enum L1_substates_control ctl)
-{
-	if (CONFIG(SOC_INTEL_COMPLIANCE_TEST_MODE))
-		ctl = L1_SS_DISABLED;
-	else if (ctl > L1_SS_L1_2 || ctl == L1_SS_FSP_DEFAULT)
-		ctl = L1_SS_L1_2;
-	return ctl - 1;
-}
-
-/*
- * Chip config parameter pcie_rp_aspm uses (UPD value + 1) because
- * a UPD value of 0 for pcie_rp_aspm means disabled. In order to ensure
- * that the mainboard setting does not disable ASPM incorrectly, chip
- * config parameter values are offset by 1 with 0 meaning use FSP UPD default.
- * get_aspm_control() ensures that the right UPD value is set in fsp_params.
- * 0: Use FSP UPD default
- * 1: Disable ASPM
- * 2: L0s only
- * 3: L1 only
- * 4: L0s and L1
- * 5: Auto configuration
- */
-static unsigned int get_aspm_control(enum ASPM_control ctl)
-{
-	if (ctl > ASPM_AUTO || ctl == ASPM_DEFAULT)
-		ctl = ASPM_AUTO;
-	return ctl - 1;
-}
-
 __weak void mainboard_update_soc_chip_config(struct soc_intel_pantherlake_config *config)
 {
 	/* Override settings per board. */
@@ -629,19 +589,16 @@ static void fill_fsps_pcie_params(FSP_S_CONFIG *s_cfg,
 	uint32_t enable_mask = pcie_rp_enable_mask(get_pcie_rp_table());
 
 	for (size_t i = 0; i < CONFIG_MAX_ROOT_PORTS; i++) {
-		const struct pcie_rp_config *rp_cfg = &config->pcie_rp[i];
 		if (!(enable_mask & BIT(i)))
 			continue;
-		s_cfg->PcieRpL1Substates[i] =
-			get_l1_substate_control(rp_cfg->PcieRpL1Substates);
+		const struct pcie_rp_config *rp_cfg = &config->pcie_rp[i];
 		s_cfg->PcieRpLtrEnable[i] = !!(rp_cfg->flags & PCIE_RP_LTR);
 		s_cfg->PcieRpAdvancedErrorReporting[i] = !!(rp_cfg->flags & PCIE_RP_AER);
 		s_cfg->PcieRpHotPlug[i] =
 			!!(rp_cfg->flags & PCIE_RP_HOTPLUG) || CONFIG(SOC_INTEL_COMPLIANCE_TEST_MODE);
 		s_cfg->PcieRpClkReqDetect[i] = !!(rp_cfg->flags & PCIE_RP_CLK_REQ_DETECT);
 		s_cfg->PcieRpDetectTimeoutMs[i] = rp_cfg->pcie_rp_detect_timeout_ms;
-		if (rp_cfg->pcie_rp_aspm)
-			s_cfg->PcieRpAspm[i] = get_aspm_control(rp_cfg->pcie_rp_aspm);
+		configure_pch_rp_power_management(s_cfg, rp_cfg, i);
 	}
 
 	s_cfg->PcieComplianceTestMode = CONFIG(SOC_INTEL_COMPLIANCE_TEST_MODE);

From 317d2e43e587ce908ab01ccb717501af9e3a48f3 Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Mon, 26 Jan 2026 11:32:53 -0600
Subject: [PATCH 3183/3886] soc/intel/apollolake: Add USB port aliases to
 chipset.cb
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Add USB port aliases to chipset_glk.cb and chipset_apl.cb to enable
boards to use device ref syntax for USB devices. Port counts match
hardware specs: GLK has 9 USB2/7 USB3 ports, APL has 8 USB2/7 USB3
ports.

Select 'DRIVERS_USB_ACPI' so that the required USB ACPI drivers are
built and linked for all boards.

Change-Id: Ibc7dd2cbfda8c8eb42b243ea7adcdb6d1fdea98b
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90924
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Reviewed-by: Eric Lai <ericllai@google.com>
---
 src/soc/intel/apollolake/Kconfig        |  1 +
 src/soc/intel/apollolake/chipset_apl.cb | 53 ++++++++++++++++++++++-
 src/soc/intel/apollolake/chipset_glk.cb | 56 ++++++++++++++++++++++++-
 3 files changed, 108 insertions(+), 2 deletions(-)

diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig
index 18e8466cff..2f0ea9953d 100644
--- a/src/soc/intel/apollolake/Kconfig
+++ b/src/soc/intel/apollolake/Kconfig
@@ -20,6 +20,7 @@ config SOC_INTEL_APOLLOLAKE
 	select SOC_INTEL_COMMON_NHLT
 	# Misc options
 	select CACHE_MRC_SETTINGS
+	select DRIVERS_USB_ACPI
 	select EDK2_CPU_TIMER_LIB if PAYLOAD_EDK2
 	select FAST_SPI_GENERATE_SSDT
 	select FSP_PLATFORM_MEMORY_SETTINGS_VERSIONS
diff --git a/src/soc/intel/apollolake/chipset_apl.cb b/src/soc/intel/apollolake/chipset_apl.cb
index fc2ec2822d..547cbee2f8 100644
--- a/src/soc/intel/apollolake/chipset_apl.cb
+++ b/src/soc/intel/apollolake/chipset_apl.cb
@@ -22,7 +22,58 @@ chip soc/intel/apollolake
 		device pci 13.3 alias pcie_rp04		off ops pcie_rp_ops	end # PCIE Express Root Port 4
 		device pci 14.0 alias pcie_rp05		off ops pcie_rp_ops	end # PCIE Express Root Port 5
 		device pci 14.1 alias pcie_rp06		off ops pcie_rp_ops	end # PCIE Express Root Port 6
-		device pci 15.0 alias xhci		off ops usb_xhci_ops end # XHCI
+		device pci 15.0 alias xhci		off ops usb_xhci_ops
+			chip drivers/usb/acpi
+				register "type" = "UPC_TYPE_HUB"
+				device usb 0.0 alias xhci_root_hub off
+					chip drivers/usb/acpi
+						device usb 2.0 alias usb2_port1 off end
+					end
+					chip drivers/usb/acpi
+						device usb 2.1 alias usb2_port2 off end
+					end
+					chip drivers/usb/acpi
+						device usb 2.2 alias usb2_port3 off end
+					end
+					chip drivers/usb/acpi
+						device usb 2.3 alias usb2_port4 off end
+					end
+					chip drivers/usb/acpi
+						device usb 2.4 alias usb2_port5 off end
+					end
+					chip drivers/usb/acpi
+						device usb 2.5 alias usb2_port6 off end
+					end
+					chip drivers/usb/acpi
+						device usb 2.6 alias usb2_port7 off end
+					end
+					chip drivers/usb/acpi
+						device usb 2.7 alias usb2_port8 off end
+					end
+					chip drivers/usb/acpi
+						device usb 3.0 alias usb3_port1 off end
+					end
+					chip drivers/usb/acpi
+						device usb 3.1 alias usb3_port2 off end
+					end
+					chip drivers/usb/acpi
+						device usb 3.2 alias usb3_port3 off end
+					end
+					chip drivers/usb/acpi
+						device usb 3.3 alias usb3_port4 off end
+					end
+					chip drivers/usb/acpi
+						device usb 3.4 alias usb3_port5 off end
+					end
+					chip drivers/usb/acpi
+						device usb 3.5 alias usb3_port6 off end
+					end
+					chip drivers/usb/acpi
+						device usb 3.6 alias usb3_port7 off end
+					end
+				end
+			end
+		end # XHCI
 		device pci 15.1 alias xdci		off ops usb_xdci_ops end # XDCI
 		device pci 16.0 alias i2c0		off ops i2c_dev_ops end # I2C0
 		device pci 16.1 alias i2c1		off ops i2c_dev_ops end # I2C1
diff --git a/src/soc/intel/apollolake/chipset_glk.cb b/src/soc/intel/apollolake/chipset_glk.cb
index ab5ca0cf36..dbbab3dab3 100644
--- a/src/soc/intel/apollolake/chipset_glk.cb
+++ b/src/soc/intel/apollolake/chipset_glk.cb
@@ -23,7 +23,61 @@ chip soc/intel/apollolake
 		device pci 13.3 alias pcie_rp04		off ops pcie_rp_ops	end # PCIE Express Root Port 4
 		device pci 14.0 alias pcie_rp05		off ops pcie_rp_ops	end # PCIE Express Root Port 5
 		device pci 14.1 alias pcie_rp06		off ops pcie_rp_ops	end # PCIE Express Root Port 6
-		device pci 15.0 alias xhci		off ops usb_xhci_ops end # XHCI
+		device pci 15.0 alias xhci		off ops usb_xhci_ops
+			chip drivers/usb/acpi
+				register "type" = "UPC_TYPE_HUB"
+				device usb 0.0 alias xhci_root_hub off
+					chip drivers/usb/acpi
+						device usb 2.0 alias usb2_port1 off end
+					end
+					chip drivers/usb/acpi
+						device usb 2.1 alias usb2_port2 off end
+					end
+					chip drivers/usb/acpi
+						device usb 2.2 alias usb2_port3 off end
+					end
+					chip drivers/usb/acpi
+						device usb 2.3 alias usb2_port4 off end
+					end
+					chip drivers/usb/acpi
+						device usb 2.4 alias usb2_port5 off end
+					end
+					chip drivers/usb/acpi
+						device usb 2.5 alias usb2_port6 off end
+					end
+					chip drivers/usb/acpi
+						device usb 2.6 alias usb2_port7 off end
+					end
+					chip drivers/usb/acpi
+						device usb 2.7 alias usb2_port8 off end
+					end
+					chip drivers/usb/acpi
+						device usb 2.8 alias usb2_port9 off end
+					end
+					chip drivers/usb/acpi
+						device usb 3.0 alias usb3_port1 off end
+					end
+					chip drivers/usb/acpi
+						device usb 3.1 alias usb3_port2 off end
+					end
+					chip drivers/usb/acpi
+						device usb 3.2 alias usb3_port3 off end
+					end
+					chip drivers/usb/acpi
+						device usb 3.3 alias usb3_port4 off end
+					end
+					chip drivers/usb/acpi
+						device usb 3.4 alias usb3_port5 off end
+					end
+					chip drivers/usb/acpi
+						device usb 3.5 alias usb3_port6 off end
+					end
+					chip drivers/usb/acpi
+						device usb 3.6 alias usb3_port7 off end
+					end
+				end
+			end
+		end # XHCI
 		device pci 15.1 alias xdci		off ops usb_xdci_ops end # XDCI
 		device pci 16.0 alias i2c0		off ops i2c_dev_ops end # I2C0
 		device pci 16.1 alias i2c1		off ops i2c_dev_ops end # I2C1

From 94d1bb7ff918fa3790eda13beeac4e5810cf4c78 Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Mon, 26 Jan 2026 12:34:32 -0600
Subject: [PATCH 3184/3886] mb/google/octopus: Drop selection of
 DRIVERS_USB_ACPI

It's selected at the SoC level now, so no need for the mainboard to
select it as well.

TEST=build octopus

Change-Id: Id8bf73de73fd9c93e875c52b339b63970c32d50a
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90926
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
---
 src/mainboard/google/octopus/Kconfig | 1 -
 1 file changed, 1 deletion(-)

diff --git a/src/mainboard/google/octopus/Kconfig b/src/mainboard/google/octopus/Kconfig
index 1ba172e687..8723820f14 100644
--- a/src/mainboard/google/octopus/Kconfig
+++ b/src/mainboard/google/octopus/Kconfig
@@ -12,7 +12,6 @@ config BOARD_GOOGLE_BASEBOARD_OCTOPUS
 	select DRIVERS_I2C_SX9310
 	select DRIVERS_OPTION_CFR_ENABLED if PAYLOAD_EDK2 && SMMSTORE
 	select DRIVERS_SPI_ACPI
-	select DRIVERS_USB_ACPI
 	select EC_GOOGLE_CHROMEEC
 	select EC_GOOGLE_CHROMEEC_BOARDID
 	select EC_GOOGLE_CHROMEEC_ESPI

From 8cf6088ba563b62d4539660ddb019be71a77fa78 Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Mon, 26 Jan 2026 11:47:28 -0600
Subject: [PATCH 3185/3886] mb/google/octopus: Use aliases in
 device/overridetrees

Convert all PCI device and USB port references in octopus baseboard
devicetree and variant overridetrees to use aliases from the Geminilake
chipset.cb instead of direct device/function numbers. This improves
maintainability by using symbolic names, and reduces file size by
eliminating entries which match those in the chipset or baseboard
devicetrees.

TEST=Build all octopus variants

Change-Id: Ic4f93608234b52d548d8e5f94b137754e8924484
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90925
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
---
 .../octopus/variants/ampton/overridetree.cb   |  16 +--
 .../octopus/variants/baseboard/devicetree.cb  | 112 +++++++-----------
 .../octopus/variants/bloog/overridetree.cb    |  14 +--
 .../octopus/variants/bobba/overridetree.cb    |  20 ++--
 .../octopus/variants/casta/overridetree.cb    |  22 ++--
 .../octopus/variants/dood/overridetree.cb     |  14 +--
 .../octopus/variants/fleex/overridetree.cb    |  18 +--
 .../octopus/variants/foob/overridetree.cb     |  16 +--
 .../octopus/variants/garg/overridetree.cb     |  16 +--
 .../octopus/variants/lick/overridetree.cb     |   8 +-
 .../octopus/variants/meep/overridetree.cb     |  38 +++---
 .../octopus/variants/phaser/overridetree.cb   |  16 +--
 .../octopus/variants/yorp/overridetree.cb     |  16 +--
 13 files changed, 153 insertions(+), 173 deletions(-)

diff --git a/src/mainboard/google/octopus/variants/ampton/overridetree.cb b/src/mainboard/google/octopus/variants/ampton/overridetree.cb
index ee607aa6f0..2647d518e6 100644
--- a/src/mainboard/google/octopus/variants/ampton/overridetree.cb
+++ b/src/mainboard/google/octopus/variants/ampton/overridetree.cb
@@ -71,7 +71,7 @@ chip soc/intel/apollolake
 		},
 	}"
 	device domain 0 on
-		device pci 16.0 on
+		device ref i2c0		on
 			chip drivers/i2c/hid
 				register "generic.hid" = ""WCOM50C1""
 				register "generic.desc" = ""WCOM Digitizer""
@@ -83,8 +83,8 @@ chip soc/intel/apollolake
 				register "hid_desc_reg_offset" = "0x1"
 				device i2c 0x9 on end
 			end
-		end	# - I2C 0
-		device pci 17.1 on
+		end
+		device ref i2c5		on
 			chip drivers/i2c/generic
 				register "hid" = ""10EC5682""
 				register "name" = ""RT58""
@@ -98,8 +98,8 @@ chip soc/intel/apollolake
 				register "property_list[0].integer" = "1"
 				device i2c 1a on end
 			end
-		end	# - I2C 5
-		device pci 17.2 on
+		end
+		device ref i2c6		on
 			chip drivers/i2c/generic
 				register "hid" = ""ELAN0000""
 				register "desc" = ""ELAN Touchpad""
@@ -108,8 +108,8 @@ chip soc/intel/apollolake
 				register "detect" = "1"
 				device i2c 15 on end
 			end
-		end	# - I2C 6
-		device pci 17.3 on
+		end
+		device ref i2c7		on
 			chip drivers/i2c/generic
 				register "hid" = ""ELAN0001""
 				register "desc" = ""ELAN Touchscreen""
@@ -135,6 +135,6 @@ chip soc/intel/apollolake
 				register "hid_desc_reg_offset" = "0x01"
 				device i2c 40 on end
 			end
-		end	# - I2C 7
+		end
 	end
 end
diff --git a/src/mainboard/google/octopus/variants/baseboard/devicetree.cb b/src/mainboard/google/octopus/variants/baseboard/devicetree.cb
index 671150d656..21c68bab82 100644
--- a/src/mainboard/google/octopus/variants/baseboard/devicetree.cb
+++ b/src/mainboard/google/octopus/variants/baseboard/devicetree.cb
@@ -106,168 +106,148 @@ chip soc/intel/apollolake
 	register "pnp_settings" = "PNP_PERF_POWER"
 
 	device domain 0 on
-		device pci 00.0 on  end	# - Host Bridge
-		device pci 00.1 on  end	# - DPTF
-		device pci 00.2 off end	# - NPK
-		device pci 02.0 on	# - Gen
+		device ref igd		on
 			register "gfx" = "GMA_DEFAULT_PANEL(0)"
 		end
-		device pci 03.0 off end # - Gaussian Mixture Model (GMM)
-		device pci 0c.0 on
+		device ref cnvi		on
 			chip drivers/wifi/generic
 				register "wake" = "GPE0A_CNVI_PME_STS"
 				device generic 0 on end
 			end
-		end	# - CNVi
-		device pci 0d.0 on  end	# - P2SB
-		device pci 0d.1 on  end	# - PMC
-		device pci 0d.2 on  end	# - Fast SPI
-		device pci 0d.3 on  end	# - Shared SRAM
-		device pci 0e.0 on
+		end
+		device ref p2sb		on end
+		device ref pmc		on end
+		device ref fast_spi	on end
+		device ref sram		on end
+		device ref hda		on
 			chip drivers/generic/max98357a
 				register "hid" = ""MX98357A""
 				register "sdmode_gpio" =  "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_91)"
 				register "sdmode_delay" = "5"
 				device generic 0 on end
 			end
-		end	# - Audio
-		device pci 0f.0 on  end	# - Heci1
-		device pci 0f.1 on  end	# - Heci2
-		device pci 0f.2 on  end	# - Heci3
-		device pci 11.0 off end	# - ISH
-		device pci 12.0 off end	# - SATA
-		device pci 13.0 on
+		end
+		device ref heci1	on end
+		device ref heci2	on end
+		device ref heci3	on end
+		device ref pcie_rp01	on
 			chip drivers/wifi/generic
 				register "wake" = "GPE0_DW3_11"
 				device pci 00.0 on end
 			end
-		end	# - PCIe-A 0 Onboard M2 Slot(Wifi)
-		device pci 13.1 off end	# - PCIe-A 1
-		device pci 13.2 off end	# - PCIe-A 2
-		device pci 13.3 off end	# - PCIe-A 3
-		device pci 14.0 off end	# - PCIe-B 0
-		device pci 14.1 off end	# - PCIe-B 1
-		device pci 15.0 on
+		end
+		device ref xhci		on
 			chip drivers/usb/acpi
 				register "desc" = ""Root Hub""
 				register "type" = "UPC_TYPE_HUB"
-				device usb 0.0 on
+				device ref xhci_root_hub on
 					chip drivers/usb/acpi
 						register "desc" = ""Left Type-C Port""
 						register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
 						register "group" = "ACPI_PLD_GROUP(1, 1)"
-						device usb 2.0 on end
+						device ref usb2_port1 on end
 					end
 					chip drivers/usb/acpi
 						register "desc" = ""Left Type-A Port""
 						register "type" = "UPC_TYPE_A"
 						register "group" = "ACPI_PLD_GROUP(1, 2)"
-						device usb 2.1 on end
+						device ref usb2_port2 on end
 					end
 					chip drivers/usb/acpi
 						register "desc" = ""Bluetooth""
 						register "type" = "UPC_TYPE_INTERNAL"
 						register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPIO_109)"
-						device usb 2.2 on end
+						device ref usb2_port3 on end
 					end
 					chip drivers/usb/acpi
 						register "desc" = ""Right Type-A Port""
 						register "type" = "UPC_TYPE_A"
 						register "group" = "ACPI_PLD_GROUP(2, 2)"
-						device usb 2.3 on end
+						device ref usb2_port4 on end
 					end
 					chip drivers/usb/acpi
 						register "desc" = ""Right Type-C Port""
 						register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
 						register "group" = "ACPI_PLD_GROUP(2, 1)"
-						device usb 2.4 on end
+						device ref usb2_port5 on end
 					end
 					chip drivers/usb/acpi
 						register "desc" = ""SDCard""
 						register "type" = "UPC_TYPE_EXPRESSCARD"
-						device usb 2.5 on end
+						device ref usb2_port6 on end
 					end
 					chip drivers/usb/acpi
 						register "desc" = ""User Facing Camera""
 						register "type" = "UPC_TYPE_INTERNAL"
-						device usb 2.6 on end
+						device ref usb2_port7 on end
 					end
 					chip drivers/usb/acpi
 						register "desc" = ""World Facing Camera""
 						register "type" = "UPC_TYPE_INTERNAL"
-						device usb 2.7 on end
+						device ref usb2_port8 on end
 					end
 					chip drivers/usb/acpi
 						register "desc" = ""Bluetooth""
 						register "type" = "UPC_TYPE_INTERNAL"
 						register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPIO_109)"
-						device usb 2.8 on end
+						device ref usb2_port9 on end
 					end
 					chip drivers/usb/acpi
 						register "desc" = ""Left Type-C Port""
 						register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
 						register "group" = "ACPI_PLD_GROUP(1, 1)"
-						device usb 3.0 on end
+						device ref usb3_port1 on end
 					end
 					chip drivers/usb/acpi
 						register "desc" = ""Left Type-A Port""
 						register "type" = "UPC_TYPE_USB3_A"
 						register "group" = "ACPI_PLD_GROUP(1, 2)"
-						device usb 3.1 on end
+						device ref usb3_port2 on end
 					end
 					chip drivers/usb/acpi
 						register "desc" = ""Right Type-A Port""
 						register "type" = "UPC_TYPE_USB3_A"
 						register "group" = "ACPI_PLD_GROUP(2, 2)"
-						device usb 3.3 on end
+						device ref usb3_port4 on end
 					end
 					chip drivers/usb/acpi
 						register "desc" = ""Right Type-C Port""
 						register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
 						register "group" = "ACPI_PLD_GROUP(2, 1)"
-						device usb 3.4 on end
+						device ref usb3_port5 on end
 					end
 					chip drivers/usb/acpi
 						register "desc" = ""SDCard""
 						register "type" = "UPC_TYPE_EXPRESSCARD"
-						device usb 3.5 on end
+						device ref usb3_port6 on end
 					end
 				end
 			end
-		end	# - XHCI
-		device pci 15.1 off end	# - XDCI
-		device pci 16.0 on  end	# - I2C 0
-		device pci 16.1 off  end	# - I2C 1
-		device pci 16.2 off  end	# - I2C 2
-		device pci 16.3 off  end	# - I2C 3
-		device pci 17.0 on  end	# - I2C 4
-		device pci 17.1 on  end	# - I2C 5
-		device pci 17.2 on  end	# - I2C 6
-		device pci 17.3 off end	# - I2C 7
-		device pci 18.0 on  end	# - UART 0
-		device pci 18.1 off end	# - UART 1
-		device pci 18.2 on  end	# - UART 2
-		device pci 18.3 off end	# - UART 3
-		device pci 19.0 on
+		end
+		device ref i2c0		on end
+		device ref i2c4		on end
+		device ref i2c5		on end
+		device ref i2c6		on end
+		device ref uart0	on end
+		device ref uart2	on end
+		device ref spi0		on
 			chip drivers/spi/acpi
 				register "hid" = "ACPI_DT_NAMESPACE_HID"
 				register "compat_string" = ""google,cr50""
 				register "irq" = "ACPI_IRQ_EDGE_LOW(GPIO_63_IRQ)"
 				device spi 0 on end
 			end
-		end # - GSPI 0
-		device pci 19.1 off end	# - SPI 1
-		device pci 19.2 on  end	# - SPI 2
-		device pci 1a.0 on  end	# - PWM
-		device pci 1c.0 on  end	# - eMMC
-		device pci 1d.0 on  end # - UFS
-		device pci 1e.0 off end	# - SDIO
-		device pci 1f.0 on
+		end
+		device ref spi2		on end
+		device ref pwm		on end
+		device ref emmc		on end
+		device ref ufs		on end
+		device ref lpc_espi	on
 			chip ec/google/chromeec
 				device pnp 0c09.0 on end
 			end
-		end	# - ESPI
-		device pci 1f.1 on  end	# - SMBUS
+		end
+		device ref smbus	on end
 	end
 
 	# FSP provides UPD interface to execute IPC command. PMIC has
diff --git a/src/mainboard/google/octopus/variants/bloog/overridetree.cb b/src/mainboard/google/octopus/variants/bloog/overridetree.cb
index 32e17cbb1a..5b3db19d90 100644
--- a/src/mainboard/google/octopus/variants/bloog/overridetree.cb
+++ b/src/mainboard/google/octopus/variants/bloog/overridetree.cb
@@ -81,8 +81,8 @@ chip soc/intel/apollolake
 	}"
 
 	device domain 0 on
-		device pci 16.0 off  end     # - I2C 0
-		device pci 17.1 on
+		device ref i2c0		off end
+		device ref i2c5		on
 			chip drivers/i2c/da7219
 				register "irq" = "ACPI_IRQ_LEVEL_LOW(GPIO_137_IRQ)"
 				register "btn_cfg" = "50"
@@ -113,8 +113,8 @@ chip soc/intel/apollolake
 				register "property_list[0].integer" = "1"
 				device i2c 1a on end
 			end
-		end	# - I2C 5
-		device pci 17.2 on
+		end
+		device ref i2c6		on
 			chip drivers/i2c/generic
 				register "hid" = ""ELAN0000""
 				register "desc" = ""ELAN Touchpad""
@@ -123,8 +123,8 @@ chip soc/intel/apollolake
 				register "detect" = "1"
 				device i2c 15 on end
 			end
-		end	# - I2C 6
-		device pci 17.3 on
+		end
+		device ref i2c7		on
 			chip drivers/i2c/generic
 				register "hid" = ""ELAN0001""
 				register "desc" = ""ELAN Touchscreen""
@@ -164,7 +164,7 @@ chip soc/intel/apollolake
 				register "hid_desc_reg_offset" = "0x01"
 				device i2c 40 on end
 			end
-		end	# - I2C 7
+		end
 	end
 
 	# Disable compliance mode
diff --git a/src/mainboard/google/octopus/variants/bobba/overridetree.cb b/src/mainboard/google/octopus/variants/bobba/overridetree.cb
index a79d15e2f1..d466695eb3 100644
--- a/src/mainboard/google/octopus/variants/bobba/overridetree.cb
+++ b/src/mainboard/google/octopus/variants/bobba/overridetree.cb
@@ -92,7 +92,7 @@ chip soc/intel/apollolake
 	}"
 
 	device domain 0 on
-		device pci 16.0 on
+		device ref i2c0		on
 			chip drivers/i2c/hid
 				register "generic.hid" = ""WCOM50C1""
 				register "generic.desc" = ""WCOM Digitizer""
@@ -116,8 +116,8 @@ chip soc/intel/apollolake
 				register "key.wakeup_event_action" = "EV_ACT_DEASSERTED"
 				device generic 0 on end
 			end
-		end	# - I2C 0
-		device pci 16.1 on
+		end
+		device ref i2c1		on
 			chip drivers/i2c/sx9310
 				register "desc" = ""SAR Proximity Sensor""
 				register "irq" = "ACPI_IRQ_LEVEL_LOW(GPIO_214_IRQ)"
@@ -132,8 +132,8 @@ chip soc/intel/apollolake
 				register "proxraw_strength" = "0"
 				device i2c 28 on end
 			end
-		end	# - I2C 1
-		device pci 17.1 on
+		end
+		device ref i2c5		on
 			chip drivers/i2c/da7219
 				register "irq" = "ACPI_IRQ_LEVEL_LOW(GPIO_137_IRQ)"
 				register "btn_cfg" = "50"
@@ -164,8 +164,8 @@ chip soc/intel/apollolake
 				register "property_list[0].integer" = "1"
 				device i2c 1a on end
 			end
-		end	# - I2C 5
-		device pci 17.2 on
+		end
+		device ref i2c6		on
 			chip drivers/i2c/generic
 				register "hid" = ""ELAN0000""
 				register "desc" = ""ELAN Touchpad""
@@ -184,8 +184,8 @@ chip soc/intel/apollolake
 				register "hid_desc_reg_offset" = "0x20"
 				device i2c 0x2c on end
 			end
-		end	# - I2C 6
-		device pci 17.3 on
+		end
+		device ref i2c7		on
 			chip drivers/i2c/generic
 				register "hid" = ""ELAN0001""
 				register "desc" = ""ELAN Touchscreen""
@@ -223,7 +223,7 @@ chip soc/intel/apollolake
 				register "hid_desc_reg_offset" = "0x01"
 				device i2c 40 on end
 			end
-		end	# - I2C 7
+		end
 	end
 
 	# Disable compliance mode
diff --git a/src/mainboard/google/octopus/variants/casta/overridetree.cb b/src/mainboard/google/octopus/variants/casta/overridetree.cb
index 8d3fafd956..a6cac573a3 100644
--- a/src/mainboard/google/octopus/variants/casta/overridetree.cb
+++ b/src/mainboard/google/octopus/variants/casta/overridetree.cb
@@ -83,33 +83,33 @@ chip soc/intel/apollolake
 	}"
 
 	device domain 0 on
-		device pci 15.0 on
+		device ref xhci		on
 			chip drivers/usb/acpi
 				register "desc" = ""Root Hub""
 				register "type" = "UPC_TYPE_HUB"
-				device usb 0.0 on
+				device ref xhci_root_hub on
 					chip drivers/usb/acpi
 						register "desc" = ""Right Type-A Port""
 						register "type" = "UPC_TYPE_A"
 						register "group" = "ACPI_PLD_GROUP(2, 2)"
-						device usb 2.1 on end
+						device ref usb2_port2 on end
 					end
 					chip drivers/usb/acpi
-						device usb 2.3 off end
+						device ref usb2_port4 off end
 					end
 					chip drivers/usb/acpi
 						register "desc" = ""Right Type-A Port""
 						register "type" = "UPC_TYPE_USB3_A"
 						register "group" = "ACPI_PLD_GROUP(2, 2)"
-						device usb 3.1 on end
+						device ref usb3_port2 on end
 					end
 					chip drivers/usb/acpi
-						device usb 3.3 off end
+						device ref usb3_port4 off end
 					end
 				end
 			end
-		end	# - XHCI
-		device pci 17.1 on
+		end
+		device ref i2c5		on
 			chip drivers/i2c/da7219
 				register "irq" = "ACPI_IRQ_LEVEL_LOW(GPIO_137_IRQ)"
 				register "btn_cfg" = "50"
@@ -127,8 +127,8 @@ chip soc/intel/apollolake
 				register "mic_amp_in_sel" = ""diff""
 				device i2c 1a on end
 			end
-		end	# - I2C 5
-		device pci 17.2 on
+		end
+		device ref i2c6		on
 			chip drivers/i2c/generic
 				register "hid" = ""ELAN0000""
 				register "desc" = ""ELAN Touchpad""
@@ -146,7 +146,7 @@ chip soc/intel/apollolake
 				register "hid_desc_reg_offset" = "0xE"
 				device i2c 40 on end
 			end
-		end	# - I2C 6
+		end
 	end
 
 	# Disable compliance mode
diff --git a/src/mainboard/google/octopus/variants/dood/overridetree.cb b/src/mainboard/google/octopus/variants/dood/overridetree.cb
index eb8490da76..8e04bd3060 100644
--- a/src/mainboard/google/octopus/variants/dood/overridetree.cb
+++ b/src/mainboard/google/octopus/variants/dood/overridetree.cb
@@ -80,8 +80,8 @@ chip soc/intel/apollolake
 	}"
 
 	device domain 0 on
-		device pci 16.0 off  end     # - I2C 0
-		device pci 17.1 on
+		device ref i2c0		off end
+		device ref i2c5		on
 			chip drivers/i2c/da7219
 				register "irq" = "ACPI_IRQ_LEVEL_LOW(GPIO_137_IRQ)"
 				register "btn_cfg" = "50"
@@ -99,8 +99,8 @@ chip soc/intel/apollolake
 				register "mic_amp_in_sel" = ""diff""
 				device i2c 1a on end
 			end
-		end	# - I2C 5
-		device pci 17.2 on
+		end
+		device ref i2c6		on
 			chip drivers/i2c/generic
 				register "hid" = ""ELAN0000""
 				register "desc" = ""ELAN Touchpad""
@@ -119,8 +119,8 @@ chip soc/intel/apollolake
 				register "hid_desc_reg_offset" = "0x20"
 				device i2c 0x2c on end
 			end
-		end	# - I2C 6
-		device pci 17.3 on
+		end
+		device ref i2c7		on
 			chip drivers/i2c/generic
 				register "hid" = ""ELAN0001""
 				register "desc" = ""ELAN Touchscreen""
@@ -158,7 +158,7 @@ chip soc/intel/apollolake
 				register "hid_desc_reg_offset" = "0x01"
 				device i2c 40 on end
 			end
-		end	# - I2C 7
+		end
 	end
 
 	# Disable compliance mode
diff --git a/src/mainboard/google/octopus/variants/fleex/overridetree.cb b/src/mainboard/google/octopus/variants/fleex/overridetree.cb
index 3a17abba45..4583787f88 100644
--- a/src/mainboard/google/octopus/variants/fleex/overridetree.cb
+++ b/src/mainboard/google/octopus/variants/fleex/overridetree.cb
@@ -89,7 +89,7 @@ chip soc/intel/apollolake
 	register "disable_xhci_lfps_pm" = "0"
 
 	device domain 0 on
-		device pci 16.0 on
+		device ref i2c0		on
 			chip drivers/i2c/hid
 				register "generic.hid" = ""WCOM50C1""
 				register "generic.desc" = ""WCOM Digitizer""
@@ -102,9 +102,9 @@ chip soc/intel/apollolake
 				register "hid_desc_reg_offset" = "0x1"
 				device i2c 0x9 on end
 			end
-		end	# - I2C 0
-		device pci 16.1 off  end	# - I2C 1
-		device pci 17.1 on
+		end
+		device ref i2c1		off end
+		device ref i2c5		on
 			chip drivers/i2c/da7219
 				register "irq" = "ACPI_IRQ_LEVEL_LOW(GPIO_137_IRQ)"
 				register "btn_cfg" = "50"
@@ -151,8 +151,8 @@ chip soc/intel/apollolake
 				register "hs_bias_sense_disable" = "true"
 				device i2c 48 on end
  			end
-		end	# - I2C 5
-		device pci 17.2 on
+		end
+		device ref i2c6		on
 			chip drivers/i2c/generic
 				register "hid" = ""ELAN0000""
 				register "desc" = ""ELAN Touchpad""
@@ -170,8 +170,8 @@ chip soc/intel/apollolake
 				register "hid_desc_reg_offset" = "0x20"
 				device i2c 2c on end
 			end
-		end	# - I2C 6
-		device pci 17.3 on
+		end
+		device ref i2c7		on
 			chip drivers/i2c/generic
 				register "hid" = ""ELAN0001""
 				register "desc" = ""ELAN Touchscreen""
@@ -210,6 +210,6 @@ chip soc/intel/apollolake
 				register "hid_desc_reg_offset" = "0x01"
 				device i2c 40 on end
 			end
-		end	# - I2C 7
+		end
 	end
 end
diff --git a/src/mainboard/google/octopus/variants/foob/overridetree.cb b/src/mainboard/google/octopus/variants/foob/overridetree.cb
index 154345599c..b7d70935f2 100644
--- a/src/mainboard/google/octopus/variants/foob/overridetree.cb
+++ b/src/mainboard/google/octopus/variants/foob/overridetree.cb
@@ -83,7 +83,7 @@ chip soc/intel/apollolake
 	}"
 
 	device domain 0 on
-		device pci 16.0 on
+		device ref i2c0		on
 			chip drivers/i2c/hid
 				register "generic.hid" = ""WCOM50C1""
 				register "generic.desc" = ""WCOM Digitizer""
@@ -94,8 +94,8 @@ chip soc/intel/apollolake
 				register "hid_desc_reg_offset" = "0x1"
 				device i2c 0x9 on end
 			end
-		end	# - I2C 0
-		device pci 17.1 on
+		end
+		device ref i2c5		on
 			chip drivers/i2c/da7219
 				register "irq" = "ACPI_IRQ_LEVEL_LOW(GPIO_137_IRQ)"
 				register "btn_cfg" = "50"
@@ -113,8 +113,8 @@ chip soc/intel/apollolake
 				register "mic_amp_in_sel" = ""diff""
 				device i2c 1a on end
 			end
-		end	# - I2C 5
-		device pci 17.2 on
+		end
+		device ref i2c6		on
 			chip drivers/i2c/generic
 				register "hid" = ""ELAN0000""
 				register "desc" = ""ELAN Touchpad""
@@ -133,8 +133,8 @@ chip soc/intel/apollolake
 				register "hid_desc_reg_offset" = "0x20"
 				device i2c 0x2c on end
 			end
-		end	# - I2C 6
-		device pci 17.3 on
+		end
+		device ref i2c7		on
 			chip drivers/i2c/hid
 				register "generic.hid" = ""ELAN90FC""
 				register "generic.desc" = ""ELAN Touchscreen""
@@ -159,7 +159,7 @@ chip soc/intel/apollolake
 				register "hid_desc_reg_offset" = "0x20"
 				device i2c 20 on end
 			end
-		end	# - I2C 7
+		end
 	end
 
 	# Disable xHCI compliance mode
diff --git a/src/mainboard/google/octopus/variants/garg/overridetree.cb b/src/mainboard/google/octopus/variants/garg/overridetree.cb
index a653148d10..4084297fe6 100644
--- a/src/mainboard/google/octopus/variants/garg/overridetree.cb
+++ b/src/mainboard/google/octopus/variants/garg/overridetree.cb
@@ -86,7 +86,7 @@ chip soc/intel/apollolake
 	}"
 
 	device domain 0 on
-		device pci 16.0 on
+		device ref i2c0		on
 			chip drivers/i2c/hid
 				register "generic.hid" = ""WCOM50C1""
 				register "generic.desc" = ""WCOM Digitizer""
@@ -109,8 +109,8 @@ chip soc/intel/apollolake
 				register "key.wakeup_event_action" = "EV_ACT_DEASSERTED"
 				device generic 0 on end
 			end
-		end	# - I2C 0
-		device pci 17.1 on
+		end
+		device ref i2c5		on
 			chip drivers/i2c/da7219
 				register "irq" = "ACPI_IRQ_LEVEL_LOW(GPIO_137_IRQ)"
 				register "btn_cfg" = "50"
@@ -141,8 +141,8 @@ chip soc/intel/apollolake
 				register "property_list[0].integer" = "1"
 				device i2c 1a on end
 			end
-		end	# - I2C 5
-		device pci 17.2 on
+		end
+		device ref i2c6		on
 			chip drivers/i2c/generic
 				register "hid" = ""ELAN0000""
 				register "desc" = ""ELAN Touchpad""
@@ -161,8 +161,8 @@ chip soc/intel/apollolake
 				register "hid_desc_reg_offset" = "0x20"
 				device i2c 0x2c on end
 			end
-		end	# - I2C 6
-		device pci 17.3 on
+		end
+		device ref i2c7		on
 			chip drivers/i2c/generic
 				register "hid" = ""ELAN0001""
 				register "desc" = ""ELAN Touchscreen""
@@ -200,7 +200,7 @@ chip soc/intel/apollolake
 				register "hid_desc_reg_offset" = "0x01"
 				device i2c 40 on end
 			end
-		end	# - I2C 7
+		end
 	end
 
 	# Disable compliance mode
diff --git a/src/mainboard/google/octopus/variants/lick/overridetree.cb b/src/mainboard/google/octopus/variants/lick/overridetree.cb
index a89a506dae..a534173a6b 100644
--- a/src/mainboard/google/octopus/variants/lick/overridetree.cb
+++ b/src/mainboard/google/octopus/variants/lick/overridetree.cb
@@ -73,7 +73,7 @@ chip soc/intel/apollolake
 	}"
 
 	device domain 0 on
-		device pci 17.1 on
+		device ref i2c5		on
 			chip drivers/i2c/da7219
 				register "irq" = "ACPI_IRQ_LEVEL_LOW(GPIO_137_IRQ)"
 				register "btn_cfg" = "50"
@@ -91,8 +91,8 @@ chip soc/intel/apollolake
 				register "mic_amp_in_sel" = ""diff""
 				device i2c 1a on end
 			end
-		end	# - I2C 5
-		device pci 17.2 on
+		end
+		device ref i2c6		on
 			chip drivers/i2c/generic
 				register "hid" = ""ELAN0000""
 				register "desc" = ""ELAN Touchpad""
@@ -111,7 +111,7 @@ chip soc/intel/apollolake
 				register "hid_desc_reg_offset" = "0x20"
 				device i2c 0x2c on end
 			end
-		end	# - I2C 6
+		end
 	end
 
 	# Disable compliance mode
diff --git a/src/mainboard/google/octopus/variants/meep/overridetree.cb b/src/mainboard/google/octopus/variants/meep/overridetree.cb
index 9634cf13bb..11038d7e0a 100644
--- a/src/mainboard/google/octopus/variants/meep/overridetree.cb
+++ b/src/mainboard/google/octopus/variants/meep/overridetree.cb
@@ -83,63 +83,63 @@ chip soc/intel/apollolake
 	}"
 
 	device domain 0 on
-		device pci 15.0 on
+		device ref xhci		on
 			chip drivers/usb/acpi
 				register "desc" = ""Root Hub""
 				register "type" = "UPC_TYPE_HUB"
-				device usb 0.0 on
+				device ref xhci_root_hub on
 					chip drivers/usb/acpi
 						register "desc" = ""Right Type-C Port""
 						register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
 						register "group" = "ACPI_PLD_GROUP(2, 1)"
-						device usb 2.0 on end
+						device ref usb2_port1 on end
 					end
 					chip drivers/usb/acpi
 						register "desc" = ""Right Type-A Port""
 						register "type" = "UPC_TYPE_A"
 						register "group" = "ACPI_PLD_GROUP(2, 2)"
-						device usb 2.1 on end
+						device ref usb2_port2 on end
 					end
 					chip drivers/usb/acpi
 						register "desc" = ""Left Type-A Port""
 						register "type" = "UPC_TYPE_A"
 						register "group" = "ACPI_PLD_GROUP(1, 2)"
-						device usb 2.3 on end
+						device ref usb2_port4 on end
 					end
 					chip drivers/usb/acpi
 						register "desc" = ""Left Type-C Port""
 						register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
 						register "group" = "ACPI_PLD_GROUP(1, 1)"
-						device usb 2.4 on end
+						device ref usb2_port5 on end
 					end
 					chip drivers/usb/acpi
 						register "desc" = ""Right Type-C Port""
 						register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
 						register "group" = "ACPI_PLD_GROUP(2, 1)"
-						device usb 3.0 on end
+						device ref usb3_port1 on end
 					end
 					chip drivers/usb/acpi
 						register "desc" = ""Right Type-A Port""
 						register "type" = "UPC_TYPE_USB3_A"
 						register "group" = "ACPI_PLD_GROUP(2, 2)"
-						device usb 3.1 on end
+						device ref usb3_port2 on end
 					end
 					chip drivers/usb/acpi
 						register "desc" = ""Left Type-A Port""
 						register "type" = "UPC_TYPE_USB3_A"
 						register "group" = "ACPI_PLD_GROUP(1, 2)"
-						device usb 3.3 on end
+						device ref usb3_port4 on end
 					end
 					chip drivers/usb/acpi
 						register "desc" = ""Left Type-C Port""
 						register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
 						register "group" = "ACPI_PLD_GROUP(1, 1)"
-						device usb 3.4 on end
+						device ref usb3_port5 on end
 					end
 				end
 			end
-		end	# - XHCI
-		device pci 16.0 on
+		end
+		device ref i2c0		on
 			chip drivers/i2c/hid
 				register "generic.hid" = ""WCOM50C1""
 				register "generic.desc" = ""WCOM Digitizer""
@@ -162,8 +162,8 @@ chip soc/intel/apollolake
 				register "hid_desc_reg_offset" = "0x1"
 				device i2c 0xa on end
 			end
-		end	# - I2C 0
-		device pci 17.1 on
+		end
+		device ref i2c5		on
 			chip drivers/i2c/da7219
 				register "irq" = "ACPI_IRQ_LEVEL_LOW(GPIO_137_IRQ)"
 				register "btn_cfg" = "50"
@@ -194,8 +194,8 @@ chip soc/intel/apollolake
 				register "property_list[0].integer" = "1"
 				device i2c 1a on end
 			end
-		end	# - I2C 5
-		device pci 17.2 on
+		end
+		device ref i2c6		on
 			chip drivers/i2c/generic
 				register "hid" = ""ELAN0000""
 				register "desc" = ""ELAN Touchpad""
@@ -204,8 +204,8 @@ chip soc/intel/apollolake
 				register "detect" = "1"
 				device i2c 15 on end
 			end
-		end	# - I2C 6
-		device pci 17.3 on
+		end
+		device ref i2c7		on
 			chip drivers/i2c/generic
 				register "hid" = ""ELAN0001""
 				register "desc" = ""ELAN Touchscreen""
@@ -244,7 +244,7 @@ chip soc/intel/apollolake
 				register "hid_desc_reg_offset" = "0x01"
 				device i2c 40 on end
 			end
-		end	# - I2C 7
+		end
 	end
 
 	# Disable compliance mode
diff --git a/src/mainboard/google/octopus/variants/phaser/overridetree.cb b/src/mainboard/google/octopus/variants/phaser/overridetree.cb
index 41b654c871..468ae4cb90 100644
--- a/src/mainboard/google/octopus/variants/phaser/overridetree.cb
+++ b/src/mainboard/google/octopus/variants/phaser/overridetree.cb
@@ -83,7 +83,7 @@ chip soc/intel/apollolake
 	}"
 
 	device domain 0 on
-		device pci 16.0 on
+		device ref i2c0		on
 			chip drivers/i2c/hid
 				register "generic.hid" = ""WCOM50C1""
 				register "generic.desc" = ""WCOM Digitizer""
@@ -95,8 +95,8 @@ chip soc/intel/apollolake
 				register "hid_desc_reg_offset" = "0x1"
 				device i2c 0x9 on end
 			end
-		end	# - I2C 0
-		device pci 17.1 on
+		end
+		device ref i2c5		on
 			chip drivers/i2c/da7219
 				register "irq" = "ACPI_IRQ_LEVEL_LOW(GPIO_137_IRQ)"
 				register "btn_cfg" = "50"
@@ -127,8 +127,8 @@ chip soc/intel/apollolake
 				register "property_list[0].integer" = "1"
 				device i2c 1a on end
 			end
-		end	# - I2C 5
-		device pci 17.2 on
+		end
+		device ref i2c6		on
 			chip drivers/i2c/generic
 				register "hid" = ""ELAN0000""
 				register "desc" = ""ELAN Touchpad""
@@ -147,8 +147,8 @@ chip soc/intel/apollolake
 				register "hid_desc_reg_offset" = "0x20"
 				device i2c 0x2c on end
 			end
-		end	# - I2C 6
-		device pci 17.3 on
+		end
+		device ref i2c7		on
 			chip drivers/i2c/generic
 				register "hid" = ""ELAN0001""
 				register "desc" = ""ELAN Touchscreen""
@@ -198,7 +198,7 @@ chip soc/intel/apollolake
 				register "hid_desc_reg_offset" = "0x01"
 				device i2c 40 on end
 			end
-		end	# - I2C 7
+		end
 	end
 
 	# Disable xHCI compliance mode
diff --git a/src/mainboard/google/octopus/variants/yorp/overridetree.cb b/src/mainboard/google/octopus/variants/yorp/overridetree.cb
index 82a0ee4263..85db9f2aae 100644
--- a/src/mainboard/google/octopus/variants/yorp/overridetree.cb
+++ b/src/mainboard/google/octopus/variants/yorp/overridetree.cb
@@ -42,7 +42,7 @@ chip soc/intel/apollolake
 	register "emmc_rx_strobe_cntl" = "0x0a0a"
 
 	device domain 0 on
-		device pci 16.0 on
+		device ref i2c0		on
 			chip drivers/i2c/hid
 				register "generic.hid" = ""WCOM50C1""
 				register "generic.desc" = ""WCOM Digitizer""
@@ -53,8 +53,8 @@ chip soc/intel/apollolake
 				register "hid_desc_reg_offset" = "0x1"
 				device i2c 0x9 on end
 			end
-		end	# - I2C 0
-		device pci 17.1 on
+		end
+		device ref i2c5		on
 			chip drivers/i2c/da7219
 				register "irq" = "ACPI_IRQ_LEVEL_LOW(GPIO_137_IRQ)"
 				register "btn_cfg" = "50"
@@ -72,8 +72,8 @@ chip soc/intel/apollolake
 				register "mic_amp_in_sel" = ""diff""
 				device i2c 1a on end
 			end
-		end	# - I2C 5
-		device pci 17.2 on
+		end
+		device ref i2c6		on
 			chip drivers/i2c/generic
 				register "hid" = ""ELAN0000""
 				register "desc" = ""ELAN Touchpad""
@@ -82,8 +82,8 @@ chip soc/intel/apollolake
 				register "detect" = "1"
 				device i2c 15 on end
 			end
-		end	# - I2C 6
-		device pci 17.3 on
+		end
+		device ref i2c7		on
 			chip drivers/i2c/generic
 				register "hid" = ""ELAN0001""
 				register "desc" = ""ELAN Touchscreen""
@@ -96,6 +96,6 @@ chip soc/intel/apollolake
 				register "has_power_resource" = "true"
 				device i2c 10 on end
 			end
-		end	# - I2C 7
+		end
 	end
 end

From bbc3042bbfb49ca5f01fa7bd3ad591a45bf05c5e Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Mon, 26 Jan 2026 12:10:10 -0600
Subject: [PATCH 3186/3886] mb/google/reef: Use aliases in devicetrees

Convert all PCI device and USB port references in the reef devicetrees
to use aliases from the Apollolake chipset.cb instead of direct device/
function numbers. This improves maintainability by using symbolic
names, and reduces file size by eliminating entries which match those
in the chipset devicetree.

TEST=Build all reef variants

Change-Id: I08f96d2367fa8fc1ac7eb785c0d5cc08e293921b
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90927
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 .../reef/variants/baseboard/devicetree.cb     | 78 ++++++++-----------
 .../google/reef/variants/coral/devicetree.cb  | 78 ++++++++-----------
 .../google/reef/variants/pyro/devicetree.cb   | 77 ++++++++----------
 .../google/reef/variants/sand/devicetree.cb   | 78 ++++++++-----------
 .../google/reef/variants/snappy/devicetree.cb | 78 ++++++++-----------
 5 files changed, 155 insertions(+), 234 deletions(-)

diff --git a/src/mainboard/google/reef/variants/baseboard/devicetree.cb b/src/mainboard/google/reef/variants/baseboard/devicetree.cb
index 5eee33e790..6c3f3f5d1e 100644
--- a/src/mainboard/google/reef/variants/baseboard/devicetree.cb
+++ b/src/mainboard/google/reef/variants/baseboard/devicetree.cb
@@ -118,18 +118,14 @@ chip soc/intel/apollolake
 	register "slp_s3_assertion_width_usecs" = "28000"
 
 	device domain 0 on
-		device pci 00.0 on  end	# - Host Bridge
-		device pci 00.1 on  end	# - DPTF
-		device pci 00.2 off end	# - NPK
-		device pci 02.0 on	# - Gen
+		device ref igd		on
 			register "gfx" = "GMA_DEFAULT_PANEL(0)"
 		end
-		device pci 03.0 off end	# - Iunit
-		device pci 0d.0 on  end	# - P2SB
-		device pci 0d.1 on  end	# - PMC
-		device pci 0d.2 on  end	# - SPI
-		device pci 0d.3 on  end	# - Shared SRAM
-		device pci 0e.0 on	# - Audio
+		device ref p2sb		on end
+		device ref pmc		on end
+		device ref fast_spi	on end
+		device ref sram		on end
+		device ref hda		on
 			chip drivers/generic/max98357a
 				register "hid" = ""MX98357A""
 				register "sdmode_gpio" =  "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_76)"
@@ -137,23 +133,17 @@ chip soc/intel/apollolake
 				device generic 0 on end
 			end
 		end
-		device pci 0f.0 on  end	# - CSE
-		device pci 11.0 off end	# - ISH
-		device pci 12.0 off end	# - SATA
-		device pci 13.0 off end	# - Root Port 2 - PCIe-A 0
-		device pci 13.1 off end	# - Root Port 3 - PCIe-A 1
-		device pci 13.2 off end	# - Root Port 4 - PCIe-A 2
-		device pci 13.3 off end	# - Root Port 5 - PCIe-A 3
-		device pci 14.0 on
+		device ref heci1	on end
+		device ref heci2	on end
+		device ref heci3	on end
+		device ref pcie_rp05	on
 			chip drivers/wifi/generic
 				register "wake" = "GPE0_DW3_00"
 				device pci 00.0 on end
 			end
-		end	# - Root Port 0 - PCIe-B 0 - Wifi
-		device pci 14.1 off end	# - Root Port 1 - PCIe-B 1
-		device pci 15.0 on  end	# - XHCI
-		device pci 15.1 off end # - XDCI
-		device pci 16.0 on	# - I2C 0
+		end
+		device ref xhci		on end
+		device ref i2c0		on
 			chip drivers/i2c/da7219
 				register "irq" = "ACPI_IRQ_LEVEL_LOW(GPIO_116_IRQ)"
 				register "btn_cfg" = "50"
@@ -172,15 +162,15 @@ chip soc/intel/apollolake
 				device i2c 1a on end
 			end
 		end
-		device pci 16.1 on  end	# - I2C 1
-		device pci 16.2 on
+		device ref i2c1		on end
+		device ref i2c2		on
 			chip drivers/i2c/tpm
 				register "hid" = ""GOOG0005""
 				register "irq" = "ACPI_IRQ_EDGE_LOW(GPIO_28_IRQ)"
 				device i2c 50 on end
 			end
-		end	# - I2C 2
-		device pci 16.3 on
+		end
+		device ref i2c3		on
 			chip drivers/i2c/generic
 				register "hid" = ""ELAN0001""
 				register "desc" = ""ELAN Touchscreen""
@@ -193,8 +183,8 @@ chip soc/intel/apollolake
 				register "has_power_resource" = "true"
 				device i2c 10 on end
 			end
-		end	# - I2C 3
-		device pci 17.0 on
+		end
+		device ref i2c4		on
 			chip drivers/i2c/generic
 				register "hid" = ""ELAN0000""
 				register "desc" = ""ELAN Touchpad""
@@ -203,8 +193,8 @@ chip soc/intel/apollolake
 				register "detect" = "1"
 				device i2c 15 on end
 			end
-		end # - I2C 4
-		device pci 17.1 on
+		end
+		device ref i2c5		on
 			chip drivers/i2c/hid
 				register "generic.hid" = ""WCOM50C1""
 				register "generic.desc" = ""WCOM Digitizer""
@@ -212,25 +202,19 @@ chip soc/intel/apollolake
 				register "hid_desc_reg_offset" = "0x1"
 				device i2c 0x9 on end
 			end
-		end	# - I2C 5
-		device pci 17.2 off end	# - I2C 6
-		device pci 17.3 off end	# - I2C 7
-		device pci 18.0 on  end	# - UART 0
-		device pci 18.1 on  end	# - UART 1
-		device pci 18.2 on  end	# - UART 2
-		device pci 18.3 off end	# - UART 3
-		device pci 19.0 on  end	# - SPI 0
-		device pci 19.1 off end	# - SPI 1
-		device pci 19.2 off end	# - SPI 2
-		device pci 1a.0 on  end	# - PWM
-		device pci 1b.0 on  end	# - SDCARD
-		device pci 1c.0 on  end	# - eMMC
-		device pci 1e.0 off end	# - SDIO
-		device pci 1f.0 on	# - LPC
+		end
+		device ref uart0	on end
+		device ref uart1	on end
+		device ref uart2	on end
+		device ref spi0		on end
+		device ref pwm		on end
+		device ref sdcard	on end
+		device ref emmc		on end
+		device ref lpc_espi	on
 			chip ec/google/chromeec
 				device pnp 0c09.0 on end
 			end
 		end
-		device pci 1f.1 on  end	# - SMBUS
+		device ref smbus	on end
 	end
 end
diff --git a/src/mainboard/google/reef/variants/coral/devicetree.cb b/src/mainboard/google/reef/variants/coral/devicetree.cb
index ecfd522560..c7ddc9f33e 100644
--- a/src/mainboard/google/reef/variants/coral/devicetree.cb
+++ b/src/mainboard/google/reef/variants/coral/devicetree.cb
@@ -118,18 +118,14 @@ chip soc/intel/apollolake
 	register "slp_s3_assertion_width_usecs" = "28000"
 
 	device domain 0 on
-		device pci 00.0 on  end	# - Host Bridge
-		device pci 00.1 on  end	# - DPTF
-		device pci 00.2 off end	# - NPK
-		device pci 02.0 on	# - Gen
+		device ref igd		on
 			register "gfx" = "GMA_DEFAULT_PANEL(0)"
 		end
-		device pci 03.0 off end	# - Iunit
-		device pci 0d.0 on  end	# - P2SB
-		device pci 0d.1 on  end	# - PMC
-		device pci 0d.2 on  end	# - SPI
-		device pci 0d.3 on  end	# - Shared SRAM
-		device pci 0e.0 on	# - Audio
+		device ref p2sb		on end
+		device ref pmc		on end
+		device ref fast_spi	on end
+		device ref sram		on end
+		device ref hda		on
 			chip drivers/generic/max98357a
 				register "hid" = ""MX98357A""
 				register "sdmode_gpio" =  "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_76)"
@@ -137,23 +133,17 @@ chip soc/intel/apollolake
 				device generic 0 on end
 			end
 		end
-		device pci 0f.0 on  end	# - CSE
-		device pci 11.0 off end	# - ISH
-		device pci 12.0 off end	# - SATA
-		device pci 13.0 off end	# - Root Port 2 - PCIe-A 0
-		device pci 13.1 off end	# - Root Port 3 - PCIe-A 1
-		device pci 13.2 off end	# - Root Port 4 - PCIe-A 2
-		device pci 13.3 off end	# - Root Port 5 - PCIe-A 3
-		device pci 14.0 on
+		device ref heci1	on end
+		device ref heci2	on end
+		device ref heci3	on end
+		device ref pcie_rp05	on
 			chip drivers/wifi/generic
 				register "wake" = "GPE0_DW3_00"
 				device pci 00.0 on end
 			end
-		end	# - Root Port 0 - PCIe-B 0 - Wifi
-		device pci 14.1 off end	# - Root Port 1 - PCIe-B 1
-		device pci 15.0 on  end	# - XHCI
-		device pci 15.1 off end # - XDCI
-		device pci 16.0 on	# - I2C 0
+		end
+		device ref xhci		on end
+		device ref i2c0		on
 			chip drivers/i2c/da7219
 				register "irq" = "ACPI_IRQ_LEVEL_LOW(GPIO_116_IRQ)"
 				register "btn_cfg" = "50"
@@ -172,15 +162,15 @@ chip soc/intel/apollolake
 				device i2c 1a on end
 			end
 		end
-		device pci 16.1 on  end	# - I2C 1
-		device pci 16.2 on
+		device ref i2c1		on end
+		device ref i2c2		on
 			chip drivers/i2c/tpm
 				register "hid" = ""GOOG0005""
 				register "irq" = "ACPI_IRQ_EDGE_LOW(GPIO_28_IRQ)"
 				device i2c 50 on end
 			end
-		end	# - I2C 2
-		device pci 16.3 on
+		end
+		device ref i2c3		on
 			chip drivers/i2c/generic
 				register "hid" = ""ELAN0001""
 				register "desc" = ""ELAN Touchscreen""
@@ -205,8 +195,8 @@ chip soc/intel/apollolake
 				register "has_power_resource" = "true"
 				device i2c 39 on end
 			end
-		end	# - I2C 3
-		device pci 17.0 on
+		end
+		device ref i2c4		on
 			chip drivers/i2c/generic
 				register "hid" = ""ELAN0000""
 				register "desc" = ""ELAN Touchpad""
@@ -225,8 +215,8 @@ chip soc/intel/apollolake
 				register "hid_desc_reg_offset" = "0x20"
 				device i2c 0x2c on end
 			end
-		end # - I2C 4
-		device pci 17.1 on
+		end
+		device ref i2c5		on
 			chip drivers/i2c/hid
 				register "generic.hid" = ""WCOM50C1""
 				register "generic.desc" = ""WCOM Digitizer""
@@ -234,25 +224,19 @@ chip soc/intel/apollolake
 				register "hid_desc_reg_offset" = "0x1"
 				device i2c 0x9 on end
 			end
-		end	# - I2C 5
-		device pci 17.2 off end	# - I2C 6
-		device pci 17.3 off end	# - I2C 7
-		device pci 18.0 on  end	# - UART 0
-		device pci 18.1 off end	# - UART 1
-		device pci 18.2 off end	# - UART 2
-		device pci 18.3 off end	# - UART 3
-		device pci 19.0 on  end	# - SPI 0
-		device pci 19.1 off end	# - SPI 1
-		device pci 19.2 off end	# - SPI 2
-		device pci 1a.0 on  end	# - PWM
-		device pci 1b.0 on  end	# - SDCARD
-		device pci 1c.0 on  end	# - eMMC
-		device pci 1e.0 off end	# - SDIO
-		device pci 1f.0 on	# - LPC
+		end
+		device ref uart0	on end
+		device ref uart1	off end
+		device ref uart2	off end
+		device ref spi0		on end
+		device ref pwm		on end
+		device ref sdcard	on end
+		device ref emmc		on end
+		device ref lpc_espi	on
 			chip ec/google/chromeec
 				device pnp 0c09.0 on end
 			end
 		end
-		device pci 1f.1 on  end	# - SMBUS
+		device ref smbus	on end
 	end
 end
diff --git a/src/mainboard/google/reef/variants/pyro/devicetree.cb b/src/mainboard/google/reef/variants/pyro/devicetree.cb
index 5385aaaccf..479fc92802 100644
--- a/src/mainboard/google/reef/variants/pyro/devicetree.cb
+++ b/src/mainboard/google/reef/variants/pyro/devicetree.cb
@@ -127,18 +127,14 @@ chip soc/intel/apollolake
 	}"
 
 	device domain 0 on
-		device pci 00.0 on  end	# - Host Bridge
-		device pci 00.1 on  end	# - DPTF
-		device pci 00.2 off end	# - NPK
-		device pci 02.0 on	# - Gen
+		device ref igd		on
 			register "gfx" = "GMA_DEFAULT_PANEL(0)"
 		end
-		device pci 03.0 off end	# - Iunit
-		device pci 0d.0 on  end	# - P2SB
-		device pci 0d.1 on  end	# - PMC
-		device pci 0d.2 on  end	# - SPI
-		device pci 0d.3 on  end	# - Shared SRAM
-		device pci 0e.0 on	# - Audio
+		device ref p2sb		on end
+		device ref pmc		on end
+		device ref fast_spi	on end
+		device ref sram		on end
+		device ref hda		on
 			chip drivers/generic/max98357a
 				register "hid" = ""MX98357A""
 				register "sdmode_gpio" =  "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_76)"
@@ -146,23 +142,17 @@ chip soc/intel/apollolake
 				device generic 0 on end
 			end
 		end
-		device pci 0f.0 on  end	# - CSE
-		device pci 11.0 off end	# - ISH
-		device pci 12.0 off end	# - SATA
-		device pci 13.0 off end	# - Root Port 2 - PCIe-A 0
-		device pci 13.1 off end	# - Root Port 3 - PCIe-A 1
-		device pci 13.2 off end	# - Root Port 4 - PCIe-A 2
-		device pci 13.3 off end	# - Root Port 5 - PCIe-A 3
-		device pci 14.0 on
+		device ref heci1	on end
+		device ref heci2	on end
+		device ref heci3	on end
+		device ref pcie_rp05	on
 			chip drivers/wifi/generic
 				register "wake" = "GPE0_DW3_00"
 				device pci 00.0 on end
 			end
-		end	# - Root Port 0 - PCIe-B 0 - Wifi
-		device pci 14.1 off end	# - Root Port 1 - PCIe-B 1
-		device pci 15.0 on  end	# - XHCI
-		device pci 15.1 off end # - XDCI
-		device pci 16.0 on	# - I2C 0
+		end
+		device ref xhci		on end
+		device ref i2c0		on
 			chip drivers/i2c/da7219
 				register "irq" = "ACPI_IRQ_LEVEL_LOW(GPIO_116_IRQ)"
 				register "btn_cfg" = "50"
@@ -181,15 +171,15 @@ chip soc/intel/apollolake
 				device i2c 1a on end
 			end
 		end
-		device pci 16.1 on  end	# - I2C 1
-		device pci 16.2 on
+		device ref i2c1		on end
+		device ref i2c2		on
 			chip drivers/i2c/tpm
 				register "hid" = ""GOOG0005""
 				register "irq" = "ACPI_IRQ_EDGE_LOW(GPIO_28_IRQ)"
 				device i2c 50 on end
 			end
-		end	# - I2C 2
-		device pci 16.3 on
+		end
+		device ref i2c3		on
 			chip drivers/i2c/hid
 				register "generic.hid" = ""WCOMNTN2""
 				register "generic.desc" = ""WCOM Touchscreen""
@@ -215,8 +205,8 @@ chip soc/intel/apollolake
 				register "has_power_resource" = "true"
 				device i2c 10 on end
 			end
-		end	# - I2C 3
-		device pci 17.0 on
+		end
+		device ref i2c4		on
 			chip drivers/i2c/generic
 				register "hid" = ""ELAN0000""
 				register "desc" = ""ELAN Touchpad""
@@ -225,26 +215,21 @@ chip soc/intel/apollolake
 				register "detect" = "1"
 				device i2c 15 on end
 			end
-		end # - I2C 4
-		device pci 17.1 off end	# - I2C 5
-		device pci 17.2 off end	# - I2C 6
-		device pci 17.3 off end	# - I2C 7
-		device pci 18.0 on  end	# - UART 0
-		device pci 18.1 on  end	# - UART 1
-		device pci 18.2 on  end	# - UART 2
-		device pci 18.3 off end	# - UART 3
-		device pci 19.0 on  end	# - SPI 0
-		device pci 19.1 off end	# - SPI 1
-		device pci 19.2 off end	# - SPI 2
-		device pci 1a.0 on  end	# - PWM
-		device pci 1b.0 on  end	# - SDCARD
-		device pci 1c.0 on  end	# - eMMC
-		device pci 1e.0 off end	# - SDIO
-		device pci 1f.0 on	# - LPC
+		end
+		device ref i2c5		off end
+		device ref i2c6		off end
+		device ref uart0	on end
+		device ref uart1	on end
+		device ref uart2	on end
+		device ref spi0		on end
+		device ref pwm		on end
+		device ref sdcard	on end
+		device ref emmc		on end
+		device ref lpc_espi	on
 			chip ec/google/chromeec
 				device pnp 0c09.0 on end
 			end
 		end
-		device pci 1f.1 on  end	# - SMBUS
+		device ref smbus	on end
 	end
 end
diff --git a/src/mainboard/google/reef/variants/sand/devicetree.cb b/src/mainboard/google/reef/variants/sand/devicetree.cb
index f27d26a5e4..f1e8b1a21a 100644
--- a/src/mainboard/google/reef/variants/sand/devicetree.cb
+++ b/src/mainboard/google/reef/variants/sand/devicetree.cb
@@ -114,18 +114,14 @@ chip soc/intel/apollolake
 	register "slp_s3_assertion_width_usecs" = "28000"
 
 	device domain 0 on
-		device pci 00.0 on  end	# - Host Bridge
-		device pci 00.1 on  end	# - DPTF
-		device pci 00.2 off end	# - NPK
-		device pci 02.0 on	# - Gen
+		device ref igd		on
 			register "gfx" = "GMA_DEFAULT_PANEL(0)"
 		end
-		device pci 03.0 off end	# - Iunit
-		device pci 0d.0 on  end	# - P2SB
-		device pci 0d.1 on  end	# - PMC
-		device pci 0d.2 on  end	# - SPI
-		device pci 0d.3 on  end	# - Shared SRAM
-		device pci 0e.0 on	# - Audio
+		device ref p2sb		on end
+		device ref pmc		on end
+		device ref fast_spi	on end
+		device ref sram		on end
+		device ref hda		on
 			chip drivers/generic/max98357a
 				register "hid" = ""MX98357A""
 				register "sdmode_gpio" =  "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_76)"
@@ -133,23 +129,17 @@ chip soc/intel/apollolake
 				device generic 0 on end
 			end
 		end
-		device pci 0f.0 on  end	# - CSE
-		device pci 11.0 off end	# - ISH
-		device pci 12.0 off end	# - SATA
-		device pci 13.0 off end	# - Root Port 2 - PCIe-A 0
-		device pci 13.1 off end	# - Root Port 3 - PCIe-A 1
-		device pci 13.2 off end	# - Root Port 4 - PCIe-A 2
-		device pci 13.3 off end	# - Root Port 5 - PCIe-A 3
-		device pci 14.0 on
+		device ref heci1	on end
+		device ref heci2	on end
+		device ref heci3	on end
+		device ref pcie_rp05	on
 			chip drivers/wifi/generic
 				register "wake" = "GPE0_DW3_00"
 				device pci 00.0 on end
 			end
-		end	# - Root Port 0 - PCIe-B 0 - Wifi
-		device pci 14.1 off end	# - Root Port 1 - PCIe-B 1
-		device pci 15.0 on  end	# - XHCI
-		device pci 15.1 off end # - XDCI
-		device pci 16.0 on	# - I2C 0
+		end
+		device ref xhci		on end
+		device ref i2c0		on
 			chip drivers/i2c/da7219
 				register "irq" = "ACPI_IRQ_LEVEL_LOW(GPIO_116_IRQ)"
 				register "btn_cfg" = "50"
@@ -168,15 +158,15 @@ chip soc/intel/apollolake
 				device i2c 1a on end
 			end
 		end
-		device pci 16.1 on  end	# - I2C 1
-		device pci 16.2 on
+		device ref i2c1		on end
+		device ref i2c2		on
 			chip drivers/i2c/tpm
 				register "hid" = ""GOOG0005""
 				register "irq" = "ACPI_IRQ_EDGE_LOW(GPIO_28_IRQ)"
 				device i2c 50 on end
 			end
-		end	# - I2C 2
-		device pci 16.3 on
+		end
+		device ref i2c3		on
 			chip drivers/i2c/generic
 				register "hid" = ""RAYD0001""
 				register "desc" = ""Raydium Touchscreen""
@@ -189,8 +179,8 @@ chip soc/intel/apollolake
 				register "has_power_resource" = "true"
 				device i2c 39 on end
 			end
-		end	# - I2C 3
-		device pci 17.0 on
+		end
+		device ref i2c4		on
 			chip drivers/i2c/generic
 				register "hid" = ""ELAN0000""
 				register "desc" = ""ELAN Touchpad""
@@ -199,8 +189,8 @@ chip soc/intel/apollolake
 				register "detect" = "1"
 				device i2c 15 on end
 			end
-		end # - I2C 4
-		device pci 17.1 on
+		end
+		device ref i2c5		on
 			chip drivers/i2c/hid
 				register "generic.hid" = ""WCOM50C1""
 				register "generic.desc" = ""WCOM Digitizer""
@@ -208,25 +198,19 @@ chip soc/intel/apollolake
 				register "hid_desc_reg_offset" = "0x1"
 				device i2c 0x9 on end
 			end
-		end	# - I2C 5
-		device pci 17.2 off end	# - I2C 6
-		device pci 17.3 off end	# - I2C 7
-		device pci 18.0 on  end	# - UART 0
-		device pci 18.1 on  end	# - UART 1
-		device pci 18.2 on  end	# - UART 2
-		device pci 18.3 off end	# - UART 3
-		device pci 19.0 on  end	# - SPI 0
-		device pci 19.1 off end	# - SPI 1
-		device pci 19.2 off end	# - SPI 2
-		device pci 1a.0 on  end	# - PWM
-		device pci 1b.0 on  end	# - SDCARD
-		device pci 1c.0 on  end	# - eMMC
-		device pci 1e.0 off end	# - SDIO
-		device pci 1f.0 on	# - LPC
+		end
+		device ref uart0	on end
+		device ref uart1	on end
+		device ref uart2	on end
+		device ref spi0		on end
+		device ref pwm		on end
+		device ref sdcard	on end
+		device ref emmc		on end
+		device ref lpc_espi	on
 			chip ec/google/chromeec
 				device pnp 0c09.0 on end
 			end
 		end
-		device pci 1f.1 on  end	# - SMBUS
+		device ref smbus	on end
 	end
 end
diff --git a/src/mainboard/google/reef/variants/snappy/devicetree.cb b/src/mainboard/google/reef/variants/snappy/devicetree.cb
index e755776aae..fcc75a37d3 100644
--- a/src/mainboard/google/reef/variants/snappy/devicetree.cb
+++ b/src/mainboard/google/reef/variants/snappy/devicetree.cb
@@ -123,18 +123,14 @@ chip soc/intel/apollolake
 	}"
 
 	device domain 0 on
-		device pci 00.0 on  end	# - Host Bridge
-		device pci 00.1 on  end	# - DPTF
-		device pci 00.2 off end	# - NPK
-		device pci 02.0 on	# - Gen
+		device ref igd		on
 			register "gfx" = "GMA_DEFAULT_PANEL(0)"
 		end
-		device pci 03.0 off end	# - Iunit
-		device pci 0d.0 on  end	# - P2SB
-		device pci 0d.1 on  end	# - PMC
-		device pci 0d.2 on  end	# - SPI
-		device pci 0d.3 on  end	# - Shared SRAM
-		device pci 0e.0 on	# - Audio
+		device ref p2sb		on end
+		device ref pmc		on end
+		device ref fast_spi	on end
+		device ref sram		on end
+		device ref hda		on
 			chip drivers/generic/max98357a
 				register "hid" = ""MX98357A""
 				register "sdmode_gpio" =  "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_76)"
@@ -142,23 +138,17 @@ chip soc/intel/apollolake
 				device generic 0 on end
 			end
 		end
-		device pci 0f.0 on  end	# - CSE
-		device pci 11.0 off end	# - ISH
-		device pci 12.0 off end	# - SATA
-		device pci 13.0 off end	# - Root Port 2 - PCIe-A 0
-		device pci 13.1 off end	# - Root Port 3 - PCIe-A 1
-		device pci 13.2 off end	# - Root Port 4 - PCIe-A 2
-		device pci 13.3 off end	# - Root Port 5 - PCIe-A 3
-		device pci 14.0 on
+		device ref heci1	on end
+		device ref heci2	on end
+		device ref heci3	on end
+		device ref pcie_rp05	on
 			chip drivers/wifi/generic
 				register "wake" = "GPE0_DW3_00"
 				device pci 00.0 on end
 			end
-		end	# - Root Port 0 - PCIe-B 0 - Wifi
-		device pci 14.1 off end	# - Root Port 1 - PCIe-B 1
-		device pci 15.0 on  end	# - XHCI
-		device pci 15.1 off end # - XDCI
-		device pci 16.0 on	# - I2C 0
+		end
+		device ref xhci		on end
+		device ref i2c0		on
 			chip drivers/i2c/da7219
 				register "irq" = "ACPI_IRQ_LEVEL_LOW(GPIO_116_IRQ)"
 				register "btn_cfg" = "50"
@@ -177,15 +167,15 @@ chip soc/intel/apollolake
 				device i2c 1a on end
 			end
 		end
-		device pci 16.1 on  end	# - I2C 1
-		device pci 16.2 on
+		device ref i2c1		on end
+		device ref i2c2		on
 			chip drivers/i2c/tpm
 				register "hid" = ""GOOG0005""
 				register "irq" = "ACPI_IRQ_EDGE_LOW(GPIO_28_IRQ)"
 				device i2c 50 on end
 			end
-		end	# - I2C 2
-		device pci 16.3 on
+		end
+		device ref i2c3		on
 			chip drivers/i2c/generic
 				register "hid" = ""ELAN0001""
 				register "desc" = ""ELAN Touchscreen""
@@ -257,8 +247,8 @@ chip soc/intel/apollolake
 				register "hid_desc_reg_offset" = "0x01"
 				device i2c 40 on end
 			end
-		end	# - I2C 3
-		device pci 17.0 on
+		end
+		device ref i2c4		on
 			chip drivers/i2c/generic
 				register "hid" = ""ELAN0000""
 				register "desc" = ""ELAN Touchpad""
@@ -267,8 +257,8 @@ chip soc/intel/apollolake
 				register "detect" = "1"
 				device i2c 15 on end
 			end
-		end # - I2C 4
-		device pci 17.1 on
+		end
+		device ref i2c5		on
 			chip drivers/i2c/hid
 				register "generic.hid" = ""WCOM50C1""
 				register "generic.desc" = ""WCOM Digitizer""
@@ -276,25 +266,19 @@ chip soc/intel/apollolake
 				register "hid_desc_reg_offset" = "0x1"
 				device i2c 0x9 on end
 			end
-		end	# - I2C 5
-		device pci 17.2 off end	# - I2C 6
-		device pci 17.3 off end	# - I2C 7
-		device pci 18.0 on  end	# - UART 0
-		device pci 18.1 on  end	# - UART 1
-		device pci 18.2 on  end	# - UART 2
-		device pci 18.3 off end	# - UART 3
-		device pci 19.0 on  end	# - SPI 0
-		device pci 19.1 off end	# - SPI 1
-		device pci 19.2 off end	# - SPI 2
-		device pci 1a.0 on  end	# - PWM
-		device pci 1b.0 on  end	# - SDCARD
-		device pci 1c.0 on  end	# - eMMC
-		device pci 1e.0 off end	# - SDIO
-		device pci 1f.0 on	# - LPC
+		end
+		device ref uart0	on end
+		device ref uart1	on end
+		device ref uart2	on end
+		device ref spi0		on end
+		device ref pwm		on end
+		device ref sdcard	on end
+		device ref emmc		on end
+		device ref lpc_espi	on
 			chip ec/google/chromeec
 				device pnp 0c09.0 on end
 			end
 		end
-		device pci 1f.1 on  end	# - SMBUS
+		device ref smbus	on end
 	end
 end

From 2bccc76db6e4a758854eb7b593ef8b6e321b3306 Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Mon, 26 Jan 2026 12:27:04 -0600
Subject: [PATCH 3187/3886] mb/google/reef: Convert to use variant
 overridetrees

Rather than separate devicetrees for each variant, convert to using a
single baseboard devicetree plus overridetrees for each variant.
The Reef uses variant uses the baseboard only (no override).

- Set DEVICETREE to variants/baseboard/devicetree.cb for all variants
- Add OVERRIDE_DEVICETREE for non-reef variants
- Add overridetree.cb for coral, sand, pyro, snappy with only the
  differences from the baseboard
- Remove variant devicetree.cb files

TEST=build all REEF variants

Change-Id: I1e8edc968cb0a733b23007dc2295b7f1189ea4fa
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90928
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/google/reef/Kconfig             |   7 +-
 .../google/reef/variants/coral/devicetree.cb  | 242 ---------------
 .../reef/variants/coral/overridetree.cb       |  52 ++++
 .../google/reef/variants/pyro/devicetree.cb   | 235 ---------------
 .../google/reef/variants/pyro/overridetree.cb |  74 +++++
 .../google/reef/variants/sand/devicetree.cb   | 216 -------------
 .../google/reef/variants/sand/overridetree.cb |  48 +++
 .../google/reef/variants/snappy/devicetree.cb | 284 ------------------
 .../reef/variants/snappy/overridetree.cb      | 113 +++++++
 9 files changed, 290 insertions(+), 981 deletions(-)
 delete mode 100644 src/mainboard/google/reef/variants/coral/devicetree.cb
 create mode 100644 src/mainboard/google/reef/variants/coral/overridetree.cb
 delete mode 100644 src/mainboard/google/reef/variants/pyro/devicetree.cb
 create mode 100644 src/mainboard/google/reef/variants/pyro/overridetree.cb
 delete mode 100644 src/mainboard/google/reef/variants/sand/devicetree.cb
 create mode 100644 src/mainboard/google/reef/variants/sand/overridetree.cb
 delete mode 100644 src/mainboard/google/reef/variants/snappy/devicetree.cb
 create mode 100644 src/mainboard/google/reef/variants/snappy/overridetree.cb

diff --git a/src/mainboard/google/reef/Kconfig b/src/mainboard/google/reef/Kconfig
index 899efeb4b8..06c5575e45 100644
--- a/src/mainboard/google/reef/Kconfig
+++ b/src/mainboard/google/reef/Kconfig
@@ -76,12 +76,11 @@ config VARIANT_DIR
 	default "coral" if BOARD_GOOGLE_CORAL
 
 config DEVICETREE
-	default "variants/coral/devicetree.cb" if BOARD_GOOGLE_CORAL
-	default "variants/pyro/devicetree.cb" if BOARD_GOOGLE_PYRO
-	default "variants/sand/devicetree.cb" if BOARD_GOOGLE_SAND
-	default "variants/snappy/devicetree.cb" if BOARD_GOOGLE_SNAPPY
 	default "variants/baseboard/devicetree.cb"
 
+config OVERRIDE_DEVICETREE
+	default "variants/\$(CONFIG_VARIANT_DIR)/overridetree.cb" if !BOARD_GOOGLE_REEF
+
 config MAINBOARD_PART_NUMBER
 	default "Reef" if BOARD_GOOGLE_REEF
 	default "Pyro" if BOARD_GOOGLE_PYRO
diff --git a/src/mainboard/google/reef/variants/coral/devicetree.cb b/src/mainboard/google/reef/variants/coral/devicetree.cb
deleted file mode 100644
index c7ddc9f33e..0000000000
--- a/src/mainboard/google/reef/variants/coral/devicetree.cb
+++ /dev/null
@@ -1,242 +0,0 @@
-chip soc/intel/apollolake
-
-	register "pcie_rp_clkreq_pin[0]" = "0"    # wifi/bt
-	# Disable unused clkreq of PCIe root ports
-	register "pcie_rp_clkreq_pin[1]" = "CLKREQ_DISABLED"
-	register "pcie_rp_clkreq_pin[2]" = "CLKREQ_DISABLED"
-	register "pcie_rp_clkreq_pin[3]" = "CLKREQ_DISABLED"
-	register "pcie_rp_clkreq_pin[4]" = "CLKREQ_DISABLED"
-	register "pcie_rp_clkreq_pin[5]" = "CLKREQ_DISABLED"
-
-	# GPIO for PERST_0
-	# If the Board has PERST_0 signal, assign the GPIO
-	# If the Board does not have PERST_0, assign GPIO_PRT0_UDEF
-	register "prt0_gpio" = "GPIO_122"
-
-	# GPIO for SD card detect
-	register "sdcard_cd_gpio" = "GPIO_177"
-
-	# EMMC TX DATA Delay 1
-	# Refer to EDS-Vol2-22.3.
-	# [14:8] steps of delay for HS400, each 125ps.
-	# [6:0] steps of delay for SDR104/HS200, each 125ps.
-	register "emmc_tx_data_cntl1" = "0x0C16"
-
-	# EMMC TX DATA Delay 2
-	# Refer to EDS-Vol2-22.3.
-	# [30:24] steps of delay for SDR50, each 125ps.
-	# [22:16] steps of delay for DDR50, each 125ps.
-	# [14:8] steps of delay for SDR25/HS50, each 125ps.
-	# [6:0] steps of delay for SDR12, each 125ps.
-	register "emmc_tx_data_cntl2" = "0x28162828"
-
-	# EMMC RX CMD/DATA Delay 1
-	# Refer to EDS-Vol2-22.3.
-	# [30:24] steps of delay for SDR50, each 125ps.
-	# [22:16] steps of delay for DDR50, each 125ps.
-	# [14:8] steps of delay for SDR25/HS50, each 125ps.
-	# [6:0] steps of delay for SDR12, each 125ps.
-	register "emmc_rx_cmd_data_cntl1" = "0x00181717"
-
-	# EMMC RX CMD/DATA Delay 2
-	# Refer to EDS-Vol2-22.3.
-	# [17:16] stands for Rx Clock before Output Buffer
-	# [14:8] steps of delay for Auto Tuning Mode, each 125ps.
-	# [6:0] steps of delay for HS200, each 125ps.
-	register "emmc_rx_cmd_data_cntl2" = "0x10008"
-
-	# Enable DPTF
-	register "dptf_enable" = "true"
-
-	# PL1 override 12 W: the energy calculation is wrong with the
-	# current VR solution. Experiments show that SoC TDP max (6W) can
-	# be reached when RAPL PL1 is set to 12W.
-	# Set RAPL PL2 to 15W.
-	register "power_limits_config" = "{
-		.tdp_pl1_override = 12,
-		.tdp_pl2_override = 15,
-	}"
-
-	# Enable Audio Clock and Power gating
-	register "hdaudio_clk_gate_enable" = "1"
-	register "hdaudio_pwr_gate_enable" = "1"
-	register "hdaudio_bios_config_lockdown" = "1"
-
-	# Enable lpss s0ix
-	register "lpss_s0ix_enable" = "true"
-
-	# GPE configuration
-	# Note that GPE events called out in ASL code rely on this
-	# route, i.e., if this route changes then the affected GPE
-	# offset bits also need to be changed. This sets the PMC register
-	# GPE_CFG fields.
-	register "gpe0_dw1" = "PMC_GPE_N_31_0"
-	register "gpe0_dw2" = "PMC_GPE_N_63_32"
-	register "gpe0_dw3" = "PMC_GPE_SW_31_0"
-
-	# Intel Common SoC Config
-	#+-------------------+---------------------------+
-	#| Field             |  Value                    |
-	#+-------------------+---------------------------+
-	#| I2C0              | Audio                     |
-	#| I2C2              | TPM                       |
-	#| I2C3              | Touchscreen               |
-	#| I2C4              | Trackpad                  |
-	#| I2C5              | Digitizer                 |
-	#+-------------------+---------------------------+
-	register "common_soc_config" = "{
-		.i2c[0] = {
-			.speed = I2C_SPEED_FAST,
-			.rise_time_ns = 104,
-			.fall_time_ns = 52,
-		},
-		.i2c[2] = {
-			.early_init = 1,
-			.speed = I2C_SPEED_FAST,
-			.rise_time_ns = 57,
-			.fall_time_ns = 28,
-		},
-		.i2c[3] = {
-			.speed = I2C_SPEED_FAST,
-			.rise_time_ns = 76,
-			.fall_time_ns = 164,
-		},
-		.i2c[4] = {
-			.speed = I2C_SPEED_FAST,
-			.rise_time_ns = 114,
-			.fall_time_ns = 164,
-			.data_hold_time_ns = 350,
-		},
-		.i2c[5] = {
-			.speed = I2C_SPEED_FAST,
-			.rise_time_ns = 152,
-			.fall_time_ns = 30,
-		},
-	}"
-
-	# Minimum SLP S3 assertion width 28ms.
-	register "slp_s3_assertion_width_usecs" = "28000"
-
-	device domain 0 on
-		device ref igd		on
-			register "gfx" = "GMA_DEFAULT_PANEL(0)"
-		end
-		device ref p2sb		on end
-		device ref pmc		on end
-		device ref fast_spi	on end
-		device ref sram		on end
-		device ref hda		on
-			chip drivers/generic/max98357a
-				register "hid" = ""MX98357A""
-				register "sdmode_gpio" =  "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_76)"
-				register "sdmode_delay" = "5"
-				device generic 0 on end
-			end
-		end
-		device ref heci1	on end
-		device ref heci2	on end
-		device ref heci3	on end
-		device ref pcie_rp05	on
-			chip drivers/wifi/generic
-				register "wake" = "GPE0_DW3_00"
-				device pci 00.0 on end
-			end
-		end
-		device ref xhci		on end
-		device ref i2c0		on
-			chip drivers/i2c/da7219
-				register "irq" = "ACPI_IRQ_LEVEL_LOW(GPIO_116_IRQ)"
-				register "btn_cfg" = "50"
-				register "mic_det_thr" = "200"
-				register "jack_ins_deb" = "20"
-				register "jack_det_rate" = ""32ms_64ms""
-				register "jack_rem_deb" = "1"
-				register "a_d_btn_thr" = "0xa"
-				register "d_b_btn_thr" = "0x16"
-				register "b_c_btn_thr" = "0x21"
-				register "c_mic_btn_thr" = "0x3e"
-				register "btn_avg" = "4"
-				register "adc_1bit_rpt" = "1"
-				register "micbias_lvl" = "2600"
-				register "mic_amp_in_sel" = ""diff""
-				device i2c 1a on end
-			end
-		end
-		device ref i2c1		on end
-		device ref i2c2		on
-			chip drivers/i2c/tpm
-				register "hid" = ""GOOG0005""
-				register "irq" = "ACPI_IRQ_EDGE_LOW(GPIO_28_IRQ)"
-				device i2c 50 on end
-			end
-		end
-		device ref i2c3		on
-			chip drivers/i2c/generic
-				register "hid" = ""ELAN0001""
-				register "desc" = ""ELAN Touchscreen""
-				register "irq" = "ACPI_IRQ_LEVEL_LOW(GPIO_21_IRQ)"
-				register "detect" = "1"
-				register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_36)"
-				register "reset_delay_ms" = "20"
-				register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_152)"
-				register "enable_delay_ms" = "1"
-				register "has_power_resource" = "true"
-				device i2c 10 on end
-			end
-			chip drivers/i2c/generic
-				register "hid" = ""RAYD0001""
-				register "desc" = ""Raydium Touchscreen""
-				register "irq" = "ACPI_IRQ_LEVEL_LOW(GPIO_21_IRQ)"
-				register "detect" = "1"
-				register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_36)"
-				register "reset_delay_ms" = "1"
-				register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_152)"
-				register "enable_delay_ms" = "50"
-				register "has_power_resource" = "true"
-				device i2c 39 on end
-			end
-		end
-		device ref i2c4		on
-			chip drivers/i2c/generic
-				register "hid" = ""ELAN0000""
-				register "desc" = ""ELAN Touchpad""
-				register "irq" = "ACPI_IRQ_LEVEL_LOW(GPIO_18_IRQ)"
-				register "wake" = "GPE0_DW1_15"
-				register "detect" = "1"
-				device i2c 15 on end
-			end
-			chip drivers/i2c/hid
-				register "generic.hid" = ""SYNA0000""
-				register "generic.cid" = ""ACPI0C50""
-				register "generic.desc" = ""Synaptics Touchpad""
-				register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPIO_18_IRQ)"
-				register "generic.wake" = "GPE0_DW1_15"
-				register "generic.detect" = "1"
-				register "hid_desc_reg_offset" = "0x20"
-				device i2c 0x2c on end
-			end
-		end
-		device ref i2c5		on
-			chip drivers/i2c/hid
-				register "generic.hid" = ""WCOM50C1""
-				register "generic.desc" = ""WCOM Digitizer""
-				register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPIO_13_IRQ)"
-				register "hid_desc_reg_offset" = "0x1"
-				device i2c 0x9 on end
-			end
-		end
-		device ref uart0	on end
-		device ref uart1	off end
-		device ref uart2	off end
-		device ref spi0		on end
-		device ref pwm		on end
-		device ref sdcard	on end
-		device ref emmc		on end
-		device ref lpc_espi	on
-			chip ec/google/chromeec
-				device pnp 0c09.0 on end
-			end
-		end
-		device ref smbus	on end
-	end
-end
diff --git a/src/mainboard/google/reef/variants/coral/overridetree.cb b/src/mainboard/google/reef/variants/coral/overridetree.cb
new file mode 100644
index 0000000000..0df53c0f7a
--- /dev/null
+++ b/src/mainboard/google/reef/variants/coral/overridetree.cb
@@ -0,0 +1,52 @@
+chip soc/intel/apollolake
+	device domain 0 on
+		device ref i2c3		on
+			chip drivers/i2c/generic
+				register "hid" = ""ELAN0001""
+				register "desc" = ""ELAN Touchscreen""
+				register "irq" = "ACPI_IRQ_LEVEL_LOW(GPIO_21_IRQ)"
+				register "detect" = "1"
+				register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_36)"
+				register "reset_delay_ms" = "20"
+				register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_152)"
+				register "enable_delay_ms" = "1"
+				register "has_power_resource" = "true"
+				device i2c 10 on end
+			end
+			chip drivers/i2c/generic
+				register "hid" = ""RAYD0001""
+				register "desc" = ""Raydium Touchscreen""
+				register "irq" = "ACPI_IRQ_LEVEL_LOW(GPIO_21_IRQ)"
+				register "detect" = "1"
+				register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_36)"
+				register "reset_delay_ms" = "1"
+				register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_152)"
+				register "enable_delay_ms" = "50"
+				register "has_power_resource" = "true"
+				device i2c 39 on end
+			end
+		end
+		device ref i2c4		on
+			chip drivers/i2c/generic
+				register "hid" = ""ELAN0000""
+				register "desc" = ""ELAN Touchpad""
+				register "irq" = "ACPI_IRQ_LEVEL_LOW(GPIO_18_IRQ)"
+				register "wake" = "GPE0_DW1_15"
+				register "detect" = "1"
+				device i2c 15 on end
+			end
+			chip drivers/i2c/hid
+				register "generic.hid" = ""SYNA0000""
+				register "generic.cid" = ""ACPI0C50""
+				register "generic.desc" = ""Synaptics Touchpad""
+				register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPIO_18_IRQ)"
+				register "generic.wake" = "GPE0_DW1_15"
+				register "generic.detect" = "1"
+				register "hid_desc_reg_offset" = "0x20"
+				device i2c 0x2c on end
+			end
+		end
+		device ref uart1	off end
+		device ref uart2	off end
+	end
+end
diff --git a/src/mainboard/google/reef/variants/pyro/devicetree.cb b/src/mainboard/google/reef/variants/pyro/devicetree.cb
deleted file mode 100644
index 479fc92802..0000000000
--- a/src/mainboard/google/reef/variants/pyro/devicetree.cb
+++ /dev/null
@@ -1,235 +0,0 @@
-chip soc/intel/apollolake
-
-	register "pcie_rp_clkreq_pin[0]" = "0"    # wifi/bt
-	# Disable unused clkreq of PCIe root ports
-	register "pcie_rp_clkreq_pin[1]" = "CLKREQ_DISABLED"
-	register "pcie_rp_clkreq_pin[2]" = "CLKREQ_DISABLED"
-	register "pcie_rp_clkreq_pin[3]" = "CLKREQ_DISABLED"
-	register "pcie_rp_clkreq_pin[4]" = "CLKREQ_DISABLED"
-	register "pcie_rp_clkreq_pin[5]" = "CLKREQ_DISABLED"
-
-	# GPIO for PERST_0
-	# If the Board has PERST_0 signal, assign the GPIO
-	# If the Board does not have PERST_0, assign GPIO_PRT0_UDEF
-	register "prt0_gpio" = "GPIO_122"
-
-	# GPIO for SD card detect
-	register "sdcard_cd_gpio" = "GPIO_177"
-
-	# EMMC TX DATA Delay 1
-	# Refer to EDS-Vol2-22.3.
-	# [14:8] steps of delay for HS400, each 125ps.
-	# [6:0] steps of delay for SDR104/HS200, each 125ps.
-	register "emmc_tx_data_cntl1" = "0x0C16"
-
-	# EMMC TX DATA Delay 2
-	# Refer to EDS-Vol2-22.3.
-	# [30:24] steps of delay for SDR50, each 125ps.
-	# [22:16] steps of delay for DDR50, each 125ps.
-	# [14:8] steps of delay for SDR25/HS50, each 125ps.
-	# [6:0] steps of delay for SDR12, each 125ps.
-	register "emmc_tx_data_cntl2" = "0x28162828"
-
-	# EMMC RX CMD/DATA Delay 1
-	# Refer to EDS-Vol2-22.3.
-	# [30:24] steps of delay for SDR50, each 125ps.
-	# [22:16] steps of delay for DDR50, each 125ps.
-	# [14:8] steps of delay for SDR25/HS50, each 125ps.
-	# [6:0] steps of delay for SDR12, each 125ps.
-	register "emmc_rx_cmd_data_cntl1" = "0x00181717"
-
-	# EMMC RX CMD/DATA Delay 2
-	# Refer to EDS-Vol2-22.3.
-	# [17:16] stands for Rx Clock before Output Buffer
-	# [14:8] steps of delay for Auto Tuning Mode, each 125ps.
-	# [6:0] steps of delay for HS200, each 125ps.
-	register "emmc_rx_cmd_data_cntl2" = "0x10008"
-
-	# Enable DPTF
-	register "dptf_enable" = "true"
-
-	# PL1 override 12 W: the energy calculation is wrong with the
-	# current VR solution. Experiments show that SoC TDP max (6W) can
-	# be reached when RAPL PL1 is set to 12W.
-	# Set RAPL PL2 to 15W.
-	register "power_limits_config" = "{
-		.tdp_pl1_override = 12,
-		.tdp_pl2_override = 15,
-	}"
-
-	# Enable Audio Clock and Power gating
-	register "hdaudio_clk_gate_enable" = "1"
-	register "hdaudio_pwr_gate_enable" = "1"
-	register "hdaudio_bios_config_lockdown" = "1"
-
-	# Enable lpss s0ix
-	register "lpss_s0ix_enable" = "true"
-
-	# GPE configuration
-	# Note that GPE events called out in ASL code rely on this
-	# route, i.e., if this route changes then the affected GPE
-	# offset bits also need to be changed. This sets the PMC register
-	# GPE_CFG fields.
-	register "gpe0_dw1" = "PMC_GPE_N_31_0"
-	register "gpe0_dw2" = "PMC_GPE_N_63_32"
-	register "gpe0_dw3" = "PMC_GPE_SW_31_0"
-
-	# Intel Common SoC Config
-	#+-------------------+---------------------------+
-	#| Field             |  Value                    |
-	#+-------------------+---------------------------+
-	#| I2C0              | Audio                     |
-	#| I2C2              | TPM                       |
-	#| I2C3              | Touchscreen               |
-	#| I2C4              | Trackpad                  |
-	#+-------------------+---------------------------+
-	register "common_soc_config" = "{
-		.i2c[0] = {
-			.speed = I2C_SPEED_FAST,
-			.rise_time_ns = 104,
-			.fall_time_ns = 52,
-		},
-		.i2c[2] = {
-			.early_init = 1,
-			.speed = I2C_SPEED_FAST,
-			.rise_time_ns = 50,
-			.fall_time_ns = 23,
-		},
-		.i2c[3] = {
-			.speed = I2C_SPEED_FAST,
-			.rise_time_ns = 76,
-			.fall_time_ns = 164,
-		},
-		.i2c[4] = {
-			.speed = I2C_SPEED_FAST,
-			.rise_time_ns = 90,
-			.fall_time_ns = 164,
-		},
-	}"
-
-	# Minimum SLP S3 assertion width 28ms.
-	register "slp_s3_assertion_width_usecs" = "28000"
-
-	# Override USB2 PER PORT register (PORT 0)
-	register "usb2eye[0]" = "{
-		.Usb20PerPortPeTxiSet = 7,
-		.Usb20PerPortTxiSet = 1,
-		.Usb20IUsbTxEmphasisEn = 3,
-		.Usb20PerPortTxPeHalf = 0,
-	}"
-
-	# Override USB2 PER PORT register (PORT 1)
-	register "usb2eye[1]" = "{
-		.Usb20PerPortPeTxiSet = 7,
-		.Usb20PerPortTxiSet = 2,
-		.Usb20IUsbTxEmphasisEn = 3,
-		.Usb20PerPortTxPeHalf = 0,
-	}"
-
-	device domain 0 on
-		device ref igd		on
-			register "gfx" = "GMA_DEFAULT_PANEL(0)"
-		end
-		device ref p2sb		on end
-		device ref pmc		on end
-		device ref fast_spi	on end
-		device ref sram		on end
-		device ref hda		on
-			chip drivers/generic/max98357a
-				register "hid" = ""MX98357A""
-				register "sdmode_gpio" =  "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_76)"
-				register "sdmode_delay" = "5"
-				device generic 0 on end
-			end
-		end
-		device ref heci1	on end
-		device ref heci2	on end
-		device ref heci3	on end
-		device ref pcie_rp05	on
-			chip drivers/wifi/generic
-				register "wake" = "GPE0_DW3_00"
-				device pci 00.0 on end
-			end
-		end
-		device ref xhci		on end
-		device ref i2c0		on
-			chip drivers/i2c/da7219
-				register "irq" = "ACPI_IRQ_LEVEL_LOW(GPIO_116_IRQ)"
-				register "btn_cfg" = "50"
-				register "mic_det_thr" = "200"
-				register "jack_ins_deb" = "20"
-				register "jack_det_rate" = ""32ms_64ms""
-				register "jack_rem_deb" = "1"
-				register "a_d_btn_thr" = "0xa"
-				register "d_b_btn_thr" = "0x16"
-				register "b_c_btn_thr" = "0x21"
-				register "c_mic_btn_thr" = "0x3e"
-				register "btn_avg" = "4"
-				register "adc_1bit_rpt" = "1"
-				register "micbias_lvl" = "2600"
-				register "mic_amp_in_sel" = ""diff""
-				device i2c 1a on end
-			end
-		end
-		device ref i2c1		on end
-		device ref i2c2		on
-			chip drivers/i2c/tpm
-				register "hid" = ""GOOG0005""
-				register "irq" = "ACPI_IRQ_EDGE_LOW(GPIO_28_IRQ)"
-				device i2c 50 on end
-			end
-		end
-		device ref i2c3		on
-			chip drivers/i2c/hid
-				register "generic.hid" = ""WCOMNTN2""
-				register "generic.desc" = ""WCOM Touchscreen""
-				register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPIO_21_IRQ)"
-				register "generic.detect" = "1"
-				register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_36)"
-				register "generic.reset_delay_ms" = "20"
-				register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_152)"
-				register "generic.enable_delay_ms" = "1"
-				register "generic.has_power_resource" = "1"
-				register "hid_desc_reg_offset" = "0x1"
-				device i2c 0xA on end
-			end
-			chip drivers/i2c/generic
-				register "hid" = ""ELAN0001""
-				register "desc" = ""ELAN Touchscreen""
-				register "irq" = "ACPI_IRQ_LEVEL_LOW(GPIO_21_IRQ)"
-				register "detect" = "1"
-				register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_36)"
-				register "reset_delay_ms" = "20"
-				register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_152)"
-				register "enable_delay_ms" = "1"
-				register "has_power_resource" = "true"
-				device i2c 10 on end
-			end
-		end
-		device ref i2c4		on
-			chip drivers/i2c/generic
-				register "hid" = ""ELAN0000""
-				register "desc" = ""ELAN Touchpad""
-				register "irq" = "ACPI_IRQ_LEVEL_LOW(GPIO_18_IRQ)"
-				register "wake" = "GPE0_DW1_15"
-				register "detect" = "1"
-				device i2c 15 on end
-			end
-		end
-		device ref i2c5		off end
-		device ref i2c6		off end
-		device ref uart0	on end
-		device ref uart1	on end
-		device ref uart2	on end
-		device ref spi0		on end
-		device ref pwm		on end
-		device ref sdcard	on end
-		device ref emmc		on end
-		device ref lpc_espi	on
-			chip ec/google/chromeec
-				device pnp 0c09.0 on end
-			end
-		end
-		device ref smbus	on end
-	end
-end
diff --git a/src/mainboard/google/reef/variants/pyro/overridetree.cb b/src/mainboard/google/reef/variants/pyro/overridetree.cb
new file mode 100644
index 0000000000..f669639695
--- /dev/null
+++ b/src/mainboard/google/reef/variants/pyro/overridetree.cb
@@ -0,0 +1,74 @@
+chip soc/intel/apollolake
+	# Intel Common SoC Config (no i2c[5])
+	register "common_soc_config" = "{
+		.i2c[0] = {
+			.speed = I2C_SPEED_FAST,
+			.rise_time_ns = 104,
+			.fall_time_ns = 52,
+		},
+		.i2c[2] = {
+			.early_init = 1,
+			.speed = I2C_SPEED_FAST,
+			.rise_time_ns = 50,
+			.fall_time_ns = 23,
+		},
+		.i2c[3] = {
+			.speed = I2C_SPEED_FAST,
+			.rise_time_ns = 76,
+			.fall_time_ns = 164,
+		},
+		.i2c[4] = {
+			.speed = I2C_SPEED_FAST,
+			.rise_time_ns = 90,
+			.fall_time_ns = 164,
+		},
+	}"
+
+	# Override USB2 PER PORT register (PORT 0)
+	register "usb2eye[0]" = "{
+		.Usb20PerPortPeTxiSet = 7,
+		.Usb20PerPortTxiSet = 1,
+		.Usb20IUsbTxEmphasisEn = 3,
+		.Usb20PerPortTxPeHalf = 0,
+	}"
+
+	# Override USB2 PER PORT register (PORT 1)
+	register "usb2eye[1]" = "{
+		.Usb20PerPortPeTxiSet = 7,
+		.Usb20PerPortTxiSet = 2,
+		.Usb20IUsbTxEmphasisEn = 3,
+		.Usb20PerPortTxPeHalf = 0,
+	}"
+
+	device domain 0 on
+		device ref i2c3		on
+			chip drivers/i2c/hid
+				register "generic.hid" = ""WCOMNTN2""
+				register "generic.desc" = ""WCOM Touchscreen""
+				register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPIO_21_IRQ)"
+				register "generic.detect" = "1"
+				register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_36)"
+				register "generic.reset_delay_ms" = "20"
+				register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_152)"
+				register "generic.enable_delay_ms" = "1"
+				register "generic.has_power_resource" = "1"
+				register "hid_desc_reg_offset" = "0x1"
+				device i2c 0xA on end
+			end
+			chip drivers/i2c/generic
+				register "hid" = ""ELAN0001""
+				register "desc" = ""ELAN Touchscreen""
+				register "irq" = "ACPI_IRQ_LEVEL_LOW(GPIO_21_IRQ)"
+				register "detect" = "1"
+				register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_36)"
+				register "reset_delay_ms" = "20"
+				register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_152)"
+				register "enable_delay_ms" = "1"
+				register "has_power_resource" = "true"
+				device i2c 10 on end
+			end
+		end
+		device ref i2c5		off end
+		device ref i2c6		off end
+	end
+end
diff --git a/src/mainboard/google/reef/variants/sand/devicetree.cb b/src/mainboard/google/reef/variants/sand/devicetree.cb
deleted file mode 100644
index f1e8b1a21a..0000000000
--- a/src/mainboard/google/reef/variants/sand/devicetree.cb
+++ /dev/null
@@ -1,216 +0,0 @@
-chip soc/intel/apollolake
-
-	register "pcie_rp_clkreq_pin[0]" = "0"    # wifi/bt
-	# Disable unused clkreq of PCIe root ports
-	register "pcie_rp_clkreq_pin[1]" = "CLKREQ_DISABLED"
-	register "pcie_rp_clkreq_pin[2]" = "CLKREQ_DISABLED"
-	register "pcie_rp_clkreq_pin[3]" = "CLKREQ_DISABLED"
-	register "pcie_rp_clkreq_pin[4]" = "CLKREQ_DISABLED"
-	register "pcie_rp_clkreq_pin[5]" = "CLKREQ_DISABLED"
-
-	# GPIO for PERST_0
-	# If the Board has PERST_0 signal, assign the GPIO
-	# If the Board does not have PERST_0, assign GPIO_PRT0_UDEF
-	register "prt0_gpio" = "GPIO_122"
-
-	# EMMC TX DATA Delay 1
-	# Refer to EDS-Vol2-22.3.
-	# [14:8] steps of delay for HS400, each 125ps.
-	# [6:0] steps of delay for SDR104/HS200, each 125ps.
-	register "emmc_tx_data_cntl1" = "0x0C16"
-
-	# EMMC TX DATA Delay 2
-	# Refer to EDS-Vol2-22.3.
-	# [30:24] steps of delay for SDR50, each 125ps.
-	# [22:16] steps of delay for DDR50, each 125ps.
-	# [14:8] steps of delay for SDR25/HS50, each 125ps.
-	# [6:0] steps of delay for SDR12, each 125ps.
-	register "emmc_tx_data_cntl2" = "0x28162828"
-
-	# EMMC RX CMD/DATA Delay 1
-	# Refer to EDS-Vol2-22.3.
-	# [30:24] steps of delay for SDR50, each 125ps.
-	# [22:16] steps of delay for DDR50, each 125ps.
-	# [14:8] steps of delay for SDR25/HS50, each 125ps.
-	# [6:0] steps of delay for SDR12, each 125ps.
-	register "emmc_rx_cmd_data_cntl1" = "0x00181717"
-
-	# EMMC RX CMD/DATA Delay 2
-	# Refer to EDS-Vol2-22.3.
-	# [17:16] stands for Rx Clock before Output Buffer
-	# [14:8] steps of delay for Auto Tuning Mode, each 125ps.
-	# [6:0] steps of delay for HS200, each 125ps.
-	register "emmc_rx_cmd_data_cntl2" = "0x10008"
-
-	# Enable DPTF
-	register "dptf_enable" = "true"
-
-	# PL1 override 12 W: the energy calculation is wrong with the
-	# current VR solution. Experiments show that SoC TDP max (6W) can
-	# be reached when RAPL PL1 is set to 12W.
-	# Set RAPL PL2 to 15W.
-	register "power_limits_config" = "{
-		.tdp_pl1_override = 12,
-		.tdp_pl2_override = 15,
-	}"
-
-	# Enable Audio Clock and Power gating
-	register "hdaudio_clk_gate_enable" = "1"
-	register "hdaudio_pwr_gate_enable" = "1"
-	register "hdaudio_bios_config_lockdown" = "1"
-
-	# Enable lpss s0ix
-	register "lpss_s0ix_enable" = "true"
-
-	# GPE configuration
-	# Note that GPE events called out in ASL code rely on this
-	# route, i.e., if this route changes then the affected GPE
-	# offset bits also need to be changed. This sets the PMC register
-	# GPE_CFG fields.
-	register "gpe0_dw1" = "PMC_GPE_N_31_0"
-	register "gpe0_dw2" = "PMC_GPE_N_63_32"
-	register "gpe0_dw3" = "PMC_GPE_SW_31_0"
-
-	# Intel Common SoC Config
-	#+-------------------+---------------------------+
-	#| Field             |  Value                    |
-	#+-------------------+---------------------------+
-	#| I2C0              | Audio                     |
-	#| I2C2              | TPM                       |
-	#| I2C3              | Touchscreen               |
-	#| I2C4              | Trackpad                  |
-	#| I2C5              | Digitizer                 |
-	#+-------------------+---------------------------+
-	register "common_soc_config" = "{
-		.i2c[0] = {
-			.speed = I2C_SPEED_FAST,
-			.rise_time_ns = 104,
-			.fall_time_ns = 52,
-		},
-		.i2c[2] = {
-			.early_init = 1,
-			.speed = I2C_SPEED_FAST,
-			.rise_time_ns = 57,
-			.fall_time_ns = 28,
-		},
-		.i2c[3] = {
-			.speed = I2C_SPEED_FAST,
-			.rise_time_ns = 76,
-			.fall_time_ns = 164,
-		},
-		.i2c[4] = {
-			.speed = I2C_SPEED_FAST,
-			.rise_time_ns = 114,
-			.fall_time_ns = 164,
-		},
-		.i2c[5] = {
-			.speed = I2C_SPEED_FAST,
-			.rise_time_ns = 152,
-			.fall_time_ns = 30,
-		},
-	}"
-
-	# Minimum SLP S3 assertion width 28ms.
-	register "slp_s3_assertion_width_usecs" = "28000"
-
-	device domain 0 on
-		device ref igd		on
-			register "gfx" = "GMA_DEFAULT_PANEL(0)"
-		end
-		device ref p2sb		on end
-		device ref pmc		on end
-		device ref fast_spi	on end
-		device ref sram		on end
-		device ref hda		on
-			chip drivers/generic/max98357a
-				register "hid" = ""MX98357A""
-				register "sdmode_gpio" =  "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_76)"
-				register "sdmode_delay" = "5"
-				device generic 0 on end
-			end
-		end
-		device ref heci1	on end
-		device ref heci2	on end
-		device ref heci3	on end
-		device ref pcie_rp05	on
-			chip drivers/wifi/generic
-				register "wake" = "GPE0_DW3_00"
-				device pci 00.0 on end
-			end
-		end
-		device ref xhci		on end
-		device ref i2c0		on
-			chip drivers/i2c/da7219
-				register "irq" = "ACPI_IRQ_LEVEL_LOW(GPIO_116_IRQ)"
-				register "btn_cfg" = "50"
-				register "mic_det_thr" = "200"
-				register "jack_ins_deb" = "20"
-				register "jack_det_rate" = ""32ms_64ms""
-				register "jack_rem_deb" = "1"
-				register "a_d_btn_thr" = "0xa"
-				register "d_b_btn_thr" = "0x16"
-				register "b_c_btn_thr" = "0x21"
-				register "c_mic_btn_thr" = "0x3e"
-				register "btn_avg" = "4"
-				register "adc_1bit_rpt" = "1"
-				register "micbias_lvl" = "2600"
-				register "mic_amp_in_sel" = ""diff""
-				device i2c 1a on end
-			end
-		end
-		device ref i2c1		on end
-		device ref i2c2		on
-			chip drivers/i2c/tpm
-				register "hid" = ""GOOG0005""
-				register "irq" = "ACPI_IRQ_EDGE_LOW(GPIO_28_IRQ)"
-				device i2c 50 on end
-			end
-		end
-		device ref i2c3		on
-			chip drivers/i2c/generic
-				register "hid" = ""RAYD0001""
-				register "desc" = ""Raydium Touchscreen""
-				register "irq" = "ACPI_IRQ_LEVEL_LOW(GPIO_21_IRQ)"
-				register "detect" = "1"
-				register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_36)"
-				register "reset_delay_ms" = "20"
-				register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_152)"
-				register "enable_delay_ms" = "1"
-				register "has_power_resource" = "true"
-				device i2c 39 on end
-			end
-		end
-		device ref i2c4		on
-			chip drivers/i2c/generic
-				register "hid" = ""ELAN0000""
-				register "desc" = ""ELAN Touchpad""
-				register "irq" = "ACPI_IRQ_LEVEL_LOW(GPIO_18_IRQ)"
-				register "wake" = "GPE0_DW1_15"
-				register "detect" = "1"
-				device i2c 15 on end
-			end
-		end
-		device ref i2c5		on
-			chip drivers/i2c/hid
-				register "generic.hid" = ""WCOM50C1""
-				register "generic.desc" = ""WCOM Digitizer""
-				register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPIO_13_IRQ)"
-				register "hid_desc_reg_offset" = "0x1"
-				device i2c 0x9 on end
-			end
-		end
-		device ref uart0	on end
-		device ref uart1	on end
-		device ref uart2	on end
-		device ref spi0		on end
-		device ref pwm		on end
-		device ref sdcard	on end
-		device ref emmc		on end
-		device ref lpc_espi	on
-			chip ec/google/chromeec
-				device pnp 0c09.0 on end
-			end
-		end
-		device ref smbus	on end
-	end
-end
diff --git a/src/mainboard/google/reef/variants/sand/overridetree.cb b/src/mainboard/google/reef/variants/sand/overridetree.cb
new file mode 100644
index 0000000000..7571a772bc
--- /dev/null
+++ b/src/mainboard/google/reef/variants/sand/overridetree.cb
@@ -0,0 +1,48 @@
+chip soc/intel/apollolake
+	# Intel Common SoC Config (i2c[4] without data_hold_time_ns)
+	register "common_soc_config" = "{
+		.i2c[0] = {
+			.speed = I2C_SPEED_FAST,
+			.rise_time_ns = 104,
+			.fall_time_ns = 52,
+		},
+		.i2c[2] = {
+			.early_init = 1,
+			.speed = I2C_SPEED_FAST,
+			.rise_time_ns = 57,
+			.fall_time_ns = 28,
+		},
+		.i2c[3] = {
+			.speed = I2C_SPEED_FAST,
+			.rise_time_ns = 76,
+			.fall_time_ns = 164,
+		},
+		.i2c[4] = {
+			.speed = I2C_SPEED_FAST,
+			.rise_time_ns = 114,
+			.fall_time_ns = 164,
+		},
+		.i2c[5] = {
+			.speed = I2C_SPEED_FAST,
+			.rise_time_ns = 152,
+			.fall_time_ns = 30,
+		},
+	}"
+
+	device domain 0 on
+		device ref i2c3		on
+			chip drivers/i2c/generic
+				register "hid" = ""RAYD0001""
+				register "desc" = ""Raydium Touchscreen""
+				register "irq" = "ACPI_IRQ_LEVEL_LOW(GPIO_21_IRQ)"
+				register "detect" = "1"
+				register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_36)"
+				register "reset_delay_ms" = "20"
+				register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_152)"
+				register "enable_delay_ms" = "1"
+				register "has_power_resource" = "true"
+				device i2c 39 on end
+			end
+		end
+	end
+end
diff --git a/src/mainboard/google/reef/variants/snappy/devicetree.cb b/src/mainboard/google/reef/variants/snappy/devicetree.cb
deleted file mode 100644
index fcc75a37d3..0000000000
--- a/src/mainboard/google/reef/variants/snappy/devicetree.cb
+++ /dev/null
@@ -1,284 +0,0 @@
-chip soc/intel/apollolake
-
-	register "pcie_rp_clkreq_pin[0]" = "0"    # wifi/bt
-	# Disable unused clkreq of PCIe root ports
-	register "pcie_rp_clkreq_pin[1]" = "CLKREQ_DISABLED"
-	register "pcie_rp_clkreq_pin[2]" = "CLKREQ_DISABLED"
-	register "pcie_rp_clkreq_pin[3]" = "CLKREQ_DISABLED"
-	register "pcie_rp_clkreq_pin[4]" = "CLKREQ_DISABLED"
-	register "pcie_rp_clkreq_pin[5]" = "CLKREQ_DISABLED"
-
-	# GPIO for PERST_0
-	# If the Board has PERST_0 signal, assign the GPIO
-	# If the Board does not have PERST_0, assign GPIO_PRT0_UDEF
-	register "prt0_gpio" = "GPIO_122"
-
-	# GPIO for SD card detect
-	register "sdcard_cd_gpio" = "GPIO_177"
-
-	# EMMC TX DATA Delay 1
-	# Refer to EDS-Vol2-22.3.
-	# [14:8] steps of delay for HS400, each 125ps.
-	# [6:0] steps of delay for SDR104/HS200, each 125ps.
-	register "emmc_tx_data_cntl1" = "0x0C16"
-
-	# EMMC TX DATA Delay 2
-	# Refer to EDS-Vol2-22.3.
-	# [30:24] steps of delay for SDR50, each 125ps.
-	# [22:16] steps of delay for DDR50, each 125ps.
-	# [14:8] steps of delay for SDR25/HS50, each 125ps.
-	# [6:0] steps of delay for SDR12, each 125ps.
-	register "emmc_tx_data_cntl2" = "0x28162828"
-
-	# EMMC RX CMD/DATA Delay 1
-	# Refer to EDS-Vol2-22.3.
-	# [30:24] steps of delay for SDR50, each 125ps.
-	# [22:16] steps of delay for DDR50, each 125ps.
-	# [14:8] steps of delay for SDR25/HS50, each 125ps.
-	# [6:0] steps of delay for SDR12, each 125ps.
-	register "emmc_rx_cmd_data_cntl1" = "0x00181717"
-
-	# EMMC RX CMD/DATA Delay 2
-	# Refer to EDS-Vol2-22.3.
-	# [17:16] stands for Rx Clock before Output Buffer
-	# [14:8] steps of delay for Auto Tuning Mode, each 125ps.
-	# [6:0] steps of delay for HS200, each 125ps.
-	register "emmc_rx_cmd_data_cntl2" = "0x10008"
-
-	# Enable DPTF
-	register "dptf_enable" = "true"
-
-	# PL1 override 12 W: the energy calculation is wrong with the
-	# current VR solution. Experiments show that SoC TDP max (6W) can
-	# be reached when RAPL PL1 is set to 12W.
-	# Set RAPL PL2 to 15W.
-	register "power_limits_config" = "{
-		.tdp_pl1_override = 12,
-		.tdp_pl2_override = 15,
-	}"
-
-	# Enable Audio Clock and Power gating
-	register "hdaudio_clk_gate_enable" = "1"
-	register "hdaudio_pwr_gate_enable" = "1"
-	register "hdaudio_bios_config_lockdown" = "1"
-
-	# Enable lpss s0ix
-	register "lpss_s0ix_enable" = "true"
-
-	# GPE configuration
-	# Note that GPE events called out in ASL code rely on this
-	# route, i.e., if this route changes then the affected GPE
-	# offset bits also need to be changed. This sets the PMC register
-	# GPE_CFG fields.
-	register "gpe0_dw1" = "PMC_GPE_N_31_0"
-	register "gpe0_dw2" = "PMC_GPE_N_63_32"
-	register "gpe0_dw3" = "PMC_GPE_SW_31_0"
-
-	# Intel Common SoC Config
-	#+-------------------+---------------------------+
-	#| Field             |  Value                    |
-	#+-------------------+---------------------------+
-	#| I2C0              | Audio                     |
-	#| I2C2              | TPM                       |
-	#| I2C3              | Touchscreen               |
-	#| I2C4              | Trackpad                  |
-	#| I2C5              | Digitizer                 |
-	#+-------------------+---------------------------+
-	register "common_soc_config" = "{
-		.i2c[0] = {
-			.speed = I2C_SPEED_FAST,
-			.rise_time_ns = 44,
-			.fall_time_ns = 22,
-		},
-		.i2c[2] = {
-			.early_init = 1,
-			.speed = I2C_SPEED_FAST,
-			.rise_time_ns = 40,
-			.fall_time_ns = 20,
-		},
-		.i2c[3] = {
-			.speed = I2C_SPEED_FAST,
-			.rise_time_ns = 70,
-			.fall_time_ns = 164,
-		},
-		.i2c[4] = {
-			.speed = I2C_SPEED_FAST,
-			.rise_time_ns = 20,
-			.fall_time_ns = 164,
-		},
-		.i2c[5] = {
-			.speed = I2C_SPEED_FAST,
-			.rise_time_ns = 152,
-			.fall_time_ns = 30,
-		},
-	}"
-
-	# Minimum SLP S3 assertion width 28ms.
-	register "slp_s3_assertion_width_usecs" = "28000"
-
-	# Override USB2 PER PORT register (PORT 1)
-	register "usb2eye[1]" = "{
-		.Usb20PerPortPeTxiSet = 7,
-		.Usb20PerPortTxiSet = 0,
-	}"
-
-	device domain 0 on
-		device ref igd		on
-			register "gfx" = "GMA_DEFAULT_PANEL(0)"
-		end
-		device ref p2sb		on end
-		device ref pmc		on end
-		device ref fast_spi	on end
-		device ref sram		on end
-		device ref hda		on
-			chip drivers/generic/max98357a
-				register "hid" = ""MX98357A""
-				register "sdmode_gpio" =  "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_76)"
-				register "sdmode_delay" = "5"
-				device generic 0 on end
-			end
-		end
-		device ref heci1	on end
-		device ref heci2	on end
-		device ref heci3	on end
-		device ref pcie_rp05	on
-			chip drivers/wifi/generic
-				register "wake" = "GPE0_DW3_00"
-				device pci 00.0 on end
-			end
-		end
-		device ref xhci		on end
-		device ref i2c0		on
-			chip drivers/i2c/da7219
-				register "irq" = "ACPI_IRQ_LEVEL_LOW(GPIO_116_IRQ)"
-				register "btn_cfg" = "50"
-				register "mic_det_thr" = "200"
-				register "jack_ins_deb" = "20"
-				register "jack_det_rate" = ""32ms_64ms""
-				register "jack_rem_deb" = "1"
-				register "a_d_btn_thr" = "0xa"
-				register "d_b_btn_thr" = "0x16"
-				register "b_c_btn_thr" = "0x21"
-				register "c_mic_btn_thr" = "0x3e"
-				register "btn_avg" = "4"
-				register "adc_1bit_rpt" = "1"
-				register "micbias_lvl" = "2600"
-				register "mic_amp_in_sel" = ""diff""
-				device i2c 1a on end
-			end
-		end
-		device ref i2c1		on end
-		device ref i2c2		on
-			chip drivers/i2c/tpm
-				register "hid" = ""GOOG0005""
-				register "irq" = "ACPI_IRQ_EDGE_LOW(GPIO_28_IRQ)"
-				device i2c 50 on end
-			end
-		end
-		device ref i2c3		on
-			chip drivers/i2c/generic
-				register "hid" = ""ELAN0001""
-				register "desc" = ""ELAN Touchscreen""
-				register "irq" = "ACPI_IRQ_LEVEL_LOW(GPIO_21_IRQ)"
-				register "detect" = "1"
-				register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_36)"
-				register "reset_delay_ms" = "20"
-				register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_152)"
-				register "enable_delay_ms" = "1"
-				register "has_power_resource" = "true"
-				device i2c 10 on end
-			end
-			chip drivers/i2c/generic
-				register "hid" = ""MLFS0000""
-				register "desc" = ""Melfas Touchscreen""
-				register "irq" = "ACPI_IRQ_LEVEL_LOW(GPIO_21_IRQ)"
-				register "detect" = "1"
-				# Melfas TS IC doesn't have reset pin design, current FW also not
-				# declare "ce-gpios" in ACPI _DSD to let Melfas TS driver to know
-				# "enable gpio#152 (VTSP) but because of kernel bug & Melfas TS driver
-				# is unable to separate clear power sequence path for certain
-				# TS IC (ex: MIT-410) and kernel will still obstain GPIO from _CRS
-				# by index "0" since no matched "gpio" in ACPI _DSD.
-				# coreboot needs to have "dummy pin" as workaround  in order to let
-				# kernel driver grab "useless" GPIO to prevent Melfas TS driver cut
-				# power by driver itself.
-				register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_36)"
-				register "reset_delay_ms" = "1"
-				register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_152)"
-				register "enable_delay_ms" = "5"
-				register "has_power_resource" = "true"
-				device i2c 34 on end
-			end
-			chip drivers/i2c/generic
-				register "hid" = ""RAYD0001""
-				register "desc" = ""Raydium Touchscreen""
-				register "irq" = "ACPI_IRQ_LEVEL_LOW(GPIO_21_IRQ)"
-				register "detect" = "1"
-				register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_36)"
-				register "reset_delay_ms" = "1"
-				register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_152)"
-				register "enable_delay_ms" = "50"
-				register "has_power_resource" = "true"
-				device i2c 39 on end
-			end
-			chip drivers/i2c/hid
-				register "generic.hid" = ""WDHT0002""
-				register "generic.desc" = ""WDT Touchscreen""
-				register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPIO_21_IRQ)"
-				register "generic.detect" = "1"
-				register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_36)"
-				register "generic.reset_delay_ms" = "130"
-				register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_152)"
-				register "generic.enable_delay_ms" = "1"
-				register "generic.has_power_resource" = "1"
-				register "hid_desc_reg_offset" = "0x20"
-				device i2c 2c on end
-			end
-			chip drivers/i2c/hid
-				register "generic.hid" = ""GTCH7503""
-				register "generic.desc" = ""G2TOUCH Touchscreen""
-				register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPIO_21_IRQ)"
-				register "generic.detect" = "1"
-				register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_36)"
-				register "generic.reset_delay_ms" = "50"
-				register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_152)"
-				register "generic.enable_delay_ms" = "1"
-				register "generic.has_power_resource" = "1"
-				register "hid_desc_reg_offset" = "0x01"
-				device i2c 40 on end
-			end
-		end
-		device ref i2c4		on
-			chip drivers/i2c/generic
-				register "hid" = ""ELAN0000""
-				register "desc" = ""ELAN Touchpad""
-				register "irq" = "ACPI_IRQ_LEVEL_LOW(GPIO_18_IRQ)"
-				register "wake" = "GPE0_DW1_15"
-				register "detect" = "1"
-				device i2c 15 on end
-			end
-		end
-		device ref i2c5		on
-			chip drivers/i2c/hid
-				register "generic.hid" = ""WCOM50C1""
-				register "generic.desc" = ""WCOM Digitizer""
-				register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPIO_13_IRQ)"
-				register "hid_desc_reg_offset" = "0x1"
-				device i2c 0x9 on end
-			end
-		end
-		device ref uart0	on end
-		device ref uart1	on end
-		device ref uart2	on end
-		device ref spi0		on end
-		device ref pwm		on end
-		device ref sdcard	on end
-		device ref emmc		on end
-		device ref lpc_espi	on
-			chip ec/google/chromeec
-				device pnp 0c09.0 on end
-			end
-		end
-		device ref smbus	on end
-	end
-end
diff --git a/src/mainboard/google/reef/variants/snappy/overridetree.cb b/src/mainboard/google/reef/variants/snappy/overridetree.cb
new file mode 100644
index 0000000000..3c420d4ddb
--- /dev/null
+++ b/src/mainboard/google/reef/variants/snappy/overridetree.cb
@@ -0,0 +1,113 @@
+chip soc/intel/apollolake
+	# Intel Common SoC Config
+	register "common_soc_config" = "{
+		.i2c[0] = {
+			.speed = I2C_SPEED_FAST,
+			.rise_time_ns = 44,
+			.fall_time_ns = 22,
+		},
+		.i2c[2] = {
+			.early_init = 1,
+			.speed = I2C_SPEED_FAST,
+			.rise_time_ns = 40,
+			.fall_time_ns = 20,
+		},
+		.i2c[3] = {
+			.speed = I2C_SPEED_FAST,
+			.rise_time_ns = 70,
+			.fall_time_ns = 164,
+		},
+		.i2c[4] = {
+			.speed = I2C_SPEED_FAST,
+			.rise_time_ns = 20,
+			.fall_time_ns = 164,
+		},
+		.i2c[5] = {
+			.speed = I2C_SPEED_FAST,
+			.rise_time_ns = 152,
+			.fall_time_ns = 30,
+		},
+	}"
+
+	# Override USB2 PER PORT register (PORT 1)
+	register "usb2eye[1]" = "{
+		.Usb20PerPortPeTxiSet = 7,
+		.Usb20PerPortTxiSet = 0,
+	}"
+
+	device domain 0 on
+		device ref i2c3		on
+			chip drivers/i2c/generic
+				register "hid" = ""ELAN0001""
+				register "desc" = ""ELAN Touchscreen""
+				register "irq" = "ACPI_IRQ_LEVEL_LOW(GPIO_21_IRQ)"
+				register "detect" = "1"
+				register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_36)"
+				register "reset_delay_ms" = "20"
+				register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_152)"
+				register "enable_delay_ms" = "1"
+				register "has_power_resource" = "true"
+				device i2c 10 on end
+			end
+			chip drivers/i2c/generic
+				register "hid" = ""MLFS0000""
+				register "desc" = ""Melfas Touchscreen""
+				register "irq" = "ACPI_IRQ_LEVEL_LOW(GPIO_21_IRQ)"
+				register "detect" = "1"
+				# Melfas TS IC doesn't have reset pin design, current FW also not
+				# declare "ce-gpios" in ACPI _DSD to let Melfas TS driver to know
+				# "enable gpio#152 (VTSP) but because of kernel bug & Melfas TS driver
+				# is unable to separate clear power sequence path for certain
+				# TS IC (ex: MIT-410) and kernel will still obstain GPIO from _CRS
+				# by index "0" since no matched "gpio" in ACPI _DSD.
+				# coreboot needs to have "dummy pin" as workaround  in order to let
+				# kernel driver grab "useless" GPIO to prevent Melfas TS driver cut
+				# power by driver itself.
+				register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_36)"
+				register "reset_delay_ms" = "1"
+				register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_152)"
+				register "enable_delay_ms" = "5"
+				register "has_power_resource" = "true"
+				device i2c 34 on end
+			end
+			chip drivers/i2c/generic
+				register "hid" = ""RAYD0001""
+				register "desc" = ""Raydium Touchscreen""
+				register "irq" = "ACPI_IRQ_LEVEL_LOW(GPIO_21_IRQ)"
+				register "detect" = "1"
+				register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_36)"
+				register "reset_delay_ms" = "1"
+				register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_152)"
+				register "enable_delay_ms" = "50"
+				register "has_power_resource" = "true"
+				device i2c 39 on end
+			end
+			chip drivers/i2c/hid
+				register "generic.hid" = ""WDHT0002""
+				register "generic.desc" = ""WDT Touchscreen""
+				register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPIO_21_IRQ)"
+				register "generic.detect" = "1"
+				register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_36)"
+				register "generic.reset_delay_ms" = "130"
+				register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_152)"
+				register "generic.enable_delay_ms" = "1"
+				register "generic.has_power_resource" = "1"
+				register "hid_desc_reg_offset" = "0x20"
+				device i2c 2c on end
+			end
+			chip drivers/i2c/hid
+				register "generic.hid" = ""GTCH7503""
+				register "generic.desc" = ""G2TOUCH Touchscreen""
+				register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPIO_21_IRQ)"
+				register "generic.detect" = "1"
+				register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_36)"
+				register "generic.reset_delay_ms" = "50"
+				register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_152)"
+				register "generic.enable_delay_ms" = "1"
+				register "generic.has_power_resource" = "1"
+				register "hid_desc_reg_offset" = "0x01"
+				device i2c 40 on end
+			end
+		end
+	end
+end

From 8602d0e2aa0063aba2437957970fd8f1bd875108 Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Sun, 18 Jan 2026 21:18:35 +0000
Subject: [PATCH 3188/3886] soc/intel/common/block/smm: Keep selected wake
 sources enabled in S5
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

The generic Intel SMM S5 entry path disables all GPEs before asserting
SLP_EN, which clears OS-armed wake enables (e.g. LAN_WAKE) and prevents
Wake-on-LAN from S5.

Add a mainboard override hook, mainboard_smi_sleep_finalize(), called
after the S5 teardown but before SLP_EN is asserted, allowing boards to
restore required wake sources.

Change-Id: I9e97308ed94961fc4c08a10714b1b53f198bb593
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90792
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
---
 src/cpu/x86/smm/smm_module_handler.c        | 1 +
 src/include/cpu/x86/smm.h                   | 1 +
 src/soc/intel/common/block/smm/smihandler.c | 3 +++
 3 files changed, 5 insertions(+)

diff --git a/src/cpu/x86/smm/smm_module_handler.c b/src/cpu/x86/smm/smm_module_handler.c
index d9f64204d6..8bcda32b33 100644
--- a/src/cpu/x86/smm/smm_module_handler.c
+++ b/src/cpu/x86/smm/smm_module_handler.c
@@ -226,6 +226,7 @@ void __weak southbridge_smi_handler(void) {}
 void __weak mainboard_smi_gpi(u32 gpi_sts) {}
 int __weak mainboard_smi_apmc(u8 data) { return 0; }
 void __weak mainboard_smi_sleep(u8 slp_typ) {}
+void __weak mainboard_smi_sleep_finalize(u8 slp_typ) {}
 void __weak mainboard_smi_finalize(void) {}
 
 void __weak smm_soc_early_init(void) {}
diff --git a/src/include/cpu/x86/smm.h b/src/include/cpu/x86/smm.h
index b552d33b5a..8c41623817 100644
--- a/src/include/cpu/x86/smm.h
+++ b/src/include/cpu/x86/smm.h
@@ -61,6 +61,7 @@ void southbridge_smi_handler(void);
 void mainboard_smi_gpi(u32 gpi_sts);
 int  mainboard_smi_apmc(u8 data);
 void mainboard_smi_sleep(u8 slp_typ);
+void mainboard_smi_sleep_finalize(u8 slp_typ);
 void mainboard_smi_finalize(void);
 int mainboard_set_smm_log_level(void);
 
diff --git a/src/soc/intel/common/block/smm/smihandler.c b/src/soc/intel/common/block/smm/smihandler.c
index 59489a4f03..cd78de26c3 100644
--- a/src/soc/intel/common/block/smm/smihandler.c
+++ b/src/soc/intel/common/block/smm/smihandler.c
@@ -220,6 +220,9 @@ void smihandler_southbridge_sleep(
 		break;
 	}
 
+	/* Allow mainboard to restore wake sources (e.g. for S5 WOL). */
+	mainboard_smi_sleep_finalize(slp_typ);
+
 	/*
 	 * Write back to the SLP register to cause the originally intended
 	 * event again. We need to set BIT13 (SLP_EN) though to make the

From 7c4a0479dd6900b50561683f748d8cf4cdecbf37 Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Sun, 18 Jan 2026 21:20:33 +0000
Subject: [PATCH 3189/3886] mb/starlabs/byte_adl: Allow WOL in S5
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Utilise mainboard_smi_sleep_finalize to leave LAN_WAKE# armed
when entering S5.

Change-Id: I85d3bea71f07dae1c9d6caa89015d52dca5116ce
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90793
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
---
 src/mainboard/starlabs/byte_adl/smihandler.c  | 27 +++++++++++++++++++
 .../byte_adl/variants/mk_ii/devicetree.cb     |  4 +--
 2 files changed, 29 insertions(+), 2 deletions(-)
 create mode 100644 src/mainboard/starlabs/byte_adl/smihandler.c

diff --git a/src/mainboard/starlabs/byte_adl/smihandler.c b/src/mainboard/starlabs/byte_adl/smihandler.c
new file mode 100644
index 0000000000..fa77eb0568
--- /dev/null
+++ b/src/mainboard/starlabs/byte_adl/smihandler.c
@@ -0,0 +1,27 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <acpi/acpi.h>
+#include <arch/io.h>
+#include <cpu/x86/smm.h>
+#include <intelblocks/pmclib.h>
+#include <soc/gpe.h>
+#include <soc/iomap.h>
+#include <soc/pm.h>
+#include <types.h>
+
+void mainboard_smi_sleep_finalize(u8 slp_typ)
+{
+	if (slp_typ != ACPI_S5)
+		return;
+
+	/*
+	 * Keep LAN_WAKE# armed in S5 for WOL.
+	 * GPE0_LAN_WAK is GPE 112, which is bit 16 in the STD GPE block (127:96).
+	 */
+	const uint32_t lan_wake_mask = 1U << (GPE0_LAN_WAK - 96);
+
+	/* Clear any pending LAN_WAKE event to avoid immediate wake. */
+	outl(lan_wake_mask, ACPI_BASE_ADDRESS + GPE0_STS(GPE_STD));
+	pmc_enable_std_gpe(lan_wake_mask);
+	outl(lan_wake_mask, ACPI_BASE_ADDRESS + GPE0_STS(GPE_STD));
+}
diff --git a/src/mainboard/starlabs/byte_adl/variants/mk_ii/devicetree.cb b/src/mainboard/starlabs/byte_adl/variants/mk_ii/devicetree.cb
index ec5d3c03e9..0ea50a4f36 100644
--- a/src/mainboard/starlabs/byte_adl/variants/mk_ii/devicetree.cb
+++ b/src/mainboard/starlabs/byte_adl/variants/mk_ii/devicetree.cb
@@ -156,7 +156,7 @@ chip soc/intel/alderlake
 			}"
 			chip drivers/pcie/generic
 				register "wake_gpe" = "GPE0_LAN_WAK"
-				register "wake_deepest" = "ACPI_S3"
+				register "wake_deepest" = "ACPI_S5"
 				device generic 0 on end
 			end
 			smbios_slot_desc				"SlotTypePciExpressGen4x1"
@@ -174,7 +174,7 @@ chip soc/intel/alderlake
 			}"
 			chip drivers/pcie/generic
 				register "wake_gpe" = "GPE0_LAN_WAK"
-				register "wake_deepest" = "ACPI_S3"
+				register "wake_deepest" = "ACPI_S5"
 				device generic 0 on end
 			end
 			smbios_slot_desc				"SlotTypePciExpressGen3X4"

From dd817408e127105da1fd68e078d73fc523549a9e Mon Sep 17 00:00:00 2001
From: Patrick Rudolph <patrick.rudolph@9elements.com>
Date: Thu, 13 Feb 2025 13:03:37 +0100
Subject: [PATCH 3190/3886] device/pci_device: Fix leftover devices

Don't print leftover devices when they are disabled in the devicetree.
It's expected to not find a device when it's not enabled.

Change-Id: Ia6e998d3088fbd329f976e66a92e08ecae9f760a
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86491
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
---
 src/device/pci_device.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/device/pci_device.c b/src/device/pci_device.c
index 202e8b5055..d7f6a3ad34 100644
--- a/src/device/pci_device.c
+++ b/src/device/pci_device.c
@@ -1442,7 +1442,7 @@ void pci_scan_bus(struct bus *bus, unsigned int min_devfn,
 		 * and it has a Vendor ID of 0 (the default for a device that
 		 * could not be probed).
 		 */
-		if (dev->vendor != 0 || dev->hidden) {
+		if (dev->vendor != 0 || dev->hidden || !dev->enabled) {
 			prev = &dev->sibling;
 			continue;
 		}

From 37fee37ceab25dae8b1e9d9ebffedcc00b1e7420 Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Wed, 28 Jan 2026 22:23:40 +0000
Subject: [PATCH 3191/3886] Revert "ec/starlabs/merlin: Add retry to
 get_ec_version()"

This reverts commit 60c8496afe6e43901c774ac180965125c805fbc4.

The reason for needing that was the EC initialising PM1DO to 0
on reset, which set the OBF flag, leading to coreboot consuming
0 on it's first read.

This issue has now been fixed, so the rety is no longer needed.

Change-Id: I87b779e3859daecfe6285cd499e8d6b61cdbb852
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90979
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/ec/starlabs/merlin/ite.c | 4 ----
 1 file changed, 4 deletions(-)

diff --git a/src/ec/starlabs/merlin/ite.c b/src/ec/starlabs/merlin/ite.c
index ec4c9a65ab..953c9e3de6 100644
--- a/src/ec/starlabs/merlin/ite.c
+++ b/src/ec/starlabs/merlin/ite.c
@@ -1,7 +1,6 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
 #include <console/console.h>
-#include <delay.h>
 #include <device/device.h>
 #include <device/pnp.h>
 #include <ec/acpi/ec.h>
@@ -18,9 +17,6 @@
 
 uint16_t ec_get_version(void)
 {
-	for (int i = 0; i < 10 && ec_read(ECRAM_MAJOR_VERSION) == 0; i++)
-		mdelay(10);
-
 	return (ec_read(ECRAM_MAJOR_VERSION) << 8) | ec_read(ECRAM_MINOR_VERSION);
 }
 

From 56403e52a130e3c318c0a9e9e3a89fb6ef1f2e18 Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Tue, 20 Jan 2026 12:15:00 +0000
Subject: [PATCH 3192/3886] mb/starlabs/*: Expose BIOS Lock option

Expose BIOS Lock option in CFR, that controls SMM BIOS Write
Protection.

Change-Id: I327881785d3292d8fd4805f5dd5ac0f2f0ed32dd
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90810
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/starlabs/byte_adl/cfr.c     | 1 +
 src/mainboard/starlabs/common/Kconfig     | 6 ++++++
 src/mainboard/starlabs/lite/cfr.c         | 1 +
 src/mainboard/starlabs/starbook/cfr.c     | 1 +
 src/mainboard/starlabs/starfighter/cfr.c  | 1 +
 src/mainboard/starlabs/starlite_adl/cfr.c | 1 +
 6 files changed, 11 insertions(+)

diff --git a/src/mainboard/starlabs/byte_adl/cfr.c b/src/mainboard/starlabs/byte_adl/cfr.c
index e80108ba42..d67d501508 100644
--- a/src/mainboard/starlabs/byte_adl/cfr.c
+++ b/src/mainboard/starlabs/byte_adl/cfr.c
@@ -50,6 +50,7 @@ static struct sm_obj_form devices_group = {
 static struct sm_obj_form security_group = {
 	.ui_name = "Security",
 	.obj_list = (const struct sm_object *[]) {
+		&bios_lock,
 		&intel_tme,
 		NULL
 	},
diff --git a/src/mainboard/starlabs/common/Kconfig b/src/mainboard/starlabs/common/Kconfig
index a59bc86dcf..e4361dea5f 100644
--- a/src/mainboard/starlabs/common/Kconfig
+++ b/src/mainboard/starlabs/common/Kconfig
@@ -4,6 +4,12 @@ if VENDOR_STARLABS
 
 menu "Star Labs Settings"
 
+config BOOTMEDIA_SMM_BWP
+	default y
+
+config BOOTMEDIA_SMM_BWP_RUNTIME_OPTION
+	default y
+
 config DRIVERS_EFI_FW_INFO
 	default y
 
diff --git a/src/mainboard/starlabs/lite/cfr.c b/src/mainboard/starlabs/lite/cfr.c
index 81d236ea86..0ca59b8e48 100644
--- a/src/mainboard/starlabs/lite/cfr.c
+++ b/src/mainboard/starlabs/lite/cfr.c
@@ -57,6 +57,7 @@ static struct sm_obj_form devices_group = {
 static struct sm_obj_form security_group = {
 	.ui_name = "Security",
 	.obj_list = (const struct sm_object *[]) {
+		&bios_lock,
 		&intel_tme,
 		NULL
 	},
diff --git a/src/mainboard/starlabs/starbook/cfr.c b/src/mainboard/starlabs/starbook/cfr.c
index d317d2e531..f95ff65cb3 100644
--- a/src/mainboard/starlabs/starbook/cfr.c
+++ b/src/mainboard/starlabs/starbook/cfr.c
@@ -87,6 +87,7 @@ static struct sm_obj_form devices_group = {
 static struct sm_obj_form security_group = {
 	.ui_name = "Security",
 	.obj_list = (const struct sm_object *[]) {
+		&bios_lock,
 		&intel_tme,
 		NULL
 	},
diff --git a/src/mainboard/starlabs/starfighter/cfr.c b/src/mainboard/starlabs/starfighter/cfr.c
index 45df94c424..dc306f5776 100644
--- a/src/mainboard/starlabs/starfighter/cfr.c
+++ b/src/mainboard/starlabs/starfighter/cfr.c
@@ -77,6 +77,7 @@ static struct sm_obj_form devices_group = {
 static struct sm_obj_form security_group = {
 	.ui_name = "Security",
 	.obj_list = (const struct sm_object *[]) {
+		&bios_lock,
 		&intel_tme,
 		NULL
 	},
diff --git a/src/mainboard/starlabs/starlite_adl/cfr.c b/src/mainboard/starlabs/starlite_adl/cfr.c
index 62370cfc2d..9526992fd5 100644
--- a/src/mainboard/starlabs/starlite_adl/cfr.c
+++ b/src/mainboard/starlabs/starlite_adl/cfr.c
@@ -78,6 +78,7 @@ static struct sm_obj_form devices_group = {
 static struct sm_obj_form security_group = {
 	.ui_name = "Security",
 	.obj_list = (const struct sm_object *[]) {
+		&bios_lock,
 		&intel_tme,
 		NULL
 	},

From 8ec0dc7356da2addf487f5a18f790ac0cb5395c9 Mon Sep 17 00:00:00 2001
From: Patrick Rudolph <patrick.rudolph@9elements.com>
Date: Wed, 28 Jan 2026 11:11:12 +0100
Subject: [PATCH 3193/3886] soc/intel/common/block/cpu/smmrelocate: Fix
 regression
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Fix regression introduced by commit d18cc50e6ab2 ("soc/intel/xeon_sp:
Use common smm_relocate").

The MSR SMM_FEATURE_CONTROL_MSR is only implemented on client SoCs.
Starting from Haswell server onwards the "SMM feature control" on
server platforms resides on the UBOX in PCI space.

Parallel SMM relocation was never supported on server platforms, thus
disable parallel SMM relocation for now and thus fix booting on all
Xeon-SP platforms. Added a FIXME to possibly implement this feature
in the future.

TEST=Can boot on OCP/tiogapass again.

Change-Id: I7b4fbe633046acbf9f921cca722ff343a64962cd
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90970
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
---
 src/soc/intel/common/block/cpu/smmrelocate.c | 9 +++++++++
 src/soc/intel/snowridge/include/soc/msr.h    | 8 --------
 2 files changed, 9 insertions(+), 8 deletions(-)

diff --git a/src/soc/intel/common/block/cpu/smmrelocate.c b/src/soc/intel/common/block/cpu/smmrelocate.c
index 8c45c218b2..e510c96f99 100644
--- a/src/soc/intel/common/block/cpu/smmrelocate.c
+++ b/src/soc/intel/common/block/cpu/smmrelocate.c
@@ -78,6 +78,15 @@ static int bsp_setup_msr_save_state(struct smm_relocation_params *relo_params)
 {
 	msr_t smm_mca_cap;
 
+	/*
+	 * FIXME: On Xeon-SP the MSR SMM_FEATURE_CONTROL_MSR is not implemented.
+	 *        SMM feature control resides on the UBOX PCI device.
+	 * FIXME: Need to enable save state in MSRs on all sockets, however BSP
+	 *        runs on a single socket only.
+	 */
+	if (CONFIG(XEON_SP_COMMON_BASE) || CONFIG(SOC_INTEL_SNOWRIDGE))
+		return 0;
+
 	smm_mca_cap = rdmsr(SMM_MCA_CAP_MSR);
 	if (smm_mca_cap.hi & SMM_CPU_SVRSTR_MASK) {
 		msr_t smm_feature_control;
diff --git a/src/soc/intel/snowridge/include/soc/msr.h b/src/soc/intel/snowridge/include/soc/msr.h
index b45050b794..45bf831290 100644
--- a/src/soc/intel/snowridge/include/soc/msr.h
+++ b/src/soc/intel/snowridge/include/soc/msr.h
@@ -5,14 +5,6 @@
 
 #include <intelblocks/msr.h>
 
-/**
- * @brief Force serialized SMM relocation by hardcoding `SMM_CPU_SVRSTR` feature as not supported.
- */
-#ifdef SMM_CPU_SVRSTR_MASK
-#undef SMM_CPU_SVRSTR_MASK
-#endif
-#define SMM_CPU_SVRSTR_MASK 0
-
 #define MSR_BIOS_DONE       0x151
 #define ENABLE_IA_UNTRUSTED BIT(0)
 

From 8ade2c8239c9fe84900bd8d8a8b236e5991b257e Mon Sep 17 00:00:00 2001
From: Subrata Banik <subratabanik@google.com>
Date: Wed, 28 Jan 2026 13:21:20 +0530
Subject: [PATCH 3194/3886] mb/google/fatcat/var/lapis: Remove redundant splash
 logo alignment

This patch removes logo_valignment from overridetree.cb. The alignment
`FW_SPLASH_VALIGNMENT_CENTER` is the default behavior in the coreboot
splash driver, making this explicit assignment unnecessary.

BUG=none
TEST=Build and boot lapis; verify logo remains centered.

Change-Id: Ibf3ea2a9843b31f39fd08621f6056e63c2676ff7
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90965
Reviewed-by: YH Lin <yueherngl@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Pranava Y N <pranavayn@google.com>
Reviewed-by: Avi Uday <aviuday@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
---
 src/mainboard/google/fatcat/variants/lapis/overridetree.cb | 1 -
 1 file changed, 1 deletion(-)

diff --git a/src/mainboard/google/fatcat/variants/lapis/overridetree.cb b/src/mainboard/google/fatcat/variants/lapis/overridetree.cb
index 3d7e53aba5..930a464fbf 100644
--- a/src/mainboard/google/fatcat/variants/lapis/overridetree.cb
+++ b/src/mainboard/google/fatcat/variants/lapis/overridetree.cb
@@ -111,7 +111,6 @@ chip soc/intel/pantherlake
 	#| I2C3              | cr50 TPM.                 |
 	#+-------------------+---------------------------+
 	register "common_soc_config" = "{
-		.logo_valignment = FW_SPLASH_VALIGNMENT_MIDDLE,
 		.i2c[3] = {
 			.early_init=1,
 			.speed = I2C_SPEED_FAST,

From 85e59e87e9a583db1266f51b872823dd44606a0c Mon Sep 17 00:00:00 2001
From: Anand Vaikar <a.vaikar2021@gmail.com>
Date: Tue, 27 Jan 2026 15:54:46 +0530
Subject: [PATCH 3195/3886] soc/amd/common/block/apob: Fix APOB data hash
 mismatch issue

In the first boot after coreboot is flashed, ABL FW performs
memory training and passes APOB data to coreboot. coreboot
writes APOB data in SPI flash along with hash of the APOB data.
If APOB signature is not written in CMOS, Memory context is
not restored by ABL in subsequent boot and full training is
initiated which increases boot time.coreboot keeps writing the
APOB data to flash in every boot due to hash mismatch of APOB
data which inturn increases boot time.This change fixes the
issue of ABL FW not doing Memory Context restore due to missing
CMOS signature.On some older platforms FSP writes this signature
unconditionally and hence this coreboot patch doesnt impact
the older platforms.

TEST= Validated on crater platform. APOB write is not initiated
by coreboot on every boot. APOB write to flash happens only once
after the coreboot flash.

Change-Id: Id799d0d2ed9f54e29db7681509f3d66c1638b6ac
Signed-off-by: Anand Vaikar <a.vaikar2021@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90947
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/soc/amd/common/block/apob/apob_cache.c | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/src/soc/amd/common/block/apob/apob_cache.c b/src/soc/amd/common/block/apob/apob_cache.c
index d70adfc5b2..d9a7067683 100644
--- a/src/soc/amd/common/block/apob/apob_cache.c
+++ b/src/soc/amd/common/block/apob/apob_cache.c
@@ -17,6 +17,7 @@
 #include <thread.h>
 #include <timestamp.h>
 #include <types.h>
+#include <pc80/mc146818rtc.h>
 
 #define DEFAULT_MRC_CACHE	"RW_MRC_CACHE"
 #define DEFAULT_MRC_CACHE_SIZE	FMAP_SECTION_RW_MRC_CACHE_SIZE
@@ -272,6 +273,10 @@ static void soc_update_apob_cache(void *unused)
 	if (CONFIG(SOC_AMD_COMMON_BLOCK_APOB_HASH))
 		update_apob_nv_hash(ram_hash, &write_rdev);
 
+	// update the signature in CMOS to indicate APOB updated.
+	cmos_write(0x5A, 0x86);
+	cmos_write(0xA5, 0x87);
+
 	timestamp_add_now(TS_AMD_APOB_END);
 
 	printk(BIOS_INFO, "Updated APOB in flash\n");

From e464a02635f2bcd3833711e09f07f9426e4b620f Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Tue, 27 Jan 2026 18:15:22 -0600
Subject: [PATCH 3196/3886] ec/google/chromeec: Add Kconfig to enable battery
 full workaround
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Commit 55a972236ee9 ("chromeec: Disable battery remaining capacity
workaround") disabled the workaround for all ChromeEC devices, since
newer EC firmware applies compensation via battery_compensate_params.
Older boards use EC branches that lack this logic; without it, users can
see 93–100% charge–discharge cycling and stale full-capacity reporting.

Add a Kconfig to configure the workaround, and select it for older
boards whose EC firmware lacks battery_compensate_params logic.
EC firmware branches were inspected to determine which ones lack this
logic.


TEST=build/boot google/lulu, verify battery full indication works
     correctly with the Kconfig selected.

Change-Id: I096e0cf402e07f846b961319e01fb8f2c2dde7fc
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90960
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
---
 src/ec/google/chromeec/Kconfig          | 11 +++++++++++
 src/ec/google/chromeec/acpi/battery.asl | 10 ++++++----
 src/mainboard/google/auron/Kconfig      |  1 +
 src/mainboard/google/cyan/Kconfig       |  1 +
 src/mainboard/google/eve/Kconfig        |  1 +
 src/mainboard/google/glados/Kconfig     |  1 +
 src/mainboard/google/link/Kconfig       |  1 +
 src/mainboard/google/poppy/Kconfig      |  1 +
 src/mainboard/google/rambi/Kconfig      |  1 +
 src/mainboard/google/reef/Kconfig       |  1 +
 src/mainboard/google/slippy/Kconfig     |  1 +
 11 files changed, 26 insertions(+), 4 deletions(-)

diff --git a/src/ec/google/chromeec/Kconfig b/src/ec/google/chromeec/Kconfig
index 0239a08904..b09c64a88c 100644
--- a/src/ec/google/chromeec/Kconfig
+++ b/src/ec/google/chromeec/Kconfig
@@ -220,6 +220,17 @@ config EC_GOOGLE_CHROMEEC_READ_BATTERY_LONG_STRING
 
 	  If unsure, say N.
 
+config EC_GOOGLE_CHROMEEC_NEEDS_BATTERY_WORKAROUND
+	bool
+	help
+	  Enable the ACPI "full battery" workaround (BFWK) for remaining capacity.
+	  When enabled, remaining charge near full is reported as full capacity to
+	  hide 93-100% charge-discharge cycles and to handle batteries that don't report
+	  full capacity timely.
+	  Select this for older boards whose EC firmware lacks battery_compensate_params
+	  logic.
+	  If unsure, say N.
+
 config EC_GOOGLE_CHROMEEC_LPC_GENERIC_MEMORY_RANGE
 	def_bool n
 	help
diff --git a/src/ec/google/chromeec/acpi/battery.asl b/src/ec/google/chromeec/acpi/battery.asl
index 41b77861a5..eb19c3c422 100644
--- a/src/ec/google/chromeec/acpi/battery.asl
+++ b/src/ec/google/chromeec/acpi/battery.asl
@@ -414,8 +414,9 @@ Device (BAT0)
 	})
 	Name (BSTP, 0)
 
-	// Workaround for full battery status, disabled by default
-	Name (BFWK, 0)
+	// Workaround for full battery status, disabled by default,
+	// enabled via Kconfig for older boards lacking EC compensation.
+	Name (BFWK, CONFIG(EC_GOOGLE_CHROMEEC_NEEDS_BATTERY_WORKAROUND))
 
 	// Method to enable full battery workaround
 	Method (BFWE)
@@ -504,8 +505,9 @@ Device (BAT1)
 	})
 	Name (BSTP, 0)
 
-	// Workaround for full battery status, disabled by default
-	Name (BFWK, 0)
+	// Workaround for full battery status, disabled by default,
+	// enabled via Kconfig for older boards lacking EC compensation.
+	Name (BFWK, CONFIG(EC_GOOGLE_CHROMEEC_NEEDS_BATTERY_WORKAROUND))
 
 	// Method to enable full battery workaround
 	Method (BFWE)
diff --git a/src/mainboard/google/auron/Kconfig b/src/mainboard/google/auron/Kconfig
index b84708f657..a9039912db 100644
--- a/src/mainboard/google/auron/Kconfig
+++ b/src/mainboard/google/auron/Kconfig
@@ -9,6 +9,7 @@ config BOARD_GOOGLE_BASEBOARD_AURON
 	select DRIVERS_OPTION_CFR_ENABLED if PAYLOAD_EDK2 && SMMSTORE
 	select EC_GOOGLE_CHROMEEC
 	select EC_GOOGLE_CHROMEEC_LPC
+	select EC_GOOGLE_CHROMEEC_NEEDS_BATTERY_WORKAROUND
 	select HAVE_ACPI_RESUME
 	select HAVE_ACPI_TABLES
 	select HAVE_OPTION_TABLE
diff --git a/src/mainboard/google/cyan/Kconfig b/src/mainboard/google/cyan/Kconfig
index fe4d2a1067..bda0416172 100644
--- a/src/mainboard/google/cyan/Kconfig
+++ b/src/mainboard/google/cyan/Kconfig
@@ -8,6 +8,7 @@ config BOARD_GOOGLE_BASEBOARD_CYAN
 	select EC_GOOGLE_CHROMEEC_BOARDID
 	select EC_GOOGLE_CHROMEEC_LPC
 	select EC_GOOGLE_CHROMEEC_MEC
+	select EC_GOOGLE_CHROMEEC_NEEDS_BATTERY_WORKAROUND
 	select HAVE_ACPI_RESUME
 	select HAVE_ACPI_TABLES
 	select HAVE_OPTION_TABLE
diff --git a/src/mainboard/google/eve/Kconfig b/src/mainboard/google/eve/Kconfig
index 40eebc5c50..b473d502bf 100644
--- a/src/mainboard/google/eve/Kconfig
+++ b/src/mainboard/google/eve/Kconfig
@@ -15,6 +15,7 @@ config BOARD_SPECIFIC_OPTIONS
 	select EC_GOOGLE_CHROMEEC
 	select EC_GOOGLE_CHROMEEC_BOARDID
 	select EC_GOOGLE_CHROMEEC_ESPI
+	select EC_GOOGLE_CHROMEEC_NEEDS_BATTERY_WORKAROUND
 	select HAVE_ACPI_RESUME
 	select HAVE_ACPI_TABLES
 	select I2C_TPM
diff --git a/src/mainboard/google/glados/Kconfig b/src/mainboard/google/glados/Kconfig
index 811a03deac..6786d1b5f1 100644
--- a/src/mainboard/google/glados/Kconfig
+++ b/src/mainboard/google/glados/Kconfig
@@ -10,6 +10,7 @@ config BOARD_GOOGLE_BASEBOARD_GLADOS
 	select EC_GOOGLE_CHROMEEC_BOARDID
 	select EC_GOOGLE_CHROMEEC_LPC
 	select EC_GOOGLE_CHROMEEC_MEC
+	select EC_GOOGLE_CHROMEEC_NEEDS_BATTERY_WORKAROUND
 	select EC_GOOGLE_CHROMEEC_PD
 	select HAVE_ACPI_RESUME
 	select HAVE_ACPI_TABLES
diff --git a/src/mainboard/google/link/Kconfig b/src/mainboard/google/link/Kconfig
index 86dd014f2a..df85382246 100644
--- a/src/mainboard/google/link/Kconfig
+++ b/src/mainboard/google/link/Kconfig
@@ -10,6 +10,7 @@ config BOARD_SPECIFIC_OPTIONS
 	select DRIVERS_OPTION_CFR_ENABLED if PAYLOAD_EDK2 && SMMSTORE
 	select EC_GOOGLE_CHROMEEC
 	select EC_GOOGLE_CHROMEEC_AUTO_FAN_CTRL
+	select EC_GOOGLE_CHROMEEC_NEEDS_BATTERY_WORKAROUND
 	select EC_GOOGLE_CHROMEEC_LPC
 	select HAVE_ACPI_RESUME
 	select HAVE_ACPI_TABLES
diff --git a/src/mainboard/google/poppy/Kconfig b/src/mainboard/google/poppy/Kconfig
index a9b45920db..ac9aa54e56 100644
--- a/src/mainboard/google/poppy/Kconfig
+++ b/src/mainboard/google/poppy/Kconfig
@@ -73,6 +73,7 @@ config BOARD_GOOGLE_NOCTURNE
 	select DRIVERS_I2C_SX9310
 	select DRIVERS_SPI_ACPI
 	select DRIVERS_USB_ACPI
+	select EC_GOOGLE_CHROMEEC_NEEDS_BATTERY_WORKAROUND
 	select EXCLUDE_NATIVE_SD_INTERFACE
 	select GEO_SAR_ENABLE if CHROMEOS_WIFI_SAR
 	select INTEL_GMA_HAVE_VBT
diff --git a/src/mainboard/google/rambi/Kconfig b/src/mainboard/google/rambi/Kconfig
index 750eba1e30..ccdc02a45c 100644
--- a/src/mainboard/google/rambi/Kconfig
+++ b/src/mainboard/google/rambi/Kconfig
@@ -6,6 +6,7 @@ config BOARD_GOOGLE_BASEBOARD_RAMBI
 	select BOARD_ROMSIZE_KB_8192
 	select EC_GOOGLE_CHROMEEC
 	select EC_GOOGLE_CHROMEEC_LPC
+	select EC_GOOGLE_CHROMEEC_NEEDS_BATTERY_WORKAROUND
 	select ENABLE_BUILTIN_COM1 if CONSOLE_SERIAL
 	select HAVE_ACPI_RESUME
 	select HAVE_ACPI_TABLES
diff --git a/src/mainboard/google/reef/Kconfig b/src/mainboard/google/reef/Kconfig
index 06c5575e45..1ce2353432 100644
--- a/src/mainboard/google/reef/Kconfig
+++ b/src/mainboard/google/reef/Kconfig
@@ -10,6 +10,7 @@ config BOARD_GOOGLE_BASEBOARD_REEF
 	select DRIVERS_OPTION_CFR_ENABLED if PAYLOAD_EDK2 && SMMSTORE
 	select EC_GOOGLE_CHROMEEC
 	select EC_GOOGLE_CHROMEEC_BOARDID
+	select EC_GOOGLE_CHROMEEC_NEEDS_BATTERY_WORKAROUND
 	select EC_GOOGLE_CHROMEEC_LPC
 	select GOOGLE_SMBIOS_MAINBOARD_VERSION
 	select HAVE_ACPI_RESUME
diff --git a/src/mainboard/google/slippy/Kconfig b/src/mainboard/google/slippy/Kconfig
index d9684d34b3..380ed9fe72 100644
--- a/src/mainboard/google/slippy/Kconfig
+++ b/src/mainboard/google/slippy/Kconfig
@@ -8,6 +8,7 @@ config BOARD_GOOGLE_BASEBOARD_SLIPPY
 	select DRIVERS_OPTION_CFR_ENABLED if PAYLOAD_EDK2 && SMMSTORE
 	select EC_GOOGLE_CHROMEEC
 	select EC_GOOGLE_CHROMEEC_LPC
+	select EC_GOOGLE_CHROMEEC_NEEDS_BATTERY_WORKAROUND
 	select HAVE_ACPI_RESUME
 	select HAVE_ACPI_TABLES
 	select HAVE_OPTION_TABLE

From 1658fb98932e038a6b42724b07ced5da57fd4213 Mon Sep 17 00:00:00 2001
From: Maximilian Brune <maximilian.brune@9elements.com>
Date: Tue, 20 Jan 2026 17:30:52 +0100
Subject: [PATCH 3197/3886] treewide: Use __printf macro instead of
 "__attribute__(format(printf"

Using this, the compiler is going to check if the printf formatting is
correct for our printk messages.

Since we already have the macro, might as well use it.

Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: I247f24ed64c2be7fc411f5e2fdd38715698bc4e3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90829
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 payloads/libpayload/include/stdio.h    | 12 ++++--------
 payloads/libpayload/include/usb/usb.h  |  2 +-
 src/include/console/console.h          |  6 ++----
 util/cbfstool/flashmap/kv_pair.h       |  2 +-
 util/vgabios/include/console/console.h |  2 +-
 5 files changed, 9 insertions(+), 15 deletions(-)

diff --git a/payloads/libpayload/include/stdio.h b/payloads/libpayload/include/stdio.h
index ced4d19b99..d19d3aa847 100644
--- a/payloads/libpayload/include/stdio.h
+++ b/payloads/libpayload/include/stdio.h
@@ -41,14 +41,10 @@ extern FILE *stdout, *stdin, *stderr;
  * @defgroup printf Print functions
  * @{
  */
-int snprintf(char *str, size_t size, const char *fmt, ...)
-	__attribute__((format (printf, 3, 4)));
-int sprintf(char *str, const char *fmt, ...)
-	__attribute__((format (printf, 2, 3)));
-int printf(const char *fmt, ...)
-	__attribute__((format (printf, 1, 2)));
-int fprintf(FILE *file, const char *fmt, ...)
-	__attribute__((format (printf, 2, 3)));
+int snprintf(char *str, size_t size, const char *fmt, ...) __printf(3, 4);
+int sprintf(char *str, const char *fmt, ...) __printf(2, 3);
+int printf(const char *fmt, ...) __printf(1, 2);
+int fprintf(FILE *file, const char *fmt, ...) __printf(2, 3);
 /** @} */
 
 void perror(const char *s);
diff --git a/payloads/libpayload/include/usb/usb.h b/payloads/libpayload/include/usb/usb.h
index f36bb5c5be..9e929e59c8 100644
--- a/payloads/libpayload/include/usb/usb.h
+++ b/payloads/libpayload/include/usb/usb.h
@@ -344,7 +344,7 @@ int usb_interface_check(u16 vendor, u16 device);
 #define USB_QUIRK_TEST				(1 << 31)
 #define USB_QUIRK_NONE				 0
 
-static inline void __attribute__((format(printf, 1, 2))) usb_debug(const char *fmt, ...)
+static inline void __printf(1, 2) usb_debug(const char *fmt, ...)
 {
 #ifdef USB_DEBUG
 	va_list ap;
diff --git a/src/include/console/console.h b/src/include/console/console.h
index 927b1d6ef0..a24425935c 100644
--- a/src/include/console/console.h
+++ b/src/include/console/console.h
@@ -53,7 +53,7 @@ int get_log_level(void);
 void console_init(void);
 int console_log_level(int msg_level);
 
-int printk(int msg_level, const char *fmt, ...) __attribute__((format(printf, 2, 3)));
+int printk(int msg_level, const char *fmt, ...) __printf(2, 3);
 int vprintk(int msg_level, const char *fmt, va_list args);
 
 void do_putchar(unsigned char byte);
@@ -80,9 +80,7 @@ enum { CONSOLE_LOG_NONE = 0, CONSOLE_LOG_FAST, CONSOLE_LOG_ALL };
 static inline int get_log_level(void) { return -1; }
 static inline void console_init(void) {}
 static inline int console_log_level(int msg_level) { return 0; }
-static inline int
-	__attribute__((format(printf, 2, 3)))
-	printk(int LEVEL, const char *fmt, ...) { return 0; }
+static inline int __printf(2, 3) printk(int LEVEL, const char *fmt, ...) { return 0; }
 static inline int vprintk(int LEVEL, const char *fmt, va_list args) { return 0; }
 static inline void do_putchar(unsigned char byte) {}
 static inline long console_time_get_and_reset(void) { return 0; }
diff --git a/util/cbfstool/flashmap/kv_pair.h b/util/cbfstool/flashmap/kv_pair.h
index 5771570743..a582ff764d 100644
--- a/util/cbfstool/flashmap/kv_pair.h
+++ b/util/cbfstool/flashmap/kv_pair.h
@@ -78,7 +78,7 @@ extern struct kv_pair *kv_pair_fmt(struct kv_pair *kv_list,
 #if defined(_WIN32) || (_WIN64)
 				   __attribute__((format(gnu_printf, 3, 4)));
 #else
-				   __attribute__((format(printf, 3, 4)));
+				   __printf(3, 4);
 #endif
 
 /*
diff --git a/util/vgabios/include/console/console.h b/util/vgabios/include/console/console.h
index 0aa5595590..edad4d084b 100644
--- a/util/vgabios/include/console/console.h
+++ b/util/vgabios/include/console/console.h
@@ -3,6 +3,6 @@
 #ifndef _CONSOLE_CONSOLE_H
 #define _CONSOLE_CONSOLE_H
 
-int printk(int msg_level, const char *fmt, ...) __attribute__((format(printf, 2, 3)));
+int printk(int msg_level, const char *fmt, ...) __printf(2, 3);
 
 #endif

From 9ae5af54cc990d6f7e33eae2a56177024d2251c2 Mon Sep 17 00:00:00 2001
From: Mario Scheithauer <mario.scheithauer@siemens.com>
Date: Tue, 27 Jan 2026 10:04:08 +0100
Subject: [PATCH 3198/3886] soc/intel/jasperlake: Move PCIe ModPHY parameter to
 common pcie_rp.h
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Since the ModPHY settings are also available on other Intel platforms,
these parameters should be moved to common code.

Change-Id: Ic2666c7bbd576681dea7f360c396c068b42306e2
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90943
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 .../block/include/intelblocks/pcie_rp.h       | 20 +++++++++++++++-
 src/soc/intel/jasperlake/chip.h               |  1 -
 .../jasperlake/include/soc/pcie_modphy.h      | 24 -------------------
 3 files changed, 19 insertions(+), 26 deletions(-)
 delete mode 100644 src/soc/intel/jasperlake/include/soc/pcie_modphy.h

diff --git a/src/soc/intel/common/block/include/intelblocks/pcie_rp.h b/src/soc/intel/common/block/include/intelblocks/pcie_rp.h
index 68137490b9..9538e3bf06 100644
--- a/src/soc/intel/common/block/include/intelblocks/pcie_rp.h
+++ b/src/soc/intel/common/block/include/intelblocks/pcie_rp.h
@@ -3,7 +3,7 @@
 #ifndef SOC_INTEL_COMMON_BLOCK_PCIE_RP_H
 #define SOC_INTEL_COMMON_BLOCK_PCIE_RP_H
 
-#include <stdint.h>
+#include <types.h>
 
 /*
  * In schematic PCIe root port numbers are 1-based, but FSP use 0-based indexes for
@@ -85,6 +85,24 @@ struct pcie_rp_config {
 	enum PCIE_SPEED_control pcie_rp_pcie_speed;
 };
 
+struct pcie_modphy_config {
+	/* TX Output Downscale Amplitude Adjustment */
+	bool tx_gen1_downscale_amp_override;
+	uint8_t tx_gen1_downscale_amp;
+	/* TX Output Downscale Amplitude Adjustment */
+	bool tx_gen2_downscale_amp_override;
+	uint8_t tx_gen2_downscale_amp;
+	/* TX Output Downscale Amplitude Adjustment */
+	bool tx_gen3_downscale_amp_override;
+	uint8_t tx_gen3_downscale_amp;
+	/* TX Output -3.5dB Mode De-Emphasis Adjustment Setting */
+	uint8_t tx_gen1_de_emph;
+	/* TX Output -3.5dB Mode De-Emphasis Adjustment Setting */
+	uint8_t tx_gen2_de_emph_3p5;
+	/* TX Output -6.0dB Mode De-Emphasis Adjustment Setting */
+	uint8_t tx_gen2_de_emph_6p0;
+};
+
 /*
  * The PCIe Root Ports usually come in groups of up to 8 PCI-device
  * functions.
diff --git a/src/soc/intel/jasperlake/chip.h b/src/soc/intel/jasperlake/chip.h
index 380549451e..3fdf82db97 100644
--- a/src/soc/intel/jasperlake/chip.h
+++ b/src/soc/intel/jasperlake/chip.h
@@ -15,7 +15,6 @@
 #include <soc/gpe.h>
 #include <soc/pch.h>
 #include <soc/pci_devs.h>
-#include <soc/pcie_modphy.h>
 #include <soc/pmc.h>
 #include <soc/serialio.h>
 #include <soc/usb.h>
diff --git a/src/soc/intel/jasperlake/include/soc/pcie_modphy.h b/src/soc/intel/jasperlake/include/soc/pcie_modphy.h
deleted file mode 100644
index 60f145195f..0000000000
--- a/src/soc/intel/jasperlake/include/soc/pcie_modphy.h
+++ /dev/null
@@ -1,24 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#ifndef _SOC_JASPERLAKE_PCIE_MODPHY_H_
-#define _SOC_JASPERLAKE_PCIE_MODPHY_H_
-
-struct pcie_modphy_config {
-	/* TX Output Downscale Amplitude Adjustment */
-	bool tx_gen1_downscale_amp_override;
-	uint8_t tx_gen1_downscale_amp;
-	/* TX Output Downscale Amplitude Adjustment */
-	bool tx_gen2_downscale_amp_override;
-	uint8_t tx_gen2_downscale_amp;
-	/* TX Output Downscale Amplitude Adjustment */
-	bool tx_gen3_downscale_amp_override;
-	uint8_t tx_gen3_downscale_amp;
-	/* TX Output -3.5dB Mode De-Emphasis Adjustment Setting */
-	uint8_t tx_gen1_de_emph;
-	/* TX Output -3.5dB Mode De-Emphasis Adjustment Setting */
-	uint8_t tx_gen2_de_emph_3p5;
-	/* TX Output -6.0dB Mode De-Emphasis Adjustment Setting */
-	uint8_t tx_gen2_de_emph_6p0;
-};
-
-#endif

From 388fb318add4257a74714e11b670a53aa367fe02 Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Mon, 3 Nov 2025 18:40:45 -0600
Subject: [PATCH 3199/3886] soc/intel/common: Add opt-in runtime control for
 BIOS SMM write protection

Add support for runtime control of BIOS lock
(BOOTMEDIA_SMM_BWP) via the CFR option API. This allows
users to enable/disable BIOS write protection in SMM
through the setup menu when explicitly enabled.

The implementation adds a new "bios_lock" CFR option that:
- Controls SMM BIOS write protection at runtime
- Sets EISS (Enable InSMM.STS) when enabled
- Enables SPI/LPC write protection in SMM
- Prevents unauthorised BIOS modifications outside SMM

Security model:
- Runtime control is opt-in via
  BOOTMEDIA_SMM_BWP_RUNTIME_OPTION config
- When disabled, the option is suppressed in CFR
  (not exposed in UI)
- Compile-time CONFIG(BOOTMEDIA_SMM_BWP) serves as the
  default/fallback
- Protects against unauthorised EFI variable
  modifications, bypassing BIOS lock when the runtime
  option is not enabled

The option is integrated into Intel's common lockdown
code and SMI handlers, replacing compile-time-only
checks with conditional runtime lookups where
BOOTMEDIA_SMM_BWP_RUNTIME_OPTION is enabled.

Change-Id: Ie3b63462501e0d204c33dc3f8a006b73da0899d3
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89919
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/security/lockdown/Kconfig                 |  8 ++++++++
 src/security/lockdown/lockdown.h              | 16 ++++++++++++++++
 .../common/block/include/intelblocks/cfr.h    | 19 +++++++++++++++++++
 src/soc/intel/common/block/smm/smihandler.c   |  6 ++++--
 src/soc/intel/common/pch/lockdown/lockdown.c  |  6 ++++--
 src/southbridge/intel/common/finalize.c       |  4 +++-
 src/southbridge/intel/common/spi.c            |  4 +++-
 7 files changed, 57 insertions(+), 6 deletions(-)
 create mode 100644 src/security/lockdown/lockdown.h

diff --git a/src/security/lockdown/Kconfig b/src/security/lockdown/Kconfig
index 95a768a148..ec76cea213 100644
--- a/src/security/lockdown/Kconfig
+++ b/src/security/lockdown/Kconfig
@@ -107,6 +107,14 @@ config BOOTMEDIA_SMM_BWP
 	  while also preventing unauthorized writes through the internal controller.
 	  Note that this breaks flashconsole, since the flash becomes read-only.
 
+config BOOTMEDIA_SMM_BWP_RUNTIME_OPTION
+	bool "Boot media only writable in SMM can be controlled via option API"
+	depends on BOOTMEDIA_SMM_BWP
+	depends on DRIVERS_OPTION_CFR
+	help
+	  Provide a runtime option "bios_lock" to enable or disable SMM BIOS Write Protection
+	  via the option API.
+
 choice
 	prompt "SPI Flash write protection duration"
 	default BOOTMEDIA_SPI_LOCK_REBOOT
diff --git a/src/security/lockdown/lockdown.h b/src/security/lockdown/lockdown.h
new file mode 100644
index 0000000000..b81e636c32
--- /dev/null
+++ b/src/security/lockdown/lockdown.h
@@ -0,0 +1,16 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#ifndef SECURITY_LOCKDOWN_LOCKDOWN_H
+#define SECURITY_LOCKDOWN_LOCKDOWN_H
+
+#include <option.h>
+#include <types.h>
+
+static inline bool enable_smm_bios_protection(void)
+{
+	if (CONFIG(BOOTMEDIA_SMM_BWP_RUNTIME_OPTION))
+		return get_uint_option("bios_lock", CONFIG(BOOTMEDIA_SMM_BWP));
+	return CONFIG(BOOTMEDIA_SMM_BWP);
+}
+
+#endif /* SECURITY_LOCKDOWN_LOCKDOWN_H */
diff --git a/src/soc/intel/common/block/include/intelblocks/cfr.h b/src/soc/intel/common/block/include/intelblocks/cfr.h
index 15dcacab23..e31af7f4c9 100644
--- a/src/soc/intel/common/block/include/intelblocks/cfr.h
+++ b/src/soc/intel/common/block/include/intelblocks/cfr.h
@@ -150,5 +150,24 @@ static const struct sm_object intel_tme = SM_DECLARE_BOOL({
 	.default_value	= CONFIG(INTEL_TME),
 }, WITH_CALLBACK(update_intel_tme));
 
+/* BIOS Lock */
+static void update_smm_bwp(struct sm_object *new)
+{
+	if (!CONFIG(BOOTMEDIA_SMM_BWP_RUNTIME_OPTION))
+		new->sm_bool.flags |= CFR_OPTFLAG_SUPPRESS;
+}
+
+static const struct sm_object bios_lock = SM_DECLARE_ENUM({
+	.opt_name	= "bios_lock",
+	.ui_name	= "BIOS Lock",
+	.ui_helptext	= "Enable BIOS write protection in SMM. When enabled, the boot media"
+			  " (SPI flash) is only writable in System Management Mode, preventing"
+			  " unauthorized writes through the internal controller.",
+	.default_value	= CONFIG(BOOTMEDIA_SMM_BWP),
+	.values		= (const struct sm_enum_value[]) {
+				{ "Disabled",	false	},
+				{ "Enabled",	true	},
+				SM_ENUM_VALUE_END	},
+}, WITH_CALLBACK(update_smm_bwp));
 
 #endif /* SOC_INTEL_CMN_CFR_H */
diff --git a/src/soc/intel/common/block/smm/smihandler.c b/src/soc/intel/common/block/smm/smihandler.c
index cd78de26c3..1af03739d2 100644
--- a/src/soc/intel/common/block/smm/smihandler.c
+++ b/src/soc/intel/common/block/smm/smihandler.c
@@ -20,6 +20,8 @@
 #include <intelblocks/smihandler.h>
 #include <intelblocks/tco.h>
 #include <intelblocks/uart.h>
+#include <option.h>
+#include <security/lockdown/lockdown.h>
 #include <smmstore.h>
 #include <soc/nvs.h>
 #include <soc/pci_devs.h>
@@ -352,7 +354,7 @@ static void finalize(void)
 		/* Re-init SPI driver to handle locked BAR */
 		fast_spi_init();
 
-	if (CONFIG(BOOTMEDIA_SMM_BWP)) {
+	if (enable_smm_bios_protection()) {
 		fast_spi_enable_wp();
 		set_insmm_sts(false);
 	}
@@ -443,7 +445,7 @@ void smihandler_southbridge_tco(
 	fast_spi_clear_sync_smi_status();
 
 	/* If enabled, enforce SMM BIOS write protection */
-	if (CONFIG(BOOTMEDIA_SMM_BWP) && fast_spi_wpd_status()) {
+	if (enable_smm_bios_protection() && fast_spi_wpd_status()) {
 		/*
 		 * BWE is RW, so the SMI was caused by a
 		 * write to BWE, not by a write to the BIOS
diff --git a/src/soc/intel/common/pch/lockdown/lockdown.c b/src/soc/intel/common/pch/lockdown/lockdown.c
index eec3beb01b..ff7ca959fc 100644
--- a/src/soc/intel/common/pch/lockdown/lockdown.c
+++ b/src/soc/intel/common/pch/lockdown/lockdown.c
@@ -8,6 +8,8 @@
 #include <intelblocks/systemagent.h>
 #include <intelpch/lockdown.h>
 #include <intelblocks/gpmr.h>
+#include <option.h>
+#include <security/lockdown/lockdown.h>
 #include <soc/pci_devs.h>
 #include <soc/pcr_ids.h>
 #include <soc/soc_chip.h>
@@ -81,7 +83,7 @@ static void fast_spi_lockdown_cfg(int chipset_lockdown)
 		fast_spi_set_bios_interface_lock_down();
 
 		/* Only allow writes in SMM */
-		if (CONFIG(BOOTMEDIA_SMM_BWP)) {
+		if (enable_smm_bios_protection()) {
 			fast_spi_set_eiss();
 			fast_spi_enable_wp();
 		}
@@ -102,7 +104,7 @@ static void lpc_lockdown_config(int chipset_lockdown)
 		lpc_set_bios_interface_lock_down();
 
 		/* Only allow writes in SMM */
-		if (CONFIG(BOOTMEDIA_SMM_BWP)) {
+		if (enable_smm_bios_protection()) {
 			lpc_set_eiss();
 			lpc_enable_wp();
 		}
diff --git a/src/southbridge/intel/common/finalize.c b/src/southbridge/intel/common/finalize.c
index 490bdae74e..759ab8ea2d 100644
--- a/src/southbridge/intel/common/finalize.c
+++ b/src/southbridge/intel/common/finalize.c
@@ -2,6 +2,8 @@
 
 #include <console/console.h>
 #include <device/pci_ops.h>
+#include <option.h>
+#include <security/lockdown/lockdown.h>
 #include <southbridge/intel/common/pmbase.h>
 #include <southbridge/intel/common/pmutil.h>
 #include <southbridge/intel/common/rcba.h>
@@ -45,7 +47,7 @@ void intel_pch_finalize_smm(void)
 	pci_write_config32(PCI_DEV(0, 27, 0), 0x74,
 		    pci_read_config32(PCI_DEV(0, 27, 0), 0x74));
 
-	if (CONFIG(BOOTMEDIA_SMM_BWP))
+	if (enable_smm_bios_protection())
 		write_pmbase16(SMI_EN, read_pmbase16(SMI_EN) | TCO_EN);
 
 	write_pmbase16(TCO1_CNT, read_pmbase16(TCO1_CNT) | TCO_LOCK);
diff --git a/src/southbridge/intel/common/spi.c b/src/southbridge/intel/common/spi.c
index bcdcaa9158..089e3ce234 100644
--- a/src/southbridge/intel/common/spi.c
+++ b/src/southbridge/intel/common/spi.c
@@ -13,6 +13,8 @@
 #include <console/console.h>
 #include <device/device.h>
 #include <device/pci.h>
+#include <option.h>
+#include <security/lockdown/lockdown.h>
 #include <spi_flash.h>
 #include <spi-generic.h>
 #include <timer.h>
@@ -1116,7 +1118,7 @@ void spi_finalize_ops(void)
 	}
 	writew_(optype, cntlr.optype);
 
-	spi_set_smm_only_flashing(CONFIG(BOOTMEDIA_SMM_BWP));
+	spi_set_smm_only_flashing(enable_smm_bios_protection());
 }
 
 __weak void intel_southbridge_override_spi(struct intel_swseq_spi_config *spi_config)

From dd60a487631f683580736913ee8739f400659608 Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Fri, 19 Dec 2025 20:41:38 +0000
Subject: [PATCH 3200/3886] mb/starlabs/adl: Add StarBook Horizon (N305)

Tested using `edk2` from
`https://github.com/starlabsltd/edk2/tree/uefipayload_vs`:
* Ubuntu 24.04
* Manjaro 24

No known issues.

https://starlabs.systems/pages/starbook-horizon-specification

Change-Id: I7535bc5f49324027eacc9c2750a9abe742fee470
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90570
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 Documentation/mainboard/index.md              |   1 +
 .../mainboard/starlabs/adl_horizon.md         |  86 ++++++
 src/mainboard/starlabs/adl/Kconfig            | 117 ++++++++
 src/mainboard/starlabs/adl/Kconfig.name       |   4 +
 src/mainboard/starlabs/adl/Makefile.mk        |  10 +
 src/mainboard/starlabs/adl/acpi/ec.asl        |   1 +
 src/mainboard/starlabs/adl/acpi/mainboard.asl |   5 +
 src/mainboard/starlabs/adl/acpi/sleep.asl     |  11 +
 src/mainboard/starlabs/adl/acpi/superio.asl   |   1 +
 src/mainboard/starlabs/adl/board_info.txt     |   6 +
 src/mainboard/starlabs/adl/bootblock.c        |  14 +
 src/mainboard/starlabs/adl/cfr.c              | 109 +++++++
 src/mainboard/starlabs/adl/cmos.default       |   6 +
 src/mainboard/starlabs/adl/cmos.layout        |  46 +++
 src/mainboard/starlabs/adl/dsdt.asl           |  47 ++++
 src/mainboard/starlabs/adl/include/variants.h |  17 ++
 src/mainboard/starlabs/adl/mainboard.c        |  22 ++
 src/mainboard/starlabs/adl/spd/Makefile.mk    |   5 +
 .../adl/spd/rs4g32l05d8fdb-5500.spd.hex       |  32 +++
 .../adl/spd/rs4g32l05d8fdb-6400.spd.hex       |  32 +++
 .../adl/spd/rs4g32l05d8fdb-7500.spd.hex       |  32 +++
 .../starlabs/adl/variants/hz/Makefile.mk      |  12 +
 .../starlabs/adl/variants/hz/board.fmd        |  14 +
 .../starlabs/adl/variants/hz/data.vbt         | Bin 0 -> 9216 bytes
 .../adl/variants/hz/data_native_res.vbt       | Bin 0 -> 9216 bytes
 .../starlabs/adl/variants/hz/devicetree.cb    | 240 ++++++++++++++++
 .../starlabs/adl/variants/hz/devtree.c        |  33 +++
 src/mainboard/starlabs/adl/variants/hz/gpio.c | 266 ++++++++++++++++++
 .../starlabs/adl/variants/hz/hda_verb.c       |  97 +++++++
 .../starlabs/adl/variants/hz/ramstage.c       |  19 ++
 .../starlabs/adl/variants/hz/romstage.c       | 102 +++++++
 src/mainboard/starlabs/adl/vboot.c            |   8 +
 32 files changed, 1395 insertions(+)
 create mode 100644 Documentation/mainboard/starlabs/adl_horizon.md
 create mode 100644 src/mainboard/starlabs/adl/Kconfig
 create mode 100644 src/mainboard/starlabs/adl/Kconfig.name
 create mode 100644 src/mainboard/starlabs/adl/Makefile.mk
 create mode 100644 src/mainboard/starlabs/adl/acpi/ec.asl
 create mode 100644 src/mainboard/starlabs/adl/acpi/mainboard.asl
 create mode 100644 src/mainboard/starlabs/adl/acpi/sleep.asl
 create mode 100644 src/mainboard/starlabs/adl/acpi/superio.asl
 create mode 100644 src/mainboard/starlabs/adl/board_info.txt
 create mode 100644 src/mainboard/starlabs/adl/bootblock.c
 create mode 100644 src/mainboard/starlabs/adl/cfr.c
 create mode 100644 src/mainboard/starlabs/adl/cmos.default
 create mode 100644 src/mainboard/starlabs/adl/cmos.layout
 create mode 100644 src/mainboard/starlabs/adl/dsdt.asl
 create mode 100644 src/mainboard/starlabs/adl/include/variants.h
 create mode 100644 src/mainboard/starlabs/adl/mainboard.c
 create mode 100644 src/mainboard/starlabs/adl/spd/Makefile.mk
 create mode 100644 src/mainboard/starlabs/adl/spd/rs4g32l05d8fdb-5500.spd.hex
 create mode 100644 src/mainboard/starlabs/adl/spd/rs4g32l05d8fdb-6400.spd.hex
 create mode 100644 src/mainboard/starlabs/adl/spd/rs4g32l05d8fdb-7500.spd.hex
 create mode 100644 src/mainboard/starlabs/adl/variants/hz/Makefile.mk
 create mode 100644 src/mainboard/starlabs/adl/variants/hz/board.fmd
 create mode 100644 src/mainboard/starlabs/adl/variants/hz/data.vbt
 create mode 100644 src/mainboard/starlabs/adl/variants/hz/data_native_res.vbt
 create mode 100644 src/mainboard/starlabs/adl/variants/hz/devicetree.cb
 create mode 100644 src/mainboard/starlabs/adl/variants/hz/devtree.c
 create mode 100644 src/mainboard/starlabs/adl/variants/hz/gpio.c
 create mode 100644 src/mainboard/starlabs/adl/variants/hz/hda_verb.c
 create mode 100644 src/mainboard/starlabs/adl/variants/hz/ramstage.c
 create mode 100644 src/mainboard/starlabs/adl/variants/hz/romstage.c
 create mode 100644 src/mainboard/starlabs/adl/vboot.c

diff --git a/Documentation/mainboard/index.md b/Documentation/mainboard/index.md
index de731f3048..92aec1173f 100644
--- a/Documentation/mainboard/index.md
+++ b/Documentation/mainboard/index.md
@@ -358,6 +358,7 @@ StarBook Mk V <starlabs/starbook_tgl.md>
 StarBook Mk VI <starlabs/starbook_adl.md>
 StarBook Mk VII (N200) <starlabs/starbook_adl_n.md>
 StarBook Mk VII (165H) <starlabs/starbook_mtl.md>
+StarBook Horizon <starlabs/adl_horizon.md>
 Byte Mk II <starlabs/byte_adl.md>
 StarFighter Mk I <starlabs/starfighter_rpl.md>
 StarFighter Mk II <starlabs/starfighter_mtl.md>
diff --git a/Documentation/mainboard/starlabs/adl_horizon.md b/Documentation/mainboard/starlabs/adl_horizon.md
new file mode 100644
index 0000000000..4d81b7f9fc
--- /dev/null
+++ b/Documentation/mainboard/starlabs/adl_horizon.md
@@ -0,0 +1,86 @@
+# StarBook Mk V
+
+## Specs
+
+- CPU (full processor specs available at <https://ark.intel.com>)
+    - Intel N305 (Alder Lake)
+- EC
+    - ITE IT5570E
+    - Backlit keyboard, with standard PS/2 keycodes and SCI hotkeys
+    - Battery
+    - USB-C PD Charger
+    - Suspend / resume
+- GPU
+    - Intel® Iris® Xe Graphics
+    - GOP driver is recommended, VBT is provided
+    - eDP 13.4-inch 2520x1680 LCD
+    - HDMI video
+    - USB-C DisplayPort video
+- Memory
+    - 32GB LPDD% on-board memory
+- Networking
+    - AX210 2230 WiFi / Bluetooth
+- Sound
+    - Realtek ALC269-VB6
+    - Internal speakers
+    - Internal microphone
+    - Combined headphone / microphone 3.5-mm jack
+    - HDMI audio
+    - USB-C DisplayPort audio
+- Storage
+    - M.2 PCIe SSD
+- USB
+    - 1920x1080 CCD camera
+    - USB 3.1 Gen 2 (left)
+    - USB 3.1 Gen 2 (right)
+    - USB 3.1 Gen 2 Type-A (right)
+
+## Building coreboot
+
+Please follow the [Star Labs build instructions](common/building.md) to build coreboot, using `config.starlabs_adl_horizon` as config file.
+
+### Preliminaries
+
+Prior to building coreboot the following files are required:
+* Intel Flash Descriptor file (descriptor.bin)
+* Intel Management Engine firmware (me.bin)
+* ITE Embedded Controller firmware (ec.bin)
+
+The files listed below are optional:
+- Splash screen image in Windows 3.1 BMP format (Logo.bmp)
+
+These files exist in the correct location in the StarLabsLtd/blobs repo on GitHub which is used in place of the standard 3rdparty/blobs repo.
+
+### Build
+
+The following commands will build a working image:
+
+```bash
+make distclean
+make defconfig KBUILD_DEFCONFIG=configs/config.starlabs_adl_horizon_n
+make
+```
+
+## Flashing coreboot
+
+```{eval-rst}
++---------------------+------------+
+| Type                | Value      |
++=====================+============+
+| Socketed flash      | no         |
++---------------------+------------+
+| Vendor              | Winbond    |
++---------------------+------------+
+| Model               | W25Q256.V  |
++---------------------+------------+
+| Size                | 32 MiB     |
++---------------------+------------+
+| Package             | WSON-8     |
++---------------------+------------+
+| Internal flashing   | yes        |
++---------------------+------------+
+| External flashing   | yes        |
++---------------------+------------+
+```
+
+Please see [here](common/flashing.md) for instructions on how to flash with fwupd.
diff --git a/src/mainboard/starlabs/adl/Kconfig b/src/mainboard/starlabs/adl/Kconfig
new file mode 100644
index 0000000000..adfa25bb8d
--- /dev/null
+++ b/src/mainboard/starlabs/adl/Kconfig
@@ -0,0 +1,117 @@
+config BOARD_STARLABS_ADL_SERIES
+	def_bool n
+	select AZALIA_USE_LEGACY_VERB_TABLE
+	select CSE_DEFAULT_CFR_OPTION_STATE_DISABLED
+	select DRIVERS_EFI_VARIABLE_STORE
+	select DRIVERS_GFX_GENERIC
+	select DRIVERS_I2C_HID
+	select DRIVERS_INTEL_PMC
+	select DRIVERS_OPTION_CFR_ENABLED
+	select EC_STARLABS_MERLIN
+	select HAVE_ACPI_RESUME
+	select HAVE_ACPI_TABLES
+	select HAVE_CMOS_DEFAULT
+	select HAVE_HDA_DMIC
+	select HAVE_OPTION_TABLE
+	select HAVE_SPD_IN_CBFS
+	select INTEL_GMA_HAVE_VBT
+	select INTEL_LPSS_UART_FOR_CONSOLE
+	select MAINBOARD_HAS_TPM2
+	select MEMORY_MAPPED_TPM
+	select NO_UART_ON_SUPERIO
+	select PMC_IPC_ACPI_INTERFACE
+	select SOC_INTEL_ALDERLAKE
+	select SOC_INTEL_COMMON_BLOCK_HDA_VERB
+	select SOC_INTEL_COMMON_BLOCK_TCSS
+	select SOC_INTEL_CRASHLOG
+	select SPD_READ_BY_WORD
+	select SPI_FLASH_WINBOND
+	select SYSTEM_TYPE_LAPTOP
+	select TPM2
+	select TPM_MEASURED_BOOT
+	select VALIDATE_INTEL_DESCRIPTOR
+
+config BOARD_STARLABS_ADL_HORIZON
+	select BOARD_ROMSIZE_KB_16384
+	select BOARD_STARLABS_ADL_SERIES
+	select SOC_INTEL_ALDERLAKE_PCH_N
+
+if BOARD_STARLABS_ADL_HORIZON
+
+config CCD_PORT
+	int
+	default 4
+
+config CONSOLE_SERIAL
+	default n if !EDK2_DEBUG
+
+config D3COLD_SUPPORT
+	default n
+
+config DEVICETREE
+	default "variants/\$(CONFIG_VARIANT_DIR)/devicetree.cb"
+
+config DIMM_SPD_SIZE
+	default 512
+
+config EDK2_BOOTSPLASH_FILE
+	string
+	default "3rdparty/blobs/mainboard/starlabs/Logo.bmp"
+
+config EC_STARLABS_BATTERY_MODEL
+	default "U5266122PV-2S1P"
+
+config EC_STARLABS_BATTERY_TYPE
+	default "LION"
+
+config EC_STARLABS_BATTERY_OEM
+	default "Shenzhen Utility Energy Co., Ltd"
+
+config EC_STARLABS_ITE_BIN_PATH
+	string
+	default "3rdparty/blobs/mainboard/\$(MAINBOARDDIR)/\$(CONFIG_VARIANT_DIR)/ec.bin"
+
+config FMDFILE
+	default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/variants/\$(CONFIG_VARIANT_DIR)/board.fmd"
+
+config IFD_BIN_PATH
+	string
+	default "3rdparty/blobs/mainboard/\$(MAINBOARDDIR)/\$(CONFIG_VARIANT_DIR)/flashdescriptor.bin"
+
+config MAINBOARD_DIR
+	default "starlabs/adl"
+
+config MAINBOARD_FAMILY
+	string
+	default "HZ"
+
+config MAINBOARD_PART_NUMBER
+	default "StarBook Horizon"
+
+config MAINBOARD_SMBIOS_PRODUCT_NAME
+	default "StarBook Horizon"
+
+config ME_BIN_PATH
+	string
+	default "3rdparty/blobs/mainboard/\$(MAINBOARDDIR)/\$(CONFIG_VARIANT_DIR)/intel_me.bin"
+
+config POWER_STATE_DEFAULT_ON_AFTER_FAILURE
+	default n
+
+config SOC_INTEL_CSE_SEND_EOP_EARLY
+	default n
+
+config TPM_PIRQ
+	depends on MAINBOARD_HAS_TPM2
+	default 0x28
+
+config UART_FOR_CONSOLE
+	default 0
+
+config USE_PM_ACPI_TIMER
+	default n
+
+config VARIANT_DIR
+	default "hz"
+
+endif
diff --git a/src/mainboard/starlabs/adl/Kconfig.name b/src/mainboard/starlabs/adl/Kconfig.name
new file mode 100644
index 0000000000..e9af44560e
--- /dev/null
+++ b/src/mainboard/starlabs/adl/Kconfig.name
@@ -0,0 +1,4 @@
+comment "Star Labs StarLite Series"
+
+config BOARD_STARLABS_ADL_HORIZON
+	bool "Star Labs StarBook Horizon (N305)"
diff --git a/src/mainboard/starlabs/adl/Makefile.mk b/src/mainboard/starlabs/adl/Makefile.mk
new file mode 100644
index 0000000000..ad15bbd510
--- /dev/null
+++ b/src/mainboard/starlabs/adl/Makefile.mk
@@ -0,0 +1,10 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
+CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/include
+subdirs-$(CONFIG_HAVE_SPD_IN_CBFS) += ./spd
+subdirs-y += variants/$(VARIANT_DIR)
+
+bootblock-y += bootblock.c
+
+ramstage-$(CONFIG_DRIVERS_OPTION_CFR) += cfr.c
+ramstage-y += mainboard.c
diff --git a/src/mainboard/starlabs/adl/acpi/ec.asl b/src/mainboard/starlabs/adl/acpi/ec.asl
new file mode 100644
index 0000000000..853b0877b3
--- /dev/null
+++ b/src/mainboard/starlabs/adl/acpi/ec.asl
@@ -0,0 +1 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
diff --git a/src/mainboard/starlabs/adl/acpi/mainboard.asl b/src/mainboard/starlabs/adl/acpi/mainboard.asl
new file mode 100644
index 0000000000..34b90af325
--- /dev/null
+++ b/src/mainboard/starlabs/adl/acpi/mainboard.asl
@@ -0,0 +1,5 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+Scope (\_SB) {
+	#include "sleep.asl"
+}
diff --git a/src/mainboard/starlabs/adl/acpi/sleep.asl b/src/mainboard/starlabs/adl/acpi/sleep.asl
new file mode 100644
index 0000000000..7ed74e3514
--- /dev/null
+++ b/src/mainboard/starlabs/adl/acpi/sleep.asl
@@ -0,0 +1,11 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+Method (MPTS, 1, NotSerialized)
+{
+	RPTS (Arg0)
+}
+
+Method (MWAK, 1, NotSerialized)
+{
+	RWAK (Arg0)
+}
diff --git a/src/mainboard/starlabs/adl/acpi/superio.asl b/src/mainboard/starlabs/adl/acpi/superio.asl
new file mode 100644
index 0000000000..853b0877b3
--- /dev/null
+++ b/src/mainboard/starlabs/adl/acpi/superio.asl
@@ -0,0 +1 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
diff --git a/src/mainboard/starlabs/adl/board_info.txt b/src/mainboard/starlabs/adl/board_info.txt
new file mode 100644
index 0000000000..5416db044b
--- /dev/null
+++ b/src/mainboard/starlabs/adl/board_info.txt
@@ -0,0 +1,6 @@
+Vendor name: Star Labs
+Board name: StarBook Horizon
+Category: laptop
+ROM protocol: SPI
+ROM socketed: n
+Flashrom support: y
diff --git a/src/mainboard/starlabs/adl/bootblock.c b/src/mainboard/starlabs/adl/bootblock.c
new file mode 100644
index 0000000000..ca48bb1ab2
--- /dev/null
+++ b/src/mainboard/starlabs/adl/bootblock.c
@@ -0,0 +1,14 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <bootblock_common.h>
+#include <soc/gpio.h>
+#include <variants.h>
+
+void bootblock_mainboard_init(void)
+{
+	const struct pad_config *pads;
+	size_t num;
+
+	pads = variant_early_gpio_table(&num);
+	gpio_configure_pads(pads, num);
+}
diff --git a/src/mainboard/starlabs/adl/cfr.c b/src/mainboard/starlabs/adl/cfr.c
new file mode 100644
index 0000000000..4f920a69f6
--- /dev/null
+++ b/src/mainboard/starlabs/adl/cfr.c
@@ -0,0 +1,109 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <boot/coreboot_tables.h>
+#include <console/cfr.h>
+#include <drivers/option/cfr_frontend.h>
+#include <ec/starlabs/merlin/cfr.h>
+#include <intelblocks/cfr.h>
+#include <common/cfr.h>
+
+static struct sm_obj_form performance_group = {
+	.ui_name = "Performance",
+	.obj_list = (const struct sm_object *[]) {
+		&fan_mode,
+		&memory_speed,
+		&power_profile,
+		NULL
+	},
+};
+
+static struct sm_obj_form processor_group = {
+	.ui_name = "Processor",
+	.obj_list = (const struct sm_object *[]) {
+		&me_state,
+		&me_state_counter,
+		&s0ix_enable,
+		&vtd,
+		NULL
+	},
+};
+
+static struct sm_obj_form power_group = {
+	.ui_name = "Power",
+	.obj_list = (const struct sm_object *[]) {
+		&max_charge,
+		&charging_speed,
+		&power_led,
+		&charge_led,
+		&power_on_after_fail_bool,
+		NULL
+	},
+};
+
+static struct sm_obj_form keyboard_group = {
+	.ui_name = "Keyboard",
+	.obj_list = (const struct sm_object *[]) {
+		&kbl_timeout,
+		&fn_ctrl_swap,
+		NULL
+	},
+};
+
+static struct sm_obj_form devices_group = {
+	.ui_name = "Devices",
+	.obj_list = (const struct sm_object *[]) {
+		&bluetooth,
+		&display_native_res,
+		&gna,
+		&lid_switch,
+		&microphone,
+		&webcam,
+		&wifi,
+		NULL
+	},
+};
+
+static struct sm_obj_form security_group = {
+	.ui_name = "Security",
+	.obj_list = (const struct sm_object *[]) {
+		&bios_lock,
+		&intel_tme,
+		NULL
+	},
+};
+
+static struct sm_obj_form pci_group = {
+	.ui_name = "PCI",
+	.obj_list = (const struct sm_object *[]) {
+		&pciexp_clk_pm,
+		&pciexp_aspm,
+		&pciexp_l1ss,
+		NULL
+	},
+};
+
+static struct sm_obj_form coreboot_group = {
+	.ui_name = "coreboot",
+	.obj_list = (const struct sm_object *[]) {
+		&debug_level,
+		NULL
+	},
+};
+
+static struct sm_obj_form *sm_root[] = {
+	&performance_group,
+	&processor_group,
+	&power_group,
+	&keyboard_group,
+	&devices_group,
+	&security_group,
+	&pci_group,
+	&coreboot_group,
+	NULL
+};
+
+void mb_cfr_setup_menu(struct lb_cfr *cfr_root)
+{
+	starlabs_cfr_register_overrides();
+	cfr_write_setup_menu(cfr_root, sm_root);
+}
diff --git a/src/mainboard/starlabs/adl/cmos.default b/src/mainboard/starlabs/adl/cmos.default
new file mode 100644
index 0000000000..49faae3e6a
--- /dev/null
+++ b/src/mainboard/starlabs/adl/cmos.default
@@ -0,0 +1,6 @@
+## SPDX-License-Identifier: GPL-2.0-only
+# Functions
+fn_lock_state=0x1
+trackpad_state=0x1
+kbl_brightness=0x0
+kbl_state=0x1
diff --git a/src/mainboard/starlabs/adl/cmos.layout b/src/mainboard/starlabs/adl/cmos.layout
new file mode 100644
index 0000000000..ebba7fbd5d
--- /dev/null
+++ b/src/mainboard/starlabs/adl/cmos.layout
@@ -0,0 +1,46 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
+# -----------------------------------------------------------------
+entries
+
+# Bank: 1
+# -----------------------------------------------------------------
+0	120	r	0	reserved_memory
+
+# -----------------------------------------------------------------
+# coreboot config options: ramtop
+304	80	h	0	ramtop
+
+# RTC_BOOT_BYTE (coreboot hardcoded)
+388	4	h	0	reboot_counter
+
+# coreboot config options: cpu
+#400	8	r	0	reserved for century byte
+
+# coreboot config options: check sums
+984	16	h	0	check_sum
+
+# Bank: 2
+# embedded controller settings (outside the checksummed area)
+1024	8	h	1	fn_lock_state
+1032	8	h	1	trackpad_state
+1040	8	h	2	kbl_brightness
+1048	8	h	1	kbl_state
+
+# -----------------------------------------------------------------
+
+enumerations
+
+#ID	value	text
+1	0	Disable
+1	1	Enable
+
+2	0	Off
+2	1	Low
+2	2	High
+2	3	On
+
+# -----------------------------------------------------------------
+checksums
+
+checksum 392 983 984
diff --git a/src/mainboard/starlabs/adl/dsdt.asl b/src/mainboard/starlabs/adl/dsdt.asl
new file mode 100644
index 0000000000..b7783eae63
--- /dev/null
+++ b/src/mainboard/starlabs/adl/dsdt.asl
@@ -0,0 +1,47 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <acpi/acpi.h>
+DefinitionBlock(
+	"dsdt.aml",
+	"DSDT",
+	ACPI_DSDT_REV_2,
+	OEM_ID,
+	ACPI_TABLE_CREATOR,
+	0x20220930
+)
+{
+	#include <acpi/dsdt_top.asl>
+	#include <soc/intel/common/block/acpi/acpi/platform.asl>
+	#include <soc/intel/common/block/acpi/acpi/globalnvs.asl>
+	#include <cpu/intel/common/acpi/cpu.asl>
+
+	Device (\_SB.PCI0)
+	{
+		#include <soc/intel/common/block/acpi/acpi/northbridge.asl>
+		#include <soc/intel/alderlake/acpi/southbridge.asl>
+		#include <soc/intel/alderlake/acpi/tcss.asl>
+
+		#include <drivers/intel/gma/acpi/default_brightness_levels.asl>
+
+		#include <soc/intel/common/block/acpi/acpi/gna.asl>
+
+		/* PS/2 Keyboard */
+		#include <drivers/pc80/pc/ps2_controller.asl>
+	}
+
+	#include <southbridge/intel/common/acpi/sleepstates.asl>
+
+	/* Star Labs EC */
+	#include <ec/starlabs/merlin/acpi/ec.asl>
+
+	Scope (\_SB)
+	{
+		/* HID Driver */
+		#include <ec/starlabs/merlin/acpi/hid.asl>
+
+		/* Suspend Methods */
+		#include <ec/starlabs/merlin/acpi/suspend.asl>
+	}
+
+	#include "acpi/mainboard.asl"
+}
diff --git a/src/mainboard/starlabs/adl/include/variants.h b/src/mainboard/starlabs/adl/include/variants.h
new file mode 100644
index 0000000000..c95d15bd72
--- /dev/null
+++ b/src/mainboard/starlabs/adl/include/variants.h
@@ -0,0 +1,17 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef _BASEBOARD_VARIANTS_H_
+#define _BASEBOARD_VARIANTS_H_
+
+#include <soc/gpio.h>
+
+/*
+ * The next set of functions return the gpio table and fill in the number of
+ * entries for each table.
+ */
+const struct pad_config *variant_gpio_table(size_t *num);
+const struct pad_config *variant_early_gpio_table(size_t *num);
+
+void devtree_update(void);
+
+#endif /* _BASEBOARD_VARIANTS_H_ */
diff --git a/src/mainboard/starlabs/adl/mainboard.c b/src/mainboard/starlabs/adl/mainboard.c
new file mode 100644
index 0000000000..1d2fceae53
--- /dev/null
+++ b/src/mainboard/starlabs/adl/mainboard.c
@@ -0,0 +1,22 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <device/device.h>
+#include <drivers/intel/gma/opregion.h>
+#include <soc/ramstage.h>
+#include <option.h>
+#include <variants.h>
+
+static void init_mainboard(void *chip_info)
+{
+	const struct pad_config *pads;
+	size_t num;
+
+	pads = variant_gpio_table(&num);
+	gpio_configure_pads(pads, num);
+
+	devtree_update();
+}
+
+struct chip_operations mainboard_ops = {
+	.init = init_mainboard,
+};
diff --git a/src/mainboard/starlabs/adl/spd/Makefile.mk b/src/mainboard/starlabs/adl/spd/Makefile.mk
new file mode 100644
index 0000000000..f979c5a066
--- /dev/null
+++ b/src/mainboard/starlabs/adl/spd/Makefile.mk
@@ -0,0 +1,5 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
+SPD_SOURCES = rs4g32l05d8fdb-5500
+SPD_SOURCES += rs4g32l05d8fdb-6400
+SPD_SOURCES += rs4g32l05d8fdb-7500
diff --git a/src/mainboard/starlabs/adl/spd/rs4g32l05d8fdb-5500.spd.hex b/src/mainboard/starlabs/adl/spd/rs4g32l05d8fdb-5500.spd.hex
new file mode 100644
index 0000000000..a52441a71b
--- /dev/null
+++ b/src/mainboard/starlabs/adl/spd/rs4g32l05d8fdb-5500.spd.hex
@@ -0,0 +1,32 @@
+23 10 13 0E 16 2A 91 08 00 00 00 00 09 01 00 00
+00 00 0B 00 00 00 00 00 AE 00 90 A8 90 C0 08 60
+04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 4B 00 50 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 20 20 20 20 20 20 20
+20 20 20 20 20 20 20 20 20 20 20 20 20 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
diff --git a/src/mainboard/starlabs/adl/spd/rs4g32l05d8fdb-6400.spd.hex b/src/mainboard/starlabs/adl/spd/rs4g32l05d8fdb-6400.spd.hex
new file mode 100644
index 0000000000..0969d01568
--- /dev/null
+++ b/src/mainboard/starlabs/adl/spd/rs4g32l05d8fdb-6400.spd.hex
@@ -0,0 +1,32 @@
+23 10 13 0E 16 2A 91 08 00 00 00 00 09 01 00 00
+00 00 0A 00 00 00 00 00 AA 00 90 A8 90 C0 08 60
+04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 20 20 20 20 20 20 20
+20 20 20 20 20 20 20 20 20 20 20 20 20 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
diff --git a/src/mainboard/starlabs/adl/spd/rs4g32l05d8fdb-7500.spd.hex b/src/mainboard/starlabs/adl/spd/rs4g32l05d8fdb-7500.spd.hex
new file mode 100644
index 0000000000..c132efab8c
--- /dev/null
+++ b/src/mainboard/starlabs/adl/spd/rs4g32l05d8fdb-7500.spd.hex
@@ -0,0 +1,32 @@
+23 10 13 0E 16 2A 91 08 00 00 00 00 09 01 00 00
+00 00 08 00 00 00 00 00 AA 00 90 A8 90 C0 08 60
+04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 46 00 42 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 20 20 20 20 20 20 20
+20 20 20 20 20 20 20 20 20 20 20 20 20 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
diff --git a/src/mainboard/starlabs/adl/variants/hz/Makefile.mk b/src/mainboard/starlabs/adl/variants/hz/Makefile.mk
new file mode 100644
index 0000000000..bfea7ef255
--- /dev/null
+++ b/src/mainboard/starlabs/adl/variants/hz/Makefile.mk
@@ -0,0 +1,12 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
+bootblock-y += gpio.c
+
+romstage-y += romstage.c
+
+ramstage-y += devtree.c
+ramstage-y += gpio.c
+ramstage-y += hda_verb.c
+ramstage-y += ramstage.c
+
+$(call add_vbt_to_cbfs, vbt_native_res.bin, data_native_res.vbt)
diff --git a/src/mainboard/starlabs/adl/variants/hz/board.fmd b/src/mainboard/starlabs/adl/variants/hz/board.fmd
new file mode 100644
index 0000000000..2197262237
--- /dev/null
+++ b/src/mainboard/starlabs/adl/variants/hz/board.fmd
@@ -0,0 +1,14 @@
+FLASH	0x1000000 {
+	SI_ALL	0x600000 {
+		SI_DESC			0x1000
+		SI_ME			0x411000
+	}
+	SI_BIOS 0xa00000 {
+		EC@0x0			0x20000
+		RW_MRC_CACHE@0x20000	0x10000
+		SMMSTORE@0x30000	0x80000
+		CONSOLE@0xB0000		0x20000
+		FMAP@0xD0000		0x1000
+		COREBOOT(CBFS)
+	}
+}
diff --git a/src/mainboard/starlabs/adl/variants/hz/data.vbt b/src/mainboard/starlabs/adl/variants/hz/data.vbt
new file mode 100644
index 0000000000000000000000000000000000000000..a2adefc8b2589fa70efa3937551bf02da294487d
GIT binary patch
literal 9216
zcmeHMUrbw782`?_Z7H=#H_&ys;ejn!aKNQ($Oy@9q2Ri~D1Sz}L_^0~mB<D%W|%SA
zHS)lV$$go!#l&hfG5CTHKHEo(F(ET9K4`+5bJ>F?dvl}y&bck6Ft%zo9ZSFFJLkLi
z`_Aut-*-;WIrrZE!yQ9B&=c$$=m{L}st<Eej5MmM{v73I>In4>jsyckfsu}$zRu&E
z*t7IU)#^>67-PHLO`6seIyW63_YKtY-igt%@pxk}e*VqriAf&r4DrC3Gx72G)amJX
zj1LaK9N+@4#MN<OY&^zKTsS)#pK9X((O}J+4mLC&<lO&Kqt@K$*P0GN)7I3|cIa@4
zE7;Z9*BcJ?1cpL=CwSig4~7N<gM(eY9X+Rbc%biSs3SDg6)bV(gwQ!Ld2wp&^*5%u
zud|l>(NDd^l`iwniK)p39vC0z1H$G!ABdliPrV(FHI%pnP?DTBM#NlHnj{E<?skxe
zoTP&}N{*Vy0CRA@q+Di-jmYODhj)D&^r_-HDS<NzPOC;nPS-_NorEiVO$9p}U5k>(
zLxC!fyv>Ld2uZ}iA!le+7ZU7VP1}`Z`i-XTgcqc)a=I?@E~f2DiQqQyCUfm%Z@{~p
zw%b8umv%;Ozrq>O@7HO&G9rhxGjr{vudw?eZ6}(6HuOuYa!_FR`$juj?;q^)q&x4x
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zl^l{<uUV&pT-`RmIy~TV$n(}VkE7szAp?aB6f#iAKp_K#3=}d@$iV-Yfws?-J@m>b
zk)fD)eHEn@win;~<X2Hj!ZH10BCZnikwFpIGV2Yl)ZMrX1DnpgG>13ZHF$C6kf9hT
zSH8geYWqCXXc9IW+TmFilmrXijGZ$NbQLyFj?Vl==vG*S=Ao;}(Jjv?q&qZ42g;(&
zpQF3e%V^lXz`DtVFO|@V2Vuko{&|^^=}3@99GI1BekP$aPbp*+S-M5rK16PPiWE9q
zf>FZ0%))eqX4Pt7TF=-*Ct}bYOXQ_~=wiYeY{j=#UXsx7FA;f3;E^8QsJqZAo0syS
t@WqSR>#5aNpX2A%_b?_-eEP<Z9A)rDeh-lOyx;ge2|A>$Ku>N4{szB+fGz+4

literal 0
HcmV?d00001

diff --git a/src/mainboard/starlabs/adl/variants/hz/data_native_res.vbt b/src/mainboard/starlabs/adl/variants/hz/data_native_res.vbt
new file mode 100644
index 0000000000000000000000000000000000000000..7e4f64ad7fd3cd3eafeb099eab9154b2b97e3e42
GIT binary patch
literal 9216
zcmeHMUrbw782`?_ZRu)}ZlLRM!vkBe;DAfnkP(vI^3QdH(H2I!L_^0~mB<D%W|%SA
zHS)lV$$go!#l&i2V(<kYe727mV?t(Je9(k9=i-AVdvl}y&bck6Ft%zo9ZSFFyXU+2
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z^J%%ZIj7wCheZ{)EN?RpN_*K0luqB+VVHbnpT`-iv1(VfUdG%nWH(o%%7YP-Wt^I$
zd%4f3SVNHWI1t3#^k9Ve9?}C;t9j>IEd+1tWmRqkfM6$^K<L1lymb^>J<W$n)3r&g
zse%v%DhkOxW3Ma-VTOk*J-TNd0yD)jUMRvBO*1Ru%33`-pYws4Vu2^O?pQ3qhhs-|
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zGk3@+jFLj4@O2o;$;JIZs28=YzA)vY>rUEd3m6aA>XOUh*%~c$b@v*AN>2$HnJffB
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z_7E-ivmyTHWs98FEhi4OVk$B*GssDDU0#KlP9K#$A*N&D<#Of(E+*Hq%g-OJK*x#>
z-ikUp$mt)e?QLbWf9$*;hsP0L2l-(xkC-TnE$4Dq%=W_{VYiv}n=Ak4Qm$w6C5NQ8
z>(;IyU$@QgjznAzx!>C6aTMJzW}ujXVg`yCC}yCTfno-V8TcPF(EgdSmtGkqG87Z9
zuVS>q_ThV<{3=Q*IHrG0#8qNGGAIgLX1&3cx|?@lVAGkG=I}<l7B9{mG86;XmCy0M
z+CI-TnuLvpdN|91QedH*v2*5uuF~eo)0saD-3p7+Jan~ry5$*#bcd$sKv}f;^K^Im
z84cSPSTC9Ir3yN65Jp_!pOzV!jwETsfmyZYX9_y=v_eLSrCYS^N95M0NTIVO871w@
zEJRmnR;>Z1b;cGt5rghnA}@uZiwkS872j5QNkM<0ROBUzBR#xPccWG=FBRRw7cXLO
opf+1Wo}bs=L!UVD=^H<Cl*1SKJwWF3e*O0(=#aJ|J-He98_KqSE&u=k

literal 0
HcmV?d00001

diff --git a/src/mainboard/starlabs/adl/variants/hz/devicetree.cb b/src/mainboard/starlabs/adl/variants/hz/devicetree.cb
new file mode 100644
index 0000000000..229ce37de4
--- /dev/null
+++ b/src/mainboard/starlabs/adl/variants/hz/devicetree.cb
@@ -0,0 +1,240 @@
+chip soc/intel/alderlake
+	# FSP UPDs
+	register "eist_enable"			= "true"
+	register "enable_c6dram"		= "true"
+	register "energy_efficient_turbo"	= "true"
+	register "sagv"				= "SaGv_Enabled"
+
+	# Serial I/O
+	register "serial_io_i2c_mode" = "{
+		[PchSerialIoIndexI2C0]		= PchSerialIoSkipInit,
+		[PchSerialIoIndexI2C3]		= PchSerialIoPci,
+	}"
+
+	register "common_soc_config" = "{
+		.i2c[3] = {
+			.speed				= I2C_SPEED_FAST,
+		},
+	}"
+
+	register "serial_io_uart_mode" = "{
+		[PchSerialIoIndexUART0]		= PchSerialIoSkipInit,
+	}"
+
+	# Power
+	register "pch_slp_s3_min_assertion_width"	= "SLP_S3_ASSERTION_1_MS"
+	register "pch_slp_s4_min_assertion_width"	= "SLP_S4_ASSERTION_3S"
+	register "pch_slp_sus_min_assertion_width"	= "SLP_SUS_ASSERTION_1_S"
+	register "pch_slp_a_min_assertion_width"	= "SLP_A_ASSERTION_98_MS"
+
+	device domain 0 on
+		device ref igpu		on
+			chip drivers/gfx/generic
+				register "device_count"		= "6"
+				# [DDIA] eDP
+				register "device[0].name"	= ""LCD0""
+				register "device[0].type"	= "panel"
+				# [DDIB] HDMI
+				register "device[1].name"	= ""DD01""
+				# [TCP0] Type-C
+				register "device[2].name"	= ""DD02""
+				# [TCP1] Type-C
+				register "device[3].name"	= ""DD03""
+				register "device[2].use_pld"	= "true"
+				register "device[2].pld"	= "ACPI_PLD_TYPE_C(LEFT, CENTER, ACPI_PLD_GROUP(0, 1))"
+				# [TCP2] N/A
+				register "device[4].name"	= ""DD04""
+				# [TCP3] N/A
+				register "device[5].name"	= ""DD05""
+				device generic 0 on end
+			end
+
+			register "ddi_portA_config"		= "1"
+			register "ddi_ports_config" = "{
+				[DDI_PORT_A]				= DDI_ENABLE_HPD | DDI_ENABLE_DDC,
+				[DDI_PORT_B]				= DDI_ENABLE_HPD | DDI_ENABLE_DDC,
+			}"
+		end
+		device ref gna		on  end
+		device ref xhci		on
+			# Left Rear USB 2.0 Type-C		3289 mil
+			register "usb2_ports[0]"		= "USB2_PORT_SHORT(OC_SKIP)"
+
+			# Left Front USB 3.0 Type C
+			register "usb2_ports[1]"		= "USB2_PORT_SHORT(OC_SKIP)"
+			register "usb3_ports[3]"		= "USB3_PORT_DEFAULT(OC_SKIP)"
+
+			# Right USB 3.0 Hub
+			register "usb2_ports[6]"		= "USB2_PORT_SHORT(OC_SKIP)"
+			register "usb3_ports[0]"		= "USB3_PORT_DEFAULT(OC_SKIP)"
+
+			# Webcam				3249 mil
+			register "usb2_ports[CONFIG_CCD_PORT]"	= "USB2_PORT_SHORT(OC_SKIP)"
+
+			# Internal Bluetooth			1874 mil
+			register "usb2_ports[9]"		= "USB2_PORT_SHORT(OC_SKIP)"
+
+			chip drivers/usb/acpi
+				device ref xhci_root_hub on
+					chip drivers/usb/acpi
+						register "desc"			= ""Left Back USB Type-C""
+						register "type"			= "UPC_TYPE_C_USB2_ONLY"
+						register "group"		= "ACPI_PLD_GROUP(0, 0)"
+						device ref usb2_port1 on end
+					end
+
+					chip drivers/usb/acpi
+						register "desc"			= ""Left Front USB Type-C""
+						register "type"			= "UPC_TYPE_C_USB2_SS_SWITCH"
+						register "use_custom_pld"	= "true"
+						register "custom_pld"		= "ACPI_PLD_TYPE_C(LEFT, CENTER, ACPI_PLD_GROUP(0, 1))"
+						device ref usb2_port2 on end
+					end
+					chip drivers/usb/acpi
+						register "desc"			= ""Left Front USB Type-C""
+						register "type"			= "UPC_TYPE_C_USB2_SS_SWITCH"
+						register "use_custom_pld"	= "true"
+						register "custom_pld"		= "ACPI_PLD_TYPE_C(LEFT, CENTER, ACPI_PLD_GROUP(0, 1))"
+						device ref usb3_port4 on end
+					end
+
+					chip drivers/usb/acpi
+						register "desc"			= ""Right USB 3.0 Hub""
+						register "type"			= "UPC_TYPE_HUB"
+						register "use_custom_pld"	= "true"
+						register "custom_pld"		= "ACPI_PLD_TYPE_C(RIGHT, CENTER, ACPI_PLD_GROUP(0, 2))"
+						device ref usb2_port7 on end
+					end
+					chip drivers/usb/acpi
+						register "desc"			= ""Right USB 3.0 Hub""
+						register "type"			= "UPC_TYPE_HUB"
+						register "use_custom_pld"	= "true"
+						register "custom_pld"		= "ACPI_PLD_TYPE_C(RIGHT, CENTER, ACPI_PLD_GROUP(0, 2))"
+						device ref usb3_port1 on end
+					end
+
+					chip drivers/usb/acpi
+						register "desc"			= ""Internal Webcam""
+						register "type"			= "UPC_TYPE_INTERNAL"
+						register "group"		= "ACPI_PLD_GROUP(0, 3)"
+						device ref usb2_port5 on end
+					end
+
+					chip drivers/usb/acpi
+						register "desc"			= ""CNVi Bluetooth""
+						register "type"			= "UPC_TYPE_INTERNAL"
+						register "is_intel_bluetooth"	= "1"
+						register "enable_gpio"		= "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_VGPIO_0)"
+						register "reset_gpio"		= "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A13)"
+						register "group"		= "ACPI_PLD_GROUP(0, 4)"
+						device ref usb2_port10 on end
+					end
+				end
+			end
+		end
+		device ref i2c0		on  end
+		device ref i2c3		on
+			chip drivers/i2c/hid
+				register "generic.hid"		= ""STAR0001""
+				register "generic.desc"		= ""Touchpad""
+				register "generic.irq"		= "ACPI_IRQ_LEVEL_LOW(GPP_E12_IRQ)"
+				register "hid_desc_reg_offset"	= "0x20"
+				device i2c 2c on end
+			end
+		end
+		device ref shared_sram	on  end
+                device ref cnvi_wifi	on
+			chip drivers/wifi/generic
+				register "add_acpi_dma_property"	= "true"
+				register "cnvi_enable_gpio"		= "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E3)"
+				register "enable_cnvi_ddr_rfim"		= "true"
+				device generic 0 on end
+			end
+		end
+		device ref pcie_rp9	on				# SSD x4
+			register "pch_pcie_rp[PCH_RP(9)]" = "{
+				.clk_src				= 0,
+				.clk_req				= 0,
+				.flags					= PCIE_RP_LTR | PCIE_RP_AER,
+				.pcie_rp_aspm				= ASPM_L0S_L1,
+				.PcieRpL1Substates			= L1_SS_L1_2,
+				.pcie_rp_detect_timeout_ms		= 50,
+
+			}"
+			smbios_slot_desc				"SlotTypeM2Socket3"
+									"SlotLengthLong"
+									"M.2/M 2280"
+									"SlotDataBusWidth4X"
+			chip soc/intel/common/block/pcie/rtd3
+				register "enable_gpio"			= "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D16)"
+				register "reset_gpio"			= "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_H0)"
+				register "srcclk_pin"			= "0"
+				register "is_storage"			= "true"
+				register "add_acpi_dma_property"	= "true"
+				register "skip_on_off_support"		= "true"
+				register "ext_pm_support"		= "ACPI_PCIE_RP_EMIT_ALL"
+				register "use_rp_mutex"			= "true"
+				device generic 0 on end
+			end
+		end
+		device ref uart0	on  end
+		device ref pch_espi	on
+			register "gen1_dec"			= "0x00040069"
+			register "gen2_dec"			= "0x00fc0201"
+			register "gen3_dec"			= "0x000c0081"
+
+			chip drivers/pc80/tpm
+				device pnp 0c31.0 on end
+			end
+
+			chip ec/starlabs/merlin
+				# Port pair 4Eh/4Fh
+				device pnp 4e.01 off end			# Com 1
+				device pnp 4e.02 off end			# Com 2
+				device pnp 4e.04 off end			# System Wake-Up
+				device pnp 4e.05 off end			# PS/2 Mouse
+				device pnp 4e.06 on				# PS/2 Keyboard
+					io 0x60			= 0x0060
+					io 0x62			= 0x0064
+					irq 0x70		= 1
+				end
+				device pnp 4e.0a off end			# Consumer IR
+				device pnp 4e.0f off end			# Shared Memory/Flash Interface
+				device pnp 4e.10 off end			# RTC-like Timer
+				device pnp 4e.11 off end			# Power Management Channel 1
+				device pnp 4e.12 off end			# Power Management Channel 2
+				device pnp 4e.13 off end			# Serial Peripheral Interface
+				device pnp 4e.14 off end			# Platform EC Interface
+				device pnp 4e.17 off end			# Power Management Channel 3
+				device pnp 4e.18 off end			# Power Management Channel 4
+				device pnp 4e.19 off end			# Power Management Channel 5
+			end
+		end
+		device ref pmc		hidden
+			chip drivers/intel/pmc_mux
+				device generic 0 on
+					chip drivers/intel/pmc_mux/conn
+						use usb2_port2 as usb2_port
+						use usb3_port4 as usb3_port
+						device generic 0 alias conn0 on end
+					end
+					chip drivers/intel/pmc_mux/conn
+						use usb2_port7 as usb2_port
+						use usb3_port1 as usb3_port
+						device generic 1 alias conn1 on end
+					end
+				end
+			end
+		end
+		device ref hda		on
+			subsystemid 0x1e50 0x7038
+			register "pch_hda_sdi_enable[0]"		= "true"
+			register "pch_hda_dsp_enable"			= "true"
+			register "pch_hda_audio_link_hda_enable"	= "true"
+			register "pch_hda_idisp_codec_enable"		= "true"
+			register "pch_hda_idisp_link_frequency"		= "HDA_LINKFREQ_96MHZ"
+			register "pch_hda_idisp_link_tmode"		= "HDA_TMODE_8T"
+		end
+		device ref smbus	on  end
+	end
+end
diff --git a/src/mainboard/starlabs/adl/variants/hz/devtree.c b/src/mainboard/starlabs/adl/variants/hz/devtree.c
new file mode 100644
index 0000000000..3ae2d08956
--- /dev/null
+++ b/src/mainboard/starlabs/adl/variants/hz/devtree.c
@@ -0,0 +1,33 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <chip.h>
+#include <cpu/intel/turbo.h>
+#include <device/device.h>
+#include <device/pci_def.h>
+#include <option.h>
+#include <static.h>
+#include <types.h>
+#include <variants.h>
+#include <common/powercap.h>
+
+void devtree_update(void)
+{
+	config_t *cfg = config_of_soc();
+	update_power_limits(cfg);
+
+	/* Enable/Disable WiFi based on CMOS settings */
+	if (get_uint_option("wifi", 1) == 0)
+		DEV_PTR(cnvi_wifi)->enabled = 0;
+
+	/* Enable/Disable Bluetooth based on CMOS settings */
+	if (get_uint_option("bluetooth", 1) == 0)
+		cfg->usb2_ports[9].enable = 0;
+
+	/* Enable/Disable Webcam based on CMOS settings */
+	if (get_uint_option("webcam", 1) == 0)
+		cfg->usb2_ports[CONFIG_CCD_PORT].enable = 0;
+
+	/* Enable/Disable GNA based on CMOS settings */
+	if (get_uint_option("gna", 0) == 0)
+		DEV_PTR(gna)->enabled = 0;
+}
diff --git a/src/mainboard/starlabs/adl/variants/hz/gpio.c b/src/mainboard/starlabs/adl/variants/hz/gpio.c
new file mode 100644
index 0000000000..a72cc6e157
--- /dev/null
+++ b/src/mainboard/starlabs/adl/variants/hz/gpio.c
@@ -0,0 +1,266 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <variants.h>
+
+/* Early pad configuration in bootblock */
+const struct pad_config early_gpio_table[] = {
+	/* Debug Connector */
+	PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2),				/* RXD */
+	PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2),				/* TXD */
+};
+
+const struct pad_config *variant_early_gpio_table(size_t *num)
+{
+	*num = ARRAY_SIZE(early_gpio_table);
+	return early_gpio_table;
+}
+
+/* Pad configuration in ramstage. */
+const struct pad_config gpio_table[] = {
+	/* General Purpose I/O Deep */
+	PAD_CFG_NF(GPD0, NONE, DEEP, NF1),				/* Battery Low */
+	PAD_CFG_NF(GPD1, NONE, DEEP, NF1),				/* Charger Connected */
+	PAD_CFG_NF(GPD3, UP_20K, DEEP, NF1),				/* Power Button */
+	PAD_CFG_NF(GPD4, NONE, DEEP, NF1),				/* Sleep S3 */
+	PAD_CFG_NF(GPD5, NONE, DEEP, NF1),				/* Sleep S4 */
+	PAD_CFG_NF(GPD8, NONE, DEEP, NF1),				/* Bluetooth Suspend */
+
+	/* eSPI - Configure automatically on reset */
+	// PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_A0, UP_20K, DEEP, NF1),	/* eSPI IO 0 */
+	// PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_A1, UP_20K, DEEP, NF1),	/* eSPI IO 1 */
+	// PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_A2, UP_20K, DEEP, NF1),	/* eSPI IO 2 */
+	// PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_A3, UP_20K, DEEP, NF1),	/* eSPI IO 3 */
+	// PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_A4, UP_20K, DEEP, NF1),	/* eSPI CS 0 */
+	// PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_A9, UP_20K, DEEP, NF1),	/* eSPI Clk */
+	// PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_A10, NONE, DEEP, NF1),	/* eSPI Reset */
+
+	/* Touchpad */
+	PAD_CFG_NF(GPP_B7, NONE, DEEP, NF2),				/* Data */
+	PAD_CFG_NF(GPP_B8, NONE, DEEP, NF2),				/* Clock */
+	PAD_CFG_GPI_APIC_LOW(GPP_E12, NONE, PLTRST),			/* Interrupt */
+
+	/* SSD */
+	PAD_CFG_NF(GPP_D5, NONE, DEEP, NF1),				/* Clock Request 0 */
+	PAD_CFG_GPO(GPP_H0, 1, PLTRST),					/* Reset */
+	PAD_CFG_GPO(GPP_D16, 1, DEEP),					/* Enable */
+
+	/* Wireless */
+	PAD_CFG_NF(GPP_F0, NONE, DEEP, NF1),				/* BRI Data */
+	PAD_CFG_NF(GPP_F1, UP_20K, DEEP, NF1),				/* BRI Response */
+	PAD_CFG_NF(GPP_F2, NONE, DEEP, NF1),				/* RGI Data */
+	PAD_CFG_NF(GPP_F3, UP_20K, DEEP, NF1),				/* RGI Response */
+	PAD_CFG_NF(GPP_F4, NONE, DEEP, NF1),				/* RF Reset */
+	PAD_CFG_NF(GPP_F5, NONE, DEEP, NF2),				/* Modem Clock Request */
+	PAD_CFG_GPO(GPP_E3, 1, DEEP),					/* WiFi RF Kill */
+	PAD_CFG_GPO(GPP_A13, 1, DEEP),					/* Bluetooth RF Kill */
+
+	/* Display */
+	PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1),				/* eDP Hot Plug */
+	PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1),				/* HDMI Hot Plug */
+	PAD_CFG_NF(GPP_H15, NONE, DEEP, NF1),				/* HDMI Clock */
+	PAD_CFG_NF(GPP_H17, NONE, DEEP, NF1),				/* HDMI Data */
+	PAD_CFG_NF(GPP_A20, NONE, DEEP, NF1),				/* TCP1 Hot Plug */
+
+	/* High-Definition Audio */
+	PAD_CFG_NF(GPP_R0, NATIVE, DEEP, NF1),				/* Clock */
+	PAD_CFG_NF(GPP_R1, NATIVE, DEEP, NF1),				/* Sync */
+	PAD_CFG_NF(GPP_R2, NATIVE, DEEP, NF1),				/* Data Output */
+	PAD_CFG_NF(GPP_R3, NATIVE, DEEP, NF1),				/* Data Input */
+	PAD_CFG_NF(GPP_R4, NATIVE, DEEP, NF1),				/* Reset */
+
+	/* PCH */
+	PAD_CFG_NF(GPP_H18, NONE, DEEP, NF1),				/* C10 Gate */
+	PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1),				/* Platform Reset */
+	PAD_CFG_NF(GPP_B0, NONE, DEEP, NF1),				/* Vendor ID 0 */
+	PAD_CFG_NF(GPP_B1, NONE, DEEP, NF1),				/* Vendor ID 1 */
+	PAD_CFG_GPI_SCI(GPP_B2, NONE, PLTRST, EDGE_SINGLE, INVERT),	/* Processor Hot */
+
+	/* TPM */
+	PAD_CFG_GPI_APIC_LOW(GPP_E2, NONE, PLTRST),			/* Interrupt */
+
+	/* SMBus */
+	PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1),				/* Clock */
+	PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1),				/* Data */
+	PAD_CFG_GPO(GPP_E8, 1, DEEP),					/* DRAM Sleep */
+
+	/* Config Straps									[ Low      / High     ] */
+	PAD_CFG_GPO(GPP_B14, 0, PLTRST),				/* Top Swap		[ Disabled / Enabled  ] */
+	PAD_CFG_GPO(GPP_B18, 0, PLTRST),				/* Reboot Support	[ Enabled  / Disabled ] */
+	PAD_CFG_GPO(GPP_C2, 1, PLTRST),					/* TLS Confidentiality	[ Disabled / Enabled  ] */
+	PAD_CFG_GPO(GPP_C5, 0, PLTRST),					/* eSPI			[ Enabled  / Disabled ] */
+	PAD_CFG_GPO(GPP_E6, 0, PLTRST),					/* JTAG ODT		[ Disabled / Enabled  ] */
+	PAD_CFG_GPO(GPP_H1, 0, PLTRST),					/* BFX Strap 2 Bit 3	[ Disabled / Enabled  ] */
+	PAD_CFG_GPO(GPP_E19, 0, PLTRST),				/* TBT LSX #0		[ 1.8V     / 3.3V     ] */
+	PAD_CFG_GPO(GPP_E21, 0, PLTRST),				/* TBT LSX #1           [ 1.8V     / 3.3V     ] */
+	PAD_CFG_GPO(GPP_D10, 0, PLTRST),				/* TBT LSX #2		[ 1.8V     / 3.3V     ] */
+	PAD_CFG_GPO(GPP_D12, 0, PLTRST),				/* TBT LSX #3		[ 1.8V     / 3.3V     ] */
+	PAD_CFG_GPO(GPP_F7, 0, PLTRST),					/* MCRO LDO		[ Disabled / Bypass   ] */
+	PAD_CFG_GPO(GPD7, 0, PLTRST),					/* RTC Clock Delay	[ Disabled / 95ms     ] */
+
+	PAD_NC(GPD2, NONE),
+	PAD_NC(GPD6, NONE),
+	PAD_NC(GPD9, NONE),
+	PAD_NC(GPD10, NONE),
+	PAD_NC(GPD11, NONE),
+
+	PAD_NC(GPP_A5, NONE),
+	PAD_NC(GPP_A6, NONE),
+	PAD_NC(GPP_A7, NONE),
+	PAD_NC(GPP_A8, NONE),
+	PAD_NC(GPP_A11, NONE),
+	PAD_NC(GPP_A12, NONE),
+	PAD_NC(GPP_A14, NONE),
+	PAD_NC(GPP_A15, NONE),
+	PAD_NC(GPP_A16, NONE),
+	PAD_NC(GPP_A17, NONE),
+	PAD_NC(GPP_A19, NONE),
+	PAD_NC(GPP_A21, NONE),
+	PAD_NC(GPP_A22, NONE),
+	PAD_NC(GPP_A23, NONE),
+
+	PAD_NC(GPP_B3, NONE),
+	PAD_NC(GPP_B4, NONE),
+	PAD_NC(GPP_B5, NONE),
+	PAD_NC(GPP_B6, NONE),
+	PAD_NC(GPP_B9, NONE),
+	PAD_NC(GPP_B10, NONE),
+	PAD_NC(GPP_B11, NONE),
+	PAD_NC(GPP_B12, NONE),
+	PAD_NC(GPP_B15, NONE),
+	PAD_NC(GPP_B16, NONE),
+	PAD_NC(GPP_B17, NONE),
+	PAD_NC(GPP_B19, NONE),
+	PAD_NC(GPP_B20, NONE),
+	PAD_NC(GPP_B21, NONE),
+	PAD_NC(GPP_B22, NONE),
+	PAD_NC(GPP_B23, NONE),
+	PAD_NC(GPP_B24, NONE),
+	PAD_NC(GPP_B25, NONE),
+
+	PAD_NC(GPP_C3, NONE),
+	PAD_NC(GPP_C4, NONE),
+	PAD_NC(GPP_C6, NONE),
+	PAD_NC(GPP_C7, NONE),
+	PAD_NC(GPP_C8, NONE),
+	PAD_NC(GPP_C9, NONE),
+	PAD_NC(GPP_C10, NONE),
+	PAD_NC(GPP_C11, NONE),
+	PAD_NC(GPP_C12, NONE),
+	PAD_NC(GPP_C13, NONE),
+	PAD_NC(GPP_C14, NONE),
+	PAD_NC(GPP_C15, NONE),
+	PAD_NC(GPP_C16, NONE),
+	PAD_NC(GPP_C17, NONE),
+	PAD_NC(GPP_C18, NONE),
+	PAD_NC(GPP_C19, NONE),
+	PAD_NC(GPP_C20, NONE),
+	PAD_NC(GPP_C21, NONE),
+	PAD_NC(GPP_C22, NONE),
+	PAD_NC(GPP_C23, NONE),
+
+	PAD_NC(GPP_D0, NONE),
+	PAD_NC(GPP_D1, NONE),
+	PAD_NC(GPP_D2, NONE),
+	PAD_NC(GPP_D3, NONE),
+	PAD_NC(GPP_D4, NONE),
+	PAD_NC(GPP_D6, NONE),
+	PAD_NC(GPP_D7, NONE),
+	PAD_NC(GPP_D8, NONE),
+	PAD_NC(GPP_D9, NONE),
+	PAD_NC(GPP_D11, NONE),
+	PAD_NC(GPP_D13, NONE),
+	PAD_NC(GPP_D14, NONE),
+	PAD_NC(GPP_D15, NONE),
+	PAD_NC(GPP_D17, NONE),
+	PAD_NC(GPP_D18, NONE),
+	PAD_NC(GPP_D19, NONE),
+
+	PAD_NC(GPP_E0, NONE),
+	PAD_NC(GPP_E1, NONE),
+	PAD_NC(GPP_E4, NONE),
+	PAD_NC(GPP_E5, NONE),
+	PAD_NC(GPP_E7, NONE),
+	PAD_NC(GPP_E9, NONE),
+	PAD_NC(GPP_E10, NONE),
+	PAD_NC(GPP_E13, NONE),
+	PAD_NC(GPP_E15, NONE),
+	PAD_NC(GPP_E16, NONE),
+	PAD_NC(GPP_E17, NONE),
+	PAD_NC(GPP_E18, NONE),
+	PAD_NC(GPP_E20, NONE),
+	PAD_NC(GPP_E21, NONE),
+	PAD_NC(GPP_E22, NONE),
+	PAD_NC(GPP_E23, NONE),
+
+	PAD_NC(GPP_F6, NONE),
+	PAD_NC(GPP_F8, NONE),
+	PAD_NC(GPP_F9, NONE),
+	PAD_NC(GPP_F10, NONE),
+	PAD_NC(GPP_F11, NONE),
+	PAD_NC(GPP_F12, NONE),
+	PAD_NC(GPP_F13, NONE),
+	PAD_NC(GPP_F14, NONE),
+	PAD_NC(GPP_F15, NONE),
+	PAD_NC(GPP_F16, NONE),
+	PAD_NC(GPP_F17, NONE),
+	PAD_NC(GPP_F18, NONE),
+	PAD_NC(GPP_F19, NONE),
+	PAD_NC(GPP_F20, NONE),
+	PAD_NC(GPP_F21, NONE),
+	PAD_NC(GPP_F22, NONE),
+	PAD_NC(GPP_F23, NONE),
+
+	PAD_NC(GPP_H2, NONE),
+	PAD_NC(GPP_H3, NONE),
+	PAD_NC(GPP_H4, NONE),
+	PAD_NC(GPP_H5, NONE),
+	PAD_NC(GPP_H6, NONE),
+	PAD_NC(GPP_H7, NONE),
+	PAD_NC(GPP_H8, NONE),
+	PAD_NC(GPP_H9, NONE),
+	PAD_NC(GPP_H12, NONE),
+	PAD_NC(GPP_H13, NONE),
+	PAD_NC(GPP_H14, NONE),
+	PAD_NC(GPP_H16, NONE),
+	PAD_NC(GPP_H19, NONE),
+	PAD_NC(GPP_H20, NONE),
+	PAD_NC(GPP_H21, NONE),
+	PAD_NC(GPP_H22, NONE),
+	PAD_NC(GPP_H23, NONE),
+
+	PAD_NC(GPP_S0, NONE),
+	PAD_NC(GPP_S1, NONE),
+	PAD_NC(GPP_S2, NONE),
+	PAD_NC(GPP_S3, NONE),
+	PAD_NC(GPP_S4, NONE),
+	PAD_NC(GPP_S5, NONE),
+	PAD_NC(GPP_S6, NONE),
+	PAD_NC(GPP_S7, NONE),
+
+	PAD_NC(GPP_T0, NONE),
+	PAD_NC(GPP_T1, NONE),
+	PAD_NC(GPP_T2, NONE),
+	PAD_NC(GPP_T3, NONE),
+	PAD_NC(GPP_T4, NONE),
+	PAD_NC(GPP_T5, NONE),
+	PAD_NC(GPP_T6, NONE),
+	PAD_NC(GPP_T7, NONE),
+	PAD_NC(GPP_T8, NONE),
+	PAD_NC(GPP_T9, NONE),
+	PAD_NC(GPP_T10, NONE),
+	PAD_NC(GPP_T11, NONE),
+	PAD_NC(GPP_T12, NONE),
+	PAD_NC(GPP_T13, NONE),
+	PAD_NC(GPP_T14, NONE),
+	PAD_NC(GPP_T15, NONE),
+
+	PAD_NC(GPP_R5, NONE),
+	PAD_NC(GPP_R6, NONE),
+	PAD_NC(GPP_R7, NONE),
+};
+
+const struct pad_config *variant_gpio_table(size_t *num)
+{
+	*num = ARRAY_SIZE(gpio_table);
+	return gpio_table;
+}
diff --git a/src/mainboard/starlabs/adl/variants/hz/hda_verb.c b/src/mainboard/starlabs/adl/variants/hz/hda_verb.c
new file mode 100644
index 0000000000..813c0f0458
--- /dev/null
+++ b/src/mainboard/starlabs/adl/variants/hz/hda_verb.c
@@ -0,0 +1,97 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <device/azalia_device.h>
+#include <device/azalia_codec/realtek.h>
+
+const u32 cim_verb_data[] = {
+	/* coreboot specific header */
+	0x10ec0269,	/* Codec Vendor / Device ID: Realtek ALC269 */
+	0x1e507038,	/* Subsystem ID */
+	18,		/* Number of verb entries */
+
+	/* Reset Codec First */
+	AZALIA_RESET(0x1),
+
+	/* HDA Codec Subsystem ID */
+	AZALIA_SUBVENDOR(0, 0x1e507038),
+
+	/* Pin Widget Verb-table */
+	AZALIA_PIN_CFG(0, ALC269_DMIC12,	AZALIA_PIN_DESC(
+							AZALIA_INTEGRATED,
+							AZALIA_MOBILE_LID_INSIDE,
+							AZALIA_MIC_IN,
+							AZALIA_OTHER_DIGITAL,
+							AZALIA_COLOR_UNKNOWN,
+							AZALIA_NO_JACK_PRESENCE_DETECT,
+							3,
+							0
+						)),
+	AZALIA_PIN_CFG(0, ALC269_SPEAKERS,	AZALIA_PIN_DESC(
+							AZALIA_INTEGRATED,
+							AZALIA_INTERNAL | AZALIA_FRONT,
+							AZALIA_SPEAKER,
+							AZALIA_OTHER_ANALOG,
+							AZALIA_COLOR_UNKNOWN,
+							AZALIA_NO_JACK_PRESENCE_DETECT,
+							1,
+							0
+						)),
+	AZALIA_PIN_CFG(0, ALC269_VC_HP_OUT,	AZALIA_PIN_DESC(
+							AZALIA_JACK,
+							AZALIA_EXTERNAL_PRIMARY_CHASSIS | AZALIA_RIGHT,
+							AZALIA_HP_OUT,
+							AZALIA_STEREO_MONO_1_8,
+							AZALIA_BLACK,
+							AZALIA_JACK_PRESENCE_DETECT,
+							2,
+							0
+						)),
+	AZALIA_PIN_CFG(0, ALC269_MIC1,		AZALIA_PIN_DESC(
+							AZALIA_JACK,
+							AZALIA_EXTERNAL_PRIMARY_CHASSIS | AZALIA_RIGHT,
+							AZALIA_MIC_IN,
+							AZALIA_STEREO_MONO_1_8,
+							AZALIA_BLACK,
+							AZALIA_JACK_PRESENCE_DETECT,
+							4,
+							0
+						)),
+	AZALIA_PIN_CFG(0, ALC269_MONO,		AZALIA_PIN_CFG_NC(0)),
+	AZALIA_PIN_CFG(0, ALC269_MIC2,		AZALIA_PIN_CFG_NC(0)),
+	AZALIA_PIN_CFG(0, ALC269_LINE1,		AZALIA_PIN_CFG_NC(0)),
+	AZALIA_PIN_CFG(0, ALC269_LINE2,		AZALIA_PIN_CFG_NC(0)),
+	AZALIA_PIN_CFG(0, ALC269_PC_BEEP,	AZALIA_PIN_CFG_NC(0)),
+	AZALIA_PIN_CFG(0, ALC269_SPDIF_OUT,	AZALIA_PIN_CFG_NC(0)),
+	AZALIA_PIN_CFG(0, ALC269_VB_HP_OUT,	AZALIA_PIN_CFG_NC(0)),
+
+	/* ALC269 Default 1 */
+	0x02050018,
+	0x02040184,
+	0x0205001c,
+	0x02044800,
+	/* ALC269 Default 2 */
+	0x02050024,
+	0x02040000,
+	0x02050004,
+	0x02040080,
+	/* ALC269 Default 3 */
+	0x02050008,
+	0x02040000,
+	0x0205000c,
+	0x02043f00,
+	/* ALC269 Default 4 */
+	0x02050015,
+	0x02048002,
+	0x02050015,
+	0x02048002,
+	/* Widget 0x0c */
+	0x00c37080,
+	0x00270610,
+	0x00d37080,
+	0x00370610,
+};
+
+const u32 pc_beep_verbs[] = {
+};
+
+AZALIA_ARRAY_SIZES;
diff --git a/src/mainboard/starlabs/adl/variants/hz/ramstage.c b/src/mainboard/starlabs/adl/variants/hz/ramstage.c
new file mode 100644
index 0000000000..370f5c8769
--- /dev/null
+++ b/src/mainboard/starlabs/adl/variants/hz/ramstage.c
@@ -0,0 +1,19 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <drivers/intel/gma/opregion.h>
+#include <soc/ramstage.h>
+#include <option.h>
+#include <common/pin_mux.h>
+
+void mainboard_silicon_init_params(FSP_S_CONFIG *supd)
+{
+	configure_pin_mux(supd);
+}
+
+const char *mainboard_vbt_filename(void)
+{
+	if (get_uint_option("display_native_res", 0) == 1)
+		return "vbt_native_res.bin";
+
+	return "vbt.bin";
+}
diff --git a/src/mainboard/starlabs/adl/variants/hz/romstage.c b/src/mainboard/starlabs/adl/variants/hz/romstage.c
new file mode 100644
index 0000000000..9162509387
--- /dev/null
+++ b/src/mainboard/starlabs/adl/variants/hz/romstage.c
@@ -0,0 +1,102 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <option.h>
+#include <soc/meminit.h>
+#include <soc/romstage.h>
+#include <types.h>
+
+void mainboard_memory_init_params(FSPM_UPD *mupd)
+{
+	const struct mb_cfg mem_config = {
+		.type = MEM_TYPE_LP5X,
+
+		.lpx_dq_map = {
+			.ddr0 = {
+				.dq0	= {	10,	14,	13,	12,	9,	11,	15,	8	},
+				.dq1	= {	4,	1,	7,	3,	5,	0,	2,	6	},
+			},
+			.ddr1 = {
+				.dq0	= {	2,	7,	6,	0,	1,	3,	5,	4	},
+				.dq1	= {	13,	11,	9,	8,	10,	14,	12,	15	},
+			},
+			.ddr2 = {
+				.dq0	= {	7,	0,	1,	6,	4,	5,	2,	3	},
+				.dq1	= {	8,	10,	9,	11,	15,	13,	12,	14	},
+			},
+			.ddr3 = {
+				.dq0	= {	2,	0,	3,	1,	4,	5,	7,	6	},
+				.dq1	= {	10,	9,	14,	11,	12,	13,	15,	8	},
+			},
+			.ddr4 = {
+				.dq0	= {	3,	2,	1,	0,	7,	4,	6,	5	},
+				.dq1	= {	8,	10,	11,	9,	14,	13,	12,	15	},
+			},
+			.ddr5 = {
+				.dq0	= {	8,	9,	10,	11,	12,	13,	14,	15	},
+				.dq1	= {	7,	6,	5,	4,	3,	2,	1,	0	},
+			},
+			.ddr6 = {
+				.dq0	= {	13,	12,	15,	14,	9,	8,	11,	10	},
+				.dq1	= {	5,	4,	7,	6,	3,	1,	2,	0	},
+			},
+			.ddr7 = {
+				.dq0	= {	3,	1,	2,	0,	4,	6,	5,	7	},
+				.dq1	= {	15,	12,	9,	8,	11,	10,	13,	14	},
+			},
+		},
+		.lpx_dqs_map = {
+			.ddr0 =	{
+				.dqs0	= 1,
+				.dqs1	= 0,
+			},
+			.ddr1 =	{
+				.dqs0	= 0,
+				.dqs1	= 1,
+			},
+			.ddr2 =	{
+				.dqs0	= 0,
+				.dqs1	= 1,
+			},
+			.ddr3 =	{
+				.dqs0	= 0,
+				.dqs1	= 1,
+			},
+			.ddr4 =	{
+				.dqs0	= 1,
+				.dqs1	= 0,
+			},
+			.ddr5 =	{
+				.dqs0	= 0,
+				.dqs1	= 1,
+			},
+			.ddr6 =	{
+				.dqs0	= 0,
+				.dqs1	= 1,
+			},
+			.ddr7 =	{
+				.dqs0	= 1,
+				.dqs1	= 0,
+			}
+		},
+
+		.ect			= true,
+		.UserBd			= BOARD_TYPE_ULT_ULX,
+		.LpDdrDqDqsReTraining	= true,
+
+		.lp5x_config = {
+			.ccc_config	= 0x00,
+		}
+	};
+
+	const bool half_populated = true;
+
+	const struct mem_spd lpddr5_spd_info = {
+		.topo = MEM_TOPO_MEMORY_DOWN,
+		.cbfs_index = get_uint_option("memory_speed", 1),
+	};
+
+	memcfg_init(mupd, &mem_config, &lpddr5_spd_info, half_populated);
+
+	const uint8_t vtd = get_uint_option("vtd", 1);
+	mupd->FspmConfig.VtdDisable = !vtd;
+};
diff --git a/src/mainboard/starlabs/adl/vboot.c b/src/mainboard/starlabs/adl/vboot.c
new file mode 100644
index 0000000000..8511825004
--- /dev/null
+++ b/src/mainboard/starlabs/adl/vboot.c
@@ -0,0 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <bootmode.h>
+
+int get_recovery_mode_switch(void)
+{
+	return 0;
+}

From 9d262b9e2d48d04ee537f33da52baa7f0bb17426 Mon Sep 17 00:00:00 2001
From: Pranava Y N <pranavayn@google.com>
Date: Thu, 29 Jan 2026 19:59:36 +0530
Subject: [PATCH 3201/3886] mb/starlabs/common: Define type for Kconfigs

Define `BOOTMEDIA_SMM_BWP`, `BOOTMEDIA_SMM_PWP_RUNTIME_OPTION` and
`DRIVERS_EFI_FW_INFO` Kconfig type as bool to satisfy Kconfig lint
requirements.

TEST=None

Change-Id: Ie798378665e6bd3e00ce271e17b36e81df92e2ad
Signed-off-by: Pranava Y N <pranavayn@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90997
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-by: Jon Murphy <jpmurphy@google.com>
---
 src/mainboard/starlabs/common/Kconfig | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/src/mainboard/starlabs/common/Kconfig b/src/mainboard/starlabs/common/Kconfig
index e4361dea5f..f5496b05c0 100644
--- a/src/mainboard/starlabs/common/Kconfig
+++ b/src/mainboard/starlabs/common/Kconfig
@@ -5,13 +5,13 @@ if VENDOR_STARLABS
 menu "Star Labs Settings"
 
 config BOOTMEDIA_SMM_BWP
-	default y
+	def_bool y
 
 config BOOTMEDIA_SMM_BWP_RUNTIME_OPTION
-	default y
+	def_bool y
 
 config DRIVERS_EFI_FW_INFO
-	default y
+	def_bool y
 
 config MB_COMMON_DIR
 	string

From 6fa7f0cba485117e855298707d5afd0314fe6933 Mon Sep 17 00:00:00 2001
From: Yang Wu <wuyang5@huaqin.corp-partner.google.com>
Date: Thu, 29 Jan 2026 11:56:14 +0800
Subject: [PATCH 3202/3886] drivers/mipi: Fix flicker on TM_TL121BVMS07_00C by
 tuning RX params

Display flickering and occasional corruption were observed during panel
initialization on some TM_TL121BVMS07_00C panels when using an EMI-type
FPC.

According to Ilitek, this is caused by insufficient RX margin under
higher EMI conditions. Increasing receiver EQ, mask, bias, and voltage
settings improves signal tolerance and stabilizes display output.

Update the panel initialization code with the following parameters:

EQ:
  P6_8F = 0xF0
Mask:
  P8_82 = 0x13
  P8_7D = 0x84
  P8_7F = 0xDA
Bias:
  P6_90 = 0x55
Voltage:
  P5_3F = 0x47

Datasheet: Preliminary+specification+TL121BVMS07+-00+V01+20250721.pdf

BUG=b:479436242
TEST=build and check firmware screen.
BRANCH=skywalker

Change-Id: Id8272103abfb94f4d4f4d915107eafb9d0f4edc9
Signed-off-by: Yang Wu <wuyang5@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90983
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
---
 src/drivers/mipi/panel-TM_TL121BVMS07_00C.c | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/src/drivers/mipi/panel-TM_TL121BVMS07_00C.c b/src/drivers/mipi/panel-TM_TL121BVMS07_00C.c
index cbc93804c8..52b3e1ff1f 100644
--- a/src/drivers/mipi/panel-TM_TL121BVMS07_00C.c
+++ b/src/drivers/mipi/panel-TM_TL121BVMS07_00C.c
@@ -22,6 +22,14 @@ struct panel_serializable_data TM_TL121BVMS07_00C = {
 		PANEL_DELAY(24),
 		PANEL_DCS(0xFF, 0x5A, 0xA5, 0x06),
 		PANEL_DCS(0x3E, 0x62),
+		PANEL_DCS(0x90, 0x55),
+		PANEL_DCS(0x8F, 0xF0),
+		PANEL_DCS(0xFF, 0x5A, 0xA5, 0x08),
+		PANEL_DCS(0x82, 0x13),
+		PANEL_DCS(0x7D, 0x84),
+		PANEL_DCS(0x7F, 0xDA),
+		PANEL_DCS(0xFF, 0x5A, 0xA5, 0x05),
+		PANEL_DCS(0x3F, 0x47),
 		PANEL_DCS(0xFF, 0x5A, 0xA5, 0x02),
 		PANEL_DCS(0x1B, 0x20),
 		PANEL_DCS(0x5D, 0x00),

From 57c6f5e995345d92418d3a1d36bcc9e41c15d9e5 Mon Sep 17 00:00:00 2001
From: Subrata Banik <subratabanik@google.com>
Date: Wed, 28 Jan 2026 06:35:12 +0000
Subject: [PATCH 3203/3886] ec/google/chromeec: Add helper for critical battery
 state detection

Implement google_chromeec_is_critically_low_on_battery() to check if
the system is at risk of an imminent power-off.

This function returns true only if the battery is below the critical
threshold and no charger is detected. Combining these checks into a
single helper ensures that firmware notifications (like a red
lightbar) or emergency power-down logic do not trigger while the
device is successfully connected to AC power.

- Implement google_chromeec_is_critically_low_on_battery in ec.c.
- Export the function in ec.h for use in romstage/ramstage.

TEST=Verified on Fatcat & Bluey that the function correctly identifies
the low-power state and suppresses warnings when a charger is plugged
in.

Change-Id: I9f0f268d6660d913f989a9deffa24ab1f585b508
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90963
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Jayvik Desai <jayvik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/ec/google/chromeec/ec.c | 11 +++++++++++
 src/ec/google/chromeec/ec.h |  7 +++++++
 2 files changed, 18 insertions(+)

diff --git a/src/ec/google/chromeec/ec.c b/src/ec/google/chromeec/ec.c
index b9d53e7788..804bda0c81 100644
--- a/src/ec/google/chromeec/ec.c
+++ b/src/ec/google/chromeec/ec.c
@@ -1981,3 +1981,14 @@ int google_chromeec_set_lightbar_rgb(unsigned int led, int red, int green,
 
 	return google_chromeec_command(&cmd);
 }
+
+/*
+ * Check if the battery is critically low and not currently charging.
+ *
+ * Return true if battery is below threshold and AC is not present.
+ */
+bool google_chromeec_is_critically_low_on_battery(void)
+{
+	return google_chromeec_is_below_critical_threshold() &&
+	       !google_chromeec_is_charger_present();
+}
diff --git a/src/ec/google/chromeec/ec.h b/src/ec/google/chromeec/ec.h
index e5a4b0647d..075694bd4a 100644
--- a/src/ec/google/chromeec/ec.h
+++ b/src/ec/google/chromeec/ec.h
@@ -562,4 +562,11 @@ int google_chromeec_read_batt_state_of_charge(uint32_t *state);
 int google_chromeec_set_lightbar_rgb(unsigned int led, int red, int green,
 			 int blue);
 
+/*
+ * Check if the battery is critically low and AC is not present.
+ *
+ * Return true if battery is below threshold and AC is not present.
+ */
+bool google_chromeec_is_critically_low_on_battery(void);
+
 #endif /* _EC_GOOGLE_CHROMEEC_EC_H */

From e13c79a31e95796f1eea1f5900f0e2201d51e1f3 Mon Sep 17 00:00:00 2001
From: Subrata Banik <subratabanik@google.com>
Date: Thu, 29 Jan 2026 22:41:12 +0530
Subject: [PATCH 3204/3886] arch/x86: Add pre- and post-memory platform hooks
 to romstage
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Introduce platform_romstage_pre_mem() and platform_romstage_post_mem()
as weak symbols in the x86 romstage cycle.

These hooks allow SoCs and mainboards to execute low-level setup or
instrumentation immediately before and after memory initialization
without modifying the core romstage.c flow.

- platform_romstage_pre_mem: Called before mainboard_romstage_entry.
- platform_romstage_post_mem: Called after memory is up but while still
  running on the Cache-as-RAM (CAR) stack.

Change-Id: I59cb115de0d512106d9a029d683c10b025076893
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90999
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Reviewed-by: Pranava Y N <pranavayn@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/arch/x86/include/arch/romstage.h | 13 +++++++++++++
 src/cpu/intel/car/romstage.c         | 15 +++++++++++++++
 2 files changed, 28 insertions(+)

diff --git a/src/arch/x86/include/arch/romstage.h b/src/arch/x86/include/arch/romstage.h
index 063d4edd6b..e0e82fd96e 100644
--- a/src/arch/x86/include/arch/romstage.h
+++ b/src/arch/x86/include/arch/romstage.h
@@ -7,6 +7,19 @@
 #include <stdint.h>
 #include <cpu/x86/mtrr.h>
 
+/*
+ * Platform-specific hooks for logic surrounding memory initialization.
+ *
+ * platform_romstage_pre_mem() is invoked before memory training.
+ *
+ * platform_romstage_post_mem() is invoked after DRAM is initialized but
+ * before the transition to the RAM-based stack (Post-CAR).
+ *
+ * Default: No-op. These are weak symbols to be overridden by SoC or mainboard.
+ */
+void platform_romstage_pre_mem(void);
+void platform_romstage_post_mem(void);
+
 void mainboard_romstage_entry(void);
 
 /*
diff --git a/src/cpu/intel/car/romstage.c b/src/cpu/intel/car/romstage.c
index 285c2f48b2..f0a55f14b3 100644
--- a/src/cpu/intel/car/romstage.c
+++ b/src/cpu/intel/car/romstage.c
@@ -16,6 +16,19 @@
    following as a guideline for acceptable stack usage. */
 #define DCACHE_RAM_ROMSTAGE_STACK_SIZE 0x2000
 
+/*
+ * Platform-specific hooks for logic surrounding memory initialization.
+ *
+ * platform_romstage_pre_mem() is invoked before memory training.
+ *
+ * platform_romstage_post_mem() is invoked after DRAM is initialized but
+ * before the transition to the RAM-based stack (Post-CAR).
+ *
+ * Default: No-op. These are weak symbols to be overridden by SoC or mainboard.
+ */
+__weak void platform_romstage_pre_mem(void) { /* no-op */ }
+__weak void platform_romstage_post_mem(void) { /* no-op */ }
+
 void __noreturn romstage_main(void)
 {
 	int i;
@@ -71,7 +84,9 @@ void __noreturn romstage_main(void)
 	 */
 	romstage_adainit();
 
+	platform_romstage_pre_mem();
 	mainboard_romstage_entry();
+	platform_romstage_post_mem();
 
 	/* Check the stack. */
 	for (i = 0; i < num_guards; i++) {

From 9b663182d38876dedccc3507c883b32b2575287e Mon Sep 17 00:00:00 2001
From: Subrata Banik <subratabanik@google.com>
Date: Thu, 29 Jan 2026 23:42:27 +0530
Subject: [PATCH 3205/3886] mb/google/fatcat: Move battery LED logic to
 platform hook
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

This patch moves the ChromeEC battery-low LED signaling from the
Panther Lake SoC romstage code to the Fatcat mainboard-specific
romstage.

By utilizing the platform_romstage_pre_mem() hook, we remove Google-
specific EC logic from the generic Intel SoC directory, adhering better
to the separation of concerns between SoC and Mainboard code.

- Implement platform_romstage_pre_mem() in google/fatcat.
- Remove redundant EC include and LED logic from Panther Lake SoC.

Change-Id: I09f7dd516f1a98cf99313db379cfbef5157c9869
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91000
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Pranava Y N <pranavayn@google.com>
---
 src/mainboard/google/fatcat/romstage.c | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/src/mainboard/google/fatcat/romstage.c b/src/mainboard/google/fatcat/romstage.c
index 8f0000c2ce..2b3452eff8 100644
--- a/src/mainboard/google/fatcat/romstage.c
+++ b/src/mainboard/google/fatcat/romstage.c
@@ -1,6 +1,8 @@
 /* SPDX-License-Identifier: GPL-2.0-or-later */
 
+#include <arch/romstage.h>
 #include <baseboard/variants.h>
+#include <ec/google/chromeec/ec.h>
 #include <fsp/api.h>
 #include <soc/romstage.h>
 #include <soc/soc_chip.h>
@@ -43,3 +45,10 @@ void mainboard_memory_init_params(FSPM_UPD *memupd)
 	/* Override FSP-M UPD per board if required. */
 	variant_update_soc_memory_init_params(memupd);
 }
+
+void platform_romstage_pre_mem(void)
+{
+	/* Set LED to Red to alert the user visually */
+	if (CONFIG(EC_GOOGLE_CHROMEEC) && google_chromeec_is_critically_low_on_battery())
+		google_chromeec_set_lightbar_rgb(0xff, 0xff, 0x00, 0x00);
+}

From 219b6c84387948efb283e28e1ff9ae36a47bfba7 Mon Sep 17 00:00:00 2001
From: Subrata Banik <subratabanik@google.com>
Date: Wed, 21 Jan 2026 15:36:50 +0530
Subject: [PATCH 3206/3886] mb/google/bluey: Rename LB_BOOT_MODE_LOW_BATTERY
 for clarity

The current LB_BOOT_MODE_LOW_BATTERY actually implies a state where the
battery is below the critical threshold but a charger is attached,
allowing the system to boot into a charging-only or limited state.

Update the enum name to LB_BOOT_MODE_LOW_BATTERY_CHARGING across
coreboot tables and libpayload to better reflect this hardware state.

Changes:
- Rename boot mode enums in commonlib and libpayload.
- Update bluey mainboard logic to use the more descriptive name.
- Refactor is_low_power_boot() to is_low_power_boot_with_charger()
  to improve code readability.
- Ensure the charger-present condition is explicitly checked in
  romstage when setting the boot mode.

TEST=Verify bluey boots into off-mode charging and low-battery
charging modes correctly.

Change-Id: I2478c7519c781a8b5af78445899b7f9bf412cf42
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90845
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Jayvik Desai <jayvik@google.com>
---
 payloads/libpayload/include/coreboot_tables.h |  5 ++++-
 .../include/commonlib/coreboot_tables.h       |  5 ++++-
 src/mainboard/google/bluey/mainboard.c        | 20 ++++++++++---------
 src/mainboard/google/bluey/romstage.c         |  5 +++--
 4 files changed, 22 insertions(+), 13 deletions(-)

diff --git a/payloads/libpayload/include/coreboot_tables.h b/payloads/libpayload/include/coreboot_tables.h
index 36ec6e9125..6cb2558f3a 100644
--- a/payloads/libpayload/include/coreboot_tables.h
+++ b/payloads/libpayload/include/coreboot_tables.h
@@ -456,8 +456,11 @@ struct cb_panel_poweroff {
 };
 
 enum boot_mode_t {
+	/* Regular boot scenarios */
 	CB_BOOT_MODE_NORMAL,
-	CB_BOOT_MODE_LOW_BATTERY,
+	/* Device is booting in low-batter w/ charger attached */
+	CB_BOOT_MODE_LOW_BATTERY_CHARGING,
+	/* Device is booting in due to charger insertion */
 	CB_BOOT_MODE_OFFMODE_CHARGING,
 };
 
diff --git a/src/commonlib/include/commonlib/coreboot_tables.h b/src/commonlib/include/commonlib/coreboot_tables.h
index ed5d52f0b5..d4582559df 100644
--- a/src/commonlib/include/commonlib/coreboot_tables.h
+++ b/src/commonlib/include/commonlib/coreboot_tables.h
@@ -639,8 +639,11 @@ struct lb_panel_poweroff {
 };
 
 enum boot_mode_t {
+	/* Regular boot scenarios */
 	LB_BOOT_MODE_NORMAL,
-	LB_BOOT_MODE_LOW_BATTERY,
+	/* Device is booting in low-batter w/ charger attached */
+	LB_BOOT_MODE_LOW_BATTERY_CHARGING,
+	/* Device is booting in due to charger insertion */
 	LB_BOOT_MODE_OFFMODE_CHARGING,
 };
 
diff --git a/src/mainboard/google/bluey/mainboard.c b/src/mainboard/google/bluey/mainboard.c
index ad02b2ea3c..6d3538dcde 100644
--- a/src/mainboard/google/bluey/mainboard.c
+++ b/src/mainboard/google/bluey/mainboard.c
@@ -63,13 +63,15 @@ static enum boot_mode_t get_boot_mode(void)
 	return boot_mode;
 }
 
-static bool is_low_power_boot(void)
+static bool is_low_power_boot_with_charger(void)
 {
+	bool ret = false;
 	enum boot_mode_t boot_mode = get_boot_mode();
-	if ((boot_mode == LB_BOOT_MODE_LOW_BATTERY) ||
+	if ((boot_mode == LB_BOOT_MODE_LOW_BATTERY_CHARGING) ||
 	    (boot_mode == LB_BOOT_MODE_OFFMODE_CHARGING))
-		return true;
-	return false;
+		ret = true;
+
+	return ret;
 }
 
 static void enable_usb_camera(void)
@@ -99,7 +101,7 @@ static void setup_usb(void)
 static void setup_usb_late(void *unused)
 {
 	/* Skip USB initialization if boot mode is "low-battery" or "off-mode charging"*/
-	if (is_low_power_boot())
+	if (is_low_power_boot_with_charger())
 		return;
 
 	setup_usb_host0();
@@ -119,15 +121,15 @@ void lb_add_boot_mode(struct lb_header *header)
 	mode->size = sizeof(*mode);
 	mode->boot_mode = get_boot_mode();
 
-	/* Enable charging only during off-mode or low-battery mode and charger present */
-	if (is_low_power_boot() && google_chromeec_is_charger_present())
+	/* Enable charging only during off-mode or low-battery mode with charger present */
+	if (is_low_power_boot_with_charger())
 		enable_slow_battery_charging();
 }
 
 bool mainboard_needs_pcie_init(void)
 {
 	/* Skip PCIe initialization if boot mode is "low-battery" or "off-mode charging"*/
-	if (is_low_power_boot())
+	if (is_low_power_boot_with_charger())
 		return false;
 
 	return true;
@@ -152,7 +154,7 @@ static void mainboard_init(struct device *dev)
 	configure_parallel_charging();
 
 	/* Skip mainboard initialization if boot mode is "low-battery" or "off-mode charging"*/
-	if (is_low_power_boot())
+	if (is_low_power_boot_with_charger())
 		return;
 
 	gpi_firmware_load(QUP_0_GSI_BASE);
diff --git a/src/mainboard/google/bluey/romstage.c b/src/mainboard/google/bluey/romstage.c
index aeb1eeda6b..c25704f077 100644
--- a/src/mainboard/google/bluey/romstage.c
+++ b/src/mainboard/google/bluey/romstage.c
@@ -39,8 +39,9 @@ static enum boot_mode_t set_boot_mode(void)
 	enum boot_mode_t boot_mode_new = LB_BOOT_MODE_NORMAL;
 	if (is_off_mode())
 		boot_mode_new = LB_BOOT_MODE_OFFMODE_CHARGING;
-	else if (google_chromeec_is_below_critical_threshold())
-		boot_mode_new = LB_BOOT_MODE_LOW_BATTERY;
+	else if (google_chromeec_is_below_critical_threshold() &&
+			 google_chromeec_is_charger_present())
+		boot_mode_new = LB_BOOT_MODE_LOW_BATTERY_CHARGING;
 	boot_mode = boot_mode_new;
 	return boot_mode_new;
 }

From 772270c2c1039d902892eef1fe7537d5165c6a9d Mon Sep 17 00:00:00 2001
From: Subrata Banik <subratabanik@google.com>
Date: Wed, 21 Jan 2026 16:30:58 +0530
Subject: [PATCH 3207/3886] mb/google/bluey: Differentiate low battery boot
 modes

Currently, the system does not explicitly distinguish between a low
battery boot with a charger and one without. This is critical for
deciding whether to allow the boot to proceed or to protect the
battery.

This patch:
1.  Re-introduces LB_BOOT_MODE_LOW_BATTERY to represent a critical
    battery state without a charger present.
2.  Refactors set_boot_mode() to accommodate off-mode charging and
    evaluating battery health (low-batter w/ or w/o charger present)..

TEST=Verified on Bluey:
- Boot with charger + low battery enters LOW_BATTERY_CHARGING.
- Boot without charger + low battery enters LOW_BATTERY..
- Boot with normal battery enters NORMAL mode.

Change-Id: I2c9fa7eb61d1bbd6f9379c81577aee53ab6a0761
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90849
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Jayvik Desai <jayvik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 payloads/libpayload/include/coreboot_tables.h   |  2 ++
 .../include/commonlib/coreboot_tables.h         |  2 ++
 src/mainboard/google/bluey/romstage.c           | 17 ++++++++++++-----
 3 files changed, 16 insertions(+), 5 deletions(-)

diff --git a/payloads/libpayload/include/coreboot_tables.h b/payloads/libpayload/include/coreboot_tables.h
index 6cb2558f3a..9864c2b5d4 100644
--- a/payloads/libpayload/include/coreboot_tables.h
+++ b/payloads/libpayload/include/coreboot_tables.h
@@ -458,6 +458,8 @@ struct cb_panel_poweroff {
 enum boot_mode_t {
 	/* Regular boot scenarios */
 	CB_BOOT_MODE_NORMAL,
+	/* Device is booting in low-batter w/o charger attached */
+	CB_BOOT_MODE_LOW_BATTERY,
 	/* Device is booting in low-batter w/ charger attached */
 	CB_BOOT_MODE_LOW_BATTERY_CHARGING,
 	/* Device is booting in due to charger insertion */
diff --git a/src/commonlib/include/commonlib/coreboot_tables.h b/src/commonlib/include/commonlib/coreboot_tables.h
index d4582559df..cb16e65c5c 100644
--- a/src/commonlib/include/commonlib/coreboot_tables.h
+++ b/src/commonlib/include/commonlib/coreboot_tables.h
@@ -641,6 +641,8 @@ struct lb_panel_poweroff {
 enum boot_mode_t {
 	/* Regular boot scenarios */
 	LB_BOOT_MODE_NORMAL,
+	/* Device is booting in low-batter w/o charger attached */
+	LB_BOOT_MODE_LOW_BATTERY,
 	/* Device is booting in low-batter w/ charger attached */
 	LB_BOOT_MODE_LOW_BATTERY_CHARGING,
 	/* Device is booting in due to charger insertion */
diff --git a/src/mainboard/google/bluey/romstage.c b/src/mainboard/google/bluey/romstage.c
index c25704f077..12b1479801 100644
--- a/src/mainboard/google/bluey/romstage.c
+++ b/src/mainboard/google/bluey/romstage.c
@@ -36,12 +36,19 @@ static enum boot_mode_t set_boot_mode(void)
 	if (!CONFIG(EC_GOOGLE_CHROMEEC))
 		return boot_mode;
 
-	enum boot_mode_t boot_mode_new = LB_BOOT_MODE_NORMAL;
-	if (is_off_mode())
+	enum boot_mode_t boot_mode_new;
+
+	if (is_off_mode()) {
 		boot_mode_new = LB_BOOT_MODE_OFFMODE_CHARGING;
-	else if (google_chromeec_is_below_critical_threshold() &&
-			 google_chromeec_is_charger_present())
-		boot_mode_new = LB_BOOT_MODE_LOW_BATTERY_CHARGING;
+	} else if (google_chromeec_is_below_critical_threshold()) {
+		if (google_chromeec_is_charger_present())
+			boot_mode_new = LB_BOOT_MODE_LOW_BATTERY_CHARGING;
+		else
+			boot_mode_new = LB_BOOT_MODE_LOW_BATTERY;
+	} else {
+		boot_mode_new = LB_BOOT_MODE_NORMAL;
+	}
+
 	boot_mode = boot_mode_new;
 	return boot_mode_new;
 }

From 642433813f0e81cb06dcce00eadf27f49a06bbd8 Mon Sep 17 00:00:00 2001
From: Kapil Porwal <kapilporwal@google.com>
Date: Wed, 28 Jan 2026 15:00:00 +0530
Subject: [PATCH 3208/3886] mb/google/bluey: Initialize display before
 low-power boot check

Currently, display_startup() is called near the end of mainboard_init.
If the system enters a low-power boot mode (such as low-battery or
off-mode charging), the function returns early, leaving the display
uninitialized.

Move display_startup() before the is_low_power_boot() check. This
ensures the display is ready to show user notifications, such as
battery status or charging icons, even when the rest of the
mainboard initialization is skipped.

TEST=Build and boot Google/Quartz.

Change-Id: Ibaa2b20d3ea1ca8548ea6ebf93efbc48cb7a6b95
Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90968
Reviewed-by: Jayvik Desai <jayvik@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/google/bluey/mainboard.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/mainboard/google/bluey/mainboard.c b/src/mainboard/google/bluey/mainboard.c
index 6d3538dcde..c7c136a886 100644
--- a/src/mainboard/google/bluey/mainboard.c
+++ b/src/mainboard/google/bluey/mainboard.c
@@ -153,6 +153,8 @@ static void mainboard_init(struct device *dev)
 {
 	configure_parallel_charging();
 
+	display_startup();
+
 	/* Skip mainboard initialization if boot mode is "low-battery" or "off-mode charging"*/
 	if (is_low_power_boot_with_charger())
 		return;
@@ -204,8 +206,6 @@ static void mainboard_init(struct device *dev)
 	/* Setup USB related initial config */
 	setup_usb();
 
-	display_startup();
-
 	lpass_init();
 }
 

From 3c9077cb819aaae183a1f878849e24898848b5c4 Mon Sep 17 00:00:00 2001
From: Subrata Banik <subratabanik@google.com>
Date: Wed, 28 Jan 2026 10:05:55 +0000
Subject: [PATCH 3209/3886] mb/google/bluey: Implement graceful critical
 battery shutdown

When a critical battery level is detected without a charger present,
the system must shutdown to protect the battery from deep discharge.
Previously, this was an immediate power-off with minimal feedback.

This patch improves the shutdown sequence by:
1.  Adding trigger_critical_battery_shutdown() to encapsulate the
    safety logic.
2.  Providing visual feedback by setting the ChromeOS LED to Red
    during early boot flow (at romstage) for user feedback..
3.  Logging an ELOG_TYPE_LOW_BATTERY_INDICATOR event to the event log
    for post-mortem analysis.
4.  Introducing a 5-second delay before power-off to ensure UART
    logs are flushed and the user can observe the LED alert.

The shutdown logic remains in ramstage to ensure the user is able to
see the low-battery notification before powering off the system.

TEST=Boot Bluey with battery < critical threshold and no charger:
- Observed LED turning Red.
- Observed "Critical battery level..." warning in serial log.
- System powered off after 5 seconds.
- Verified 'cbmem -l' showed the low battery event after next boot.

Change-Id: I52948eac87417bca895000cb10dbaa87bb6a9384
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90850
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/google/bluey/mainboard.c | 29 ++++++++++++++++++++++++++
 src/mainboard/google/bluey/romstage.c  |  4 ++++
 2 files changed, 33 insertions(+)

diff --git a/src/mainboard/google/bluey/mainboard.c b/src/mainboard/google/bluey/mainboard.c
index c7c136a886..3bdf4f4425 100644
--- a/src/mainboard/google/bluey/mainboard.c
+++ b/src/mainboard/google/bluey/mainboard.c
@@ -11,6 +11,7 @@
 #include <device/device.h>
 #include <device/i2c_simple.h>
 #include <ec/google/chromeec/ec.h>
+#include <elog.h>
 #include <gpio.h>
 #include <soc/clock.h>
 #include <soc/pcie.h>
@@ -29,6 +30,8 @@
 #define USB3_MODE_NORMAL_VAL	0x21
 #define USB3_MODE_FLIP_VAL	0x23
 
+#define LOW_BATTERY_SHUTDOWN_DELAY_SEC 5
+
 void mainboard_usb_typec_configure(uint8_t port_num, bool inverse_polarity)
 {
 	if (!CONFIG(MAINBOARD_HAS_PS8820_RETIMER))
@@ -149,12 +152,38 @@ static void display_startup(void)
 	enable_mdss_clk();
 }
 
+static void trigger_critical_battery_shutdown(void)
+{
+	printk(BIOS_WARNING, "Critical battery level detected without charger! Shutting down.\n");
+
+	if (!CONFIG(EC_GOOGLE_CHROMEEC))
+		return;
+
+	/* Set LED to Red to alert the user visually */
+	google_chromeec_set_lightbar_rgb(0xff, 0xff, 0x00, 0x00);
+
+	/* Log the event to CMOS/Flash for post-mortem analysis */
+	elog_add_event_byte(ELOG_TYPE_LOW_BATTERY_INDICATOR, ELOG_FW_ISSUE_SHUTDOWN);
+
+	/* Allow time for the log to flush and the user to see the LED change */
+	delay(LOW_BATTERY_SHUTDOWN_DELAY_SEC);
+
+	google_chromeec_ap_poweroff();
+}
+
 static void mainboard_init(struct device *dev)
 {
 	configure_parallel_charging();
 
 	display_startup();
 
+	/*
+	 * Low-battery boot indicator is done. Therefore, power off if battery
+	 * is critical and not charging
+	 */
+	if (get_boot_mode() == LB_BOOT_MODE_LOW_BATTERY)
+		trigger_critical_battery_shutdown();
+
 	/* Skip mainboard initialization if boot mode is "low-battery" or "off-mode charging"*/
 	if (is_low_power_boot_with_charger())
 		return;
diff --git a/src/mainboard/google/bluey/romstage.c b/src/mainboard/google/bluey/romstage.c
index 12b1479801..2b8e95c201 100644
--- a/src/mainboard/google/bluey/romstage.c
+++ b/src/mainboard/google/bluey/romstage.c
@@ -109,6 +109,10 @@ static void early_setup_usb(void)
 
 void platform_romstage_main(void)
 {
+	/* Set LED to Red to alert the user visually */
+	if (CONFIG(EC_GOOGLE_CHROMEEC) && google_chromeec_is_critically_low_on_battery())
+		google_chromeec_set_lightbar_rgb(0xff, 0xff, 0x00, 0x00);
+
 	/* Setup early USB related config */
 	early_setup_usb();
 

From 4a09db75d9271011236c34c90d55d7bfb4fc8e5b Mon Sep 17 00:00:00 2001
From: Nicholas Chin <nic.c3.14@gmail.com>
Date: Sun, 16 Nov 2025 11:07:59 -0700
Subject: [PATCH 3210/3886] util/autoport: Add support for 9 Series PCHs (Lynx
 Point Refresh)

The existing Lynx Point code is known to work with 9 series PCHs, as
evidenced by commit f5105313cf69 ("mb/asrock/z97_extreme6: Add new
mainboard") and commit 58c7a840976a ("mb/asrock: Add Z97E-ITX/ac
(Haswell/Broadwell)"). Add the missing IDs to autoport's existing Lynx
Point code.

These IDs were taken from the Intel 9 Series Chipset Family Platform
Controller Hub datasheet (document 330550), section 1.4 "Device and
Revision ID Table".

TEST=Autoport output for the ASRock Z87E-ITX remains unchanged
TEST=Autoport generates output for the ASRock Z97E-ITX/ac

Change-Id: I94c0b35245624d1a68ab69332fe9a5c5abfc5310
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90054
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 util/autoport/azalia.go    |  4 ++-
 util/autoport/lynxpoint.go | 50 ++++++++++++++++++++++++++++++++------
 2 files changed, 45 insertions(+), 9 deletions(-)

diff --git a/util/autoport/azalia.go b/util/autoport/azalia.go
index eb28a7c2dc..e5681ae9dc 100644
--- a/util/autoport/azalia.go
+++ b/util/autoport/azalia.go
@@ -65,7 +65,9 @@ func init() {
 	RegisterPCI(0x8086, 0x1c20, azalia{})
 	/* C216/ivybridge */
 	RegisterPCI(0x8086, 0x1e20, azalia{})
-	/* Lynx Point */
+	/* Lynx Point (8 Series PCH) */
 	RegisterPCI(0x8086, 0x8c20, azalia{})
 	RegisterPCI(0x8086, 0x9c20, azalia{})
+	/* Lynx Point Refresh (9 Series PCH) */
+	RegisterPCI(0x8086, 0x8ca0, azalia{})
 }
diff --git a/util/autoport/lynxpoint.go b/util/autoport/lynxpoint.go
index 681072c6b4..0ac428e7fa 100644
--- a/util/autoport/lynxpoint.go
+++ b/util/autoport/lynxpoint.go
@@ -9,6 +9,7 @@ const (
 	LYNX_POINT_DESKTOP
 	LYNX_POINT_SERVER
 	LYNX_POINT_ULT
+	LYNX_POINT_REFRESH
 )
 
 type lynxpoint struct {
@@ -161,6 +162,11 @@ func (b lynxpoint) Scan(ctx Context, addr PCIDevData) {
 		ich9GetFlashSize(ctx)
 	}
 
+	if (b.variant == LYNX_POINT_REFRESH) {
+		KconfigBool["USE_BROADWELL_MRC"] = true
+		KconfigComment["USE_BROADWELL_MRC"] = "if !USE_NATIVE_RAMINIT # FIXME: Uncomment the if"
+	}
+
 	FADT := ctx.InfoSource.GetACPI()["FACP"]
 
 	sp0dtle_data := (inteltool.IOBP[0xea002750] >> 24) & 0xf
@@ -393,12 +399,14 @@ const struct usb3_port_config mainboard_usb3_ports[MAX_USB3_PORTS] = {
 
 func init() {
 	for _, id := range []uint16{
+		/* Lynx Point (8 Series PCH) */
 		0x8c41, 0x8c49, 0x8c4b, 0x8c4f,
 	} {
 		RegisterPCI(0x8086, uint16(id), lynxpoint{variant: LYNX_POINT_MOBILE})
 	}
 
 	for _, id := range []uint16{
+		/* Lynx Point (8 Series PCH) */
 		0x8c42, 0x8c44, 0x8c46, 0x8c4a,
 		0x8c4c, 0x8c4e, 0x8c50, 0x8c5c,
 	} {
@@ -417,52 +425,78 @@ func init() {
 		RegisterPCI(0x8086, uint16(id), lynxpoint{variant: LYNX_POINT_ULT})
 	}
 
+	for _, id := range []uint16{
+		/* Lynx Point Refresh (9 Series PCH) */
+		0x8cc1, 0x8cc2, 0x8cc3, 0x8cc4, 0x8cc6,
+	} {
+		RegisterPCI(0x8086, uint16(id), lynxpoint{variant: LYNX_POINT_REFRESH})
+	}
+
 	/* PCIe bridge */
 	for _, id := range []uint16{
+		/* Lynx Point (8 Series PCH) */
 		0x8c10, 0x8c12, 0x8c14, 0x8c16, 0x8c18, 0x8c1a, 0x8c1c, 0x8c1e,
+		/* Lynx Point LP */
 		0x9c10, 0x9c12, 0x9c14, 0x9c16, 0x9c18, 0x9c1a,
+		/* Lynx Point Refresh (9 Series PCH) */
+		0x8c90, 0x8c92, 0x8c94, 0x8c96, 0x8c98, 0x8c9a, 0x8c9c, 0x8c9e,
 	} {
 		RegisterPCI(0x8086, id, GenericPCI{})
 	}
 
 	/* SMBus controller  */
-	RegisterPCI(0x8086, 0x8c22, GenericPCI{MissingParent: "smbus"})
-	RegisterPCI(0x8086, 0x9c22, GenericPCI{MissingParent: "smbus"})
+	RegisterPCI(0x8086, 0x8c22, GenericPCI{MissingParent: "smbus"}) /* Lynx Point (8 Series PCH) */
+	RegisterPCI(0x8086, 0x9c22, GenericPCI{MissingParent: "smbus"}) /* Lynx Point LP */
+	RegisterPCI(0x8086, 0x8ca2, GenericPCI{MissingParent: "smbus"}) /* Lynx Point Refresh (9 Series PCH) */
 
 	/* SATA */
 	for _, id := range []uint16{
+		/* Lynx Point (8 Series PCH) */
 		0x8c00, 0x8c02, 0x8c04, 0x8c06, 0x8c08, 0x8c0e,
 		0x8c01, 0x8c03, 0x8c05, 0x8c07, 0x8c09, 0x8c0f,
+		/* Lynx Point LP */
 		0x9c03, 0x9c05, 0x9c07, 0x9c0f,
+		/* Lynx Point Refresh (9 Series PCH) */
+		0x8c80, 0x8c82, 0x8c84, 0x8c86, 0x8c88, 0x8c8e,
+		0x8c81, 0x8c83, 0x8c85, 0x8c87, 0x8c89, 0x8c8f,
 	} {
 		RegisterPCI(0x8086, id, GenericPCI{})
 	}
 
 	/* EHCI */
 	for _, id := range []uint16{
-		0x9c26, 0x8c26, 0x8c2d,
+		0x8c26, 0x8c2d, /* Lynx Point (8 Series PCH) */
+		0x9c26,         /* Lynx Point LP */
+		0x8ca6, 0x8cad, /* Lynx Point Refresh (9 Series PCH) */
 	} {
 		RegisterPCI(0x8086, id, GenericPCI{})
 	}
 
 	/* XHCI */
-	RegisterPCI(0x8086, 0x8c31, GenericPCI{})
-	RegisterPCI(0x8086, 0x9c31, GenericPCI{})
+	RegisterPCI(0x8086, 0x8c31, GenericPCI{}) /* Lynx Point (8 Series PCH) */
+	RegisterPCI(0x8086, 0x9c31, GenericPCI{}) /* Lynx Point LP */
+	RegisterPCI(0x8086, 0x8cb1, GenericPCI{}) /* Lynx Point Refresh (9 Series PCH) */
 
 	/* ME and children */
 	for _, id := range []uint16{
+		/* Lynx Point (8 Series PCH) */
 		0x8c3a, 0x8c3b, 0x8c3c, 0x8c3d,
+		/* Lynx Point LP */
 		0x9c3a, 0x9c3b, 0x9c3c, 0x9c3d,
+		/* Lynx Point Refresh (9 Series PCH) */
+		0x8cba, 0x8cbb, 0x8cbc, 0x8cbd,
 	} {
 		RegisterPCI(0x8086, id, GenericPCI{})
 	}
 
 	/* Ethernet */
-	RegisterPCI(0x8086, 0x8c33, GenericPCI{})
+	RegisterPCI(0x8086, 0x8c33, GenericPCI{}) /* Lynx Point (8 Series PCH) */
+	RegisterPCI(0x8086, 0x8cb3, GenericPCI{}) /* Lynx Point Refresh (9 Series PCH) */
 
 	/* Thermal */
-	RegisterPCI(0x8086, 0x8c24, GenericPCI{})
-	RegisterPCI(0x8086, 0x9c24, GenericPCI{})
+	RegisterPCI(0x8086, 0x8c24, GenericPCI{}) /* Lynx Point (8 Series PCH) */
+	RegisterPCI(0x8086, 0x9c24, GenericPCI{}) /* Lynx Point LP */
+	RegisterPCI(0x8086, 0x8ca4, GenericPCI{}) /* Lynx Point Refresh (9 Series PCH) */
 
 	/* LAN Controller on LP PCH (if EEPROM has 0x0000/0xffff in DID) */
 	RegisterPCI(0x8086, 0x155a, GenericPCI{})

From fa2e54907b0c7a155da771213f918c065b717c19 Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Wed, 28 Jan 2026 18:09:19 -0600
Subject: [PATCH 3211/3886] mb/google/brya: Mark PCIe root ports with attached
 eMMC as built-in

Set the PCIE_RP_BUILT_IN flag on the PCIe root ports which have eMMC
attached via a GL9763E bridge/controller for all variants using PCIe-
attached eMMC. This ensures the FSP PcieRpSlotImplemented UPD is set
properly and that FSP correctly treats these RPs as built-in rather
than slot devices.

TEST=tested with rest of patch train

Change-Id: Ifb4b255ea5367733405a7ac5d73c616ce7f8aad5
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90980
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
---
 src/mainboard/google/brya/variants/anahera/overridetree.cb    | 2 +-
 src/mainboard/google/brya/variants/anahera4es/overridetree.cb | 2 +-
 src/mainboard/google/brya/variants/aurash/overridetree.cb     | 2 +-
 src/mainboard/google/brya/variants/crota/overridetree.cb      | 2 +-
 src/mainboard/google/brya/variants/gladios/overridetree.cb    | 2 +-
 src/mainboard/google/brya/variants/kinox/overridetree.cb      | 2 +-
 src/mainboard/google/brya/variants/lisbon/overridetree.cb     | 2 +-
 src/mainboard/google/brya/variants/moli/overridetree.cb       | 2 +-
 src/mainboard/google/brya/variants/primus/overridetree.cb     | 2 +-
 src/mainboard/google/brya/variants/taeko/overridetree.cb      | 2 +-
 src/mainboard/google/brya/variants/taniks/overridetree.cb     | 2 +-
 src/mainboard/google/brya/variants/volmar/overridetree.cb     | 2 +-
 12 files changed, 12 insertions(+), 12 deletions(-)

diff --git a/src/mainboard/google/brya/variants/anahera/overridetree.cb b/src/mainboard/google/brya/variants/anahera/overridetree.cb
index 12566087db..b0dfb81526 100644
--- a/src/mainboard/google/brya/variants/anahera/overridetree.cb
+++ b/src/mainboard/google/brya/variants/anahera/overridetree.cb
@@ -202,7 +202,7 @@ chip soc/intel/alderlake
 			register "pch_pcie_rp[PCH_RP(7)]" = "{
 				.clk_src = 6,
 				.clk_req = 6,
-				.flags = PCIE_RP_HOTPLUG | PCIE_RP_AER,
+				.flags = PCIE_RP_HOTPLUG | PCIE_RP_AER | PCIE_RP_BUILT_IN,
 			}"
 		end     #PCIE7 EMMC
 		device ref tcss_dma0 on
diff --git a/src/mainboard/google/brya/variants/anahera4es/overridetree.cb b/src/mainboard/google/brya/variants/anahera4es/overridetree.cb
index 33daa9962c..41393781c7 100644
--- a/src/mainboard/google/brya/variants/anahera4es/overridetree.cb
+++ b/src/mainboard/google/brya/variants/anahera4es/overridetree.cb
@@ -184,7 +184,7 @@ chip soc/intel/alderlake
 			register "pch_pcie_rp[PCH_RP(7)]" = "{
 				.clk_src = 6,
 				.clk_req = 6,
-				.flags = PCIE_RP_HOTPLUG | PCIE_RP_AER,
+				.flags = PCIE_RP_HOTPLUG | PCIE_RP_AER | PCIE_RP_BUILT_IN,
 			}"
 		end     #PCIE7 EMMC
 		device ref tcss_dma0 on
diff --git a/src/mainboard/google/brya/variants/aurash/overridetree.cb b/src/mainboard/google/brya/variants/aurash/overridetree.cb
index a18197627c..0d2cd9974b 100644
--- a/src/mainboard/google/brya/variants/aurash/overridetree.cb
+++ b/src/mainboard/google/brya/variants/aurash/overridetree.cb
@@ -193,7 +193,7 @@ chip soc/intel/alderlake
 			register "pch_pcie_rp[PCH_RP(12)]" = "{
 				.clk_src = 1,
 				.clk_req = 1,
-				.flags = PCIE_RP_LTR | PCIE_RP_AER,
+				.flags = PCIE_RP_LTR | PCIE_RP_AER | PCIE_RP_BUILT_IN,
 			}"
 			probe STORAGE STORAGE_EMMC
 			probe STORAGE STORAGE_UNKNOWN
diff --git a/src/mainboard/google/brya/variants/crota/overridetree.cb b/src/mainboard/google/brya/variants/crota/overridetree.cb
index a55c68c98e..a7994127c1 100644
--- a/src/mainboard/google/brya/variants/crota/overridetree.cb
+++ b/src/mainboard/google/brya/variants/crota/overridetree.cb
@@ -203,7 +203,7 @@ chip soc/intel/alderlake
 			register "pch_pcie_rp[PCH_RP(3)]" = "{
 				.clk_src = 1,
 				.clk_req = 1,
-				.flags = PCIE_RP_LTR | PCIE_RP_AER,
+				.flags = PCIE_RP_LTR | PCIE_RP_AER | PCIE_RP_BUILT_IN,
 			}"
 		end	#PCIE3 BH799BB
 		device ref pcie_rp9 off end
diff --git a/src/mainboard/google/brya/variants/gladios/overridetree.cb b/src/mainboard/google/brya/variants/gladios/overridetree.cb
index 6c3eaf952a..10b54c4f92 100644
--- a/src/mainboard/google/brya/variants/gladios/overridetree.cb
+++ b/src/mainboard/google/brya/variants/gladios/overridetree.cb
@@ -213,7 +213,7 @@ chip soc/intel/alderlake
 			register "pch_pcie_rp[PCH_RP(12)]" = "{
 				.clk_src = 4,
 				.clk_req = 4,
-				.flags = PCIE_RP_HOTPLUG | PCIE_RP_AER,
+				.flags = PCIE_RP_HOTPLUG | PCIE_RP_AER | PCIE_RP_BUILT_IN,
 			}"
 			probe STORAGE STORAGE_EMMC
 		end     #PCIE12 EMMC
diff --git a/src/mainboard/google/brya/variants/kinox/overridetree.cb b/src/mainboard/google/brya/variants/kinox/overridetree.cb
index d0740b339d..5b708f08f7 100644
--- a/src/mainboard/google/brya/variants/kinox/overridetree.cb
+++ b/src/mainboard/google/brya/variants/kinox/overridetree.cb
@@ -261,7 +261,7 @@ chip soc/intel/alderlake
 			register "pch_pcie_rp[PCH_RP(6)]" = "{
 				.clk_src = 1,
 				.clk_req = 1,
-				.flags = PCIE_RP_LTR | PCIE_RP_AER,
+				.flags = PCIE_RP_LTR | PCIE_RP_AER | PCIE_RP_BUILT_IN,
 			}"
 			chip soc/intel/common/block/pcie/rtd3
 				register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_H13)"
diff --git a/src/mainboard/google/brya/variants/lisbon/overridetree.cb b/src/mainboard/google/brya/variants/lisbon/overridetree.cb
index 6c3eaf952a..10b54c4f92 100644
--- a/src/mainboard/google/brya/variants/lisbon/overridetree.cb
+++ b/src/mainboard/google/brya/variants/lisbon/overridetree.cb
@@ -213,7 +213,7 @@ chip soc/intel/alderlake
 			register "pch_pcie_rp[PCH_RP(12)]" = "{
 				.clk_src = 4,
 				.clk_req = 4,
-				.flags = PCIE_RP_HOTPLUG | PCIE_RP_AER,
+				.flags = PCIE_RP_HOTPLUG | PCIE_RP_AER | PCIE_RP_BUILT_IN,
 			}"
 			probe STORAGE STORAGE_EMMC
 		end     #PCIE12 EMMC
diff --git a/src/mainboard/google/brya/variants/moli/overridetree.cb b/src/mainboard/google/brya/variants/moli/overridetree.cb
index 3397d0c211..741d54d748 100644
--- a/src/mainboard/google/brya/variants/moli/overridetree.cb
+++ b/src/mainboard/google/brya/variants/moli/overridetree.cb
@@ -201,7 +201,7 @@ chip soc/intel/alderlake
 			register "pch_pcie_rp[PCH_RP(12)]" = "{
 				.clk_src = 1,
 				.clk_req = 1,
-				.flags = PCIE_RP_LTR | PCIE_RP_AER,
+				.flags = PCIE_RP_LTR | PCIE_RP_AER | PCIE_RP_BUILT_IN,
 			}"
 			probe STORAGE STORAGE_EMMC
 			probe STORAGE STORAGE_UNKNOWN
diff --git a/src/mainboard/google/brya/variants/primus/overridetree.cb b/src/mainboard/google/brya/variants/primus/overridetree.cb
index b2619ee67d..f073184ed4 100644
--- a/src/mainboard/google/brya/variants/primus/overridetree.cb
+++ b/src/mainboard/google/brya/variants/primus/overridetree.cb
@@ -183,7 +183,7 @@ chip soc/intel/alderlake
 			register "pch_pcie_rp[PCH_RP(3)]" = "{
 				.clk_src = 6,
 				.clk_req = 6,
-				.flags = PCIE_RP_LTR | PCIE_RP_AER,
+				.flags = PCIE_RP_LTR | PCIE_RP_AER | PCIE_RP_BUILT_IN,
 			}"
 		end	#PCIE3 BH799BB
 		device ref tcss_dma0 on
diff --git a/src/mainboard/google/brya/variants/taeko/overridetree.cb b/src/mainboard/google/brya/variants/taeko/overridetree.cb
index 0e1290f873..0abad554cc 100644
--- a/src/mainboard/google/brya/variants/taeko/overridetree.cb
+++ b/src/mainboard/google/brya/variants/taeko/overridetree.cb
@@ -565,7 +565,7 @@ chip soc/intel/alderlake
 			register "pch_pcie_rp[PCH_RP(9)]" = "{
 				.clk_src = 0,
 				.clk_req = 0,
-				.flags = PCIE_RP_LTR | PCIE_RP_AER,
+				.flags = PCIE_RP_LTR | PCIE_RP_AER | PCIE_RP_BUILT_IN,
 				.pcie_rp_aspm = ASPM_L1,
 			}"
 			probe BOOT_EMMC_MASK BOOT_EMMC_ENABLED
diff --git a/src/mainboard/google/brya/variants/taniks/overridetree.cb b/src/mainboard/google/brya/variants/taniks/overridetree.cb
index e11793ae4e..09654293dc 100644
--- a/src/mainboard/google/brya/variants/taniks/overridetree.cb
+++ b/src/mainboard/google/brya/variants/taniks/overridetree.cb
@@ -383,7 +383,7 @@ chip soc/intel/alderlake
 			register "pch_pcie_rp[PCH_RP(9)]" = "{
 				.clk_src = 0,
 				.clk_req = 0,
-				.flags = PCIE_RP_LTR | PCIE_RP_AER,
+				.flags = PCIE_RP_LTR | PCIE_RP_AER | PCIE_RP_BUILT_IN,
 			}"
 			probe BOOT_EMMC_MASK BOOT_EMMC_ENABLED
 		end
diff --git a/src/mainboard/google/brya/variants/volmar/overridetree.cb b/src/mainboard/google/brya/variants/volmar/overridetree.cb
index f57b733931..2145204245 100644
--- a/src/mainboard/google/brya/variants/volmar/overridetree.cb
+++ b/src/mainboard/google/brya/variants/volmar/overridetree.cb
@@ -331,7 +331,7 @@ chip soc/intel/alderlake
 			register "pch_pcie_rp[PCH_RP(3)]" = "{
 				.clk_src = 4,
 				.clk_req = 4,
-				.flags = PCIE_RP_LTR | PCIE_RP_AER,
+				.flags = PCIE_RP_LTR | PCIE_RP_AER | PCIE_RP_BUILT_IN,
 			}"
 			probe BOOT_EMMC_MASK BOOT_EMMC_ENABLED
 		end	#PCIE3 BH799BB

From 0f9940bf89dc211e0f5b1baca00631a9385c6c87 Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Wed, 28 Jan 2026 18:19:46 -0600
Subject: [PATCH 3212/3886] mb/google/volteer: Mark PCIe root ports with
 attached eMMC as built-in

Set PcieRpSlotImplemented to 0 on the PCIe root ports which have eMMC
attached via a GL9763E bridge/controller for chronicler and elemi
variants. This ensures that FSP correctly treats these RPs as built-in
rather than slot devices.

TEST=tested with rest of patch train

Change-Id: I0e06df689164f95ee9f0253fde3df2891239fa63
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90981
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
---
 src/mainboard/google/volteer/variants/chronicler/overridetree.cb | 1 +
 src/mainboard/google/volteer/variants/elemi/overridetree.cb      | 1 +
 2 files changed, 2 insertions(+)

diff --git a/src/mainboard/google/volteer/variants/chronicler/overridetree.cb b/src/mainboard/google/volteer/variants/chronicler/overridetree.cb
index 180acca7b3..483fd3df21 100644
--- a/src/mainboard/google/volteer/variants/chronicler/overridetree.cb
+++ b/src/mainboard/google/volteer/variants/chronicler/overridetree.cb
@@ -272,6 +272,7 @@ chip soc/intel/tigerlake
 			register "PcieRpHotPlug[4]" = "1"
 			register "PcieClkSrcUsage[5]" = "4"
 			register "PcieClkSrcClkReq[5]" = "5"
+			register "PcieRpSlotImplemented[4]" = "false"
 		end
 		device ref pmc hidden
 			# The pmc_mux chip driver is a placeholder for the
diff --git a/src/mainboard/google/volteer/variants/elemi/overridetree.cb b/src/mainboard/google/volteer/variants/elemi/overridetree.cb
index 8f220b8fcd..c63dd738f2 100644
--- a/src/mainboard/google/volteer/variants/elemi/overridetree.cb
+++ b/src/mainboard/google/volteer/variants/elemi/overridetree.cb
@@ -273,6 +273,7 @@ chip soc/intel/tigerlake
 			register "PcieRpHotPlug[4]" = "1"
 			register "PcieClkSrcUsage[5]" = "4"
 			register "PcieClkSrcClkReq[5]" = "5"
+			register "PcieRpSlotImplemented[4]" = "false"
 		end
 		device ref pmc hidden
 			# The pmc_mux chip driver is a placeholder for the

From 235bb1e617173c7d35f71a66b59f717c9d834493 Mon Sep 17 00:00:00 2001
From: Maximilian Brune <maximilian.brune@9elements.com>
Date: Tue, 30 Sep 2025 03:18:43 +0200
Subject: [PATCH 3213/3886] util/crossgcc: Update clang to 21.1.8

The current clang version cannot be built using GCC-15 so switch to a
more recent release.

It also adds a new dependency called third party. Its used in various
LLVM components and is needed to build clang.

Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: I0f2ebc214726fd4ae4f7bba50a662dd5cb89a718
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89377
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 util/crossgcc/buildgcc                        | 11 +++++--
 .../clang-18.1.8.src_x86_baremetal.patch      | 29 -------------------
 .../clang-21.1.8.src_x86_baremetal.patch      | 25 ++++++++++++++++
 .../sum/clang-18.1.8.src.tar.xz.cksum         |  1 -
 .../sum/clang-21.1.8.src.tar.xz.cksum         |  1 +
 .../clang-tools-extra-18.1.8.src.tar.xz.cksum |  1 -
 .../clang-tools-extra-21.1.8.src.tar.xz.cksum |  1 +
 .../sum/cmake-18.1.8.src.tar.xz.cksum         |  1 -
 .../sum/cmake-21.1.8.src.tar.xz.cksum         |  1 +
 .../sum/compiler-rt-18.1.8.src.tar.xz.cksum   |  1 -
 .../sum/compiler-rt-21.1.8.src.tar.xz.cksum   |  1 +
 .../sum/libunwind-18.1.8.src.tar.xz.cksum     |  1 -
 .../sum/libunwind-21.1.8.src.tar.xz.cksum     |  1 +
 util/crossgcc/sum/lld-18.1.8.src.tar.xz.cksum |  1 -
 util/crossgcc/sum/lld-21.1.8.src.tar.xz.cksum |  1 +
 .../crossgcc/sum/llvm-18.1.8.src.tar.xz.cksum |  1 -
 .../crossgcc/sum/llvm-21.1.8.src.tar.xz.cksum |  1 +
 .../sum/runtimes-18.1.8.src.tar.xz.cksum      |  1 -
 .../sum/runtimes-21.1.8.src.tar.xz.cksum      |  1 +
 .../sum/third-party-21.1.8.src.tar.xz.cksum   |  1 +
 20 files changed, 42 insertions(+), 40 deletions(-)
 delete mode 100644 util/crossgcc/patches/clang-18.1.8.src_x86_baremetal.patch
 create mode 100644 util/crossgcc/patches/clang-21.1.8.src_x86_baremetal.patch
 delete mode 100644 util/crossgcc/sum/clang-18.1.8.src.tar.xz.cksum
 create mode 100644 util/crossgcc/sum/clang-21.1.8.src.tar.xz.cksum
 delete mode 100644 util/crossgcc/sum/clang-tools-extra-18.1.8.src.tar.xz.cksum
 create mode 100644 util/crossgcc/sum/clang-tools-extra-21.1.8.src.tar.xz.cksum
 delete mode 100644 util/crossgcc/sum/cmake-18.1.8.src.tar.xz.cksum
 create mode 100644 util/crossgcc/sum/cmake-21.1.8.src.tar.xz.cksum
 delete mode 100644 util/crossgcc/sum/compiler-rt-18.1.8.src.tar.xz.cksum
 create mode 100644 util/crossgcc/sum/compiler-rt-21.1.8.src.tar.xz.cksum
 delete mode 100644 util/crossgcc/sum/libunwind-18.1.8.src.tar.xz.cksum
 create mode 100644 util/crossgcc/sum/libunwind-21.1.8.src.tar.xz.cksum
 delete mode 100644 util/crossgcc/sum/lld-18.1.8.src.tar.xz.cksum
 create mode 100644 util/crossgcc/sum/lld-21.1.8.src.tar.xz.cksum
 delete mode 100644 util/crossgcc/sum/llvm-18.1.8.src.tar.xz.cksum
 create mode 100644 util/crossgcc/sum/llvm-21.1.8.src.tar.xz.cksum
 delete mode 100644 util/crossgcc/sum/runtimes-18.1.8.src.tar.xz.cksum
 create mode 100644 util/crossgcc/sum/runtimes-21.1.8.src.tar.xz.cksum
 create mode 100644 util/crossgcc/sum/third-party-21.1.8.src.tar.xz.cksum

diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc
index be5493d16f..cfcd44e8a7 100755
--- a/util/crossgcc/buildgcc
+++ b/util/crossgcc/buildgcc
@@ -49,7 +49,7 @@ NASM_VERSION=2.16.03	# x86 assembly
 IASL_VERSION=20250807	# ACPI compiler
 
 # Clang/LLVM Toolchain (alternative to GCC, built separately)
-CLANG_VERSION=18.1.8
+CLANG_VERSION=21.1.8
 CMAKE_VERSION=4.0.3	# Required for building Clang
 
 # Architecture-specific options
@@ -72,6 +72,7 @@ CTE_ARCHIVE="clang-tools-extra-${CLANG_VERSION}.src.tar.xz"
 LLVMCMAKE_ARCHIVE="cmake-${CLANG_VERSION}.src.tar.xz"
 LIBUNWIND_ARCHIVE="libunwind-${CLANG_VERSION}.src.tar.xz"
 RUNTIMES_ARCHIVE="runtimes-${CLANG_VERSION}.src.tar.xz"
+THIRD_PARTY_ARCHIVE="third-party-${CLANG_VERSION}.src.tar.xz"
 CMAKE_ARCHIVE="cmake-${CMAKE_VERSION}.tar.gz"
 NASM_ARCHIVE="nasm-${NASM_VERSION}.tar.bz2"
 
@@ -96,6 +97,7 @@ LLVMCMAKE_BASE_URL="https://github.com/llvm/llvm-project/releases/download/llvmo
 LLD_BASE_URL="https://github.com/llvm/llvm-project/releases/download/llvmorg-${CLANG_VERSION}"
 LIBUNWIND_BASE_URL="https://github.com/llvm/llvm-project/releases/download/llvmorg-${CLANG_VERSION}"
 RUNTIMES_BASE_URL="https://github.com/llvm/llvm-project/releases/download/llvmorg-${CLANG_VERSION}"
+THIRD_PARTY_BASE_URL="https://github.com/llvm/llvm-project/releases/download/llvmorg-${CLANG_VERSION}"
 CMAKE_BASE_URL="https://cmake.org/files/v${CMAKE_VERSION%.*}"
 NASM_BASE_URL="https://www.nasm.us/pub/nasm/releasebuilds/${NASM_VERSION}"
 
@@ -104,7 +106,8 @@ ALL_ARCHIVES="$GMP_BASE_URL/$GMP_ARCHIVE $MPFR_BASE_URL/$MPFR_ARCHIVE $MPC_BASE_
 	$LLD_BASE_URL/$LLD_ARCHIVE $LLVM_BASE_URL/$LLVM_ARCHIVE $CLANG_BASE_URL/$CLANG_ARCHIVE \
 	$LLVMCMAKE_BASE_URL/$LLVMCMAKE_ARCHIVE $CRT_BASE_URL/$CRT_ARCHIVE $CTE_BASE_URL/$CTE_ARCHIVE \
 	$LIBUNWIND_BASE_URL/$LIBUNWIND_ARCHIVE $RUNTIMES_BASE_URL/$RUNTIMES_ARCHIVE \
-	$CMAKE_BASE_URL/$CMAKE_ARCHIVE $NASM_BASE_URL/$NASM_ARCHIVE $LIBSTDCXX_BASE_URL/$LIBSTDCXX_ARCHIVE"
+	$THIRD_PARTY_BASE_URL/$THIRD_PARTY_ARCHIVE $CMAKE_BASE_URL/$CMAKE_ARCHIVE \
+	$NASM_BASE_URL/$NASM_ARCHIVE $LIBSTDCXX_BASE_URL/$LIBSTDCXX_ARCHIVE"
 
 # GCC toolchain directories
 GMP_DIR="gmp-${GMP_VERSION}"
@@ -125,6 +128,7 @@ CTE_DIR="clang-tools-extra-${CLANG_VERSION}.src"
 LLVMCMAKE_DIR="cmake-${CLANG_VERSION}.src"
 LIBUNWIND_DIR="libunwind-${CLANG_VERSION}.src"
 RUNTIMES_DIR="runtimes-${CLANG_VERSION}.src"
+THIRD_PARTY_DIR="third-party-${CLANG_VERSION}.src"
 CMAKE_DIR="cmake-${CMAKE_VERSION}"
 NASM_DIR="nasm-${NASM_VERSION}"
 
@@ -953,6 +957,7 @@ build_LLVM() {
 	ln -nsf "$LLVMCMAKE_DIR" ../cmake
 	ln -nsf "$LIBUNWIND_DIR" ../libunwind
 	ln -nsf "$RUNTIMES_DIR" ../runtimes
+	ln -nsf "$THIRD_PARTY_DIR" ../third-party
 
 	$CMAKE -G "Unix Makefiles" \
 		-DCMAKE_INSTALL_PREFIX="$DESTDIR$TARGETDIR" \
@@ -1109,7 +1114,7 @@ case "$PACKAGE" in
 	CLANG|clang)
 		NAME="LLVM clang"
 		LLVM_VERSION=${CLANG_VERSION}
-		PACKAGES="CMAKE LLVM CLANG CRT CTE LLVMCMAKE LLD LIBUNWIND RUNTIMES"
+		PACKAGES="CMAKE LLVM CLANG CRT CTE LLVMCMAKE LLD LIBUNWIND RUNTIMES THIRD_PARTY"
 		CMAKE=${DESTDIR}${TARGETDIR}/bin/cmake
 		;;
 	IASL|iasl)
diff --git a/util/crossgcc/patches/clang-18.1.8.src_x86_baremetal.patch b/util/crossgcc/patches/clang-18.1.8.src_x86_baremetal.patch
deleted file mode 100644
index 61c608cbbe..0000000000
--- a/util/crossgcc/patches/clang-18.1.8.src_x86_baremetal.patch
+++ /dev/null
@@ -1,29 +0,0 @@
-diff --git a/lib/Driver/ToolChains/BareMetal.cpp b/lib/Driver/ToolChains/BareMetal.cpp
-index 852e0442..eb84a785 100644
---- a/lib/Driver/ToolChains/BareMetal.cpp
-+++ b/lib/Driver/ToolChains/BareMetal.cpp
-@@ -169,6 +169,12 @@ static bool isPPCBareMetal(const llvm::Triple &Triple) {
-          Triple.getEnvironment() == llvm::Triple::EABI;
- }
-
-+/// Is the triple x86_32 or x86_64 -*-none-elf?
-+static bool isX86BareMetal(const llvm::Triple &Triple) {
-+  return Triple.isX86() && Triple.getOS() == llvm::Triple::UnknownOS &&
-+    Triple.getEnvironmentName() == "elf";
-+}
-+
- static void findMultilibsFromYAML(const ToolChain &TC, const Driver &D,
-                                   StringRef MultilibPath, const ArgList &Args,
-                                   DetectedMultilibs &Result) {
-@@ -234,9 +240,10 @@ void BareMetal::findMultilibs(const Driver &D, const llvm::Triple &Triple,
-
- bool BareMetal::handlesTarget(const llvm::Triple &Triple) {
-   return isARMBareMetal(Triple) || isAArch64BareMetal(Triple) ||
--         isRISCVBareMetal(Triple) || isPPCBareMetal(Triple);
-+    isRISCVBareMetal(Triple) || isPPCBareMetal(Triple) || isX86BareMetal(Triple);
- }
-
-+
- Tool *BareMetal::buildLinker() const {
-   return new tools::baremetal::Linker(*this);
- }
diff --git a/util/crossgcc/patches/clang-21.1.8.src_x86_baremetal.patch b/util/crossgcc/patches/clang-21.1.8.src_x86_baremetal.patch
new file mode 100644
index 0000000000..809b290339
--- /dev/null
+++ b/util/crossgcc/patches/clang-21.1.8.src_x86_baremetal.patch
@@ -0,0 +1,25 @@
+diff -u a/lib/Driver/ToolChains/BareMetal.cpp b/lib/Driver/ToolChains/BareMetal.cpp
+--- a/lib/Driver/ToolChains/BareMetal.cpp
++++ b/lib/Driver/ToolChains/BareMetal.cpp
+@@ -51,6 +51,12 @@
+          Triple.getEnvironment() == llvm::Triple::EABI;
+ }
+ 
++/// Is the triple x86_32 or x86_64 -*-none-elf?
++static bool isX86BareMetal(const llvm::Triple &Triple) {
++  return Triple.isX86() && Triple.getOS() == llvm::Triple::UnknownOS &&
++    Triple.getEnvironmentName() == "elf";
++}
++
+ static bool findRISCVMultilibs(const Driver &D,
+                                const llvm::Triple &TargetTriple,
+                                const ArgList &Args, DetectedMultilibs &Result) {
+@@ -351,7 +357,7 @@
+ bool BareMetal::handlesTarget(const llvm::Triple &Triple) {
+   return arm::isARMEABIBareMetal(Triple) ||
+          aarch64::isAArch64BareMetal(Triple) || isRISCVBareMetal(Triple) ||
+-         isPPCBareMetal(Triple);
++         isPPCBareMetal(Triple) || isX86BareMetal(Triple);
+ }
+ 
+ Tool *BareMetal::buildLinker() const {
diff --git a/util/crossgcc/sum/clang-18.1.8.src.tar.xz.cksum b/util/crossgcc/sum/clang-18.1.8.src.tar.xz.cksum
deleted file mode 100644
index a517ab901a..0000000000
--- a/util/crossgcc/sum/clang-18.1.8.src.tar.xz.cksum
+++ /dev/null
@@ -1 +0,0 @@
-581e929ba0d9fafc555081ab18d8c3fdf4478ac2  tarballs/clang-18.1.8.src.tar.xz
diff --git a/util/crossgcc/sum/clang-21.1.8.src.tar.xz.cksum b/util/crossgcc/sum/clang-21.1.8.src.tar.xz.cksum
new file mode 100644
index 0000000000..243e5e2616
--- /dev/null
+++ b/util/crossgcc/sum/clang-21.1.8.src.tar.xz.cksum
@@ -0,0 +1 @@
+052b4b826aba886d0a3fada696445d2fb1ffec88  tarballs/clang-21.1.8.src.tar.xz
diff --git a/util/crossgcc/sum/clang-tools-extra-18.1.8.src.tar.xz.cksum b/util/crossgcc/sum/clang-tools-extra-18.1.8.src.tar.xz.cksum
deleted file mode 100644
index 6b9b67cb64..0000000000
--- a/util/crossgcc/sum/clang-tools-extra-18.1.8.src.tar.xz.cksum
+++ /dev/null
@@ -1 +0,0 @@
-32923b812700526b76451384e4662ca45360d564  tarballs/clang-tools-extra-18.1.8.src.tar.xz
diff --git a/util/crossgcc/sum/clang-tools-extra-21.1.8.src.tar.xz.cksum b/util/crossgcc/sum/clang-tools-extra-21.1.8.src.tar.xz.cksum
new file mode 100644
index 0000000000..0e31f14c51
--- /dev/null
+++ b/util/crossgcc/sum/clang-tools-extra-21.1.8.src.tar.xz.cksum
@@ -0,0 +1 @@
+2429c7b1836e6db177e26cf4c85b5a817cda7c62  tarballs/clang-tools-extra-21.1.8.src.tar.xz
diff --git a/util/crossgcc/sum/cmake-18.1.8.src.tar.xz.cksum b/util/crossgcc/sum/cmake-18.1.8.src.tar.xz.cksum
deleted file mode 100644
index d0e63313d9..0000000000
--- a/util/crossgcc/sum/cmake-18.1.8.src.tar.xz.cksum
+++ /dev/null
@@ -1 +0,0 @@
-1ea03e355b705b4cada3051bd7301a57daa19283  tarballs/cmake-18.1.8.src.tar.xz
diff --git a/util/crossgcc/sum/cmake-21.1.8.src.tar.xz.cksum b/util/crossgcc/sum/cmake-21.1.8.src.tar.xz.cksum
new file mode 100644
index 0000000000..6317498355
--- /dev/null
+++ b/util/crossgcc/sum/cmake-21.1.8.src.tar.xz.cksum
@@ -0,0 +1 @@
+da308aa4c0e80835e123771ebe3e5fbfc5244a45  tarballs/cmake-21.1.8.src.tar.xz
diff --git a/util/crossgcc/sum/compiler-rt-18.1.8.src.tar.xz.cksum b/util/crossgcc/sum/compiler-rt-18.1.8.src.tar.xz.cksum
deleted file mode 100644
index 711ef353c4..0000000000
--- a/util/crossgcc/sum/compiler-rt-18.1.8.src.tar.xz.cksum
+++ /dev/null
@@ -1 +0,0 @@
-6ecbfa5516b60adb4e4e60f991b0d8ddf5aab12a  tarballs/compiler-rt-18.1.8.src.tar.xz
diff --git a/util/crossgcc/sum/compiler-rt-21.1.8.src.tar.xz.cksum b/util/crossgcc/sum/compiler-rt-21.1.8.src.tar.xz.cksum
new file mode 100644
index 0000000000..2362125c5a
--- /dev/null
+++ b/util/crossgcc/sum/compiler-rt-21.1.8.src.tar.xz.cksum
@@ -0,0 +1 @@
+141a3877eedd036349feaddc0d303abeeff96b6c  tarballs/compiler-rt-21.1.8.src.tar.xz
diff --git a/util/crossgcc/sum/libunwind-18.1.8.src.tar.xz.cksum b/util/crossgcc/sum/libunwind-18.1.8.src.tar.xz.cksum
deleted file mode 100644
index d3819e303a..0000000000
--- a/util/crossgcc/sum/libunwind-18.1.8.src.tar.xz.cksum
+++ /dev/null
@@ -1 +0,0 @@
-5bee6cd2847f6d468861c78a21236e1c6fdc8374  tarballs/libunwind-18.1.8.src.tar.xz
diff --git a/util/crossgcc/sum/libunwind-21.1.8.src.tar.xz.cksum b/util/crossgcc/sum/libunwind-21.1.8.src.tar.xz.cksum
new file mode 100644
index 0000000000..6b0516a6b2
--- /dev/null
+++ b/util/crossgcc/sum/libunwind-21.1.8.src.tar.xz.cksum
@@ -0,0 +1 @@
+c71485804e2a8e531469ee461fc312218686d641  tarballs/libunwind-21.1.8.src.tar.xz
diff --git a/util/crossgcc/sum/lld-18.1.8.src.tar.xz.cksum b/util/crossgcc/sum/lld-18.1.8.src.tar.xz.cksum
deleted file mode 100644
index 490a83596e..0000000000
--- a/util/crossgcc/sum/lld-18.1.8.src.tar.xz.cksum
+++ /dev/null
@@ -1 +0,0 @@
-1cf1fa9848b05a07d3d52e69949d44003f2ab2af  tarballs/lld-18.1.8.src.tar.xz
diff --git a/util/crossgcc/sum/lld-21.1.8.src.tar.xz.cksum b/util/crossgcc/sum/lld-21.1.8.src.tar.xz.cksum
new file mode 100644
index 0000000000..6e98bb89dc
--- /dev/null
+++ b/util/crossgcc/sum/lld-21.1.8.src.tar.xz.cksum
@@ -0,0 +1 @@
+c41039defb66d59d292567fe1d3e4d28fc2dec70  tarballs/lld-21.1.8.src.tar.xz
diff --git a/util/crossgcc/sum/llvm-18.1.8.src.tar.xz.cksum b/util/crossgcc/sum/llvm-18.1.8.src.tar.xz.cksum
deleted file mode 100644
index 4845fb5b01..0000000000
--- a/util/crossgcc/sum/llvm-18.1.8.src.tar.xz.cksum
+++ /dev/null
@@ -1 +0,0 @@
-f9befa4cbef3f688ab48fca42449e13c5bcb872d  tarballs/llvm-18.1.8.src.tar.xz
diff --git a/util/crossgcc/sum/llvm-21.1.8.src.tar.xz.cksum b/util/crossgcc/sum/llvm-21.1.8.src.tar.xz.cksum
new file mode 100644
index 0000000000..a4ca09f05e
--- /dev/null
+++ b/util/crossgcc/sum/llvm-21.1.8.src.tar.xz.cksum
@@ -0,0 +1 @@
+5aea9c8a3b1f1fa7ddebc2d2cc6742d4a1ee569e  tarballs/llvm-21.1.8.src.tar.xz
diff --git a/util/crossgcc/sum/runtimes-18.1.8.src.tar.xz.cksum b/util/crossgcc/sum/runtimes-18.1.8.src.tar.xz.cksum
deleted file mode 100644
index fbee9941d1..0000000000
--- a/util/crossgcc/sum/runtimes-18.1.8.src.tar.xz.cksum
+++ /dev/null
@@ -1 +0,0 @@
-4a5ea2f22b2d81467e739f4b070cf7ff52785856  tarballs/runtimes-18.1.8.src.tar.xz
diff --git a/util/crossgcc/sum/runtimes-21.1.8.src.tar.xz.cksum b/util/crossgcc/sum/runtimes-21.1.8.src.tar.xz.cksum
new file mode 100644
index 0000000000..0022a20757
--- /dev/null
+++ b/util/crossgcc/sum/runtimes-21.1.8.src.tar.xz.cksum
@@ -0,0 +1 @@
+2edc085c606ef464cde44b5cbfb5727c59ae2fd3  tarballs/runtimes-21.1.8.src.tar.xz
diff --git a/util/crossgcc/sum/third-party-21.1.8.src.tar.xz.cksum b/util/crossgcc/sum/third-party-21.1.8.src.tar.xz.cksum
new file mode 100644
index 0000000000..654980e1a1
--- /dev/null
+++ b/util/crossgcc/sum/third-party-21.1.8.src.tar.xz.cksum
@@ -0,0 +1 @@
+a1a50bb1f6a02aa82ef6de5942b164061f9acbc4  tarballs/third-party-21.1.8.src.tar.xz

From d2f98171ee041513126aa5680b49ebfb845abd7a Mon Sep 17 00:00:00 2001
From: Pierce Chou <chou.pierce@inventec.corp-partner.google.com>
Date: Mon, 26 Jan 2026 13:56:51 +0800
Subject: [PATCH 3214/3886] mb/google/ocelot/var/ocicat: Fix ELAN Touchpad i2c
 error

Revised the GPP_E18 configuration to use GPI IRQ.

BUG=b:473955137
TEST=Confirmed that the ELAN touchpad functionality
is operating correctly,and no occurrences of the
following error message are observed in the logs:
elan_i2c i2c-ELAN0000:00: invalid report id data (0)

Change-Id: Ie8fd2f13f5db4f830e4ffcd88a5a7b55f4d9bee3
Signed-off-by: Pierce Chou <chou.pierce@inventec.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90908
Reviewed-by: Pranava Y N <pranavayn@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/google/ocelot/variants/ocicat/gpio.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/mainboard/google/ocelot/variants/ocicat/gpio.c b/src/mainboard/google/ocelot/variants/ocicat/gpio.c
index 25aa28c73b..3c2f44b1c9 100644
--- a/src/mainboard/google/ocelot/variants/ocicat/gpio.c
+++ b/src/mainboard/google/ocelot/variants/ocicat/gpio.c
@@ -209,8 +209,8 @@ static const struct pad_config gpio_table[] = {
 	PAD_NC(GPP_E16, NONE),
 	/* GPP_E17:     NC */
 	PAD_NC(GPP_E17, NONE),
-	/* GPP_E18:     THC0_SPI1_INT_N_TCH_PNL1 */
-	PAD_CFG_NF(GPP_E18, NONE, DEEP, NF3),
+	/* GPP_E18:     TCHPAD_INT_ODL */
+	PAD_CFG_GPI_IRQ_WAKE(GPP_E18, NONE, PWROK, LEVEL, INVERT),
 	/* GPP_E19:     NC */
 	PAD_NC(GPP_E19, NONE),
 	/* GPP_E20:     NC */

From 025d45ac76fab3777363bc7400080c7b49a49d37 Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Wed, 28 Jan 2026 20:14:59 -0600
Subject: [PATCH 3215/3886] drivers/genesyslogic/gl9763e: Generate ACPI device
 for attached eMMC

Generate an 'EMMC' ACPI device under the PCIe root port to which the
GL9763E is attached. The EMMC device contains a child CARD device whose
_RMV method returns 0. This allows Windows to identify the eMMC as a
fixed internal drive instead of a removable one.

This fixes an issue where the Windows 11 installer fails around 55%
with a generic 'Windows 11 installation has failed' error. Install
logs show the failure is due to Windows identifying the storage
device as removable and aborting (error 0xC1420134).

TEST=build/boot Win11 installer on google/taeko with eMMC installed,
verify Windows installer identifies it as a non-removable drive via
diskpart, and install completes successfully.

Change-Id: I51e59cb9e9dc2459724138b4bd404fb1eea64680
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90982
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
---
 src/drivers/genesyslogic/gl9763e/gl9763e.c | 50 ++++++++++++++++++++++
 1 file changed, 50 insertions(+)

diff --git a/src/drivers/genesyslogic/gl9763e/gl9763e.c b/src/drivers/genesyslogic/gl9763e/gl9763e.c
index 98e69bb3f8..a80a3d48db 100644
--- a/src/drivers/genesyslogic/gl9763e/gl9763e.c
+++ b/src/drivers/genesyslogic/gl9763e/gl9763e.c
@@ -8,6 +8,9 @@
 #include <device/pciexp.h>
 #include <device/pci_ops.h>
 #include <device/pci_ids.h>
+#include <acpi/acpi.h>
+#include <acpi/acpi_device.h>
+#include <acpi/acpigen.h>
 #include "gl9763e.h"
 
 static void gl9763e_init(struct device *dev)
@@ -54,12 +57,59 @@ static void gl9763e_init(struct device *dev)
 	pci_update_config32(dev, VHS, ~VHS_REV_MASK, VHS_REV_R);
 }
 
+/*
+ * Generate ACPI device for on-board eMMC (SD Host Controller + fixed CARD) under the
+ * root port so the OS sees non-removable storage. Scope is the parent root port
+ * (e.g. \_SB.PCI0.RP09).
+ *
+ * Generated ASL:
+ * Scope (\_SB.PCI0.RPxx) {
+ *     Device (EMMC) {
+ *         Name (_ADR, 0x00000000)
+ *         Device (CARD) {
+ *             Name (_ADR, 0x00000008)
+ *             Method (_RMV, 0, NotSerialized) {
+ *                 Return (0)  // Fixed (not removable)
+ *             }
+ *         }
+ *     }
+ * }
+ */
+static void gl9763e_fill_ssdt(const struct device *dev)
+{
+	const char *scope;
+
+	if (!is_dev_enabled(dev))
+		return;
+
+	scope = acpi_device_scope(dev);
+	if (!scope)
+		return;
+
+	/* Emit EMMC device under root port so OS sees fixed (non-removable) storage */
+	acpigen_write_scope(scope);
+	acpigen_write_device("EMMC");
+	acpigen_write_name_integer("_ADR", 0x0);
+
+	/* CARD child: slot at address 0x08, not removable */
+	acpigen_write_device("CARD");
+	acpigen_write_name_integer("_ADR", 0x8);
+	acpigen_write_method_serialized("_RMV", 0);
+	acpigen_write_return_integer(0);  /* Fixed (not removable) */
+	acpigen_write_method_end();
+	acpigen_write_device_end();  /* CARD */
+
+	acpigen_write_device_end();  /* EMMC */
+	acpigen_write_scope_end();
+}
+
 static struct device_operations gl9763e_ops = {
 	.read_resources		= pci_dev_read_resources,
 	.set_resources		= pci_dev_set_resources,
 	.enable_resources	= pci_dev_enable_resources,
 	.ops_pci		= &pci_dev_ops_pci,
 	.init			= gl9763e_init,
+	.acpi_fill_ssdt		= gl9763e_fill_ssdt,
 };
 
 static const unsigned short pci_device_ids[] = {

From 261274992d03a41c75819c1e7b24bdbb5e4eba7a Mon Sep 17 00:00:00 2001
From: Alicja Michalska <alicja.michalska@9elements.com>
Date: Thu, 22 Jan 2026 02:03:56 +0100
Subject: [PATCH 3216/3886] soc/intel/pantherlake: Enable all RootPorts on
 PTL-H484
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

According to EDS #872188, PTL-H484 has 8 more PCIe
lanes than PTL-H404 and 12Xe SKUs.

I believe there's been a mixup during bringup, as PCIe ACPI tables are
"gated" for an SKU with more PCIe 5.0 lanes.

To be exact, in a file: "src/soc/intel/pantherlake/acpi/ptl_pcie.asl"
we can notice PCIe 5.0 RootPorts depending on SOC_INTEL_PANTHERLAKE_H.
Google/Fatcat boards seem to be using PANTHERLAKE_U_H instead.

TEST: Build/boot intel/pantherlake_crb. Make sure Linux doesn't report
PCIe routing errors.

Change-Id: I1d136cf1959a3851d0ac37b256fd4df28a8d30df
Signed-off-by: Alicja Michalska <alicja.michalska@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90863
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Pranava Y N <pranavayn@google.com>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
---
 src/soc/intel/pantherlake/Kconfig | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/soc/intel/pantherlake/Kconfig b/src/soc/intel/pantherlake/Kconfig
index 59369a6a46..45a8c8376e 100644
--- a/src/soc/intel/pantherlake/Kconfig
+++ b/src/soc/intel/pantherlake/Kconfig
@@ -253,8 +253,8 @@ config MAX_TBT_ROOT_PORTS
 config MAX_ROOT_PORTS
 	int
 	default 6 if SOC_INTEL_WILDCATLAKE
-	default 10 if SOC_INTEL_PANTHERLAKE_H
-	default 12
+	default 12 if SOC_INTEL_PANTHERLAKE_H
+	default 10
 
 config MAX_PCIE_CLOCK_SRC
 	int

From e2d3d9758dea284f83ef12fa63a40b377439ae4d Mon Sep 17 00:00:00 2001
From: Nicholas Chin <nic.c3.14@gmail.com>
Date: Sat, 24 Jan 2026 19:20:21 -0700
Subject: [PATCH 3217/3886] soc/intel/skylake: Set pad_cfg_lock_offset in
 skl_gpio_communities

The GPIO pad community definition for Skylake does not set the
pad_cfg_lock_offset member, leading to an "offset not defined for pad"
error when trying to lock a pad config in gpio_non_smm_lock_pad(). This
must be set to the offset of the first Pad Configuration Lock register
within each GPIO communities register blocks which can be found in the
GPIO sections of the processor I/O and PCH-H datasheets.

References:
Skylake-U/Y: Intel 332691
Sunrise Point-H: Intel 332996
Kaby Lake-U/Y: Intel 334659
Union Point-H: Intel 335193

Change-Id: I2991a7cbfb333d9fdda008cbb4cbc272aa508ef0
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90884
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
---
 src/soc/intel/skylake/gpio.c                  |  4 ++++
 src/soc/intel/skylake/include/soc/gpio_defs.h | 13 +++++++++++++
 2 files changed, 17 insertions(+)

diff --git a/src/soc/intel/skylake/gpio.c b/src/soc/intel/skylake/gpio.c
index 50628a7d98..00099794d8 100644
--- a/src/soc/intel/skylake/gpio.c
+++ b/src/soc/intel/skylake/gpio.c
@@ -57,6 +57,7 @@ static const struct pad_community skl_gpio_communities[] = {
 		.last_pad = GPP_B23,
 		.num_gpi_regs = NUM_GPIO_COM0_GPI_REGS,
 		.pad_cfg_base = PAD_CFG_BASE,
+		.pad_cfg_lock_offset = PAD_CFG_LOCK_OFFSET_COM0,
 		.host_own_reg_0 = HOSTSW_OWN_REG_0,
 		.gpi_int_sts_reg_0 = GPI_INT_STS_0,
 		.gpi_int_en_reg_0 = GPI_INT_EN_0,
@@ -81,6 +82,7 @@ static const struct pad_community skl_gpio_communities[] = {
 #endif
 		.num_gpi_regs = NUM_GPIO_COM1_GPI_REGS,
 		.pad_cfg_base = PAD_CFG_BASE,
+		.pad_cfg_lock_offset = PAD_CFG_LOCK_OFFSET_COM1,
 		.host_own_reg_0 = HOSTSW_OWN_REG_0,
 		.gpi_int_sts_reg_0 = GPI_INT_STS_0,
 		.gpi_int_en_reg_0 = GPI_INT_EN_0,
@@ -106,6 +108,7 @@ static const struct pad_community skl_gpio_communities[] = {
 #endif
 		.num_gpi_regs = NUM_GPIO_COM3_GPI_REGS,
 		.pad_cfg_base = PAD_CFG_BASE,
+		.pad_cfg_lock_offset = PAD_CFG_LOCK_OFFSET_COM3,
 		.host_own_reg_0 = HOSTSW_OWN_REG_0,
 		.gpi_int_sts_reg_0 = GPI_INT_STS_0,
 		.gpi_int_en_reg_0 = GPI_INT_EN_0,
@@ -126,6 +129,7 @@ static const struct pad_community skl_gpio_communities[] = {
 		.last_pad = GPD11,
 		.num_gpi_regs = NUM_GPIO_COM2_GPI_REGS,
 		.pad_cfg_base = PAD_CFG_BASE,
+		.pad_cfg_lock_offset = PAD_CFG_LOCK_OFFSET_COM2,
 		.host_own_reg_0 = HOSTSW_OWN_REG_0,
 		.gpi_int_sts_reg_0 = GPI_INT_STS_0,
 		.gpi_int_en_reg_0 = GPI_INT_EN_0,
diff --git a/src/soc/intel/skylake/include/soc/gpio_defs.h b/src/soc/intel/skylake/include/soc/gpio_defs.h
index 0e98b89169..f91dd63300 100644
--- a/src/soc/intel/skylake/include/soc/gpio_defs.h
+++ b/src/soc/intel/skylake/include/soc/gpio_defs.h
@@ -209,6 +209,19 @@
 #define  GPIO_DRIVER_IRQ_ROUTE_IRQ14   0
 #define  GPIO_DRIVER_IRQ_ROUTE_IRQ15   8
 #define HOSTSW_OWN_REG_0	0xd0
+
+#if CONFIG(SKYLAKE_SOC_PCH_H)
+#define PAD_CFG_LOCK_OFFSET_COM0 0xa0
+#define PAD_CFG_LOCK_OFFSET_COM1 0x90
+#define PAD_CFG_LOCK_OFFSET_COM2 0x90
+#define PAD_CFG_LOCK_OFFSET_COM3 0x90
+#else
+#define PAD_CFG_LOCK_OFFSET_COM0 0xa0
+#define PAD_CFG_LOCK_OFFSET_COM1 0xa0
+#define PAD_CFG_LOCK_OFFSET_COM2 0xa0
+#define PAD_CFG_LOCK_OFFSET_COM3 0xa0
+#endif /* CONFIG(SKYLAKE_SOC_PCH_H) */
+
 #define PAD_CFG_BASE		0x400
 #define GPI_INT_STS_0		0x100
 #define GPI_INT_EN_0		0x120

From 05c7869dd517b76e5612cb3da5824449ccf67a1c Mon Sep 17 00:00:00 2001
From: Riku Viitanen <riku.viitanen@protonmail.com>
Date: Wed, 12 Nov 2025 23:05:17 +0200
Subject: [PATCH 3218/3886] util/inteltool: Support more Comet Lake-S IDs
 (Q470)

Tested on a HP ProDesk 400 G7, with an i5-10500 and a Q470 chipset.

Dumping MCH, SPI/BIOS CONTROL, LPC/eSPI, GPIO, EPBAR and DMIBAR work.

Change-Id: I0eca3a72c42b0cb85bcda8502bccbb4a80704b3b
Signed-off-by: Riku Viitanen <riku.viitanen@protonmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90012
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
---
 util/inteltool/gpio.c        |  1 +
 util/inteltool/gpio_groups.c |  1 +
 util/inteltool/inteltool.c   | 11 +++++++++++
 util/inteltool/inteltool.h   |  6 ++++++
 util/inteltool/lpc.c         |  1 +
 util/inteltool/memory.c      |  5 +++++
 util/inteltool/pcie.c        | 15 +++++++++++++++
 util/inteltool/pcr.c         |  1 +
 util/inteltool/rootcmplx.c   |  1 +
 util/inteltool/spi.c         |  2 ++
 10 files changed, 44 insertions(+)

diff --git a/util/inteltool/gpio.c b/util/inteltool/gpio.c
index 07f39593a0..c0005bf802 100644
--- a/util/inteltool/gpio.c
+++ b/util/inteltool/gpio.c
@@ -1119,6 +1119,7 @@ int print_gpios(struct pci_dev *sb, int show_all, int show_diffs)
 	case PCI_DEVICE_ID_INTEL_HM770:
 	case PCI_DEVICE_ID_INTEL_WM790:
 	case PCI_DEVICE_ID_INTEL_HM470:
+	case PCI_DEVICE_ID_INTEL_Q470:
 	case PCI_DEVICE_ID_INTEL_C262:
 	case PCI_DEVICE_ID_INTEL_C266:
 	case PCI_DEVICE_ID_INTEL_ADL_P:
diff --git a/util/inteltool/gpio_groups.c b/util/inteltool/gpio_groups.c
index c8fbdb4439..77b808fff9 100644
--- a/util/inteltool/gpio_groups.c
+++ b/util/inteltool/gpio_groups.c
@@ -187,6 +187,7 @@ const struct gpio_community *const *get_gpio_communities(struct pci_dev *const s
 	case PCI_DEVICE_ID_INTEL_HM370:
 	case PCI_DEVICE_ID_INTEL_CM246:
 	case PCI_DEVICE_ID_INTEL_HM470:
+	case PCI_DEVICE_ID_INTEL_Q470:
 		*community_count = ARRAY_SIZE(cannonlake_pch_h_communities);
 		*pad_stepping = 16;
 		return cannonlake_pch_h_communities;
diff --git a/util/inteltool/inteltool.c b/util/inteltool/inteltool.c
index 0ed9b8331c..bc40e57daa 100644
--- a/util/inteltool/inteltool.c
+++ b/util/inteltool/inteltool.c
@@ -156,6 +156,16 @@ static const struct {
 	  "10th generation (Comet Lake-H family) Core Processor (Mobile)" },
 	{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_CML_H_4_2,
 	  "10th generation (Comet Lake-H family) Core Processor (Mobile)" },
+	{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_CML_S_10,
+	  "10th generation (Comet Lake-S family) Core Processor (Desktop)" },
+	{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_CML_S_8,
+	  "10th generation (Comet Lake-S family) Core Processor (Desktop)" },
+	{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_CML_S_6,
+	  "10th generation (Comet Lake-S family) Core Processor (Desktop)" },
+	{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_CML_S_4,
+	  "10th generation (Comet Lake-S family) Core Processor (Desktop)" },
+	{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_CML_S_2,
+	  "10th generation (Comet Lake-S family) Core Processor (Desktop)" },
 	{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_HEWITTLAKE,
 	  "Xeon E7 v4/Xeon E5 v4/Xeon E3 v4/Xeon D (Hewitt Lake)" },
 	{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SAPPHIRERAPIDS_SP,
@@ -441,6 +451,7 @@ static const struct {
 	{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_GLK_LPC, "Gemini Lake" },
 	{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_H510, "H510" },
 	{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_H570, "H570" },
+	{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_Q470, "Q470" },
 	{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_HM470, "HM470" },
 	{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_Z590, "Z590" },
 	{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_Q570, "Q570" },
diff --git a/util/inteltool/inteltool.h b/util/inteltool/inteltool.h
index a9419e3431..3a173da19c 100644
--- a/util/inteltool/inteltool.h
+++ b/util/inteltool/inteltool.h
@@ -224,6 +224,7 @@ static inline uint32_t inl(unsigned port)
 #define PCI_DEVICE_ID_INTEL_WM590		0x4389
 #define PCI_DEVICE_ID_INTEL_QM580		0x438a
 #define PCI_DEVICE_ID_INTEL_HM570		0x438b
+#define PCI_DEVICE_ID_INTEL_Q470		0x0687
 #define PCI_DEVICE_ID_INTEL_HM470		0x068d
 #define PCI_DEVICE_ID_INTEL_C252		0x438c
 #define PCI_DEVICE_ID_INTEL_C256		0x438d
@@ -403,6 +404,11 @@ static inline uint32_t inl(unsigned port)
 #define PCI_DEVICE_ID_INTEL_CORE_CML_H_8_2	0x9b44 /* Cometlake H 8+2 (Mobile) */
 #define PCI_DEVICE_ID_INTEL_CORE_CML_H_6_2	0x9b54 /* Cometlake H 6+2 (Mobile) */
 #define PCI_DEVICE_ID_INTEL_CORE_CML_H_4_2	0x9b64 /* Cometlake H 4+2 (Mobile) */
+#define PCI_DEVICE_ID_INTEL_CORE_CML_S_10	0x9b33 /* Cometlake S 10 (Desktop) */
+#define PCI_DEVICE_ID_INTEL_CORE_CML_S_8	0x9b43 /* Cometlake S 8 (Desktop) */
+#define PCI_DEVICE_ID_INTEL_CORE_CML_S_6	0x9b53 /* Cometlake S 6 (Desktop) */
+#define PCI_DEVICE_ID_INTEL_CORE_CML_S_4	0x9b63 /* Cometlake S 4 (Desktop) */
+#define PCI_DEVICE_ID_INTEL_CORE_CML_S_2	0x9b73 /* Cometlake S 2 (Desktop) */
 #define PCI_DEVICE_ID_INTEL_CORE_TGL_ID_U_2	0x9a04 /* Tigerlake UP3 2 Cores */
 #define PCI_DEVICE_ID_INTEL_CORE_TGL_ID_U_4	0x9a14 /* Tigerlake UP3 4 Cores */
 #define PCI_DEVICE_ID_INTEL_CORE_TGL_ID_Y_2	0x9a02 /* Tigerlake UP4 2 Cores */
diff --git a/util/inteltool/lpc.c b/util/inteltool/lpc.c
index 9fbec66402..711e64b1a2 100644
--- a/util/inteltool/lpc.c
+++ b/util/inteltool/lpc.c
@@ -151,6 +151,7 @@ int print_lpc(struct pci_dev *sb, struct pci_access *pacc)
 		}
 		break;
 	case PCI_DEVICE_ID_INTEL_HM470:
+	case PCI_DEVICE_ID_INTEL_Q470:
 		dev = pci_get_dev(pacc, sb->domain, sb->bus, sb->dev, 0);
 		if (!dev) {
 			printf("LPC/eSPI interface not found.\n");
diff --git a/util/inteltool/memory.c b/util/inteltool/memory.c
index 608a95533a..0fb36aa38c 100644
--- a/util/inteltool/memory.c
+++ b/util/inteltool/memory.c
@@ -232,6 +232,11 @@ int print_mchbar(struct pci_dev *nb, struct pci_access *pacc, const char *dump_s
 	case PCI_DEVICE_ID_INTEL_CORE_CML_H_8_2:
 	case PCI_DEVICE_ID_INTEL_CORE_CML_H_6_2:
 	case PCI_DEVICE_ID_INTEL_CORE_CML_H_4_2:
+	case PCI_DEVICE_ID_INTEL_CORE_CML_S_10:
+	case PCI_DEVICE_ID_INTEL_CORE_CML_S_8:
+	case PCI_DEVICE_ID_INTEL_CORE_CML_S_6:
+	case PCI_DEVICE_ID_INTEL_CORE_CML_S_4:
+	case PCI_DEVICE_ID_INTEL_CORE_CML_S_2:
 		mchbar_phys = pci_read_long(nb, 0x48);
 		mchbar_phys |= ((uint64_t)pci_read_long(nb, 0x4c)) << 32;
 		mchbar_phys &= 0x0000007fffff8000UL; /* 38:15 */
diff --git a/util/inteltool/pcie.c b/util/inteltool/pcie.c
index 06a09df3ca..6544bac5a7 100644
--- a/util/inteltool/pcie.c
+++ b/util/inteltool/pcie.c
@@ -327,6 +327,11 @@ int print_epbar(struct pci_dev *nb)
 	case PCI_DEVICE_ID_INTEL_CORE_CML_H_8_2:
 	case PCI_DEVICE_ID_INTEL_CORE_CML_H_6_2:
 	case PCI_DEVICE_ID_INTEL_CORE_CML_H_4_2:
+	case PCI_DEVICE_ID_INTEL_CORE_CML_S_10:
+	case PCI_DEVICE_ID_INTEL_CORE_CML_S_8:
+	case PCI_DEVICE_ID_INTEL_CORE_CML_S_6:
+	case PCI_DEVICE_ID_INTEL_CORE_CML_S_4:
+	case PCI_DEVICE_ID_INTEL_CORE_CML_S_2:
 		epbar_phys = pci_read_long(nb, 0x40) & 0xfffffffe;
 		epbar_phys |= ((uint64_t)pci_read_long(nb, 0x44)) << 32;
 		break;
@@ -474,6 +479,11 @@ int print_dmibar(struct pci_dev *nb)
 	case PCI_DEVICE_ID_INTEL_CORE_CML_H_8_2:
 	case PCI_DEVICE_ID_INTEL_CORE_CML_H_6_2:
 	case PCI_DEVICE_ID_INTEL_CORE_CML_H_4_2:
+	case PCI_DEVICE_ID_INTEL_CORE_CML_S_10:
+	case PCI_DEVICE_ID_INTEL_CORE_CML_S_8:
+	case PCI_DEVICE_ID_INTEL_CORE_CML_S_6:
+	case PCI_DEVICE_ID_INTEL_CORE_CML_S_4:
+	case PCI_DEVICE_ID_INTEL_CORE_CML_S_2:
 		dmi_registers = cometlake_dmi_registers;
 		size = ARRAY_SIZE(cometlake_dmi_registers);
 		dmibar_phys = pci_read_long(nb, 0x68);
@@ -608,6 +618,11 @@ int print_pciexbar(struct pci_dev *nb)
 	case PCI_DEVICE_ID_INTEL_CORE_CML_H_8_2:
 	case PCI_DEVICE_ID_INTEL_CORE_CML_H_6_2:
 	case PCI_DEVICE_ID_INTEL_CORE_CML_H_4_2:
+	case PCI_DEVICE_ID_INTEL_CORE_CML_S_10:
+	case PCI_DEVICE_ID_INTEL_CORE_CML_S_8:
+	case PCI_DEVICE_ID_INTEL_CORE_CML_S_6:
+	case PCI_DEVICE_ID_INTEL_CORE_CML_S_4:
+	case PCI_DEVICE_ID_INTEL_CORE_CML_S_2:
 		pciexbar_reg = pci_read_long(nb, 0x60);
 		pciexbar_reg |= ((uint64_t)pci_read_long(nb, 0x64)) << 32;
 		break;
diff --git a/util/inteltool/pcr.c b/util/inteltool/pcr.c
index 8654e32a89..cfc12911f3 100644
--- a/util/inteltool/pcr.c
+++ b/util/inteltool/pcr.c
@@ -142,6 +142,7 @@ void pcr_init(struct pci_dev *const sb)
 	case PCI_DEVICE_ID_INTEL_C256:
 	case PCI_DEVICE_ID_INTEL_W580:
 	case PCI_DEVICE_ID_INTEL_HM470:
+	case PCI_DEVICE_ID_INTEL_Q470:
 	case PCI_DEVICE_ID_INTEL_CANNONPOINT_LP_U_PREM:
 	case PCI_DEVICE_ID_INTEL_COMETPOINT_LP_U_PREM:
 	case PCI_DEVICE_ID_INTEL_COMETPOINT_LP_U_BASE:
diff --git a/util/inteltool/rootcmplx.c b/util/inteltool/rootcmplx.c
index a11cf5f2e8..46f7858feb 100644
--- a/util/inteltool/rootcmplx.c
+++ b/util/inteltool/rootcmplx.c
@@ -126,6 +126,7 @@ int print_rcba(struct pci_dev *sb)
 	case PCI_DEVICE_ID_INTEL_ICH5:
 	case PCI_DEVICE_ID_INTEL_ADL_N:
 	case PCI_DEVICE_ID_INTEL_HM470:
+	case PCI_DEVICE_ID_INTEL_Q470:
 		printf("This southbridge does not have RCBA.\n");
 		return 1;
 	default:
diff --git a/util/inteltool/spi.c b/util/inteltool/spi.c
index 9c3d2f12f5..6e869a2da9 100644
--- a/util/inteltool/spi.c
+++ b/util/inteltool/spi.c
@@ -351,6 +351,7 @@ static int print_bioscntl(struct pci_dev *sb)
 		break;
 	case PCI_DEVICE_ID_INTEL_ADL_N:
 	case PCI_DEVICE_ID_INTEL_HM470:
+	case PCI_DEVICE_ID_INTEL_Q470:
 		bios_cntl = pci_read_byte(sb, 0xdc);
 		bios_cntl_register = adl_pch_bios_cntl_registers;
 		size = ARRAY_SIZE(adl_pch_bios_cntl_registers);
@@ -534,6 +535,7 @@ static int print_spibar(struct pci_dev *sb, struct pci_access *pacc) {
 		size = ARRAY_SIZE(elkhart_spi_bar_registers);
 		break;
 	case PCI_DEVICE_ID_INTEL_HM470:
+	case PCI_DEVICE_ID_INTEL_Q470:
 		if (get_espibar_phys(sb, pacc, 5, 0x10, 0xfffff000, &rcba_phys))
 			return 1;
 		rcba_size = 4096;

From 9263722f416cbb9948d4212b2d700ae2933ccf17 Mon Sep 17 00:00:00 2001
From: Subrata Banik <subratabanik@google.com>
Date: Fri, 30 Jan 2026 15:04:26 +0530
Subject: [PATCH 3219/3886] mb/google/fatcat: Refine low battery LED alert
 conditions

Update platform_romstage_pre_mem() to only trigger the red LED alert
when the lid is closed.

Previously, the critical low battery alert would trigger regardless of
the lid state. Checking the lid switch ensures the visual alert is
targeted at "closed-lid" scenarios where the user needs a physical
indicator of a power-critical state that prevents booting.

Change-Id: I9833fb26df9c31989abec142536e1fe7efb93c10
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91007
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
---
 src/mainboard/google/fatcat/romstage.c | 9 +++++++--
 1 file changed, 7 insertions(+), 2 deletions(-)

diff --git a/src/mainboard/google/fatcat/romstage.c b/src/mainboard/google/fatcat/romstage.c
index 2b3452eff8..4e3c5b764a 100644
--- a/src/mainboard/google/fatcat/romstage.c
+++ b/src/mainboard/google/fatcat/romstage.c
@@ -2,6 +2,7 @@
 
 #include <arch/romstage.h>
 #include <baseboard/variants.h>
+#include <bootmode.h>
 #include <ec/google/chromeec/ec.h>
 #include <fsp/api.h>
 #include <soc/romstage.h>
@@ -48,7 +49,11 @@ void mainboard_memory_init_params(FSPM_UPD *memupd)
 
 void platform_romstage_pre_mem(void)
 {
-	/* Set LED to Red to alert the user visually */
-	if (CONFIG(EC_GOOGLE_CHROMEEC) && google_chromeec_is_critically_low_on_battery())
+	/*
+	 * Only alert the user (set LED to red in color) if the lid is closed and the battery
+	 * is critically low without AC power.
+	 */
+	if (CONFIG(EC_GOOGLE_CHROMEEC) && CONFIG(VBOOT_LID_SWITCH) && !get_lid_switch() &&
+			 google_chromeec_is_critically_low_on_battery())
 		google_chromeec_set_lightbar_rgb(0xff, 0xff, 0x00, 0x00);
 }

From 781a8a98f105ed40199863f90e7243f8eee382e8 Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Fri, 30 Jan 2026 20:02:57 +0000
Subject: [PATCH 3220/3886] starlabs/starlite_adl: hide touchscreen CFR when
 accel off

The touchscreen device is dependent on the accelerometer on starlite_adl,
so offer the touchscreen CFR option only when the accelerometer option is
enabled.

Implement a new weak cfr_touchscreen_update() callback in the starlabs
common CFR code and override it in starlite_adl to suppress the
touchscreen option when accelerometer is disabled

Change-Id: I4bab6ccb92c40190014ab55200ff214064d5d2ae
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91024
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
---
 src/mainboard/starlabs/common/cfr/cfr.c            | 5 +++++
 src/mainboard/starlabs/common/include/common/cfr.h | 3 ++-
 src/mainboard/starlabs/starlite_adl/cfr.c          | 7 +++++++
 3 files changed, 14 insertions(+), 1 deletion(-)

diff --git a/src/mainboard/starlabs/common/cfr/cfr.c b/src/mainboard/starlabs/common/cfr/cfr.c
index 70899d21b1..44ee68323e 100644
--- a/src/mainboard/starlabs/common/cfr/cfr.c
+++ b/src/mainboard/starlabs/common/cfr/cfr.c
@@ -9,6 +9,11 @@ void __weak cfr_card_reader_update(struct sm_object *new_obj)
 	(void)new_obj;
 }
 
+void __weak cfr_touchscreen_update(struct sm_object *new_obj)
+{
+	(void)new_obj;
+}
+
 static const struct cfr_default_override starlabs_cfr_overrides[] = {
 	CFR_OVERRIDE_ENUM("pciexp_aspm", ASPM_L0S_L1),
 	CFR_OVERRIDE_END
diff --git a/src/mainboard/starlabs/common/include/common/cfr.h b/src/mainboard/starlabs/common/include/common/cfr.h
index 4613b94fbd..b62b39701e 100644
--- a/src/mainboard/starlabs/common/include/common/cfr.h
+++ b/src/mainboard/starlabs/common/include/common/cfr.h
@@ -8,6 +8,7 @@
 #include <common/powercap.h>
 
 void cfr_card_reader_update(struct sm_object *new_obj);
+void cfr_touchscreen_update(struct sm_object *new_obj);
 void starlabs_cfr_register_overrides(void);
 
 static const struct sm_object accelerometer = SM_DECLARE_BOOL({
@@ -131,7 +132,7 @@ static const struct sm_object touchscreen = SM_DECLARE_BOOL({
 	.ui_name	= "Touchscreen",
 	.ui_helptext	= "Enable or disable the built-in touch-screen",
 	.default_value	= true,
-});
+}, WITH_CALLBACK(cfr_touchscreen_update));
 
 static const struct sm_object vpu = SM_DECLARE_BOOL({
 	.opt_name	= "vpu",
diff --git a/src/mainboard/starlabs/starlite_adl/cfr.c b/src/mainboard/starlabs/starlite_adl/cfr.c
index 9526992fd5..004cd75945 100644
--- a/src/mainboard/starlabs/starlite_adl/cfr.c
+++ b/src/mainboard/starlabs/starlite_adl/cfr.c
@@ -7,6 +7,7 @@
 #include <intelblocks/cfr.h>
 #include <device/i2c_bus.h>
 #include <device/i2c_simple.h>
+#include <option.h>
 #include <static.h>
 #include <variants.h>
 #include <common/cfr.h>
@@ -19,6 +20,12 @@ void cfr_card_reader_update(struct sm_object *new_obj)
 		new_obj->sm_bool.flags = CFR_OPTFLAG_SUPPRESS;
 }
 
+void cfr_touchscreen_update(struct sm_object *new_obj)
+{
+	if (get_uint_option("accelerometer", 1) == 0)
+		new_obj->sm_bool.flags = CFR_OPTFLAG_SUPPRESS;
+}
+
 static struct sm_obj_form performance_group = {
 	.ui_name = "Performance",
 	.obj_list = (const struct sm_object *[]) {

From 616469062acb2a60bac48dd3aeefea37f9ae1c3e Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Thu, 29 Jan 2026 12:35:49 +0000
Subject: [PATCH 3221/3886] soc/intel/common: Add CFR dependencies for PCIe
 ASPM
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Make PCIe ASPM/L1SS CFR options depend on PCIe Clock Power Management
so the setup UI can hide them when CLK PM is disabled.

Change-Id: I7dc778bc2d6fb15d6062a4ab855bc8b700c22fad
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90996
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
---
 .../common/block/include/intelblocks/cfr.h    | 46 +++++++++++++------
 1 file changed, 32 insertions(+), 14 deletions(-)

diff --git a/src/soc/intel/common/block/include/intelblocks/cfr.h b/src/soc/intel/common/block/include/intelblocks/cfr.h
index e31af7f4c9..00785ae2eb 100644
--- a/src/soc/intel/common/block/include/intelblocks/cfr.h
+++ b/src/soc/intel/common/block/include/intelblocks/cfr.h
@@ -60,6 +60,35 @@ static const struct sm_object power_on_after_fail_bool = SM_DECLARE_BOOL({
 });
 
 /* PCIe PCH RP ASPM */
+static void update_pcie_aspm(struct sm_object *new)
+{
+	if (!CONFIG(PCIEXP_ASPM))
+		new->sm_enum.flags |= CFR_OPTFLAG_SUPPRESS;
+}
+
+static void update_pcie_aspm_cpu(struct sm_object *new)
+{
+	if (!CONFIG(PCIEXP_ASPM) || !CONFIG(HAS_INTEL_CPU_ROOT_PORTS))
+		new->sm_enum.flags |= CFR_OPTFLAG_SUPPRESS;
+}
+
+static void update_pcie_l1ss(struct sm_object *new)
+{
+	if (!CONFIG(PCIEXP_ASPM) || !CONFIG(PCIEXP_L1_SUB_STATE))
+		new->sm_enum.flags |= CFR_OPTFLAG_SUPPRESS;
+}
+
+/* PCIe Clock PM */
+static const struct sm_object pciexp_clk_pm = SM_DECLARE_BOOL({
+	.opt_name	= "pciexp_clk_pm",
+	.ui_name	= "PCIe Clock Power Management",
+	.ui_helptext	= "Enables or disables power management for the PCIe clock. When"
+			  " enabled, it reduces power consumption during idle states."
+			  " This can help lower overall energy use but may impact"
+			  " performance in power-sensitive tasks.",
+	.default_value	= true,
+});
+
 static const struct sm_object pciexp_aspm = SM_DECLARE_ENUM({
 	.opt_name	= "pciexp_aspm",
 	.ui_name	= "PCIe PCH RP ASPM",
@@ -74,7 +103,7 @@ static const struct sm_object pciexp_aspm = SM_DECLARE_ENUM({
 				{ "L0sL1",	ASPM_L0S_L1	},
 				{ "Auto",	ASPM_AUTO	},
 				SM_ENUM_VALUE_END		},
-});
+}, WITH_DEP_VALUES(&pciexp_clk_pm, 1), WITH_CALLBACK(update_pcie_aspm));
 
 /* PCIe CPU RP ASPM */
 static const struct sm_object pciexp_aspm_cpu = SM_DECLARE_ENUM({
@@ -90,18 +119,7 @@ static const struct sm_object pciexp_aspm_cpu = SM_DECLARE_ENUM({
 				{ "L1",		ASPM_L1		},
 				{ "L0sL1",	ASPM_L0S_L1	},
 				SM_ENUM_VALUE_END		},
-});
-
-/* PCIe Clock PM */
-static const struct sm_object pciexp_clk_pm = SM_DECLARE_BOOL({
-	.opt_name	= "pciexp_clk_pm",
-	.ui_name	= "PCIe Clock Power Management",
-	.ui_helptext	= "Enables or disables power management for the PCIe clock. When"
-			  " enabled, it reduces power consumption during idle states."
-			  " This can help lower overall energy use but may impact"
-			  " performance in power-sensitive tasks.",
-	.default_value	= true,
-});
+}, WITH_DEP_VALUES(&pciexp_clk_pm, 1), WITH_CALLBACK(update_pcie_aspm_cpu));
 
 /* PCIe L1 Substates */
 static const struct sm_object pciexp_l1ss = SM_DECLARE_ENUM({
@@ -117,7 +135,7 @@ static const struct sm_object pciexp_l1ss = SM_DECLARE_ENUM({
 				{ "L1.1",	L1_SS_L1_1	},
 				{ "L1.2",	L1_SS_L1_2	},
 				SM_ENUM_VALUE_END		},
-});
+}, WITH_DEP_VALUES(&pciexp_clk_pm, 1), WITH_CALLBACK(update_pcie_l1ss));
 
 /* PCIe PCH Root Port Speed */
 static const struct sm_object pciexp_speed = SM_DECLARE_ENUM({

From 42927e8273c5d9f39196baa4f5e2bc83a04caa45 Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Thu, 29 Jan 2026 10:43:20 -0600
Subject: [PATCH 3222/3886] device/pci_device: Fix comment for leftover devices

Commit dd817408e127 ("device/pci_device: Fix leftover devices") changed
the conditions for a device to be considered leftover to include not
being disabled, so update the comment to reflect that.

Change-Id: If80a5aae00ba97c1e0580dedb460a605a71bb627
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90998
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
---
 src/device/pci_device.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/device/pci_device.c b/src/device/pci_device.c
index d7f6a3ad34..a0a8df3d4d 100644
--- a/src/device/pci_device.c
+++ b/src/device/pci_device.c
@@ -1438,8 +1438,8 @@ void pci_scan_bus(struct bus *bus, unsigned int min_devfn,
 		}
 
 		/*
-		 * The device is only considered leftover if it is not hidden
-		 * and it has a Vendor ID of 0 (the default for a device that
+		 * The device is only considered leftover if it is enabled, not
+		 * hidden, and has a Vendor ID of 0 (the default for a device that
 		 * could not be probed).
 		 */
 		if (dev->vendor != 0 || dev->hidden || !dev->enabled) {

From 1e1e99d723c365d141201a9c396ba66bbbdcc208 Mon Sep 17 00:00:00 2001
From: Alicja Michalska <alicja.michalska@9elements.com>
Date: Fri, 30 Jan 2026 18:25:07 +0100
Subject: [PATCH 3223/3886] soc/intel/pantherlake: Include FSP API header
 globally
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

As discussed under CB:88768, building for PantherLake targets fails due
to odd race-condition:
```
src/include/stdint.h:66:9: error: "INT32_MAX" redefined [-Werror]
   66 | #define INT32_MAX  ((int32_t)0x7FFFFFFF)
      |         ^~~~~~~~~
[...]
  129 |   #define INT32_MAX                       (0x7FFFFFFF)
      |           ^~~~~~~~~
cc1: all warnings being treated as errors
make: *** Waiting for unfinished jobs....
```

Board maintainers shouldn't need to include the FSP API header in their
ports, adding this header globally to meminit.h resolves the
race-condition and allows the build to finish.

Change-Id: Id7656d476ca6db78ea74629ef37a20323362997a
Signed-off-by: Alicja Michalska <alicja.michalska@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91023
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
---
 src/mainboard/google/fatcat/romstage.c          | 1 -
 src/mainboard/intel/ptlrvp/romstage.c           | 1 -
 src/soc/intel/pantherlake/include/soc/meminit.h | 1 +
 3 files changed, 1 insertion(+), 2 deletions(-)

diff --git a/src/mainboard/google/fatcat/romstage.c b/src/mainboard/google/fatcat/romstage.c
index 4e3c5b764a..9cece34bf6 100644
--- a/src/mainboard/google/fatcat/romstage.c
+++ b/src/mainboard/google/fatcat/romstage.c
@@ -4,7 +4,6 @@
 #include <baseboard/variants.h>
 #include <bootmode.h>
 #include <ec/google/chromeec/ec.h>
-#include <fsp/api.h>
 #include <soc/romstage.h>
 #include <soc/soc_chip.h>
 #include <string.h>
diff --git a/src/mainboard/intel/ptlrvp/romstage.c b/src/mainboard/intel/ptlrvp/romstage.c
index 1172f006cb..e228f3a5bd 100644
--- a/src/mainboard/intel/ptlrvp/romstage.c
+++ b/src/mainboard/intel/ptlrvp/romstage.c
@@ -2,7 +2,6 @@
 
 #include <baseboard/variants.h>
 #include <ec/intel/board_id.h>
-#include <fsp/api.h>
 #include <soc/romstage.h>
 #include <soc/soc_chip.h>
 #include <string.h>
diff --git a/src/soc/intel/pantherlake/include/soc/meminit.h b/src/soc/intel/pantherlake/include/soc/meminit.h
index 63404f8c17..d9506500ef 100644
--- a/src/soc/intel/pantherlake/include/soc/meminit.h
+++ b/src/soc/intel/pantherlake/include/soc/meminit.h
@@ -3,6 +3,7 @@
 #ifndef _SOC_PANTHERLAKE_MEMINIT_H_
 #define _SOC_PANTHERLAKE_MEMINIT_H_
 
+#include <fsp/api.h>
 #include <fsp/soc_binding.h>
 #include <intelblocks/meminit.h>
 #include <types.h>

From 4ae5366ba25ffc59abe4c307579701009ba77487 Mon Sep 17 00:00:00 2001
From: Patrick Rudolph <patrick.rudolph@9elements.com>
Date: Fri, 30 Jan 2026 09:36:07 +0100
Subject: [PATCH 3224/3886] cpu/intel/smm/gen1/smmrelocate: Fix comments
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

The code was copied from newer generation SoC supporting parallel
SMM relocation, but it wasn't properly cleaned.

Gen1 doesn't support parallel SMM relocation, so fix the comments.

Change-Id: Idbe6d2c18f668a9c1922b93ce1b2cc3d126ff2f9
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91013
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/cpu/intel/smm/gen1/smmrelocate.c | 18 +++---------------
 1 file changed, 3 insertions(+), 15 deletions(-)

diff --git a/src/cpu/intel/smm/gen1/smmrelocate.c b/src/cpu/intel/smm/gen1/smmrelocate.c
index 8dffceb4fd..c57a661ef7 100644
--- a/src/cpu/intel/smm/gen1/smmrelocate.c
+++ b/src/cpu/intel/smm/gen1/smmrelocate.c
@@ -145,10 +145,7 @@ void smm_initialize(void)
 	/* Clear the SMM state in the southbridge. */
 	smm_southbridge_clear_state();
 
-	/*
-	 * Run the relocation handler for on the BSP to check and set up
-	 * parallel SMM relocation.
-	 */
+	/* Run the relocation handler on the BSP. */
 	smm_initiate_relocation();
 }
 
@@ -195,20 +192,11 @@ void smm_relocation_handler(int cpu, uintptr_t curr_smbase,
 		write_smrr(relo_params);
 }
 
-/*
- * The default SMM entry can happen in parallel or serially. If the
- * default SMM entry is done in parallel the BSP has already setup
- * the saving state to each CPU's MSRs. At least one save state size
- * is required for the initial SMM entry for the BSP to determine if
- * parallel SMM relocation is even feasible.
- */
 void smm_relocate(void)
 {
 	/*
-	 * If smm_save_state_in_msrs is non-zero then parallel SMM relocation
-	 * shall take place. Run the relocation handler a second time on the
-	 * BSP to do the final move. For APs, a relocation handler always
-	 * needs to be run.
+	 * The BSP had already run SMM relocation in smm_initialize(),
+	 * so skip it for the BSP and only run it on the APs.
 	 */
 	if (!boot_cpu())
 		smm_initiate_relocation();

From a1048f60938f084541693ebe519bd6db1d8b97e7 Mon Sep 17 00:00:00 2001
From: KangMin Wang <kangmin.wang@luxshare.corp-partner.google.com>
Date: Tue, 27 Jan 2026 21:07:12 +0800
Subject: [PATCH 3225/3886] mb/google/bluey:Add support for Mica variant

BUG=b:479018455
TEST=build mica board

Change-Id: I77a8e118cf2d03cdd09c3e5babab307f0be3d8c6
Signed-off-by: KangMin Wang <kangmin.wang@luxshare.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90951
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Derek Huang <derekhuang@google.com>
---
 src/mainboard/google/bluey/Kconfig      | 13 +++++++++++++
 src/mainboard/google/bluey/Kconfig.name |  3 +++
 2 files changed, 16 insertions(+)

diff --git a/src/mainboard/google/bluey/Kconfig b/src/mainboard/google/bluey/Kconfig
index 163650702f..4cbb5e06ba 100644
--- a/src/mainboard/google/bluey/Kconfig
+++ b/src/mainboard/google/bluey/Kconfig
@@ -60,6 +60,19 @@ config BOARD_GOOGLE_QUARTZ
 	select MAINBOARD_NO_USB_A_PORT
 	select MAINBOARD_SUPPORTS_PARALLEL_CHARGING
 
+config BOARD_GOOGLE_MODEL_MICA
+	def_bool n
+	select BOARD_GOOGLE_BASEBOARD_BLUEY
+	select BOARD_ROMSIZE_KB_32768
+	select EC_GOOGLE_CHROMEEC_BATTERY_SOC_DYNAMIC
+	select MAINBOARD_HAS_CHROME_EC
+	select MAINBOARD_HAS_FINGERPRINT_VIA_USB
+	select MAINBOARD_HAS_GOOGLE_TPM
+
+config BOARD_GOOGLE_MICA
+	select BOARD_GOOGLE_MODEL_MICA
+	select SOC_QUALCOMM_HAMOA
+
 if BOARD_GOOGLE_BLUEY_COMMON
 
 config MAINBOARD_DIR
diff --git a/src/mainboard/google/bluey/Kconfig.name b/src/mainboard/google/bluey/Kconfig.name
index 274c1e5042..25009d7be0 100644
--- a/src/mainboard/google/bluey/Kconfig.name
+++ b/src/mainboard/google/bluey/Kconfig.name
@@ -16,3 +16,6 @@ config BOARD_GOOGLE_QUENBIH
 
 config BOARD_GOOGLE_QUARTZ
 	bool "->  Quartz"
+
+config BOARD_GOOGLE_MICA
+	bool "->  Mica"

From e50f7e8b4937e8c92aa25aa967843495f40f640e Mon Sep 17 00:00:00 2001
From: Yu-Ping Wu <yupingso@google.com>
Date: Wed, 28 Jan 2026 12:30:50 +0800
Subject: [PATCH 3226/3886] commonlib/list: Add list_length() and more to API

In a follow-up patch (CB:90962), the list will be changed to a circular
one, and list_node fields 'next' and 'prev' will become private to the
implementation.

To allow smooth transition to circular lists for all call sites, add the
following functions to the list API:

- list_is_empty()
- list_next()
- list_prev()
- list_first()
- list_last()
- list_length()

All list API call sites are expected to use the public API instead of
the raw 'next' and 'prev' pointers.

Change-Id: Ib1040f5caab8550ea52db9b55a074d7d79c591e5
Signed-off-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90961
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jakub "Kuba" Czapiga <czapiga@google.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
---
 src/commonlib/include/commonlib/list.h |  35 ++++++++-
 src/commonlib/list.c                   |  21 +++++
 tests/commonlib/list-test.c            | 101 ++++++++++++++++---------
 3 files changed, 120 insertions(+), 37 deletions(-)

diff --git a/src/commonlib/include/commonlib/list.h b/src/commonlib/include/commonlib/list.h
index 970d68ea49..9bad52f3a3 100644
--- a/src/commonlib/include/commonlib/list.h
+++ b/src/commonlib/include/commonlib/list.h
@@ -5,6 +5,7 @@
 #define __COMMONLIB_LIST_H__
 
 #include <commonlib/helpers.h>
+#include <stdbool.h>
 #include <stdint.h>
 
 struct list_node {
@@ -18,9 +19,41 @@ void list_remove(struct list_node *node);
 void list_insert_after(struct list_node *node, struct list_node *after);
 // Insert list_node node before list_node before in a doubly linked list.
 void list_insert_before(struct list_node *node, struct list_node *before);
-// Appends the node to the end of the list.
+// Append the node to the end of the list.
 void list_append(struct list_node *node, struct list_node *head);
 
+// Return if the list is empty.
+static inline bool list_is_empty(const struct list_node *head)
+{
+	return !head->next;
+}
+
+// Get next node.
+static inline const struct list_node *list_next(const struct list_node *node,
+						const struct list_node *head)
+{
+	return node->next;
+};
+
+// Get prev node.
+static inline const struct list_node *list_prev(const struct list_node *node,
+						const struct list_node *head)
+{
+	return node->prev == head ? NULL : node->prev;
+};
+
+// Get first node.
+static inline const struct list_node *list_first(const struct list_node *head)
+{
+	return list_is_empty(head) ? NULL : head->next;
+}
+
+// Get last node.
+const struct list_node *list_last(const struct list_node *head);
+
+// Get the number of list elements.
+size_t list_length(const struct list_node *head);
+
 #define list_for_each(ptr, head, member)                                      \
 	for ((ptr) = container_of((head).next, typeof(*(ptr)), member);       \
 		(uintptr_t)ptr + (uintptr_t)offsetof(typeof(*(ptr)), member); \
diff --git a/src/commonlib/list.c b/src/commonlib/list.c
index b1030c8263..9d11d9606c 100644
--- a/src/commonlib/list.c
+++ b/src/commonlib/list.c
@@ -36,3 +36,24 @@ void list_append(struct list_node *node, struct list_node *head)
 
 	list_insert_after(node, head);
 }
+
+const struct list_node *list_last(const struct list_node *head)
+{
+	const struct list_node *ptr = head;
+	while (ptr->next)
+		ptr = ptr->next;
+	return ptr == head ? NULL : ptr;
+}
+
+size_t list_length(const struct list_node *head)
+{
+	struct {
+		struct list_node node;
+	} const *ptr;
+	size_t len = 0;
+
+	list_for_each(ptr, *head, node)
+		len++;
+
+	return len;
+}
diff --git a/tests/commonlib/list-test.c b/tests/commonlib/list-test.c
index 4ca48a468f..568fa1d3dd 100644
--- a/tests/commonlib/list-test.c
+++ b/tests/commonlib/list-test.c
@@ -1,9 +1,10 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
-#include <tests/test.h>
+#include <commonlib/list.h>
 #include <stdlib.h>
 #include <string.h>
-#include <commonlib/list.h>
+#include <tests/test.h>
+#include <types.h>
 
 struct test_container {
 	int value;
@@ -11,10 +12,40 @@ struct test_container {
 	struct list_node list_node;
 };
 
-void test_list_insert_after(void **state)
+static void test_list_empty(void **state)
+{
+	struct list_node head = {};
+	struct test_container *node;
+
+	list_for_each(node, head, list_node) {
+		assert_true(false);
+	}
+
+	assert_true(list_is_empty(&head));
+	assert_null(list_first(&head));
+	assert_null(list_last(&head));
+	assert_int_equal(0, list_length(&head));
+}
+
+static void test_list_one_node(void **state)
+{
+	struct list_node head = {};
+	struct test_container c = { .value = 1 };
+
+	list_insert_after(&c.list_node, &head);
+
+	assert_false(list_is_empty(&head));
+	assert_null(list_next(&c.list_node, &head));
+	assert_null(list_prev(&c.list_node, &head));
+	assert_ptr_equal(&c.list_node, list_first(&head));
+	assert_ptr_equal(&c.list_node, list_last(&head));
+	assert_int_equal(1, list_length(&head));
+}
+
+static void test_list_insert_after(void **state)
 {
 	int i = 0;
-	struct list_node root = { .prev = NULL, .next = NULL };
+	struct list_node head = { .prev = NULL, .next = NULL };
 	struct test_container *c1 = (struct test_container *)malloc(sizeof(*c1));
 	struct test_container *c2 = (struct test_container *)malloc(sizeof(*c2));
 	struct test_container *c3 = (struct test_container *)malloc(sizeof(*c2));
@@ -29,26 +60,33 @@ void test_list_insert_after(void **state)
 	c2->value = values[1];
 	c3->value = values[2];
 
-	list_insert_after(&c1->list_node, &root);
+	list_insert_after(&c1->list_node, &head);
 	list_insert_after(&c2->list_node, &c1->list_node);
 	list_insert_after(&c3->list_node, &c2->list_node);
 
-	list_for_each(ptr, root, list_node) {
+	list_for_each(ptr, head, list_node) {
 		assert_int_equal(values[i], ptr->value);
 		i++;
 	}
 
 	assert_int_equal(3, i);
+	assert_int_equal(3, list_length(&head));
+	assert_false(list_is_empty(&head));
+
+	assert_ptr_equal(&c3->list_node, list_next(&c2->list_node, &head));
+	assert_ptr_equal(&c1->list_node, list_prev(&c2->list_node, &head));
+	assert_ptr_equal(&c1->list_node, list_first(&head));
+	assert_ptr_equal(&c3->list_node, list_last(&head));
 
 	free(c3);
 	free(c2);
 	free(c1);
 }
 
-void test_list_insert_before(void **state)
+static void test_list_insert_before(void **state)
 {
 	int i = 0;
-	struct list_node root = { .prev = NULL, .next = NULL };
+	struct list_node head = { .prev = NULL, .next = NULL };
 	struct test_container *c1 = (struct test_container *)malloc(sizeof(*c1));
 	struct test_container *c2 = (struct test_container *)malloc(sizeof(*c2));
 	struct test_container *c3 = (struct test_container *)malloc(sizeof(*c2));
@@ -63,87 +101,78 @@ void test_list_insert_before(void **state)
 	c2->value = values[1];
 	c3->value = values[2];
 
-	list_insert_after(&c3->list_node, &root);
+	list_insert_after(&c3->list_node, &head);
 	list_insert_before(&c2->list_node, &c3->list_node);
 	list_insert_before(&c1->list_node, &c2->list_node);
 
 
-	list_for_each(ptr, root, list_node) {
+	list_for_each(ptr, head, list_node) {
 		assert_int_equal(values[i], ptr->value);
 		i++;
 	}
 
 	assert_int_equal(3, i);
+	assert_int_equal(3, list_length(&head));
+	assert_false(list_is_empty(&head));
 
 	free(c3);
 	free(c2);
 	free(c1);
 }
 
-void test_list_remove(void **state)
+static void test_list_remove(void **state)
 {
-	struct list_node root = { .prev = NULL, .next = NULL };
+	struct list_node head = { .prev = NULL, .next = NULL };
 	struct test_container *c1 = (struct test_container *)malloc(sizeof(*c1));
 	struct test_container *c2 = (struct test_container *)malloc(sizeof(*c2));
-	struct test_container *ptr;
-	int len;
 
-	list_insert_after(&c1->list_node, &root);
+	list_insert_after(&c1->list_node, &head);
 	list_insert_after(&c2->list_node, &c1->list_node);
 
-	len = 0;
-	list_for_each(ptr, root, list_node) {
-		len++;
-	}
-	assert_int_equal(2, len);
+	assert_int_equal(2, list_length(&head));
 
 	list_remove(&c1->list_node);
-
-	len = 0;
-	list_for_each(ptr, root, list_node) {
-		len++;
-	}
-	assert_int_equal(1, len);
+	assert_int_equal(1, list_length(&head));
 
 	list_remove(&c2->list_node);
-	len = 0;
-	list_for_each(ptr, root, list_node) {
-		len++;
-	}
-	assert_int_equal(0, len);
+	assert_int_equal(0, list_length(&head));
 
 	free(c2);
 	free(c1);
 }
 
-void test_list_append(void **state)
+static void test_list_append(void **state)
 {
 	size_t idx;
 	struct test_container *node;
-	struct list_node root = {};
+	struct list_node head = {};
 	struct test_container nodes[] = {
 		{1}, {2}, {3}
 	};
 
 	for (idx = 0; idx < ARRAY_SIZE(nodes); ++idx)
-		list_append(&nodes[idx].list_node, &root);
+		list_append(&nodes[idx].list_node, &head);
 
 	idx = 0;
-	list_for_each(node, root, list_node) {
+	list_for_each(node, head, list_node) {
 		assert_ptr_equal(node, &nodes[idx]);
 		idx++;
 	}
+
+	assert_int_equal(3, idx);
+	assert_int_equal(3, list_length(&head));
 }
 
 int main(void)
 {
 	const struct CMUnitTest tests[] = {
+		cmocka_unit_test(test_list_empty),
+		cmocka_unit_test(test_list_one_node),
 		cmocka_unit_test(test_list_insert_after),
 		cmocka_unit_test(test_list_insert_before),
 		cmocka_unit_test(test_list_remove),
 		cmocka_unit_test(test_list_append),
 	};
 
-
 	return cb_run_group_tests(tests, NULL, NULL);
 }

From b9aecb89bb040b0db306cc882e33f39afb2f1a91 Mon Sep 17 00:00:00 2001
From: Yu-Ping Wu <yupingso@google.com>
Date: Fri, 30 Jan 2026 17:30:05 +0800
Subject: [PATCH 3227/3886] lib/fit: Switch to commonlib/list public API

CB:90961 introduces list_is_empty() function. Use it to improve
readability.

Change-Id: Icffbce9e77b19c3885e0a0466f8d109ec84d70c4
Signed-off-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91006
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jakub "Kuba" Czapiga <czapiga@google.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
---
 src/lib/fit.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/lib/fit.c b/src/lib/fit.c
index 3bfca57aab..1942cb3040 100644
--- a/src/lib/fit.c
+++ b/src/lib/fit.c
@@ -396,7 +396,7 @@ static int fit_update_compat(struct fit_config_node *config)
 		}
 
 		/* FDT overlays are not supported in legacy FIT images. */
-		if (config->overlays.next) {
+		if (!list_is_empty(&config->overlays)) {
 			printk(BIOS_ERR, "config %s has overlay but no compat!\n",
 			       config->name);
 			return -1;

From 4499c6d65c6cf246d2cddfc86977fdb1d7dbb2bb Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Thu, 29 Jan 2026 16:31:46 -0600
Subject: [PATCH 3228/3886] util/inteltool: Unify LPC/eSPI handling for ADL/RPL

Handle ADL-P and ADL-M PCI IDs the same as ADL-N and RPL-P for
dumping LPC registers. Add southbridge names/labels for ADL-P
and ADL-M.

TEST=build and run 'inteltool -l' to dump LPC/eSPI registers on
google/taeko (RPL-P), verify output matches LPC decode set in devicetree

Change-Id: I84901a8e25eb679acb31be1caa8fffa667454c62
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91026
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 util/inteltool/inteltool.c | 6 ++++--
 util/inteltool/lpc.c       | 3 +++
 2 files changed, 7 insertions(+), 2 deletions(-)

diff --git a/util/inteltool/inteltool.c b/util/inteltool/inteltool.c
index bc40e57daa..66d42a903d 100644
--- a/util/inteltool/inteltool.c
+++ b/util/inteltool/inteltool.c
@@ -483,8 +483,10 @@ static const struct {
 	{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_C266, "C266" },
 	{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EHL, "Elkhart Lake" },
 	{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_JSL, "Jasper Lake" },
-	{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ADL_N, "Alder Lake-N"},
-	{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_RPL_P, "Raptor Lake" },
+	{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ADL_M, "Alder Lake-M" },
+	{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ADL_N, "Alder Lake-N" },
+	{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ADL_P, "Alder Lake-P" },
+	{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_RPL_P, "Raptor Lake-P" },
 	{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_MTL_P, "Meteor Lake-P"},
 	{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ARL_H, "Arrow Lake-H"},
 
diff --git a/util/inteltool/lpc.c b/util/inteltool/lpc.c
index 711e64b1a2..0d21bedc80 100644
--- a/util/inteltool/lpc.c
+++ b/util/inteltool/lpc.c
@@ -168,7 +168,10 @@ int print_lpc(struct pci_dev *sb, struct pci_access *pacc)
 			cfg_registers_size = ARRAY_SIZE(sunrise_lpc_cfg_registers);
 		}
 		break;
+	case PCI_DEVICE_ID_INTEL_ADL_M:
 	case PCI_DEVICE_ID_INTEL_ADL_N:
+	case PCI_DEVICE_ID_INTEL_ADL_P:
+	case PCI_DEVICE_ID_INTEL_RPL_P:
 		dev = pci_get_dev(pacc, sb->domain, sb->bus, sb->dev, 0);
 		if (!dev) {
 			printf("LPC/eSPI interface not found.\n");

From be31c8a212cb72d5689e3d8ffc7894791db0b174 Mon Sep 17 00:00:00 2001
From: Patrick Rudolph <patrick.rudolph@9elements.com>
Date: Sun, 1 Feb 2026 10:00:03 +0100
Subject: [PATCH 3229/3886] nb/intel/sandybridge: Advertise all MCH BARs

Currently not all fixed	MMIO ranges are	advertised to the resource
allocator. This	is not an issue	as long	bottom-up allocation is
used and as long as only small PCI BARs are present on the system.

Tell the PCI resource allocator about active MCH BARs to not overlap
PCI BARs with MCH BARs.

TEST=Can still boot on Lenovo X220. No issues seen in coreboot or Linux.

Change-Id: I9148ce492b3b16542bae2737c98b0e6fd0701745
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91039
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
---
 src/northbridge/intel/sandybridge/northbridge.c | 14 ++++++++++++++
 1 file changed, 14 insertions(+)

diff --git a/src/northbridge/intel/sandybridge/northbridge.c b/src/northbridge/intel/sandybridge/northbridge.c
index 998562cbed..0d691d9343 100644
--- a/src/northbridge/intel/sandybridge/northbridge.c
+++ b/src/northbridge/intel/sandybridge/northbridge.c
@@ -201,6 +201,20 @@ static void mc_read_resources(struct device *dev)
 		printk(BIOS_DEBUG, "DPR base 0x%08x size %uM\n", dpr_base_k * KiB, dpr.size);
 	}
 
+	/* Non standard BARs */
+	u64 bar = pci_read_config32(dev, MCHBAR);
+	bar |= ((u64)pci_read_config32(dev, MCHBAR + 4) << 32);
+	if (bar & 1)
+		mmio_range(dev, index++, bar & ~0xf, 0x8000);
+	bar = pci_read_config32(dev, DMIBAR);
+	bar |= ((u64)pci_read_config32(dev, DMIBAR + 4) << 32);
+	if (bar & 1)
+		mmio_range(dev, index++, bar & ~0xf, 0x1000);
+	bar = pci_read_config32(dev, EPBAR);
+	bar |= ((u64)pci_read_config32(dev, EPBAR + 4) << 32);
+	if (bar & 1)
+		mmio_range(dev, index++, bar & ~0xf, 0x1000);
+
 	printk(BIOS_INFO, "Available memory below 4GB: %lluM\n", tomk >> 10);
 
 	/* Report the memory regions */

From 1b7aa42421bacc45b153950f8955edf6846e6b9b Mon Sep 17 00:00:00 2001
From: Patrick Rudolph <patrick.rudolph@9elements.com>
Date: Sat, 31 Jan 2026 08:20:20 +0100
Subject: [PATCH 3230/3886] libgfxinit: Bump submodule

Bump the submodule and thus include the following new commits:

hw-gfx-gma-i2c: Reduce EDID I2C timeout
transcoder: Don't try to disable disabled DDI func
gfxtest: Handle 64-bit aperture base and register location
gma: Get DPCD 1.1+ displays out of D3
gma: Work around GNATprove issue with nested loops

TEST=libgfxinit still works on Lenovo X220 and is 450msec faster.

Change-Id: If32fd0256280ee8539c6bbc0440c30d89711996c
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91030
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 3rdparty/libgfxinit | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/3rdparty/libgfxinit b/3rdparty/libgfxinit
index 17cfc92f40..3c3828add5 160000
--- a/3rdparty/libgfxinit
+++ b/3rdparty/libgfxinit
@@ -1 +1 @@
-Subproject commit 17cfc92f402493979783585b6581efbd98c0cf07
+Subproject commit 3c3828add50024e90e57d6fbe0e660d1b66302d9

From 1f20a947c5c7bce0b6a741543daaaae1b18b1b65 Mon Sep 17 00:00:00 2001
From: Angel Pons <th3fanbus@gmail.com>
Date: Fri, 30 Jan 2026 22:33:00 +0100
Subject: [PATCH 3231/3886] util/autoport: Fix newly-added Kconfig select

Commit 4a09db75d9271011236c34c90d55d7bfb4fc8e5b ("util/autoport: Add
support for 9 Series PCHs (Lynx Point Refresh)") got submitted after
commit 01d82febb2f7d784d3ac918740045772e94e777e ("util/autoport:
Separate handling of Kconfig selects").

The latter commit was specifically made so that the former commit could
properly express a Kconfig select with a condition. However, the former
commit did not get updated, and got submitted as-is since there was no
unresolved review comment to keep track of this TODO. As a result, what
should have been a conditional Kconfig select but with the condition in
a comment to work around limitations of the original system accidentally
became a bool option override.

So, simply use the new system to express a conditional Kconfig select.
This fixes the wrongly-generated Kconfig as well as the original issue.

Even though this would still have worked, the `USE_BROADWELL_MRC` option
must be selected for boards with a Lynx Point Refresh PCH, since Haswell
MRC will not work on those PCHs. Still, this can be caught and corrected
during review, in case any board ports are made before this fix lands.

Change-Id: I98f032283e9e5bb5ec13dbff382304b7abfec07e
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91027
Reviewed-by: Nicholas <nic.c3.14@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
---
 util/autoport/lynxpoint.go | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/util/autoport/lynxpoint.go b/util/autoport/lynxpoint.go
index 0ac428e7fa..ffb955d229 100644
--- a/util/autoport/lynxpoint.go
+++ b/util/autoport/lynxpoint.go
@@ -163,8 +163,7 @@ func (b lynxpoint) Scan(ctx Context, addr PCIDevData) {
 	}
 
 	if (b.variant == LYNX_POINT_REFRESH) {
-		KconfigBool["USE_BROADWELL_MRC"] = true
-		KconfigComment["USE_BROADWELL_MRC"] = "if !USE_NATIVE_RAMINIT # FIXME: Uncomment the if"
+		KconfigSelect["USE_BROADWELL_MRC"] = "!USE_NATIVE_RAMINIT"
 	}
 
 	FADT := ctx.InfoSource.GetACPI()["FACP"]

From 6b7084a053d8bc6d943375ef9ff9888884381b05 Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Mon, 2 Feb 2026 20:21:09 +0000
Subject: [PATCH 3232/3886] mainboard/starlabs: rework power profile limits

Recompute PL1/PL2 from the per-SKU TDP values instead of deriving PL1
from PL2.

- Performance: PL1 = TDP, PL2 = round_up(TDP * 2, 5)
- Balanced/Power saver: scale TDP first, then derive PL2
- Performance TCC offset: 10C with fan, 20C without
- Lower profiles: add +10C offset per step down

PL4 continues to be sourced from CONFIG_PL4_WATTS.

Change-Id: Idc5d008c8db0391fcc600e7485010e15c8fc01d8
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91055
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 .../starlabs/common/include/common/powercap.h |  2 --
 .../starlabs/common/powercap/powercap.c       | 32 +++++++++++--------
 2 files changed, 18 insertions(+), 16 deletions(-)

diff --git a/src/mainboard/starlabs/common/include/common/powercap.h b/src/mainboard/starlabs/common/include/common/powercap.h
index a9ea99916c..2447ce9851 100644
--- a/src/mainboard/starlabs/common/include/common/powercap.h
+++ b/src/mainboard/starlabs/common/include/common/powercap.h
@@ -5,8 +5,6 @@
 
 #include <soc/soc_chip.h>
 
-#define TCC(temp)	(CONFIG_TJ_MAX - temp)
-
 enum cmos_power_profile {
 	PP_POWER_SAVER	= 0,
 	PP_BALANCED	= 1,
diff --git a/src/mainboard/starlabs/common/powercap/powercap.c b/src/mainboard/starlabs/common/powercap/powercap.c
index a1eeb019cf..2bc7705136 100644
--- a/src/mainboard/starlabs/common/powercap/powercap.c
+++ b/src/mainboard/starlabs/common/powercap/powercap.c
@@ -1,5 +1,6 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
+#include <commonlib/helpers.h>
 #include <option.h>
 #include <types.h>
 #include <common/powercap.h>
@@ -10,47 +11,50 @@ static enum cmos_power_profile get_power_profile(enum cmos_power_profile fallbac
 	return power_profile < NUM_POWER_PROFILES ? power_profile : fallback;
 }
 
+static uint16_t round_up_to_5(uint16_t value)
+{
+	return DIV_ROUND_UP(value, 5) * 5;
+}
 
 void update_power_limits(config_t *cfg)
 {
 	uint8_t performance_scale = 100;
+	uint32_t performance_tcc_offset = CONFIG(EC_STARLABS_FAN) ? 10 : 20;
 
 	/* Scale PL1 & PL2 based on CMOS settings */
 	switch (get_power_profile(PP_POWER_SAVER)) {
 	case PP_POWER_SAVER:
 		performance_scale -= 50;
-		cfg->tcc_offset = TCC(80);
+		cfg->tcc_offset = performance_tcc_offset + 20;
 		break;
 	case PP_BALANCED:
 		performance_scale -= 25;
-		cfg->tcc_offset = TCC(90);
+		cfg->tcc_offset = performance_tcc_offset + 10;
 		break;
 	case PP_PERFORMANCE:
-		/* Use the Intel defaults */
-		cfg->tcc_offset = TCC(100);
+		cfg->tcc_offset = performance_tcc_offset;
 		break;
 	}
 
 	struct soc_power_limits_config *limits =
 		(struct soc_power_limits_config *)&cfg->power_limits_config;
-	size_t limit_count = sizeof(cfg->power_limits_config) /
-			     sizeof(struct soc_power_limits_config);
+	size_t limit_count =
+		sizeof(cfg->power_limits_config) / sizeof(struct soc_power_limits_config);
 
 	for (size_t i = 0; i < limit_count; i++) {
 		struct soc_power_limits_config *entry = &limits[i];
+		uint16_t tdp, pl1, pl2;
 
 		entry->tdp_pl4 = (uint16_t)CONFIG_PL4_WATTS;
 
-		if (!entry->tdp_pl2_override)
+		tdp = entry->tdp_pl1_override;
+		if (!tdp)
 			continue;
 
-		/* Set PL1 to 50% of PL2 */
-		entry->tdp_pl1_override = (entry->tdp_pl2_override / 2) & ~1;
+		pl1 = (tdp * performance_scale) / 100;
+		pl2 = round_up_to_5(pl1 * 2);
 
-		if (performance_scale == 100)
-			continue;
-
-		entry->tdp_pl1_override = ((entry->tdp_pl1_override * performance_scale) / 100);
-		entry->tdp_pl2_override = ((entry->tdp_pl2_override * performance_scale) / 100);
+		entry->tdp_pl1_override = pl1;
+		entry->tdp_pl2_override = pl2;
 	}
 }

From bf044a940235bc507c51c47ee32c3107eff33798 Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Mon, 2 Feb 2026 20:30:59 +0000
Subject: [PATCH 3233/3886] soc/intel/meteorlake: add ARL-H 45W power entry

configure_tdp() selects the power limit table based on the
SA PCI device ID and the CPU's nominal TDP.

Add a 45W entry for PCI_DID_INTEL_ARL_H_ID_1 (e.g. Intel
285H) so power limits are programmed instead of being
skipped.

Change-Id: Ia90633b43b78bc616ff0b750ed3ef44333019957
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91056
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/soc/intel/meteorlake/chip.h | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/src/soc/intel/meteorlake/chip.h b/src/soc/intel/meteorlake/chip.h
index 7c4c954d26..c32bb74ade 100644
--- a/src/soc/intel/meteorlake/chip.h
+++ b/src/soc/intel/meteorlake/chip.h
@@ -52,7 +52,8 @@ enum soc_intel_meteorlake_power_limits {
 /* TDP values for different SKUs */
 enum soc_intel_meteorlake_cpu_tdps {
 	TDP_15W = 15,
-	TDP_28W = 28
+	TDP_28W = 28,
+	TDP_45W = 45,
 };
 
 /* Mapping of different SKUs based on CPU ID and TDP values */
@@ -66,6 +67,7 @@ static const struct {
 	{ PCI_DID_INTEL_MTL_P_ID_3, MTL_P_682_482_CORE, TDP_28W },
 	{ PCI_DID_INTEL_MTL_P_ID_1, MTL_P_682_482_CORE, TDP_28W },
 	{ PCI_DID_INTEL_ARL_H_ID_1, MTL_P_682_482_CORE, TDP_28W },
+	{ PCI_DID_INTEL_ARL_H_ID_1, MTL_P_682_482_CORE, TDP_45W },
 	{ PCI_DID_INTEL_ARL_H_ID_2, MTL_P_682_482_CORE, TDP_28W },
 };
 

From e2ef764430e1f74b45415ca62749ee070b0aceeb Mon Sep 17 00:00:00 2001
From: Kapil Porwal <kapilporwal@google.com>
Date: Tue, 3 Feb 2026 14:32:56 +0530
Subject: [PATCH 3234/3886] Revert "mb/google/bluey: Add support to invoke
 LPASS Init"

This reverts commit dec1dfe1601d26a6abc6bde0904c7fbb7ed719df.

Reason for revert: It is causing ADSP load failure in the OS.

BUG=b:480195888
TEST=Able to load the ADSP on Google/Quenbi.

Change-Id: I029c2b7ba74764a15227e44edc3be755cb8b9363
Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91072
Reviewed-by: Pranava Y N <pranavayn@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jayvik Desai <jayvik@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
---
 src/mainboard/google/bluey/mainboard.c | 2 --
 1 file changed, 2 deletions(-)

diff --git a/src/mainboard/google/bluey/mainboard.c b/src/mainboard/google/bluey/mainboard.c
index 3bdf4f4425..9fff83bba7 100644
--- a/src/mainboard/google/bluey/mainboard.c
+++ b/src/mainboard/google/bluey/mainboard.c
@@ -234,8 +234,6 @@ static void mainboard_init(struct device *dev)
 
 	/* Setup USB related initial config */
 	setup_usb();
-
-	lpass_init();
 }
 
 static void mainboard_enable(struct device *dev)

From 0fd6a83a1164a27361650bb73c0cc3fab6ec49cc Mon Sep 17 00:00:00 2001
From: Qinghong Zeng <zengqinghong@huaqin.corp-partner.google.com>
Date: Fri, 30 Jan 2026 16:40:57 +0800
Subject: [PATCH 3235/3886] mb/google/nissa/var/rull: Support x32 memory
 configuration

Use GPP_E19 level to determine whether x32 memory configuration is
supported.

BUG=b:480003949
TEST=emerge-nissa coreboot chromeos-bootimage

Change-Id: I68d9060686f6b48c2fd7a296cd78346233265e24
Signed-off-by: Qinghong Zeng <zengqinghong@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91003
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
---
 src/mainboard/google/brya/Kconfig             |  1 +
 .../google/brya/variants/rull/Makefile.mk     |  1 +
 .../google/brya/variants/rull/gpio.c          |  5 +++++
 .../google/brya/variants/rull/memory.c        | 19 +++++++++++++++++++
 4 files changed, 26 insertions(+)
 create mode 100644 src/mainboard/google/brya/variants/rull/memory.c

diff --git a/src/mainboard/google/brya/Kconfig b/src/mainboard/google/brya/Kconfig
index e1d64876c5..39d88156bb 100644
--- a/src/mainboard/google/brya/Kconfig
+++ b/src/mainboard/google/brya/Kconfig
@@ -605,6 +605,7 @@ config BOARD_GOOGLE_RULL
 	select CHROMEOS_WIFI_SAR if CHROMEOS
 	select DRIVERS_GENERIC_BAYHUB_LV2
 	select DRIVERS_GENERIC_GPIO_KEYS
+	select ENFORCE_MEM_CHANNEL_DISABLE
 	select MAINBOARD_HAS_GOOGLE_STRAUSS_KEYBOARD
 	select SOC_INTEL_TWINLAKE
 
diff --git a/src/mainboard/google/brya/variants/rull/Makefile.mk b/src/mainboard/google/brya/variants/rull/Makefile.mk
index f41cdfdb8a..efe5002383 100644
--- a/src/mainboard/google/brya/variants/rull/Makefile.mk
+++ b/src/mainboard/google/brya/variants/rull/Makefile.mk
@@ -1,6 +1,7 @@
 # SPDX-License-Identifier: GPL-2.0-only
 bootblock-y += gpio.c
 
+romstage-y += memory.c
 romstage-y += gpio.c
 
 ramstage-y += gpio.c
diff --git a/src/mainboard/google/brya/variants/rull/gpio.c b/src/mainboard/google/brya/variants/rull/gpio.c
index 24096d73bc..0c5c2d0552 100644
--- a/src/mainboard/google/brya/variants/rull/gpio.c
+++ b/src/mainboard/google/brya/variants/rull/gpio.c
@@ -90,6 +90,9 @@ static const struct pad_config override_gpio_table[] = {
 	/* R7 : DMIC_DATA_1A ==> DMIC_WCAM_DATA */
 	PAD_CFG_NF(GPP_R7, NONE, DEEP, NF3),
 
+	/* E19 : DDP1_CTRLDATA ==> GPP_E19_STRAP */
+	PAD_CFG_GPI_LOCK(GPP_E19, DN_20K, LOCK_CONFIG),
+
 	/* Configure the virtual CNVi Bluetooth I2S GPIO pads */
 	/* BT_I2S_BCLK */
 	PAD_CFG_NF(GPP_VGPIO_30, NONE, DEEP, NF3),
@@ -138,6 +141,8 @@ static const struct pad_config early_gpio_table[] = {
 	PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2),
     /* H20 : IMGCLKOUT1 ==> WLAN_PERST_L */
 	PAD_CFG_GPO(GPP_H20, 0, DEEP),
+	/* E19 : DDP1_CTRLDATA ==> GPP_E19_STRAP */
+	PAD_CFG_GPI(GPP_E19, DN_20K, DEEP),
 };
 
 static const struct pad_config romstage_gpio_table[] = {
diff --git a/src/mainboard/google/brya/variants/rull/memory.c b/src/mainboard/google/brya/variants/rull/memory.c
new file mode 100644
index 0000000000..0608ae7e0d
--- /dev/null
+++ b/src/mainboard/google/brya/variants/rull/memory.c
@@ -0,0 +1,19 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <baseboard/gpio.h>
+#include <baseboard/variants.h>
+#include <gpio.h>
+#include <soc/romstage.h>
+
+uint8_t mb_get_channel_disable_mask(void)
+{
+	/*
+	 * GPP_E19 High -> One RAM Chip
+	 * GPP_E19 Low  -> Two RAM Chip
+	 * Disable all other channels except first two on each controller
+	 */
+	if (gpio_get(GPP_E19))
+		return (BIT(2) | BIT(3));
+
+	return 0;
+}

From 28608c503a0405a0e659d26e826f1bddb40c7a0d Mon Sep 17 00:00:00 2001
From: Pranava Y N <pranavayn@google.com>
Date: Tue, 3 Feb 2026 18:28:10 +0530
Subject: [PATCH 3236/3886] Revert "soc/intel/pantherlake: Enable all RootPorts
 on PTL-H484"
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

This reverts commit 261274992d03a41c75819c1e7b24bdbb5e4eba7a.

Reason for revert: Panther Lake U/H Processor EDS vol 1/2 says PTL-U/H
12Xe has 12 PCIe RPs where else PTL-H 4Xe has 10 PCIe RPs.

This change has limit the capability for devices that is build with
PTL-U/H 12Xe hence, we are seeing below errors

```
[ERROR]  pcie_rp_update_devicetree: Error: Group exceeds
CONFIG_MAX_ROOT_PORTS.
```

As a result PCIe Gen 5 devices (SSD) unable to init and enabled during
boot.

Change-Id: I0443554ef8f619c485f16edc576794f9cf2e85ea
Signed-off-by: Pranava Y N <pranavayn@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91075
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/soc/intel/pantherlake/Kconfig | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/soc/intel/pantherlake/Kconfig b/src/soc/intel/pantherlake/Kconfig
index 45a8c8376e..59369a6a46 100644
--- a/src/soc/intel/pantherlake/Kconfig
+++ b/src/soc/intel/pantherlake/Kconfig
@@ -253,8 +253,8 @@ config MAX_TBT_ROOT_PORTS
 config MAX_ROOT_PORTS
 	int
 	default 6 if SOC_INTEL_WILDCATLAKE
-	default 12 if SOC_INTEL_PANTHERLAKE_H
-	default 10
+	default 10 if SOC_INTEL_PANTHERLAKE_H
+	default 12
 
 config MAX_PCIE_CLOCK_SRC
 	int

From 3d4c77c7f434d430370fc3867e406880f0e1dff1 Mon Sep 17 00:00:00 2001
From: Pranava Y N <pranavayn@google.com>
Date: Tue, 3 Feb 2026 18:45:54 +0530
Subject: [PATCH 3237/3886] soc/intel/pantherlake: Set CONFIG_MAX_ROOT_PORTS to
 12
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Increase the maximum root port count for Panther Lake (PTL) to 12.
While the actual number of active ports may vary depending on the
specific SKU and strapping, setting this constant to 12 is safe
and systematically handled by the existing SoC logic.

Systematic Bounds: The common PCIe root port driver (pcie_rp.c)
and PTL-specific FSP parameter logic utilize ptl_rp_groups and
PCI configuration space accesses to determine the actual hardware
limits at runtime.

Safe Ceiling: CONFIG_MAX_ROOT_PORTS serves as a compile-time upper
bound for array allocations and iteration loops. Setting this to
12 accommodates the maximum possible PTL configuration without
over-allocating resources.

Consistency: This aligns the configuration with the hardware's
maximum capability, allowing the silicon initialization code to
dynamically "fill in" the details for lower-port SKUs without
requiring further Kconfig changes.

BUG=None
TEST=Able to build boards that use different PTL SKUs.

Change-Id: Icb8f2c075aa56531e311d1ce718953fe3366a5e2
Signed-off-by: Pranava Y N <pranavayn@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91078
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/soc/intel/pantherlake/Kconfig | 1 -
 1 file changed, 1 deletion(-)

diff --git a/src/soc/intel/pantherlake/Kconfig b/src/soc/intel/pantherlake/Kconfig
index 59369a6a46..92397037af 100644
--- a/src/soc/intel/pantherlake/Kconfig
+++ b/src/soc/intel/pantherlake/Kconfig
@@ -253,7 +253,6 @@ config MAX_TBT_ROOT_PORTS
 config MAX_ROOT_PORTS
 	int
 	default 6 if SOC_INTEL_WILDCATLAKE
-	default 10 if SOC_INTEL_PANTHERLAKE_H
 	default 12
 
 config MAX_PCIE_CLOCK_SRC

From ab9d9ecd7e3016ec44f28a9a5b1e076415562026 Mon Sep 17 00:00:00 2001
From: Luca Lai <luca.lai@lcfc.corp-partner.google.com>
Date: Mon, 2 Feb 2026 14:13:14 +0800
Subject: [PATCH 3238/3886] mb/google/fatcat/var/ruby: Enable
 FSP_UGOP_EARLY_SIGN_OF_LIFE

BUG=b:452180266
BRANCH=none
TEST=Build and check system can boot to OS

Change-Id: I6092f620f4ae0635ffbbd9c26cf0ce0d55b44ba8
Signed-off-by: Luca Lai <luca.lai@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91048
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: YH Lin <yueherngl@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Pranava Y N <pranavayn@google.com>
---
 src/mainboard/google/fatcat/Kconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/src/mainboard/google/fatcat/Kconfig b/src/mainboard/google/fatcat/Kconfig
index b38a4e90b9..15b149b226 100644
--- a/src/mainboard/google/fatcat/Kconfig
+++ b/src/mainboard/google/fatcat/Kconfig
@@ -157,6 +157,7 @@ config BOARD_GOOGLE_MODEL_RUBY
 	select BOARD_GOOGLE_BASEBOARD_FATCAT
 	select DRIVERS_I2C_TAS2563
 	select EC_GOOGLE_CHROMEEC_FW_CONFIG_FROM_UFSC
+	select FSP_UGOP_EARLY_SIGN_OF_LIFE
 	select HAVE_SLP_S0_GATE
 	select MAINBOARD_HAS_GOOGLE_STRAUSS_KEYBOARD
 

From ca770df1e732307990ecf1f52028174d6c743c23 Mon Sep 17 00:00:00 2001
From: Luca Lai <luca.lai@lcfc.corp-partner.google.com>
Date: Mon, 2 Feb 2026 14:44:38 +0800
Subject: [PATCH 3239/3886] mb/google/fatcat/var/ruby: Correct GPP_V17
 configuration

Correct the GPP_V17 gpio pin from platform reset to deep to
avoid uncontrollable behavior in s0ix mode.

BUG=b:475990377
BRANCH=none
TEST=Build and boot to OS, check GPP_V17 behavior is correct.

Change-Id: I8f8bc59b71b8f8b4c5d4dbdbdcf8fcbfdbd96921
Signed-off-by: Luca Lai <luca.lai@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91050
Reviewed-by: YH Lin <yueherngl@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Pranava Y N <pranavayn@google.com>
---
 src/mainboard/google/fatcat/variants/ruby/gpio.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/mainboard/google/fatcat/variants/ruby/gpio.c b/src/mainboard/google/fatcat/variants/ruby/gpio.c
index 6324a5d9b8..215bf9c61a 100644
--- a/src/mainboard/google/fatcat/variants/ruby/gpio.c
+++ b/src/mainboard/google/fatcat/variants/ruby/gpio.c
@@ -381,7 +381,7 @@ static const struct pad_config gpio_table[] = {
 	/* GPP_V16:     GPP_V16_VCCST_EN */
 	PAD_CFG_NF(GPP_V16, NONE, DEEP, NF1),
 	/* GPP_V17:     SLP_S0_GATE_R */
-	PAD_CFG_GPO(GPP_V17, 1, PLTRST),
+	PAD_CFG_GPO(GPP_V17, 1, DEEP),
 };
 
 /* Early pad configuration in bootblock */

From 490dba2a8b08b49ac7bce888a27666e9c3f8e25b Mon Sep 17 00:00:00 2001
From: Kapil Porwal <kapilporwal@google.com>
Date: Fri, 30 Jan 2026 16:56:39 +0530
Subject: [PATCH 3240/3886] ec/google/chromeec: Implement host command to read
 lid state

On non-LPC platforms (such as those using I2C or SPI for EC comms),
the EC memory map is not directly accessible via memory-mapped I/O.
Instead, these platforms must use the EC_CMD_READ_MEMMAP host command
to retrieve system information.

Implement google_chromeec_get_switches() using this host command for
non-LPC systems. This enables get_lid_switch() to function correctly
on eSPI-based and other non-LPC mainboards, allowing them to support
lid-controlled logic.

BUG=none
TEST=Verify the LID state using get_lid_switch() on Google/Quartz.

Change-Id: Ic7dbe1bcf6b528dfefc168e2f0de0357430dc84d
Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91008
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
---
 src/ec/google/chromeec/ec.c       | 34 +++++++++++++++++++++++++++++++
 src/ec/google/chromeec/switches.c |  2 --
 2 files changed, 34 insertions(+), 2 deletions(-)

diff --git a/src/ec/google/chromeec/ec.c b/src/ec/google/chromeec/ec.c
index 804bda0c81..e6de2c9810 100644
--- a/src/ec/google/chromeec/ec.c
+++ b/src/ec/google/chromeec/ec.c
@@ -1992,3 +1992,37 @@ bool google_chromeec_is_critically_low_on_battery(void)
 	return google_chromeec_is_below_critical_threshold() &&
 	       !google_chromeec_is_charger_present();
 }
+
+#if !CONFIG(EC_GOOGLE_CHROMEEC_LPC)
+static int google_chromeec_read_memmap(uint8_t offset, uint8_t size, void *dest)
+{
+	struct ec_params_read_memmap params;
+
+	params.offset = offset;
+	params.size = size;
+
+	struct chromeec_command cmd = {
+		.cmd_code = EC_CMD_READ_MEMMAP,
+		.cmd_version = 0,
+		.cmd_data_in = &params,
+		.cmd_data_out = dest,
+		.cmd_size_in = sizeof(params),
+		.cmd_size_out = size,
+	};
+
+	return google_chromeec_command(&cmd);
+}
+
+/*
+ * Return the byte of EC switch states e.g. lid state
+ */
+uint8_t google_chromeec_get_switches(void)
+{
+	uint8_t flags;
+
+	if (google_chromeec_read_memmap(EC_MEMMAP_SWITCHES, sizeof(flags), &flags))
+		return 0;
+
+	return flags;
+}
+#endif
diff --git a/src/ec/google/chromeec/switches.c b/src/ec/google/chromeec/switches.c
index e35e7722ea..066a788f71 100644
--- a/src/ec/google/chromeec/switches.c
+++ b/src/ec/google/chromeec/switches.c
@@ -5,7 +5,6 @@
 #include <elog.h>
 #include <security/vboot/misc.h>
 
-#if CONFIG(EC_GOOGLE_CHROMEEC_LPC)
 /*
  * Retrieves the state of the lid switch.
  *
@@ -32,7 +31,6 @@ int get_lid_switch(void)
 
 	return !!(google_chromeec_get_switches() & EC_SWITCH_LID_OPEN);
 }
-#endif
 
 int get_recovery_mode_switch(void)
 {

From 37ef6bc245564df58c89d16646e1a99dd19e0b5c Mon Sep 17 00:00:00 2001
From: Kapil Porwal <kapilporwal@google.com>
Date: Fri, 30 Jan 2026 17:01:39 +0530
Subject: [PATCH 3241/3886] mb/google/bluey: Enable vboot lid switch support

With the ChromeEC driver now supporting lid state retrieval via host
commands for non-LPC platforms, enable VBOOT_LID_SWITCH for Bluey.

This allows the mainboard to utilize vboot features that depend on
the lid status, such as preventing boot when the lid is closed.

BUG=none
TEST=Verify LID status on Google/Quartz.

Change-Id: Idfc45258170e86a673aede9fc63a87a9a2ca3c3b
Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91009
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/google/bluey/Kconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/src/mainboard/google/bluey/Kconfig b/src/mainboard/google/bluey/Kconfig
index 4cbb5e06ba..2021787699 100644
--- a/src/mainboard/google/bluey/Kconfig
+++ b/src/mainboard/google/bluey/Kconfig
@@ -149,6 +149,7 @@ config MAINBOARD_VENDOR
 
 config VBOOT
 	select VBOOT_ALWAYS_ENABLE_DISPLAY
+	select VBOOT_LID_SWITCH if MAINBOARD_HAS_CHROME_EC
 	select VBOOT_NO_BOARD_SUPPORT if BOARD_GOOGLE_MODEL_BLUEY
 	select VBOOT_VBNV_FLASH
 

From eecd2b49cabe3eb76a532af64b8a349ac0d0a2b9 Mon Sep 17 00:00:00 2001
From: Kapil Porwal <kapilporwal@google.com>
Date: Fri, 30 Jan 2026 19:37:25 +0530
Subject: [PATCH 3242/3886] mb/google/bluey: Skip display initialization when
 lid is closed

If the system is powered on while the lid is closed (e.g., via a
power button or auto-power-on event), there is no need to initialize
the internal display.

Update display_startup() to check the lid state via get_lid_switch().
Skipping initialization in this state reduces unnecessary power
consumption and slightly improves boot time for closed-lid scenarios.

BUG=none
TEST=Verify display does not initialize when lid is closed on
Google/Quartz.

Change-Id: I2ec48876f102b7309a1401aa9d7bdc0fdc96791a
Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91011
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/google/bluey/mainboard.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/mainboard/google/bluey/mainboard.c b/src/mainboard/google/bluey/mainboard.c
index 9fff83bba7..b12edfdabe 100644
--- a/src/mainboard/google/bluey/mainboard.c
+++ b/src/mainboard/google/bluey/mainboard.c
@@ -140,7 +140,7 @@ bool mainboard_needs_pcie_init(void)
 
 static void display_startup(void)
 {
-	if (!display_init_required()) {
+	if (!display_init_required() || (CONFIG(VBOOT_LID_SWITCH) && !get_lid_switch())) {
 		printk(BIOS_INFO, "Skipping display init.\n");
 		return;
 	}

From b999d71c492bdf19e54117c3ffb42170cb352690 Mon Sep 17 00:00:00 2001
From: Kapil Porwal <kapilporwal@google.com>
Date: Fri, 30 Jan 2026 19:39:57 +0530
Subject: [PATCH 3243/3886] mb/google/bluey: Restrict low battery LED alert to
 closed-lid state

Refine the critically low battery alert logic to only trigger when the
lid is closed. This prevents the red LED alert from firing
unnecessarily when the system is open, or ensures it specifically
targets the user notification flow designed for a closed-lid blocked
boot.

This change requires VBOOT_LID_SWITCH to be enabled to correctly
detect the lid state in romstage.

BUG=none
TEST=Verify LED behavior on Google/Quartz with low battery and AC unplugged.

Change-Id: Ibe9e7b3bd46527f72a873f161cc359e0641c35f4
Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91012
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
---
 src/mainboard/google/bluey/romstage.c | 9 +++++++--
 1 file changed, 7 insertions(+), 2 deletions(-)

diff --git a/src/mainboard/google/bluey/romstage.c b/src/mainboard/google/bluey/romstage.c
index 2b8e95c201..33878069c6 100644
--- a/src/mainboard/google/bluey/romstage.c
+++ b/src/mainboard/google/bluey/romstage.c
@@ -2,6 +2,7 @@
 
 #include <arch/stages.h>
 #include "board.h"
+#include <bootmode.h>
 #include <cbmem.h>
 #include <commonlib/bsd/cbmem_id.h>
 #include <commonlib/coreboot_tables.h>
@@ -109,8 +110,12 @@ static void early_setup_usb(void)
 
 void platform_romstage_main(void)
 {
-	/* Set LED to Red to alert the user visually */
-	if (CONFIG(EC_GOOGLE_CHROMEEC) && google_chromeec_is_critically_low_on_battery())
+	/*
+	 * Only alert the user (set LED to red in color) if the lid is closed and the battery
+	 * is critically low without AC power.
+	 */
+	if (CONFIG(EC_GOOGLE_CHROMEEC) && CONFIG(VBOOT_LID_SWITCH) && !get_lid_switch() &&
+			 google_chromeec_is_critically_low_on_battery())
 		google_chromeec_set_lightbar_rgb(0xff, 0xff, 0x00, 0x00);
 
 	/* Setup early USB related config */

From 051516af1add5c1c54cc0fde03c5b0345e12132d Mon Sep 17 00:00:00 2001
From: Appukuttan V K <appukuttan.vk@intel.com>
Date: Mon, 19 Jan 2026 23:31:54 +0530
Subject: [PATCH 3244/3886] soc/intel/pantherlake: Consolidate WCL SKUs and
 update GT VR settings

Simplify Wildcat Lake SKU configuration by consolidating multiple
SKU variants into a single WCL_SKU_1 configuration. All WCL device
IDs (WCL_ID_2 through WCL_ID_5) now map to WCL_SKU_1 instead of
having separate SKU definitions.

Additionally, update GT domain VR controller settings for WCL_SKU_1:
 - Set IccMax to 36A (144 in register units) for GT domain

BUG=b:467349691
TEST=Build ocelot and verify system boots with consolidated WCL SKU
configuration. Confirm GT VR IccMax is set to 36A in coreboot logs.

Change-Id: I6466c150bcd712430cf2595db5be13039688fecb
Signed-off-by: Appukuttan V K <appukuttan.vk@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90803
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: P, Usha <usha.p@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/soc/intel/pantherlake/chip.h         | 12 ++++--------
 src/soc/intel/pantherlake/chipset_wcl.cb |  4 ++++
 2 files changed, 8 insertions(+), 8 deletions(-)

diff --git a/src/soc/intel/pantherlake/chip.h b/src/soc/intel/pantherlake/chip.h
index 1301813aaf..15a1501e18 100644
--- a/src/soc/intel/pantherlake/chip.h
+++ b/src/soc/intel/pantherlake/chip.h
@@ -78,10 +78,6 @@ enum soc_intel_pantherlake_sku {
 	PTL_SKU_6,
 	PTL_SKU_7,
 	WCL_SKU_1,
-	WCL_SKU_2,
-	WCL_SKU_3,
-	WCL_SKU_4,
-	WCL_SKU_5,
 	MAX_PTL_SKUS,
 };
 
@@ -119,10 +115,10 @@ static const struct soc_intel_pantherlake_power_map {
 	{ PCI_DID_INTEL_PTL_H_ID_7, PTL_CORE_4, TDP_25W, PTL_SKU_7, PTL_TDC_4 },
 	{ PCI_DID_INTEL_PTL_H_ID_8, PTL_CORE_3, TDP_25W, PTL_SKU_2, PTL_TDC_3 },
 	{ PCI_DID_INTEL_WCL_ID_1, WCL_CORE, TDP_15W, WCL_SKU_1, WCL_TDC_1 },
-	{ PCI_DID_INTEL_WCL_ID_2, WCL_CORE, TDP_15W, WCL_SKU_2, WCL_TDC_1 },
-	{ PCI_DID_INTEL_WCL_ID_3, WCL_CORE, TDP_15W, WCL_SKU_3, WCL_TDC_1 },
-	{ PCI_DID_INTEL_WCL_ID_4, WCL_CORE, TDP_15W, WCL_SKU_4, WCL_TDC_1 },
-	{ PCI_DID_INTEL_WCL_ID_5, WCL_CORE, TDP_15W, WCL_SKU_5, WCL_TDC_1 },
+	{ PCI_DID_INTEL_WCL_ID_2, WCL_CORE, TDP_15W, WCL_SKU_1, WCL_TDC_1 },
+	{ PCI_DID_INTEL_WCL_ID_3, WCL_CORE, TDP_15W, WCL_SKU_1, WCL_TDC_1 },
+	{ PCI_DID_INTEL_WCL_ID_4, WCL_CORE, TDP_15W, WCL_SKU_1, WCL_TDC_1 },
+	{ PCI_DID_INTEL_WCL_ID_5, WCL_CORE, TDP_15W, WCL_SKU_1, WCL_TDC_1 },
 };
 
 /* Types of display ports */
diff --git a/src/soc/intel/pantherlake/chipset_wcl.cb b/src/soc/intel/pantherlake/chipset_wcl.cb
index 465ad05ad9..4d8d296aa5 100644
--- a/src/soc/intel/pantherlake/chipset_wcl.cb
+++ b/src/soc/intel/pantherlake/chipset_wcl.cb
@@ -8,6 +8,10 @@ chip soc/intel/pantherlake
 		.tdp_pl4 = 93,
 	}"
 
+	register "icc_max[WCL_SKU_1]" = "{
+		[VR_DOMAIN_GT] = 36 * 4,
+	}"
+
 	# Reduce the size of BasicMemoryTests to speed up the boot time.
 	register "lower_basic_mem_test_size" = "true"
 

From c242193ca42efc5d89173441bb5c9be69208867e Mon Sep 17 00:00:00 2001
From: Patrick Rudolph <patrick.rudolph@9elements.com>
Date: Sat, 31 Jan 2026 07:23:55 +0100
Subject: [PATCH 3245/3886] device/smbus: Add i2c_eeprom_read
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Expose the existing i2c block read functionality usually used in
romstage to the smbus_bus_operations for use in ramstage.

This allows faster reading of I2C EEPROM in ramstage.

TEST=Can read I2C EEPROM on Lenovo X220 using I2C block read.

Change-Id: I1264f17317c3095f9661b0ab6aa3124a00ce86c5
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91028
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
---
 src/device/smbus_ops.c                   |  8 ++++++++
 src/include/device/smbus.h               |  2 ++
 src/southbridge/intel/common/smbus_ops.c | 21 +++++++++++++++++----
 3 files changed, 27 insertions(+), 4 deletions(-)

diff --git a/src/device/smbus_ops.c b/src/device/smbus_ops.c
index d08965c7e0..0bff636c62 100644
--- a/src/device/smbus_ops.c
+++ b/src/device/smbus_ops.c
@@ -35,3 +35,11 @@ int smbus_block_write(struct device *dev, u8 cmd, u8 bytes, const u8 *buffer)
 	return ops_smbus_bus(get_pbus_smbus(dev))->block_write(dev, cmd,
 							       bytes, buffer);
 }
+
+int smbus_i2c_eeprom_read(struct device *dev, u8 cmd, u8 bytes, u8 *buffer)
+{
+	CHECK_PRESENCE(i2c_eeprom_read);
+
+	return ops_smbus_bus(get_pbus_smbus(dev))->i2c_eeprom_read(dev, cmd,
+								   bytes, buffer);
+}
diff --git a/src/include/device/smbus.h b/src/include/device/smbus.h
index 171e304472..02ddec661a 100644
--- a/src/include/device/smbus.h
+++ b/src/include/device/smbus.h
@@ -16,6 +16,7 @@ struct smbus_bus_operations {
 	int (*block_read)(struct device *dev, u8 cmd, u8 bytes, u8 *buffer);
 	int (*block_write)(struct device *dev, u8 cmd, u8 bytes,
 			   const u8 *buffer);
+	int (*i2c_eeprom_read)(struct device *dev, u8 offset, u8 bytes, u8 *buffer);
 };
 
 static inline const struct smbus_bus_operations *ops_smbus_bus(struct bus *bus)
@@ -54,6 +55,7 @@ static inline int smbus_write_byte(struct device *const dev, u8 addr, u8 val)
 
 int smbus_block_read(struct device *dev, u8 cmd, u8 bytes, u8 *buffer);
 int smbus_block_write(struct device *dev, u8 cmd, u8 bytes, const u8 *buffer);
+int smbus_i2c_eeprom_read(struct device *dev, u8 cmd, u8 bytes, u8 *buffer);
 #endif
 
 #endif /* DEVICE_SMBUS_H */
diff --git a/src/southbridge/intel/common/smbus_ops.c b/src/southbridge/intel/common/smbus_ops.c
index 8542ba3d04..242603765a 100644
--- a/src/southbridge/intel/common/smbus_ops.c
+++ b/src/southbridge/intel/common/smbus_ops.c
@@ -56,11 +56,24 @@ static int lsmbus_block_read(struct device *dev, u8 cmd, u8 bytes, u8 *buf)
 	return do_smbus_block_read(res->base, device, cmd, bytes, buf);
 }
 
+static int lsmbus_i2c_eeprom_read(struct device *dev, u8 offset, u8 bytes, u8 *buf)
+{
+	u16 device;
+	struct resource *res;
+	struct bus *pbus;
+
+	device = dev->path.i2c.device;
+	pbus = get_pbus_smbus(dev);
+	res = find_resource(pbus->dev, PCI_BASE_ADDRESS_4);
+	return do_i2c_eeprom_read(res->base, device, offset, bytes, buf);
+}
+
 struct smbus_bus_operations lops_smbus_bus = {
-	.read_byte	= lsmbus_read_byte,
-	.write_byte	= lsmbus_write_byte,
-	.block_read	= lsmbus_block_read,
-	.block_write	= lsmbus_block_write,
+	.read_byte		= lsmbus_read_byte,
+	.write_byte		= lsmbus_write_byte,
+	.block_read		= lsmbus_block_read,
+	.block_write		= lsmbus_block_write,
+	.i2c_eeprom_read	= lsmbus_i2c_eeprom_read,
 };
 
 void smbus_read_resources(struct device *dev)

From 702cec8635e94785633e6efa01a218189b764ef5 Mon Sep 17 00:00:00 2001
From: Patrick Rudolph <patrick.rudolph@9elements.com>
Date: Sun, 1 Feb 2026 14:04:33 +0100
Subject: [PATCH 3246/3886] drivers/i2c/at24rf08c/lenovo_serials: Fix out of
 bounds
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Ensure that the mainboard version string is fully contained within
one 128byte block of the EEPROM. Since it's read from offset 0x27
it can be 89 characters long. One byte for the final null terminator.

Change-Id: I264ea2d1f634bb3493858da9f066bd6cef1ca960
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91041
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
---
 src/drivers/i2c/at24rf08c/lenovo_serials.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/drivers/i2c/at24rf08c/lenovo_serials.c b/src/drivers/i2c/at24rf08c/lenovo_serials.c
index dd09dda7fe..8b355062e5 100644
--- a/src/drivers/i2c/at24rf08c/lenovo_serials.c
+++ b/src/drivers/i2c/at24rf08c/lenovo_serials.c
@@ -154,7 +154,7 @@ void smbios_system_set_uuid(u8 *uuid)
 
 const char *smbios_mainboard_version(void)
 {
-	static char result[100];
+	static char result[90];
 	static int already_read;
 	struct device *dev;
 	int len;

From 77a39d588ec87d0c60e7354025a12f4c6373946e Mon Sep 17 00:00:00 2001
From: Patrick Rudolph <patrick.rudolph@9elements.com>
Date: Sat, 31 Jan 2026 07:38:43 +0100
Subject: [PATCH 3247/3886] drivers/i2c/at24rf08c: Use I2C block read
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Use I2C block read command to access the VPD EEPROM to speed up
SMBIOS table generation, but keep the single byte read as fallback.

Shrink the size of the mainboard version string to not crossing the
128 byte block boundary.

TEST=On Lenovo X220 the BS_WRITE_TABLES is 15 msec faster.

Change-Id: Ida21a8dc653551440e79b062abcce9194d11bef4
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91029
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
---
 src/drivers/i2c/at24rf08c/lenovo_serials.c | 51 +++++++++++-----------
 1 file changed, 26 insertions(+), 25 deletions(-)

diff --git a/src/drivers/i2c/at24rf08c/lenovo_serials.c b/src/drivers/i2c/at24rf08c/lenovo_serials.c
index 8b355062e5..34b98004c6 100644
--- a/src/drivers/i2c/at24rf08c/lenovo_serials.c
+++ b/src/drivers/i2c/at24rf08c/lenovo_serials.c
@@ -1,5 +1,6 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
+#include <assert.h>
 #include <build.h>
 #include <types.h>
 #include <string.h>
@@ -38,18 +39,22 @@ static int at24rf08c_read_byte(struct device *dev, u8 addr)
 	return t;
 }
 
-static void at24rf08c_read_string_dev(struct device *dev, u8 start,
-				      u8 len, char *result)
+static void at24rf08c_read_string_dev(struct device *dev, const u8 start,
+				      const u8 len, char *result)
 {
-	int i;
-	for (i = 0; i < len; i++) {
-		int t = at24rf08c_read_byte(dev, start + i);
+	assert(start + len <= 128);
 
-		if (t < 0x20 || t > 0x7f) {
+	int ret = smbus_i2c_eeprom_read(dev, start, len, (u8 *)result);
+	if (ret != len) {
+		for (int i = 0; i < len; i++)
+			result[i] = at24rf08c_read_byte(dev, start + i);
+	}
+
+	for (int i = 0; i < len; i++) {
+		if (result[i] < 0x20) {
 			memcpy(result, ERROR_STRING, sizeof(ERROR_STRING));
 			return;
 		}
-		result[i] = t;
 	}
 	result[len] = '\0';
 }
@@ -106,7 +111,7 @@ const char *smbios_mainboard_product_name(void)
 void smbios_system_set_uuid(u8 *uuid)
 {
 	static char result[16];
-	unsigned int i;
+	u8 buf[16];
 	static int already_read;
 	struct device *dev;
 	const int remap[16] = {
@@ -119,34 +124,30 @@ void smbios_system_set_uuid(u8 *uuid)
 		return;
 	}
 
-	memset(result, 0, sizeof(result));
+	memset(uuid, 0, 16);
 
 	dev = dev_find_slot_on_smbus(1, 0x56);
 	if (dev == NULL) {
 		printk(BIOS_WARNING, "EEPROM not found\n");
 		already_read = 1;
-		memset(uuid, 0, 16);
 		return;
 	}
 
-	for (i = 0; i < 16; i++) {
-		int t;
-		int j;
-		/* After a register write AT24RF08C (which we issued in init function) sometimes stops responding.
-		   Retry several times in case of failure.
-		*/
-		for (j = 0; j < 100; j++) {
-			t = smbus_read_byte(dev, 0x12 + i);
-			if (t >= 0)
-				break;
+	int ret = smbus_i2c_eeprom_read(dev, 0x12, 16, buf);
+	if (ret != 16) {
+		for (int i = 0; i < 16; i++) {
+			int c = at24rf08c_read_byte(dev, 0x12 + i);
+			if (c < 0) {
+				already_read = 1;
+				return;
+			}
+			buf[i] = c;
 		}
-		if (t < 0) {
-			memset(result, 0, sizeof(result));
-			break;
-		}
-		result[remap[i]] = t;
 	}
 
+	for (int i = 0; i < 16; i++)
+		result[remap[i]] = buf[i];
+
 	already_read = 1;
 
 	memcpy(uuid, result, 16);

From e2d7bd16b31d40e0a3589ad2cddd2f7c83e62ba8 Mon Sep 17 00:00:00 2001
From: Cindy Lu <luyi8@huaqin.corp-partner.google.com>
Date: Thu, 22 Jan 2026 23:21:14 +0800
Subject: [PATCH 3248/3886] drivers/mipi: Add support for TG-XTI05101 panel

Add TaiGuan panel TG-XTI05101 serializable data to CBFS.
Datasheet:TG-XTI05101-01A-SPEC-V1_20260202.pdf

[INFO ]  CBFS: Found 'panel-TG_XTI05101' @0x40b40 size 0x1bb in mcache @0xfffdd474

BUG=b:477767887
TEST= check above log during booting
BRANCH=None

Change-Id: I9cdae763d2d570a96228bcc9e3b987b4a3910751
Signed-off-by: Cindy Lu <luyi8@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90872
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Yang Wu <wuyang5@huaqin.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
---
 src/drivers/mipi/Kconfig             |   3 +
 src/drivers/mipi/Makefile.mk         |   2 +
 src/drivers/mipi/panel-TG_XTI05101.c | 227 +++++++++++++++++++++++++++
 3 files changed, 232 insertions(+)
 create mode 100644 src/drivers/mipi/panel-TG_XTI05101.c

diff --git a/src/drivers/mipi/Kconfig b/src/drivers/mipi/Kconfig
index 10d46628b4..80533ffd27 100644
--- a/src/drivers/mipi/Kconfig
+++ b/src/drivers/mipi/Kconfig
@@ -75,6 +75,9 @@ config MIPI_PANEL_STA_HIMAX83102_J02
 config MIPI_PANEL_STA_ILI9882T
 	bool
 
+config MIPI_PANEL_TG_XTI05101
+	bool
+
 config MIPI_PANEL_TM_TL121BVMS07_00C
 	bool
 
diff --git a/src/drivers/mipi/Makefile.mk b/src/drivers/mipi/Makefile.mk
index e814414d82..4aa4d1217b 100644
--- a/src/drivers/mipi/Makefile.mk
+++ b/src/drivers/mipi/Makefile.mk
@@ -35,6 +35,8 @@ panel-params-$(CONFIG_MIPI_PANEL_STA_ER88577) += panel-STA_ER88577
 panel-params-$(CONFIG_MIPI_PANEL_STA_HIMAX83102_J02) += panel-STA_HIMAX83102_J02
 panel-params-$(CONFIG_MIPI_PANEL_STA_ILI9882T) += panel-STA_ILI9882T
 
+panel-params-$(CONFIG_MIPI_PANEL_TG_XTI05101) += panel-TG_XTI05101
+
 panel-params-$(CONFIG_MIPI_PANEL_TM_TL121BVMS07_00C) += panel-TM_TL121BVMS07_00C
 
 panel-params-$(CONFIG_MIPI_PANEL_VIS_RM69299) += panel-VIS_RM69299
diff --git a/src/drivers/mipi/panel-TG_XTI05101.c b/src/drivers/mipi/panel-TG_XTI05101.c
new file mode 100644
index 0000000000..71a1ad0d0f
--- /dev/null
+++ b/src/drivers/mipi/panel-TG_XTI05101.c
@@ -0,0 +1,227 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <mipi/panel.h>
+
+struct panel_serializable_data TG_XTI05101 = {
+	.edid = {
+		.ascii_string = "XTI05101",
+		.manufacturer_name = "TG",
+		.panel_bits_per_color = 8,
+		.panel_bits_per_pixel = 24,
+		.mode = {
+			.pixel_clock = 69167,
+			.lvds_dual_channel = 0,
+			.refresh = 60,
+			.ha = 800, .hbl = 72, .hso = 24, .hspw = 24,
+			.va = 1280, .vbl = 42, .vso = 30, .vspw = 4,
+			.phsync = '-', .pvsync = '-',
+			.x_mm = 135, .y_mm = 216,
+		},
+	},
+	.init = {
+		PANEL_DELAY(24),
+		PANEL_DCS(0xE0, 0x00),
+		PANEL_DCS(0xE1, 0x93),
+		PANEL_DCS(0xE2, 0x65),
+		PANEL_DCS(0xE3, 0xF8),
+		PANEL_DCS(0x80, 0x03),
+		PANEL_DCS(0xE0, 0x01),
+		PANEL_DCS(0x0C, 0x74),
+		PANEL_DCS(0x17, 0x00),
+		PANEL_DCS(0x18, 0xD7),
+		PANEL_DCS(0x19, 0x01),
+		PANEL_DCS(0x1A, 0x00),
+		PANEL_DCS(0x1B, 0xD7),
+		PANEL_DCS(0x1C, 0x01),
+		PANEL_DCS(0x24, 0xFE),
+		PANEL_DCS(0x37, 0x19),
+		PANEL_DCS(0x35, 0x28),
+		PANEL_DCS(0x38, 0x05),
+		PANEL_DCS(0x39, 0x08),
+		PANEL_DCS(0x3A, 0x12),
+		PANEL_DCS(0x3C, 0x78),
+		PANEL_DCS(0x3D, 0xFF),
+		PANEL_DCS(0x3E, 0xFF),
+		PANEL_DCS(0x3F, 0x7F),
+		PANEL_DCS(0x40, 0x06),
+		PANEL_DCS(0x41, 0xA0),
+		PANEL_DCS(0x43, 0x1E),
+		PANEL_DCS(0x44, 0x0B),
+		PANEL_DCS(0x55, 0x02),
+		PANEL_DCS(0x57, 0x6A),
+		PANEL_DCS(0x59, 0x0A),
+		PANEL_DCS(0x5A, 0x2E),
+		PANEL_DCS(0x5B, 0x1A),
+		PANEL_DCS(0x5C, 0x15),
+
+		/* -------- Gamma -------- */
+		PANEL_DCS(0x5D, 0x7F),
+		PANEL_DCS(0x5E, 0x58),
+		PANEL_DCS(0x5F, 0x46),
+		PANEL_DCS(0x60, 0x39),
+		PANEL_DCS(0x61, 0x35),
+		PANEL_DCS(0x62, 0x27),
+		PANEL_DCS(0x63, 0x2B),
+		PANEL_DCS(0x64, 0x16),
+		PANEL_DCS(0x65, 0x30),
+		PANEL_DCS(0x66, 0x2E),
+		PANEL_DCS(0x67, 0x2F),
+		PANEL_DCS(0x68, 0x4D),
+		PANEL_DCS(0x69, 0x3C),
+		PANEL_DCS(0x6A, 0x43),
+		PANEL_DCS(0x6B, 0x36),
+		PANEL_DCS(0x6C, 0x31),
+		PANEL_DCS(0x6D, 0x24),
+		PANEL_DCS(0x6E, 0x14),
+		PANEL_DCS(0x6F, 0x02),
+		PANEL_DCS(0x70, 0x7F),
+		PANEL_DCS(0x71, 0x58),
+		PANEL_DCS(0x72, 0x46),
+		PANEL_DCS(0x73, 0x39),
+		PANEL_DCS(0x74, 0x35),
+		PANEL_DCS(0x75, 0x27),
+		PANEL_DCS(0x76, 0x2B),
+		PANEL_DCS(0x77, 0x16),
+		PANEL_DCS(0x78, 0x30),
+		PANEL_DCS(0x79, 0x2E),
+		PANEL_DCS(0x7A, 0x2F),
+		PANEL_DCS(0x7B, 0x4D),
+		PANEL_DCS(0x7C, 0x3C),
+		PANEL_DCS(0x7D, 0x43),
+		PANEL_DCS(0x7E, 0x36),
+		PANEL_DCS(0x7F, 0x31),
+		PANEL_DCS(0x80, 0x24),
+		PANEL_DCS(0x81, 0x14),
+		PANEL_DCS(0x82, 0x02),
+
+		/* -------- Page 2 -------- */
+		PANEL_DCS(0xE0, 0x02),
+		PANEL_DCS(0x00, 0x52),
+		PANEL_DCS(0x01, 0x5F),
+		PANEL_DCS(0x02, 0x5F),
+		PANEL_DCS(0x03, 0x50),
+		PANEL_DCS(0x04, 0x77),
+		PANEL_DCS(0x05, 0x57),
+		PANEL_DCS(0x06, 0x5F),
+		PANEL_DCS(0x07, 0x4E),
+		PANEL_DCS(0x08, 0x4C),
+		PANEL_DCS(0x09, 0x5F),
+		PANEL_DCS(0x0A, 0x4A),
+		PANEL_DCS(0x0B, 0x48),
+		PANEL_DCS(0x0C, 0x5F),
+		PANEL_DCS(0x0D, 0x46),
+		PANEL_DCS(0x0E, 0x44),
+		PANEL_DCS(0x0F, 0x40),
+		PANEL_DCS(0x10, 0x5F),
+		PANEL_DCS(0x11, 0x5F),
+		PANEL_DCS(0x12, 0x5F),
+		PANEL_DCS(0x13, 0x5F),
+		PANEL_DCS(0x14, 0x5F),
+		PANEL_DCS(0x15, 0x5F),
+		PANEL_DCS(0x16, 0x53),
+		PANEL_DCS(0x17, 0x5F),
+		PANEL_DCS(0x18, 0x5F),
+		PANEL_DCS(0x19, 0x51),
+		PANEL_DCS(0x1A, 0x77),
+		PANEL_DCS(0x1B, 0x57),
+		PANEL_DCS(0x1C, 0x5F),
+		PANEL_DCS(0x1D, 0x4F),
+		PANEL_DCS(0x1E, 0x4D),
+		PANEL_DCS(0x1F, 0x5F),
+		PANEL_DCS(0x20, 0x4B),
+		PANEL_DCS(0x21, 0x49),
+		PANEL_DCS(0x22, 0x5F),
+		PANEL_DCS(0x23, 0x47),
+		PANEL_DCS(0x24, 0x45),
+		PANEL_DCS(0x25, 0x41),
+		PANEL_DCS(0x26, 0x5F),
+		PANEL_DCS(0x27, 0x5F),
+		PANEL_DCS(0x28, 0x5F),
+		PANEL_DCS(0x29, 0x5F),
+		PANEL_DCS(0x2A, 0x5F),
+		PANEL_DCS(0x2B, 0x5F),
+		PANEL_DCS(0x2C, 0x13),
+		PANEL_DCS(0x2D, 0x1F),
+		PANEL_DCS(0x2E, 0x1F),
+		PANEL_DCS(0x2F, 0x01),
+		PANEL_DCS(0x30, 0x17),
+		PANEL_DCS(0x31, 0x17),
+		PANEL_DCS(0x32, 0x1F),
+		PANEL_DCS(0x33, 0x0D),
+		PANEL_DCS(0x34, 0x0F),
+		PANEL_DCS(0x35, 0x1F),
+		PANEL_DCS(0x36, 0x05),
+		PANEL_DCS(0x37, 0x07),
+		PANEL_DCS(0x38, 0x1F),
+		PANEL_DCS(0x39, 0x09),
+		PANEL_DCS(0x3A, 0x0B),
+		PANEL_DCS(0x3B, 0x11),
+		PANEL_DCS(0x3C, 0x1F),
+		PANEL_DCS(0x3D, 0x1F),
+		PANEL_DCS(0x3E, 0x1F),
+		PANEL_DCS(0x3F, 0x1F),
+		PANEL_DCS(0x40, 0x1F),
+		PANEL_DCS(0x41, 0x1F),
+		PANEL_DCS(0x42, 0x12),
+		PANEL_DCS(0x43, 0x1F),
+		PANEL_DCS(0x44, 0x1F),
+		PANEL_DCS(0x45, 0x00),
+		PANEL_DCS(0x46, 0x17),
+		PANEL_DCS(0x47, 0x17),
+		PANEL_DCS(0x48, 0x1F),
+		PANEL_DCS(0x49, 0x0C),
+		PANEL_DCS(0x4A, 0x0E),
+		PANEL_DCS(0x4B, 0x1F),
+		PANEL_DCS(0x4C, 0x04),
+		PANEL_DCS(0x4D, 0x06),
+		PANEL_DCS(0x4E, 0x1F),
+		PANEL_DCS(0x4F, 0x08),
+		PANEL_DCS(0x50, 0x0A),
+		PANEL_DCS(0x51, 0x10),
+		PANEL_DCS(0x52, 0x1F),
+		PANEL_DCS(0x53, 0x1F),
+		PANEL_DCS(0x54, 0x1F),
+		PANEL_DCS(0x55, 0x1F),
+		PANEL_DCS(0x56, 0x1F),
+		PANEL_DCS(0x57, 0x1F),
+		PANEL_DCS(0x58, 0x40),
+		PANEL_DCS(0x5B, 0x10),
+		PANEL_DCS(0x5C, 0x06),
+		PANEL_DCS(0x5D, 0x40),
+		PANEL_DCS(0x5E, 0x00),
+		PANEL_DCS(0x5F, 0x00),
+		PANEL_DCS(0x60, 0x40),
+		PANEL_DCS(0x61, 0x03),
+		PANEL_DCS(0x62, 0x04),
+		PANEL_DCS(0x63, 0x6C),
+		PANEL_DCS(0x64, 0x6C),
+		PANEL_DCS(0x65, 0x75),
+		PANEL_DCS(0x66, 0x08),
+		PANEL_DCS(0x67, 0xB4),
+		PANEL_DCS(0x68, 0x08),
+		PANEL_DCS(0x69, 0x6C),
+		PANEL_DCS(0x6A, 0x6C),
+		PANEL_DCS(0x6B, 0x0C),
+		PANEL_DCS(0x6D, 0x00),
+		PANEL_DCS(0x6E, 0x00),
+		PANEL_DCS(0x6F, 0x88),
+		PANEL_DCS(0x75, 0xBB),
+		PANEL_DCS(0x76, 0x00),
+		PANEL_DCS(0x77, 0x05),
+		PANEL_DCS(0x78, 0x2A),
+		PANEL_DCS(0xE0, 0x04),
+		PANEL_DCS(0x00, 0x0E),
+		PANEL_DCS(0x02, 0xB3),
+		PANEL_DCS(0x09, 0x61),
+		PANEL_DCS(0x0E, 0x48),
+		PANEL_DCS(0x2B, 0x0F),
+		PANEL_DCS(0x37, 0x58),
+		PANEL_DCS(0xE0, 0x00),
+		PANEL_DCS(0x11),
+		PANEL_DELAY(120),
+		PANEL_DCS(0x29),
+		PANEL_DELAY(20),
+
+		PANEL_END,
+	},
+};

From 0efea195b21dedc93358119c304b398706abf4d9 Mon Sep 17 00:00:00 2001
From: Cindy Lu <luyi8@huaqin.corp-partner.google.com>
Date: Fri, 23 Jan 2026 16:19:42 +0800
Subject: [PATCH 3249/3886] mb/google/corsola/var/wugtrio: Add TG-XTI05101 MIPI
 panel

Add TG-XTI05101 MIPI panel for Wugtrio.
Datasheet:TG-XTI05101-01A-SPEC-V1_20260202.pdf

BUG=b:479758139
TEST=emerge-staryu coreboot depthcharge libpayload chromeos-bootimage
     can see the fw screen,jump to kernel and can see chromeos logo
BRANCH=corsola

Change-Id: Ibec69165fe39675d6e6ef4e0db7733825af7bf56
Signed-off-by: Cindy Lu <luyi8@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90873
Reviewed-by: Yang Wu <wuyang5@huaqin.corp-partner.google.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/google/corsola/Kconfig         | 1 +
 src/mainboard/google/corsola/panel_wugtrio.c | 8 ++++++++
 2 files changed, 9 insertions(+)

diff --git a/src/mainboard/google/corsola/Kconfig b/src/mainboard/google/corsola/Kconfig
index 1f249ac1a1..b137588191 100644
--- a/src/mainboard/google/corsola/Kconfig
+++ b/src/mainboard/google/corsola/Kconfig
@@ -77,6 +77,7 @@ config BOARD_SPECIFIC_OPTIONS
 	select MIPI_PANEL_STA_ER88577 if BOARD_GOOGLE_WUGTRIO
 	select MIPI_PANEL_STA_HIMAX83102_J02 if BOARD_GOOGLE_STARMIE
 	select MIPI_PANEL_STA_ILI9882T if BOARD_GOOGLE_STARMIE
+	select MIPI_PANEL_TG_XTI05101 if BOARD_GOOGLE_WUGTRIO
 
 config VBOOT
 	select EC_GOOGLE_CHROMEEC_SWITCHES
diff --git a/src/mainboard/google/corsola/panel_wugtrio.c b/src/mainboard/google/corsola/panel_wugtrio.c
index 0603ce0516..7a729b2724 100644
--- a/src/mainboard/google/corsola/panel_wugtrio.c
+++ b/src/mainboard/google/corsola/panel_wugtrio.c
@@ -49,6 +49,14 @@ static struct panel_description wugtrio_panels[] = {
 		.disp_path = DISP_PATH_MIPI,
 		.orientation = LB_FB_ORIENTATION_RIGHT_UP,
 	},
+	/*  TaiGuan Corporation panel with bias IC on it */
+	[10] = {
+		.configure_backlight = backlight_control,
+		.power_on = mipi_panel_power_on,
+		.name = "TG_XTI05101",
+		.disp_path = DISP_PATH_MIPI,
+		.orientation = LB_FB_ORIENTATION_RIGHT_UP,
+	},
 };
 
 struct panel_description *get_panel_description(void)

From 7c57c69e03b70cdb3136010ecf75ddd0ae6127fd Mon Sep 17 00:00:00 2001
From: Hualin Wei <weihualin@huaqin.corp-partner.google.com>
Date: Mon, 2 Feb 2026 10:09:33 +0800
Subject: [PATCH 3250/3886] mb/google/fatcat/var/lapis: Improve USB2 port 6
 strength

Improving the driving capabilities of USB2 enables the eye
diagram of a USB camera to pass the test.

BUG=b:478790360
TEST=emerge-fatcat coreboot, EA test pass

Change-Id: Id400fb541fd1c797ea602e3f8e12be07ed05b5b8
Signed-off-by: Hualin Wei <weihualin@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91047
Reviewed-by: Pranava Y N <pranavayn@google.com>
Reviewed-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/google/fatcat/variants/lapis/overridetree.cb | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/mainboard/google/fatcat/variants/lapis/overridetree.cb b/src/mainboard/google/fatcat/variants/lapis/overridetree.cb
index 930a464fbf..6d6961e15b 100644
--- a/src/mainboard/google/fatcat/variants/lapis/overridetree.cb
+++ b/src/mainboard/google/fatcat/variants/lapis/overridetree.cb
@@ -76,7 +76,7 @@ chip soc/intel/pantherlake
 	register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # LED
 	register "usb2_ports[3]" = "USB2_PORT_MID(OC_SKIP)" # Type-A Port A0 (MB)
 	register "usb2_ports[4]" = "USB2_PORT_MID(OC_SKIP)" # Type-A Port A1 (DB)
-	register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)" # USB HUB (USB2 Camera)
+	register "usb2_ports[5]" = "USB2_PORT_LONG(OC_SKIP)" # USB HUB (USB2 Camera)
 	register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" # Fingerprint
 	register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # Discrete Bluetooth
 

From a69f91b5817cf8da90d8036b7afd5d6bc4be9b21 Mon Sep 17 00:00:00 2001
From: Appukuttan V K <appukuttan.vk@intel.com>
Date: Tue, 3 Feb 2026 14:35:22 +0530
Subject: [PATCH 3251/3886] mb/google/ocelot: Update GT VR controller
 configuration

This patch implements the recommended BIOS power delivery settings
described in Intel WW03 2026 Wildcat Lake platform message of the
week (844458).

Key changes:
 - Enable acoustic noise mitigation with SLEW_FAST_4 for GT domain
 - Enable fast package C-state ramp disable for GT domain
 - Update fast_vmode_i_trip to 25A (was 38A)
 - Enable GT VR fast voltage mode and CEP

BUG=b:467349691
TEST=Build ocelot and verify that the system boots to UI with the
updated parameters.

 [SPEW ]  IccMax[1]:0x90
 [SPEW ]  EnableFastVmode[1]:0x1
 [SPEW ]  IccLimit[1]:0x64
 [SPEW ]  CepEnable[1]:0x1
 [SPEW ]  FastPkgCRampDisable[1]:0x1
 [SPEW ]  SlowSlewRate[1]:0x1
 [SPEW ]  AcousticNoiseMitigation:0x1

Change-Id: I76cefc79457c6bcfb250ba3525c501a126b526fb
Signed-off-by: Appukuttan V K <appukuttan.vk@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91073
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: P, Usha <usha.p@intel.com>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
---
 .../variants/baseboard/ocelot/devicetree.cb       | 15 ++++++++++-----
 1 file changed, 10 insertions(+), 5 deletions(-)

diff --git a/src/mainboard/google/ocelot/variants/baseboard/ocelot/devicetree.cb b/src/mainboard/google/ocelot/variants/baseboard/ocelot/devicetree.cb
index 9391ac9d37..23b276e15a 100644
--- a/src/mainboard/google/ocelot/variants/baseboard/ocelot/devicetree.cb
+++ b/src/mainboard/google/ocelot/variants/baseboard/ocelot/devicetree.cb
@@ -29,6 +29,12 @@ chip soc/intel/pantherlake
 	register "tcss_ports[0]" = "TCSS_PORT_EMPTY"	# Disable USB-C Port 0
 	register "tcss_ports[1]" = "TCSS_PORT_EMPTY"	# Disable USB-C Port 1
 
+	# Acoustic Noise settings and slew rate configuration:
+	# Slew rate for GT Domain: Fast/4
+	register "enable_acoustic_noise_mitigation" = "true"
+	register "disable_fast_pkgc_ramp[VR_DOMAIN_GT]" = "true"
+	register "slow_slew_rate_config[VR_DOMAIN_GT]" = "SLEW_FAST_4"
+
 	# Enable SAGv
 	register "sagv" = "SAGV_ENABLED"
 
@@ -61,15 +67,14 @@ chip soc/intel/pantherlake
 	# Enable Energy Reporting
 	register "pch_pm_energy_report_enable" = "true"
 
-	# Reference: 858124 Power Delivery Guide Rev1p0, 830097 Powermap Rev1p1
+	# Reference: 844458 MOW WW03
 	# fast_vmode_i_trip values are derived from ICCMax with a safety margin.
 	# ITRIP_NOM is approximately 0.70 of ICCMax
 	# TODO: Update with actual i_trip values.
-
+	register "enable_fast_vmode[VR_DOMAIN_GT]" = "true"
+	register "cep_enable[VR_DOMAIN_GT]" = "true"
 	register "fast_vmode_i_trip[WCL_CORE]" = "{
-		[VR_DOMAIN_IA] = 35 * 4,
-		[VR_DOMAIN_GT] = 35 * 4,
-		[VR_DOMAIN_SA] = 24 * 4
+		[VR_DOMAIN_GT] = 25 * 4,
 	}"
 
 	register "serial_io_uart_mode" = "{

From 8108e9f2b61733ec8fbdfbed522efd8d417e51b7 Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Mon, 2 Feb 2026 10:59:03 -0600
Subject: [PATCH 3252/3886] drivers/generic/gpio_keys: Set ACPI status to
 HIDDEN

The gpio-keys is a Linux-specific ACPI interface, and the kernel driver
does not care what the status is. Windows does not have drivers
however, so set the ACPI status to HIDDEN to avoid an unknown device
from appearing in Device Manager.

TEST=build/boot Win11 on google/magolor, verify PENH device no longer
listed under Device Manager.

Change-Id: I8a476e57b36c26795bfe9605e725ba3d5f860b3a
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91068
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/drivers/generic/gpio_keys/gpio_keys.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/drivers/generic/gpio_keys/gpio_keys.c b/src/drivers/generic/gpio_keys/gpio_keys.c
index f5df0c45bc..e837e04158 100644
--- a/src/drivers/generic/gpio_keys/gpio_keys.c
+++ b/src/drivers/generic/gpio_keys/gpio_keys.c
@@ -86,7 +86,7 @@ static void gpio_keys_fill_ssdt_generator(const struct device *dev)
 		acpi_dp_add_child(dsd, "button-0", child);
 	acpi_dp_write(dsd);
 
-	acpigen_write_STA(acpi_device_status(dev));
+	acpigen_write_STA(ACPI_STATUS_DEVICE_HIDDEN_ON);
 
 	acpigen_pop_len(); /* Device */
 	acpigen_pop_len(); /* Scope */

From 2b976ddd8a759550d7d190d35421e90a488f5293 Mon Sep 17 00:00:00 2001
From: Jamie Chen <jamie.chen@intel.com>
Date: Thu, 8 Jan 2026 17:39:28 +0800
Subject: [PATCH 3253/3886] mb/google/{nissa,trulo}: select
 HAVE_CHIPSETINIT_BINARY

According to Intel SA Doc#873795, select HAVE_CHIPSETINIT_BINARY
on nissa and trulo baseboard.

BUG=b:447290550
TEST=1. build coreboot
     2. check log to confirm load chipsetinit.bin successfully.

Change-Id: I66a0c1a3dbfbbf563461b319c5839910dfc11656
Signed-off-by: Jamie Chen <jamie.chen@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90698
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Kao, Ben <ben.kao@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/google/brya/Kconfig | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/src/mainboard/google/brya/Kconfig b/src/mainboard/google/brya/Kconfig
index 39d88156bb..6a4082dfdf 100644
--- a/src/mainboard/google/brya/Kconfig
+++ b/src/mainboard/google/brya/Kconfig
@@ -96,6 +96,7 @@ config BOARD_GOOGLE_BASEBOARD_NISSA
 	select DRIVERS_GFX_GENERIC
 	select DRIVERS_INTEL_ISH
 	select FSP_TYPE_IOT if !CHROMEOS
+	select HAVE_CHIPSETINIT_BINARY
 	select MAINBOARD_DISABLE_STAGE_CACHE
 	select MAINBOARD_HAS_EARLY_LIBGFXINIT
 	select MEMORY_SOLDERDOWN
@@ -115,6 +116,7 @@ config BOARD_GOOGLE_BASEBOARD_TRULO
 	select DRIVERS_GFX_GENERIC
 	select DRIVERS_INTEL_ISH
 	select DRIVER_INTEL_ISH_HAS_MAIN_FW
+	select HAVE_CHIPSETINIT_BINARY
 	select MAINBOARD_DISABLE_STAGE_CACHE
 	select MAINBOARD_HAS_EARLY_LIBGFXINIT
 	select MEMORY_SOLDERDOWN

From a45590126f4c86f4808f32e1c6d93908d099c6f6 Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Mon, 2 Feb 2026 09:39:24 -0600
Subject: [PATCH 3254/3886] soc/intel/jasperlake: add soc_acpi_name entry for
 IGD
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

JSL was missing an entry for the IGD, preventing the use of
DRIVERS_GFX_GENERIC since the call to acpi_device_scope() for it
returned null. Add the missing IGD entry, consistent with other
modern Intel SoCs.

TEST=build/boot google/magolor with chip drivers/gfx/generic entry
and verify SSDT entry correctly created.

Change-Id: Idf1d8992b45c60f68fd2b156c6e7cae816df84b4
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91064
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
---
 src/soc/intel/jasperlake/chip.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/src/soc/intel/jasperlake/chip.c b/src/soc/intel/jasperlake/chip.c
index e1f6099127..5b4a8232d4 100644
--- a/src/soc/intel/jasperlake/chip.c
+++ b/src/soc/intel/jasperlake/chip.c
@@ -63,6 +63,7 @@ const char *soc_acpi_name(const struct device *dev)
 
 	switch (dev->path.pci.devfn) {
 	case SA_DEVFN_ROOT:	return "MCHC";
+	case SA_DEVFN_IGD:	return "GFX0";
 	case SA_DEVFN_IPU:	return "IPU0";
 	case PCH_DEVFN_ISH:	return "ISHB";
 	case SA_DEVFN_GNA:	return "GNA";

From a49bd226687d4496488ed9f2cdd6edb47d045a25 Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Mon, 2 Feb 2026 12:37:45 -0600
Subject: [PATCH 3255/3886] mb/google/dedede: Use DRIVERS_GFX_GENERIC for
 laptops

For dedede laptops, switch from using GMA_DEFAULT_PANEL(0), previously
set in the baseboard, to using a per-variant gfx generic chip driver,
so that variants which use IPU/MIPI cameras can add the IPUA camera
device in a subsequent commit.

For dedede laptops, this is a no-op; for Chromeboxes, it removes the
previously defined internal panel which they do not have.

TEST=build/boot dexi, magolor variants. verify ACPI brightness controls
still functional under Linux and Windows for the latter.

Change-Id: I83fd2d952ca785bef8210024cbbb9280688d6a5e
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91065
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
---
 src/mainboard/google/dedede/Kconfig                   |  1 +
 .../google/dedede/variants/awasuki/overridetree.cb    | 11 +++++++++++
 .../google/dedede/variants/baseboard/devicetree.cb    |  4 +---
 .../google/dedede/variants/beadrix/overridetree.cb    | 11 +++++++++++
 .../google/dedede/variants/blipper/overridetree.cb    | 11 +++++++++++
 .../google/dedede/variants/boten/overridetree.cb      | 11 +++++++++++
 .../google/dedede/variants/bugzzy/overridetree.cb     | 11 +++++++++++
 .../google/dedede/variants/cappy2/overridetree.cb     | 11 +++++++++++
 .../google/dedede/variants/corori/overridetree.cb     | 11 +++++++++++
 .../google/dedede/variants/cret/overridetree.cb       | 11 +++++++++++
 .../google/dedede/variants/drawcia/overridetree.cb    | 11 +++++++++++
 .../google/dedede/variants/driblee/overridetree.cb    | 11 +++++++++++
 .../google/dedede/variants/galtic/overridetree.cb     | 11 +++++++++++
 .../google/dedede/variants/gooey/overridetree.cb      | 11 +++++++++++
 .../google/dedede/variants/haboki/overridetree.cb     | 11 +++++++++++
 .../google/dedede/variants/kracko/overridetree.cb     | 11 +++++++++++
 .../google/dedede/variants/lalala/overridetree.cb     | 11 +++++++++++
 .../google/dedede/variants/lantis/overridetree.cb     | 11 +++++++++++
 .../google/dedede/variants/madoo/overridetree.cb      | 11 +++++++++++
 .../google/dedede/variants/magolor/overridetree.cb    | 11 +++++++++++
 .../google/dedede/variants/metaknight/overridetree.cb | 11 +++++++++++
 .../google/dedede/variants/pirika/overridetree.cb     | 11 +++++++++++
 .../google/dedede/variants/sasuke/overridetree.cb     | 11 +++++++++++
 .../google/dedede/variants/sasukette/overridetree.cb  | 11 +++++++++++
 .../google/dedede/variants/storo/overridetree.cb      | 11 +++++++++++
 .../google/dedede/variants/waddledee/overridetree.cb  | 11 +++++++++++
 .../google/dedede/variants/waddledoo/overridetree.cb  | 11 +++++++++++
 27 files changed, 277 insertions(+), 3 deletions(-)

diff --git a/src/mainboard/google/dedede/Kconfig b/src/mainboard/google/dedede/Kconfig
index a17c756046..d6af56057d 100644
--- a/src/mainboard/google/dedede/Kconfig
+++ b/src/mainboard/google/dedede/Kconfig
@@ -278,6 +278,7 @@ if BOARD_GOOGLE_BASEBOARD_DEDEDE
 
 config BASEBOARD_DEDEDE_LAPTOP
 	def_bool n
+	select DRIVERS_GFX_GENERIC
 	select SYSTEM_TYPE_LAPTOP
 
 config CHROMEOS
diff --git a/src/mainboard/google/dedede/variants/awasuki/overridetree.cb b/src/mainboard/google/dedede/variants/awasuki/overridetree.cb
index 570403f81f..f179a77388 100644
--- a/src/mainboard/google/dedede/variants/awasuki/overridetree.cb
+++ b/src/mainboard/google/dedede/variants/awasuki/overridetree.cb
@@ -84,6 +84,17 @@ chip soc/intel/jasperlake
 	register "SdCardPowerEnableActiveHigh" = "0"
 
 	device domain 0 on
+		device ref igpu on
+			chip drivers/gfx/generic
+				register "device_count" = "1"
+				# DDIA for eDP
+				register "device[0].name" = ""LCD0""
+				# Internal panel on the first port of the graphics chip
+				register "device[0].type" = "panel"
+
+				device generic 0 on end
+			end
+		end
 		device ref dptf on
 			chip drivers/intel/dptf
 				## sensor information
diff --git a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb
index 240c3e6c4b..d7f91cda46 100644
--- a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb
+++ b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb
@@ -228,9 +228,7 @@ chip soc/intel/jasperlake
 	register "xhci_lfps_sampling_offtime_ms" = "9"
 
 	device domain 0 on
-		device ref igpu on
-			register "gfx" = "GMA_DEFAULT_PANEL(0)"
-		end
+		device ref igpu on end
 		device ref dptf on
 			# Default DPTF Policy for all Dedede boards if not overridden
 			chip drivers/intel/dptf
diff --git a/src/mainboard/google/dedede/variants/beadrix/overridetree.cb b/src/mainboard/google/dedede/variants/beadrix/overridetree.cb
index a1c95148ba..6693a6e9c3 100644
--- a/src/mainboard/google/dedede/variants/beadrix/overridetree.cb
+++ b/src/mainboard/google/dedede/variants/beadrix/overridetree.cb
@@ -60,6 +60,17 @@ chip soc/intel/jasperlake
 	register "SerialIoI2cMode[PchSerialIoIndexI2C5]" = "PchSerialIoPci"
 
 	device domain 0 on
+		device ref igpu on
+			chip drivers/gfx/generic
+				register "device_count" = "1"
+				# DDIA for eDP
+				register "device[0].name" = ""LCD0""
+				# Internal panel on the first port of the graphics chip
+				register "device[0].type" = "panel"
+
+				device generic 0 on end
+			end
+		end
 		device ref dptf on
 			# Default DPTF Policy for all Dedede boards if not overridden
 			chip drivers/intel/dptf
diff --git a/src/mainboard/google/dedede/variants/blipper/overridetree.cb b/src/mainboard/google/dedede/variants/blipper/overridetree.cb
index 535c0f6934..1e510536a4 100644
--- a/src/mainboard/google/dedede/variants/blipper/overridetree.cb
+++ b/src/mainboard/google/dedede/variants/blipper/overridetree.cb
@@ -63,6 +63,17 @@ chip soc/intel/jasperlake
 	register "FastPkgCRampDisable" = "1"
 
 	device domain 0 on
+		device ref igpu on
+			chip drivers/gfx/generic
+				register "device_count" = "1"
+				# DDIA for eDP
+				register "device[0].name" = ""LCD0""
+				# Internal panel on the first port of the graphics chip
+				register "device[0].type" = "panel"
+
+				device generic 0 on end
+			end
+		end
 		device ref dptf on
 			chip drivers/intel/dptf
 				## Passive Policy
diff --git a/src/mainboard/google/dedede/variants/boten/overridetree.cb b/src/mainboard/google/dedede/variants/boten/overridetree.cb
index 5e3614c0b4..aa54ba3059 100644
--- a/src/mainboard/google/dedede/variants/boten/overridetree.cb
+++ b/src/mainboard/google/dedede/variants/boten/overridetree.cb
@@ -89,6 +89,17 @@ chip soc/intel/jasperlake
 	register "xhci_lfps_sampling_offtime_ms" = "0"
 
 	device domain 0 on
+		device ref igpu on
+			chip drivers/gfx/generic
+				register "device_count" = "1"
+				# DDIA for eDP
+				register "device[0].name" = ""LCD0""
+				# Internal panel on the first port of the graphics chip
+				register "device[0].type" = "panel"
+
+				device generic 0 on end
+			end
+		end
 		device ref dptf on
 			chip drivers/intel/dptf
 				## Passive Policy
diff --git a/src/mainboard/google/dedede/variants/bugzzy/overridetree.cb b/src/mainboard/google/dedede/variants/bugzzy/overridetree.cb
index 441707e940..dfce134c30 100644
--- a/src/mainboard/google/dedede/variants/bugzzy/overridetree.cb
+++ b/src/mainboard/google/dedede/variants/bugzzy/overridetree.cb
@@ -94,6 +94,17 @@ chip soc/intel/jasperlake
 	register "SerialIoI2cMode[PchSerialIoIndexI2C4]" = "PchSerialIoPci"
 
 	device domain 0 on
+		device ref igpu on
+			chip drivers/gfx/generic
+				register "device_count" = "1"
+				# DDIA for eDP
+				register "device[0].name" = ""LCD0""
+				# Internal panel on the first port of the graphics chip
+				register "device[0].type" = "panel"
+
+				device generic 0 on end
+			end
+		end
 		device ref dptf on
 			chip drivers/intel/dptf
 				register "options.tsr[0].desc" = ""Memory""
diff --git a/src/mainboard/google/dedede/variants/cappy2/overridetree.cb b/src/mainboard/google/dedede/variants/cappy2/overridetree.cb
index 59c7f9fd1c..372fe482e8 100644
--- a/src/mainboard/google/dedede/variants/cappy2/overridetree.cb
+++ b/src/mainboard/google/dedede/variants/cappy2/overridetree.cb
@@ -77,6 +77,17 @@ chip soc/intel/jasperlake
 	}" # Camera
 
 	device domain 0 on
+		device ref igpu on
+			chip drivers/gfx/generic
+				register "device_count" = "1"
+				# DDIA for eDP
+				register "device[0].name" = ""LCD0""
+				# Internal panel on the first port of the graphics chip
+				register "device[0].type" = "panel"
+
+				device generic 0 on end
+			end
+		end
 		device ref dptf on
 			chip drivers/intel/dptf
 				## Passive Policy
diff --git a/src/mainboard/google/dedede/variants/corori/overridetree.cb b/src/mainboard/google/dedede/variants/corori/overridetree.cb
index 76aadb44dd..c1a3cb0f72 100644
--- a/src/mainboard/google/dedede/variants/corori/overridetree.cb
+++ b/src/mainboard/google/dedede/variants/corori/overridetree.cb
@@ -44,6 +44,17 @@ chip soc/intel/jasperlake
 	register "SerialIoGSpiCsMode[PchSerialIoIndexGSPI0]" = "0"
 
 	device domain 0 on
+		device ref igpu on
+			chip drivers/gfx/generic
+				register "device_count" = "1"
+				# DDIA for eDP
+				register "device[0].name" = ""LCD0""
+				# Internal panel on the first port of the graphics chip
+				register "device[0].type" = "panel"
+
+				device generic 0 on end
+			end
+		end
 		device ref dptf on
 			chip drivers/intel/dptf
 				## Passive Policy
diff --git a/src/mainboard/google/dedede/variants/cret/overridetree.cb b/src/mainboard/google/dedede/variants/cret/overridetree.cb
index 3156c9096f..726328c2ef 100644
--- a/src/mainboard/google/dedede/variants/cret/overridetree.cb
+++ b/src/mainboard/google/dedede/variants/cret/overridetree.cb
@@ -52,6 +52,17 @@ chip soc/intel/jasperlake
 		},
 	}"
 	device domain 0 on
+		device ref igpu on
+			chip drivers/gfx/generic
+				register "device_count" = "1"
+				# DDIA for eDP
+				register "device[0].name" = ""LCD0""
+				# Internal panel on the first port of the graphics chip
+				register "device[0].type" = "panel"
+
+				device generic 0 on end
+			end
+		end
 		device ref dptf on
 			chip drivers/intel/dptf
 				## Passive Policy
diff --git a/src/mainboard/google/dedede/variants/drawcia/overridetree.cb b/src/mainboard/google/dedede/variants/drawcia/overridetree.cb
index 8e13098ccc..ddc65a219f 100644
--- a/src/mainboard/google/dedede/variants/drawcia/overridetree.cb
+++ b/src/mainboard/google/dedede/variants/drawcia/overridetree.cb
@@ -82,6 +82,17 @@ chip soc/intel/jasperlake
 	register "FastPkgCRampDisable" = "1"
 
 	device domain 0 on
+		device ref igpu on
+			chip drivers/gfx/generic
+				register "device_count" = "1"
+				# DDIA for eDP
+				register "device[0].name" = ""LCD0""
+				# Internal panel on the first port of the graphics chip
+				register "device[0].type" = "panel"
+
+				device generic 0 on end
+			end
+		end
 		device ref ipu on
 			chip drivers/intel/mipi_camera
 				register "acpi_uid" = "0x50000"
diff --git a/src/mainboard/google/dedede/variants/driblee/overridetree.cb b/src/mainboard/google/dedede/variants/driblee/overridetree.cb
index 23d1875054..97614fa5b2 100644
--- a/src/mainboard/google/dedede/variants/driblee/overridetree.cb
+++ b/src/mainboard/google/dedede/variants/driblee/overridetree.cb
@@ -35,6 +35,17 @@ chip soc/intel/jasperlake
 	register "SerialIoGSpiCsMode[PchSerialIoIndexGSPI0]" = "0"
 
 	device domain 0 on
+		device ref igpu on
+			chip drivers/gfx/generic
+				register "device_count" = "1"
+				# DDIA for eDP
+				register "device[0].name" = ""LCD0""
+				# Internal panel on the first port of the graphics chip
+				register "device[0].type" = "panel"
+
+				device generic 0 on end
+			end
+		end
 		device ref dptf on
 			chip drivers/intel/dptf
 				## Passive Policy
diff --git a/src/mainboard/google/dedede/variants/galtic/overridetree.cb b/src/mainboard/google/dedede/variants/galtic/overridetree.cb
index 189029b5cd..8fbe6ead57 100644
--- a/src/mainboard/google/dedede/variants/galtic/overridetree.cb
+++ b/src/mainboard/google/dedede/variants/galtic/overridetree.cb
@@ -69,6 +69,17 @@ chip soc/intel/jasperlake
 	register "tcc_offset" = "8"     # TCC of 97C
 
 	device domain 0 on
+		device ref igpu on
+			chip drivers/gfx/generic
+				register "device_count" = "1"
+				# DDIA for eDP
+				register "device[0].name" = ""LCD0""
+				# Internal panel on the first port of the graphics chip
+				register "device[0].type" = "panel"
+
+				device generic 0 on end
+			end
+		end
 		device ref dptf on
 			# Default DPTF Policy for all Dedede boards if not overridden
 			chip drivers/intel/dptf
diff --git a/src/mainboard/google/dedede/variants/gooey/overridetree.cb b/src/mainboard/google/dedede/variants/gooey/overridetree.cb
index 0a73b9c471..05144d1ff4 100644
--- a/src/mainboard/google/dedede/variants/gooey/overridetree.cb
+++ b/src/mainboard/google/dedede/variants/gooey/overridetree.cb
@@ -68,6 +68,17 @@ chip soc/intel/jasperlake
 	register "xhci_lfps_sampling_offtime_ms" = "0"
 
 	device domain 0 on
+		device ref igpu on
+			chip drivers/gfx/generic
+				register "device_count" = "1"
+				# DDIA for eDP
+				register "device[0].name" = ""LCD0""
+				# Internal panel on the first port of the graphics chip
+				register "device[0].type" = "panel"
+
+				device generic 0 on end
+			end
+		end
 		device ref dptf on
 			chip drivers/intel/dptf
 				## Passive Policy
diff --git a/src/mainboard/google/dedede/variants/haboki/overridetree.cb b/src/mainboard/google/dedede/variants/haboki/overridetree.cb
index 7146bd899f..1341cd2e26 100644
--- a/src/mainboard/google/dedede/variants/haboki/overridetree.cb
+++ b/src/mainboard/google/dedede/variants/haboki/overridetree.cb
@@ -53,6 +53,17 @@ chip soc/intel/jasperlake
 	register "FastPkgCRampDisable" = "1"
 
 	device domain 0 on
+		device ref igpu on
+			chip drivers/gfx/generic
+				register "device_count" = "1"
+				# DDIA for eDP
+				register "device[0].name" = ""LCD0""
+				# Internal panel on the first port of the graphics chip
+				register "device[0].type" = "panel"
+
+				device generic 0 on end
+			end
+		end
 		device ref ipu on
 			chip drivers/intel/mipi_camera
 				register "acpi_uid" = "0x50000"
diff --git a/src/mainboard/google/dedede/variants/kracko/overridetree.cb b/src/mainboard/google/dedede/variants/kracko/overridetree.cb
index c45ccdc428..89d3a7ea96 100644
--- a/src/mainboard/google/dedede/variants/kracko/overridetree.cb
+++ b/src/mainboard/google/dedede/variants/kracko/overridetree.cb
@@ -65,6 +65,17 @@ chip soc/intel/jasperlake
 	register "tcc_offset" = "20"	# TCC of 85C
 
 	device domain 0 on
+		device ref igpu on
+			chip drivers/gfx/generic
+				register "device_count" = "1"
+				# DDIA for eDP
+				register "device[0].name" = ""LCD0""
+				# Internal panel on the first port of the graphics chip
+				register "device[0].type" = "panel"
+
+				device generic 0 on end
+			end
+		end
 		device ref dptf on
 			chip drivers/intel/dptf
 				# Default DPTF Policy for all drawcia boards if not overridden
diff --git a/src/mainboard/google/dedede/variants/lalala/overridetree.cb b/src/mainboard/google/dedede/variants/lalala/overridetree.cb
index 26569c52ca..e5041ae5b8 100644
--- a/src/mainboard/google/dedede/variants/lalala/overridetree.cb
+++ b/src/mainboard/google/dedede/variants/lalala/overridetree.cb
@@ -87,6 +87,17 @@ chip soc/intel/jasperlake
 	register "FastPkgCRampDisable" = "1"
 
 	device domain 0 on
+		device ref igpu on
+			chip drivers/gfx/generic
+				register "device_count" = "1"
+				# DDIA for eDP
+				register "device[0].name" = ""LCD0""
+				# Internal panel on the first port of the graphics chip
+				register "device[0].type" = "panel"
+
+				device generic 0 on end
+			end
+		end
 		device ref dptf on
 			chip drivers/intel/dptf
 				register "options.tsr[0].desc" = ""Memory""
diff --git a/src/mainboard/google/dedede/variants/lantis/overridetree.cb b/src/mainboard/google/dedede/variants/lantis/overridetree.cb
index 21e15d43ee..9159086945 100644
--- a/src/mainboard/google/dedede/variants/lantis/overridetree.cb
+++ b/src/mainboard/google/dedede/variants/lantis/overridetree.cb
@@ -90,6 +90,17 @@ chip soc/intel/jasperlake
 	register "FastPkgCRampDisable" = "1"
 
 	device domain 0 on
+		device ref igpu on
+			chip drivers/gfx/generic
+				register "device_count" = "1"
+				# DDIA for eDP
+				register "device[0].name" = ""LCD0""
+				# Internal panel on the first port of the graphics chip
+				register "device[0].type" = "panel"
+
+				device generic 0 on end
+			end
+		end
 		device ref dptf on
 			chip drivers/intel/dptf
 				register "options.tsr[0].desc" = ""Memory""
diff --git a/src/mainboard/google/dedede/variants/madoo/overridetree.cb b/src/mainboard/google/dedede/variants/madoo/overridetree.cb
index 801b947f1e..dea54bdc0e 100644
--- a/src/mainboard/google/dedede/variants/madoo/overridetree.cb
+++ b/src/mainboard/google/dedede/variants/madoo/overridetree.cb
@@ -57,6 +57,17 @@ chip soc/intel/jasperlake
 	register "SlowSlewRate" = "2"
 
 	device domain 0 on
+		device ref igpu on
+			chip drivers/gfx/generic
+				register "device_count" = "1"
+				# DDIA for eDP
+				register "device[0].name" = ""LCD0""
+				# Internal panel on the first port of the graphics chip
+				register "device[0].type" = "panel"
+
+				device generic 0 on end
+			end
+		end
 		device ref dptf on
 			chip drivers/intel/dptf
 				register "policies.passive" = "{
diff --git a/src/mainboard/google/dedede/variants/magolor/overridetree.cb b/src/mainboard/google/dedede/variants/magolor/overridetree.cb
index 45cd9971ca..e4d6ce4235 100644
--- a/src/mainboard/google/dedede/variants/magolor/overridetree.cb
+++ b/src/mainboard/google/dedede/variants/magolor/overridetree.cb
@@ -126,6 +126,17 @@ chip soc/intel/jasperlake
 	register "FastPkgCRampDisable" = "1"
 
 	device domain 0 on
+		device ref igpu on
+			chip drivers/gfx/generic
+				register "device_count" = "1"
+				# DDIA for eDP
+				register "device[0].name" = ""LCD0""
+				# Internal panel on the first port of the graphics chip
+				register "device[0].type" = "panel"
+
+				device generic 0 on end
+			end
+		end
 		device ref dptf on
 			chip drivers/intel/dptf
 				register "options.tsr[0].desc" = ""Memory""
diff --git a/src/mainboard/google/dedede/variants/metaknight/overridetree.cb b/src/mainboard/google/dedede/variants/metaknight/overridetree.cb
index 631fb5c5df..cafdaa1ff1 100644
--- a/src/mainboard/google/dedede/variants/metaknight/overridetree.cb
+++ b/src/mainboard/google/dedede/variants/metaknight/overridetree.cb
@@ -84,6 +84,17 @@ chip soc/intel/jasperlake
 	}"
 
 	device domain 0 on
+		device ref igpu on
+			chip drivers/gfx/generic
+				register "device_count" = "1"
+				# DDIA for eDP
+				register "device[0].name" = ""LCD0""
+				# Internal panel on the first port of the graphics chip
+				register "device[0].type" = "panel"
+
+				device generic 0 on end
+			end
+		end
 		device ref dptf on
 			chip drivers/intel/dptf
 				register "options.tsr[0].desc" = ""Memory""
diff --git a/src/mainboard/google/dedede/variants/pirika/overridetree.cb b/src/mainboard/google/dedede/variants/pirika/overridetree.cb
index 01f724c5fa..831ef975a2 100644
--- a/src/mainboard/google/dedede/variants/pirika/overridetree.cb
+++ b/src/mainboard/google/dedede/variants/pirika/overridetree.cb
@@ -78,6 +78,17 @@ chip soc/intel/jasperlake
 	register "tcc_offset" = "8"     # TCC of 97C
 
 	device domain 0 on
+		device ref igpu on
+			chip drivers/gfx/generic
+				register "device_count" = "1"
+				# DDIA for eDP
+				register "device[0].name" = ""LCD0""
+				# Internal panel on the first port of the graphics chip
+				register "device[0].type" = "panel"
+
+				device generic 0 on end
+			end
+		end
 		device ref dptf on
 			# Default DPTF Policy for all Dedede boards if not overridden
 			chip drivers/intel/dptf
diff --git a/src/mainboard/google/dedede/variants/sasuke/overridetree.cb b/src/mainboard/google/dedede/variants/sasuke/overridetree.cb
index 4be52ff3d2..ffef13129a 100644
--- a/src/mainboard/google/dedede/variants/sasuke/overridetree.cb
+++ b/src/mainboard/google/dedede/variants/sasuke/overridetree.cb
@@ -85,6 +85,17 @@ chip soc/intel/jasperlake
 	register "SerialIoI2cMode[PchSerialIoIndexI2C4]" = "PchSerialIoPci"
 
 	device domain 0 on
+		device ref igpu on
+			chip drivers/gfx/generic
+				register "device_count" = "1"
+				# DDIA for eDP
+				register "device[0].name" = ""LCD0""
+				# Internal panel on the first port of the graphics chip
+				register "device[0].type" = "panel"
+
+				device generic 0 on end
+			end
+		end
 		device ref dptf on
 			chip drivers/intel/dptf
 				register "options.tsr[0].desc" = ""Charger""
diff --git a/src/mainboard/google/dedede/variants/sasukette/overridetree.cb b/src/mainboard/google/dedede/variants/sasukette/overridetree.cb
index 90a7a10199..518a490246 100644
--- a/src/mainboard/google/dedede/variants/sasukette/overridetree.cb
+++ b/src/mainboard/google/dedede/variants/sasukette/overridetree.cb
@@ -96,6 +96,17 @@ chip soc/intel/jasperlake
 	register "xhci_lfps_sampling_offtime_ms" = "0"
 
 	device domain 0 on
+		device ref igpu on
+			chip drivers/gfx/generic
+				register "device_count" = "1"
+				# DDIA for eDP
+				register "device[0].name" = ""LCD0""
+				# Internal panel on the first port of the graphics chip
+				register "device[0].type" = "panel"
+
+				device generic 0 on end
+			end
+		end
 		device ref dptf on
 			chip drivers/intel/dptf
 				## Passive Policy
diff --git a/src/mainboard/google/dedede/variants/storo/overridetree.cb b/src/mainboard/google/dedede/variants/storo/overridetree.cb
index 729aff50a2..4dd66ef967 100644
--- a/src/mainboard/google/dedede/variants/storo/overridetree.cb
+++ b/src/mainboard/google/dedede/variants/storo/overridetree.cb
@@ -100,6 +100,17 @@ chip soc/intel/jasperlake
 	register "xhci_lfps_sampling_offtime_ms" = "0"
 
 	device domain 0 on
+		device ref igpu on
+			chip drivers/gfx/generic
+				register "device_count" = "1"
+				# DDIA for eDP
+				register "device[0].name" = ""LCD0""
+				# Internal panel on the first port of the graphics chip
+				register "device[0].type" = "panel"
+
+				device generic 0 on end
+			end
+		end
 		device ref dptf on
 			chip drivers/intel/dptf
 				## Passive Policy
diff --git a/src/mainboard/google/dedede/variants/waddledee/overridetree.cb b/src/mainboard/google/dedede/variants/waddledee/overridetree.cb
index 7356e95625..38f94e0b73 100644
--- a/src/mainboard/google/dedede/variants/waddledee/overridetree.cb
+++ b/src/mainboard/google/dedede/variants/waddledee/overridetree.cb
@@ -61,6 +61,17 @@ chip soc/intel/jasperlake
 	register "SerialIoI2cMode[PchSerialIoIndexI2C4]" = "PchSerialIoPci"
 
 	device domain 0 on
+		device ref igpu on
+			chip drivers/gfx/generic
+				register "device_count" = "1"
+				# DDIA for eDP
+				register "device[0].name" = ""LCD0""
+				# Internal panel on the first port of the graphics chip
+				register "device[0].type" = "panel"
+
+				device generic 0 on end
+			end
+		end
 		device ref ipu on end
 		device ref south_xhci on
 			chip drivers/usb/acpi
diff --git a/src/mainboard/google/dedede/variants/waddledoo/overridetree.cb b/src/mainboard/google/dedede/variants/waddledoo/overridetree.cb
index 9b9d308019..9df4f0e6a6 100644
--- a/src/mainboard/google/dedede/variants/waddledoo/overridetree.cb
+++ b/src/mainboard/google/dedede/variants/waddledoo/overridetree.cb
@@ -57,6 +57,17 @@ chip soc/intel/jasperlake
 	register "SerialIoI2cMode[PchSerialIoIndexI2C4]" = "PchSerialIoPci"
 
 	device domain 0 on
+		device ref igpu on
+			chip drivers/gfx/generic
+				register "device_count" = "1"
+				# DDIA for eDP
+				register "device[0].name" = ""LCD0""
+				# Internal panel on the first port of the graphics chip
+				register "device[0].type" = "panel"
+
+				device generic 0 on end
+			end
+		end
 		device ref ipu on
 			chip drivers/intel/mipi_camera
 				register "acpi_uid" = "0x50000"

From 1fb063c0da068741f39b496e76c6b8053763739f Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Mon, 2 Feb 2026 13:48:24 -0600
Subject: [PATCH 3256/3886] mb/google/dedede: Fix/Clean up IPU/MIPI camera
 settings

- Add IPUA device under igpu (gfx/generic) for variants with IPU:
  bugzzy, drawcia, haboki, lalala, magolor, storo, waddledoo
- Set ssdb.link_used to match cio2_prt
- Drop ssdb.rom_type and rom_address from mipi_camera sensor nodes;
  JSL doesn't use this, and it causes a BSOD under Windows
- Add missing sensor_name for CAMERA_SENSOR on magolor and waddledoo

TEST=build/boot Win11 on magolor, verify MIPI camera functional

Change-Id: I7fca3c6bb8bca9271a4dbaf888cc28304d6545a8
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91066
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 .../google/dedede/variants/bugzzy/overridetree.cb   | 10 ++++++----
 .../google/dedede/variants/drawcia/overridetree.cb  | 10 ++++++----
 .../google/dedede/variants/haboki/overridetree.cb   | 10 ++++++----
 .../google/dedede/variants/lalala/overridetree.cb   | 10 ++++++----
 .../google/dedede/variants/magolor/overridetree.cb  | 13 ++++++++-----
 .../google/dedede/variants/storo/overridetree.cb    | 10 ++++++----
 .../dedede/variants/waddledoo/overridetree.cb       | 11 +++++++----
 7 files changed, 45 insertions(+), 29 deletions(-)

diff --git a/src/mainboard/google/dedede/variants/bugzzy/overridetree.cb b/src/mainboard/google/dedede/variants/bugzzy/overridetree.cb
index dfce134c30..bf8fbbe913 100644
--- a/src/mainboard/google/dedede/variants/bugzzy/overridetree.cb
+++ b/src/mainboard/google/dedede/variants/bugzzy/overridetree.cb
@@ -96,11 +96,15 @@ chip soc/intel/jasperlake
 	device domain 0 on
 		device ref igpu on
 			chip drivers/gfx/generic
-				register "device_count" = "1"
+				register "device_count" = "2"
 				# DDIA for eDP
 				register "device[0].name" = ""LCD0""
 				# Internal panel on the first port of the graphics chip
 				register "device[0].type" = "panel"
+				# IPUA for IPUs
+				register "device[1].name" = ""IPUA""
+				register "device[1].non_vga_device" = "true"
+				register "device[1].addr" = "0x3480"
 
 				device generic 0 on end
 			end
@@ -257,13 +261,11 @@ chip soc/intel/jasperlake
 				register "device_type" = "INTEL_ACPI_CAMERA_SENSOR"
 
 				register "ssdb.lanes_used" = "4"
-				register "ssdb.link_used" = "1"
+				register "ssdb.link_used" = "2"
 				register "ssdb.platform" = "PLAT_JSL"
 				register "ssdb.vcm_type" = "VCM_DW9714"
 				register "vcm_address" = "0x0C"
 				register "vcm_name" = ""VCM0""
-				register "ssdb.rom_type" = "ROM_EEPROM_CAT24C08"
-				register "rom_address" = "0x50"
 				register "num_freq_entries" = "2"
 				register "link_freq[0]" = "360000000"
 				register "link_freq[1]" = "180000000"
diff --git a/src/mainboard/google/dedede/variants/drawcia/overridetree.cb b/src/mainboard/google/dedede/variants/drawcia/overridetree.cb
index ddc65a219f..a2c5bb0c02 100644
--- a/src/mainboard/google/dedede/variants/drawcia/overridetree.cb
+++ b/src/mainboard/google/dedede/variants/drawcia/overridetree.cb
@@ -84,11 +84,15 @@ chip soc/intel/jasperlake
 	device domain 0 on
 		device ref igpu on
 			chip drivers/gfx/generic
-				register "device_count" = "1"
+				register "device_count" = "2"
 				# DDIA for eDP
 				register "device[0].name" = ""LCD0""
 				# Internal panel on the first port of the graphics chip
 				register "device[0].type" = "panel"
+				# IPUA for IPUs
+				register "device[1].name" = ""IPUA""
+				register "device[1].non_vga_device" = "true"
+				register "device[1].addr" = "0x3480"
 
 				device generic 0 on end
 			end
@@ -317,13 +321,11 @@ chip soc/intel/jasperlake
 				register "device_type" = "INTEL_ACPI_CAMERA_SENSOR"
 
 				register "ssdb.lanes_used" = "4"
-				register "ssdb.link_used" = "1"
+				register "ssdb.link_used" = "2"
 				register "ssdb.platform" = "PLAT_JSL"
 				register "ssdb.vcm_type" = "VCM_DW9714"
 				register "vcm_address" = "0x0C"
 				register "vcm_name" = ""VCM0""
-				register "ssdb.rom_type" = "ROM_EEPROM_CAT24C08"
-				register "rom_address" = "0x50"
 				register "num_freq_entries" = "2"
 				register "link_freq[0]" = "360000000"
 				register "link_freq[1]" = "180000000"
diff --git a/src/mainboard/google/dedede/variants/haboki/overridetree.cb b/src/mainboard/google/dedede/variants/haboki/overridetree.cb
index 1341cd2e26..3eae64536b 100644
--- a/src/mainboard/google/dedede/variants/haboki/overridetree.cb
+++ b/src/mainboard/google/dedede/variants/haboki/overridetree.cb
@@ -55,11 +55,15 @@ chip soc/intel/jasperlake
 	device domain 0 on
 		device ref igpu on
 			chip drivers/gfx/generic
-				register "device_count" = "1"
+				register "device_count" = "2"
 				# DDIA for eDP
 				register "device[0].name" = ""LCD0""
 				# Internal panel on the first port of the graphics chip
 				register "device[0].type" = "panel"
+				# IPUA for IPUs
+				register "device[1].name" = ""IPUA""
+				register "device[1].non_vga_device" = "true"
+				register "device[1].addr" = "0x3480"
 
 				device generic 0 on end
 			end
@@ -231,13 +235,11 @@ chip soc/intel/jasperlake
 				register "device_type" = "INTEL_ACPI_CAMERA_SENSOR"
 
 				register "ssdb.lanes_used" = "4"
-				register "ssdb.link_used" = "1"
+				register "ssdb.link_used" = "2"
 				register "ssdb.platform" = "PLAT_JSL"
 				register "ssdb.vcm_type" = "VCM_DW9714"
 				register "vcm_address" = "0x0C"
 				register "vcm_name" = ""VCM0""
-				register "ssdb.rom_type" = "ROM_EEPROM_CAT24C08"
-				register "rom_address" = "0x50"
 				register "num_freq_entries" = "2"
 				register "link_freq[0]" = "360000000"
 				register "link_freq[1]" = "180000000"
diff --git a/src/mainboard/google/dedede/variants/lalala/overridetree.cb b/src/mainboard/google/dedede/variants/lalala/overridetree.cb
index e5041ae5b8..a680eed1e0 100644
--- a/src/mainboard/google/dedede/variants/lalala/overridetree.cb
+++ b/src/mainboard/google/dedede/variants/lalala/overridetree.cb
@@ -89,11 +89,15 @@ chip soc/intel/jasperlake
 	device domain 0 on
 		device ref igpu on
 			chip drivers/gfx/generic
-				register "device_count" = "1"
+				register "device_count" = "2"
 				# DDIA for eDP
 				register "device[0].name" = ""LCD0""
 				# Internal panel on the first port of the graphics chip
 				register "device[0].type" = "panel"
+				# IPUA for IPUs
+				register "device[1].name" = ""IPUA""
+				register "device[1].non_vga_device" = "true"
+				register "device[1].addr" = "0x3480"
 
 				device generic 0 on end
 			end
@@ -229,13 +233,11 @@ chip soc/intel/jasperlake
 				register "device_type" = "INTEL_ACPI_CAMERA_SENSOR"
 
 				register "ssdb.lanes_used" = "2"
-				register "ssdb.link_used" = "1"
+				register "ssdb.link_used" = "2"
 				register "ssdb.platform" = "PLAT_JSL"
 				register "ssdb.vcm_type" = "VCM_DW9714"
 				register "vcm_address" = "0x0C"
 				register "vcm_name" = ""VCM0""
-				register "ssdb.rom_type" = "ROM_EEPROM_CAT24C08"
-				register "rom_address" = "0x50"
 				register "num_freq_entries" = "1"
 				register "link_freq[0]" = "DEFAULT_LINK_FREQ"
 				register "remote_name" = ""IPU0""
diff --git a/src/mainboard/google/dedede/variants/magolor/overridetree.cb b/src/mainboard/google/dedede/variants/magolor/overridetree.cb
index e4d6ce4235..56116f7b5f 100644
--- a/src/mainboard/google/dedede/variants/magolor/overridetree.cb
+++ b/src/mainboard/google/dedede/variants/magolor/overridetree.cb
@@ -128,11 +128,15 @@ chip soc/intel/jasperlake
 	device domain 0 on
 		device ref igpu on
 			chip drivers/gfx/generic
-				register "device_count" = "1"
+				register "device_count" = "2"
 				# DDIA for eDP
 				register "device[0].name" = ""LCD0""
 				# Internal panel on the first port of the graphics chip
 				register "device[0].type" = "panel"
+				# IPUA for IPUs
+				register "device[1].name" = ""IPUA""
+				register "device[1].non_vga_device" = "true"
+				register "device[1].addr" = "0x3480"
 
 				device generic 0 on end
 			end
@@ -363,7 +367,7 @@ chip soc/intel/jasperlake
 				register "device_type" = "INTEL_ACPI_CAMERA_SENSOR"
 
 				register "ssdb.lanes_used" = "2"
-				register "ssdb.link_used" = "1"
+				register "ssdb.link_used" = "2"
 				register "ssdb.platform" = "PLAT_JSL"
 				register "ssdb.vcm_type" = "VCM_DW9714"
 				register "vcm_address" = "0x0C"
@@ -406,16 +410,15 @@ chip soc/intel/jasperlake
 				register "acpi_uid" = "0"
 				register "acpi_name" = ""CAM0""
 				register "chip_name" = ""Ov 8856 Camera""
+				register "sensor_name" = ""CJAJ813""
 				register "device_type" = "INTEL_ACPI_CAMERA_SENSOR"
 
 				register "ssdb.lanes_used" = "2"
-				register "ssdb.link_used" = "1"
+				register "ssdb.link_used" = "2"
 				register "ssdb.platform" = "PLAT_JSL"
 				register "ssdb.vcm_type" = "VCM_DW9714"
 				register "vcm_address" = "0x0C"
 				register "vcm_name" = ""VCM0""
-				register "ssdb.rom_type" = "ROM_EEPROM_CAT24C08"
-				register "rom_address" = "0x50"
 				register "num_freq_entries" = "2"
 				register "link_freq[0]" = "720000000"
 				register "link_freq[1]" = "360000000"
diff --git a/src/mainboard/google/dedede/variants/storo/overridetree.cb b/src/mainboard/google/dedede/variants/storo/overridetree.cb
index 4dd66ef967..c8c83634a2 100644
--- a/src/mainboard/google/dedede/variants/storo/overridetree.cb
+++ b/src/mainboard/google/dedede/variants/storo/overridetree.cb
@@ -102,11 +102,15 @@ chip soc/intel/jasperlake
 	device domain 0 on
 		device ref igpu on
 			chip drivers/gfx/generic
-				register "device_count" = "1"
+				register "device_count" = "2"
 				# DDIA for eDP
 				register "device[0].name" = ""LCD0""
 				# Internal panel on the first port of the graphics chip
 				register "device[0].type" = "panel"
+				# IPUA for IPUs
+				register "device[1].name" = ""IPUA""
+				register "device[1].non_vga_device" = "true"
+				register "device[1].addr" = "0x3480"
 
 				device generic 0 on end
 			end
@@ -237,13 +241,11 @@ chip soc/intel/jasperlake
 				register "device_type" = "INTEL_ACPI_CAMERA_SENSOR"
 
 				register "ssdb.lanes_used" = "4"
-				register "ssdb.link_used" = "1"
+				register "ssdb.link_used" = "2"
 				register "ssdb.platform" = "PLAT_JSL"
 				register "ssdb.vcm_type" = "VCM_DW9714"
 				register "vcm_address" = "0x0C"
 				register "vcm_name" = ""VCM0""
-				register "ssdb.rom_type" = "ROM_EEPROM_CAT24C08"
-				register "rom_address" = "0x50"
 				register "num_freq_entries" = "2"
 				register "link_freq[0]" = "360000000"
 				register "link_freq[1]" = "180000000"
diff --git a/src/mainboard/google/dedede/variants/waddledoo/overridetree.cb b/src/mainboard/google/dedede/variants/waddledoo/overridetree.cb
index 9df4f0e6a6..9c7379c2f0 100644
--- a/src/mainboard/google/dedede/variants/waddledoo/overridetree.cb
+++ b/src/mainboard/google/dedede/variants/waddledoo/overridetree.cb
@@ -59,11 +59,15 @@ chip soc/intel/jasperlake
 	device domain 0 on
 		device ref igpu on
 			chip drivers/gfx/generic
-				register "device_count" = "1"
+				register "device_count" = "2"
 				# DDIA for eDP
 				register "device[0].name" = ""LCD0""
 				# Internal panel on the first port of the graphics chip
 				register "device[0].type" = "panel"
+				# IPUA for IPUs
+				register "device[1].name" = ""IPUA""
+				register "device[1].non_vga_device" = "true"
+				register "device[1].addr" = "0x3480"
 
 				device generic 0 on end
 			end
@@ -162,6 +166,7 @@ chip soc/intel/jasperlake
 				register "acpi_name" = ""CAM1""
 				register "chip_name" = ""Ov 8856 Camera""
 				register "device_type" = "INTEL_ACPI_CAMERA_SENSOR"
+				register "sensor_name" = ""CJAJ813""
 
 				register "ssdb.lanes_used" = "4"
 				register "ssdb.link_used" = "2"
@@ -169,9 +174,6 @@ chip soc/intel/jasperlake
 				register "ssdb.vcm_type" = "VCM_DW9808"
 				register "vcm_address" = "0x0C"
 				register "vcm_name" = ""VCM0""
-				# placeholder; ROM type 24C1024 currently unsupported
-				# register "ssdb.rom_type" = "ROM_EEPROM_24C1024"
-				# register "rom_address" = "0x50"
 				register "num_freq_entries" = "2"
 				register "link_freq[0]" = "360000000"
 				register "link_freq[1]" = "180000000"
@@ -236,6 +238,7 @@ chip soc/intel/jasperlake
 				register "acpi_name" = ""CAM0""
 				register "chip_name" = ""Ov 9734 Camera""
 				register "device_type" = "INTEL_ACPI_CAMERA_SENSOR"
+				register "sensor_name" = ""CJAJ813""
 				register "has_power_resource" = "true"
 
 				register "ssdb.lanes_used" = "1"

From 987f61f1a6e5be7a09268cf0375f11b44586a115 Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Mon, 2 Feb 2026 19:04:13 -0600
Subject: [PATCH 3257/3886] mb/google/dedede/var/waddledee: Drop unused IPU
 devtree entry

waddledee dosn't have a MIPI camera, so drop the unused ipu devicetree
reference.

Change-Id: Ieca23f03d83fe1feeb026a923aec2c5fab6a9fe5
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91067
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
---
 src/mainboard/google/dedede/variants/waddledee/overridetree.cb | 1 -
 1 file changed, 1 deletion(-)

diff --git a/src/mainboard/google/dedede/variants/waddledee/overridetree.cb b/src/mainboard/google/dedede/variants/waddledee/overridetree.cb
index 38f94e0b73..7fc1a8bcaa 100644
--- a/src/mainboard/google/dedede/variants/waddledee/overridetree.cb
+++ b/src/mainboard/google/dedede/variants/waddledee/overridetree.cb
@@ -72,7 +72,6 @@ chip soc/intel/jasperlake
 				device generic 0 on end
 			end
 		end
-		device ref ipu on end
 		device ref south_xhci on
 			chip drivers/usb/acpi
 				device ref xhci_root_hub on

From 9f27b5d5fd6f32980ed9e39513fc97097aaf56d8 Mon Sep 17 00:00:00 2001
From: Subrata Banik <subratabanik@google.com>
Date: Wed, 4 Feb 2026 00:11:11 +0530
Subject: [PATCH 3258/3886] vc/google/chromeos: Allow mainboard-specific boot
 logo overrides

The current bmp_logo_filename implementation returns static filenames
based on Kconfig or ChromeOS branding levels. This lacks flexibility
for boards that need to select a logo dynamically at runtime (e.g.,
based on SKU ID or hardware straps).

Introduce a weak function mainboard_bmp_logo_filename() that can be
overridden by mainboard code. If the mainboard implementation returns
a non-NULL string, that filename is used; otherwise, the logic falls
back to the existing default behavior.

BUG=None
BRANCH=None
TEST=Verified that a mainboard can override the logo filename by
implementing mainboard_bmp_logo_filename. Verified default behavior
is preserved when no override is present.

Change-Id: Ia410dfb2a7a88779bb8eb4551605747bb326d353
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91082
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/include/bootsplash.h                |  2 ++
 src/vendorcode/google/chromeos/splash.c | 14 ++++++++++++++
 2 files changed, 16 insertions(+)

diff --git a/src/include/bootsplash.h b/src/include/bootsplash.h
index da51590345..fa13316955 100644
--- a/src/include/bootsplash.h
+++ b/src/include/bootsplash.h
@@ -147,6 +147,8 @@ void convert_bmp_to_blt(uintptr_t logo, size_t logo_size,
 	uintptr_t *blt, size_t *blt_size, uint32_t *pixel_height, uint32_t *pixel_width,
 	enum lb_fb_orientation orientation);
 
+/* Mainboard-specific override for logo filenames */
+const char *mainboard_bmp_logo_filename(void);
 /*
  * Allow platform-specific BMP logo overrides via HAVE_CUSTOM_BMP_LOGO config.
  * For example: Introduce configurable BMP logo for customization on platforms like ChromeOS
diff --git a/src/vendorcode/google/chromeos/splash.c b/src/vendorcode/google/chromeos/splash.c
index 5923513473..ff6d83d6dd 100644
--- a/src/vendorcode/google/chromeos/splash.c
+++ b/src/vendorcode/google/chromeos/splash.c
@@ -3,8 +3,22 @@
 #include <bootsplash.h>
 #include <vendorcode/google/chromeos/chromeos.h>
 
+/*
+ * Mainboard-specific override for logo filenames.
+ * Default implementation returns NULL to signal no override.
+ */
+__weak const char *mainboard_bmp_logo_filename(void)
+{
+	return NULL;
+}
+
 const char *bmp_logo_filename(void)
 {
+	/* Check if the mainboard wants to provide a logo */
+	const char *mainboard_logo = mainboard_bmp_logo_filename();
+	if (mainboard_logo)
+		return mainboard_logo;
+
 	/*
 	 * If the device has a custom boot splash footer logo (SPLASH_SCREEN_FOOTER Kconfig
 	 * is enabled and a logo path is provided), we only return the main OEM logo, which

From 0da04cf6754925d47ef98e402c9fdacd0a9babd7 Mon Sep 17 00:00:00 2001
From: Subrata Banik <subratabanik@google.com>
Date: Wed, 4 Feb 2026 19:11:36 +0000
Subject: [PATCH 3259/3886] mb/google/bluey: Consider vboot modes for PD
 negotiation

This change introduces a check to ensure Power Delivery (PD)
negotiation is enabled when the device is in a specific vboot state.

PD negotiation will now be enabled if:
1. It is explicitly required by the hardware sync logic.
2. The device is in Developer Mode.
3. The device is in Recovery Mode.
4. A recovery request is pending.

This ensures that charging and PD sync are prioritized during
critical recovery and development paths.

This patch ensures the factory process remains powered by enabling
early charging based on the specific vboot mode.

In normal user scenarios, early charging is bypassed to allow higher
-level software to manage power negotiation according to standard
policy.

BUG=b:481546101
TEST=Build and boot on google/quartz. Verified PD negotiation is
active in developer/recovery mode.

Change-Id: I44b2ebd4fe3eec78a6df235df6282264dd97341f
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91096
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jayvik Desai <jayvik@google.com>
Reviewed-by: Pranava Y N <pranavayn@google.com>
---
 src/mainboard/google/bluey/romstage.c | 18 +++++++++++++++++-
 1 file changed, 17 insertions(+), 1 deletion(-)

diff --git a/src/mainboard/google/bluey/romstage.c b/src/mainboard/google/bluey/romstage.c
index 33878069c6..a357f6d3d5 100644
--- a/src/mainboard/google/bluey/romstage.c
+++ b/src/mainboard/google/bluey/romstage.c
@@ -8,6 +8,7 @@
 #include <commonlib/coreboot_tables.h>
 #include <ec/google/chromeec/ec.h>
 #include <gpio.h>
+#include <security/vboot/vboot_common.h>
 #include <soc/aop_common.h>
 #include <soc/pmic.h>
 #include <soc/qclib_common.h>
@@ -74,12 +75,27 @@ static bool is_pd_sync_required(void)
 	return false;
 }
 
+/* Check if it is okay to enable PD sync. */
+static bool vboot_can_enable_pd_sync(void)
+{
+	if (!CONFIG(VBOOT))
+		return false;
+
+	/* Always enable if in developer or recovery mode */
+	if (vboot_developer_mode_enabled() || vboot_recovery_mode_enabled() ||
+			 vboot_check_recovery_request())
+		return true;
+
+	/* Otherwise disable */
+	return false;
+}
+
 int qclib_mainboard_override(struct qclib_cb_if_table *table)
 {
 	if (!CONFIG(EC_GOOGLE_CHROMEEC))
 		return 0;
 
-	if (is_pd_sync_required())
+	if (is_pd_sync_required() || vboot_can_enable_pd_sync())
 		table->global_attributes |= QCLIB_GA_ENABLE_PD_NEGOTIATION;
 	else
 		table->global_attributes &= ~QCLIB_GA_ENABLE_PD_NEGOTIATION;

From aee21f53cc9fc1571692e10f74d70264d986d431 Mon Sep 17 00:00:00 2001
From: Patrick Rudolph <patrick.rudolph@9elements.com>
Date: Sat, 24 Jan 2026 09:50:08 +0100
Subject: [PATCH 3260/3886] soc/amd/common/block/cpu/smm: Move microcode load

Load microcode from CBFS before setting up MTRRs using
x86_setup_mtrrs_with_detect(), since it will remove caching the
SPI flash MMIO area and thus slow down CBFS accesses.

TEST=Booted on AMD/crater with CBFS_VERIFICATION enabled. The system
     boots 6msec faster than before.

Change-Id: I3fafb98c1348daa549448707db88954316a12ff2
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90891
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
---
 src/soc/amd/common/block/cpu/smm/smm_relocate.c | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/src/soc/amd/common/block/cpu/smm/smm_relocate.c b/src/soc/amd/common/block/cpu/smm/smm_relocate.c
index e5b8d9d17a..4ca8911e2a 100644
--- a/src/soc/amd/common/block/cpu/smm/smm_relocate.c
+++ b/src/soc/amd/common/block/cpu/smm/smm_relocate.c
@@ -17,10 +17,11 @@
 /* AP MTRRs will be synced to the BSP in the SIPI vector so set them up before MP init. */
 static void pre_mp_init(void)
 {
-	x86_setup_mtrrs_with_detect();
-	x86_mtrr_check();
 	if (CONFIG(SOC_AMD_COMMON_BLOCK_UCODE))
 		amd_load_microcode_from_cbfs();
+
+	x86_setup_mtrrs_with_detect();
+	x86_mtrr_check();
 }
 
 static void get_smm_info(uintptr_t *perm_smbase, size_t *perm_smsize,

From 72ed0426d806911643a7b47a8ebd5498f961abcd Mon Sep 17 00:00:00 2001
From: Patrick Rudolph <patrick.rudolph@amd.com>
Date: Mon, 8 Sep 2025 15:50:00 +0200
Subject: [PATCH 3261/3886] soc/amd/*/acpi: Define PCI bridges in DSDT

Add all known PCI bridge devices to the DSDT. This allows to reference
the devices from DSDT, allowing to add more SoC DSDT code and it allows
mainboard developers to add board specific ACPI code for devices behind
PCIe bridges (like NVMe D3cold).

Currently this is only possible using SSDT generators. The SSDT ACPI
generation is also broken, since the mainboard SSDT is run before SoC
SSDT, causing the interpreter to complain about missing devices.

TEST=Still boots on amd/birman_plus. No ACPI errors seen in dmesg.

Signed-off-by: Patrick Rudolph <patrick.rudolph@amd.com>
Change-Id: I9d6f84b97fa943bb531d6b7b3f16c0422cd7901f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89456
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/soc/amd/cezanne/acpi/pci.asl         | 27 +++++++++++++++++++
 src/soc/amd/cezanne/acpi/soc.asl         |  2 ++
 src/soc/amd/common/acpi/pci_template.asl | 22 +++++++++++++++
 src/soc/amd/common/block/pci/pcie_gpp.c  | 14 +++-------
 src/soc/amd/glinda/acpi/pci.asl          | 34 ++++++++++++++++++++++++
 src/soc/amd/glinda/acpi/soc.asl          |  2 ++
 src/soc/amd/mendocino/acpi/pci.asl       | 21 +++++++++++++++
 src/soc/amd/mendocino/acpi/soc.asl       |  2 ++
 src/soc/amd/phoenix/acpi/pci.asl         | 31 +++++++++++++++++++++
 src/soc/amd/phoenix/acpi/soc.asl         |  2 ++
 src/soc/amd/picasso/acpi/pci.asl         | 22 +++++++++++++++
 src/soc/amd/picasso/acpi/soc.asl         |  1 +
 12 files changed, 170 insertions(+), 10 deletions(-)
 create mode 100644 src/soc/amd/cezanne/acpi/pci.asl
 create mode 100644 src/soc/amd/common/acpi/pci_template.asl
 create mode 100644 src/soc/amd/glinda/acpi/pci.asl
 create mode 100644 src/soc/amd/mendocino/acpi/pci.asl
 create mode 100644 src/soc/amd/phoenix/acpi/pci.asl
 create mode 100644 src/soc/amd/picasso/acpi/pci.asl

diff --git a/src/soc/amd/cezanne/acpi/pci.asl b/src/soc/amd/cezanne/acpi/pci.asl
new file mode 100644
index 0000000000..d892da4d86
--- /dev/null
+++ b/src/soc/amd/cezanne/acpi/pci.asl
@@ -0,0 +1,27 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <soc/amd/common/acpi/pci_template.asl>
+
+/*
+ * Keep name in sync with SSDT generator pcie_gpp_acpi_name()!
+ * Currently the name is hex representation of dev->path.pci.devfn.
+ */
+
+/* PCIe GPP */
+ACPI_PCI_DEV(GP09, 1, 1)
+ACPI_PCI_DEV(GP0A, 1, 2)
+ACPI_PCI_DEV(GP0B, 1, 3)
+
+/* PCIe GPP */
+ACPI_PCI_DEV(GP11, 2, 1)
+ACPI_PCI_DEV(GP12, 2, 2)
+ACPI_PCI_DEV(GP13, 2, 3)
+ACPI_PCI_DEV(GP14, 2, 4)
+ACPI_PCI_DEV(GP15, 2, 5)
+ACPI_PCI_DEV(GP16, 2, 6)
+ACPI_PCI_DEV(GP17, 2, 7)
+
+/* Internal GPP bridges */
+ACPI_PCI_DEV(GP41, 8, 1)
+ACPI_PCI_DEV(GP42, 8, 2)
+ACPI_PCI_DEV(GP43, 8, 3)
diff --git a/src/soc/amd/cezanne/acpi/soc.asl b/src/soc/amd/cezanne/acpi/soc.asl
index f89aaf4f1f..2d9d1dfb18 100644
--- a/src/soc/amd/cezanne/acpi/soc.asl
+++ b/src/soc/amd/cezanne/acpi/soc.asl
@@ -21,6 +21,8 @@ Scope(\_SB) {
 
 	Scope(PCI0) {
 		#include <soc/amd/common/acpi/lpc.asl>
+
+		#include "pci.asl"
 	} /* End PCI0 scope */
 } /* End \_SB scope */
 
diff --git a/src/soc/amd/common/acpi/pci_template.asl b/src/soc/amd/common/acpi/pci_template.asl
new file mode 100644
index 0000000000..dd9e4b149a
--- /dev/null
+++ b/src/soc/amd/common/acpi/pci_template.asl
@@ -0,0 +1,22 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+/*
+ * Template for fixed PCI devices on the SoC. SSDT will emit STAT=1 when enabled
+ * in hardware and devicetree.cb. Allows to write DSDT code for such devices or
+ * it's children. Possible use cases:
+ * - PowerResources for devices behind PCIe bridges (NVVMe D3cold)
+ * - _DSM for ACP
+ * - BOCO and BACO for GPU
+ */
+#ifdef ACPI_PCI_DEV
+ #undef ACPI_PCI_DEV
+#endif
+#define ACPI_PCI_DEV(name, dev, fun) \
+	Device(name) {					\
+		Name(_ADR, (dev << 16) + fun)		\
+		Name (STAT, 0x0)			\
+		Method (_STA, 0, NotSerialized)		\
+		{					\
+			Return (STAT)			\
+		}					\
+	}
diff --git a/src/soc/amd/common/block/pci/pcie_gpp.c b/src/soc/amd/common/block/pci/pcie_gpp.c
index 0f983d04be..03bd45f7ba 100644
--- a/src/soc/amd/common/block/pci/pcie_gpp.c
+++ b/src/soc/amd/common/block/pci/pcie_gpp.c
@@ -28,22 +28,16 @@ static const char *pcie_gpp_acpi_name(const struct device *dev)
 
 static void acpi_device_write_gpp_pci_dev(const struct device *dev)
 {
-	const char *scope = acpi_device_scope(dev);
-	const char *name = acpi_device_name(dev);
+	const char *path = acpi_device_path(dev);
 
 	assert(dev->path.type == DEVICE_PATH_PCI);
-	assert(name);
-	assert(scope);
+	assert(path);
 
-	acpigen_write_scope(scope);
-	acpigen_write_device(name);
-
-	acpigen_write_ADR_pci_device(dev);
-	acpigen_write_STA(acpi_device_status(dev));
+	acpigen_write_scope(path);
 
+	acpigen_write_store_int_to_namestr(acpi_device_status(dev), "STAT");
 	acpigen_write_pci_GNB_PRT(dev);
 
-	acpigen_pop_len(); /* Device */
 	acpigen_pop_len(); /* Scope */
 }
 
diff --git a/src/soc/amd/glinda/acpi/pci.asl b/src/soc/amd/glinda/acpi/pci.asl
new file mode 100644
index 0000000000..0fabe961ad
--- /dev/null
+++ b/src/soc/amd/glinda/acpi/pci.asl
@@ -0,0 +1,34 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <soc/amd/common/acpi/pci_template.asl>
+
+/*
+ * Keep name in sync with SSDT generator pcie_gpp_acpi_name()!
+ * Currently the name is hex representation of dev->path.pci.devfn.
+ */
+
+/* USB4.0 bridge */
+ACPI_PCI_DEV(GP09, 1, 1)
+ACPI_PCI_DEV(GP0A, 1, 2)
+ACPI_PCI_DEV(GP0B, 1, 3)
+
+/* PCIe GPP */
+ACPI_PCI_DEV(GP11, 2, 1)
+ACPI_PCI_DEV(GP12, 2, 2)
+ACPI_PCI_DEV(GP13, 2, 3)
+ACPI_PCI_DEV(GP14, 2, 4)
+ACPI_PCI_DEV(GP15, 2, 5)
+ACPI_PCI_DEV(GP16, 2, 6)
+
+/* PCIe GPP */
+ACPI_PCI_DEV(GP19, 3, 1)
+ACPI_PCI_DEV(GP1A, 3, 2)
+ACPI_PCI_DEV(GP1B, 3, 3)
+ACPI_PCI_DEV(GP1C, 3, 4)
+ACPI_PCI_DEV(GP1D, 3, 5)
+ACPI_PCI_DEV(GP1E, 3, 6)
+
+/* Internal GPP bridges */
+ACPI_PCI_DEV(GP41, 8, 1)
+ACPI_PCI_DEV(GP42, 8, 2)
+ACPI_PCI_DEV(GP43, 8, 3)
diff --git a/src/soc/amd/glinda/acpi/soc.asl b/src/soc/amd/glinda/acpi/soc.asl
index 964cad94b5..1daf153a4a 100644
--- a/src/soc/amd/glinda/acpi/soc.asl
+++ b/src/soc/amd/glinda/acpi/soc.asl
@@ -23,6 +23,8 @@ Scope(\_SB) {
 
 	Scope(PCI0) {
 		#include <soc/amd/common/acpi/lpc.asl>
+
+		#include "pci.asl"
 	} /* End PCI0 scope */
 } /* End \_SB scope */
 
diff --git a/src/soc/amd/mendocino/acpi/pci.asl b/src/soc/amd/mendocino/acpi/pci.asl
new file mode 100644
index 0000000000..e1a239d3a2
--- /dev/null
+++ b/src/soc/amd/mendocino/acpi/pci.asl
@@ -0,0 +1,21 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <soc/amd/common/acpi/pci_template.asl>
+
+/*
+ * Keep name in sync with SSDT generator pcie_gpp_acpi_name()!
+ * Currently the name is hex representation of dev->path.pci.devfn.
+ */
+
+/* PCIe GPP */
+ACPI_PCI_DEV(GP11, 2, 1)
+ACPI_PCI_DEV(GP12, 2, 2)
+ACPI_PCI_DEV(GP13, 2, 3)
+ACPI_PCI_DEV(GP14, 2, 4)
+ACPI_PCI_DEV(GP15, 2, 5)
+ACPI_PCI_DEV(GP16, 2, 6)
+
+/* Internal GPP bridges */
+ACPI_PCI_DEV(GP41, 8, 1)
+ACPI_PCI_DEV(GP42, 8, 2)
+ACPI_PCI_DEV(GP43, 8, 3)
diff --git a/src/soc/amd/mendocino/acpi/soc.asl b/src/soc/amd/mendocino/acpi/soc.asl
index 5a73f3bd65..417370fe82 100644
--- a/src/soc/amd/mendocino/acpi/soc.asl
+++ b/src/soc/amd/mendocino/acpi/soc.asl
@@ -23,6 +23,8 @@ Scope(\_SB) {
 
 	Scope(PCI0) {
 		#include <soc/amd/common/acpi/lpc.asl>
+
+		#include "pci.asl"
 	} /* End PCI0 scope */
 } /* End \_SB scope */
 
diff --git a/src/soc/amd/phoenix/acpi/pci.asl b/src/soc/amd/phoenix/acpi/pci.asl
new file mode 100644
index 0000000000..c0a522246b
--- /dev/null
+++ b/src/soc/amd/phoenix/acpi/pci.asl
@@ -0,0 +1,31 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <soc/amd/common/acpi/pci_template.asl>
+
+/*
+ * Keep name in sync with SSDT generator pcie_gpp_acpi_name()!
+ * Currently the name is hex representation of dev->path.pci.devfn.
+ */
+
+/* PCIe GPP */
+ACPI_PCI_DEV(GP09, 1, 1)
+ACPI_PCI_DEV(GP0A, 1, 2)
+ACPI_PCI_DEV(GP0B, 1, 3)
+ACPI_PCI_DEV(GP0C, 1, 4)
+
+/* PCIe GPP */
+ACPI_PCI_DEV(GP11, 2, 1)
+ACPI_PCI_DEV(GP12, 2, 2)
+ACPI_PCI_DEV(GP13, 2, 3)
+ACPI_PCI_DEV(GP14, 2, 4)
+ACPI_PCI_DEV(GP15, 2, 5)
+ACPI_PCI_DEV(GP16, 2, 6)
+
+/* USB4.0 bridges */
+ACPI_PCI_DEV(GP19, 3, 1)
+ACPI_PCI_DEV(GP21, 4, 1)
+
+/* Internal GPP bridges */
+ACPI_PCI_DEV(GP41, 8, 1)
+ACPI_PCI_DEV(GP42, 8, 2)
+ACPI_PCI_DEV(GP43, 8, 3)
diff --git a/src/soc/amd/phoenix/acpi/soc.asl b/src/soc/amd/phoenix/acpi/soc.asl
index ee2e9c886b..997c819bd6 100644
--- a/src/soc/amd/phoenix/acpi/soc.asl
+++ b/src/soc/amd/phoenix/acpi/soc.asl
@@ -23,6 +23,8 @@ Scope(\_SB) {
 
 	Scope(PCI0) {
 		#include <soc/amd/common/acpi/lpc.asl>
+
+		#include "pci.asl"
 	} /* End PCI0 scope */
 } /* End \_SB scope */
 
diff --git a/src/soc/amd/picasso/acpi/pci.asl b/src/soc/amd/picasso/acpi/pci.asl
new file mode 100644
index 0000000000..539ef381be
--- /dev/null
+++ b/src/soc/amd/picasso/acpi/pci.asl
@@ -0,0 +1,22 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <soc/amd/common/acpi/pci_template.asl>
+
+/*
+ * Keep name in sync with SSDT generator pcie_gpp_acpi_name()!
+ * Currently the name is hex representation of dev->path.pci.devfn.
+ */
+
+/* PCIe GPP */
+ACPI_PCI_DEV(GP09, 1, 1)
+ACPI_PCI_DEV(GP0A, 1, 2)
+ACPI_PCI_DEV(GP0B, 1, 3)
+ACPI_PCI_DEV(GP0C, 1, 4)
+ACPI_PCI_DEV(GP0D, 1, 5)
+ACPI_PCI_DEV(GP0E, 1, 6)
+ACPI_PCI_DEV(GP0F, 1, 7)
+
+/* Internal GPP bridges */
+ACPI_PCI_DEV(GP41, 8, 1)
+ACPI_PCI_DEV(GP42, 8, 2)
+ACPI_PCI_DEV(GP43, 8, 3)
diff --git a/src/soc/amd/picasso/acpi/soc.asl b/src/soc/amd/picasso/acpi/soc.asl
index 7c13f0863e..deedd5dd5a 100644
--- a/src/soc/amd/picasso/acpi/soc.asl
+++ b/src/soc/amd/picasso/acpi/soc.asl
@@ -22,6 +22,7 @@ Scope(\_SB) { /* Start \_SB scope */
 	Scope(PCI0) {
 		/* Describe the AMD Northbridge */
 		#include "northbridge.asl"
+		#include "pci.asl"
 
 		/* Describe the AMD Fusion Controller Hub */
 		#include <soc/amd/common/acpi/lpc.asl>

From 5d46eecbc8a471cb4d8f32a00a152a8360db7475 Mon Sep 17 00:00:00 2001
From: Bora Guvendik <bora.guvendik@intel.com>
Date: Thu, 23 Oct 2025 11:06:18 -0700
Subject: [PATCH 3262/3886] mb/google/fatcat: Update frequency for SaGv work
 point 4
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Update SaGv work point 4 frequency value as per recommendation
from power and performance team.

BUG=b:461762075
TEST=Boot to OS on fatcat board, verified performance improvements
and frequency setting.

Change-Id: Ic4dfe6bf5a441b491a27e952010a43d4f7a68af5
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89693
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Pranava Y N <pranavayn@google.com>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
---
 .../google/fatcat/variants/baseboard/fatcat/devicetree.cb     | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/src/mainboard/google/fatcat/variants/baseboard/fatcat/devicetree.cb b/src/mainboard/google/fatcat/variants/baseboard/fatcat/devicetree.cb
index 6ccd7c2e18..0f74bc79b8 100644
--- a/src/mainboard/google/fatcat/variants/baseboard/fatcat/devicetree.cb
+++ b/src/mainboard/google/fatcat/variants/baseboard/fatcat/devicetree.cb
@@ -48,9 +48,11 @@ chip soc/intel/pantherlake
 	register "sagv_freq_mhz[2]" = "6400"
 	register "sagv_gear[2]" = "GEAR_4"
 
-	register "sagv_freq_mhz[3]" = "6800"
+	register "sagv_freq_mhz[3]" = "7467"
 	register "sagv_gear[3]" = "GEAR_4"
 
+	register "max_dram_speed_mts" = "7467"
+
 	# Enable s0ix
 	register "s0ix_enable" = "true"
 

From 708b2b7779d32d807c2d39596a77a0a869c4ac99 Mon Sep 17 00:00:00 2001
From: Sowmya Aralguppe <sowmya.aralguppe@intel.com>
Date: Fri, 30 Jan 2026 13:46:36 +0530
Subject: [PATCH 3263/3886] soc/intel/pantherlake: Fix fast_vmode_i_trip array
 indexing
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Fix incorrect indexing for fast_vmode_i_trip arrays. This patch ensures
consistent SKU-based indexing across the VR configuration.

BUG=b:481561587
TEST=Verify VR parameters are correctly applied in FSP debug log

Change-Id: I532d9fc51d7d1342f2f0464f7aeacffe0b603267
Signed-off-by: Sowmya Aralguppe <sowmya.aralguppe@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91002
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Reviewed-by: Pranava Y N <pranavayn@google.com>
---
 src/soc/intel/pantherlake/chip.h                | 8 ++++----
 src/soc/intel/pantherlake/romstage/fsp_params.c | 2 +-
 2 files changed, 5 insertions(+), 5 deletions(-)

diff --git a/src/soc/intel/pantherlake/chip.h b/src/soc/intel/pantherlake/chip.h
index 15a1501e18..1d75b0ae43 100644
--- a/src/soc/intel/pantherlake/chip.h
+++ b/src/soc/intel/pantherlake/chip.h
@@ -378,18 +378,18 @@ struct soc_intel_pantherlake_config {
 	 * Fast Vmode I_TRIP Thresholds for VR Domains
 	 *
 	 * This two-dimensional array represents the Fast Vmode I_TRIP thresholds
-	 * for various Voltage Regulator (VR) domains across different power limit
-	 * configurations in Panther Lake SoCs.
+	 * for various Voltage Regulator (VR) domains across different SKUs
+	 * in Panther Lake SoCs.
 	 *
 	 * The Fast Vmode I_TRIP threshold is used to override the default current
 	 * threshold settings, ensuring optimal power management by adapting to
-	 * specific VR domain requirements under different power limit scenarios.
+	 * specific VR domain requirements for each SKU's hardware capabilities.
 	 *
 	 * 0-255A in 1/4 A units. Example: 400 = 100A
 	 * This setting overrides the default value set by FSPs when Fast VMode
 	 * is enabled.
 	 */
-	uint16_t fast_vmode_i_trip[PTL_POWER_LIMITS_COUNT][NUM_VR_DOMAINS];
+	uint16_t fast_vmode_i_trip[MAX_PTL_SKUS][NUM_VR_DOMAINS];
 
 	/*
 	 * Power state current threshold 1.
diff --git a/src/soc/intel/pantherlake/romstage/fsp_params.c b/src/soc/intel/pantherlake/romstage/fsp_params.c
index d6f628b36a..bef87158d7 100644
--- a/src/soc/intel/pantherlake/romstage/fsp_params.c
+++ b/src/soc/intel/pantherlake/romstage/fsp_params.c
@@ -348,7 +348,7 @@ static void fill_fspm_vr_config_params(FSP_M_CONFIG *m_cfg,
 		m_cfg->CepEnable[i] = config->cep_enable[i];
 		if (config->enable_fast_vmode[i]) {
 			m_cfg->EnableFastVmode[i] = config->enable_fast_vmode[i];
-			m_cfg->IccLimit[i] = config->fast_vmode_i_trip[map->limits][i];
+			m_cfg->IccLimit[i] = config->fast_vmode_i_trip[map->sku][i];
 		}
 	}
 

From cf147e930a4fc7e40b4ae46955305094f416a9d6 Mon Sep 17 00:00:00 2001
From: Sowmya Aralguppe <sowmya.aralguppe@intel.com>
Date: Mon, 2 Feb 2026 19:47:42 +0530
Subject: [PATCH 3264/3886] mb/google/fatcat/ruby: Fix fast_vmode_i_trip
 indexing

Update fast_vmode_i_trip array references to use PTL_SKU_* constants
instead of PTL_CORE_* constants.This change maintains consistency with
the corrected SKU-based indexing scheme implemented across the VR
configuration system and prevents potential runtime errors.

TEST=Build ruby variant, verify correct VR parameter application

Change-Id: I957ec2c81f670108edfb5eb4d7739eb48f111fb4
Signed-off-by: Sowmya Aralguppe <sowmya.aralguppe@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91053
Reviewed-by: Pranava Y N <pranavayn@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/google/fatcat/variants/ruby/overridetree.cb | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/mainboard/google/fatcat/variants/ruby/overridetree.cb b/src/mainboard/google/fatcat/variants/ruby/overridetree.cb
index f2a4e75198..494c8c5cf7 100644
--- a/src/mainboard/google/fatcat/variants/ruby/overridetree.cb
+++ b/src/mainboard/google/fatcat/variants/ruby/overridetree.cb
@@ -62,12 +62,12 @@ chip soc/intel/pantherlake
 		.tdp_pl4 = 150,
 	}"
 
-	register "fast_vmode_i_trip[PTL_CORE_1]" = "{
+	register "fast_vmode_i_trip[PTL_SKU_1]" = "{
 		[VR_DOMAIN_IA] = 74 * 4,
 		[VR_DOMAIN_GT] = 38 * 4,
 		[VR_DOMAIN_SA] = 38 * 4
 	}"
-	register "fast_vmode_i_trip[PTL_CORE_2]" = "{
+	register "fast_vmode_i_trip[PTL_SKU_5]" = "{
 		[VR_DOMAIN_IA] = 74 * 4,
 		[VR_DOMAIN_GT] = 38 * 4,
 		[VR_DOMAIN_SA] = 38 * 4

From 438aa853f8c3221d419237fd00326796e55850c6 Mon Sep 17 00:00:00 2001
From: Shon Wang <shon.wang@quanta.corp-partner.google.com>
Date: Mon, 2 Feb 2026 15:16:10 +0800
Subject: [PATCH 3265/3886] spd/lp5x: Generate initial SPD for BWMYAX32P8A-32G

Generate initial SPD for BIWIN BWMYAX32P8A-32G

BUG=b:438402880
BRANCH=firmware-nissa-15217.B
TEST=util/spd_tools/bin/spd_gen spd/lp5/memory_parts.json lp5

Change-Id: Ia1ec6d9395ed930f47dcfe23d671b9da977eab6d
Signed-off-by: Shon Wang <shon.wang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91051
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
---
 spd/lp5/memory_parts.json                      | 11 +++++++++++
 spd/lp5/set-0/parts_spd_manifest.generated.txt |  1 +
 spd/lp5/set-1/parts_spd_manifest.generated.txt |  1 +
 3 files changed, 13 insertions(+)

diff --git a/spd/lp5/memory_parts.json b/spd/lp5/memory_parts.json
index 40a8f65ec2..033d001b70 100644
--- a/spd/lp5/memory_parts.json
+++ b/spd/lp5/memory_parts.json
@@ -434,6 +434,17 @@
             "speedMbps": 8533,
             "lp5x": true
         }
+    },
+    {
+        "name": "BWMYAX32P8A-32G",
+        "attribs": {
+            "densityPerDieGb": 16,
+            "diesPerPackage": 2,
+            "bitWidthPerChannel": 16,
+            "ranksPerChannel": 1,
+            "speedMbps": 7500,
+            "lp5x": true
+        }
     }
     ]
 }
diff --git a/spd/lp5/set-0/parts_spd_manifest.generated.txt b/spd/lp5/set-0/parts_spd_manifest.generated.txt
index 3976379d4a..0401c008e0 100644
--- a/spd/lp5/set-0/parts_spd_manifest.generated.txt
+++ b/spd/lp5/set-0/parts_spd_manifest.generated.txt
@@ -42,3 +42,4 @@ K3KL8L80EM-MGCV,spd-11.hex
 MT62F1G32D2DS-031RF WT:C,spd-3.hex
 MT62F2G32D4DS-031RF WT:C,spd-6.hex
 RS1G32LO5D2FDB-23BT,spd-11.hex
+BWMYAX32P8A-32G,spd-7.hex
diff --git a/spd/lp5/set-1/parts_spd_manifest.generated.txt b/spd/lp5/set-1/parts_spd_manifest.generated.txt
index 3976379d4a..0401c008e0 100644
--- a/spd/lp5/set-1/parts_spd_manifest.generated.txt
+++ b/spd/lp5/set-1/parts_spd_manifest.generated.txt
@@ -42,3 +42,4 @@ K3KL8L80EM-MGCV,spd-11.hex
 MT62F1G32D2DS-031RF WT:C,spd-3.hex
 MT62F2G32D4DS-031RF WT:C,spd-6.hex
 RS1G32LO5D2FDB-23BT,spd-11.hex
+BWMYAX32P8A-32G,spd-7.hex

From 16ccfc0e80179ac763e24d1b7b688546de272ae3 Mon Sep 17 00:00:00 2001
From: Shon Wang <shon.wang@quanta.corp-partner.google.com>
Date: Mon, 2 Feb 2026 15:20:05 +0800
Subject: [PATCH 3266/3886] mb/google/nissa/var/quandiso: Generate RAM ID for
 BWMYAX32P8A-32G

Generate RAM ID for BWMYAX32P8A-32G

DRAM Part Name                 ID to assign
BWMYAX32P8A-32G                3 (0011)

BUG=b:438402880
BRANCH=firmware-nissa-15217.B
TEST=emerge-nissa coreboot

Change-Id: I4b26b3c74c2985d9b663bc8eb72824d1ca82850b
Signed-off-by: Shon Wang <shon.wang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91052
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Kyle Lin <kylelinck@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
---
 src/mainboard/google/brya/variants/quandiso/memory/Makefile.mk  | 2 +-
 .../google/brya/variants/quandiso/memory/dram_id.generated.txt  | 1 +
 .../google/brya/variants/quandiso/memory/mem_parts_used.txt     | 1 +
 3 files changed, 3 insertions(+), 1 deletion(-)

diff --git a/src/mainboard/google/brya/variants/quandiso/memory/Makefile.mk b/src/mainboard/google/brya/variants/quandiso/memory/Makefile.mk
index 166769396f..6c970ad89e 100644
--- a/src/mainboard/google/brya/variants/quandiso/memory/Makefile.mk
+++ b/src/mainboard/google/brya/variants/quandiso/memory/Makefile.mk
@@ -7,7 +7,7 @@ SPD_SOURCES =
 SPD_SOURCES += spd/lp5/set-0/spd-1.hex      # ID = 0(0b0000)  Parts = MT62F512M32D2DR-031 WT:B, H9JCNNNBK3MLYR-N6E
 SPD_SOURCES += spd/lp5/set-0/spd-2.hex      # ID = 1(0b0001)  Parts = MT62F1G32D4DR-031 WT:B
 SPD_SOURCES += spd/lp5/set-0/spd-3.hex      # ID = 2(0b0010)  Parts = H58G56AK6BX069, K3LKBKB0BM-MGCP
-SPD_SOURCES += spd/lp5/set-0/spd-7.hex      # ID = 3(0b0011)  Parts = H58G56BK7BX068, MT62F1G32D2DS-026 WT:B, K3KL8L80CM-MGCT
+SPD_SOURCES += spd/lp5/set-0/spd-7.hex      # ID = 3(0b0011)  Parts = H58G56BK7BX068, MT62F1G32D2DS-026 WT:B, K3KL8L80CM-MGCT, BWMYAX32P8A-32G
 SPD_SOURCES += spd/lp5/set-0/spd-8.hex      # ID = 4(0b0100)  Parts = H58G66BK7BX067, MT62F2G32D4DS-026 WT:B, K3KL9L90CM-MGCT
 SPD_SOURCES += spd/lp5/set-0/spd-6.hex      # ID = 5(0b0101)  Parts = H58G66AK6BX070
 SPD_SOURCES += spd/lp5/set-0/spd-9.hex      # ID = 6(0b0110)  Parts = K3KL6L60GM-MGCT
diff --git a/src/mainboard/google/brya/variants/quandiso/memory/dram_id.generated.txt b/src/mainboard/google/brya/variants/quandiso/memory/dram_id.generated.txt
index 362ef9ea21..275125f0d2 100644
--- a/src/mainboard/google/brya/variants/quandiso/memory/dram_id.generated.txt
+++ b/src/mainboard/google/brya/variants/quandiso/memory/dram_id.generated.txt
@@ -21,3 +21,4 @@ MT62F1G32D2DS-023 WT:C         7 (0111)
 H58G56CK8BX146                 7 (0111)
 K3KL8L80EM-MGCU                7 (0111)
 MT62F512M32D1DS-023 WT:E       7 (0111)
+BWMYAX32P8A-32G                3 (0011)
diff --git a/src/mainboard/google/brya/variants/quandiso/memory/mem_parts_used.txt b/src/mainboard/google/brya/variants/quandiso/memory/mem_parts_used.txt
index 76c6d3f316..1570fe8962 100644
--- a/src/mainboard/google/brya/variants/quandiso/memory/mem_parts_used.txt
+++ b/src/mainboard/google/brya/variants/quandiso/memory/mem_parts_used.txt
@@ -26,3 +26,4 @@ MT62F1G32D2DS-023 WT:C
 H58G56CK8BX146
 K3KL8L80EM-MGCU
 MT62F512M32D1DS-023 WT:E
+BWMYAX32P8A-32G

From a6e77b1e646e9f63dd339a977a3384194ba8862c Mon Sep 17 00:00:00 2001
From: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Date: Tue, 3 Feb 2026 14:52:09 +0800
Subject: [PATCH 3267/3886] mb/google/fatcat/kinmen: Remove RTD3 config for SSD

The Kinmen hardware design does not have a power load switch for
the SSD. Without it, the platform cannot cut off the main power rail
to the device to enter D3cold.
Therefore, remove the RTD3 chip driver and its associated GPIO
configurations (enable/reset) in the overridetree to align with the
hardware capability. The system will support D3hot instead of D3cold.

BUG=460038237
TEST=Build and boot to OS on Kinmen, verify SSD still functions
    correctly and power state transitions align with HW design.

Change-Id: I5e20c247bd45427f817e7afd8355a71c7a9c161c
Signed-off-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91085
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Pranava Y N <pranavayn@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
---
 .../google/fatcat/variants/kinmen/overridetree.cb          | 7 -------
 1 file changed, 7 deletions(-)

diff --git a/src/mainboard/google/fatcat/variants/kinmen/overridetree.cb b/src/mainboard/google/fatcat/variants/kinmen/overridetree.cb
index 36a7c30d09..bee842d0b4 100644
--- a/src/mainboard/google/fatcat/variants/kinmen/overridetree.cb
+++ b/src/mainboard/google/fatcat/variants/kinmen/overridetree.cb
@@ -374,13 +374,6 @@ chip soc/intel/pantherlake
 			.clk_req = 1,
 			.flags = PCIE_RP_CLK_REQ_DETECT | PCIE_RP_LTR | PCIE_RP_AER,
 			}"
-			chip soc/intel/common/block/pcie/rtd3
-				register "is_storage" = "true"
-				register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B16)"
-				register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_E03)"
-				register "srcclk_pin" = "1"
-				device generic 0 on end
-			end
 		end # Gen5 M.2 SSD
 		device ref cnvi_wifi on
 			chip drivers/wifi/generic

From bd634f386089fd281398fe7c22a00ff14ca5968c Mon Sep 17 00:00:00 2001
From: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Date: Tue, 3 Feb 2026 14:59:26 +0800
Subject: [PATCH 3268/3886] mb/google/ocelot/matsu: Remove RTD3 config for SSD

The Matsu hardware design does not have a power load switch for
the SSD. Without it, the platform cannot cut off the main power rail
to the device to enter D3cold.
Therefore, remove the RTD3 chip driver and its associated GPIO
configurations (enable/reset) in the overridetree to align with the
hardware capability. The system will support D3hot instead of D3cold.

BUG=443612246
TEST=Build and boot to OS on Matsu, verify SSD still functions
    correctly and power state transitions align with HW design.

Change-Id: I84db81c17afffafbdb6c7abcc752009c824bc2ed
Signed-off-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91086
Reviewed-by: Pranava Y N <pranavayn@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
---
 src/mainboard/google/ocelot/variants/matsu/overridetree.cb | 7 -------
 1 file changed, 7 deletions(-)

diff --git a/src/mainboard/google/ocelot/variants/matsu/overridetree.cb b/src/mainboard/google/ocelot/variants/matsu/overridetree.cb
index 59d6226735..8da38fe1d8 100644
--- a/src/mainboard/google/ocelot/variants/matsu/overridetree.cb
+++ b/src/mainboard/google/ocelot/variants/matsu/overridetree.cb
@@ -337,13 +337,6 @@ chip soc/intel/pantherlake
 			.clk_req = 3,
 			.flags = PCIE_RP_CLK_REQ_DETECT | PCIE_RP_LTR | PCIE_RP_AER,
 			}"
-			chip soc/intel/common/block/pcie/rtd3
-				register "is_storage" = "true"
-				register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_H18)"
-				register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A08)"
-				register "srcclk_pin" = "3"
-				device generic 0 on end
-			end
 		end # Gen4 M.2 SSD
 
 		device ref cnvi_wifi on

From 1777f962fd8efc2f6afc6e81fd52db7dbbba56aa Mon Sep 17 00:00:00 2001
From: "lai.kaiden" <lai.kaiden@inventec.corp-partner.google.com>
Date: Tue, 3 Feb 2026 14:03:34 +0800
Subject: [PATCH 3269/3886] mb/google/ocelot/var/ocicat: Remove RTD3 config for
 SSD

The ocicat hardware design does not have a power load switch for the SSD , so remove the RTD3 chip driver and its associated GPIO configurations (enable/reset) in the overridetree.

BUG=b:481143310
TEST=Build and boot to OS,verify SSD still functions correctly and power state transitions align with HW design.

Change-Id: Iace755963109caa07db036cb7b2fce88eb246d2c
Signed-off-by: lai.kaiden <lai.kaiden@inventec.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91070
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Pranava Y N <pranavayn@google.com>
---
 .../google/ocelot/variants/ocicat/overridetree.cb          | 7 -------
 1 file changed, 7 deletions(-)

diff --git a/src/mainboard/google/ocelot/variants/ocicat/overridetree.cb b/src/mainboard/google/ocelot/variants/ocicat/overridetree.cb
index 61a9c72b96..8ed23a7148 100644
--- a/src/mainboard/google/ocelot/variants/ocicat/overridetree.cb
+++ b/src/mainboard/google/ocelot/variants/ocicat/overridetree.cb
@@ -365,13 +365,6 @@ chip soc/intel/pantherlake
 			.clk_req = 3,
 			.flags = PCIE_RP_CLK_REQ_DETECT | PCIE_RP_LTR | PCIE_RP_AER,
 			}"
-			chip soc/intel/common/block/pcie/rtd3
-				register "is_storage" = "true"
-				register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_H18)"
-				register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A08)"
-				register "srcclk_pin" = "3"
-				device generic 0 on end
-			end
 		end # Gen4 M.2 SSD
 
 		device ref pcie_rp5 on

From 8954bd72a9bafdb9c9870d5ba2f085794eb28bb6 Mon Sep 17 00:00:00 2001
From: Alicja Michalska <alicja.michalska@9elements.com>
Date: Wed, 6 Aug 2025 05:04:14 +0200
Subject: [PATCH 3270/3886] mainboard/intel: Add PantherLake CRB for Edge

This patch adds initial support for Intel's Customer Reference Board for
Edge Platforms.

Tested working:
- Serial output (RS232/LPSS) on Micro-USB port
- Built-in DisplayPort (DDI-A, NOT AIC)
- Built-in GbE NIC
- M.2 Gen4 NVME
- M.2 Gen4 WiFi
- PCIe Gen4 x1
- PCIe Gen5 x4
- USB ports
- Booting into Linux from USB/NVME

Not implemented yet (lack of hardware, waiting for upstreaming):
- Audio
- Thunderbolt
- IPU Cameras

Unresolved issues, untested:
- Automatic fan control (Unobtainable IT8659E datasheet).
- System suspend (Unobtainable IT8659E datasheet).
- PCIe Gen5 x8 (Likely an issue with early silicon sample).

For more information please refer to #854345 (Intel CNDA).

Change-Id: I1d4e4dd4d18f49bd72405275fc96b7ca0630f612
Signed-off-by: Alicja Michalska <alicja.michalska@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90939
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
---
 src/mainboard/intel/pantherlake_crb/Kconfig   |  58 ++++
 .../intel/pantherlake_crb/Kconfig.name        |   4 +
 .../intel/pantherlake_crb/Makefile.mk         |   5 +
 src/mainboard/intel/pantherlake_crb/board.fmd |  21 ++
 .../intel/pantherlake_crb/board_info.txt      |   6 +
 .../intel/pantherlake_crb/bootblock.c         |  24 ++
 src/mainboard/intel/pantherlake_crb/data.vbt  | Bin 0 -> 7680 bytes
 .../intel/pantherlake_crb/devicetree.cb       | 262 ++++++++++++++++++
 src/mainboard/intel/pantherlake_crb/dsdt.asl  |  29 ++
 src/mainboard/intel/pantherlake_crb/gpio.h    | 230 +++++++++++++++
 .../intel/pantherlake_crb/hda_verb.c          |  12 +
 .../intel/pantherlake_crb/ramstage.c          |  20 ++
 .../intel/pantherlake_crb/romstage.c          |  64 +++++
 13 files changed, 735 insertions(+)
 create mode 100644 src/mainboard/intel/pantherlake_crb/Kconfig
 create mode 100644 src/mainboard/intel/pantherlake_crb/Kconfig.name
 create mode 100644 src/mainboard/intel/pantherlake_crb/Makefile.mk
 create mode 100644 src/mainboard/intel/pantherlake_crb/board.fmd
 create mode 100644 src/mainboard/intel/pantherlake_crb/board_info.txt
 create mode 100644 src/mainboard/intel/pantherlake_crb/bootblock.c
 create mode 100644 src/mainboard/intel/pantherlake_crb/data.vbt
 create mode 100644 src/mainboard/intel/pantherlake_crb/devicetree.cb
 create mode 100644 src/mainboard/intel/pantherlake_crb/dsdt.asl
 create mode 100644 src/mainboard/intel/pantherlake_crb/gpio.h
 create mode 100644 src/mainboard/intel/pantherlake_crb/hda_verb.c
 create mode 100644 src/mainboard/intel/pantherlake_crb/ramstage.c
 create mode 100644 src/mainboard/intel/pantherlake_crb/romstage.c

diff --git a/src/mainboard/intel/pantherlake_crb/Kconfig b/src/mainboard/intel/pantherlake_crb/Kconfig
new file mode 100644
index 0000000000..bd1506ad36
--- /dev/null
+++ b/src/mainboard/intel/pantherlake_crb/Kconfig
@@ -0,0 +1,58 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
+if BOARD_INTEL_PANTHERLAKE_CRB
+
+config BOARD_SPECIFIC_OPTIONS
+	def_bool y
+	select BOARD_ROMSIZE_KB_32768
+	select CPU_INTEL_SOCKET_OTHER
+	select CRB_TPM
+	select DRIVERS_INTEL_DPTF
+	select DRIVERS_INTEL_MIPI_CAMERA
+	select DRIVERS_INTEL_MIPI_SUPPORTS_PRE_PRODUCTION_SOC if SOC_INTEL_PANTHERLAKE_PRE_PRODUCTION_SILICON
+	select DRIVERS_INTEL_PMC
+	select DRIVERS_INTEL_USB4_RETIMER
+	select DRIVERS_INTEL_SOUNDWIRE
+	select DRIVERS_SOUNDWIRE_ALC_BASE_7XX
+	select DRIVERS_GFX_GENERIC
+	select DRIVERS_I2C_GENERIC
+	select DRIVERS_USB_ACPI
+	select DRIVERS_SPI_ACPI
+	select DUMP_SMBIOS_TYPE17
+	select GENERATE_SMBIOS_TABLES
+	select HAVE_ACPI_RESUME
+	select HAVE_ACPI_TABLES
+	select HAVE_INTEL_PTT
+	select INTEL_GMA_HAVE_VBT
+	select DRIVERS_UART_8250IO
+	select MAINBOARD_USES_IFD_GBE_REGION
+	select MAINBOARD_USES_IFD_EC_REGION
+	select PMC_IPC_ACPI_INTERFACE
+	select SOC_INTEL_COMMON_BLOCK_HDA_VERB
+	select AZALIA_USE_LEGACY_VERB_TABLE
+	select SOC_INTEL_COMMON_BLOCK_MEMINIT
+	select SOC_INTEL_IOE_DIE_SUPPORT
+	select SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES
+	select SOC_INTEL_PANTHERLAKE_H
+	select SOC_INTEL_TCSS_USE_PDC_PMC_USBC_MUX_CONFIGURATION
+	select SUPERIO_ITE_IT8659E
+	# To be removed when we receive production SKUs for testing
+	select SOC_INTEL_PANTHERLAKE_PRE_PRODUCTION_SILICON
+	select FSP_UGOP_EARLY_SIGN_OF_LIFE
+
+config MAINBOARD_SMBIOS_PRODUCT_NAME
+	default "PantherLake CRB"
+
+config MAINBOARD_DIR
+	default "intel/pantherlake_crb"
+
+config MAINBOARD_PART_NUMBER
+	default "PantherLake CRB"
+
+config CBFS_SIZE
+	default 0xA00000
+
+config USE_PM_ACPI_TIMER
+	default n
+
+endif
diff --git a/src/mainboard/intel/pantherlake_crb/Kconfig.name b/src/mainboard/intel/pantherlake_crb/Kconfig.name
new file mode 100644
index 0000000000..788be0ebb4
--- /dev/null
+++ b/src/mainboard/intel/pantherlake_crb/Kconfig.name
@@ -0,0 +1,4 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
+config BOARD_INTEL_PANTHERLAKE_CRB
+	bool "Intel PantherLake CRB for Edge"
diff --git a/src/mainboard/intel/pantherlake_crb/Makefile.mk b/src/mainboard/intel/pantherlake_crb/Makefile.mk
new file mode 100644
index 0000000000..bc081ab530
--- /dev/null
+++ b/src/mainboard/intel/pantherlake_crb/Makefile.mk
@@ -0,0 +1,5 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
+bootblock-y += bootblock.c
+ramstage-y += ramstage.c
+romstage-y += romstage.c
diff --git a/src/mainboard/intel/pantherlake_crb/board.fmd b/src/mainboard/intel/pantherlake_crb/board.fmd
new file mode 100644
index 0000000000..1e1a005c8c
--- /dev/null
+++ b/src/mainboard/intel/pantherlake_crb/board.fmd
@@ -0,0 +1,21 @@
+FLASH 32M {
+	SI_ALL 18M {
+		SI_DESC 16K
+		SI_EC 576K
+		SI_GBE 8K
+		SI_ME
+		SI_PDR 4K
+	}
+
+	SI_BIOS 14M {
+		UNIFIED_MRC_CACHE(PRESERVE) 256K {
+			RECOVERY_MRC_CACHE 128K
+			RW_MRC_CACHE 128K
+		}
+		SMMSTORE(PRESERVE) 256K
+		CONSOLE 128K
+		RW_VPD(PRESERVE) 32K
+		FMAP 2K
+		COREBOOT(CBFS)
+	}
+}
diff --git a/src/mainboard/intel/pantherlake_crb/board_info.txt b/src/mainboard/intel/pantherlake_crb/board_info.txt
new file mode 100644
index 0000000000..2c124320d6
--- /dev/null
+++ b/src/mainboard/intel/pantherlake_crb/board_info.txt
@@ -0,0 +1,6 @@
+Vendor name: Intel
+Board name: PantherLake CRB
+Category: eval
+ROM protocol: SPI
+ROM socketed: y
+Flashrom support: y
diff --git a/src/mainboard/intel/pantherlake_crb/bootblock.c b/src/mainboard/intel/pantherlake_crb/bootblock.c
new file mode 100644
index 0000000000..97955b7c1b
--- /dev/null
+++ b/src/mainboard/intel/pantherlake_crb/bootblock.c
@@ -0,0 +1,24 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <bootblock_common.h>
+#include <soc/gpio.h>
+#include <device/pnp_ops.h>
+#include <superio/ite/common/ite.h>
+#include <superio/ite/it8659e/it8659e.h>
+#include "gpio.h"
+
+#define UART_DEV PNP_DEV(0x4e, IT8659E_SP1)
+#define GPIO_DEV PNP_DEV(0x4e, IT8659E_GPIO)
+
+void bootblock_mainboard_early_init(void)
+{
+	// Early eSPI and LPSS UART initialization
+	gpio_configure_pads(early_gpio_table, ARRAY_SIZE(early_gpio_table));
+
+	ite_reg_write(GPIO_DEV, 0x26, 0xc0);
+	ite_reg_write(GPIO_DEV, 0x29, 0x24);
+	ite_reg_write(GPIO_DEV, 0x2c, 0x88);
+
+	// COM1 (CP2105 Port B)
+	ite_enable_serial(UART_DEV, CONFIG_TTYS0_BASE);
+}
diff --git a/src/mainboard/intel/pantherlake_crb/data.vbt b/src/mainboard/intel/pantherlake_crb/data.vbt
new file mode 100644
index 0000000000000000000000000000000000000000..84ffc62bd454c74948733e99a6ff8f7b1077fd6b
GIT binary patch
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literal 0
HcmV?d00001

diff --git a/src/mainboard/intel/pantherlake_crb/devicetree.cb b/src/mainboard/intel/pantherlake_crb/devicetree.cb
new file mode 100644
index 0000000000..ac7516c89d
--- /dev/null
+++ b/src/mainboard/intel/pantherlake_crb/devicetree.cb
@@ -0,0 +1,262 @@
+chip soc/intel/pantherlake
+
+	register "pmc_gpe0_dw0" = "GPP_A"
+	register "pmc_gpe0_dw1" = "GPP_D"
+	register "pmc_gpe0_dw2" = "GPP_E"
+
+	device domain 0 on
+		device ref igpu on
+			# DDI-A: DP, DDI-B: Unused, DDI-C: Unused
+			# DDI-1: TCP-0, DDI-2: TCP-1, DDI-3: TCP-2, DDI-4: TCP-4
+			register "ddi_port_A_config" = "1"
+			register "ddi_ports_config" = "{
+				[DDI_PORT_A] = DDI_ENABLE_HPD | DDI_ENABLE_DDC,
+				[DDI_PORT_1] = DDI_ENABLE_HPD | DDI_ENABLE_DDC,
+				[DDI_PORT_2] = DDI_ENABLE_HPD | DDI_ENABLE_DDC,
+				[DDI_PORT_3] = DDI_ENABLE_HPD | DDI_ENABLE_DDC,
+				[DDI_PORT_4] = DDI_ENABLE_HPD | DDI_ENABLE_DDC,
+			}"
+		end
+
+		# TODO: IPU Cameras. Currently no modules available.
+
+		# GbE LAN
+		device ref gbe on
+			register "pcie_rp[PCIE_RP(1)]" = "{
+				.clk_src = 3,
+				.clk_req = 3,
+				.flags = PCIE_RP_LTR,
+			}"
+			register "pcie_clk_config_flag[3]" = "PCIE_CLK_LAN"
+		end
+
+		# M.2 WWAN (untested)
+		device ref pcie_rp2 on
+			register "pcie_rp[PCIE_RP(2)]" = "{
+				.clk_src = 5,
+				.clk_req = 5,
+				.flags = PCIE_RP_LTR | PCIE_RP_AER | PCIE_RP_CLK_REQ_DETECT,
+			}"
+		end
+
+		# Gen4 x1 slot
+		device ref pcie_rp3 on
+			register "pcie_rp[PCIE_RP(3)]" = "{
+				.clk_src = 2,
+				.clk_req = 2,
+				.flags = PCIE_RP_LTR | PCIE_RP_AER | PCIE_RP_CLK_REQ_DETECT,
+			}"
+		end
+
+		# M.2 WiFi
+		device ref pcie_rp4 on
+			register "pcie_rp[PCH_RP(4)]" = "{
+				.clk_src = 4,
+				.clk_req = 4,
+				.flags = PCIE_RP_LTR | PCIE_RP_AER | PCIE_RP_CLK_REQ_DETECT,
+			}"
+			chip soc/intel/common/block/pcie/rtd3
+				register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A11)"
+				register "srcclk_pin" = "4"
+				device pci 00.0 on end
+			end
+			chip drivers/wifi/generic
+				register "add_acpi_dma_property" = "true"
+				register "wake" = "GPE0_DW0_12" # GPP_A12
+				use usb2_port7 as bluetooth_companion
+				device pci 00.0 on end
+			end
+		end
+
+		# M.2 SSD Gen4
+		device ref pcie_rp5 on
+			register "pcie_rp[PCIE_RP(5)]" = "{
+				.clk_src = 6,
+				.clk_req = 6,
+				.flags = PCIE_RP_LTR | PCIE_RP_AER | PCIE_RP_CLK_REQ_DETECT,
+			}"
+			chip soc/intel/common/block/pcie/rtd3
+				register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B10)"
+				register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B09)"
+				register "srcclk_pin" = "6"
+				device generic 0 on end
+			end
+		end
+
+		# PEG Gen5 x4 slot (M.2 SSD Gen5 with rework)
+		device ref pcie_rp9 on
+			register "pcie_rp[PCIE_RP(9)]" = "{
+				.clk_src = 1,
+				.clk_req = 1,
+				.flags = PCIE_RP_LTR | PCIE_RP_AER | PCIE_RP_CLK_REQ_DETECT,
+			}"
+		end
+
+		# PEG Gen5 x8 slot (available only on PTL-H484)
+		device ref pcie_rp11 on
+			register "pcie_rp[PCIE_RP(11)]" = "{
+				.clk_src = 0,
+				.clk_req = 0,
+				.flags = PCIE_RP_LTR | PCIE_RP_AER | PCIE_RP_CLK_REQ_DETECT,
+			}"
+		end
+
+		# TODO: Thunderbolt. No AIC modules available at the moment.
+		device ref tbt_pcie_rp0 on end
+		device ref tbt_pcie_rp1 on end
+		device ref tcss_xhci on end
+
+		# TODO: Type-C role switch
+		device ref xhci on
+			register "usb2_ports" = "{
+				[0] = USB2_PORT_TYPE_C(OC3),	// Type-C P0
+				[1] = USB2_PORT_TYPE_C(OC3),	// Type-C P1
+				[2] = USB2_PORT_TYPE_C(OC6),	// Type-C P2
+				[3] = USB2_PORT_TYPE_C(OC7),	// Type-C P3
+				[4] = USB2_PORT_MID(OC0),	// Type-A P1
+				[5] = USB2_PORT_MID(OC0),	// Type-A P2
+				[6] = USB2_PORT_MID(OC_SKIP),	// M.2 WWAN
+				[7] = USB2_PORT_MID(OC_SKIP),	// M.2 NGFF (BT)
+			}"
+
+			register "usb3_ports" = "{
+				[0] = USB3_PORT_DEFAULT(OC0),	// Type-C P1
+				[1] = USB3_PORT_DEFAULT(OC0),	// Type-C P2
+			}"
+		end
+
+		# CNVi (Untested: lack of hardware).
+		device ref cnvi_wifi on
+			chip drivers/wifi/generic
+				register "wake" = "GPE0_PME_B0"
+				register "add_acpi_dma_property" = "true"
+				register "enable_cnvi_ddr_rfim" = "true"
+				use cnvi_bluetooth as bluetooth_companion
+				device generic 0 on end
+			end
+		end
+		device ref cnvi_bluetooth on
+			chip soc/intel/common/block/cnvi
+				register "wake" = "GPE0_PME_B0"
+				device generic 0 on end
+			end
+		end
+
+		device ref npu on end
+
+		# Likely broken on pre-production silicon?
+		# Linux freaks out if it's enabled.
+		device ref iaa off end
+
+		# I2C interfaces
+		device ref i2c0 on
+			# TODO: PD Controller
+				## Port-A @ 0x20
+				## Port-B @ 0x24
+			# TODO: TCSS1
+			# TODO: TCSS2
+			# TODO: TTK3 @ 0x70
+			# TODO: POST_LED @ 0x38
+			# TODO: 1x3 HDR
+		end
+
+		device ref i2c1 on
+			# TODO: IPU CARD 1
+		end
+
+		device ref i2c2 on
+			# TODO: IPU CARD 2
+		end
+
+		device ref i2c3 on
+			# TODO: AUDIO HDR: 0x1a, 0x28, 0x19, 0x2a, 0x2b
+		end
+
+		device ref i2c4 on
+			# TODO: DP Repeater @ (0x08, 0x17)?
+			# TODO: VBY1 HDR @ 0x48
+		end
+
+		device ref i2c5 on end
+
+		# LPSS UART interfaces
+		device ref uart0 on end		# USB-TTL Bridge (Port A).
+		device ref uart1 on end		# J17 header.
+		device ref uart2 on end		# J7 header.
+
+		## UART0 will fail to initialize on pre-production silicon if set to "Pci"!
+		register "serial_io_uart_mode" = "{
+			[PchSerialIoIndexUART0] = PchSerialIoSkipInit,
+			[PchSerialIoIndexUART1] = PchSerialIoHidden,
+			[PchSerialIoIndexUART2] = PchSerialIoHidden,
+		}"
+
+		register "serial_io_uart_dma_enable" = "{
+			[PchSerialIoIndexUART0] = PchSerialDma,
+			[PchSerialIoIndexUART1] = PchSerialDma,
+			[PchSerialIoIndexUART2] = PchSerialDma,
+		}"
+
+		# ITE IT8659E SuperIO
+		device ref soc_espi on
+			chip superio/ite/it8659e
+				device pnp 4e.1 on	# COM1: USB-TTL bridge (Port B)
+					io 0x60 = 0x3f8
+					irq 0x70 = 0x04
+					irq 0xf0 = 0x01
+					irq 0xf1 = 0x50
+					irq 0xf2 = 0x00
+				end
+				device pnp 4e.2 off	# COM2
+					io 0x60 = 0x2f8
+					irq 0x70 = 0x03
+					irq 0xf0 = 0x00
+					irq 0xf1 = 0x50
+					irq 0xf2 = 0x00
+				end
+
+				device pnp 4e.4 on	# EC
+					io 0x60 = 0x290
+					io 0x62 = 0x230
+					irq 0x70 = 0x00
+					irq 0xf0 = 0x80
+					irq 0xf1 = 0x40
+					irq 0xf6 = 0xf0
+				end
+
+				device pnp 4e.5 off end	# PS/2 KB
+				device pnp 4e.6 off end	# PS/2 MS
+
+				device pnp 4e.7 on 	# GPIO
+					io 0x60 = 0x000
+					io 0x62 = 0x000
+					irq 0x26 = 0xc0
+					irq 0x29 = 0x24
+					irq 0x2c = 0x88
+					irq 0x72 = 0x80
+					irq 0xb8 = 0x00
+					irq 0xbc = 0x20
+					irq 0xcb = 0x00
+					irq 0xe7 = 0x10
+					irq 0xf0 = 0x10
+					irq 0xf1 = 0x40
+					irq 0xf4 = 0x2d
+					irq 0xf6 = 0x0e
+				end
+
+				device pnp 4e.a off end	# CIR
+			end
+		end
+
+		# TODO: Realtek ALC722-CG Audio. DSP firmware not upstreamed into Linux yet.
+		device ref hda on
+			register "pch_hda_dsp_enable" = "true"
+			register "pch_hda_idisp_link_tmode" = "HDA_TMODE_8T"
+			register "pch_hda_idisp_link_frequency" = "HDA_LINKFREQ_96MHZ"
+			register "pch_hda_idisp_codec_enable" = "true"
+		end
+
+		device ref pmc_shared_sram on end
+		device ref smbus on end
+	end
+end
diff --git a/src/mainboard/intel/pantherlake_crb/dsdt.asl b/src/mainboard/intel/pantherlake_crb/dsdt.asl
new file mode 100644
index 0000000000..d5571d7a20
--- /dev/null
+++ b/src/mainboard/intel/pantherlake_crb/dsdt.asl
@@ -0,0 +1,29 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+// HACK: MISCCFG_GPIO_PM_CONFIG_BITS are missing
+#include <acpi/acpi.h>
+#include <soc/gpio.h>
+
+DefinitionBlock(
+	"dsdt.aml",
+	"DSDT",
+	ACPI_DSDT_REV_2,
+	OEM_ID,
+	ACPI_TABLE_CREATOR,
+	0x20240917
+)
+
+{
+	#include <acpi/dsdt_top.asl>
+	#include <soc/intel/common/block/acpi/acpi/platform.asl>
+	#include <soc/intel/common/block/acpi/acpi/globalnvs.asl>
+	#include <cpu/intel/common/acpi/cpu.asl>
+
+	Device (\_SB.PCI0) {
+		#include <soc/intel/common/block/acpi/acpi/northbridge.asl>
+		#include <soc/intel/pantherlake/acpi/southbridge.asl>
+		#include <soc/intel/pantherlake/acpi/tcss.asl>
+	}
+
+	#include <southbridge/intel/common/acpi/sleepstates.asl>
+}
diff --git a/src/mainboard/intel/pantherlake_crb/gpio.h b/src/mainboard/intel/pantherlake_crb/gpio.h
new file mode 100644
index 0000000000..b8038005e3
--- /dev/null
+++ b/src/mainboard/intel/pantherlake_crb/gpio.h
@@ -0,0 +1,230 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <soc/gpio.h>
+
+/* GPIOs configured in bootblock */
+static const struct pad_config early_gpio_table[] = {
+	// eSPI: IT8659E SuperIO
+	PAD_CFG_NF(GPP_A00, NONE, DEEP, NF1),	// ESPI_IO0_SIO_R
+	PAD_CFG_NF(GPP_A01, NONE, DEEP, NF1),	// ESPI_IO1_SIO_R
+	PAD_CFG_NF(GPP_A02, NONE, DEEP, NF1),	// ESPI_IO2_SIO_R
+	PAD_CFG_NF(GPP_A03, NONE, DEEP, NF1),	// ESPI_IO3_SIO_R
+	PAD_CFG_NF(GPP_A04, NONE, DEEP, NF1),	// ESPI_CS0_SIO_R_N
+	PAD_CFG_NF(GPP_A05, NONE, DEEP, NF1),	// ESPI_CLK_SIO
+	PAD_CFG_NF(GPP_A06, NONE, DEEP, NF1),	// ESPI_RST_SIO_R_N
+	PAD_CFG_NF(GPP_B24, NONE, DEEP, NF1),	// ESPI_ALERT_SIO_R_N
+
+	// LPSS UART0: USB TTL bridge
+	PAD_CFG_NF(GPP_H08, NONE, DEEP, NF1),	// RXD
+	PAD_CFG_NF(GPP_H09, NONE, DEEP, NF1),	// TXD
+	PAD_CFG_NF(GPP_H10, NONE, DEEP, NF1),	// RTS
+	PAD_CFG_NF(GPP_H11, NONE, DEEP, NF1),	// CTS
+
+	// LPSS UART1: J17 header
+	PAD_CFG_NF(GPP_H14, NONE, DEEP, NF2),	// TXD
+	PAD_CFG_NF(GPP_H15, NONE, DEEP, NF2),	// RXD
+
+	// LPSS UART2: J7 header
+	PAD_CFG_NF(GPP_F00, NONE, DEEP, NF2),	// RTS
+	PAD_CFG_NF(GPP_F01, NONE, DEEP, NF2),	// RXD
+	PAD_CFG_NF(GPP_F02, NONE, DEEP, NF2),	// TXD
+	PAD_CFG_NF(GPP_F03, NONE, DEEP, NF2),	// CTS
+
+};
+
+/* GPIOs configured in romstage */
+static const struct pad_config main_gpio_table[] = {
+	/* GPIO Community A */
+	PAD_CFG_GPO(GPP_A08, 1, PLTRST),	// X1_PCIE_SLOT_PWR_EN
+	PAD_CFG_GPO(GPP_A09, 0, DEEP),		// M.2_WWAN_FCP_OFF_N
+	PAD_CFG_GPO(GPP_A10, 0, DEEP),		// M.2_WWAN_DISABLE_N
+	PAD_CFG_GPO(GPP_A11, 1, PLTRST),	// WLAN_RST_N
+	PAD_CFG_GPI_SCI_LOW(GPP_A12, NONE, DEEP, LEVEL),	// WLAN_WAKE_N
+	PAD_CFG_NF(GPP_A13, NONE, PLTRST, NF1), // WWAN_DPR
+	PAD_CFG_NF(GPP_A15, NONE, DEEP, NF1),	// DNX_FORCE_RELOAD
+	PAD_CFG_GPO(GPP_A16, 1, DEEP),		// BT_RF_KILL_N
+	PAD_CFG_GPO(GPP_A17, 1, DEEP),		// WIFI_RF_KILL_N
+
+	/* GPIO Community B */
+	PAD_CFG_NF(GPP_B00, NONE, DEEP, NF1),	// USB-C SMLCLK
+	PAD_CFG_NF(GPP_B01, NONE, DEEP, NF1),	// USB-C SMLDATA
+	PAD_CFG_NF(GPP_B02, NONE, DEEP, NF3),	// CAM1_ISH_I2C_SDA
+	PAD_CFG_NF(GPP_B03, NONE, DEEP, NF3),	// CAM1_ISH_I2C_SCL
+	PAD_CFG_GPO(GPP_B04, 0, DEEP),		// VBY1_BKLTCTRL_3P3V
+	PAD_CFG_GPO(GPP_B05, 0, DEEP),		// VBY1_GPIO2_3P3V
+	PAD_CFG_GPO(GPP_B06, 0, DEEP),		// VBY1_GPIO1_3P3V
+	PAD_CFG_NF(GPP_B07, NONE, DEEP, NF4),	// ALC722 PCBEEP
+	PAD_CFG_GPO(GPP_B08, 0, DEEP),		// VBY1_GPIO0_3P3V
+	PAD_CFG_GPO(GPP_B09, 1, PLTRST),	// M2_GEN4_SSD_RESET_N
+	PAD_CFG_GPO(GPP_B10, 0, PLTRST),	// M2_GEN4_SSD_PWR_DIS
+	PAD_CFG_NF(GPP_B11, NONE, DEEP, NF2),	// MOD_TCSS1_DISP_HPD3
+	PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1),	// PM_SLP_S0_N
+	PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1),	// PLT_RST_N
+	PAD_CFG_NF(GPP_B14, NONE, DEEP, NF2),	// MOD_TCSS2_DISP_HPD4
+	PAD_CFG_NF(GPP_B15, NONE, DEEP, NF1),	// MOD_TCSS1_USB_TYP_A_OC3_N
+	PAD_CFG_GPO(GPP_B16, 0, PLTRST),	// X4_PCIE_SLOT_PWR_EN_N
+	PAD_NC(GPP_B17, NONE),			// N/C
+	PAD_CFG_NF(GPP_B18, NONE, DEEP, NF2),	// DDIA_RDVR_I2C_DATA
+	PAD_CFG_NF(GPP_B19, NONE, DEEP, NF2),	// DDIA_RDVR_I2C_CLK
+	PAD_CFG_GPO(GPP_B20, 1, PLTRST),	// M.2_WWAN_RST_BUF_N
+	PAD_CFG_GPO(GPP_B21, 0, DEEP),		// TCP_RETIMER_FORCE_PWR
+	PAD_CFG_GPO(GPP_B22, 0, PLTRST),	// TIME_SYNC0
+	PAD_CFG_GPO(GPP_B23, 0, PLTRST),	// TIME_SYNC1
+	// B24 configured in bootblock
+	PAD_CFG_GPI_SCI_LOW(GPP_B25, NONE, DEEP, LEVEL),	// X1_SLOT_LAN_WAKE_N
+
+	/* GPIO Community C */
+	PAD_CFG_NF(GPP_C00, NONE, DEEP, NF1),	// DRAM_HSCL_1P0
+	PAD_CFG_NF(GPP_C01, NONE, DEEP, NF1),	// DRAM_HSDA_1P0
+	PAD_CFG_GPI_SCI_LOW(GPP_C02, NONE, DEEP, LEVEL),	// PCA9555_0_INT_N
+	PAD_CFG_NF(GPP_C03, NONE, DEEP, NF1),	// SML0_SCL_LAN_PCIE
+	PAD_CFG_NF(GPP_C04, NONE, DEEP, NF1),	// SML0_SDA_LAN_PCIE
+	PAD_CFG_GPO(GPP_C05, 0, DEEP),		// CRD1_PWREN
+	PAD_NC(GPP_C06, NONE),			// N/C
+	PAD_NC(GPP_C07, NONE),			// N/C
+	PAD_CFG_GPO(GPP_C08, 0, DEEP),		// CRD2_PWREN
+
+	/* Source Clock Requests */
+	PAD_CFG_NF(GPP_C09, NONE, DEEP, NF1),	// SRCCLKREQ0: X8_GEN5_DT_CEM_SLOT_FOR_DGFX
+	PAD_CFG_NF(GPP_C10, NONE, DEEP, NF1),	// SRCCLKREQ1: X4_GEN5_DT_CEM_SLOT
+	PAD_CFG_NF(GPP_C11, NONE, DEEP, NF1),	// SRCCLKREQ2: X1_GEN4_DT_CEM_SLOT
+	PAD_CFG_NF(GPP_C12, NONE, DEEP, NF1),	// SRCCLKREQ3: I226_LAN
+	PAD_CFG_NF(GPP_C13, NONE, DEEP, NF1),	// SRCCLKREQ4: M.2_WLAN_KEY-E
+	PAD_CFG_NF(GPP_C14, NONE, DEEP, NF1),	// SRCCLKREQ5: M.2_WWAN_KEY-B
+	PAD_CFG_NF(GPP_D18, NONE, DEEP, NF1),	// SRCCLKREQ6: X4_GEN4_M.2_SSD_KEY-M
+	PAD_CFG_NF(GPP_D20, NONE, DEEP, NF1),	// SRCCLKREQ7: N/C, exposed on RFSH
+	PAD_CFG_NF(GPP_D21, NONE, DEEP, NF1),	// SRCCLKREQ8: N/C, exposed on RFSH
+
+	PAD_CFG_GPO(GPP_C15, 1, PLTRST),	// CAM1_CLK_EN
+
+	/* Thunderbolt/USB-C Display Data Channels */
+	PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1),	// TBT_LSX0_TXD
+	PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1),	// TBT_LSX0_RXD
+	PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1),	// TBT_LSX1_TXD
+	PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1),	// TBT_LSX1_RXD
+	PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1),	// MOD_TCSS1_LS_TX_DDC_SCL
+	PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1),	// MOD_TCSS1_LS_RX_DDC_SDA
+	PAD_CFG_NF(GPP_C22, NONE, DEEP, NF2),	// MOD_TCSS2_LS_TX_DDC_SCL
+	PAD_CFG_NF(GPP_C23, NONE, DEEP, NF2),	// MOD_TCSS2_LS_RX_DDC_SDA
+
+	/* GPIO Community D */
+	PAD_CFG_NF(GPP_D00, NONE, DEEP, NF1),	// IMGCLKOUT_1
+	PAD_CFG_GPO(GPP_D01, 1, DEEP),		// MOD_TCSS1_TYP_A_VBUS_EN
+	PAD_CFG_GPO(GPP_D02, 1, DEEP),		// VBY1_BKLTEN_3P3V
+	PAD_CFG_GPO(GPP_D03, 1, PLTRST),	// M.2_WWAN_PERST_GPIO_N
+	PAD_CFG_NF(GPP_D04, NONE, DEEP, NF1),	// IMGCLKOUT_0
+	PAD_NC(GPP_D05, NONE),			// Unknown, exposed on RFSH
+	PAD_NC(GPP_D06, NONE),			// Unknown, exposed on RFSH
+	PAD_NC(GPP_D07, NONE),			// N/C
+	PAD_NC(GPP_D08, NONE),			// N/C
+	PAD_CFG_GPO(GPP_D09, 1, PLTRST),	// PEG_SLOT_RST_N
+	PAD_CFG_NF(GPP_D10, NONE, DEEP, NF1),	// HDA_BCLK_I2S0_SCLK_HDR
+	PAD_CFG_NF(GPP_D11, NONE, DEEP, NF1),	// HDA_SYNC_I2S0_SFRM_HDR
+	PAD_CFG_NF(GPP_D12, NONE, DEEP, NF1),	// HDA_SDO_I2S0_TXD_HDR
+	PAD_CFG_NF(GPP_D13, NONE, DEEP, NF1),	// HDA_SDI0_I2S0_RXD_HDR
+	PAD_CFG_GPI_TRIG_OWN(GPP_D14, NONE, PLTRST, LEVEL, ACPI),		// COINLESS_MODE_SELECT
+	PAD_CFG_GPI_APIC_LOCK(GPP_D15, NONE, LEVEL, INVERT, LOCK_CONFIG),	// SPI_TPM_INT_N
+	PAD_CFG_NF(GPP_D16, NONE, DEEP, NF1),	// HDA_RST_N_HDR
+	PAD_CFG_NF(GPP_D17, NONE, DEEP, NF1),	// HDA_SDI1_HDR
+	PAD_CFG_GPO(GPP_D19, 1, PLTRST),	// X1_DT_PCIE_RST_N
+	PAD_CFG_NF(GPP_D22, NONE, DEEP, NF1),	// PD_TCP1_DBG_I3C_SDA
+	PAD_CFG_NF(GPP_D23, NONE, DEEP, NF1),	// PD_TCP1_DBG_I3C_SCL
+	PAD_CFG_GPI_SCI_LOW(GPP_D24, NONE, DEEP, LEVEL),	// PEG_SLOT_WAKE_N
+	PAD_CFG_GPI_SCI_LOW(GPP_D25, NONE, DEEP, LEVEL),	// X4_SLOT_WAKE_N
+
+	/* GPIO Community E */
+	PAD_CFG_GPO(GPP_E01, 0, PLTRST),	// CRD2_RST_N
+	PAD_NC(GPP_E02, NONE),			// N/C
+	PAD_CFG_GPO(GPP_E03, 1, PLTRST),	// X4_DT_PCIE_RST_N
+	PAD_CFG_GPI_SCI_LOW(GPP_E05, NONE, DEEP, LEVEL),		// VBY1_INT_3P3V_N
+	PAD_CFG_GPI_TRIG_OWN(GPP_E06, NONE, PLTRST, LEVEL, ACPI),	// SECURE_CAM_SW
+	PAD_CFG_NF(GPP_E07, NONE, DEEP, NF1),	// DDPA_DDIA_CTRLCLK_R
+	PAD_CFG_NF(GPP_E08, NONE, DEEP, NF1),	// DDPA_DDIA_CTRLDATA_R
+	PAD_CFG_NF(GPP_E09, NONE, DEEP, NF1),	// USB32_TYPEA_CONN1_OC0_N
+	PAD_CFG_GPO(GPP_E10, 0, PLTRST),	// CAM1_RST_N
+	PAD_NC(GPP_E11, NONE),			// GSPI0_CLK: N/C, exposed on RFSH
+	PAD_NC(GPP_E12, NONE),			// GSPI0_MOSI: N/C, exposed on RFSH
+	PAD_NC(GPP_E13, NONE),			// GSPI0_MISO: N/C, exposed on RFSH
+	PAD_CFG_NF(GPP_E14, NONE, DEEP, NF3),	// PD_ALERT_N
+	PAD_NC(GPP_E15, NONE),			// N/C
+	PAD_CFG_GPI_SCI_LOW(GPP_E16, NONE, DEEP, LEVEL),		// DEV_MODE_ID
+	PAD_NC(GPP_E17, NONE),			// GSPI0_CS0: N/C, exposed on RFSH
+	PAD_NC(GPP_E18, NONE),			// N/C, TP1506
+	PAD_NC(GPP_E19, NONE),			// X8_PEG_SEL_PROCHOT_N
+	PAD_NC(GPP_E20, NONE),			// X8_PEG_DGPU_PWR_OK_3P3
+	PAD_CFG_NF(GPP_E21, NONE, DEEP, NF1),	// PMC_ALERT_N
+	PAD_NC(GPP_E22, NONE),			// N/C
+
+	/* GPIO Community F */
+	PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_F04, NONE, DEEP, NF1),	// CNV_RF_RESET_R_N
+	PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_F05, NONE, DEEP, NF3),	// CRF_CLKREQ_R
+
+	PAD_NC(GPP_F06, NONE),			// N/C
+	PAD_CFG_NF(GPP_F07, NONE, DEEP, NF2),	// IMGCLKOUT_2
+	PAD_CFG_GPO(GPP_F08, 0, PLTRST),	// N/C, but exposed on FUSA and J25
+	PAD_CFG_NF(GPP_F09, NONE, DEEP, NF4),	// ISH_INT_GP11_CVS_+V12S_CRD1
+	PAD_CFG_GPO(GPP_F10, 0, PLTRST),	// PEG_SLOT_PWR_EN_N
+	PAD_CFG_GPO(GPP_F11, 1, DEEP),		// MOD_TCSS2_TYP_A_VBUS_EN
+	PAD_CFG_GPI_TRIG_OWN(GPP_F12, NONE, PLTRST, LEVEL, ACPI),	// MOD_TCSS2_DETECT
+	PAD_CFG_GPI_TRIG_OWN(GPP_F13, NONE, PLTRST, LEVEL, ACPI),	// MOD_TCSS2_DETECT_R
+	PAD_NC(GPP_F14, NONE),			// N/C
+	PAD_NC(GPP_F15, NONE),			// N/C
+	PAD_NC(GPP_F16, NONE),			// N/C
+	PAD_CFG_GPI(GPP_F17, NONE, DEEP),	// CODEC_IRQ_HDR
+	PAD_NC(GPP_F18, NONE),			// N/C
+	PAD_CFG_GPO(GPP_F19, 0, PLTRST),	// PRIVACY_LED_CAM2
+	PAD_CFG_GPO(GPP_F20, 0, PLTRST),	// PRIVACY_LED_CAM1_CVS_HST_WAKE
+	PAD_CFG_GPO(GPP_F22, 1, PLTRST),	// MOD_TCSS1/2_SX_CNTRL_R
+	PAD_CFG_GPI_SCI_LOW(GPP_F23, NONE, DEEP, LEVEL),		// M.2_WWAN_WAKE
+
+	/* GPIO Community H */
+	PAD_CFG_GPO(GPP_H00, 0, PLTRST),	// CAM2_CLK_EN
+	PAD_CFG_GPO(GPP_H01, 0, PLTRST),	// CAM2_FLSH_STROBE
+	PAD_CFG_GPO(GPP_H02, 0, PLTRST),	// DNX_IN_PROG_LED_R
+	PAD_CFG_NF(GPP_H03, NONE, DEEP, NF1),	// MIC_MUTE
+	PAD_CFG_NF(GPP_H04, NONE, DEEP, NF1),	// I2C2_SDA_CAM_FLSH
+	PAD_CFG_NF(GPP_H05, NONE, DEEP, NF1),	// I2C2_SCL_CAM_FLSH
+	PAD_CFG_NF(GPP_H06, NONE, DEEP, NF1),	// I2C3_SDA_AUDIO_HDR
+	PAD_CFG_NF(GPP_H07, NONE, DEEP, NF1),	// I2C3_SCL_AUDIO_HDR
+
+	/* GPP_H08, H09, H10 and H11 are configured in bootblock for early UART0 bringup
+	 * GPP_H14 and H15 are configured in bootblock for early UART1 bringup */
+
+	PAD_CFG_NF(GPP_H13, NONE, DEEP, NF1),	// CPU_C10_GATE_N
+	PAD_NC(GPP_H16, NONE),			// N/C
+	PAD_CFG_NF(GPP_H17, NONE, DEEP, NF1),	// MIC_MUTE_LED
+	PAD_CFG_NF(GPP_H19, NONE, DEEP, NF1),	// I2C0_SDA_PORT80_DISP_R
+	PAD_CFG_NF(GPP_H20, NONE, DEEP, NF1),	// I2C0_SCL_PORT80_DISP_R
+	PAD_NC(GPP_H21, NONE),			// N/C
+	PAD_NC(GPP_H22, NONE),			// N/C
+
+	/* GPIO Community S (SoundWire) */
+	PAD_CFG_NF(GPP_S00, NONE, DEEP, NF1),	// SNDW3_CLK_CODEC
+	PAD_CFG_NF(GPP_S01, NONE, DEEP, NF1),	// SNDW3_DATA0_CODEC
+	PAD_CFG_NF(GPP_S02, NONE, DEEP, NF1),	// SNDW3_DATA1_CODEC
+	PAD_CFG_NF(GPP_S03, NONE, DEEP, NF1),	// SNDW3_DATA2_CODEC
+	PAD_CFG_NF(GPP_S04, NONE, DEEP, NF2),	// SNDW2_CLK_DMIC_CLK_A
+	PAD_CFG_NF(GPP_S05, NONE, DEEP, NF2),	// SNDW2_DATA0
+	PAD_CFG_NF(GPP_S06, NONE, DEEP, NF3),	// SNDW1_CLK_DMIC1
+	PAD_CFG_NF(GPP_S07, NONE, DEEP, NF3),	// SNDW1_DATA0_DMIC1
+
+	/* GPIO Community V */
+	PAD_CFG_NF(GPP_V00, NONE, DEEP, NF1),	// BATLOW_N
+	PAD_CFG_NF(GPP_V01, NONE, DEEP, NF1),	// AC_PRESENT
+	PAD_CFG_NF(GPP_V02, NONE, DEEP, NF1),	// LANWAKE_N
+	PAD_CFG_NF(GPP_V03, NONE, DEEP, NF1),	// PM_PWRBTN_N
+	PAD_CFG_NF(GPP_V04, NONE, DEEP, NF1),	// PM_SLP_S3_N
+	PAD_CFG_NF(GPP_V05, NONE, DEEP, NF1),	// PM_SLP_S4_N
+	PAD_CFG_NF(GPP_V06, NONE, DEEP, NF1),	// PM_SLP_A_N
+	PAD_NC(GPP_V07, NONE),			// N/C
+	PAD_CFG_NF(GPP_V08, NONE, DEEP, NF1),	// SLP_WLAN_N
+	PAD_CFG_NF(GPP_V09, NONE, DEEP, NF1),	// PM_SLP_S5_N
+	PAD_CFG_NF(GPP_V10, NONE, DEEP, NF1),	// LAN_PHY_PC
+	PAD_CFG_NF(GPP_V11, NONE, DEEP, NF1),	// LAN_SW_EN
+	PAD_CFG_NF(GPP_V12, NONE, DEEP, NF1),	// WAKE_N
+	PAD_CFG_NF(GPP_V13, NONE, DEEP, NF1),	// H_CATERR_N
+	PAD_CFG_NF(GPP_V14, NONE, DEEP, NF1),	// FORCE_PROCHOT
+	PAD_CFG_NF(GPP_V15, NONE, DEEP, NF1),	// THERMTRIP_N
+	PAD_CFG_NF(GPP_V16, NONE, DEEP, NF1),	// VCCST_EN_R
+	PAD_CFG_GPO(GPP_V17, 1, DEEP),		// MOD_TCSS1_RT_S0IX_ENTRY_EXIT_N
+};
diff --git a/src/mainboard/intel/pantherlake_crb/hda_verb.c b/src/mainboard/intel/pantherlake_crb/hda_verb.c
new file mode 100644
index 0000000000..ee90770400
--- /dev/null
+++ b/src/mainboard/intel/pantherlake_crb/hda_verb.c
@@ -0,0 +1,12 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <device/azalia_device.h>
+
+const u32 cim_verb_data[] = {
+	// TODO: Realtek ALC722-CG pins
+};
+
+const u32 pc_beep_verbs[] = {
+};
+
+AZALIA_ARRAY_SIZES;
diff --git a/src/mainboard/intel/pantherlake_crb/ramstage.c b/src/mainboard/intel/pantherlake_crb/ramstage.c
new file mode 100644
index 0000000000..ea5e3ab781
--- /dev/null
+++ b/src/mainboard/intel/pantherlake_crb/ramstage.c
@@ -0,0 +1,20 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <device/device.h>
+#include <soc/pci_devs.h>
+#include <soc/ramstage.h>
+#include "gpio.h"
+
+static void init_mainboard(void *chip_info)
+{
+	gpio_configure_pads(main_gpio_table, ARRAY_SIZE(main_gpio_table));
+}
+
+struct chip_operations mainboard_ops = {
+	.init = init_mainboard,
+};
+
+void mainboard_silicon_init_params(FSP_S_CONFIG *params)
+{
+	params->PchLegacyIoLowLatency = 1;
+}
diff --git a/src/mainboard/intel/pantherlake_crb/romstage.c b/src/mainboard/intel/pantherlake_crb/romstage.c
new file mode 100644
index 0000000000..a3e8815370
--- /dev/null
+++ b/src/mainboard/intel/pantherlake_crb/romstage.c
@@ -0,0 +1,64 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <soc/meminit.h>
+#include <soc/romstage.h>
+
+static const struct mb_cfg mem_config = {
+	.type = MEM_TYPE_DDR5,
+	.user_bd = BOARD_TYPE_ULT_ULX,
+	.ect = true,
+
+	.rcomp = {
+		.resistor = 100,
+	},
+
+	.ddr_config = {
+		.dq_pins_interleaved = false,
+	}
+};
+
+static const struct mem_spd spd_info = {
+	.topo = MEM_TOPO_DIMM_MODULE,
+	.smbus = {
+		[0] = {
+			.addr_dimm[0] = 0x50,
+			.addr_dimm[1] = 0x0,
+		},
+
+		[1] = {
+			.addr_dimm[0] = 0x50,
+			.addr_dimm[1] = 0x0,
+		},
+
+		[2] = {
+			.addr_dimm[0] = 0x52,
+			.addr_dimm[1] = 0x0,
+		},
+
+		[3] = {
+			.addr_dimm[0] = 0x52,
+			.addr_dimm[1] = 0x0,
+		},
+	},
+};
+
+void mainboard_memory_init_params(FSPM_UPD *mupd)
+{
+	const uint8_t channel_to_ckd_qck[] = { 0, 0, 1, 0, 0, 0, 1, 0 };
+	memcpy(mupd->FspmConfig.ChannelToCkdQckMapping,
+		channel_to_ckd_qck, sizeof(channel_to_ckd_qck));
+
+	const uint8_t phy_clock_to_ckd_dimm[] = { 0, 0, 0, 0, 8, 0, 8, 0 };
+	memcpy(mupd->FspmConfig.PhyClockToCkdDimm,
+		phy_clock_to_ckd_dimm, sizeof(phy_clock_to_ckd_dimm));
+
+
+	// Raise FSP loglevel for verbose debugging. Requires debug build (NDA).
+	//	mupd->FspmConfig.PcdSerialDebugLevel = 4;
+
+	// GpioOverride needs to be disabled, messes with PCIe CLKREQs
+	mupd->FspmConfig.GpioOverride = 0;
+	mupd->FspmConfig.EnableAbove4GBMmio = 1;
+
+	memcfg_init(mupd, &mem_config, &spd_info, false);
+}

From 4772d019f340c74a8cb1abb8907ccd59da17e86c Mon Sep 17 00:00:00 2001
From: Patrick Rudolph <patrick.rudolph@9elements.com>
Date: Mon, 26 Jan 2026 07:36:20 +0100
Subject: [PATCH 3271/3886] soc/intel/apollolake: Align MPinit code

Align the MPinit code with other Intel CPU drivers and move the
microcode update on the BSP to pre_mp_init(). This also ensures that
the microcode is located in CBFS before the MTRRs are set up using
x86_setup_mtrrs_with_detect() which removes caching the SPI flash
MMIO area.

No functional change, thus untested.

Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Change-Id: I47573dde5d471c9654ea9f14bd24b2a7087dd6df
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90909
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
---
 src/soc/intel/apollolake/cpu.c | 8 +++++---
 1 file changed, 5 insertions(+), 3 deletions(-)

diff --git a/src/soc/intel/apollolake/cpu.c b/src/soc/intel/apollolake/cpu.c
index fb95009f7d..67450b2d5d 100644
--- a/src/soc/intel/apollolake/cpu.c
+++ b/src/soc/intel/apollolake/cpu.c
@@ -162,6 +162,11 @@ static void pre_mp_init(void)
 		fsps_load();
 		return;
 	}
+
+	/* Make sure BSP is using the microcode from cbfs */
+	const struct microcode *microcode_patch = intel_microcode_find();
+	intel_microcode_load_unlocked(microcode_patch);
+
 	x86_setup_mtrrs_with_detect();
 	x86_mtrr_check();
 }
@@ -192,9 +197,6 @@ void get_microcode_info(const void **microcode, int *parallel)
 {
 	*microcode = intel_microcode_find();
 	*parallel = 1;
-
-	/* Make sure BSP is using the microcode from cbfs */
-	intel_microcode_load_unlocked(*microcode);
 }
 #endif
 

From f91f18cdc4f7bf5f1a552d54218084928b2eeb06 Mon Sep 17 00:00:00 2001
From: Nick Vaccaro <nvaccaro@google.com>
Date: Wed, 21 Jan 2026 13:56:36 -0800
Subject: [PATCH 3272/3886] mb/goog/ocelot/var/ocelot: add LPSS touchscreen
 support for Rex Touchscreen

Support for the rex touchscreen panel was needed for the RVP to validate touchscreen functionality. The LPSS touchscreen is mapped to I2C bus 4 and the rex panel is mapped to address 0x10.

BUG=b:458429110
TEST=None

Change-Id: I99b2c7beaab63da1877995c655ff8eddf9c3a69f
Signed-off-by: Avi Uday <aviuday@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90859
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Pranava Y N <pranavayn@google.com>
---
 .../google/ocelot/variants/ocelot/fw_config.c | 23 +++++++++++++++
 .../ocelot/variants/ocelot/overridetree.cb    | 28 ++++++++++++++++++-
 2 files changed, 50 insertions(+), 1 deletion(-)

diff --git a/src/mainboard/google/ocelot/variants/ocelot/fw_config.c b/src/mainboard/google/ocelot/variants/ocelot/fw_config.c
index d9f68ab505..003cd84728 100644
--- a/src/mainboard/google/ocelot/variants/ocelot/fw_config.c
+++ b/src/mainboard/google/ocelot/variants/ocelot/fw_config.c
@@ -292,6 +292,27 @@ static const struct pad_config touchscreen_disable_pads[] = {
 	PAD_NC(GPP_VGPIO3_THC0, NONE),
 };
 
+static const struct pad_config touchscreen_lpss_i2c_enable_pads[] = {
+	/* GPP_E11:     THC0_SPI1_CLK_TCH_PNL1 */
+	PAD_NC(GPP_E11, NONE),
+	/* GPP_E12:     THC0_SPI1_IO_0_I2C4_SCL_TCH_PNL1 NF1: THC I2C0_SCL */
+	PAD_CFG_NF(GPP_E12, NONE, DEEP, NF8),
+	/* GPP_E13:     THC0_SPI1_IO_1_I2C4_SDA_TCH_PNL1 NF1: THC I2C0 SDA */
+	PAD_CFG_NF(GPP_E13, NONE, DEEP, NF8),
+	/* GPP_E14:     THC0_SPI1_IO_2_TCH_PNL1 */
+	PAD_NC(GPP_E14, NONE),
+	/* GPP_E15:     THC0_SPI1_IO_3_TCH_PNL1 */
+	PAD_NC(GPP_E15, NONE),
+	/* GPP_E16:     THC0_SPI1_RST_N_TCH_PNL1 */
+	PAD_CFG_GPO(GPP_E16, 1, DEEP),
+	/* GPP_E17:     THC0_SPI1_CS0_N_TCH_PNL1 */
+	PAD_NC(GPP_E17, NONE),
+	/* GPP_E18:     THC0_SPI1_INT_N_TCH_PNL1 */
+	PAD_CFG_GPI_APIC(GPP_E18, NONE, PLTRST, LEVEL, NONE),
+	/* GPP_VGPIO3_THC0: THC0_WOT */
+	PAD_NC(GPP_VGPIO3_THC0, NONE),
+};
+
 static const struct pad_config touchscreen_thc_i2c_enable_pads[] = {
 	/* GPP_E11:     THC0_SPI1_CLK_TCH_PNL1 */
 	PAD_NC(GPP_E11, NONE),
@@ -572,6 +593,8 @@ void fw_config_gpio_padbased_override(struct pad_config *padbased_table)
 		GPIO_PADBASED_OVERRIDE(padbased_table, touchscreen_thc_spi_enable_pads);
 		if (config->thc_wake_on_touch[0])
 			GPIO_PADBASED_OVERRIDE(padbased_table, thc0_enable_wake);
+	} else if (fw_config_probe(FW_CONFIG(TOUCHSCREEN, TOUCHSCREEN_LPSS_I2C_ELAN_REX))) {
+		GPIO_PADBASED_OVERRIDE(padbased_table, touchscreen_lpss_i2c_enable_pads);
 	} else {
 		GPIO_PADBASED_OVERRIDE(padbased_table, touchscreen_disable_pads);
 	}
diff --git a/src/mainboard/google/ocelot/variants/ocelot/overridetree.cb b/src/mainboard/google/ocelot/variants/ocelot/overridetree.cb
index d7bd320ccd..5a36e4bf0b 100644
--- a/src/mainboard/google/ocelot/variants/ocelot/overridetree.cb
+++ b/src/mainboard/google/ocelot/variants/ocelot/overridetree.cb
@@ -21,6 +21,7 @@ fw_config
 		option TOUCHSCREEN_NONE			0
 		option TOUCHSCREEN_THC_SPI		1
 		option TOUCHSCREEN_THC_I2C		2
+		option TOUCHSCREEN_LPSS_I2C_ELAN_REX	3
 	end
 	field TOUCHPAD 9 10
 		option TOUCHPAD_NONE			0
@@ -93,7 +94,7 @@ chip soc/intel/pantherlake
 		[PchSerialIoIndexI2C1]  = PchSerialIoPci,
 		[PchSerialIoIndexI2C2]  = PchSerialIoDisabled,
 		[PchSerialIoIndexI2C3]  = PchSerialIoPci,
-		[PchSerialIoIndexI2C4]  = PchSerialIoDisabled,
+		[PchSerialIoIndexI2C4]  = PchSerialIoPci,
 		[PchSerialIoIndexI2C5]  = PchSerialIoPci,
 	}"
 
@@ -109,6 +110,7 @@ chip soc/intel/pantherlake
 	#+-------------------+---------------------------+
 	#| I2C1              | TPM(cr50)                 |
 	#| I2C3              | Audio                     |
+	#| I2C4		     | Touchscreen (LPSS)	 |
 	#| I2C5              | Touchpad                  |
 	#+-------------------+---------------------------+
 	register "common_soc_config" = "{
@@ -123,6 +125,10 @@ chip soc/intel/pantherlake
 			.speed = I2C_SPEED_FAST,
 			.early_init = 1,
 		},
+		.i2c[4] = {
+			.speed = I2C_SPEED_FAST,
+			.early_init = 1,
+		},
 		.i2c[5] = {
 			.speed = I2C_SPEED_FAST,
 		},
@@ -553,6 +559,26 @@ chip soc/intel/pantherlake
 				end
 			end
 		end #I2C3
+		device ref i2c4 on
+			chip drivers/i2c/hid
+				register "generic.hid" = ""ELAN9006""
+				register "generic.desc" = ""ELAN Touchscreen""
+				register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_E18_IRQ)"
+				# NOTE: pmc_gpe0_dw2 is GPP_E in baseboard devicetree.cb.
+				register "generic.wake" = "GPE0_DW2_18"
+				register "generic.probed" = "1"
+				register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_E16)"
+				register "generic.reset_delay_ms" = "20"
+				register "generic.reset_off_delay_ms" = "2"
+				register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_F08)"
+				register "generic.enable_delay_ms" = "1"
+				register "generic.has_power_resource" = "1"
+				register "hid_desc_reg_offset" = "0x01"
+				device i2c 10 on
+					probe TOUCHSCREEN TOUCHSCREEN_LPSS_I2C_ELAN_REX
+				end
+			end
+		end # I2C4
 		device ref i2c5 on
 			chip drivers/i2c/hid
 				register "generic.hid" = ""HFW68H""

From 283359601e01c35c1d191de67531e8151ed73b70 Mon Sep 17 00:00:00 2001
From: Yu-Ping Wu <yupingso@google.com>
Date: Fri, 6 Feb 2026 09:55:45 +0800
Subject: [PATCH 3273/3886] commonlib/list: Drop 'const' qualifier from return
 type

The 'const' qualifier is unnecessary for the return values of the
following:

- list_next()
- list_prev()
- list_first()
- list_last()

Therefore, drop it. No caller needs to be changed.

Change-Id: I0f5bc2b0ed3cd47d0d6355c8dffea17f6e085407
Signed-off-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91113
Reviewed-by: Jakub "Kuba" Czapiga <czapiga@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
---
 src/commonlib/include/commonlib/list.h | 12 ++++++------
 src/commonlib/list.c                   |  9 ++++++---
 2 files changed, 12 insertions(+), 9 deletions(-)

diff --git a/src/commonlib/include/commonlib/list.h b/src/commonlib/include/commonlib/list.h
index 9bad52f3a3..ce74ca34b6 100644
--- a/src/commonlib/include/commonlib/list.h
+++ b/src/commonlib/include/commonlib/list.h
@@ -29,27 +29,27 @@ static inline bool list_is_empty(const struct list_node *head)
 }
 
 // Get next node.
-static inline const struct list_node *list_next(const struct list_node *node,
-						const struct list_node *head)
+static inline struct list_node *list_next(const struct list_node *node,
+					  const struct list_node *head)
 {
 	return node->next;
 };
 
 // Get prev node.
-static inline const struct list_node *list_prev(const struct list_node *node,
-						const struct list_node *head)
+static inline struct list_node *list_prev(const struct list_node *node,
+					  const struct list_node *head)
 {
 	return node->prev == head ? NULL : node->prev;
 };
 
 // Get first node.
-static inline const struct list_node *list_first(const struct list_node *head)
+static inline struct list_node *list_first(const struct list_node *head)
 {
 	return list_is_empty(head) ? NULL : head->next;
 }
 
 // Get last node.
-const struct list_node *list_last(const struct list_node *head);
+struct list_node *list_last(const struct list_node *head);
 
 // Get the number of list elements.
 size_t list_length(const struct list_node *head);
diff --git a/src/commonlib/list.c b/src/commonlib/list.c
index 9d11d9606c..1af92c8ac5 100644
--- a/src/commonlib/list.c
+++ b/src/commonlib/list.c
@@ -37,12 +37,15 @@ void list_append(struct list_node *node, struct list_node *head)
 	list_insert_after(node, head);
 }
 
-const struct list_node *list_last(const struct list_node *head)
+struct list_node *list_last(const struct list_node *head)
 {
-	const struct list_node *ptr = head;
+	if (!head->next)
+		return NULL;
+
+	struct list_node *ptr = head->next;
 	while (ptr->next)
 		ptr = ptr->next;
-	return ptr == head ? NULL : ptr;
+	return ptr;
 }
 
 size_t list_length(const struct list_node *head)

From 546707da25f0c0837bc25c44e2e434646702b99d Mon Sep 17 00:00:00 2001
From: Subrata Banik <subratabanik@google.com>
Date: Thu, 5 Feb 2026 11:59:25 +0530
Subject: [PATCH 3274/3886] lib: Generalize low-battery shutdown delay to
 post-render delay
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

The existing PLATFORM_LOW_BATTERY_SHUTDOWN_DELAY_SEC was strictly
tied to the low-battery indicator logic. This change renames and
generalizes the configuration to PLATFORM_POST_RENDER_DELAY_SEC.

By moving this out of the low-battery specific conditional block in
Kconfig, the delay can now be utilized more broadly. While it still
ensures the low-battery warning remains visible before power-off, it
can now also be used to ensure display synchronization or user
notifications are visible before passing control to the OS in normal
boot flows.

Updated Intel common reset logic to utilize the renamed config.

BUG=b:473480933
TEST=Verified that low-battery shutdown still respects the 5-second
default delay on target hardware.

Change-Id: I0277ea278fb299499f6eab2be983761a8f6ba536
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91104
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/lib/Kconfig              | 15 ++++++++-------
 src/soc/intel/common/reset.c |  2 +-
 2 files changed, 9 insertions(+), 8 deletions(-)

diff --git a/src/lib/Kconfig b/src/lib/Kconfig
index 6407c82cfa..0c8fc454ff 100644
--- a/src/lib/Kconfig
+++ b/src/lib/Kconfig
@@ -229,16 +229,17 @@ config PLATFORM_HAS_LOW_BATTERY_INDICATOR
 	  This option requires that the system have a display and that the BMP_LOGO option is
 	  enabled.
 
-if PLATFORM_HAS_LOW_BATTERY_INDICATOR
-
-config PLATFORM_LOW_BATTERY_SHUTDOWN_DELAY_SEC
+config PLATFORM_POST_RENDER_DELAY_SEC
 	int
 	default 5
 	help
-	  Delay, in seconds, before system shutdown due to low battery.
-	  This delay allows the user to observe the low-battery indicator.
-	  The default value of 5 seconds aligns with standard user experience (UX) practices.
-	  Platforms may override this value based on specific product requirements.
+	  Delay, in seconds, after rendering a splash screen element.
+	  In low-battery mode, this ensures the warning is visible before shutdown.
+	  In normal modes, this can be used to ensure the display has finished
+	  teardown/synchronization after user notification before passing control
+	  to the OS.
+
+if PLATFORM_HAS_LOW_BATTERY_INDICATOR
 
 config PLATFORM_HAS_EARLY_LOW_BATTERY_INDICATOR
 	bool "Display low battery indicator in romstage"
diff --git a/src/soc/intel/common/reset.c b/src/soc/intel/common/reset.c
index 307be5769a..40cea6bccc 100644
--- a/src/soc/intel/common/reset.c
+++ b/src/soc/intel/common/reset.c
@@ -28,7 +28,7 @@ void do_low_battery_poweroff(void)
 {
 	if (CONFIG(PLATFORM_HAS_LOW_BATTERY_INDICATOR)) {
 		elog_add_event_byte(ELOG_TYPE_LOW_BATTERY_INDICATOR, ELOG_FW_ISSUE_SHUTDOWN);
-		delay(CONFIG_PLATFORM_LOW_BATTERY_SHUTDOWN_DELAY_SEC);
+		delay(CONFIG_PLATFORM_POST_RENDER_DELAY_SEC);
 	}
 
 	poweroff();

From 1472a023779450cad64d12a121bed49972e994ef Mon Sep 17 00:00:00 2001
From: Subrata Banik <subratabanik@google.com>
Date: Fri, 6 Feb 2026 10:27:32 +0530
Subject: [PATCH 3275/3886] mb/google/bluey: Use PLATFORM_POST_RENDER_DELAY_SEC
 for battery shutdown

Replace the local LOW_BATTERY_SHUTDOWN_DELAY_SEC macro with the newly
introduced, globally configurable PLATFORM_POST_RENDER_DELAY_SEC
Kconfig.

This aligns the bluey mainboard with the shared platform delay logic,
ensuring a consistent user experience across products while allowing
easier adjustment of the shutdown/teardown timing buffer.

TEST=Verified build and boot on bluey; critical battery shutdown still
respects the intended 5-second delay (as per default Kconfig).

Change-Id: I1ddab276e797b793974e0205a91ba832f3085ead
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91114
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
---
 src/mainboard/google/bluey/mainboard.c | 4 +---
 1 file changed, 1 insertion(+), 3 deletions(-)

diff --git a/src/mainboard/google/bluey/mainboard.c b/src/mainboard/google/bluey/mainboard.c
index b12edfdabe..5b6278b3a0 100644
--- a/src/mainboard/google/bluey/mainboard.c
+++ b/src/mainboard/google/bluey/mainboard.c
@@ -30,8 +30,6 @@
 #define USB3_MODE_NORMAL_VAL	0x21
 #define USB3_MODE_FLIP_VAL	0x23
 
-#define LOW_BATTERY_SHUTDOWN_DELAY_SEC 5
-
 void mainboard_usb_typec_configure(uint8_t port_num, bool inverse_polarity)
 {
 	if (!CONFIG(MAINBOARD_HAS_PS8820_RETIMER))
@@ -166,7 +164,7 @@ static void trigger_critical_battery_shutdown(void)
 	elog_add_event_byte(ELOG_TYPE_LOW_BATTERY_INDICATOR, ELOG_FW_ISSUE_SHUTDOWN);
 
 	/* Allow time for the log to flush and the user to see the LED change */
-	delay(LOW_BATTERY_SHUTDOWN_DELAY_SEC);
+	delay(CONFIG_PLATFORM_POST_RENDER_DELAY_SEC);
 
 	google_chromeec_ap_poweroff();
 }

From 901cac7c3c0740eb689a716d85e2e34b14dfaa79 Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Thu, 5 Feb 2026 12:20:44 +0000
Subject: [PATCH 3276/3886] x86/mtrr: Avoid WC for VGA BARs above 4GiB

On Arrow Lake we ran out of variable MTRRs, leaving PCI BARs uncached.
This made the edk2 setup UI extremely slow due to UC MMIO/framebuffer
writes.

Ensure BAR ranges get a cacheable attribute instead of falling back to
UC.

Change-Id: I74a89cf334d1eb74bbfbb4b0f9621f098bfa4a89
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91109
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/cpu/x86/mtrr/mtrr.c | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/src/cpu/x86/mtrr/mtrr.c b/src/cpu/x86/mtrr/mtrr.c
index 72727861de..001f9b5a88 100644
--- a/src/cpu/x86/mtrr/mtrr.c
+++ b/src/cpu/x86/mtrr/mtrr.c
@@ -122,6 +122,16 @@ static int filter_vga_wrcomb(struct device *dev, struct resource *res)
 	if (((dev->class >> 8) != PCI_CLASS_DISPLAY_VGA))
 		return 0;
 
+	/*
+	 * Only mark 32-bit BARs as WC. Some platforms expose additional large
+	 * prefetchable BARs above 4GiB for the iGPU, and tagging those as WC
+	 * can fragment the address space enough to exhaust variable MTRRs.
+	 * Keeping the below-4GiB framebuffer WC is the priority for payload UI
+	 * performance.
+	 */
+	if (res->size != 0 && res->base >= 0x100000000ULL)
+		return 0;
+
 	/* Add resource as write-combining in the address space. */
 	return 1;
 }

From 007a6c492b7ae01ee640ca4f6f5c8504ff1143c1 Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Tue, 3 Feb 2026 10:12:03 +0000
Subject: [PATCH 3277/3886] mb/starlabs/starbook/adl: Update layout to match
 updated descriptor

The descriptor was updated to support Raptor Lake upgrades, which
increased the ME region size.

Change-Id: I0fa909e8aa58c8825fb9cd0301e9bbc60cf1ca89
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91111
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
---
 src/mainboard/starlabs/starbook/variants/adl/board.fmd | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/mainboard/starlabs/starbook/variants/adl/board.fmd b/src/mainboard/starlabs/starbook/variants/adl/board.fmd
index 7495d43cec..b921fa1f2b 100644
--- a/src/mainboard/starlabs/starbook/variants/adl/board.fmd
+++ b/src/mainboard/starlabs/starbook/variants/adl/board.fmd
@@ -1,7 +1,7 @@
 FLASH	0x2000000 {
 	SI_ALL	0x1000000 {
 		SI_DESC			0x1000
-		SI_ME			0x41c000
+		SI_ME			0x4c0000
 	}
 	SI_BIOS 0x1000000 {
 		EC@0x0			0x20000

From 16c7e63ae435a1fddb92c2ed3bded5147714e6d7 Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Thu, 29 Jan 2026 12:35:49 +0000
Subject: [PATCH 3278/3886] mb/starlabs/*: Restructure CFR options

Adjust the option groups into more logical groups, and ensure all
are alphabetised.

Change-Id: I8bac31206e16146ce55c3946fa8e8e4accdc7060
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91112
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/starlabs/adl/cfr.c          | 128 ++++++++++-------
 src/mainboard/starlabs/byte_adl/cfr.c     |  89 ++++++------
 src/mainboard/starlabs/lite/cfr.c         | 103 +++++++------
 src/mainboard/starlabs/starbook/cfr.c     | 168 ++++++++++++++--------
 src/mainboard/starlabs/starfighter/cfr.c  | 152 ++++++++++++--------
 src/mainboard/starlabs/starlite_adl/cfr.c | 132 +++++++++++------
 6 files changed, 475 insertions(+), 297 deletions(-)

diff --git a/src/mainboard/starlabs/adl/cfr.c b/src/mainboard/starlabs/adl/cfr.c
index 4f920a69f6..634f945f6e 100644
--- a/src/mainboard/starlabs/adl/cfr.c
+++ b/src/mainboard/starlabs/adl/cfr.c
@@ -7,58 +7,76 @@
 #include <intelblocks/cfr.h>
 #include <common/cfr.h>
 
-static struct sm_obj_form performance_group = {
-	.ui_name = "Performance",
+static struct sm_obj_form battery_group = {
+	.ui_name = "Battery",
 	.obj_list = (const struct sm_object *[]) {
-		&fan_mode,
-		&memory_speed,
-		&power_profile,
-		NULL
-	},
-};
-
-static struct sm_obj_form processor_group = {
-	.ui_name = "Processor",
-	.obj_list = (const struct sm_object *[]) {
-		&me_state,
-		&me_state_counter,
-		&s0ix_enable,
-		&vtd,
-		NULL
-	},
-};
-
-static struct sm_obj_form power_group = {
-	.ui_name = "Power",
-	.obj_list = (const struct sm_object *[]) {
-		&max_charge,
 		&charging_speed,
-		&power_led,
-		&charge_led,
+		&max_charge,
 		&power_on_after_fail_bool,
 		NULL
 	},
 };
 
+static struct sm_obj_form debug_group = {
+	.ui_name = "Debug",
+	.obj_list = (const struct sm_object *[]) {
+		&debug_level,
+		NULL
+	},
+};
+
+static struct sm_obj_form leds_group = {
+	.ui_name = "LEDs",
+	.obj_list = (const struct sm_object *[]) {
+		&charge_led,
+		&power_led,
+		NULL
+	},
+};
+
 static struct sm_obj_form keyboard_group = {
 	.ui_name = "Keyboard",
 	.obj_list = (const struct sm_object *[]) {
-		&kbl_timeout,
 		&fn_ctrl_swap,
+		&kbl_timeout,
 		NULL
 	},
 };
 
-static struct sm_obj_form devices_group = {
-	.ui_name = "Devices",
+static struct sm_obj_form audio_video_group = {
+	.ui_name = "Audio/Video",
 	.obj_list = (const struct sm_object *[]) {
-		&bluetooth,
-		&display_native_res,
-		&gna,
-		&lid_switch,
 		&microphone,
 		&webcam,
-		&wifi,
+		NULL
+	},
+};
+
+static struct sm_obj_form display_group = {
+	.ui_name = "Display",
+	.obj_list = (const struct sm_object *[]) {
+		&display_native_res,
+		NULL
+	},
+};
+
+static struct sm_obj_form pcie_power_management_group = {
+	.ui_name = "PCIe Power Management",
+	.obj_list = (const struct sm_object *[]) {
+		&pciexp_aspm,
+		&pciexp_clk_pm,
+		&pciexp_l1ss,
+		NULL
+	},
+};
+
+static struct sm_obj_form performance_group = {
+	.ui_name = "Performance",
+	.obj_list = (const struct sm_object *[]) {
+		&fan_mode,
+		&gna,
+		&memory_speed,
+		&power_profile,
 		NULL
 	},
 };
@@ -68,37 +86,51 @@ static struct sm_obj_form security_group = {
 	.obj_list = (const struct sm_object *[]) {
 		&bios_lock,
 		&intel_tme,
+		&me_state,
+		&me_state_counter,
 		NULL
 	},
 };
 
-static struct sm_obj_form pci_group = {
-	.ui_name = "PCI",
+static struct sm_obj_form suspend_lid_group = {
+	.ui_name = "Suspend & Lid",
 	.obj_list = (const struct sm_object *[]) {
-		&pciexp_clk_pm,
-		&pciexp_aspm,
-		&pciexp_l1ss,
+		&lid_switch,
+		&s0ix_enable,
 		NULL
 	},
 };
 
-static struct sm_obj_form coreboot_group = {
-	.ui_name = "coreboot",
+static struct sm_obj_form virtualization_group = {
+	.ui_name = "Virtualization",
 	.obj_list = (const struct sm_object *[]) {
-		&debug_level,
+		&vtd,
+		NULL
+	},
+};
+
+static struct sm_obj_form wireless_group = {
+	.ui_name = "Wireless",
+	.obj_list = (const struct sm_object *[]) {
+		&bluetooth,
+		&wifi,
 		NULL
 	},
 };
 
 static struct sm_obj_form *sm_root[] = {
-	&performance_group,
-	&processor_group,
-	&power_group,
+	&audio_video_group,
+	&battery_group,
+	&debug_group,
+	&display_group,
 	&keyboard_group,
-	&devices_group,
+	&leds_group,
+	&pcie_power_management_group,
+	&performance_group,
 	&security_group,
-	&pci_group,
-	&coreboot_group,
+	&suspend_lid_group,
+	&virtualization_group,
+	&wireless_group,
 	NULL
 };
 
diff --git a/src/mainboard/starlabs/byte_adl/cfr.c b/src/mainboard/starlabs/byte_adl/cfr.c
index d67d501508..bf658a4249 100644
--- a/src/mainboard/starlabs/byte_adl/cfr.c
+++ b/src/mainboard/starlabs/byte_adl/cfr.c
@@ -8,41 +8,38 @@
 #include <variants.h>
 #include <common/cfr.h>
 
-static struct sm_obj_form performance_group = {
-	.ui_name = "Performance",
-	.obj_list = (const struct sm_object *[]) {
-		&bluetooth_rtd3,
-		&fan_mode,
-		&power_profile,
-		NULL
-	},
-};
-
-static struct sm_obj_form processor_group = {
-	.ui_name = "Processor",
-	.obj_list = (const struct sm_object *[]) {
-		&me_state,
-		&me_state_counter,
-		&s0ix_enable,
-		&vtd,
-		NULL
-	},
-};
-
-static struct sm_obj_form power_group = {
-	.ui_name = "Power",
+static struct sm_obj_form battery_group = {
+	.ui_name = "Battery",
 	.obj_list = (const struct sm_object *[]) {
 		&power_on_after_fail_bool,
 		NULL
 	},
 };
 
-static struct sm_obj_form devices_group = {
-	.ui_name = "Devices",
+static struct sm_obj_form debug_group = {
+	.ui_name = "Debug",
 	.obj_list = (const struct sm_object *[]) {
-		&bluetooth,
+		&debug_level,
+		NULL
+	},
+};
+
+static struct sm_obj_form pcie_power_management_group = {
+	.ui_name = "PCIe Power Management",
+	.obj_list = (const struct sm_object *[]) {
+		&pciexp_aspm,
+		&pciexp_clk_pm,
+		&pciexp_l1ss,
+		NULL
+	},
+};
+
+static struct sm_obj_form performance_group = {
+	.ui_name = "Performance",
+	.obj_list = (const struct sm_object *[]) {
+		&fan_mode,
 		&gna,
-		&wifi,
+		&power_profile,
 		NULL
 	},
 };
@@ -52,37 +49,47 @@ static struct sm_obj_form security_group = {
 	.obj_list = (const struct sm_object *[]) {
 		&bios_lock,
 		&intel_tme,
+		&me_state,
+		&me_state_counter,
 		NULL
 	},
 };
 
-
-static struct sm_obj_form pci_group = {
-	.ui_name = "PCI",
+static struct sm_obj_form suspend_lid_group = {
+	.ui_name = "Suspend & Lid",
 	.obj_list = (const struct sm_object *[]) {
-		&pciexp_clk_pm,
-		&pciexp_aspm,
-		&pciexp_l1ss,
+		&s0ix_enable,
 		NULL
 	},
 };
 
-static struct sm_obj_form coreboot_group = {
-	.ui_name = "coreboot",
+static struct sm_obj_form virtualization_group = {
+	.ui_name = "Virtualization",
 	.obj_list = (const struct sm_object *[]) {
-		&debug_level,
+		&vtd,
+		NULL
+	},
+};
+
+static struct sm_obj_form wireless_group = {
+	.ui_name = "Wireless",
+	.obj_list = (const struct sm_object *[]) {
+		&bluetooth,
+		&bluetooth_rtd3,
+		&wifi,
 		NULL
 	},
 };
 
 static struct sm_obj_form *sm_root[] = {
+	&battery_group,
+	&debug_group,
+	&pcie_power_management_group,
 	&performance_group,
-	&processor_group,
-	&power_group,
-	&devices_group,
 	&security_group,
-	&pci_group,
-	&coreboot_group,
+	&suspend_lid_group,
+	&virtualization_group,
+	&wireless_group,
 	NULL
 };
 
diff --git a/src/mainboard/starlabs/lite/cfr.c b/src/mainboard/starlabs/lite/cfr.c
index 0ca59b8e48..4a91a46a06 100644
--- a/src/mainboard/starlabs/lite/cfr.c
+++ b/src/mainboard/starlabs/lite/cfr.c
@@ -8,48 +8,44 @@
 #include <variants.h>
 #include <common/cfr.h>
 
-static struct sm_obj_form performance_group = {
-	.ui_name = "Performance",
+static struct sm_obj_form audio_video_group = {
+	.ui_name = "Audio/Video",
 	.obj_list = (const struct sm_object *[]) {
-		&power_profile,
+		&microphone,
+		&webcam,
 		NULL
 	},
 };
 
-static struct sm_obj_form processor_group = {
-	.ui_name = "Processor",
-	.obj_list = (const struct sm_object *[]) {
-		&s0ix_enable,
-		&vtd,
-		NULL
-	},
-};
-
-static struct sm_obj_form power_group = {
-	.ui_name = "Power",
+static struct sm_obj_form battery_group = {
+	.ui_name = "Battery",
 	.obj_list = (const struct sm_object *[]) {
 		&power_on_after_fail_bool,
 		NULL
 	},
 };
 
+static struct sm_obj_form debug_group = {
+	.ui_name = "Debug",
+	.obj_list = (const struct sm_object *[]) {
+		&debug_level,
+		NULL
+	},
+};
+
+static struct sm_obj_form io_expansion_group = {
+	.ui_name = "I/O / Expansion",
+	.obj_list = (const struct sm_object *[]) {
+		&card_reader,
+		NULL
+	},
+};
+
 static struct sm_obj_form keyboard_group = {
 	.ui_name = "Keyboard",
 	.obj_list = (const struct sm_object *[]) {
-		&kbl_timeout,
 		&fn_ctrl_swap,
-		NULL
-	},
-};
-
-static struct sm_obj_form devices_group = {
-	.ui_name = "Devices",
-	.obj_list = (const struct sm_object *[]) {
-		&bluetooth,
-		&card_reader,
-		&microphone,
-		&webcam,
-		&wifi,
+		&kbl_timeout,
 		NULL
 	},
 };
@@ -63,36 +59,63 @@ static struct sm_obj_form security_group = {
 	},
 };
 
-
-static struct sm_obj_form pci_group = {
-	.ui_name = "PCI",
+static struct sm_obj_form pcie_power_management_group = {
+	.ui_name = "PCIe Power Management",
 	.obj_list = (const struct sm_object *[]) {
 		#if CONFIG(SOC_INTEL_ALDERLAKE)
-		&pciexp_clk_pm,
 		&pciexp_aspm,
+		&pciexp_clk_pm,
 		&pciexp_l1ss,
 		#endif
 		NULL
 	},
 };
 
-static struct sm_obj_form coreboot_group = {
-	.ui_name = "coreboot",
+static struct sm_obj_form performance_group = {
+	.ui_name = "Performance",
 	.obj_list = (const struct sm_object *[]) {
-		&debug_level,
+		&power_profile,
+		NULL
+	},
+};
+
+static struct sm_obj_form suspend_lid_group = {
+	.ui_name = "Suspend & Lid",
+	.obj_list = (const struct sm_object *[]) {
+		&s0ix_enable,
+		NULL
+	},
+};
+
+static struct sm_obj_form virtualization_group = {
+	.ui_name = "Virtualization",
+	.obj_list = (const struct sm_object *[]) {
+		&vtd,
+		NULL
+	},
+};
+
+static struct sm_obj_form wireless_group = {
+	.ui_name = "Wireless",
+	.obj_list = (const struct sm_object *[]) {
+		&bluetooth,
+		&wifi,
 		NULL
 	},
 };
 
 static struct sm_obj_form *sm_root[] = {
-	&performance_group,
-	&processor_group,
-	&power_group,
+	&audio_video_group,
+	&battery_group,
+	&debug_group,
+	&io_expansion_group,
 	&keyboard_group,
-	&devices_group,
+	&pcie_power_management_group,
+	&performance_group,
 	&security_group,
-	&pci_group,
-	&coreboot_group,
+	&suspend_lid_group,
+	&virtualization_group,
+	&wireless_group,
 	NULL
 };
 
diff --git a/src/mainboard/starlabs/starbook/cfr.c b/src/mainboard/starlabs/starbook/cfr.c
index f95ff65cb3..10263c45fa 100644
--- a/src/mainboard/starlabs/starbook/cfr.c
+++ b/src/mainboard/starlabs/starbook/cfr.c
@@ -7,79 +7,107 @@
 #include <intelblocks/cfr.h>
 #include <common/cfr.h>
 
-static struct sm_obj_form performance_group = {
-	.ui_name = "Performance",
+static struct sm_obj_form audio_video_group = {
+	.ui_name = "Audio/Video",
 	.obj_list = (const struct sm_object *[]) {
-		&bluetooth_rtd3,
-		&fan_mode,
-		&power_profile,
+		&microphone,
+		&webcam,
 		NULL
 	},
 };
 
-static struct sm_obj_form processor_group = {
-	.ui_name = "Processor",
+static struct sm_obj_form battery_group = {
+	.ui_name = "Battery",
 	.obj_list = (const struct sm_object *[]) {
-		&me_state,
-		&me_state_counter,
-		#if CONFIG(BOARD_SUPPORTS_HT)
-		&hyper_threading,
-		#endif
-		&s0ix_enable,
-		&vtd,
-		NULL
-	},
-};
-
-static struct sm_obj_form power_group = {
-	.ui_name = "Power",
-	.obj_list = (const struct sm_object *[]) {
-		&max_charge,
 		#if CONFIG(EC_STARLABS_CHARGING_SPEED)
 		&charging_speed,
 		#endif
-		&power_led,
-		&charge_led,
+		&max_charge,
 		&power_on_after_fail_bool,
 		NULL
 	},
 };
 
+static struct sm_obj_form debug_group = {
+	.ui_name = "Debug",
+	.obj_list = (const struct sm_object *[]) {
+		&debug_level,
+		NULL
+	},
+};
+
+#if CONFIG(BOARD_USES_FIXED_MODE_VBT)
+static struct sm_obj_form display_group = {
+	.ui_name = "Display",
+	.obj_list = (const struct sm_object *[]) {
+		&display_native_res,
+		NULL
+	},
+};
+#endif
+
+static struct sm_obj_form io_expansion_group = {
+	.ui_name = "I/O / Expansion",
+	.obj_list = (const struct sm_object *[]) {
+		&card_reader,
+		#if CONFIG(BOARD_STARLABS_STARBOOK_ADL)
+		&pci_hot_plug,
+		#endif
+		#if CONFIG(DRIVERS_INTEL_USB4_RETIMER)
+		&thunderbolt,
+		#endif
+		NULL
+	},
+};
+
 static struct sm_obj_form keyboard_group = {
 	.ui_name = "Keyboard",
 	.obj_list = (const struct sm_object *[]) {
-		&kbl_timeout,
 		&fn_ctrl_swap,
+		&kbl_timeout,
 		NULL
 	},
 };
 
-static struct sm_obj_form devices_group = {
-	.ui_name = "Devices",
+static struct sm_obj_form leds_group = {
+	.ui_name = "LEDs",
 	.obj_list = (const struct sm_object *[]) {
-		&bluetooth,
-		&card_reader,
-		#if CONFIG(BOARD_USES_FIXED_MODE_VBT)
-		&display_native_res,
+		&charge_led,
+		&power_led,
+		NULL
+	},
+};
+
+static struct sm_obj_form pcie_power_management_group = {
+	.ui_name = "PCIe Power Management",
+	.obj_list = (const struct sm_object *[]) {
+		#if CONFIG(SOC_INTEL_COMMON_BLOCK_ASPM)
+		#if CONFIG(BOARD_STARLABS_STARBOOK_RPL)
+		&pciexp_aspm_cpu,
+		#else
+		&pciexp_aspm,
 		#endif
-		#if CONFIG(BOARD_HAS_FPR)
-		&fingerprint_reader,
+		&pciexp_clk_pm,
+		&pciexp_l1ss,
 		#endif
+		NULL
+	},
+};
+
+static struct sm_obj_form performance_group = {
+	.ui_name = "Performance",
+	.obj_list = (const struct sm_object *[]) {
+		&fan_mode,
 		#if CONFIG(BOARD_HAS_GNA)
 		&gna,
 		#endif
-		#if CONFIG(EC_STARLABS_LID_SWITCH)
-		&lid_switch,
-		#endif
-		&microphone,
-		#if CONFIG(DRIVERS_INTEL_USB4_RETIMER)
-		&thunderbolt,
+		#if CONFIG(BOARD_SUPPORTS_HT)
+		&hyper_threading,
 		#endif
+		&power_profile,
 		#if CONFIG(SOC_INTEL_METEORLAKE)
 		&vpu,
 		#endif
-		&webcam,
-		&wifi,
 		NULL
 	},
 };
@@ -88,47 +116,61 @@ static struct sm_obj_form security_group = {
 	.ui_name = "Security",
 	.obj_list = (const struct sm_object *[]) {
 		&bios_lock,
+		#if CONFIG(BOARD_HAS_FPR)
+		&fingerprint_reader,
+		#endif
 		&intel_tme,
+		&me_state,
+		&me_state_counter,
 		NULL
 	},
 };
 
-static struct sm_obj_form pci_group = {
-	.ui_name = "PCI",
+static struct sm_obj_form suspend_lid_group = {
+	.ui_name = "Suspend & Lid",
 	.obj_list = (const struct sm_object *[]) {
-		#if CONFIG(BOARD_STARLABS_STARBOOK_ADL)
-		&pci_hot_plug,
-		#endif
-		#if CONFIG(SOC_INTEL_COMMON_BLOCK_ASPM)
-		&pciexp_clk_pm,
-		#if CONFIG(BOARD_STARLABS_STARBOOK_RPL)
-		&pciexp_aspm_cpu,
-		#else
-		&pciexp_aspm,
-		#endif
-		&pciexp_l1ss,
+		#if CONFIG(EC_STARLABS_LID_SWITCH)
+		&lid_switch,
 		#endif
+		&s0ix_enable,
 		NULL
 	},
 };
 
-static struct sm_obj_form coreboot_group = {
-	.ui_name = "coreboot",
+static struct sm_obj_form virtualization_group = {
+	.ui_name = "Virtualization",
 	.obj_list = (const struct sm_object *[]) {
-		&debug_level,
+		&vtd,
+		NULL
+	},
+};
+
+static struct sm_obj_form wireless_group = {
+	.ui_name = "Wireless",
+	.obj_list = (const struct sm_object *[]) {
+		&bluetooth,
+		&bluetooth_rtd3,
+		&wifi,
 		NULL
 	},
 };
 
 static struct sm_obj_form *sm_root[] = {
-	&performance_group,
-	&processor_group,
-	&power_group,
+	&audio_video_group,
+	&battery_group,
+	&debug_group,
+	#if CONFIG(BOARD_USES_FIXED_MODE_VBT)
+	&display_group,
+	#endif
+	&io_expansion_group,
 	&keyboard_group,
-	&devices_group,
+	&leds_group,
+	&pcie_power_management_group,
+	&performance_group,
 	&security_group,
-	&pci_group,
-	&coreboot_group,
+	&suspend_lid_group,
+	&virtualization_group,
+	&wireless_group,
 	NULL
 };
 
diff --git a/src/mainboard/starlabs/starfighter/cfr.c b/src/mainboard/starlabs/starfighter/cfr.c
index dc306f5776..cb092cae33 100644
--- a/src/mainboard/starlabs/starfighter/cfr.c
+++ b/src/mainboard/starlabs/starfighter/cfr.c
@@ -8,65 +8,87 @@
 #include <variants.h>
 #include <common/cfr.h>
 
-static struct sm_obj_form performance_group = {
-	.ui_name = "Performance",
+static struct sm_obj_form battery_group = {
+	.ui_name = "Battery",
 	.obj_list = (const struct sm_object *[]) {
-		&bluetooth_rtd3,
-		&memory_speed,
-		&fan_mode,
-		&power_profile,
-		NULL
-	},
-};
-
-static struct sm_obj_form processor_group = {
-	.ui_name = "Processor",
-	.obj_list = (const struct sm_object *[]) {
-		&me_state,
-		&me_state_counter,
-		&hyper_threading,
-		&s0ix_enable,
-		&vtd,
-		NULL
-	},
-};
-
-static struct sm_obj_form power_group = {
-	.ui_name = "Power",
-	.obj_list = (const struct sm_object *[]) {
-		&max_charge,
 		#if CONFIG(EC_STARLABS_CHARGING_SPEED)
 		&charging_speed,
 		#endif
-		&power_led,
-		&charge_led,
+		&max_charge,
 		&power_on_after_fail_bool,
 		NULL
 	},
 };
 
-static struct sm_obj_form keyboard_group = {
-	.ui_name = "Keyboard",
+static struct sm_obj_form debug_group = {
+	.ui_name = "Debug",
 	.obj_list = (const struct sm_object *[]) {
-		&kbl_timeout,
-		&fn_ctrl_swap,
+		&debug_level,
 		NULL
 	},
 };
 
-static struct sm_obj_form devices_group = {
-	.ui_name = "Devices",
+static struct sm_obj_form display_group = {
+	.ui_name = "Display",
 	.obj_list = (const struct sm_object *[]) {
+		&display_native_res,
+		NULL
+	},
+};
+
+#if CONFIG(DRIVERS_INTEL_USB4_RETIMER)
+static struct sm_obj_form io_expansion_group = {
+	.ui_name = "I/O / Expansion",
+	.obj_list = (const struct sm_object *[]) {
+		&thunderbolt,
+		NULL
+	},
+};
+#endif
+
+static struct sm_obj_form keyboard_group = {
+	.ui_name = "Keyboard",
+	.obj_list = (const struct sm_object *[]) {
+		&fn_ctrl_swap,
+		&kbl_timeout,
+		NULL
+	},
+};
+
+static struct sm_obj_form leds_group = {
+	.ui_name = "LEDs",
+	.obj_list = (const struct sm_object *[]) {
+		&charge_led,
+		&power_led,
+		NULL
+	},
+};
+
+static struct sm_obj_form pcie_power_management_group = {
+	.ui_name = "PCIe Power Management",
+	.obj_list = (const struct sm_object *[]) {
+		#if CONFIG(SOC_INTEL_COMMON_BLOCK_ASPM)
+		&pciexp_aspm,
+		#if CONFIG(HAS_INTEL_CPU_ROOT_PORTS)
+		&pciexp_aspm_cpu,
+		#endif
+		&pciexp_clk_pm,
+		&pciexp_l1ss,
+		#endif
+		NULL
+	},
+};
+
+static struct sm_obj_form performance_group = {
+	.ui_name = "Performance",
+	.obj_list = (const struct sm_object *[]) {
+		&fan_mode,
 		#if CONFIG(SOC_INTEL_TIGERLAKE) || CONFIG(SOC_INTEL_ALDERLAKE) || CONFIG(SOC_INTEL_RAPTORLAKE)
 		&gna,
 		#endif
-		&display_native_res,
-		#if CONFIG(EC_STARLABS_LID_SWITCH)
-		&lid_switch,
-		#endif
-		#if CONFIG(DRIVERS_INTEL_USB4_RETIMER)
-		&thunderbolt,
-		#endif
+		&hyper_threading,
+		&memory_speed,
+		&power_profile,
 		#if CONFIG(SOC_INTEL_METEORLAKE)
 		&vpu,
 		#endif
@@ -79,42 +101,54 @@ static struct sm_obj_form security_group = {
 	.obj_list = (const struct sm_object *[]) {
 		&bios_lock,
 		&intel_tme,
+		&me_state,
+		&me_state_counter,
 		NULL
 	},
 };
 
-static struct sm_obj_form pci_group = {
-	.ui_name = "PCI",
+static struct sm_obj_form suspend_lid_group = {
+	.ui_name = "Suspend & Lid",
 	.obj_list = (const struct sm_object *[]) {
-		#if CONFIG(SOC_INTEL_COMMON_BLOCK_ASPM)
-		&pciexp_clk_pm,
-		&pciexp_aspm,
-		#if CONFIG(HAS_INTEL_CPU_ROOT_PORTS)
-		&pciexp_aspm_cpu,
-		#endif
-		&pciexp_l1ss,
+		#if CONFIG(EC_STARLABS_LID_SWITCH)
+		&lid_switch,
 		#endif
+		&s0ix_enable,
 		NULL
 	},
 };
 
-static struct sm_obj_form coreboot_group = {
-	.ui_name = "coreboot",
+static struct sm_obj_form virtualization_group = {
+	.ui_name = "Virtualization",
 	.obj_list = (const struct sm_object *[]) {
-		&debug_level,
+		&vtd,
+		NULL
+	},
+};
+
+static struct sm_obj_form wireless_group = {
+	.ui_name = "Wireless",
+	.obj_list = (const struct sm_object *[]) {
+		&bluetooth_rtd3,
 		NULL
 	},
 };
 
 static struct sm_obj_form *sm_root[] = {
-	&performance_group,
-	&processor_group,
-	&power_group,
+	&battery_group,
+	&debug_group,
+	&display_group,
+	#if CONFIG(DRIVERS_INTEL_USB4_RETIMER)
+	&io_expansion_group,
+	#endif
 	&keyboard_group,
-	&devices_group,
+	&leds_group,
+	&pcie_power_management_group,
+	&performance_group,
 	&security_group,
-	&pci_group,
-	&coreboot_group,
+	&suspend_lid_group,
+	&virtualization_group,
+	&wireless_group,
 	NULL
 };
 
diff --git a/src/mainboard/starlabs/starlite_adl/cfr.c b/src/mainboard/starlabs/starlite_adl/cfr.c
index 004cd75945..0cf911b9f2 100644
--- a/src/mainboard/starlabs/starlite_adl/cfr.c
+++ b/src/mainboard/starlabs/starlite_adl/cfr.c
@@ -26,58 +26,82 @@ void cfr_touchscreen_update(struct sm_object *new_obj)
 		new_obj->sm_bool.flags = CFR_OPTFLAG_SUPPRESS;
 }
 
-static struct sm_obj_form performance_group = {
-	.ui_name = "Performance",
+static struct sm_obj_form audio_video_group = {
+	.ui_name = "Audio/Video",
 	.obj_list = (const struct sm_object *[]) {
-		&bluetooth_rtd3,
-		&memory_speed,
-		&power_profile,
+		&microphone,
+		&webcam,
 		NULL
 	},
 };
 
-static struct sm_obj_form processor_group = {
-	.ui_name = "Processor",
+static struct sm_obj_form battery_group = {
+	.ui_name = "Battery",
 	.obj_list = (const struct sm_object *[]) {
-		&me_state,
-		&me_state_counter,
-		&s0ix_enable,
-		&vtd,
-		NULL
-	},
-};
-
-static struct sm_obj_form power_group = {
-	.ui_name = "Power",
-	.obj_list = (const struct sm_object *[]) {
-		&max_charge,
 		#if CONFIG(EC_STARLABS_CHARGING_SPEED)
 		&charging_speed,
 		#endif
-		&power_led,
-		&charge_led,
+		&max_charge,
 		&power_on_after_fail_bool,
 		NULL
 	},
 };
 
-static struct sm_obj_form devices_group = {
-	.ui_name = "Devices",
+static struct sm_obj_form debug_group = {
+	.ui_name = "Debug",
+	.obj_list = (const struct sm_object *[]) {
+		&debug_level,
+		NULL
+	},
+};
+
+static struct sm_obj_form display_group = {
+	.ui_name = "Display",
 	.obj_list = (const struct sm_object *[]) {
 		&accelerometer,
-		&bluetooth,
-		&card_reader,
 		&display_native_res,
+		&touchscreen,
+		NULL
+	},
+};
+
+static struct sm_obj_form io_expansion_group = {
+	.ui_name = "I/O / Expansion",
+	.obj_list = (const struct sm_object *[]) {
+		&card_reader,
+		NULL
+	},
+};
+
+static struct sm_obj_form leds_group = {
+	.ui_name = "LEDs",
+	.obj_list = (const struct sm_object *[]) {
+		&charge_led,
+		&power_led,
+		NULL
+	},
+};
+
+static struct sm_obj_form pcie_power_management_group = {
+	.ui_name = "PCIe Power Management",
+	.obj_list = (const struct sm_object *[]) {
+		#if CONFIG(SOC_INTEL_COMMON_BLOCK_ASPM)
+		&pciexp_aspm,
+		&pciexp_clk_pm,
+		&pciexp_l1ss,
+		#endif
+		NULL
+	},
+};
+
+static struct sm_obj_form performance_group = {
+	.ui_name = "Performance",
+	.obj_list = (const struct sm_object *[]) {
 		#if CONFIG(SOC_INTEL_TIGERLAKE) || CONFIG(SOC_INTEL_ALDERLAKE) || CONFIG(SOC_INTEL_RAPTORLAKE)
 		&gna,
 		#endif
-		#if CONFIG(EC_STARLABS_LID_SWITCH)
-		&lid_switch,
-		#endif
-		&microphone,
-		&touchscreen,
-		&webcam,
-		&wifi,
+		&memory_speed,
+		&power_profile,
 		NULL
 	},
 };
@@ -87,38 +111,54 @@ static struct sm_obj_form security_group = {
 	.obj_list = (const struct sm_object *[]) {
 		&bios_lock,
 		&intel_tme,
+		&me_state,
+		&me_state_counter,
 		NULL
 	},
 };
 
-static struct sm_obj_form pci_group = {
-	.ui_name = "PCI",
+static struct sm_obj_form suspend_lid_group = {
+	.ui_name = "Suspend & Lid",
 	.obj_list = (const struct sm_object *[]) {
-		#if CONFIG(SOC_INTEL_COMMON_BLOCK_ASPM)
-		&pciexp_clk_pm,
-		&pciexp_aspm,
-		&pciexp_l1ss,
+		#if CONFIG(EC_STARLABS_LID_SWITCH)
+		&lid_switch,
 		#endif
+		&s0ix_enable,
 		NULL
 	},
 };
 
-static struct sm_obj_form coreboot_group = {
-	.ui_name = "coreboot",
+static struct sm_obj_form virtualization_group = {
+	.ui_name = "Virtualization",
 	.obj_list = (const struct sm_object *[]) {
-		&debug_level,
+		&vtd,
+		NULL
+	},
+};
+
+static struct sm_obj_form wireless_group = {
+	.ui_name = "Wireless",
+	.obj_list = (const struct sm_object *[]) {
+		&bluetooth,
+		&bluetooth_rtd3,
+		&wifi,
 		NULL
 	},
 };
 
 static struct sm_obj_form *sm_root[] = {
+	&audio_video_group,
+	&battery_group,
+	&debug_group,
+	&display_group,
+	&io_expansion_group,
+	&leds_group,
+	&pcie_power_management_group,
 	&performance_group,
-	&processor_group,
-	&power_group,
-	&devices_group,
 	&security_group,
-	&pci_group,
-	&coreboot_group,
+	&suspend_lid_group,
+	&virtualization_group,
+	&wireless_group,
 	NULL
 };
 

From 582d86777a42c291714354d8c0d9c7a886a8bb6f Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Thu, 18 Dec 2025 17:59:00 -0600
Subject: [PATCH 3279/3886] mb/google/{brya,dedede}: Add MIPI camera
 sensor_name where available

Add the corresponding sensor_name value used by the Windows drivers for
each camera sensor. Update the name used for Redrix based on testing.
This value is not used by ChromeOS/Linux.

TEST=build/boot Win11 on redrix, magolor. Verify IPU/MIPI camera works
properly using available drivers.

Change-Id: Id4fba3667f9497f71787e504bf244d54e433e552
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91107
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
---
 src/mainboard/google/brya/variants/anraggar/overridetree.cb  | 1 +
 src/mainboard/google/brya/variants/craask/overridetree.cb    | 2 ++
 src/mainboard/google/brya/variants/meliks/overridetree.cb    | 1 +
 src/mainboard/google/brya/variants/nivviks/overridetree.cb   | 1 +
 src/mainboard/google/brya/variants/pirrha/overridetree.cb    | 1 +
 src/mainboard/google/brya/variants/pujjolo/overridetree.cb   | 1 +
 src/mainboard/google/brya/variants/redrix/overridetree.cb    | 2 +-
 src/mainboard/google/brya/variants/redrix4es/overridetree.cb | 1 +
 src/mainboard/google/brya/variants/riven/overridetree.cb     | 2 ++
 src/mainboard/google/brya/variants/teliks/overridetree.cb    | 1 +
 src/mainboard/google/brya/variants/telith/overridetree.cb    | 1 +
 src/mainboard/google/brya/variants/vell/overridetree.cb      | 1 +
 src/mainboard/google/brya/variants/xivu/overridetree.cb      | 1 +
 src/mainboard/google/brya/variants/yaviks/overridetree.cb    | 1 +
 src/mainboard/google/brya/variants/yavilla/overridetree.cb   | 1 +
 src/mainboard/google/brya/variants/zydron/overridetree.cb    | 2 ++
 src/mainboard/google/dedede/variants/bugzzy/overridetree.cb  | 1 +
 src/mainboard/google/dedede/variants/drawcia/overridetree.cb | 1 +
 src/mainboard/google/dedede/variants/haboki/overridetree.cb  | 1 +
 src/mainboard/google/dedede/variants/lalala/overridetree.cb  | 1 +
 src/mainboard/google/dedede/variants/magolor/overridetree.cb | 1 +
 src/mainboard/google/dedede/variants/storo/overridetree.cb   | 1 +
 22 files changed, 25 insertions(+), 1 deletion(-)

diff --git a/src/mainboard/google/brya/variants/anraggar/overridetree.cb b/src/mainboard/google/brya/variants/anraggar/overridetree.cb
index 5b71e31795..afb1eb468d 100644
--- a/src/mainboard/google/brya/variants/anraggar/overridetree.cb
+++ b/src/mainboard/google/brya/variants/anraggar/overridetree.cb
@@ -267,6 +267,7 @@ chip soc/intel/alderlake
 				register "acpi_uid" = "0"
 				register "acpi_name" = ""CAM0""
 				register "chip_name" = ""Ov 13b10 Camera""
+				register "sensor_name" = ""09B13U""
 				register "device_type" = "INTEL_ACPI_CAMERA_SENSOR"
 
 				register "ssdb.lanes_used" = "4"
diff --git a/src/mainboard/google/brya/variants/craask/overridetree.cb b/src/mainboard/google/brya/variants/craask/overridetree.cb
index 86a5cfc465..71c5651262 100644
--- a/src/mainboard/google/brya/variants/craask/overridetree.cb
+++ b/src/mainboard/google/brya/variants/craask/overridetree.cb
@@ -477,6 +477,7 @@ chip soc/intel/alderlake
 				register "acpi_uid" = "0"
 				register "acpi_name" = ""CAM0""
 				register "chip_name" = ""Ov 5675 Camera""
+				register "sensor_name" = ""CJFLE39""
 				register "device_type" = "INTEL_ACPI_CAMERA_SENSOR"
 
 				register "ssdb.lanes_used" = "2"
@@ -524,6 +525,7 @@ chip soc/intel/alderlake
 				register "acpi_uid" = "0"
 				register "acpi_name" = ""CAM0""
 				register "chip_name" = ""Ov 8856 Camera""
+				register "sensor_name" = ""CJAJ813""
 				register "device_type" = "INTEL_ACPI_CAMERA_SENSOR"
 				register "has_power_resource" = "true"
 				register "max_dstate_for_probe" = "ACPI_DEVICE_SLEEP_D3_COLD"
diff --git a/src/mainboard/google/brya/variants/meliks/overridetree.cb b/src/mainboard/google/brya/variants/meliks/overridetree.cb
index 1e11eafa90..4b4947765e 100644
--- a/src/mainboard/google/brya/variants/meliks/overridetree.cb
+++ b/src/mainboard/google/brya/variants/meliks/overridetree.cb
@@ -261,6 +261,7 @@ chip soc/intel/alderlake
 				register "acpi_uid" = "0"
 				register "acpi_name" = ""CAM0""
 				register "chip_name" = ""Ov 8856 Camera""
+				register "sensor_name" = ""CJAJ813""
 				register "device_type" = "INTEL_ACPI_CAMERA_SENSOR"
 
 				register "ssdb.lanes_used" = "4"
diff --git a/src/mainboard/google/brya/variants/nivviks/overridetree.cb b/src/mainboard/google/brya/variants/nivviks/overridetree.cb
index b90cda1782..db860c434d 100644
--- a/src/mainboard/google/brya/variants/nivviks/overridetree.cb
+++ b/src/mainboard/google/brya/variants/nivviks/overridetree.cb
@@ -386,6 +386,7 @@ chip soc/intel/alderlake
 				register "acpi_uid" = "0"
 				register "acpi_name" = ""CAM0""
 				register "chip_name" = ""Ov 5675 Camera""
+				register "sensor_name" = ""CJFLE39""
 				register "device_type" = "INTEL_ACPI_CAMERA_SENSOR"
 
 				register "ssdb.lanes_used" = "2"
diff --git a/src/mainboard/google/brya/variants/pirrha/overridetree.cb b/src/mainboard/google/brya/variants/pirrha/overridetree.cb
index 561ab72473..58f83b5b21 100644
--- a/src/mainboard/google/brya/variants/pirrha/overridetree.cb
+++ b/src/mainboard/google/brya/variants/pirrha/overridetree.cb
@@ -300,6 +300,7 @@ chip soc/intel/alderlake
 				register "acpi_uid" = "0"
 				register "acpi_name" = ""CAM0""
 				register "chip_name" = ""Ov 8856 Camera""
+				register "sensor_name" = ""CJAJ813""
 				register "device_type" = "INTEL_ACPI_CAMERA_SENSOR"
 
 				register "ssdb.lanes_used" = "4"
diff --git a/src/mainboard/google/brya/variants/pujjolo/overridetree.cb b/src/mainboard/google/brya/variants/pujjolo/overridetree.cb
index 738f1cb31e..57fbfaf7f9 100644
--- a/src/mainboard/google/brya/variants/pujjolo/overridetree.cb
+++ b/src/mainboard/google/brya/variants/pujjolo/overridetree.cb
@@ -388,6 +388,7 @@ chip soc/intel/alderlake
 				register "acpi_uid" = "0"
 				register "acpi_name" = ""CAM0""
 				register "chip_name" = ""Ov 8856 Camera""
+				register "sensor_name" = ""CJAJ813""
 				register "device_type" = "INTEL_ACPI_CAMERA_SENSOR"
 				register "has_power_resource" = "1"
 				register "max_dstate_for_probe" = "ACPI_DEVICE_SLEEP_D3_COLD"
diff --git a/src/mainboard/google/brya/variants/redrix/overridetree.cb b/src/mainboard/google/brya/variants/redrix/overridetree.cb
index 3bc331129a..4410e49f20 100644
--- a/src/mainboard/google/brya/variants/redrix/overridetree.cb
+++ b/src/mainboard/google/brya/variants/redrix/overridetree.cb
@@ -425,7 +425,7 @@ chip soc/intel/alderlake
 				register "acpi_uid" = "0"
 				register "acpi_name" = ""CAM0""
 				register "chip_name" = ""Ov 5675 Camera""
-				register "sensor_name" = ""S5VM17""
+				register "sensor_name" = ""CJFLE39""
 				register "device_type" = "INTEL_ACPI_CAMERA_SENSOR"
 
 				register "ssdb.lanes_used" = "2"
diff --git a/src/mainboard/google/brya/variants/redrix4es/overridetree.cb b/src/mainboard/google/brya/variants/redrix4es/overridetree.cb
index 4ebc017eab..c10a37acbf 100644
--- a/src/mainboard/google/brya/variants/redrix4es/overridetree.cb
+++ b/src/mainboard/google/brya/variants/redrix4es/overridetree.cb
@@ -347,6 +347,7 @@ chip soc/intel/alderlake
 				register "acpi_uid" = "0"
 				register "acpi_name" = ""CAM0""
 				register "chip_name" = ""Ov 5675 Camera""
+				register "sensor_name" = ""CJFLE39""
 				register "device_type" = "INTEL_ACPI_CAMERA_SENSOR"
 
 				register "ssdb.lanes_used" = "2"
diff --git a/src/mainboard/google/brya/variants/riven/overridetree.cb b/src/mainboard/google/brya/variants/riven/overridetree.cb
index 60111e5af2..acaffef226 100644
--- a/src/mainboard/google/brya/variants/riven/overridetree.cb
+++ b/src/mainboard/google/brya/variants/riven/overridetree.cb
@@ -342,6 +342,7 @@ chip soc/intel/alderlake
 				register "acpi_uid" = "0"
 				register "acpi_name" = ""CAM0""
 				register "chip_name" = ""Ov 5675 Camera""
+				register "sensor_name" = ""CJFLE39""
 				register "device_type" = "INTEL_ACPI_CAMERA_SENSOR"
 
 				register "ssdb.lanes_used" = "2"
@@ -391,6 +392,7 @@ chip soc/intel/alderlake
 				register "acpi_uid" = "0"
 				register "acpi_name" = ""CAM0""
 				register "chip_name" = ""Ov 8856 Camera""
+				register "sensor_name" = ""CJAJ813""
 				register "device_type" = "INTEL_ACPI_CAMERA_SENSOR"
 				register "has_power_resource" = "true"
 				register "max_dstate_for_probe" = "ACPI_DEVICE_SLEEP_D3_COLD"
diff --git a/src/mainboard/google/brya/variants/teliks/overridetree.cb b/src/mainboard/google/brya/variants/teliks/overridetree.cb
index 9e4f90c0ab..4197c80340 100644
--- a/src/mainboard/google/brya/variants/teliks/overridetree.cb
+++ b/src/mainboard/google/brya/variants/teliks/overridetree.cb
@@ -284,6 +284,7 @@ chip soc/intel/alderlake
 				register "acpi_uid" = "0"
 				register "acpi_name" = ""CAM0""
 				register "chip_name" = ""Ov 13b10 Camera""
+				register "sensor_name" = ""09B13U""
 				register "device_type" = "INTEL_ACPI_CAMERA_SENSOR"
 
 				register "ssdb.lanes_used" = "4"
diff --git a/src/mainboard/google/brya/variants/telith/overridetree.cb b/src/mainboard/google/brya/variants/telith/overridetree.cb
index 1a6982d1d2..211b7b1e80 100644
--- a/src/mainboard/google/brya/variants/telith/overridetree.cb
+++ b/src/mainboard/google/brya/variants/telith/overridetree.cb
@@ -410,6 +410,7 @@ chip soc/intel/alderlake
 				register "acpi_uid" = "0"
 				register "acpi_name" = ""CAM0""
 				register "chip_name" = ""Ov 13b10 Camera""
+				register "sensor_name" = ""09B13U""
 				register "device_type" = "INTEL_ACPI_CAMERA_SENSOR"
 
 				register "ssdb.lanes_used" = "4"
diff --git a/src/mainboard/google/brya/variants/vell/overridetree.cb b/src/mainboard/google/brya/variants/vell/overridetree.cb
index 7fa68933df..6bf7c63328 100644
--- a/src/mainboard/google/brya/variants/vell/overridetree.cb
+++ b/src/mainboard/google/brya/variants/vell/overridetree.cb
@@ -341,6 +341,7 @@ chip soc/intel/alderlake
 				register "acpi_uid" = "0"
 				register "acpi_name" = ""CAM0""
 				register "chip_name" = ""Ov 8856 Camera""
+				register "sensor_name" = ""CJAJ813""
 				register "device_type" = "INTEL_ACPI_CAMERA_SENSOR"
 				register "has_power_resource" = "true"
 
diff --git a/src/mainboard/google/brya/variants/xivu/overridetree.cb b/src/mainboard/google/brya/variants/xivu/overridetree.cb
index 364f720374..a367761ddf 100644
--- a/src/mainboard/google/brya/variants/xivu/overridetree.cb
+++ b/src/mainboard/google/brya/variants/xivu/overridetree.cb
@@ -250,6 +250,7 @@ chip soc/intel/alderlake
 				register "acpi_uid" = "0"
 				register "acpi_name" = ""CAM0""
 				register "chip_name" = ""Ov 8856 Camera""
+				register "sensor_name" = ""CJAJ813""
 				register "device_type" = "INTEL_ACPI_CAMERA_SENSOR"
 
 				register "ssdb.lanes_used" = "4"
diff --git a/src/mainboard/google/brya/variants/yaviks/overridetree.cb b/src/mainboard/google/brya/variants/yaviks/overridetree.cb
index 334b2bc619..31e89fa88c 100644
--- a/src/mainboard/google/brya/variants/yaviks/overridetree.cb
+++ b/src/mainboard/google/brya/variants/yaviks/overridetree.cb
@@ -327,6 +327,7 @@ chip soc/intel/alderlake
 				register "acpi_uid" = "0"
 				register "acpi_name" = ""CAM0""
 				register "chip_name" = ""Ov 8856 Camera""
+				register "sensor_name" = ""CJAJ813""
 				register "device_type" = "INTEL_ACPI_CAMERA_SENSOR"
 				register "has_power_resource" = "true"
 
diff --git a/src/mainboard/google/brya/variants/yavilla/overridetree.cb b/src/mainboard/google/brya/variants/yavilla/overridetree.cb
index 8ed08cc0d3..ce890af476 100644
--- a/src/mainboard/google/brya/variants/yavilla/overridetree.cb
+++ b/src/mainboard/google/brya/variants/yavilla/overridetree.cb
@@ -367,6 +367,7 @@ chip soc/intel/alderlake
 				register "acpi_uid" = "0"
 				register "acpi_name" = ""CAM0""
 				register "chip_name" = ""Ov 8856 Camera""
+				register "sensor_name" = ""CJAJ813""
 				register "device_type" = "INTEL_ACPI_CAMERA_SENSOR"
 				register "has_power_resource" = "true"
 				register "max_dstate_for_probe" = "ACPI_DEVICE_SLEEP_D3_COLD"
diff --git a/src/mainboard/google/brya/variants/zydron/overridetree.cb b/src/mainboard/google/brya/variants/zydron/overridetree.cb
index a632d36294..f87f9f3f16 100644
--- a/src/mainboard/google/brya/variants/zydron/overridetree.cb
+++ b/src/mainboard/google/brya/variants/zydron/overridetree.cb
@@ -298,6 +298,7 @@ chip soc/intel/alderlake
 				register "acpi_uid" = "0"
 				register "acpi_name" = ""CAM0""
 				register "chip_name" = ""Ov 2740 Camera""
+				register "sensor_name" = ""CJFLE23""
 				register "device_type" = "INTEL_ACPI_CAMERA_SENSOR"
 				register "has_power_resource" = "true"
 
@@ -341,6 +342,7 @@ chip soc/intel/alderlake
 				register "acpi_uid" = "0"
 				register "acpi_name" = ""CAM0""
 				register "chip_name" = ""Hi-556 Camera""
+				register "sensor_name" = ""CJFLE25""
 				register "device_type" = "INTEL_ACPI_CAMERA_SENSOR"
 				register "has_power_resource" = "true"
 
diff --git a/src/mainboard/google/dedede/variants/bugzzy/overridetree.cb b/src/mainboard/google/dedede/variants/bugzzy/overridetree.cb
index bf8fbbe913..64e3214567 100644
--- a/src/mainboard/google/dedede/variants/bugzzy/overridetree.cb
+++ b/src/mainboard/google/dedede/variants/bugzzy/overridetree.cb
@@ -258,6 +258,7 @@ chip soc/intel/jasperlake
 				register "acpi_uid" = "0"
 				register "acpi_name" = ""CAM1""
 				register "chip_name" = ""Ov 8856 Camera""
+				register "sensor_name" = ""CJAJ813""
 				register "device_type" = "INTEL_ACPI_CAMERA_SENSOR"
 
 				register "ssdb.lanes_used" = "4"
diff --git a/src/mainboard/google/dedede/variants/drawcia/overridetree.cb b/src/mainboard/google/dedede/variants/drawcia/overridetree.cb
index a2c5bb0c02..1900e7e4cb 100644
--- a/src/mainboard/google/dedede/variants/drawcia/overridetree.cb
+++ b/src/mainboard/google/dedede/variants/drawcia/overridetree.cb
@@ -318,6 +318,7 @@ chip soc/intel/jasperlake
 				register "acpi_uid" = "0"
 				register "acpi_name" = ""CAM1""
 				register "chip_name" = ""Ov 8856 Camera""
+				register "sensor_name" = ""CJAJ813""
 				register "device_type" = "INTEL_ACPI_CAMERA_SENSOR"
 
 				register "ssdb.lanes_used" = "4"
diff --git a/src/mainboard/google/dedede/variants/haboki/overridetree.cb b/src/mainboard/google/dedede/variants/haboki/overridetree.cb
index 3eae64536b..7377f904c2 100644
--- a/src/mainboard/google/dedede/variants/haboki/overridetree.cb
+++ b/src/mainboard/google/dedede/variants/haboki/overridetree.cb
@@ -232,6 +232,7 @@ chip soc/intel/jasperlake
 				register "acpi_uid" = "0"
 				register "acpi_name" = ""CAM1""
 				register "chip_name" = ""Ov 8856 Camera""
+				register "sensor_name" = ""CJAJ813""
 				register "device_type" = "INTEL_ACPI_CAMERA_SENSOR"
 
 				register "ssdb.lanes_used" = "4"
diff --git a/src/mainboard/google/dedede/variants/lalala/overridetree.cb b/src/mainboard/google/dedede/variants/lalala/overridetree.cb
index a680eed1e0..e703d5e799 100644
--- a/src/mainboard/google/dedede/variants/lalala/overridetree.cb
+++ b/src/mainboard/google/dedede/variants/lalala/overridetree.cb
@@ -230,6 +230,7 @@ chip soc/intel/jasperlake
 				register "acpi_uid" = "0"
 				register "acpi_name" = ""CAM0""
 				register "chip_name" = ""Ov 5675 Camera""
+				register "sensor_name" = ""CJFLE39""
 				register "device_type" = "INTEL_ACPI_CAMERA_SENSOR"
 
 				register "ssdb.lanes_used" = "2"
diff --git a/src/mainboard/google/dedede/variants/magolor/overridetree.cb b/src/mainboard/google/dedede/variants/magolor/overridetree.cb
index 56116f7b5f..baf24b9436 100644
--- a/src/mainboard/google/dedede/variants/magolor/overridetree.cb
+++ b/src/mainboard/google/dedede/variants/magolor/overridetree.cb
@@ -364,6 +364,7 @@ chip soc/intel/jasperlake
 				register "acpi_uid" = "0"
 				register "acpi_name" = ""CAM0""
 				register "chip_name" = ""Ov 5675 Camera""
+				register "sensor_name" = ""CJFLE39""
 				register "device_type" = "INTEL_ACPI_CAMERA_SENSOR"
 
 				register "ssdb.lanes_used" = "2"
diff --git a/src/mainboard/google/dedede/variants/storo/overridetree.cb b/src/mainboard/google/dedede/variants/storo/overridetree.cb
index c8c83634a2..5469ea4808 100644
--- a/src/mainboard/google/dedede/variants/storo/overridetree.cb
+++ b/src/mainboard/google/dedede/variants/storo/overridetree.cb
@@ -238,6 +238,7 @@ chip soc/intel/jasperlake
 				register "acpi_uid" = "0"
 				register "acpi_name" = ""CAM1""
 				register "chip_name" = ""Ov 8856 Camera""
+				register "sensor_name" = ""CJAJ813""
 				register "device_type" = "INTEL_ACPI_CAMERA_SENSOR"
 
 				register "ssdb.lanes_used" = "4"

From a8c7ee02355395d7c74ce25d336f5576a9c40a50 Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Thu, 5 Feb 2026 09:09:41 -0600
Subject: [PATCH 3280/3886] mb/google/brya: Change HID for Ov 13b10 MIPI camera
 sensor

Change the HID used from OVTIDB10 to OVTI13B1 for proper attachment
under Windows. Linux/ChromeOS don't use the HID, and so are unaffected
by the change.

TEST=build/boot Win11 on Teliks, verify MIPI camera driver loads
properly.

Change-Id: Ia81bd8cfaf6bb160f4f18214edccdf425d22cf6f
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91108
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/google/brya/variants/anraggar/overridetree.cb | 2 +-
 src/mainboard/google/brya/variants/teliks/overridetree.cb   | 2 +-
 src/mainboard/google/brya/variants/telith/overridetree.cb   | 2 +-
 3 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/src/mainboard/google/brya/variants/anraggar/overridetree.cb b/src/mainboard/google/brya/variants/anraggar/overridetree.cb
index afb1eb468d..c9500476e9 100644
--- a/src/mainboard/google/brya/variants/anraggar/overridetree.cb
+++ b/src/mainboard/google/brya/variants/anraggar/overridetree.cb
@@ -263,7 +263,7 @@ chip soc/intel/alderlake
 		end
 		device ref i2c2 on
 			chip drivers/intel/mipi_camera
-				register "acpi_hid" = ""OVTIDB10""
+				register "acpi_hid" = ""OVTI13B1""
 				register "acpi_uid" = "0"
 				register "acpi_name" = ""CAM0""
 				register "chip_name" = ""Ov 13b10 Camera""
diff --git a/src/mainboard/google/brya/variants/teliks/overridetree.cb b/src/mainboard/google/brya/variants/teliks/overridetree.cb
index 4197c80340..b3b8eb500a 100644
--- a/src/mainboard/google/brya/variants/teliks/overridetree.cb
+++ b/src/mainboard/google/brya/variants/teliks/overridetree.cb
@@ -280,7 +280,7 @@ chip soc/intel/alderlake
 		end
 		device ref i2c2 on
 			chip drivers/intel/mipi_camera
-				register "acpi_hid" = ""OVTIDB10""
+				register "acpi_hid" = ""OVTI13B1""
 				register "acpi_uid" = "0"
 				register "acpi_name" = ""CAM0""
 				register "chip_name" = ""Ov 13b10 Camera""
diff --git a/src/mainboard/google/brya/variants/telith/overridetree.cb b/src/mainboard/google/brya/variants/telith/overridetree.cb
index 211b7b1e80..a071a16df0 100644
--- a/src/mainboard/google/brya/variants/telith/overridetree.cb
+++ b/src/mainboard/google/brya/variants/telith/overridetree.cb
@@ -406,7 +406,7 @@ chip soc/intel/alderlake
 		end
 		device ref i2c2 on
 			chip drivers/intel/mipi_camera
-				register "acpi_hid" = ""OVTIDB10""
+				register "acpi_hid" = ""OVTI13B1""
 				register "acpi_uid" = "0"
 				register "acpi_name" = ""CAM0""
 				register "chip_name" = ""Ov 13b10 Camera""

From c463b7761e2592f46c5c7f8bdf5e680c7f1fae22 Mon Sep 17 00:00:00 2001
From: Mario Scheithauer <mario.scheithauer@siemens.com>
Date: Tue, 27 Jan 2026 10:20:16 +0100
Subject: [PATCH 3281/3886] soc/intel/ehl: Add PCIe High Speed I/O ModPHY
 support

This patch provides support for board-specific fine-tuning of PCIe root
ports.

The following parameters can be adjusted.

PchPcieHsioTxGen1DownscaleAmp:
- Adjust the transmitter driver strength and its output swing for Gen 1
  PCIe devices
PchPcieHsioTxGen2DownscaleAmp:
- Adjust the transmitter driver strength and its output swing for Gen 2
  PCIe devices
PchPcieHsioTxGen3DownscaleAmp:
- Adjust the transmitter driver strength and its output swing for Gen 3
  PCIe devices
PchPcieHsioTxGen1DeEmph:
- Adjust or fine-tune the amount for PCIe Gen 1 devices by which the
  output is de-emphasized for -3.5dB mode
PchPcieHsioTxGen2DeEmph3p5:
- Adjust or fine-tune the amount for PCIe Gen 2 devices by which the
  output is de-emphasized for -3.5dB mode
PchPcieHsioTxGen2DeEmph6p0:
- Adjust or fine-tune the amount for PCIe Gen 2 devices by which the
  output is de-emphasized for -6.0dB mode

Change-Id: I7b51de2b7f75e15d902e471a19b8b29166ddfb48
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90944
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
---
 src/soc/intel/elkhartlake/chip.h              |  3 ++
 .../intel/elkhartlake/romstage/fsp_params.c   | 36 +++++++++++++++++++
 2 files changed, 39 insertions(+)

diff --git a/src/soc/intel/elkhartlake/chip.h b/src/soc/intel/elkhartlake/chip.h
index d4bb04ff75..e7593f8d14 100644
--- a/src/soc/intel/elkhartlake/chip.h
+++ b/src/soc/intel/elkhartlake/chip.h
@@ -238,6 +238,9 @@ struct soc_intel_elkhartlake_config {
 	/* PCIe RP L1 substate */
 	enum L1_substates_control PcieRpL1Substates[CONFIG_MAX_ROOT_PORTS];
 
+	/* PCIe ModPhy related */
+	struct pcie_modphy_config pcie_mp_cfg[CONFIG_MAX_ROOT_PORTS];
+
 	/* PCIe root port maximum payload size, default is set to 128 bytes. */
 	enum {
 		RpMaxPayload_128,
diff --git a/src/soc/intel/elkhartlake/romstage/fsp_params.c b/src/soc/intel/elkhartlake/romstage/fsp_params.c
index d05a94d2aa..71bd473ca8 100644
--- a/src/soc/intel/elkhartlake/romstage/fsp_params.c
+++ b/src/soc/intel/elkhartlake/romstage/fsp_params.c
@@ -22,6 +22,8 @@ enum {
 static void soc_memory_init_params(FSP_M_CONFIG *m_cfg,
 		const struct soc_intel_elkhartlake_config *config)
 {
+	size_t i;
+
 	/*
 	 * If IGD is enabled, set IGD stolen size to 60MB.
 	 * Otherwise, skip IGD init in FSP.
@@ -33,6 +35,40 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg,
 	m_cfg->SaGv = config->SaGv;
 	m_cfg->RMT = config->RMT;
 
+	/* PCIe ModPhy configuration */
+	for (i = 0; i < CONFIG_MAX_ROOT_PORTS; i++) {
+		if (config->pcie_mp_cfg[i].tx_gen1_downscale_amp_override) {
+			m_cfg->PchPcieHsioTxGen1DownscaleAmpEnable[i] = 1;
+			m_cfg->PchPcieHsioTxGen1DownscaleAmp[i] =
+					config->pcie_mp_cfg[i].tx_gen1_downscale_amp;
+		}
+		if (config->pcie_mp_cfg[i].tx_gen2_downscale_amp_override) {
+			m_cfg->PchPcieHsioTxGen2DownscaleAmpEnable[i] = 1;
+			m_cfg->PchPcieHsioTxGen2DownscaleAmp[i] =
+					config->pcie_mp_cfg[i].tx_gen2_downscale_amp;
+		}
+		if (config->pcie_mp_cfg[i].tx_gen3_downscale_amp_override) {
+			m_cfg->PchPcieHsioTxGen3DownscaleAmpEnable[i] = 1;
+			m_cfg->PchPcieHsioTxGen3DownscaleAmp[i] =
+					config->pcie_mp_cfg[i].tx_gen3_downscale_amp;
+		}
+		if (config->pcie_mp_cfg[i].tx_gen1_de_emph) {
+			m_cfg->PchPcieHsioTxGen1DeEmphEnable[i] = 1;
+			m_cfg->PchPcieHsioTxGen1DeEmph[i] =
+					config->pcie_mp_cfg[i].tx_gen1_de_emph;
+		}
+		if (config->pcie_mp_cfg[i].tx_gen2_de_emph_3p5) {
+			m_cfg->PchPcieHsioTxGen2DeEmph3p5Enable[i] = 1;
+			m_cfg->PchPcieHsioTxGen2DeEmph3p5[i] =
+					config->pcie_mp_cfg[i].tx_gen2_de_emph_3p5;
+		}
+		if (config->pcie_mp_cfg[i].tx_gen2_de_emph_6p0) {
+			m_cfg->PchPcieHsioTxGen2DeEmph6p0Enable[i] = 1;
+			m_cfg->PchPcieHsioTxGen2DeEmph6p0[i] =
+					config->pcie_mp_cfg[i].tx_gen2_de_emph_6p0;
+		}
+	}
+
 	m_cfg->PcieRpEnableMask = pcie_rp_enable_mask(pch_rp_groups);
 
 	FSP_ARRAY_LOAD(m_cfg->PcieClkSrcUsage, config->PcieClkSrcUsage);

From b117179256a192c2229ae36683ac5256e24e6a92 Mon Sep 17 00:00:00 2001
From: Mario Scheithauer <mario.scheithauer@siemens.com>
Date: Tue, 27 Jan 2026 10:21:22 +0100
Subject: [PATCH 3282/3886] mb/siemens/{mc_ehl2,mc_ehl5}: Fine-tune Gen1 TX
 Output De-Emphasis for PCIe RP #7

On these two mainboards, a Gen1 device is connected on PCIe RP #7.
Measurements have shown that a value of -0.137 dB yields an optimal eye
TX mask test.

BUG=none
TEST=Eye TX mask test for PCIe RP #7 passed using an oscilloscope

Change-Id: I2d95e50473e39c325531c6071773a6a3cbb3a1a0
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90945
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb | 5 +++++
 src/mainboard/siemens/mc_ehl/variants/mc_ehl5/devicetree.cb | 5 +++++
 2 files changed, 10 insertions(+)

diff --git a/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb b/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb
index 4a7a997446..c1ebf7b5be 100644
--- a/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb
+++ b/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb
@@ -62,6 +62,11 @@ chip soc/intel/elkhartlake
 	register "PcieRpLtrDisable[1]" = "true"
 	register "PcieRpLtrDisable[6]" = "true"
 
+	# Adjust TX Output De-Emphasis for PCIe RP7 to -0.137 dB
+	register "pcie_mp_cfg[6]" = "{
+		.tx_gen1_de_emph = 0x3f,
+	}"
+
 	# Storage (SDCARD/EMMC) related UPDs
 	register "ScsEmmcHs400Enabled" = "0"
 	register "ScsEmmcDdr50Enabled" = "1"
diff --git a/src/mainboard/siemens/mc_ehl/variants/mc_ehl5/devicetree.cb b/src/mainboard/siemens/mc_ehl/variants/mc_ehl5/devicetree.cb
index bcd76cb991..5fca41cd4b 100644
--- a/src/mainboard/siemens/mc_ehl/variants/mc_ehl5/devicetree.cb
+++ b/src/mainboard/siemens/mc_ehl/variants/mc_ehl5/devicetree.cb
@@ -62,6 +62,11 @@ chip soc/intel/elkhartlake
 	register "PcieRpLtrDisable[1]" = "true"
 	register "PcieRpLtrDisable[6]" = "true"
 
+	# Adjust TX Output De-Emphasis for PCIe RP7 to -0.137 dB
+	register "pcie_mp_cfg[6]" = "{
+		.tx_gen1_de_emph = 0x3f,
+	}"
+
 	# Storage (SDCARD/EMMC) related UPDs
 	register "ScsEmmcHs400Enabled" = "0"
 	register "ScsEmmcDdr50Enabled" = "1"

From d23bd33161278b03e571d87704467f11b4bc562c Mon Sep 17 00:00:00 2001
From: "Evie (Ivi) Ballou" <iviballou@gmail.com>
Date: Sun, 1 Feb 2026 03:08:06 +0200
Subject: [PATCH 3283/3886] acpi/dsdt_top.asl: Move `RBUF` out of the _CRS
 method

This solves the remark:
```
dsdt.asl     28:    Name (RBUF, ResourceTemplate ()
Remark   2173 -             ^ Creation of named objects within a method is highly inefficient, use globals or method local variables instead (\_SB.PERC._CRS)
```

Change-Id: Ifff2678e351cf6d92a7fba5d3cf64413e15393c0
Signed-off-by: Evie (Ivi) Ballou <iviballou@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91037
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
---
 src/acpi/dsdt_top.asl | 28 ++++++++++++++--------------
 1 file changed, 14 insertions(+), 14 deletions(-)

diff --git a/src/acpi/dsdt_top.asl b/src/acpi/dsdt_top.asl
index 7539f00e57..a99d80bbf4 100644
--- a/src/acpi/dsdt_top.asl
+++ b/src/acpi/dsdt_top.asl
@@ -57,22 +57,22 @@ Scope(\_SB) {
 	Device (PERC)	// PCI ECAM Resource Consumption
 	{
 		Name (_HID, EisaId("PNP0C02"))
+		Name (RBUF, ResourceTemplate ()
+		{
+			QWordMemory (ResourceConsumer, PosDecode, MinFixed, MaxFixed,
+				NonCacheable, ReadWrite,
+				0x0000000000000000, // Granularity
+				0x0000000000000000, // _MIN
+				0x0000000000000001, // _MAX
+				0x0000000000000000, // Translation
+				0x0000000000000002, // _Len
+				,, _Y00, AddressRangeMemory, TypeStatic)
+		})
 		Method (_CRS, 0, Serialized)
 		{
-			Name (RBUF, ResourceTemplate ()
-			{
-				QWordMemory (ResourceConsumer, PosDecode, MinFixed, MaxFixed,
-				    NonCacheable, ReadWrite,
-				    0x0000000000000000, // Granularity
-				    0x0000000000000000, // _MIN
-				    0x0000000000000001, // _MAX
-				    0x0000000000000000, // Translation
-				    0x0000000000000002, // _Len
-				    ,, _Y00, AddressRangeMemory, TypeStatic)
-			})
-			CreateQWordField (RBUF, \_SB.PERC._CRS._Y00._MIN, MIN1)
-			CreateQWordField (RBUF, \_SB.PERC._CRS._Y00._MAX, MAX1)
-			CreateQWordField (RBUF, \_SB.PERC._CRS._Y00._LEN, LEN1)
+			CreateQWordField (RBUF, \_SB.PERC._Y00._MIN, MIN1)
+			CreateQWordField (RBUF, \_SB.PERC._Y00._MAX, MAX1)
+			CreateQWordField (RBUF, \_SB.PERC._Y00._LEN, LEN1)
 			MIN1 = CONFIG_ECAM_MMCONF_BASE_ADDRESS
 			MAX1 = (MIN1 + CONFIG_ECAM_MMCONF_LENGTH -1)
 			LEN1 = CONFIG_ECAM_MMCONF_LENGTH

From 6560bc04129f16ef9587f973f55c252b8aa119c4 Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Sat, 24 Jan 2026 11:54:20 -0600
Subject: [PATCH 3284/3886] mb/google: Set CBFS_SIZE to IFD BIOS size for
 Intel-based boards

Set CBFS_SIZE to match the SI_BIOS region size defined in each board's
chromeos.fmd file, up to a maximum of 16MiB. This ensures the largest
possible region is available for CBFS use without requiring manual
CBFS_SIZE overrides. The size is capped at 16MiB as that is the
largest area that can be memory mapped, the FIT pointer must be
located in the top 16MiB.

This change applies to all Intel-based Google mainboards with ChromeOS
FMD layouts that explicitly define SI_BIOS region sizes, and which do
not define a default non-ChromeOS FMAP layout (octopus, reef).

For boards with multiple ChromeOS FMD files, CBFS_SIZE is set
conditionally based on ROM size or silicon variant, using the
same logic as to select the ChromeOS FMD file.

This eliminates the need to override CBFS_SIZE when using larger
payloads (e.g., edk2) or multiple payloads, making the default
configuration more flexible.

TEST=build/boot various google boards with edk2 payload without
overriding CBFS_SIZE.

Change-Id: If7ef6cc96afcdd025958c578ad80fd0db641582a
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90883
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
---
 src/mainboard/google/auron/Kconfig     | 3 +++
 src/mainboard/google/beltino/Kconfig   | 3 +++
 src/mainboard/google/brox/Kconfig      | 3 +++
 src/mainboard/google/brya/Kconfig      | 4 ++++
 src/mainboard/google/butterfly/Kconfig | 3 +++
 src/mainboard/google/dedede/Kconfig    | 4 ++++
 src/mainboard/google/drallion/Kconfig  | 3 +++
 src/mainboard/google/eve/Kconfig       | 3 +++
 src/mainboard/google/fatcat/Kconfig    | 3 +++
 src/mainboard/google/fizz/Kconfig      | 3 +++
 src/mainboard/google/glados/Kconfig    | 3 +++
 src/mainboard/google/hatch/Kconfig     | 4 ++++
 src/mainboard/google/jecht/Kconfig     | 3 +++
 src/mainboard/google/kahlee/Kconfig    | 3 +++
 src/mainboard/google/link/Kconfig      | 3 +++
 src/mainboard/google/ocelot/Kconfig    | 3 +++
 src/mainboard/google/parrot/Kconfig    | 3 +++
 src/mainboard/google/poppy/Kconfig     | 3 +++
 src/mainboard/google/puff/Kconfig      | 4 ++++
 src/mainboard/google/rambi/Kconfig     | 3 +++
 src/mainboard/google/rex/Kconfig       | 3 +++
 src/mainboard/google/sarien/Kconfig    | 3 +++
 src/mainboard/google/slippy/Kconfig    | 3 +++
 src/mainboard/google/stout/Kconfig     | 3 +++
 src/mainboard/google/volteer/Kconfig   | 3 +++
 25 files changed, 79 insertions(+)

diff --git a/src/mainboard/google/auron/Kconfig b/src/mainboard/google/auron/Kconfig
index a9039912db..10d9a35191 100644
--- a/src/mainboard/google/auron/Kconfig
+++ b/src/mainboard/google/auron/Kconfig
@@ -71,6 +71,9 @@ config MAINBOARD_PART_NUMBER
 config OVERRIDE_DEVICETREE
 	default "variants/\$(CONFIG_VARIANT_DIR)/overridetree.cb"
 
+config CBFS_SIZE
+	default 0x600000
+
 config MAINBOARD_SMBIOS_MANUFACTURER
 	string
 	default "GOOGLE"
diff --git a/src/mainboard/google/beltino/Kconfig b/src/mainboard/google/beltino/Kconfig
index 9f061c2aae..0b5be0d535 100644
--- a/src/mainboard/google/beltino/Kconfig
+++ b/src/mainboard/google/beltino/Kconfig
@@ -66,6 +66,9 @@ config MAINBOARD_FAMILY
 config INTEL_GMA_VBT_FILE
 	default "src/mainboard/\$(MAINBOARDDIR)/data.vbt" if !BOARD_GOOGLE_MONROE
 
+config CBFS_SIZE
+	default 0x600000
+
 config MAINBOARD_SMBIOS_MANUFACTURER
 	string
 	default "GOOGLE"
diff --git a/src/mainboard/google/brox/Kconfig b/src/mainboard/google/brox/Kconfig
index 44db591f32..45e989c8e5 100644
--- a/src/mainboard/google/brox/Kconfig
+++ b/src/mainboard/google/brox/Kconfig
@@ -213,6 +213,9 @@ config HAVE_WWAN_POWER_SEQUENCE
 config HAVE_PCIE_WWAN
 	def_bool n
 
+config CBFS_SIZE
+	default 0x1000000
+
 config USE_PM_ACPI_TIMER
 	default n
 
diff --git a/src/mainboard/google/brya/Kconfig b/src/mainboard/google/brya/Kconfig
index 6a4082dfdf..707ffc9b4d 100644
--- a/src/mainboard/google/brya/Kconfig
+++ b/src/mainboard/google/brya/Kconfig
@@ -1186,6 +1186,10 @@ config UART_FOR_CONSOLE
 	int
 	default 0
 
+config CBFS_SIZE
+	default 0xc60000 if BOARD_ROMSIZE_KB_16384
+	default 0x1000000 if BOARD_ROMSIZE_KB_32768
+
 config HAVE_WWAN_POWER_SEQUENCE
 	def_bool n
 	help
diff --git a/src/mainboard/google/butterfly/Kconfig b/src/mainboard/google/butterfly/Kconfig
index 432374bb97..09ef13511b 100644
--- a/src/mainboard/google/butterfly/Kconfig
+++ b/src/mainboard/google/butterfly/Kconfig
@@ -35,6 +35,9 @@ config MAINBOARD_DIR
 config MAINBOARD_PART_NUMBER
 	default "Butterfly"
 
+config CBFS_SIZE
+	default 0x600000
+
 config MAINBOARD_VENDOR
 	string
 	default "Hewlett-Packard"
diff --git a/src/mainboard/google/dedede/Kconfig b/src/mainboard/google/dedede/Kconfig
index d6af56057d..7e470d6b87 100644
--- a/src/mainboard/google/dedede/Kconfig
+++ b/src/mainboard/google/dedede/Kconfig
@@ -310,6 +310,10 @@ config FMDFILE
 	default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/chromeos-dedede-16MiB.fmd" if CHROMEOS && BOARD_ROMSIZE_KB_16384
 	default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/chromeos-dedede-32MiB.fmd" if CHROMEOS && BOARD_ROMSIZE_KB_32768
 
+config CBFS_SIZE
+	default 0xc7f000 if BOARD_ROMSIZE_KB_16384
+	default 0x1000000 if BOARD_ROMSIZE_KB_32768
+
 config MAINBOARD_DIR
 	default "google/dedede"
 
diff --git a/src/mainboard/google/drallion/Kconfig b/src/mainboard/google/drallion/Kconfig
index 34c9da5a8e..1353447ee2 100644
--- a/src/mainboard/google/drallion/Kconfig
+++ b/src/mainboard/google/drallion/Kconfig
@@ -98,4 +98,7 @@ config VBOOT
 config FMDFILE
 	default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/default.fmd" if !CHROMEOS
 
+config CBFS_SIZE
+	default 0x1000000
+
 endif # BOARD_GOOGLE_BASEBOARD_DRALLION
diff --git a/src/mainboard/google/eve/Kconfig b/src/mainboard/google/eve/Kconfig
index b473d502bf..cd4c5ad5e6 100644
--- a/src/mainboard/google/eve/Kconfig
+++ b/src/mainboard/google/eve/Kconfig
@@ -74,6 +74,9 @@ config UART_FOR_CONSOLE
 	int
 	default 2
 
+config CBFS_SIZE
+	default 0xe00000
+
 config USE_PM_ACPI_TIMER
 	default n
 endif
diff --git a/src/mainboard/google/fatcat/Kconfig b/src/mainboard/google/fatcat/Kconfig
index 15b149b226..20889dbdf0 100644
--- a/src/mainboard/google/fatcat/Kconfig
+++ b/src/mainboard/google/fatcat/Kconfig
@@ -244,6 +244,9 @@ config UART_FOR_CONSOLE
 	int
 	default 0
 
+config CBFS_SIZE
+	default 0x1000000
+
 config USE_PM_ACPI_TIMER
 	default n
 
diff --git a/src/mainboard/google/fizz/Kconfig b/src/mainboard/google/fizz/Kconfig
index d07ce2ff10..daaf81410a 100644
--- a/src/mainboard/google/fizz/Kconfig
+++ b/src/mainboard/google/fizz/Kconfig
@@ -102,6 +102,9 @@ config UART_FOR_CONSOLE
 	int
 	default 2
 
+config CBFS_SIZE
+	default 0xe00000
+
 config USE_PM_ACPI_TIMER
 	default n
 
diff --git a/src/mainboard/google/glados/Kconfig b/src/mainboard/google/glados/Kconfig
index 6786d1b5f1..746e326c04 100644
--- a/src/mainboard/google/glados/Kconfig
+++ b/src/mainboard/google/glados/Kconfig
@@ -128,6 +128,9 @@ config UART_FOR_CONSOLE
 	int
 	default 2
 
+config CBFS_SIZE
+	default 0xe00000
+
 config CONSOLE_SERIAL
 	bool
 	default n
diff --git a/src/mainboard/google/hatch/Kconfig b/src/mainboard/google/hatch/Kconfig
index 1336c65eed..1f9a7d2eb0 100644
--- a/src/mainboard/google/hatch/Kconfig
+++ b/src/mainboard/google/hatch/Kconfig
@@ -125,6 +125,10 @@ config FMDFILE
 	default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/chromeos-16MiB.fmd" if BOARD_ROMSIZE_KB_16384 && CHROMEOS
 	default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/chromeos-32MiB.fmd" if BOARD_ROMSIZE_KB_32768 && CHROMEOS
 
+config CBFS_SIZE
+	default 0xc00000 if BOARD_ROMSIZE_KB_16384
+	default 0x1000000 if BOARD_ROMSIZE_KB_32768
+
 config MAINBOARD_DIR
 	default "google/hatch"
 
diff --git a/src/mainboard/google/jecht/Kconfig b/src/mainboard/google/jecht/Kconfig
index 0ced2cd61d..0edbf5ebab 100644
--- a/src/mainboard/google/jecht/Kconfig
+++ b/src/mainboard/google/jecht/Kconfig
@@ -55,6 +55,9 @@ config MAINBOARD_PART_NUMBER
 config INTEL_GMA_VBT_FILE
 	default "src/mainboard/\$(MAINBOARDDIR)/data.vbt" if !BOARD_GOOGLE_TIDUS
 
+config CBFS_SIZE
+	default 0x600000
+
 config MAINBOARD_SMBIOS_MANUFACTURER
 	string
 	default "GOOGLE"
diff --git a/src/mainboard/google/kahlee/Kconfig b/src/mainboard/google/kahlee/Kconfig
index b3fb71a04e..157c317a62 100644
--- a/src/mainboard/google/kahlee/Kconfig
+++ b/src/mainboard/google/kahlee/Kconfig
@@ -103,6 +103,9 @@ config FMDFILE
 	  but in some cases more complex setups are required.
 	  When an fmd is specified, it overrides the default format.
 
+config CBFS_SIZE
+	default 0x1000000
+
 config MAX_CPUS
 	int
 	default 4
diff --git a/src/mainboard/google/link/Kconfig b/src/mainboard/google/link/Kconfig
index df85382246..ab889f1c24 100644
--- a/src/mainboard/google/link/Kconfig
+++ b/src/mainboard/google/link/Kconfig
@@ -38,6 +38,9 @@ config MAINBOARD_DIR
 config MAINBOARD_PART_NUMBER
 	default "Link"
 
+config CBFS_SIZE
+	default 0x600000
+
 config MAINBOARD_SMBIOS_MANUFACTURER
 	string
 	default "GOOGLE"
diff --git a/src/mainboard/google/ocelot/Kconfig b/src/mainboard/google/ocelot/Kconfig
index b20ef17289..d5e37c742f 100644
--- a/src/mainboard/google/ocelot/Kconfig
+++ b/src/mainboard/google/ocelot/Kconfig
@@ -210,6 +210,9 @@ config UART_FOR_CONSOLE
 	int
 	default 0
 
+config CBFS_SIZE
+	default 0x1000000
+
 config USE_PM_ACPI_TIMER
 	default n
 
diff --git a/src/mainboard/google/parrot/Kconfig b/src/mainboard/google/parrot/Kconfig
index dc0e8606fe..2fa7420a14 100644
--- a/src/mainboard/google/parrot/Kconfig
+++ b/src/mainboard/google/parrot/Kconfig
@@ -36,6 +36,9 @@ config MAINBOARD_DIR
 config MAINBOARD_PART_NUMBER
 	default "Parrot"
 
+config CBFS_SIZE
+	default 0x600000
+
 config MAINBOARD_SMBIOS_MANUFACTURER
 	string
 	default "GOOGLE"
diff --git a/src/mainboard/google/poppy/Kconfig b/src/mainboard/google/poppy/Kconfig
index ac9aa54e56..cef94552f7 100644
--- a/src/mainboard/google/poppy/Kconfig
+++ b/src/mainboard/google/poppy/Kconfig
@@ -225,6 +225,9 @@ config UART_FOR_CONSOLE
 	int
 	default 2
 
+config CBFS_SIZE
+	default 0xe00000
+
 config USE_PM_ACPI_TIMER
 	default n
 
diff --git a/src/mainboard/google/puff/Kconfig b/src/mainboard/google/puff/Kconfig
index 2ec9d996b9..ebf9ea523b 100644
--- a/src/mainboard/google/puff/Kconfig
+++ b/src/mainboard/google/puff/Kconfig
@@ -120,6 +120,10 @@ config FMDFILE
 	default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/chromeos-16MiB.fmd" if BOARD_ROMSIZE_KB_16384 && CHROMEOS
 	default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/chromeos-32MiB.fmd" if BOARD_ROMSIZE_KB_32768 && CHROMEOS
 
+config CBFS_SIZE
+	default 0xd00000 if BOARD_ROMSIZE_KB_16384
+	default 0x1000000 if BOARD_ROMSIZE_KB_32768
+
 config POWER_OFF_ON_CR50_UPDATE
 	bool
 	default n
diff --git a/src/mainboard/google/rambi/Kconfig b/src/mainboard/google/rambi/Kconfig
index ccdc02a45c..399872e230 100644
--- a/src/mainboard/google/rambi/Kconfig
+++ b/src/mainboard/google/rambi/Kconfig
@@ -146,6 +146,9 @@ config MAINBOARD_PART_NUMBER
 config OVERRIDE_DEVICETREE
 	default "variants/\$(CONFIG_VARIANT_DIR)/overridetree.cb"
 
+config CBFS_SIZE
+	default 0x600000
+
 config MAINBOARD_SMBIOS_MANUFACTURER
 	string
 	default "GOOGLE"
diff --git a/src/mainboard/google/rex/Kconfig b/src/mainboard/google/rex/Kconfig
index f9afd38141..b5f8858033 100644
--- a/src/mainboard/google/rex/Kconfig
+++ b/src/mainboard/google/rex/Kconfig
@@ -259,6 +259,9 @@ config UART_FOR_CONSOLE
 	int
 	default 0
 
+config CBFS_SIZE
+	default 0x1000000
+
 config OVERRIDE_DEVICETREE
 	default "variants/\$(CONFIG_VARIANT_DIR)/overridetree.cb"
 
diff --git a/src/mainboard/google/sarien/Kconfig b/src/mainboard/google/sarien/Kconfig
index dcf94470ec..d4f5171d61 100644
--- a/src/mainboard/google/sarien/Kconfig
+++ b/src/mainboard/google/sarien/Kconfig
@@ -110,4 +110,7 @@ config VBOOT
 config FMDFILE
 	default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/default.fmd" if !CHROMEOS
 
+config CBFS_SIZE
+	default 0x1000000
+
 endif # BOARD_GOOGLE_BASEBOARD_SARIEN
diff --git a/src/mainboard/google/slippy/Kconfig b/src/mainboard/google/slippy/Kconfig
index 380ed9fe72..5420557d82 100644
--- a/src/mainboard/google/slippy/Kconfig
+++ b/src/mainboard/google/slippy/Kconfig
@@ -71,6 +71,9 @@ config OVERRIDE_DEVICETREE
 config INTEL_GMA_VBT_FILE
 	default "src/mainboard/\$(MAINBOARDDIR)/data.vbt"
 
+config CBFS_SIZE
+	default 0x600000
+
 config MAINBOARD_SMBIOS_MANUFACTURER
 	string
 	default "GOOGLE"
diff --git a/src/mainboard/google/stout/Kconfig b/src/mainboard/google/stout/Kconfig
index 2c354419d8..25add1b340 100644
--- a/src/mainboard/google/stout/Kconfig
+++ b/src/mainboard/google/stout/Kconfig
@@ -38,6 +38,9 @@ config VGA_BIOS_ID
 	string
 	default "8086,0156"
 
+config CBFS_SIZE
+	default 0x600000
+
 config MAINBOARD_SMBIOS_MANUFACTURER
 	string
 	default "GOOGLE"
diff --git a/src/mainboard/google/volteer/Kconfig b/src/mainboard/google/volteer/Kconfig
index 872d28540e..dc586f1538 100644
--- a/src/mainboard/google/volteer/Kconfig
+++ b/src/mainboard/google/volteer/Kconfig
@@ -245,6 +245,9 @@ config VARIANT_DIR
 	default "volteer2" if BOARD_GOOGLE_VOLTEER2_TI50
 	default "voxel" if BOARD_GOOGLE_VOXEL
 
+config CBFS_SIZE
+	default 0x1000000
+
 config USE_PM_ACPI_TIMER
 	default n
 

From 1e97b44e41fa2ae8607af1cead0b714cf23db76f Mon Sep 17 00:00:00 2001
From: Patrick Rudolph <patrick.rudolph@9elements.com>
Date: Mon, 26 Jan 2026 07:38:14 +0100
Subject: [PATCH 3285/3886] cpu/intel/microcode: Fix get_microcode_size

Ancient microcode update files do not have a total_size field.
Add support for such platforms and return 2048 in that case.

Change-Id: I952edc12cccf24f396d940bc594d8ef97826a253
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90910
Reviewed-by: Naresh <naresh.solanki.2011@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
---
 src/cpu/intel/microcode/microcode.c | 7 ++++++-
 1 file changed, 6 insertions(+), 1 deletion(-)

diff --git a/src/cpu/intel/microcode/microcode.c b/src/cpu/intel/microcode/microcode.c
index b22822641a..7e1e1b0641 100644
--- a/src/cpu/intel/microcode/microcode.c
+++ b/src/cpu/intel/microcode/microcode.c
@@ -132,7 +132,12 @@ uint32_t get_microcode_rev(const void *microcode)
 
 uint32_t get_microcode_size(const void *microcode)
 {
-	return ((struct microcode *)microcode)->total_size;
+	u32 size = ((struct microcode *)microcode)->total_size;
+
+	/* Newer microcode updates include a size field, whereas older
+	 * containers set it at 0 and are exactly 2048 bytes long */
+
+	return size ? size : 2048;
 }
 
 uint32_t get_microcode_checksum(const void *microcode)

From fda17b0390d0cc98d88a017dad1bc89b6be825f0 Mon Sep 17 00:00:00 2001
From: Subrata Banik <subratabanik@google.com>
Date: Mon, 9 Feb 2026 23:16:32 +0530
Subject: [PATCH 3286/3886] soc/intel/pantherlake: Update IGD stolen memory
 size definitions
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Update the Integrated Graphics Device (IGD) stolen memory size enum
values to align with the Panther Lake Reference Code. This change
introduces the 96MB definition and corrects the value for 128MB.

Modified values:
- IGD_SM_96MB:  Added as 0x03
- IGD_SM_128MB: Updated from 0x03 to 0x04

Change-Id: Id7a547e8a530294a76f201e87865e8508ff67a92
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91140
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/soc/intel/pantherlake/chip.h | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/src/soc/intel/pantherlake/chip.h b/src/soc/intel/pantherlake/chip.h
index 1d75b0ae43..96f9a936b5 100644
--- a/src/soc/intel/pantherlake/chip.h
+++ b/src/soc/intel/pantherlake/chip.h
@@ -337,7 +337,8 @@ struct soc_intel_pantherlake_config {
 		IGD_SM_0MB = 0x00,
 		IGD_SM_32MB = 0x01,
 		IGD_SM_64MB = 0x02,
-		IGD_SM_128MB = 0x03,
+		IGD_SM_96MB = 0x03,
+		IGD_SM_128MB = 0x04,
 		IGD_SM_4MB = 0xF0,
 		IGD_SM_8MB = 0xF1,
 		IGD_SM_12MB = 0xF2,

From 3dc9427becb4278c7f205ca7494bbb957dbcbde5 Mon Sep 17 00:00:00 2001
From: Subrata Banik <subratabanik@google.com>
Date: Mon, 9 Feb 2026 13:32:53 +0530
Subject: [PATCH 3287/3886] soc/intel/pantherlake: Update IGD stolen memory
 size
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

This commit increases the default pre-allocated IGD stolen memory size
from 64MB to 128MB in FSP-M parameters. This ensures sufficient memory
is allocated for higher resolution displays and graphics-intensive
early-boot tasks on Panther Lake platforms.

BUG=b:481209815
TEST=Able to build and boot google/ruby.

Change-Id: Idd3f1bcb9cbb27adc18a31c0dd5952e901ecf5eb
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91126
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/soc/intel/pantherlake/romstage/fsp_params.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/soc/intel/pantherlake/romstage/fsp_params.c b/src/soc/intel/pantherlake/romstage/fsp_params.c
index bef87158d7..d143d95688 100644
--- a/src/soc/intel/pantherlake/romstage/fsp_params.c
+++ b/src/soc/intel/pantherlake/romstage/fsp_params.c
@@ -41,8 +41,8 @@ static void fill_fspm_igd_params(FSP_M_CONFIG *m_cfg,
 	};
 	m_cfg->InternalGraphics = !CONFIG(SOC_INTEL_DISABLE_IGD) && is_devfn_enabled(PCI_DEVFN_IGD);
 	if (m_cfg->InternalGraphics) {
-		/* IGD is enabled, set IGD stolen size to 64MB. */
-		m_cfg->IgdDvmt50PreAlloc = IGD_SM_64MB;
+		/* IGD is enabled, set IGD stolen size to 128MB. */
+		m_cfg->IgdDvmt50PreAlloc = IGD_SM_128MB;
 		/* DP port config */
 		m_cfg->DdiPortAConfig = config->ddi_port_A_config;
 		m_cfg->DdiPortBConfig = config->ddi_port_B_config;

From 623c0972fd4f031fd0aefbb14669c847e2a944fe Mon Sep 17 00:00:00 2001
From: Subrata Banik <subratabanik@google.com>
Date: Thu, 5 Feb 2026 12:48:45 +0530
Subject: [PATCH 3288/3886] lib: Add support for off-mode charging indicator

Introduce CONFIG_PLATFORM_HAS_OFF_MODE_CHARGING_INDICATOR to support
rendering a dedicated splash screen when a device is in an off-mode
charging state. This provides visual feedback to the user when a
device autoboots upon power cable insertion instead of performing
a full OS boot.

Changes:
- Add Kconfig options for enabling the indicator and specifying
  the logo path.
- Update Makefile.mk to include the off-mode charging BMP file
  in CBFS when the feature is enabled.
- Depend on BMP_LOGO infrastructure for asset rendering.

BUG=b:473480933
TEST=Able to build google/fatcat.

Change-Id: Ib09de15ca3526bf5b10f7404dc58032d63c01e6d
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91105
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
---
 src/lib/Kconfig     | 17 +++++++++++++++++
 src/lib/Makefile.mk |  2 ++
 2 files changed, 19 insertions(+)

diff --git a/src/lib/Kconfig b/src/lib/Kconfig
index 0c8fc454ff..d70374d758 100644
--- a/src/lib/Kconfig
+++ b/src/lib/Kconfig
@@ -270,6 +270,23 @@ config SPLASH_SCREEN_FOOTER_LOGO_PATH
 	depends on SPLASH_SCREEN_FOOTER
 	default "3rdparty/blobs/mainboard/\$(MAINBOARDDIR)/logo.bmp"
 
+config PLATFORM_HAS_OFF_MODE_CHARGING_INDICATOR
+	bool "Display off-mode charging indicator"
+	default n
+	depends on BMP_LOGO
+	help
+	  Enable an off-mode charging splash screen to notify the user that
+	  the device is charging. This prevents user confusion when a
+	  device autoboots into a charging state upon the
+	  insertion of a power cable, rather than performing a full OS boot.
+
+	  This feature requires a functional display and depends on the
+	  BMP_LOGO infrastructure to render the charging assets.
+
+config PLATFORM_OFF_MODE_CHARGING_INDICATOR_LOGO_PATH
+	string "Path to off-mode charging logo file"
+	default "3rdparty/blobs/mainboard/\$(MAINBOARDDIR)/off_mode_charging.bmp"
+
 endmenu
 
 config HAVE_EARLY_POWEROFF_SUPPORT
diff --git a/src/lib/Makefile.mk b/src/lib/Makefile.mk
index d7cf8455b1..0405cbeb5b 100644
--- a/src/lib/Makefile.mk
+++ b/src/lib/Makefile.mk
@@ -449,3 +449,5 @@ $(eval $(call add_bmp_logo_file_to_cbfs,CONFIG_PLATFORM_HAS_LOW_BATTERY_INDICATO
 	      low_battery.bmp,CONFIG_PLATFORM_LOW_BATTERY_INDICATOR_LOGO_PATH))
 $(eval $(call add_bmp_logo_file_to_cbfs,CONFIG_SPLASH_SCREEN_FOOTER, \
 	      footer_logo.bmp,CONFIG_SPLASH_SCREEN_FOOTER_LOGO_PATH))
+$(eval $(call add_bmp_logo_file_to_cbfs,CONFIG_PLATFORM_HAS_OFF_MODE_CHARGING_INDICATOR, \
+	      off_mode_charging.bmp,CONFIG_PLATFORM_OFF_MODE_CHARGING_INDICATOR_LOGO_PATH))

From aa16822643e652833e8c368b7724e5b3c0c6d875 Mon Sep 17 00:00:00 2001
From: Subrata Banik <subratabanik@google.com>
Date: Thu, 5 Feb 2026 14:41:04 +0530
Subject: [PATCH 3289/3886] lib: Add support for off-mode charging splash
 screen

Introduce the infrastructure required to display an off-mode charging
notification. This is used when a device boots due to power cable
insertion but should remain in a charging state rather than booting
the full operating system.

Changes:
- Add BOOTSPLASH_OFF_MODE_CHARGING to bootsplash_type.
- Define platform_is_off_mode_charging_active() with a weak inline
  fallback to allow platforms to signal off-mode charging status.
- Update bmp_logo.c to recognize "off_mode_charging.bmp" and select
  it as the active logo type when charging is active.
- Modify render_bmp.c to handle layout and rendering for the charging
  logo, including support for footer text if enabled.
- Ensure the rendering flow bails out early after displaying the
  charging notification to prevent standard OS boot splash.

BUG=b:473480933
TEST=Able to build google/fatcat.

Change-Id: Ief4c65eaf0178ff3d736363c3e56acfe1adba14a
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91106
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/include/bootsplash.h | 25 +++++++++++++++++++++++++
 src/lib/bmp_logo.c       |  6 +++++-
 src/lib/render_bmp.c     | 13 ++++++++++++-
 3 files changed, 42 insertions(+), 2 deletions(-)

diff --git a/src/include/bootsplash.h b/src/include/bootsplash.h
index fa13316955..a3d8487968 100644
--- a/src/include/bootsplash.h
+++ b/src/include/bootsplash.h
@@ -13,6 +13,8 @@ enum bootsplash_type {
 	BOOTSPLASH_CENTER,
 	/* Indicates an optional OEM defined bootsplash logo for footer of the splash screen. */
 	BOOTSPLASH_FOOTER,
+	/* Indicates a off-mode charging bootsplash logo. */
+	BOOTSPLASH_OFF_MODE_CHARGING,
 
 	/* It's used to determine the total number of bootsplash types. */
 	BOOTSPLASH_MAX_NUM,
@@ -171,6 +173,29 @@ bool platform_is_low_battery_shutdown_needed(void);
 static inline bool platform_is_low_battery_shutdown_needed(void) { return false; }
 #endif
 
+/*
+ * Platform specific callbacks for off-mode bootsplash handling.
+ *
+ * These callbacks allow the platform to determine if the device
+ * has booted in off-mode charging to render the appropriate user
+ * notification.
+ */
+#if CONFIG(PLATFORM_HAS_OFF_MODE_CHARGING_INDICATOR)
+/*
+ * platform_is_off_mode_charging_active - Check if off-mode charging is required.
+ *
+ * Returns true if the system should stay in a "charging splash" state
+ * instead of performing a full OS boot or a complete power-off.
+ */
+bool platform_is_off_mode_charging_active(void);
+#else
+/* Inline fallback for platforms without off-mode charging support */
+static inline bool platform_is_off_mode_charging_active(void)
+{
+	return false;
+}
+#endif
+
 /*
  * VGA Mode 12h (640x480 with 16 colors):
  * As per page 13 of https://www.phatcode.net/res/221/files/vbe20.pdf
diff --git a/src/lib/bmp_logo.c b/src/lib/bmp_logo.c
index 9dfe15a085..7b0de54720 100644
--- a/src/lib/bmp_logo.c
+++ b/src/lib/bmp_logo.c
@@ -13,7 +13,8 @@ static const struct cbmem_entry *logo_entry;
 static const char *bootsplash_list[BOOTSPLASH_MAX_NUM] = {
 	[BOOTSPLASH_LOW_BATTERY] = "low_battery.bmp",
 	[BOOTSPLASH_CENTER] = "logo.bmp",
-	[BOOTSPLASH_FOOTER] = "footer_logo.bmp"
+	[BOOTSPLASH_FOOTER] = "footer_logo.bmp",
+	[BOOTSPLASH_OFF_MODE_CHARGING] = "off_mode_charging.bmp"
 };
 
 /*
@@ -60,6 +61,9 @@ void *bmp_load_logo(size_t *logo_size)
 	if (platform_is_low_battery_shutdown_needed())
 		type = BOOTSPLASH_LOW_BATTERY;
 
+	if (platform_is_off_mode_charging_active())
+		type = BOOTSPLASH_OFF_MODE_CHARGING;
+
 	return bmp_load_logo_by_type(type, logo_size);
 }
 
diff --git a/src/lib/render_bmp.c b/src/lib/render_bmp.c
index b91015bf89..39242d0d97 100644
--- a/src/lib/render_bmp.c
+++ b/src/lib/render_bmp.c
@@ -576,7 +576,8 @@ static void get_logo_layout(
 	if (!config || !logo_halignment || !logo_valignment || !logo_bottom_margin)
 		return;
 
-	if (logo_type == BOOTSPLASH_LOW_BATTERY || logo_type == BOOTSPLASH_CENTER) {
+	if (logo_type == BOOTSPLASH_LOW_BATTERY || logo_type == BOOTSPLASH_CENTER ||
+			logo_type == BOOTSPLASH_OFF_MODE_CHARGING) {
 		*logo_halignment = config->halignment;
 		*logo_valignment = config->valignment;
 		/* Override logo alignment if the default screen orientation is not normal */
@@ -710,6 +711,16 @@ void render_logo_to_framebuffer(struct logo_config *config)
 		return;
 	}
 
+	/*
+	 * If the device has booted due to cable power insertion aka off-mode then display
+	 * off-mode charging user notification and bail out early.
+	 */
+	if (platform_is_off_mode_charging_active()) {
+		if (load_and_render_logo_to_framebuffer(BOOTSPLASH_OFF_MODE_CHARGING, config) != 0)
+			printk(BIOS_ERR, "%s: Failed to render off-mode charging logo.\n", __func__);
+		return;
+	}
+
 	/* Render the main logo */
 	if (load_and_render_logo_to_framebuffer(BOOTSPLASH_CENTER, config) != 0) {
 		printk(BIOS_ERR, "%s: Failed to render main splash screen logo.\n", __func__);

From 95461ee3dfc8c9270c05efd8366d862b5c20a593 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Filip=20Lewi=C5=84ski?= <filip.lewinski@3mdeb.com>
Date: Mon, 8 Dec 2025 11:54:56 +0100
Subject: [PATCH 3290/3886] Documentation/soc/intel/redundancy.md: add
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Add documentation for the Intel PCH Top Swap based A/B redundancy
mechanism. Describe the BOOTBLOCK and TOPSWAP bootblock regions,
COREBOOT and COREBOOT_TS CBFS regions, the attempt_slot_b CMOS option
and its application time, and how the active CBFS region is selected
based on the Top Swap state.

This follows the A/B redundancy proposal discussed on the coreboot
mailing list:

https://mail.coreboot.org/archives/list/coreboot@coreboot.org/thread/C6JN2PB7K7D67EG7OIKB6BBERZU5YV35/

Change-Id: I1b88989201e209b2f69964c067c432ff82a0057e
Signed-off-by: Filip Lewiński <filip.lewinski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90412
Reviewed-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 Documentation/soc/intel/index.md      |   1 +
 Documentation/soc/intel/redundancy.md | 174 ++++++++++++++++++++++++++
 2 files changed, 175 insertions(+)
 create mode 100644 Documentation/soc/intel/redundancy.md

diff --git a/Documentation/soc/intel/index.md b/Documentation/soc/intel/index.md
index ef032f5ece..96a23a5572 100644
--- a/Documentation/soc/intel/index.md
+++ b/Documentation/soc/intel/index.md
@@ -17,4 +17,5 @@ Apollolake <apollolake/index.md>
 CSE FW Update <cse_fw_update/cse_fw_update.md>
 Xeon Scalable processor <xeon_sp/index.md>
 Skylake/Kaby Lake BootGuard bypass <deguard.md>
+Intel Top Swap based A/B redundancy <redundancy.md>
 ```
diff --git a/Documentation/soc/intel/redundancy.md b/Documentation/soc/intel/redundancy.md
new file mode 100644
index 0000000000..bd3a92aaa5
--- /dev/null
+++ b/Documentation/soc/intel/redundancy.md
@@ -0,0 +1,174 @@
+# Intel Top Swap based A and B redundancy
+
+This document describes a simple firmware A and B redundancy scheme based on
+Intel PCH Top Swap. The scheme maintains two firmware slots and uses the Top
+Swap control bit to choose which bootblock runs on boot. Each bootblock then
+continues booting from a matching CBFS region, so switching the Top Swap state
+switches the active slot.
+
+The Intel Top Swap feature allows the PCH to take two physically topmost chunks
+of the BIOS flash chip, and decide in which order to map them - effectively
+allowing to swap the two chunks, and deciding which of them lands at the reset
+vector.
+
+For background on the hardware mechanism, consult the Intel documentation
+for your PCH and platform and search for sections named similarly to "Top
+Swap", "Top Swap Block Size (TSBS)", or "Boot Block Update Scheme". The exact
+document title and section naming varies between generations. The Alder Lake
+implementation for example has been developed basing mainly on ADL-P EDS Vol
+1&2, sections:
+
+* `3.2.1 Boot Block Update Scheme`,
+* `9.70 PCH Descriptor Record 69 (Flash Descriptor Records)`,
+* `31.3.2 Backed Up Control (BUC)`,
+* `2.1.17 BIOS Control (ESPI_BC)`
+
+## Flash layout and CBFS regions
+
+The implementation assumes four FMAP regions that are CBFS formatted and that
+use the following names.
+
+The bootblocks live in `BOOTBLOCK` and `TOPSWAP`. Each of these is a relatively
+small CBFS region that contains a bootblock image and any additional files that
+must reside next to it for early boot on a given platform. These regions must
+exist in the board's `.fmd` file and must be sized with headroom for growth
+- keeping in mind the FIT table and Boot Guard ACM's must reside in the same
+region as the bootblock.
+
+The main firmware CBFS regions are `COREBOOT` and `COREBOOT_TS`. `COREBOOT` is
+typically the base slot and is often placed under write protection, along with
+`BOOTBLOCK`. `COREBOOT_TS` is the alternate slot and is typically left writable
+so it can be replaced by an update mechanism, along with `TOPSWAP`.
+
+The `BOOTBLOCK` and `TOPSWAP` regions are expected to be placed in the
+flash area covered by the Top Swap configuration. The sizes of the regions
+must match and be equal to the corresponding field in the IFD. coreboot
+can adjust the The Top Swap size (also called Top Swap Block Size in
+Intel's documentation) field in the descriptor during the build. This
+is controlled by `CONFIG_INTEL_IFD_SET_TOP_SWAP_BOOTBLOCK_SIZE` and uses
+`CONFIG_INTEL_TOP_SWAP_BOOTBLOCK_SIZE` as the requested size.
+
+## Kconfig options
+
+The option `CONFIG_INTEL_ADD_TOP_SWAP_BOOTBLOCK` creates two copies of the
+bootblock.
+
+The option `CONFIG_INTEL_TOP_SWAP_SEPARATE_REGIONS` changes where the bootblocks
+are stored. When it is disabled, both are stored in the primary CBFS region as
+on existing platforms. When it is enabled, they are placed in the `BOOTBLOCK`
+`TOPSWAP` FMAP regions. It also places copies of the following stages and
+required files from the `COREBOOT` region in the `COREBOOT_TS` region.
+
+If CBFS verification is enabled, the image build checks verification status for
+all main CBFS regions that are part of the redundancy configuration, not only
+for `COREBOOT`.
+
+The option `CONFIG_INTEL_TOP_SWAP_OPTION_CONTROL` enables runtime control of the
+Top Swap control bit based on a CMOS option. In tree, this option is constrained
+to specific Intel SoCs. For a board to use it, the SoC bootblock must apply the
+setting early enough for writes to the Top Swap control bit to take effect.
+
+To reduce per board configuration burden, `CONFIG_TOP_SWAP_REDUNDANCY` exists
+as a convenience option that selects the relevant pieces for Top Swap based
+redundancy. Even with this convenience option enabled, a board still must
+provide an appropriate `.fmd` layout and a `cmos.layout` entry as described
+below.
+
+Boards that use Top Swap based redundancy must enable CMOS option support
+and ensure the option backend can read options at boot time. The symbol
+`MAINBOARD_NEEDS_CMOS_OPTIONS` exists to indicate this dependency. Please
+note that not every SoC supports this functionality.
+
+## CMOS option and when it is applied
+
+Runtime Top Swap selection is controlled by a CMOS option named
+`attempt_slot_b`. The name is defined as `TOP_SWAP_ENABLE_CMOS_OPTION` in
+`src/soc/intel/common/block/include/intelblocks/rtc.h`. A board enabling
+`CONFIG_INTEL_TOP_SWAP_OPTION_CONTROL` must provide a CMOS entry with this exact
+name in its `cmos.layout` file.
+
+The function `sync_rtc_buc_top_swap()` in `src/soc/intel/common/block/rtc/rtc.c`
+implements the synchronization logic. It reads the CMOS option via
+`get_uint_option()`, reads the current Top Swap state from the RTC BUC register,
+compares the two, and if they differ it programs the new state and resets the
+platform. The reset is intentional and ensures the new Top Swap state is in
+effect from the beginning of the subsequent boot.
+
+The SoC bootblock must call `sync_rtc_buc_top_swap()` early in
+`bootblock_soc_init()` when `CONFIG_INTEL_TOP_SWAP_OPTION_CONTROL` is enabled.
+This must happen before the platform locks down the relevant interfaces such
+that Top Swap state changes no longer take effect.
+
+Because the CMOS option is applied in bootblock, a mismatch between the requested
+slot and the current Top Swap state causes a very early reset. The next boot
+then starts directly from the selected slot.
+
+## CBFS region selection
+
+The choice of the main CBFS region is made in `cbfs_get_boot_device()` in
+`src/lib/cbfs.c`. Instead of always locating `COREBOOT`, the code calls
+`cbfs_fmap_region_hint()` to obtain the FMAP region name and then locates that
+region.
+
+The default `cbfs_fmap_region_hint()` implementation is a weak symbol that
+returns `COREBOOT`, so platforms that do not override it retain the existing
+behavior.
+
+Intel Top Swap platforms provide a strong definition of
+`cbfs_fmap_region_hint()` in `src/soc/intel/common/block/rtc/rtc.c`. When
+`CONFIG_INTEL_TOP_SWAP_OPTION_CONTROL` is enabled and the Top Swap control
+bit is set, it returns `COREBOOT_TS`. Otherwise it returns `COREBOOT`.
+`cbfs_get_boot_device()` logs the selected region and stops with an error if the
+region cannot be found in FMAP.
+
+This is deliberately based on the actual hardware Top Swap state rather than on
+reading CMOS again. At the point where `cbfs_fmap_region_hint()` is used, the
+option table is not reliably available, because the `cmos_layout.bin` backing
+the option table is itself stored in CBFS.
+
+For the override to apply in a given stage, the RTC block code must be linked
+into that stage. The common RTC block is built into multiple stages and is
+also built into postcar to ensure the hint function is available when CBFS is
+accessed there.
+
+## Boot flow summary
+
+A typical update and rollback sequence is as follows.
+
+The platform starts in slot A with Top Swap disabled. The hardware boots from
+the `BOOTBLOCK` and coreboot continues from the `COREBOOT` CBFS region.
+
+An update writes into the `TOPSWAP` and `COREBOOT_TS` regions, then sets the
+`attempt_slot_b` CMOS option.
+
+On the next boot, `sync_rtc_buc_top_swap()` observes that the CMOS request
+differs from the current hardware Top Swap state, programs the new Top Swap
+state, and resets the platform.
+
+After the reset, the hardware starts from the bootblock corresponding to
+the new Top Swap state. When coreboot later initializes its boot device,
+`cbfs_fmap_region_hint()` sees the Top Swap state and selects `COREBOOT_TS`, so
+the remainder of the boot uses the updated slot.
+
+Clearing CMOS or resetting `attempt_slot_b` triggers the same sequence in the
+opposite direction, returning the platform to `COREBOOT` without requiring
+external flashing.
+
+## Troubleshooting notes
+
+If the platform does not switch slots as expected, confirm that the
+`attempt_slot_b` entry exists in `cmos.layout` and that the option table backend
+is in use so `get_uint_option()` can read it in bootblock.
+
+If the platform resets but still boots from `COREBOOT`, confirm that the RTC
+block implementation providing `cbfs_fmap_region_hint()` is linked into the
+stage that performs CBFS initialization on your platform.
+
+If the build fails to boot after enabling separate regions, confirm that the
+`.fmd` file defines `BOOTBLOCK`, `TOPSWAP`, `COREBOOT`, and `COREBOOT_TS` as
+CBFS regions and that the platform Top Swap configuration matches the reserved
+bootblock and Top Swap region placement and sizing.
+
+Serial logs should show the CMOS request and the RTC BUC control bit values
+during bootblock, followed by a log line indicating which CBFS region is being
+used.

From 1fe88cc716f65bdc990f34895835f26a8e2d6958 Mon Sep 17 00:00:00 2001
From: Sowmya Aralguppe <sowmya.aralguppe@intel.com>
Date: Mon, 2 Feb 2026 12:16:41 +0530
Subject: [PATCH 3291/3886] mb/google/fatcat: Fix fast_vmode_i_trip indexing in
 devicetree
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Update fast_vmode_i_trip array references as per 813278_Rev2p1p1 to use
PTL_SKU_* constants instead of PTL_CORE_* constants. This aligns with
the corrected indexing scheme used in the SoC VR configuration code.

TEST=Verify IccLimit value for different SKUs in FSP debug log

Change-Id: I90a5c6e03633ba2b4a0a132ed9f94d8e5c4ff8bf
Signed-off-by: Sowmya Aralguppe <sowmya.aralguppe@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91049
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Pranava Y N <pranavayn@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
---
 .../variants/baseboard/fatcat/devicetree.cb   | 30 ++++++++++++++-----
 1 file changed, 22 insertions(+), 8 deletions(-)

diff --git a/src/mainboard/google/fatcat/variants/baseboard/fatcat/devicetree.cb b/src/mainboard/google/fatcat/variants/baseboard/fatcat/devicetree.cb
index 0f74bc79b8..fd1f55fabe 100644
--- a/src/mainboard/google/fatcat/variants/baseboard/fatcat/devicetree.cb
+++ b/src/mainboard/google/fatcat/variants/baseboard/fatcat/devicetree.cb
@@ -87,22 +87,36 @@ chip soc/intel/pantherlake
 	register "cep_enable[VR_DOMAIN_GT]" = "true"
 	register "enable_fast_vmode[VR_DOMAIN_SA]" = "true"
 	register "cep_enable[VR_DOMAIN_SA]" = "true"
-	register "fast_vmode_i_trip[PTL_CORE_1]" = "{
+	register "fast_vmode_i_trip[PTL_SKU_1]" = "{
 		[VR_DOMAIN_IA] = 63 * 4,
 		[VR_DOMAIN_GT] = 38 * 4,
 		[VR_DOMAIN_SA] = 38 * 4
 	}"
-	register "fast_vmode_i_trip[PTL_CORE_2]" = "{
-		[VR_DOMAIN_IA] = 63 * 4,
-		[VR_DOMAIN_GT] = 38 * 4,
-		[VR_DOMAIN_SA] = 38 * 4
-	}"
-	register "fast_vmode_i_trip[PTL_CORE_3]" = "{
+	register "fast_vmode_i_trip[PTL_SKU_2]" = "{
 		[VR_DOMAIN_IA] = 75 * 4,
 		[VR_DOMAIN_GT] = 75 * 4,
 		[VR_DOMAIN_SA] = 38 * 4
 	}"
-
+	register "fast_vmode_i_trip[PTL_SKU_3]" = "{
+		[VR_DOMAIN_IA] = 75 * 4,
+		[VR_DOMAIN_GT] = 38 * 4,
+		[VR_DOMAIN_SA] = 38 * 4
+	}"
+	register "fast_vmode_i_trip[PTL_SKU_5]" = "{
+		[VR_DOMAIN_IA] = 63 * 4,
+		[VR_DOMAIN_GT] = 38 * 4,
+		[VR_DOMAIN_SA] = 38 * 4
+	}"
+	register "fast_vmode_i_trip[PTL_SKU_6]" = "{
+		[VR_DOMAIN_IA] = 75 * 4,
+		[VR_DOMAIN_GT] = 75 * 4,
+		[VR_DOMAIN_SA] = 38 * 4
+	}"
+	register "fast_vmode_i_trip[PTL_SKU_7]" = "{
+		[VR_DOMAIN_IA] = 75 * 4,
+		[VR_DOMAIN_GT] = 38 * 4,
+		[VR_DOMAIN_SA] = 38 * 4
+	}"
 	# Set on-board graphics as primary display
 	register "skip_ext_gfx_scan" = "true"
 

From c078552e712cd8b2a69bdca41ca6c84826a70756 Mon Sep 17 00:00:00 2001
From: Bora Guvendik <bora.guvendik@intel.com>
Date: Mon, 2 Feb 2026 15:12:48 -0800
Subject: [PATCH 3292/3886] soc/intel: Replace sa_get_tseg_size() with
 CONFIG_SMM_TSEG_SIZE
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Remove the sa_get_tseg_size() function and replace all its usage with
CONFIG_SMM_TSEG_SIZE configuration option. The TSEG size is now
obtained directly from the configuration instead of being calculated
dynamically. The existing calculation assumes GSM and TSEG regions are
contiguous, but there is no guarantee this is always true depending on
how FSP operates. This could lead to incorrect size calculations.
Using CONFIG_SMM_TSEG_SIZE is more reliable as this value is provided
to the FSP during initialization.

This change:
- Removes sa_get_tseg_size() function declaration and implementation
- Updates smm_region() to use CONFIG_SMM_TSEG_SIZE directly
- Updates Alder Lake, Meteor Lake, and Panther Lake system agent code
to use CONFIG_SMM_TSEG_SIZE instead of sa_get_tseg_size()

Before (sa_get_tseg_size):

[SPEW ]  TsegBase = 0x78000000
[SPEW ]  GsmBase = 0x7BC00000
[DEBUG]  sa_get_tseg_size:0x3c00000
[DEBUG]  New SMBASE=0x7b5ec000 IEDBASE=0x7b800000
[DEBUG]  Writing SMRR. base = 0x78000006, mask=0xfc400c00
System hangs during SMM relocation

After (CONFIG_SMM_TSEG_SIZE):

[SPEW ]  TsegBase = 0x78000000
[SPEW ]  GsmBase = 0x7BC00000
[DEBUG]  CONFIG_SMM_TSEG_SIZE:0x2000000
[DEBUG]  New SMBASE=0x799ec000 IEDBASE=0x79c00000
[DEBUG]  Writing SMRR. base = 0x78000006, mask=0xfe000c00
[DEBUG]  Relocation complete.
System boots successfully

BUG=none

Change-Id: Ie2a1f3dd68941924e056a12f01857c1182b69198
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91063
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Kim, Wonkyu <wonkyu.kim@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
---
 src/soc/intel/alderlake/systemagent.c                        | 2 +-
 src/soc/intel/common/block/include/intelblocks/systemagent.h | 2 --
 src/soc/intel/common/block/systemagent/memmap.c              | 2 +-
 src/soc/intel/common/block/systemagent/systemagent_early.c   | 5 -----
 src/soc/intel/meteorlake/systemagent.c                       | 2 +-
 src/soc/intel/pantherlake/systemagent.c                      | 2 +-
 6 files changed, 4 insertions(+), 11 deletions(-)

diff --git a/src/soc/intel/alderlake/systemagent.c b/src/soc/intel/alderlake/systemagent.c
index be0c6996a4..bbc421b0cb 100644
--- a/src/soc/intel/alderlake/systemagent.c
+++ b/src/soc/intel/alderlake/systemagent.c
@@ -116,7 +116,7 @@ void soc_add_configurable_mmio_resources(struct device *dev, int *resource_cnt)
 	}
 
 	/* TSEG */
-	size = sa_get_tseg_size();
+	size = CONFIG_SMM_TSEG_SIZE;
 	tseg_base = sa_get_tseg_base();
 	if (size > 0)
 		set_mmio_resource(&(cfg_rsrc[count++]), tseg_base, size, "TSEG");
diff --git a/src/soc/intel/common/block/include/intelblocks/systemagent.h b/src/soc/intel/common/block/include/intelblocks/systemagent.h
index a3ae8c38bf..5047f1d9aa 100644
--- a/src/soc/intel/common/block/include/intelblocks/systemagent.h
+++ b/src/soc/intel/common/block/include/intelblocks/systemagent.h
@@ -91,8 +91,6 @@ uintptr_t sa_get_tolud_base(void);
 uintptr_t sa_get_gsm_base(void);
 /* API to get TSEG base address */
 uintptr_t sa_get_tseg_base(void);
-/* API to get TSEG size */
-size_t sa_get_tseg_size(void);
 /* API to lock PAM registers */
 void sa_lock_pam(void);
 /* API to get MMIO config size */
diff --git a/src/soc/intel/common/block/systemagent/memmap.c b/src/soc/intel/common/block/systemagent/memmap.c
index 3b0fb6e8ae..9a3971098f 100644
--- a/src/soc/intel/common/block/systemagent/memmap.c
+++ b/src/soc/intel/common/block/systemagent/memmap.c
@@ -54,7 +54,7 @@
 void smm_region(uintptr_t *start, size_t *size)
 {
 	*start = sa_get_tseg_base();
-	*size = sa_get_tseg_size();
+	*size = CONFIG_SMM_TSEG_SIZE;
 }
 
 void fill_postcar_frame(struct postcar_frame *pcf)
diff --git a/src/soc/intel/common/block/systemagent/systemagent_early.c b/src/soc/intel/common/block/systemagent/systemagent_early.c
index aecdfbb429..993d008eb6 100644
--- a/src/soc/intel/common/block/systemagent/systemagent_early.c
+++ b/src/soc/intel/common/block/systemagent/systemagent_early.c
@@ -146,11 +146,6 @@ uintptr_t sa_get_tseg_base(void)
 	return ALIGN_DOWN(pci_read_config32(SA_DEV_ROOT, TSEG), 1*MiB);
 }
 
-size_t sa_get_tseg_size(void)
-{
-	return sa_get_gsm_base() - sa_get_tseg_base();
-}
-
 union dpr_register txt_get_chipset_dpr(void)
 {
 	return (union dpr_register) { .raw = pci_read_config32(SA_DEV_ROOT, DPR) };
diff --git a/src/soc/intel/meteorlake/systemagent.c b/src/soc/intel/meteorlake/systemagent.c
index bb841aa60b..9dc771f6e2 100644
--- a/src/soc/intel/meteorlake/systemagent.c
+++ b/src/soc/intel/meteorlake/systemagent.c
@@ -108,7 +108,7 @@ void soc_add_configurable_mmio_resources(struct device *dev, int *resource_cnt)
 	}
 
 	/* TSEG */
-	size = sa_get_tseg_size();
+	size = CONFIG_SMM_TSEG_SIZE;
 	tseg_base = sa_get_tseg_base();
 	if (size > 0)
 		set_mmio_resource(&(cfg_rsrc[count++]), tseg_base, size, "TSEG");
diff --git a/src/soc/intel/pantherlake/systemagent.c b/src/soc/intel/pantherlake/systemagent.c
index c1a081cb1b..f88aedb95c 100644
--- a/src/soc/intel/pantherlake/systemagent.c
+++ b/src/soc/intel/pantherlake/systemagent.c
@@ -105,7 +105,7 @@ void soc_add_configurable_mmio_resources(struct device *dev, int *resource_cnt)
 	}
 
 	/* TSEG */
-	size = sa_get_tseg_size();
+	size = CONFIG_SMM_TSEG_SIZE;
 	tseg_base = sa_get_tseg_base();
 	if (size > 0)
 		set_mmio_resource(&(cfg_rsrc[count++]), tseg_base, size, "TSEG");

From 8790998fa5ec1c64dd732760cdf5a6627cb87caa Mon Sep 17 00:00:00 2001
From: Subrata Banik <subratabanik@google.com>
Date: Sun, 8 Feb 2026 00:23:37 +0530
Subject: [PATCH 3293/3886] util/font: Add bitmapped font generation utility

This adds generate_font.py, a Python utility designed to convert
standard TTF/OTF files into a compact bitmapped format suitable for
firmware framebuffers.

Key features:
- Generates a left-aligned (normalized) bitmapped table to eliminate
  dead space in font glyphs.
- Outputs a character width table to support proportional spacing.
- Exports FONT_HEIGHT and FONT_WIDTH macros for C synchronization.
- Limits output to printable ASCII (32-126) to minimize binary bloat.

The tool uses the Pillow (PIL) library to rasterize glyphs and is
intended to be used during the build process to generate C source
files for splash screen text rendering.

Usage:
  python util/font/generate_font.py <font.ttf> > font_table.c

Change-Id: Iec8907f1a5f24d61822230f6a22295c8382d2229
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91122
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
---
 util/font/generate_font.py | 124 +++++++++++++++++++++++++++++++++++++
 1 file changed, 124 insertions(+)
 create mode 100644 util/font/generate_font.py

diff --git a/util/font/generate_font.py b/util/font/generate_font.py
new file mode 100644
index 0000000000..4af3ed0434
--- /dev/null
+++ b/util/font/generate_font.py
@@ -0,0 +1,124 @@
+#!/usr/bin/env python3
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+"""
+This utility generates a compressed bitmapped font table from a TTF/OTF file.
+The output is a C source file containing:
+1. Font dimensions and range macros.
+2. A normalized (left-aligned) bitmapped font table.
+3. A character width table for proportional spacing.
+
+Usage:
+  python generate_font.py <path_to_ttf> > font_table.c
+"""
+
+from PIL import Image, ImageFont, ImageDraw
+import sys
+import os
+
+# FONT DIMENSIONS
+FONT_SIZE = 19
+CANVAS_WIDTH = 16
+CANVAS_HEIGHT = 24
+Y_OFFSET = -2
+
+# PRINTABLE ASCII RANGE
+START_CHAR = 32
+END_CHAR = 126
+NUM_CHARS = END_CHAR - START_CHAR + 1
+
+def generate_c_table(font_path):
+    if not os.path.exists(font_path):
+        print(f"Error: Font file '{font_path}' not found.", file=sys.stderr)
+        sys.exit(1)
+
+    try:
+        font = ImageFont.truetype(font_path, FONT_SIZE)
+    except OSError:
+        print(f"Error: Could not open font file '{font_path}'.", file=sys.stderr)
+        sys.exit(1)
+
+    # Header for the generated C file
+    print("/* SPDX-License-Identifier: GPL-2.0-or-later */\n")
+    print("/*")
+    print(" * THIS FILE WAS AUTOMATICALLY GENERATED. DO NOT EDIT.")
+    print(f" * Source: {os.path.basename(font_path)}")
+    print(f" * Command: python util/font/{os.path.basename(__file__)} {font_path}")
+    print(" */\n")
+    print("#include <stdint.h>\n")
+
+    # 1. Output the Macros for C code usage
+    print(f"#define FONT_WIDTH      {CANVAS_WIDTH}")
+    print(f"#define FONT_HEIGHT     {CANVAS_HEIGHT}")
+    print(f"#define FONT_START_CHAR {START_CHAR}")
+    print(f"#define FONT_END_CHAR   {END_CHAR}")
+    print(f"#define FONT_NUM_CHARS  (FONT_END_CHAR - FONT_START_CHAR + 1)\n")
+
+    widths = []
+
+    # 2. Generate packed font table with block formatting
+    print(f"const uint16_t font_table[FONT_NUM_CHARS][FONT_HEIGHT] = {{")
+
+    for char_code in range(START_CHAR, END_CHAR + 1):
+        char = chr(char_code)
+        image = Image.new("1", (CANVAS_WIDTH, CANVAS_HEIGHT), 0)
+        draw = ImageDraw.Draw(image)
+        draw.text((0, Y_OFFSET), char, font=font, fill=1)
+
+        pixels = list(image.getdata())
+        rows = []
+        global_mask = 0
+
+        for y in range(CANVAS_HEIGHT):
+            row_val = 0
+            base = y * CANVAS_WIDTH
+            for x in range(CANVAS_WIDTH):
+                if pixels[base + x]:
+                    row_val |= (1 << ((CANVAS_WIDTH - 1) - x))
+            rows.append(row_val)
+            global_mask |= row_val
+
+        # Dead space removal / Normalization
+        left_shift = 0
+        actual_width = 0
+        if global_mask > 0:
+            temp_mask = global_mask
+            while not (temp_mask & 0x8000):
+                temp_mask <<= 1
+                left_shift += 1
+
+            rightmost_bit = 0
+            for i in range(CANVAS_WIDTH):
+                if (global_mask >> i) & 1:
+                    rightmost_bit = i
+                    break
+            actual_width = ((CANVAS_WIDTH - 1) - left_shift) - rightmost_bit + 1
+        else:
+            actual_width = 6 # Default space width
+
+        widths.append(actual_width)
+
+        # Format the pre-shifted hex rows into blocks of 8
+        hex_values = [f"0x{(row << left_shift) & 0xFFFF:04x}" for row in rows]
+        char_repr = f"'{char}'" if char not in ["'", "\\"] else f"'\\{char}'"
+
+        print(f"\t[0x{char_code:02x} - FONT_START_CHAR] = {{")
+        for i in range(0, len(hex_values), 8):
+            line = ", ".join(hex_values[i:i+8])
+            print(f"\t\t{line},")
+        print(f"\t}}, /* {char_repr} */")
+
+    print("};\n")
+
+    # 3. Output Width Table
+    print(f"const uint8_t font_widths[FONT_NUM_CHARS] = {{")
+    for i, w in enumerate(widths):
+        char_code = i + START_CHAR
+        print(f"\t[0x{char_code:02x} - FONT_START_CHAR] = {w},")
+    print("};")
+
+if __name__ == "__main__":
+    if len(sys.argv) < 2:
+        print(f"Usage: python3 {sys.argv[0]} <path_to_ttf_file>")
+        sys.exit(1)
+    generate_c_table(sys.argv[1])

From e942bc658f488351d7644ebf0b18882c34b46527 Mon Sep 17 00:00:00 2001
From: David Wu <david_wu@quanta.corp-partner.google.com>
Date: Wed, 4 Feb 2026 20:29:24 +0800
Subject: [PATCH 3294/3886] mb/google/brox: Create juchi variant

Create the juchi variant of the jubilant project by
copying the files to a new directory named for the variant.

BUG=b:481602501
TEST=util/abuild/abuild -p none -t google/brox -x -a
make sure the build includes GOOGLE_JUCHI.

Change-Id: I4a1919f6a2480e4e2f993fa24658836a1739714c
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91090
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
---
 src/mainboard/google/brox/Kconfig             |  11 +
 src/mainboard/google/brox/Kconfig.name        |   3 +
 .../google/brox/variants/juchi/Makefile.mk    |  14 +
 .../google/brox/variants/juchi/data.vbt       | Bin 0 -> 8704 bytes
 .../google/brox/variants/juchi/fw_config.c    | 102 ++++
 .../google/brox/variants/juchi/gpio.c         | 242 +++++++++
 .../brox/variants/juchi/include/variant/ec.h  |   8 +
 .../variants/juchi/include/variant/gpio.h     |  13 +
 .../variants/juchi/include/variant/hda_verb.h | 133 +++++
 .../google/brox/variants/juchi/memory.c       | 109 ++++
 .../brox/variants/juchi/memory/Makefile.mk    |  10 +
 .../juchi/memory/dram_id.generated.txt        |  13 +
 .../variants/juchi/memory/mem_parts_used.txt  |   7 +
 .../brox/variants/juchi/overridetree.cb       | 481 ++++++++++++++++++
 .../google/brox/variants/juchi/ramstage.c     |  43 ++
 .../google/brox/variants/juchi/smihandler.c   |  21 +
 .../google/brox/variants/juchi/variant.c      |  46 ++
 17 files changed, 1256 insertions(+)
 create mode 100644 src/mainboard/google/brox/variants/juchi/Makefile.mk
 create mode 100644 src/mainboard/google/brox/variants/juchi/data.vbt
 create mode 100644 src/mainboard/google/brox/variants/juchi/fw_config.c
 create mode 100644 src/mainboard/google/brox/variants/juchi/gpio.c
 create mode 100644 src/mainboard/google/brox/variants/juchi/include/variant/ec.h
 create mode 100644 src/mainboard/google/brox/variants/juchi/include/variant/gpio.h
 create mode 100644 src/mainboard/google/brox/variants/juchi/include/variant/hda_verb.h
 create mode 100644 src/mainboard/google/brox/variants/juchi/memory.c
 create mode 100644 src/mainboard/google/brox/variants/juchi/memory/Makefile.mk
 create mode 100644 src/mainboard/google/brox/variants/juchi/memory/dram_id.generated.txt
 create mode 100644 src/mainboard/google/brox/variants/juchi/memory/mem_parts_used.txt
 create mode 100644 src/mainboard/google/brox/variants/juchi/overridetree.cb
 create mode 100644 src/mainboard/google/brox/variants/juchi/ramstage.c
 create mode 100644 src/mainboard/google/brox/variants/juchi/smihandler.c
 create mode 100644 src/mainboard/google/brox/variants/juchi/variant.c

diff --git a/src/mainboard/google/brox/Kconfig b/src/mainboard/google/brox/Kconfig
index 45e989c8e5..bb4d3746b2 100644
--- a/src/mainboard/google/brox/Kconfig
+++ b/src/mainboard/google/brox/Kconfig
@@ -98,6 +98,14 @@ config BOARD_GOOGLE_JUBILANT
 	select MAINBOARD_HAS_GOOGLE_STRAUSS_KEYBOARD
 	select USE_UNIFIED_AP_FIRMWARE_FOR_UFS_AND_NON_UFS
 
+config BOARD_GOOGLE_JUCHI
+	select BOARD_GOOGLE_BASEBOARD_BROX
+	select CHROMEOS_WIFI_SAR if CHROMEOS
+	select DRIVERS_GENERIC_ALC1015
+	select DRIVERS_I2C_SX9324
+	select MAINBOARD_HAS_GOOGLE_STRAUSS_KEYBOARD
+	select USE_UNIFIED_AP_FIRMWARE_FOR_UFS_AND_NON_UFS
+
 config BOARD_GOOGLE_CABOC
 	select BOARD_GOOGLE_BASEBOARD_BROX
 	select CHROMEOS_WIFI_SAR if CHROMEOS
@@ -141,6 +149,7 @@ config PL4_LIMIT_FOR_CRITICAL_BAT_BOOT
 	default 9 if BOARD_GOOGLE_BROX_RTK_EC
 	default 14 if BOARD_GOOGLE_CABOC
 	default 14 if BOARD_GOOGLE_JUBILANT
+	default 14 if BOARD_GOOGLE_JUCHI
 	default 40 if BOARD_GOOGLE_LOTSO
 	help
 	  Select this if the variant has to boot even with low battery, critical battery
@@ -181,6 +190,7 @@ config MAINBOARD_PART_NUMBER
 	default "Caboc" if BOARD_GOOGLE_CABOC
 	default "Greenbayupoc" if BOARD_GOOGLE_GREENBAYUPOC
 	default "Jubilant" if BOARD_GOOGLE_JUBILANT
+	default "Juchi" if BOARD_GOOGLE_JUCHI
 	default "Lotso" if BOARD_GOOGLE_LOTSO
 
 config VARIANT_DIR
@@ -193,6 +203,7 @@ config VARIANT_DIR
 	default "lotso" if BOARD_GOOGLE_LOTSO
 	default "greenbayupoc" if BOARD_GOOGLE_GREENBAYUPOC
 	default "jubilant" if BOARD_GOOGLE_JUBILANT
+	default "juchi" if BOARD_GOOGLE_JUCHI
 
 config VBOOT
 	select VBOOT_LID_SWITCH
diff --git a/src/mainboard/google/brox/Kconfig.name b/src/mainboard/google/brox/Kconfig.name
index 4c73eebcf3..ec754a68a7 100644
--- a/src/mainboard/google/brox/Kconfig.name
+++ b/src/mainboard/google/brox/Kconfig.name
@@ -27,5 +27,8 @@ config BOARD_GOOGLE_JUBILANT
 	  - Acer Chromebook Plus 514
 	  - Acer Chromebook Plus 516 (CB516-1H,CB516-1HT)
 
+config BOARD_GOOGLE_JUCHI
+	bool "->  Juchi"
+
 config BOARD_GOOGLE_LOTSO
 	bool "->  Lotso (Lenovo Chromebook Plus 2-in-1)"
diff --git a/src/mainboard/google/brox/variants/juchi/Makefile.mk b/src/mainboard/google/brox/variants/juchi/Makefile.mk
new file mode 100644
index 0000000000..bb7543b968
--- /dev/null
+++ b/src/mainboard/google/brox/variants/juchi/Makefile.mk
@@ -0,0 +1,14 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
+bootblock-y += gpio.c
+
+romstage-y += gpio.c
+romstage-y += memory.c
+romstage-$(CONFIG_FW_CONFIG) += variant.c
+
+ramstage-$(CONFIG_FW_CONFIG) += fw_config.c
+ramstage-$(CONFIG_FW_CONFIG) += variant.c
+ramstage-y += gpio.c
+ramstage-y += ramstage.c
+
+smm-y += smihandler.c
diff --git a/src/mainboard/google/brox/variants/juchi/data.vbt b/src/mainboard/google/brox/variants/juchi/data.vbt
new file mode 100644
index 0000000000000000000000000000000000000000..716d09f557dab5fec2978a41ed2c332c3d7db3fe
GIT binary patch
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HcmV?d00001

diff --git a/src/mainboard/google/brox/variants/juchi/fw_config.c b/src/mainboard/google/brox/variants/juchi/fw_config.c
new file mode 100644
index 0000000000..6d50ca2495
--- /dev/null
+++ b/src/mainboard/google/brox/variants/juchi/fw_config.c
@@ -0,0 +1,102 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <bootstate.h>
+#include <baseboard/gpio.h>
+#include <baseboard/variants.h>
+#include <console/console.h>
+#include <fw_config.h>
+
+static const struct pad_config fp_disable_pads[] = {
+	/* D2  : ISH_GP2 ==> EN_FP_PWR (NC) */
+	PAD_NC(GPP_D2, NONE),
+	/* GPP_D3 : IPCH_FP_BOOT0 (active high) (NC) */
+	PAD_NC(GPP_D3, NONE),
+	/* GPP_D15 : FPMCU_RST_J_SUB_L (active low) (NC) */
+	PAD_NC(GPP_D15, NONE),
+	/* GPP_D13 : FP GSPI INT (NC)  */
+	PAD_NC(GPP_D13, NONE),
+	/* GPP_F11 : FP GSPI CLK (NC) */
+	PAD_NC(GPP_F11, NONE),
+	/* GPP_F12 : FP GSPI DO (NC) */
+	PAD_NC(GPP_F12, NONE),
+	/* GPP_F13 : FP GSPI DI (NC) */
+	PAD_NC(GPP_F13, NONE),
+	/* GPP_F16 : FP GSPI CS (NC) */
+	PAD_NC(GPP_F16, NONE),
+};
+
+static const struct pad_config lte_disable_pads[] = {
+	/* GPP_E11 : WWAN_CFG0 */
+	PAD_NC(GPP_E11, NONE),
+	/* GPP_E17 : WWAN_CFG02 */
+	PAD_NC(GPP_E17, NONE),
+	/* GPP_D7 :WWAN_RF_DISABLE_ODL */
+	PAD_NC(GPP_D7, NONE),
+	/* GPP_D5 : WWAN_SAR_ODL */
+	PAD_NC(GPP_D5, NONE),
+	/* GPP_F21 : WWAN_FCPO_L */
+	PAD_NC(GPP_F21, NONE),
+	/* GPP_S4 : WWAN_WLAN_COEX1 */
+	PAD_NC(GPP_S4, NONE),
+	/* GPP_S5 : WWAN_WLAN_COEX2 */
+	PAD_NC(GPP_S5, NONE),
+	/* GPP_F6 : WWAN_WLAN_COEX3 */
+	PAD_NC(GPP_F6, NONE),
+	/* GPP_A12 : WWAN_PWR_EN */
+	PAD_NC(GPP_A12, NONE),
+	/* GPP_H23 : WWAN_RST_L */
+	PAD_NC(GPP_H23, NONE),
+	/* GPP_H19 : SRCCLKREQ4_L ==> SAR1_INT_L (NC) */
+	PAD_NC(GPP_H19, NONE),
+};
+
+static const struct pad_config lte_sar_disable_pads[] = {
+	/* GPP_D5 : WWAN_SAR_ODL */
+	PAD_NC(GPP_D5, NONE),
+	/* GPP_S4 : WWAN_WLAN_COEX1 */
+	PAD_NC(GPP_S4, NONE),
+	/* GPP_S5 : WWAN_WLAN_COEX2 */
+	PAD_NC(GPP_S5, NONE),
+	/* GPP_F6 : WWAN_WLAN_COEX3 */
+	PAD_NC(GPP_F6, NONE),
+	/* GPP_H19 : SRCCLKREQ4_L ==> SAR1_INT_L (NC) */
+	PAD_NC(GPP_H19, NONE),
+};
+
+static const struct pad_config nvme_disable_pads[] = {
+	/* GPP_F9 : SSD_PERST_L */
+	PAD_NC(GPP_F9, NONE),
+	/* GPP_D11 : EN_PP3300_SSD (NC) */
+	PAD_NC(GPP_D11, NONE),
+	/* GPP_D8 : SSD_CLKREQ_ODL */
+	PAD_NC(GPP_D8, NONE),
+};
+
+static void fw_config_handle(void *unused)
+{
+	if (!fw_config_is_provisioned()) {
+		printk(BIOS_WARNING, "FW_CONFIG is unprovisioned. Skip disable device's pads.\n");
+		return;
+	}
+
+	if (fw_config_probe(FW_CONFIG(FPMCU, FPMCU_ABSENT))) {
+		printk(BIOS_INFO, "Disable Fingerprint GPIOs by fw_config.\n");
+		gpio_configure_pads(fp_disable_pads, ARRAY_SIZE(fp_disable_pads));
+	}
+
+	if (fw_config_probe(FW_CONFIG(DB_USB, DB_1A))) {
+		printk(BIOS_INFO, "Disable LTE-related GPIO pins by fw_config.\n");
+		gpio_configure_pads(lte_disable_pads, ARRAY_SIZE(lte_disable_pads));
+	}
+
+	if (fw_config_probe(FW_CONFIG(DB_USB, DB_1A_LTE))) {
+		printk(BIOS_INFO, "Disable LTE's Sar sensor related GPIO pins by fw_config.\n");
+		gpio_configure_pads(lte_sar_disable_pads, ARRAY_SIZE(lte_sar_disable_pads));
+	}
+
+	if (!fw_config_probe(FW_CONFIG(STORAGE, STORAGE_NVME))) {
+		printk(BIOS_INFO, "Disable NVMe GPIO pins by fw_config.\n");
+		gpio_configure_pads(nvme_disable_pads, ARRAY_SIZE(nvme_disable_pads));
+	}
+}
+BOOT_STATE_INIT_ENTRY(BS_DEV_ENABLE, BS_ON_ENTRY, fw_config_handle, NULL);
diff --git a/src/mainboard/google/brox/variants/juchi/gpio.c b/src/mainboard/google/brox/variants/juchi/gpio.c
new file mode 100644
index 0000000000..c633a9116c
--- /dev/null
+++ b/src/mainboard/google/brox/variants/juchi/gpio.c
@@ -0,0 +1,242 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <baseboard/gpio.h>
+#include <baseboard/variants.h>
+#include <commonlib/helpers.h>
+#include <soc/gpio.h>
+#include <vendorcode/google/chromeos/chromeos.h>
+
+/* Pad configuration in ramstage */
+static const struct pad_config override_gpio_table[] = {
+	/* GPP_E11 : [NF2: THC0_SPI1_CLK NF6: USB_C_GPP_E11 NF7: GSPI0_CLK] ==> WWAN_CFG0 */
+	PAD_CFG_GPI(GPP_E11, NONE, PLTRST),
+	/* GPP_E17 : [NF2: THC0_SPI1_INT# NF6: USB_C_GPP_E17] ==> WWAN_CFG02 */
+	PAD_CFG_GPI(GPP_E17, NONE, PLTRST),
+	/* GPP_D7 : SRCCLKREQ2_L ==> WWAN_RF_DISABLE (Reserved) */
+	PAD_NC_LOCK(GPP_D7, NONE, LOCK_CONFIG),
+	/* GPP_D5 : SRCCLKREQ0_L ==> WWAN_SAR_ODL */
+	PAD_CFG_GPO(GPP_D5, 1, DEEP),
+	/* GPP_S4 : SNDW2_CLK/DMIC_CLK_B0 ==> WWAN_WLAN_COEX1 */
+	PAD_CFG_GPI(GPP_S4, NONE, DEEP),
+	/* GPP_S5 : SNDW2_DATA/DMIC_CLK_B1 ==> WWAN_WLAN_COEX2 */
+	PAD_CFG_GPI(GPP_S5, NONE, DEEP),
+	/* GPP_F6 : [NF1: CNV_PA_BLANKING NF6: USB_C_GPP_F6] ==>WWAN_WLAN_COEX3 */
+	PAD_CFG_GPI(GPP_F6, NONE, DEEP),
+	/*
+	 * GPP_A12 : [NF1: SATAXPCIE1 NF2: SATAGP1 NF4: SRCCLKREQ9B# NF6: USB_C_GPP_A12]
+	 *  ==> WWAN_PWR_EN
+	 */
+	PAD_CFG_GPO_LOCK(GPP_A12, 1, LOCK_CONFIG),
+	/* GPP_H23 : SRCCLKREQ5_L ==> WWAN_RST_L */
+	PAD_CFG_GPO_LOCK(GPP_H23, 0, LOCK_CONFIG),
+	/* GPP_F21 : [NF1: Reserved NF6: USB_C_GPP_F21] ==> WWAN_FCPO_L */
+	PAD_CFG_GPO_LOCK(GPP_F21, 0, LOCK_CONFIG),
+
+	/* GPP_H19 : SRCCLKREQ4_L ==> SAR1_INT_L */
+	PAD_CFG_GPI_APIC_LOCK(GPP_H19, NONE, LEVEL, NONE, LOCK_CONFIG),
+
+	/* GPP_D2 : [NF1: ISH_GP2 NF2: BK2 NF5: SBK2 NF6: USB_C_GPP_D2] ==> EN_FP_PWR (active high) */
+	PAD_CFG_GPO_LOCK(GPP_D2, 0, LOCK_CONFIG),
+	/* GPP_D3 : [NF1: ISH_GP3 NF2: BK3 NF5: SBK3 NF6: USB_C_GPP_D3] ==> IPCH_FP_BOOT0 (active high) */
+	PAD_CFG_GPO_LOCK(GPP_D3, 0, LOCK_CONFIG),
+	/* GPP_D15 : ISH_UART0_RTS_L/I2C7B_SDA ==> FPMCU_RST_J_SUB_L (active low) */
+	PAD_CFG_GPO_LOCK(GPP_D15, 0, LOCK_CONFIG),
+	/* GPP_D13 : [NF1: ISH_UART0_RXD NF3: I2C6_SDA NF6: USB_C_GPP_D13] ==> FP GSPI INT */
+	PAD_CFG_GPI_IRQ_WAKE(GPP_D13, NONE, PWROK, LEVEL, INVERT),
+	/* GPP_F11 : [NF3: THC1_SPI2_CLK NF4: GSPI1_CLK NF6: USB_C_GPP_F11] ==>  FP GSPI CLK */
+	PAD_CFG_NF_LOCK(GPP_F11, NONE, NF4, LOCK_CONFIG),
+	/* GPP_F12 : [NF1: GSXDOUT NF3: THC1_SPI2_IO0 NF4: GSPI1_MOSI NF5: I2C1A_SCL
+	NF6: USB_C_GPP_F12] ==> FP GSPI DO */
+	PAD_CFG_NF_LOCK(GPP_F12, NONE, NF4, LOCK_CONFIG),
+	/* GPP_F13 : [NF1: GSXSLOAD NF3: THC1_SPI2_IO1 NF4: GSPI1_MISIO NF5: I2C1A_SDA
+	NF6: USB_C_GPP_F13] ==> SFP GSPI DI */
+	PAD_CFG_NF_LOCK(GPP_F13, NONE, NF4, LOCK_CONFIG),
+	/* GPP_F16 : [NF1: GSXCLK NF3: THC1_SPI2_CS# NF4: GSPI1_CS0# NF6: USB_C_GPP_F16] ==> FP GSPI CS */
+	PAD_CFG_NF_LOCK(GPP_F16, NONE, NF4, LOCK_CONFIG),
+
+	/* GPP_F14 : [NF1: GSXDIN NF3: THC1_SPI2_IO2 NF6: USB_C_GPP_F14] ==> PCH_TCHSCR_REPORT_EN */
+	PAD_CFG_GPO(GPP_F14, 0, DEEP),
+
+	/* GPP_E7 : [NF1: PROC_GP1 NF6: USB_C_GPP_E7] ==> EN_UCAM_PWR */
+	PAD_CFG_GPO(GPP_E7, 1, PLTRST),
+
+	/* GPP_B5 : [NF1: ISH_I2C0_SDA NF2: I2C2_SDA NF6: USB_C_GPP_B5] ==> PCH_I2C_MISC_R_SDA (SAR, HP) */
+	PAD_CFG_NF(GPP_B5, NONE, DEEP, NF2),
+	/* GPP_B6 : [NF1: ISH_I2C0_SCL NF2: I2C2_SCL NF6: USB_C_GPP_B6] ==> PCH_I2C_MISC_R_SCL (SAR, HP) */
+	PAD_CFG_NF(GPP_B6, NONE, DEEP, NF2),
+
+	/* GPP_S6 : SNDW3_CLK/DMIC_CLK_A1 ==> HP_INT_L (Headphone interrupt) */
+	PAD_CFG_GPI_INT(GPP_S6, NONE, PLTRST, EDGE_BOTH),
+	/* GPP_D19 : [NF1: I2S_MCLK1_OUT NF6: USB_C_GPP_D19] ==> I2S_MCLK_R (headphone MCLK) */
+	PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1),
+	/* GPP_R0 : [NF1: HDA_BCLK NF2: I2S0_SCLK NF3: DMIC_CLK_B0 NF4: HDAPROC_BCLK] ==> I2S0_SCLK */
+	PAD_CFG_NF(GPP_R0, NONE, PLTRST, NF2),
+	/* GPP_R1 : [NF1: HDA_SYNC NF3: DMIC_CLK_B1] ==> I2S0_SFRM */
+	PAD_CFG_NF(GPP_R1, NONE, PLTRST, NF2),
+	/* GPP_R2 : [NF1: HDA_SDO NF2: I2S0_TXD NF4: HDAPROC_SDO] ==> I2S0_TXD */
+	PAD_CFG_NF(GPP_R2, NONE, PLTRST, NF2),
+	/* GPP_R3 : [NF1: HDA_SDI0 NF2: I2S0_RXD NF4: HDAPROC_SDI] ==> I2S0_RXD */
+	PAD_CFG_NF(GPP_R3, NONE, PLTRST, NF2),
+
+	/* GPP_F20 : [NF1: Reserved NF6: USB_C_GPP_F20] ==> SPK enable (active high) */
+	PAD_CFG_GPO(GPP_F20, 1, DEEP),
+	/* GPP_S0 : SNDW0_CLL/I2S1_SCLK ==> SPK I2S_CLK */
+	PAD_CFG_NF(GPP_S0, NONE, PLTRST, NF4),
+	/* GPP_S1 : SNDW0_DATA/I2S1_SFRM ==> SPK I2S_FRAME */
+	PAD_CFG_NF(GPP_S1, NONE, PLTRST, NF4),
+	/* GPP_S2 : [NF1: SNDW1_CLK NF2: DMIC_CKL_A0 NF4: I2S1_TXD] ==> SPK I2S_TX */
+	PAD_CFG_NF(GPP_S2, NONE, PLTRST, NF4),
+	/* GPP_S3 : [NF1: SNDW1_DATA NF2: DMIC_DAGPP_D1TA0 NF4: I2S1_RXD] ==> SPK I2S_RX */
+	PAD_CFG_NF(GPP_S3, NONE, PLTRST, NF4),
+
+	/* GPP_R4 : HDA_RST_L/I2S2_SCLK/DMIC_CLK_A0 ==> DMIC_CLK_A0 */
+	PAD_CFG_NF(GPP_R4, NONE, PLTRST, NF3),
+	/* GPP_R5 : HDA_SDI1/I2S2_SFRM/DMIC_DATA0 ==> SDMIC_DATA0 */
+	PAD_CFG_NF(GPP_R5, NONE, PLTRST, NF3),
+	/* GPP_R6 : I2S2_TXD/DMIC_CLK_A1 ==> DMIC_CLK_A1 */
+	PAD_CFG_NF(GPP_R6, NONE, PLTRST, NF3),
+	/* GPP_R7 : I2S2_RXD/DMIC_DATA1 ==> DMIC_DATA1 */
+	PAD_CFG_NF(GPP_R7, NONE, PLTRST, NF3),
+
+	/* GPP_E15 : SRCCLK_OE8_L ==> MEM_STRAP_0 */
+	PAD_CFG_GPI(GPP_E15, NONE, PLTRST),
+	/* GPP_E12 : THC0_SPI1_IO1/I2C0A_SDA/GSPI0_MISO ==> MEM_STRAP_1 */
+	PAD_CFG_GPI(GPP_E12, NONE, PLTRST),
+	/* GPP_E13 : THC0_SPI1_IO0/I2C0A_SCL/GSPI0_MOSI ==> MEM_STRAP_2 */
+	PAD_CFG_GPI(GPP_E13, NONE, PLTRST),
+	/* GPP_E10 : THC0_SPI1_CS_L/GSPI0_CS0_L ==> MEM_STRAP_3 */
+	PAD_CFG_GPI(GPP_E10,  NONE, PLTRST),
+	/* GPP_S7 : SNDW3_DATA/DMIC_DATA1 ==> MEM_CH_SEL */
+	PAD_CFG_GPI(GPP_S7, NONE, DEEP),
+};
+
+/* Early pad configuration in bootblock */
+static const struct pad_config early_gpio_table[] = {
+
+	/*
+	 * GPP_A12 : [NF1: SATAXPCIE1 NF2: SATAGP1 NF4: SRCCLKREQ9B# NF6: USB_C_GPP_A12]
+	 *  ==> WWAN_PWR_EN
+	 */
+	PAD_CFG_GPO_LOCK(GPP_A12, 1, LOCK_CONFIG),
+	/* GPP_H23 : SRCCLKREQ5_L ==> WWAN_RST_L */
+	PAD_CFG_GPO_LOCK(GPP_H23, 0, LOCK_CONFIG),
+	/* GPP_F21 : [NF1: Reserved NF6: USB_C_GPP_F21] ==> WWAN_FCPO_L */
+	PAD_CFG_GPO_LOCK(GPP_F21, 0, LOCK_CONFIG),
+
+	/*
+	 * FP_RST_ODL comes out of reset as hi-z and does not have an external pull-down.
+	 * To ensure proper power sequencing for the FPMCU device, reset signal is driven low
+	 * early on in bootblock, followed by enabling of power. Reset signal is deasserted
+	 * later on in ramstage. Since reset signal is asserted in bootblock, it results in
+	 * FPMCU not working after a S3 resume. This is a known issue.
+	 */
+	/* GPP_D15 : ISH_UART0_RTS_L/I2C7B_SDA ==> FPMCU_RST_J_SUB_L (active low) */
+	PAD_CFG_GPO(GPP_D15, 0, DEEP),
+	/* D2  : ISH_GP2 ==> EN_FP_PWR */
+	PAD_CFG_GPO(GPP_D2, 1, DEEP),
+
+	/* GPP_F9 : [NF1: BOOTMPC NF6: USB_C_GPP_F9] ==> SSD_PERST_L */
+	PAD_CFG_GPO(GPP_F9, 0, DEEP),
+	/* GPP_D11 : [] ==> EN_PP3300_SSD (NC) */
+	PAD_NC(GPP_D11, NONE),
+
+	/* GPP_E2  : THC0_SPI1_IO3 ==> GSC_PCH_INT_ODL */
+	PAD_CFG_GPI_APIC_LOCK(GPP_E2, NONE, LEVEL, INVERT, LOCK_CONFIG),
+	/* GPP_E8 : GPP_E8 ==> PCH_WP_OD */
+	PAD_CFG_GPI_LOCK(GPP_E8, NONE, LOCK_CONFIG),
+	/* GPP_H8 : [NF1: I2C4_SDA NF2: CNV_MFUART2_RXD NF6: USB_C_GPP_H8] ==> PCH_I2C_GSC_SDA */
+	PAD_CFG_NF(GPP_H8, NONE, DEEP, NF1),
+	/* GPP_H9 : [NF1: I2C4_SCL NF2: CNV_MFUART2_TXD] ==> PCH_I2C_GSC_SCL */
+	PAD_CFG_NF(GPP_H9, NONE, DEEP, NF1),
+
+	/* H10 : UART0_RXD ==> UART_PCH_RX_DBG_TX */
+	PAD_CFG_NF(GPP_H10, NONE, PLTRST, NF2),
+	/* H11 : UART0_TXD ==> UART_PCH_TX_DBG_RX */
+	PAD_CFG_NF(GPP_H11, NONE, PLTRST, NF2),
+
+	/* GPP_S7 : SNDW3_DATA/DMIC_DATA1 ==> MEM_CH_SEL */
+	PAD_CFG_GPI(GPP_S7, NONE, DEEP),
+
+	/* CPU PCIe VGPIO for PEG60 */
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_48, NONE, PLTRST, NF1),
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_49, NONE, PLTRST, NF1),
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_50, NONE, PLTRST, NF1),
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_51, NONE, PLTRST, NF1),
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_52, NONE, PLTRST, NF1),
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_53, NONE, PLTRST, NF1),
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_54, NONE, PLTRST, NF1),
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_55, NONE, PLTRST, NF1),
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_56, NONE, PLTRST, NF1),
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_57, NONE, PLTRST, NF1),
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_58, NONE, PLTRST, NF1),
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_59, NONE, PLTRST, NF1),
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_60, NONE, PLTRST, NF1),
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_61, NONE, PLTRST, NF1),
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_62, NONE, PLTRST, NF1),
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_63, NONE, PLTRST, NF1),
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_76, NONE, PLTRST, NF1),
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_77, NONE, PLTRST, NF1),
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_78, NONE, PLTRST, NF1),
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_79, NONE, PLTRST, NF1),
+};
+
+static const struct pad_config romstage_gpio_table[] = {
+	/* GPP_D15 : ISH_UART0_RTS_L/I2C7B_SDA ==> FPMCU_RST_J_SUB_L (active low) */
+	PAD_CFG_GPO(GPP_D15, 0, DEEP),
+	/* D2  : ISH_GP2 ==> EN_FP_PWR */
+	PAD_CFG_GPO(GPP_D2, 0, DEEP),
+
+	/*
+	 * GPP_A12 : [NF1: SATAXPCIE1 NF2: SATAGP1 NF4: SRCCLKREQ9B# NF6: USB_C_GPP_A12]
+	 *  ==> WWAN_PWR_EN
+	 */
+	PAD_CFG_GPO_LOCK(GPP_A12, 1, LOCK_CONFIG),
+	/* GPP_H23 : SRCCLKREQ5_L ==> WWAN_RST_L */
+	PAD_CFG_GPO_LOCK(GPP_H23, 0, LOCK_CONFIG),
+	/* GPP_F21 : [NF1: Reserved NF6: USB_C_GPP_F21] ==> WWAN_FCPO_L */
+	PAD_CFG_GPO_LOCK(GPP_F21, 0, LOCK_CONFIG),
+
+	/* GPP_E15 : SRCCLK_OE8_L ==> MEM_STRAP_0 */
+	PAD_CFG_GPI(GPP_E15, NONE, PLTRST),
+	/* GPP_E12 : THC0_SPI1_IO1/I2C0A_SDA/GSPI0_MISO ==> MEM_STRAP_1 */
+	PAD_CFG_GPI(GPP_E12, NONE, PLTRST),
+	/* GPP_E13 : THC0_SPI1_IO0/I2C0A_SCL/GSPI0_MOSI ==> MEM_STRAP_2 */
+	PAD_CFG_GPI(GPP_E13, NONE, PLTRST),
+	/* GPP_E10 : THC0_SPI1_CS_L/GSPI0_CS0_L ==> MEM_STRAP_3 */
+	PAD_CFG_GPI(GPP_E10,  NONE, PLTRST),
+	/* GPP_S7 : SNDW3_DATA/DMIC_DATA1 ==> MEM_CH_SEL */
+	PAD_CFG_GPI(GPP_S7, NONE, DEEP),
+
+	/* GPP_F7 : [NF6: USB_C_GPP_F7] ==> EN_PP3300_TCHSCR */
+	PAD_CFG_GPO(GPP_F7, 1, PLTRST),
+	/* GPP_F17 : [NF3: THC1_SPI2_RST# NF6: USB_C_GPP_F17] ==> TCHSCR_RST_L */
+	PAD_CFG_GPO(GPP_F17, 0, DEEP),
+
+	/* GPP_F9 : [NF1: BOOTMPC NF6: USB_C_GPP_F9] ==> SSD_PERST_L */
+	PAD_CFG_GPO(GPP_F9, 1, DEEP),
+};
+
+const struct pad_config *variant_gpio_override_table(size_t *num)
+{
+	*num = ARRAY_SIZE(override_gpio_table);
+	return override_gpio_table;
+}
+
+const struct pad_config *variant_early_gpio_table(size_t *num)
+{
+	*num = ARRAY_SIZE(early_gpio_table);
+	return early_gpio_table;
+}
+
+const struct pad_config *variant_romstage_gpio_table(size_t *num)
+{
+	*num = ARRAY_SIZE(romstage_gpio_table);
+	return romstage_gpio_table;
+}
+
+static const struct cros_gpio cros_gpios[] = {
+	CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME),
+	CROS_GPIO_WP_AH(GPIO_PCH_WP, CROS_GPIO_DEVICE_NAME),
+};
+
+DECLARE_WEAK_CROS_GPIOS(cros_gpios);
diff --git a/src/mainboard/google/brox/variants/juchi/include/variant/ec.h b/src/mainboard/google/brox/variants/juchi/include/variant/ec.h
new file mode 100644
index 0000000000..4fc0622f15
--- /dev/null
+++ b/src/mainboard/google/brox/variants/juchi/include/variant/ec.h
@@ -0,0 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#ifndef MAINBOARD_EC_H
+#define MAINBOARD_EC_H
+
+#include <baseboard/ec.h>
+
+#endif /* MAINBOARD_GPIO_H */
diff --git a/src/mainboard/google/brox/variants/juchi/include/variant/gpio.h b/src/mainboard/google/brox/variants/juchi/include/variant/gpio.h
new file mode 100644
index 0000000000..1d660cf503
--- /dev/null
+++ b/src/mainboard/google/brox/variants/juchi/include/variant/gpio.h
@@ -0,0 +1,13 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#ifndef __MAINBOARD_GPIO_H__
+#define __MAINBOARD_GPIO_H__
+
+#include <baseboard/gpio.h>
+
+#define T1_OFF_MS	16
+#define T2_OFF_MS	2
+#define WWAN_FCPO	GPP_F21
+#define WWAN_RST	GPP_H23
+
+#endif /* __MAINBOARD_GPIO_H__ */
diff --git a/src/mainboard/google/brox/variants/juchi/include/variant/hda_verb.h b/src/mainboard/google/brox/variants/juchi/include/variant/hda_verb.h
new file mode 100644
index 0000000000..c0b0eb0733
--- /dev/null
+++ b/src/mainboard/google/brox/variants/juchi/include/variant/hda_verb.h
@@ -0,0 +1,133 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef MAINBOARD_HDA_VERB_H
+#define MAINBOARD_HDA_VERB_H
+
+#include <device/azalia_device.h>
+
+const u32 cim_verb_data[] = {
+	/* coreboot specific header */
+	0x10ec0256,	// Codec Vendor / Device ID: Realtek ALC256
+	0x10ec12ac,	// Subsystem ID
+	0x00000013,	// Number of jacks (NID entries)
+
+	AZALIA_RESET(0x1),
+	/* NID 0x01, HDA Codec Subsystem ID Verb table */
+	AZALIA_SUBVENDOR(0, 0x10ec12ac),
+
+	/* Pin Widget Verb Table */
+
+	/*
+	 * DMIC
+	 * Requirement is to use PCH DMIC. Hence,
+	 * commented out codec's Internal DMIC.
+	 * AZALIA_PIN_CFG(0, 0x12, 0x90A60130),
+	 * AZALIA_PIN_CFG(0, 0x13, 0x40000000),
+	 */
+
+	/* Pin widget 0x14 - Front (Port-D) */
+	AZALIA_PIN_CFG(0, 0x14, 0x90170110),
+	/* Pin widget 0x18 - NPC */
+	AZALIA_PIN_CFG(0, 0x18, 0x411111F0),
+	/* Pin widget 0x19 - MIC2 (Port-F) */
+	AZALIA_PIN_CFG(0, 0x19, 0x04A11040),
+	/* Pin widget 0x1A - LINE1 (Port-C) */
+	AZALIA_PIN_CFG(0, 0x1a, 0x411111F0),
+	/* Pin widget 0x1B - NPC */
+	AZALIA_PIN_CFG(0, 0x1b, 0x411111F0),
+	/* Pin widget 0x1D - BEEP-IN */
+	AZALIA_PIN_CFG(0, 0x1d, 0x40610041),
+	/* Pin widget 0x1E - NPC */
+	AZALIA_PIN_CFG(0, 0x1e, 0x411111F0),
+	/* Pin widget 0x21 - HP1-OUT (Port-I) */
+	AZALIA_PIN_CFG(0, 0x21, 0x04211020),
+	/*
+	 * Widget node 0x20 - 1
+	 * Codec hidden reset and speaker power 2W/4ohm
+	 */
+	0x0205001A,
+	0x0204C003,
+	0x02050038,
+	0x02047901,
+	/*
+	 * Widget node 0x20 - 2
+	 * Class D power on Reset
+	 */
+	0x0205003C,
+	0x02040354,
+	0x0205003C,
+	0x02040314,
+	/*
+	 * Widget node 0x20 - 3
+	 * Disable AGC and set AGC limit to -1.5dB
+	 */
+	0x02050016,
+	0x02040C50,
+	0x02050012,
+	0x0204EBC1,
+	/*
+	 * Widget node 0x20 - 4
+	 * Set AGC Post gain +1.5dB then Enable AGC
+	 */
+	0x02050013,
+	0x02044023,
+	0x02050016,
+	0x02040E50,
+	/*
+	 * Widget node 0x20 - 5
+	 * Silence detector enabling + Set EAPD to verb control
+	 */
+	0x02050037,
+	0x0204FE15,
+	0x02050010,
+	0x02040020,
+	/*
+	 * Widget node 0x20 - 6
+	 * Silence data mode Threshold (-90dB)
+	 */
+	0x02050030,
+	0x0204A000,
+	0x0205001B,
+	0x02040A4B,
+	/*
+	 * Widget node 0x20 - 7
+	 * Default setting - 1
+	 */
+	0x05750003,
+	0x05740DA3,
+	0x02050046,
+	0x02040004,
+	/*
+	 * Widget node 0x20 - 8
+	 * support 1 pin detect two port
+	 */
+	0x02050009,
+	0x0204E003,
+	0x0205000A,
+	0x02047770,
+	/*
+	 * Widget node 0x20 - 9
+	 * To set LDO1/LDO2 as default (used for headset)
+	 */
+	0x02050008,
+	0x02046A0C,
+	0x02050008,
+	0x02046A0C,
+};
+
+const u32 pc_beep_verbs[] = {
+	/* Dos beep path - 1 */
+	0x01470C00,
+	0x02050036,
+	0x02047151,
+	0x01470740,
+	/* Dos beep path - 2 */
+	0x0143b000,
+	0x01470C02,
+	0x01470C02,
+	0x01470C02,
+};
+
+AZALIA_ARRAY_SIZES;
+
+#endif
diff --git a/src/mainboard/google/brox/variants/juchi/memory.c b/src/mainboard/google/brox/variants/juchi/memory.c
new file mode 100644
index 0000000000..f7023ac56f
--- /dev/null
+++ b/src/mainboard/google/brox/variants/juchi/memory.c
@@ -0,0 +1,109 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <baseboard/gpio.h>
+#include <baseboard/variants.h>
+#include <gpio.h>
+#include <soc/romstage.h>
+
+static const struct mb_cfg baseboard_memcfg = {
+	.type = MEM_TYPE_LP5X,
+
+	.rcomp = {
+		/* Baseboard uses only 100ohm Rcomp resistors */
+		.resistor = 100,
+	},
+
+	/* DQ byte map */
+	.lpx_dq_map = {
+		.ddr0 = {
+			.dq0 = {  0,  3,  2,  1,  6,  4,  5,  7 },
+			.dq1 = { 14, 12, 13, 15, 8,  11, 9,  10 },
+		},
+		.ddr1 = {
+			.dq0 = {  1,  0,  2,  3,  6,  4,  7,  5 },
+			.dq1 = { 11,  8, 10,  9, 15, 14, 13, 12 },
+		},
+		.ddr2 = {
+			.dq0 = {  6,  4,  7,  5,  3,  1,  2,  0 },
+			.dq1 = { 14, 12, 13, 15,  9, 10, 11,  8 },
+		},
+		.ddr3 = {
+			.dq0 = {  1,  2,  3,  0,  6,  4,  7,  5 },
+			.dq1 = { 13, 15, 12, 14,  8,  11, 10, 9 },
+		},
+		.ddr4 = {
+			.dq0 = {  2,  3,  0,  1,  6,  5,  7,  4 },
+			.dq1 = { 14, 15, 13, 12, 10,  8,  9, 11 },
+		},
+		.ddr5 = {
+			.dq0 = {  1,  2,  3,  0,  6,  4,  7,  5 },
+			.dq1 = { 15, 13, 12, 14, 10,  9,  8, 11 },
+		},
+		.ddr6 = {
+			.dq0 = {  2,  1,  3,  0,  7,  5,  4,  6 },
+			.dq1 = { 15, 13, 14, 12, 11,  9, 10,  8 },
+		},
+		.ddr7 = {
+			.dq0 = {  3,  1,  2,  0,  5,  4,  7,  6 },
+			.dq1 = { 14, 15,  9, 11,  13, 8, 10, 12 },
+		},
+	},
+
+	/* DQS CPU<>DRAM map */
+	.lpx_dqs_map = {
+		.ddr0 = { .dqs0 = 0, .dqs1 = 1 },
+		.ddr1 = { .dqs0 = 0, .dqs1 = 1 },
+		.ddr2 = { .dqs0 = 0, .dqs1 = 1 },
+		.ddr3 = { .dqs0 = 0, .dqs1 = 1 },
+		.ddr4 = { .dqs0 = 0, .dqs1 = 1 },
+		.ddr5 = { .dqs0 = 0, .dqs1 = 1 },
+		.ddr6 = { .dqs0 = 0, .dqs1 = 1 },
+		.ddr7 = { .dqs0 = 0, .dqs1 = 1 },
+	},
+
+	.lp5x_config = {
+		.ccc_config = 0xff,
+	},
+
+	.LpDdrDqDqsReTraining = 1,
+
+	.ect = 1, /* Early Command Training */
+
+	.UserBd = BOARD_TYPE_ULT_ULX,
+};
+
+const struct mb_cfg *variant_memory_params(void)
+{
+	return &baseboard_memcfg;
+}
+
+int variant_memory_sku(void)
+{
+	/*
+	 * Memory configuration board straps
+	 * MEM_STRAP_0	GPP_E15
+	 * MEM_STRAP_1	GPP_E12
+	 * MEM_STRAP_2	GPP_E13
+	 * MEM_STRAP_3	GPP_E10
+	 */
+	gpio_t spd_gpios[] = {
+		GPP_E15,
+		GPP_E12,
+		GPP_E13,
+		GPP_E10,
+	};
+
+	return gpio_base2_value(spd_gpios, ARRAY_SIZE(spd_gpios));
+}
+
+bool variant_is_half_populated(void)
+{
+	/* MEM_CH_SEL GPP_S7 */
+	return gpio_get(GPP_S7);
+}
+
+void variant_get_spd_info(struct mem_spd *spd_info)
+{
+	spd_info->topo = MEM_TOPO_MEMORY_DOWN;
+	spd_info->cbfs_index = variant_memory_sku();
+}
diff --git a/src/mainboard/google/brox/variants/juchi/memory/Makefile.mk b/src/mainboard/google/brox/variants/juchi/memory/Makefile.mk
new file mode 100644
index 0000000000..bcb5920648
--- /dev/null
+++ b/src/mainboard/google/brox/variants/juchi/memory/Makefile.mk
@@ -0,0 +1,10 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+# This is an auto-generated file. Do not edit!!
+# Generated by:
+# util/spd_tools/bin/part_id_gen adl lp5 src/mainboard/google/brox/variants/juchi/memory src/mainboard/google/brox/variants/juchi/memory/mem_parts_used.txt
+
+SPD_SOURCES =
+SPD_SOURCES += spd/lp5/set-0/spd-1.hex      # ID = 0(0b0000)  Parts = MT62F512M32D2DR-031 WT:B, H9JCNNNBK3MLYR-N6E
+SPD_SOURCES += spd/lp5/set-0/spd-2.hex      # ID = 1(0b0001)  Parts = MT62F1G32D4DR-031 WT:B
+SPD_SOURCES += spd/lp5/set-0/spd-11.hex      # ID = 2(0b0010)  Parts = MT62F1G32D2DS-023 WT:B, H58G56BK8BX068, H58G56CK8BX146
+SPD_SOURCES += spd/lp5/set-0/spd-7.hex      # ID = 3(0b0011)  Parts = K3KL8L80CM-MGCT
diff --git a/src/mainboard/google/brox/variants/juchi/memory/dram_id.generated.txt b/src/mainboard/google/brox/variants/juchi/memory/dram_id.generated.txt
new file mode 100644
index 0000000000..2acaeaed86
--- /dev/null
+++ b/src/mainboard/google/brox/variants/juchi/memory/dram_id.generated.txt
@@ -0,0 +1,13 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+# This is an auto-generated file. Do not edit!!
+# Generated by:
+# util/spd_tools/bin/part_id_gen adl lp5 src/mainboard/google/brox/variants/juchi/memory src/mainboard/google/brox/variants/juchi/memory/mem_parts_used.txt
+
+DRAM Part Name                 ID to assign
+MT62F512M32D2DR-031 WT:B       0 (0000)
+H9JCNNNBK3MLYR-N6E             0 (0000)
+MT62F1G32D4DR-031 WT:B         1 (0001)
+MT62F1G32D2DS-023 WT:B         2 (0010)
+H58G56BK8BX068                 2 (0010)
+K3KL8L80CM-MGCT                3 (0011)
+H58G56CK8BX146                 2 (0010)
diff --git a/src/mainboard/google/brox/variants/juchi/memory/mem_parts_used.txt b/src/mainboard/google/brox/variants/juchi/memory/mem_parts_used.txt
new file mode 100644
index 0000000000..a1a7a9932f
--- /dev/null
+++ b/src/mainboard/google/brox/variants/juchi/memory/mem_parts_used.txt
@@ -0,0 +1,7 @@
+MT62F512M32D2DR-031 WT:B
+H9JCNNNBK3MLYR-N6E
+MT62F1G32D4DR-031 WT:B
+MT62F1G32D2DS-023 WT:B
+H58G56BK8BX068
+K3KL8L80CM-MGCT
+H58G56CK8BX146
diff --git a/src/mainboard/google/brox/variants/juchi/overridetree.cb b/src/mainboard/google/brox/variants/juchi/overridetree.cb
new file mode 100644
index 0000000000..1d667507a8
--- /dev/null
+++ b/src/mainboard/google/brox/variants/juchi/overridetree.cb
@@ -0,0 +1,481 @@
+fw_config
+	field STORAGE 2 3
+		option STORAGE_UFS			1
+		option STORAGE_NVME			2
+	end
+	field WIFI_BT 4 4
+		option WIFI_BT_CNVI			0
+		option WIFI_BT_PCIE			1
+	end
+	field DB_USB 11 12
+		option DB_1A				0
+		option DB_1A_LTE			1
+		option DB_1A_LTE_SAR			2
+	end
+	field FPMCU 17 18
+		option FPMCU_ABSENT			0
+		option FPMCU_NUVOTON			1
+	end
+	field PANEL_PWR 19
+		option DISABLE				0
+		option ENABLE				1
+	end
+end
+
+chip soc/intel/alderlake
+	register "platform_pmax" = "208"
+
+	# As per Intel Advisory doc#723158, the change is required to prevent possible
+	# display flickering issue.
+	register "disable_dynamic_tccold_handshake" = "true"
+
+	register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC_SKIP)"  # USB2_C0
+	register "usb2_ports[1]" = "USB2_PORT_EMPTY"		# Disable USB2 Port
+	register "usb2_ports[2]" = "USB2_PORT_TYPE_C(OC_SKIP)"  # USB2_C2
+	register "usb2_ports[3]" = "USB2_PORT_MID(OC_SKIP)"	# WWAN
+	register "usb2_ports[4]" = "USB2_PORT_EMPTY"     	# Disable USB2 Port
+	register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)"     # Camera
+	register "usb2_ports[6]" = "USB2_PORT_MID(OC2)"     	# Type-A Port A0
+	register "usb2_ports[7]" = "USB2_PORT_EMPTY"		# Disable USB2 Port
+	register "usb2_ports[8]" = "USB2_PORT_MID(OC1)"     	# Type-A Port A1
+	register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)"     # M.2 Bluetooth
+
+	register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC1)"     # Type-A port A1(DB)
+	register "usb3_ports[1]" = "USB3_PORT_EMPTY"		# Disable USB3 Port
+	register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC2)"     # Type A port A0(DCI)
+	register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # WWAN
+
+	# Intel Common SoC Config
+	#+-------------------+---------------------------+
+	#| Field             |  Value                    |
+	#+-------------------+---------------------------+
+	#| I2C0              | Trackpad                  |
+	#| I2C1              | Touchscreen               |
+	#| I2C2              | Audio codec & Sar sensor  |
+	#| I2C4              | cr50 TPM. Early init is   |
+	#|                   | required to set up a BAR  |
+	#|                   | for TPM communication     |
+	#+-------------------+---------------------------+
+	register "common_soc_config" = "{
+		.i2c[0] = {
+			.speed = I2C_SPEED_FAST,
+			.rise_time_ns = 650,
+			.fall_time_ns = 330,
+			.data_hold_time_ns = 50,
+		},
+		.i2c[1] = {
+			.speed = I2C_SPEED_FAST,
+			.rise_time_ns = 600,
+			.fall_time_ns = 350,
+			.data_hold_time_ns = 50,
+		},
+		.i2c[2] = {
+			.speed = I2C_SPEED_FAST,
+			.rise_time_ns = 600,
+			.fall_time_ns = 250,
+			.data_hold_time_ns = 50,
+		},
+		.i2c[4] = {
+			.early_init = 1,
+			.speed = I2C_SPEED_FAST,
+			.rise_time_ns = 650,
+			.fall_time_ns = 400,
+			.data_hold_time_ns = 50,
+		},
+	}"
+
+	register "power_limits_config[RPL_P_282_242_142_15W_CORE]" = "{
+		.tdp_pl1_override = 15,
+		.tdp_pl2_override = 41,
+		.tdp_pl4 = 87,
+	}"
+
+	device domain 0 on
+		device ref dtt on
+			chip drivers/intel/dptf
+				## sensor information
+				register "options.tsr[0].desc" = ""DRAM""
+				register "options.tsr[1].desc" = ""Soc""
+				register "options.tsr[2].desc" = ""Charger""
+
+				## Passive Policy
+				register "policies.passive" = "{
+						[0] = DPTF_PASSIVE(CPU,		CPU,		97, 5000),
+						[1] = DPTF_PASSIVE(CPU,		TEMP_SENSOR_0,	85, 5000),
+						[2] = DPTF_PASSIVE(CPU,		TEMP_SENSOR_1,	85, 5000),
+						[3] = DPTF_PASSIVE(CHARGER,	TEMP_SENSOR_2,	85, 5000),
+				}"
+
+				## Critical Policy
+				register "policies.critical" = "{
+						[0] = DPTF_CRITICAL(CPU,               105, SHUTDOWN),
+						[1] = DPTF_CRITICAL(TEMP_SENSOR_0,      95, SHUTDOWN),
+						[2] = DPTF_CRITICAL(TEMP_SENSOR_1,      95, SHUTDOWN),
+						[3] = DPTF_CRITICAL(TEMP_SENSOR_2,      95, SHUTDOWN),
+				}"
+
+				register "controls.power_limits" = "{
+						.pl1 = {
+							.min_power = 15000,
+							.max_power = 18000,
+							.time_window_min = 28 * MSECS_PER_SEC,
+							.time_window_max = 32 * MSECS_PER_SEC,
+							.granularity = 200,
+							},
+						.pl2 = {
+							.min_power = 41000,
+							.max_power = 41000,
+							.time_window_min = 28 * MSECS_PER_SEC,
+							.time_window_max = 32 * MSECS_PER_SEC,
+							.granularity = 1000,
+							}
+				}"
+
+				## Charger Performance Control (Control, mA)
+				register "controls.charger_perf" = "{
+						[0] = { 255, 1700 },
+						[1] = {  24, 1500 },
+						[2] = {  16, 1000 },
+						[3] = {   8,  500 }
+				}"
+
+				device generic 0 alias dptf_policy on end
+			end
+		end # DTT
+		device ref igpu on
+			chip drivers/gfx/generic
+				register "device_count" = "6"
+				# DDIA for eDP
+				register "device[0].name" = ""LCD0""
+				register "device[0].type" = "panel"
+				# DDIB for HDMI
+				# If HDMI is not enumerated in the kernel, then no GFX device should be added for DDIB
+				register "device[1].name" = ""DD01""
+				# TCP0 (DP-1) for port C0
+				register "device[2].name" = ""DD02""
+				register "device[2].use_pld" = "true"
+				register "device[2].pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(1, 1))"
+				# TCP1 (DP-2) is unused for any ports but still enumerated in the kernel, so GFX device is added for TCP1
+				register "device[3].name" = ""DD03""
+				# TCP2 (DP-3) for port C2
+				register "device[4].name" = ""DD04""
+				register "device[4].use_pld" = "true"
+				register "device[4].pld" = "ACPI_PLD_TYPE_C(LEFT, RIGHT, ACPI_PLD_GROUP(2, 1))"
+				# TCP3 (DP-4) is unused for any ports but still enumerated in the kernel, so GFX device is added for TCP3
+				register "device[5].name" = ""DD05""
+				device generic 0 on end
+			end
+		end # Integrated Graphics Device
+		device ref pch_espi on
+			chip ec/google/chromeec
+				device pnp 0c09.0 on end
+			end
+		end
+		device ref pmc hidden
+			chip drivers/intel/pmc_mux
+				device generic 0 on
+					chip drivers/intel/pmc_mux/conn
+						use usb2_port1 as usb2_port
+						use tcss_usb3_port1 as usb3_port
+						device generic 0 on end
+					end
+					chip drivers/intel/pmc_mux/conn
+						use usb2_port3 as usb2_port
+						use tcss_usb3_port3 as usb3_port
+						device generic 1 on end
+					end
+				end
+			end
+		end
+		device ref tcss_xhci on
+			chip drivers/usb/acpi
+				device ref tcss_root_hub on
+					chip drivers/usb/acpi
+						register "desc" = ""USB3 Type-C Port C0 (MLB)""
+						register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
+						register "use_custom_pld" = "true"
+						register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(1, 1))"
+						device ref tcss_usb3_port1 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB3 Type-C Port C2 (MLB)""
+						register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
+						register "use_custom_pld" = "true"
+						register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, RIGHT, ACPI_PLD_GROUP(2, 1))"
+						device ref tcss_usb3_port3 on end
+					end
+				end
+			end
+		end
+		device ref xhci on
+			chip drivers/usb/acpi
+				device ref xhci_root_hub on
+					chip drivers/usb/acpi
+						register "desc" = ""USB2 Type-C Port C0 (MLB)""
+						register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
+						register "use_custom_pld" = "true"
+						register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(1, 1))"
+						device ref usb2_port1 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB2 Type-C Port C2 (MLB)""
+						register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
+						register "use_custom_pld" = "true"
+						register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, RIGHT, ACPI_PLD_GROUP(2, 1))"
+						device ref usb2_port3 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB2 WWAN""
+						register "type" = "UPC_TYPE_INTERNAL"
+						device ref usb2_port4 on
+							probe DB_USB DB_1A_LTE
+							probe DB_USB DB_1A_LTE_SAR
+							probe unprovisioned
+						end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB2 Camera""
+						register "type" = "UPC_TYPE_INTERNAL"
+						register "has_power_resource" = "true"
+						register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E7)"
+						device ref usb2_port6 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB2 Type-A Port A0 (DCI)""
+						register "type" = "UPC_TYPE_A"
+						register "use_custom_pld" = "true"
+						register "custom_pld" = "ACPI_PLD_TYPE_A(RIGHT, LEFT, ACPI_PLD_GROUP(3, 1))"
+						device ref usb2_port7 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB2 Type-A Port A1 (DB)""
+						register "type" = "UPC_TYPE_A"
+						register "use_custom_pld" = "true"
+						register "custom_pld" = "ACPI_PLD_TYPE_A(LEFT, LEFT, ACPI_PLD_GROUP(4, 1))"
+						device ref usb2_port9 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB2 Bluetooth""
+						register "type" = "UPC_TYPE_INTERNAL"
+						register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A13)"
+						device ref usb2_port10 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB3 Type-A Port A1 (DB)""
+						register "type" = "UPC_TYPE_USB3_A"
+						register "use_custom_pld" = "true"
+						register "custom_pld" = "ACPI_PLD_TYPE_A(LEFT, LEFT, ACPI_PLD_GROUP(4, 1))"
+						device ref usb3_port1 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB3 Type-A Port A0 (DCI)""
+						register "type" = "UPC_TYPE_USB3_A"
+						register "use_custom_pld" = "true"
+						register "custom_pld" = "ACPI_PLD_TYPE_A(RIGHT, LEFT, ACPI_PLD_GROUP(3, 1))"
+						device ref usb3_port3 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB3 WWAN""
+						register "type" = "UPC_TYPE_INTERNAL"
+						device ref usb3_port4 on
+							probe DB_USB DB_1A_LTE
+							probe DB_USB DB_1A_LTE_SAR
+							probe unprovisioned
+						end
+					end
+				end
+			end
+		end
+		device ref pcie4_0 on
+			# Enable CPU PCIE RP 1 using CLK 3
+			register "cpu_pcie_rp[CPU_RP(1)]" = "{
+				.clk_req = 3,
+				.clk_src = 3,
+				.flags = PCIE_RP_LTR | PCIE_RP_AER,
+				.pcie_rp_aspm = ASPM_L1,
+			}"
+			probe STORAGE STORAGE_NVME
+			probe unprovisioned
+		end
+		device ref pcie_rp5 on
+			register "pch_pcie_rp[PCH_RP(5)]" = "{
+				.clk_src = 1,
+				.clk_req = 1,
+				.flags = PCIE_RP_LTR | PCIE_RP_AER,
+				.pcie_rp_pcie_speed = SPEED_GEN2,
+			}"
+			chip drivers/wifi/generic
+				register "wake" = "GPE0_DW0_03"
+				register "add_acpi_dma_property" = "true"
+				use usb2_port10 as bluetooth_companion
+				device pci 00.0 on
+					probe WIFI_BT WIFI_BT_PCIE
+					probe unprovisioned
+				end
+			end
+			chip soc/intel/common/block/pcie/rtd3
+				# enable_gpio is controlled by the EC with EC_EN_PP3300_WLAN
+				register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_H2)"
+				register "srcclk_pin" = "1"
+				device generic 0 on end
+			end
+			probe WIFI_BT WIFI_BT_PCIE
+			probe unprovisioned
+		end
+		device ref cnvi_wifi on
+			chip drivers/wifi/generic
+				register "wake" = "GPE0_PME_B0"
+				register "add_acpi_dma_property" = "true"
+				register "enable_cnvi_ddr_rfim" = "true"
+				device generic 0 on end
+			end
+			probe WIFI_BT WIFI_BT_CNVI
+			probe unprovisioned
+		end
+		device ref ish on
+			chip drivers/intel/ish
+				register "add_acpi_dma_property" = "true"
+				device generic 0 alias ish_conf on end
+			end
+			probe STORAGE STORAGE_UFS
+			probe unprovisioned
+		end
+		device ref ufs on
+			probe STORAGE STORAGE_UFS
+			probe unprovisioned
+		end
+		device ref i2c0 on
+			chip drivers/i2c/generic
+				register "hid" = ""ELAN0000""
+				register "desc" = ""ELAN Touchpad""
+				register "irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_E3_IRQ)"
+				register "wake" = "GPE0_DW2_03"
+				register "detect" = "1"
+				device i2c 0x15 on end
+			end
+			chip drivers/i2c/hid
+				register "generic.hid" = ""SYNA0000""
+				register "generic.cid" = ""ACPI0C50""
+				register "generic.desc" = ""Synaptics Touchpad""
+				register "generic.irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_E3_IRQ)"
+				register "generic.wake" = "GPE0_DW2_03"
+				register "generic.detect" = "1"
+				register "hid_desc_reg_offset" = "0x20"
+				device i2c 0x2c on end
+			end
+			chip drivers/i2c/hid
+				register "generic.hid" = ""PIXA2303""
+				register "generic.desc" = ""PIXA Touchpad""
+				register "generic.irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_E3_IRQ)"
+				register "generic.wake" = "GPE0_DW2_03"
+				register "generic.detect" = "1"
+				register "hid_desc_reg_offset" = "0x20"
+				device i2c 0x68 on end
+			end
+		end #I2C0
+		device ref i2c1 on
+			chip drivers/i2c/hid
+				register "generic.hid" = ""ILTK0001""
+				register "generic.desc" = ""ILITEK Touchscreen""
+				register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_F18_IRQ)"
+				register "generic.detect" = "1"
+				register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_F17)"
+				register "generic.reset_delay_ms" = "200"
+				register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_F7)"
+				register "generic.enable_delay_ms" = "12"
+				register "generic.has_power_resource" = "1"
+				register "generic.use_gpio_for_status" = "true"
+				register "hid_desc_reg_offset" = "0x01"
+				device i2c 41 on end
+			end
+			chip drivers/i2c/hid
+				register "generic.hid" = ""ELAN9004""
+				register "generic.desc" = ""ELAN Touchscreen""
+				register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_F18_IRQ)"
+				register "generic.detect" = "1"
+				register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_F17)"
+				register "generic.reset_delay_ms" = "20"
+				register "generic.reset_off_delay_ms" = "2"
+				register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_F7)"
+				register "generic.enable_delay_ms" = "1"
+				register "generic.stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_F14)"
+				register "generic.stop_delay_ms" = "150"
+				register "generic.stop_off_delay_ms" = "2"
+				register "generic.has_power_resource" = "1"
+				register "generic.use_gpio_for_status" = "true"
+				register "hid_desc_reg_offset" = "0x01"
+				device i2c 10 on end
+			end
+			probe PANEL_PWR ENABLE
+		end
+		device ref i2c2 on
+			chip drivers/i2c/generic
+				register "hid" = ""RTL5682""
+				register "name" = ""RT58""
+				register "desc" = ""Headset Codec""
+				register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_S6)"
+				# Set the jd_src to RT5668_JD1 for jack detection
+				register "property_count" = "1"
+				register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER"
+				register "property_list[0].name" = ""realtek,jd-src""
+				register "property_list[0].integer" = "1"
+				device i2c 1a on end
+			end
+			chip drivers/generic/alc1015
+				register "hid" = ""RTL1019""
+				register "sdb" =  "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_F20)"
+				device generic 0 on end
+			end
+			chip drivers/i2c/sx9324
+				register "desc" = ""SAR Proximity Sensor""
+				register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_H19_IRQ)"
+				register "speed" = "I2C_SPEED_FAST"
+				register "uid" = "1"
+				register "ph0_pin" = "{1, 2, 2}"
+				register "ph1_pin" = "{2, 1, 2}"
+				register "ph2_pin" = "{2, 2, 1}"
+				register "ph3_pin" = "{2, 1, 1}"
+				register "ph01_resolution" = "1024"
+				register "ph23_resolution" = "1024"
+				register "startup_sensor" = "1"
+				register "ph01_proxraw_strength" = "2"
+				register "ph23_proxraw_strength" = "2"
+				register "avg_pos_strength" = "256"
+				register "cs_idle_sleep" = ""hi-z""
+				register "int_comp_resistor" = ""lowest""
+				register "input_precharge_resistor_ohms" = "4000"
+				register "input_analog_gain" = "1"
+				device i2c 28 on
+					probe DB_USB DB_1A_LTE_SAR
+					probe unprovisioned
+				end
+			end
+		end
+		device ref gspi1 on
+			chip drivers/spi/acpi
+				register "name" = ""CRFP""
+				register "hid" = "ACPI_DT_NAMESPACE_HID"
+				register "uid" = "1"
+				register "compat_string" = ""google,cros-ec-spi""
+				register "irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_D13_IRQ)"
+				register "wake" = "GPE0_DW1_13"
+				register "has_power_resource" = "true"
+				register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D15)"
+				register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D2)"
+				register "enable_delay_ms" = "3"
+				device spi 0 on
+					probe FPMCU FPMCU_NUVOTON
+					probe unprovisioned
+				end
+			end # FPMCU
+		end
+		device ref hda on
+			chip drivers/sof
+				register "spkr_tplg" = "rt1019"
+				register "jack_tplg" = "rt5682"
+				register "mic_tplg" = "_2ch_pdm0"
+				device generic 0 on end
+			end
+		end
+	end
+end
diff --git a/src/mainboard/google/brox/variants/juchi/ramstage.c b/src/mainboard/google/brox/variants/juchi/ramstage.c
new file mode 100644
index 0000000000..0f78e26bd0
--- /dev/null
+++ b/src/mainboard/google/brox/variants/juchi/ramstage.c
@@ -0,0 +1,43 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <baseboard/variants.h>
+#include <device/pci_ids.h>
+#include <ec/google/chromeec/ec.h>
+#include <intelblocks/power_limit.h>
+
+/*
+ * SKU_ID, TDP (Watts), pl1_min (milliWatts), pl1_max (milliWatts),
+ * pl2_min (milliWatts), pl2_max (milliWatts), pl4 (milliWatts)
+ * Following values are for performance config as per document #640982
+ */
+
+const struct cpu_power_limits performance_efficient_limits[] = {
+	{
+		.mchid = PCI_DID_INTEL_RPL_P_ID_3,
+		.cpu_tdp = 15,
+		.pl1_min_power = 15000,
+		.pl1_max_power = 18000,
+		.pl2_min_power = 41000,
+		.pl2_max_power = 41000,
+		.pl4_power = 87000
+	},
+	{
+		.mchid = PCI_DID_INTEL_RPL_P_ID_4,
+		.cpu_tdp = 15,
+		.pl1_min_power = 15000,
+		.pl1_max_power = 18000,
+		.pl2_min_power = 41000,
+		.pl2_max_power = 41000,
+		.pl4_power = 87000
+	},
+};
+
+void __weak variant_devtree_update(void)
+{
+	printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__);
+
+	const struct cpu_power_limits *limits = performance_efficient_limits;
+	size_t limits_size = ARRAY_SIZE(performance_efficient_limits);
+
+	variant_update_power_limits(limits, limits_size);
+}
diff --git a/src/mainboard/google/brox/variants/juchi/smihandler.c b/src/mainboard/google/brox/variants/juchi/smihandler.c
new file mode 100644
index 0000000000..9f848eae4f
--- /dev/null
+++ b/src/mainboard/google/brox/variants/juchi/smihandler.c
@@ -0,0 +1,21 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <acpi/acpi.h>
+#include <baseboard/variants.h>
+#include <delay.h>
+
+#include "gpio.h"
+
+#define WWAN_FCPO_L	GPP_F21
+#define WWAN_RSL_L	GPP_H23
+#define WWAN_TOFF	15
+
+void variant_smi_sleep(u8 slp_typ)
+{
+	if (slp_typ == ACPI_S5) {
+		/* WWAN RW101R-GL power off sequence */
+		gpio_set(WWAN_RSL_L, 0);
+		mdelay(WWAN_TOFF);
+		gpio_set(WWAN_FCPO_L, 0);
+	}
+}
diff --git a/src/mainboard/google/brox/variants/juchi/variant.c b/src/mainboard/google/brox/variants/juchi/variant.c
new file mode 100644
index 0000000000..ed0f3de01e
--- /dev/null
+++ b/src/mainboard/google/brox/variants/juchi/variant.c
@@ -0,0 +1,46 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <bootstate.h>
+#include <baseboard/variants.h>
+#include <chip.h>
+#include <device/device.h>
+#include <fw_config.h>
+#include <sar.h>
+
+#include "gpio.h"
+
+#define WWAN_RSL_L		GPP_H23
+#define WWAN_FCPO_L		GPP_F21
+
+void variant_update_soc_chip_config(struct soc_intel_alderlake_config *config)
+{
+	if (fw_config_probe(FW_CONFIG(WIFI_BT, WIFI_BT_CNVI)) || (!fw_config_is_provisioned())) {
+		printk(BIOS_INFO, "CNVi bluetooth enabled by fw_config\n");
+		config->cnvi_bt_core = true;
+		config->cnvi_bt_audio_offload = true;
+	} else {
+		printk(BIOS_INFO, "CNVi bluetooth disabled by fw_config\n");
+		config->cnvi_bt_core = false;
+		config->cnvi_bt_audio_offload = false;
+	}
+}
+
+const char *get_wifi_sar_cbfs_filename(void)
+{
+	return get_wifi_sar_fw_config_filename(FW_CONFIG_FIELD(WIFI_BT));
+}
+
+const char *variant_get_auxfw_version_file(void)
+{
+	return "rts5453_retimer_bypass.hash";
+}
+
+static void wwan_out_of_reset(void *unused)
+{
+	if (fw_config_probe(FW_CONFIG(DB_USB, DB_1A_LTE)) ||
+		fw_config_probe(FW_CONFIG(DB_USB, DB_1A_LTE_SAR))) {
+		gpio_set(WWAN_FCPO_L, 1);
+		gpio_set(WWAN_RSL_L, 1);
+	}
+}
+BOOT_STATE_INIT_ENTRY(BS_DEV_ENABLE, BS_ON_ENTRY, wwan_out_of_reset, NULL);

From 8f44a8acca1d4d5f4740d89b5b7c8a437cb5fb21 Mon Sep 17 00:00:00 2001
From: Subrata Banik <subratabanik@google.com>
Date: Sat, 7 Feb 2026 10:59:46 +0000
Subject: [PATCH 3295/3886] mb/google/bluey: Reset FCC limits during charge
 disable

When disabling slow battery charging, explicitly set the Fast Charge
Current (FCC) configuration to 0x8c (disable) for both SMB1 and SMB2
controllers.

This ensures that the PMIC charging registers are returned to a
neutral/safe state while disabling the charging.

BUG=b:481546101
TEST=Build and boot Bluey. Verified that SMB1/SMB2_CHGR_MAX_FCC_CFG
registers are cleared during the disable_slow_battery_charging call.

Change-Id: Ic5da492b097747dec88b117ac021759644b8b816
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91121
Reviewed-by: Jayvik Desai <jayvik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/google/bluey/charging.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/src/mainboard/google/bluey/charging.c b/src/mainboard/google/bluey/charging.c
index 9d53372f9b..95f98a0799 100644
--- a/src/mainboard/google/bluey/charging.c
+++ b/src/mainboard/google/bluey/charging.c
@@ -15,6 +15,7 @@
 #define SMB2_CHGR_CHRG_EN_CMD ((SMB2_SLAVE_ID << 16) | SCHG_CHGR_CHARGING_ENABLE_CMD)
 
 #define FCC_1A_STEP_50MA 0x14
+#define FCC_DISABLE 0x8c
 
 enum charging_status {
 	CHRG_DISABLE,
@@ -71,4 +72,6 @@ void disable_slow_battery_charging(void)
 	printk(BIOS_INFO, "Disable slow charge support\n");
 	spmi_write8(SMB1_CHGR_CHRG_EN_CMD, CHRG_DISABLE);
 	spmi_write8(SMB2_CHGR_CHRG_EN_CMD, CHRG_DISABLE);
+	spmi_write8(SMB1_CHGR_MAX_FCC_CFG, FCC_DISABLE);
+	spmi_write8(SMB2_CHGR_MAX_FCC_CFG, FCC_DISABLE);
 }

From 634d841d3093c6dbb70a7ce3ffc4aa9b60cfae50 Mon Sep 17 00:00:00 2001
From: Pranava Y N <pranavayn@google.com>
Date: Wed, 4 Feb 2026 12:08:27 +0530
Subject: [PATCH 3296/3886] mb/google/fatcat/var/ruby: Add wake configuration
 to cnvi_bluetooth

This commit adds a wake configuration to the cnvi_bluetooth device for
the ruby variant. The "wake" setting is now registered to "GPE0_PME_B0"
using the common CNVi block. This enhancement ensures that the
cnvi_bluetooth device can properly wake the system.

TEST=Able to wake up the device from a low power state using a keyboard
     Bluetooth device.

Change-Id: If1b3af2a9ad8c3e3800f5c839190727d78122853
Signed-off-by: Pranava Y N <pranavayn@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91087
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: YH Lin <yueherngl@google.com>
---
 src/mainboard/google/fatcat/variants/ruby/overridetree.cb | 7 ++++++-
 1 file changed, 6 insertions(+), 1 deletion(-)

diff --git a/src/mainboard/google/fatcat/variants/ruby/overridetree.cb b/src/mainboard/google/fatcat/variants/ruby/overridetree.cb
index 494c8c5cf7..90b39c4cd8 100644
--- a/src/mainboard/google/fatcat/variants/ruby/overridetree.cb
+++ b/src/mainboard/google/fatcat/variants/ruby/overridetree.cb
@@ -277,7 +277,12 @@ chip soc/intel/pantherlake
 			end
 		end # CNVi
 
-		device ref cnvi_bluetooth on end
+		device ref cnvi_bluetooth on
+			chip soc/intel/common/block/cnvi
+				register "wake" = "GPE0_PME_B0"
+				device generic 0 on end
+			end
+		end
 
 		# NOTE: i2c0 is function 0; hence it needs to be enabled when any of i2c1-5 is enabled.
 		# TPM device is under i2c3. Therefore, i2c0 needs to be enabled anyways.

From 5778d9f8b2cdb5d7288c6b93c4a673cfb6e55dd1 Mon Sep 17 00:00:00 2001
From: Subrata Banik <subratabanik@google.com>
Date: Tue, 10 Feb 2026 03:21:15 +0000
Subject: [PATCH 3297/3886] soc/intel/pantherlake: Add support for USB wake up
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Add the same wakeup method that Meteor Lake uses to Panther Lake.

TEST=Able to build and boot google/moonstone where able to wake
the device using differnt USB devices like USB FP, KB and Mouse.

Change-Id: Id680b443791c3dbc502d1b6776fd0fa03bd80691
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91147
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Reviewed-by: Pranava Y N <pranavayn@google.com>
---
 src/soc/intel/pantherlake/acpi/xhci.asl | 17 +++++++++++++++++
 1 file changed, 17 insertions(+)

diff --git a/src/soc/intel/pantherlake/acpi/xhci.asl b/src/soc/intel/pantherlake/acpi/xhci.asl
index cd3b9f22fe..d1a8919c9b 100644
--- a/src/soc/intel/pantherlake/acpi/xhci.asl
+++ b/src/soc/intel/pantherlake/acpi/xhci.asl
@@ -2,6 +2,9 @@
 
 #include <soc/gpe.h>
 
+/* Include UWES method for enabling USB wake */
+#include <soc/intel/common/acpi/xhci_wake.asl>
+
 /* XHCI Controller 0:14.0 */
 
 Device (XHCI)
@@ -10,6 +13,20 @@ Device (XHCI)
 
 	Name (_PRW, Package () { GPE0_PME_B0, 3 })
 
+	OperationRegion (XPRT, PCI_Config, 0x00, 0x100)
+	Field (XPRT, AnyAcc, NoLock, Preserve)
+	{
+		Offset (0x10),
+		, 16,
+		XMEM, 16,	/* MEM_BASE */
+	}
+
+	Method (_DSW, 3)
+	{
+		UWES ((\U2WE & 0xFFF), PORTSCN_OFFSET, XMEM)
+		UWES ((\U3WE & 0x3F ), PORTSCXUSB3_OFFSET, XMEM)
+	}
+
 	Name (_S3D, 3)	/* D3 supported in S3 */
 	Name (_S0W, 3)	/* D3 can wake device in S0 */
 	Name (_S3W, 3)	/* D3 can wake system from S3 */

From dffdb05223a8f93f4af12d33252eed435dcd0f56 Mon Sep 17 00:00:00 2001
From: jamie_chen <jamie_chen@compal.corp-partner.google.com>
Date: Tue, 10 Feb 2026 13:50:50 +0800
Subject: [PATCH 3298/3886] mb/google/skywalker: Create variant Jaina

Create the variant Jaina.

BUG=b:481949605
TEST=emerge-skywalker coreboot
BRANCH=skywalker

Change-Id: I5b2f7c46b79b677bbbbaf90fa5b2e05ac9eccdc2
Signed-off-by: jamie_chen <jamie_chen@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91148
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Shawn Ku <shawnku@google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
---
 src/mainboard/google/skywalker/Kconfig      | 2 ++
 src/mainboard/google/skywalker/Kconfig.name | 3 +++
 2 files changed, 5 insertions(+)

diff --git a/src/mainboard/google/skywalker/Kconfig b/src/mainboard/google/skywalker/Kconfig
index 19cfab5d9a..a61cb6d46f 100644
--- a/src/mainboard/google/skywalker/Kconfig
+++ b/src/mainboard/google/skywalker/Kconfig
@@ -6,6 +6,7 @@ config BOARD_GOOGLE_SKYWALKER_COMMON
 		 BOARD_GOOGLE_BAZE || \
 		 BOARD_GOOGLE_DOOKU || \
 		 BOARD_GOOGLE_GROGU || \
+		 BOARD_GOOGLE_JAINA || \
 		 BOARD_GOOGLE_MACE || \
 		 BOARD_GOOGLE_OBIWAN || \
 		 BOARD_GOOGLE_PADME || \
@@ -57,6 +58,7 @@ config MAINBOARD_PART_NUMBER
 	default "Baze" if BOARD_GOOGLE_BAZE
 	default "Dooku" if BOARD_GOOGLE_DOOKU
 	default "Grogu" if BOARD_GOOGLE_GROGU
+	default "Jaina" if BOARD_GOOGLE_JAINA
 	default "Mace" if BOARD_GOOGLE_MACE
 	default "Obiwan" if BOARD_GOOGLE_OBIWAN
 	default "Padme" if BOARD_GOOGLE_PADME
diff --git a/src/mainboard/google/skywalker/Kconfig.name b/src/mainboard/google/skywalker/Kconfig.name
index aa5b6550bf..ad04340621 100644
--- a/src/mainboard/google/skywalker/Kconfig.name
+++ b/src/mainboard/google/skywalker/Kconfig.name
@@ -14,6 +14,9 @@ config BOARD_GOOGLE_DOOKU
 config BOARD_GOOGLE_GROGU
 	bool "->  Grogu"
 
+config BOARD_GOOGLE_JAINA
+	bool "->  Jaina"
+
 config BOARD_GOOGLE_MACE
 	bool "->  Mace"
 

From b4b9e87669383fd49a3be74aae15d7ab3fa8ad38 Mon Sep 17 00:00:00 2001
From: Patrick Rudolph <patrick.rudolph@9elements.com>
Date: Sat, 24 Jan 2026 09:58:59 +0100
Subject: [PATCH 3299/3886] cpu/intel/model_206xx: Load microcode in
 pre_mp_init()

Ensure that BSP has latest microcode loaded before MPinit starts.
This aligns the code with other platforms ensuring that the microcode
on the BSP is up to date.

It likely has updated microcode before enabling NEM, so this is a
nop, but it also ensures that the microcode is located in CBFS
before the MTRRs are setup using x86_setup_mtrrs_with_detect() which
removes caching the SPI flash MMIO area.

Since intel_microcode_find() caches the microcode location
get_microcode_info() will be faster since it doesn't need to access
the CBFS.

TEST=Lenovo X220 still boots.

Change-Id: Ic4c5d1a06ce314b38b92e8a9c089ed901716ff27
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90893
Reviewed-by: Naresh <naresh.solanki.2011@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/cpu/intel/model_2065x/model_2065x_init.c | 3 +++
 src/cpu/intel/model_206ax/model_206ax_init.c | 3 +++
 2 files changed, 6 insertions(+)

diff --git a/src/cpu/intel/model_2065x/model_2065x_init.c b/src/cpu/intel/model_2065x/model_2065x_init.c
index 70a2d1ae80..d02c70bdfa 100644
--- a/src/cpu/intel/model_2065x/model_2065x_init.c
+++ b/src/cpu/intel/model_2065x/model_2065x_init.c
@@ -106,6 +106,9 @@ static void model_2065x_init(struct device *cpu)
 /* MP initialization support. */
 static void pre_mp_init(void)
 {
+	const void *microcode_patch = intel_microcode_find();
+	intel_microcode_load_unlocked(microcode_patch);
+
 	/* Setup MTRRs based on physical address size. */
 	x86_setup_mtrrs_with_detect();
 	x86_mtrr_check();
diff --git a/src/cpu/intel/model_206ax/model_206ax_init.c b/src/cpu/intel/model_206ax/model_206ax_init.c
index 21a13f3d11..162c674e0f 100644
--- a/src/cpu/intel/model_206ax/model_206ax_init.c
+++ b/src/cpu/intel/model_206ax/model_206ax_init.c
@@ -486,6 +486,9 @@ static void model_206ax_init(struct device *cpu)
 /* MP initialization support. */
 static void pre_mp_init(void)
 {
+	const void *microcode_patch = intel_microcode_find();
+	intel_microcode_load_unlocked(microcode_patch);
+
 	/* Setup MTRRs based on physical address size. */
 	x86_setup_mtrrs_with_detect();
 	x86_mtrr_check();

From f6f4217bfded5243c23e11d81a4ec00009b687da Mon Sep 17 00:00:00 2001
From: David Wu <david_wu@quanta.corp-partner.google.com>
Date: Tue, 3 Feb 2026 21:02:11 +0800
Subject: [PATCH 3300/3886] mb/google/brya: Create moxoe variant

Create the moxoe variant of the moxie project by
copying the files to a new directory named for the variant.

BUG=b:481186489
TEST=util/abuild/abuild -p none -t google/brya -x -a
make sure the build includes GOOGLE_MOXOE

Change-Id: I5dd9cc21b647834144cfffcd43bdcf84e9df3a0c
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91076
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kenneth Chan <kenneth.chan@quanta.corp-partner.google.com>
---
 src/mainboard/google/brya/Kconfig             |  11 +
 src/mainboard/google/brya/Kconfig.name        |   3 +
 .../google/brya/variants/moxoe/Makefile.mk    |   9 +
 .../google/brya/variants/moxoe/data.vbt       | Bin 0 -> 8704 bytes
 .../google/brya/variants/moxoe/fw_config.c    |  75 ++++
 .../google/brya/variants/moxoe/gpio.c         | 133 +++++++
 .../brya/variants/moxoe/include/variant/ec.h  |   8 +
 .../variants/moxoe/include/variant/gpio.h     |   8 +
 .../brya/variants/moxoe/overridetree.cb       | 354 ++++++++++++++++++
 .../google/brya/variants/moxoe/ramstage.c     |  58 +++
 .../google/brya/variants/moxoe/variant.c      |  23 ++
 11 files changed, 682 insertions(+)
 create mode 100644 src/mainboard/google/brya/variants/moxoe/Makefile.mk
 create mode 100644 src/mainboard/google/brya/variants/moxoe/data.vbt
 create mode 100644 src/mainboard/google/brya/variants/moxoe/fw_config.c
 create mode 100644 src/mainboard/google/brya/variants/moxoe/gpio.c
 create mode 100644 src/mainboard/google/brya/variants/moxoe/include/variant/ec.h
 create mode 100644 src/mainboard/google/brya/variants/moxoe/include/variant/gpio.h
 create mode 100644 src/mainboard/google/brya/variants/moxoe/overridetree.cb
 create mode 100644 src/mainboard/google/brya/variants/moxoe/ramstage.c
 create mode 100644 src/mainboard/google/brya/variants/moxoe/variant.c

diff --git a/src/mainboard/google/brya/Kconfig b/src/mainboard/google/brya/Kconfig
index 707ffc9b4d..dd23e4d651 100644
--- a/src/mainboard/google/brya/Kconfig
+++ b/src/mainboard/google/brya/Kconfig
@@ -407,6 +407,13 @@ config BOARD_GOOGLE_MOXIE
 	select INTEL_GMA_HAVE_VBT
 	select SOC_INTEL_RAPTORLAKE
 
+config BOARD_GOOGLE_MOXOE
+	select BOARD_GOOGLE_BASEBOARD_BRASK
+	select DRIVERS_GENESYSLOGIC_GL9755
+	select EC_GOOGLE_CHROMEEC_INCLUDE_SSFC_IN_FW_CONFIG
+	select INTEL_GMA_HAVE_VBT
+	select SOC_INTEL_RAPTORLAKE
+
 config BOARD_GOOGLE_NIVVIKS
 	select BOARD_GOOGLE_BASEBOARD_NISSA
 	select BOARD_ROMSIZE_KB_32768
@@ -871,6 +878,7 @@ config DRIVER_TPM_I2C_BUS
 	default 0x1 if BOARD_GOOGLE_MITHRAX
 	default 0x1 if BOARD_GOOGLE_MOLI
 	default 0x1 if BOARD_GOOGLE_MOXIE
+	default 0x1 if BOARD_GOOGLE_MOXOE
 	default 0x0 if BOARD_GOOGLE_NEREID
 	default 0x0 if BOARD_GOOGLE_NIVVIKS
 	default 0x1 if BOARD_GOOGLE_NOVA
@@ -959,6 +967,7 @@ config TPM_TIS_ACPI_INTERRUPT
 	default 13 if BOARD_GOOGLE_MITHRAX
 	default 13 if BOARD_GOOGLE_MOLI
 	default 13 if BOARD_GOOGLE_MOXIE
+	default 13 if BOARD_GOOGLE_MOXOE
 	default 13 if BOARD_GOOGLE_NEREID
 	default 13 if BOARD_GOOGLE_NIVVIKS
 	default 13 if BOARD_GOOGLE_NOVA
@@ -1051,6 +1060,7 @@ config MAINBOARD_PART_NUMBER
 	default "Mithrax" if BOARD_GOOGLE_MITHRAX
 	default "Moli" if BOARD_GOOGLE_MOLI
 	default "Moxie" if BOARD_GOOGLE_MOXIE
+	default "Moxoe" if BOARD_GOOGLE_MOXOE
 	default "Nereid" if BOARD_GOOGLE_NEREID
 	default "Nivviks" if BOARD_GOOGLE_NIVVIKS
 	default "Nokris" if BOARD_GOOGLE_NOKRIS
@@ -1132,6 +1142,7 @@ config VARIANT_DIR
 	default "mithrax" if BOARD_GOOGLE_MITHRAX
 	default "moli" if BOARD_GOOGLE_MOLI
 	default "moxie" if BOARD_GOOGLE_MOXIE
+	default "moxoe" if BOARD_GOOGLE_MOXOE
 	default "nereid" if BOARD_GOOGLE_NEREID
 	default "nereid" if BOARD_GOOGLE_TEREID
 	default "nivviks" if BOARD_GOOGLE_NIVVIKS
diff --git a/src/mainboard/google/brya/Kconfig.name b/src/mainboard/google/brya/Kconfig.name
index c4a5c06dc7..4e32500b63 100644
--- a/src/mainboard/google/brya/Kconfig.name
+++ b/src/mainboard/google/brya/Kconfig.name
@@ -118,6 +118,9 @@ config BOARD_GOOGLE_MOLI
 config BOARD_GOOGLE_MOXIE
 	bool "->  Moxie (Acer Chromebox CXI6)"
 
+config BOARD_GOOGLE_MOXOE
+	bool "->  Moxoe"
+
 config BOARD_GOOGLE_NIVVIKS
 	bool "->  Nivviks"
 
diff --git a/src/mainboard/google/brya/variants/moxoe/Makefile.mk b/src/mainboard/google/brya/variants/moxoe/Makefile.mk
new file mode 100644
index 0000000000..e31aaa1707
--- /dev/null
+++ b/src/mainboard/google/brya/variants/moxoe/Makefile.mk
@@ -0,0 +1,9 @@
+# SPDX-License-Identifier: GPL-2.0-only
+bootblock-y += gpio.c
+
+romstage-y += gpio.c
+
+ramstage-y += gpio.c
+ramstage-y += ramstage.c
+ramstage-$(CONFIG_FW_CONFIG) += fw_config.c
+ramstage-$(CONFIG_FW_CONFIG) += variant.c
diff --git a/src/mainboard/google/brya/variants/moxoe/data.vbt b/src/mainboard/google/brya/variants/moxoe/data.vbt
new file mode 100644
index 0000000000000000000000000000000000000000..7d14588c613c3501ddb3970a2254560b709b00a0
GIT binary patch
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diff --git a/src/mainboard/google/brya/variants/moxoe/fw_config.c b/src/mainboard/google/brya/variants/moxoe/fw_config.c
new file mode 100644
index 0000000000..42613af163
--- /dev/null
+++ b/src/mainboard/google/brya/variants/moxoe/fw_config.c
@@ -0,0 +1,75 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <bootstate.h>
+#include <console/console.h>
+#include <fw_config.h>
+#include <gpio.h>
+
+static const struct pad_config dmic_enable_pads[] = {
+	PAD_CFG_NF(GPP_R6, NONE, DEEP, NF3),	/* DMIC_CLK1_R */
+	PAD_CFG_NF(GPP_R7, NONE, DEEP, NF3),	/* DMIC_DATA1_R */
+};
+
+static const struct pad_config dmic_disable_pads[] = {
+	PAD_NC(GPP_R6, NONE),
+	PAD_NC(GPP_R7, NONE),
+};
+
+static const struct pad_config i2s_enable_pads[] = {
+	PAD_CFG_NF(GPP_R0, NONE, DEEP, NF2),	/* I2S_HP_SCLK_R */
+	PAD_CFG_NF(GPP_R1, NONE, DEEP, NF2),	/* I2S_HP_SFRM_R */
+	PAD_CFG_NF(GPP_R2, DN_20K, DEEP, NF2),	/* I2S_PCH_TX_HP_RX_STRAP */
+	PAD_CFG_NF(GPP_R3, NONE, DEEP, NF2),	/* I2S_PCH_RX_HP_TX */
+};
+
+static const struct pad_config i2s_disable_pads[] = {
+	PAD_NC(GPP_R0, NONE),
+	PAD_NC(GPP_R1, NONE),
+	PAD_NC(GPP_R2, NONE),
+	PAD_NC(GPP_R3, NONE),
+};
+
+static const struct pad_config bt_i2s_enable_pads[] = {
+	PAD_CFG_NF(GPP_VGPIO_30, NONE, DEEP, NF3),	/* BT_I2S_BCLK */
+	PAD_CFG_NF(GPP_VGPIO_31, NONE, DEEP, NF3),	/* BT_I2S_SYNC */
+	PAD_CFG_NF(GPP_VGPIO_32, NONE, DEEP, NF3),	/* BT_I2S_SDO */
+	PAD_CFG_NF(GPP_VGPIO_33, NONE, DEEP, NF3),	/* BT_I2S_SDI */
+	PAD_CFG_NF(GPP_VGPIO_34, NONE, DEEP, NF1),	/* SSP2_SCLK */
+	PAD_CFG_NF(GPP_VGPIO_35, NONE, DEEP, NF1),	/* SSP2_SFRM */
+	PAD_CFG_NF(GPP_VGPIO_36, NONE, DEEP, NF1),	/* SSP_TXD */
+	PAD_CFG_NF(GPP_VGPIO_37, NONE, DEEP, NF1),	/* SSP_RXD */
+};
+
+static const struct pad_config bt_i2s_disable_pads[] = {
+	PAD_NC(GPP_VGPIO_30, NONE),
+	PAD_NC(GPP_VGPIO_31, NONE),
+	PAD_NC(GPP_VGPIO_32, NONE),
+	PAD_NC(GPP_VGPIO_33, NONE),
+	PAD_NC(GPP_VGPIO_34, NONE),
+	PAD_NC(GPP_VGPIO_35, NONE),
+	PAD_NC(GPP_VGPIO_36, NONE),
+	PAD_NC(GPP_VGPIO_37, NONE),
+};
+
+static void fw_config_handle(void *unused)
+{
+	if (!fw_config_is_provisioned() || fw_config_probe(FW_CONFIG(AUDIO, AUDIO_UNKNOWN))) {
+		printk(BIOS_INFO, "Disable audio related GPIO pins.\n");
+		gpio_configure_pads(i2s_disable_pads, ARRAY_SIZE(i2s_disable_pads));
+		gpio_configure_pads(dmic_disable_pads, ARRAY_SIZE(dmic_disable_pads));
+		gpio_configure_pads(bt_i2s_disable_pads, ARRAY_SIZE(bt_i2s_disable_pads));
+		return;
+	}
+
+	if (fw_config_probe(FW_CONFIG(AUDIO, NAU88L25B_I2S))) {
+		printk(BIOS_INFO, "Configure audio over I2S with NAU88L25B.\n");
+		gpio_configure_pads(dmic_enable_pads, ARRAY_SIZE(dmic_enable_pads));
+		gpio_configure_pads(i2s_enable_pads, ARRAY_SIZE(i2s_enable_pads));
+		printk(BIOS_INFO, "BT offload enabled\n");
+		gpio_configure_pads(bt_i2s_enable_pads, ARRAY_SIZE(bt_i2s_enable_pads));
+	} else {
+		printk(BIOS_INFO, "BT offload disabled\n");
+		gpio_configure_pads(bt_i2s_disable_pads, ARRAY_SIZE(bt_i2s_disable_pads));
+	}
+}
+BOOT_STATE_INIT_ENTRY(BS_DEV_ENABLE, BS_ON_ENTRY, fw_config_handle, NULL);
diff --git a/src/mainboard/google/brya/variants/moxoe/gpio.c b/src/mainboard/google/brya/variants/moxoe/gpio.c
new file mode 100644
index 0000000000..556e8b694c
--- /dev/null
+++ b/src/mainboard/google/brya/variants/moxoe/gpio.c
@@ -0,0 +1,133 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <baseboard/gpio.h>
+#include <baseboard/variants.h>
+#include <commonlib/helpers.h>
+#include <soc/gpio.h>
+
+/* Pad configuration in ramstage */
+static const struct pad_config override_gpio_table[] = {
+	/* A14 : USB_OC1# ==> HDMIA_HPD */
+	PAD_CFG_NF(GPP_A14, NONE, DEEP, NF2),
+	/* A15 : USB_OC2# ==> NC */
+	PAD_NC(GPP_A15, NONE),
+	/* A19 : DDSP_HPD1 ==> NC */
+	PAD_NC(GPP_A19, NONE),
+	/* A20 : DDSP_HPD2 ==> NC */
+	PAD_NC(GPP_A20, NONE),
+	/* A21 : DDPC_CTRCLK ==> NC */
+	PAD_NC(GPP_A21, NONE),
+	/* A22 : DDPC_CTRLDATA ==> NC */
+	PAD_NC(GPP_A22, NONE),
+
+	/* B7  : ISH_12C1_SDA ==> PCH_I2C_MISCB_SDA */
+	PAD_CFG_NF_LOCK(GPP_B7, NONE, NF2, LOCK_CONFIG),
+	/* B8  : ISH_I2C1_SCL ==> PCH_I2C_MISCB_SCL */
+	PAD_CFG_NF_LOCK(GPP_B8, NONE, NF2, LOCK_CONFIG),
+
+	/* C3 : SML0CLK ==> USB_C0_AUX_DC_P */
+	PAD_CFG_NF(GPP_C3, NONE, DEEP, NF6),
+	/* C4 : SML0DATA ==> USB_C0_AUX_DC_N */
+	PAD_CFG_NF(GPP_C4, NONE, DEEP, NF6),
+
+	/* D0  : ISH_GP0 ==> NC */
+	PAD_NC_LOCK(GPP_D0, NONE, LOCK_CONFIG),
+	/* D1  : ISH_GP1 ==> NC */
+	PAD_NC_LOCK(GPP_D1, NONE, LOCK_CONFIG),
+	/* D2  : ISH_GP2 ==> NC */
+	PAD_NC_LOCK(GPP_D2, NONE, LOCK_CONFIG),
+	/* D3  : ISH_GP3 ==> NC */
+	PAD_NC_LOCK(GPP_D3, NONE, LOCK_CONFIG),
+	/* D9  : ISH_SPI_CS# ==> NC */
+	PAD_NC_LOCK(GPP_D9, NONE, LOCK_CONFIG),
+
+	/* E20 : DDP2_CTRLCLK ==> HDMIA_CTRLCLK */
+	PAD_CFG_NF(GPP_E20, NONE, DEEP, NF1),
+	/* E21 : DDP2_CTRLDATA ==> HDMIA_CTRLDATA_STRAP */
+	PAD_CFG_NF(GPP_E21, NONE, DEEP, NF1),
+
+	/* F11 : THC1_SPI2_CLK ==> NC */
+	PAD_NC_LOCK(GPP_F11, NONE, LOCK_CONFIG),
+	/* F12 : GSXDOUT ==> NC */
+	PAD_NC_LOCK(GPP_F12, NONE, LOCK_CONFIG),
+	/* F13 : GSXDOUT ==> NC */
+	PAD_NC_LOCK(GPP_F13, NONE, LOCK_CONFIG),
+	/* F15 : GSXSRESET# ==> NC */
+	PAD_NC_LOCK(GPP_F15, NONE, LOCK_CONFIG),
+	/* F16 : GSXCLK ==> NC */
+	PAD_NC_LOCK(GPP_F16, NONE, LOCK_CONFIG),
+
+	/* R4 : HDA_RST# ==> NC */
+	PAD_NC(GPP_R4, NONE),
+	/* R5 : HDA_SDI1 ==> NC */
+	PAD_NC(GPP_R5, NONE),
+};
+
+/* Early pad configuration in bootblock */
+static const struct pad_config early_gpio_table[] = {
+	/* A13 : PMC_I2C_SCL ==> GSC_PCH_INT_ODL */
+	PAD_CFG_GPI_APIC(GPP_A13, NONE, PLTRST, LEVEL, INVERT),
+	/* B4  : PROC_GP3 ==> SSD_PERST_L */
+	PAD_CFG_GPO(GPP_B4, 0, DEEP),
+	/* E15 : RSVD_TP ==> PCH_WP_OD */
+	PAD_CFG_GPI_GPIO_DRIVER(GPP_E15, NONE, DEEP),
+	/* F14 : GSXDIN ==> EN_PP3300_SSD */
+	PAD_CFG_GPO(GPP_F14, 1, DEEP),
+	/* F18 : THC1_SPI2_INT# ==> EC_IN_RW_OD */
+	PAD_CFG_GPI(GPP_F18, NONE, DEEP),
+	/* H6  : I2C1_SDA ==> PCH_I2C_TPM_SDA */
+	PAD_CFG_NF(GPP_H6, NONE, DEEP, NF1),
+	/* H7  : I2C1_SCL ==> PCH_I2C_TPM_SCL */
+	PAD_CFG_NF(GPP_H7, NONE, DEEP, NF1),
+	/* H10 : UART0_RXD ==> UART_PCH_RX_DBG_TX */
+	PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2),
+	/* H11 : UART0_TXD ==> UART_PCH_TX_DBG_RX */
+	PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2),
+	/* H13 : I2C7_SCL ==> EN_PP3300_SD */
+	PAD_CFG_GPO(GPP_H13, 1, DEEP),
+
+	/* CPU PCIe VGPIO for PEG60 */
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_48, NONE, PLTRST, NF1),
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_49, NONE, PLTRST, NF1),
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_50, NONE, PLTRST, NF1),
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_51, NONE, PLTRST, NF1),
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_52, NONE, PLTRST, NF1),
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_53, NONE, PLTRST, NF1),
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_54, NONE, PLTRST, NF1),
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_55, NONE, PLTRST, NF1),
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_56, NONE, PLTRST, NF1),
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_57, NONE, PLTRST, NF1),
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_58, NONE, PLTRST, NF1),
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_59, NONE, PLTRST, NF1),
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_60, NONE, PLTRST, NF1),
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_61, NONE, PLTRST, NF1),
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_62, NONE, PLTRST, NF1),
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_63, NONE, PLTRST, NF1),
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_76, NONE, PLTRST, NF1),
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_77, NONE, PLTRST, NF1),
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_78, NONE, PLTRST, NF1),
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_79, NONE, PLTRST, NF1),
+};
+
+static const struct pad_config romstage_gpio_table[] = {
+	/* B4  : PROC_GP3 ==> SSD_PERST_L */
+	PAD_CFG_GPO(GPP_B4, 1, DEEP),
+};
+
+const struct pad_config *variant_gpio_override_table(size_t *num)
+{
+	*num = ARRAY_SIZE(override_gpio_table);
+	return override_gpio_table;
+}
+
+const struct pad_config *variant_early_gpio_table(size_t *num)
+{
+	*num = ARRAY_SIZE(early_gpio_table);
+	return early_gpio_table;
+}
+
+const struct pad_config *variant_romstage_gpio_table(size_t *num)
+{
+	*num = ARRAY_SIZE(romstage_gpio_table);
+	return romstage_gpio_table;
+}
diff --git a/src/mainboard/google/brya/variants/moxoe/include/variant/ec.h b/src/mainboard/google/brya/variants/moxoe/include/variant/ec.h
new file mode 100644
index 0000000000..7a2a6ff8b7
--- /dev/null
+++ b/src/mainboard/google/brya/variants/moxoe/include/variant/ec.h
@@ -0,0 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#ifndef __VARIANT_EC_H__
+#define __VARIANT_EC_H__
+
+#include <baseboard/ec.h>
+
+#endif
diff --git a/src/mainboard/google/brya/variants/moxoe/include/variant/gpio.h b/src/mainboard/google/brya/variants/moxoe/include/variant/gpio.h
new file mode 100644
index 0000000000..c4fe342621
--- /dev/null
+++ b/src/mainboard/google/brya/variants/moxoe/include/variant/gpio.h
@@ -0,0 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#ifndef VARIANT_GPIO_H
+#define VARIANT_GPIO_H
+
+#include <baseboard/gpio.h>
+
+#endif
diff --git a/src/mainboard/google/brya/variants/moxoe/overridetree.cb b/src/mainboard/google/brya/variants/moxoe/overridetree.cb
new file mode 100644
index 0000000000..9733305b69
--- /dev/null
+++ b/src/mainboard/google/brya/variants/moxoe/overridetree.cb
@@ -0,0 +1,354 @@
+fw_config
+	field AUDIO 0 2
+		option AUDIO_UNKNOWN	0
+		option NAU88L25B_I2S	1
+	end
+	field BJ_POWER 3 4
+		option BJ_POWER_150W	0
+		option BJ_POWER_230W	1
+		option BJ_POWER_65W	2
+		option BJ_POWER_135W	3
+	end
+	field MB_USBC 6 7
+		option TC_USB4	0
+		option TC_USB3	1
+	end
+	field USB_HUB 32
+		option HUB_ABSENT	0
+		option HUB_PRESENT	1
+	end
+end
+
+chip soc/intel/alderlake
+	register "domain_vr_config[VR_DOMAIN_IA]" = "{
+		.enable_fast_vmode = 1,
+	}"
+
+	register "sagv" = "SaGv_Enabled"
+
+	register "usb2_ports[1]" = "USB2_PORT_EMPTY"	# Disable USB2 Port 1
+	register "usb2_ports[2]" = "USB2_PORT_EMPTY"	# Disable USB2 Port 2
+	register "usb2_ports[4]" = "USB2_PORT_EMPTY"	# Disable USB2 Port 4
+
+	register "usb3_ports[0]" = "{
+		.enable           = 1,
+		.ocpin            = OC_SKIP,
+		.tx_de_emp        = 0x2B,
+		.tx_downscale_amp = 0x00,
+	}" # Type-A port A0
+	register "usb3_ports[1]" = "{
+		.enable           = 1,
+		.ocpin            = OC_SKIP,
+		.tx_de_emp        = 0x2B,
+		.tx_downscale_amp = 0x00,
+	}" # Type-A port A1
+
+	register "serial_io_gspi_mode" = "{
+		[PchSerialIoIndexGSPI0] = PchSerialIoDisabled,
+		[PchSerialIoIndexGSPI1] = PchSerialIoDisabled,
+	}"
+
+	register "ddi_ports_config" = "{
+		[DDI_PORT_A] = DDI_ENABLE_HPD,
+		[DDI_PORT_B] = DDI_ENABLE_HPD | DDI_ENABLE_DDC,
+		[DDI_PORT_1] = DDI_ENABLE_HPD,
+		[DDI_PORT_3] = DDI_ENABLE_HPD | DDI_ENABLE_DDC,
+	}"
+
+	register "power_limits_config[RPL_P_282_242_142_15W_CORE]" = "{
+		.tdp_pl1_override = 15,
+		.tdp_pl2_override = 55,
+		.tdp_pl4 = 100,
+	}"
+
+	device domain 0 on
+		device ref dtt on
+			chip drivers/intel/dptf
+				## sensor information
+				register "options.tsr[0].desc" = ""DRAM""
+				register "options.tsr[1].desc" = ""Charger""
+
+				# TODO: below values are initial reference values only
+				## Active Policy
+				register "policies.active" = "{
+					[0] = {
+						.target = DPTF_CPU,
+						.thresholds = {
+								TEMP_PCT(85, 90),
+								TEMP_PCT(80, 80),
+								TEMP_PCT(75, 70),
+						}
+					}
+				}"
+
+				## Passive Policy
+				register "policies.passive" = "{
+					[0] = DPTF_PASSIVE(CPU,         CPU,           95, 5000),
+					[1] = DPTF_PASSIVE(CPU,         TEMP_SENSOR_0, 75, 5000),
+					[2] = DPTF_PASSIVE(CHARGER,     TEMP_SENSOR_1, 75, 5000),
+				}"
+
+				## Critical Policy
+				register "policies.critical" = "{
+					[0] = DPTF_CRITICAL(CPU,               105, SHUTDOWN),
+					[1] = DPTF_CRITICAL(TEMP_SENSOR_0,      85, SHUTDOWN),
+					[2] = DPTF_CRITICAL(TEMP_SENSOR_1,      85, SHUTDOWN),
+				}"
+
+				register "controls.power_limits" = "{
+					.pl1 = {
+							.min_power = 3000,
+							.max_power = 15000,
+							.time_window_min = 28 * MSECS_PER_SEC,
+							.time_window_max = 32 * MSECS_PER_SEC,
+							.granularity = 200,
+						},
+					.pl2 = {
+							.min_power = 55000,
+							.max_power = 55000,
+							.time_window_min = 28 * MSECS_PER_SEC,
+							.time_window_max = 32 * MSECS_PER_SEC,
+							.granularity = 1000,
+						}
+				}"
+
+				## Charger Performance Control (Control, mA)
+				register "controls.charger_perf" = "{
+					[0] = { 255, 1700 },
+					[1] = {  24, 1500 },
+					[2] = {  16, 1000 },
+					[3] = {   8,  500 }
+				}"
+
+				## Fan Performance Control (Percent, Speed, Noise, Power)
+				register "controls.fan_perf" = "{
+					[0] = {  90, 6700, 220, 2200, },
+					[1] = {  80, 5800, 180, 1800, },
+					[2] = {  70, 5000, 145, 1450, },
+					[3] = {  60, 4900, 115, 1150, },
+					[4] = {  50, 3838,  90,  900, },
+					[5] = {  40, 2904,  55,  550, },
+					[6] = {  30, 2337,  30,  300, },
+					[7] = {  20, 1608,  15,  150, },
+					[8] = {  10,  800,  10,  100, },
+					[9] = {   0,    0,   0,   50, }
+				}"
+
+				## Fan options
+				register "options.fan.fine_grained_control" = "true"
+				register "options.fan.step_size" = "2"
+
+				device generic 0 alias dptf_policy on end
+			end
+		end
+		device ref pcie4_0 on
+			# Enable CPU PCIE RP 1 using CLK 0
+			register "cpu_pcie_rp[CPU_RP(1)]" = "{
+				.clk_req = 0,
+				.clk_src = 0,
+				.flags = PCIE_RP_LTR | PCIE_RP_AER,
+			}"
+			chip soc/intel/common/block/pcie/rtd3
+				register "is_storage" = "true"
+				register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_F14)"
+				register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B4)"
+				register "srcclk_pin" = "0"
+				device generic 0 on end
+			end
+		end
+		device ref tbt_pcie_rp0 on
+			probe MB_USBC TC_USB4
+		end
+		device ref tbt_pcie_rp1 on
+			probe MB_USBC TC_USB4
+		end
+		device ref tbt_pcie_rp2 on
+			probe MB_USBC TC_USB4
+		end
+		device ref tcss_dma0 on
+			probe MB_USBC TC_USB4
+			chip drivers/intel/usb4/retimer
+				register "dfp[0].power_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E4)"
+				use tcss_usb3_port1 as dfp[0].typec_port
+				device generic 0 on end
+			end
+		end
+		device ref cnvi_wifi on
+			chip drivers/wifi/generic
+				register "wake" = "GPE0_PME_B0"
+				device generic 0 on end
+			end
+		end
+		device ref i2c0 on
+			chip drivers/i2c/nau8825
+				register "irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPP_A23)"
+				register "jkdet_enable" = "1"
+				register "jkdet_pull_enable" = "0"
+				register "jkdet_pull_up" = "0"
+				register "jkdet_polarity" = "1"      # ActiveLow
+				register "vref_impedance" = "2"      # 125kOhm
+				register "micbias_voltage" = "6"     # 2.754
+				register "sar_threshold_num" = "4"
+				register "sar_threshold[0]" = "0x0C"
+				register "sar_threshold[1]" = "0x1C"
+				register "sar_threshold[2]" = "0x38"
+				register "sar_threshold[3]" = "0x60"
+				register "sar_hysteresis" = "1"
+				register "sar_voltage" = "0"          # VDDA
+				register "sar_compare_time" = "0"     # 500ns
+				register "sar_sampling_time" = "0"    # 2us
+				register "short_key_debounce" = "2"   # 100ms
+				register "jack_insert_debounce" = "7" # 512ms
+				register "jack_eject_debounce" = "7"  # 512ms
+				device i2c 1a on
+					probe AUDIO NAU88L25B_I2S
+				end
+			end
+		end
+		device ref pcie_rp7 on
+			chip drivers/net
+				register "wake" = "GPE0_DW0_07"
+				register "led_feature" = "0xe0"
+				register "customized_leds" = "0x05af"
+				register "customized_led0" = "0x23f"
+				register "customized_led2" = "0x028"
+				register "enable_aspm_l1_2" = "1"
+				register "add_acpi_dma_property" = "true"
+				device pci 00.0 on end
+			end
+		end # RTL8125 and RTL8111K Ethernet NIC
+		device ref pcie_rp8 on
+			chip soc/intel/common/block/pcie/rtd3
+				register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_H13)"
+				register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D18)"
+				register "srcclk_pin" = "3"
+				device generic 0 on end
+			end
+		end	#PCIE8 SD card
+		device ref gspi1 off end
+		device ref pch_espi on
+			chip ec/google/chromeec
+				use conn0 as mux_conn[0]
+				device pnp 0c09.0 on end
+			end
+		end
+		device ref pmc hidden
+			chip drivers/intel/pmc_mux
+				device generic 0 on
+					chip drivers/intel/pmc_mux/conn
+						use usb2_port1 as usb2_port
+						use tcss_usb3_port1 as usb3_port
+						device generic 0 alias conn0 on end
+					end
+				end
+			end
+		end
+		device ref tcss_xhci on
+			chip drivers/usb/acpi
+				device ref tcss_root_hub on
+					chip drivers/usb/acpi
+						register "desc" = ""USB3 Type-C Port C0 (MLB)""
+						register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
+						register "use_custom_pld" = "true"
+						register "custom_pld" = "ACPI_PLD_TYPE_C(BACK, RIGHT, ACPI_PLD_GROUP(1, 1))"
+						device ref tcss_usb3_port1 on end
+					end
+				end
+			end
+		end
+		device ref xhci on
+			chip drivers/usb/acpi
+				device ref xhci_root_hub on
+					chip drivers/usb/acpi
+						register "desc" = ""USB2 Type-C Port C0 (MLB)""
+						register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
+						register "use_custom_pld" = "true"
+						register "custom_pld" = "ACPI_PLD_TYPE_C(BACK, RIGHT, ACPI_PLD_GROUP(1, 1))"
+						device ref usb2_port1 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB2 Type-A Port A3 (MLB)""
+						register "type" = "UPC_TYPE_A"
+						register "use_custom_pld" = "true"
+						register "custom_pld" = "ACPI_PLD_TYPE_A(BACK, LEFT, ACPI_PLD_GROUP(5, 1))"
+						device ref usb2_port6 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB2 Type-A Port A2 (MLB)""
+						register "type" = "UPC_TYPE_A"
+						register "use_custom_pld" = "true"
+						register "custom_pld" = "ACPI_PLD_TYPE_A(BACK, CENTER, ACPI_PLD_GROUP(6, 1))"
+						device ref usb2_port7 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB2 Type-A Port A1 (MLB)""
+						register "type" = "UPC_TYPE_A"
+						register "use_custom_pld" = "true"
+						register "custom_pld" = "ACPI_PLD_TYPE_A(FRONT, LEFT, ACPI_PLD_GROUP(4, 1))"
+						device ref usb2_port8 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB2 Type-A Port A0 (MLB)""
+						register "type" = "UPC_TYPE_A"
+						register "use_custom_pld" = "true"
+						register "custom_pld" = "ACPI_PLD_TYPE_A(FRONT, RIGHT, ACPI_PLD_GROUP(1, 2))"
+						device ref usb2_port9 on
+							probe USB_HUB HUB_ABSENT
+						end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB2 Hub for Type-A Port A0/A4/A5 (MLB)""
+						register "type" = "UPC_TYPE_INTERNAL"
+						device ref usb2_port9 on
+							probe USB_HUB HUB_PRESENT
+						end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB2 Bluetooth""
+						register "type" = "UPC_TYPE_INTERNAL"
+						register "reset_gpio" =
+							"ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D4)"
+						device ref usb2_port10 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB3 Type-A Port A0 (MLB)""
+						register "type" = "UPC_TYPE_USB3_A"
+						register "use_custom_pld" = "true"
+						register "custom_pld" = "ACPI_PLD_TYPE_A(FRONT, RIGHT, ACPI_PLD_GROUP(1, 2))"
+						device ref usb3_port1 on
+							probe USB_HUB HUB_ABSENT
+						end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB3 Hub for Type-A Port A0/A4/A5 (MLB)""
+						register "type" = "UPC_TYPE_INTERNAL"
+						device ref usb3_port1 on
+							probe USB_HUB HUB_PRESENT
+						end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB3 Type-A Port A1 (MLB)""
+						register "type" = "UPC_TYPE_USB3_A"
+						register "use_custom_pld" = "true"
+						register "custom_pld" = "ACPI_PLD_TYPE_A(FRONT, LEFT, ACPI_PLD_GROUP(4, 1))"
+						device ref usb3_port2 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB3 Type-A Port A2 (MLB)""
+						register "type" = "UPC_TYPE_USB3_A"
+						register "use_custom_pld" = "true"
+						register "custom_pld" = "ACPI_PLD_TYPE_A(BACK, CENTER, ACPI_PLD_GROUP(6, 1))"
+						device ref usb3_port3 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB3 Type-A Port A3 (MLB)""
+						register "type" = "UPC_TYPE_USB3_A"
+						register "use_custom_pld" = "true"
+						register "custom_pld" = "ACPI_PLD_TYPE_A(BACK, LEFT, ACPI_PLD_GROUP(5, 1))"
+						device ref usb3_port4 on end
+					end
+				end
+			end
+		end
+	end
+end
diff --git a/src/mainboard/google/brya/variants/moxoe/ramstage.c b/src/mainboard/google/brya/variants/moxoe/ramstage.c
new file mode 100644
index 0000000000..de5254337a
--- /dev/null
+++ b/src/mainboard/google/brya/variants/moxoe/ramstage.c
@@ -0,0 +1,58 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <baseboard/variants.h>
+#include <chip.h>
+#include <device/device.h>
+#include <device/pci_ids.h>
+#include <device/pci_ops.h>
+#include <ec/google/chromeec/ec.h>
+#include <fw_config.h>
+#include <intelblocks/power_limit.h>
+
+const struct cpu_power_limits limits[] = {
+	/* SKU_ID, TDP (Watts), pl1_min, pl1_max, pl2_min, pl2_max, pl4 */
+	{ PCI_DID_INTEL_RPL_P_ID_5, 15, 15000, 15000,  55000,  55000, 100000 },
+	{ PCI_DID_INTEL_RPL_P_ID_4, 15, 15000, 15000,  55000,  55000, 100000 },
+	{ PCI_DID_INTEL_RPL_P_ID_3, 15, 15000, 15000,  55000,  55000, 100000 },
+};
+
+const struct system_power_limits sys_limits[] = {
+	/* SKU_ID, TDP (Watts), psys_pl2 (Watts) */
+	{ PCI_DID_INTEL_RPL_P_ID_5, 15, 138 },
+	{ PCI_DID_INTEL_RPL_P_ID_4, 15, 138 },
+	{ PCI_DID_INTEL_RPL_P_ID_3, 15, 138 },
+};
+
+/*
+ * Psys_pmax considerations.
+ *
+ * Given the hardware design in moxoe, the serial shunt resistor is 0.005ohm.
+ * The full scale of hardware PSYS signal 1.6v maps to system current 11.25A
+ * instead of real system power. The equation is shown below:
+ * PSYS = 1.6v = (0.005ohm x 11.25A) x 50 (INA213, gain 50V/V) x R501/(R501 + R510)
+ * R501/(R501 + R510) = 0.57 = 20K / (20K + 15K)
+ *
+ * The Psys_pmax is a SW setting which tells IMVP9.1 the mapping b/w system input
+ * current and the actual system power. Since there is no voltage information
+ * from PSYS, different voltage input would map to different Psys_pmax settings:
+ * For Type-C 15V, the Psys_pmax should be 15v x 11.25A = 168.75W
+ * For Type-C 20V, the Psys_pmax should be 20v x 11.25A = 225W
+ * For a barrel jack, the Psys_pmax should be 20v x 11.25A = 225W
+ *
+ * Imagine that there is a type-c 100W (20V/5A) connected to DUT w/ full loading,
+ * and the Psys_pmax setting is 225W. Then IMVP9.1 can calculate the current system
+ * power = 225W * 5A / 11.25A = 100W, which is the actual system power.
+ */
+const struct psys_config psys_config = {
+	.efficiency = 97,
+	.psys_imax_ma = 11250,
+	.bj_volts_mv = 20000
+};
+
+void variant_devtree_update(void)
+{
+	size_t total_entries = ARRAY_SIZE(limits);
+	variant_update_psys_power_limits(limits, sys_limits, total_entries, &psys_config);
+
+	variant_update_power_limits(limits, total_entries);
+}
diff --git a/src/mainboard/google/brya/variants/moxoe/variant.c b/src/mainboard/google/brya/variants/moxoe/variant.c
new file mode 100644
index 0000000000..b7cba968a5
--- /dev/null
+++ b/src/mainboard/google/brya/variants/moxoe/variant.c
@@ -0,0 +1,23 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <baseboard/variants.h>
+#include <chip.h>
+#include <fw_config.h>
+#include <sar.h>
+
+const char *get_wifi_sar_cbfs_filename(void)
+{
+	return "wifi_sar_0.hex";
+}
+
+void variant_update_soc_chip_config(struct soc_intel_alderlake_config *config)
+{
+	config->cnvi_bt_audio_offload = fw_config_probe(FW_CONFIG(AUDIO,
+							NAU88L25B_I2S));
+
+	if (fw_config_probe(FW_CONFIG(MB_USBC, TC_USB3))) {
+		config->tcss_aux_ori = 1;
+		config->typec_aux_bias_pads[0].pad_auxp_dc = GPP_C3;
+		config->typec_aux_bias_pads[0].pad_auxn_dc = GPP_C4;
+	}
+}

From f0bc0a5999a04342f780e74249a48ea992597bc7 Mon Sep 17 00:00:00 2001
From: David Wu <david_wu@quanta.corp-partner.google.com>
Date: Fri, 30 Jan 2026 19:40:17 +0800
Subject: [PATCH 3301/3886] mb/google/brya: Create kulnex variant

Create the kulnex variant of the kuldax project by
copying the files to a new directory named for the variant.

BUG=b:480035819
TEST=util/abuild/abuild -p none -t google/brya -x -a
make sure the build includes GOOGLE_KULNEX

Change-Id: Ice06b67aeaa3bb8f36a6d3721014888defbfac15
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91010
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kenneth Chan <kenneth.chan@quanta.corp-partner.google.com>
---
 src/mainboard/google/brya/Kconfig             |  11 +
 src/mainboard/google/brya/Kconfig.name        |   3 +
 .../google/brya/variants/kulnex/Makefile.mk   |   9 +
 .../google/brya/variants/kulnex/data.vbt      | Bin 0 -> 8704 bytes
 .../google/brya/variants/kulnex/fw_config.c   |  75 ++++
 .../google/brya/variants/kulnex/gpio.c        | 133 +++++++
 .../brya/variants/kulnex/include/variant/ec.h |   8 +
 .../variants/kulnex/include/variant/gpio.h    |   8 +
 .../brya/variants/kulnex/overridetree.cb      | 354 ++++++++++++++++++
 .../google/brya/variants/kulnex/ramstage.c    |  58 +++
 .../google/brya/variants/kulnex/variant.c     |  23 ++
 11 files changed, 682 insertions(+)
 create mode 100644 src/mainboard/google/brya/variants/kulnex/Makefile.mk
 create mode 100644 src/mainboard/google/brya/variants/kulnex/data.vbt
 create mode 100644 src/mainboard/google/brya/variants/kulnex/fw_config.c
 create mode 100644 src/mainboard/google/brya/variants/kulnex/gpio.c
 create mode 100644 src/mainboard/google/brya/variants/kulnex/include/variant/ec.h
 create mode 100644 src/mainboard/google/brya/variants/kulnex/include/variant/gpio.h
 create mode 100644 src/mainboard/google/brya/variants/kulnex/overridetree.cb
 create mode 100644 src/mainboard/google/brya/variants/kulnex/ramstage.c
 create mode 100644 src/mainboard/google/brya/variants/kulnex/variant.c

diff --git a/src/mainboard/google/brya/Kconfig b/src/mainboard/google/brya/Kconfig
index dd23e4d651..56498ecf04 100644
--- a/src/mainboard/google/brya/Kconfig
+++ b/src/mainboard/google/brya/Kconfig
@@ -359,6 +359,13 @@ config BOARD_GOOGLE_KULDAX
 	select INTEL_GMA_HAVE_VBT
 	select SOC_INTEL_RAPTORLAKE
 
+config BOARD_GOOGLE_KULNEX
+	select BOARD_GOOGLE_BASEBOARD_BRASK
+	select DRIVERS_GENESYSLOGIC_GL9755
+	select EC_GOOGLE_CHROMEEC_INCLUDE_SSFC_IN_FW_CONFIG
+	select INTEL_GMA_HAVE_VBT
+	select SOC_INTEL_RAPTORLAKE
+
 config BOARD_GOOGLE_JOXER
 	select BOARD_GOOGLE_BASEBOARD_NISSA
 	select CHROMEOS_WIFI_SAR if CHROMEOS
@@ -873,6 +880,7 @@ config DRIVER_TPM_I2C_BUS
 	default 0x0 if BOARD_GOOGLE_KALADIN
 	default 0x1 if BOARD_GOOGLE_KINOX
 	default 0x1 if BOARD_GOOGLE_KULDAX
+	default 0x1 if BOARD_GOOGLE_KULNEX
 	default 0x1 if BOARD_GOOGLE_LISBON
 	default 0x1 if BOARD_GOOGLE_MARASOV
 	default 0x1 if BOARD_GOOGLE_MITHRAX
@@ -962,6 +970,7 @@ config TPM_TIS_ACPI_INTERRUPT
 	default 13 if BOARD_GOOGLE_KALADIN
 	default 13 if BOARD_GOOGLE_KINOX
 	default 13 if BOARD_GOOGLE_KULDAX
+	default 13 if BOARD_GOOGLE_KULNEX
 	default 13 if BOARD_GOOGLE_LISBON
 	default 13 if BOARD_GOOGLE_MARASOV
 	default 13 if BOARD_GOOGLE_MITHRAX
@@ -1055,6 +1064,7 @@ config MAINBOARD_PART_NUMBER
 	default "Kaladin" if BOARD_GOOGLE_KALADIN
 	default "Kinox" if BOARD_GOOGLE_KINOX
 	default "Kuldax" if BOARD_GOOGLE_KULDAX
+	default "Kulnex" if BOARD_GOOGLE_KULNEX
 	default "Lisbon" if BOARD_GOOGLE_LISBON
 	default "Marasov" if BOARD_GOOGLE_MARASOV
 	default "Mithrax" if BOARD_GOOGLE_MITHRAX
@@ -1137,6 +1147,7 @@ config VARIANT_DIR
 	default "kaladin" if BOARD_GOOGLE_KALADIN
 	default "kinox" if BOARD_GOOGLE_KINOX
 	default "kuldax" if BOARD_GOOGLE_KULDAX
+	default "kulnex" if BOARD_GOOGLE_KULNEX
 	default "lisbon" if BOARD_GOOGLE_LISBON
 	default "marasov" if BOARD_GOOGLE_MARASOV
 	default "mithrax" if BOARD_GOOGLE_MITHRAX
diff --git a/src/mainboard/google/brya/Kconfig.name b/src/mainboard/google/brya/Kconfig.name
index 4e32500b63..bce6d1c83f 100644
--- a/src/mainboard/google/brya/Kconfig.name
+++ b/src/mainboard/google/brya/Kconfig.name
@@ -95,6 +95,9 @@ config BOARD_GOOGLE_KINOX
 config BOARD_GOOGLE_KULDAX
 	bool "->  Kuldax (ASUS Chromebox 5/5a (CN67))"
 
+config BOARD_GOOGLE_KULNEX
+	bool "->  Kulnex"
+
 config BOARD_GOOGLE_JOXER
 	bool "->  Joxer (HP Chromebook x360 14b)"
 
diff --git a/src/mainboard/google/brya/variants/kulnex/Makefile.mk b/src/mainboard/google/brya/variants/kulnex/Makefile.mk
new file mode 100644
index 0000000000..e31aaa1707
--- /dev/null
+++ b/src/mainboard/google/brya/variants/kulnex/Makefile.mk
@@ -0,0 +1,9 @@
+# SPDX-License-Identifier: GPL-2.0-only
+bootblock-y += gpio.c
+
+romstage-y += gpio.c
+
+ramstage-y += gpio.c
+ramstage-y += ramstage.c
+ramstage-$(CONFIG_FW_CONFIG) += fw_config.c
+ramstage-$(CONFIG_FW_CONFIG) += variant.c
diff --git a/src/mainboard/google/brya/variants/kulnex/data.vbt b/src/mainboard/google/brya/variants/kulnex/data.vbt
new file mode 100644
index 0000000000000000000000000000000000000000..7d14588c613c3501ddb3970a2254560b709b00a0
GIT binary patch
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diff --git a/src/mainboard/google/brya/variants/kulnex/fw_config.c b/src/mainboard/google/brya/variants/kulnex/fw_config.c
new file mode 100644
index 0000000000..42613af163
--- /dev/null
+++ b/src/mainboard/google/brya/variants/kulnex/fw_config.c
@@ -0,0 +1,75 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <bootstate.h>
+#include <console/console.h>
+#include <fw_config.h>
+#include <gpio.h>
+
+static const struct pad_config dmic_enable_pads[] = {
+	PAD_CFG_NF(GPP_R6, NONE, DEEP, NF3),	/* DMIC_CLK1_R */
+	PAD_CFG_NF(GPP_R7, NONE, DEEP, NF3),	/* DMIC_DATA1_R */
+};
+
+static const struct pad_config dmic_disable_pads[] = {
+	PAD_NC(GPP_R6, NONE),
+	PAD_NC(GPP_R7, NONE),
+};
+
+static const struct pad_config i2s_enable_pads[] = {
+	PAD_CFG_NF(GPP_R0, NONE, DEEP, NF2),	/* I2S_HP_SCLK_R */
+	PAD_CFG_NF(GPP_R1, NONE, DEEP, NF2),	/* I2S_HP_SFRM_R */
+	PAD_CFG_NF(GPP_R2, DN_20K, DEEP, NF2),	/* I2S_PCH_TX_HP_RX_STRAP */
+	PAD_CFG_NF(GPP_R3, NONE, DEEP, NF2),	/* I2S_PCH_RX_HP_TX */
+};
+
+static const struct pad_config i2s_disable_pads[] = {
+	PAD_NC(GPP_R0, NONE),
+	PAD_NC(GPP_R1, NONE),
+	PAD_NC(GPP_R2, NONE),
+	PAD_NC(GPP_R3, NONE),
+};
+
+static const struct pad_config bt_i2s_enable_pads[] = {
+	PAD_CFG_NF(GPP_VGPIO_30, NONE, DEEP, NF3),	/* BT_I2S_BCLK */
+	PAD_CFG_NF(GPP_VGPIO_31, NONE, DEEP, NF3),	/* BT_I2S_SYNC */
+	PAD_CFG_NF(GPP_VGPIO_32, NONE, DEEP, NF3),	/* BT_I2S_SDO */
+	PAD_CFG_NF(GPP_VGPIO_33, NONE, DEEP, NF3),	/* BT_I2S_SDI */
+	PAD_CFG_NF(GPP_VGPIO_34, NONE, DEEP, NF1),	/* SSP2_SCLK */
+	PAD_CFG_NF(GPP_VGPIO_35, NONE, DEEP, NF1),	/* SSP2_SFRM */
+	PAD_CFG_NF(GPP_VGPIO_36, NONE, DEEP, NF1),	/* SSP_TXD */
+	PAD_CFG_NF(GPP_VGPIO_37, NONE, DEEP, NF1),	/* SSP_RXD */
+};
+
+static const struct pad_config bt_i2s_disable_pads[] = {
+	PAD_NC(GPP_VGPIO_30, NONE),
+	PAD_NC(GPP_VGPIO_31, NONE),
+	PAD_NC(GPP_VGPIO_32, NONE),
+	PAD_NC(GPP_VGPIO_33, NONE),
+	PAD_NC(GPP_VGPIO_34, NONE),
+	PAD_NC(GPP_VGPIO_35, NONE),
+	PAD_NC(GPP_VGPIO_36, NONE),
+	PAD_NC(GPP_VGPIO_37, NONE),
+};
+
+static void fw_config_handle(void *unused)
+{
+	if (!fw_config_is_provisioned() || fw_config_probe(FW_CONFIG(AUDIO, AUDIO_UNKNOWN))) {
+		printk(BIOS_INFO, "Disable audio related GPIO pins.\n");
+		gpio_configure_pads(i2s_disable_pads, ARRAY_SIZE(i2s_disable_pads));
+		gpio_configure_pads(dmic_disable_pads, ARRAY_SIZE(dmic_disable_pads));
+		gpio_configure_pads(bt_i2s_disable_pads, ARRAY_SIZE(bt_i2s_disable_pads));
+		return;
+	}
+
+	if (fw_config_probe(FW_CONFIG(AUDIO, NAU88L25B_I2S))) {
+		printk(BIOS_INFO, "Configure audio over I2S with NAU88L25B.\n");
+		gpio_configure_pads(dmic_enable_pads, ARRAY_SIZE(dmic_enable_pads));
+		gpio_configure_pads(i2s_enable_pads, ARRAY_SIZE(i2s_enable_pads));
+		printk(BIOS_INFO, "BT offload enabled\n");
+		gpio_configure_pads(bt_i2s_enable_pads, ARRAY_SIZE(bt_i2s_enable_pads));
+	} else {
+		printk(BIOS_INFO, "BT offload disabled\n");
+		gpio_configure_pads(bt_i2s_disable_pads, ARRAY_SIZE(bt_i2s_disable_pads));
+	}
+}
+BOOT_STATE_INIT_ENTRY(BS_DEV_ENABLE, BS_ON_ENTRY, fw_config_handle, NULL);
diff --git a/src/mainboard/google/brya/variants/kulnex/gpio.c b/src/mainboard/google/brya/variants/kulnex/gpio.c
new file mode 100644
index 0000000000..556e8b694c
--- /dev/null
+++ b/src/mainboard/google/brya/variants/kulnex/gpio.c
@@ -0,0 +1,133 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <baseboard/gpio.h>
+#include <baseboard/variants.h>
+#include <commonlib/helpers.h>
+#include <soc/gpio.h>
+
+/* Pad configuration in ramstage */
+static const struct pad_config override_gpio_table[] = {
+	/* A14 : USB_OC1# ==> HDMIA_HPD */
+	PAD_CFG_NF(GPP_A14, NONE, DEEP, NF2),
+	/* A15 : USB_OC2# ==> NC */
+	PAD_NC(GPP_A15, NONE),
+	/* A19 : DDSP_HPD1 ==> NC */
+	PAD_NC(GPP_A19, NONE),
+	/* A20 : DDSP_HPD2 ==> NC */
+	PAD_NC(GPP_A20, NONE),
+	/* A21 : DDPC_CTRCLK ==> NC */
+	PAD_NC(GPP_A21, NONE),
+	/* A22 : DDPC_CTRLDATA ==> NC */
+	PAD_NC(GPP_A22, NONE),
+
+	/* B7  : ISH_12C1_SDA ==> PCH_I2C_MISCB_SDA */
+	PAD_CFG_NF_LOCK(GPP_B7, NONE, NF2, LOCK_CONFIG),
+	/* B8  : ISH_I2C1_SCL ==> PCH_I2C_MISCB_SCL */
+	PAD_CFG_NF_LOCK(GPP_B8, NONE, NF2, LOCK_CONFIG),
+
+	/* C3 : SML0CLK ==> USB_C0_AUX_DC_P */
+	PAD_CFG_NF(GPP_C3, NONE, DEEP, NF6),
+	/* C4 : SML0DATA ==> USB_C0_AUX_DC_N */
+	PAD_CFG_NF(GPP_C4, NONE, DEEP, NF6),
+
+	/* D0  : ISH_GP0 ==> NC */
+	PAD_NC_LOCK(GPP_D0, NONE, LOCK_CONFIG),
+	/* D1  : ISH_GP1 ==> NC */
+	PAD_NC_LOCK(GPP_D1, NONE, LOCK_CONFIG),
+	/* D2  : ISH_GP2 ==> NC */
+	PAD_NC_LOCK(GPP_D2, NONE, LOCK_CONFIG),
+	/* D3  : ISH_GP3 ==> NC */
+	PAD_NC_LOCK(GPP_D3, NONE, LOCK_CONFIG),
+	/* D9  : ISH_SPI_CS# ==> NC */
+	PAD_NC_LOCK(GPP_D9, NONE, LOCK_CONFIG),
+
+	/* E20 : DDP2_CTRLCLK ==> HDMIA_CTRLCLK */
+	PAD_CFG_NF(GPP_E20, NONE, DEEP, NF1),
+	/* E21 : DDP2_CTRLDATA ==> HDMIA_CTRLDATA_STRAP */
+	PAD_CFG_NF(GPP_E21, NONE, DEEP, NF1),
+
+	/* F11 : THC1_SPI2_CLK ==> NC */
+	PAD_NC_LOCK(GPP_F11, NONE, LOCK_CONFIG),
+	/* F12 : GSXDOUT ==> NC */
+	PAD_NC_LOCK(GPP_F12, NONE, LOCK_CONFIG),
+	/* F13 : GSXDOUT ==> NC */
+	PAD_NC_LOCK(GPP_F13, NONE, LOCK_CONFIG),
+	/* F15 : GSXSRESET# ==> NC */
+	PAD_NC_LOCK(GPP_F15, NONE, LOCK_CONFIG),
+	/* F16 : GSXCLK ==> NC */
+	PAD_NC_LOCK(GPP_F16, NONE, LOCK_CONFIG),
+
+	/* R4 : HDA_RST# ==> NC */
+	PAD_NC(GPP_R4, NONE),
+	/* R5 : HDA_SDI1 ==> NC */
+	PAD_NC(GPP_R5, NONE),
+};
+
+/* Early pad configuration in bootblock */
+static const struct pad_config early_gpio_table[] = {
+	/* A13 : PMC_I2C_SCL ==> GSC_PCH_INT_ODL */
+	PAD_CFG_GPI_APIC(GPP_A13, NONE, PLTRST, LEVEL, INVERT),
+	/* B4  : PROC_GP3 ==> SSD_PERST_L */
+	PAD_CFG_GPO(GPP_B4, 0, DEEP),
+	/* E15 : RSVD_TP ==> PCH_WP_OD */
+	PAD_CFG_GPI_GPIO_DRIVER(GPP_E15, NONE, DEEP),
+	/* F14 : GSXDIN ==> EN_PP3300_SSD */
+	PAD_CFG_GPO(GPP_F14, 1, DEEP),
+	/* F18 : THC1_SPI2_INT# ==> EC_IN_RW_OD */
+	PAD_CFG_GPI(GPP_F18, NONE, DEEP),
+	/* H6  : I2C1_SDA ==> PCH_I2C_TPM_SDA */
+	PAD_CFG_NF(GPP_H6, NONE, DEEP, NF1),
+	/* H7  : I2C1_SCL ==> PCH_I2C_TPM_SCL */
+	PAD_CFG_NF(GPP_H7, NONE, DEEP, NF1),
+	/* H10 : UART0_RXD ==> UART_PCH_RX_DBG_TX */
+	PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2),
+	/* H11 : UART0_TXD ==> UART_PCH_TX_DBG_RX */
+	PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2),
+	/* H13 : I2C7_SCL ==> EN_PP3300_SD */
+	PAD_CFG_GPO(GPP_H13, 1, DEEP),
+
+	/* CPU PCIe VGPIO for PEG60 */
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_48, NONE, PLTRST, NF1),
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_49, NONE, PLTRST, NF1),
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_50, NONE, PLTRST, NF1),
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_51, NONE, PLTRST, NF1),
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_52, NONE, PLTRST, NF1),
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_53, NONE, PLTRST, NF1),
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_54, NONE, PLTRST, NF1),
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_55, NONE, PLTRST, NF1),
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_56, NONE, PLTRST, NF1),
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_57, NONE, PLTRST, NF1),
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_58, NONE, PLTRST, NF1),
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_59, NONE, PLTRST, NF1),
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_60, NONE, PLTRST, NF1),
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_61, NONE, PLTRST, NF1),
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_62, NONE, PLTRST, NF1),
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_63, NONE, PLTRST, NF1),
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_76, NONE, PLTRST, NF1),
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_77, NONE, PLTRST, NF1),
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_78, NONE, PLTRST, NF1),
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_79, NONE, PLTRST, NF1),
+};
+
+static const struct pad_config romstage_gpio_table[] = {
+	/* B4  : PROC_GP3 ==> SSD_PERST_L */
+	PAD_CFG_GPO(GPP_B4, 1, DEEP),
+};
+
+const struct pad_config *variant_gpio_override_table(size_t *num)
+{
+	*num = ARRAY_SIZE(override_gpio_table);
+	return override_gpio_table;
+}
+
+const struct pad_config *variant_early_gpio_table(size_t *num)
+{
+	*num = ARRAY_SIZE(early_gpio_table);
+	return early_gpio_table;
+}
+
+const struct pad_config *variant_romstage_gpio_table(size_t *num)
+{
+	*num = ARRAY_SIZE(romstage_gpio_table);
+	return romstage_gpio_table;
+}
diff --git a/src/mainboard/google/brya/variants/kulnex/include/variant/ec.h b/src/mainboard/google/brya/variants/kulnex/include/variant/ec.h
new file mode 100644
index 0000000000..7a2a6ff8b7
--- /dev/null
+++ b/src/mainboard/google/brya/variants/kulnex/include/variant/ec.h
@@ -0,0 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#ifndef __VARIANT_EC_H__
+#define __VARIANT_EC_H__
+
+#include <baseboard/ec.h>
+
+#endif
diff --git a/src/mainboard/google/brya/variants/kulnex/include/variant/gpio.h b/src/mainboard/google/brya/variants/kulnex/include/variant/gpio.h
new file mode 100644
index 0000000000..c4fe342621
--- /dev/null
+++ b/src/mainboard/google/brya/variants/kulnex/include/variant/gpio.h
@@ -0,0 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#ifndef VARIANT_GPIO_H
+#define VARIANT_GPIO_H
+
+#include <baseboard/gpio.h>
+
+#endif
diff --git a/src/mainboard/google/brya/variants/kulnex/overridetree.cb b/src/mainboard/google/brya/variants/kulnex/overridetree.cb
new file mode 100644
index 0000000000..9733305b69
--- /dev/null
+++ b/src/mainboard/google/brya/variants/kulnex/overridetree.cb
@@ -0,0 +1,354 @@
+fw_config
+	field AUDIO 0 2
+		option AUDIO_UNKNOWN	0
+		option NAU88L25B_I2S	1
+	end
+	field BJ_POWER 3 4
+		option BJ_POWER_150W	0
+		option BJ_POWER_230W	1
+		option BJ_POWER_65W	2
+		option BJ_POWER_135W	3
+	end
+	field MB_USBC 6 7
+		option TC_USB4	0
+		option TC_USB3	1
+	end
+	field USB_HUB 32
+		option HUB_ABSENT	0
+		option HUB_PRESENT	1
+	end
+end
+
+chip soc/intel/alderlake
+	register "domain_vr_config[VR_DOMAIN_IA]" = "{
+		.enable_fast_vmode = 1,
+	}"
+
+	register "sagv" = "SaGv_Enabled"
+
+	register "usb2_ports[1]" = "USB2_PORT_EMPTY"	# Disable USB2 Port 1
+	register "usb2_ports[2]" = "USB2_PORT_EMPTY"	# Disable USB2 Port 2
+	register "usb2_ports[4]" = "USB2_PORT_EMPTY"	# Disable USB2 Port 4
+
+	register "usb3_ports[0]" = "{
+		.enable           = 1,
+		.ocpin            = OC_SKIP,
+		.tx_de_emp        = 0x2B,
+		.tx_downscale_amp = 0x00,
+	}" # Type-A port A0
+	register "usb3_ports[1]" = "{
+		.enable           = 1,
+		.ocpin            = OC_SKIP,
+		.tx_de_emp        = 0x2B,
+		.tx_downscale_amp = 0x00,
+	}" # Type-A port A1
+
+	register "serial_io_gspi_mode" = "{
+		[PchSerialIoIndexGSPI0] = PchSerialIoDisabled,
+		[PchSerialIoIndexGSPI1] = PchSerialIoDisabled,
+	}"
+
+	register "ddi_ports_config" = "{
+		[DDI_PORT_A] = DDI_ENABLE_HPD,
+		[DDI_PORT_B] = DDI_ENABLE_HPD | DDI_ENABLE_DDC,
+		[DDI_PORT_1] = DDI_ENABLE_HPD,
+		[DDI_PORT_3] = DDI_ENABLE_HPD | DDI_ENABLE_DDC,
+	}"
+
+	register "power_limits_config[RPL_P_282_242_142_15W_CORE]" = "{
+		.tdp_pl1_override = 15,
+		.tdp_pl2_override = 55,
+		.tdp_pl4 = 100,
+	}"
+
+	device domain 0 on
+		device ref dtt on
+			chip drivers/intel/dptf
+				## sensor information
+				register "options.tsr[0].desc" = ""DRAM""
+				register "options.tsr[1].desc" = ""Charger""
+
+				# TODO: below values are initial reference values only
+				## Active Policy
+				register "policies.active" = "{
+					[0] = {
+						.target = DPTF_CPU,
+						.thresholds = {
+								TEMP_PCT(85, 90),
+								TEMP_PCT(80, 80),
+								TEMP_PCT(75, 70),
+						}
+					}
+				}"
+
+				## Passive Policy
+				register "policies.passive" = "{
+					[0] = DPTF_PASSIVE(CPU,         CPU,           95, 5000),
+					[1] = DPTF_PASSIVE(CPU,         TEMP_SENSOR_0, 75, 5000),
+					[2] = DPTF_PASSIVE(CHARGER,     TEMP_SENSOR_1, 75, 5000),
+				}"
+
+				## Critical Policy
+				register "policies.critical" = "{
+					[0] = DPTF_CRITICAL(CPU,               105, SHUTDOWN),
+					[1] = DPTF_CRITICAL(TEMP_SENSOR_0,      85, SHUTDOWN),
+					[2] = DPTF_CRITICAL(TEMP_SENSOR_1,      85, SHUTDOWN),
+				}"
+
+				register "controls.power_limits" = "{
+					.pl1 = {
+							.min_power = 3000,
+							.max_power = 15000,
+							.time_window_min = 28 * MSECS_PER_SEC,
+							.time_window_max = 32 * MSECS_PER_SEC,
+							.granularity = 200,
+						},
+					.pl2 = {
+							.min_power = 55000,
+							.max_power = 55000,
+							.time_window_min = 28 * MSECS_PER_SEC,
+							.time_window_max = 32 * MSECS_PER_SEC,
+							.granularity = 1000,
+						}
+				}"
+
+				## Charger Performance Control (Control, mA)
+				register "controls.charger_perf" = "{
+					[0] = { 255, 1700 },
+					[1] = {  24, 1500 },
+					[2] = {  16, 1000 },
+					[3] = {   8,  500 }
+				}"
+
+				## Fan Performance Control (Percent, Speed, Noise, Power)
+				register "controls.fan_perf" = "{
+					[0] = {  90, 6700, 220, 2200, },
+					[1] = {  80, 5800, 180, 1800, },
+					[2] = {  70, 5000, 145, 1450, },
+					[3] = {  60, 4900, 115, 1150, },
+					[4] = {  50, 3838,  90,  900, },
+					[5] = {  40, 2904,  55,  550, },
+					[6] = {  30, 2337,  30,  300, },
+					[7] = {  20, 1608,  15,  150, },
+					[8] = {  10,  800,  10,  100, },
+					[9] = {   0,    0,   0,   50, }
+				}"
+
+				## Fan options
+				register "options.fan.fine_grained_control" = "true"
+				register "options.fan.step_size" = "2"
+
+				device generic 0 alias dptf_policy on end
+			end
+		end
+		device ref pcie4_0 on
+			# Enable CPU PCIE RP 1 using CLK 0
+			register "cpu_pcie_rp[CPU_RP(1)]" = "{
+				.clk_req = 0,
+				.clk_src = 0,
+				.flags = PCIE_RP_LTR | PCIE_RP_AER,
+			}"
+			chip soc/intel/common/block/pcie/rtd3
+				register "is_storage" = "true"
+				register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_F14)"
+				register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B4)"
+				register "srcclk_pin" = "0"
+				device generic 0 on end
+			end
+		end
+		device ref tbt_pcie_rp0 on
+			probe MB_USBC TC_USB4
+		end
+		device ref tbt_pcie_rp1 on
+			probe MB_USBC TC_USB4
+		end
+		device ref tbt_pcie_rp2 on
+			probe MB_USBC TC_USB4
+		end
+		device ref tcss_dma0 on
+			probe MB_USBC TC_USB4
+			chip drivers/intel/usb4/retimer
+				register "dfp[0].power_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E4)"
+				use tcss_usb3_port1 as dfp[0].typec_port
+				device generic 0 on end
+			end
+		end
+		device ref cnvi_wifi on
+			chip drivers/wifi/generic
+				register "wake" = "GPE0_PME_B0"
+				device generic 0 on end
+			end
+		end
+		device ref i2c0 on
+			chip drivers/i2c/nau8825
+				register "irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPP_A23)"
+				register "jkdet_enable" = "1"
+				register "jkdet_pull_enable" = "0"
+				register "jkdet_pull_up" = "0"
+				register "jkdet_polarity" = "1"      # ActiveLow
+				register "vref_impedance" = "2"      # 125kOhm
+				register "micbias_voltage" = "6"     # 2.754
+				register "sar_threshold_num" = "4"
+				register "sar_threshold[0]" = "0x0C"
+				register "sar_threshold[1]" = "0x1C"
+				register "sar_threshold[2]" = "0x38"
+				register "sar_threshold[3]" = "0x60"
+				register "sar_hysteresis" = "1"
+				register "sar_voltage" = "0"          # VDDA
+				register "sar_compare_time" = "0"     # 500ns
+				register "sar_sampling_time" = "0"    # 2us
+				register "short_key_debounce" = "2"   # 100ms
+				register "jack_insert_debounce" = "7" # 512ms
+				register "jack_eject_debounce" = "7"  # 512ms
+				device i2c 1a on
+					probe AUDIO NAU88L25B_I2S
+				end
+			end
+		end
+		device ref pcie_rp7 on
+			chip drivers/net
+				register "wake" = "GPE0_DW0_07"
+				register "led_feature" = "0xe0"
+				register "customized_leds" = "0x05af"
+				register "customized_led0" = "0x23f"
+				register "customized_led2" = "0x028"
+				register "enable_aspm_l1_2" = "1"
+				register "add_acpi_dma_property" = "true"
+				device pci 00.0 on end
+			end
+		end # RTL8125 and RTL8111K Ethernet NIC
+		device ref pcie_rp8 on
+			chip soc/intel/common/block/pcie/rtd3
+				register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_H13)"
+				register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D18)"
+				register "srcclk_pin" = "3"
+				device generic 0 on end
+			end
+		end	#PCIE8 SD card
+		device ref gspi1 off end
+		device ref pch_espi on
+			chip ec/google/chromeec
+				use conn0 as mux_conn[0]
+				device pnp 0c09.0 on end
+			end
+		end
+		device ref pmc hidden
+			chip drivers/intel/pmc_mux
+				device generic 0 on
+					chip drivers/intel/pmc_mux/conn
+						use usb2_port1 as usb2_port
+						use tcss_usb3_port1 as usb3_port
+						device generic 0 alias conn0 on end
+					end
+				end
+			end
+		end
+		device ref tcss_xhci on
+			chip drivers/usb/acpi
+				device ref tcss_root_hub on
+					chip drivers/usb/acpi
+						register "desc" = ""USB3 Type-C Port C0 (MLB)""
+						register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
+						register "use_custom_pld" = "true"
+						register "custom_pld" = "ACPI_PLD_TYPE_C(BACK, RIGHT, ACPI_PLD_GROUP(1, 1))"
+						device ref tcss_usb3_port1 on end
+					end
+				end
+			end
+		end
+		device ref xhci on
+			chip drivers/usb/acpi
+				device ref xhci_root_hub on
+					chip drivers/usb/acpi
+						register "desc" = ""USB2 Type-C Port C0 (MLB)""
+						register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
+						register "use_custom_pld" = "true"
+						register "custom_pld" = "ACPI_PLD_TYPE_C(BACK, RIGHT, ACPI_PLD_GROUP(1, 1))"
+						device ref usb2_port1 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB2 Type-A Port A3 (MLB)""
+						register "type" = "UPC_TYPE_A"
+						register "use_custom_pld" = "true"
+						register "custom_pld" = "ACPI_PLD_TYPE_A(BACK, LEFT, ACPI_PLD_GROUP(5, 1))"
+						device ref usb2_port6 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB2 Type-A Port A2 (MLB)""
+						register "type" = "UPC_TYPE_A"
+						register "use_custom_pld" = "true"
+						register "custom_pld" = "ACPI_PLD_TYPE_A(BACK, CENTER, ACPI_PLD_GROUP(6, 1))"
+						device ref usb2_port7 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB2 Type-A Port A1 (MLB)""
+						register "type" = "UPC_TYPE_A"
+						register "use_custom_pld" = "true"
+						register "custom_pld" = "ACPI_PLD_TYPE_A(FRONT, LEFT, ACPI_PLD_GROUP(4, 1))"
+						device ref usb2_port8 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB2 Type-A Port A0 (MLB)""
+						register "type" = "UPC_TYPE_A"
+						register "use_custom_pld" = "true"
+						register "custom_pld" = "ACPI_PLD_TYPE_A(FRONT, RIGHT, ACPI_PLD_GROUP(1, 2))"
+						device ref usb2_port9 on
+							probe USB_HUB HUB_ABSENT
+						end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB2 Hub for Type-A Port A0/A4/A5 (MLB)""
+						register "type" = "UPC_TYPE_INTERNAL"
+						device ref usb2_port9 on
+							probe USB_HUB HUB_PRESENT
+						end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB2 Bluetooth""
+						register "type" = "UPC_TYPE_INTERNAL"
+						register "reset_gpio" =
+							"ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D4)"
+						device ref usb2_port10 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB3 Type-A Port A0 (MLB)""
+						register "type" = "UPC_TYPE_USB3_A"
+						register "use_custom_pld" = "true"
+						register "custom_pld" = "ACPI_PLD_TYPE_A(FRONT, RIGHT, ACPI_PLD_GROUP(1, 2))"
+						device ref usb3_port1 on
+							probe USB_HUB HUB_ABSENT
+						end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB3 Hub for Type-A Port A0/A4/A5 (MLB)""
+						register "type" = "UPC_TYPE_INTERNAL"
+						device ref usb3_port1 on
+							probe USB_HUB HUB_PRESENT
+						end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB3 Type-A Port A1 (MLB)""
+						register "type" = "UPC_TYPE_USB3_A"
+						register "use_custom_pld" = "true"
+						register "custom_pld" = "ACPI_PLD_TYPE_A(FRONT, LEFT, ACPI_PLD_GROUP(4, 1))"
+						device ref usb3_port2 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB3 Type-A Port A2 (MLB)""
+						register "type" = "UPC_TYPE_USB3_A"
+						register "use_custom_pld" = "true"
+						register "custom_pld" = "ACPI_PLD_TYPE_A(BACK, CENTER, ACPI_PLD_GROUP(6, 1))"
+						device ref usb3_port3 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB3 Type-A Port A3 (MLB)""
+						register "type" = "UPC_TYPE_USB3_A"
+						register "use_custom_pld" = "true"
+						register "custom_pld" = "ACPI_PLD_TYPE_A(BACK, LEFT, ACPI_PLD_GROUP(5, 1))"
+						device ref usb3_port4 on end
+					end
+				end
+			end
+		end
+	end
+end
diff --git a/src/mainboard/google/brya/variants/kulnex/ramstage.c b/src/mainboard/google/brya/variants/kulnex/ramstage.c
new file mode 100644
index 0000000000..a3cd9f3fc6
--- /dev/null
+++ b/src/mainboard/google/brya/variants/kulnex/ramstage.c
@@ -0,0 +1,58 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <baseboard/variants.h>
+#include <chip.h>
+#include <device/device.h>
+#include <device/pci_ids.h>
+#include <device/pci_ops.h>
+#include <ec/google/chromeec/ec.h>
+#include <fw_config.h>
+#include <intelblocks/power_limit.h>
+
+const struct cpu_power_limits limits[] = {
+	/* SKU_ID, TDP (Watts), pl1_min, pl1_max, pl2_min, pl2_max, pl4 */
+	{ PCI_DID_INTEL_RPL_P_ID_5, 15, 15000, 15000,  55000,  55000, 100000 },
+	{ PCI_DID_INTEL_RPL_P_ID_4, 15, 15000, 15000,  55000,  55000, 100000 },
+	{ PCI_DID_INTEL_RPL_P_ID_3, 15, 15000, 15000,  55000,  55000, 100000 },
+};
+
+const struct system_power_limits sys_limits[] = {
+	/* SKU_ID, TDP (Watts), psys_pl2 (Watts) */
+	{ PCI_DID_INTEL_RPL_P_ID_5, 15, 138 },
+	{ PCI_DID_INTEL_RPL_P_ID_4, 15, 138 },
+	{ PCI_DID_INTEL_RPL_P_ID_3, 15, 138 },
+};
+
+/*
+ * Psys_pmax considerations.
+ *
+ * Given the hardware design in kulnex, the serial shunt resistor is 0.005ohm.
+ * The full scale of hardware PSYS signal 1.6v maps to system current 11.25A
+ * instead of real system power. The equation is shown below:
+ * PSYS = 1.6v = (0.005ohm x 11.25A) x 50 (INA213, gain 50V/V) x R501/(R501 + R510)
+ * R501/(R501 + R510) = 0.57 = 20K / (20K + 15K)
+ *
+ * The Psys_pmax is a SW setting which tells IMVP9.1 the mapping b/w system input
+ * current and the actual system power. Since there is no voltage information
+ * from PSYS, different voltage input would map to different Psys_pmax settings:
+ * For Type-C 15V, the Psys_pmax should be 15v x 11.25A = 168.75W
+ * For Type-C 20V, the Psys_pmax should be 20v x 11.25A = 225W
+ * For a barrel jack, the Psys_pmax should be 20v x 11.25A = 225W
+ *
+ * Imagine that there is a type-c 100W (20V/5A) connected to DUT w/ full loading,
+ * and the Psys_pmax setting is 225W. Then IMVP9.1 can calculate the current system
+ * power = 225W * 5A / 11.25A = 100W, which is the actual system power.
+ */
+const struct psys_config psys_config = {
+	.efficiency = 97,
+	.psys_imax_ma = 11250,
+	.bj_volts_mv = 20000
+};
+
+void variant_devtree_update(void)
+{
+	size_t total_entries = ARRAY_SIZE(limits);
+	variant_update_psys_power_limits(limits, sys_limits, total_entries, &psys_config);
+
+	variant_update_power_limits(limits, total_entries);
+}
diff --git a/src/mainboard/google/brya/variants/kulnex/variant.c b/src/mainboard/google/brya/variants/kulnex/variant.c
new file mode 100644
index 0000000000..b7cba968a5
--- /dev/null
+++ b/src/mainboard/google/brya/variants/kulnex/variant.c
@@ -0,0 +1,23 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <baseboard/variants.h>
+#include <chip.h>
+#include <fw_config.h>
+#include <sar.h>
+
+const char *get_wifi_sar_cbfs_filename(void)
+{
+	return "wifi_sar_0.hex";
+}
+
+void variant_update_soc_chip_config(struct soc_intel_alderlake_config *config)
+{
+	config->cnvi_bt_audio_offload = fw_config_probe(FW_CONFIG(AUDIO,
+							NAU88L25B_I2S));
+
+	if (fw_config_probe(FW_CONFIG(MB_USBC, TC_USB3))) {
+		config->tcss_aux_ori = 1;
+		config->typec_aux_bias_pads[0].pad_auxp_dc = GPP_C3;
+		config->typec_aux_bias_pads[0].pad_auxn_dc = GPP_C4;
+	}
+}

From a607d831c083b11541b2376482c42f25b4a098c8 Mon Sep 17 00:00:00 2001
From: Patrick Rudolph <patrick.rudolph@9elements.com>
Date: Sat, 31 Jan 2026 08:30:51 +0100
Subject: [PATCH 3302/3886] drivers/i2c/at24rf08c: Add option for early locking
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Currently the Sandybridge Lenovo devices are spending 25msec waiting
for ME to signal if RAM has been replaced. At the same time the RFID
I2C EEPROM needs to be locked, taking about 26msec.

By moving the locking to romstage the time spent waiting for ME can
be used to do something useful and thus reduce boot time.

TEST=On Lenovo X220 it boots 24msec faster.

Change-Id: Idd1f02a20dab6e422d55e3cf01d7b4a168792272
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91031
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
---
 src/drivers/i2c/at24rf08c/Kconfig              |  4 ++++
 src/drivers/i2c/at24rf08c/Makefile.mk          |  1 +
 src/drivers/i2c/at24rf08c/at24rf08c.c          |  3 +++
 src/drivers/i2c/at24rf08c/lenovo.h             |  2 ++
 src/drivers/i2c/at24rf08c/romstage.c           | 18 ++++++++++++++++++
 src/mainboard/lenovo/l520/Kconfig              |  1 +
 src/mainboard/lenovo/l520/Makefile.mk          |  1 +
 src/mainboard/lenovo/l520/early_init.c         |  9 +++++++++
 src/mainboard/lenovo/s230u/Kconfig             |  1 +
 src/mainboard/lenovo/s230u/early_init.c        |  7 +++++++
 src/mainboard/lenovo/t420/Kconfig              |  1 +
 src/mainboard/lenovo/t420/early_init.c         |  2 ++
 src/mainboard/lenovo/t420s/Kconfig             |  1 +
 src/mainboard/lenovo/t420s/early_init.c        |  2 ++
 src/mainboard/lenovo/t430/Kconfig              |  1 +
 src/mainboard/lenovo/t430/early_init.c         |  2 ++
 src/mainboard/lenovo/t430s/Kconfig             |  1 +
 .../lenovo/t430s/variants/t430s/romstage.c     |  3 +++
 .../lenovo/t430s/variants/t431s/romstage.c     |  7 +++++++
 src/mainboard/lenovo/t520/Kconfig              |  1 +
 src/mainboard/lenovo/t520/early_init.c         |  6 ++++--
 src/mainboard/lenovo/t530/Kconfig              |  1 +
 src/mainboard/lenovo/t530/early_init.c         |  4 +++-
 src/mainboard/lenovo/x131e/Kconfig             |  1 +
 src/mainboard/lenovo/x131e/Makefile.mk         |  1 +
 src/mainboard/lenovo/x131e/early_init.c        |  9 +++++++++
 src/mainboard/lenovo/x1_carbon_gen1/Kconfig    |  1 +
 .../lenovo/x1_carbon_gen1/early_init.c         |  7 +++++++
 src/mainboard/lenovo/x220/Kconfig              |  1 +
 src/mainboard/lenovo/x220/early_init.c         |  7 +++++++
 src/mainboard/lenovo/x230/Kconfig              |  1 +
 src/mainboard/lenovo/x230/Makefile.mk          |  2 ++
 src/mainboard/lenovo/x230/early_init.c         |  9 +++++++++
 33 files changed, 115 insertions(+), 3 deletions(-)
 create mode 100644 src/drivers/i2c/at24rf08c/romstage.c
 create mode 100644 src/mainboard/lenovo/l520/early_init.c
 create mode 100644 src/mainboard/lenovo/x131e/early_init.c
 create mode 100644 src/mainboard/lenovo/x230/early_init.c

diff --git a/src/drivers/i2c/at24rf08c/Kconfig b/src/drivers/i2c/at24rf08c/Kconfig
index a930a46123..219c091a92 100644
--- a/src/drivers/i2c/at24rf08c/Kconfig
+++ b/src/drivers/i2c/at24rf08c/Kconfig
@@ -3,3 +3,7 @@
 config DRIVER_LENOVO_SERIALS
 	bool
 	select SMBIOS_PROVIDED_BY_MOBO
+
+config DRIVER_LENOVO_SERIALS_EARLY_LOCK
+	bool
+	depends on DRIVER_LENOVO_SERIALS
diff --git a/src/drivers/i2c/at24rf08c/Makefile.mk b/src/drivers/i2c/at24rf08c/Makefile.mk
index 4ef2bc595c..223f6903a4 100644
--- a/src/drivers/i2c/at24rf08c/Makefile.mk
+++ b/src/drivers/i2c/at24rf08c/Makefile.mk
@@ -3,3 +3,4 @@
 ramstage-$(CONFIG_DRIVER_LENOVO_SERIALS) += at24rf08c.c
 $(call src-to-obj,ramstage,$(dir)/lenovo_serials.c) : $(obj)/build.h
 ramstage-$(CONFIG_DRIVER_LENOVO_SERIALS) += lenovo_serials.c
+romstage-$(CONFIG_DRIVER_LENOVO_SERIALS_EARLY_LOCK) += romstage.c
diff --git a/src/drivers/i2c/at24rf08c/at24rf08c.c b/src/drivers/i2c/at24rf08c/at24rf08c.c
index 99ea7a47f0..6005f74c4c 100644
--- a/src/drivers/i2c/at24rf08c/at24rf08c.c
+++ b/src/drivers/i2c/at24rf08c/at24rf08c.c
@@ -11,6 +11,9 @@ static void at24rf08c_init(struct device *dev)
 	if (!dev->enabled)
 		return;
 
+	if (CONFIG(DRIVER_LENOVO_SERIALS_EARLY_LOCK))
+		return;
+
 	/* Ensure that EEPROM/RFID chip is not accessible through RFID.
 	   Need to do it only on 5c. */
 	if (dev->path.type != DEVICE_PATH_I2C || dev->path.i2c.device != 0x5c)
diff --git a/src/drivers/i2c/at24rf08c/lenovo.h b/src/drivers/i2c/at24rf08c/lenovo.h
index f94b9ee06d..628308d5dd 100644
--- a/src/drivers/i2c/at24rf08c/lenovo.h
+++ b/src/drivers/i2c/at24rf08c/lenovo.h
@@ -1,3 +1,5 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
 const char *lenovo_mainboard_partnumber(void);
+
+void lenovo_mainboard_eeprom_lock(void);
diff --git a/src/drivers/i2c/at24rf08c/romstage.c b/src/drivers/i2c/at24rf08c/romstage.c
new file mode 100644
index 0000000000..00026b7f3f
--- /dev/null
+++ b/src/drivers/i2c/at24rf08c/romstage.c
@@ -0,0 +1,18 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <device/smbus_host.h>
+#include <console/console.h>
+#include <drivers/i2c/at24rf08c/lenovo.h>
+
+void lenovo_mainboard_eeprom_lock(void)
+{
+	printk(BIOS_DEBUG, "Locking EEPROM RFID\n");
+
+	for (int i = 0; i < 8; i++) {
+		/* After a register write AT24RF08C sometimes stops responding.
+		   Retry several times in case of failure. */
+		for (int j = 0; j < 100; j++)
+			if (smbus_write_byte(0x5c, i, 0x0f) >= 0)
+				break;
+	}
+}
diff --git a/src/mainboard/lenovo/l520/Kconfig b/src/mainboard/lenovo/l520/Kconfig
index 6f7c433828..c3e318e328 100644
--- a/src/mainboard/lenovo/l520/Kconfig
+++ b/src/mainboard/lenovo/l520/Kconfig
@@ -7,6 +7,7 @@ config BOARD_SPECIFIC_OPTIONS
 	select AZALIA_USE_LEGACY_VERB_TABLE
 	select BOARD_ROMSIZE_KB_4096
 	select DRIVER_LENOVO_SERIALS
+	select DRIVER_LENOVO_SERIALS_EARLY_LOCK
 	select EC_LENOVO_H8
 	select EC_LENOVO_PMH7
 	select HAVE_ACPI_RESUME
diff --git a/src/mainboard/lenovo/l520/Makefile.mk b/src/mainboard/lenovo/l520/Makefile.mk
index 7611194339..2afc15156d 100644
--- a/src/mainboard/lenovo/l520/Makefile.mk
+++ b/src/mainboard/lenovo/l520/Makefile.mk
@@ -2,5 +2,6 @@
 
 bootblock-y += gpio.c
 romstage-y += gpio.c
+romstage-y += early_init.c
 
 ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads
diff --git a/src/mainboard/lenovo/l520/early_init.c b/src/mainboard/lenovo/l520/early_init.c
new file mode 100644
index 0000000000..7d36c4b990
--- /dev/null
+++ b/src/mainboard/lenovo/l520/early_init.c
@@ -0,0 +1,9 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <northbridge/intel/sandybridge/sandybridge.h>
+#include <drivers/i2c/at24rf08c/lenovo.h>
+
+void mainboard_early_init(bool s3resume)
+{
+	lenovo_mainboard_eeprom_lock();
+}
diff --git a/src/mainboard/lenovo/s230u/Kconfig b/src/mainboard/lenovo/s230u/Kconfig
index 5fc7570aa9..ca0a639edd 100644
--- a/src/mainboard/lenovo/s230u/Kconfig
+++ b/src/mainboard/lenovo/s230u/Kconfig
@@ -7,6 +7,7 @@ config BOARD_SPECIFIC_OPTIONS
 	select AZALIA_USE_LEGACY_VERB_TABLE
 	select BOARD_ROMSIZE_KB_12288
 	select DRIVER_LENOVO_SERIALS
+	select DRIVER_LENOVO_SERIALS_EARLY_LOCK
 	select EC_ACPI
 	select EC_COMPAL_ENE932
 	select GFX_GMA_PANEL_1_ON_LVDS
diff --git a/src/mainboard/lenovo/s230u/early_init.c b/src/mainboard/lenovo/s230u/early_init.c
index ba52b7e7c9..1f25091620 100644
--- a/src/mainboard/lenovo/s230u/early_init.c
+++ b/src/mainboard/lenovo/s230u/early_init.c
@@ -2,8 +2,10 @@
 
 #include <device/pci_ops.h>
 #include <console/console.h>
+#include <drivers/i2c/at24rf08c/lenovo.h>
 #include <gpio.h>
 #include <northbridge/intel/sandybridge/raminit.h>
+#include <northbridge/intel/sandybridge/sandybridge.h>
 #include <southbridge/intel/bd82x6x/pch.h>
 #include "ec.h"
 
@@ -56,3 +58,8 @@ void mb_get_spd_map(struct spd_info *spdi)
 	spdi->addresses[0] = SPD_MEMORY_DOWN;
 	spdi->spd_index = spd_index;
 }
+
+void mainboard_early_init(bool s3resume)
+{
+	lenovo_mainboard_eeprom_lock();
+}
diff --git a/src/mainboard/lenovo/t420/Kconfig b/src/mainboard/lenovo/t420/Kconfig
index 54d1cda106..b14885eb6a 100644
--- a/src/mainboard/lenovo/t420/Kconfig
+++ b/src/mainboard/lenovo/t420/Kconfig
@@ -22,6 +22,7 @@ config BOARD_SPECIFIC_OPTIONS
 	select INTEL_INT15
 	select DRIVERS_RICOH_RCE822
 	select DRIVER_LENOVO_SERIALS
+	select DRIVER_LENOVO_SERIALS_EARLY_LOCK
 	select MEMORY_MAPPED_TPM
 	select MAINBOARD_HAS_TPM1
 	select MAINBOARD_HAS_LIBGFXINIT
diff --git a/src/mainboard/lenovo/t420/early_init.c b/src/mainboard/lenovo/t420/early_init.c
index b14fea93a6..89e3514316 100644
--- a/src/mainboard/lenovo/t420/early_init.c
+++ b/src/mainboard/lenovo/t420/early_init.c
@@ -1,6 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
 #include <device/pci_ops.h>
+#include <drivers/i2c/at24rf08c/lenovo.h>
 #include <drivers/lenovo/hybrid_graphics/hybrid_graphics.h>
 #include <northbridge/intel/sandybridge/sandybridge.h>
 
@@ -33,4 +34,5 @@ static void hybrid_graphics_init(void)
 void mainboard_early_init(bool s3resume)
 {
 	hybrid_graphics_init();
+	lenovo_mainboard_eeprom_lock();
 }
diff --git a/src/mainboard/lenovo/t420s/Kconfig b/src/mainboard/lenovo/t420s/Kconfig
index bbfc9d0ef5..bf8a9cf0f3 100644
--- a/src/mainboard/lenovo/t420s/Kconfig
+++ b/src/mainboard/lenovo/t420s/Kconfig
@@ -8,6 +8,7 @@ config BOARD_SPECIFIC_OPTIONS
 	select BOARD_ROMSIZE_KB_8192
 	select DRIVERS_LENOVO_HYBRID_GRAPHICS
 	select DRIVER_LENOVO_SERIALS
+	select DRIVER_LENOVO_SERIALS_EARLY_LOCK
 	select EC_LENOVO_H8
 	select EC_LENOVO_PMH7
 	select GFX_GMA_PANEL_1_ON_LVDS
diff --git a/src/mainboard/lenovo/t420s/early_init.c b/src/mainboard/lenovo/t420s/early_init.c
index b14fea93a6..89e3514316 100644
--- a/src/mainboard/lenovo/t420s/early_init.c
+++ b/src/mainboard/lenovo/t420s/early_init.c
@@ -1,6 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
 #include <device/pci_ops.h>
+#include <drivers/i2c/at24rf08c/lenovo.h>
 #include <drivers/lenovo/hybrid_graphics/hybrid_graphics.h>
 #include <northbridge/intel/sandybridge/sandybridge.h>
 
@@ -33,4 +34,5 @@ static void hybrid_graphics_init(void)
 void mainboard_early_init(bool s3resume)
 {
 	hybrid_graphics_init();
+	lenovo_mainboard_eeprom_lock();
 }
diff --git a/src/mainboard/lenovo/t430/Kconfig b/src/mainboard/lenovo/t430/Kconfig
index fe1d5fcd7b..2b6eb17e9c 100644
--- a/src/mainboard/lenovo/t430/Kconfig
+++ b/src/mainboard/lenovo/t430/Kconfig
@@ -8,6 +8,7 @@ config BOARD_SPECIFIC_OPTIONS
 	select BOARD_ROMSIZE_KB_12288
 	select DRIVERS_LENOVO_HYBRID_GRAPHICS
 	select DRIVER_LENOVO_SERIALS
+	select DRIVER_LENOVO_SERIALS_EARLY_LOCK
 	select DRIVERS_RICOH_RCE822
 	select EC_LENOVO_H8
 	select EC_LENOVO_PMH7
diff --git a/src/mainboard/lenovo/t430/early_init.c b/src/mainboard/lenovo/t430/early_init.c
index 8306e0e720..d982660856 100644
--- a/src/mainboard/lenovo/t430/early_init.c
+++ b/src/mainboard/lenovo/t430/early_init.c
@@ -3,6 +3,7 @@
 #include <device/pci_ops.h>
 #include <device/pci_def.h>
 #include <ec/lenovo/pmh7/pmh7.h>
+#include <drivers/i2c/at24rf08c/lenovo.h>
 #include <drivers/lenovo/hybrid_graphics/hybrid_graphics.h>
 #include <northbridge/intel/sandybridge/sandybridge.h>
 
@@ -35,4 +36,5 @@ static void hybrid_graphics_init(void)
 void mainboard_early_init(bool s3resume)
 {
 	hybrid_graphics_init();
+	lenovo_mainboard_eeprom_lock();
 }
diff --git a/src/mainboard/lenovo/t430s/Kconfig b/src/mainboard/lenovo/t430s/Kconfig
index 1e80628384..c7c0ffb347 100644
--- a/src/mainboard/lenovo/t430s/Kconfig
+++ b/src/mainboard/lenovo/t430s/Kconfig
@@ -29,6 +29,7 @@ config BOARD_SPECIFIC_OPTIONS
 	select MAINBOARD_USES_IFD_GBE_REGION
 	select DRIVERS_RICOH_RCE822 if BOARD_LENOVO_T431S
 	select DRIVER_LENOVO_SERIALS
+	select DRIVER_LENOVO_SERIALS_EARLY_LOCK
 	select HAVE_SPD_IN_CBFS if BOARD_LENOVO_T431S
 
 	# Workaround for EC/KBC IRQ1.
diff --git a/src/mainboard/lenovo/t430s/variants/t430s/romstage.c b/src/mainboard/lenovo/t430s/variants/t430s/romstage.c
index 211ec2d345..c658a34a4d 100644
--- a/src/mainboard/lenovo/t430s/variants/t430s/romstage.c
+++ b/src/mainboard/lenovo/t430s/variants/t430s/romstage.c
@@ -3,6 +3,7 @@
 #include <option.h>
 #include <device/pci_ops.h>
 #include <device/pci_def.h>
+#include <drivers/i2c/at24rf08c/lenovo.h>
 #include <northbridge/intel/sandybridge/sandybridge.h>
 #include <ec/lenovo/pmh7/pmh7.h>
 #include <types.h>
@@ -20,4 +21,6 @@ void mainboard_early_init(bool s3resume)
 		// Hide disabled dGPU device
 		pci_and_config32(HOST_BRIDGE, DEVEN, ~DEVEN_PEG10);
 	}
+
+	lenovo_mainboard_eeprom_lock();
 }
diff --git a/src/mainboard/lenovo/t430s/variants/t431s/romstage.c b/src/mainboard/lenovo/t430s/variants/t431s/romstage.c
index 9a78bac813..e1e5029e7c 100644
--- a/src/mainboard/lenovo/t430s/variants/t431s/romstage.c
+++ b/src/mainboard/lenovo/t430s/variants/t431s/romstage.c
@@ -1,6 +1,8 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
 #include <northbridge/intel/sandybridge/raminit.h>
+#include <northbridge/intel/sandybridge/sandybridge.h>
+#include <drivers/i2c/at24rf08c/lenovo.h>
 
 void mb_get_spd_map(struct spd_info *spdi)
 {
@@ -9,3 +11,8 @@ void mb_get_spd_map(struct spd_info *spdi)
 	spdi->addresses[2] = 0x51;
 	spdi->spd_index = 0;
 }
+
+void mainboard_early_init(bool s3resume)
+{
+	lenovo_mainboard_eeprom_lock();
+}
diff --git a/src/mainboard/lenovo/t520/Kconfig b/src/mainboard/lenovo/t520/Kconfig
index ed424ed0a7..cef7750a40 100644
--- a/src/mainboard/lenovo/t520/Kconfig
+++ b/src/mainboard/lenovo/t520/Kconfig
@@ -27,6 +27,7 @@ config BOARD_LENOVO_BASEBOARD_T520
 	select INTEL_GMA_HAVE_VBT if BOARD_LENOVO_T520
 	select MAINBOARD_USES_IFD_GBE_REGION
 	select DRIVER_LENOVO_SERIALS
+	select DRIVER_LENOVO_SERIALS_EARLY_LOCK
 
 	# Workaround for EC/KBC IRQ1.
 	select SERIRQ_CONTINUOUS_MODE
diff --git a/src/mainboard/lenovo/t520/early_init.c b/src/mainboard/lenovo/t520/early_init.c
index ba98ec700f..198d603ff7 100644
--- a/src/mainboard/lenovo/t520/early_init.c
+++ b/src/mainboard/lenovo/t520/early_init.c
@@ -1,12 +1,13 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
 #include <stdint.h>
+#include <device/device.h>
 #include <device/pci_ops.h>
 #include <device/pci_def.h>
+#include <drivers/i2c/at24rf08c/lenovo.h>
+#include <drivers/lenovo/hybrid_graphics/hybrid_graphics.h>
 #include <northbridge/intel/sandybridge/sandybridge.h>
 #include <southbridge/intel/bd82x6x/pch.h>
-#include <drivers/lenovo/hybrid_graphics/hybrid_graphics.h>
-#include <device/device.h>
 
 static void hybrid_graphics_init(void)
 {
@@ -37,4 +38,5 @@ static void hybrid_graphics_init(void)
 void mainboard_early_init(bool s3resume)
 {
 	hybrid_graphics_init();
+	lenovo_mainboard_eeprom_lock();
 }
diff --git a/src/mainboard/lenovo/t530/Kconfig b/src/mainboard/lenovo/t530/Kconfig
index a825e1186b..8830c39301 100644
--- a/src/mainboard/lenovo/t530/Kconfig
+++ b/src/mainboard/lenovo/t530/Kconfig
@@ -6,6 +6,7 @@ config BOARD_LENOVO_BASEBOARD_T530
 	select BOARD_ROMSIZE_KB_12288
 	select DRIVERS_LENOVO_HYBRID_GRAPHICS
 	select DRIVER_LENOVO_SERIALS
+	select DRIVER_LENOVO_SERIALS_EARLY_LOCK
 	select EC_LENOVO_H8
 	select EC_LENOVO_PMH7
 	select GFX_GMA_PANEL_1_ON_LVDS
diff --git a/src/mainboard/lenovo/t530/early_init.c b/src/mainboard/lenovo/t530/early_init.c
index 429ab2857a..b7bc35adbb 100644
--- a/src/mainboard/lenovo/t530/early_init.c
+++ b/src/mainboard/lenovo/t530/early_init.c
@@ -1,11 +1,12 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
 #include <types.h>
+#include <device/device.h>
 #include <device/pci_ops.h>
 #include <device/pci_def.h>
+#include <drivers/i2c/at24rf08c/lenovo.h>
 #include <northbridge/intel/sandybridge/sandybridge.h>
 #include <drivers/lenovo/hybrid_graphics/hybrid_graphics.h>
-#include <device/device.h>
 
 static void hybrid_graphics_init(void)
 {
@@ -36,4 +37,5 @@ static void hybrid_graphics_init(void)
 void mainboard_early_init(bool s3resume)
 {
 	hybrid_graphics_init();
+	lenovo_mainboard_eeprom_lock();
 }
diff --git a/src/mainboard/lenovo/x131e/Kconfig b/src/mainboard/lenovo/x131e/Kconfig
index c59660adf1..3c6d453100 100644
--- a/src/mainboard/lenovo/x131e/Kconfig
+++ b/src/mainboard/lenovo/x131e/Kconfig
@@ -7,6 +7,7 @@ config BOARD_SPECIFIC_OPTIONS
 	select AZALIA_USE_LEGACY_VERB_TABLE
 	select BOARD_ROMSIZE_KB_12288
 	select DRIVER_LENOVO_SERIALS
+	select DRIVER_LENOVO_SERIALS_EARLY_LOCK
 	select EC_LENOVO_H8
 	select GFX_GMA_PANEL_1_ON_LVDS
 	select HAVE_ACPI_RESUME
diff --git a/src/mainboard/lenovo/x131e/Makefile.mk b/src/mainboard/lenovo/x131e/Makefile.mk
index 7611194339..2afc15156d 100644
--- a/src/mainboard/lenovo/x131e/Makefile.mk
+++ b/src/mainboard/lenovo/x131e/Makefile.mk
@@ -2,5 +2,6 @@
 
 bootblock-y += gpio.c
 romstage-y += gpio.c
+romstage-y += early_init.c
 
 ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads
diff --git a/src/mainboard/lenovo/x131e/early_init.c b/src/mainboard/lenovo/x131e/early_init.c
new file mode 100644
index 0000000000..7d36c4b990
--- /dev/null
+++ b/src/mainboard/lenovo/x131e/early_init.c
@@ -0,0 +1,9 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <northbridge/intel/sandybridge/sandybridge.h>
+#include <drivers/i2c/at24rf08c/lenovo.h>
+
+void mainboard_early_init(bool s3resume)
+{
+	lenovo_mainboard_eeprom_lock();
+}
diff --git a/src/mainboard/lenovo/x1_carbon_gen1/Kconfig b/src/mainboard/lenovo/x1_carbon_gen1/Kconfig
index 39daee8b0d..84b8fedaa4 100644
--- a/src/mainboard/lenovo/x1_carbon_gen1/Kconfig
+++ b/src/mainboard/lenovo/x1_carbon_gen1/Kconfig
@@ -8,6 +8,7 @@ config BOARD_SPECIFIC_OPTIONS
 	select BOARD_ROMSIZE_KB_12288
 	select DRIVERS_RICOH_RCE822
 	select DRIVER_LENOVO_SERIALS
+	select DRIVER_LENOVO_SERIALS_EARLY_LOCK
 	select EC_LENOVO_H8
 	select EC_LENOVO_PMH7
 	select GFX_GMA_PANEL_1_ON_LVDS
diff --git a/src/mainboard/lenovo/x1_carbon_gen1/early_init.c b/src/mainboard/lenovo/x1_carbon_gen1/early_init.c
index 7cfc5d9a0e..880635280e 100644
--- a/src/mainboard/lenovo/x1_carbon_gen1/early_init.c
+++ b/src/mainboard/lenovo/x1_carbon_gen1/early_init.c
@@ -1,8 +1,10 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
 #include <console/console.h>
+#include <drivers/i2c/at24rf08c/lenovo.h>
 #include <gpio.h>
 #include <northbridge/intel/sandybridge/raminit.h>
+#include <northbridge/intel/sandybridge/sandybridge.h>
 
 static unsigned int get_spd_index(void)
 {
@@ -40,3 +42,8 @@ void mb_get_spd_map(struct spd_info *spdi)
 	spdi->addresses[2] = SPD_MEMORY_DOWN;
 	spdi->spd_index = get_spd_index();
 }
+
+void mainboard_early_init(bool s3resume)
+{
+	lenovo_mainboard_eeprom_lock();
+}
diff --git a/src/mainboard/lenovo/x220/Kconfig b/src/mainboard/lenovo/x220/Kconfig
index 3b4c6ce0ea..8291965976 100644
--- a/src/mainboard/lenovo/x220/Kconfig
+++ b/src/mainboard/lenovo/x220/Kconfig
@@ -8,6 +8,7 @@ config BOARD_SPECIFIC_OPTIONS
 	select BOARD_ROMSIZE_KB_8192
 	select DRIVERS_RICOH_RCE822
 	select DRIVER_LENOVO_SERIALS
+	select DRIVER_LENOVO_SERIALS_EARLY_LOCK
 	select EC_LENOVO_H8
 	select EC_LENOVO_PMH7
 	select GFX_GMA_PANEL_1_ON_LVDS
diff --git a/src/mainboard/lenovo/x220/early_init.c b/src/mainboard/lenovo/x220/early_init.c
index 826796eddf..492614bdd6 100644
--- a/src/mainboard/lenovo/x220/early_init.c
+++ b/src/mainboard/lenovo/x220/early_init.c
@@ -2,7 +2,14 @@
 
 #include <stdint.h>
 #include <northbridge/intel/sandybridge/raminit.h>
+#include <northbridge/intel/sandybridge/sandybridge.h>
+#include <drivers/i2c/at24rf08c/lenovo.h>
 
 void mainboard_fill_pei_data(struct pei_data *pei_data)
 {
 }
+
+void mainboard_early_init(bool s3resume)
+{
+	lenovo_mainboard_eeprom_lock();
+}
diff --git a/src/mainboard/lenovo/x230/Kconfig b/src/mainboard/lenovo/x230/Kconfig
index 2980c91b3a..9b35477c5b 100644
--- a/src/mainboard/lenovo/x230/Kconfig
+++ b/src/mainboard/lenovo/x230/Kconfig
@@ -24,6 +24,7 @@ config BOARD_SPECIFIC_OPTIONS
 	select INTEL_INT15
 	select DRIVERS_RICOH_RCE822
 	select DRIVER_LENOVO_SERIALS
+	select DRIVER_LENOVO_SERIALS_EARLY_LOCK
 	select MEMORY_MAPPED_TPM
 	select MAINBOARD_HAS_TPM1 if BOARD_LENOVO_X230 || BOARD_LENOVO_X230T || BOARD_LENOVO_X230_EDP
 	select MAINBOARD_HAS_LIBGFXINIT
diff --git a/src/mainboard/lenovo/x230/Makefile.mk b/src/mainboard/lenovo/x230/Makefile.mk
index 5cbdb7dc1b..5a4ec5c21e 100644
--- a/src/mainboard/lenovo/x230/Makefile.mk
+++ b/src/mainboard/lenovo/x230/Makefile.mk
@@ -4,6 +4,8 @@ bootblock-y += variants/$(VARIANT_DIR)/gpio.c
 romstage-y += variants/$(VARIANT_DIR)/gpio.c
 ramstage-y += variants/$(VARIANT_DIR)/hda_verb.c
 
+romstage-y += early_init.c
+
 ifeq ($(CONFIG_BOARD_LENOVO_X230_EDP),y)
 ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += variants/x230_edp/gma-mainboard.ads
 else
diff --git a/src/mainboard/lenovo/x230/early_init.c b/src/mainboard/lenovo/x230/early_init.c
new file mode 100644
index 0000000000..7d36c4b990
--- /dev/null
+++ b/src/mainboard/lenovo/x230/early_init.c
@@ -0,0 +1,9 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <northbridge/intel/sandybridge/sandybridge.h>
+#include <drivers/i2c/at24rf08c/lenovo.h>
+
+void mainboard_early_init(bool s3resume)
+{
+	lenovo_mainboard_eeprom_lock();
+}

From 86b24f199863c56de59d22aa64faa1ead56d6f6c Mon Sep 17 00:00:00 2001
From: David Wu <david_wu@quanta.corp-partner.google.com>
Date: Fri, 6 Feb 2026 13:55:34 +0800
Subject: [PATCH 3303/3886] mb/google/nissa/var/riven: Support x32 memory
 configuration

Use GPP_E5 level to determine whether x32 memory configuration is
supported.

Schematic version: ZDKC-Proto_MB_20260209.pdf

BUG=b:337169542
TEST=Build and boot to OS. Verify functions work.

Change-Id: I51229e99242351d957cbe26a00d9c5440c5d6784
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91115
Reviewed-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/google/brya/Kconfig             |  1 +
 .../google/brya/variants/riven/Makefile.mk    |  1 +
 .../google/brya/variants/riven/gpio.c         |  4 ++++
 .../google/brya/variants/riven/memory.c       | 22 +++++++++++++++++++
 4 files changed, 28 insertions(+)
 create mode 100644 src/mainboard/google/brya/variants/riven/memory.c

diff --git a/src/mainboard/google/brya/Kconfig b/src/mainboard/google/brya/Kconfig
index 56498ecf04..c7fad434f4 100644
--- a/src/mainboard/google/brya/Kconfig
+++ b/src/mainboard/google/brya/Kconfig
@@ -609,6 +609,7 @@ config BOARD_GOOGLE_RIVEN
 	select CHROMEOS_WIFI_SAR if CHROMEOS
 	select DRIVERS_GENERIC_GPIO_KEYS
 	select DRIVERS_INTEL_MIPI_CAMERA
+	select ENFORCE_MEM_CHANNEL_DISABLE
 	select HAVE_WWAN_POWER_SEQUENCE
 	select INTEL_GMA_HAVE_VBT
 	select MAINBOARD_HAS_GOOGLE_STRAUSS_KEYBOARD
diff --git a/src/mainboard/google/brya/variants/riven/Makefile.mk b/src/mainboard/google/brya/variants/riven/Makefile.mk
index 393ccfdf1c..f8d4e8ffdd 100644
--- a/src/mainboard/google/brya/variants/riven/Makefile.mk
+++ b/src/mainboard/google/brya/variants/riven/Makefile.mk
@@ -1,6 +1,7 @@
 # SPDX-License-Identifier: GPL-2.0-only
 bootblock-y += gpio.c
 
+romstage-y += memory.c
 romstage-y += gpio.c
 
 ramstage-$(CONFIG_FW_CONFIG) += fw_config.c
diff --git a/src/mainboard/google/brya/variants/riven/gpio.c b/src/mainboard/google/brya/variants/riven/gpio.c
index 4d0a6fea79..6d0098f775 100644
--- a/src/mainboard/google/brya/variants/riven/gpio.c
+++ b/src/mainboard/google/brya/variants/riven/gpio.c
@@ -15,6 +15,8 @@ static const struct pad_config override_gpio_table[] = {
 	PAD_CFG_GPO(GPP_D6, 1, DEEP),
 	/* D8  : SRCCLKREQ3# ==> NC */
 	PAD_NC(GPP_D8, NONE),
+	/* E5  : NC ==> GPP_E5_STRAP */
+	PAD_CFG_GPI_LOCK(GPP_E5, DN_20K, LOCK_CONFIG),
 	/* F12 : WWAN_RST_L */
 	PAD_CFG_GPO_LOCK(GPP_F12, 1, LOCK_CONFIG),
 	/* H12 : UART0_RTS# ==> NC */
@@ -71,6 +73,8 @@ static const struct pad_config early_gpio_table[] = {
 	PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2),
 	/* H11 : UART0_TXD ==> UART_SOC_TX_DBG_RX */
 	PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2),
+	/* E5  : NC ==> GPP_E5_STRAP */
+	PAD_CFG_GPI(GPP_E5, DN_20K, DEEP),
 };
 
 static const struct pad_config romstage_gpio_table[] = {
diff --git a/src/mainboard/google/brya/variants/riven/memory.c b/src/mainboard/google/brya/variants/riven/memory.c
new file mode 100644
index 0000000000..f5de481ed0
--- /dev/null
+++ b/src/mainboard/google/brya/variants/riven/memory.c
@@ -0,0 +1,22 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <baseboard/gpio.h>
+#include <baseboard/variants.h>
+#include <gpio.h>
+#include <soc/romstage.h>
+
+uint8_t mb_get_channel_disable_mask(void)
+{
+	/*
+	 * GPP_E5 High -> One RAM Chip
+	 * GPP_E5 Low  -> Two RAM Chip
+	 */
+	if (gpio_get(GPP_E5)) {
+		/* Disable all other channels except first two on each controller */
+		printk(BIOS_INFO, "Device only supports one DIMM. Disable all other memory"
+		"channels except first two on each memory controller.\n");
+		return (BIT(2) | BIT(3));
+	}
+
+	return 0;
+}

From 4b131c945e621be6c08b7b3e5ca947f47d15faa6 Mon Sep 17 00:00:00 2001
From: Patrick Rudolph <patrick.rudolph@9elements.com>
Date: Thu, 20 Nov 2025 12:13:05 +0100
Subject: [PATCH 3304/3886] arch/x86: Add support for socketed CPUs

When SMBIOS_TYPE4_SOCKETED_CPU is selected advertise upgrade
support in SMBIOS Type4 table.

Change-Id: I877c72592277690cdfa9ac6805697494c0e87b4e
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91146
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/Kconfig           | 7 +++++++
 src/arch/x86/smbios.c | 2 ++
 2 files changed, 9 insertions(+)

diff --git a/src/Kconfig b/src/Kconfig
index ec7dde2e53..2dad082a08 100644
--- a/src/Kconfig
+++ b/src/Kconfig
@@ -1012,6 +1012,13 @@ config SMBIOS_PROVIDED_BY_MOBO
 	bool
 	default n
 
+config SMBIOS_TYPE4_SOCKETED_CPU
+	bool
+	default n
+	help
+	  If enabled the CPU can be replaced and Type 4 advertises upgrade
+	  support.
+
 if GENERATE_SMBIOS_TABLES
 
 config BIOS_VENDOR
diff --git a/src/arch/x86/smbios.c b/src/arch/x86/smbios.c
index 922340a886..f0fa6a4bf6 100644
--- a/src/arch/x86/smbios.c
+++ b/src/arch/x86/smbios.c
@@ -64,6 +64,8 @@ static int get_socket_type(void)
 		return PROCESSOR_UPGRADE_SOCKET_LGA3647_1;
 	if (CONFIG(CPU_INTEL_SOCKET_OTHER))
 		return PROCESSOR_UPGRADE_OTHER;
+	if (CONFIG(SMBIOS_TYPE4_SOCKETED_CPU))
+		return PROCESSOR_UPGRADE_OTHER;
 
 	return PROCESSOR_UPGRADE_UNKNOWN;
 }

From 31f705f5556d470d5cd582e87f60ab8971eb3fb8 Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Sun, 8 Feb 2026 21:19:14 -0600
Subject: [PATCH 3305/3886] mb/google/brya/var/taeko: Fix SoF speaker topology
 mapping

A Windows driver bug resulted in the max98357a-tdm topology being
identified as the correct one, when in fact the non-TDM version is
correct. Now that the bug has been fixed, correct the speaker
topology. Linux was unaffacted as it uses a different mapping
method.

TEST=build/boot Win11 on RPL Taeko, verify audio functional out
of both left/right speakers and mixer functions properly.

Change-Id: I2f9cc7353540cd8722beada656a8c2a8b1ba8669
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91144
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/google/brya/variants/taeko/overridetree.cb | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/mainboard/google/brya/variants/taeko/overridetree.cb b/src/mainboard/google/brya/variants/taeko/overridetree.cb
index 0abad554cc..dfd88a6c16 100644
--- a/src/mainboard/google/brya/variants/taeko/overridetree.cb
+++ b/src/mainboard/google/brya/variants/taeko/overridetree.cb
@@ -530,7 +530,7 @@ chip soc/intel/alderlake
 				end
 			end
 			chip drivers/sof
-				register "spkr_tplg" = "max98357a_tdm"
+				register "spkr_tplg" = "max98357a"
 				register "jack_tplg" = "rt5682"
 				register "mic_tplg" = "_2ch_pdm0"
 				device generic 0 on end

From 7158a1746c7bf62e57265dedd0170f93824258a0 Mon Sep 17 00:00:00 2001
From: Maximilian Brune <maximilian.brune@9elements.com>
Date: Sat, 29 Nov 2025 04:41:24 +0100
Subject: [PATCH 3306/3886] treewide: Move check-ramstage-overlap variables

Moves the variables to more appropriate locations to save some lines and
make it more readable. For x86 it now also adds the intermediate, but
since x86 doesn't define any regions (e.g. ramstage) to check against,
the intermediate is effectively skipped.

Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: I28371ae3416040243f238271ba45238ceccfcf0b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90816
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 Makefile.mk                | 16 +++++++++-------
 src/arch/arm/Makefile.mk   |  6 ++----
 src/arch/arm64/Makefile.mk | 10 ++--------
 src/arch/ppc64/Makefile.mk |  2 ++
 src/arch/riscv/Makefile.mk |  6 ++----
 src/arch/x86/Makefile.mk   |  4 ++++
 6 files changed, 21 insertions(+), 23 deletions(-)

diff --git a/Makefile.mk b/Makefile.mk
index 14f9b835d7..5fccb4a52d 100644
--- a/Makefile.mk
+++ b/Makefile.mk
@@ -1447,11 +1447,6 @@ bootsplash$(BOOTSPLASH_SUFFIX)-file := $(call strip_quotes,$(CONFIG_BOOTSPLASH_F
 bootsplash$(BOOTSPLASH_SUFFIX)-type := bootsplash
 endif
 
-# Ensure that no payload segment overlaps with memory regions used by ramstage
-# (not for x86 since it can relocate itself in that case)
-ifneq ($(CONFIG_ARCH_X86),y)
-check-ramstage-overlap-regions := ramstage
-check-ramstage-overlap-files :=
 ifneq ($(CONFIG_PAYLOAD_NONE),y)
 check-ramstage-overlap-files += $(CONFIG_CBFS_PREFIX)/payload
 endif
@@ -1464,6 +1459,15 @@ ramstage-symbol-addr-cmd = $(OBJDUMP_ramstage) -t $(objcbfs)/ramstage.elf | \
 	sed -n '/ $(1)$$/s/^\([0-9a-fA-F]*\) .*/0x\1/p' | \
 	uniq
 
+# Ensures that no segments from files in check-ramstage-overlap-files overlap memory regions
+# used by ramstage. By default the segments of the payload are checked against the ramstage
+# segments, but there may be other executables in RAM (e.g. BL31, OPENSBI). So Architecture
+# Makefiles may add relevant executables to `check-ramstage-overlap-files`. Architecture
+# Makefiles need to initialize `check-ramstage-overlap-regions` to use this check.
+# For example:
+# Common regions to add are `ramstage`, `stack` or `postram_cbfs_cache`. Which means that the
+# ramstage segments `ramstage`, `stack`, `postram_cbfs_cache` are checked to make sure they
+# don't overlap with the segments of check-ramstage-overlap-files (e.g. payload).
 $(call add_intermediate, check-ramstage-overlaps)
 	programs=$$($(foreach file,$(check-ramstage-overlap-files), \
 		$(call cbfs-get-segments-cmd,$(file)) ; )) ; \
@@ -1489,5 +1493,3 @@ $(call add_intermediate, check-ramstage-overlaps)
 	    done ; \
 	    pstart= ; pend= ; \
 	done
-
-endif
diff --git a/src/arch/arm/Makefile.mk b/src/arch/arm/Makefile.mk
index ef87dcf14f..89cca2b793 100644
--- a/src/arch/arm/Makefile.mk
+++ b/src/arch/arm/Makefile.mk
@@ -4,10 +4,6 @@
 # ARM specific options
 ###############################################################################
 
-ifeq ($(CONFIG_ARCH_RAMSTAGE_ARM),y)
-check-ramstage-overlap-regions += postram_cbfs_cache stack ttb
-endif
-
 ifeq ($(CONFIG_ARCH_ARM),y)
 subdirs-y += libgcc/
 subdirs-y += armv4/ armv7/
@@ -99,6 +95,8 @@ endif # CONFIG_ARCH_ROMSTAGE_ARM
 
 ifeq ($(CONFIG_ARCH_RAMSTAGE_ARM),y)
 
+check-ramstage-overlap-regions += postram_cbfs_cache stack ttb ramstage
+
 ramstage-y += stages.c
 ramstage-y += div0.c
 ramstage-y += eabi_compat.c
diff --git a/src/arch/arm64/Makefile.mk b/src/arch/arm64/Makefile.mk
index 279d31fb47..efd628fee7 100644
--- a/src/arch/arm64/Makefile.mk
+++ b/src/arch/arm64/Makefile.mk
@@ -6,14 +6,6 @@
 
 subdirs-y += armv8/
 
-################################################################################
-# ARM specific options
-################################################################################
-
-ifeq ($(CONFIG_ARCH_RAMSTAGE_ARM64),y)
-check-ramstage-overlap-regions += postram_cbfs_cache stack ttb
-endif
-
 ################################################################################
 # bootblock
 ################################################################################
@@ -106,6 +98,8 @@ endif # CONFIG_ARCH_ROMSTAGE_ARM64
 
 ifeq ($(CONFIG_ARCH_RAMSTAGE_ARM64),y)
 
+check-ramstage-overlap-regions += postram_cbfs_cache stack ttb ramstage
+
 ramstage-y += div0.c
 ramstage-y += eabi_compat.c
 ramstage-y += boot.c
diff --git a/src/arch/ppc64/Makefile.mk b/src/arch/ppc64/Makefile.mk
index 4a118b638a..9a4a2b01e7 100644
--- a/src/arch/ppc64/Makefile.mk
+++ b/src/arch/ppc64/Makefile.mk
@@ -65,6 +65,8 @@ endif
 ################################################################################
 ifeq ($(CONFIG_ARCH_RAMSTAGE_PPC64),y)
 
+check-ramstage-overlap-regions += ramstage
+
 ramstage-y += stages.c
 ramstage-y += arch_timer.c
 ramstage-y += boot.c
diff --git a/src/arch/riscv/Makefile.mk b/src/arch/riscv/Makefile.mk
index 95e439d5a9..cf393ba700 100644
--- a/src/arch/riscv/Makefile.mk
+++ b/src/arch/riscv/Makefile.mk
@@ -5,10 +5,6 @@
 ################################################################################
 ifeq ($(CONFIG_ARCH_RISCV),y)
 
-ifeq ($(CONFIG_ARCH_RAMSTAGE_RISCV),y)
-check-ramstage-overlap-regions += stack
-endif
-
 riscv_flags = -I$(src)/arch/riscv/
 
 ifeq ($(CONFIG_ARCH_RISCV_RV64),y)
@@ -134,6 +130,8 @@ endif #CONFIG_ARCH_ROMSTAGE_RISCV
 ################################################################################
 ifeq ($(CONFIG_ARCH_RAMSTAGE_RISCV),y)
 
+check-ramstage-overlap-regions += stack ramstage
+
 ramstage-y =
 ramstage-y += ramstage.S
 ramstage-y += tables.c
diff --git a/src/arch/x86/Makefile.mk b/src/arch/x86/Makefile.mk
index 0aaa962cfa..785d35c0aa 100644
--- a/src/arch/x86/Makefile.mk
+++ b/src/arch/x86/Makefile.mk
@@ -224,6 +224,10 @@ $(CONFIG_CBFS_PREFIX)/postcar-compression := none
 
 ifeq ($(CONFIG_ARCH_RAMSTAGE_X86_32)$(CONFIG_ARCH_RAMSTAGE_X86_64),y)
 
+# not adding a check-ramstage-overlap-regions here because x86 ramstage can automatically
+# relocate itself to a free area (its build as a rmodule). Therefore no ramstage segments can
+# overlap with other executables in RAM.
+
 ramstage-y += acpi.c
 ramstage-$(CONFIG_HAVE_ACPI_RESUME) += acpi_s3.c
 ramstage-$(CONFIG_ACPI_BERT) += acpi_bert_storage.c

From 2e8545c44106fe7bae4552da5a5635878b1f362f Mon Sep 17 00:00:00 2001
From: Subrata Banik <subratabanik@google.com>
Date: Tue, 10 Feb 2026 15:52:11 +0530
Subject: [PATCH 3307/3886] soc/intel/common: Refactor poweroff() logic for
 early poweroff support

The existing logic prioritized the check for ENV_ROMSTAGE_OR_BEFORE
over the HAVE_EARLY_POWEROFF_SUPPORT configuration. This meant that
platforms with early poweroff support might still fall through to the
incorrect path depending on the boot phase.

Refactor the logic to:
1. Prioritize CONFIG(HAVE_EARLY_POWEROFF_SUPPORT) as the primary
   mechanism for poweroff.
2. If early support is not available, check the environment stage:
   - Perform standard pmc_control_poweroff() if after romstage.
   - Halt with an emergency message if attempted too early in the
     boot process without platform support.

This structure ensures that platform-specific early poweroff routines
are always preferred when configured.

TEST=Able to verify the AC host event is not getting cleared after
power-off.

Change-Id: Ieec8bcae5e1002d264db59cafe9236aaef6576e0
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91149
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Pranava Y N <pranavayn@google.com>
Reviewed-by: Avi Uday <aviuday@google.com>
---
 src/soc/intel/common/block/pmc/pmclib.c | 14 ++++++++------
 1 file changed, 8 insertions(+), 6 deletions(-)

diff --git a/src/soc/intel/common/block/pmc/pmclib.c b/src/soc/intel/common/block/pmc/pmclib.c
index 64b9bb997c..dc36d30bdb 100644
--- a/src/soc/intel/common/block/pmc/pmclib.c
+++ b/src/soc/intel/common/block/pmc/pmclib.c
@@ -632,14 +632,16 @@ static void pmc_control_poweroff(void)
 
 void poweroff(void)
 {
-	if (!ENV_ROMSTAGE_OR_BEFORE) {
-		pmc_control_poweroff();
-	} else if (CONFIG(HAVE_EARLY_POWEROFF_SUPPORT)) {
+	if (CONFIG(HAVE_EARLY_POWEROFF_SUPPORT)) {
 		platform_do_early_poweroff();
 	} else {
-		printk(BIOS_EMERG, "This platform cannot be powered off until the silicon"
-			" initialization is complete, hanging!\n");
-		halt();
+		if (!ENV_ROMSTAGE_OR_BEFORE) {
+			pmc_control_poweroff();
+		} else {
+			printk(BIOS_EMERG, "This platform cannot be powered off until the silicon"
+				 " initialization is complete, hanging!\n");
+			halt();
+		}
 	}
 }
 

From 6b61e4ce687f96a19183d8e2bafc7fd1a09ceb84 Mon Sep 17 00:00:00 2001
From: Patrick Rudolph <patrick.rudolph@amd.com>
Date: Thu, 8 Jan 2026 16:46:56 +0100
Subject: [PATCH 3308/3886] soc/amd/glinda: Fill in fch_rt_device_enable_map

Currently FSP modifies the AOAC bits of the FCH devices and
thus needs the current status passed via fch_rt_device_enable_map.
By default fch_rt_device_enable_map is 0, effectly disabling all FCH
devices, including the debug UART. This causes a hang at boot.

Fill fch_rt_device_enable_map in SoC code.

TEST=Can boot on amd/birman_plus again.

Change-Id: I00ef35ea6fe11939c4154940fef8cb902955fe27
Signed-off-by: Patrick Rudolph <patrick.rudolph@amd.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91160
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
---
 src/soc/amd/glinda/fsp_m_params.c | 27 +++++++++++++++++++++++++++
 1 file changed, 27 insertions(+)

diff --git a/src/soc/amd/glinda/fsp_m_params.c b/src/soc/amd/glinda/fsp_m_params.c
index 32a708fd70..ff5f04c7f2 100644
--- a/src/soc/amd/glinda/fsp_m_params.c
+++ b/src/soc/amd/glinda/fsp_m_params.c
@@ -3,6 +3,7 @@
 /* TODO: Update for Glinda */
 /* TODO: See what can be moved to common */
 
+#include <amdblocks/aoac.h>
 #include <amdblocks/apob_cache.h>
 #include <amdblocks/ioapic.h>
 #include <amdblocks/memmap.h>
@@ -13,6 +14,7 @@
 #include <fsp/api.h>
 #include <soc/platform_descriptors.h>
 #include <soc/pci_devs.h>
+#include <soc/aoac_defs.h>
 #include <static.h>
 #include <string.h>
 #include <types.h>
@@ -176,6 +178,31 @@ void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version)
 		mcfg->usb_phy_ptr = 0;
 	}
 
+	/* Sync AOAC devices */
+	int fch_aoac_devs[] = {
+		FCH_AOAC_DEV_I2C0,
+		FCH_AOAC_DEV_I2C1,
+		FCH_AOAC_DEV_I2C2,
+		FCH_AOAC_DEV_I2C3,
+		FCH_AOAC_DEV_UART0,
+		FCH_AOAC_DEV_UART1,
+		FCH_AOAC_DEV_UART2,
+		FCH_AOAC_DEV_UART3,
+		FCH_AOAC_DEV_UART4,
+		FCH_AOAC_DEV_I3C0,
+		FCH_AOAC_DEV_I3C1,
+		FCH_AOAC_DEV_I3C2,
+		FCH_AOAC_DEV_I3C3,
+	};
+
+	for (int i = 0; i < ARRAY_SIZE(fch_aoac_devs); i++) {
+		const int mask = BIT(fch_aoac_devs[i]);
+		if (is_aoac_device_enabled(fch_aoac_devs[i]))
+			mcfg->fch_rt_device_enable_map |= mask;
+		else
+			mcfg->fch_rt_device_enable_map &= ~mask;
+	}
+
 	fsp_fill_pcie_ddi_descriptors(mcfg);
 	fsp_assign_ioapic_upds(mcfg);
 	mb_pre_fspm(mcfg);

From fcc53b1075de6367820e33661a808c5fe742ef6e Mon Sep 17 00:00:00 2001
From: Patrick Rudolph <patrick.rudolph@amd.com>
Date: Tue, 3 Feb 2026 14:28:43 +0100
Subject: [PATCH 3309/3886] mb/amd/birman_plus: Set TDP value

The default CPU for birman_plus is STX1FP8 with a TDP of 28W.

Set SystemConfig to 2 to use the default IRM configuration
for 28W TDP CPUs and tweak slow PPT and fast PPT.

Change-Id: I555326228ad6a1dfa2f18c7fbd5a69b9b95b0f04
Signed-off-by: Patrick Rudolph <patrick.rudolph@amd.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91162
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
---
 src/mainboard/amd/birman_plus/devicetree_glinda.cb | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/src/mainboard/amd/birman_plus/devicetree_glinda.cb b/src/mainboard/amd/birman_plus/devicetree_glinda.cb
index 9ec3c8fd71..2027d5b6c0 100644
--- a/src/mainboard/amd/birman_plus/devicetree_glinda.cb
+++ b/src/mainboard/amd/birman_plus/devicetree_glinda.cb
@@ -21,6 +21,11 @@ chip soc/amd/glinda
 		.flash_ch_en = 0,
 	}"
 
+	register "system_configuration" = "2"
+
+	register "slow_ppt_limit_mW" = "45000"
+	register "fast_ppt_limit_mW" = "45000"
+
 	register "i2c_scl_reset" = "GPIO_I2C0_SCL | GPIO_I2C1_SCL |
 					GPIO_I2C2_SCL | GPIO_I2C3_SCL"
 	register "i2c[2].early_init" = "1"

From e9dc589eab03a20251fc1c5737853828afc9af21 Mon Sep 17 00:00:00 2001
From: Patrick Rudolph <patrick.rudolph@amd.com>
Date: Wed, 4 Feb 2026 10:26:45 +0100
Subject: [PATCH 3310/3886] soc/amd/glinda: Only allow warm reset on Faegan

Select SOC_AMD_SUPPORTS_WARM_RESET on faegon only.
Glinda doesn't currently support warm resets.

Signed-off-by: Patrick Rudolph <patrick.rudolph@amd.com>
Change-Id: Ic7a011827d16685bb3f2a13a576b7832a4929119
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91163
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
---
 src/soc/amd/glinda/Kconfig | 2 +-
 src/soc/amd/glinda/fch.c   | 2 ++
 2 files changed, 3 insertions(+), 1 deletion(-)

diff --git a/src/soc/amd/glinda/Kconfig b/src/soc/amd/glinda/Kconfig
index 3be4725763..70a1fc6331 100644
--- a/src/soc/amd/glinda/Kconfig
+++ b/src/soc/amd/glinda/Kconfig
@@ -92,7 +92,6 @@ config SOC_AMD_GLINDA_BASE
 	select X86_AMD_FIXED_MTRRS
 	select X86_INIT_NEED_1_SIPI
 	select HAVE_X86_64_SUPPORT
-	select SOC_AMD_SUPPORTS_WARM_RESET
 	help
 	  AMD Glinda support
 
@@ -105,6 +104,7 @@ config SOC_AMD_GLINDA
 config SOC_AMD_FAEGAN
 	bool
 	select SOC_AMD_GLINDA_BASE
+	select SOC_AMD_SUPPORTS_WARM_RESET
 	help
 	  AMD Faegan support
 
diff --git a/src/soc/amd/glinda/fch.c b/src/soc/amd/glinda/fch.c
index 849e466442..1e0b08ced4 100644
--- a/src/soc/amd/glinda/fch.c
+++ b/src/soc/amd/glinda/fch.c
@@ -156,6 +156,8 @@ static void cgpll_clock_gate_init(void)
 
 void fch_init(void *chip_info)
 {
+	if (!CONFIG(SOC_AMD_SUPPORTS_WARM_RESET))
+		set_resets_to_cold();
 	i2c_soc_init();
 	fch_init_acpi_ports();
 

From 7493b41f37f7ba301212d18bdadd7e09df18d7c4 Mon Sep 17 00:00:00 2001
From: Patrick Rudolph <patrick.rudolph@9elements.com>
Date: Wed, 11 Feb 2026 13:33:24 +0100
Subject: [PATCH 3311/3886] mb/amd/birman_plus: Disable PCIe feature
 programming

Before the PCIe features can be programmed FSP-S must set non
public bits in the EnumInitPhaseAfterPciEnumeration callback.
Violating this rule causes system instabilities and reboot loops,
depending on the selected features and hardware plugged into slots.

Since FSP-S can handle all types of PCIe features disable all of
them in coreboot and let FSP set the bits at the right time.

TEST=Can boot on AMD/glinda with ASPM L1SS enabled without seeing
     system crashed.

Change-Id: Ib4c4597c91d6612018e4f55e1a989a676aff842d
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91164
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/amd/birman_plus/Kconfig | 4 ----
 1 file changed, 4 deletions(-)

diff --git a/src/mainboard/amd/birman_plus/Kconfig b/src/mainboard/amd/birman_plus/Kconfig
index a5291a495c..21b8607b48 100644
--- a/src/mainboard/amd/birman_plus/Kconfig
+++ b/src/mainboard/amd/birman_plus/Kconfig
@@ -8,10 +8,6 @@ config BOARD_AMD_BIRMANPLUS_COMMON
 	select DRIVERS_PCIE_RTD3_DEVICE
 	select DRIVERS_I2C_GENERIC
 	select MAINBOARD_HAS_CHROMEOS
-	select PCIEXP_ASPM
-	select PCIEXP_CLK_PM
-	select PCIEXP_COMMON_CLOCK
-	select PCIEXP_L1_SUB_STATE
 	select SOC_AMD_COMMON_BLOCK_ESPI_RETAIN_PORT80_EN if !SOC_AMD_COMMON_BLOCK_SIMNOW_BUILD
 	select SOC_AMD_COMMON_BLOCK_SIMNOW_SUPPORTED
 	select SPI_FLASH_EXIT_4_BYTE_ADDR_MODE

From 332b8a9a1cd42b60151488ec226d9d9c8aaa56d1 Mon Sep 17 00:00:00 2001
From: David Wu <david_wu@quanta.corp-partner.google.com>
Date: Tue, 3 Feb 2026 12:51:34 +0800
Subject: [PATCH 3312/3886] mb/google/brask/var/kulnex: Switch memory to DDR5

Kulnex uses DDR5 SODIMM. Configure the board to support DDR5.

BUG=b:480035819
TEST=build pass

Change-Id: Idc2205318bc5c9db8a4a699764de247e6fa25e66
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91069
Reviewed-by: Derek Huang <derekhuang@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 .../google/brya/variants/kulnex/Makefile.mk   |  1 +
 .../google/brya/variants/kulnex/memory.c      | 45 +++++++++++++++++++
 2 files changed, 46 insertions(+)
 create mode 100644 src/mainboard/google/brya/variants/kulnex/memory.c

diff --git a/src/mainboard/google/brya/variants/kulnex/Makefile.mk b/src/mainboard/google/brya/variants/kulnex/Makefile.mk
index e31aaa1707..2b274c69e2 100644
--- a/src/mainboard/google/brya/variants/kulnex/Makefile.mk
+++ b/src/mainboard/google/brya/variants/kulnex/Makefile.mk
@@ -1,6 +1,7 @@
 # SPDX-License-Identifier: GPL-2.0-only
 bootblock-y += gpio.c
 
+romstage-y += memory.c
 romstage-y += gpio.c
 
 ramstage-y += gpio.c
diff --git a/src/mainboard/google/brya/variants/kulnex/memory.c b/src/mainboard/google/brya/variants/kulnex/memory.c
new file mode 100644
index 0000000000..742ce7fe3a
--- /dev/null
+++ b/src/mainboard/google/brya/variants/kulnex/memory.c
@@ -0,0 +1,45 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <baseboard/gpio.h>
+#include <baseboard/variants.h>
+#include <gpio.h>
+#include <soc/romstage.h>
+
+static const struct mb_cfg ddr5_mem_config = {
+	.type = MEM_TYPE_DDR5,
+
+	.rcomp = {
+		/* Baseboard uses only 100ohm Rcomp resistors */
+		.resistor = 100,
+
+		/* Baseboard Rcomp target values */
+		.targets = {50, 20, 25, 25, 25},
+	},
+
+	.LpDdrDqDqsReTraining = 1,
+
+	.ect = 1, /* Early Command Training */
+
+	.UserBd = BOARD_TYPE_MOBILE,
+
+	.ddr_config = {
+		.dq_pins_interleaved = false,
+	},
+};
+
+const struct mb_cfg *__weak variant_memory_params(void)
+{
+	return &ddr5_mem_config;
+}
+
+bool __weak variant_is_half_populated(void)
+{
+	return false;
+}
+
+void __weak variant_get_spd_info(struct mem_spd *spd_info)
+{
+	spd_info->topo = MEM_TOPO_DIMM_MODULE;
+	spd_info->smbus[0].addr_dimm[0] = 0x50;
+	spd_info->smbus[1].addr_dimm[0] = 0x52;
+}

From 3b2525eab6c778755e6c21d8c8c7379311e56926 Mon Sep 17 00:00:00 2001
From: Kenneth Chan <kenneth.chan@quanta.corp-partner.google.com>
Date: Tue, 3 Feb 2026 14:18:58 +0800
Subject: [PATCH 3313/3886] mb/google/brask/var/kulnex: Enable PCIe WiFi 7
 support

Add configuration for the PCIe Root Port connected to the WiFi 7 module.

BUG=b:480035819
TEST=Build successfully for kulnex. Verify WiFi 7 functionality on
 moxie.

Change-Id: I46dfe87afe7356cbe48cf15dd87a58b55a528094
Signed-off-by: Kenneth Chan <kenneth.chan@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91071
Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 .../brya/variants/kulnex/overridetree.cb      | 32 ++++++++++++++++++-
 1 file changed, 31 insertions(+), 1 deletion(-)

diff --git a/src/mainboard/google/brya/variants/kulnex/overridetree.cb b/src/mainboard/google/brya/variants/kulnex/overridetree.cb
index 9733305b69..71268f88ac 100644
--- a/src/mainboard/google/brya/variants/kulnex/overridetree.cb
+++ b/src/mainboard/google/brya/variants/kulnex/overridetree.cb
@@ -13,6 +13,10 @@ fw_config
 		option TC_USB4	0
 		option TC_USB3	1
 	end
+	field WIFI_TYPE 10
+		option WIFI_PCIE	0
+		option WIFI_CNVI	1
+	end
 	field USB_HUB 32
 		option HUB_ABSENT	0
 		option HUB_PRESENT	1
@@ -176,7 +180,9 @@ chip soc/intel/alderlake
 		device ref cnvi_wifi on
 			chip drivers/wifi/generic
 				register "wake" = "GPE0_PME_B0"
-				device generic 0 on end
+				device generic 0 on
+					probe WIFI_TYPE WIFI_CNVI
+				end
 			end
 		end
 		device ref i2c0 on
@@ -205,6 +211,30 @@ chip soc/intel/alderlake
 				end
 			end
 		end
+		device ref pcie_rp5 on
+			probe WIFI_TYPE WIFI_PCIE
+			# Enable wlan PCIe 5 using clk 2
+			register "pch_pcie_rp[PCH_RP(5)]" = "{
+				.clk_src = 2,
+				.clk_req = 2,
+				.flags = PCIE_RP_LTR | PCIE_RP_AER,
+			}"
+			chip drivers/wifi/generic
+				register "wake" = "GPE0_DW1_03"
+				register "add_acpi_dma_property" = "true"
+				device pci 00.0 on
+					probe WIFI_TYPE WIFI_PCIE
+				end
+			end
+			chip soc/intel/common/block/pcie/rtd3
+				register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B11)"
+				register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_H20)"
+				register "srcclk_pin" = "2"
+				device generic 0 on
+					probe WIFI_TYPE WIFI_PCIE
+				end
+			end
+		end     #PCIE5 WLAN card
 		device ref pcie_rp7 on
 			chip drivers/net
 				register "wake" = "GPE0_DW0_07"

From 4ccca8f8c4cdd051d2f3d7383a6faa652cf18232 Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Wed, 11 Feb 2026 20:06:47 +0000
Subject: [PATCH 3314/3886] mb/starlabs/adl: Fix generic graphics information

Some of the entries were indexed wrong, so fix them.

Change-Id: I76890a3c3b2b30d8123a81352346776a656e8f7f
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91167
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/starlabs/adl/variants/hz/devicetree.cb | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/mainboard/starlabs/adl/variants/hz/devicetree.cb b/src/mainboard/starlabs/adl/variants/hz/devicetree.cb
index 229ce37de4..5a540d75bd 100644
--- a/src/mainboard/starlabs/adl/variants/hz/devicetree.cb
+++ b/src/mainboard/starlabs/adl/variants/hz/devicetree.cb
@@ -40,8 +40,8 @@ chip soc/intel/alderlake
 				register "device[2].name"	= ""DD02""
 				# [TCP1] Type-C
 				register "device[3].name"	= ""DD03""
-				register "device[2].use_pld"	= "true"
-				register "device[2].pld"	= "ACPI_PLD_TYPE_C(LEFT, CENTER, ACPI_PLD_GROUP(0, 1))"
+				register "device[3].use_pld"	= "true"
+				register "device[3].pld"	= "ACPI_PLD_TYPE_C(LEFT, CENTER, ACPI_PLD_GROUP(0, 1))"
 				# [TCP2] N/A
 				register "device[4].name"	= ""DD04""
 				# [TCP3] N/A

From e0121eb463e7ca3065634300198d9d5234f281e8 Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Mon, 9 Feb 2026 20:07:27 +0000
Subject: [PATCH 3315/3886] mb/starlabs/adl: Enable TCP0 Display Output

Enable TCP0 alongside TCP1.

Test=build and boot adl/horizon, check there is video output over
USB-C.

Change-Id: I9db17fd3ed3e1eb0f6ea94320b595ce0d51f33e2
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91168
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 .../starlabs/adl/variants/hz/data.vbt         | Bin 9216 -> 9216 bytes
 .../adl/variants/hz/data_native_res.vbt       | Bin 9216 -> 9216 bytes
 .../starlabs/adl/variants/hz/devicetree.cb    |  15 +++++++++++++--
 src/mainboard/starlabs/adl/variants/hz/gpio.c |   2 +-
 4 files changed, 14 insertions(+), 3 deletions(-)

diff --git a/src/mainboard/starlabs/adl/variants/hz/data.vbt b/src/mainboard/starlabs/adl/variants/hz/data.vbt
index a2adefc8b2589fa70efa3937551bf02da294487d..8c22ab4f40c953db62bbe3744709b4430e547cff 100644
GIT binary patch
delta 70
zcmZqhXz-XI#cal4FgcM?c%y+hqcRHv2ZI9;D=@GCX$LT^0OT_O`3yil1A_ukt@Pwp
P#wMm~37a{YzAFL%l$8uA

delta 54
zcmZqhXz-XI#k_>UU~(a&@J0i1MqvjA4h97V2O#EPU|?tfVui_xY}%7s8Jn0G7&db<
HeOCkkL30Z}

diff --git a/src/mainboard/starlabs/adl/variants/hz/data_native_res.vbt b/src/mainboard/starlabs/adl/variants/hz/data_native_res.vbt
index 7e4f64ad7fd3cd3eafeb099eab9154b2b97e3e42..a101af780b8ecc78fff9335c3dc0cab7239b2250 100644
GIT binary patch
delta 70
zcmZqhXz-XI#azT-FgcM?c%y+hqcRHv2ZI9;D=@GCX$LT^0OT_O`3yil1A_ukt@Pwp
P#wMm~37a{YzAFL%qgf1P

delta 54
zcmZqhXz-XI#r%N5U~(a&@J0i1MqvjA4h97V2O#EPU|?tfVui_xY}%7s8Jn0G7&db<
HeOCkkOm_=<

diff --git a/src/mainboard/starlabs/adl/variants/hz/devicetree.cb b/src/mainboard/starlabs/adl/variants/hz/devicetree.cb
index 5a540d75bd..c06ad29b9a 100644
--- a/src/mainboard/starlabs/adl/variants/hz/devicetree.cb
+++ b/src/mainboard/starlabs/adl/variants/hz/devicetree.cb
@@ -38,6 +38,8 @@ chip soc/intel/alderlake
 				register "device[1].name"	= ""DD01""
 				# [TCP0] Type-C
 				register "device[2].name"	= ""DD02""
+				register "device[2].use_pld"	= "true"
+				register "device[2].pld"	= "ACPI_PLD_TYPE_C(LEFT, CENTER, ACPI_PLD_GROUP(0, 0))"
 				# [TCP1] Type-C
 				register "device[3].name"	= ""DD03""
 				register "device[3].use_pld"	= "true"
@@ -59,6 +61,7 @@ chip soc/intel/alderlake
 		device ref xhci		on
 			# Left Rear USB 2.0 Type-C		3289 mil
 			register "usb2_ports[0]"		= "USB2_PORT_SHORT(OC_SKIP)"
+			register "usb3_ports[1]"		= "USB3_PORT_DEFAULT(OC_SKIP)"
 
 			# Left Front USB 3.0 Type C
 			register "usb2_ports[1]"		= "USB2_PORT_SHORT(OC_SKIP)"
@@ -78,10 +81,18 @@ chip soc/intel/alderlake
 				device ref xhci_root_hub on
 					chip drivers/usb/acpi
 						register "desc"			= ""Left Back USB Type-C""
-						register "type"			= "UPC_TYPE_C_USB2_ONLY"
-						register "group"		= "ACPI_PLD_GROUP(0, 0)"
+						register "type"			= "UPC_TYPE_C_USB2_SS_SWITCH"
+						register "use_custom_pld"	= "true"
+						register "custom_pld"		= "ACPI_PLD_TYPE_C(LEFT, CENTER, ACPI_PLD_GROUP(0, 0))"
 						device ref usb2_port1 on end
 					end
+					chip drivers/usb/acpi
+						register "desc"			= ""Left Back USB Type-C""
+						register "type"			= "UPC_TYPE_C_USB2_SS_SWITCH"
+						register "use_custom_pld"	= "true"
+						register "custom_pld"		= "ACPI_PLD_TYPE_C(LEFT, CENTER, ACPI_PLD_GROUP(0, 0))"
+						device ref usb3_port2 on end
+					end
 
 					chip drivers/usb/acpi
 						register "desc"			= ""Left Front USB Type-C""
diff --git a/src/mainboard/starlabs/adl/variants/hz/gpio.c b/src/mainboard/starlabs/adl/variants/hz/gpio.c
index a72cc6e157..e214a14cec 100644
--- a/src/mainboard/starlabs/adl/variants/hz/gpio.c
+++ b/src/mainboard/starlabs/adl/variants/hz/gpio.c
@@ -59,6 +59,7 @@ const struct pad_config gpio_table[] = {
 	PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1),				/* HDMI Hot Plug */
 	PAD_CFG_NF(GPP_H15, NONE, DEEP, NF1),				/* HDMI Clock */
 	PAD_CFG_NF(GPP_H17, NONE, DEEP, NF1),				/* HDMI Data */
+	PAD_CFG_NF(GPP_A19, NONE, DEEP, NF1),				/* TCP0 Hot Plug */
 	PAD_CFG_NF(GPP_A20, NONE, DEEP, NF1),				/* TCP1 Hot Plug */
 
 	/* High-Definition Audio */
@@ -113,7 +114,6 @@ const struct pad_config gpio_table[] = {
 	PAD_NC(GPP_A15, NONE),
 	PAD_NC(GPP_A16, NONE),
 	PAD_NC(GPP_A17, NONE),
-	PAD_NC(GPP_A19, NONE),
 	PAD_NC(GPP_A21, NONE),
 	PAD_NC(GPP_A22, NONE),
 	PAD_NC(GPP_A23, NONE),

From 02867c27978056f4920bc8222d5ef5312f2613d2 Mon Sep 17 00:00:00 2001
From: Karthikeyan Ramasubramanian <kramasub@google.com>
Date: Tue, 10 Feb 2026 14:52:42 -0700
Subject: [PATCH 3316/3886] payloads/libpayload/liblz4: Export magic number
 definitions

Move LZ4 magic number definitions to public header file so that it can
be used in the payload. Also rename LEGACY_MAGICNUMBER to
LZ4_LEGACY_MAGICNUMBER for clarity when using from the payload.

BUG=None
TEST=Build Hylia BIOS image and boot to OS/UI.

Change-Id: Ief180105ec3fa7abf1013d0c5408aa96edde681b
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91152
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
---
 payloads/libpayload/include/lz4.h        | 3 +++
 payloads/libpayload/liblz4/lz4_wrapper.c | 5 +----
 2 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/payloads/libpayload/include/lz4.h b/payloads/libpayload/include/lz4.h
index 249afb3a41..3879f47ab9 100644
--- a/payloads/libpayload/include/lz4.h
+++ b/payloads/libpayload/include/lz4.h
@@ -34,6 +34,9 @@
 
 #include <stddef.h>
 
+#define LZ4F_MAGICNUMBER 0x184D2204
+#define LZ4_LEGACY_MAGICNUMBER 0x184C2102
+
 /* Decompresses an LZ4F image (multiple LZ4 blocks with frame header) from src
  * to dst, ensuring that it doesn't read more than srcn bytes and doesn't write
  * more than dstn. Buffer sizes must stay below 2GB. Can decompress files loaded
diff --git a/payloads/libpayload/liblz4/lz4_wrapper.c b/payloads/libpayload/liblz4/lz4_wrapper.c
index 160d5dcb74..f80ccc7178 100644
--- a/payloads/libpayload/liblz4/lz4_wrapper.c
+++ b/payloads/libpayload/liblz4/lz4_wrapper.c
@@ -73,9 +73,6 @@ typedef uint64_t U64;
 /* Unaltered (just removed unrelated code) from github.com/Cyan4973/lz4/dev. */
 #include "lz4.c.inc"	/* #include for inlining, do not link! */
 
-#define LZ4F_MAGICNUMBER 0x184D2204
-#define LEGACY_MAGICNUMBER 0x184C2102
-
 struct lz4_frame_header {
 	uint32_t magic;
 	union {
@@ -198,7 +195,7 @@ size_t ulz4ln(const void *src, size_t srcn, void *dst, size_t dstn)
 	void *out = dst;
 	size_t out_size = 0;
 
-	if (le32toh(*((const uint32_t *)in)) != LEGACY_MAGICNUMBER)
+	if (le32toh(*((const uint32_t *)in)) != LZ4_LEGACY_MAGICNUMBER)
 		return 0;
 
 	in += sizeof(uint32_t);

From a6015c180b13912a6daa4102057befc2cb7d1a5c Mon Sep 17 00:00:00 2001
From: Maximilian Brune <maximilian.brune@9elements.com>
Date: Mon, 9 Feb 2026 20:00:23 +0100
Subject: [PATCH 3317/3886] util/mec152x/Makefile.mk: Include
 commonlib/bsd/compiler.h

cbfstool/flashmap/kv_pair.h uses the `__printf` macro. So we need to
include the header file defining `__printf` in the compilation.

Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: I4ce98f59b94d64ef4e0694e0c83f7b83f6feec7c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91141
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
---
 util/mec152x/Makefile.mk | 1 +
 1 file changed, 1 insertion(+)

diff --git a/util/mec152x/Makefile.mk b/util/mec152x/Makefile.mk
index 067fdb097f..ccbdda0cf9 100644
--- a/util/mec152x/Makefile.mk
+++ b/util/mec152x/Makefile.mk
@@ -8,6 +8,7 @@ MEC152XCFLAGS := -Wno-array-bounds -Wextra -O3 -Wshadow $(WERROR)
 MEC152XCFLAGS += -I $(top)/util/cbfstool/flashmap/
 MEC152XCFLAGS += -I $(top)/util/mec152x
 MEC152XCFLAGS += -I $(top)/src/commonlib/bsd/include
+MEC152XCFLAGS += -include $(top)/src/commonlib/bsd/include/commonlib/bsd/compiler.h
 
 additional-dirs += $(objutil)/mec152x
 

From f4fc769099e0c347f784588b638c7f198a6def05 Mon Sep 17 00:00:00 2001
From: Patrick Rudolph <patrick.rudolph@amd.com>
Date: Thu, 8 Jan 2026 12:48:17 +0100
Subject: [PATCH 3318/3886] mb/amd/birman_plus: Fix graphics init

The Birman+ evaluation board allows to test different display
connectors (HDMI, Displayport, ...) by plugin in different "NOVA"
cards. Every NOVA card has a small EEPROM identifying the connector.
Currently the graphics init isn't working with a DisplayPort
monitor connected to the DP NOVA card.

Fix the auto-detection code of the NOVA card. The code was swapping
the endianness of the connector_type which isn't necessary according
to the spec, but it looks like some cards where programmed with
different endianness.

To support both types, little and big endian, accept both for now.

TEST=Can boot into EDK2 with graphics enabled.

Change-Id: I54754967dd4887363043808116495cb36c636baf
Signed-off-by: Patrick Rudolph <patrick.rudolph@amd.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91161
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
---
 .../amd/birman_plus/port_descriptors_glinda.c | 22 ++++++++++---------
 1 file changed, 12 insertions(+), 10 deletions(-)

diff --git a/src/mainboard/amd/birman_plus/port_descriptors_glinda.c b/src/mainboard/amd/birman_plus/port_descriptors_glinda.c
index b699ca8e16..a30179f420 100644
--- a/src/mainboard/amd/birman_plus/port_descriptors_glinda.c
+++ b/src/mainboard/amd/birman_plus/port_descriptors_glinda.c
@@ -144,30 +144,32 @@ static uint8_t get_ddi1_type(void)
 	const uint8_t eeprom_i2c_bus = 2;
 	const uint8_t eeprom_i2c_address = 0x55;
 	const uint16_t eeprom_connector_type_offset = 2;
-	uint8_t eeprom_connector_type_data[2];
-	uint16_t connector_type;
+	uint16_t connector_type = 0;
 
 	if (i2c_2ba_read_bytes(eeprom_i2c_bus, eeprom_i2c_address,
-			       eeprom_connector_type_offset, eeprom_connector_type_data,
-			       sizeof(eeprom_connector_type_data))) {
+			       eeprom_connector_type_offset, (void *)&connector_type,
+			       sizeof(connector_type))) {
 		printk(BIOS_NOTICE,
 		       "Display connector type couldn't be determined. Disabling DDI1.\n");
 		return DDI_UNUSED_TYPE;
 	}
 
-	connector_type = eeprom_connector_type_data[1] | eeprom_connector_type_data[0] << 8;
-
+	/* On some NOVA cards it's LE, on some it's BE... */
 	switch (connector_type) {
-	case 0x0c:
+	case 0x0c00:
+	case 0x000c:
 		printk(BIOS_DEBUG, "Configuring DDI1 as HDMI.\n");
 		return DDI_HDMI;
-	case 0x13:
+	case 0x1300:
+	case 0x0013:
 		printk(BIOS_DEBUG, "Configuring DDI1 as DP.\n");
 		return DDI_DP;
-	case 0x14:
+	case 0x1400:
+	case 0x0014:
 		printk(BIOS_DEBUG, "Configuring DDI1 as eDP.\n");
 		return DDI_EDP;
-	case 0x17:
+	case 0x1700:
+	case 0x0017:
 		printk(BIOS_DEBUG, "Configuring DDI1 as USB-C.\n");
 		return DDI_DP_W_TYPEC;
 	default:

From 74df39f65ec4c36320564389d914d2be5ed40836 Mon Sep 17 00:00:00 2001
From: Swathi Tamilselvan <tswathi@qualcomm.corp-partner.google.com>
Date: Fri, 6 Feb 2026 18:59:27 +0530
Subject: [PATCH 3319/3886] soc/qualcomm/x1p42100: Add support to invoke LPASS
 Init
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Add support to invoke LPASS Initialization. Implement
voting-based enablement for the core HM GDSC and AON CC PLL
instead of direct control.

BUG=b:480195888
Test=1. Create an image.serial.bin and ensure it boots on X1P42100.
2. Verified LP0 BCM vote using serial logs.
Serial Log:
[DEBUG]  BCM: Found address 0x00050048 for resource LP0
[INFO ]  BCM: Successfully voted for LP0 (addr=0x00050048, val=0x60004001)
3. Verified if the clocks are enabled by taking clock dump. Clock
enablement is verified by dumping the 31st bit of the corresponding
clock’s CBCR register. A value of 0 in bit 31 indicates that the clock
is ON. The register details are part of HRD-X1P42100-S1 document.
https://docs.qualcomm.com/bundle/resource/topics/HRD-X1P42100-S1/
4. Able to boot X1P42100 w/o any adsp failed to bootup error.

Change-Id: I51ca2b7a5da8b35d0d8dd803000f1db28441c136
Signed-off-by: Swathi Tamilselvan <tswathi@qualcomm.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91128
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
---
 src/soc/qualcomm/x1p42100/include/soc/clock.h | 10 +++++++---
 src/soc/qualcomm/x1p42100/include/soc/lpass.h |  6 +++++-
 src/soc/qualcomm/x1p42100/lpass.c             | 17 +++++++++--------
 src/soc/qualcomm/x1p42100/soc.c               |  2 ++
 4 files changed, 23 insertions(+), 12 deletions(-)

diff --git a/src/soc/qualcomm/x1p42100/include/soc/clock.h b/src/soc/qualcomm/x1p42100/include/soc/clock.h
index 95258eaa85..c126baac62 100644
--- a/src/soc/qualcomm/x1p42100/include/soc/clock.h
+++ b/src/soc/qualcomm/x1p42100/include/soc/clock.h
@@ -66,6 +66,7 @@ enum clk_ctl_lpass_aon_cc_pll_user_ctl_x1p42100 {
 	AON_CC_PLL_PLLOUT_ODD_SHFT_X1P42100 = 2,
 	AON_CC_PLL_POST_DIV_EVEN_SHFT_X1P42100 = 10,
 	AON_CC_PLL_POST_DIV_ODD_SHFT_X1P42100 = 14,
+	AON_CC_PLL_ENABLE_VOTE_RUN = 25
 };
 
 enum clk_pll_src {
@@ -280,16 +281,19 @@ struct x1p42100_lpass_aon_cc {
 	u32 va_mem0_cbcr;
 	u8 _res1[0x2c];
 	u32 lpass_audio_hm_gdscr;
-	u8 _res2[0x8F78];
+	u8 _res2[0x2f6c];
+	u32 lpass_hm_collapse_vote_for_q6;
+	u8 _res3[0x6008];
 	u32 va_2x_cbcr;
-	u8 _res3[0x4];
+	u8 _res4[0x4];
 	u32 va_cbcr;
-	u8 _res4[0xffc];
+	u8 _res5[0xffc];
 	u32 tx_mclk_cbcr;
 };
 
 check_member(x1p42100_lpass_aon_cc, va_mem0_cbcr, 0x9060);
 check_member(x1p42100_lpass_aon_cc, lpass_audio_hm_gdscr, 0x9090);
+check_member(x1p42100_lpass_aon_cc, lpass_hm_collapse_vote_for_q6, 0xc000);
 check_member(x1p42100_lpass_aon_cc, va_2x_cbcr, 0x1200C);
 check_member(x1p42100_lpass_aon_cc, va_cbcr, 0x12014);
 check_member(x1p42100_lpass_aon_cc, tx_mclk_cbcr, 0x13014);
diff --git a/src/soc/qualcomm/x1p42100/include/soc/lpass.h b/src/soc/qualcomm/x1p42100/include/soc/lpass.h
index 79439e4ba7..0b5a8bd4dd 100644
--- a/src/soc/qualcomm/x1p42100/include/soc/lpass.h
+++ b/src/soc/qualcomm/x1p42100/include/soc/lpass.h
@@ -8,7 +8,8 @@
 /* LPASS AON CC PLL Settings */
 #define HAL_CLK_LPASS_AON_CC_PLL_L_VALUE	0x00000020
 #define HAL_CLK_LPASS_AON_CC_PLL_ALPHA_VALUE	0x00000000
-#define HAL_CLK_LPASS_AON_CC_PLL_CAL_L_VALUE	0x00000044
+#define HAL_CLK_LPASS_AON_CC_PLL_RING_CAL_L_VALUE	(0x44 << 16)
+#define HAL_CLK_LPASS_AON_CC_PLL_PROC_CAL_L_VALUE	(0x44 << 24)
 #define HAL_CLK_LPASS_AON_CC_PLL_CONFIG_CTL	0x20485699
 #define HAL_CLK_LPASS_AON_CC_PLL_CONFIG_CTL_U	0x00182261
 #define HAL_CLK_LPASS_AON_CC_PLL_CONFIG_CTL_U1	0x82AA299C
@@ -23,5 +24,8 @@
 #define HW_CTL					BIT(1)
 #define GDSC_ENABLE_BIT				0
 
+#define LPASS_CORE_HM_VOTE_POWER_ON		0x0
+#define GDSC_PWR_ON				BIT(31)
+
 #define BCM_LP0_VOTE_VALUE			0x60004001
 #endif /* _SOC_QUALCOMM_X1P42100_LPASS_H_ */
diff --git a/src/soc/qualcomm/x1p42100/lpass.c b/src/soc/qualcomm/x1p42100/lpass.c
index 437a888cb0..fb96616dbd 100644
--- a/src/soc/qualcomm/x1p42100/lpass.c
+++ b/src/soc/qualcomm/x1p42100/lpass.c
@@ -13,13 +13,14 @@ static enum cb_err lpass_aon_cc_pll_enable(void)
 
 	pll_cfg.reg_mode = &lpass_aon_cc_pll->pll_mode;
 	pll_cfg.reg_l = &lpass_aon_cc_pll->pll_l_val;
-	pll_cfg.l_val = HAL_CLK_LPASS_AON_CC_PLL_L_VALUE;
+	pll_cfg.l_val = HAL_CLK_LPASS_AON_CC_PLL_L_VALUE |
+		HAL_CLK_LPASS_AON_CC_PLL_PROC_CAL_L_VALUE |
+			HAL_CLK_LPASS_AON_CC_PLL_RING_CAL_L_VALUE;
 
 	pll_cfg.reg_alpha = &lpass_aon_cc_pll->pll_alpha_val;
 	pll_cfg.alpha_val = HAL_CLK_LPASS_AON_CC_PLL_ALPHA_VALUE;
 
 	pll_cfg.reg_cal_l = &lpass_aon_cc_pll->pll_l_val;
-	pll_cfg.cal_l_val = HAL_CLK_LPASS_AON_CC_PLL_CAL_L_VALUE;
 
 	pll_cfg.reg_config_ctl = &lpass_aon_cc_pll->pll_config_ctl;
 	pll_cfg.config_ctl_val = HAL_CLK_LPASS_AON_CC_PLL_CONFIG_CTL;
@@ -45,10 +46,8 @@ static enum cb_err lpass_aon_cc_pll_enable(void)
 	write32(&lpass_aon_cc_pll->pll_test_ctl_u1, HAL_CLK_LPASS_AON_CC_PLL_TEST_CTL_U1);
 	write32(&lpass_aon_cc_pll->pll_test_ctl_u2, HAL_CLK_LPASS_AON_CC_PLL_TEST_CTL_U2);
 
-	if (lucidole_pll_enable(&pll_cfg) != CB_SUCCESS) {
-		printk(BIOS_ERR, "LPASS: AON CC PLL enable failed\n");
-		return CB_ERR;
-	}
+	setbits32(&lpass_aon_cc_pll->pll_user_ctl, BIT(AON_CC_PLL_ENABLE_VOTE_RUN));
+	setbits32(&lpass_aon_cc_pll->pll_mode, BIT(PLL_RESET_SHFT));
 
 	setbits32(&lpass_aon_cc_pll->pll_user_ctl, (BIT(AON_CC_PLL_PLLOUT_EVEN_SHFT_X1P42100) |
 				BIT(AON_CC_PLL_PLLOUT_ODD_SHFT_X1P42100)));
@@ -66,8 +65,10 @@ static enum cb_err lpass_setup_core_infrastructure(void)
 
 	setbits32(&lpass_core_gdsc->lpass_top_cc_lpass_core_sway_ahb_ls_cbcr, HW_CTL);
 
-	if (enable_and_poll_gdsc_status(&lpass_core_gdsc->core_hm_gdscr) != CB_SUCCESS) {
-		printk(BIOS_ERR, "LPASS: Failed to enable Core HM GDSC\n");
+	write32(&lpass_aon_cc->lpass_hm_collapse_vote_for_q6, LPASS_CORE_HM_VOTE_POWER_ON);
+
+	if (!wait_us(150000, !(read32(&lpass_core_gdsc->core_hm_gdscr) & GDSC_PWR_ON))) {
+		printk(BIOS_ERR, "LPASS: Core HM GDSC PWR_ON timeout after vote\n");
 		return CB_ERR;
 	}
 
diff --git a/src/soc/qualcomm/x1p42100/soc.c b/src/soc/qualcomm/x1p42100/soc.c
index 78fa43a175..df4e803627 100644
--- a/src/soc/qualcomm/x1p42100/soc.c
+++ b/src/soc/qualcomm/x1p42100/soc.c
@@ -5,6 +5,7 @@
 #include <soc/mmu_common.h>
 #include <soc/symbols_common.h>
 #include <soc/pcie.h>
+#include <soc/clock.h>
 #include <soc/cpucp.h>
 #include <program_loading.h>
 
@@ -89,6 +90,7 @@ static void soc_init(struct device *dev)
 {
 	cpucp_fw_load_reset();
 	qtee_fw_config_load();
+	lpass_init();
 }
 
 static struct device_operations soc_ops = {

From c293bab76ee4c0ade6b0ca039f76f8841fe38abe Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Wed, 11 Feb 2026 11:06:44 -0600
Subject: [PATCH 3320/3886] soc/intel/apollolake: Add CONFIG_SMM_TSEG_SIZE

Add SMM_TSEG_SIZE for Apollo Lake and Gemini Lake, set to same value as
used by other Intel SoCs. This is required since commit c078552e712c
("soc/intel: Replace sa_get_tseg_size() with CONFIG_SMM_TSEG_SIZE")
removed the use of sa_get_tseg_size() without verifying that all SoCs
actually set the Kconfig being used to replace it.

TEST=build google/reef and verify CONFIG_SMM_TSEG_SIZE set in .config.

Change-Id: Iaac2eaddc6ef3ccfa299b8b10103d26d08881370
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91166
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-by: Guvendik, Bora <bora.guvendik@intel.com>
---
 src/soc/intel/apollolake/Kconfig | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig
index 2f0ea9953d..d48a010342 100644
--- a/src/soc/intel/apollolake/Kconfig
+++ b/src/soc/intel/apollolake/Kconfig
@@ -327,6 +327,10 @@ config SMM_RESERVED_SIZE
 	hex
 	default 0x100000
 
+config SMM_TSEG_SIZE
+	hex
+	default 0x800000
+
 config CHIPSET_DEVICETREE
 	string
 	default "soc/intel/apollolake/chipset_glk.cb" if SOC_INTEL_GEMINILAKE

From 292fcec3312814d37c9b61a9da508d1305a4d2f1 Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Sat, 31 Jan 2026 18:24:20 -0600
Subject: [PATCH 3321/3886] util/superiotool/nuvoton: Drop global CR 0x2d for
 NCT6791D

Per the NCT6791D datasheet, global configuration register 0x2d is
reserved, so exclude it from the dump like other reserved registers
(0x12, 0x15-0x19, 0x23, etc).

This was discovered when comparing datasheets for the -91D and -96D;
0x2d is a strapped register for the -96D, but reserved for the -91D.

Change-Id: I7d0372c4592f5532480acc5220ee11d9800d2277
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91097
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
---
 util/superiotool/nuvoton.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/util/superiotool/nuvoton.c b/util/superiotool/nuvoton.c
index 5f249e7463..90c7a93f7d 100644
--- a/util/superiotool/nuvoton.c
+++ b/util/superiotool/nuvoton.c
@@ -688,8 +688,8 @@ static const struct superio_registers reg_table[] = {
 		{EOT}}},
 	{0xc803, "NCT6791D", {
 		{NOLDN, NULL,
-			{0x07,0x10,0x11,0x13,0x14,0x1a,0x1b,0x1c,0x1d,0x20,0x21,0x22,0x24,0x25,0x26,0x27,0x28,0x2a,0x2b,0x2c,0x2d,0x2f,EOT},
-			{0x00,0xff,0xff,0x00,0x00,0x30,0x70,0x10,0x00,0xc8,0x03,0xff,0x04,0x00,MISC,0x00,0x00,0xc0,0x00,0x01,0x00,MISC,EOT}},
+			{0x07,0x10,0x11,0x13,0x14,0x1a,0x1b,0x1c,0x1d,0x20,0x21,0x22,0x24,0x25,0x26,0x27,0x28,0x2a,0x2b,0x2c,0x2f,EOT},
+			{0x00,0xff,0xff,0x00,0x00,0x30,0x70,0x10,0x00,0xc8,0x03,0xff,0x04,0x00,MISC,0x00,0x00,0xc0,0x00,0x01,MISC,EOT}},
 		{0x01, "Parallel Port",
 			{0x30,0x60,0x61,0x70,0x74,0xf0,EOT},
 			{0x01,0x03,0x78,0x07,0x04,0x3f,EOT}},

From 458b15b3f6c2a0e0883c544a10e0e4f5dac83560 Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Sat, 31 Jan 2026 18:50:48 -0600
Subject: [PATCH 3322/3886] util/superiotool/nuvoton: Add HWM banked register
 dump for NCT6791D/NCT6796D
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Add extra_dump (-e) support for NCT6791D and NCT6796D to dump all HWM
banked registers: global, SYSFAN, CPUFAN, AUXFAN0, PECI calibration,
PECI setup, AUXFAN1–3 (+AUXFAN4 for -96D). Uses index port at base+5
and data port at base+6, per datasheets.

TEST=build/dump SIO registers for out-of-tree board Erying SRMJ4 with
NCT6796D.

Change-Id: I689374826bc1e38efaa3d68013610a8fa2052b1f
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91098
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 util/superiotool/nuvoton.c | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/util/superiotool/nuvoton.c b/util/superiotool/nuvoton.c
index 90c7a93f7d..8f9a029aea 100644
--- a/util/superiotool/nuvoton.c
+++ b/util/superiotool/nuvoton.c
@@ -1098,6 +1098,16 @@ extra:
 			for (i = 0; i < 10; i++)
 				dump_data(iobase + 5, i);
 			break;
+		case 0xc800:	/* NCT6791D */
+			printf("HWM banked registers:\n");
+			for (i = 0; i <= 0xa; i++)
+				dump_data(iobase + 5, i);
+			break;
+		case 0xd420:	/* NCT6796D */
+			printf("HWM banked registers:\n");
+			for (i = 0; i <= 0xb; i++)
+				dump_data(iobase + 5, i);
+			break;
 		case 0xd590: /* NCT6687D-W */
 			dump_nct6687d_gpios(port);
 			/* One can use the APCI/BIOS register set, although the

From 855eb93547d7ab5b4d2df340ff9ba305c4b24c68 Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Wed, 4 Feb 2026 10:37:10 -0600
Subject: [PATCH 3323/3886] sio/nuvoton/nct6791d: Fix fallthrough linter error

Apply the recommended change to correctly notate a switch fallthrough.

Change-Id: If5f26f47dde641e6a5b687c4ab669efad438d8c4
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91099
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
---
 src/superio/nuvoton/nct6791d/superio.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/src/superio/nuvoton/nct6791d/superio.c b/src/superio/nuvoton/nct6791d/superio.c
index 91a39084a9..343dd13475 100644
--- a/src/superio/nuvoton/nct6791d/superio.c
+++ b/src/superio/nuvoton/nct6791d/superio.c
@@ -30,7 +30,8 @@ static const char *nct6791d_acpi_hid(const struct device *dev)
 		return NULL;
 
 	switch (dev->path.pnp.device & 0xff) {
-	case NCT6791D_SP1: /* fallthrough */
+	case NCT6791D_SP1:
+		__fallthrough;
 	case NCT6791D_SP2:
 		return ACPI_HID_COM;
 	case NCT6791D_KBC:

From 5cb2fa1dc0bd89d091816c9e7d18a1029ee5842c Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Wed, 4 Feb 2026 10:23:37 -0600
Subject: [PATCH 3324/3886] sio/nuvoton: Add NCT6796D as a copy of NCT6791D

The -96D is an updated version of the -91D and has additional LDNs.
This initial commit is a clone of the -91D with strings changed;
additional functionality will be added in subsequent commits.

TEST=tested with out-of-tree board Erying SRMJ4

Change-Id: I8f67c999f4076aaca52c93060a6a461dd9bcc62f
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91100
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/superio/nuvoton/Makefile.mk          |   1 +
 src/superio/nuvoton/nct6796d/Kconfig     |   5 ++
 src/superio/nuvoton/nct6796d/Makefile.mk |   5 ++
 src/superio/nuvoton/nct6796d/nct6796d.h  |  44 +++++++++
 src/superio/nuvoton/nct6796d/superio.c   | 108 +++++++++++++++++++++++
 5 files changed, 163 insertions(+)
 create mode 100644 src/superio/nuvoton/nct6796d/Kconfig
 create mode 100644 src/superio/nuvoton/nct6796d/Makefile.mk
 create mode 100644 src/superio/nuvoton/nct6796d/nct6796d.h
 create mode 100644 src/superio/nuvoton/nct6796d/superio.c

diff --git a/src/superio/nuvoton/Makefile.mk b/src/superio/nuvoton/Makefile.mk
index 3c8df4f8f1..f56f5f4734 100644
--- a/src/superio/nuvoton/Makefile.mk
+++ b/src/superio/nuvoton/Makefile.mk
@@ -13,4 +13,5 @@ subdirs-$(CONFIG_SUPERIO_NUVOTON_NCT6687D) += nct6687d
 subdirs-$(CONFIG_SUPERIO_NUVOTON_NCT6776) += nct6776
 subdirs-$(CONFIG_SUPERIO_NUVOTON_NCT6779D) += nct6779d
 subdirs-$(CONFIG_SUPERIO_NUVOTON_NCT6791D) += nct6791d
+subdirs-$(CONFIG_SUPERIO_NUVOTON_NCT6796D) += nct6796d
 subdirs-$(CONFIG_SUPERIO_NUVOTON_NPCD378) += npcd378
diff --git a/src/superio/nuvoton/nct6796d/Kconfig b/src/superio/nuvoton/nct6796d/Kconfig
new file mode 100644
index 0000000000..49689e2709
--- /dev/null
+++ b/src/superio/nuvoton/nct6796d/Kconfig
@@ -0,0 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
+config SUPERIO_NUVOTON_NCT6796D
+	bool
+	select SUPERIO_NUVOTON_COMMON_PRE_RAM
diff --git a/src/superio/nuvoton/nct6796d/Makefile.mk b/src/superio/nuvoton/nct6796d/Makefile.mk
new file mode 100644
index 0000000000..9700af5de5
--- /dev/null
+++ b/src/superio/nuvoton/nct6796d/Makefile.mk
@@ -0,0 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
+ramstage-$(CONFIG_SUPERIO_NUVOTON_NCT6796D) += superio.c
+ramstage-$(CONFIG_SUPERIO_NUVOTON_NCT6796D) += ../../common/ssdt.c
+ramstage-$(CONFIG_SUPERIO_NUVOTON_NCT6796D) += ../../common/generic.c
diff --git a/src/superio/nuvoton/nct6796d/nct6796d.h b/src/superio/nuvoton/nct6796d/nct6796d.h
new file mode 100644
index 0000000000..53aeab4e2d
--- /dev/null
+++ b/src/superio/nuvoton/nct6796d/nct6796d.h
@@ -0,0 +1,44 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#ifndef SUPERIO_NUVOTON_NCT6796D_H
+#define SUPERIO_NUVOTON_NCT6796D_H
+
+/* Logical Device Numbers (LDN). */
+#define NCT6796D_PP			0x01 /* Parallel port */
+#define NCT6796D_SP1			0x02 /* UART A */
+#define NCT6796D_SP2			0x03 /* UART B, IR */
+#define NCT6796D_KBC			0x05 /* Keyboard Controller */
+#define NCT6796D_CIR			0x06 /* Consumer IR */
+#define NCT6796D_GPIO678		0x07 /* GPIO 6, 7 & 8 */
+#define NCT6796D_WDT1_WDTMEM_GPIO01	0x08 /* WDT1, WDT_MEM, GPIO 0 & 1 */
+#define NCT6796D_GPIO2345		0x09 /* GPIO 2, 3, 4 & 5 */
+#define NCT6796D_ACPI			0x0A /* ACPI */
+#define NCT6796D_HWM_FPLED		0x0B /* HW Monitor, Front Panel LED */
+#define NCT6796D_BCLK_WDT2_WDTMEM	0x0D /* BCLK, WDT2, WDT_MEM */
+#define NCT6796D_CIRWUP			0x0E /* CIR Wake-Up */
+#define NCT6796D_GPIO_PP_OD		0x0F /* GPIO Push-Pull/Open-Drain */
+#define NCT6796D_PORT80			0x14 /* Port 80 UART */
+#define NCT6796D_DS			0x16 /* Deep Sleep */
+
+/* Virtual LDNs */
+#define NCT6796D_WDT1		((0 << 8) | NCT6796D_WDT1_WDTMEM_GPIO01)
+#define NCT6796D_WDTMEM		((4 << 8) | NCT6796D_WDT1_WDTMEM_GPIO01)
+#define NCT6796D_GPIOBASE	((3 << 8) | NCT6796D_WDT1_WDTMEM_GPIO01)
+#define NCT6796D_GPIO0		((1 << 8) | NCT6796D_WDT1_WDTMEM_GPIO01)
+#define NCT6796D_GPIO1		((7 << 8) | NCT6796D_WDT1_WDTMEM_GPIO01)
+#define NCT6796D_GPIO2		((0 << 8) | NCT6796D_GPIO2345)
+#define NCT6796D_GPIO3		((1 << 8) | NCT6796D_GPIO2345)
+#define NCT6796D_GPIO4		((2 << 8) | NCT6796D_GPIO2345)
+#define NCT6796D_GPIO5		((3 << 8) | NCT6796D_GPIO2345)
+#define NCT6796D_GPIO6		((0 << 8) | NCT6796D_GPIO678)
+#define NCT6796D_GPIO7		((1 << 8) | NCT6796D_GPIO678)
+#define NCT6796D_GPIO8		((2 << 8) | NCT6796D_GPIO678)
+#define NCT6796D_DS5		((0 << 8) | NCT6796D_DS)
+#define NCT6796D_DS3		((1 << 8) | NCT6796D_DS)
+#define NCT6796D_PCHDSW		((3 << 8) | NCT6796D_DS)
+#define NCT6796D_DSWWOPT	((4 << 8) | NCT6796D_DS)
+#define NCT6796D_DS3OPT		((5 << 8) | NCT6796D_DS)
+#define NCT6796D_DSDSS		((6 << 8) | NCT6796D_DS)
+#define NCT6796D_DSPU		((7 << 8) | NCT6796D_DS)
+
+#endif /* SUPERIO_NUVOTON_NCT6796D_H */
diff --git a/src/superio/nuvoton/nct6796d/superio.c b/src/superio/nuvoton/nct6796d/superio.c
new file mode 100644
index 0000000000..65d7465461
--- /dev/null
+++ b/src/superio/nuvoton/nct6796d/superio.c
@@ -0,0 +1,108 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <device/device.h>
+#include <device/pnp.h>
+#include <pc80/keyboard.h>
+#include <superio/conf_mode.h>
+#include <superio/common/ssdt.h>
+#include <acpi/acpi.h>
+#include "nct6796d.h"
+
+static void nct6796d_init(struct device *dev)
+{
+	if (!dev->enabled)
+		return;
+
+	switch (dev->path.pnp.device) {
+	case NCT6796D_KBC:
+		pc_keyboard_init(NO_AUX_DEVICE);
+		break;
+	}
+}
+
+#if CONFIG(HAVE_ACPI_TABLES)
+/* Provide ACPI HIDs for generic Super I/O SSDT */
+static const char *nct6796d_acpi_hid(const struct device *dev)
+{
+	if ((dev->path.type != DEVICE_PATH_PNP) ||
+		(dev->path.pnp.port == 0) ||
+		((dev->path.pnp.device & 0xff) > NCT6796D_DS))
+		return NULL;
+
+	switch (dev->path.pnp.device & 0xff) {
+	case NCT6796D_SP1:
+		__fallthrough;
+	case NCT6796D_SP2:
+		return ACPI_HID_COM;
+	case NCT6796D_KBC:
+		return ACPI_HID_KEYBOARD;
+	default:
+		return ACPI_HID_PNP;
+	}
+}
+#endif
+
+static struct device_operations ops = {
+	.read_resources   = pnp_read_resources,
+	.set_resources    = pnp_set_resources,
+	.enable_resources = pnp_enable_resources,
+	.enable           = pnp_alt_enable,
+	.init             = nct6796d_init,
+	.ops_pnp_mode     = &pnp_conf_mode_8787_aa,
+#if CONFIG(HAVE_ACPI_TABLES)
+	.acpi_fill_ssdt   = superio_common_fill_ssdt_generator,
+	.acpi_name        = superio_common_ldn_acpi_name,
+	.acpi_hid         = nct6796d_acpi_hid,
+#endif
+};
+
+static struct pnp_info pnp_dev_info[] = {
+	{ NULL, NCT6796D_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0,
+		0x0ff8, },
+	{ NULL, NCT6796D_SP1, PNP_IO0 | PNP_IRQ0,
+		0x0ff8, },
+	{ NULL, NCT6796D_SP2, PNP_IO0 | PNP_IRQ0,
+		0x0ff8, },
+	{ NULL, NCT6796D_KBC, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_IRQ1,
+		0x0fff, 0x0fff, },
+	{ NULL, NCT6796D_CIR, PNP_IO0 | PNP_IRQ0,
+		0x0ff8, },
+	{ NULL, NCT6796D_ACPI},
+	{ NULL, NCT6796D_HWM_FPLED, PNP_IO0 | PNP_IO1 | PNP_IRQ0,
+		0x0ffe, 0x0ffe, },
+	{ NULL, NCT6796D_BCLK_WDT2_WDTMEM},
+	{ NULL, NCT6796D_CIRWUP, PNP_IO0 | PNP_IRQ0,
+		0x0ff8, },
+	{ NULL, NCT6796D_GPIO_PP_OD},
+	{ NULL, NCT6796D_PORT80},
+	{ NULL, NCT6796D_WDT1},
+	{ NULL, NCT6796D_WDTMEM},
+	{ NULL, NCT6796D_GPIOBASE, PNP_IO0,
+		0x0ff8, },
+	{ NULL, NCT6796D_GPIO0},
+	{ NULL, NCT6796D_GPIO1},
+	{ NULL, NCT6796D_GPIO2},
+	{ NULL, NCT6796D_GPIO3},
+	{ NULL, NCT6796D_GPIO4},
+	{ NULL, NCT6796D_GPIO5},
+	{ NULL, NCT6796D_GPIO6},
+	{ NULL, NCT6796D_GPIO7},
+	{ NULL, NCT6796D_GPIO8},
+	{ NULL, NCT6796D_DS5},
+	{ NULL, NCT6796D_DS3},
+	{ NULL, NCT6796D_PCHDSW},
+	{ NULL, NCT6796D_DSWWOPT},
+	{ NULL, NCT6796D_DS3OPT},
+	{ NULL, NCT6796D_DSDSS},
+	{ NULL, NCT6796D_DSPU},
+};
+
+static void enable_dev(struct device *dev)
+{
+	pnp_enable_devices(dev, &ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info);
+}
+
+struct chip_operations superio_nuvoton_nct6796d_ops = {
+	.name = "NUVOTON NCT6796D Super I/O",
+	.enable_dev = enable_dev,
+};

From f813e602cf2ec46260dedcb68dc040242b45f83f Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Wed, 4 Feb 2026 10:33:54 -0600
Subject: [PATCH 3325/3886] sio/nuvoton/nct6796d: Add additional LDNs

Add new LDNs supported by the NCT6796D:
- 0x11: PGPIO, RI PSOUT Wake-Up
- 0x12: LED control
- 0x15: LED control 2

Change-Id: Icef4d32fad5430cbbe8ee4f3719d603361cfea95
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91101
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
---
 src/superio/nuvoton/nct6796d/nct6796d.h | 3 +++
 src/superio/nuvoton/nct6796d/superio.c  | 3 +++
 2 files changed, 6 insertions(+)

diff --git a/src/superio/nuvoton/nct6796d/nct6796d.h b/src/superio/nuvoton/nct6796d/nct6796d.h
index 53aeab4e2d..5468acbab1 100644
--- a/src/superio/nuvoton/nct6796d/nct6796d.h
+++ b/src/superio/nuvoton/nct6796d/nct6796d.h
@@ -17,7 +17,10 @@
 #define NCT6796D_BCLK_WDT2_WDTMEM	0x0D /* BCLK, WDT2, WDT_MEM */
 #define NCT6796D_CIRWUP			0x0E /* CIR Wake-Up */
 #define NCT6796D_GPIO_PP_OD		0x0F /* GPIO Push-Pull/Open-Drain */
+#define NCT6796D_PGPIO_RI_PSOUT		0x11 /* PGPIO, RI PSOUT Wake-Up */
+#define NCT6796D_LED			0x12 /* LED control */
 #define NCT6796D_PORT80			0x14 /* Port 80 UART */
+#define NCT6796D_LED2			0x15 /* LED Control 2 */
 #define NCT6796D_DS			0x16 /* Deep Sleep */
 
 /* Virtual LDNs */
diff --git a/src/superio/nuvoton/nct6796d/superio.c b/src/superio/nuvoton/nct6796d/superio.c
index 65d7465461..79dc685eef 100644
--- a/src/superio/nuvoton/nct6796d/superio.c
+++ b/src/superio/nuvoton/nct6796d/superio.c
@@ -74,7 +74,10 @@ static struct pnp_info pnp_dev_info[] = {
 	{ NULL, NCT6796D_CIRWUP, PNP_IO0 | PNP_IRQ0,
 		0x0ff8, },
 	{ NULL, NCT6796D_GPIO_PP_OD},
+	{ NULL, NCT6796D_PGPIO_RI_PSOUT},
+	{ NULL, NCT6796D_LED},
 	{ NULL, NCT6796D_PORT80},
+	{ NULL, NCT6796D_LED2},
 	{ NULL, NCT6796D_WDT1},
 	{ NULL, NCT6796D_WDTMEM},
 	{ NULL, NCT6796D_GPIOBASE, PNP_IO0,

From 255fcb14ba02061d8853bdd4d9060bf0009e4253 Mon Sep 17 00:00:00 2001
From: Patrick Rudolph <patrick.rudolph@9elements.com>
Date: Sun, 1 Feb 2026 10:02:46 +0100
Subject: [PATCH 3326/3886] sb/intel/bd82x6x/lpc: Advertise all fixed MMIO
 ranges

Currently not all fixed MMIO ranges are advertised to the resource
allocator. This is not an issue as long bottom-up allocation is
used and as long as only small PCI BARs are present on the system.

Properly advertise all fixed MMIO ranges decoded by the PCH:
- RCBA
- TXT private
- TXT reserved
- TPM TIS
- LGMR
- HPET

Also remove subtractive decoding from IOAPIC and SPI ROM. Comments
indicate that there's an issue with the OS, but newer platforms also
don't set it to subtractive. No issue was seen with EDK2 payload and
Linux 6.8.8. As a side effect IOAPIC and SPI ROM are now marked as
reserved in e820, which should help payloads not aware of IOAPIC
and SPI ROM to behave more properly.

TEST=Still boots on Lenovo X220. No issues seen in coreboot or Linux.

New e820 reserved ranges:
[DEBUG]  15. 00000000fec00000-00000000fec00fff: RESERVED
[DEBUG]  16. 00000000fed00000-00000000fed00fff: RESERVED
[DEBUG]  18. 00000000fed1c000-00000000fed3ffff: RESERVED
[DEBUG]  19. 00000000fed45000-00000000fed91fff: RESERVED
[DEBUG]  20. 00000000ff000000-00000000ffffffff: RESERVED

Change-Id: I9c251a8c4a4403c5dc0ad535769d8d893dc64a05
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91040
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
---
 src/southbridge/intel/bd82x6x/lpc.c | 56 ++++++++++++++++++++++++++---
 1 file changed, 52 insertions(+), 4 deletions(-)

diff --git a/src/southbridge/intel/bd82x6x/lpc.c b/src/southbridge/intel/bd82x6x/lpc.c
index 67d883ad48..cdd1bb3f11 100644
--- a/src/southbridge/intel/bd82x6x/lpc.c
+++ b/src/southbridge/intel/bd82x6x/lpc.c
@@ -1,5 +1,6 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
+#include <arch/hpet.h>
 #include <console/console.h>
 #include <device/device.h>
 #include <device/pci.h>
@@ -560,19 +561,66 @@ static void pch_lpc_read_resources(struct device *dev)
 	res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE |
 		     IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
 
-	res = new_resource(dev, IOINDEX_SUBTRACTIVE(io_index++, 0));
+	res = new_resource(dev, 2);
 	res->base = 0xff000000;
 	/* Some systems (e.g. X230) have 12 MiB flash.
 	   SPI controller supports up to 2 x 16 MiB of flash but
 	   address map limits this to 16MiB.  */
 	res->size = 0x01000000; /* 16 MB for flash */
-	res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE |
-		     IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
+	res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED |
+		     IORESOURCE_FIXED | IORESOURCE_RESERVE;
 
 	res = new_resource(dev, 3); /* IOAPIC */
 	res->base = IO_APIC_ADDR;
 	res->size = 0x00001000;
-	res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
+	res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED |
+		     IORESOURCE_FIXED | IORESOURCE_RESERVE;
+
+	/* HPET */
+	res = new_resource(dev, 4);
+	res->base = (resource_t)HPET_BASE_ADDRESS;
+	res->size = 4 * KiB;
+	res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED |
+		     IORESOURCE_FIXED | IORESOURCE_RESERVE;
+
+	/* TXT_PRIVATE_SPACE */
+	res = new_resource(dev, 5);
+	res->base = (resource_t)0xfed20000;
+	res->size = 0x20000;
+	res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED |
+		     IORESOURCE_FIXED | IORESOURCE_RESERVE;
+
+	/* Misc ICH + TXT_RESERVED_SPACE */
+	res = new_resource(dev, 6);
+	res->base = (resource_t)0xfed45000;
+	res->size = 0x4b000;
+	res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED |
+			IORESOURCE_FIXED | IORESOURCE_RESERVE;
+
+	/* RCBA */
+	res = new_resource(dev, RCBA);
+	res->base = (resource_t)CONFIG_FIXED_RCBA_MMIO_BASE;
+	res->size = CONFIG_RCBA_LENGTH;
+	res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED |
+			IORESOURCE_FIXED | IORESOURCE_RESERVE;
+
+	/* LPC TPM TIS */
+	res = new_resource(dev, IOINDEX_SUBTRACTIVE(io_index++, 0));
+	res->base = 0xfed40000;
+	res->size = 0x00005000;
+	res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE |
+		     IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
+
+	/* Check LPC Memory Decode register. */
+	u32 reg = pci_read_config32(dev, LGMR);
+	if (reg & 1) {
+		reg &= ~0xffff;
+		res = new_resource(dev, LGMR);
+		res->base = reg;
+		res->size = 64 * 1024;
+		res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED |
+			     IORESOURCE_FIXED | IORESOURCE_RESERVE;
+	}
 
 	/* Set PCH IO decode ranges if required.*/
 	if ((config->gen1_dec & 0xFFFC) > 0x1000) {

From ab42fceadc7a2d2d802463611cf2e1b1b2f06cf2 Mon Sep 17 00:00:00 2001
From: Alicja Michalska <alicja.michalska@9elements.com>
Date: Tue, 10 Feb 2026 19:20:17 +0100
Subject: [PATCH 3327/3886] MAINTAINERS: Add myself as maintainer for Intel TGL
 and PTL

I would like to stay on track for everything regarding PantherLake,
given I'm working alongside Intel's engineers to support this SoC
properly.

TigerLake is just a formality, there are only two maintainers currently
and not many systems supported. I own the only TGL-H system in the tree
(erying/tgl) and ELDRID (Google/Volteer baseboard) with TGL-UP3.

Change-Id: I4849aa85787528086e247d9aec8be6138523f5a7
Signed-off-by: Alicja Michalska <alicja.michalska@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91150
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
---
 MAINTAINERS | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/MAINTAINERS b/MAINTAINERS
index 083f91e9e6..2c21b764e9 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -927,12 +927,14 @@ M:	Pranava Y N <pranavayn@google.com>
 M:	Jayvik Desai <jayvik@google.com>
 M:	Avi Uday <aviuday@google.com>
 M:	Dinesh Gehlot <digehlot@google.com>
+M:	Alicja Michalska <alicja.michalska@9elements.com>
 S:	Maintained
 F:	src/soc/intel/pantherlake/
 
 INTEL TIGERLAKE SOC
 M:	Subrata Banik <subratabanik@google.com>
 M:	Nick Vaccaro <nvaccaro@chromium.org>
+M:	Alicja Michalska <alicja.michalska@9elements.com>
 S:	Maintained
 F:	src/soc/intel/tigerlake/
 

From 7d94e5a6603f167b0f34d68456ec1d3427b2aa42 Mon Sep 17 00:00:00 2001
From: Alicja Michalska <alicja.michalska@9elements.com>
Date: Tue, 10 Feb 2026 19:29:50 +0100
Subject: [PATCH 3328/3886] MAINTAINERS: Add myself as maintainer of
 PantherLake reference board

Change-Id: Ief08115a3a92b4ccb2f52f461506eca2ca64e070
Signed-off-by: Alicja Michalska <alicja.michalska@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91151
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
---
 MAINTAINERS | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/MAINTAINERS b/MAINTAINERS
index 2c21b764e9..ce9b93d949 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -435,6 +435,11 @@ M:	Vanessa Eusebio <vanessa.f.eusebio@intel.com>
 S:	Maintained
 F:	src/mainboard/intel/harcuvar/
 
+INTEL PANTHERLAKE_CRB MAINBOARD
+M:	Alicja Michalska <alicja.michalska@9elements.com>
+S:	Supported
+F:	src/mainboard/intel/pantherlake_crb/
+
 
 
 INVENTEC MAINBOARDS

From 2158ebb9338f4d71c58805f41113c68331521450 Mon Sep 17 00:00:00 2001
From: Pranava Y N <pranavayn@google.com>
Date: Thu, 12 Feb 2026 15:22:09 +0530
Subject: [PATCH 3329/3886] mb/google/fatcat/var/lapis: configure
 chipset_lockdown for lapis

Configure lapis to use coreboot (CHIPSET_LOCKDOWN_COREBOOT) to set BIOS
interface lock. Otherwise, FSP code will be responsible for locking the
chipset.

BUG=None
TEST=Able to build and boot lapis

Change-Id: Ia3a13390e4a1862164d820dd1ee220dea682a6a0
Signed-off-by: Pranava Y N <pranavayn@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91177
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Avi Uday <aviuday@google.com>
---
 src/mainboard/google/fatcat/variants/lapis/overridetree.cb | 1 +
 1 file changed, 1 insertion(+)

diff --git a/src/mainboard/google/fatcat/variants/lapis/overridetree.cb b/src/mainboard/google/fatcat/variants/lapis/overridetree.cb
index 6d6961e15b..0a84ba36e9 100644
--- a/src/mainboard/google/fatcat/variants/lapis/overridetree.cb
+++ b/src/mainboard/google/fatcat/variants/lapis/overridetree.cb
@@ -111,6 +111,7 @@ chip soc/intel/pantherlake
 	#| I2C3              | cr50 TPM.                 |
 	#+-------------------+---------------------------+
 	register "common_soc_config" = "{
+		.chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT,
 		.i2c[3] = {
 			.early_init=1,
 			.speed = I2C_SPEED_FAST,

From 96b29e37dbeb2974faec4cee94f929a7cf52a99b Mon Sep 17 00:00:00 2001
From: Subrata Banik <subratabanik@google.com>
Date: Wed, 11 Feb 2026 20:21:21 +0530
Subject: [PATCH 3330/3886] util/font: Add support for dynamic canvas
 dimensions

Update generate_font.py to support user-defined canvas width and height
via command-line arguments. This replaces the hardcoded 16x24 limits.

Key changes:
- Use argparse for --width and --height parameters.
- Ensure glyphs are left-aligned to the MSB (bit 15 or 31) for
  scalability.

TEST=Able to create font table upto 32 pixels wide.

```
python generate_font.py <path_to_ttf> --width 24 --height 32 > font_table.c
```

Change-Id: Ifd02a979abf41a2c2b088ae58bb931f9f6421491
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91165
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 util/font/generate_font.py | 104 +++++++++++++++++++++++--------------
 1 file changed, 66 insertions(+), 38 deletions(-)

diff --git a/util/font/generate_font.py b/util/font/generate_font.py
index 4af3ed0434..b301a2e533 100644
--- a/util/font/generate_font.py
+++ b/util/font/generate_font.py
@@ -9,31 +9,40 @@ The output is a C source file containing:
 3. A character width table for proportional spacing.
 
 Usage:
-  python generate_font.py <path_to_ttf> > font_table.c
+  python generate_font.py <path_to_ttf> --width 24 --height 32 > font_table.c
 """
-
+import argparse
 from PIL import Image, ImageFont, ImageDraw
 import sys
 import os
 
-# FONT DIMENSIONS
-FONT_SIZE = 19
-CANVAS_WIDTH = 16
-CANVAS_HEIGHT = 24
-Y_OFFSET = -2
-
 # PRINTABLE ASCII RANGE
 START_CHAR = 32
 END_CHAR = 126
 NUM_CHARS = END_CHAR - START_CHAR + 1
 
-def generate_c_table(font_path):
+def generate_c_table(font_path, canvas_width, canvas_height):
     if not os.path.exists(font_path):
         print(f"Error: Font file '{font_path}' not found.", file=sys.stderr)
         sys.exit(1)
 
+    # Validation: Width must not exceed 32 bits for uint32_t storage
+    if canvas_width > 32:
+        print(f"Error: Requested width ({canvas_width}) exceeds 32-bit capacity. "
+              "The current renderer supports up to 32 pixels wide.", file=sys.stderr)
+        sys.exit(1)
+
+    # Validation: Basic sanity check for positive dimensions
+    if canvas_width <= 0 or canvas_height <= 0:
+        print("Error: Width and Height must be positive integers.", file=sys.stderr)
+        sys.exit(1)
+
+    # Use canvas_width as font size to maintain original calculation style
+    font_size = canvas_width
+    y_offset = 0
+
     try:
-        font = ImageFont.truetype(font_path, FONT_SIZE)
+        font = ImageFont.truetype(font_path, font_size)
     except OSError:
         print(f"Error: Could not open font file '{font_path}'.", file=sys.stderr)
         sys.exit(1)
@@ -43,63 +52,79 @@ def generate_c_table(font_path):
     print("/*")
     print(" * THIS FILE WAS AUTOMATICALLY GENERATED. DO NOT EDIT.")
     print(f" * Source: {os.path.basename(font_path)}")
-    print(f" * Command: python util/font/{os.path.basename(__file__)} {font_path}")
+    print(f" * Command: python {os.path.basename(__file__)} {font_path} --width {canvas_width} --height {canvas_height}")
     print(" */\n")
     print("#include <stdint.h>\n")
 
     # 1. Output the Macros for C code usage
-    print(f"#define FONT_WIDTH      {CANVAS_WIDTH}")
-    print(f"#define FONT_HEIGHT     {CANVAS_HEIGHT}")
+    print(f"#define FONT_WIDTH      {canvas_width}")
+    print(f"#define FONT_HEIGHT     {canvas_height}")
     print(f"#define FONT_START_CHAR {START_CHAR}")
     print(f"#define FONT_END_CHAR   {END_CHAR}")
     print(f"#define FONT_NUM_CHARS  (FONT_END_CHAR - FONT_START_CHAR + 1)\n")
 
     widths = []
 
-    # 2. Generate packed font table with block formatting
-    print(f"const uint16_t font_table[FONT_NUM_CHARS][FONT_HEIGHT] = {{")
+    # Choose data type based on width
+    data_type = "uint32_t"
+    hex_format = "08x" if canvas_width > 16 else "04x"
+    bit_depth = 32 if canvas_width > 16 else 16
+
+    # 2. Generate packed font table
+    print(f"const {data_type} font_table[FONT_NUM_CHARS][FONT_HEIGHT] = {{")
 
     for char_code in range(START_CHAR, END_CHAR + 1):
         char = chr(char_code)
-        image = Image.new("1", (CANVAS_WIDTH, CANVAS_HEIGHT), 0)
+        image = Image.new("1", (canvas_width, canvas_height), 0)
         draw = ImageDraw.Draw(image)
-        draw.text((0, Y_OFFSET), char, font=font, fill=1)
+        draw.text((0, y_offset), char, font=font, fill=1)
 
         pixels = list(image.getdata())
         rows = []
         global_mask = 0
 
-        for y in range(CANVAS_HEIGHT):
+        for y in range(canvas_height):
             row_val = 0
-            base = y * CANVAS_WIDTH
-            for x in range(CANVAS_WIDTH):
+            base = y * canvas_width
+            for x in range(canvas_width):
                 if pixels[base + x]:
-                    row_val |= (1 << ((CANVAS_WIDTH - 1) - x))
+                    # Map pixels to bits: Leftmost pixel is highest bit
+                    row_val |= (1 << ((canvas_width - 1) - x))
             rows.append(row_val)
             global_mask |= row_val
 
         # Dead space removal / Normalization
         left_shift = 0
         actual_width = 0
-        if global_mask > 0:
-            temp_mask = global_mask
-            while not (temp_mask & 0x8000):
-                temp_mask <<= 1
-                left_shift += 1
 
-            rightmost_bit = 0
-            for i in range(CANVAS_WIDTH):
-                if (global_mask >> i) & 1:
-                    rightmost_bit = i
+        if global_mask > 0:
+            # Find the leftmost pixel column
+            leftmost_col = 0
+            for i in range(canvas_width):
+                if (global_mask >> (canvas_width - 1 - i)) & 1:
+                    leftmost_col = i
                     break
-            actual_width = ((CANVAS_WIDTH - 1) - left_shift) - rightmost_bit + 1
+
+            # Find the rightmost pixel column
+            rightmost_col = 0
+            for i in range(canvas_width):
+                if (global_mask >> i) & 1:
+                    rightmost_col = (canvas_width - 1) - i
+                    break
+
+            # Width is the horizontal span of active pixels
+            actual_width = rightmost_col - leftmost_col + 1
+
+            # left_shift ensures character is left-aligned to MSB of the data type
+            left_shift = (bit_depth - canvas_width) + leftmost_col
         else:
-            actual_width = 6 # Default space width
+            actual_width = canvas_width // 3  # Default width for space
 
         widths.append(actual_width)
 
-        # Format the pre-shifted hex rows into blocks of 8
-        hex_values = [f"0x{(row << left_shift) & 0xFFFF:04x}" for row in rows]
+        # Pre-shift values to be MSB-aligned and mask based on bit depth
+        mask_val = 0xFFFFFFFF if bit_depth == 32 else 0xFFFF
+        hex_values = [f"0x{(row << left_shift) & mask_val:{hex_format}}" for row in rows]
         char_repr = f"'{char}'" if char not in ["'", "\\"] else f"'\\{char}'"
 
         print(f"\t[0x{char_code:02x} - FONT_START_CHAR] = {{")
@@ -118,7 +143,10 @@ def generate_c_table(font_path):
     print("};")
 
 if __name__ == "__main__":
-    if len(sys.argv) < 2:
-        print(f"Usage: python3 {sys.argv[0]} <path_to_ttf_file>")
-        sys.exit(1)
-    generate_c_table(sys.argv[1])
+    parser = argparse.ArgumentParser(description="Generate bitmapped font table.")
+    parser.add_argument("font_path", help="Path to TTF/OTF font file")
+    parser.add_argument("--width", type=int, default=24, help="Canvas width (default: 24)")
+    parser.add_argument("--height", type=int, default=32, help="Canvas height (default: 32)")
+
+    args = parser.parse_args()
+    generate_c_table(args.font_path, args.width, args.height)

From 5aeda3e7bb97cf0b8c7dbe6a71399f194a0e4efb Mon Sep 17 00:00:00 2001
From: Subrata Banik <subratabanik@google.com>
Date: Mon, 9 Feb 2026 23:40:27 +0530
Subject: [PATCH 3331/3886] lib: Export calculate_logo_coordinates for external
 use

Expose calculate_logo_coordinates() by moving its declaration to
bootsplash.h and removing the static qualifier in render_bmp.c.

This allows other parts of the codebase, such as the upcoming text
rendering logic, to reuse the existing logo positioning math to
calculate destination coordinates based on alignment settings.

Change-Id: I8f8b767b093d6bc2befefdc55fe2effa38b95752
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91154
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/include/bootsplash.h | 9 +++++++++
 src/lib/render_bmp.c     | 2 +-
 2 files changed, 10 insertions(+), 1 deletion(-)

diff --git a/src/include/bootsplash.h b/src/include/bootsplash.h
index a3d8487968..5caebd278d 100644
--- a/src/include/bootsplash.h
+++ b/src/include/bootsplash.h
@@ -141,6 +141,15 @@ struct logo_config {
 	uint8_t logo_bottom_margin;
 };
 
+/*
+ * Calculates the destination coordinates for the logo based on both horizontal and
+ * vertical alignment settings.
+ */
+struct logo_coordinates calculate_logo_coordinates(
+	uint32_t horizontal_resolution, uint32_t vertical_resolution,
+	uint32_t logo_width, uint32_t logo_height,
+	enum fw_splash_horizontal_alignment halignment,
+	enum fw_splash_vertical_alignment valignment);
 void render_logo_to_framebuffer(struct logo_config *config);
 void load_and_convert_bmp_to_blt(uintptr_t *logo, size_t *logo_size,
 	uintptr_t *blt, size_t *blt_size, uint32_t *pixel_height, uint32_t *pixel_width,
diff --git a/src/lib/render_bmp.c b/src/lib/render_bmp.c
index 39242d0d97..f5dc91221f 100644
--- a/src/lib/render_bmp.c
+++ b/src/lib/render_bmp.c
@@ -487,7 +487,7 @@ void convert_bmp_to_blt(uintptr_t logo, size_t logo_size,
  * Returning `struct logo_coordinates` that contains the calculated x and y coordinates
  * for rendering the logo.
  */
-static struct logo_coordinates calculate_logo_coordinates(
+struct logo_coordinates calculate_logo_coordinates(
 	uint32_t horizontal_resolution, uint32_t vertical_resolution,
 	uint32_t logo_width, uint32_t logo_height,
 	enum fw_splash_horizontal_alignment halignment,

From 8cd9454d00ed389164d55541c6c6842d7bb1f8b6 Mon Sep 17 00:00:00 2001
From: Subrata Banik <subratabanik@google.com>
Date: Wed, 4 Feb 2026 20:48:49 +0530
Subject: [PATCH 3332/3886] lib: Add support for text rendering on splash
 screen

Introduce FRAMEBUFFER_SPLASH_TEXT to allow rendering status messages
directly into the linear framebuffer. This enables displaying dynamic
information, such as battery levels or system status, during the
bootsplash stage without requiring complex graphics libraries.

Changes:
- Add Kconfig option to toggle framebuffer text support.
- User to call `render_text_to_framebuffer` to display the text message.
- Include render_text.c in ramstage build when
  FRAMEBUFFER_SPLASH_TEXT is enabled.
- Create 24x32 font table entry using GoogleSansFlex_24pt-Medium.ttf.

TEST=Able to build google/fatcat.

Change-Id: I6ac25d8d8a9d3d77a9cc2f8c6e0139268b2066b9
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91092
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/include/bootsplash.h                      |  13 +
 src/lib/Kconfig                               |  40 +
 src/lib/Makefile.mk                           |   2 +
 ...font_table_google_sans_flex_medium_24x32.c | 686 ++++++++++++++++++
 src/lib/fonts/fonts.h                         |  16 +
 src/lib/render_text.c                         | 210 ++++++
 6 files changed, 967 insertions(+)
 create mode 100644 src/lib/fonts/font_table_google_sans_flex_medium_24x32.c
 create mode 100644 src/lib/fonts/fonts.h
 create mode 100644 src/lib/render_text.c

diff --git a/src/include/bootsplash.h b/src/include/bootsplash.h
index 5caebd278d..cd02f7382e 100644
--- a/src/include/bootsplash.h
+++ b/src/include/bootsplash.h
@@ -20,6 +20,16 @@ enum bootsplash_type {
 	BOOTSPLASH_MAX_NUM,
 };
 
+enum bootsplash_text_type {
+	/* Indicates a bootsplash text message appear at the center of the screen. */
+	BOOTSPLASH_TEXT_CENTER,
+	/* Indicates a bootsplash text message appear at the footer of the screen. */
+	BOOTSPLASH_TEXT_FOOTER,
+
+	/* It's used to determine the total number of bootsplash types. */
+	BOOTSPLASH_TEXT_MAX_NUM,
+};
+
 /**
  * Sets up the framebuffer with the bootsplash.jpg from cbfs.
  * Returns 0 on success
@@ -157,6 +167,9 @@ void load_and_convert_bmp_to_blt(uintptr_t *logo, size_t *logo_size,
 void convert_bmp_to_blt(uintptr_t logo, size_t logo_size,
 	uintptr_t *blt, size_t *blt_size, uint32_t *pixel_height, uint32_t *pixel_width,
 	enum lb_fb_orientation orientation);
+void render_text_to_framebuffer(struct logo_config *config, const char *str,
+	enum bootsplash_text_type type);
+bool platform_get_splash_text(enum bootsplash_type logo_type, char *msg, size_t msg_max);
 
 /* Mainboard-specific override for logo filenames */
 const char *mainboard_bmp_logo_filename(void);
diff --git a/src/lib/Kconfig b/src/lib/Kconfig
index d70374d758..38cc459086 100644
--- a/src/lib/Kconfig
+++ b/src/lib/Kconfig
@@ -287,6 +287,46 @@ config PLATFORM_OFF_MODE_CHARGING_INDICATOR_LOGO_PATH
 	string "Path to off-mode charging logo file"
 	default "3rdparty/blobs/mainboard/\$(MAINBOARDDIR)/off_mode_charging.bmp"
 
+config FRAMEBUFFER_SPLASH_TEXT
+	bool "Enable splash screen text"
+	default n
+	help
+	  Enable logic to render bitmapped text strings directly into
+	  the linear framebuffer during the splash screen stage. This
+	  method uses a bitmapped font table to display system
+	  status messages, such as battery charging levels.
+
+if FRAMEBUFFER_SPLASH_TEXT
+
+choice
+	prompt "Font Selection"
+	default FONT_GOOGLE_SANS_FLEX_MEDIUM_24X32
+
+config FONT_GOOGLE_SANS_FLEX_MEDIUM_24X32
+	bool "Google Sans Flex Medium 24x32"
+	help
+	  Use the Google Sans Medium font table generated from
+	  GoogleSansFlex_24pt-Medium.ttf using `generate_font.py` script.
+	  Dimensions: 24x32 pixels.
+
+endchoice
+
+config FONT_WIDTH
+	int
+	default 24 if FONT_GOOGLE_SANS_FLEX_MEDIUM_24X32
+	default 16
+	help
+	  The width of the font canvas in pixels.
+
+config FONT_HEIGHT
+	int
+	default 32 if FONT_GOOGLE_SANS_FLEX_MEDIUM_24X32
+	default 24
+	help
+	  The height of the font canvas in pixels.
+
+endif # FRAMEBUFFER_SPLASH_TEXT
+
 endmenu
 
 config HAVE_EARLY_POWEROFF_SUPPORT
diff --git a/src/lib/Makefile.mk b/src/lib/Makefile.mk
index 0405cbeb5b..3ffdfa807c 100644
--- a/src/lib/Makefile.mk
+++ b/src/lib/Makefile.mk
@@ -149,6 +149,8 @@ ramstage-y += wrdd.c
 ramstage-$(CONFIG_CONSOLE_CBMEM) += cbmem_console.c
 ramstage-$(CONFIG_BMP_LOGO) += bmp_logo.c
 ramstage-$(CONFIG_BMP_LOGO) += render_bmp.c
+ramstage-$(CONFIG_FRAMEBUFFER_SPLASH_TEXT) += render_text.c
+ramstage-$(CONFIG_FONT_GOOGLE_SANS_FLEX_MEDIUM_24X32) += fonts/font_table_google_sans_flex_medium_24x32.c
 ramstage-$(CONFIG_BOOTSPLASH) += bootsplash.c
 ramstage-$(CONFIG_BOOTSPLASH) += jpeg.c
 ramstage-$(CONFIG_COLLECT_TIMESTAMPS) += timestamp.c
diff --git a/src/lib/fonts/font_table_google_sans_flex_medium_24x32.c b/src/lib/fonts/font_table_google_sans_flex_medium_24x32.c
new file mode 100644
index 0000000000..7b211698bc
--- /dev/null
+++ b/src/lib/fonts/font_table_google_sans_flex_medium_24x32.c
@@ -0,0 +1,686 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+/*
+ * THIS FILE WAS AUTOMATICALLY GENERATED. DO NOT EDIT.
+ * Source: GoogleSansFlex_24pt-Medium.ttf
+ * Command: python generate_font.py GoogleSansFlex_24pt-Medium.ttf --width 24 --height 32
+ */
+
+#include <stdint.h>
+
+#define FONT_WIDTH      24
+#define FONT_HEIGHT     32
+#define FONT_START_CHAR 32
+#define FONT_END_CHAR   126
+#define FONT_NUM_CHARS  (FONT_END_CHAR - FONT_START_CHAR + 1)
+
+const uint32_t font_table[FONT_NUM_CHARS][FONT_HEIGHT] = {
+	[0x20 - FONT_START_CHAR] = {
+		0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+		0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+		0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+		0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+	}, /* ' ' */
+	[0x21 - FONT_START_CHAR] = {
+		0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x60000000, 0x60000000,
+		0x60000000, 0x60000000, 0x60000000, 0x60000000, 0x60000000, 0x60000000, 0x60000000, 0x60000000,
+		0x60000000, 0x60000000, 0x00000000, 0x00000000, 0x60000000, 0xf0000000, 0x60000000, 0x00000000,
+		0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+	}, /* '!' */
+	[0x22 - FONT_START_CHAR] = {
+		0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xec000000, 0xec000000,
+		0xec000000, 0xec000000, 0xec000000, 0xec000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+		0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+		0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+	}, /* '"' */
+	[0x23 - FONT_START_CHAR] = {
+		0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x0e300000, 0x0c700000,
+		0x0c600000, 0x0c600000, 0x0c600000, 0x7ffc0000, 0xfffc0000, 0x18600000, 0x18e00000, 0x18c00000,
+		0xfff80000, 0xfff80000, 0x18c00000, 0x38c00000, 0x30c00000, 0x31800000, 0x31800000, 0x00000000,
+		0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+	}, /* '#' */
+	[0x24 - FONT_START_CHAR] = {
+		0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x06000000, 0x06000000, 0x1f800000, 0x3fe00000,
+		0x76f00000, 0x66600000, 0x66000000, 0x76000000, 0x7e000000, 0x3f000000, 0x0fc00000, 0x07e00000,
+		0x06700000, 0x06700000, 0xe6300000, 0xe6700000, 0x7ee00000, 0x3fe00000, 0x1f800000, 0x06000000,
+		0x06000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+	}, /* '$' */
+	[0x25 - FONT_START_CHAR] = {
+		0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x3c020000, 0x7e070000,
+		0xc7060000, 0xc30c0000, 0xc31c0000, 0xc3180000, 0xfe300000, 0x7c700000, 0x00600000, 0x00c00000,
+		0x01cf0000, 0x039fc000, 0x0318c000, 0x0730e000, 0x0e306000, 0x0c38c000, 0x1c1fc000, 0x180f8000,
+		0x08000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+	}, /* '%' */
+	[0x26 - FONT_START_CHAR] = {
+		0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x02000000, 0x1f800000,
+		0x1fc00000, 0x38e00000, 0x38000000, 0x38000000, 0x1c000000, 0x1e000000, 0x3e000000, 0x77000000,
+		0xe3800000, 0xe1cc0000, 0xe0ec0000, 0xe0fc0000, 0xe0780000, 0x70780000, 0x7ffc0000, 0x1fd80000,
+		0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+	}, /* '&' */
+	[0x27 - FONT_START_CHAR] = {
+		0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xe0000000, 0xe0000000,
+		0xe0000000, 0xe0000000, 0xe0000000, 0xe0000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+		0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+		0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+	}, /* '\'' */
+	[0x28 - FONT_START_CHAR] = {
+		0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x0c000000, 0x1e000000, 0x1c000000, 0x38000000,
+		0x30000000, 0x70000000, 0x70000000, 0x60000000, 0x60000000, 0xe0000000, 0xe0000000, 0xe0000000,
+		0xe0000000, 0x60000000, 0x60000000, 0x70000000, 0x70000000, 0x38000000, 0x38000000, 0x1c000000,
+		0x1e000000, 0x0c000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+	}, /* '(' */
+	[0x29 - FONT_START_CHAR] = {
+		0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x60000000, 0x70000000, 0x70000000, 0x38000000,
+		0x18000000, 0x1c000000, 0x1c000000, 0x0c000000, 0x0e000000, 0x0e000000, 0x0e000000, 0x0e000000,
+		0x0e000000, 0x0e000000, 0x0c000000, 0x1c000000, 0x1c000000, 0x18000000, 0x38000000, 0x70000000,
+		0xf0000000, 0x60000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+	}, /* ')' */
+	[0x2a - FONT_START_CHAR] = {
+		0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x18000000, 0x18000000,
+		0x98800000, 0xff800000, 0xff000000, 0x1c000000, 0x3e000000, 0x67000000, 0x62000000, 0x00000000,
+		0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+		0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+	}, /* '*' */
+	[0x2b - FONT_START_CHAR] = {
+		0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+		0x00000000, 0x00000000, 0x00000000, 0x06000000, 0x06000000, 0x06000000, 0x06000000, 0xffe00000,
+		0xffe00000, 0xffe00000, 0x06000000, 0x06000000, 0x06000000, 0x06000000, 0x00000000, 0x00000000,
+		0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+	}, /* '+' */
+	[0x2c - FONT_START_CHAR] = {
+		0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+		0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+		0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xf0000000, 0xf0000000, 0x70000000, 0x60000000,
+		0xc0000000, 0x40000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+	}, /* ',' */
+	[0x2d - FONT_START_CHAR] = {
+		0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+		0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xff000000, 0xff000000,
+		0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+		0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+	}, /* '-' */
+	[0x2e - FONT_START_CHAR] = {
+		0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+		0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+		0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xf0000000, 0xf0000000, 0x60000000, 0x00000000,
+		0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+	}, /* '.' */
+	[0x2f - FONT_START_CHAR] = {
+		0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x07000000, 0x06000000,
+		0x06000000, 0x0e000000, 0x0c000000, 0x0c000000, 0x1c000000, 0x18000000, 0x18000000, 0x38000000,
+		0x38000000, 0x30000000, 0x70000000, 0x70000000, 0x60000000, 0x60000000, 0xe0000000, 0x00000000,
+		0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+	}, /* '/' */
+	[0x30 - FONT_START_CHAR] = {
+		0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x03000000, 0x1fc00000,
+		0x3fe00000, 0x38700000, 0x70380000, 0x60380000, 0xe0380000, 0xe0180000, 0xe0180000, 0xe0180000,
+		0xe0180000, 0xe0180000, 0xe0380000, 0x60380000, 0x70300000, 0x38f00000, 0x3fe00000, 0x0fc00000,
+		0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+	}, /* '0' */
+	[0x31 - FONT_START_CHAR] = {
+		0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x0c000000, 0x3c000000,
+		0x7c000000, 0xec000000, 0xcc000000, 0x0c000000, 0x0c000000, 0x0c000000, 0x0c000000, 0x0c000000,
+		0x0c000000, 0x0c000000, 0x0c000000, 0x0c000000, 0x0c000000, 0x0c000000, 0x0c000000, 0x00000000,
+		0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+	}, /* '1' */
+	[0x32 - FONT_START_CHAR] = {
+		0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x0c000000, 0x3f800000,
+		0x7fc00000, 0xf1c00000, 0x60e00000, 0x00e00000, 0x00e00000, 0x01c00000, 0x01c00000, 0x03800000,
+		0x07000000, 0x0e000000, 0x1c000000, 0x38000000, 0x70000000, 0xe0000000, 0xffe00000, 0xffe00000,
+		0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+	}, /* '2' */
+	[0x33 - FONT_START_CHAR] = {
+		0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x0c000000, 0x3f800000,
+		0x7fc00000, 0xe1c00000, 0x60e00000, 0x00e00000, 0x00c00000, 0x01c00000, 0x0f800000, 0x0f800000,
+		0x01c00000, 0x00e00000, 0x00e00000, 0x40e00000, 0xe0e00000, 0xf1e00000, 0x7fc00000, 0x3f800000,
+		0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+	}, /* '3' */
+	[0x34 - FONT_START_CHAR] = {
+		0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x01c00000, 0x01c00000,
+		0x03c00000, 0x07c00000, 0x0ec00000, 0x0cc00000, 0x1cc00000, 0x38c00000, 0x30c00000, 0x70c00000,
+		0xe0c00000, 0xfff00000, 0xfff00000, 0x00c00000, 0x00c00000, 0x00c00000, 0x00c00000, 0x00000000,
+		0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+	}, /* '4' */
+	[0x35 - FONT_START_CHAR] = {
+		0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x3fe00000, 0x7fe00000,
+		0x70000000, 0x70000000, 0x60000000, 0x60000000, 0x6f800000, 0x7fc00000, 0x79e00000, 0x20e00000,
+		0x00700000, 0x00700000, 0x60700000, 0xe0600000, 0x70e00000, 0x7fc00000, 0x3f800000, 0x00000000,
+		0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+	}, /* '5' */
+	[0x36 - FONT_START_CHAR] = {
+		0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x02000000, 0x03800000,
+		0x07800000, 0x07000000, 0x0e000000, 0x1c000000, 0x3c000000, 0x3f800000, 0x7fc00000, 0x79e00000,
+		0xe0700000, 0xe0700000, 0xe0700000, 0xe0700000, 0xe0700000, 0x70e00000, 0x7fc00000, 0x1f800000,
+		0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+	}, /* '6' */
+	[0x37 - FONT_START_CHAR] = {
+		0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xffe00000, 0xffe00000,
+		0x00c00000, 0x01c00000, 0x01800000, 0x03800000, 0x03000000, 0x07000000, 0x0e000000, 0x0e000000,
+		0x1c000000, 0x1c000000, 0x38000000, 0x38000000, 0x70000000, 0x70000000, 0xe0000000, 0x00000000,
+		0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+	}, /* '7' */
+	[0x38 - FONT_START_CHAR] = {
+		0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x06000000, 0x3f800000,
+		0x7fc00000, 0x70e00000, 0x60e00000, 0x60e00000, 0x60e00000, 0x71c00000, 0x3f800000, 0x3fc00000,
+		0x71e00000, 0xe0e00000, 0xe0600000, 0xe0700000, 0xe0600000, 0xf0e00000, 0x7fc00000, 0x3f800000,
+		0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+	}, /* '8' */
+	[0x39 - FONT_START_CHAR] = {
+		0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x06000000, 0x3f800000,
+		0x7fc00000, 0xf0e00000, 0xe0600000, 0xc0700000, 0xc0700000, 0xe0700000, 0xe0e00000, 0x7be00000,
+		0x3fc00000, 0x1fc00000, 0x03800000, 0x07000000, 0x0f000000, 0x0e000000, 0x1c000000, 0x18000000,
+		0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+	}, /* '9' */
+	[0x3a - FONT_START_CHAR] = {
+		0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+		0x00000000, 0x00000000, 0x00000000, 0xf0000000, 0xf0000000, 0x60000000, 0x00000000, 0x00000000,
+		0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xf0000000, 0xf0000000, 0x60000000, 0x00000000,
+		0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+	}, /* ':' */
+	[0x3b - FONT_START_CHAR] = {
+		0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+		0x00000000, 0x00000000, 0x00000000, 0x70000000, 0xf0000000, 0x70000000, 0x00000000, 0x00000000,
+		0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xf0000000, 0xf0000000, 0x70000000, 0x60000000,
+		0xc0000000, 0x40000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+	}, /* ';' */
+	[0x3c - FONT_START_CHAR] = {
+		0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+		0x00000000, 0x00000000, 0x00000000, 0x00200000, 0x00e00000, 0x07e00000, 0x1f000000, 0x7c000000,
+		0xe0000000, 0xfc000000, 0x1f000000, 0x07e00000, 0x00e00000, 0x00200000, 0x00000000, 0x00000000,
+		0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+	}, /* '<' */
+	[0x3d - FONT_START_CHAR] = {
+		0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+		0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xffe00000, 0xffe00000, 0xffe00000,
+		0x00000000, 0xffe00000, 0xffe00000, 0xffe00000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+		0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+	}, /* '=' */
+	[0x3e - FONT_START_CHAR] = {
+		0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+		0x00000000, 0x00000000, 0x00000000, 0x80000000, 0xe0000000, 0xf8000000, 0x3f000000, 0x07c00000,
+		0x01c00000, 0x07c00000, 0x3f000000, 0xf8000000, 0xe0000000, 0x80000000, 0x00000000, 0x00000000,
+		0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+	}, /* '>' */
+	[0x3f - FONT_START_CHAR] = {
+		0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x0c000000, 0x3f800000,
+		0x7fc00000, 0xe1c00000, 0x61c00000, 0x01c00000, 0x01c00000, 0x03800000, 0x07000000, 0x0e000000,
+		0x0e000000, 0x0c000000, 0x0c000000, 0x00000000, 0x0c000000, 0x1e000000, 0x1e000000, 0x0e000000,
+		0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+	}, /* '?' */
+	[0x40 - FONT_START_CHAR] = {
+		0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00e00000,
+		0x07fc0000, 0x0f0f0000, 0x38038000, 0x3001c000, 0x61fcc000, 0x63fc6000, 0xc60c6000, 0xc60c6000,
+		0xc60c6000, 0xc60c6000, 0xc60c6000, 0x671ee000, 0x63f7c000, 0x70c10000, 0x38000000, 0x1c000000,
+		0x0ff80000, 0x03fc0000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+	}, /* '@' */
+	[0x41 - FONT_START_CHAR] = {
+		0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x01c00000, 0x03c00000,
+		0x03e00000, 0x07e00000, 0x07600000, 0x06700000, 0x0e700000, 0x0e300000, 0x0c380000, 0x1c380000,
+		0x181c0000, 0x3ffc0000, 0x3ffc0000, 0x300e0000, 0x700e0000, 0x70060000, 0xe0070000, 0x00000000,
+		0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+	}, /* 'A' */
+	[0x42 - FONT_START_CHAR] = {
+		0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xff800000, 0xffc00000,
+		0xc0e00000, 0xc0600000, 0xc0600000, 0xc0600000, 0xc0e00000, 0xffc00000, 0xffc00000, 0xc0e00000,
+		0xc0700000, 0xc0700000, 0xc0700000, 0xc0700000, 0xc0e00000, 0xffe00000, 0xff800000, 0x00000000,
+		0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+	}, /* 'B' */
+	[0x43 - FONT_START_CHAR] = {
+		0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00c00000, 0x0ff80000,
+		0x1ffe0000, 0x3c1e0000, 0x78040000, 0x70000000, 0xe0000000, 0xe0000000, 0xe0000000, 0xe0000000,
+		0xe0000000, 0xe0000000, 0xe0000000, 0x70040000, 0x78060000, 0x3e1e0000, 0x1ffc0000, 0x07f80000,
+		0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+	}, /* 'C' */
+	[0x44 - FONT_START_CHAR] = {
+		0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xff800000, 0xffe00000,
+		0xc1f00000, 0xc0780000, 0xc0380000, 0xc01c0000, 0xc01c0000, 0xc01c0000, 0xc01c0000, 0xc01c0000,
+		0xc01c0000, 0xc01c0000, 0xc0380000, 0xc0780000, 0xc1f00000, 0xffe00000, 0xff800000, 0x00000000,
+		0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+	}, /* 'D' */
+	[0x45 - FONT_START_CHAR] = {
+		0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xffc00000, 0xffc00000,
+		0xc0000000, 0xc0000000, 0xc0000000, 0xc0000000, 0xc0000000, 0xff800000, 0xff800000, 0xff800000,
+		0xc0000000, 0xc0000000, 0xc0000000, 0xc0000000, 0xc0000000, 0xffc00000, 0xffc00000, 0x00000000,
+		0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+	}, /* 'E' */
+	[0x46 - FONT_START_CHAR] = {
+		0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xffc00000, 0xffc00000,
+		0xc0000000, 0xc0000000, 0xc0000000, 0xc0000000, 0xc0000000, 0xff800000, 0xff800000, 0xff800000,
+		0xc0000000, 0xc0000000, 0xc0000000, 0xc0000000, 0xc0000000, 0xc0000000, 0xc0000000, 0x00000000,
+		0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+	}, /* 'F' */
+	[0x47 - FONT_START_CHAR] = {
+		0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00c00000, 0x07f80000,
+		0x1ffe0000, 0x3c0e0000, 0x78040000, 0x70000000, 0xe0000000, 0xe0000000, 0xe0000000, 0xe07f8000,
+		0xe07f8000, 0xe0018000, 0xe0038000, 0x70038000, 0x78070000, 0x3e0f0000, 0x1ffe0000, 0x07f80000,
+		0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+	}, /* 'G' */
+	[0x48 - FONT_START_CHAR] = {
+		0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xc0180000, 0xc0180000,
+		0xc0180000, 0xc0180000, 0xc0180000, 0xc0180000, 0xc0180000, 0xfff80000, 0xfff80000, 0xc0180000,
+		0xc0180000, 0xc0180000, 0xc0180000, 0xc0180000, 0xc0180000, 0xc0180000, 0xc0180000, 0x00000000,
+		0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+	}, /* 'H' */
+	[0x49 - FONT_START_CHAR] = {
+		0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xe0000000, 0xe0000000,
+		0xe0000000, 0xe0000000, 0xe0000000, 0xe0000000, 0xe0000000, 0xe0000000, 0xe0000000, 0xe0000000,
+		0xe0000000, 0xe0000000, 0xe0000000, 0xe0000000, 0xe0000000, 0xe0000000, 0xe0000000, 0x00000000,
+		0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+	}, /* 'I' */
+	[0x4a - FONT_START_CHAR] = {
+		0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00600000, 0x00600000,
+		0x00600000, 0x00600000, 0x00600000, 0x00600000, 0x00600000, 0x00600000, 0x00600000, 0x00600000,
+		0x00600000, 0x00600000, 0x20600000, 0xe0e00000, 0x71e00000, 0x3fc00000, 0x1f800000, 0x00000000,
+		0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+	}, /* 'J' */
+	[0x4b - FONT_START_CHAR] = {
+		0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xc0780000, 0xc0f00000,
+		0xc1e00000, 0xc1c00000, 0xc3800000, 0xc7000000, 0xce000000, 0xde000000, 0xff000000, 0xff000000,
+		0xf3800000, 0xe1c00000, 0xc1c00000, 0xc0e00000, 0xc0700000, 0xc0700000, 0xc0380000, 0x00000000,
+		0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+	}, /* 'K' */
+	[0x4c - FONT_START_CHAR] = {
+		0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xc0000000, 0xc0000000,
+		0xc0000000, 0xc0000000, 0xc0000000, 0xc0000000, 0xc0000000, 0xc0000000, 0xc0000000, 0xc0000000,
+		0xc0000000, 0xc0000000, 0xc0000000, 0xc0000000, 0xc0000000, 0xffc00000, 0xffc00000, 0x00000000,
+		0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+	}, /* 'L' */
+	[0x4d - FONT_START_CHAR] = {
+		0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xf003c000, 0xf007c000,
+		0xf007c000, 0xf807c000, 0xd80fc000, 0xdc0dc000, 0xdc1dc000, 0xcc1dc000, 0xce19c000, 0xc639c000,
+		0xc731c000, 0xc771c000, 0xc371c000, 0xc3e1c000, 0xc1e1c000, 0xc1c1c000, 0xc1c1c000, 0x00000000,
+		0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+	}, /* 'M' */
+	[0x4e - FONT_START_CHAR] = {
+		0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xe0180000, 0xf0180000,
+		0xf8180000, 0xf8180000, 0xdc180000, 0xcc180000, 0xce180000, 0xc7180000, 0xc7180000, 0xc3980000,
+		0xc1d80000, 0xc1d80000, 0xc0f80000, 0xc0780000, 0xc0780000, 0xc0380000, 0xc0180000, 0x00000000,
+		0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+	}, /* 'N' */
+	[0x4f - FONT_START_CHAR] = {
+		0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00c00000, 0x0ff80000,
+		0x1ffe0000, 0x3c1f0000, 0x78070000, 0x70038000, 0xe0038000, 0xe001c000, 0xe001c000, 0xe001c000,
+		0xe001c000, 0xe0018000, 0xe0038000, 0x70038000, 0x78070000, 0x3e1e0000, 0x1ffc0000, 0x07f80000,
+		0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+	}, /* 'O' */
+	[0x50 - FONT_START_CHAR] = {
+		0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xff800000, 0xffc00000,
+		0xc1e00000, 0xc0e00000, 0xc0700000, 0xc0700000, 0xc0700000, 0xc0e00000, 0xc1e00000, 0xffc00000,
+		0xff000000, 0xc0000000, 0xc0000000, 0xc0000000, 0xc0000000, 0xc0000000, 0xc0000000, 0x00000000,
+		0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+	}, /* 'P' */
+	[0x51 - FONT_START_CHAR] = {
+		0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00c00000, 0x0ff80000,
+		0x1ffe0000, 0x3c1f0000, 0x78070000, 0x70038000, 0xe0038000, 0xe001c000, 0xe001c000, 0xe001c000,
+		0xe001c000, 0xe0018000, 0xe0338000, 0x703b8000, 0x781f0000, 0x3e1e0000, 0x1ffe0000, 0x07ff0000,
+		0x00070000, 0x00020000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+	}, /* 'Q' */
+	[0x52 - FONT_START_CHAR] = {
+		0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xff800000, 0xffc00000,
+		0xc1e00000, 0xc0e00000, 0xc0700000, 0xc0700000, 0xc0600000, 0xc0e00000, 0xffc00000, 0xff800000,
+		0xc7000000, 0xc3800000, 0xc3800000, 0xc1c00000, 0xc0e00000, 0xc0e00000, 0xc0700000, 0x00000000,
+		0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+	}, /* 'R' */
+	[0x53 - FONT_START_CHAR] = {
+		0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x06000000, 0x3f800000,
+		0x7fc00000, 0x70e00000, 0xe0400000, 0xe0000000, 0xf0000000, 0x7c000000, 0x3f000000, 0x0fc00000,
+		0x03e00000, 0x00e00000, 0x00700000, 0xc0700000, 0xe0700000, 0xf0e00000, 0x7fe00000, 0x3f800000,
+		0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+	}, /* 'S' */
+	[0x54 - FONT_START_CHAR] = {
+		0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xfff00000, 0xfff00000,
+		0x0e000000, 0x0e000000, 0x0e000000, 0x0e000000, 0x0e000000, 0x0e000000, 0x0e000000, 0x0e000000,
+		0x0e000000, 0x0e000000, 0x0e000000, 0x0e000000, 0x0e000000, 0x0e000000, 0x0e000000, 0x00000000,
+		0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+	}, /* 'T' */
+	[0x55 - FONT_START_CHAR] = {
+		0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xe01c0000, 0xe01c0000,
+		0xe01c0000, 0xe01c0000, 0xe01c0000, 0xe01c0000, 0xe01c0000, 0xe01c0000, 0xe01c0000, 0xe01c0000,
+		0xe01c0000, 0xe01c0000, 0x60180000, 0x70380000, 0x78780000, 0x3ff00000, 0x1fe00000, 0x00000000,
+		0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+	}, /* 'U' */
+	[0x56 - FONT_START_CHAR] = {
+		0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xe00e0000, 0x700e0000,
+		0x700c0000, 0x301c0000, 0x381c0000, 0x38180000, 0x18380000, 0x1c380000, 0x1c700000, 0x0c700000,
+		0x0e600000, 0x0ee00000, 0x06e00000, 0x07c00000, 0x03c00000, 0x03c00000, 0x03800000, 0x00000000,
+		0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+	}, /* 'V' */
+	[0x57 - FONT_START_CHAR] = {
+		0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xe0380e00, 0x70380c00,
+		0x703c1c00, 0x707c1c00, 0x306c1c00, 0x386e1800, 0x38ee3800, 0x38e63800, 0x18c63000, 0x1dc73000,
+		0x1dc37000, 0x0d837000, 0x0d83e000, 0x0f81e000, 0x0f01e000, 0x0701e000, 0x0701c000, 0x00000000,
+		0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+	}, /* 'W' */
+	[0x58 - FONT_START_CHAR] = {
+		0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x701e0000, 0x381c0000,
+		0x38380000, 0x1c700000, 0x0e700000, 0x0ee00000, 0x07c00000, 0x03c00000, 0x03c00000, 0x07c00000,
+		0x07e00000, 0x0e700000, 0x1c700000, 0x1c380000, 0x381c0000, 0x701c0000, 0xf00e0000, 0x00000000,
+		0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+	}, /* 'X' */
+	[0x59 - FONT_START_CHAR] = {
+		0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xf01e0000, 0x701c0000,
+		0x38380000, 0x1c700000, 0x1c700000, 0x0ee00000, 0x0ec00000, 0x07c00000, 0x03800000, 0x03800000,
+		0x03800000, 0x03800000, 0x03800000, 0x03800000, 0x03800000, 0x03800000, 0x03800000, 0x00000000,
+		0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+	}, /* 'Y' */
+	[0x5a - FONT_START_CHAR] = {
+		0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xfff00000, 0xfff00000,
+		0x00f00000, 0x00e00000, 0x01c00000, 0x03c00000, 0x03800000, 0x07000000, 0x0e000000, 0x1e000000,
+		0x1c000000, 0x38000000, 0x78000000, 0x70000000, 0xe0000000, 0xfff00000, 0xfff00000, 0x00000000,
+		0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+	}, /* 'Z' */
+	[0x5b - FONT_START_CHAR] = {
+		0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xfc000000, 0xfc000000, 0xe0000000, 0xe0000000,
+		0xe0000000, 0xe0000000, 0xe0000000, 0xe0000000, 0xe0000000, 0xe0000000, 0xe0000000, 0xe0000000,
+		0xe0000000, 0xe0000000, 0xe0000000, 0xe0000000, 0xe0000000, 0xe0000000, 0xe0000000, 0xe0000000,
+		0xfc000000, 0xfc000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+	}, /* '[' */
+	[0x5c - FONT_START_CHAR] = {
+		0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xe0000000, 0x60000000,
+		0x60000000, 0x70000000, 0x30000000, 0x30000000, 0x38000000, 0x18000000, 0x18000000, 0x1c000000,
+		0x0c000000, 0x0c000000, 0x0e000000, 0x0e000000, 0x06000000, 0x07000000, 0x07000000, 0x00000000,
+		0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+	}, /* '\\' */
+	[0x5d - FONT_START_CHAR] = {
+		0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xf8000000, 0xf8000000, 0x38000000, 0x38000000,
+		0x38000000, 0x38000000, 0x38000000, 0x38000000, 0x38000000, 0x38000000, 0x38000000, 0x38000000,
+		0x38000000, 0x38000000, 0x38000000, 0x38000000, 0x38000000, 0x38000000, 0x38000000, 0x38000000,
+		0xf8000000, 0xf8000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+	}, /* ']' */
+	[0x5e - FONT_START_CHAR] = {
+		0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x0e000000, 0x0f000000,
+		0x1f000000, 0x1b800000, 0x31c00000, 0x70c00000, 0xe0e00000, 0x00000000, 0x00000000, 0x00000000,
+		0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+		0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+	}, /* '^' */
+	[0x5f - FONT_START_CHAR] = {
+		0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+		0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+		0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+		0x00000000, 0x00000000, 0xfff00000, 0xfff00000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+	}, /* '_' */
+	[0x60 - FONT_START_CHAR] = {
+		0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xe0000000, 0x70000000,
+		0x30000000, 0x30000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+		0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+		0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+	}, /* '`' */
+	[0x61 - FONT_START_CHAR] = {
+		0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+		0x00000000, 0x00000000, 0x00000000, 0x0e000000, 0x7f800000, 0xf3c00000, 0x40e00000, 0x00e00000,
+		0x1ee00000, 0x7fe00000, 0xe0e00000, 0xc0e00000, 0xc0e00000, 0xe1e00000, 0xffe00000, 0x7ee00000,
+		0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+	}, /* 'a' */
+	[0x62 - FONT_START_CHAR] = {
+		0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xe0000000, 0xe0000000,
+		0xe0000000, 0xe0000000, 0xe3800000, 0xefe00000, 0xfff00000, 0xf0700000, 0xf0380000, 0xe0380000,
+		0xe0380000, 0xe0380000, 0xe0380000, 0xf0380000, 0xf8700000, 0xffe00000, 0xefc00000, 0x00000000,
+		0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+	}, /* 'b' */
+	[0x63 - FONT_START_CHAR] = {
+		0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+		0x00000000, 0x00000000, 0x00000000, 0x07000000, 0x3fc00000, 0x7fe00000, 0x70700000, 0xe0400000,
+		0xc0000000, 0xc0000000, 0xc0000000, 0xe0000000, 0xe0700000, 0x70e00000, 0x3fe00000, 0x1f800000,
+		0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+	}, /* 'c' */
+	[0x64 - FONT_START_CHAR] = {
+		0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00300000, 0x00300000,
+		0x00300000, 0x00300000, 0x0e300000, 0x3fb00000, 0x7ff00000, 0x70f00000, 0xe0700000, 0xc0300000,
+		0xc0300000, 0xc0300000, 0xe0300000, 0xe0700000, 0x70f00000, 0x7ff00000, 0x1fb00000, 0x00000000,
+		0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+	}, /* 'd' */
+	[0x65 - FONT_START_CHAR] = {
+		0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+		0x00000000, 0x00000000, 0x00000000, 0x0f000000, 0x3fc00000, 0x7fe00000, 0x70e00000, 0xe0700000,
+		0xc0700000, 0xfff00000, 0xc0000000, 0xe0000000, 0xe0400000, 0x70700000, 0x7fe00000, 0x1fc00000,
+		0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+	}, /* 'e' */
+	[0x66 - FONT_START_CHAR] = {
+		0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x06000000, 0x1f000000,
+		0x3f000000, 0x38000000, 0x30000000, 0x30000000, 0xfe000000, 0xfe000000, 0x30000000, 0x30000000,
+		0x30000000, 0x30000000, 0x30000000, 0x30000000, 0x30000000, 0x30000000, 0x30000000, 0x30000000,
+		0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+	}, /* 'f' */
+	[0x67 - FONT_START_CHAR] = {
+		0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+		0x00000000, 0x00000000, 0x00000000, 0x0e000000, 0x3fb00000, 0x7ff00000, 0xf0f00000, 0xe0700000,
+		0xc0300000, 0xc0300000, 0xc0300000, 0xe0700000, 0xe0700000, 0x70f00000, 0x7fb00000, 0x1f300000,
+		0x00300000, 0x20700000, 0xf0700000, 0x7fe00000, 0x3fc00000, 0x06000000, 0x00000000, 0x00000000,
+	}, /* 'g' */
+	[0x68 - FONT_START_CHAR] = {
+		0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xe0000000, 0xe0000000,
+		0xe0000000, 0xe0000000, 0xe3800000, 0xefc00000, 0xffe00000, 0xf0e00000, 0xe0700000, 0xe0700000,
+		0xe0700000, 0xe0700000, 0xe0700000, 0xe0700000, 0xe0700000, 0xe0700000, 0xe0700000, 0x00000000,
+		0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+	}, /* 'h' */
+	[0x69 - FONT_START_CHAR] = {
+		0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x60000000, 0xf0000000,
+		0xe0000000, 0x00000000, 0x00000000, 0x00000000, 0x60000000, 0x60000000, 0x60000000, 0x60000000,
+		0x60000000, 0x60000000, 0x60000000, 0x60000000, 0x60000000, 0x60000000, 0x60000000, 0x60000000,
+		0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+	}, /* 'i' */
+	[0x6a - FONT_START_CHAR] = {
+		0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x30000000, 0x78000000,
+		0x70000000, 0x00000000, 0x00000000, 0x00000000, 0x30000000, 0x30000000, 0x30000000, 0x30000000,
+		0x30000000, 0x30000000, 0x30000000, 0x30000000, 0x30000000, 0x30000000, 0x30000000, 0x30000000,
+		0x30000000, 0x30000000, 0x70000000, 0xf0000000, 0xe0000000, 0x80000000, 0x00000000, 0x00000000,
+	}, /* 'j' */
+	[0x6b - FONT_START_CHAR] = {
+		0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xe0000000, 0xe0000000,
+		0xe0000000, 0xe0000000, 0xe0100000, 0xe0e00000, 0xe1c00000, 0xe3800000, 0xe7000000, 0xee000000,
+		0xff000000, 0xff000000, 0xf3800000, 0xe3c00000, 0xe1c00000, 0xe0e00000, 0xe0f00000, 0x00000000,
+		0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+	}, /* 'k' */
+	[0x6c - FONT_START_CHAR] = {
+		0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xe0000000, 0xe0000000,
+		0xe0000000, 0xe0000000, 0xe0000000, 0xe0000000, 0xe0000000, 0xe0000000, 0xe0000000, 0xe0000000,
+		0xe0000000, 0xe0000000, 0xe0000000, 0xe0000000, 0xe0000000, 0xe0000000, 0xe0000000, 0x00000000,
+		0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+	}, /* 'l' */
+	[0x6d - FONT_START_CHAR] = {
+		0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+		0x00000000, 0x00000000, 0x00000000, 0x03030000, 0xefcfc000, 0xffffe000, 0xf0f0e000, 0xe0e06000,
+		0xe0606000, 0xe0606000, 0xe0606000, 0xe0606000, 0xe0606000, 0xe0606000, 0xe0606000, 0xe0606000,
+		0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+	}, /* 'm' */
+	[0x6e - FONT_START_CHAR] = {
+		0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+		0x00000000, 0x00000000, 0x00000000, 0x03800000, 0xefc00000, 0xffe00000, 0xf0e00000, 0xe0700000,
+		0xe0700000, 0xe0700000, 0xe0700000, 0xe0700000, 0xe0700000, 0xe0700000, 0xe0700000, 0xe0700000,
+		0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+	}, /* 'n' */
+	[0x6f - FONT_START_CHAR] = {
+		0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+		0x00000000, 0x00000000, 0x00000000, 0x07000000, 0x3fc00000, 0x7fe00000, 0x70700000, 0xe0300000,
+		0xe0380000, 0xc0380000, 0xc0380000, 0xe0380000, 0xe0700000, 0x70f00000, 0x3fe00000, 0x1fc00000,
+		0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+	}, /* 'o' */
+	[0x70 - FONT_START_CHAR] = {
+		0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+		0x00000000, 0x00000000, 0x00000000, 0x03800000, 0xefe00000, 0xfff00000, 0xf0700000, 0xf0380000,
+		0xe0380000, 0xe0380000, 0xe0380000, 0xe0380000, 0xf0380000, 0xf8700000, 0xffe00000, 0xefc00000,
+		0xe0000000, 0xe0000000, 0xe0000000, 0xe0000000, 0xe0000000, 0x00000000, 0x00000000, 0x00000000,
+	}, /* 'p' */
+	[0x71 - FONT_START_CHAR] = {
+		0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+		0x00000000, 0x00000000, 0x00000000, 0x0e000000, 0x3fb00000, 0x7ff00000, 0x70f00000, 0xe0700000,
+		0xc0300000, 0xc0300000, 0xc0300000, 0xe0300000, 0xe0700000, 0x70f00000, 0x7ff00000, 0x1fb00000,
+		0x00300000, 0x00300000, 0x00300000, 0x00300000, 0x00300000, 0x00000000, 0x00000000, 0x00000000,
+	}, /* 'q' */
+	[0x72 - FONT_START_CHAR] = {
+		0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+		0x00000000, 0x00000000, 0x00000000, 0x07000000, 0xef000000, 0xff000000, 0xf0000000, 0xe0000000,
+		0xe0000000, 0xe0000000, 0xe0000000, 0xe0000000, 0xe0000000, 0xe0000000, 0xe0000000, 0xe0000000,
+		0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+	}, /* 'r' */
+	[0x73 - FONT_START_CHAR] = {
+		0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+		0x00000000, 0x00000000, 0x00000000, 0x1c000000, 0x7f800000, 0xf3c00000, 0xe1800000, 0xe0000000,
+		0xf8000000, 0x7f000000, 0x1f800000, 0x01c00000, 0x41c00000, 0xe1c00000, 0xff800000, 0x7f000000,
+		0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+	}, /* 's' */
+	[0x74 - FONT_START_CHAR] = {
+		0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+		0x30000000, 0x30000000, 0x30000000, 0x30000000, 0xfe000000, 0xfe000000, 0x30000000, 0x30000000,
+		0x30000000, 0x30000000, 0x30000000, 0x30000000, 0x30000000, 0x30000000, 0x3e000000, 0x1e000000,
+		0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+	}, /* 't' */
+	[0x75 - FONT_START_CHAR] = {
+		0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+		0x00000000, 0x00000000, 0x00000000, 0xe0600000, 0xe0600000, 0xe0600000, 0xe0600000, 0xe0600000,
+		0xe0600000, 0xe0600000, 0xe0600000, 0xe0e00000, 0x70e00000, 0x7fe00000, 0x3f600000, 0x00000000,
+		0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+	}, /* 'u' */
+	[0x76 - FONT_START_CHAR] = {
+		0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+		0x00000000, 0x00000000, 0x00000000, 0xe0380000, 0x60700000, 0x70700000, 0x30600000, 0x38e00000,
+		0x38c00000, 0x19c00000, 0x1d800000, 0x0d800000, 0x0f800000, 0x0f000000, 0x07000000, 0x00000000,
+		0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+	}, /* 'v' */
+	[0x77 - FONT_START_CHAR] = {
+		0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+		0x00000000, 0x00000000, 0x00000000, 0xe0e0e000, 0x60e0c000, 0x71f1c000, 0x71b1c000, 0x31b18000,
+		0x33b98000, 0x3b1b8000, 0x1b1b0000, 0x1b1b0000, 0x1e0f0000, 0x0e0e0000, 0x0e0e0000, 0x00000000,
+		0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+	}, /* 'w' */
+	[0x78 - FONT_START_CHAR] = {
+		0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+		0x00000000, 0x00000000, 0x00000000, 0xf0700000, 0x70e00000, 0x39c00000, 0x1d800000, 0x0f800000,
+		0x0f000000, 0x0f000000, 0x1f800000, 0x19800000, 0x39c00000, 0x70e00000, 0xe0700000, 0x00000000,
+		0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+	}, /* 'x' */
+	[0x79 - FONT_START_CHAR] = {
+		0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+		0x00000000, 0x00000000, 0x00000000, 0xe0380000, 0x70700000, 0x70600000, 0x30e00000, 0x38e00000,
+		0x18c00000, 0x1dc00000, 0x0d800000, 0x0f800000, 0x0f000000, 0x07000000, 0x07000000, 0x06000000,
+		0x0e000000, 0x0c000000, 0x1c000000, 0x38000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+	}, /* 'y' */
+	[0x7a - FONT_START_CHAR] = {
+		0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+		0x00000000, 0x00000000, 0x00000000, 0xffc00000, 0xffc00000, 0x03800000, 0x07000000, 0x0e000000,
+		0x0e000000, 0x1c000000, 0x38000000, 0x70000000, 0xe0000000, 0xffc00000, 0xffc00000, 0x00000000,
+		0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+	}, /* 'z' */
+	[0x7b - FONT_START_CHAR] = {
+		0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x0e000000, 0x1e000000, 0x38000000, 0x38000000,
+		0x38000000, 0x38000000, 0x38000000, 0x38000000, 0x38000000, 0x30000000, 0xf0000000, 0xf0000000,
+		0x30000000, 0x38000000, 0x38000000, 0x38000000, 0x38000000, 0x38000000, 0x38000000, 0x38000000,
+		0x1e000000, 0x0e000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+	}, /* '{' */
+	[0x7c - FONT_START_CHAR] = {
+		0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xc0000000, 0xc0000000, 0xc0000000,
+		0xc0000000, 0xc0000000, 0xc0000000, 0xc0000000, 0xc0000000, 0xc0000000, 0xc0000000, 0xc0000000,
+		0xc0000000, 0xc0000000, 0xc0000000, 0xc0000000, 0xc0000000, 0xc0000000, 0xc0000000, 0xc0000000,
+		0xc0000000, 0xc0000000, 0xc0000000, 0xc0000000, 0xc0000000, 0x00000000, 0x00000000, 0x00000000,
+	}, /* '|' */
+	[0x7d - FONT_START_CHAR] = {
+		0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xe0000000, 0xf0000000, 0x70000000, 0x30000000,
+		0x30000000, 0x30000000, 0x30000000, 0x30000000, 0x30000000, 0x38000000, 0x1c000000, 0x1c000000,
+		0x38000000, 0x30000000, 0x30000000, 0x30000000, 0x30000000, 0x30000000, 0x30000000, 0x70000000,
+		0xf0000000, 0xc0000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+	}, /* '}' */
+	[0x7e - FONT_START_CHAR] = {
+		0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+		0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x7e700000, 0xffe00000,
+		0xc3e00000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+		0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+	}, /* '~' */
+};
+
+const uint8_t font_widths[FONT_NUM_CHARS] = {
+	[0x20 - FONT_START_CHAR] = 8,
+	[0x21 - FONT_START_CHAR] = 4,
+	[0x22 - FONT_START_CHAR] = 6,
+	[0x23 - FONT_START_CHAR] = 14,
+	[0x24 - FONT_START_CHAR] = 12,
+	[0x25 - FONT_START_CHAR] = 19,
+	[0x26 - FONT_START_CHAR] = 14,
+	[0x27 - FONT_START_CHAR] = 3,
+	[0x28 - FONT_START_CHAR] = 7,
+	[0x29 - FONT_START_CHAR] = 7,
+	[0x2a - FONT_START_CHAR] = 9,
+	[0x2b - FONT_START_CHAR] = 11,
+	[0x2c - FONT_START_CHAR] = 4,
+	[0x2d - FONT_START_CHAR] = 8,
+	[0x2e - FONT_START_CHAR] = 4,
+	[0x2f - FONT_START_CHAR] = 8,
+	[0x30 - FONT_START_CHAR] = 13,
+	[0x31 - FONT_START_CHAR] = 6,
+	[0x32 - FONT_START_CHAR] = 11,
+	[0x33 - FONT_START_CHAR] = 11,
+	[0x34 - FONT_START_CHAR] = 12,
+	[0x35 - FONT_START_CHAR] = 12,
+	[0x36 - FONT_START_CHAR] = 12,
+	[0x37 - FONT_START_CHAR] = 11,
+	[0x38 - FONT_START_CHAR] = 12,
+	[0x39 - FONT_START_CHAR] = 12,
+	[0x3a - FONT_START_CHAR] = 4,
+	[0x3b - FONT_START_CHAR] = 4,
+	[0x3c - FONT_START_CHAR] = 11,
+	[0x3d - FONT_START_CHAR] = 11,
+	[0x3e - FONT_START_CHAR] = 10,
+	[0x3f - FONT_START_CHAR] = 10,
+	[0x40 - FONT_START_CHAR] = 19,
+	[0x41 - FONT_START_CHAR] = 16,
+	[0x42 - FONT_START_CHAR] = 12,
+	[0x43 - FONT_START_CHAR] = 15,
+	[0x44 - FONT_START_CHAR] = 14,
+	[0x45 - FONT_START_CHAR] = 10,
+	[0x46 - FONT_START_CHAR] = 10,
+	[0x47 - FONT_START_CHAR] = 17,
+	[0x48 - FONT_START_CHAR] = 13,
+	[0x49 - FONT_START_CHAR] = 3,
+	[0x4a - FONT_START_CHAR] = 11,
+	[0x4b - FONT_START_CHAR] = 13,
+	[0x4c - FONT_START_CHAR] = 10,
+	[0x4d - FONT_START_CHAR] = 18,
+	[0x4e - FONT_START_CHAR] = 13,
+	[0x4f - FONT_START_CHAR] = 18,
+	[0x50 - FONT_START_CHAR] = 12,
+	[0x51 - FONT_START_CHAR] = 18,
+	[0x52 - FONT_START_CHAR] = 12,
+	[0x53 - FONT_START_CHAR] = 12,
+	[0x54 - FONT_START_CHAR] = 12,
+	[0x55 - FONT_START_CHAR] = 14,
+	[0x56 - FONT_START_CHAR] = 15,
+	[0x57 - FONT_START_CHAR] = 23,
+	[0x58 - FONT_START_CHAR] = 15,
+	[0x59 - FONT_START_CHAR] = 15,
+	[0x5a - FONT_START_CHAR] = 12,
+	[0x5b - FONT_START_CHAR] = 6,
+	[0x5c - FONT_START_CHAR] = 8,
+	[0x5d - FONT_START_CHAR] = 5,
+	[0x5e - FONT_START_CHAR] = 11,
+	[0x5f - FONT_START_CHAR] = 12,
+	[0x60 - FONT_START_CHAR] = 4,
+	[0x61 - FONT_START_CHAR] = 11,
+	[0x62 - FONT_START_CHAR] = 13,
+	[0x63 - FONT_START_CHAR] = 12,
+	[0x64 - FONT_START_CHAR] = 12,
+	[0x65 - FONT_START_CHAR] = 12,
+	[0x66 - FONT_START_CHAR] = 8,
+	[0x67 - FONT_START_CHAR] = 12,
+	[0x68 - FONT_START_CHAR] = 12,
+	[0x69 - FONT_START_CHAR] = 4,
+	[0x6a - FONT_START_CHAR] = 5,
+	[0x6b - FONT_START_CHAR] = 12,
+	[0x6c - FONT_START_CHAR] = 3,
+	[0x6d - FONT_START_CHAR] = 19,
+	[0x6e - FONT_START_CHAR] = 12,
+	[0x6f - FONT_START_CHAR] = 13,
+	[0x70 - FONT_START_CHAR] = 13,
+	[0x71 - FONT_START_CHAR] = 12,
+	[0x72 - FONT_START_CHAR] = 8,
+	[0x73 - FONT_START_CHAR] = 10,
+	[0x74 - FONT_START_CHAR] = 7,
+	[0x75 - FONT_START_CHAR] = 11,
+	[0x76 - FONT_START_CHAR] = 13,
+	[0x77 - FONT_START_CHAR] = 19,
+	[0x78 - FONT_START_CHAR] = 12,
+	[0x79 - FONT_START_CHAR] = 13,
+	[0x7a - FONT_START_CHAR] = 10,
+	[0x7b - FONT_START_CHAR] = 7,
+	[0x7c - FONT_START_CHAR] = 2,
+	[0x7d - FONT_START_CHAR] = 6,
+	[0x7e - FONT_START_CHAR] = 12,
+};
diff --git a/src/lib/fonts/fonts.h b/src/lib/fonts/fonts.h
new file mode 100644
index 0000000000..3317e012ba
--- /dev/null
+++ b/src/lib/fonts/fonts.h
@@ -0,0 +1,16 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#ifndef __FONTS_H__
+#define __FONTS_H__
+
+#include <types.h>
+
+/* Printable ASCII character range [32-126] */
+#define FONT_START_CHAR  32   /* ASCII Space */
+#define FONT_END_CHAR    126  /* ASCII ~ */
+#define FONT_NUM_CHARS  (FONT_END_CHAR - FONT_START_CHAR + 1)
+
+extern const uint32_t font_table[FONT_NUM_CHARS][CONFIG_FONT_HEIGHT];
+extern const uint8_t font_widths[];
+
+#endif // __FONTS_H__
diff --git a/src/lib/render_text.c b/src/lib/render_text.c
new file mode 100644
index 0000000000..da2aef1d3d
--- /dev/null
+++ b/src/lib/render_text.c
@@ -0,0 +1,210 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <bootsplash.h>
+#include <console/console.h>
+#include <stdlib.h>
+
+#include "fonts/fonts.h"
+#include "render_bmp.h"
+
+/* Maps an unsigned character to the font table index */
+static const uint32_t *get_glyph_data(unsigned char c)
+{
+	/* Range check using macros generated by Python */
+	if (c < FONT_START_CHAR || c > FONT_END_CHAR)
+		return font_table[0]; /* Default to space character */
+
+	return font_table[c - FONT_START_CHAR];
+}
+
+/* Retrieves the pre-calculated width for a character */
+static uint8_t get_glyph_width(unsigned char c)
+{
+	if (c < FONT_START_CHAR || c > FONT_END_CHAR)
+		return font_widths[0];
+
+	return font_widths[c - FONT_START_CHAR];
+}
+
+/*
+ * Maps local glyph coordinates to physical framebuffer coordinates
+ * based on the panel's physical orientation.
+ */
+static inline void get_rotated_text_coords(struct logo_config *config,
+		uint32_t x, uint32_t y, int row, int col, uint32_t *fb_x, uint32_t *fb_y)
+{
+	switch (config->panel_orientation) {
+	case LB_FB_ORIENTATION_RIGHT_UP:
+		*fb_x = x + (CONFIG_FONT_HEIGHT - 1 - row);
+		*fb_y = y + col;
+		break;
+	case LB_FB_ORIENTATION_LEFT_UP:
+		*fb_x = x + row;
+		*fb_y = y + (CONFIG_FONT_WIDTH - 1 - col);
+		break;
+	case LB_FB_ORIENTATION_BOTTOM_UP:
+		*fb_x = x + (CONFIG_FONT_WIDTH - 1 - col);
+		*fb_y = y + (CONFIG_FONT_HEIGHT - 1 - row);
+		break;
+	default: /* LB_FB_ORIENTATION_NORMAL */
+		*fb_x = x + col;
+		*fb_y = y + row;
+		break;
+	}
+}
+
+/*
+ * Renders a single character to the framebuffer.
+ * @config: Framebuffer and orientation configuration.
+ * @c:      Character to render.
+ * @x, @y:  Starting coordinates in the virtual grid.
+ * @color:  Primary text color.
+ */
+static void draw_char(struct logo_config *config, unsigned char c, uint32_t x, uint32_t y,
+		struct blt_pixel color)
+{
+	size_t pixel_size = sizeof(struct blt_pixel);
+	uint8_t *fb = (uint8_t *)config->framebuffer_base;
+	const uint32_t *glyph = get_glyph_data(c);
+	uint8_t actual_width = get_glyph_width(c);
+
+	for (int row = 0; row < CONFIG_FONT_HEIGHT; row++) {
+		uint32_t row_data = glyph[row];
+
+		for (int col = 0; col < actual_width; col++) {
+			uint32_t mask = (1 << (CONFIG_FONT_HEIGHT - 1));
+			if (row_data & (mask >> col)) {
+				uint32_t fb_x, fb_y;
+				get_rotated_text_coords(config, x, y, row, col, &fb_x, &fb_y);
+
+				if (fb_x < config->horizontal_resolution &&
+						 fb_y < config->vertical_resolution) {
+					struct blt_pixel *pixel = (struct blt_pixel *)
+							(fb + (fb_y * config->bytes_per_scanline) + (fb_x * pixel_size));
+					*pixel = color;
+				}
+			}
+		}
+	}
+}
+
+static bool setup_text_alignment(struct logo_config *config,
+	 enum bootsplash_text_type type, enum fw_splash_horizontal_alignment *halign,
+	 enum fw_splash_vertical_alignment *valign, uint32_t *margin)
+{
+	/* Default to center/center */
+	*halign = FW_SPLASH_HALIGNMENT_CENTER;
+	*valign = FW_SPLASH_VALIGNMENT_CENTER;
+	*margin = 0;
+
+	if (type == BOOTSPLASH_TEXT_CENTER)
+		return true;
+
+	if (type != BOOTSPLASH_TEXT_FOOTER) {
+		printk(BIOS_ERR, "%s: Invalid text type %d\n", __func__, type);
+		return false;
+	}
+
+	*margin = config->logo_bottom_margin;
+
+	switch (config->panel_orientation) {
+	case LB_FB_ORIENTATION_RIGHT_UP:
+		*halign = FW_SPLASH_HALIGNMENT_LEFT;
+		*valign = FW_SPLASH_VALIGNMENT_CENTER;
+		break;
+	case LB_FB_ORIENTATION_LEFT_UP:
+		*halign = FW_SPLASH_HALIGNMENT_RIGHT;
+		*valign = FW_SPLASH_VALIGNMENT_CENTER;
+		break;
+	case LB_FB_ORIENTATION_BOTTOM_UP:
+		*halign = FW_SPLASH_HALIGNMENT_CENTER;
+		*valign = FW_SPLASH_VALIGNMENT_TOP;
+		break;
+	default: /* LB_FB_ORIENTATION_NORMAL */
+		*halign = FW_SPLASH_HALIGNMENT_CENTER;
+		*valign = FW_SPLASH_VALIGNMENT_BOTTOM;
+		break;
+	}
+
+	return true;
+}
+
+/*
+ * Renders a string centered on the screen.
+ * @config: Framebuffer and logo configuration.
+ * @str:    The null-terminated string to render.
+ * @type:   Type of bootsplash text (i.e., enum bootsplash_text_type).
+ */
+void render_text_to_framebuffer(struct logo_config *config, const char *str,
+	enum bootsplash_text_type type)
+{
+	if (!config || !str || config->framebuffer_base == 0)
+		return;
+
+	size_t len = strlen(str);
+	if (len == 0)
+		return;
+
+	const uint32_t kerning = 1;
+	uint32_t total_width = 0;
+
+	for (size_t i = 0; i < len; i++)
+		total_width += get_glyph_width((unsigned char)str[i]) + kerning;
+
+	uint32_t text_w, text_h;
+	enum fw_splash_horizontal_alignment halign;
+	enum fw_splash_vertical_alignment valign;
+	uint32_t margin;
+
+	if (setup_text_alignment(config, type, &halign, &valign, &margin) == false)
+		return;
+
+	if (config->panel_orientation == LB_FB_ORIENTATION_LEFT_UP ||
+			 config->panel_orientation == LB_FB_ORIENTATION_RIGHT_UP) {
+		text_w = CONFIG_FONT_HEIGHT;
+		text_h = total_width;
+	} else {
+		text_w = total_width;
+		text_h = CONFIG_FONT_HEIGHT;
+	}
+
+	struct logo_coordinates coords = calculate_logo_coordinates(config->horizontal_resolution,
+				 config->vertical_resolution, text_w, text_h, halign, valign);
+
+	switch (config->panel_orientation) {
+	case LB_FB_ORIENTATION_RIGHT_UP:
+		coords.x += margin;
+		break;
+	case LB_FB_ORIENTATION_LEFT_UP:
+		coords.x -= margin;
+		coords.y += total_width;
+		break;
+	case LB_FB_ORIENTATION_BOTTOM_UP:
+		coords.x += total_width;
+		coords.y += margin;
+		break;
+	default: /* LB_FB_ORIENTATION_NORMAL (default) */
+		coords.y -= margin;
+	}
+
+	/* Text Color: White (Default) */
+	struct blt_pixel text_color = { .Red = 0xff, .Green = 0xff, .Blue = 0xff };
+	uint32_t cur_x = coords.x;
+	uint32_t cur_y = coords.y;
+
+	/* Loop through characters and draw them */
+	for (size_t i = 0; i < len; i++) {
+		unsigned char c = (unsigned char)str[i];
+		draw_char(config, c, cur_x, cur_y, text_color);
+
+		uint32_t advance = get_glyph_width(c) + kerning;
+		if (config->panel_orientation == LB_FB_ORIENTATION_RIGHT_UP)
+			cur_y += advance;
+		else if (config->panel_orientation == LB_FB_ORIENTATION_LEFT_UP)
+			cur_y -= advance;
+		else if (config->panel_orientation == LB_FB_ORIENTATION_BOTTOM_UP)
+			cur_x -= advance;
+		else
+			cur_x += advance;
+	}
+}

From c1db700d43b16d4c04cc8353a378797e256c3151 Mon Sep 17 00:00:00 2001
From: Subrata Banik <subratabanik@google.com>
Date: Wed, 4 Feb 2026 20:52:35 +0530
Subject: [PATCH 3333/3886] lib: Integrate splash text rendering into
 low-battery/off-mode boot

Enable rendering of system status messages during the `low-battery`
bootsplash sequence when `FRAMEBUFFER_SPLASH_TEXT` Kconfig is enabled.

This change adds a 32-byte buffer to capture platform-specific text
(such as battery status) and draws it at the footer of the framebuffer
alongside the logo.

TEST=Able to build and boot google/fatcat.

Change-Id: I298804869eb909201a9056b83e4954e223e2b9bb
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91093
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
---
 src/lib/render_bmp.c | 17 +++++++++++++++++
 1 file changed, 17 insertions(+)

diff --git a/src/lib/render_bmp.c b/src/lib/render_bmp.c
index f5dc91221f..81b5876422 100644
--- a/src/lib/render_bmp.c
+++ b/src/lib/render_bmp.c
@@ -10,6 +10,8 @@
 
 #include "render_bmp.h"
 
+#define MAX_SPLASH_TEXT_WIDTH 32
+
 static bool is_bmp_image_valid(struct bmp_image_header *header)
 {
 	/* Check if the BMP Header Signature is valid */
@@ -708,6 +710,13 @@ void render_logo_to_framebuffer(struct logo_config *config)
 		if (load_and_render_logo_to_framebuffer(BOOTSPLASH_LOW_BATTERY, config) != 0) {
 			printk(BIOS_ERR, "%s: Failed to render low-battery logo.\n", __func__);
 		}
+
+		/* Display Text message at the footer of splash screen if supported */
+		if (CONFIG(FRAMEBUFFER_SPLASH_TEXT)) {
+			char msg[MAX_SPLASH_TEXT_WIDTH];
+			if (platform_get_splash_text(BOOTSPLASH_LOW_BATTERY, msg, MAX_SPLASH_TEXT_WIDTH))
+				render_text_to_framebuffer(config, msg, BOOTSPLASH_TEXT_FOOTER);
+		}
 		return;
 	}
 
@@ -718,6 +727,14 @@ void render_logo_to_framebuffer(struct logo_config *config)
 	if (platform_is_off_mode_charging_active()) {
 		if (load_and_render_logo_to_framebuffer(BOOTSPLASH_OFF_MODE_CHARGING, config) != 0)
 			printk(BIOS_ERR, "%s: Failed to render off-mode charging logo.\n", __func__);
+
+		/* Display Text message at the footer of splash screen if supported */
+		if (CONFIG(FRAMEBUFFER_SPLASH_TEXT)) {
+			char msg[MAX_SPLASH_TEXT_WIDTH];
+			if (platform_get_splash_text(BOOTSPLASH_OFF_MODE_CHARGING, msg,
+					 MAX_SPLASH_TEXT_WIDTH))
+				render_text_to_framebuffer(config, msg, BOOTSPLASH_TEXT_FOOTER);
+		}
 		return;
 	}
 

From ce431ac056863ecf4d7a76c362a41c1f0b409ff1 Mon Sep 17 00:00:00 2001
From: Subrata Banik <subratabanik@google.com>
Date: Wed, 4 Feb 2026 21:04:00 +0530
Subject: [PATCH 3334/3886] vc/google/chromeos: Implement splash text for
 low-battery/off-mode boot

This patch adds platform-level support for dynamic splash screen text
rendering on ChromeOS devices. This implementation interfaces with the
ChromeEC to retrieve battery state-of-charge and charging status,
formatting these into human-readable strings during the bootsplash
stage.

TEST=Able to build and boot google/fatcat.

Change-Id: I5dc57d60cd6be0dc9c79668a8b1560d421e4d6cc
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91095
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/vendorcode/google/chromeos/Makefile.mk   |  1 +
 src/vendorcode/google/chromeos/splash_text.c | 41 ++++++++++++++++++++
 2 files changed, 42 insertions(+)
 create mode 100644 src/vendorcode/google/chromeos/splash_text.c

diff --git a/src/vendorcode/google/chromeos/Makefile.mk b/src/vendorcode/google/chromeos/Makefile.mk
index cfb4af45de..644003e603 100644
--- a/src/vendorcode/google/chromeos/Makefile.mk
+++ b/src/vendorcode/google/chromeos/Makefile.mk
@@ -24,6 +24,7 @@ romstage-$(CONFIG_CHROMEOS_DRAM_PART_NUMBER_IN_CBI) += dram_part_num_override.c
 
 ramstage-$(CONFIG_PLATFORM_HAS_LOW_BATTERY_INDICATOR) += battery.c
 ramstage-$(CONFIG_CHROMEOS_FW_SPLASH_SCREEN) += splash.c
+ramstage-$(CONFIG_FRAMEBUFFER_SPLASH_TEXT) += splash_text.c
 ramstage-$(CONFIG_CHROMEOS_PVMFW_CBMEM) += pvmfw_cbmem.c
 
 # Add logo to the cbfs image
diff --git a/src/vendorcode/google/chromeos/splash_text.c b/src/vendorcode/google/chromeos/splash_text.c
new file mode 100644
index 0000000000..bad33f3b49
--- /dev/null
+++ b/src/vendorcode/google/chromeos/splash_text.c
@@ -0,0 +1,41 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <bootsplash.h>
+#include <console/console.h>
+#include <ec/google/chromeec/ec.h>
+#include <stdio.h>
+#include <string.h>
+
+static bool get_battery_status_msg(char *msg, size_t msg_max)
+{
+	uint32_t batt_pct;
+
+	if (google_chromeec_read_batt_state_of_charge(&batt_pct)) {
+		printk(BIOS_WARNING, "Failed to get battery level\n");
+		return false;
+	}
+
+	if (google_chromeec_is_critically_low_on_battery()) {
+		snprintf(msg, msg_max, "%u%%", batt_pct);
+	} else if (google_chromeec_is_charger_present()) {
+		if (batt_pct == 100)
+			snprintf(msg, msg_max, "Charged");
+		else
+			snprintf(msg, msg_max, "Charging: %u%%", batt_pct);
+	}
+
+	return true;
+}
+
+bool platform_get_splash_text(enum bootsplash_type logo_type, char *msg, size_t msg_max)
+{
+	if (!CONFIG(EC_GOOGLE_CHROMEEC) || !msg || msg_max == 0)
+		return false;
+
+	memset(msg, 0, msg_max);
+
+	if (logo_type == BOOTSPLASH_LOW_BATTERY || logo_type == BOOTSPLASH_OFF_MODE_CHARGING)
+		return get_battery_status_msg(msg, msg_max);
+
+	return false;
+}

From d4c3d979178762a742b87c9b2c253efad6276539 Mon Sep 17 00:00:00 2001
From: Subrata Banik <subratabanik@google.com>
Date: Thu, 12 Feb 2026 15:04:24 +0530
Subject: [PATCH 3335/3886] util/font: Transition to 8-bit anti-aliased font
 generation

Update generate_font.py to produce 8-bit alpha maps instead of 1-bit
packed bitmaps. This enables text smoothing (anti-aliasing) during
framebuffer rendering by providing pixel intensity values (0-255).

Key changes:
- Switch PIL image mode from "1" (monochrome) to "L" (8-bit grayscale).
- Change C data type from uint32_t bit-packed rows to uint8_t byte arrays.
- Implement vertical centering logic using font metrics (ascent/descent).
- Add glyph clipping detection and warnings for both width and height.
- Format C output so each source line represents one glyph row.

Change-Id: Iec8a0123456789abcdef0123456789abcdef0123
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91178
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 util/font/generate_font.py | 101 +++++++++++++++++--------------------
 1 file changed, 45 insertions(+), 56 deletions(-)

diff --git a/util/font/generate_font.py b/util/font/generate_font.py
index b301a2e533..81b45b1689 100644
--- a/util/font/generate_font.py
+++ b/util/font/generate_font.py
@@ -2,10 +2,10 @@
 # SPDX-License-Identifier: GPL-2.0-or-later
 
 """
-This utility generates a compressed bitmapped font table from a TTF/OTF file.
+This utility generates an anti-aliased (smoothed) font table from a TTF/OTF file.
 The output is a C source file containing:
 1. Font dimensions and range macros.
-2. A normalized (left-aligned) bitmapped font table.
+2. An 8-bit alpha map font table (0=transparent, 255=opaque).
 3. A character width table for proportional spacing.
 
 Usage:
@@ -26,11 +26,10 @@ def generate_c_table(font_path, canvas_width, canvas_height):
         print(f"Error: Font file '{font_path}' not found.", file=sys.stderr)
         sys.exit(1)
 
-    # Validation: Width must not exceed 32 bits for uint32_t storage
-    if canvas_width > 32:
-        print(f"Error: Requested width ({canvas_width}) exceeds 32-bit capacity. "
-              "The current renderer supports up to 32 pixels wide.", file=sys.stderr)
-        sys.exit(1)
+    # RESTRICTION: Width and Height checks for firmware safety
+    if canvas_width > 64 or canvas_height > 64:
+        print(f"Warning: Large dimensions ({canvas_width}x{canvas_height}) "
+              "will consume significant flash memory.", file=sys.stderr)
 
     # Validation: Basic sanity check for positive dimensions
     if canvas_width <= 0 or canvas_height <= 0:
@@ -39,7 +38,6 @@ def generate_c_table(font_path, canvas_width, canvas_height):
 
     # Use canvas_width as font size to maintain original calculation style
     font_size = canvas_width
-    y_offset = 0
 
     try:
         font = ImageFont.truetype(font_path, font_size)
@@ -47,6 +45,16 @@ def generate_c_table(font_path, canvas_width, canvas_height):
         print(f"Error: Could not open font file '{font_path}'.", file=sys.stderr)
         sys.exit(1)
 
+    # Check for vertical clipping based on font metrics
+    ascent, descent = font.getmetrics()
+    total_font_height = ascent + descent
+    if total_font_height > canvas_height:
+        print(f"Warning: Font vertical size ({total_font_height}px) exceeds "
+              f"canvas height ({canvas_height}px).", file=sys.stderr)
+        y_offset = 0
+    else:
+        y_offset = (canvas_height - total_font_height) // 2
+
     # Header for the generated C file
     print("/* SPDX-License-Identifier: GPL-2.0-or-later */\n")
     print("/*")
@@ -65,72 +73,50 @@ def generate_c_table(font_path, canvas_width, canvas_height):
 
     widths = []
 
-    # Choose data type based on width
-    data_type = "uint32_t"
-    hex_format = "08x" if canvas_width > 16 else "04x"
-    bit_depth = 32 if canvas_width > 16 else 16
+    print(f"const uint8_t font_table[FONT_NUM_CHARS][FONT_HEIGHT * FONT_WIDTH] = {{")
 
-    # 2. Generate packed font table
-    print(f"const {data_type} font_table[FONT_NUM_CHARS][FONT_HEIGHT] = {{")
+    clipped_glyphs = []
 
     for char_code in range(START_CHAR, END_CHAR + 1):
         char = chr(char_code)
-        image = Image.new("1", (canvas_width, canvas_height), 0)
+        image = Image.new("L", (canvas_width, canvas_height), 0)
         draw = ImageDraw.Draw(image)
-        draw.text((0, y_offset), char, font=font, fill=1)
+        draw.text((0, y_offset), char, font=font, fill=255)
 
         pixels = list(image.getdata())
-        rows = []
-        global_mask = 0
+
+        leftmost = canvas_width
+        rightmost = 0
+        has_pixels = False
 
         for y in range(canvas_height):
-            row_val = 0
-            base = y * canvas_width
             for x in range(canvas_width):
-                if pixels[base + x]:
-                    # Map pixels to bits: Leftmost pixel is highest bit
-                    row_val |= (1 << ((canvas_width - 1) - x))
-            rows.append(row_val)
-            global_mask |= row_val
+                if pixels[y * canvas_width + x] > 0:
+                    if x < leftmost: leftmost = x
+                    if x > rightmost: rightmost = x
+                    has_pixels = True
 
-        # Dead space removal / Normalization
-        left_shift = 0
-        actual_width = 0
-
-        if global_mask > 0:
-            # Find the leftmost pixel column
-            leftmost_col = 0
-            for i in range(canvas_width):
-                if (global_mask >> (canvas_width - 1 - i)) & 1:
-                    leftmost_col = i
-                    break
-
-            # Find the rightmost pixel column
-            rightmost_col = 0
-            for i in range(canvas_width):
-                if (global_mask >> i) & 1:
-                    rightmost_col = (canvas_width - 1) - i
-                    break
-
-            # Width is the horizontal span of active pixels
-            actual_width = rightmost_col - leftmost_col + 1
-
-            # left_shift ensures character is left-aligned to MSB of the data type
-            left_shift = (bit_depth - canvas_width) + leftmost_col
+        if has_pixels:
+            actual_width = rightmost - leftmost + 1
+            if actual_width >= canvas_width:
+                clipped_glyphs.append(char)
         else:
             actual_width = canvas_width // 3  # Default width for space
 
         widths.append(actual_width)
 
-        # Pre-shift values to be MSB-aligned and mask based on bit depth
-        mask_val = 0xFFFFFFFF if bit_depth == 32 else 0xFFFF
-        hex_values = [f"0x{(row << left_shift) & mask_val:{hex_format}}" for row in rows]
         char_repr = f"'{char}'" if char not in ["'", "\\"] else f"'\\{char}'"
 
         print(f"\t[0x{char_code:02x} - FONT_START_CHAR] = {{")
-        for i in range(0, len(hex_values), 8):
-            line = ", ".join(hex_values[i:i+8])
-            print(f"\t\t{line},")
+
+        # Format with line breaks every 8 entries
+        for i in range(0, len(pixels), canvas_width):
+            row = pixels[i : i + canvas_width]
+            for j in range(0, len(row), 8):
+                chunk = row[j : j + 8]
+                line = ", ".join([f"0x{p:02x}" for p in chunk])
+                print(f"\t\t{line},")
+
         print(f"\t}}, /* {char_repr} */")
 
     print("};\n")
@@ -142,8 +128,11 @@ def generate_c_table(font_path, canvas_width, canvas_height):
         print(f"\t[0x{char_code:02x} - FONT_START_CHAR] = {w},")
     print("};")
 
+    if clipped_glyphs:
+        print(f"/* Warning: Characters clipped: {' '.join(clipped_glyphs)} */", file=sys.stderr)
+
 if __name__ == "__main__":
-    parser = argparse.ArgumentParser(description="Generate bitmapped font table.")
+    parser = argparse.ArgumentParser(description="Generate anti-aliased font table.")
     parser.add_argument("font_path", help="Path to TTF/OTF font file")
     parser.add_argument("--width", type=int, default=24, help="Canvas width (default: 24)")
     parser.add_argument("--height", type=int, default=32, help="Canvas height (default: 32)")

From 5ea25c7ca2e926af762574986131142d3e45b431 Mon Sep 17 00:00:00 2001
From: Subrata Banik <subratabanik@google.com>
Date: Thu, 12 Feb 2026 16:49:42 +0530
Subject: [PATCH 3336/3886] lib: Implement anti-aliased text rendering

Transition the bootsplash text renderer from 1-bit monochrome bitmaps
to 8-bit alpha maps to support text smoothing (anti-aliasing).

Key changes:
- Update fonts.h to declare font_table as a 2D uint8_t array containing
  alpha intensity values (0-255) for each pixel.
- Update draw_char() to perform alpha blending by mixing the text color
  with the existing background pixel using the formula:
  Result = (Color * Alpha + BG * (255 - Alpha)) / 255.
- Regenerate the font table data to reflect the new 8-bit format and
  updated character widths.

Change-Id: I9d4dde74d86fd552b30523f3b8ff34fb8fdba782
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91179
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
---
 ...font_table_google_sans_flex_medium_24x32.c | 9634 ++++++++++++++++-
 src/lib/fonts/fonts.h                         |    4 +-
 src/lib/render_text.c                         |   40 +-
 3 files changed, 9215 insertions(+), 463 deletions(-)

diff --git a/src/lib/fonts/font_table_google_sans_flex_medium_24x32.c b/src/lib/fonts/font_table_google_sans_flex_medium_24x32.c
index 7b211698bc..421292e171 100644
--- a/src/lib/fonts/font_table_google_sans_flex_medium_24x32.c
+++ b/src/lib/fonts/font_table_google_sans_flex_medium_24x32.c
@@ -14,673 +14,9413 @@
 #define FONT_END_CHAR   126
 #define FONT_NUM_CHARS  (FONT_END_CHAR - FONT_START_CHAR + 1)
 
-const uint32_t font_table[FONT_NUM_CHARS][FONT_HEIGHT] = {
+const uint8_t font_table[FONT_NUM_CHARS][FONT_HEIGHT * FONT_WIDTH] = {
 	[0x20 - FONT_START_CHAR] = {
-		0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-		0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-		0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-		0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 	}, /* ' ' */
 	[0x21 - FONT_START_CHAR] = {
-		0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x60000000, 0x60000000,
-		0x60000000, 0x60000000, 0x60000000, 0x60000000, 0x60000000, 0x60000000, 0x60000000, 0x60000000,
-		0x60000000, 0x60000000, 0x00000000, 0x00000000, 0x60000000, 0xf0000000, 0x60000000, 0x00000000,
-		0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x0f, 0x30, 0x30, 0x11, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x4c, 0xff, 0xff, 0x57, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x46, 0xff, 0xff, 0x50, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x3f, 0xff, 0xff, 0x4a, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x39, 0xff, 0xff, 0x42, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x32, 0xff, 0xff, 0x3b, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x2d, 0xff, 0xff, 0x34, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x26, 0xff, 0xff, 0x2e, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x20, 0xff, 0xff, 0x26, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x1a, 0xff, 0xff, 0x1f, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x13, 0xff, 0xff, 0x18, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x0d, 0xff, 0xff, 0x12, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x06, 0xe0, 0xe0, 0x09, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x13, 0x14, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x57, 0xfb, 0xfc, 0x5f, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0xb9, 0xff, 0xff, 0xc0, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x69, 0xff, 0xff, 0x71, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x2b, 0x2c, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 	}, /* '!' */
 	[0x22 - FONT_START_CHAR] = {
-		0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xec000000, 0xec000000,
-		0xec000000, 0xec000000, 0xec000000, 0xec000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-		0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-		0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 	}, /* '"' */
 	[0x23 - FONT_START_CHAR] = {
-		0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x0e300000, 0x0c700000,
-		0x0c600000, 0x0c600000, 0x0c600000, 0x7ffc0000, 0xfffc0000, 0x18600000, 0x18e00000, 0x18c00000,
-		0xfff80000, 0xfff80000, 0x18c00000, 0x38c00000, 0x30c00000, 0x31800000, 0x31800000, 0x00000000,
-		0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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+		0x00, 0x00, 0x00, 0x00, 0x00, 0x1e, 0x30, 0x17,
+		0x00, 0x00, 0x13, 0x30, 0x23, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0xb6, 0xff, 0x67,
+		0x00, 0x00, 0x79, 0xff, 0xa6, 0x00, 0x00, 0x00,
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+		0x00, 0x00, 0x9e, 0xff, 0x82, 0x00, 0x00, 0x00,
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+		0x00, 0x00, 0xc2, 0xff, 0x5d, 0x00, 0x00, 0x00,
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+		0x00, 0x00, 0xe7, 0xff, 0x37, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x0f, 0x34, 0x34, 0x6d, 0xff, 0xe0, 0x34,
+		0x34, 0x3d, 0xff, 0xff, 0x46, 0x34, 0x34, 0x02,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x60, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
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+		0x00, 0x6d, 0xd4, 0xd4, 0xf2, 0xff, 0xea, 0xd4,
+		0xd4, 0xe8, 0xff, 0xf5, 0xd4, 0xd4, 0xac, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0xb7, 0xff, 0x65, 0x00,
+		0x00, 0x79, 0xff, 0xa3, 0x00, 0x00, 0x00, 0x00,
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+		0x00, 0x9e, 0xff, 0x7e, 0x00, 0x00, 0x00, 0x00,
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+		0x00, 0xc2, 0xff, 0x5a, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x0f, 0xac, 0xac, 0xb7, 0xff, 0xff, 0xad, 0xac,
+		0xac, 0xf6, 0xff, 0xc2, 0xac, 0xac, 0x2a, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x38, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+		0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x1e, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x1f, 0x5c, 0x5c, 0xaa, 0xff, 0xc9, 0x5c, 0x5c,
+		0x81, 0xff, 0xf0, 0x5c, 0x5c, 0x5c, 0x01, 0x00,
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+		0x55, 0xff, 0xc6, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0xb9, 0xff, 0x64, 0x00, 0x00,
+		0x79, 0xff, 0xa1, 0x00, 0x00, 0x00, 0x00, 0x00,
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+		0x00, 0x00, 0x00, 0xdd, 0xff, 0x3f, 0x00, 0x00,
+		0x9d, 0xff, 0x7b, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x06, 0xfc, 0xff, 0x1a, 0x00, 0x00,
+		0xc2, 0xff, 0x56, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 	}, /* '#' */
 	[0x24 - FONT_START_CHAR] = {
-		0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x06000000, 0x06000000, 0x1f800000, 0x3fe00000,
-		0x76f00000, 0x66600000, 0x66000000, 0x76000000, 0x7e000000, 0x3f000000, 0x0fc00000, 0x07e00000,
-		0x06700000, 0x06700000, 0xe6300000, 0xe6700000, 0x7ee00000, 0x3fe00000, 0x1f800000, 0x06000000,
-		0x06000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x19, 0x2c,
+		0x0a, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x90, 0xff,
+		0x38, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0xa1, 0xff,
+		0x48, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x2c, 0xb2, 0xfa, 0xff, 0xff,
+		0xff, 0xda, 0x67, 0x01, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x40, 0xf6, 0xff, 0xff, 0xff, 0xff,
+		0xff, 0xff, 0xff, 0xa7, 0x03, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x05, 0xe2, 0xff, 0xeb, 0x57, 0x9f, 0xff,
+		0x6c, 0xbc, 0xff, 0xff, 0x6f, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x3c, 0xff, 0xff, 0x5b, 0x00, 0x90, 0xff,
+		0x38, 0x04, 0xb5, 0x9c, 0x0e, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x4c, 0xff, 0xff, 0x47, 0x00, 0x90, 0xff,
+		0x38, 0x00, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x21, 0xff, 0xff, 0xbd, 0x08, 0x90, 0xff,
+		0x38, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0xab, 0xff, 0xff, 0xdf, 0xcd, 0xff,
+		0x38, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x0e, 0xb7, 0xff, 0xff, 0xff, 0xff,
+		0xc9, 0x62, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x4f, 0xbf, 0xff, 0xff,
+		0xff, 0xff, 0xde, 0x3d, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x98, 0xff,
+		0xe8, 0xff, 0xff, 0xf8, 0x35, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x94, 0xff,
+		0x39, 0x65, 0xfc, 0xff, 0xc0, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x12, 0x1c, 0x00, 0x00, 0x94, 0xff,
+		0x38, 0x00, 0x9f, 0xff, 0xfd, 0x05, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x79, 0xf2, 0xa5, 0x00, 0x00, 0x94, 0xff,
+		0x38, 0x00, 0x81, 0xff, 0xff, 0x0a, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x9b, 0xff, 0xff, 0x57, 0x00, 0x94, 0xff,
+		0x38, 0x08, 0xd3, 0xff, 0xdf, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x1b, 0xec, 0xff, 0xfe, 0x9e, 0xbb, 0xff,
+		0x88, 0xcb, 0xff, 0xff, 0x75, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x36, 0xea, 0xff, 0xff, 0xff, 0xff,
+		0xff, 0xff, 0xff, 0xa2, 0x03, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x14, 0x85, 0xd3, 0xfc, 0xff,
+		0xeb, 0xb2, 0x4e, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x94, 0xff,
+		0x38, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x92, 0xfc,
+		0x37, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 	}, /* '$' */
 	[0x25 - FONT_START_CHAR] = {
-		0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x3c020000, 0x7e070000,
-		0xc7060000, 0xc30c0000, 0xc31c0000, 0xc3180000, 0xfe300000, 0x7c700000, 0x00600000, 0x00c00000,
-		0x01cf0000, 0x039fc000, 0x0318c000, 0x0730e000, 0x0e306000, 0x0c38c000, 0x1c1fc000, 0x180f8000,
-		0x08000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x54, 0xcb, 0xf8, 0xe9, 0x9a, 0x16,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x28, 0x66,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x70, 0xff, 0xff, 0xf5, 0xfd, 0xff, 0xdc,
+		0x14, 0x00, 0x00, 0x00, 0x00, 0x03, 0xc8, 0xff,
+		0x68, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x1d, 0xfa, 0xfe, 0x60, 0x02, 0x18, 0xc5, 0xff,
+		0x97, 0x00, 0x00, 0x00, 0x00, 0x75, 0xff, 0xdb,
+		0x0a, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x63, 0xff, 0xbb, 0x00, 0x00, 0x00, 0x39, 0xff,
+		0xe2, 0x00, 0x00, 0x00, 0x28, 0xf8, 0xfe, 0x3d,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x70, 0xff, 0xa7, 0x00, 0x00, 0x00, 0x25, 0xff,
+		0xee, 0x00, 0x00, 0x03, 0xc9, 0xff, 0x8e, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x3e, 0xff, 0xf0, 0x1d, 0x00, 0x00, 0x82, 0xff,
+		0xbe, 0x00, 0x00, 0x7a, 0xff, 0xd8, 0x09, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x01, 0xbe, 0xff, 0xe7, 0x93, 0xaf, 0xff, 0xfd,
+		0x42, 0x00, 0x2c, 0xf9, 0xfd, 0x38, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x12, 0xb9, 0xff, 0xff, 0xff, 0xf1, 0x5a,
+		0x00, 0x04, 0xcc, 0xff, 0x8b, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x32, 0x60, 0x50, 0x10, 0x00,
+		0x00, 0x7c, 0xff, 0xd6, 0x08, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x2e, 0xfa, 0xfc, 0x34, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x05,
+		0xce, 0xff, 0x85, 0x00, 0x08, 0x81, 0xe0, 0xf8,
+		0xd8, 0x71, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x7e,
+		0xff, 0xd3, 0x07, 0x04, 0xbc, 0xff, 0xff, 0xf2,
+		0xff, 0xff, 0xa1, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0xfb,
+		0xfb, 0x33, 0x00, 0x68, 0xff, 0xe4, 0x2e, 0x00,
+		0x3d, 0xf1, 0xff, 0x46, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x06, 0xd1, 0xff,
+		0x83, 0x00, 0x00, 0xb3, 0xff, 0x6b, 0x00, 0x00,
+		0x00, 0x89, 0xff, 0x93, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x83, 0xff, 0xd0,
+		0x06, 0x00, 0x00, 0xc0, 0xff, 0x57, 0x00, 0x00,
+		0x00, 0x75, 0xff, 0x9e, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x33, 0xfb, 0xfa, 0x30,
+		0x00, 0x00, 0x00, 0x8f, 0xff, 0xbb, 0x03, 0x00,
+		0x06, 0xcb, 0xff, 0x6e, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x07, 0xd3, 0xff, 0x7e, 0x00,
+		0x00, 0x00, 0x00, 0x1e, 0xf0, 0xff, 0xc9, 0x8e,
+		0xd2, 0xff, 0xe1, 0x0d, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x36, 0xf4, 0xce, 0x05, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x38, 0xe2, 0xff, 0xff,
+		0xff, 0xd3, 0x25, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x22, 0x28, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x07, 0x48, 0x62,
+		0x3e, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 	}, /* '%' */
 	[0x26 - FONT_START_CHAR] = {
-		0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x02000000, 0x1f800000,
-		0x1fc00000, 0x38e00000, 0x38000000, 0x38000000, 0x1c000000, 0x1e000000, 0x3e000000, 0x77000000,
-		0xe3800000, 0xe1cc0000, 0xe0ec0000, 0xe0fc0000, 0xe0780000, 0x70780000, 0x7ffc0000, 0x1fd80000,
-		0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x34, 0x7a, 0x8e,
+		0x74, 0x23, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x03, 0x9e, 0xff, 0xff, 0xff,
+		0xff, 0xfb, 0x65, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x72, 0xff, 0xff, 0xec, 0xb6,
+		0xeb, 0xff, 0xfd, 0x32, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0xcc, 0xff, 0xed, 0x14, 0x00,
+		0x18, 0xeb, 0xf0, 0x55, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0xdc, 0xff, 0xc7, 0x00, 0x00,
+		0x00, 0x3b, 0x0e, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0xa6, 0xff, 0xf8, 0x1c, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x2c, 0xfa, 0xff, 0xc4, 0x05,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x21, 0xd8, 0xff, 0xff, 0x96,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x34, 0xed, 0xff, 0xff, 0xff, 0xff,
+		0x63, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x11, 0xe7, 0xff, 0xf2, 0x5e, 0xd0, 0xff,
+		0xf9, 0x37, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x80, 0xff, 0xff, 0x54, 0x00, 0x22, 0xee,
+		0xff, 0xe5, 0x18, 0x00, 0x00, 0x2f, 0x02, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0xcc, 0xff, 0xe2, 0x01, 0x00, 0x00, 0x48,
+		0xfd, 0xff, 0xc4, 0x06, 0x11, 0xf8, 0xd9, 0x2d,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0xe6, 0xff, 0xc1, 0x00, 0x00, 0x00, 0x00,
+		0x79, 0xff, 0xff, 0x96, 0x7b, 0xff, 0xf3, 0x0d,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0xd8, 0xff, 0xde, 0x00, 0x00, 0x00, 0x00,
+		0x01, 0xaf, 0xff, 0xff, 0xfb, 0xff, 0x8c, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0xa3, 0xff, 0xff, 0x4d, 0x00, 0x00, 0x00,
+		0x00, 0x0d, 0xd7, 0xff, 0xff, 0xeb, 0x13, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x3b, 0xff, 0xff, 0xf3, 0x64, 0x0c, 0x00,
+		0x08, 0x53, 0xdf, 0xff, 0xff, 0xe9, 0x18, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x84, 0xff, 0xff, 0xff, 0xfe, 0xf0,
+		0xfc, 0xff, 0xff, 0xfb, 0xff, 0xff, 0xc4, 0x05,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x62, 0xe4, 0xff, 0xff, 0xff,
+		0xff, 0xff, 0xbc, 0x2f, 0x87, 0xfc, 0x75, 0x01,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x02, 0x31, 0x58, 0x61,
+		0x4f, 0x1c, 0x00, 0x00, 0x03, 0x30, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 	}, /* '&' */
 	[0x27 - FONT_START_CHAR] = {
-		0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xe0000000, 0xe0000000,
-		0xe0000000, 0xe0000000, 0xe0000000, 0xe0000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-		0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-		0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x21, 0x30, 0x1e, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0xb0, 0xff, 0xa0, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0xb0, 0xff, 0xa0, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0xb0, 0xff, 0xa0, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0xb0, 0xff, 0xa0, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0xb0, 0xff, 0xa0, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0xb0, 0xff, 0xa0, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x03, 0x04, 0x03, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 	}, /* '\'' */
 	[0x28 - FONT_START_CHAR] = {
-		0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x0c000000, 0x1e000000, 0x1c000000, 0x38000000,
-		0x30000000, 0x70000000, 0x70000000, 0x60000000, 0x60000000, 0xe0000000, 0xe0000000, 0xe0000000,
-		0xe0000000, 0x60000000, 0x60000000, 0x70000000, 0x70000000, 0x38000000, 0x38000000, 0x1c000000,
-		0x1e000000, 0x0c000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x1c, 0x01, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x13, 0xe5, 0xbf, 0x27,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0xa4, 0xff, 0xff, 0x53,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x3e, 0xff, 0xff, 0xac, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0xc5, 0xff, 0xf4, 0x1b, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x3e, 0xff, 0xff, 0x88, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0xa6, 0xff, 0xf9, 0x16, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x07, 0xf4, 0xff, 0xaf, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x3f, 0xff, 0xff, 0x61, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x74, 0xff, 0xff, 0x28, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x94, 0xff, 0xfe, 0x04, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0xa4, 0xff, 0xf0, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0xa4, 0xff, 0xf0, 0x00, 0x00, 0x00, 0x00,
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+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x71, 0xff, 0xff, 0x28, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x3f, 0xff, 0xff, 0x62, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x07, 0xf3, 0xff, 0xb0, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0xa4, 0xff, 0xfb, 0x19, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x3e, 0xff, 0xff, 0x8d, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0xc4, 0xff, 0xf7, 0x1f, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x3a, 0xff, 0xff, 0xb0, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x9f, 0xff, 0xff, 0x56,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x10, 0xe2, 0xb7, 0x1f,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x17, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 	}, /* '(' */
 	[0x29 - FONT_START_CHAR] = {
-		0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x60000000, 0x70000000, 0x70000000, 0x38000000,
-		0x18000000, 0x1c000000, 0x1c000000, 0x0c000000, 0x0e000000, 0x0e000000, 0x0e000000, 0x0e000000,
-		0x0e000000, 0x0e000000, 0x0c000000, 0x1c000000, 0x1c000000, 0x18000000, 0x38000000, 0x70000000,
-		0xf0000000, 0x60000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x1c, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x14, 0xa2, 0xf7, 0x2b, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x2c, 0xf9, 0xff, 0xcc, 0x03, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x7f, 0xff, 0xff, 0x6b, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x07, 0xdd, 0xff, 0xe8, 0x0b, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x5c, 0xff, 0xff, 0x6c, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x03, 0xe0, 0xff, 0xd4, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x83, 0xff, 0xff, 0x29, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x34, 0xff, 0xff, 0x6d, 0x00,
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+		0x00, 0x00, 0x00, 0x03, 0xf8, 0xff, 0x9f, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0xd5, 0xff, 0xc0, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0xc4, 0xff, 0xd0, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0xc4, 0xff, 0xd0, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0xd8, 0xff, 0xbf, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x05, 0xf9, 0xff, 0x9d, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x37, 0xff, 0xff, 0x69, 0x00,
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+		0x00, 0x00, 0x00, 0x85, 0xff, 0xff, 0x26, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x04, 0xe3, 0xff, 0xce, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x60, 0xff, 0xff, 0x66, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x09, 0xdf, 0xff, 0xe7, 0x08, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x84, 0xff, 0xff, 0x65, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x32, 0xfb, 0xff, 0xc8, 0x02, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x12, 0x9c, 0xf5, 0x28, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x17, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 	}, /* ')' */
 	[0x2a - FONT_START_CHAR] = {
-		0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x18000000, 0x18000000,
-		0x98800000, 0xff800000, 0xff000000, 0x1c000000, 0x3e000000, 0x67000000, 0x62000000, 0x00000000,
-		0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-		0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x7f, 0xb4, 0x31, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0xae, 0xff, 0x42, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x69, 0x2f, 0x00, 0xa8, 0xff, 0x3d, 0x07,
+		0x59, 0x35, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x14, 0xfb, 0xff, 0xca, 0xd5, 0xff, 0xb2, 0xec,
+		0xff, 0x9e, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x18, 0x86, 0xd2, 0xff, 0xff, 0xff, 0xff, 0xf6,
+		0xae, 0x54, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x81, 0xff, 0xff, 0xf8, 0x23,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x36, 0xf9, 0xf5, 0xa4, 0xff, 0xc2,
+		0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x16, 0xe3, 0xff, 0x6a, 0x07, 0xd3, 0xff,
+		0x8e, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x08, 0x93, 0xb9, 0x01, 0x00, 0x2f, 0xe1,
+		0x47, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 	}, /* '*' */
 	[0x2b - FONT_START_CHAR] = {
-		0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-		0x00000000, 0x00000000, 0x00000000, 0x06000000, 0x06000000, 0x06000000, 0x06000000, 0xffe00000,
-		0xffe00000, 0xffe00000, 0x06000000, 0x06000000, 0x06000000, 0x06000000, 0x00000000, 0x00000000,
-		0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x58, 0x9c, 0x9c, 0x9c, 0xc1, 0xff, 0xff,
+		0x9c, 0x9c, 0x9c, 0x9c, 0x25, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x90, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+		0xff, 0xff, 0xff, 0xff, 0x3c, 0x00, 0x00, 0x00,
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+		0x00, 0x5f, 0xa8, 0xa8, 0xa8, 0xca, 0xff, 0xff,
+		0xa8, 0xa8, 0xa8, 0xa8, 0x27, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 	}, /* '+' */
 	[0x2c - FONT_START_CHAR] = {
-		0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-		0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-		0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xf0000000, 0xf0000000, 0x70000000, 0x60000000,
-		0xc0000000, 0x40000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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+		0x00, 0x49, 0xf1, 0xff, 0x81, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x1d, 0xef, 0xdb, 0x0a, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x02, 0xc0, 0xfd, 0x38, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x56, 0x7b, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 	}, /* ',' */
 	[0x2d - FONT_START_CHAR] = {
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+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x1c, 0x30, 0x26,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0xc2, 0xff, 0x9e,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x15, 0xfd, 0xff, 0x4e,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x63, 0xff, 0xf5, 0x09,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0xb2, 0xff, 0xae, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x0b, 0xf7, 0xff, 0x5e, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x52, 0xff, 0xfc, 0x12, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0xa3, 0xff, 0xbe, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x04, 0xee, 0xff, 0x70, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x42, 0xff, 0xff, 0x21, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x92, 0xff, 0xd2, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x01, 0xe3, 0xff, 0x82, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x32, 0xff, 0xff, 0x32, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x83, 0xff, 0xe1, 0x01, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0xd5, 0xff, 0x92, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x26, 0xff, 0xff, 0x42, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x75, 0xff, 0xee, 0x04, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0xc5, 0xff, 0xa4, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 	}, /* '/' */
 	[0x30 - FONT_START_CHAR] = {
-		0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x03000000, 0x1fc00000,
-		0x3fe00000, 0x38700000, 0x70380000, 0x60380000, 0xe0380000, 0xe0180000, 0xe0180000, 0xe0180000,
-		0xe0180000, 0xe0180000, 0xe0380000, 0x60380000, 0x70300000, 0x38f00000, 0x3fe00000, 0x0fc00000,
-		0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x25, 0x6e, 0x8d,
+		0x83, 0x52, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x09, 0x9b, 0xfe, 0xff, 0xff,
+		0xff, 0xff, 0xe6, 0x4b, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x03, 0xb8, 0xff, 0xff, 0xff, 0xf3,
+		0xfa, 0xff, 0xff, 0xfc, 0x4e, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x76, 0xff, 0xff, 0xc4, 0x2b, 0x00,
+		0x07, 0x64, 0xf6, 0xff, 0xef, 0x17, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x0b, 0xef, 0xff, 0xe0, 0x0d, 0x00, 0x00,
+		0x00, 0x00, 0x5b, 0xff, 0xff, 0x8b, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x59, 0xff, 0xff, 0x65, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0xd2, 0xff, 0xe9, 0x02, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x9b, 0xff, 0xff, 0x13, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x7f, 0xff, 0xff, 0x2e, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0xc6, 0xff, 0xe1, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x4d, 0xff, 0xff, 0x58, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0xdd, 0xff, 0xc7, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x34, 0xff, 0xff, 0x70, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0xe3, 0xff, 0xc1, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x2d, 0xff, 0xff, 0x76, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0xd9, 0xff, 0xcb, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x37, 0xff, 0xff, 0x6d, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0xbf, 0xff, 0xe9, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x55, 0xff, 0xff, 0x52, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x8f, 0xff, 0xff, 0x1e, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x8d, 0xff, 0xff, 0x23, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x49, 0xff, 0xff, 0x79, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x05, 0xe2, 0xff, 0xdb, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x04, 0xe0, 0xff, 0xef, 0x1e, 0x00, 0x00,
+		0x00, 0x00, 0x7b, 0xff, 0xff, 0x76, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x57, 0xff, 0xff, 0xe2, 0x57, 0x1f,
+		0x2d, 0x91, 0xff, 0xff, 0xdd, 0x0a, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x93, 0xff, 0xff, 0xff, 0xff,
+		0xff, 0xff, 0xff, 0xf1, 0x32, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x01, 0x6f, 0xef, 0xff, 0xff,
+		0xff, 0xff, 0xc2, 0x2a, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x09, 0x41, 0x61,
+		0x57, 0x27, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 	}, /* '0' */
 	[0x31 - FONT_START_CHAR] = {
-		0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x0c000000, 0x3c000000,
-		0x7c000000, 0xec000000, 0xcc000000, 0x0c000000, 0x0c000000, 0x0c000000, 0x0c000000, 0x0c000000,
-		0x0c000000, 0x0c000000, 0x0c000000, 0x0c000000, 0x0c000000, 0x0c000000, 0x0c000000, 0x00000000,
-		0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x1a, 0x30, 0x0e,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x01, 0x6c, 0xf7, 0xff, 0x48,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x17, 0xb5, 0xff, 0xff, 0xff, 0x48,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x4b, 0xe9, 0xff, 0xff, 0xff, 0xff, 0x48,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x28, 0xfd, 0xff, 0xf6, 0xad, 0xff, 0xff, 0x48,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x89, 0xce, 0x29, 0x54, 0xff, 0xff, 0x48,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x05, 0x07, 0x00, 0x54, 0xff, 0xff, 0x48,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x54, 0xff, 0xff, 0x48,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x54, 0xff, 0xff, 0x48,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x54, 0xff, 0xff, 0x48,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x54, 0xff, 0xff, 0x48,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x54, 0xff, 0xff, 0x48,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x54, 0xff, 0xff, 0x48,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x54, 0xff, 0xff, 0x48,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x54, 0xff, 0xff, 0x48,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x54, 0xff, 0xff, 0x48,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x54, 0xff, 0xff, 0x48,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x54, 0xff, 0xff, 0x48,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 	}, /* '1' */
 	[0x32 - FONT_START_CHAR] = {
-		0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x0c000000, 0x3f800000,
-		0x7fc00000, 0xf1c00000, 0x60e00000, 0x00e00000, 0x00e00000, 0x01c00000, 0x01c00000, 0x03800000,
-		0x07000000, 0x0e000000, 0x1c000000, 0x38000000, 0x70000000, 0xe0000000, 0xffe00000, 0xffe00000,
-		0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x04, 0x4c, 0x80, 0x8e, 0x79,
+		0x38, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x2f, 0xd8, 0xff, 0xff, 0xff, 0xff,
+		0xff, 0xb9, 0x14, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x1f, 0xed, 0xff, 0xff, 0xfa, 0xee, 0xff,
+		0xff, 0xff, 0xcb, 0x04, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0xa7, 0xff, 0xff, 0x88, 0x0b, 0x00, 0x26,
+		0xce, 0xff, 0xff, 0x59, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x71, 0xe5, 0xa8, 0x00, 0x00, 0x00, 0x00,
+		0x32, 0xff, 0xff, 0x9b, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x05, 0x0e, 0x00, 0x00, 0x00, 0x00,
+		0x0a, 0xff, 0xff, 0xa8, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x31, 0xff, 0xff, 0x85, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0xa3, 0xff, 0xff, 0x31, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x54,
+		0xff, 0xff, 0xb0, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3b, 0xf7,
+		0xff, 0xe5, 0x17, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0xf0, 0xff,
+		0xf1, 0x31, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x25, 0xe9, 0xff, 0xf5,
+		0x3b, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x1d, 0xe1, 0xff, 0xf8, 0x44,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x15, 0xd8, 0xff, 0xfb, 0x4c, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x0f, 0xcd, 0xff, 0xfd, 0x56, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0xbd, 0xff, 0xff, 0xbc, 0x64, 0x64, 0x64,
+		0x64, 0x64, 0x64, 0x58, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0xf4, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+		0xff, 0xff, 0xff, 0xe0, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0xf4, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+		0xff, 0xff, 0xff, 0xe0, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 	}, /* '2' */
 	[0x33 - FONT_START_CHAR] = {
-		0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x0c000000, 0x3f800000,
-		0x7fc00000, 0xe1c00000, 0x60e00000, 0x00e00000, 0x00c00000, 0x01c00000, 0x0f800000, 0x0f800000,
-		0x01c00000, 0x00e00000, 0x00e00000, 0x40e00000, 0xe0e00000, 0xf1e00000, 0x7fc00000, 0x3f800000,
-		0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x01, 0x42, 0x7e, 0x8e, 0x7b,
+		0x42, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x1c, 0xc7, 0xff, 0xff, 0xff, 0xff,
+		0xff, 0xcd, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x0e, 0xdb, 0xff, 0xff, 0xeb, 0xd2, 0xf8,
+		0xff, 0xff, 0xd8, 0x06, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x8e, 0xff, 0xff, 0x7e, 0x03, 0x00, 0x12,
+		0xbe, 0xff, 0xff, 0x58, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x26, 0xa5, 0xaf, 0x00, 0x00, 0x00, 0x00,
+		0x2b, 0xff, 0xff, 0x88, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x00,
+		0x0f, 0xff, 0xff, 0x85, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x51, 0xff, 0xff, 0x52, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x03, 0x0c, 0x14, 0x5c,
+		0xed, 0xff, 0xcc, 0x04, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x44, 0xff, 0xff, 0xff,
+		0xff, 0xab, 0x14, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x44, 0xff, 0xff, 0xff,
+		0xff, 0xe9, 0x57, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x09, 0x20, 0x26, 0x55,
+		0xd4, 0xff, 0xff, 0x4d, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x0f, 0xe5, 0xff, 0xd3, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x95, 0xff, 0xff, 0x11, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x3a, 0xa0, 0x43, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x92, 0xff, 0xff, 0x1c, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x0f, 0xf6, 0xff, 0xca, 0x05, 0x00, 0x00, 0x00,
+		0x09, 0xdf, 0xff, 0xf3, 0x04, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x8f, 0xff, 0xff, 0xb1, 0x21, 0x01, 0x29,
+		0xba, 0xff, 0xff, 0x98, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x0c, 0xd0, 0xff, 0xff, 0xff, 0xff, 0xff,
+		0xff, 0xff, 0xd5, 0x12, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x11, 0xa6, 0xfe, 0xff, 0xff, 0xff,
+		0xfd, 0xa4, 0x12, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x1c, 0x53, 0x62, 0x4e,
+		0x17, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 	}, /* '3' */
 	[0x34 - FONT_START_CHAR] = {
-		0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x01c00000, 0x01c00000,
-		0x03c00000, 0x07c00000, 0x0ec00000, 0x0cc00000, 0x1cc00000, 0x38c00000, 0x30c00000, 0x70c00000,
-		0xe0c00000, 0xfff00000, 0xfff00000, 0x00c00000, 0x00c00000, 0x00c00000, 0x00c00000, 0x00000000,
-		0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x14, 0x30, 0x30, 0x14, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x04,
+		0xcc, 0xff, 0xff, 0x68, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x7b,
+		0xff, 0xff, 0xff, 0x68, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x2d, 0xf9,
+		0xff, 0xff, 0xff, 0x68, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x04, 0xcd, 0xff,
+		0xcd, 0xff, 0xff, 0x68, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x7d, 0xff, 0xf0,
+		0x33, 0xff, 0xff, 0x68, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x2e, 0xfa, 0xff, 0x5f,
+		0x18, 0xff, 0xff, 0x68, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x05, 0xcf, 0xff, 0xb0, 0x00,
+		0x18, 0xff, 0xff, 0x68, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x80, 0xff, 0xed, 0x18, 0x00,
+		0x18, 0xff, 0xff, 0x68, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x31, 0xfb, 0xff, 0x59, 0x00, 0x00,
+		0x18, 0xff, 0xff, 0x68, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x06, 0xd2, 0xff, 0xad, 0x00, 0x00, 0x00,
+		0x18, 0xff, 0xff, 0x68, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x83, 0xff, 0xeb, 0x17, 0x00, 0x00, 0x00,
+		0x18, 0xff, 0xff, 0x68, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x18, 0xfc, 0xff, 0xf6, 0xe4, 0xe4, 0xe4, 0xe4,
+		0xea, 0xff, 0xff, 0xf6, 0xec, 0x51, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x24, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+		0xff, 0xff, 0xff, 0xff, 0xff, 0x58, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x10, 0x70, 0x70, 0x70, 0x70, 0x70, 0x70, 0x70,
+		0x8e, 0xff, 0xff, 0xac, 0x70, 0x27, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x34, 0xff, 0xff, 0x68, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x34, 0xff, 0xff, 0x68, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x34, 0xff, 0xff, 0x68, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 	}, /* '4' */
 	[0x35 - FONT_START_CHAR] = {
-		0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x3fe00000, 0x7fe00000,
-		0x70000000, 0x70000000, 0x60000000, 0x60000000, 0x6f800000, 0x7fc00000, 0x79e00000, 0x20e00000,
-		0x00700000, 0x00700000, 0x60700000, 0xe0600000, 0x70e00000, 0x7fc00000, 0x3f800000, 0x00000000,
-		0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x11, 0x30, 0x30, 0x30, 0x30, 0x30,
+		0x30, 0x30, 0x30, 0x1b, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x70, 0xff, 0xff, 0xff, 0xff, 0xff,
+		0xff, 0xff, 0xff, 0x90, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x90, 0xff, 0xff, 0xff, 0xff, 0xff,
+		0xff, 0xff, 0xff, 0x90, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0xb0, 0xff, 0xb5, 0x34, 0x34, 0x34,
+		0x34, 0x34, 0x34, 0x1d, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0xd0, 0xff, 0x84, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0xf0, 0xff, 0x64, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x10, 0xff, 0xff, 0x42, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x30, 0xff, 0xff, 0x43, 0x9a, 0xdc, 0xed,
+		0xd3, 0x84, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x50, 0xff, 0xff, 0xf8, 0xff, 0xff, 0xff,
+		0xff, 0xff, 0xde, 0x20, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x5c, 0xff, 0xff, 0xf8, 0x8f, 0x5a, 0x69,
+		0xc4, 0xff, 0xff, 0xcf, 0x03, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x25, 0x8b, 0x3b, 0x00, 0x00, 0x00,
+		0x02, 0xa6, 0xff, 0xff, 0x4f, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x1f, 0xff, 0xff, 0x92, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0xf5, 0xff, 0xa9, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x01, 0x59, 0xbe, 0x82, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x10, 0xff, 0xff, 0x9b, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0xd3, 0xff, 0xf2, 0x1f, 0x00, 0x00, 0x00,
+		0x00, 0x79, 0xff, 0xff, 0x60, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x5a, 0xff, 0xff, 0xd8, 0x46, 0x0e, 0x1e,
+		0x7f, 0xfd, 0xff, 0xe7, 0x0b, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x9f, 0xff, 0xff, 0xff, 0xff, 0xff,
+		0xff, 0xff, 0xf8, 0x41, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x02, 0x79, 0xf2, 0xff, 0xff, 0xff,
+		0xff, 0xcf, 0x37, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x0b, 0x45, 0x61, 0x5a,
+		0x2d, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 	}, /* '5' */
 	[0x36 - FONT_START_CHAR] = {
-		0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x02000000, 0x03800000,
-		0x07800000, 0x07000000, 0x0e000000, 0x1c000000, 0x3c000000, 0x3f800000, 0x7fc00000, 0x79e00000,
-		0xe0700000, 0xe0700000, 0xe0700000, 0xe0700000, 0xe0700000, 0x70e00000, 0x7fc00000, 0x1f800000,
-		0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x31,
+		0x46, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0c, 0xda,
+		0xff, 0x93, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x9e, 0xff,
+		0xff, 0x81, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x59, 0xff, 0xff,
+		0xc1, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x21, 0xf1, 0xff, 0xed,
+		0x1c, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x04, 0xc5, 0xff, 0xff, 0x4e,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x7e, 0xff, 0xff, 0x92, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x2d, 0xfa, 0xff, 0xff, 0xd7, 0xec,
+		0xdf, 0x9d, 0x28, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x01, 0xc3, 0xff, 0xff, 0xff, 0xff, 0xff,
+		0xff, 0xff, 0xf8, 0x52, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x4d, 0xff, 0xff, 0xfd, 0x99, 0x51, 0x52,
+		0x9c, 0xfe, 0xff, 0xf8, 0x28, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0xb5, 0xff, 0xff, 0x55, 0x00, 0x00, 0x00,
+		0x00, 0x63, 0xff, 0xff, 0x9d, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0xf0, 0xff, 0xc5, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0xd7, 0xff, 0xde, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x04, 0xff, 0xff, 0x9a, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0xae, 0xff, 0xf2, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0xf3, 0xff, 0xb5, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0xc8, 0xff, 0xde, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0xba, 0xff, 0xfb, 0x2f, 0x00, 0x00, 0x00,
+		0x00, 0x3a, 0xff, 0xff, 0x9d, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x46, 0xff, 0xff, 0xea, 0x5f, 0x18, 0x19,
+		0x62, 0xee, 0xff, 0xfb, 0x2b, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x8c, 0xff, 0xff, 0xff, 0xff, 0xff,
+		0xff, 0xff, 0xff, 0x66, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x67, 0xe9, 0xff, 0xff, 0xff,
+		0xff, 0xdb, 0x4b, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x04, 0x3a, 0x5b, 0x59,
+		0x32, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 	}, /* '6' */
 	[0x37 - FONT_START_CHAR] = {
-		0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xffe00000, 0xffe00000,
-		0x00c00000, 0x01c00000, 0x01800000, 0x03800000, 0x03000000, 0x07000000, 0x0e000000, 0x0e000000,
-		0x1c000000, 0x1c000000, 0x38000000, 0x38000000, 0x70000000, 0x70000000, 0xe0000000, 0x00000000,
-		0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x12, 0x30, 0x30, 0x30, 0x30, 0x30, 0x30, 0x30,
+		0x30, 0x30, 0x30, 0x1d, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x60, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+		0xff, 0xff, 0xff, 0x98, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x60, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+		0xff, 0xff, 0xff, 0x98, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x15, 0x38, 0x38, 0x38, 0x38, 0x38, 0x38, 0x38,
+		0x7a, 0xff, 0xff, 0x75, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02,
+		0xce, 0xff, 0xe9, 0x0c, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x5a,
+		0xff, 0xff, 0x70, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x06, 0xde,
+		0xff, 0xe2, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x6d, 0xff,
+		0xff, 0x65, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x0d, 0xeb, 0xff,
+		0xdb, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x82, 0xff, 0xff,
+		0x5b, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x17, 0xf4, 0xff, 0xd3,
+		0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x96, 0xff, 0xff, 0x4f,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x25, 0xfb, 0xff, 0xc9, 0x01,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0xa9, 0xff, 0xff, 0x44, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x35, 0xff, 0xff, 0xbf, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0xbe, 0xff, 0xff, 0x3a, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x47, 0xff, 0xff, 0xb4, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x3b, 0xcc, 0xff, 0x31, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x01, 0x37, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 	}, /* '7' */
 	[0x38 - FONT_START_CHAR] = {
-		0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x06000000, 0x3f800000,
-		0x7fc00000, 0x70e00000, 0x60e00000, 0x60e00000, 0x60e00000, 0x71c00000, 0x3f800000, 0x3fc00000,
-		0x71e00000, 0xe0e00000, 0xe0600000, 0xe0700000, 0xe0600000, 0xf0e00000, 0x7fc00000, 0x3f800000,
-		0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x23, 0x6e, 0x8d, 0x83,
+		0x52, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x03, 0x8f, 0xfd, 0xff, 0xff, 0xff,
+		0xff, 0xe2, 0x3a, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x8d, 0xff, 0xff, 0xf9, 0xcd, 0xdf,
+		0xff, 0xff, 0xf4, 0x26, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x1a, 0xfc, 0xff, 0xd1, 0x1b, 0x00, 0x00,
+		0x5e, 0xfe, 0xff, 0xa1, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x54, 0xff, 0xff, 0x43, 0x00, 0x00, 0x00,
+		0x00, 0xb7, 0xff, 0xe0, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x5f, 0xff, 0xff, 0x22, 0x00, 0x00, 0x00,
+		0x00, 0x96, 0xff, 0xea, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x30, 0xff, 0xff, 0x60, 0x00, 0x00, 0x00,
+		0x02, 0xd2, 0xff, 0xbb, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0xb0, 0xff, 0xef, 0x56, 0x0d, 0x1f,
+		0xa2, 0xff, 0xfd, 0x3e, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x0b, 0xae, 0xff, 0xff, 0xff, 0xff,
+		0xff, 0xf1, 0x54, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x30, 0xd3, 0xff, 0xff, 0xff, 0xff,
+		0xff, 0xfa, 0x8d, 0x05, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x23, 0xf0, 0xff, 0xdd, 0x59, 0x24, 0x31,
+		0x8f, 0xfe, 0xff, 0x9f, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0xa7, 0xff, 0xf1, 0x1a, 0x00, 0x00, 0x00,
+		0x00, 0x83, 0xff, 0xff, 0x32, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0xec, 0xff, 0xa7, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x1e, 0xff, 0xff, 0x78, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0xfc, 0xff, 0xa0, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x12, 0xff, 0xff, 0x88, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0xdb, 0xff, 0xe8, 0x0d, 0x00, 0x00, 0x00,
+		0x00, 0x62, 0xff, 0xff, 0x68, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x81, 0xff, 0xff, 0xc4, 0x2d, 0x00, 0x08,
+		0x60, 0xf5, 0xff, 0xf6, 0x17, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x09, 0xc8, 0xff, 0xff, 0xff, 0xf6, 0xfd,
+		0xff, 0xff, 0xff, 0x61, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x0c, 0x95, 0xf9, 0xff, 0xff, 0xff,
+		0xff, 0xdb, 0x4c, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x10, 0x49, 0x61, 0x5a,
+		0x31, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 	}, /* '8' */
 	[0x39 - FONT_START_CHAR] = {
-		0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x06000000, 0x3f800000,
-		0x7fc00000, 0xf0e00000, 0xe0600000, 0xc0700000, 0xc0700000, 0xe0700000, 0xe0e00000, 0x7be00000,
-		0x3fc00000, 0x1fc00000, 0x03800000, 0x07000000, 0x0f000000, 0x0e000000, 0x1c000000, 0x18000000,
-		0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x2d, 0x71, 0x8d, 0x83,
+		0x55, 0x0b, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x13, 0xaf, 0xff, 0xff, 0xff, 0xff,
+		0xff, 0xed, 0x5b, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x0d, 0xd3, 0xff, 0xff, 0xfe, 0xe6, 0xf5,
+		0xff, 0xff, 0xff, 0x61, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x90, 0xff, 0xff, 0xa6, 0x17, 0x00, 0x04,
+		0x5b, 0xf4, 0xff, 0xf5, 0x19, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x08, 0xf5, 0xff, 0xc8, 0x03, 0x00, 0x00, 0x00,
+		0x00, 0x5b, 0xff, 0xff, 0x73, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x34, 0xff, 0xff, 0x6e, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x04, 0xf6, 0xff, 0xa7, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x40, 0xff, 0xff, 0x60, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0xec, 0xff, 0xb1, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x27, 0xff, 0xff, 0x98, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x28, 0xff, 0xff, 0x95, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x01, 0xdb, 0xff, 0xf9, 0x42, 0x00, 0x00, 0x00,
+		0x0d, 0xc3, 0xff, 0xff, 0x51, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x50, 0xff, 0xff, 0xfc, 0xaa, 0x7a, 0x8e,
+		0xe6, 0xff, 0xff, 0xe0, 0x05, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x69, 0xfa, 0xff, 0xff, 0xff, 0xff,
+		0xff, 0xff, 0xff, 0x59, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x26, 0x8a, 0xb9, 0xb9, 0xd1,
+		0xff, 0xff, 0xbb, 0x01, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1c, 0xed,
+		0xff, 0xf0, 0x1f, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0xc1, 0xff,
+		0xff, 0x58, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0xff,
+		0x9d, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x3f, 0xfd, 0xff, 0xda,
+		0x0c, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x13, 0xe4, 0xff, 0xfa, 0x32,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x0e, 0x9e, 0xff, 0x73, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x3b, 0x01, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 	}, /* '9' */
 	[0x3a - FONT_START_CHAR] = {
-		0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-		0x00000000, 0x00000000, 0x00000000, 0xf0000000, 0xf0000000, 0x60000000, 0x00000000, 0x00000000,
-		0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xf0000000, 0xf0000000, 0x60000000, 0x00000000,
-		0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 	}, /* '<' */
 	[0x3d - FONT_START_CHAR] = {
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 	}, /* '=' */
 	[0x3e - FONT_START_CHAR] = {
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-		0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
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+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x50, 0xff, 0xfb, 0xaa, 0x3f, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x2e, 0xd4, 0xff, 0xff, 0xff, 0xd4, 0x68,
+		0x0c, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x37, 0x99, 0xf2, 0xff, 0xff,
+		0xf1, 0x93, 0x28, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x0a, 0x5f, 0xc1,
+		0xff, 0xff, 0xff, 0xbc, 0x15, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x3d, 0xe6, 0xff, 0xff, 0x2c, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x4c, 0xb0,
+		0xfb, 0xff, 0xff, 0xcc, 0x18, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x22, 0x84, 0xe5, 0xff, 0xff,
+		0xf8, 0xa2, 0x38, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x27, 0xbd, 0xff, 0xff, 0xff, 0xe1, 0x79,
+		0x15, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x50, 0xff, 0xff, 0xbb, 0x4f, 0x03, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x43, 0x91, 0x28, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 	}, /* '>' */
 	[0x3f - FONT_START_CHAR] = {
-		0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x0c000000, 0x3f800000,
-		0x7fc00000, 0xe1c00000, 0x61c00000, 0x01c00000, 0x01c00000, 0x03800000, 0x07000000, 0x0e000000,
-		0x0e000000, 0x0c000000, 0x0c000000, 0x00000000, 0x0c000000, 0x1e000000, 0x1e000000, 0x0e000000,
-		0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x0b, 0x5b, 0x8d, 0x93, 0x75,
+		0x27, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x4a, 0xeb, 0xff, 0xff, 0xff, 0xff,
+		0xfe, 0x92, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x3b, 0xfa, 0xff, 0xff, 0xe3, 0xda, 0xfe,
+		0xff, 0xff, 0x83, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x01, 0xd0, 0xff, 0xfc, 0x59, 0x00, 0x00, 0x31,
+		0xf0, 0xff, 0xf4, 0x0a, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x05, 0x68, 0xc2, 0x8a, 0x00, 0x00, 0x00, 0x00,
+		0x95, 0xff, 0xff, 0x31, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x8e, 0xff, 0xff, 0x2a, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x16,
+		0xe9, 0xff, 0xe5, 0x03, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x18, 0xd3,
+		0xff, 0xff, 0x5a, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x1b, 0xdc, 0xff,
+		0xff, 0x7e, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x01, 0xc3, 0xff, 0xff,
+		0x6f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x2d, 0xff, 0xff, 0xa6,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x4b, 0xff, 0xff, 0x64,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x35, 0xb4, 0xb4, 0x44,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x18, 0x97, 0xa6, 0x34,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0xbc, 0xff, 0xff, 0xef,
+		0x0b, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0xdc, 0xff, 0xff, 0xff,
+		0x1c, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x64, 0xfd, 0xff, 0x9f,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x19, 0x26, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 	}, /* '?' */
 	[0x40 - FONT_START_CHAR] = {
-		0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00e00000,
-		0x07fc0000, 0x0f0f0000, 0x38038000, 0x3001c000, 0x61fcc000, 0x63fc6000, 0xc60c6000, 0xc60c6000,
-		0xc60c6000, 0xc60c6000, 0xc60c6000, 0x671ee000, 0x63f7c000, 0x70c10000, 0x38000000, 0x1c000000,
-		0x0ff80000, 0x03fc0000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x18,
+		0x57, 0x7f, 0x8d, 0x88, 0x6f, 0x3a, 0x03, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x31, 0xb6, 0xfe,
+		0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xe8, 0x78,
+		0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x74, 0xfc, 0xff, 0xe5,
+		0x8f, 0x59, 0x40, 0x44, 0x65, 0xa9, 0xf9, 0xff,
+		0xd2, 0x1e, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x7b, 0xff, 0xfa, 0x79, 0x06,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1e, 0xba,
+		0xff, 0xdf, 0x16, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x44, 0xfe, 0xf9, 0x48, 0x00, 0x00,
+		0x00, 0x1f, 0x2c, 0x0a, 0x00, 0x00, 0x00, 0x03,
+		0xa6, 0xff, 0xb4, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x02, 0xd7, 0xff, 0x6a, 0x00, 0x00, 0x47,
+		0xd9, 0xff, 0xff, 0xf7, 0x8c, 0x85, 0xe4, 0x27,
+		0x08, 0xd8, 0xff, 0x3e, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x42, 0xff, 0xd4, 0x02, 0x00, 0x47, 0xfc,
+		0xff, 0xc8, 0x9f, 0xcd, 0xff, 0xf7, 0xff, 0x2c,
+		0x00, 0x58, 0xff, 0x9e, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x8b, 0xff, 0x76, 0x00, 0x02, 0xdd, 0xff,
+		0x7a, 0x00, 0x00, 0x00, 0x82, 0xff, 0xff, 0x2c,
+		0x00, 0x09, 0xfa, 0xe0, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0xb4, 0xff, 0x3d, 0x00, 0x31, 0xff, 0xe3,
+		0x02, 0x00, 0x00, 0x00, 0x03, 0xe4, 0xff, 0x2c,
+		0x00, 0x00, 0xd4, 0xff, 0x08, 0x00, 0x00, 0x00,
+		0x00, 0xc5, 0xff, 0x27, 0x00, 0x51, 0xff, 0xb7,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0xb7, 0xff, 0x2c,
+		0x00, 0x00, 0xc3, 0xff, 0x14, 0x00, 0x00, 0x00,
+		0x00, 0xbf, 0xff, 0x2f, 0x00, 0x46, 0xff, 0xc7,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0xc8, 0xff, 0x2c,
+		0x00, 0x00, 0xcd, 0xff, 0x0d, 0x00, 0x00, 0x00,
+		0x00, 0xa2, 0xff, 0x53, 0x00, 0x12, 0xfa, 0xfd,
+		0x2e, 0x00, 0x00, 0x00, 0x33, 0xfe, 0xff, 0x3f,
+		0x00, 0x0d, 0xf8, 0xe4, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x6b, 0xff, 0x9b, 0x00, 0x00, 0x90, 0xff,
+		0xe5, 0x5c, 0x32, 0x63, 0xea, 0xf9, 0xff, 0xc2,
+		0x46, 0xac, 0xff, 0x8a, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x1b, 0xfb, 0xf5, 0x1a, 0x00, 0x06, 0xac,
+		0xff, 0xff, 0xff, 0xff, 0xf2, 0x46, 0xc2, 0xff,
+		0xff, 0xff, 0xd7, 0x10, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x9c, 0xff, 0xb9, 0x04, 0x00, 0x00,
+		0x42, 0x87, 0x94, 0x6d, 0x15, 0x00, 0x09, 0x6b,
+		0x96, 0x6f, 0x0d, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x12, 0xe0, 0xff, 0xae, 0x0c, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x27, 0xe4, 0xff, 0xe1, 0x67,
+		0x13, 0x00, 0x00, 0x00, 0x12, 0x51, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x18, 0xb0, 0xff, 0xff,
+		0xfe, 0xe1, 0xd2, 0xe1, 0xff, 0xff, 0x3c, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x32, 0x8f,
+		0xcc, 0xed, 0xf6, 0xea, 0xc4, 0x85, 0x21, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 	}, /* '@' */
 	[0x41 - FONT_START_CHAR] = {
-		0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x01c00000, 0x03c00000,
-		0x03e00000, 0x07e00000, 0x07600000, 0x06700000, 0x0e700000, 0x0e300000, 0x0c380000, 0x1c380000,
-		0x181c0000, 0x3ffc0000, 0x3ffc0000, 0x300e0000, 0x700e0000, 0x70060000, 0xe0070000, 0x00000000,
-		0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x30,
+		0x30, 0x1c, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x68, 0xff,
+		0xff, 0xd0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc9, 0xff,
+		0xff, 0xff, 0x30, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x2c, 0xff, 0xff,
+		0xfe, 0xff, 0x90, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x8d, 0xff, 0xee,
+		0xa0, 0xff, 0xeb, 0x07, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x05, 0xeb, 0xff, 0x9e,
+		0x4a, 0xff, 0xff, 0x54, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x51, 0xff, 0xff, 0x45,
+		0x06, 0xed, 0xff, 0xb4, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0xb4, 0xff, 0xe6, 0x03,
+		0x00, 0x97, 0xff, 0xfc, 0x18, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x18, 0xfc, 0xff, 0x8c, 0x00,
+		0x00, 0x3b, 0xff, 0xff, 0x75, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x78, 0xff, 0xff, 0x2e, 0x00,
+		0x00, 0x01, 0xde, 0xff, 0xd8, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x01, 0xd8, 0xff, 0xd2, 0x00, 0x00,
+		0x00, 0x00, 0x83, 0xff, 0xff, 0x38, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x3c, 0xff, 0xff, 0xc0, 0x74, 0x74,
+		0x74, 0x74, 0x96, 0xff, 0xff, 0x98, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x9c, 0xff, 0xff, 0xff, 0xff, 0xff,
+		0xff, 0xff, 0xff, 0xff, 0xff, 0xf0, 0x0a, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x0c, 0xf4, 0xff, 0xe5, 0xbc, 0xbc, 0xbc,
+		0xbc, 0xbc, 0xbc, 0xd1, 0xff, 0xff, 0x5c, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x61, 0xff, 0xff, 0x5c, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x16, 0xfc, 0xff, 0xbc, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0xc4, 0xff, 0xf4, 0x0c, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0xb6, 0xff, 0xfe, 0x1e,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x25, 0xff, 0xff, 0xa4, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x5a, 0xff, 0xff, 0x7f,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x87, 0xff, 0xff, 0x46, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x0a, 0xf4, 0xff, 0xde,
+		0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 	}, /* 'A' */
 	[0x42 - FONT_START_CHAR] = {
-		0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xff800000, 0xffc00000,
-		0xc0e00000, 0xc0600000, 0xc0600000, 0xc0600000, 0xc0e00000, 0xffc00000, 0xffc00000, 0xc0e00000,
-		0xc0700000, 0xc0700000, 0xc0700000, 0xc0700000, 0xc0e00000, 0xffe00000, 0xff800000, 0x00000000,
-		0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x07, 0x30, 0x30, 0x30, 0x30, 0x30, 0x30,
+		0x2f, 0x15, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x24, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+		0xff, 0xff, 0xcc, 0x42, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x24, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+		0xff, 0xff, 0xff, 0xfd, 0x5a, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x24, 0xff, 0xff, 0x8b, 0x24, 0x24, 0x24,
+		0x2c, 0x75, 0xf9, 0xff, 0xf2, 0x10, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x24, 0xff, 0xff, 0x78, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x73, 0xff, 0xff, 0x55, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x24, 0xff, 0xff, 0x78, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x2b, 0xff, 0xff, 0x68, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x24, 0xff, 0xff, 0x78, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x52, 0xff, 0xff, 0x42, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x24, 0xff, 0xff, 0x78, 0x00, 0x00, 0x00,
+		0x00, 0x2e, 0xe2, 0xff, 0xcf, 0x03, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x24, 0xff, 0xff, 0xec, 0xd8, 0xd8, 0xd8,
+		0xe0, 0xff, 0xff, 0xcb, 0x1c, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x24, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+		0xff, 0xff, 0xff, 0xa5, 0x1e, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x24, 0xff, 0xff, 0xa4, 0x50, 0x50, 0x50,
+		0x53, 0x7e, 0xee, 0xff, 0xe9, 0x21, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x24, 0xff, 0xff, 0x78, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x2a, 0xf9, 0xff, 0xad, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x24, 0xff, 0xff, 0x78, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0xb5, 0xff, 0xf5, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x24, 0xff, 0xff, 0x78, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0xb6, 0xff, 0xfc, 0x01, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x24, 0xff, 0xff, 0x78, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x2b, 0xfa, 0xff, 0xd0, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x24, 0xff, 0xff, 0xa0, 0x4c, 0x4c, 0x4c,
+		0x4d, 0x76, 0xec, 0xff, 0xff, 0x60, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x24, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+		0xff, 0xff, 0xff, 0xff, 0x95, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x24, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+		0xff, 0xf3, 0xc0, 0x54, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 	}, /* 'B' */
 	[0x43 - FONT_START_CHAR] = {
-		0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00c00000, 0x0ff80000,
-		0x1ffe0000, 0x3c1e0000, 0x78040000, 0x70000000, 0xe0000000, 0xe0000000, 0xe0000000, 0xe0000000,
-		0xe0000000, 0xe0000000, 0xe0000000, 0x70040000, 0x78060000, 0x3e1e0000, 0x1ffc0000, 0x07f80000,
-		0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x07, 0x44,
+		0x75, 0x8c, 0x8a, 0x6a, 0x2d, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x08, 0x7c, 0xec, 0xff,
+		0xff, 0xff, 0xff, 0xff, 0xff, 0xcd, 0x44, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x1c, 0xd1, 0xff, 0xff, 0xff,
+		0xff, 0xf6, 0xfa, 0xff, 0xff, 0xff, 0xff, 0x82,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x13, 0xdd, 0xff, 0xff, 0xda, 0x61,
+		0x16, 0x00, 0x01, 0x26, 0x82, 0xf4, 0xff, 0xf7,
+		0x25, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0xae, 0xff, 0xff, 0xaa, 0x09, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x28, 0xd4, 0x3e,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x39, 0xff, 0xff, 0xc6, 0x04, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x98, 0xff, 0xff, 0x37, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0xd8, 0xff, 0xde, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0xf9, 0xff, 0xb1, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x01, 0xff, 0xff, 0xa7, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0xf3, 0xff, 0xb9, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0xcb, 0xff, 0xed, 0x04, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x85, 0xff, 0xff, 0x56, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x22, 0xfb, 0xff, 0xe3, 0x16, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x33, 0x1f,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x88, 0xff, 0xff, 0xd2, 0x24, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x45, 0xed, 0xe1,
+		0x25, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x06, 0xbb, 0xff, 0xff, 0xf6, 0x96,
+		0x4b, 0x29, 0x2d, 0x5a, 0xb6, 0xff, 0xff, 0xff,
+		0x75, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x09, 0xa8, 0xff, 0xff, 0xff,
+		0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xfc, 0x7b,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x4e, 0xc6, 0xff,
+		0xff, 0xff, 0xff, 0xff, 0xf9, 0xab, 0x2e, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x19,
+		0x4a, 0x60, 0x5e, 0x41, 0x0c, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 	}, /* 'C' */
 	[0x44 - FONT_START_CHAR] = {
-		0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xff800000, 0xffe00000,
-		0xc1f00000, 0xc0780000, 0xc0380000, 0xc01c0000, 0xc01c0000, 0xc01c0000, 0xc01c0000, 0xc01c0000,
-		0xc01c0000, 0xc01c0000, 0xc0380000, 0xc0780000, 0xc1f00000, 0xffe00000, 0xff800000, 0x00000000,
-		0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x07, 0x30, 0x30, 0x30, 0x30, 0x30, 0x2e,
+		0x1f, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x24, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+		0xff, 0xf6, 0xb9, 0x54, 0x01, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x24, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+		0xff, 0xff, 0xff, 0xff, 0xc3, 0x1a, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x24, 0xff, 0xff, 0x9e, 0x48, 0x48, 0x4a,
+		0x61, 0x97, 0xef, 0xff, 0xff, 0xdf, 0x19, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x24, 0xff, 0xff, 0x78, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x11, 0xac, 0xff, 0xff, 0xbd, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x24, 0xff, 0xff, 0x78, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x03, 0xb9, 0xff, 0xff, 0x48,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x24, 0xff, 0xff, 0x78, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x28, 0xff, 0xff, 0xa8,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x24, 0xff, 0xff, 0x78, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0xd1, 0xff, 0xe4,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x24, 0xff, 0xff, 0x78, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0xa5, 0xff, 0xff,
+		0x06, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x24, 0xff, 0xff, 0x78, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x9b, 0xff, 0xff,
+		0x0d, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x24, 0xff, 0xff, 0x78, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0xac, 0xff, 0xfc,
+		0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x24, 0xff, 0xff, 0x78, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0xdd, 0xff, 0xd9,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x24, 0xff, 0xff, 0x78, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x3c, 0xff, 0xff, 0x97,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x24, 0xff, 0xff, 0x78, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x0a, 0xcf, 0xff, 0xff, 0x31,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x24, 0xff, 0xff, 0x78, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x26, 0xc8, 0xff, 0xff, 0x9a, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x24, 0xff, 0xff, 0xb1, 0x6c, 0x6c, 0x6e,
+		0x82, 0xbb, 0xfd, 0xff, 0xff, 0xbe, 0x09, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x24, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+		0xff, 0xff, 0xff, 0xfd, 0x92, 0x08, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x24, 0xff, 0xff, 0xff, 0xff, 0xff, 0xfe,
+		0xef, 0xca, 0x88, 0x27, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 	}, /* 'D' */
 	[0x45 - FONT_START_CHAR] = {
-		0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xffc00000, 0xffc00000,
-		0xc0000000, 0xc0000000, 0xc0000000, 0xc0000000, 0xc0000000, 0xff800000, 0xff800000, 0xff800000,
-		0xc0000000, 0xc0000000, 0xc0000000, 0xc0000000, 0xc0000000, 0xffc00000, 0xffc00000, 0x00000000,
-		0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x07, 0x30, 0x30, 0x30, 0x30, 0x30, 0x30,
+		0x30, 0x30, 0x30, 0x2b, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x24, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+		0xff, 0xff, 0xff, 0xe4, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x24, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+		0xff, 0xff, 0xff, 0xe4, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x24, 0xff, 0xff, 0x9b, 0x48, 0x48, 0x48,
+		0x48, 0x48, 0x48, 0x40, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x24, 0xff, 0xff, 0x74, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x24, 0xff, 0xff, 0x74, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x24, 0xff, 0xff, 0x74, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x24, 0xff, 0xff, 0x74, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x24, 0xff, 0xff, 0xdd, 0xc0, 0xc0, 0xc0,
+		0xc0, 0xc0, 0xc0, 0x5d, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x24, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+		0xff, 0xff, 0xff, 0x7c, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x24, 0xff, 0xff, 0xc5, 0x90, 0x90, 0x90,
+		0x90, 0x90, 0x90, 0x46, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x24, 0xff, 0xff, 0x74, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x24, 0xff, 0xff, 0x74, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x24, 0xff, 0xff, 0x74, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x24, 0xff, 0xff, 0x74, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x24, 0xff, 0xff, 0xb3, 0x74, 0x74, 0x74,
+		0x74, 0x74, 0x74, 0x74, 0x04, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x24, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+		0xff, 0xff, 0xff, 0xff, 0x08, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x24, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+		0xff, 0xff, 0xff, 0xff, 0x08, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 	}, /* 'E' */
 	[0x46 - FONT_START_CHAR] = {
-		0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xffc00000, 0xffc00000,
-		0xc0000000, 0xc0000000, 0xc0000000, 0xc0000000, 0xc0000000, 0xff800000, 0xff800000, 0xff800000,
-		0xc0000000, 0xc0000000, 0xc0000000, 0xc0000000, 0xc0000000, 0xc0000000, 0xc0000000, 0x00000000,
-		0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x07, 0x30, 0x30, 0x30, 0x30, 0x30, 0x30,
+		0x30, 0x30, 0x30, 0x21, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x24, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+		0xff, 0xff, 0xff, 0xb0, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x24, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+		0xff, 0xff, 0xff, 0xb0, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x24, 0xff, 0xff, 0xa1, 0x48, 0x48, 0x48,
+		0x48, 0x48, 0x48, 0x32, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x24, 0xff, 0xff, 0x7c, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x24, 0xff, 0xff, 0x7c, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x24, 0xff, 0xff, 0x7c, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x24, 0xff, 0xff, 0x7c, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x24, 0xff, 0xff, 0xc3, 0x88, 0x88, 0x88,
+		0x88, 0x88, 0x88, 0x31, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x24, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+		0xff, 0xff, 0xff, 0x5c, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x24, 0xff, 0xff, 0xec, 0xd8, 0xd8, 0xd8,
+		0xd8, 0xd8, 0xd8, 0x4e, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x24, 0xff, 0xff, 0x7c, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x24, 0xff, 0xff, 0x7c, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x24, 0xff, 0xff, 0x7c, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x24, 0xff, 0xff, 0x7c, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x24, 0xff, 0xff, 0x7c, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x24, 0xff, 0xff, 0x7c, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x24, 0xff, 0xff, 0x7c, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 	}, /* 'F' */
 	[0x47 - FONT_START_CHAR] = {
-		0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00c00000, 0x07f80000,
-		0x1ffe0000, 0x3c0e0000, 0x78040000, 0x70000000, 0xe0000000, 0xe0000000, 0xe0000000, 0xe07f8000,
-		0xe07f8000, 0xe0018000, 0xe0038000, 0x70038000, 0x78070000, 0x3e0f0000, 0x1ffe0000, 0x07f80000,
-		0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x04, 0x41,
+		0x75, 0x8b, 0x8a, 0x71, 0x3c, 0x03, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x04, 0x72, 0xea, 0xff,
+		0xff, 0xff, 0xff, 0xff, 0xff, 0xe5, 0x6a, 0x02,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x14, 0xc4, 0xff, 0xff, 0xff,
+		0xff, 0xee, 0xf0, 0xff, 0xff, 0xff, 0xff, 0xb3,
+		0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x0e, 0xd1, 0xff, 0xff, 0xd8, 0x5e,
+		0x11, 0x00, 0x00, 0x16, 0x69, 0xe5, 0xff, 0xd5,
+		0x14, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0xa2, 0xff, 0xff, 0xa7, 0x08, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x13, 0xa5, 0x18,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x32, 0xff, 0xff, 0xc3, 0x04, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x95, 0xff, 0xff, 0x33, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0xd6, 0xff, 0xda, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0xf9, 0xff, 0xa9, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x0a, 0x5c, 0x5c, 0x5c, 0x5c, 0x5c, 0x5c,
+		0x5c, 0x5c, 0x21, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x01, 0xff, 0xff, 0x9f, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x1c, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+		0xff, 0xff, 0x61, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0xf2, 0xff, 0xb1, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x19, 0xe4, 0xe4, 0xe4, 0xe4, 0xe4, 0xe9,
+		0xff, 0xff, 0x5f, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0xc8, 0xff, 0xe6, 0x02, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x47,
+		0xff, 0xff, 0x47, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x7e, 0xff, 0xff, 0x4d, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x89,
+		0xff, 0xfe, 0x15, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x19, 0xf7, 0xff, 0xdd, 0x11, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x17, 0xef,
+		0xff, 0xbe, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x77, 0xff, 0xff, 0xcb, 0x1b, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x16, 0xc9, 0xff,
+		0xff, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x02, 0xa6, 0xff, 0xff, 0xf1, 0x86,
+		0x36, 0x12, 0x12, 0x33, 0x7d, 0xec, 0xff, 0xff,
+		0x86, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x03, 0x8f, 0xff, 0xff, 0xff,
+		0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x85,
+		0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x3c, 0xb8, 0xfd,
+		0xff, 0xff, 0xff, 0xff, 0xfd, 0xb9, 0x3a, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x12,
+		0x44, 0x5e, 0x5e, 0x43, 0x12, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 	}, /* 'G' */
 	[0x48 - FONT_START_CHAR] = {
-		0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xc0180000, 0xc0180000,
-		0xc0180000, 0xc0180000, 0xc0180000, 0xc0180000, 0xc0180000, 0xfff80000, 0xfff80000, 0xc0180000,
-		0xc0180000, 0xc0180000, 0xc0180000, 0xc0180000, 0xc0180000, 0xc0180000, 0xc0180000, 0x00000000,
-		0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x07, 0x30, 0x30, 0x17, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x10, 0x30, 0x30, 0x0e,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x24, 0xff, 0xff, 0x78, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x54, 0xff, 0xff, 0x4c,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x24, 0xff, 0xff, 0x78, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x54, 0xff, 0xff, 0x4c,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x24, 0xff, 0xff, 0x78, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x54, 0xff, 0xff, 0x4c,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x24, 0xff, 0xff, 0x78, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x54, 0xff, 0xff, 0x4c,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x24, 0xff, 0xff, 0x78, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x54, 0xff, 0xff, 0x4c,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x24, 0xff, 0xff, 0x78, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x54, 0xff, 0xff, 0x4c,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x24, 0xff, 0xff, 0x7b, 0x04, 0x04, 0x04,
+		0x04, 0x04, 0x04, 0x04, 0x57, 0xff, 0xff, 0x4c,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x24, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+		0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x4c,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x24, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+		0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x4c,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x24, 0xff, 0xff, 0xb6, 0x74, 0x74, 0x74,
+		0x74, 0x74, 0x74, 0x74, 0xa4, 0xff, 0xff, 0x4c,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x24, 0xff, 0xff, 0x78, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x54, 0xff, 0xff, 0x4c,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x24, 0xff, 0xff, 0x78, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x54, 0xff, 0xff, 0x4c,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x24, 0xff, 0xff, 0x78, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x54, 0xff, 0xff, 0x4c,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x24, 0xff, 0xff, 0x78, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x54, 0xff, 0xff, 0x4c,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x24, 0xff, 0xff, 0x78, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x54, 0xff, 0xff, 0x4c,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x24, 0xff, 0xff, 0x78, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x54, 0xff, 0xff, 0x4c,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x24, 0xff, 0xff, 0x78, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x54, 0xff, 0xff, 0x4c,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 	}, /* 'H' */
 	[0x49 - FONT_START_CHAR] = {
-		0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xe0000000, 0xe0000000,
-		0xe0000000, 0xe0000000, 0xe0000000, 0xe0000000, 0xe0000000, 0xe0000000, 0xe0000000, 0xe0000000,
-		0xe0000000, 0xe0000000, 0xe0000000, 0xe0000000, 0xe0000000, 0xe0000000, 0xe0000000, 0x00000000,
-		0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x07, 0x30, 0x30, 0x18, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x24, 0xff, 0xff, 0x80, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x24, 0xff, 0xff, 0x80, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x24, 0xff, 0xff, 0x80, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x24, 0xff, 0xff, 0x80, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x24, 0xff, 0xff, 0x80, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x24, 0xff, 0xff, 0x80, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x24, 0xff, 0xff, 0x80, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x24, 0xff, 0xff, 0x80, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x24, 0xff, 0xff, 0x80, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x24, 0xff, 0xff, 0x80, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x24, 0xff, 0xff, 0x80, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x24, 0xff, 0xff, 0x80, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x24, 0xff, 0xff, 0x80, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x24, 0xff, 0xff, 0x80, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x24, 0xff, 0xff, 0x80, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x24, 0xff, 0xff, 0x80, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x24, 0xff, 0xff, 0x80, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 	}, /* 'I' */
 	[0x4a - FONT_START_CHAR] = {
-		0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00600000, 0x00600000,
-		0x00600000, 0x00600000, 0x00600000, 0x00600000, 0x00600000, 0x00600000, 0x00600000, 0x00600000,
-		0x00600000, 0x00600000, 0x20600000, 0xe0e00000, 0x71e00000, 0x3fc00000, 0x1f800000, 0x00000000,
-		0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x0b, 0x30, 0x30, 0x12, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x3c, 0xff, 0xff, 0x60, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x3c, 0xff, 0xff, 0x60, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x3c, 0xff, 0xff, 0x60, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x3c, 0xff, 0xff, 0x60, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x3c, 0xff, 0xff, 0x60, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x3c, 0xff, 0xff, 0x60, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x3c, 0xff, 0xff, 0x60, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x3c, 0xff, 0xff, 0x60, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x3c, 0xff, 0xff, 0x60, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x3c, 0xff, 0xff, 0x60, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x3c, 0xff, 0xff, 0x60, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x3d, 0xff, 0xff, 0x5f, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x3a, 0x8f, 0x01, 0x00, 0x00, 0x00, 0x00,
+		0x52, 0xff, 0xff, 0x53, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x61, 0xff, 0xff, 0x5d, 0x00, 0x00, 0x00, 0x00,
+		0xa8, 0xff, 0xff, 0x23, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x13, 0xf0, 0xff, 0xf6, 0x66, 0x1c, 0x28, 0x92,
+		0xff, 0xff, 0xc7, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x52, 0xfd, 0xff, 0xff, 0xff, 0xff, 0xff,
+		0xff, 0xf5, 0x31, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x4a, 0xe0, 0xff, 0xff, 0xff, 0xff,
+		0xd1, 0x33, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x03, 0x3b, 0x5e, 0x5d, 0x32,
+		0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 	}, /* 'J' */
 	[0x4b - FONT_START_CHAR] = {
-		0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xc0780000, 0xc0f00000,
-		0xc1e00000, 0xc1c00000, 0xc3800000, 0xc7000000, 0xce000000, 0xde000000, 0xff000000, 0xff000000,
-		0xf3800000, 0xe1c00000, 0xc1c00000, 0xc0e00000, 0xc0700000, 0xc0700000, 0xc0380000, 0x00000000,
-		0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x07, 0x30, 0x30, 0x17, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x11, 0x30, 0x30, 0x2f, 0x01,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x24, 0xff, 0xff, 0x78, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x0c, 0xcf, 0xff, 0xff, 0x77, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x24, 0xff, 0xff, 0x78, 0x00, 0x00, 0x00,
+		0x00, 0x02, 0xb2, 0xff, 0xff, 0x9b, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x24, 0xff, 0xff, 0x78, 0x00, 0x00, 0x00,
+		0x00, 0x8c, 0xff, 0xff, 0xb8, 0x04, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x24, 0xff, 0xff, 0x78, 0x00, 0x00, 0x00,
+		0x65, 0xff, 0xff, 0xd0, 0x0d, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x24, 0xff, 0xff, 0x78, 0x00, 0x00, 0x42,
+		0xfb, 0xff, 0xe4, 0x1c, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x24, 0xff, 0xff, 0x78, 0x00, 0x25, 0xee,
+		0xff, 0xf3, 0x31, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x24, 0xff, 0xff, 0x78, 0x11, 0xd9, 0xff,
+		0xfc, 0x48, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x24, 0xff, 0xff, 0x7d, 0xbd, 0xff, 0xff,
+		0xe1, 0x09, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x24, 0xff, 0xff, 0xee, 0xff, 0xff, 0xff,
+		0xff, 0x92, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x24, 0xff, 0xff, 0xff, 0xff, 0xac, 0xd5,
+		0xff, 0xff, 0x45, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x24, 0xff, 0xff, 0xff, 0xc4, 0x08, 0x33,
+		0xfb, 0xff, 0xe4, 0x11, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x24, 0xff, 0xff, 0xd9, 0x13, 0x00, 0x00,
+		0x7d, 0xff, 0xff, 0xa6, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x24, 0xff, 0xff, 0x7a, 0x00, 0x00, 0x00,
+		0x04, 0xc8, 0xff, 0xff, 0x5a, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x24, 0xff, 0xff, 0x78, 0x00, 0x00, 0x00,
+		0x00, 0x25, 0xf5, 0xff, 0xee, 0x1b, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x24, 0xff, 0xff, 0x78, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x6a, 0xff, 0xff, 0xbb, 0x01, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x24, 0xff, 0xff, 0x78, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x01, 0xb8, 0xff, 0xff, 0x6e, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x24, 0xff, 0xff, 0x78, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x1b, 0xed, 0xff, 0xf7, 0x28,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 	}, /* 'K' */
 	[0x4c - FONT_START_CHAR] = {
-		0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xc0000000, 0xc0000000,
-		0xc0000000, 0xc0000000, 0xc0000000, 0xc0000000, 0xc0000000, 0xc0000000, 0xc0000000, 0xc0000000,
-		0xc0000000, 0xc0000000, 0xc0000000, 0xc0000000, 0xc0000000, 0xffc00000, 0xffc00000, 0x00000000,
-		0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x07, 0x30, 0x30, 0x17, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x24, 0xff, 0xff, 0x78, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x24, 0xff, 0xff, 0x78, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x24, 0xff, 0xff, 0x78, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x24, 0xff, 0xff, 0x78, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x24, 0xff, 0xff, 0x78, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x24, 0xff, 0xff, 0x78, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x24, 0xff, 0xff, 0x78, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x24, 0xff, 0xff, 0x78, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x24, 0xff, 0xff, 0x78, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x24, 0xff, 0xff, 0x78, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x24, 0xff, 0xff, 0x78, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x24, 0xff, 0xff, 0x78, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x24, 0xff, 0xff, 0x78, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x24, 0xff, 0xff, 0x78, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x24, 0xff, 0xff, 0xb8, 0x78, 0x78, 0x78,
+		0x78, 0x78, 0x78, 0x71, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x24, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+		0xff, 0xff, 0xff, 0xf0, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x24, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+		0xff, 0xff, 0xff, 0xf0, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 	}, /* 'L' */
 	[0x4d - FONT_START_CHAR] = {
-		0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xf003c000, 0xf007c000,
-		0xf007c000, 0xf807c000, 0xd80fc000, 0xdc0dc000, 0xdc1dc000, 0xcc1dc000, 0xce19c000, 0xc639c000,
-		0xc731c000, 0xc771c000, 0xc371c000, 0xc3e1c000, 0xc1e1c000, 0xc1c1c000, 0xc1c1c000, 0x00000000,
-		0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x07, 0x30, 0x30, 0x30, 0x12, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x2d, 0x30, 0x30, 0x1c, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x24, 0xff, 0xff, 0xff, 0x9e, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x2d,
+		0xff, 0xff, 0xff, 0x94, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x24, 0xff, 0xff, 0xff, 0xf5, 0x0e, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x93,
+		0xff, 0xff, 0xff, 0x94, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x24, 0xff, 0xff, 0xff, 0xff, 0x68, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0xef,
+		0xff, 0xff, 0xff, 0x94, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x24, 0xff, 0xff, 0xfc, 0xff, 0xce, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x5c, 0xff,
+		0xff, 0xfc, 0xff, 0x94, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x24, 0xff, 0xff, 0xae, 0xff, 0xff, 0x33,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc2, 0xff,
+		0xc6, 0xea, 0xff, 0x94, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x24, 0xff, 0xff, 0x67, 0xe6, 0xff, 0x99,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x28, 0xff, 0xff,
+		0x60, 0xf2, 0xff, 0x94, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x24, 0xff, 0xff, 0x6a, 0x84, 0xff, 0xf2,
+		0x0c, 0x00, 0x00, 0x00, 0x00, 0x8b, 0xff, 0xf0,
+		0x0a, 0xfa, 0xff, 0x94, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x24, 0xff, 0xff, 0x6c, 0x20, 0xfe, 0xff,
+		0x63, 0x00, 0x00, 0x00, 0x06, 0xeb, 0xff, 0x93,
+		0x00, 0xfc, 0xff, 0x94, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x24, 0xff, 0xff, 0x6c, 0x00, 0xb7, 0xff,
+		0xc9, 0x00, 0x00, 0x00, 0x56, 0xff, 0xff, 0x2d,
+		0x00, 0xfc, 0xff, 0x94, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x24, 0xff, 0xff, 0x6c, 0x00, 0x51, 0xff,
+		0xff, 0x2d, 0x00, 0x00, 0xbb, 0xff, 0xc6, 0x00,
+		0x00, 0xfc, 0xff, 0x94, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x24, 0xff, 0xff, 0x6c, 0x00, 0x04, 0xe6,
+		0xff, 0x93, 0x00, 0x22, 0xfe, 0xff, 0x60, 0x00,
+		0x00, 0xfc, 0xff, 0x94, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x24, 0xff, 0xff, 0x6c, 0x00, 0x00, 0x84,
+		0xff, 0xf0, 0x0a, 0x85, 0xff, 0xef, 0x0a, 0x00,
+		0x00, 0xfc, 0xff, 0x94, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x24, 0xff, 0xff, 0x6c, 0x00, 0x00, 0x20,
+		0xfe, 0xff, 0x62, 0xe6, 0xff, 0x93, 0x00, 0x00,
+		0x00, 0xfc, 0xff, 0x94, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x24, 0xff, 0xff, 0x6c, 0x00, 0x00, 0x00,
+		0xb6, 0xff, 0xf0, 0xff, 0xff, 0x2c, 0x00, 0x00,
+		0x00, 0xfc, 0xff, 0x94, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x24, 0xff, 0xff, 0x6c, 0x00, 0x00, 0x00,
+		0x50, 0xff, 0xff, 0xff, 0xc5, 0x00, 0x00, 0x00,
+		0x00, 0xfc, 0xff, 0x94, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x24, 0xff, 0xff, 0x6c, 0x00, 0x00, 0x00,
+		0x04, 0xe6, 0xff, 0xff, 0x5e, 0x00, 0x00, 0x00,
+		0x00, 0xfc, 0xff, 0x94, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x24, 0xff, 0xff, 0x6c, 0x00, 0x00, 0x00,
+		0x00, 0x83, 0xff, 0xef, 0x08, 0x00, 0x00, 0x00,
+		0x00, 0xfc, 0xff, 0x94, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 	}, /* 'M' */
 	[0x4e - FONT_START_CHAR] = {
-		0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xe0180000, 0xf0180000,
-		0xf8180000, 0xf8180000, 0xdc180000, 0xcc180000, 0xce180000, 0xc7180000, 0xc7180000, 0xc3980000,
-		0xc1d80000, 0xc1d80000, 0xc0f80000, 0xc0780000, 0xc0780000, 0xc0380000, 0xc0180000, 0x00000000,
-		0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x07, 0x30, 0x30, 0x28, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x08, 0x30, 0x30, 0x14,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x24, 0xff, 0xff, 0xfe, 0x3a, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x2c, 0xff, 0xff, 0x68,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x24, 0xff, 0xff, 0xff, 0xd4, 0x06, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x2c, 0xff, 0xff, 0x68,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x24, 0xff, 0xff, 0xff, 0xff, 0x7e, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x2c, 0xff, 0xff, 0x68,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x24, 0xff, 0xff, 0xf7, 0xff, 0xf9, 0x27,
+		0x00, 0x00, 0x00, 0x00, 0x2c, 0xff, 0xff, 0x68,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x24, 0xff, 0xff, 0x82, 0xf7, 0xff, 0xc2,
+		0x01, 0x00, 0x00, 0x00, 0x2c, 0xff, 0xff, 0x68,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x24, 0xff, 0xff, 0x66, 0x78, 0xff, 0xff,
+		0x67, 0x00, 0x00, 0x00, 0x2c, 0xff, 0xff, 0x68,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x24, 0xff, 0xff, 0x6d, 0x05, 0xd0, 0xff,
+		0xf0, 0x18, 0x00, 0x00, 0x2c, 0xff, 0xff, 0x68,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x24, 0xff, 0xff, 0x70, 0x00, 0x34, 0xfd,
+		0xff, 0xac, 0x00, 0x00, 0x2c, 0xff, 0xff, 0x68,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x24, 0xff, 0xff, 0x70, 0x00, 0x00, 0x8f,
+		0xff, 0xff, 0x4f, 0x00, 0x2c, 0xff, 0xff, 0x68,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x24, 0xff, 0xff, 0x70, 0x00, 0x00, 0x0b,
+		0xe0, 0xff, 0xe3, 0x0e, 0x2b, 0xff, 0xff, 0x68,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x24, 0xff, 0xff, 0x70, 0x00, 0x00, 0x00,
+		0x47, 0xff, 0xff, 0x94, 0x25, 0xff, 0xff, 0x68,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x24, 0xff, 0xff, 0x70, 0x00, 0x00, 0x00,
+		0x00, 0xa4, 0xff, 0xfe, 0x58, 0xff, 0xff, 0x68,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x24, 0xff, 0xff, 0x70, 0x00, 0x00, 0x00,
+		0x00, 0x14, 0xec, 0xff, 0xe6, 0xff, 0xff, 0x68,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x24, 0xff, 0xff, 0x70, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x5c, 0xff, 0xff, 0xff, 0xff, 0x68,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x24, 0xff, 0xff, 0x70, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0xb8, 0xff, 0xff, 0xff, 0x68,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x24, 0xff, 0xff, 0x70, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x20, 0xf5, 0xff, 0xff, 0x68,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x24, 0xff, 0xff, 0x70, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x71, 0xff, 0xff, 0x68,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 	}, /* 'N' */
 	[0x4f - FONT_START_CHAR] = {
-		0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00c00000, 0x0ff80000,
-		0x1ffe0000, 0x3c1f0000, 0x78070000, 0x70038000, 0xe0038000, 0xe001c000, 0xe001c000, 0xe001c000,
-		0xe001c000, 0xe0018000, 0xe0038000, 0x70038000, 0x78070000, 0x3e1e0000, 0x1ffc0000, 0x07f80000,
-		0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x07, 0x44,
+		0x78, 0x8c, 0x87, 0x69, 0x2d, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x07, 0x7c, 0xec, 0xff,
+		0xff, 0xff, 0xff, 0xff, 0xff, 0xcf, 0x47, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x1b, 0xcc, 0xff, 0xff, 0xff,
+		0xff, 0xf4, 0xfa, 0xff, 0xff, 0xff, 0xff, 0x8f,
+		0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x12, 0xda, 0xff, 0xff, 0xda, 0x5f,
+		0x14, 0x00, 0x01, 0x29, 0x84, 0xf5, 0xff, 0xff,
+		0x93, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0xac, 0xff, 0xff, 0xad, 0x09, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x29, 0xe2, 0xff,
+		0xff, 0x53, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x38, 0xff, 0xff, 0xc9, 0x06, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x2b, 0xf8,
+		0xff, 0xdc, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x98, 0xff, 0xff, 0x3a, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x8f,
+		0xff, 0xff, 0x3f, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0xd7, 0xff, 0xde, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x35,
+		0xff, 0xff, 0x7e, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0xf9, 0xff, 0xad, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x06,
+		0xff, 0xff, 0xa1, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x01, 0xff, 0xff, 0xa3, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0xfb, 0xff, 0xa9, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0xf3, 0xff, 0xb5, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0d,
+		0xff, 0xff, 0x9b, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0xcb, 0xff, 0xeb, 0x03, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x46,
+		0xff, 0xff, 0x73, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x86, 0xff, 0xff, 0x52, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xac,
+		0xff, 0xff, 0x2c, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x22, 0xfb, 0xff, 0xe1, 0x14, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x4e, 0xff,
+		0xff, 0xc1, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x88, 0xff, 0xff, 0xd0, 0x1f, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x51, 0xf6, 0xff,
+		0xfa, 0x32, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x05, 0xba, 0xff, 0xff, 0xf4, 0x8f,
+		0x44, 0x24, 0x2b, 0x58, 0xb4, 0xff, 0xff, 0xff,
+		0x64, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x08, 0xa5, 0xff, 0xff, 0xff,
+		0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf6, 0x5d,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x4c, 0xc7, 0xff,
+		0xff, 0xff, 0xff, 0xff, 0xf7, 0xa1, 0x22, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1a,
+		0x4b, 0x60, 0x5c, 0x3d, 0x0a, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 	}, /* 'O' */
 	[0x50 - FONT_START_CHAR] = {
-		0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xff800000, 0xffc00000,
-		0xc1e00000, 0xc0e00000, 0xc0700000, 0xc0700000, 0xc0700000, 0xc0e00000, 0xc1e00000, 0xffc00000,
-		0xff000000, 0xc0000000, 0xc0000000, 0xc0000000, 0xc0000000, 0xc0000000, 0xc0000000, 0x00000000,
-		0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x07, 0x30, 0x30, 0x30, 0x30, 0x30, 0x30,
+		0x28, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x24, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+		0xff, 0xf9, 0xa9, 0x22, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x24, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+		0xff, 0xff, 0xff, 0xef, 0x31, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x24, 0xff, 0xff, 0x98, 0x3c, 0x3c, 0x3c,
+		0x52, 0xb2, 0xff, 0xff, 0xda, 0x04, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x24, 0xff, 0xff, 0x78, 0x00, 0x00, 0x00,
+		0x00, 0x01, 0xa7, 0xff, 0xff, 0x4c, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x24, 0xff, 0xff, 0x78, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x31, 0xff, 0xff, 0x86, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x24, 0xff, 0xff, 0x78, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x12, 0xff, 0xff, 0x96, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x24, 0xff, 0xff, 0x78, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x32, 0xff, 0xff, 0x83, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x24, 0xff, 0xff, 0x78, 0x00, 0x00, 0x00,
+		0x00, 0x04, 0xb5, 0xff, 0xff, 0x44, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x24, 0xff, 0xff, 0xaa, 0x5c, 0x5c, 0x5d,
+		0x73, 0xcf, 0xff, 0xff, 0xc6, 0x01, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x24, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+		0xff, 0xff, 0xff, 0xd4, 0x1b, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x24, 0xff, 0xff, 0xfc, 0xf8, 0xf8, 0xf8,
+		0xee, 0xc4, 0x6f, 0x08, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x24, 0xff, 0xff, 0x78, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x24, 0xff, 0xff, 0x78, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x24, 0xff, 0xff, 0x78, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x24, 0xff, 0xff, 0x78, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x24, 0xff, 0xff, 0x78, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x24, 0xff, 0xff, 0x78, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 	}, /* 'P' */
 	[0x51 - FONT_START_CHAR] = {
-		0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00c00000, 0x0ff80000,
-		0x1ffe0000, 0x3c1f0000, 0x78070000, 0x70038000, 0xe0038000, 0xe001c000, 0xe001c000, 0xe001c000,
-		0xe001c000, 0xe0018000, 0xe0338000, 0x703b8000, 0x781f0000, 0x3e1e0000, 0x1ffe0000, 0x07ff0000,
-		0x00070000, 0x00020000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x07, 0x44,
+		0x78, 0x8c, 0x87, 0x69, 0x2d, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x07, 0x7c, 0xec, 0xff,
+		0xff, 0xff, 0xff, 0xff, 0xff, 0xcf, 0x47, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x1b, 0xcc, 0xff, 0xff, 0xff,
+		0xff, 0xf4, 0xfa, 0xff, 0xff, 0xff, 0xff, 0x8f,
+		0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x12, 0xda, 0xff, 0xff, 0xda, 0x5f,
+		0x14, 0x00, 0x01, 0x29, 0x84, 0xf5, 0xff, 0xff,
+		0x93, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0xac, 0xff, 0xff, 0xad, 0x09, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x29, 0xe2, 0xff,
+		0xff, 0x53, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x38, 0xff, 0xff, 0xc9, 0x06, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x2b, 0xf8,
+		0xff, 0xdc, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x98, 0xff, 0xff, 0x3a, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x8f,
+		0xff, 0xff, 0x3f, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0xd7, 0xff, 0xde, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x35,
+		0xff, 0xff, 0x7e, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0xf9, 0xff, 0xad, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x06,
+		0xff, 0xff, 0xa1, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x01, 0xff, 0xff, 0xa3, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0xfb, 0xff, 0xa9, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0xf3, 0xff, 0xb5, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0d,
+		0xff, 0xff, 0x9b, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0xcb, 0xff, 0xeb, 0x03, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x2c, 0x00, 0x00, 0x46,
+		0xff, 0xff, 0x73, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x86, 0xff, 0xff, 0x52, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x16, 0xa3, 0xff, 0x50, 0x00, 0xac,
+		0xff, 0xff, 0x2c, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x22, 0xfb, 0xff, 0xe1, 0x14, 0x00, 0x00,
+		0x00, 0x00, 0x23, 0xf5, 0xff, 0xe8, 0x5f, 0xff,
+		0xff, 0xc1, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x88, 0xff, 0xff, 0xd0, 0x1f, 0x00,
+		0x00, 0x00, 0x00, 0x70, 0xff, 0xff, 0xff, 0xff,
+		0xfa, 0x32, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x05, 0xba, 0xff, 0xff, 0xf4, 0x8f,
+		0x44, 0x24, 0x2b, 0x5a, 0xf8, 0xff, 0xff, 0xff,
+		0x64, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x08, 0xa5, 0xff, 0xff, 0xff,
+		0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xeb,
+		0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x4c, 0xc7, 0xff,
+		0xff, 0xff, 0xff, 0xff, 0xf7, 0xc9, 0xff, 0xff,
+		0x9f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1a,
+		0x4b, 0x60, 0x5c, 0x3d, 0x0a, 0x03, 0xcc, 0xff,
+		0xd5, 0x0d, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x2c, 0x78,
+		0x06, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 	}, /* 'Q' */
 	[0x52 - FONT_START_CHAR] = {
-		0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xff800000, 0xffc00000,
-		0xc1e00000, 0xc0e00000, 0xc0700000, 0xc0700000, 0xc0600000, 0xc0e00000, 0xffc00000, 0xff800000,
-		0xc7000000, 0xc3800000, 0xc3800000, 0xc1c00000, 0xc0e00000, 0xc0e00000, 0xc0700000, 0x00000000,
-		0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x07, 0x30, 0x30, 0x30, 0x30, 0x30, 0x30,
+		0x29, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x24, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+		0xff, 0xf9, 0xa7, 0x20, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x24, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+		0xff, 0xff, 0xff, 0xee, 0x34, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x24, 0xff, 0xff, 0x96, 0x38, 0x38, 0x38,
+		0x4b, 0xad, 0xff, 0xff, 0xde, 0x06, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x24, 0xff, 0xff, 0x78, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x9f, 0xff, 0xff, 0x52, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x24, 0xff, 0xff, 0x78, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x2d, 0xff, 0xff, 0x82, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x24, 0xff, 0xff, 0x78, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x23, 0xff, 0xff, 0x85, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x24, 0xff, 0xff, 0x78, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x70, 0xff, 0xff, 0x5b, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x24, 0xff, 0xff, 0x78, 0x00, 0x00, 0x00,
+		0x03, 0x5c, 0xf7, 0xff, 0xec, 0x0d, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x24, 0xff, 0xff, 0xee, 0xdc, 0xdc, 0xdc,
+		0xf1, 0xff, 0xff, 0xfb, 0x4b, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x24, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+		0xff, 0xff, 0xca, 0x3b, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x24, 0xff, 0xff, 0xa6, 0x54, 0x55, 0xe0,
+		0xff, 0xf0, 0x19, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x24, 0xff, 0xff, 0x78, 0x00, 0x00, 0x43,
+		0xff, 0xff, 0xb5, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x24, 0xff, 0xff, 0x78, 0x00, 0x00, 0x00,
+		0x9a, 0xff, 0xff, 0x65, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x24, 0xff, 0xff, 0x78, 0x00, 0x00, 0x00,
+		0x0e, 0xe3, 0xff, 0xf2, 0x20, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x24, 0xff, 0xff, 0x78, 0x00, 0x00, 0x00,
+		0x00, 0x4b, 0xff, 0xff, 0xc0, 0x02, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x24, 0xff, 0xff, 0x78, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0xa5, 0xff, 0xff, 0x71, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x24, 0xff, 0xff, 0x78, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x13, 0xe9, 0xff, 0xf8, 0x29, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 	}, /* 'R' */
 	[0x53 - FONT_START_CHAR] = {
-		0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x06000000, 0x3f800000,
-		0x7fc00000, 0x70e00000, 0xe0400000, 0xe0000000, 0xf0000000, 0x7c000000, 0x3f000000, 0x0fc00000,
-		0x03e00000, 0x00e00000, 0x00700000, 0xc0700000, 0xe0700000, 0xf0e00000, 0x7fe00000, 0x3f800000,
-		0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x2d, 0x71, 0x8d, 0x86,
+		0x5f, 0x14, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x13, 0xb1, 0xff, 0xff, 0xff, 0xff,
+		0xff, 0xf6, 0x71, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x07, 0xce, 0xff, 0xff, 0xf1, 0xcb, 0xda,
+		0xff, 0xff, 0xff, 0x74, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x69, 0xff, 0xff, 0x93, 0x08, 0x00, 0x00,
+		0x35, 0xe3, 0xff, 0xf9, 0x1e, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0xaa, 0xff, 0xf4, 0x05, 0x00, 0x00, 0x00,
+		0x00, 0x3a, 0xc0, 0x56, 0x04, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0xb1, 0xff, 0xf6, 0x09, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x7d, 0xff, 0xff, 0xa1, 0x0a, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x14, 0xe9, 0xff, 0xff, 0xea, 0x85, 0x27,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x2c, 0xda, 0xff, 0xff, 0xff, 0xff,
+		0xcc, 0x61, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x07, 0x6b, 0xd6, 0xff, 0xff,
+		0xff, 0xff, 0xcd, 0x1f, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x32, 0x93,
+		0xf4, 0xff, 0xff, 0xdb, 0x0c, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x17, 0xbb, 0xff, 0xff, 0x74, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x0c, 0x03, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x0e, 0xf3, 0xff, 0xb7, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x1b, 0x98, 0xf3, 0x52, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0xd3, 0xff, 0xc5, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x15, 0xf8, 0xff, 0xd8, 0x0b, 0x00, 0x00, 0x00,
+		0x00, 0x1c, 0xfa, 0xff, 0xa3, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x90, 0xff, 0xff, 0xc7, 0x37, 0x01, 0x02,
+		0x3b, 0xd2, 0xff, 0xff, 0x4c, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x0a, 0xcd, 0xff, 0xff, 0xff, 0xf8, 0xfa,
+		0xff, 0xff, 0xff, 0x9f, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x0c, 0x94, 0xf8, 0xff, 0xff, 0xff,
+		0xff, 0xea, 0x6f, 0x02, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x0f, 0x46, 0x60, 0x5c,
+		0x39, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 	}, /* 'S' */
 	[0x54 - FONT_START_CHAR] = {
-		0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xfff00000, 0xfff00000,
-		0x0e000000, 0x0e000000, 0x0e000000, 0x0e000000, 0x0e000000, 0x0e000000, 0x0e000000, 0x0e000000,
-		0x0e000000, 0x0e000000, 0x0e000000, 0x0e000000, 0x0e000000, 0x0e000000, 0x0e000000, 0x00000000,
-		0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x15, 0x30, 0x30, 0x30, 0x30, 0x30, 0x30, 0x30,
+		0x30, 0x30, 0x30, 0x30, 0x24, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x70, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+		0xff, 0xff, 0xff, 0xff, 0xc0, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x70, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+		0xff, 0xff, 0xff, 0xff, 0xc0, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x20, 0x48, 0x48, 0x48, 0x48, 0xbf, 0xff, 0xfe,
+		0x48, 0x48, 0x48, 0x48, 0x36, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0xa4, 0xff, 0xfc,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0xa4, 0xff, 0xfc,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0xa4, 0xff, 0xfc,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0xa4, 0xff, 0xfc,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0xa4, 0xff, 0xfc,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0xa4, 0xff, 0xfc,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0xa4, 0xff, 0xfc,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0xa4, 0xff, 0xfc,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0xa4, 0xff, 0xfc,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0xa4, 0xff, 0xfc,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0xa4, 0xff, 0xfc,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0xa4, 0xff, 0xfc,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0xa4, 0xff, 0xfc,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0xa4, 0xff, 0xfc,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 	}, /* 'T' */
 	[0x55 - FONT_START_CHAR] = {
-		0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xe01c0000, 0xe01c0000,
-		0xe01c0000, 0xe01c0000, 0xe01c0000, 0xe01c0000, 0xe01c0000, 0xe01c0000, 0xe01c0000, 0xe01c0000,
-		0xe01c0000, 0xe01c0000, 0x60180000, 0x70380000, 0x78780000, 0x3ff00000, 0x1fe00000, 0x00000000,
-		0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x1a, 0x30, 0x30, 0x05, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x02, 0x30, 0x30, 0x1b, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x88, 0xff, 0xff, 0x18, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x08, 0xff, 0xff, 0x90, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x88, 0xff, 0xff, 0x18, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x08, 0xff, 0xff, 0x90, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x88, 0xff, 0xff, 0x18, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x08, 0xff, 0xff, 0x90, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x88, 0xff, 0xff, 0x18, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x08, 0xff, 0xff, 0x90, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x88, 0xff, 0xff, 0x18, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x08, 0xff, 0xff, 0x90, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x88, 0xff, 0xff, 0x18, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x08, 0xff, 0xff, 0x90, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x88, 0xff, 0xff, 0x18, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x08, 0xff, 0xff, 0x90, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x88, 0xff, 0xff, 0x18, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x08, 0xff, 0xff, 0x90, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x88, 0xff, 0xff, 0x18, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x08, 0xff, 0xff, 0x90, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x88, 0xff, 0xff, 0x18, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x08, 0xff, 0xff, 0x90, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x87, 0xff, 0xff, 0x19, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x09, 0xff, 0xff, 0x8f, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x7b, 0xff, 0xff, 0x29, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x19, 0xff, 0xff, 0x83, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x4f, 0xff, 0xff, 0x67, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x5a, 0xff, 0xff, 0x5a, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x0c, 0xf2, 0xff, 0xdf, 0x10, 0x00, 0x00,
+		0x00, 0x00, 0x0c, 0xd6, 0xff, 0xf9, 0x14, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x7a, 0xff, 0xff, 0xd7, 0x4f, 0x15,
+		0x14, 0x4b, 0xd0, 0xff, 0xff, 0x8f, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x03, 0xaf, 0xff, 0xff, 0xff, 0xff,
+		0xff, 0xff, 0xff, 0xff, 0xc3, 0x09, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x03, 0x79, 0xef, 0xff, 0xff,
+		0xff, 0xff, 0xf4, 0x89, 0x08, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x07, 0x3d, 0x5e,
+		0x5f, 0x41, 0x0a, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 	}, /* 'U' */
 	[0x56 - FONT_START_CHAR] = {
-		0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xe00e0000, 0x700e0000,
-		0x700c0000, 0x301c0000, 0x381c0000, 0x38180000, 0x18380000, 0x1c380000, 0x1c700000, 0x0c700000,
-		0x0e600000, 0x0ee00000, 0x06e00000, 0x07c00000, 0x03c00000, 0x03c00000, 0x03800000, 0x00000000,
-		0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x22, 0x30, 0x30, 0x06, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x17, 0x30, 0x30, 0x0f,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x7d, 0xff, 0xff, 0x55, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0xb2, 0xff, 0xfd, 0x1a,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x21, 0xff, 0xff, 0xae, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x13, 0xfa, 0xff, 0xb8, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0xc4, 0xff, 0xf8, 0x0e, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x67, 0xff, 0xff, 0x58, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x69, 0xff, 0xff, 0x5f, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0xc1, 0xff, 0xf1, 0x09, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x13, 0xf9, 0xff, 0xb8, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x1d, 0xfe, 0xff, 0x9c, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0xb0, 0xff, 0xfc, 0x16, 0x00, 0x00,
+		0x00, 0x00, 0x76, 0xff, 0xff, 0x3c, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x54, 0xff, 0xff, 0x6a, 0x00, 0x00,
+		0x00, 0x00, 0xd0, 0xff, 0xdb, 0x01, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x08, 0xf0, 0xff, 0xc2, 0x00, 0x00,
+		0x00, 0x2a, 0xff, 0xff, 0x7e, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x9b, 0xff, 0xfe, 0x1d, 0x00,
+		0x00, 0x85, 0xff, 0xff, 0x21, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x3f, 0xff, 0xff, 0x74, 0x00,
+		0x01, 0xde, 0xff, 0xc0, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x02, 0xe2, 0xff, 0xce, 0x00,
+		0x39, 0xff, 0xff, 0x60, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x87, 0xff, 0xff, 0x26,
+		0x93, 0xff, 0xf6, 0x0c, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x2b, 0xff, 0xff, 0x7b,
+		0xe7, 0xff, 0xa4, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0xcf, 0xff, 0xf0,
+		0xff, 0xff, 0x44, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x72, 0xff, 0xff,
+		0xff, 0xe2, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x19, 0xfd, 0xff,
+		0xff, 0x86, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xbb, 0xff,
+		0xff, 0x28, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 	}, /* 'V' */
 	[0x57 - FONT_START_CHAR] = {
-		0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xe0380e00, 0x70380c00,
-		0x703c1c00, 0x707c1c00, 0x306c1c00, 0x386e1800, 0x38ee3800, 0x38e63800, 0x18c63000, 0x1dc73000,
-		0x1dc37000, 0x0d837000, 0x0d83e000, 0x0f81e000, 0x0f01e000, 0x0701e000, 0x0701c000, 0x00000000,
-		0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x1c, 0x30, 0x30, 0x09, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x1b, 0x30, 0x2e, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x2f, 0x30, 0x26, 0x00,
+		0x6d, 0xff, 0xff, 0x54, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0xbe, 0xff, 0xff, 0x20, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x20, 0xff, 0xff, 0xa1, 0x00,
+		0x29, 0xff, 0xff, 0x94, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x12, 0xfc, 0xff, 0xff, 0x6b, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x60, 0xff, 0xff, 0x5c, 0x00,
+		0x00, 0xe3, 0xff, 0xd4, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x5c, 0xff, 0xff, 0xff, 0xb4, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x9f, 0xff, 0xff, 0x18, 0x00,
+		0x00, 0x9f, 0xff, 0xff, 0x15, 0x00, 0x00, 0x00,
+		0x00, 0xaa, 0xff, 0xfb, 0xff, 0xf7, 0x09, 0x00,
+		0x00, 0x00, 0x00, 0xdc, 0xff, 0xd2, 0x00, 0x00,
+		0x00, 0x5b, 0xff, 0xff, 0x54, 0x00, 0x00, 0x00,
+		0x07, 0xf3, 0xff, 0x8c, 0xff, 0xff, 0x4c, 0x00,
+		0x00, 0x00, 0x1c, 0xff, 0xff, 0x8d, 0x00, 0x00,
+		0x00, 0x17, 0xff, 0xff, 0x94, 0x00, 0x00, 0x00,
+		0x4a, 0xff, 0xff, 0x1b, 0xd9, 0xff, 0x97, 0x00,
+		0x00, 0x00, 0x5c, 0xff, 0xff, 0x47, 0x00, 0x00,
+		0x00, 0x00, 0xd1, 0xff, 0xd4, 0x00, 0x00, 0x00,
+		0x9a, 0xff, 0xce, 0x00, 0x8c, 0xff, 0xe1, 0x00,
+		0x00, 0x00, 0x9c, 0xff, 0xf9, 0x0a, 0x00, 0x00,
+		0x00, 0x00, 0x8d, 0xff, 0xff, 0x15, 0x00, 0x01,
+		0xe6, 0xff, 0x7e, 0x00, 0x3f, 0xff, 0xff, 0x2c,
+		0x00, 0x00, 0xdc, 0xff, 0xbe, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x46, 0xff, 0xff, 0x54, 0x00, 0x36,
+		0xff, 0xff, 0x30, 0x00, 0x04, 0xef, 0xff, 0x79,
+		0x00, 0x19, 0xff, 0xff, 0x7a, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x0a, 0xf9, 0xff, 0x94, 0x00, 0x86,
+		0xff, 0xe1, 0x00, 0x00, 0x00, 0xa6, 0xff, 0xc3,
+		0x00, 0x59, 0xff, 0xff, 0x35, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0xbe, 0xff, 0xd4, 0x00, 0xd6,
+		0xff, 0x92, 0x00, 0x00, 0x00, 0x5a, 0xff, 0xfc,
+		0x11, 0x99, 0xff, 0xed, 0x02, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x7a, 0xff, 0xff, 0x39, 0xff,
+		0xff, 0x43, 0x00, 0x00, 0x00, 0x11, 0xfc, 0xff,
+		0x59, 0xd7, 0xff, 0xab, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x35, 0xff, 0xff, 0xbf, 0xff,
+		0xf0, 0x06, 0x00, 0x00, 0x00, 0x00, 0xc1, 0xff,
+		0xbd, 0xff, 0xff, 0x66, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x03, 0xee, 0xff, 0xff, 0xff,
+		0xa6, 0x00, 0x00, 0x00, 0x00, 0x00, 0x74, 0xff,
+		0xff, 0xff, 0xff, 0x21, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0xac, 0xff, 0xff, 0xff,
+		0x59, 0x00, 0x00, 0x00, 0x00, 0x00, 0x28, 0xff,
+		0xff, 0xff, 0xdc, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x68, 0xff, 0xff, 0xfa,
+		0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xda,
+		0xff, 0xff, 0x97, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x22, 0xff, 0xff, 0xba,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x8e,
+		0xff, 0xff, 0x52, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 	}, /* 'W' */
 	[0x58 - FONT_START_CHAR] = {
-		0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x701e0000, 0x381c0000,
-		0x38380000, 0x1c700000, 0x0e700000, 0x0ee00000, 0x07c00000, 0x03c00000, 0x03c00000, 0x07c00000,
-		0x07e00000, 0x0e700000, 0x1c700000, 0x1c380000, 0x381c0000, 0x701c0000, 0xf00e0000, 0x00000000,
-		0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x11, 0x30, 0x30, 0x24, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x07, 0x30, 0x30, 0x29, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x10, 0xe5, 0xff, 0xf9, 0x28, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x8b, 0xff, 0xff, 0x72, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x4b, 0xff, 0xff, 0xc4, 0x02, 0x00, 0x00,
+		0x00, 0x00, 0x34, 0xfc, 0xff, 0xc7, 0x03, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0xa0, 0xff, 0xff, 0x6a, 0x00, 0x00,
+		0x00, 0x05, 0xd2, 0xff, 0xf8, 0x27, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x10, 0xe5, 0xff, 0xf2, 0x1d, 0x00,
+		0x00, 0x7e, 0xff, 0xff, 0x75, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x4b, 0xff, 0xff, 0xb4, 0x00,
+		0x2c, 0xf9, 0xff, 0xc8, 0x03, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0xa0, 0xff, 0xff, 0x5c,
+		0xc8, 0xff, 0xf8, 0x28, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x10, 0xe5, 0xff, 0xfd,
+		0xff, 0xff, 0x75, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x4b, 0xff, 0xff,
+		0xff, 0xc8, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x23, 0xfc, 0xff,
+		0xff, 0xae, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x01, 0xc0, 0xff, 0xff,
+		0xff, 0xff, 0x56, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x6a, 0xff, 0xff, 0x9f,
+		0xed, 0xff, 0xeb, 0x17, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x20, 0xf3, 0xff, 0xda, 0x09,
+		0x5b, 0xff, 0xff, 0xae, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x01, 0xbc, 0xff, 0xfe, 0x3d, 0x00,
+		0x00, 0xb5, 0xff, 0xff, 0x5b, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x67, 0xff, 0xff, 0x90, 0x00, 0x00,
+		0x00, 0x1b, 0xf0, 0xff, 0xed, 0x1a, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x1e, 0xf2, 0xff, 0xdd, 0x0b, 0x00, 0x00,
+		0x00, 0x00, 0x61, 0xff, 0xff, 0xb5, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x01, 0xba, 0xff, 0xfe, 0x3f, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x01, 0xba, 0xff, 0xff, 0x60, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x65, 0xff, 0xff, 0x94, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x1e, 0xf2, 0xff, 0xf0, 0x1e,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 	}, /* 'X' */
 	[0x59 - FONT_START_CHAR] = {
-		0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xf01e0000, 0x701c0000,
-		0x38380000, 0x1c700000, 0x1c700000, 0x0ee00000, 0x0ec00000, 0x07c00000, 0x03800000, 0x03800000,
-		0x03800000, 0x03800000, 0x03800000, 0x03800000, 0x03800000, 0x03800000, 0x03800000, 0x00000000,
-		0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x22, 0x30, 0x30, 0x11, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x12, 0x30, 0x30, 0x1c, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x54, 0xff, 0xff, 0xb5, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0xbd, 0xff, 0xfe, 0x39, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0xb5, 0xff, 0xff, 0x4e, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x56, 0xff, 0xff, 0x98, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x1f, 0xf5, 0xff, 0xde, 0x09, 0x00, 0x00,
+		0x00, 0x0c, 0xe3, 0xff, 0xe8, 0x10, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x71, 0xff, 0xff, 0x81, 0x00, 0x00,
+		0x00, 0x88, 0xff, 0xff, 0x58, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x03, 0xcd, 0xff, 0xf7, 0x22, 0x00,
+		0x28, 0xfa, 0xff, 0xb8, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x33, 0xfd, 0xff, 0xb2, 0x00,
+		0xbb, 0xff, 0xf7, 0x22, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x90, 0xff, 0xff, 0x99,
+		0xff, 0xff, 0x7b, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x0d, 0xe1, 0xff, 0xff,
+		0xff, 0xd6, 0x06, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x4d, 0xff, 0xff,
+		0xff, 0x3d, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xdb, 0xff,
+		0xd2, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xd0, 0xff,
+		0xcc, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xd0, 0xff,
+		0xcc, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xd0, 0xff,
+		0xcc, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xd0, 0xff,
+		0xcc, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xd0, 0xff,
+		0xcc, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xd0, 0xff,
+		0xcc, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xd0, 0xff,
+		0xcc, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 	}, /* 'Y' */
 	[0x5a - FONT_START_CHAR] = {
-		0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xfff00000, 0xfff00000,
-		0x00f00000, 0x00e00000, 0x01c00000, 0x03c00000, 0x03800000, 0x07000000, 0x0e000000, 0x1e000000,
-		0x1c000000, 0x38000000, 0x78000000, 0x70000000, 0xe0000000, 0xfff00000, 0xfff00000, 0x00000000,
-		0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x24, 0x30, 0x30, 0x30, 0x30, 0x30, 0x30,
+		0x30, 0x30, 0x30, 0x30, 0x26, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+		0xff, 0xff, 0xff, 0xff, 0xcc, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+		0xff, 0xff, 0xff, 0xff, 0xcc, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x36, 0x48, 0x48, 0x48, 0x48, 0x48, 0x48,
+		0x48, 0xb5, 0xff, 0xff, 0xa5, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x39, 0xfc, 0xff, 0xe4, 0x13, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0e,
+		0xde, 0xff, 0xfe, 0x42, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xa5,
+		0xff, 0xff, 0x87, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x5c, 0xff,
+		0xff, 0xca, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x22, 0xf2, 0xff,
+		0xf3, 0x23, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x04, 0xc7, 0xff, 0xff,
+		0x5e, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x83, 0xff, 0xff, 0xa6,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x40, 0xfd, 0xff, 0xdf, 0x0f,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x12, 0xe3, 0xff, 0xfc, 0x3b, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0xac, 0xff, 0xff, 0x7f, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x65, 0xff, 0xff, 0xc4, 0x03, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x10, 0xf5, 0xff, 0xff, 0x96, 0x78, 0x78, 0x78,
+		0x78, 0x78, 0x78, 0x78, 0x6d, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x1c, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+		0xff, 0xff, 0xff, 0xff, 0xe8, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x1c, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+		0xff, 0xff, 0xff, 0xff, 0xe8, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 	}, /* 'Z' */
 	[0x5b - FONT_START_CHAR] = {
-		0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xfc000000, 0xfc000000, 0xe0000000, 0xe0000000,
-		0xe0000000, 0xe0000000, 0xe0000000, 0xe0000000, 0xe0000000, 0xe0000000, 0xe0000000, 0xe0000000,
-		0xe0000000, 0xe0000000, 0xe0000000, 0xe0000000, 0xe0000000, 0xe0000000, 0xe0000000, 0xe0000000,
-		0xfc000000, 0xfc000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x02, 0x04, 0x04, 0x04, 0x04, 0x03,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x80, 0xff, 0xff, 0xff, 0xff, 0xd8,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x80, 0xff, 0xff, 0xff, 0xff, 0xd8,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x80, 0xff, 0xde, 0x24, 0x24, 0x1e,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x80, 0xff, 0xd8, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x80, 0xff, 0xd8, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x80, 0xff, 0xd8, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x80, 0xff, 0xd8, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x80, 0xff, 0xd8, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x80, 0xff, 0xd8, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x80, 0xff, 0xd8, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x80, 0xff, 0xd8, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x80, 0xff, 0xd8, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x80, 0xff, 0xd8, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x80, 0xff, 0xd8, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x80, 0xff, 0xd8, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x80, 0xff, 0xd8, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x80, 0xff, 0xd8, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x80, 0xff, 0xd8, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x80, 0xff, 0xd8, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x80, 0xff, 0xdf, 0x2c, 0x2c, 0x25,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x80, 0xff, 0xff, 0xff, 0xff, 0xd8,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x7c, 0xf8, 0xf8, 0xf8, 0xf8, 0xd1,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 	}, /* '[' */
 	[0x5c - FONT_START_CHAR] = {
-		0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xe0000000, 0x60000000,
-		0x60000000, 0x70000000, 0x30000000, 0x30000000, 0x38000000, 0x18000000, 0x18000000, 0x1c000000,
-		0x0c000000, 0x0c000000, 0x0e000000, 0x0e000000, 0x06000000, 0x07000000, 0x07000000, 0x00000000,
-		0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x2b, 0x30, 0x17, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0xb3, 0xff, 0xad, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x62, 0xff, 0xf5, 0x0a, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x12, 0xfc, 0xff, 0x52, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0xbd, 0xff, 0xa6, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x6a, 0xff, 0xf1, 0x07, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x19, 0xfe, 0xff, 0x4a, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0xc6, 0xff, 0x9d, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x72, 0xff, 0xeb, 0x04, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x22, 0xff, 0xff, 0x42, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0xce, 0xff, 0x94, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x2a, 0xff, 0xff, 0x3a, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0xd6, 0xff, 0x8d, 0x00,
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+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x32, 0xff, 0xff, 0x32,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0xdf, 0xff, 0x84,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x8e, 0xff, 0xd6,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 	}, /* '\\' */
 	[0x5d - FONT_START_CHAR] = {
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-		0x38000000, 0x38000000, 0x38000000, 0x38000000, 0x38000000, 0x38000000, 0x38000000, 0x38000000,
-		0x38000000, 0x38000000, 0x38000000, 0x38000000, 0x38000000, 0x38000000, 0x38000000, 0x38000000,
-		0xf8000000, 0xf8000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
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+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 	}, /* ']' */
 	[0x5e - FONT_START_CHAR] = {
-		0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x0e000000, 0x0f000000,
-		0x1f000000, 0x1b800000, 0x31c00000, 0x70c00000, 0xe0e00000, 0x00000000, 0x00000000, 0x00000000,
-		0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-		0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
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+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 	}, /* '^' */
 	[0x5f - FONT_START_CHAR] = {
-		0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-		0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-		0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-		0x00000000, 0x00000000, 0xfff00000, 0xfff00000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x1e, 0x74, 0xa1, 0xaa, 0x97,
+		0x61, 0x0d, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x03, 0x84, 0xfb, 0xff, 0xff, 0xff, 0xff,
+		0xff, 0xea, 0x46, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x8a, 0xff, 0xff, 0xc9, 0x80, 0x76, 0xaa,
+		0xfc, 0xff, 0xf7, 0x26, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x12, 0xc1, 0x6d, 0x00, 0x00, 0x00, 0x00,
+		0x49, 0xfe, 0xff, 0x97, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0xc1, 0xff, 0xcf, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x07, 0x5f, 0xa6, 0xc3, 0xc1, 0xa3,
+		0x66, 0xb2, 0xff, 0xdc, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x22, 0xd7, 0xff, 0xff, 0xfc, 0xf0, 0xfe,
+		0xff, 0xff, 0xff, 0xdc, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x01, 0xcd, 0xff, 0xec, 0x51, 0x05, 0x00, 0x09,
+		0x4a, 0xdb, 0xff, 0xdc, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x29, 0xff, 0xff, 0x6b, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0xbb, 0xff, 0xdc, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x3c, 0xff, 0xff, 0x53, 0x00, 0x00, 0x00, 0x00,
+		0x1e, 0xf9, 0xff, 0xdc, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x16, 0xfd, 0xff, 0xbb, 0x08, 0x00, 0x00, 0x19,
+		0xcd, 0xff, 0xff, 0xdc, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x9c, 0xff, 0xff, 0xe4, 0xa8, 0xb4, 0xf5,
+		0xf7, 0xd0, 0xff, 0xdc, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x07, 0x9b, 0xfe, 0xff, 0xff, 0xff, 0xde,
+		0x3e, 0xa0, 0xff, 0xdc, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x1c, 0x56, 0x61, 0x3e, 0x04,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 	}, /* 'a' */
 	[0x62 - FONT_START_CHAR] = {
-		0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xe0000000, 0xe0000000,
-		0xe0000000, 0xe0000000, 0xe3800000, 0xefe00000, 0xfff00000, 0xf0700000, 0xf0380000, 0xe0380000,
-		0xe0380000, 0xe0380000, 0xe0380000, 0xf0380000, 0xf8700000, 0xffe00000, 0xefc00000, 0x00000000,
-		0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x19, 0x30, 0x30, 0x05, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x84, 0xff, 0xff, 0x18, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x84, 0xff, 0xff, 0x18, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x84, 0xff, 0xff, 0x18, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x84, 0xff, 0xff, 0x18, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x84, 0xff, 0xff, 0x18, 0x09, 0x60, 0x9d,
+		0xa8, 0x87, 0x34, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x84, 0xff, 0xff, 0x41, 0xdc, 0xff, 0xff,
+		0xff, 0xff, 0xff, 0xa2, 0x08, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x84, 0xff, 0xff, 0xea, 0xff, 0xd3, 0x9c,
+		0xb0, 0xf7, 0xff, 0xff, 0xac, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x84, 0xff, 0xff, 0xfe, 0x6b, 0x00, 0x00,
+		0x00, 0x1e, 0xd3, 0xff, 0xff, 0x51, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x84, 0xff, 0xff, 0x94, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x24, 0xfb, 0xff, 0xb8, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x84, 0xff, 0xff, 0x2b, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0xb7, 0xff, 0xf1, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x84, 0xff, 0xff, 0x04, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x91, 0xff, 0xff, 0x09, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x84, 0xff, 0xff, 0x0d, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x99, 0xff, 0xff, 0x05, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x84, 0xff, 0xff, 0x46, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0xd0, 0xff, 0xe0, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x84, 0xff, 0xff, 0xc5, 0x04, 0x00, 0x00,
+		0x00, 0x00, 0x4e, 0xff, 0xff, 0x97, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x84, 0xff, 0xff, 0xff, 0xb3, 0x20, 0x00,
+		0x04, 0x5e, 0xf5, 0xff, 0xf9, 0x26, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x84, 0xff, 0xfb, 0xc4, 0xff, 0xff, 0xe8,
+		0xf6, 0xff, 0xff, 0xff, 0x65, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x84, 0xff, 0xf8, 0x10, 0xa4, 0xfe, 0xff,
+		0xff, 0xff, 0xe5, 0x53, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1d, 0x56,
+		0x61, 0x3e, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 	}, /* 'b' */
 	[0x63 - FONT_START_CHAR] = {
-		0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-		0x00000000, 0x00000000, 0x00000000, 0x07000000, 0x3fc00000, 0x7fe00000, 0x70700000, 0xe0400000,
-		0xc0000000, 0xc0000000, 0xc0000000, 0xe0000000, 0xe0700000, 0x70e00000, 0x3fe00000, 0x1f800000,
-		0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x2a, 0x7b, 0xa2, 0xa7,
+		0x89, 0x42, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x08, 0x9a, 0xff, 0xff, 0xff, 0xff,
+		0xff, 0xff, 0xbd, 0x15, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x02, 0xb6, 0xff, 0xff, 0xee, 0xa9, 0xa1,
+		0xd8, 0xff, 0xff, 0xca, 0x04, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x6a, 0xff, 0xff, 0xb4, 0x0e, 0x00, 0x00,
+		0x01, 0x83, 0xff, 0xff, 0x62, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0xd9, 0xff, 0xe1, 0x0a, 0x00, 0x00, 0x00,
+		0x00, 0x01, 0x8c, 0x4d, 0x03, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x16, 0xff, 0xff, 0x82, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x31, 0xff, 0xff, 0x5c, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x2a, 0xff, 0xff, 0x65, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x09, 0xfb, 0xff, 0x9d, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0xb8, 0xff, 0xf9, 0x2b, 0x00, 0x00, 0x00,
+		0x00, 0x09, 0xd4, 0xa9, 0x35, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x39, 0xfd, 0xff, 0xe5, 0x49, 0x02, 0x00,
+		0x28, 0xbd, 0xff, 0xff, 0x4c, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x6f, 0xff, 0xff, 0xff, 0xf3, 0xed,
+		0xff, 0xff, 0xff, 0x9b, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x50, 0xdc, 0xff, 0xff, 0xff,
+		0xff, 0xef, 0x76, 0x02, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x01, 0x33, 0x5b, 0x5f,
+		0x40, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 	}, /* 'c' */
 	[0x64 - FONT_START_CHAR] = {
-		0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00300000, 0x00300000,
-		0x00300000, 0x00300000, 0x0e300000, 0x3fb00000, 0x7ff00000, 0x70f00000, 0xe0700000, 0xc0300000,
-		0xc0300000, 0xc0300000, 0xe0300000, 0xe0700000, 0x70f00000, 0x7ff00000, 0x1fb00000, 0x00000000,
-		0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x0d, 0x30, 0x30, 0x0f, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x44, 0xff, 0xff, 0x50, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x44, 0xff, 0xff, 0x50, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x44, 0xff, 0xff, 0x50, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x44, 0xff, 0xff, 0x50, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x3e, 0x88, 0xa4, 0x94,
+		0x51, 0x03, 0x44, 0xff, 0xff, 0x50, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x0f, 0xb3, 0xff, 0xff, 0xff, 0xff,
+		0xff, 0xc8, 0x59, 0xff, 0xff, 0x50, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x05, 0xc3, 0xff, 0xff, 0xf0, 0xb0, 0xa9,
+		0xe5, 0xff, 0xeb, 0xff, 0xff, 0x50, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x6f, 0xff, 0xff, 0xb7, 0x10, 0x00, 0x00,
+		0x06, 0x94, 0xff, 0xff, 0xff, 0x50, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0xd9, 0xff, 0xe2, 0x0b, 0x00, 0x00, 0x00,
+		0x00, 0x01, 0xc1, 0xff, 0xff, 0x50, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x16, 0xff, 0xff, 0x85, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x5a, 0xff, 0xff, 0x50, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x30, 0xff, 0xff, 0x5d, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x31, 0xff, 0xff, 0x50, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x2c, 0xff, 0xff, 0x64, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x38, 0xff, 0xff, 0x50, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x0d, 0xfe, 0xff, 0x9c, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x70, 0xff, 0xff, 0x50, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0xc6, 0xff, 0xf6, 0x25, 0x00, 0x00, 0x00,
+		0x00, 0x10, 0xe2, 0xff, 0xff, 0x50, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x50, 0xff, 0xff, 0xe0, 0x3f, 0x00, 0x00,
+		0x2a, 0xcb, 0xff, 0xff, 0xff, 0x50, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x98, 0xff, 0xff, 0xff, 0xec, 0xe5,
+		0xff, 0xff, 0xc5, 0xff, 0xff, 0x50, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x01, 0x76, 0xf3, 0xff, 0xff, 0xff,
+		0xf9, 0x8e, 0x2e, 0xff, 0xff, 0x50, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x0c, 0x48, 0x61, 0x4f,
+		0x13, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 	}, /* 'd' */
 	[0x65 - FONT_START_CHAR] = {
-		0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-		0x00000000, 0x00000000, 0x00000000, 0x0f000000, 0x3fc00000, 0x7fe00000, 0x70e00000, 0xe0700000,
-		0xc0700000, 0xfff00000, 0xc0000000, 0xe0000000, 0xe0400000, 0x70700000, 0x7fe00000, 0x1fc00000,
-		0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x33, 0x84, 0xa6, 0xa4,
+		0x7f, 0x30, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x0a, 0xa7, 0xff, 0xff, 0xff, 0xff,
+		0xff, 0xff, 0xa2, 0x09, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x03, 0xb9, 0xff, 0xff, 0xd2, 0x91, 0x97,
+		0xdd, 0xff, 0xff, 0xb2, 0x01, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x69, 0xff, 0xff, 0x87, 0x01, 0x00, 0x00,
+		0x04, 0x9f, 0xff, 0xff, 0x52, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0xd6, 0xff, 0xd0, 0x02, 0x00, 0x00, 0x00,
+		0x00, 0x09, 0xec, 0xff, 0xae, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x15, 0xff, 0xff, 0xb7, 0x64, 0x64, 0x64, 0x64,
+		0x64, 0x64, 0xd6, 0xff, 0xd8, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x31, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+		0xff, 0xff, 0xff, 0xff, 0xe0, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x2c, 0xff, 0xff, 0x9f, 0x5c, 0x5c, 0x5c, 0x5c,
+		0x5c, 0x5c, 0x5c, 0x5c, 0x51, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x0c, 0xfd, 0xff, 0x94, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0xbd, 0xff, 0xf2, 0x1d, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x79, 0x60, 0x01, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x40, 0xff, 0xff, 0xd7, 0x33, 0x00, 0x00,
+		0x08, 0x7d, 0xff, 0xff, 0x5e, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x7c, 0xff, 0xff, 0xff, 0xdc, 0xce,
+		0xf1, 0xff, 0xff, 0xb7, 0x03, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x59, 0xe4, 0xff, 0xff, 0xff,
+		0xff, 0xf6, 0x89, 0x07, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x03, 0x38, 0x5d, 0x60,
+		0x45, 0x0d, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 	}, /* 'e' */
 	[0x66 - FONT_START_CHAR] = {
-		0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x06000000, 0x1f000000,
-		0x3f000000, 0x38000000, 0x30000000, 0x30000000, 0xfe000000, 0xfe000000, 0x30000000, 0x30000000,
-		0x30000000, 0x30000000, 0x30000000, 0x30000000, 0x30000000, 0x30000000, 0x30000000, 0x30000000,
-		0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x0e, 0x63, 0x8c, 0x84,
+		0x48, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x30, 0xe7, 0xff, 0xff, 0xff,
+		0xc0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x02, 0xd8, 0xff, 0xff, 0xce, 0xb6,
+		0xa2, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x30, 0xff, 0xff, 0x9d, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x47, 0xff, 0xff, 0x57, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x1c, 0x48, 0x7c, 0xff, 0xff, 0x85, 0x48, 0x48,
+		0x15, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x64, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+		0x4c, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x59, 0xe4, 0xed, 0xff, 0xff, 0xf0, 0xe4, 0xe4,
+		0x44, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x48, 0xff, 0xff, 0x54, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x48, 0xff, 0xff, 0x54, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x48, 0xff, 0xff, 0x54, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x48, 0xff, 0xff, 0x54, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x48, 0xff, 0xff, 0x54, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x48, 0xff, 0xff, 0x54, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x48, 0xff, 0xff, 0x54, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x48, 0xff, 0xff, 0x54, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x48, 0xff, 0xff, 0x54, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x48, 0xff, 0xff, 0x54, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 	}, /* 'f' */
 	[0x67 - FONT_START_CHAR] = {
-		0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-		0x00000000, 0x00000000, 0x00000000, 0x0e000000, 0x3fb00000, 0x7ff00000, 0xf0f00000, 0xe0700000,
-		0xc0300000, 0xc0300000, 0xc0300000, 0xe0700000, 0xe0700000, 0x70f00000, 0x7fb00000, 0x1f300000,
-		0x00300000, 0x20700000, 0xf0700000, 0x7fe00000, 0x3fc00000, 0x06000000, 0x00000000, 0x00000000,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x01, 0x4a, 0x90, 0xa9, 0x96,
+		0x52, 0x03, 0x13, 0x48, 0x48, 0x10, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x19, 0xc4, 0xff, 0xff, 0xff, 0xff,
+		0xff, 0xcb, 0x5b, 0xff, 0xff, 0x38, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x0b, 0xd5, 0xff, 0xff, 0xe3, 0xa2, 0x9d,
+		0xdc, 0xff, 0xf0, 0xff, 0xff, 0x38, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x82, 0xff, 0xff, 0x9b, 0x06, 0x00, 0x00,
+		0x03, 0x86, 0xff, 0xff, 0xff, 0x38, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0xe5, 0xff, 0xd3, 0x03, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0xc1, 0xff, 0xff, 0x38, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x1b, 0xff, 0xff, 0x79, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x66, 0xff, 0xff, 0x38, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x32, 0xff, 0xff, 0x5b, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x47, 0xff, 0xff, 0x38, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x2a, 0xff, 0xff, 0x66, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x55, 0xff, 0xff, 0x38, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x09, 0xfc, 0xff, 0x9e, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x92, 0xff, 0xff, 0x38, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0xbb, 0xff, 0xf9, 0x2e, 0x00, 0x00, 0x00,
+		0x00, 0x2a, 0xf6, 0xff, 0xff, 0x38, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x3f, 0xff, 0xff, 0xee, 0x6a, 0x23, 0x22,
+		0x65, 0xeb, 0xff, 0xff, 0xff, 0x38, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x77, 0xff, 0xff, 0xff, 0xff, 0xff,
+		0xff, 0xfd, 0xa8, 0xff, 0xff, 0x38, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x4e, 0xd0, 0xff, 0xff, 0xff,
+		0xcc, 0x42, 0x5b, 0xff, 0xff, 0x36, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x15, 0x2a, 0x15,
+		0x00, 0x00, 0x74, 0xff, 0xff, 0x24, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x06, 0x69, 0x98, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0xc3, 0xff, 0xf0, 0x03, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x7b, 0xff, 0xff, 0x89, 0x04, 0x00, 0x00,
+		0x02, 0x7e, 0xff, 0xff, 0x94, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x0a, 0xd0, 0xff, 0xff, 0xe5, 0xab, 0xa9,
+		0xe1, 0xff, 0xff, 0xde, 0x13, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x10, 0xa4, 0xfe, 0xff, 0xff, 0xff,
+		0xff, 0xff, 0xb7, 0x1a, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x21, 0x66, 0x86, 0x87,
+		0x69, 0x29, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 	}, /* 'g' */
 	[0x68 - FONT_START_CHAR] = {
-		0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xe0000000, 0xe0000000,
-		0xe0000000, 0xe0000000, 0xe3800000, 0xefc00000, 0xffe00000, 0xf0e00000, 0xe0700000, 0xe0700000,
-		0xe0700000, 0xe0700000, 0xe0700000, 0xe0700000, 0xe0700000, 0xe0700000, 0xe0700000, 0x00000000,
-		0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x19, 0x30, 0x30, 0x03, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x84, 0xff, 0xff, 0x10, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x84, 0xff, 0xff, 0x10, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x84, 0xff, 0xff, 0x10, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x84, 0xff, 0xff, 0x10, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x84, 0xff, 0xff, 0x10, 0x09, 0x66, 0xa0,
+		0xa5, 0x7c, 0x1e, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x84, 0xff, 0xff, 0x34, 0xdc, 0xff, 0xff,
+		0xff, 0xff, 0xf5, 0x49, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x84, 0xff, 0xff, 0xde, 0xfc, 0xb2, 0x9b,
+		0xd8, 0xff, 0xff, 0xef, 0x10, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x84, 0xff, 0xff, 0xf5, 0x3a, 0x00, 0x00,
+		0x03, 0xac, 0xff, 0xff, 0x60, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x84, 0xff, 0xff, 0x7a, 0x00, 0x00, 0x00,
+		0x00, 0x2f, 0xff, 0xff, 0x89, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x84, 0xff, 0xff, 0x2a, 0x00, 0x00, 0x00,
+		0x00, 0x0f, 0xff, 0xff, 0x90, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x84, 0xff, 0xff, 0x18, 0x00, 0x00, 0x00,
+		0x00, 0x0c, 0xff, 0xff, 0x90, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x84, 0xff, 0xff, 0x18, 0x00, 0x00, 0x00,
+		0x00, 0x0c, 0xff, 0xff, 0x90, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x84, 0xff, 0xff, 0x18, 0x00, 0x00, 0x00,
+		0x00, 0x0c, 0xff, 0xff, 0x90, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x84, 0xff, 0xff, 0x18, 0x00, 0x00, 0x00,
+		0x00, 0x0c, 0xff, 0xff, 0x90, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x84, 0xff, 0xff, 0x18, 0x00, 0x00, 0x00,
+		0x00, 0x0c, 0xff, 0xff, 0x90, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x84, 0xff, 0xff, 0x18, 0x00, 0x00, 0x00,
+		0x00, 0x0c, 0xff, 0xff, 0x90, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x84, 0xff, 0xff, 0x18, 0x00, 0x00, 0x00,
+		0x00, 0x0c, 0xff, 0xff, 0x90, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 	}, /* 'h' */
 	[0x69 - FONT_START_CHAR] = {
-		0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x60000000, 0xf0000000,
-		0xe0000000, 0x00000000, 0x00000000, 0x00000000, 0x60000000, 0x60000000, 0x60000000, 0x60000000,
-		0x60000000, 0x60000000, 0x60000000, 0x60000000, 0x60000000, 0x60000000, 0x60000000, 0x60000000,
-		0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x21, 0xb4, 0xac, 0x15, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x9e, 0xff, 0xff, 0x7d, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x79, 0xff, 0xff, 0x5b, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x02, 0x54, 0x4b, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x1a, 0x48, 0x48, 0x12, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x5c, 0xff, 0xff, 0x40, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x5c, 0xff, 0xff, 0x40, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x5c, 0xff, 0xff, 0x40, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x5c, 0xff, 0xff, 0x40, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x5c, 0xff, 0xff, 0x40, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x5c, 0xff, 0xff, 0x40, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x5c, 0xff, 0xff, 0x40, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x5c, 0xff, 0xff, 0x40, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x5c, 0xff, 0xff, 0x40, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x5c, 0xff, 0xff, 0x40, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x5c, 0xff, 0xff, 0x40, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x5c, 0xff, 0xff, 0x40, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 	}, /* 'i' */
 	[0x6a - FONT_START_CHAR] = {
-		0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x30000000, 0x78000000,
-		0x70000000, 0x00000000, 0x00000000, 0x00000000, 0x30000000, 0x30000000, 0x30000000, 0x30000000,
-		0x30000000, 0x30000000, 0x30000000, 0x30000000, 0x30000000, 0x30000000, 0x30000000, 0x30000000,
-		0x30000000, 0x30000000, 0x70000000, 0xf0000000, 0xe0000000, 0x80000000, 0x00000000, 0x00000000,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x1e, 0xb3, 0xaf, 0x19, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x96, 0xff, 0xff, 0x86, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x71, 0xff, 0xff, 0x63, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x01, 0x50, 0x4f, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x19, 0x48, 0x48, 0x13, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x58, 0xff, 0xff, 0x44, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x58, 0xff, 0xff, 0x44, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x58, 0xff, 0xff, 0x44, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x58, 0xff, 0xff, 0x44, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x58, 0xff, 0xff, 0x44, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x58, 0xff, 0xff, 0x44, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x58, 0xff, 0xff, 0x44, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x58, 0xff, 0xff, 0x44, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x58, 0xff, 0xff, 0x44, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x58, 0xff, 0xff, 0x44, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x58, 0xff, 0xff, 0x44, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x58, 0xff, 0xff, 0x44, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x58, 0xff, 0xff, 0x44, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x5d, 0xff, 0xff, 0x43, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x01, 0xac, 0xff, 0xff, 0x2c, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0xda, 0xff, 0xff, 0xd4, 0x01, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0xff, 0xff, 0xe4, 0x2b, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x88, 0x5e, 0x0c, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 	}, /* 'j' */
 	[0x6b - FONT_START_CHAR] = {
-		0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xe0000000, 0xe0000000,
-		0xe0000000, 0xe0000000, 0xe0100000, 0xe0e00000, 0xe1c00000, 0xe3800000, 0xe7000000, 0xee000000,
-		0xff000000, 0xff000000, 0xf3800000, 0xe3c00000, 0xe1c00000, 0xe0e00000, 0xe0f00000, 0x00000000,
-		0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x19, 0x30, 0x30, 0x05, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x84, 0xff, 0xff, 0x18, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x84, 0xff, 0xff, 0x18, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x84, 0xff, 0xff, 0x18, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x84, 0xff, 0xff, 0x18, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x84, 0xff, 0xff, 0x18, 0x00, 0x00, 0x00,
+		0x00, 0x37, 0x48, 0x48, 0x29, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x84, 0xff, 0xff, 0x18, 0x00, 0x00, 0x00,
+		0x63, 0xff, 0xff, 0xd5, 0x17, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x84, 0xff, 0xff, 0x18, 0x00, 0x00, 0x5e,
+		0xfe, 0xff, 0xd5, 0x17, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x84, 0xff, 0xff, 0x18, 0x00, 0x59, 0xfd,
+		0xff, 0xd5, 0x17, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x84, 0xff, 0xff, 0x18, 0x53, 0xfc, 0xff,
+		0xd5, 0x17, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x84, 0xff, 0xff, 0x66, 0xfb, 0xff, 0xff,
+		0x1d, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x84, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+		0x83, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x84, 0xff, 0xff, 0xff, 0xd6, 0xdb, 0xff,
+		0xfc, 0x34, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x84, 0xff, 0xff, 0xd5, 0x17, 0x3b, 0xfe,
+		0xff, 0xd4, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x84, 0xff, 0xff, 0x2a, 0x00, 0x00, 0x92,
+		0xff, 0xff, 0x8b, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x84, 0xff, 0xff, 0x18, 0x00, 0x00, 0x0c,
+		0xe0, 0xff, 0xfd, 0x39, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x84, 0xff, 0xff, 0x18, 0x00, 0x00, 0x00,
+		0x46, 0xff, 0xff, 0xdb, 0x0a, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x84, 0xff, 0xff, 0x18, 0x00, 0x00, 0x00,
+		0x00, 0x9f, 0xff, 0xff, 0x92, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 	}, /* 'k' */
 	[0x6c - FONT_START_CHAR] = {
-		0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xe0000000, 0xe0000000,
-		0xe0000000, 0xe0000000, 0xe0000000, 0xe0000000, 0xe0000000, 0xe0000000, 0xe0000000, 0xe0000000,
-		0xe0000000, 0xe0000000, 0xe0000000, 0xe0000000, 0xe0000000, 0xe0000000, 0xe0000000, 0x00000000,
-		0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x19, 0x30, 0x30, 0x05, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x84, 0xff, 0xff, 0x18, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x84, 0xff, 0xff, 0x18, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x84, 0xff, 0xff, 0x18, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x84, 0xff, 0xff, 0x18, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x84, 0xff, 0xff, 0x18, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x84, 0xff, 0xff, 0x18, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x84, 0xff, 0xff, 0x18, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x84, 0xff, 0xff, 0x18, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x84, 0xff, 0xff, 0x18, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x84, 0xff, 0xff, 0x18, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x84, 0xff, 0xff, 0x18, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x84, 0xff, 0xff, 0x18, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x84, 0xff, 0xff, 0x18, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x84, 0xff, 0xff, 0x18, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x84, 0xff, 0xff, 0x18, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x84, 0xff, 0xff, 0x18, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x84, 0xff, 0xff, 0x18, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 	}, /* 'l' */
 	[0x6d - FONT_START_CHAR] = {
-		0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-		0x00000000, 0x00000000, 0x00000000, 0x03030000, 0xefcfc000, 0xffffe000, 0xf0f0e000, 0xe0e06000,
-		0xe0606000, 0xe0606000, 0xe0606000, 0xe0606000, 0xe0606000, 0xe0606000, 0xe0606000, 0xe0606000,
-		0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x25, 0x48, 0x46, 0x00, 0x0e, 0x6d, 0xa4,
+		0xa0, 0x64, 0x07, 0x00, 0x00, 0x1b, 0x78, 0xa5,
+		0xa2, 0x70, 0x11, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x84, 0xff, 0xf8, 0x33, 0xe7, 0xff, 0xff,
+		0xff, 0xff, 0xcf, 0x12, 0x57, 0xf5, 0xff, 0xff,
+		0xff, 0xff, 0xe4, 0x22, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x84, 0xff, 0xfc, 0xe4, 0xf4, 0xa6, 0xa0,
+		0xea, 0xff, 0xff, 0xbf, 0xfb, 0xf9, 0xac, 0x9d,
+		0xe1, 0xff, 0xff, 0xb6, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x84, 0xff, 0xff, 0xec, 0x26, 0x00, 0x00,
+		0x15, 0xe8, 0xff, 0xff, 0xf4, 0x31, 0x00, 0x00,
+		0x0b, 0xd5, 0xff, 0xfe, 0x11, 0x00, 0x00, 0x00,
+		0x00, 0x84, 0xff, 0xff, 0x6d, 0x00, 0x00, 0x00,
+		0x00, 0x8f, 0xff, 0xff, 0x7f, 0x00, 0x00, 0x00,
+		0x00, 0x75, 0xff, 0xff, 0x35, 0x00, 0x00, 0x00,
+		0x00, 0x84, 0xff, 0xff, 0x27, 0x00, 0x00, 0x00,
+		0x00, 0x73, 0xff, 0xff, 0x3a, 0x00, 0x00, 0x00,
+		0x00, 0x5b, 0xff, 0xff, 0x3c, 0x00, 0x00, 0x00,
+		0x00, 0x84, 0xff, 0xff, 0x18, 0x00, 0x00, 0x00,
+		0x00, 0x70, 0xff, 0xff, 0x2c, 0x00, 0x00, 0x00,
+		0x00, 0x58, 0xff, 0xff, 0x3c, 0x00, 0x00, 0x00,
+		0x00, 0x84, 0xff, 0xff, 0x18, 0x00, 0x00, 0x00,
+		0x00, 0x70, 0xff, 0xff, 0x2c, 0x00, 0x00, 0x00,
+		0x00, 0x58, 0xff, 0xff, 0x3c, 0x00, 0x00, 0x00,
+		0x00, 0x84, 0xff, 0xff, 0x18, 0x00, 0x00, 0x00,
+		0x00, 0x70, 0xff, 0xff, 0x2c, 0x00, 0x00, 0x00,
+		0x00, 0x58, 0xff, 0xff, 0x3c, 0x00, 0x00, 0x00,
+		0x00, 0x84, 0xff, 0xff, 0x18, 0x00, 0x00, 0x00,
+		0x00, 0x70, 0xff, 0xff, 0x2c, 0x00, 0x00, 0x00,
+		0x00, 0x58, 0xff, 0xff, 0x3c, 0x00, 0x00, 0x00,
+		0x00, 0x84, 0xff, 0xff, 0x18, 0x00, 0x00, 0x00,
+		0x00, 0x70, 0xff, 0xff, 0x2c, 0x00, 0x00, 0x00,
+		0x00, 0x58, 0xff, 0xff, 0x3c, 0x00, 0x00, 0x00,
+		0x00, 0x84, 0xff, 0xff, 0x18, 0x00, 0x00, 0x00,
+		0x00, 0x70, 0xff, 0xff, 0x2c, 0x00, 0x00, 0x00,
+		0x00, 0x58, 0xff, 0xff, 0x3c, 0x00, 0x00, 0x00,
+		0x00, 0x84, 0xff, 0xff, 0x18, 0x00, 0x00, 0x00,
+		0x00, 0x70, 0xff, 0xff, 0x2c, 0x00, 0x00, 0x00,
+		0x00, 0x58, 0xff, 0xff, 0x3c, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 	}, /* 'm' */
 	[0x6e - FONT_START_CHAR] = {
-		0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-		0x00000000, 0x00000000, 0x00000000, 0x03800000, 0xefc00000, 0xffe00000, 0xf0e00000, 0xe0700000,
-		0xe0700000, 0xe0700000, 0xe0700000, 0xe0700000, 0xe0700000, 0xe0700000, 0xe0700000, 0xe0700000,
-		0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x25, 0x48, 0x46, 0x00, 0x0a, 0x64, 0xa0,
+		0xa5, 0x7c, 0x1e, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x84, 0xff, 0xf8, 0x2e, 0xe0, 0xff, 0xff,
+		0xff, 0xff, 0xf5, 0x4a, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x84, 0xff, 0xfc, 0xe3, 0xf9, 0xac, 0x9b,
+		0xd5, 0xff, 0xff, 0xf0, 0x11, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x84, 0xff, 0xff, 0xf1, 0x2f, 0x00, 0x00,
+		0x02, 0xa5, 0xff, 0xff, 0x61, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x84, 0xff, 0xff, 0x72, 0x00, 0x00, 0x00,
+		0x00, 0x2e, 0xff, 0xff, 0x89, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x84, 0xff, 0xff, 0x27, 0x00, 0x00, 0x00,
+		0x00, 0x0f, 0xff, 0xff, 0x90, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x84, 0xff, 0xff, 0x18, 0x00, 0x00, 0x00,
+		0x00, 0x0c, 0xff, 0xff, 0x90, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x84, 0xff, 0xff, 0x18, 0x00, 0x00, 0x00,
+		0x00, 0x0c, 0xff, 0xff, 0x90, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x84, 0xff, 0xff, 0x18, 0x00, 0x00, 0x00,
+		0x00, 0x0c, 0xff, 0xff, 0x90, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x84, 0xff, 0xff, 0x18, 0x00, 0x00, 0x00,
+		0x00, 0x0c, 0xff, 0xff, 0x90, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x84, 0xff, 0xff, 0x18, 0x00, 0x00, 0x00,
+		0x00, 0x0c, 0xff, 0xff, 0x90, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x84, 0xff, 0xff, 0x18, 0x00, 0x00, 0x00,
+		0x00, 0x0c, 0xff, 0xff, 0x90, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x84, 0xff, 0xff, 0x18, 0x00, 0x00, 0x00,
+		0x00, 0x0c, 0xff, 0xff, 0x90, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 	}, /* 'n' */
 	[0x6f - FONT_START_CHAR] = {
-		0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-		0x00000000, 0x00000000, 0x00000000, 0x07000000, 0x3fc00000, 0x7fe00000, 0x70700000, 0xe0300000,
-		0xe0380000, 0xc0380000, 0xc0380000, 0xe0380000, 0xe0700000, 0x70f00000, 0x3fe00000, 0x1fc00000,
-		0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x20, 0x75, 0x9f, 0xa9,
+		0x8e, 0x4d, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x04, 0x8c, 0xfc, 0xff, 0xff, 0xff,
+		0xff, 0xff, 0xd5, 0x30, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x01, 0xa8, 0xff, 0xff, 0xf3, 0xb0, 0xa0,
+		0xd2, 0xff, 0xff, 0xf2, 0x31, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x60, 0xff, 0xff, 0xbc, 0x14, 0x00, 0x00,
+		0x00, 0x5c, 0xfa, 0xff, 0xd7, 0x04, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0xd3, 0xff, 0xe5, 0x0c, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x76, 0xff, 0xff, 0x50, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x15, 0xff, 0xff, 0x85, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x0e, 0xfd, 0xff, 0x94, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x30, 0xff, 0xff, 0x5d, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0xe1, 0xff, 0xb0, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x2b, 0xff, 0xff, 0x65, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0xe9, 0xff, 0xaa, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x09, 0xfa, 0xff, 0x9d, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x24, 0xff, 0xff, 0x83, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0xb4, 0xff, 0xf9, 0x2c, 0x00, 0x00, 0x00,
+		0x00, 0x01, 0xa9, 0xff, 0xff, 0x34, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x32, 0xfb, 0xff, 0xe8, 0x4f, 0x03, 0x00,
+		0x1c, 0xa6, 0xff, 0xff, 0xae, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x62, 0xfe, 0xff, 0xff, 0xf5, 0xe8,
+		0xff, 0xff, 0xff, 0xd1, 0x11, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x43, 0xd4, 0xff, 0xff, 0xff,
+		0xff, 0xf8, 0x94, 0x0c, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x2d, 0x58, 0x61,
+		0x47, 0x0f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 	}, /* 'o' */
 	[0x70 - FONT_START_CHAR] = {
-		0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-		0x00000000, 0x00000000, 0x00000000, 0x03800000, 0xefe00000, 0xfff00000, 0xf0700000, 0xf0380000,
-		0xe0380000, 0xe0380000, 0xe0380000, 0xe0380000, 0xf0380000, 0xf8700000, 0xffe00000, 0xefc00000,
-		0xe0000000, 0xe0000000, 0xe0000000, 0xe0000000, 0xe0000000, 0x00000000, 0x00000000, 0x00000000,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x25, 0x48, 0x46, 0x00, 0x0b, 0x64, 0x9e,
+		0xa8, 0x87, 0x34, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x84, 0xff, 0xf8, 0x36, 0xe4, 0xff, 0xff,
+		0xff, 0xff, 0xff, 0xa2, 0x08, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x84, 0xff, 0xfe, 0xea, 0xff, 0xd3, 0x9c,
+		0xb0, 0xf7, 0xff, 0xff, 0xac, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x84, 0xff, 0xff, 0xfe, 0x69, 0x00, 0x00,
+		0x00, 0x1e, 0xd3, 0xff, 0xff, 0x51, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x84, 0xff, 0xff, 0x95, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x22, 0xfa, 0xff, 0xb8, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x84, 0xff, 0xff, 0x2c, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0xb5, 0xff, 0xf0, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x84, 0xff, 0xff, 0x04, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x8d, 0xff, 0xff, 0x09, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x84, 0xff, 0xff, 0x0d, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x95, 0xff, 0xff, 0x05, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x84, 0xff, 0xff, 0x45, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0xcd, 0xff, 0xe1, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x84, 0xff, 0xff, 0xc4, 0x04, 0x00, 0x00,
+		0x00, 0x00, 0x4e, 0xff, 0xff, 0x97, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x84, 0xff, 0xff, 0xff, 0xb3, 0x20, 0x00,
+		0x04, 0x5f, 0xf5, 0xff, 0xf9, 0x26, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x84, 0xff, 0xff, 0xd9, 0xff, 0xff, 0xe8,
+		0xf6, 0xff, 0xff, 0xff, 0x66, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x84, 0xff, 0xff, 0x2d, 0xb3, 0xff, 0xff,
+		0xff, 0xff, 0xe5, 0x53, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x84, 0xff, 0xff, 0x18, 0x00, 0x21, 0x57,
+		0x61, 0x3e, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x84, 0xff, 0xff, 0x18, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x84, 0xff, 0xff, 0x18, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x84, 0xff, 0xff, 0x18, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x84, 0xff, 0xff, 0x18, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x15, 0x28, 0x28, 0x04, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 	}, /* 'p' */
 	[0x71 - FONT_START_CHAR] = {
-		0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-		0x00000000, 0x00000000, 0x00000000, 0x0e000000, 0x3fb00000, 0x7ff00000, 0x70f00000, 0xe0700000,
-		0xc0300000, 0xc0300000, 0xc0300000, 0xe0300000, 0xe0700000, 0x70f00000, 0x7ff00000, 0x1fb00000,
-		0x00300000, 0x00300000, 0x00300000, 0x00300000, 0x00300000, 0x00000000, 0x00000000, 0x00000000,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x42, 0x8d, 0xa8, 0x98,
+		0x56, 0x04, 0x0b, 0x48, 0x48, 0x17, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x12, 0xb7, 0xff, 0xff, 0xff, 0xff,
+		0xff, 0xd1, 0x46, 0xff, 0xff, 0x50, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x06, 0xc9, 0xff, 0xff, 0xed, 0xa8, 0xa1,
+		0xe0, 0xff, 0xeb, 0xff, 0xff, 0x50, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x74, 0xff, 0xff, 0xb5, 0x0e, 0x00, 0x00,
+		0x04, 0x8f, 0xff, 0xff, 0xff, 0x50, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0xde, 0xff, 0xe2, 0x0b, 0x00, 0x00, 0x00,
+		0x00, 0x01, 0xbc, 0xff, 0xff, 0x50, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x19, 0xff, 0xff, 0x84, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x54, 0xff, 0xff, 0x50, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x31, 0xff, 0xff, 0x5c, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x2d, 0xff, 0xff, 0x50, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x2c, 0xff, 0xff, 0x65, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x33, 0xff, 0xff, 0x50, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x0c, 0xfd, 0xff, 0x9d, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x68, 0xff, 0xff, 0x50, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0xc3, 0xff, 0xf7, 0x29, 0x00, 0x00, 0x00,
+		0x00, 0x09, 0xd6, 0xff, 0xff, 0x50, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x4c, 0xff, 0xff, 0xe4, 0x47, 0x01, 0x00,
+		0x27, 0xbd, 0xff, 0xff, 0xff, 0x50, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x91, 0xff, 0xff, 0xff, 0xf3, 0xec,
+		0xff, 0xff, 0xd5, 0xff, 0xff, 0x50, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x01, 0x75, 0xf2, 0xff, 0xff, 0xff,
+		0xfc, 0x95, 0x4b, 0xff, 0xff, 0x50, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x0c, 0x48, 0x61, 0x51,
+		0x18, 0x00, 0x44, 0xff, 0xff, 0x50, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x44, 0xff, 0xff, 0x50, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x44, 0xff, 0xff, 0x50, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x44, 0xff, 0xff, 0x50, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x44, 0xff, 0xff, 0x50, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x0b, 0x28, 0x28, 0x0d, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 	}, /* 'q' */
 	[0x72 - FONT_START_CHAR] = {
-		0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-		0x00000000, 0x00000000, 0x00000000, 0x07000000, 0xef000000, 0xff000000, 0xf0000000, 0xe0000000,
-		0xe0000000, 0xe0000000, 0xe0000000, 0xe0000000, 0xe0000000, 0xe0000000, 0xe0000000, 0xe0000000,
-		0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x25, 0x48, 0x46, 0x00, 0x1d, 0x83, 0xa6,
+		0x8b, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x84, 0xff, 0xf8, 0x40, 0xf3, 0xff, 0xff,
+		0xff, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x84, 0xff, 0xfc, 0xdf, 0xff, 0xea, 0xd8,
+		0xfb, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x84, 0xff, 0xff, 0xfc, 0x65, 0x02, 0x00,
+		0x0b, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x84, 0xff, 0xff, 0x8b, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x84, 0xff, 0xff, 0x30, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x84, 0xff, 0xff, 0x19, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x84, 0xff, 0xff, 0x18, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x84, 0xff, 0xff, 0x18, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x84, 0xff, 0xff, 0x18, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x84, 0xff, 0xff, 0x18, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x84, 0xff, 0xff, 0x18, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x84, 0xff, 0xff, 0x18, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 	}, /* 'r' */
 	[0x73 - FONT_START_CHAR] = {
-		0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-		0x00000000, 0x00000000, 0x00000000, 0x1c000000, 0x7f800000, 0xf3c00000, 0xe1800000, 0xe0000000,
-		0xf8000000, 0x7f000000, 0x1f800000, 0x01c00000, 0x41c00000, 0xe1c00000, 0xff800000, 0x7f000000,
-		0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x3f, 0x89, 0xa6, 0xa2, 0x7d,
+		0x29, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x0e, 0xb5, 0xff, 0xff, 0xff, 0xff, 0xff,
+		0xfe, 0x8b, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0xa0, 0xff, 0xff, 0xb4, 0x76, 0x80, 0xcd,
+		0xff, 0xff, 0x6c, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0xf2, 0xff, 0xaa, 0x00, 0x00, 0x00, 0x02,
+		0x96, 0x90, 0x0d, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0xeb, 0xff, 0xc5, 0x06, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x91, 0xff, 0xff, 0xe0, 0x87, 0x44, 0x0a,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x07, 0x9d, 0xff, 0xff, 0xff, 0xff, 0xf7,
+		0xa9, 0x2b, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x29, 0x84, 0xc9, 0xfc, 0xff,
+		0xff, 0xf7, 0x3e, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x65,
+		0xf3, 0xff, 0xcc, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x49, 0xa1, 0x02, 0x00, 0x00, 0x00, 0x00,
+		0x97, 0xff, 0xf8, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x3c, 0xff, 0xff, 0xa0, 0x0d, 0x00, 0x00, 0x12,
+		0xd2, 0xff, 0xd5, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0xa3, 0xff, 0xff, 0xf4, 0xc8, 0xc4, 0xf3,
+		0xff, 0xff, 0x5a, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x03, 0x7d, 0xf3, 0xff, 0xff, 0xff, 0xff,
+		0xe6, 0x59, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x0b, 0x44, 0x60, 0x5d, 0x3a,
+		0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 	}, /* 's' */
 	[0x74 - FONT_START_CHAR] = {
-		0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-		0x30000000, 0x30000000, 0x30000000, 0x30000000, 0xfe000000, 0xfe000000, 0x30000000, 0x30000000,
-		0x30000000, 0x30000000, 0x30000000, 0x30000000, 0x30000000, 0x30000000, 0x3e000000, 0x1e000000,
-		0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x46, 0xb4, 0xb4, 0x25, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x64, 0xff, 0xff, 0x34, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x64, 0xff, 0xff, 0x34, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x1e, 0x48, 0x91, 0xff, 0xff, 0x6f, 0x48, 0x48,
+		0x0f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x6c, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+		0x34, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x60, 0xe4, 0xf2, 0xff, 0xff, 0xeb, 0xe4, 0xe4,
+		0x2e, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x64, 0xff, 0xff, 0x34, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x64, 0xff, 0xff, 0x34, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x64, 0xff, 0xff, 0x34, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x64, 0xff, 0xff, 0x34, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x64, 0xff, 0xff, 0x34, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x64, 0xff, 0xff, 0x34, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x63, 0xff, 0xff, 0x39, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x50, 0xff, 0xff, 0x86, 0x00, 0x04,
+		0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x12, 0xf4, 0xff, 0xff, 0xe4, 0xf2,
+		0x38, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x50, 0xf4, 0xff, 0xff, 0xff,
+		0x38, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x12, 0x50, 0x60, 0x3b,
+		0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 	}, /* 't' */
 	[0x75 - FONT_START_CHAR] = {
-		0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-		0x00000000, 0x00000000, 0x00000000, 0xe0600000, 0xe0600000, 0xe0600000, 0xe0600000, 0xe0600000,
-		0xe0600000, 0xe0600000, 0xe0600000, 0xe0e00000, 0x70e00000, 0x7fe00000, 0x3f600000, 0x00000000,
-		0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x2d, 0x48, 0x46, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x0b, 0x48, 0x48, 0x20, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0xa0, 0xff, 0xf8, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x28, 0xff, 0xff, 0x70, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0xa0, 0xff, 0xf8, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x28, 0xff, 0xff, 0x70, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0xa0, 0xff, 0xf8, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x28, 0xff, 0xff, 0x70, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0xa0, 0xff, 0xf8, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x28, 0xff, 0xff, 0x70, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0xa0, 0xff, 0xf8, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x28, 0xff, 0xff, 0x70, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0xa0, 0xff, 0xf8, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x28, 0xff, 0xff, 0x70, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0xa0, 0xff, 0xf8, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x29, 0xff, 0xff, 0x70, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x9f, 0xff, 0xfd, 0x01, 0x00, 0x00, 0x00,
+		0x00, 0x42, 0xff, 0xff, 0x70, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x90, 0xff, 0xff, 0x2e, 0x00, 0x00, 0x00,
+		0x00, 0xa0, 0xff, 0xff, 0x70, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x58, 0xff, 0xff, 0xbd, 0x0f, 0x00, 0x03,
+		0x74, 0xff, 0xff, 0xff, 0x70, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x08, 0xdc, 0xff, 0xff, 0xf4, 0xcd, 0xe9,
+		0xff, 0xc4, 0xff, 0xff, 0x70, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x26, 0xd2, 0xff, 0xff, 0xff, 0xff,
+		0xa8, 0x17, 0xff, 0xff, 0x70, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x02, 0x38, 0x5f, 0x58, 0x21,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 	}, /* 'u' */
 	[0x76 - FONT_START_CHAR] = {
-		0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-		0x00000000, 0x00000000, 0x00000000, 0xe0380000, 0x60700000, 0x70700000, 0x30600000, 0x38e00000,
-		0x38c00000, 0x19c00000, 0x1d800000, 0x0d800000, 0x0f800000, 0x0f000000, 0x07000000, 0x00000000,
-		0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x3e, 0x48, 0x3f, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x06, 0x48, 0x48, 0x2a, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x9b, 0xff, 0xfe, 0x1e, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x54, 0xff, 0xff, 0x53, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x34, 0xff, 0xff, 0x7c, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0xb4, 0xff, 0xe6, 0x04, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0xcd, 0xff, 0xdb, 0x01, 0x00, 0x00, 0x00,
+		0x19, 0xfc, 0xff, 0x82, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x66, 0xff, 0xff, 0x40, 0x00, 0x00, 0x00,
+		0x78, 0xff, 0xfd, 0x1d, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x0c, 0xf2, 0xff, 0xa0, 0x00, 0x00, 0x00,
+		0xd8, 0xff, 0xb2, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x98, 0xff, 0xf4, 0x0c, 0x00, 0x38,
+		0xff, 0xff, 0x4a, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x30, 0xff, 0xff, 0x61, 0x00, 0x99,
+		0xff, 0xdf, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0xc9, 0xff, 0xc4, 0x0a, 0xf2,
+		0xff, 0x79, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x61, 0xff, 0xff, 0x7e, 0xff,
+		0xfa, 0x16, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x0a, 0xf0, 0xff, 0xfc, 0xff,
+		0xa8, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x93, 0xff, 0xff, 0xff,
+		0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x2d, 0xff, 0xff, 0xd7,
+		0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 	}, /* 'v' */
 	[0x77 - FONT_START_CHAR] = {
-		0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-		0x00000000, 0x00000000, 0x00000000, 0xe0e0e000, 0x60e0c000, 0x71f1c000, 0x71b1c000, 0x31b18000,
-		0x33b98000, 0x3b1b8000, 0x1b1b0000, 0x1b1b0000, 0x1e0f0000, 0x0e0e0000, 0x0e0e0000, 0x00000000,
-		0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x3c, 0x48, 0x3a, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x35, 0x48, 0x38, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x36, 0x48, 0x39, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0xa2, 0xff, 0xf6, 0x08, 0x00, 0x00, 0x00, 0x03,
+		0xeb, 0xff, 0xf3, 0x07, 0x00, 0x00, 0x00, 0x03,
+		0xec, 0xff, 0x93, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x4e, 0xff, 0xff, 0x47, 0x00, 0x00, 0x00, 0x3e,
+		0xff, 0xff, 0xff, 0x4a, 0x00, 0x00, 0x00, 0x3b,
+		0xff, 0xff, 0x42, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x09, 0xf5, 0xff, 0x93, 0x00, 0x00, 0x00, 0x8e,
+		0xff, 0xf9, 0xff, 0x9a, 0x00, 0x00, 0x00, 0x87,
+		0xff, 0xeb, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0xaa, 0xff, 0xde, 0x00, 0x00, 0x00, 0xdf,
+		0xff, 0x87, 0xff, 0xe8, 0x02, 0x00, 0x00, 0xd2,
+		0xff, 0x9d, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x5a, 0xff, 0xff, 0x28, 0x00, 0x2e, 0xff,
+		0xe5, 0x0e, 0xf9, 0xff, 0x3a, 0x00, 0x1e, 0xff,
+		0xff, 0x4a, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x0e, 0xf9, 0xff, 0x71, 0x00, 0x7f, 0xff,
+		0x96, 0x00, 0xb6, 0xff, 0x8a, 0x00, 0x69, 0xff,
+		0xf1, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0xb6, 0xff, 0xbc, 0x00, 0xd2, 0xff,
+		0x45, 0x00, 0x63, 0xff, 0xda, 0x00, 0xb4, 0xff,
+		0xa6, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x64, 0xff, 0xfa, 0x2e, 0xff, 0xf0,
+		0x05, 0x00, 0x15, 0xfd, 0xff, 0x33, 0xf7, 0xff,
+		0x52, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x15, 0xfd, 0xff, 0xc1, 0xff, 0xa6,
+		0x00, 0x00, 0x00, 0xbe, 0xff, 0xc2, 0xff, 0xf6,
+		0x0b, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0xc1, 0xff, 0xff, 0xff, 0x56,
+		0x00, 0x00, 0x00, 0x6e, 0xff, 0xff, 0xff, 0xae,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x6e, 0xff, 0xff, 0xf8, 0x0d,
+		0x00, 0x00, 0x00, 0x1b, 0xff, 0xff, 0xff, 0x5a,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x1e, 0xff, 0xff, 0xb5, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0xc9, 0xff, 0xfa, 0x10,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 	}, /* 'w' */
 	[0x78 - FONT_START_CHAR] = {
-		0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-		0x00000000, 0x00000000, 0x00000000, 0xf0700000, 0x70e00000, 0x39c00000, 0x1d800000, 0x0f800000,
-		0x0f000000, 0x0f000000, 0x1f800000, 0x19800000, 0x39c00000, 0x70e00000, 0xe0700000, 0x00000000,
-		0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x30, 0x48, 0x48, 0x12, 0x00, 0x00, 0x00, 0x00,
+		0x02, 0x46, 0x48, 0x3e, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x3b, 0xfc, 0xff, 0xb3, 0x00, 0x00, 0x00, 0x00,
+		0x6f, 0xff, 0xff, 0x65, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x81, 0xff, 0xff, 0x60, 0x00, 0x00, 0x25,
+		0xf6, 0xff, 0xac, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x04, 0xc8, 0xff, 0xf0, 0x1e, 0x03, 0xc5,
+		0xff, 0xe3, 0x12, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x23, 0xf4, 0xff, 0xba, 0x76, 0xff,
+		0xfd, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x61, 0xff, 0xff, 0xff, 0xff,
+		0x85, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0xb9, 0xff, 0xff, 0xd1,
+		0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x1c, 0xee, 0xff, 0xff, 0xf2,
+		0x22, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x02, 0xbd, 0xff, 0xe5, 0xe5, 0xff,
+		0xc5, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x72, 0xff, 0xff, 0x48, 0x4d, 0xff,
+		0xff, 0x7d, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x2d, 0xf9, 0xff, 0x9b, 0x00, 0x00, 0xa5,
+		0xff, 0xfb, 0x35, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x07, 0xd3, 0xff, 0xe1, 0x0e, 0x00, 0x00, 0x13,
+		0xe9, 0xff, 0xda, 0x0b, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x8e, 0xff, 0xff, 0x44, 0x00, 0x00, 0x00, 0x00,
+		0x54, 0xff, 0xff, 0x99, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 	}, /* 'x' */
 	[0x79 - FONT_START_CHAR] = {
-		0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-		0x00000000, 0x00000000, 0x00000000, 0xe0380000, 0x70700000, 0x70600000, 0x30e00000, 0x38e00000,
-		0x18c00000, 0x1dc00000, 0x0d800000, 0x0f800000, 0x0f000000, 0x07000000, 0x07000000, 0x06000000,
-		0x0e000000, 0x0c000000, 0x1c000000, 0x38000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x3e, 0x48, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x0b, 0x48, 0x48, 0x28, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x94, 0xff, 0xff, 0x29, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x68, 0xff, 0xff, 0x46, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x24, 0xfe, 0xff, 0x94, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0xce, 0xff, 0xd7, 0x01, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0xb2, 0xff, 0xf3, 0x0d, 0x00, 0x00, 0x00,
+		0x34, 0xff, 0xff, 0x6a, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x3e, 0xff, 0xff, 0x6c, 0x00, 0x00, 0x00,
+		0x9a, 0xff, 0xf1, 0x0c, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0xce, 0xff, 0xd7, 0x01, 0x00, 0x0d,
+		0xf4, 0xff, 0x8e, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x5c, 0xff, 0xff, 0x43, 0x00, 0x66,
+		0xff, 0xfe, 0x22, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x05, 0xe5, 0xff, 0xaf, 0x00, 0xcd,
+		0xff, 0xb2, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x7a, 0xff, 0xfd, 0x4a, 0xff,
+		0xff, 0x43, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x11, 0xf5, 0xff, 0xe9, 0xff,
+		0xd5, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x96, 0xff, 0xff, 0xff,
+		0x68, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x27, 0xfe, 0xff, 0xef,
+		0x0b, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x0f, 0xfa, 0xff, 0x8c,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x77, 0xff, 0xfd, 0x21,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x06, 0xe5, 0xff, 0xb1, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x60, 0xff, 0xff, 0x42, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x01, 0xd4, 0xff, 0xd4, 0x01, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x48, 0xff, 0xff, 0x66, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x18, 0x2c, 0x2c, 0x06, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 	}, /* 'y' */
 	[0x7a - FONT_START_CHAR] = {
-		0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-		0x00000000, 0x00000000, 0x00000000, 0xffc00000, 0xffc00000, 0x03800000, 0x07000000, 0x0e000000,
-		0x0e000000, 0x1c000000, 0x38000000, 0x70000000, 0xe0000000, 0xffc00000, 0xffc00000, 0x00000000,
-		0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x03, 0x48, 0x48, 0x48, 0x48, 0x48, 0x48, 0x48,
+		0x48, 0x48, 0x35, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x0c, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+		0xff, 0xff, 0xbc, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x0b, 0xe0, 0xe0, 0xe0, 0xe0, 0xe0, 0xe0, 0xec,
+		0xff, 0xff, 0xb8, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0c, 0xcf,
+		0xff, 0xf4, 0x31, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0xb4, 0xff,
+		0xfc, 0x4b, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x93, 0xff, 0xff,
+		0x6a, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x6f, 0xff, 0xff, 0x8c,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x4f, 0xfd, 0xff, 0xad, 0x02,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x34, 0xf6, 0xff, 0xc9, 0x09, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x1e, 0xe8, 0xff, 0xe0, 0x17, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x0f, 0xd4, 0xff, 0xfb, 0x55, 0x2c, 0x2c, 0x2c,
+		0x2c, 0x2c, 0x27, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x40, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+		0xff, 0xff, 0xe4, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x40, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+		0xff, 0xff, 0xe4, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 	}, /* 'z' */
 	[0x7b - FONT_START_CHAR] = {
-		0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x0e000000, 0x1e000000, 0x38000000, 0x38000000,
-		0x38000000, 0x38000000, 0x38000000, 0x38000000, 0x38000000, 0x30000000, 0xf0000000, 0xf0000000,
-		0x30000000, 0x38000000, 0x38000000, 0x38000000, 0x38000000, 0x38000000, 0x38000000, 0x38000000,
-		0x1e000000, 0x0e000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x04,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x31, 0xbd, 0xfa, 0xfc,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x24, 0xf3, 0xff, 0xff, 0xfc,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x96, 0xff, 0xfa, 0x55, 0x0d,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0xc8, 0xff, 0xa6, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0xd0, 0xff, 0x89, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0xd0, 0xff, 0x88, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0xd0, 0xff, 0x88, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0xd0, 0xff, 0x88, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0xde, 0xff, 0x81, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x0d, 0x57, 0xff, 0xff, 0x4f, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0xa0, 0xff, 0xfa, 0x8f, 0x01, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0xa0, 0xff, 0xfb, 0x97, 0x02, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x0b, 0x50, 0xff, 0xff, 0x53, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0xdd, 0xff, 0x83, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0xd0, 0xff, 0x88, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0xd0, 0xff, 0x88, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0xd0, 0xff, 0x88, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0xd0, 0xff, 0x89, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0xc8, 0xff, 0xa6, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x98, 0xff, 0xfa, 0x55, 0x15,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x27, 0xf6, 0xff, 0xff, 0xfc,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x36, 0xb9, 0xed, 0xf2,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 	}, /* '{' */
 	[0x7c - FONT_START_CHAR] = {
-		0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xc0000000, 0xc0000000, 0xc0000000,
-		0xc0000000, 0xc0000000, 0xc0000000, 0xc0000000, 0xc0000000, 0xc0000000, 0xc0000000, 0xc0000000,
-		0xc0000000, 0xc0000000, 0xc0000000, 0xc0000000, 0xc0000000, 0xc0000000, 0xc0000000, 0xc0000000,
-		0xc0000000, 0xc0000000, 0xc0000000, 0xc0000000, 0xc0000000, 0x00000000, 0x00000000, 0x00000000,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x0a, 0xd0, 0xd0, 0x4b, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x0c, 0xff, 0xff, 0x5c, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x0c, 0xff, 0xff, 0x5c, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x0c, 0xff, 0xff, 0x5c, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x0c, 0xff, 0xff, 0x5c, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x0c, 0xff, 0xff, 0x5c, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x0c, 0xff, 0xff, 0x5c, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x0c, 0xff, 0xff, 0x5c, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x0c, 0xff, 0xff, 0x5c, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x0c, 0xff, 0xff, 0x5c, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x0c, 0xff, 0xff, 0x5c, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x0c, 0xff, 0xff, 0x5c, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x0c, 0xff, 0xff, 0x5c, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x0c, 0xff, 0xff, 0x5c, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x0c, 0xff, 0xff, 0x5c, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x0c, 0xff, 0xff, 0x5c, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x0c, 0xff, 0xff, 0x5c, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x0c, 0xff, 0xff, 0x5c, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x0c, 0xff, 0xff, 0x5c, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x0c, 0xff, 0xff, 0x5c, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x0c, 0xff, 0xff, 0x5c, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x0c, 0xff, 0xff, 0x5c, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x0c, 0xff, 0xff, 0x5c, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x0c, 0xff, 0xff, 0x5c, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x02, 0x28, 0x28, 0x0e, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 	}, /* '|' */
 	[0x7d - FONT_START_CHAR] = {
-		0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xe0000000, 0xf0000000, 0x70000000, 0x30000000,
-		0x30000000, 0x30000000, 0x30000000, 0x30000000, 0x30000000, 0x38000000, 0x1c000000, 0x1c000000,
-		0x38000000, 0x30000000, 0x30000000, 0x30000000, 0x30000000, 0x30000000, 0x30000000, 0x70000000,
-		0xf0000000, 0xc0000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x7c, 0xfe, 0xe4, 0x8a, 0x08, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x7c, 0xff, 0xff, 0xff, 0xa4, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x06, 0x1b, 0xb4, 0xff, 0xff, 0x1d, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x29, 0xff, 0xff, 0x4d, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x0d, 0xff, 0xff, 0x54, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x0c, 0xff, 0xff, 0x54, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x0c, 0xff, 0xff, 0x54, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x0c, 0xff, 0xff, 0x54, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x07, 0xff, 0xff, 0x62, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0xd3, 0xff, 0xc1, 0x26,
+		0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x35, 0xd8, 0xff, 0xff,
+		0x24, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x39, 0xde, 0xff, 0xff,
+		0x24, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0xd6, 0xff, 0xbb, 0x1a,
+		0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x07, 0xff, 0xff, 0x61, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x0c, 0xff, 0xff, 0x54, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x0c, 0xff, 0xff, 0x54, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x0c, 0xff, 0xff, 0x54, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x0d, 0xff, 0xff, 0x54, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x2e, 0xff, 0xff, 0x4a, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x09, 0x27, 0xc0, 0xff, 0xfd, 0x19, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x7c, 0xff, 0xff, 0xff, 0x92, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x78, 0xf7, 0xd9, 0x74, 0x02, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 	}, /* '}' */
 	[0x7e - FONT_START_CHAR] = {
-		0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-		0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x7e700000, 0xffe00000,
-		0xc3e00000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-		0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x0e, 0x61, 0x77, 0x4d, 0x08, 0x00,
+		0x00, 0x00, 0x1d, 0x28, 0x17, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x15, 0xdc, 0xff, 0xff, 0xff, 0xec, 0x84,
+		0x1c, 0x0f, 0xe7, 0xff, 0x7c, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x91, 0xff, 0xfb, 0xcd, 0xf9, 0xff, 0xff,
+		0xff, 0xfa, 0xff, 0xfe, 0x2b, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0xd4, 0xf8, 0x80, 0x00, 0x14, 0x7a, 0xe1,
+		0xff, 0xff, 0xfe, 0x79, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02,
+		0x30, 0x48, 0x1d, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 	}, /* '~' */
 };
 
 const uint8_t font_widths[FONT_NUM_CHARS] = {
 	[0x20 - FONT_START_CHAR] = 8,
 	[0x21 - FONT_START_CHAR] = 4,
-	[0x22 - FONT_START_CHAR] = 6,
-	[0x23 - FONT_START_CHAR] = 14,
-	[0x24 - FONT_START_CHAR] = 12,
-	[0x25 - FONT_START_CHAR] = 19,
-	[0x26 - FONT_START_CHAR] = 14,
+	[0x22 - FONT_START_CHAR] = 7,
+	[0x23 - FONT_START_CHAR] = 16,
+	[0x24 - FONT_START_CHAR] = 13,
+	[0x25 - FONT_START_CHAR] = 20,
+	[0x26 - FONT_START_CHAR] = 15,
 	[0x27 - FONT_START_CHAR] = 3,
 	[0x28 - FONT_START_CHAR] = 7,
 	[0x29 - FONT_START_CHAR] = 7,
-	[0x2a - FONT_START_CHAR] = 9,
-	[0x2b - FONT_START_CHAR] = 11,
-	[0x2c - FONT_START_CHAR] = 4,
+	[0x2a - FONT_START_CHAR] = 10,
+	[0x2b - FONT_START_CHAR] = 12,
+	[0x2c - FONT_START_CHAR] = 5,
 	[0x2d - FONT_START_CHAR] = 8,
 	[0x2e - FONT_START_CHAR] = 4,
 	[0x2f - FONT_START_CHAR] = 8,
-	[0x30 - FONT_START_CHAR] = 13,
-	[0x31 - FONT_START_CHAR] = 6,
+	[0x30 - FONT_START_CHAR] = 14,
+	[0x31 - FONT_START_CHAR] = 8,
 	[0x32 - FONT_START_CHAR] = 11,
-	[0x33 - FONT_START_CHAR] = 11,
-	[0x34 - FONT_START_CHAR] = 12,
-	[0x35 - FONT_START_CHAR] = 12,
-	[0x36 - FONT_START_CHAR] = 12,
-	[0x37 - FONT_START_CHAR] = 11,
+	[0x33 - FONT_START_CHAR] = 13,
+	[0x34 - FONT_START_CHAR] = 14,
+	[0x35 - FONT_START_CHAR] = 13,
+	[0x36 - FONT_START_CHAR] = 13,
+	[0x37 - FONT_START_CHAR] = 12,
 	[0x38 - FONT_START_CHAR] = 12,
-	[0x39 - FONT_START_CHAR] = 12,
+	[0x39 - FONT_START_CHAR] = 13,
 	[0x3a - FONT_START_CHAR] = 4,
-	[0x3b - FONT_START_CHAR] = 4,
+	[0x3b - FONT_START_CHAR] = 6,
 	[0x3c - FONT_START_CHAR] = 11,
-	[0x3d - FONT_START_CHAR] = 11,
-	[0x3e - FONT_START_CHAR] = 10,
-	[0x3f - FONT_START_CHAR] = 10,
-	[0x40 - FONT_START_CHAR] = 19,
-	[0x41 - FONT_START_CHAR] = 16,
-	[0x42 - FONT_START_CHAR] = 12,
-	[0x43 - FONT_START_CHAR] = 15,
-	[0x44 - FONT_START_CHAR] = 14,
-	[0x45 - FONT_START_CHAR] = 10,
-	[0x46 - FONT_START_CHAR] = 10,
-	[0x47 - FONT_START_CHAR] = 17,
-	[0x48 - FONT_START_CHAR] = 13,
-	[0x49 - FONT_START_CHAR] = 3,
-	[0x4a - FONT_START_CHAR] = 11,
-	[0x4b - FONT_START_CHAR] = 13,
-	[0x4c - FONT_START_CHAR] = 10,
-	[0x4d - FONT_START_CHAR] = 18,
-	[0x4e - FONT_START_CHAR] = 13,
-	[0x4f - FONT_START_CHAR] = 18,
-	[0x50 - FONT_START_CHAR] = 12,
-	[0x51 - FONT_START_CHAR] = 18,
-	[0x52 - FONT_START_CHAR] = 12,
-	[0x53 - FONT_START_CHAR] = 12,
-	[0x54 - FONT_START_CHAR] = 12,
+	[0x3d - FONT_START_CHAR] = 12,
+	[0x3e - FONT_START_CHAR] = 12,
+	[0x3f - FONT_START_CHAR] = 12,
+	[0x40 - FONT_START_CHAR] = 20,
+	[0x41 - FONT_START_CHAR] = 17,
+	[0x42 - FONT_START_CHAR] = 14,
+	[0x43 - FONT_START_CHAR] = 17,
+	[0x44 - FONT_START_CHAR] = 16,
+	[0x45 - FONT_START_CHAR] = 12,
+	[0x46 - FONT_START_CHAR] = 11,
+	[0x47 - FONT_START_CHAR] = 19,
+	[0x48 - FONT_START_CHAR] = 15,
+	[0x49 - FONT_START_CHAR] = 4,
+	[0x4a - FONT_START_CHAR] = 12,
+	[0x4b - FONT_START_CHAR] = 15,
+	[0x4c - FONT_START_CHAR] = 11,
+	[0x4d - FONT_START_CHAR] = 19,
+	[0x4e - FONT_START_CHAR] = 15,
+	[0x4f - FONT_START_CHAR] = 19,
+	[0x50 - FONT_START_CHAR] = 13,
+	[0x51 - FONT_START_CHAR] = 19,
+	[0x52 - FONT_START_CHAR] = 14,
+	[0x53 - FONT_START_CHAR] = 13,
+	[0x54 - FONT_START_CHAR] = 13,
 	[0x55 - FONT_START_CHAR] = 14,
-	[0x56 - FONT_START_CHAR] = 15,
+	[0x56 - FONT_START_CHAR] = 16,
 	[0x57 - FONT_START_CHAR] = 23,
-	[0x58 - FONT_START_CHAR] = 15,
+	[0x58 - FONT_START_CHAR] = 16,
 	[0x59 - FONT_START_CHAR] = 15,
-	[0x5a - FONT_START_CHAR] = 12,
+	[0x5a - FONT_START_CHAR] = 13,
 	[0x5b - FONT_START_CHAR] = 6,
 	[0x5c - FONT_START_CHAR] = 8,
-	[0x5d - FONT_START_CHAR] = 5,
-	[0x5e - FONT_START_CHAR] = 11,
+	[0x5d - FONT_START_CHAR] = 6,
+	[0x5e - FONT_START_CHAR] = 12,
 	[0x5f - FONT_START_CHAR] = 12,
-	[0x60 - FONT_START_CHAR] = 4,
-	[0x61 - FONT_START_CHAR] = 11,
-	[0x62 - FONT_START_CHAR] = 13,
-	[0x63 - FONT_START_CHAR] = 12,
-	[0x64 - FONT_START_CHAR] = 12,
-	[0x65 - FONT_START_CHAR] = 12,
-	[0x66 - FONT_START_CHAR] = 8,
-	[0x67 - FONT_START_CHAR] = 12,
+	[0x60 - FONT_START_CHAR] = 5,
+	[0x61 - FONT_START_CHAR] = 12,
+	[0x62 - FONT_START_CHAR] = 14,
+	[0x63 - FONT_START_CHAR] = 13,
+	[0x64 - FONT_START_CHAR] = 14,
+	[0x65 - FONT_START_CHAR] = 13,
+	[0x66 - FONT_START_CHAR] = 9,
+	[0x67 - FONT_START_CHAR] = 14,
 	[0x68 - FONT_START_CHAR] = 12,
 	[0x69 - FONT_START_CHAR] = 4,
 	[0x6a - FONT_START_CHAR] = 5,
 	[0x6b - FONT_START_CHAR] = 12,
-	[0x6c - FONT_START_CHAR] = 3,
-	[0x6d - FONT_START_CHAR] = 19,
+	[0x6c - FONT_START_CHAR] = 4,
+	[0x6d - FONT_START_CHAR] = 20,
 	[0x6e - FONT_START_CHAR] = 12,
-	[0x6f - FONT_START_CHAR] = 13,
-	[0x70 - FONT_START_CHAR] = 13,
-	[0x71 - FONT_START_CHAR] = 12,
-	[0x72 - FONT_START_CHAR] = 8,
-	[0x73 - FONT_START_CHAR] = 10,
-	[0x74 - FONT_START_CHAR] = 7,
-	[0x75 - FONT_START_CHAR] = 11,
+	[0x6f - FONT_START_CHAR] = 14,
+	[0x70 - FONT_START_CHAR] = 14,
+	[0x71 - FONT_START_CHAR] = 14,
+	[0x72 - FONT_START_CHAR] = 9,
+	[0x73 - FONT_START_CHAR] = 11,
+	[0x74 - FONT_START_CHAR] = 9,
+	[0x75 - FONT_START_CHAR] = 12,
 	[0x76 - FONT_START_CHAR] = 13,
 	[0x77 - FONT_START_CHAR] = 19,
 	[0x78 - FONT_START_CHAR] = 12,
 	[0x79 - FONT_START_CHAR] = 13,
-	[0x7a - FONT_START_CHAR] = 10,
+	[0x7a - FONT_START_CHAR] = 11,
 	[0x7b - FONT_START_CHAR] = 7,
-	[0x7c - FONT_START_CHAR] = 2,
-	[0x7d - FONT_START_CHAR] = 6,
+	[0x7c - FONT_START_CHAR] = 4,
+	[0x7d - FONT_START_CHAR] = 8,
 	[0x7e - FONT_START_CHAR] = 12,
 };
diff --git a/src/lib/fonts/fonts.h b/src/lib/fonts/fonts.h
index 3317e012ba..45371438c3 100644
--- a/src/lib/fonts/fonts.h
+++ b/src/lib/fonts/fonts.h
@@ -10,7 +10,7 @@
 #define FONT_END_CHAR    126  /* ASCII ~ */
 #define FONT_NUM_CHARS  (FONT_END_CHAR - FONT_START_CHAR + 1)
 
-extern const uint32_t font_table[FONT_NUM_CHARS][CONFIG_FONT_HEIGHT];
-extern const uint8_t font_widths[];
+extern const uint8_t font_table[FONT_NUM_CHARS][CONFIG_FONT_WIDTH * CONFIG_FONT_HEIGHT];
+extern const uint8_t font_widths[FONT_NUM_CHARS];
 
 #endif // __FONTS_H__
diff --git a/src/lib/render_text.c b/src/lib/render_text.c
index da2aef1d3d..d20281b6e1 100644
--- a/src/lib/render_text.c
+++ b/src/lib/render_text.c
@@ -7,8 +7,8 @@
 #include "fonts/fonts.h"
 #include "render_bmp.h"
 
-/* Maps an unsigned character to the font table index */
-static const uint32_t *get_glyph_data(unsigned char c)
+/* Maps an unsigned character to the 8-bit alpha map (smoothing data) */
+static const uint8_t *get_glyph_data(unsigned char c)
 {
 	/* Range check using macros generated by Python */
 	if (c < FONT_START_CHAR || c > FONT_END_CHAR)
@@ -65,23 +65,35 @@ static void draw_char(struct logo_config *config, unsigned char c, uint32_t x, u
 {
 	size_t pixel_size = sizeof(struct blt_pixel);
 	uint8_t *fb = (uint8_t *)config->framebuffer_base;
-	const uint32_t *glyph = get_glyph_data(c);
+
+	const uint8_t *glyph = get_glyph_data(c);
 	uint8_t actual_width = get_glyph_width(c);
 
 	for (int row = 0; row < CONFIG_FONT_HEIGHT; row++) {
-		uint32_t row_data = glyph[row];
-
 		for (int col = 0; col < actual_width; col++) {
-			uint32_t mask = (1 << (CONFIG_FONT_HEIGHT - 1));
-			if (row_data & (mask >> col)) {
-				uint32_t fb_x, fb_y;
-				get_rotated_text_coords(config, x, y, row, col, &fb_x, &fb_y);
+			/* Get the 8-bit alpha value (0-255) for this pixel */
+			uint8_t alpha = glyph[row * CONFIG_FONT_WIDTH + col];
 
-				if (fb_x < config->horizontal_resolution &&
-						 fb_y < config->vertical_resolution) {
-					struct blt_pixel *pixel = (struct blt_pixel *)
-							(fb + (fb_y * config->bytes_per_scanline) + (fb_x * pixel_size));
-					*pixel = color;
+			if (alpha == 0)
+				continue;
+
+			uint32_t fb_x, fb_y;
+			get_rotated_text_coords(config, x, y, row, col, &fb_x, &fb_y);
+
+			if (fb_x < config->horizontal_resolution &&
+				fb_y < config->vertical_resolution) {
+
+				struct blt_pixel *bg = (struct blt_pixel *)
+						(fb + (fb_y * config->bytes_per_scanline) + (fb_x * pixel_size));
+
+				if (alpha == 255) {
+					/* Fully opaque: just overwrite */
+					*bg = color;
+				} else {
+					/* Perform Alpha Blending */
+					bg->Red = (uint8_t)((color.Red * alpha + bg->Red * (255 - alpha)) / 255);
+					bg->Green = (uint8_t)((color.Green * alpha + bg->Green * (255 - alpha)) / 255);
+					bg->Blue = (uint8_t)((color.Blue * alpha + bg->Blue * (255 - alpha)) / 255);
 				}
 			}
 		}

From b9458ff2bc7175ea7778328268a66ff95fa8f4a0 Mon Sep 17 00:00:00 2001
From: Subrata Banik <subratabanik@google.com>
Date: Thu, 12 Feb 2026 18:37:37 +0530
Subject: [PATCH 3337/3886] lib: Implement resolution-based text scaling

Add support for dynamic text scaling based on the display resolution
to ensure bootsplash text remains legible on high-density panels.

Key changes:
- Implement get_resolution_scale() to determine a scaling factor (1x,
  2x, or 3x) based on the panel's major dimension (HD, QHD, or 4K).
- Update draw_char() to render glyphs as scaled blocks, repeating each
  font pixel across a square of the calculated scale factor.
- Apply the scaling factor to all text layout calculations, including
  kerning, character advance, and total string dimensions.
- Ensure anti-aliasing (alpha blending) is correctly applied to each
  individual pixel within the scaled blocks.

Change-Id: I8b22019ddaa46f1a24f38d565d946bb28a213791
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91182
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
---
 src/lib/render_text.c | 73 ++++++++++++++++++++++++++++++-------------
 1 file changed, 51 insertions(+), 22 deletions(-)

diff --git a/src/lib/render_text.c b/src/lib/render_text.c
index d20281b6e1..a87489a616 100644
--- a/src/lib/render_text.c
+++ b/src/lib/render_text.c
@@ -3,10 +3,30 @@
 #include <bootsplash.h>
 #include <console/console.h>
 #include <stdlib.h>
+#include <string.h>
 
 #include "fonts/fonts.h"
 #include "render_bmp.h"
 
+/* Major dimension for panel */
+#define PANEL_4K 3840
+#define PANEL_2K_QHD 2560
+
+/* Determine scaling factor based on display resolution */
+static uint32_t get_resolution_scale(struct logo_config *config)
+{
+	uint32_t width = config->horizontal_resolution;
+	uint32_t height = config->vertical_resolution;
+	uint32_t major_dim = (width > height) ? width : height;
+
+	if (major_dim >= PANEL_4K)
+		return 3;
+	else if (major_dim >= PANEL_2K_QHD)
+		return 2;
+	else /* HD / FHD Panels */
+		return 1;
+}
+
 /* Maps an unsigned character to the 8-bit alpha map (smoothing data) */
 static const uint8_t *get_glyph_data(unsigned char c)
 {
@@ -61,7 +81,7 @@ static inline void get_rotated_text_coords(struct logo_config *config,
  * @color:  Primary text color.
  */
 static void draw_char(struct logo_config *config, unsigned char c, uint32_t x, uint32_t y,
-		struct blt_pixel color)
+		struct blt_pixel color, uint32_t scale)
 {
 	size_t pixel_size = sizeof(struct blt_pixel);
 	uint8_t *fb = (uint8_t *)config->framebuffer_base;
@@ -77,23 +97,31 @@ static void draw_char(struct logo_config *config, unsigned char c, uint32_t x, u
 			if (alpha == 0)
 				continue;
 
-			uint32_t fb_x, fb_y;
-			get_rotated_text_coords(config, x, y, row, col, &fb_x, &fb_y);
+			/* Fill a scale x scale block for each font pixel */
+			for (uint32_t sy = 0; sy < scale; sy++) {
+				for (uint32_t sx = 0; sx < scale; sx++) {
+					uint32_t fb_x, fb_y;
+					get_rotated_text_coords(config, x, y,
+						(row * scale) + sy,
+						(col * scale) + sx,
+						&fb_x, &fb_y);
 
-			if (fb_x < config->horizontal_resolution &&
-				fb_y < config->vertical_resolution) {
+					if (fb_x < config->horizontal_resolution &&
+					    fb_y < config->vertical_resolution) {
+						struct blt_pixel *bg = (struct blt_pixel *)
+							(fb + (fb_y * config->bytes_per_scanline) + (fb_x * pixel_size));
 
-				struct blt_pixel *bg = (struct blt_pixel *)
-						(fb + (fb_y * config->bytes_per_scanline) + (fb_x * pixel_size));
-
-				if (alpha == 255) {
-					/* Fully opaque: just overwrite */
-					*bg = color;
-				} else {
-					/* Perform Alpha Blending */
-					bg->Red = (uint8_t)((color.Red * alpha + bg->Red * (255 - alpha)) / 255);
-					bg->Green = (uint8_t)((color.Green * alpha + bg->Green * (255 - alpha)) / 255);
-					bg->Blue = (uint8_t)((color.Blue * alpha + bg->Blue * (255 - alpha)) / 255);
+						if (alpha == 255) {
+							*bg = color;
+						} else {
+							bg->Red = (uint8_t)((color.Red * alpha + bg->Red *
+										 (255 - alpha)) / 255);
+							bg->Green = (uint8_t)((color.Green * alpha + bg->Green *
+										 (255 - alpha)) / 255);
+							bg->Blue = (uint8_t)((color.Blue * alpha + bg->Blue *
+										 (255 - alpha)) / 255);
+						}
+					}
 				}
 			}
 		}
@@ -157,11 +185,12 @@ void render_text_to_framebuffer(struct logo_config *config, const char *str,
 	if (len == 0)
 		return;
 
-	const uint32_t kerning = 1;
+	uint32_t scale = get_resolution_scale(config);
+	const uint32_t kerning = 1 * scale;
 	uint32_t total_width = 0;
 
 	for (size_t i = 0; i < len; i++)
-		total_width += get_glyph_width((unsigned char)str[i]) + kerning;
+		total_width += (get_glyph_width((unsigned char)str[i]) * scale) + kerning;
 
 	uint32_t text_w, text_h;
 	enum fw_splash_horizontal_alignment halign;
@@ -173,11 +202,11 @@ void render_text_to_framebuffer(struct logo_config *config, const char *str,
 
 	if (config->panel_orientation == LB_FB_ORIENTATION_LEFT_UP ||
 			 config->panel_orientation == LB_FB_ORIENTATION_RIGHT_UP) {
-		text_w = CONFIG_FONT_HEIGHT;
+		text_w = CONFIG_FONT_HEIGHT * scale;
 		text_h = total_width;
 	} else {
 		text_w = total_width;
-		text_h = CONFIG_FONT_HEIGHT;
+		text_h = CONFIG_FONT_HEIGHT * scale;
 	}
 
 	struct logo_coordinates coords = calculate_logo_coordinates(config->horizontal_resolution,
@@ -207,9 +236,9 @@ void render_text_to_framebuffer(struct logo_config *config, const char *str,
 	/* Loop through characters and draw them */
 	for (size_t i = 0; i < len; i++) {
 		unsigned char c = (unsigned char)str[i];
-		draw_char(config, c, cur_x, cur_y, text_color);
+		draw_char(config, c, cur_x, cur_y, text_color, scale);
 
-		uint32_t advance = get_glyph_width(c) + kerning;
+		uint32_t advance = (get_glyph_width(c) * scale) + kerning;
 		if (config->panel_orientation == LB_FB_ORIENTATION_RIGHT_UP)
 			cur_y += advance;
 		else if (config->panel_orientation == LB_FB_ORIENTATION_LEFT_UP)

From 6711ce38478332f9ab0cd5793342934170262af4 Mon Sep 17 00:00:00 2001
From: Subrata Banik <subratabanik@google.com>
Date: Wed, 11 Feb 2026 14:50:36 +0530
Subject: [PATCH 3338/3886] mb/google/fatcat: Increase OEM footer logo bottom
 margin to 200px

Update the logo_bottom_margin for all fatcat variants from 100px to
200px. This adjustment ensures the OEM footer logo and associated
splash text are rendered higher on the screen, improving visibility
and alignment with updated UX requirements.

Modified variants:
- fatcat
- felino
- francka
- kinmen
- lapis
- moonstone
- ruby

Change-Id: Ia0f446768f1b0b13c09873176f79ed4418f28aa2
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91155
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Jayvik Desai <jayvik@google.com>
Reviewed-by: Avi Uday <aviuday@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/google/fatcat/variants/fatcat/overridetree.cb   | 4 ++--
 src/mainboard/google/fatcat/variants/felino/overridetree.cb   | 4 ++--
 src/mainboard/google/fatcat/variants/francka/overridetree.cb  | 4 ++--
 src/mainboard/google/fatcat/variants/kinmen/overridetree.cb   | 4 ++--
 src/mainboard/google/fatcat/variants/lapis/overridetree.cb    | 2 ++
 .../google/fatcat/variants/moonstone/overridetree.cb          | 4 ++--
 src/mainboard/google/fatcat/variants/ruby/overridetree.cb     | 4 ++--
 7 files changed, 14 insertions(+), 12 deletions(-)

diff --git a/src/mainboard/google/fatcat/variants/fatcat/overridetree.cb b/src/mainboard/google/fatcat/variants/fatcat/overridetree.cb
index dc744d0cd1..db599a394b 100644
--- a/src/mainboard/google/fatcat/variants/fatcat/overridetree.cb
+++ b/src/mainboard/google/fatcat/variants/fatcat/overridetree.cb
@@ -132,8 +132,8 @@ chip soc/intel/pantherlake
 	#| I2C5              | Touchpad                  |
 	#+-------------------+---------------------------+
 	register "common_soc_config" = "{
-		/* Render OEM footer logo 100px above from the edge */
-		.logo_bottom_margin = 100,
+		/* Render OEM footer logo 200px above from the edge */
+		.logo_bottom_margin = 200,
 		.chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT,
 		.i2c[1] = {
 			.speed = I2C_SPEED_FAST,
diff --git a/src/mainboard/google/fatcat/variants/felino/overridetree.cb b/src/mainboard/google/fatcat/variants/felino/overridetree.cb
index 0be19ae39c..b70a1da722 100644
--- a/src/mainboard/google/fatcat/variants/felino/overridetree.cb
+++ b/src/mainboard/google/fatcat/variants/felino/overridetree.cb
@@ -102,8 +102,8 @@ chip soc/intel/pantherlake
 	#| I2C4              | CLICK PAD                 |
 	#+-------------------+---------------------------+
 	register "common_soc_config" = "{
-		/* Render OEM footer logo 100px above from the edge */
-		.logo_bottom_margin = 100,
+		/* Render OEM footer logo 200px above from the edge */
+		.logo_bottom_margin = 200,
 		.i2c[1] = {
 			.early_init=1,
 			.speed = I2C_SPEED_FAST,
diff --git a/src/mainboard/google/fatcat/variants/francka/overridetree.cb b/src/mainboard/google/fatcat/variants/francka/overridetree.cb
index 4b758ea293..3f26fb4878 100644
--- a/src/mainboard/google/fatcat/variants/francka/overridetree.cb
+++ b/src/mainboard/google/fatcat/variants/francka/overridetree.cb
@@ -79,8 +79,8 @@ chip soc/intel/pantherlake
 	#| I2C4              | Touchscreen, Touchpad     |
 	#+-------------------+---------------------------+
 	register "common_soc_config" = "{
-		/* Render OEM footer logo 100px above from the edge */
-		.logo_bottom_margin = 100,
+		/* Render OEM footer logo 200px above from the edge */
+		.logo_bottom_margin = 200,
 		.chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT,
 		.i2c[1] = {
 			.early_init = 1,
diff --git a/src/mainboard/google/fatcat/variants/kinmen/overridetree.cb b/src/mainboard/google/fatcat/variants/kinmen/overridetree.cb
index bee842d0b4..1eb39299dd 100644
--- a/src/mainboard/google/fatcat/variants/kinmen/overridetree.cb
+++ b/src/mainboard/google/fatcat/variants/kinmen/overridetree.cb
@@ -86,8 +86,8 @@ chip soc/intel/pantherlake
 	#| I2C5              | Touchscreen               |
 	#+-------------------+---------------------------+
 	register "common_soc_config" = "{
-		/* Render OEM footer logo 100px above from the edge */
-		.logo_bottom_margin = 100,
+		/* Render OEM footer logo 200px above from the edge */
+		.logo_bottom_margin = 200,
 		.chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT,
 		.i2c[3] = {
 			.early_init = 1,
diff --git a/src/mainboard/google/fatcat/variants/lapis/overridetree.cb b/src/mainboard/google/fatcat/variants/lapis/overridetree.cb
index 0a84ba36e9..762af4de21 100644
--- a/src/mainboard/google/fatcat/variants/lapis/overridetree.cb
+++ b/src/mainboard/google/fatcat/variants/lapis/overridetree.cb
@@ -112,6 +112,8 @@ chip soc/intel/pantherlake
 	#+-------------------+---------------------------+
 	register "common_soc_config" = "{
 		.chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT,
+		/* Render OEM footer logo 200px above from the edge */
+		.logo_bottom_margin = 200,
 		.i2c[3] = {
 			.early_init=1,
 			.speed = I2C_SPEED_FAST,
diff --git a/src/mainboard/google/fatcat/variants/moonstone/overridetree.cb b/src/mainboard/google/fatcat/variants/moonstone/overridetree.cb
index 16847cc41f..7faed6236c 100644
--- a/src/mainboard/google/fatcat/variants/moonstone/overridetree.cb
+++ b/src/mainboard/google/fatcat/variants/moonstone/overridetree.cb
@@ -111,8 +111,8 @@ chip soc/intel/pantherlake
 	#| I2C5              | Touchscreen               |
 	#+-------------------+---------------------------+
 	register "common_soc_config" = "{
-		/* Render OEM footer logo 100px above from the edge */
-		.logo_bottom_margin = 100,
+		/* Render OEM footer logo 200px above from the edge */
+		.logo_bottom_margin = 200,
 		.chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT,
 		.i2c[3] = {
 			.early_init = 1,
diff --git a/src/mainboard/google/fatcat/variants/ruby/overridetree.cb b/src/mainboard/google/fatcat/variants/ruby/overridetree.cb
index 90b39c4cd8..1c1399dc21 100644
--- a/src/mainboard/google/fatcat/variants/ruby/overridetree.cb
+++ b/src/mainboard/google/fatcat/variants/ruby/overridetree.cb
@@ -125,8 +125,8 @@ chip soc/intel/pantherlake
 	#| I2C5              | Touchscreen               |
 	#+-------------------+---------------------------+
 	register "common_soc_config" = "{
-		/* Render OEM footer logo 100px above from the edge */
-		.logo_bottom_margin = 100,
+		/* Render OEM footer logo 200px above from the edge */
+		.logo_bottom_margin = 200,
 		.chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT,
 		.i2c[0] = {
 			.speed = I2C_SPEED_FAST,

From 23c41622a90f957b91df6390656ded1a7b8aa16f Mon Sep 17 00:00:00 2001
From: Yu-Ping Wu <yupingso@chromium.org>
Date: Fri, 9 Jan 2026 16:58:14 +0800
Subject: [PATCH 3339/3886] commonlib/list: Change to circular list

This is a reland of
commit c4be70f6ff53 ("commonlib/list: Support circular list").

In some use cases, we want to add items to the linked list and then
iterate over them with the insertion order. With the current API, the
call site needs to either use the inefficient list_append() function to
append items to the end of the list, or manually maintain a "tail"
node pointer.

To support that use case, add an internal helper function _list_init()
to initialize the list as a circular one with a placeholder head node.
_list_init() is automatically called within list_insert_after() and
list_append(). In list_insert_before(), an assertion is added to avoid
an insertion before the head node (which should be invalid). The
implementation ensures that the list is initialized as a circular one
whenever the first element is added. That also allows all call sites to
be auto-upgraded to the "circular list" implementation without any
modification.

Modify list_for_each() to support circular lists, and improve
list_append() efficiency by inserting the new node before the
placeholder head node. Also add a few assertions in the implementation.

Add a new test case to test iterating over an empty list.

Note that '(uintptr_t)ptr + (uintptr_t)offsetof(typeof(*(ptr)), member)'
was used instead of the simpler '&((ptr)->member)' because GCC9+ assumes
that the address can never be NULL. See commit 88991caf00d3
("include/list.h: Add support for GCC9+") for details. Now, with the
new list_for_each() implementation, that pointer value can never be
NULL.

Change-Id: Idc22887cce71284c9028dce10eeef9cc16669028
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90962
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jakub "Kuba" Czapiga <czapiga@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
---
 src/commonlib/include/commonlib/list.h | 55 +++++++++++++++++-----
 src/commonlib/list.c                   | 65 +++++++++++++-------------
 tests/commonlib/list-test.c            | 23 +++++++--
 3 files changed, 94 insertions(+), 49 deletions(-)

diff --git a/src/commonlib/include/commonlib/list.h b/src/commonlib/include/commonlib/list.h
index ce74ca34b6..a6c87ceee2 100644
--- a/src/commonlib/include/commonlib/list.h
+++ b/src/commonlib/include/commonlib/list.h
@@ -9,55 +9,86 @@
 #include <stdint.h>
 
 struct list_node {
-	struct list_node *next;
-	struct list_node *prev;
+	struct _internal_do_not_access_list_node {
+		struct list_node *next;
+		struct list_node *prev;
+	} _internal_do_not_access;
 };
 
+// These macros do NOT belong to the public API.
+#define NEXT(ptr) ((ptr)->_internal_do_not_access.next)
+#define PREV(ptr) ((ptr)->_internal_do_not_access.prev)
+
+/* Initialize a circular list, with `head` being a placeholder head node. */
+void _list_init(struct list_node *head);
+
 // Remove list_node node from the doubly linked list it's a part of.
 void list_remove(struct list_node *node);
 // Insert list_node node after list_node after in a doubly linked list.
 void list_insert_after(struct list_node *node, struct list_node *after);
 // Insert list_node node before list_node before in a doubly linked list.
+// `before` must not be the placeholder head node.
 void list_insert_before(struct list_node *node, struct list_node *before);
 // Append the node to the end of the list.
-void list_append(struct list_node *node, struct list_node *head);
+static inline void list_append(struct list_node *node, struct list_node *head)
+{
+	_list_init(head);
+	/* With a circular list, we just need to insert before the head. */
+	list_insert_before(node, head);
+}
 
 // Return if the list is empty.
 static inline bool list_is_empty(const struct list_node *head)
 {
-	return !head->next;
+	return !NEXT(head) || NEXT(head) == head;
 }
 
 // Get next node.
 static inline struct list_node *list_next(const struct list_node *node,
 					  const struct list_node *head)
 {
-	return node->next;
+	return NEXT(node) == head ? NULL : NEXT(node);
 };
 
 // Get prev node.
 static inline struct list_node *list_prev(const struct list_node *node,
 					  const struct list_node *head)
 {
-	return node->prev == head ? NULL : node->prev;
+	return PREV(node) == head ? NULL : PREV(node);
 };
 
 // Get first node.
 static inline struct list_node *list_first(const struct list_node *head)
 {
-	return list_is_empty(head) ? NULL : head->next;
+	return list_next(head, head);
 }
 
 // Get last node.
-struct list_node *list_last(const struct list_node *head);
+static inline struct list_node *list_last(const struct list_node *head)
+{
+	return list_prev(head, head);
+}
 
 // Get the number of list elements.
 size_t list_length(const struct list_node *head);
 
-#define list_for_each(ptr, head, member)                                      \
-	for ((ptr) = container_of((head).next, typeof(*(ptr)), member);       \
-		(uintptr_t)ptr + (uintptr_t)offsetof(typeof(*(ptr)), member); \
-		(ptr) = container_of((ptr)->member.next,                      \
+/*
+ * Explanation of `ptr` initialization:
+ * 1. head.next != NULL: This means the list isn't empty. As the implementation ensures that
+ *    _list_init() is called when the very first element is added, we can safely assume that
+ *    the list is circular, and hence set `ptr` to the 1st element.
+ * 2. head.next == NULL: This means the list is empty, and _list_init() hasn't been called.
+ *    As the `head` arg might be const, we cannot simply call _list_init() here. Instead, we set
+ *    `ptr` to a special value such that `&(ptr->member) == &head`, causing the loop to
+ *    terminate immediately.
+ */
+#define list_for_each(ptr, head, member) \
+	for ((ptr) = container_of((head)._internal_do_not_access.next ?: &(head), typeof(*(ptr)), member); \
+		&((ptr)->member) != &(head); \
+		(ptr) = container_of((ptr)->member._internal_do_not_access.next, \
 			typeof(*(ptr)), member))
 
+#undef NEXT
+#undef PREV
+
 #endif /* __COMMONLIB_LIST_H__ */
diff --git a/src/commonlib/list.c b/src/commonlib/list.c
index 1af92c8ac5..93a9b12887 100644
--- a/src/commonlib/list.c
+++ b/src/commonlib/list.c
@@ -1,51 +1,47 @@
 /* Taken from depthcharge: src/base/list.c */
 /* SPDX-License-Identifier: GPL-2.0-or-later */
 
+#include <assert.h>
 #include <commonlib/list.h>
 
+#define NEXT(ptr) ((ptr)->_internal_do_not_access.next)
+#define PREV(ptr) ((ptr)->_internal_do_not_access.prev)
+
+void _list_init(struct list_node *head)
+{
+	if (!NEXT(head)) {
+		assert(!PREV(head));
+		PREV(head) = NEXT(head) = head;
+	}
+}
+
 void list_remove(struct list_node *node)
 {
-	if (node->prev)
-		node->prev->next = node->next;
-	if (node->next)
-		node->next->prev = node->prev;
+	/* Cannot remove the head node. */
+	assert(PREV(node) && NEXT(node));
+	NEXT(PREV(node)) = NEXT(node);
+	PREV(NEXT(node)) = PREV(node);
 }
 
 void list_insert_after(struct list_node *node, struct list_node *after)
 {
-	node->next = after->next;
-	node->prev = after;
-	after->next = node;
-	if (node->next)
-		node->next->prev = node;
+	/* Check uninitialized head node. */
+	if (!PREV(after))
+		_list_init(after);
+	NEXT(node) = NEXT(after);
+	PREV(node) = after;
+	NEXT(after) = node;
+	PREV(NEXT(node)) = node;
 }
 
 void list_insert_before(struct list_node *node, struct list_node *before)
 {
-	node->prev = before->prev;
-	node->next = before;
-	before->prev = node;
-	if (node->prev)
-		node->prev->next = node;
-}
-
-void list_append(struct list_node *node, struct list_node *head)
-{
-	while (head->next)
-		head = head->next;
-
-	list_insert_after(node, head);
-}
-
-struct list_node *list_last(const struct list_node *head)
-{
-	if (!head->next)
-		return NULL;
-
-	struct list_node *ptr = head->next;
-	while (ptr->next)
-		ptr = ptr->next;
-	return ptr;
+	/* `before` cannot be an uninitialized head node. */
+	assert(PREV(before));
+	PREV(node) = PREV(before);
+	NEXT(node) = before;
+	PREV(before) = node;
+	NEXT(PREV(node)) = node;
 }
 
 size_t list_length(const struct list_node *head)
@@ -60,3 +56,6 @@ size_t list_length(const struct list_node *head)
 
 	return len;
 }
+
+#undef NEXT
+#undef PREV
diff --git a/tests/commonlib/list-test.c b/tests/commonlib/list-test.c
index 568fa1d3dd..e4dbd8e14a 100644
--- a/tests/commonlib/list-test.c
+++ b/tests/commonlib/list-test.c
@@ -45,7 +45,7 @@ static void test_list_one_node(void **state)
 static void test_list_insert_after(void **state)
 {
 	int i = 0;
-	struct list_node head = { .prev = NULL, .next = NULL };
+	struct list_node head = {};
 	struct test_container *c1 = (struct test_container *)malloc(sizeof(*c1));
 	struct test_container *c2 = (struct test_container *)malloc(sizeof(*c2));
 	struct test_container *c3 = (struct test_container *)malloc(sizeof(*c2));
@@ -86,7 +86,7 @@ static void test_list_insert_after(void **state)
 static void test_list_insert_before(void **state)
 {
 	int i = 0;
-	struct list_node head = { .prev = NULL, .next = NULL };
+	struct list_node head = {};
 	struct test_container *c1 = (struct test_container *)malloc(sizeof(*c1));
 	struct test_container *c2 = (struct test_container *)malloc(sizeof(*c2));
 	struct test_container *c3 = (struct test_container *)malloc(sizeof(*c2));
@@ -105,7 +105,6 @@ static void test_list_insert_before(void **state)
 	list_insert_before(&c2->list_node, &c3->list_node);
 	list_insert_before(&c1->list_node, &c2->list_node);
 
-
 	list_for_each(ptr, head, list_node) {
 		assert_int_equal(values[i], ptr->value);
 		i++;
@@ -120,9 +119,17 @@ static void test_list_insert_before(void **state)
 	free(c1);
 }
 
+static void test_list_insert_before_head(void **state)
+{
+	struct list_node head = {};
+	struct test_container c = {};
+
+	expect_assert_failure(list_insert_before(&c.list_node, &head));
+}
+
 static void test_list_remove(void **state)
 {
-	struct list_node head = { .prev = NULL, .next = NULL };
+	struct list_node head = {};
 	struct test_container *c1 = (struct test_container *)malloc(sizeof(*c1));
 	struct test_container *c2 = (struct test_container *)malloc(sizeof(*c2));
 
@@ -141,6 +148,12 @@ static void test_list_remove(void **state)
 	free(c1);
 }
 
+static void test_list_remove_head(void **state)
+{
+	struct list_node head = {};
+	expect_assert_failure(list_remove(&head));
+}
+
 static void test_list_append(void **state)
 {
 	size_t idx;
@@ -170,7 +183,9 @@ int main(void)
 		cmocka_unit_test(test_list_one_node),
 		cmocka_unit_test(test_list_insert_after),
 		cmocka_unit_test(test_list_insert_before),
+		cmocka_unit_test(test_list_insert_before_head),
 		cmocka_unit_test(test_list_remove),
+		cmocka_unit_test(test_list_remove_head),
 		cmocka_unit_test(test_list_append),
 	};
 

From 61ae24a854b5a5de21278832802858f3057ca413 Mon Sep 17 00:00:00 2001
From: Kenneth Chan <kenneth.chan@quanta.corp-partner.google.com>
Date: Thu, 5 Feb 2026 16:19:06 +0800
Subject: [PATCH 3340/3886] mb/google/brask/var/moxoe: Enable PCIe WiFi 7
 support

Add configuration for the PCIe Root Port connected to the WiFi 7 module.

BUG=b:481186489
TEST=Build successfully for moxoe. Verify WiFi 7 functionality on
 moxie.

Change-Id: I8941b587ac35f6c03654de959cc93350b5604b35
Signed-off-by: Kenneth Chan <kenneth.chan@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91103
Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
---
 .../brya/variants/moxoe/overridetree.cb       | 32 ++++++++++++++++++-
 1 file changed, 31 insertions(+), 1 deletion(-)

diff --git a/src/mainboard/google/brya/variants/moxoe/overridetree.cb b/src/mainboard/google/brya/variants/moxoe/overridetree.cb
index 9733305b69..71268f88ac 100644
--- a/src/mainboard/google/brya/variants/moxoe/overridetree.cb
+++ b/src/mainboard/google/brya/variants/moxoe/overridetree.cb
@@ -13,6 +13,10 @@ fw_config
 		option TC_USB4	0
 		option TC_USB3	1
 	end
+	field WIFI_TYPE 10
+		option WIFI_PCIE	0
+		option WIFI_CNVI	1
+	end
 	field USB_HUB 32
 		option HUB_ABSENT	0
 		option HUB_PRESENT	1
@@ -176,7 +180,9 @@ chip soc/intel/alderlake
 		device ref cnvi_wifi on
 			chip drivers/wifi/generic
 				register "wake" = "GPE0_PME_B0"
-				device generic 0 on end
+				device generic 0 on
+					probe WIFI_TYPE WIFI_CNVI
+				end
 			end
 		end
 		device ref i2c0 on
@@ -205,6 +211,30 @@ chip soc/intel/alderlake
 				end
 			end
 		end
+		device ref pcie_rp5 on
+			probe WIFI_TYPE WIFI_PCIE
+			# Enable wlan PCIe 5 using clk 2
+			register "pch_pcie_rp[PCH_RP(5)]" = "{
+				.clk_src = 2,
+				.clk_req = 2,
+				.flags = PCIE_RP_LTR | PCIE_RP_AER,
+			}"
+			chip drivers/wifi/generic
+				register "wake" = "GPE0_DW1_03"
+				register "add_acpi_dma_property" = "true"
+				device pci 00.0 on
+					probe WIFI_TYPE WIFI_PCIE
+				end
+			end
+			chip soc/intel/common/block/pcie/rtd3
+				register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B11)"
+				register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_H20)"
+				register "srcclk_pin" = "2"
+				device generic 0 on
+					probe WIFI_TYPE WIFI_PCIE
+				end
+			end
+		end     #PCIE5 WLAN card
 		device ref pcie_rp7 on
 			chip drivers/net
 				register "wake" = "GPE0_DW0_07"

From 51039db875c3831996befc40474d6bfba9f456fa Mon Sep 17 00:00:00 2001
From: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Date: Thu, 12 Feb 2026 09:17:41 +0800
Subject: [PATCH 3341/3886] /mb/google/nissa/var/yavilla: Add LXST2024 LGD
 touchscreen

This CL aims to make the code support ready before touchscreen launch.

BUG=b:483762467
TEST=build nissa coreboot image

Change-Id: I919f92b782905ea9184203804f5ea095e37e9893
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91169
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
---
 .../brya/variants/yavilla/overridetree.cb      | 18 ++++++++++++++++++
 1 file changed, 18 insertions(+)

diff --git a/src/mainboard/google/brya/variants/yavilla/overridetree.cb b/src/mainboard/google/brya/variants/yavilla/overridetree.cb
index ce890af476..3686de90e9 100644
--- a/src/mainboard/google/brya/variants/yavilla/overridetree.cb
+++ b/src/mainboard/google/brya/variants/yavilla/overridetree.cb
@@ -329,6 +329,24 @@ chip soc/intel/alderlake
 					probe TOUCH_PANEL TOUCH_G2_HID_I2c
 				end
                         end
+			chip drivers/i2c/hid
+				register "generic.hid" = ""LXST2024""
+				register "generic.desc" = ""LGD Touchscreen""
+				register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_C7_IRQ)"
+				register "generic.detect" = "1"
+				register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C1)"
+				register "generic.reset_delay_ms" = "20"
+				register "generic.reset_off_delay_ms" = "2"
+				register "generic.stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C6)"
+				register "generic.stop_delay_ms" = "280"
+				register "generic.stop_off_delay_ms" = "2"
+				register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C0)"
+				register "generic.enable_delay_ms" = "1"
+				register "generic.has_power_resource" = "1"
+				register "generic.use_gpio_for_status" = "true"
+				register "hid_desc_reg_offset" = "0x00"
+				device i2c 34 on end
+			end
 			chip drivers/i2c/hid
 				register "generic.hid" = ""GTCH7503""
 				register "generic.desc" = ""G2TOUCH Touchscreen""

From 1148ced5cab0297a1d8344f8de71dfe7cf6d8562 Mon Sep 17 00:00:00 2001
From: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Date: Wed, 11 Feb 2026 17:44:18 +0800
Subject: [PATCH 3342/3886] mb/google/brox/var/caboc: Add LXST2024 LGD
 touchscreen

This CL aims to make the code support ready before touchscreen launch.

BUG=b:483588481
TEST=build brox coreboot image

Change-Id: I9f8715311c976e92049ff3058920039c0d38ba3a
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91156
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com>
---
 .../google/brox/variants/caboc/overridetree.cb    | 15 +++++++++++++++
 1 file changed, 15 insertions(+)

diff --git a/src/mainboard/google/brox/variants/caboc/overridetree.cb b/src/mainboard/google/brox/variants/caboc/overridetree.cb
index 9816c123c1..0587d16324 100644
--- a/src/mainboard/google/brox/variants/caboc/overridetree.cb
+++ b/src/mainboard/google/brox/variants/caboc/overridetree.cb
@@ -419,6 +419,21 @@ chip soc/intel/alderlake
 					probe PANEL TOUCH_G2TOUCH_HID_I2C
 				end
 			end
+			chip drivers/i2c/hid
+				register "generic.hid" = ""LXST2024""
+				register "generic.desc" = ""LGD Touchscreen""
+				register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_F18_IRQ)"
+				register "generic.detect" = "1"
+				register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_F17)"
+				register "generic.reset_delay_ms" = "150"
+				register "generic.reset_off_delay_ms" = "2"
+				register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_F7)"
+				register "generic.enable_delay_ms" = "1"
+				register "generic.has_power_resource" = "1"
+				register "generic.use_gpio_for_status" = "true"
+				register "hid_desc_reg_offset" = "0x00"
+				device i2c 34 on end
+			end
 		end
 		device ref gspi1 on
 			chip drivers/spi/acpi

From 8d020508fc1f08d9bde3e140410aaaba2815253c Mon Sep 17 00:00:00 2001
From: Cliff Huang <cliff.huang@intel.com>
Date: Tue, 27 Aug 2024 19:56:13 -0700
Subject: [PATCH 3343/3886] payloads/depthcharge: Add default 64-bit libpayload
 config
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Add CONFIG_LP_DEFCONFIG_OVERRIDE_X64 flag to select default 64-bit
config file in payloads/libpayload/configs directory.

This is used in standalone environment. The existing libpayload
deconfig file is for boards with 32-bit format and deconfig_64
file is added for 64-bit without adding specific
board.[board name] file in libpayload.

BUG=none
TEST=Build with this new flag and check that the libpayload and
depthcharge.elf are built in 64-bit format.

Signed-off-by: Cliff Huang <cliff.huang@intel.com>
Change-Id: Iac07cf9e3c11e49955c69553407be76ef4f8c060
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84107
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kim, Wonkyu <wonkyu.kim@intel.com>
---
 payloads/external/Makefile.mk            |  3 ++-
 payloads/external/depthcharge/Kconfig    | 11 +++++++++++
 payloads/external/depthcharge/Makefile   |  3 +++
 payloads/libpayload/configs/defconfig_64 |  9 +++++++++
 payloads/libpayload/curses/Makefile.mk   |  5 ++++-
 5 files changed, 29 insertions(+), 2 deletions(-)
 create mode 100644 payloads/libpayload/configs/defconfig_64

diff --git a/payloads/external/Makefile.mk b/payloads/external/Makefile.mk
index 1a494486db..a15ec2f378 100644
--- a/payloads/external/Makefile.mk
+++ b/payloads/external/Makefile.mk
@@ -152,7 +152,8 @@ payloads/external/depthcharge/depthcharge/build/depthcharge.elf depthcharge: $(D
 		DEPTHCHARGE_STABLE=$(CONFIG_DEPTHCHARGE_STABLE) \
 		DEPTHCHARGE_REVISION=$(CONFIG_DEPTHCHARGE_REVISION) \
 		DEPTHCHARGE_REVISION_ID=$(CONFIG_DEPTHCHARGE_REVISION_ID) \
-		OVERRIDE_DEFCONFIG=$(CONFIG_LP_DEFCONFIG_OVERRIDE)
+		OVERRIDE_DEFCONFIG=$(CONFIG_LP_DEFCONFIG_OVERRIDE) \
+		OVERRIDE_DEFCONFIG_64=$(CONFIG_LP_DEFCONFIG_OVERRIDE_X64)
 
 # edk2
 
diff --git a/payloads/external/depthcharge/Kconfig b/payloads/external/depthcharge/Kconfig
index 86b20abcaf..7a9c7d7596 100644
--- a/payloads/external/depthcharge/Kconfig
+++ b/payloads/external/depthcharge/Kconfig
@@ -62,4 +62,15 @@ config LP_DEFCONFIG_OVERRIDE
 	  instead.  This is can be a convenience for development purposes, or
 	  if the defaults in defconfig are sufficient for your system.
 
+config LP_DEFCONFIG_OVERRIDE_X64
+	bool "Use default 64-bit libpayload config"
+	depends on !LP_DEFCONFIG_OVERRIDE
+	help
+	  The Depthcharge makefile looks for a file config.<boardname> in the
+	  libpayload/configs directory.  Say Y here to use the file defconfig
+	  for 64-bit format instead. This can be convenient for development for
+	  a new board, or if the defaults in 64-bit defconfig file (i.e.
+	  defconfig_64) are sufficient for your system without creating
+	  board.[name] file.
+
 endif
diff --git a/payloads/external/depthcharge/Makefile b/payloads/external/depthcharge/Makefile
index af303da872..2328d6d2c6 100644
--- a/payloads/external/depthcharge/Makefile
+++ b/payloads/external/depthcharge/Makefile
@@ -30,6 +30,9 @@ BOARD:=$(notdir $(CONFIG_MAINBOARD_DIR))
 ifeq ($(OVERRIDE_DEFCONFIG),y)
 libpayload_config=$(libpayload_dir)/configs/defconfig
 DEPTHCHARGE_LIBPAYLOAD_MSG="Depthcharge: Using default defconfig for libpayload"
+else ifeq ($(OVERRIDE_DEFCONFIG_64),y)
+libpayload_config=$(libpayload_dir)/configs/defconfig_64
+DEPTHCHARGE_LIBPAYLOAD_MSG="Depthcharge: Using default defconfig for 64-bit libpayload"
 else
 libpayload_config=$(libpayload_dir)/configs/config.$(BOARD)
 DEPTHCHARGE_LIBPAYLOAD_MSG="Depthcharge: Using $(libpayload_dir)/configs/config.$(BOARD)"
diff --git a/payloads/libpayload/configs/defconfig_64 b/payloads/libpayload/configs/defconfig_64
new file mode 100644
index 0000000000..9db83c0635
--- /dev/null
+++ b/payloads/libpayload/configs/defconfig_64
@@ -0,0 +1,9 @@
+CONFIG_LP_ARCH_X86_64=y
+# CONFIG_LP_MULTIBOOT is not set
+CONFIG_LP_COREBOOT_VIDEO_CONSOLE=y
+CONFIG_LP_USB=y
+CONFIG_LP_USB_UHCI=y
+CONFIG_LP_USB_OHCI=y
+CONFIG_LP_USB_EHCI=y
+CONFIG_LP_USB_XHCI=y
+CONFIG_LP_HEAP_SIZE=1048576
diff --git a/payloads/libpayload/curses/Makefile.mk b/payloads/libpayload/curses/Makefile.mk
index 99f8d70e05..8c8c401c65 100644
--- a/payloads/libpayload/curses/Makefile.mk
+++ b/payloads/libpayload/curses/Makefile.mk
@@ -38,7 +38,10 @@ includes-$(CONFIG_LP_TINYCURSES) += curses.h
 
 ifeq ($(CONFIG_LP_PDCURSES),y)
 PDCURSES := PDCurses
-INCLUDES += -D_LP64=0 -Icurses/$(PDCURSES) -Icurses/pdcurses-backend -Icurses/menu -Icurses/form
+ifneq ($(CONFIG_LP_ARCH_X86_64),y)
+INCLUDES += -D_LP64=0
+endif
+INCLUDES += -Icurses/$(PDCURSES) -Icurses/pdcurses-backend -Icurses/menu -Icurses/form
 endif
 
 libcurses-$(CONFIG_LP_PDCURSES) += pdcurses-backend/pdcdisp.c

From 93c52ed3405971602ee99b0d3c14582be3a23e07 Mon Sep 17 00:00:00 2001
From: Kapil Porwal <kapilporwal@google.com>
Date: Wed, 11 Feb 2026 13:34:26 +0530
Subject: [PATCH 3344/3886] mb/google/bluey: Add parallel charging
 configuration

BUG=b:468120472
TEST=Probe and verify the GPIOs on Google/Quartz.

Change-Id: I414509d40e3c6e4495dcdb56a8abfd300caf47d9
Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91153
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/google/bluey/board.h     |  1 +
 src/mainboard/google/bluey/charging.c  | 17 +++++++++++++++--
 src/mainboard/google/bluey/mainboard.c |  2 ++
 3 files changed, 18 insertions(+), 2 deletions(-)

diff --git a/src/mainboard/google/bluey/board.h b/src/mainboard/google/bluey/board.h
index 3d42d89a48..d5218b469b 100644
--- a/src/mainboard/google/bluey/board.h
+++ b/src/mainboard/google/bluey/board.h
@@ -53,6 +53,7 @@
 void setup_chromeos_gpios(void);
 bool is_off_mode(void);
 void configure_parallel_charging(void);
+void configure_parallel_charging_late(void);
 void enable_slow_battery_charging(void);
 void disable_slow_battery_charging(void);
 
diff --git a/src/mainboard/google/bluey/charging.c b/src/mainboard/google/bluey/charging.c
index 95f98a0799..6027dc3c6b 100644
--- a/src/mainboard/google/bluey/charging.c
+++ b/src/mainboard/google/bluey/charging.c
@@ -34,6 +34,8 @@ enum charging_status {
 #define OUTPUT_INVERT		0x80
 #define PERPH_EN		0x80
 
+#define GPIO_PARALLEL_CHARGING_CFG GPIO(71)
+
 /*
  * Enable PMC8380F GPIO07 & GPIO09 for parallel charging.
  */
@@ -43,12 +45,23 @@ void configure_parallel_charging(void)
 		return;
 
 	printk(BIOS_INFO, "Configure parallel charging support\n");
-	spmi_write8(SPMI_ADDR(PMC8380F_SLAVE_ID, GPIO07_MODE_CTL), MODE_OUTPUT);
 	spmi_write8(SPMI_ADDR(PMC8380F_SLAVE_ID, GPIO07_DIG_OUT_SOURCE_CTL), OUTPUT_INVERT);
 	spmi_write8(SPMI_ADDR(PMC8380F_SLAVE_ID, GPIO07_EN_CTL), PERPH_EN);
-	spmi_write8(SPMI_ADDR(PMC8380F_SLAVE_ID, GPIO09_MODE_CTL), MODE_OUTPUT);
+	spmi_write8(SPMI_ADDR(PMC8380F_SLAVE_ID, GPIO07_MODE_CTL), MODE_OUTPUT);
 	spmi_write8(SPMI_ADDR(PMC8380F_SLAVE_ID, GPIO09_DIG_OUT_SOURCE_CTL), OUTPUT_INVERT);
 	spmi_write8(SPMI_ADDR(PMC8380F_SLAVE_ID, GPIO09_EN_CTL), PERPH_EN);
+	spmi_write8(SPMI_ADDR(PMC8380F_SLAVE_ID, GPIO09_MODE_CTL), MODE_OUTPUT);
+}
+
+/*
+ * Late configuration for parallel charging.
+ */
+void configure_parallel_charging_late(void)
+{
+	if (!CONFIG(MAINBOARD_SUPPORTS_PARALLEL_CHARGING))
+		return;
+
+	gpio_output(GPIO_PARALLEL_CHARGING_CFG, 1);
 }
 
 /*
diff --git a/src/mainboard/google/bluey/mainboard.c b/src/mainboard/google/bluey/mainboard.c
index 5b6278b3a0..099f825344 100644
--- a/src/mainboard/google/bluey/mainboard.c
+++ b/src/mainboard/google/bluey/mainboard.c
@@ -122,6 +122,8 @@ void lb_add_boot_mode(struct lb_header *header)
 	mode->size = sizeof(*mode);
 	mode->boot_mode = get_boot_mode();
 
+	configure_parallel_charging_late();
+
 	/* Enable charging only during off-mode or low-battery mode with charger present */
 	if (is_low_power_boot_with_charger())
 		enable_slow_battery_charging();

From 77d5cb358ee406012bb9a30a30d8634624805e5c Mon Sep 17 00:00:00 2001
From: Jayvik Desai <jayvik@google.com>
Date: Tue, 3 Feb 2026 18:31:06 +0530
Subject: [PATCH 3345/3886] mb/google/bluey: Add support to enable charging for
 debug access port

When the system is in a low-power boot state or early charging mode,
it is necessary to enable charging even when a debug access port
is connected. This ensures that developers can charge the
device while using the servov4.1 with the charger.

This patch updates the charging configuration to enable the debug
access sink by writing to the TYPE_C_TYPE_C_DEBUG_ACCESS_SNK_CFG
register.

BUG=b:474297115
TEST=Build Google/quartz

Change-Id: I155b071e678c8bc0ff0d719ac924b5026b21b37a
Signed-off-by: Jayvik Desai <jayvik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91077
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
---
 src/mainboard/google/bluey/Kconfig    | 6 ++++++
 src/mainboard/google/bluey/charging.c | 7 +++++++
 2 files changed, 13 insertions(+)

diff --git a/src/mainboard/google/bluey/Kconfig b/src/mainboard/google/bluey/Kconfig
index 2021787699..6dc2325465 100644
--- a/src/mainboard/google/bluey/Kconfig
+++ b/src/mainboard/google/bluey/Kconfig
@@ -123,6 +123,12 @@ config MAINBOARD_SUPPORTS_PARALLEL_CHARGING
 	help
 	  Enable this option if your mainboard supports parallel charging.
 
+config HAVE_CHARGING_DEBUG_ACCESS_PORT
+	bool
+	default n
+	help
+	  Enable this option to allow charging on the debug access port.
+
 config MAINBOARD_HAS_GOOGLE_TPM
 	bool
 	default n
diff --git a/src/mainboard/google/bluey/charging.c b/src/mainboard/google/bluey/charging.c
index 6027dc3c6b..5252a1e531 100644
--- a/src/mainboard/google/bluey/charging.c
+++ b/src/mainboard/google/bluey/charging.c
@@ -11,11 +11,15 @@
 #define SMB1_CHGR_MAX_FCC_CFG ((SMB1_SLAVE_ID << 16) | SCHG_CHGR_MAX_FAST_CHARGE_CURRENT_CFG)
 #define SMB2_CHGR_MAX_FCC_CFG ((SMB2_SLAVE_ID << 16) | SCHG_CHGR_MAX_FAST_CHARGE_CURRENT_CFG)
 #define SCHG_CHGR_CHARGING_ENABLE_CMD 0x2642
+#define SCHG_TYPE_C_TYPE_C_DEBUG_ACCESS_SNK_CFG 0x2B4A
 #define SMB1_CHGR_CHRG_EN_CMD ((SMB1_SLAVE_ID << 16) | SCHG_CHGR_CHARGING_ENABLE_CMD)
 #define SMB2_CHGR_CHRG_EN_CMD ((SMB2_SLAVE_ID << 16) | SCHG_CHGR_CHARGING_ENABLE_CMD)
+#define SMB1_SCHG_TYPE_C_TYPE_C_DEBUG_ACCESS_SNK_CFG \
+((SMB1_SLAVE_ID << 16) | SCHG_TYPE_C_TYPE_C_DEBUG_ACCESS_SNK_CFG)
 
 #define FCC_1A_STEP_50MA 0x14
 #define FCC_DISABLE 0x8c
+#define EN_DEBUG_ACCESS_SNK 0x1B
 
 enum charging_status {
 	CHRG_DISABLE,
@@ -75,6 +79,9 @@ void enable_slow_battery_charging(void)
 	spmi_write8(SMB2_CHGR_MAX_FCC_CFG, FCC_1A_STEP_50MA);
 	spmi_write8(SMB1_CHGR_CHRG_EN_CMD, CHRG_ENABLE);
 	spmi_write8(SMB2_CHGR_CHRG_EN_CMD, CHRG_ENABLE);
+
+	if (CONFIG(HAVE_CHARGING_DEBUG_ACCESS_PORT))
+		spmi_write8(SMB1_SCHG_TYPE_C_TYPE_C_DEBUG_ACCESS_SNK_CFG, EN_DEBUG_ACCESS_SNK);
 }
 
 /*

From 542289bf56816293959b85a40d3ed30afd894055 Mon Sep 17 00:00:00 2001
From: Jayvik Desai <jayvik@google.com>
Date: Thu, 12 Feb 2026 16:48:38 +0530
Subject: [PATCH 3346/3886] mb/google/bluey/quartz: Enable charging for debug
 access port for quartz

Select HAVE_CHARGING_DEBUG_ACCESS_PORT for the Quartz variant.

BUG=b:474297115
TEST=Verified that quartz starts charging when the charger is connected
via the servov4.1 to the C0 port.
TEST=Verified that quartz starts charging when the charger is directly
connected to the C0 port.
TEST=Verified that the battery is charging by checking the battery
State of charge after 20-30 mins of charging.

Change-Id: Ie5e0d980780daa0adeee4e6a3e3525eb2616a29f
Signed-off-by: Jayvik Desai <jayvik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91181
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
---
 src/mainboard/google/bluey/Kconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/src/mainboard/google/bluey/Kconfig b/src/mainboard/google/bluey/Kconfig
index 6dc2325465..45017a4e01 100644
--- a/src/mainboard/google/bluey/Kconfig
+++ b/src/mainboard/google/bluey/Kconfig
@@ -55,6 +55,7 @@ config BOARD_GOOGLE_QUENBIH
 
 config BOARD_GOOGLE_QUARTZ
 	select BOARD_GOOGLE_MODEL_QUARTZ
+	select HAVE_CHARGING_DEBUG_ACCESS_PORT
 	select SOC_QUALCOMM_HAMOA
 	select MAINBOARD_HAS_PS8820_RETIMER
 	select MAINBOARD_NO_USB_A_PORT

From cb1668acb82018fd3d5845db61cf65539e9ebf2a Mon Sep 17 00:00:00 2001
From: Pranava Y N <pranavayn@google.com>
Date: Thu, 12 Feb 2026 18:17:56 +0530
Subject: [PATCH 3347/3886] mb/google/fatcat/var/lapis: Enable SMBus controller

The SMBus controller was previously disabled on the Lapis variant.
Enable the SMBus device in the overridetree to allow the system to
communicate with onboard peripherals like the SPD EEPROMs and
thermal sensors.

BUG=none
TEST=Build and boot on Lapis; verify smbus is initialized.

Change-Id: I9d7254b6c2686ec67392294d45b870e3670f2aca
Signed-off-by: Pranava Y N <pranavayn@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91196
Reviewed-by: Avi Uday <aviuday@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/google/fatcat/variants/lapis/overridetree.cb | 1 +
 1 file changed, 1 insertion(+)

diff --git a/src/mainboard/google/fatcat/variants/lapis/overridetree.cb b/src/mainboard/google/fatcat/variants/lapis/overridetree.cb
index 762af4de21..db79988b95 100644
--- a/src/mainboard/google/fatcat/variants/lapis/overridetree.cb
+++ b/src/mainboard/google/fatcat/variants/lapis/overridetree.cb
@@ -517,6 +517,7 @@ chip soc/intel/pantherlake
 				end
 			end
 		end # SNDW
+		device ref smbus on end
 		device ref i2c0 on end
 		device ref i2c3 on
 			chip drivers/i2c/tpm

From 8cc632b5d0cd676c7828aac56b94453577088875 Mon Sep 17 00:00:00 2001
From: Hualin Wei <weihualin@huaqin.corp-partner.google.com>
Date: Thu, 12 Feb 2026 20:48:16 +0800
Subject: [PATCH 3348/3886] mb/google/fatcat/var/lapis: Turn off ipu

The Lapis project uses a USB camera and does not have
a MIPI camera, therefore the IPU interface is disabled.

BUG=b:475355637
TEST=emerge-fatcat coreboot

Change-Id: I35273251d73a3f885b7dd8750b746dbca06e9564
Signed-off-by: Hualin Wei <weihualin@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91180
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com>
Reviewed-by: Pranava Y N <pranavayn@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/google/fatcat/variants/lapis/overridetree.cb | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/mainboard/google/fatcat/variants/lapis/overridetree.cb b/src/mainboard/google/fatcat/variants/lapis/overridetree.cb
index db79988b95..04565a14ef 100644
--- a/src/mainboard/google/fatcat/variants/lapis/overridetree.cb
+++ b/src/mainboard/google/fatcat/variants/lapis/overridetree.cb
@@ -282,7 +282,7 @@ chip soc/intel/pantherlake
 				device generic 0 on end
 			end
 		end
-		device ref ipu on end
+		device ref ipu off end
 		device ref iaa off end
 		device ref tbt_pcie_rp0 on end
 		device ref tbt_pcie_rp2 on end

From e95ed7aecf25b48dcc77aca34cbc3949c18f6f7d Mon Sep 17 00:00:00 2001
From: Patrick Rudolph <patrick.rudolph@9elements.com>
Date: Thu, 12 Feb 2026 16:05:59 +0100
Subject: [PATCH 3349/3886] soc/amd/*/acpi: Add root complex ACPI device

The Root complex always resides at 0:0.0 and is always enabled.
Add a static device in DSDT that can be extended later on.

Change-Id: I1d45f7cd732c41343ac154c313a7ca368b0ea2b3
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91183
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/soc/amd/cezanne/acpi/pci.asl   | 10 ++++++++++
 src/soc/amd/cezanne/root_complex.c |  1 -
 src/soc/amd/glinda/acpi/pci.asl    | 10 ++++++++++
 src/soc/amd/mendocino/acpi/pci.asl | 10 ++++++++++
 src/soc/amd/phoenix/acpi/pci.asl   | 10 ++++++++++
 src/soc/amd/picasso/acpi/pci.asl   | 10 ++++++++++
 6 files changed, 50 insertions(+), 1 deletion(-)

diff --git a/src/soc/amd/cezanne/acpi/pci.asl b/src/soc/amd/cezanne/acpi/pci.asl
index d892da4d86..770a8701f6 100644
--- a/src/soc/amd/cezanne/acpi/pci.asl
+++ b/src/soc/amd/cezanne/acpi/pci.asl
@@ -7,6 +7,16 @@
  * Currently the name is hex representation of dev->path.pci.devfn.
  */
 
+/* Root complex */
+Device (GNB)
+{
+	Name (_ADR, 0)
+	Method (_STA, 0, NotSerialized)
+	{
+		Return (0x0F)
+	}
+}
+
 /* PCIe GPP */
 ACPI_PCI_DEV(GP09, 1, 1)
 ACPI_PCI_DEV(GP0A, 1, 2)
diff --git a/src/soc/amd/cezanne/root_complex.c b/src/soc/amd/cezanne/root_complex.c
index 15958dc0a8..81a99e55ec 100644
--- a/src/soc/amd/cezanne/root_complex.c
+++ b/src/soc/amd/cezanne/root_complex.c
@@ -93,7 +93,6 @@ static void root_complex_fill_ssdt(const struct device *device)
 	 *		}
 	 *	}
 	 */
-	acpi_device_write_pci_dev(device);
 	acpigen_write_scope(acpi_device_path(device));
 	struct opregion opreg = OPREGION("SMN", SYSTEMMEMORY,
 					 CONFIG_ECAM_MMCONF_BASE_ADDRESS + 0xb8, 0x8);
diff --git a/src/soc/amd/glinda/acpi/pci.asl b/src/soc/amd/glinda/acpi/pci.asl
index 0fabe961ad..ec5e33da88 100644
--- a/src/soc/amd/glinda/acpi/pci.asl
+++ b/src/soc/amd/glinda/acpi/pci.asl
@@ -7,6 +7,16 @@
  * Currently the name is hex representation of dev->path.pci.devfn.
  */
 
+/* Root complex */
+Device (GNB)
+{
+	Name (_ADR, 0)
+	Method (_STA, 0, NotSerialized)
+	{
+		Return (0x0F)
+	}
+}
+
 /* USB4.0 bridge */
 ACPI_PCI_DEV(GP09, 1, 1)
 ACPI_PCI_DEV(GP0A, 1, 2)
diff --git a/src/soc/amd/mendocino/acpi/pci.asl b/src/soc/amd/mendocino/acpi/pci.asl
index e1a239d3a2..774b4a8f67 100644
--- a/src/soc/amd/mendocino/acpi/pci.asl
+++ b/src/soc/amd/mendocino/acpi/pci.asl
@@ -7,6 +7,16 @@
  * Currently the name is hex representation of dev->path.pci.devfn.
  */
 
+/* Root complex */
+Device (GNB)
+{
+	Name (_ADR, 0)
+	Method (_STA, 0, NotSerialized)
+	{
+		Return (0x0F)
+	}
+}
+
 /* PCIe GPP */
 ACPI_PCI_DEV(GP11, 2, 1)
 ACPI_PCI_DEV(GP12, 2, 2)
diff --git a/src/soc/amd/phoenix/acpi/pci.asl b/src/soc/amd/phoenix/acpi/pci.asl
index c0a522246b..ae2c617381 100644
--- a/src/soc/amd/phoenix/acpi/pci.asl
+++ b/src/soc/amd/phoenix/acpi/pci.asl
@@ -7,6 +7,16 @@
  * Currently the name is hex representation of dev->path.pci.devfn.
  */
 
+/* Root complex */
+Device (GNB)
+{
+	Name (_ADR, 0)
+	Method (_STA, 0, NotSerialized)
+	{
+		Return (0x0F)
+	}
+}
+
 /* PCIe GPP */
 ACPI_PCI_DEV(GP09, 1, 1)
 ACPI_PCI_DEV(GP0A, 1, 2)
diff --git a/src/soc/amd/picasso/acpi/pci.asl b/src/soc/amd/picasso/acpi/pci.asl
index 539ef381be..4f119fe42d 100644
--- a/src/soc/amd/picasso/acpi/pci.asl
+++ b/src/soc/amd/picasso/acpi/pci.asl
@@ -7,6 +7,16 @@
  * Currently the name is hex representation of dev->path.pci.devfn.
  */
 
+/* Root complex */
+Device (GNB)
+{
+	Name (_ADR, 0)
+	Method (_STA, 0, NotSerialized)
+	{
+		Return (0x0F)
+	}
+}
+
 /* PCIe GPP */
 ACPI_PCI_DEV(GP09, 1, 1)
 ACPI_PCI_DEV(GP0A, 1, 2)

From 3b9fae176d9ef65be7f3baeec1f4ffda3b5a1bbb Mon Sep 17 00:00:00 2001
From: "Johann C. Rode" <jcrode@gmx.net>
Date: Wed, 11 Feb 2026 20:07:01 -0800
Subject: [PATCH 3350/3886] mb/lenovo/sklkbl/spd: Fix integer overflow

This fixes an integer overflow in the calculation of the offset within
the SPD binary that has caused memory detection failures on some
machines (e.g. this resolves https://ticket.coreboot.org/issues/627 ).
In a nutshell, spd_index (uint8_t) receives an assigned multiplication
by 512 (SPD_SIZE_MAX_DDR4) which will always truncate the result.

Change-Id: I048a73c18c9a3d1b20e2a4276e1714e59550eaf5
Signed-off-by: Johann C. Rode <jcrode@gmx.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91170
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/lenovo/sklkbl_thinkpad/spd/spd.c | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/spd/spd.c b/src/mainboard/lenovo/sklkbl_thinkpad/spd/spd.c
index 6ce18e5167..eaff251cc7 100644
--- a/src/mainboard/lenovo/sklkbl_thinkpad/spd/spd.c
+++ b/src/mainboard/lenovo/sklkbl_thinkpad/spd/spd.c
@@ -28,8 +28,7 @@ uint8_t *mainboard_find_spd_data(uint8_t spd_index)
 		die("Missing SPD data (spd.bin size %zu smaller than SPD size %u).", spd_file_len, SPD_SIZE_MAX_DDR4);
 
 	/* Assume same memory in both channels */
-	spd_index *= SPD_SIZE_MAX_DDR4;
-	spd_data = (uint8_t *)(spd_file + spd_index);
+	spd_data = (uint8_t *)(spd_file + spd_index * SPD_SIZE_MAX_DDR4);
 
 	/* Make sure a valid SPD was found */
 	if (spd_data[0] == 0)

From e18eb0a38b3056f1eba486de530ab321d8f553ff Mon Sep 17 00:00:00 2001
From: Patrick Rudolph <patrick.rudolph@9elements.com>
Date: Thu, 12 Feb 2026 07:51:02 +0100
Subject: [PATCH 3351/3886] mb/lenovo/sklkbl_thinkpad: Enable ACPI P-state
 table generation

Set eist_enable to true to call generate_p_state_entries() while writing
ACPI processor nodes to ACPI.

Resolves: https://ticket.coreboot.org/issues/623

Change-Id: Ic8965dddc0f50ac6dbd1b0af81af546aa53fbb58
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91173
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
---
 src/mainboard/lenovo/sklkbl_thinkpad/devicetree.cb | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/devicetree.cb b/src/mainboard/lenovo/sklkbl_thinkpad/devicetree.cb
index 5ec7750025..1ce50a0358 100644
--- a/src/mainboard/lenovo/sklkbl_thinkpad/devicetree.cb
+++ b/src/mainboard/lenovo/sklkbl_thinkpad/devicetree.cb
@@ -8,6 +8,8 @@ chip soc/intel/skylake
         register "PmConfigSlpSusMinAssert" = "3"        # 500ms
         register "PmConfigSlpAMinAssert" = "3"          # 2s
 
+	# Generate ACPI P-State table
+	register "eist_enable" = "true"
 	device domain 0 on
 		subsystemid 0x17aa 0x225d inherit
 		device ref igpu on

From 835b63980d113232b74b92bc7d1349d3e37d8747 Mon Sep 17 00:00:00 2001
From: Avi Uday <aviuday@google.com>
Date: Fri, 13 Feb 2026 18:31:39 +0530
Subject: [PATCH 3352/3886] soc/intel/pantherlake: Fix DDR5 channel mapping

This patch applies commit 0e7cf3d81d12 ("soc/intel/alderlake: Fix DDR5
channel mapping") to PantherLake.

DDR5 memory modules have two separate 32-bit channels (40-bit on ECC
memory modules), and the SPD info refers to one channel: the primary
bus width is 32 (or 40) bits and the "DIMM size" is halved. On Panther
Lake, there are 2 memory controllers with 4 32-bit channels each for
DDR5. FSP has 16 positions to store SPD data, some of which are only
used with LPDDR4/LPDDR5.

To try to make things less confusing, FSP abstracts the DDR5 channels
so that the configuration works like on DDR4. This is done by copying
each DIMM's SPD data to the other half-channel. Thus, fix the wrapper
parameters for DDR5 accordingly.

BUG=None
TEST=Build fatcat and verify there are no errors

Change-Id: I10226a2e04905040523d95ba8f5bc56f45606fe6
Signed-off-by: Avi Uday <aviuday@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91201
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Pranava Y N <pranavayn@google.com>
---
 src/soc/intel/pantherlake/meminit.c | 14 ++++++--------
 1 file changed, 6 insertions(+), 8 deletions(-)

diff --git a/src/soc/intel/pantherlake/meminit.c b/src/soc/intel/pantherlake/meminit.c
index eef4adf5f0..f9f8bac8da 100644
--- a/src/soc/intel/pantherlake/meminit.c
+++ b/src/soc/intel/pantherlake/meminit.c
@@ -35,18 +35,16 @@ static const struct soc_mem_cfg soc_mem_cfg[] = {
 		.num_phys_channels = DDR5_CHANNELS,
 		.phys_to_mrc_map = {
 			[0] = 0,
-			[1] = 1,
-			[2] = 4,
-			[3] = 5,
+			[1] = 4,
 		},
 		.md_phy_masks = {
 			/*
-			 * Physical channels 0 and 1 are populated in case of
-			 * half-populated configurations.
+			 * Only channel 0 is populated in case of half-populated
+			 * configuration.
 			 */
-			.half_channel = BIT(0) | BIT(1),
-			/* In mixed topology, channels 2 and 3 are always memory-down. */
-			.mixed_topo = BIT(2) | BIT(3),
+			.half_channel = BIT(0),
+			/* In mixed topologies, either channel 0 or 1 can be memory-down. */
+			.mixed_topo = BIT(0) | BIT(1),
 		},
 	},
 	[MEM_TYPE_LP5X] = {

From 42210fdb2849ecdeca29de875201cf92eb2462d0 Mon Sep 17 00:00:00 2001
From: Avi Uday <aviuday@google.com>
Date: Fri, 13 Feb 2026 18:39:20 +0530
Subject: [PATCH 3353/3886] soc/intel/pantherlake: Fill in SPD data on both
 channels of DDR5 memory
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Commit 91a1276d532b ("soc/intel/alderlake: Implement WA for DDR5 DIMM
modules") was added to allow FSP to perform the SPD read for DDR5
modules since coreboot did not properly support reading SPD from
EEPROM for DDR5. The same code is copied here for Pantherlake.

BUG=None
TEST=Build fatcat and verify there are no errors
Change-Id: Iacd43774c227fae5edc309dc1e163cc5c87160e4
Signed-off-by: Avi Uday <aviuday@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91202
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Reviewed-by: Pranava Y N <pranavayn@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/soc/intel/pantherlake/meminit.c | 31 +++++++++++++++++------------
 1 file changed, 18 insertions(+), 13 deletions(-)

diff --git a/src/soc/intel/pantherlake/meminit.c b/src/soc/intel/pantherlake/meminit.c
index f9f8bac8da..894ec30643 100644
--- a/src/soc/intel/pantherlake/meminit.c
+++ b/src/soc/intel/pantherlake/meminit.c
@@ -70,7 +70,8 @@ static const struct soc_mem_cfg soc_mem_cfg[] = {
 	},
 };
 
-static void mem_init_spd_upds(FSP_M_CONFIG *mem_cfg, const struct mem_channel_data *data)
+static void mem_init_spd_upds(FSP_M_CONFIG *mem_cfg, const struct mem_channel_data *data,
+				bool expand_channels)
 {
 	uint64_t *spd_upds[MRC_CHANNELS][CONFIG_DIMMS_PER_CHANNEL] = {
 		[0] = { &mem_cfg->MemorySpdPtr000, &mem_cfg->MemorySpdPtr001, },
@@ -103,7 +104,19 @@ static void mem_init_spd_upds(FSP_M_CONFIG *mem_cfg, const struct mem_channel_da
 		for (dimm = 0; dimm < CONFIG_DIMMS_PER_CHANNEL; dimm++) {
 			uint64_t *spd_ptr = spd_upds[ch][dimm];
 
-			*spd_ptr = data->spd[ch][dimm];
+			/*
+			 * In DDR5 systems, since each DIMM has 2 channels,
+			 * we need to copy the SPD data such that:
+			 * Channel 0 data is used by channel 0 and 1
+			 * Channel 2 data is used by channel 2 and 3
+			 * Channel 4 data is used by channel 4 and 5
+			 * Channel 6 data is used by channel 6 and 7
+			 */
+			if (expand_channels)
+				*spd_ptr = data->spd[ch & ~1][dimm];
+			else
+				*spd_ptr = data->spd[ch][dimm];
+
 			if (*spd_ptr)
 				enable_channel = 1;
 		}
@@ -184,6 +197,7 @@ void memcfg_init(FSPM_UPD *memupd, const struct mb_cfg *mb_cfg,
 {
 	struct mem_channel_data data;
 	bool dq_dqs_auto_detect = false;
+	bool expand_channels = false;
 	FSP_M_CONFIG *mem_cfg = &memupd->FspmConfig;
 
 	mem_cfg->ECT = mb_cfg->ect;
@@ -195,16 +209,7 @@ void memcfg_init(FSPM_UPD *memupd, const struct mb_cfg *mb_cfg,
 		printk(BIOS_DEBUG, "%s: module type is DDR5\n", __func__);
 		meminit_ddr(mem_cfg, &mb_cfg->ddr_config);
 		dq_dqs_auto_detect = true;
-		/*
-		 * TODO: Drop this workaround once SMBus driver in coreboot is
-		 * updated to support DDR5 EEPROM reading.
-		 */
-		if (spd_info->topo == MEM_TOPO_DIMM_MODULE) {
-			fill_dimm_module_info(mem_cfg, mb_cfg, spd_info);
-			mem_init_dq_upds(mem_cfg, NULL, mb_cfg, true);
-			mem_init_dqs_upds(mem_cfg, NULL, mb_cfg, true);
-			return;
-		}
+		expand_channels = true;
 		break;
 	case MEM_TYPE_LP5X:
 		meminit_lp5x(mem_cfg, &mb_cfg->lp5x_config);
@@ -218,7 +223,7 @@ void memcfg_init(FSPM_UPD *memupd, const struct mb_cfg *mb_cfg,
 
 	mem_populate_channel_data(memupd, &soc_mem_cfg[mb_cfg->type], spd_info,
 				  half_populated, &data);
-	mem_init_spd_upds(mem_cfg, &data);
+	mem_init_spd_upds(mem_cfg, &data, expand_channels);
 	mem_init_dq_upds(mem_cfg, &data, mb_cfg, dq_dqs_auto_detect);
 	mem_init_dqs_upds(mem_cfg, &data, mb_cfg, dq_dqs_auto_detect);
 }

From e21093b0558058f22f89139e8cd3cee8b8981707 Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Mon, 16 Feb 2026 10:18:01 +0000
Subject: [PATCH 3354/3886] mb/starlabs/byte_adl: Disable DMIC NID

This board does not have a DMIC, so update the verb table to
reflect that.

Change-Id: Idd38dc016d7d178002f291ac8a0088e5f7b7490d
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91287
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
---
 src/mainboard/starlabs/byte_adl/variants/mk_ii/hda_verb.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/mainboard/starlabs/byte_adl/variants/mk_ii/hda_verb.c b/src/mainboard/starlabs/byte_adl/variants/mk_ii/hda_verb.c
index 9b87198c4a..203d5c1961 100644
--- a/src/mainboard/starlabs/byte_adl/variants/mk_ii/hda_verb.c
+++ b/src/mainboard/starlabs/byte_adl/variants/mk_ii/hda_verb.c
@@ -59,7 +59,7 @@ const uint32_t cim_verb_data[] = {
 
 	AZALIA_PIN_CFG(0, 0x16, 0x04214040),
 	AZALIA_PIN_CFG(0, 0x18, 0x40f001f0),
-	AZALIA_PIN_CFG(0, 0x1a,	0x90a72150),
+	AZALIA_PIN_CFG(0, 0x1a,	AZALIA_PIN_CFG_NC(0)),
 	AZALIA_PIN_CFG(0, 0x19, 0x04a19020),
 	AZALIA_PIN_CFG(0, 0x1d,	0x00000000),
 	AZALIA_PIN_CFG(0, 0x1e, 0x00000000),

From 392529ebb2acbdd8e92f6ab57c79a46c185b1f3c Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Fri, 13 Feb 2026 12:46:16 -0600
Subject: [PATCH 3355/3886] mb/starlabs/starbook/tgl: Correct GPIO reset for
 GPP_C6/C7

Eliminates errors in cbmem log:
[ERROR]  gpio_pad_reset_config_override: Logical to Chipset mapping
         not found

Change-Id: I562e63365599a2dc62526f5789b7c6c79318cb9e
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91298
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
---
 src/mainboard/starlabs/starbook/variants/tgl/gpio.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/mainboard/starlabs/starbook/variants/tgl/gpio.c b/src/mainboard/starlabs/starbook/variants/tgl/gpio.c
index 448683ce28..0bf5afba78 100644
--- a/src/mainboard/starlabs/starbook/variants/tgl/gpio.c
+++ b/src/mainboard/starlabs/starbook/variants/tgl/gpio.c
@@ -61,8 +61,8 @@ const struct pad_config gpio_table[] = {
 	PAD_CFG_NF(GPP_H16, NONE, DEEP, NF1),				/* HDMI Clock */
 	PAD_CFG_NF(GPP_H17, NONE, DEEP, NF1),				/* HDMI Data */
 	PAD_CFG_NF(GPP_B11, NONE, DEEP, NF1),				/* PMC Interrupt */
-	PAD_CFG_NF(GPP_C6, NONE, PWROK, NF1),				/* SML Clock */
-	PAD_CFG_NF(GPP_C7, NONE, PWROK, NF1),				/* SML Data */
+	PAD_CFG_NF(GPP_C6, NONE, DEEP, NF1),				/* SML Clock */
+	PAD_CFG_NF(GPP_C7, NONE, DEEP, NF1),				/* SML Data */
 
 	/* Webcam */
 	PAD_CFG_TERM_GPO(GPP_D19, 1, UP_20K, DEEP),			/* Power */

From 44b2510db1065eb41ac28065f0f731441a7f045e Mon Sep 17 00:00:00 2001
From: Patrick Rudolph <patrick.rudolph@9elements.com>
Date: Wed, 11 Feb 2026 11:22:52 +0100
Subject: [PATCH 3356/3886] soc/amd/common/block/acp/acp: Drop
 acpi_device_write_pci_dev

Move the ACP ACPI device called ACPD from SSDT to DSDT so that a SoC
or a mainboard DSDT can extend the ACP configuration.
Therefore, drop acpi_device_write_pci_dev() in SSDT. Introduce a STAT
variable in ASL, which defaults to 3 (present, enabled, hidden, not ok)
when the device is set to "off" in the devicetree.cb, since the PCI
device is not actual disabled by FSP. When not disabled in devicetree.cb,
STAT will be overriden in SSDT with the actual device status. The STAT
variable is returned by _STA method.

The ACP child devices where seen on Phoenix and KrackenPoint and not
seen on Rembrandt, Cezanne or Mendocino.
Assume older platforms do not have ACP child devices in ACPI.

TEST=Booted on AMD birman_plus (glinda) and verified ACP is working.
TEST=Set ACP device to off and verified it's marked hidden on Windows 11
     Device Manager.

Change-Id: I31c3f01f83f27d0121f9e003e60a7f12d49427f6
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91157
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
---
 src/soc/amd/cezanne/acpi/acp.asl   | 14 +++++++++
 src/soc/amd/cezanne/acpi/soc.asl   |  2 ++
 src/soc/amd/common/block/acp/acp.c | 17 +++++++---
 src/soc/amd/glinda/acpi/acp.asl    | 50 ++++++++++++++++++++++++++++++
 src/soc/amd/glinda/acpi/soc.asl    |  3 ++
 src/soc/amd/mendocino/acpi/acp.asl | 14 +++++++++
 src/soc/amd/mendocino/acpi/soc.asl |  3 ++
 src/soc/amd/phoenix/acpi/acp.asl   | 50 ++++++++++++++++++++++++++++++
 src/soc/amd/phoenix/acpi/soc.asl   |  3 ++
 src/soc/amd/picasso/acpi/acp.asl   | 14 +++++++++
 src/soc/amd/picasso/acpi/soc.asl   |  2 ++
 11 files changed, 167 insertions(+), 5 deletions(-)
 create mode 100644 src/soc/amd/cezanne/acpi/acp.asl
 create mode 100644 src/soc/amd/glinda/acpi/acp.asl
 create mode 100644 src/soc/amd/mendocino/acpi/acp.asl
 create mode 100644 src/soc/amd/phoenix/acpi/acp.asl
 create mode 100644 src/soc/amd/picasso/acpi/acp.asl

diff --git a/src/soc/amd/cezanne/acpi/acp.asl b/src/soc/amd/cezanne/acpi/acp.asl
new file mode 100644
index 0000000000..184fe15704
--- /dev/null
+++ b/src/soc/amd/cezanne/acpi/acp.asl
@@ -0,0 +1,14 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/* ACP Audio Configuration */
+Scope (\_SB.PCI0.GP41) {
+	Device (ACPD) {
+		/* Device addressing for ACP (Audio Coprocessor) */
+		Name (_ADR, 0x05)  /* Device 0, Function 5 */
+
+		Name (STAT, 0x3) /* Decoding Resources, Hide from UI */
+		Method (_STA, 0x0, NotSerialized)
+		{
+			Return (STAT)
+		}
+	}
+}
diff --git a/src/soc/amd/cezanne/acpi/soc.asl b/src/soc/amd/cezanne/acpi/soc.asl
index 2d9d1dfb18..5749ff80b4 100644
--- a/src/soc/amd/cezanne/acpi/soc.asl
+++ b/src/soc/amd/cezanne/acpi/soc.asl
@@ -24,6 +24,8 @@ Scope(\_SB) {
 
 		#include "pci.asl"
 	} /* End PCI0 scope */
+
+	#include "acp.asl"
 } /* End \_SB scope */
 
 #include <soc/amd/common/acpi/alib.asl>
diff --git a/src/soc/amd/common/block/acp/acp.c b/src/soc/amd/common/block/acp/acp.c
index 4985980bf5..877dd9c153 100644
--- a/src/soc/amd/common/block/acp/acp.c
+++ b/src/soc/amd/common/block/acp/acp.c
@@ -22,23 +22,30 @@ static const char *acp_acpi_name(const struct device *dev)
 static void acp_fill_wov_method(const struct device *dev)
 {
 	const struct soc_amd_common_config *cfg = soc_get_common_config();
-	const char *scope = acpi_device_path(dev);
 
-	if (!cfg->acp_config.dmic_present || !scope)
+	if (!cfg->acp_config.dmic_present)
 		return;
 
 	/* For ACP DMIC hardware runtime detection on the platform, _WOV method is populated. */
-	acpigen_write_scope(scope); /* Scope */
 	acpigen_write_method("_WOV", 0);
 	acpigen_write_return_integer(1);
 	acpigen_write_method_end();
-	acpigen_write_scope_end();
 }
 
 static void acp_fill_ssdt(const struct device *dev)
 {
-	acpi_device_write_pci_dev(dev);
+	const char *scope = acpi_device_path(dev);
+	assert(scope);
+	if (!scope)
+		return;
+
+	acpigen_write_scope(scope);
+
+	acpigen_write_store_int_to_namestr(acpi_device_status(dev), "STAT");
 	acp_fill_wov_method(dev);
+
+	acpigen_pop_len(); /* Scope */
+
 	if (CONFIG(SOC_AMD_COMMON_BLOCK_ACP_SOC_SPECIFIC_SSDT_ENTRY))
 		acp_soc_write_ssdt_entry(dev);
 }
diff --git a/src/soc/amd/glinda/acpi/acp.asl b/src/soc/amd/glinda/acpi/acp.asl
new file mode 100644
index 0000000000..0e3dd5a055
--- /dev/null
+++ b/src/soc/amd/glinda/acpi/acp.asl
@@ -0,0 +1,50 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/* ACP Audio Configuration */
+Scope (\_SB.PCI0.GP41) {
+	Device (ACPD) {
+		/* Device addressing for ACP (Audio Coprocessor) */
+		Name (_ADR, 0x05)  /* Device 0, Function 5 */
+
+		Name (STAT, 0x3) /* Decoding Resources, Hide from UI */
+		Method (_STA, 0x0, NotSerialized)
+		{
+			Return (STAT)
+		}
+
+		/* Child Devices - Audio endpoints */
+		Device (HDA0)   /* HDA0 - HD Audio */
+		{
+			Name (_ADR, 0x01)
+		}
+
+		Device (PDMC)   /* PDM Controller */
+		{
+			Name (_ADR, 0x02)
+		}
+
+		Device (I2SC)   /* I2S Controller */
+		{
+			Name (_ADR, 0x03)
+		}
+
+		Device (BTSC)   /* BT Sideband Controller */
+		{
+			Name (_ADR, 0x04)
+		}
+
+		Device (SDWC)   /* SoundWire Controller */
+		{
+			Name (_ADR, 0x05)
+		}
+
+		Device(SDWS)	/* SoundWire Streaming */
+		{
+			Name (_ADR, 0x06)
+		}
+
+		Device(USBS)	/* USB Sideband */
+		{
+			Name (_ADR, 0x07)
+		}
+	}
+}
diff --git a/src/soc/amd/glinda/acpi/soc.asl b/src/soc/amd/glinda/acpi/soc.asl
index 1daf153a4a..82d5587751 100644
--- a/src/soc/amd/glinda/acpi/soc.asl
+++ b/src/soc/amd/glinda/acpi/soc.asl
@@ -26,6 +26,9 @@ Scope(\_SB) {
 
 		#include "pci.asl"
 	} /* End PCI0 scope */
+
+	#include "acp.asl"
+
 } /* End \_SB scope */
 
 #include <soc/amd/common/acpi/alib.asl>
diff --git a/src/soc/amd/mendocino/acpi/acp.asl b/src/soc/amd/mendocino/acpi/acp.asl
new file mode 100644
index 0000000000..184fe15704
--- /dev/null
+++ b/src/soc/amd/mendocino/acpi/acp.asl
@@ -0,0 +1,14 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/* ACP Audio Configuration */
+Scope (\_SB.PCI0.GP41) {
+	Device (ACPD) {
+		/* Device addressing for ACP (Audio Coprocessor) */
+		Name (_ADR, 0x05)  /* Device 0, Function 5 */
+
+		Name (STAT, 0x3) /* Decoding Resources, Hide from UI */
+		Method (_STA, 0x0, NotSerialized)
+		{
+			Return (STAT)
+		}
+	}
+}
diff --git a/src/soc/amd/mendocino/acpi/soc.asl b/src/soc/amd/mendocino/acpi/soc.asl
index 417370fe82..8b78e4ec95 100644
--- a/src/soc/amd/mendocino/acpi/soc.asl
+++ b/src/soc/amd/mendocino/acpi/soc.asl
@@ -26,6 +26,9 @@ Scope(\_SB) {
 
 		#include "pci.asl"
 	} /* End PCI0 scope */
+
+	#include "acp.asl"
+
 } /* End \_SB scope */
 
 #include <soc/amd/common/acpi/alib.asl>
diff --git a/src/soc/amd/phoenix/acpi/acp.asl b/src/soc/amd/phoenix/acpi/acp.asl
new file mode 100644
index 0000000000..2b6a5e876b
--- /dev/null
+++ b/src/soc/amd/phoenix/acpi/acp.asl
@@ -0,0 +1,50 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/* ACP Audio Configuration */
+Scope (\_SB.PCI0.GP41) {
+	Device (ACPD) {
+		/* Device addressing for ACP (Audio Coprocessor) */
+		Name (_ADR, 0x05)  /* Device 0, Function 5 */
+
+		Name (STAT, 0x3) /* Decoding Resources, Hide from UI */
+		Method (_STA, 0x0, NotSerialized)
+		{
+			Return (STAT)
+		}
+
+		/* Child Devices - Audio endpoints */
+		Device (HDA0)   /* HDA0 - HD Audio */
+		{
+			Name (_ADR, 0x01)
+		}
+
+		Device (PDMC)   /* PDM Controller */
+		{
+			Name (_ADR, 0x02)
+		}
+
+		Device (I2SC)   /* I2S Controller */
+		{
+			Name (_ADR, 0x03)
+		}
+
+		Device (BTSC)   /* BT Sideband Controller */
+		{
+			Name (_ADR, 0x04)
+		}
+
+		Device (SDWC)   /* SoundWire Controller */
+		{
+			Name (_ADR, 0x05)
+		}
+
+		Device (SDWS)	/* SoundWire Streaming */
+		{
+			Name (_ADR, 0x06)
+		}
+
+		Device (USBS)	/* USB Sideband */
+		{
+			Name (_ADR, 0x07)
+		}
+	}
+}
diff --git a/src/soc/amd/phoenix/acpi/soc.asl b/src/soc/amd/phoenix/acpi/soc.asl
index 997c819bd6..fcd41c34e9 100644
--- a/src/soc/amd/phoenix/acpi/soc.asl
+++ b/src/soc/amd/phoenix/acpi/soc.asl
@@ -26,6 +26,9 @@ Scope(\_SB) {
 
 		#include "pci.asl"
 	} /* End PCI0 scope */
+
+	#include "acp.asl"
+
 } /* End \_SB scope */
 
 #include <soc/amd/common/acpi/alib.asl>
diff --git a/src/soc/amd/picasso/acpi/acp.asl b/src/soc/amd/picasso/acpi/acp.asl
new file mode 100644
index 0000000000..184fe15704
--- /dev/null
+++ b/src/soc/amd/picasso/acpi/acp.asl
@@ -0,0 +1,14 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/* ACP Audio Configuration */
+Scope (\_SB.PCI0.GP41) {
+	Device (ACPD) {
+		/* Device addressing for ACP (Audio Coprocessor) */
+		Name (_ADR, 0x05)  /* Device 0, Function 5 */
+
+		Name (STAT, 0x3) /* Decoding Resources, Hide from UI */
+		Method (_STA, 0x0, NotSerialized)
+		{
+			Return (STAT)
+		}
+	}
+}
diff --git a/src/soc/amd/picasso/acpi/soc.asl b/src/soc/amd/picasso/acpi/soc.asl
index deedd5dd5a..67eb3f5749 100644
--- a/src/soc/amd/picasso/acpi/soc.asl
+++ b/src/soc/amd/picasso/acpi/soc.asl
@@ -38,6 +38,8 @@ Scope(\_SB) { /* Start \_SB scope */
 	/* Describe the MMIO devices in the FCH */
 	#include "mmio.asl"
 
+	#include "acp.asl"
+
 	/* Add GPIO library */
 	#include <soc/amd/common/acpi/gpio_bank_lib.asl>
 

From 8c56a9c53e050ae4ef3bc01ff8f02b0d69aa23f8 Mon Sep 17 00:00:00 2001
From: Patrick Rudolph <patrick.rudolph@9elements.com>
Date: Wed, 11 Feb 2026 11:25:05 +0100
Subject: [PATCH 3357/3886] mb/amd/birman_plus: Fix ACP Windows driver

The Windows 11 ACP driver depends on the ACPI _DSD method, thus
add the data based on the UEFI implementation.

TEST=Windows 11 ACP driver reports no issues any more.

Change-Id: I3e193ee0dbf736aab9f7d21927a01992e2f84973
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91158
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
---
 src/mainboard/amd/birman_plus/acpi/acp.asl | 243 +++++++++++++++++++++
 src/mainboard/amd/birman_plus/dsdt.asl     |   1 +
 2 files changed, 244 insertions(+)
 create mode 100644 src/mainboard/amd/birman_plus/acpi/acp.asl

diff --git a/src/mainboard/amd/birman_plus/acpi/acp.asl b/src/mainboard/amd/birman_plus/acpi/acp.asl
new file mode 100644
index 0000000000..6de8190112
--- /dev/null
+++ b/src/mainboard/amd/birman_plus/acpi/acp.asl
@@ -0,0 +1,243 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+/* ACP Audio Configuration */
+Scope (\_SB.PCI0.GP41.ACPD) {
+
+	/* Global Configuration - _DSD properties for ACP device */
+	Name (_DSD, Package (0x02)
+	{
+		ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+		Package (0x02)
+		{
+			Package (0x02) {"acp-audio-zsc-enable", 0x01},
+			Package (0x02) {"acp-audio-config-flag", 0x10}
+		}
+	})
+}
+Scope (\_SB.PCI0.GP41.ACPD.HDA0) {
+	Name (_DSD, Package ()
+	{
+		ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+		Package ()
+		{
+			Package (2) {"acp-audio-device-interface-version",0x01},
+			Package (2) {"acp-audio-device-type",0x01}
+		},
+
+		ToUUID ("dbb8e3e6-5886-4ba6-8795-1319f52a966b"),
+		Package ()
+		{
+			Package (0x02) {"acp-audio-device-eps",
+			Package () { "PE00","PE01"}
+			}
+		}
+	})
+	Name (PE00, Package ()
+	{
+		ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+		Package ()
+		{
+			Package (0x02) {"acp-audio-ep-type", 0x0 },
+			Package (0x02) {"acp-audio-ep-dsp-offload-supported",0x1},
+			Package (0x02) {"acp-audio-ep-category", 0x1}
+		},
+
+		ToUUID ("dbb8e3e6-5886-4ba6-8795-1319f52a966b"),
+		Package ()
+		{
+			Package (0x02){"acp-audio-ep-format", "FMTS"},
+			Package (0x02){"acp-audio-ep-apo-fx-type-ex", "EFXS"}
+		}
+	})
+	Name (PE01, Package ()
+	{
+		ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+		Package ()
+		{
+			Package (0x02){"acp-audio-ep-type", 0x0},
+			Package (0x02){"acp-audio-ep-dsp-offload-supported", 0x1},
+			Package (0x02){"acp-audio-ep-category", 0x2}
+		},
+
+		ToUUID ("dbb8e3e6-5886-4ba6-8795-1319f52a966b"),
+		Package ()
+		{
+			Package (0x02){"acp-audio-ep-format", "FMTH"},
+			Package (0x02){"acp-audio-ep-apo-fx-type-ex","EFXH"}
+		}
+	})
+	Name (FMTS, Package ()
+		{
+		ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+		Package ()
+		{
+			Package (0x02){"acp-audio-ep-format-max-channels", 0x02},
+			Package (0x02){"acp-audio-ep-format-sampling-frequency",
+			Package (){ 48000,96000}
+			},
+			Package (0x02){"acp-audio-ep-format-bits-per-sample",
+			Package (){16,24}
+			}
+		}
+	})
+	Name (FMTH, Package ()
+	{
+		ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+		Package ()
+		{
+			Package (0x02){"acp-audio-ep-format-max-channels", 0x02},
+			Package (0x02){"acp-audio-ep-format-sampling-frequency",
+			Package (){ 48000,96000}
+			},
+			Package (0x02){"acp-audio-ep-format-bits-per-sample",
+			Package (){16,24}
+			}
+		}
+	})
+	Name (EFXS, Package ()
+	{
+		ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+		Package ()
+		{
+			Package (0x02){"{05714B44-A61C-40F0-9F72-3A2EFF40D74C}", "{00000000-0000-0000-0000-000000000000}"},
+			Package (0x02){"{591689D6-7499-4444-BFDE-BA2BE1D9A5D6}", "{00000000-0000-0000-0000-000000000000}"},
+			Package (0x02){"{E5E0FB95-F997-4EB4-9580-35A81438FE5B}", "{00000000-0000-0000-0000-000000000000}"}
+		}
+		})
+		Name (EFXH, Package ()
+		{
+		ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+		Package ()
+		{
+			Package (0x02){"{591689D6-7499-4444-BFDE-BA2BE1D9A5D6}", "{00000000-0000-0000-0000-000000000000}"},
+			Package (0x02){"{E5E0FB95-F997-4EB4-9580-35A81438FE5B}", "{00000000-0000-0000-0000-000000000000}"}
+		}
+	})
+}
+Scope (\_SB.PCI0.GP41.ACPD.BTSC) {
+	Name (_DSD, Package ()
+	{
+		ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+		Package ()
+		{
+			Package (2) {"acp-audio-device-interface-version",0x01},
+			Package (2) {"acp-audio-device-type",0x04}
+		},
+
+		ToUUID ("dbb8e3e6-5886-4ba6-8795-1319f52a966b"),
+		Package ()
+		{
+			Package (0x02) {"acp-audio-device-eps",
+			Package () { "PE00","CE00"}
+			}
+		}
+	})
+	Name (PE00, Package ()
+	{
+		ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+		Package ()
+		{
+			Package (0x02) {"acp-audio-ep-type", 0x0 },
+			Package (0x02) {"acp-audio-ep-dsp-offload-supported",0x1},
+			Package (0x02) {"acp-audio-ep-category", 0x1},
+			Package (0x02) {"acp-audio-ep-port", 0x3},
+			Package (0x02) {"acp-audio-ep-node", 0x2},
+			Package (0x02) {"acp-audio-ep-capabilities",
+			Package (){ 0x1, 0x2, 0x4, 0x8}}
+		},
+
+		ToUUID ("dbb8e3e6-5886-4ba6-8795-1319f52a966b"),
+		Package ()
+		{
+			Package (0x02){"acp-audio-ep-format", "FMT0"},
+			Package (0x02){"acp-audio-ep-apo-fx-type", "EFX0"},
+			Package (0x02){"acp-audio-ep-apo-fx-type-ex","EFX1"}
+		}
+	})
+	Name (FMT0, Package ()
+	{
+		ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+		Package ()
+		{
+			Package (0x02){"acp-audio-ep-format-max-channels", 0x02},
+			Package (0x02){"acp-audio-ep-format-sampling-frequency",
+			Package (){ 8000,16000, 48000}},
+			Package (0x02){"acp-audio-ep-format-bits-per-sample",
+			Package (){16}}
+		}
+	})
+	Name (EFX0, Package ()
+	{
+		ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+		Package ()
+		{
+			Package (0x02){"acp-audio-ep-apo-efx-type", 0x0},
+			Package (0x02){"acp-audio-ep-apo-mfx-type", 0x0},
+			Package (0x02){"acp-audio-ep-apo-sfx-type", 0x0},
+			Package (0x02){"acp-audio-ep-apo-efx-encoder-type", 0x100}
+		}
+	})
+	Name (EFX1, Package ()
+	{
+		ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+		Package ()
+		{
+			Package (0x02){"{591689D6-7499-4444-BFDE-BA2BE1D9A5D6}", "{00000000-0000-0000-0000-000000000000}"},
+			Package (0x02){"{E5E0FB95-F997-4EB4-9580-35A81438FE5B}", "{00000000-0000-0000-0000-000000000000}"},
+			Package (0x02){"{09DF37AE-0217-4601-A842-DEC90EEBC68F}", "{66E5A40D-4559-4019-B0F1-5F842C7E461A}"},
+		}
+	})
+	Name (CE00, Package ()
+	{
+		ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+		Package ()
+		{
+			Package (0x02) {"acp-audio-ep-type", 0x1 },
+			Package (0x02) {"acp-audio-ep-dsp-offload-supported",0x1},
+			Package (0x02) {"acp-audio-ep-ai-noise-reduction-supported", 0x0},
+			Package (0x02) {"acp-audio-ep-port", 0x3},
+			Package (0x02) {"acp-audio-ep-node", 0x2}
+		},
+
+		ToUUID ("dbb8e3e6-5886-4ba6-8795-1319f52a966b"),
+		Package ()
+		{
+			Package (0x02){"acp-audio-ep-format", "FMT1"},
+			Package (0x02){"acp-audio-ep-apo-fx-type", "EFX2"},
+			Package (0x02){"acp-audio-ep-apo-fx-type-ex","EFX3"}
+		}
+	})
+	Name (FMT1, Package ()
+	{
+		ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+		Package ()
+		{
+			Package (0x02){"acp-audio-ep-format-max-channels", 0x02},
+			Package (0x02){"acp-audio-ep-format-sampling-frequency",
+			Package (){ 8000,16000}},
+			Package (0x02){"acp-audio-ep-format-bits-per-sample",
+			Package (){16}}
+		}
+	})
+	Name (EFX2, Package ()
+	{
+		ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+		Package ()
+		{
+			Package (0x02){"acp-audio-ep-apo-efx-type", 0x0},
+			Package (0x02){"acp-audio-ep-apo-mfx-type", 0x0},
+			Package (0x02){"acp-audio-ep-apo-sfx-type", 0x0},
+			Package (0x02){"acp-audio-ep-apo-efx-encoder-type", 0x100}
+		}
+	})
+	Name (EFX3, Package ()
+	{
+		ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+		Package ()
+		{
+			Package (0x02){"{65E94A28-DE71-4154-AD49-F67C7831EA4D}", "{00000000-0000-0000-0000-000000000000}"},
+			Package (0x02){"{E5B78E46-DAA2-4827-8D84-F6C0C0306541}", "{00000000-0000-0000-0000-000000000000}"},
+			Package (0x02){"{09DF37AE-0217-4601-A842-DEC90EEBC68F}", "{66E5A40D-4559-4019-B0F1-5F842C7E461A}"}
+		}
+	})
+}
diff --git a/src/mainboard/amd/birman_plus/dsdt.asl b/src/mainboard/amd/birman_plus/dsdt.asl
index 7b8982a645..751b9fb9ca 100644
--- a/src/mainboard/amd/birman_plus/dsdt.asl
+++ b/src/mainboard/amd/birman_plus/dsdt.asl
@@ -13,4 +13,5 @@ DefinitionBlock (
 	#include <acpi/dsdt_top.asl>
 
 	#include <soc.asl>
+	#include "acpi/acp.asl"
 }

From 4e61dd36e4f1389ed7a8e10a2b03bf989a462df0 Mon Sep 17 00:00:00 2001
From: Patrick Rudolph <patrick.rudolph@9elements.com>
Date: Wed, 11 Feb 2026 11:57:07 +0100
Subject: [PATCH 3358/3886] soc/amd/cezanne: Move SSDT code into DSDT

Now that the ACP device is always present in DSDT move the
MSG0 method and helper functions into DSDT. This allows to clean
the common ACP code and reduces differences in the runtime code
pathes. The newly introduced DSDT is also verified at compile time.

Change-Id: Ifc55278aa66abcb54691017738cc843e3088d8e8
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91159
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/soc/amd/cezanne/Kconfig                   |   1 -
 src/soc/amd/cezanne/acpi.c                    | 223 ------------------
 src/soc/amd/cezanne/acpi/acp.asl              |  79 +++++++
 src/soc/amd/common/block/acp/Kconfig          |   6 -
 src/soc/amd/common/block/acp/acp.c            |   3 -
 .../amd/common/block/include/amdblocks/acp.h  |   2 -
 6 files changed, 79 insertions(+), 235 deletions(-)

diff --git a/src/soc/amd/cezanne/Kconfig b/src/soc/amd/cezanne/Kconfig
index 26d3f3e4a8..dacd542c8e 100644
--- a/src/soc/amd/cezanne/Kconfig
+++ b/src/soc/amd/cezanne/Kconfig
@@ -26,7 +26,6 @@ config SOC_AMD_CEZANNE_BASE
 	select RTC
 	select SOC_AMD_COMMON
 	select SOC_AMD_COMMON_BLOCK_ACP_GEN1
-	select SOC_AMD_COMMON_BLOCK_ACP_SOC_SPECIFIC_SSDT_ENTRY
 	select SOC_AMD_COMMON_BLOCK_ACPI
 	select SOC_AMD_COMMON_BLOCK_ACPIMMIO
 	select SOC_AMD_COMMON_BLOCK_ACPIMMIO_PM_IO_ACCESS
diff --git a/src/soc/amd/cezanne/acpi.c b/src/soc/amd/cezanne/acpi.c
index b54b88b2e8..6d7bbefe19 100644
--- a/src/soc/amd/cezanne/acpi.c
+++ b/src/soc/amd/cezanne/acpi.c
@@ -92,226 +92,3 @@ const acpi_cstate_t *get_cstate_config_data(size_t *size)
 	*size = ARRAY_SIZE(cstate_cfg_table);
 	return cstate_cfg_table;
 }
-
-static void acp_soc_write_smn_access_methods(void)
-{
-	acpigen_write_method_serialized("SMNR", 1);
-	acpigen_write_store_op_to_namestr(ARG0_OP, "\\_SB.PCI0.GNB.SMNA");
-	acpigen_write_return_namestr("\\_SB.PCI0.GNB.SMND");
-	acpigen_write_method_end();
-
-	acpigen_write_method_serialized("SMNW", 2);
-	acpigen_write_store_op_to_namestr(ARG0_OP, "\\_SB.PCI0.GNB.SMNA");
-	acpigen_write_store_op_to_namestr(ARG1_OP, "\\_SB.PCI0.GNB.SMND");
-	acpigen_write_method_end();
-}
-
-/* write value of ACPI variable into SMN register */
-static void acp_soc_write_smn_register_write(uint8_t op, uint32_t smn_address)
-{
-	acpigen_emit_namestring("^SMNW");
-	acpigen_write_integer(smn_address);
-	acpigen_emit_byte(op);
-}
-
-/* read SMN register and store value into ACPI variable */
-static void acp_soc_write_smn_register_read(uint32_t smn_address, uint8_t op)
-{
-	acpigen_write_store();
-	acpigen_emit_namestring("^SMNR");
-	acpigen_write_integer(smn_address);
-	acpigen_emit_byte(op);
-}
-
-static void acp_soc_write_mailbox_access(void)
-{
-	acp_soc_write_smn_register_write(ARG0_OP, 0x00058A74);
-	acp_soc_write_smn_register_write(ARG1_OP, 0x00058A54);
-	acp_soc_write_smn_register_write(ARG2_OP, 0x00058A14);
-	acp_soc_write_smn_register_read(0x00058A74, LOCAL0_OP);
-
-	/* While (LEqual (Local0, 0)) */
-	acpigen_emit_byte(WHILE_OP);
-	acpigen_write_len_f();
-	acpigen_emit_byte(LEQUAL_OP);
-	acpigen_emit_byte(LOCAL0_OP);
-	acpigen_emit_byte(ZERO_OP);
-
-	acp_soc_write_smn_register_read(0x00058A74, LOCAL0_OP);
-
-	acpigen_pop_len(); /* While */
-
-	acp_soc_write_smn_register_read(0x00058A54, LOCAL1_OP);
-
-	acpigen_write_return_op(LOCAL1_OP);
-}
-
-static void acp_soc_write_psp_mbox_buffer_field(void)
-{
-	acpigen_write_name("MBOX");
-	acpigen_write_byte_buffer(NULL, 4);
-	acpigen_write_create_buffer_word_field("MBOX", 0, "STAT");
-	acpigen_write_create_buffer_byte_field("MBOX", 2, "CMDI");
-	acpigen_write_create_buffer_bit_field("MBOX", 31, "REDY");
-}
-
-static void acp_soc_write_psp_read_mbox_from_hw(void)
-{
-	acp_soc_write_smn_register_read(0x03810570, LOCAL0_OP);
-	acpigen_write_store_op_to_namestr(LOCAL0_OP, "MBOX");
-}
-
-static void acp_soc_write_psp_write_mbox_to_hw(void)
-{
-	acpigen_write_store_namestr_to_op("MBOX", LOCAL0_OP);
-	acp_soc_write_smn_register_write(LOCAL0_OP, 0x03810570);
-}
-
-static void acp_soc_write_psp_mailbox_access(void)
-{
-
-	acp_soc_write_psp_mbox_buffer_field();
-
-	acp_soc_write_psp_read_mbox_from_hw();
-
-	/* While (LOr (LNotEqual (REDY, 0x1), LNotEqual (CMDI, 0x00))) */
-	acpigen_emit_byte(WHILE_OP);
-	acpigen_write_len_f();
-	acpigen_emit_byte(LOR_OP);
-	acpigen_emit_byte(LNOT_OP);
-	acpigen_emit_byte(LEQUAL_OP);
-	acpigen_emit_namestring("REDY");
-	acpigen_write_integer(1);
-	acpigen_emit_byte(LNOT_OP);
-	acpigen_emit_byte(LEQUAL_OP);
-	acpigen_emit_namestring("CMDI");
-	acpigen_write_integer(0);
-
-	acp_soc_write_psp_read_mbox_from_hw();
-
-	acpigen_pop_len(); /* While */
-
-	acpigen_write_store_int_to_op(0, LOCAL0_OP);
-	acpigen_write_store_op_to_namestr(LOCAL0_OP, "MBOX");
-	acpigen_write_store_int_to_namestr(0x33, "CMDI");
-
-	acp_soc_write_psp_write_mbox_to_hw();
-
-	acpigen_write_sleep(1);
-
-	acp_soc_write_psp_read_mbox_from_hw();
-
-	/* While (LNotEqual (CMDI, 0x00)) */
-	acpigen_emit_byte(WHILE_OP);
-	acpigen_write_len_f();
-	acpigen_emit_byte(LNOT_OP);
-	acpigen_emit_byte(LEQUAL_OP);
-	acpigen_emit_namestring("CMDI");
-	acpigen_write_integer(0);
-
-	acp_soc_write_psp_read_mbox_from_hw();
-
-	acpigen_pop_len(); /* While */
-
-	acpigen_write_return_op(LOCAL0_OP);
-}
-
-static void acp_soc_write_msg0_method(void)
-{
-	acpigen_write_method_serialized("MSG0", 3);
-
-	/* If (ARG2 != 0x9) */
-	acpigen_write_if_lnotequal_op_int(ARG2_OP, 0x9);
-
-	acp_soc_write_mailbox_access();
-
-	acpigen_write_else();
-
-	acp_soc_write_psp_mailbox_access();
-
-	acpigen_write_if_end();
-
-	acpigen_write_method_end(); /* MSG0 */
-}
-
-void acp_soc_write_ssdt_entry(const struct device *dev)
-{
-	/*
-	 * SMN and mailbox interface using the SMN OperationRegion on the host bridge
-	 *
-	 * Provide both SMN read/write methods for direct SMN register access and the MSG0
-	 * method which is used by some ACP drivers to access two different mailbox interfaces
-	 * in the hardware. One mailbox interface is used to configure the ACP's clock source,
-	 * the other one is used to notify the PSP that the DSP firmware has been loaded, so
-	 * that the PSP can validate the firmware and set the qualifier bit to enable running
-	 * it.
-	 *
-	 * Scope (\_SB.PCI0.GP41.ACPD)
-	 * {
-	 *	Method (SMNR, 1, Serialized)
-	 *	{
-	 *		Store (Arg0, \_SB.PCI0.GNB.SMNA)
-	 *		Return (\_SB.PCI0.GNB.SMND)
-	 *	}
-	 *
-	 *	Method (SMNW, 2, Serialized)
-	 *	{
-	 *		Store (Arg0, \_SB.PCI0.GNB.SMNA)
-	 *		Store (Arg1, \_SB.PCI0.GNB.SMND)
-	 *	}
-	 *
-	 *	Method (MSG0, 3, Serialized)
-	 *	{
-	 *		If (LNotEqual (Arg2, 0x09))
-	 *		{
-	 *			^SMNW (0x00058A74, Arg0)
-	 *			^SMNW (0x00058A54, Arg1)
-	 *			^SMNW (0x00058A14, Arg2)
-	 *			Store (^SMNR (0x00058A74), Local0)
-	 *			While (LEqual (Local0, Zero))
-	 *			{
-	 *				Store (^SMNR (0x00058A74), Local0)
-	 *			}
-	 *			Store (^SMNR (0x00058A54), Local1)
-	 *			Return (Local1)
-	 *		}
-	 *		Else
-	 *		{
-	 *			Name (MBOX, Buffer (0x04){})
-	 *			CreateWordField (MBOX, Zero, STAT)
-	 *			CreateByteField (MBOX, 0x02, CMDI)
-	 *			CreateBitField (MBOX, 0x1F, REDY)
-	 *			Store (^SMNR (0x03810570), Local0)
-	 *			Store (Local0, MBOX)
-	 *			While (LOr (LNotEqual (REDY, One), LNotEqual (CMDI, Zero)))
-	 *			{
-	 *				Store (^SMNR (0x03810570), Local0)
-	 *				Store (Local0, MBOX)
-	 *			}
-	 *			Store (Zero, Local0)
-	 *			Store (Local0, MBOX)
-	 *			Store (0x33, CMDI)
-	 *			Store (MBOX, Local0)
-	 *			^SMNW (0x03810570, Local0)
-	 *			Sleep (One)
-	 *			Store (^SMNR (0x03810570), Local0)
-	 *			Store (Local0, MBOX)
-	 *			While (LNotEqual (CMDI, Zero))
-	 *			{
-	 *				Store (^SMNR (0x03810570), Local0)
-	 *				Store (Local0, MBOX)
-	 *			}
-	 *			Return (Local0)
-	 *		}
-	 *	}
-	 * }
-	 */
-
-	acpigen_write_scope(acpi_device_path(dev));
-
-	acp_soc_write_smn_access_methods();
-
-	acp_soc_write_msg0_method();
-
-	acpigen_write_scope_end();
-}
diff --git a/src/soc/amd/cezanne/acpi/acp.asl b/src/soc/amd/cezanne/acpi/acp.asl
index 184fe15704..806b587f75 100644
--- a/src/soc/amd/cezanne/acpi/acp.asl
+++ b/src/soc/amd/cezanne/acpi/acp.asl
@@ -10,5 +10,84 @@ Scope (\_SB.PCI0.GP41) {
 		{
 			Return (STAT)
 		}
+
+		External (\_SB.PCI0.GNB.SMNA, FieldUnitObj)
+		External (\_SB.PCI0.GNB.SMND, FieldUnitObj)
+
+		/* Read SMN register and store value into ACPI variable */
+		Method (SMNR, 1, Serialized)
+		{
+			\_SB.PCI0.GNB.SMNA = Arg0
+			Return (\_SB.PCI0.GNB.SMND)
+		}
+
+		/* Write value of ACPI variable into SMN register */
+		Method (SMNW, 2, Serialized)
+		{
+			\_SB.PCI0.GNB.SMNA = Arg0
+			\_SB.PCI0.GNB.SMND = Arg1
+		}
+
+		/*
+		 * SMN and mailbox interface using the SMN OperationRegion on the host bridge
+		 *
+		 * Provide both SMN read/write methods for direct SMN register access and the MSG0
+		 * method which is used by some ACP drivers to access two different mailbox interfaces
+		 * in the hardware. One mailbox interface is used to configure the ACP's clock source,
+		 * the other one is used to notify the PSP that the DSP firmware has been loaded, so
+		 * that the PSP can validate the firmware and set the qualifier bit to enable running
+		 * it.
+		 */
+		Method (MSG0, 3, Serialized)
+		{
+			If (Arg2 != 0x09)
+			{
+				/* mailbox access */
+				^SMNW (0x00058A74, Arg0)
+				^SMNW (0x00058A54, Arg1)
+				^SMNW (0x00058A14, Arg2)
+				Local0 = ^SMNR (0x00058A74)
+				While (Local0 == 0)
+				{
+					Local0 = ^SMNR (0x00058A74)
+				}
+
+				Local1 = ^SMNR (0x00058A54)
+				Return (Local1)
+			}
+			Else
+			{
+				/* PSP mailbox access */
+				Name (MBOX, Buffer (0x04) {
+					0x20, 0x57, 0x91, 0x7B
+				})
+				CreateWordField (MBOX, Zero, STAT)
+				CreateByteField (MBOX, 0x02, CMDI)
+				CreateBitField (MBOX, 0x1F, REDY)
+				Local0 = ^SMNR (0x03810570)
+				MBOX = Local0
+				While (((REDY != 1) || (CMDI != 0)))
+				{
+					Local0 = ^SMNR (0x03810570)
+					MBOX = Local0
+				}
+
+				Local0 = Zero
+				MBOX = Local0
+				CMDI = 0x33
+				Local0 = MBOX
+				^SMNW (0x03810570, Local0)
+				Sleep (1)
+				Local0 = ^SMNR (0x03810570)
+				MBOX = Local0
+				While (CMDI != 0)
+				{
+					Local0 = ^SMNR (0x03810570)
+					MBOX = Local0
+				}
+
+				Return (Local0)
+			}
+		}
 	}
 }
diff --git a/src/soc/amd/common/block/acp/Kconfig b/src/soc/amd/common/block/acp/Kconfig
index a6ff48327b..bc2dddc1f9 100644
--- a/src/soc/amd/common/block/acp/Kconfig
+++ b/src/soc/amd/common/block/acp/Kconfig
@@ -11,9 +11,3 @@ config SOC_AMD_COMMON_BLOCK_ACP_GEN2
 	help
 	  Select this option to perform Audio Co-Processor(ACP) configuration.
 	  Used by the ACP in AMD mendocino (family 17h) and possibly newer CPUs.
-
-config SOC_AMD_COMMON_BLOCK_ACP_SOC_SPECIFIC_SSDT_ENTRY
-	bool
-	help
-	  Select this option to call into the SoC code when generating the SSDT
-	  entry for the Audio Co-Processor (ACP).
diff --git a/src/soc/amd/common/block/acp/acp.c b/src/soc/amd/common/block/acp/acp.c
index 877dd9c153..836d17b052 100644
--- a/src/soc/amd/common/block/acp/acp.c
+++ b/src/soc/amd/common/block/acp/acp.c
@@ -45,9 +45,6 @@ static void acp_fill_ssdt(const struct device *dev)
 	acp_fill_wov_method(dev);
 
 	acpigen_pop_len(); /* Scope */
-
-	if (CONFIG(SOC_AMD_COMMON_BLOCK_ACP_SOC_SPECIFIC_SSDT_ENTRY))
-		acp_soc_write_ssdt_entry(dev);
 }
 
 struct device_operations amd_acp_ops = {
diff --git a/src/soc/amd/common/block/include/amdblocks/acp.h b/src/soc/amd/common/block/include/amdblocks/acp.h
index 3ec38c93d5..cdd5202bc7 100644
--- a/src/soc/amd/common/block/include/amdblocks/acp.h
+++ b/src/soc/amd/common/block/include/amdblocks/acp.h
@@ -45,6 +45,4 @@ struct acp_config {
 	bool dmic_present;
 };
 
-void acp_soc_write_ssdt_entry(const struct device *dev);
-
 #endif /* AMD_COMMON_ACP_H */

From 90d9411271fbf24b8411214b96e9f6bf6cd53071 Mon Sep 17 00:00:00 2001
From: Patrick Rudolph <patrick.rudolph@9elements.com>
Date: Thu, 12 Feb 2026 16:24:22 +0100
Subject: [PATCH 3359/3886] soc/amd/cezanne/acpi: Move SMN accessor to DSDT

Move the SMN accessor code from SSDT code to DSDT.
This allows compiletime verification of the ACPI code.

Change-Id: I3cddea079f3bfc37eb4e2b2f4496dce6441b289f
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91184
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/soc/amd/cezanne/acpi/acp.asl   |  3 --
 src/soc/amd/cezanne/acpi/pci.asl   | 20 +++++++++++++
 src/soc/amd/cezanne/root_complex.c | 45 ------------------------------
 3 files changed, 20 insertions(+), 48 deletions(-)

diff --git a/src/soc/amd/cezanne/acpi/acp.asl b/src/soc/amd/cezanne/acpi/acp.asl
index 806b587f75..51d22183df 100644
--- a/src/soc/amd/cezanne/acpi/acp.asl
+++ b/src/soc/amd/cezanne/acpi/acp.asl
@@ -11,9 +11,6 @@ Scope (\_SB.PCI0.GP41) {
 			Return (STAT)
 		}
 
-		External (\_SB.PCI0.GNB.SMNA, FieldUnitObj)
-		External (\_SB.PCI0.GNB.SMND, FieldUnitObj)
-
 		/* Read SMN register and store value into ACPI variable */
 		Method (SMNR, 1, Serialized)
 		{
diff --git a/src/soc/amd/cezanne/acpi/pci.asl b/src/soc/amd/cezanne/acpi/pci.asl
index 770a8701f6..4942f989e3 100644
--- a/src/soc/amd/cezanne/acpi/pci.asl
+++ b/src/soc/amd/cezanne/acpi/pci.asl
@@ -15,6 +15,26 @@ Device (GNB)
 	{
 		Return (0x0F)
 	}
+
+	/* Add opregion to host bridge needed for ACP driver.
+	 *
+	 * This is used by an ACPI method in the ACP's ACPI code to access different mailbox
+	 * interfaces in the hardware. Some ACP drivers will use that to both notify the PSP
+	 * that the DSP firmware has been loaded, so that the PSP can validate the firmware
+	 * and set the qualifier bit to enable running it, and to configure the ACP's clock
+	 * source.
+	 *
+	 * As this SMN access is not arbitrated and there may be other drivers or parts of
+	 * the firmware attempting to use the SMN access register pair, there is a risk of
+	 * conflict / incorrect data, but given the frequency and duration of accesses, the
+	 * risk is deemed to be quite low.
+	 */
+	OperationRegion (PSMN, PCI_Config, 0x00, 0x100)
+	Field(PSMN, AnyAcc, NoLock, Preserve) {
+		Offset (0xB8),
+		SMNA,   32,
+		SMND,   32,
+	}
 }
 
 /* PCIe GPP */
diff --git a/src/soc/amd/cezanne/root_complex.c b/src/soc/amd/cezanne/root_complex.c
index 81a99e55ec..d9999b9163 100644
--- a/src/soc/amd/cezanne/root_complex.c
+++ b/src/soc/amd/cezanne/root_complex.c
@@ -59,51 +59,6 @@ static void root_complex_fill_ssdt(const struct device *device)
 {
 	if (CONFIG(SOC_AMD_COMMON_BLOCK_ACPI_DPTC))
 		acipgen_dptci();
-
-	/* Add ACPI device, opregion to host bridge needed for ACP driver.
-	 *
-	 * This is used by an ACPI method in the ACP's ACPI code to access different mailbox
-	 * interfaces in th hardware. Some ACP drivers will use that to both notify the PSP
-	 * that the DSP firmware has been loaded, so that the PSP can validate the firmware
-	 * and set the qualifier bit to enable running it, and to configure the ACP's clock
-	 * source.
-	 *
-	 * As this SMN access is not arbitrated and there may be other drivers or parts of
-	 * the firmware attempting to use the SMN access register pair, there is a risk of
-	 * conflict / incorrect data, but given the frequency and duration of accesses, the
-	 * risk is deemed to be quite low.
-	 *
-	 *	Scope (\_SB.PCI0)
-	 *	{
-	 *		Device (GNB)
-	 *		{
-	 *			Name (_ADR, 0x0000000000000000)
-	 *			Method (_STA, 0, NotSerialized)
-	 *			{
-	 *				Return (0x0F)
-	 *			}
-	 *		}
-	 *	}
-	 *	Scope (\_SB.PCI0.GNB)
-	 *	{
-	 *		OperationRegion(SMN, SystemMemory , 0xF80000B8, 0x8)
-	 *		Field(SMN, AnyAcc, NoLock, Preserve) {
-	 *			SMNA,   32,
-	 *			SMND,   32,
-	 *		}
-	 *	}
-	 */
-	acpigen_write_scope(acpi_device_path(device));
-	struct opregion opreg = OPREGION("SMN", SYSTEMMEMORY,
-					 CONFIG_ECAM_MMCONF_BASE_ADDRESS + 0xb8, 0x8);
-	acpigen_write_opregion(&opreg);
-	static const struct fieldlist list[] = {
-		FIELDLIST_NAMESTR("SMNA", 32),
-		FIELDLIST_NAMESTR("SMND", 32),
-	};
-	acpigen_write_field(opreg.name, list, ARRAY_SIZE(list),
-			FIELD_ANYACC | FIELD_NOLOCK | FIELD_PRESERVE);
-	acpigen_write_scope_end();
 }
 
 static const char *gnb_acpi_name(const struct device *dev)

From ca601f7df6e86f6142750e7034c5f7373538a79c Mon Sep 17 00:00:00 2001
From: Kilian Krause <kilian.krause@siemens.com>
Date: Fri, 13 Feb 2026 13:08:52 +0100
Subject: [PATCH 3360/3886] drivers/i2c/rv3028c7: Use byte ops for i801 SMBus
 compatibility

The RV3028-C7 driver currently uses i2c_dev_read_at() and
i2c_dev_write_at() for block transfers when accessing RTC registers.
These block transfer functions are not universally supported across all
I2C/SMBus controller implementations in coreboot.

Specifically, the Intel i801 SMBus controller does not implement block
read/write operations, causing the RV3028-C7 driver to fail on platforms
using this controller due to missing transfer ops.

Replace block transfers with byte-by-byte operations
i2c_dev_readb_at() and i2c_dev_writeb_at(). These functions are
supported by i801.

TEST=Verified new SMBus functionality on mc_ehl8 (i801 controller).
     Verified I2C functionality still works on mc_ehl2.
     Used i2ctools from OS to read out registers 0x00-0x06 and confirmed
     values match date/time set in coreboot.

Change-Id: I8a40ae14e62e3acf7c3904a8654c1d58fe4eb813
Signed-off-by: Kilian Krause <kilian.krause@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91199
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/drivers/i2c/rv3028c7/rv3028c7.c | 38 +++++++++++++++++------------
 1 file changed, 23 insertions(+), 15 deletions(-)

diff --git a/src/drivers/i2c/rv3028c7/rv3028c7.c b/src/drivers/i2c/rv3028c7/rv3028c7.c
index 0a1e4b6872..a8ac33b5a2 100644
--- a/src/drivers/i2c/rv3028c7/rv3028c7.c
+++ b/src/drivers/i2c/rv3028c7/rv3028c7.c
@@ -86,29 +86,37 @@ static void rtc_set_time_date(struct device *dev)
 		buf[6] = coreboot_build_date.year;
 		printk(BIOS_DEBUG, "%s: Set to coreboot build date\n", dev->chip_ops->name);
 	}
-	/* According to the datasheet, date and time should be transferred in "one go"
-	   in order to avoid value corruption. */
-	if (i2c_dev_write_at(dev, buf, sizeof(buf), 0) != sizeof(buf)) {
-		printk(BIOS_ERR, "%s: Not able to set date and time!\n", dev->chip_ops->name);
+	for (size_t i = 0; i < ARRAY_SIZE(buf); i++) {
+		if (i2c_dev_writeb_at(dev, i, buf[i]) < 0) {
+			printk(BIOS_ERR, "%s: Failed to write register 0x%02zx!\n",
+				dev->chip_ops->name, i);
+			return;
+		}
 	}
 }
 
 static void rtc_final(struct device *dev)
 {
 	uint8_t buf[7];
+	int val;
+	/* Read back current RTC date and time byte by byte */
+	printk(BIOS_DEBUG, "%s: Reading current date and time...\n", dev->chip_ops->name);
 
-	/* Read back current RTC date and time and print it to the console.
-	   Date and time are read in "one go", the buffer contains seconds (byte 0)
-	   through years (byte 6) after this read. */
-	if (i2c_dev_read_at(dev, buf, sizeof(buf), 0) != sizeof(buf)) {
-		printk(BIOS_ERR, "%s: Not able to read current date and time!\n",
-			dev->chip_ops->name);
-	} else {
-		printk(BIOS_INFO, "%s: Current date %02d.%02d.%02d %02d:%02d:%02d\n",
-				dev->chip_ops->name, bcd2bin(buf[5]), bcd2bin(buf[4]),
-				bcd2bin(buf[6]), bcd2bin(buf[2]), bcd2bin(buf[1]),
-				bcd2bin(buf[0]));
+	for (size_t i = 0; i < ARRAY_SIZE(buf); i++) {
+		val = i2c_dev_readb_at(dev, i);
+		if (val < 0) {
+			printk(BIOS_ERR, "%s: Failed to read register 0x%02zx!\n",
+			       dev->chip_ops->name, i);
+			return;
+		}
+		buf[i] = (uint8_t)val;
 	}
+
+	printk(BIOS_INFO, "%s: Current date %02d.%02d.%02d %02d:%02d:%02d\n",
+			dev->chip_ops->name, bcd2bin(buf[5]), bcd2bin(buf[4]),
+			bcd2bin(buf[6]), bcd2bin(buf[2]), bcd2bin(buf[1]),
+			bcd2bin(buf[0]));
+
 	/* Make sure the EEPROM automatic refresh is enabled. */
 	if (rtc_eep_auto_refresh(dev, EEP_REFRESH_EN) != CB_SUCCESS) {
 		printk(BIOS_ERR, "%s: Not able to enable EEPROM auto refresh!\n",

From 5db15609a712e254c37f67dfb679e550bfc23487 Mon Sep 17 00:00:00 2001
From: Kilian Krause <kilian.krause@siemens.com>
Date: Fri, 13 Feb 2026 13:13:34 +0100
Subject: [PATCH 3361/3886] mb/siemens/mc_ehl8: Disable SPD write protection
 for RTC access

The mc_ehl8 variant has an RTC (RV3028-C7) at SMBus address 0x52, which
falls within the SPD EEPROM address range (0x50-0x57). By default, FSP
write-protects this range.

Disable write protection for mc_ehl8 to allow RTC configuration.

TEST=Boot system into OS and use i2ctools to read out registers
     0x00-0x06 of the RTC to verify that the driver set the correct date
     and time.

Change-Id: I0e6426f57d7e316a74102b1e5352ce9d334eac02
Signed-off-by: Kilian Krause <kilian.krause@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91200
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/siemens/mc_ehl/romstage_fsp_params.c | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/src/mainboard/siemens/mc_ehl/romstage_fsp_params.c b/src/mainboard/siemens/mc_ehl/romstage_fsp_params.c
index d386d756a6..1e818345ba 100644
--- a/src/mainboard/siemens/mc_ehl/romstage_fsp_params.c
+++ b/src/mainboard/siemens/mc_ehl/romstage_fsp_params.c
@@ -38,8 +38,10 @@ void mainboard_memory_init_params(FSPM_UPD *memupd)
 
 	/* Enable Row-Hammer prevention */
 	memupd->FspmConfig.RhPrevention = 1;
-	if (CONFIG(BOARD_SIEMENS_MC_EHL1)) {
-		/* Allow writes to EEPROM addresses 0x50..0x57. */
+	if (CONFIG(BOARD_SIEMENS_MC_EHL1) || CONFIG(BOARD_SIEMENS_MC_EHL8)) {
+		/* Disable write protection for SMBus addresses 0x50-0x57.
+		* mc_ehl1: Writable SPD EEPROM
+		* mc_ehl8: RTC at address 0x52 */
 		memupd->FspmConfig.SmbusSpdWriteDisable = 0;
 	}
 }

From 5d084f533ff21e4f7458b565b844a506aa5099dd Mon Sep 17 00:00:00 2001
From: Jeremy Soller <jeremy@system76.com>
Date: Fri, 31 May 2024 13:58:00 -0600
Subject: [PATCH 3362/3886] drivers/intel/dtbt: Add discrete Thunderbolt driver

Add a new driver which enables basic TBT support for the Alpine Ridge,
Titan Ridge, and Maple Ridge discrete Thunderbolt controllers.

This driver will initially be used on the Lenovo T480/T480s and
System76 RPL-HX platform boards.

Ref: edk2-platforms KabylakeOpenBoardPkg reference implementation
Ref: Titan Ridge BIOS Implementation Guide v1.4
Ref: Maple Ridge BIOS Implementation Guide v1.6 (#632472)

Change-Id: Ib78ce43740956fa2c93b9ebddb0eeb319dcc0364
Signed-off-by: Jeremy Soller <jeremy@system76.com>
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75286
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/drivers/intel/dtbt/Kconfig     |   9 ++
 src/drivers/intel/dtbt/Makefile.mk |   3 +
 src/drivers/intel/dtbt/chip.h      |   8 +
 src/drivers/intel/dtbt/dtbt.c      | 247 +++++++++++++++++++++++++++++
 src/drivers/intel/dtbt/dtbt.h      |  78 +++++++++
 5 files changed, 345 insertions(+)
 create mode 100644 src/drivers/intel/dtbt/Kconfig
 create mode 100644 src/drivers/intel/dtbt/Makefile.mk
 create mode 100644 src/drivers/intel/dtbt/chip.h
 create mode 100644 src/drivers/intel/dtbt/dtbt.c
 create mode 100644 src/drivers/intel/dtbt/dtbt.h

diff --git a/src/drivers/intel/dtbt/Kconfig b/src/drivers/intel/dtbt/Kconfig
new file mode 100644
index 0000000000..c357288816
--- /dev/null
+++ b/src/drivers/intel/dtbt/Kconfig
@@ -0,0 +1,9 @@
+config DRIVERS_INTEL_DTBT
+	def_bool n
+	help
+	  Enable support for discrete Thunderbolt controllers (Alpine Ridge,
+	  Titan Ridge, and Maple Ridge). Provides device initialization and ACPI
+	  _DSD/opregion for S3 sleep support. Mainboards must call \TBTS from
+	  their MPTS so TBT is prepared before sleep.
+
+	  Note: Only a single TBT bridge device is currently supported.
diff --git a/src/drivers/intel/dtbt/Makefile.mk b/src/drivers/intel/dtbt/Makefile.mk
new file mode 100644
index 0000000000..1b5252dda0
--- /dev/null
+++ b/src/drivers/intel/dtbt/Makefile.mk
@@ -0,0 +1,3 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
+ramstage-$(CONFIG_DRIVERS_INTEL_DTBT) += dtbt.c
diff --git a/src/drivers/intel/dtbt/chip.h b/src/drivers/intel/dtbt/chip.h
new file mode 100644
index 0000000000..2b1dfa70a5
--- /dev/null
+++ b/src/drivers/intel/dtbt/chip.h
@@ -0,0 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef _DRIVERS_INTEL_DTBT_CHIP_H_
+#define _DRIVERS_INTEL_DTBT_CHIP_H_
+
+struct drivers_intel_dtbt_config {};
+
+#endif /* _DRIVERS_INTEL_DTBT_CHIP_H_ */
diff --git a/src/drivers/intel/dtbt/dtbt.c b/src/drivers/intel/dtbt/dtbt.c
new file mode 100644
index 0000000000..695f44105e
--- /dev/null
+++ b/src/drivers/intel/dtbt/dtbt.c
@@ -0,0 +1,247 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <acpi/acpigen.h>
+#include <console/console.h>
+#include <delay.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pciexp.h>
+#include <device/pci_ids.h>
+#include <timer.h>
+#include "chip.h"
+#include "dtbt.h"
+
+
+/* Returns true on success, false on timeout or TBT2PCIE Error field non-zero */
+static bool dtbt_cmd(struct device *dev, u8 command, u32 data, u32 timeout)
+{
+	u32 reg = (data << 8) | (command << 1) | PCIE2TBT_VALID;
+	u32 status;
+	u8 error;
+
+	printk(BIOS_SPEW, "dTBT send command 0x%x\n", command);
+	/* Send command */
+	pci_write_config32(dev, PCIE2TBT, reg);
+	/* Wait for Done bit */
+	if (!wait_ms(timeout, (status = pci_read_config32(dev, TBT2PCIE)) & TBT2PCIE_DONE)) {
+		printk(BIOS_ERR, "dTBT command 0x%x send timeout, status 0x%x\n", command, status);
+		return false;
+	}
+	/* Check Error field (bits 15:12) */
+	error = (status & TBT2PCIE_ERROR_MASK) >> 12;
+	if (error != TBT2PCIE_ERROR_SUCCESS) {
+		printk(BIOS_ERR, "dTBT command 0x%x failed, TBT2PCIE Error 0x%x (status 0x%x)\n",
+		       command, error, status);
+		pci_write_config32(dev, PCIE2TBT, 0);
+		return false;
+	}
+	/* Clear valid bit */
+	pci_write_config32(dev, PCIE2TBT, 0);
+	/* Wait for done bit to be cleared */
+	if (!wait_ms(timeout, (status = pci_read_config32(dev, TBT2PCIE)) & TBT2PCIE_DONE)) {
+		printk(BIOS_ERR, "dTBT command 0x%x clear valid bit timeout, status 0x%x\n",
+		       command, status);
+		return false;
+	}
+	return true;
+}
+
+static void dtbt_write_dsd(void)
+{
+	struct acpi_dp *dsd = acpi_dp_new_table("_DSD");
+
+	acpi_device_add_hotplug_support_in_d3(dsd);
+	acpi_device_add_external_facing_port(dsd);
+	acpi_dp_write(dsd);
+}
+
+static void dtbt_write_opregion(void)
+{
+	const struct opregion opregion = OPREGION("PXCS", PCI_CONFIG, 0, 0x1000);
+	const struct fieldlist fieldlist[] = {
+		FIELDLIST_OFFSET(TBT2PCIE),
+		FIELDLIST_NAMESTR("TB2P", 32),
+		FIELDLIST_OFFSET(PCIE2TBT),
+		FIELDLIST_NAMESTR("P2TB", 32),
+	};
+
+	acpigen_write_opregion(&opregion);
+	acpigen_write_field("PXCS", fieldlist, ARRAY_SIZE(fieldlist),
+			    FIELD_DWORDACC | FIELD_NOLOCK | FIELD_PRESERVE);
+}
+
+/*
+ * Generated ASL:
+ *
+ * Scope (\_SB.PCI0.RPxx)
+ * {
+ *     _DSD (Package () { ... hotplug support, external facing port ... })
+ *     Device (DTBT)
+ *     {
+ *         Name (_ADR, 0)
+ *         OperationRegion (PXCS, PCI_Config, 0, 0x1000)
+ *         Field (PXCS, DWordAcc, NoLock, Preserve)
+ *         {
+ *             Offset (0x2A40),
+ *             TB2P,   32,
+ *             Offset (0),
+ *             P2TB,   32,
+ *         }
+ *         Method (PTS, 0, Serialized)
+ *         {
+ *             Debug = "dTBT prepare to sleep"
+ *             Store (0x06, P2TB)
+ *             Debug = TB2P
+ *             Store (0, P2TB)
+ *             Debug = TB2P
+ *         }
+ *     }
+ * }
+ * Scope (\)
+ * {
+ *     Method (TBTS, 0)
+ *     {
+ *         \_SB.PCI0.RPxx.DTBT.PTS ()
+ *     }
+ * }
+ */
+static void dtbt_fill_ssdt(const struct device *dev)
+{
+	/* We only want to create a single ACPI device in the SSDT */
+	static bool ssdt_done;
+
+	struct bus *bus;
+	struct device *parent;
+	const char *parent_scope;
+	const char *dev_name = acpi_device_name(dev);
+
+	if (ssdt_done)
+		return;
+
+	bus = dev->upstream;
+	if (!bus) {
+		printk(BIOS_ERR, "dTBT bus invalid\n");
+		return;
+	}
+
+	parent = bus->dev;
+	if (!parent || !is_pci(parent)) {
+		printk(BIOS_ERR, "dTBT parent invalid\n");
+		return;
+	}
+
+	parent_scope = acpi_device_path(parent);
+	if (!parent_scope) {
+		printk(BIOS_ERR, "dTBT parent scope not valid\n");
+		return;
+	}
+
+	/* Scope */
+	acpigen_write_scope(parent_scope);
+	dtbt_write_dsd();
+
+	/* Device */
+	acpigen_write_device(dev_name);
+	acpigen_write_name_integer("_ADR", 0);
+	dtbt_write_opregion();
+
+	/* PTS Method */
+	acpigen_write_method_serialized("PTS", 0);
+
+	acpigen_write_debug_string("dTBT prepare to sleep");
+	acpigen_write_store_int_to_namestr(PCIE2TBT_GO2SX_NO_WAKE << 1, "P2TB");
+	acpigen_write_delay_until_namestr_int(GO2SX_TIMEOUT_MS, "TB2P", PCIE2TBT_GO2SX_NO_WAKE << 1);
+
+	acpigen_write_debug_namestr("TB2P");
+	acpigen_write_store_int_to_namestr(0, "P2TB");
+	acpigen_write_delay_until_namestr_int(GO2SX_TIMEOUT_MS, "TB2P", 0);
+	acpigen_write_debug_namestr("TB2P");
+
+	acpigen_write_method_end();
+	acpigen_write_device_end();
+	acpigen_write_scope_end();
+
+	/* \.TBTS Method: mainboard must call this from MPTS/_PTS */
+	acpigen_write_scope("\\");
+	acpigen_write_method("TBTS", 0);
+	acpigen_emit_namestring(acpi_device_path_join(dev, "PTS"));
+	acpigen_write_method_end();
+	acpigen_write_scope_end();
+
+	printk(BIOS_INFO, "%s.%s %s\n", parent_scope, dev_name, dev_path(dev));
+	ssdt_done = true;
+}
+
+static const char *dtbt_acpi_name(const struct device *dev)
+{
+	return "DTBT";
+}
+
+static void dtbt_enable(struct device *dev)
+{
+	/* Only enable the primary bridge device (device 0, function 0) */
+	if (!is_dev_enabled(dev) || dev->path.pci.devfn != 0)
+		return;
+
+	printk(BIOS_INFO, "dTBT controller found at %s\n", dev_path(dev));
+
+	/* Set security level (Table 37/428); failure aborts enable */
+	// XXX: Recommendation is to set SL1 ("User Authorization")
+	printk(BIOS_DEBUG, "dTBT set security level SL0\n");
+	if (!dtbt_cmd(dev, PCIE2TBT_SET_SECURITY_LEVEL, SEC_LEVEL_NONE, MBOX_TIMEOUT_MS)) {
+		printk(BIOS_ERR, "dTBT Set_Security_Level failed, aborting enable\n");
+		return;
+	}
+
+	if (acpi_is_wakeup_s3()) {
+		printk(BIOS_DEBUG, "dTBT SX exit\n");
+		if (!dtbt_cmd(dev, PCIE2TBT_SX_EXIT_TBT_CONNECTED, 0, MBOX_TIMEOUT_MS))
+			printk(BIOS_ERR, "dTBT Sx_Exit_TBT_Connected failed\n");
+		if (pci_read_config32(dev, TBT2PCIE) == 0xffffffff)
+			printk(BIOS_ERR, "dTBT S3 resume failure.\n");
+	} else {
+		printk(BIOS_DEBUG, "dTBT set boot on\n");
+		if (dtbt_cmd(dev, PCIE2TBT_BOOT_ON, 0, MBOX_TIMEOUT_MS)) {
+			printk(BIOS_DEBUG, "dTBT set USB on\n");
+			dtbt_cmd(dev, PCIE2TBT_USB_ON, 0, MBOX_TIMEOUT_MS);
+		} else {
+			printk(BIOS_ERR, "dTBT BOOT_ON failed, skipping USB_ON\n");
+		}
+	}
+}
+
+static struct device_operations dtbt_device_ops = {
+	.read_resources   = pci_bus_read_resources,
+	.set_resources    = pci_dev_set_resources,
+	.enable_resources = pci_bus_enable_resources,
+	.acpi_fill_ssdt   = dtbt_fill_ssdt,
+	.acpi_name        = dtbt_acpi_name,
+	.scan_bus         = pciexp_scan_bridge,
+	.reset_bus        = pci_bus_reset,
+	.enable           = dtbt_enable
+};
+
+/* We only want to match the bridge devices */
+static const unsigned short pci_device_ids[] = {
+	AR_2C_BRG,
+	AR_4C_BRG,
+	AR_LP_BRG,
+	AR_4C_C0_BRG,
+	AR_2C_C0_BRG,
+	TR_2C_BRG,
+	TR_4C_BRG,
+	TR_DD_BRG,
+	MR_2C_BRG,
+	MR_4C_BRG,
+	0
+};
+
+static const struct pci_driver intel_dtbt_driver __pci_driver = {
+	.ops		= &dtbt_device_ops,
+	.vendor		= PCI_VID_INTEL,
+	.devices	= pci_device_ids,
+};
+
+struct chip_operations drivers_intel_dtbt_ops = {
+	.name = "Intel Discrete Thunderbolt",
+};
diff --git a/src/drivers/intel/dtbt/dtbt.h b/src/drivers/intel/dtbt/dtbt.h
new file mode 100644
index 0000000000..40c1938ceb
--- /dev/null
+++ b/src/drivers/intel/dtbt/dtbt.h
@@ -0,0 +1,78 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef _DRIVERS_INTEL_DTBT_H_
+#define _DRIVERS_INTEL_DTBT_H_
+
+/* Alpine Ridge device IDs */
+#define AR_2C_NHI	0x1575
+#define AR_2C_BRG	0x1576
+#define AR_2C_USB	0x15B5
+#define AR_4C_NHI	0x1577
+#define AR_4C_BRG	0x1578
+#define AR_4C_USB	0x15B6
+#define AR_LP_NHI	0x15BF
+#define AR_LP_BRG	0x15C0
+#define AR_LP_USB	0x15C1
+#define AR_4C_C0_NHI	0x15D2
+#define AR_4C_C0_BRG	0x15D3
+#define AR_4C_C0_USB	0x15D4
+#define AR_2C_C0_NHI	0x15D9
+#define AR_2C_C0_BRG	0x15DA
+#define AR_2C_C0_USB	0x15DB
+
+/* Titan Ridge device IDs */
+#define TR_2C_BRG	0x15E7
+#define TR_2C_NHI	0x15E8
+#define TR_2C_USB	0x15E9
+#define TR_4C_BRG	0x15EA
+#define TR_4C_NHI	0x15EB
+#define TR_4C_USB	0x15EC
+#define TR_DD_BRG	0x15EF
+#define TR_DD_USB	0x15F0
+
+/* Maple Ridge device IDs */
+#define MR_2C_BRG	0x1133
+#define MR_2C_NHI	0x1134
+#define MR_2C_USB	0x1135
+#define MR_4C_BRG	0x1136
+#define MR_4C_NHI	0x1137
+#define MR_4C_USB	0x1138
+
+/* Security Levels */
+#define SEC_LEVEL_NONE			0
+#define SEC_LEVEL_USER			1
+#define SEC_LEVEL_AUTH			2
+#define SEC_LEVEL_DP_ONLY		3
+
+#define PCIE2TBT			0x54C
+#define PCIE2TBT_VALID			BIT(0)
+#define PCIE2TBT_GO2SX			2
+#define PCIE2TBT_GO2SX_NO_WAKE		3
+#define PCIE2TBT_SX_EXIT_TBT_CONNECTED	4
+#define PCIE2TBT_OS_UP			6
+#define PCIE2TBT_SET_SECURITY_LEVEL	8
+#define PCIE2TBT_GET_SECURITY_LEVEL	9
+#define PCIE2TBT_BOOT_ON		24
+#define PCIE2TBT_USB_ON			25
+#define PCIE2TBT_GET_ENUMERATION_METHOD	26
+#define PCIE2TBT_SET_ENUMERATION_METHOD	27
+#define PCIE2TBT_POWER_CYCLE		28
+#define PCIE2TBT_SX_START		29
+#define PCIE2TBT_ACL_BOOT		30
+#define PCIE2TBT_CONNECT_TOPOLOGY	31
+
+#define TBT2PCIE			0x548
+#define TBT2PCIE_DONE			BIT(0)
+#define TBT2PCIE_ERROR_MASK		(0xF << 12)	/* bits 15:12, Table 38 */
+#define TBT2PCIE_ERROR_SUCCESS		0
+#define TBT2PCIE_ERROR_GENERAL		1
+#define TBT2PCIE_ERROR_ILLEGAL_DATA	2
+#define TBT2PCIE_ERROR_TIMEOUT		3
+
+// Timeout for mailbox commands unless otherwise specified.
+#define MBOX_TIMEOUT_MS			5000
+
+// Timeout for controller to ack GO2SX/GO2SX_NO_WAKE mailbox command.
+#define GO2SX_TIMEOUT_MS		600
+
+#endif /* _DRIVERS_INTEL_DTBT_H_ */

From 38468f67337d009856dced3c2fd0e418cf0bae67 Mon Sep 17 00:00:00 2001
From: Tim Crawford <tcrawford@system76.com>
Date: Fri, 31 May 2024 13:59:33 -0600
Subject: [PATCH 3363/3886] mb/system76/rpl: Select discrete TBT controller
 driver

The HX boards, using PCH-S, use a discrete Thunderbolt device (Intel
Maple Ridge), as opposed to a built-in one like the boards using PCH-P.

Fixes Thunderbolt on RPL-HX boards using the Maple Ridge controller.

Change-Id: I53d18f3ec5a084431e1113782c791bcb42728350
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76584
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Evie (Ivi) Ballou <iviballou@gmail.com>
---
 src/mainboard/system76/rpl/Kconfig | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/src/mainboard/system76/rpl/Kconfig b/src/mainboard/system76/rpl/Kconfig
index f29c110596..c46ed2dada 100644
--- a/src/mainboard/system76/rpl/Kconfig
+++ b/src/mainboard/system76/rpl/Kconfig
@@ -27,6 +27,7 @@ config BOARD_SYSTEM76_RPL_COMMON
 
 config BOARD_SYSTEM76_ADDW3
 	select BOARD_SYSTEM76_RPL_COMMON
+	select DRIVERS_INTEL_DTBT
 	select EC_SYSTEM76_EC_DGPU
 	select MAINBOARD_USES_IFD_GBE_REGION
 	select PCIEXP_HOTPLUG
@@ -40,6 +41,7 @@ config BOARD_SYSTEM76_ADDW4
 
 config BOARD_SYSTEM76_BONW15
 	select BOARD_SYSTEM76_RPL_COMMON
+	select DRIVERS_INTEL_DTBT
 	select EC_SYSTEM76_EC_DGPU
 	select PCIEXP_HOTPLUG
 	select SOC_INTEL_ALDERLAKE_PCH_S
@@ -74,12 +76,14 @@ config BOARD_SYSTEM76_ORYP11
 config BOARD_SYSTEM76_ORYP12
 	select BOARD_SYSTEM76_RPL_COMMON
 	select DRIVERS_I2C_TAS5825M
+	select DRIVERS_INTEL_DTBT
 	select EC_SYSTEM76_EC_DGPU
 	select PCIEXP_HOTPLUG
 	select SOC_INTEL_ALDERLAKE_PCH_S
 
 config BOARD_SYSTEM76_SERW13
 	select BOARD_SYSTEM76_RPL_COMMON
+	select DRIVERS_INTEL_DTBT
 	select EC_SYSTEM76_EC_DGPU
 	select PCIEXP_HOTPLUG
 	select SOC_INTEL_ALDERLAKE_PCH_S

From 1f12249ec017aa48434b715d3a17d3c45f76d520 Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Fri, 18 Jul 2025 14:24:05 -0500
Subject: [PATCH 3364/3886] mb/lenovo/{t480,t480s,x280}: Enable TBT support

Select the discrete TBT controller driver, and configure the necessary
GPIOs for the Alpine Ridge TBT controller to be fully functional.
Add ACPI to ensure the TBT controller properly handles S3 sleep and
resume. Update the documentation w/r/t TBT functionality.

TEST=build/boot Lenovo T480, boot Linux, verify all TBT-related PCI
devices populated, lower USB-C port works for USB data and PCIe.

Change-Id: Ie5586fa72ed6819b9d1c37373c21605d39bad7b4
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88490
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 Documentation/mainboard/lenovo/skylake.md              |  3 +--
 src/mainboard/lenovo/sklkbl_thinkpad/Kconfig           |  3 +++
 .../lenovo/sklkbl_thinkpad/acpi/mainboard.asl          |  5 +++++
 src/mainboard/lenovo/sklkbl_thinkpad/acpi/sleep.asl    |  8 ++++++++
 src/mainboard/lenovo/sklkbl_thinkpad/dsdt.asl          |  1 +
 .../lenovo/sklkbl_thinkpad/variants/t480/gpio.c        |  8 ++++----
 .../lenovo/sklkbl_thinkpad/variants/t480s/gpio.c       |  8 ++++----
 .../lenovo/sklkbl_thinkpad/variants/x280/gpio.c        | 10 +++++-----
 8 files changed, 31 insertions(+), 15 deletions(-)
 create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/acpi/mainboard.asl
 create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/acpi/sleep.asl

diff --git a/Documentation/mainboard/lenovo/skylake.md b/Documentation/mainboard/lenovo/skylake.md
index 64e075e2cd..352d91b3ef 100644
--- a/Documentation/mainboard/lenovo/skylake.md
+++ b/Documentation/mainboard/lenovo/skylake.md
@@ -193,8 +193,6 @@ binaries if only flashing the `bios` region.
 
 ## Known Issues
 
-- Alpine Ridge Thunderbolt 3 controller does not work
-  - Lower (right) USB-C port only works for charging/DP alt mode, not USB/PCIe data
 - Some Fn+F{1-12} keys aren't handled correctly
 - Nvidia dGPU is finicky
   - Needs option ROM
@@ -206,6 +204,7 @@ binaries if only flashing the `bios` region.
 
 ## Verified Working
 
+- Alpine Ridge Thunderbolt 3 controller
 - Integrated graphics init with libgfxinit
 - video output: internal (eDP), miniDP
 - ACPI support
diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/Kconfig b/src/mainboard/lenovo/sklkbl_thinkpad/Kconfig
index d69d94f638..b7cc705699 100644
--- a/src/mainboard/lenovo/sklkbl_thinkpad/Kconfig
+++ b/src/mainboard/lenovo/sklkbl_thinkpad/Kconfig
@@ -32,6 +32,7 @@ config BOARD_LENOVO_T470S
 config BOARD_LENOVO_T480
 	bool
 	select BOARD_LENOVO_SKLKBL_THINKPAD_COMMON
+	select DRIVERS_INTEL_DTBT
 	select SOC_INTEL_KABYLAKE
 	select MEC1653_HAS_DEBUG_UNLOCK
 	select VARIANT_HAS_DGPU
@@ -39,6 +40,7 @@ config BOARD_LENOVO_T480
 config BOARD_LENOVO_T480S
 	bool
 	select BOARD_LENOVO_SKLKBL_THINKPAD_COMMON
+	select DRIVERS_INTEL_DTBT
 	select SOC_INTEL_KABYLAKE
 	select VARIANT_HAS_DGPU
 
@@ -52,6 +54,7 @@ config BOARD_LENOVO_T580
 config BOARD_LENOVO_X280
 	bool
 	select BOARD_LENOVO_SKLKBL_THINKPAD_COMMON
+	select DRIVERS_INTEL_DTBT
 	select SOC_INTEL_KABYLAKE
 	select HAVE_SPD_IN_CBFS
 
diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/acpi/mainboard.asl b/src/mainboard/lenovo/sklkbl_thinkpad/acpi/mainboard.asl
new file mode 100644
index 0000000000..34b90af325
--- /dev/null
+++ b/src/mainboard/lenovo/sklkbl_thinkpad/acpi/mainboard.asl
@@ -0,0 +1,5 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+Scope (\_SB) {
+	#include "sleep.asl"
+}
diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/acpi/sleep.asl b/src/mainboard/lenovo/sklkbl_thinkpad/acpi/sleep.asl
new file mode 100644
index 0000000000..7460baeabb
--- /dev/null
+++ b/src/mainboard/lenovo/sklkbl_thinkpad/acpi/sleep.asl
@@ -0,0 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+/* Prepare discrete TBT controller before sleep */
+Method(MPTS, 1, Serialized) {
+	If (CondRefOf(\TBTS)) {
+		\TBTS()
+	}
+}
diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/dsdt.asl b/src/mainboard/lenovo/sklkbl_thinkpad/dsdt.asl
index aa4d4de2a6..1279665bee 100644
--- a/src/mainboard/lenovo/sklkbl_thinkpad/dsdt.asl
+++ b/src/mainboard/lenovo/sklkbl_thinkpad/dsdt.asl
@@ -11,6 +11,7 @@ DefinitionBlock(
 )
 {
 	#include <acpi/dsdt_top.asl>
+	#include <soc/intel/common/block/acpi/acpi/platform.asl>
 	#include <soc/intel/common/block/acpi/acpi/globalnvs.asl>
 	#include <cpu/intel/common/acpi/cpu.asl>
 
diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480/gpio.c b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480/gpio.c
index f337843fd9..ffd2841e49 100644
--- a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480/gpio.c
+++ b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480/gpio.c
@@ -86,7 +86,7 @@ static const struct pad_config gpio_table[] = {
 	PAD_NC(GPP_C18, NONE),
 	PAD_NC(GPP_C19, NONE),
 	PAD_CFG_GPO(GPP_C20, 0, DEEP),					/* EPRIVACY_ON */
-	PAD_CFG_GPO(GPP_C21, 0, DEEP),					/* TBT_FORCE_PWR */
+	PAD_CFG_GPO(GPP_C21, 1, PLTRST),				/* TBT_FORCE_PWR */
 	PAD_CFG_GPI_SCI(GPP_C22, NONE, DEEP, EDGE_SINGLE, INVERT),	/* -EC_SCI */
 	PAD_CFG_GPI_SCI(GPP_C23, NONE, DEEP, EDGE_SINGLE, INVERT),	/* -EC_WAKE */
 
@@ -191,9 +191,9 @@ static const struct pad_config gpio_table[] = {
 	PAD_NC(GPP_G1, NONE),
 	PAD_NC(GPP_G2, NONE),
 	PAD_NC(GPP_G3, NONE),
-	PAD_CFG_GPO(GPP_G4, 0, DEEP),					/* TBT_RTD3_PWR_EN */
-	PAD_CFG_GPO(GPP_G5, 0, DEEP),					/* TBT_FORCE_USB_PWR */
-	PAD_CFG_GPO(GPP_G6, 0, DEEP),					/* -TBT_PERST */
+	PAD_CFG_GPO(GPP_G4, 1, PLTRST),					/* TBT_RTD3_PWR_EN */
+	PAD_CFG_GPO(GPP_G5, 1, PLTRST),					/* TBT_FORCE_USB_PWR */
+	PAD_CFG_GPO(GPP_G6, 1, PLTRST),					/* -TBT_PERST */
 	PAD_CFG_GPI_SCI(GPP_G7, NONE, DEEP, LEVEL, INVERT),		/* -TBT_PCIE_WAKE */
 };
 
diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/gpio.c b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/gpio.c
index 4f1c57390d..c24c1abb07 100644
--- a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/gpio.c
+++ b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/gpio.c
@@ -82,7 +82,7 @@ static const struct pad_config gpio_table[] = {
 	PAD_NC(GPP_C18, NONE),
 	PAD_NC(GPP_C19, NONE),
 	PAD_CFG_GPO(GPP_C20, 0, DEEP),					/* EPRIVACY_ON */
-	PAD_CFG_GPO(GPP_C21, 0, DEEP),					/* TBT_FORCE_PWR */
+	PAD_CFG_GPO(GPP_C21, 1, PLTRST),					/* TBT_FORCE_PWR */
 	PAD_CFG_GPI_SCI(GPP_C22, NONE, DEEP, EDGE_SINGLE, INVERT),	/* -EC_SCI */
 	PAD_CFG_GPI_SCI(GPP_C23, NONE, DEEP, EDGE_SINGLE, INVERT),	/* -EC_WAKE */
 
@@ -187,9 +187,9 @@ static const struct pad_config gpio_table[] = {
 	PAD_NC(GPP_G1, NONE),
 	PAD_NC(GPP_G2, NONE),
 	PAD_NC(GPP_G3, NONE),
-	PAD_CFG_GPO(GPP_G4, 0, DEEP),					/* TBT_RTD3_PWR_EN */
-	PAD_CFG_GPO(GPP_G5, 0, DEEP),					/* TBT_FORCE_USB_PWR */
-	PAD_CFG_GPO(GPP_G6, 0, DEEP),					/* -TBT_PERST */
+	PAD_CFG_GPO(GPP_G4, 1, PLTRST),					/* TBT_RTD3_PWR_EN */
+	PAD_CFG_GPO(GPP_G5, 1, PLTRST),					/* TBT_FORCE_USB_PWR */
+	PAD_CFG_GPO(GPP_G6, 1, PLTRST),					/* -TBT_PERST */
 	PAD_CFG_GPI_SCI(GPP_G7, NONE, DEEP, LEVEL, INVERT),		/* -TBT_PCIE_WAKE */
 };
 
diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/x280/gpio.c b/src/mainboard/lenovo/sklkbl_thinkpad/variants/x280/gpio.c
index f38734be85..13c4a5240b 100644
--- a/src/mainboard/lenovo/sklkbl_thinkpad/variants/x280/gpio.c
+++ b/src/mainboard/lenovo/sklkbl_thinkpad/variants/x280/gpio.c
@@ -82,7 +82,7 @@ static const struct pad_config gpio_table[] = {
 	PAD_NC(GPP_C18, NONE),
 	PAD_NC(GPP_C19, NONE),
 	PAD_NC(GPP_C20, NONE),
-	PAD_CFG_GPO(GPP_C21, 0, DEEP),					/* TBT_FORCE_PWR */
+	PAD_CFG_GPO(GPP_C21, 1, PLTRST),				/* TBT_FORCE_PWR */
 	PAD_CFG_GPI_SCI(GPP_C22, NONE, DEEP, EDGE_SINGLE, INVERT),	/* -EC_SCI */
 	PAD_CFG_GPI_SCI(GPP_C23, NONE, DEEP, EDGE_SINGLE, INVERT),	/* -EC_WAKE */
 
@@ -187,10 +187,10 @@ static const struct pad_config gpio_table[] = {
 	PAD_NC(GPP_G1, NONE),
 	PAD_NC(GPP_G2, NONE),
 	PAD_NC(GPP_G3, NONE),
-	PAD_CFG_GPO(GPP_G4, 0, DEEP),                                   /* TBT_RTD3_PWR_EN */
-	PAD_CFG_GPO(GPP_G5, 0, DEEP),                                   /* TBT_FORCE_USB_PWR */
-	PAD_CFG_GPO(GPP_G6, 0, DEEP),                                   /* -TBT_PERST */
-	PAD_CFG_GPI_SCI(GPP_G7, NONE, DEEP, LEVEL, INVERT),             /* -TBT_PCIE_WAKE */
+	PAD_CFG_GPO(GPP_G4, 1, PLTRST),					/* TBT_RTD3_PWR_EN */
+	PAD_CFG_GPO(GPP_G5, 1, PLTRST),					/* TBT_FORCE_USB_PWR */
+	PAD_CFG_GPO(GPP_G6, 1, PLTRST),					/* -TBT_PERST */
+	PAD_CFG_GPI_SCI(GPP_G7, NONE, DEEP, LEVEL, INVERT),		/* -TBT_PCIE_WAKE */
 
 };
 

From 970201012365bad68b1a6d71fcbc10f44694007d Mon Sep 17 00:00:00 2001
From: Bora Guvendik <bora.guvendik@intel.com>
Date: Tue, 16 Dec 2025 08:56:38 -0800
Subject: [PATCH 3365/3886] mb/google/fatcat: Fix Gen4 SSD power sequencing
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Move Gen4 SSD power enable (GPP_B10) from ramstage GPIO table to
pre-memory configuration to ensure proper delay between power enable
and reset signals. This is required to fix PCIe speed downgrade or
link failure issues seen with some NVMe parts when a non-serial image
is used for boot.

Changes:
 - Enable GPP_B10 (GEN4_SSD_PWREN) in pre_mem_gen4_ssd_pwr_pads
 - Remove duplicate GPP_B10 configuration from gen4_ssd_pads
 - Remove GPP_B10 from ramstage gpio_table

BUG=None
TEST=Boot to OS, check PCIe link speed for SSD.

Change-Id: I969a0d5576b9a229f70a4d01737b7f594876b106
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90523
Reviewed-by: Huang, Cliff <cliff.huang@intel.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Pranava Y N <pranavayn@google.com>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 .../google/fatcat/variants/fatcat/fw_config.c     | 15 +++++++++++----
 .../google/fatcat/variants/fatcat/gpio.c          |  2 --
 2 files changed, 11 insertions(+), 6 deletions(-)

diff --git a/src/mainboard/google/fatcat/variants/fatcat/fw_config.c b/src/mainboard/google/fatcat/variants/fatcat/fw_config.c
index e0a59219a4..0344103453 100644
--- a/src/mainboard/google/fatcat/variants/fatcat/fw_config.c
+++ b/src/mainboard/google/fatcat/variants/fatcat/fw_config.c
@@ -235,14 +235,17 @@ static const struct pad_config wwan_disable_pads[] = {
 };
 
 /* Gen4 NVME: at the top M.2 slot */
-static const struct pad_config pre_mem_gen4_ssd_pwr_pads[] = {
+static const struct pad_config pre_mem_gen4_ssd_pwr_seq1_pads[] = {
 	/* GPP_B10:     GEN4_SSD_PWREN */
 	PAD_CFG_GPO(GPP_B10, 0, PLTRST),
 };
 
-static const struct pad_config gen4_ssd_pads[] = {
+static const struct pad_config pre_mem_gen4_ssd_pwr_seq2_pads[] = {
 	/* GPP_B10:     GEN4_SSD_PWREN */
 	PAD_CFG_GPO(GPP_B10, 1, PLTRST),
+};
+
+static const struct pad_config gen4_ssd_pads[] = {
 	/* GPP_B09:     M2_GEN4_SSD_RESET_N */
 	PAD_CFG_GPO(GPP_B09, 1, PLTRST),
 };
@@ -568,11 +571,11 @@ void fw_config_configure_pre_mem_gpio(void)
 		GPIO_CONFIGURE_PADS(pre_mem_wwan_pwr_seq1_pads);
 
 	if (fw_config_probe(FW_CONFIG(STORAGE, STORAGE_NVME_GEN4))) {
-		GPIO_CONFIGURE_PADS(pre_mem_gen4_ssd_pwr_pads);
+		GPIO_CONFIGURE_PADS(pre_mem_gen4_ssd_pwr_seq1_pads);
 	} else if (fw_config_probe(FW_CONFIG(STORAGE, STORAGE_NVME_GEN5))) {
 		GPIO_CONFIGURE_PADS(pre_mem_gen5_ssd_pwr_pads);
 	} else if (fw_config_probe(FW_CONFIG(STORAGE, STORAGE_UNKNOWN))) {
-		GPIO_CONFIGURE_PADS(pre_mem_gen4_ssd_pwr_pads);
+		GPIO_CONFIGURE_PADS(pre_mem_gen4_ssd_pwr_seq1_pads);
 		GPIO_CONFIGURE_PADS(pre_mem_gen5_ssd_pwr_pads);
 	}
 
@@ -592,6 +595,10 @@ void fw_config_configure_pre_mem_gpio(void)
 	if (fw_config_probe(FW_CONFIG(FP, FP_PRESENT)))
 		GPIO_CONFIGURE_PADS(pre_mem_fp_enable_pads);
 
+	if (fw_config_probe(FW_CONFIG(STORAGE, STORAGE_NVME_GEN4)) ||
+	    fw_config_probe(FW_CONFIG(STORAGE, STORAGE_UNKNOWN))) {
+		GPIO_CONFIGURE_PADS(pre_mem_gen4_ssd_pwr_seq2_pads);
+	}
 }
 
 void fw_config_gpio_padbased_override(struct pad_config *padbased_table)
diff --git a/src/mainboard/google/fatcat/variants/fatcat/gpio.c b/src/mainboard/google/fatcat/variants/fatcat/gpio.c
index eb03641251..59dbe23680 100644
--- a/src/mainboard/google/fatcat/variants/fatcat/gpio.c
+++ b/src/mainboard/google/fatcat/variants/fatcat/gpio.c
@@ -55,8 +55,6 @@ static const struct pad_config gpio_table[] = {
 	PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_B03, NONE, DEEP, NF3),
 	/* GPP_B09:     M2_GEN4_SSD_RESET_N */
 	PAD_CFG_GPO(GPP_B09, 1, PLTRST),
-	/* GPP_B10:     GEN4_SSD_PWREN */
-	PAD_CFG_GPO(GPP_B10, 1, PLTRST),
 	/* GPP_B11:     MOD_TCSS1_DISP_HPD3 */
 	PAD_CFG_NF(GPP_B11, NONE, DEEP, NF2),
 	/* GPP_B12:     PM_SLP_S0_N */

From 59593b5b5c9444609b51e199bb8a57cf0c31efcc Mon Sep 17 00:00:00 2001
From: Cliff Huang <cliff.huang@intel.com>
Date: Tue, 11 Nov 2025 11:19:02 -0800
Subject: [PATCH 3366/3886] mb/google/fatcat: Add x1 slot power sequence and
 support AICs with PRSNT2#

Address x1 slot enumeration issues for certain add in cards (AICs)
during boot. This change implements proper power sequencing and adds
support for AICs that use PRSNT2# signaling instead of ClkReq#. The
x1 slot power rail (X1_PCIE_SLOT_PWR_EN via GPP_A8) is pull-high by
design, with GPP_A08 PAD defaulting to GPI configuration. This enables
slot power during early boot phases. PERST# (GPP_D19) is logically
ANDed with PLTRST#, ensuring PLTRST# de-assertion occurs only after x1
slot power stabilization, maintaining proper PCIe timing automatically.

For scenarios requiring power-off at boot, the following sequence
ensures compliance with PCIe link training timing requirements:

Step 1 (romstage): ClkReq PAD off; PERST# asserted; power off
Step 2 (ramstage at BS_PRE_DEVICE exit): Power on; ClkReq PAD on (if
       used)
Step 3 (ramstage at BS_DEV_INIT_CHIPS entry): PERST# de-asserted

The CBI fw_config SD field has been redefined to accommodate different
AIC types:
- SD_BAYHUB: For AICs supporting ClkReq# signaling
- SD_GENSYS: For AICs using only PRSNT2# signaling

BUG=None
TEST=Boot Fatcat board with AIC cards configured via CBI fw_config SD
field (SD_BAYHUB or SD_GENSYS). Confirm PCIe device enumeration
appears correctly in boot log. For instance:
[SPEW ]  do_pci_scan_bridge for PCI: 00:00:1c.0
[DEBUG]  PCI: pci_scan_bus for segment group 00 bus ae
[DEBUG]  PCI: 00:ae:00.0 [1217/9860] enabled

The device should be seen from lspci command, such as:
ae:00.0 Class 0805: Device 1217:9860 (rev 01)

Signed-off-by: Cliff Huang <cliff.huang@intel.com>
Change-Id: I94a7ee2ecd8d3fd83006297ef68f97ff49e47595
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90000
Reviewed-by: Pranava Y N <pranavayn@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/google/fatcat/mainboard.c       | 12 +++
 .../baseboard/include/baseboard/variants.h    |  1 +
 .../google/fatcat/variants/fatcat/fw_config.c | 74 +++++++++++++++++--
 .../google/fatcat/variants/fatcat/gpio.c      | 11 ++-
 .../fatcat/variants/fatcat/overridetree.cb    |  8 +-
 .../google/fatcat/variants/fatcat/variant.c   |  8 ++
 6 files changed, 103 insertions(+), 11 deletions(-)

diff --git a/src/mainboard/google/fatcat/mainboard.c b/src/mainboard/google/fatcat/mainboard.c
index 1ea606a6f1..b731f1d4d5 100644
--- a/src/mainboard/google/fatcat/mainboard.c
+++ b/src/mainboard/google/fatcat/mainboard.c
@@ -62,6 +62,18 @@ static void mainboard_early(void *unused)
 
 BOOT_STATE_INIT_ENTRY(BS_PRE_DEVICE, BS_ON_EXIT, mainboard_early, NULL);
 
+void __weak fw_config_post_gpio_configure(void)
+{
+	/* default implementation does nothing */
+}
+
+static void mainboard_pre_dev_init_chips(void *unused)
+{
+	fw_config_post_gpio_configure();
+}
+
+BOOT_STATE_INIT_ENTRY(BS_DEV_INIT_CHIPS, BS_ON_ENTRY, mainboard_pre_dev_init_chips, NULL);
+
 void __weak baseboard_devtree_update(void)
 {
 	/* Override dev tree settings per baseboard */
diff --git a/src/mainboard/google/fatcat/variants/baseboard/include/baseboard/variants.h b/src/mainboard/google/fatcat/variants/baseboard/include/baseboard/variants.h
index ad26ab8a67..e0f4996579 100644
--- a/src/mainboard/google/fatcat/variants/baseboard/include/baseboard/variants.h
+++ b/src/mainboard/google/fatcat/variants/baseboard/include/baseboard/variants.h
@@ -19,6 +19,7 @@ const struct pad_config *variant_early_gpio_table(size_t *num);
 const struct pad_config *variant_romstage_gpio_table(size_t *num);
 void fw_config_configure_pre_mem_gpio(void);
 void fw_config_gpio_padbased_override(struct pad_config *padbased_table);
+void fw_config_post_gpio_configure(void);
 
 const struct mb_cfg *variant_memory_params(void);
 void variant_get_spd_info(struct mem_spd *spd_info);
diff --git a/src/mainboard/google/fatcat/variants/fatcat/fw_config.c b/src/mainboard/google/fatcat/variants/fatcat/fw_config.c
index 0344103453..25f9a339df 100644
--- a/src/mainboard/google/fatcat/variants/fatcat/fw_config.c
+++ b/src/mainboard/google/fatcat/variants/fatcat/fw_config.c
@@ -168,20 +168,70 @@ static const struct pad_config audio_disable_pads[] = {
 	PAD_NC(GPP_D17, NONE),
 };
 
+/*
+ * NOTE: The PCIe slot power PADs are pulled high by default on Fatcat. Since
+ * these PADs default to GPI configuration, slot power is enabled during early
+ * boot. Also, PERST# PADs are logically ANDed with PLTRST#. This ensures that
+ * PLTRST# de-assertion at the slot occurs after PCIe slot power stabilization,
+ * maintaining proper PCIe power-on sequences.
+ *
+ * If slot power must be disabled at boot, PERST# de-assertion must occur after
+ * power restoration and satisfy PCIe link training timing requirements.
+ * Additionally, the slot power PADs are recommended to be reworked to pull low
+ *  to avoid a power glitch. The suggested power sequence is:
+ *
+ *  Step 1 (romstage): ClkReq PAD off; PERST# asserted; power off
+ *  Step 2 (ramstage at BS_PRE_DEVICE exit): Power on; ClkReq PAD on (if used)
+ *  Step 3 (ramstage at BS_DEV_INIT_CHIPS entry): PERST# de-asserted
+ */
+
+/* x1 slot power sequence: 1. no clkreq; PERST=asserted; power=off */
+static const struct pad_config pre_mem_x1slot_pads[] = {
+	/* GPP_C11:     CLKREQ2_X1_GEN4_DT_CEM_SLOT_N */
+	PAD_CFG_GPI(GPP_C11, NONE, DEEP),
+	/* GPP_D19:     X1_DT_PCIE_RST_N */
+	PAD_CFG_GPO(GPP_D19, 0, PLTRST),
+	/* GPP_A08:     X1_PCIE_SLOT_PWR_EN */
+	PAD_CFG_GPO(GPP_A08, 0, PLTRST),
+};
+
+/* x1 slot CBI + x1 slot power sequence: 2. power=on */
 static const struct pad_config x1slot_pads[] = {
 	/* GPP_A08:     X1_PCIE_SLOT_PWR_EN */
 	PAD_CFG_GPO(GPP_A08, 1, PLTRST),
 	/* GPP_D19:     X1_DT_PCIE_RST_N */
-	PAD_CFG_GPO(GPP_D19, 1, PLTRST),
+	PAD_CFG_GPO(GPP_D19, 0, PLTRST),
 	/* GPP_B25:     X1_SLOT_WAKE_N */
 	PAD_CFG_GPI_SCI_LOW(GPP_B25, NONE, DEEP, LEVEL),
 };
 
+/*
+ * x1 slot power sequence: 3. PERST# = de-assert;
+ */
+static const struct pad_config post_x1slot_pads[] = {
+	/* GPP_D19:     X1_DT_PCIE_RST_N */
+	PAD_CFG_GPO(GPP_D19, 1, PLTRST),
+};
+
+static const struct pad_config x1slot_clkreq_pads[] = {
+	/* x1 slot power sequence: 3a. Clkreq = enable for AIC with clkreq support */
+	/* GPP_C11:     CLKREQ2_X1_GEN4_DT_CEM_SLOT_N */
+	PAD_CFG_NF(GPP_C11, NONE, DEEP, NF1),
+};
+
+static const struct pad_config x1slot_prsnt_pads[] = {
+	/* x1 slot power sequence: 3b. clkreq = GPI or NC for AIC using PRSNT2# */
+	/* GPP_C11:     for PRSNT2_X1_GEN4_DT_CEM_SLOT_N */
+	PAD_CFG_GPI(GPP_C11, NONE, DEEP),
+};
+
 static const struct pad_config x1slot_disable_pads[] = {
 	/* GPP_A08:     X1_PCIE_SLOT_PWR_EN */
-	PAD_CFG_GPO(GPP_A08, 0, PLTRST),
+	PAD_CFG_GPO(GPP_A08, 1, PLTRST),
 	/* GPP_D19:     X1_DT_PCIE_RST_N */
 	PAD_NC(GPP_D19, NONE),
+	/* GPP_C11:     CLKREQ2_X1_GEN4_DT_CEM_SLOT_N */
+	PAD_NC(GPP_C11, NONE),
 	/* GPP_B25:     X1_SLOT_WAKE_N */
 	PAD_NC(GPP_B25, NONE)
 };
@@ -579,6 +629,9 @@ void fw_config_configure_pre_mem_gpio(void)
 		GPIO_CONFIGURE_PADS(pre_mem_gen5_ssd_pwr_pads);
 	}
 
+	if (!fw_config_probe(FW_CONFIG(SD, SD_NONE)))
+		GPIO_CONFIGURE_PADS(pre_mem_x1slot_pads);
+
 	/*
 	 * NOTE: We place WWAN sequence 2 here. According to the WWAN FIBOCOM
 	 * FM350-GL datasheet, the minimum time requirement (Tpr: time between 3.3V
@@ -661,10 +714,15 @@ void fw_config_gpio_padbased_override(struct pad_config *padbased_table)
 		GPIO_PADBASED_OVERRIDE(padbased_table, wwan_disable_pads);
 	}
 
-	if (fw_config_probe(FW_CONFIG(SD, SD_NONE)))
-		GPIO_PADBASED_OVERRIDE(padbased_table, x1slot_disable_pads);
-	else
+	if (fw_config_probe(FW_CONFIG(SD, SD_GENSYS))) {
 		GPIO_PADBASED_OVERRIDE(padbased_table, x1slot_pads);
+		GPIO_PADBASED_OVERRIDE(padbased_table, x1slot_prsnt_pads);
+	} else if (fw_config_probe(FW_CONFIG(SD, SD_BAYHUB))) {
+		GPIO_PADBASED_OVERRIDE(padbased_table, x1slot_pads);
+		GPIO_PADBASED_OVERRIDE(padbased_table, x1slot_clkreq_pads);
+	} else {
+		GPIO_PADBASED_OVERRIDE(padbased_table, x1slot_disable_pads);
+	}
 
 	if (fw_config_probe(FW_CONFIG(TOUCHPAD, TOUCHPAD_LPSS_I2C))) {
 		GPIO_PADBASED_OVERRIDE(padbased_table, touchpad_lpss_i2c_enable_pads);
@@ -727,3 +785,9 @@ void fw_config_gpio_padbased_override(struct pad_config *padbased_table)
 		GPIO_PADBASED_OVERRIDE(padbased_table, fp_disable_pads);
 	}
 }
+
+void fw_config_post_gpio_configure(void)
+{
+	if (!fw_config_probe(FW_CONFIG(SD, SD_NONE)))
+		GPIO_CONFIGURE_PADS(post_x1slot_pads);
+}
diff --git a/src/mainboard/google/fatcat/variants/fatcat/gpio.c b/src/mainboard/google/fatcat/variants/fatcat/gpio.c
index 59dbe23680..696fb8ba4d 100644
--- a/src/mainboard/google/fatcat/variants/fatcat/gpio.c
+++ b/src/mainboard/google/fatcat/variants/fatcat/gpio.c
@@ -28,6 +28,8 @@ static const struct pad_config gpio_table[] = {
 	/* GPP_A06:     ESPI_RST_EC_R_N */
 	/*  GPP_A06 : GPP_A06 ==> ESPI_RST_HDR configured on reset, do not touch */
 
+	/* GPP_A08:     X1_PCIE_SLOT_PWR_EN */
+	/* NOTE: x1 slot power will be updated according to SD fw_config */
 	/* GPP_A09:     M.2_WWAN_FCP_OFF_N */
 	PAD_CFG_GPO(GPP_A09, 1, PLTRST),
 	/* GPP_A10:     M.2_WWAN_DISABLE_N */
@@ -81,7 +83,8 @@ static const struct pad_config gpio_table[] = {
 	PAD_CFG_GPO(GPP_B21, 0, DEEP),
 	/* GPP_B24:     ESPI_ALERT0_EC_R_N */
 	PAD_NC(GPP_B24, NONE),
-
+	/* GPP_B25:     X1_SLOT_WAKE_N */
+	/* NOTE: x1 slot wake will be overridden according to SD fw_config */
 	/* GPP_C00:     GPP_C0_SMBCLK */
 	PAD_CFG_NF(GPP_C00, NONE, DEEP, NF1),
 	/* GPP_C01:     GPP_C1_SMBDATA */
@@ -101,7 +104,7 @@ static const struct pad_config gpio_table[] = {
 	/* GPP_C10:     CLKREQ1_X4_GEN5_M2_SSD_N */
 	PAD_CFG_NF(GPP_C10, NONE, DEEP, NF1),
 	/* GPP_C11:     CLKREQ2_X1_GEN4_DT_CEM_SLOT_N */
-	PAD_CFG_NF(GPP_C11, NONE, DEEP, NF1),
+	/* NOTE: x1 slot clkreq will be overridden according to SD fw_config */
 	/* GPP_C12:     CLKREQ3_X1_GEN1_GBE_LAN_N */
 	PAD_CFG_NF(GPP_C12, NONE, DEEP, NF1),
 	/* GPP_C13:     CLKREQ4_X1_GEN4_M2_WLAN_N */
@@ -159,6 +162,8 @@ static const struct pad_config gpio_table[] = {
 	PAD_CFG_NF(GPP_D17, NONE, DEEP, NF1),
 	/* GPP_D18:     CLKREQ6_X4_GEN4_M2_SSD_N */
 	PAD_CFG_NF(GPP_D18, NONE, DEEP, NF1),
+	/* GPP_D19:     X1_DT_PCIE_RST_N */
+	/* NOTE: X1 PERST will follow power sequence according to SD fw_config */
 	/* GPP_D20:     CSE_EARLY_SW */
 	PAD_CFG_GPI_SCI_HIGH(GPP_D20, NONE, DEEP, LEVEL),
 	/* GPP_D21:     NC */
@@ -363,8 +368,6 @@ static const struct pad_config early_gpio_table[] = {
 
 /* Pad configuration in romstage */
 static const struct pad_config romstage_gpio_table[] = {
-	/* GPP_A08:     X1_PCIE_SLOT_PWR_EN */
-	PAD_CFG_GPO(GPP_A08, 0, PLTRST),
 	/* GPP_C00:     GPP_C0_SMBCLK */
 	PAD_CFG_NF(GPP_C00, NONE, DEEP, NF1),
 	/* GPP_C01:     GPP_C1_SMBDATA */
diff --git a/src/mainboard/google/fatcat/variants/fatcat/overridetree.cb b/src/mainboard/google/fatcat/variants/fatcat/overridetree.cb
index db599a394b..5ad0dc63c8 100644
--- a/src/mainboard/google/fatcat/variants/fatcat/overridetree.cb
+++ b/src/mainboard/google/fatcat/variants/fatcat/overridetree.cb
@@ -36,8 +36,8 @@ fw_config
 	end
 	field SD 13 14
 		option SD_NONE			0
-		option SD_GENSYS		1
-		option SD_BAYHUB		2
+		option SD_GENSYS		1	# use pin B17 as PRSNT2#
+		option SD_BAYHUB		2	# use pin B17 as ClkReq#
 	end
 	field STORAGE 15 16
 		option STORAGE_UNKNOWN		0
@@ -602,6 +602,10 @@ chip soc/intel/pantherlake
 			register "pcie_rp[PCIE_RP(3)]" = "{
 				.clk_src = 2,
 				.clk_req = 2,
+				/*
+				 * NOTE: The clock usage flag is changed to
+				 * PCIE_RP_CLK_REQ_UNUSED in variant.c when PRSNT#2 is used.
+				 */
 				.flags = PCIE_RP_CLK_REQ_DETECT | PCIE_RP_LTR | PCIE_RP_AER,
 			}"
 			chip soc/intel/common/block/pcie/rtd3
diff --git a/src/mainboard/google/fatcat/variants/fatcat/variant.c b/src/mainboard/google/fatcat/variants/fatcat/variant.c
index a8b5b4146d..cb42dfb3b0 100644
--- a/src/mainboard/google/fatcat/variants/fatcat/variant.c
+++ b/src/mainboard/google/fatcat/variants/fatcat/variant.c
@@ -75,6 +75,14 @@ void variant_update_soc_chip_config(struct soc_intel_pantherlake_config *config)
 			 */
 			config->thc_mode[0] = THC_HID_I2C_MODE;
 	}
+
+	/* x1 Slot */
+	if (fw_config_probe(FW_CONFIG(SD, SD_GENSYS))) {
+		uint8_t flags = config->pcie_rp[PCIE_RP(3)].flags;
+		flags &= ~(PCIE_RP_CLK_REQ_DETECT | PCIE_RP_CLK_REQ_UNUSED);
+		flags |= PCIE_RP_CLK_SRC_UNUSED;
+		config->pcie_rp[PCIE_RP(3)].flags = flags;
+	}
 }
 
 void variant_update_soc_memory_init_params(FSPM_UPD *memupd)

From c731fd720cf46d347f9b15502beba2284ad6699f Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Mon, 9 Feb 2026 09:00:39 -0600
Subject: [PATCH 3367/3886] lib/spd_bin: Add support for DDR5 SPD parsing

Without explicit DDR5 support, print_spd_info() was decoding DDR5 DIMMs
with the DDR4 SPD layout, so banks, ranks, rows, columns, and module
size were all displaying incorrect values.

Add DDR5-specific decoding in spd_bin.c using JESD400-5 byte positions.
Define these offsets in ddr5.h and branch in each getter when
dram_type is DDR5 so printed SPD info matches the actual module.

Fix printk reporting DIMM module size to only report "per channel" when
the DIMM actually contains multiple channels.

TEST=build/boot on out-of-tree board Erying SRMJ4 and Starlabs Starbook
MTL. Verify DIMM info printed in cbmem console is correct.

Change-Id: I7f418db3f89c67c2a71b2c327bb511a78faf7300
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91145
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/include/device/dram/ddr5.h |  9 ++++
 src/lib/spd_bin.c              | 77 ++++++++++++++++++++++++++++++----
 2 files changed, 77 insertions(+), 9 deletions(-)

diff --git a/src/include/device/dram/ddr5.h b/src/include/device/dram/ddr5.h
index 78d18b24f8..ba048f6cb3 100644
--- a/src/include/device/dram/ddr5.h
+++ b/src/include/device/dram/ddr5.h
@@ -15,6 +15,15 @@
 /** Maximum SPD size supported */
 #define SPD_SIZE_MAX_DDR5	1024
 
+/* DDR5 SPD byte offsets */
+#define DDR5_SPD_DENSITY_PACKAGE	4
+#define DDR5_SPD_ADDRESSING		5
+#define DDR5_SPD_IO_WIDTH		6
+#define DDR5_SPD_BANKS			7
+#define DDR5_SPD_MODULE_ORG		234
+#define DDR5_SPD_CHANNEL_BUS_WIDTH	235
+#define DDR5_SPD_MIN_LEN		236
+
 enum spd_dimm_type_ddr5 {
 	SPD_DDR5_DIMM_TYPE_RDIMM = 0x01,
 	SPD_DDR5_DIMM_TYPE_UDIMM = 0x02,
diff --git a/src/lib/spd_bin.c b/src/lib/spd_bin.c
index e3108cbcfd..2f387f38ea 100644
--- a/src/lib/spd_bin.c
+++ b/src/lib/spd_bin.c
@@ -4,11 +4,18 @@
 #include <console/console.h>
 #include <device/dram/ddr3.h>
 #include <device/dram/ddr4.h>
+#include <device/dram/ddr5.h>
 #include <memory_info.h>
 #include <spd.h>
 #include <spd_bin.h>
+#include <stdbool.h>
 #include <string.h>
 
+static bool is_ddr5(int dram_type)
+{
+	return dram_type == SPD_MEMORY_TYPE_DDR5_SDRAM;
+}
+
 void dump_spd_info(struct spd_block *blk)
 {
 	u8 i;
@@ -76,8 +83,14 @@ static int spd_get_banks(const uint8_t spd[], int dram_type)
 {
 	static const int ddr3_banks[4] = { 8, 16, 32, 64 };
 	static const int ddr4_banks[10] = { 4, 8, -1, -1, 8, 16, -1, -1, 16, 32 };
-	int index = (spd[SPD_DENSITY_BANKS] >> 4) & 0xf;
 
+	if (is_ddr5(dram_type)) {
+		/* DDR5 byte 7: BanksPerBG (bits 2:0) * BankGroups (bits 5:3) */
+		int banks_per_bg = 1 << (spd[DDR5_SPD_BANKS] & 7);
+		int bank_groups = 1 << ((spd[DDR5_SPD_BANKS] >> 3) & 7);
+		return banks_per_bg * bank_groups;
+	}
+	int index = (spd[SPD_DENSITY_BANKS] >> 4) & 0xf;
 	if (use_ddr4_params(dram_type)) {
 		if (index >= ARRAY_SIZE(ddr4_banks))
 			return -1;
@@ -89,8 +102,24 @@ static int spd_get_banks(const uint8_t spd[], int dram_type)
 	}
 }
 
-static int spd_get_capmb(const uint8_t spd[])
+static int spd_get_capmb(const uint8_t spd[], int dram_type)
 {
+	/*
+	 * DDR5: byte 4 = Density (5 bits, Gb per die) + DiePerPkg (3 bits).
+	 * Capacity in Mb per package.
+	 */
+	if (is_ddr5(dram_type)) {
+		static const uint8_t ddr5_density_gb[32] = {
+			0, 4, 8, 12, 16, 24, 32, 48, 64, 0, 0, 0, 0, 0, 0, 0,
+			0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
+		};
+		static const uint8_t ddr5_die_per_pkg[8] = { 1, 0, 2, 4, 8, 16, 0, 0 };
+		uint8_t density_gb = ddr5_density_gb[spd[DDR5_SPD_DENSITY_PACKAGE] & 0x1f];
+		uint8_t dies = ddr5_die_per_pkg[(spd[DDR5_SPD_DENSITY_PACKAGE] >> 5) & 7];
+		if (density_gb == 0 || dies == 0)
+			return -1;
+		return (int)density_gb * dies * 1024; /* Mb per package */
+	}
 	static const int spd_capmb[13] = { 1, 2, 4, 8, 16, 32, 64,
 					   128, 48, 96, 12, 24, 72 };
 	int index = spd[SPD_DENSITY_BANKS] & 0xf;
@@ -99,8 +128,12 @@ static int spd_get_capmb(const uint8_t spd[])
 	return spd_capmb[index] * 256;
 }
 
-static int spd_get_rows(const uint8_t spd[])
+static int spd_get_rows(const uint8_t spd[], int dram_type)
 {
+	if (is_ddr5(dram_type)) {
+		/* DDR5 byte 5 bits 7:3 = row address count; rows = 16 + value */
+		return 16 + ((spd[DDR5_SPD_ADDRESSING] >> 3) & 0x1f);
+	}
 	static const int spd_rows[7]  = { 12, 13, 14, 15, 16, 17, 18 };
 	int index = (spd[SPD_ADDRESSING] >> 3) & 7;
 	if (index >= ARRAY_SIZE(spd_rows))
@@ -108,8 +141,12 @@ static int spd_get_rows(const uint8_t spd[])
 	return spd_rows[index];
 }
 
-static int spd_get_cols(const uint8_t spd[])
+static int spd_get_cols(const uint8_t spd[], int dram_type)
 {
+	if (is_ddr5(dram_type)) {
+		/* DDR5 byte 5 bits 2:0 = column address count; cols = 10 + value */
+		return 10 + (spd[DDR5_SPD_ADDRESSING] & 7);
+	}
 	static const int spd_cols[4]  = { 9, 10, 11, 12 };
 	int index = spd[SPD_ADDRESSING] & 7;
 	if (index >= ARRAY_SIZE(spd_cols))
@@ -119,6 +156,10 @@ static int spd_get_cols(const uint8_t spd[])
 
 static int spd_get_ranks(const uint8_t spd[], int dram_type)
 {
+	if (is_ddr5(dram_type)) {
+		/* DDR5 byte 234 bits 5:3 = package ranks per channel; ranks = 1 + value */
+		return 1 + ((spd[DDR5_SPD_MODULE_ORG] >> 3) & 7);
+	}
 	static const int spd_ranks[8] = { 1, 2, 3, 4, 5, 6, 7, 8 };
 	int organ_offset = use_ddr4_params(dram_type) ? DDR4_ORGANIZATION
 						      : DDR3_ORGANIZATION;
@@ -130,6 +171,10 @@ static int spd_get_ranks(const uint8_t spd[], int dram_type)
 
 static int spd_get_devw(const uint8_t spd[], int dram_type)
 {
+	if (is_ddr5(dram_type)) {
+		/* DDR5 byte 6 bits 2:0 = SDRAM I/O width; 4 << value */
+		return 4 << (spd[DDR5_SPD_IO_WIDTH] & 7);
+	}
 	static const int spd_devw[4]  = { 4, 8, 16, 32 };
 	int organ_offset = use_ddr4_params(dram_type) ? DDR4_ORGANIZATION
 						      : DDR3_ORGANIZATION;
@@ -141,6 +186,10 @@ static int spd_get_devw(const uint8_t spd[], int dram_type)
 
 static int spd_get_busw(const uint8_t spd[], int dram_type)
 {
+	if (is_ddr5(dram_type)) {
+		/* DDR5 byte 235 bits 2:0 = primary bus width; 8 << value */
+		return 8 << (spd[DDR5_SPD_CHANNEL_BUS_WIDTH] & 7);
+	}
 	static const int spd_busw[4]  = { 8, 16, 32, 64 };
 	int busw_offset = use_ddr4_params(dram_type) ? DDR4_BUS_DEV_WIDTH
 						     : DDR3_BUS_DEV_WIDTH;
@@ -188,12 +237,14 @@ void print_spd_info(uint8_t spd[])
 	size_t len;
 	int type  = spd[SPD_MEMORY_TYPE];
 	int banks = spd_get_banks(spd, type);
-	int capmb = spd_get_capmb(spd);
-	int rows  = spd_get_rows(spd);
-	int cols  = spd_get_cols(spd);
+	int capmb = spd_get_capmb(spd, type);
+	int rows  = spd_get_rows(spd, type);
+	int cols  = spd_get_cols(spd, type);
 	int ranks = spd_get_ranks(spd, type);
 	int devw  = spd_get_devw(spd, type);
 	int busw  = spd_get_busw(spd, type);
+	int channels;
+	u32 size_mb;
 
 	/* Module type */
 	printk(BIOS_INFO, "SPD: module type is %s\n",
@@ -211,8 +262,16 @@ void print_spd_info(uint8_t spd[])
 
 	if (capmb > 0 && busw > 0 && devw > 0 && ranks > 0) {
 		/* SIZE = DENSITY / 8 * BUS_WIDTH / SDRAM_WIDTH * RANKS */
-		printk(BIOS_INFO, "SPD: module size is %u MB (per channel)\n",
-			capmb / 8 * busw / devw * ranks);
+		size_mb = (u32)capmb / 8 * busw / devw * ranks;
+		if (size_mb > 0) {
+			channels = 1 + (is_ddr5(type) ? ((spd[DDR5_SPD_CHANNEL_BUS_WIDTH] >> 5) & 3) : 0);
+			if (channels > 1) {
+				printk(BIOS_INFO, "SPD: module size is %u MB (%u MB per channel)\n",
+				       size_mb, size_mb / channels);
+				return;
+			}
+			printk(BIOS_INFO, "SPD: module size is %u MB\n", size_mb);
+		}
 	}
 }
 

From dec409e9a4b1dce0088e9d7702e50ac2081cd067 Mon Sep 17 00:00:00 2001
From: Patrick Rudolph <patrick.rudolph@9elements.com>
Date: Sat, 14 Feb 2026 09:25:44 +0100
Subject: [PATCH 3368/3886] payloads/external/edk2: Warn user about missing
 Kconfig option

Add a build time warning in case the DRIVERS_EFI_VARIABLE_STORE is not
selected, but UefiPayload will have a working firmware menu and will
write non-volatile variables into flash.

Without DRIVERS_EFI_VARIABLE_STORE coreboot will be fully functional,
but the settings made in the firmware menu have no effect at all.

Change-Id: Ib8872297d5d3451834f8ccfdaaee32f23727c178
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91230
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
---
 payloads/external/Makefile.mk | 15 +++++++++++++++
 1 file changed, 15 insertions(+)

diff --git a/payloads/external/Makefile.mk b/payloads/external/Makefile.mk
index a15ec2f378..429c0b2a85 100644
--- a/payloads/external/Makefile.mk
+++ b/payloads/external/Makefile.mk
@@ -161,6 +161,21 @@ ifeq ($(CONFIG_EDK2_ENABLE_IPXE),y)
 IPXE_EFI := payloads/external/iPXE/ipxe/ipxe.rom
 endif
 
+ifeq ($(CONFIG_PAYLOAD_EDK2)$(CONFIG_SMMSTORE_V2)$(CONFIG_DRIVERS_OPTION_CFR),yyy)
+ifeq ($(CONFIG_DRIVERS_EFI_VARIABLE_STORE),)
+show_notices:: warn_no_option_cfr_enabled
+
+PHONY+=warn_no_option_cfr_enabled
+warn_no_option_cfr_enabled:
+	printf "\n\t** WARNING **\n"
+	printf "edk2 has been configured to store non-volatile variables in the 'SMMSTORE'\n"
+	printf "flash area, and to show coreboot's setup option menu, but coreboot is not\n"
+	printf "configured to use variables stored by edk2 in the 'SMMSTORE' flash area.\n"
+	printf "coreboot-related changes made in edk2's setup menu will have no effect.\n"
+	printf "To fix this, select CONFIG_DRIVERS_EFI_VARIABLE_STORE.\n\n"
+endif
+endif
+
 $(obj)/UEFIPAYLOAD.fd: $(DOTCONFIG) $(IPXE_EFI)
 	$(MAKE) -C payloads/external/edk2 UefiPayloadPkg \
 		HOSTCC="$(HOSTCC)" \

From 3bb3188acd826b12a7f506c7917671dd4a094887 Mon Sep 17 00:00:00 2001
From: Patrick Rudolph <patrick.rudolph@9elements.com>
Date: Sat, 14 Feb 2026 09:48:55 +0100
Subject: [PATCH 3369/3886] mb/lenovo/x220: Select DRIVERS_OPTION_CFR_ENABLED

Automatically use the CFR driver when EDK2 payload and SMMSTORE
are enabled. Selects the UEFI variable option backend by default
when SMMSTORE is enabled.

Change-Id: Ib7cb122dc863d3449c670d1917ebdd2a0a6317d0
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91231
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
---
 src/mainboard/lenovo/x220/Kconfig | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/mainboard/lenovo/x220/Kconfig b/src/mainboard/lenovo/x220/Kconfig
index 8291965976..1fe5566ab4 100644
--- a/src/mainboard/lenovo/x220/Kconfig
+++ b/src/mainboard/lenovo/x220/Kconfig
@@ -30,7 +30,7 @@ config BOARD_SPECIFIC_OPTIONS
 	select SERIRQ_CONTINUOUS_MODE
 	select SOUTHBRIDGE_INTEL_C216
 	select SYSTEM_TYPE_LAPTOP
-
+	select DRIVERS_OPTION_CFR_ENABLED if PAYLOAD_EDK2 && SMMSTORE
 
 config VBOOT
 	select GBB_FLAG_DISABLE_EC_SOFTWARE_SYNC

From f530d37da736c190f475bbe7333932e612edf43f Mon Sep 17 00:00:00 2001
From: Patrick Rudolph <patrick.rudolph@9elements.com>
Date: Sat, 14 Feb 2026 18:35:58 +0100
Subject: [PATCH 3370/3886] mb/lenovo/x220: Add PCIe ports in CFR

Allow the user to disable PCIe ports that are not required.

Change-Id: Id2d7640255c347c768387408f27e9f5448cbef01
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91232
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
---
 src/mainboard/lenovo/x220/cfr.c       | 21 ++++++++++++++++++
 src/mainboard/lenovo/x220/mainboard.c | 32 +++++++++++++++++++++++++++
 src/southbridge/intel/bd82x6x/cfr.h   | 12 ++++++++++
 3 files changed, 65 insertions(+)

diff --git a/src/mainboard/lenovo/x220/cfr.c b/src/mainboard/lenovo/x220/cfr.c
index 6d43c17856..2ebfd32d77 100644
--- a/src/mainboard/lenovo/x220/cfr.c
+++ b/src/mainboard/lenovo/x220/cfr.c
@@ -8,6 +8,26 @@
 #include <northbridge/intel/sandybridge/cfr.h>
 #include <southbridge/intel/bd82x6x/cfr.h>
 
+GEN_RP_ENUM(1, "Wifi")
+#if CONFIG(BOARD_LENOVO_X220)
+GEN_RP_ENUM(3, "ExpressCard")
+#endif
+GEN_RP_ENUM(4, "SD Card Reader")
+GEN_RP_ENUM(6, "xHCI")
+
+static struct sm_obj_form pcie = {
+	.ui_name = "PCH PCIe",
+	.obj_list = (const struct sm_object *[]) {
+		&pcie_rp1,
+#if CONFIG(BOARD_LENOVO_X220)
+		&pcie_rp3,
+#endif
+		&pcie_rp4,
+		&pcie_rp6,
+		NULL
+	},
+};
+
 static struct sm_obj_form ec = {
 	.ui_name = "Embedded Controller",
 	.obj_list = (const struct sm_object *[]) {
@@ -49,6 +69,7 @@ static struct sm_obj_form *sm_root[] = {
 	&system,
 	&power,
 	&ec,
+	&pcie,
 	NULL
 };
 
diff --git a/src/mainboard/lenovo/x220/mainboard.c b/src/mainboard/lenovo/x220/mainboard.c
index 50c944e341..92e4b8e12e 100644
--- a/src/mainboard/lenovo/x220/mainboard.c
+++ b/src/mainboard/lenovo/x220/mainboard.c
@@ -1,7 +1,11 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
 #include <device/device.h>
+#include <device/pci_def.h>
 #include <drivers/intel/gma/int15.h>
+#include <option.h>
+#include <southbridge/intel/bd82x6x/pch.h>
+#include <stdio.h>
 
 static void mainboard_enable(struct device *dev)
 {
@@ -10,6 +14,34 @@ static void mainboard_enable(struct device *dev)
 					GMA_INT15_BOOT_DISPLAY_DEFAULT, 0);
 }
 
+static void mainboard_init(void *chip_info)
+{
+	char option[20];
+
+	/* Apply user config and disable ports if option exists and is 0 */
+	for (struct device *dev = all_devices; dev; dev = dev->next) {
+		/* Only care about PCH PCIe root ports */
+		if (PCI_SLOT(dev->path.pci.devfn) !=
+		    PCH_PCIE_DEV_SLOT)
+			continue;
+		/*
+		 * Only care about ports enabled at this point. Ports that are
+		 * disabled here are not implemented on this mainboard.
+		 */
+		if (!dev->enabled)
+			continue;
+
+		const unsigned int idx = PCI_FUNC(dev->path.pci.devfn);
+		snprintf(option, sizeof(option), "pch_pcie_enable_rp%u", idx);
+
+		/* When option is not found keep current configuration */
+		dev->enabled = get_uint_option(option, dev->enabled);
+		printk(BIOS_DEBUG, "%s: %s %sabled\n", __func__, dev_path(dev),
+		       dev->enabled ? "en" : "dis");
+	}
+}
+
 struct chip_operations mainboard_ops = {
+	.init = mainboard_init,
 	.enable_dev = mainboard_enable,
 };
diff --git a/src/southbridge/intel/bd82x6x/cfr.h b/src/southbridge/intel/bd82x6x/cfr.h
index 8b9f928f34..d70650463a 100644
--- a/src/southbridge/intel/bd82x6x/cfr.h
+++ b/src/southbridge/intel/bd82x6x/cfr.h
@@ -11,6 +11,18 @@
 #include <southbridge/intel/common/pmutil.h>
 #include "me.h"
 
+#define GEN_RP_ENUM(x, y)					\
+static const struct sm_object pcie_rp##x = SM_DECLARE_ENUM({	\
+	.opt_name	= "pch_pcie_enable_rp"#x,		\
+	.ui_name	= y,					\
+	.ui_helptext	= "Enable or disable "#y,		\
+	.default_value	= 1,					\
+	.values		= (const struct sm_enum_value[]) {	\
+		{ "Disabled",	0	},			\
+		{ "Enabled",	1	},			\
+		SM_ENUM_VALUE_END	},			\
+});
+
 /* Power state after power loss */
 static const struct sm_object power_on_after_fail = SM_DECLARE_ENUM({
 	.opt_name	= "power_on_after_fail",

From 3a6298ad8584847fa1d165bf4cc2345c6ed6db95 Mon Sep 17 00:00:00 2001
From: Patrick Rudolph <patrick.rudolph@9elements.com>
Date: Sun, 15 Feb 2026 08:37:42 +0100
Subject: [PATCH 3371/3886] mb/lenovo/x220: Correct USB port config

- Drop USB OC2#, OC3#, OC4#, OC6#
  Those are either pulled high or used as GPIO and used by internal
  devices only.
- Disable Port 4, 6, 7. They are unused.
- Add comments with devices connected.

TEST=On Lenovo x220 the USB ports P00, P01, P02, P03, P08, P09, P11,
     P13 are still working.

Change-Id: I00b0a36a80b812adb9a4ee976dabb528afd36409
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91233
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 .../lenovo/x220/variants/x220/overridetree.cb | 28 +++++++++----------
 1 file changed, 14 insertions(+), 14 deletions(-)

diff --git a/src/mainboard/lenovo/x220/variants/x220/overridetree.cb b/src/mainboard/lenovo/x220/variants/x220/overridetree.cb
index 626f7eb3a6..7aed10d4bf 100644
--- a/src/mainboard/lenovo/x220/variants/x220/overridetree.cb
+++ b/src/mainboard/lenovo/x220/variants/x220/overridetree.cb
@@ -2,20 +2,20 @@ chip northbridge/intel/sandybridge
 	device domain 0 on
 		chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH
 			register "usb_port_config" = "{
-				{1, 0, 0 },
-				{1, 1, 1 },
-				{1, 1, 3 },
-				{1, 1, 3 },
-				{1, 1, -1},
-				{1, 1, -1},
-				{1, 0, 2 },
-				{1, 0, 2 },
-				{1, 1, 6 },
-				{1, 1, 5 },
-				{1, 1, 6 },
-				{1, 1, 6 },
-				{1, 1, 7 },
-				{1, 1, 6 },
+				{1, 0, 0 },  /* P00: System Port (near VGA) */
+				{1, 1, 1 },  /* P01: System Port (near ExpressCard) */
+				{1, 1, -1 }, /* P02: WLAN */
+				{1, 1, -1 }, /* P03: WWAN */
+				{0, 0, -1},  /* P04: Reserved */
+				{1, 1, -1},  /* P05: ExpressCard */
+				{0, 0, -1},  /* P06: Reserved */
+				{0, 0, -1 }, /* P07: Reserved */
+				{1, 1, -1 }, /* P08: Docking */
+				{1, 1, 5 },  /* P09: Always On System Port */
+				{1, 1, -1 }, /* P10: FPR */
+				{1, 1, -1 }, /* P11: BDC */
+				{1, 1, 7 },  /* P12: Docking */
+				{1, 1, -1 }, /* P13: Camera */
 			}"
 
 			device ref lpc on

From 4e6c9f5954b18e4054e7f872d3173c2480fa3a5b Mon Sep 17 00:00:00 2001
From: Patrick Rudolph <patrick.rudolph@9elements.com>
Date: Sat, 17 Jan 2026 17:55:57 +0100
Subject: [PATCH 3372/3886] sb/intel/bd82x6x/early_usb: Add mainboard hook for
 USB devices

Allow the mainboard code to disable USB ports based on GPIO straps,
SKU or user configuration. The mainboard code must implement
mb_usb20_port_override() in romstage to disable USB ports. Ports
that are statically disabled in devicetree cannot be enabled
using this method.

Change-Id: I0fd01e12c05d633695a5fb19ff804e9dc588d6ed
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91234
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
---
 src/southbridge/intel/bd82x6x/early_usb.c     | 11 ++++++++++-
 src/southbridge/intel/bd82x6x/early_usb_mrc.c | 12 +++++++++++-
 src/southbridge/intel/bd82x6x/pch.h           |  3 +++
 3 files changed, 24 insertions(+), 2 deletions(-)

diff --git a/src/southbridge/intel/bd82x6x/early_usb.c b/src/southbridge/intel/bd82x6x/early_usb.c
index 7bca0bbc49..50b66d5acf 100644
--- a/src/southbridge/intel/bd82x6x/early_usb.c
+++ b/src/southbridge/intel/bd82x6x/early_usb.c
@@ -10,6 +10,11 @@
 #include "pch.h"
 #include "chip.h"
 
+__weak uint16_t mb_usb20_port_override(void)
+{
+	return 0x3fff;
+}
+
 void early_usb_init(void)
 {
 	u32 reg32;
@@ -68,7 +73,11 @@ void early_usb_init(void)
 	for (i = 0; i < 14; i++)
 		if (!portmap[i].enabled)
 			reg32 |= (1 << i);
-	RCBA32(USBPDO) = reg32;
+
+	/* Allow mainboard to disable ports based on SKU or user config */
+	reg32 |= ~mb_usb20_port_override();
+
+	RCBA32(USBPDO) = reg32 & 0x3fff;
 	reg32 = 0;
 	for (i = 0; i < 8; i++)
 		if (portmap[i].enabled && portmap[i].oc_pin >= 0)
diff --git a/src/southbridge/intel/bd82x6x/early_usb_mrc.c b/src/southbridge/intel/bd82x6x/early_usb_mrc.c
index bf43e263a4..e12ade0287 100644
--- a/src/southbridge/intel/bd82x6x/early_usb_mrc.c
+++ b/src/southbridge/intel/bd82x6x/early_usb_mrc.c
@@ -32,6 +32,11 @@ void enable_usb_bar(void)
 	pci_or_config16(usb1, PCI_COMMAND, PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY);
 }
 
+__weak uint16_t mb_usb20_port_override(void)
+{
+	return 0x3fff;
+}
+
 /*
  * Translate coreboot native USB port configuration in devicetree
  * into a format reference code expects:
@@ -64,6 +69,10 @@ void southbridge_fill_pei_data(struct pei_data *pei_data)
 	const uint16_t currents[] = { 0x40, 0x80, 0x130,
 				      0, 0, 0, /* 3-5 not seen in MRC */
 				      0x40, 0x130, 0x40, 0x80};
+
+	/* Allow mainboard to disable ports based on SKU or user config */
+	u16 mb_usb20_enable = mb_usb20_port_override();
+
 	for (unsigned int port = 0; port < ARRAY_SIZE(config->usb_port_config); port++) {
 		uint16_t current = 0;
 		int ocp = config->usb_port_config[port].oc_pin;
@@ -84,7 +93,8 @@ void southbridge_fill_pei_data(struct pei_data *pei_data)
 			       __func__, port, config->usb_port_config[port].current);
 		}
 
-		pei_data->usb_port_config[port][0] = config->usb_port_config[port].enabled;
+		pei_data->usb_port_config[port][0] = config->usb_port_config[port].enabled &&
+						     (mb_usb20_enable & BIT(port));
 		pei_data->usb_port_config[port][1] = ocp;
 		pei_data->usb_port_config[port][2] = current;
 	}
diff --git a/src/southbridge/intel/bd82x6x/pch.h b/src/southbridge/intel/bd82x6x/pch.h
index 2fb97f0d60..534251d5e8 100644
--- a/src/southbridge/intel/bd82x6x/pch.h
+++ b/src/southbridge/intel/bd82x6x/pch.h
@@ -39,6 +39,9 @@ bool pch_is_mobile(void);
 void pch_iobp_update(u32 address, u32 andvalue, u32 orvalue);
 
 void enable_usb_bar(void);
+/* Optional mainboard hook to do disable additional USB ports
+   based on SKU or user configuration. Set bit to 0 to disable port. */
+uint16_t mb_usb20_port_override(void);
 
 void early_thermal_init(void);
 void southbridge_configure_default_intmap(void);

From 968c60c0d934f16c9961a4417545762aaf85ac67 Mon Sep 17 00:00:00 2001
From: Subrata Banik <subratabanik@google.com>
Date: Tue, 17 Feb 2026 00:33:35 +0530
Subject: [PATCH 3373/3886] mb/google/bluey: Check for battery presence in
 off-mode charging

Verify that a battery is actually present before setting the boot
mode to LB_BOOT_MODE_OFFMODE_CHARGING. This prevents the system
from incorrectly entering a charging state when running on AC power
without a battery connected.

TEST=Build and boot on bluey with and without battery present.
Verify boot mode transitions correctly.

Change-Id: I67098bc06b34c25429daf516f3891c50930209fe
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91290
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
---
 src/mainboard/google/bluey/romstage.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/mainboard/google/bluey/romstage.c b/src/mainboard/google/bluey/romstage.c
index a357f6d3d5..a3806668b7 100644
--- a/src/mainboard/google/bluey/romstage.c
+++ b/src/mainboard/google/bluey/romstage.c
@@ -40,7 +40,7 @@ static enum boot_mode_t set_boot_mode(void)
 
 	enum boot_mode_t boot_mode_new;
 
-	if (is_off_mode()) {
+	if (is_off_mode() && google_chromeec_is_battery_present()) {
 		boot_mode_new = LB_BOOT_MODE_OFFMODE_CHARGING;
 	} else if (google_chromeec_is_below_critical_threshold()) {
 		if (google_chromeec_is_charger_present())

From 7239385f5e028ab93d4944cb1de81a856432423d Mon Sep 17 00:00:00 2001
From: Enzo Potenza <enzo.potenza@gmail.com>
Date: Thu, 25 Sep 2025 11:55:07 +0200
Subject: [PATCH 3374/3886] mb/qotom/qdnv01: Add CRB using intel/harcuvar
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Mainboard features:
- Intel Atom C3758R SoC, passive heatsink
- DDR4 ECC, 2x SO-DIMM
- 4x 10 GbE (SFP+), Intel X553
- 5x 2.5 GbE (RJ-45), Intel i226
- 2× M.2 (PCIe 3.0 × 2)
- 2x SATA connector
- 1× Serial on RJ-45
- 2x USB3.0, 1x USB2.0
- 1x VGA on AST2400
- 1× Mini SAS (SFF8087)

Tested:
- booted with EDK2 payload
- all devices are recognized correctly

Not working:
- VGA pre OS
- PC speaker

Untested:
- mini SAS (lack of hardware for it)
- special M.2 for 4G/5G (lack of hardware for it)

Change-Id: Idb814ab8b02d85730bf072f57368bbf2ccefc19b
Signed-off-by: Enzo Potenza <enzo.potenza@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89346
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
---
 configs/config.qotom_qdnv01                   |   5 +
 src/mainboard/qotom/Kconfig                   |  17 +
 src/mainboard/qotom/Kconfig.name              |   4 +
 src/mainboard/qotom/qdnv01/Kconfig            |  23 +
 src/mainboard/qotom/qdnv01/Kconfig.name       |   4 +
 src/mainboard/qotom/qdnv01/Makefile.mk        |  10 +
 src/mainboard/qotom/qdnv01/acpi/mainboard.asl |   3 +
 .../qotom/qdnv01/acpi/mainboard_pci_irqs.asl  | 173 +++++
 src/mainboard/qotom/qdnv01/acpi/platform.asl  |  16 +
 src/mainboard/qotom/qdnv01/acpi_tables.c      |   8 +
 src/mainboard/qotom/qdnv01/board_info.txt     |   6 +
 src/mainboard/qotom/qdnv01/bootblock.c        |   9 +
 src/mainboard/qotom/qdnv01/devicetree.cb      |  78 +++
 src/mainboard/qotom/qdnv01/dsdt.asl           |  32 +
 src/mainboard/qotom/qdnv01/gpio.h             | 622 ++++++++++++++++++
 src/mainboard/qotom/qdnv01/hsio.c             | 253 +++++++
 src/mainboard/qotom/qdnv01/ramstage.c         |   9 +
 src/mainboard/qotom/qdnv01/romstage.c         |  37 ++
 18 files changed, 1309 insertions(+)
 create mode 100644 configs/config.qotom_qdnv01
 create mode 100644 src/mainboard/qotom/Kconfig
 create mode 100644 src/mainboard/qotom/Kconfig.name
 create mode 100644 src/mainboard/qotom/qdnv01/Kconfig
 create mode 100644 src/mainboard/qotom/qdnv01/Kconfig.name
 create mode 100644 src/mainboard/qotom/qdnv01/Makefile.mk
 create mode 100644 src/mainboard/qotom/qdnv01/acpi/mainboard.asl
 create mode 100644 src/mainboard/qotom/qdnv01/acpi/mainboard_pci_irqs.asl
 create mode 100644 src/mainboard/qotom/qdnv01/acpi/platform.asl
 create mode 100644 src/mainboard/qotom/qdnv01/acpi_tables.c
 create mode 100644 src/mainboard/qotom/qdnv01/board_info.txt
 create mode 100644 src/mainboard/qotom/qdnv01/bootblock.c
 create mode 100644 src/mainboard/qotom/qdnv01/devicetree.cb
 create mode 100644 src/mainboard/qotom/qdnv01/dsdt.asl
 create mode 100644 src/mainboard/qotom/qdnv01/gpio.h
 create mode 100644 src/mainboard/qotom/qdnv01/hsio.c
 create mode 100644 src/mainboard/qotom/qdnv01/ramstage.c
 create mode 100644 src/mainboard/qotom/qdnv01/romstage.c

diff --git a/configs/config.qotom_qdnv01 b/configs/config.qotom_qdnv01
new file mode 100644
index 0000000000..1042ec6de4
--- /dev/null
+++ b/configs/config.qotom_qdnv01
@@ -0,0 +1,5 @@
+CONFIG_VENDOR_QOTOM=y
+CONFIG_MAINBOARD_PART_NUMBER="Qotom QDNV01"
+CONFIG_ENABLE_HSUART=y
+CONFIG_USE_DENVERTON_NS_FSP_CAR=y
+# CONFIG_SMMSTORE is not set
diff --git a/src/mainboard/qotom/Kconfig b/src/mainboard/qotom/Kconfig
new file mode 100644
index 0000000000..066df4af96
--- /dev/null
+++ b/src/mainboard/qotom/Kconfig
@@ -0,0 +1,17 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
+if VENDOR_QOTOM
+
+choice
+	prompt "Mainboard model"
+
+source "src/mainboard/qotom/*/Kconfig.name"
+
+endchoice
+
+source "src/mainboard/qotom/*/Kconfig"
+
+config MAINBOARD_VENDOR
+	default "Qotom"
+
+endif # VENDOR_QOTOM
diff --git a/src/mainboard/qotom/Kconfig.name b/src/mainboard/qotom/Kconfig.name
new file mode 100644
index 0000000000..c20833d139
--- /dev/null
+++ b/src/mainboard/qotom/Kconfig.name
@@ -0,0 +1,4 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
+config VENDOR_QOTOM
+	bool "Qotom"
diff --git a/src/mainboard/qotom/qdnv01/Kconfig b/src/mainboard/qotom/qdnv01/Kconfig
new file mode 100644
index 0000000000..269cee07d1
--- /dev/null
+++ b/src/mainboard/qotom/qdnv01/Kconfig
@@ -0,0 +1,23 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
+if BOARD_QOTOM_QDNV01
+
+config BOARD_SPECIFIC_OPTIONS
+	def_bool y
+	select SOC_INTEL_DENVERTON_NS
+	select BOARD_ROMSIZE_KB_16384
+	select HAVE_ACPI_TABLES
+	select DRIVERS_ASPEED_AST2050
+	select MAINBOARD_USES_IFD_10GBE_0_REGION
+	select MAINBOARD_USES_IFD_10GBE_1_REGION
+
+config MAINBOARD_DIR
+	default "qotom/qdnv01"
+
+config MAINBOARD_PART_NUMBER
+	default "QDNV01"
+
+config CBFS_SIZE
+	default 0x800000
+
+endif # BOARD_QOTOM_QDNV01
diff --git a/src/mainboard/qotom/qdnv01/Kconfig.name b/src/mainboard/qotom/qdnv01/Kconfig.name
new file mode 100644
index 0000000000..a3a2270c3b
--- /dev/null
+++ b/src/mainboard/qotom/qdnv01/Kconfig.name
@@ -0,0 +1,4 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
+config BOARD_QOTOM_QDNV01
+	bool "QDNV01"
diff --git a/src/mainboard/qotom/qdnv01/Makefile.mk b/src/mainboard/qotom/qdnv01/Makefile.mk
new file mode 100644
index 0000000000..8917ff6f64
--- /dev/null
+++ b/src/mainboard/qotom/qdnv01/Makefile.mk
@@ -0,0 +1,10 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
+bootblock-y += bootblock.c
+
+romstage-y += hsio.c
+
+ramstage-y += ramstage.c
+ramstage-y += hsio.c
+
+CPPFLAGS_common += -Isrc/mainboard/$(MAINBOARDDIR)/
diff --git a/src/mainboard/qotom/qdnv01/acpi/mainboard.asl b/src/mainboard/qotom/qdnv01/acpi/mainboard.asl
new file mode 100644
index 0000000000..16990d45f4
--- /dev/null
+++ b/src/mainboard/qotom/qdnv01/acpi/mainboard.asl
@@ -0,0 +1,3 @@
+/* SPDX-License-Identifier: CC-PDDC */
+
+/* Please update the license if adding licensable material. */
diff --git a/src/mainboard/qotom/qdnv01/acpi/mainboard_pci_irqs.asl b/src/mainboard/qotom/qdnv01/acpi/mainboard_pci_irqs.asl
new file mode 100644
index 0000000000..3482e23761
--- /dev/null
+++ b/src/mainboard/qotom/qdnv01/acpi/mainboard_pci_irqs.asl
@@ -0,0 +1,173 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+/* This is board specific information: IRQ routing */
+
+// PCI Interrupt Routing
+Method(_PRT)
+{
+	If (PICM) {
+		Return (Package() {
+			// [GREG]: Global Registers
+			Package() { 0x0004ffff, 0, 0, 16 },
+
+			// [RCEC]: Root Complex Event Collector
+			Package() { 0x0005ffff, 0, 0, 23 },
+
+			// [VRP2]: Virtual root port 2
+			Package() { 0x0006ffff, 2, 0, 18 },
+
+			// [PEX0]: PCI Express Port 0
+			Package() { 0x0009ffff, 0, 0, 16 },
+
+			// [PEX1]: PCI Express Port 1
+			Package() { 0x000affff, 1, 0, 17 },
+
+			// [PEX2]: PCI Express Port 2
+			Package() { 0x000bffff, 2, 0, 18 },
+
+			// [PEX3]: PCI Express Port 3
+			Package() { 0x000cffff, 3, 0, 19 },
+
+			// [PEX4]: PCI Express Port 4
+			Package() { 0x000effff, 0, 0, 20 },
+
+			// [PEX5]: PCI Express Port 5
+			Package() { 0x000fffff, 1, 0, 21 },
+
+			// [PEX6]: PCI Express Port 6
+			Package() { 0x0010ffff, 2, 0, 22 },
+
+			// [PEX7]: PCI Express Port 7
+			Package() { 0x0011ffff, 3, 0, 23 },
+
+			// [SMB1]: SMBus controller
+			Package() { 0x0012ffff, 0, 0, 16 },
+
+			// [SAT0]: SATA controller 0
+			Package() { 0x0013ffff, 0, 0, 20 },
+
+			// [SAT1]: SATA controller 1
+			Package() { 0x0014ffff, 0, 0, 21 },
+
+			// [XHC0]: XHCI USB controller
+			Package() { 0x0015ffff, 0, 0, 19 },
+
+			// [VRP0]: Virtual root port 0
+			Package() { 0x0016ffff, 0, 0, 16 },
+
+			// [VRP1]: Virtual root port 1
+			Package() { 0x0017ffff, 1, 0, 17 },
+
+			// [HECI]: ME HECI
+			Package() { 0x0018ffff, 0, 0, 16 },
+
+			// [HEC2]: ME HECI2
+			Package() { 0x0018ffff, 1, 0, 17 },
+
+			// [MEKT]: MEKT on PCH
+			Package() { 0x0018ffff, 2, 0, 18 },
+
+			// [HEC3]: ME HECI3
+			Package() { 0x0018ffff, 3, 0, 19 },
+
+			// [UAR0]: UART 0
+			Package() { 0x001affff, 0, 0, 16 },
+
+			// [UAR1]: UART 1
+			Package() { 0x001affff, 1, 0, 17 },
+
+			// [UAR2]: UART 2
+			Package() { 0x001affff, 2, 0, 18 },
+
+			// [EMMC]: eMMC
+			Package() { 0x001cffff, 0, 0, 16 },
+
+			// [P2SB]: Primary to sideband bridge
+			// [SMB0]: SMBus controller
+			// [NPK0]: Northpeak DFX
+			Package() { 0x001fffff, 0, 0, 23 },
+		})
+	} Else {
+		Return (Package() {
+			// [GREG]: Global Registers		0:4.0
+			Package() { 0x0004ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
+
+			// [RCEC]: Root Complex Event Collector		0:5.0
+			Package() { 0x0005ffff, 0, \_SB.PCI0.LPCB.LNKH, 0 },
+
+			// [VRP2]: Virtual root port 2		0:6.0
+			Package() { 0x0006ffff, 2, \_SB.PCI0.LPCB.LNKC, 0 },
+
+			// [PEX0]: PCI Express Port 0		0:9.0
+			Package() { 0x0009ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
+
+			// [PEX1]: PCI Express Port 1		0:a.0
+			Package() { 0x000affff, 1, \_SB.PCI0.LPCB.LNKB, 0 },
+
+			// [PEX2]: PCI Express Port 2		0:b.0
+			Package() { 0x000bffff, 2, \_SB.PCI0.LPCB.LNKC, 0 },
+
+			// [PEX3]: PCI Express Port 3		0:c.0
+			Package() { 0x000cffff, 3, \_SB.PCI0.LPCB.LNKD, 0 },
+
+			// [PEX4]: PCI Express Port 4		0:e.0
+			Package() { 0x000effff, 0, \_SB.PCI0.LPCB.LNKE, 0 },
+
+			// [PEX5]: PCI Express Port 5		0:f.0
+			Package() { 0x000fffff, 1, \_SB.PCI0.LPCB.LNKF, 0 },
+
+			// [PEX6]: PCI Express Port 6		0:10.0
+			Package() { 0x0010ffff, 2, \_SB.PCI0.LPCB.LNKG, 0 },
+
+			// [PEX7]: PCI Express Port 7		0:11.0
+			Package() { 0x0011ffff, 3, \_SB.PCI0.LPCB.LNKH, 0 },
+
+			// [SMB1]: SMBus controller		0:12.0
+			Package() { 0x0012ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
+
+			// [SAT0]: SATA controller 0		0:13.0
+			Package() { 0x0013ffff, 0, \_SB.PCI0.LPCB.LNKE, 0 },
+
+			// [SAT1]: SATA controller 1		0:14.0
+			Package() { 0x0014ffff, 0, \_SB.PCI0.LPCB.LNKF, 0 },
+
+			// [XHC0]: XHCI USB controller		0:15.0
+			Package() { 0x0015ffff, 0, \_SB.PCI0.LPCB.LNKD, 0 },
+
+			// [VRP0]: Virtual root port 0		0:16.0
+			Package() { 0x0016ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
+
+			// [VRP1]: Virtual root port 1		0:17.0
+			Package() { 0x0017ffff, 1, \_SB.PCI0.LPCB.LNKB, 0 },
+
+			// [HECI]: ME HECI		0:18.0
+			Package() { 0x0018ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
+
+			// [HEC2]: ME HECI2		0:18.1
+			Package() { 0x0018ffff, 1, \_SB.PCI0.LPCB.LNKB, 0 },
+
+			// [MEKT]: MEKT on PCH		0:18.2
+			Package() { 0x0018ffff, 2, \_SB.PCI0.LPCB.LNKC, 0 },
+
+			// [HEC3]: ME HECI3		0:18.3
+			Package() { 0x0018ffff, 3, \_SB.PCI0.LPCB.LNKD, 0 },
+
+			// [UAR0]: UART 0		0:1a.0
+			Package() { 0x001affff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
+
+			// [UAR1]: UART 1		0:1a.1
+			Package() { 0x001affff, 1, \_SB.PCI0.LPCB.LNKB, 0 },
+
+			// [UAR2]: UART 2		0:1a.2
+			Package() { 0x001affff, 2, \_SB.PCI0.LPCB.LNKC, 0 },
+
+			// [EMMC]: eMMC		0:1c.0
+			Package() { 0x001cffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
+
+			// [P2SB]: Primary to sideband bridge
+			// [SMB0]: SMBus controller
+			// [NPK0]: Northpeak DFX
+			Package() { 0x001ffffF, 0, \_SB.PCI0.LPCB.LNKH, 0 },
+		})
+	}
+}
diff --git a/src/mainboard/qotom/qdnv01/acpi/platform.asl b/src/mainboard/qotom/qdnv01/acpi/platform.asl
new file mode 100644
index 0000000000..bbee0a2787
--- /dev/null
+++ b/src/mainboard/qotom/qdnv01/acpi/platform.asl
@@ -0,0 +1,16 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+/* The _PTS method (Prepare To Sleep) is called before the OS is
+ * entering a sleep state. The sleep state number is passed in Arg0
+ */
+
+Method(_PTS,1)
+{
+}
+
+/* The _WAK method is called on system wakeup */
+
+Method(_WAK,1)
+{
+	Return(Package(){0,0})
+}
diff --git a/src/mainboard/qotom/qdnv01/acpi_tables.c b/src/mainboard/qotom/qdnv01/acpi_tables.c
new file mode 100644
index 0000000000..b6e3846f28
--- /dev/null
+++ b/src/mainboard/qotom/qdnv01/acpi_tables.c
@@ -0,0 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <acpi/acpi.h>
+
+void mainboard_fill_fadt(acpi_fadt_t *fadt)
+{
+	fadt->preferred_pm_profile = PM_ENTERPRISE_SERVER;
+}
diff --git a/src/mainboard/qotom/qdnv01/board_info.txt b/src/mainboard/qotom/qdnv01/board_info.txt
new file mode 100644
index 0000000000..88971b9bfd
--- /dev/null
+++ b/src/mainboard/qotom/qdnv01/board_info.txt
@@ -0,0 +1,6 @@
+Vendor name: Qotom
+Board name: QDNV01
+Category: eval
+ROM protocol: SPI
+ROM socketed: n
+Flashrom support: y
diff --git a/src/mainboard/qotom/qdnv01/bootblock.c b/src/mainboard/qotom/qdnv01/bootblock.c
new file mode 100644
index 0000000000..3b3fd22940
--- /dev/null
+++ b/src/mainboard/qotom/qdnv01/bootblock.c
@@ -0,0 +1,9 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <bootblock_common.h>
+#include <console/uart.h>
+
+
+void bootblock_mainboard_early_init(void)
+{
+}
diff --git a/src/mainboard/qotom/qdnv01/devicetree.cb b/src/mainboard/qotom/qdnv01/devicetree.cb
new file mode 100644
index 0000000000..b7ba01f1ac
--- /dev/null
+++ b/src/mainboard/qotom/qdnv01/devicetree.cb
@@ -0,0 +1,78 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
+chip soc/intel/denverton_ns
+
+	# configure pirq routing
+	register "pirqa_routing" = "11"
+	register "pirqb_routing" = "10"
+	register "pirqc_routing" = "06"
+	register "pirqd_routing" = "07"
+	register "pirqe_routing" = "12"
+	register "pirqf_routing" = "14"
+	register "pirqg_routing" = "15"
+	register "pirqh_routing" = "15"
+	# configure device interrupt routing
+	register "ir00_routing" = "0x3217" # IR00, Dev31
+	register "ir01_routing" = "0x3210" # IR01, Dev22
+	register "ir02_routing" = "0x3211" # IR02, Dev23
+	register "ir03_routing" = "0x3217" # IR03, Dev5
+	register "ir04_routing" = "0x3212" # IR04, Dev6
+	register "ir05_routing" = "0x3210" # IR05, Dev24
+	register "ir06_routing" = "0x3214" # IR06, Dev19
+	register "ir07_routing" = "0x3210" # IR07, Dev9/10/11/12
+	register "ir08_routing" = "0x7654" # IR08, Dev14/15/16/17
+	register "ir09_routing" = "0x3213" # IR09, Dev21
+	register "ir10_routing" = "0x3210" # IR10, Dev26/18
+	register "ir11_routing" = "0x3215" # IR11, Dev20
+	register "ir12_routing" = "0x3210" # IR12, Dev27
+	# configure interrupt polarity control
+	register "ipc0" = "0x00ff4000" # IPC0, PIRQA-H (IRQ16-23) should always be ActiveLow
+	register "ipc1" = "0x00000000" # IPC1
+	register "ipc2" = "0x00000000" # IPC2
+	register "ipc3" = "0x00000000" # IPC3
+
+	device cpu_cluster 0 on	end
+
+	device domain 0 on
+		device pci 00.0 on end # Host Bridge
+		device pci 04.0 on end # RAS
+		device pci 05.0 on end # RCEC (Root Complex Event Collector)
+		device pci 06.0 on end # Virtual root port 2 (QAT)
+		device pci 09.0 on end # PCI Express Port 0
+		device pci 0a.0 on end # PCI Express Port 1
+		device pci 0b.0 on     # PCI Express Port 2
+			device pci 00.0 on end # Intel Ethernet Controller I226-V
+		end
+		device pci 0c.0 on     # PCI Express Port 3
+			device pci 00.0 on end # Intel Ethernet Controller I226-V
+		end
+		device pci 0e.0 on     # PCI Express Port 4
+			device pci 00.0 on end # Intel Ethernet Controller I226-V
+		end
+		device pci 0f.0 on     # PCI Express Port 5
+			device pci 00.0 on end # Intel Ethernet Controller I226-V
+		end
+		device pci 10.0 on     # PCI Express Port 6
+			device pci 00.0 on end # Intel Ethernet Controller I226-V
+		end
+		device pci 11.0 on     # PCI Express Port 7
+			device pci 00.0 on # ASPEED PCI-to-PCI bridge 1a03:1150
+				device pci 00.0 on end # ASPEED VGA controller 1a03:2000
+			end
+		end
+		device pci 12.0 on end # SMBus Controller
+		device pci 13.0 on end # SATA Controller 0
+		device pci 14.0 on end # SATA Controller 1
+		device pci 15.0 on end # XHCI USB Controller
+		device pci 16.0 on end # Virtual root port 0 (10GBE0)
+		device pci 17.0 on end # Virtual root port 1 (10GBE1)
+		device pci 18.0 on end # CSME HECI 1
+		device pci 1a.0 on end # UART 0
+		device pci 1a.1 on end # UART 1
+		device pci 1a.2 on end # UART 2
+		device pci 1f.0 on end # LPC or eSPI
+		device pci 1f.2 on end # PMC/ACPI
+		device pci 1f.4 on end # SMBus Controller
+		device pci 1f.5 on end # SPI Controller
+	end
+end
diff --git a/src/mainboard/qotom/qdnv01/dsdt.asl b/src/mainboard/qotom/qdnv01/dsdt.asl
new file mode 100644
index 0000000000..3fa7422c46
--- /dev/null
+++ b/src/mainboard/qotom/qdnv01/dsdt.asl
@@ -0,0 +1,32 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <acpi/acpi.h>
+DefinitionBlock(
+	"dsdt.aml",
+	"DSDT",
+	ACPI_DSDT_REV_2,
+	OEM_ID,
+	ACPI_TABLE_CREATOR,
+	0x20110725
+)
+{
+	#include <acpi/dsdt_top.asl>
+	#include <southbridge/intel/common/acpi/platform.asl>
+	#include "acpi/platform.asl"
+	#include "acpi/mainboard.asl"
+
+	// global NVS and variables
+	#include <soc/intel/denverton_ns/acpi/globalnvs.asl>
+
+	#include <cpu/intel/common/acpi/cpu.asl>
+
+	Scope (\_SB) {
+		Device (PCI0)
+		{
+			#include <soc/intel/denverton_ns/acpi/northcluster.asl>
+			#include <soc/intel/denverton_ns/acpi/southcluster.asl>
+		}
+	}
+
+	#include <southbridge/intel/common/acpi/sleepstates.asl>
+}
diff --git a/src/mainboard/qotom/qdnv01/gpio.h b/src/mainboard/qotom/qdnv01/gpio.h
new file mode 100644
index 0000000000..b065369929
--- /dev/null
+++ b/src/mainboard/qotom/qdnv01/gpio.h
@@ -0,0 +1,622 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef _MAINBOARD_GPIO_H
+#define _MAINBOARD_GPIO_H
+
+#include <soc/gpio_dnv.h>
+
+#ifndef __ACPI__
+const struct dnv_pad_config qdnv01_gpio_table[] = {
+	// GBE0_SDP0 (GPIO_14)
+	{NORTH_ALL_GBE0_SDP0,
+	 {GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault,
+	  GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
+	// GBE1_SDP0 (GPIO_15)
+	{NORTH_ALL_GBE1_SDP0,
+	 {GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault,
+	  GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
+	// GBE2_I2C_CLK (GPIO_16)
+	{NORTH_ALL_GBE0_SDP1,
+	 {GpioPadModeNative2, GpioHostOwnGpio, GpioDirOut, GpioOutDefault,
+	  GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
+	// GBE2_I2C_DATA (GPIO_17)
+	{NORTH_ALL_GBE1_SDP1,
+	 {GpioPadModeNative2, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault,
+	  GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
+	// GBE2_SDP0 (GPIO_18)
+	{NORTH_ALL_GBE0_SDP2,
+	 {GpioPadModeNative2, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault,
+	  GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
+	// GBE3_SDP0 (GPIO_19)
+	{NORTH_ALL_GBE1_SDP2,
+	 {GpioPadModeNative2, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault,
+	  GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
+	// GBE3_I2C_CLK (GPIO_20)
+	{NORTH_ALL_GBE0_SDP3,
+	 {GpioPadModeNative2, GpioHostOwnGpio, GpioDirOut, GpioOutDefault,
+	  GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
+	// GBE3_I2C_DATA (GPIO_21)
+	{NORTH_ALL_GBE1_SDP3,
+	 {GpioPadModeNative2, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault,
+	  GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
+	// GBE2_LED0 (GPIO_22)
+	{NORTH_ALL_GBE2_LED0,
+	 {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault,
+	  GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
+	// GBE2_LED1 (GPIO_23)
+	{NORTH_ALL_GBE2_LED1,
+	 {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault,
+	  GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
+	// GBE0_I2C_CLK (GPIO_24)
+	{NORTH_ALL_GBE0_I2C_CLK,
+	 {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault,
+	  GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
+	// GBE0_I2C_DATA (GPIO_25)
+	{NORTH_ALL_GBE0_I2C_DATA,
+	 {GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault,
+	  GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
+	// GBE1_I2C_CLK (GPIO_26)
+	{NORTH_ALL_GBE1_I2C_CLK,
+	 {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault,
+	  GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
+	// GBE1_I2C_DATA (GPIO_27)
+	{NORTH_ALL_GBE1_I2C_DATA,
+	 {GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault,
+	  GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
+	// NCSI_RXD0 (GPIO_28)
+	{NORTH_ALL_NCSI_RXD0,
+	 {GpioPadModeNative2, GpioHostOwnGpio, GpioDirIn, GpioOutDefault,
+	  GpioIntDefault, GpioResetPwrGood, GpioTermDefault, GpioLockDefault} },
+	// NCSI_CLK_IN (GPIO_29)
+	{NORTH_ALL_NCSI_CLK_IN,
+	 {GpioPadModeNative2, GpioHostOwnGpio, GpioDirIn, GpioOutDefault,
+	  GpioIntDefault, GpioResetPwrGood, GpioTermDefault, GpioLockDefault} },
+	// NCSI_RXD1 (GPIO_30)
+	{NORTH_ALL_NCSI_RXD1,
+	 {GpioPadModeNative2, GpioHostOwnGpio, GpioDirIn, GpioOutDefault,
+	  GpioIntDefault, GpioResetPwrGood, GpioTermDefault, GpioLockDefault} },
+	// NCSI_CRS_DV (GPIO_31)
+	{NORTH_ALL_NCSI_CRS_DV,
+	 {GpioPadModeNative2, GpioHostOwnGpio, GpioDirIn, GpioOutDefault,
+	  GpioIntDefault, GpioResetPwrGood, GpioTermDefault, GpioLockDefault} },
+	// NCSI_ARB_IN (GPIO_32)
+	{NORTH_ALL_NCSI_ARB_IN,
+	 {GpioPadModeNative2, GpioHostOwnGpio, GpioDirIn, GpioOutDefault,
+	  GpioIntDefault, GpioResetPwrGood, GpioTermDefault, GpioLockDefault} },
+	// NCSI_TX_EN (GPIO_33)
+	{NORTH_ALL_NCSI_TX_EN,
+	 {GpioPadModeNative2, GpioHostOwnGpio, GpioDirIn, GpioOutDefault,
+	  GpioIntDefault, GpioResetPwrGood, GpioTermDefault, GpioLockDefault} },
+	// NCSI_TXD0 (GPIO_34)
+	{NORTH_ALL_NCSI_TXD0,
+	 {GpioPadModeNative2, GpioHostOwnGpio, GpioDirOut, GpioOutDefault,
+	  GpioIntDefault, GpioResetPwrGood, GpioTermDefault, GpioLockDefault} },
+	// NCSI_TXD1 (GPIO_35)
+	{NORTH_ALL_NCSI_TXD1,
+	 {GpioPadModeNative2, GpioHostOwnGpio, GpioDirOut, GpioOutDefault,
+	  GpioIntDefault, GpioResetPwrGood, GpioTermDefault, GpioLockDefault} },
+	// NCSI_ARB_OUT (GPIO_36)
+	{NORTH_ALL_NCSI_ARB_OUT,
+	 {GpioPadModeNative2, GpioHostOwnGpio, GpioDirOut, GpioOutDefault,
+	  GpioIntDefault, GpioResetPwrGood, GpioTermDefault, GpioLockDefault} },
+	// GBE0_LED0 (GPIO_37)
+	{NORTH_ALL_GBE0_LED0,
+	 {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault,
+	  GpioIntDefault, GpioResetPwrGood, GpioTermDefault, GpioLockDefault} },
+	// GBE0_LED1 (GPIO_38)
+	{NORTH_ALL_GBE0_LED1,
+	 {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault,
+	  GpioIntDefault, GpioResetPwrGood, GpioTermDefault, GpioLockDefault} },
+	// GBE1_LED0 (GPIO_39)
+	{NORTH_ALL_GBE1_LED0,
+	 {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault,
+	  GpioIntDefault, GpioResetPwrGood, GpioTermDefault, GpioLockDefault} },
+	// GBE1_LED1 (GPIO_40)
+	{NORTH_ALL_GBE1_LED1,
+	 {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault,
+	  GpioIntDefault, GpioResetPwrGood, GpioTermDefault, GpioLockDefault} },
+	// ADR-COMPLETE (GPIO_0)
+	{NORTH_ALL_GPIO_0,
+	 {GpioPadModeNative3, GpioHostOwnGpio, GpioDirOut, GpioOutDefault,
+	  GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
+	// PCIE_CLKREQ0_N (GPIO_41)
+	{NORTH_ALL_PCIE_CLKREQ0_N,
+	 {GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, GpioOutDefault,
+	  GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
+	// PCIE_CLKREQ1_N (GPIO_42)
+	{NORTH_ALL_PCIE_CLKREQ1_N,
+	 {GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, GpioOutDefault,
+	  GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
+	// PCIE_CLKREQ2_N (GPIO_43)
+	{NORTH_ALL_PCIE_CLKREQ2_N,
+	 {GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, GpioOutDefault,
+	  GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
+	// PCIE_CLKREQ3_N (GPIO_44)
+	{NORTH_ALL_PCIE_CLKREQ3_N,
+	 {GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, GpioOutDefault,
+	  GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
+	// FORCE_POWER (GPIO_45)
+	{NORTH_ALL_PCIE_CLKREQ4_N,
+	 {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutDefault,
+	  GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
+	// GBE_MDC (GPIO_1)
+	{NORTH_ALL_GPIO_1,
+	 {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault,
+	  GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
+	// GBE_MDIO  (GPIO_2)
+	{NORTH_ALL_GPIO_2,
+	 {GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault,
+	  GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
+	// SVID_ALERT_N (GPIO_47)
+	{NORTH_ALL_SVID_ALERT_N,
+	 {GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, GpioOutDefault,
+	  GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
+	// SVID_DATA (GPIO_48)
+	{NORTH_ALL_SVID_DATA,
+	 {GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault,
+	  GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
+	// SVID_CLK (GPIO_49)
+	{NORTH_ALL_SVID_CLK,
+	 {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault,
+	  GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
+	// THERMTRIP_N (GPIO_50)
+	{NORTH_ALL_THERMTRIP_N,
+	 {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault,
+	  GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
+	// PROCHOT_N (GPIO_51)
+	{NORTH_ALL_PROCHOT_N,
+	 {GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, GpioOutDefault,
+	  GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
+	// MEMHOT_N (GPIO_52)
+	{NORTH_ALL_MEMHOT_N,
+	 {GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, GpioOutDefault,
+	  GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
+	// DFX_PORT_CLK0 (GPIO_53)
+	{SOUTH_DFX_DFX_PORT_CLK0,
+	 {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault,
+	  GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
+	// DFX_PORT_CLK1 (GPIO_54)
+	{SOUTH_DFX_DFX_PORT_CLK1,
+	 {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault,
+	  GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
+	// DFX_PORT0 (GPIO_55)
+	{SOUTH_DFX_DFX_PORT0,
+	 {GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault,
+	  GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
+	// DFX_PORT1 (GPIO_56)
+	{SOUTH_DFX_DFX_PORT1,
+	 {GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault,
+	  GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
+	// DFX_PORT2 (GPIO_57)
+	{SOUTH_DFX_DFX_PORT2,
+	 {GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault,
+	  GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
+	// DFX_PORT3 (GPIO_58)
+	{SOUTH_DFX_DFX_PORT3,
+	 {GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault,
+	  GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
+	// DFX_PORT4 (GPIO_59)
+	{SOUTH_DFX_DFX_PORT4,
+	 {GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault,
+	  GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
+	// DFX_PORT5 (GPIO_60)
+	{SOUTH_DFX_DFX_PORT5,
+	 {GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault,
+	  GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
+	// DFX_PORT6 (GPIO_61)
+	{SOUTH_DFX_DFX_PORT6,
+	 {GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault,
+	  GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
+	// DFX_PORT7 (GPIO_62)
+	{SOUTH_DFX_DFX_PORT7,
+	 {GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault,
+	  GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
+	// DFX_PORT8 (GPIO_63)
+	{SOUTH_DFX_DFX_PORT8,
+	 {GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault,
+	  GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
+	// DFX_PORT9 (GPIO_134)
+	{SOUTH_DFX_DFX_PORT9,
+	 {GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault,
+	  GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
+	// DFX_PORT10 (GPIO_135)
+	{SOUTH_DFX_DFX_PORT10,
+	 {GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault,
+	  GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
+	// DFX_PORT11 (GPIO_136)
+	{SOUTH_DFX_DFX_PORT11,
+	 {GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault,
+	  GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
+	// DFX_PORT12 (GPIO_137)
+	{SOUTH_DFX_DFX_PORT12,
+	 {GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault,
+	  GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
+	// DFX_PORT13 (GPIO_138)
+	{SOUTH_DFX_DFX_PORT13,
+	 {GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault,
+	  GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
+	// DFX_PORT14 (GPIO_139)
+	{SOUTH_DFX_DFX_PORT14,
+	 {GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault,
+	  GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
+	// DFX_PORT15 (GPIO_140)
+	{SOUTH_DFX_DFX_PORT15,
+	 {GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault,
+	  GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
+	// SPI_TPM_CS_N (GPIO_12)
+	{SOUTH_GROUP0_GPIO_12,
+	 {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault,
+	  GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
+	// SMB5_GBE_ALRT_N (GPIO_13)
+	{SOUTH_GROUP0_SMB5_GBE_ALRT_N,
+	 {GpioPadModeNative3, GpioHostOwnGpio, GpioDirIn, GpioOutDefault,
+	  GpioIntDefault, GpioResetPwrGood, GpioTermDefault, GpioLockDefault} },
+	// SMI (GPIO_98)
+	{SOUTH_GROUP0_PCIE_CLKREQ5_N,
+	 {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault,
+	  GpioIntSmi, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
+	// NMI (GPIO_99)
+	{SOUTH_GROUP0_PCIE_CLKREQ6_N,
+	 {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault,
+	  GpioIntNmi, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
+	// GBE3_LED0 (GPIO_100)
+	{SOUTH_GROUP0_PCIE_CLKREQ7_N,
+	 {GpioPadModeNative3, GpioHostOwnGpio, GpioDirOut, GpioOutDefault,
+	  GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
+	// UART0_RXD (GPIO_101)
+	{SOUTH_GROUP0_UART0_RXD,
+	 {GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, GpioOutDefault,
+	  GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
+	// UART0_TXD (GPIO_102)
+	{SOUTH_GROUP0_UART0_TXD,
+	 {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault,
+	  GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
+	// SMB5_GBE_CLK (GPIO_103)
+	{SOUTH_GROUP0_SMB5_GBE_CLK,
+	 {GpioPadModeNative3, GpioHostOwnGpio, GpioDirOut, GpioOutDefault,
+	  GpioIntDefault, GpioResetPwrGood, GpioTermDefault, GpioLockDefault} },
+	// SMB_GBE_DATA (GPIO_104)
+	{SOUTH_GROUP0_SMB5_GBE_DATA,
+	 {GpioPadModeNative3, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault,
+	  GpioIntDefault, GpioResetPwrGood, GpioTermDefault, GpioLockDefault} },
+	// ERROR2_N (GPIO_105)
+	{SOUTH_GROUP0_ERROR2_N,
+	 {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault,
+	  GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
+	// ERROR1_N (GPIO_106)
+	{SOUTH_GROUP0_ERROR1_N,
+	 {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault,
+	  GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
+	// ERROR0_N (GPIO_107)
+	{SOUTH_GROUP0_ERROR0_N,
+	 {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault,
+	  GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
+	// IERR_N (CATERR_N) (GPIO_108)
+	{SOUTH_GROUP0_IERR_N,
+	 {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault,
+	  GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
+	// MCERR_N  (GPIO_109)
+	{SOUTH_GROUP0_MCERR_N,
+	 {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault,
+	  GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
+	// SMB0_LEG_CLK (GPIO_110)
+	{SOUTH_GROUP0_SMB0_LEG_CLK,
+	 {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault,
+	  GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
+	// SMB0_LEG_DATA (GPIO_111)
+	{SOUTH_GROUP0_SMB0_LEG_DATA,
+	 {GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault,
+	  GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
+	// SMB0_LEG_ALRT_N (GPIO_112)
+	{SOUTH_GROUP0_SMB0_LEG_ALRT_N,
+	 {GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, GpioOutDefault,
+	  GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
+	// SMB1_HOST_DATA (GPIO_113)
+	{SOUTH_GROUP0_SMB1_HOST_DATA,
+	 {GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault,
+	  GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
+	// SMB1_HOST_CLK (GPIO_114)
+	{SOUTH_GROUP0_SMB1_HOST_CLK,
+	 {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault,
+	  GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
+	// SMB2_PECI_DATA (GPIO_115)
+	{SOUTH_GROUP0_SMB2_PECI_DATA,
+	 {GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault,
+	  GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
+	// SMB2_PECI_CLK (GPIO_116)
+	{SOUTH_GROUP0_SMB2_PECI_CLK,
+	 {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault,
+	  GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
+	// SMB4_CSME0_DATA (GPIO_117)
+	{SOUTH_GROUP0_SMB4_CSME0_DATA,
+	 {GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault,
+	  GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
+	// SMB4_CSME0_CLK (GPIO_118)
+	{SOUTH_GROUP0_SMB4_CSME0_CLK,
+	 {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault,
+	  GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
+	// SMB4_CSME0_ALRT_N (GPIO_119)
+	{SOUTH_GROUP0_SMB4_CSME0_ALRT_N,
+	 {GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, GpioOutDefault,
+	  GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
+	// USB_OC0_N (GPIO_120)
+	{SOUTH_GROUP0_USB_OC0_N,
+	 {GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, GpioOutDefault,
+	  GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
+	// FLEX_CLK_SE0 (GPIO_121)
+	{SOUTH_GROUP0_FLEX_CLK_SE0,
+	 {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault,
+	  GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
+	// FLEX_CLK_SE1 (GPIO_122)
+	{SOUTH_GROUP0_FLEX_CLK_SE1,
+	 {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault,
+	  GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
+	// GBE3_LED1 (GPIO_4)
+	{SOUTH_GROUP0_GPIO_4,
+	 {GpioPadModeNative3, GpioHostOwnGpio, GpioDirOut, GpioOutDefault,
+	  GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
+	// SMB3_IE0_CLK (GPIO_5)
+	{SOUTH_GROUP0_GPIO_5,
+	 {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault,
+	  GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
+	// SMB3_IE0_DATA (GPIO_6)
+	{SOUTH_GROUP0_GPIO_6,
+	 {GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault,
+	  GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
+	// SMB3_IE0_ALERT_N (GPIO_7)
+	{SOUTH_GROUP0_GPIO_7,
+	 {GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, GpioOutDefault,
+	  GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
+	// SATA0_LED (GPIO_90)
+	{SOUTH_GROUP0_SATA0_LED_N,
+	 {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault,
+	  GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
+	// SATA1_LED (GPIO_91)
+	{SOUTH_GROUP0_SATA1_LED_N,
+	 {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault,
+	  GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
+	// SATA_PDETECT0 (GPIO_92)
+	{SOUTH_GROUP0_SATA_PDETECT0,
+	 {GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, GpioOutDefault,
+	  GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
+	// SATA_PDETECT1 (GPIO_93)
+	{SOUTH_GROUP0_SATA_PDETECT1,
+	 {GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, GpioOutDefault,
+	  GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
+	// UART1_RTS (GPIO_94)
+	{SOUTH_GROUP0_SATA0_SDOUT,
+	 {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault,
+	  GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
+	// UART1_CTS (GPIO_95)
+	{SOUTH_GROUP0_SATA1_SDOUT,
+	 {GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, GpioOutDefault,
+	  GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
+	// UART1_RXD (GPIO_96)
+	{SOUTH_GROUP0_UART1_RXD,
+	 {GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, GpioOutDefault,
+	  GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
+	// UART1_TXD (GPIO_97)
+	{SOUTH_GROUP0_UART1_TXD,
+	 {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault,
+	  GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
+	// SMB6_CSME1_DATA (GPIO_8)
+	{SOUTH_GROUP0_GPIO_8,
+	 {GpioPadModeNative3, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault,
+	  GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
+	// SMB6_CSME1_CLK (GPIO_9)
+	{SOUTH_GROUP0_GPIO_9,
+	 {GpioPadModeNative3, GpioHostOwnGpio, GpioDirOut, GpioOutDefault,
+	  GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
+	// TCK (GPIO_141)
+	{SOUTH_GROUP0_TCK,
+	 {GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, GpioOutDefault,
+	  GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
+	// TRST_N (GPIO_142)
+	{SOUTH_GROUP0_TRST_N,
+	 {GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, GpioOutDefault,
+	  GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
+	// TMS (GPIO_143)
+	{SOUTH_GROUP0_TMS,
+	 {GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, GpioOutDefault,
+	  GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
+	// TDI (GPIO_144)
+	{SOUTH_GROUP0_TDI,
+	 {GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, GpioOutDefault,
+	  GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
+	// TDO (GPIO_145)
+	{SOUTH_GROUP0_TDO,
+	 {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault,
+	  GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
+	// CX_PRDY_N (GPIO_146)
+	{SOUTH_GROUP0_CX_PRDY_N,
+	 {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault,
+	  GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
+	// CX-PREQ_N (GPIO_147)
+	{SOUTH_GROUP0_CX_PREQ_N,
+	 {GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, GpioOutDefault,
+	  GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
+	// ME_RECVR_HDR (GPIO_148)
+	{SOUTH_GROUP0_CTBTRIGINOUT,
+	 {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault,
+	  GpioIntDefault, GpioResetDefault,  GpioTermWpu20K /*GpioTermDefault*/,
+							GpioLockDefault} },
+	// ADV_DBG_DFX_HDR (GPIO_149)
+	{SOUTH_GROUP0_CTBTRIGOUT,
+	 {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault,
+	  GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
+	// LAD2_SPI_IRQ_N (GPIO_150)
+	{SOUTH_GROUP0_DFX_SPARE2,
+	 {GpioPadModeGpio, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault,
+	  GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
+	// SMB_PECI_ALRT_N (GPIO_151)
+	{SOUTH_GROUP0_DFX_SPARE3,
+	 {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault,
+	  GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
+	// SMB_CSME1_ALRT_N (GPIO_152)
+	{SOUTH_GROUP0_DFX_SPARE4,
+	 {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault,
+	  GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
+	// SUSPWRDNACK (GPIO_79)
+	{SOUTH_GROUP1_SUSPWRDNACK,
+	 {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault,
+	  GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
+	// PMU_SUSCLK (GPIO_80)
+	{SOUTH_GROUP1_PMU_SUSCLK,
+	 {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault,
+	  GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
+	// ADR_TRIGGER_N (GPIO_81)
+	{SOUTH_GROUP1_ADR_TRIGGER,
+	 {GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, GpioOutDefault,
+	  GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
+	// PMU_SLP_S45_N (GPIO_82)
+	{SOUTH_GROUP1_PMU_SLP_S45_N,
+	 {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault,
+	  GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
+	// PMU_SLP_S3_N (GPIO_83)
+	{SOUTH_GROUP1_PMU_SLP_S3_N,
+	 {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault,
+	  GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
+	// PMU_WAKE_N (GPIO_84)
+	{SOUTH_GROUP1_PMU_WAKE_N,
+	 {GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, GpioOutDefault,
+	  GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
+	// PMU_PWRBTN_N (GPIO_85)
+	{SOUTH_GROUP1_PMU_PWRBTN_N,
+	 {GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, GpioOutDefault,
+	  GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
+	// PMU_RESETBUTTON_N (GPIO_86)
+	{SOUTH_GROUP1_PMU_RESETBUTTON_N,
+	 {GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, GpioOutDefault,
+	  GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
+	// PMU_PLTRST_N (GPIO_87)
+	{SOUTH_GROUP1_PMU_PLTRST_N,
+	 {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault,
+	  GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
+	// PMU_SUS_STAT_N (GPIO_88)
+	{SOUTH_GROUP1_SUS_STAT_N,
+	 {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault,
+	  GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
+	// TDB_CIO_PLUG_EVENT (GPIO_89)
+	{SOUTH_GROUP1_SLP_S0IX_N,
+	 {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault,
+	  GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
+	// SPI_CS0_N (GPIO_72)
+	{SOUTH_GROUP1_SPI_CS0_N,
+	 {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault,
+	  GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
+	// SPI_CS1_N (GPIO_73)
+	{SOUTH_GROUP1_SPI_CS1_N,
+	 {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault,
+	  GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
+	// SPI_MOSI_IO0 (GPIO_74)
+	{SOUTH_GROUP1_SPI_MOSI_IO0,
+	 {GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault,
+	  GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
+	// SPI_MISO_IO1 (GPIO_75)
+	{SOUTH_GROUP1_SPI_MISO_IO1,
+	 {GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault,
+	  GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
+	// SPI_IO2 (GPIO_76)
+	{SOUTH_GROUP1_SPI_IO2,
+	 {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault,
+	  GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
+	// SPI_IO3 (GPIO_77)
+	{SOUTH_GROUP1_SPI_IO3,
+	 {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault,
+	  GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
+	// SPI_CLK (GPIO_78)
+	{SOUTH_GROUP1_SPI_CLK,
+	 {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault,
+	  GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
+	// LPC_AD0 (GPIO_64)
+	{SOUTH_GROUP1_ESPI_IO0,
+	 {GpioPadModeNative2, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault,
+	  GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
+	// LPC_AD1 (GPIO_65)
+	{SOUTH_GROUP1_ESPI_IO1,
+	 {GpioPadModeNative2, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault,
+	  GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
+	// LPC_AD2 (GPIO_66)
+	{SOUTH_GROUP1_ESPI_IO2,
+	 {GpioPadModeNative2, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault,
+	  GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
+	// LPC_AD3 (GPIO_67)
+	{SOUTH_GROUP1_ESPI_IO3,
+	 {GpioPadModeNative2, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault,
+	  GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
+	// LPC_FRAME_N (GPIO_68)
+	{SOUTH_GROUP1_ESPI_CS0_N,
+	 {GpioPadModeNative2, GpioHostOwnGpio, GpioDirOut, GpioOutDefault,
+	  GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
+	// LPC_CLKOUT0 (GPIO_69)
+	{SOUTH_GROUP1_ESPI_CLK,
+	 {GpioPadModeNative2, GpioHostOwnGpio, GpioDirOut, GpioOutDefault,
+	  GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
+	// LPC_CLKOUT1 (GPIO_70)
+	{SOUTH_GROUP1_ESPI_RST_N,
+	 {GpioPadModeNative2, GpioHostOwnGpio, GpioDirOut, GpioOutDefault,
+	  GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
+	// LPC_CLKRUN_N (GPIO_71)
+	{SOUTH_GROUP1_ESPI_ALRT0_N,
+	 {GpioPadModeNative2, GpioHostOwnGpio, GpioDirOut, GpioOutDefault,
+	  GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
+	// MFG_MODE_HDR (GPIO_10)
+	{SOUTH_GROUP1_GPIO_10,
+	 {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault,
+	  GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
+	// LPC_SERIRQ (GPIO_11)
+	{SOUTH_GROUP1_GPIO_11,
+	 {GpioPadModeNative2, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault,
+	  GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
+	// EMMC-CMD (GPIO_123)
+	{SOUTH_GROUP1_EMMC_CMD,
+	 {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault,
+	  GpioIntDefault, GpioResetDefault, GpioTermWpu20K, GpioLockDefault} },
+	// EMMC-CSTROBE (GPIO_124)
+	{SOUTH_GROUP1_EMMC_STROBE,
+	 {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault,
+	  GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
+	// EMMC-CLK (GPIO_125)
+	{SOUTH_GROUP1_EMMC_CLK,
+	 {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault,
+	  GpioIntDefault, GpioResetDefault, GpioTermWpd20K, GpioLockDefault} },
+	// EMMC-D0 (GPIO_126)
+	{SOUTH_GROUP1_EMMC_D0,
+	 {GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault,
+	  GpioIntDefault, GpioResetDefault, GpioTermWpu20K, GpioLockDefault} },
+	// EMMC-D1 (GPIO_127)
+	{SOUTH_GROUP1_EMMC_D1,
+	 {GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault,
+	  GpioIntDefault, GpioResetDefault, GpioTermWpu20K, GpioLockDefault} },
+	// EMMC-D2 (GPIO_128)
+	{SOUTH_GROUP1_EMMC_D2,
+	 {GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault,
+	  GpioIntDefault, GpioResetDefault, GpioTermWpu20K, GpioLockDefault} },
+	// EMMC-D3 (GPIO_129)
+	{SOUTH_GROUP1_EMMC_D3,
+	 {GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault,
+	  GpioIntDefault, GpioResetDefault, GpioTermWpu20K, GpioLockDefault} },
+	// EMMC-D4 (GPIO_130)
+	{SOUTH_GROUP1_EMMC_D4,
+	 {GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault,
+	  GpioIntDefault, GpioResetDefault, GpioTermWpu20K, GpioLockDefault} },
+	// EMMC-D5 (GPIO_131)
+	{SOUTH_GROUP1_EMMC_D5,
+	 {GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault,
+	  GpioIntDefault, GpioResetDefault, GpioTermWpu20K, GpioLockDefault} },
+	// EMMC-D6 (GPIO_132)
+	{SOUTH_GROUP1_EMMC_D6,
+	 {GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault,
+	  GpioIntDefault, GpioResetDefault, GpioTermWpu20K, GpioLockDefault} },
+	// EMMC-D7 (GPIO_133)
+	{SOUTH_GROUP1_EMMC_D7,
+	 {GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault,
+	  GpioIntDefault, GpioResetDefault, GpioTermWpu20K, GpioLockDefault} },
+	// IE_ROM GPIO (GPIO_3)
+	{SOUTH_GROUP1_GPIO_3,
+	 {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutDefault,
+	  GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },
+};
+#endif
+
+#endif /* _MAINBOARD_GPIO_H */
diff --git a/src/mainboard/qotom/qdnv01/hsio.c b/src/mainboard/qotom/qdnv01/hsio.c
new file mode 100644
index 0000000000..3b1beac3ff
--- /dev/null
+++ b/src/mainboard/qotom/qdnv01/hsio.c
@@ -0,0 +1,253 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <fsp/util.h>
+#include <soc/fiamux.h>
+
+static const BL_HSIO_INFORMATION qdnv01_hsio_config[] = {
+	/*
+	*
+	*	Bifurcation:
+	*	PCIE cluster #0: x2x2x2x2
+	*	PCIE cluster #1: x2x2x2x2
+	*
+	*/
+	{BL_SKU_HSIO_20,
+	{PCIE_BIF_CTRL_x2x2x2x2, PCIE_BIF_CTRL_x2x2x2x2},
+	{/* ME_FIA_MUX_CONFIG */
+	  {BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_PCIE, BL_FIA_LANE00) |
+	   BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_PCIE, BL_FIA_LANE01) |
+	   BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_PCIE, BL_FIA_LANE02) |
+	   BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_PCIE, BL_FIA_LANE03) |
+	   BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_PCIE, BL_FIA_LANE04) |
+	   BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_PCIE, BL_FIA_LANE05) |
+	   BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_PCIE, BL_FIA_LANE06) |
+	   BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_PCIE, BL_FIA_LANE07) |
+	   BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_PCIE, BL_FIA_LANE08) |
+	   BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_PCIE, BL_FIA_LANE09) |
+	   BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_PCIE, BL_FIA_LANE10) |
+	   BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_PCIE, BL_FIA_LANE11) |
+	   BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_PCIE, BL_FIA_LANE12) |
+	   BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_PCIE, BL_FIA_LANE13) |
+	   BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_PCIE, BL_FIA_LANE14) |
+	   BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_PCIE, BL_FIA_LANE15) |
+	   BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_SATA, BL_FIA_LANE16) |
+	   BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_SATA, BL_FIA_LANE17) |
+	   BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_SATA, BL_FIA_LANE18) |
+	   BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_XHCI, BL_FIA_LANE19)},
+
+	  /* ME_FIA_SATA_CONFIG */
+	  {BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,
+				   BL_FIA_SATA_LANE04) |
+	   BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,
+				   BL_FIA_SATA_LANE05) |
+	   BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,
+				   BL_FIA_SATA_LANE06) |
+	   BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,
+				   BL_FIA_SATA_LANE07) |
+	   BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,
+				   BL_FIA_SATA_LANE08) |
+	   BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,
+				   BL_FIA_SATA_LANE09) |
+	   BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,
+				   BL_FIA_SATA_LANE10) |
+	   BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,
+				   BL_FIA_SATA_LANE11) |
+	   BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,
+				   BL_FIA_SATA_LANE12) |
+	   BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,
+				   BL_FIA_SATA_LANE13) |
+	   BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,
+				   BL_FIA_SATA_LANE14) |
+	   BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,
+				   BL_FIA_SATA_LANE15) |
+	   BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_ASSIGNED,
+				   BL_FIA_SATA_LANE16) |
+	   BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_ASSIGNED,
+				   BL_FIA_SATA_LANE17) |
+	   BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_ASSIGNED,
+				   BL_FIA_SATA_LANE18) |
+	   BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,
+				   BL_FIA_SATA_LANE19)},
+
+	  /* ME_FIA_PCIE_ROOT_PORTS_CONFIG */
+	  {BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_STATE,
+					BL_ME_FIA_PCIE_ROOT_PORT_ENABLED,
+					BL_FIA_PCIE_ROOT_PORT_0) |
+	   BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_STATE,
+					BL_ME_FIA_PCIE_ROOT_PORT_ENABLED,
+					BL_FIA_PCIE_ROOT_PORT_1) |
+	   BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_STATE,
+					BL_ME_FIA_PCIE_ROOT_PORT_ENABLED,
+					BL_FIA_PCIE_ROOT_PORT_2) |
+	   BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_STATE,
+					BL_ME_FIA_PCIE_ROOT_PORT_ENABLED,
+					BL_FIA_PCIE_ROOT_PORT_3) |
+	   BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_STATE,
+					BL_ME_FIA_PCIE_ROOT_PORT_ENABLED,
+					BL_FIA_PCIE_ROOT_PORT_4) |
+	   BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_STATE,
+					BL_ME_FIA_PCIE_ROOT_PORT_ENABLED,
+					BL_FIA_PCIE_ROOT_PORT_5) |
+	   BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_STATE,
+					BL_ME_FIA_PCIE_ROOT_PORT_ENABLED,
+					BL_FIA_PCIE_ROOT_PORT_6) |
+	   BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_STATE,
+					BL_ME_FIA_PCIE_ROOT_PORT_ENABLED,
+					BL_FIA_PCIE_ROOT_PORT_7) |
+	   BL_FIA_PCIE_ROOT_PORT_CONFIG(
+		   BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH,
+		   BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL,
+		   BL_FIA_PCIE_ROOT_PORT_0) |
+	   BL_FIA_PCIE_ROOT_PORT_CONFIG(
+		   BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH,
+		   BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL,
+		   BL_FIA_PCIE_ROOT_PORT_1) |
+	   BL_FIA_PCIE_ROOT_PORT_CONFIG(
+		   BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH,
+		   BL_ME_FIA_PCIE_ROOT_PORT_LINK_X1,
+		   BL_FIA_PCIE_ROOT_PORT_2) |
+	   BL_FIA_PCIE_ROOT_PORT_CONFIG(
+		   BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH,
+		   BL_ME_FIA_PCIE_ROOT_PORT_LINK_X1,
+		   BL_FIA_PCIE_ROOT_PORT_3) |
+	   BL_FIA_PCIE_ROOT_PORT_CONFIG(
+		   BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH,
+		   BL_ME_FIA_PCIE_ROOT_PORT_LINK_X1,
+		   BL_FIA_PCIE_ROOT_PORT_4) |
+	   BL_FIA_PCIE_ROOT_PORT_CONFIG(
+		   BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH,
+		   BL_ME_FIA_PCIE_ROOT_PORT_LINK_X1,
+		   BL_FIA_PCIE_ROOT_PORT_5) |
+	   BL_FIA_PCIE_ROOT_PORT_CONFIG(
+		   BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH,
+		   BL_ME_FIA_PCIE_ROOT_PORT_LINK_X1,
+		   BL_FIA_PCIE_ROOT_PORT_6) |
+	   BL_FIA_PCIE_ROOT_PORT_CONFIG(
+		   BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH,
+		   BL_ME_FIA_PCIE_ROOT_PORT_LINK_X1,
+		   BL_FIA_PCIE_ROOT_PORT_7)} } },
+
+	/* SKU HSIO 12 */
+	{BL_SKU_HSIO_12,
+	{PCIE_BIF_CTRL_x2x2x2x2, PCIE_BIF_CTRL_x2x2x2x2},
+	{/*ME_FIA_MUX_CONFIG */
+	  {BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_PCIE, BL_FIA_LANE00) |
+	   BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_PCIE, BL_FIA_LANE01) |
+	   BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_PCIE, BL_FIA_LANE02) |
+	   BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_PCIE, BL_FIA_LANE03) |
+	   BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE04) |
+	   BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE05) |
+	   BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE06) |
+	   BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE07) |
+	   BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_PCIE, BL_FIA_LANE08) |
+	   BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_PCIE, BL_FIA_LANE09) |
+	   BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE10) |
+	   BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE11) |
+	   BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_PCIE, BL_FIA_LANE12) |
+	   BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_PCIE, BL_FIA_LANE13) |
+	   BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE14) |
+	   BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE15) |
+	   BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_SATA, BL_FIA_LANE16) |
+	   BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_SATA, BL_FIA_LANE17) |
+	   BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_SATA, BL_FIA_LANE18) |
+	   BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_XHCI, BL_FIA_LANE19)},
+
+	  /* ME_FIA_SATA_CONFIG */
+	  {BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,
+				   BL_FIA_SATA_LANE04) |
+	   BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,
+				   BL_FIA_SATA_LANE05) |
+	   BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,
+				   BL_FIA_SATA_LANE06) |
+	   BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,
+				   BL_FIA_SATA_LANE07) |
+	   BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,
+				   BL_FIA_SATA_LANE08) |
+	   BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,
+				   BL_FIA_SATA_LANE09) |
+	   BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,
+				   BL_FIA_SATA_LANE10) |
+	   BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,
+				   BL_FIA_SATA_LANE11) |
+	   BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,
+				   BL_FIA_SATA_LANE12) |
+	   BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,
+				   BL_FIA_SATA_LANE13) |
+	   BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,
+				   BL_FIA_SATA_LANE14) |
+	   BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,
+				   BL_FIA_SATA_LANE15) |
+	   BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_ASSIGNED,
+				   BL_FIA_SATA_LANE16) |
+	   BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_ASSIGNED,
+				   BL_FIA_SATA_LANE17) |
+	   BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_ASSIGNED,
+				   BL_FIA_SATA_LANE18) |
+	   BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,
+				   BL_FIA_SATA_LANE19)},
+
+	  /* ME_FIA_PCIE_ROOT_PORTS_CONFIG */
+	  {BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_STATE,
+					BL_ME_FIA_PCIE_ROOT_PORT_ENABLED,
+					BL_FIA_PCIE_ROOT_PORT_0) |
+	   BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_STATE,
+					BL_ME_FIA_PCIE_ROOT_PORT_ENABLED,
+					BL_FIA_PCIE_ROOT_PORT_1) |
+	   BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_STATE,
+					BL_ME_FIA_PCIE_ROOT_PORT_ENABLED,
+					BL_FIA_PCIE_ROOT_PORT_2) |
+	   BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_STATE,
+					BL_ME_FIA_PCIE_ROOT_PORT_ENABLED,
+					BL_FIA_PCIE_ROOT_PORT_3) |
+	   BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_STATE,
+					BL_ME_FIA_PCIE_ROOT_PORT_ENABLED,
+					BL_FIA_PCIE_ROOT_PORT_4) |
+	   BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_STATE,
+					BL_ME_FIA_PCIE_ROOT_PORT_ENABLED,
+					BL_FIA_PCIE_ROOT_PORT_5) |
+	   BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_STATE,
+					BL_ME_FIA_PCIE_ROOT_PORT_ENABLED,
+					BL_FIA_PCIE_ROOT_PORT_6) |
+	   BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_STATE,
+					BL_ME_FIA_PCIE_ROOT_PORT_ENABLED,
+					BL_FIA_PCIE_ROOT_PORT_7) |
+	   BL_FIA_PCIE_ROOT_PORT_CONFIG(
+		   BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH,
+		   BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL,
+		   BL_FIA_PCIE_ROOT_PORT_0) |
+	   BL_FIA_PCIE_ROOT_PORT_CONFIG(
+		   BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH,
+		   BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL,
+		   BL_FIA_PCIE_ROOT_PORT_1) |
+	   BL_FIA_PCIE_ROOT_PORT_CONFIG(
+		   BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH,
+		   BL_ME_FIA_PCIE_ROOT_PORT_LINK_X1,
+		   BL_FIA_PCIE_ROOT_PORT_2) |
+	   BL_FIA_PCIE_ROOT_PORT_CONFIG(
+		   BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH,
+		   BL_ME_FIA_PCIE_ROOT_PORT_LINK_X1,
+		   BL_FIA_PCIE_ROOT_PORT_3) |
+	   BL_FIA_PCIE_ROOT_PORT_CONFIG(
+		   BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH,
+		   BL_ME_FIA_PCIE_ROOT_PORT_LINK_X1,
+		   BL_FIA_PCIE_ROOT_PORT_4) |
+	   BL_FIA_PCIE_ROOT_PORT_CONFIG(
+		   BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH,
+		   BL_ME_FIA_PCIE_ROOT_PORT_LINK_X1,
+		   BL_FIA_PCIE_ROOT_PORT_5) |
+	   BL_FIA_PCIE_ROOT_PORT_CONFIG(
+		   BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH,
+		   BL_ME_FIA_PCIE_ROOT_PORT_LINK_X1,
+		   BL_FIA_PCIE_ROOT_PORT_6) |
+	   BL_FIA_PCIE_ROOT_PORT_CONFIG(
+		   BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH,
+		   BL_ME_FIA_PCIE_ROOT_PORT_LINK_X1,
+		   BL_FIA_PCIE_ROOT_PORT_7)} } }
+};
+
+size_t mainboard_get_hsio_config(BL_HSIO_INFORMATION **p_hsio_config)
+{
+	const size_t num = ARRAY_SIZE(qdnv01_hsio_config);
+	(*p_hsio_config) = (BL_HSIO_INFORMATION *)qdnv01_hsio_config;
+	return num;
+}
diff --git a/src/mainboard/qotom/qdnv01/ramstage.c b/src/mainboard/qotom/qdnv01/ramstage.c
new file mode 100644
index 0000000000..b7e56c569d
--- /dev/null
+++ b/src/mainboard/qotom/qdnv01/ramstage.c
@@ -0,0 +1,9 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <soc/ramstage.h>
+
+void mainboard_silicon_init_params(FSPS_UPD *params)
+{
+	/* Disable eMMC */
+	params->FspsConfig.PcdEnableEmmc = 0;
+}
diff --git a/src/mainboard/qotom/qdnv01/romstage.c b/src/mainboard/qotom/qdnv01/romstage.c
new file mode 100644
index 0000000000..4a2ea2c4e2
--- /dev/null
+++ b/src/mainboard/qotom/qdnv01/romstage.c
@@ -0,0 +1,37 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include "gpio.h"
+#include <console/console.h>
+#include <soc/romstage.h>
+#include <fsp/api.h>
+#include <fsp/soc_binding.h>
+
+
+/*
+* Configure GPIO depend on platform
+*/
+void mainboard_config_gpios(void)
+{
+	const int num = ARRAY_SIZE(qdnv01_gpio_table);
+	const struct dnv_pad_config *table = qdnv01_gpio_table;
+
+	printk(BIOS_INFO, "GPIO table: 0x%lx, entry num: %d!\n",
+	       (uintptr_t)table, num);
+	gpio_configure_dnv_pads(table, num);
+}
+
+void mainboard_memory_init_params(FSPM_UPD *mupd)
+{
+	/* Disable Memory Down function */
+	mupd->FspmConfig.PcdMemoryDown = 0;
+
+	mupd->FspmConfig.PcdMmioSize = 2;
+
+	/* Enable memory preservation through warm resets and Fast Boot by default */
+	mupd->FspmConfig.PcdMemoryPreservation = 1;
+	mupd->FspmConfig.PcdFastBoot = 1;
+	mupd->FspmConfig.PcdSkipMemoryTest = 1;
+
+	/* FSP debug message level */
+	mupd->FspmConfig.PcdFspDebugPrintErrorLevel = 1;
+}

From 2439a12a68728319b06b29ae8a194b9fd1bcc4e1 Mon Sep 17 00:00:00 2001
From: Jon Murphy <jpmurphy@google.com>
Date: Tue, 17 Feb 2026 13:47:20 -0700
Subject: [PATCH 3375/3886] mb/google/volteer/var/elemi: Check FP presence
 against SKU ID

Add/update FP enable/disable based on SKU ID. This is meant
to resolve a UMA issue with devices that had the FPMCU populated on
non-fp devices.  Since the FPMCU is present, and the firmware enables
the power GPIO's based on variant, not SKU, the devices were reporting
data on fingerprint errantly.  Specify the SKUs which should not have a
FP sensor and default to true to maintain the legacy behavior for
undefined devices and limit risk.  Variants which do not have FP SKUs
will be unaffected.

BUG=b:354769653,b:484162286
TEST=Flash on device, test FP.
Disable test SKU, flash on device, test FP.

To test, run `ectool --name=cros_fp version` in the shell
When enabled, the fpmcu fw version should be displayed.
When disabled, an error should be displayed because the fpmcu
is inaccessible.

Change-Id: I6998534e3b9c5909839aceb886ab04a04f394289
Signed-off-by: Jon Murphy <jpmurphy@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91329
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
---
 .../google/volteer/variants/elemi/ramstage.c  | 28 +++++++++++++------
 1 file changed, 20 insertions(+), 8 deletions(-)

diff --git a/src/mainboard/google/volteer/variants/elemi/ramstage.c b/src/mainboard/google/volteer/variants/elemi/ramstage.c
index 16261b7d45..adff524d06 100644
--- a/src/mainboard/google/volteer/variants/elemi/ramstage.c
+++ b/src/mainboard/google/volteer/variants/elemi/ramstage.c
@@ -10,11 +10,26 @@ void variant_ramstage_init(void)
 	uint32_t sku_id = google_chromeec_get_board_sku();
 
 	switch (sku_id) {
-	case 102:
-	case 104:
-	case 107:
-	case 109:
-	case 115:
+	case 0xB0012:
+	case 0xB0014:
+	case 0xB0015:
+	case 0xB0016:
+	case 0xB0021:
+	case 0xB0023:
+	case 0xB0027:
+	case 0xB0032:
+	case 0xB0036:
+	case 0xB0037:
+	case 0xB0038:
+	case 0xB0040:
+	case 0xB0041:
+	case 0xB0042:
+	case 0xB0043:
+	case 0xB0047:
+	case 0xB0048:
+		/* SKU does not have FP Sensor, do not enable FPMCU */
+		break;
+	default:
 		/*
 		 * Assert FPMCU reset and enable power to FPMCU,
 		 * wait for power rail to stabilize,
@@ -26,8 +41,5 @@ void variant_ramstage_init(void)
 		mdelay(1);
 		gpio_output(GPP_C23, 1);
 		break;
-	default:
-		/* SKU does not have FP Sensor, do not enable FPMCU */
-		break;
 	}
 }

From 6186399a0f373c28009737c6cd7b95c96cef7bf5 Mon Sep 17 00:00:00 2001
From: Sowmya V <v.sowmya@intel.com>
Date: Wed, 14 Jan 2026 10:33:39 +0530
Subject: [PATCH 3376/3886] soc/intel/pantherlake: Add CD clock frequency
 control support

This change adds support for configuring higher CD Clock frequencies
for VGA SOL initialization during the Pre-Memory phase.
This feature allows BIOS to request specific display core clock
frequencies when VGA support is enabled during MRC training.

The VgaInitControl field in IGPU_PEI_PREMEM_CONFIG has been extended
to include BIT6-7 for CD Clock frequency selection:
* 0: No higher CD Clock required
* 1: 442 MHz
* 2: 461 MHz

BUG=b:458353982
TEST=Build and boot fatcat/lapis, verify display initialization.

Change-Id: I82fae0d21bb83ed26aad73b830ed15fcd626a9ae
Signed-off-by: Alok Agarwal <alok.agarwal@intel.com>
Signed-off-by: Sowmya V <v.sowmya@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90795
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/soc/intel/pantherlake/chip.h        | 13 +++++++++++++
 src/soc/intel/pantherlake/romstage/ux.c | 14 ++++++++++++++
 2 files changed, 27 insertions(+)

diff --git a/src/soc/intel/pantherlake/chip.h b/src/soc/intel/pantherlake/chip.h
index 96f9a936b5..0db0b14036 100644
--- a/src/soc/intel/pantherlake/chip.h
+++ b/src/soc/intel/pantherlake/chip.h
@@ -758,6 +758,19 @@ struct soc_intel_pantherlake_config {
 
 	/* Disable the progress bar during MRC training operations. */
 	bool disable_progress_bar;
+
+	/*
+	 * VgaInitControl CD Clock Frequency Selection
+	 * 0: CD_CLK_NONE - No higher CD Clock required
+	 * 1: CD_CLK_442MHZ - 441 MHz
+	 * 2: CD_CLK_461MHZ - 461 MHz
+	 */
+	enum cd_clock {
+		CD_CLK_NONE = 0,
+		CD_CLK_442MHZ,
+		CD_CLK_461MHZ,
+		MAX_CD_CLOCK = CD_CLK_461MHZ
+	} vga_cd_clk_freq_sel;
 };
 
 typedef struct soc_intel_pantherlake_config config_t;
diff --git a/src/soc/intel/pantherlake/romstage/ux.c b/src/soc/intel/pantherlake/romstage/ux.c
index e0a84257dc..4f9519b6e8 100644
--- a/src/soc/intel/pantherlake/romstage/ux.c
+++ b/src/soc/intel/pantherlake/romstage/ux.c
@@ -50,6 +50,17 @@ static void setup_vga_mode12_params(FSP_M_CONFIG *m_cfg, enum ux_locale_msg id)
 		m_cfg->VgaInitControl |= VGA_INIT_CONTROL_MODE12_MONOCHROME;
 }
 
+static void set_cd_clock(FSP_M_CONFIG *m_cfg, enum cd_clock clk)
+{
+	if (clk > MAX_CD_CLOCK) {
+		printk(BIOS_ERR, "CD Clock setting out of bounds!\n");
+		return;
+	}
+
+	m_cfg->VgaInitControl = (m_cfg->VgaInitControl & ~(0x3 << 6)) | (clk << 6);
+	printk(BIOS_DEBUG, "CD Clock: %d\n", clk);
+}
+
 static bool ux_inform_user_of_operation(const char *name, enum ux_locale_msg id,
 		 FSPM_UPD *mupd)
 {
@@ -90,6 +101,9 @@ static bool ux_inform_user_of_operation(const char *name, enum ux_locale_msg id,
 	m_cfg->VgaInitControl = VGA_INIT_CONTROL_ENABLE;
 	if (config->disable_progress_bar)
 		m_cfg->VgaInitControl |= VGA_INIT_DISABLE_ANIMATION;
+
+	set_cd_clock(m_cfg, config->vga_cd_clk_freq_sel);
+
 	m_cfg->VbtPtr = (efi_uintn_t)vbt;
 	m_cfg->VbtSize = vbt_size;
 	m_cfg->LidStatus = CONFIG(VBOOT_LID_SWITCH) ? get_lid_switch() : CONFIG(RUN_FSP_GOP);

From 5eb9e9999d986c313b96365b452941434a40441e Mon Sep 17 00:00:00 2001
From: Sowmya V <v.sowmya@intel.com>
Date: Tue, 17 Feb 2026 16:12:23 +0530
Subject: [PATCH 3377/3886] mb/google/fatcat: Configure CDCLK frequency for
 display

Configure the Core Display Clock (CDCLK) frequency selection by setting
the 'vga_cd_clk_freq_sel' register to CD_CLK_461MHZ in the fatcat
baseboard devicetree. This ensures the display engine operates at the
required frequency for the panel to meet the hardware configuration.

BUG=b:458353982
TEST=Build and boot fatcat/lapis, verify display initialization.

Change-Id: If8812bc66149b402adb7b9159f3a28d35903b785
Signed-off-by: Sowmya V <v.sowmya@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91309
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
---
 .../google/fatcat/variants/baseboard/fatcat/devicetree.cb        | 1 +
 1 file changed, 1 insertion(+)

diff --git a/src/mainboard/google/fatcat/variants/baseboard/fatcat/devicetree.cb b/src/mainboard/google/fatcat/variants/baseboard/fatcat/devicetree.cb
index fd1f55fabe..c9b9ddb293 100644
--- a/src/mainboard/google/fatcat/variants/baseboard/fatcat/devicetree.cb
+++ b/src/mainboard/google/fatcat/variants/baseboard/fatcat/devicetree.cb
@@ -141,6 +141,7 @@ chip soc/intel/pantherlake
 	register "pch_hda_idisp_codec_enable" = "true"
 
 	register "disable_progress_bar" = "true"
+	register "vga_cd_clk_freq_sel" = "CD_CLK_461MHZ"
 
 	device domain 0 on
 		device ref dtt on end

From d0e139437a5f60fb4ca068f50c9fe6d750aedc9c Mon Sep 17 00:00:00 2001
From: Sowmya V <v.sowmya@intel.com>
Date: Tue, 17 Feb 2026 17:04:29 +0530
Subject: [PATCH 3378/3886] mb/intel/ptlrvp: Configure CDCLK frequency for
 display

Configure the Core Display Clock (CDCLK) frequency selection by setting
the 'vga_cd_clk_freq_sel' register to CD_CLK_461MHZ in the ptlrvp
baseboard devicetree. This ensures the display engine operates at
the required frequency for the panel to meet the hardware configuration.

BUG=b:458353982
TEST=Build and boot ptlrvp, verify display initialization.

Change-Id: I34abb742ab5d95da4d21ea22da2b1bc7270f1a9c
Signed-off-by: Sowmya V <v.sowmya@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91311
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
---
 .../intel/ptlrvp/variants/baseboard/ptlrvp/devicetree.cb         | 1 +
 1 file changed, 1 insertion(+)

diff --git a/src/mainboard/intel/ptlrvp/variants/baseboard/ptlrvp/devicetree.cb b/src/mainboard/intel/ptlrvp/variants/baseboard/ptlrvp/devicetree.cb
index 83e99fb682..2f9ed9f8c6 100644
--- a/src/mainboard/intel/ptlrvp/variants/baseboard/ptlrvp/devicetree.cb
+++ b/src/mainboard/intel/ptlrvp/variants/baseboard/ptlrvp/devicetree.cb
@@ -83,6 +83,7 @@ chip soc/intel/pantherlake
 	register "pch_hda_idisp_codec_enable" = "true"
 
 	register "disable_progress_bar" = "true"
+	register "vga_cd_clk_freq_sel" = "CD_CLK_461MHZ"
 
 	device domain 0 on
 		device ref dtt on end

From ae2e78ce31714c2a3f3f6a4e03b9c7ae79dc76d7 Mon Sep 17 00:00:00 2001
From: Subrata Banik <subratabanik@google.com>
Date: Sun, 15 Feb 2026 22:29:44 +0530
Subject: [PATCH 3379/3886] mb/google/fatcat/var/moonstone: Configure CDCLK
 frequency for display

Configure the Core Display Clock (CDCLK) frequency selection by setting
the 'vga_cd_clk_freq_sel' register to 1 in the moonstone variant
overridetree. This ensures the display engine operates at the required
frequency (442Mhz) for the panel to meet the hardware configuration.

BUG=b:484559627
TEST=Build and boot google/moonstone, verify display initialization.

Change-Id: I4d3d0082f9f221333150bd5b427b3f20e7a2f154
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91236
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/google/fatcat/variants/moonstone/overridetree.cb | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/src/mainboard/google/fatcat/variants/moonstone/overridetree.cb b/src/mainboard/google/fatcat/variants/moonstone/overridetree.cb
index 7faed6236c..28b2fec984 100644
--- a/src/mainboard/google/fatcat/variants/moonstone/overridetree.cb
+++ b/src/mainboard/google/fatcat/variants/moonstone/overridetree.cb
@@ -87,6 +87,8 @@ chip soc/intel/pantherlake
 	register "cnvi_wifi_core" = "true"
 	register "cnvi_bt_core" = "true"
 
+	register "vga_cd_clk_freq_sel" = "CD_CLK_442MHZ"
+
 	register "serial_io_i2c_mode" = "{
 		[PchSerialIoIndexI2C0]  = PchSerialIoPci,
 		[PchSerialIoIndexI2C1] = PchSerialIoDisabled,

From ed5a993f0f98a47d5e780e375e5861860019b183 Mon Sep 17 00:00:00 2001
From: Sowmya V <v.sowmya@intel.com>
Date: Tue, 17 Feb 2026 16:23:10 +0530
Subject: [PATCH 3380/3886] mb/google/fatcat/lapis: Enable eSOL feature

This patch enables the eSOL feature for lapis.

BUG=b:458353982
TEST=Build and boot google/lapis, verify display initialization

Change-Id: I12cf423a48e6b497f3b79f26f40f7d16d87e6668
Signed-off-by: Sowmya V <v.sowmya@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91310
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: <srinivas.kulkarni@intel.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/google/fatcat/Kconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/src/mainboard/google/fatcat/Kconfig b/src/mainboard/google/fatcat/Kconfig
index 20889dbdf0..8f9029b2fc 100644
--- a/src/mainboard/google/fatcat/Kconfig
+++ b/src/mainboard/google/fatcat/Kconfig
@@ -143,6 +143,7 @@ config BOARD_GOOGLE_LAPIS
 	select EC_GOOGLE_CHROMEEC_LPC_GENERIC_MEMORY_RANGE
 	select HAVE_SLP_S0_GATE
 	select MAINBOARD_HAS_GOOGLE_STRAUSS_KEYBOARD
+	select FSP_UGOP_EARLY_SIGN_OF_LIFE
 
 config BOARD_GOOGLE_MOONSTONE
 	select BOARD_GOOGLE_BASEBOARD_FATCAT

From 08b05f56a6c44e1d802590edc6e4e628112ca66a Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Wed, 28 Jan 2026 11:16:09 -0600
Subject: [PATCH 3381/3886] Revert "mb/google/dedede/galtic: Add CFR option for
 touchpad type"

This reverts commit ee599486ac4a2aed195a7c53f8eec2832359110d.

Having the touchpad type selectable via CFR causes more user confusion
than is solves; switch to using SSFC/fw_config in a subsequent patch.

Change-Id: Ie35d1db19dd2f22ea19289f60dbd86cbf1fa137e
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90977
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/google/dedede/cfr.c             | 16 -------------
 .../dedede/variants/galtic/overridetree.cb    |  6 +++--
 .../google/dedede/variants/galtic/variant.c   | 24 -------------------
 3 files changed, 4 insertions(+), 42 deletions(-)

diff --git a/src/mainboard/google/dedede/cfr.c b/src/mainboard/google/dedede/cfr.c
index 63705fcd3d..50f85c90cb 100644
--- a/src/mainboard/google/dedede/cfr.c
+++ b/src/mainboard/google/dedede/cfr.c
@@ -24,21 +24,6 @@ static const struct sm_object touchscreen = SM_DECLARE_ENUM({
 #endif
 });
 
-static const struct sm_object touchpad = SM_DECLARE_ENUM({
-	.opt_name	= "touchpad",
-	.ui_name	= "Touchpad Type",
-	.ui_helptext	= "Select the model of the integrated touchpad device",
-	.default_value	= 0,
-	.values		= (const struct sm_enum_value[]) {
-		{ "Auto-select",	0		},
-		{ "ELAN0000",		1		},
-		{ "ELAN2702",		2		},
-		SM_ENUM_VALUE_END			},
-#if !CONFIG(BOARD_GOOGLE_GALTIC)
-	.flags		= CFR_OPTFLAG_SUPPRESS,
-#endif
-});
-
 static struct sm_obj_form system = {
 	.ui_name = "System",
 	.obj_list = (const struct sm_object *[]) {
@@ -69,7 +54,6 @@ static struct sm_obj_form devices = {
 	.ui_name = "Devices",
 	.obj_list = (const struct sm_object *[]) {
 		&touchscreen,
-		&touchpad,
 		NULL
 	},
 };
diff --git a/src/mainboard/google/dedede/variants/galtic/overridetree.cb b/src/mainboard/google/dedede/variants/galtic/overridetree.cb
index 8fbe6ead57..254d291ed8 100644
--- a/src/mainboard/google/dedede/variants/galtic/overridetree.cb
+++ b/src/mainboard/google/dedede/variants/galtic/overridetree.cb
@@ -150,15 +150,17 @@ chip soc/intel/jasperlake
 				register "desc" = ""ELAN Touchpad""
 				register "irq" = "ACPI_IRQ_WAKE_EDGE_LOW(GPP_B3_IRQ)"
 				register "wake" = "GPE0_DW0_03"
-				device i2c 15 alias elan0000 on end
+				register "detect" = "1"
+				device i2c 15 on end
 			end
 			chip drivers/i2c/hid
 				register "generic.hid" = ""ELAN2702""
 				register "generic.desc" = ""ELAN Touchpad""
 				register "generic.irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_B3_IRQ)"
 				register "generic.wake" = "GPE0_DW0_03"
+				register "generic.detect" = "1"
 				register "hid_desc_reg_offset" = "0x01"
-				device i2c 15 alias elan2702 on end
+				device i2c 15 on end
 			end
 		end
 		device ref i2c2 on
diff --git a/src/mainboard/google/dedede/variants/galtic/variant.c b/src/mainboard/google/dedede/variants/galtic/variant.c
index a3f91896c0..1e62f0c187 100644
--- a/src/mainboard/google/dedede/variants/galtic/variant.c
+++ b/src/mainboard/google/dedede/variants/galtic/variant.c
@@ -1,12 +1,8 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
-#include <baseboard/variants.h>
-#include <device/device.h>
 #include <ec/google/chromeec/ec.h>
 #include <fw_config.h>
-#include <option.h>
 #include <sar.h>
-#include <static.h>
 
 enum {
 	GALTIC_SKU_START    = 0x120000,
@@ -41,23 +37,3 @@ const char *get_wifi_sar_cbfs_filename(void)
 
 	return WIFI_SAR_CBFS_DEFAULT_FILENAME;
 }
-
-#define TP_TYPE_AUTO_SELECT 0
-#define TP_TYPE_ELAN0000 1
-#define TP_TYPE_ELAN2702 2
-
-void variant_devtree_update(void)
-{
-	struct device *tp_elan0000 = DEV_PTR(elan0000);
-	struct device *tp_elan2702 = DEV_PTR(elan2702);
-
-	/* Update touchpad device */
-	switch (get_uint_option("touchpad", TP_TYPE_AUTO_SELECT)) {
-	case TP_TYPE_ELAN0000:
-		tp_elan2702->enabled = 0;
-		break;
-	case TP_TYPE_ELAN2702:
-		tp_elan0000->enabled = 0;
-		break;
-	}
-}

From f1e4de7fbfe21a34fb536c12679bd5b5508fb475 Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Sun, 21 Jul 2024 10:57:37 -0500
Subject: [PATCH 3382/3886] mb/google/dedede/var/galtic: Add fw_config option
 for touchpad type

Galtic has two Elan touchpad options, and since both use the same i2c
address, the runtime i2c detection performed during SSDT generation
can't distinquish between them, leading to both devices being added
to the SSDT. This isn't a problem for Linux, but Windows can't
deal with two touchpads being enabled and using the same resources.

To mitigate this, add a new fw_config field which allows selection
between the two touchpad models, as well as a fallback option for
all devices which are not configured. Users who need to can set the
touchpad type in the SSFC using ectool, and then coreboot will
enable only the selected touchpad at boot.

TEST=build/boot google/dedede (galnat) after setting touchpad type
in SSFC. Verify correct touchpad selected via fw_config, only one
touchpad entry present in SSDT, and touchpad functional under both
Linux and Windows 11.

Change-Id: I36797eb5c8f262782380f95ff3c2e38443cf00c0
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83606
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
---
 .../google/dedede/variants/galtic/overridetree.cb | 15 +++++++++++++--
 1 file changed, 13 insertions(+), 2 deletions(-)

diff --git a/src/mainboard/google/dedede/variants/galtic/overridetree.cb b/src/mainboard/google/dedede/variants/galtic/overridetree.cb
index 254d291ed8..0ccfbfa519 100644
--- a/src/mainboard/google/dedede/variants/galtic/overridetree.cb
+++ b/src/mainboard/google/dedede/variants/galtic/overridetree.cb
@@ -9,6 +9,11 @@ fw_config
 		option AUDIO_CODEC_ALC5682 1
 		option AUDIO_CODEC_ALC5682I_VS 2
 	end
+	field TOUCHPAD_SOURCE 62 63
+		option TOUCHPAD_UNPROVISIONED 0
+		option TOUCHPAD_ELAN0000 1
+		option TOUCHPAD_ELAN2702 2
+	end
 end
 
 chip soc/intel/jasperlake
@@ -151,7 +156,10 @@ chip soc/intel/jasperlake
 				register "irq" = "ACPI_IRQ_WAKE_EDGE_LOW(GPP_B3_IRQ)"
 				register "wake" = "GPE0_DW0_03"
 				register "detect" = "1"
-				device i2c 15 on end
+				device i2c 15 on
+					probe TOUCHPAD_SOURCE TOUCHPAD_UNPROVISIONED
+					probe TOUCHPAD_SOURCE TOUCHPAD_ELAN0000
+				end
 			end
 			chip drivers/i2c/hid
 				register "generic.hid" = ""ELAN2702""
@@ -160,7 +168,10 @@ chip soc/intel/jasperlake
 				register "generic.wake" = "GPE0_DW0_03"
 				register "generic.detect" = "1"
 				register "hid_desc_reg_offset" = "0x01"
-				device i2c 15 on end
+				device i2c 15 on
+					probe TOUCHPAD_SOURCE TOUCHPAD_UNPROVISIONED
+					probe TOUCHPAD_SOURCE TOUCHPAD_ELAN2702
+				end
 			end
 		end
 		device ref i2c2 on

From 339ef9b5c9297019330259828b278dab2f524cdc Mon Sep 17 00:00:00 2001
From: Patrick Rudolph <patrick.rudolph@9elements.com>
Date: Thu, 12 Feb 2026 07:11:47 +0100
Subject: [PATCH 3383/3886] soc/intel/common/block/lpc: Improve automatic
 window opening
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

When an existing LPC window covers an IO range, but is bigger or starts
earlier the current code doesn't recognize it. It will open another
window overlapping an existing one.

Check if an existing LPC IO window covers the current one and allow it
to be bigger than the entry.

TEST=Thinkpad X280 still boots and error messages are gone.

Should fix the following line seen in the coreboot log of the Lenovo
T480 and compatible:
[ERROR]  LPC: Cannot open IO window: 1604 size 1
[ERROR]  No more IO windows
[ERROR]  LPC: Cannot open IO window: 1606 size 1
[ERROR]  No more IO windows
[ERROR]  LPC: Cannot open IO window: 1610 size 10
[ERROR]  No more IO windows

Change-Id: I586066238b801d2abb1122698fb4092ee0b2f6b9
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91171
Reviewed-by: Ladislav Ezr <ladislav@ezr.cz>
Reviewed-by: Johann C Rode <jcrode82@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/soc/intel/common/block/lpc/lpc_lib.c | 19 +++++++++++++------
 1 file changed, 13 insertions(+), 6 deletions(-)

diff --git a/src/soc/intel/common/block/lpc/lpc_lib.c b/src/soc/intel/common/block/lpc/lpc_lib.c
index 9a7165baaf..337a098848 100644
--- a/src/soc/intel/common/block/lpc/lpc_lib.c
+++ b/src/soc/intel/common/block/lpc/lpc_lib.c
@@ -169,14 +169,17 @@ void lpc_open_pmio_window(uint16_t base, uint16_t size)
 		alignment = 1UL << (log2_ceil(window_size));
 		window_size = ALIGN_UP(window_size, alignment);
 
-		/* Address[15:2] in LGIR[15:12] and Mask[7:2] in LGIR[23:18]. */
-		lgir = (bridge_base & LPC_LGIR_ADDR_MASK) | LPC_LGIR_EN;
-		lgir |= ((window_size - 1) << 16) & LPC_LGIR_AMASK_MASK;
+		const struct region win = region_create(bridge_base, window_size);
 
-		/* Skip programming if same range already programmed. */
+		/* Skip programming if covered by existing window. */
 		for (i = 0; i < LPC_NUM_GENERIC_IO_RANGES; i++) {
-			if (lgir == pci_read_config32(PCH_DEV_LPC,
-						LPC_GENERIC_IO_RANGE(i)))
+			const u32 reg32 = pci_read_config32(PCH_DEV_LPC, LPC_GENERIC_IO_RANGE(i));
+			if (!(reg32 & LPC_LGIR_EN))
+				continue;
+			const struct region exist = region_create(reg32 & LPC_LGIR_ADDR_MASK,
+							1 + ((reg32 & LPC_LGIR_AMASK_MASK) >> 16));
+
+			if (region_is_subregion(&exist, &win))
 				return;
 		}
 
@@ -190,6 +193,10 @@ void lpc_open_pmio_window(uint16_t base, uint16_t size)
 		}
 		lgir_reg_offset = LPC_GENERIC_IO_RANGE(lgir_reg_num);
 
+		/* Address[15:2] in LGIR[15:12] and Mask[7:2] in LGIR[23:18]. */
+		lgir = (bridge_base & LPC_LGIR_ADDR_MASK) | LPC_LGIR_EN;
+		lgir |= ((window_size - 1) << 16) & LPC_LGIR_AMASK_MASK;
+
 		pci_write_config32(PCH_DEV_LPC, lgir_reg_offset, lgir);
 		if (CONFIG(SOC_INTEL_COMMON_BLOCK_LPC_MIRROR_TO_GPMR))
 			gpmr_write32(GPMR_LPCLGIR1 + lgir_reg_num * 4, lgir);

From c996684f408dedab3d9a96c5e3bdff2339a74c14 Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Wed, 18 Feb 2026 13:23:55 +0000
Subject: [PATCH 3384/3886] intel/smm: make TCO INTRUDER# SMI optional

Some platforms can have INTRUDER# asserted continuously. If it is routed
to SMI, this can cause an SMI storm and prevent boot.

Introduce SOC_INTEL_COMMON_BLOCK_SMM_TCO_INTRUDER_SMI_ENABLE to control
whether INTRUDER# is routed to SMI, while keeping TCO SMIs available for
other uses (e.g. SPI sync SMIs needed by BOOTMEDIA_SMM_BWP).

TEST=build

Change-Id: I33eb8ce3bee64c95a4d5a6f95a096577d55c742d
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91335
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
---
 src/soc/intel/common/block/smbus/tco.c | 11 +++++------
 src/soc/intel/common/block/smm/Kconfig |  9 +++++++++
 2 files changed, 14 insertions(+), 6 deletions(-)

diff --git a/src/soc/intel/common/block/smbus/tco.c b/src/soc/intel/common/block/smbus/tco.c
index b7c9922590..fa462e0921 100644
--- a/src/soc/intel/common/block/smbus/tco.c
+++ b/src/soc/intel/common/block/smbus/tco.c
@@ -102,15 +102,15 @@ static void tco_timer_disable(void)
 	tco_write_reg(TCO1_CNT, tcocnt);
 }
 
-/* Enable and initialize TCO intruder SMI */
-static void tco_intruder_smi_enable(void)
+/* Configure TCO intruder routing */
+static void tco_intruder_smi_configure(void)
 {
 	uint16_t tcocnt;
 
-	/* Make TCO issue an SMI on INTRD_DET assertion */
 	tcocnt = tco_read_reg(TCO2_CNT);
 	tcocnt &= ~TCO2_INTRD_SEL_MASK;
-	tcocnt |= TCO2_INTRD_SEL_SMI;
+	if (CONFIG(SOC_INTEL_COMMON_BLOCK_SMM_TCO_INTRUDER_SMI_ENABLE))
+		tcocnt |= TCO2_INTRD_SEL_SMI;
 	tco_write_reg(TCO2_CNT, tcocnt);
 }
 
@@ -148,9 +148,8 @@ void tco_configure(void)
 
 	tco_timer_disable();
 
-	/* Enable intruder interrupt if TCO interrupts are enabled*/
 	if (CONFIG(SOC_INTEL_COMMON_BLOCK_SMM_TCO_ENABLE))
-		tco_intruder_smi_enable();
+		tco_intruder_smi_configure();
 }
 
 uint32_t tco_get_timer_period(void)
diff --git a/src/soc/intel/common/block/smm/Kconfig b/src/soc/intel/common/block/smm/Kconfig
index 84c406ef3e..446c371bce 100644
--- a/src/soc/intel/common/block/smm/Kconfig
+++ b/src/soc/intel/common/block/smm/Kconfig
@@ -30,6 +30,15 @@ config SOC_INTEL_COMMON_BLOCK_SMM_TCO_ENABLE
 	help
 	  Enable TCO SMI source to e.g. handle case instrusion.
 
+config SOC_INTEL_COMMON_BLOCK_SMM_TCO_INTRUDER_SMI_ENABLE
+	bool "Enable TCO INTRUDER# SMI"
+	depends on SOC_INTEL_COMMON_BLOCK_SMM_TCO_ENABLE
+	default y
+	help
+	  When enabled, route the TCO INTRUDER# event to SMI.
+	  Some boards may see INTRUDER# asserted continuously. Routing it to
+	  SMI would then cause an SMI storm and prevent boot.
+
 config SOC_INTEL_COMMON_BLOCK_SMM_S5_DELAY_MS
 	int
 	default 100 if CHROMEOS

From afeca9f42281c0b38ba80981f17550fff5d3dc09 Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Wed, 18 Feb 2026 13:24:14 +0000
Subject: [PATCH 3385/3886] mb/starlabs: disable TCO INTRUDER# SMI by default

INTRUDER# may be asserted continuously on some Star Labs systems.
Disable routing the event to SMI by default to avoid SMI storms when TCO
SMIs are enabled (e.g. via BOOTMEDIA_SMM_BWP).

This allows boards, like starbook_tgl, which assert INTRUDER# constantly
to boot.

TEST=build/boot starbook_tgl with BOOTMEDIA_SMM_BWP selected

Change-Id: I6a2a188a295cc6be3af2043ea902d45c5bb5b95d
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91336
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
---
 src/mainboard/starlabs/common/Kconfig | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/src/mainboard/starlabs/common/Kconfig b/src/mainboard/starlabs/common/Kconfig
index f5496b05c0..adeda59bdf 100644
--- a/src/mainboard/starlabs/common/Kconfig
+++ b/src/mainboard/starlabs/common/Kconfig
@@ -17,6 +17,9 @@ config MB_COMMON_DIR
 	string
 	default "starlabs/common"
 
+config SOC_INTEL_COMMON_BLOCK_SMM_TCO_INTRUDER_SMI_ENABLE
+	default n
+
 source "src/mainboard/starlabs/common/hda/Kconfig"
 
 endmenu

From 7876bcaa86c61ea8809f0f6d4aa38455c025a8eb Mon Sep 17 00:00:00 2001
From: Keith Hui <buurin@gmail.com>
Date: Tue, 16 Apr 2024 14:36:01 -0400
Subject: [PATCH 3386/3886] sio/nuvoton: Implement common ramstage
 keyboard/ACPI init routines

With few exceptions, Nuvoton super I/O chips have the same
configuration registers.

This patch provides a single set of initialization routines to set
up power loss resume, initialize keyboard, and handle switching
PS/2 port role for mainboards with only one PS/2 port.
Power loss resume handling and PS/2 port role switching can be
controlled using nvram or CFR options. Mainboards lacking such
options will need to add them separately.

The common routines support all currently in-tree Nuvoton SIO chips
except nct5104d, nct6687d, npcd378, wpcm450. They will be hooked up
in follow-up patches.

There is also SMM code to disable PS/2 keyboard wakeup before going to
S5, otherwise the system will also power up with any key on the
keyboard, which is most likely undesirable. To use this, mainboards
must set Kconfig SUPERIO_NUVOTON_PNP_BASE, add smm.c to Makefile.mk
and call it from mainboard_smi_sleep().

Update the help text of HAVE_SHARED_PS2_PORT Kconfig with the final
option name used.

TEST=Both power loss resume and PS/2 port role control work on
asus/p8z77-m with entire train of supporting patches applied.

Change-Id: Ibaddcaa2d77c5b06ddfbb6dbaac00df5e72dd4bd
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82632
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
---
 src/superio/nuvoton/Makefile.mk      |   2 +
 src/superio/nuvoton/common/Kconfig   |   5 +-
 src/superio/nuvoton/common/common.c  | 137 +++++++++++++++++++++++++++
 src/superio/nuvoton/common/nuvoton.h |  19 +++-
 src/superio/nuvoton/common/smm.c     |  31 ++++++
 5 files changed, 190 insertions(+), 4 deletions(-)
 create mode 100644 src/superio/nuvoton/common/common.c
 create mode 100644 src/superio/nuvoton/common/smm.c

diff --git a/src/superio/nuvoton/Makefile.mk b/src/superio/nuvoton/Makefile.mk
index f56f5f4734..eab992a666 100644
--- a/src/superio/nuvoton/Makefile.mk
+++ b/src/superio/nuvoton/Makefile.mk
@@ -3,6 +3,8 @@
 ## include generic nuvoton pre-ram stage driver
 bootblock-$(CONFIG_SUPERIO_NUVOTON_COMMON_PRE_RAM) += common/early_serial.c
 romstage-$(CONFIG_SUPERIO_NUVOTON_COMMON_PRE_RAM) += common/early_serial.c
+## include generic nuvoton helper
+ramstage-$(CONFIG_SUPERIO_NUVOTON_COMMON_PRE_RAM) += common/common.c
 
 subdirs-$(CONFIG_SUPERIO_NUVOTON_WPCM450) += wpcm450
 subdirs-$(CONFIG_SUPERIO_NUVOTON_NCT5104D) += nct5104d
diff --git a/src/superio/nuvoton/common/Kconfig b/src/superio/nuvoton/common/Kconfig
index 2525c5d445..f3e8e4ae93 100644
--- a/src/superio/nuvoton/common/Kconfig
+++ b/src/superio/nuvoton/common/Kconfig
@@ -18,9 +18,8 @@ config HAVE_SHARED_PS2_PORT
 	help
 	  Select this option if your mainboard has a single PS/2 port for both keyboard and
 	  mouse, and where a Y-cable cannot allow both keyboard and mouse to work off the same
-	  port. This one port usually works for keyboards only. Add the nvram option
-	  "swap_keyboard_and_mouse" to cmos.layout to allow changing this port into a
-	  mouse port.
+	  port. This one port usually works for keyboards only. Add the nvram/CFR option
+	  "ps2_port_role" to allow changing this port into a mouse port.
 
 config SUPERIO_NUVOTON_PNP_BASE
 	hex
diff --git a/src/superio/nuvoton/common/common.c b/src/superio/nuvoton/common/common.c
new file mode 100644
index 0000000000..e2948cfb2d
--- /dev/null
+++ b/src/superio/nuvoton/common/common.c
@@ -0,0 +1,137 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+/*
+ * Configuration routines common to Nuvoton SIO chips,
+ * except nct5104d, nct6687d, npcd378, wpcm450.
+ */
+
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pnp.h>
+#include <option.h>
+#include <pc80/keyboard.h>
+#include <superio/conf_mode.h>
+#include "nuvoton.h"
+
+#define MAINBOARD_POWER_OFF	0
+#define MAINBOARD_POWER_ON	1
+#define MAINBOARD_POWER_KEEP	2
+
+#define POWER_LOSS_CONTROL_SHIFT	5
+#define POWER_LOSS_CONTROL_MASK		(3 << POWER_LOSS_CONTROL_SHIFT)
+
+/* CR 0xe0 */
+#define KBD_WAKEUP_PSOUT	BIT(6)
+#define KBD_MS_SWAP		BIT(2)
+#define KBXKEY			BIT(0)
+/* CR 0xe4 */
+/* Power RAM in S3; for reference only; this needs to be enabled in bootblock */
+#define EN_3VSBSW		BIT(4)
+#define KBD_WAKEUP_ANYKEY	BIT(3)
+
+static void enable_ps2_mouse(struct device *dev, bool en)
+{
+	if (!CONFIG(HAVE_SHARED_PS2_PORT))
+		return;
+
+	pnp_enter_conf_mode(dev);
+	u8 bit = KBD_MS_SWAP;
+	/* pnp_set_logical_device() is not used because the bit is in another LD. */
+	pnp_write_config(dev, 0x7, NCT677X_ACPI);
+	pnp_unset_and_set_config(dev, 0xe0, bit, en ? bit : 0);
+	pnp_exit_conf_mode(dev);
+}
+
+void nuvoton_common_init(struct device *dev)
+{
+	u8 byte, role, mask;
+
+	if (!dev->enabled)
+		return;
+
+	switch (dev->path.pnp.device) {
+	case NCT677X_KBC:
+		/*
+		 * If mainboard has both PS/2 keyboard and mouse ports, bootblock code
+		 * should enable both and leave them enabled.
+		 */
+		role = PS2_PORT_ROLE_KEYBOARD;
+		if (CONFIG(HAVE_SHARED_PS2_PORT)) {
+			role = get_uint_option("ps2_port_role", PS2_PORT_ROLE_KEYBOARD);
+			if (role > PS2_PORT_ROLE_AUTO)
+				break; /* Invalid setting; abort */
+		}
+		if (role != PS2_PORT_ROLE_KEYBOARD) {
+			enable_ps2_mouse(dev, true);
+			if (role == PS2_PORT_ROLE_MOUSE)
+				break; /* Leave the port swapped; we're done */
+
+			/* This leaves PS2_PORT_ROLE_AUTO */
+			if (pc_keyboard_init(PROBE_AUX_DEVICE)) {
+				break; /* Mouse found; leave the port swapped */
+			} else {
+				printk(BIOS_INFO, "%s: Mouse not detected.\n", __func__);
+			}
+		}
+		/* Set port as keyboard, and initialize keyboard if enabled in Kconfig */
+		enable_ps2_mouse(dev, false);
+		pc_keyboard_init(NO_AUX_DEVICE);
+		break;
+	case NCT677X_ACPI:
+		pnp_enter_conf_mode(dev);
+		pnp_set_logical_device(dev);
+
+		/*
+		 * Keyboard wakeup: any key
+		 * NOTE: Bits related to keyboard wakeup are kept even in S5 (soft off),
+		 *       and will allow keyboard to wake system even from this state.
+		 *       Add SMM/ACPI code to turn it back off before entering S5.
+		 */
+		pnp_unset_and_set_config(dev, 0xe0, 0, KBD_WAKEUP_PSOUT | KBXKEY);
+
+		byte = KBD_WAKEUP_ANYKEY;
+		mask = 0;
+		/*
+		 * Set power state after power fail.
+		 *
+		 * Important: Make sure the definitions in mainboard/Kconfig around
+		 * MAINBOARD_POWER_FAILURE_STATE and your board's cmos.layout match.
+		 * And if MAINBOARD_POWER_FAILURE_STATE deviates from the chip's
+		 * expectation (ie. 0=off, 1=on, 2=keep), this code must be adapted.
+		 */
+		if (CONFIG(HAVE_POWER_STATE_AFTER_FAILURE)) {
+			unsigned int power_status = get_uint_option("power_on_after_fail",
+				CONFIG_MAINBOARD_POWER_FAILURE_STATE);
+
+			switch (power_status) {
+			case MAINBOARD_POWER_KEEP:
+				/*
+				 * KEEP power state is software emulated using USER and
+				 * a manually set power state.
+				 */
+				power_status = 3;
+				__fallthrough;
+			case MAINBOARD_POWER_OFF:
+			case MAINBOARD_POWER_ON:
+				byte |= (power_status << POWER_LOSS_CONTROL_SHIFT);
+				mask = POWER_LOSS_CONTROL_MASK;
+				break;
+			}
+			/* Log a "on" power state */
+			pnp_unset_and_set_config(dev, 0xe6, BIT(4), 0);
+		}
+
+		pnp_unset_and_set_config(dev, 0xe4, mask, byte);
+		pnp_exit_conf_mode(dev);
+		break;
+	}
+}
+
+struct device_operations nuvoton_common_ops = {
+	.read_resources   = noop_read_resources,
+	.set_resources    = pnp_set_resources,
+	.enable_resources = pnp_enable_resources,
+	.enable           = pnp_alt_enable,
+	.init             = nuvoton_common_init,
+	.ops_pnp_mode     = &pnp_conf_mode_8787_aa,
+};
diff --git a/src/superio/nuvoton/common/nuvoton.h b/src/superio/nuvoton/common/nuvoton.h
index 77eafeb240..1dd20923e0 100644
--- a/src/superio/nuvoton/common/nuvoton.h
+++ b/src/superio/nuvoton/common/nuvoton.h
@@ -4,6 +4,7 @@
 #define SUPERIO_NUVOTON_COMMON_H
 
 #ifndef __ACPI__
+#include <device/device.h>
 #include <device/pnp_type.h>
 #include <stdint.h>
 
@@ -31,11 +32,27 @@ static __always_inline void nuvoton_pnp_exit_conf_state(pnp_devfn_t dev)
 	outb(NUVOTON_EXIT_KEY, port);
 }
 
+void nuvoton_enable_serial(pnp_devfn_t dev, u16 iobase);
 #endif /* SIMPLE_DEVICE */
 
-void nuvoton_enable_serial(pnp_devfn_t dev, u16 iobase);
+#if ENV_RAMSTAGE
+extern struct device_operations nuvoton_common_ops;
+
+void nuvoton_common_init(struct device *dev);
 #endif
 
+#if ENV_SMM
+void nuvoton_smi_sleep(u8 slp_typ);
+#endif
+
+enum e_ps2role {
+	PS2_PORT_ROLE_KEYBOARD	= 0,
+	PS2_PORT_ROLE_MOUSE	= 1,
+	PS2_PORT_ROLE_AUTO	= 2
+};
+
+#endif /* __ACPI__ */
+
 /*
  * Logical Device Numbers (LDN) common to all Nuvoton SIOs.
  * Because they will be incorporated into ACPI device IDs,
diff --git a/src/superio/nuvoton/common/smm.c b/src/superio/nuvoton/common/smm.c
new file mode 100644
index 0000000000..9fdefc43b6
--- /dev/null
+++ b/src/superio/nuvoton/common/smm.c
@@ -0,0 +1,31 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+/*
+ * SMM routines common to Nuvoton NCTxxxx SIO chips,
+ * except 5104, 6687, npcd378, wpcm450.
+ */
+
+/* SMM code needs to be kept simple */
+#define __SIMPLE_DEVICE__
+
+#include <assert.h>
+#include <acpi/acpi.h>
+#include <arch/io.h>
+#include <device/pnp_ops.h>
+#include "nuvoton.h"
+
+#define ACPI_DEV   PNP_DEV(CONFIG_SUPERIO_NUVOTON_PNP_BASE, NCT677X_ACPI)
+
+void nuvoton_smi_sleep(u8 slp_typ)
+{
+	if (slp_typ != ACPI_S5)
+		return;
+
+	_Static_assert(CONFIG_SUPERIO_NUVOTON_PNP_BASE != 0,
+	       "Kconfig SUPERIO_NUVOTON_PNP_BASE must be set!");
+	nuvoton_pnp_enter_conf_state(ACPI_DEV);
+	pnp_set_logical_device(ACPI_DEV);
+	pnp_unset_and_set_config(ACPI_DEV, 0xe0, BIT(6), 0); /* KB wakeup off */
+	pnp_unset_and_set_config(ACPI_DEV, 0xe6, 0, BIT(4)); /* Power off */
+	nuvoton_pnp_exit_conf_state(ACPI_DEV);
+}

From c30802d6fbd7f92b05eaf2cb7e8383a780b342ea Mon Sep 17 00:00:00 2001
From: Keith Hui <buurin@gmail.com>
Date: Fri, 19 Dec 2025 00:56:47 -0500
Subject: [PATCH 3387/3886] sio/nuvoton/nct6779d: Enable common ASL code

Define the requisite super I/O chip identities and bring in the common
ACPI code.

Change-Id: I1db85c8d0028a1c3e4a5582f3d0e503b71beac70
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90574
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
---
 src/superio/nuvoton/nct6779d/acpi/superio.asl | 15 +++++++++++++++
 1 file changed, 15 insertions(+)
 create mode 100644 src/superio/nuvoton/nct6779d/acpi/superio.asl

diff --git a/src/superio/nuvoton/nct6779d/acpi/superio.asl b/src/superio/nuvoton/nct6779d/acpi/superio.asl
new file mode 100644
index 0000000000..181f198564
--- /dev/null
+++ b/src/superio/nuvoton/nct6779d/acpi/superio.asl
@@ -0,0 +1,15 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef SUPERIO_CHIP_NAME
+#define SUPERIO_CHIP_NAME NCT6779D
+#endif
+
+#ifndef SUPERIO_FULL_CHIP_NAME
+#define SUPERIO_FULL_CHIP_NAME "Nuvoton NCT6779D Super I/O"
+#endif
+
+/*
+ * See ASL file below for details of defines to control
+ * device visibilities.
+ */
+#include <superio/nuvoton/common/acpi/superio.asl>

From 4cee52e457f946854065885893ec88a3e726190c Mon Sep 17 00:00:00 2001
From: Keith Hui <buurin@gmail.com>
Date: Fri, 19 Dec 2025 00:59:09 -0500
Subject: [PATCH 3388/3886] sio/nuvoton/nct6791d: Enable common ASL code

Define the requisite super I/O chip identities and bring in the common
ACPI code.

Change-Id: I2fbd77b0ddc5618a2da844f6e18ce483774c4cf0
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90575
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
---
 src/superio/nuvoton/nct6791d/acpi/superio.asl | 15 +++++++++++++++
 1 file changed, 15 insertions(+)
 create mode 100644 src/superio/nuvoton/nct6791d/acpi/superio.asl

diff --git a/src/superio/nuvoton/nct6791d/acpi/superio.asl b/src/superio/nuvoton/nct6791d/acpi/superio.asl
new file mode 100644
index 0000000000..d9fcb50f44
--- /dev/null
+++ b/src/superio/nuvoton/nct6791d/acpi/superio.asl
@@ -0,0 +1,15 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef SUPERIO_CHIP_NAME
+#define SUPERIO_CHIP_NAME NCT6791D
+#endif
+
+#ifndef SUPERIO_FULL_CHIP_NAME
+#define SUPERIO_FULL_CHIP_NAME "Nuvoton NCT6791D Super I/O"
+#endif
+
+/*
+ * See ASL file below for details of defines to control
+ * device visibilities.
+ */
+#include <superio/nuvoton/common/acpi/superio.asl>

From 94a356e0c820a7913a6f8a62c24a62c258f8b621 Mon Sep 17 00:00:00 2001
From: Keith Hui <buurin@gmail.com>
Date: Thu, 23 Oct 2025 19:45:40 -0400
Subject: [PATCH 3389/3886] sio/nuvoton/nct5535d: Use common ASL code

Make this chip use the common Nuvoton ACPI code before mainboards using
this chip begin to come online.

Change-Id: I000ebc92d1c408a865fb803a2e540ca3cca53ee7
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89742
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
---
 src/superio/nuvoton/nct5535d/acpi/superio.asl | 176 +-----------------
 1 file changed, 8 insertions(+), 168 deletions(-)

diff --git a/src/superio/nuvoton/nct5535d/acpi/superio.asl b/src/superio/nuvoton/nct5535d/acpi/superio.asl
index c23c3b47bf..332792b14b 100644
--- a/src/superio/nuvoton/nct5535d/acpi/superio.asl
+++ b/src/superio/nuvoton/nct5535d/acpi/superio.asl
@@ -1,175 +1,15 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
-/*
- * Include this file into a mainboard's DSDT _SB device tree and it will
- * expose the NCT5535D SuperIO and some of its functionality.
- *
- * It allows the change of IO ports, IRQs and DMA settings on logical
- * devices, disabling and reenabling logical devices.
- *
- *   LDN		State
- * 0x2 SP1		Implemented, untested
- * 0x5 KBC		Implemented, untested
- * 0x8 GPIO		Implemented, untested
- * 0xb HWM		Implemented, untested
- *
- * Controllable through preprocessor defines:
- * SUPERIO_DEV		Device identifier for this SIO (e.g. SIO0)
- * SUPERIO_PNP_BASE	I/O address of the first PnP configuration register
- * NCT5535D_SHOW_SP1	If defined, Serial Port 1 will be exposed.
- * NCT5535D_SHOW_KBC	If defined, the Keyboard Controller will be exposed.
- * NCT5535D_SHOW_GPIO	If defined, GPIO support will be exposed.
- * NCT5535D_SHOW_HWM	If defined, the Environment Controller will be exposed.
- */
-#include <superio/nuvoton/nct5535d/nct5535d.h>
-
-#undef SUPERIO_CHIP_NAME
+#ifndef SUPERIO_CHIP_NAME
 #define SUPERIO_CHIP_NAME NCT5535D
-#include <superio/acpi/pnp.asl>
-
-#undef PNP_DEFAULT_PSC
-#define PNP_DEFAULT_PSC Return (0) /* no power management */
-
-#define ENABLE_KEYBOARD_WAKEUP SKWK
-#define POWER_LOSS_CONTROL     SPWL
-
-Device(SUPERIO_DEV) {
-	Name (_HID, EisaId("PNP0A05"))
-	Name (_STR, Unicode("Nuvoton NCT5535D Super I/O"))
-	Name (_UID, SUPERIO_UID(SUPERIO_DEV,))
-
-	/* SuperIO configuration ports */
-	OperationRegion (CREG, SystemIO, SUPERIO_PNP_BASE, 2)
-	Field (CREG, ByteAcc, NoLock, Preserve)
-	{
-		PNP_ADDR_REG,	8,
-		PNP_DATA_REG,	8,
-	}
-	IndexField (PNP_ADDR_REG, PNP_DATA_REG, ByteAcc, NoLock, Preserve)
-	{
-		Offset (0x07),
-		PNP_LOGICAL_DEVICE,	8, /* Logical device selector */
-
-		Offset (0x30),
-		PNP_DEVICE_ACTIVE,	1, /* Logical device activation */
-		ACT1,			1, /* Logical device activation */
-		ACT2,			1, /* Logical device activation */
-		ACT3,			1, /* Logical device activation */
-		ACT4,			1, /* Logical device activation */
-		ACT5,			1, /* Logical device activation */
-		ACT6,			1, /* Logical device activation */
-		ACT7,			1, /* Logical device activation */
-
-		Offset (0x60),
-		PNP_IO0_HIGH_BYTE,	8, /* First I/O port base - high byte */
-		PNP_IO0_LOW_BYTE,	8, /* First I/O port base - low byte */
-		Offset (0x62),
-		PNP_IO1_HIGH_BYTE,	8, /* Second I/O port base - high byte */
-		PNP_IO1_LOW_BYTE,	8, /* Second I/O port base - low byte */
-
-		Offset (0x70),
-		PNP_IRQ0,		8, /* First IRQ */
-		Offset (0x72),
-		PNP_IRQ1,		8, /* Second IRQ */
-		Offset (0x74),
-		PNP_DMA0,		8, /* DRQ */
-		Offset (0xe0),		   /* Config register 0xe0 etc. */
-		,6,
-		ENABLE_KEYBOARD_WAKEUP,	1,
-		Offset (0xe4),
-		,5,
-		POWER_LOSS_CONTROL,	2,
-	}
-
-	Method (_CRS)
-	{
-		/* Announce the used I/O ports to the OS */
-		Return (ResourceTemplate () {
-			IO (Decode16, SUPERIO_PNP_BASE, SUPERIO_PNP_BASE, 0x01, 0x02)
-		})
-	}
-
-	Method (SIOS, 1, NotSerialized)
-	{
-		if (Arg0 == 5)
-		{
-			ENTER_CONFIG_MODE(NCT5535D_ACPI)
-			ENABLE_KEYBOARD_WAKEUP = 0
-			EXIT_CONFIG_MODE()
-		}
-	}
-
-	Method (SIOW, 1, NotSerialized)
-	{
-	}
-
-	#undef PNP_ENTER_MAGIC_1ST
-	#undef PNP_ENTER_MAGIC_2ND
-	#undef PNP_ENTER_MAGIC_3RD
-	#undef PNP_ENTER_MAGIC_4TH
-	#undef PNP_EXIT_MAGIC_1ST
-	#undef PNP_EXIT_SPECIAL_REG
-	#undef PNP_EXIT_SPECIAL_VAL
-	#define PNP_ENTER_MAGIC_1ST	0x87
-	#define PNP_ENTER_MAGIC_2ND	0x87
-	#define PNP_EXIT_MAGIC_1ST	0xaa
-	#include <superio/acpi/pnp_config.asl>
-
-#ifdef NCT5535D_SHOW_SP1
-	#undef SUPERIO_UART_LDN
-	#undef SUPERIO_UART_DDN
-	#undef SUPERIO_UART_PM_REG
-	#undef SUPERIO_UART_PM_VAL
-	#undef SUPERIO_UART_PM_LDN
-	#define SUPERIO_UART_LDN NCT5535D_SP1
-	#include <superio/acpi/pnp_uart.asl>
 #endif
 
-#ifdef NCT5535D_SHOW_KBC
-	#undef SUPERIO_KBC_LDN
-	#undef SUPERIO_KBC_PS2M
-	#undef SUPERIO_KBC_PS2LDN
-	#define SUPERIO_KBC_LDN NCT5535D_KBC
-	#define SUPERIO_KBC_PS2M
-	#include <superio/acpi/pnp_kbc.asl>
+#ifndef SUPERIO_FULL_CHIP_NAME
+#define SUPERIO_FULL_CHIP_NAME "Nuvoton NCT5535D Super I/O"
 #endif
 
-#ifdef NCT5535D_SHOW_HWM
-	#undef SUPERIO_PNP_HID
-	#undef SUPERIO_PNP_LDN
-	#undef SUPERIO_PNP_DDN
-	#undef SUPERIO_PNP_NO_DIS
-	#undef SUPERIO_PNP_PM_REG
-	#undef SUPERIO_PNP_PM_VAL
-	#undef SUPERIO_PNP_PM_LDN
-	#undef SUPERIO_PNP_IO0
-	#undef SUPERIO_PNP_IO1
-	#undef SUPERIO_PNP_IO2
-	#undef SUPERIO_PNP_IRQ0
-	#undef SUPERIO_PNP_IRQ1
-	#undef SUPERIO_PNP_DMA
-	#define SUPERIO_PNP_LDN NCT5535D_HWM_FPLED
-	#define SUPERIO_PNP_IO0 0x08, 0x08
-	#define SUPERIO_PNP_IO1 0x08, 0x08
-	#define SUPERIO_PNP_IRQ0
-	#include <superio/acpi/pnp_generic.asl>
-#endif
-
-#ifdef NCT5535D_SHOW_GPIO
-	#undef SUPERIO_PNP_HID
-	#undef SUPERIO_PNP_LDN
-	#undef SUPERIO_PNP_DDN
-	#undef SUPERIO_PNP_NO_DIS
-	#undef SUPERIO_PNP_PM_REG
-	#undef SUPERIO_PNP_PM_VAL
-	#undef SUPERIO_PNP_PM_LDN
-	#undef SUPERIO_PNP_IO0
-	#undef SUPERIO_PNP_IO1
-	#undef SUPERIO_PNP_IRQ0
-	#undef PNP_DEVICE_ACTIVE
-	#define PNP_DEVICE_ACTIVE ACT3
-	#define SUPERIO_PNP_LDN 8
-	#define SUPERIO_PNP_IO0 0x08, 0x08
-	#include <superio/acpi/pnp_generic.asl>
-#endif
-}
+/*
+ * See ASL file below for details of defines to control
+ * device visibilities.
+ */
+#include <superio/nuvoton/common/acpi/superio.asl>

From 2de0c9575d4806a7bd06678286af40a7506a8d2a Mon Sep 17 00:00:00 2001
From: Keith Hui <buurin@gmail.com>
Date: Thu, 23 Oct 2025 19:48:41 -0400
Subject: [PATCH 3390/3886] sio/nuvoton/nct6776: Switch to common Nuvoton ASL
 code

TEST=Processed dsdt.asl for mainboards using this super I/O chip
only contain changes specifically made by CB:89740.

Change-Id: Id8067e6058b650121e7c830a0cb298752a45d62c
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89743
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
---
 src/superio/nuvoton/nct6776/acpi/superio.asl | 188 ++-----------------
 1 file changed, 16 insertions(+), 172 deletions(-)

diff --git a/src/superio/nuvoton/nct6776/acpi/superio.asl b/src/superio/nuvoton/nct6776/acpi/superio.asl
index 1297aa15a0..d9d823b36d 100644
--- a/src/superio/nuvoton/nct6776/acpi/superio.asl
+++ b/src/superio/nuvoton/nct6776/acpi/superio.asl
@@ -1,186 +1,30 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
-/*
- * Include this file into a mainboard's DSDT _SB device tree and it will
- * expose the NCT6776 SuperIO and some of its functionality.
- *
- * It allows the change of IO ports, IRQs and DMA settings on logical
- * devices, disabling and reenabling logical devices.
- *
- *   LDN		State
- * 0x1 PP		Implemented, untested
- * 0x2 SP1		Implemented, untested
- * 0x5 KBC		Implemented, untested
- * 0x8 GPIO		Implemented, untested
- * 0xb HWM		Implemented, untested
- *
- * Controllable through preprocessor defines:
- * SUPERIO_DEV		Device identifier for this SIO (e.g. SIO0)
- * SUPERIO_PNP_BASE	I/O address of the first PnP configuration register
- * NCT6776_SHOW_PP	If defined, the parallel port will be exposed.
- * NCT6776_SHOW_SP1	If defined, Serial Port 1 will be exposed.
- * NCT6776_SHOW_KBC	If defined, the Keyboard Controller will be exposed.
- * NCT6776_SHOW_GPIO	If defined, GPIO support will be exposed.
- * NCT6776_SHOW_HWM	If defined, the Environment Controller will be exposed.
- */
-
-#undef SUPERIO_CHIP_NAME
+#ifndef SUPERIO_CHIP_NAME
 #define SUPERIO_CHIP_NAME NCT6776
-#include <superio/acpi/pnp.asl>
+#endif
 
-#undef PNP_DEFAULT_PSC
-#define PNP_DEFAULT_PSC Return (0) /* no power management */
-
-Device(SUPERIO_DEV) {
-	Name (_HID, EisaId("PNP0A05"))
-	Name (_STR, Unicode("Nuvoton NCT6776 Super I/O"))
-	Name (_UID, SUPERIO_UID(SUPERIO_DEV,))
-
-	/* SuperIO configuration ports */
-	OperationRegion (CREG, SystemIO, SUPERIO_PNP_BASE, 0x02)
-	Field (CREG, ByteAcc, NoLock, Preserve)
-	{
-		PNP_ADDR_REG,	8,
-		PNP_DATA_REG,	8,
-	}
-	IndexField (PNP_ADDR_REG, PNP_DATA_REG, ByteAcc, NoLock, Preserve)
-	{
-		Offset (0x07),
-		PNP_LOGICAL_DEVICE,	8, /* Logical device selector */
-
-		Offset (0x30),
-		PNP_DEVICE_ACTIVE,	1, /* Logical device activation */
-		ACT1,			1, /* Logical device activation */
-		ACT2,			1, /* Logical device activation */
-		ACT3,			1, /* Logical device activation */
-		ACT4,			1, /* Logical device activation */
-		ACT5,			1, /* Logical device activation */
-		ACT6,			1, /* Logical device activation */
-		ACT7,			1, /* Logical device activation */
-
-		Offset (0x60),
-		PNP_IO0_HIGH_BYTE,	8, /* First I/O port base - high byte */
-		PNP_IO0_LOW_BYTE,	8, /* First I/O port base - low byte */
-		Offset (0x62),
-		PNP_IO1_HIGH_BYTE,	8, /* Second I/O port base - high byte */
-		PNP_IO1_LOW_BYTE,	8, /* Second I/O port base - low byte */
-		Offset (0x64),
-		PNP_IO2_HIGH_BYTE,	8, /* Third I/O port base - high byte */
-		PNP_IO2_LOW_BYTE,	8, /* Third I/O port base - low byte */
-
-		Offset (0x70),
-		PNP_IRQ0,		8, /* First IRQ */
-		Offset (0x72),
-		PNP_IRQ1,		8, /* Second IRQ */
-		Offset (0x74),
-		PNP_DMA0,		8, /* DRQ */
-	}
-
-	Method (_CRS)
-	{
-		/* Announce the used I/O ports to the OS */
-		Return (ResourceTemplate () {
-			IO (Decode16, SUPERIO_PNP_BASE, SUPERIO_PNP_BASE, 0x01, 0x02)
-		})
-	}
-
-	#undef PNP_ENTER_MAGIC_1ST
-	#undef PNP_ENTER_MAGIC_2ND
-	#undef PNP_ENTER_MAGIC_3RD
-	#undef PNP_ENTER_MAGIC_4TH
-	#undef PNP_EXIT_MAGIC_1ST
-	#undef PNP_EXIT_SPECIAL_REG
-	#undef PNP_EXIT_SPECIAL_VAL
-	#define PNP_ENTER_MAGIC_1ST	0x87
-	#define PNP_ENTER_MAGIC_2ND	0x87
-	#define PNP_EXIT_MAGIC_1ST	0xaa
-	#include <superio/acpi/pnp_config.asl>
+#ifndef SUPERIO_FULL_CHIP_NAME
+#define SUPERIO_FULL_CHIP_NAME "Nuvoton NCT6776 Super I/O"
+#endif
 
 #ifdef NCT6776_SHOW_PP
-	#undef SUPERIO_PNP_HID
-	#undef SUPERIO_PNP_LDN
-	#undef SUPERIO_PNP_DDN
-	#undef SUPERIO_PNP_NO_DIS
-	#undef SUPERIO_PNP_PM_REG
-	#undef SUPERIO_PNP_PM_VAL
-	#undef SUPERIO_PNP_PM_LDN
-	#undef SUPERIO_PNP_IO0
-	#undef SUPERIO_PNP_IO1
-	#undef SUPERIO_PNP_IO2
-	#undef SUPERIO_PNP_IRQ0
-	#undef SUPERIO_PNP_IRQ1
-	#undef SUPERIO_PNP_DMA
-	/*
-	 * The extra code required to dynamically reflect ECP in the HID
-	 * isn't currently justified, so the HID is hardcoded as not
-	 * using ECP. "PNP0401" would indicate ECP.
-	 */
-	#define SUPERIO_PNP_HID "PNP0400"
-	#define SUPERIO_PNP_LDN 1
-	#define SUPERIO_PNP_IO0 0x08, 0x08
-	#define SUPERIO_PNP_IRQ0
-	#define SUPERIO_PNP_DMA
-	#include <superio/acpi/pnp_generic.asl>
+#define NCT677X_SHOW_PP
 #endif
-
 #ifdef NCT6776_SHOW_SP1
-	#undef SUPERIO_UART_LDN
-	#undef SUPERIO_UART_DDN
-	#undef SUPERIO_UART_PM_REG
-	#undef SUPERIO_UART_PM_VAL
-	#undef SUPERIO_UART_PM_LDN
-	#define SUPERIO_UART_LDN 2
-	#include <superio/acpi/pnp_uart.asl>
+#define NCT677X_SHOW_SP1
+#endif
+#ifdef NCT6776_SHOW_SP2
+#define NCT677X_SHOW_SP2
 #endif
-
 #ifdef NCT6776_SHOW_KBC
-	#undef SUPERIO_KBC_LDN
-	#undef SUPERIO_KBC_PS2M
-	#undef SUPERIO_KBC_PS2LDN
-	#define SUPERIO_KBC_LDN 5
-	#define SUPERIO_KBC_PS2M
-	#include <superio/acpi/pnp_kbc.asl>
+#define NCT677X_SHOW_KBC
 #endif
-
 #ifdef NCT6776_SHOW_HWM
-	#undef SUPERIO_PNP_HID
-	#undef SUPERIO_PNP_LDN
-	#undef SUPERIO_PNP_DDN
-	#undef SUPERIO_PNP_NO_DIS
-	#undef SUPERIO_PNP_PM_REG
-	#undef SUPERIO_PNP_PM_VAL
-	#undef SUPERIO_PNP_PM_LDN
-	#undef SUPERIO_PNP_IO0
-	#undef SUPERIO_PNP_IO1
-	#undef SUPERIO_PNP_IO2
-	#undef SUPERIO_PNP_IRQ0
-	#undef SUPERIO_PNP_IRQ1
-	#undef SUPERIO_PNP_DMA
-	#define SUPERIO_PNP_LDN 11
-	#define SUPERIO_PNP_IO0 0x08, 0x08
-	#define SUPERIO_PNP_IO1 0x08, 0x08
-	#define SUPERIO_PNP_IRQ0
-	#include <superio/acpi/pnp_generic.asl>
+#define NCT677X_SHOW_HWM
+#endif
+#ifdef NCT6776_SHOW_GPIO
+#define NCT677X_SHOW_GPIO
 #endif
 
-#ifdef NCT6776_SHOW_GPIO
-	#undef SUPERIO_PNP_HID
-	#undef SUPERIO_PNP_LDN
-	#undef SUPERIO_PNP_DDN
-	#undef SUPERIO_PNP_NO_DIS
-	#undef SUPERIO_PNP_PM_REG
-	#undef SUPERIO_PNP_PM_VAL
-	#undef SUPERIO_PNP_PM_LDN
-	#undef SUPERIO_PNP_IO0
-	#undef SUPERIO_PNP_IO1
-	#undef SUPERIO_PNP_IO2
-	#undef SUPERIO_PNP_IRQ0
-	#undef SUPERIO_PNP_IRQ1
-	#undef SUPERIO_PNP_DMA
-	#undef PNP_DEVICE_ACTIVE
-	#define PNP_DEVICE_ACTIVE ACT3
-	#define SUPERIO_PNP_LDN 8
-	#define SUPERIO_PNP_IO0 0x08, 0x08
-	#include <superio/acpi/pnp_generic.asl>
-#endif
-}
+#include <superio/nuvoton/common/acpi/superio.asl>

From 65c4ea0bfbff1f493f78f52a37a6f5a88fb17962 Mon Sep 17 00:00:00 2001
From: Keith Hui <buurin@gmail.com>
Date: Fri, 19 Dec 2025 22:44:41 -0500
Subject: [PATCH 3391/3886] superio/acpi/pnp_kbc.asl: Allow changing device and
 PNP IDs

Currently DSDT keyboard and mouse device declarations generated by
this file use IDs derived from the logical device number, in the
form of KBD# and PS2# where # is the LDN. This is far from the norm
for mainboards with only one super I/O chip, where they are named
PS2K and PS2M, which is also the names used by the much more
simplistic ASL code in drivers/pc/pc80. They also use hard coded
PNP IDs.

This patch adds two preprocessor symbols, SUPERIO_KBC_PS2KID and
SUPERIO_KBC_PS2MID, to allow these device IDs to be changed, most
likely to PS2K and PS2M. If not defined, existing naming logic is
kept.

Their _HIDs are also changed to refer to EISA ID from Kconfig,
like pc80 does. This in theory allows mainboard to change
their PNP IDs if needed. Only Lenovo laptops actually change this
from the Kconfig default, which is also the formerly hardcoded value.

Goal is to allow eliminating pc80 in favour of this when appropriate,
to avoid potential conflicts that may arise from having duplicate PS/2
devices defined.

TEST=With new symbols undefined, generated dsdt.asl did not change.
Generated dsdt.asl checked for correctness manually via temporary
manual edits, with all combinations of preprocessor controls.

Change-Id: I0dcc94c2cb09fee2e22776fd800c3435a9409c84
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90576
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
---
 src/superio/acpi/pnp_kbc.asl | 48 +++++++++++++++++++++++-------------
 1 file changed, 31 insertions(+), 17 deletions(-)

diff --git a/src/superio/acpi/pnp_kbc.asl b/src/superio/acpi/pnp_kbc.asl
index b0055be225..fca0c77382 100644
--- a/src/superio/acpi/pnp_kbc.asl
+++ b/src/superio/acpi/pnp_kbc.asl
@@ -11,12 +11,18 @@
  * SUPERIO_CHIP_NAME	The name of the Super I/O chip (unique, required)
  * SUPERIO_KBC_LDN	The logical device number on the Super I/O
  *			chip for this keyboard controller (required)
+ * SUPERIO_KBC_PS2KID	The name of PS/2 keyboard controller device.
+ *			If not defined, defaults to KBD# where # is
+ *			SUPERIO_KBC_LDN.
  * SUPERIO_KBC_PS2M	If defined, PS/2 mouse support is included in
  *			the KBC_LDN. Mouse irq is set at IRQ1 of the
  *			KBC_LDN.
  * SUPERIO_KBC_PS2LDN	If defined, specifies a second LDN to configure
  *			PS/2 mouse support. Mouse irq is set at IRQ0 of
  *			this LDN.
+ * SUPERIO_KBC_PS2MID	The name of PS/2 mouse support device.
+ *			If not defined, defaults to PS2# where # is
+ *			KBC_LDN or KBC_PS2LDN as appropriate.
  * SUPERIO_KBC_PS2M and SUPERIO_KBC_PS2LDN are mutually exclusive.
  */
 
@@ -34,8 +40,20 @@
 # error "SUPERIO_KBC_PS2M and SUPERIO_KBC_PS2LDN are mutually exclusive."
 #endif
 
-Device (SUPERIO_ID(KBD, SUPERIO_KBC_LDN)) {
-	Name (_HID, EisaId ("PNP0303"))
+#ifndef SUPERIO_KBC_PS2KID
+#define SUPERIO_KBC_PS2KID SUPERIO_ID(KBD, SUPERIO_KBC_LDN)
+#endif
+
+#ifndef SUPERIO_KBC_PS2MID
+#ifdef SUPERIO_KBC_PS2LDN
+#define SUPERIO_KBC_PS2MID SUPERIO_ID(PS2, SUPERIO_KBC_PS2LDN)
+#else
+#define SUPERIO_KBC_PS2MID SUPERIO_ID(PS2, SUPERIO_KBC_LDN)
+#endif /* SUPERIO_KBC_PS2LDN */
+#endif
+
+Device (SUPERIO_KBC_PS2KID) {
+	Name (_HID, EisaId (CONFIG_PS2K_EISAID))
 	Name (_UID, SUPERIO_UID(KBD, SUPERIO_KBC_LDN))
 
 	Method (_STA)
@@ -48,10 +66,8 @@ Device (SUPERIO_ID(KBD, SUPERIO_KBC_LDN)) {
 		ENTER_CONFIG_MODE (SUPERIO_KBC_LDN)
 		  PNP_DEVICE_ACTIVE = 0
 		EXIT_CONFIG_MODE ()
-		#if defined(SUPERIO_KBC_PS2LDN)
-		Notify (SUPERIO_ID(PS2, SUPERIO_KBC_PS2LDN), 1)
-		#elif defined(SUPERIO_KBC_PS2M)
-		Notify (SUPERIO_ID(PS2, SUPERIO_KBC_LDN), 1)
+		#if defined(SUPERIO_KBC_PS2LDN) || defined(SUPERIO_KBC_PS2M)
+		Notify (SUPERIO_KBC_PS2MID, 1)
 		#endif
 	}
 
@@ -97,26 +113,24 @@ Device (SUPERIO_ID(KBD, SUPERIO_KBC_LDN)) {
 		  PNP_WRITE_IRQ(PNP_IRQ0, Arg0, IR0)
 		  PNP_DEVICE_ACTIVE = 1
 		EXIT_CONFIG_MODE ()
-		#if defined(SUPERIO_KBC_PS2LDN)
-		Notify (SUPERIO_ID(PS2, SUPERIO_KBC_PS2LDN), 1)
-		#elif defined(SUPERIO_KBC_PS2M)
-		Notify (SUPERIO_ID(PS2, SUPERIO_KBC_LDN), 1)
+		#if defined(SUPERIO_KBC_PS2LDN) || defined(SUPERIO_KBC_PS2M)
+		Notify (SUPERIO_KBC_PS2MID, 1)
 		#endif
 	}
 }
 
 #if defined(SUPERIO_KBC_PS2M)
-Device (SUPERIO_ID(PS2, SUPERIO_KBC_LDN)) {
-	Name (_HID, EisaId ("PNP0F13"))
+Device (SUPERIO_KBC_PS2MID) {
+	Name (_HID, EisaId (CONFIG_PS2M_EISAID))
 	Name (_UID, SUPERIO_UID(PS2, SUPERIO_KBC_LDN))
 
 	Method (_STA)
 	{
-		Return (^^SUPERIO_ID(KBD, SUPERIO_KBC_LDN)._STA ())
+		Return (^^SUPERIO_KBC_PS2KID._STA ())
 	}
 
 	Method (_PSC) {
-		Return (^^SUPERIO_ID(KBD, SUPERIO_KBC_LDN)._PSC ())
+		Return (^^SUPERIO_KBC_PS2KID._PSC ())
 	}
 
 	Method (_CRS, 0, Serialized)
@@ -149,13 +163,13 @@ Device (SUPERIO_ID(PS2, SUPERIO_KBC_LDN)) {
 	}
 }
 #elif defined(SUPERIO_KBC_PS2LDN)
-Device (SUPERIO_ID(PS2, SUPERIO_KBC_PS2LDN)) {
-	Name (_HID, EisaId ("PNP0F13"))
+Device (SUPERIO_KBC_PS2MID) {
+	Name (_HID, EisaId (CONFIG_PS2M_EISAID))
 	Name (_UID, SUPERIO_UID(PS2, SUPERIO_KBC_PS2LDN))
 
 	Method (_STA)
 	{
-		Local0 = ^^SUPERIO_ID(KBD, SUPERIO_KBC_LDN)._STA ()
+		Local0 = ^^SUPERIO_KBC_PS2KID._STA ()
 		If (Local0 == DEVICE_PRESENT_ACTIVE) {
 			PNP_GENERIC_STA(SUPERIO_KBC_PS2LDN)
 		} Else {

From e72a325c40f5b8177741d55856bf2e888a93449a Mon Sep 17 00:00:00 2001
From: Keith Hui <buurin@gmail.com>
Date: Fri, 24 Oct 2025 00:20:56 -0400
Subject: [PATCH 3392/3886] sio/nuvoton/nct{5535,6779}d: Use new common init
 code

Retire the short-lived special setup to share C code between them, in
favour of the common init code provided by CB:82632.

Tested on asus/p8z77-m with SeaBIOS 1.17.0.

Change-Id: I699fc08d9bfc56dad28eb20042884e979785c070
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89744
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
---
 src/superio/nuvoton/nct5535d/Makefile.mk      |  2 +-
 .../nct5535d/{nct5535d.c => superio.c}        |  5 +-
 src/superio/nuvoton/nct6779d/Makefile.mk      |  3 +-
 src/superio/nuvoton/nct6779d/nct6779d.c       | 42 -----------
 src/superio/nuvoton/nct6779d/nct6779d.h       |  4 -
 src/superio/nuvoton/nct6779d/superio.c        | 74 ++++++++-----------
 6 files changed, 37 insertions(+), 93 deletions(-)
 rename src/superio/nuvoton/nct5535d/{nct5535d.c => superio.c} (76%)
 delete mode 100644 src/superio/nuvoton/nct6779d/nct6779d.c

diff --git a/src/superio/nuvoton/nct5535d/Makefile.mk b/src/superio/nuvoton/nct5535d/Makefile.mk
index bfac11a5f6..1b48a19ec3 100644
--- a/src/superio/nuvoton/nct5535d/Makefile.mk
+++ b/src/superio/nuvoton/nct5535d/Makefile.mk
@@ -1,3 +1,3 @@
 # SPDX-License-Identifier: GPL-2.0-or-later
 
-ramstage-$(CONFIG_SUPERIO_NUVOTON_NCT5535D) += nct5535d.c
+ramstage-$(CONFIG_SUPERIO_NUVOTON_NCT5535D) += superio.c
diff --git a/src/superio/nuvoton/nct5535d/nct5535d.c b/src/superio/nuvoton/nct5535d/superio.c
similarity index 76%
rename from src/superio/nuvoton/nct5535d/nct5535d.c
rename to src/superio/nuvoton/nct5535d/superio.c
index 0b183a8bc1..ef2209ce64 100644
--- a/src/superio/nuvoton/nct5535d/nct5535d.c
+++ b/src/superio/nuvoton/nct5535d/superio.c
@@ -2,10 +2,11 @@
 
 #include <device/device.h>
 #include <device/pnp.h>
+#include <superio/nuvoton/common/nuvoton.h>
 
 #include "nct5535d.h"
 
-/* Initialization C code is provided by nct6779d */
+/* Initialization C code is provided by common code */
 
 static struct pnp_info pnp_dev_info[] = {
 	{ NULL, NCT5535D_SP1, PNP_IO0 | PNP_IRQ0, 0x0ff8, },
@@ -18,7 +19,7 @@ static struct pnp_info pnp_dev_info[] = {
 
 static void enable_dev(struct device *dev)
 {
-	pnp_enable_devices(dev, &_nuvoton_nct6779d_ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info);
+	pnp_enable_devices(dev, &nuvoton_common_ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info);
 }
 
 struct chip_operations superio_nuvoton_nct5535d_ops = {
diff --git a/src/superio/nuvoton/nct6779d/Makefile.mk b/src/superio/nuvoton/nct6779d/Makefile.mk
index 327081f7f9..d5476e4625 100644
--- a/src/superio/nuvoton/nct6779d/Makefile.mk
+++ b/src/superio/nuvoton/nct6779d/Makefile.mk
@@ -1,4 +1,3 @@
 # SPDX-License-Identifier: GPL-2.0-or-later
 
-ramstage-$(CONFIG_SUPERIO_NUVOTON_NCT6779D) += superio.c nct6779d.c
-ramstage-$(CONFIG_SUPERIO_NUVOTON_NCT5535D) += superio.c
+ramstage-$(CONFIG_SUPERIO_NUVOTON_NCT6779D) += superio.c
diff --git a/src/superio/nuvoton/nct6779d/nct6779d.c b/src/superio/nuvoton/nct6779d/nct6779d.c
deleted file mode 100644
index 940f600775..0000000000
--- a/src/superio/nuvoton/nct6779d/nct6779d.c
+++ /dev/null
@@ -1,42 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-or-later */
-
-#include <device/device.h>
-#include <device/pnp.h>
-#include "nct6779d.h"
-
-static struct pnp_info pnp_dev_info[] = {
-	{ NULL, NCT6779D_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x0ff8, },
-	{ NULL, NCT6779D_SP1, PNP_IO0 | PNP_IRQ0, 0x0ff8, },
-	{ NULL, NCT6779D_SP2, PNP_IO0 | PNP_IRQ0, 0x0ff8, },
-	{ NULL, NCT6779D_KBC, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_IRQ1,
-		0x0fff, 0x0fff, },
-	{ NULL, NCT6779D_CIR, PNP_IO0 | PNP_IRQ0, 0x0ff8, },
-	{ NULL, NCT6779D_ACPI, PNP_MSC2,},
-	{ NULL, NCT6779D_HWM_FPLED, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_MSC0,
-		0x0ffe, 0x0ffe, },
-	{ NULL, NCT6779D_WDT1},
-	{ NULL, NCT6779D_CIRWKUP, PNP_IO0 | PNP_IRQ0, 0x0ff8, },
-	{ NULL, NCT6779D_GPIO_PP_OD},
-	{ NULL, NCT6779D_PRT80},
-	{ NULL, NCT6779D_DSLP},
-	{ NULL, NCT6779D_GPIOBASE, PNP_IO0, 0x0ff8, },
-	{ NULL, NCT6779D_GPIO0},
-	{ NULL, NCT6779D_GPIO1},
-	{ NULL, NCT6779D_GPIO2},
-	{ NULL, NCT6779D_GPIO3},
-	{ NULL, NCT6779D_GPIO4},
-	{ NULL, NCT6779D_GPIO5, PNP_MSC4 | PNP_MSC5},
-	{ NULL, NCT6779D_GPIO6, PNP_MSC4 | PNP_MSC5},
-	{ NULL, NCT6779D_GPIO7},
-	{ NULL, NCT6779D_GPIO8},
-};
-
-static void enable_dev(struct device *dev)
-{
-	pnp_enable_devices(dev, &_nuvoton_nct6779d_ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info);
-}
-
-struct chip_operations superio_nuvoton_nct6779d_ops = {
-	.name = "NUVOTON NCT6779D Super I/O",
-	.enable_dev = enable_dev,
-};
diff --git a/src/superio/nuvoton/nct6779d/nct6779d.h b/src/superio/nuvoton/nct6779d/nct6779d.h
index 133450a083..63b7b0e914 100644
--- a/src/superio/nuvoton/nct6779d/nct6779d.h
+++ b/src/superio/nuvoton/nct6779d/nct6779d.h
@@ -3,8 +3,6 @@
 #ifndef SUPERIO_NUVOTON_NCT6779D_H
 #define SUPERIO_NUVOTON_NCT6779D_H
 
-#include <device/device.h>
-
 /* Logical Device Numbers (LDN). */
 #define NCT6779D_PP		0x01 /* Parallel port */
 #define NCT6779D_SP1		0x02 /* Com1 */
@@ -36,6 +34,4 @@
 #define NCT6779D_GPIO7		((7 << 8) | NCT6779D_GPIO12345678_V)
 #define NCT6779D_GPIO8		((0 << 8) | NCT6779D_GPIO12345678_V)
 
-extern struct device_operations _nuvoton_nct6779d_ops;
-
 #endif /* SUPERIO_NUVOTON_NCT6779D_H */
diff --git a/src/superio/nuvoton/nct6779d/superio.c b/src/superio/nuvoton/nct6779d/superio.c
index 262170770c..785c30059c 100644
--- a/src/superio/nuvoton/nct6779d/superio.c
+++ b/src/superio/nuvoton/nct6779d/superio.c
@@ -2,53 +2,43 @@
 
 #include <device/device.h>
 #include <device/pnp.h>
-#include <option.h>
-#include <pc80/keyboard.h>
-#include <superio/conf_mode.h>
+#include <superio/nuvoton/common/nuvoton.h>
 
 #include "nct6779d.h"
 
-/* C code shared by NCT6779D and NCT5535D */
+static struct pnp_info pnp_dev_info[] = {
+	{ NULL, NCT6779D_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x0ff8, },
+	{ NULL, NCT6779D_SP1, PNP_IO0 | PNP_IRQ0, 0x0ff8, },
+	{ NULL, NCT6779D_SP2, PNP_IO0 | PNP_IRQ0, 0x0ff8, },
+	{ NULL, NCT6779D_KBC, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_IRQ1,
+		0x0fff, 0x0fff, },
+	{ NULL, NCT6779D_CIR, PNP_IO0 | PNP_IRQ0, 0x0ff8, },
+	{ NULL, NCT6779D_ACPI, PNP_MSC2,},
+	{ NULL, NCT6779D_HWM_FPLED, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_MSC0,
+		0x0ffe, 0x0ffe, },
+	{ NULL, NCT6779D_WDT1},
+	{ NULL, NCT6779D_CIRWKUP, PNP_IO0 | PNP_IRQ0, 0x0ff8, },
+	{ NULL, NCT6779D_GPIO_PP_OD},
+	{ NULL, NCT6779D_PRT80},
+	{ NULL, NCT6779D_DSLP},
+	{ NULL, NCT6779D_GPIOBASE, PNP_IO0, 0x0ff8, },
+	{ NULL, NCT6779D_GPIO0},
+	{ NULL, NCT6779D_GPIO1},
+	{ NULL, NCT6779D_GPIO2},
+	{ NULL, NCT6779D_GPIO3},
+	{ NULL, NCT6779D_GPIO4},
+	{ NULL, NCT6779D_GPIO5, PNP_MSC4 | PNP_MSC5},
+	{ NULL, NCT6779D_GPIO6, PNP_MSC4 | PNP_MSC5},
+	{ NULL, NCT6779D_GPIO7},
+	{ NULL, NCT6779D_GPIO8},
+};
 
-#define MAINBOARD_POWER_OFF	0
-#define MAINBOARD_POWER_ON	1
-#define MAINBOARD_POWER_KEEP	2
-
-static void nct6779d_init(struct device *dev)
+static void enable_dev(struct device *dev)
 {
-	uint8_t byte, power_status;
-
-	if (!dev->enabled)
-		return;
-
-	switch (dev->path.pnp.device) {
-	/* TODO: Might potentially need code for HWM or FDC etc. */
-	case NCT6779D_KBC:
-		pc_keyboard_init(NO_AUX_DEVICE);
-		break;
-	case NCT6779D_ACPI:
-		/* Set power state after power fail */
-		power_status = get_uint_option("power_on_after_fail",
-				CONFIG_MAINBOARD_POWER_FAILURE_STATE);
-		pnp_enter_conf_mode(dev);
-		pnp_set_logical_device(dev);
-		byte = pnp_read_config(dev, 0xe4) & ~0x60;
-		if (power_status == MAINBOARD_POWER_ON)
-			byte |= (MAINBOARD_POWER_ON << 5);
-		else if (power_status == MAINBOARD_POWER_KEEP)
-			byte |= (MAINBOARD_POWER_KEEP << 5);
-		pnp_write_config(dev, 0xe4, byte);
-		pnp_exit_conf_mode(dev);
-		printk(BIOS_INFO, "set power %s after power fail\n", power_status ? "on" : "off");
-		break;
-	}
+	pnp_enable_devices(dev, &nuvoton_common_ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info);
 }
 
-struct device_operations _nuvoton_nct6779d_ops = {
-	.read_resources   = pnp_read_resources,
-	.set_resources    = pnp_set_resources,
-	.enable_resources = pnp_enable_resources,
-	.enable           = pnp_alt_enable,
-	.init             = nct6779d_init,
-	.ops_pnp_mode     = &pnp_conf_mode_8787_aa,
+struct chip_operations superio_nuvoton_nct6779d_ops = {
+	.name = "NUVOTON NCT6779D Super I/O",
+	.enable_dev = enable_dev,
 };

From e82ecc739d5f3bb614dafe8195a8502e13f8bb8a Mon Sep 17 00:00:00 2001
From: Keith Hui <buurin@gmail.com>
Date: Fri, 24 Oct 2025 16:38:29 -0400
Subject: [PATCH 3393/3886] sio/nuvoton/nct6776: Switch to common init code

TEST=abuild

Change-Id: I10ced926e8844a54fe2c6e892f10459689bbd07b
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89745
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/superio/nuvoton/nct6776/superio.c | 27 ++-------------------------
 1 file changed, 2 insertions(+), 25 deletions(-)

diff --git a/src/superio/nuvoton/nct6776/superio.c b/src/superio/nuvoton/nct6776/superio.c
index d98e303b96..2cce597508 100644
--- a/src/superio/nuvoton/nct6776/superio.c
+++ b/src/superio/nuvoton/nct6776/superio.c
@@ -2,35 +2,12 @@
 
 #include <device/device.h>
 #include <device/pnp.h>
-#include <pc80/keyboard.h>
-#include <superio/conf_mode.h>
+#include <superio/nuvoton/common/nuvoton.h>
 
 #include "nct6776.h"
 
 /* Both NCT6776D and NCT6776F package variants are supported. */
 
-static void nct6776_init(struct device *dev)
-{
-	if (!dev->enabled)
-		return;
-
-	switch (dev->path.pnp.device) {
-	/* TODO: Might potentially need code for HWM or FDC etc. */
-	case NCT6776_KBC:
-		pc_keyboard_init(NO_AUX_DEVICE);
-		break;
-	}
-}
-
-static struct device_operations ops = {
-	.read_resources   = pnp_read_resources,
-	.set_resources    = pnp_set_resources,
-	.enable_resources = pnp_enable_resources,
-	.enable           = pnp_alt_enable,
-	.init             = nct6776_init,
-	.ops_pnp_mode     = &pnp_conf_mode_8787_aa,
-};
-
 static struct pnp_info pnp_dev_info[] = {
 	{ NULL, NCT6776_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x0ff8 },
 	{ NULL, NCT6776_PP,  PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x0ff8 },
@@ -63,7 +40,7 @@ static struct pnp_info pnp_dev_info[] = {
 
 static void enable_dev(struct device *dev)
 {
-	pnp_enable_devices(dev, &ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info);
+	pnp_enable_devices(dev, &nuvoton_common_ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info);
 }
 
 struct chip_operations superio_nuvoton_nct6776_ops = {

From e47952c3a757ef3867a2bbd877d65d0a15b90c57 Mon Sep 17 00:00:00 2001
From: Keith Hui <buurin@gmail.com>
Date: Fri, 24 Oct 2025 17:13:18 -0400
Subject: [PATCH 3394/3886] mb/asus/p8x7x-series: Enable common SIO ASL code

Bring in ACPI ASL code from sio/nuvoton/common and hook up the
SIO ACPI suspend hook.

TEST=PS/2 keyboard can wake asus/p8z77-m from S3 but not S5, as
expected.

Change-Id: I8d38928adb840d6fcb4703dd9ad69480813156ca
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89746
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 .../asus/p8x7x-series/acpi/platform.asl       |  2 ++
 .../asus/p8x7x-series/acpi/superio.asl        | 30 ++++++++++++++++++-
 2 files changed, 31 insertions(+), 1 deletion(-)

diff --git a/src/mainboard/asus/p8x7x-series/acpi/platform.asl b/src/mainboard/asus/p8x7x-series/acpi/platform.asl
index b5c3fc333a..d7dcaeeec5 100644
--- a/src/mainboard/asus/p8x7x-series/acpi/platform.asl
+++ b/src/mainboard/asus/p8x7x-series/acpi/platform.asl
@@ -12,10 +12,12 @@ Method(_PTS, 1)
 	{
 	    BLINK_POWER_LED = 1
 	}
+	\_SB.PCI0.LPCB.SIO0.SIOS(Arg0)
 }
 
 Method(_WAK, 1)
 {
 	BLINK_POWER_LED = 0
+	\_SB.PCI0.LPCB.SIO0.SIOW(Arg0)
 	Return(Package(){0, 0})
 }
diff --git a/src/mainboard/asus/p8x7x-series/acpi/superio.asl b/src/mainboard/asus/p8x7x-series/acpi/superio.asl
index 55b1db5b11..3fb0be5bef 100644
--- a/src/mainboard/asus/p8x7x-series/acpi/superio.asl
+++ b/src/mainboard/asus/p8x7x-series/acpi/superio.asl
@@ -1,3 +1,31 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
+#define SUPERIO_DEV		SIO0
+#define SUPERIO_PNP_BASE	CONFIG_SUPERIO_NUVOTON_PNP_BASE
 
-#include <drivers/pc80/pc/ps2_controller.asl>
+/* Defines to have ASLs below make visible some devices */
+#if !CONFIG(NO_UART_ON_SUPERIO)
+#define NCT677X_SHOW_SP1
+#endif
+
+/* TODO: Exclude next lines for variants without PS/2 port */
+#define NCT677X_SHOW_KBC
+#define SUPERIO_KBC_PS2KID	PS2K
+#define SUPERIO_KBC_PS2MID	PS2M
+
+/*
+ * This series uses one of four SIO chips:
+ * NCT6776 (p8c_ws)
+ * NCT6779D
+ * NCT5535D
+ * IT8771E (P8H77-I and P8H77-V LE, both not yet supported)
+ *
+ * Include the correct ASL file.
+ */
+
+#if CONFIG(SUPERIO_NUVOTON_NCT6779D)
+#include <superio/nuvoton/nct6779d/acpi/superio.asl>
+#elif CONFIG(SUPERIO_NUVOTON_NCT5535D)
+#include <superio/nuvoton/nct5535d/acpi/superio.asl>
+#elif CONFIG(SUPERIO_NUVOTON_NCT6776)
+#include <superio/nuvoton/nct6776/acpi/superio.asl>
+#endif

From a3923d678ffe45f0f3bade4a32a62336efdd19ba Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Mon, 16 Feb 2026 21:06:29 +0000
Subject: [PATCH 3395/3886] ec/starlabs/merlin: fix ITE CMOS index mapping

ACPI stores trackpad_state and kbl_brightness as small indices in
CMOS (per cmos.layout and RPTS/RWAK). The ITE init path treated the
CMOS byte as the EC's raw encoded value, so non-default settings
would fall back (e.g. trackpad disabled, kbd backlight brightness).

Treat CMOS-backed values as LUT indices and fix the kbl_brightness
fallback to use an index.

Change-Id: Id8d320c9544c9fa73b234817717c47f1fa169c64
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91301
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/ec/starlabs/merlin/ite.c | 25 ++++++++++++++++++-------
 1 file changed, 18 insertions(+), 7 deletions(-)

diff --git a/src/ec/starlabs/merlin/ite.c b/src/ec/starlabs/merlin/ite.c
index 953c9e3de6..8ce556a308 100644
--- a/src/ec/starlabs/merlin/ite.c
+++ b/src/ec/starlabs/merlin/ite.c
@@ -41,15 +41,26 @@ static uint8_t get_ec_value_from_option(const char *name,
 					uint32_t cmos_start_bit,
 					uint32_t cmos_length)
 {
-	uint8_t value;
+	/*
+	 * CMOS-backed EC options store an index (see cmos.layout and ACPI
+	 * RPTS/RWAK mappings), while the option backend stores the EC's raw
+	 * values (e.g. 0xaa/0xbb/0xdd).
+	 */
+	if (cmos_start_bit != UINT_MAX) {
+		unsigned int index = get_cmos_value(cmos_start_bit, cmos_length);
 
-	if (cmos_start_bit != UINT_MAX)
-		value = get_cmos_value(cmos_start_bit, cmos_length);
-	else
-		value = get_uint_option(name, fallback);
+		if (index >= lut_size)
+			index = fallback;
+		if (index >= lut_size)
+			index = 0;
+
+		return lut[index];
+	}
+
+	const uint8_t value = get_uint_option(name, fallback);
 
 	/* Check if the value exists in the LUT array */
-	for (int i = 0; i < lut_size; i++)
+	for (size_t i = 0; i < lut_size; i++)
 		if (lut[i] == value)
 			return value;
 
@@ -265,7 +276,7 @@ static void merlin_init(struct device *dev)
 
 	ec_write(ECRAM_KBL_BRIGHTNESS,
 		get_ec_value_from_option("kbl_brightness",
-			CONFIG(EC_STARLABS_KBL_LEVELS) ? KBL_LOW : KBL_ON,
+			CONFIG(EC_STARLABS_KBL_LEVELS) ? 2 : 0,
 			kbl_brightness,
 			ARRAY_SIZE(kbl_brightness),
 			CMOS_VSTART_kbl_brightness,

From bf148cae0a1626c4dfb11bfd22fc19029284aa66 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Micha=C5=82=20=C5=BBygowski?= <michal.zygowski@3mdeb.com>
Date: Mon, 6 Oct 2025 11:23:57 +0200
Subject: [PATCH 3396/3886] lib/dimm_info_util.c: Handle 16-bit memory bus
 extension for ECC
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Some silicon initialization modules, like OpenSIL report bus width
extension as 16 bits for ECC for DDR5 memories. Handle this case
correctly for DDR5 and LPDDR5 memories by reporting appropriate
bitfield of the SPD width. This field is used later by coreboot to
calculate the bus extension again, which results in 16bit extension
for ECC.

Change-Id: Ia0a9c221a5d047dd7feb212027f5da2399ccb8e1
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89482
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
---
 src/lib/dimm_info_util.c | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/src/lib/dimm_info_util.c b/src/lib/dimm_info_util.c
index d16cb46d0a..6ca707c542 100644
--- a/src/lib/dimm_info_util.c
+++ b/src/lib/dimm_info_util.c
@@ -45,6 +45,13 @@ uint8_t smbios_bus_width_to_spd_width(uint8_t ddr_type, uint16_t total_width,
 		else
 			out |= SPD_ECC_8BIT;
 		break;
+	case 16:
+		if (ddr_type == MEMORY_TYPE_DDR5 || ddr_type == MEMORY_TYPE_LPDDR5)
+			out |= SPD_ECC_8BIT_LP5_DDR5;
+		else
+			printk(BIOS_NOTICE, "Unknown number of extension bits %hu\n",
+			       extension_bits);
+		break;
 	case 0:
 		/* No extension bits */
 		break;

From 06446dd0ac844899df01fb72eb7cb4cb97e1639c Mon Sep 17 00:00:00 2001
From: Patrick Rudolph <patrick.rudolph@9elements.com>
Date: Fri, 5 Dec 2025 14:07:05 +0100
Subject: [PATCH 3397/3886] dram/ddr3: Add speed in MT/s

Fill in the speed in MT/s that the DIMM currently runs at and the
speed it could run at.

Change-Id: I936b97bd517f2fcf80ff403171fc89d4a4487761
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90396
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/device/dram/ddr3.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/src/device/dram/ddr3.c b/src/device/dram/ddr3.c
index c99255ba5a..eb87289481 100644
--- a/src/device/dram/ddr3.c
+++ b/src/device/dram/ddr3.c
@@ -542,6 +542,9 @@ enum cb_err spd_add_smbios17(const u8 channel, const u8 slot, const u16 selected
 	if (info->size_mb) {
 		dimm->ddr_type = MEMORY_TYPE_DDR3;
 		dimm->ddr_frequency = selected_freq;
+		dimm->configured_speed_mts = 2 * selected_freq;
+		if (info->tCK > 0)
+			dimm->max_speed_mts = 2 * NS2MHZ_DIV256 / info->tCK;
 		dimm->dimm_size = info->size_mb;
 		dimm->channel_num = channel;
 		dimm->rank_per_dimm = info->ranks;

From 571dbbe34588f853cfbd182742752c7b9be84bd6 Mon Sep 17 00:00:00 2001
From: Patrick Rudolph <patrick.rudolph@9elements.com>
Date: Sun, 15 Feb 2026 13:37:29 +0100
Subject: [PATCH 3398/3886] mb/lenovo/t430: Move TPM in devicetree.cb

Move the TPM entry to make the devicetree.cb look like the T530
devicetree.cb. Should not change any functionality, but changes the
TIMELESS build artifact.

Change-Id: Ia49c8fe9781e4d97aaf5ef38d5d76fdfc8c0f0be
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91282
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
---
 src/mainboard/lenovo/t430/devicetree.cb | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/src/mainboard/lenovo/t430/devicetree.cb b/src/mainboard/lenovo/t430/devicetree.cb
index 02a4c85344..198900b399 100644
--- a/src/mainboard/lenovo/t430/devicetree.cb
+++ b/src/mainboard/lenovo/t430/devicetree.cb
@@ -87,6 +87,9 @@ chip northbridge/intel/sandybridge
 					register "dock_event_enable" = "true"
 					device pnp ff.1 on end # dummy
 				end
+				chip drivers/pc80/tpm
+					device pnp 0c31.0 on end
+				end
 				chip ec/lenovo/h8
 					device pnp ff.2 on # dummy
 						io 0x60 = 0x62
@@ -138,9 +141,6 @@ chip northbridge/intel/sandybridge
 
 					register "has_thinker1" = "true"
 				end
-				chip drivers/pc80/tpm
-					device pnp 0c31.0 on end
-				end
 			end
 			device ref sata1 on end # SATA Controller 1
 			device ref smbus on # SMBus

From 33d873324ec37f0924eb0d0d78fedc9f71384be5 Mon Sep 17 00:00:00 2001
From: Patrick Rudolph <patrick.rudolph@9elements.com>
Date: Sun, 15 Feb 2026 13:52:53 +0100
Subject: [PATCH 3399/3886] mb/lenovo/*: Drop unused ACPI code

Drop useless ACPI code and make the codebase look more like the
T430 codebase. IASL doesn't remove empty scope blocks and it
causes binary differences in the produced DSDT.

TEST=TIMELESS build shows that T530 DSDT is now identical to the
     T430 DSDT.

Change-Id: Ie65668b98c5ee772a926a265d09ee20ab8d2e15e
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91284
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
---
 src/mainboard/lenovo/l520/acpi/ec.asl           | 4 ----
 src/mainboard/lenovo/t420/acpi/ec.asl           | 5 -----
 src/mainboard/lenovo/t420s/acpi/ec.asl          | 5 -----
 src/mainboard/lenovo/t430s/acpi/ec.asl          | 5 -----
 src/mainboard/lenovo/t520/acpi/ec.asl           | 5 -----
 src/mainboard/lenovo/t530/acpi/ec.asl           | 5 -----
 src/mainboard/lenovo/x1_carbon_gen1/acpi/ec.asl | 5 -----
 src/mainboard/lenovo/x201/acpi/ec.asl           | 5 -----
 src/mainboard/lenovo/x220/acpi/ec.asl           | 5 -----
 src/mainboard/lenovo/x230/acpi/ec.asl           | 5 -----
 10 files changed, 49 deletions(-)

diff --git a/src/mainboard/lenovo/l520/acpi/ec.asl b/src/mainboard/lenovo/l520/acpi/ec.asl
index 0e576b13d1..7e96ed79a0 100644
--- a/src/mainboard/lenovo/l520/acpi/ec.asl
+++ b/src/mainboard/lenovo/l520/acpi/ec.asl
@@ -1,7 +1,3 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
 #include <ec/lenovo/h8/acpi/ec.asl>
-
-Scope(\_SB.PCI0.LPCB.EC)
-{
-}
diff --git a/src/mainboard/lenovo/t420/acpi/ec.asl b/src/mainboard/lenovo/t420/acpi/ec.asl
index 7971d027b2..987593e919 100644
--- a/src/mainboard/lenovo/t420/acpi/ec.asl
+++ b/src/mainboard/lenovo/t420/acpi/ec.asl
@@ -1,9 +1,4 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
 #include <ec/lenovo/h8/acpi/ec.asl>
-
-Scope(\_SB.PCI0.LPCB.EC)
-{
-}
-
 #include <ec/lenovo/h8/acpi/thinkpad_bat_thresholds_b0.asl>
diff --git a/src/mainboard/lenovo/t420s/acpi/ec.asl b/src/mainboard/lenovo/t420s/acpi/ec.asl
index 7971d027b2..987593e919 100644
--- a/src/mainboard/lenovo/t420s/acpi/ec.asl
+++ b/src/mainboard/lenovo/t420s/acpi/ec.asl
@@ -1,9 +1,4 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
 #include <ec/lenovo/h8/acpi/ec.asl>
-
-Scope(\_SB.PCI0.LPCB.EC)
-{
-}
-
 #include <ec/lenovo/h8/acpi/thinkpad_bat_thresholds_b0.asl>
diff --git a/src/mainboard/lenovo/t430s/acpi/ec.asl b/src/mainboard/lenovo/t430s/acpi/ec.asl
index 7971d027b2..987593e919 100644
--- a/src/mainboard/lenovo/t430s/acpi/ec.asl
+++ b/src/mainboard/lenovo/t430s/acpi/ec.asl
@@ -1,9 +1,4 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
 #include <ec/lenovo/h8/acpi/ec.asl>
-
-Scope(\_SB.PCI0.LPCB.EC)
-{
-}
-
 #include <ec/lenovo/h8/acpi/thinkpad_bat_thresholds_b0.asl>
diff --git a/src/mainboard/lenovo/t520/acpi/ec.asl b/src/mainboard/lenovo/t520/acpi/ec.asl
index 7971d027b2..987593e919 100644
--- a/src/mainboard/lenovo/t520/acpi/ec.asl
+++ b/src/mainboard/lenovo/t520/acpi/ec.asl
@@ -1,9 +1,4 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
 #include <ec/lenovo/h8/acpi/ec.asl>
-
-Scope(\_SB.PCI0.LPCB.EC)
-{
-}
-
 #include <ec/lenovo/h8/acpi/thinkpad_bat_thresholds_b0.asl>
diff --git a/src/mainboard/lenovo/t530/acpi/ec.asl b/src/mainboard/lenovo/t530/acpi/ec.asl
index 7971d027b2..987593e919 100644
--- a/src/mainboard/lenovo/t530/acpi/ec.asl
+++ b/src/mainboard/lenovo/t530/acpi/ec.asl
@@ -1,9 +1,4 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
 #include <ec/lenovo/h8/acpi/ec.asl>
-
-Scope(\_SB.PCI0.LPCB.EC)
-{
-}
-
 #include <ec/lenovo/h8/acpi/thinkpad_bat_thresholds_b0.asl>
diff --git a/src/mainboard/lenovo/x1_carbon_gen1/acpi/ec.asl b/src/mainboard/lenovo/x1_carbon_gen1/acpi/ec.asl
index 7971d027b2..987593e919 100644
--- a/src/mainboard/lenovo/x1_carbon_gen1/acpi/ec.asl
+++ b/src/mainboard/lenovo/x1_carbon_gen1/acpi/ec.asl
@@ -1,9 +1,4 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
 #include <ec/lenovo/h8/acpi/ec.asl>
-
-Scope(\_SB.PCI0.LPCB.EC)
-{
-}
-
 #include <ec/lenovo/h8/acpi/thinkpad_bat_thresholds_b0.asl>
diff --git a/src/mainboard/lenovo/x201/acpi/ec.asl b/src/mainboard/lenovo/x201/acpi/ec.asl
index 1ce63054f8..6d2e71f8c0 100644
--- a/src/mainboard/lenovo/x201/acpi/ec.asl
+++ b/src/mainboard/lenovo/x201/acpi/ec.asl
@@ -5,10 +5,5 @@ Name(\TPSV, 90)
 Name(\FLVL, 0)
 
 #include <ec/lenovo/h8/acpi/ec.asl>
-
-Scope(\_SB.PCI0.LPCB.EC)
-{
-}
-
 #define H8_BAT_THRESHOLDS_BIT7
 #include <ec/lenovo/h8/acpi/thinkpad_bat_thresholds_24.asl>
diff --git a/src/mainboard/lenovo/x220/acpi/ec.asl b/src/mainboard/lenovo/x220/acpi/ec.asl
index 7971d027b2..987593e919 100644
--- a/src/mainboard/lenovo/x220/acpi/ec.asl
+++ b/src/mainboard/lenovo/x220/acpi/ec.asl
@@ -1,9 +1,4 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
 #include <ec/lenovo/h8/acpi/ec.asl>
-
-Scope(\_SB.PCI0.LPCB.EC)
-{
-}
-
 #include <ec/lenovo/h8/acpi/thinkpad_bat_thresholds_b0.asl>
diff --git a/src/mainboard/lenovo/x230/acpi/ec.asl b/src/mainboard/lenovo/x230/acpi/ec.asl
index 7971d027b2..987593e919 100644
--- a/src/mainboard/lenovo/x230/acpi/ec.asl
+++ b/src/mainboard/lenovo/x230/acpi/ec.asl
@@ -1,9 +1,4 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
 #include <ec/lenovo/h8/acpi/ec.asl>
-
-Scope(\_SB.PCI0.LPCB.EC)
-{
-}
-
 #include <ec/lenovo/h8/acpi/thinkpad_bat_thresholds_b0.asl>

From 24866fefef7601ea52aeb70df89760823e109da4 Mon Sep 17 00:00:00 2001
From: Hualin Wei <weihualin@huaqin.corp-partner.google.com>
Date: Tue, 23 Dec 2025 14:11:04 +0800
Subject: [PATCH 3400/3886] mb/google/fatcat/var/lapis: Add UFSC bit of new FP
 MCU

Lapis requires the addition of a new fingerprint module, and
the fingerprint module needs to be distinguished via UFSC when
updating the fingerprint module fw.

BUG=b:463867670
TEST=./config/payload_utils/generate_ufsc.py ap

Change-Id: I69846aa404adc76c6446de68749f0fe469e570a3
Signed-off-by: Hualin Wei <weihualin@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90602
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Pranava Y N <pranavayn@google.com>
---
 .../google/fatcat/variants/lapis/overridetree.cb       | 10 +++++++++-
 1 file changed, 9 insertions(+), 1 deletion(-)

diff --git a/src/mainboard/google/fatcat/variants/lapis/overridetree.cb b/src/mainboard/google/fatcat/variants/lapis/overridetree.cb
index 04565a14ef..a2da0752b0 100644
--- a/src/mainboard/google/fatcat/variants/lapis/overridetree.cb
+++ b/src/mainboard/google/fatcat/variants/lapis/overridetree.cb
@@ -22,6 +22,10 @@ fw_config
 		option TOUCHSCREEN_SOC_INTERFACE_I2C_LPSS	1
 		option TOUCHSCREEN_SOC_INTERFACE_I2C_THC	2
 	end
+	field SENSOR_HUB 23 23
+		option ISH_ABSENT	0
+		option ISH_PRESENT	1
+	end
 	field FINGERPRINT_INTERFACE 24 25
 		option FINGERPRINT_INTERFACE_UNKNOWN	0
 		option FINGERPRINT_INTERFACE_SPI	1
@@ -40,7 +44,7 @@ fw_config
 		option TRACKPAD_SOC_INTERFACE_I2C_LPSS	1
 		option TRACKPAD_SOC_INTERFACE_I2C_THC	2
 	end
-	field KB_BACKLIGHT_PRESENT 43 43
+	field KB_BACKLIGHT 43 43
 		option KB_BACKLIGHT_ABSENT	0
 		option KB_BACKLIGHT_PRESENT	1
 	end
@@ -48,6 +52,10 @@ fw_config
 		option WIFI_SAR_ID0	0
 		option WIFI_SAR_ID1	1
 	end
+	field FINGERPRINT_MCU 63 63
+		option FINGERPRINT_FT9001_FT9865	0
+		option FINGERPRINT_FT9001C_FT9849	1
+	end
 end
 
 chip soc/intel/pantherlake

From d88e98cf49993c8fecd70137b7c68c64948ea167 Mon Sep 17 00:00:00 2001
From: Pranava Y N <pranavayn@google.com>
Date: Tue, 17 Feb 2026 17:04:47 +0530
Subject: [PATCH 3401/3886] mb/google/fatcat/lapis: Remove RTD3 config for SSD

The lapis hardware design does not have a power load switch for
the SSD. Without it, the platform cannot cut off the main power rail
to the device to enter D3cold.
Therefore, remove the RTD3 chip driver and its associated configurations
in the overridetree to align with the hardware capability. The system
will support D3hot instead of D3cold.

BUG=None
TEST=Build and boot to OS on Lapis, verify SSD functions correctly and
power state transitions align with HW design.

Change-Id: I61f15165e1d41c4f347499e2a7200f30d18bcca7
Signed-off-by: Pranava Y N <pranavayn@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91308
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
---
 src/mainboard/google/fatcat/variants/lapis/overridetree.cb | 5 -----
 1 file changed, 5 deletions(-)

diff --git a/src/mainboard/google/fatcat/variants/lapis/overridetree.cb b/src/mainboard/google/fatcat/variants/lapis/overridetree.cb
index a2da0752b0..6855616bb9 100644
--- a/src/mainboard/google/fatcat/variants/lapis/overridetree.cb
+++ b/src/mainboard/google/fatcat/variants/lapis/overridetree.cb
@@ -405,11 +405,6 @@ chip soc/intel/pantherlake
 			.clk_req = 0,
 			.flags = PCIE_RP_CLK_REQ_DETECT | PCIE_RP_LTR | PCIE_RP_AER,
 			}"
-			chip soc/intel/common/block/pcie/rtd3
-				register "is_storage" = "true"
-				register "srcclk_pin" = "0"
-				device generic 0 on end
-			end
 		end # Gen4 SSD
 
 		device ref cnvi_wifi on

From c9578eac246f7f4ada9115037e4f06bc5ab4d124 Mon Sep 17 00:00:00 2001
From: Appukuttan V K <appukuttan.vk@intel.com>
Date: Fri, 13 Feb 2026 11:43:33 +0530
Subject: [PATCH 3402/3886] mb/google/ocelot: Add THC-SPI Touchscreen support
 in fw_config

Add support for THC-SPI touchscreen configuration in the GPIO pad-based
override logic.

The GPP_E17 pin serves dual purposes depending on the hardware
configuration:
 - When touchscreen THC-SPI is present: NF3 (THC HID-SPI CS0)
 - When fingerprint sensor is present: NF5 (GSPI0 CS0)

The firmware configuration logic now prioritizes touchscreen THC-SPI
over fingerprint sensor configuration, as these are mutually exclusive
hardware configurations.

BUG=None
TEST=Build ocelot and verify correct GPIO configuration based on
fw_config settings for both touchscreen THC-SPI and fingerprint sensor
configurations

Change-Id: I93deb6352cd0f1168ad53819151c705c6ce48b28
Signed-off-by: Appukuttan V K <appukuttan.vk@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91197
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: P, Usha <usha.p@intel.com>
---
 .../google/ocelot/variants/ocelot/fw_config.c    | 16 +++++++++++++++-
 1 file changed, 15 insertions(+), 1 deletion(-)

diff --git a/src/mainboard/google/ocelot/variants/ocelot/fw_config.c b/src/mainboard/google/ocelot/variants/ocelot/fw_config.c
index 003cd84728..9984ef5e89 100644
--- a/src/mainboard/google/ocelot/variants/ocelot/fw_config.c
+++ b/src/mainboard/google/ocelot/variants/ocelot/fw_config.c
@@ -605,7 +605,21 @@ void fw_config_gpio_padbased_override(struct pad_config *padbased_table)
 		GPIO_PADBASED_OVERRIDE(padbased_table, ish_disable_pads);
 	}
 
-	if (fw_config_probe(FW_CONFIG(FP, FP_PRESENT))) {
+	/*
+	 * *=========================================================================*
+	 * |             Usage                     |           GPP_E17               |
+	 * *=========================================================================*
+	 * | Touchscreen in THC-SPI (with rework)  | NF3: THC HID-SPI CS0            |
+	 * *---------------------------------------*---------------------------------*
+	 * | FPS present         (without rework)  | NF5: GSPI0 CS0                  |
+	 * *---------------------------------------*---------------------------------*
+	 *
+	 * NOTE: 1. CBI selecting TS THC-SPI or implies TS rework is applied for the board.
+	 *       2. CBI selecting TS THC-SPI with FPS present is invalid case.
+	 */
+	if (fw_config_probe(FW_CONFIG(TOUCHSCREEN, TOUCHSCREEN_THC_SPI))) {
+		/*  Board has TS THC-SPI rework and does not support FPS*/
+	} else if (fw_config_probe(FW_CONFIG(FP, FP_PRESENT))) {
 		GPIO_PADBASED_OVERRIDE(padbased_table, fp_enable_pads);
 	} else {
 		GPIO_PADBASED_OVERRIDE(padbased_table, fp_disable_pads);

From 220669643b500825d97482c88d6ead0ce8fed840 Mon Sep 17 00:00:00 2001
From: Subrata Banik <subratabanik@google.com>
Date: Wed, 18 Feb 2026 12:31:05 +0530
Subject: [PATCH 3403/3886] soc/qualcomm: Add Kconfig to skip redundant MMU
 toggling

Introduce SOC_QUALCOMM_QCLIB_SKIP_MMU_TOGGLE to allow platforms to
maintain the MMU state across the QCLib execution boundary.

Traditionally, coreboot enables the MMU and performs cache maintenance
before disabling it and handing control to QCLib. QCLib then performs
its own initialization: saving MMU registers, performing cache flushes,
and disabling the MMU before returning to coreboot. During the
subsequent entry, QCLib would restore registers and repeat the cycle.

By selecting this Kconfig, we optimize boot time by avoiding these
repeated enable/disable operations. QCLib is permitted to utilize the
MMU context already established by coreboot, bypassing redundant
reinitialization, register restoration, and expensive cache flushes
to the Point of Coherency.

- Legacy platforms continue to toggle the MMU by default.
- Platforms selecting this option bypass mmu_disable() and mmu_enable().

BUG=b:449871690, b:477139887
TEST=Able to reduce boot time by 600ms while booting google/quenbi.

Change-Id: I6b5e199afc27dcb27d74d2753d2ce269ee22f0ac
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90041
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
---
 src/soc/qualcomm/common/Kconfig | 13 +++++++++++++
 src/soc/qualcomm/common/qclib.c | 30 +++++++++++++++++++-----------
 2 files changed, 32 insertions(+), 11 deletions(-)

diff --git a/src/soc/qualcomm/common/Kconfig b/src/soc/qualcomm/common/Kconfig
index 5d692779b0..98760cec63 100644
--- a/src/soc/qualcomm/common/Kconfig
+++ b/src/soc/qualcomm/common/Kconfig
@@ -41,4 +41,17 @@ config QC_RAMDUMP_ENABLE
 	  Ramdump is a debug image that is loaded during a system crash to capture
 	  memory contents for post-crash analysis.
 
+config SOC_QUALCOMM_QCLIB_SKIP_MMU_TOGGLE
+	bool
+	default n
+	help
+	  Avoid disabling and re-enabling the MMU during QCLib execution.
+
+	  Select this option if the platform's QCLib version supports running
+	  within the existing coreboot MMU configuration without modification.
+
+	  Enabling this reduces boot latency by eliminating redundant cache
+	  flushes and TLB invalidations associated with mmu_disable() and
+	  mmu_enable() calls.
+
 endif
diff --git a/src/soc/qualcomm/common/qclib.c b/src/soc/qualcomm/common/qclib.c
index 8dad95715d..8b7843540b 100644
--- a/src/soc/qualcomm/common/qclib.c
+++ b/src/soc/qualcomm/common/qclib.c
@@ -224,20 +224,28 @@ static void qclib_prepare_and_run(void)
 	printk(BIOS_DEBUG, "Jumping to QCLib code at %p(%p)\n",
 		prog_entry(&qclib), prog_entry_arg(&qclib));
 
-	/* back-up mmu context before disabling mmu and executing qclib */
-	mmu_save_context(&pre_qclib_mmu_context);
-	/* disable mmu before jumping to qclib. mmu_disable also
-	   flushes and invalidates caches before disabling mmu. */
-	mmu_disable();
+	/*
+	 * Backup MMU context and disable the MMU before executing QCLib,
+	 * unless the platform handles QCLib with the MMU enabled.
+	 * mmu_disable() also handles required cache maintenance.
+	 */
+	if (!CONFIG(SOC_QUALCOMM_QCLIB_SKIP_MMU_TOGGLE)) {
+		mmu_save_context(&pre_qclib_mmu_context);
+		mmu_disable();
+	}
 
 	prog_run(&qclib);
 
-	/* Before returning, QCLib flushes cache and disables mmu.
-	   Explicitly disable mmu (flush, invalidate and disable mmu)
-	   before re-enabling mmu with backed-up mmu context */
-	mmu_disable();
-	mmu_restore_context(&pre_qclib_mmu_context);
-	mmu_enable();
+	/*
+	 * Post-QCLib execution: If the MMU was toggled off, ensure it is
+	 * cleanly disabled (flushed/invalidated) before restoring the
+	 * previous context and re-enabling. Otherwise, just restore context.
+	 */
+	if (!CONFIG(SOC_QUALCOMM_QCLIB_SKIP_MMU_TOGGLE)) {
+		mmu_disable();
+		mmu_restore_context(&pre_qclib_mmu_context);
+		mmu_enable();
+	}
 
 	if (qclib_cb_if_table.global_attributes & QCLIB_GA_FORCE_COLD_REBOOT) {
 		printk(BIOS_NOTICE, "QcLib requested cold reboot\n");

From 7e8850a8624b44d038b5bdb0dc310e91f2e77ba9 Mon Sep 17 00:00:00 2001
From: Angel Pons <th3fanbus@gmail.com>
Date: Wed, 18 Feb 2026 21:43:18 +0100
Subject: [PATCH 3404/3886] mb/google/*/cfr.c: Drop initial empty line

For some reason, there is a blank line at the beginning of these files.
There is no reason to keep this line, so drop it for consistency.

Change-Id: I38092fae7a3f32b34c15d1b4500c4009fca4d5e2
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91339
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Jakub "Kuba" Czapiga <czapiga@google.com>
---
 src/mainboard/google/brya/cfr.c     | 1 -
 src/mainboard/google/drallion/cfr.c | 1 -
 src/mainboard/google/hatch/cfr.c    | 1 -
 src/mainboard/google/jecht/cfr.c    | 1 -
 src/mainboard/google/puff/cfr.c     | 1 -
 src/mainboard/google/rex/cfr.c      | 1 -
 src/mainboard/google/sarien/cfr.c   | 1 -
 src/mainboard/google/volteer/cfr.c  | 1 -
 8 files changed, 8 deletions(-)

diff --git a/src/mainboard/google/brya/cfr.c b/src/mainboard/google/brya/cfr.c
index 637e1b38d5..2128145042 100644
--- a/src/mainboard/google/brya/cfr.c
+++ b/src/mainboard/google/brya/cfr.c
@@ -1,4 +1,3 @@
-
 /* SPDX-License-Identifier: GPL-2.0-only */
 
 #include <boot/coreboot_tables.h>
diff --git a/src/mainboard/google/drallion/cfr.c b/src/mainboard/google/drallion/cfr.c
index aa9265db7d..805b2870a1 100644
--- a/src/mainboard/google/drallion/cfr.c
+++ b/src/mainboard/google/drallion/cfr.c
@@ -1,4 +1,3 @@
-
 /* SPDX-License-Identifier: GPL-2.0-only */
 
 #include <boot/coreboot_tables.h>
diff --git a/src/mainboard/google/hatch/cfr.c b/src/mainboard/google/hatch/cfr.c
index 76f12e232c..ac424fbb16 100644
--- a/src/mainboard/google/hatch/cfr.c
+++ b/src/mainboard/google/hatch/cfr.c
@@ -1,4 +1,3 @@
-
 /* SPDX-License-Identifier: GPL-2.0-only */
 
 #include <boot/coreboot_tables.h>
diff --git a/src/mainboard/google/jecht/cfr.c b/src/mainboard/google/jecht/cfr.c
index 9f4d19088e..199f2e54d9 100644
--- a/src/mainboard/google/jecht/cfr.c
+++ b/src/mainboard/google/jecht/cfr.c
@@ -1,4 +1,3 @@
-
 /* SPDX-License-Identifier: GPL-2.0-only */
 
 #include <boot/coreboot_tables.h>
diff --git a/src/mainboard/google/puff/cfr.c b/src/mainboard/google/puff/cfr.c
index e50af539c8..10df17757c 100644
--- a/src/mainboard/google/puff/cfr.c
+++ b/src/mainboard/google/puff/cfr.c
@@ -1,4 +1,3 @@
-
 /* SPDX-License-Identifier: GPL-2.0-only */
 
 #include <boot/coreboot_tables.h>
diff --git a/src/mainboard/google/rex/cfr.c b/src/mainboard/google/rex/cfr.c
index a84d9aae4d..d64bbc7b79 100644
--- a/src/mainboard/google/rex/cfr.c
+++ b/src/mainboard/google/rex/cfr.c
@@ -1,4 +1,3 @@
-
 /* SPDX-License-Identifier: GPL-2.0-only */
 
 #include <boot/coreboot_tables.h>
diff --git a/src/mainboard/google/sarien/cfr.c b/src/mainboard/google/sarien/cfr.c
index aa9265db7d..805b2870a1 100644
--- a/src/mainboard/google/sarien/cfr.c
+++ b/src/mainboard/google/sarien/cfr.c
@@ -1,4 +1,3 @@
-
 /* SPDX-License-Identifier: GPL-2.0-only */
 
 #include <boot/coreboot_tables.h>
diff --git a/src/mainboard/google/volteer/cfr.c b/src/mainboard/google/volteer/cfr.c
index 76f12e232c..ac424fbb16 100644
--- a/src/mainboard/google/volteer/cfr.c
+++ b/src/mainboard/google/volteer/cfr.c
@@ -1,4 +1,3 @@
-
 /* SPDX-License-Identifier: GPL-2.0-only */
 
 #include <boot/coreboot_tables.h>

From f9f81e483941c7b5741430e306a122a5644e3630 Mon Sep 17 00:00:00 2001
From: Angel Pons <th3fanbus@gmail.com>
Date: Wed, 18 Feb 2026 20:39:35 +0100
Subject: [PATCH 3405/3886] mb/lenovo/x220: Replace CFR enums with booleans

Commit f530d37da736 ("mb/lenovo/x220: Add PCIe ports in CFR") introduced
several enum options for "Enabled"/"Disabled" settings. These work like
bool options, except that they add extra bloat to the resulting CFR data
structures.

Replace the enum options with bool options. Also rename the macro as it
no longer generates an enum option. While we're at it, properly format
"Wi-Fi" and drop a blank line at the start of a file.

Also, since checkpatch complains about the macro including a trailing
semicolon, drop it from the macro definition and add it at the end of
every use of the macro.

Change-Id: I7889e22d12e01171ed77ae98d29bbd067e45d82b
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91340
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
---
 src/mainboard/lenovo/x220/cfr.c     |  9 ++++-----
 src/southbridge/intel/bd82x6x/cfr.h | 18 +++++++-----------
 2 files changed, 11 insertions(+), 16 deletions(-)

diff --git a/src/mainboard/lenovo/x220/cfr.c b/src/mainboard/lenovo/x220/cfr.c
index 2ebfd32d77..e37464a07a 100644
--- a/src/mainboard/lenovo/x220/cfr.c
+++ b/src/mainboard/lenovo/x220/cfr.c
@@ -1,4 +1,3 @@
-
 /* SPDX-License-Identifier: GPL-2.0-only */
 
 #include <boot/coreboot_tables.h>
@@ -8,12 +7,12 @@
 #include <northbridge/intel/sandybridge/cfr.h>
 #include <southbridge/intel/bd82x6x/cfr.h>
 
-GEN_RP_ENUM(1, "Wifi")
+DEFINE_RP_ENABLE_OPTION(1, "Wi-Fi");
 #if CONFIG(BOARD_LENOVO_X220)
-GEN_RP_ENUM(3, "ExpressCard")
+DEFINE_RP_ENABLE_OPTION(3, "ExpressCard");
 #endif
-GEN_RP_ENUM(4, "SD Card Reader")
-GEN_RP_ENUM(6, "xHCI")
+DEFINE_RP_ENABLE_OPTION(4, "SD Card Reader");
+DEFINE_RP_ENABLE_OPTION(6, "xHCI");
 
 static struct sm_obj_form pcie = {
 	.ui_name = "PCH PCIe",
diff --git a/src/southbridge/intel/bd82x6x/cfr.h b/src/southbridge/intel/bd82x6x/cfr.h
index d70650463a..064636d6b5 100644
--- a/src/southbridge/intel/bd82x6x/cfr.h
+++ b/src/southbridge/intel/bd82x6x/cfr.h
@@ -11,17 +11,13 @@
 #include <southbridge/intel/common/pmutil.h>
 #include "me.h"
 
-#define GEN_RP_ENUM(x, y)					\
-static const struct sm_object pcie_rp##x = SM_DECLARE_ENUM({	\
-	.opt_name	= "pch_pcie_enable_rp"#x,		\
-	.ui_name	= y,					\
-	.ui_helptext	= "Enable or disable "#y,		\
-	.default_value	= 1,					\
-	.values		= (const struct sm_enum_value[]) {	\
-		{ "Disabled",	0	},			\
-		{ "Enabled",	1	},			\
-		SM_ENUM_VALUE_END	},			\
-});
+#define DEFINE_RP_ENABLE_OPTION(_rp, _name)			\
+static const struct sm_object pcie_rp##_rp = SM_DECLARE_BOOL({	\
+	.opt_name	= "pch_pcie_enable_rp"#_rp,		\
+	.ui_name	= _name,				\
+	.ui_helptext	= "Enable or disable "#_name,		\
+	.default_value	= true,					\
+})
 
 /* Power state after power loss */
 static const struct sm_object power_on_after_fail = SM_DECLARE_ENUM({

From 0ff3c3d2ecb05c30706d09f79dd39f62f7bbfa4d Mon Sep 17 00:00:00 2001
From: Angel Pons <th3fanbus@gmail.com>
Date: Wed, 18 Feb 2026 21:02:41 +0100
Subject: [PATCH 3406/3886] ec/lenovo/h8: Replace CFR enums with booleans

Boolean options are intended to represent generic "Enable"/"Disable"
options, but without enum options' extra bloat in the CFR structures.

The "volume" option has been left as-is because the code reading its
value does not seem to handle it like a boolean.

Change-Id: If183957cff6097187904e0d76c7d3ad997fe365c
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91341
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/ec/lenovo/h8/cfr.h | 78 ++++++++++--------------------------------
 1 file changed, 19 insertions(+), 59 deletions(-)

diff --git a/src/ec/lenovo/h8/cfr.h b/src/ec/lenovo/h8/cfr.h
index b410f2d449..fbda80471a 100644
--- a/src/ec/lenovo/h8/cfr.h
+++ b/src/ec/lenovo/h8/cfr.h
@@ -11,27 +11,19 @@
 #include "h8.h"
 
 /* Bluetooth */
-static const struct sm_object bluetooth = SM_DECLARE_ENUM({
+static const struct sm_object bluetooth = SM_DECLARE_BOOL({
 	.opt_name	= "bluetooth",
 	.ui_name	= "Bluetooth",
 	.ui_helptext	= "Enable or disable the bluetooth module",
-	.default_value	= 1,
-	.values		= (const struct sm_enum_value[]) {
-				{ "Disabled",	0	},
-				{ "Enabled",	1	},
-				SM_ENUM_VALUE_END	},
+	.default_value	= true,
 });
 
 /* Keyboard Backlight */
-static const struct sm_object backlight = SM_DECLARE_ENUM({
+static const struct sm_object backlight = SM_DECLARE_BOOL({
 	.opt_name	= "backlight",
 	.ui_name	= "Keyboard Backlight",
 	.ui_helptext	= "Enable or disable the keyboard backlight",
-	.default_value	= 0,
-	.values		= (const struct sm_enum_value[]) {
-				{ "Disabled",	0	},
-				{ "Enabled",	1	},
-				SM_ENUM_VALUE_END	},
+	.default_value	= false,
 });
 
 /* USB Always-On */
@@ -48,15 +40,11 @@ static const struct sm_object usb_always_on = SM_DECLARE_ENUM({
 });
 
 /* Ultrawideband */
-static const struct sm_object uwb = SM_DECLARE_ENUM({
+static const struct sm_object uwb = SM_DECLARE_BOOL({
 	.opt_name	= "uwb",
 	.ui_name	= "Ultrawideband",
 	.ui_helptext	= "TBD",
-	.default_value	= 1,
-	.values		= (const struct sm_enum_value[]) {
-				{ "Disabled",	0	},
-				{ "Enabled",	1	},
-				SM_ENUM_VALUE_END	},
+	.default_value	= true,
 });
 
 /* Volume control */
@@ -72,87 +60,59 @@ static const struct sm_object volume = SM_DECLARE_ENUM({
 });
 
 /* WLAN */
-static const struct sm_object wlan = SM_DECLARE_ENUM({
+static const struct sm_object wlan = SM_DECLARE_BOOL({
 	.opt_name	= "wlan",
 	.ui_name	= "WLAN",
 	.ui_helptext	= "Enable or disable the WLAN module",
-	.default_value	= 1,
-	.values		= (const struct sm_enum_value[]) {
-				{ "Disabled",	0	},
-				{ "Enabled",	1	},
-				SM_ENUM_VALUE_END	},
+	.default_value	= true,
 });
 
 /* WWAN */
-static const struct sm_object wwan = SM_DECLARE_ENUM({
+static const struct sm_object wwan = SM_DECLARE_BOOL({
 	.opt_name	= "wwan",
 	.ui_name	= "WWAN",
 	.ui_helptext	= "Enable or disable the WWAN module",
-	.default_value	= 1,
-	.values		= (const struct sm_enum_value[]) {
-				{ "Disabled",	0	},
-				{ "Enabled",	1	},
-				SM_ENUM_VALUE_END	},
+	.default_value	= true,
 });
 
 /* Power Management Beeps */
-static const struct sm_object pm_beeps = SM_DECLARE_ENUM({
+static const struct sm_object pm_beeps = SM_DECLARE_BOOL({
 	.opt_name	= "power_management_beeps",
 	.ui_name	= "Power Management Beeps",
 	.ui_helptext	= "Enable or disable power management beeps",
-	.default_value	= 1,
-	.values		= (const struct sm_enum_value[]) {
-				{ "Disabled",	0	},
-				{ "Enabled",	1	},
-				SM_ENUM_VALUE_END	},
+	.default_value	= true,
 });
 
 /* Low Battery Beep */
-static const struct sm_object battery_beep = SM_DECLARE_ENUM({
+static const struct sm_object battery_beep = SM_DECLARE_BOOL({
 	.opt_name	= "low_battery_beep",
 	.ui_name	= "Low Battery Beep",
 	.ui_helptext	= "Enable or disable low battery beep",
-	.default_value	= 1,
-	.values		= (const struct sm_enum_value[]) {
-				{ "Disabled",	0	},
-				{ "Enabled",	1	},
-				SM_ENUM_VALUE_END	},
+	.default_value	= true,
 });
 
 /* Fn-CTRL Swap */
-static const struct sm_object fn_ctrl_swap = SM_DECLARE_ENUM({
+static const struct sm_object fn_ctrl_swap = SM_DECLARE_BOOL({
 	.opt_name	= "fn_ctrl_swap",
 	.ui_name	= "Swap Fn and CTRL",
 	.ui_helptext	= "Swap the left Fn and CTRL keys",
 	.default_value	= CONFIG(H8_FN_CTRL_SWAP),
-	.values		= (const struct sm_enum_value[]) {
-				{ "Disabled",	0	},
-				{ "Enabled",	1	},
-				SM_ENUM_VALUE_END	},
 });
 
 /* Fn Lock */
-static const struct sm_object sticky_fn = SM_DECLARE_ENUM({
+static const struct sm_object sticky_fn = SM_DECLARE_BOOL({
 	.opt_name	= "sticky_fn",
 	.ui_name	= "Sticky Fn key",
 	.ui_helptext	= "Function key acts as a toggle",
-	.default_value	= 0,
-	.values		= (const struct sm_enum_value[]) {
-				{ "Disabled",	0	},
-				{ "Enabled",	1	},
-				SM_ENUM_VALUE_END	},
+	.default_value	= false,
 });
 
 /* Function keys primary */
-static const struct sm_object f1_to_f12_as_primary = SM_DECLARE_ENUM({
+static const struct sm_object f1_to_f12_as_primary = SM_DECLARE_BOOL({
 	.opt_name	= "f1_to_f12_as_primary",
 	.ui_name	= "Primary Function keys",
 	.ui_helptext	= "F1-F12 default act as function keys",
-	.default_value	= 1,
-	.values		= (const struct sm_enum_value[]) {
-				{ "Disabled",	0	},
-				{ "Enabled",	1	},
-				SM_ENUM_VALUE_END	},
+	.default_value	= true,
 });
 
 #endif /* _LENOVO_H8_CFR_H_ */

From d19e5d2550b1182b89ae4310ee5afa33fb27d81a Mon Sep 17 00:00:00 2001
From: Angel Pons <th3fanbus@gmail.com>
Date: Wed, 18 Feb 2026 21:08:32 +0100
Subject: [PATCH 3407/3886] ec/lenovo/pmh7: Replace CFR enums with booleans

Boolean options are intended to represent generic "Enable"/"Disable"
options, but without enum options' extra bloat in the CFR structures.

Change-Id: I3c73f289271eb4bba899bbfe9d3036171cb31d7b
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91342
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
---
 src/ec/lenovo/pmh7/cfr.h | 16 ++++------------
 1 file changed, 4 insertions(+), 12 deletions(-)

diff --git a/src/ec/lenovo/pmh7/cfr.h b/src/ec/lenovo/pmh7/cfr.h
index 329fb56a3e..bda05edeea 100644
--- a/src/ec/lenovo/pmh7/cfr.h
+++ b/src/ec/lenovo/pmh7/cfr.h
@@ -10,27 +10,19 @@
 #include <drivers/option/cfr_frontend.h>
 
 /* Touchpad */
-static const struct sm_object touchpad = SM_DECLARE_ENUM({
+static const struct sm_object touchpad = SM_DECLARE_BOOL({
 	.opt_name	= "touchpad",
 	.ui_name	= "Touchpad",
 	.ui_helptext	= "Enable or disable the touchpad",
-	.default_value	= 1,
-	.values		= (const struct sm_enum_value[]) {
-				{ "Disabled",	0	},
-				{ "Enabled",	1	},
-				SM_ENUM_VALUE_END	},
+	.default_value	= true,
 });
 
 /* Trackpoint */
-static const struct sm_object trackpoint = SM_DECLARE_ENUM({
+static const struct sm_object trackpoint = SM_DECLARE_BOOL({
 	.opt_name	= "trackpoint",
 	.ui_name	= "Trackpoint",
 	.ui_helptext	= "Enable or disable the trackpoint",
-	.default_value	= 1,
-	.values		= (const struct sm_enum_value[]) {
-				{ "Disabled",	0	},
-				{ "Enabled",	1	},
-				SM_ENUM_VALUE_END	},
+	.default_value	= true,
 });
 
 #endif /* _LENOVO_PMH7_CFR_H_ */

From ed10b36edf956adc965941a97e33e6f64f2aa6f6 Mon Sep 17 00:00:00 2001
From: Angel Pons <th3fanbus@gmail.com>
Date: Wed, 18 Feb 2026 21:09:46 +0100
Subject: [PATCH 3408/3886] ec/google/chromeec: Replace CFR enums with booleans

Boolean options are intended to represent generic "Enable"/"Disable"
options, but without enum options' extra bloat in the CFR structures.

In this case, the callback function already treated the option as if
it were a boolean option, which likely only worked by chance.

Change-Id: I7e53c791d48bd5ce5271505c59856bf7ff18e6d0
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91343
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/ec/google/chromeec/cfr.h | 9 ++-------
 1 file changed, 2 insertions(+), 7 deletions(-)

diff --git a/src/ec/google/chromeec/cfr.h b/src/ec/google/chromeec/cfr.h
index 2972bd5424..07ca0e9b68 100644
--- a/src/ec/google/chromeec/cfr.h
+++ b/src/ec/google/chromeec/cfr.h
@@ -14,20 +14,15 @@ static void update_fan_control(struct sm_object *new)
 {
 	if (!CONFIG(EC_GOOGLE_CHROMEEC_AUTO_FAN_CTRL) && !google_chromeec_has_fan()) {
 		new->sm_bool.flags = CFR_OPTFLAG_SUPPRESS;
-		new->sm_bool.default_value = 0;
+		new->sm_bool.default_value = false;
 	}
 }
 
-static const struct sm_object auto_fan_control = SM_DECLARE_ENUM({
+static const struct sm_object auto_fan_control = SM_DECLARE_BOOL({
 	.opt_name       = "auto_fan_control",
 	.ui_name        = "Automatic Fan Control",
 	.ui_helptext    = "Enable or disable automatic fan control.",
 	.default_value  = CONFIG(EC_GOOGLE_CHROMEEC_AUTO_FAN_CTRL),
-	.values         = (struct sm_enum_value[]) {
-		{ "Enabled", 1 },
-		{ "Disabled", 0 },
-		SM_ENUM_VALUE_END,
-	},
 }, WITH_CALLBACK(update_fan_control));
 
 static const struct sm_enum_value ec_backlight_values[] = {

From 71b716739626fddc99b426c18df8888b67aa288a Mon Sep 17 00:00:00 2001
From: Angel Pons <th3fanbus@gmail.com>
Date: Wed, 18 Feb 2026 21:17:23 +0100
Subject: [PATCH 3409/3886] mb/lenovo/sklkbl_thinkpad: Replace CFR enums with
 booleans

Boolean options are intended to represent generic "Enable"/"Disable"
options, but without enum options' extra bloat in the CFR structures.

In this case, the callback function already treated the option as if
it were a boolean option, which likely only worked by chance.

Change-Id: I747ecd0b5a33d2773eda409e6578362d694154ee
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91344
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/lenovo/sklkbl_thinkpad/cfr.c | 6 +-----
 1 file changed, 1 insertion(+), 5 deletions(-)

diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/cfr.c b/src/mainboard/lenovo/sklkbl_thinkpad/cfr.c
index b5d979806d..213c90a17d 100644
--- a/src/mainboard/lenovo/sklkbl_thinkpad/cfr.c
+++ b/src/mainboard/lenovo/sklkbl_thinkpad/cfr.c
@@ -24,11 +24,7 @@ static const struct sm_object dgpu = SM_DECLARE_ENUM({
 	.opt_name	= "dgpu_enable",
 	.ui_name	= "dGPU",
 	.ui_helptext	= "Enable or disable the dGPU",
-	.default_value	= 0,
-	.values		= (const struct sm_enum_value[]) {
-				{ "Disabled",	0	},
-				{ "Enabled",	1	},
-				SM_ENUM_VALUE_END	},
+	.default_value	= false,
 }, WITH_CALLBACK(update_dgpu));
 
 static struct sm_obj_form system = {

From e7c05d666c42ea9abbd0bc7652b1c4e11ed89d81 Mon Sep 17 00:00:00 2001
From: Angel Pons <th3fanbus@gmail.com>
Date: Wed, 18 Feb 2026 21:19:45 +0100
Subject: [PATCH 3410/3886] mb/google/volteer: Replace CFR enums with booleans

Boolean options are intended to represent generic "Enable"/"Disable"
options, but without enum options' extra bloat in the CFR structures.

Change-Id: I8f3a69dfb9fb915c44c9a5486512aa82c2615fab
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91345
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
---
 src/mainboard/google/volteer/cfr.c | 8 ++------
 1 file changed, 2 insertions(+), 6 deletions(-)

diff --git a/src/mainboard/google/volteer/cfr.c b/src/mainboard/google/volteer/cfr.c
index ac424fbb16..3ddcdb1a19 100644
--- a/src/mainboard/google/volteer/cfr.c
+++ b/src/mainboard/google/volteer/cfr.c
@@ -6,17 +6,13 @@
 #include <intelblocks/cfr.h>
 #include <soc/cfr.h>
 
-static const struct sm_object touchpad_wake = SM_DECLARE_ENUM({
+static const struct sm_object touchpad_wake = SM_DECLARE_BOOL({
 	.opt_name	= "touchpad_wake",
 	.ui_name	= "Touchpad Wake",
 	.ui_helptext	= "Enable or disable touchpad wake from sleep.\n"
 			  "Disabled by default to prevent random wakeups when\n"
 			  "the system is moved while sleeping.",
-	.default_value	= 0,
-	.values		= (const struct sm_enum_value[]) {
-				{ "Disabled",	0	},
-				{ "Enabled",	1	},
-				SM_ENUM_VALUE_END	},
+	.default_value	= false,
 });
 
 static struct sm_obj_form system = {

From 9a58dc7fee330021954e913c85b409776ee23d83 Mon Sep 17 00:00:00 2001
From: Angel Pons <th3fanbus@gmail.com>
Date: Wed, 18 Feb 2026 21:21:25 +0100
Subject: [PATCH 3411/3886] mb/google/auron: Replace CFR enums with booleans

Boolean options are intended to represent generic "Enable"/"Disable"
options, but without enum options' extra bloat in the CFR structures.

Change-Id: Ib480c7dcd99eb5bf16b124584b4e7dbad90d0c84
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91346
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
---
 src/mainboard/google/auron/cfr.c | 8 ++------
 1 file changed, 2 insertions(+), 6 deletions(-)

diff --git a/src/mainboard/google/auron/cfr.c b/src/mainboard/google/auron/cfr.c
index 90106a5586..dea0e812be 100644
--- a/src/mainboard/google/auron/cfr.c
+++ b/src/mainboard/google/auron/cfr.c
@@ -5,15 +5,11 @@
 #include <ec/google/chromeec/cfr.h>
 #include <soc/cfr.h>
 
-static const struct sm_object touchscreen = SM_DECLARE_ENUM({
+static const struct sm_object touchscreen = SM_DECLARE_BOOL({
 	.opt_name	= "touchscreen",
 	.ui_name	= "Touchscreen",
 	.ui_helptext	= "Enable or disable the integrated touchscreen device",
-	.default_value	= 1,
-	.values		= (const struct sm_enum_value[]) {
-		{ "Disabled",		0		},
-		{ "Enabled",		1		},
-		SM_ENUM_VALUE_END			},
+	.default_value	= true,
 #if !CONFIG(BOARD_GOOGLE_LULU)
 	.flags		= CFR_OPTFLAG_SUPPRESS,
 #endif

From 6b481c73dd1f4a14d116ec41fa0db7fb419be71a Mon Sep 17 00:00:00 2001
From: Angel Pons <th3fanbus@gmail.com>
Date: Wed, 18 Feb 2026 21:22:24 +0100
Subject: [PATCH 3412/3886] mb/google/hatch: Replace CFR enums with booleans

Boolean options are intended to represent generic "Enable"/"Disable"
options, but without enum options' extra bloat in the CFR structures.

Change-Id: I77bfefd0bf173da34675ad64253daae472834bb8
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91347
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
---
 src/mainboard/google/hatch/cfr.c | 8 ++------
 1 file changed, 2 insertions(+), 6 deletions(-)

diff --git a/src/mainboard/google/hatch/cfr.c b/src/mainboard/google/hatch/cfr.c
index ac424fbb16..3ddcdb1a19 100644
--- a/src/mainboard/google/hatch/cfr.c
+++ b/src/mainboard/google/hatch/cfr.c
@@ -6,17 +6,13 @@
 #include <intelblocks/cfr.h>
 #include <soc/cfr.h>
 
-static const struct sm_object touchpad_wake = SM_DECLARE_ENUM({
+static const struct sm_object touchpad_wake = SM_DECLARE_BOOL({
 	.opt_name	= "touchpad_wake",
 	.ui_name	= "Touchpad Wake",
 	.ui_helptext	= "Enable or disable touchpad wake from sleep.\n"
 			  "Disabled by default to prevent random wakeups when\n"
 			  "the system is moved while sleeping.",
-	.default_value	= 0,
-	.values		= (const struct sm_enum_value[]) {
-				{ "Disabled",	0	},
-				{ "Enabled",	1	},
-				SM_ENUM_VALUE_END	},
+	.default_value	= false,
 });
 
 static struct sm_obj_form system = {

From 90f9d9e7c681ae8958727729912c826ae80545a7 Mon Sep 17 00:00:00 2001
From: Angel Pons <th3fanbus@gmail.com>
Date: Wed, 18 Feb 2026 21:23:18 +0100
Subject: [PATCH 3413/3886] mb/google/poppy: Replace CFR enums with booleans

Boolean options are intended to represent generic "Enable"/"Disable"
options, but without enum options' extra bloat in the CFR structures.

Change-Id: I491f92b334d0e9f98737b94a7232e9361e86743d
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91348
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/google/poppy/cfr.c | 6 +-----
 1 file changed, 1 insertion(+), 5 deletions(-)

diff --git a/src/mainboard/google/poppy/cfr.c b/src/mainboard/google/poppy/cfr.c
index 01793c080c..40bc75656f 100644
--- a/src/mainboard/google/poppy/cfr.c
+++ b/src/mainboard/google/poppy/cfr.c
@@ -6,15 +6,11 @@
 #include <intelblocks/cfr.h>
 #include <soc/cfr.h>
 
-static const struct sm_object ipu_camera = SM_DECLARE_ENUM({
+static const struct sm_object ipu_camera = SM_DECLARE_BOOL({
 	.opt_name	= "ipu_camera",
 	.ui_name	= "IPU Camera",
 	.ui_helptext	= "Enable or disable integrated camera devices",
 	.default_value	= true,
-	.values		= (const struct sm_enum_value[]) {
-		{ "Disabled",		0		},
-		{ "Enabled",		1		},
-		SM_ENUM_VALUE_END			},
 	#if !CONFIG(VARIANT_HAS_CAMERA_ACPI)
 	.flags		= CFR_OPTFLAG_SUPPRESS,
 	#endif

From daa32be457c4825a608d535355e64a8a8648fcb8 Mon Sep 17 00:00:00 2001
From: Angel Pons <th3fanbus@gmail.com>
Date: Wed, 18 Feb 2026 21:25:10 +0100
Subject: [PATCH 3414/3886] soc/intel/apollolake: Replace CFR enums with
 booleans

Boolean options are intended to represent generic "Enable"/"Disable"
options, but without enum options' extra bloat in the CFR structures.

Change-Id: I009413db0873c42a98cfc8bddb8613c66d496947
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91349
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/soc/intel/apollolake/include/soc/cfr.h | 24 ++++++----------------
 1 file changed, 6 insertions(+), 18 deletions(-)

diff --git a/src/soc/intel/apollolake/include/soc/cfr.h b/src/soc/intel/apollolake/include/soc/cfr.h
index df4a9200cc..7cef8127dc 100644
--- a/src/soc/intel/apollolake/include/soc/cfr.h
+++ b/src/soc/intel/apollolake/include/soc/cfr.h
@@ -11,39 +11,27 @@
 #include <soc/soc_chip.h>
 
 /* Legacy 8254 Timer */
-static const struct sm_object legacy_8254_timer = SM_DECLARE_ENUM({
+static const struct sm_object legacy_8254_timer = SM_DECLARE_BOOL({
 	.opt_name	= "legacy_8254_timer",
 	.ui_name	= "Legacy 8254 Timer",
 	.ui_helptext	= "Enable the legacy 8254 timer by disabling clock gating.",
-	.default_value	= 0,
-	.values		= (const struct sm_enum_value[]) {
-				{ "Disabled",		0	},
-				{ "Enabled",		1	},
-				SM_ENUM_VALUE_END		},
+	.default_value	= false,
 });
 
 /* S0ix Enable */
-static const struct sm_object s0ix_enable = SM_DECLARE_ENUM({
+static const struct sm_object s0ix_enable = SM_DECLARE_BOOL({
 	.opt_name	= "s0ix_enable",
 	.ui_name	= "Modern Standby (S0ix)",
 	.ui_helptext	= "Enabled: use Modern Standby / S0ix. Disabled: use APCI S3 sleep",
-	.default_value	= 1,
-	.values		= (const struct sm_enum_value[]) {
-				{ "Disabled",		0	},
-				{ "Enabled",		1	},
-				SM_ENUM_VALUE_END		},
+	.default_value	= true,
 });
 
 /* VT-d */
-static const struct sm_object vtd = SM_DECLARE_ENUM({
+static const struct sm_object vtd = SM_DECLARE_BOOL({
 	.opt_name	= "vtd",
 	.ui_name	= "VT-d",
 	.ui_helptext	= "Enable or disable Intel VT-d (virtualization)",
-	.default_value	= 1,
-	.values		= (const struct sm_enum_value[]) {
-				{ "Disabled",		0	},
-				{ "Enabled",		1	},
-				SM_ENUM_VALUE_END		},
+	.default_value	= true,
 });
 
 #endif /* _APOLLOLAKE_CFR_H_ */

From b935d5b05831d238967f9abd03f3d233682e5d41 Mon Sep 17 00:00:00 2001
From: Angel Pons <th3fanbus@gmail.com>
Date: Wed, 18 Feb 2026 21:27:24 +0100
Subject: [PATCH 3415/3886] soc/intel/cannonlake: Replace CFR enums with
 booleans

Boolean options are intended to represent generic "Enable"/"Disable"
options, but without enum options' extra bloat in the CFR structures.

Change-Id: I4be1ac4644c461fd64766e27383e479ff518a889
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91350
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/soc/intel/cannonlake/include/soc/cfr.h | 40 ++++++----------------
 1 file changed, 10 insertions(+), 30 deletions(-)

diff --git a/src/soc/intel/cannonlake/include/soc/cfr.h b/src/soc/intel/cannonlake/include/soc/cfr.h
index d177d2db83..80ddd18b2e 100644
--- a/src/soc/intel/cannonlake/include/soc/cfr.h
+++ b/src/soc/intel/cannonlake/include/soc/cfr.h
@@ -11,27 +11,19 @@
 #include <soc/soc_chip.h>
 
 /* FSP hyperthreading */
-static const struct sm_object hyper_threading = SM_DECLARE_ENUM({
+static const struct sm_object hyper_threading = SM_DECLARE_BOOL({
 	.opt_name	= "hyper_threading",
 	.ui_name	= "Hyper-Threading",
 	.ui_helptext	= "Enable or disable Hyper-Threading",
 	.default_value	= CONFIG(FSP_HYPERTHREADING),
-	.values		= (const struct sm_enum_value[]) {
-				{ "Disabled",		0	},
-				{ "Enabled",		1	},
-				SM_ENUM_VALUE_END		},
 });
 
 /* IGD Enabled */
-static const struct sm_object igd_enabled = SM_DECLARE_ENUM({
+static const struct sm_object igd_enabled = SM_DECLARE_BOOL({
 	.opt_name	= "igd_enabled",
 	.ui_name	= "Enable the Intel iGPU",
 	.ui_helptext	= "Enable or disable the Intel iGPU",
 	.default_value	= !CONFIG(SOC_INTEL_DISABLE_IGD),
-	.values		= (const struct sm_enum_value[]) {
-				{ "Disabled",		0	},
-				{ "Enabled",		1	},
-				SM_ENUM_VALUE_END		},
 });
 
 /* IGD Aperture Size */
@@ -45,7 +37,7 @@ static const struct sm_object igd_aperture = SM_DECLARE_ENUM({
 				{ "256 MB",	IGD_AP_SZ_256MB	},
 				{ "512 MB",	IGD_AP_SZ_512MB	},
 				SM_ENUM_VALUE_END		},
-}, WITH_DEP_VALUES(&igd_enabled, 1));
+}, WITH_DEP_VALUES(&igd_enabled, true));
 
 /* IGD DVMT pre-allocated memory */
 static const struct sm_object igd_dvmt = SM_DECLARE_ENUM({
@@ -59,42 +51,30 @@ static const struct sm_object igd_dvmt = SM_DECLARE_ENUM({
 				{ "96 MB",	IGD_SM_96MB	},
 				{ "128 MB",	IGD_SM_128MB	},
 				SM_ENUM_VALUE_END		},
-}, WITH_DEP_VALUES(&igd_enabled, 1));
+}, WITH_DEP_VALUES(&igd_enabled, true));
 
 /* Legacy 8254 Timer */
-static const struct sm_object legacy_8254_timer = SM_DECLARE_ENUM({
+static const struct sm_object legacy_8254_timer = SM_DECLARE_BOOL({
 	.opt_name	= "legacy_8254_timer",
 	.ui_name	= "Legacy 8254 Timer",
 	.ui_helptext	= "Enable the legacy 8254 timer by disabling clock gating.",
-	.default_value	= 0,
-	.values		= (const struct sm_enum_value[]) {
-				{ "Disabled",		0	},
-				{ "Enabled",		1	},
-				SM_ENUM_VALUE_END		},
+	.default_value	= false,
 });
 
 /* S0ix Enable */
-static const struct sm_object s0ix_enable = SM_DECLARE_ENUM({
+static const struct sm_object s0ix_enable = SM_DECLARE_BOOL({
 	.opt_name	= "s0ix_enable",
 	.ui_name	= "Modern Standby (S0ix)",
 	.ui_helptext	= "Enabled: use Modern Standby / S0ix. Disabled: use ACPI S3 sleep",
-	.default_value	= 1,
-	.values		= (const struct sm_enum_value[]) {
-				{ "Disabled",		0	},
-				{ "Enabled",		1	},
-				SM_ENUM_VALUE_END		},
+	.default_value	= true,
 });
 
 /* VT-d */
-static const struct sm_object vtd = SM_DECLARE_ENUM({
+static const struct sm_object vtd = SM_DECLARE_BOOL({
 	.opt_name	= "vtd",
 	.ui_name	= "VT-d",
 	.ui_helptext	= "Enable or disable Intel VT-d (virtualization)",
-	.default_value	= 1,
-	.values		= (const struct sm_enum_value[]) {
-				{ "Disabled",		0	},
-				{ "Enabled",		1	},
-				SM_ENUM_VALUE_END		},
+	.default_value	= true,
 });
 
 #endif /* CANNONLAKE_CFR_H */

From 1b0147f05b05d83ec54467beac7a4ba662385871 Mon Sep 17 00:00:00 2001
From: Angel Pons <th3fanbus@gmail.com>
Date: Wed, 18 Feb 2026 21:28:24 +0100
Subject: [PATCH 3416/3886] soc/intel/meteorlake: Replace CFR enums with
 booleans
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Boolean options are intended to represent generic "Enable"/"Disable"
options, but without enum options' extra bloat in the CFR structures.

Change-Id: I4e4f5c071f4299876e4ecd9defe7782c85eac3d8
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91351
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
---
 src/soc/intel/meteorlake/include/soc/cfr.h | 38 +++++-----------------
 1 file changed, 9 insertions(+), 29 deletions(-)

diff --git a/src/soc/intel/meteorlake/include/soc/cfr.h b/src/soc/intel/meteorlake/include/soc/cfr.h
index 5379f439c4..acc7fb6b7a 100644
--- a/src/soc/intel/meteorlake/include/soc/cfr.h
+++ b/src/soc/intel/meteorlake/include/soc/cfr.h
@@ -11,27 +11,19 @@
 #include <soc/soc_chip.h>
 
 /* FSP hyperthreading */
-static const struct sm_object hyper_threading = SM_DECLARE_ENUM({
+static const struct sm_object hyper_threading = SM_DECLARE_BOOL({
 	.opt_name	= "hyper_threading",
 	.ui_name	= "Hyper-Threading",
 	.ui_helptext	= "Enable or disable Hyper-Threading",
 	.default_value	= CONFIG(FSP_HYPERTHREADING),
-	.values		= (const struct sm_enum_value[]) {
-				{ "Disabled",		0	},
-				{ "Enabled",		1	},
-				SM_ENUM_VALUE_END		},
 });
 
 /* IGD Enabled */
-static const struct sm_object igd_enabled = SM_DECLARE_ENUM({
+static const struct sm_object igd_enabled = SM_DECLARE_BOOL({
 	.opt_name	= "igd_enabled",
 	.ui_name	= "Enable the Intel iGPU",
 	.ui_helptext	= "Enable or disable the Intel iGPU",
 	.default_value	= !CONFIG(SOC_INTEL_DISABLE_IGD),
-	.values		= (const struct sm_enum_value[]) {
-				{ "Disabled",		0	},
-				{ "Enabled",		1	},
-				SM_ENUM_VALUE_END		},
 });
 
 /* IGD DVMT pre-allocated memory */
@@ -47,42 +39,30 @@ static const struct sm_object igd_dvmt = SM_DECLARE_ENUM({
 				{ "128 MB",		IGD_SM_128MB	},
 				{ "160 MB",		IGD_SM_160MB	},
 				SM_ENUM_VALUE_END			},
-}, WITH_DEP_VALUES(&igd_enabled, 1));
+}, WITH_DEP_VALUES(&igd_enabled, true));
 
 /* Legacy 8254 Timer */
-static const struct sm_object legacy_8254_timer = SM_DECLARE_ENUM({
+static const struct sm_object legacy_8254_timer = SM_DECLARE_BOOL({
 	.opt_name	= "legacy_8254_timer",
 	.ui_name	= "Legacy 8254 Timer",
 	.ui_helptext	= "Enable the legacy 8254 timer by disabling clock gating.",
-	.default_value	= 0,
-	.values		= (const struct sm_enum_value[]) {
-				{ "Disabled",		0	},
-				{ "Enabled",		1	},
-				SM_ENUM_VALUE_END		},
+	.default_value	= false,
 });
 
 /* S0ix Enable */
-static const struct sm_object s0ix_enable = SM_DECLARE_ENUM({
+static const struct sm_object s0ix_enable = SM_DECLARE_BOOL({
 	.opt_name	= "s0ix_enable",
 	.ui_name	= "Modern Standby (S0ix)",
 	.ui_helptext	= "Enabled: use Modern Standby / S0ix. Disabled: use ACPI S3 sleep",
-	.default_value	= 1,
-	.values		= (const struct sm_enum_value[]) {
-				{ "Disabled",		0	},
-				{ "Enabled",		1	},
-				SM_ENUM_VALUE_END		},
+	.default_value	= true,
 });
 
 /* VT-d */
-static const struct sm_object vtd = SM_DECLARE_ENUM({
+static const struct sm_object vtd = SM_DECLARE_BOOL({
 	.opt_name	= "vtd",
 	.ui_name	= "VT-d",
 	.ui_helptext	= "Enable or disable Intel VT-d (virtualization)",
-	.default_value	= 1,
-	.values		= (const struct sm_enum_value[]) {
-				{ "Disabled",		0	},
-				{ "Enabled",		1	},
-				SM_ENUM_VALUE_END		},
+	.default_value	= true,
 });
 
 #endif /* _METEORLAKE_CFR_H_ */

From 47bc0a727c5718932395c62b56a2ab65d255e5fb Mon Sep 17 00:00:00 2001
From: Angel Pons <th3fanbus@gmail.com>
Date: Wed, 18 Feb 2026 21:32:15 +0100
Subject: [PATCH 3417/3886] soc/intel/jasperlake: Replace CFR enums with
 booleans
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Boolean options are intended to represent generic "Enable"/"Disable"
options, but without enum options' extra bloat in the CFR structures.

Change-Id: If9030e770a59d9de87f7b0f2112887db6126aacf
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91352
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
---
 src/soc/intel/jasperlake/include/soc/cfr.h | 34 ++++++----------------
 1 file changed, 9 insertions(+), 25 deletions(-)

diff --git a/src/soc/intel/jasperlake/include/soc/cfr.h b/src/soc/intel/jasperlake/include/soc/cfr.h
index c275324d65..e3ff9f87ef 100644
--- a/src/soc/intel/jasperlake/include/soc/cfr.h
+++ b/src/soc/intel/jasperlake/include/soc/cfr.h
@@ -11,15 +11,11 @@
 #include <soc/soc_chip.h>
 
 /* IGD Enabled */
-static const struct sm_object igd_enabled = SM_DECLARE_ENUM({
+static const struct sm_object igd_enabled = SM_DECLARE_BOOL({
 	.opt_name	= "igd_enabled",
 	.ui_name	= "Enable the Intel iGPU",
 	.ui_helptext	= "Enable or disable the Intel iGPU",
 	.default_value	= !CONFIG(SOC_INTEL_DISABLE_IGD),
-	.values		= (const struct sm_enum_value[]) {
-				{ "Disabled",		0	},
-				{ "Enabled",		1	},
-				SM_ENUM_VALUE_END		},
 });
 
 /* IGD Aperture Size */
@@ -33,7 +29,7 @@ static const struct sm_object igd_aperture = SM_DECLARE_ENUM({
 				{ " 256 MB",		IGD_AP_SZ_256MB		},
 				{ " 512 MB",		IGD_AP_SZ_512MB		},
 				SM_ENUM_VALUE_END				},
-}, WITH_DEP_VALUES(&igd_enabled, 1));
+}, WITH_DEP_VALUES(&igd_enabled, true));
 
 /* IGD DVMT pre-allocated memory */
 static const struct sm_object igd_dvmt = SM_DECLARE_ENUM({
@@ -49,42 +45,30 @@ static const struct sm_object igd_dvmt = SM_DECLARE_ENUM({
 				{ "128 MB",		IGD_SM_128MB	},
 				{ "160 MB",		IGD_SM_160MB	},
 				SM_ENUM_VALUE_END			},
-}, WITH_DEP_VALUES(&igd_enabled, 1));
+}, WITH_DEP_VALUES(&igd_enabled, true));
 
 /* Legacy 8254 Timer */
-static const struct sm_object legacy_8254_timer = SM_DECLARE_ENUM({
+static const struct sm_object legacy_8254_timer = SM_DECLARE_BOOL({
 	.opt_name	= "legacy_8254_timer",
 	.ui_name	= "Legacy 8254 Timer",
 	.ui_helptext	= "Enable the legacy 8254 timer by disabling clock gating.",
-	.default_value	= 0,
-	.values		= (const struct sm_enum_value[]) {
-				{ "Disabled",		0	},
-				{ "Enabled",		1	},
-				SM_ENUM_VALUE_END		},
+	.default_value	= false,
 });
 
 /* S0ix Enable */
-static const struct sm_object s0ix_enable = SM_DECLARE_ENUM({
+static const struct sm_object s0ix_enable = SM_DECLARE_BOOL({
 	.opt_name	= "s0ix_enable",
 	.ui_name	= "Modern Standby (S0ix)",
 	.ui_helptext	= "Enabled: use Modern Standby / S0ix. Disabled: use ACPI S3 sleep",
-	.default_value	= 1,
-	.values		= (const struct sm_enum_value[]) {
-				{ "Disabled",		0	},
-				{ "Enabled",		1	},
-				SM_ENUM_VALUE_END		},
+	.default_value	= true,
 });
 
 /* VT-d */
-static const struct sm_object vtd = SM_DECLARE_ENUM({
+static const struct sm_object vtd = SM_DECLARE_BOOL({
 	.opt_name	= "vtd",
 	.ui_name	= "VT-d",
 	.ui_helptext	= "Enable or disable Intel VT-d (virtualization)",
-	.default_value	= 1,
-	.values		= (const struct sm_enum_value[]) {
-				{ "Disabled",		0	},
-				{ "Enabled",		1	},
-				SM_ENUM_VALUE_END		},
+	.default_value	= true,
 });
 
 #endif /* _JASPERLAKE_CFR_H_ */

From 12f99ab06759ccc0f7ceae514143a361626307d7 Mon Sep 17 00:00:00 2001
From: Angel Pons <th3fanbus@gmail.com>
Date: Wed, 18 Feb 2026 21:35:45 +0100
Subject: [PATCH 3418/3886] soc/intel/alderlake: Replace CFR enums with
 booleans

Boolean options are intended to represent generic "Enable"/"Disable"
options, but without enum options' extra bloat in the CFR structures.

Change-Id: I7f3bb4f13a143e37869c22d66a514581a88deeb2
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91353
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/soc/intel/alderlake/include/soc/cfr.h | 40 ++++++-----------------
 1 file changed, 10 insertions(+), 30 deletions(-)

diff --git a/src/soc/intel/alderlake/include/soc/cfr.h b/src/soc/intel/alderlake/include/soc/cfr.h
index 1cacac618c..4834ba1bc3 100644
--- a/src/soc/intel/alderlake/include/soc/cfr.h
+++ b/src/soc/intel/alderlake/include/soc/cfr.h
@@ -11,27 +11,19 @@
 #include <soc/soc_chip.h>
 
 /* FSP hyperthreading */
-static const struct sm_object hyper_threading = SM_DECLARE_ENUM({
+static const struct sm_object hyper_threading = SM_DECLARE_BOOL({
 	.opt_name	= "hyper_threading",
 	.ui_name	= "Hyper-Threading",
 	.ui_helptext	= "Enable or disable Hyper-Threading",
 	.default_value	= CONFIG(FSP_HYPERTHREADING),
-	.values		= (const struct sm_enum_value[]) {
-				{ "Disabled",		0	},
-				{ "Enabled",		1	},
-				SM_ENUM_VALUE_END		},
 });
 
 /* IGD Enabled */
-static const struct sm_object igd_enabled = SM_DECLARE_ENUM({
+static const struct sm_object igd_enabled = SM_DECLARE_BOOL({
 	.opt_name	= "igd_enabled",
 	.ui_name	= "Enable the Intel iGPU",
 	.ui_helptext	= "Enable or disable the Intel iGPU",
 	.default_value	= !CONFIG(SOC_INTEL_DISABLE_IGD),
-	.values		= (const struct sm_enum_value[]) {
-				{ "Disabled",		0	},
-				{ "Enabled",		1	},
-				SM_ENUM_VALUE_END		},
 });
 
 /* IGD Aperture Size */
@@ -51,7 +43,7 @@ static const struct sm_object igd_aperture = SM_DECLARE_ENUM({
 				{ " 512 MB",		IGD_AP_SZ_512MB		},
 #endif
 				SM_ENUM_VALUE_END				},
-}, WITH_DEP_VALUES(&igd_enabled, 1));
+}, WITH_DEP_VALUES(&igd_enabled, true));
 
 /* IGD DVMT pre-allocated memory */
 static const struct sm_object igd_dvmt = SM_DECLARE_ENUM({
@@ -67,42 +59,30 @@ static const struct sm_object igd_dvmt = SM_DECLARE_ENUM({
 				{ "128 MB",		IGD_SM_128MB	},
 				{ "160 MB",		IGD_SM_160MB	},
 				SM_ENUM_VALUE_END			},
-}, WITH_DEP_VALUES(&igd_enabled, 1));
+}, WITH_DEP_VALUES(&igd_enabled, true));
 
 /* Legacy 8254 Timer */
-static const struct sm_object legacy_8254_timer = SM_DECLARE_ENUM({
+static const struct sm_object legacy_8254_timer = SM_DECLARE_BOOL({
 	.opt_name	= "legacy_8254_timer",
 	.ui_name	= "Legacy 8254 Timer",
 	.ui_helptext	= "Enable the legacy 8254 timer by disabling clock gating.",
-	.default_value	= 0,
-	.values		= (const struct sm_enum_value[]) {
-				{ "Disabled",		0	},
-				{ "Enabled",		1	},
-				SM_ENUM_VALUE_END		},
+	.default_value	= false,
 });
 
 /* S0ix Enable */
-static const struct sm_object s0ix_enable = SM_DECLARE_ENUM({
+static const struct sm_object s0ix_enable = SM_DECLARE_BOOL({
 	.opt_name	= "s0ix_enable",
 	.ui_name	= "Modern Standby (S0ix)",
 	.ui_helptext	= "Enabled: use Modern Standby / S0ix. Disabled: use ACPI S3 sleep",
-	.default_value	= 1,
-	.values		= (const struct sm_enum_value[]) {
-				{ "Disabled",		0	},
-				{ "Enabled",		1	},
-				SM_ENUM_VALUE_END		},
+	.default_value	= true,
 });
 
 /* VT-d */
-static const struct sm_object vtd = SM_DECLARE_ENUM({
+static const struct sm_object vtd = SM_DECLARE_BOOL({
 	.opt_name	= "vtd",
 	.ui_name	= "VT-d",
 	.ui_helptext	= "Enable or disable Intel VT-d (virtualization)",
-	.default_value	= 1,
-	.values		= (const struct sm_enum_value[]) {
-				{ "Disabled",		0	},
-				{ "Enabled",		1	},
-				SM_ENUM_VALUE_END		},
+	.default_value	= true,
 });
 
 #endif /* _ALDERLAKE_CFR_H_ */

From 666e66800c3f2f9c8d48f741e84b598d5c1427ec Mon Sep 17 00:00:00 2001
From: Angel Pons <th3fanbus@gmail.com>
Date: Wed, 18 Feb 2026 21:37:05 +0100
Subject: [PATCH 3419/3886] soc/intel/tigerlake: Replace CFR enums with
 booleans

Boolean options are intended to represent generic "Enable"/"Disable"
options, but without enum options' extra bloat in the CFR structures.

Change-Id: I3ac872881627179cb4ef344132bb601c78ca3a01
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91354
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
---
 src/soc/intel/tigerlake/include/soc/cfr.h | 40 ++++++-----------------
 1 file changed, 10 insertions(+), 30 deletions(-)

diff --git a/src/soc/intel/tigerlake/include/soc/cfr.h b/src/soc/intel/tigerlake/include/soc/cfr.h
index d424946c5a..a7f965ce8f 100644
--- a/src/soc/intel/tigerlake/include/soc/cfr.h
+++ b/src/soc/intel/tigerlake/include/soc/cfr.h
@@ -11,27 +11,19 @@
 #include <soc/soc_chip.h>
 
 /* FSP hyperthreading */
-static const struct sm_object hyper_threading = SM_DECLARE_ENUM({
+static const struct sm_object hyper_threading = SM_DECLARE_BOOL({
 	.opt_name	= "hyper_threading",
 	.ui_name	= "Hyper-Threading",
 	.ui_helptext	= "Enable or disable Hyper-Threading",
 	.default_value	= CONFIG(FSP_HYPERTHREADING),
-	.values		= (const struct sm_enum_value[]) {
-				{ "Disabled",		0	},
-				{ "Enabled",		1	},
-				SM_ENUM_VALUE_END		},
 });
 
 /* IGD Enabled */
-static const struct sm_object igd_enabled = SM_DECLARE_ENUM({
+static const struct sm_object igd_enabled = SM_DECLARE_BOOL({
 	.opt_name	= "igd_enabled",
 	.ui_name	= "Enable the Intel iGPU",
 	.ui_helptext	= "Enable or disable the Intel iGPU",
 	.default_value	= !CONFIG(SOC_INTEL_DISABLE_IGD),
-	.values		= (const struct sm_enum_value[]) {
-				{ "Disabled",		0	},
-				{ "Enabled",		1	},
-				SM_ENUM_VALUE_END		},
 });
 
 /* IGD Aperture Size */
@@ -51,7 +43,7 @@ static const struct sm_object igd_aperture = SM_DECLARE_ENUM({
 				{ " 512 MB",		IGD_AP_SZ_512MB		},
 #endif
 				SM_ENUM_VALUE_END				},
-}, WITH_DEP_VALUES(&igd_enabled, 1));
+}, WITH_DEP_VALUES(&igd_enabled, true));
 
 /* IGD DVMT pre-allocated memory */
 static const struct sm_object igd_dvmt = SM_DECLARE_ENUM({
@@ -67,42 +59,30 @@ static const struct sm_object igd_dvmt = SM_DECLARE_ENUM({
 				{ "128 MB",		IGD_SM_128MB	},
 				{ "160 MB",		IGD_SM_160MB	},
 				SM_ENUM_VALUE_END			},
-}, WITH_DEP_VALUES(&igd_enabled, 1));
+}, WITH_DEP_VALUES(&igd_enabled, true));
 
 /* Legacy 8254 Timer */
-static const struct sm_object legacy_8254_timer = SM_DECLARE_ENUM({
+static const struct sm_object legacy_8254_timer = SM_DECLARE_BOOL({
 	.opt_name	= "legacy_8254_timer",
 	.ui_name	= "Legacy 8254 Timer",
 	.ui_helptext	= "Enable the legacy 8254 timer by disabling clock gating.",
-	.default_value	= 0,
-	.values		= (const struct sm_enum_value[]) {
-				{ "Disabled",		0	},
-				{ "Enabled",		1	},
-				SM_ENUM_VALUE_END		},
+	.default_value	= false,
 });
 
 /* S0ix Enable */
-static const struct sm_object s0ix_enable = SM_DECLARE_ENUM({
+static const struct sm_object s0ix_enable = SM_DECLARE_BOOL({
 	.opt_name	= "s0ix_enable",
 	.ui_name	= "Modern Standby (S0ix)",
 	.ui_helptext	= "Enabled: use Modern Standby / S0ix. Disabled: use ACPI S3 sleep",
-	.default_value	= 1,
-	.values		= (const struct sm_enum_value[]) {
-				{ "Disabled",		0	},
-				{ "Enabled",		1	},
-				SM_ENUM_VALUE_END		},
+	.default_value	= true,
 });
 
 /* VT-d */
-static const struct sm_object vtd = SM_DECLARE_ENUM({
+static const struct sm_object vtd = SM_DECLARE_BOOL({
 	.opt_name	= "vtd",
 	.ui_name	= "VT-d",
 	.ui_helptext	= "Enable or disable Intel VT-d (virtualization)",
-	.default_value	= 1,
-	.values		= (const struct sm_enum_value[]) {
-				{ "Disabled",		0	},
-				{ "Enabled",		1	},
-				SM_ENUM_VALUE_END		},
+	.default_value	= true,
 });
 
 #endif /* _TIGERLAKE_CFR_H_ */

From 24870f54e09def50fcb7315b4017290f001e92d7 Mon Sep 17 00:00:00 2001
From: Angel Pons <th3fanbus@gmail.com>
Date: Wed, 18 Feb 2026 21:38:15 +0100
Subject: [PATCH 3420/3886] soc/intel/skylake: Replace CFR enums with booleans

Boolean options are intended to represent generic "Enable"/"Disable"
options, but without enum options' extra bloat in the CFR structures.

Change-Id: I6c4e44507fc371fc8b693b2289c58eb61ac84aa8
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91355
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/soc/intel/skylake/include/soc/cfr.h | 40 +++++++------------------
 1 file changed, 10 insertions(+), 30 deletions(-)

diff --git a/src/soc/intel/skylake/include/soc/cfr.h b/src/soc/intel/skylake/include/soc/cfr.h
index 355dea6b8f..f68f1d4599 100644
--- a/src/soc/intel/skylake/include/soc/cfr.h
+++ b/src/soc/intel/skylake/include/soc/cfr.h
@@ -11,27 +11,19 @@
 #include <soc/soc_chip.h>
 
 /* FSP hyperthreading */
-static const struct sm_object hyper_threading = SM_DECLARE_ENUM({
+static const struct sm_object hyper_threading = SM_DECLARE_BOOL({
 	.opt_name	= "hyper_threading",
 	.ui_name	= "Hyper-Threading",
 	.ui_helptext	= "Enable or disable Hyper-Threading",
 	.default_value	= CONFIG(FSP_HYPERTHREADING),
-	.values		= (const struct sm_enum_value[]) {
-				{ "Disabled",		0	},
-				{ "Enabled",		1	},
-				SM_ENUM_VALUE_END		},
 });
 
 /* IGD Enabled */
-static const struct sm_object igd_enabled = SM_DECLARE_ENUM({
+static const struct sm_object igd_enabled = SM_DECLARE_BOOL({
 	.opt_name	= "igd_enabled",
 	.ui_name	= "Enable the Intel iGPU",
 	.ui_helptext	= "Enable or disable the Intel iGPU",
 	.default_value	= !CONFIG(SOC_INTEL_DISABLE_IGD),
-	.values		= (const struct sm_enum_value[]) {
-				{ "Disabled",		0	},
-				{ "Enabled",		1	},
-				SM_ENUM_VALUE_END		},
 });
 
 /* IGD Aperture Size */
@@ -45,7 +37,7 @@ static const struct sm_object igd_aperture = SM_DECLARE_ENUM({
 				{ "256 MB",	IGD_AP_SZ_256MB	},
 				{ "512 MB",	IGD_AP_SZ_512MB	},
 				SM_ENUM_VALUE_END		},
-}, WITH_DEP_VALUES(&igd_enabled, 1));
+}, WITH_DEP_VALUES(&igd_enabled, true));
 
 /* IGD DVMT pre-allocated memory */
 static const struct sm_object igd_dvmt = SM_DECLARE_ENUM({
@@ -59,42 +51,30 @@ static const struct sm_object igd_dvmt = SM_DECLARE_ENUM({
 				{ "96 MB",	IGD_SM_96MB	},
 				{ "128 MB",	IGD_SM_128MB	},
 				SM_ENUM_VALUE_END		},
-}, WITH_DEP_VALUES(&igd_enabled, 1));
+}, WITH_DEP_VALUES(&igd_enabled, true));
 
 /* Legacy 8254 Timer */
-static const struct sm_object legacy_8254_timer = SM_DECLARE_ENUM({
+static const struct sm_object legacy_8254_timer = SM_DECLARE_BOOL({
 	.opt_name	= "legacy_8254_timer",
 	.ui_name	= "Legacy 8254 Timer",
 	.ui_helptext	= "Enable the legacy 8254 timer by disabling clock gating.",
-	.default_value	= 0,
-	.values		= (const struct sm_enum_value[]) {
-				{ "Disabled",		0	},
-				{ "Enabled",		1	},
-				SM_ENUM_VALUE_END		},
+	.default_value	= false,
 });
 
 /* S0ix Enable */
-static const struct sm_object s0ix_enable = SM_DECLARE_ENUM({
+static const struct sm_object s0ix_enable = SM_DECLARE_BOOL({
 	.opt_name	= "s0ix_enable",
 	.ui_name	= "Modern Standby (S0ix)",
 	.ui_helptext	= "Enabled: use Modern Standby / S0ix. Disabled: use ACPI S3 sleep",
-	.default_value	= 1,
-	.values		= (const struct sm_enum_value[]) {
-				{ "Disabled",		0	},
-				{ "Enabled",		1	},
-				SM_ENUM_VALUE_END		},
+	.default_value	= true,
 });
 
 /* VT-d */
-static const struct sm_object vtd = SM_DECLARE_ENUM({
+static const struct sm_object vtd = SM_DECLARE_BOOL({
 	.opt_name	= "vtd",
 	.ui_name	= "VT-d",
 	.ui_helptext	= "Enable or disable Intel VT-d (virtualization)",
-	.default_value	= 1,
-	.values		= (const struct sm_enum_value[]) {
-				{ "Disabled",		0	},
-				{ "Enabled",		1	},
-				SM_ENUM_VALUE_END		},
+	.default_value	= true,
 });
 
 #endif /* SKYLAKE_CFR_H */

From f691421dafc55faf46a44f8bba2cd7abd81ae96f Mon Sep 17 00:00:00 2001
From: Angel Pons <th3fanbus@gmail.com>
Date: Wed, 18 Feb 2026 21:40:11 +0100
Subject: [PATCH 3421/3886] soc/intel/common: Replace CFR enums with booleans
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Boolean options are intended to represent generic "Enable"/"Disable"
options, but without enum options' extra bloat in the CFR structures.

In this case, the callback function already treated the option as if
it were a boolean option, which likely only worked by chance.

Change-Id: Ic4b86c45e4837fcdb30cf594bb7e30400864e77e
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91356
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
---
 src/soc/intel/common/block/include/intelblocks/cfr.h | 12 ++++--------
 1 file changed, 4 insertions(+), 8 deletions(-)

diff --git a/src/soc/intel/common/block/include/intelblocks/cfr.h b/src/soc/intel/common/block/include/intelblocks/cfr.h
index 00785ae2eb..0185b0c028 100644
--- a/src/soc/intel/common/block/include/intelblocks/cfr.h
+++ b/src/soc/intel/common/block/include/intelblocks/cfr.h
@@ -103,7 +103,7 @@ static const struct sm_object pciexp_aspm = SM_DECLARE_ENUM({
 				{ "L0sL1",	ASPM_L0S_L1	},
 				{ "Auto",	ASPM_AUTO	},
 				SM_ENUM_VALUE_END		},
-}, WITH_DEP_VALUES(&pciexp_clk_pm, 1), WITH_CALLBACK(update_pcie_aspm));
+}, WITH_DEP_VALUES(&pciexp_clk_pm, true), WITH_CALLBACK(update_pcie_aspm));
 
 /* PCIe CPU RP ASPM */
 static const struct sm_object pciexp_aspm_cpu = SM_DECLARE_ENUM({
@@ -119,7 +119,7 @@ static const struct sm_object pciexp_aspm_cpu = SM_DECLARE_ENUM({
 				{ "L1",		ASPM_L1		},
 				{ "L0sL1",	ASPM_L0S_L1	},
 				SM_ENUM_VALUE_END		},
-}, WITH_DEP_VALUES(&pciexp_clk_pm, 1), WITH_CALLBACK(update_pcie_aspm_cpu));
+}, WITH_DEP_VALUES(&pciexp_clk_pm, true), WITH_CALLBACK(update_pcie_aspm_cpu));
 
 /* PCIe L1 Substates */
 static const struct sm_object pciexp_l1ss = SM_DECLARE_ENUM({
@@ -135,7 +135,7 @@ static const struct sm_object pciexp_l1ss = SM_DECLARE_ENUM({
 				{ "L1.1",	L1_SS_L1_1	},
 				{ "L1.2",	L1_SS_L1_2	},
 				SM_ENUM_VALUE_END		},
-}, WITH_DEP_VALUES(&pciexp_clk_pm, 1), WITH_CALLBACK(update_pcie_l1ss));
+}, WITH_DEP_VALUES(&pciexp_clk_pm, true), WITH_CALLBACK(update_pcie_l1ss));
 
 /* PCIe PCH Root Port Speed */
 static const struct sm_object pciexp_speed = SM_DECLARE_ENUM({
@@ -175,17 +175,13 @@ static void update_smm_bwp(struct sm_object *new)
 		new->sm_bool.flags |= CFR_OPTFLAG_SUPPRESS;
 }
 
-static const struct sm_object bios_lock = SM_DECLARE_ENUM({
+static const struct sm_object bios_lock = SM_DECLARE_BOOL({
 	.opt_name	= "bios_lock",
 	.ui_name	= "BIOS Lock",
 	.ui_helptext	= "Enable BIOS write protection in SMM. When enabled, the boot media"
 			  " (SPI flash) is only writable in System Management Mode, preventing"
 			  " unauthorized writes through the internal controller.",
 	.default_value	= CONFIG(BOOTMEDIA_SMM_BWP),
-	.values		= (const struct sm_enum_value[]) {
-				{ "Disabled",	false	},
-				{ "Enabled",	true	},
-				SM_ENUM_VALUE_END	},
 }, WITH_CALLBACK(update_smm_bwp));
 
 #endif /* SOC_INTEL_CMN_CFR_H */

From 78295974f83b1f37d5fc5dde7a74399023c55a2f Mon Sep 17 00:00:00 2001
From: Jeremy Compostella <jeremy.compostella@intel.com>
Date: Wed, 18 Feb 2026 21:21:46 -0800
Subject: [PATCH 3422/3886] soc/intel/common: Add feature directory for
 SoC-specific common code

Introduce a new directory structure src/soc/intel/common/feature/ for
sharing SoC-specific code across Intel SoC generations to reduce code
duplication.

Unlike the common block code (src/soc/intel/common/block/) which is
intended for reusable IP blocks, the feature code is for SoC-specific
functionality that is similar (but not identical) across multiple
generations. Platform-specific differences are handled through
configuration options or platform-specific macros.

This commit:
- Creates src/soc/intel/common/feature/ directory
- Adds feature/Kconfig defining SOC_INTEL_COMMON_FEATURE
- Adds feature/Makefile.mk to build subdirectories
- Updates src/soc/intel/common/Kconfig.common to source feature/Kconfig
- Updates src/soc/intel/common/Makefile.mk to include feature/ subdirs
- Documents the common code directory structure in
  Documentation/soc/intel/code_development_model/code_development_model.md

Change-Id: Idb842376a0a785a6439eeeb5a3a934d0bc575b09
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91360
Reviewed-by: Bora Guvendik <bora.guvendik@intel.corp-partner.google.com>
Reviewed-by: Jakub "Kuba" Czapiga <czapiga@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Pranava Y N <pranavayn@google.com>
---
 .../code_development_model.md                  | 10 +++++++---
 src/soc/intel/common/Kconfig.common            |  3 +++
 src/soc/intel/common/Makefile.mk               |  1 +
 src/soc/intel/common/feature/Kconfig           | 18 ++++++++++++++++++
 src/soc/intel/common/feature/Makefile.mk       |  6 ++++++
 5 files changed, 35 insertions(+), 3 deletions(-)
 create mode 100644 src/soc/intel/common/feature/Kconfig
 create mode 100644 src/soc/intel/common/feature/Makefile.mk

diff --git a/Documentation/soc/intel/code_development_model/code_development_model.md b/Documentation/soc/intel/code_development_model/code_development_model.md
index ad27bd498a..11674e8bdc 100644
--- a/Documentation/soc/intel/code_development_model/code_development_model.md
+++ b/Documentation/soc/intel/code_development_model/code_development_model.md
@@ -87,9 +87,13 @@ Code design after common code in coreboot will look as follows:
 
 [coreboot_common_code_design]: coreboot_common_code_design.png
 
-There will be still some duplicated files left in each SOC folder and we may
-copy across a SOC as a base but these files are subject to change as
-development continues.
+There will be still some duplicated files left in each SOC folder and we
+may copy across a SOC as a base but these files are subject to change as
+development continues. Some of those files, presenting strong similarities
+from generation to generation, can be consolidated into the common feature
+directory to reduce code duplication and improve
+maintenance. Platform-specific differences are handled through
+configuration options or platform-specific macros.
 
 ## Benefits
 
diff --git a/src/soc/intel/common/Kconfig.common b/src/soc/intel/common/Kconfig.common
index a1a2f39cfb..5e6ae6b19f 100644
--- a/src/soc/intel/common/Kconfig.common
+++ b/src/soc/intel/common/Kconfig.common
@@ -94,6 +94,9 @@ if SOC_INTEL_COMMON
 comment "Intel SoC Common Code for IP blocks"
 source "src/soc/intel/common/block/Kconfig"
 
+comment "Intel SoC Common Code for features"
+source "src/soc/intel/common/feature/Kconfig"
+
 comment "Intel SoC Common PCH Code"
 source "src/soc/intel/common/pch/Kconfig"
 
diff --git a/src/soc/intel/common/Makefile.mk b/src/soc/intel/common/Makefile.mk
index b273ed7c12..d1eacbfd17 100644
--- a/src/soc/intel/common/Makefile.mk
+++ b/src/soc/intel/common/Makefile.mk
@@ -3,6 +3,7 @@ ifeq ($(CONFIG_SOC_INTEL_COMMON),y)
 
 subdirs-y += basecode/
 subdirs-y += block/
+subdirs-y += feature/
 subdirs-y += pch/
 
 verstage-$(CONFIG_SOC_INTEL_COMMON_RESET) += reset.c
diff --git a/src/soc/intel/common/feature/Kconfig b/src/soc/intel/common/feature/Kconfig
new file mode 100644
index 0000000000..357ebf3643
--- /dev/null
+++ b/src/soc/intel/common/feature/Kconfig
@@ -0,0 +1,18 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
+config SOC_INTEL_COMMON_FEATURE
+	bool
+	help
+	  Intel SoC common feature code. This option enables sharing of
+	  SoC-specific code across Intel SoC generations to reduce code
+	  duplication. Unlike the common block code which is intended for
+	  reusable IP blocks, the feature code is for SoC-specific
+	  functionality that is similar across multiple generations but
+	  may have minor platform-specific differences handled through
+	  configuration options or platform-specific macros.
+
+if SOC_INTEL_COMMON_FEATURE
+
+source "src/soc/intel/common/feature/*/Kconfig"
+
+endif
diff --git a/src/soc/intel/common/feature/Makefile.mk b/src/soc/intel/common/feature/Makefile.mk
new file mode 100644
index 0000000000..62cccaad42
--- /dev/null
+++ b/src/soc/intel/common/feature/Makefile.mk
@@ -0,0 +1,6 @@
+## SPDX-License-Identifier: GPL-2.0-only
+ifeq ($(CONFIG_SOC_INTEL_COMMON_FEATURE),y)
+
+subdirs-y += ./*
+
+endif

From bb941824cad1787c977ef6b7c89b84b96cbbb3e5 Mon Sep 17 00:00:00 2001
From: Jeremy Compostella <jeremy.compostella@intel.com>
Date: Thu, 19 Feb 2026 08:22:52 -0800
Subject: [PATCH 3423/3886] soc/intel/common/feature/uart: Add common UART
 device list driver

This patch introduces a common UART device list implementation that
eliminates duplication across multiple Intel SoC platforms. Instead of
maintaining nearly identical uart.c files in each platform directory,
this common driver uses platform-specific macros to define UART device
function numbers.

The common implementation expects each platform to define the following
macros in their soc/pci_devs.h header:
- PCI_DEVFN_UART0
- PCI_DEVFN_UART1
- PCI_DEVFN_UART2

This approach maintains platform flexibility while reducing code
duplication and simplifying maintenance. The driver is compiled across
all stages (bootblock, verstage, romstage, postcar, ramstage, smm) to
support various UART usage scenarios.

Change-Id: Iba82a2fe24dd9ccf704e4a0fadc481b63662b94d
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91241
Reviewed-by: Kim, Wonkyu <wonkyu.kim@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Pranava Y N <pranavayn@google.com>
---
 src/soc/intel/common/feature/uart/Kconfig        |  9 +++++++++
 src/soc/intel/common/feature/uart/Makefile.mk    |  3 +++
 src/soc/intel/common/feature/uart/uart_devices.c | 12 ++++++++++++
 3 files changed, 24 insertions(+)
 create mode 100644 src/soc/intel/common/feature/uart/Kconfig
 create mode 100644 src/soc/intel/common/feature/uart/Makefile.mk
 create mode 100644 src/soc/intel/common/feature/uart/uart_devices.c

diff --git a/src/soc/intel/common/feature/uart/Kconfig b/src/soc/intel/common/feature/uart/Kconfig
new file mode 100644
index 0000000000..73429af335
--- /dev/null
+++ b/src/soc/intel/common/feature/uart/Kconfig
@@ -0,0 +1,9 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
+config SOC_INTEL_COMMON_FEATURE_UART_DEVICES
+	bool
+	help
+	  Include common UART device list support. This option eliminates
+	  per-platform duplication of uart.c files by providing a common
+	  implementation. Platforms must define PCI_UART_DEVFN* macro in
+	  their soc/pci_devs.h header.
diff --git a/src/soc/intel/common/feature/uart/Makefile.mk b/src/soc/intel/common/feature/uart/Makefile.mk
new file mode 100644
index 0000000000..dfc36965ba
--- /dev/null
+++ b/src/soc/intel/common/feature/uart/Makefile.mk
@@ -0,0 +1,3 @@
+## SPDX-License-Identifier: GPL-2.0-only
+all-$(CONFIG_SOC_INTEL_COMMON_FEATURE_UART_DEVICES) += uart_devices.c
+smm-$(CONFIG_SOC_INTEL_COMMON_FEATURE_UART_DEVICES) += uart_devices.c
diff --git a/src/soc/intel/common/feature/uart/uart_devices.c b/src/soc/intel/common/feature/uart/uart_devices.c
new file mode 100644
index 0000000000..9f549c5ae8
--- /dev/null
+++ b/src/soc/intel/common/feature/uart/uart_devices.c
@@ -0,0 +1,12 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <commonlib/helpers.h>
+#include <soc/pci_devs.h>
+
+const unsigned int uart_devices[] = {
+	PCI_DEVFN_UART0,
+	PCI_DEVFN_UART1,
+	PCI_DEVFN_UART2,
+};
+
+const int uart_devices_size = ARRAY_SIZE(uart_devices);

From 3337e56b50505166fc82bcc28de99a9e8fc4b38d Mon Sep 17 00:00:00 2001
From: Jeremy Compostella <jeremy.compostella@intel.com>
Date: Wed, 18 Feb 2026 21:25:18 -0800
Subject: [PATCH 3424/3886] soc/intel/alderlake: Use common UART device list
 driver

Remove platform-specific uart.c and switch to the common UART device
list driver. This eliminates 18 lines of duplicate code.

The Alder Lake uart.c simply defined uart_devices[] array with
PCH_DEVFN_UART* macros. The common driver now handles this using the
PCI_UART_DEVFNn macro defined in pci_devs.h.

This commit:
- Adds PCI_DEVFN_UART* aliases pointing to PCH_DEVFN_UART* for naming
  consistency with common code
- Selects SOC_INTEL_COMMON_FEATURE and
  SOC_INTEL_COMMON_FEATURE_UART_DEVICES in Kconfig
- Removes uart.c and updates Makefile.mk

Change-Id: Iafd4881c44dd9ccf7e204378bbafafbd1c884db0
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91242
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/soc/intel/alderlake/Kconfig                |  2 ++
 src/soc/intel/alderlake/Makefile.mk            |  2 --
 src/soc/intel/alderlake/include/soc/pci_devs.h |  5 +++++
 src/soc/intel/alderlake/uart.c                 | 18 ------------------
 4 files changed, 7 insertions(+), 20 deletions(-)
 delete mode 100644 src/soc/intel/alderlake/uart.c

diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig
index 34c9baf544..9034f5d252 100644
--- a/src/soc/intel/alderlake/Kconfig
+++ b/src/soc/intel/alderlake/Kconfig
@@ -84,6 +84,8 @@ config SOC_INTEL_ALDERLAKE
 	select SOC_INTEL_COMMON_BLOCK_VTD
 	select SOC_INTEL_COMMON_BLOCK_XHCI
 	select SOC_INTEL_COMMON_BLOCK_XHCI_ELOG
+	select SOC_INTEL_COMMON_FEATURE
+	select SOC_INTEL_COMMON_FEATURE_UART_DEVICES
 	select SOC_INTEL_COMMON_FSP_RESET
 	select SOC_INTEL_COMMON_PCH_CLIENT
 	select SOC_INTEL_COMMON_RESET
diff --git a/src/soc/intel/alderlake/Makefile.mk b/src/soc/intel/alderlake/Makefile.mk
index 6262cf2999..eafba3cbd6 100644
--- a/src/soc/intel/alderlake/Makefile.mk
+++ b/src/soc/intel/alderlake/Makefile.mk
@@ -9,7 +9,6 @@ all-y += gspi.c
 all-y += i2c.c
 all-y += pmutil.c
 all-y += spi.c
-all-y += uart.c
 
 bootblock-y += bootblock/bootblock.c
 bootblock-y += bootblock/pch.c
@@ -50,7 +49,6 @@ smm-y += elog.c
 smm-y += p2sb.c
 smm-y += pmutil.c
 smm-y += smihandler.c
-smm-y += uart.c
 smm-y += xhci.c
 
 ifeq ($(CONFIG_SOC_INTEL_ALDERLAKE_PCH_S),y)
diff --git a/src/soc/intel/alderlake/include/soc/pci_devs.h b/src/soc/intel/alderlake/include/soc/pci_devs.h
index 010a2101ea..9876397219 100644
--- a/src/soc/intel/alderlake/include/soc/pci_devs.h
+++ b/src/soc/intel/alderlake/include/soc/pci_devs.h
@@ -278,4 +278,9 @@
 #define  PCH_DEV_GBE		_PCH_DEV(ESPI, 6)
 #define  PCH_DEV_TRACEHUB	_PCH_DEV(ESPI, 7)
 
+/* for common code */
+#define PCI_DEVFN_UART0		PCH_DEVFN_UART0
+#define PCI_DEVFN_UART1		PCH_DEVFN_UART1
+#define PCI_DEVFN_UART2		PCH_DEVFN_UART2
+
 #endif
diff --git a/src/soc/intel/alderlake/uart.c b/src/soc/intel/alderlake/uart.c
deleted file mode 100644
index 2344a6a717..0000000000
--- a/src/soc/intel/alderlake/uart.c
+++ /dev/null
@@ -1,18 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-/*
- * This file is created based on Intel Alder Lake Processor PCH Datasheet
- * Document number: 621483
- * Chapter number: 9
- */
-
-#include <commonlib/helpers.h>
-#include <soc/pci_devs.h>
-
-const unsigned int uart_devices[] = {
-	PCH_DEVFN_UART0,
-	PCH_DEVFN_UART1,
-	PCH_DEVFN_UART2,
-};
-
-const int uart_devices_size = ARRAY_SIZE(uart_devices);

From 326e33b82d3bdb182da334e60b044574d5edb472 Mon Sep 17 00:00:00 2001
From: Jeremy Compostella <jeremy.compostella@intel.com>
Date: Thu, 19 Feb 2026 07:43:35 -0800
Subject: [PATCH 3425/3886] soc/intel/pantherlake: Use common UART device list
 driver

Remove platform-specific uart.c and switch to the common UART device
list driver. This eliminates duplicate code.

The pantherlake uart.c simply defined uart_devices[] array. The common
driver now handles this using the PCI_UART_DEVFN macro defined in
pci_devs.h.

This commit:
- Selects SOC_INTEL_COMMON_FEATURE and
  SOC_INTEL_COMMON_FEATURE_UART_DEVICES in Kconfig
- Removes uart.c and updates Makefile.mk

Change-Id: I59443ece21bc45c8b6986fdd2bc24dd9ccf7a543
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91244
Reviewed-by: Kim, Wonkyu <wonkyu.kim@intel.com>
Reviewed-by: Pranava Y N <pranavayn@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/soc/intel/pantherlake/Kconfig     |  2 ++
 src/soc/intel/pantherlake/Makefile.mk |  2 --
 src/soc/intel/pantherlake/uart.c      | 12 ------------
 3 files changed, 2 insertions(+), 14 deletions(-)
 delete mode 100644 src/soc/intel/pantherlake/uart.c

diff --git a/src/soc/intel/pantherlake/Kconfig b/src/soc/intel/pantherlake/Kconfig
index 92397037af..a67b2410ad 100644
--- a/src/soc/intel/pantherlake/Kconfig
+++ b/src/soc/intel/pantherlake/Kconfig
@@ -96,6 +96,8 @@ config SOC_INTEL_PANTHERLAKE_BASE
 	select SOC_INTEL_COMMON_BLOCK_TRACEHUB
 	select SOC_INTEL_COMMON_BLOCK_XHCI
 	select SOC_INTEL_COMMON_BLOCK_XHCI_ELOG
+	select SOC_INTEL_COMMON_FEATURE
+	select SOC_INTEL_COMMON_FEATURE_UART_DEVICES
 	select SOC_INTEL_COMMON_FSP_RESET
 	select SOC_INTEL_COMMON_PCH_CLIENT
 	select SOC_INTEL_COMMON_RESET
diff --git a/src/soc/intel/pantherlake/Makefile.mk b/src/soc/intel/pantherlake/Makefile.mk
index ab118c5055..fd9760a965 100644
--- a/src/soc/intel/pantherlake/Makefile.mk
+++ b/src/soc/intel/pantherlake/Makefile.mk
@@ -11,7 +11,6 @@ all-y += gspi.c
 all-y += i2c.c
 all-y += pmutil.c
 all-y += spi.c
-all-y += uart.c
 all-y += gpio.c
 
 bootblock-y += bootblock/bootblock.c
@@ -53,7 +52,6 @@ smm-y += gpio.c
 smm-y += p2sb.c
 smm-y += pmutil.c
 smm-y += smihandler.c
-smm-y += uart.c
 smm-y += xhci.c
 CPPFLAGS_common += -I$(src)/soc/intel/pantherlake
 CPPFLAGS_common += -I$(src)/soc/intel/pantherlake/include
diff --git a/src/soc/intel/pantherlake/uart.c b/src/soc/intel/pantherlake/uart.c
deleted file mode 100644
index 9f549c5ae8..0000000000
--- a/src/soc/intel/pantherlake/uart.c
+++ /dev/null
@@ -1,12 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <commonlib/helpers.h>
-#include <soc/pci_devs.h>
-
-const unsigned int uart_devices[] = {
-	PCI_DEVFN_UART0,
-	PCI_DEVFN_UART1,
-	PCI_DEVFN_UART2,
-};
-
-const int uart_devices_size = ARRAY_SIZE(uart_devices);

From f01e11ac5cf15896b7d60e465bee7cf33571190f Mon Sep 17 00:00:00 2001
From: Sowmya V <v.sowmya@intel.com>
Date: Wed, 14 Jan 2026 11:54:47 +0530
Subject: [PATCH 3426/3886] vc/intel/fsp/fsp2_0/wildcatlake: Update WCL FSP
 headers to version WCL.3515.03

Update Wildcatlake FSP headers to align with the FSP version WCL.3515.03.

BUG=b:475358197
TEST=Build the ocelot CB with the latest header changes.

Change-Id: I1232523e662d91cf43e7ed6bcc4fbefeaf8447e9
Signed-off-by: Sowmya V <v.sowmya@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90753
Reviewed-by: Pranava Y N <pranavayn@google.com>
Reviewed-by: Avi Uday <aviuday@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 .../intel/fsp/fsp2_0/wildcatlake/FspUpd.h     |    2 +-
 .../intel/fsp/fsp2_0/wildcatlake/FspmUpd.h    | 1837 +++++++++++++++--
 .../intel/fsp/fsp2_0/wildcatlake/FspsUpd.h    | 1683 ++++++++++++++-
 .../intel/fsp/fsp2_0/wildcatlake/MemInfoHob.h |    7 +-
 4 files changed, 3259 insertions(+), 270 deletions(-)

diff --git a/src/vendorcode/intel/fsp/fsp2_0/wildcatlake/FspUpd.h b/src/vendorcode/intel/fsp/fsp2_0/wildcatlake/FspUpd.h
index 9661285ef3..33ae66b1e5 100644
--- a/src/vendorcode/intel/fsp/fsp2_0/wildcatlake/FspUpd.h
+++ b/src/vendorcode/intel/fsp/fsp2_0/wildcatlake/FspUpd.h
@@ -1,6 +1,6 @@
 /** @file
 
-Copyright (c) 2024, Intel Corporation. All rights reserved.<BR>
+Copyright (c) 2026, Intel Corporation. All rights reserved.<BR>
 
 Redistribution and use in source and binary forms, with or without modification,
 are permitted provided that the following conditions are met:
diff --git a/src/vendorcode/intel/fsp/fsp2_0/wildcatlake/FspmUpd.h b/src/vendorcode/intel/fsp/fsp2_0/wildcatlake/FspmUpd.h
index 2c5c2af641..50e13411f6 100644
--- a/src/vendorcode/intel/fsp/fsp2_0/wildcatlake/FspmUpd.h
+++ b/src/vendorcode/intel/fsp/fsp2_0/wildcatlake/FspmUpd.h
@@ -93,9 +93,11 @@ typedef struct {
 **/
   UINT32                      SerialIoUartDebugCtsPinMux;
 
-/** Offset 0x0074 - Reserved
+/** Offset 0x0074 - SerialIo Uart PowerGating
+  Select SerialIo Uart Powergating mode
+  0:Disabled, 1:Enabled, 2:Auto
 **/
-  UINT8                       Reserved1;
+  UINT8                       SerialIoUartPowerGating;
 
 /** Offset 0x0075 - DCI Enable
   Determine if to enable DCI debug from host
@@ -110,9 +112,28 @@ typedef struct {
 **/
   UINT8                       DciDbcMode;
 
-/** Offset 0x0077 - Reserved
+/** Offset 0x0077 - DCI Clock Enable
+  Enable/Disable DCI clock in lowest power state
+  $EN_DIS
 **/
-  UINT8                       Reserved2[3];
+  UINT8                       DciClkEnable;
+
+/** Offset 0x0078 - Keep Early Trace
+  Trace is activated by default. When enable, keep early trace data and keep tracing,
+  may block s0ix.\n
+  When disabled will abandon trace data and stop tracing which allows enter s0ix\n
+  \n
+  noted:enable this option will not enable TraceHub; When probe is connected, keep
+  early trace will then be configured by tool, this option will not take effect.
+  $EN_DIS
+**/
+  UINT8                       KeepEarlyTrace;
+
+/** Offset 0x0079 - Enable/Disable MemoryOverlap check
+  Enable(Default): Enable MemoryOverlap check, Disable: Disable MemoryOverlap check
+  $EN_DIS
+**/
+  UINT8                       MemMapOverlapCheckSupport;
 
 /** Offset 0x007A - Memory Test on Warm Boot
   Run Base Memory Test on Warm Boot
@@ -122,7 +143,7 @@ typedef struct {
 
 /** Offset 0x007B - Reserved
 **/
-  UINT8                       Reserved3[5];
+  UINT8                       Reserved1[5];
 
 /** Offset 0x0080 - Platform Reserved Memory Size
   The minimum platform memory size required to pass control into DXE
@@ -137,7 +158,7 @@ typedef struct {
 
 /** Offset 0x008A - Reserved
 **/
-  UINT8                       Reserved4[6];
+  UINT8                       Reserved2[6];
 
 /** Offset 0x0090 - Memory SPD Pointer Controller 0 Channel 0 Dimm 0
   Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00
@@ -316,9 +337,19 @@ typedef struct {
 **/
   UINT8                       LowerBasicMemTestSize;
 
-/** Offset 0x01AD - Reserved
+/** Offset 0x01AD - EccGranularity32BEn
+  Reduce BasicMemTest size. 0: Disabled (default), regular BasicMemTest. 1: Enabled,
+  shorter BasicMemTest (faster boot)
+  $EN_DIS
 **/
-  UINT8                       Reserved5[2];
+  UINT8                       EccGranularity32BEn;
+
+/** Offset 0x01AE - EccCorrectionMode
+  Reduce BasicMemTest size. 0: Disabled (default), regular BasicMemTest. 1: Enabled,
+  shorter BasicMemTest (faster boot)
+  $EN_DIS
+**/
+  UINT8                       EccCorrectionMode;
 
 /** Offset 0x01AF - CaVrefHigh
   DDR5 CA Sweep High Vref Value for DDR5 OC
@@ -350,9 +381,13 @@ typedef struct {
 **/
   UINT8                       DFETap2StepSize;
 
-/** Offset 0x01B5 - Reserved
+/** Offset 0x01B5 - IbeccEccInjControl
+  IBECC Error Injection Control
+  0: No Error Injection, 1:Inject Correctable Error Address match, 3:Inject Correctable
+  Error on insertion counter, 5: Inject Uncorrectable Error Address match, 7:Inject
+  Uncorrectable Error on insertion counter
 **/
-  UINT8                       Reserved6;
+  UINT8                       IbeccEccInjControl;
 
 /** Offset 0x01B6 - VDD2 override
   VDD2 override for DDR5 OC; 0 - Auto
@@ -473,9 +508,17 @@ typedef struct {
 **/
   UINT16                      tCCD_L_WR;
 
-/** Offset 0x01E2 - Reserved
+/** Offset 0x01E2 - Periodic COMP
+  Enable/disable Periodic Compensation
+  $EN_DIS
 **/
-  UINT8                       Reserved7[2];
+  UINT8                       EnPeriodicComp;
+
+/** Offset 0x01E3 - LPMode4 Support
+  LPMode4 Options
+  0: Disable, 1:Enable, 2:Dynamic Threshold 2, 3:Dynamic Threshold 3
+**/
+  UINT8                       LpMode4;
 
 /** Offset 0x01E4 - LPMode Support
   Bit[0]: Enable Lpmode0p5 (Idle_enable), Bit[1]: Enable Lpmode2 (Powerdown_enable),
@@ -483,9 +526,17 @@ typedef struct {
 **/
   UINT8                       LpMode;
 
-/** Offset 0x01E5 - Reserved
+/** Offset 0x01E5 - Opportunistic Read
+  Enables/Disable Opportunistic Read (Def= Enable)
+  $EN_DIS
 **/
-  UINT8                       Reserved8[2];
+  UINT8                       OpportunisticRead;
+
+/** Offset 0x01E6 - Cycle Bypass Support
+  Enables/Disable Cycle Bypass Support(Def=Disable)
+  $EN_DIS
+**/
+  UINT8                       Disable2CycleBypass;
 
 /** Offset 0x01E7 - MRC OCSafeMode
   OverClocking Safe Mode for tCL
@@ -493,9 +544,13 @@ typedef struct {
 **/
   UINT8                       OCSafeMode;
 
-/** Offset 0x01E8 - Reserved
+/** Offset 0x01E8 - DQ Vref Ctrl Offset
+  Offset to be applied to DDRDATA7CH1_CR_DDRCRVREFADJUST1.Ch0VrefCtl
+  0xF4:-12,0xF5:-11, 0xF6:-10, 0xF7:-9, 0xF8:-8, 0xF9:-7, 0xFA:-6, 0xFB:-5, 0xFC:-4,
+  0xFD:-3, 0xFE:-2, 0xFF:-1, 0:0, 1:+1, 2:+2, 3:+3, 4:+4, 5:+5, 6:+6, 7:+7, 8:+8,
+  9:+9, 10:+10, 11:+11, 12:+12
 **/
-  UINT8                       Reserved9;
+  UINT8                       VrefCtlOffset;
 
 /** Offset 0x01E9 - Dqs Pins Interleaved Setting
   Indicates DqPinsInterleaved setting: board-dependent
@@ -536,9 +591,10 @@ typedef struct {
 **/
   UINT8                       ProbelessTrace;
 
-/** Offset 0x01EF - Reserved
+/** Offset 0x01EF - IbeccEccInjCount
+  Number of memory transactions between ECC error injection
 **/
-  UINT8                       Reserved10;
+  UINT8                       IbeccEccInjCount;
 
 /** Offset 0x01F0 - DDR Frequency Limit
   Maximum Memory Frequency Selections in Mhz. Options are 1067, 1333, 1600, 1867,
@@ -676,9 +732,11 @@ typedef struct {
 **/
   UINT8                       TXDQSDCC;
 
-/** Offset 0x0213 - Reserved
+/** Offset 0x0213 - Rx DQS Duty Cycle Correction
+  Enables/Disable Rx DQS Duty Cycle Correction
+  $EN_DIS
 **/
-  UINT8                       Reserved11;
+  UINT8                       RXDQSDCC;
 
 /** Offset 0x0214 - Ch Hash Override
   Select if Channel Hash setting values will be taken from input parameters or automatically
@@ -687,9 +745,17 @@ typedef struct {
 **/
   UINT8                       ChHashOverride;
 
-/** Offset 0x0215 - Reserved
+/** Offset 0x0215 - Voltage Readout
+  Enables/Disable Voltage Readout for VCCClk and PBias
+  $EN_DIS
 **/
-  UINT8                       Reserved12[2];
+  UINT8                       VoltageReadout;
+
+/** Offset 0x0216 - DQS Rise/Fall
+  Enables/Disable DQS Rise/Fall
+  $EN_DIS
+**/
+  UINT8                       DQSRF;
 
 /** Offset 0x0217 - DQS Rise/Fall
   Enables/Disable DQS Rise/Fall
@@ -697,9 +763,17 @@ typedef struct {
 **/
   UINT8                       RDDQSODTT;
 
-/** Offset 0x0218 - Reserved
+/** Offset 0x0218 - PreTraining
+  Enables/Disable PreTraining
+  $EN_DIS
 **/
-  UINT8                       Reserved13[2];
+  UINT8                       PRETRAIN;
+
+/** Offset 0x0219 - DUNIT Configuration
+  Enables/Disable Dunit Configuration
+  $EN_DIS
+**/
+  UINT8                       DUNITC;
 
 /** Offset 0x021A - Functional Duty Cycle Correction for DDR5 CLK
   Enable/Disable Functional Duty Cycle Correction for DDR5 CLK
@@ -729,9 +803,11 @@ typedef struct {
 **/
   UINT8                       DQDQSSWZ;
 
-/** Offset 0x021F - Reserved
+/** Offset 0x021F - LP5 Dca Training
+  Enable/Disable LP5 Dca Training
+  $EN_DIS
 **/
-  UINT8                       Reserved14;
+  UINT8                       DCCLP5READDCA;
 
 /** Offset 0x0220 - Functional Duty Cycle Correction for Data DQ
   Enable/Disable Functional Duty Cycle Correction for Data DQ
@@ -739,9 +815,39 @@ typedef struct {
 **/
   UINT8                       FUNCDCCDQ;
 
-/** Offset 0x0221 - Reserved
+/** Offset 0x0221 - SubCh Hash Override
+  Select if SubChannel Hash setting values will be taken from input parameters or
+  automatically taken from POR values depending on DRAM type detected. NOTE: ONLY
+  if Memory interleaved Mode
+  $EN_DIS
 **/
-  UINT8                       Reserved15[5];
+  UINT8                       SubChHashOverride;
+
+/** Offset 0x0222 - DDR5 Auto Precharge Enable
+  Auto Precharge Enable for DDR5: <b>O=Auto</b>, 1=Disable, 2=Enable
+  $EN_DIS
+**/
+  UINT8                       Ddr5AutoPrechargeEnable;
+
+/** Offset 0x0223 - Lp5 SplitACT Enable
+  SplitACT enable for LP5
+  0:Auto, 1:Disable, 2:Enable
+**/
+  UINT8                       Lp5SplitACTEnable;
+
+/** Offset 0x0224 - CCC Half Frequency
+  CCC Half Frequency (CccGear4) Mode: 0 = Auto (Default), 1 = Disable, 2 = GroupGv0
+  (SaGv0 only), 3 = GroupGv1 (Up to SaGv1), 4 = GroupGv2 (Up to SaGv2), 5 = GroupGv3
+  (Up to SaGv3)
+  0: Auto, 1: Disable, 2: GroupGv0, 3: GroupGv1, 4: GroupGv2, 5: GroupGv3
+**/
+  UINT8                       CccHalfFrequency;
+
+/** Offset 0x0225 - DIMM Non-Target ODT Training
+  Enables/Disable DIMM Non-Target ODT Training
+  $EN_DIS
+**/
+  UINT8                       DIMMNTODT;
 
 /** Offset 0x0226 - Unmatched Rx Calibration
   Enable/Disable Rx Unmatched Calibration
@@ -749,9 +855,60 @@ typedef struct {
 **/
   UINT8                       RXUNMATCHEDCAL;
 
-/** Offset 0x0227 - Reserved
+/** Offset 0x0227 - Hard Post Package Repair
+  Deprecated
+  $EN_DIS
 **/
-  UINT8                       Reserved16[10];
+  UINT8                       PPR;
+
+/** Offset 0x0228 - PPR Test Type
+  Deprecated
+**/
+  UINT8                       PprTestType;
+
+/** Offset 0x0229 - PPR Run Once
+  When Eanble, PPR will run only once and then is disabled at next training cycle
+  $EN_DIS
+**/
+  UINT8                       PprRunOnce;
+
+/** Offset 0x022A - PPR Run During Fastboot
+  Deprecated
+  $EN_DIS
+**/
+  UINT8                       PprRunAtFastboot;
+
+/** Offset 0x022B - PPR Repair Type
+  PPR Repair Type: 0:Do not Repair (Default), 1:Soft Repair, 2:Hard Repair
+  0:Do not Repair (Default), 1:Soft Repair, 2:Hard Repair
+**/
+  UINT8                       PprRepairType;
+
+/** Offset 0x022C - PPR Error Injection
+  When Eanble, PPR will inject bad rows during testing
+  $EN_DIS
+**/
+  UINT8                       PprErrorInjection;
+
+/** Offset 0x022D - PPR Repair Controller
+  Deprecated
+**/
+  UINT8                       PprRepairController;
+
+/** Offset 0x022E - PPR Repair Channel
+  Deprecated
+**/
+  UINT8                       PprRepairChannel;
+
+/** Offset 0x022F - PPR Repair Dimm
+  Deprecated
+**/
+  UINT8                       PprRepairDimm;
+
+/** Offset 0x0230 - PPR Repair Rank
+  Deprecated
+**/
+  UINT8                       PprRepairRank;
 
 /** Offset 0x0231 - Memory Slice Hash LSB Bit
   Memory Slice (Controller) Hash LSB bit. Valid values are 0..7 for BITS 6..13; used
@@ -766,9 +923,25 @@ typedef struct {
 **/
   UINT16                      MsHashMask;
 
-/** Offset 0x0234 - Reserved
+/** Offset 0x0234 - PPR Repair Row
+  Deprecated
 **/
-  UINT8                      Reserved17[13];
+  UINT32                      PprRepairRow;
+
+/** Offset 0x0238 - PPR Repair Physical Address Low
+  Deprecated
+**/
+  UINT32                      PprRepairPhysicalAddrLow;
+
+/** Offset 0x023C - PPR Repair Physical Address High
+  Deprecated
+**/
+  UINT32                      PprRepairPhysicalAddrHigh;
+
+/** Offset 0x0240 - PPR Repair BankGroup
+  Deprecated
+**/
+  UINT8                       PprRepairBankGroup;
 
 /** Offset 0x0241 - LVR Auto Trim
   Enable/disable LVR Auto Trim
@@ -788,9 +961,23 @@ typedef struct {
 **/
   UINT8                       WRTRETRAIN;
 
-/** Offset 0x0244 - Reserved
+/** Offset 0x0244 - DCC Phase Clk Calibration
+  Enable/disable DCC Phase Clk Calibration
+  $EN_DIS
 **/
-  UINT8                       Reserved18[3];
+  UINT8                       PHASECLKCAL;
+
+/** Offset 0x0245 - DCC Tline Clk Calibration
+  Enable/disable DCC Tline Clk Calibration
+  $EN_DIS
+**/
+  UINT8                       TLINECLKCAL;
+
+/** Offset 0x0246 - DCC Tline Serializer Calibration
+  Enable/disable DCC PI Serializer Calibratio
+  $EN_DIS
+**/
+  UINT8                       DCCPISERIALCAL;
 
 /** Offset 0x0247 - RDDQODTT
   Enable/disable Read DQ ODT Training
@@ -1000,9 +1187,11 @@ typedef struct {
 **/
   UINT8                       TAT;
 
-/** Offset 0x026A - Reserved
+/** Offset 0x026A - Rmt Even Odd
+  Enables/Disable Rmt Even Odd
+  $EN_DIS
 **/
-  UINT8                       Reserved19;
+  UINT8                       RMTEVENODD;
 
 /** Offset 0x026B - DIMM SPD Alias Test
   Enables/Disable DIMM SPD Alias Test
@@ -1028,9 +1217,17 @@ typedef struct {
 **/
   UINT8                       EccSupport;
 
-/** Offset 0x026F - Reserved
+/** Offset 0x026F - DLL DCC Calibration
+  Enables/Disable DLL DCC Calibration
+  $EN_DIS
 **/
-  UINT8                       Reserved20[2];
+  UINT8                       DLLDCC;
+
+/** Offset 0x0270 - DLL BW Select Calibration
+  Enables/Disable DLL BW Select Calibration
+  $EN_DIS
+**/
+  UINT8                       DLLBWSEL;
 
 /** Offset 0x0271 - Ibecc
   In-Band ECC Support
@@ -1044,9 +1241,11 @@ typedef struct {
 **/
   UINT8                       IbeccParity;
 
-/** Offset 0x0273 - Reserved
+/** Offset 0x0273 - MsHashEnable
+  Controller Hash Enable: 0=Disable, <b>1=Enable</b>
+  $EN_DIS
 **/
-  UINT8                       Reserved21;
+  UINT8                       MsHashEnable;
 
 /** Offset 0x0274 - IbeccOperationMode
   In-Band ECC Operation Mode
@@ -1062,7 +1261,7 @@ typedef struct {
 
 /** Offset 0x027D - Reserved
 **/
-  UINT8                       Reserved22;
+  UINT8                       Reserved3;
 
 /** Offset 0x027E - IbeccProtectedRegionBases
   IBECC Protected Region Bases per IBECC instance
@@ -1135,9 +1334,17 @@ typedef struct {
 **/
   UINT8                       ExitOnFailure;
 
-/** Offset 0x02A8 - Reserved
+/** Offset 0x02A8 - Wck Pad DCC Calibration
+  Enable/disable Wck Pad DCC Calibration
+  $EN_DIS
 **/
-  UINT8                       Reserved23[2];
+  UINT8                       WCKPADDCCCAL;
+
+/** Offset 0x02A9 - DCC PI Code LUT Calibration
+  Enable/Disable DCC PI Code LUT Calibration
+  $EN_DIS
+**/
+  UINT8                       DCCPICODELUT;
 
 /** Offset 0x02AA - Read Voltage Centering 1D
   Enable/Disable Read Voltage Centering 1D
@@ -1223,9 +1430,11 @@ typedef struct {
 **/
   UINT8                       RowPressEn;
 
-/** Offset 0x02B8 - Reserved
+/** Offset 0x02B8 - DBI feature
+  Enables/Disable DBI feature
+  $EN_DIS
 **/
-  UINT8                       Reserved24;
+  UINT8                       DBI;
 
 /** Offset 0x02B9 - DDR5 MR7 WICA support
   Enable if DDR5 DRAM Device supports MR7 WICA 0.5 tCK offset alignment
@@ -1252,9 +1461,10 @@ typedef struct {
 **/
   UINT16                      ChHashMask;
 
-/** Offset 0x02BE - Reserved
+/** Offset 0x02BE - CccPinsInterleaved
+  Interleaving mode of CCC pins which depends on board routing: <b>0=Disable</b>, 1=Enable
 **/
-  UINT8                       Reserved25;
+  UINT8                       CccPinsInterleaved;
 
 /** Offset 0x02BF - Throttler CKEMin Timer
   Timer value for CKEMin, range[255;0]. Req'd min of SC_ROUND_T + BYTE_LENGTH (4).
@@ -1333,7 +1543,12 @@ typedef struct {
 
 /** Offset 0x02CB - Reserved
 **/
-  UINT8                       Reserved26[5];
+  UINT8                       Reserved4;
+
+/** Offset 0x02CC - IbeccEccInjAddrBase
+  Address to match against for ECC error injection. Example: 1 = 32MB, 2 = 64MB
+**/
+  UINT32                      IbeccEccInjAddrBase;
 
 /** Offset 0x02D0 - DDR Phy Safe Mode Support
   DdrSafeMode[0]: Basic PM Features, DdrSafeMode[1]: Spine Gating, DdrSafeMode[2]:
@@ -1353,9 +1568,56 @@ typedef struct {
 **/
   UINT8                       CleanMemory;
 
-/** Offset 0x02D6 - Reserved
+/** Offset 0x02D6 - Tseg Retry Count
+  Tseg Retry count will increase based on TSEG Region Fail count
+  0: Default, 1:3
 **/
-  UINT8                       Reserved27[8];
+  UINT8                       RetryCount;
+
+/** Offset 0x02D7 - Mrc Ppr Status
+   Get Mrc PPR Status after PPR Recovery flow will get Trigger
+  0: PASS, 1: FAIL(Default)
+**/
+  UINT8                       MrcPprStatus;
+
+/** Offset 0x02D8 - Tseg Memory Test Status
+   If enabled, PPR Recovery flow will get Trigger
+  0: PASS, 1: FAIL(Default)
+**/
+  UINT8                       TsegMemoryTestStatus;
+
+/** Offset 0x02D9 - Ppr Recovery Status Enable
+  0: Disabled(Default), 1: Enabled.  If enabled, PPR Recovery flow will get Trigger.
+  $EN_DIS
+**/
+  UINT8                       PprRecoveryStatusEnable;
+
+/** Offset 0x02DA - Safe Loading Bios Enable State
+  0: Disabled(Default), 1: Enabled. If enabled, Memory diagnostic will perform for
+  TSEG Region.
+  $EN_DIS
+**/
+  UINT8                       SafeLoadingBiosEnableState;
+
+/** Offset 0x02DB - BDAT test type
+  When BdatEnable is set to TRUE, this option selects the type of data which will
+  be populated in the BIOS Data ACPI Tables: <b>0=RMT</b>, 1=RMT Per Bit, 2=Margin 2D.
+  0:RMT per Rank, 1:RMT per Bit, 2:Margin2D
+**/
+  UINT8                       MrcBdatTestType;
+
+/** Offset 0x02DC - MrcBdatEnable
+  0: Disabled(Default), 1: Enabled. This field enables the generation of the BIOS
+  DATA ACPI Tables: <b>0=FALSE</b>, 1=TRUE.
+  $EN_DIS
+**/
+  UINT8                       MrcBdatEnable;
+
+/** Offset 0x02DD - DisableMrcRetraining
+  0: Disabled(Default), 1: Enabled. Enable/Disable DisableMrcRetraining
+  $EN_DIS
+**/
+  UINT8                       DisableMrcRetraining;
 
 /** Offset 0x02DE - RMTLoopCount
   Specifies the Loop Count to be used during Rank Margin Tool Testing. 0 - AUTO
@@ -1391,7 +1653,7 @@ typedef struct {
 
 /** Offset 0x02E7 - Reserved
 **/
-  UINT8                       Reserved28;
+  UINT8                       Reserved5;
 
 /** Offset 0x02E8 - Margin limit check L2
   Margin limit check L2 threshold: <b>100=Default</b>
@@ -1404,9 +1666,12 @@ typedef struct {
 **/
   UINT8                       ExtendedBankHashing;
 
-/** Offset 0x02EB - Reserved
+/** Offset 0x02EB - DRFM Blast Radius Configuration
+  Row Hammer DRFM Blast Radius Configuration determines number of victim rows around
+  aggressor row targeted to send the DRFM sequence to: <b>2=BlastRadius 2</b>, 3=BlastRadius
+  3, 4=BlastRadius 4
 **/
-  UINT8                       Reserved29;
+  UINT8                       DrfmBrc;
 
 /** Offset 0x02EC - LP5 Command Pins Mapping
   BitMask where bits [3:0] are Controller 0 Channel [3:0] and bits [7:4] are Controller
@@ -1426,9 +1691,73 @@ typedef struct {
 **/
   UINT8                       MrcTimeMeasure;
 
-/** Offset 0x02EF - Reserved
+/** Offset 0x02EF - DVFSQ Enabled
+  Enable/Disable DVFSQ
+  $EN_DIS
 **/
-  UINT8                       Reserved30[43];
+  UINT8                       DvfsqEnabled;
+
+/** Offset 0x02F0 - E-DVFSC Enabled
+  Eanble/Disable DVFSC
+  $EN_DIS
+**/
+  UINT8                       DvfscEnabled;
+
+/** Offset 0x02F1 - Ddr5 Dca Training
+  Enable/Disable DDR5 Dca Training
+  $EN_DIS
+**/
+  UINT8                       DCCDDR5READDCA;
+
+/** Offset 0x02F2 - PPR Run WCHMATS8
+  Run WCHMATS8 in Post Package Repair flow
+**/
+  UINT8                       PprRunWCHMATS8;
+
+/** Offset 0x02F3 - PPR Run Retention
+  Run Data Retention in Post Package Repair flow
+**/
+  UINT8                       PprRunRetention;
+
+/** Offset 0x02F4 - PPR Run XMarch
+  Run XMarch in Post Package Repair flow
+**/
+  UINT8                       PprRunXMarch;
+
+/** Offset 0x02F5 - PPR Run XMarchG
+  Run XMarchG in Post Package Repair flow
+**/
+  UINT8                       PprRunXMarchG;
+
+/** Offset 0x02F6 - PPR Run YMarchShort
+  Run YMarchShort in Post Package Repair flow
+**/
+  UINT8                       PprRunYMarchShort;
+
+/** Offset 0x02F7 - PPR Run YMarchLong
+  Run YMarchLong in Post Package Repair flow
+**/
+  UINT8                       PprRunYMarchLong;
+
+/** Offset 0x02F8 - PPR Run Mmrw
+  Run Mmrw in Post Package Repair flow
+**/
+  UINT8                       PprRunMmrw;
+
+/** Offset 0x02F9 - PPR Test Disabled
+  Don't run any test in Post Package Repair flow
+**/
+  UINT8                       PprTestDisabled;
+
+/** Offset 0x02FA - PPR Entry Info
+  PPR Repair Info
+**/
+  UINT8                       PprEntryInfo[16];
+
+/** Offset 0x030A - PPR Entry Address
+  PPR Repair Memory Address
+**/
+  UINT8                       PprEntryAddress[16];
 
 /** Offset 0x031A - Read Vref Decap Training*
   Enable/Disable Read Timing Centering Training with SR stress*
@@ -1454,9 +1783,27 @@ typedef struct {
 **/
   UINT8                       IsWckIdleExitEnabled;
 
-/** Offset 0x031E - Reserved
+/** Offset 0x031E - LP5 Safe Speed
+  Enable / Disable LP5 Safe Speed feature
+  $EN_DIS
 **/
-  UINT8                       Reserved31[17];
+  UINT8                       Lp5SafeSpeed;
+
+/** Offset 0x031F - Force InternalClkOn
+  Force InternalClocksOn and TxPiOn to be set to 1 for frequencies >= 7467
+  $EN_DIS
+**/
+  UINT8                       ForceInternalClkOn;
+
+/** Offset 0x0320 - DIMM Rx Offset Calibration training
+  Enable/Disable DIMM Rx Offset Calibration training
+  $EN_DIS
+**/
+  UINT8                       DIMMRXOFFSET;
+
+/** Offset 0x0321 - Reserved
+**/
+  UINT8                       Reserved6[14];
 
 /** Offset 0x032F - Board Type
   MrcBoardType, Options are 0=Mobile/Mobile Halo, 1=Desktop/DT Halo, 5=ULT/ULX/Mobile
@@ -1478,9 +1825,11 @@ typedef struct {
 **/
   UINT8                       TxtImplemented;
 
-/** Offset 0x0341 - Reserved
+/** Offset 0x0341 - PCIE Resizable BAR Support
+  Enable/Disable PCIE Resizable BAR Support.0: Disable; 1: Enable; 2: Auto(Default).
+  $EN_DIS
 **/
-  UINT8                       Reserved32;
+  UINT8                       PcieResizableBarSupport;
 
 /** Offset 0x0342 - Skip external display device scanning
   Enable: Do not scan for external display device, Disable (Default): Scan external
@@ -1608,7 +1957,7 @@ typedef struct {
 
 /** Offset 0x04D6 - Reserved
 **/
-  UINT8                       Reserved33[2];
+  UINT8                       Reserved7[2];
 
 /** Offset 0x04D8 - DMIC<N> ClkA Pin Muxing (N - DMIC number)
   Determines DMIC<N> ClkA Pin muxing. See  GPIO_*_MUXING_DMIC<N>_CLKA_*
@@ -1623,7 +1972,7 @@ typedef struct {
 
 /** Offset 0x04E1 - Reserved
 **/
-  UINT8                       Reserved34[3];
+  UINT8                       Reserved8[3];
 
 /** Offset 0x04E4 - DMIC<N> Data Pin Muxing
   Determines DMIC<N> Data Pin muxing. See GPIO_*_MUXING_DMIC<N>_DATA_*
@@ -1635,9 +1984,35 @@ typedef struct {
 **/
   UINT8                       PchHdaAudioLinkSspEnable[7];
 
-/** Offset 0x04F3 - Reserved
+/** Offset 0x04F3 - PCH Hda Disc Bt Off Enabled
+  Hda Disc Bt Off Enabled
 **/
-  UINT8                       Reserved35[117];
+  UINT8                       PchHdaDiscBtOffEnabled;
+
+/** Offset 0x04F4 - PCH HDA Discrete BT Offload Ssp Link
+  Discrete BT Offload Ssp Link
+**/
+  UINT32                      PchHdaDiscBtOffSspLink;
+
+/** Offset 0x04F8 - SSP<N> Sclk Pin Muxing (N - SSP Number)
+  Determines SSP<N> Sclk Pin muxing. See GPIOV2_*_MUXING_I2S*_SCLK
+**/
+  UINT32                      PchHdaAudioLinkSspSclkPinMux[7];
+
+/** Offset 0x0514 - SSP<N> Sfmr Pin Muxing (N - SSP Number)
+  Determines SSP<N> Sfmr Pin muxing. See GPIOV2_*_MUXING_I2S*_SFMR
+**/
+  UINT32                      PchHdaAudioLinkSspSfmrPinMux[7];
+
+/** Offset 0x0530 - SSP<N> Txd Pin Muxing (N - SSP Number)
+  Determines SSP<N> Txd Pin muxing. See GPIOV2_*_MUXING_I2S*_TXD
+**/
+  UINT32                      PchHdaAudioLinkSspTxdPinMux[7];
+
+/** Offset 0x054C - SSP<N> Rxd Pin Muxing (N - SSP Number)
+  Determines SSP<N> Rxd Pin muxing. See GPIOV2_*_MUXING_I2S*_RXD
+**/
+  UINT32                      PchHdaAudioLinkSspRxdPinMux[7];
 
 /** Offset 0x0568 - Enable HD Audio SoundWire#N Link
   Enable/disable HD Audio SNDW#N link. Muxed with HDA.
@@ -1656,9 +2031,41 @@ typedef struct {
 **/
   UINT8                       PchHdaIDispLinkTmode;
 
-/** Offset 0x056F - Reserved
+/** Offset 0x056F - Sndw Multilane enablement
+  SoundWire Multiline enablement. Default is DISABLE. 0: DISABLE, 1: Two lines enabled,
+  2: Three lines enabled, 3: Four Lines enabled.
+  $EN_DIS
 **/
-  UINT8                       Reserved36[45];
+  UINT8                       PchHdAudioSndwMultilaneEnable[2];
+
+/** Offset 0x0571 - Reserved
+**/
+  UINT8                       Reserved9[3];
+
+/** Offset 0x0574 - SoundWire<N> Clk Pin Muxing (N - SoundWire number)
+  Determines SoundWire<N> Clk Pin muxing. See  GPIOV2_*_MUXING_SNDW<N>_CLK*
+**/
+  UINT32                      PchHdaAudioLinkMultilaneClkPinMux[2];
+
+/** Offset 0x057C - SoundWire<N> Multilane Data0 Pin Muxing (N - SoundWire number)
+  Determines SoundWire<N> Multilane Clk Pin muxing. See  GPIOV2_*_MUXING_SNDW<N>_DATA0*
+**/
+  UINT32                      PchHdaAudioLinkMultilaneData0PinMux[2];
+
+/** Offset 0x0584 - SoundWire<N> Multilane Data1 Pin Muxing (N - SoundWire number)
+  Determines SoundWire<N> Multilane Clk Pin muxing. See  GPIOV2_*_MUXING_SNDW<N>_DATA1*
+**/
+  UINT32                      PchHdaAudioLinkMultilaneData1PinMux[2];
+
+/** Offset 0x058C - SoundWire<N> Multilane Data2 Pin Muxing (N - SoundWire number)
+  Determines SoundWire<N> Multilane Clk Pin muxing. See  GPIOV2_*_MUXING_SNDW<N>_DATA2*
+**/
+  UINT32                      PchHdaAudioLinkMultilaneData2PinMux[2];
+
+/** Offset 0x0594 - SoundWire<N> Multilane Data3 Pin Muxing (N - SoundWire number)
+  Determines SoundWire<N> Multilane Clk Pin muxing. See  GPIOV2_*_MUXING_SNDW<N>_DATA3*
+**/
+  UINT32                      PchHdaAudioLinkMultilaneData3PinMux[2];
 
 /** Offset 0x059C - iDisplay Audio Codec disconnection
   0: Not disconnected, enumerable, 1: Disconnected SDI, not enumerable.
@@ -1666,9 +2073,20 @@ typedef struct {
 **/
   UINT8                       PchHdaIDispCodecDisconnect;
 
-/** Offset 0x059D - Reserved
+/** Offset 0x059D - Sndw<N> Interface for Multilanes (N - SoundWire number)
+  0: Not disconnected, enumerable, 1: Disconnected SDI, not enumerable.
+  0: Sndw0, 1: Sndw1, 2: Sndw2, 3: Sndw3, 4: Sndw4, 5: Sndw5
 **/
-  UINT8                       Reserved37[5];
+  UINT8                       PchHdAudioSndwMultilaneSndwInterface[2];
+
+/** Offset 0x059F - Reserved
+**/
+  UINT8                       Reserved10;
+
+/** Offset 0x05A0 - Audio Sub System IDs
+  Set default Audio Sub System IDs. If its set to 0 then value from Strap is used.
+**/
+  UINT16                      ResetWaitTimer;
 
 /** Offset 0x05A2 - HDA Power/Clock Gating (PGD/CGD)
   Enable/Disable HD Audio Power and Clock Gating(POR: Enable). 0: PLATFORM_POR, 1:
@@ -1677,18 +2095,22 @@ typedef struct {
 **/
   UINT8                       PchHdaTestPowerClockGating;
 
-/** Offset 0x05A3 - Reserved
+/** Offset 0x05A3 - Low Frequency Link Clock Source (LFLCS)
+  0: POR (Enable), 1: Enable (XTAL), 2: Disable (Audio PLL).
+  0: POR (Enable), 1: Enable (XTAL), 2: Disable (Audio PLL)
 **/
-  UINT8                       Reserved38;
+  UINT8                       PchHdaTestLowFreqLinkClkSrc;
 
 /** Offset 0x05A4 - Audio Sub System IDs
   Set default Audio Sub System IDs. If its set to 0 then value from Strap is used.
 **/
   UINT32                      PchHdaSubSystemIds;
 
-/** Offset 0x05A8 - Reserved
+/** Offset 0x05A8 - SoundWire clock source select
+  Select clock source for the SoundWire controllers. 0: XTAL, 1: Audio PLL.
+  $EN_DIS
 **/
-  UINT8                       Reserved39;
+  UINT8                       PchHdaSndwClockSourceSelect;
 
 /** Offset 0x05A9 - PCH LPC Enhance the port 8xh decoding
   Original LPC only decodes one byte of port 80h.
@@ -1708,7 +2130,12 @@ typedef struct {
 
 /** Offset 0x05CE - Reserved
 **/
-  UINT8                       Reserved40[46];
+  UINT8                       Reserved11[14];
+
+/** Offset 0x05DC - Clk Req GPIO Pin
+  Select Clk Req Pin. Refer to GPIO_*_MUXING_SRC_CLKREQ_x* for possible values.
+**/
+  UINT32                      PcieClkReqGpioMux[8];
 
 /** Offset 0x05FC - Enable PCIE RP Mask
   Enable/disable PCIE Root Ports. 0: disable, 1: enable. One bit for each port, bit0
@@ -1724,7 +2151,7 @@ typedef struct {
 
 /** Offset 0x0601 - Reserved
 **/
-  UINT8                       Reserved41[3];
+  UINT8                       Reserved12[3];
 
 /** Offset 0x0604 - Serial Io Uart Debug Mmio Base
   Select SerialIo Uart default MMIO resource in SEC/PEI phase when PcdLpssUartMode
@@ -1799,9 +2226,13 @@ typedef struct {
 **/
   UINT8                       WdtDisableAndLock;
 
-/** Offset 0x061A - Reserved
+/** Offset 0x061A
 **/
-  UINT8                       Reserved42[2];
+  UINT8                       FabricGVDisable;
+
+/** Offset 0x061B - Reserved
+**/
+  UINT8                       Reserved13;
 
 /** Offset 0x061C - HECI Timeouts
   0: Disable, 1: Enable (Default) timeout check for HECI
@@ -1852,9 +2283,18 @@ typedef struct {
 **/
   UINT8                       SkipMbpHob;
 
-/** Offset 0x0624 - Reserved
+/** Offset 0x0624 - HECI Communication
+  Test, 0: POR, 1: enable, 2: disable, Disables HECI communication causing ME to enter
+  error state.
+  $EN_DIS
 **/
-  UINT8                       Reserved43[2];
+  UINT8                       HeciCommunication;
+
+/** Offset 0x0625 - HECI3 Interface Communication
+  Test, 0: POR, 1: enable, 2: disable, Adds or Removes HECI3 Device from PCI space.
+  $EN_DIS
+**/
+  UINT8                       HeciCommunication3;
 
 /** Offset 0x0626 - ISA Serial Base selection
   Select ISA Serial Base address. Default is 0x3F8.
@@ -1873,9 +2313,47 @@ typedef struct {
 **/
   UINT16                      PostCodeOutputPort;
 
-/** Offset 0x062A - Reserved
+/** Offset 0x062A - Enable/Disable I2cPostcode
+  Enable (Default): Postcode via I2C, Disable: Postcode via Port80
+  $EN_DIS
 **/
-  UINT8                       Reserved44[26];
+  UINT8                       I2cPostCodeEnable;
+
+/** Offset 0x062B - Reserved
+**/
+  UINT8                       Reserved14[5];
+
+/** Offset 0x0630 - FSPM Validation Pointer
+  Point to FSPM Validation configuration structure
+**/
+  UINT64                      FspmValidationPtr;
+
+/** Offset 0x0638 - Extended BIOS Support
+  Enable/Disable Extended BIOS Region Support. Default is DISABLE. 0: DISABLE, 1: ENABLE
+  $EN_DIS
+**/
+  UINT8                       ExtendedBiosDecodeRange;
+
+/** Offset 0x0639 - Extented BIOS Direct Read Decode enable
+  Enable/Disable access to bigger than 16MB BIOS Region through Direct Memory Reads.
+  0: disabled (default), 1: enabled
+  $EN_DIS
+**/
+  UINT8                       PchSpiExtendedBiosDecodeRangeEnable;
+
+/** Offset 0x063A - Reserved
+**/
+  UINT8                       Reserved15[2];
+
+/** Offset 0x063C - Extended BIOS Direct Read Decode Range base
+  Bits of 31:16 of a memory address that'll be a base for Extended BIOS Direct Read Decode.
+**/
+  UINT32                      PchSpiExtendedBiosDecodeRangeBase;
+
+/** Offset 0x0640 - Extended BIOS Direct Read Decode Range limit
+  Bits of 31:16 of a memory address that'll be a limit for Extended BIOS Direct Read Decode.
+**/
+  UINT32                      PchSpiExtendedBiosDecodeRangeLimit;
 
 /** Offset 0x0644 - Enable SMBus
   Enable/disable SMBus controller.
@@ -1896,7 +2374,7 @@ typedef struct {
 
 /** Offset 0x0647 - Reserved
 **/
-  UINT8                       Reserved45;
+  UINT8                       Reserved16;
 
 /** Offset 0x0648 - SMBUS Base Address
   SMBUS Base Address (IO space).
@@ -1911,7 +2389,7 @@ typedef struct {
 
 /** Offset 0x064B - Reserved
 **/
-  UINT8                       Reserved46[13];
+  UINT8                       Reserved17[13];
 
 /** Offset 0x0658 - Smbus dynamic power gating
   Disable or Enable Smbus dynamic power gating.
@@ -1932,9 +2410,51 @@ typedef struct {
 **/
   UINT8                       SaOcSupport;
 
-/** Offset 0x065B - Reserved
+/** Offset 0x065B - VF Point Count
+  Number of supported Voltage & Frequency Point Offset
 **/
-  UINT8                       Reserved47[18];
+  UINT8                       VfPointCount[10];
+
+/** Offset 0x0665 - ProcessVmaxLimit
+  Disabling Process Vmax Limit will allow user to set any voltage
+**/
+  UINT8                       ProcessVmaxLimit;
+
+/** Offset 0x0666 - CorePllCurrentRefTuningOffset
+  Core PLL Current Reference Tuning Offset. <b>0: No offset</b>. Range 0-15
+**/
+  UINT8                       CorePllCurrentRefTuningOffset;
+
+/** Offset 0x0667 - RingPllCurrentRefTuningOffset
+  Ring PLL Current Reference Tuning Offset. <b>0: No offset</b>. Range 0-15
+**/
+  UINT8                       RingPllCurrentRefTuningOffset;
+
+/** Offset 0x0668 - IaAtomPllCurrentRefTuningOffset
+  IaAtom PLL Current Reference Tuning Offset. <b>0: No offset</b>. Range 0-15
+**/
+  UINT8                       IaAtomPllCurrentRefTuningOffset;
+
+/** Offset 0x0669 - CoreMinRatio
+  equest Core Min Ratio. Limit Core minimum ratio for extreme overclocking. Default
+  0 indicates no request
+**/
+  UINT8                       CoreMinRatio;
+
+/** Offset 0x066A - CoreMiNegativeTemperatureReportingnRatio
+  Negative Temperature Reporting Enable. <b>0: Disable</b>, 1: enable
+**/
+  UINT8                       NegativeTemperatureReporting;
+
+/** Offset 0x066B - PcorePowerDensityThrottle
+  Power Density Throttle control allows user to disable P-core
+**/
+  UINT8                       PcorePowerDensityThrottle;
+
+/** Offset 0x066C - EcorePowerDensityThrottle
+  Power Density Throttle control allows user to disable P-core
+**/
+  UINT8                       EcorePowerDensityThrottle;
 
 /** Offset 0x066D - Over clocking support
   Over clocking support; <b>0: Disable</b>; 1: Enable
@@ -1942,9 +2462,12 @@ typedef struct {
 **/
   UINT8                       OcSupport;
 
-/** Offset 0x066E - Reserved
+/** Offset 0x066E - UnderVolt Protection
+  When UnderVolt Protection is enabled, user will be not be able to program under
+  voltage in OS runtime. 0: Disabled; <b>1: Enabled</b>
+  $EN_DIS
 **/
-  UINT8                       Reserved48;
+  UINT8                       UnderVoltProtection;
 
 /** Offset 0x066F - Realtime Memory Timing
   0(Default): Disabled, 1: Enabled. When enabled, it will allow the system to perform
@@ -2005,9 +2528,18 @@ typedef struct {
 **/
   UINT8                       Lfsr1Mask;
 
-/** Offset 0x067B - Reserved
+/** Offset 0x067B - Row Hammer DRAM Refresh Management Mode
+  Row Hammer Adaptive Refresh Management Level: 0-RFM (default), 1-ARFMLevel A, 2-ARFMLevel
+  B, 3-ARFMLevel C, 4-Disable ARFM and RFM
+  0: RFM, 1: ARFM Level A, 2: ARFM Level B, 3: ARFM Level C, 4: ARFM and RFM Disabled
 **/
-  UINT8                       Reserved49[2];
+  UINT8                       DramRfmMode;
+
+/** Offset 0x067C - Row Hammer Targeted Row Refresh Mode
+  Row Hammer Targeted Row Refresh: 0-DRFM, 1-pTRR (default), 2-Disable DRFM and pTRR
+  0: DRFM, 1: pTRR, 2: Targeted Row Refresh Disabled
+**/
+  UINT8                       TargetedRowRefreshMode;
 
 /** Offset 0x067D - TjMax Offset
   TjMax offset.Specified value here is clipped by pCode (125 - TjMax Offset) to support
@@ -2015,9 +2547,27 @@ typedef struct {
 **/
   UINT8                       TjMaxOffset;
 
-/** Offset 0x067E - Reserved
+/** Offset 0x067E - Per-Atom-Cluster VF Offset
+  Array used to specifies the selected Atom Core Cluster Offset Voltage. This voltage
+  is specified in millivolts.
 **/
-  UINT8                      Reserved50[48];
+  UINT16                      PerAtomClusterVoltageOffset[8];
+
+/** Offset 0x068E - Per-Atom-Cluster VF Offset Prefix
+  Sets the PerAtomCLusterVoltageOffset value as positive or negative for the selected
+  Core; <b>0: Positive </b>; 1: Negative.
+**/
+  UINT8                       PerAtomClusterVoltageOffsetPrefix[8];
+
+/** Offset 0x0696 - Per-Atom-Cluster Voltage Mode
+  Array used to specifies the selected Atom Core ClusterVoltage Mode.
+**/
+  UINT8                       PerAtomClusterVoltageMode[8];
+
+/** Offset 0x069E - Per-Atom-Cluster Voltage Override
+  Array used to specifies the selected Atom Core Cluster Voltage Override.
+**/
+  UINT16                      PerAtomClusterVoltageOverride[8];
 
 /** Offset 0x06AE - Core VF Point Offset
   Array used to specifies the Core Voltage Offset applied to the each selected VF
@@ -2037,9 +2587,28 @@ typedef struct {
 **/
   UINT8                       CoreVfPointRatio[15];
 
-/** Offset 0x06EA - Reserved
+/** Offset 0x06EA - Core VF Configuration Scope
+  Allows both all-core VF curve or per-core VF curve configuration; <b>0: All-core</b>;
+  1: Per-core.
+  0:All-core, 1:Per-core
 **/
-  UINT8                       Reserved51[26];
+  UINT8                       CoreVfConfigScope;
+
+/** Offset 0x06EB - Reserved
+**/
+  UINT8                       Reserved18;
+
+/** Offset 0x06EC - Per-core VF Offset
+  Array used to specifies the selected Core Offset Voltage. This voltage is specified
+  in millivolts.
+**/
+  UINT16                      PerCoreVoltageOffset[8];
+
+/** Offset 0x06FC - Per-core VF Offset Prefix
+  Sets the PerCoreVoltageOffset value as positive or negative for the selected Core;
+  <b>0: Positive </b>; 1: Negative.
+**/
+  UINT8                       PerCoreVoltageOffsetPrefix[8];
 
 /** Offset 0x0704 - Per Core Max Ratio override
   Enable or disable Per Core PState OC supported by writing OCMB 0x1D to program new
@@ -2048,18 +2617,30 @@ typedef struct {
 **/
   UINT8                       PerCoreRatioOverride;
 
-/** Offset 0x0705 - Reserved
+/** Offset 0x0705 - Per-core Voltage Mode
+  Array used to specifies the selected Core Voltage Mode.
 **/
-  UINT8                       Reserved52[25];
+  UINT8                       PerCoreVoltageMode[8];
+
+/** Offset 0x070D - Reserved
+**/
+  UINT8                       Reserved19;
+
+/** Offset 0x070E - Per-core Voltage Override
+  Array used to specifies the selected Core Voltage Override.
+**/
+  UINT16                      PerCoreVoltageOverride[8];
 
 /** Offset 0x071E - Per Core Current Max Ratio
   Array for the Per Core Max Ratio
 **/
   UINT8                       PerCoreRatio[8];
 
-/** Offset 0x0726 - Reserved
+/** Offset 0x0726 - Atom Cluster Max Ratio
+  Array for Atom Cluster Max Ratio, 4 ATOM cores are in the same Cluster and their
+  max core ratio will be aligned.
 **/
-  UINT8                       Reserved53[8];
+  UINT8                       AtomClusterRatio[8];
 
 /** Offset 0x072E - Pvd Ratio Threshold for SOC/CPU die
   Array of Pvd Ratio Threshold for SOC/CPU die is the threshold value for input ratio
@@ -2070,9 +2651,53 @@ typedef struct {
 **/
   UINT8                       PvdRatioThreshold;
 
-/** Offset 0x072F - Reserved
+/** Offset 0x072F - Pvd Mode SOC/CPU die
+  Array of PVD Mode. Value from 0 to 3 for SOC/CPU. 0x0 = div-1 (VCO = Output clock),
+  0x1 = div-2 (VCO = 2x Output clock), 0x2 = div-4 (VCO = 4x Output clock), 0x3 =
+  div-8 (VCO = 8x Output clock).
 **/
-  UINT8                       Reserved54[65];
+  UINT8                       PvdMode;
+
+/** Offset 0x0730 - FLL Overclock Mode
+  Select FLL Mode Value from 0 to 3. 0x0 = no overclocking, 0x1 = ratio overclocking
+  with nominal (0.5-1x) reference clock frequency, 0x2 = BCLK overclocking with elevated
+  (1-3x) reference clock frequency, 0x3 = BCLK overclocking with extreme elevated
+  (3-5x) reference clock frequency and ratio limited to 63.
+**/
+  UINT8                       FllOverclockMode;
+
+/** Offset 0x0731 - Reserved
+**/
+  UINT8                       Reserved20;
+
+/** Offset 0x0732 - Ring VF Point Offset
+  Array used to specifies the Ring Voltage Offset applied to the each selected VF
+  Point. This voltage is specified in millivolts.
+**/
+  UINT16                      RingVfPointOffset[15];
+
+/** Offset 0x0750 - Ring VF Point Offset Prefix
+  Sets the RingVfPointOffset value as positive or negative for corresponding core
+  VF Point; <b>0: Positive </b>; 1: Negative.
+**/
+  UINT8                       RingVfPointOffsetPrefix[15];
+
+/** Offset 0x075F - Ring VF Point Ratio
+  Array for the each selected Ring VF Point to display the ration.
+**/
+  UINT8                       RingVfPointRatio[15];
+
+/** Offset 0x076E - Soc Die SSC enable
+  Enable/Disable Soc-Die SSC Configuration. 0(Default)=Disable, 1=Enable
+  $EN_DIS
+**/
+  UINT8                       SocDieSscEnable;
+
+/** Offset 0x076F - Core Operating Point Reporting
+  Enables Core Operating point reporting. <b>0: Disable</b>; 1: Enable
+  0:Disable, 1:Enable
+**/
+  UINT8                       CoreOpPointReportingEn;
 
 /** Offset 0x0770 - CPU BCLK OC Frequency
   CPU BCLK OC Frequency in KHz units. 98000000Hz = 98MHz <b>0 - Auto</b>. Range is
@@ -2080,9 +2705,23 @@ typedef struct {
 **/
   UINT32                      CpuBclkOcFrequency;
 
-/** Offset 0x0774 - Reserved
+/** Offset 0x0774 - SOC BCLK OC Frequency
+  SOC BCLK OC Frequency in KHz units. 98000000Hz = 98MHz <b>0 - Auto</b>. Range is
+  40Mhz-1000Mhz.
 **/
-  UINT8                      Reserved55[13];
+  UINT32                      SocBclkOcFrequency;
+
+/** Offset 0x0778 - Bitmask of disable cores
+  Core mask is a bitwise indication of which core should be disabled. <b>0x00=Default</b>;
+  Bit 0 - core 0, bit 7 - core 7.
+**/
+  UINT64                      DisablePerCoreMask;
+
+/** Offset 0x0780 - Granular Ratio Override
+  Enable or disable OC Granular Ratio Override. <b>0: Disable</b>, 1: enable
+  $EN_DIS
+**/
+  UINT8                       GranularRatioOverride;
 
 /** Offset 0x0781 - Avx2 Voltage Guardband Scaling Factor
   AVX2 Voltage Guardband Scale factor applied to AVX2 workloads. Range is 0-200 in
@@ -2097,7 +2736,7 @@ typedef struct {
 
 /** Offset 0x0783 - Reserved
 **/
-  UINT8                       Reserved56[5];
+  UINT8                       Reserved21[5];
 
 /** Offset 0x0788 - Enable PCH ISH Controller
   0: Disable, 1: Enable (Default) ISH Controller
@@ -2107,7 +2746,7 @@ typedef struct {
 
 /** Offset 0x0789 - Reserved
 **/
-  UINT8                       Reserved57;
+  UINT8                       Reserved22;
 
 /** Offset 0x078A - BiosSize
   The size of the BIOS region of the IFWI. Used if FspmUpd->FspmConfig.BiosGuard !=
@@ -2140,9 +2779,24 @@ typedef struct {
 **/
   UINT8                       SkipStopPbet;
 
-/** Offset 0x0790 - Reserved
+/** Offset 0x0790 - Reset Auxiliary content
+  Reset Auxiliary content, <b>0: Disabled</b>, 1: Enabled
+  $EN_DIS
 **/
-  UINT8                       Reserved58[3];
+  UINT8                       ResetAux;
+
+/** Offset 0x0791 - TseEnable
+  Enable/Disable. 0: Disable, Enable/Disable Tse feature, 1: enable
+  $EN_DIS
+**/
+  UINT8                       TseEnable;
+
+/** Offset 0x0792 - Enable or Disable TDX
+  Configure Trust Domain Extension (TDX) to isolate VMs from Virtual-Machine Manager
+  (VMM)/hypervisor <b>0: Disable</b>; 1: Enable.
+  $EN_DIS
+**/
+  UINT8                       TdxEnable;
 
 /** Offset 0x0793 - MKTME Key-Id Bits Override Enable
   Configure Trust Domain Extension (TDX) to isolate VMs from Virtual-Machine Manager
@@ -2153,7 +2807,7 @@ typedef struct {
 
 /** Offset 0x0794 - Reserved
 **/
-  UINT8                       Reserved59[4];
+  UINT8                       Reserved23[4];
 
 /** Offset 0x0798 - TME Exclude Base Address
   TME Exclude Base Address.
@@ -2165,9 +2819,26 @@ typedef struct {
 **/
   UINT64                      TmeExcludeSize;
 
-/** Offset 0x07A8 - Reserved
+/** Offset 0x07A8 - TdxActmModuleAddr
+  Base address of Tdx Actm module, used for launching the Actm
 **/
-  UINT8                      Reserved60[14];
+  UINT64                      TdxActmModuleAddr;
+
+/** Offset 0x07B0 - TdxActmModuleSize
+  size of Tdx Actm module, used for launching the Actm
+**/
+  UINT32                      TdxActmModuleSize;
+
+/** Offset 0x07B4 - TdxSeamldrSvn
+  TdxSeamldrSvn
+**/
+  UINT8                       TdxSeamldrSvn;
+
+/** Offset 0x07B5 - Boot max frequency
+  Enable Boot Maximum Frequency in CPU strap. 0: Disable; <b>1: Enable</b>
+  $EN_DIS
+**/
+  UINT8                       BootMaxFrequency;
 
 /** Offset 0x07B6 - BIST on Reset
   Enable/Disable BIST (Built-In Self Test) on reset. <b>0: Disable</b>; 1: Enable.
@@ -2175,9 +2846,11 @@ typedef struct {
 **/
   UINT8                       BistOnReset;
 
-/** Offset 0x07B7 - Reserved
+/** Offset 0x07B7 - Reduce XeCores
+  Enable/Disable Reduce XeCores. <b>0: Disable(strap=1) </b>; 1: Enable(strap=0.
+  $EN_DIS
 **/
-  UINT8                       Reserved61;
+  UINT8                       ReduceXecores;
 
 /** Offset 0x07B8 - Enable or Disable VMX
   Enable or Disable VMX, When enabled, a VMM can utilize the additional hardware capabilities
@@ -2245,9 +2918,29 @@ typedef struct {
 **/
   UINT8                       ActiveCoreCount;
 
-/** Offset 0x07C2 - Reserved
+/** Offset 0x07C2 - Number of active small cores
+  Number of E-cores to enable in each processor package. Note: Number of P-Cores and
+  E-Cores are looked at together. When both are {0,0
+  0:Disable all small cores, 1:1, 2:2, 3:3, 0xFF:Active all small cores
 **/
-  UINT8                       Reserved62[6];
+  UINT8                       ActiveSmallCoreCount;
+
+/** Offset 0x07C3 - Number of LP Atom cores
+  Number of LP E-cores to enable in LP. 0: Disable all LP Atom cores; 1: 1; 2: 2;
+  <b>0xFF: Active all LP Atom cores</b>
+  0:Disable all LP Atom cores, 1:1, 2:2, 0xFF:Active all cores
+**/
+  UINT8                       ActiveLpAtomCoreCount;
+
+/** Offset 0x07C4 - DFD Enable
+  Enable or Disable DFD. <b>0: Disable</b>, 1:Enable
+  $EN_DIS
+**/
+  UINT8                       DfdEnable;
+
+/** Offset 0x07C5 - Reserved
+**/
+  UINT8                       Reserved24[3];
 
 /** Offset 0x07C8 - PrmrrSize
   Enable/Disable. 0: Disable, define default value of PrmrrSize , 1: enable
@@ -2275,7 +2968,311 @@ typedef struct {
 
 /** Offset 0x07D2 - Reserved
 **/
-  UINT8                       Reserved63[92];
+  UINT8                       Reserved25[2];
+
+/** Offset 0x07D4 - Platform PL1 power
+  Platform Power Limit 1 Power in Milli Watts. BIOS will round to the nearest 1/8W
+  when programming. Value set 120 = 15W. Any value can be programmed between Max
+  and Min Power Limits. This setting will act as the new PL1 value for the Package
+  RAPL algorithm. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit. Valid Range
+  0 to 32767.
+**/
+  UINT32                      PsysPowerLimit1Power;
+
+/** Offset 0x07D8 - PlatformAtxTelemetryUnit Mode
+  Enable/Disable PlatformAtxTelemetryUnit Mode.  <b>0: Disable</b> ; 1:Enable
+  $EN_DIS
+**/
+  UINT32                      PlatformAtxTelemetryUnit;
+
+/** Offset 0x07DC - Platform PL1 power
+   Short term Power Limit value for custom cTDP level. Units are 125 milliwatt.
+**/
+  UINT16                      CustomPowerLimit1;
+
+/** Offset 0x07DE - Platform PL1 power
+   Short term Power Limit value for custom cTDP level. Units are 125 milliwatt.
+**/
+  UINT16                      CustomPowerLimit2;
+
+/** Offset 0x07E0 - Platform PL2 power
+  Platform Power Limit 2 Power in Milli Watts. BIOS will round to the nearest 1/8W
+  when programming. Value set 120 = 15W. Any value can be programmed between Max
+  and Min Power Limits. This setting will act as the new Max Turbo Power (PL2) value
+  for the Package RAPL algorithm. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.
+  Valid Range 0 to 32767.
+**/
+  UINT32                      PsysPowerLimit2Power;
+
+/** Offset 0x07E4 - Vsys Max System battery volatge
+  Vsys Max defined in 1/1000 increments. Range is 0-65535. For a 1.25 voltage, enter
+  1250. <b>Default =0xFF</b>.
+**/
+  UINT16                      VsysMax;
+
+/** Offset 0x07E6 - ThETA Ibatt Feature
+  Enable or Disable ThETA Ibatt Feature. <b>0: Disable</b>; 1: Enable.
+  $EN_DIS
+**/
+  UINT8                       ThETAIbattEnable;
+
+/** Offset 0x07E7 - Reserved
+**/
+  UINT8                       Reserved26;
+
+/** Offset 0x07E8 - ISYS Current Limit L1
+  This field indicated the current limitiation of L1. Indicate current limit for which
+  dependency is on AC/DC mode before PSYS.Units of measurements are 1/8 A
+**/
+  UINT16                      IsysCurrentLimitL1;
+
+/** Offset 0x07EA - ISYS Current Limit L1 Tau
+  This Specifies the time window used to calculate average current for ISYS_L1. The
+  units of measuremnts are specified in PACKAGE_POWER_SKU[TIME_UNIT]
+**/
+  UINT8                       IsysCurrentL1Tau;
+
+/** Offset 0x07EB - Reserved
+**/
+  UINT8                       Reserved27;
+
+/** Offset 0x07EC - ISYS Current Limit L2
+  This bits enables disables ISYS_CURRENT_LIMIT_L2 algorithm.Indicate current limit
+  for which dependency is on AC/DC mode before PSYS. Units of measurements are 1/8 A
+**/
+  UINT16                      IsysCurrentLimitL2;
+
+/** Offset 0x07EE - ISYS Current Limit L1 Enable
+  This bits enables disables ISYS_CURRENT_LIMIT_L1 algorithm. It control loop based
+  on the system power source AC or DC mode. <b>0: Disable</b>; 1: Enable.
+  $EN_DIS
+**/
+  UINT8                       IsysCurrentLimitL1Enable;
+
+/** Offset 0x07EF - ISYS Current Limit L2 Enable
+  This bits enables disables ISYS_CURRENT_LIMIT_L2 algorithm. It control loop based
+  on the system power source AC or DC mode. <b>0: Disable</b>; 1: Enable.
+  $EN_DIS
+**/
+  UINT8                       IsysCurrentLimitL2Enable;
+
+/** Offset 0x07F0 - Package PL4 boost configuration
+  Configure Power Limit 4 Boost in Watts. Valid Range 0 to 63000 in step size of 125
+  mWatt. The value 0 means disable.
+**/
+  UINT16                      PowerLimit4Boost;
+
+/** Offset 0x07F2 - Skin Temperature Target
+  Target temperature is limit to which the control mechanism is regulating.It is defined
+  in 1/2 C increments.Range is 0-255. Temperature Range is 0-122.5 C.<b>0: Auto</b>.
+**/
+  UINT8                       SkinTargetTemp[3];
+
+/** Offset 0x07F5 - Skin Control Temperature Enable MMIO
+  Enables the skin temperature control for MMIO register. <b>0: Disable</b>; 1: Enable.
+  $EN_DIS
+**/
+  UINT8                       SkinTempControlEnable[3];
+
+/** Offset 0x07F8 - Skin Temperature Loop Gain
+  Sets the aggressiveness of control loop where 0 is graceful, favors performance
+  on expense of temperature overshoots and 7 is for aggressive, favors tight regulation
+  over performance. Range is 0-7.<b>0: Auto</b>.
+**/
+  UINT8                       SkinControlLoopGain[3];
+
+/** Offset 0x07FB - Skin Temperature Override Enable
+  When set, Pcode will use TEMPERATURE_OVERRIDE values instead of reading from corresponding
+  sensor.. <b>0: Disable</b>; 1: Enable.
+  $EN_DIS
+**/
+  UINT8                       SkinTempOverrideEnable[3];
+
+/** Offset 0x07FE - Skin Temperature Minimum Performance Level
+  Minimum Performance level below which the STC limit will not throttle. 0 - all levels
+  of throttling allowed incl. survivability actions. 256 - no throttling allowed.<b>0: Auto</b>.
+**/
+  UINT8                       SkinMinPerformanceLevel[3];
+
+/** Offset 0x0801 - Skin Temperature Override
+  Allows SW to override the input temperature. Pcode will use this value instead of
+  the sensor temperature. EC control is not impacted. Units: 0.5C. Values are 0 to
+  255 which represents 0C-122.5C range.<b>0: Auto</b>.
+**/
+  UINT8                       SkinTempOverride[3];
+
+/** Offset 0x0804 - Skin Temperature Control Enable
+  Enables Skin Temperature Control Sensors Feature. <b>0: Disable</b>; 1: Enable.
+  $EN_DIS
+**/
+  UINT8                       SkinTempControl;
+
+/** Offset 0x0805 - AC or DC Power State
+  AC or DC power State; <b>0: DC</b>; 1: AC
+  0:DC, 1:AC
+**/
+  UINT8                       AcDcPowerState;
+
+/** Offset 0x0806 - Enable or Disable VR Thermal Alert
+  Enable or Disable VR Thermal Alert; <b>0: Disable</b>; 1: Enable.
+  $EN_DIS
+**/
+  UINT8                       DisableVrThermalAlert;
+
+/** Offset 0x0807 - Enable or Disable Thermal Monitor
+  Enable or Disable Thermal Monitor; 0: Disable; <b>1: Enable</b>
+  $EN_DIS
+**/
+  UINT8                       ThermalMonitor;
+
+/** Offset 0x0808 - Configuration for boot TDP selection
+  Assured Power (cTDP) Mode as Nominal/Level1/Level2/Deactivate Base Power (TDP) selection.
+  Deactivate option will set MSR to Nominal and MMIO to Zero. <b>0: Base Power (TDP)
+  Nominal</b>; 1: Base Power (TDP) Down; 2: Base Power (TDP) Up;0xFF : Deactivate
+**/
+  UINT8                       ConfigTdpLevel;
+
+/** Offset 0x0809 - ConfigTdp mode settings Lock
+  Assured Power (cTDP) Mode Lock sets the Lock bits on TURBO_ACTIVATION_RATIO and
+  CONFIG_TDP_CONTROL. Note: When CTDP (Assured Power) Lock is enabled Custom ConfigTDP
+  Count will be forced to 1 and Custom ConfigTDP Boot Index will be forced to 0.
+  <b>0: Disable</b>; 1: Enable
+  $EN_DIS
+**/
+  UINT8                       ConfigTdpLock;
+
+/** Offset 0x080A - Load Configurable TDP SSDT
+  Enables Assured Power (cTDP) control via runtime ACPI BIOS methods. This 'BIOS only'
+  feature does not require EC or driver support. <b>0: Disable</b>; 1: Enable.
+  $EN_DIS
+**/
+  UINT8                       ConfigTdpBios;
+
+/** Offset 0x080B - CustomTurboActivationRatio
+  Turbo Activation Ratio for custom cTDP level
+  $EN_DIS
+**/
+  UINT8                       CustomTurboActivationRatio;
+
+/** Offset 0x080C - CustomPowerLimit1Time
+  Short term Power Limit time window value for custom cTDP level.
+  $EN_DIS
+**/
+  UINT8                       CustomPowerLimit1Time;
+
+/** Offset 0x080D - PL1 Enable value
+  Enable/Disable Platform Power Limit 1 programming. If this option is enabled, it
+  activates the PL1 value to be used by the processor to limit the average power
+  of given time window. <b>0: Disable</b>; 1: Enable.
+  $EN_DIS
+**/
+  UINT8                       PsysPowerLimit1;
+
+/** Offset 0x080E - PL1 timewindow
+  Platform Power Limit 1 Time Window value in seconds. The value may vary from 0 to
+  128. 0 = default values. Indicates the time window over which Platform Processor
+  Base Power (TDP) value should be maintained. Valid values(Unit in seconds) 0 to
+  8 , 10 , 12 ,14 , 16 , 20 , 24 , 28 , 32 , 40 , 48 , 56 , 64 , 80 , 96 , 112 , 128
+**/
+  UINT8                       PsysPowerLimit1Time;
+
+/** Offset 0x080F - PL2 Enable Value
+  Enable/Disable Platform Power Limit 2 programming. If this option is disabled, BIOS
+  will program the default values for Platform Power Limit 2. <b>0: Disable</b>;
+  1: Enable.
+  $EN_DIS
+**/
+  UINT8                       PsysPowerLimit2;
+
+/** Offset 0x0810 - Package PL3 time window
+  Power Limit 3 Time Window value in Milli seconds. Indicates the time window over
+  which Power Limit 3 value should be maintained. If the value is 0, BIOS leaves
+  the hardware default value. Valid value: <b>0</b>, 3-8, 10, 12, 14, 16, 20, 24,
+  28, 32, 40, 48, 56, 64.
+**/
+  UINT8                       PowerLimit3Time;
+
+/** Offset 0x0811 - Package Long duration turbo mode time
+  Power Limit 1 Time Window value in seconds. The value may vary from 0 to 128. 0
+  = default value (28 sec for Mobile and 8 sec for Desktop). Defines time window
+  which Processor Base Power (TDP) value should be maintained. Valid values(Unit
+  in seconds) 0 to 8 , 10 , 12 ,14 , 16 , 20 , 24 , 28 , 32 , 40 , 48 , 56 , 64 ,
+  80 , 96 , 112 , 128
+**/
+  UINT8                       PowerLimit1Time;
+
+/** Offset 0x0812 - Reserved
+**/
+  UINT8                       Reserved28[2];
+
+/** Offset 0x0814 - Package Long duration turbo mode power limit
+  Power Limit 1 in Milli Watts. BIOS will round to the nearest 1/8W when programming.
+  Value set 120 = 15W. 0 = no custom override. Overclocking SKU: Value must be between
+  Max and Min Power Limits. Other SKUs: This value must be between Min Power Limit
+  and Processor Base Power (TDP) Limit. If value is 0, BIOS will program Processor
+  Base Power (TDP) value. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit. Valid
+  Range 0 to 32767.
+**/
+  UINT32                      PowerLimit1;
+
+/** Offset 0x0818 - Package Short duration turbo mode power limit
+  Power Limit 2 in Milli Watts. BIOS will round to the nearest 1/8W when programming.
+  Value set 120 = 15W. If the value is 0, BIOS will program this value as 1.25*Processor
+  Base Power (TDP). Processor applies control policies such that the package power
+  does not exceed this limit. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.
+  Valid Range 0 to 32767.
+**/
+  UINT32                      PowerLimit2Power;
+
+/** Offset 0x081C - Package PL3 power limit
+  Power Limit 3 in Milli Watts. BIOS will round to the nearest 1/8W when programming.
+  Value set 120 = 15W. XE SKU: Any value can be programmed. Overclocking SKU: Value
+  must be between Max and Min Power Limits. Other SKUs: This value must be between
+  Min Power Limit and Processor Base Power (TDP) Limit. If the value is 0, BIOS leaves
+  the hardware default value. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.
+  Valid Range 0 to 32767.
+**/
+  UINT32                      PowerLimit3;
+
+/** Offset 0x0820 - Package PL4 power limit
+  Power Limit 4 in Milli Watts. BIOS will round to the nearest 1/8W when programming.
+  Value set 120 = 15W. If the value is 0, BIOS leaves default value. Units are based
+  on POWER_MGMT_CONFIG.CustomPowerUnit. Valid Range 0 to 32767.
+**/
+  UINT32                      PowerLimit4;
+
+/** Offset 0x0824 - Short term Power Limit value for custom cTDP level 1
+  Power Limit 1 in Milli Watts. BIOS will round to the nearest 1/8W when programming.
+  Value set 120 = 15W. 0 = no custom override. Overclocking SKU: Value must be between
+  Max and Min Power Limits. Other SKUs: This value must be between Min Power Limit
+  and Processor Base Power (TDP) Limit. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.
+  Valid Range 0 to 32767.
+**/
+  UINT32                      Custom1PowerLimit1;
+
+/** Offset 0x0828 - Long term Power Limit value for custom cTDP level 1
+  Power Limit 2 value in Milli Watts. BIOS will round to the nearest 1/8W when programming.
+  Value set 120 = 15W. 0 = no custom override. Processor applies control policies
+  such that the package power does not exceed this limit. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.
+  Valid Range 0 to 32767.
+**/
+  UINT32                      Custom1PowerLimit2;
+
+/** Offset 0x082C - Enable Configurable TDP
+  Applies Assured Power (cTDP) initialization settings based on non-Assured Power
+  (cTDP) or Assured Power (cTDP). Default is 1: Applies to Assured Power (cTDP) ;
+  if 0 then applies non-Assured Power (cTDP) and BIOS will bypass Assured Power (cTDP)
+  initialization flow
+  $EN_DIS
+**/
+  UINT8                       ApplyConfigTdp;
+
+/** Offset 0x082D - Dual Tau Boost
+  Enable Dual Tau Boost feature. This is only applicable for Desktop 35W/65W/125W
+  sku. When DPTF is enabled this feature is ignored. <b>0: Disable</b>; 1: Enable
+  $EN_DIS
+**/
+  UINT8                       DualTauBoost;
 
 /** Offset 0x082E - Tcc Offset Lock
   Tcc Offset Lock for Runtime Average Temperature Limit (RATL) to lock temperature
@@ -2284,9 +3281,38 @@ typedef struct {
 **/
   UINT8                       TccOffsetLock;
 
-/** Offset 0x082F - Reserved
+/** Offset 0x082F - Package PL3 Duty Cycle
+  Specify the duty cycle in percentage that the CPU is required to maintain over the
+  configured time window. Range is 0-100.
 **/
-  UINT8                       Reserved64[5];
+  UINT8                       PowerLimit3DutyCycle;
+
+/** Offset 0x0830 - Package PL3 Lock
+  Power Limit 3 Lock. When enabled PL3 configurations are locked during OS. When disabled
+  PL3 configuration can be changed during OS. <b>0: Disable</b> ; 1:Enable
+  $EN_DIS
+**/
+  UINT8                       PowerLimit3Lock;
+
+/** Offset 0x0831 - Package PL4 Lock
+  Power Limit 4 Lock. When enabled PL4 configurations are locked during OS. When disabled
+  PL4 configuration can be changed during OS. <b>0: Disable</b> ; 1:Enable
+  $EN_DIS
+**/
+  UINT8                       PowerLimit4Lock;
+
+/** Offset 0x0832 - Short Duration Turbo Mode
+  Enable/Disable Power Limit 2 override. If this option is disabled, BIOS will program
+  the default values for Power Limit 2. 0: Disable; <b>1: Enable</b>
+  $EN_DIS
+**/
+  UINT8                       PowerLimit2;
+
+/** Offset 0x0833 - Response Mode
+  Enable/Disable Response Mode.  <b>0: Disable</b> ; 1:Enable
+  $EN_DIS
+**/
+  UINT8                       ResponseMode;
 
 /** Offset 0x0834 - SinitMemorySize
   Enable/Disable. 0: Disable, define default value of SinitMemorySize , 1: enable
@@ -2351,9 +3377,18 @@ typedef struct {
 **/
   UINT8                       AcousticNoiseMitigation;
 
-/** Offset 0x086E - Reserved
+/** Offset 0x086E - RfiMitigation
+  Enable or Disable RFI Mitigation. <b>0: Disable - DCM is the IO_N default</b>; 1:
+  Enable - Enable IO_N DCM/CCM switching as RFI mitigation.
+  $EN_DIS
 **/
-  UINT8                       Reserved65[2];
+  UINT8                       RfiMitigation;
+
+/** Offset 0x086F - Platform Psys slope correction
+  PSYS Slope defined in 1/100 increments. <b>0 - Auto</b> Specified in 1/100 increment
+  values. Range is 0-200. 125 = 1.25
+**/
+  UINT8                       PsysSlope;
 
 /** Offset 0x0870 - Platform Power Pmax
   PSYS PMax power, defined in 1/8 Watt increments. <b>0 - Auto</b> Specified in 1/8
@@ -2405,7 +3440,14 @@ typedef struct {
 
 /** Offset 0x08BA - Reserved
 **/
-  UINT8                       Reserved66[26];
+  UINT8                       Reserved29[2];
+
+/** Offset 0x08BC - Imon offset correction
+  IMON Offset is an 32-bit signed value (2's complement). Units 1/1000, Range is [-128000,
+  127999]. For an offset of 25.348, enter 25348. <b>0: Auto</b>. [0] for IA, [1]
+  for GT, [2] for SA, [3] through [5] are Reserved.
+**/
+  UINT32                      ImonOffset[6];
 
 /** Offset 0x08D4 - Icc Max limit
   Voltage Regulator Current Limit (Icc Max). This value represents the Maximum instantaneous
@@ -2415,9 +3457,34 @@ typedef struct {
 **/
   UINT16                      IccMax[6];
 
-/** Offset 0x08E0 - Reserved
+/** Offset 0x08E0 - VR Fast Vmode VoltageLimit support
+  Voltage Regulator Fast VoltageLimit .
 **/
-  UINT8                      Reserved67[42];
+  UINT16                      VrVoltageLimit[6];
+
+/** Offset 0x08EC - Imon slope correction
+  IMON Slope defined in 1/100 increments. Range is 0-200. For a 1.25 slope, enter
+  125. <b>0: Auto</b>. [0] for IA, [1] for GT, [2] for SA, [3] through [5] are Reserved.
+**/
+  UINT16                      ImonSlope[6];
+
+/** Offset 0x08F8 - Power State 3 enable/disable
+  PS3 Enable/Disable. 0 - Disabled, 1 - Enabled. [0] for IA, [1] for GT, [2] for SA,
+  [3] through [5] are Reserved.
+**/
+  UINT8                       Ps3Enable[6];
+
+/** Offset 0x08FE - Power State 4 enable/disable
+  PS4 Enable/Disable. 0 - Disabled, 1 - Enabled. [0] for IA, [1] for GT, [2] for SA,
+  [3] through [5] are Reserved.
+**/
+  UINT8                       Ps4Enable[6];
+
+/** Offset 0x0904 - Enable/Disable BIOS configuration of VR
+  VR Config Enable. [0] for IA, [1] for GT, [2] for SA, [3] through [5] are Reserved.
+  <b>0: Disable</b>; 1: Enable.
+**/
+  UINT8                       VrConfigEnable[6];
 
 /** Offset 0x090A - Thermal Design Current enable/disable
   Thermal Design Current enable/disable; <b>0: Disable</b>; 1: Enable. [0] for IA,
@@ -2425,9 +3492,11 @@ typedef struct {
 **/
   UINT8                       TdcEnable[6];
 
-/** Offset 0x0910 - Reserved
+/** Offset 0x0910 - Thermal Design Current Lock
+  Thermal Design Current Lock; <b>0: Disable</b>; 1: Enable. [0] for IA, [1] for GT,
+  [2] for SA, [3] for atom, [4]-[5] are Reserved.
 **/
-  UINT8                       Reserved68[6];
+  UINT8                       TdcLock[6];
 
 /** Offset 0x0916 - Disable Fast Slew Rate for Deep Package C States for VR domains
   This option needs to be configured to reduce acoustic noise during deeper C states.
@@ -2449,7 +3518,14 @@ typedef struct {
 
 /** Offset 0x0922 - Reserved
 **/
-  UINT8                       Reserved69[6];
+  UINT8                       Reserved30[2];
+
+/** Offset 0x0924 - Platform Psys offset correction
+  PSYS Offset defined in 1/1000 increments. <b>0 - Auto</b> This is an 32-bit signed
+  value (2's complement). Units 1/1000, Range is [-128000, 127999]. For an offset
+  of 25.348, enter 25348.
+**/
+  UINT32                      PsysOffset;
 
 /** Offset 0x0928 - Thermal Design Current time window
   Auto = 0 is default. Range is from 1ms to 448s. <b>0: Auto</b>. [0] for IA, [1]
@@ -2463,9 +3539,17 @@ typedef struct {
 **/
   UINT8                       TdcMode[6];
 
-/** Offset 0x0946 - Reserved
+/** Offset 0x0946 - DLVR RFI Enable
+  Enable/Disable DLVR RFI frequency hopping. 0: Disable; <b>1: Enable</b>.
+  $EN_DIS
 **/
-  UINT8                       Reserved70[2];
+  UINT8                       FivrSpectrumEnable;
+
+/** Offset 0x0947 - DLVR RFI Spread Spectrum Percentage
+  DLVR SSC in percentage with multiple of 0.25%. 0 = 0%, 10 = 4%. 0x00: 0% , <b>0x02:
+  0.5%</b>, 0x04: 1% , 0x08: 2% ,0x10: 4%; u3.2 value from 0% - 4%.
+**/
+  UINT8                       DlvrSpreadSpectrumPercentage;
 
 /** Offset 0x0948 - DLVR RFI Enable
   Enable/Disable DLVR RFI frequency hopping. 0: Disable; <b>1: Enable</b>.
@@ -2485,7 +3569,53 @@ typedef struct {
 
 /** Offset 0x094B - Reserved
 **/
-  UINT8                       Reserved71[11];
+  UINT8                       Reserved31;
+
+/** Offset 0x094C - DLVR RFI Frequency
+  DLVR RFI Frequency in MHz. <b>0: 2227 MHz</b> , 1: 2140MHZ.
+**/
+  UINT16                      DlvrRfiFrequency;
+
+/** Offset 0x094E - DLVR PHASE_SSC Enable
+  Enable/Disable DLVR PHASE_SSC. <b>0: Disable.</b> 1:Enable.
+  $EN_DIS
+**/
+  UINT8                       VrPowerDeliveryDesign;
+
+/** Offset 0x094F - DLVR PHASE_SSC Enable
+  Enable/Disable DLVR PHASE_SSC. <b>0: Disable.</b> 1:Enable.
+  $EN_DIS
+**/
+  UINT8                       DlvrPhaseSsc;
+
+/** Offset 0x0950 - Vsys Critical
+  PCODE MMIO Mailbox: Vsys Critical. <b>0: Disable</b>; 1: Enable Range is 0-255.
+**/
+  UINT8                       EnableVsysCritical;
+
+/** Offset 0x0951 - Assertion Deglitch Mantissa
+  Assertion Deglitch Mantissa, Range is 0-255
+**/
+  UINT8                       VsysAssertionDeglitchMantissa;
+
+/** Offset 0x0952 - Assertion Deglitch Exponent
+  Assertion Deglitch Exponent, Range is 0-255
+**/
+  UINT8                       VsysAssertionDeglitchExponent;
+
+/** Offset 0x0953 - De assertion Deglitch Mantissa
+  De assertion Deglitch Mantissa, Range is 0-255
+**/
+  UINT8                       VsysDeassertionDeglitchMantissa;
+
+/** Offset 0x0954 - De assertion Deglitch Exponent
+  De assertion Deglitch Exponent, Range is 0-255
+**/
+  UINT8                       VsysDeassertionDeglitchExponent;
+
+/** Offset 0x0955 - Reserved
+**/
+  UINT8                       Reserved32;
 
 /** Offset 0x0956 - VR Fast Vmode ICC Limit support
   Voltage Regulator Fast Vmode ICC Limit. A value of 400 = 100A. A value of 0 corresponds
@@ -2510,7 +3640,44 @@ typedef struct {
 
 /** Offset 0x096E - Reserved
 **/
-  UINT8                       Reserved72[28];
+  UINT8                       Reserved33[2];
+
+/** Offset 0x0970 - Vsys Full Scale
+  Vsys Full Scale, Range is 0-255000mV
+**/
+  UINT32                      VsysFullScale;
+
+/** Offset 0x0974 - Vsys Critical Threshold
+  Vsys Critical Threshold, Range is 0-255000mV
+**/
+  UINT32                      VsysCriticalThreshold;
+
+/** Offset 0x0978 - Psys Full Scale
+  Psys Full Scale, Range is 0-255000mV
+**/
+  UINT32                      PsysFullScale;
+
+/** Offset 0x097C - Psys Critical Threshold
+  Psys Critical Threshold, Range is 0-255000mV
+**/
+  UINT32                      PsysCriticalThreshold;
+
+/** Offset 0x0980 - Reserved
+**/
+  UINT8                       Reserved34[8];
+
+/** Offset 0x0988 - IOE Debug Enable
+  Enable/Disable IOE Debug. When enabled, IOE D2D Dfx link will keep up and clock
+  is enabled
+  $EN_DIS
+**/
+  UINT8                       IoeDebugEn;
+
+/** Offset 0x0989 - Pmode Clock Enable
+  Enable/Disable PMODE clock. When enabled, Pmode clock will toggle for XDP use
+  $EN_DIS
+**/
+  UINT8                       PmodeClkEn;
 
 /** Offset 0x098A - PCH Port80 Route
   Control where the Port 80h cycles are sent, 0: LPC; 1: PCI.
@@ -2525,9 +3692,21 @@ typedef struct {
 **/
   UINT8                       GpioOverride;
 
-/** Offset 0x098C - Reserved
+/** Offset 0x098C - Pmc Privacy Consent
+  Enable/Disable Pmc Privacy Consent
+  $EN_DIS
 **/
-  UINT8                       Reserved73[4];
+  UINT8                       PmcPrivacyConsent;
+
+/** Offset 0x098D - DMI ME UMA Root Space Check
+  DMI IOSF Root Space attribute check for RS3 for cycles targeting MEUMA.
+  0: POR, 1: enable, 2: disable
+**/
+  UINT8                       PchTestDmiMeUmaRootSpaceCheck;
+
+/** Offset 0x098E - Reserved
+**/
+  UINT8                       Reserved35[2];
 
 /** Offset 0x0990 - PMR Size
   Size of PMR memory buffer. 0x400000 for normal boot and 0x200000 for S3 boot
@@ -2551,9 +3730,11 @@ typedef struct {
 **/
   UINT8                       VtdDisable;
 
-/** Offset 0x0997 - Reserved
+/** Offset 0x0997 - State of Vtd Capabilities
+  0x0=(No operation), BIT0 = 1 (Defeature Nested Support), BIT1 = 1 (Defeature Posted
+  Interrupt Support)
 **/
-  UINT8                       Reserved74;
+  UINT8                       VtdCapabilityControl;
 
 /** Offset 0x0998 - Base addresses for VT-d function MMIO access
   Base addresses for VT-d MMIO access per VT-d engine
@@ -2562,7 +3743,17 @@ typedef struct {
 
 /** Offset 0x09BC - Reserved
 **/
-  UINT8                       Reserved75[20];
+  UINT8                       Reserved36[4];
+
+/** Offset 0x09C0 - MMIO Size
+  Size of MMIO space reserved for devices. 0(Default)=Auto, non-Zero=size in MB
+**/
+  UINT64                      MchBar;
+
+/** Offset 0x09C8 - MMIO Size
+  Size of MMIO space reserved for devices. 0(Default)=Auto, non-Zero=size in MB
+**/
+  UINT64                      RegBar;
 
 /** Offset 0x09D0 - MMIO Size
   Size of MMIO space reserved for devices. 0(Default)=Auto, non-Zero=size in MB
@@ -2575,9 +3766,50 @@ typedef struct {
 **/
   UINT16                      MmioSizeAdjustment;
 
-/** Offset 0x09D4 - Reserved
+/** Offset 0x09D4 - Temporary address for ApicLocalAddress
+  The reference code will use this as Temporary address space
 **/
-  UINT8                      Reserved76[36];
+  UINT32                      ApicLocalAddress;
+
+/** Offset 0x09D8 - Temporary address for NvmeHcPeiMmioBase
+  The reference code will use this as Temporary address space
+**/
+  UINT32                      NvmeHcPeiMmioBase;
+
+/** Offset 0x09DC - Temporary address for NvmeHcPeiMmioLimit
+  The reference code will use this as Temporary address space
+**/
+  UINT32                      NvmeHcPeiMmioLimit;
+
+/** Offset 0x09E0 - Temporary address for AhciPeiMmioBase
+  The reference code will use this as Temporary address space
+**/
+  UINT32                      AhciPeiMmioBase;
+
+/** Offset 0x09E4 - Temporary address for AhciPeiMmioLimit
+  The reference code will use this as Temporary address space
+**/
+  UINT32                      AhciPeiMmioLimit;
+
+/** Offset 0x09E8 - Temporary address for EcExtraIoBase
+  The reference code will use this as Temporary address space
+**/
+  UINT16                      EcExtraIoBase;
+
+/** Offset 0x09EA - Temporary address for SioBaseAddress
+  The reference code will use this as Temporary address space
+**/
+  UINT16                      SioBaseAddress;
+
+/** Offset 0x09EC - Temporary CfgBar address for VMD
+  The reference code will use this as Temporary address space
+**/
+  UINT32                      VmdCfgBarBar;
+
+/** Offset 0x09F0 - System Agent SafBar
+  Address of System Agent SafBar
+**/
+  UINT64                      SafBar;
 
 /** Offset 0x09F8 - Enable above 4GB MMIO resource support
   Enable/disable above 4GB MMIO resource support
@@ -2593,7 +3825,20 @@ typedef struct {
 
 /** Offset 0x09FA - Reserved
 **/
-  UINT8                       Reserved77[10];
+  UINT8                       Reserved37[2];
+
+/** Offset 0x09FC - StreamTracer Mode
+  Disable: Disable StreamTracer, Advanced Tracing: StreamTracer size 512MB - Recommended
+  when all groups in high verbosity are traced in 'red', Auto: StreamTracer size
+  8MB - Recommended when using up to 8 groups red or up to 16 groups in green in
+  med verbosity, User input: Allow User to enter a size in the range of 64KB-512MB
+  0: Disable (Default), 524288: Advanced Tracing , 8192: Auto , 3: User input
+**/
+  UINT32                      StreamTracerMode;
+
+/** Offset 0x0A00
+**/
+  UINT32                      StreamTracerSize;
 
 /** Offset 0x0A04 - Enable/Disable CrashLog Device
   Enable or Disable CrashLog/Telemetry Device  0- Disable, <b>1- Enable</b>
@@ -2601,9 +3846,39 @@ typedef struct {
 **/
   UINT32                      CpuCrashLogDevice;
 
-/** Offset 0x0A08 - Reserved
+/** Offset 0x0A08 - StreamTracer physical address
+  StreamTracer physical address
 **/
-  UINT8                      Reserved78[20];
+  UINT64                      StreamTracerBase;
+
+/** Offset 0x0A10 - Temporary MemBar1 address for VMD
+  StreamTracer physical address
+**/
+  UINT32                      VmdMemBar1Bar;
+
+/** Offset 0x0A14 - Temporary MemBar2 address for VMD
+  StreamTracer physical address
+**/
+  UINT32                      VmdMemBar2Bar;
+
+/** Offset 0x0A18 - Skip override boot mode When Fw Update.
+  When set to TRUE and boot mode is BOOT_ON_FLASH_UPDATE, skip setting boot mode to
+  BOOT_WITH_FULL_CONFIGURATION in PEI memory init.
+  $EN_DIS
+**/
+  UINT8                       SiSkipOverrideBootModeWhenFwUpdate;
+
+/** Offset 0x0A19 - Reserved
+**/
+  UINT8                       Reserved38;
+
+/** Offset 0x0A1A - Static Content at 4GB Location
+  0 (Default): No Allocation, 0x20:32MB, 0x40:64MB, 0x80:128MB, 0x100:256MB, 0x200:512MB,
+  0x400:1GB, 0x800:2GB, 0xC00:3GB, 0x1000:4GB, 0x2000:8GB
+  0: No Allocation, 0x20:32MB, 0x40:64MB, 0x80:128MB, 0x100:256MB, 0x200:512MB, 0x400:1GB,
+  0x800:2GB, 0xC00:3GB, 0x1000:4GB, 0x2000:8GB
+**/
+  UINT16                      StaticContentSizeAt4Gb;
 
 /** Offset 0x0A1C - Platform Debug Option
   Enabled Trace active: TraceHub is enabled and trace is active, blocks s0ix.\n
@@ -2618,9 +3893,14 @@ typedef struct {
 **/
   UINT8                       PlatformDebugOption;
 
-/** Offset 0x0A1D - Reserved
+/** Offset 0x0A1D - TXT CMOS Offset
+  CMOS Offset for TXT policy data. Default 0x2A
 **/
-  UINT8                       Reserved79[14];
+  UINT8                       CmosTxtOffset;
+
+/** Offset 0x0A1E - Reserved
+**/
+  UINT8                       Reserved39[13];
 
 /** Offset 0x0A2B - Program GPIOs for LFP on DDI port-A device
   0=Disabled,1(Default)=eDP, 2=MIPI DSI
@@ -2628,9 +3908,10 @@ typedef struct {
 **/
   UINT8                       DdiPortAConfig;
 
-/** Offset 0x0A2C - Reserved
+/** Offset 0x0A2C - HgSubSystemId
+  Hybrid Graphics SubSystemId
 **/
-  UINT8                      Reserved80[2];
+  UINT16                      HgSubSystemId;
 
 /** Offset 0x0A2E - Program GPIOs for LFP on DDI port-B device
   0(Default)=Disabled,1=eDP, 2=MIPI DSI
@@ -2722,9 +4003,15 @@ typedef struct {
 **/
   UINT8                       DdiPort4Ddc;
 
-/** Offset 0x0A3D - Reserved
+/** Offset 0x0A3D - Oem T12 Dealy Override
+  Oem T12 Dealy Override. 0(Default)=Disable  1=Enable
+  $EN_DIS
 **/
-  UINT8                       Reserved81[3];
+  UINT8                       OemT12DelayOverride;
+
+/** Offset 0x0A3E - Reserved
+**/
+  UINT8                       Reserved40[2];
 
 /** Offset 0x0A40 - Temporary MMIO address for GMADR
   The reference code will use this as Temporary MMIO address space to access GMADR
@@ -2741,9 +4028,12 @@ typedef struct {
 **/
   UINT64                      GttMmAdr;
 
-/** Offset 0x0A50 - Reserved
+/** Offset 0x0A50 - Delta T12 Power Cycle Delay required in ms
+  Select the value for delay required. 0= No delay, 0xFFFF(Default) = Auto calculate
+  T12 Delay to max 500ms
+  0 : No Delay, 0xFFFF : Auto Calulate T12 Delay
 **/
-  UINT8                      Reserved82[2];
+  UINT16                      DeltaT12PowerCycleDelay;
 
 /** Offset 0x0A52 - Enable/Disable Memory Bandwidth Compression
   0=Disable, 1(Default)=Enable
@@ -2773,7 +4063,7 @@ typedef struct {
 
 /** Offset 0x0A56 - Reserved
 **/
-  UINT8                       Reserved83[2];
+  UINT8                       Reserved41[2];
 
 /** Offset 0x0A58 - Intel Graphics VBT (Video BIOS Table) Size
   Size of Internal Graphics VBT Image
@@ -2782,7 +4072,7 @@ typedef struct {
 
 /** Offset 0x0A5C - Reserved
 **/
-  UINT8                       Reserved84[4];
+  UINT8                       Reserved42[4];
 
 /** Offset 0x0A60 - Graphics Configuration Ptr
   Points to VBT
@@ -2804,7 +4094,8 @@ typedef struct {
   Initialise SOL Init, BIT0 - (0 : Disable VGA Support, 1 : Enable VGA Support),,
   BIT1 - (0 : VGA Text Mode 3, 1 : VGA Graphics Mode 12), BIT2 - (0 : VGA Exit Supported,
   1: NO VGA Exit), BIT3 - (0 : VGA Init During Display Init, 1 - VGA Init During
-  MRC Cold Boot), BIT4 - (0 : Enable Progress Bar, 1 : Disable Progress Bar)
+  MRC Cold Boot), BIT4 - (0 : Enable Progress Bar, 1 : Disable Progress Bar), BIT5
+  - (0 : VGA Mode 12 16 Color Support, 1 : VGA Mode 12 Monochrome Black and White Support)
   0:VGA Disable, 1:Mode 3 VGA, 2:Mode 12 VGA
 **/
   UINT8                       VgaInitControl;
@@ -2841,9 +4132,11 @@ typedef struct {
 **/
   UINT8                       TcssXhciEn;
 
-/** Offset 0x0A83 - Reserved
+/** Offset 0x0A83 - IomUsbCDpConfig
+  Set IomUsbCDpConfig expect 4 values from 0 to 3
+  0:Disabled, 1:IOM_DP, 2:IOM_HDMI, 3: IOM_EDP
 **/
-  UINT8                       Reserved85[4];
+  UINT8                       IomUsbCDpConfig[4];
 
 /** Offset 0x0A87 - TCSS Type C Port 0
   Set TCSS Type C Port 0 Type, Options are 0=DISABLE, 1=DP_ONLY, 2=NO_TBT, 3=NO_PCIE,
@@ -2873,9 +4166,11 @@ typedef struct {
 **/
   UINT8                       TcssPort3;
 
-/** Offset 0x0A8B - Reserved
+/** Offset 0x0A8B - TCSS Platform Configuration
+  Set TCSS Platform Configuration - Retimer Map, TCP0 - Bits[1:0], TCP1 - Bits[3:2],
+  TCP2 - Bits[5:4], TCP3 - Bits[7:6]; 0=Retimerless, 1=Retimer
 **/
-  UINT8                       Reserved86;
+  UINT8                       TcssPlatConf;
 
 /** Offset 0x0A8C - TypeC port GPIO setting
   GPIO Pin number for Type C Aux orientation setting, use the GpioPad that is defined
@@ -2941,9 +4236,11 @@ typedef struct {
 **/
   UINT8                       InternalGraphics;
 
-/** Offset 0x0AC9 - Reserved
+/** Offset 0x0AC9 - Asynchronous ODT
+  This option configures the Memory Controler Asynchronous ODT control
+  0:Enabled, 1:Disabled
 **/
-  UINT8                       Reserved87;
+  UINT8                       AsyncOdtDis;
 
 /** Offset 0x0ACA - DLL Weak Lock Support
   Enables/Disable DLL Weak Lock Support
@@ -2953,7 +4250,7 @@ typedef struct {
 
 /** Offset 0x0ACB - Reserved
 **/
-  UINT8                       Reserved88;
+  UINT8                       Reserved43;
 
 /** Offset 0x0ACC - Rx DQS Delay Comp Support
   Enables/Disable Rx DQS Delay Comp Support
@@ -2963,7 +4260,7 @@ typedef struct {
 
 /** Offset 0x0ACD - Reserved
 **/
-  UINT8                       Reserved89[2];
+  UINT8                       Reserved44[2];
 
 /** Offset 0x0ACF - Mrc Failure On Unsupported Dimm
   Enables/Disable Mrc Failure On Unsupported Dimm
@@ -2971,9 +4268,11 @@ typedef struct {
 **/
   UINT8                       MrcFailureOnUnsupportedDimm;
 
-/** Offset 0x0AD0 - Reserved
+/** Offset 0x0AD0 - Fore Single Rank config
+  Enables/Disable Fore Single Rank config
+  $EN_DIS
 **/
-  UINT8                      Reserved90[4];
+  UINT32                      ForceSingleRank;
 
 /** Offset 0x0AD4 - DynamicMemoryBoost
   Enable/Disable Dynamic Memory Boost Feature. Only valid if SpdProfileSelected is
@@ -2989,9 +4288,55 @@ typedef struct {
 **/
   UINT32                      RealtimeMemoryFrequency;
 
-/** Offset 0x0ADC - Reserved
+/** Offset 0x0ADC - SelfRefresh IdleTimer
+  SelfRefresh IdleTimer, Default is 256
 **/
-  UINT8                      Reserved91[9];
+  UINT16                      SrefCfgIdleTmr;
+
+/** Offset 0x0ADE - MC Register Offset
+  Apply user offsets to select MC registers(Def=Disable)
+  $EN_DIS
+**/
+  UINT8                       MCREGOFFSET;
+
+/** Offset 0x0ADF - CA Vref Ctl Offset
+  Offset to be applied to DDRDATA7CH1_CR_DDRCRVREFADJUST1.CAVref
+  0xF4:-12,0xF5:-11, 0xF6:-10, 0xF7:-9, 0xF8:-8, 0xF9:-7, 0xFA:-6, 0xFB:-5, 0xFC:-4,
+  0xFD:-3, 0xFE:-2, 0xFF:-1, 0:0, 1:+1, 2:+2, 3:+3, 4:+4, 5:+5, 6:+6, 7:+7, 8:+8,
+  9:+9, 10:+10, 11:+11, 12:+12
+**/
+  UINT8                       CAVrefCtlOffset;
+
+/** Offset 0x0AE0 - Clk PI Code Offset
+  Offset to be applied to DDRCLKCH0_CR_DDRCRCLKPICODE.PiSettingRank[0-3]
+  0xFA:-6, 0xFB:-5, 0xFC:-4, 0xFD:-3, 0xFE:-2, 0xFF:-1, 0:0, 1:+1, 2:+2, 3:+3, 4:+4,
+  5:+5, 6:+6
+**/
+  UINT8                       ClkPiCodeOffset;
+
+/** Offset 0x0AE1 - RcvEn Offset
+  Offset to be applied to DDRDATACH0_CR_DDRCRDATAOFFSETTRAIN.RcvEn
+  0xFD:-3, 0xFE:-2, 0xFF:-1, 0:0, 1:+1, 2:+2, 3:+3
+**/
+  UINT8                       RcvEnOffset;
+
+/** Offset 0x0AE2 - Rx Dqs Offset
+  Offset to be applied to DDRDATACHX_CR_DDRCRDATAOFFSETTRAIN.RxDqsOffset
+  0xFD:-3, 0xFE:-2, 0xFF:-1, 0:0, 1:+1, 2:+2, 3:+3
+**/
+  UINT8                       RxDqsOffset;
+
+/** Offset 0x0AE3 - Tx Dq Offset
+  Offset to be applied to DDRDATACH0_CR_DDRCRDATAOFFSETTRAIN.TxDqOffset
+  0xFD:-3, 0xFE:-2, 0xFF:-1, 0:0, 1:+1, 2:+2, 3:+3
+**/
+  UINT8                       TxDqOffset;
+
+/** Offset 0x0AE4 - Tx Dqs Offset
+  Offset to be applied to DDRDATACH0_CR_DDRCRDATAOFFSETTRAIN.TxDqsOffset
+  0xFD:-3, 0xFE:-2, 0xFF:-1, 0:0, 1:+1, 2:+2, 3:+3
+**/
+  UINT8                       TxDqsOffset;
 
 /** Offset 0x0AE5 - Vref Offset
   Offset to be applied to DDRDATACH0_CR_DDRCRDATAOFFSETTRAIN.VrefOffset
@@ -3000,9 +4345,15 @@ typedef struct {
 **/
   UINT8                       VrefOffset;
 
-/** Offset 0x0AE6 - Reserved
+/** Offset 0x0AE6 - Controller mask
+  Controller mask to apply on parameter offset
 **/
-  UINT8                       Reserved92[2];
+  UINT8                       CntrlrMask;
+
+/** Offset 0x0AE7 - Channel  mask
+  Channel  mask to apply on parameter offset
+**/
+  UINT8                       ChMask;
 
 /** Offset 0x0AE8 - tRRSG Delta
   Delay between Read-to-Read commands in the same Bank Group. 0 - Auto. Signed TAT
@@ -3116,9 +4467,158 @@ typedef struct {
 **/
   UINT8                       tRWDD;
 
-/** Offset 0x0AF8 - Reserved
+/** Offset 0x0AF8 - MRC Interpreter
+  Select CMOS location match of DD01 or Ctrl-Break key or force entry
+  0:CMOS, 1:Break, 2:Force
 **/
-  UINT8                       Reserved93[41];
+  UINT8                       Interpreter;
+
+/** Offset 0x0AF9 - ODT mode
+  ODT mode
+  0:Default, 1:Vtt, 2:Vddq, 3:Vss, 4:Max
+**/
+  UINT8                       IoOdtMode;
+
+/** Offset 0x0AFA - PerBankRefresh
+  Control of Per Bank Refresh feature for LPDDR DRAMs
+  $EN_DIS
+**/
+  UINT8                       PerBankRefresh;
+
+/** Offset 0x0AFB - Mimic WC display pattern in IPQ
+  Using for Disable/Enable Mimic WC display pattern in IPQ: 0:Disable, 1:Enable 1
+  ACT resources usage, 3:Enable 2 ACT resources usage, 3:Enable 3 ACT resources usage,0xf:
+  Enable 4 ACT resources usage
+  1:1, 3:3, 0xf:0xf, 0:Auto
+**/
+  UINT8                       MimicWcDisaplayInIpq;
+
+/** Offset 0x0AFC - Fake SAGV
+  Fake SAGV: 0:Disabled, 1:Enabled
+  $EN_DIS
+**/
+  UINT32                      FakeSagv;
+
+/** Offset 0x0B00 - Lock DPR register
+  Lock DPR register. <b>0: Platform POR </b>; 1: Enable; 2: Disable
+  0:Platform POR, 1: Enable, 2: Disable
+**/
+  UINT32                      DprLock;
+
+/** Offset 0x0B04 - Board Stack Up
+  Board Stack Up: <b>0=Typical</b>, 1=Freq Limited
+  0:Typical, 1:Freq Limited
+**/
+  UINT8                       BoardStackUp;
+
+/** Offset 0x0B05 - PPR ForceRepair
+  When Eanble, PPR will force repair some rows many times (90)
+  $EN_DIS
+**/
+  UINT8                       PprForceRepair;
+
+/** Offset 0x0B06 - PPR Repair Bank
+  Deprecated
+**/
+  UINT8                       PprRepairBank;
+
+/** Offset 0x0B07 - Board Topology
+  Board Topology: <b>0=Daisy Chain</b>, 1=Tee.
+  0:Daisy Chain, 1:Tee
+**/
+  UINT8                       BoardTopology;
+
+/** Offset 0x0B08 - SubCh Hash Interleaved Bit
+  Select the MC Enhanced Channel interleave bit, to set different address bit for
+  sub channel selection than bit-6
+  0:BIT6, 1:BIT7, 2:BIT8, 3:BIT9, 4:BIT10, 5:BIT11, 6:BIT12, 7:BIT13
+**/
+  UINT8                       SubChHashInterleaveBit;
+
+/** Offset 0x0B09 - Reserved
+**/
+  UINT8                       Reserved45;
+
+/** Offset 0x0B0A - SubCh Hash Mask
+  Set the BIT(s) to be included in the XOR function. NOTE BIT mask corresponds to
+  BITS [19:6] Default is 0x834
+**/
+  UINT16                      SubChHashMask;
+
+/** Offset 0x0B0C - Force CKD in Bypass Mode
+  Enable/Disable Force CKD in Bypass Mode
+  $EN_DIS
+**/
+  UINT8                       ForceCkdBypass;
+
+/** Offset 0x0B0D - Reserved
+**/
+  UINT8                       Reserved46[3];
+
+/** Offset 0x0B10 - Disable Zq
+  Enable/Disable Zq Calibration: 0:Enabled, 1:Disabled
+  $EN_DIS
+**/
+  UINT32                      DisableZq;
+
+/** Offset 0x0B14 - Replicate SAGV
+  Replicate SAGV: 0:Disabled, 1:Enabled
+  $EN_DIS
+**/
+  UINT32                      ReplicateSagv;
+
+/** Offset 0x0B18 - Adjust wck mode
+  Adjust wck mode: 0:safe mode, 1:manual mode, 2:dynamic mode, 3:Default
+  0:safe mode, 1:manual mode, 2:dynamic mode, 3:Default
+**/
+  UINT8                       AdjustWckMode;
+
+/** Offset 0x0B19 - Control MC/PMA telemetry
+  Control MC/PMA telemetry: 0: Default, 1: Enable, 2: Disable
+  0: Default, 1: Enable, 2: Disable
+**/
+  UINT8                       TelemetryControl;
+
+/** Offset 0x0B1A - PHclk\Qclk SPINE gating Control
+  PHclk\Qclk SPINE gating Control: 0:Disabled, 1:Enabled
+  $EN_DIS
+**/
+  UINT8                       SpineAndPhclkGateControl;
+
+/** Offset 0x0B1B - SpineGating per lpmode
+  SpineGatePerLpmode[0]:Lpmode0.5, SpineGatePerLpmode[1]:Lpmode2, SpineGatePerLpmode[2]:Lpmode3,
+  SpineGatePerLpmode[3]:Lpmode4
+**/
+  UINT8                       SpineGatePerLpmode;
+
+/** Offset 0x0B1C - PhClkGating control per lpmode
+  PhclkGatePerLpmode[0]:Lpmode0.5, PhclkGatePerLpmode[1]:Lpmode1, PhclkGatePerLpmode[2]:Lpmode2,
+  PhclkGatePerLpmode[3]:Lpmode3, PhclkGatePerLpmode[4]:Lpmode4
+**/
+  UINT8                       PhclkGatePerLpmode;
+
+/** Offset 0x0B1D - DFI Control after cold boot
+  Disable Switch DFI Control to MC after cold boot: 0(Default)=switch DFI to MC, 1=Keep
+  with PHY/MPTU
+  $EN_DIS
+**/
+  UINT8                       DisableSwitchDfiToMc;
+
+/** Offset 0x0B1E - Enable/Disable SmbusPostcode
+  Disable (Default): Postcode via Port80, Enable: Postcode via Smbus
+  $EN_DIS
+**/
+  UINT8                       SmbusPostCodeEnable;
+
+/** Offset 0x0B1F - SmbusPostcode Address
+  Slave address for Smbus postcode device
+**/
+  UINT8                       SmbusPostCodeAddress;
+
+/** Offset 0x0B20 - SmbusPostcode Command
+  Command value for Smbus postcode device
+**/
+  UINT8                       SmbusPostCodeCommand;
 
 /** Offset 0x0B21 - Channel to CKD QCK Mapping
   Specify Channel to CKD QCK Mapping for CH0D0/CH0D1/CH1D0&CH1D1
@@ -3130,9 +4630,16 @@ typedef struct {
 **/
   UINT8                       PhyClockToCkdDimm[8];
 
-/** Offset 0x0B31 - Reserved
+/** Offset 0x0B31 - CKD Address Table
+  Specify CKD Address table for all DIMMs
 **/
-  UINT8                       Reserved94[17];
+  UINT8                       CkdAddressTable[16];
+
+/** Offset 0x0B41 - Single VDD2 Rail
+  LP5x VDD2 rail: 0: Dual rail (E-DVFSC is possible), 1: Single rail(No E-DVFSC; VDD2L == VDD2H)
+  $EN_DIS
+**/
+  UINT8                       SingleVdd2Rail;
 
 /** Offset 0x0B42 - VDD2 Voltage
   Voltage is multiple of 5mV where 0 means Auto.
@@ -3156,7 +4663,7 @@ typedef struct {
 
 /** Offset 0x0B4A - Reserved
 **/
-  UINT8                       Reserved95[30];
+  UINT8                       Reserved47[30];
 } FSP_M_CONFIG;
 
 /** Fsp M UPD Configuration
diff --git a/src/vendorcode/intel/fsp/fsp2_0/wildcatlake/FspsUpd.h b/src/vendorcode/intel/fsp/fsp2_0/wildcatlake/FspsUpd.h
index ae0ffe29dd..051aa8c2de 100644
--- a/src/vendorcode/intel/fsp/fsp2_0/wildcatlake/FspsUpd.h
+++ b/src/vendorcode/intel/fsp/fsp2_0/wildcatlake/FspsUpd.h
@@ -1,6 +1,6 @@
 /** @file
 
-Copyright (c) 2025, Intel Corporation. All rights reserved.<BR>
+Copyright (c) 2026, Intel Corporation. All rights reserved.<BR>
 
 Redistribution and use in source and binary forms, with or without modification,
 are permitted provided that the following conditions are met:
@@ -104,9 +104,24 @@ typedef struct {
 **/
   UINT64                      BiosGuardModulePtr;
 
-/** Offset 0x0080 - Reserved
+/** Offset 0x0080 - EcProvisionEav
+  EcProvisionEav function pointer. \n
+  @code typedef EFI_STATUS (EFIAPI *EC_PROVISION_EAV) (IN UINT32 Eav, OUT UINT8
+  *ReturnValue); @endcode
 **/
-  UINT8                      Reserved1[17];
+  UINT64                      EcProvisionEav;
+
+/** Offset 0x0088 - EcBiosGuardCmdLock
+  EcBiosGuardCmdLock function pointer. \n
+  @code typedef EFI_STATUS (EFIAPI *EC_CMD_LOCK) (OUT UINT8 *ReturnValue); @endcode
+**/
+  UINT64                      EcBiosGuardCmdLock;
+
+/** Offset 0x0090 - PCH eSPI Host and Device BME enabled
+  PCH eSPI Host and Device BME enabled
+  $EN_DIS
+**/
+  UINT8                       PchEspiBmeHostDeviceEnabled;
 
 /** Offset 0x0091 - PCH eSPI Link Configuration Lock (SBLCL)
   Enable/Disable lock of communication through SET_CONFIG/GET_CONFIG to eSPI target
@@ -127,9 +142,27 @@ typedef struct {
 **/
   UINT8                       PchEspiLgmrEnable;
 
-/** Offset 0x0094 - Reserved
+/** Offset 0x0094 - PCH eSPI PmHAE
+  This option enables or disables espi lgmr
+  $EN_DIS
 **/
-  UINT8                       Reserved2[4];
+  UINT8                       PchEspiPmHAE;
+
+/** Offset 0x0095 - PCH eSPI HideNonFatalErrors
+  This option enables or disables espi lgmr
+  $EN_DIS
+**/
+  UINT8                       PchEspiHideNonFatalErrors;
+
+/** Offset 0x0096 - PCH eSPI NmiEnableCs1
+  Set this bit to enable eSPI NMI VW events to be processed by the SOC
+  $EN_DIS
+**/
+  UINT8                       PchEspiNmiEnableCs1;
+
+/** Offset 0x0097 - Reserved
+**/
+  UINT8                       Reserved1;
 
 /** Offset 0x0098 - CpuBistData
   Pointer CPU BIST Data
@@ -151,7 +184,16 @@ typedef struct {
 
 /** Offset 0x00A9 - Reserved
 **/
-  UINT8                       Reserved3[7];
+  UINT8                       Reserved2[3];
+
+/** Offset 0x00AC - StreamTracer Mode
+  Disable: Disable StreamTracer, Advanced Tracing: StreamTracer size 512MB - Recommended
+  when all groups in high verbosity are traced in 'red', Auto: StreamTracer size
+  8MB - Recommended when using up to 8 groups red or up to 16 groups in green in
+  med verbosity, User input: Allow User to enter a size in the range of 64KB-512MB
+  0: Disable (Default), 524288: Advanced Tracing , 8192: Auto , 3: User input
+**/
+  UINT32                      StreamTracerMode;
 
 /** Offset 0x00B0 - MicrocodeRegionBase
   Memory Base of Microcode Updates
@@ -192,9 +234,12 @@ typedef struct {
 **/
   UINT8                       AvxDisable;
 
-/** Offset 0x00C4 - Reserved
+/** Offset 0x00C4 - X2ApicEnable
+  Enable/Disable X2APIC Operating Mode. When this option is configured as 'Enabled',
+  'VT-d' option must be 'Enabled'.
+  $EN_DIS
 **/
-  UINT8                       Reserved4;
+  UINT8                       X2ApicEnable;
 
 /** Offset 0x00C5 - P-state ratios for max 16 version of custom P-state table
   P-state ratios for max 16 version of custom P-state table. This table is used for
@@ -287,9 +332,17 @@ typedef struct {
 **/
   UINT8                       PkgCStateLimit;
 
-/** Offset 0x00E1 - Reserved
+/** Offset 0x00E1 - ForcePr Demotion Algorithm configuration
+  ForcePr Demotion Algorithm configuration. 0: Disable;<b> 1: Enable</b>
+  0: Disable, 1: Enable
 **/
-  UINT8                       Reserved5[2];
+  UINT8                       ForcePrDemotion;
+
+/** Offset 0x00E2 - VrAlert Demotion Algorithm configuration
+  VrAlert Demotion Algorithm configuration. 0: Disable;<b> 1: Enable</b>
+  0: Disable, 1: Enable
+**/
+  UINT8                       VrAlertDemotion;
 
 /** Offset 0x00E3 - Interrupt Redirection Mode Select
   Interrupt Redirection Mode Select for Logical Interrupts. 0: Fixed priority; 1:
@@ -303,9 +356,12 @@ typedef struct {
 **/
   UINT8                       TurboMode;
 
-/** Offset 0x00E5 - Reserved
+/** Offset 0x00E5 - Power Floor PCIe Gen Downgrade
+  SoC can downgrade PCIe gen speed to lower SoC floor power (Default enabled).  0:
+  Disable: Reduction in PCIe gen speed will not be used by SoC., <b>1: Enable </b>
+  $EN_DIS
 **/
-  UINT8                       Reserved6;
+  UINT8                       PowerFloorPcieGenDowngrade;
 
 /** Offset 0x00E6 - P-state ratios for custom P-state table
   P-state ratios for custom P-state table. NumberOfEntries has valid range between
@@ -325,9 +381,12 @@ typedef struct {
 **/
   UINT8                       MaxRatio;
 
-/** Offset 0x0110 - Reserved
+/** Offset 0x0110 - Boot frequency
+  Select the performance state that the BIOS will set starting from reset vector.
+  0: Maximum battery performance. 1: Maximum non-turbo performance. <b>2: Turbo performance </b>
+  0:0, 1:1, 2:2
 **/
-  UINT8                       Reserved7;
+  UINT8                       BootFrequency;
 
 /** Offset 0x0111 - Turbo settings Lock
   Enable/Disable locking of Package Power Limit settings. When enabled, PACKAGE_POWER_LIMIT
@@ -337,9 +396,41 @@ typedef struct {
 **/
   UINT8                       TurboPowerLimitLock;
 
-/** Offset 0x0112 - Reserved
+/** Offset 0x0112 - FastMsrHwpReq
+  0: Disable; <b> 1: Enable;</b>
+  $EN_DIS
 **/
-  UINT8                       Reserved8[33];
+  UINT8                       EnableFastMsrHwpReq;
+
+/** Offset 0x0113 - Turbo Ratio Limit Ratio array
+  Performance-core Turbo Ratio Limit Ratio0-7 (TRLR) defines the turbo ratio (max
+  is 85 in normal mode and 120 in core extension mode). Ratio[0]: This Turbo Ratio
+  Limit Ratio0 must be greater than or equal all other ratio values. If this value
+  is invalid, thn set all other active cores to minimum. Otherwise, align the Ratio
+  Limit to 0. Please check each active cores. Ratio[1~7]: This Turbo Ratio Limit
+  Ratio1 must be <= to Turbo Ratio Limit Ratio0~6.
+**/
+  UINT8                       TurboRatioLimitRatio[8];
+
+/** Offset 0x011B - Turbo Ratio Limit Num Core array
+  Performance-core Turbo Ratio Limit Core0~7 defines the core range, the turbo ratio
+  is defined in Turbo Ratio Limit Ratio0~7. If value is zero, this entry is ignored.
+**/
+  UINT8                       TurboRatioLimitNumCore[8];
+
+/** Offset 0x0123 - ATOM Turbo Ratio Limit Ratio array
+  Efficient-core Turbo Ratio Limit Ratio0-7 defines the turbo ratio (max is 85 irrespective
+  of the core extension mode), the core range is defined in E-core Turbo Ratio Limit
+  CoreCount0-7.
+**/
+  UINT8                       AtomTurboRatioLimitRatio[8];
+
+/** Offset 0x012B - ATOM Turbo Ratio Limit Num Core array
+  Efficient-core Turbo Ratio Limit CoreCount0-7 defines the core range, the turbo
+  ratio is defined in E-core Turbo Ratio Limit Ratio0-7. If value is zero, this entry
+  is ignored.
+**/
+  UINT8                       AtomTurboRatioLimitNumCore[8];
 
 /** Offset 0x0133 - Race To Halt
   Enable/Disable Race To Halt feature. RTH will dynamically increase CPU frequency
@@ -373,9 +464,11 @@ typedef struct {
 **/
   UINT8                       MaxRingRatioLimit;
 
-/** Offset 0x0138 - Reserved
+/** Offset 0x0138 - Resource Priority Feature
+  Enable/Disable Resource Priority Feature. Enable/Disable; 0: Disable, <b>1: Enable </b>
+  $EN_DIS
 **/
-  UINT8                       Reserved9;
+  UINT8                       EnableRp;
 
 /** Offset 0x0139 - Enable or Disable HWP
   Enable/Disable Intel(R) Speed Shift Technology support. Enabling will expose the
@@ -406,9 +499,42 @@ typedef struct {
 **/
   UINT8                       EnableHwpAutoEppGrouping;
 
-/** Offset 0x013D - Reserved
+/** Offset 0x013D - Dynamic Efficiency Control
+  Enable or Disable SoC to control energy efficiency targets autonomously, regardless
+  of EPP, EPB and other SW inputs. 0: Disable; </b>1: Enable <b>
+  $EN_DIS
 **/
-  UINT8                       Reserved10[5];
+  UINT8                       EnableDynamicEfficiencyControl;
+
+/** Offset 0x013E - Misc Power Management MSR Lock
+  Enable/Disable HWP Lock support in Misc Power Management MSR. 0: Disable, <b>1:
+  Enable </b>
+  $EN_DIS
+**/
+  UINT8                       HwpLock;
+
+/** Offset 0x013F - Power Floor Managment for SOC
+  Option to disable Power Floor Managment for SOC. Disabling this might effectively
+  raise power floor of the SoC and may lead to stability issues. 0: Disable, <b>1:
+  Enable </b>
+  $EN_DIS
+**/
+  UINT8                       PowerFloorManagement;
+
+/** Offset 0x0140 - Power Floor Disaplay Disconnect
+  SoC can disconnect secondary/external display to lower SoC floor power (Default
+  disabled).  0: Disable: Display disconnect will not be used by SoC., </b>1: Enable <b>
+  $EN_DIS
+**/
+  UINT8                       PowerFloorDisplayDisconnect;
+
+/** Offset 0x0141 - Memory size per thread allocated for Processor Trace
+  Memory size per thread for Processor Trace. Processor Trace requires 2^N alignment
+  and size in bytes per thread, from 4KB to 128MB.\n
+  <b> 0xff:none </b>, 0:4k, 0x1:8k, 0x2:16k, 0x3:32k, 0x4:64k, 0x5:128k, 0x6:256k,
+  0x7:512k, 0x8:1M, 0x9:2M, 0xa:4M. 0xb:8M, 0xc:16M, 0xd:32M, 0xe:64M, 0xf:128M
+**/
+  UINT8                       ProcessorTraceMemSize;
 
 /** Offset 0x0142 - Enable or Disable MLC Streamer Prefetcher
   Enable or Disable MLC Streamer Prefetcher; 0: Disable; <b>1: Enable</b>.
@@ -447,9 +573,25 @@ typedef struct {
 **/
   UINT8                       ProcessorTraceEnable;
 
-/** Offset 0x0148 - Reserved
+/** Offset 0x0148 - Processor trace enabled for Bsp only or all cores
+  Processor trace enabled for Bsp only or all cores; <b>0: all cores</b>; 1: Bsp only.
+  0: all cores, 1: Bsp only
 **/
-  UINT8                       Reserved11[3];
+  UINT8                       ProcessorTraceBspOnly;
+
+/** Offset 0x0149 - Enable/Disable processor trace Timing Packet
+  Enable/Disable collocting processor trace performance (CYC, TSC); <b>0: Disable</b>;
+  1: Enable.
+  $EN_DIS
+**/
+  UINT8                       ProcessorTraceTimingPacket;
+
+/** Offset 0x014A - Enable or Disable Three Strike Counter
+  Enable (default): Three Strike counter will be incremented. Disable: Prevents Three
+  Strike counter from incrementing; 0: Disable; <b>1: Enable</b>
+  $EN_DIS
+**/
+  UINT8                       ThreeStrikeCounter;
 
 /** Offset 0x014B - UFS enable/disable
   Enable/Disable UFS controller, One byte for each Controller - (1,0) to enable controller
@@ -466,9 +608,12 @@ typedef struct {
 **/
   UINT8                       UfsInlineEncryption[2];
 
-/** Offset 0x014F - Reserved
+/** Offset 0x014F - UFS Connection Status
+  UFS Connection Status, One byte for each Controller - (1,0) to UFS connected to
+  controller 0 and (0,1) to UFS connected to controller 1
+  $EN_DIS
 **/
-  UINT8                       Reserved12[2];
+  UINT8                       UfsDeviceConnected[2];
 
 /** Offset 0x0151 - Enable/Disable PCIe tunneling for USB4
   Enable/Disable PCIe tunneling for USB4, default is enable
@@ -478,7 +623,7 @@ typedef struct {
 
 /** Offset 0x0152 - Reserved
 **/
-  UINT8                       Reserved13[2];
+  UINT8                       Reserved3[2];
 
 /** Offset 0x0154 - ITBTForcePowerOn Timeout value
   ITBTForcePowerOn value. Specified increment values in miliseconds. Range is 0-1000.
@@ -504,7 +649,12 @@ typedef struct {
 
 /** Offset 0x015D - Reserved
 **/
-  UINT8                       Reserved14[19];
+  UINT8                       Reserved4[11];
+
+/** Offset 0x0168 - FSPS Validation
+  Point to FSPS Validation configuration structure
+**/
+  UINT64                      FspsValidationPtr;
 
 /** Offset 0x0170 - IEH Mode
   Integrated Error Handler Mode, 0: Bypass, 1: Enable
@@ -563,7 +713,7 @@ typedef struct {
 
 /** Offset 0x017B - Reserved
 **/
-  UINT8                       Reserved15;
+  UINT8                       Reserved5;
 
 /** Offset 0x017C - ISH GP GPIO Pin Muxing
   Determines ISH GP GPIO Pin muxing. See GPIO_*_MUXING_ISH_GP_x_GPIO_*. 'x' are GP_NUMBER
@@ -746,9 +896,11 @@ typedef struct {
 **/
   UINT8                       PchIshPdtUnlock;
 
-/** Offset 0x025C - Reserved
+/** Offset 0x025C - PCH ISH MSI Interrupts
+  0: False; 1: True.
+  $EN_DIS
 **/
-  UINT8                       Reserved16;
+  UINT8                       PchIshMsiInterrupt;
 
 /** Offset 0x025D - End of Post message
   Test, Send End of Post message. Disable(0x0): Disable EOP message, Send in PEI(0x1):
@@ -778,9 +930,44 @@ typedef struct {
 **/
   UINT8                       MeUnconfigOnRtcClear;
 
-/** Offset 0x0261 - Reserved
+/** Offset 0x0261 - CSE Data Resilience Support
+  0: Disable CSE Data Resilience Support. <b>1: Enable CSE Data Resilience Support.</b>
+  2: Enable CSE Data Resilience but defer to DXE.
+  $EN_DIS
 **/
-  UINT8                       Reserved17[22];
+  UINT8                       CseDataResilience;
+
+/** Offset 0x0262 - PSE EOM Flow Control
+  0: Disable PSE EOM Flow. <b>1: Enable PSE EOM Flow.</b>
+  $EN_DIS
+**/
+  UINT8                       PseEomFlowEnable;
+
+/** Offset 0x0263 - ISH I3C SDA Pin Muxing
+  Select ISH I3C SDA Pin muxing. Refer to GPIO_*_MUXING_ISH_I3Cx_SDA_* for possible values.
+**/
+  UINT8                       IshI3cSdaPinMuxing[8];
+
+/** Offset 0x026B - ISH I3C SCL Pin Muxing
+  Select ISH I3C SCL Pin muxing. Refer to GPIO_*_MUXING_ISH_I3Cx_SCL_* for possible values.
+**/
+  UINT8                       IshI3cSclPinMuxing[8];
+
+/** Offset 0x0273 - ISH I3C SDA Pad termination
+  0x0: Hardware default, 0x1: None, 0x13: 1kOhm weak pull-up, 0x15: 5kOhm weak pull-up,
+  0x19: 20kOhm weak pull-up - Enable/disable SerialIo I2C#N Sda pads termination
+  respectively. #N-byte for each controller, byte0 for I2C0 Sda, byte1 for I2C1 Sda,
+  and so on.
+**/
+  UINT8                       IshI3cSdaPadTermination[2];
+
+/** Offset 0x0275 - ISH I3C SCL Pad termination
+  0x0: Hardware default, 0x1: None, 0x13: 1kOhm weak pull-up, 0x15: 5kOhm weak pull-up,
+  0x19: 20kOhm weak pull-up - Enable/disable SerialIo I2C#N Scl pads termination
+  respectively. #N-byte for each controller, byte0 for I2C0 Scl, byte1 for I2C1 Scl,
+  and so on.
+**/
+  UINT8                       IshI3cSclPadTermination[2];
 
 /** Offset 0x0277 - Enable PCH ISH I3C pins assigned
   Set if ISH I3C native pins are to be enabled by BIOS. 0: Disable; 1: Enable.
@@ -789,7 +976,7 @@ typedef struct {
 
 /** Offset 0x0279 - Reserved
 **/
-  UINT8                       Reserved18[3];
+  UINT8                       Reserved6[3];
 
 /** Offset 0x027C - Power button debounce configuration
   Debounce time for PWRBTN in microseconds. For values not supported by HW, they will
@@ -972,9 +1159,11 @@ typedef struct {
 **/
   UINT8                       PmcLpmS0ixSubStateEnableMask;
 
-/** Offset 0x029C - Reserved
+/** Offset 0x029C - PCH PMC ER Debug mode
+  Disable/Enable Energy Reporting Debug Mode.
+  $EN_DIS
 **/
-  UINT8                       Reserved19;
+  UINT8                       PchPmErDebugMode;
 
 /** Offset 0x029D - PMC C10 dynamic threshold dajustment enable
   Set if you want to enable PMC C10 dynamic threshold adjustment. Only works on supported SKUs
@@ -1143,9 +1332,11 @@ typedef struct {
 **/
   UINT8                       PcieRpAspm[28];
 
-/** Offset 0x053C - Reserved
+/** Offset 0x053C - HostL0sTxDis
+  Disable Host L0 transmission state
+  $EN_DIS
 **/
-  UINT8                       Reserved20[28];
+  UINT8                       HostL0sTxDis[28];
 
 /** Offset 0x0558 - PCIE RP L1 Substates
   The L1 Substates configuration of the root port (see: PCH_PCIE_L1SUBSTATES_CONTROL).
@@ -1169,9 +1360,677 @@ typedef struct {
 **/
   UINT8                       PcieEqOverrideDefault[12];
 
-/** Offset 0x05B8 - Reserved
+/** Offset 0x05B8 - PCIE RP choose EQ method
+  Choose PCIe EQ method
+  0: HardwareEq, 1: FixedEq
 **/
-  UINT8                       Reserved21[1525];
+  UINT8                       PcieGen3EqMethod[12];
+
+/** Offset 0x05C4 - PCIE RP choose EQ mode
+  Choose PCIe EQ mode
+  0: PresetEq, 1: CoefficientEq
+**/
+  UINT8                       PcieGen3EqMode[12];
+
+/** Offset 0x05D0 - PCIE RP EQ local transmitter override
+  Enable/Disable local transmitter override
+  $EN_DIS
+**/
+  UINT8                       PcieGen3EqLocalTxOverrideEn[12];
+
+/** Offset 0x05DC - PCI RP number of valid list entries
+  Select number of presets or coefficients depending on the mode
+**/
+  UINT8                       PcieGen3EqPh3NoOfPresetOrCoeff[12];
+
+/** Offset 0x05E8 - PCIE RP pre-cursor coefficient list
+  Provide a list of pre-cursor coefficients to be used during phase 3 EQ
+**/
+  UINT8                       PcieGen3EqPh3PreCursor0List[12];
+
+/** Offset 0x05F4 - PCIE RP post-cursor coefficient list
+  Provide a list of post-cursor coefficients to be used during phase 3 EQ
+**/
+  UINT8                       PcieGen3EqPh3PostCursor0List[12];
+
+/** Offset 0x0600 - PCIE RP pre-cursor coefficient list
+  Provide a list of pre-cursor coefficients to be used during phase 3 EQ
+**/
+  UINT8                       PcieGen3EqPh3PreCursor1List[12];
+
+/** Offset 0x060C - PCIE RP post-cursor coefficient list
+  Provide a list of post-cursor coefficients to be used during phase 3 EQ
+**/
+  UINT8                       PcieGen3EqPh3PostCursor1List[12];
+
+/** Offset 0x0618 - PCIE RP pre-cursor coefficient list
+  Provide a list of pre-cursor coefficients to be used during phase 3 EQ
+**/
+  UINT8                       PcieGen3EqPh3PreCursor2List[12];
+
+/** Offset 0x0624 - PCIE RP post-cursor coefficient list
+  Provide a list of post-cursor coefficients to be used during phase 3 EQ
+**/
+  UINT8                       PcieGen3EqPh3PostCursor2List[12];
+
+/** Offset 0x0630 - PCIR RP pre-cursor coefficient list
+  Provide a list of pre-cursor coefficients to be used during phase 3 EQ
+**/
+  UINT8                       PcieGen3EqPh3PreCursor3List[12];
+
+/** Offset 0x063C - PCIE RP post-cursor coefficient list
+  Provide a list of post-cursor coefficients to be used during phase 3 EQ
+**/
+  UINT8                       PcieGen3EqPh3PostCursor3List[12];
+
+/** Offset 0x0648 - PCIE RP pre-cursor coefficient list
+  Provide a list of pre-cursor coefficients to be used during phase 3 EQ
+**/
+  UINT8                       PcieGen3EqPh3PreCursor4List[12];
+
+/** Offset 0x0654 - PCIE RP post-cursor coefficient list
+  Provide a list of post-cursor coefficients to be used during phase 3 EQ
+**/
+  UINT8                       PcieGen3EqPh3PostCursor4List[12];
+
+/** Offset 0x0660 - PCIE RP pre-cursor coefficient list
+  Provide a list of pre-cursor coefficients to be used during phase 3 EQ
+**/
+  UINT8                       PcieGen3EqPh3PreCursor5List[12];
+
+/** Offset 0x066C - PCIE RP post-cursor coefficient list
+  Provide a list of post-cursor coefficients to be used during phase 3 EQ
+**/
+  UINT8                       PcieGen3EqPh3PostCursor5List[12];
+
+/** Offset 0x0678 - PCIE RP pre-cursor coefficient list
+  Provide a list of pre-cursor coefficients to be used during phase 3 EQ
+**/
+  UINT8                       PcieGen3EqPh3PreCursor6List[12];
+
+/** Offset 0x0684 - PCIe post-cursor coefficient list
+  Provide a list of post-cursor coefficients to be used during phase 3 EQ
+**/
+  UINT8                       PcieGen3EqPh3PostCursor6List[12];
+
+/** Offset 0x0690 - PCIE RP pre-cursor coefficient list
+  Provide a list of pre-cursor coefficients to be used during phase 3 EQ
+**/
+  UINT8                       PcieGen3EqPh3PreCursor7List[12];
+
+/** Offset 0x069C - PCIE RP post-cursor coefficient list
+  Provide a list of post-cursor coefficients to be used during phase 3 EQ
+**/
+  UINT8                       PcieGen3EqPh3PostCursor7List[12];
+
+/** Offset 0x06A8 - PCIE RP pre-cursor coefficient list
+  Provide a list of pre-cursor coefficients to be used during phase 3 EQ
+**/
+  UINT8                       PcieGen3EqPh3PreCursor8List[12];
+
+/** Offset 0x06B4 - PCIE RP post-cursor coefficient list
+  Provide a list of post-cursor coefficients to be used during phase 3 EQ
+**/
+  UINT8                       PcieGen3EqPh3PostCursor8List[12];
+
+/** Offset 0x06C0 - PCIE RP pre-cursor coefficient list
+  Provide a list of pre-cursor coefficients to be used during phase 3 EQ
+**/
+  UINT8                       PcieGen3EqPh3PreCursor9List[12];
+
+/** Offset 0x06CC - PCIE RP post-cursor coefficient list
+  Provide a list of post-cursor coefficients to be used during phase 3 EQ
+**/
+  UINT8                       PcieGen3EqPh3PostCursor9List[12];
+
+/** Offset 0x06D8 - PCIE RP preset list
+  Provide a list of presets to be used during phase 3 EQ
+**/
+  UINT8                       PcieGen3EqPh3Preset0List[12];
+
+/** Offset 0x06E4 - PCIe preset list
+  Provide a list of presets to be used during phase 3 EQ
+**/
+  UINT8                       PcieGen3EqPh3Preset1List[12];
+
+/** Offset 0x06F0 - PCIE RP preset list
+  Provide a list of presets to be used during phase 3 EQ
+**/
+  UINT8                       PcieGen3EqPh3Preset2List[12];
+
+/** Offset 0x06FC - PCIE RP preset list
+  Provide a list of presets to be used during phase 3 EQ
+**/
+  UINT8                       PcieGen3EqPh3Preset3List[12];
+
+/** Offset 0x0708 - PCIE RP preset list
+  Provide a list of presets to be used during phase 3 EQ
+**/
+  UINT8                       PcieGen3EqPh3Preset4List[12];
+
+/** Offset 0x0714 - PCIE RP preset list
+  Provide a list of presets to be used during phase 3 EQ
+**/
+  UINT8                       PcieGen3EqPh3Preset5List[12];
+
+/** Offset 0x0720 - PCIE RP preset list
+  Provide a list of presets to be used during phase 3 EQ
+**/
+  UINT8                       PcieGen3EqPh3Preset6List[12];
+
+/** Offset 0x072C - PCIE RP preset list
+  Provide a list of presets to be used during phase 3 EQ
+**/
+  UINT8                       PcieGen3EqPh3Preset7List[12];
+
+/** Offset 0x0738 - PCIE RP preset list
+  Provide a list of presets to be used during phase 3 EQ
+**/
+  UINT8                       PcieGen3EqPh3Preset8List[12];
+
+/** Offset 0x0744 - PCIE RP preset list
+  Provide a list of presets to be used during phase 3 EQ
+**/
+  UINT8                       PcieGen3EqPh3Preset9List[12];
+
+/** Offset 0x0750 - PCIE RP preset list
+  Provide a list of presets to be used during phase 3 EQ
+**/
+  UINT8                       PcieGen3EqPh3Preset10List[12];
+
+/** Offset 0x075C - PCIe EQ phase 1 downstream transmitter port preset
+  Allows to select the downstream port preset value that will be used during phase
+  1 of equalization
+**/
+  UINT8                       PcieGen3EqPh1DpTxPreset[12];
+
+/** Offset 0x0768 - PCIE RP EQ phase 1 upstream tranmitter port preset
+  Allows to select the upstream port preset value that will be used during phase 1
+  of equalization
+**/
+  UINT8                       PcieGen3EqPh1UpTxPreset[12];
+
+/** Offset 0x0774 - PCIE RP EQ phase 2 local transmitter override preset
+  Allows to select the value of the preset used during phase 2 local transmitter override
+**/
+  UINT8                       PcieGen3EqPh2LocalTxOverridePreset[12];
+
+/** Offset 0x0780 - PCIE RP choose EQ method
+  Choose PCIe EQ method
+  0: HardwareEq, 1: FixedEq
+**/
+  UINT8                       PcieGen4EqMethod[12];
+
+/** Offset 0x078C - PCIE RP choose EQ mode
+  Choose PCIe EQ mode
+  0: PresetEq, 1: CoefficientEq
+**/
+  UINT8                       PcieGen4EqMode[12];
+
+/** Offset 0x0798 - PCIE RP EQ local transmitter override
+  Enable/Disable local transmitter override
+  $EN_DIS
+**/
+  UINT8                       PcieGen4EqLocalTxOverrideEn[12];
+
+/** Offset 0x07A4 - PCI RP number of valid list entries
+  Select number of presets or coefficients depending on the mode
+**/
+  UINT8                       PcieGen4EqPh3NoOfPresetOrCoeff[12];
+
+/** Offset 0x07B0 - PCIE RP pre-cursor coefficient list
+  Provide a list of pre-cursor coefficients to be used during phase 3 EQ
+**/
+  UINT8                       PcieGen4EqPh3PreCursor0List[12];
+
+/** Offset 0x07BC - PCIE RP post-cursor coefficient list
+  Provide a list of post-cursor coefficients to be used during phase 3 EQ
+**/
+  UINT8                       PcieGen4EqPh3PostCursor0List[12];
+
+/** Offset 0x07C8 - PCIE RP pre-cursor coefficient list
+  Provide a list of pre-cursor coefficients to be used during phase 3 EQ
+**/
+  UINT8                       PcieGen4EqPh3PreCursor1List[12];
+
+/** Offset 0x07D4 - PCIE RP post-cursor coefficient list
+  Provide a list of post-cursor coefficients to be used during phase 3 EQ
+**/
+  UINT8                       PcieGen4EqPh3PostCursor1List[12];
+
+/** Offset 0x07E0 - PCIE RP pre-cursor coefficient list
+  Provide a list of pre-cursor coefficients to be used during phase 3 EQ
+**/
+  UINT8                       PcieGen4EqPh3PreCursor2List[12];
+
+/** Offset 0x07EC - PCIE RP post-cursor coefficient list
+  Provide a list of post-cursor coefficients to be used during phase 3 EQ
+**/
+  UINT8                       PcieGen4EqPh3PostCursor2List[12];
+
+/** Offset 0x07F8 - PCIR RP pre-cursor coefficient list
+  Provide a list of pre-cursor coefficients to be used during phase 3 EQ
+**/
+  UINT8                       PcieGen4EqPh3PreCursor3List[12];
+
+/** Offset 0x0804 - PCIE RP post-cursor coefficient list
+  Provide a list of post-cursor coefficients to be used during phase 3 EQ
+**/
+  UINT8                       PcieGen4EqPh3PostCursor3List[12];
+
+/** Offset 0x0810 - PCIE RP pre-cursor coefficient list
+  Provide a list of pre-cursor coefficients to be used during phase 3 EQ
+**/
+  UINT8                       PcieGen4EqPh3PreCursor4List[12];
+
+/** Offset 0x081C - PCIE RP post-cursor coefficient list
+  Provide a list of post-cursor coefficients to be used during phase 3 EQ
+**/
+  UINT8                       PcieGen4EqPh3PostCursor4List[12];
+
+/** Offset 0x0828 - PCIE RP pre-cursor coefficient list
+  Provide a list of pre-cursor coefficients to be used during phase 3 EQ
+**/
+  UINT8                       PcieGen4EqPh3PreCursor5List[12];
+
+/** Offset 0x0834 - PCIE RP post-cursor coefficient list
+  Provide a list of post-cursor coefficients to be used during phase 3 EQ
+**/
+  UINT8                       PcieGen4EqPh3PostCursor5List[12];
+
+/** Offset 0x0840 - PCIE RP pre-cursor coefficient list
+  Provide a list of pre-cursor coefficients to be used during phase 3 EQ
+**/
+  UINT8                       PcieGen4EqPh3PreCursor6List[12];
+
+/** Offset 0x084C - PCIe post-cursor coefficient list
+  Provide a list of post-cursor coefficients to be used during phase 3 EQ
+**/
+  UINT8                       PcieGen4EqPh3PostCursor6List[12];
+
+/** Offset 0x0858 - PCIE RP pre-cursor coefficient list
+  Provide a list of pre-cursor coefficients to be used during phase 3 EQ
+**/
+  UINT8                       PcieGen4EqPh3PreCursor7List[12];
+
+/** Offset 0x0864 - PCIE RP post-cursor coefficient list
+  Provide a list of post-cursor coefficients to be used during phase 3 EQ
+**/
+  UINT8                       PcieGen4EqPh3PostCursor7List[12];
+
+/** Offset 0x0870 - PCIE RP pre-cursor coefficient list
+  Provide a list of pre-cursor coefficients to be used during phase 3 EQ
+**/
+  UINT8                       PcieGen4EqPh3PreCursor8List[12];
+
+/** Offset 0x087C - PCIE RP post-cursor coefficient list
+  Provide a list of post-cursor coefficients to be used during phase 3 EQ
+**/
+  UINT8                       PcieGen4EqPh3PostCursor8List[12];
+
+/** Offset 0x0888 - PCIE RP pre-cursor coefficient list
+  Provide a list of pre-cursor coefficients to be used during phase 3 EQ
+**/
+  UINT8                       PcieGen4EqPh3PreCursor9List[12];
+
+/** Offset 0x0894 - PCIE RP post-cursor coefficient list
+  Provide a list of post-cursor coefficients to be used during phase 3 EQ
+**/
+  UINT8                       PcieGen4EqPh3PostCursor9List[12];
+
+/** Offset 0x08A0 - PCIE RP preset list
+  Provide a list of presets to be used during phase 3 EQ
+**/
+  UINT8                       PcieGen4EqPh3Preset0List[12];
+
+/** Offset 0x08AC - PCIe preset list
+  Provide a list of presets to be used during phase 3 EQ
+**/
+  UINT8                       PcieGen4EqPh3Preset1List[12];
+
+/** Offset 0x08B8 - PCIE RP preset list
+  Provide a list of presets to be used during phase 3 EQ
+**/
+  UINT8                       PcieGen4EqPh3Preset2List[12];
+
+/** Offset 0x08C4 - PCIE RP preset list
+  Provide a list of presets to be used during phase 3 EQ
+**/
+  UINT8                       PcieGen4EqPh3Preset3List[12];
+
+/** Offset 0x08D0 - PCIE RP preset list
+  Provide a list of presets to be used during phase 3 EQ
+**/
+  UINT8                       PcieGen4EqPh3Preset4List[12];
+
+/** Offset 0x08DC - PCIE RP preset list
+  Provide a list of presets to be used during phase 3 EQ
+**/
+  UINT8                       PcieGen4EqPh3Preset5List[12];
+
+/** Offset 0x08E8 - PCIE RP preset list
+  Provide a list of presets to be used during phase 3 EQ
+**/
+  UINT8                       PcieGen4EqPh3Preset6List[12];
+
+/** Offset 0x08F4 - PCIE RP preset list
+  Provide a list of presets to be used during phase 3 EQ
+**/
+  UINT8                       PcieGen4EqPh3Preset7List[12];
+
+/** Offset 0x0900 - PCIE RP preset list
+  Provide a list of presets to be used during phase 3 EQ
+**/
+  UINT8                       PcieGen4EqPh3Preset8List[12];
+
+/** Offset 0x090C - PCIE RP preset list
+  Provide a list of presets to be used during phase 3 EQ
+**/
+  UINT8                       PcieGen4EqPh3Preset9List[12];
+
+/** Offset 0x0918 - PCIE RP preset list
+  Provide a list of presets to be used during phase 3 EQ
+**/
+  UINT8                       PcieGen4EqPh3Preset10List[12];
+
+/** Offset 0x0924 - PCIe EQ phase 1 downstream transmitter port preset
+  Allows to select the downstream port preset value that will be used during phase
+  1 of equalization
+**/
+  UINT8                       PcieGen4EqPh1DpTxPreset[12];
+
+/** Offset 0x0930 - PCIE RP EQ phase 1 upstream tranmitter port preset
+  Allows to select the upstream port preset value that will be used during phase 1
+  of equalization
+**/
+  UINT8                       PcieGen4EqPh1UpTxPreset[12];
+
+/** Offset 0x093C - PCIE RP EQ phase 2 local transmitter override preset
+  Allows to select the value of the preset used during phase 2 local transmitter override
+**/
+  UINT8                       PcieGen4EqPh2LocalTxOverridePreset[12];
+
+/** Offset 0x0948 - PCIE RP choose EQ method
+  Choose PCIe EQ method
+  0: HardwareEq, 1: FixedEq
+**/
+  UINT8                       PcieGen5EqMethod[12];
+
+/** Offset 0x0954 - PCIE RP choose EQ mode
+  Choose PCIe EQ mode
+  0: PresetEq, 1: CoefficientEq
+**/
+  UINT8                       PcieGen5EqMode[12];
+
+/** Offset 0x0960 - PCIE RP EQ local transmitter override
+  Enable/Disable local transmitter override
+  $EN_DIS
+**/
+  UINT8                       PcieGen5EqLocalTxOverrideEn[12];
+
+/** Offset 0x096C - PCI RP number of valid list entries
+  Select number of presets or coefficients depending on the mode
+**/
+  UINT8                       PcieGen5EqPh3NoOfPresetOrCoeff[12];
+
+/** Offset 0x0978 - PCIE RP pre-cursor coefficient list
+  Provide a list of pre-cursor coefficients to be used during phase 3 EQ
+**/
+  UINT8                       PcieGen5EqPh3PreCursor0List[12];
+
+/** Offset 0x0984 - PCIE RP post-cursor coefficient list
+  Provide a list of post-cursor coefficients to be used during phase 3 EQ
+**/
+  UINT8                       PcieGen5EqPh3PostCursor0List[12];
+
+/** Offset 0x0990 - PCIE RP pre-cursor coefficient list
+  Provide a list of pre-cursor coefficients to be used during phase 3 EQ
+**/
+  UINT8                       PcieGen5EqPh3PreCursor1List[12];
+
+/** Offset 0x099C - PCIE RP post-cursor coefficient list
+  Provide a list of post-cursor coefficients to be used during phase 3 EQ
+**/
+  UINT8                       PcieGen5EqPh3PostCursor1List[12];
+
+/** Offset 0x09A8 - PCIE RP pre-cursor coefficient list
+  Provide a list of pre-cursor coefficients to be used during phase 3 EQ
+**/
+  UINT8                       PcieGen5EqPh3PreCursor2List[12];
+
+/** Offset 0x09B4 - PCIE RP post-cursor coefficient list
+  Provide a list of post-cursor coefficients to be used during phase 3 EQ
+**/
+  UINT8                       PcieGen5EqPh3PostCursor2List[12];
+
+/** Offset 0x09C0 - PCIR RP pre-cursor coefficient list
+  Provide a list of pre-cursor coefficients to be used during phase 3 EQ
+**/
+  UINT8                       PcieGen5EqPh3PreCursor3List[12];
+
+/** Offset 0x09CC - PCIE RP post-cursor coefficient list
+  Provide a list of post-cursor coefficients to be used during phase 3 EQ
+**/
+  UINT8                       PcieGen5EqPh3PostCursor3List[12];
+
+/** Offset 0x09D8 - PCIE RP pre-cursor coefficient list
+  Provide a list of pre-cursor coefficients to be used during phase 3 EQ
+**/
+  UINT8                       PcieGen5EqPh3PreCursor4List[12];
+
+/** Offset 0x09E4 - PCIE RP post-cursor coefficient list
+  Provide a list of post-cursor coefficients to be used during phase 3 EQ
+**/
+  UINT8                       PcieGen5EqPh3PostCursor4List[12];
+
+/** Offset 0x09F0 - PCIE RP pre-cursor coefficient list
+  Provide a list of pre-cursor coefficients to be used during phase 3 EQ
+**/
+  UINT8                       PcieGen5EqPh3PreCursor5List[12];
+
+/** Offset 0x09FC - PCIE RP post-cursor coefficient list
+  Provide a list of post-cursor coefficients to be used during phase 3 EQ
+**/
+  UINT8                       PcieGen5EqPh3PostCursor5List[12];
+
+/** Offset 0x0A08 - PCIE RP pre-cursor coefficient list
+  Provide a list of pre-cursor coefficients to be used during phase 3 EQ
+**/
+  UINT8                       PcieGen5EqPh3PreCursor6List[12];
+
+/** Offset 0x0A14 - PCIe post-cursor coefficient list
+  Provide a list of post-cursor coefficients to be used during phase 3 EQ
+**/
+  UINT8                       PcieGen5EqPh3PostCursor6List[12];
+
+/** Offset 0x0A20 - PCIE RP pre-cursor coefficient list
+  Provide a list of pre-cursor coefficients to be used during phase 3 EQ
+**/
+  UINT8                       PcieGen5EqPh3PreCursor7List[12];
+
+/** Offset 0x0A2C - PCIE RP post-cursor coefficient list
+  Provide a list of post-cursor coefficients to be used during phase 3 EQ
+**/
+  UINT8                       PcieGen5EqPh3PostCursor7List[12];
+
+/** Offset 0x0A38 - PCIE RP pre-cursor coefficient list
+  Provide a list of pre-cursor coefficients to be used during phase 3 EQ
+**/
+  UINT8                       PcieGen5EqPh3PreCursor8List[12];
+
+/** Offset 0x0A44 - PCIE RP post-cursor coefficient list
+  Provide a list of post-cursor coefficients to be used during phase 3 EQ
+**/
+  UINT8                       PcieGen5EqPh3PostCursor8List[12];
+
+/** Offset 0x0A50 - PCIE RP pre-cursor coefficient list
+  Provide a list of pre-cursor coefficients to be used during phase 3 EQ
+**/
+  UINT8                       PcieGen5EqPh3PreCursor9List[12];
+
+/** Offset 0x0A5C - PCIE RP post-cursor coefficient list
+  Provide a list of post-cursor coefficients to be used during phase 3 EQ
+**/
+  UINT8                       PcieGen5EqPh3PostCursor9List[12];
+
+/** Offset 0x0A68 - PCIE RP preset list
+  Provide a list of presets to be used during phase 3 EQ
+**/
+  UINT8                       PcieGen5EqPh3Preset0List[12];
+
+/** Offset 0x0A74 - PCIe preset list
+  Provide a list of presets to be used during phase 3 EQ
+**/
+  UINT8                       PcieGen5EqPh3Preset1List[12];
+
+/** Offset 0x0A80 - PCIE RP preset list
+  Provide a list of presets to be used during phase 3 EQ
+**/
+  UINT8                       PcieGen5EqPh3Preset2List[12];
+
+/** Offset 0x0A8C - PCIE RP preset list
+  Provide a list of presets to be used during phase 3 EQ
+**/
+  UINT8                       PcieGen5EqPh3Preset3List[12];
+
+/** Offset 0x0A98 - PCIE RP preset list
+  Provide a list of presets to be used during phase 3 EQ
+**/
+  UINT8                       PcieGen5EqPh3Preset4List[12];
+
+/** Offset 0x0AA4 - PCIE RP preset list
+  Provide a list of presets to be used during phase 3 EQ
+**/
+  UINT8                       PcieGen5EqPh3Preset5List[12];
+
+/** Offset 0x0AB0 - PCIE RP preset list
+  Provide a list of presets to be used during phase 3 EQ
+**/
+  UINT8                       PcieGen5EqPh3Preset6List[12];
+
+/** Offset 0x0ABC - PCIE RP preset list
+  Provide a list of presets to be used during phase 3 EQ
+**/
+  UINT8                       PcieGen5EqPh3Preset7List[12];
+
+/** Offset 0x0AC8 - PCIE RP preset list
+  Provide a list of presets to be used during phase 3 EQ
+**/
+  UINT8                       PcieGen5EqPh3Preset8List[12];
+
+/** Offset 0x0AD4 - PCIE RP preset list
+  Provide a list of presets to be used during phase 3 EQ
+**/
+  UINT8                       PcieGen5EqPh3Preset9List[12];
+
+/** Offset 0x0AE0 - PCIE RP preset list
+  Provide a list of presets to be used during phase 3 EQ
+**/
+  UINT8                       PcieGen5EqPh3Preset10List[12];
+
+/** Offset 0x0AEC - PCIe EQ phase 1 downstream transmitter port preset
+  Allows to select the downstream port preset value that will be used during phase
+  1 of equalization
+**/
+  UINT8                       PcieGen5EqPh1DpTxPreset[12];
+
+/** Offset 0x0AF8 - PCIE RP EQ phase 1 upstream tranmitter port preset
+  Allows to select the upstream port preset value that will be used during phase 1
+  of equalization
+**/
+  UINT8                       PcieGen5EqPh1UpTxPreset[12];
+
+/** Offset 0x0B04 - PCIE RP EQ phase 2 local transmitter override preset
+  Allows to select the value of the preset used during phase 2 local transmitter override
+**/
+  UINT8                       PcieGen5EqPh2LocalTxOverridePreset[12];
+
+/** Offset 0x0B10 - Phase3 RP Gen3 EQ enable
+  Phase3 Gen3 EQ enable. Disabled(0x0)(Default): Disable phase 3, Enabled(0x1): Enable phase 3
+  0:Disable, 1:Enable, 2:Auto
+**/
+  UINT8                       PcieRpGen3EqPh3Bypass[12];
+
+/** Offset 0x0B1C - Phase3 RP Gen4 EQ enable
+  Phase3 Gen4 EQ enable. Disabled(0x0)(Default): Disable phase 3, Enabled(0x1): Enable phase 3
+  0:Disable, 1:Enable, 2:Auto
+**/
+  UINT8                       PcieRpGen4EqPh3Bypass[12];
+
+/** Offset 0x0B28 - Phase3 RP Gen5 EQ enable
+  Phase3 Gen5 EQ enable. Disabled(0x0)(Default): Disable phase 3, Enabled(0x1): Enable phase 3
+  0:Disable, 1:Enable, 2:Auto
+**/
+  UINT8                       PcieRpGen5EqPh3Bypass[12];
+
+/** Offset 0x0B34 - Phase2-3 RP Gen3 EQ enable
+  Phase2-3 Gen3 EQ enable. Disabled(0x0)(Default): Disable Phase2-3, Enabled(0x1):
+  Enable Phase2-3
+  0:Disable, 1:Enable, 2:Auto
+**/
+  UINT8                       PcieRpGen3EqPh23Bypass[12];
+
+/** Offset 0x0B40 - Phase2-3 RP Gen4 EQ enable
+  Phase2-3 Gen4 EQ enable. Disabled(0x0)(Default): Disable Phase2-3, Enabled(0x1):
+  Enable Phase2-3
+  0:Disable, 1:Enable, 2:Auto
+**/
+  UINT8                       PcieRpGen4EqPh23Bypass[12];
+
+/** Offset 0x0B4C - Phase2-3 RP Gen5 EQ enable
+  Phase2-3 Gen5 EQ enable. Disabled(0x0)(Default): Disable Phase2-3, Enabled(0x1):
+  Enable Phase2-3
+  0:Disable, 1:Enable, 2:Auto
+**/
+  UINT8                       PcieRpGen5EqPh23Bypass[12];
+
+/** Offset 0x0B58 - PCET Timer
+  Preset/Coefficient Evaluation Timeout Gen3 PCET Timer. See PCIE_GEN3_PCET. Default
+  is 0x0(2ms)
+**/
+  UINT8                       PcieGen3PcetTimer[12];
+
+/** Offset 0x0B64 - Gen4 PCET Timer
+  Preset/Coefficient Evaluation Timeout - Gen4 PCET Timer. See PCIE_GEN4_PCET. Default
+  is 0x0(2ms)
+**/
+  UINT8                       PcieGen4PcetTimer[12];
+
+/** Offset 0x0B70 - Gen5 PCET Timer
+  Preset/Coefficient Evaluation Timeout - Gen5 PCET Timer. See PCIE_GEN5_PCET. Default
+  is 0x0(2ms)
+**/
+  UINT8                       PcieGen5PcetTimer[12];
+
+/** Offset 0x0B7C - TS Lock Timer for Gen3
+  Training Sequence Wait Latency For Presets/Coefficients Evaluation - Gen3 TS Lock
+  Timer. See PCIE_GEN3_TS_LOCK_TIMER. Default is 0x0
+**/
+  UINT8                       PcieGen3TsLockTimer[12];
+
+/** Offset 0x0B88 - PTS Lock Timer for Gen4
+  Training Sequence Wait Latency For Presets/Coefficients Evaluation - Gen4 TS Lock
+  Timer. See PCIE_GEN4_TS_LCOK_TIMER. Default is 0x0
+**/
+  UINT8                       PcieGen4TsLockTimer[12];
+
+/** Offset 0x0B94 - PTS Lock Timer for Gen5
+  Training Sequence Wait Latency For Presets/Coefficients Evaluation - Gen5 TS Lock
+  Timer. See PCIE_GEN5_TS_LCOK_TIMER. Default is 0x0
+**/
+  UINT8                       PcieGen5TsLockTimer[12];
+
+/** Offset 0x0BA0 - PCIE Secure Register Lock
+  Describes whether Secure Register Lock is enaled or disabled. When it will be enbaled,
+  load PcieRpSetSecuredRegisterLock recipe. 0: Disable(Default); 1: Enable
+  $EN_DIS
+**/
+  UINT8                       PcieSetSecuredRegisterLock;
+
+/** Offset 0x0BA1 - Enable/Disable ASPM Optionality Compliance
+  Enable/Disable ASPM Optionality Compliance.
+**/
+  UINT8                       PcieRpTestAspmOc[12];
 
 /** Offset 0x0BAD - PCIE RP Enable Peer Memory Write
   This member describes whether Peer Memory Writes are enabled on the platform.
@@ -1199,9 +2058,12 @@ typedef struct {
 **/
   UINT8                       PcieRpFunctionSwap;
 
-/** Offset 0x0BC7 - Reserved
+/** Offset 0x0BC7 - PCIe RootPort Clock Gating
+  Describes whether the PCI Express Clock Gating for each root port is enabled by
+  platform modules. 0: Disable; 1: Enable(Default).
+  $EN_DIS
 **/
-  UINT8                       Reserved22[12];
+  UINT8                       PcieClockGating[12];
 
 /** Offset 0x0BD3 - PCIe RootPort Power Gating
   Describes whether the PCI Express Power Gating for each root port is enabled by
@@ -1210,9 +2072,36 @@ typedef struct {
 **/
   UINT8                       PciePowerGating[12];
 
-/** Offset 0x0BDF - Reserved
+/** Offset 0x0BDF - PCIe RootPort VISA Clock Gating
+  Describes whether the PCI Express VISA Clock Gating. 0: Disable; 1: Enable(Default).
+  $EN_DIS
 **/
-  UINT8                       Reserved23[49];
+  UINT8                       PcieVisaClockGating[12];
+
+/** Offset 0x0BEB - PCIe RootPort AutoPower Gating
+  Describes the Auto Power Gating for per controller. 0: Disable; 1: Enable(Default).
+  $EN_DIS
+**/
+  UINT8                       PcieAutoPowerGating[12];
+
+/** Offset 0x0BF7 - PCIe RootPort PHY AutoPower Gating
+  Describes the PHY Auto Power Gating for per controller. 0: Disable; 1: Enable(Default).
+  $EN_DIS
+**/
+  UINT8                       PciePhyAutoPowerGating;
+
+/** Offset 0x0BF8 - FOMS Control Policy
+  Choose the Foms Control Policy, <b>Default = 0 </b>
+  0: Auto, 1: Gen3 Foms, 2: Gen4 Foms, 3: Gen3 and Gen4 Foms
+**/
+  UINT8                       PcieFomsCp[12];
+
+/** Offset 0x0C04 - EqPhBypass Control Policy
+  PCIe Equalization Phase Enable Control, <b>Disabled</b>       (0x0) : Disable Phase
+  (Default), Enabled (0x1) : Enable Phase
+  0: Auto, 1: Gen3 Foms, 2: Gen4 Foms, 3: Gen3 and Gen4 Foms
+**/
+  UINT8                       PcieEqPhBypass[12];
 
 /** Offset 0x0C10 - PCIE RP Ltr Max Snoop Latency
   Latency Tolerance Reporting, Max Snoop Latency.
@@ -1276,9 +2165,34 @@ typedef struct {
 **/
   UINT8                       PchPciePort8xhDecodePortIndex;
 
-/** Offset 0x0D8E - Reserved
+/** Offset 0x0D8E - PCIE RP LTR Override Spec Compliant
+  Override LTR based on Ep capability.
 **/
-  UINT8                       Reserved24[114];
+  UINT8                       PcieRpLtrOverrideSpecCompliant[28];
+
+/** Offset 0x0DAA - PCIe AER _OSC Setting
+  Enable/Disable Global PCIe Advanced Error Reporting
+  0:Disable, 1:Enable
+**/
+  UINT8                       GlobalPcieAer;
+
+/** Offset 0x0DAB - PCIe TBT Performance Boost Bitmap
+  Bitmap of TBT performance boost enabled PCIe controllers to which discrete TBT controllers
+  connect. Bit0: PXPA, Bit1: PXPB, Bit2: PXPC, Bit3: PXPD, Bit4: PXPE
+**/
+  UINT8                       PcieTbtPerfBoost;
+
+/** Offset 0x0DAC - Serial IO SPI CLK Pin Muxing
+  Select SerialIo LPSS SPI CS pin muxing. Refer to GPIO_*_MUXING_SERIALIO_SPIx_CLK*
+  for possible values.
+**/
+  UINT32                      SerialIoLpssSpiClkPinMux[7];
+
+/** Offset 0x0DC8 - Serial IO SPI CS Pin Muxing
+  Select SerialIo  LPSS SPI CS pin muxing. Refer to GPIO_*_MUXING_SERIALIO_SPIx_CS*
+  for possible values.
+**/
+  UINT32                      SerialIoLpssSpiCsPinMux[14];
 
 /** Offset 0x0E00 - SPIn Device Mode
   Selects SPI operation mode. N represents controller index: SPI0, SPI1, ... Available
@@ -1288,7 +2202,27 @@ typedef struct {
 
 /** Offset 0x0E07 - Reserved
 **/
-  UINT8                       Reserved25[85];
+  UINT8                       Reserved7;
+
+/** Offset 0x0E08 - LPSS SPI MOSI Pin Muxing
+  Select LPSS SPI MOSI pin muxing. Refer to GPIO_*_MUXING_LPSS_SPIx_MOSI* for possible values.
+**/
+  UINT32                      SerialIoLpssSpiMosiPinMux[7];
+
+/** Offset 0x0E24 - LPSS SPI MISO Pin Muxing
+  Select Lpss SPI MISO pin muxing. Refer to GPIO_*_MUXING_LPSS_SPIx_MISO* for possible values.
+**/
+  UINT32                      SerialIoLpssSpiMisoPinMux[7];
+
+/** Offset 0x0E40 - SPI<N> Chip Select Polarity
+  Sets polarity for each chip Select. Available options: 0:LpssSpiCsActiveLow, 1:LpssSpiCsActiveHigh
+**/
+  UINT8                       SerialIoLpssSpiCsPolarity[14];
+
+/** Offset 0x0E4E - SPI<N> Chip Select Enable
+  0:Disabled, 1:Enabled. Enables GPIO for CS0 or CS1 if it is Enabled
+**/
+  UINT8                       SerialIoLpssSpiCsEnable[14];
 
 /** Offset 0x0E5C - SPIn Default Chip Select Mode HW/SW
   Sets Default CS Mode Hardware or Software. N represents controller index: SPI0,
@@ -1311,7 +2245,7 @@ typedef struct {
 
 /** Offset 0x0E71 - Reserved
 **/
-  UINT8                       Reserved26[3];
+  UINT8                       Reserved8[3];
 
 /** Offset 0x0E74 - Default BaudRate for each Serial IO UART
   Set default BaudRate Supported from 0 - default to 6000000
@@ -1351,7 +2285,7 @@ typedef struct {
 
 /** Offset 0x0EBA - Reserved
 **/
-  UINT8                       Reserved27[2];
+  UINT8                       Reserved9[2];
 
 /** Offset 0x0EBC - SerialIoUartRtsPinMuxPolicy
   Select SerialIo Uart Rts pin muxing. Refer to GPIO_*_MUXING_SERIALIO_UARTx_RTS*
@@ -1377,9 +2311,11 @@ typedef struct {
 **/
   UINT8                       SerialIoUartDbg2[7];
 
-/** Offset 0x0F17 - Reserved
+/** Offset 0x0F17 - Serial IO UART PG DBG2 table
+  Enable or disable Serial Io UART PG DBG2 table, default is Disable; <b>0: Disable;</b>
+  1: Enable.
 **/
-  UINT8                       Reserved28[7];
+  UINT8                       SerialIoUartPgDbg2[7];
 
 /** Offset 0x0F1E - I2Cn Device Mode
   Selects I2c operation mode. N represents controller index: I2c0, I2c1, ... Available
@@ -1389,7 +2325,7 @@ typedef struct {
 
 /** Offset 0x0F26 - Reserved
 **/
-  UINT8                       Reserved29[2];
+  UINT8                       Reserved10[2];
 
 /** Offset 0x0F28 - Serial IO I2C SDA Pin Muxing
   Select SerialIo I2c Sda pin muxing. Refer to GPIO_*_MUXING_SERIALIO_I2Cx_SDA* for
@@ -1418,7 +2354,54 @@ typedef struct {
 
 /** Offset 0x0F73 - Reserved
 **/
-  UINT8                       Reserved30[48];
+  UINT8                       Reserved11;
+
+/** Offset 0x0F74 - Serial IO I3C SDA Pin Muxing
+  Select SerialIo I3c Sda pin muxing. Refer to GPIO_*_MUXING_SERIALIO_I3Cx_SDA* for
+  possible values.
+**/
+  UINT32                      SerialIoI3cSdaPinMux[3];
+
+/** Offset 0x0F80 - Serial IO I3C SDA Pad Termination
+  0x0: Hardware default, 0x1: None, 0x13: 1kOhm weak pull-up, 0x15: 5kOhm weak pull-up,
+  0x19: 20kOhm weak pull-up - Enable/disable SerialIo I3C0,I3C1,... pads termination
+  respectively. One byte for each controller, byte0 for I3C0, byte1 for I3C1, and so on.
+**/
+  UINT8                       SerialIoI3cSdaPadTermination[3];
+
+/** Offset 0x0F83 - Reserved
+**/
+  UINT8                       Reserved12;
+
+/** Offset 0x0F84 - Serial IO I3C SCL Pin Muxing
+  Select SerialIo I3c Scl pin muxing. Refer to GPIO_*_MUXING_SERIALIO_I3Cx_SCL* for
+  possible values.
+**/
+  UINT32                      SerialIoI3cSclPinMux[3];
+
+/** Offset 0x0F90 - Serial IO I3C SCL Pad Termination
+  0x0: Hardware default, 0x1: None, 0x13: 1kOhm weak pull-up, 0x15: 5kOhm weak pull-up,
+  0x19: 20kOhm weak pull-up - Enable/disable SerialIo I3C0,I3C1,... pads termination
+  respectively. One byte for each controller, byte0 for I3C0, byte1 for I3C1, and so on.
+**/
+  UINT8                       SerialIoI3cSclPadTermination[3];
+
+/** Offset 0x0F93 - Reserved
+**/
+  UINT8                       Reserved13;
+
+/** Offset 0x0F94 - Serial IO I3C SCL FB Pin Muxing
+  Select SerialIo I3c SclFb pin muxing. Refer to GPIO_*_MUXING_SERIALIO_I3Cx_SCL FB*
+  for possible values.
+**/
+  UINT32                      SerialIoI3cSclFbPinMux[3];
+
+/** Offset 0x0FA0 - Serial IO I3C SCL FB Pad Termination
+  0x0: Hardware default, 0x1: None, 0x13: 1kOhm weak pull-up, 0x15: 5kOhm weak pull-up,
+  0x19: 20kOhm weak pull-up - Enable/disable SerialIo I3C0,I3C1,... pads termination
+  respectively. One byte for each controller, byte0 for I3C0, byte1 for I3C1, and so on.
+**/
+  UINT8                       SerialIoI3cSclFbPadTermination[3];
 
 /** Offset 0x0FA3 - Enable VMD controller
   Enable/disable to VMD controller.0: Disable; 1: Enable(Default)
@@ -1438,9 +2421,10 @@ typedef struct {
 **/
   UINT8                       VmdPort[31];
 
-/** Offset 0x0FC4 - Reserved
+/** Offset 0x0FC4 - VMD Port Bus
+  VMD Root port bus number.
 **/
-  UINT8                       Reserved31[31];
+  UINT8                       VmdPortBus[31];
 
 /** Offset 0x0FE3 - VMD Port Device
   VMD Root port device number.
@@ -1454,16 +2438,17 @@ typedef struct {
 
 /** Offset 0x1021 - Reserved
 **/
-  UINT8                       Reserved32[7];
+  UINT8                       Reserved14[7];
 
 /** Offset 0x1028 - VMD Variable
   VMD Variable Pointer.
 **/
   UINT64                      VmdVariablePtr;
 
-/** Offset 0x1030 - Reserved
+/** Offset 0x1030 - Temporary CfgBar address for VMD
+  VMD Variable Pointer.
 **/
-  UINT8                      Reserved33[4];
+  UINT32                      VmdCfgBarBase;
 
 /** Offset 0x1034 - Temporary MemBar1 address for VMD
   VMD Variable Pointer.
@@ -1481,9 +2466,15 @@ typedef struct {
 **/
   UINT8                       D3HotEnable;
 
-/** Offset 0x103D - Reserved
+/** Offset 0x103D - TCSS TBT Performance Boost Bitmap
+  Bitmap of TBT performance boost enabled TCSS PCIe root ports. Bit0: TCSS port0,
+  Bit1: TCSS port1, Bit2: TCSS port2, Bit3: TCSS port3
 **/
-  UINT8                       Reserved34[3];
+  UINT8                       TcssTbtPerfBoost;
+
+/** Offset 0x103E - Reserved
+**/
+  UINT8                       Reserved15[2];
 
 /** Offset 0x1040 - TypeC port GPIO setting
   GPIO Ping number for Type C Aux orientation setting, use the GpioPad that is defined
@@ -1508,9 +2499,17 @@ typedef struct {
 **/
   UINT8                       TcCstateLimit;
 
-/** Offset 0x107C - Reserved
+/** Offset 0x107C - TC Notify Igd
+  Tc Notify Igd
 **/
-  UINT8                       Reserved35[2];
+  UINT8                       TcNotifyIgd;
+
+/** Offset 0x107D - TCSS CPU USB PDO Programming
+  Enable/disable PDO programming for TCSS CPU USB in PEI phase. Disabling will allow
+  for programming during later phase. 1: enable, 0: disable
+  $EN_DIS
+**/
+  UINT8                       TcssCpuUsbPdoProgramming;
 
 /** Offset 0x107E - Enable/Disable PMC-PD Solution
   This policy will enable/disable PMC-PD Solution vs EC-TCPC Solution
@@ -1520,7 +2519,7 @@ typedef struct {
 
 /** Offset 0x107F - Reserved
 **/
-  UINT8                       Reserved36;
+  UINT8                       Reserved16;
 
 /** Offset 0x1080 - TCSS Aux Orientation Override Enable
   Bits 0, 2, ... 10 control override enables, bits 1, 3, ... 11 control overrides
@@ -1594,9 +2593,11 @@ typedef struct {
 **/
   UINT8                       SaPcieItbtRpLtrConfigLock[4];
 
-/** Offset 0x10B6 - Reserved
+/** Offset 0x10B6 - Type C Port x Convert to TypeA
+  Enable / Disable(default) Type C Port x Convert to TypeA
+  $EN_DIS
 **/
-  UINT8                       Reserved37[4];
+  UINT8                       EnableTcssCovTypeA[4];
 
 /** Offset 0x10BA - Touch Host Controller Assignment
   Assign THC 0x0:ThcAssignmentNone, 0x1:ThcAssignmentThc0, 0x2:ThcAssignmentThc1
@@ -1620,9 +2621,276 @@ typedef struct {
 **/
   UINT8                       ThcWakeOnTouch[2];
 
-/** Offset 0x10C8 - Reserved
+/** Offset 0x10C8 - Touch Host Controller Active Ltr
+  Expose Active Ltr for OS driver to set
 **/
-  UINT8                      Reserved38[337];
+  UINT32                      ThcActiveLtr[2];
+
+/** Offset 0x10D0 - Touch Host Controller Idle Ltr
+  Expose Idle Ltr for OS driver to set
+**/
+  UINT32                      ThcIdleLtr[2];
+
+/** Offset 0x10D8 - Touch Host Controller Timestamp timer behavior in D0i2
+  Timestamp timer behavior in D0i2. 1 = Timer resets to 0 when entering D0i2 0 = Timer
+  is paused instead of reset to 0 when entering D0i2
+**/
+  UINT8                       TimestampTimerMode[2];
+
+/** Offset 0x10DA - Reserved
+**/
+  UINT8                       Reserved17[2];
+
+/** Offset 0x10DC - Touch Host Controller Display Frame Sync Period
+  Period of the emulated display frame sync [ms] The minimum period is 2ms, maximum
+  period is 100ms
+**/
+  UINT32                      DisplayFrameSyncPeriod[2];
+
+/** Offset 0x10E4 - Touch Host Controller ResetPad
+  ResetPad
+**/
+  UINT32                      ThcResetPad[2];
+
+/** Offset 0x10EC - Touch Host Controller ResetPad Trigger
+  Hid Over Spi Reset Pad Trigger 0x0:Low, 0x1:High
+**/
+  UINT32                      ThcResetPadTrigger[2];
+
+/** Offset 0x10F4 - Touch Host Controller DYSync
+  Based on this setting GPIO for given THC will be in native mode
+**/
+  UINT8                       ThcDsyncPad[2];
+
+/** Offset 0x10F6 - Reserved
+**/
+  UINT8                       Reserved18[2];
+
+/** Offset 0x10F8 - Touch Host Controller Hid Over Spi Connection Speed
+  Hid Over Spi Connection Speed - SPI Frequency
+**/
+  UINT32                      ThcHidSpiConnectionSpeed[2];
+
+/** Offset 0x1100 - Touch Host Controller Hid Over Spi Limit PacketSize
+  When set, limits SPI read & write packet size to 64B. Otherwise, THC uses Max Soc
+  packet size for SPI Read and Write 0x0- Max Soc Packet Size,  0x11 - 64 Bytes
+**/
+  UINT32                      ThcHidSpiLimitPacketSize[2];
+
+/** Offset 0x1108 - Touch Host Controller Hid Over Spi Limit PacketSize
+  Minimum amount of delay the THC/QUICKSPI driver must wait between end of write operation
+  and begin of read operation. This value shall be in 10us multiples 0x0: Disabled,
+  1-65535 (0xFFFF) - up to 655350 us
+**/
+  UINT32                      ThcPerformanceLimitation[2];
+
+/** Offset 0x1110 - Touch Host Controller Hid Over Spi Input Report Header Address
+  Hid Over Spi Input Report Header Address
+**/
+  UINT32                      ThcHidSpiInputReportHeaderAddress[2];
+
+/** Offset 0x1118 - Touch Host Controller Hid Over Spi Input Report Body Address
+  Hid Over Spi Input Report Body Address
+**/
+  UINT32                      ThcHidSpiInputReportBodyAddress[2];
+
+/** Offset 0x1120 - Touch Host Controller Hid Over Spi Output Report Address
+  Hid Over Spi Output Report Address
+**/
+  UINT32                      ThcHidSpiOutputReportAddress[2];
+
+/** Offset 0x1128 - Touch Host Controller Hid Over Spi Read Opcode
+  Hid Over Spi Read Opcode
+**/
+  UINT32                      ThcHidSpiReadOpcode[2];
+
+/** Offset 0x1130 - Touch Host Controller Hid Over Spi Write Opcode
+  Hid Over Spi Write Opcode
+**/
+  UINT32                      ThcHidSpiWriteOpcode[2];
+
+/** Offset 0x1138 - Touch Host Controller Hid Over Spi Flags
+  Hid Over Spi Flags 0x0:Single SPI Mode, 0x4000:Dual SPI Mode, 0x8000:Quad SPI Mode
+**/
+  UINT32                      ThcHidSpiFlags[2];
+
+/** Offset 0x1140 - Touch Host Controller Reset Sequencing Delay [ms]
+  Policy control for reset sequencing delay (ACPI _INI, _RST) default 300ms
+**/
+  UINT16                      ThcResetSequencingDelay[2];
+
+/** Offset 0x1144 - Touch Host Controller Hid Over I2c Device Address
+  Hid Over I2c Device Address
+**/
+  UINT32                      ThcHidI2cDeviceAddress[2];
+
+/** Offset 0x114C - Touch Host Controller Hid Over I2c Connection Speed
+  Hid Over I2c Connection Speed [Hz]
+**/
+  UINT32                      ThcHidI2cConnectionSpeed[2];
+
+/** Offset 0x1154 - Touch Host Controller Hid Over I2c Addressing Mode
+  Hid Over I2c Addressing Mode - 0x1: The connection uses 10-bit addressing. 0x0:
+  The connection uses 7-bit addressing.
+**/
+  UINT8                       ThcHidI2cAddressingMode[2];
+
+/** Offset 0x1156 - Reserved
+**/
+  UINT8                       Reserved19[2];
+
+/** Offset 0x1158 - Touch Host Controller Hid Over I2c Device Descriptor Address
+  Hid Over I2c Device Descriptor Address
+**/
+  UINT32                      ThcHidI2cDeviceDescriptorAddress[2];
+
+/** Offset 0x1160 - Touch Host Controller Hid Over I2c Serial Clock Line High Period
+  Hid Over I2c Device Descriptor Address
+**/
+  UINT32                      ThcHidI2cStandardModeSerialClockLineHighPeriod[2];
+
+/** Offset 0x1168 - Touch Host Controller Hid Over I2c Standard Mode Serial Clock Line Low Period
+  Hid Over I2c Device Descriptor Address
+**/
+  UINT32                      ThcHidI2cStandardModeSerialClockLineLowPeriod[2];
+
+/** Offset 0x1170 - Touch Host Controller Hid Over I2c Standard Mode Serial Data Line Transmit Hold Period
+  Hid Over I2c Device Descriptor Address
+**/
+  UINT32                      ThcHidI2cStandardModeSerialDataLineTransmitHoldPeriod[2];
+
+/** Offset 0x1178 - Touch Host Controller Hid Over I2c Standard Mode Serial Data Line Receive Hold Period
+  Hid Over I2c Device Descriptor Address
+**/
+  UINT32                      ThcHidI2cStandardModeSerialDataLineReceiveHoldPeriod[2];
+
+/** Offset 0x1180 - Touch Host Controller Hid Over I2c Fast Mode Serial Clock Line High Period
+  Hid Over I2c Device Descriptor Address
+**/
+  UINT32                      ThcHidI2cFastModeSerialClockLineHighPeriod[2];
+
+/** Offset 0x1188 - Touch Host Controller Hid Over I2c Fast Mode Serial Clock Line Low Period
+  Hid Over I2c Device Descriptor Address
+**/
+  UINT32                      ThcHidI2cFastModeSerialClockLineLowPeriod[2];
+
+/** Offset 0x1190 - Touch Host Controller Hid Over I2c Fast Mode Serial Data Line Transmit Hold Period
+  Hid Over I2c Device Descriptor Address
+**/
+  UINT32                      ThcHidI2cFastModeSerialDataLineTransmitHoldPeriod[2];
+
+/** Offset 0x1198 - Touch Host Controller Hid Over I2c Fast Mode Serial Data Line Receive Hold Period
+  Hid Over I2c Device Descriptor Address
+**/
+  UINT32                      ThcHidI2cFastModeSerialDataLineReceiveHoldPeriod[2];
+
+/** Offset 0x11A0 - Touch Host Controller Hid Over I2c Maximum Length Of Suppressed Spikes In Std Mode Fast Mode And Fast Mode Plus
+  Hid Over I2c Device Descriptor Address
+**/
+  UINT32                      ThcHidI2cMaxSuppressedSpikesSMFMFMP[2];
+
+/** Offset 0x11A8 - Touch Host Controller Hid Over I2c Fast Mode Plus Serial Clock Line High Period
+  Hid Over I2c Device Descriptor Address
+**/
+  UINT32                      ThcHidI2cFastModePlusSerialClockLineHighPeriod[2];
+
+/** Offset 0x11B0 - Touch Host Controller Hid Over I2c Fast Mode Plus Serial Clock Line Low Period
+  Hid Over I2c Device Descriptor Address
+**/
+  UINT32                      ThcHidI2cFastModePlusSerialClockLineLowPeriod[2];
+
+/** Offset 0x11B8 - Touch Host Controller Hid Over I2c Fast Mode Plus Serial Data Line Transmit Hold Period
+  Hid Over I2c Device Descriptor Address
+**/
+  UINT32                      ThcHidI2cFastModePlusSerialDataLineTransmitHoldPeriod[2];
+
+/** Offset 0x11C0 - Touch Host Controller Hid Over I2c Fast Mode Plus Serial Data Line Receive Hold Period
+  Hid Over I2c Device Descriptor Address
+**/
+  UINT32                      ThcHidI2cFastModePlusSerialDataLineReceiveHoldPeriod[2];
+
+/** Offset 0x11C8 - Touch Host Controller Hid Over I2c High Speed Mode Plus Serial Clock Line High Period
+  Hid Over I2c Device Descriptor Address
+**/
+  UINT32                      ThcHidI2cHighSpeedModePlusSerialClockLineHighPeriod[2];
+
+/** Offset 0x11D0 - Touch Host Controller Hid Over I2c High Speed Mode Plus Serial Clock Line Low Period
+  Hid Over I2c Device Descriptor Address
+**/
+  UINT32                      ThcHidI2cHighSpeedModePlusSerialClockLineLowPeriod[2];
+
+/** Offset 0x11D8 - Touch Host Controller Hid Over I2c High Speed Mode Plus Serial Data Line Transmit Hold Period
+  Hid Over I2c Device Descriptor Address
+**/
+  UINT32                      ThcHidI2cHighSpeedModePlusSerialDataLineTransmitHoldPeriod[2];
+
+/** Offset 0x11E0 - Touch Host Controller Hid Over I2c High Speed Mode Plus Serial Data Line Receive Hold Period
+  Hid Over I2c Device Descriptor Address
+**/
+  UINT32                      ThcHidI2cHighSpeedModePlusSerialDataLineReceiveHoldPeriod[2];
+
+/** Offset 0x11E8 - Touch Host Controller Hid Over I2c Maximum Length Of Suppressed Spikes In High Speed Mode
+  Hid Over I2c Device Descriptor Address
+**/
+  UINT32                      ThcHidI2cMaximumLengthOfSuppressedSpikesInHighSpeedMode[2];
+
+/** Offset 0x11F0 - THC Wake On Touch GPIO resource Edge or Level
+  Definition of GPIO resource configuration of Edge or Level
+**/
+  UINT8                       ThcWotEdgeLevel[2];
+
+/** Offset 0x11F2 - THC Wake On Touch GPIO resource of Active Level
+  Definition of GPIO resource configuration of Active Level
+**/
+  UINT8                       ThcWotActiveLevel[2];
+
+/** Offset 0x11F4 - THC Wake On Touch GPIO resource of pin configuration
+  Definition of GPIO resource configuration of pin configuration
+**/
+  UINT8                       ThcWotPinConfig[2];
+
+/** Offset 0x11F6 - THC customized SubSytem ID for Port
+  Definition of GPIO resource configuration of pin configuration
+**/
+  UINT16                      ThcCustomizedSsid[2];
+
+/** Offset 0x11FA - THC Sets Customized SubSytem Vendor ID for Port
+  Definition of GPIO resource configuration of pin configuration
+**/
+  UINT16                      ThcCustomizedSvid[2];
+
+/** Offset 0x11FE - Reserved
+**/
+  UINT8                       Reserved20[2];
+
+/** Offset 0x1200 - USB 3.1 Speed Selection
+  Choose USB 3.1 Port Speed Selection. Each bit represents a port. 1: Gen1, 0: Gen2
+**/
+  UINT32                      Usb31PortSpeed;
+
+/** Offset 0x1204 - Touch Host Controller Hid Over I2c Maximum Frame Size Enable
+  Choose USB 3.1 Port Speed Selection. Each bit represents a port. 1: Gen1, 0: Gen2
+**/
+  UINT8                       ThcHidI2cMaxFrameSize[2];
+
+/** Offset 0x1206 - Touch Host Controller Hid Over I2c Maximum Frame Size Value
+  Choose USB 3.1 Port Speed Selection. Each bit represents a port. 1: Gen1, 0: Gen2
+**/
+  UINT16                      ThcHidI2cMaxFrameSizeValue[2];
+
+/** Offset 0x120A - Touch Host Controller Hid Over I2c Interrupt Delay Enable
+  Choose USB 3.1 Port Speed Selection. Each bit represents a port. 1: Gen1, 0: Gen2
+**/
+  UINT8                       ThcHidI2cIntDelay[2];
+
+/** Offset 0x120C - Touch Host Controller Hid Over I2c Interrupt Delay Value
+  Choose USB 3.1 Port Speed Selection. Each bit represents a port. 1: Gen1, 0: Gen2
+**/
+  UINT16                      ThcHidI2cIntDelayValue[2];
+
+/** Offset 0x1210 - Reserved
+**/
+  UINT8                       Reserved21[9];
 
 /** Offset 0x1219 - PCHHOT# pin
   Enable PCHHOT# pin assertion when temperature is higher than PchHotLevel. 0: disable, 1: enable
@@ -1683,7 +2951,47 @@ typedef struct {
 
 /** Offset 0x122A - Reserved
 **/
-  UINT8                      Reserved39[34];
+  UINT8                      Reserved22[2];
+
+/** Offset 0x122C - PCH TSN MAC Address High Bits
+  Set TSN MAC Address High.
+**/
+  UINT32                      PchTsn1MacAddressHigh;
+
+/** Offset 0x1230 - PCH TSN MAC Address Low Bits
+  Set TSN MAC Address Low.
+**/
+  UINT32                      PchTsn1MacAddressLow;
+
+/** Offset 0x1234 - PCH TSN2 MAC Address High Bits
+  Set TSN2 MAC Address High.
+**/
+  UINT32                      PchTsn2MacAddressHigh;
+
+/** Offset 0x1238 - PCH TSN2 MAC Address Low Bits
+  Set TSN2 MAC Address Low.
+**/
+  UINT32                      PchTsn2MacAddressLow;
+
+/** Offset 0x123C - PCH TSN3 MAC Address High Bits
+  Set TSN3 MAC Address High.
+**/
+  UINT32                      PchTsn3MacAddressHigh;
+
+/** Offset 0x1240 - PCH TSN3 MAC Address Low Bits
+  Set TSN3 MAC Address Low.
+**/
+  UINT32                      PchTsn3MacAddressLow;
+
+/** Offset 0x1244 - PCH TSN4 MAC Address High Bits
+  Set TSN4 MAC Address High.
+**/
+  UINT32                      PchTsn4MacAddressHigh;
+
+/** Offset 0x1248 - PCH TSN MAC4 Address Low Bits
+  Set TSN MAC4 Address Low.
+**/
+  UINT32                      PchTsn4MacAddressLow;
 
 /** Offset 0x124C - Enable USB2 ports
   Enable/disable per USB2 ports. One byte for each port, byte0 for port0, byte1 for
@@ -1710,9 +3018,11 @@ typedef struct {
 **/
   UINT8                       UsbPdoProgramming;
 
-/** Offset 0x1268 - Reserved
+/** Offset 0x1268 - USB Audio Offload enable
+  Enable/Disable USB Audio Offload capabilites. 0: disabled, 1: enabled (default)
+  $EN_DIS
 **/
-  UINT8                       Reserved40;
+  UINT8                       PchXhciUaolEnable;
 
 /** Offset 0x1269 - PCH USB OverCurrent mapping enable
   1: Will program USB OC pin mapping in xHCI controller memory, 0: Will clear OC pin
@@ -1737,9 +3047,15 @@ typedef struct {
 **/
   UINT8                       PchUsbLtrOverrideEnable;
 
-/** Offset 0x1285 - Reserved
+/** Offset 0x1285 - USB DWB enable
+  Enable/Disable USB DWB. 0: disabled, 1: enabled (default)
+  $EN_DIS
 **/
-  UINT8                       Reserved41[3];
+  UINT8                       PchXhciDwbEnable;
+
+/** Offset 0x1286 - Reserved
+**/
+  UINT8                       Reserved23[2];
 
 /** Offset 0x1288 - xHCI High Idle Time LTR override
   Value used for overriding LTR recommendation for xHCI High Idle Time LTR setting
@@ -1897,9 +3213,21 @@ typedef struct {
 **/
   UINT8                       Usb3HsioTxRate0UniqTran[10];
 
-/** Offset 0x13AD - Reserved
+/** Offset 0x13AD - PCIe Fia Programming
+  Load Fia configuration if enable. 0: Disable; 1: Enable(Default).
+  $EN_DIS
 **/
-  UINT8                       Reserved42[4];
+  UINT8                       PcieFiaProgramming;
+
+/** Offset 0x13AE - Enable SSE Device
+  Test, 0: POR, 1: enable, 2: disable, Enable/Disable SSE/SSE++ Devices from PCI config space
+  $EN_DIS
+**/
+  UINT8                       SseCommunication;
+
+/** Offset 0x13AF - Reserved
+**/
+  UINT8                       Reserved24[2];
 
 /** Offset 0x13B1 - Enable/Disable NPU Device
   Enable(Default): Enable NPU Device, Disable: Disable NPU Device
@@ -1919,9 +3247,11 @@ typedef struct {
 **/
   UINT8                       PchLanLtrEnable;
 
-/** Offset 0x13B4 - Reserved
+/** Offset 0x13B4 - PCH Lan WOL Fast Support
+  Enables bit B_PCH_ACPI_GPE0_EN_127_96_PME_B0 during PchLanSxCallback in PchLanSxSmm.
+  $EN_DIS
 **/
-  UINT8                       Reserved43;
+  UINT8                       PchLanWOLFastSupport;
 
 /** Offset 0x13B5 - Skip Ssid Programming.
   When set to TRUE, silicon code will not do any SSID programming and platform code
@@ -1942,9 +3272,15 @@ typedef struct {
 **/
   UINT16                      SiCustomizedSsid;
 
-/** Offset 0x13BA - Reserved
+/** Offset 0x13BA - CAN Configurations
+  Enable/Disable CAN Controllers.0: Disable, <b>1: Enable</b>
+  $EN_DIS
 **/
-  UINT8                       Reserved44[6];
+  UINT8                       PchCanEnable[2];
+
+/** Offset 0x13BC - Reserved
+**/
+  UINT8                       Reserved25[4];
 
 /** Offset 0x13C0 - SVID SDID table Poniter.
   The address of the table of SVID SDID to customize each SVID SDID entry. This is
@@ -1958,9 +3294,15 @@ typedef struct {
 **/
   UINT16                      SiNumberOfSsidTableEntry;
 
-/** Offset 0x13CA - Reserved
+/** Offset 0x13CA - Skip DFX.
+  Skip DFX.
+  $EN_DIS
 **/
-  UINT8                       Reserved45[10];
+  UINT8                       DfxSkipBiosDone;
+
+/** Offset 0x13CB - Reserved
+**/
+  UINT8                       Reserved26[9];
 
 /** Offset 0x13D4 - LogoPixelHeight Address
   Address of LogoPixelHeight
@@ -1974,7 +3316,7 @@ typedef struct {
 
 /** Offset 0x13DC - Reserved
 **/
-  UINT8                       Reserved46[4];
+  UINT8                       Reserved27[4];
 
 /** Offset 0x13E0 - Blt Buffer Address
   Address of Blt buffer
@@ -1992,9 +3334,11 @@ typedef struct {
 **/
   UINT8                       SkipFspGop;
 
-/** Offset 0x13F1 - Reserved
+/** Offset 0x13F1 - Enable/Disable Media Configuration
+  Enable(Default): Configure Media for use, Disable: Skip Media Configuration
+  $EN_DIS
 **/
-  UINT8                       Reserved47;
+  UINT8                       ConfigureMedia;
 
 /** Offset 0x13F2 - Enable/Disable IGFX RenderStandby
   Enable(Default): Enable IGFX RenderStandby, Disable: Disable IGFX RenderStandby
@@ -2002,9 +3346,23 @@ typedef struct {
 **/
   UINT8                       RenderStandby;
 
-/** Offset 0x13F3 - Reserved
+/** Offset 0x13F3 - Enable/Disable GT Configuration
+  Enable(Default): Configure GT for use, Disable: Skip GT Configuration
+  $EN_DIS
 **/
-  UINT8                       Reserved48[3];
+  UINT8                       ConfigureGT;
+
+/** Offset 0x13F4 - Enable RC1p GT frequency request to PMA (provided all other conditions are met)
+  0(Default)=Disable, 1=Enable
+  $EN_DIS
+**/
+  UINT8                       RC1pGtFreqEnable;
+
+/** Offset 0x13F5 - Enable RC1p Media frequency request to PMA (provided all other conditions are met)
+  0(Default)=Disable, 1=Enable
+  $EN_DIS
+**/
+  UINT8                       RC1pMediaFreqEnable;
 
 /** Offset 0x13F6 - Enable/Disable PavpEnable
   Enable(Default): Enable PavpEnable, Disable: Disable PavpEnable
@@ -2019,9 +3377,21 @@ typedef struct {
 **/
   UINT8                       PeiGraphicsPeimInit;
 
-/** Offset 0x13F8 - Reserved
+/** Offset 0x13F8 - Enable/Disable IGFX Media Standby
+  Enable(Default): Enable IGFX Media Standby, Disable: Disable IGFX MediaStandby
+  $EN_DIS
 **/
-  UINT8                       Reserved49[4];
+  UINT8                       MediaStandby;
+
+/** Offset 0x13F9 - Enable/Disable Gfx Workstation
+  Enable(Default): Is a workstation, Disable: Is not a workstation
+  $EN_DIS
+**/
+  UINT8                       Dev2IsGfxWorkstation;
+
+/** Offset 0x13FA - Reserved
+**/
+  UINT8                       Reserved28[2];
 
 /** Offset 0x13FC - Intel Graphics VBT (Video BIOS Table) Size
   Size of Internal Graphics VBT Image
@@ -2042,7 +3412,21 @@ typedef struct {
 
 /** Offset 0x1402 - Reserved
 **/
-  UINT8                       Reserved50[66];
+  UINT8                       Reserved29[2];
+
+/** Offset 0x1404 - HorizontalResolution for PEI Logo
+  HorizontalResolution from PEIm Gfx for PEI Logo
+**/
+  UINT32                      HorizontalResolution;
+
+/** Offset 0x1408 - VerticalResolution for PEI Logo
+  VerticalResolution from PEIm Gfx for PEI Logo
+**/
+  UINT32                      VerticalResolution;
+
+/** Offset 0x140C - Reserved
+**/
+  UINT8                       Reserved30[56];
 
 /** Offset 0x1444 - Address of PCH_DEVICE_INTERRUPT_CONFIG table.
   The address of the table of PCH_DEVICE_INTERRUPT_CONFIG.
@@ -2076,9 +3460,33 @@ typedef struct {
 **/
   UINT8                       TcoIrqEnable;
 
-/** Offset 0x144D - Reserved
+/** Offset 0x144D - PMC ADR enable
+  Enable/disable asynchronous DRAM refresh
+  $EN_DIS
 **/
-  UINT8                       Reserved51[5];
+  UINT8                       PmcAdrEn;
+
+/** Offset 0x144E - PMC ADR timer configuration enable
+  Enable/disable ADR timer configuration
+  $EN_DIS
+**/
+  UINT8                       PmcAdrTimerEn;
+
+/** Offset 0x144F - PMC ADR phase 1 timer value
+  Enable/disable ADR timer configuration
+**/
+  UINT8                       PmcAdrTimer1Val;
+
+/** Offset 0x1450 - PMC ADR phase 1 timer multiplier value
+  Specify the multiplier value for phase 1 ADR timer
+**/
+  UINT8                       PmcAdrMultiplier1Val;
+
+/** Offset 0x1451 - PMC ADR host reset partition enable
+  Specify whether PMC should set ADR_RST_STS bit after receiving Reset_Warn_Ack DMI message
+  $EN_DIS
+**/
+  UINT8                       PmcAdrHostPartitionReset;
 
 /** Offset 0x1452 - Mask to enable the usage of external V1p05 VR rail in specific S0ix or Sx states
   Enable External V1P05 Rail in: BIT0:S0i1/S0i2, BIT1:S0i3, BIT2:S3, BIT3:S4, BIT5:S5
@@ -2112,7 +3520,7 @@ typedef struct {
 
 /** Offset 0x1459 - Reserved
 **/
-  UINT8                       Reserved52;
+  UINT8                       Reserved31;
 
 /** Offset 0x145A - External Vnn Voltage Value that will be used in S0ix/Sx states
   Value is given in 2.5mV increments (0=0mV, 1=2.5mV, 2=5mV...), Default is set to 420
@@ -2173,7 +3581,7 @@ typedef struct {
 
 /** Offset 0x1467 - Reserved
 **/
-  UINT8                       Reserved53;
+  UINT8                       Reserved32;
 
 /** Offset 0x1468 - External V1P05 Icc Max Value
   Granularity of this setting is 1mA and maximal possible value is 500mA
@@ -2213,9 +3621,11 @@ typedef struct {
 **/
   UINT8                       PchLegacyIoLowLatency;
 
-/** Offset 0x1472 - Reserved
+/** Offset 0x1472 - PCH P2SB
+  PCH P2SB
+  $EN_DIS
 **/
-  UINT8                       Reserved54;
+  UINT8                       SvTestUnhideP2sb;
 
 /** Offset 0x1473 - PCH Unlock SideBand access
   The SideBand PortID mask for certain end point (e.g. PSFx) will be locked before
@@ -2282,9 +3692,19 @@ typedef struct {
 **/
   UINT8                       CnviBtAudioOffload;
 
-/** Offset 0x147D - Reserved
+/** Offset 0x147D - WWAN Coex
+  WWAN Coex is getting updated from UEFI variable
 **/
-  UINT8                       Reserved55[3];
+  UINT8                       CnviWwanCoex;
+
+/** Offset 0x147E - Skip BtPreInit
+  BtPreInit can be skipped if SkipBtPreInit is enabled
+**/
+  UINT8                       SkipBtPreInit;
+
+/** Offset 0x147F - Reserved
+**/
+  UINT8                       Reserved33;
 
 /** Offset 0x1480 - CNVi RF_RESET pin muxing
   Select CNVi RF_RESET# pin depending on board routing. LP/P/M: GPP_A8 = 0x2942E408(default)
@@ -2299,9 +3719,11 @@ typedef struct {
 **/
   UINT32                      CnviClkreqPinMux;
 
-/** Offset 0x1488 - Reserved
+/** Offset 0x1488 - CNVi BT Audio OffOffloadInterfaceload
+  Enable/Disable BT Audio OffloadInterface, Default is ENABLE. 0: DISABLE, 1: ENABLE
+  $EN_DIS
 **/
-  UINT8                       Reserved56;
+  UINT8                       CnviBtAudioOffloadInterface;
 
 /** Offset 0x1489 - Enable Device 4
   Enable/disable Device 4
@@ -2316,9 +3738,10 @@ typedef struct {
 **/
   UINT8                       SkipPamLock;
 
-/** Offset 0x148B - Reserved
+/** Offset 0x148B - TCSS LSx OE Enable
+  Bits 0, 1, ... max Type C Rettimerless port LSx OE enables
 **/
-  UINT8                       Reserved57;
+  UINT8                       TcssLsxOe;
 
 /** Offset 0x148C - PCH HDA Verb Table Entry Number
   Number of Entries in Verb Table.
@@ -2327,7 +3750,7 @@ typedef struct {
 
 /** Offset 0x148D - Reserved
 **/
-  UINT8                       Reserved58[3];
+  UINT8                       Reserved34[3];
 
 /** Offset 0x1490 - PCH HDA Verb Table Pointer
   Pointer to Array of pointers to Verb Table.
@@ -2359,9 +3782,11 @@ typedef struct {
 **/
   UINT8                       PchHdaMicPrivacyMode;
 
-/** Offset 0x149C - Reserved
+/** Offset 0x149C - HD Audio Microphone Privacy Deglitch
+  HD Audio Microphone Privacy Deglitch: 0: Disable, 1: Enable
+  $EN_DIS
 **/
-  UINT8                       Reserved59;
+  UINT8                       PchHdaMicPrivacyDeglitch;
 
 /** Offset 0x149D - HD Audio Microphone Privacy applied for SoundWire Link number 0 in HW Mode
   HD Audio Microphone Privacy applied for SoundWire Link number 0 in HW Mode: 0: Disable, 1: Enable
@@ -2401,7 +3826,17 @@ typedef struct {
 
 /** Offset 0x14A3 - Reserved
 **/
-  UINT8                       Reserved60[13];
+  UINT8                       Reserved35;
+
+/** Offset 0x14A4 - HD Audio Microphone Privacy Timeout. Indicates the time-out duration to wait before forcing the actual microphone privacy DMA data zeroing.
+  HD Audio Microphone Privacy Timeout. Indicates the time-out duration to wait before
+  forcing the actual microphone privacy DMA data zeroing.
+**/
+  UINT32                      PchHdaMicPrivacyTimeout;
+
+/** Offset 0x14A8 - Reserved
+**/
+  UINT8                       Reserved36[8];
 
 /** Offset 0x14B0 - Pointer to ChipsetInit Binary
   ChipsetInit Binary Pointer.
@@ -2415,7 +3850,49 @@ typedef struct {
 
 /** Offset 0x14BC - Reserved
 **/
-  UINT8                       Reserved61[36];
+  UINT8                       Reserved37[4];
+
+/** Offset 0x14C0 - Pointer to NPHY Binary
+  Nphy Binary Pointer.
+**/
+  UINT64                      NphyBinPtr;
+
+/** Offset 0x14C8 - Length of NPHY Binary
+  Nphy Binary Length.
+**/
+  UINT32                      NphyBinLen;
+
+/** Offset 0x14CC - Reserved
+**/
+  UINT8                       Reserved38[4];
+
+/** Offset 0x14D0 - Pointer to SYNPS PHY Binary
+  Synps Binary Pointer.
+**/
+  UINT64                      SynpsPhyBinPtr;
+
+/** Offset 0x14D8 - Length of SYNPS PHY Binary
+  Synps Binary Length.
+**/
+  UINT32                      SynpsPhyBinLen;
+
+/** Offset 0x14DC - Skip setting BIOS_DONE When Fw Update.
+  When set to TRUE and boot mode is BOOT_ON_FLASH_UPDATE,skip setting BIOS_DONE MSR
+  at EndofPei. Note: BIOS_DONE MSR should be set in later phase before executing
+  3rd party code if SiSkipBiosDoneWhenFwUpdate set to TRUE.
+  $EN_DIS
+**/
+  UINT8                       SiSkipBiosDoneWhenFwUpdate;
+
+/** Offset 0x14DD - PMC WDT enable
+  Enable/disable PMC WDT configuration
+  $EN_DIS
+**/
+  UINT8                       PmcWdtTimerEn;
+
+/** Offset 0x14DE - Reserved
+**/
+  UINT8                       Reserved39[2];
 } FSP_S_CONFIG;
 
 /** Fsp S UPD Configuration
diff --git a/src/vendorcode/intel/fsp/fsp2_0/wildcatlake/MemInfoHob.h b/src/vendorcode/intel/fsp/fsp2_0/wildcatlake/MemInfoHob.h
index c89cf2cab1..a6d862368f 100644
--- a/src/vendorcode/intel/fsp/fsp2_0/wildcatlake/MemInfoHob.h
+++ b/src/vendorcode/intel/fsp/fsp2_0/wildcatlake/MemInfoHob.h
@@ -312,7 +312,8 @@ typedef struct _PPR_RESULT_COLUMNS_HOB {
   - DIMM_INFO: Added SerialNumber, TotalWidth and DataWidth
   - DIMM_INFO: Removed SpdModuleMemoryBusWidth
   - MFG ID fields: use HOB_MANUFACTURER_ID_CODE instead of UINT16 for easier parsing
-
+  <b>Revision 4:</b>
+  - Added FailingChannelMask
 **/
 typedef struct {
   UINT8             Revision;
@@ -363,6 +364,7 @@ typedef struct {
   UINT8             MaxRankCapacity;                   ///< Maximum possible rank capacity in [GB]
   UINT16            PprFailingChannelBitMask;          ///< PPR failing channel mask
   BOOLEAN           PprTargetedStatus[PPR_REQUEST_MAX]; ///< PPR status of each Targeted PPR request (0 = Targeted PPR was successful, 1 = PPR failed)
+  UINT8             FailingChannelMask;                ///< Limp Home mode failing channel bitmask
 } MEMORY_INFO_DATA_HOB;
 
 /**
@@ -387,6 +389,9 @@ typedef struct {
   PSMI_MEM_INFO     PsmiInfo[MAX_TRACE_CACHE_TYPE];
   PSMI_MEM_INFO     PsmiRegionInfo[MAX_TRACE_REGION];
   BOOLEAN           MrcBasicMemoryTestPass;
+  UINT8             Reserved1[3];                      // Reserved for alignment
+  UINT64            BiosPeiMemoryBaseAddress;
+  UINT64            BiosPeiMemoryLength;
 } MEMORY_PLATFORM_DATA;
 
 typedef struct {

From f89ac4e6ce267ce875f6ea40f4e907e47e24ee1e Mon Sep 17 00:00:00 2001
From: Subrata Banik <subratabanik@google.com>
Date: Mon, 23 Feb 2026 12:01:42 +0530
Subject: [PATCH 3427/3886] soc/mediatek/common: Adjust splash logo bottom
 margin

Increase the logo_bottom_margin from 100 to 200 in the display_logo
configuration if FRAMEBUFFER_SPLASH_TEXT Kconfig is enabled.

This adjustment ensures the OEM footer logo and associated
splash text are rendered higher on the screen, improving visibility
and alignment with updated UX requirements.

BUG=None
TEST=Boot MediaTek device and verify the splash text is 200px from
the screen bottom edge as expected.

Change-Id: I490e50e200dfffedf24cb30fe0ca6ea6ae037d3d
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91383
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/soc/mediatek/common/display.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/soc/mediatek/common/display.c b/src/soc/mediatek/common/display.c
index 9d2c873838..3b9d8be96c 100644
--- a/src/soc/mediatek/common/display.c
+++ b/src/soc/mediatek/common/display.c
@@ -90,7 +90,7 @@ static void display_logo(struct panel_description *panel,
 		.panel_orientation = panel->orientation,
 		.halignment = FW_SPLASH_HALIGNMENT_CENTER,
 		.valignment = FW_SPLASH_VALIGNMENT_CENTER,
-		.logo_bottom_margin = 100,
+		.logo_bottom_margin = CONFIG(FRAMEBUFFER_SPLASH_TEXT) ? 200 : 100,
 	};
 	render_logo_to_framebuffer(&config);
 

From 6a1b0161842cbc53035877c73f1ae9a2f6f65810 Mon Sep 17 00:00:00 2001
From: Angel Pons <th3fanbus@gmail.com>
Date: Sun, 22 Feb 2026 17:08:27 +0100
Subject: [PATCH 3428/3886] nb/intel/haswell: Tidy up memory info prints

Be consistent when printing the channel assignment, and use unsigned
printf specifiers since the values themselves are unsigned.

Change-Id: I66b93233707dec73dc7a25423789a24770ac678f
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91376
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Benjamin Doron <benjamin.doron00@gmail.com>
---
 src/northbridge/intel/haswell/raminit_shared.c | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/src/northbridge/intel/haswell/raminit_shared.c b/src/northbridge/intel/haswell/raminit_shared.c
index 6fcb0ec98a..1e6394da77 100644
--- a/src/northbridge/intel/haswell/raminit_shared.c
+++ b/src/northbridge/intel/haswell/raminit_shared.c
@@ -36,7 +36,7 @@ void report_memory_config(void)
 	printk(BIOS_DEBUG, "memcfg DDR3 clock %d MHz\n",
 	       DIV_ROUND_CLOSEST(mchbar_read32(MC_BIOS_DATA) * 13333 * 2, 100));
 
-	printk(BIOS_DEBUG, "memcfg channel assignment: A: %d, B % d, C % d\n",
+	printk(BIOS_DEBUG, "memcfg channel assignment: A: %u, B: %u, C: %u\n",
 	       (addr_decoder_common >> 0) & 3,
 	       (addr_decoder_common >> 2) & 3,
 	       (addr_decoder_common >> 4) & 3);
@@ -44,7 +44,7 @@ void report_memory_config(void)
 	for (unsigned int i = 0; i < NUM_CHANNELS; i++) {
 		const uint32_t ch_conf = mchbar_read32(MAD_DIMM(i));
 
-		printk(BIOS_DEBUG, "memcfg channel[%d] config (%8.8x):\n", i, ch_conf);
+		printk(BIOS_DEBUG, "memcfg channel[%u] config (%8.8x):\n", i, ch_conf);
 		printk(BIOS_DEBUG, "   ECC %s\n", ecc_decoder[(ch_conf >> 24) & 3]);
 		printk(BIOS_DEBUG, "   enhanced interleave mode %s\n",
 		       ((ch_conf >> 22) & 1) ? "on" : "off");
@@ -52,13 +52,13 @@ void report_memory_config(void)
 		printk(BIOS_DEBUG, "   rank interleave %s\n",
 		       ((ch_conf >> 21) & 1) ? "on" : "off");
 
-		printk(BIOS_DEBUG, "   DIMMA %d MB width %s %s rank%s\n",
+		printk(BIOS_DEBUG, "   DIMMA %u MB width %s %s rank%s\n",
 		       ((ch_conf >> 0) & 0xff) * 256,
 		       ((ch_conf >> 19) & 1) ? "x16" : "x8 or x32",
 		       ((ch_conf >> 17) & 1) ? "dual" : "single",
 		       ((ch_conf >> 16) & 1) ? "" : ", selected");
 
-		printk(BIOS_DEBUG, "   DIMMB %d MB width %s %s rank%s\n",
+		printk(BIOS_DEBUG, "   DIMMB %u MB width %s %s rank%s\n",
 		       ((ch_conf >> 8) & 0xff) * 256,
 		       ((ch_conf >> 20) & 1) ? "x16" : "x8 or x32",
 		       ((ch_conf >> 18) & 1) ? "dual" : "single",

From d9bc4740da9fbd945790fa618c0ae3ee6e6760b2 Mon Sep 17 00:00:00 2001
From: Angel Pons <th3fanbus@gmail.com>
Date: Sun, 22 Feb 2026 16:46:12 +0100
Subject: [PATCH 3429/3886] nb/intel/haswell: Fix DDR frequency reporting

DDR frequency (in MHz) was doubled for no reason, then doubled again to
convert it to MT/s. Moreover, the calculations assume a reference clock
of 133 MHz, but a 100 MHz reference clock also exists.

Add two functions: `is_100_mhz_refclk()` to check whether the reference
clock is 100 MHz, and `get_ddr_freq_mhz()` to get the DDR frequency, in
MHz. Use both functions in `report_memory_config()` to show the correct
DDR ref. clock and frequency, and use one in `setup_sdram_meminfo()` so
that SMBIOS tables contain the correct memory speed.

Tested on ASRock Z97 Extreme6 with four DDR3-1600 sticks, DDR frequency
is correctly reported as 800 MHz with either reference clock frequency:

Default 133 MHz reference clock:
    memcfg DDR3 ref clock 133 MHz
    memcfg DDR3 clock 800 MHz

After forcing 100 MHz ref clock for 800 MHz (edit NRI's `init_mpll.c`):
    memcfg DDR3 ref clock 100 MHz
    memcfg DDR3 clock 800 MHz

Also, SMBIOS type 17 correctly reports memory speeds of 1600 MT/s:

$ sudo dmidecode --type 17 | grep -i speed
	Speed: 1600 MT/s
	Configured Memory Speed: 1600 MT/s
	Speed: 1600 MT/s
	Configured Memory Speed: 1600 MT/s
	Speed: 1600 MT/s
	Configured Memory Speed: 1600 MT/s
	Speed: 1600 MT/s
	Configured Memory Speed: 1600 MT/s

It is expected that behaviour using either MRC binary is the same since
the `MC_BIOS_REQ` and `MC_BIOS_DATA` registers have to be programmed in
order for the DDR clock to start running. The decision to test with NRI
is because one can easily change the chosen reference clock to 100 MHz.

Resolves: https://ticket.coreboot.org/issues/624

Change-Id: Idead9cd55b453d3ff4695c977dee763ff50830f8
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91375
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Benjamin Doron <benjamin.doron00@gmail.com>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
---
 .../intel/haswell/raminit_shared.c            | 22 +++++++++++++++----
 1 file changed, 18 insertions(+), 4 deletions(-)

diff --git a/src/northbridge/intel/haswell/raminit_shared.c b/src/northbridge/intel/haswell/raminit_shared.c
index 1e6394da77..5e3602c31e 100644
--- a/src/northbridge/intel/haswell/raminit_shared.c
+++ b/src/northbridge/intel/haswell/raminit_shared.c
@@ -28,13 +28,28 @@ static const char *const ecc_decoder[] = {
 	"active",
 };
 
+static bool is_100_mhz_refclk(void)
+{
+	return mchbar_read32(MC_BIOS_REQ) & (1 << 4);
+}
+
+static unsigned int get_ddr_freq_mhz(void)
+{
+	/* Use KHz to minimise rounding errors */
+	const unsigned int refclk_khz = is_100_mhz_refclk() ? 100000 : 133333;
+	const unsigned int multiplier = mchbar_read32(MC_BIOS_DATA) & 0xf;
+
+	return DIV_ROUND_CLOSEST(multiplier * refclk_khz, 1000);
+}
+
 /* Print out the memory controller configuration, as per the values in its registers. */
 void report_memory_config(void)
 {
 	const uint32_t addr_decoder_common = mchbar_read32(MAD_CHNL);
 
-	printk(BIOS_DEBUG, "memcfg DDR3 clock %d MHz\n",
-	       DIV_ROUND_CLOSEST(mchbar_read32(MC_BIOS_DATA) * 13333 * 2, 100));
+	const unsigned int refclk_mhz = is_100_mhz_refclk() ? 100 : 133;
+	printk(BIOS_DEBUG, "memcfg DDR3 ref clock %u MHz\n", refclk_mhz);
+	printk(BIOS_DEBUG, "memcfg DDR3 clock %u MHz\n", get_ddr_freq_mhz());
 
 	printk(BIOS_DEBUG, "memcfg channel assignment: A: %u, B: %u, C: %u\n",
 	       (addr_decoder_common >> 0) & 3,
@@ -113,8 +128,7 @@ void setup_sdram_meminfo(const uint8_t *spd_data[NUM_CHANNELS][NUM_SLOTS])
 
 	memset(mem_info, 0, sizeof(struct memory_info));
 
-	/* TODO: This looks like an open-coded DIV_ROUND_CLOSEST() */
-	const uint32_t ddr_freq_mhz = (mchbar_read32(MC_BIOS_DATA) * 13333 * 2 + 50) / 100;
+	const uint32_t ddr_freq_mhz = get_ddr_freq_mhz();
 
 	unsigned int dimm_cnt = 0;
 	for (unsigned int channel = 0; channel < NUM_CHANNELS; channel++) {

From f96644e7743c26fb33dd99745675507f90ab285f Mon Sep 17 00:00:00 2001
From: Angel Pons <th3fanbus@gmail.com>
Date: Sun, 22 Feb 2026 15:54:39 +0100
Subject: [PATCH 3430/3886] nb/intel/haswell: Do not print ME status twice

The `intel_early_me_init_done()` function prints the ME status. In order
to see the ME status once in all paths, have the aforementioned function
only call `intel_early_me_status()` before handling a reset request.

Change-Id: I42ad1b25889a21047b7cf55e7940293e73794d8b
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91374
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Benjamin Doron <benjamin.doron00@gmail.com>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
---
 src/southbridge/intel/lynxpoint/early_me.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/src/southbridge/intel/lynxpoint/early_me.c b/src/southbridge/intel/lynxpoint/early_me.c
index 07013c5539..6dab65238e 100644
--- a/src/southbridge/intel/lynxpoint/early_me.c
+++ b/src/southbridge/intel/lynxpoint/early_me.c
@@ -159,9 +159,6 @@ int intel_early_me_init_done(u8 status)
 	printk(BIOS_NOTICE, "ME: Requested BIOS Action: %s\n",
 	       me_ack_values[hfs.ack_data]);
 
-	/* Check status after acknowledgement */
-	intel_early_me_status();
-
 	reset = 0;
 	switch (hfs.ack_data) {
 	case ME_HFS_ACK_CONTINUE:
@@ -190,6 +187,9 @@ int intel_early_me_init_done(u8 status)
 
 	/* Perform the requested reset */
 	if (reset) {
+		/* Show ME status before resetting */
+		intel_early_me_status();
+
 		outb(reset, 0xcf9);
 		halt();
 	}

From fd2cdf206d10d05353b852174ab39f9ae42084cf Mon Sep 17 00:00:00 2001
From: Patrick Rudolph <patrick.rudolph@9elements.com>
Date: Fri, 30 Jan 2026 15:19:59 +0100
Subject: [PATCH 3431/3886] cpu/intel/smm/gen1: Optimize
 cpu_has_alternative_smrr

For most targets it's known if the CPU supports alternative SMRR
registers or not. Only on model_6fx runtime detection is necessary.

On all platforms this allows the compiler to optimize the code and
thus shrink the code size if alternative SMRR aren't supported.

TEST=On Lenovo X220 the ramstage is 308 bytes smaller.

Change-Id: I3a965d142f79ad587b8cedc9b4646b05e2a45f8b
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91014
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
---
 src/cpu/intel/model_1067x/mp_init.c  |  2 +-
 src/cpu/intel/smm/gen1/smmrelocate.c | 19 ++++++++-----------
 src/include/cpu/intel/smm_reloc.h    |  2 --
 3 files changed, 9 insertions(+), 14 deletions(-)

diff --git a/src/cpu/intel/model_1067x/mp_init.c b/src/cpu/intel/model_1067x/mp_init.c
index bc53214310..8f04bf9ccc 100644
--- a/src/cpu/intel/model_1067x/mp_init.c
+++ b/src/cpu/intel/model_1067x/mp_init.c
@@ -48,7 +48,7 @@ static void pre_mp_smm_init(void)
 static void per_cpu_smm_trigger(void)
 {
 	msr_t mtrr_cap = rdmsr(MTRR_CAP_MSR);
-	if (cpu_has_alternative_smrr() && mtrr_cap.lo & SMRR_SUPPORTED) {
+	if (mtrr_cap.lo & SMRR_SUPPORTED) {
 		set_feature_ctrl_vmx();
 		msr_t ia32_ft_ctrl = rdmsr(IA32_FEATURE_CONTROL);
 		/* We don't care if the lock is already setting
diff --git a/src/cpu/intel/smm/gen1/smmrelocate.c b/src/cpu/intel/smm/gen1/smmrelocate.c
index c57a661ef7..6f3806dede 100644
--- a/src/cpu/intel/smm/gen1/smmrelocate.c
+++ b/src/cpu/intel/smm/gen1/smmrelocate.c
@@ -28,20 +28,17 @@
 /* On model_6fx, model_1067x and model_106cx SMRR functions slightly
    differently. The MSR are at different location from the rest
    and need to be explicitly enabled in IA32_FEATURE_CONTROL MSR. */
-bool cpu_has_alternative_smrr(void)
+static inline bool cpu_has_alternative_smrr(void)
 {
+	if (CONFIG(CPU_INTEL_MODEL_1067X) ||
+	    CONFIG(CPU_INTEL_MODEL_106CX))
+		return true;
+	if (!CONFIG(CPU_INTEL_MODEL_6FX))
+		return false;
+	/* Runtime detection as model_6fx also supports Fam 6 Model 16h */
 	struct cpuinfo_x86 c;
 	get_fms(&c, cpuid_eax(1));
-	if (c.x86 != 6)
-		return false;
-	switch (c.x86_model) {
-	case 0xf:
-	case 0x17: /* core2 */
-	case 0x1c: /* Bonnell */
-		return true;
-	default:
-		return false;
-	}
+	return c.x86 == 6 && c.x86_model == 0xf;
 }
 
 static void write_smrr_alt(struct smm_relocation_params *relo_params)
diff --git a/src/include/cpu/intel/smm_reloc.h b/src/include/cpu/intel/smm_reloc.h
index 6b1a525d6c..2b25c75705 100644
--- a/src/include/cpu/intel/smm_reloc.h
+++ b/src/include/cpu/intel/smm_reloc.h
@@ -51,8 +51,6 @@ void smm_initialize(void);
 void smm_info(uintptr_t *perm_smbase, size_t *perm_smsize, size_t *smm_save_state_size);
 void smm_relocation_handler(int cpu, uintptr_t curr_smbase, uintptr_t staggered_smbase);
 
-bool cpu_has_alternative_smrr(void);
-
 #define MSR_PRMRR_PHYS_BASE 0x1f4
 #define MSR_PRMRR_PHYS_MASK 0x1f5
 #define MSR_UNCORE_PRMRR_PHYS_BASE 0x2f4

From dfcd63370daceefca8394524f47ac298c4dcf8c0 Mon Sep 17 00:00:00 2001
From: Patrick Rudolph <patrick.rudolph@9elements.com>
Date: Fri, 30 Jan 2026 15:26:51 +0100
Subject: [PATCH 3432/3886] cpu/intel: Use existing defines for MTRR_CAP_MSR

Use existing define for SMRR and PMRR support instead of redefining
it in various places.

TEST=No functional change, thus untested.

Change-Id: Ie366a9d695800acd9713bd4e8393201a1f0a5ab2
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91015
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/cpu/intel/haswell/haswell.h                      | 4 ----
 src/cpu/intel/haswell/smmrelocate.c                  | 4 ++--
 src/cpu/intel/model_1067x/mp_init.c                  | 4 +---
 src/cpu/intel/smm/gen1/smmrelocate.c                 | 4 +---
 src/soc/intel/common/block/cpu/smmrelocate.c         | 2 +-
 src/soc/intel/common/block/include/intelblocks/msr.h | 2 --
 6 files changed, 5 insertions(+), 15 deletions(-)

diff --git a/src/cpu/intel/haswell/haswell.h b/src/cpu/intel/haswell/haswell.h
index f42199de0a..d24cbe1975 100644
--- a/src/cpu/intel/haswell/haswell.h
+++ b/src/cpu/intel/haswell/haswell.h
@@ -103,10 +103,6 @@
 #define SMBASE_MSR			0xc20
 #define IEDBASE_MSR			0xc22
 
-/* MTRR_CAP_MSR bit definitions */
-#define SMRR_SUPPORTED			(1 << 11)
-#define PRMRR_SUPPORTED			(1 << 12)
-
 /* Intel suggested latency times in units of 1024ns. */
 #define C_STATE_LATENCY_CONTROL_0_LIMIT 0x42
 #define C_STATE_LATENCY_CONTROL_1_LIMIT 0x73
diff --git a/src/cpu/intel/haswell/smmrelocate.c b/src/cpu/intel/haswell/smmrelocate.c
index 47946e8401..6ce41965d1 100644
--- a/src/cpu/intel/haswell/smmrelocate.c
+++ b/src/cpu/intel/haswell/smmrelocate.c
@@ -124,10 +124,10 @@ void smm_relocation_handler(int cpu, uintptr_t curr_smbase,
 
 	/* Write PRMRR and SMRR MSRs based on indicated support. */
 	mtrr_cap = rdmsr(MTRR_CAP_MSR);
-	if (mtrr_cap.lo & SMRR_SUPPORTED)
+	if (mtrr_cap.lo & MTRR_CAP_SMRR)
 		write_smrr(relo_params);
 
-	if (mtrr_cap.lo & PRMRR_SUPPORTED) {
+	if (mtrr_cap.lo & MTRR_CAP_PRMRR) {
 		write_prmrr(relo_params);
 		/* UNCORE_PRMRR msrs are package level. Therefore, only
 		 * configure these MSRs on the BSP. */
diff --git a/src/cpu/intel/model_1067x/mp_init.c b/src/cpu/intel/model_1067x/mp_init.c
index 8f04bf9ccc..def136e689 100644
--- a/src/cpu/intel/model_1067x/mp_init.c
+++ b/src/cpu/intel/model_1067x/mp_init.c
@@ -43,12 +43,10 @@ static void pre_mp_smm_init(void)
 	smm_initialize();
 }
 
-#define SMRR_SUPPORTED (1 << 11)
-
 static void per_cpu_smm_trigger(void)
 {
 	msr_t mtrr_cap = rdmsr(MTRR_CAP_MSR);
-	if (mtrr_cap.lo & SMRR_SUPPORTED) {
+	if (mtrr_cap.lo & MTRR_CAP_SMRR) {
 		set_feature_ctrl_vmx();
 		msr_t ia32_ft_ctrl = rdmsr(IA32_FEATURE_CONTROL);
 		/* We don't care if the lock is already setting
diff --git a/src/cpu/intel/smm/gen1/smmrelocate.c b/src/cpu/intel/smm/gen1/smmrelocate.c
index 6f3806dede..1408a67469 100644
--- a/src/cpu/intel/smm/gen1/smmrelocate.c
+++ b/src/cpu/intel/smm/gen1/smmrelocate.c
@@ -17,8 +17,6 @@
 #include <console/console.h>
 #include <smp/node.h>
 
-#define SMRR_SUPPORTED (1 << 11)
-
 #define  D_OPEN		(1 << 6)
 #define  D_CLS		(1 << 5)
 #define  D_LCK		(1 << 4)
@@ -180,7 +178,7 @@ void smm_relocation_handler(int cpu, uintptr_t curr_smbase,
 
 	/* Write EMRR and SMRR MSRs based on indicated support. */
 	mtrr_cap = rdmsr(MTRR_CAP_MSR);
-	if (!(mtrr_cap.lo & SMRR_SUPPORTED))
+	if (!(mtrr_cap.lo & MTRR_CAP_SMRR))
 		return;
 
 	if (cpu_has_alternative_smrr())
diff --git a/src/soc/intel/common/block/cpu/smmrelocate.c b/src/soc/intel/common/block/cpu/smmrelocate.c
index e510c96f99..fa4c8963a1 100644
--- a/src/soc/intel/common/block/cpu/smmrelocate.c
+++ b/src/soc/intel/common/block/cpu/smmrelocate.c
@@ -164,7 +164,7 @@ void smm_relocation_handler(int cpu, uintptr_t curr_smbase,
 		relo_params->smrr_mask.lo |= SMRR_PHYS_MASK_LOCK;
 
 	/* Write SMRRs if supported */
-	if (mtrr_cap.lo & SMRR_SUPPORTED)
+	if (mtrr_cap.lo & MTRR_CAP_SMRR)
 		write_smrr(relo_params);
 }
 
diff --git a/src/soc/intel/common/block/include/intelblocks/msr.h b/src/soc/intel/common/block/include/intelblocks/msr.h
index 4bdd90c536..1965b36d59 100644
--- a/src/soc/intel/common/block/include/intelblocks/msr.h
+++ b/src/soc/intel/common/block/include/intelblocks/msr.h
@@ -110,8 +110,6 @@
 #define MSR_L2_QOS_MASK(reg)		(0xd10 + reg)
 
 /* MTRR_CAP_MSR bits */
-#define SMRR_SUPPORTED			(1<<11)
-#define PRMRR_SUPPORTED			(1<<12)
 #define SMRR_LOCK_SUPPORTED		(1<<14)
 
 #define SGX_SUPPORTED			(1<<2)

From 44fcbf84b32bfbc2566b5b08a4681fc29b14285f Mon Sep 17 00:00:00 2001
From: Patrick Rudolph <patrick.rudolph@9elements.com>
Date: Fri, 30 Jan 2026 09:46:52 +0100
Subject: [PATCH 3433/3886] soc/intel/snowridge: Move defines to soc/pci_devs.h

Move the defines for PCI register SMM_FEATURE_CONTROL to the header
soc/pci_devs.h like it's done on other server platforms as well.

While on it add BIT1 that will be used in the following commit.

TEST=Not a function change, thus untested.

Change-Id: Ib05bb129f069ab1a6f4752a2dac829b3b7b41ec9
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91016
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
---
 src/soc/intel/snowridge/include/soc/pci_devs.h | 6 ++++++
 src/soc/intel/snowridge/lockdown.c             | 4 ----
 2 files changed, 6 insertions(+), 4 deletions(-)

diff --git a/src/soc/intel/snowridge/include/soc/pci_devs.h b/src/soc/intel/snowridge/include/soc/pci_devs.h
index ca50bf8eb1..09336c0724 100644
--- a/src/soc/intel/snowridge/include/soc/pci_devs.h
+++ b/src/soc/intel/snowridge/include/soc/pci_devs.h
@@ -68,6 +68,12 @@
 
 /* Stack U0. */
 #define UBOX_DEV_RACU   _UBOX0_DEV(0x00, 1)
+
+#define SMM_FEATURE_CONTROL		0x8c
+#define  SMM_CODE_CHK_EN		BIT(2)
+#define  SMM_FC_CPU_SAVE_EN		BIT(1)
+#define  SMM_FEATURE_CONTROL_LOCK	BIT(0)
+
 #define UBOX_DEV_NCDECS _UBOX0_DEV(0x00, 2)
 
 /* Stack U1. */
diff --git a/src/soc/intel/snowridge/lockdown.c b/src/soc/intel/snowridge/lockdown.c
index b74b74ca4b..485d3413d3 100644
--- a/src/soc/intel/snowridge/lockdown.c
+++ b/src/soc/intel/snowridge/lockdown.c
@@ -8,10 +8,6 @@
 #include <soc/pm.h>
 #include <soc/pmc.h>
 
-#define SMM_FEATURE_CONTROL      0x8c
-#define SMM_CODE_CHK_EN          (1 << 2)
-#define SMM_FEATURE_CONTROL_LOCK (1 << 0)
-
 static void pmc_lockdown_cfg(int chipset_lockdown)
 {
 	pmc_or_mmio32(PMSYNC_TPR_CFG, PCH2CPU_TPR_CFG_LOCK);

From 38baf0c5f6081367355b969af281432d8b8f4f46 Mon Sep 17 00:00:00 2001
From: Jeremy Compostella <jeremy.compostella@intel.com>
Date: Thu, 19 Feb 2026 07:43:35 -0800
Subject: [PATCH 3434/3886] soc/intel/meteorlake: Use common UART device list
 driver

Remove platform-specific uart.c and switch to the common UART device
list driver. This eliminates duplicate code.

The meteorlake uart.c simply defined uart_devices[] array. The common
driver now handles this using the SOC_UART_DEVFN(n) macro defined in
pci_devs.h which uses token concatenation to map to platform-specific
PCI_DEVFN_UARTn definitions.

This commit:
- Selects SOC_INTEL_COMMON_FEATURE and
  SOC_INTEL_COMMON_FEATURE_UART_DEVICES in Kconfig
- Removes uart.c and updates Makefile.mk

Change-Id: Ic791eaa2521a44aba330e149fb0185094dd9ccf7
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91243
Reviewed-by: Kim, Wonkyu <wonkyu.kim@intel.com>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/soc/intel/meteorlake/Kconfig     |  2 ++
 src/soc/intel/meteorlake/Makefile.mk |  2 --
 src/soc/intel/meteorlake/uart.c      | 12 ------------
 3 files changed, 2 insertions(+), 14 deletions(-)
 delete mode 100644 src/soc/intel/meteorlake/uart.c

diff --git a/src/soc/intel/meteorlake/Kconfig b/src/soc/intel/meteorlake/Kconfig
index a0e648a856..b223fa01d2 100644
--- a/src/soc/intel/meteorlake/Kconfig
+++ b/src/soc/intel/meteorlake/Kconfig
@@ -86,6 +86,8 @@ config SOC_INTEL_METEORLAKE
 	select SOC_INTEL_COMMON_BLOCK_THERMAL_BEHIND_PMC
 	select SOC_INTEL_COMMON_BLOCK_XHCI
 	select SOC_INTEL_COMMON_BLOCK_XHCI_ELOG
+	select SOC_INTEL_COMMON_FEATURE
+	select SOC_INTEL_COMMON_FEATURE_UART_DEVICES
 	select SOC_INTEL_COMMON_BASECODE
 	select SOC_INTEL_COMMON_BASECODE_RAMTOP
 	select SOC_INTEL_COMMON_FSP_RESET
diff --git a/src/soc/intel/meteorlake/Makefile.mk b/src/soc/intel/meteorlake/Makefile.mk
index 2ef53f5395..81be9ff856 100644
--- a/src/soc/intel/meteorlake/Makefile.mk
+++ b/src/soc/intel/meteorlake/Makefile.mk
@@ -10,7 +10,6 @@ all-y += gspi.c
 all-y += i2c.c
 all-y += pmutil.c
 all-y += spi.c
-all-y += uart.c
 all-y += gpio.c
 
 bootblock-y += bootblock/bootblock.c
@@ -55,7 +54,6 @@ smm-y += p2sb.c
 smm-y += pmutil.c
 smm-y += smihandler.c
 smm-y += soc_info.c
-smm-y += uart.c
 smm-y += xhci.c
 
 CPPFLAGS_common += -I$(src)/soc/intel/meteorlake
diff --git a/src/soc/intel/meteorlake/uart.c b/src/soc/intel/meteorlake/uart.c
deleted file mode 100644
index 9f549c5ae8..0000000000
--- a/src/soc/intel/meteorlake/uart.c
+++ /dev/null
@@ -1,12 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <commonlib/helpers.h>
-#include <soc/pci_devs.h>
-
-const unsigned int uart_devices[] = {
-	PCI_DEVFN_UART0,
-	PCI_DEVFN_UART1,
-	PCI_DEVFN_UART2,
-};
-
-const int uart_devices_size = ARRAY_SIZE(uart_devices);

From 61dc1e04e05f264fe579a68fa7ffcc5ef5533d9d Mon Sep 17 00:00:00 2001
From: Jeremy Compostella <jeremy.compostella@intel.com>
Date: Thu, 19 Feb 2026 07:43:36 -0800
Subject: [PATCH 3435/3886] soc/intel/tigerlake: Use common UART device list
 driver

Remove platform-specific uart.c and switch to the common UART device
list driver. This eliminates duplicate code.

The tigerlake uart.c simply defined uart_devices[] array. The common
driver now handles this using the PCI_UART_DEVFNn macros defined in
pci_devs.h.

This commit:
- Adds PCI_DEVFN_UART* aliases pointing to PCH_DEVFN_UART* for naming
  consistency with common code
- Selects SOC_INTEL_COMMON_FEATURE and
  SOC_INTEL_COMMON_FEATURE_UART_DEVICES in Kconfig
- Removes uart.c and updates Makefile.mk

Change-Id: I9520bd3f4dd9ccf777e34c79a8c8237adb8b0fed
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91245
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/soc/intel/tigerlake/Kconfig                |  2 ++
 src/soc/intel/tigerlake/Makefile.mk            |  2 --
 src/soc/intel/tigerlake/include/soc/pci_devs.h |  5 +++++
 src/soc/intel/tigerlake/uart.c                 | 18 ------------------
 4 files changed, 7 insertions(+), 20 deletions(-)
 delete mode 100644 src/soc/intel/tigerlake/uart.c

diff --git a/src/soc/intel/tigerlake/Kconfig b/src/soc/intel/tigerlake/Kconfig
index d76ddec335..1d6c21e06f 100644
--- a/src/soc/intel/tigerlake/Kconfig
+++ b/src/soc/intel/tigerlake/Kconfig
@@ -72,6 +72,8 @@ config SOC_INTEL_TIGERLAKE
 	select SOC_INTEL_COMMON_BLOCK_USB4_PCIE
 	select SOC_INTEL_COMMON_BLOCK_USB4_XHCI
 	select SOC_INTEL_COMMON_BLOCK_XHCI_ELOG
+	select SOC_INTEL_COMMON_FEATURE
+	select SOC_INTEL_COMMON_FEATURE_UART_DEVICES
 	select SOC_INTEL_COMMON_FSP_RESET
 	select SOC_INTEL_COMMON_PCH_CLIENT
 	select SOC_INTEL_COMMON_RESET
diff --git a/src/soc/intel/tigerlake/Makefile.mk b/src/soc/intel/tigerlake/Makefile.mk
index 27e07a99b4..19b504362f 100644
--- a/src/soc/intel/tigerlake/Makefile.mk
+++ b/src/soc/intel/tigerlake/Makefile.mk
@@ -10,7 +10,6 @@ all-y += gspi.c
 all-y += i2c.c
 all-y += pmutil.c
 all-y += spi.c
-all-y += uart.c
 
 bootblock-y += bootblock/bootblock.c
 bootblock-y += bootblock/pch.c
@@ -47,7 +46,6 @@ ramstage-$(CONFIG_SOC_INTEL_CRASHLOG) += crashlog_lib.c
 smm-y += p2sb.c
 smm-y += pmutil.c
 smm-y += smihandler.c
-smm-y += uart.c
 smm-y += elog.c
 smm-y += xhci.c
 
diff --git a/src/soc/intel/tigerlake/include/soc/pci_devs.h b/src/soc/intel/tigerlake/include/soc/pci_devs.h
index d93c97f3c3..c615f3bc70 100644
--- a/src/soc/intel/tigerlake/include/soc/pci_devs.h
+++ b/src/soc/intel/tigerlake/include/soc/pci_devs.h
@@ -245,4 +245,9 @@
 #define  PCH_DEV_GBE		_PCH_DEV(ESPI, 6)
 #define  PCH_DEV_TRACEHUB	_PCH_DEV(ESPI, 7)
 
+/* for common code */
+#define PCI_DEVFN_UART0		PCH_DEVFN_UART0
+#define PCI_DEVFN_UART1		PCH_DEVFN_UART1
+#define PCI_DEVFN_UART2		PCH_DEVFN_UART2
+
 #endif
diff --git a/src/soc/intel/tigerlake/uart.c b/src/soc/intel/tigerlake/uart.c
deleted file mode 100644
index fa4760c118..0000000000
--- a/src/soc/intel/tigerlake/uart.c
+++ /dev/null
@@ -1,18 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-/*
- * This file is created based on Intel Tiger Lake Processor PCH Datasheet
- * Document number: 575857
- * Chapter number: 9
- */
-
-#include <commonlib/helpers.h>
-#include <soc/pci_devs.h>
-
-const unsigned int uart_devices[] = {
-	PCH_DEVFN_UART0,
-	PCH_DEVFN_UART1,
-	PCH_DEVFN_UART2,
-};
-
-const int uart_devices_size = ARRAY_SIZE(uart_devices);

From bb95093b8f0b5ae3dfc4f2447f93aa5b11dca855 Mon Sep 17 00:00:00 2001
From: Jeremy Compostella <jeremy.compostella@intel.com>
Date: Thu, 19 Feb 2026 07:43:36 -0800
Subject: [PATCH 3436/3886] soc/intel/jasperlake: Use common UART device list
 driver

Remove platform-specific uart.c and switch to the common UART device
list driver. This eliminates duplicate code.

The jasperlake uart.c simply defined uart_devices[] array. The common
driver now handles this using the PCI_UART_DEVFNn macro defined in
pci_devs.h.

This commit:
- Adds PCI_DEVFN_UART* aliases pointing to PCH_DEVFN_UART* for naming
  consistency with common code
- Selects SOC_INTEL_COMMON_FEATURE and
  SOC_INTEL_COMMON_FEATURE_UART_DEVICES in Kconfig
- Removes uart.c and updates Makefile.mk

Change-Id: I8f7c68c8c44dd9ccf7cb49af8a3561a47d4aacc2
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91246
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
---
 src/soc/intel/jasperlake/Kconfig                |  2 ++
 src/soc/intel/jasperlake/Makefile.mk            |  2 --
 src/soc/intel/jasperlake/include/soc/pci_devs.h |  5 +++++
 src/soc/intel/jasperlake/uart.c                 | 12 ------------
 4 files changed, 7 insertions(+), 14 deletions(-)
 delete mode 100644 src/soc/intel/jasperlake/uart.c

diff --git a/src/soc/intel/jasperlake/Kconfig b/src/soc/intel/jasperlake/Kconfig
index e80028ae80..6de9931de3 100644
--- a/src/soc/intel/jasperlake/Kconfig
+++ b/src/soc/intel/jasperlake/Kconfig
@@ -55,6 +55,8 @@ config SOC_INTEL_JASPERLAKE
 	select SOC_INTEL_COMMON_BLOCK_POWER_LIMIT
 	select SOC_INTEL_COMMON_BLOCK_SMM_IO_TRAP
 	select SOC_INTEL_COMMON_BLOCK_XHCI_ELOG
+	select SOC_INTEL_COMMON_FEATURE
+	select SOC_INTEL_COMMON_FEATURE_UART_DEVICES
 	select SOC_INTEL_COMMON_FSP_RESET
 	select SOC_INTEL_COMMON_PCH_CLIENT
 	select SOC_INTEL_COMMON_RESET
diff --git a/src/soc/intel/jasperlake/Makefile.mk b/src/soc/intel/jasperlake/Makefile.mk
index 1377fff9e0..6346f2d3d2 100644
--- a/src/soc/intel/jasperlake/Makefile.mk
+++ b/src/soc/intel/jasperlake/Makefile.mk
@@ -10,7 +10,6 @@ all-y += gspi.c
 all-y += i2c.c
 all-y += pmutil.c
 all-y += spi.c
-all-y += uart.c
 
 bootblock-y += bootblock/bootblock.c
 bootblock-y += bootblock/pch.c
@@ -47,7 +46,6 @@ smm-y += gpio.c
 smm-y += p2sb.c
 smm-y += pmutil.c
 smm-y += smihandler.c
-smm-y += uart.c
 smm-y += elog.c
 smm-y += xhci.c
 
diff --git a/src/soc/intel/jasperlake/include/soc/pci_devs.h b/src/soc/intel/jasperlake/include/soc/pci_devs.h
index e3276458bf..2d2b96a09e 100644
--- a/src/soc/intel/jasperlake/include/soc/pci_devs.h
+++ b/src/soc/intel/jasperlake/include/soc/pci_devs.h
@@ -193,4 +193,9 @@
 #define  PCH_DEV_GBE		_PCH_DEV(ESPI, 6)
 #define  PCH_DEV_TRACEHUB	_PCH_DEV(ESPI, 7)
 
+/* for common code */
+#define PCI_DEVFN_UART0		PCH_DEVFN_UART0
+#define PCI_DEVFN_UART1		PCH_DEVFN_UART1
+#define PCI_DEVFN_UART2		PCH_DEVFN_UART2
+
 #endif
diff --git a/src/soc/intel/jasperlake/uart.c b/src/soc/intel/jasperlake/uart.c
deleted file mode 100644
index 9946880263..0000000000
--- a/src/soc/intel/jasperlake/uart.c
+++ /dev/null
@@ -1,12 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <commonlib/helpers.h>
-#include <soc/pci_devs.h>
-
-const unsigned int uart_devices[] = {
-	PCH_DEVFN_UART0,
-	PCH_DEVFN_UART1,
-	PCH_DEVFN_UART2,
-};
-
-const int uart_devices_size = ARRAY_SIZE(uart_devices);

From 7b4fb78e34c95ad62b5f4b257cd9bbd09071166c Mon Sep 17 00:00:00 2001
From: Jeremy Compostella <jeremy.compostella@intel.com>
Date: Thu, 19 Feb 2026 07:43:36 -0800
Subject: [PATCH 3437/3886] soc/intel/elkhartlake: Use common UART device list
 driver

Remove platform-specific uart.c and switch to the common UART device
list driver. This eliminates duplicate code.

The elkhartlake uart.c simply defined uart_devices[] array. The common
driver now handles this using the PCI_UART_DEVFNn macro defined in
pci_devs.h.

This commit:
- Adds PCI_DEVFN_UART* aliases pointing to PCH_DEVFN_UART* for naming
  consistency with common code
- Selects SOC_INTEL_COMMON_FEATURE and
  SOC_INTEL_COMMON_FEATURE_UART_DEVICES in Kconfig
- Removes uart.c and updates Makefile.mk

Change-Id: I778faf19128f41509f70d324dd9ccf71d93cab0b
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91247
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
---
 src/soc/intel/elkhartlake/Kconfig                |  2 ++
 src/soc/intel/elkhartlake/Makefile.mk            |  2 --
 src/soc/intel/elkhartlake/include/soc/pci_devs.h |  5 +++++
 src/soc/intel/elkhartlake/uart.c                 | 12 ------------
 4 files changed, 7 insertions(+), 14 deletions(-)
 delete mode 100644 src/soc/intel/elkhartlake/uart.c

diff --git a/src/soc/intel/elkhartlake/Kconfig b/src/soc/intel/elkhartlake/Kconfig
index 6fb4f52d61..79e57e6894 100644
--- a/src/soc/intel/elkhartlake/Kconfig
+++ b/src/soc/intel/elkhartlake/Kconfig
@@ -55,6 +55,8 @@ config SOC_INTEL_ELKHARTLAKE
 	select SOC_INTEL_COMMON_BLOCK_SCS
 	select SOC_INTEL_COMMON_BLOCK_SMM
 	select SOC_INTEL_COMMON_BLOCK_SMM_IO_TRAP
+	select SOC_INTEL_COMMON_FEATURE
+	select SOC_INTEL_COMMON_FEATURE_UART_DEVICES
 	select SOC_INTEL_COMMON_FSP_RESET
 	select SOC_INTEL_COMMON_PCH_CLIENT
 	select SOC_INTEL_COMMON_RESET
diff --git a/src/soc/intel/elkhartlake/Makefile.mk b/src/soc/intel/elkhartlake/Makefile.mk
index b5f5f2ad74..393a90d17c 100644
--- a/src/soc/intel/elkhartlake/Makefile.mk
+++ b/src/soc/intel/elkhartlake/Makefile.mk
@@ -10,7 +10,6 @@ all-y += gspi.c
 all-y += i2c.c
 all-y += pmutil.c
 all-y += spi.c
-all-y += uart.c
 
 bootblock-y += bootblock/bootblock.c
 bootblock-y += bootblock/pch.c
@@ -45,7 +44,6 @@ smm-y += gpio.c
 smm-y += p2sb.c
 smm-y += pmutil.c
 smm-y += smihandler.c
-smm-y += uart.c
 
 verstage-y += gpio.c
 
diff --git a/src/soc/intel/elkhartlake/include/soc/pci_devs.h b/src/soc/intel/elkhartlake/include/soc/pci_devs.h
index 8cf193829c..743c3a8cd6 100644
--- a/src/soc/intel/elkhartlake/include/soc/pci_devs.h
+++ b/src/soc/intel/elkhartlake/include/soc/pci_devs.h
@@ -247,4 +247,9 @@
 #define  PCH_DEV_SPI		_PCH_DEV(ESPI, 5)
 #define  PCH_DEV_TRACEHUB	_PCH_DEV(ESPI, 7)
 
+/* for common code */
+#define PCI_DEVFN_UART0		PCH_DEVFN_UART0
+#define PCI_DEVFN_UART1		PCH_DEVFN_UART1
+#define PCI_DEVFN_UART2		PCH_DEVFN_UART2
+
 #endif
diff --git a/src/soc/intel/elkhartlake/uart.c b/src/soc/intel/elkhartlake/uart.c
deleted file mode 100644
index 9946880263..0000000000
--- a/src/soc/intel/elkhartlake/uart.c
+++ /dev/null
@@ -1,12 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <commonlib/helpers.h>
-#include <soc/pci_devs.h>
-
-const unsigned int uart_devices[] = {
-	PCH_DEVFN_UART0,
-	PCH_DEVFN_UART1,
-	PCH_DEVFN_UART2,
-};
-
-const int uart_devices_size = ARRAY_SIZE(uart_devices);

From e31d32443e84204ed0be0990380b3cf199ad0aa6 Mon Sep 17 00:00:00 2001
From: Pranava Y N <pranavayn@google.com>
Date: Wed, 25 Feb 2026 15:09:03 +0530
Subject: [PATCH 3438/3886] Revert "mb/google/fatcat: Fix Gen4 SSD power
 sequencing"

This reverts commit 970201012365bad68b1a6d71fcbc10f44694007d.

Fatcat RVP is sometimes unable to boot when non-serial image is flashed.
Reverting this CL until permanent verified fix is landed.

BUG=b:487523987
TEST=Able to boot fatcat to OS from Gen4 SSD slot

Change-Id: I5c61879cfb6e5f54d439284d1f75db5bfceddd1d
Signed-off-by: Pranava Y N <pranavayn@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91422
Reviewed-by: <srinivas.kulkarni@intel.com>
Reviewed-by: Avi Uday <aviuday@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Jayvik Desai <jayvik@google.com>
---
 .../google/fatcat/variants/fatcat/fw_config.c     | 15 ++++-----------
 .../google/fatcat/variants/fatcat/gpio.c          |  2 ++
 2 files changed, 6 insertions(+), 11 deletions(-)

diff --git a/src/mainboard/google/fatcat/variants/fatcat/fw_config.c b/src/mainboard/google/fatcat/variants/fatcat/fw_config.c
index 25f9a339df..ccece4647f 100644
--- a/src/mainboard/google/fatcat/variants/fatcat/fw_config.c
+++ b/src/mainboard/google/fatcat/variants/fatcat/fw_config.c
@@ -285,17 +285,14 @@ static const struct pad_config wwan_disable_pads[] = {
 };
 
 /* Gen4 NVME: at the top M.2 slot */
-static const struct pad_config pre_mem_gen4_ssd_pwr_seq1_pads[] = {
+static const struct pad_config pre_mem_gen4_ssd_pwr_pads[] = {
 	/* GPP_B10:     GEN4_SSD_PWREN */
 	PAD_CFG_GPO(GPP_B10, 0, PLTRST),
 };
 
-static const struct pad_config pre_mem_gen4_ssd_pwr_seq2_pads[] = {
+static const struct pad_config gen4_ssd_pads[] = {
 	/* GPP_B10:     GEN4_SSD_PWREN */
 	PAD_CFG_GPO(GPP_B10, 1, PLTRST),
-};
-
-static const struct pad_config gen4_ssd_pads[] = {
 	/* GPP_B09:     M2_GEN4_SSD_RESET_N */
 	PAD_CFG_GPO(GPP_B09, 1, PLTRST),
 };
@@ -621,11 +618,11 @@ void fw_config_configure_pre_mem_gpio(void)
 		GPIO_CONFIGURE_PADS(pre_mem_wwan_pwr_seq1_pads);
 
 	if (fw_config_probe(FW_CONFIG(STORAGE, STORAGE_NVME_GEN4))) {
-		GPIO_CONFIGURE_PADS(pre_mem_gen4_ssd_pwr_seq1_pads);
+		GPIO_CONFIGURE_PADS(pre_mem_gen4_ssd_pwr_pads);
 	} else if (fw_config_probe(FW_CONFIG(STORAGE, STORAGE_NVME_GEN5))) {
 		GPIO_CONFIGURE_PADS(pre_mem_gen5_ssd_pwr_pads);
 	} else if (fw_config_probe(FW_CONFIG(STORAGE, STORAGE_UNKNOWN))) {
-		GPIO_CONFIGURE_PADS(pre_mem_gen4_ssd_pwr_seq1_pads);
+		GPIO_CONFIGURE_PADS(pre_mem_gen4_ssd_pwr_pads);
 		GPIO_CONFIGURE_PADS(pre_mem_gen5_ssd_pwr_pads);
 	}
 
@@ -648,10 +645,6 @@ void fw_config_configure_pre_mem_gpio(void)
 	if (fw_config_probe(FW_CONFIG(FP, FP_PRESENT)))
 		GPIO_CONFIGURE_PADS(pre_mem_fp_enable_pads);
 
-	if (fw_config_probe(FW_CONFIG(STORAGE, STORAGE_NVME_GEN4)) ||
-	    fw_config_probe(FW_CONFIG(STORAGE, STORAGE_UNKNOWN))) {
-		GPIO_CONFIGURE_PADS(pre_mem_gen4_ssd_pwr_seq2_pads);
-	}
 }
 
 void fw_config_gpio_padbased_override(struct pad_config *padbased_table)
diff --git a/src/mainboard/google/fatcat/variants/fatcat/gpio.c b/src/mainboard/google/fatcat/variants/fatcat/gpio.c
index 696fb8ba4d..13e6bbe1e3 100644
--- a/src/mainboard/google/fatcat/variants/fatcat/gpio.c
+++ b/src/mainboard/google/fatcat/variants/fatcat/gpio.c
@@ -57,6 +57,8 @@ static const struct pad_config gpio_table[] = {
 	PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_B03, NONE, DEEP, NF3),
 	/* GPP_B09:     M2_GEN4_SSD_RESET_N */
 	PAD_CFG_GPO(GPP_B09, 1, PLTRST),
+	/* GPP_B10:     GEN4_SSD_PWREN */
+	PAD_CFG_GPO(GPP_B10, 1, PLTRST),
 	/* GPP_B11:     MOD_TCSS1_DISP_HPD3 */
 	PAD_CFG_NF(GPP_B11, NONE, DEEP, NF2),
 	/* GPP_B12:     PM_SLP_S0_N */

From a69d537e61c6dee7e19d29d9bd44405e652746f3 Mon Sep 17 00:00:00 2001
From: Jeremy Compostella <jeremy.compostella@intel.com>
Date: Thu, 19 Feb 2026 07:43:36 -0800
Subject: [PATCH 3439/3886] soc/intel/cannonlake: Use common UART device list
 driver

Remove platform-specific uart.c and switch to the common UART device
list driver. This eliminates duplicate code.

The cannonlake uart.c simply defined uart_devices[] array. The common
driver now handles this using the PCI_UART_DEVFNn macro defined in
pci_devs.h.

This commit:
- Adds PCI_DEVFN_UART* aliases pointing to PCH_DEVFN_UART* for naming
  consistency with common code
- Selects SOC_INTEL_COMMON_FEATURE and
  SOC_INTEL_COMMON_FEATURE_UART_DEVICES in Kconfig
- Removes uart.c and updates Makefile.mk

Change-Id: I819dc9853b4b44eb97238c1d5ad464dd9ccf7f9a
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91248
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/soc/intel/cannonlake/Kconfig                |  2 ++
 src/soc/intel/cannonlake/Makefile.mk            |  6 ------
 src/soc/intel/cannonlake/include/soc/pci_devs.h |  5 +++++
 src/soc/intel/cannonlake/uart.c                 | 12 ------------
 4 files changed, 7 insertions(+), 18 deletions(-)
 delete mode 100644 src/soc/intel/cannonlake/uart.c

diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig
index 738371bc1b..d7075d0d0d 100644
--- a/src/soc/intel/cannonlake/Kconfig
+++ b/src/soc/intel/cannonlake/Kconfig
@@ -59,6 +59,8 @@ config SOC_INTEL_CANNONLAKE_BASE
 	select SOC_INTEL_COMMON_BLOCK_THERMAL_PCI_DEV
 	select SOC_INTEL_COMMON_BLOCK_XHCI
 	select SOC_INTEL_COMMON_BLOCK_XHCI_ELOG
+	select SOC_INTEL_COMMON_FEATURE
+	select SOC_INTEL_COMMON_FEATURE_UART_DEVICES
 	select SOC_INTEL_COMMON_FSP_RESET
 	select SOC_INTEL_COMMON_NHLT
 	select SOC_INTEL_COMMON_PCH_CLIENT
diff --git a/src/soc/intel/cannonlake/Makefile.mk b/src/soc/intel/cannonlake/Makefile.mk
index 96c02074ef..fc51fa0067 100644
--- a/src/soc/intel/cannonlake/Makefile.mk
+++ b/src/soc/intel/cannonlake/Makefile.mk
@@ -15,7 +15,6 @@ bootblock-y += i2c.c
 bootblock-y += spi.c
 bootblock-y += lpc.c
 bootblock-y += p2sb.c
-bootblock-y += uart.c
 
 romstage-y += cnl_memcfg_init.c
 romstage-y += gspi.c
@@ -25,7 +24,6 @@ romstage-y += pcie_rp.c
 romstage-y += pmutil.c
 romstage-y += reset.c
 romstage-y += spi.c
-romstage-y += uart.c
 
 ramstage-y += acpi.c
 ramstage-y += chip.c
@@ -46,7 +44,6 @@ ramstage-y += pmutil.c
 ramstage-y += reset.c
 ramstage-y += spi.c
 ramstage-y += systemagent.c
-ramstage-y += uart.c
 ramstage-y += vr_config.c
 ramstage-y += sd.c
 ramstage-y += xhci.c
@@ -55,20 +52,17 @@ smm-y += elog.c
 smm-y += p2sb.c
 smm-y += pmutil.c
 smm-y += smihandler.c
-smm-y += uart.c
 smm-y += xhci.c
 
 postcar-y += pmutil.c
 postcar-y += i2c.c
 postcar-y += gspi.c
 postcar-y += spi.c
-postcar-y += uart.c
 
 verstage-y += gspi.c
 verstage-y += i2c.c
 verstage-y += pmutil.c
 verstage-y += spi.c
-verstage-y += uart.c
 
 ifeq ($(CONFIG_SOC_INTEL_CANNONLAKE_PCH_H),y)
 bootblock-y += gpio_cnp_h.c
diff --git a/src/soc/intel/cannonlake/include/soc/pci_devs.h b/src/soc/intel/cannonlake/include/soc/pci_devs.h
index 6998eb1022..d5aa36b554 100644
--- a/src/soc/intel/cannonlake/include/soc/pci_devs.h
+++ b/src/soc/intel/cannonlake/include/soc/pci_devs.h
@@ -204,4 +204,9 @@
 #define  PCH_DEV_GBE		_PCH_DEV(LPC, 6)
 #define  PCH_DEV_TRACEHUB	_PCH_DEV(LPC, 7)
 
+/* for common code */
+#define PCI_DEVFN_UART0		PCH_DEVFN_UART0
+#define PCI_DEVFN_UART1		PCH_DEVFN_UART1
+#define PCI_DEVFN_UART2		PCH_DEVFN_UART2
+
 #endif
diff --git a/src/soc/intel/cannonlake/uart.c b/src/soc/intel/cannonlake/uart.c
deleted file mode 100644
index 9946880263..0000000000
--- a/src/soc/intel/cannonlake/uart.c
+++ /dev/null
@@ -1,12 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <commonlib/helpers.h>
-#include <soc/pci_devs.h>
-
-const unsigned int uart_devices[] = {
-	PCH_DEVFN_UART0,
-	PCH_DEVFN_UART1,
-	PCH_DEVFN_UART2,
-};
-
-const int uart_devices_size = ARRAY_SIZE(uart_devices);

From acd8f42410c3204e0ea1a7e4f4b8be1c5d0e489e Mon Sep 17 00:00:00 2001
From: Jeremy Compostella <jeremy.compostella@intel.com>
Date: Thu, 19 Feb 2026 08:23:33 -0800
Subject: [PATCH 3440/3886] soc/intel/skylake: Use common UART device list
 driver

Remove platform-specific uart.c and switch to the common UART device
list driver. This eliminates 12 lines of duplicate code.

The Skylake uart.c simply defined uart_devices[] array. The common
driver now handles this using the PCI_DEVFN_UARTn macros defined in
pci_devs.h.

This commit:
- Adds PCI_DEVFN_UART* aliases pointing to PCH_DEVFN_UART* for naming
  consistency with common code
- Selects SOC_INTEL_COMMON_FEATURE and
  SOC_INTEL_COMMON_FEATURE_UART_DEVICES in Kconfig
- Removes uart.c and updates Makefile.mk

Change-Id: Id686de6bb4dd9ccf78644817881b2abfb5ae0352
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91249
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
---
 src/soc/intel/skylake/Kconfig                |  2 ++
 src/soc/intel/skylake/Makefile.mk            |  6 ------
 src/soc/intel/skylake/include/soc/pci_devs.h |  5 +++++
 src/soc/intel/skylake/uart.c                 | 12 ------------
 4 files changed, 7 insertions(+), 18 deletions(-)
 delete mode 100644 src/soc/intel/skylake/uart.c

diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig
index 7c530f2c75..aa64511249 100644
--- a/src/soc/intel/skylake/Kconfig
+++ b/src/soc/intel/skylake/Kconfig
@@ -58,6 +58,8 @@ config SOC_INTEL_COMMON_SKYLAKE_BASE
 	select SOC_INTEL_COMMON_BLOCK_THERMAL_PCI_DEV
 	select SOC_INTEL_COMMON_BLOCK_UART
 	select SOC_INTEL_COMMON_BLOCK_XHCI_ELOG
+	select SOC_INTEL_COMMON_FEATURE
+	select SOC_INTEL_COMMON_FEATURE_UART_DEVICES
 	select SOC_INTEL_COMMON_FSP_RESET
 	select SOC_INTEL_COMMON_PCH_CLIENT
 	select SOC_INTEL_COMMON_NHLT
diff --git a/src/soc/intel/skylake/Makefile.mk b/src/soc/intel/skylake/Makefile.mk
index 04ba96b7dd..de251f2de3 100644
--- a/src/soc/intel/skylake/Makefile.mk
+++ b/src/soc/intel/skylake/Makefile.mk
@@ -17,14 +17,12 @@ bootblock-y += p2sb.c
 bootblock-y += pmutil.c
 bootblock-y += spi.c
 bootblock-y += lpc.c
-bootblock-y += uart.c
 
 verstage-y += gpio.c
 verstage-y += gspi.c
 verstage-y += pmutil.c
 verstage-y += i2c.c
 verstage-y += spi.c
-verstage-y += uart.c
 
 romstage-y += gpio.c
 romstage-y += gspi.c
@@ -34,7 +32,6 @@ romstage-y += pcie_rp.c
 romstage-y += pmutil.c
 romstage-y += reset.c
 romstage-y += spi.c
-romstage-y += uart.c
 
 ramstage-$(CONFIG_HAVE_ACPI_TABLES) += acpi.c
 ramstage-y += chip.c
@@ -58,7 +55,6 @@ ramstage-y += reset.c
 ramstage-y += sd.c
 ramstage-y += spi.c
 ramstage-y += systemagent.c
-ramstage-y += uart.c
 ramstage-y += vr_config.c
 ramstage-y += xhci.c
 
@@ -67,13 +63,11 @@ smm-y += gpio.c
 smm-y += p2sb.c
 smm-y += pmutil.c
 smm-y += smihandler.c
-smm-y += uart.c
 smm-y += xhci.c
 
 postcar-y += gspi.c
 postcar-y += spi.c
 postcar-y += i2c.c
-postcar-y += uart.c
 
 ifeq ($(CONFIG_SKYLAKE_SOC_PCH_H),y)
 ifeq ($(CONFIG_MAINBOARD_SUPPORTS_SKYLAKE_CPU),y)
diff --git a/src/soc/intel/skylake/include/soc/pci_devs.h b/src/soc/intel/skylake/include/soc/pci_devs.h
index 661ed5cd65..b1e5208523 100644
--- a/src/soc/intel/skylake/include/soc/pci_devs.h
+++ b/src/soc/intel/skylake/include/soc/pci_devs.h
@@ -187,4 +187,9 @@
 #define  PCH_DEV_GBE		_PCH_DEV(LPC, 6)
 #define  PCH_DEV_TRACEHUB	_PCH_DEV(LPC, 7)
 
+/* for common code */
+#define PCI_DEVFN_UART0		PCH_DEVFN_UART0
+#define PCI_DEVFN_UART1		PCH_DEVFN_UART1
+#define PCI_DEVFN_UART2		PCH_DEVFN_UART2
+
 #endif
diff --git a/src/soc/intel/skylake/uart.c b/src/soc/intel/skylake/uart.c
deleted file mode 100644
index 9946880263..0000000000
--- a/src/soc/intel/skylake/uart.c
+++ /dev/null
@@ -1,12 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <commonlib/helpers.h>
-#include <soc/pci_devs.h>
-
-const unsigned int uart_devices[] = {
-	PCH_DEVFN_UART0,
-	PCH_DEVFN_UART1,
-	PCH_DEVFN_UART2,
-};
-
-const int uart_devices_size = ARRAY_SIZE(uart_devices);

From 61ce86ea3edfbae4c3470778c6d43e4fa37a07d1 Mon Sep 17 00:00:00 2001
From: Uwe Poeche <uwe.poeche@siemens.com>
Date: Tue, 3 Feb 2026 15:31:25 +0100
Subject: [PATCH 3441/3886] mb/siemens/mc_ehl6: Reduce clock rate for I2C1

Signal integrity measurement on I2C1 bus showed not optimal rise time.
Therefore the clock frequency is reduced from 400kHz to 100kHz to reach
optimal signal integrity also during coreboot runtime.

TEST=Signal integrity measurement during coreboot runtime.

Change-Id: I9721ede7aa645b2ca46f377bbe557f78c36581f6
Signed-off-by: Uwe Poeche <uwe.poeche@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91079
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/siemens/mc_ehl/variants/mc_ehl6/devicetree.cb | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/src/mainboard/siemens/mc_ehl/variants/mc_ehl6/devicetree.cb b/src/mainboard/siemens/mc_ehl/variants/mc_ehl6/devicetree.cb
index 5180770908..f47fde0cab 100644
--- a/src/mainboard/siemens/mc_ehl/variants/mc_ehl6/devicetree.cb
+++ b/src/mainboard/siemens/mc_ehl/variants/mc_ehl6/devicetree.cb
@@ -111,6 +111,12 @@ chip soc/intel/elkhartlake
 		[PchSerialIoIndexI2C6] = 1,
         }"
 
+	register "common_soc_config" = "{
+		.i2c[1] = {
+			.speed = I2C_SPEED_STANDARD,
+		},
+	}"
+
 	register "SerialIoUartMode" = "{
 		[PchSerialIoIndexUART0] = PchSerialIoPci,
 		[PchSerialIoIndexUART1] = PchSerialIoPci,

From 5ac3e402820475a55e03836ad9e77872d9d7d2e8 Mon Sep 17 00:00:00 2001
From: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Date: Mon, 23 Feb 2026 16:19:11 +0800
Subject: [PATCH 3442/3886] mb/google/brox/var/caboc: Probe LGD touchscreen by
 fw_config

1. Probe with fw_config TOUCH_LGD_HID_I2C.
2. Update slave address to 0x10.

BUG=b:483588481
TEST=build brox coreboot image

Change-Id: I1286679f840b8335ab1877bf1c4e8f72d5704586
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91384
Reviewed-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/google/brox/variants/caboc/overridetree.cb | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/src/mainboard/google/brox/variants/caboc/overridetree.cb b/src/mainboard/google/brox/variants/caboc/overridetree.cb
index 0587d16324..cded4fd875 100644
--- a/src/mainboard/google/brox/variants/caboc/overridetree.cb
+++ b/src/mainboard/google/brox/variants/caboc/overridetree.cb
@@ -23,6 +23,7 @@ fw_config
 		option TOUCH_UNKNOWN		0
 		option TOUCH_ELAN_HID_I2C	1
 		option TOUCH_G2TOUCH_HID_I2C	2
+		option TOUCH_LGD_HID_I2C	3
 	end
 end
 
@@ -432,7 +433,9 @@ chip soc/intel/alderlake
 				register "generic.has_power_resource" = "1"
 				register "generic.use_gpio_for_status" = "true"
 				register "hid_desc_reg_offset" = "0x00"
-				device i2c 34 on end
+				device i2c 10 on
+					probe PANEL TOUCH_LGD_HID_I2C
+				end
 			end
 		end
 		device ref gspi1 on

From c069dc3eb17db88a6fb60da7aedf91d0eb2ce404 Mon Sep 17 00:00:00 2001
From: Luca Lai <luca.lai@lcfc.corp-partner.google.com>
Date: Tue, 24 Feb 2026 16:08:13 +0800
Subject: [PATCH 3443/3886] mb/google/fatcat/var/ruby: Add settings for
 resolving EE noise
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Because of EE noise issue, so add acoustic mitigation items.

Acoustic Noise Mitigation → Enable
Slow Slew Rate for IAcore Domain → <Fast/4>
Slow Slew Rate for GT Domain → <Fast/2>
Slow Slew Rate for Ecore Domain →  <Fast/4>
IAcore Disable Fast Package C-state ramp → True
GT Disable Fast Package C-state ramp → True
Ecore Disable Fast Package C-state ramp → True
P-Core Hysteresis  →  <3>
E-Core Hysteresis  →  <3>

BUG=b:479695733
TEST=Build and boot to OS, check EE noise are resolved.

Change-Id: I5d96cb3e87e9e5a2260b278746b7fce72be4fb59
Signed-off-by: Luca Lai <luca.lai@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91412
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 .../google/fatcat/variants/ruby/overridetree.cb    | 14 ++++++++++++++
 1 file changed, 14 insertions(+)

diff --git a/src/mainboard/google/fatcat/variants/ruby/overridetree.cb b/src/mainboard/google/fatcat/variants/ruby/overridetree.cb
index 1c1399dc21..6b37f24a0f 100644
--- a/src/mainboard/google/fatcat/variants/ruby/overridetree.cb
+++ b/src/mainboard/google/fatcat/variants/ruby/overridetree.cb
@@ -73,6 +73,20 @@ chip soc/intel/pantherlake
 		[VR_DOMAIN_SA] = 38 * 4
 	}"
 
+	# Acoustic Noise settings and slew rate configuration:
+	register "enable_acoustic_noise_mitigation" = "true"
+	# Slew rate for IA Domain: Fast/4
+	register "slow_slew_rate_config[VR_DOMAIN_IA]" = "SLEW_FAST_4"
+	# Slew rate for GT Domain: Fast/2
+	register "slow_slew_rate_config[VR_DOMAIN_GT]" = "SLEW_FAST_2"
+	# Slew rate for ATOM Domain: Fast/4
+	register "slow_slew_rate_config[VR_DOMAIN_ATOM]" = "SLEW_FAST_4"
+	register "disable_fast_pkgc_ramp[VR_DOMAIN_IA]" = "true"
+	register "disable_fast_pkgc_ramp[VR_DOMAIN_GT]" = "true"
+	register "disable_fast_pkgc_ramp[VR_DOMAIN_ATOM]" = "true"
+	register "pcore_hysteresis_window_ms" = "3"
+	register "ecore_hysteresis_window_ms" = "3"
+
 	register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC_SKIP)"	# USB2_C0
 	register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC_SKIP)"	# USB2_C1
 	register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # USB HUB (USB2 Camera)

From 57e30e6b9db19d21bfbb56f09bbc32c17e89ab1f Mon Sep 17 00:00:00 2001
From: Kenneth Chan <kenneth.chan@quanta.corp-partner.google.com>
Date: Wed, 4 Feb 2026 18:15:01 +0800
Subject: [PATCH 3444/3886] mb/google/brask/var/moxoe: Switch memory to DDR5

Moxoe uses DDR5 SODIMM. Configure the board to support DDR5.

BUG=b:481186489
TEST=Builds successfully for moxoe.

Change-Id: Ic2f35dab77c24863cf63f6672ba14cbb560edf14
Signed-off-by: Kenneth Chan <kenneth.chan@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91089
Reviewed-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 .../google/brya/variants/moxoe/Makefile.mk    |  1 +
 .../google/brya/variants/moxoe/memory.c       | 45 +++++++++++++++++++
 2 files changed, 46 insertions(+)
 create mode 100644 src/mainboard/google/brya/variants/moxoe/memory.c

diff --git a/src/mainboard/google/brya/variants/moxoe/Makefile.mk b/src/mainboard/google/brya/variants/moxoe/Makefile.mk
index e31aaa1707..2b274c69e2 100644
--- a/src/mainboard/google/brya/variants/moxoe/Makefile.mk
+++ b/src/mainboard/google/brya/variants/moxoe/Makefile.mk
@@ -1,6 +1,7 @@
 # SPDX-License-Identifier: GPL-2.0-only
 bootblock-y += gpio.c
 
+romstage-y += memory.c
 romstage-y += gpio.c
 
 ramstage-y += gpio.c
diff --git a/src/mainboard/google/brya/variants/moxoe/memory.c b/src/mainboard/google/brya/variants/moxoe/memory.c
new file mode 100644
index 0000000000..742ce7fe3a
--- /dev/null
+++ b/src/mainboard/google/brya/variants/moxoe/memory.c
@@ -0,0 +1,45 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <baseboard/gpio.h>
+#include <baseboard/variants.h>
+#include <gpio.h>
+#include <soc/romstage.h>
+
+static const struct mb_cfg ddr5_mem_config = {
+	.type = MEM_TYPE_DDR5,
+
+	.rcomp = {
+		/* Baseboard uses only 100ohm Rcomp resistors */
+		.resistor = 100,
+
+		/* Baseboard Rcomp target values */
+		.targets = {50, 20, 25, 25, 25},
+	},
+
+	.LpDdrDqDqsReTraining = 1,
+
+	.ect = 1, /* Early Command Training */
+
+	.UserBd = BOARD_TYPE_MOBILE,
+
+	.ddr_config = {
+		.dq_pins_interleaved = false,
+	},
+};
+
+const struct mb_cfg *__weak variant_memory_params(void)
+{
+	return &ddr5_mem_config;
+}
+
+bool __weak variant_is_half_populated(void)
+{
+	return false;
+}
+
+void __weak variant_get_spd_info(struct mem_spd *spd_info)
+{
+	spd_info->topo = MEM_TOPO_DIMM_MODULE;
+	spd_info->smbus[0].addr_dimm[0] = 0x50;
+	spd_info->smbus[1].addr_dimm[0] = 0x52;
+}

From 800db242bd4247c4726307752335ede9e4e4d712 Mon Sep 17 00:00:00 2001
From: Angel Pons <th3fanbus@gmail.com>
Date: Mon, 23 Feb 2026 17:50:12 +0100
Subject: [PATCH 3445/3886] {soc,sb}/intel: Drop named object from ASL `GPLD`
 method
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Creation of named objects within a method is highly inefficient, as per
IASL's remarks during DSDT compilation. But it is possible to use local
variables instead of named objects to store a package.

Update the `GPLD` method to use a local variable, instead of creating a
named object. While at it, unify cosmetics of the several copies of the
method across the codebase.

TEST: Build coreboot for the ASRock Z97 Extreme6 (Lynx Point) and run:
  - acpiexec -b "Evaluate _SB.PCI0.XHCI.HUB7.GPLD 0" build/dsdt.aml
  - acpiexec -b "Evaluate _SB.PCI0.XHCI.HUB7.GPLD 1" build/dsdt.aml
Observe return value is the same before and after this change.

Change-Id: Id66322150c90309f42f574584728c6b1db353c0c
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91390
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/soc/intel/baytrail/acpi/xhci.asl          | 14 +++----
 src/soc/intel/broadwell/pch/acpi/xhci.asl     | 10 ++---
 src/soc/intel/skylake/acpi/xhci.asl           | 20 ++++------
 src/southbridge/intel/bd82x6x/acpi/usb.asl    | 40 ++++++++-----------
 src/southbridge/intel/lynxpoint/acpi/xhci.asl | 10 ++---
 5 files changed, 41 insertions(+), 53 deletions(-)

diff --git a/src/soc/intel/baytrail/acpi/xhci.asl b/src/soc/intel/baytrail/acpi/xhci.asl
index 368f34faad..4e1be831b9 100644
--- a/src/soc/intel/baytrail/acpi/xhci.asl
+++ b/src/soc/intel/baytrail/acpi/xhci.asl
@@ -12,18 +12,18 @@ Device (XHCI)
 
 		// GPLD: Generate Port Location Data (PLD)
 		Method (GPLD, 1, Serialized) {
-			Name (PCKG, Package (0x01) {
+			Local0 = Package () {
 				Buffer (0x10) {}
-			})
+			}
 
-			// REV: Revision 0x02 for ACPI 5.0
-			CreateField (DerefOf (PCKG[0]), 0, 0x07, REV)
-			REV = 0x02
+			// REV: Revision 2 for ACPI 5.0
+			CreateField (DerefOf (Local0[0]), 0, 7, REV)
+			REV = 2
 
 			// VISI: Port visibility to user per port
-			CreateField (DerefOf (PCKG[0]), 0x40, 1, VISI)
+			CreateField (DerefOf (Local0[0]), 0x40, 1, VISI)
 			VISI = Arg0
-			Return (PCKG)
+			Return (Local0)
 		}
 
 		Device (PRT1) { Name (_ADR, 1) }
diff --git a/src/soc/intel/broadwell/pch/acpi/xhci.asl b/src/soc/intel/broadwell/pch/acpi/xhci.asl
index 0656a6cf2a..e98bd42637 100644
--- a/src/soc/intel/broadwell/pch/acpi/xhci.asl
+++ b/src/soc/intel/broadwell/pch/acpi/xhci.asl
@@ -330,18 +330,18 @@ Device (XHCI)
 
 		// GPLD: Generate Port Location Data (PLD)
 		Method (GPLD, 1, Serialized) {
-			Name (PCKG, Package () {
+			Local0 = Package () {
 				Buffer (0x10) {}
-			})
+			}
 
 			// REV: Revision 2 for ACPI 5.0
-			CreateField (DerefOf (PCKG [0]), 0, 7, REV)
+			CreateField (DerefOf (Local0[0]), 0, 7, REV)
 			REV = 2
 
 			// VISI: Port visibility to user per port
-			CreateField (DerefOf (PCKG [0]), 0x40, 1, VISI)
+			CreateField (DerefOf (Local0[0]), 0x40, 1, VISI)
 			VISI = Arg0
-			Return (PCKG)
+			Return (Local0)
 		}
 
 		Device (PRT1) { Name (_ADR, 1) } // USB Port 0
diff --git a/src/soc/intel/skylake/acpi/xhci.asl b/src/soc/intel/skylake/acpi/xhci.asl
index bfe6c6df77..5ce7b0d809 100644
--- a/src/soc/intel/skylake/acpi/xhci.asl
+++ b/src/soc/intel/skylake/acpi/xhci.asl
@@ -159,23 +159,19 @@ Device (XHCI)
 		Name (_ADR, 0)
 
 		// GPLD: Generate Port Location Data (PLD)
-		Method (GPLD, 1, Serialized)
-		 {
-
-			Name (PCKG, Package (0x01)
-			{
+		Method (GPLD, 1, Serialized) {
+			Local0 = Package () {
 				Buffer (0x10) {}
-			})
+			}
 
-			// REV: Revision 0x02 for ACPI 5.0
-			CreateField (DerefOf (PCKG[0]), 0, 0x07, REV)
-			REV = 0x02
+			// REV: Revision 2 for ACPI 5.0
+			CreateField (DerefOf (Local0[0]), 0, 7, REV)
+			REV = 2
 
 			// VISI: Port visibility to user per port
-			CreateField (DerefOf (PCKG[0]), 0x40, 1, VISI)
+			CreateField (DerefOf (Local0[0]), 0x40, 1, VISI)
 			VISI = Arg0
-
-			Return (PCKG)
+			Return (Local0)
 		}
 
 		/* USB2 */
diff --git a/src/southbridge/intel/bd82x6x/acpi/usb.asl b/src/southbridge/intel/bd82x6x/acpi/usb.asl
index 3e2ba78db4..4d80c40e1b 100644
--- a/src/southbridge/intel/bd82x6x/acpi/usb.asl
+++ b/src/southbridge/intel/bd82x6x/acpi/usb.asl
@@ -26,25 +26,20 @@ Device (EHC1)
 	{
 		Name (_ADR, 0x00000000)
 
-
 		// GPLD: Generate Port Location Data (PLD)
-		Method (GPLD, 1, Serialized)
-		 {
-
-			Name (PCKG, Package (0x01)
-			{
+		Method (GPLD, 1, Serialized) {
+			Local0 = Package () {
 				Buffer (0x10) {}
-			})
+			}
 
-			// REV: Revision 0x02 for ACPI 5.0
-			CreateField (DerefOf (PCKG [0]), 0, 0x07, REV)
-			REV = 0x02
+			// REV: Revision 2 for ACPI 5.0
+			CreateField (DerefOf (Local0[0]), 0, 7, REV)
+			REV = 2
 
 			// VISI: Port visibility to user per port
-			CreateField (DerefOf (PCKG [0]), 0x40, 1, VISI)
+			CreateField (DerefOf (Local0[0]), 0x40, 1, VISI)
 			VISI = Arg0
-
-			Return (PCKG)
+			Return (Local0)
 		}
 
 		// How many are there?
@@ -82,22 +77,19 @@ Device (EHC2)
 		Name (_ADR, 0x00000000)
 
 		// GPLD: Generate Port Location Data (PLD)
-		Method (GPLD, 1, Serialized)
-		 {
-			Name (PCKG, Package (0x01)
-			{
+		Method (GPLD, 1, Serialized) {
+			Local0 = Package () {
 				Buffer (0x10) {}
-			})
+			}
 
-			// REV: Revision 0x02 for ACPI 5.0
-			CreateField (DerefOf (PCKG [0]), 0, 0x07, REV)
-			REV = 0x02
+			// REV: Revision 2 for ACPI 5.0
+			CreateField (DerefOf (Local0[0]), 0, 7, REV)
+			REV = 2
 
 			// VISI: Port visibility to user per port
-			CreateField (DerefOf (PCKG [0]), 0x40, 1, VISI)
+			CreateField (DerefOf (Local0[0]), 0x40, 1, VISI)
 			VISI = Arg0
-
-			Return (PCKG)
+			Return (Local0)
 		}
 
 		// How many are there?
diff --git a/src/southbridge/intel/lynxpoint/acpi/xhci.asl b/src/southbridge/intel/lynxpoint/acpi/xhci.asl
index c7b0c181ed..d059e08815 100644
--- a/src/southbridge/intel/lynxpoint/acpi/xhci.asl
+++ b/src/southbridge/intel/lynxpoint/acpi/xhci.asl
@@ -364,18 +364,18 @@ Device (XHCI)
 
 		// GPLD: Generate Port Location Data (PLD)
 		Method (GPLD, 1, Serialized) {
-			Name (PCKG, Package () {
+			Local0 = Package () {
 				Buffer (0x10) {}
-			})
+			}
 
 			// REV: Revision 2 for ACPI 5.0
-			CreateField (DerefOf (PCKG [0]), 0, 7, REV)
+			CreateField (DerefOf (Local0[0]), 0, 7, REV)
 			REV = 2
 
 			// VISI: Port visibility to user per port
-			CreateField (DerefOf (PCKG [0]), 0x40, 1, VISI)
+			CreateField (DerefOf (Local0[0]), 0x40, 1, VISI)
 			VISI = Arg0
-			Return (PCKG)
+			Return (Local0)
 		}
 
 		Device (PRT1) { Name (_ADR, 1) } // USB Port 0

From 4028996c9d085de94b2a246317fb523356f655c8 Mon Sep 17 00:00:00 2001
From: Luca Lai <luca.lai@lcfc.corp-partner.google.com>
Date: Thu, 12 Feb 2026 14:41:07 +0800
Subject: [PATCH 3446/3886] mb/google/nissa/var/pujjoquince: Add support for
 Micron MT62F1G32D2DS-031RF

Add Micron MT62F1G32D2DS-031RF memory part to mem_parts_used.txt
and generate corresponding SPD ID entry.

BUG=b:483845259
TEST=Use part_id_gen to generate related settings

Change-Id: I0476c4dcc55204b8fc278d969fa0f09462671b8c
Signed-off-by: Luca Lai <luca.lai@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91172
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
---
 src/mainboard/google/brya/variants/pujjolo/memory/Makefile.mk    | 1 +
 .../google/brya/variants/pujjolo/memory/dram_id.generated.txt    | 1 +
 .../google/brya/variants/pujjolo/memory/mem_parts_used.txt       | 1 +
 3 files changed, 3 insertions(+)

diff --git a/src/mainboard/google/brya/variants/pujjolo/memory/Makefile.mk b/src/mainboard/google/brya/variants/pujjolo/memory/Makefile.mk
index b4d593dccf..b1092e4170 100644
--- a/src/mainboard/google/brya/variants/pujjolo/memory/Makefile.mk
+++ b/src/mainboard/google/brya/variants/pujjolo/memory/Makefile.mk
@@ -8,3 +8,4 @@ SPD_SOURCES += spd/lp5/set-0/spd-9.hex      # ID = 0(0b0000)  Parts = K3KL6L60GM
 SPD_SOURCES += spd/lp5/set-0/spd-7.hex      # ID = 1(0b0001)  Parts = K3KL8L80CM-MGCT
 SPD_SOURCES += spd/lp5/set-0/spd-11.hex      # ID = 2(0b0010)  Parts = H58G56CK8BX146
 SPD_SOURCES += spd/lp5/set-0/spd-1.hex      # ID = 3(0b0011)  Parts = H9JCNNNBK3MLYR-N6E
+SPD_SOURCES += spd/lp5/set-0/spd-3.hex      # ID = 4(0b0100)  Parts = MT62F1G32D2DS-031RF WT:C
diff --git a/src/mainboard/google/brya/variants/pujjolo/memory/dram_id.generated.txt b/src/mainboard/google/brya/variants/pujjolo/memory/dram_id.generated.txt
index 3d03fa66a3..a29454e5b5 100644
--- a/src/mainboard/google/brya/variants/pujjolo/memory/dram_id.generated.txt
+++ b/src/mainboard/google/brya/variants/pujjolo/memory/dram_id.generated.txt
@@ -8,3 +8,4 @@ K3KL6L60GM-MGCT                0 (0000)
 K3KL8L80CM-MGCT                1 (0001)
 H58G56CK8BX146                 2 (0010)
 H9JCNNNBK3MLYR-N6E             3 (0011)
+MT62F1G32D2DS-031RF WT:C       4 (0100)
diff --git a/src/mainboard/google/brya/variants/pujjolo/memory/mem_parts_used.txt b/src/mainboard/google/brya/variants/pujjolo/memory/mem_parts_used.txt
index e1102d6c26..a1fac3fa94 100644
--- a/src/mainboard/google/brya/variants/pujjolo/memory/mem_parts_used.txt
+++ b/src/mainboard/google/brya/variants/pujjolo/memory/mem_parts_used.txt
@@ -13,3 +13,4 @@ K3KL6L60GM-MGCT
 K3KL8L80CM-MGCT
 H58G56CK8BX146
 H9JCNNNBK3MLYR-N6E
+MT62F1G32D2DS-031RF WT:C

From 5f9a1ad962a316ae3fb8c5537bfdbc00e316a02b Mon Sep 17 00:00:00 2001
From: Subrata Banik <subratabanik@google.com>
Date: Mon, 23 Feb 2026 09:00:28 +0530
Subject: [PATCH 3447/3886] ec/google/chromeec: Add API to turn off lightbar

Implement google_chromeec_lightbar_off() to allow the host to
explicitly disable the Chrome EC lightbar. This is achieved by
sending the LIGHTBAR_CMD_OFF sub-command via the multiplexed
EC_CMD_LIGHTBAR_CMD host command.

This API is useful for power-saving scenarios or UI synchronization
during specific boot modes, such as low-battery or off-mode charging.

BUG=None
TEST=Verified that the lightbar turns off when this function is
called on supported hardware.

Change-Id: Ic118dbd5e9af64d06490dd16aa115aca2c1df3a5
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91377
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/ec/google/chromeec/ec.c | 25 +++++++++++++++++++++++++
 src/ec/google/chromeec/ec.h | 10 ++++++++++
 2 files changed, 35 insertions(+)

diff --git a/src/ec/google/chromeec/ec.c b/src/ec/google/chromeec/ec.c
index e6de2c9810..5fe90c8e39 100644
--- a/src/ec/google/chromeec/ec.c
+++ b/src/ec/google/chromeec/ec.c
@@ -1982,6 +1982,31 @@ int google_chromeec_set_lightbar_rgb(unsigned int led, int red, int green,
 	return google_chromeec_command(&cmd);
 }
 
+/*
+ * Sends a command to turn off the Chrome EC lightbar.
+ *
+ * This function packages a LIGHTBAR_CMD_OFF sub-command into a standard
+ * EC_CMD_LIGHTBAR_CMD packet.
+ *
+ * @return 0 on success, non-zero error code from the EC transport on failure.
+ */
+int google_chromeec_lightbar_off(void)
+{
+	const struct ec_params_lightbar req = {
+		.cmd = LIGHTBAR_CMD_OFF,
+	};
+
+	struct chromeec_command cmd = {
+		.cmd_code = EC_CMD_LIGHTBAR_CMD,
+		.cmd_size_out = 0,
+		.cmd_data_out = NULL,
+		.cmd_size_in = sizeof(req),
+		.cmd_data_in = &req,
+	};
+
+	return google_chromeec_command(&cmd);
+}
+
 /*
  * Check if the battery is critically low and not currently charging.
  *
diff --git a/src/ec/google/chromeec/ec.h b/src/ec/google/chromeec/ec.h
index 075694bd4a..79aa69bcf8 100644
--- a/src/ec/google/chromeec/ec.h
+++ b/src/ec/google/chromeec/ec.h
@@ -562,6 +562,16 @@ int google_chromeec_read_batt_state_of_charge(uint32_t *state);
 int google_chromeec_set_lightbar_rgb(unsigned int led, int red, int green,
 			 int blue);
 
+/*
+ * Sends a command to turn off the Chrome EC lightbar.
+ *
+ * This function packages a LIGHTBAR_CMD_OFF sub-command into a standard
+ * EC_CMD_LIGHTBAR_CMD packet.
+ *
+ * @return 0 on success, non-zero error code from the EC transport on failure.
+ */
+int google_chromeec_lightbar_off(void);
+
 /*
  * Check if the battery is critically low and AC is not present.
  *

From b68ba242440894f12dcddfe23455fe8bac17de33 Mon Sep 17 00:00:00 2001
From: Subrata Banik <subratabanik@google.com>
Date: Mon, 23 Feb 2026 10:35:10 +0530
Subject: [PATCH 3448/3886] ec/google/chromeec: Add API to turn on lightbar

Implement google_chromeec_lightbar_on() to allow the host to
explicitly enable the Chrome EC lightbar. This function sends the
LIGHTBAR_CMD_ON sub-command through the EC_CMD_LIGHTBAR_CMD
host command.

BUG=None
TEST=Verified lightbar can be re-enabled after being turned off on
supported hardware.

Change-Id: I838525ba091281fefb3b6a33b9974037d06706d4
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91381
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
---
 src/ec/google/chromeec/ec.c | 26 ++++++++++++++++++++++++++
 src/ec/google/chromeec/ec.h | 10 ++++++++++
 2 files changed, 36 insertions(+)

diff --git a/src/ec/google/chromeec/ec.c b/src/ec/google/chromeec/ec.c
index 5fe90c8e39..ab4df3dde2 100644
--- a/src/ec/google/chromeec/ec.c
+++ b/src/ec/google/chromeec/ec.c
@@ -2007,6 +2007,32 @@ int google_chromeec_lightbar_off(void)
 	return google_chromeec_command(&cmd);
 }
 
+/*
+ * Sends a command to enable the Chrome EC lightbar.
+ *
+ * This function wraps the LIGHTBAR_CMD_ON sub-command into a standard
+ * EC_CMD_LIGHTBAR_CMD host command.
+ *
+ * @return 0 on success, or a non-zero EC transport error code on failure.
+ */
+int google_chromeec_lightbar_on(void)
+{
+	const struct ec_params_lightbar req = {
+		.cmd = LIGHTBAR_CMD_ON,
+	};
+
+	struct chromeec_command cmd = {
+		.cmd_code = EC_CMD_LIGHTBAR_CMD,
+		.cmd_size_out = 0,
+		.cmd_data_out = NULL,
+		.cmd_size_in = sizeof(req),
+		.cmd_data_in = &req,
+	};
+
+	return google_chromeec_command(&cmd);
+}
+
+
 /*
  * Check if the battery is critically low and not currently charging.
  *
diff --git a/src/ec/google/chromeec/ec.h b/src/ec/google/chromeec/ec.h
index 79aa69bcf8..73ec3eeda8 100644
--- a/src/ec/google/chromeec/ec.h
+++ b/src/ec/google/chromeec/ec.h
@@ -572,6 +572,16 @@ int google_chromeec_set_lightbar_rgb(unsigned int led, int red, int green,
  */
 int google_chromeec_lightbar_off(void);
 
+/*
+ * Sends a command to enable the Chrome EC lightbar.
+ *
+ * This function wraps the LIGHTBAR_CMD_ON sub-command into a standard
+ * EC_CMD_LIGHTBAR_CMD host command.
+ *
+ * @return 0 on success, or a non-zero EC transport error code on failure.
+ */
+int google_chromeec_lightbar_on(void);
+
 /*
  * Check if the battery is critically low and AC is not present.
  *

From d39f406f55dd5f80f30a762fd4401f92390e09bb Mon Sep 17 00:00:00 2001
From: Subrata Banik <subratabanik@google.com>
Date: Mon, 23 Feb 2026 09:01:32 +0530
Subject: [PATCH 3449/3886] mb/google/bluey: Disable lightbar during low-power
 charging boot

Turn off the lightbar when the system boots into Low-Battery with
Charger or Off-Mode Charging states.

This ensures that the external lightbar does not provide conflicting
visual signals while the built-in display is showing the charging
animation. Additionally, this prevents unnecessary power consumption
from the lightbar in these power-restricted modes.

BUG=b:477531197
TEST=Boot bluey in off-mode charging; verify lightbar is disabled.
     Boot bluey normally; verify lightbar functions as expected.

Change-Id: Ice64d700aee82c780f872a3cb18f8a873e9189f5
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91378
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
---
 src/mainboard/google/bluey/mainboard.c | 11 +++++++++--
 1 file changed, 9 insertions(+), 2 deletions(-)

diff --git a/src/mainboard/google/bluey/mainboard.c b/src/mainboard/google/bluey/mainboard.c
index 099f825344..89a2a2a0eb 100644
--- a/src/mainboard/google/bluey/mainboard.c
+++ b/src/mainboard/google/bluey/mainboard.c
@@ -184,9 +184,16 @@ static void mainboard_init(struct device *dev)
 	if (get_boot_mode() == LB_BOOT_MODE_LOW_BATTERY)
 		trigger_critical_battery_shutdown();
 
-	/* Skip mainboard initialization if boot mode is "low-battery" or "off-mode charging"*/
-	if (is_low_power_boot_with_charger())
+	/* Skip mainboard initialization if boot mode is "low-battery" or "off-mode charging" */
+	if (is_low_power_boot_with_charger()) {
+		/* Disable the lightbar for Low-Battery or Off-Mode charging sequences.
+		 * This maintains visual consistency between the built-in display
+		 * indicators and the external lightbar.
+		 */
+		if (CONFIG(EC_GOOGLE_CHROMEEC))
+			google_chromeec_lightbar_off();
 		return;
+	}
 
 	gpi_firmware_load(QUP_0_GSI_BASE);
 	gpi_firmware_load(QUP_1_GSI_BASE);

From 2a821d8db63aee0556024e143f71f5e4e0198680 Mon Sep 17 00:00:00 2001
From: Subrata Banik <subratabanik@google.com>
Date: Tue, 24 Feb 2026 09:35:16 +0530
Subject: [PATCH 3450/3886] mb/google/bluey: Early enablement of lightbar

Initialize and turn on the Chrome EC lightbar during the early romstage
initialization phase. This ensures that the lightbar is active and
ready to provide visual feedback as early as possible in the boot
process.

This covers edge cases where the lightbar was left in an OFF state
by AP firmware and no EC reset occurred to restore defaults.

BUG=b:477531197
TEST=Boot bluey and verify the lightbar turns on during the
early romstage.

Change-Id: I9336acc83d0455c21378ef7cb77939d4d5d54250
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91382
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
---
 src/mainboard/google/bluey/romstage.c | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/src/mainboard/google/bluey/romstage.c b/src/mainboard/google/bluey/romstage.c
index a3806668b7..a415228e8b 100644
--- a/src/mainboard/google/bluey/romstage.c
+++ b/src/mainboard/google/bluey/romstage.c
@@ -126,6 +126,14 @@ static void early_setup_usb(void)
 
 void platform_romstage_main(void)
 {
+	/*
+	 * Early initialization of the Chrome EC lightbar.
+	 * Ensures visual continuity if the AP firmware disabled the lightbar
+	 * in a previous boot without a subsequent EC reset.
+	 */
+	if (CONFIG(EC_GOOGLE_CHROMEEC))
+		google_chromeec_lightbar_on();
+
 	/*
 	 * Only alert the user (set LED to red in color) if the lid is closed and the battery
 	 * is critically low without AC power.

From 086d3a32324ac37be26da5f14108d7facc3ba50f Mon Sep 17 00:00:00 2001
From: Subrata Banik <subratabanik@google.com>
Date: Tue, 24 Feb 2026 09:40:36 +0530
Subject: [PATCH 3451/3886] mb/google/fatcat: Enable ChromeOS EC LEDs in
 romstage

Initialize the ChromeOS EC LEDs during the bootblock phase for the
fatcat mainboard. This ensures the LEDs are powered on early in the boot
process to provide visual feedback to the user.

This covers edge cases where the lightbar was left in an OFF state
by AP firmware and no EC reset occurred to restore defaults.

TEST=Boot moonstome and verify the LEDs turns on during the
bootblock stage.

Change-Id: I24ce78e4a30ea8fce7d7a90e01525c328db7e325
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91392
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
---
 src/mainboard/google/fatcat/romstage.c | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/src/mainboard/google/fatcat/romstage.c b/src/mainboard/google/fatcat/romstage.c
index 9cece34bf6..5098cd3d8b 100644
--- a/src/mainboard/google/fatcat/romstage.c
+++ b/src/mainboard/google/fatcat/romstage.c
@@ -48,6 +48,14 @@ void mainboard_memory_init_params(FSPM_UPD *memupd)
 
 void platform_romstage_pre_mem(void)
 {
+	/*
+	 * Early initialization of the Chrome EC lightbar.
+	 * Ensures visual continuity if the AP firmware disabled the lightbar
+	 * in a previous boot without a subsequent EC reset.
+	 */
+	if (CONFIG(EC_GOOGLE_CHROMEEC))
+		google_chromeec_lightbar_on();
+
 	/*
 	 * Only alert the user (set LED to red in color) if the lid is closed and the battery
 	 * is critically low without AC power.

From 5c44e689ee763608c5db9fe51a8c075483383f9d Mon Sep 17 00:00:00 2001
From: Subrata Banik <subratabanik@google.com>
Date: Tue, 24 Feb 2026 12:35:30 +0530
Subject: [PATCH 3452/3886] vc/google/chromeos: Add platform hook for emergency
 battery shutdown

Introduce platform_handle_emergency_low_battery() to handle the
pre-shutdown sequence when battery levels are critical.

This hook ensures:
1. Visual feedback is provided (Lightbar set to red).
2. The event is logged to ELOG for post-mortem analysis.
3. A delay is enforced to ensure logs are committed and the user
   notices the alert before the AP powers off.

BUG=none
BRANCH=none
TEST=Verified lightbar turns red and ELOG is recorded on low battery
     boot.

Change-Id: I3f1b2757002d7a2a76dfb51d24a04e2d81b061bb
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91409
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
---
 src/include/bootsplash.h                 |  7 +++++++
 src/vendorcode/google/chromeos/battery.c | 24 ++++++++++++++++++++++++
 2 files changed, 31 insertions(+)

diff --git a/src/include/bootsplash.h b/src/include/bootsplash.h
index cd02f7382e..67b3a405a1 100644
--- a/src/include/bootsplash.h
+++ b/src/include/bootsplash.h
@@ -191,8 +191,15 @@ void bmp_release_logo(void);
  */
 #if CONFIG(PLATFORM_HAS_LOW_BATTERY_INDICATOR)
 bool platform_is_low_battery_shutdown_needed(void);
+/*
+ * Platform hooks for system shutdown due to critical battery levels.
+ * Provides visual feedback via the Lightbar/LEDs and logs the event
+ * to non-volatile storage before signaling to cut power.
+ */
+void platform_handle_emergency_low_battery(void);
 #else
 static inline bool platform_is_low_battery_shutdown_needed(void) { return false; }
+static inline void platform_handle_emergency_low_battery(void) { /* nop */ }
 #endif
 
 /*
diff --git a/src/vendorcode/google/chromeos/battery.c b/src/vendorcode/google/chromeos/battery.c
index 438098256b..0e676b3f2a 100644
--- a/src/vendorcode/google/chromeos/battery.c
+++ b/src/vendorcode/google/chromeos/battery.c
@@ -2,6 +2,8 @@
 
 #include <ec/google/chromeec/ec.h>
 #include <bootsplash.h>
+#include <elog.h>
+#include <delay.h>
 
 /*
  * Check if low battery shutdown is needed
@@ -32,3 +34,25 @@ bool platform_is_low_battery_shutdown_needed(void)
 
 	return result;
 }
+
+/*
+ * Platform hooks for system shutdown due to critical battery levels.
+ * Provides visual feedback via the Lightbar/LEDs and logs the event
+ * to non-volatile storage before signaling to cut power.
+ */
+void platform_handle_emergency_low_battery(void)
+{
+	if (!CONFIG(EC_GOOGLE_CHROMEEC))
+		return;
+
+	/* Visual alert: Set Lightbar to solid Red */
+	google_chromeec_set_lightbar_rgb(0xff, 0xff, 0x00, 0x00);
+
+	/* Record the event for post-mortem diagnostics (stored in CMOS/Flash) */
+	elog_add_event_byte(ELOG_TYPE_LOW_BATTERY_INDICATOR, ELOG_FW_ISSUE_SHUTDOWN);
+
+	/* * Pause briefly to ensure the user perceives the LED change and
+	 * the event log is safely committed to storage.
+	 */
+	delay(CONFIG_PLATFORM_POST_RENDER_DELAY_SEC);
+}

From a96f1a464b4863adb8fdaa22604c61f72d198c0a Mon Sep 17 00:00:00 2001
From: Subrata Banik <subratabanik@google.com>
Date: Tue, 24 Feb 2026 12:39:06 +0530
Subject: [PATCH 3453/3886] mb/google/bluey: Use common platform hook for
 emergency shutdown

Refactor trigger_critical_battery_shutdown() to use the newly
implemented platform_handle_emergency_low_battery() hook.

This removes duplicate logic from the Bluey mainboard directory and
ensures consistency with the ChromeOS common battery handling code
for visual alerts and ELOG recording.

BUG=none
BRANCH=none
TEST=Build and boot on Bluey; verify emergency shutdown still
triggers red LEDs and logs ELOG events correctly.

Change-Id: I28da29eb3f0033abe524f7ee12d6b823392e9766
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91410
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
---
 src/mainboard/google/bluey/mainboard.c | 11 ++---------
 1 file changed, 2 insertions(+), 9 deletions(-)

diff --git a/src/mainboard/google/bluey/mainboard.c b/src/mainboard/google/bluey/mainboard.c
index 89a2a2a0eb..2fc8cfdde9 100644
--- a/src/mainboard/google/bluey/mainboard.c
+++ b/src/mainboard/google/bluey/mainboard.c
@@ -2,6 +2,7 @@
 
 #include <boot/coreboot_tables.h>
 #include <bootmode.h>
+#include <bootsplash.h>
 #include <bootstate.h>
 #include <cbmem.h>
 #include <commonlib/bsd/cbmem_id.h>
@@ -11,7 +12,6 @@
 #include <device/device.h>
 #include <device/i2c_simple.h>
 #include <ec/google/chromeec/ec.h>
-#include <elog.h>
 #include <gpio.h>
 #include <soc/clock.h>
 #include <soc/pcie.h>
@@ -159,14 +159,7 @@ static void trigger_critical_battery_shutdown(void)
 	if (!CONFIG(EC_GOOGLE_CHROMEEC))
 		return;
 
-	/* Set LED to Red to alert the user visually */
-	google_chromeec_set_lightbar_rgb(0xff, 0xff, 0x00, 0x00);
-
-	/* Log the event to CMOS/Flash for post-mortem analysis */
-	elog_add_event_byte(ELOG_TYPE_LOW_BATTERY_INDICATOR, ELOG_FW_ISSUE_SHUTDOWN);
-
-	/* Allow time for the log to flush and the user to see the LED change */
-	delay(CONFIG_PLATFORM_POST_RENDER_DELAY_SEC);
+	platform_handle_emergency_low_battery();
 
 	google_chromeec_ap_poweroff();
 }

From b50c219557d0ea99571aaf2f939e1c5c6c99ecfb Mon Sep 17 00:00:00 2001
From: Subrata Banik <subratabanik@google.com>
Date: Tue, 24 Feb 2026 12:42:46 +0530
Subject: [PATCH 3454/3886] soc/intel: Use centralized emergency battery
 shutdown hook

Migrate the low-battery power-off sequence in Intel common reset
logic to use platform_handle_emergency_low_battery().

This ensures that all Intel-based boards benefit from the unified
ChromeOS battery alert flow (LED notification and ELOG recording)
without duplicating the logic in the SOC layer.

BUG=none
BRANCH=none
TEST=Verified that low-battery shutdown on Intel platforms still
correctly logs ELOG and triggers visual alerts via the new hook.

Change-Id: I37c15a1f7dd5acee10389c0521e8c9b2f2d90d42
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91411
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
---
 src/soc/intel/common/reset.c | 8 ++------
 1 file changed, 2 insertions(+), 6 deletions(-)

diff --git a/src/soc/intel/common/reset.c b/src/soc/intel/common/reset.c
index 40cea6bccc..14a32c1697 100644
--- a/src/soc/intel/common/reset.c
+++ b/src/soc/intel/common/reset.c
@@ -1,10 +1,9 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
 #include <arch/cache.h>
+#include <bootsplash.h>
 #include <cf9_reset.h>
 #include <console/console.h>
-#include <delay.h>
-#include <elog.h>
 #include <halt.h>
 #include <reset.h>
 
@@ -26,10 +25,7 @@ void do_board_reset(void)
 
 void do_low_battery_poweroff(void)
 {
-	if (CONFIG(PLATFORM_HAS_LOW_BATTERY_INDICATOR)) {
-		elog_add_event_byte(ELOG_TYPE_LOW_BATTERY_INDICATOR, ELOG_FW_ISSUE_SHUTDOWN);
-		delay(CONFIG_PLATFORM_POST_RENDER_DELAY_SEC);
-	}
+	platform_handle_emergency_low_battery();
 
 	poweroff();
 	halt();

From 34c156427dcac5311eb2e96dd847e624cf200809 Mon Sep 17 00:00:00 2001
From: Patrick Rudolph <patrick.rudolph@9elements.com>
Date: Thu, 12 Feb 2026 07:11:47 +0100
Subject: [PATCH 3455/3886] soc/intel/common/block/lpc: Fix AMASK decoding in
 window detection

Commit 339ef9b5c929 ("soc/intel/common/block/lpc: Improve automatic
window opening") introduced a bug in the decoding of existing LPC I/O
window sizes from the LGIR (LPC Generic I/O Range) registers.

The AMASK field in the LGIR register stores bits [7:2] of the address
mask, with bits [1:0] implicitly always set to 1 (representing 4-byte
granularity). The original implementation incorrectly calculated the
window size as:

  exist_size = 1 + ((reg32 & LPC_LGIR_AMASK_MASK) >> 16)

This fails to restore the implicit lower bits [1:0] of the mask.

For example, a window programmed with size 8 bytes:
- Stored mask: (8-1) & 0xfc = 0x4 (bits [7:2] only)
- Incorrectly decoded: 0x4 + 1 = 5 bytes (WRONG)
- Correctly decoded: (0x4 | 0x3) + 1 = 8 bytes (CORRECT)

This bug caused failures on Panther Lake boards where existing windows
were not recognized as covering requested ranges, leading to:

  [ERROR] LPC: Cannot open IO window: 800 size 8
  [ERROR] No more IO windows

The fix properly reconstructs the full mask by OR-ing in the implicit
bits [1:0] before calculating the size:

  exist_size = ((amask_raw & 0xfc) | 0x3) + 1

BUG=b:486133237
TEST=Boot Panther Lake Fatcat board, verify no LPC window errors

Change-Id: I0b5f95c01da6ce84924a038106edec600e3b97f8
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91418
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Pranava Y N <pranavayn@google.com>
---
 src/soc/intel/common/block/lpc/lpc_lib.c | 12 ++++++++++--
 1 file changed, 10 insertions(+), 2 deletions(-)

diff --git a/src/soc/intel/common/block/lpc/lpc_lib.c b/src/soc/intel/common/block/lpc/lpc_lib.c
index 337a098848..18cf1670af 100644
--- a/src/soc/intel/common/block/lpc/lpc_lib.c
+++ b/src/soc/intel/common/block/lpc/lpc_lib.c
@@ -176,8 +176,16 @@ void lpc_open_pmio_window(uint16_t base, uint16_t size)
 			const u32 reg32 = pci_read_config32(PCH_DEV_LPC, LPC_GENERIC_IO_RANGE(i));
 			if (!(reg32 & LPC_LGIR_EN))
 				continue;
-			const struct region exist = region_create(reg32 & LPC_LGIR_ADDR_MASK,
-							1 + ((reg32 & LPC_LGIR_AMASK_MASK) >> 16));
+
+			/* The AMASK field stores bits [7:2] of the address mask.
+			 * Bits [1:0] are always set (4-byte granularity).
+			 * To decode: mask = (amask_raw & 0xfc) | 0x3
+			 *            size = mask + 1
+			 */
+			const u32 exist_base = reg32 & LPC_LGIR_ADDR_MASK;
+			const u32 amask_raw = (reg32 & LPC_LGIR_AMASK_MASK) >> 16;
+			const u32 exist_size = ((amask_raw & 0xfc) | 0x3) + 1;
+			const struct region exist = region_create(exist_base, exist_size);
 
 			if (region_is_subregion(&exist, &win))
 				return;

From b21e861ab5975fd8e5cbcb45728313be16d67530 Mon Sep 17 00:00:00 2001
From: Jeremy Compostella <jeremy.compostella@intel.com>
Date: Mon, 23 Feb 2026 07:18:19 -0800
Subject: [PATCH 3456/3886] soc/intel/common/feature/i2c: Add common devfn
 mapping

Introduce a common implementation for I2C device function to bus
number mapping that can be shared across multiple Intel SoC platforms.

The implementation uses:
- CONFIG_SOC_INTEL_I2C_DEV_MAX: Kconfig value for max I2C controllers
- SOC_I2C_DEVFN(n): SoC-specific macro for I2C devfn names

This eliminates duplicate code across platforms that follow the
standard I2C controller numbering scheme.

Change-Id: Ib242d7a839ccb26394794382098cecb658adf698
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91258
Reviewed-by: Guvendik, Bora <bora.guvendik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/soc/intel/common/feature/i2c/Kconfig     |  8 ++
 src/soc/intel/common/feature/i2c/Makefile.mk |  4 +
 src/soc/intel/common/feature/i2c/i2c_devfn.c | 79 ++++++++++++++++++++
 3 files changed, 91 insertions(+)
 create mode 100644 src/soc/intel/common/feature/i2c/Kconfig
 create mode 100644 src/soc/intel/common/feature/i2c/Makefile.mk
 create mode 100644 src/soc/intel/common/feature/i2c/i2c_devfn.c

diff --git a/src/soc/intel/common/feature/i2c/Kconfig b/src/soc/intel/common/feature/i2c/Kconfig
new file mode 100644
index 0000000000..5dede903d3
--- /dev/null
+++ b/src/soc/intel/common/feature/i2c/Kconfig
@@ -0,0 +1,8 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
+config SOC_INTEL_COMMON_FEATURE_I2C_DEVFN
+	bool
+	help
+	  Common I2C device function to bus mapping implementation.
+	  SoCs using this must define SOC_I2C_DEVFN(n) macro in their
+	  pci_devs.h and CONFIG_SOC_INTEL_I2C_DEV_MAX in their Kconfig.
diff --git a/src/soc/intel/common/feature/i2c/Makefile.mk b/src/soc/intel/common/feature/i2c/Makefile.mk
new file mode 100644
index 0000000000..2b4a6ab6fb
--- /dev/null
+++ b/src/soc/intel/common/feature/i2c/Makefile.mk
@@ -0,0 +1,4 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
+all-$(CONFIG_SOC_INTEL_COMMON_FEATURE_I2C_DEVFN) += i2c_devfn.c
+smm-$(CONFIG_SOC_INTEL_COMMON_FEATURE_I2C_DEVFN) += i2c_devfn.c
diff --git a/src/soc/intel/common/feature/i2c/i2c_devfn.c b/src/soc/intel/common/feature/i2c/i2c_devfn.c
new file mode 100644
index 0000000000..e8adb2fe4b
--- /dev/null
+++ b/src/soc/intel/common/feature/i2c/i2c_devfn.c
@@ -0,0 +1,79 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <device/device.h>
+#include <drivers/i2c/designware/dw_i2c.h>
+#include <soc/pci_devs.h>
+
+/*
+ * SoC-specific I2C device function to bus number mapping.
+ *
+ * Each SoC must define:
+ * - CONFIG_SOC_INTEL_I2C_DEV_MAX: Maximum number of I2C controllers
+ * - SOC_I2C_DEVFN(n): Macro that expands to the SoC-specific I2C device
+ *   function name (e.g., PCH_DEVFN_I2Cn or PCI_DEVFN_I2Cn)
+ */
+
+_Static_assert(CONFIG_SOC_INTEL_I2C_DEV_MAX <= 8,
+	       "CONFIG_SOC_INTEL_I2C_DEV_MAX greater than 8 is not supported.");
+
+int dw_i2c_soc_devfn_to_bus(unsigned int devfn)
+{
+	switch (devfn) {
+	case SOC_I2C_DEVFN(0):
+		return 0;
+	case SOC_I2C_DEVFN(1):
+		return 1;
+	case SOC_I2C_DEVFN(2):
+		return 2;
+	case SOC_I2C_DEVFN(3):
+		return 3;
+#if CONFIG_SOC_INTEL_I2C_DEV_MAX > 4
+	case SOC_I2C_DEVFN(4):
+		return 4;
+#endif
+#if CONFIG_SOC_INTEL_I2C_DEV_MAX > 5
+	case SOC_I2C_DEVFN(5):
+		return 5;
+#endif
+#if CONFIG_SOC_INTEL_I2C_DEV_MAX > 6
+	case SOC_I2C_DEVFN(6):
+		return 6;
+#endif
+#if CONFIG_SOC_INTEL_I2C_DEV_MAX > 7
+	case SOC_I2C_DEVFN(7):
+		return 7;
+#endif
+	}
+	return -1;
+}
+
+int dw_i2c_soc_bus_to_devfn(unsigned int bus)
+{
+	switch (bus) {
+	case 0:
+		return SOC_I2C_DEVFN(0);
+	case 1:
+		return SOC_I2C_DEVFN(1);
+	case 2:
+		return SOC_I2C_DEVFN(2);
+	case 3:
+		return SOC_I2C_DEVFN(3);
+#if CONFIG_SOC_INTEL_I2C_DEV_MAX > 4
+	case 4:
+		return SOC_I2C_DEVFN(4);
+#endif
+#if CONFIG_SOC_INTEL_I2C_DEV_MAX > 5
+	case 5:
+		return SOC_I2C_DEVFN(5);
+#endif
+#if CONFIG_SOC_INTEL_I2C_DEV_MAX > 6
+	case 6:
+		return SOC_I2C_DEVFN(6);
+#endif
+#if CONFIG_SOC_INTEL_I2C_DEV_MAX > 7
+	case 7:
+		return SOC_I2C_DEVFN(7);
+#endif
+	}
+	return -1;
+}

From 749bae2f94ce1116a95e0ac4342cf30eeebd2cf4 Mon Sep 17 00:00:00 2001
From: Jeremy Compostella <jeremy.compostella@intel.com>
Date: Mon, 23 Feb 2026 07:46:06 -0800
Subject: [PATCH 3457/3886] soc/intel/alderlake: Use common I2C devfn mapping

Replace platform-specific i2c.c with common implementation.

Defines SOC_I2C_DEVFN(n) macro and uses existing
CONFIG_SOC_INTEL_I2C_DEV_MAX Kconfig.

Change-Id: I5d8420231d1252986b8b7274a4c8c2f6d41f759d
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91259
Reviewed-by: Guvendik, Bora <bora.guvendik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/soc/intel/alderlake/Kconfig               |  1 +
 src/soc/intel/alderlake/Makefile.mk           |  1 -
 src/soc/intel/alderlake/i2c.c                 | 57 -------------------
 .../intel/alderlake/include/soc/pci_devs.h    |  3 +
 4 files changed, 4 insertions(+), 58 deletions(-)
 delete mode 100644 src/soc/intel/alderlake/i2c.c

diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig
index 9034f5d252..c78a09076d 100644
--- a/src/soc/intel/alderlake/Kconfig
+++ b/src/soc/intel/alderlake/Kconfig
@@ -85,6 +85,7 @@ config SOC_INTEL_ALDERLAKE
 	select SOC_INTEL_COMMON_BLOCK_XHCI
 	select SOC_INTEL_COMMON_BLOCK_XHCI_ELOG
 	select SOC_INTEL_COMMON_FEATURE
+	select SOC_INTEL_COMMON_FEATURE_I2C_DEVFN
 	select SOC_INTEL_COMMON_FEATURE_UART_DEVICES
 	select SOC_INTEL_COMMON_FSP_RESET
 	select SOC_INTEL_COMMON_PCH_CLIENT
diff --git a/src/soc/intel/alderlake/Makefile.mk b/src/soc/intel/alderlake/Makefile.mk
index eafba3cbd6..2e97718bc2 100644
--- a/src/soc/intel/alderlake/Makefile.mk
+++ b/src/soc/intel/alderlake/Makefile.mk
@@ -6,7 +6,6 @@ subdirs-y += ../../../cpu/intel/turbo
 
 # all (bootblock, verstage, romstage, postcar, ramstage)
 all-y += gspi.c
-all-y += i2c.c
 all-y += pmutil.c
 all-y += spi.c
 
diff --git a/src/soc/intel/alderlake/i2c.c b/src/soc/intel/alderlake/i2c.c
deleted file mode 100644
index 5fcca2a9e7..0000000000
--- a/src/soc/intel/alderlake/i2c.c
+++ /dev/null
@@ -1,57 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-/*
- * This file is created based on Intel Alder Lake Processor PCH Datasheet
- * Document number: 621483
- * Chapter number: 13
- */
-
-#include <device/device.h>
-#include <drivers/i2c/designware/dw_i2c.h>
-#include <soc/pci_devs.h>
-
-int dw_i2c_soc_devfn_to_bus(unsigned int devfn)
-{
-	switch (devfn) {
-	case PCH_DEVFN_I2C0:
-		return 0;
-	case PCH_DEVFN_I2C1:
-		return 1;
-	case PCH_DEVFN_I2C2:
-		return 2;
-	case PCH_DEVFN_I2C3:
-		return 3;
-	case PCH_DEVFN_I2C4:
-		return 4;
-	case PCH_DEVFN_I2C5:
-		return 5;
-	case PCH_DEVFN_I2C6:
-		return 6;
-	case PCH_DEVFN_I2C7:
-		return 7;
-	}
-	return -1;
-}
-
-int dw_i2c_soc_bus_to_devfn(unsigned int bus)
-{
-	switch (bus) {
-	case 0:
-		return PCH_DEVFN_I2C0;
-	case 1:
-		return PCH_DEVFN_I2C1;
-	case 2:
-		return PCH_DEVFN_I2C2;
-	case 3:
-		return PCH_DEVFN_I2C3;
-	case 4:
-		return PCH_DEVFN_I2C4;
-	case 5:
-		return PCH_DEVFN_I2C5;
-	case 6:
-		return PCH_DEVFN_I2C6;
-	case 7:
-		return PCH_DEVFN_I2C7;
-	}
-	return -1;
-}
diff --git a/src/soc/intel/alderlake/include/soc/pci_devs.h b/src/soc/intel/alderlake/include/soc/pci_devs.h
index 9876397219..13cea6d2fc 100644
--- a/src/soc/intel/alderlake/include/soc/pci_devs.h
+++ b/src/soc/intel/alderlake/include/soc/pci_devs.h
@@ -284,3 +284,6 @@
 #define PCI_DEVFN_UART2		PCH_DEVFN_UART2
 
 #endif
+
+/* for common code */
+#define SOC_I2C_DEVFN(n)	PCH_DEVFN_I2C##n

From fe728d62c92bfb79d7b5102d75db2dca713f5989 Mon Sep 17 00:00:00 2001
From: Jeremy Compostella <jeremy.compostella@intel.com>
Date: Mon, 23 Feb 2026 07:46:06 -0800
Subject: [PATCH 3458/3886] soc/intel/elkhartlake: Use common I2C devfn mapping

Replace platform-specific i2c.c with common implementation.

Defines SOC_I2C_DEVFN(n) macro and uses existing
CONFIG_SOC_INTEL_I2C_DEV_MAX Kconfig.

Change-Id: I09aec87fbac0861d3b50d26f475016fdd5aa6fb7
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91260
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Guvendik, Bora <bora.guvendik@intel.com>
---
 src/soc/intel/elkhartlake/Kconfig             |  1 +
 src/soc/intel/elkhartlake/Makefile.mk         |  1 -
 src/soc/intel/elkhartlake/i2c.c               | 51 -------------------
 .../intel/elkhartlake/include/soc/pci_devs.h  |  3 ++
 4 files changed, 4 insertions(+), 52 deletions(-)
 delete mode 100644 src/soc/intel/elkhartlake/i2c.c

diff --git a/src/soc/intel/elkhartlake/Kconfig b/src/soc/intel/elkhartlake/Kconfig
index 79e57e6894..4e5b9bc99c 100644
--- a/src/soc/intel/elkhartlake/Kconfig
+++ b/src/soc/intel/elkhartlake/Kconfig
@@ -56,6 +56,7 @@ config SOC_INTEL_ELKHARTLAKE
 	select SOC_INTEL_COMMON_BLOCK_SMM
 	select SOC_INTEL_COMMON_BLOCK_SMM_IO_TRAP
 	select SOC_INTEL_COMMON_FEATURE
+	select SOC_INTEL_COMMON_FEATURE_I2C_DEVFN
 	select SOC_INTEL_COMMON_FEATURE_UART_DEVICES
 	select SOC_INTEL_COMMON_FSP_RESET
 	select SOC_INTEL_COMMON_PCH_CLIENT
diff --git a/src/soc/intel/elkhartlake/Makefile.mk b/src/soc/intel/elkhartlake/Makefile.mk
index 393a90d17c..b457a2a53b 100644
--- a/src/soc/intel/elkhartlake/Makefile.mk
+++ b/src/soc/intel/elkhartlake/Makefile.mk
@@ -7,7 +7,6 @@ subdirs-y += ../../../cpu/intel/turbo
 
 # all (bootblock, verstage, romstage, postcar, ramstage)
 all-y += gspi.c
-all-y += i2c.c
 all-y += pmutil.c
 all-y += spi.c
 
diff --git a/src/soc/intel/elkhartlake/i2c.c b/src/soc/intel/elkhartlake/i2c.c
deleted file mode 100644
index 78ee37b72d..0000000000
--- a/src/soc/intel/elkhartlake/i2c.c
+++ /dev/null
@@ -1,51 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <device/device.h>
-#include <drivers/i2c/designware/dw_i2c.h>
-#include <soc/pci_devs.h>
-
-int dw_i2c_soc_devfn_to_bus(unsigned int devfn)
-{
-	switch (devfn) {
-	case PCH_DEVFN_I2C0:
-		return 0;
-	case PCH_DEVFN_I2C1:
-		return 1;
-	case PCH_DEVFN_I2C2:
-		return 2;
-	case PCH_DEVFN_I2C3:
-		return 3;
-	case PCH_DEVFN_I2C4:
-		return 4;
-	case PCH_DEVFN_I2C5:
-		return 5;
-	case PCH_DEVFN_I2C6:
-		return 6;
-	case PCH_DEVFN_I2C7:
-		return 7;
-	}
-	return -1;
-}
-
-int dw_i2c_soc_bus_to_devfn(unsigned int bus)
-{
-	switch (bus) {
-	case 0:
-		return PCH_DEVFN_I2C0;
-	case 1:
-		return PCH_DEVFN_I2C1;
-	case 2:
-		return PCH_DEVFN_I2C2;
-	case 3:
-		return PCH_DEVFN_I2C3;
-	case 4:
-		return PCH_DEVFN_I2C4;
-	case 5:
-		return PCH_DEVFN_I2C5;
-	case 6:
-		return PCH_DEVFN_I2C6;
-	case 7:
-		return PCH_DEVFN_I2C7;
-	}
-	return -1;
-}
diff --git a/src/soc/intel/elkhartlake/include/soc/pci_devs.h b/src/soc/intel/elkhartlake/include/soc/pci_devs.h
index 743c3a8cd6..885ebac506 100644
--- a/src/soc/intel/elkhartlake/include/soc/pci_devs.h
+++ b/src/soc/intel/elkhartlake/include/soc/pci_devs.h
@@ -253,3 +253,6 @@
 #define PCI_DEVFN_UART2		PCH_DEVFN_UART2
 
 #endif
+
+/* for common code */
+#define SOC_I2C_DEVFN(n)	PCH_DEVFN_I2C##n

From 83325f354b1cc2e82972ab3f29d24d8a38ee0dff Mon Sep 17 00:00:00 2001
From: Jeremy Compostella <jeremy.compostella@intel.com>
Date: Mon, 23 Feb 2026 07:46:06 -0800
Subject: [PATCH 3459/3886] soc/intel/tigerlake: Use common I2C devfn mapping

Replace platform-specific i2c.c with common implementation.

Defines SOC_I2C_DEVFN(n) macro and uses existing
CONFIG_SOC_INTEL_I2C_DEV_MAX Kconfig.

Change-Id: Id8ac536813cadedc8d49ccb922d583a678436d2e
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91261
Reviewed-by: Guvendik, Bora <bora.guvendik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/soc/intel/tigerlake/Kconfig               |  1 +
 src/soc/intel/tigerlake/Makefile.mk           |  1 -
 src/soc/intel/tigerlake/i2c.c                 | 49 -------------------
 .../intel/tigerlake/include/soc/pci_devs.h    |  3 ++
 4 files changed, 4 insertions(+), 50 deletions(-)
 delete mode 100644 src/soc/intel/tigerlake/i2c.c

diff --git a/src/soc/intel/tigerlake/Kconfig b/src/soc/intel/tigerlake/Kconfig
index 1d6c21e06f..48cf447bd1 100644
--- a/src/soc/intel/tigerlake/Kconfig
+++ b/src/soc/intel/tigerlake/Kconfig
@@ -73,6 +73,7 @@ config SOC_INTEL_TIGERLAKE
 	select SOC_INTEL_COMMON_BLOCK_USB4_XHCI
 	select SOC_INTEL_COMMON_BLOCK_XHCI_ELOG
 	select SOC_INTEL_COMMON_FEATURE
+	select SOC_INTEL_COMMON_FEATURE_I2C_DEVFN
 	select SOC_INTEL_COMMON_FEATURE_UART_DEVICES
 	select SOC_INTEL_COMMON_FSP_RESET
 	select SOC_INTEL_COMMON_PCH_CLIENT
diff --git a/src/soc/intel/tigerlake/Makefile.mk b/src/soc/intel/tigerlake/Makefile.mk
index 19b504362f..53a5d9580f 100644
--- a/src/soc/intel/tigerlake/Makefile.mk
+++ b/src/soc/intel/tigerlake/Makefile.mk
@@ -7,7 +7,6 @@ subdirs-y += ../../../cpu/intel/turbo
 
 # all (bootblock, verstage, romstage, postcar, ramstage)
 all-y += gspi.c
-all-y += i2c.c
 all-y += pmutil.c
 all-y += spi.c
 
diff --git a/src/soc/intel/tigerlake/i2c.c b/src/soc/intel/tigerlake/i2c.c
deleted file mode 100644
index 5b4e0cb214..0000000000
--- a/src/soc/intel/tigerlake/i2c.c
+++ /dev/null
@@ -1,49 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-/*
- * This file is created based on Intel Tiger Lake Processor PCH Datasheet
- * Document number: 575857
- * Chapter number: 13
- */
-
-#include <device/device.h>
-#include <drivers/i2c/designware/dw_i2c.h>
-#include <soc/pci_devs.h>
-
-int dw_i2c_soc_devfn_to_bus(unsigned int devfn)
-{
-	switch (devfn) {
-	case PCH_DEVFN_I2C0:
-		return 0;
-	case PCH_DEVFN_I2C1:
-		return 1;
-	case PCH_DEVFN_I2C2:
-		return 2;
-	case PCH_DEVFN_I2C3:
-		return 3;
-	case PCH_DEVFN_I2C4:
-		return 4;
-	case PCH_DEVFN_I2C5:
-		return 5;
-	}
-	return -1;
-}
-
-int dw_i2c_soc_bus_to_devfn(unsigned int bus)
-{
-	switch (bus) {
-	case 0:
-		return PCH_DEVFN_I2C0;
-	case 1:
-		return PCH_DEVFN_I2C1;
-	case 2:
-		return PCH_DEVFN_I2C2;
-	case 3:
-		return PCH_DEVFN_I2C3;
-	case 4:
-		return PCH_DEVFN_I2C4;
-	case 5:
-		return PCH_DEVFN_I2C5;
-	}
-	return -1;
-}
diff --git a/src/soc/intel/tigerlake/include/soc/pci_devs.h b/src/soc/intel/tigerlake/include/soc/pci_devs.h
index c615f3bc70..29216f5670 100644
--- a/src/soc/intel/tigerlake/include/soc/pci_devs.h
+++ b/src/soc/intel/tigerlake/include/soc/pci_devs.h
@@ -251,3 +251,6 @@
 #define PCI_DEVFN_UART2		PCH_DEVFN_UART2
 
 #endif
+
+/* for common code */
+#define SOC_I2C_DEVFN(n)	PCH_DEVFN_I2C##n

From a0ba812a096d1683297b0e7622514d1a7d22b774 Mon Sep 17 00:00:00 2001
From: Jeremy Compostella <jeremy.compostella@intel.com>
Date: Mon, 23 Feb 2026 07:46:06 -0800
Subject: [PATCH 3460/3886] soc/intel/jasperlake: Use common I2C devfn mapping

Replace platform-specific i2c.c with common implementation.

Defines SOC_I2C_DEVFN(n) macro and uses existing
CONFIG_SOC_INTEL_I2C_DEV_MAX Kconfig.

Change-Id: Ia98748818fde9d1048355d4a144211a327c453ba
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91262
Reviewed-by: Guvendik, Bora <bora.guvendik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/soc/intel/jasperlake/Kconfig              |  1 +
 src/soc/intel/jasperlake/Makefile.mk          |  1 -
 src/soc/intel/jasperlake/i2c.c                | 43 -------------------
 .../intel/jasperlake/include/soc/pci_devs.h   |  3 ++
 4 files changed, 4 insertions(+), 44 deletions(-)
 delete mode 100644 src/soc/intel/jasperlake/i2c.c

diff --git a/src/soc/intel/jasperlake/Kconfig b/src/soc/intel/jasperlake/Kconfig
index 6de9931de3..b1257a76a0 100644
--- a/src/soc/intel/jasperlake/Kconfig
+++ b/src/soc/intel/jasperlake/Kconfig
@@ -56,6 +56,7 @@ config SOC_INTEL_JASPERLAKE
 	select SOC_INTEL_COMMON_BLOCK_SMM_IO_TRAP
 	select SOC_INTEL_COMMON_BLOCK_XHCI_ELOG
 	select SOC_INTEL_COMMON_FEATURE
+	select SOC_INTEL_COMMON_FEATURE_I2C_DEVFN
 	select SOC_INTEL_COMMON_FEATURE_UART_DEVICES
 	select SOC_INTEL_COMMON_FSP_RESET
 	select SOC_INTEL_COMMON_PCH_CLIENT
diff --git a/src/soc/intel/jasperlake/Makefile.mk b/src/soc/intel/jasperlake/Makefile.mk
index 6346f2d3d2..875cc76a9c 100644
--- a/src/soc/intel/jasperlake/Makefile.mk
+++ b/src/soc/intel/jasperlake/Makefile.mk
@@ -7,7 +7,6 @@ subdirs-y += ../../../cpu/intel/turbo
 
 # all (bootblock, verstage, romstage, postcar, ramstage)
 all-y += gspi.c
-all-y += i2c.c
 all-y += pmutil.c
 all-y += spi.c
 
diff --git a/src/soc/intel/jasperlake/i2c.c b/src/soc/intel/jasperlake/i2c.c
deleted file mode 100644
index c13a1a6099..0000000000
--- a/src/soc/intel/jasperlake/i2c.c
+++ /dev/null
@@ -1,43 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <device/device.h>
-#include <drivers/i2c/designware/dw_i2c.h>
-#include <soc/pci_devs.h>
-
-int dw_i2c_soc_devfn_to_bus(unsigned int devfn)
-{
-	switch (devfn) {
-	case PCH_DEVFN_I2C0:
-		return 0;
-	case PCH_DEVFN_I2C1:
-		return 1;
-	case PCH_DEVFN_I2C2:
-		return 2;
-	case PCH_DEVFN_I2C3:
-		return 3;
-	case PCH_DEVFN_I2C4:
-		return 4;
-	case PCH_DEVFN_I2C5:
-		return 5;
-	}
-	return -1;
-}
-
-int dw_i2c_soc_bus_to_devfn(unsigned int bus)
-{
-	switch (bus) {
-	case 0:
-		return PCH_DEVFN_I2C0;
-	case 1:
-		return PCH_DEVFN_I2C1;
-	case 2:
-		return PCH_DEVFN_I2C2;
-	case 3:
-		return PCH_DEVFN_I2C3;
-	case 4:
-		return PCH_DEVFN_I2C4;
-	case 5:
-		return PCH_DEVFN_I2C5;
-	}
-	return -1;
-}
diff --git a/src/soc/intel/jasperlake/include/soc/pci_devs.h b/src/soc/intel/jasperlake/include/soc/pci_devs.h
index 2d2b96a09e..5e9107003e 100644
--- a/src/soc/intel/jasperlake/include/soc/pci_devs.h
+++ b/src/soc/intel/jasperlake/include/soc/pci_devs.h
@@ -199,3 +199,6 @@
 #define PCI_DEVFN_UART2		PCH_DEVFN_UART2
 
 #endif
+
+/* for common code */
+#define SOC_I2C_DEVFN(n)	PCH_DEVFN_I2C##n

From 7f922438be7d5a1e592550095ad195375820d0e3 Mon Sep 17 00:00:00 2001
From: Jeremy Compostella <jeremy.compostella@intel.com>
Date: Mon, 23 Feb 2026 07:46:06 -0800
Subject: [PATCH 3461/3886] soc/intel/cannonlake: Use common I2C devfn mapping

Replace platform-specific i2c.c with common implementation.

Defines SOC_I2C_DEVFN(n) macro and uses existing
CONFIG_SOC_INTEL_I2C_DEV_MAX Kconfig.

Change-Id: I0117a418d35cea3e7c0442c8c3ea27d17b8bdf06
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91263
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Guvendik, Bora <bora.guvendik@intel.com>
---
 src/soc/intel/cannonlake/Kconfig              |  1 +
 src/soc/intel/cannonlake/Makefile.mk          |  5 ---
 src/soc/intel/cannonlake/i2c.c                | 43 -------------------
 .../intel/cannonlake/include/soc/pci_devs.h   |  3 ++
 4 files changed, 4 insertions(+), 48 deletions(-)
 delete mode 100644 src/soc/intel/cannonlake/i2c.c

diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig
index d7075d0d0d..be788ae527 100644
--- a/src/soc/intel/cannonlake/Kconfig
+++ b/src/soc/intel/cannonlake/Kconfig
@@ -60,6 +60,7 @@ config SOC_INTEL_CANNONLAKE_BASE
 	select SOC_INTEL_COMMON_BLOCK_XHCI
 	select SOC_INTEL_COMMON_BLOCK_XHCI_ELOG
 	select SOC_INTEL_COMMON_FEATURE
+	select SOC_INTEL_COMMON_FEATURE_I2C_DEVFN
 	select SOC_INTEL_COMMON_FEATURE_UART_DEVICES
 	select SOC_INTEL_COMMON_FSP_RESET
 	select SOC_INTEL_COMMON_NHLT
diff --git a/src/soc/intel/cannonlake/Makefile.mk b/src/soc/intel/cannonlake/Makefile.mk
index fc51fa0067..2f0c7c1a40 100644
--- a/src/soc/intel/cannonlake/Makefile.mk
+++ b/src/soc/intel/cannonlake/Makefile.mk
@@ -11,14 +11,12 @@ bootblock-y += bootblock/pch.c
 bootblock-y += pmutil.c
 bootblock-y += bootblock/report_platform.c
 bootblock-y += gspi.c
-bootblock-y += i2c.c
 bootblock-y += spi.c
 bootblock-y += lpc.c
 bootblock-y += p2sb.c
 
 romstage-y += cnl_memcfg_init.c
 romstage-y += gspi.c
-romstage-y += i2c.c
 romstage-y += lpc.c
 romstage-y += pcie_rp.c
 romstage-y += pmutil.c
@@ -33,7 +31,6 @@ ramstage-y += finalize.c
 ramstage-y += fsp_params.c
 ramstage-y += graphics.c
 ramstage-y += gspi.c
-ramstage-y += i2c.c
 ramstage-y += lockdown.c
 ramstage-y += lpc.c
 ramstage-y += nhlt.c
@@ -55,12 +52,10 @@ smm-y += smihandler.c
 smm-y += xhci.c
 
 postcar-y += pmutil.c
-postcar-y += i2c.c
 postcar-y += gspi.c
 postcar-y += spi.c
 
 verstage-y += gspi.c
-verstage-y += i2c.c
 verstage-y += pmutil.c
 verstage-y += spi.c
 
diff --git a/src/soc/intel/cannonlake/i2c.c b/src/soc/intel/cannonlake/i2c.c
deleted file mode 100644
index c13a1a6099..0000000000
--- a/src/soc/intel/cannonlake/i2c.c
+++ /dev/null
@@ -1,43 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <device/device.h>
-#include <drivers/i2c/designware/dw_i2c.h>
-#include <soc/pci_devs.h>
-
-int dw_i2c_soc_devfn_to_bus(unsigned int devfn)
-{
-	switch (devfn) {
-	case PCH_DEVFN_I2C0:
-		return 0;
-	case PCH_DEVFN_I2C1:
-		return 1;
-	case PCH_DEVFN_I2C2:
-		return 2;
-	case PCH_DEVFN_I2C3:
-		return 3;
-	case PCH_DEVFN_I2C4:
-		return 4;
-	case PCH_DEVFN_I2C5:
-		return 5;
-	}
-	return -1;
-}
-
-int dw_i2c_soc_bus_to_devfn(unsigned int bus)
-{
-	switch (bus) {
-	case 0:
-		return PCH_DEVFN_I2C0;
-	case 1:
-		return PCH_DEVFN_I2C1;
-	case 2:
-		return PCH_DEVFN_I2C2;
-	case 3:
-		return PCH_DEVFN_I2C3;
-	case 4:
-		return PCH_DEVFN_I2C4;
-	case 5:
-		return PCH_DEVFN_I2C5;
-	}
-	return -1;
-}
diff --git a/src/soc/intel/cannonlake/include/soc/pci_devs.h b/src/soc/intel/cannonlake/include/soc/pci_devs.h
index d5aa36b554..607733c98e 100644
--- a/src/soc/intel/cannonlake/include/soc/pci_devs.h
+++ b/src/soc/intel/cannonlake/include/soc/pci_devs.h
@@ -210,3 +210,6 @@
 #define PCI_DEVFN_UART2		PCH_DEVFN_UART2
 
 #endif
+
+/* for common code */
+#define SOC_I2C_DEVFN(n)	PCH_DEVFN_I2C##n

From f703f2800cd0038e39104a6e4c04c6c0244def95 Mon Sep 17 00:00:00 2001
From: Jeremy Compostella <jeremy.compostella@intel.com>
Date: Mon, 23 Feb 2026 07:46:07 -0800
Subject: [PATCH 3462/3886] soc/intel/skylake: Use common I2C devfn mapping

Replace platform-specific i2c.c with common implementation.

Defines SOC_I2C_DEVFN(n) macro and uses existing
CONFIG_SOC_INTEL_I2C_DEV_MAX Kconfig.

Change-Id: I9ae46e252c599e4ee82a60c03a8d83f874a8da98
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91264
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Guvendik, Bora <bora.guvendik@intel.com>
---
 src/soc/intel/skylake/Kconfig                |  1 +
 src/soc/intel/skylake/Makefile.mk            |  5 ---
 src/soc/intel/skylake/i2c.c                  | 44 --------------------
 src/soc/intel/skylake/include/soc/pci_devs.h |  3 ++
 4 files changed, 4 insertions(+), 49 deletions(-)
 delete mode 100644 src/soc/intel/skylake/i2c.c

diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig
index aa64511249..d3bdd4c8c3 100644
--- a/src/soc/intel/skylake/Kconfig
+++ b/src/soc/intel/skylake/Kconfig
@@ -59,6 +59,7 @@ config SOC_INTEL_COMMON_SKYLAKE_BASE
 	select SOC_INTEL_COMMON_BLOCK_UART
 	select SOC_INTEL_COMMON_BLOCK_XHCI_ELOG
 	select SOC_INTEL_COMMON_FEATURE
+	select SOC_INTEL_COMMON_FEATURE_I2C_DEVFN
 	select SOC_INTEL_COMMON_FEATURE_UART_DEVICES
 	select SOC_INTEL_COMMON_FSP_RESET
 	select SOC_INTEL_COMMON_PCH_CLIENT
diff --git a/src/soc/intel/skylake/Makefile.mk b/src/soc/intel/skylake/Makefile.mk
index de251f2de3..c8513eaf73 100644
--- a/src/soc/intel/skylake/Makefile.mk
+++ b/src/soc/intel/skylake/Makefile.mk
@@ -8,7 +8,6 @@ subdirs-y += ../../../cpu/intel/microcode
 subdirs-y += ../../../cpu/intel/turbo
 
 bootblock-y += bootblock/bootblock.c
-bootblock-y += i2c.c
 bootblock-y += bootblock/pch.c
 bootblock-y += bootblock/report_platform.c
 bootblock-y += gpio.c
@@ -21,12 +20,10 @@ bootblock-y += lpc.c
 verstage-y += gpio.c
 verstage-y += gspi.c
 verstage-y += pmutil.c
-verstage-y += i2c.c
 verstage-y += spi.c
 
 romstage-y += gpio.c
 romstage-y += gspi.c
-romstage-y += i2c.c
 romstage-y += me.c
 romstage-y += pcie_rp.c
 romstage-y += pmutil.c
@@ -41,7 +38,6 @@ ramstage-y += fadt.c
 ramstage-y += finalize.c
 ramstage-y += gpio.c
 ramstage-y += gspi.c
-ramstage-y += i2c.c
 ramstage-y += graphics.c
 ramstage-y += irq.c
 ramstage-y += lockdown.c
@@ -67,7 +63,6 @@ smm-y += xhci.c
 
 postcar-y += gspi.c
 postcar-y += spi.c
-postcar-y += i2c.c
 
 ifeq ($(CONFIG_SKYLAKE_SOC_PCH_H),y)
 ifeq ($(CONFIG_MAINBOARD_SUPPORTS_SKYLAKE_CPU),y)
diff --git a/src/soc/intel/skylake/i2c.c b/src/soc/intel/skylake/i2c.c
deleted file mode 100644
index 521fcb0dd7..0000000000
--- a/src/soc/intel/skylake/i2c.c
+++ /dev/null
@@ -1,44 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <device/device.h>
-#include <intelblocks/cfg.h>
-#include <drivers/i2c/designware/dw_i2c.h>
-#include <soc/pci_devs.h>
-
-int dw_i2c_soc_devfn_to_bus(unsigned int devfn)
-{
-	switch (devfn) {
-	case PCH_DEVFN_I2C0:
-		return 0;
-	case PCH_DEVFN_I2C1:
-		return 1;
-	case PCH_DEVFN_I2C2:
-		return 2;
-	case PCH_DEVFN_I2C3:
-		return 3;
-	case PCH_DEVFN_I2C4:
-		return 4;
-	case PCH_DEVFN_I2C5:
-		return 5;
-	}
-	return -1;
-}
-
-int dw_i2c_soc_bus_to_devfn(unsigned int bus)
-{
-	switch (bus) {
-	case 0:
-		return PCH_DEVFN_I2C0;
-	case 1:
-		return PCH_DEVFN_I2C1;
-	case 2:
-		return PCH_DEVFN_I2C2;
-	case 3:
-		return PCH_DEVFN_I2C3;
-	case 4:
-		return PCH_DEVFN_I2C4;
-	case 5:
-		return PCH_DEVFN_I2C5;
-	}
-	return -1;
-}
diff --git a/src/soc/intel/skylake/include/soc/pci_devs.h b/src/soc/intel/skylake/include/soc/pci_devs.h
index b1e5208523..2f6f649542 100644
--- a/src/soc/intel/skylake/include/soc/pci_devs.h
+++ b/src/soc/intel/skylake/include/soc/pci_devs.h
@@ -193,3 +193,6 @@
 #define PCI_DEVFN_UART2		PCH_DEVFN_UART2
 
 #endif
+
+/* for common code */
+#define SOC_I2C_DEVFN(n)	PCH_DEVFN_I2C##n

From 78e36f8c78f9b1188d7f5bc734b254ad62caecc9 Mon Sep 17 00:00:00 2001
From: Jeremy Compostella <jeremy.compostella@intel.com>
Date: Mon, 23 Feb 2026 07:46:07 -0800
Subject: [PATCH 3463/3886] soc/intel/meteorlake: Use common I2C devfn mapping

Replace platform-specific i2c.c with common implementation.

Defines SOC_I2C_DEVFN(n) macro and uses existing
CONFIG_SOC_INTEL_I2C_DEV_MAX Kconfig.

Change-Id: Ifab488ada515656a5108aee5a6f481abda6a9c0d
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91265
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Guvendik, Bora <bora.guvendik@intel.com>
---
 src/soc/intel/meteorlake/Kconfig              |  1 +
 src/soc/intel/meteorlake/Makefile.mk          |  1 -
 src/soc/intel/meteorlake/i2c.c                | 43 -------------------
 .../intel/meteorlake/include/soc/pci_devs.h   |  1 +
 4 files changed, 2 insertions(+), 44 deletions(-)
 delete mode 100644 src/soc/intel/meteorlake/i2c.c

diff --git a/src/soc/intel/meteorlake/Kconfig b/src/soc/intel/meteorlake/Kconfig
index b223fa01d2..7d7d2df513 100644
--- a/src/soc/intel/meteorlake/Kconfig
+++ b/src/soc/intel/meteorlake/Kconfig
@@ -87,6 +87,7 @@ config SOC_INTEL_METEORLAKE
 	select SOC_INTEL_COMMON_BLOCK_XHCI
 	select SOC_INTEL_COMMON_BLOCK_XHCI_ELOG
 	select SOC_INTEL_COMMON_FEATURE
+	select SOC_INTEL_COMMON_FEATURE_I2C_DEVFN
 	select SOC_INTEL_COMMON_FEATURE_UART_DEVICES
 	select SOC_INTEL_COMMON_BASECODE
 	select SOC_INTEL_COMMON_BASECODE_RAMTOP
diff --git a/src/soc/intel/meteorlake/Makefile.mk b/src/soc/intel/meteorlake/Makefile.mk
index 81be9ff856..1e9a1fc93d 100644
--- a/src/soc/intel/meteorlake/Makefile.mk
+++ b/src/soc/intel/meteorlake/Makefile.mk
@@ -7,7 +7,6 @@ subdirs-y += ../../../cpu/intel/turbo
 
 # all (bootblock, verstage, romstage, postcar, ramstage)
 all-y += gspi.c
-all-y += i2c.c
 all-y += pmutil.c
 all-y += spi.c
 all-y += gpio.c
diff --git a/src/soc/intel/meteorlake/i2c.c b/src/soc/intel/meteorlake/i2c.c
deleted file mode 100644
index 50ab4a73eb..0000000000
--- a/src/soc/intel/meteorlake/i2c.c
+++ /dev/null
@@ -1,43 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <device/device.h>
-#include <drivers/i2c/designware/dw_i2c.h>
-#include <soc/pci_devs.h>
-
-int dw_i2c_soc_devfn_to_bus(unsigned int devfn)
-{
-	switch (devfn) {
-	case PCI_DEVFN_I2C0:
-		return 0;
-	case PCI_DEVFN_I2C1:
-		return 1;
-	case PCI_DEVFN_I2C2:
-		return 2;
-	case PCI_DEVFN_I2C3:
-		return 3;
-	case PCI_DEVFN_I2C4:
-		return 4;
-	case PCI_DEVFN_I2C5:
-		return 5;
-	}
-	return -1;
-}
-
-int dw_i2c_soc_bus_to_devfn(unsigned int bus)
-{
-	switch (bus) {
-	case 0:
-		return PCI_DEVFN_I2C0;
-	case 1:
-		return PCI_DEVFN_I2C1;
-	case 2:
-		return PCI_DEVFN_I2C2;
-	case 3:
-		return PCI_DEVFN_I2C3;
-	case 4:
-		return PCI_DEVFN_I2C4;
-	case 5:
-		return PCI_DEVFN_I2C5;
-	}
-	return -1;
-}
diff --git a/src/soc/intel/meteorlake/include/soc/pci_devs.h b/src/soc/intel/meteorlake/include/soc/pci_devs.h
index 0e55da24bb..034f5e6b6c 100644
--- a/src/soc/intel/meteorlake/include/soc/pci_devs.h
+++ b/src/soc/intel/meteorlake/include/soc/pci_devs.h
@@ -241,5 +241,6 @@
 #define SA_DEVFN_TCSS_DMA1	PCI_DEVFN_TCSS_DMA1
 #define SA_DEV_IGD		PCI_DEV_IGD
 #define SA_DEVFN_IGD		PCI_DEVFN_IGD
+#define SOC_I2C_DEVFN(n)	PCI_DEVFN_I2C##n
 
 #endif // _SOC_METEORLAKE_PCI_DEVS_H_

From d5161611a4b36acd3e82c4bc764c7539616446a2 Mon Sep 17 00:00:00 2001
From: Jeremy Compostella <jeremy.compostella@intel.com>
Date: Mon, 23 Feb 2026 07:46:07 -0800
Subject: [PATCH 3464/3886] soc/intel/pantherlake: Use common I2C devfn mapping

Replace platform-specific i2c.c with common implementation.

Defines SOC_I2C_DEVFN(n) macro and uses existing
CONFIG_SOC_INTEL_I2C_DEV_MAX Kconfig.

Change-Id: I9200c41bf459dfef29599cc1c736e14e8cbd36b9
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91266
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Guvendik, Bora <bora.guvendik@intel.com>
---
 src/soc/intel/pantherlake/Kconfig             |  1 +
 src/soc/intel/pantherlake/Makefile.mk         |  1 -
 src/soc/intel/pantherlake/i2c.c               | 43 -------------------
 .../intel/pantherlake/include/soc/pci_devs.h  |  1 +
 4 files changed, 2 insertions(+), 44 deletions(-)
 delete mode 100644 src/soc/intel/pantherlake/i2c.c

diff --git a/src/soc/intel/pantherlake/Kconfig b/src/soc/intel/pantherlake/Kconfig
index a67b2410ad..2e1bc2ef10 100644
--- a/src/soc/intel/pantherlake/Kconfig
+++ b/src/soc/intel/pantherlake/Kconfig
@@ -97,6 +97,7 @@ config SOC_INTEL_PANTHERLAKE_BASE
 	select SOC_INTEL_COMMON_BLOCK_XHCI
 	select SOC_INTEL_COMMON_BLOCK_XHCI_ELOG
 	select SOC_INTEL_COMMON_FEATURE
+	select SOC_INTEL_COMMON_FEATURE_I2C_DEVFN
 	select SOC_INTEL_COMMON_FEATURE_UART_DEVICES
 	select SOC_INTEL_COMMON_FSP_RESET
 	select SOC_INTEL_COMMON_PCH_CLIENT
diff --git a/src/soc/intel/pantherlake/Makefile.mk b/src/soc/intel/pantherlake/Makefile.mk
index fd9760a965..dadba99ccd 100644
--- a/src/soc/intel/pantherlake/Makefile.mk
+++ b/src/soc/intel/pantherlake/Makefile.mk
@@ -8,7 +8,6 @@ subdirs-y += ../../../cpu/intel/turbo
 
 # all (bootblock, verstage, romstage, postcar, ramstage)
 all-y += gspi.c
-all-y += i2c.c
 all-y += pmutil.c
 all-y += spi.c
 all-y += gpio.c
diff --git a/src/soc/intel/pantherlake/i2c.c b/src/soc/intel/pantherlake/i2c.c
deleted file mode 100644
index 50ab4a73eb..0000000000
--- a/src/soc/intel/pantherlake/i2c.c
+++ /dev/null
@@ -1,43 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <device/device.h>
-#include <drivers/i2c/designware/dw_i2c.h>
-#include <soc/pci_devs.h>
-
-int dw_i2c_soc_devfn_to_bus(unsigned int devfn)
-{
-	switch (devfn) {
-	case PCI_DEVFN_I2C0:
-		return 0;
-	case PCI_DEVFN_I2C1:
-		return 1;
-	case PCI_DEVFN_I2C2:
-		return 2;
-	case PCI_DEVFN_I2C3:
-		return 3;
-	case PCI_DEVFN_I2C4:
-		return 4;
-	case PCI_DEVFN_I2C5:
-		return 5;
-	}
-	return -1;
-}
-
-int dw_i2c_soc_bus_to_devfn(unsigned int bus)
-{
-	switch (bus) {
-	case 0:
-		return PCI_DEVFN_I2C0;
-	case 1:
-		return PCI_DEVFN_I2C1;
-	case 2:
-		return PCI_DEVFN_I2C2;
-	case 3:
-		return PCI_DEVFN_I2C3;
-	case 4:
-		return PCI_DEVFN_I2C4;
-	case 5:
-		return PCI_DEVFN_I2C5;
-	}
-	return -1;
-}
diff --git a/src/soc/intel/pantherlake/include/soc/pci_devs.h b/src/soc/intel/pantherlake/include/soc/pci_devs.h
index 25468ab39a..a1ef4f4c32 100644
--- a/src/soc/intel/pantherlake/include/soc/pci_devs.h
+++ b/src/soc/intel/pantherlake/include/soc/pci_devs.h
@@ -256,5 +256,6 @@
 #define SA_DEVFN_TCSS_DMA1	PCI_DEVFN_TCSS_DMA1
 #define SA_DEV_IGD		PCI_DEV_IGD
 #define SA_DEVFN_IGD		PCI_DEVFN_IGD
+#define SOC_I2C_DEVFN(n)	PCI_DEVFN_I2C##n
 
 #endif // _SOC_PANTHERLAKE_PCI_DEVS_H_

From a59ddda11ed165c2420a1233b6b1eb98aff8be13 Mon Sep 17 00:00:00 2001
From: Purdea Andrei <andrei@purdea.ro>
Date: Sun, 14 Sep 2025 17:17:32 +0300
Subject: [PATCH 3465/3886] Doc/mb/protectli/fw6: describe revisions and more
 variants

- Add documentation about Old/New motherboard revisions
- Mention that FW6A/B/C exist as both Old and New Revision
- Mention that the current codebase only supports the Old Revision
- Add documentation about FW6D and FW6E variants, currently unsupported

Signed-off-by: Purdea Andrei <andrei@purdea.ro>
Change-Id: Ifdf1624c8d206326c64163382b31c6001300b4df
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88226
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
---
 Documentation/mainboard/protectli/fw6.md | 82 +++++++++++++++++++++---
 1 file changed, 73 insertions(+), 9 deletions(-)

diff --git a/Documentation/mainboard/protectli/fw6.md b/Documentation/mainboard/protectli/fw6.md
index df61ee364b..2f55d8566e 100644
--- a/Documentation/mainboard/protectli/fw6.md
+++ b/Documentation/mainboard/protectli/fw6.md
@@ -57,8 +57,13 @@ This chip is located on the bottom side of the case (the radiator side). One
 has to remove all screws (in order): 4 top cover screws, 4 side cover screws
 (one side is enough), 4 mainboard screws, 4 CPU screws (under DIMMs). Lift up
 the mainboard and turn around it. The flash chip is near the SoC on the DIMM
-slots side. Use a clip (or solder the wires) to program the chip. Specifically,
-it's a Macronix MX25L6406E (3.3V) -[datasheet][MX25L6406E].
+slots side. Desolder and reprogram the chip, or use a clip (or solder the
+wires) to program the chip. Specifically, it's a Macronix MX25L6406E (3.3V)
+-[datasheet][MX25L6406E], while on some other boards it's a Macronix MX25L6436F.
+
+At least on some revisions of the motherboard, it's not possible to reprogram
+the chip with a clip, while the board is powered off, because there's no diode
+to prevent backfeeding power to other components on the board.
 
 ## Known issues
 
@@ -99,8 +104,26 @@ the cables or not being populated on the board case.
 
 ## Technology
 
-There are 3 variants of FW6 boards: FW6A, FW6B and FW6C. They differ only in
-used SoC.
+There are 5 variants of FW6 boards: FW6A, FW6B, FW6C, FW6D and FW6E. They differ
+in used SoC.
+
+There are two revisions of the motherboard, hereby called Old Revision
+(using IT8772E Super I/O chip), and New Revision (using IT8613E Super I/O chip).
+Besides the different Super I/O chip, they also differ in component placement,
+and available internal motherboard headers. The Old Revision motherboards are
+marked with silkscreen "YL-SK1L6-V1", while the New Revision motherboards are
+marked with silkscreen "KBR6LAV20".
+
+WARNING: The current code base only supports the Old Revision motherboards.
+
+To compare the two motherboard
+revisions one may compare the [New Revision FW6A Datasheet] to the
+[Old Revision FW6 Series Hardware Overview].
+
+The FW6A/FW6B/FW6C variants are known to have been produced with both
+motherboard revisions.
+
+The FW6D/FW6E variants are only known to exist with the new motherboard revision.
 
 - FW6A:
 
@@ -110,10 +133,12 @@ used SoC.
 +------------------+--------------------------------------------------+
 | PCH              | Kaby Lake U w/ iHDCP2.2 Base                     |
 +------------------+--------------------------------------------------+
-| Super I/O, EC    | ITE IT8772E                                      |
+| Super I/O, EC    | Old revision: ITE IT8772E, New rev.: ITE IT8613E |
 +------------------+--------------------------------------------------+
 | Coprocessor      | Intel Management Engine                          |
 +------------------+--------------------------------------------------+
+| Support          | Currently only the Old Revision is supported     |
++------------------+--------------------------------------------------+
 ```
 
 - FW6B:
@@ -124,10 +149,12 @@ used SoC.
 +------------------+--------------------------------------------------+
 | PCH              | Kaby Lake U w/ iHDCP2.2 Premium                  |
 +------------------+--------------------------------------------------+
-| Super I/O, EC    | ITE IT8772E                                      |
+| Super I/O, EC    | Old revision: ITE IT8772E, New rev.: ITE IT8613E |
 +------------------+--------------------------------------------------+
 | Coprocessor      | Intel Management Engine                          |
 +------------------+--------------------------------------------------+
+| Support          | Currently only the Old Revision is supported     |
++------------------+--------------------------------------------------+
 ```
 
 - FW6C:
@@ -138,21 +165,58 @@ used SoC.
 +------------------+--------------------------------------------------+
 | PCH              | Kaby Lake U w/ iHDCP2.2 Premium                  |
 +------------------+--------------------------------------------------+
-| Super I/O, EC    | ITE IT8772E                                      |
+| Super I/O, EC    | Old revision: ITE IT8772E, New rev.: ITE IT8613E |
 +------------------+--------------------------------------------------+
 | Coprocessor      | Intel Management Engine                          |
 +------------------+--------------------------------------------------+
+| Support          | Currently only the Old Revision is supported     |
++------------------+--------------------------------------------------+
+```
+
+- FW6D:
+
+```{eval-rst}
++------------------+--------------------------------------------------+
+| CPU              | Intel Core i5-8250U                              |
++------------------+--------------------------------------------------+
+| PCH              | Kaby Lake U w/ iHDCP2.2 Premium                  |
++------------------+--------------------------------------------------+
+| Super I/O, EC    | ITE IT8613E                                      |
++------------------+--------------------------------------------------+
+| Coprocessor      | Intel Management Engine                          |
++------------------+--------------------------------------------------+
+| Support          | Currently not supported                          |
++------------------+--------------------------------------------------+
+```
+
+- FW6E:
+
+```{eval-rst}
++------------------+--------------------------------------------------+
+| CPU              | Intel Core i7-8550U                              |
++------------------+--------------------------------------------------+
+| PCH              | Kaby Lake U w/ iHDCP2.2 Premium                  |
++------------------+--------------------------------------------------+
+| Super I/O, EC    | ITE IT8613E                                      |
++------------------+--------------------------------------------------+
+| Coprocessor      | Intel Management Engine                          |
++------------------+--------------------------------------------------+
+| Support          | Currently not supported                          |
++------------------+--------------------------------------------------+
 ```
 
 ## Other compatible boards
 
 As Protectli licenses and uses [Yanling] appliances with no modifications
 to the actual hardware, any compatible [Yanling] appliances would work.
-Specifically, look for hardware with the same CPU and NIC and coreboot
-should be able to compile and boot with no modifications required.
+Specifically, look for hardware with the same CPU, NIC, and Super I/O chip
+and coreboot should be able to compile and boot with no modifications
+required.
 
 [Protectli FW6]: https://protectli.com/vault-6-port/
 [website]: https://protectli.com/kb/coreboot-on-the-vault/
 [MX25L6406E]: https://www.macronix.com/Lists/Datasheet/Attachments/7370/MX25L6406E,%203V,%2064Mb,%20v1.9.pdf
 [flashrom]: https://flashrom.org/
 [Yanling]: http://www.ylgkdn.cn/
+[New Revision FW6A Datasheet]: https://kb.protectli.com/wp-content/uploads/sites/9/2025/04/FW6A-Datasheet-20250204.pdf
+[Old Revision FW6 Series Hardware Overview]: https://kb.protectli.com/kb/fw6-hardware-overview/

From 3cde265c2821556a0080a584eaa08f0094462357 Mon Sep 17 00:00:00 2001
From: Angel Pons <th3fanbus@gmail.com>
Date: Mon, 23 Feb 2026 19:07:03 +0100
Subject: [PATCH 3466/3886] sb/intel/lynxpoint/acpi/xhci.asl: Drop redundant
 writes

Setting `SWAI` and `SAIP` is already done in the LPT-H and LPT-LP
specific branches, so there's no need to do it again. WPT-LP does
NOT need these writes.

Change-Id: Ib5156fab1384cdc531fc1d49dd61e5fc4600e894
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91391
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
---
 src/southbridge/intel/lynxpoint/acpi/xhci.asl | 12 ------------
 1 file changed, 12 deletions(-)

diff --git a/src/southbridge/intel/lynxpoint/acpi/xhci.asl b/src/southbridge/intel/lynxpoint/acpi/xhci.asl
index d059e08815..d5b97d03e3 100644
--- a/src/southbridge/intel/lynxpoint/acpi/xhci.asl
+++ b/src/southbridge/intel/lynxpoint/acpi/xhci.asl
@@ -256,12 +256,6 @@ Device (XHCI)
 		^SAIP = 0
 #endif
 
-		// Clear PCI CFG offset 0x40[11]
-		^SWAI = 0
-
-		// Clear PCI CFG offset 0x44[13:12]
-		^SAIP = 0
-
 		Return ()
 	}
 
@@ -332,12 +326,6 @@ Device (XHCI)
 		^SAIP = 1
 #endif
 
-		// Set PCI CFG offset 0x40[11]
-		^SWAI = 1
-
-		// Set PCI CFG offset 0x44[13:12]
-		^SAIP = 1
-
 		// Put device in D3
 		^D0D3 = 3
 

From 813edbbde879e4db365435f3fb025985a0cdfec8 Mon Sep 17 00:00:00 2001
From: Angel Pons <th3fanbus@gmail.com>
Date: Mon, 23 Feb 2026 20:43:45 +0100
Subject: [PATCH 3467/3886] sb/intel/lynxpoint/acpi/xhci.asl: Use macros for
 constants

Declaring named objects for constants is not ideal, especially when done
inside of a method (it is highly inefficient). Instead, use preprocessor
defines.

Change-Id: I1143f2aa09a2ed04da92edcf6ae9d832c0b5e2fa
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91393
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
---
 src/southbridge/intel/lynxpoint/acpi/xhci.asl | 42 +++++++++----------
 1 file changed, 20 insertions(+), 22 deletions(-)

diff --git a/src/southbridge/intel/lynxpoint/acpi/xhci.asl b/src/southbridge/intel/lynxpoint/acpi/xhci.asl
index d5b97d03e3..9c7bb2c1ac 100644
--- a/src/southbridge/intel/lynxpoint/acpi/xhci.asl
+++ b/src/southbridge/intel/lynxpoint/acpi/xhci.asl
@@ -6,9 +6,6 @@ Device (XHCI)
 {
 	Name (_ADR, 0x00140000)
 
-	Name (PLSD, 5) // Port Link State - RxDetect
-	Name (PLSP, 7) // Port Link State - Polling
-
 	OperationRegion (XPRT, PCI_Config, 0, 0x100)
 	Field (XPRT, AnyAcc, NoLock, Preserve)
 	{
@@ -57,27 +54,24 @@ Device (XHCI)
 			PSC3, 32,
 		}
 
-		// Port Enabled/Disabled (Bit 1)
-		Name (PEDB, 1 << 1)
-
-		// Change Status (Bits 23:17)
-		Name (CHST, 0x7f << 17)
+#define PSC_PORT_ENABLED	(1 << 1)
+#define PSC_PORT_CHANGE_BITS	(0x7f << 17)
 
 		// Port 0
-		Local0 = PSC0 & ~PEDB
-		PSC0 = Local0 | CHST
+		Local0 = PSC0 & ~PSC_PORT_ENABLED
+		PSC0 = Local0 | PSC_PORT_CHANGE_BITS
 
 		// Port 1
-		Local0 = PSC1 & ~PEDB
-		PSC1 = Local0 | CHST
+		Local0 = PSC1 & ~PSC_PORT_ENABLED
+		PSC1 = Local0 | PSC_PORT_CHANGE_BITS
 
 		// Port 2
-		Local0 = PSC2 & ~PEDB
-		PSC2 = Local0 | CHST
+		Local0 = PSC2 & ~PSC_PORT_ENABLED
+		PSC2 = Local0 | PSC_PORT_CHANGE_BITS
 
 		// Port 3
-		Local0 = PSC3 & ~PEDB
-		PSC3 = Local0 | CHST
+		Local0 = PSC3 & ~PSC_PORT_ENABLED
+		PSC3 = Local0 | PSC_PORT_CHANGE_BITS
 	}
 
 	Method (LPS0, 0, Serialized)
@@ -127,10 +121,12 @@ Device (XHCI)
 			WPR4, 1,	// [31] Warm Port Reset
 		}
 
+#define PLS_POLLING 7
+
 		// Wait for all powered ports to finish polling
 		Local0 = 10
-		While ((PPR1 == 1 && PLS1 == PLSP || PPR2 == 1 && PLS2 == PLSP) ||
-		       (PPR3 == 1 && PLS3 == PLSP || PPR4 == 1 && PLS4 == PLSP))
+		While ((PPR1 == 1 && PLS1 == PLS_POLLING || PPR2 == 1 && PLS2 == PLS_POLLING) ||
+		       (PPR3 == 1 && PLS3 == PLS_POLLING || PPR4 == 1 && PLS4 == PLS_POLLING))
 		{
 			If (Local0 == 0) {
 				Break
@@ -151,19 +147,21 @@ Device (XHCI)
 		Local3 = 0
 		Local4 = 0
 
-		If (PLS1 == PLSD && (CSC1 == 0 && PPR1 == 1)) {
+#define PLS_RX_DETECT 5
+
+		If (PLS1 == PLS_RX_DETECT && (CSC1 == 0 && PPR1 == 1)) {
 			WPR1 = 1	// Issue warm reset
 			Local1 = 1
 		}
-		If (PLS2 == PLSD && (CSC2 == 0 && PPR2 == 1)) {
+		If (PLS2 == PLS_RX_DETECT && (CSC2 == 0 && PPR2 == 1)) {
 			WPR2 = 1	// Issue warm reset
 			Local2 = 1
 		}
-		If (PLS3 == PLSD && (CSC3 == 0 && PPR3 == 1)) {
+		If (PLS3 == PLS_RX_DETECT && (CSC3 == 0 && PPR3 == 1)) {
 			WPR3 = 1	// Issue warm reset
 			Local3 = 1
 		}
-		If (PLS4 == PLSD && (CSC4 == 0 && PPR4 == 1)) {
+		If (PLS4 == PLS_RX_DETECT && (CSC4 == 0 && PPR4 == 1)) {
 			WPR4 = 1	// Issue warm reset
 			Local4 = 1
 		}

From 72ecebf0c3a9cc1fba650fa1165aae4a0a7c8e6f Mon Sep 17 00:00:00 2001
From: Angel Pons <th3fanbus@gmail.com>
Date: Mon, 23 Feb 2026 20:48:41 +0100
Subject: [PATCH 3468/3886] soc/intel/broadwell/acpi/xhci.asl: Use macros for
 constants

Declaring named objects for constants is not ideal, especially when done
inside of a method (it is highly inefficient). Instead, use preprocessor
defines.

Change-Id: I2d9d17b820ee72ba628b44ae508a7c467c023dd9
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91394
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
---
 src/soc/intel/broadwell/pch/acpi/xhci.asl | 42 +++++++++++------------
 1 file changed, 20 insertions(+), 22 deletions(-)

diff --git a/src/soc/intel/broadwell/pch/acpi/xhci.asl b/src/soc/intel/broadwell/pch/acpi/xhci.asl
index e98bd42637..d040201e5b 100644
--- a/src/soc/intel/broadwell/pch/acpi/xhci.asl
+++ b/src/soc/intel/broadwell/pch/acpi/xhci.asl
@@ -6,9 +6,6 @@ Device (XHCI)
 {
 	Name (_ADR, 0x00140000)
 
-	Name (PLSD, 5) // Port Link State - RxDetect
-	Name (PLSP, 7) // Port Link State - Polling
-
 	OperationRegion (XPRT, PCI_Config, 0, 0x100)
 	Field (XPRT, AnyAcc, NoLock, Preserve)
 	{
@@ -57,27 +54,24 @@ Device (XHCI)
 			PSC3, 32,
 		}
 
-		// Port Enabled/Disabled (Bit 1)
-		Name (PEDB, 1 << 1)
-
-		// Change Status (Bits 23:17)
-		Name (CHST, 0x7f << 17)
+#define PSC_PORT_ENABLED	(1 << 1)
+#define PSC_PORT_CHANGE_BITS	(0x7f << 17)
 
 		// Port 0
-		Local0 = PSC0 & ~PEDB
-		PSC0 = Local0 | CHST
+		Local0 = PSC0 & ~PSC_PORT_ENABLED
+		PSC0 = Local0 | PSC_PORT_CHANGE_BITS
 
 		// Port 1
-		Local0 = PSC1 & ~PEDB
-		PSC1 = Local0 | CHST
+		Local0 = PSC1 & ~PSC_PORT_ENABLED
+		PSC1 = Local0 | PSC_PORT_CHANGE_BITS
 
 		// Port 2
-		Local0 = PSC2 & ~PEDB
-		PSC2 = Local0 | CHST
+		Local0 = PSC2 & ~PSC_PORT_ENABLED
+		PSC2 = Local0 | PSC_PORT_CHANGE_BITS
 
 		// Port 3
-		Local0 = PSC3 & ~PEDB
-		PSC3 = Local0 | CHST
+		Local0 = PSC3 & ~PSC_PORT_ENABLED
+		PSC3 = Local0 | PSC_PORT_CHANGE_BITS
 	}
 
 	Method (LPS0, 0, Serialized)
@@ -127,10 +121,12 @@ Device (XHCI)
 			WPR4, 1,	// [31] Warm Port Reset
 		}
 
+#define PLS_POLLING 7
+
 		// Wait for all powered ports to finish polling
 		Local0 = 10
-		While ((PPR1 == 1 && PLS1 == PLSP || PPR2 == 1 && PLS2 == PLSP) ||
-		       (PPR3 == 1 && PLS3 == PLSP || PPR4 == 1 && PLS4 == PLSP))
+		While ((PPR1 == 1 && PLS1 == PLS_POLLING || PPR2 == 1 && PLS2 == PLS_POLLING) ||
+		       (PPR3 == 1 && PLS3 == PLS_POLLING || PPR4 == 1 && PLS4 == PLS_POLLING))
 		{
 			If (Local0 == 0) {
 				Break
@@ -151,19 +147,21 @@ Device (XHCI)
 		Local3 = 0
 		Local4 = 0
 
-		If (PLS1 == PLSD && (CSC1 == 0 && PPR1 == 1)) {
+#define PLS_RX_DETECT 5
+
+		If (PLS1 == PLS_RX_DETECT && (CSC1 == 0 && PPR1 == 1)) {
 			WPR1 = 1	// Issue warm reset
 			Local1 = 1
 		}
-		If (PLS2 == PLSD && (CSC2 == 0 && PPR2 == 1)) {
+		If (PLS2 == PLS_RX_DETECT && (CSC2 == 0 && PPR2 == 1)) {
 			WPR2 = 1	// Issue warm reset
 			Local2 = 1
 		}
-		If (PLS3 == PLSD && (CSC3 == 0 && PPR3 == 1)) {
+		If (PLS3 == PLS_RX_DETECT && (CSC3 == 0 && PPR3 == 1)) {
 			WPR3 = 1	// Issue warm reset
 			Local3 = 1
 		}
-		If (PLS4 == PLSD && (CSC4 == 0 && PPR4 == 1)) {
+		If (PLS4 == PLS_RX_DETECT && (CSC4 == 0 && PPR4 == 1)) {
 			WPR4 = 1	// Issue warm reset
 			Local4 = 1
 		}

From 253689aebb5b59f22d11a65182c33da5a6a24547 Mon Sep 17 00:00:00 2001
From: Angel Pons <th3fanbus@gmail.com>
Date: Mon, 23 Feb 2026 20:50:31 +0100
Subject: [PATCH 3469/3886] sb/intel/lynxpoint/acpi/xhci.asl: Guard PCH-LP
 methods

The `LPCL` and `LPS0` methods are specific to PCH-LP, and are not used
at all on PCH-H. To prevent accidental use and to reduce the DSDT size
on PCH-H builds, add some preprocessor guards around those methods.

For the ASRock Z97 Extreme, `build/dsdt.aml` size goes from 8538 bytes
down to 7904 bytes, a reduction of about 7%.

Change-Id: I775dcde4932f6039ba7d5673364e495837a386da
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91395
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
---
 src/southbridge/intel/lynxpoint/acpi/xhci.asl | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/src/southbridge/intel/lynxpoint/acpi/xhci.asl b/src/southbridge/intel/lynxpoint/acpi/xhci.asl
index 9c7bb2c1ac..c38a592372 100644
--- a/src/southbridge/intel/lynxpoint/acpi/xhci.asl
+++ b/src/southbridge/intel/lynxpoint/acpi/xhci.asl
@@ -38,6 +38,7 @@ Device (XHCI)
 		PR3M, 32,  // USB3PRM
 	}
 
+#if CONFIG(INTEL_LYNXPOINT_LP)
 	// Clear status bits
 	Method (LPCL, 0, Serialized)
 	{
@@ -181,6 +182,7 @@ Device (XHCI)
 		// Clear status bits in all ports
 		LPCL ()
 	}
+#endif
 
 	Method (_PSC, 0, NotSerialized)
 	{

From a4bc3131a5fa0787b7024e5115ff3f9ec33ad291 Mon Sep 17 00:00:00 2001
From: Jeremy Compostella <jeremy.compostella@intel.com>
Date: Wed, 25 Feb 2026 10:33:14 -0800
Subject: [PATCH 3470/3886] soc/intel/common/feature/gspi: Add common devfn
 mapping

Add a common implementation of gspi_soc_bus_to_devfn() to reduce code
duplication across multiple Intel SoC platforms. This implementation
uses the SOC_GSPI_DEVFN(n) macro which must be defined by each platform
in their soc/pci_devs.h header to map GSPI bus numbers to PCI device and
function values.

This change enables consolidation of nearly identical gspi.c files from
Alder Lake, Meteor Lake, Panther Lake, Tiger Lake, Jasper Lake, Elkhart
Lake, Cannon Lake, and Skylake platforms.

The implementation leverages the existing
CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX Kconfig option and includes
compile-time assertions to ensure the configuration is within supported
limits (up to 7 GSPI controllers).

Change-Id: I776cebd70968fd4b8bbab176bca0a446a0cc76ab
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91322
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/soc/intel/common/feature/gspi/Kconfig     |  9 ++++
 src/soc/intel/common/feature/gspi/Makefile.mk |  3 ++
 .../intel/common/feature/gspi/gspi_devfn.c    | 44 +++++++++++++++++++
 3 files changed, 56 insertions(+)
 create mode 100644 src/soc/intel/common/feature/gspi/Kconfig
 create mode 100644 src/soc/intel/common/feature/gspi/Makefile.mk
 create mode 100644 src/soc/intel/common/feature/gspi/gspi_devfn.c

diff --git a/src/soc/intel/common/feature/gspi/Kconfig b/src/soc/intel/common/feature/gspi/Kconfig
new file mode 100644
index 0000000000..4ac4e47693
--- /dev/null
+++ b/src/soc/intel/common/feature/gspi/Kconfig
@@ -0,0 +1,9 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
+config SOC_INTEL_COMMON_FEATURE_GSPI_DEVFN
+	bool
+	help
+	  Common GSPI device function to bus mapping implementation.
+	  SoCs using this must define SOC_GSPI_DEVFN(n) macro in their
+	  pci_devs.h and CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX in their
+	  Kconfig.
diff --git a/src/soc/intel/common/feature/gspi/Makefile.mk b/src/soc/intel/common/feature/gspi/Makefile.mk
new file mode 100644
index 0000000000..6ac84bac54
--- /dev/null
+++ b/src/soc/intel/common/feature/gspi/Makefile.mk
@@ -0,0 +1,3 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
+all-$(CONFIG_SOC_INTEL_COMMON_FEATURE_GSPI_DEVFN) += gspi_devfn.c
diff --git a/src/soc/intel/common/feature/gspi/gspi_devfn.c b/src/soc/intel/common/feature/gspi/gspi_devfn.c
new file mode 100644
index 0000000000..23cdaaaf14
--- /dev/null
+++ b/src/soc/intel/common/feature/gspi/gspi_devfn.c
@@ -0,0 +1,44 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <intelblocks/gspi.h>
+#include <soc/pci_devs.h>
+
+/*
+ * Ensure the platform defines SOC_GSPI_DEVFN(n) macro to map GSPI bus numbers
+ * to their PCI device/function values. The macro should be defined in the
+ * platform's soc/pci_devs.h header.
+ */
+
+_Static_assert(CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX <= 7,
+	       "CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX greater than 7 is not supported.");
+
+int gspi_soc_bus_to_devfn(unsigned int gspi_bus)
+{
+	switch (gspi_bus) {
+	case 0:
+		return SOC_GSPI_DEVFN(0);
+	case 1:
+		return SOC_GSPI_DEVFN(1);
+#if CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX > 2
+	case 2:
+		return SOC_GSPI_DEVFN(2);
+#endif
+#if CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX > 3
+	case 3:
+		return SOC_GSPI_DEVFN(3);
+#endif
+#if CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX > 4
+	case 4:
+		return SOC_GSPI_DEVFN(4);
+#endif
+#if CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX > 5
+	case 5:
+		return SOC_GSPI_DEVFN(5);
+#endif
+#if CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX > 6
+	case 6:
+		return SOC_GSPI_DEVFN(6);
+#endif
+	}
+	return -1;
+}

From 039f21b5e36d1010ff4c61def737556ce31714ca Mon Sep 17 00:00:00 2001
From: Jeremy Compostella <jeremy.compostella@intel.com>
Date: Wed, 25 Feb 2026 10:44:17 -0800
Subject: [PATCH 3471/3886] soc/intel/alderlake: Use common GSPI devfn mapping

Replace platform-specific gspi.c with the common GSPI device function
mapping implementation.

Changes:
- Select SOC_INTEL_COMMON_FEATURE_GSPI_DEVFN in Kconfig
- Define SOC_GSPI_DEVFN(n) macro in pci_devs.h
- Remove platform-specific gspi.c file

Change-Id: Ia1b2c3d4e5f6a7b8c9d0e1f2a3b4c5d6e7f8a9b0
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91314
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/soc/intel/alderlake/Kconfig               |  1 +
 src/soc/intel/alderlake/Makefile.mk           |  1 -
 src/soc/intel/alderlake/gspi.c                | 25 -------------------
 .../intel/alderlake/include/soc/pci_devs.h    |  1 +
 4 files changed, 2 insertions(+), 26 deletions(-)
 delete mode 100644 src/soc/intel/alderlake/gspi.c

diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig
index c78a09076d..4ab0b1c820 100644
--- a/src/soc/intel/alderlake/Kconfig
+++ b/src/soc/intel/alderlake/Kconfig
@@ -85,6 +85,7 @@ config SOC_INTEL_ALDERLAKE
 	select SOC_INTEL_COMMON_BLOCK_XHCI
 	select SOC_INTEL_COMMON_BLOCK_XHCI_ELOG
 	select SOC_INTEL_COMMON_FEATURE
+	select SOC_INTEL_COMMON_FEATURE_GSPI_DEVFN
 	select SOC_INTEL_COMMON_FEATURE_I2C_DEVFN
 	select SOC_INTEL_COMMON_FEATURE_UART_DEVICES
 	select SOC_INTEL_COMMON_FSP_RESET
diff --git a/src/soc/intel/alderlake/Makefile.mk b/src/soc/intel/alderlake/Makefile.mk
index 2e97718bc2..35f84a5cb4 100644
--- a/src/soc/intel/alderlake/Makefile.mk
+++ b/src/soc/intel/alderlake/Makefile.mk
@@ -5,7 +5,6 @@ subdirs-y += ../../../cpu/intel/microcode
 subdirs-y += ../../../cpu/intel/turbo
 
 # all (bootblock, verstage, romstage, postcar, ramstage)
-all-y += gspi.c
 all-y += pmutil.c
 all-y += spi.c
 
diff --git a/src/soc/intel/alderlake/gspi.c b/src/soc/intel/alderlake/gspi.c
deleted file mode 100644
index dd07b07f1a..0000000000
--- a/src/soc/intel/alderlake/gspi.c
+++ /dev/null
@@ -1,25 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-or-later */
-
-/*
- * This file is created based on Intel Alder Lake Processor PCH Datasheet
- * Document number: 621483
- * Chapter number: 11
- */
-
-#include <intelblocks/gspi.h>
-#include <soc/pci_devs.h>
-
-int gspi_soc_bus_to_devfn(unsigned int gspi_bus)
-{
-	switch (gspi_bus) {
-	case 0:
-		return PCH_DEVFN_GSPI0;
-	case 1:
-		return PCH_DEVFN_GSPI1;
-	case 2:
-		return PCH_DEVFN_GSPI2;
-	case 3:
-		return PCH_DEVFN_GSPI3;
-	}
-	return -1;
-}
diff --git a/src/soc/intel/alderlake/include/soc/pci_devs.h b/src/soc/intel/alderlake/include/soc/pci_devs.h
index 13cea6d2fc..15ec661870 100644
--- a/src/soc/intel/alderlake/include/soc/pci_devs.h
+++ b/src/soc/intel/alderlake/include/soc/pci_devs.h
@@ -282,6 +282,7 @@
 #define PCI_DEVFN_UART0		PCH_DEVFN_UART0
 #define PCI_DEVFN_UART1		PCH_DEVFN_UART1
 #define PCI_DEVFN_UART2		PCH_DEVFN_UART2
+#define SOC_GSPI_DEVFN(n)	PCH_DEVFN_GSPI##n
 
 #endif
 

From 6459039b76c14e04ea79c6b025ddc73a502d58be Mon Sep 17 00:00:00 2001
From: Jeremy Compostella <jeremy.compostella@intel.com>
Date: Wed, 25 Feb 2026 10:44:17 -0800
Subject: [PATCH 3472/3886] soc/intel/meteorlake: Use common GSPI devfn mapping

Replace platform-specific gspi.c with the common GSPI device function
mapping implementation.

Changes:
- Select SOC_INTEL_COMMON_FEATURE_GSPI_DEVFN in Kconfig
- Define SOC_GSPI_DEVFN(n) macro in pci_devs.h
- Remove platform-specific gspi.c file

Change-Id: Ib2c3d4e5f6a7b8c9d0e1f2a3b4c5d6e7f8a9b0c1
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91315
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/soc/intel/meteorlake/Kconfig                |  1 +
 src/soc/intel/meteorlake/Makefile.mk            |  1 -
 src/soc/intel/meteorlake/gspi.c                 | 17 -----------------
 src/soc/intel/meteorlake/include/soc/pci_devs.h |  1 +
 4 files changed, 2 insertions(+), 18 deletions(-)
 delete mode 100644 src/soc/intel/meteorlake/gspi.c

diff --git a/src/soc/intel/meteorlake/Kconfig b/src/soc/intel/meteorlake/Kconfig
index 7d7d2df513..1d341d1484 100644
--- a/src/soc/intel/meteorlake/Kconfig
+++ b/src/soc/intel/meteorlake/Kconfig
@@ -87,6 +87,7 @@ config SOC_INTEL_METEORLAKE
 	select SOC_INTEL_COMMON_BLOCK_XHCI
 	select SOC_INTEL_COMMON_BLOCK_XHCI_ELOG
 	select SOC_INTEL_COMMON_FEATURE
+	select SOC_INTEL_COMMON_FEATURE_GSPI_DEVFN
 	select SOC_INTEL_COMMON_FEATURE_I2C_DEVFN
 	select SOC_INTEL_COMMON_FEATURE_UART_DEVICES
 	select SOC_INTEL_COMMON_BASECODE
diff --git a/src/soc/intel/meteorlake/Makefile.mk b/src/soc/intel/meteorlake/Makefile.mk
index 1e9a1fc93d..60044f376f 100644
--- a/src/soc/intel/meteorlake/Makefile.mk
+++ b/src/soc/intel/meteorlake/Makefile.mk
@@ -6,7 +6,6 @@ subdirs-y += ../../../cpu/intel/microcode
 subdirs-y += ../../../cpu/intel/turbo
 
 # all (bootblock, verstage, romstage, postcar, ramstage)
-all-y += gspi.c
 all-y += pmutil.c
 all-y += spi.c
 all-y += gpio.c
diff --git a/src/soc/intel/meteorlake/gspi.c b/src/soc/intel/meteorlake/gspi.c
deleted file mode 100644
index 387d3e3949..0000000000
--- a/src/soc/intel/meteorlake/gspi.c
+++ /dev/null
@@ -1,17 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-or-later */
-
-#include <intelblocks/gspi.h>
-#include <soc/pci_devs.h>
-
-int gspi_soc_bus_to_devfn(unsigned int gspi_bus)
-{
-	switch (gspi_bus) {
-	case 0:
-		return PCI_DEVFN_GSPI0;
-	case 1:
-		return PCI_DEVFN_GSPI1;
-	case 2:
-		return PCI_DEVFN_GSPI2;
-	}
-	return -1;
-}
diff --git a/src/soc/intel/meteorlake/include/soc/pci_devs.h b/src/soc/intel/meteorlake/include/soc/pci_devs.h
index 034f5e6b6c..17f4526538 100644
--- a/src/soc/intel/meteorlake/include/soc/pci_devs.h
+++ b/src/soc/intel/meteorlake/include/soc/pci_devs.h
@@ -242,5 +242,6 @@
 #define SA_DEV_IGD		PCI_DEV_IGD
 #define SA_DEVFN_IGD		PCI_DEVFN_IGD
 #define SOC_I2C_DEVFN(n)	PCI_DEVFN_I2C##n
+#define SOC_GSPI_DEVFN(n)	PCI_DEVFN_GSPI##n
 
 #endif // _SOC_METEORLAKE_PCI_DEVS_H_

From 3c92c8402acf163379ddd0ec91d4a9bb39d41f9d Mon Sep 17 00:00:00 2001
From: Jeremy Compostella <jeremy.compostella@intel.com>
Date: Wed, 25 Feb 2026 10:44:17 -0800
Subject: [PATCH 3473/3886] soc/intel/pantherlake: Use common GSPI devfn
 mapping

Replace platform-specific gspi.c with the common GSPI device function
mapping implementation.

Changes:
- Select SOC_INTEL_COMMON_FEATURE_GSPI_DEVFN in Kconfig
- Define SOC_GSPI_DEVFN(n) macro in pci_devs.h
- Remove platform-specific gspi.c file

TEST=Panther Lake Fatcat OS boots properly

Change-Id: Ic3d4e5f6a7b8c9d0e1f2a3b4c5d6e7f8a9b0c1d2
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91316
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/soc/intel/pantherlake/Kconfig               |  1 +
 src/soc/intel/pantherlake/Makefile.mk           |  1 -
 src/soc/intel/pantherlake/gspi.c                | 17 -----------------
 .../intel/pantherlake/include/soc/pci_devs.h    |  1 +
 4 files changed, 2 insertions(+), 18 deletions(-)
 delete mode 100644 src/soc/intel/pantherlake/gspi.c

diff --git a/src/soc/intel/pantherlake/Kconfig b/src/soc/intel/pantherlake/Kconfig
index 2e1bc2ef10..133a0b8684 100644
--- a/src/soc/intel/pantherlake/Kconfig
+++ b/src/soc/intel/pantherlake/Kconfig
@@ -97,6 +97,7 @@ config SOC_INTEL_PANTHERLAKE_BASE
 	select SOC_INTEL_COMMON_BLOCK_XHCI
 	select SOC_INTEL_COMMON_BLOCK_XHCI_ELOG
 	select SOC_INTEL_COMMON_FEATURE
+	select SOC_INTEL_COMMON_FEATURE_GSPI_DEVFN
 	select SOC_INTEL_COMMON_FEATURE_I2C_DEVFN
 	select SOC_INTEL_COMMON_FEATURE_UART_DEVICES
 	select SOC_INTEL_COMMON_FSP_RESET
diff --git a/src/soc/intel/pantherlake/Makefile.mk b/src/soc/intel/pantherlake/Makefile.mk
index dadba99ccd..5f956db228 100644
--- a/src/soc/intel/pantherlake/Makefile.mk
+++ b/src/soc/intel/pantherlake/Makefile.mk
@@ -7,7 +7,6 @@ subdirs-y += ../../../cpu/intel/microcode
 subdirs-y += ../../../cpu/intel/turbo
 
 # all (bootblock, verstage, romstage, postcar, ramstage)
-all-y += gspi.c
 all-y += pmutil.c
 all-y += spi.c
 all-y += gpio.c
diff --git a/src/soc/intel/pantherlake/gspi.c b/src/soc/intel/pantherlake/gspi.c
deleted file mode 100644
index 387d3e3949..0000000000
--- a/src/soc/intel/pantherlake/gspi.c
+++ /dev/null
@@ -1,17 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-or-later */
-
-#include <intelblocks/gspi.h>
-#include <soc/pci_devs.h>
-
-int gspi_soc_bus_to_devfn(unsigned int gspi_bus)
-{
-	switch (gspi_bus) {
-	case 0:
-		return PCI_DEVFN_GSPI0;
-	case 1:
-		return PCI_DEVFN_GSPI1;
-	case 2:
-		return PCI_DEVFN_GSPI2;
-	}
-	return -1;
-}
diff --git a/src/soc/intel/pantherlake/include/soc/pci_devs.h b/src/soc/intel/pantherlake/include/soc/pci_devs.h
index a1ef4f4c32..3a41280a26 100644
--- a/src/soc/intel/pantherlake/include/soc/pci_devs.h
+++ b/src/soc/intel/pantherlake/include/soc/pci_devs.h
@@ -257,5 +257,6 @@
 #define SA_DEV_IGD		PCI_DEV_IGD
 #define SA_DEVFN_IGD		PCI_DEVFN_IGD
 #define SOC_I2C_DEVFN(n)	PCI_DEVFN_I2C##n
+#define SOC_GSPI_DEVFN(n)	PCI_DEVFN_GSPI##n
 
 #endif // _SOC_PANTHERLAKE_PCI_DEVS_H_

From 66a6c25ef8cc1e0248d8f8cf0938397578d99bcc Mon Sep 17 00:00:00 2001
From: Jeremy Compostella <jeremy.compostella@intel.com>
Date: Wed, 25 Feb 2026 10:44:18 -0800
Subject: [PATCH 3474/3886] soc/intel/tigerlake: Use common GSPI devfn mapping

Replace platform-specific gspi.c with the common GSPI device function
mapping implementation.

Changes:
- Select SOC_INTEL_COMMON_FEATURE_GSPI_DEVFN in Kconfig
- Define SOC_GSPI_DEVFN(n) macro in pci_devs.h
- Remove platform-specific gspi.c file

Change-Id: Id4e5f6a7b8c9d0e1f2a3b4c5d6e7f8a9b0c1d2e3
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91317
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/soc/intel/tigerlake/Kconfig               |  1 +
 src/soc/intel/tigerlake/Makefile.mk           |  1 -
 src/soc/intel/tigerlake/gspi.c                | 23 -------------------
 .../intel/tigerlake/include/soc/pci_devs.h    |  1 +
 4 files changed, 2 insertions(+), 24 deletions(-)
 delete mode 100644 src/soc/intel/tigerlake/gspi.c

diff --git a/src/soc/intel/tigerlake/Kconfig b/src/soc/intel/tigerlake/Kconfig
index 48cf447bd1..38c1e8125c 100644
--- a/src/soc/intel/tigerlake/Kconfig
+++ b/src/soc/intel/tigerlake/Kconfig
@@ -73,6 +73,7 @@ config SOC_INTEL_TIGERLAKE
 	select SOC_INTEL_COMMON_BLOCK_USB4_XHCI
 	select SOC_INTEL_COMMON_BLOCK_XHCI_ELOG
 	select SOC_INTEL_COMMON_FEATURE
+	select SOC_INTEL_COMMON_FEATURE_GSPI_DEVFN
 	select SOC_INTEL_COMMON_FEATURE_I2C_DEVFN
 	select SOC_INTEL_COMMON_FEATURE_UART_DEVICES
 	select SOC_INTEL_COMMON_FSP_RESET
diff --git a/src/soc/intel/tigerlake/Makefile.mk b/src/soc/intel/tigerlake/Makefile.mk
index 53a5d9580f..895395d362 100644
--- a/src/soc/intel/tigerlake/Makefile.mk
+++ b/src/soc/intel/tigerlake/Makefile.mk
@@ -6,7 +6,6 @@ subdirs-y += ../../../cpu/intel/microcode
 subdirs-y += ../../../cpu/intel/turbo
 
 # all (bootblock, verstage, romstage, postcar, ramstage)
-all-y += gspi.c
 all-y += pmutil.c
 all-y += spi.c
 
diff --git a/src/soc/intel/tigerlake/gspi.c b/src/soc/intel/tigerlake/gspi.c
deleted file mode 100644
index 83552f9435..0000000000
--- a/src/soc/intel/tigerlake/gspi.c
+++ /dev/null
@@ -1,23 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-or-later */
-
-/*
- * This file is created based on Intel Tiger Lake Processor PCH Datasheet
- * Document number: 575857
- * Chapter number: 11
- */
-
-#include <intelblocks/gspi.h>
-#include <soc/pci_devs.h>
-
-int gspi_soc_bus_to_devfn(unsigned int gspi_bus)
-{
-	switch (gspi_bus) {
-	case 0:
-		return PCH_DEVFN_GSPI0;
-	case 1:
-		return PCH_DEVFN_GSPI1;
-	case 2:
-		return PCH_DEVFN_GSPI2;
-	}
-	return -1;
-}
diff --git a/src/soc/intel/tigerlake/include/soc/pci_devs.h b/src/soc/intel/tigerlake/include/soc/pci_devs.h
index 29216f5670..2f36bd159c 100644
--- a/src/soc/intel/tigerlake/include/soc/pci_devs.h
+++ b/src/soc/intel/tigerlake/include/soc/pci_devs.h
@@ -249,6 +249,7 @@
 #define PCI_DEVFN_UART0		PCH_DEVFN_UART0
 #define PCI_DEVFN_UART1		PCH_DEVFN_UART1
 #define PCI_DEVFN_UART2		PCH_DEVFN_UART2
+#define SOC_GSPI_DEVFN(n)	PCH_DEVFN_GSPI##n
 
 #endif
 

From 78ef2d0433fc98ffd2469ec25bb8201d0c325cd8 Mon Sep 17 00:00:00 2001
From: Jeremy Compostella <jeremy.compostella@intel.com>
Date: Wed, 25 Feb 2026 10:44:18 -0800
Subject: [PATCH 3475/3886] soc/intel/jasperlake: Use common GSPI devfn mapping

Replace platform-specific gspi.c with the common GSPI device function
mapping implementation.

Changes:
- Select SOC_INTEL_COMMON_FEATURE_GSPI_DEVFN in Kconfig
- Define SOC_GSPI_DEVFN(n) macro in pci_devs.h
- Remove platform-specific gspi.c file

Change-Id: Ie5f6a7b8c9d0e1f2a3b4c5d6e7f8a9b0c1d2e3f4
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91318
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
---
 src/soc/intel/jasperlake/Kconfig                |  1 +
 src/soc/intel/jasperlake/Makefile.mk            |  1 -
 src/soc/intel/jasperlake/gspi.c                 | 17 -----------------
 src/soc/intel/jasperlake/include/soc/pci_devs.h |  1 +
 4 files changed, 2 insertions(+), 18 deletions(-)
 delete mode 100644 src/soc/intel/jasperlake/gspi.c

diff --git a/src/soc/intel/jasperlake/Kconfig b/src/soc/intel/jasperlake/Kconfig
index b1257a76a0..7f6831e9c1 100644
--- a/src/soc/intel/jasperlake/Kconfig
+++ b/src/soc/intel/jasperlake/Kconfig
@@ -56,6 +56,7 @@ config SOC_INTEL_JASPERLAKE
 	select SOC_INTEL_COMMON_BLOCK_SMM_IO_TRAP
 	select SOC_INTEL_COMMON_BLOCK_XHCI_ELOG
 	select SOC_INTEL_COMMON_FEATURE
+	select SOC_INTEL_COMMON_FEATURE_GSPI_DEVFN
 	select SOC_INTEL_COMMON_FEATURE_I2C_DEVFN
 	select SOC_INTEL_COMMON_FEATURE_UART_DEVICES
 	select SOC_INTEL_COMMON_FSP_RESET
diff --git a/src/soc/intel/jasperlake/Makefile.mk b/src/soc/intel/jasperlake/Makefile.mk
index 875cc76a9c..73765deb13 100644
--- a/src/soc/intel/jasperlake/Makefile.mk
+++ b/src/soc/intel/jasperlake/Makefile.mk
@@ -6,7 +6,6 @@ subdirs-y += ../../../cpu/intel/microcode
 subdirs-y += ../../../cpu/intel/turbo
 
 # all (bootblock, verstage, romstage, postcar, ramstage)
-all-y += gspi.c
 all-y += pmutil.c
 all-y += spi.c
 
diff --git a/src/soc/intel/jasperlake/gspi.c b/src/soc/intel/jasperlake/gspi.c
deleted file mode 100644
index 61ad2608db..0000000000
--- a/src/soc/intel/jasperlake/gspi.c
+++ /dev/null
@@ -1,17 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-or-later */
-
-#include <intelblocks/gspi.h>
-#include <soc/pci_devs.h>
-
-int gspi_soc_bus_to_devfn(unsigned int gspi_bus)
-{
-	switch (gspi_bus) {
-	case 0:
-		return PCH_DEVFN_GSPI0;
-	case 1:
-		return PCH_DEVFN_GSPI1;
-	case 2:
-		return PCH_DEVFN_GSPI2;
-	}
-	return -1;
-}
diff --git a/src/soc/intel/jasperlake/include/soc/pci_devs.h b/src/soc/intel/jasperlake/include/soc/pci_devs.h
index 5e9107003e..f2e6dd4e7d 100644
--- a/src/soc/intel/jasperlake/include/soc/pci_devs.h
+++ b/src/soc/intel/jasperlake/include/soc/pci_devs.h
@@ -197,6 +197,7 @@
 #define PCI_DEVFN_UART0		PCH_DEVFN_UART0
 #define PCI_DEVFN_UART1		PCH_DEVFN_UART1
 #define PCI_DEVFN_UART2		PCH_DEVFN_UART2
+#define SOC_GSPI_DEVFN(n)	PCH_DEVFN_GSPI##n
 
 #endif
 

From 4aae5fb66d69f4a8342e18a871c115e952f0b4ae Mon Sep 17 00:00:00 2001
From: Jeremy Compostella <jeremy.compostella@intel.com>
Date: Wed, 25 Feb 2026 10:44:18 -0800
Subject: [PATCH 3476/3886] soc/intel/elkhartlake: Use common GSPI devfn
 mapping

Replace platform-specific gspi.c with the common GSPI device function
mapping implementation.

Changes:
- Select SOC_INTEL_COMMON_FEATURE_GSPI_DEVFN in Kconfig
- Define SOC_GSPI_DEVFN(n) macro in pci_devs.h
- Remove platform-specific gspi.c file

Change-Id: If6a7b8c9d0e1f2a3b4c5d6e7f8a9b0c1d2e3f4a5
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91319
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/soc/intel/elkhartlake/Kconfig               |  1 +
 src/soc/intel/elkhartlake/Makefile.mk           |  1 -
 src/soc/intel/elkhartlake/gspi.c                | 17 -----------------
 .../intel/elkhartlake/include/soc/pci_devs.h    |  1 +
 4 files changed, 2 insertions(+), 18 deletions(-)
 delete mode 100644 src/soc/intel/elkhartlake/gspi.c

diff --git a/src/soc/intel/elkhartlake/Kconfig b/src/soc/intel/elkhartlake/Kconfig
index 4e5b9bc99c..a15833346e 100644
--- a/src/soc/intel/elkhartlake/Kconfig
+++ b/src/soc/intel/elkhartlake/Kconfig
@@ -56,6 +56,7 @@ config SOC_INTEL_ELKHARTLAKE
 	select SOC_INTEL_COMMON_BLOCK_SMM
 	select SOC_INTEL_COMMON_BLOCK_SMM_IO_TRAP
 	select SOC_INTEL_COMMON_FEATURE
+	select SOC_INTEL_COMMON_FEATURE_GSPI_DEVFN
 	select SOC_INTEL_COMMON_FEATURE_I2C_DEVFN
 	select SOC_INTEL_COMMON_FEATURE_UART_DEVICES
 	select SOC_INTEL_COMMON_FSP_RESET
diff --git a/src/soc/intel/elkhartlake/Makefile.mk b/src/soc/intel/elkhartlake/Makefile.mk
index b457a2a53b..ee2204300c 100644
--- a/src/soc/intel/elkhartlake/Makefile.mk
+++ b/src/soc/intel/elkhartlake/Makefile.mk
@@ -6,7 +6,6 @@ subdirs-y += ../../../cpu/intel/microcode
 subdirs-y += ../../../cpu/intel/turbo
 
 # all (bootblock, verstage, romstage, postcar, ramstage)
-all-y += gspi.c
 all-y += pmutil.c
 all-y += spi.c
 
diff --git a/src/soc/intel/elkhartlake/gspi.c b/src/soc/intel/elkhartlake/gspi.c
deleted file mode 100644
index 61ad2608db..0000000000
--- a/src/soc/intel/elkhartlake/gspi.c
+++ /dev/null
@@ -1,17 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-or-later */
-
-#include <intelblocks/gspi.h>
-#include <soc/pci_devs.h>
-
-int gspi_soc_bus_to_devfn(unsigned int gspi_bus)
-{
-	switch (gspi_bus) {
-	case 0:
-		return PCH_DEVFN_GSPI0;
-	case 1:
-		return PCH_DEVFN_GSPI1;
-	case 2:
-		return PCH_DEVFN_GSPI2;
-	}
-	return -1;
-}
diff --git a/src/soc/intel/elkhartlake/include/soc/pci_devs.h b/src/soc/intel/elkhartlake/include/soc/pci_devs.h
index 885ebac506..e4e899b881 100644
--- a/src/soc/intel/elkhartlake/include/soc/pci_devs.h
+++ b/src/soc/intel/elkhartlake/include/soc/pci_devs.h
@@ -251,6 +251,7 @@
 #define PCI_DEVFN_UART0		PCH_DEVFN_UART0
 #define PCI_DEVFN_UART1		PCH_DEVFN_UART1
 #define PCI_DEVFN_UART2		PCH_DEVFN_UART2
+#define SOC_GSPI_DEVFN(n)	PCH_DEVFN_GSPI##n
 
 #endif
 

From 45d3ab84a89db62d301cbfc2fb35a99f20af6450 Mon Sep 17 00:00:00 2001
From: Jeremy Compostella <jeremy.compostella@intel.com>
Date: Wed, 25 Feb 2026 10:44:18 -0800
Subject: [PATCH 3477/3886] soc/intel/cannonlake: Use common GSPI devfn mapping

Replace platform-specific gspi.c with the common GSPI device function
mapping implementation.

Changes:
- Select SOC_INTEL_COMMON_FEATURE_GSPI_DEVFN in Kconfig
- Define SOC_GSPI_DEVFN(n) macro in pci_devs.h
- Remove platform-specific gspi.c file

Change-Id: Ia6b7c8d9e0f1a2b3c4d5e6f7a8b9c0d1e2f3a4b5
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91320
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/soc/intel/cannonlake/Kconfig                |  1 +
 src/soc/intel/cannonlake/Makefile.mk            |  5 -----
 src/soc/intel/cannonlake/gspi.c                 | 17 -----------------
 src/soc/intel/cannonlake/include/soc/pci_devs.h |  1 +
 4 files changed, 2 insertions(+), 22 deletions(-)
 delete mode 100644 src/soc/intel/cannonlake/gspi.c

diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig
index be788ae527..0389d58f9c 100644
--- a/src/soc/intel/cannonlake/Kconfig
+++ b/src/soc/intel/cannonlake/Kconfig
@@ -60,6 +60,7 @@ config SOC_INTEL_CANNONLAKE_BASE
 	select SOC_INTEL_COMMON_BLOCK_XHCI
 	select SOC_INTEL_COMMON_BLOCK_XHCI_ELOG
 	select SOC_INTEL_COMMON_FEATURE
+	select SOC_INTEL_COMMON_FEATURE_GSPI_DEVFN
 	select SOC_INTEL_COMMON_FEATURE_I2C_DEVFN
 	select SOC_INTEL_COMMON_FEATURE_UART_DEVICES
 	select SOC_INTEL_COMMON_FSP_RESET
diff --git a/src/soc/intel/cannonlake/Makefile.mk b/src/soc/intel/cannonlake/Makefile.mk
index 2f0c7c1a40..a281068425 100644
--- a/src/soc/intel/cannonlake/Makefile.mk
+++ b/src/soc/intel/cannonlake/Makefile.mk
@@ -10,13 +10,11 @@ bootblock-y += bootblock/bootblock.c
 bootblock-y += bootblock/pch.c
 bootblock-y += pmutil.c
 bootblock-y += bootblock/report_platform.c
-bootblock-y += gspi.c
 bootblock-y += spi.c
 bootblock-y += lpc.c
 bootblock-y += p2sb.c
 
 romstage-y += cnl_memcfg_init.c
-romstage-y += gspi.c
 romstage-y += lpc.c
 romstage-y += pcie_rp.c
 romstage-y += pmutil.c
@@ -30,7 +28,6 @@ ramstage-y += elog.c
 ramstage-y += finalize.c
 ramstage-y += fsp_params.c
 ramstage-y += graphics.c
-ramstage-y += gspi.c
 ramstage-y += lockdown.c
 ramstage-y += lpc.c
 ramstage-y += nhlt.c
@@ -52,10 +49,8 @@ smm-y += smihandler.c
 smm-y += xhci.c
 
 postcar-y += pmutil.c
-postcar-y += gspi.c
 postcar-y += spi.c
 
-verstage-y += gspi.c
 verstage-y += pmutil.c
 verstage-y += spi.c
 
diff --git a/src/soc/intel/cannonlake/gspi.c b/src/soc/intel/cannonlake/gspi.c
deleted file mode 100644
index 61ad2608db..0000000000
--- a/src/soc/intel/cannonlake/gspi.c
+++ /dev/null
@@ -1,17 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-or-later */
-
-#include <intelblocks/gspi.h>
-#include <soc/pci_devs.h>
-
-int gspi_soc_bus_to_devfn(unsigned int gspi_bus)
-{
-	switch (gspi_bus) {
-	case 0:
-		return PCH_DEVFN_GSPI0;
-	case 1:
-		return PCH_DEVFN_GSPI1;
-	case 2:
-		return PCH_DEVFN_GSPI2;
-	}
-	return -1;
-}
diff --git a/src/soc/intel/cannonlake/include/soc/pci_devs.h b/src/soc/intel/cannonlake/include/soc/pci_devs.h
index 607733c98e..c2d7b411ba 100644
--- a/src/soc/intel/cannonlake/include/soc/pci_devs.h
+++ b/src/soc/intel/cannonlake/include/soc/pci_devs.h
@@ -208,6 +208,7 @@
 #define PCI_DEVFN_UART0		PCH_DEVFN_UART0
 #define PCI_DEVFN_UART1		PCH_DEVFN_UART1
 #define PCI_DEVFN_UART2		PCH_DEVFN_UART2
+#define SOC_GSPI_DEVFN(n)	PCH_DEVFN_GSPI##n
 
 #endif
 

From 0668959a929f3c3ef7eb278a7c14c40b1d725be1 Mon Sep 17 00:00:00 2001
From: Jeremy Compostella <jeremy.compostella@intel.com>
Date: Wed, 25 Feb 2026 10:44:18 -0800
Subject: [PATCH 3478/3886] soc/intel/skylake: Use common GSPI devfn mapping

Replace platform-specific gspi.c with the common GSPI device function
mapping implementation.

Changes:
- Select SOC_INTEL_COMMON_FEATURE_GSPI_DEVFN in Kconfig
- Define SOC_GSPI_DEVFN(n) macro in pci_devs.h
- Remove platform-specific gspi.c file

Change-Id: Ib7c8d9e0f1a2b3c4d5e6f7a8b9c0d1e2f3a4b5c6
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91321
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
---
 src/soc/intel/skylake/Kconfig                |  1 +
 src/soc/intel/skylake/Makefile.mk            |  5 -----
 src/soc/intel/skylake/gspi.c                 | 14 --------------
 src/soc/intel/skylake/include/soc/pci_devs.h |  1 +
 4 files changed, 2 insertions(+), 19 deletions(-)
 delete mode 100644 src/soc/intel/skylake/gspi.c

diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig
index d3bdd4c8c3..e0d2c4d222 100644
--- a/src/soc/intel/skylake/Kconfig
+++ b/src/soc/intel/skylake/Kconfig
@@ -59,6 +59,7 @@ config SOC_INTEL_COMMON_SKYLAKE_BASE
 	select SOC_INTEL_COMMON_BLOCK_UART
 	select SOC_INTEL_COMMON_BLOCK_XHCI_ELOG
 	select SOC_INTEL_COMMON_FEATURE
+	select SOC_INTEL_COMMON_FEATURE_GSPI_DEVFN
 	select SOC_INTEL_COMMON_FEATURE_I2C_DEVFN
 	select SOC_INTEL_COMMON_FEATURE_UART_DEVICES
 	select SOC_INTEL_COMMON_FSP_RESET
diff --git a/src/soc/intel/skylake/Makefile.mk b/src/soc/intel/skylake/Makefile.mk
index c8513eaf73..73479d95bc 100644
--- a/src/soc/intel/skylake/Makefile.mk
+++ b/src/soc/intel/skylake/Makefile.mk
@@ -11,19 +11,16 @@ bootblock-y += bootblock/bootblock.c
 bootblock-y += bootblock/pch.c
 bootblock-y += bootblock/report_platform.c
 bootblock-y += gpio.c
-bootblock-y += gspi.c
 bootblock-y += p2sb.c
 bootblock-y += pmutil.c
 bootblock-y += spi.c
 bootblock-y += lpc.c
 
 verstage-y += gpio.c
-verstage-y += gspi.c
 verstage-y += pmutil.c
 verstage-y += spi.c
 
 romstage-y += gpio.c
-romstage-y += gspi.c
 romstage-y += me.c
 romstage-y += pcie_rp.c
 romstage-y += pmutil.c
@@ -37,7 +34,6 @@ ramstage-y += elog.c
 ramstage-y += fadt.c
 ramstage-y += finalize.c
 ramstage-y += gpio.c
-ramstage-y += gspi.c
 ramstage-y += graphics.c
 ramstage-y += irq.c
 ramstage-y += lockdown.c
@@ -61,7 +57,6 @@ smm-y += pmutil.c
 smm-y += smihandler.c
 smm-y += xhci.c
 
-postcar-y += gspi.c
 postcar-y += spi.c
 
 ifeq ($(CONFIG_SKYLAKE_SOC_PCH_H),y)
diff --git a/src/soc/intel/skylake/gspi.c b/src/soc/intel/skylake/gspi.c
deleted file mode 100644
index 4952dffc7d..0000000000
--- a/src/soc/intel/skylake/gspi.c
+++ /dev/null
@@ -1,14 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-or-later */
-#include <intelblocks/gspi.h>
-#include <soc/pci_devs.h>
-
-int gspi_soc_bus_to_devfn(unsigned int gspi_bus)
-{
-	switch (gspi_bus) {
-	case 0:
-		return PCH_DEVFN_GSPI0;
-	case 1:
-		return PCH_DEVFN_GSPI1;
-	}
-	return -1;
-}
diff --git a/src/soc/intel/skylake/include/soc/pci_devs.h b/src/soc/intel/skylake/include/soc/pci_devs.h
index 2f6f649542..557dc58c55 100644
--- a/src/soc/intel/skylake/include/soc/pci_devs.h
+++ b/src/soc/intel/skylake/include/soc/pci_devs.h
@@ -191,6 +191,7 @@
 #define PCI_DEVFN_UART0		PCH_DEVFN_UART0
 #define PCI_DEVFN_UART1		PCH_DEVFN_UART1
 #define PCI_DEVFN_UART2		PCH_DEVFN_UART2
+#define SOC_GSPI_DEVFN(n)	PCH_DEVFN_GSPI##n
 
 #endif
 

From 91520ab096b7468273802559ecfaf4990393f6f9 Mon Sep 17 00:00:00 2001
From: Jeremy Compostella <jeremy.compostella@intel.com>
Date: Wed, 25 Feb 2026 10:44:45 -0800
Subject: [PATCH 3479/3886] soc/intel/common/feature/spi: Add common SPI device
 function driver

Add a common driver for SPI device function to bus mapping. This
eliminates code duplication across Intel SoC platforms by providing
a generic implementation that can be configured via platform-specific
macros.

The driver provides:
- spi_soc_devfn_to_bus(): Convert device function to bus number using
  platform-defined SOC_SPI_DEVFN(n) macros
- soc_get_spi_psf_destination_id(): Optional PSF destination ID support
  for platforms that need it

Platforms must define SOC_SPI_DEVFN(n) in soc/pci_devs.h.

Platforms must define the following Kconfig:
- SOC_INTEL_SPI_DEV_MAX: Number of SPI controllers available on the
  platform.
- SOC_INTEL_COMMON_FEATURE_SPI_DEVFN_PSF: To enable PSF designation, the
  ID must be provided with SOC_INTEL_SPI_PSF_DESTINATION_ID.
- SOC_INTEL_SPI_PSF_DESTINATION_ID: (optional) PSF destination ID for
  SPI controller.

Change-Id: I07ded6e6d2156a02eef7b4fea86ac1c8fa5ff3ce
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91323
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/soc/intel/common/feature/spi/Kconfig     | 36 ++++++++++++++
 src/soc/intel/common/feature/spi/Makefile.mk |  4 ++
 src/soc/intel/common/feature/spi/spi_devfn.c | 50 ++++++++++++++++++++
 3 files changed, 90 insertions(+)
 create mode 100644 src/soc/intel/common/feature/spi/Kconfig
 create mode 100644 src/soc/intel/common/feature/spi/Makefile.mk
 create mode 100644 src/soc/intel/common/feature/spi/spi_devfn.c

diff --git a/src/soc/intel/common/feature/spi/Kconfig b/src/soc/intel/common/feature/spi/Kconfig
new file mode 100644
index 0000000000..4f09abbd03
--- /dev/null
+++ b/src/soc/intel/common/feature/spi/Kconfig
@@ -0,0 +1,36 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
+config SOC_INTEL_COMMON_FEATURE_SPI_DEVFN
+	bool
+	default n
+	depends on SOC_INTEL_COMMON_BLOCK_SPI
+	help
+	  Use common SPI device function to bus mapping. SoCs must define
+	  CONFIG_SOC_INTEL_SPI_DEV_MAX and SOC_GSPI_DEVFN(n) macro in
+	  soc/pci_devs.h.
+
+config SOC_INTEL_SPI_DEV_MAX
+	int
+	default 0
+	depends on SOC_INTEL_COMMON_FEATURE_SPI_DEVFN
+	help
+	  Number of SPI controllers available on the platform. This is used
+	  for SPI device function to bus number mapping. Platforms should
+	  override this with the actual count of SPI controllers.
+
+config SOC_INTEL_COMMON_FEATURE_SPI_DEVFN_PSF
+	bool
+	default n
+	depends on SOC_INTEL_COMMON_FEATURE_SPI_DEVFN
+	help
+	  SoC provides soc_get_spi_psf_destination_id() via common driver.
+	  Platforms must define CONFIG_SOC_INTEL_SPI_PSF_DESTINATION_ID.
+
+config SOC_INTEL_SPI_PSF_DESTINATION_ID
+	hex
+	default 0x0
+	depends on SOC_INTEL_COMMON_FEATURE_SPI_DEVFN_PSF
+	help
+	  PSF destination ID for SPI controller. This value is platform-specific
+	  and is used for PSF programming. Platforms should override this with
+	  the correct value from their hardware specification.
diff --git a/src/soc/intel/common/feature/spi/Makefile.mk b/src/soc/intel/common/feature/spi/Makefile.mk
new file mode 100644
index 0000000000..798c7ec12e
--- /dev/null
+++ b/src/soc/intel/common/feature/spi/Makefile.mk
@@ -0,0 +1,4 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
+all-$(CONFIG_SOC_INTEL_COMMON_FEATURE_SPI_DEVFN) += spi_devfn.c
+smm-$(CONFIG_SOC_INTEL_COMMON_FEATURE_SPI_DEVFN) += spi_devfn.c
diff --git a/src/soc/intel/common/feature/spi/spi_devfn.c b/src/soc/intel/common/feature/spi/spi_devfn.c
new file mode 100644
index 0000000000..eb39c5dfca
--- /dev/null
+++ b/src/soc/intel/common/feature/spi/spi_devfn.c
@@ -0,0 +1,50 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <console/console.h>
+#include <intelblocks/fast_spi.h>
+#include <intelblocks/spi.h>
+#include <soc/pci_devs.h>
+#include <stdint.h>
+
+/*
+ * Ensure the platform defines SOC_GSPI_DEVFN(n) macro to map GSPI bus numbers
+ * to their PCI device/function values. The macro should be defined in the
+ * platform's soc/pci_devs.h header.
+ */
+
+_Static_assert(CONFIG_SOC_INTEL_SPI_DEV_MAX <= 5,
+	       "CONFIG_SOC_INTEL_SPI_DEV_MAX greater than 5 is not supported.");
+
+int spi_soc_devfn_to_bus(unsigned int devfn)
+{
+	switch (devfn) {
+#if CONFIG_SOC_INTEL_SPI_DEV_MAX > 0
+	case SOC_GSPI_DEVFN(0):
+		return 1;
+#endif
+#if CONFIG_SOC_INTEL_SPI_DEV_MAX > 1
+	case SOC_GSPI_DEVFN(1):
+		return 2;
+#endif
+#if CONFIG_SOC_INTEL_SPI_DEV_MAX > 2
+	case SOC_GSPI_DEVFN(2):
+		return 3;
+#endif
+#if CONFIG_SOC_INTEL_SPI_DEV_MAX > 3
+	case SOC_GSPI_DEVFN(3):
+		return 4;
+#endif
+#if CONFIG_SOC_INTEL_SPI_DEV_MAX > 4
+	case SOC_GSPI_DEVFN(4):
+		return 5;
+#endif
+	}
+	return -1;
+}
+
+#if CONFIG(SOC_INTEL_COMMON_FEATURE_SPI_DEVFN_PSF)
+uint32_t soc_get_spi_psf_destination_id(void)
+{
+	return CONFIG_SOC_INTEL_SPI_PSF_DESTINATION_ID;
+}
+#endif

From 47f3e7e3cca3719a10bb00c1c22f5c48c1561d37 Mon Sep 17 00:00:00 2001
From: Jeremy Compostella <jeremy.compostella@intel.com>
Date: Wed, 25 Feb 2026 11:00:07 -0800
Subject: [PATCH 3480/3886] soc/intel/jasperlake: Use common SPI device
 function driver

Switch to the common SPI device function driver implementation. This
eliminates platform-specific SPI code by leveraging the common driver
with platform-specific Kconfig and macros.

This commit:
- Selects SOC_INTEL_COMMON_FEATURE_SPI_DEVFN in Kconfig
- Adds CONFIG_SOC_INTEL_SPI_DEV_MAX=3
- Removes src/soc/intel/jasperlake/spi.c
- Updates Makefile.mk to remove spi.c compilation

Note: This platform does not use PSF destination ID.
The common code uses SOC_GSPI_DEVFN(n) macro directly.

Change-Id: If42aa1f955bc0aae2698aac35dbe23b79c68bf09
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91324
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/soc/intel/jasperlake/Kconfig     |  5 +++++
 src/soc/intel/jasperlake/Makefile.mk |  1 -
 src/soc/intel/jasperlake/spi.c       | 17 -----------------
 3 files changed, 5 insertions(+), 18 deletions(-)
 delete mode 100644 src/soc/intel/jasperlake/spi.c

diff --git a/src/soc/intel/jasperlake/Kconfig b/src/soc/intel/jasperlake/Kconfig
index 7f6831e9c1..df65e73a78 100644
--- a/src/soc/intel/jasperlake/Kconfig
+++ b/src/soc/intel/jasperlake/Kconfig
@@ -57,6 +57,7 @@ config SOC_INTEL_JASPERLAKE
 	select SOC_INTEL_COMMON_BLOCK_XHCI_ELOG
 	select SOC_INTEL_COMMON_FEATURE
 	select SOC_INTEL_COMMON_FEATURE_GSPI_DEVFN
+	select SOC_INTEL_COMMON_FEATURE_SPI_DEVFN
 	select SOC_INTEL_COMMON_FEATURE_I2C_DEVFN
 	select SOC_INTEL_COMMON_FEATURE_UART_DEVICES
 	select SOC_INTEL_COMMON_FSP_RESET
@@ -215,4 +216,8 @@ config INTEL_GMA_BCLM_OFFSET
 
 config INTEL_GMA_BCLM_WIDTH
 	default 32
+
+config SOC_INTEL_SPI_DEV_MAX
+	int
+	default 3
 endif
diff --git a/src/soc/intel/jasperlake/Makefile.mk b/src/soc/intel/jasperlake/Makefile.mk
index 73765deb13..cb3ebfacd2 100644
--- a/src/soc/intel/jasperlake/Makefile.mk
+++ b/src/soc/intel/jasperlake/Makefile.mk
@@ -7,7 +7,6 @@ subdirs-y += ../../../cpu/intel/turbo
 
 # all (bootblock, verstage, romstage, postcar, ramstage)
 all-y += pmutil.c
-all-y += spi.c
 
 bootblock-y += bootblock/bootblock.c
 bootblock-y += bootblock/pch.c
diff --git a/src/soc/intel/jasperlake/spi.c b/src/soc/intel/jasperlake/spi.c
deleted file mode 100644
index 8a7ed73b47..0000000000
--- a/src/soc/intel/jasperlake/spi.c
+++ /dev/null
@@ -1,17 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-or-later */
-
-#include <intelblocks/spi.h>
-#include <soc/pci_devs.h>
-
-int spi_soc_devfn_to_bus(unsigned int devfn)
-{
-	switch (devfn) {
-	case PCH_DEVFN_GSPI0:
-		return 1;
-	case PCH_DEVFN_GSPI1:
-		return 2;
-	case PCH_DEVFN_GSPI2:
-		return 3;
-	}
-	return -1;
-}

From 0aea05411dda6441a1a050012c63acea3fa63e21 Mon Sep 17 00:00:00 2001
From: Jeremy Compostella <jeremy.compostella@intel.com>
Date: Wed, 25 Feb 2026 11:00:07 -0800
Subject: [PATCH 3481/3886] soc/intel/tigerlake: Use common SPI device function
 driver

Switch to the common SPI device function driver implementation. This
eliminates platform-specific SPI code by leveraging the common driver
with platform-specific Kconfig and macros.

This commit:
- Selects SOC_INTEL_COMMON_FEATURE_SPI_DEVFN and
  SOC_INTEL_COMMON_FEATURE_SPI_DEVFN_PSF in Kconfig
- Adds CONFIG_SOC_INTEL_SPI_DEV_MAX=3
- Adds CONFIG_SOC_INTEL_SPI_PSF_DESTINATION_ID (0x23b0 for PCH-H, 0x23a8
  default)
- Removes src/soc/intel/tigerlake/spi.c
- Updates Makefile.mk to remove spi.c compilation

The common code uses SOC_GSPI_DEVFN(n) macro directly.

Change-Id: Ib195ffcc0d46f7e95eba2d0a2c66fbcdcca615a2
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91325
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
---
 src/soc/intel/tigerlake/Kconfig     | 11 +++++++++
 src/soc/intel/tigerlake/Makefile.mk |  1 -
 src/soc/intel/tigerlake/spi.c       | 35 -----------------------------
 3 files changed, 11 insertions(+), 36 deletions(-)
 delete mode 100644 src/soc/intel/tigerlake/spi.c

diff --git a/src/soc/intel/tigerlake/Kconfig b/src/soc/intel/tigerlake/Kconfig
index 38c1e8125c..5168546661 100644
--- a/src/soc/intel/tigerlake/Kconfig
+++ b/src/soc/intel/tigerlake/Kconfig
@@ -74,6 +74,8 @@ config SOC_INTEL_TIGERLAKE
 	select SOC_INTEL_COMMON_BLOCK_XHCI_ELOG
 	select SOC_INTEL_COMMON_FEATURE
 	select SOC_INTEL_COMMON_FEATURE_GSPI_DEVFN
+	select SOC_INTEL_COMMON_FEATURE_SPI_DEVFN
+	select SOC_INTEL_COMMON_FEATURE_SPI_DEVFN_PSF
 	select SOC_INTEL_COMMON_FEATURE_I2C_DEVFN
 	select SOC_INTEL_COMMON_FEATURE_UART_DEVICES
 	select SOC_INTEL_COMMON_FSP_RESET
@@ -304,4 +306,13 @@ config INTEL_GMA_BCLM_OFFSET
 config INTEL_GMA_BCLM_WIDTH
 	default 32
 
+config SOC_INTEL_SPI_DEV_MAX
+	int
+	default 3
+
+config SOC_INTEL_SPI_PSF_DESTINATION_ID
+	hex
+	default 0x23b0 if SOC_INTEL_TIGERLAKE_PCH_H
+	default 0x23a8
+
 endif
diff --git a/src/soc/intel/tigerlake/Makefile.mk b/src/soc/intel/tigerlake/Makefile.mk
index 895395d362..074f172d38 100644
--- a/src/soc/intel/tigerlake/Makefile.mk
+++ b/src/soc/intel/tigerlake/Makefile.mk
@@ -7,7 +7,6 @@ subdirs-y += ../../../cpu/intel/turbo
 
 # all (bootblock, verstage, romstage, postcar, ramstage)
 all-y += pmutil.c
-all-y += spi.c
 
 bootblock-y += bootblock/bootblock.c
 bootblock-y += bootblock/pch.c
diff --git a/src/soc/intel/tigerlake/spi.c b/src/soc/intel/tigerlake/spi.c
deleted file mode 100644
index 47b3b33ce2..0000000000
--- a/src/soc/intel/tigerlake/spi.c
+++ /dev/null
@@ -1,35 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-or-later */
-
-/*
- * This file is created based on Intel Tiger Lake Processor PCH Datasheet
- * Document number: 575857
- * Chapter number: 7
- */
-
-#include <intelblocks/fast_spi.h>
-#include <intelblocks/spi.h>
-#include <soc/pci_devs.h>
-#include <stdint.h>
-
-#define PSF_SPI_DESTINATION_ID_H	0x23b0
-#define PSF_SPI_DESTINATION_ID		0x23a8
-
-int spi_soc_devfn_to_bus(unsigned int devfn)
-{
-	switch (devfn) {
-	case PCH_DEVFN_GSPI0:
-		return 1;
-	case PCH_DEVFN_GSPI1:
-		return 2;
-	case PCH_DEVFN_GSPI2:
-		return 3;
-	}
-	return -1;
-}
-
-uint32_t soc_get_spi_psf_destination_id(void)
-{
-	if (CONFIG(SOC_INTEL_TIGERLAKE_PCH_H))
-		return PSF_SPI_DESTINATION_ID_H;
-	return PSF_SPI_DESTINATION_ID;
-}

From 8ecff12528a33eb2388fd39bc84b4bdc6d9894e5 Mon Sep 17 00:00:00 2001
From: Jeremy Compostella <jeremy.compostella@intel.com>
Date: Wed, 25 Feb 2026 11:00:08 -0800
Subject: [PATCH 3482/3886] soc/intel/alderlake: Use common SPI device function
 driver

Switch to the common SPI device function driver implementation. This
eliminates platform-specific SPI code by leveraging the common driver
with platform-specific Kconfig and macros.

This commit:
- Selects SOC_INTEL_COMMON_FEATURE_SPI_DEVFN and
  SOC_INTEL_COMMON_FEATURE_SPI_DEVFN_PSF in Kconfig
- Adds CONFIG_SOC_INTEL_SPI_DEV_MAX=4
- Adds CONFIG_SOC_INTEL_SPI_PSF_DESTINATION_ID=0x23a8
- Removes src/soc/intel/alderlake/spi.c
- Updates Makefile.mk to remove spi.c compilation

The common code uses SOC_GSPI_DEVFN(n) macro directly.

Change-Id: I346e6c6cbe95c8608009e5f9fc53dbcff5edba4e
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91326
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/soc/intel/alderlake/Kconfig     | 10 +++++++++
 src/soc/intel/alderlake/Makefile.mk |  1 -
 src/soc/intel/alderlake/spi.c       | 33 -----------------------------
 3 files changed, 10 insertions(+), 34 deletions(-)
 delete mode 100644 src/soc/intel/alderlake/spi.c

diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig
index 4ab0b1c820..52c3d84dca 100644
--- a/src/soc/intel/alderlake/Kconfig
+++ b/src/soc/intel/alderlake/Kconfig
@@ -86,6 +86,8 @@ config SOC_INTEL_ALDERLAKE
 	select SOC_INTEL_COMMON_BLOCK_XHCI_ELOG
 	select SOC_INTEL_COMMON_FEATURE
 	select SOC_INTEL_COMMON_FEATURE_GSPI_DEVFN
+	select SOC_INTEL_COMMON_FEATURE_SPI_DEVFN
+	select SOC_INTEL_COMMON_FEATURE_SPI_DEVFN_PSF
 	select SOC_INTEL_COMMON_FEATURE_I2C_DEVFN
 	select SOC_INTEL_COMMON_FEATURE_UART_DEVICES
 	select SOC_INTEL_COMMON_FSP_RESET
@@ -574,4 +576,12 @@ config SOC_INTEL_COMMON_BLOCK_ACPI_SLP_S0_FREQ_HZ
 	help
 	  slp_s0_residency granularity in 122us ticks (i.e. ~8.2KHz).
 
+config SOC_INTEL_SPI_DEV_MAX
+	int
+	default 4
+
+config SOC_INTEL_SPI_PSF_DESTINATION_ID
+	hex
+	default 0x23a8
+
 endif
diff --git a/src/soc/intel/alderlake/Makefile.mk b/src/soc/intel/alderlake/Makefile.mk
index 35f84a5cb4..f287e91322 100644
--- a/src/soc/intel/alderlake/Makefile.mk
+++ b/src/soc/intel/alderlake/Makefile.mk
@@ -6,7 +6,6 @@ subdirs-y += ../../../cpu/intel/turbo
 
 # all (bootblock, verstage, romstage, postcar, ramstage)
 all-y += pmutil.c
-all-y += spi.c
 
 bootblock-y += bootblock/bootblock.c
 bootblock-y += bootblock/pch.c
diff --git a/src/soc/intel/alderlake/spi.c b/src/soc/intel/alderlake/spi.c
deleted file mode 100644
index 1149425101..0000000000
--- a/src/soc/intel/alderlake/spi.c
+++ /dev/null
@@ -1,33 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-or-later */
-
-/*
- * This file is created based on Intel Alder Lake Processor PCH Datasheet
- * Document number: 621483
- * Chapter number: 7
- */
-
-#include <intelblocks/fast_spi.h>
-#include <intelblocks/spi.h>
-#include <soc/pci_devs.h>
-
-#define PSF_SPI_DESTINATION_ID	0x23a8
-
-int spi_soc_devfn_to_bus(unsigned int devfn)
-{
-	switch (devfn) {
-	case PCH_DEVFN_GSPI0:
-		return 1;
-	case PCH_DEVFN_GSPI1:
-		return 2;
-	case PCH_DEVFN_GSPI2:
-		return 3;
-	case PCH_DEVFN_GSPI3:
-		return 4;
-	}
-	return -1;
-}
-
-uint32_t soc_get_spi_psf_destination_id(void)
-{
-	return PSF_SPI_DESTINATION_ID;
-}

From 4bdeb7363542b0d33d3be651a0f7b0639c87bb02 Mon Sep 17 00:00:00 2001
From: Jeremy Compostella <jeremy.compostella@intel.com>
Date: Wed, 25 Feb 2026 11:00:08 -0800
Subject: [PATCH 3483/3886] soc/intel/meteorlake: Use common SPI device
 function driver

Switch to the common SPI device function driver implementation. This
eliminates platform-specific SPI code by leveraging the common driver
with platform-specific Kconfig and macros.

This commit:
- Selects SOC_INTEL_COMMON_FEATURE_SPI_DEVFN and
  SOC_INTEL_COMMON_FEATURE_SPI_DEVFN_PSF in Kconfig
- Adds CONFIG_SOC_INTEL_SPI_DEV_MAX=3
- Adds CONFIG_SOC_INTEL_SPI_PSF_DESTINATION_ID=0x5140
- Removes src/soc/intel/meteorlake/spi.c
- Updates Makefile.mk to remove spi.c compilation

The common code uses SOC_GSPI_DEVFN(n) macro directly.

Change-Id: I6ac7bdf4c9eeaab2d0d0ecbe8cd2ea2bf7f9ea19
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91327
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
---
 src/soc/intel/meteorlake/Kconfig     | 10 ++++++++++
 src/soc/intel/meteorlake/Makefile.mk |  1 -
 src/soc/intel/meteorlake/spi.c       | 25 -------------------------
 3 files changed, 10 insertions(+), 26 deletions(-)
 delete mode 100644 src/soc/intel/meteorlake/spi.c

diff --git a/src/soc/intel/meteorlake/Kconfig b/src/soc/intel/meteorlake/Kconfig
index 1d341d1484..566bc05bda 100644
--- a/src/soc/intel/meteorlake/Kconfig
+++ b/src/soc/intel/meteorlake/Kconfig
@@ -88,6 +88,8 @@ config SOC_INTEL_METEORLAKE
 	select SOC_INTEL_COMMON_BLOCK_XHCI_ELOG
 	select SOC_INTEL_COMMON_FEATURE
 	select SOC_INTEL_COMMON_FEATURE_GSPI_DEVFN
+	select SOC_INTEL_COMMON_FEATURE_SPI_DEVFN
+	select SOC_INTEL_COMMON_FEATURE_SPI_DEVFN_PSF
 	select SOC_INTEL_COMMON_FEATURE_I2C_DEVFN
 	select SOC_INTEL_COMMON_FEATURE_UART_DEVICES
 	select SOC_INTEL_COMMON_BASECODE
@@ -478,4 +480,12 @@ config SKIP_SEND_CONNECT_TOPOLOGY_CMD
 config TME_KEY_REGENERATION_ON_WARM_BOOT
 	default y if INTEL_TME
 
+config SOC_INTEL_SPI_DEV_MAX
+	int
+	default 3
+
+config SOC_INTEL_SPI_PSF_DESTINATION_ID
+	hex
+	default 0x5140
+
 endif
diff --git a/src/soc/intel/meteorlake/Makefile.mk b/src/soc/intel/meteorlake/Makefile.mk
index 60044f376f..d2192c0483 100644
--- a/src/soc/intel/meteorlake/Makefile.mk
+++ b/src/soc/intel/meteorlake/Makefile.mk
@@ -7,7 +7,6 @@ subdirs-y += ../../../cpu/intel/turbo
 
 # all (bootblock, verstage, romstage, postcar, ramstage)
 all-y += pmutil.c
-all-y += spi.c
 all-y += gpio.c
 
 bootblock-y += bootblock/bootblock.c
diff --git a/src/soc/intel/meteorlake/spi.c b/src/soc/intel/meteorlake/spi.c
deleted file mode 100644
index f7d751f98e..0000000000
--- a/src/soc/intel/meteorlake/spi.c
+++ /dev/null
@@ -1,25 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-or-later */
-
-#include <intelblocks/fast_spi.h>
-#include <intelblocks/spi.h>
-#include <soc/pci_devs.h>
-
-#define PSF_SPI_DESTINATION_ID  0x5140
-
-int spi_soc_devfn_to_bus(unsigned int devfn)
-{
-	switch (devfn) {
-	case PCI_DEVFN_GSPI0:
-		return 1;
-	case PCI_DEVFN_GSPI1:
-		return 2;
-	case PCI_DEVFN_GSPI2:
-		return 3;
-	}
-	return -1;
-}
-
-uint32_t soc_get_spi_psf_destination_id(void)
-{
-	return PSF_SPI_DESTINATION_ID;
-}

From 56ede20f103fd30307447f66c26e630382e2205f Mon Sep 17 00:00:00 2001
From: Jeremy Compostella <jeremy.compostella@intel.com>
Date: Wed, 25 Feb 2026 11:00:08 -0800
Subject: [PATCH 3484/3886] soc/intel/pantherlake: Use common SPI device
 function driver

Switch to the common SPI device function driver implementation. This
eliminates platform-specific SPI code by leveraging the common driver
with platform-specific Kconfig and macros.

This commit:
- Selects SOC_INTEL_COMMON_FEATURE_SPI_DEVFN and
  SOC_INTEL_COMMON_FEATURE_SPI_DEVFN_PSF in Kconfig
- Adds CONFIG_SOC_INTEL_SPI_DEV_MAX=3
- Adds CONFIG_SOC_INTEL_SPI_PSF_DESTINATION_ID=0x5140
- Removes src/soc/intel/pantherlake/spi.c
- Updates Makefile.mk to remove spi.c compilation

The common code uses SOC_GSPI_DEVFN(n) macro directly.

TEST=Panther Lake Fatcat OS boots properly

Change-Id: Id7462deeb80c1efe32accf0ab7fc9fa68494ddfd
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91328
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/soc/intel/pantherlake/Kconfig     | 10 ++++++++++
 src/soc/intel/pantherlake/Makefile.mk |  1 -
 src/soc/intel/pantherlake/spi.c       | 25 -------------------------
 3 files changed, 10 insertions(+), 26 deletions(-)
 delete mode 100644 src/soc/intel/pantherlake/spi.c

diff --git a/src/soc/intel/pantherlake/Kconfig b/src/soc/intel/pantherlake/Kconfig
index 133a0b8684..33a592cb07 100644
--- a/src/soc/intel/pantherlake/Kconfig
+++ b/src/soc/intel/pantherlake/Kconfig
@@ -98,6 +98,8 @@ config SOC_INTEL_PANTHERLAKE_BASE
 	select SOC_INTEL_COMMON_BLOCK_XHCI_ELOG
 	select SOC_INTEL_COMMON_FEATURE
 	select SOC_INTEL_COMMON_FEATURE_GSPI_DEVFN
+	select SOC_INTEL_COMMON_FEATURE_SPI_DEVFN
+	select SOC_INTEL_COMMON_FEATURE_SPI_DEVFN_PSF
 	select SOC_INTEL_COMMON_FEATURE_I2C_DEVFN
 	select SOC_INTEL_COMMON_FEATURE_UART_DEVICES
 	select SOC_INTEL_COMMON_FSP_RESET
@@ -479,4 +481,12 @@ config RAMSTAGE_CBFS_CACHE_SIZE
 config CBFS_CACHE_ALIGN
 	default 1024
 
+config SOC_INTEL_SPI_DEV_MAX
+	int
+	default 3
+
+config SOC_INTEL_SPI_PSF_DESTINATION_ID
+	hex
+	default 0x5140
+
 endif
diff --git a/src/soc/intel/pantherlake/Makefile.mk b/src/soc/intel/pantherlake/Makefile.mk
index 5f956db228..857e7ab648 100644
--- a/src/soc/intel/pantherlake/Makefile.mk
+++ b/src/soc/intel/pantherlake/Makefile.mk
@@ -8,7 +8,6 @@ subdirs-y += ../../../cpu/intel/turbo
 
 # all (bootblock, verstage, romstage, postcar, ramstage)
 all-y += pmutil.c
-all-y += spi.c
 all-y += gpio.c
 
 bootblock-y += bootblock/bootblock.c
diff --git a/src/soc/intel/pantherlake/spi.c b/src/soc/intel/pantherlake/spi.c
deleted file mode 100644
index f7d751f98e..0000000000
--- a/src/soc/intel/pantherlake/spi.c
+++ /dev/null
@@ -1,25 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-or-later */
-
-#include <intelblocks/fast_spi.h>
-#include <intelblocks/spi.h>
-#include <soc/pci_devs.h>
-
-#define PSF_SPI_DESTINATION_ID  0x5140
-
-int spi_soc_devfn_to_bus(unsigned int devfn)
-{
-	switch (devfn) {
-	case PCI_DEVFN_GSPI0:
-		return 1;
-	case PCI_DEVFN_GSPI1:
-		return 2;
-	case PCI_DEVFN_GSPI2:
-		return 3;
-	}
-	return -1;
-}
-
-uint32_t soc_get_spi_psf_destination_id(void)
-{
-	return PSF_SPI_DESTINATION_ID;
-}

From cf5d6f1c885a5508c85bda1f574aff71de0cb58e Mon Sep 17 00:00:00 2001
From: Jeremy Compostella <jeremy.compostella@intel.com>
Date: Wed, 18 Feb 2026 14:49:51 -0800
Subject: [PATCH 3485/3886] soc/intel/common/block/gspi: Simplify Makefile
 using all-$()

Replace individual stage-specific lines with all-$() for each file.
This simplifies the Makefile from 6 lines to 2 lines while maintaining
identical functionality.

The all-$() variable automatically includes the file in all build stages
(bootblock, verstage, romstage, postcar, ramstage, smm), which is
exactly what the original code was doing manually for each stage.

Change-Id: Ie89ba86a545c548fcc4ad0eb48a5cbb33733b541
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91358
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
---
 src/soc/intel/common/block/gspi/Makefile.mk | 6 +-----
 1 file changed, 1 insertion(+), 5 deletions(-)

diff --git a/src/soc/intel/common/block/gspi/Makefile.mk b/src/soc/intel/common/block/gspi/Makefile.mk
index a820866ceb..5b52f2146f 100644
--- a/src/soc/intel/common/block/gspi/Makefile.mk
+++ b/src/soc/intel/common/block/gspi/Makefile.mk
@@ -1,6 +1,2 @@
 ## SPDX-License-Identifier: GPL-2.0-only
-bootblock-$(CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI) += gspi.c
-romstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI) += gspi.c
-ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI) += gspi.c
-verstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI) += gspi.c
-postcar-$(CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI) += gspi.c
+all-$(CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI) += gspi.c

From f4825e5c12fe1129c7862a61b91bb7e60f1e9b45 Mon Sep 17 00:00:00 2001
From: Patrick Rudolph <patrick.rudolph@9elements.com>
Date: Thu, 5 Jun 2025 09:12:24 +0200
Subject: [PATCH 3486/3886] soc/amd/common: Add I3C driver

Add an I3C driver that allows to use the I3C HW from the OS.
It does:
- Power on/off the I3C HW
- Configures the IOMUX

Add the SoC specific AOAC devices and GPIO pins to reconfigure
the GPIO for I3C HW.

New log messages are seen in coreboot:
[DEBUG]  MMIO: fedd2000 disabled

TEST: The I3C driver loads on amd/glinda using Ubuntu 25.04.

Change-Id: Ibca20e2a4f0cb0e6006cfa47fd4addbe27504645
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87960
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
---
 src/soc/amd/common/block/i2c/i3c.c            | 86 ++++++++++++++++---
 .../amd/common/block/include/amdblocks/i2c.h  |  1 +
 src/soc/amd/genoa_poc/i3c.c                   |  9 +-
 src/soc/amd/glinda/i3c.c                      |  9 +-
 src/soc/amd/mendocino/i3c.c                   |  9 +-
 src/soc/amd/phoenix/i3c.c                     |  9 +-
 src/soc/amd/turin_poc/i3c.c                   |  9 +-
 7 files changed, 101 insertions(+), 31 deletions(-)

diff --git a/src/soc/amd/common/block/i2c/i3c.c b/src/soc/amd/common/block/i2c/i3c.c
index 43eae71b67..4fbe6ae37b 100644
--- a/src/soc/amd/common/block/i2c/i3c.c
+++ b/src/soc/amd/common/block/i2c/i3c.c
@@ -1,28 +1,57 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
-
+#include <device/mmio.h>
 #include <acpi/acpigen.h>
+#include <amdblocks/aoac.h>
 #include <amdblocks/i2c.h>
 #include <console/console.h>
 #include <device/device.h>
 #include <types.h>
 
-#if CONFIG(HAVE_ACPI_TABLES)
-static const char *i3c_acpi_name(const struct device *dev)
+static int get_i3c_bus_for_dev(const struct device *dev,
+			       const struct soc_i3c_ctrlr_info *ctrlr,
+			       const size_t num_ctrlrs)
 {
-	size_t i;
-	size_t num_ctrlrs;
-	const struct soc_i3c_ctrlr_info *ctrlr = soc_get_i3c_ctrlr_info(&num_ctrlrs);
+	if (!dev || !ctrlr)
+		return -1;
 
 	if (!(uintptr_t)dev->path.mmio.addr) {
 		printk(BIOS_ERR, "NULL MMIO address at %s\n", __func__);
-		return NULL;
+		return -1;
 	}
 
-	for (i = 0; i < num_ctrlrs; i++) {
-		if ((uintptr_t)dev->path.mmio.addr == ctrlr[i].bar)
-			return ctrlr[i].acpi_name;
+	for (int i = 0; i < num_ctrlrs; i++) {
+		if (dev->path.mmio.addr != ctrlr[i].bar)
+			continue;
+		return i;
 	}
-	printk(BIOS_ERR, "%s: Could not find %lu\n", __func__, (uintptr_t)dev->path.mmio.addr);
+	printk(BIOS_ERR, "%s: Could not find i3c bus for %s\n", __func__, dev_path(dev));
+
+	return -1;
+}
+
+static const struct soc_i3c_ctrlr_info *
+get_i3c_info_for_dev(const struct device *dev)
+{
+	size_t num_ctrlrs;
+	const struct soc_i3c_ctrlr_info *ctrlr = soc_get_i3c_ctrlr_info(&num_ctrlrs);
+	const int bus = get_i3c_bus_for_dev(dev, ctrlr, num_ctrlrs);
+
+	if (ctrlr && bus >= 0 && bus < num_ctrlrs)
+		return &ctrlr[bus];
+
+	printk(BIOS_ERR, "%s: Could not find soc_i3c_ctrlr_info for %s\n", __func__, dev_path(dev));
+
+	return NULL;
+}
+
+#if CONFIG(HAVE_ACPI_TABLES)
+static const char *i3c_acpi_name(const struct device *dev)
+{
+	const struct soc_i3c_ctrlr_info *info = get_i3c_info_for_dev(dev);
+	if (info)
+		return info->acpi_name;
+
+	printk(BIOS_ERR, "%s: Could not find soc_i3c_ctrlr_info for %s\n", __func__, dev_path(dev));
 	return NULL;
 }
 
@@ -34,12 +63,47 @@ static void i3c_acpi_fill_ssdt(const struct device *dev)
 }
 #endif
 
+/* Even though this is called enable, it gets called for both enabled and disabled devices. */
+static void i3c_enable(struct device *dev)
+{
+	const struct soc_i3c_ctrlr_info *info = get_i3c_info_for_dev(dev);
+	if (!info)
+		return;
+
+	if (dev->enabled) {
+		power_on_aoac_device(info->aoac_device);
+		wait_for_aoac_enabled(info->aoac_device);
+	} else {
+		power_off_aoac_device(info->aoac_device);
+	}
+}
+
+static void i3c_init(struct device *dev)
+{
+	size_t num_ctrlrs, num_buses;
+	const struct soc_i3c_ctrlr_info *ctrlr = soc_get_i3c_ctrlr_info(&num_ctrlrs);
+	const int bus = get_i3c_bus_for_dev(dev, ctrlr, num_ctrlrs);
+	if (bus < 0)
+		return;
+
+	const struct dw_i2c_bus_config *cfg = soc_get_i2c_bus_config(&num_buses);
+
+	if (cfg)
+		soc_i2c_misc_init(bus, cfg);
+}
+
 static void i3c_read_resources(struct device *dev)
 {
 	mmio_range(dev, 0, dev->path.mmio.addr, 4 * KiB);
 }
 
+/*
+ * Currently there's no I3C driver, thus the I3C hardware cannot be used pre ramstage.
+ * It's sufficient to power switch the I3C controllers in the enable method.
+ */
 struct device_operations soc_amd_i3c_mmio_ops = {
+	.enable = i3c_enable,
+	.init = i3c_init,
 	.read_resources = i3c_read_resources,
 	.set_resources = noop_set_resources,
 #if CONFIG(HAVE_ACPI_TABLES)
diff --git a/src/soc/amd/common/block/include/amdblocks/i2c.h b/src/soc/amd/common/block/include/amdblocks/i2c.h
index fc1a03217a..553561b7fc 100644
--- a/src/soc/amd/common/block/include/amdblocks/i2c.h
+++ b/src/soc/amd/common/block/include/amdblocks/i2c.h
@@ -74,6 +74,7 @@ struct i2c_pad_control {
 struct soc_i3c_ctrlr_info {
 	uintptr_t bar;
 	const char *acpi_name;
+	unsigned int aoac_device;
 };
 
 void fch_i2c_pad_init(unsigned int bus,
diff --git a/src/soc/amd/genoa_poc/i3c.c b/src/soc/amd/genoa_poc/i3c.c
index e694623177..0e041942b6 100644
--- a/src/soc/amd/genoa_poc/i3c.c
+++ b/src/soc/amd/genoa_poc/i3c.c
@@ -1,14 +1,15 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
 #include <amdblocks/i2c.h>
+#include <soc/aoac_defs.h>
 #include <soc/iomap.h>
 #include <types.h>
 
 static const struct soc_i3c_ctrlr_info i3c_ctrlr[I3C_CTRLR_COUNT] = {
-	{ APU_I3C0_BASE, "I3C0" },
-	{ APU_I3C1_BASE, "I3C1" },
-	{ APU_I3C2_BASE, "I3C2" },
-	{ APU_I3C3_BASE, "I3C3" }
+	{ APU_I3C0_BASE, "I3C0", FCH_AOAC_DEV_I3C0},
+	{ APU_I3C1_BASE, "I3C1", FCH_AOAC_DEV_I3C1},
+	{ APU_I3C2_BASE, "I3C2", FCH_AOAC_DEV_I3C2},
+	{ APU_I3C3_BASE, "I3C3", FCH_AOAC_DEV_I3C3}
 };
 
 const struct soc_i3c_ctrlr_info *soc_get_i3c_ctrlr_info(size_t *num_ctrlrs)
diff --git a/src/soc/amd/glinda/i3c.c b/src/soc/amd/glinda/i3c.c
index e694623177..0e041942b6 100644
--- a/src/soc/amd/glinda/i3c.c
+++ b/src/soc/amd/glinda/i3c.c
@@ -1,14 +1,15 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
 #include <amdblocks/i2c.h>
+#include <soc/aoac_defs.h>
 #include <soc/iomap.h>
 #include <types.h>
 
 static const struct soc_i3c_ctrlr_info i3c_ctrlr[I3C_CTRLR_COUNT] = {
-	{ APU_I3C0_BASE, "I3C0" },
-	{ APU_I3C1_BASE, "I3C1" },
-	{ APU_I3C2_BASE, "I3C2" },
-	{ APU_I3C3_BASE, "I3C3" }
+	{ APU_I3C0_BASE, "I3C0", FCH_AOAC_DEV_I3C0},
+	{ APU_I3C1_BASE, "I3C1", FCH_AOAC_DEV_I3C1},
+	{ APU_I3C2_BASE, "I3C2", FCH_AOAC_DEV_I3C2},
+	{ APU_I3C3_BASE, "I3C3", FCH_AOAC_DEV_I3C3}
 };
 
 const struct soc_i3c_ctrlr_info *soc_get_i3c_ctrlr_info(size_t *num_ctrlrs)
diff --git a/src/soc/amd/mendocino/i3c.c b/src/soc/amd/mendocino/i3c.c
index e694623177..0e041942b6 100644
--- a/src/soc/amd/mendocino/i3c.c
+++ b/src/soc/amd/mendocino/i3c.c
@@ -1,14 +1,15 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
 #include <amdblocks/i2c.h>
+#include <soc/aoac_defs.h>
 #include <soc/iomap.h>
 #include <types.h>
 
 static const struct soc_i3c_ctrlr_info i3c_ctrlr[I3C_CTRLR_COUNT] = {
-	{ APU_I3C0_BASE, "I3C0" },
-	{ APU_I3C1_BASE, "I3C1" },
-	{ APU_I3C2_BASE, "I3C2" },
-	{ APU_I3C3_BASE, "I3C3" }
+	{ APU_I3C0_BASE, "I3C0", FCH_AOAC_DEV_I3C0},
+	{ APU_I3C1_BASE, "I3C1", FCH_AOAC_DEV_I3C1},
+	{ APU_I3C2_BASE, "I3C2", FCH_AOAC_DEV_I3C2},
+	{ APU_I3C3_BASE, "I3C3", FCH_AOAC_DEV_I3C3}
 };
 
 const struct soc_i3c_ctrlr_info *soc_get_i3c_ctrlr_info(size_t *num_ctrlrs)
diff --git a/src/soc/amd/phoenix/i3c.c b/src/soc/amd/phoenix/i3c.c
index e694623177..0e041942b6 100644
--- a/src/soc/amd/phoenix/i3c.c
+++ b/src/soc/amd/phoenix/i3c.c
@@ -1,14 +1,15 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
 #include <amdblocks/i2c.h>
+#include <soc/aoac_defs.h>
 #include <soc/iomap.h>
 #include <types.h>
 
 static const struct soc_i3c_ctrlr_info i3c_ctrlr[I3C_CTRLR_COUNT] = {
-	{ APU_I3C0_BASE, "I3C0" },
-	{ APU_I3C1_BASE, "I3C1" },
-	{ APU_I3C2_BASE, "I3C2" },
-	{ APU_I3C3_BASE, "I3C3" }
+	{ APU_I3C0_BASE, "I3C0", FCH_AOAC_DEV_I3C0},
+	{ APU_I3C1_BASE, "I3C1", FCH_AOAC_DEV_I3C1},
+	{ APU_I3C2_BASE, "I3C2", FCH_AOAC_DEV_I3C2},
+	{ APU_I3C3_BASE, "I3C3", FCH_AOAC_DEV_I3C3}
 };
 
 const struct soc_i3c_ctrlr_info *soc_get_i3c_ctrlr_info(size_t *num_ctrlrs)
diff --git a/src/soc/amd/turin_poc/i3c.c b/src/soc/amd/turin_poc/i3c.c
index e694623177..0e041942b6 100644
--- a/src/soc/amd/turin_poc/i3c.c
+++ b/src/soc/amd/turin_poc/i3c.c
@@ -1,14 +1,15 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
 #include <amdblocks/i2c.h>
+#include <soc/aoac_defs.h>
 #include <soc/iomap.h>
 #include <types.h>
 
 static const struct soc_i3c_ctrlr_info i3c_ctrlr[I3C_CTRLR_COUNT] = {
-	{ APU_I3C0_BASE, "I3C0" },
-	{ APU_I3C1_BASE, "I3C1" },
-	{ APU_I3C2_BASE, "I3C2" },
-	{ APU_I3C3_BASE, "I3C3" }
+	{ APU_I3C0_BASE, "I3C0", FCH_AOAC_DEV_I3C0},
+	{ APU_I3C1_BASE, "I3C1", FCH_AOAC_DEV_I3C1},
+	{ APU_I3C2_BASE, "I3C2", FCH_AOAC_DEV_I3C2},
+	{ APU_I3C3_BASE, "I3C3", FCH_AOAC_DEV_I3C3}
 };
 
 const struct soc_i3c_ctrlr_info *soc_get_i3c_ctrlr_info(size_t *num_ctrlrs)

From b1e8f87b301da9d7a1c43bb78006aba8856ebb0a Mon Sep 17 00:00:00 2001
From: Jarried Lin <jarried.lin@mediatek.corp-partner.google.com>
Date: Mon, 9 Feb 2026 13:26:00 +0800
Subject: [PATCH 3487/3886] mb/google/rauru: Enable MEDIATEK_WDT_RESET_BY_SW

For MT8196p, watchdog external reset is enabled by kernel configuration,
and EC ignores the reset signal AP_PMIC_WDTRST_L. Therefore, enable
MEDIATEK_WDT_RESET_BY_SW to allow triggering the secondary watchdog
reset via software instead of watchdog hardware.

BUG=b:481854714
TEST=cbmem logs preserved on WDT timeout

Change-Id: Ib6b1ddbe28b0cd2aac2043f18dcd15caf4cac37a
Signed-off-by: Jarried Lin <jarried.lin@mediatek.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91420
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/google/rauru/Kconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/src/mainboard/google/rauru/Kconfig b/src/mainboard/google/rauru/Kconfig
index 486e273874..c13149aefe 100644
--- a/src/mainboard/google/rauru/Kconfig
+++ b/src/mainboard/google/rauru/Kconfig
@@ -40,6 +40,7 @@ config BOARD_SPECIFIC_OPTIONS
 	select FW_CONFIG_SOURCE_CHROMEEC_CBI
 	select RTC
 	select MIPI_PANEL_BOE_NS130069_M00 if BOARD_GOOGLE_SAPPHIRE
+	select MEDIATEK_WDT_RESET_BY_SW if BOARD_GOOGLE_SAPPHIRE
 
 config MAINBOARD_DIR
 	string

From 7b205808e464a369ddffb49cb15cd2f13e59862d Mon Sep 17 00:00:00 2001
From: Jarried Lin <jarried.lin@mediatek.corp-partner.google.com>
Date: Mon, 9 Feb 2026 13:24:20 +0800
Subject: [PATCH 3488/3886] mb/google/rauru: Disable
 CHROMEOS_USE_EC_WATCHDOG_FLAG

Now that we use the WATCHDOG_TOMBSTONE section to store the watchdog
event magic, there is no need to ask EC for the last reset reason. In
fact, with MEDIATEK_WDT_RESET_BY_SW enabled, EC doesn't even record the
watchdog reset reason.

Enable CHROMEOS_USE_EC_WATCHDOG_FLAG only if MEDIATEK_WDT_RESET_BY_SW is
disabled.

BUG=b:481854714
TEST= After triggering WDT timeout, the following log can be observed:
[NOTE ]  coreboot-coreboot-unknown.9999.782bb84 Mon Feb 23 06:42:21 UTC 2026 aarch64 bootblock starting (log level: 8)
[DEBUG]  ARM64: Exception handlers installed.
[DEBUG]  ARM64: Testing exception
[DEBUG]  ARM64: Done test exception
[DEBUG]  [booker_init] AP hash rule: 0xbe00
[INFO ]  mtk_cksys_init = 0x1
[INFO ]  WDT: Status = 0x20000
[INFO ]  WDT: Last reset was other reset type: 0x00020000
[INFO ]  mtk_wdt_swreset() called!
[INFO ]  board_reset() called!

And "elogtool list" contained "Hardware watchdog reset".

Change-Id: I44a940d88948897e6727fad5c87f364e3ba9ac61
Signed-off-by: Jarried Lin <jarried.lin@mediatek.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91421
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/google/rauru/Kconfig | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/mainboard/google/rauru/Kconfig b/src/mainboard/google/rauru/Kconfig
index c13149aefe..dbbfcfb360 100644
--- a/src/mainboard/google/rauru/Kconfig
+++ b/src/mainboard/google/rauru/Kconfig
@@ -26,7 +26,7 @@ config BOARD_SPECIFIC_OPTIONS
 	select SPI_FLASH_INCLUDE_ALL_DRIVERS
 	select MAINBOARD_HAS_NATIVE_VGA_INIT
 	select HAVE_LINEAR_FRAMEBUFFER
-	select CHROMEOS_USE_EC_WATCHDOG_FLAG if CHROMEOS
+	select CHROMEOS_USE_EC_WATCHDOG_FLAG if CHROMEOS && !MEDIATEK_WDT_RESET_BY_SW
 	select EC_GOOGLE_CHROMEEC
 	select EC_GOOGLE_CHROMEEC_BOARDID
 	select EC_GOOGLE_CHROMEEC_FW_CONFIG_FROM_UFSC if BOARD_GOOGLE_SAPPHIRE

From 098a5cf16e5a972216833fedd57d594185668b15 Mon Sep 17 00:00:00 2001
From: Sowmya V <v.sowmya@intel.com>
Date: Tue, 17 Feb 2026 17:06:57 +0530
Subject: [PATCH 3489/3886] mb/google/ocelot: Configure CDCLK frequency for
 display

Configure the Core Display Clock (CDCLK) frequency selection by setting
the 'vga_cd_clk_freq_sel' register to CD_CLK_461MHZ in the ocelot
baseboard devicetree. This ensures the display engine operates at the
required frequency for the panel to meet the hardware configuration.

TEST=Build and boot ocelot, verify display initialization.

Change-Id: Ic2f8fccc4391febd342f8f140014c5f3e09472c4
Signed-off-by: Sowmya V <v.sowmya@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91312
Reviewed-by: Avi Uday <aviuday@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 .../google/ocelot/variants/baseboard/ocelot/devicetree.cb        | 1 +
 1 file changed, 1 insertion(+)

diff --git a/src/mainboard/google/ocelot/variants/baseboard/ocelot/devicetree.cb b/src/mainboard/google/ocelot/variants/baseboard/ocelot/devicetree.cb
index 23b276e15a..b53380c2ee 100644
--- a/src/mainboard/google/ocelot/variants/baseboard/ocelot/devicetree.cb
+++ b/src/mainboard/google/ocelot/variants/baseboard/ocelot/devicetree.cb
@@ -95,6 +95,7 @@ chip soc/intel/pantherlake
 	register "pch_hda_idisp_codec_enable" = "true"
 
 	register "disable_progress_bar" = "true"
+	register "vga_cd_clk_freq_sel" = "CD_CLK_461MHZ"
 
 	device domain 0 on
 		device ref dtt on end

From 08f2f3a21bcbb3ea32ad25fa3af788ebbf447b6d Mon Sep 17 00:00:00 2001
From: Angel Pons <th3fanbus@gmail.com>
Date: Wed, 10 Sep 2025 16:30:34 +0200
Subject: [PATCH 3490/3886] Haswell NRI: Implement 1D margin training

Implement an algorithm that performs a simple 1D margin training. This
algorithm is generic, i.e. it can be used with multiple margin params.
Use this algorithm to train three margin parameters: RdT, WrT and RdV.

This algorithm also does per-bit calibration, but only for RdT and WrT
since Haswell does not have per-rank per-bit RdV (c.f. `RX_OFFSET_VDQ`
register). Still, implement support in `change_margin()` for all three
types of per-bit margins (WrTBit, RdTBit, RdVBit) for completeness.

Tested on Asrock Z97 Extreme6 with 2 DIMMs per channel (1R + 2R):
- NRI finishes successfully, board still boots to Arch Linux.
- Both fast training as well as S3 suspend/resume still work.

Change-Id: I382cea8e230aee46a0dc66248f1e678d8a9a0090
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89314
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 .../intel/haswell/native_raminit/Makefile.mk  |   1 +
 .../haswell/native_raminit/change_margin.c    | 122 ++++++-
 .../haswell/native_raminit/raminit_main.c     |   3 +
 .../haswell/native_raminit/raminit_native.h   |  59 ++++
 .../intel/haswell/native_raminit/reut.c       |   9 +
 .../haswell/native_raminit/train_1d_margins.c | 305 ++++++++++++++++++
 .../intel/haswell/registers/mchbar.h          |   5 +
 7 files changed, 496 insertions(+), 8 deletions(-)
 create mode 100644 src/northbridge/intel/haswell/native_raminit/train_1d_margins.c

diff --git a/src/northbridge/intel/haswell/native_raminit/Makefile.mk b/src/northbridge/intel/haswell/native_raminit/Makefile.mk
index 4bd668a2d6..c7a5f4ba5a 100644
--- a/src/northbridge/intel/haswell/native_raminit/Makefile.mk
+++ b/src/northbridge/intel/haswell/native_raminit/Makefile.mk
@@ -18,6 +18,7 @@ romstage-y += setup_wdb.c
 romstage-y += spd_bitmunching.c
 romstage-y += testing_io.c
 romstage-y += timings_refresh.c
+romstage-y += train_1d_margins.c
 romstage-y += train_jedec_write_leveling.c
 romstage-y += train_read_mpr.c
 romstage-y += train_receive_enable.c
diff --git a/src/northbridge/intel/haswell/native_raminit/change_margin.c b/src/northbridge/intel/haswell/native_raminit/change_margin.c
index 517ddc23a6..2ef8712bf8 100644
--- a/src/northbridge/intel/haswell/native_raminit/change_margin.c
+++ b/src/northbridge/intel/haswell/native_raminit/change_margin.c
@@ -200,18 +200,109 @@ static void update_data_offset_train(
 	}
 }
 
-static uint32_t get_max_margin(const enum margin_parameter param)
+static uint16_t get_per_bit_reg(
+	const enum margin_parameter param,
+	const bool multicast,
+	const uint8_t channel,
+	const uint8_t rank,
+	const uint8_t byte)
+{
+	switch (param) {
+	case RdTBit:
+		if (multicast) {
+			return DDR_DATA_RX_PER_BIT_RANK(rank);
+		} else {
+			return RX_PER_BIT(channel, rank, byte);
+		}
+	case WrTBit:
+		if (multicast) {
+			return DDR_DATA_TX_PER_BIT_RANK(rank);
+		} else {
+			return TX_PER_BIT(channel, rank, byte);
+		}
+	case RdVBit:
+		/** TODO: Broadwell has per-rank RX_OFFSET_VDQ registers **/
+		if (multicast) {
+			return DDR_DATA_RX_OFFSET_VDQ;
+		} else {
+			return RX_OFFSET_VDQ(channel, byte);
+		}
+	default:
+		die("%s: Invalid margin parameter %d\n", __func__, param);
+	}
+}
+
+static void update_per_bit_margin(
+	struct sysinfo *ctrl,
+	const enum margin_parameter param,
+	const uint8_t channel,
+	const uint8_t rank,
+	const uint8_t byte,
+	const uint32_t value)
+{
+	for (uint8_t bit = 0; bit < NUM_BITS; bit++) {
+		const uint8_t v_bit = value >> (4 * bit) & 0xf;
+		switch (param) {
+		case RdTBit:
+			ctrl->rxdqpb[channel][rank][byte][bit].center = v_bit;
+			break;
+		case WrTBit:
+			ctrl->txdqpb[channel][rank][byte][bit].center = v_bit;
+			break;
+		case RdVBit:
+			ctrl->rxdqvrefpb[channel][rank][byte][bit].center = v_bit;
+			break;
+		default:
+			break;
+		}
+	}
+}
+
+static void change_per_bit_margin(
+	struct sysinfo *ctrl,
+	const enum margin_parameter param,
+	const bool multicast,
+	const uint8_t in_channel,
+	const uint8_t rank,
+	const uint8_t in_byte,
+	const bool update_ctrl,
+	const uint32_t value,
+	const enum regfile_mode regfile)
+{
+	const bool is_rd = param == RdTBit || param == RdVBit;
+	const bool is_wr = param == WrTBit;
+	const uint16_t reg = get_per_bit_reg(param, multicast, in_channel, rank, in_byte);
+	mchbar_write32(reg, value);
+	if (multicast) {
+		for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
+			if (!does_ch_exist(ctrl, channel))
+				continue;
+
+			download_regfile(ctrl, channel, true, rank, regfile, 0, is_rd, is_wr);
+			if (!update_ctrl)
+				continue;
+
+			for (uint8_t byte = 0; byte < ctrl->lanes; byte++) {
+				update_per_bit_margin(ctrl, param, channel, rank, byte, value);
+			}
+		}
+	} else {
+		download_regfile(ctrl, in_channel, false, rank, regfile, in_byte, is_rd, is_wr);
+		if (!update_ctrl)
+			return;
+
+		update_per_bit_margin(ctrl, param, in_channel, rank, in_byte, value);
+	}
+}
+
+uint32_t get_max_margin_for_param(const enum margin_parameter param)
 {
 	switch (param) {
-	case RcvEna:
-	case RdT:
-	case WrT:
-	case WrDqsT:
-		return MAX_POSSIBLE_TIME;
 	case RdV:
+	case WrV:
 		return MAX_POSSIBLE_VREF;
 	default:
-		die("%s: Invalid margin parameter %u\n", __func__, param);
+		return MAX_POSSIBLE_TIME;
 	}
 }
 
@@ -233,7 +324,22 @@ void change_margin(
 	if (!en_multicast && !does_ch_exist(ctrl, channel))
 		die("%s: Tried to change margin of empty channel %u\n", __func__, channel);
 
-	const uint32_t max_value = get_max_margin(param);
+	/* Per-bit margins are handled differently */
+	if (param == WrTBit || param == RdTBit || param == RdVBit) {
+		change_per_bit_margin(
+			ctrl,
+			param,
+			en_multicast,
+			channel,
+			rank,
+			byte,
+			update_ctrl,
+			(uint32_t)value0,
+			regfile);
+		return;
+	}
+
+	const uint32_t max_value = get_max_margin_for_param(param);
 	const int32_t v0 = clamp_s32(-max_value, value0, max_value);
 
 	union ddr_data_offset_train_reg ddr_data_offset_train = {
diff --git a/src/northbridge/intel/haswell/native_raminit/raminit_main.c b/src/northbridge/intel/haswell/native_raminit/raminit_main.c
index 84db33ebdf..91c1920725 100644
--- a/src/northbridge/intel/haswell/native_raminit/raminit_main.c
+++ b/src/northbridge/intel/haswell/native_raminit/raminit_main.c
@@ -129,6 +129,9 @@ static const struct task_entry cold_boot[] = {
 	{ train_receive_enable,                                   true, "RCVET",      },
 	{ train_read_mpr,                                         true, "RDMPRT",     },
 	{ train_jedec_write_leveling,                             true, "JWRL",       },
+	{ train_write_timing_centering,                           true, "WRTC1D",     },
+	{ train_read_timing_centering,                            true, "RDTC1D",     },
+	{ train_read_voltage_centering,                           true, "RDVC1D",     },
 	{ optimise_comp,                                          true, "OPTCOMP",    },
 	{ post_training,                                          true, "POSTTRAIN",  },
 	{ activate_mc,                                            true, "ACTIVATE",   },
diff --git a/src/northbridge/intel/haswell/native_raminit/raminit_native.h b/src/northbridge/intel/haswell/native_raminit/raminit_native.h
index 53dbe4df28..123f579a76 100644
--- a/src/northbridge/intel/haswell/native_raminit/raminit_native.h
+++ b/src/northbridge/intel/haswell/native_raminit/raminit_native.h
@@ -68,6 +68,29 @@ enum margin_parameter {
 	WrT,
 	WrDqsT,
 	RdV,
+	WrV,
+	WrLevel,
+	WrTBit,
+	RdTBit,
+	RdVBit,
+	INVALID_MARGIN,
+};
+
+/*
+ * This enum is used to index an array of margin results. Those are
+ * used to keep track of available margin in more advanced training
+ * algorithms (optimisation), c.f. margin_result member in sysinfo.
+ */
+enum last_margin_param {
+	LastRxV,
+	LastRxT,
+	LastTxV,
+	LastTxT,
+	LastRcvEna,
+	LastWrLevel,
+	LastCmdT,
+	LastCmdV,
+	MAX_RESULT_TYPE,
 };
 
 enum opt_param {
@@ -232,6 +255,7 @@ enum raminit_status {
 	RAMINIT_STATUS_SUCCESS = 0,
 	RAMINIT_STATUS_NO_MEMORY_INSTALLED,
 	RAMINIT_STATUS_UNSUPPORTED_MEMORY,
+	RAMINIT_STATUS_INVALID_PARAMETER,
 	RAMINIT_STATUS_MPLL_INIT_FAILURE,
 	RAMINIT_STATUS_POLL_TIMEOUT,
 	RAMINIT_STATUS_REUT_ERROR,
@@ -239,6 +263,7 @@ enum raminit_status {
 	RAMINIT_STATUS_RCVEN_FAILURE,
 	RAMINIT_STATUS_RMPR_FAILURE,
 	RAMINIT_STATUS_JWRL_FAILURE,
+	RAMINIT_STATUS_1D_MARGINING_FAILURE,
 	RAMINIT_STATUS_INVALID_CACHE,
 	RAMINIT_STATUS_UNSPECIFIED_ERROR, /** TODO: Deprecated in favor of specific values **/
 };
@@ -261,12 +286,32 @@ struct raminit_dimm_info {
 	bool valid;
 };
 
+struct last_margin {
+	uint32_t start;
+	uint32_t end;
+};
+
+struct time_margin {
+	uint8_t left;
+	uint8_t center;
+	uint8_t right;
+};
+
 struct vref_margin {
 	uint8_t low;
 	uint8_t center;
 	uint8_t high;
 };
 
+union raw_bitlane_errors {
+	struct {
+		uint32_t lower;
+		uint32_t upper;
+		uint8_t ecc;
+	};
+	uint8_t per_byte[NUM_LANES];
+};
+
 struct sysinfo {
 	enum raminit_boot_mode bootmode;
 	enum generic_stepping stepping;
@@ -355,6 +400,9 @@ struct sysinfo {
 	uint8_t rxdqsn[NUM_CHANNELS][NUM_SLOTRANKS][NUM_LANES];
 	int8_t  rxvref[NUM_CHANNELS][NUM_SLOTRANKS][NUM_LANES];
 
+	struct time_margin rxdqpb[NUM_CHANNELS][NUM_SLOTRANKS][NUM_LANES][NUM_BITS];
+	struct time_margin txdqpb[NUM_CHANNELS][NUM_SLOTRANKS][NUM_LANES][NUM_BITS];
+
 	struct vref_margin rxdqvrefpb[NUM_CHANNELS][NUM_SLOTRANKS][NUM_LANES][NUM_BITS];
 
 	uint8_t clk_pi_code[NUM_CHANNELS][NUM_SLOTRANKS];
@@ -365,6 +413,11 @@ struct sysinfo {
 	uint8_t cmd_north_pi_code[NUM_CHANNELS][NUM_GROUPS];
 	uint8_t cmd_south_pi_code[NUM_CHANNELS][NUM_GROUPS];
 
+	/*
+	 * BIG WARNING: The slotrank comes before the channel!
+	 */
+	struct last_margin results[MAX_RESULT_TYPE][NUM_SLOTRANKS][NUM_CHANNELS][NUM_LANES];
+
 	union tc_bank_reg tc_bank[NUM_CHANNELS];
 	union tc_bank_rank_a_reg tc_bankrank_a[NUM_CHANNELS];
 	union tc_bank_rank_b_reg tc_bankrank_b[NUM_CHANNELS];
@@ -488,6 +541,9 @@ enum raminit_status train_sense_amp_offset(struct sysinfo *ctrl);
 enum raminit_status train_receive_enable(struct sysinfo *ctrl);
 enum raminit_status train_read_mpr(struct sysinfo *ctrl);
 enum raminit_status train_jedec_write_leveling(struct sysinfo *ctrl);
+enum raminit_status train_read_timing_centering(struct sysinfo *ctrl);
+enum raminit_status train_write_timing_centering(struct sysinfo *ctrl);
+enum raminit_status train_read_voltage_centering(struct sysinfo *ctrl);
 enum raminit_status optimise_comp(struct sysinfo *ctrl);
 enum raminit_status save_training_values(struct sysinfo *ctrl);
 enum raminit_status restore_training_values(struct sysinfo *ctrl);
@@ -536,6 +592,7 @@ void reut_issue_mrs_all(
 	const uint16_t val[NUM_SLOTS]);
 
 enum raminit_status reut_issue_zq(struct sysinfo *ctrl, uint8_t chanmask, uint8_t zq_type);
+union raw_bitlane_errors get_bitlane_errors(const uint8_t channel);
 
 void write_wdb_fixed_pat(
 	const struct sysinfo *ctrl,
@@ -604,6 +661,8 @@ void download_regfile(
 	bool read_rf_rd,
 	bool read_rf_wr);
 
+uint32_t get_max_margin_for_param(const enum margin_parameter param);
+
 void change_margin(
 	struct sysinfo *ctrl,
 	const enum margin_parameter param,
diff --git a/src/northbridge/intel/haswell/native_raminit/reut.c b/src/northbridge/intel/haswell/native_raminit/reut.c
index 31019f74a1..10fb8cc1c3 100644
--- a/src/northbridge/intel/haswell/native_raminit/reut.c
+++ b/src/northbridge/intel/haswell/native_raminit/reut.c
@@ -194,3 +194,12 @@ enum raminit_status reut_issue_zq(struct sysinfo *ctrl, uint8_t chanmask, uint8_
 
 	return status;
 }
+
+union raw_bitlane_errors get_bitlane_errors(const uint8_t channel)
+{
+	return (union raw_bitlane_errors) {
+		.lower = mchbar_read32(REUT_ch_ERR_DATA_STATUS(channel) + 0),
+		.upper = mchbar_read32(REUT_ch_ERR_DATA_STATUS(channel) + 4),
+		.ecc   = mchbar_read8(REUT_ch_ERR_MISC_STATUS(channel)),
+	};
+}
diff --git a/src/northbridge/intel/haswell/native_raminit/train_1d_margins.c b/src/northbridge/intel/haswell/native_raminit/train_1d_margins.c
new file mode 100644
index 0000000000..bea17f2f1a
--- /dev/null
+++ b/src/northbridge/intel/haswell/native_raminit/train_1d_margins.c
@@ -0,0 +1,305 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include "raminit_native.h"
+#include "ranges.h"
+
+#define MAX_BITLANE_LINES	(2 * MAX_POSSIBLE_BOTH + 1)
+#define MARGIN_MIN_WIDTH	8
+
+#define MARGIN_1D_PLOT		RAM_DEBUG
+
+static void print_bitlane(
+	struct sysinfo *ctrl,
+	const uint8_t channel,
+	const int32_t m_start,
+	const int32_t m_step,
+	const int32_t m_stop,
+	const union raw_bitlane_errors bit_failures[NUM_CHANNELS][MAX_BITLANE_LINES])
+{
+	for (int32_t offset = m_start; offset <= m_stop; offset += m_step) {
+		const uint32_t index = offset + MAX_POSSIBLE_BOTH;
+		const union raw_bitlane_errors *failures = &bit_failures[channel][index];
+		printk(MARGIN_1D_PLOT, "\n% 5d\t", offset);
+		for (uint8_t byte = 0; byte < ctrl->lanes; byte++) {
+			const uint8_t byte_errors = failures->per_byte[byte];
+			for (uint8_t bit = 0; bit < NUM_BITS; bit++)
+				printk(MARGIN_1D_PLOT, byte_errors & BIT(bit) ? "#" : ".");
+		}
+	}
+}
+
+static enum raminit_status apply_dq_offsets(
+	struct sysinfo *ctrl,
+	const uint8_t channel,
+	const uint8_t rank,
+	const enum margin_parameter param,
+	enum raminit_status status,
+	const struct linear_train_data chan_data[])
+{
+	printk(BIOS_DEBUG, "\nC%u.R%u:  Left\tRight\tWidth\tCenter\n", channel, rank);
+
+	for (uint8_t byte = 0; byte < ctrl->lanes; byte++) {
+		const struct linear_train_data *const curr_data = &chan_data[byte];
+		const int32_t lwidth = range_width(curr_data->largest);
+		const int32_t center = range_center(curr_data->largest);
+		printk(BIOS_DEBUG, "  B%u:   %d\t%d\t%d\t%d",
+			byte,
+			curr_data->largest.start,
+			curr_data->largest.end,
+			lwidth,
+			center);
+		if (lwidth < MARGIN_MIN_WIDTH) {
+			printk(BIOS_ERR,
+				"\t1D eye too small! channel: %u byte: %u width: %d\n",
+				channel, byte, lwidth);
+			status = RAMINIT_STATUS_1D_MARGINING_FAILURE;
+		} else {
+			printk(BIOS_DEBUG, "\n");
+		}
+		const struct last_margin margin = {
+			.start = ABS(curr_data->largest.start - center) * 10,
+			.end   = ABS(curr_data->largest.end   - center) * 10,
+		};
+		switch (param) {
+		case RdT:
+			ctrl->rxdqsp[channel][rank][byte] += center;
+			ctrl->rxdqsn[channel][rank][byte] += center;
+			update_rxt(ctrl, channel, rank, byte, RXT_RESTORE, 0);
+			ctrl->results[LastRxT][rank][channel][byte] = margin;
+			break;
+		case WrT:
+			ctrl->tx_dq[channel][rank][byte] += center;
+			update_txt(ctrl, channel, rank, byte, TXT_RESTORE, 0);
+			ctrl->results[LastTxT][rank][channel][byte] = margin;
+			break;
+		case RdV:
+			/* RdV training uses half steps */
+			ctrl->rxvref[channel][rank][byte] += center / 2;
+			update_rxt(ctrl, channel, rank, byte, RXT_RESTORE, 0);
+			ctrl->results[LastRxV][rank][channel][byte] = margin;
+			break;
+		default:
+			break;
+		}
+	}
+	return status;
+}
+
+static const char *const get_delay_string(const enum margin_parameter param)
+{
+	switch (param) {
+		case RdT:	return "RdDqsDelay";
+		case WrT:	return "WrDqsDelay";
+		case RdV:	return "RdVoltage";
+		default:	return NULL;
+	}
+}
+
+static enum margin_parameter get_per_bit_margin_param(const enum margin_parameter param)
+{
+	switch (param) {
+		case RdT:	return RdTBit;
+		case WrT:	return WrTBit;
+		case RdV:	return RdVBit;
+		default:	return INVALID_MARGIN;
+	}
+}
+
+static enum raminit_status train_1d_margin(
+	struct sysinfo *ctrl,
+	const uint8_t chanmask_in,
+	const enum margin_parameter param,
+	const bool reset_per_bit,
+	const uint8_t loopcount)
+{
+	const char *const delay_string = get_delay_string(param);
+	if (!delay_string) {
+		printk(BIOS_ERR, "%s: Invalid margin parameter %u\n", __func__, param);
+		return RAMINIT_STATUS_INVALID_PARAMETER;
+	}
+	setup_io_test_basic_va(ctrl, chanmask_in, loopcount, NSOE);
+
+	const enum margin_parameter param_bit = get_per_bit_margin_param(param);
+	if (reset_per_bit && param_bit == INVALID_MARGIN) {
+		printk(BIOS_ERR, "%s: Invalid per-bit margin for param %u\n", __func__, param);
+		return RAMINIT_STATUS_INVALID_PARAMETER;
+	}
+
+	const int32_t m_stop = get_max_margin_for_param(param);
+	const int32_t m_start = -m_stop;
+	const int32_t m_step = 1;
+	enum raminit_status status = 0;
+	for (uint8_t rank = 0; rank < NUM_SLOTRANKS; rank++) {
+		if (!does_rank_exist(ctrl, rank))
+			continue;
+
+		/* Hell thinks this should be resetting the currently selected rank */
+		if (reset_per_bit) {
+			change_1d_margin_multicast(
+				ctrl,
+				param_bit,
+				0x88888888,
+				rank,
+				true,
+				REG_FILE_USE_RANK);
+		}
+		printk(BIOS_DEBUG, "Rank %u\n", rank);
+		printk(MARGIN_1D_PLOT, "Channel");
+		for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
+			if (!rank_in_ch(ctrl, rank, channel))
+				continue;
+
+			printk(MARGIN_1D_PLOT, "\t%u\t\t", channel);
+		}
+		printk(MARGIN_1D_PLOT, "\nByte");
+		for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
+			if (!rank_in_ch(ctrl, rank, channel))
+				continue;
+
+			printk(MARGIN_1D_PLOT, "\t");
+			for (uint8_t byte = 0; byte < ctrl->lanes; byte++)
+				printk(MARGIN_1D_PLOT, "%u ", byte);
+		}
+		uint8_t chanmask = 0;
+		for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
+			chanmask |= select_reut_ranks(ctrl, channel, BIT(rank));
+			if (!(BIT(channel) & chanmask))
+				continue;
+
+			/* Update rank timing to middle value */
+			for (uint8_t byte = 0; byte < ctrl->lanes; byte++) {
+				if (param == RdT) {
+					ctrl->rxdqsp[channel][rank][byte] = 32;
+					ctrl->rxdqsn[channel][rank][byte] = 32;
+					update_rxt(ctrl, channel, rank, byte, RXT_RESTORE, 0);
+				} else if (param == WrT) {
+					/*
+					 * Put TxDq in the middle of the strobe and ensure
+					 * there is enough room to sweep to the right.
+					 */
+					uint16_t tx_dq = ctrl->txdqs[channel][rank][byte] + 32;
+					if ((tx_dq + m_stop) > 511)
+						tx_dq = 511 - m_stop;
+
+					ctrl->tx_dq[channel][rank][byte] = tx_dq;
+					update_txt(ctrl, channel, rank, byte, TXT_RESTORE, 0);
+				} else if (param == RdV) {
+					ctrl->rxvref[channel][rank][byte] = 0;
+					update_rxt(ctrl, channel, rank, byte, RXT_RESTORE, 0);
+				}
+			}
+
+			/* Set up REUT error counters to count errors per channel */
+			mchbar_write32(REUT_ch_ERR_COUNTER_CTL_x(channel, 0), 0);
+		}
+		if (!chanmask)
+			continue;
+
+		clear_data_offset_train_all(ctrl);
+		printk(MARGIN_1D_PLOT, "\n%s", delay_string);
+		struct linear_train_data region_data[NUM_CHANNELS][NUM_LANES] = { 0 };
+		union raw_bitlane_errors bit_errors[NUM_CHANNELS][MAX_BITLANE_LINES] = { 0 };
+		for (int32_t offset = m_start; offset <= m_stop; offset += m_step) {
+			printk(MARGIN_1D_PLOT, "\n% 5d", offset);
+			change_1d_margin_multicast(
+				ctrl,
+				param,
+				offset,
+				0,
+				false,
+				REG_FILE_USE_START);
+
+			run_io_test(ctrl, chanmask, ctrl->dq_pat, 1);
+			for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
+				if (!(chanmask & BIT(channel)))
+					continue;
+
+				/* Read out byte group error results and update limit */
+				const uint16_t result = get_byte_group_errors(channel);
+				bit_errors[channel][offset + MAX_POSSIBLE_BOTH] =
+						get_bitlane_errors(channel);
+				printk(MARGIN_1D_PLOT, "\t");
+				for (uint8_t byte = 0; byte < ctrl->lanes; byte++) {
+					const bool pass = !(result & BIT(byte));
+					printk(MARGIN_1D_PLOT, pass ? ". " : "# ");
+					linear_record_pass(
+						&region_data[channel][byte],
+						pass,
+						offset,
+						m_start,
+						m_step);
+				}
+			}
+		}
+		printk(MARGIN_1D_PLOT, "\n\nBit lane information");
+		for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
+			if (!(chanmask & BIT(channel)))
+				continue;
+
+			printk(MARGIN_1D_PLOT, "\nChannel %u\nByte    ", channel);
+			for (uint8_t byte = 0; byte < ctrl->lanes; byte++)
+				printk(MARGIN_1D_PLOT, "%u       ", byte);
+
+			printk(MARGIN_1D_PLOT, "\nBit     ");
+			for (uint8_t bit_count = 0; bit_count < ctrl->lanes * 8; bit_count++)
+				printk(MARGIN_1D_PLOT, "%u", bit_count % 8);
+
+			printk(MARGIN_1D_PLOT, "\n%s", delay_string);
+			print_bitlane(
+				ctrl,
+				channel,
+				m_start,
+				m_step,
+				m_stop,
+				bit_errors);
+
+			printk(MARGIN_1D_PLOT, "\n");
+		}
+		change_1d_margin_multicast(
+			ctrl,
+			param,
+			0,
+			0,
+			false,
+			REG_FILE_USE_CURRENT);
+
+		for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
+			if (!(chanmask & BIT(channel)))
+				continue;
+
+			status = apply_dq_offsets(
+				ctrl,
+				channel,
+				rank,
+				param,
+				status,
+				region_data[channel]);
+		}
+		printk(BIOS_DEBUG, "\n");
+	}
+
+	return status;
+}
+
+#define DATA_TRAIN_LOOP_COUNT	15
+
+enum raminit_status train_read_timing_centering(struct sysinfo *ctrl)
+{
+	return train_1d_margin(ctrl, ctrl->chanmap, RdT, true, DATA_TRAIN_LOOP_COUNT);
+}
+
+enum raminit_status train_write_timing_centering(struct sysinfo *ctrl)
+{
+	return train_1d_margin(ctrl, ctrl->chanmap, WrT, true, DATA_TRAIN_LOOP_COUNT);
+}
+
+enum raminit_status train_read_voltage_centering(struct sysinfo *ctrl)
+{
+	/*
+	 * We do not reset per-bit RdV. Haswell only has one RX_OFFSET_VDQ register
+	 * per rank, so this would require combining training results for all ranks
+	 * somehow. While Broadwell and newer platforms have per-rank RX_OFFSET_VDQ
+	 * registers, we can keep using sense amp offset training results, for now.
+	 */
+	return train_1d_margin(ctrl, ctrl->chanmap, RdV, false, DATA_TRAIN_LOOP_COUNT);
+}
diff --git a/src/northbridge/intel/haswell/registers/mchbar.h b/src/northbridge/intel/haswell/registers/mchbar.h
index a944e12625..5be398734c 100644
--- a/src/northbridge/intel/haswell/registers/mchbar.h
+++ b/src/northbridge/intel/haswell/registers/mchbar.h
@@ -16,7 +16,9 @@
 
 /* DDR DATA per-channel per-bytelane */
 #define RX_TRAIN_ch_r_b(ch, rank, byte)		_DDRIO_C_R_B(0x0000, ch, rank, byte)
+#define RX_PER_BIT(ch, rank, byte)		_DDRIO_C_R_B(0x0010, ch, rank, byte)
 #define TX_TRAIN_ch_r_b(ch, rank, byte)		_DDRIO_C_R_B(0x0020, ch, rank, byte)
+#define TX_PER_BIT(ch, rank, byte)		_DDRIO_C_R_B(0x0030, ch, rank, byte)
 
 #define RX_OFFSET_VDQ(ch, byte)			_DDRIO_C_R_B(0x004c, ch, 0, byte)
 
@@ -126,8 +128,11 @@
 
 #define REUT_ch_ERR_DATA_MASK(ch)		_MCMAIN_C(0x40d8, ch)
 
+#define REUT_ch_ERR_DATA_STATUS(ch)		_MCMAIN_C(0x40e0, ch)
 #define REUT_ch_ERR_MISC_STATUS(ch)		_MCMAIN_C(0x40e8, ch)
 
+#define REUT_ch_ERR_COUNTER_CTL_x(ch, byte)	_MCMAIN_C_X(0x40f0, ch, byte)
+
 #define REUT_ch_MISC_CKE_CTRL(ch)		_MCMAIN_C(0x4190, ch)
 #define REUT_ch_MISC_ODT_CTRL(ch)		_MCMAIN_C(0x4194, ch)
 #define REUT_ch_MISC_PAT_CADB_CTRL(ch)		_MCMAIN_C(0x4198, ch)

From 5e46ac13648e30b5aea8ecc5b7a8403f39fc1b26 Mon Sep 17 00:00:00 2001
From: Subrata Banik <subratabanik@google.com>
Date: Mon, 23 Feb 2026 09:20:14 +0530
Subject: [PATCH 3491/3886] mb/google/bluey: Resize WP_RO and add RW_UNUSED
 region

Modify the flash map (fmd) to reduce the Write-Protected RO (WP_RO)
section from 12M to 8M. The recovered 4M of space is reallocated
to a new RW_UNUSED region positioned before RW_LEGACY.

BUG=None
TEST=Build bluey image and verify FMAP table with 'fmap_decode'.
Ensure resulting layout matches the intended offsets.

Change-Id: I6dde5fac5ba3be5fb28f2cd46c5518d87082c067
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91379
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
---
 src/mainboard/google/bluey/chromeos-nogsc.fmd | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/src/mainboard/google/bluey/chromeos-nogsc.fmd b/src/mainboard/google/bluey/chromeos-nogsc.fmd
index 6ffe1d335c..85ef0fe673 100644
--- a/src/mainboard/google/bluey/chromeos-nogsc.fmd
+++ b/src/mainboard/google/bluey/chromeos-nogsc.fmd
@@ -1,7 +1,7 @@
 ## SPDX-License-Identifier: GPL-2.0-only
 
 FLASH@0x0 CONFIG_ROM_SIZE {
-	WP_RO 12M {
+	WP_RO 8M {
 		RO_SECTION {
 			BOOTBLOCK 512K
 			FMAP 4K
@@ -37,5 +37,7 @@ FLASH@0x0 CONFIG_ROM_SIZE {
 		RW_FWID_B 256
 	}
 
+	RW_UNUSED 4M
+
 	RW_LEGACY(CBFS)
 }

From 523242b2b933d4e4c12c6fd11dc130780ce28486 Mon Sep 17 00:00:00 2001
From: Subrata Banik <subratabanik@google.com>
Date: Mon, 23 Feb 2026 09:22:25 +0530
Subject: [PATCH 3492/3886] google/bluey: Add RW_CDT region to flash map

Carve out 256K from the RW_UNUSED region to create a new RW_CDT
section at the end of the flash. The RW_UNUSED region is reduced
from 4096K (4M) to 3840K to maintain the existing flash offset
for the start of the unused block.

The RW_CDT region will be used to store Configuration Data Tables,
allowing for platform-specific configuration binary blobs to be
stored and updated in the RW section of the flash.

BUG=b:483194720
TEST=Build bluey and verify the FMAP layout using 'dump_fmap'.
     Ensure RW_CDT exists at the expected offset.

dump_fmap -h ../../out/build/bluey/firmware/image-bluey.serial.bin
RW_CDT                     01fc0000    02000000    00040000
RW_UNUSED                  01c00000    01fc0000    003c0000
RW_LEGACY                  0192e000    01c00000    002d2000
RW_SECTION_B               010ae000    0192e000    00880000
  RW_FWID_B                  0192df00    0192e000    00000100
  FW_MAIN_B                  010b0000    0192df00    0087df00
  VBLOCK_B                   010ae000    010b0000    00002000
RW_SECTION_A               0082e000    010ae000    00880000
  RW_FWID_A                  010adf00    010ae000    00000100
  FW_MAIN_A                  00830000    010adf00    0087df00
  VBLOCK_A                   0082e000    00830000    00002000
RW_MISC                    00800000    0082e000    0002e000
  RW_NVRAM                   0082a000    0082e000    00004000
  RW_VPD                     00822000    0082a000    00008000
  RW_SHARED                  00821000    00822000    00001000
  SHARED_DATA                00821000    00822000    00001000
  RW_ELOG                    00820000    00821000    00001000
  UNIFIED_MRC_CACHE          00800000    00820000    00020000
    RW_MRC_CACHE               00810000    00820000    00010000
    RECOVERY_MRC_CACHE         00800000    00810000    00010000
WP_RO                      00000000    00800000    00800000
  RO_VPD                     007fc000    00800000    00004000
  RO_GSCVD                   007fa000    007fc000    00002000
  RO_SECTION                 00000000    007fa000    007fa000
    RO_FRID                    007f9f00    007fa000    00000100
    GBB                        007f7000    007f9f00    00002f00
    COREBOOT                   00081000    007f7000    00776000
    FMAP                       00080000    00081000    00001000
    BOOTBLOCK                  00000000    00080000    00080000

Change-Id: I7d305647731862e61871e781ad7bfb7cd430b699
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91380
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
---
 src/mainboard/google/bluey/chromeos-nogsc.fmd | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/src/mainboard/google/bluey/chromeos-nogsc.fmd b/src/mainboard/google/bluey/chromeos-nogsc.fmd
index 85ef0fe673..cd3caa84f2 100644
--- a/src/mainboard/google/bluey/chromeos-nogsc.fmd
+++ b/src/mainboard/google/bluey/chromeos-nogsc.fmd
@@ -37,7 +37,9 @@ FLASH@0x0 CONFIG_ROM_SIZE {
 		RW_FWID_B 256
 	}
 
-	RW_UNUSED 4M
-
 	RW_LEGACY(CBFS)
+
+	RW_UNUSED 3840K
+
+	RW_CDT 256K
 }

From 08dcaf404cf8a0ff84148abc02dff08aa3f92718 Mon Sep 17 00:00:00 2001
From: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Date: Tue, 24 Feb 2026 15:09:24 +0800
Subject: [PATCH 3493/3886] mb/google/nissa/var/yavilla: Add micron memory to
 RAM ID table

DRAM Part Name                 ID to assign
MT62F1G32D2DS-031RF WT:C       2 (0010)
MT62F2G32D4DS-031RF WT:C       5 (0101)

BUG=b:487113903
TEST=build nissa coreboot

Change-Id: I5b49ec3513fd1878942c96bc8b5375d79e049898
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91406
Reviewed-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/google/brya/variants/yavilla/memory/Makefile.mk | 4 ++--
 .../google/brya/variants/yavilla/memory/dram_id.generated.txt | 2 ++
 .../google/brya/variants/yavilla/memory/mem_parts_used.txt    | 2 ++
 3 files changed, 6 insertions(+), 2 deletions(-)

diff --git a/src/mainboard/google/brya/variants/yavilla/memory/Makefile.mk b/src/mainboard/google/brya/variants/yavilla/memory/Makefile.mk
index 26c31d4ef3..99061e1d12 100644
--- a/src/mainboard/google/brya/variants/yavilla/memory/Makefile.mk
+++ b/src/mainboard/google/brya/variants/yavilla/memory/Makefile.mk
@@ -6,9 +6,9 @@
 SPD_SOURCES =
 SPD_SOURCES += spd/lp5/set-0/spd-1.hex      # ID = 0(0b0000)  Parts = MT62F512M32D2DR-031 WT:B, H9JCNNNBK3MLYR-N6E
 SPD_SOURCES += spd/lp5/set-0/spd-10.hex      # ID = 1(0b0001)  Parts = H58G66CK8BX147
-SPD_SOURCES += spd/lp5/set-0/spd-3.hex      # ID = 2(0b0010)  Parts = H58G56AK6BX069, K3LKBKB0BM-MGCP
+SPD_SOURCES += spd/lp5/set-0/spd-3.hex      # ID = 2(0b0010)  Parts = H58G56AK6BX069, K3LKBKB0BM-MGCP, MT62F1G32D2DS-031RF WT:C
 SPD_SOURCES += spd/lp5/set-0/spd-7.hex      # ID = 3(0b0011)  Parts = H58G56BK7BX068, MT62F1G32D2DS-026 WT:B, K3KL8L80CM-MGCT
 SPD_SOURCES += spd/lp5/set-0/spd-8.hex      # ID = 4(0b0100)  Parts = H58G66BK7BX067, MT62F2G32D4DS-026 WT:B, K3KL9L90CM-MGCT
-SPD_SOURCES += spd/lp5/set-0/spd-6.hex      # ID = 5(0b0101)  Parts = H58G66AK6BX070
+SPD_SOURCES += spd/lp5/set-0/spd-6.hex      # ID = 5(0b0101)  Parts = H58G66AK6BX070, MT62F2G32D4DS-031RF WT:C
 SPD_SOURCES += spd/lp5/set-0/spd-9.hex      # ID = 6(0b0110)  Parts = K3KL6L60GM-MGCT
 SPD_SOURCES += spd/lp5/set-0/spd-11.hex      # ID = 7(0b0111)  Parts = H58G56CK8BX146
diff --git a/src/mainboard/google/brya/variants/yavilla/memory/dram_id.generated.txt b/src/mainboard/google/brya/variants/yavilla/memory/dram_id.generated.txt
index 1264f20e91..6b938ba8dd 100644
--- a/src/mainboard/google/brya/variants/yavilla/memory/dram_id.generated.txt
+++ b/src/mainboard/google/brya/variants/yavilla/memory/dram_id.generated.txt
@@ -18,3 +18,5 @@ K3KL9L90CM-MGCT                4 (0100)
 H58G66AK6BX070                 5 (0101)
 K3KL6L60GM-MGCT                6 (0110)
 H58G56CK8BX146                 7 (0111)
+MT62F1G32D2DS-031RF WT:C       2 (0010)
+MT62F2G32D4DS-031RF WT:C       5 (0101)
diff --git a/src/mainboard/google/brya/variants/yavilla/memory/mem_parts_used.txt b/src/mainboard/google/brya/variants/yavilla/memory/mem_parts_used.txt
index 76efa2cd44..d0add1f65a 100644
--- a/src/mainboard/google/brya/variants/yavilla/memory/mem_parts_used.txt
+++ b/src/mainboard/google/brya/variants/yavilla/memory/mem_parts_used.txt
@@ -23,3 +23,5 @@ K3KL9L90CM-MGCT
 H58G66AK6BX070
 K3KL6L60GM-MGCT
 H58G56CK8BX146
+MT62F1G32D2DS-031RF WT:C
+MT62F2G32D4DS-031RF WT:C

From e84415b8f8c479be0d4f10dda421976ca7e4acc6 Mon Sep 17 00:00:00 2001
From: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Date: Tue, 24 Feb 2026 15:10:20 +0800
Subject: [PATCH 3494/3886] mb/google/nissa/var/yaviks: Add micron memory to
 RAM ID table

DRAM Part Name                 ID to assign
MT62F1G32D2DS-031RF WT:C       2 (0010)
MT62F2G32D4DS-031RF WT:C       5 (0101)

BUG=b:487113903
TEST=build nissa coreboot

Change-Id: I171d2cdfcd4ec41562b09705dab64f00ce51c6a2
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91407
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com>
---
 src/mainboard/google/brya/variants/yaviks/memory/Makefile.mk  | 4 ++--
 .../google/brya/variants/yaviks/memory/dram_id.generated.txt  | 2 ++
 .../google/brya/variants/yaviks/memory/mem_parts_used.txt     | 2 ++
 3 files changed, 6 insertions(+), 2 deletions(-)

diff --git a/src/mainboard/google/brya/variants/yaviks/memory/Makefile.mk b/src/mainboard/google/brya/variants/yaviks/memory/Makefile.mk
index 8f38bca9de..ccd34e882d 100644
--- a/src/mainboard/google/brya/variants/yaviks/memory/Makefile.mk
+++ b/src/mainboard/google/brya/variants/yaviks/memory/Makefile.mk
@@ -6,9 +6,9 @@
 SPD_SOURCES =
 SPD_SOURCES += spd/lp5/set-0/spd-1.hex      # ID = 0(0b0000)  Parts = MT62F512M32D2DR-031 WT:B, H9JCNNNBK3MLYR-N6E
 SPD_SOURCES += spd/lp5/set-0/spd-2.hex      # ID = 1(0b0001)  Parts = MT62F1G32D4DR-031 WT:B
-SPD_SOURCES += spd/lp5/set-0/spd-3.hex      # ID = 2(0b0010)  Parts = H58G56AK6BX069, K3LKBKB0BM-MGCP
+SPD_SOURCES += spd/lp5/set-0/spd-3.hex      # ID = 2(0b0010)  Parts = H58G56AK6BX069, K3LKBKB0BM-MGCP, MT62F1G32D2DS-031RF WT:C
 SPD_SOURCES += spd/lp5/set-0/spd-7.hex      # ID = 3(0b0011)  Parts = H58G56BK7BX068, MT62F1G32D2DS-026 WT:B, K3KL8L80CM-MGCT
 SPD_SOURCES += spd/lp5/set-0/spd-8.hex      # ID = 4(0b0100)  Parts = H58G66BK7BX067, MT62F2G32D4DS-026 WT:B, K3KL9L90CM-MGCT
-SPD_SOURCES += spd/lp5/set-0/spd-6.hex      # ID = 5(0b0101)  Parts = H58G66AK6BX070
+SPD_SOURCES += spd/lp5/set-0/spd-6.hex      # ID = 5(0b0101)  Parts = H58G66AK6BX070, MT62F2G32D4DS-031RF WT:C
 SPD_SOURCES += spd/lp5/set-0/spd-9.hex      # ID = 6(0b0110)  Parts = K3KL6L60GM-MGCT
 SPD_SOURCES += spd/lp5/set-0/spd-11.hex      # ID = 7(0b0111)  Parts = H58G56CK8BX146
diff --git a/src/mainboard/google/brya/variants/yaviks/memory/dram_id.generated.txt b/src/mainboard/google/brya/variants/yaviks/memory/dram_id.generated.txt
index d0e3dfe8de..4dbb10bc33 100644
--- a/src/mainboard/google/brya/variants/yaviks/memory/dram_id.generated.txt
+++ b/src/mainboard/google/brya/variants/yaviks/memory/dram_id.generated.txt
@@ -18,3 +18,5 @@ K3KL9L90CM-MGCT                4 (0100)
 H58G66AK6BX070                 5 (0101)
 K3KL6L60GM-MGCT                6 (0110)
 H58G56CK8BX146                 7 (0111)
+MT62F1G32D2DS-031RF WT:C       2 (0010)
+MT62F2G32D4DS-031RF WT:C       5 (0101)
diff --git a/src/mainboard/google/brya/variants/yaviks/memory/mem_parts_used.txt b/src/mainboard/google/brya/variants/yaviks/memory/mem_parts_used.txt
index d9e4129cba..3a13bb4951 100644
--- a/src/mainboard/google/brya/variants/yaviks/memory/mem_parts_used.txt
+++ b/src/mainboard/google/brya/variants/yaviks/memory/mem_parts_used.txt
@@ -23,3 +23,5 @@ K3KL9L90CM-MGCT
 H58G66AK6BX070
 K3KL6L60GM-MGCT
 H58G56CK8BX146
+MT62F1G32D2DS-031RF WT:C
+MT62F2G32D4DS-031RF WT:C

From 38988a727e9e15bbc675929205db3ba682575fcc Mon Sep 17 00:00:00 2001
From: Jarried Lin <jarried.lin@mediatek.corp-partner.google.com>
Date: Mon, 9 Feb 2026 13:17:18 +0800
Subject: [PATCH 3495/3886] util/mediatek: Reduce non-boot related BROM
 settings

Reduce BROM settings that are not related to boot to save boot time.

BUG=b:480810041
TEST= 0:1st timestamp reduce from 400ms to 250ms

Change-Id: Ia97a78515d80a141b9b409407f6e41a07261cad9
Signed-off-by: Jarried Lin <jarried.lin@mediatek.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91423
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Chen-Tsung Hsieh <chentsung@google.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
---
 util/mediatek/gen-bl-img.py | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/util/mediatek/gen-bl-img.py b/util/mediatek/gen-bl-img.py
index 7cd7dbb079..a98b1ea845 100755
--- a/util/mediatek/gen-bl-img.py
+++ b/util/mediatek/gen-bl-img.py
@@ -43,7 +43,7 @@ def gen_gfh_info(chip, data):
 		0x00000000, 0x00000000, 0x00000000, 0x00000000,
 		0x00000000, 0x00000000, 0x00000000, 0x00000000,
 		0x00000000, 0x00000000, 0x00000000, 0x00000000,
-		0x00000000, 0x00000000, 0x00006400, 0x00001388,
+		0x00000000, 0x52000000, 0x00006400, 0x00001388,
 		0x00000000, 0x00000000, 0x00000000, 0x00000000)
 
 	return gfh

From 8ba58ef800aa899feada62c0562f3f64857934cf Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Thu, 26 Feb 2026 08:20:05 -0600
Subject: [PATCH 3496/3886] mb/samsung/lumpy: Correct NID 0x08 HDA pin config
 macro usage

Commit eb504eb49ab7 ("mb/samsung/lumpy: Fix HDA pin configuration
issues") incorrectly used AZALIA_PIN_CFG_NC(0) as a standalone entry
for NID 0x08. Change to AZALIA_PIN_CFG(0, 0x08, AZALIA_PIN_CFG_NC(0))
so the verb for NID 0x08 is emitted correctly.

Change-Id: Iaf23b6e8791a352758189d92ad9c89414fc5a22d
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91442
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
---
 src/mainboard/samsung/lumpy/hda_verb.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/mainboard/samsung/lumpy/hda_verb.c b/src/mainboard/samsung/lumpy/hda_verb.c
index aedd7b6ce2..e6ed443a95 100644
--- a/src/mainboard/samsung/lumpy/hda_verb.c
+++ b/src/mainboard/samsung/lumpy/hda_verb.c
@@ -56,7 +56,7 @@ const u32 cim_verb_data[] = {
 					)),
 
 	/* Pin Complex (NID 0x08) - Unused (NC) */
-	AZALIA_PIN_CFG_NC(0),
+	AZALIA_PIN_CFG(0, 0x08, AZALIA_PIN_CFG_NC(0)),
 
 	/* Pin Complex (NID 0x09) - Internal Digital Mic */
 	AZALIA_PIN_CFG(0, 0x09, AZALIA_PIN_DESC(

From c57b88d74ddd6e7296b60a8e327a2d2c22ac725c Mon Sep 17 00:00:00 2001
From: Rui Zhou <zhourui@huaqin.corp-partner.google.com>
Date: Thu, 26 Feb 2026 09:28:08 +0800
Subject: [PATCH 3497/3886] mb/google/brox/var/lotso: delete
 mb_get_channel_disable_mask

We found that the lotso project has already used
variant_is_half_populated. If we continue to use the
mb_get_channel_disable_mask API, it will reduce the memory of each DDR
by half. In reality, we are reducing the number of DDR modules (from 4
to 2), so we should remove mb_get_channel_disable_mask to ensure proper
DIMM identification.

BUG=b:468889066
BRANCH=None
TEST=boot to kernel success, and the log shows that the RAM ID is correct.

Change-Id: Ia7fc4610b3257bc20a871080f52f02e089b8531c
Signed-off-by: Rui Zhou <zhourui@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91426
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
---
 src/mainboard/google/brox/Kconfig                 |  1 -
 src/mainboard/google/brox/variants/lotso/memory.c | 13 -------------
 2 files changed, 14 deletions(-)

diff --git a/src/mainboard/google/brox/Kconfig b/src/mainboard/google/brox/Kconfig
index bb4d3746b2..8847f33e72 100644
--- a/src/mainboard/google/brox/Kconfig
+++ b/src/mainboard/google/brox/Kconfig
@@ -81,7 +81,6 @@ config BOARD_GOOGLE_BROX_EC_ISH
 config BOARD_GOOGLE_LOTSO
 	select BOARD_GOOGLE_BASEBOARD_BROX
 	select CHROMEOS_WIFI_SAR if CHROMEOS
-	select ENFORCE_MEM_CHANNEL_DISABLE
 	select MAINBOARD_HAS_GOOGLE_STRAUSS_KEYBOARD
 	select USE_UNIFIED_AP_FIRMWARE_FOR_UFS_AND_NON_UFS
 
diff --git a/src/mainboard/google/brox/variants/lotso/memory.c b/src/mainboard/google/brox/variants/lotso/memory.c
index 0997707e9f..84b9f4a70d 100644
--- a/src/mainboard/google/brox/variants/lotso/memory.c
+++ b/src/mainboard/google/brox/variants/lotso/memory.c
@@ -99,19 +99,6 @@ bool variant_is_half_populated(void)
 	return gpio_get(GPP_S0);
 }
 
-uint8_t mb_get_channel_disable_mask(void)
-{
-	/*
-	 * GPP_S0 High -> One RAM Chip
-	 * GPP_S0 Low  -> Two RAM Chip
-	 * Disable all other channels except first two on each controller
-	 */
-	if (gpio_get(GPP_S0))
-		return (BIT(2) | BIT(3));
-
-	return 0;
-}
-
 void variant_get_spd_info(struct mem_spd *spd_info)
 {
 	spd_info->topo = MEM_TOPO_MEMORY_DOWN;

From f9f43d862db83745996f4587487902d70f9d280a Mon Sep 17 00:00:00 2001
From: Hualin Wei <weihualin@huaqin.corp-partner.google.com>
Date: Thu, 12 Feb 2026 12:38:36 +0800
Subject: [PATCH 3498/3886] spd/lp5: Add Micron memory part

Add Micron memory part MT62F2G32D4DS-023 to LP5
global list.

BUG=b:488228474
TEST=emerge-fatcat coreboot, rework by EE
     flash it and boot normal.

Change-Id: I5c628f35ae789a20688a761c09c1c04578e40f1f
Signed-off-by: Hualin Wei <weihualin@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91451
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com>
Reviewed-by: Pranava Y N <pranavayn@google.com>
---
 spd/lp5/memory_parts.json                      | 11 +++++++++++
 spd/lp5/set-0/parts_spd_manifest.generated.txt |  1 +
 spd/lp5/set-1/parts_spd_manifest.generated.txt |  1 +
 3 files changed, 13 insertions(+)

diff --git a/spd/lp5/memory_parts.json b/spd/lp5/memory_parts.json
index 033d001b70..4c21c7bb28 100644
--- a/spd/lp5/memory_parts.json
+++ b/spd/lp5/memory_parts.json
@@ -445,6 +445,17 @@
             "speedMbps": 7500,
             "lp5x": true
         }
+    },
+    {
+        "name":  "MT62F2G32D4DS-020 WT:D",
+        "attribs": {
+            "densityPerDieGb": 16,
+            "diesPerPackage": 4,
+            "bitWidthPerChannel": 16,
+            "ranksPerChannel": 2,
+            "speedMbps": 8533,
+            "lp5x": true
+        }
     }
     ]
 }
diff --git a/spd/lp5/set-0/parts_spd_manifest.generated.txt b/spd/lp5/set-0/parts_spd_manifest.generated.txt
index 0401c008e0..11221ec42c 100644
--- a/spd/lp5/set-0/parts_spd_manifest.generated.txt
+++ b/spd/lp5/set-0/parts_spd_manifest.generated.txt
@@ -43,3 +43,4 @@ MT62F1G32D2DS-031RF WT:C,spd-3.hex
 MT62F2G32D4DS-031RF WT:C,spd-6.hex
 RS1G32LO5D2FDB-23BT,spd-11.hex
 BWMYAX32P8A-32G,spd-7.hex
+MT62F2G32D4DS-020 WT:D,spd-10.hex
diff --git a/spd/lp5/set-1/parts_spd_manifest.generated.txt b/spd/lp5/set-1/parts_spd_manifest.generated.txt
index 0401c008e0..11221ec42c 100644
--- a/spd/lp5/set-1/parts_spd_manifest.generated.txt
+++ b/spd/lp5/set-1/parts_spd_manifest.generated.txt
@@ -43,3 +43,4 @@ MT62F1G32D2DS-031RF WT:C,spd-3.hex
 MT62F2G32D4DS-031RF WT:C,spd-6.hex
 RS1G32LO5D2FDB-23BT,spd-11.hex
 BWMYAX32P8A-32G,spd-7.hex
+MT62F2G32D4DS-020 WT:D,spd-10.hex

From 8718db133af1f5abe789e6160460aeac37310219 Mon Sep 17 00:00:00 2001
From: Hualin Wei <weihualin@huaqin.corp-partner.google.com>
Date: Thu, 12 Feb 2026 12:45:53 +0800
Subject: [PATCH 3499/3886] mb/google/fatcat/var/lapis: Add 2 Micron modules to
 RAM id table

Add Micron MT62F1G32D2DS-020 WT:D  as id 1, and add Micron
MT62F2G32D4DS-020 WT:D as id 0, resulting in the list below:

DRAM Part Name                 ID to assign
H58G66CK8BX147                 0 (0000)
K3KL9L90EM-MGCU                0 (0000)
MT62F2G32D4DS-023 WT:C         0 (0000)
H58G56CK8BX146                 1 (0001)
K3KL8L80EM-MGCU                1 (0001)
MT62F1G32D2DS-023 WT:C         1 (0001)
K3KLALA0EM-MGCU                2 (0010)
MT62F1G32D2DS-020 WT:D         1 (0001)
MT62F2G32D4DS-020 WT:D         0 (0000)

BUG=b:488228474
TEST=emerge-fatcat coreboot, rework by EE
         flash it and boot normal.

Change-Id: I23ee56fe7e8f2e2ade75eaaf1fa19b91e784030f
Signed-off-by: Hualin Wei <weihualin@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91452
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com>
Reviewed-by: Pranava Y N <pranavayn@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/google/fatcat/variants/lapis/memory/Makefile.mk | 4 ++--
 .../google/fatcat/variants/lapis/memory/dram_id.generated.txt | 2 ++
 .../google/fatcat/variants/lapis/memory/mem_parts_used.txt    | 2 ++
 3 files changed, 6 insertions(+), 2 deletions(-)

diff --git a/src/mainboard/google/fatcat/variants/lapis/memory/Makefile.mk b/src/mainboard/google/fatcat/variants/lapis/memory/Makefile.mk
index 3580f944f9..05fac1eb69 100644
--- a/src/mainboard/google/fatcat/variants/lapis/memory/Makefile.mk
+++ b/src/mainboard/google/fatcat/variants/lapis/memory/Makefile.mk
@@ -4,6 +4,6 @@
 # util/spd_tools/bin/part_id_gen PTL lp5 src/mainboard/google/fatcat/variants/lapis/memory src/mainboard/google/fatcat/variants/lapis/memory/mem_parts_used.txt
 
 SPD_SOURCES =
-SPD_SOURCES += spd/lp5/set-0/spd-10.hex      # ID = 0(0b0000)  Parts = H58G66CK8BX147, K3KL9L90EM-MGCU, MT62F2G32D4DS-023 WT:C
-SPD_SOURCES += spd/lp5/set-0/spd-11.hex      # ID = 1(0b0001)  Parts = H58G56CK8BX146, K3KL8L80EM-MGCU, MT62F1G32D2DS-023 WT:C
+SPD_SOURCES += spd/lp5/set-0/spd-10.hex      # ID = 0(0b0000)  Parts = H58G66CK8BX147, K3KL9L90EM-MGCU, MT62F2G32D4DS-023 WT:C, MT62F2G32D4DS-020 WT:D
+SPD_SOURCES += spd/lp5/set-0/spd-11.hex      # ID = 1(0b0001)  Parts = H58G56CK8BX146, K3KL8L80EM-MGCU, MT62F1G32D2DS-023 WT:C, MT62F1G32D2DS-020 WT:D
 SPD_SOURCES += spd/lp5/set-0/spd-13.hex      # ID = 2(0b0010)  Parts = K3KLALA0EM-MGCU
diff --git a/src/mainboard/google/fatcat/variants/lapis/memory/dram_id.generated.txt b/src/mainboard/google/fatcat/variants/lapis/memory/dram_id.generated.txt
index 9d1f695535..cbb2a992c8 100644
--- a/src/mainboard/google/fatcat/variants/lapis/memory/dram_id.generated.txt
+++ b/src/mainboard/google/fatcat/variants/lapis/memory/dram_id.generated.txt
@@ -11,3 +11,5 @@ H58G56CK8BX146                 1 (0001)
 K3KL8L80EM-MGCU                1 (0001)
 MT62F1G32D2DS-023 WT:C         1 (0001)
 K3KLALA0EM-MGCU                2 (0010)
+MT62F1G32D2DS-020 WT:D         1 (0001)
+MT62F2G32D4DS-020 WT:D         0 (0000)
diff --git a/src/mainboard/google/fatcat/variants/lapis/memory/mem_parts_used.txt b/src/mainboard/google/fatcat/variants/lapis/memory/mem_parts_used.txt
index 332be8dc20..87fdf46aa6 100644
--- a/src/mainboard/google/fatcat/variants/lapis/memory/mem_parts_used.txt
+++ b/src/mainboard/google/fatcat/variants/lapis/memory/mem_parts_used.txt
@@ -16,3 +16,5 @@ H58G56CK8BX146
 K3KL8L80EM-MGCU
 MT62F1G32D2DS-023 WT:C
 K3KLALA0EM-MGCU
+MT62F1G32D2DS-020 WT:D
+MT62F2G32D4DS-020 WT:D

From 6be9ee7ce496afadc70f50e3b6864fa04b0aa909 Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Wed, 25 Feb 2026 08:02:09 -0600
Subject: [PATCH 3500/3886] mb/google/link: Use AZALIA_PIN_DESC macros for pin
 widgets
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Update the Creative CA0132 Pin Widget Verb Table from raw hex config
values to AZALIA_PIN_DESC for NIDs 0x0B–0x13, and use
AZALIA_PIN_CFG_NC(0) for N/C pins (0x0C–0x0F).

Mapping generated by hda-decoder utility.

TEST=build/boot LINK

Change-Id: Ia1c9bce2bf0a71aa3a60678828cbc6bc55f7bfc1
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91443
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
---
 src/mainboard/google/link/hda_verb.c | 53 +++++++++++++++++++++++-----
 1 file changed, 44 insertions(+), 9 deletions(-)

diff --git a/src/mainboard/google/link/hda_verb.c b/src/mainboard/google/link/hda_verb.c
index d3309cd6d7..07f88be305 100644
--- a/src/mainboard/google/link/hda_verb.c
+++ b/src/mainboard/google/link/hda_verb.c
@@ -72,31 +72,66 @@ const u32 cim_verb_data[] = {
 	AZALIA_SUBVENDOR(0, 0x10280550),
 
 	/* Pin Complex (NID 0x0B)  Port-G Analog Unknown  Speaker at Int N/A */
-	AZALIA_PIN_CFG(0, 0x0b, 0x901700f0),
+	AZALIA_PIN_CFG(0, 0x0b, AZALIA_PIN_DESC(
+		AZALIA_INTEGRATED,
+		AZALIA_INTERNAL,
+		AZALIA_SPEAKER,
+		AZALIA_OTHER_ANALOG,
+		AZALIA_COLOR_UNKNOWN,
+		AZALIA_JACK_PRESENCE_DETECT,
+		15, 0)),
 
 	/* Pin Complex (NID 0x0C)  N/C */
-	AZALIA_PIN_CFG(0, 0x0c, 0x70f000f0),
+	AZALIA_PIN_CFG(0, 0x0c, AZALIA_PIN_CFG_NC(0)),
 
 	/* Pin Complex (NID 0x0D)  N/C */
-	AZALIA_PIN_CFG(0, 0x0d, 0x70f000f0),
+	AZALIA_PIN_CFG(0, 0x0d, AZALIA_PIN_CFG_NC(0)),
 
 	/* Pin Complex (NID 0x0E)  N/C */
-	AZALIA_PIN_CFG(0, 0x0e, 0x70f000f0),
+	AZALIA_PIN_CFG(0, 0x0e, AZALIA_PIN_CFG_NC(0)),
 
 	/* Pin Complex (NID 0x0F)  N/C */
-	AZALIA_PIN_CFG(0, 0x0f, 0x70f000f0),
+	AZALIA_PIN_CFG(0, 0x0f, AZALIA_PIN_CFG_NC(0)),
 
 	/* Pin Complex (NID 0x10)  Port-D 1/8 Black HP Out at Ext Left */
-	AZALIA_PIN_CFG(0, 0x10, 0x032110f0),
+	AZALIA_PIN_CFG(0, 0x10, AZALIA_PIN_DESC(
+		AZALIA_JACK,
+		AZALIA_EXTERNAL_PRIMARY_CHASSIS | AZALIA_LEFT,
+		AZALIA_HP_OUT,
+		AZALIA_STEREO_MONO_1_8,
+		AZALIA_BLACK,
+		AZALIA_JACK_PRESENCE_DETECT,
+		15, 0)),
 
 	/* Pin Complex (NID 0x11) Port-B Click Mic */
-	AZALIA_PIN_CFG(0, 0x11, 0x90a700f0),
+	AZALIA_PIN_CFG(0, 0x11, AZALIA_PIN_DESC(
+		AZALIA_INTEGRATED,
+		AZALIA_INTERNAL,
+		AZALIA_MIC_IN,
+		AZALIA_OTHER_ANALOG,
+		AZALIA_COLOR_UNKNOWN,
+		AZALIA_JACK_PRESENCE_DETECT,
+		15, 0)),
 
 	/* Pin Complex (NID 0x12) Port-C Combo Jack Mic or D-Mic */
-	AZALIA_PIN_CFG(0, 0x12, 0x03a110f0),
+	AZALIA_PIN_CFG(0, 0x12, AZALIA_PIN_DESC(
+		AZALIA_JACK,
+		AZALIA_EXTERNAL_PRIMARY_CHASSIS | AZALIA_LEFT,
+		AZALIA_MIC_IN,
+		AZALIA_STEREO_MONO_1_8,
+		AZALIA_BLACK,
+		AZALIA_JACK_PRESENCE_DETECT,
+		15, 0)),
 
 	/* Pin Complex (NID 0x13) What you hear */
-	AZALIA_PIN_CFG(0, 0x13, 0x90d600f0),
+	AZALIA_PIN_CFG(0, 0x13, AZALIA_PIN_DESC(
+		AZALIA_INTEGRATED,
+		AZALIA_INTERNAL,
+		AZALIA_DIGITAL_OTHER_IN,
+		AZALIA_OTHER_DIGITAL,
+		AZALIA_COLOR_UNKNOWN,
+		AZALIA_JACK_PRESENCE_DETECT,
+		15, 0)),
 
 	/* coreboot specific header */
 	0x80862806,	// Codec Vendor / Device ID: Intel CougarPoint HDMI

From 57f96b83fe5fd58a72c29dba63d8dec96796f026 Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Wed, 25 Feb 2026 08:08:55 -0600
Subject: [PATCH 3501/3886] mb/google/link/hda_verb: Remove presence detect
 flag from internal sources

The pin widgets for the internal speakers and microphone should not
have the presence detect flag set, as this causes the jack detect
to fail on some distros, leading to headphone output not working.

TEST=build/boot LINK

Change-Id: I798d0cc4a0f4de65ebe51f1dafaeeb12728d2f40
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91444
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
---
 src/mainboard/google/link/hda_verb.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/mainboard/google/link/hda_verb.c b/src/mainboard/google/link/hda_verb.c
index 07f88be305..7199e5a6f1 100644
--- a/src/mainboard/google/link/hda_verb.c
+++ b/src/mainboard/google/link/hda_verb.c
@@ -78,7 +78,7 @@ const u32 cim_verb_data[] = {
 		AZALIA_SPEAKER,
 		AZALIA_OTHER_ANALOG,
 		AZALIA_COLOR_UNKNOWN,
-		AZALIA_JACK_PRESENCE_DETECT,
+		AZALIA_NO_JACK_PRESENCE_DETECT,
 		15, 0)),
 
 	/* Pin Complex (NID 0x0C)  N/C */
@@ -110,7 +110,7 @@ const u32 cim_verb_data[] = {
 		AZALIA_MIC_IN,
 		AZALIA_OTHER_ANALOG,
 		AZALIA_COLOR_UNKNOWN,
-		AZALIA_JACK_PRESENCE_DETECT,
+		AZALIA_NO_JACK_PRESENCE_DETECT,
 		15, 0)),
 
 	/* Pin Complex (NID 0x12) Port-C Combo Jack Mic or D-Mic */

From 416875e93ee71bcc53079146873ebb5635497c70 Mon Sep 17 00:00:00 2001
From: Patrick Rudolph <patrick.rudolph@9elements.com>
Date: Sun, 15 Feb 2026 12:54:31 +0100
Subject: [PATCH 3502/3886] mb/lenovo/t430|t530: Reduces differences in code

Make the T430 look like the T530 codebase by reordering includes,
update the ACPI code and update the CMOS defaults file. Should have
not influence on functionality, but changes the TIMELESS build artifacts.

Change-Id: I2c300ecbf44fa950183ee5e05ba1e05cdf5ff00d
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91281
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
---
 src/mainboard/lenovo/t430/cmos.default |  2 +-
 src/mainboard/lenovo/t430/cmos.layout  |  1 +
 src/mainboard/lenovo/t430/dsdt.asl     | 17 +++++++++++------
 src/mainboard/lenovo/t430/smihandler.c |  2 +-
 src/mainboard/lenovo/t530/early_init.c |  5 ++---
 5 files changed, 16 insertions(+), 11 deletions(-)

diff --git a/src/mainboard/lenovo/t430/cmos.default b/src/mainboard/lenovo/t430/cmos.default
index c896eadec1..4857f92f67 100644
--- a/src/mainboard/lenovo/t430/cmos.default
+++ b/src/mainboard/lenovo/t430/cmos.default
@@ -15,6 +15,6 @@ fn_ctrl_swap=Disable
 sticky_fn=Disable
 trackpoint=Enable
 backlight=Both
-usb_always_on=Disable
 hybrid_graphics_mode=Integrated Only
+usb_always_on=Disable
 me_state=Normal
diff --git a/src/mainboard/lenovo/t430/cmos.layout b/src/mainboard/lenovo/t430/cmos.layout
index 3e48df5584..d109a61b4e 100644
--- a/src/mainboard/lenovo/t430/cmos.layout
+++ b/src/mainboard/lenovo/t430/cmos.layout
@@ -41,6 +41,7 @@ entries
 # coreboot config options: northbridge
 432	3	e	11	gfx_uma_size
 435	2	e	12	hybrid_graphics_mode
+
 440	8	h	0	volume
 
 # VBOOT
diff --git a/src/mainboard/lenovo/t430/dsdt.asl b/src/mainboard/lenovo/t430/dsdt.asl
index 795f9a1ee9..1134782675 100644
--- a/src/mainboard/lenovo/t430/dsdt.asl
+++ b/src/mainboard/lenovo/t430/dsdt.asl
@@ -11,24 +11,29 @@ DefinitionBlock(
 	ACPI_DSDT_REV_2,
 	OEM_ID,
 	ACPI_TABLE_CREATOR,
-	0x20141018	// OEM revision
+	0x20110725	// OEM revision
 )
 {
 	#include <acpi/dsdt_top.asl>
-	#include "acpi/platform.asl"
-	#include <cpu/intel/common/acpi/cpu.asl>
 	#include <southbridge/intel/common/acpi/platform.asl>
-	/* global NVS and variables. */
+
+	#include "acpi/platform.asl"
+
+	// global NVS and variables
 	#include <southbridge/intel/bd82x6x/acpi/globalnvs.asl>
-	#include <southbridge/intel/common/acpi/sleepstates.asl>
+
+	#include <cpu/intel/common/acpi/cpu.asl>
 
 	Scope (\_SB) {
 		Device (PCI0)
 		{
 			#include <northbridge/intel/sandybridge/acpi/sandybridge.asl>
-			#include <drivers/intel/gma/acpi/default_brightness_levels.asl>
 			#include <southbridge/intel/bd82x6x/acpi/pch.asl>
+
+			#include <drivers/intel/gma/acpi/default_brightness_levels.asl>
 		}
 	}
+
+	#include <southbridge/intel/common/acpi/sleepstates.asl>
 	#include <ec/lenovo/h8/acpi/thinklight.asl>
 }
diff --git a/src/mainboard/lenovo/t430/smihandler.c b/src/mainboard/lenovo/t430/smihandler.c
index 81cbc487f6..03c899e0d9 100644
--- a/src/mainboard/lenovo/t430/smihandler.c
+++ b/src/mainboard/lenovo/t430/smihandler.c
@@ -5,8 +5,8 @@
 #include <cpu/x86/smm.h>
 #include <ec/acpi/ec.h>
 #include <ec/lenovo/h8/h8.h>
-#include <southbridge/intel/bd82x6x/pch.h>
 #include <southbridge/intel/common/pmutil.h>
+#include <southbridge/intel/bd82x6x/pch.h>
 
 #define GPE_EC_SCI	1
 #define GPE_EC_WAKE	13
diff --git a/src/mainboard/lenovo/t530/early_init.c b/src/mainboard/lenovo/t530/early_init.c
index b7bc35adbb..d982660856 100644
--- a/src/mainboard/lenovo/t530/early_init.c
+++ b/src/mainboard/lenovo/t530/early_init.c
@@ -1,12 +1,11 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
-#include <types.h>
-#include <device/device.h>
 #include <device/pci_ops.h>
 #include <device/pci_def.h>
+#include <ec/lenovo/pmh7/pmh7.h>
 #include <drivers/i2c/at24rf08c/lenovo.h>
-#include <northbridge/intel/sandybridge/sandybridge.h>
 #include <drivers/lenovo/hybrid_graphics/hybrid_graphics.h>
+#include <northbridge/intel/sandybridge/sandybridge.h>
 
 static void hybrid_graphics_init(void)
 {

From 3a5e4660bbf735dd2a2b65cc6032828b8dbfe00a Mon Sep 17 00:00:00 2001
From: Patrick Rudolph <patrick.rudolph@9elements.com>
Date: Sun, 15 Feb 2026 13:39:44 +0100
Subject: [PATCH 3503/3886] mb/lenovo/t530: Unify GEN_DEC entries

Use the same GEN_DEC ranges as on t430. This makes the code look more
similar, but doesn't change the functionality. It changes the TIMELESS
build artifact.

Change-Id: Ibfac61f615fba2b91101125a2187b45af6dadd19
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91283
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/lenovo/t530/devicetree.cb | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/src/mainboard/lenovo/t530/devicetree.cb b/src/mainboard/lenovo/t530/devicetree.cb
index 13c40d91d4..944de3dd49 100644
--- a/src/mainboard/lenovo/t530/devicetree.cb
+++ b/src/mainboard/lenovo/t530/devicetree.cb
@@ -35,9 +35,9 @@ chip northbridge/intel/sandybridge
 			# Set max SATA speed to 6.0 Gb/s
 			register "sata_interface_speed_support" = "0x3"
 
-			register "gen1_dec" = "0x7c1601"
-			register "gen2_dec" = "0x0c15e1"
-			register "gen4_dec" = "0x0c06a1"
+			register "gen1_dec" = "0x00c15e1"
+			register "gen2_dec" = "0x07c1601"
+			register "gen3_dec" = "0x00c06a1"
 
 			# Enable zero-based linear PCIe root port functions
 			register "pcie_port_coalesce" = "true"

From 091ae533b9fdb5b78a5edbc2b68c2faee083f1dd Mon Sep 17 00:00:00 2001
From: Patrick Rudolph <patrick.rudolph@9elements.com>
Date: Sun, 15 Feb 2026 13:23:02 +0100
Subject: [PATCH 3504/3886] mb/lenovo/t430: Merge into t430 into t530

Both models are quite similar, so reuse existing code and reduce
code duplication.

TEST=TIMELESS build shows identical devicetree.cb, DSDT, cmos layout,
     bootblock, romstage and postcar stages. ramstage shows minor
     differences as static.c is now build before hda_verb.c, resulting
     in different location of data symbols. Binary analysis shows that
     the data itself didn't change, just the position in the final
     binary.

Change-Id: I2e7cf67c9e2542a199b11257e7349a55e0518aac
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91285
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
---
 src/mainboard/lenovo/t430/Kconfig             |  80 ---------
 src/mainboard/lenovo/t430/Kconfig.name        |   4 -
 src/mainboard/lenovo/t430/Makefile.mk         |   8 -
 src/mainboard/lenovo/t430/acpi/ec.asl         |   4 -
 src/mainboard/lenovo/t430/acpi/platform.asl   |  23 ---
 src/mainboard/lenovo/t430/acpi/superio.asl    |   3 -
 src/mainboard/lenovo/t430/acpi_tables.c       |  15 --
 src/mainboard/lenovo/t430/board_info.txt      |   6 -
 src/mainboard/lenovo/t430/cmos.default        |  20 ---
 src/mainboard/lenovo/t430/cmos.layout         | 108 ------------
 src/mainboard/lenovo/t430/devicetree.cb       | 166 ------------------
 src/mainboard/lenovo/t430/dsdt.asl            |  39 ----
 src/mainboard/lenovo/t430/early_init.c        |  40 -----
 src/mainboard/lenovo/t430/gma-mainboard.ads   |  22 ---
 src/mainboard/lenovo/t430/mainboard.c         |  15 --
 src/mainboard/lenovo/t430/smihandler.c        |  68 -------
 .../lenovo/t430/vboot-ro-me_clean.fmd         |  21 ---
 src/mainboard/lenovo/t430/vboot-ro.fmd        |  21 ---
 src/mainboard/lenovo/t430/vboot-rwab.fmd      |  35 ----
 src/mainboard/lenovo/t530/Kconfig             |   7 +
 src/mainboard/lenovo/t530/Kconfig.name        |   3 +
 src/mainboard/lenovo/t530/Makefile.mk         |   1 +
 .../lenovo/{ => t530/variants}/t430/data.vbt  | Bin
 .../lenovo/{ => t530/variants}/t430/gpio.c    |   0
 .../{ => t530/variants}/t430/hda_verb.c       |   0
 .../lenovo/t530/variants/t430/overridetree.cb |  58 ++++++
 .../t530/{ => variants/t530}/hda_verb.c       |   0
 .../lenovo/t530/variants/w530/hda_verb.c      |  75 ++++++++
 28 files changed, 144 insertions(+), 698 deletions(-)
 delete mode 100644 src/mainboard/lenovo/t430/Kconfig
 delete mode 100644 src/mainboard/lenovo/t430/Kconfig.name
 delete mode 100644 src/mainboard/lenovo/t430/Makefile.mk
 delete mode 100644 src/mainboard/lenovo/t430/acpi/ec.asl
 delete mode 100644 src/mainboard/lenovo/t430/acpi/platform.asl
 delete mode 100644 src/mainboard/lenovo/t430/acpi/superio.asl
 delete mode 100644 src/mainboard/lenovo/t430/acpi_tables.c
 delete mode 100644 src/mainboard/lenovo/t430/board_info.txt
 delete mode 100644 src/mainboard/lenovo/t430/cmos.default
 delete mode 100644 src/mainboard/lenovo/t430/cmos.layout
 delete mode 100644 src/mainboard/lenovo/t430/devicetree.cb
 delete mode 100644 src/mainboard/lenovo/t430/dsdt.asl
 delete mode 100644 src/mainboard/lenovo/t430/early_init.c
 delete mode 100644 src/mainboard/lenovo/t430/gma-mainboard.ads
 delete mode 100644 src/mainboard/lenovo/t430/mainboard.c
 delete mode 100644 src/mainboard/lenovo/t430/smihandler.c
 delete mode 100644 src/mainboard/lenovo/t430/vboot-ro-me_clean.fmd
 delete mode 100644 src/mainboard/lenovo/t430/vboot-ro.fmd
 delete mode 100644 src/mainboard/lenovo/t430/vboot-rwab.fmd
 rename src/mainboard/lenovo/{ => t530/variants}/t430/data.vbt (100%)
 rename src/mainboard/lenovo/{ => t530/variants}/t430/gpio.c (100%)
 rename src/mainboard/lenovo/{ => t530/variants}/t430/hda_verb.c (100%)
 create mode 100644 src/mainboard/lenovo/t530/variants/t430/overridetree.cb
 rename src/mainboard/lenovo/t530/{ => variants/t530}/hda_verb.c (100%)
 create mode 100644 src/mainboard/lenovo/t530/variants/w530/hda_verb.c

diff --git a/src/mainboard/lenovo/t430/Kconfig b/src/mainboard/lenovo/t430/Kconfig
deleted file mode 100644
index 2b6eb17e9c..0000000000
--- a/src/mainboard/lenovo/t430/Kconfig
+++ /dev/null
@@ -1,80 +0,0 @@
-## SPDX-License-Identifier: GPL-2.0-only
-
-if BOARD_LENOVO_THINKPAD_T430
-
-config BOARD_SPECIFIC_OPTIONS
-	def_bool y
-	select AZALIA_USE_LEGACY_VERB_TABLE
-	select BOARD_ROMSIZE_KB_12288
-	select DRIVERS_LENOVO_HYBRID_GRAPHICS
-	select DRIVER_LENOVO_SERIALS
-	select DRIVER_LENOVO_SERIALS_EARLY_LOCK
-	select DRIVERS_RICOH_RCE822
-	select EC_LENOVO_H8
-	select EC_LENOVO_PMH7
-	select GFX_GMA_PANEL_1_ON_LVDS
-	select H8_HAS_BAT_THRESHOLDS_IMPL
-	select H8_HAS_BDC_GPIO_DETECTION
-	select H8_HAS_WWAN_GPIO_DETECTION
-	select HAVE_ACPI_RESUME
-	select HAVE_ACPI_TABLES
-	select HAVE_CMOS_DEFAULT
-	select HAVE_OPTION_TABLE
-	select INTEL_GMA_HAVE_VBT
-	select INTEL_INT15
-	select MAINBOARD_HAS_LIBGFXINIT
-	select MAINBOARD_HAS_TPM1
-	select MAINBOARD_USES_IFD_GBE_REGION
-	select MEMORY_MAPPED_TPM
-	select NO_UART_ON_SUPERIO
-	select NORTHBRIDGE_INTEL_SANDYBRIDGE
-	select SERIRQ_CONTINUOUS_MODE
-	select SOUTHBRIDGE_INTEL_C216
-	select SYSTEM_TYPE_LAPTOP
-	select USE_NATIVE_RAMINIT
-
-config VBOOT
-	select GBB_FLAG_DISABLE_EC_SOFTWARE_SYNC
-	select GBB_FLAG_DISABLE_FWMP
-	select GBB_FLAG_DISABLE_LID_SHUTDOWN
-	select GBB_FLAG_DISABLE_PD_SOFTWARE_SYNC
-	select HAS_RECOVERY_MRC_CACHE
-	select VBOOT_VBNV_FLASH
-
-config VBOOT_SLOTS_RW_AB
-	default y
-
-config CBFS_SIZE
-	default 0x700000
-
-config FMDFILE
-	default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/vboot-rwab.fmd" if VBOOT
-
-config MAINBOARD_DIR
-	default "lenovo/t430"
-
-config MAINBOARD_PART_NUMBER
-	default "ThinkPad T430"
-
-config VGA_BIOS_ID
-	string
-	default "8086,0166"
-
-config DRAM_RESET_GATE_GPIO
-	int
-	default 10
-
-config USBDEBUG_HCD_INDEX
-	int
-	default 2
-
-config PS2K_EISAID
-	default "PNP0303"
-
-config PS2M_EISAID
-	default "LEN0015"
-
-config THINKPADEC_HKEY_EISAID
-	default "LEN0068"
-
-endif
diff --git a/src/mainboard/lenovo/t430/Kconfig.name b/src/mainboard/lenovo/t430/Kconfig.name
deleted file mode 100644
index f14a1a2d78..0000000000
--- a/src/mainboard/lenovo/t430/Kconfig.name
+++ /dev/null
@@ -1,4 +0,0 @@
-## SPDX-License-Identifier: GPL-2.0-only
-
-config BOARD_LENOVO_THINKPAD_T430
-	bool "ThinkPad T430"
diff --git a/src/mainboard/lenovo/t430/Makefile.mk b/src/mainboard/lenovo/t430/Makefile.mk
deleted file mode 100644
index e4b6fbf0f0..0000000000
--- a/src/mainboard/lenovo/t430/Makefile.mk
+++ /dev/null
@@ -1,8 +0,0 @@
-## SPDX-License-Identifier: GPL-2.0-only
-
-bootblock-y += gpio.c
-romstage-y += gpio.c
-
-ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads
-bootblock-y += early_init.c
-romstage-y += early_init.c
diff --git a/src/mainboard/lenovo/t430/acpi/ec.asl b/src/mainboard/lenovo/t430/acpi/ec.asl
deleted file mode 100644
index 987593e919..0000000000
--- a/src/mainboard/lenovo/t430/acpi/ec.asl
+++ /dev/null
@@ -1,4 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <ec/lenovo/h8/acpi/ec.asl>
-#include <ec/lenovo/h8/acpi/thinkpad_bat_thresholds_b0.asl>
diff --git a/src/mainboard/lenovo/t430/acpi/platform.asl b/src/mainboard/lenovo/t430/acpi/platform.asl
deleted file mode 100644
index 9dee90edc3..0000000000
--- a/src/mainboard/lenovo/t430/acpi/platform.asl
+++ /dev/null
@@ -1,23 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-/* The _PTS method (Prepare To Sleep) is called before the OS is
- * entering a sleep state. The sleep state number is passed in Arg0
- */
-
-Method(_PTS,1)
-{
-	\_SB.PCI0.LPCB.EC.MUTE(1)
-	\_SB.PCI0.LPCB.EC.USBP(0)
-	\_SB.PCI0.LPCB.EC.RADI(0)
-}
-
-/* The _WAK method is called on system wakeup */
-
-Method(_WAK,1)
-{
-	/* Wake the HKEY to init BT/WWAN */
-	\_SB.PCI0.LPCB.EC.HKEY.WAKE (Arg0)
-
-	/* Not implemented. */
-	Return(Package(){0,0})
-}
diff --git a/src/mainboard/lenovo/t430/acpi/superio.asl b/src/mainboard/lenovo/t430/acpi/superio.asl
deleted file mode 100644
index ee2eabeb75..0000000000
--- a/src/mainboard/lenovo/t430/acpi/superio.asl
+++ /dev/null
@@ -1,3 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-or-later */
-
-#include <drivers/pc80/pc/ps2_controller.asl>
diff --git a/src/mainboard/lenovo/t430/acpi_tables.c b/src/mainboard/lenovo/t430/acpi_tables.c
deleted file mode 100644
index 36d3e85c1e..0000000000
--- a/src/mainboard/lenovo/t430/acpi_tables.c
+++ /dev/null
@@ -1,15 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <acpi/acpi_gnvs.h>
-#include <soc/nvs.h>
-
-void mainboard_fill_gnvs(struct global_nvs *gnvs)
-{
-	/* The lid is open by default */
-	gnvs->lids = 1;
-
-	/* Temperature at which OS will shutdown */
-	gnvs->tcrt = 100;
-	/* Temperature at which OS will throttle CPU */
-	gnvs->tpsv = 90;
-}
diff --git a/src/mainboard/lenovo/t430/board_info.txt b/src/mainboard/lenovo/t430/board_info.txt
deleted file mode 100644
index 09ddde1f85..0000000000
--- a/src/mainboard/lenovo/t430/board_info.txt
+++ /dev/null
@@ -1,6 +0,0 @@
-Category: laptop
-ROM package: SOIC-8
-ROM protocol: SPI
-ROM socketed: n
-Flashrom support: n
-Release year: 2012
diff --git a/src/mainboard/lenovo/t430/cmos.default b/src/mainboard/lenovo/t430/cmos.default
deleted file mode 100644
index 4857f92f67..0000000000
--- a/src/mainboard/lenovo/t430/cmos.default
+++ /dev/null
@@ -1,20 +0,0 @@
-## SPDX-License-Identifier: GPL-2.0-only
-
-boot_option=Fallback
-debug_level=Debug
-power_on_after_fail=Disable
-nmi=Enable
-volume=0x3
-first_battery=Primary
-bluetooth=Enable
-wwan=Enable
-wlan=Enable
-touchpad=Enable
-sata_mode=AHCI
-fn_ctrl_swap=Disable
-sticky_fn=Disable
-trackpoint=Enable
-backlight=Both
-hybrid_graphics_mode=Integrated Only
-usb_always_on=Disable
-me_state=Normal
diff --git a/src/mainboard/lenovo/t430/cmos.layout b/src/mainboard/lenovo/t430/cmos.layout
deleted file mode 100644
index d109a61b4e..0000000000
--- a/src/mainboard/lenovo/t430/cmos.layout
+++ /dev/null
@@ -1,108 +0,0 @@
-## SPDX-License-Identifier: GPL-2.0-only
-
-# -----------------------------------------------------------------
-entries
-
-# -----------------------------------------------------------------
-0	120	r	0	reserved_memory
-
-# -----------------------------------------------------------------
-# RTC_BOOT_BYTE (coreboot hardcoded)
-384	1	e	4	boot_option
-388	4	h	0	reboot_counter
-
-# -----------------------------------------------------------------
-# coreboot config options: console
-395	4	e	6	debug_level
-
-#400	8	r	0	reserved for century byte
-
-# coreboot config options: southbridge
-408	1	e	1	nmi
-409	2	e	7	power_on_after_fail
-
-# coreboot config options: EC
-411	1	e	8	first_battery
-412	1	e	1	bluetooth
-413	1	e	1	wwan
-414	1	e	1	touchpad
-415	1	e	1	wlan
-416	1	e	1	trackpoint
-417	1	e	1	fn_ctrl_swap
-418	1	e	1	sticky_fn
-419	2	e	13	usb_always_on
-421	1	e	9	sata_mode
-422	2	e	10	backlight
-
-# coreboot config options: ME
-424	1	e	14	me_state
-425	2	h	0	me_state_prev
-
-# coreboot config options: northbridge
-432	3	e	11	gfx_uma_size
-435	2	e	12	hybrid_graphics_mode
-
-440	8	h	0	volume
-
-# VBOOT
-448	128	r	0	vbnv
-
-# SandyBridge MRC Scrambler Seed values
-896	32	r	0	mrc_scrambler_seed
-928	32	r	0	mrc_scrambler_seed_s3
-960	16	r	0	mrc_scrambler_seed_chk
-
-# coreboot config options: check sums
-984	16	h	0	check_sum
-
-# -----------------------------------------------------------------
-
-enumerations
-
-#ID	value	text
-1	0	Disable
-1	1	Enable
-2	0	Enable
-2	1	Disable
-4	0	Fallback
-4	1	Normal
-6	0	Emergency
-6	1	Alert
-6	2	Critical
-6	3	Error
-6	4	Warning
-6	5	Notice
-6	6	Info
-6	7	Debug
-6	8	Spew
-7	0	Disable
-7	1	Enable
-7	2	Keep
-8	0	Secondary
-8	1	Primary
-9	0	AHCI
-9	1	Compatible
-10	0	Both
-10	1	Keyboard only
-10	2	Thinklight only
-10	3	None
-11	0	32M
-11	1	64M
-11	2	96M
-11	3	128M
-11	4	160M
-11	5	192M
-11	6	224M
-12	0	Integrated Only
-12	1	Discrete Only
-12	2	Dual Graphics
-13	0	Disable
-13	1	AC and battery
-13	2	AC only
-14	0	Normal
-14	1	Disabled
-
-# -----------------------------------------------------------------
-checksums
-
-checksum 392 447 984
diff --git a/src/mainboard/lenovo/t430/devicetree.cb b/src/mainboard/lenovo/t430/devicetree.cb
deleted file mode 100644
index 198900b399..0000000000
--- a/src/mainboard/lenovo/t430/devicetree.cb
+++ /dev/null
@@ -1,166 +0,0 @@
-chip northbridge/intel/sandybridge
-	register "gfx" = "GMA_STATIC_DISPLAYS(1)"
-
-	# Enable DisplayPort Hotplug with 6ms pulse
-	register "gpu_dp_d_hotplug" = "0x06"
-
-	# Enable Panel as LVDS and configure power delays
-	register "gpu_panel_port_select" = "PANEL_PORT_LVDS"
-	register "gpu_panel_power_cycle_delay" = "6"		# T7: 500ms
-	register "gpu_panel_power_up_delay" = "100"		# T1+T2: 10ms
-	register "gpu_panel_power_down_delay" = "100"		# T5+T6: 10ms
-	register "gpu_panel_power_backlight_on_delay" = "2100"	# T3: 210ms
-	register "gpu_panel_power_backlight_off_delay" = "2100"	# T4: 210ms
-	register "gpu_cpu_backlight" = "0x1155"
-	register "gpu_pch_backlight" = "0x11551155"
-
-	register "spd_addresses" = "{0x50, 0, 0x51, 0}"
-
-	device domain 0 on
-		subsystemid 0x17aa 0x21f3 inherit
-
-		chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH
-			register "docking_supported" = "true"
-			register "gen1_dec" = "0x000c15e1"
-			register "gen2_dec" = "0x007c1601"
-			register "gen3_dec" = "0x000c06a1"
-			register "gpi13_routing" = "2"
-			register "gpi1_routing" = "2"
-			register "pcie_hotplug_map" = "{ 0, 0, 1, 0, 0, 0, 0, 0 }"
-			register "pcie_port_coalesce" = "true"
-			register "sata_interface_speed_support" = "0x3"
-			register "sata_port_map" = "0x17"
-
-			# Do not enable xHCI Port 4 since WWAN USB is EHCI-only
-			register "superspeed_capable_ports" = "0x7"
-			register "xhci_switchable_ports" = "0x7"
-			register "usb_port_config" = "{
-				{ 1, 1,  0 },
-				{ 1, 1,  1 },
-				{ 1, 2,  3 },
-				{ 1, 1, -1 },
-				{ 1, 1,  2 },
-				{ 1, 0, -1 },
-				{ 0, 0, -1 },
-				{ 1, 2, -1 },
-				{ 1, 0, -1 },
-				{ 1, 1,  5 },
-				{ 1, 0, -1 },
-				{ 1, 0, -1 },
-				{ 1, 3, -1 },
-				{ 1, 1, -1 }
-			}"
-
-			# device specific SPI configuration
-			register "spi_uvscc" = "0x2005"
-			register "spi_lvscc" = "0x2005"
-
-			device ref xhci on end # USB 3.0 Controller
-			device ref mei1 on end # Management Engine Interface 1
-			device ref mei2 off end # Management Engine Interface 2
-			device ref me_ide_r off end # Management Engine IDE-R
-			device ref me_kt off end # Management Engine KT
-			device ref gbe on end # Intel Gigabit Ethernet
-			device ref ehci2 on end # USB2 EHCI #2
-			device ref hda on end # High Definition Audio controller
-			device ref pcie_rp1 on # PCIe Port #1
-				chip drivers/ricoh/rce822 # Ricoh cardreader
-					register "disable_mask" = "0x87"
-					register "sdwppol" = "1"
-					device pci 00.0 on end # Ricoh SD card reader
-				end
-			end
-			device ref pcie_rp2 on end # PCIe Port #2
-			device ref pcie_rp3 on # PCIe Port #3
-				smbios_slot_desc "7" "3" "ExpressCard Slot" "8"
-			end
-			device ref pcie_rp4 off end # PCIe Port #4
-			device ref pcie_rp5 off end # PCIe Port #5
-			device ref pcie_rp6 off end # PCIe Port #6
-			device ref pcie_rp7 off end # PCIe Port #7
-			device ref pcie_rp8 off end # PCIe Port #8
-			device ref ehci1 on end # USB2 EHCI #1
-			device ref pci_bridge off end # PCI bridge
-			device ref lpc on # LPC bridge PCI-LPC bridge
-				chip ec/lenovo/pmh7
-					register "backlight_enable" = "true"
-					register "dock_event_enable" = "true"
-					device pnp ff.1 on end # dummy
-				end
-				chip drivers/pc80/tpm
-					device pnp 0c31.0 on end
-				end
-				chip ec/lenovo/h8
-					device pnp ff.2 on # dummy
-						io 0x60 = 0x62
-						io 0x62 = 0x66
-						io 0x64 = 0x1600
-						io 0x66 = 0x1604
-					end
-					register "config0" = "0xa7"
-					register "config1" = "0x01"
-					register "config2" = "0xa0"
-					register "config3" = "0xe2"
-
-					register "has_keyboard_backlight" = "0"
-
-					register "beepmask0" = "0x02"
-					register "beepmask1" = "0x86"
-					register "has_power_management_beeps" = "1"
-					register "event2_enable" = "0xff"
-					register "event3_enable" = "0xff"
-					register "event4_enable" = "0xf0"
-					register "event5_enable" = "0x3c"
-					register "event6_enable" = "0x00"
-					register "event7_enable" = "0xa1"
-					register "event8_enable" = "0x7b"
-					register "event9_enable" = "0xff"
-					register "eventa_enable" = "0x00"
-					register "eventb_enable" = "0x00"
-					register "eventc_enable" = "0xff"
-					register "eventd_enable" = "0xff"
-					register "evente_enable" = "0x0d"
-
-					register "bdc_gpio_num" = "54"
-					register "bdc_gpio_lvl" = "0"
-
-					register "wwan_gpio_num" = "70"
-					register "wwan_gpio_lvl" = "0"
-				end
-				chip drivers/lenovo/hybrid_graphics
-					device pnp ff.f on end # dummy
-
-					register "detect_gpio" = "21"
-
-					register "has_panel_hybrid_gpio" = "true"
-					register "panel_hybrid_gpio" = "52"
-					register "panel_integrated_lvl" = "true"
-
-					register "has_backlight_gpio" = "false"
-					register "has_dgpu_power_gpio" = "false"
-
-					register "has_thinker1" = "true"
-				end
-			end
-			device ref sata1 on end # SATA Controller 1
-			device ref smbus on # SMBus
-				chip drivers/i2c/at24rf08c # eeprom, 8 virtual devices, same chip
-					device i2c 54 on end
-					device i2c 55 on end
-					device i2c 56 on end
-					device i2c 57 on end
-					device i2c 5c on end
-					device i2c 5d on end
-					device i2c 5e on end
-					device i2c 5f on end
-				end
-			end
-			device ref sata2 off end # SATA Controller 2
-			device ref thermal off end # Thermal
-		end
-		device ref host_bridge on end # Host bridge Host bridge
-		device ref peg10 on end # PCIe Bridge for discrete graphics
-		device ref igd on end # Internal graphics VGA controller
-		device ref dev4 off end # Signal processing controller
-	end
-end
diff --git a/src/mainboard/lenovo/t430/dsdt.asl b/src/mainboard/lenovo/t430/dsdt.asl
deleted file mode 100644
index 1134782675..0000000000
--- a/src/mainboard/lenovo/t430/dsdt.asl
+++ /dev/null
@@ -1,39 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#define THINKPAD_EC_GPE 17
-#define BRIGHTNESS_UP \_SB.PCI0.GFX0.INCB
-#define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.DECB
-
-#include <acpi/acpi.h>
-DefinitionBlock(
-	"dsdt.aml",
-	"DSDT",
-	ACPI_DSDT_REV_2,
-	OEM_ID,
-	ACPI_TABLE_CREATOR,
-	0x20110725	// OEM revision
-)
-{
-	#include <acpi/dsdt_top.asl>
-	#include <southbridge/intel/common/acpi/platform.asl>
-
-	#include "acpi/platform.asl"
-
-	// global NVS and variables
-	#include <southbridge/intel/bd82x6x/acpi/globalnvs.asl>
-
-	#include <cpu/intel/common/acpi/cpu.asl>
-
-	Scope (\_SB) {
-		Device (PCI0)
-		{
-			#include <northbridge/intel/sandybridge/acpi/sandybridge.asl>
-			#include <southbridge/intel/bd82x6x/acpi/pch.asl>
-
-			#include <drivers/intel/gma/acpi/default_brightness_levels.asl>
-		}
-	}
-
-	#include <southbridge/intel/common/acpi/sleepstates.asl>
-	#include <ec/lenovo/h8/acpi/thinklight.asl>
-}
diff --git a/src/mainboard/lenovo/t430/early_init.c b/src/mainboard/lenovo/t430/early_init.c
deleted file mode 100644
index d982660856..0000000000
--- a/src/mainboard/lenovo/t430/early_init.c
+++ /dev/null
@@ -1,40 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <device/pci_ops.h>
-#include <device/pci_def.h>
-#include <ec/lenovo/pmh7/pmh7.h>
-#include <drivers/i2c/at24rf08c/lenovo.h>
-#include <drivers/lenovo/hybrid_graphics/hybrid_graphics.h>
-#include <northbridge/intel/sandybridge/sandybridge.h>
-
-static void hybrid_graphics_init(void)
-{
-	bool peg, igd;
-	u32 reg32;
-
-	early_hybrid_graphics(&igd, &peg);
-
-	if (peg && igd)
-		return;
-
-	/* Hide disabled devices */
-	reg32 = pci_read_config32(PCI_DEV(0, 0, 0), DEVEN);
-	reg32 &= ~(DEVEN_PEG10 | DEVEN_IGD);
-
-	if (peg)
-		reg32 |= DEVEN_PEG10;
-
-	if (igd)
-		reg32 |= DEVEN_IGD;
-	else
-		/* Disable IGD VGA decode, no GTT or GFX stolen */
-		pci_write_config16(PCI_DEV(0, 0, 0), GGC, 2);
-
-	pci_write_config32(PCI_DEV(0, 0, 0), DEVEN, reg32);
-}
-
-void mainboard_early_init(bool s3resume)
-{
-	hybrid_graphics_init();
-	lenovo_mainboard_eeprom_lock();
-}
diff --git a/src/mainboard/lenovo/t430/gma-mainboard.ads b/src/mainboard/lenovo/t430/gma-mainboard.ads
deleted file mode 100644
index 3df1e37f3e..0000000000
--- a/src/mainboard/lenovo/t430/gma-mainboard.ads
+++ /dev/null
@@ -1,22 +0,0 @@
--- SPDX-License-Identifier: GPL-2.0-or-later
-
-with HW.GFX.GMA;
-with HW.GFX.GMA.Display_Probing;
-
-use HW.GFX.GMA;
-use HW.GFX.GMA.Display_Probing;
-
-private package GMA.Mainboard is
-
-   ports : constant Port_List :=
-     (DP1,
-      DP2,
-      DP3,
-      HDMI1,
-      HDMI2,
-      HDMI3,
-      Analog,
-      LVDS,
-      others => Disabled);
-
-end GMA.Mainboard;
diff --git a/src/mainboard/lenovo/t430/mainboard.c b/src/mainboard/lenovo/t430/mainboard.c
deleted file mode 100644
index 50c944e341..0000000000
--- a/src/mainboard/lenovo/t430/mainboard.c
+++ /dev/null
@@ -1,15 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <device/device.h>
-#include <drivers/intel/gma/int15.h>
-
-static void mainboard_enable(struct device *dev)
-{
-	install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS,
-					GMA_INT15_PANEL_FIT_DEFAULT,
-					GMA_INT15_BOOT_DISPLAY_DEFAULT, 0);
-}
-
-struct chip_operations mainboard_ops = {
-	.enable_dev = mainboard_enable,
-};
diff --git a/src/mainboard/lenovo/t430/smihandler.c b/src/mainboard/lenovo/t430/smihandler.c
deleted file mode 100644
index 03c899e0d9..0000000000
--- a/src/mainboard/lenovo/t430/smihandler.c
+++ /dev/null
@@ -1,68 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <arch/io.h>
-#include <console/console.h>
-#include <cpu/x86/smm.h>
-#include <ec/acpi/ec.h>
-#include <ec/lenovo/h8/h8.h>
-#include <southbridge/intel/common/pmutil.h>
-#include <southbridge/intel/bd82x6x/pch.h>
-
-#define GPE_EC_SCI	1
-#define GPE_EC_WAKE	13
-
-static void mainboard_smi_handle_ec_sci(void)
-{
-	u8 status = inb(EC_SC);
-	u8 event;
-
-	if (!(status & EC_SCI_EVT))
-		return;
-
-	event = ec_query();
-	printk(BIOS_DEBUG, "EC event %#02x\n", event);
-}
-
-void mainboard_smi_gpi(u32 gpi_sts)
-{
-	if (gpi_sts & (1 << GPE_EC_SCI))
-		mainboard_smi_handle_ec_sci();
-}
-
-int mainboard_smi_apmc(u8 data)
-{
-	switch (data) {
-	case APM_CNT_ACPI_ENABLE:
-		/* use 0x1600/0x1604 to prevent races with userspace */
-		ec_set_ports(0x1604, 0x1600);
-		/* route EC_SCI to SCI */
-		gpi_route_interrupt(GPE_EC_SCI, GPI_IS_SCI);
-		/* discard all events, and enable attention */
-		ec_write(0x80, 0x01);
-		break;
-	case APM_CNT_ACPI_DISABLE:
-		/* we have to use port 0x62/0x66, as 0x1600/0x1604 doesn't
-		   provide a EC query function */
-		ec_set_ports(0x66, 0x62);
-		/* route EC_SCI to SMI */
-		gpi_route_interrupt(GPE_EC_SCI, GPI_IS_SMI);
-		/* discard all events, and enable attention */
-		ec_write(0x80, 0x01);
-		break;
-	default:
-		break;
-	}
-	return 0;
-}
-
-void mainboard_smi_sleep(u8 slp_typ)
-{
-	if (slp_typ == 3) {
-		u8 ec_wake = ec_read(0x32);
-		/* If EC wake events are enabled, enable wake on EC WAKE GPE. */
-		if (ec_wake & 0x14) {
-			/* Redirect EC WAKE GPE to SCI. */
-			gpi_route_interrupt(GPE_EC_WAKE, GPI_IS_SCI);
-		}
-	}
-}
diff --git a/src/mainboard/lenovo/t430/vboot-ro-me_clean.fmd b/src/mainboard/lenovo/t430/vboot-ro-me_clean.fmd
deleted file mode 100644
index 5101caa59c..0000000000
--- a/src/mainboard/lenovo/t430/vboot-ro-me_clean.fmd
+++ /dev/null
@@ -1,21 +0,0 @@
-FLASH 0xc00000 {
-	SI_ALL 0x20000 {
-		SI_DESC 0x1000
-		SI_GBE 0x2000
-		SI_ME
-	}
-	SI_BIOS 0xbe0000 {
-		UNIFIED_MRC_CACHE 0x20000 {
-			RECOVERY_MRC_CACHE 0x10000
-			RW_MRC_CACHE 0x10000
-		}
-
-		WP_RO {
-			FMAP 0x800
-			RO_FRID 0x40
-			RO_PADDING 0x7c0
-			GBB 0x1e000
-			COREBOOT(CBFS)
-		}
-	}
-}
diff --git a/src/mainboard/lenovo/t430/vboot-ro.fmd b/src/mainboard/lenovo/t430/vboot-ro.fmd
deleted file mode 100644
index 027849bfe9..0000000000
--- a/src/mainboard/lenovo/t430/vboot-ro.fmd
+++ /dev/null
@@ -1,21 +0,0 @@
-FLASH 0xc00000 {
-	SI_ALL 0x500000 {
-		SI_DESC 0x1000
-		SI_GBE 0x2000
-		SI_ME
-	}
-	SI_BIOS 0x700000 {
-		UNIFIED_MRC_CACHE 0x20000 {
-			RECOVERY_MRC_CACHE 0x10000
-			RW_MRC_CACHE 0x10000
-		}
-
-		WP_RO {
-			FMAP 0x800
-			RO_FRID 0x40
-			RO_PADDING 0x7c0
-			GBB 0x1e000
-			COREBOOT(CBFS)
-		}
-	}
-}
diff --git a/src/mainboard/lenovo/t430/vboot-rwab.fmd b/src/mainboard/lenovo/t430/vboot-rwab.fmd
deleted file mode 100644
index 8819959dfe..0000000000
--- a/src/mainboard/lenovo/t430/vboot-rwab.fmd
+++ /dev/null
@@ -1,35 +0,0 @@
-FLASH 0xc00000 {
-	SI_ALL@0x0 0x500000 {
-		SI_DESC@0x0 0x1000
-		SI_GBE@0x1000 0x2000
-		SI_ME
-	}
-	SI_BIOS@0x500000 0x700000 {
-		RW_SECTION_A 0x280000 {
-			VBLOCK_A 0x10000
-			FW_MAIN_A(CBFS)
-			RW_FWID_A 0x40
-		}
-		RW_SECTION_B 0x280000 {
-			VBLOCK_B 0x10000
-			FW_MAIN_B(CBFS)
-			RW_FWID_B 0x40
-		}
-		UNIFIED_MRC_CACHE@0x500000 0x20000 {
-			RECOVERY_MRC_CACHE@0x0 0x10000
-			RW_MRC_CACHE@0x10000 0x10000
-		}
-		RW_VPD(PRESERVE) 0x1000
-		SMMSTORE(PRESERVE)@0x521000 0x40000
-		RW_NVRAM(PRESERVE)@0x561000 0x2000
-
-		WP_RO {
-			FMAP 0x800
-			RO_FRID 0x40
-			RO_PADDING 0x7c0
-			RO_VPD(PRESERVE) 0x1000
-			GBB 0x1e000
-			COREBOOT(CBFS)
-		}
-	}
-}
diff --git a/src/mainboard/lenovo/t530/Kconfig b/src/mainboard/lenovo/t530/Kconfig
index 8830c39301..4f0002f536 100644
--- a/src/mainboard/lenovo/t530/Kconfig
+++ b/src/mainboard/lenovo/t530/Kconfig
@@ -38,6 +38,10 @@ config BOARD_LENOVO_W530
 	select BOARD_LENOVO_BASEBOARD_T530
 	select DRIVERS_RICOH_RCE822
 
+config BOARD_LENOVO_T430
+	select BOARD_LENOVO_BASEBOARD_T530
+	select DRIVERS_RICOH_RCE822
+
 if BOARD_LENOVO_BASEBOARD_T530
 
 config VBOOT
@@ -60,6 +64,7 @@ config FMDFILE
 config VARIANT_DIR
 	default "t530" if BOARD_LENOVO_T530
 	default "w530" if BOARD_LENOVO_W530
+	default "t430" if BOARD_LENOVO_T430
 
 config MAINBOARD_DIR
 	default "lenovo/t530"
@@ -70,6 +75,7 @@ config OVERRIDE_DEVICETREE
 config MAINBOARD_PART_NUMBER
 	default "ThinkPad T530" if BOARD_LENOVO_T530
 	default "ThinkPad W530" if BOARD_LENOVO_W530
+	default "ThinkPad T430" if BOARD_LENOVO_T430
 
 config USBDEBUG_HCD_INDEX
 	int
@@ -84,6 +90,7 @@ config VGA_BIOS_ID
 	default "8086,0166"
 
 config PS2K_EISAID
+	default "PNP0303" if BOARD_LENOVO_T430
 	default "LEN0071"
 
 config PS2M_EISAID
diff --git a/src/mainboard/lenovo/t530/Kconfig.name b/src/mainboard/lenovo/t530/Kconfig.name
index d8b1925f65..5b42bd2f89 100644
--- a/src/mainboard/lenovo/t530/Kconfig.name
+++ b/src/mainboard/lenovo/t530/Kconfig.name
@@ -5,3 +5,6 @@ config BOARD_LENOVO_T530
 
 config BOARD_LENOVO_W530
 	bool "ThinkPad W530"
+
+config BOARD_LENOVO_T430
+	bool "ThinkPad T430"
diff --git a/src/mainboard/lenovo/t530/Makefile.mk b/src/mainboard/lenovo/t530/Makefile.mk
index 69ef08873b..1c72bfe045 100644
--- a/src/mainboard/lenovo/t530/Makefile.mk
+++ b/src/mainboard/lenovo/t530/Makefile.mk
@@ -5,3 +5,4 @@ romstage-y += variants/$(VARIANT_DIR)/gpio.c
 ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads
 bootblock-y += early_init.c
 romstage-y += early_init.c
+ramstage-y += variants/$(VARIANT_DIR)/hda_verb.c
diff --git a/src/mainboard/lenovo/t430/data.vbt b/src/mainboard/lenovo/t530/variants/t430/data.vbt
similarity index 100%
rename from src/mainboard/lenovo/t430/data.vbt
rename to src/mainboard/lenovo/t530/variants/t430/data.vbt
diff --git a/src/mainboard/lenovo/t430/gpio.c b/src/mainboard/lenovo/t530/variants/t430/gpio.c
similarity index 100%
rename from src/mainboard/lenovo/t430/gpio.c
rename to src/mainboard/lenovo/t530/variants/t430/gpio.c
diff --git a/src/mainboard/lenovo/t430/hda_verb.c b/src/mainboard/lenovo/t530/variants/t430/hda_verb.c
similarity index 100%
rename from src/mainboard/lenovo/t430/hda_verb.c
rename to src/mainboard/lenovo/t530/variants/t430/hda_verb.c
diff --git a/src/mainboard/lenovo/t530/variants/t430/overridetree.cb b/src/mainboard/lenovo/t530/variants/t430/overridetree.cb
new file mode 100644
index 0000000000..72cc6b54e1
--- /dev/null
+++ b/src/mainboard/lenovo/t530/variants/t430/overridetree.cb
@@ -0,0 +1,58 @@
+chip northbridge/intel/sandybridge
+	register "gpu_panel_power_backlight_on_delay" = "2100"	# T3: 210ms
+	register "gpu_panel_power_backlight_off_delay" = "2100"	# T4: 210ms
+
+	register "spd_addresses" = "{0x50, 0, 0x51, 0}"
+	device domain 0 on
+		subsystemid 0x17aa 0x21f3 inherit
+		chip southbridge/intel/bd82x6x # Intel Series 7 Panther Point PCH
+			register "sata_interface_speed_support" = "0x3"
+			register "sata_port_map" = "0x17"
+
+			# Do not enable xHCI Port 4 since WWAN USB is EHCI-only
+			register "superspeed_capable_ports" = "0x7"
+			register "xhci_switchable_ports" = "0x7"
+			register "usb_port_config" = "{
+				{ 1, 1,  0 },
+				{ 1, 1,  1 },
+				{ 1, 2,  3 },
+				{ 1, 1, -1 },
+				{ 1, 1,  2 },
+				{ 1, 0, -1 },
+				{ 0, 0, -1 },
+				{ 1, 2, -1 },
+				{ 1, 0, -1 },
+				{ 1, 1,  5 },
+				{ 1, 0, -1 },
+				{ 1, 0, -1 },
+				{ 1, 3, -1 },
+				{ 1, 1, -1 }
+			}"
+
+			device ref pcie_rp1 on # PCIe Port #1
+				chip drivers/ricoh/rce822 # Ricoh cardreader
+					register "disable_mask" = "0x87"
+					register "sdwppol" = "1"
+					device pci 00.0 on end # Ricoh SD card reader
+				end
+			end
+			device ref lpc on
+				chip ec/lenovo/h8
+					device pnp ff.2 on end # dummy
+					register "wwan_gpio_num" = "70"
+					register "wwan_gpio_lvl" = "0"
+					register "config1" = "0x01"
+					register "config3" = "0xe2"
+					register "has_keyboard_backlight" = "0"
+					register "beepmask0" = "0x02"
+					register "has_power_management_beeps" = "1"
+					register "event4_enable" = "0xf0"
+					register "event5_enable" = "0x3c"
+					register "event7_enable" = "0xa1"
+					register "eventa_enable" = "0x00"
+				end
+			end
+			device ref thermal off end # Thermal
+		end
+	end
+end
diff --git a/src/mainboard/lenovo/t530/hda_verb.c b/src/mainboard/lenovo/t530/variants/t530/hda_verb.c
similarity index 100%
rename from src/mainboard/lenovo/t530/hda_verb.c
rename to src/mainboard/lenovo/t530/variants/t530/hda_verb.c
diff --git a/src/mainboard/lenovo/t530/variants/w530/hda_verb.c b/src/mainboard/lenovo/t530/variants/w530/hda_verb.c
new file mode 100644
index 0000000000..564aff2d77
--- /dev/null
+++ b/src/mainboard/lenovo/t530/variants/w530/hda_verb.c
@@ -0,0 +1,75 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+/* Bits 31:28 - Codec Address */
+/* Bits 27:20 - NID */
+/* Bits 19:8 - Verb ID */
+/* Bits 7:0  - Payload */
+
+#include <device/azalia_device.h>
+
+const u32 cim_verb_data[] = {
+	0x10ec0269,	/* Codec Vendor / Device ID: Realtek ALC269VC */
+	0x17aa21fa,	/* Subsystem ID */
+	18,		/* Number of 4 dword sets */
+	AZALIA_SUBVENDOR(0, 0x17aa21fa),
+
+	/* Ext. Microphone Connector:	External,Right; MicIn,3.5mm; Black,JD; DA,Seq */
+	AZALIA_PIN_CFG(0, 0x0a, 0x04a11020),
+
+	/* Headphones Connector:	External,Right; HP,3.5mm; Black,JD; DA,Seq */
+	AZALIA_PIN_CFG(0, 0x0b, 0x0421101f),
+
+	/* Not connected:		N/A,N/A; Other,Unknown; Unknown,JD; DA,Seq */
+	AZALIA_PIN_CFG(0, 0x0c, 0x40f000f0),
+
+	/* Internal Speakers		Fixed,Int; Speaker,Other Analog; Unknown,nJD; DA,Seq */
+	AZALIA_PIN_CFG(0, 0x0d, 0x90170110),
+
+	/* Not connected */
+	AZALIA_PIN_CFG(0, 0x0f, 0x40f000f0),
+
+	/* Internal Microphone:		Fixed,Int,Top; Mic In,ATIPI; Unknown,nJD; DA,Seq */
+	AZALIA_PIN_CFG(0, 0x11, 0xd5a30140),
+	AZALIA_PIN_CFG(0, 0x12, 0x90a60140),
+	AZALIA_PIN_CFG(0, 0x14, 0x90170110),
+	AZALIA_PIN_CFG(0, 0x15, 0x03211020),
+	AZALIA_PIN_CFG(0, 0x18, 0x03a11830),
+	AZALIA_PIN_CFG(0, 0x19, AZALIA_PIN_CFG_NC(0)),
+
+	0x01970804,
+	0x01870803,
+	0x01470740,
+	0x00970600,
+
+	AZALIA_PIN_CFG(0, 0x1a, AZALIA_PIN_CFG_NC(0)),
+	AZALIA_PIN_CFG(0, 0x1d, 0x40138205),
+	AZALIA_PIN_CFG(0, 0x1e, AZALIA_PIN_CFG_NC(0)),
+
+	/* Misc entries */
+		0x00370600,
+		0x00270600,
+		0x00b707C0, /* Enable PortB as Output with HP amp */
+		0x00d70740, /* Enable PortD as Output */
+		0x0017a200, /* Disable ClkEn of PortSenseTst */
+		0x0017c621, /* Slave Port - Port A used as microphone input for
+		                            combo Jack
+		               Master Port - Port B used for Jack Presence Detect
+		               Enable Combo Jack Detection */
+		0x0017a208, /* Enable ClkEn of PortSenseTst */
+		0x00170500, /* Set power state to D0 */
+
+	/* --- Codec #3 --- */
+	0x80862806,	/* Codec Vendor / Device ID: Intel PantherPoint HDMI */
+	0x80860101,	/* Subsystem ID */
+	4,		/* Number of 4 dword sets */
+	AZALIA_SUBVENDOR(3, 0x80860101),
+	AZALIA_PIN_CFG(3, 0x05, 0x18560010),
+	AZALIA_PIN_CFG(3, 0x06, 0x18560020),
+	AZALIA_PIN_CFG(3, 0x07, 0x18560030),
+};
+
+const u32 pc_beep_verbs[] = {
+	0x02177a00, /* Digital PCBEEP Gain: 0h=-9db, 1h=-6db ... 4h=+3db, 5h=+6db */
+};
+
+AZALIA_ARRAY_SIZES;

From 7847a54eed29d26696163d3ff4bb241221d21e5e Mon Sep 17 00:00:00 2001
From: Patrick Rudolph <patrick.rudolph@9elements.com>
Date: Thu, 26 Feb 2026 14:44:39 +0100
Subject: [PATCH 3505/3886] mb/lenovo: Convert PNP device to generic device

Convert the hybrid graphics mux into a generic device and give it an
alias so that the driver can reference it by name.

Change-Id: Icbf6f298cab9e11acc9363daba68f9fbc613e79d
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91440
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
---
 src/drivers/lenovo/hybrid_graphics/chip.h               | 4 ----
 src/drivers/lenovo/hybrid_graphics/romstage.c           | 7 ++++---
 src/mainboard/lenovo/t400/variants/t400/overridetree.cb | 2 +-
 src/mainboard/lenovo/t410/devicetree.cb                 | 2 +-
 src/mainboard/lenovo/t420/devicetree.cb                 | 2 +-
 src/mainboard/lenovo/t420s/devicetree.cb                | 2 +-
 src/mainboard/lenovo/t520/devicetree.cb                 | 2 +-
 src/mainboard/lenovo/t530/devicetree.cb                 | 2 +-
 8 files changed, 10 insertions(+), 13 deletions(-)

diff --git a/src/drivers/lenovo/hybrid_graphics/chip.h b/src/drivers/lenovo/hybrid_graphics/chip.h
index 4a17138552..81d3552e98 100644
--- a/src/drivers/lenovo/hybrid_graphics/chip.h
+++ b/src/drivers/lenovo/hybrid_graphics/chip.h
@@ -3,10 +3,6 @@
 #ifndef _LENOVO_HYBRID_GRAPHICS_CHIP_H_
 #define _LENOVO_HYBRID_GRAPHICS_CHIP_H_
 
-#define HYBRID_GRAPHICS_PORT 0xff
-
-#define HYBRID_GRAPHICS_DEVICE 0xf
-
 enum hybrid_graphics_req {
 	HYBRID_GRAPHICS_INTEGRATED = 0,
 	HYBRID_GRAPHICS_DISCRETE = 1,
diff --git a/src/drivers/lenovo/hybrid_graphics/romstage.c b/src/drivers/lenovo/hybrid_graphics/romstage.c
index 10f94439f8..6860c958f3 100644
--- a/src/drivers/lenovo/hybrid_graphics/romstage.c
+++ b/src/drivers/lenovo/hybrid_graphics/romstage.c
@@ -5,11 +5,14 @@
 #include <ec/lenovo/pmh7/pmh7.h>
 #include <option.h>
 #include <gpio.h>
+#include <static.h>
 #include <types.h>
 
 #include "hybrid_graphics.h"
 #include "chip.h"
 
+WEAK_DEV_PTR(hg_mux);
+
 /*
  * Returns the hybrid graphics presence and user's card preferences.
  */
@@ -19,9 +22,7 @@ void early_hybrid_graphics(bool *enable_igd, bool *enable_peg)
 	const struct device *dev;
 	enum hybrid_graphics_req mode;
 
-	/* TODO: Use generic device instead of dummy PNP device */
-	dev = dev_find_slot_pnp(HYBRID_GRAPHICS_PORT, HYBRID_GRAPHICS_DEVICE);
-
+	dev = DEV_PTR(hg_mux);
 	if (!dev || !dev->chip_info) {
 		printk(BIOS_ERR, "Hybrid graphics: ERROR\n");
 		*enable_igd = true;
diff --git a/src/mainboard/lenovo/t400/variants/t400/overridetree.cb b/src/mainboard/lenovo/t400/variants/t400/overridetree.cb
index c3c3b082a5..1e0c3fe100 100644
--- a/src/mainboard/lenovo/t400/variants/t400/overridetree.cb
+++ b/src/mainboard/lenovo/t400/variants/t400/overridetree.cb
@@ -4,7 +4,7 @@ chip northbridge/intel/gm45
 			device pci 1f.0 on # LPC bridge
 				subsystemid 0x17aa 0x20f5
 				chip drivers/lenovo/hybrid_graphics
-					device pnp ff.f on end # dummy
+					device generic 0 alias hg_mux on end # dummy
 
 					register "detect_gpio" = "21"
 
diff --git a/src/mainboard/lenovo/t410/devicetree.cb b/src/mainboard/lenovo/t410/devicetree.cb
index 9ba70d79e8..d4af8253e6 100644
--- a/src/mainboard/lenovo/t410/devicetree.cb
+++ b/src/mainboard/lenovo/t410/devicetree.cb
@@ -134,7 +134,7 @@ chip northbridge/intel/ironlake
 					register "evente_enable" = "0x2d"
 				end
 				chip drivers/lenovo/hybrid_graphics
-					device pnp ff.f on end # dummy
+					device generic 0 alias hg_mux on end # dummy
 
 					register "detect_gpio" = "21"
 
diff --git a/src/mainboard/lenovo/t420/devicetree.cb b/src/mainboard/lenovo/t420/devicetree.cb
index 37ac884eb3..4e4d4a0d8e 100644
--- a/src/mainboard/lenovo/t420/devicetree.cb
+++ b/src/mainboard/lenovo/t420/devicetree.cb
@@ -153,7 +153,7 @@ chip northbridge/intel/sandybridge
 					register "bdc_gpio_lvl" = "0"
 				end
 				chip drivers/lenovo/hybrid_graphics
-					device pnp ff.f on end # dummy
+					device generic 0 alias hg_mux on end # dummy
 
 					register "detect_gpio" = "21"
 
diff --git a/src/mainboard/lenovo/t420s/devicetree.cb b/src/mainboard/lenovo/t420s/devicetree.cb
index 335e025c72..4ae67ec3f8 100644
--- a/src/mainboard/lenovo/t420s/devicetree.cb
+++ b/src/mainboard/lenovo/t420s/devicetree.cb
@@ -145,7 +145,7 @@ chip northbridge/intel/sandybridge
 					register "bdc_gpio_lvl" = "0"
 				end
 				chip drivers/lenovo/hybrid_graphics
-					device pnp ff.f on end # dummy
+					device generic 0 alias hg_mux on end # dummy
 
 					register "detect_gpio" = "21"
 
diff --git a/src/mainboard/lenovo/t520/devicetree.cb b/src/mainboard/lenovo/t520/devicetree.cb
index 74605ca081..9456f85bd4 100644
--- a/src/mainboard/lenovo/t520/devicetree.cb
+++ b/src/mainboard/lenovo/t520/devicetree.cb
@@ -141,7 +141,7 @@ chip northbridge/intel/sandybridge
 					register "bdc_gpio_lvl" = "0"
 				end
 				chip drivers/lenovo/hybrid_graphics
-					device pnp ff.f on end # dummy
+					device generic 0 alias hg_mux on end # dummy
 
 					register "detect_gpio" = "21"
 
diff --git a/src/mainboard/lenovo/t530/devicetree.cb b/src/mainboard/lenovo/t530/devicetree.cb
index 944de3dd49..3ca79999f1 100644
--- a/src/mainboard/lenovo/t530/devicetree.cb
+++ b/src/mainboard/lenovo/t530/devicetree.cb
@@ -121,7 +121,7 @@ chip northbridge/intel/sandybridge
 					register "bdc_gpio_lvl" = "0"
 				end
 				chip drivers/lenovo/hybrid_graphics
-					device pnp ff.f on end # dummy
+					device generic 0 alias hg_mux on end # dummy
 
 					register "detect_gpio" = "21"
 

From c2eea0c96c6ea050396ab82049517afb0f6d87cc Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Thu, 26 Feb 2026 21:38:06 +0000
Subject: [PATCH 3506/3886] mainboard/starlabs/adl: add Bluetooth RTD3 CFR
 option

Expose the existing bluetooth_rtd3 CFR option on ADL boards.

BUG=None
TEST=BUILD_TIMELESS=1 build BOARD_STARLABS_ADL_HORIZON

Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I2d2f0abe6f9230f3744d3d7e100eda923b0aabc6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91447
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
---
 src/mainboard/starlabs/adl/cfr.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/src/mainboard/starlabs/adl/cfr.c b/src/mainboard/starlabs/adl/cfr.c
index 634f945f6e..43d064f90f 100644
--- a/src/mainboard/starlabs/adl/cfr.c
+++ b/src/mainboard/starlabs/adl/cfr.c
@@ -113,6 +113,7 @@ static struct sm_obj_form wireless_group = {
 	.ui_name = "Wireless",
 	.obj_list = (const struct sm_object *[]) {
 		&bluetooth,
+		&bluetooth_rtd3,
 		&wifi,
 		NULL
 	},

From ce5c91534485c8181425449a6c2a286076c6d18c Mon Sep 17 00:00:00 2001
From: Nicholas Chin <nic.c3.14@gmail.com>
Date: Tue, 24 Feb 2026 23:29:17 -0700
Subject: [PATCH 3507/3886] drivers/spi/flashconsole.c: Fix flashconsole

Commit 1f2408f57300 ("console: Fix flushing for slow consoles") fixed a
typo related to some refactoring of the CBMEM fast code path. However,
this also seems to have indirectly broken the SPI flash console, causing
only the console header messages at the beginning of each stage to be
stored.

This is caused by multiple calls to flashconsole_tx_flush() without a
call to flashconsole_tx_byte() in between them. Data is accumulated in a
buffer during calls to flashconsole_tx_byte(), which is then written to
the flash during a flush. If no tx calls occur between flushes, the
second call will try to write data of length 0, which seems to cause
rdev_writeat() to return -1. This causes an early return, since the
return value of rdev_writeat() must match the data length in order for
the rest of the flashconsole_tx_flush to run. The flush function
contains a busy flag to prevent recursive calls to itself, and the early
return prevents it from being reset. Thus, the busy flag remains set for
the remainder of the stage, blocking all future flushes.

The multiple flushes occur because vprintk flushes console drivers after
the string has been sent, but flashconsole_tx_byte() also calls a flush
whenever a newline is encountered. Because of this, flushes are disabled
for the remainder of each stage after the first printk call containing a
newline is stored to the flash console. Although this newline check
could be omitted, flashconsole_tx_byte() also invokes a flush when its
data buffer is full, which shouldn't be avoided.

Prior to the mentioned commit, the incorrect logic happened to prevent
the flush in vprintk, preventing the double flush issue from occurring.
The mentioned commit inverted the logic, allowing the double flush to
occur.

Address this by returning early if len = 0. While we're here,
consolidate the early returns into a single check and change the busy
flag to a bool instead of an int.

TEST=Console messages are not missing in the flashconsole. Tested on the
Lenovo ThinkCentre M900 SFF.

Change-Id: Ic6c2418f04a687610df020df117f7be90b1724b9
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91428
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
---
 src/drivers/spi/flashconsole.c | 16 +++++++++-------
 1 file changed, 9 insertions(+), 7 deletions(-)

diff --git a/src/drivers/spi/flashconsole.c b/src/drivers/spi/flashconsole.c
index 679c814dff..878cef0ce3 100644
--- a/src/drivers/spi/flashconsole.c
+++ b/src/drivers/spi/flashconsole.c
@@ -87,18 +87,20 @@ void flashconsole_tx_flush(void)
 {
 	size_t len = line_offset;
 	size_t region_size;
-	static int busy;
 
 	/* Prevent any recursive loops in case the spi flash driver
 	 * calls printk (in case of transaction timeout or
 	 * any other error while writing) */
-	if (busy)
+	static bool busy;
+
+	/* In addition to being an obvious runtime optimization, checking for
+	 * len = 0 also prevents false disabling of the driver, as rdev_writeat
+	 * seems to return -1 if len is zero even though this should be a
+	 * recoverable condition. */
+	if (busy || !rdev_ptr || len == 0)
 		return;
 
-	if (!rdev_ptr)
-		return;
-
-	busy = 1;
+	busy = true;
 	region_size = region_device_sz(rdev_ptr);
 	if (offset + len >= region_size)
 		len = region_size - offset;
@@ -113,5 +115,5 @@ void flashconsole_tx_flush(void)
 	offset += len;
 	line_offset = 0;
 
-	busy = 0;
+	busy = false;
 }

From e0c26a05d435f76005c05d0fac7d66ef9daf679d Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Thu, 26 Feb 2026 12:39:12 +0000
Subject: [PATCH 3508/3886] ec/starlabs/merlin: fix OSFG suspend comment

OSFG is toggled from _PTS/_WAK via MPTS/MWAK and therefore runs for all
supported sleep states. Update the suspend/resume comments to match the
unguarded behavior.

Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I613efd68ed2770798c2754a1c59f802f47986795
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91439
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
---
 src/ec/starlabs/merlin/acpi/suspend.asl | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/ec/starlabs/merlin/acpi/suspend.asl b/src/ec/starlabs/merlin/acpi/suspend.asl
index 2039b34c47..966362f8a4 100644
--- a/src/ec/starlabs/merlin/acpi/suspend.asl
+++ b/src/ec/starlabs/merlin/acpi/suspend.asl
@@ -66,7 +66,7 @@ Method (RPTS, 1, Serialized)
 
 	/*
 	 * Disable ACPI support.
-	 * This should always be the last action before entering S4 or S5.
+	 * This should always be the last action before entering a sleep state.
 	 */
 	\_SB.PCI0.LPCB.EC.ECWR(0x00, RefOf(\_SB.PCI0.LPCB.EC.OSFG))
 }
@@ -75,7 +75,7 @@ Method (RWAK, 1, Serialized)
 {
 	/*
 	 * Enable ACPI support.
-	 * This should always be the first action when exiting S4 or S5.
+	 * This should always be the first action when exiting a sleep state.
 	 */
 	\_SB.PCI0.LPCB.EC.ECWR(0x01, RefOf(\_SB.PCI0.LPCB.EC.OSFG))
 

From 50e92c9cf11226e9c7be14fade8d0d88d03125dc Mon Sep 17 00:00:00 2001
From: Tom Hiller <thrilleratplay@gmail.com>
Date: Thu, 4 Dec 2025 19:54:36 -0500
Subject: [PATCH 3509/3886] mb/lenovo/m920q: Rename to reflect use for m720q
 variant as well

The m920q and m720q are the same board, so rename the m920q to reflect
that

Change-Id: Ieef22530207ad4c35ac3cb4255d2ad65e62b65bf
Signed-off-by: Tom Hiller <thrilleratplay@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90374
Reviewed-by: Evie (Ivi) Ballou <iviballou@gmail.com>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/lenovo/{m920q => m720q_m920q}/Kconfig |  10 ++++++----
 .../lenovo/{m920q => m720q_m920q}/Kconfig.name      |   3 +++
 .../lenovo/{m920q => m720q_m920q}/Makefile.mk       |   0
 .../lenovo/{m920q => m720q_m920q}/acpi/ec.asl       |   0
 .../{m920q => m720q_m920q}/acpi/mainboard.asl       |   0
 .../lenovo/{m920q => m720q_m920q}/acpi/superio.asl  |   0
 .../lenovo/{m920q => m720q_m920q}/board_info.txt    |   4 ++--
 .../lenovo/{m920q => m720q_m920q}/bootblock.c       |   0
 .../lenovo/{m920q => m720q_m920q}/cmos.default      |   0
 .../lenovo/{m920q => m720q_m920q}/cmos.layout       |   0
 .../lenovo/{m920q => m720q_m920q}/data.vbt          | Bin
 .../lenovo/{m920q => m720q_m920q}/devicetree.cb     |   0
 .../lenovo/{m920q => m720q_m920q}/dsdt.asl          |   0
 .../lenovo/{m920q => m720q_m920q}/gma-mainboard.ads |   0
 src/mainboard/lenovo/{m920q => m720q_m920q}/gpio.c  |   0
 .../lenovo/{m920q => m720q_m920q}/hda_verb.c        |   0
 .../{m920q => m720q_m920q}/include/mainboard/gpio.h |   0
 .../lenovo/{m920q => m720q_m920q}/ramstage.c        |   0
 .../lenovo/{m920q => m720q_m920q}/romstage.c        |   0
 19 files changed, 11 insertions(+), 6 deletions(-)
 rename src/mainboard/lenovo/{m920q => m720q_m920q}/Kconfig (68%)
 rename src/mainboard/lenovo/{m920q => m720q_m920q}/Kconfig.name (62%)
 rename src/mainboard/lenovo/{m920q => m720q_m920q}/Makefile.mk (100%)
 rename src/mainboard/lenovo/{m920q => m720q_m920q}/acpi/ec.asl (100%)
 rename src/mainboard/lenovo/{m920q => m720q_m920q}/acpi/mainboard.asl (100%)
 rename src/mainboard/lenovo/{m920q => m720q_m920q}/acpi/superio.asl (100%)
 rename src/mainboard/lenovo/{m920q => m720q_m920q}/board_info.txt (51%)
 rename src/mainboard/lenovo/{m920q => m720q_m920q}/bootblock.c (100%)
 rename src/mainboard/lenovo/{m920q => m720q_m920q}/cmos.default (100%)
 rename src/mainboard/lenovo/{m920q => m720q_m920q}/cmos.layout (100%)
 rename src/mainboard/lenovo/{m920q => m720q_m920q}/data.vbt (100%)
 rename src/mainboard/lenovo/{m920q => m720q_m920q}/devicetree.cb (100%)
 rename src/mainboard/lenovo/{m920q => m720q_m920q}/dsdt.asl (100%)
 rename src/mainboard/lenovo/{m920q => m720q_m920q}/gma-mainboard.ads (100%)
 rename src/mainboard/lenovo/{m920q => m720q_m920q}/gpio.c (100%)
 rename src/mainboard/lenovo/{m920q => m720q_m920q}/hda_verb.c (100%)
 rename src/mainboard/lenovo/{m920q => m720q_m920q}/include/mainboard/gpio.h (100%)
 rename src/mainboard/lenovo/{m920q => m720q_m920q}/ramstage.c (100%)
 rename src/mainboard/lenovo/{m920q => m720q_m920q}/romstage.c (100%)

diff --git a/src/mainboard/lenovo/m920q/Kconfig b/src/mainboard/lenovo/m720q_m920q/Kconfig
similarity index 68%
rename from src/mainboard/lenovo/m920q/Kconfig
rename to src/mainboard/lenovo/m720q_m920q/Kconfig
index 53d74b821a..40641c211f 100644
--- a/src/mainboard/lenovo/m920q/Kconfig
+++ b/src/mainboard/lenovo/m720q_m920q/Kconfig
@@ -1,11 +1,12 @@
 # SPDX-License-Identifier: GPL-2.0-only
 
-if BOARD_LENOVO_M920Q
+if BOARD_LENOVO_M920Q || BOARD_LENOVO_M720Q
 
 config BOARD_SPECIFIC_OPTIONS
 	def_bool y
 	select AZALIA_USE_LEGACY_VERB_TABLE
-	select BOARD_ROMSIZE_KB_24576
+	select BOARD_ROMSIZE_KB_16384 if BOARD_LENOVO_M720Q
+	select BOARD_ROMSIZE_KB_24576 if BOARD_LENOVO_M920Q
 	select DRIVERS_UART_8250IO
 	select HAVE_ACPI_RESUME
 	select HAVE_ACPI_TABLES
@@ -22,10 +23,11 @@ config BOARD_SPECIFIC_OPTIONS
 	select SUPERIO_NUVOTON_NCT6687D
 
 config MAINBOARD_DIR
-	default "lenovo/m920q"
+	default "lenovo/m720q_m920q"
 
 config MAINBOARD_PART_NUMBER
-	default "ThinkCentre M920 Tiny"
+	default "ThinkCentre M720 Tiny" if BOARD_LENOVO_M720Q
+	default "ThinkCentre M920 Tiny" if BOARD_LENOVO_M920Q
 
 config CBFS_SIZE
 	default 0x900000
diff --git a/src/mainboard/lenovo/m920q/Kconfig.name b/src/mainboard/lenovo/m720q_m920q/Kconfig.name
similarity index 62%
rename from src/mainboard/lenovo/m920q/Kconfig.name
rename to src/mainboard/lenovo/m720q_m920q/Kconfig.name
index ccdd21a237..6f5110366a 100644
--- a/src/mainboard/lenovo/m920q/Kconfig.name
+++ b/src/mainboard/lenovo/m720q_m920q/Kconfig.name
@@ -1,4 +1,7 @@
 # SPDX-License-Identifier: GPL-2.0-only
 
+config BOARD_LENOVO_M720Q
+	bool "ThinkCentre M720 Tiny"
+
 config BOARD_LENOVO_M920Q
 	bool "ThinkCentre M920 Tiny"
diff --git a/src/mainboard/lenovo/m920q/Makefile.mk b/src/mainboard/lenovo/m720q_m920q/Makefile.mk
similarity index 100%
rename from src/mainboard/lenovo/m920q/Makefile.mk
rename to src/mainboard/lenovo/m720q_m920q/Makefile.mk
diff --git a/src/mainboard/lenovo/m920q/acpi/ec.asl b/src/mainboard/lenovo/m720q_m920q/acpi/ec.asl
similarity index 100%
rename from src/mainboard/lenovo/m920q/acpi/ec.asl
rename to src/mainboard/lenovo/m720q_m920q/acpi/ec.asl
diff --git a/src/mainboard/lenovo/m920q/acpi/mainboard.asl b/src/mainboard/lenovo/m720q_m920q/acpi/mainboard.asl
similarity index 100%
rename from src/mainboard/lenovo/m920q/acpi/mainboard.asl
rename to src/mainboard/lenovo/m720q_m920q/acpi/mainboard.asl
diff --git a/src/mainboard/lenovo/m920q/acpi/superio.asl b/src/mainboard/lenovo/m720q_m920q/acpi/superio.asl
similarity index 100%
rename from src/mainboard/lenovo/m920q/acpi/superio.asl
rename to src/mainboard/lenovo/m720q_m920q/acpi/superio.asl
diff --git a/src/mainboard/lenovo/m920q/board_info.txt b/src/mainboard/lenovo/m720q_m920q/board_info.txt
similarity index 51%
rename from src/mainboard/lenovo/m920q/board_info.txt
rename to src/mainboard/lenovo/m720q_m920q/board_info.txt
index 02e3e322eb..8420ecc448 100644
--- a/src/mainboard/lenovo/m920q/board_info.txt
+++ b/src/mainboard/lenovo/m720q_m920q/board_info.txt
@@ -1,7 +1,7 @@
 Category: desktop
-Board URL: https://psref.lenovo.com/Product/ThinkCentre_M920_Tiny
+Board URL: ThinkCentre M720q/M920q
 ROM package: SOIC-8
 ROM protocol: SPI
 ROM socketed: n
 Flashrom support: y
-Release year: 2021
+Release year: 2018
diff --git a/src/mainboard/lenovo/m920q/bootblock.c b/src/mainboard/lenovo/m720q_m920q/bootblock.c
similarity index 100%
rename from src/mainboard/lenovo/m920q/bootblock.c
rename to src/mainboard/lenovo/m720q_m920q/bootblock.c
diff --git a/src/mainboard/lenovo/m920q/cmos.default b/src/mainboard/lenovo/m720q_m920q/cmos.default
similarity index 100%
rename from src/mainboard/lenovo/m920q/cmos.default
rename to src/mainboard/lenovo/m720q_m920q/cmos.default
diff --git a/src/mainboard/lenovo/m920q/cmos.layout b/src/mainboard/lenovo/m720q_m920q/cmos.layout
similarity index 100%
rename from src/mainboard/lenovo/m920q/cmos.layout
rename to src/mainboard/lenovo/m720q_m920q/cmos.layout
diff --git a/src/mainboard/lenovo/m920q/data.vbt b/src/mainboard/lenovo/m720q_m920q/data.vbt
similarity index 100%
rename from src/mainboard/lenovo/m920q/data.vbt
rename to src/mainboard/lenovo/m720q_m920q/data.vbt
diff --git a/src/mainboard/lenovo/m920q/devicetree.cb b/src/mainboard/lenovo/m720q_m920q/devicetree.cb
similarity index 100%
rename from src/mainboard/lenovo/m920q/devicetree.cb
rename to src/mainboard/lenovo/m720q_m920q/devicetree.cb
diff --git a/src/mainboard/lenovo/m920q/dsdt.asl b/src/mainboard/lenovo/m720q_m920q/dsdt.asl
similarity index 100%
rename from src/mainboard/lenovo/m920q/dsdt.asl
rename to src/mainboard/lenovo/m720q_m920q/dsdt.asl
diff --git a/src/mainboard/lenovo/m920q/gma-mainboard.ads b/src/mainboard/lenovo/m720q_m920q/gma-mainboard.ads
similarity index 100%
rename from src/mainboard/lenovo/m920q/gma-mainboard.ads
rename to src/mainboard/lenovo/m720q_m920q/gma-mainboard.ads
diff --git a/src/mainboard/lenovo/m920q/gpio.c b/src/mainboard/lenovo/m720q_m920q/gpio.c
similarity index 100%
rename from src/mainboard/lenovo/m920q/gpio.c
rename to src/mainboard/lenovo/m720q_m920q/gpio.c
diff --git a/src/mainboard/lenovo/m920q/hda_verb.c b/src/mainboard/lenovo/m720q_m920q/hda_verb.c
similarity index 100%
rename from src/mainboard/lenovo/m920q/hda_verb.c
rename to src/mainboard/lenovo/m720q_m920q/hda_verb.c
diff --git a/src/mainboard/lenovo/m920q/include/mainboard/gpio.h b/src/mainboard/lenovo/m720q_m920q/include/mainboard/gpio.h
similarity index 100%
rename from src/mainboard/lenovo/m920q/include/mainboard/gpio.h
rename to src/mainboard/lenovo/m720q_m920q/include/mainboard/gpio.h
diff --git a/src/mainboard/lenovo/m920q/ramstage.c b/src/mainboard/lenovo/m720q_m920q/ramstage.c
similarity index 100%
rename from src/mainboard/lenovo/m920q/ramstage.c
rename to src/mainboard/lenovo/m720q_m920q/ramstage.c
diff --git a/src/mainboard/lenovo/m920q/romstage.c b/src/mainboard/lenovo/m720q_m920q/romstage.c
similarity index 100%
rename from src/mainboard/lenovo/m920q/romstage.c
rename to src/mainboard/lenovo/m720q_m920q/romstage.c

From 69242d5bb10e014c6c80bfb489e9574cab0db931 Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Thu, 26 Feb 2026 12:37:55 -0600
Subject: [PATCH 3510/3886] drivers/usb/acpi: Add DSM function 3 support for
 Intel Bluetooth

The Linux btintel driver requires DSM function 3 (DSM_SET_RESET_METHOD)
to be supported before it will use the ACPI _PRR/_RST reset path.
Without it, the driver falls back to GPIO or USB reset.

Add set_reset_method callback that returns success. coreboot only
supports WDISABLE2 (GPIO); the _RST method already implements the
toggle. Update the capability buffer (0x03 -> 0x0b) to advertise
function 3 support. Change RDLY default from 105 to 160 ms to match
the Linux driver.

Change-Id: I6a7c9289dcffbbbd769ab3fb4e59765d2fef7598
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91445
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/drivers/usb/acpi/intel_bluetooth.c | 32 ++++++++++++++++++++------
 1 file changed, 25 insertions(+), 7 deletions(-)

diff --git a/src/drivers/usb/acpi/intel_bluetooth.c b/src/drivers/usb/acpi/intel_bluetooth.c
index 2ccb13bfe8..151f2bb18c 100644
--- a/src/drivers/usb/acpi/intel_bluetooth.c
+++ b/src/drivers/usb/acpi/intel_bluetooth.c
@@ -14,16 +14,20 @@
  *
  * Arg2 == 1:	Set the reset delay based on Arg3
  *
- * Arg2 == 3:	Set the reset method based on Arg3 (Not supported by this driver)
- * WDISABLE2 (BT_RF_KILL_N)
- * VSEC (PCI Config Space)
+ * Arg2 == 2:	Reserved
+ *
+ * Arg2 == 3:	Set the reset method based on Arg3 (required by Linux driver)
+ * Arg3 is a 4-byte buffer: [0x01, 0x00, type, 0x00]
+ *   type 0 = WDISABLE2 (BT_RF_KILL_N) - supported by this driver
+ *   type 1 = VSEC (PCI Config Space) - not supported
  */
 
 static void check_reset_delay(void *arg)
 {
 	acpigen_write_if_lequal_op_int(ARG1_OP, 0);
 	{
-		acpigen_write_return_singleton_buffer(0x03);
+		/* Bits 0, 1, 3: other funcs, reset timing, set reset method (Linux) */
+		acpigen_write_return_singleton_buffer(0x0b);
 	}
 	acpigen_write_else();
 	{
@@ -37,12 +41,26 @@ static void set_reset_delay(void *arg)
 	acpigen_write_store_op_to_namestr(ARG3_OP, "RDLY");
 }
 
+static void set_reset_method(void *arg)
+{
+	/*
+	 * coreboot only supports WDISABLE2 (GPIO). Linux sends type in Arg3[2].
+	 * Accept and return success - _RST already implements GPIO toggle.
+	 */
+	acpigen_write_return_singleton_buffer(0x01);
+}
+
 static void not_supported(void *arg)
 {
 	acpigen_write_return_singleton_buffer(0x00);
 }
 
-void (*reset_supported[])(void *) = { check_reset_delay, set_reset_delay };
+void (*reset_supported[])(void *) = {
+	check_reset_delay,	/* 0: capability query */
+	set_reset_delay,	/* 1: set delay */
+	not_supported,		/* 2: reserved */
+	set_reset_method,	/* 3: set reset method (required by Linux) */
+};
 void (*reset_unsupported[])(void *) = { not_supported };
 
 void acpi_device_intel_bt(const struct acpi_gpio *enable_gpio,
@@ -55,9 +73,9 @@ void acpi_device_intel_bt(const struct acpi_gpio *enable_gpio,
 	acpigen_write_name_integer("_S0W", ACPI_DEVICE_SLEEP_D2);
 
 /*
- *	Name (RDLY, 0x69)
+ *	Name (RDLY, 160)  // ms, matches Linux driver default
  */
-	acpigen_write_name_integer("RDLY", 0x69);
+	acpigen_write_name_integer("RDLY", 160);
 
 /*
  *	Method (_DSM, 4, Serialized)

From f8494fbeae6bdde1b2f5bf1d93e9c7a2be79354b Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Sun, 15 Feb 2026 21:12:13 +0000
Subject: [PATCH 3511/3886] lib: Add devtree_update bootstate hook

Provide a weak devtree_update() hook and invoke it early in ramstage
at BS_PRE_DEVICE. Mainboards can override devtree_update() to
enable/disable devices at runtime based on CMOS/NVRAM settings.

Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: Ic84ddb25e1da050543c230ea457042b8a8a3061f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91250
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
---
 src/include/devtree_update.h | 14 ++++++++++++++
 src/lib/Makefile.mk          |  1 +
 src/lib/devtree_update.c     | 16 ++++++++++++++++
 3 files changed, 31 insertions(+)
 create mode 100644 src/include/devtree_update.h
 create mode 100644 src/lib/devtree_update.c

diff --git a/src/include/devtree_update.h b/src/include/devtree_update.h
new file mode 100644
index 0000000000..b99b689b99
--- /dev/null
+++ b/src/include/devtree_update.h
@@ -0,0 +1,14 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef __DEVTREE_UPDATE_H__
+#define __DEVTREE_UPDATE_H__
+
+/*
+ * Optional mainboard hook to update devicetree runtime enable/disable state
+ * based on CMOS/NVRAM settings.
+ *
+ * This function is called early in ramstage at BS_PRE_DEVICE.
+ */
+void devtree_update(void);
+
+#endif /* __DEVTREE_UPDATE_H__ */
diff --git a/src/lib/Makefile.mk b/src/lib/Makefile.mk
index 3ffdfa807c..0dc41ce921 100644
--- a/src/lib/Makefile.mk
+++ b/src/lib/Makefile.mk
@@ -155,6 +155,7 @@ ramstage-$(CONFIG_BOOTSPLASH) += bootsplash.c
 ramstage-$(CONFIG_BOOTSPLASH) += jpeg.c
 ramstage-$(CONFIG_COLLECT_TIMESTAMPS) += timestamp.c
 ramstage-$(CONFIG_COVERAGE) += libgcov.c
+ramstage-y += devtree_update.c
 ramstage-y += dp_aux.c
 ramstage-y += framebuffer_info.c
 ramstage-y += edid.c
diff --git a/src/lib/devtree_update.c b/src/lib/devtree_update.c
new file mode 100644
index 0000000000..1b454a2580
--- /dev/null
+++ b/src/lib/devtree_update.c
@@ -0,0 +1,16 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <bootstate.h>
+#include <commonlib/bsd/compiler.h>
+#include <devtree_update.h>
+
+__weak void devtree_update(void)
+{
+}
+
+static void run_devtree_update(void *unused)
+{
+	devtree_update();
+}
+
+BOOT_STATE_INIT_ENTRY(BS_PRE_DEVICE, BS_ON_ENTRY, run_devtree_update, NULL);

From 7bee4f5efbcad847e175e83c192017a4eec48bce Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Sun, 15 Feb 2026 21:13:00 +0000
Subject: [PATCH 3512/3886] mb/starlabs: Drop explicit devtree_update calls

devtree_update() is invoked automatically at BS_PRE_DEVICE. Remove the
per-board init_mainboard() calls and associated includes.

Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: Ifb44080dc2e785a8554f5404902540daa9e872d1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90990
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
---
 src/mainboard/starlabs/byte_adl/mainboard.c     |  3 ---
 src/mainboard/starlabs/lite/mainboard.c         |  2 --
 src/mainboard/starlabs/starbook/mainboard.c     |  2 --
 src/mainboard/starlabs/starfighter/mainboard.c  |  3 ---
 src/mainboard/starlabs/starlite_adl/mainboard.c | 12 +++---------
 5 files changed, 3 insertions(+), 19 deletions(-)

diff --git a/src/mainboard/starlabs/byte_adl/mainboard.c b/src/mainboard/starlabs/byte_adl/mainboard.c
index 60e65ee8c4..cd46529c0f 100644
--- a/src/mainboard/starlabs/byte_adl/mainboard.c
+++ b/src/mainboard/starlabs/byte_adl/mainboard.c
@@ -2,7 +2,6 @@
 
 #include <device/device.h>
 #include <soc/ramstage.h>
-#include <option.h>
 #include <variants.h>
 
 static void init_mainboard(void *chip_info)
@@ -12,8 +11,6 @@ static void init_mainboard(void *chip_info)
 
 	pads = variant_gpio_table(&num);
 	gpio_configure_pads(pads, num);
-
-	devtree_update();
 }
 
 struct chip_operations mainboard_ops = {
diff --git a/src/mainboard/starlabs/lite/mainboard.c b/src/mainboard/starlabs/lite/mainboard.c
index 04537094d0..cd46529c0f 100644
--- a/src/mainboard/starlabs/lite/mainboard.c
+++ b/src/mainboard/starlabs/lite/mainboard.c
@@ -11,8 +11,6 @@ static void init_mainboard(void *chip_info)
 
 	pads = variant_gpio_table(&num);
 	gpio_configure_pads(pads, num);
-
-	devtree_update();
 }
 
 struct chip_operations mainboard_ops = {
diff --git a/src/mainboard/starlabs/starbook/mainboard.c b/src/mainboard/starlabs/starbook/mainboard.c
index 772e32cc1c..f392ed8759 100644
--- a/src/mainboard/starlabs/starbook/mainboard.c
+++ b/src/mainboard/starlabs/starbook/mainboard.c
@@ -13,8 +13,6 @@ static void init_mainboard(void *chip_info)
 
 	pads = variant_gpio_table(&num);
 	gpio_configure_pads(pads, num);
-
-	devtree_update();
 }
 
 struct chip_operations mainboard_ops = {
diff --git a/src/mainboard/starlabs/starfighter/mainboard.c b/src/mainboard/starlabs/starfighter/mainboard.c
index 60e65ee8c4..cd46529c0f 100644
--- a/src/mainboard/starlabs/starfighter/mainboard.c
+++ b/src/mainboard/starlabs/starfighter/mainboard.c
@@ -2,7 +2,6 @@
 
 #include <device/device.h>
 #include <soc/ramstage.h>
-#include <option.h>
 #include <variants.h>
 
 static void init_mainboard(void *chip_info)
@@ -12,8 +11,6 @@ static void init_mainboard(void *chip_info)
 
 	pads = variant_gpio_table(&num);
 	gpio_configure_pads(pads, num);
-
-	devtree_update();
 }
 
 struct chip_operations mainboard_ops = {
diff --git a/src/mainboard/starlabs/starlite_adl/mainboard.c b/src/mainboard/starlabs/starlite_adl/mainboard.c
index b82e2c0eba..1583ad9094 100644
--- a/src/mainboard/starlabs/starlite_adl/mainboard.c
+++ b/src/mainboard/starlabs/starlite_adl/mainboard.c
@@ -3,7 +3,6 @@
 #include <acpi/acpigen_ps2_keybd.h>
 #include <device/device.h>
 #include <soc/ramstage.h>
-#include <option.h>
 #include <variants.h>
 
 static void init_mainboard(void *chip_info)
@@ -13,18 +12,13 @@ static void init_mainboard(void *chip_info)
 
 	pads = variant_gpio_table(&num);
 	gpio_configure_pads(pads, num);
-
-	devtree_update();
 }
 
 static void mainboard_fill_ssdt(const struct device *dev)
 {
-	enum ps2_action_key ps2_action_keys[2] = {
-		PS2_KEY_VOL_DOWN,
-		PS2_KEY_VOL_UP
-	};
-	acpigen_ps2_keyboard_dsd("_SB.PCI0.PS2K", ARRAY_SIZE(ps2_action_keys),
-		ps2_action_keys, false, false, false, false, false);
+	enum ps2_action_key ps2_action_keys[2] = {PS2_KEY_VOL_DOWN, PS2_KEY_VOL_UP};
+	acpigen_ps2_keyboard_dsd("_SB.PCI0.PS2K", ARRAY_SIZE(ps2_action_keys), ps2_action_keys,
+				 false, false, false, false, false);
 }
 
 static void enable_mainboard(struct device *dev)

From 74d4fac21048dac022914f2744bc8b63624448c4 Mon Sep 17 00:00:00 2001
From: Jeremy Compostella <jeremy.compostella@intel.com>
Date: Thu, 26 Feb 2026 09:16:06 -0800
Subject: [PATCH 3513/3886] soc/intel/common/feature/soundwire: Add common
 SoundWire driver

Add a common implementation of soc_fill_soundwire_controller() to reduce
code duplication across multiple Intel SoC platforms. This
implementation consolidates identical SoundWire link configuration code
from Alder Lake, Meteor Lake, Panther Lake, and Tiger Lake platforms.

The common driver uses platform-specific Kconfig options:
- SOC_SOUNDWIRE_ACPI_ADDRESS: ACPI address for the controller
  (default 0x40000000)
- SOC_SOUNDWIRE_MASTER_COUNT: Number of SoundWire master links
  (default 4)

Platforms can override these defaults in their Kconfig if needed.

This change enables consolidation of nearly identical soundwire.c files
across four platforms, reducing duplication by approximately 210 lines.

Change-Id: I5e188b0b60da91a33cf0325caefbbcabef0ebcba
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91276
Reviewed-by: Huang, Cliff <cliff.huang@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 .../intel/common/feature/soundwire/Kconfig    | 24 +++++++
 .../common/feature/soundwire/Makefile.mk      |  3 +
 .../common/feature/soundwire/soundwire.c      | 71 +++++++++++++++++++
 3 files changed, 98 insertions(+)
 create mode 100644 src/soc/intel/common/feature/soundwire/Kconfig
 create mode 100644 src/soc/intel/common/feature/soundwire/Makefile.mk
 create mode 100644 src/soc/intel/common/feature/soundwire/soundwire.c

diff --git a/src/soc/intel/common/feature/soundwire/Kconfig b/src/soc/intel/common/feature/soundwire/Kconfig
new file mode 100644
index 0000000000..c53b0e39b8
--- /dev/null
+++ b/src/soc/intel/common/feature/soundwire/Kconfig
@@ -0,0 +1,24 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
+config SOC_INTEL_COMMON_FEATURE_SOUNDWIRE
+	bool
+	help
+	  Intel Processor Common SoundWire support. This provides a common
+	  implementation of soc_fill_soundwire_controller() for platforms
+	  that use the same SoundWire link configuration. The platform must
+	  define SOC_SOUNDWIRE_ACPI_ADDRESS and SOC_SOUNDWIRE_MASTER_COUNT
+	  in their Kconfig.
+
+config SOC_SOUNDWIRE_ACPI_ADDRESS
+	hex
+	default 0x40000000
+	depends on SOC_INTEL_COMMON_FEATURE_SOUNDWIRE
+	help
+	  ACPI address for the SoundWire controller.
+
+config SOC_SOUNDWIRE_MASTER_COUNT
+	int
+	default 4
+	depends on SOC_INTEL_COMMON_FEATURE_SOUNDWIRE
+	help
+	  Number of SoundWire master interfaces supported by the platform.
diff --git a/src/soc/intel/common/feature/soundwire/Makefile.mk b/src/soc/intel/common/feature/soundwire/Makefile.mk
new file mode 100644
index 0000000000..a668fdbaa9
--- /dev/null
+++ b/src/soc/intel/common/feature/soundwire/Makefile.mk
@@ -0,0 +1,3 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
+ramstage-$(CONFIG_SOC_INTEL_COMMON_FEATURE_SOUNDWIRE) += soundwire.c
diff --git a/src/soc/intel/common/feature/soundwire/soundwire.c b/src/soc/intel/common/feature/soundwire/soundwire.c
new file mode 100644
index 0000000000..d9528df1a7
--- /dev/null
+++ b/src/soc/intel/common/feature/soundwire/soundwire.c
@@ -0,0 +1,71 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <acpi/acpi_soundwire.h>
+#include <console/console.h>
+#include <device/mmio.h>
+#include <device/soundwire.h>
+#include <drivers/intel/soundwire/soundwire.h>
+#include <intelblocks/pmclib.h>
+#include <stddef.h>
+#include <string.h>
+
+static const struct soundwire_link link_xtal_38_4 = {
+	.clock_stop_mode0_supported = 1,
+	.clock_stop_mode1_supported = 1,
+	.clock_frequencies_supported_count = 1,
+	.clock_frequencies_supported = { 4800 * KHz },
+	.default_frame_rate = 48 * KHz,
+	.default_frame_row_size = 50,
+	.default_frame_col_size = 4,
+	.dynamic_frame_shape = 1,
+	.command_error_threshold = 16,
+};
+
+static const struct soundwire_link link_xtal_24 = {
+	.clock_stop_mode0_supported = 1,
+	.clock_stop_mode1_supported = 1,
+	.clock_frequencies_supported_count = 1,
+	.clock_frequencies_supported = { 6 * MHz },
+	.default_frame_rate = 48 * KHz,
+	.default_frame_row_size = 125,
+	.default_frame_col_size = 2,
+	.dynamic_frame_shape = 1,
+	.command_error_threshold = 16,
+};
+
+static struct intel_soundwire_controller intel_controller = {
+	.acpi_address = CONFIG_SOC_SOUNDWIRE_ACPI_ADDRESS,
+	.sdw = {
+		.master_list_count = CONFIG_SOC_SOUNDWIRE_MASTER_COUNT
+	}
+};
+
+int soc_fill_soundwire_controller(struct intel_soundwire_controller **controller)
+{
+	const struct soundwire_link *link;
+	enum pch_pmc_xtal xtal = pmc_get_xtal_freq();
+	size_t i;
+
+	/* Select link config based on XTAL frequency and set IP clock. */
+	switch (xtal) {
+	case XTAL_24_MHZ:
+		link = &link_xtal_24;
+		intel_controller.ip_clock = 24 * MHz;
+		break;
+	case XTAL_38_4_MHZ:
+		link = &link_xtal_38_4;
+		intel_controller.ip_clock = 38400 * KHz;
+		break;
+	case XTAL_19_2_MHZ:
+	default:
+		printk(BIOS_ERR, "%s: XTAL not supported: 0x%x\n", __func__, xtal);
+		return -1;
+	}
+
+	/* Fill link config in controller map based on selected XTAL. */
+	for (i = 0; i < intel_controller.sdw.master_list_count; i++)
+		memcpy(&intel_controller.sdw.master_list[i], link, sizeof(*link));
+
+	*controller = &intel_controller;
+	return 0;
+}

From ef364d623d06c12858acb321e1e81c6f25cdc068 Mon Sep 17 00:00:00 2001
From: Jeremy Compostella <jeremy.compostella@intel.com>
Date: Thu, 26 Feb 2026 09:16:31 -0800
Subject: [PATCH 3514/3886] soc/intel/alderlake: Use common SoundWire driver

Migrate Alder Lake to use the common SoundWire driver implementation
from the Intel common feature code. This change eliminates platform-
specific code by leveraging the shared soundwire.c driver.

This commit:
- Selects SOC_INTEL_COMMON_FEATURE_SOUNDWIRE Kconfig
- Removes src/soc/intel/alderlake/soundwire.c
- Updates Makefile to remove soundwire.c compilation

Alder Lake uses the default values (4 SoundWire master links with ACPI
address 0x40000000).

Change-Id: Idf21d32d0cab9e3c6ca35e2b9f20c42c0455b5bb
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91277
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Huang, Cliff <cliff.huang@intel.com>
---
 src/soc/intel/alderlake/Kconfig     |  1 +
 src/soc/intel/alderlake/Makefile.mk |  1 -
 src/soc/intel/alderlake/soundwire.c | 71 -----------------------------
 3 files changed, 1 insertion(+), 72 deletions(-)
 delete mode 100644 src/soc/intel/alderlake/soundwire.c

diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig
index 52c3d84dca..be44a9eabb 100644
--- a/src/soc/intel/alderlake/Kconfig
+++ b/src/soc/intel/alderlake/Kconfig
@@ -86,6 +86,7 @@ config SOC_INTEL_ALDERLAKE
 	select SOC_INTEL_COMMON_BLOCK_XHCI_ELOG
 	select SOC_INTEL_COMMON_FEATURE
 	select SOC_INTEL_COMMON_FEATURE_GSPI_DEVFN
+	select SOC_INTEL_COMMON_FEATURE_SOUNDWIRE
 	select SOC_INTEL_COMMON_FEATURE_SPI_DEVFN
 	select SOC_INTEL_COMMON_FEATURE_SPI_DEVFN_PSF
 	select SOC_INTEL_COMMON_FEATURE_I2C_DEVFN
diff --git a/src/soc/intel/alderlake/Makefile.mk b/src/soc/intel/alderlake/Makefile.mk
index f287e91322..5d604a994a 100644
--- a/src/soc/intel/alderlake/Makefile.mk
+++ b/src/soc/intel/alderlake/Makefile.mk
@@ -35,7 +35,6 @@ ramstage-y += pcie_rp.c
 ramstage-y += pmc.c
 ramstage-y += reset.c
 ramstage-$(CONFIG_SOC_INTEL_ALDERLAKE_TCSS_USB4_SUPPORT) += retimer.c
-ramstage-y += soundwire.c
 ramstage-y += systemagent.c
 ramstage-y += tcss.c
 ramstage-y += vr_config.c
diff --git a/src/soc/intel/alderlake/soundwire.c b/src/soc/intel/alderlake/soundwire.c
deleted file mode 100644
index 1fbdb4418e..0000000000
--- a/src/soc/intel/alderlake/soundwire.c
+++ /dev/null
@@ -1,71 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <acpi/acpi_soundwire.h>
-#include <console/console.h>
-#include <device/mmio.h>
-#include <device/soundwire.h>
-#include <drivers/intel/soundwire/soundwire.h>
-#include <intelblocks/pmclib.h>
-#include <stddef.h>
-#include <string.h>
-
-static const struct soundwire_link link_xtal_38_4 = {
-	.clock_stop_mode0_supported = 1,
-	.clock_stop_mode1_supported = 1,
-	.clock_frequencies_supported_count = 1,
-	.clock_frequencies_supported = { 4800 * KHz },
-	.default_frame_rate = 48 * KHz,
-	.default_frame_row_size = 50,
-	.default_frame_col_size = 4,
-	.dynamic_frame_shape = 1,
-	.command_error_threshold = 16,
-};
-
-static const struct soundwire_link link_xtal_24 = {
-	.clock_stop_mode0_supported = 1,
-	.clock_stop_mode1_supported = 1,
-	.clock_frequencies_supported_count = 1,
-	.clock_frequencies_supported = { 6 * MHz },
-	.default_frame_rate = 48 * KHz,
-	.default_frame_row_size = 125,
-	.default_frame_col_size = 2,
-	.dynamic_frame_shape = 1,
-	.command_error_threshold = 16,
-};
-
-static struct intel_soundwire_controller intel_controller = {
-	.acpi_address = 0x40000000,
-	.sdw = {
-		.master_list_count = 4
-	}
-};
-
-int soc_fill_soundwire_controller(struct intel_soundwire_controller **controller)
-{
-	const struct soundwire_link *link;
-	enum pch_pmc_xtal xtal = pmc_get_xtal_freq();
-	size_t i;
-
-	/* Select link config based on XTAL frequency and set IP clock. */
-	switch (xtal) {
-	case XTAL_24_MHZ:
-		link = &link_xtal_24;
-		intel_controller.ip_clock = 24 * MHz;
-		break;
-	case XTAL_38_4_MHZ:
-		link = &link_xtal_38_4;
-		intel_controller.ip_clock = 38400 * KHz;
-		break;
-	case XTAL_19_2_MHZ:
-	default:
-		printk(BIOS_ERR, "%s: XTAL not supported: 0x%x\n", __func__, xtal);
-		return -1;
-	}
-
-	/* Fill link config in controller map based on selected XTAL. */
-	for (i = 0; i < intel_controller.sdw.master_list_count; i++)
-		memcpy(&intel_controller.sdw.master_list[i], link, sizeof(*link));
-
-	*controller = &intel_controller;
-	return 0;
-}

From ffc67b2938b494271738b49b86577ef280a893bc Mon Sep 17 00:00:00 2001
From: Jeremy Compostella <jeremy.compostella@intel.com>
Date: Thu, 26 Feb 2026 09:16:49 -0800
Subject: [PATCH 3515/3886] soc/intel/meteorlake: Use common SoundWire driver

Migrate Meteor Lake to use the common SoundWire driver implementation
from the Intel common feature code. This change eliminates platform-
specific code by leveraging the shared soundwire.c driver.

This commit:
- Selects SOC_INTEL_COMMON_FEATURE_SOUNDWIRE Kconfig
- Removes src/soc/intel/meteorlake/soundwire.c
- Updates Makefile to remove soundwire.c compilation

Meteor Lake uses the default values (4 SoundWire master links with ACPI
address 0x40000000).

Change-Id: Ib6d412b22cce78caf56ca2d09fcf74e57f54d09c
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91278
Reviewed-by: Huang, Cliff <cliff.huang@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/soc/intel/meteorlake/Kconfig     |  1 +
 src/soc/intel/meteorlake/Makefile.mk |  1 -
 src/soc/intel/meteorlake/soundwire.c | 72 ----------------------------
 3 files changed, 1 insertion(+), 73 deletions(-)
 delete mode 100644 src/soc/intel/meteorlake/soundwire.c

diff --git a/src/soc/intel/meteorlake/Kconfig b/src/soc/intel/meteorlake/Kconfig
index 566bc05bda..8601557650 100644
--- a/src/soc/intel/meteorlake/Kconfig
+++ b/src/soc/intel/meteorlake/Kconfig
@@ -88,6 +88,7 @@ config SOC_INTEL_METEORLAKE
 	select SOC_INTEL_COMMON_BLOCK_XHCI_ELOG
 	select SOC_INTEL_COMMON_FEATURE
 	select SOC_INTEL_COMMON_FEATURE_GSPI_DEVFN
+	select SOC_INTEL_COMMON_FEATURE_SOUNDWIRE
 	select SOC_INTEL_COMMON_FEATURE_SPI_DEVFN
 	select SOC_INTEL_COMMON_FEATURE_SPI_DEVFN_PSF
 	select SOC_INTEL_COMMON_FEATURE_I2C_DEVFN
diff --git a/src/soc/intel/meteorlake/Makefile.mk b/src/soc/intel/meteorlake/Makefile.mk
index d2192c0483..3b3a2d7703 100644
--- a/src/soc/intel/meteorlake/Makefile.mk
+++ b/src/soc/intel/meteorlake/Makefile.mk
@@ -39,7 +39,6 @@ ramstage-y += pcie_rp.c
 ramstage-y += pmc.c
 ramstage-y += reset.c
 ramstage-y += retimer.c
-ramstage-y += soundwire.c
 ramstage-y += systemagent.c
 ramstage-y += tcss.c
 ramstage-y += xhci.c
diff --git a/src/soc/intel/meteorlake/soundwire.c b/src/soc/intel/meteorlake/soundwire.c
deleted file mode 100644
index c3ff05d2e3..0000000000
--- a/src/soc/intel/meteorlake/soundwire.c
+++ /dev/null
@@ -1,72 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <acpi/acpi_soundwire.h>
-#include <console/console.h>
-#include <device/mmio.h>
-#include <device/soundwire.h>
-#include <drivers/intel/soundwire/soundwire.h>
-#include <intelblocks/pmclib.h>
-#include <soc/pmc.h>
-#include <stddef.h>
-#include <string.h>
-
-static const struct soundwire_link link_xtal_38_4 = {
-	.clock_stop_mode0_supported = 1,
-	.clock_stop_mode1_supported = 1,
-	.clock_frequencies_supported_count = 1,
-	.clock_frequencies_supported = { 4800 * KHz },
-	.default_frame_rate = 48 * KHz,
-	.default_frame_row_size = 50,
-	.default_frame_col_size = 4,
-	.dynamic_frame_shape = 1,
-	.command_error_threshold = 16,
-};
-
-static const struct soundwire_link link_xtal_24 = {
-	.clock_stop_mode0_supported = 1,
-	.clock_stop_mode1_supported = 1,
-	.clock_frequencies_supported_count = 1,
-	.clock_frequencies_supported = { 6 * MHz },
-	.default_frame_rate = 48 * KHz,
-	.default_frame_row_size = 125,
-	.default_frame_col_size = 2,
-	.dynamic_frame_shape = 1,
-	.command_error_threshold = 16,
-};
-
-static struct intel_soundwire_controller intel_controller = {
-	.acpi_address = 0x40000000,
-	.sdw = {
-		.master_list_count = 4
-	}
-};
-
-int soc_fill_soundwire_controller(struct intel_soundwire_controller **controller)
-{
-	const struct soundwire_link *link;
-	enum pch_pmc_xtal xtal = pmc_get_xtal_freq();
-	size_t i;
-
-	/* Select link config based on XTAL frequency and set IP clock. */
-	switch (xtal) {
-	case XTAL_24_MHZ:
-		link = &link_xtal_24;
-		intel_controller.ip_clock = 24 * MHz;
-		break;
-	case XTAL_38_4_MHZ:
-		link = &link_xtal_38_4;
-		intel_controller.ip_clock = 38400 * KHz;
-		break;
-	case XTAL_19_2_MHZ:
-	default:
-		printk(BIOS_ERR, "%s: XTAL not supported: 0x%x\n", __func__, xtal);
-		return -1;
-	}
-
-	/* Fill link config in controller map based on selected XTAL. */
-	for (i = 0; i < intel_controller.sdw.master_list_count; i++)
-		memcpy(&intel_controller.sdw.master_list[i], link, sizeof(*link));
-
-	*controller = &intel_controller;
-	return 0;
-}

From 620a33f1c85d0b9534592e51e2d13918c406c120 Mon Sep 17 00:00:00 2001
From: Jeremy Compostella <jeremy.compostella@intel.com>
Date: Thu, 26 Feb 2026 09:17:08 -0800
Subject: [PATCH 3516/3886] soc/intel/pantherlake: Use common SoundWire driver

Migrate Panther Lake to use the common SoundWire driver implementation
from the Intel common feature code. This change eliminates platform-
specific code by leveraging the shared soundwire.c driver.

This commit:
- Selects SOC_INTEL_COMMON_FEATURE_SOUNDWIRE Kconfig
- Removes src/soc/intel/pantherlake/soundwire.c
- Updates Makefile to remove soundwire.c compilation

Panther Lake uses the default values (4 SoundWire master links with ACPI
address 0x40000000).

TEST=Build and boot to the OS on a Fatcat device

Change-Id: Iaebb27ddc44da536c8e6a6aece1dfee3a4ac7bac
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91279
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Huang, Cliff <cliff.huang@intel.com>
---
 src/soc/intel/pantherlake/Kconfig     |  1 +
 src/soc/intel/pantherlake/Makefile.mk |  1 -
 src/soc/intel/pantherlake/soundwire.c | 72 ---------------------------
 3 files changed, 1 insertion(+), 73 deletions(-)
 delete mode 100644 src/soc/intel/pantherlake/soundwire.c

diff --git a/src/soc/intel/pantherlake/Kconfig b/src/soc/intel/pantherlake/Kconfig
index 33a592cb07..243b9fa41f 100644
--- a/src/soc/intel/pantherlake/Kconfig
+++ b/src/soc/intel/pantherlake/Kconfig
@@ -98,6 +98,7 @@ config SOC_INTEL_PANTHERLAKE_BASE
 	select SOC_INTEL_COMMON_BLOCK_XHCI_ELOG
 	select SOC_INTEL_COMMON_FEATURE
 	select SOC_INTEL_COMMON_FEATURE_GSPI_DEVFN
+	select SOC_INTEL_COMMON_FEATURE_SOUNDWIRE
 	select SOC_INTEL_COMMON_FEATURE_SPI_DEVFN
 	select SOC_INTEL_COMMON_FEATURE_SPI_DEVFN_PSF
 	select SOC_INTEL_COMMON_FEATURE_I2C_DEVFN
diff --git a/src/soc/intel/pantherlake/Makefile.mk b/src/soc/intel/pantherlake/Makefile.mk
index 857e7ab648..361b583839 100644
--- a/src/soc/intel/pantherlake/Makefile.mk
+++ b/src/soc/intel/pantherlake/Makefile.mk
@@ -37,7 +37,6 @@ ramstage-y += pcie_rp.c
 ramstage-y += pmc.c
 ramstage-y += reset.c
 ramstage-y += retimer.c
-ramstage-y += soundwire.c
 ramstage-y += systemagent.c
 ramstage-y += tcss.c
 ramstage-y += tdp.c
diff --git a/src/soc/intel/pantherlake/soundwire.c b/src/soc/intel/pantherlake/soundwire.c
deleted file mode 100644
index ab1d0bc683..0000000000
--- a/src/soc/intel/pantherlake/soundwire.c
+++ /dev/null
@@ -1,72 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <acpi/acpi_soundwire.h>
-#include <console/console.h>
-#include <device/mmio.h>
-#include <device/soundwire.h>
-#include <drivers/intel/soundwire/soundwire.h>
-#include <intelblocks/pmclib.h>
-#include <soc/pmc.h>
-#include <stddef.h>
-#include <string.h>
-
-static const struct soundwire_link link_xtal_38_4 = {
-	.clock_stop_mode0_supported = 1,
-	.clock_stop_mode1_supported = 1,
-	.clock_frequencies_supported_count = 1,
-	.clock_frequencies_supported = { 4800 * KHz },
-	.default_frame_rate = 48 * KHz,
-	.default_frame_row_size = 50,
-	.default_frame_col_size = 4,
-	.dynamic_frame_shape = 1,
-	.command_error_threshold = 16,
-};
-
-static const struct soundwire_link link_xtal_24 = {
-	.clock_stop_mode0_supported = 1,
-	.clock_stop_mode1_supported = 1,
-	.clock_frequencies_supported_count = 1,
-	.clock_frequencies_supported = { 6 * MHz },
-	.default_frame_rate = 48 * KHz,
-	.default_frame_row_size = 125,
-	.default_frame_col_size = 2,
-	.dynamic_frame_shape = 1,
-	.command_error_threshold = 16,
-};
-
-static struct intel_soundwire_controller intel_controller = {
-	.acpi_address = 0x40000000, /* Custom address for SNDW driver */
-	.sdw = {
-		.master_list_count = 4
-	}
-};
-
-int soc_fill_soundwire_controller(struct intel_soundwire_controller **controller)
-{
-	const struct soundwire_link *link;
-	enum pch_pmc_xtal xtal = pmc_get_xtal_freq();
-	size_t i;
-
-	/* Select link config based on XTAL frequency and set IP clock. */
-	switch (xtal) {
-	case XTAL_24_MHZ:
-		link = &link_xtal_24;
-		intel_controller.ip_clock = 24 * MHz;
-		break;
-	case XTAL_38_4_MHZ:
-		link = &link_xtal_38_4;
-		intel_controller.ip_clock = 38400 * KHz;
-		break;
-	case XTAL_19_2_MHZ:
-	default:
-		printk(BIOS_ERR, "%s: XTAL not supported: 0x%x\n", __func__, xtal);
-		return -1;
-	}
-
-	/* Fill link config in controller map based on selected XTAL. */
-	for (i = 0; i < intel_controller.sdw.master_list_count; i++)
-		memcpy(&intel_controller.sdw.master_list[i], link, sizeof(*link));
-
-	*controller = &intel_controller;
-	return 0;
-}

From f780b7c576bc7df13b706c649ac8b6879c9e4958 Mon Sep 17 00:00:00 2001
From: Jeremy Compostella <jeremy.compostella@intel.com>
Date: Thu, 26 Feb 2026 09:17:26 -0800
Subject: [PATCH 3517/3886] soc/intel/tigerlake: Use common SoundWire driver

Migrate Tiger Lake to use the common SoundWire driver implementation
from the Intel common feature code. This change eliminates platform-
specific code by leveraging the shared soundwire.c driver.

This commit:
- Selects SOC_INTEL_COMMON_FEATURE_SOUNDWIRE Kconfig
- Removes src/soc/intel/tigerlake/soundwire.c
- Updates Makefile to remove soundwire.c compilation

Tiger Lake uses the default values (4 SoundWire master links with ACPI
address 0x40000000).

Change-Id: Ife743d28c8760d9de3f593f7d8caafd7a73efe3a
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91280
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Huang, Cliff <cliff.huang@intel.com>
---
 src/soc/intel/tigerlake/Kconfig     |  1 +
 src/soc/intel/tigerlake/Makefile.mk |  1 -
 src/soc/intel/tigerlake/soundwire.c | 70 -----------------------------
 3 files changed, 1 insertion(+), 71 deletions(-)
 delete mode 100644 src/soc/intel/tigerlake/soundwire.c

diff --git a/src/soc/intel/tigerlake/Kconfig b/src/soc/intel/tigerlake/Kconfig
index 5168546661..b136c3354b 100644
--- a/src/soc/intel/tigerlake/Kconfig
+++ b/src/soc/intel/tigerlake/Kconfig
@@ -74,6 +74,7 @@ config SOC_INTEL_TIGERLAKE
 	select SOC_INTEL_COMMON_BLOCK_XHCI_ELOG
 	select SOC_INTEL_COMMON_FEATURE
 	select SOC_INTEL_COMMON_FEATURE_GSPI_DEVFN
+	select SOC_INTEL_COMMON_FEATURE_SOUNDWIRE
 	select SOC_INTEL_COMMON_FEATURE_SPI_DEVFN
 	select SOC_INTEL_COMMON_FEATURE_SPI_DEVFN_PSF
 	select SOC_INTEL_COMMON_FEATURE_I2C_DEVFN
diff --git a/src/soc/intel/tigerlake/Makefile.mk b/src/soc/intel/tigerlake/Makefile.mk
index 074f172d38..973ad0f015 100644
--- a/src/soc/intel/tigerlake/Makefile.mk
+++ b/src/soc/intel/tigerlake/Makefile.mk
@@ -34,7 +34,6 @@ ramstage-y += pcie_rp.c
 ramstage-y += pmc.c
 ramstage-y += reset.c
 ramstage-y += retimer.c
-ramstage-y += soundwire.c
 ramstage-y += systemagent.c
 ramstage-y += tcss.c
 ramstage-y += xhci.c
diff --git a/src/soc/intel/tigerlake/soundwire.c b/src/soc/intel/tigerlake/soundwire.c
deleted file mode 100644
index 878ce1973c..0000000000
--- a/src/soc/intel/tigerlake/soundwire.c
+++ /dev/null
@@ -1,70 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <acpi/acpi_soundwire.h>
-#include <console/console.h>
-#include <device/mmio.h>
-#include <device/soundwire.h>
-#include <drivers/intel/soundwire/soundwire.h>
-#include <intelblocks/pmclib.h>
-#include <string.h>
-
-static const struct soundwire_link link_xtal_38_4 = {
-	.clock_stop_mode0_supported = 1,
-	.clock_stop_mode1_supported = 1,
-	.clock_frequencies_supported_count = 1,
-	.clock_frequencies_supported = { 4800 * KHz },
-	.default_frame_rate = 48 * KHz,
-	.default_frame_row_size = 50,
-	.default_frame_col_size = 4,
-	.dynamic_frame_shape = 1,
-	.command_error_threshold = 16,
-};
-
-static const struct soundwire_link link_xtal_24 = {
-	.clock_stop_mode0_supported = 1,
-	.clock_stop_mode1_supported = 1,
-	.clock_frequencies_supported_count = 1,
-	.clock_frequencies_supported = { 6 * MHz },
-	.default_frame_rate = 48 * KHz,
-	.default_frame_row_size = 125,
-	.default_frame_col_size = 2,
-	.dynamic_frame_shape = 1,
-	.command_error_threshold = 16,
-};
-
-static struct intel_soundwire_controller intel_controller = {
-	.acpi_address = 0x40000000,
-	.sdw = {
-		.master_list_count = 4
-	}
-};
-
-int soc_fill_soundwire_controller(struct intel_soundwire_controller **controller)
-{
-	const struct soundwire_link *link;
-	enum pch_pmc_xtal xtal = pmc_get_xtal_freq();
-	size_t i;
-
-	/* Select link config based on XTAL frequency and set IP clock. */
-	switch (xtal) {
-	case XTAL_24_MHZ:
-		link = &link_xtal_24;
-		intel_controller.ip_clock = 24 * MHz;
-		break;
-	case XTAL_38_4_MHZ:
-		link = &link_xtal_38_4;
-		intel_controller.ip_clock = 38400 * KHz;
-		break;
-	case XTAL_19_2_MHZ:
-	default:
-		printk(BIOS_ERR, "%s: XTAL not supported: 0x%x\n", __func__, xtal);
-		return -1;
-	}
-
-	/* Fill link config in controller map based on selected XTAL. */
-	for (i = 0; i < intel_controller.sdw.master_list_count; i++)
-		memcpy(&intel_controller.sdw.master_list[i], link, sizeof(*link));
-
-	*controller = &intel_controller;
-	return 0;
-}

From 0464f1032aec2b74fb595fbfcd0c49090bf0e8cb Mon Sep 17 00:00:00 2001
From: Jeremy Compostella <jeremy.compostella@intel.com>
Date: Thu, 26 Feb 2026 09:38:05 -0800
Subject: [PATCH 3518/3886] soc/intel/common/feature/espi: Add common eSPI/LPC
 initialization

This introduces a common implementation for eSPI/LPC initialization
that handles generic IO decode range configuration and standard
interrupt setup. This code is nearly identical across multiple Intel
client platforms.

The implementation includes:
- soc_get_gen_io_dec_range(): Configures generic IO decode ranges
  from devicetree (gen1_dec through gen4_dec)
- lpc_soc_init(): Performs legacy ISA/DMA initialization, enables
  CLKRUN for power gating, configures Serial IRQ mode, and sets up
  the interrupt controllers (IOAPIC, PIRQ, i8259)

Platform-specific configuration is handled through the config_t
typedef that each platform defines via its soc_chip.h header,
eliminating the need for preprocessor conditionals.

The common driver is enabled via the SOC_INTEL_COMMON_FEATURE_ESPI
Kconfig option and works across bootblock, romstage, and ramstage.

Platforms that will use this common implementation:
- Alder Lake
- Meteor Lake
- Panther Lake
- Tiger Lake
- Jasper Lake
- Elkhart Lake

Change-Id: Idbdecff1cef44dae90afb35ff6e2afca011ea5b4
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91216
Reviewed-by: Huang, Cliff <cliff.huang@intel.com>
Reviewed-by: Guvendik, Bora <bora.guvendik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/soc/intel/common/feature/espi/Kconfig     |  8 ++++
 src/soc/intel/common/feature/espi/Makefile.mk |  5 ++
 src/soc/intel/common/feature/espi/espi.c      | 46 +++++++++++++++++++
 3 files changed, 59 insertions(+)
 create mode 100644 src/soc/intel/common/feature/espi/Kconfig
 create mode 100644 src/soc/intel/common/feature/espi/Makefile.mk
 create mode 100644 src/soc/intel/common/feature/espi/espi.c

diff --git a/src/soc/intel/common/feature/espi/Kconfig b/src/soc/intel/common/feature/espi/Kconfig
new file mode 100644
index 0000000000..521c7bbe5c
--- /dev/null
+++ b/src/soc/intel/common/feature/espi/Kconfig
@@ -0,0 +1,8 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
+config SOC_INTEL_COMMON_FEATURE_ESPI
+	bool
+	help
+	  Select this if the platform supports common eSPI/LPC initialization
+	  with generic IO decode range configuration and standard interrupt
+	  setup. This is applicable for most modern Intel client platforms.
diff --git a/src/soc/intel/common/feature/espi/Makefile.mk b/src/soc/intel/common/feature/espi/Makefile.mk
new file mode 100644
index 0000000000..69542218b3
--- /dev/null
+++ b/src/soc/intel/common/feature/espi/Makefile.mk
@@ -0,0 +1,5 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
+bootblock-$(CONFIG_SOC_INTEL_COMMON_FEATURE_ESPI) += espi.c
+romstage-$(CONFIG_SOC_INTEL_COMMON_FEATURE_ESPI) += espi.c
+ramstage-$(CONFIG_SOC_INTEL_COMMON_FEATURE_ESPI) += espi.c
diff --git a/src/soc/intel/common/feature/espi/espi.c b/src/soc/intel/common/feature/espi/espi.c
new file mode 100644
index 0000000000..b0620c683d
--- /dev/null
+++ b/src/soc/intel/common/feature/espi/espi.c
@@ -0,0 +1,46 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <arch/ioapic.h>
+#include <device/pci.h>
+#include <intelblocks/itss.h>
+#include <intelblocks/lpc_lib.h>
+#include <intelpch/espi.h>
+#include <pc80/i8259.h>
+#include <pc80/isa-dma.h>
+#include <soc/iomap.h>
+#include <soc/irq.h>
+#include <soc/pci_devs.h>
+#include <soc/soc_chip.h>
+#include <static.h>
+
+void soc_get_gen_io_dec_range(uint32_t gen_io_dec[LPC_NUM_GENERIC_IO_RANGES])
+{
+	const config_t *config = config_of_soc();
+
+	gen_io_dec[0] = config->gen1_dec;
+	gen_io_dec[1] = config->gen2_dec;
+	gen_io_dec[2] = config->gen3_dec;
+	gen_io_dec[3] = config->gen4_dec;
+}
+
+void lpc_soc_init(struct device *dev)
+{
+	/* Legacy initialization */
+	isa_dma_init();
+	pch_misc_init();
+
+	/* Enable CLKRUN_EN for power gating ESPI */
+	lpc_enable_pci_clk_cntl();
+
+	/* Set ESPI Serial IRQ mode */
+	if (CONFIG(SERIRQ_CONTINUOUS_MODE))
+		lpc_set_serirq_mode(SERIRQ_CONTINUOUS);
+	else
+		lpc_set_serirq_mode(SERIRQ_QUIET);
+
+	/* Interrupt configuration */
+	pch_enable_ioapic();
+	pch_pirq_init();
+	setup_i8259();
+	i8259_configure_irq_trigger(9, 1);
+}

From 34be3842a18f70ee60ef3055ce3a2064f87ee25b Mon Sep 17 00:00:00 2001
From: Jeremy Compostella <jeremy.compostella@intel.com>
Date: Thu, 26 Feb 2026 09:38:28 -0800
Subject: [PATCH 3519/3886] soc/intel/alderlake: Switch to common eSPI/LPC
 initialization

Replace platform-specific espi.c with the common eSPI/LPC
initialization driver.

Changes:
- Remove src/soc/intel/alderlake/espi.c
- Enable SOC_INTEL_COMMON_FEATURE_ESPI in Kconfig
- Update Makefile.mk to remove espi.c from build

The eSPI/LPC initialization was nearly identical across platforms,
differing only in minor header inclusions and ENV_RAMSTAGE wrapper
usage. The common implementation uses the config_t typedef that
each platform defines, providing clean abstraction without
preprocessor conditionals.

Change-Id: Ifacdd480a9cfd59d9e54faebad82e1cc2db8a8ed
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91217
Reviewed-by: Guvendik, Bora <bora.guvendik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/soc/intel/alderlake/Kconfig     |  1 +
 src/soc/intel/alderlake/Makefile.mk |  3 --
 src/soc/intel/alderlake/espi.c      | 56 -----------------------------
 3 files changed, 1 insertion(+), 59 deletions(-)
 delete mode 100644 src/soc/intel/alderlake/espi.c

diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig
index be44a9eabb..30be64a3e9 100644
--- a/src/soc/intel/alderlake/Kconfig
+++ b/src/soc/intel/alderlake/Kconfig
@@ -85,6 +85,7 @@ config SOC_INTEL_ALDERLAKE
 	select SOC_INTEL_COMMON_BLOCK_XHCI
 	select SOC_INTEL_COMMON_BLOCK_XHCI_ELOG
 	select SOC_INTEL_COMMON_FEATURE
+	select SOC_INTEL_COMMON_FEATURE_ESPI
 	select SOC_INTEL_COMMON_FEATURE_GSPI_DEVFN
 	select SOC_INTEL_COMMON_FEATURE_SOUNDWIRE
 	select SOC_INTEL_COMMON_FEATURE_SPI_DEVFN
diff --git a/src/soc/intel/alderlake/Makefile.mk b/src/soc/intel/alderlake/Makefile.mk
index 5d604a994a..83ae0a8c14 100644
--- a/src/soc/intel/alderlake/Makefile.mk
+++ b/src/soc/intel/alderlake/Makefile.mk
@@ -10,12 +10,10 @@ all-y += pmutil.c
 bootblock-y += bootblock/bootblock.c
 bootblock-y += bootblock/pch.c
 bootblock-y += bootblock/report_platform.c
-bootblock-y += espi.c
 bootblock-y += p2sb.c
 bootblock-$(CONFIG_ALDERLAKE_CONFIGURE_DESCRIPTOR) += bootblock/update_descriptor.c
 
 romstage-$(CONFIG_SOC_INTEL_CSE_PRE_CPU_RESET_TELEMETRY) += cse_telemetry.c
-romstage-y += espi.c
 romstage-y += meminit.c
 romstage-y += pcie_rp.c
 romstage-y += reset.c
@@ -24,7 +22,6 @@ ramstage-y += acpi.c
 ramstage-y += chip.c
 ramstage-y += cpu.c
 ramstage-y += elog.c
-ramstage-y += espi.c
 ramstage-y += finalize.c
 ramstage-y += fsp_params.c
 ramstage-y += graphics.c
diff --git a/src/soc/intel/alderlake/espi.c b/src/soc/intel/alderlake/espi.c
deleted file mode 100644
index bdc41a6a30..0000000000
--- a/src/soc/intel/alderlake/espi.c
+++ /dev/null
@@ -1,56 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-/*
- * This file is created based on Intel Alder Lake Processor PCH Datasheet
- * Document number: 621483
- * Chapter number: 2
- */
-
-#include <device/pci.h>
-#include <pc80/isa-dma.h>
-#include <pc80/i8259.h>
-#include <arch/ioapic.h>
-#include <intelblocks/itss.h>
-#include <intelblocks/lpc_lib.h>
-#include <intelblocks/pcr.h>
-#include <intelpch/espi.h>
-#include <soc/iomap.h>
-#include <soc/irq.h>
-#include <soc/pci_devs.h>
-#include <soc/pcr_ids.h>
-#include <soc/soc_chip.h>
-#include <static.h>
-
-void soc_get_gen_io_dec_range(uint32_t gen_io_dec[LPC_NUM_GENERIC_IO_RANGES])
-{
-	const config_t *config = config_of_soc();
-
-	gen_io_dec[0] = config->gen1_dec;
-	gen_io_dec[1] = config->gen2_dec;
-	gen_io_dec[2] = config->gen3_dec;
-	gen_io_dec[3] = config->gen4_dec;
-}
-
-#if ENV_RAMSTAGE
-void lpc_soc_init(struct device *dev)
-{
-	/* Legacy initialization */
-	isa_dma_init();
-	pch_misc_init();
-
-	/* Enable CLKRUN_EN for power gating ESPI */
-	lpc_enable_pci_clk_cntl();
-
-	/* Set ESPI Serial IRQ mode */
-	if (CONFIG(SERIRQ_CONTINUOUS_MODE))
-		lpc_set_serirq_mode(SERIRQ_CONTINUOUS);
-	else
-		lpc_set_serirq_mode(SERIRQ_QUIET);
-
-	/* Interrupt configuration */
-	pch_enable_ioapic();
-	pch_pirq_init();
-	setup_i8259();
-	i8259_configure_irq_trigger(9, 1);
-}
-#endif

From 4fe7e7fa364a2a07a3a987abae9424c94f0eb711 Mon Sep 17 00:00:00 2001
From: Jeremy Compostella <jeremy.compostella@intel.com>
Date: Thu, 26 Feb 2026 09:38:49 -0800
Subject: [PATCH 3520/3886] soc/intel/meteorlake: Switch to common eSPI/LPC
 initialization

Replace platform-specific espi.c with the common eSPI/LPC
initialization driver.

Changes:
- Remove src/soc/intel/meteorlake/espi.c
- Enable SOC_INTEL_COMMON_FEATURE_ESPI in Kconfig
- Update Makefile.mk to remove espi.c from build

The eSPI/LPC initialization was nearly identical across platforms,
differing only in minor header inclusions and ENV_RAMSTAGE wrapper
usage. The common implementation uses the config_t typedef that
each platform defines, providing clean abstraction without
preprocessor conditionals.

Change-Id: Ifb198964c5eda1fceaec6111cd7fba374bacf1b6
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91218
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Guvendik, Bora <bora.guvendik@intel.com>
---
 src/soc/intel/meteorlake/Kconfig     |  1 +
 src/soc/intel/meteorlake/Makefile.mk |  3 --
 src/soc/intel/meteorlake/espi.c      | 48 ----------------------------
 3 files changed, 1 insertion(+), 51 deletions(-)
 delete mode 100644 src/soc/intel/meteorlake/espi.c

diff --git a/src/soc/intel/meteorlake/Kconfig b/src/soc/intel/meteorlake/Kconfig
index 8601557650..6ec4c9aaa7 100644
--- a/src/soc/intel/meteorlake/Kconfig
+++ b/src/soc/intel/meteorlake/Kconfig
@@ -87,6 +87,7 @@ config SOC_INTEL_METEORLAKE
 	select SOC_INTEL_COMMON_BLOCK_XHCI
 	select SOC_INTEL_COMMON_BLOCK_XHCI_ELOG
 	select SOC_INTEL_COMMON_FEATURE
+	select SOC_INTEL_COMMON_FEATURE_ESPI
 	select SOC_INTEL_COMMON_FEATURE_GSPI_DEVFN
 	select SOC_INTEL_COMMON_FEATURE_SOUNDWIRE
 	select SOC_INTEL_COMMON_FEATURE_SPI_DEVFN
diff --git a/src/soc/intel/meteorlake/Makefile.mk b/src/soc/intel/meteorlake/Makefile.mk
index 3b3a2d7703..a6c77a8bdd 100644
--- a/src/soc/intel/meteorlake/Makefile.mk
+++ b/src/soc/intel/meteorlake/Makefile.mk
@@ -13,11 +13,9 @@ bootblock-y += bootblock/bootblock.c
 bootblock-y += bootblock/ioe_die.c
 bootblock-y += bootblock/report_platform.c
 bootblock-y += bootblock/soc_die.c
-bootblock-y += espi.c
 bootblock-y += soc_info.c
 
 romstage-$(CONFIG_SOC_INTEL_CSE_PRE_CPU_RESET_TELEMETRY) += cse_telemetry.c
-romstage-y += espi.c
 romstage-y += meminit.c
 romstage-y += pcie_rp.c
 romstage-y += reset.c
@@ -29,7 +27,6 @@ ramstage-y += cpu.c
 ramstage-$(CONFIG_SOC_INTEL_CRASHLOG) += crashlog.c
 ramstage-y += ioe_pmc.c
 ramstage-y += elog.c
-ramstage-y += espi.c
 ramstage-y += finalize.c
 ramstage-y += fsp_params.c
 ramstage-y += graphics.c
diff --git a/src/soc/intel/meteorlake/espi.c b/src/soc/intel/meteorlake/espi.c
deleted file mode 100644
index 98fd9fc045..0000000000
--- a/src/soc/intel/meteorlake/espi.c
+++ /dev/null
@@ -1,48 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <device/pci.h>
-#include <pc80/isa-dma.h>
-#include <pc80/i8259.h>
-#include <arch/ioapic.h>
-#include <intelblocks/itss.h>
-#include <intelblocks/lpc_lib.h>
-#include <intelblocks/pcr.h>
-#include <intelpch/espi.h>
-#include <soc/iomap.h>
-#include <soc/irq.h>
-#include <soc/pci_devs.h>
-#include <soc/pcr_ids.h>
-#include <soc/soc_chip.h>
-#include <static.h>
-
-void soc_get_gen_io_dec_range(uint32_t gen_io_dec[LPC_NUM_GENERIC_IO_RANGES])
-{
-	const config_t *config = config_of_soc();
-
-	gen_io_dec[0] = config->gen1_dec;
-	gen_io_dec[1] = config->gen2_dec;
-	gen_io_dec[2] = config->gen3_dec;
-	gen_io_dec[3] = config->gen4_dec;
-}
-
-void lpc_soc_init(struct device *dev)
-{
-	/* Legacy initialization */
-	isa_dma_init();
-	pch_misc_init();
-
-	/* Enable CLKRUN_EN for power gating ESPI */
-	lpc_enable_pci_clk_cntl();
-
-	/* Set ESPI Serial IRQ mode */
-	if (CONFIG(SERIRQ_CONTINUOUS_MODE))
-		lpc_set_serirq_mode(SERIRQ_CONTINUOUS);
-	else
-		lpc_set_serirq_mode(SERIRQ_QUIET);
-
-	/* Interrupt configuration */
-	pch_enable_ioapic();
-	pch_pirq_init();
-	setup_i8259();
-	i8259_configure_irq_trigger(9, 1);
-}

From 7278030fa61489fa3325e95547302f0f53578faa Mon Sep 17 00:00:00 2001
From: Jeremy Compostella <jeremy.compostella@intel.com>
Date: Thu, 26 Feb 2026 09:38:57 -0800
Subject: [PATCH 3521/3886] soc/intel/pantherlake: Switch to common eSPI/LPC
 initialization

Replace platform-specific espi.c with the common eSPI/LPC
initialization driver.

Changes:
- Remove src/soc/intel/pantherlake/espi.c
- Enable SOC_INTEL_COMMON_FEATURE_ESPI in Kconfig
- Update Makefile.mk to remove espi.c from build

The eSPI/LPC initialization was nearly identical across platforms,
differing only in minor header inclusions and ENV_RAMSTAGE wrapper
usage. The common implementation uses the config_t typedef that
each platform defines, providing clean abstraction without
preprocessor conditionals.

TEST=Build and boot to the OS on a Fatcat device

Change-Id: If5f2de9faa209ff30f986f34b1816ffa6d5fc683
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91219
Reviewed-by: Guvendik, Bora <bora.guvendik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/soc/intel/pantherlake/Kconfig     |  1 +
 src/soc/intel/pantherlake/Makefile.mk |  3 --
 src/soc/intel/pantherlake/espi.c      | 48 ---------------------------
 3 files changed, 1 insertion(+), 51 deletions(-)
 delete mode 100644 src/soc/intel/pantherlake/espi.c

diff --git a/src/soc/intel/pantherlake/Kconfig b/src/soc/intel/pantherlake/Kconfig
index 243b9fa41f..75f5ac463b 100644
--- a/src/soc/intel/pantherlake/Kconfig
+++ b/src/soc/intel/pantherlake/Kconfig
@@ -97,6 +97,7 @@ config SOC_INTEL_PANTHERLAKE_BASE
 	select SOC_INTEL_COMMON_BLOCK_XHCI
 	select SOC_INTEL_COMMON_BLOCK_XHCI_ELOG
 	select SOC_INTEL_COMMON_FEATURE
+	select SOC_INTEL_COMMON_FEATURE_ESPI
 	select SOC_INTEL_COMMON_FEATURE_GSPI_DEVFN
 	select SOC_INTEL_COMMON_FEATURE_SOUNDWIRE
 	select SOC_INTEL_COMMON_FEATURE_SPI_DEVFN
diff --git a/src/soc/intel/pantherlake/Makefile.mk b/src/soc/intel/pantherlake/Makefile.mk
index 361b583839..8fc9cb543c 100644
--- a/src/soc/intel/pantherlake/Makefile.mk
+++ b/src/soc/intel/pantherlake/Makefile.mk
@@ -13,10 +13,8 @@ all-y += gpio.c
 bootblock-y += bootblock/bootblock.c
 bootblock-y += bootblock/pcd.c
 bootblock-y += bootblock/report_platform.c
-bootblock-y += espi.c
 
 romstage-$(CONFIG_SOC_INTEL_CSE_PRE_CPU_RESET_TELEMETRY) += cse_telemetry.c
-romstage-y += espi.c
 romstage-y += meminit.c
 romstage-y += pcie_rp.c
 romstage-y += reset.c
@@ -28,7 +26,6 @@ ramstage-y += chip.c
 ramstage-y += cpu.c
 ramstage-$(CONFIG_SOC_INTEL_CRASHLOG) += crashlog.c
 ramstage-y += elog.c
-ramstage-y += espi.c
 ramstage-y += finalize.c
 ramstage-y += fsp_params.c
 ramstage-y += lockdown.c
diff --git a/src/soc/intel/pantherlake/espi.c b/src/soc/intel/pantherlake/espi.c
deleted file mode 100644
index d5b5cf93c9..0000000000
--- a/src/soc/intel/pantherlake/espi.c
+++ /dev/null
@@ -1,48 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <device/pci.h>
-#include <pc80/isa-dma.h>
-#include <pc80/i8259.h>
-#include <arch/ioapic.h>
-#include <intelblocks/itss.h>
-#include <intelblocks/lpc_lib.h>
-#include <intelblocks/pcr.h>
-#include <intelpch/espi.h>
-#include <soc/iomap.h>
-#include <soc/irq.h>
-#include <soc/pci_devs.h>
-#include <soc/pcr_ids.h>
-#include <soc/soc_chip.h>
-#include <static.h>
-
-void soc_get_gen_io_dec_range(uint32_t gen_io_dec[LPC_NUM_GENERIC_IO_RANGES])
-{
-	const struct soc_intel_pantherlake_config *config = config_of_soc();
-
-	gen_io_dec[0] = config->gen1_dec;
-	gen_io_dec[1] = config->gen2_dec;
-	gen_io_dec[2] = config->gen3_dec;
-	gen_io_dec[3] = config->gen4_dec;
-}
-
-void lpc_soc_init(struct device *dev)
-{
-	/* Legacy initialization */
-	isa_dma_init();
-	pch_misc_init();
-
-	/* Enable CLKRUN_EN for power gating ESPI */
-	lpc_enable_pci_clk_cntl();
-
-	/* Set ESPI Serial IRQ mode */
-	if (CONFIG(SERIRQ_CONTINUOUS_MODE))
-		lpc_set_serirq_mode(SERIRQ_CONTINUOUS);
-	else
-		lpc_set_serirq_mode(SERIRQ_QUIET);
-
-	/* Interrupt configuration */
-	pch_enable_ioapic();
-	pch_pirq_init();
-	setup_i8259();
-	i8259_configure_irq_trigger(9, 1);
-}

From 05006995b62a79962567370502564f935b7819e2 Mon Sep 17 00:00:00 2001
From: Jeremy Compostella <jeremy.compostella@intel.com>
Date: Thu, 26 Feb 2026 09:39:04 -0800
Subject: [PATCH 3522/3886] soc/intel/tigerlake: Switch to common eSPI/LPC
 initialization

Replace platform-specific espi.c with the common eSPI/LPC
initialization driver.

Changes:
- Remove src/soc/intel/tigerlake/espi.c
- Enable SOC_INTEL_COMMON_FEATURE_ESPI in Kconfig
- Update Makefile.mk to remove espi.c from build

The eSPI/LPC initialization was nearly identical across platforms,
differing only in minor header inclusions and ENV_RAMSTAGE wrapper
usage. The common implementation uses the config_t typedef that
each platform defines, providing clean abstraction without
preprocessor conditionals.

Change-Id: I65f8af8f5abccff25ec0dead4f7def7ce16d3081
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91220
Reviewed-by: Guvendik, Bora <bora.guvendik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/soc/intel/tigerlake/Kconfig     |  1 +
 src/soc/intel/tigerlake/Makefile.mk |  3 --
 src/soc/intel/tigerlake/espi.c      | 58 -----------------------------
 3 files changed, 1 insertion(+), 61 deletions(-)
 delete mode 100644 src/soc/intel/tigerlake/espi.c

diff --git a/src/soc/intel/tigerlake/Kconfig b/src/soc/intel/tigerlake/Kconfig
index b136c3354b..a470d7cde5 100644
--- a/src/soc/intel/tigerlake/Kconfig
+++ b/src/soc/intel/tigerlake/Kconfig
@@ -73,6 +73,7 @@ config SOC_INTEL_TIGERLAKE
 	select SOC_INTEL_COMMON_BLOCK_USB4_XHCI
 	select SOC_INTEL_COMMON_BLOCK_XHCI_ELOG
 	select SOC_INTEL_COMMON_FEATURE
+	select SOC_INTEL_COMMON_FEATURE_ESPI
 	select SOC_INTEL_COMMON_FEATURE_GSPI_DEVFN
 	select SOC_INTEL_COMMON_FEATURE_SOUNDWIRE
 	select SOC_INTEL_COMMON_FEATURE_SPI_DEVFN
diff --git a/src/soc/intel/tigerlake/Makefile.mk b/src/soc/intel/tigerlake/Makefile.mk
index 973ad0f015..cf6cdc2ec2 100644
--- a/src/soc/intel/tigerlake/Makefile.mk
+++ b/src/soc/intel/tigerlake/Makefile.mk
@@ -11,10 +11,8 @@ all-y += pmutil.c
 bootblock-y += bootblock/bootblock.c
 bootblock-y += bootblock/pch.c
 bootblock-y += bootblock/report_platform.c
-bootblock-y += espi.c
 bootblock-y += p2sb.c
 
-romstage-y += espi.c
 romstage-y += meminit.c
 romstage-y += pcie_rp.c
 romstage-y += reset.c
@@ -23,7 +21,6 @@ ramstage-y += acpi.c
 ramstage-y += chip.c
 ramstage-y += cpu.c
 ramstage-y += elog.c
-ramstage-y += espi.c
 ramstage-y += finalize.c
 ramstage-y += fsp_params.c
 ramstage-y += graphics.c
diff --git a/src/soc/intel/tigerlake/espi.c b/src/soc/intel/tigerlake/espi.c
deleted file mode 100644
index 3b56e290d1..0000000000
--- a/src/soc/intel/tigerlake/espi.c
+++ /dev/null
@@ -1,58 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-/*
- * This file is created based on Intel Tiger Lake Processor PCH Datasheet
- * Document number: 575857
- * Chapter number: 2
- */
-
-#include <device/device.h>
-#include <device/pci.h>
-#include <pc80/isa-dma.h>
-#include <pc80/i8259.h>
-#include <device/pci_ops.h>
-#include <arch/ioapic.h>
-#include <intelblocks/itss.h>
-#include <intelblocks/lpc_lib.h>
-#include <intelpch/espi.h>
-#include <soc/iomap.h>
-#include <soc/irq.h>
-#include <soc/pci_devs.h>
-#include <soc/pcr_ids.h>
-#include <soc/soc_chip.h>
-#include <static.h>
-
-void soc_get_gen_io_dec_range(uint32_t gen_io_dec[LPC_NUM_GENERIC_IO_RANGES])
-{
-	const config_t *config = config_of_soc();
-
-	gen_io_dec[0] = config->gen1_dec;
-	gen_io_dec[1] = config->gen2_dec;
-	gen_io_dec[2] = config->gen3_dec;
-	gen_io_dec[3] = config->gen4_dec;
-}
-
-#if ENV_RAMSTAGE
-void lpc_soc_init(struct device *dev)
-{
-	/* Legacy initialization */
-	isa_dma_init();
-	pch_misc_init();
-
-	/* Enable CLKRUN_EN for power gating ESPI */
-	lpc_enable_pci_clk_cntl();
-
-	/* Set ESPI Serial IRQ mode */
-	if (CONFIG(SERIRQ_CONTINUOUS_MODE))
-		lpc_set_serirq_mode(SERIRQ_CONTINUOUS);
-	else
-		lpc_set_serirq_mode(SERIRQ_QUIET);
-
-	/* Interrupt configuration */
-	pch_enable_ioapic();
-	pch_pirq_init();
-	setup_i8259();
-	i8259_configure_irq_trigger(9, 1);
-}
-
-#endif

From aeb9db4467a450a3bb1477d50dfe2612a570dab0 Mon Sep 17 00:00:00 2001
From: Jeremy Compostella <jeremy.compostella@intel.com>
Date: Thu, 26 Feb 2026 09:39:11 -0800
Subject: [PATCH 3523/3886] soc/intel/jasperlake: Switch to common eSPI/LPC
 initialization

Replace platform-specific espi.c with the common eSPI/LPC
initialization driver.

Changes:
- Remove src/soc/intel/jasperlake/espi.c
- Enable SOC_INTEL_COMMON_FEATURE_ESPI in Kconfig
- Update Makefile.mk to remove espi.c from build

The eSPI/LPC initialization was nearly identical across platforms,
differing only in minor header inclusions and ENV_RAMSTAGE wrapper
usage. The common implementation uses the config_t typedef that
each platform defines, providing clean abstraction without
preprocessor conditionals.

Change-Id: Ied29a5f2dabdebe0afedd1d69e4a817d6606a82d
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91221
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Guvendik, Bora <bora.guvendik@intel.com>
---
 src/soc/intel/jasperlake/Kconfig     |  1 +
 src/soc/intel/jasperlake/Makefile.mk |  3 --
 src/soc/intel/jasperlake/espi.c      | 52 ----------------------------
 3 files changed, 1 insertion(+), 55 deletions(-)
 delete mode 100644 src/soc/intel/jasperlake/espi.c

diff --git a/src/soc/intel/jasperlake/Kconfig b/src/soc/intel/jasperlake/Kconfig
index df65e73a78..7bcd734887 100644
--- a/src/soc/intel/jasperlake/Kconfig
+++ b/src/soc/intel/jasperlake/Kconfig
@@ -56,6 +56,7 @@ config SOC_INTEL_JASPERLAKE
 	select SOC_INTEL_COMMON_BLOCK_SMM_IO_TRAP
 	select SOC_INTEL_COMMON_BLOCK_XHCI_ELOG
 	select SOC_INTEL_COMMON_FEATURE
+	select SOC_INTEL_COMMON_FEATURE_ESPI
 	select SOC_INTEL_COMMON_FEATURE_GSPI_DEVFN
 	select SOC_INTEL_COMMON_FEATURE_SPI_DEVFN
 	select SOC_INTEL_COMMON_FEATURE_I2C_DEVFN
diff --git a/src/soc/intel/jasperlake/Makefile.mk b/src/soc/intel/jasperlake/Makefile.mk
index cb3ebfacd2..05288ee8a1 100644
--- a/src/soc/intel/jasperlake/Makefile.mk
+++ b/src/soc/intel/jasperlake/Makefile.mk
@@ -11,11 +11,9 @@ all-y += pmutil.c
 bootblock-y += bootblock/bootblock.c
 bootblock-y += bootblock/pch.c
 bootblock-y += bootblock/report_platform.c
-bootblock-y += espi.c
 bootblock-y += gpio.c
 bootblock-y += p2sb.c
 
-romstage-y += espi.c
 romstage-y += gpio.c
 romstage-y += meminit.c
 romstage-y += pcie_rp.c
@@ -25,7 +23,6 @@ ramstage-y += acpi.c
 ramstage-y += chip.c
 ramstage-y += cpu.c
 ramstage-y += elog.c
-ramstage-y += espi.c
 ramstage-y += finalize.c
 ramstage-y += fsp_params.c
 ramstage-y += gpio.c
diff --git a/src/soc/intel/jasperlake/espi.c b/src/soc/intel/jasperlake/espi.c
deleted file mode 100644
index dfa3b19f9a..0000000000
--- a/src/soc/intel/jasperlake/espi.c
+++ /dev/null
@@ -1,52 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <device/device.h>
-#include <device/pci.h>
-#include <pc80/isa-dma.h>
-#include <pc80/i8259.h>
-#include <device/pci_ops.h>
-#include <arch/ioapic.h>
-#include <intelblocks/itss.h>
-#include <intelblocks/lpc_lib.h>
-#include <intelpch/espi.h>
-#include <soc/iomap.h>
-#include <soc/irq.h>
-#include <soc/pci_devs.h>
-#include <soc/pcr_ids.h>
-#include <soc/soc_chip.h>
-#include <static.h>
-
-void soc_get_gen_io_dec_range(uint32_t gen_io_dec[LPC_NUM_GENERIC_IO_RANGES])
-{
-	const config_t *config = config_of_soc();
-
-	gen_io_dec[0] = config->gen1_dec;
-	gen_io_dec[1] = config->gen2_dec;
-	gen_io_dec[2] = config->gen3_dec;
-	gen_io_dec[3] = config->gen4_dec;
-}
-
-#if ENV_RAMSTAGE
-void lpc_soc_init(struct device *dev)
-{
-	/* Legacy initialization */
-	isa_dma_init();
-	pch_misc_init();
-
-	/* Enable CLKRUN_EN for power gating ESPI */
-	lpc_enable_pci_clk_cntl();
-
-	/* Set ESPI Serial IRQ mode */
-	if (CONFIG(SERIRQ_CONTINUOUS_MODE))
-		lpc_set_serirq_mode(SERIRQ_CONTINUOUS);
-	else
-		lpc_set_serirq_mode(SERIRQ_QUIET);
-
-	/* Interrupt configuration */
-	pch_enable_ioapic();
-	pch_pirq_init();
-	setup_i8259();
-	i8259_configure_irq_trigger(9, 1);
-}
-
-#endif

From 189f8d1a8634ac947c6fe30f2748d69d8e68edd3 Mon Sep 17 00:00:00 2001
From: Jeremy Compostella <jeremy.compostella@intel.com>
Date: Thu, 26 Feb 2026 09:39:19 -0800
Subject: [PATCH 3524/3886] soc/intel/elkhartlake: Switch to common eSPI/LPC
 initialization

Replace platform-specific espi.c with the common eSPI/LPC
initialization driver.

Changes:
- Remove src/soc/intel/elkhartlake/espi.c
- Enable SOC_INTEL_COMMON_FEATURE_ESPI in Kconfig
- Update Makefile.mk to remove espi.c from build

The eSPI/LPC initialization was nearly identical across platforms,
differing only in minor header inclusions and ENV_RAMSTAGE wrapper
usage. The common implementation uses the config_t typedef that
each platform defines, providing clean abstraction without
preprocessor conditionals.

Change-Id: I59d9cb1b37bca2c682e2bf87fc3f5b24c34fb920
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91222
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Guvendik, Bora <bora.guvendik@intel.com>
---
 src/soc/intel/elkhartlake/Kconfig     |  1 +
 src/soc/intel/elkhartlake/Makefile.mk |  3 --
 src/soc/intel/elkhartlake/espi.c      | 52 ---------------------------
 3 files changed, 1 insertion(+), 55 deletions(-)
 delete mode 100644 src/soc/intel/elkhartlake/espi.c

diff --git a/src/soc/intel/elkhartlake/Kconfig b/src/soc/intel/elkhartlake/Kconfig
index a15833346e..e8629039a2 100644
--- a/src/soc/intel/elkhartlake/Kconfig
+++ b/src/soc/intel/elkhartlake/Kconfig
@@ -56,6 +56,7 @@ config SOC_INTEL_ELKHARTLAKE
 	select SOC_INTEL_COMMON_BLOCK_SMM
 	select SOC_INTEL_COMMON_BLOCK_SMM_IO_TRAP
 	select SOC_INTEL_COMMON_FEATURE
+	select SOC_INTEL_COMMON_FEATURE_ESPI
 	select SOC_INTEL_COMMON_FEATURE_GSPI_DEVFN
 	select SOC_INTEL_COMMON_FEATURE_I2C_DEVFN
 	select SOC_INTEL_COMMON_FEATURE_UART_DEVICES
diff --git a/src/soc/intel/elkhartlake/Makefile.mk b/src/soc/intel/elkhartlake/Makefile.mk
index ee2204300c..e46946f0bb 100644
--- a/src/soc/intel/elkhartlake/Makefile.mk
+++ b/src/soc/intel/elkhartlake/Makefile.mk
@@ -12,11 +12,9 @@ all-y += spi.c
 bootblock-y += bootblock/bootblock.c
 bootblock-y += bootblock/pch.c
 bootblock-y += bootblock/report_platform.c
-bootblock-y += espi.c
 bootblock-y += gpio.c
 bootblock-y += p2sb.c
 
-romstage-y += espi.c
 romstage-y += gpio.c
 romstage-y += meminit.c
 romstage-y += pcie_rp.c
@@ -25,7 +23,6 @@ romstage-y += reset.c
 ramstage-y += acpi.c
 ramstage-y += chip.c
 ramstage-y += cpu.c
-ramstage-y += espi.c
 ramstage-y += finalize.c
 ramstage-y += fsp_params.c
 ramstage-y += gpio.c
diff --git a/src/soc/intel/elkhartlake/espi.c b/src/soc/intel/elkhartlake/espi.c
deleted file mode 100644
index de2a84f8f0..0000000000
--- a/src/soc/intel/elkhartlake/espi.c
+++ /dev/null
@@ -1,52 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <arch/ioapic.h>
-#include <device/device.h>
-#include <device/pci.h>
-#include <device/pci_ops.h>
-#include <intelblocks/itss.h>
-#include <intelblocks/lpc_lib.h>
-#include <intelpch/espi.h>
-#include <pc80/isa-dma.h>
-#include <pc80/i8259.h>
-#include <soc/iomap.h>
-#include <soc/irq.h>
-#include <soc/pci_devs.h>
-#include <soc/pcr_ids.h>
-#include <soc/soc_chip.h>
-#include <static.h>
-
-void soc_get_gen_io_dec_range(uint32_t gen_io_dec[LPC_NUM_GENERIC_IO_RANGES])
-{
-	const config_t *config = config_of_soc();
-
-	gen_io_dec[0] = config->gen1_dec;
-	gen_io_dec[1] = config->gen2_dec;
-	gen_io_dec[2] = config->gen3_dec;
-	gen_io_dec[3] = config->gen4_dec;
-}
-
-#if ENV_RAMSTAGE
-void lpc_soc_init(struct device *dev)
-{
-	/* Legacy initialization */
-	isa_dma_init();
-	pch_misc_init();
-
-	/* Enable CLKRUN_EN for power gating ESPI */
-	lpc_enable_pci_clk_cntl();
-
-	/* Set ESPI Serial IRQ mode */
-	if (CONFIG(SERIRQ_CONTINUOUS_MODE))
-		lpc_set_serirq_mode(SERIRQ_CONTINUOUS);
-	else
-		lpc_set_serirq_mode(SERIRQ_QUIET);
-
-	/* Interrupt configuration */
-	pch_enable_ioapic();
-	pch_pirq_init();
-	setup_i8259();
-	i8259_configure_irq_trigger(9, 1);
-}
-
-#endif

From cc31cc0ab26fd772be536ee4fb707be4c174c8eb Mon Sep 17 00:00:00 2001
From: Jeremy Compostella <jeremy.compostella@intel.com>
Date: Thu, 26 Feb 2026 10:00:38 -0800
Subject: [PATCH 3525/3886] soc/intel/common/feature/pmutil: Add common pmutil
 driver

This adds a common PM utility driver for modern Intel platforms that
share consistent PM register layouts.

The driver consolidates power management utility functions that were
previously duplicated across multiple Intel SoC platforms. This
includes functions for:
- SMI/TCO/GPE status bit decoding
- PMC MMIO base address access
- RTC failure detection
- Sleep state management
- Power state structure population
- After-G3 power state configuration
- GPE configuration retrieval using generic config_t

The GPE configuration function (soc_get_gpi_gpe_configs) uses the
generic config_t typedef that each platform defines, allowing complete
code reuse without platform-specific shims.

This common driver is controlled by the Kconfig option
SOC_INTEL_COMMON_FEATURE_PMUTIL and is built for all boot stages.

Change-Id: I45b829b7c18ee66474457df5523069f930806b35
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91237
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Huang, Cliff <cliff.huang@intel.com>
---
 src/soc/intel/common/feature/pmutil/Kconfig   |  10 +
 .../intel/common/feature/pmutil/Makefile.mk   |   4 +
 src/soc/intel/common/feature/pmutil/pmutil.c  | 287 ++++++++++++++++++
 3 files changed, 301 insertions(+)
 create mode 100644 src/soc/intel/common/feature/pmutil/Kconfig
 create mode 100644 src/soc/intel/common/feature/pmutil/Makefile.mk
 create mode 100644 src/soc/intel/common/feature/pmutil/pmutil.c

diff --git a/src/soc/intel/common/feature/pmutil/Kconfig b/src/soc/intel/common/feature/pmutil/Kconfig
new file mode 100644
index 0000000000..e0934a5e4e
--- /dev/null
+++ b/src/soc/intel/common/feature/pmutil/Kconfig
@@ -0,0 +1,10 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
+config SOC_INTEL_COMMON_FEATURE_PMUTIL
+	bool
+	help
+	  Select this if the platform supports common PMC utility driver
+	  for modern Intel platforms that share consistent PM register
+	  layouts. This consolidates power management utility functions
+	  including SMI/TCO/GPE status handling, PMC MMIO access, RTC
+	  failure detection, sleep state management, and GPE configuration.
diff --git a/src/soc/intel/common/feature/pmutil/Makefile.mk b/src/soc/intel/common/feature/pmutil/Makefile.mk
new file mode 100644
index 0000000000..3bda095d2a
--- /dev/null
+++ b/src/soc/intel/common/feature/pmutil/Makefile.mk
@@ -0,0 +1,4 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
+all-$(CONFIG_SOC_INTEL_COMMON_FEATURE_PMUTIL) += pmutil.c
+smm-$(CONFIG_SOC_INTEL_COMMON_FEATURE_PMUTIL) += pmutil.c
diff --git a/src/soc/intel/common/feature/pmutil/pmutil.c b/src/soc/intel/common/feature/pmutil/pmutil.c
new file mode 100644
index 0000000000..5d7db19f74
--- /dev/null
+++ b/src/soc/intel/common/feature/pmutil/pmutil.c
@@ -0,0 +1,287 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+/*
+ * Common helper functions for dealing with power management registers
+ * for modern Intel platforms.
+ *
+ * This driver consolidates PM utility functions that were duplicated
+ * across multiple Intel SoC platforms.
+ */
+
+#define __SIMPLE_DEVICE__
+
+#include <acpi/acpi_pm.h>
+#include <console/console.h>
+#include <device/mmio.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <intelblocks/pmclib.h>
+#include <intelblocks/rtc.h>
+#include <intelblocks/tco.h>
+#include <intelpch/espi.h>
+#include <security/vboot/vbnv.h>
+#include <soc/gpe.h>
+#include <soc/iomap.h>
+#include <soc/pci_devs.h>
+#include <soc/pm.h>
+#include <soc/smbus.h>
+#include <soc/soc_chip.h>
+#include <static.h>
+#include <types.h>
+
+/*
+ * SMI
+ */
+const char *const *soc_smi_sts_array(size_t *a)
+{
+	static const char *const smi_sts_bits[] = {
+		[BIOS_STS_BIT] = "BIOS",
+		[LEGACY_USB_STS_BIT] = "LEGACY_USB",
+		[SMI_ON_SLP_EN_STS_BIT] = "SLP_SMI",
+		[APM_STS_BIT] = "APM",
+		[SWSMI_TMR_STS_BIT] = "SWSMI_TMR",
+		[PM1_STS_BIT] = "PM1",
+		[GPE0_STS_BIT] = "GPE0",
+		[GPIO_STS_BIT] = "GPI",
+		[MCSMI_STS_BIT] = "MCSMI",
+		[DEVMON_STS_BIT] = "DEVMON",
+		[TCO_STS_BIT] = "TCO",
+		[PERIODIC_STS_BIT] = "PERIODIC",
+		[SERIRQ_SMI_STS_BIT] = "SERIRQ_SMI",
+		[SMBUS_SMI_STS_BIT] = "SMBUS_SMI",
+		[PCI_EXP_SMI_STS_BIT] = "PCI_EXP_SMI",
+		[MONITOR_STS_BIT] = "MONITOR",
+		[SPI_SMI_STS_BIT] = "SPI",
+		[GPIO_UNLOCK_SMI_STS_BIT] = "GPIO_UNLOCK",
+		[ESPI_SMI_STS_BIT] = "ESPI_SMI",
+	};
+
+	*a = ARRAY_SIZE(smi_sts_bits);
+	return smi_sts_bits;
+}
+
+/*
+ * TCO
+ */
+const char *const *soc_tco_sts_array(size_t *a)
+{
+	static const char *const tco_sts_bits[] = {
+		[0] = "NMI2SMI",
+		[1] = "SW_TCO",
+		[2] = "TCO_INT",
+		[3] = "TIMEOUT",
+		[7] = "NEWCENTURY",
+		[8] = "BIOSWR",
+		[9] = "DMISCI",
+		[10] = "DMISMI",
+		[12] = "DMISERR",
+		[13] = "SLVSEL",
+		[16] = "INTRD_DET",
+		[17] = "SECOND_TO",
+		[18] = "BOOT",
+		[20] = "SMLINK_SLV"
+	};
+
+	*a = ARRAY_SIZE(tco_sts_bits);
+	return tco_sts_bits;
+}
+
+/*
+ * GPE0
+ */
+const char *const *soc_std_gpe_sts_array(size_t *a)
+{
+	static const char *const gpe_sts_bits[] = {
+		[1] = "HOTPLUG",
+		[2] = "SWGPE",
+		[6] = "TCO_SCI",
+		[7] = "SMB_WAK",
+		[9] = "PCI_EXP",
+		[10] = "BATLOW",
+		[11] = "PME",
+		[12] = "ME",
+		[13] = "PME_B0",
+		[14] = "eSPI",
+		[15] = "GPIO Tier-2",
+		[16] = "LAN_WAKE",
+		[18] = "WADT"
+	};
+
+	*a = ARRAY_SIZE(gpe_sts_bits);
+	return gpe_sts_bits;
+}
+
+void pmc_set_disb(void)
+{
+	/* Set the DISB after DRAM init */
+	uint8_t disb_val;
+	/* Only care about bits [23:16] of register GEN_PMCON_A */
+	uint8_t *addr = (uint8_t *)(pmc_mmio_regs() + GEN_PMCON_A + 2);
+
+	disb_val = read8(addr);
+	disb_val |= (DISB >> 16);
+
+	/* Don't clear bits that are write-1-to-clear */
+	disb_val &= ~((MS4V | SUS_PWR_FLR) >> 16);
+	write8(addr, disb_val);
+}
+
+/*
+ * PMC controller gets hidden from PCI bus
+ * during FSP-Silicon init call. Hence PWRMBASE
+ * can't be accessible using PCI configuration space
+ * read/write.
+ */
+uint8_t *pmc_mmio_regs(void)
+{
+	return (void *)(uintptr_t)PCH_PWRM_BASE_ADDRESS;
+}
+
+uintptr_t soc_read_pmc_base(void)
+{
+	return (uintptr_t)pmc_mmio_regs();
+}
+
+uint32_t *soc_pmc_etr_addr(void)
+{
+	return (uint32_t *)(soc_read_pmc_base() + ETR);
+}
+
+static void pmc_gpe0_different_values(const config_t *config)
+{
+	bool all_zero = (config->pmc_gpe0_dw0 == 0) &&
+			 (config->pmc_gpe0_dw1 == 0) &&
+			 (config->pmc_gpe0_dw2 == 0);
+
+	/* Check if all values are different AND not all zero */
+	bool all_different = (config->pmc_gpe0_dw0 != config->pmc_gpe0_dw1) &&
+			 (config->pmc_gpe0_dw0 != config->pmc_gpe0_dw2) &&
+			 (config->pmc_gpe0_dw1 != config->pmc_gpe0_dw2);
+
+	assert(all_different || all_zero);
+}
+
+void soc_get_gpi_gpe_configs(uint8_t *dw0, uint8_t *dw1, uint8_t *dw2)
+{
+	DEVTREE_CONST config_t *config;
+
+	config = config_of_soc();
+	if (config == NULL) {
+		printk(BIOS_ERR, "Configuration could not be retrieved.\n");
+		return;
+	}
+
+	pmc_gpe0_different_values(config);
+
+	/* Assign to out variable */
+	*dw0 = config->pmc_gpe0_dw0;
+	*dw1 = config->pmc_gpe0_dw1;
+	*dw2 = config->pmc_gpe0_dw2;
+}
+
+static int rtc_failed(uint32_t gen_pmcon_b)
+{
+	return !!(gen_pmcon_b & RTC_BATTERY_DEAD);
+}
+
+int soc_get_rtc_failed(void)
+{
+	const struct chipset_power_state *ps;
+
+	if (acpi_fetch_pm_state(&ps, PS_CLAIMER_RTC) < 0)
+		return 1;
+
+	return rtc_failed(ps->gen_pmcon_b);
+}
+
+int vbnv_cmos_failed(void)
+{
+	return rtc_failed(read32(pmc_mmio_regs() + GEN_PMCON_B));
+}
+
+static inline int deep_s3_enabled(void)
+{
+	uint32_t deep_s3_pol;
+
+	deep_s3_pol = read32(pmc_mmio_regs() + S3_PWRGATE_POL);
+	return !!(deep_s3_pol & (S3DC_GATE_SUS | S3AC_GATE_SUS));
+}
+
+/* Return 0, 3, or 5 to indicate the previous sleep state. */
+int soc_prev_sleep_state(const struct chipset_power_state *ps, int prev_sleep_state)
+{
+	/*
+	 * Check for any power failure to determine if this a wake from
+	 * S5 because the PCH does not set the WAK_STS bit when waking
+	 * from a true G3 state.
+	 */
+	if (!(ps->pm1_sts & WAK_STS) && (ps->gen_pmcon_a & (PWR_FLR | SUS_PWR_FLR)))
+		prev_sleep_state = ACPI_S5;
+
+	/*
+	 * If waking from S3 determine if deep S3 is enabled. If not,
+	 * need to check both deep sleep well and normal suspend well.
+	 * Otherwise just check deep sleep well.
+	 */
+	if (prev_sleep_state == ACPI_S3) {
+		/* PWR_FLR represents deep sleep power well loss. */
+		uint32_t mask = PWR_FLR;
+
+		/* If deep s3 isn't enabled check the suspend well too. */
+		if (!deep_s3_enabled())
+			mask |= SUS_PWR_FLR;
+
+		if (ps->gen_pmcon_a & mask)
+			prev_sleep_state = ACPI_S5;
+	}
+
+	return prev_sleep_state;
+}
+
+void soc_fill_power_state(struct chipset_power_state *ps)
+{
+	uint8_t *pmc;
+
+	ps->tco1_sts = tco_read_reg(TCO1_STS);
+	ps->tco2_sts = tco_read_reg(TCO2_STS);
+
+	printk(BIOS_DEBUG, "TCO_STS:   %04x %04x\n", ps->tco1_sts, ps->tco2_sts);
+
+	pmc = pmc_mmio_regs();
+	ps->gen_pmcon_a = read32(pmc + GEN_PMCON_A);
+	ps->gen_pmcon_b = read32(pmc + GEN_PMCON_B);
+	ps->gblrst_cause[0] = read32(pmc + GBLRST_CAUSE0);
+	ps->gblrst_cause[1] = read32(pmc + GBLRST_CAUSE1);
+	ps->hpr_cause0 = read32(pmc + HPR_CAUSE0);
+
+	printk(BIOS_DEBUG, "GEN_PMCON: %08x %08x\n",
+		ps->gen_pmcon_a, ps->gen_pmcon_b);
+
+	printk(BIOS_DEBUG, "GBLRST_CAUSE: %08x %08x\n",
+		ps->gblrst_cause[0], ps->gblrst_cause[1]);
+
+	printk(BIOS_DEBUG, "HPR_CAUSE0: %08x\n", ps->hpr_cause0);
+}
+
+/* STM Support */
+uint16_t get_pmbase(void)
+{
+	return (uint16_t)ACPI_BASE_ADDRESS;
+}
+
+/*
+ * Set which power state system will be after reapplying
+ * the power (from G3 State)
+ */
+void pmc_soc_set_afterg3_en(const bool on)
+{
+	uint8_t reg8;
+	uint8_t *const pmcbase = pmc_mmio_regs();
+
+	reg8 = read8(pmcbase + GEN_PMCON_A);
+	if (on)
+		reg8 &= ~SLEEP_AFTER_POWER_FAIL;
+	else
+		reg8 |= SLEEP_AFTER_POWER_FAIL;
+	write8(pmcbase + GEN_PMCON_A, reg8);
+}

From 2b70ce3fbfa58947c2abb35fa25c44ebc6580114 Mon Sep 17 00:00:00 2001
From: Jeremy Compostella <jeremy.compostella@intel.com>
Date: Thu, 26 Feb 2026 10:01:06 -0800
Subject: [PATCH 3526/3886] soc/intel/alderlake: Use common pmutil driver

Migrate Alder Lake to use the common PMC utility driver instead
of maintaining platform-specific pmutil.c code.

This change:
- Enables SOC_INTEL_COMMON_FEATURE_PMUTIL in Kconfig
- Removes platform-specific pmutil.c
- Removes pmutil.c from Makefile.mk

The common driver provides all necessary functionality through
the generic config_t interface, eliminating ~290 lines of
duplicated code.

Change-Id: Ieb62ffac95550a0ae8607a3a9ae76e0f6ff0ac35
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91238
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Huang, Cliff <cliff.huang@intel.com>
---
 src/soc/intel/alderlake/Kconfig     |   1 +
 src/soc/intel/alderlake/Makefile.mk |   2 -
 src/soc/intel/alderlake/pmutil.c    | 290 ----------------------------
 3 files changed, 1 insertion(+), 292 deletions(-)
 delete mode 100644 src/soc/intel/alderlake/pmutil.c

diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig
index 30be64a3e9..1568e5b595 100644
--- a/src/soc/intel/alderlake/Kconfig
+++ b/src/soc/intel/alderlake/Kconfig
@@ -87,6 +87,7 @@ config SOC_INTEL_ALDERLAKE
 	select SOC_INTEL_COMMON_FEATURE
 	select SOC_INTEL_COMMON_FEATURE_ESPI
 	select SOC_INTEL_COMMON_FEATURE_GSPI_DEVFN
+	select SOC_INTEL_COMMON_FEATURE_PMUTIL
 	select SOC_INTEL_COMMON_FEATURE_SOUNDWIRE
 	select SOC_INTEL_COMMON_FEATURE_SPI_DEVFN
 	select SOC_INTEL_COMMON_FEATURE_SPI_DEVFN_PSF
diff --git a/src/soc/intel/alderlake/Makefile.mk b/src/soc/intel/alderlake/Makefile.mk
index 83ae0a8c14..210d84592d 100644
--- a/src/soc/intel/alderlake/Makefile.mk
+++ b/src/soc/intel/alderlake/Makefile.mk
@@ -5,7 +5,6 @@ subdirs-y += ../../../cpu/intel/microcode
 subdirs-y += ../../../cpu/intel/turbo
 
 # all (bootblock, verstage, romstage, postcar, ramstage)
-all-y += pmutil.c
 
 bootblock-y += bootblock/bootblock.c
 bootblock-y += bootblock/pch.c
@@ -40,7 +39,6 @@ ramstage-$(CONFIG_SOC_INTEL_CRASHLOG) += crashlog.c
 
 smm-y += elog.c
 smm-y += p2sb.c
-smm-y += pmutil.c
 smm-y += smihandler.c
 smm-y += xhci.c
 
diff --git a/src/soc/intel/alderlake/pmutil.c b/src/soc/intel/alderlake/pmutil.c
deleted file mode 100644
index c4591007e7..0000000000
--- a/src/soc/intel/alderlake/pmutil.c
+++ /dev/null
@@ -1,290 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-/*
- * Helper functions for dealing with power management registers
- * and the differences between PCH variants.
- */
-
-/*
- * This file is created based on Intel Alder Lake Processor PCH Datasheet
- * Document number: 621483
- * Chapter number: 4
- */
-
-#define __SIMPLE_DEVICE__
-
-#include <acpi/acpi_pm.h>
-#include <console/console.h>
-#include <device/mmio.h>
-#include <device/device.h>
-#include <device/pci.h>
-#include <gpio.h>
-#include <intelblocks/pmclib.h>
-#include <intelblocks/rtc.h>
-#include <intelblocks/tco.h>
-#include <intelpch/espi.h>
-#include <security/vboot/vbnv.h>
-#include <soc/gpe.h>
-#include <soc/iomap.h>
-#include <soc/pci_devs.h>
-#include <soc/pm.h>
-#include <soc/smbus.h>
-#include <soc/soc_chip.h>
-#include <static.h>
-#include <types.h>
-
-/*
- * SMI
- */
-
-const char *const *soc_smi_sts_array(size_t *a)
-{
-	static const char *const smi_sts_bits[] = {
-		[BIOS_STS_BIT] = "BIOS",
-		[LEGACY_USB_STS_BIT] = "LEGACY_USB",
-		[SMI_ON_SLP_EN_STS_BIT] = "SLP_SMI",
-		[APM_STS_BIT] = "APM",
-		[SWSMI_TMR_STS_BIT] = "SWSMI_TMR",
-		[PM1_STS_BIT] = "PM1",
-		[GPE0_STS_BIT] = "GPE0",
-		[GPIO_STS_BIT] = "GPI",
-		[MCSMI_STS_BIT] = "MCSMI",
-		[DEVMON_STS_BIT] = "DEVMON",
-		[TCO_STS_BIT] = "TCO",
-		[PERIODIC_STS_BIT] = "PERIODIC",
-		[SERIRQ_SMI_STS_BIT] = "SERIRQ_SMI",
-		[SMBUS_SMI_STS_BIT] = "SMBUS_SMI",
-		[PCI_EXP_SMI_STS_BIT] = "PCI_EXP_SMI",
-		[MONITOR_STS_BIT] = "MONITOR",
-		[SPI_SMI_STS_BIT] = "SPI",
-		[GPIO_UNLOCK_SMI_STS_BIT] = "GPIO_UNLOCK",
-		[ESPI_SMI_STS_BIT] = "ESPI_SMI",
-	};
-
-	*a = ARRAY_SIZE(smi_sts_bits);
-	return smi_sts_bits;
-}
-
-/*
- * TCO
- */
-
-const char *const *soc_tco_sts_array(size_t *a)
-{
-	static const char *const tco_sts_bits[] = {
-		[0] = "NMI2SMI",
-		[1] = "SW_TCO",
-		[2] = "TCO_INT",
-		[3] = "TIMEOUT",
-		[7] = "NEWCENTURY",
-		[8] = "BIOSWR",
-		[9] = "DMISCI",
-		[10] = "DMISMI",
-		[12] = "DMISERR",
-		[13] = "SLVSEL",
-		[16] = "INTRD_DET",
-		[17] = "SECOND_TO",
-		[18] = "BOOT",
-		[20] = "SMLINK_SLV"
-	};
-
-	*a = ARRAY_SIZE(tco_sts_bits);
-	return tco_sts_bits;
-}
-
-/*
- * GPE0
- */
-
-const char *const *soc_std_gpe_sts_array(size_t *a)
-{
-	static const char *const gpe_sts_bits[] = {
-		[1] = "HOTPLUG",
-		[2] = "SWGPE",
-		[6] = "TCO_SCI",
-		[7] = "SMB_WAK",
-		[9] = "PCI_EXP",
-		[10] = "BATLOW",
-		[11] = "PME",
-		[12] = "ME",
-		[13] = "PME_B0",
-		[14] = "eSPI",
-		[15] = "GPIO Tier-2",
-		[16] = "LAN_WAKE",
-		[18] = "WADT"
-	};
-
-	*a = ARRAY_SIZE(gpe_sts_bits);
-	return gpe_sts_bits;
-}
-
-void pmc_set_disb(void)
-{
-	/* Set the DISB after DRAM init */
-	uint8_t disb_val;
-	/* Only care about bits [23:16] of register GEN_PMCON_A */
-	uint8_t *addr = (uint8_t *)(pmc_mmio_regs() + GEN_PMCON_A + 2);
-
-	disb_val = read8(addr);
-	disb_val |= (DISB >> 16);
-
-	/* Don't clear bits that are write-1-to-clear */
-	disb_val &= ~((MS4V | SUS_PWR_FLR) >> 16);
-	write8(addr, disb_val);
-}
-
-/*
- * PMC controller gets hidden from PCI bus
- * during FSP-Silicon init call. Hence PWRMBASE
- * can't be accessible using PCI configuration space
- * read/write.
- */
-uint8_t *pmc_mmio_regs(void)
-{
-	return (void *)(uintptr_t)PCH_PWRM_BASE_ADDRESS;
-}
-
-uintptr_t soc_read_pmc_base(void)
-{
-	return (uintptr_t)pmc_mmio_regs();
-}
-
-uint32_t *soc_pmc_etr_addr(void)
-{
-	return (uint32_t *)(soc_read_pmc_base() + ETR);
-}
-
-static void pmc_gpe0_different_values(const struct soc_intel_alderlake_config *config)
-{
-	bool all_zero = (config->pmc_gpe0_dw0 == 0) &&
-			 (config->pmc_gpe0_dw1 == 0) &&
-			 (config->pmc_gpe0_dw2 == 0);
-
-	/* Check if all values are different AND not all zero */
-	bool all_different = (config->pmc_gpe0_dw0 != config->pmc_gpe0_dw1) &&
-			 (config->pmc_gpe0_dw0 != config->pmc_gpe0_dw2) &&
-			 (config->pmc_gpe0_dw1 != config->pmc_gpe0_dw2);
-
-	assert(all_different || all_zero);
-}
-
-void soc_get_gpi_gpe_configs(uint8_t *dw0, uint8_t *dw1, uint8_t *dw2)
-{
-	DEVTREE_CONST struct soc_intel_alderlake_config *config;
-
-	config = config_of_soc();
-
-	pmc_gpe0_different_values(config);
-
-	/* Assign to out variable */
-	*dw0 = config->pmc_gpe0_dw0;
-	*dw1 = config->pmc_gpe0_dw1;
-	*dw2 = config->pmc_gpe0_dw2;
-}
-
-static int rtc_failed(uint32_t gen_pmcon_b)
-{
-	return !!(gen_pmcon_b & RTC_BATTERY_DEAD);
-}
-
-int soc_get_rtc_failed(void)
-{
-	const struct chipset_power_state *ps;
-
-	if (acpi_fetch_pm_state(&ps, PS_CLAIMER_RTC) < 0)
-		return 1;
-
-	return rtc_failed(ps->gen_pmcon_b);
-}
-
-int vbnv_cmos_failed(void)
-{
-	return rtc_failed(read32(pmc_mmio_regs() + GEN_PMCON_B));
-}
-
-static inline int deep_s3_enabled(void)
-{
-	uint32_t deep_s3_pol;
-
-	deep_s3_pol = read32(pmc_mmio_regs() + S3_PWRGATE_POL);
-	return !!(deep_s3_pol & (S3DC_GATE_SUS | S3AC_GATE_SUS));
-}
-
-/* Return 0, 3, or 5 to indicate the previous sleep state. */
-int soc_prev_sleep_state(const struct chipset_power_state *ps, int prev_sleep_state)
-{
-	/*
-	 * Check for any power failure to determine if this a wake from
-	 * S5 because the PCH does not set the WAK_STS bit when waking
-	 * from a true G3 state.
-	 */
-	if (!(ps->pm1_sts & WAK_STS) && (ps->gen_pmcon_a & (PWR_FLR | SUS_PWR_FLR)))
-		prev_sleep_state = ACPI_S5;
-
-	/*
-	 * If waking from S3 determine if deep S3 is enabled. If not,
-	 * need to check both deep sleep well and normal suspend well.
-	 * Otherwise just check deep sleep well.
-	 */
-	if (prev_sleep_state == ACPI_S3) {
-		/* PWR_FLR represents deep sleep power well loss. */
-		uint32_t mask = PWR_FLR;
-
-		/* If deep s3 isn't enabled check the suspend well too. */
-		if (!deep_s3_enabled())
-			mask |= SUS_PWR_FLR;
-
-		if (ps->gen_pmcon_a & mask)
-			prev_sleep_state = ACPI_S5;
-	}
-
-	return prev_sleep_state;
-}
-
-void soc_fill_power_state(struct chipset_power_state *ps)
-{
-	uint8_t *pmc;
-
-	ps->tco1_sts = tco_read_reg(TCO1_STS);
-	ps->tco2_sts = tco_read_reg(TCO2_STS);
-
-	printk(BIOS_DEBUG, "TCO_STS:   %04x %04x\n", ps->tco1_sts, ps->tco2_sts);
-
-	pmc = pmc_mmio_regs();
-	ps->gen_pmcon_a = read32(pmc + GEN_PMCON_A);
-	ps->gen_pmcon_b = read32(pmc + GEN_PMCON_B);
-	ps->gblrst_cause[0] = read32(pmc + GBLRST_CAUSE0);
-	ps->gblrst_cause[1] = read32(pmc + GBLRST_CAUSE1);
-	ps->hpr_cause0 = read32(pmc + HPR_CAUSE0);
-
-	printk(BIOS_DEBUG, "GEN_PMCON: %08x %08x\n",
-		ps->gen_pmcon_a, ps->gen_pmcon_b);
-
-	printk(BIOS_DEBUG, "GBLRST_CAUSE: %08x %08x\n",
-		ps->gblrst_cause[0], ps->gblrst_cause[1]);
-
-	printk(BIOS_DEBUG, "HPR_CAUSE0: %08x\n", ps->hpr_cause0);
-}
-
-/* STM Support */
-uint16_t get_pmbase(void)
-{
-	return (uint16_t)ACPI_BASE_ADDRESS;
-}
-
-/*
- * Set which power state system will be after reapplying
- * the power (from G3 State)
- */
-void pmc_soc_set_afterg3_en(const bool on)
-{
-	uint8_t reg8;
-	uint8_t *const pmcbase = pmc_mmio_regs();
-
-	reg8 = read8(pmcbase + GEN_PMCON_A);
-	if (on)
-		reg8 &= ~SLEEP_AFTER_POWER_FAIL;
-	else
-		reg8 |= SLEEP_AFTER_POWER_FAIL;
-	write8(pmcbase + GEN_PMCON_A, reg8);
-}

From f0be882d9f0238e24a1c56b27d78c9560b2986d9 Mon Sep 17 00:00:00 2001
From: Jeremy Compostella <jeremy.compostella@intel.com>
Date: Thu, 26 Feb 2026 10:01:21 -0800
Subject: [PATCH 3527/3886] soc/intel/pantherlake: Use common pmutil driver

Migrate Panther Lake to use the common PMC utility driver instead
of maintaining platform-specific pmutil.c code.

This change:
- Enables SOC_INTEL_COMMON_FEATURE_PMUTIL in Kconfig
- Removes platform-specific pmutil.c
- Removes pmutil.c from Makefile.mk

The common driver provides all necessary functionality through
the generic config_t interface, eliminating ~290 lines of
duplicated code.

TEST=Build and boot to the OS on a Fatcat device

Change-Id: I3ee9630a6b15d7b02776ff633a3cff0766a8915b
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91239
Reviewed-by: Huang, Cliff <cliff.huang@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/soc/intel/pantherlake/Kconfig     |   1 +
 src/soc/intel/pantherlake/Makefile.mk |   2 -
 src/soc/intel/pantherlake/pmutil.c    | 285 --------------------------
 3 files changed, 1 insertion(+), 287 deletions(-)
 delete mode 100644 src/soc/intel/pantherlake/pmutil.c

diff --git a/src/soc/intel/pantherlake/Kconfig b/src/soc/intel/pantherlake/Kconfig
index 75f5ac463b..937fb36a6b 100644
--- a/src/soc/intel/pantherlake/Kconfig
+++ b/src/soc/intel/pantherlake/Kconfig
@@ -99,6 +99,7 @@ config SOC_INTEL_PANTHERLAKE_BASE
 	select SOC_INTEL_COMMON_FEATURE
 	select SOC_INTEL_COMMON_FEATURE_ESPI
 	select SOC_INTEL_COMMON_FEATURE_GSPI_DEVFN
+	select SOC_INTEL_COMMON_FEATURE_PMUTIL
 	select SOC_INTEL_COMMON_FEATURE_SOUNDWIRE
 	select SOC_INTEL_COMMON_FEATURE_SPI_DEVFN
 	select SOC_INTEL_COMMON_FEATURE_SPI_DEVFN_PSF
diff --git a/src/soc/intel/pantherlake/Makefile.mk b/src/soc/intel/pantherlake/Makefile.mk
index 8fc9cb543c..417d27d6d0 100644
--- a/src/soc/intel/pantherlake/Makefile.mk
+++ b/src/soc/intel/pantherlake/Makefile.mk
@@ -7,7 +7,6 @@ subdirs-y += ../../../cpu/intel/microcode
 subdirs-y += ../../../cpu/intel/turbo
 
 # all (bootblock, verstage, romstage, postcar, ramstage)
-all-y += pmutil.c
 all-y += gpio.c
 
 bootblock-y += bootblock/bootblock.c
@@ -43,7 +42,6 @@ ramstage-$(CONFIG_DRIVERS_INTEL_TOUCH) += touch.c
 smm-y += elog.c
 smm-y += gpio.c
 smm-y += p2sb.c
-smm-y += pmutil.c
 smm-y += smihandler.c
 smm-y += xhci.c
 CPPFLAGS_common += -I$(src)/soc/intel/pantherlake
diff --git a/src/soc/intel/pantherlake/pmutil.c b/src/soc/intel/pantherlake/pmutil.c
deleted file mode 100644
index 7ce1dacfa3..0000000000
--- a/src/soc/intel/pantherlake/pmutil.c
+++ /dev/null
@@ -1,285 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-/*
- * Helper functions for dealing with power management registers
- * and the differences between PCH variants.
- */
-
-#define __SIMPLE_DEVICE__
-
-#include <acpi/acpi_pm.h>
-#include <console/console.h>
-#include <device/mmio.h>
-#include <device/device.h>
-#include <device/pci.h>
-#include <intelblocks/pmclib.h>
-#include <intelblocks/rtc.h>
-#include <intelblocks/tco.h>
-#include <intelpch/espi.h>
-#include <security/vboot/vbnv.h>
-#include <soc/gpe.h>
-#include <soc/gpio.h>
-#include <soc/iomap.h>
-#include <soc/pci_devs.h>
-#include <soc/pm.h>
-#include <soc/smbus.h>
-#include <soc/soc_chip.h>
-#include <static.h>
-#include <types.h>
-
-/*
- * SMI
- */
-const char *const *soc_smi_sts_array(size_t *a)
-{
-	static const char *const smi_sts_bits[] = {
-		[BIOS_STS_BIT] = "BIOS",
-		[LEGACY_USB_STS_BIT] = "LEGACY_USB",
-		[SMI_ON_SLP_EN_STS_BIT] = "SLP_SMI",
-		[APM_STS_BIT] = "APM",
-		[SWSMI_TMR_STS_BIT] = "SWSMI_TMR",
-		[PM1_STS_BIT] = "PM1",
-		[GPE0_STS_BIT] = "GPE0",
-		[GPIO_STS_BIT] = "GPI",
-		[MCSMI_STS_BIT] = "MCSMI",
-		[DEVMON_STS_BIT] = "DEVMON",
-		[TCO_STS_BIT] = "TCO",
-		[PERIODIC_STS_BIT] = "PERIODIC",
-		[SERIRQ_SMI_STS_BIT] = "SERIRQ_SMI",
-		[SMBUS_SMI_STS_BIT] = "SMBUS_SMI",
-		[PCI_EXP_SMI_STS_BIT] = "PCI_EXP_SMI",
-		[MONITOR_STS_BIT] = "MONITOR",
-		[SPI_SMI_STS_BIT] = "SPI",
-		[GPIO_UNLOCK_SMI_STS_BIT] = "GPIO_UNLOCK",
-		[ESPI_SMI_STS_BIT] = "ESPI_SMI",
-	};
-
-	*a = ARRAY_SIZE(smi_sts_bits);
-	return smi_sts_bits;
-}
-
-/*
- * TCO
- */
-const char *const *soc_tco_sts_array(size_t *a)
-{
-	static const char *const tco_sts_bits[] = {
-		[0] = "NMI2SMI",
-		[1] = "SW_TCO",
-		[2] = "TCO_INT",
-		[3] = "TIMEOUT",
-		[7] = "NEWCENTURY",
-		[8] = "BIOSWR",
-		[9] = "DMISCI",
-		[10] = "DMISMI",
-		[12] = "DMISERR",
-		[13] = "SLVSEL",
-		[16] = "INTRD_DET",
-		[17] = "SECOND_TO",
-		[18] = "BOOT",
-		[20] = "SMLINK_SLV"
-	};
-
-	*a = ARRAY_SIZE(tco_sts_bits);
-	return tco_sts_bits;
-}
-
-/*
- * GPE0
- */
-const char *const *soc_std_gpe_sts_array(size_t *a)
-{
-	static const char *const gpe_sts_bits[] = {
-		[1] = "HOTPLUG",
-		[2] = "SWGPE",
-		[6] = "TCO_SCI",
-		[7] = "SMB_WAK",
-		[9] = "PCI_EXP",
-		[10] = "BATLOW",
-		[11] = "PME",
-		[12] = "ME",
-		[13] = "PME_B0",
-		[14] = "eSPI",
-		[15] = "GPIO Tier-2",
-		[16] = "LAN_WAKE",
-		[18] = "WADT"
-	};
-
-	*a = ARRAY_SIZE(gpe_sts_bits);
-	return gpe_sts_bits;
-}
-
-void pmc_set_disb(void)
-{
-	/* Set the DISB after DRAM init */
-	uint8_t disb_val;
-	/* Only care about bits [23:16] of register GEN_PMCON_A */
-	uint8_t *addr = (uint8_t *)(pmc_mmio_regs() + GEN_PMCON_A + 2);
-
-	disb_val = read8(addr);
-	disb_val |= (DISB >> 16);
-
-	/* Don't clear bits that are write-1-to-clear */
-	disb_val &= ~((MS4V | SUS_PWR_FLR) >> 16);
-	write8(addr, disb_val);
-}
-
-/*
- * PMC controller gets hidden from PCI bus
- * during FSP-Silicon init call. Hence PWRMBASE
- * can't be accessible using PCI configuration space
- * read/write.
- */
-uint8_t *pmc_mmio_regs(void)
-{
-	return (void *)(uintptr_t)PCH_PWRM_BASE_ADDRESS;
-}
-
-uintptr_t soc_read_pmc_base(void)
-{
-	return (uintptr_t)pmc_mmio_regs();
-}
-
-uint32_t *soc_pmc_etr_addr(void)
-{
-	return (uint32_t *)(soc_read_pmc_base() + ETR);
-}
-
-static void pmc_gpe0_different_values(const struct soc_intel_pantherlake_config *config)
-{
-	bool all_zero = (config->pmc_gpe0_dw0 == 0) &&
-			 (config->pmc_gpe0_dw1 == 0) &&
-			 (config->pmc_gpe0_dw2 == 0);
-
-	/* Check if all values are different AND not all zero */
-	bool all_different = (config->pmc_gpe0_dw0 != config->pmc_gpe0_dw1) &&
-			 (config->pmc_gpe0_dw0 != config->pmc_gpe0_dw2) &&
-			 (config->pmc_gpe0_dw1 != config->pmc_gpe0_dw2);
-
-	assert(all_different || all_zero);
-}
-
-void soc_get_gpi_gpe_configs(uint8_t *dw0, uint8_t *dw1, uint8_t *dw2)
-{
-	DEVTREE_CONST struct soc_intel_pantherlake_config *config;
-
-	config = config_of_soc();
-	if (config == NULL) {
-		printk(BIOS_ERR, "Configuration could not be retrieved.\n");
-		return;
-	}
-
-	pmc_gpe0_different_values(config);
-
-	/* Assign to out variable */
-	*dw0 = config->pmc_gpe0_dw0;
-	*dw1 = config->pmc_gpe0_dw1;
-	*dw2 = config->pmc_gpe0_dw2;
-}
-
-static int rtc_failed(uint32_t gen_pmcon_b)
-{
-	return !!(gen_pmcon_b & RTC_BATTERY_DEAD);
-}
-
-int soc_get_rtc_failed(void)
-{
-	const struct chipset_power_state *ps;
-
-	if (acpi_fetch_pm_state(&ps, PS_CLAIMER_RTC) < 0)
-		return 1;
-
-	return rtc_failed(ps->gen_pmcon_b);
-}
-
-int vbnv_cmos_failed(void)
-{
-	return rtc_failed(read32(pmc_mmio_regs() + GEN_PMCON_B));
-}
-
-static inline int deep_s3_enabled(void)
-{
-	uint32_t deep_s3_pol;
-
-	deep_s3_pol = read32(pmc_mmio_regs() + S3_PWRGATE_POL);
-	return !!(deep_s3_pol & (S3DC_GATE_SUS | S3AC_GATE_SUS));
-}
-
-/* Return 0, 3, or 5 to indicate the previous sleep state. */
-int soc_prev_sleep_state(const struct chipset_power_state *ps, int prev_sleep_state)
-{
-	/*
-	 * Check for any power failure to determine if this a wake from
-	 * S5 because the PCH does not set the WAK_STS bit when waking
-	 * from a true G3 state.
-	 */
-	if (!(ps->pm1_sts & WAK_STS) && (ps->gen_pmcon_a & (PWR_FLR | SUS_PWR_FLR)))
-		prev_sleep_state = ACPI_S5;
-
-	/*
-	 * If waking from S3 determine if deep S3 is enabled. If not,
-	 * need to check both deep sleep well and normal suspend well.
-	 * Otherwise just check deep sleep well.
-	 */
-	if (prev_sleep_state == ACPI_S3) {
-		/* PWR_FLR represents deep sleep power well loss. */
-		uint32_t mask = PWR_FLR;
-
-		/* If deep s3 isn't enabled check the suspend well too. */
-		if (!deep_s3_enabled())
-			mask |= SUS_PWR_FLR;
-
-		if (ps->gen_pmcon_a & mask)
-			prev_sleep_state = ACPI_S5;
-	}
-
-	return prev_sleep_state;
-}
-
-void soc_fill_power_state(struct chipset_power_state *ps)
-{
-	uint8_t *pmc;
-
-	ps->tco1_sts = tco_read_reg(TCO1_STS);
-	ps->tco2_sts = tco_read_reg(TCO2_STS);
-
-	printk(BIOS_DEBUG, "TCO_STS:   %04x %04x\n", ps->tco1_sts, ps->tco2_sts);
-
-	pmc = pmc_mmio_regs();
-	ps->gen_pmcon_a = read32(pmc + GEN_PMCON_A);
-	ps->gen_pmcon_b = read32(pmc + GEN_PMCON_B);
-	ps->gblrst_cause[0] = read32(pmc + GBLRST_CAUSE0);
-	ps->gblrst_cause[1] = read32(pmc + GBLRST_CAUSE1);
-	ps->hpr_cause0 = read32(pmc + HPR_CAUSE0);
-
-	printk(BIOS_DEBUG, "GEN_PMCON: %08x %08x\n",
-		ps->gen_pmcon_a, ps->gen_pmcon_b);
-
-	printk(BIOS_DEBUG, "GBLRST_CAUSE: %08x %08x\n",
-		ps->gblrst_cause[0], ps->gblrst_cause[1]);
-
-	printk(BIOS_DEBUG, "HPR_CAUSE0: %08x\n", ps->hpr_cause0);
-}
-
-/* STM Support */
-uint16_t get_pmbase(void)
-{
-	return (uint16_t)ACPI_BASE_ADDRESS;
-}
-
-/*
- * Set which power state system will be after reapplying
- * the power (from G3 State)
- */
-void pmc_soc_set_afterg3_en(const bool on)
-{
-	uint8_t reg8;
-	uint8_t *const pmcbase = pmc_mmio_regs();
-
-	reg8 = read8(pmcbase + GEN_PMCON_A);
-	if (on)
-		reg8 &= ~SLEEP_AFTER_POWER_FAIL;
-	else
-		reg8 |= SLEEP_AFTER_POWER_FAIL;
-	write8(pmcbase + GEN_PMCON_A, reg8);
-}

From 2eb37453e56f3c0dc2dd7c1f23c26af080cdac7c Mon Sep 17 00:00:00 2001
From: Jeremy Compostella <jeremy.compostella@intel.com>
Date: Thu, 26 Feb 2026 10:01:36 -0800
Subject: [PATCH 3528/3886] soc/intel/meteorlake: Use common pmutil driver

Migrate Meteor Lake to use the common PMC utility driver instead
of maintaining platform-specific pmutil.c code.

This change:
- Enables SOC_INTEL_COMMON_FEATURE_PMUTIL in Kconfig
- Removes platform-specific pmutil.c
- Removes pmutil.c from Makefile.mk

The common driver provides all necessary functionality through
the generic config_t interface, eliminating ~290 lines of
duplicated code.

Change-Id: I1c46a517420c8ea7410c4ed7e8e7b761d4399cf9
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91240
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Huang, Cliff <cliff.huang@intel.com>
---
 src/soc/intel/meteorlake/Kconfig          |   1 +
 src/soc/intel/meteorlake/Makefile.mk      |   2 -
 src/soc/intel/meteorlake/include/soc/pm.h |   3 -
 src/soc/intel/meteorlake/ioe_pmc.c        |   5 +
 src/soc/intel/meteorlake/pmutil.c         | 286 ----------------------
 5 files changed, 6 insertions(+), 291 deletions(-)
 delete mode 100644 src/soc/intel/meteorlake/pmutil.c

diff --git a/src/soc/intel/meteorlake/Kconfig b/src/soc/intel/meteorlake/Kconfig
index 6ec4c9aaa7..1ec20d25de 100644
--- a/src/soc/intel/meteorlake/Kconfig
+++ b/src/soc/intel/meteorlake/Kconfig
@@ -89,6 +89,7 @@ config SOC_INTEL_METEORLAKE
 	select SOC_INTEL_COMMON_FEATURE
 	select SOC_INTEL_COMMON_FEATURE_ESPI
 	select SOC_INTEL_COMMON_FEATURE_GSPI_DEVFN
+	select SOC_INTEL_COMMON_FEATURE_PMUTIL
 	select SOC_INTEL_COMMON_FEATURE_SOUNDWIRE
 	select SOC_INTEL_COMMON_FEATURE_SPI_DEVFN
 	select SOC_INTEL_COMMON_FEATURE_SPI_DEVFN_PSF
diff --git a/src/soc/intel/meteorlake/Makefile.mk b/src/soc/intel/meteorlake/Makefile.mk
index a6c77a8bdd..19ffa96d0e 100644
--- a/src/soc/intel/meteorlake/Makefile.mk
+++ b/src/soc/intel/meteorlake/Makefile.mk
@@ -6,7 +6,6 @@ subdirs-y += ../../../cpu/intel/microcode
 subdirs-y += ../../../cpu/intel/turbo
 
 # all (bootblock, verstage, romstage, postcar, ramstage)
-all-y += pmutil.c
 all-y += gpio.c
 
 bootblock-y += bootblock/bootblock.c
@@ -44,7 +43,6 @@ ramstage-y += soc_info.c
 smm-y += elog.c
 smm-y += gpio.c
 smm-y += p2sb.c
-smm-y += pmutil.c
 smm-y += smihandler.c
 smm-y += soc_info.c
 smm-y += xhci.c
diff --git a/src/soc/intel/meteorlake/include/soc/pm.h b/src/soc/intel/meteorlake/include/soc/pm.h
index 7474cdd8bc..c486232e7d 100644
--- a/src/soc/intel/meteorlake/include/soc/pm.h
+++ b/src/soc/intel/meteorlake/include/soc/pm.h
@@ -150,9 +150,6 @@ struct chipset_power_state {
 /* Get base address PMC memory mapped registers. */
 uint8_t *pmc_mmio_regs(void);
 
-/* Get base address IOE.PMC memory mapped registers. */
-uint8_t *ioe_pmc_mmio_regs(void);
-
 /* Get base address of TCO I/O registers. */
 uint16_t smbus_tco_regs(void);
 
diff --git a/src/soc/intel/meteorlake/ioe_pmc.c b/src/soc/intel/meteorlake/ioe_pmc.c
index 418c4a5535..e2fb49be4d 100644
--- a/src/soc/intel/meteorlake/ioe_pmc.c
+++ b/src/soc/intel/meteorlake/ioe_pmc.c
@@ -5,6 +5,11 @@
 #include <soc/iomap.h>
 #include <soc/pm.h>
 
+static uint8_t *ioe_pmc_mmio_regs(void)
+{
+	return (void *)(uintptr_t)IOE_PWRM_BASE_ADDRESS;
+}
+
 static void ioe_pmc_read_resources(struct device *dev)
 {
 	/* Add the fixed MMIO resource */
diff --git a/src/soc/intel/meteorlake/pmutil.c b/src/soc/intel/meteorlake/pmutil.c
deleted file mode 100644
index a0bba92f11..0000000000
--- a/src/soc/intel/meteorlake/pmutil.c
+++ /dev/null
@@ -1,286 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-/*
- * Helper functions for dealing with power management registers
- * and the differences between PCH variants.
- */
-
-#define __SIMPLE_DEVICE__
-
-#include <acpi/acpi_pm.h>
-#include <console/console.h>
-#include <device/mmio.h>
-#include <device/device.h>
-#include <device/pci.h>
-#include <gpio.h>
-#include <intelblocks/pmclib.h>
-#include <intelblocks/rtc.h>
-#include <intelblocks/tco.h>
-#include <intelpch/espi.h>
-#include <security/vboot/vbnv.h>
-#include <soc/gpe.h>
-#include <soc/iomap.h>
-#include <soc/pci_devs.h>
-#include <soc/pm.h>
-#include <soc/smbus.h>
-#include <soc/soc_chip.h>
-#include <static.h>
-#include <types.h>
-
-/*
- * SMI
- */
-const char *const *soc_smi_sts_array(size_t *a)
-{
-	static const char *const smi_sts_bits[] = {
-		[BIOS_STS_BIT] = "BIOS",
-		[LEGACY_USB_STS_BIT] = "LEGACY_USB",
-		[SMI_ON_SLP_EN_STS_BIT] = "SLP_SMI",
-		[APM_STS_BIT] = "APM",
-		[SWSMI_TMR_STS_BIT] = "SWSMI_TMR",
-		[PM1_STS_BIT] = "PM1",
-		[GPE0_STS_BIT] = "GPE0",
-		[GPIO_STS_BIT] = "GPI",
-		[MCSMI_STS_BIT] = "MCSMI",
-		[DEVMON_STS_BIT] = "DEVMON",
-		[TCO_STS_BIT] = "TCO",
-		[PERIODIC_STS_BIT] = "PERIODIC",
-		[SERIRQ_SMI_STS_BIT] = "SERIRQ_SMI",
-		[SMBUS_SMI_STS_BIT] = "SMBUS_SMI",
-		[PCI_EXP_SMI_STS_BIT] = "PCI_EXP_SMI",
-		[MONITOR_STS_BIT] = "MONITOR",
-		[SPI_SMI_STS_BIT] = "SPI",
-		[GPIO_UNLOCK_SMI_STS_BIT] = "GPIO_UNLOCK",
-		[ESPI_SMI_STS_BIT] = "ESPI_SMI",
-	};
-
-	*a = ARRAY_SIZE(smi_sts_bits);
-	return smi_sts_bits;
-}
-
-/*
- * TCO
- */
-const char *const *soc_tco_sts_array(size_t *a)
-{
-	static const char *const tco_sts_bits[] = {
-		[0] = "NMI2SMI",
-		[1] = "SW_TCO",
-		[2] = "TCO_INT",
-		[3] = "TIMEOUT",
-		[7] = "NEWCENTURY",
-		[8] = "BIOSWR",
-		[9] = "DMISCI",
-		[10] = "DMISMI",
-		[12] = "DMISERR",
-		[13] = "SLVSEL",
-		[16] = "INTRD_DET",
-		[17] = "SECOND_TO",
-		[18] = "BOOT",
-		[20] = "SMLINK_SLV"
-	};
-
-	*a = ARRAY_SIZE(tco_sts_bits);
-	return tco_sts_bits;
-}
-
-/*
- * GPE0
- */
-const char *const *soc_std_gpe_sts_array(size_t *a)
-{
-	static const char *const gpe_sts_bits[] = {
-		[1] = "HOTPLUG",
-		[2] = "SWGPE",
-		[6] = "TCO_SCI",
-		[7] = "SMB_WAK",
-		[9] = "PCI_EXP",
-		[10] = "BATLOW",
-		[11] = "PME",
-		[12] = "ME",
-		[13] = "PME_B0",
-		[14] = "eSPI",
-		[15] = "GPIO Tier-2",
-		[16] = "LAN_WAKE",
-		[18] = "WADT"
-	};
-
-	*a = ARRAY_SIZE(gpe_sts_bits);
-	return gpe_sts_bits;
-}
-
-void pmc_set_disb(void)
-{
-	/* Set the DISB after DRAM init */
-	uint8_t disb_val;
-	/* Only care about bits [23:16] of register GEN_PMCON_A */
-	uint8_t *addr = (uint8_t *)(pmc_mmio_regs() + GEN_PMCON_A + 2);
-
-	disb_val = read8(addr);
-	disb_val |= (DISB >> 16);
-
-	/* Don't clear bits that are write-1-to-clear */
-	disb_val &= ~((MS4V | SUS_PWR_FLR) >> 16);
-	write8(addr, disb_val);
-}
-
-/*
- * PMC controller gets hidden from PCI bus
- * during FSP-Silicon init call. Hence PWRMBASE
- * can't be accessible using PCI configuration space
- * read/write.
- */
-uint8_t *pmc_mmio_regs(void)
-{
-	return (void *)(uintptr_t)PCH_PWRM_BASE_ADDRESS;
-}
-
-uint8_t *ioe_pmc_mmio_regs(void)
-{
-	return (void *)(uintptr_t)IOE_PWRM_BASE_ADDRESS;
-}
-
-uintptr_t soc_read_pmc_base(void)
-{
-	return (uintptr_t)pmc_mmio_regs();
-}
-
-uint32_t *soc_pmc_etr_addr(void)
-{
-	return (uint32_t *)(soc_read_pmc_base() + ETR);
-}
-
-static void pmc_gpe0_different_values(const struct soc_intel_meteorlake_config *config)
-{
-	bool all_zero = (config->pmc_gpe0_dw0 == 0) &&
-			 (config->pmc_gpe0_dw1 == 0) &&
-			 (config->pmc_gpe0_dw2 == 0);
-
-	/* Check if all values are different AND not all zero */
-	bool all_different = (config->pmc_gpe0_dw0 != config->pmc_gpe0_dw1) &&
-			 (config->pmc_gpe0_dw0 != config->pmc_gpe0_dw2) &&
-			 (config->pmc_gpe0_dw1 != config->pmc_gpe0_dw2);
-
-	assert(all_different || all_zero);
-}
-
-void soc_get_gpi_gpe_configs(uint8_t *dw0, uint8_t *dw1, uint8_t *dw2)
-{
-	DEVTREE_CONST struct soc_intel_meteorlake_config *config;
-
-	config = config_of_soc();
-
-	pmc_gpe0_different_values(config);
-
-	/* Assign to out variable */
-	*dw0 = config->pmc_gpe0_dw0;
-	*dw1 = config->pmc_gpe0_dw1;
-	*dw2 = config->pmc_gpe0_dw2;
-}
-
-static int rtc_failed(uint32_t gen_pmcon_b)
-{
-	return !!(gen_pmcon_b & RTC_BATTERY_DEAD);
-}
-
-int soc_get_rtc_failed(void)
-{
-	const struct chipset_power_state *ps;
-
-	if (acpi_fetch_pm_state(&ps, PS_CLAIMER_RTC) < 0)
-		return 1;
-
-	return rtc_failed(ps->gen_pmcon_b);
-}
-
-int vbnv_cmos_failed(void)
-{
-	return rtc_failed(read32(pmc_mmio_regs() + GEN_PMCON_B));
-}
-
-static inline int deep_s3_enabled(void)
-{
-	uint32_t deep_s3_pol;
-
-	deep_s3_pol = read32(pmc_mmio_regs() + S3_PWRGATE_POL);
-	return !!(deep_s3_pol & (S3DC_GATE_SUS | S3AC_GATE_SUS));
-}
-
-/* Return 0, 3, or 5 to indicate the previous sleep state. */
-int soc_prev_sleep_state(const struct chipset_power_state *ps, int prev_sleep_state)
-{
-	/*
-	 * Check for any power failure to determine if this a wake from
-	 * S5 because the PCH does not set the WAK_STS bit when waking
-	 * from a true G3 state.
-	 */
-	if (!(ps->pm1_sts & WAK_STS) && (ps->gen_pmcon_a & (PWR_FLR | SUS_PWR_FLR)))
-		prev_sleep_state = ACPI_S5;
-
-	/*
-	 * If waking from S3 determine if deep S3 is enabled. If not,
-	 * need to check both deep sleep well and normal suspend well.
-	 * Otherwise just check deep sleep well.
-	 */
-	if (prev_sleep_state == ACPI_S3) {
-		/* PWR_FLR represents deep sleep power well loss. */
-		uint32_t mask = PWR_FLR;
-
-		/* If deep s3 isn't enabled check the suspend well too. */
-		if (!deep_s3_enabled())
-			mask |= SUS_PWR_FLR;
-
-		if (ps->gen_pmcon_a & mask)
-			prev_sleep_state = ACPI_S5;
-	}
-
-	return prev_sleep_state;
-}
-
-void soc_fill_power_state(struct chipset_power_state *ps)
-{
-	uint8_t *pmc;
-
-	ps->tco1_sts = tco_read_reg(TCO1_STS);
-	ps->tco2_sts = tco_read_reg(TCO2_STS);
-
-	printk(BIOS_DEBUG, "TCO_STS:   %04x %04x\n", ps->tco1_sts, ps->tco2_sts);
-
-	pmc = pmc_mmio_regs();
-	ps->gen_pmcon_a = read32(pmc + GEN_PMCON_A);
-	ps->gen_pmcon_b = read32(pmc + GEN_PMCON_B);
-	ps->gblrst_cause[0] = read32(pmc + GBLRST_CAUSE0);
-	ps->gblrst_cause[1] = read32(pmc + GBLRST_CAUSE1);
-	ps->hpr_cause0 = read32(pmc + HPR_CAUSE0);
-
-	printk(BIOS_DEBUG, "GEN_PMCON: %08x %08x\n",
-		ps->gen_pmcon_a, ps->gen_pmcon_b);
-
-	printk(BIOS_DEBUG, "GBLRST_CAUSE: %08x %08x\n",
-		ps->gblrst_cause[0], ps->gblrst_cause[1]);
-
-	printk(BIOS_DEBUG, "HPR_CAUSE0: %08x\n", ps->hpr_cause0);
-}
-
-/* STM Support */
-uint16_t get_pmbase(void)
-{
-	return (uint16_t)ACPI_BASE_ADDRESS;
-}
-
-/*
- * Set which power state system will be after reapplying
- * the power (from G3 State)
- */
-void pmc_soc_set_afterg3_en(const bool on)
-{
-	uint8_t reg8;
-	uint8_t *const pmcbase = pmc_mmio_regs();
-
-	reg8 = read8(pmcbase + GEN_PMCON_A);
-	if (on)
-		reg8 &= ~SLEEP_AFTER_POWER_FAIL;
-	else
-		reg8 |= SLEEP_AFTER_POWER_FAIL;
-	write8(pmcbase + GEN_PMCON_A, reg8);
-}

From 4b73479c3821ae14d7811c4b5870042d8b238d00 Mon Sep 17 00:00:00 2001
From: Jeremy Compostella <jeremy.compostella@intel.com>
Date: Thu, 26 Feb 2026 10:21:09 -0800
Subject: [PATCH 3529/3886] soc/intel/common/feature/smihandler: Add common PCH
 client SMI handler

Add a common implementation of SMI handler code for PCH client platforms
to reduce code duplication across Alder Lake, Meteor Lake, Panther Lake,
and Tiger Lake platforms.

This implementation consolidates:
- smihandler_soc_disable_busmaster(): Skip disabling PMC bus master
- southbridge_smi array: Standard SMI handler mappings

The common driver uses a platform-specific macro that must be defined in
each platform's soc/pci_devs.h header:
- SOC_PMC_DEV: PMC PCI device identifier

This change enables consolidation of nearly identical smihandler.c files
across four platforms, reducing duplication by approximately 100+ lines.

Change-Id: I9ecb65b7ea4feafb8acbaf5798bbeaeb80b7c24a
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91293
Reviewed-by: Huang, Cliff <cliff.huang@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 .../intel/common/feature/smihandler/Kconfig   |  9 ++++++
 .../common/feature/smihandler/Makefile.mk     |  3 ++
 .../common/feature/smihandler/smihandler.c    | 29 +++++++++++++++++++
 3 files changed, 41 insertions(+)
 create mode 100644 src/soc/intel/common/feature/smihandler/Kconfig
 create mode 100644 src/soc/intel/common/feature/smihandler/Makefile.mk
 create mode 100644 src/soc/intel/common/feature/smihandler/smihandler.c

diff --git a/src/soc/intel/common/feature/smihandler/Kconfig b/src/soc/intel/common/feature/smihandler/Kconfig
new file mode 100644
index 0000000000..a927e1828e
--- /dev/null
+++ b/src/soc/intel/common/feature/smihandler/Kconfig
@@ -0,0 +1,9 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
+config SOC_INTEL_COMMON_FEATURE_SMIHANDLER
+	bool
+	help
+	  Select this if the platform supports common PCH client SMI handler
+	  implementation. This consolidates SMI handler code for PCH client
+	  platforms including PMC bus master control and standard SMI handler
+	  mappings. The platform must define SOC_PMC_DEV in soc/pci_devs.h.
diff --git a/src/soc/intel/common/feature/smihandler/Makefile.mk b/src/soc/intel/common/feature/smihandler/Makefile.mk
new file mode 100644
index 0000000000..cda860ed0b
--- /dev/null
+++ b/src/soc/intel/common/feature/smihandler/Makefile.mk
@@ -0,0 +1,3 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
+smm-$(CONFIG_SOC_INTEL_COMMON_FEATURE_SMIHANDLER) += smihandler.c
diff --git a/src/soc/intel/common/feature/smihandler/smihandler.c b/src/soc/intel/common/feature/smihandler/smihandler.c
new file mode 100644
index 0000000000..35726049d0
--- /dev/null
+++ b/src/soc/intel/common/feature/smihandler/smihandler.c
@@ -0,0 +1,29 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <device/pci_def.h>
+#include <intelblocks/smihandler.h>
+#include <soc/pci_devs.h>
+#include <soc/pm.h>
+
+int smihandler_soc_disable_busmaster(pci_devfn_t dev)
+{
+	/* Skip disabling PMC bus master to keep IO decode enabled */
+	if (dev == SOC_PMC_DEV)
+		return 0;
+	return 1;
+}
+
+const smi_handler_t southbridge_smi[SMI_STS_BITS] = {
+	[SMI_ON_SLP_EN_STS_BIT] = smihandler_southbridge_sleep,
+	[APM_STS_BIT] = smihandler_southbridge_apmc,
+	[PM1_STS_BIT] = smihandler_southbridge_pm1,
+	[GPE0_STS_BIT] = smihandler_southbridge_gpe0,
+	[GPIO_STS_BIT] = smihandler_southbridge_gpi,
+	[ESPI_SMI_STS_BIT] = smihandler_southbridge_espi,
+	[MCSMI_STS_BIT] = smihandler_southbridge_mc,
+#if CONFIG(SOC_INTEL_COMMON_BLOCK_SMM_TCO_ENABLE)
+	[TCO_STS_BIT] = smihandler_southbridge_tco,
+#endif
+	[PERIODIC_STS_BIT] = smihandler_southbridge_periodic,
+	[MONITOR_STS_BIT] = smihandler_southbridge_monitor,
+};

From f0021f84ec0526f82ba871f134c073605351196a Mon Sep 17 00:00:00 2001
From: Jeremy Compostella <jeremy.compostella@intel.com>
Date: Thu, 26 Feb 2026 10:46:33 -0800
Subject: [PATCH 3530/3886] soc/intel/alderlake: Use common PCH client SMI
 handler

Migrate Alder Lake to use the common PCH client SMI handler
implementation from the Intel common feature code. This change
eliminates platform-specific code by leveraging the shared smihandler.c
driver.

This commit:
- Adds SOC_PMC_DEV macro definition to soc/pci_devs.h
- Selects SOC_INTEL_COMMON_FEATURE_SMIHANDLER Kconfig
- Removes src/soc/intel/alderlake/smihandler.c
- Updates Makefile to remove smihandler.c compilation

Alder Lake uses PCH_DEV_PMC as the PMC device identifier.

Change-Id: Icbbc7af25e73e952c9b5f811cf0bbe01efe3ae94
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91294
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Huang, Cliff <cliff.huang@intel.com>
---
 src/soc/intel/alderlake/Kconfig               |  1 +
 src/soc/intel/alderlake/Makefile.mk           |  1 -
 .../intel/alderlake/include/soc/pci_devs.h    |  1 +
 src/soc/intel/alderlake/smihandler.c          | 30 -------------------
 4 files changed, 2 insertions(+), 31 deletions(-)
 delete mode 100644 src/soc/intel/alderlake/smihandler.c

diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig
index 1568e5b595..a925cf09a0 100644
--- a/src/soc/intel/alderlake/Kconfig
+++ b/src/soc/intel/alderlake/Kconfig
@@ -88,6 +88,7 @@ config SOC_INTEL_ALDERLAKE
 	select SOC_INTEL_COMMON_FEATURE_ESPI
 	select SOC_INTEL_COMMON_FEATURE_GSPI_DEVFN
 	select SOC_INTEL_COMMON_FEATURE_PMUTIL
+	select SOC_INTEL_COMMON_FEATURE_SMIHANDLER
 	select SOC_INTEL_COMMON_FEATURE_SOUNDWIRE
 	select SOC_INTEL_COMMON_FEATURE_SPI_DEVFN
 	select SOC_INTEL_COMMON_FEATURE_SPI_DEVFN_PSF
diff --git a/src/soc/intel/alderlake/Makefile.mk b/src/soc/intel/alderlake/Makefile.mk
index 210d84592d..45c374849d 100644
--- a/src/soc/intel/alderlake/Makefile.mk
+++ b/src/soc/intel/alderlake/Makefile.mk
@@ -39,7 +39,6 @@ ramstage-$(CONFIG_SOC_INTEL_CRASHLOG) += crashlog.c
 
 smm-y += elog.c
 smm-y += p2sb.c
-smm-y += smihandler.c
 smm-y += xhci.c
 
 ifeq ($(CONFIG_SOC_INTEL_ALDERLAKE_PCH_S),y)
diff --git a/src/soc/intel/alderlake/include/soc/pci_devs.h b/src/soc/intel/alderlake/include/soc/pci_devs.h
index 15ec661870..27134c74a5 100644
--- a/src/soc/intel/alderlake/include/soc/pci_devs.h
+++ b/src/soc/intel/alderlake/include/soc/pci_devs.h
@@ -283,6 +283,7 @@
 #define PCI_DEVFN_UART1		PCH_DEVFN_UART1
 #define PCI_DEVFN_UART2		PCH_DEVFN_UART2
 #define SOC_GSPI_DEVFN(n)	PCH_DEVFN_GSPI##n
+#define SOC_PMC_DEV		PCH_DEV_PMC
 
 #endif
 
diff --git a/src/soc/intel/alderlake/smihandler.c b/src/soc/intel/alderlake/smihandler.c
deleted file mode 100644
index e1fc5a03ad..0000000000
--- a/src/soc/intel/alderlake/smihandler.c
+++ /dev/null
@@ -1,30 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <device/pci_def.h>
-#include <intelblocks/smihandler.h>
-#include <soc/soc_chip.h>
-#include <soc/pci_devs.h>
-#include <soc/pm.h>
-
-int smihandler_soc_disable_busmaster(pci_devfn_t dev)
-{
-	/* Skip disabling PMC bus master to keep IO decode enabled */
-	if (dev == PCH_DEV_PMC)
-		return 0;
-	return 1;
-}
-
-const smi_handler_t southbridge_smi[SMI_STS_BITS] = {
-	[SMI_ON_SLP_EN_STS_BIT] = smihandler_southbridge_sleep,
-	[APM_STS_BIT] = smihandler_southbridge_apmc,
-	[PM1_STS_BIT] = smihandler_southbridge_pm1,
-	[GPE0_STS_BIT] = smihandler_southbridge_gpe0,
-	[GPIO_STS_BIT] = smihandler_southbridge_gpi,
-	[ESPI_SMI_STS_BIT] = smihandler_southbridge_espi,
-	[MCSMI_STS_BIT] = smihandler_southbridge_mc,
-#if CONFIG(SOC_INTEL_COMMON_BLOCK_SMM_TCO_ENABLE)
-	[TCO_STS_BIT] = smihandler_southbridge_tco,
-#endif
-	[PERIODIC_STS_BIT] = smihandler_southbridge_periodic,
-	[MONITOR_STS_BIT] = smihandler_southbridge_monitor,
-};

From eb205e379ac0c46eb9fce1d037add0d55a1710e5 Mon Sep 17 00:00:00 2001
From: Jeremy Compostella <jeremy.compostella@intel.com>
Date: Thu, 26 Feb 2026 10:47:16 -0800
Subject: [PATCH 3531/3886] soc/intel/meteorlake: Use common PCH client SMI
 handler

Migrate Meteor Lake to use the common PCH client SMI handler
implementation from the Intel common feature code. This change
eliminates platform-specific code by leveraging the shared smihandler.c
driver.

This commit:
- Adds SOC_PMC_DEV macro definition to soc/pci_devs.h
- Selects SOC_INTEL_COMMON_FEATURE_SMIHANDLER Kconfig
- Removes src/soc/intel/meteorlake/smihandler.c
- Updates Makefile to remove smihandler.c compilation

Meteor Lake uses PCI_DEV_PMC as the PMC device identifier.

Change-Id: Ia21a6ee0c6fbee6d4ffcfce5fdbe9b3bdf5fcece
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91295
Reviewed-by: Huang, Cliff <cliff.huang@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/soc/intel/meteorlake/Kconfig              |  1 +
 src/soc/intel/meteorlake/Makefile.mk          |  1 -
 .../intel/meteorlake/include/soc/pci_devs.h   |  1 +
 src/soc/intel/meteorlake/smihandler.c         | 30 -------------------
 4 files changed, 2 insertions(+), 31 deletions(-)
 delete mode 100644 src/soc/intel/meteorlake/smihandler.c

diff --git a/src/soc/intel/meteorlake/Kconfig b/src/soc/intel/meteorlake/Kconfig
index 1ec20d25de..25d9d68e44 100644
--- a/src/soc/intel/meteorlake/Kconfig
+++ b/src/soc/intel/meteorlake/Kconfig
@@ -90,6 +90,7 @@ config SOC_INTEL_METEORLAKE
 	select SOC_INTEL_COMMON_FEATURE_ESPI
 	select SOC_INTEL_COMMON_FEATURE_GSPI_DEVFN
 	select SOC_INTEL_COMMON_FEATURE_PMUTIL
+	select SOC_INTEL_COMMON_FEATURE_SMIHANDLER
 	select SOC_INTEL_COMMON_FEATURE_SOUNDWIRE
 	select SOC_INTEL_COMMON_FEATURE_SPI_DEVFN
 	select SOC_INTEL_COMMON_FEATURE_SPI_DEVFN_PSF
diff --git a/src/soc/intel/meteorlake/Makefile.mk b/src/soc/intel/meteorlake/Makefile.mk
index 19ffa96d0e..b2c2429476 100644
--- a/src/soc/intel/meteorlake/Makefile.mk
+++ b/src/soc/intel/meteorlake/Makefile.mk
@@ -43,7 +43,6 @@ ramstage-y += soc_info.c
 smm-y += elog.c
 smm-y += gpio.c
 smm-y += p2sb.c
-smm-y += smihandler.c
 smm-y += soc_info.c
 smm-y += xhci.c
 
diff --git a/src/soc/intel/meteorlake/include/soc/pci_devs.h b/src/soc/intel/meteorlake/include/soc/pci_devs.h
index 17f4526538..61485fc450 100644
--- a/src/soc/intel/meteorlake/include/soc/pci_devs.h
+++ b/src/soc/intel/meteorlake/include/soc/pci_devs.h
@@ -243,5 +243,6 @@
 #define SA_DEVFN_IGD		PCI_DEVFN_IGD
 #define SOC_I2C_DEVFN(n)	PCI_DEVFN_I2C##n
 #define SOC_GSPI_DEVFN(n)	PCI_DEVFN_GSPI##n
+#define SOC_PMC_DEV		PCI_DEV_PMC
 
 #endif // _SOC_METEORLAKE_PCI_DEVS_H_
diff --git a/src/soc/intel/meteorlake/smihandler.c b/src/soc/intel/meteorlake/smihandler.c
deleted file mode 100644
index 6a21f0a757..0000000000
--- a/src/soc/intel/meteorlake/smihandler.c
+++ /dev/null
@@ -1,30 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <device/pci_def.h>
-#include <intelblocks/smihandler.h>
-#include <soc/soc_chip.h>
-#include <soc/pci_devs.h>
-#include <soc/pm.h>
-
-int smihandler_soc_disable_busmaster(pci_devfn_t dev)
-{
-	/* Skip disabling PMC bus master to keep IO decode enabled */
-	if (dev == PCI_DEV_PMC)
-		return 0;
-	return 1;
-}
-
-const smi_handler_t southbridge_smi[SMI_STS_BITS] = {
-	[SMI_ON_SLP_EN_STS_BIT] = smihandler_southbridge_sleep,
-	[APM_STS_BIT] = smihandler_southbridge_apmc,
-	[PM1_STS_BIT] = smihandler_southbridge_pm1,
-	[GPE0_STS_BIT] = smihandler_southbridge_gpe0,
-	[GPIO_STS_BIT] = smihandler_southbridge_gpi,
-	[ESPI_SMI_STS_BIT] = smihandler_southbridge_espi,
-	[MCSMI_STS_BIT] = smihandler_southbridge_mc,
-#if CONFIG(SOC_INTEL_COMMON_BLOCK_SMM_TCO_ENABLE)
-	[TCO_STS_BIT] = smihandler_southbridge_tco,
-#endif
-	[PERIODIC_STS_BIT] = smihandler_southbridge_periodic,
-	[MONITOR_STS_BIT] = smihandler_southbridge_monitor,
-};

From 402da237bcc855811079f356e6c047b82884ce9b Mon Sep 17 00:00:00 2001
From: Jeremy Compostella <jeremy.compostella@intel.com>
Date: Thu, 26 Feb 2026 10:47:44 -0800
Subject: [PATCH 3532/3886] soc/intel/pantherlake: Use common PCH client SMI
 handler

Migrate Panther Lake to use the common PCH client SMI handler
implementation from the Intel common feature code. This change
eliminates platform-specific code by leveraging the shared smihandler.c
driver.

This commit:
- Adds SOC_PMC_DEV macro definition to soc/pci_devs.h
- Selects SOC_INTEL_COMMON_FEATURE_SMIHANDLER Kconfig
- Removes src/soc/intel/pantherlake/smihandler.c
- Updates Makefile to remove smihandler.c compilation

Panther Lake uses PCI_DEV_PMC as the PMC device identifier.

TEST=Build and boot to the OS on a Fatcat device

Change-Id: I32bf4b678e7edda598319086acccc4983edcbe3e
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91296
Reviewed-by: Huang, Cliff <cliff.huang@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/soc/intel/pantherlake/Kconfig             |  1 +
 src/soc/intel/pantherlake/Makefile.mk         |  1 -
 .../intel/pantherlake/include/soc/pci_devs.h  |  1 +
 src/soc/intel/pantherlake/smihandler.c        | 30 -------------------
 4 files changed, 2 insertions(+), 31 deletions(-)
 delete mode 100644 src/soc/intel/pantherlake/smihandler.c

diff --git a/src/soc/intel/pantherlake/Kconfig b/src/soc/intel/pantherlake/Kconfig
index 937fb36a6b..decd4c84c6 100644
--- a/src/soc/intel/pantherlake/Kconfig
+++ b/src/soc/intel/pantherlake/Kconfig
@@ -100,6 +100,7 @@ config SOC_INTEL_PANTHERLAKE_BASE
 	select SOC_INTEL_COMMON_FEATURE_ESPI
 	select SOC_INTEL_COMMON_FEATURE_GSPI_DEVFN
 	select SOC_INTEL_COMMON_FEATURE_PMUTIL
+	select SOC_INTEL_COMMON_FEATURE_SMIHANDLER
 	select SOC_INTEL_COMMON_FEATURE_SOUNDWIRE
 	select SOC_INTEL_COMMON_FEATURE_SPI_DEVFN
 	select SOC_INTEL_COMMON_FEATURE_SPI_DEVFN_PSF
diff --git a/src/soc/intel/pantherlake/Makefile.mk b/src/soc/intel/pantherlake/Makefile.mk
index 417d27d6d0..7349987e28 100644
--- a/src/soc/intel/pantherlake/Makefile.mk
+++ b/src/soc/intel/pantherlake/Makefile.mk
@@ -42,7 +42,6 @@ ramstage-$(CONFIG_DRIVERS_INTEL_TOUCH) += touch.c
 smm-y += elog.c
 smm-y += gpio.c
 smm-y += p2sb.c
-smm-y += smihandler.c
 smm-y += xhci.c
 CPPFLAGS_common += -I$(src)/soc/intel/pantherlake
 CPPFLAGS_common += -I$(src)/soc/intel/pantherlake/include
diff --git a/src/soc/intel/pantherlake/include/soc/pci_devs.h b/src/soc/intel/pantherlake/include/soc/pci_devs.h
index 3a41280a26..1834dec9a5 100644
--- a/src/soc/intel/pantherlake/include/soc/pci_devs.h
+++ b/src/soc/intel/pantherlake/include/soc/pci_devs.h
@@ -258,5 +258,6 @@
 #define SA_DEVFN_IGD		PCI_DEVFN_IGD
 #define SOC_I2C_DEVFN(n)	PCI_DEVFN_I2C##n
 #define SOC_GSPI_DEVFN(n)	PCI_DEVFN_GSPI##n
+#define SOC_PMC_DEV		PCI_DEV_PMC
 
 #endif // _SOC_PANTHERLAKE_PCI_DEVS_H_
diff --git a/src/soc/intel/pantherlake/smihandler.c b/src/soc/intel/pantherlake/smihandler.c
deleted file mode 100644
index 6a21f0a757..0000000000
--- a/src/soc/intel/pantherlake/smihandler.c
+++ /dev/null
@@ -1,30 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <device/pci_def.h>
-#include <intelblocks/smihandler.h>
-#include <soc/soc_chip.h>
-#include <soc/pci_devs.h>
-#include <soc/pm.h>
-
-int smihandler_soc_disable_busmaster(pci_devfn_t dev)
-{
-	/* Skip disabling PMC bus master to keep IO decode enabled */
-	if (dev == PCI_DEV_PMC)
-		return 0;
-	return 1;
-}
-
-const smi_handler_t southbridge_smi[SMI_STS_BITS] = {
-	[SMI_ON_SLP_EN_STS_BIT] = smihandler_southbridge_sleep,
-	[APM_STS_BIT] = smihandler_southbridge_apmc,
-	[PM1_STS_BIT] = smihandler_southbridge_pm1,
-	[GPE0_STS_BIT] = smihandler_southbridge_gpe0,
-	[GPIO_STS_BIT] = smihandler_southbridge_gpi,
-	[ESPI_SMI_STS_BIT] = smihandler_southbridge_espi,
-	[MCSMI_STS_BIT] = smihandler_southbridge_mc,
-#if CONFIG(SOC_INTEL_COMMON_BLOCK_SMM_TCO_ENABLE)
-	[TCO_STS_BIT] = smihandler_southbridge_tco,
-#endif
-	[PERIODIC_STS_BIT] = smihandler_southbridge_periodic,
-	[MONITOR_STS_BIT] = smihandler_southbridge_monitor,
-};

From d03957e10fe0645b52a59b652226925d11b300cb Mon Sep 17 00:00:00 2001
From: Jeremy Compostella <jeremy.compostella@intel.com>
Date: Thu, 26 Feb 2026 10:48:14 -0800
Subject: [PATCH 3533/3886] soc/intel/tigerlake: Use common PCH client SMI
 handler

Migrate Tiger Lake to use the common PCH client SMI handler
implementation from the Intel common feature code. This change
eliminates platform-specific code by leveraging the shared smihandler.c
driver.

This commit:
- Adds SOC_PMC_DEV macro definition to soc/pci_devs.h
- Selects SOC_INTEL_COMMON_FEATURE_SMIHANDLER Kconfig
- Removes src/soc/intel/tigerlake/smihandler.c
- Updates Makefile to remove smihandler.c compilation

Tiger Lake uses PCH_DEV_PMC as the PMC device identifier.

Change-Id: Ibe06e4d100b2715aeccfe0ff85dc944ab6cd80fc
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91297
Reviewed-by: Huang, Cliff <cliff.huang@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/soc/intel/tigerlake/Kconfig               |  1 +
 src/soc/intel/tigerlake/Makefile.mk           |  1 -
 .../intel/tigerlake/include/soc/pci_devs.h    |  1 +
 src/soc/intel/tigerlake/smihandler.c          | 30 -------------------
 4 files changed, 2 insertions(+), 31 deletions(-)
 delete mode 100644 src/soc/intel/tigerlake/smihandler.c

diff --git a/src/soc/intel/tigerlake/Kconfig b/src/soc/intel/tigerlake/Kconfig
index a470d7cde5..192444ec11 100644
--- a/src/soc/intel/tigerlake/Kconfig
+++ b/src/soc/intel/tigerlake/Kconfig
@@ -75,6 +75,7 @@ config SOC_INTEL_TIGERLAKE
 	select SOC_INTEL_COMMON_FEATURE
 	select SOC_INTEL_COMMON_FEATURE_ESPI
 	select SOC_INTEL_COMMON_FEATURE_GSPI_DEVFN
+	select SOC_INTEL_COMMON_FEATURE_SMIHANDLER
 	select SOC_INTEL_COMMON_FEATURE_SOUNDWIRE
 	select SOC_INTEL_COMMON_FEATURE_SPI_DEVFN
 	select SOC_INTEL_COMMON_FEATURE_SPI_DEVFN_PSF
diff --git a/src/soc/intel/tigerlake/Makefile.mk b/src/soc/intel/tigerlake/Makefile.mk
index cf6cdc2ec2..5caff77277 100644
--- a/src/soc/intel/tigerlake/Makefile.mk
+++ b/src/soc/intel/tigerlake/Makefile.mk
@@ -38,7 +38,6 @@ ramstage-$(CONFIG_SOC_INTEL_CRASHLOG) += crashlog_lib.c
 
 smm-y += p2sb.c
 smm-y += pmutil.c
-smm-y += smihandler.c
 smm-y += elog.c
 smm-y += xhci.c
 
diff --git a/src/soc/intel/tigerlake/include/soc/pci_devs.h b/src/soc/intel/tigerlake/include/soc/pci_devs.h
index 2f36bd159c..8b49773354 100644
--- a/src/soc/intel/tigerlake/include/soc/pci_devs.h
+++ b/src/soc/intel/tigerlake/include/soc/pci_devs.h
@@ -250,6 +250,7 @@
 #define PCI_DEVFN_UART1		PCH_DEVFN_UART1
 #define PCI_DEVFN_UART2		PCH_DEVFN_UART2
 #define SOC_GSPI_DEVFN(n)	PCH_DEVFN_GSPI##n
+#define SOC_PMC_DEV		PCH_DEV_PMC
 
 #endif
 
diff --git a/src/soc/intel/tigerlake/smihandler.c b/src/soc/intel/tigerlake/smihandler.c
deleted file mode 100644
index e1fc5a03ad..0000000000
--- a/src/soc/intel/tigerlake/smihandler.c
+++ /dev/null
@@ -1,30 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <device/pci_def.h>
-#include <intelblocks/smihandler.h>
-#include <soc/soc_chip.h>
-#include <soc/pci_devs.h>
-#include <soc/pm.h>
-
-int smihandler_soc_disable_busmaster(pci_devfn_t dev)
-{
-	/* Skip disabling PMC bus master to keep IO decode enabled */
-	if (dev == PCH_DEV_PMC)
-		return 0;
-	return 1;
-}
-
-const smi_handler_t southbridge_smi[SMI_STS_BITS] = {
-	[SMI_ON_SLP_EN_STS_BIT] = smihandler_southbridge_sleep,
-	[APM_STS_BIT] = smihandler_southbridge_apmc,
-	[PM1_STS_BIT] = smihandler_southbridge_pm1,
-	[GPE0_STS_BIT] = smihandler_southbridge_gpe0,
-	[GPIO_STS_BIT] = smihandler_southbridge_gpi,
-	[ESPI_SMI_STS_BIT] = smihandler_southbridge_espi,
-	[MCSMI_STS_BIT] = smihandler_southbridge_mc,
-#if CONFIG(SOC_INTEL_COMMON_BLOCK_SMM_TCO_ENABLE)
-	[TCO_STS_BIT] = smihandler_southbridge_tco,
-#endif
-	[PERIODIC_STS_BIT] = smihandler_southbridge_periodic,
-	[MONITOR_STS_BIT] = smihandler_southbridge_monitor,
-};

From c940d20696b4200bfa47c48f3f86a6d8f9ff6147 Mon Sep 17 00:00:00 2001
From: Jeremy Compostella <jeremy.compostella@intel.com>
Date: Thu, 26 Feb 2026 11:03:57 -0800
Subject: [PATCH 3534/3886] soc/intel: Consolidate common code macro
 definitions in pci_devs.h

Move the SOC_I2C_DEVFN(n) macro definitions that were duplicated in a
separate "for common code" section at the end of multiple platform
pci_devs.h files.

Platforms affected:
- Alder Lake
- Cannon Lake
- Elkhart Lake
- Jasper Lake
- Skylake
- Tiger Lake

Change-Id: Ie3b3e6a25b0dba1beeadad1ab9acf59cafdbcf4a
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91446
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Guvendik, Bora <bora.guvendik@intel.com>
---
 src/soc/intel/alderlake/include/soc/pci_devs.h   | 4 +---
 src/soc/intel/cannonlake/include/soc/pci_devs.h  | 4 +---
 src/soc/intel/elkhartlake/include/soc/pci_devs.h | 4 +---
 src/soc/intel/jasperlake/include/soc/pci_devs.h  | 4 +---
 src/soc/intel/skylake/include/soc/pci_devs.h     | 4 +---
 src/soc/intel/tigerlake/include/soc/pci_devs.h   | 4 +---
 6 files changed, 6 insertions(+), 18 deletions(-)

diff --git a/src/soc/intel/alderlake/include/soc/pci_devs.h b/src/soc/intel/alderlake/include/soc/pci_devs.h
index 27134c74a5..a3f1d7520d 100644
--- a/src/soc/intel/alderlake/include/soc/pci_devs.h
+++ b/src/soc/intel/alderlake/include/soc/pci_devs.h
@@ -284,8 +284,6 @@
 #define PCI_DEVFN_UART2		PCH_DEVFN_UART2
 #define SOC_GSPI_DEVFN(n)	PCH_DEVFN_GSPI##n
 #define SOC_PMC_DEV		PCH_DEV_PMC
+#define SOC_I2C_DEVFN(n)	PCH_DEVFN_I2C##n
 
 #endif
-
-/* for common code */
-#define SOC_I2C_DEVFN(n)	PCH_DEVFN_I2C##n
diff --git a/src/soc/intel/cannonlake/include/soc/pci_devs.h b/src/soc/intel/cannonlake/include/soc/pci_devs.h
index c2d7b411ba..a099294cf2 100644
--- a/src/soc/intel/cannonlake/include/soc/pci_devs.h
+++ b/src/soc/intel/cannonlake/include/soc/pci_devs.h
@@ -209,8 +209,6 @@
 #define PCI_DEVFN_UART1		PCH_DEVFN_UART1
 #define PCI_DEVFN_UART2		PCH_DEVFN_UART2
 #define SOC_GSPI_DEVFN(n)	PCH_DEVFN_GSPI##n
+#define SOC_I2C_DEVFN(n)	PCH_DEVFN_I2C##n
 
 #endif
-
-/* for common code */
-#define SOC_I2C_DEVFN(n)	PCH_DEVFN_I2C##n
diff --git a/src/soc/intel/elkhartlake/include/soc/pci_devs.h b/src/soc/intel/elkhartlake/include/soc/pci_devs.h
index e4e899b881..1dd6d6c678 100644
--- a/src/soc/intel/elkhartlake/include/soc/pci_devs.h
+++ b/src/soc/intel/elkhartlake/include/soc/pci_devs.h
@@ -252,8 +252,6 @@
 #define PCI_DEVFN_UART1		PCH_DEVFN_UART1
 #define PCI_DEVFN_UART2		PCH_DEVFN_UART2
 #define SOC_GSPI_DEVFN(n)	PCH_DEVFN_GSPI##n
+#define SOC_I2C_DEVFN(n)	PCH_DEVFN_I2C##n
 
 #endif
-
-/* for common code */
-#define SOC_I2C_DEVFN(n)	PCH_DEVFN_I2C##n
diff --git a/src/soc/intel/jasperlake/include/soc/pci_devs.h b/src/soc/intel/jasperlake/include/soc/pci_devs.h
index f2e6dd4e7d..4267d9bfdf 100644
--- a/src/soc/intel/jasperlake/include/soc/pci_devs.h
+++ b/src/soc/intel/jasperlake/include/soc/pci_devs.h
@@ -198,8 +198,6 @@
 #define PCI_DEVFN_UART1		PCH_DEVFN_UART1
 #define PCI_DEVFN_UART2		PCH_DEVFN_UART2
 #define SOC_GSPI_DEVFN(n)	PCH_DEVFN_GSPI##n
+#define SOC_I2C_DEVFN(n)	PCH_DEVFN_I2C##n
 
 #endif
-
-/* for common code */
-#define SOC_I2C_DEVFN(n)	PCH_DEVFN_I2C##n
diff --git a/src/soc/intel/skylake/include/soc/pci_devs.h b/src/soc/intel/skylake/include/soc/pci_devs.h
index 557dc58c55..876170cfce 100644
--- a/src/soc/intel/skylake/include/soc/pci_devs.h
+++ b/src/soc/intel/skylake/include/soc/pci_devs.h
@@ -192,8 +192,6 @@
 #define PCI_DEVFN_UART1		PCH_DEVFN_UART1
 #define PCI_DEVFN_UART2		PCH_DEVFN_UART2
 #define SOC_GSPI_DEVFN(n)	PCH_DEVFN_GSPI##n
+#define SOC_I2C_DEVFN(n)	PCH_DEVFN_I2C##n
 
 #endif
-
-/* for common code */
-#define SOC_I2C_DEVFN(n)	PCH_DEVFN_I2C##n
diff --git a/src/soc/intel/tigerlake/include/soc/pci_devs.h b/src/soc/intel/tigerlake/include/soc/pci_devs.h
index 8b49773354..66eff3490c 100644
--- a/src/soc/intel/tigerlake/include/soc/pci_devs.h
+++ b/src/soc/intel/tigerlake/include/soc/pci_devs.h
@@ -251,8 +251,6 @@
 #define PCI_DEVFN_UART2		PCH_DEVFN_UART2
 #define SOC_GSPI_DEVFN(n)	PCH_DEVFN_GSPI##n
 #define SOC_PMC_DEV		PCH_DEV_PMC
+#define SOC_I2C_DEVFN(n)	PCH_DEVFN_I2C##n
 
 #endif
-
-/* for common code */
-#define SOC_I2C_DEVFN(n)	PCH_DEVFN_I2C##n

From 19df8826d751cc82a7ec1fb9a679b7ebdfbb22f5 Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Tue, 17 Feb 2026 08:55:51 +0000
Subject: [PATCH 3535/3886] mb/starlabs/starlite_adl: Disable the card reader
 by default

As the card reader isn't on a dedicated USB interface for all variants
for the StarLite, default to disable to ensure that an unused USB port
isn't enabled.

Change-Id: I2176fd6556797e468012c98f7e482b9573b5e3f7
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91496
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
---
 src/mainboard/starlabs/common/include/common/cfr.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/mainboard/starlabs/common/include/common/cfr.h b/src/mainboard/starlabs/common/include/common/cfr.h
index b62b39701e..0deb7eeb7e 100644
--- a/src/mainboard/starlabs/common/include/common/cfr.h
+++ b/src/mainboard/starlabs/common/include/common/cfr.h
@@ -37,7 +37,7 @@ static const struct sm_object card_reader = SM_DECLARE_BOOL({
 	.opt_name	= "card_reader",
 	.ui_name	= "Card Reader",
 	.ui_helptext	= "Enable or disable the built-in card reader",
-	.default_value	= true,
+	.default_value	= !CONFIG(BOARD_STARLABS_LITE_ADL),
 }, WITH_CALLBACK(cfr_card_reader_update));
 
 static const struct sm_object display_native_res = SM_DECLARE_BOOL({

From 56f588eec69a81f44b58a5ad180f380115085cf6 Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Tue, 17 Feb 2026 20:20:33 +0000
Subject: [PATCH 3536/3886] mb/starlabs/*: Don't consider fan presence for
 default power profile

Set the default power profile to Performance, regardless of whether
there is a fan present.

Change-Id: Id1d624355f9f08b5abb154e26026e70675322ddb
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91497
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
---
 src/mainboard/starlabs/common/include/common/cfr.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/mainboard/starlabs/common/include/common/cfr.h b/src/mainboard/starlabs/common/include/common/cfr.h
index 0deb7eeb7e..89405fd2b7 100644
--- a/src/mainboard/starlabs/common/include/common/cfr.h
+++ b/src/mainboard/starlabs/common/include/common/cfr.h
@@ -103,7 +103,7 @@ static const struct sm_object power_profile = SM_DECLARE_ENUM({
 	.opt_name	= "power_profile",
 	.ui_name	= "Power Profile",
 	.ui_helptext	= "Select whether to maximize performance, battery life or both.",
-	.default_value	= CONFIG(EC_STARLABS_FAN) ? PP_PERFORMANCE : PP_BALANCED,
+	.default_value	= PP_PERFORMANCE,
 	.values		= (const struct sm_enum_value[]) {
 			{ "Power Saver",	PP_POWER_SAVER	},
 			{ "Balanced",		PP_BALANCED	},

From 3ea94fb2dc6d0bde9878967205da2094a5a2b1ca Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Tue, 17 Feb 2026 20:29:09 +0000
Subject: [PATCH 3537/3886] mb/starlabs/starfighter: Enable the card reader

Enable the card reader USB port, along with ACPI driver info
and the CFR option to control it.

Change-Id: I30dd26438f0a7b355061a45b9ffb7f447c89a751
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91498
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
---
 src/mainboard/starlabs/starfighter/cfr.c              |  1 +
 .../starlabs/starfighter/variants/mtl/devicetree.cb   | 11 ++++++++++-
 .../starlabs/starfighter/variants/rpl/devicetree.cb   |  9 +++++++++
 3 files changed, 20 insertions(+), 1 deletion(-)

diff --git a/src/mainboard/starlabs/starfighter/cfr.c b/src/mainboard/starlabs/starfighter/cfr.c
index cb092cae33..6cdd98b189 100644
--- a/src/mainboard/starlabs/starfighter/cfr.c
+++ b/src/mainboard/starlabs/starfighter/cfr.c
@@ -40,6 +40,7 @@ static struct sm_obj_form display_group = {
 static struct sm_obj_form io_expansion_group = {
 	.ui_name = "I/O / Expansion",
 	.obj_list = (const struct sm_object *[]) {
+		&card_reader,
 		&thunderbolt,
 		NULL
 	},
diff --git a/src/mainboard/starlabs/starfighter/variants/mtl/devicetree.cb b/src/mainboard/starlabs/starfighter/variants/mtl/devicetree.cb
index 23ad639cc2..b7b8cedf85 100644
--- a/src/mainboard/starlabs/starfighter/variants/mtl/devicetree.cb
+++ b/src/mainboard/starlabs/starfighter/variants/mtl/devicetree.cb
@@ -160,6 +160,9 @@ chip soc/intel/meteorlake
 			register "usb2_ports[6]"		= "USB2_PORT_SHORT(OC_SKIP)"
 			register "usb3_ports[1]"		= "USB3_PORT_DEFAULT(OC_SKIP)"
 
+			# Card Reader
+			register "usb2_ports[3]"		= "USB2_PORT_SHORT(OC_SKIP)"
+
 			# Internal Webcam			9070 mil
 			register "usb2_ports[CONFIG_CCD_PORT]"	= "USB2_PORT_MID(OC_SKIP)"
 
@@ -207,9 +210,15 @@ chip soc/intel/meteorlake
 						device ref usb3_port2 on end
 					end
 					chip drivers/usb/acpi
-						register "desc"			= ""Internal Webcam""
+						register "desc"			= ""Card Reader""
 						register "type"			= "UPC_TYPE_INTERNAL"
 						register "group"		= "ACPI_PLD_GROUP(0, 4)"
+						device ref usb2_port4 on end
+					end
+					chip drivers/usb/acpi
+						register "desc"			= ""Internal Webcam""
+						register "type"			= "UPC_TYPE_INTERNAL"
+						register "group"		= "ACPI_PLD_GROUP(0, 5)"
 						device ref usb2_port5 on end
 					end
 					chip drivers/usb/acpi
diff --git a/src/mainboard/starlabs/starfighter/variants/rpl/devicetree.cb b/src/mainboard/starlabs/starfighter/variants/rpl/devicetree.cb
index c911b05a4b..080bde0a19 100644
--- a/src/mainboard/starlabs/starfighter/variants/rpl/devicetree.cb
+++ b/src/mainboard/starlabs/starfighter/variants/rpl/devicetree.cb
@@ -139,6 +139,9 @@ chip soc/intel/alderlake
 			register "usb2_ports[6]"		= "USB2_PORT_MID(OC_SKIP)"
 			register "usb3_ports[1]"		= "USB3_PORT_DEFAULT(OC_SKIP)"
 
+			# Card Reader
+			register "usb2_ports[3]"		= "USB2_PORT_SHORT(OC_SKIP)"
+
 			# Internal Bluetooth
 			register "usb2_ports[9]"		= "USB2_PORT_MID(OC_SKIP)"
 
@@ -182,6 +185,12 @@ chip soc/intel/alderlake
 						register "group"		= "ACPI_PLD_GROUP(0, 3)"
 						device ref usb3_port2 on end
 					end
+					chip drivers/usb/acpi
+						register "desc"			= ""Card Reader""
+						register "type"			= "UPC_TYPE_INTERNAL"
+						register "group"		= "ACPI_PLD_GROUP(0, 4)"
+						device ref usb2_port4 on end
+					end
 					chip drivers/usb/acpi
 						register "desc"			= ""Internal Webcam""
 						register "group"		= "ACPI_PLD_GROUP(0, 4)"

From e02dc13b87e2ab32a5736ca464b6c6847c7c2274 Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Sun, 15 Feb 2026 21:18:19 +0000
Subject: [PATCH 3538/3886] mainboard/starlabs: move Byte under adl/

Move the Star Labs Byte (Mk II / Mk III) into the ADL grouping under
src/mainboard/starlabs/adl/.

Like StarBook Horizon, model differences live under
src/mainboard/starlabs/adl/variants/ using SKU-style variant directories
to share common configuration. Byte Mk II (ADL) and Byte Mk III (TWL)
share a single "y2" variant directory.

Update MAINBOARD_DIR and CMOS layout handling so binary blob paths and
NVRAM options continue to resolve correctly.

Update the documentation to reflect the new blobs path.

Note that BUILD_TIMELESS ROM hashes change since MAINBOARD_DIR is
embedded in the CBFS config file.

BUG=None
TEST=BUILD_TIMELESS=1 build STARLABS_BYTE_ADL
Change-Id: I4b6be115a4ab2316d5ca4cc8e656e3643518273e
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91255
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 Documentation/mainboard/index.md              |   2 +-
 .../starlabs/{byte_adl.md => byte.md}         |   8 +-
 src/mainboard/starlabs/adl/Kconfig            | 109 +++++++++++-----
 src/mainboard/starlabs/adl/Kconfig.name       |   8 +-
 src/mainboard/starlabs/adl/board_info.txt     |   2 +-
 src/mainboard/starlabs/adl/cfr.c              |  12 ++
 src/mainboard/starlabs/adl/dsdt.asl           |   5 +-
 .../adl/{ => variants/hz}/cmos.layout         |   0
 .../mk_ii => adl/variants/y2}/Makefile.mk     |   2 +
 .../mk_ii => adl/variants/y2}/board.fmd       |   0
 .../{byte_adl => adl/variants/y2}/cmos.layout |   0
 .../mk_ii => adl/variants/y2}/data.vbt        | Bin
 .../mk_ii => adl/variants/y2}/devicetree.cb   |   0
 .../mk_ii => adl/variants/y2}/devtree.c       |   0
 .../variants/mk_ii => adl/variants/y2}/gpio.c |   2 +-
 .../mk_ii => adl/variants/y2}/hda_verb.c      |   0
 .../mk_ii => adl/variants/y2}/ramstage.c      |   0
 .../mk_ii => adl/variants/y2}/romstage.c      |   0
 .../variants/y2}/smihandler.c                 |   0
 .../mk_ii => adl/variants/y2}/vboot.fmd       |   0
 src/mainboard/starlabs/byte_adl/Kconfig       | 116 ------------------
 src/mainboard/starlabs/byte_adl/Kconfig.name  |   7 --
 src/mainboard/starlabs/byte_adl/Makefile.mk   |  13 --
 src/mainboard/starlabs/byte_adl/acpi/ec.asl   |   1 -
 .../starlabs/byte_adl/acpi/mainboard.asl      |   5 -
 .../starlabs/byte_adl/acpi/sleep.asl          |  11 --
 .../starlabs/byte_adl/acpi/superio.asl        |   1 -
 .../starlabs/byte_adl/board_info.txt          |   6 -
 src/mainboard/starlabs/byte_adl/bootblock.c   |  14 ---
 src/mainboard/starlabs/byte_adl/cfr.c         | 100 ---------------
 src/mainboard/starlabs/byte_adl/dsdt.asl      |  42 -------
 .../starlabs/byte_adl/include/variants.h      |  17 ---
 src/mainboard/starlabs/byte_adl/mainboard.c   |  18 ---
 src/mainboard/starlabs/byte_adl/vboot.c       |   8 --
 34 files changed, 111 insertions(+), 398 deletions(-)
 rename Documentation/mainboard/starlabs/{byte_adl.md => byte.md} (86%)
 rename src/mainboard/starlabs/adl/{ => variants/hz}/cmos.layout (100%)
 rename src/mainboard/starlabs/{byte_adl/variants/mk_ii => adl/variants/y2}/Makefile.mk (79%)
 rename src/mainboard/starlabs/{byte_adl/variants/mk_ii => adl/variants/y2}/board.fmd (100%)
 rename src/mainboard/starlabs/{byte_adl => adl/variants/y2}/cmos.layout (100%)
 rename src/mainboard/starlabs/{byte_adl/variants/mk_ii => adl/variants/y2}/data.vbt (100%)
 rename src/mainboard/starlabs/{byte_adl/variants/mk_ii => adl/variants/y2}/devicetree.cb (100%)
 rename src/mainboard/starlabs/{byte_adl/variants/mk_ii => adl/variants/y2}/devtree.c (100%)
 rename src/mainboard/starlabs/{byte_adl/variants/mk_ii => adl/variants/y2}/gpio.c (99%)
 rename src/mainboard/starlabs/{byte_adl/variants/mk_ii => adl/variants/y2}/hda_verb.c (100%)
 rename src/mainboard/starlabs/{byte_adl/variants/mk_ii => adl/variants/y2}/ramstage.c (100%)
 rename src/mainboard/starlabs/{byte_adl/variants/mk_ii => adl/variants/y2}/romstage.c (100%)
 rename src/mainboard/starlabs/{byte_adl => adl/variants/y2}/smihandler.c (100%)
 rename src/mainboard/starlabs/{byte_adl/variants/mk_ii => adl/variants/y2}/vboot.fmd (100%)
 delete mode 100644 src/mainboard/starlabs/byte_adl/Kconfig
 delete mode 100644 src/mainboard/starlabs/byte_adl/Kconfig.name
 delete mode 100644 src/mainboard/starlabs/byte_adl/Makefile.mk
 delete mode 100644 src/mainboard/starlabs/byte_adl/acpi/ec.asl
 delete mode 100644 src/mainboard/starlabs/byte_adl/acpi/mainboard.asl
 delete mode 100644 src/mainboard/starlabs/byte_adl/acpi/sleep.asl
 delete mode 100644 src/mainboard/starlabs/byte_adl/acpi/superio.asl
 delete mode 100644 src/mainboard/starlabs/byte_adl/board_info.txt
 delete mode 100644 src/mainboard/starlabs/byte_adl/bootblock.c
 delete mode 100644 src/mainboard/starlabs/byte_adl/cfr.c
 delete mode 100644 src/mainboard/starlabs/byte_adl/dsdt.asl
 delete mode 100644 src/mainboard/starlabs/byte_adl/include/variants.h
 delete mode 100644 src/mainboard/starlabs/byte_adl/mainboard.c
 delete mode 100644 src/mainboard/starlabs/byte_adl/vboot.c

diff --git a/Documentation/mainboard/index.md b/Documentation/mainboard/index.md
index 92aec1173f..a90e3f2396 100644
--- a/Documentation/mainboard/index.md
+++ b/Documentation/mainboard/index.md
@@ -359,7 +359,7 @@ StarBook Mk VI <starlabs/starbook_adl.md>
 StarBook Mk VII (N200) <starlabs/starbook_adl_n.md>
 StarBook Mk VII (165H) <starlabs/starbook_mtl.md>
 StarBook Horizon <starlabs/adl_horizon.md>
-Byte Mk II <starlabs/byte_adl.md>
+Byte Mk II <starlabs/byte.md>
 StarFighter Mk I <starlabs/starfighter_rpl.md>
 StarFighter Mk II <starlabs/starfighter_mtl.md>
 
diff --git a/Documentation/mainboard/starlabs/byte_adl.md b/Documentation/mainboard/starlabs/byte.md
similarity index 86%
rename from Documentation/mainboard/starlabs/byte_adl.md
rename to Documentation/mainboard/starlabs/byte.md
index 7805bb5737..4c9a86cb1a 100644
--- a/Documentation/mainboard/starlabs/byte_adl.md
+++ b/Documentation/mainboard/starlabs/byte.md
@@ -34,7 +34,7 @@
 
 ## Building coreboot
 
-Please follow the [Star Labs build instructions](common/building.md) to build coreboot, using `config.starlabs_byte_adl` as config file.
+Please follow the [Star Labs build instructions](common/building.md) to build coreboot, using `config.starlabs_byte_adl` (Byte Mk II) or `config.starlabs_byte_twl` (Byte Mk III) as config file.
 
 ### Preliminaries
 
@@ -46,6 +46,10 @@ Prior to building coreboot the following files are required:
 The files listed below are optional:
 - Splash screen image in Windows 3.1 BMP format (Logo.bmp)
 
+coreboot expects these binaries under
+`3rdparty/blobs/mainboard/starlabs/adl/<variant>/`, where `<variant>`
+matches `CONFIG_VARIANT_DIR` (default: `y2`).
+
 These files exist in the correct location in the StarLabsLtd/blobs repo on GitHub which is used in place of the standard 3rdparty/blobs repo.
 
 ### Build
@@ -55,6 +59,8 @@ The following commands will build a working image:
 ```bash
 make distclean
 make defconfig KBUILD_DEFCONFIG=configs/config.starlabs_byte_adl
+# or
+make defconfig KBUILD_DEFCONFIG=configs/config.starlabs_byte_twl
 make
 ```
 
diff --git a/src/mainboard/starlabs/adl/Kconfig b/src/mainboard/starlabs/adl/Kconfig
index adfa25bb8d..8b5c5d8b64 100644
--- a/src/mainboard/starlabs/adl/Kconfig
+++ b/src/mainboard/starlabs/adl/Kconfig
@@ -1,23 +1,17 @@
 config BOARD_STARLABS_ADL_SERIES
 	def_bool n
 	select AZALIA_USE_LEGACY_VERB_TABLE
+	select BOARD_ROMSIZE_KB_16384
 	select CSE_DEFAULT_CFR_OPTION_STATE_DISABLED
 	select DRIVERS_EFI_VARIABLE_STORE
-	select DRIVERS_GFX_GENERIC
-	select DRIVERS_I2C_HID
 	select DRIVERS_INTEL_PMC
 	select DRIVERS_OPTION_CFR_ENABLED
 	select EC_STARLABS_MERLIN
 	select HAVE_ACPI_RESUME
 	select HAVE_ACPI_TABLES
-	select HAVE_CMOS_DEFAULT
-	select HAVE_HDA_DMIC
 	select HAVE_OPTION_TABLE
-	select HAVE_SPD_IN_CBFS
 	select INTEL_GMA_HAVE_VBT
 	select INTEL_LPSS_UART_FOR_CONSOLE
-	select MAINBOARD_HAS_TPM2
-	select MEMORY_MAPPED_TPM
 	select NO_UART_ON_SUPERIO
 	select PMC_IPC_ACPI_INTERFACE
 	select SOC_INTEL_ALDERLAKE
@@ -26,21 +20,43 @@ config BOARD_STARLABS_ADL_SERIES
 	select SOC_INTEL_CRASHLOG
 	select SPD_READ_BY_WORD
 	select SPI_FLASH_WINBOND
-	select SYSTEM_TYPE_LAPTOP
 	select TPM2
-	select TPM_MEASURED_BOOT
 	select VALIDATE_INTEL_DESCRIPTOR
 
 config BOARD_STARLABS_ADL_HORIZON
-	select BOARD_ROMSIZE_KB_16384
 	select BOARD_STARLABS_ADL_SERIES
+	select DRIVERS_GFX_GENERIC
+	select DRIVERS_I2C_HID
+	select HAVE_CMOS_DEFAULT
+	select HAVE_HDA_DMIC
+	select HAVE_SPD_IN_CBFS
+	select MAINBOARD_HAS_TPM2
+	select MEMORY_MAPPED_TPM
 	select SOC_INTEL_ALDERLAKE_PCH_N
+	select SYSTEM_TYPE_LAPTOP
+	select TPM_MEASURED_BOOT
 
-if BOARD_STARLABS_ADL_HORIZON
+config BOARD_STARLABS_BYTE_ADL
+	select BOARD_STARLABS_ADL_SERIES
+	select CRB_TPM
+	select DRIVERS_PCIE_GENERIC
+	select EC_STARLABS_FAN
+	select HAVE_INTEL_PTT
+	select SOC_INTEL_ALDERLAKE_PCH_N
+	select SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES
+	select SYSTEM_TYPE_MINIPC
 
-config CCD_PORT
-	int
-	default 4
+config BOARD_STARLABS_BYTE_TWL
+	select BOARD_STARLABS_ADL_SERIES
+	select CRB_TPM
+	select DRIVERS_PCIE_GENERIC
+	select EC_STARLABS_FAN
+	select HAVE_INTEL_PTT
+	select SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES
+	select SOC_INTEL_TWINLAKE
+	select SYSTEM_TYPE_MINIPC
+
+if BOARD_STARLABS_ADL_SERIES
 
 config CONSOLE_SERIAL
 	default n if !EDK2_DEBUG
@@ -58,20 +74,12 @@ config EDK2_BOOTSPLASH_FILE
 	string
 	default "3rdparty/blobs/mainboard/starlabs/Logo.bmp"
 
-config EC_STARLABS_BATTERY_MODEL
-	default "U5266122PV-2S1P"
-
-config EC_STARLABS_BATTERY_TYPE
-	default "LION"
-
-config EC_STARLABS_BATTERY_OEM
-	default "Shenzhen Utility Energy Co., Ltd"
-
 config EC_STARLABS_ITE_BIN_PATH
 	string
 	default "3rdparty/blobs/mainboard/\$(MAINBOARDDIR)/\$(CONFIG_VARIANT_DIR)/ec.bin"
 
 config FMDFILE
+	default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/variants/\$(CONFIG_VARIANT_DIR)/vboot.fmd" if VBOOT
 	default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/variants/\$(CONFIG_VARIANT_DIR)/board.fmd"
 
 config IFD_BIN_PATH
@@ -83,13 +91,18 @@ config MAINBOARD_DIR
 
 config MAINBOARD_FAMILY
 	string
-	default "HZ"
+	default "HZ" if BOARD_STARLABS_ADL_HORIZON
+	default "Y3" if BOARD_STARLABS_BYTE_TWL
+	default "Y2" if BOARD_STARLABS_BYTE_ADL
 
 config MAINBOARD_PART_NUMBER
-	default "StarBook Horizon"
+	default "StarBook Horizon" if BOARD_STARLABS_ADL_HORIZON
+	default "Byte Mk III" if BOARD_STARLABS_BYTE_TWL
+	default "Byte Mk II" if BOARD_STARLABS_BYTE_ADL
 
 config MAINBOARD_SMBIOS_PRODUCT_NAME
-	default "StarBook Horizon"
+	default "StarBook Horizon" if BOARD_STARLABS_ADL_HORIZON
+	default "Byte" if BOARD_STARLABS_BYTE_ADL || BOARD_STARLABS_BYTE_TWL
 
 config ME_BIN_PATH
 	string
@@ -101,10 +114,6 @@ config POWER_STATE_DEFAULT_ON_AFTER_FAILURE
 config SOC_INTEL_CSE_SEND_EOP_EARLY
 	default n
 
-config TPM_PIRQ
-	depends on MAINBOARD_HAS_TPM2
-	default 0x28
-
 config UART_FOR_CONSOLE
 	default 0
 
@@ -112,6 +121,42 @@ config USE_PM_ACPI_TIMER
 	default n
 
 config VARIANT_DIR
-	default "hz"
+	default "hz" if BOARD_STARLABS_ADL_HORIZON
+	default "y2" if BOARD_STARLABS_BYTE_ADL || BOARD_STARLABS_BYTE_TWL
 
-endif
+config CMOS_LAYOUT_FILE
+	default "src/mainboard/\$(MAINBOARDDIR)/variants/\$(CONFIG_VARIANT_DIR)/cmos.layout"
+
+if BOARD_STARLABS_ADL_HORIZON
+
+config CCD_PORT
+	int
+	default 4
+
+config EC_STARLABS_BATTERY_MODEL
+	default "U5266122PV-2S1P"
+
+config EC_STARLABS_BATTERY_TYPE
+	default "LION"
+
+config EC_STARLABS_BATTERY_OEM
+	default "Shenzhen Utility Energy Co., Ltd"
+
+config TPM_PIRQ
+	depends on MAINBOARD_HAS_TPM2
+	default 0x28
+
+endif # BOARD_STARLABS_ADL_HORIZON
+
+if BOARD_STARLABS_BYTE_ADL || BOARD_STARLABS_BYTE_TWL
+
+config PL4_WATTS
+	int
+	default 65
+
+config VBOOT
+	select VBOOT_VBNV_FLASH
+
+endif # BOARD_STARLABS_BYTE_ADL || BOARD_STARLABS_BYTE_TWL
+
+endif # BOARD_STARLABS_ADL_SERIES
diff --git a/src/mainboard/starlabs/adl/Kconfig.name b/src/mainboard/starlabs/adl/Kconfig.name
index e9af44560e..cfd423e8e5 100644
--- a/src/mainboard/starlabs/adl/Kconfig.name
+++ b/src/mainboard/starlabs/adl/Kconfig.name
@@ -1,4 +1,10 @@
-comment "Star Labs StarLite Series"
+comment "Star Labs ADL Series"
 
 config BOARD_STARLABS_ADL_HORIZON
 	bool "Star Labs StarBook Horizon (N305)"
+
+config BOARD_STARLABS_BYTE_ADL
+	bool "Star Labs Byte Mk II (N200)"
+
+config BOARD_STARLABS_BYTE_TWL
+	bool "Star Labs Byte Mk III (N355)"
diff --git a/src/mainboard/starlabs/adl/board_info.txt b/src/mainboard/starlabs/adl/board_info.txt
index 5416db044b..c3772dc3d5 100644
--- a/src/mainboard/starlabs/adl/board_info.txt
+++ b/src/mainboard/starlabs/adl/board_info.txt
@@ -1,5 +1,5 @@
 Vendor name: Star Labs
-Board name: StarBook Horizon
+Board name: ADL Series
 Category: laptop
 ROM protocol: SPI
 ROM socketed: n
diff --git a/src/mainboard/starlabs/adl/cfr.c b/src/mainboard/starlabs/adl/cfr.c
index 43d064f90f..39386132df 100644
--- a/src/mainboard/starlabs/adl/cfr.c
+++ b/src/mainboard/starlabs/adl/cfr.c
@@ -10,8 +10,10 @@
 static struct sm_obj_form battery_group = {
 	.ui_name = "Battery",
 	.obj_list = (const struct sm_object *[]) {
+#if CONFIG(SYSTEM_TYPE_LAPTOP)
 		&charging_speed,
 		&max_charge,
+#endif
 		&power_on_after_fail_bool,
 		NULL
 	},
@@ -25,6 +27,7 @@ static struct sm_obj_form debug_group = {
 	},
 };
 
+#if CONFIG(SYSTEM_TYPE_LAPTOP)
 static struct sm_obj_form leds_group = {
 	.ui_name = "LEDs",
 	.obj_list = (const struct sm_object *[]) {
@@ -59,6 +62,7 @@ static struct sm_obj_form display_group = {
 		NULL
 	},
 };
+#endif
 
 static struct sm_obj_form pcie_power_management_group = {
 	.ui_name = "PCIe Power Management",
@@ -75,7 +79,9 @@ static struct sm_obj_form performance_group = {
 	.obj_list = (const struct sm_object *[]) {
 		&fan_mode,
 		&gna,
+#if CONFIG(SYSTEM_TYPE_LAPTOP)
 		&memory_speed,
+#endif
 		&power_profile,
 		NULL
 	},
@@ -95,7 +101,9 @@ static struct sm_obj_form security_group = {
 static struct sm_obj_form suspend_lid_group = {
 	.ui_name = "Suspend & Lid",
 	.obj_list = (const struct sm_object *[]) {
+#if CONFIG(SYSTEM_TYPE_LAPTOP)
 		&lid_switch,
+#endif
 		&s0ix_enable,
 		NULL
 	},
@@ -120,12 +128,16 @@ static struct sm_obj_form wireless_group = {
 };
 
 static struct sm_obj_form *sm_root[] = {
+#if CONFIG(SYSTEM_TYPE_LAPTOP)
 	&audio_video_group,
+#endif
 	&battery_group,
 	&debug_group,
+#if CONFIG(SYSTEM_TYPE_LAPTOP)
 	&display_group,
 	&keyboard_group,
 	&leds_group,
+#endif
 	&pcie_power_management_group,
 	&performance_group,
 	&security_group,
diff --git a/src/mainboard/starlabs/adl/dsdt.asl b/src/mainboard/starlabs/adl/dsdt.asl
index b7783eae63..3a68c43aa3 100644
--- a/src/mainboard/starlabs/adl/dsdt.asl
+++ b/src/mainboard/starlabs/adl/dsdt.asl
@@ -21,12 +21,13 @@ DefinitionBlock(
 		#include <soc/intel/alderlake/acpi/southbridge.asl>
 		#include <soc/intel/alderlake/acpi/tcss.asl>
 
-		#include <drivers/intel/gma/acpi/default_brightness_levels.asl>
-
 		#include <soc/intel/common/block/acpi/acpi/gna.asl>
+#if CONFIG(SYSTEM_TYPE_LAPTOP)
+		#include <drivers/intel/gma/acpi/default_brightness_levels.asl>
 
 		/* PS/2 Keyboard */
 		#include <drivers/pc80/pc/ps2_controller.asl>
+#endif
 	}
 
 	#include <southbridge/intel/common/acpi/sleepstates.asl>
diff --git a/src/mainboard/starlabs/adl/cmos.layout b/src/mainboard/starlabs/adl/variants/hz/cmos.layout
similarity index 100%
rename from src/mainboard/starlabs/adl/cmos.layout
rename to src/mainboard/starlabs/adl/variants/hz/cmos.layout
diff --git a/src/mainboard/starlabs/byte_adl/variants/mk_ii/Makefile.mk b/src/mainboard/starlabs/adl/variants/y2/Makefile.mk
similarity index 79%
rename from src/mainboard/starlabs/byte_adl/variants/mk_ii/Makefile.mk
rename to src/mainboard/starlabs/adl/variants/y2/Makefile.mk
index 9abc069b38..05782dbcc6 100644
--- a/src/mainboard/starlabs/byte_adl/variants/mk_ii/Makefile.mk
+++ b/src/mainboard/starlabs/adl/variants/y2/Makefile.mk
@@ -2,6 +2,8 @@
 
 bootblock-y += gpio.c
 
+smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c
+
 romstage-y += romstage.c
 
 ramstage-y += devtree.c
diff --git a/src/mainboard/starlabs/byte_adl/variants/mk_ii/board.fmd b/src/mainboard/starlabs/adl/variants/y2/board.fmd
similarity index 100%
rename from src/mainboard/starlabs/byte_adl/variants/mk_ii/board.fmd
rename to src/mainboard/starlabs/adl/variants/y2/board.fmd
diff --git a/src/mainboard/starlabs/byte_adl/cmos.layout b/src/mainboard/starlabs/adl/variants/y2/cmos.layout
similarity index 100%
rename from src/mainboard/starlabs/byte_adl/cmos.layout
rename to src/mainboard/starlabs/adl/variants/y2/cmos.layout
diff --git a/src/mainboard/starlabs/byte_adl/variants/mk_ii/data.vbt b/src/mainboard/starlabs/adl/variants/y2/data.vbt
similarity index 100%
rename from src/mainboard/starlabs/byte_adl/variants/mk_ii/data.vbt
rename to src/mainboard/starlabs/adl/variants/y2/data.vbt
diff --git a/src/mainboard/starlabs/byte_adl/variants/mk_ii/devicetree.cb b/src/mainboard/starlabs/adl/variants/y2/devicetree.cb
similarity index 100%
rename from src/mainboard/starlabs/byte_adl/variants/mk_ii/devicetree.cb
rename to src/mainboard/starlabs/adl/variants/y2/devicetree.cb
diff --git a/src/mainboard/starlabs/byte_adl/variants/mk_ii/devtree.c b/src/mainboard/starlabs/adl/variants/y2/devtree.c
similarity index 100%
rename from src/mainboard/starlabs/byte_adl/variants/mk_ii/devtree.c
rename to src/mainboard/starlabs/adl/variants/y2/devtree.c
diff --git a/src/mainboard/starlabs/byte_adl/variants/mk_ii/gpio.c b/src/mainboard/starlabs/adl/variants/y2/gpio.c
similarity index 99%
rename from src/mainboard/starlabs/byte_adl/variants/mk_ii/gpio.c
rename to src/mainboard/starlabs/adl/variants/y2/gpio.c
index 0c0173cb40..12d9bcb472 100644
--- a/src/mainboard/starlabs/byte_adl/variants/mk_ii/gpio.c
+++ b/src/mainboard/starlabs/adl/variants/y2/gpio.c
@@ -86,7 +86,7 @@ const struct pad_config gpio_table[] = {
 	PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1),				/* Data */
 	PAD_CFG_GPO(GPP_E8, 1, DEEP),					/* DRAM Sleep */
 
-	/* Config Straps 									[ Low      / High     ] */
+	/* Config Straps [ Low / High ] */
 	PAD_CFG_GPO(GPP_B14, 0, PLTRST),				/* Top Swap		[ Disabled / Enabled  ] */
 	PAD_CFG_GPO(GPP_B18, 0, PLTRST),				/* Reboot Support	[ Enabled  / Disabled ] */
 	PAD_CFG_GPO(GPP_C2, 1, PLTRST),					/* TLS Confidentiality	[ Disabled / Enabled  ] */
diff --git a/src/mainboard/starlabs/byte_adl/variants/mk_ii/hda_verb.c b/src/mainboard/starlabs/adl/variants/y2/hda_verb.c
similarity index 100%
rename from src/mainboard/starlabs/byte_adl/variants/mk_ii/hda_verb.c
rename to src/mainboard/starlabs/adl/variants/y2/hda_verb.c
diff --git a/src/mainboard/starlabs/byte_adl/variants/mk_ii/ramstage.c b/src/mainboard/starlabs/adl/variants/y2/ramstage.c
similarity index 100%
rename from src/mainboard/starlabs/byte_adl/variants/mk_ii/ramstage.c
rename to src/mainboard/starlabs/adl/variants/y2/ramstage.c
diff --git a/src/mainboard/starlabs/byte_adl/variants/mk_ii/romstage.c b/src/mainboard/starlabs/adl/variants/y2/romstage.c
similarity index 100%
rename from src/mainboard/starlabs/byte_adl/variants/mk_ii/romstage.c
rename to src/mainboard/starlabs/adl/variants/y2/romstage.c
diff --git a/src/mainboard/starlabs/byte_adl/smihandler.c b/src/mainboard/starlabs/adl/variants/y2/smihandler.c
similarity index 100%
rename from src/mainboard/starlabs/byte_adl/smihandler.c
rename to src/mainboard/starlabs/adl/variants/y2/smihandler.c
diff --git a/src/mainboard/starlabs/byte_adl/variants/mk_ii/vboot.fmd b/src/mainboard/starlabs/adl/variants/y2/vboot.fmd
similarity index 100%
rename from src/mainboard/starlabs/byte_adl/variants/mk_ii/vboot.fmd
rename to src/mainboard/starlabs/adl/variants/y2/vboot.fmd
diff --git a/src/mainboard/starlabs/byte_adl/Kconfig b/src/mainboard/starlabs/byte_adl/Kconfig
deleted file mode 100644
index d8524a9ceb..0000000000
--- a/src/mainboard/starlabs/byte_adl/Kconfig
+++ /dev/null
@@ -1,116 +0,0 @@
-config BOARD_STARLABS_BYTE_SERIES
-	def_bool n
-	select AZALIA_USE_LEGACY_VERB_TABLE
-	select BOARD_ROMSIZE_KB_16384
-	select CRB_TPM
-	select CSE_DEFAULT_CFR_OPTION_STATE_DISABLED
-	select DRIVERS_EFI_VARIABLE_STORE
-	select DRIVERS_INTEL_PMC
-	select DRIVERS_OPTION_CFR_ENABLED
-	select DRIVERS_PCIE_GENERIC
-	select EC_STARLABS_FAN
-	select EC_STARLABS_MERLIN
-	select HAVE_ACPI_RESUME
-	select HAVE_ACPI_TABLES
-	select HAVE_INTEL_PTT
-	select HAVE_OPTION_TABLE
-	select INTEL_GMA_HAVE_VBT
-	select INTEL_LPSS_UART_FOR_CONSOLE
-	select NO_UART_ON_SUPERIO
-	select PMC_IPC_ACPI_INTERFACE
-	select SOC_INTEL_COMMON_BLOCK_HDA_VERB
-	select SOC_INTEL_COMMON_BLOCK_TCSS
-	select SOC_INTEL_CRASHLOG
-	select SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES
-	select SPD_READ_BY_WORD
-	select SPI_FLASH_WINBOND
-	select SYSTEM_TYPE_MINIPC
-	select TPM2
-	select VALIDATE_INTEL_DESCRIPTOR
-
-config BOARD_STARLABS_BYTE_ADL
-	select BOARD_STARLABS_BYTE_SERIES
-	select SOC_INTEL_ALDERLAKE
-	select SOC_INTEL_ALDERLAKE_PCH_N
-
-config BOARD_STARLABS_BYTE_TWL
-	select BOARD_STARLABS_BYTE_SERIES
-	select SOC_INTEL_ALDERLAKE
-	select SOC_INTEL_TWINLAKE
-
-if BOARD_STARLABS_BYTE_SERIES
-
-config CONSOLE_SERIAL
-	default n if !EDK2_DEBUG
-
-config D3COLD_SUPPORT
-	default n
-
-config DEVICETREE
-	default "variants/\$(CONFIG_VARIANT_DIR)/devicetree.cb"
-
-config DIMM_SPD_SIZE
-	default 512
-
-config EC_STARLABS_ITE_BIN_PATH
-	string
-	default "3rdparty/blobs/mainboard/\$(MAINBOARDDIR)/\$(CONFIG_VARIANT_DIR)/ec.bin"
-
-config FMDFILE
-	default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/variants/\$(CONFIG_VARIANT_DIR)/vboot.fmd" if VBOOT
-	default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/variants/\$(CONFIG_VARIANT_DIR)/board.fmd"
-
-config IFD_BIN_PATH
-	string
-	default "3rdparty/blobs/mainboard/\$(MAINBOARDDIR)/\$(CONFIG_VARIANT_DIR)/flashdescriptor.bin"
-
-config MAINBOARD_DIR
-	default "starlabs/byte_adl"
-
-config MAINBOARD_FAMILY
-	string
-	default "Y3" if BOARD_STARLABS_BYTE_TWL
-	default "Y2"
-
-config MAINBOARD_PART_NUMBER
-	default "Byte Mk III" if BOARD_STARLABS_BYTE_TWL
-	default "Byte Mk II"
-
-config MAINBOARD_SMBIOS_PRODUCT_NAME
-	default "Byte"
-
-config ME_BIN_PATH
-	string
-	default "3rdparty/blobs/mainboard/\$(MAINBOARDDIR)/\$(CONFIG_VARIANT_DIR)/intel_me.bin"
-
-config PL4_WATTS
-	int
-	default 65
-
-config POWER_STATE_DEFAULT_ON_AFTER_FAILURE
-	default n
-
-config EDK2_BOOTSPLASH_FILE
-	string
-	default "3rdparty/blobs/mainboard/starlabs/Logo.bmp"
-
-config SOC_INTEL_CSE_SEND_EOP_EARLY
-	default n
-
-config TJ_MAX
-	int
-	default 105
-
-config UART_FOR_CONSOLE
-	default 0
-
-config USE_PM_ACPI_TIMER
-	default n
-
-config VBOOT
-	select VBOOT_VBNV_FLASH
-
-config VARIANT_DIR
-	default "mk_ii"
-
-endif
diff --git a/src/mainboard/starlabs/byte_adl/Kconfig.name b/src/mainboard/starlabs/byte_adl/Kconfig.name
deleted file mode 100644
index bb393c0daa..0000000000
--- a/src/mainboard/starlabs/byte_adl/Kconfig.name
+++ /dev/null
@@ -1,7 +0,0 @@
-comment "Star Labs Byte Series"
-
-config BOARD_STARLABS_BYTE_ADL
-	bool "Star Labs Byte Mk II (N200)"
-
-config BOARD_STARLABS_BYTE_TWL
-	bool "Star Labs Byte Mk III (N355)"
diff --git a/src/mainboard/starlabs/byte_adl/Makefile.mk b/src/mainboard/starlabs/byte_adl/Makefile.mk
deleted file mode 100644
index 678662b55d..0000000000
--- a/src/mainboard/starlabs/byte_adl/Makefile.mk
+++ /dev/null
@@ -1,13 +0,0 @@
-## SPDX-License-Identifier: GPL-2.0-only
-
-CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/include
-subdirs-y += variants/$(VARIANT_DIR)
-
-bootblock-y += bootblock.c
-
-verstage-$(CONFIG_VBOOT) += vboot.c
-
-romstage-$(CONFIG_VBOOT) += vboot.c
-
-ramstage-$(CONFIG_DRIVERS_OPTION_CFR) += cfr.c
-ramstage-y += mainboard.c
diff --git a/src/mainboard/starlabs/byte_adl/acpi/ec.asl b/src/mainboard/starlabs/byte_adl/acpi/ec.asl
deleted file mode 100644
index 853b0877b3..0000000000
--- a/src/mainboard/starlabs/byte_adl/acpi/ec.asl
+++ /dev/null
@@ -1 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
diff --git a/src/mainboard/starlabs/byte_adl/acpi/mainboard.asl b/src/mainboard/starlabs/byte_adl/acpi/mainboard.asl
deleted file mode 100644
index 34b90af325..0000000000
--- a/src/mainboard/starlabs/byte_adl/acpi/mainboard.asl
+++ /dev/null
@@ -1,5 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-Scope (\_SB) {
-	#include "sleep.asl"
-}
diff --git a/src/mainboard/starlabs/byte_adl/acpi/sleep.asl b/src/mainboard/starlabs/byte_adl/acpi/sleep.asl
deleted file mode 100644
index 7ed74e3514..0000000000
--- a/src/mainboard/starlabs/byte_adl/acpi/sleep.asl
+++ /dev/null
@@ -1,11 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-Method (MPTS, 1, NotSerialized)
-{
-	RPTS (Arg0)
-}
-
-Method (MWAK, 1, NotSerialized)
-{
-	RWAK (Arg0)
-}
diff --git a/src/mainboard/starlabs/byte_adl/acpi/superio.asl b/src/mainboard/starlabs/byte_adl/acpi/superio.asl
deleted file mode 100644
index 853b0877b3..0000000000
--- a/src/mainboard/starlabs/byte_adl/acpi/superio.asl
+++ /dev/null
@@ -1 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
diff --git a/src/mainboard/starlabs/byte_adl/board_info.txt b/src/mainboard/starlabs/byte_adl/board_info.txt
deleted file mode 100644
index 86a76f6126..0000000000
--- a/src/mainboard/starlabs/byte_adl/board_info.txt
+++ /dev/null
@@ -1,6 +0,0 @@
-Vendor name: Star Labs
-Board name: Byte
-Category: desktop
-ROM protocol: SPI
-ROM socketed: n
-Flashrom support: y
diff --git a/src/mainboard/starlabs/byte_adl/bootblock.c b/src/mainboard/starlabs/byte_adl/bootblock.c
deleted file mode 100644
index ca48bb1ab2..0000000000
--- a/src/mainboard/starlabs/byte_adl/bootblock.c
+++ /dev/null
@@ -1,14 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <bootblock_common.h>
-#include <soc/gpio.h>
-#include <variants.h>
-
-void bootblock_mainboard_init(void)
-{
-	const struct pad_config *pads;
-	size_t num;
-
-	pads = variant_early_gpio_table(&num);
-	gpio_configure_pads(pads, num);
-}
diff --git a/src/mainboard/starlabs/byte_adl/cfr.c b/src/mainboard/starlabs/byte_adl/cfr.c
deleted file mode 100644
index bf658a4249..0000000000
--- a/src/mainboard/starlabs/byte_adl/cfr.c
+++ /dev/null
@@ -1,100 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <boot/coreboot_tables.h>
-#include <console/cfr.h>
-#include <drivers/option/cfr_frontend.h>
-#include <ec/starlabs/merlin/cfr.h>
-#include <intelblocks/cfr.h>
-#include <variants.h>
-#include <common/cfr.h>
-
-static struct sm_obj_form battery_group = {
-	.ui_name = "Battery",
-	.obj_list = (const struct sm_object *[]) {
-		&power_on_after_fail_bool,
-		NULL
-	},
-};
-
-static struct sm_obj_form debug_group = {
-	.ui_name = "Debug",
-	.obj_list = (const struct sm_object *[]) {
-		&debug_level,
-		NULL
-	},
-};
-
-static struct sm_obj_form pcie_power_management_group = {
-	.ui_name = "PCIe Power Management",
-	.obj_list = (const struct sm_object *[]) {
-		&pciexp_aspm,
-		&pciexp_clk_pm,
-		&pciexp_l1ss,
-		NULL
-	},
-};
-
-static struct sm_obj_form performance_group = {
-	.ui_name = "Performance",
-	.obj_list = (const struct sm_object *[]) {
-		&fan_mode,
-		&gna,
-		&power_profile,
-		NULL
-	},
-};
-
-static struct sm_obj_form security_group = {
-	.ui_name = "Security",
-	.obj_list = (const struct sm_object *[]) {
-		&bios_lock,
-		&intel_tme,
-		&me_state,
-		&me_state_counter,
-		NULL
-	},
-};
-
-static struct sm_obj_form suspend_lid_group = {
-	.ui_name = "Suspend & Lid",
-	.obj_list = (const struct sm_object *[]) {
-		&s0ix_enable,
-		NULL
-	},
-};
-
-static struct sm_obj_form virtualization_group = {
-	.ui_name = "Virtualization",
-	.obj_list = (const struct sm_object *[]) {
-		&vtd,
-		NULL
-	},
-};
-
-static struct sm_obj_form wireless_group = {
-	.ui_name = "Wireless",
-	.obj_list = (const struct sm_object *[]) {
-		&bluetooth,
-		&bluetooth_rtd3,
-		&wifi,
-		NULL
-	},
-};
-
-static struct sm_obj_form *sm_root[] = {
-	&battery_group,
-	&debug_group,
-	&pcie_power_management_group,
-	&performance_group,
-	&security_group,
-	&suspend_lid_group,
-	&virtualization_group,
-	&wireless_group,
-	NULL
-};
-
-void mb_cfr_setup_menu(struct lb_cfr *cfr_root)
-{
-	starlabs_cfr_register_overrides();
-	cfr_write_setup_menu(cfr_root, sm_root);
-}
diff --git a/src/mainboard/starlabs/byte_adl/dsdt.asl b/src/mainboard/starlabs/byte_adl/dsdt.asl
deleted file mode 100644
index c0936a74ba..0000000000
--- a/src/mainboard/starlabs/byte_adl/dsdt.asl
+++ /dev/null
@@ -1,42 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <acpi/acpi.h>
-DefinitionBlock(
-	"dsdt.aml",
-	"DSDT",
-	ACPI_DSDT_REV_2,
-	OEM_ID,
-	ACPI_TABLE_CREATOR,
-	0x20220930
-)
-{
-	#include <acpi/dsdt_top.asl>
-	#include <soc/intel/common/block/acpi/acpi/platform.asl>
-	#include <soc/intel/common/block/acpi/acpi/globalnvs.asl>
-	#include <cpu/intel/common/acpi/cpu.asl>
-
-	Device (\_SB.PCI0)
-	{
-		#include <soc/intel/common/block/acpi/acpi/northbridge.asl>
-		#include <soc/intel/alderlake/acpi/southbridge.asl>
-		#include <soc/intel/alderlake/acpi/tcss.asl>
-
-		#include <soc/intel/common/block/acpi/acpi/gna.asl>
-	}
-
-	#include <southbridge/intel/common/acpi/sleepstates.asl>
-
-	/* Star Labs EC */
-	#include <ec/starlabs/merlin/acpi/ec.asl>
-
-	Scope (\_SB)
-	{
-		/* HID Driver */
-		#include <ec/starlabs/merlin/acpi/hid.asl>
-
-		/* Suspend Methods */
-		#include <ec/starlabs/merlin/acpi/suspend.asl>
-	}
-
-	#include "acpi/mainboard.asl"
-}
diff --git a/src/mainboard/starlabs/byte_adl/include/variants.h b/src/mainboard/starlabs/byte_adl/include/variants.h
deleted file mode 100644
index c95d15bd72..0000000000
--- a/src/mainboard/starlabs/byte_adl/include/variants.h
+++ /dev/null
@@ -1,17 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#ifndef _BASEBOARD_VARIANTS_H_
-#define _BASEBOARD_VARIANTS_H_
-
-#include <soc/gpio.h>
-
-/*
- * The next set of functions return the gpio table and fill in the number of
- * entries for each table.
- */
-const struct pad_config *variant_gpio_table(size_t *num);
-const struct pad_config *variant_early_gpio_table(size_t *num);
-
-void devtree_update(void);
-
-#endif /* _BASEBOARD_VARIANTS_H_ */
diff --git a/src/mainboard/starlabs/byte_adl/mainboard.c b/src/mainboard/starlabs/byte_adl/mainboard.c
deleted file mode 100644
index cd46529c0f..0000000000
--- a/src/mainboard/starlabs/byte_adl/mainboard.c
+++ /dev/null
@@ -1,18 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <device/device.h>
-#include <soc/ramstage.h>
-#include <variants.h>
-
-static void init_mainboard(void *chip_info)
-{
-	const struct pad_config *pads;
-	size_t num;
-
-	pads = variant_gpio_table(&num);
-	gpio_configure_pads(pads, num);
-}
-
-struct chip_operations mainboard_ops = {
-	.init = init_mainboard,
-};
diff --git a/src/mainboard/starlabs/byte_adl/vboot.c b/src/mainboard/starlabs/byte_adl/vboot.c
deleted file mode 100644
index 8511825004..0000000000
--- a/src/mainboard/starlabs/byte_adl/vboot.c
+++ /dev/null
@@ -1,8 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-or-later */
-
-#include <bootmode.h>
-
-int get_recovery_mode_switch(void)
-{
-	return 0;
-}

From 7f02993393573914e6139dd278f61b9239ba345b Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Sun, 15 Feb 2026 21:20:09 +0000
Subject: [PATCH 3539/3886] mainboard/starlabs: move starlite under adl/

Move StarLite Mk V (Lite ADL) into the ADL grouping under
src/mainboard/starlabs/adl/.

Like StarBook Horizon, keep common code in the ADL directory and place
model-specific data under src/mainboard/starlabs/adl/variants/ using the
SKU-style variant directory (i5).

Update MAINBOARD_DIR and related paths so binary blobs, SPD data and
CMOS layout continue to resolve correctly, and update documentation to
reflect the new blobs path.

Note that BUILD_TIMELESS ROM hashes change since MAINBOARD_DIR is
embedded in the CBFS config file.

BUG=None
TEST=BUILD_TIMELESS=1 build STARLABS_LITE_ADL
Change-Id: Ib367bc65ad63e848d9e20e7d55f542f135b3c1d5
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91256
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 Documentation/mainboard/starlabs/lite_adl.md  |  11 +-
 src/mainboard/starlabs/adl/Kconfig            |  46 ++++-
 src/mainboard/starlabs/adl/Kconfig.name       |   3 +
 src/mainboard/starlabs/adl/acpi/mainboard.asl |  10 +
 src/mainboard/starlabs/adl/cfr.c              | 190 +++++++++++-------
 src/mainboard/starlabs/adl/dsdt.asl           |   2 +-
 src/mainboard/starlabs/adl/mainboard.c        |  23 +++
 src/mainboard/starlabs/adl/spd/Makefile.mk    |   6 +
 .../spd/mt62f2g64d8-5500.spd.hex              |   0
 .../spd/mt62f2g64d8-6400.spd.hex              |   0
 .../spd/mt62f2g64d8-7500.spd.hex              |   0
 .../mk_v => adl/variants/i5}/Makefile.mk      |   0
 .../mk_v => adl/variants/i5}/board.fmd        |   0
 .../variants/i5}/cmos.layout                  |   0
 .../mk_v => adl/variants/i5}/data.vbt         | Bin
 .../variants/i5}/data_native_res.vbt          | Bin
 .../mk_v => adl/variants/i5}/devicetree.cb    |   0
 .../mk_v => adl/variants/i5}/devtree.c        |   0
 .../variants/mk_v => adl/variants/i5}/gpio.c  | 117 +++++------
 .../starlabs/adl/variants/i5/hda_verb.c       |  77 +++++++
 .../mk_v => adl/variants/i5}/ramstage.c       |   0
 .../mk_v => adl/variants/i5}/romstage.c       |   0
 .../mk_v => adl/variants/i5}/vboot.fmd        |   0
 src/mainboard/starlabs/starlite_adl/Kconfig   | 123 ------------
 .../starlabs/starlite_adl/Kconfig.name        |   4 -
 .../starlabs/starlite_adl/Makefile.mk         |  14 --
 .../starlabs/starlite_adl/acpi/ec.asl         |   1 -
 .../starlabs/starlite_adl/acpi/mainboard.asl  |  13 --
 .../starlabs/starlite_adl/acpi/sleep.asl      |  11 -
 .../starlabs/starlite_adl/acpi/superio.asl    |   1 -
 .../starlabs/starlite_adl/board_info.txt      |   6 -
 .../starlabs/starlite_adl/bootblock.c         |  14 --
 src/mainboard/starlabs/starlite_adl/cfr.c     | 169 ----------------
 src/mainboard/starlabs/starlite_adl/dsdt.asl  |  47 -----
 .../starlabs/starlite_adl/include/variants.h  |  17 --
 .../starlabs/starlite_adl/mainboard.c         |  32 ---
 .../starlabs/starlite_adl/spd/Makefile.mk     |   5 -
 .../starlite_adl/variants/mk_v/hda_verb.c     |  98 ---------
 src/mainboard/starlabs/starlite_adl/vboot.c   |   8 -
 39 files changed, 337 insertions(+), 711 deletions(-)
 rename src/mainboard/starlabs/{starlite_adl => adl}/spd/mt62f2g64d8-5500.spd.hex (100%)
 rename src/mainboard/starlabs/{starlite_adl => adl}/spd/mt62f2g64d8-6400.spd.hex (100%)
 rename src/mainboard/starlabs/{starlite_adl => adl}/spd/mt62f2g64d8-7500.spd.hex (100%)
 rename src/mainboard/starlabs/{starlite_adl/variants/mk_v => adl/variants/i5}/Makefile.mk (100%)
 rename src/mainboard/starlabs/{starlite_adl/variants/mk_v => adl/variants/i5}/board.fmd (100%)
 rename src/mainboard/starlabs/{starlite_adl => adl/variants/i5}/cmos.layout (100%)
 rename src/mainboard/starlabs/{starlite_adl/variants/mk_v => adl/variants/i5}/data.vbt (100%)
 rename src/mainboard/starlabs/{starlite_adl/variants/mk_v => adl/variants/i5}/data_native_res.vbt (100%)
 rename src/mainboard/starlabs/{starlite_adl/variants/mk_v => adl/variants/i5}/devicetree.cb (100%)
 rename src/mainboard/starlabs/{starlite_adl/variants/mk_v => adl/variants/i5}/devtree.c (100%)
 rename src/mainboard/starlabs/{starlite_adl/variants/mk_v => adl/variants/i5}/gpio.c (56%)
 create mode 100644 src/mainboard/starlabs/adl/variants/i5/hda_verb.c
 rename src/mainboard/starlabs/{starlite_adl/variants/mk_v => adl/variants/i5}/ramstage.c (100%)
 rename src/mainboard/starlabs/{starlite_adl/variants/mk_v => adl/variants/i5}/romstage.c (100%)
 rename src/mainboard/starlabs/{starlite_adl/variants/mk_v => adl/variants/i5}/vboot.fmd (100%)
 delete mode 100644 src/mainboard/starlabs/starlite_adl/Kconfig
 delete mode 100644 src/mainboard/starlabs/starlite_adl/Kconfig.name
 delete mode 100644 src/mainboard/starlabs/starlite_adl/Makefile.mk
 delete mode 100644 src/mainboard/starlabs/starlite_adl/acpi/ec.asl
 delete mode 100644 src/mainboard/starlabs/starlite_adl/acpi/mainboard.asl
 delete mode 100644 src/mainboard/starlabs/starlite_adl/acpi/sleep.asl
 delete mode 100644 src/mainboard/starlabs/starlite_adl/acpi/superio.asl
 delete mode 100644 src/mainboard/starlabs/starlite_adl/board_info.txt
 delete mode 100644 src/mainboard/starlabs/starlite_adl/bootblock.c
 delete mode 100644 src/mainboard/starlabs/starlite_adl/cfr.c
 delete mode 100644 src/mainboard/starlabs/starlite_adl/dsdt.asl
 delete mode 100644 src/mainboard/starlabs/starlite_adl/include/variants.h
 delete mode 100644 src/mainboard/starlabs/starlite_adl/mainboard.c
 delete mode 100644 src/mainboard/starlabs/starlite_adl/spd/Makefile.mk
 delete mode 100644 src/mainboard/starlabs/starlite_adl/variants/mk_v/hda_verb.c
 delete mode 100644 src/mainboard/starlabs/starlite_adl/vboot.c

diff --git a/Documentation/mainboard/starlabs/lite_adl.md b/Documentation/mainboard/starlabs/lite_adl.md
index b6e7cb37e7..f914652b5a 100644
--- a/Documentation/mainboard/starlabs/lite_adl.md
+++ b/Documentation/mainboard/starlabs/lite_adl.md
@@ -1,4 +1,4 @@
-# StarBook Mk V
+# StarLite Mk V
 
 ## Specs
 
@@ -33,7 +33,8 @@
 
 ## Building coreboot
 
-Please follow the [Star Labs build instructions](common/building.md) to build coreboot, using `config.starlabs_starbook_adl` as config file.
+Please follow the [Star Labs build instructions](common/building.md) to build
+coreboot, using `config.starlabs_lite_adl` as config file.
 
 ### Preliminaries
 
@@ -45,6 +46,10 @@ Prior to building coreboot the following files are required:
 The files listed below are optional:
 - Splash screen image in Windows 3.1 BMP format (Logo.bmp)
 
+coreboot expects these binaries under
+`3rdparty/blobs/mainboard/starlabs/adl/<variant>/`, where `<variant>`
+matches `CONFIG_VARIANT_DIR` (default: `i5`).
+
 These files exist in the correct location in the StarLabsLtd/blobs repo on GitHub which is used in place of the standard 3rdparty/blobs repo.
 
 ### Build
@@ -53,7 +58,7 @@ The following commands will build a working image:
 
 ```bash
 make distclean
-make defconfig KBUILD_DEFCONFIG=configs/config.starlabs_byte_adl
+make defconfig KBUILD_DEFCONFIG=configs/config.starlabs_lite_adl
 make
 ```
 
diff --git a/src/mainboard/starlabs/adl/Kconfig b/src/mainboard/starlabs/adl/Kconfig
index 8b5c5d8b64..569274f9e6 100644
--- a/src/mainboard/starlabs/adl/Kconfig
+++ b/src/mainboard/starlabs/adl/Kconfig
@@ -36,6 +36,17 @@ config BOARD_STARLABS_ADL_HORIZON
 	select SYSTEM_TYPE_LAPTOP
 	select TPM_MEASURED_BOOT
 
+config BOARD_STARLABS_LITE_ADL
+	select BOARD_STARLABS_ADL_SERIES
+	select CRB_TPM
+	select DRIVERS_GFX_GENERIC
+	select DRIVERS_I2C_HID
+	select HAVE_HDA_DMIC
+	select HAVE_INTEL_PTT
+	select HAVE_SPD_IN_CBFS
+	select SOC_INTEL_ALDERLAKE_PCH_N
+	select SYSTEM_TYPE_DETACHABLE
+
 config BOARD_STARLABS_BYTE_ADL
 	select BOARD_STARLABS_ADL_SERIES
 	select CRB_TPM
@@ -92,16 +103,19 @@ config MAINBOARD_DIR
 config MAINBOARD_FAMILY
 	string
 	default "HZ" if BOARD_STARLABS_ADL_HORIZON
+	default "I5" if BOARD_STARLABS_LITE_ADL
 	default "Y3" if BOARD_STARLABS_BYTE_TWL
 	default "Y2" if BOARD_STARLABS_BYTE_ADL
 
 config MAINBOARD_PART_NUMBER
 	default "StarBook Horizon" if BOARD_STARLABS_ADL_HORIZON
+	default "StarLite Mk V" if BOARD_STARLABS_LITE_ADL
 	default "Byte Mk III" if BOARD_STARLABS_BYTE_TWL
 	default "Byte Mk II" if BOARD_STARLABS_BYTE_ADL
 
 config MAINBOARD_SMBIOS_PRODUCT_NAME
 	default "StarBook Horizon" if BOARD_STARLABS_ADL_HORIZON
+	default "StarLite" if BOARD_STARLABS_LITE_ADL
 	default "Byte" if BOARD_STARLABS_BYTE_ADL || BOARD_STARLABS_BYTE_TWL
 
 config ME_BIN_PATH
@@ -122,41 +136,53 @@ config USE_PM_ACPI_TIMER
 
 config VARIANT_DIR
 	default "hz" if BOARD_STARLABS_ADL_HORIZON
+	default "i5" if BOARD_STARLABS_LITE_ADL
 	default "y2" if BOARD_STARLABS_BYTE_ADL || BOARD_STARLABS_BYTE_TWL
 
 config CMOS_LAYOUT_FILE
 	default "src/mainboard/\$(MAINBOARDDIR)/variants/\$(CONFIG_VARIANT_DIR)/cmos.layout"
 
-if BOARD_STARLABS_ADL_HORIZON
+if BOARD_STARLABS_ADL_HORIZON || BOARD_STARLABS_LITE_ADL
 
 config CCD_PORT
 	int
-	default 4
+	default 4 if BOARD_STARLABS_ADL_HORIZON
+	default 5 if BOARD_STARLABS_LITE_ADL
 
 config EC_STARLABS_BATTERY_MODEL
-	default "U5266122PV-2S1P"
+	default "U5266122PV-2S1P" if BOARD_STARLABS_ADL_HORIZON
+	default "AEC3756153-2S1P-N" if BOARD_STARLABS_LITE_ADL
 
 config EC_STARLABS_BATTERY_TYPE
 	default "LION"
 
 config EC_STARLABS_BATTERY_OEM
-	default "Shenzhen Utility Energy Co., Ltd"
+	default "Shenzhen Utility Energy Co., Ltd" if BOARD_STARLABS_ADL_HORIZON
+	default "Apower Electronics" if BOARD_STARLABS_LITE_ADL
+
+if MAINBOARD_HAS_TPM2
 
 config TPM_PIRQ
-	depends on MAINBOARD_HAS_TPM2
-	default 0x28
+	default 0x28 if BOARD_STARLABS_ADL_HORIZON
 
-endif # BOARD_STARLABS_ADL_HORIZON
+endif # MAINBOARD_HAS_TPM2
 
-if BOARD_STARLABS_BYTE_ADL || BOARD_STARLABS_BYTE_TWL
+endif # BOARD_STARLABS_ADL_HORIZON || BOARD_STARLABS_LITE_ADL
+
+if BOARD_STARLABS_BYTE_ADL || BOARD_STARLABS_BYTE_TWL || BOARD_STARLABS_LITE_ADL
 
 config PL4_WATTS
 	int
-	default 65
+	default 65 if BOARD_STARLABS_BYTE_ADL || BOARD_STARLABS_BYTE_TWL
+	default 37 if BOARD_STARLABS_LITE_ADL
+
+config TJ_MAX
+	int
+	default 105 if BOARD_STARLABS_LITE_ADL
 
 config VBOOT
 	select VBOOT_VBNV_FLASH
 
-endif # BOARD_STARLABS_BYTE_ADL || BOARD_STARLABS_BYTE_TWL
+endif # BOARD_STARLABS_BYTE_ADL || BOARD_STARLABS_BYTE_TWL || BOARD_STARLABS_LITE_ADL
 
 endif # BOARD_STARLABS_ADL_SERIES
diff --git a/src/mainboard/starlabs/adl/Kconfig.name b/src/mainboard/starlabs/adl/Kconfig.name
index cfd423e8e5..373ed84cea 100644
--- a/src/mainboard/starlabs/adl/Kconfig.name
+++ b/src/mainboard/starlabs/adl/Kconfig.name
@@ -8,3 +8,6 @@ config BOARD_STARLABS_BYTE_ADL
 
 config BOARD_STARLABS_BYTE_TWL
 	bool "Star Labs Byte Mk III (N355)"
+
+config BOARD_STARLABS_LITE_ADL
+	bool "Star Labs Lite Mk V (N200/N350)"
diff --git a/src/mainboard/starlabs/adl/acpi/mainboard.asl b/src/mainboard/starlabs/adl/acpi/mainboard.asl
index 34b90af325..702d37f353 100644
--- a/src/mainboard/starlabs/adl/acpi/mainboard.asl
+++ b/src/mainboard/starlabs/adl/acpi/mainboard.asl
@@ -3,3 +3,13 @@
 Scope (\_SB) {
 	#include "sleep.asl"
 }
+
+#if CONFIG(BOARD_STARLABS_LITE_ADL)
+Scope (_GPE)
+{
+	Method (_E0F, 0, NotSerialized)
+	{
+		\_SB.PCI0.LPCB.EC.VBTN.UPDK()
+	}
+}
+#endif
diff --git a/src/mainboard/starlabs/adl/cfr.c b/src/mainboard/starlabs/adl/cfr.c
index 39386132df..74106c295c 100644
--- a/src/mainboard/starlabs/adl/cfr.c
+++ b/src/mainboard/starlabs/adl/cfr.c
@@ -5,137 +5,176 @@
 #include <drivers/option/cfr_frontend.h>
 #include <ec/starlabs/merlin/cfr.h>
 #include <intelblocks/cfr.h>
+#if CONFIG(BOARD_STARLABS_LITE_ADL)
+#include <device/i2c_bus.h>
+#include <device/i2c_simple.h>
+#include <option.h>
+#include <static.h>
+#include <variants.h>
+#endif
 #include <common/cfr.h>
 
+#if CONFIG(BOARD_STARLABS_LITE_ADL)
+void cfr_card_reader_update(struct sm_object *new_obj)
+{
+	struct device *mxc_accel = DEV_PTR(mxc6655);
+
+	if (!i2c_dev_detect(i2c_busdev(mxc_accel), mxc_accel->path.i2c.device))
+		new_obj->sm_bool.flags = CFR_OPTFLAG_SUPPRESS;
+}
+
+void cfr_touchscreen_update(struct sm_object *new_obj)
+{
+	if (get_uint_option("accelerometer", 1) == 0)
+		new_obj->sm_bool.flags = CFR_OPTFLAG_SUPPRESS;
+}
+#endif
+
+#if CONFIG(SYSTEM_TYPE_LAPTOP) || CONFIG(SYSTEM_TYPE_DETACHABLE)
+static struct sm_obj_form audio_video_group = {
+	.ui_name = "Audio/Video",
+	.obj_list = (const struct sm_object *[]){
+		&microphone,
+		&webcam,
+		NULL,
+	},
+};
+#endif
+
 static struct sm_obj_form battery_group = {
 	.ui_name = "Battery",
-	.obj_list = (const struct sm_object *[]) {
-#if CONFIG(SYSTEM_TYPE_LAPTOP)
-		&charging_speed,
-		&max_charge,
+	.obj_list =
+		(const struct sm_object *[]){
+#if CONFIG(EC_STARLABS_CHARGING_SPEED)
+					     &charging_speed,
 #endif
-		&power_on_after_fail_bool,
-		NULL
-	},
+#if CONFIG(SYSTEM_TYPE_LAPTOP) || CONFIG(SYSTEM_TYPE_DETACHABLE)
+					     &max_charge,
+#endif
+					     &power_on_after_fail_bool, NULL},
 };
 
 static struct sm_obj_form debug_group = {
 	.ui_name = "Debug",
-	.obj_list = (const struct sm_object *[]) {
-		&debug_level,
-		NULL
-	},
+	.obj_list = (const struct sm_object *[]){&debug_level, NULL},
 };
 
-#if CONFIG(SYSTEM_TYPE_LAPTOP)
+#if CONFIG(EC_STARLABS_POWER_LED) || CONFIG(EC_STARLABS_CHARGE_LED)
 static struct sm_obj_form leds_group = {
 	.ui_name = "LEDs",
-	.obj_list = (const struct sm_object *[]) {
-		&charge_led,
-		&power_led,
-		NULL
-	},
+	.obj_list =
+		(const struct sm_object *[]){
+#if CONFIG(EC_STARLABS_CHARGE_LED)
+					     &charge_led,
+#endif
+#if CONFIG(EC_STARLABS_POWER_LED)
+					     &power_led,
+#endif
+					     NULL, },
 };
+#endif
 
+#if CONFIG(SYSTEM_TYPE_LAPTOP)
 static struct sm_obj_form keyboard_group = {
 	.ui_name = "Keyboard",
-	.obj_list = (const struct sm_object *[]) {
-		&fn_ctrl_swap,
-		&kbl_timeout,
-		NULL
-	},
-};
-
-static struct sm_obj_form audio_video_group = {
-	.ui_name = "Audio/Video",
-	.obj_list = (const struct sm_object *[]) {
-		&microphone,
-		&webcam,
-		NULL
-	},
+	.obj_list = (const struct sm_object *[]){&fn_ctrl_swap, &kbl_timeout, NULL},
 };
+#endif
 
+#if CONFIG(SYSTEM_TYPE_LAPTOP) || CONFIG(SYSTEM_TYPE_DETACHABLE)
 static struct sm_obj_form display_group = {
 	.ui_name = "Display",
-	.obj_list = (const struct sm_object *[]) {
-		&display_native_res,
-		NULL
-	},
+	.obj_list =
+		(const struct sm_object *[]){
+#if CONFIG(BOARD_STARLABS_LITE_ADL)
+					     &accelerometer,
+#endif
+					     &display_native_res,
+#if CONFIG(BOARD_STARLABS_LITE_ADL)
+					     &touchscreen,
+#endif
+					     NULL, },
+};
+#endif
+
+#if CONFIG(BOARD_STARLABS_LITE_ADL)
+static struct sm_obj_form io_expansion_group = {
+	.ui_name = "I/O / Expansion",
+	.obj_list =
+		(const struct sm_object *[]){
+					     &card_reader,
+					     NULL, },
 };
 #endif
 
 static struct sm_obj_form pcie_power_management_group = {
 	.ui_name = "PCIe Power Management",
-	.obj_list = (const struct sm_object *[]) {
-		&pciexp_aspm,
-		&pciexp_clk_pm,
-		&pciexp_l1ss,
-		NULL
-	},
+	.obj_list =
+		(const struct sm_object *[]){
+#if CONFIG(SOC_INTEL_COMMON_BLOCK_ASPM)
+					     &pciexp_aspm,
+					     &pciexp_clk_pm,
+					     &pciexp_l1ss,
+#endif
+					     NULL, },
 };
 
 static struct sm_obj_form performance_group = {
 	.ui_name = "Performance",
-	.obj_list = (const struct sm_object *[]) {
-		&fan_mode,
-		&gna,
-#if CONFIG(SYSTEM_TYPE_LAPTOP)
-		&memory_speed,
+	.obj_list =
+		(const struct sm_object *[]){
+#if CONFIG(EC_STARLABS_FAN)
+					     &fan_mode,
 #endif
-		&power_profile,
-		NULL
-	},
+					     &gna,
+#if CONFIG(SYSTEM_TYPE_LAPTOP) || CONFIG(SYSTEM_TYPE_DETACHABLE)
+					     &memory_speed,
+#endif
+					     &power_profile, NULL},
 };
 
 static struct sm_obj_form security_group = {
 	.ui_name = "Security",
-	.obj_list = (const struct sm_object *[]) {
-		&bios_lock,
-		&intel_tme,
-		&me_state,
-		&me_state_counter,
-		NULL
-	},
+	.obj_list = (const struct sm_object *[]){&bios_lock, &intel_tme, &me_state,
+						 &me_state_counter, NULL},
 };
 
 static struct sm_obj_form suspend_lid_group = {
 	.ui_name = "Suspend & Lid",
-	.obj_list = (const struct sm_object *[]) {
-#if CONFIG(SYSTEM_TYPE_LAPTOP)
-		&lid_switch,
+	.obj_list =
+		(const struct sm_object *[]){
+#if CONFIG(EC_STARLABS_LID_SWITCH)
+					     &lid_switch,
 #endif
-		&s0ix_enable,
-		NULL
-	},
+					     &s0ix_enable, NULL},
 };
 
 static struct sm_obj_form virtualization_group = {
 	.ui_name = "Virtualization",
-	.obj_list = (const struct sm_object *[]) {
-		&vtd,
-		NULL
-	},
+	.obj_list = (const struct sm_object *[]){&vtd, NULL},
 };
 
 static struct sm_obj_form wireless_group = {
 	.ui_name = "Wireless",
-	.obj_list = (const struct sm_object *[]) {
-		&bluetooth,
-		&bluetooth_rtd3,
-		&wifi,
-		NULL
-	},
+	.obj_list = (const struct sm_object *[]){&bluetooth, &bluetooth_rtd3, &wifi, NULL},
 };
 
 static struct sm_obj_form *sm_root[] = {
-#if CONFIG(SYSTEM_TYPE_LAPTOP)
+#if CONFIG(SYSTEM_TYPE_LAPTOP) || CONFIG(SYSTEM_TYPE_DETACHABLE)
 	&audio_video_group,
 #endif
 	&battery_group,
 	&debug_group,
-#if CONFIG(SYSTEM_TYPE_LAPTOP)
+#if CONFIG(SYSTEM_TYPE_LAPTOP) || CONFIG(SYSTEM_TYPE_DETACHABLE)
 	&display_group,
+#endif
+#if CONFIG(BOARD_STARLABS_LITE_ADL)
+	&io_expansion_group,
+#endif
+#if CONFIG(SYSTEM_TYPE_LAPTOP)
 	&keyboard_group,
+#endif
+#if CONFIG(EC_STARLABS_POWER_LED) || CONFIG(EC_STARLABS_CHARGE_LED)
 	&leds_group,
 #endif
 	&pcie_power_management_group,
@@ -144,8 +183,7 @@ static struct sm_obj_form *sm_root[] = {
 	&suspend_lid_group,
 	&virtualization_group,
 	&wireless_group,
-	NULL
-};
+	NULL};
 
 void mb_cfr_setup_menu(struct lb_cfr *cfr_root)
 {
diff --git a/src/mainboard/starlabs/adl/dsdt.asl b/src/mainboard/starlabs/adl/dsdt.asl
index 3a68c43aa3..367d6af038 100644
--- a/src/mainboard/starlabs/adl/dsdt.asl
+++ b/src/mainboard/starlabs/adl/dsdt.asl
@@ -22,7 +22,7 @@ DefinitionBlock(
 		#include <soc/intel/alderlake/acpi/tcss.asl>
 
 		#include <soc/intel/common/block/acpi/acpi/gna.asl>
-#if CONFIG(SYSTEM_TYPE_LAPTOP)
+#if CONFIG(SYSTEM_TYPE_LAPTOP) || CONFIG(SYSTEM_TYPE_DETACHABLE)
 		#include <drivers/intel/gma/acpi/default_brightness_levels.asl>
 
 		/* PS/2 Keyboard */
diff --git a/src/mainboard/starlabs/adl/mainboard.c b/src/mainboard/starlabs/adl/mainboard.c
index 1d2fceae53..8a3dadbc48 100644
--- a/src/mainboard/starlabs/adl/mainboard.c
+++ b/src/mainboard/starlabs/adl/mainboard.c
@@ -1,5 +1,10 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
+#if CONFIG(BOARD_STARLABS_LITE_ADL)
+#include <acpi/acpigen_ps2_keybd.h>
+#include <commonlib/helpers.h>
+#endif
+
 #include <device/device.h>
 #include <drivers/intel/gma/opregion.h>
 #include <soc/ramstage.h>
@@ -17,6 +22,24 @@ static void init_mainboard(void *chip_info)
 	devtree_update();
 }
 
+#if CONFIG(BOARD_STARLABS_LITE_ADL)
+static void mainboard_fill_ssdt(const struct device *dev)
+{
+	enum ps2_action_key ps2_action_keys[2] = {PS2_KEY_VOL_DOWN, PS2_KEY_VOL_UP};
+
+	acpigen_ps2_keyboard_dsd("_SB.PCI0.PS2K", ARRAY_SIZE(ps2_action_keys), ps2_action_keys,
+				 false, false, false, false, false);
+}
+#endif
+
+static void enable_mainboard(struct device *dev)
+{
+#if CONFIG(BOARD_STARLABS_LITE_ADL)
+	dev->ops->acpi_fill_ssdt = mainboard_fill_ssdt;
+#endif
+}
+
 struct chip_operations mainboard_ops = {
 	.init = init_mainboard,
+	.enable_dev = enable_mainboard,
 };
diff --git a/src/mainboard/starlabs/adl/spd/Makefile.mk b/src/mainboard/starlabs/adl/spd/Makefile.mk
index f979c5a066..f02db92001 100644
--- a/src/mainboard/starlabs/adl/spd/Makefile.mk
+++ b/src/mainboard/starlabs/adl/spd/Makefile.mk
@@ -1,5 +1,11 @@
 ## SPDX-License-Identifier: GPL-2.0-only
 
+ifeq ($(VARIANT_DIR),hz)
 SPD_SOURCES = rs4g32l05d8fdb-5500
 SPD_SOURCES += rs4g32l05d8fdb-6400
 SPD_SOURCES += rs4g32l05d8fdb-7500
+else ifeq ($(VARIANT_DIR),i5)
+SPD_SOURCES = mt62f2g64d8-5500
+SPD_SOURCES += mt62f2g64d8-6400
+SPD_SOURCES += mt62f2g64d8-7500
+endif
diff --git a/src/mainboard/starlabs/starlite_adl/spd/mt62f2g64d8-5500.spd.hex b/src/mainboard/starlabs/adl/spd/mt62f2g64d8-5500.spd.hex
similarity index 100%
rename from src/mainboard/starlabs/starlite_adl/spd/mt62f2g64d8-5500.spd.hex
rename to src/mainboard/starlabs/adl/spd/mt62f2g64d8-5500.spd.hex
diff --git a/src/mainboard/starlabs/starlite_adl/spd/mt62f2g64d8-6400.spd.hex b/src/mainboard/starlabs/adl/spd/mt62f2g64d8-6400.spd.hex
similarity index 100%
rename from src/mainboard/starlabs/starlite_adl/spd/mt62f2g64d8-6400.spd.hex
rename to src/mainboard/starlabs/adl/spd/mt62f2g64d8-6400.spd.hex
diff --git a/src/mainboard/starlabs/starlite_adl/spd/mt62f2g64d8-7500.spd.hex b/src/mainboard/starlabs/adl/spd/mt62f2g64d8-7500.spd.hex
similarity index 100%
rename from src/mainboard/starlabs/starlite_adl/spd/mt62f2g64d8-7500.spd.hex
rename to src/mainboard/starlabs/adl/spd/mt62f2g64d8-7500.spd.hex
diff --git a/src/mainboard/starlabs/starlite_adl/variants/mk_v/Makefile.mk b/src/mainboard/starlabs/adl/variants/i5/Makefile.mk
similarity index 100%
rename from src/mainboard/starlabs/starlite_adl/variants/mk_v/Makefile.mk
rename to src/mainboard/starlabs/adl/variants/i5/Makefile.mk
diff --git a/src/mainboard/starlabs/starlite_adl/variants/mk_v/board.fmd b/src/mainboard/starlabs/adl/variants/i5/board.fmd
similarity index 100%
rename from src/mainboard/starlabs/starlite_adl/variants/mk_v/board.fmd
rename to src/mainboard/starlabs/adl/variants/i5/board.fmd
diff --git a/src/mainboard/starlabs/starlite_adl/cmos.layout b/src/mainboard/starlabs/adl/variants/i5/cmos.layout
similarity index 100%
rename from src/mainboard/starlabs/starlite_adl/cmos.layout
rename to src/mainboard/starlabs/adl/variants/i5/cmos.layout
diff --git a/src/mainboard/starlabs/starlite_adl/variants/mk_v/data.vbt b/src/mainboard/starlabs/adl/variants/i5/data.vbt
similarity index 100%
rename from src/mainboard/starlabs/starlite_adl/variants/mk_v/data.vbt
rename to src/mainboard/starlabs/adl/variants/i5/data.vbt
diff --git a/src/mainboard/starlabs/starlite_adl/variants/mk_v/data_native_res.vbt b/src/mainboard/starlabs/adl/variants/i5/data_native_res.vbt
similarity index 100%
rename from src/mainboard/starlabs/starlite_adl/variants/mk_v/data_native_res.vbt
rename to src/mainboard/starlabs/adl/variants/i5/data_native_res.vbt
diff --git a/src/mainboard/starlabs/starlite_adl/variants/mk_v/devicetree.cb b/src/mainboard/starlabs/adl/variants/i5/devicetree.cb
similarity index 100%
rename from src/mainboard/starlabs/starlite_adl/variants/mk_v/devicetree.cb
rename to src/mainboard/starlabs/adl/variants/i5/devicetree.cb
diff --git a/src/mainboard/starlabs/starlite_adl/variants/mk_v/devtree.c b/src/mainboard/starlabs/adl/variants/i5/devtree.c
similarity index 100%
rename from src/mainboard/starlabs/starlite_adl/variants/mk_v/devtree.c
rename to src/mainboard/starlabs/adl/variants/i5/devtree.c
diff --git a/src/mainboard/starlabs/starlite_adl/variants/mk_v/gpio.c b/src/mainboard/starlabs/adl/variants/i5/gpio.c
similarity index 56%
rename from src/mainboard/starlabs/starlite_adl/variants/mk_v/gpio.c
rename to src/mainboard/starlabs/adl/variants/i5/gpio.c
index 8c1b7cf79f..e6c03fd9c0 100644
--- a/src/mainboard/starlabs/starlite_adl/variants/mk_v/gpio.c
+++ b/src/mainboard/starlabs/adl/variants/i5/gpio.c
@@ -5,8 +5,8 @@
 /* Early pad configuration in bootblock */
 const struct pad_config early_gpio_table[] = {
 	/* Debug Connector */
-	PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2),				/* RXD */
-	PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2),				/* TXD */
+	PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2), /* RXD */
+	PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2), /* TXD */
 };
 
 const struct pad_config *variant_early_gpio_table(size_t *num)
@@ -18,12 +18,12 @@ const struct pad_config *variant_early_gpio_table(size_t *num)
 /* Pad configuration in ramstage. */
 const struct pad_config gpio_table[] = {
 	/* General Purpose I/O Deep */
-	PAD_CFG_NF(GPD0, NONE, DEEP, NF1),				/* Battery Low */
-	PAD_CFG_NF(GPD1, NONE, DEEP, NF1),				/* Charger Connected */
-	PAD_CFG_NF(GPD3, UP_20K, DEEP, NF1),				/* Power Button */
-	PAD_CFG_NF(GPD4, NONE, DEEP, NF1),				/* Sleep S3 */
-	PAD_CFG_NF(GPD5, NONE, DEEP, NF1),				/* Sleep S4 */
-	PAD_CFG_NF(GPD8, NONE, DEEP, NF1),				/* Bluetooth Suspend */
+	PAD_CFG_NF(GPD0, NONE, DEEP, NF1),   /* Battery Low */
+	PAD_CFG_NF(GPD1, NONE, DEEP, NF1),   /* Charger Connected */
+	PAD_CFG_NF(GPD3, UP_20K, DEEP, NF1), /* Power Button */
+	PAD_CFG_NF(GPD4, NONE, DEEP, NF1),   /* Sleep S3 */
+	PAD_CFG_NF(GPD5, NONE, DEEP, NF1),   /* Sleep S4 */
+	PAD_CFG_NF(GPD8, NONE, DEEP, NF1),   /* Bluetooth Suspend */
 
 	/* eSPI - Configure automatically on reset */
 	// PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_A0, UP_20K, DEEP, NF1),	/* eSPI IO 0 */
@@ -35,74 +35,75 @@ const struct pad_config gpio_table[] = {
 	// PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_A10, NONE, DEEP, NF1),	/* eSPI Reset */
 
 	/* Touchpanel */
-	PAD_CFG_NF(GPP_B5, NONE, DEEP, NF2),				/* Data */
-	PAD_CFG_NF(GPP_B6, NONE, DEEP, NF2),				/* Clock */
-	PAD_CFG_GPI_APIC_LOW(GPP_E12, NONE, PLTRST),			/* Interrupt */
-	PAD_CFG_GPO(GPP_F17, 1, PLTRST),				/* Reset */
-	PAD_CFG_GPI_APIC(GPP_F18, NONE, PLTRST, LEVEL, INVERT),		/* Interrupt */
+	PAD_CFG_NF(GPP_B5, NONE, DEEP, NF2),                    /* Data */
+	PAD_CFG_NF(GPP_B6, NONE, DEEP, NF2),                    /* Clock */
+	PAD_CFG_GPI_APIC_LOW(GPP_E12, NONE, PLTRST),            /* Interrupt */
+	PAD_CFG_GPO(GPP_F17, 1, PLTRST),                        /* Reset */
+	PAD_CFG_GPI_APIC(GPP_F18, NONE, PLTRST, LEVEL, INVERT), /* Interrupt */
 
 	/* Accelerometer */
-	PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1),				/* Data */
-	PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1),				/* Clock */
+	PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1), /* Data */
+	PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1), /* Clock */
 
 	/* Keyboard */
-	PAD_CFG_GPI_SMI_LOW(GPP_F15, NONE, DEEP, EDGE_BOTH),		/* Detect */
+	PAD_CFG_GPI_SMI_LOW(GPP_F15, NONE, DEEP, EDGE_BOTH), /* Detect */
 
 	/* SSD */
-	PAD_CFG_NF(GPP_D5, NONE, DEEP, NF1),				/* Clock Request 0 */
-	PAD_CFG_GPO(GPP_H0, 1, PLTRST),					/* Reset */
-	PAD_CFG_GPO(GPP_D16, 1, DEEP),					/* Enable */
+	PAD_CFG_NF(GPP_D5, NONE, DEEP, NF1), /* Clock Request 0 */
+	PAD_CFG_GPO(GPP_H0, 1, PLTRST),      /* Reset */
+	PAD_CFG_GPO(GPP_D16, 1, DEEP),       /* Enable */
 
 	/* Wireless */
-	PAD_CFG_NF(GPP_F0, NONE, DEEP, NF1),				/* BRI Data */
-	PAD_CFG_NF(GPP_F1, UP_20K, DEEP, NF1),				/* BRI Response */
-	PAD_CFG_NF(GPP_F2, NONE, DEEP, NF1),				/* RGI Data */
-	PAD_CFG_NF(GPP_F3, UP_20K, DEEP, NF1),				/* RGI Response */
-	PAD_CFG_NF(GPP_F4, NONE, DEEP, NF1),				/* RF Reset */
-	PAD_CFG_NF(GPP_F5, NONE, DEEP, NF2),				/* Modem Clock Request */
-	PAD_CFG_GPO(GPP_E3, 1, DEEP),					/* WiFi RF Kill */
-	PAD_CFG_GPO(GPP_A13, 1, DEEP),					/* Bluetooth RF Kill */
+	PAD_CFG_NF(GPP_F0, NONE, DEEP, NF1),   /* BRI Data */
+	PAD_CFG_NF(GPP_F1, UP_20K, DEEP, NF1), /* BRI Response */
+	PAD_CFG_NF(GPP_F2, NONE, DEEP, NF1),   /* RGI Data */
+	PAD_CFG_NF(GPP_F3, UP_20K, DEEP, NF1), /* RGI Response */
+	PAD_CFG_NF(GPP_F4, NONE, DEEP, NF1),   /* RF Reset */
+	PAD_CFG_NF(GPP_F5, NONE, DEEP, NF2),   /* Modem Clock Request */
+	PAD_CFG_GPO(GPP_E3, 1, DEEP),          /* WiFi RF Kill */
+	PAD_CFG_GPO(GPP_A13, 1, DEEP),         /* Bluetooth RF Kill */
 
 	/* Display */
-	PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1),				/* eDP Hot Plug */
-	PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1),				/* HDMI Hot Plug */
-	PAD_CFG_NF(GPP_H15, NONE, DEEP, NF1),				/* HDMI Clock */
-	PAD_CFG_NF(GPP_H17, NONE, DEEP, NF1),				/* HDMI Data */
-	PAD_CFG_NF(GPP_A19, NONE, DEEP, NF1),				/* TCP0 Hot Plug */
-	PAD_CFG_NF(GPP_A20, NONE, DEEP, NF1),				/* TCP0 Hot Plug */
+	PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), /* eDP Hot Plug */
+	PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1), /* HDMI Hot Plug */
+	PAD_CFG_NF(GPP_H15, NONE, DEEP, NF1), /* HDMI Clock */
+	PAD_CFG_NF(GPP_H17, NONE, DEEP, NF1), /* HDMI Data */
+	PAD_CFG_NF(GPP_A19, NONE, DEEP, NF1), /* TCP0 Hot Plug */
+	PAD_CFG_NF(GPP_A20, NONE, DEEP, NF1), /* TCP0 Hot Plug */
 
 	/* High-Definition Audio */
-	PAD_CFG_NF(GPP_R0, NATIVE, DEEP, NF1),				/* Clock */
-	PAD_CFG_NF(GPP_R1, NATIVE, DEEP, NF1),				/* Sync */
-	PAD_CFG_NF(GPP_R2, NATIVE, DEEP, NF1),				/* Data Output */
-	PAD_CFG_NF(GPP_R3, NATIVE, DEEP, NF1),				/* Data Input */
-	PAD_CFG_NF(GPP_R4, NATIVE, DEEP, NF1),				/* Reset */
+	PAD_CFG_NF(GPP_R0, NATIVE, DEEP, NF1), /* Clock */
+	PAD_CFG_NF(GPP_R1, NATIVE, DEEP, NF1), /* Sync */
+	PAD_CFG_NF(GPP_R2, NATIVE, DEEP, NF1), /* Data Output */
+	PAD_CFG_NF(GPP_R3, NATIVE, DEEP, NF1), /* Data Input */
+	PAD_CFG_NF(GPP_R4, NATIVE, DEEP, NF1), /* Reset */
 
 	/* PCH */
-	PAD_CFG_NF(GPP_H18, NONE, DEEP, NF1),				/* C10 Gate */
-	PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1),				/* Platform Reset */
-	PAD_CFG_NF(GPP_B0, NONE, DEEP, NF1),				/* Vendor ID 0 */
-	PAD_CFG_NF(GPP_B1, NONE, DEEP, NF1),				/* Vendor ID 1 */
-	PAD_CFG_GPI_SCI(GPP_B2, NONE, PLTRST, EDGE_SINGLE, INVERT),	/* Processor Hot */
+	PAD_CFG_NF(GPP_H18, NONE, DEEP, NF1),                       /* C10 Gate */
+	PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1),                       /* Platform Reset */
+	PAD_CFG_NF(GPP_B0, NONE, DEEP, NF1),                        /* Vendor ID 0 */
+	PAD_CFG_NF(GPP_B1, NONE, DEEP, NF1),                        /* Vendor ID 1 */
+	PAD_CFG_GPI_SCI(GPP_B2, NONE, PLTRST, EDGE_SINGLE, INVERT), /* Processor Hot */
 
 	/* SMBus */
-	PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1),				/* Clock */
-	PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1),				/* Data */
-	PAD_CFG_GPO(GPP_E8, 1, DEEP),					/* DRAM Sleep */
+	PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), /* Clock */
+	PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), /* Data */
+	PAD_CFG_GPO(GPP_E8, 1, DEEP),        /* DRAM Sleep */
 
 	/* Config Straps 									[ Low      / High     ] */
-	PAD_CFG_GPO(GPP_B14, 0, PLTRST),				/* Top Swap		[ Disabled / Enabled  ] */
-	PAD_CFG_GPO(GPP_B18, 0, PLTRST),				/* Reboot Support	[ Enabled  / Disabled ] */
-	PAD_CFG_GPO(GPP_C2, 1, PLTRST),					/* TLS Confidentiality	[ Disabled / Enabled  ] */
-	PAD_CFG_GPO(GPP_C5, 0, PLTRST),					/* eSPI			[ Enabled  / Disabled ] */
-	PAD_CFG_GPO(GPP_E6, 0, PLTRST),					/* JTAG ODT		[ Disabled / Enabled  ] */
-	PAD_CFG_GPO(GPP_H1, 0, PLTRST),					/* BFX Strap 2 Bit 3	[ Disabled / Enabled  ] */
-	PAD_CFG_GPO(GPP_E19, 0, PLTRST),				/* TBT LSX #0		[ 1.8V     / 3.3V     ] */
-	PAD_CFG_GPO(GPP_E21, 0, PLTRST),				/* TBT LSX #1           [ 1.8V     / 3.3V     ] */
-	PAD_CFG_GPO(GPP_D10, 0, PLTRST),				/* TBT LSX #2		[ 1.8V     / 3.3V     ] */
-	PAD_CFG_GPO(GPP_D12, 0, PLTRST),				/* TBT LSX #3		[ 1.8V     / 3.3V     ] */
-	PAD_CFG_GPO(GPP_F7, 0, PLTRST),					/* MCRO LDO		[ Disabled / Bypass   ] */
-	PAD_CFG_GPO(GPD7, 0, PLTRST),					/* RTC Clock Delay	[ Disabled / 95ms     ] */
+	PAD_CFG_GPO(GPP_B14, 0, PLTRST), /* Top Swap		[ Disabled / Enabled  ] */
+	PAD_CFG_GPO(GPP_B18, 0, PLTRST), /* Reboot Support	[ Enabled  / Disabled ] */
+	PAD_CFG_GPO(GPP_C2, 1, PLTRST),  /* TLS Confidentiality	[ Disabled / Enabled  ] */
+	PAD_CFG_GPO(GPP_C5, 0,
+		    PLTRST),             /* eSPI			[ Enabled  / Disabled ] */
+	PAD_CFG_GPO(GPP_E6, 0, PLTRST),  /* JTAG ODT		[ Disabled / Enabled  ] */
+	PAD_CFG_GPO(GPP_H1, 0, PLTRST),  /* BFX Strap 2 Bit 3	[ Disabled / Enabled  ] */
+	PAD_CFG_GPO(GPP_E19, 0, PLTRST), /* TBT LSX #0		[ 1.8V     / 3.3V     ] */
+	PAD_CFG_GPO(GPP_E21, 0, PLTRST), /* TBT LSX #1           [ 1.8V     / 3.3V     ] */
+	PAD_CFG_GPO(GPP_D10, 0, PLTRST), /* TBT LSX #2		[ 1.8V     / 3.3V     ] */
+	PAD_CFG_GPO(GPP_D12, 0, PLTRST), /* TBT LSX #3		[ 1.8V     / 3.3V     ] */
+	PAD_CFG_GPO(GPP_F7, 0, PLTRST),  /* MCRO LDO		[ Disabled / Bypass   ] */
+	PAD_CFG_GPO(GPD7, 0, PLTRST),    /* RTC Clock Delay	[ Disabled / 95ms     ] */
 
 	PAD_NC(GPD2, NONE),
 	PAD_NC(GPD6, NONE),
diff --git a/src/mainboard/starlabs/adl/variants/i5/hda_verb.c b/src/mainboard/starlabs/adl/variants/i5/hda_verb.c
new file mode 100644
index 0000000000..f7529371d6
--- /dev/null
+++ b/src/mainboard/starlabs/adl/variants/i5/hda_verb.c
@@ -0,0 +1,77 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <device/azalia_device.h>
+#include <device/azalia_codec/realtek.h>
+
+const u32 cim_verb_data[] = {
+	/* coreboot specific header */
+	0x10ec0269, /* Codec Vendor / Device ID: Realtek ALC269 */
+	0x1e507038, /* Subsystem ID */
+	18,         /* Number of jacks (NID entries) */
+
+	/* Reset Codec First */
+	AZALIA_RESET(0x1),
+
+	/* HDA Codec Subsystem ID */
+	AZALIA_SUBVENDOR(0, 0x1e507038),
+
+	/* Pin Widget Verb-table */
+	AZALIA_PIN_CFG(0, ALC269_DMIC12,
+		       AZALIA_PIN_DESC(AZALIA_INTEGRATED, AZALIA_INTERNAL | AZALIA_FRONT,
+				       AZALIA_MIC_IN, AZALIA_OTHER_DIGITAL,
+				       AZALIA_COLOR_UNKNOWN, AZALIA_NO_JACK_PRESENCE_DETECT, 3,
+				       0)),
+
+	AZALIA_PIN_CFG(0, ALC269_SPEAKERS,
+		       AZALIA_PIN_DESC(AZALIA_INTEGRATED, AZALIA_INTERNAL | AZALIA_FRONT,
+				       AZALIA_SPEAKER, AZALIA_OTHER_ANALOG,
+				       AZALIA_COLOR_UNKNOWN, AZALIA_NO_JACK_PRESENCE_DETECT, 1,
+				       0)),
+	AZALIA_PIN_CFG(0, ALC269_VC_HP_OUT,
+		       AZALIA_PIN_DESC(AZALIA_JACK,
+				       AZALIA_EXTERNAL_PRIMARY_CHASSIS | AZALIA_RIGHT,
+				       AZALIA_HP_OUT, AZALIA_STEREO_MONO_1_8, AZALIA_BLACK,
+				       AZALIA_JACK_PRESENCE_DETECT, 2, 0)),
+	AZALIA_PIN_CFG(0, ALC269_MIC1,
+		       AZALIA_PIN_DESC(AZALIA_JACK,
+				       AZALIA_EXTERNAL_PRIMARY_CHASSIS | AZALIA_RIGHT,
+				       AZALIA_MIC_IN, AZALIA_STEREO_MONO_1_8, AZALIA_BLACK,
+				       AZALIA_JACK_PRESENCE_DETECT, 4, 0)),
+	AZALIA_PIN_CFG(0, ALC269_MONO, AZALIA_PIN_CFG_NC(0)),
+	AZALIA_PIN_CFG(0, ALC269_MIC2, AZALIA_PIN_CFG_NC(0)),
+	AZALIA_PIN_CFG(0, ALC269_LINE1, AZALIA_PIN_CFG_NC(0)),
+	AZALIA_PIN_CFG(0, ALC269_LINE2, AZALIA_PIN_CFG_NC(0)),
+	AZALIA_PIN_CFG(0, ALC269_PC_BEEP, AZALIA_PIN_CFG_NC(0)),
+	AZALIA_PIN_CFG(0, ALC269_SPDIF_OUT, AZALIA_PIN_CFG_NC(0)),
+	AZALIA_PIN_CFG(0, ALC269_VB_HP_OUT, AZALIA_PIN_CFG_NC(0)),
+
+	/* ALC269 Default 1 */
+	0x02050018,
+	0x02040184,
+	0x0205001c,
+	0x02044800,
+	/* ALC269 Default 2 */
+	0x02050024,
+	0x02040000,
+	0x02050004,
+	0x02040080,
+	/* ALC269 Default 3 */
+	0x02050008,
+	0x02040000,
+	0x0205000c,
+	0x02043f00,
+	/* ALC269 Default 4 */
+	0x02050015,
+	0x02048002,
+	0x02050015,
+	0x02048002,
+	/* Widget 0x0c */
+	0x00c37080,
+	0x00270610,
+	0x00d37080,
+	0x00370610,
+};
+
+const u32 pc_beep_verbs[] = {};
+
+AZALIA_ARRAY_SIZES;
diff --git a/src/mainboard/starlabs/starlite_adl/variants/mk_v/ramstage.c b/src/mainboard/starlabs/adl/variants/i5/ramstage.c
similarity index 100%
rename from src/mainboard/starlabs/starlite_adl/variants/mk_v/ramstage.c
rename to src/mainboard/starlabs/adl/variants/i5/ramstage.c
diff --git a/src/mainboard/starlabs/starlite_adl/variants/mk_v/romstage.c b/src/mainboard/starlabs/adl/variants/i5/romstage.c
similarity index 100%
rename from src/mainboard/starlabs/starlite_adl/variants/mk_v/romstage.c
rename to src/mainboard/starlabs/adl/variants/i5/romstage.c
diff --git a/src/mainboard/starlabs/starlite_adl/variants/mk_v/vboot.fmd b/src/mainboard/starlabs/adl/variants/i5/vboot.fmd
similarity index 100%
rename from src/mainboard/starlabs/starlite_adl/variants/mk_v/vboot.fmd
rename to src/mainboard/starlabs/adl/variants/i5/vboot.fmd
diff --git a/src/mainboard/starlabs/starlite_adl/Kconfig b/src/mainboard/starlabs/starlite_adl/Kconfig
deleted file mode 100644
index 00c2a4ecb5..0000000000
--- a/src/mainboard/starlabs/starlite_adl/Kconfig
+++ /dev/null
@@ -1,123 +0,0 @@
-config BOARD_STARLABS_STARLITE_SERIES
-	def_bool n
-	select AZALIA_USE_LEGACY_VERB_TABLE
-	select BOARD_ROMSIZE_KB_16384
-	select CRB_TPM
-	select CSE_DEFAULT_CFR_OPTION_STATE_DISABLED
-	select DRIVERS_EFI_VARIABLE_STORE
-	select DRIVERS_GFX_GENERIC
-	select DRIVERS_I2C_HID
-	select DRIVERS_INTEL_PMC
-	select DRIVERS_OPTION_CFR_ENABLED
-	select EC_STARLABS_MERLIN
-	select HAVE_ACPI_RESUME
-	select HAVE_ACPI_TABLES
-	select HAVE_HDA_DMIC
-	select HAVE_INTEL_PTT
-	select HAVE_OPTION_TABLE
-	select HAVE_SPD_IN_CBFS
-	select INTEL_GMA_HAVE_VBT
-	select INTEL_LPSS_UART_FOR_CONSOLE
-	select NO_UART_ON_SUPERIO
-	select PMC_IPC_ACPI_INTERFACE
-	select SOC_INTEL_ALDERLAKE
-	select SOC_INTEL_ALDERLAKE_PCH_N
-	select SOC_INTEL_COMMON_BLOCK_HDA_VERB
-	select SOC_INTEL_COMMON_BLOCK_TCSS
-	select SOC_INTEL_CRASHLOG
-	select SPD_READ_BY_WORD
-	select SPI_FLASH_WINBOND
-	select SYSTEM_TYPE_DETACHABLE
-	select TPM2
-	select VALIDATE_INTEL_DESCRIPTOR
-
-config BOARD_STARLABS_LITE_ADL
-	select BOARD_STARLABS_STARLITE_SERIES
-
-if BOARD_STARLABS_STARLITE_SERIES
-
-config CCD_PORT
-	int
-	default 5
-
-config CONSOLE_SERIAL
-	default n if !EDK2_DEBUG
-
-config D3COLD_SUPPORT
-	default n
-
-config DEVICETREE
-	default "variants/\$(CONFIG_VARIANT_DIR)/devicetree.cb"
-
-config DIMM_SPD_SIZE
-	default 512
-
-config EC_STARLABS_BATTERY_MODEL
-	default "AEC3756153-2S1P-N"
-
-config EC_STARLABS_BATTERY_TYPE
-	default "LION"
-
-config EC_STARLABS_BATTERY_OEM
-	default "Apower Electronics"
-
-config EC_STARLABS_ITE_BIN_PATH
-	string
-	default "3rdparty/blobs/mainboard/\$(MAINBOARDDIR)/\$(CONFIG_VARIANT_DIR)/ec.bin"
-
-config FMDFILE
-	default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/variants/\$(CONFIG_VARIANT_DIR)/vboot.fmd" if VBOOT
-	default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/variants/\$(CONFIG_VARIANT_DIR)/board.fmd"
-
-config IFD_BIN_PATH
-	string
-	default "3rdparty/blobs/mainboard/\$(MAINBOARDDIR)/\$(CONFIG_VARIANT_DIR)/flashdescriptor.bin"
-
-config MAINBOARD_DIR
-	default "starlabs/starlite_adl"
-
-config MAINBOARD_FAMILY
-	string
-	default "I5"
-
-config MAINBOARD_PART_NUMBER
-	default "StarLite Mk V"
-
-config MAINBOARD_SMBIOS_PRODUCT_NAME
-	default "StarLite"
-
-config ME_BIN_PATH
-	string
-	default "3rdparty/blobs/mainboard/\$(MAINBOARDDIR)/\$(CONFIG_VARIANT_DIR)/intel_me.bin"
-
-config POWER_STATE_DEFAULT_ON_AFTER_FAILURE
-	default n
-
-config EDK2_BOOTSPLASH_FILE
-	string
-	default "3rdparty/blobs/mainboard/starlabs/Logo.bmp"
-
-config SOC_INTEL_CSE_SEND_EOP_EARLY
-	default n
-
-config TJ_MAX
-	int
-	default 105
-
-config PL4_WATTS
-	int
-	default 37
-
-config UART_FOR_CONSOLE
-	default 0
-
-config USE_PM_ACPI_TIMER
-	default n
-
-config VBOOT
-	select VBOOT_VBNV_FLASH
-
-config VARIANT_DIR
-	default "mk_v"
-
-endif
diff --git a/src/mainboard/starlabs/starlite_adl/Kconfig.name b/src/mainboard/starlabs/starlite_adl/Kconfig.name
deleted file mode 100644
index 071490084b..0000000000
--- a/src/mainboard/starlabs/starlite_adl/Kconfig.name
+++ /dev/null
@@ -1,4 +0,0 @@
-comment "Star Labs StarLite Series"
-
-config BOARD_STARLABS_LITE_ADL
-	bool "Star Labs Lite Mk V (N200/N355)"
diff --git a/src/mainboard/starlabs/starlite_adl/Makefile.mk b/src/mainboard/starlabs/starlite_adl/Makefile.mk
deleted file mode 100644
index 14842f76e4..0000000000
--- a/src/mainboard/starlabs/starlite_adl/Makefile.mk
+++ /dev/null
@@ -1,14 +0,0 @@
-## SPDX-License-Identifier: GPL-2.0-only
-
-CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/include
-subdirs-$(CONFIG_HAVE_SPD_IN_CBFS) += ./spd
-subdirs-y += variants/$(VARIANT_DIR)
-
-bootblock-y += bootblock.c
-
-verstage-$(CONFIG_VBOOT) += vboot.c
-
-romstage-$(CONFIG_VBOOT) += vboot.c
-
-ramstage-$(CONFIG_DRIVERS_OPTION_CFR) += cfr.c
-ramstage-y += mainboard.c
diff --git a/src/mainboard/starlabs/starlite_adl/acpi/ec.asl b/src/mainboard/starlabs/starlite_adl/acpi/ec.asl
deleted file mode 100644
index 853b0877b3..0000000000
--- a/src/mainboard/starlabs/starlite_adl/acpi/ec.asl
+++ /dev/null
@@ -1 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
diff --git a/src/mainboard/starlabs/starlite_adl/acpi/mainboard.asl b/src/mainboard/starlabs/starlite_adl/acpi/mainboard.asl
deleted file mode 100644
index f9d095244a..0000000000
--- a/src/mainboard/starlabs/starlite_adl/acpi/mainboard.asl
+++ /dev/null
@@ -1,13 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-Scope (\_SB) {
-	#include "sleep.asl"
-}
-
-Scope (_GPE)
-{
-	Method (_E0F, 0, NotSerialized)
-	{
-		\_SB.PCI0.LPCB.EC.VBTN.UPDK()
-	}
-}
diff --git a/src/mainboard/starlabs/starlite_adl/acpi/sleep.asl b/src/mainboard/starlabs/starlite_adl/acpi/sleep.asl
deleted file mode 100644
index 7ed74e3514..0000000000
--- a/src/mainboard/starlabs/starlite_adl/acpi/sleep.asl
+++ /dev/null
@@ -1,11 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-Method (MPTS, 1, NotSerialized)
-{
-	RPTS (Arg0)
-}
-
-Method (MWAK, 1, NotSerialized)
-{
-	RWAK (Arg0)
-}
diff --git a/src/mainboard/starlabs/starlite_adl/acpi/superio.asl b/src/mainboard/starlabs/starlite_adl/acpi/superio.asl
deleted file mode 100644
index 853b0877b3..0000000000
--- a/src/mainboard/starlabs/starlite_adl/acpi/superio.asl
+++ /dev/null
@@ -1 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
diff --git a/src/mainboard/starlabs/starlite_adl/board_info.txt b/src/mainboard/starlabs/starlite_adl/board_info.txt
deleted file mode 100644
index 77f1b9b0d5..0000000000
--- a/src/mainboard/starlabs/starlite_adl/board_info.txt
+++ /dev/null
@@ -1,6 +0,0 @@
-Vendor name: Star Labs
-Board name: StarLite
-Category: laptop
-ROM protocol: SPI
-ROM socketed: n
-Flashrom support: y
diff --git a/src/mainboard/starlabs/starlite_adl/bootblock.c b/src/mainboard/starlabs/starlite_adl/bootblock.c
deleted file mode 100644
index ca48bb1ab2..0000000000
--- a/src/mainboard/starlabs/starlite_adl/bootblock.c
+++ /dev/null
@@ -1,14 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <bootblock_common.h>
-#include <soc/gpio.h>
-#include <variants.h>
-
-void bootblock_mainboard_init(void)
-{
-	const struct pad_config *pads;
-	size_t num;
-
-	pads = variant_early_gpio_table(&num);
-	gpio_configure_pads(pads, num);
-}
diff --git a/src/mainboard/starlabs/starlite_adl/cfr.c b/src/mainboard/starlabs/starlite_adl/cfr.c
deleted file mode 100644
index 0cf911b9f2..0000000000
--- a/src/mainboard/starlabs/starlite_adl/cfr.c
+++ /dev/null
@@ -1,169 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <boot/coreboot_tables.h>
-#include <console/cfr.h>
-#include <drivers/option/cfr_frontend.h>
-#include <ec/starlabs/merlin/cfr.h>
-#include <intelblocks/cfr.h>
-#include <device/i2c_bus.h>
-#include <device/i2c_simple.h>
-#include <option.h>
-#include <static.h>
-#include <variants.h>
-#include <common/cfr.h>
-
-void cfr_card_reader_update(struct sm_object *new_obj)
-{
-	struct device *mxc_accel = DEV_PTR(mxc6655);
-
-	if (!i2c_dev_detect(i2c_busdev(mxc_accel), mxc_accel->path.i2c.device))
-		new_obj->sm_bool.flags = CFR_OPTFLAG_SUPPRESS;
-}
-
-void cfr_touchscreen_update(struct sm_object *new_obj)
-{
-	if (get_uint_option("accelerometer", 1) == 0)
-		new_obj->sm_bool.flags = CFR_OPTFLAG_SUPPRESS;
-}
-
-static struct sm_obj_form audio_video_group = {
-	.ui_name = "Audio/Video",
-	.obj_list = (const struct sm_object *[]) {
-		&microphone,
-		&webcam,
-		NULL
-	},
-};
-
-static struct sm_obj_form battery_group = {
-	.ui_name = "Battery",
-	.obj_list = (const struct sm_object *[]) {
-		#if CONFIG(EC_STARLABS_CHARGING_SPEED)
-		&charging_speed,
-		#endif
-		&max_charge,
-		&power_on_after_fail_bool,
-		NULL
-	},
-};
-
-static struct sm_obj_form debug_group = {
-	.ui_name = "Debug",
-	.obj_list = (const struct sm_object *[]) {
-		&debug_level,
-		NULL
-	},
-};
-
-static struct sm_obj_form display_group = {
-	.ui_name = "Display",
-	.obj_list = (const struct sm_object *[]) {
-		&accelerometer,
-		&display_native_res,
-		&touchscreen,
-		NULL
-	},
-};
-
-static struct sm_obj_form io_expansion_group = {
-	.ui_name = "I/O / Expansion",
-	.obj_list = (const struct sm_object *[]) {
-		&card_reader,
-		NULL
-	},
-};
-
-static struct sm_obj_form leds_group = {
-	.ui_name = "LEDs",
-	.obj_list = (const struct sm_object *[]) {
-		&charge_led,
-		&power_led,
-		NULL
-	},
-};
-
-static struct sm_obj_form pcie_power_management_group = {
-	.ui_name = "PCIe Power Management",
-	.obj_list = (const struct sm_object *[]) {
-		#if CONFIG(SOC_INTEL_COMMON_BLOCK_ASPM)
-		&pciexp_aspm,
-		&pciexp_clk_pm,
-		&pciexp_l1ss,
-		#endif
-		NULL
-	},
-};
-
-static struct sm_obj_form performance_group = {
-	.ui_name = "Performance",
-	.obj_list = (const struct sm_object *[]) {
-		#if CONFIG(SOC_INTEL_TIGERLAKE) || CONFIG(SOC_INTEL_ALDERLAKE) || CONFIG(SOC_INTEL_RAPTORLAKE)
-		&gna,
-		#endif
-		&memory_speed,
-		&power_profile,
-		NULL
-	},
-};
-
-static struct sm_obj_form security_group = {
-	.ui_name = "Security",
-	.obj_list = (const struct sm_object *[]) {
-		&bios_lock,
-		&intel_tme,
-		&me_state,
-		&me_state_counter,
-		NULL
-	},
-};
-
-static struct sm_obj_form suspend_lid_group = {
-	.ui_name = "Suspend & Lid",
-	.obj_list = (const struct sm_object *[]) {
-		#if CONFIG(EC_STARLABS_LID_SWITCH)
-		&lid_switch,
-		#endif
-		&s0ix_enable,
-		NULL
-	},
-};
-
-static struct sm_obj_form virtualization_group = {
-	.ui_name = "Virtualization",
-	.obj_list = (const struct sm_object *[]) {
-		&vtd,
-		NULL
-	},
-};
-
-static struct sm_obj_form wireless_group = {
-	.ui_name = "Wireless",
-	.obj_list = (const struct sm_object *[]) {
-		&bluetooth,
-		&bluetooth_rtd3,
-		&wifi,
-		NULL
-	},
-};
-
-static struct sm_obj_form *sm_root[] = {
-	&audio_video_group,
-	&battery_group,
-	&debug_group,
-	&display_group,
-	&io_expansion_group,
-	&leds_group,
-	&pcie_power_management_group,
-	&performance_group,
-	&security_group,
-	&suspend_lid_group,
-	&virtualization_group,
-	&wireless_group,
-	NULL
-};
-
-void mb_cfr_setup_menu(struct lb_cfr *cfr_root)
-{
-	starlabs_cfr_register_overrides();
-	cfr_write_setup_menu(cfr_root, sm_root);
-}
diff --git a/src/mainboard/starlabs/starlite_adl/dsdt.asl b/src/mainboard/starlabs/starlite_adl/dsdt.asl
deleted file mode 100644
index b7783eae63..0000000000
--- a/src/mainboard/starlabs/starlite_adl/dsdt.asl
+++ /dev/null
@@ -1,47 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <acpi/acpi.h>
-DefinitionBlock(
-	"dsdt.aml",
-	"DSDT",
-	ACPI_DSDT_REV_2,
-	OEM_ID,
-	ACPI_TABLE_CREATOR,
-	0x20220930
-)
-{
-	#include <acpi/dsdt_top.asl>
-	#include <soc/intel/common/block/acpi/acpi/platform.asl>
-	#include <soc/intel/common/block/acpi/acpi/globalnvs.asl>
-	#include <cpu/intel/common/acpi/cpu.asl>
-
-	Device (\_SB.PCI0)
-	{
-		#include <soc/intel/common/block/acpi/acpi/northbridge.asl>
-		#include <soc/intel/alderlake/acpi/southbridge.asl>
-		#include <soc/intel/alderlake/acpi/tcss.asl>
-
-		#include <drivers/intel/gma/acpi/default_brightness_levels.asl>
-
-		#include <soc/intel/common/block/acpi/acpi/gna.asl>
-
-		/* PS/2 Keyboard */
-		#include <drivers/pc80/pc/ps2_controller.asl>
-	}
-
-	#include <southbridge/intel/common/acpi/sleepstates.asl>
-
-	/* Star Labs EC */
-	#include <ec/starlabs/merlin/acpi/ec.asl>
-
-	Scope (\_SB)
-	{
-		/* HID Driver */
-		#include <ec/starlabs/merlin/acpi/hid.asl>
-
-		/* Suspend Methods */
-		#include <ec/starlabs/merlin/acpi/suspend.asl>
-	}
-
-	#include "acpi/mainboard.asl"
-}
diff --git a/src/mainboard/starlabs/starlite_adl/include/variants.h b/src/mainboard/starlabs/starlite_adl/include/variants.h
deleted file mode 100644
index c95d15bd72..0000000000
--- a/src/mainboard/starlabs/starlite_adl/include/variants.h
+++ /dev/null
@@ -1,17 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#ifndef _BASEBOARD_VARIANTS_H_
-#define _BASEBOARD_VARIANTS_H_
-
-#include <soc/gpio.h>
-
-/*
- * The next set of functions return the gpio table and fill in the number of
- * entries for each table.
- */
-const struct pad_config *variant_gpio_table(size_t *num);
-const struct pad_config *variant_early_gpio_table(size_t *num);
-
-void devtree_update(void);
-
-#endif /* _BASEBOARD_VARIANTS_H_ */
diff --git a/src/mainboard/starlabs/starlite_adl/mainboard.c b/src/mainboard/starlabs/starlite_adl/mainboard.c
deleted file mode 100644
index 1583ad9094..0000000000
--- a/src/mainboard/starlabs/starlite_adl/mainboard.c
+++ /dev/null
@@ -1,32 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <acpi/acpigen_ps2_keybd.h>
-#include <device/device.h>
-#include <soc/ramstage.h>
-#include <variants.h>
-
-static void init_mainboard(void *chip_info)
-{
-	const struct pad_config *pads;
-	size_t num;
-
-	pads = variant_gpio_table(&num);
-	gpio_configure_pads(pads, num);
-}
-
-static void mainboard_fill_ssdt(const struct device *dev)
-{
-	enum ps2_action_key ps2_action_keys[2] = {PS2_KEY_VOL_DOWN, PS2_KEY_VOL_UP};
-	acpigen_ps2_keyboard_dsd("_SB.PCI0.PS2K", ARRAY_SIZE(ps2_action_keys), ps2_action_keys,
-				 false, false, false, false, false);
-}
-
-static void enable_mainboard(struct device *dev)
-{
-	dev->ops->acpi_fill_ssdt = mainboard_fill_ssdt;
-}
-
-struct chip_operations mainboard_ops = {
-	.init = init_mainboard,
-	.enable_dev = enable_mainboard,
-};
diff --git a/src/mainboard/starlabs/starlite_adl/spd/Makefile.mk b/src/mainboard/starlabs/starlite_adl/spd/Makefile.mk
deleted file mode 100644
index 7c50cd736a..0000000000
--- a/src/mainboard/starlabs/starlite_adl/spd/Makefile.mk
+++ /dev/null
@@ -1,5 +0,0 @@
-## SPDX-License-Identifier: GPL-2.0-only
-
-SPD_SOURCES = mt62f2g64d8-5500
-SPD_SOURCES += mt62f2g64d8-6400
-SPD_SOURCES += mt62f2g64d8-7500
diff --git a/src/mainboard/starlabs/starlite_adl/variants/mk_v/hda_verb.c b/src/mainboard/starlabs/starlite_adl/variants/mk_v/hda_verb.c
deleted file mode 100644
index 24d23ae55d..0000000000
--- a/src/mainboard/starlabs/starlite_adl/variants/mk_v/hda_verb.c
+++ /dev/null
@@ -1,98 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <device/azalia_device.h>
-#include <device/azalia_codec/realtek.h>
-
-const u32 cim_verb_data[] = {
-	/* coreboot specific header */
-	0x10ec0269,	/* Codec Vendor / Device ID: Realtek ALC269 */
-	0x1e507038,	/* Subsystem ID */
-	18,		/* Number of jacks (NID entries) */
-
-	/* Reset Codec First */
-	AZALIA_RESET(0x1),
-
-	/* HDA Codec Subsystem ID */
-	AZALIA_SUBVENDOR(0, 0x1e507038),
-
-	/* Pin Widget Verb-table */
-	AZALIA_PIN_CFG(0, ALC269_DMIC12,	AZALIA_PIN_DESC(
-							AZALIA_INTEGRATED,
-							AZALIA_INTERNAL | AZALIA_FRONT,
-							AZALIA_MIC_IN,
-							AZALIA_OTHER_DIGITAL,
-							AZALIA_COLOR_UNKNOWN,
-							AZALIA_NO_JACK_PRESENCE_DETECT,
-							3,
-							0
-						)),
-
-	AZALIA_PIN_CFG(0, ALC269_SPEAKERS,	AZALIA_PIN_DESC(
-							AZALIA_INTEGRATED,
-							AZALIA_INTERNAL | AZALIA_FRONT,
-							AZALIA_SPEAKER,
-							AZALIA_OTHER_ANALOG,
-							AZALIA_COLOR_UNKNOWN,
-							AZALIA_NO_JACK_PRESENCE_DETECT,
-							1,
-							0
-						)),
-	AZALIA_PIN_CFG(0, ALC269_VC_HP_OUT,	AZALIA_PIN_DESC(
-							AZALIA_JACK,
-							AZALIA_EXTERNAL_PRIMARY_CHASSIS | AZALIA_RIGHT,
-							AZALIA_HP_OUT,
-							AZALIA_STEREO_MONO_1_8,
-							AZALIA_BLACK,
-							AZALIA_JACK_PRESENCE_DETECT,
-							2,
-							0
-						)),
-	AZALIA_PIN_CFG(0, ALC269_MIC1,		AZALIA_PIN_DESC(
-							AZALIA_JACK,
-							AZALIA_EXTERNAL_PRIMARY_CHASSIS | AZALIA_RIGHT,
-							AZALIA_MIC_IN,
-							AZALIA_STEREO_MONO_1_8,
-							AZALIA_BLACK,
-							AZALIA_JACK_PRESENCE_DETECT,
-							4,
-							0
-						)),
-	AZALIA_PIN_CFG(0, ALC269_MONO,		AZALIA_PIN_CFG_NC(0)),
-	AZALIA_PIN_CFG(0, ALC269_MIC2,		AZALIA_PIN_CFG_NC(0)),
-	AZALIA_PIN_CFG(0, ALC269_LINE1,		AZALIA_PIN_CFG_NC(0)),
-	AZALIA_PIN_CFG(0, ALC269_LINE2,		AZALIA_PIN_CFG_NC(0)),
-	AZALIA_PIN_CFG(0, ALC269_PC_BEEP,	AZALIA_PIN_CFG_NC(0)),
-	AZALIA_PIN_CFG(0, ALC269_SPDIF_OUT,	AZALIA_PIN_CFG_NC(0)),
-	AZALIA_PIN_CFG(0, ALC269_VB_HP_OUT,	AZALIA_PIN_CFG_NC(0)),
-
-	/* ALC269 Default 1 */
-	0x02050018,
-	0x02040184,
-	0x0205001c,
-	0x02044800,
-	/* ALC269 Default 2 */
-	0x02050024,
-	0x02040000,
-	0x02050004,
-	0x02040080,
-	/* ALC269 Default 3 */
-	0x02050008,
-	0x02040000,
-	0x0205000c,
-	0x02043f00,
-	/* ALC269 Default 4 */
-	0x02050015,
-	0x02048002,
-	0x02050015,
-	0x02048002,
-	/* Widget 0x0c */
-	0x00c37080,
-	0x00270610,
-	0x00d37080,
-	0x00370610,
-};
-
-const u32 pc_beep_verbs[] = {
-};
-
-AZALIA_ARRAY_SIZES;
diff --git a/src/mainboard/starlabs/starlite_adl/vboot.c b/src/mainboard/starlabs/starlite_adl/vboot.c
deleted file mode 100644
index 8511825004..0000000000
--- a/src/mainboard/starlabs/starlite_adl/vboot.c
+++ /dev/null
@@ -1,8 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-or-later */
-
-#include <bootmode.h>
-
-int get_recovery_mode_switch(void)
-{
-	return 0;
-}

From 14fcb3baf8935cde85e617f5c0afffb04d7b5e4e Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Fri, 27 Feb 2026 21:55:50 +0000
Subject: [PATCH 3540/3886] mainboard/starlabs/adl: move CFR callbacks to
 variant

Move the i5 variant-specific CFR callbacks out of the baseboard
CFR menu and compile them from the variant directory. This
reduces preprocessor usage in the common file.

Change-Id: Ic03ec18aed100a95d347c49c2b1deecf1c3fd961
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91458
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
---
 src/mainboard/starlabs/adl/Makefile.mk       |  1 +
 src/mainboard/starlabs/adl/cfr.c             | 23 --------------------
 src/mainboard/starlabs/adl/variants/i5/cfr.c | 21 ++++++++++++++++++
 3 files changed, 22 insertions(+), 23 deletions(-)
 create mode 100644 src/mainboard/starlabs/adl/variants/i5/cfr.c

diff --git a/src/mainboard/starlabs/adl/Makefile.mk b/src/mainboard/starlabs/adl/Makefile.mk
index ad15bbd510..f42ebef3ab 100644
--- a/src/mainboard/starlabs/adl/Makefile.mk
+++ b/src/mainboard/starlabs/adl/Makefile.mk
@@ -7,4 +7,5 @@ subdirs-y += variants/$(VARIANT_DIR)
 bootblock-y += bootblock.c
 
 ramstage-$(CONFIG_DRIVERS_OPTION_CFR) += cfr.c
+ramstage-$(CONFIG_DRIVERS_OPTION_CFR) += $(wildcard variants/$(VARIANT_DIR)/cfr.c)
 ramstage-y += mainboard.c
diff --git a/src/mainboard/starlabs/adl/cfr.c b/src/mainboard/starlabs/adl/cfr.c
index 74106c295c..cd4a27c302 100644
--- a/src/mainboard/starlabs/adl/cfr.c
+++ b/src/mainboard/starlabs/adl/cfr.c
@@ -5,31 +5,8 @@
 #include <drivers/option/cfr_frontend.h>
 #include <ec/starlabs/merlin/cfr.h>
 #include <intelblocks/cfr.h>
-#if CONFIG(BOARD_STARLABS_LITE_ADL)
-#include <device/i2c_bus.h>
-#include <device/i2c_simple.h>
-#include <option.h>
-#include <static.h>
-#include <variants.h>
-#endif
 #include <common/cfr.h>
 
-#if CONFIG(BOARD_STARLABS_LITE_ADL)
-void cfr_card_reader_update(struct sm_object *new_obj)
-{
-	struct device *mxc_accel = DEV_PTR(mxc6655);
-
-	if (!i2c_dev_detect(i2c_busdev(mxc_accel), mxc_accel->path.i2c.device))
-		new_obj->sm_bool.flags = CFR_OPTFLAG_SUPPRESS;
-}
-
-void cfr_touchscreen_update(struct sm_object *new_obj)
-{
-	if (get_uint_option("accelerometer", 1) == 0)
-		new_obj->sm_bool.flags = CFR_OPTFLAG_SUPPRESS;
-}
-#endif
-
 #if CONFIG(SYSTEM_TYPE_LAPTOP) || CONFIG(SYSTEM_TYPE_DETACHABLE)
 static struct sm_obj_form audio_video_group = {
 	.ui_name = "Audio/Video",
diff --git a/src/mainboard/starlabs/adl/variants/i5/cfr.c b/src/mainboard/starlabs/adl/variants/i5/cfr.c
new file mode 100644
index 0000000000..5593cb5531
--- /dev/null
+++ b/src/mainboard/starlabs/adl/variants/i5/cfr.c
@@ -0,0 +1,21 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <device/i2c_bus.h>
+#include <device/i2c_simple.h>
+#include <drivers/option/cfr_frontend.h>
+#include <option.h>
+#include <static.h>
+
+void cfr_card_reader_update(struct sm_object *new_obj)
+{
+	struct device *mxc_accel = DEV_PTR(mxc6655);
+
+	if (!i2c_dev_detect(i2c_busdev(mxc_accel), mxc_accel->path.i2c.device))
+		new_obj->sm_bool.flags |= CFR_OPTFLAG_SUPPRESS;
+}
+
+void cfr_touchscreen_update(struct sm_object *new_obj)
+{
+	if (get_uint_option("accelerometer", 1) == 0)
+		new_obj->sm_bool.flags |= CFR_OPTFLAG_SUPPRESS;
+}

From ffad2454c43030832993495bc85733524441cdac Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Fri, 27 Feb 2026 21:56:53 +0000
Subject: [PATCH 3541/3886] mainboard/starlabs/adl: drop redundant ASPM CFR
 guard

All Star Labs ADL boards select SOC_INTEL_COMMON_BLOCK_ASPM, so the
additional preprocessor guard in the PCIe CFR form is redundant.

Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: Id7cd4911666c02f88a9c1c5f074ac996744be23d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91459
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/starlabs/adl/cfr.c | 2 --
 1 file changed, 2 deletions(-)

diff --git a/src/mainboard/starlabs/adl/cfr.c b/src/mainboard/starlabs/adl/cfr.c
index cd4a27c302..8c8f5f601f 100644
--- a/src/mainboard/starlabs/adl/cfr.c
+++ b/src/mainboard/starlabs/adl/cfr.c
@@ -88,11 +88,9 @@ static struct sm_obj_form pcie_power_management_group = {
 	.ui_name = "PCIe Power Management",
 	.obj_list =
 		(const struct sm_object *[]){
-#if CONFIG(SOC_INTEL_COMMON_BLOCK_ASPM)
 					     &pciexp_aspm,
 					     &pciexp_clk_pm,
 					     &pciexp_l1ss,
-#endif
 					     NULL, },
 };
 

From 5156ec45330744654f6b5a0fa19bec44ddab2034 Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Fri, 27 Feb 2026 21:57:29 +0000
Subject: [PATCH 3542/3886] mainboard/starlabs/adl: move SSDT hook to variant

Replace the BOARD_STARLABS_LITE_ADL preprocessor hook with a
weak baseboard function and provide the StarLite-specific SSDT
generator from the i5 variant directory.

Change-Id: Iea1a27fe1bf86bf970bd7021135760d8a1bc75a1
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91460
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/starlabs/adl/include/variants.h |  3 +++
 src/mainboard/starlabs/adl/mainboard.c        | 19 +++----------------
 .../starlabs/adl/variants/i5/Makefile.mk      |  1 +
 .../starlabs/adl/variants/i5/mainboard_ssdt.c | 16 ++++++++++++++++
 4 files changed, 23 insertions(+), 16 deletions(-)
 create mode 100644 src/mainboard/starlabs/adl/variants/i5/mainboard_ssdt.c

diff --git a/src/mainboard/starlabs/adl/include/variants.h b/src/mainboard/starlabs/adl/include/variants.h
index c95d15bd72..536ac891ae 100644
--- a/src/mainboard/starlabs/adl/include/variants.h
+++ b/src/mainboard/starlabs/adl/include/variants.h
@@ -3,6 +3,7 @@
 #ifndef _BASEBOARD_VARIANTS_H_
 #define _BASEBOARD_VARIANTS_H_
 
+#include <device/device.h>
 #include <soc/gpio.h>
 
 /*
@@ -14,4 +15,6 @@ const struct pad_config *variant_early_gpio_table(size_t *num);
 
 void devtree_update(void);
 
+void starlabs_adl_mainboard_fill_ssdt(const struct device *dev);
+
 #endif /* _BASEBOARD_VARIANTS_H_ */
diff --git a/src/mainboard/starlabs/adl/mainboard.c b/src/mainboard/starlabs/adl/mainboard.c
index 8a3dadbc48..f8c9aea3ae 100644
--- a/src/mainboard/starlabs/adl/mainboard.c
+++ b/src/mainboard/starlabs/adl/mainboard.c
@@ -1,14 +1,8 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
-#if CONFIG(BOARD_STARLABS_LITE_ADL)
-#include <acpi/acpigen_ps2_keybd.h>
-#include <commonlib/helpers.h>
-#endif
-
 #include <device/device.h>
 #include <drivers/intel/gma/opregion.h>
 #include <soc/ramstage.h>
-#include <option.h>
 #include <variants.h>
 
 static void init_mainboard(void *chip_info)
@@ -22,21 +16,14 @@ static void init_mainboard(void *chip_info)
 	devtree_update();
 }
 
-#if CONFIG(BOARD_STARLABS_LITE_ADL)
-static void mainboard_fill_ssdt(const struct device *dev)
+void __weak starlabs_adl_mainboard_fill_ssdt(const struct device *dev)
 {
-	enum ps2_action_key ps2_action_keys[2] = {PS2_KEY_VOL_DOWN, PS2_KEY_VOL_UP};
-
-	acpigen_ps2_keyboard_dsd("_SB.PCI0.PS2K", ARRAY_SIZE(ps2_action_keys), ps2_action_keys,
-				 false, false, false, false, false);
+	(void)dev;
 }
-#endif
 
 static void enable_mainboard(struct device *dev)
 {
-#if CONFIG(BOARD_STARLABS_LITE_ADL)
-	dev->ops->acpi_fill_ssdt = mainboard_fill_ssdt;
-#endif
+	dev->ops->acpi_fill_ssdt = starlabs_adl_mainboard_fill_ssdt;
 }
 
 struct chip_operations mainboard_ops = {
diff --git a/src/mainboard/starlabs/adl/variants/i5/Makefile.mk b/src/mainboard/starlabs/adl/variants/i5/Makefile.mk
index bfea7ef255..d6e2d5b29d 100644
--- a/src/mainboard/starlabs/adl/variants/i5/Makefile.mk
+++ b/src/mainboard/starlabs/adl/variants/i5/Makefile.mk
@@ -7,6 +7,7 @@ romstage-y += romstage.c
 ramstage-y += devtree.c
 ramstage-y += gpio.c
 ramstage-y += hda_verb.c
+ramstage-y += mainboard_ssdt.c
 ramstage-y += ramstage.c
 
 $(call add_vbt_to_cbfs, vbt_native_res.bin, data_native_res.vbt)
diff --git a/src/mainboard/starlabs/adl/variants/i5/mainboard_ssdt.c b/src/mainboard/starlabs/adl/variants/i5/mainboard_ssdt.c
new file mode 100644
index 0000000000..a58becd7f6
--- /dev/null
+++ b/src/mainboard/starlabs/adl/variants/i5/mainboard_ssdt.c
@@ -0,0 +1,16 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <acpi/acpigen_ps2_keybd.h>
+#include <commonlib/helpers.h>
+#include <device/device.h>
+#include <variants.h>
+
+void starlabs_adl_mainboard_fill_ssdt(const struct device *dev)
+{
+	enum ps2_action_key ps2_action_keys[2] = { PS2_KEY_VOL_DOWN, PS2_KEY_VOL_UP };
+
+	(void)dev;
+
+	acpigen_ps2_keyboard_dsd("_SB.PCI0.PS2K", ARRAY_SIZE(ps2_action_keys), ps2_action_keys,
+				 false, false, false, false, false);
+}

From 724176a218304c930aa0360bf976b3d000335571 Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Fri, 27 Feb 2026 21:58:04 +0000
Subject: [PATCH 3543/3886] mainboard/starlabs: namespace PL4 powercap setting

Rename the PL4 powercap Kconfig symbol to MB_STARLABS_PL4_WATTS
and update the common powercap logic to use the namespaced
option.

Change-Id: If36d087accc13a03eac4715948a4ca47bd70c3c4
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91461
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/starlabs/adl/Kconfig                | 2 +-
 src/mainboard/starlabs/common/powercap/powercap.c | 2 +-
 src/mainboard/starlabs/lite/Kconfig               | 2 +-
 src/mainboard/starlabs/starbook/Kconfig           | 2 +-
 src/mainboard/starlabs/starfighter/Kconfig        | 2 +-
 5 files changed, 5 insertions(+), 5 deletions(-)

diff --git a/src/mainboard/starlabs/adl/Kconfig b/src/mainboard/starlabs/adl/Kconfig
index 569274f9e6..ebe225fd76 100644
--- a/src/mainboard/starlabs/adl/Kconfig
+++ b/src/mainboard/starlabs/adl/Kconfig
@@ -171,7 +171,7 @@ endif # BOARD_STARLABS_ADL_HORIZON || BOARD_STARLABS_LITE_ADL
 
 if BOARD_STARLABS_BYTE_ADL || BOARD_STARLABS_BYTE_TWL || BOARD_STARLABS_LITE_ADL
 
-config PL4_WATTS
+config MB_STARLABS_PL4_WATTS
 	int
 	default 65 if BOARD_STARLABS_BYTE_ADL || BOARD_STARLABS_BYTE_TWL
 	default 37 if BOARD_STARLABS_LITE_ADL
diff --git a/src/mainboard/starlabs/common/powercap/powercap.c b/src/mainboard/starlabs/common/powercap/powercap.c
index 2bc7705136..21b879f5cf 100644
--- a/src/mainboard/starlabs/common/powercap/powercap.c
+++ b/src/mainboard/starlabs/common/powercap/powercap.c
@@ -45,7 +45,7 @@ void update_power_limits(config_t *cfg)
 		struct soc_power_limits_config *entry = &limits[i];
 		uint16_t tdp, pl1, pl2;
 
-		entry->tdp_pl4 = (uint16_t)CONFIG_PL4_WATTS;
+		entry->tdp_pl4 = (uint16_t)CONFIG_MB_STARLABS_PL4_WATTS;
 
 		tdp = entry->tdp_pl1_override;
 		if (!tdp)
diff --git a/src/mainboard/starlabs/lite/Kconfig b/src/mainboard/starlabs/lite/Kconfig
index e68e84b397..440b2723fe 100644
--- a/src/mainboard/starlabs/lite/Kconfig
+++ b/src/mainboard/starlabs/lite/Kconfig
@@ -87,7 +87,7 @@ config TJ_MAX
 	int
 	default 100
 
-config PL4_WATTS
+config MB_STARLABS_PL4_WATTS
 	int
 	default 45
 
diff --git a/src/mainboard/starlabs/starbook/Kconfig b/src/mainboard/starlabs/starbook/Kconfig
index 063a7c6410..9e517008f7 100644
--- a/src/mainboard/starlabs/starbook/Kconfig
+++ b/src/mainboard/starlabs/starbook/Kconfig
@@ -203,7 +203,7 @@ config TJ_MAX
 	default 105 if BOARD_STARLABS_STARBOOK_ADL_N
 	default 110
 
-config PL4_WATTS
+config MB_STARLABS_PL4_WATTS
 	int
 	default 45 if BOARD_STARLABS_LABTOP_KBL || BOARD_STARLABS_LABTOP_CML
 	default 65
diff --git a/src/mainboard/starlabs/starfighter/Kconfig b/src/mainboard/starlabs/starfighter/Kconfig
index 5709ced88c..78c2667832 100644
--- a/src/mainboard/starlabs/starfighter/Kconfig
+++ b/src/mainboard/starlabs/starfighter/Kconfig
@@ -126,7 +126,7 @@ config TJ_MAX
 	int
 	default 110
 
-config PL4_WATTS
+config MB_STARLABS_PL4_WATTS
 	int
 	default 80
 

From dde872911a06d868e0643379e2f8532c141308f3 Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Fri, 27 Feb 2026 21:58:27 +0000
Subject: [PATCH 3544/3886] mainboard/starlabs: drop unused TJ_MAX option

The TJ_MAX Kconfig option isn't referenced anywhere in-tree. Drop
the\nunused setting to avoid confusion and keep the Kconfig clean.

Change-Id: I56a5c287be5ed61094b4c006a9661ee9b46b6d36
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91462
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/starlabs/adl/Kconfig         | 4 ----
 src/mainboard/starlabs/lite/Kconfig        | 4 ----
 src/mainboard/starlabs/starbook/Kconfig    | 6 ------
 src/mainboard/starlabs/starfighter/Kconfig | 4 ----
 4 files changed, 18 deletions(-)

diff --git a/src/mainboard/starlabs/adl/Kconfig b/src/mainboard/starlabs/adl/Kconfig
index ebe225fd76..50d56bfa98 100644
--- a/src/mainboard/starlabs/adl/Kconfig
+++ b/src/mainboard/starlabs/adl/Kconfig
@@ -176,10 +176,6 @@ config MB_STARLABS_PL4_WATTS
 	default 65 if BOARD_STARLABS_BYTE_ADL || BOARD_STARLABS_BYTE_TWL
 	default 37 if BOARD_STARLABS_LITE_ADL
 
-config TJ_MAX
-	int
-	default 105 if BOARD_STARLABS_LITE_ADL
-
 config VBOOT
 	select VBOOT_VBNV_FLASH
 
diff --git a/src/mainboard/starlabs/lite/Kconfig b/src/mainboard/starlabs/lite/Kconfig
index 440b2723fe..1b03c054b2 100644
--- a/src/mainboard/starlabs/lite/Kconfig
+++ b/src/mainboard/starlabs/lite/Kconfig
@@ -83,10 +83,6 @@ config MAINBOARD_SMBIOS_PRODUCT_NAME
 config POWER_STATE_DEFAULT_ON_AFTER_FAILURE
 	default n
 
-config TJ_MAX
-	int
-	default 100
-
 config MB_STARLABS_PL4_WATTS
 	int
 	default 45
diff --git a/src/mainboard/starlabs/starbook/Kconfig b/src/mainboard/starlabs/starbook/Kconfig
index 9e517008f7..cb9bccd3a4 100644
--- a/src/mainboard/starlabs/starbook/Kconfig
+++ b/src/mainboard/starlabs/starbook/Kconfig
@@ -197,12 +197,6 @@ config POWER_STATE_DEFAULT_ON_AFTER_FAILURE
 config SOC_INTEL_CSE_SEND_EOP_EARLY
 	default n
 
-config TJ_MAX
-	int
-	default 100 if BOARD_STARLABS_LABTOP_KBL || BOARD_STARLABS_LABTOP_CML || BOARD_STARLABS_STARBOOK_TGL
-	default 105 if BOARD_STARLABS_STARBOOK_ADL_N
-	default 110
-
 config MB_STARLABS_PL4_WATTS
 	int
 	default 45 if BOARD_STARLABS_LABTOP_KBL || BOARD_STARLABS_LABTOP_CML
diff --git a/src/mainboard/starlabs/starfighter/Kconfig b/src/mainboard/starlabs/starfighter/Kconfig
index 78c2667832..f32a9a8153 100644
--- a/src/mainboard/starlabs/starfighter/Kconfig
+++ b/src/mainboard/starlabs/starfighter/Kconfig
@@ -122,10 +122,6 @@ config SOC_INTEL_CSE_SEND_EOP_EARLY
 config TME_KEY_REGENERATION_ON_WARM_BOOT
 	default n
 
-config TJ_MAX
-	int
-	default 110
-
 config MB_STARLABS_PL4_WATTS
 	int
 	default 80

From 0a6142dfbe4b81442e4e307ccd087759aae5a4a0 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Micha=C5=82=20=C5=BBygowski?= <michal.zygowski@3mdeb.com>
Date: Tue, 16 Sep 2025 08:22:41 +0200
Subject: [PATCH 3545/3886] soc/amd/turin_poc: Add SPI TPM SoC-specific
 initialization
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Add the SoC hook to initialize SPI TPM decoding. Without the additional
programming an attempt to talk to SPI TPM hangs the platform when the
TPM_MEASURED_BOOT_INIT_BOOTBLOCK is set. If TPM is initialized in
ramstage, the OpenSIL programs the SPI TPM decoding properly and the
issue is not observed.

TEST=Select TPM_MEASURED_BOOT_INIT_BOOTBLOCK and enable
TPM_MEASURED_BOOT on Gigabyte MZ33-AR1, and observe the platform does
not hang in bootblock.

Change-Id: I2e6c0aad31fd0335e0d16111ed4894a12d2ba497
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89192
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
---
 src/soc/amd/turin_poc/Makefile.mk |  3 +++
 src/soc/amd/turin_poc/lpc.c       | 11 +++++++++++
 2 files changed, 14 insertions(+)
 create mode 100644 src/soc/amd/turin_poc/lpc.c

diff --git a/src/soc/amd/turin_poc/Makefile.mk b/src/soc/amd/turin_poc/Makefile.mk
index 68144574c2..5cbcbea405 100644
--- a/src/soc/amd/turin_poc/Makefile.mk
+++ b/src/soc/amd/turin_poc/Makefile.mk
@@ -8,6 +8,9 @@ all-y		+= i2c.c
 all-y		+= i3c.c
 all-y		+= uart.c
 
+all-y		+= lpc.c
+smm-y		+= lpc.c
+
 bootblock-y	+= early_fch.c
 bootblock-y	+= aoac.c
 
diff --git a/src/soc/amd/turin_poc/lpc.c b/src/soc/amd/turin_poc/lpc.c
new file mode 100644
index 0000000000..23a32f5de3
--- /dev/null
+++ b/src/soc/amd/turin_poc/lpc.c
@@ -0,0 +1,11 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <amdblocks/lpc.h>
+#include <device/pci.h>
+#include <soc/pci_devs.h>
+
+void soc_lpc_tpm_decode_spi(void)
+{
+	/* SoC-specific SPI TPM setting */
+	pci_or_config32(SOC_LPC_DEV, 0xdc, 1);
+}

From 6de3d04c4e57e5ffc49d6e9a37366adc4e3e7af2 Mon Sep 17 00:00:00 2001
From: Subrata Banik <subratabanik@google.com>
Date: Sat, 28 Feb 2026 17:16:16 +0530
Subject: [PATCH 3546/3886] Kconfig: Add Kconfig for signed secure blobs

Adds QC_SECURE_BOOT_BLOBS to enable inclusion of OEM-signed components
for fused Qualcomm hardware. Depends on USE_QC_BLOBS.

BUG=b:488573654
TEST=Able to build google/quenbih.

Change-Id: Id08d83fc82c9441560b1afaa333b3b7fd5a9bfca
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91475
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
---
 src/Kconfig | 19 +++++++++++++++++++
 1 file changed, 19 insertions(+)

diff --git a/src/Kconfig b/src/Kconfig
index 2dad082a08..dfd703630c 100644
--- a/src/Kconfig
+++ b/src/Kconfig
@@ -360,6 +360,25 @@ config USE_QC_BLOBS
 	  mainboards cannot be built and will be hidden from the "Mainboards"
 	  section.
 
+config QC_SECURE_BOOT_BLOBS
+	bool "Enable Qualcomm secure/signed blobs for fused SoCs"
+	depends on USE_QC_BLOBS
+	help
+	  This option enables the inclusion of OEM-signed binaries and
+	  secure-world components required for booting fused Qualcomm SoCs.
+
+	  When enabled, the build system will look for signed versions of
+	  QcLib, QC-SEC, and secondary bootloader stages that match the
+	  Root of Trust (RoT) fused into the SoC.
+
+	  Select this if you are building firmware for production hardware
+	  or "fused" development units that enforce OEM signature
+	  verification at the hardware level.
+
+	  Note: Using this option without the correct signing keys or
+	  signed blobs will result in a bricked boot process on fused
+	  hardware.
+
 config COVERAGE
 	bool "Code coverage support"
 	depends on COMPILER_GCC

From 125d9c8643928e924e3cc890d96350743aff4b6b Mon Sep 17 00:00:00 2001
From: Subrata Banik <subratabanik@google.com>
Date: Sat, 28 Feb 2026 17:17:39 +0530
Subject: [PATCH 3547/3886] soc/qualcomm/x1p42100: Add logic for secure boot
 blob paths

Differentiate between secure and non-secure X1P42100 blobs in the
Makefile. Uses CONFIG_QC_SECURE_BOOT_BLOBS to select the appropriate
binary directory `BLOB_VARIANT`.

BUG=b:488573654
TEST=Able to build google/quenbih.

Change-Id: I149960b8b6b1f823df78acccfbd0ff9d3f9124e0
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91476
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
---
 src/soc/qualcomm/x1p42100/Makefile.mk | 25 +++++++++++++++----------
 1 file changed, 15 insertions(+), 10 deletions(-)

diff --git a/src/soc/qualcomm/x1p42100/Makefile.mk b/src/soc/qualcomm/x1p42100/Makefile.mk
index 2881e90350..68eff9a46b 100644
--- a/src/soc/qualcomm/x1p42100/Makefile.mk
+++ b/src/soc/qualcomm/x1p42100/Makefile.mk
@@ -67,9 +67,14 @@ CPPFLAGS_common += -Isrc/soc/qualcomm/common/include
 # look for QC blobs if QC SoC blobs are only available in upstream else ignore
 ifeq ($(CONFIG_QC_BLOBS_UPSTREAM),y)
 ifeq ($(CONFIG_USE_QC_BLOBS),y)
-# TODO: Upload X1P42100 SoC blobs
 X1P42100_BLOB := $(top)/3rdparty/qc_blobs/x1p42100
 
+ifeq ($(CONFIG_QC_SECURE_BOOT_BLOBS),y)
+BLOB_VARIANT := secure
+else
+BLOB_VARIANT := non_secure
+endif
+
 ifeq ($(CONFIG_SOC_QUALCOMM_HAMOA),y)
 DTB_DCB_BLOB_PATH := hamoa
 else
@@ -94,9 +99,9 @@ cbfs-files-y += $(QCSDI_CBFS)
 endif
 
 ################################################################################
-QC_SEC_FILE := $(X1P42100_BLOB)/qc_sec/qc_sec.mbn
-TME_SEQ_FILE := $(X1P42100_BLOB)/tme/sequencer_ram.elf
-TME_FW_FILE := $(X1P42100_BLOB)/tme/signed_firmware_soc_view.elf
+QC_SEC_FILE := $(X1P42100_BLOB)/$(BLOB_VARIANT)/qc_sec/qc_sec.mbn
+TME_SEQ_FILE := $(X1P42100_BLOB)/$(BLOB_VARIANT)/tme/sequencer_ram.elf
+TME_FW_FILE := $(X1P42100_BLOB)/$(BLOB_VARIANT)/tme/signed_firmware_soc_view.elf
 
 $(objcbfs)/bootblock.bin: $(objcbfs)/bootblock.raw.elf
 	@util/qualcomm/createxbl.py --mbn_version 7 -f $(objcbfs)/bootblock.raw.elf \
@@ -165,7 +170,7 @@ $(I2C_FW_CBFS)-compression := none
 cbfs-files-y += $(I2C_FW_CBFS)
 
 ################################################################################
-AOP_FILE := $(X1P42100_BLOB)/aop/aop.mbn
+AOP_FILE := $(X1P42100_BLOB)/$(BLOB_VARIANT)/aop/aop.mbn
 AOP_CBFS := $(CONFIG_CBFS_PREFIX)/aop
 $(AOP_CBFS)-file := $(AOP_FILE)
 $(AOP_CBFS)-type := payload
@@ -175,7 +180,7 @@ cbfs-files-y += $(AOP_CBFS)
 ################################################################################
 # Rule to create aop_meta from aop.mbn
 # This rule depends on aop.mbn built and the extractor script existing.
-$(obj)/mainboard/$(MAINBOARDDIR)/aop_meta: $(X1P42100_BLOB)/aop/aop.mbn util/qualcomm/elf_segment_extractor.py
+$(obj)/mainboard/$(MAINBOARDDIR)/aop_meta: $(X1P42100_BLOB)/$(BLOB_VARIANT)/aop/aop.mbn util/qualcomm/elf_segment_extractor.py
 	@echo "Extracting ELF headers and hash table segment from $< to $@"
 	@util/qualcomm/elf_segment_extractor.py --eh --pht --hashtable $< $@
 
@@ -187,7 +192,7 @@ $(AOP_META_CBFS)-compression := $(CBFS_COMPRESS_FLAG)
 cbfs-files-y += $(AOP_META_CBFS)
 
 ################################################################################
-AOP_CFG_FILE := $(X1P42100_BLOB)/aop/aop_devcfg.mbn
+AOP_CFG_FILE := $(X1P42100_BLOB)/$(BLOB_VARIANT)/aop/aop_devcfg.mbn
 AOP_CFG_CBFS := $(CONFIG_CBFS_PREFIX)/aop_cfg
 $(AOP_CFG_CBFS)-file := $(AOP_CFG_FILE)
 $(AOP_CFG_CBFS)-type := payload
@@ -197,7 +202,7 @@ cbfs-files-y += $(AOP_CFG_CBFS)
 ################################################################################
 # Rule to create aop_meta from aop_devcfg.mbn
 # This rule depends on aop_devcfg.mbn built and the extractor script existing.
-$(obj)/mainboard/$(MAINBOARDDIR)/aop_devcfg_meta: $(X1P42100_BLOB)/aop/aop_devcfg.mbn util/qualcomm/elf_segment_extractor.py
+$(obj)/mainboard/$(MAINBOARDDIR)/aop_devcfg_meta: $(X1P42100_BLOB)/$(BLOB_VARIANT)/aop/aop_devcfg.mbn util/qualcomm/elf_segment_extractor.py
 	@echo "Extracting ELF headers and hash table segment from $< to $@"
 	@util/qualcomm/elf_segment_extractor.py --eh --pht --hashtable $< $@
 
@@ -239,7 +244,7 @@ $(CPUCP_DTBS_CBFS)-compression := $(CBFS_COMPRESS_FLAG)
 cbfs-files-y += $(CPUCP_DTBS_CBFS)
 
 ################################################################################
-SHRM_FILE := $(X1P42100_BLOB)/shrm/shrm.elf
+SHRM_FILE := $(X1P42100_BLOB)/$(BLOB_VARIANT)/shrm/shrm.elf
 SHRM_CBFS := $(CONFIG_CBFS_PREFIX)/shrm
 $(SHRM_CBFS)-file := $(SHRM_FILE)
 $(SHRM_CBFS)-type := payload
@@ -249,7 +254,7 @@ cbfs-files-y += $(SHRM_CBFS)
 ################################################################################
 # Rule to create shrm_meta from shrm.elf
 # This rule depends on shrm.elf being built and the extractor script existing.
-$(obj)/mainboard/$(MAINBOARDDIR)/shrm_meta: $(X1P42100_BLOB)/shrm/shrm.elf util/qualcomm/elf_segment_extractor.py
+$(obj)/mainboard/$(MAINBOARDDIR)/shrm_meta: $(X1P42100_BLOB)/$(BLOB_VARIANT)/shrm/shrm.elf util/qualcomm/elf_segment_extractor.py
 	@echo "Extracting ELF headers and hash table segment from $< to $@"
 	@util/qualcomm/elf_segment_extractor.py --eh --pht --hashtable $< $@
 

From a1dd5f05b0b17a0c09da936ea1613088f756d476 Mon Sep 17 00:00:00 2001
From: Subrata Banik <subratabanik@google.com>
Date: Sun, 1 Mar 2026 11:03:09 +0530
Subject: [PATCH 3548/3886] ec/google/chromeec: Add interface for offmode
 heartbeat command

Implement google_chromeec_offmode_heartbeat() to wrap the
EC_CMD_ENABLE_OFFMODE_HEARTBEAT host command.

This allows the AP to signal the EC to maintain the power state
required for off-mode UI (such as the charging applet) during
shutdown or low-power transitions.

BUG=b:439819922
BRANCH=none
TEST=Build and verify that the charger applet can successfully
call this function to enable heartbeat signaling.

Change-Id: Ic2ed464bf454e614a098ee5bbbb662adc9d79144
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91484
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
---
 src/ec/google/chromeec/ec.c | 9 +++++++++
 src/ec/google/chromeec/ec.h | 2 ++
 2 files changed, 11 insertions(+)

diff --git a/src/ec/google/chromeec/ec.c b/src/ec/google/chromeec/ec.c
index ab4df3dde2..5b89dac265 100644
--- a/src/ec/google/chromeec/ec.c
+++ b/src/ec/google/chromeec/ec.c
@@ -795,6 +795,15 @@ int rtc_get(struct rtc_time *time)
 }
 #endif
 
+int google_chromeec_offmode_heartbeat(void)
+{
+	struct chromeec_command cmd = {
+		.cmd_code = EC_CMD_ENABLE_OFFMODE_HEARTBEAT,
+	};
+
+	return google_chromeec_command(&cmd);
+}
+
 int google_chromeec_reboot(enum ec_reboot_cmd type, uint8_t flags)
 {
 	const struct ec_params_reboot_ec params = {
diff --git a/src/ec/google/chromeec/ec.h b/src/ec/google/chromeec/ec.h
index 73ec3eeda8..aadd51ff22 100644
--- a/src/ec/google/chromeec/ec.h
+++ b/src/ec/google/chromeec/ec.h
@@ -110,6 +110,8 @@ int google_chromeec_reboot(enum ec_reboot_cmd type, uint8_t flags);
 
 void google_chromeec_ap_poweroff(void);
 
+int google_chromeec_offmode_heartbeat(void);
+
 /**
  * Get data from Cros Board Info
  *

From 12710eafff6612a71c5efa9bed0a67e04d7137df Mon Sep 17 00:00:00 2001
From: Subrata Banik <subratabanik@google.com>
Date: Sun, 1 Mar 2026 11:04:34 +0530
Subject: [PATCH 3549/3886] mb/google/bluey: Implement off-mode charging applet

Add launch_charger_applet() to handle the system state when booting
in off-mode charging or low-power modes with a charger present.

Key features:
1. Monitoring: Periodically checks battery current (I-current) via
   SPMI/PMIC registers.
2. Event Handling: Detects and clears EC power button and lid events.
   If a manual power-on event is detected, the system triggers a
   full board reset to ensure a clean boot to the OS (preventing
   firmware state conflicts like ADSP-lite vs ADSP).
3. Shutdown: If the charger is removed, it signals the EC via
   off-mode heartbeat and initiates an AP power-off.

BUG=b:439819922
BRANCH=None
TEST=Verified that the device enters the charging loop when plugged
in while off, and transitions to a full boot when the power button
is pressed.

Change-Id: I152f71eac89f5b522ea7b286517724e213c31e9a
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91485
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/google/bluey/board.h     |  4 ++
 src/mainboard/google/bluey/charging.c  | 94 ++++++++++++++++++++++++--
 src/mainboard/google/bluey/mainboard.c | 14 ++--
 3 files changed, 100 insertions(+), 12 deletions(-)

diff --git a/src/mainboard/google/bluey/board.h b/src/mainboard/google/bluey/board.h
index d5218b469b..98e34fc64b 100644
--- a/src/mainboard/google/bluey/board.h
+++ b/src/mainboard/google/bluey/board.h
@@ -35,6 +35,9 @@
 #define GPIO_PANEL_POWER_ON	GPIO(70)
 #define GPIO_PANEL_HPD		GPIO(119)
 
+/* Charging GPIOs */
+#define GPIO_PARALLEL_CHARGING_CFG GPIO(71)
+
 /* SD card specific GPIOs. Only for SD-enabled devices. */
 #if CONFIG(MAINBOARD_HAS_SD_CONTROLLER)
 #define GPIO_SD_CD_L		GPIO(71)
@@ -56,5 +59,6 @@ void configure_parallel_charging(void);
 void configure_parallel_charging_late(void);
 void enable_slow_battery_charging(void);
 void disable_slow_battery_charging(void);
+void launch_charger_applet(void);
 
 #endif /* MAINBOARD_GOOGLE_BLUEY_BOARD_H */
diff --git a/src/mainboard/google/bluey/charging.c b/src/mainboard/google/bluey/charging.c
index 5252a1e531..f1af963ec2 100644
--- a/src/mainboard/google/bluey/charging.c
+++ b/src/mainboard/google/bluey/charging.c
@@ -1,6 +1,10 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
 #include "board.h"
+
+#include <delay.h>
+#include <ec/google/chromeec/ec.h>
+#include <reset.h>
 #include <soc/pmic.h>
 #include <soc/qcom_spmi.h>
 #include <types.h>
@@ -16,16 +20,14 @@
 #define SMB2_CHGR_CHRG_EN_CMD ((SMB2_SLAVE_ID << 16) | SCHG_CHGR_CHARGING_ENABLE_CMD)
 #define SMB1_SCHG_TYPE_C_TYPE_C_DEBUG_ACCESS_SNK_CFG \
 ((SMB1_SLAVE_ID << 16) | SCHG_TYPE_C_TYPE_C_DEBUG_ACCESS_SNK_CFG)
+#define SCHG_CHGR_CHARGING_FCC 0x260A
+#define SMB1_CHGR_CHARGING_FCC ((SMB1_SLAVE_ID << 16) | SCHG_CHGR_CHARGING_FCC)
+#define SMB2_CHGR_CHARGING_FCC ((SMB2_SLAVE_ID << 16) | SCHG_CHGR_CHARGING_FCC)
 
 #define FCC_1A_STEP_50MA 0x14
 #define FCC_DISABLE 0x8c
 #define EN_DEBUG_ACCESS_SNK 0x1B
 
-enum charging_status {
-	CHRG_DISABLE,
-	CHRG_ENABLE,
-};
-
 #define PMC8380F_SLAVE_ID	0x05
 #define GPIO07_MODE_CTL			0x8E40
 #define GPIO07_DIG_OUT_SOURCE_CTL	0x8E44
@@ -38,7 +40,87 @@ enum charging_status {
 #define OUTPUT_INVERT		0x80
 #define PERPH_EN		0x80
 
-#define GPIO_PARALLEL_CHARGING_CFG GPIO(71)
+#define DELAY_CHARGING_APPLET_MS 2000 /* 2sec */
+
+enum charging_status {
+	CHRG_DISABLE,
+	CHRG_ENABLE,
+};
+
+static int get_battery_icurr_ma(void)
+{
+	/* Read battery i-current value */
+	int icurr = spmi_read8(SMB1_CHGR_CHARGING_FCC);
+	if (icurr <= 0)
+		icurr = spmi_read8(SMB2_CHGR_CHARGING_FCC);
+	if (icurr < 0)
+		icurr = 0;
+
+	icurr *= 50;
+	return icurr;
+}
+
+static void clear_ec_manual_poweron_event(void)
+{
+	const uint64_t manual_pwron_event_mask =
+		(EC_HOST_EVENT_MASK(EC_HOST_EVENT_POWER_BUTTON) |
+		EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN));
+	google_chromeec_clear_events_b(manual_pwron_event_mask);
+}
+
+static int detect_ec_manual_poweron_event(void)
+{
+	const uint64_t manual_pwron_event_mask =
+		(EC_HOST_EVENT_MASK(EC_HOST_EVENT_POWER_BUTTON) |
+		EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN));
+	uint64_t events = google_chromeec_get_events_b();
+
+	if (!!(events & manual_pwron_event_mask))
+		return 1;
+
+	return 0;
+}
+
+void launch_charger_applet(void)
+{
+	if (!CONFIG(EC_GOOGLE_CHROMEEC))
+		return;
+
+	printk(BIOS_INFO, "Inside %s. Initiating charging\n", __func__);
+
+	/* clear any pending power button press and lid open event */
+	clear_ec_manual_poweron_event();
+
+	do {
+		/* Add static delay before reading the charging applet pre-requisites */
+		mdelay(DELAY_CHARGING_APPLET_MS);
+
+		/*
+		 * Issue a shutdown if not charging.
+		 */
+		if (!get_battery_icurr_ma()) {
+			printk(BIOS_INFO, "Issuing power-off due to change in charging state.\n");
+			google_chromeec_offmode_heartbeat();
+			google_chromeec_ap_poweroff();
+		}
+
+		/*
+		 * Exit the charging loop in the event of lid open or power
+		 * button press.
+		 *
+		 * Reset the device to ensure a fresh boot to OS.
+		 * This is required to avoid any kind of tear-down due to ADSP-lite
+		 * being loaded and need some clean up before loading ADSP firmware by
+		 * linux kernel.
+		 */
+		if (detect_ec_manual_poweron_event()) {
+			printk(BIOS_INFO, "Exiting charging applet to boot to OS\n");
+			do_board_reset();
+		}
+
+		/* TODO: add Tsense support and issue a shutdown in the event of temperature trip */
+	} while (true);
+}
 
 /*
  * Enable PMC8380F GPIO07 & GPIO09 for parallel charging.
diff --git a/src/mainboard/google/bluey/mainboard.c b/src/mainboard/google/bluey/mainboard.c
index 2fc8cfdde9..30cf5b13d8 100644
--- a/src/mainboard/google/bluey/mainboard.c
+++ b/src/mainboard/google/bluey/mainboard.c
@@ -121,12 +121,6 @@ void lb_add_boot_mode(struct lb_header *header)
 	mode->tag = LB_TAG_BOOT_MODE;
 	mode->size = sizeof(*mode);
 	mode->boot_mode = get_boot_mode();
-
-	configure_parallel_charging_late();
-
-	/* Enable charging only during off-mode or low-battery mode with charger present */
-	if (is_low_power_boot_with_charger())
-		enable_slow_battery_charging();
 }
 
 bool mainboard_needs_pcie_init(void)
@@ -177,14 +171,22 @@ static void mainboard_init(struct device *dev)
 	if (get_boot_mode() == LB_BOOT_MODE_LOW_BATTERY)
 		trigger_critical_battery_shutdown();
 
+	configure_parallel_charging_late();
+
 	/* Skip mainboard initialization if boot mode is "low-battery" or "off-mode charging" */
 	if (is_low_power_boot_with_charger()) {
+		/* TODO: enable fast charging */
+		enable_slow_battery_charging();
+
 		/* Disable the lightbar for Low-Battery or Off-Mode charging sequences.
 		 * This maintains visual consistency between the built-in display
 		 * indicators and the external lightbar.
 		 */
 		if (CONFIG(EC_GOOGLE_CHROMEEC))
 			google_chromeec_lightbar_off();
+
+		/* Boot to charging applet */
+		launch_charger_applet();
 		return;
 	}
 

From fe506bfe8494cbfddaa83406deafc4bcc85f600b Mon Sep 17 00:00:00 2001
From: Subrata Banik <subratabanik@google.com>
Date: Sat, 28 Feb 2026 19:39:31 +0530
Subject: [PATCH 3550/3886] ec/google/chromeec: Add Kconfig for AP-controlled
 LED sync

Introduce EC_GOOGLE_CHROMEEC_LED_CONTROL to allow boards to opt-in to
manual LED/lightbar synchronization. This ensures that the AP firmware
can coordinate the lightbar state with boot animations or specific
power states (like critical battery alerts) without forcing the logic
on all ChromeEC-based platforms.

On Bluey, the lightbar logic is refactored into a helper function
`platform_init_lightbar()` to improve readability and is now gated
by the new Kconfig. Similar gating is applied to Fatcat's romstage.

Summary of changes:
- Add EC_GOOGLE_CHROMEEC_LED_CONTROL Kconfig option.
- Bluey: Refactor lightbar init into a helper and gate by Kconfig.
- Fatcat: Gate early lightbar initialization by Kconfig.

Change-Id: I6b0294b73b8b9929a6be0e15bf64f7e688b7da8c
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91477
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
---
 src/ec/google/chromeec/Kconfig         |  6 ++++++
 src/mainboard/google/bluey/mainboard.c |  2 +-
 src/mainboard/google/bluey/romstage.c  | 17 ++++++++++++-----
 src/mainboard/google/fatcat/romstage.c |  2 +-
 4 files changed, 20 insertions(+), 7 deletions(-)

diff --git a/src/ec/google/chromeec/Kconfig b/src/ec/google/chromeec/Kconfig
index b09c64a88c..081f7cb754 100644
--- a/src/ec/google/chromeec/Kconfig
+++ b/src/ec/google/chromeec/Kconfig
@@ -261,6 +261,12 @@ config EC_GOOGLE_CHROMEEC_BATTERY_SOC_DYNAMIC
 	  which retrieves cached telemetry from the EC rather than triggering
 	  a synchronous bus transaction to the battery.
 
+config EC_GOOGLE_CHROMEEC_LED_CONTROL
+	bool
+	help
+	  Enable manual AP control over ChromeEC LEDs/lightbars to ensure
+	  visual continuity with AP-side boot animations.
+
 endif # EC_GOOGLE_CHROMEEC
 
 source "src/ec/google/chromeec/*/Kconfig"
diff --git a/src/mainboard/google/bluey/mainboard.c b/src/mainboard/google/bluey/mainboard.c
index 30cf5b13d8..223daf89c8 100644
--- a/src/mainboard/google/bluey/mainboard.c
+++ b/src/mainboard/google/bluey/mainboard.c
@@ -182,7 +182,7 @@ static void mainboard_init(struct device *dev)
 		 * This maintains visual consistency between the built-in display
 		 * indicators and the external lightbar.
 		 */
-		if (CONFIG(EC_GOOGLE_CHROMEEC))
+		if (CONFIG(EC_GOOGLE_CHROMEEC_LED_CONTROL))
 			google_chromeec_lightbar_off();
 
 		/* Boot to charging applet */
diff --git a/src/mainboard/google/bluey/romstage.c b/src/mainboard/google/bluey/romstage.c
index a415228e8b..891809f045 100644
--- a/src/mainboard/google/bluey/romstage.c
+++ b/src/mainboard/google/bluey/romstage.c
@@ -124,23 +124,30 @@ static void early_setup_usb(void)
 	early_setup_usb_typec();
 }
 
-void platform_romstage_main(void)
+static void platform_init_lightbar(void)
 {
+	if (!CONFIG(EC_GOOGLE_CHROMEEC_LED_CONTROL))
+		return;
+
 	/*
 	 * Early initialization of the Chrome EC lightbar.
 	 * Ensures visual continuity if the AP firmware disabled the lightbar
 	 * in a previous boot without a subsequent EC reset.
 	 */
-	if (CONFIG(EC_GOOGLE_CHROMEEC))
-		google_chromeec_lightbar_on();
+	google_chromeec_lightbar_on();
 
 	/*
 	 * Only alert the user (set LED to red in color) if the lid is closed and the battery
 	 * is critically low without AC power.
 	 */
-	if (CONFIG(EC_GOOGLE_CHROMEEC) && CONFIG(VBOOT_LID_SWITCH) && !get_lid_switch() &&
-			 google_chromeec_is_critically_low_on_battery())
+	if (CONFIG(VBOOT_LID_SWITCH) && !get_lid_switch() &&
+	    google_chromeec_is_critically_low_on_battery())
 		google_chromeec_set_lightbar_rgb(0xff, 0xff, 0x00, 0x00);
+}
+
+void platform_romstage_main(void)
+{
+	platform_init_lightbar();
 
 	/* Setup early USB related config */
 	early_setup_usb();
diff --git a/src/mainboard/google/fatcat/romstage.c b/src/mainboard/google/fatcat/romstage.c
index 5098cd3d8b..04b39c58c4 100644
--- a/src/mainboard/google/fatcat/romstage.c
+++ b/src/mainboard/google/fatcat/romstage.c
@@ -53,7 +53,7 @@ void platform_romstage_pre_mem(void)
 	 * Ensures visual continuity if the AP firmware disabled the lightbar
 	 * in a previous boot without a subsequent EC reset.
 	 */
-	if (CONFIG(EC_GOOGLE_CHROMEEC))
+	if (CONFIG(EC_GOOGLE_CHROMEEC_LED_CONTROL))
 		google_chromeec_lightbar_on();
 
 	/*

From 270e84e59fee87c0054645c6aab606254147f06c Mon Sep 17 00:00:00 2001
From: Subrata Banik <subratabanik@google.com>
Date: Sat, 28 Feb 2026 16:10:48 +0530
Subject: [PATCH 3551/3886] vc/chromeos: Provide inline fallbacks for
 Chromebook Plus branding

Currently, mainboards that do not support Google TPM must manually
define stubs for chromeos_device_branded_plus_hard() and
chromeos_device_branded_plus_soft() to satisfy the linker.

Move these stubs into vendorcode/google/chromeos/chromeos.h as static
inline functions when CONFIG(TPM_GOOGLE) is disabled. This reduces
code duplication and allows the removal of redundant stub definitions
in the ptlrvp mainboard.

Change-Id: If270d4815c687a409fec7058c224f987f9e2741a
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91474
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/intel/ptlrvp/intel.c        | 10 ----------
 src/vendorcode/google/chromeos/chromeos.h | 14 ++++++++++++++
 2 files changed, 14 insertions(+), 10 deletions(-)

diff --git a/src/mainboard/intel/ptlrvp/intel.c b/src/mainboard/intel/ptlrvp/intel.c
index 600d1b3bb7..5e0358ec86 100644
--- a/src/mainboard/intel/ptlrvp/intel.c
+++ b/src/mainboard/intel/ptlrvp/intel.c
@@ -23,13 +23,3 @@ int get_recovery_mode_switch(void)
 {
 	return 0;
 }
-
-bool chromeos_device_branded_plus_hard(void)
-{
-	return false;
-}
-
-bool chromeos_device_branded_plus_soft(void)
-{
-	return false;
-}
diff --git a/src/vendorcode/google/chromeos/chromeos.h b/src/vendorcode/google/chromeos/chromeos.h
index 540f3635aa..d8f7e6117c 100644
--- a/src/vendorcode/google/chromeos/chromeos.h
+++ b/src/vendorcode/google/chromeos/chromeos.h
@@ -34,6 +34,8 @@ void chromeos_set_ramoops(void *ram_oops, size_t size);
  * Return "UNDEFINED_FACTORY_CONFIG" in case of error.
  */
 uint64_t chromeos_get_factory_config(void);
+
+#if CONFIG(TPM_GOOGLE)
 /*
  * Determines whether a ChromeOS device is branded as a Chromebook-Plus
  * based on specific bit flags:
@@ -57,6 +59,18 @@ bool chromeos_device_branded_plus_hard(void);
  * To be considered a soft-branded Chromebook-Plus, both of these conditions need to be met.
  */
 bool chromeos_device_branded_plus_soft(void);
+#else
+/* Inline fallback for platforms without Google TPM */
+static inline bool chromeos_device_branded_plus_hard(void)
+{
+	return false;
+}
+
+static inline bool chromeos_device_branded_plus_soft(void)
+{
+	return false;
+}
+#endif
 
 /*
  * Declaration for mainboards to use to generate ACPI-specific ChromeOS needs.

From 10f0a8782433a18d80bc342495f9cad2d744a89f Mon Sep 17 00:00:00 2001
From: Subrata Banik <subratabanik@google.com>
Date: Mon, 2 Mar 2026 09:46:11 +0530
Subject: [PATCH 3552/3886] soc/qualcomm/sc7280: Update console message type
 non-fatal

This patch updates console message type non-fatal from BIOS_ERR to
BIOS_INFO as appropriate.

Change-Id: I7940b5f0457388d6c5786c9cd490078065e953a4
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91501
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
---
 src/soc/qualcomm/sc7280/display/edp_aux.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/soc/qualcomm/sc7280/display/edp_aux.c b/src/soc/qualcomm/sc7280/display/edp_aux.c
index 9d330a61d1..0f37c21b47 100644
--- a/src/soc/qualcomm/sc7280/display/edp_aux.c
+++ b/src/soc/qualcomm/sc7280/display/edp_aux.c
@@ -179,7 +179,7 @@ int edp_read_edid(struct edid *out)
 	}
 
 	if (edid[EDID_EXTENSION_FLAG]) {
-		printk(BIOS_ERR, " read EDID ext block.\n");
+		printk(BIOS_INFO, " read EDID ext block.\n");
 		edid_size += EDID_LENGTH;
 		reg_addr = EDID_LENGTH;
 		err = edp_aux_transfer(EDID_I2C_ADDR, DP_AUX_I2C_WRITE, &reg_addr, 1);

From 2c5840233939e9fc0bf581a295806cca0456a816 Mon Sep 17 00:00:00 2001
From: Kapil Porwal <kapilporwal@google.com>
Date: Mon, 2 Mar 2026 18:53:11 +0530
Subject: [PATCH 3553/3886] soc/qualcomm/x1p42100: Configure OTG buck for USB
 host

Set the SCHG_DCDC_OTG_CFG register to 0x26 during USB initialization
to ensure the OTG buck is correctly configured for host mode.

TEST=Verify USB detection in the depthcharge on Google/Quartz.

Change-Id: If76be8b7210fc86f473bfd77eb56718f28f19eae
Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91509
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
---
 src/soc/qualcomm/x1p42100/include/soc/usb/usb.h |  1 +
 src/soc/qualcomm/x1p42100/usb/usb.c             | 13 +++++++++++++
 2 files changed, 14 insertions(+)

diff --git a/src/soc/qualcomm/x1p42100/include/soc/usb/usb.h b/src/soc/qualcomm/x1p42100/include/soc/usb/usb.h
index 8284656cb8..f810944542 100644
--- a/src/soc/qualcomm/x1p42100/include/soc/usb/usb.h
+++ b/src/soc/qualcomm/x1p42100/include/soc/usb/usb.h
@@ -114,6 +114,7 @@
 #define OTG_STATE_ENABLED 0x02
 #define OTG_STATUS_TIMEOUT_MS 20
 #define OTG_STATUS_POLL_DELAY_MS 2
+#define OTG_BUCK_CFG 0x26
 
 /* Type-C register offsets */
 #define SCHG_TYPE_C_TYPE_C_MISC_STATUS 0x2B0B
diff --git a/src/soc/qualcomm/x1p42100/usb/usb.c b/src/soc/qualcomm/x1p42100/usb/usb.c
index 5865a35d01..b135b0a0e9 100644
--- a/src/soc/qualcomm/x1p42100/usb/usb.c
+++ b/src/soc/qualcomm/x1p42100/usb/usb.c
@@ -495,6 +495,15 @@ static bool get_usb_typec_polarity(const struct dwc3_controller_config *config)
 	return (misc_status & CCOUT_INVERT_POLARITY) == CCOUT_INVERT_POLARITY;
 }
 
+/*
+ * Configures OTG buck for host mode
+ * @config: Controller configuration containing SMB slave address
+ */
+static void usb_configure_otg_buck(const struct dwc3_controller_config *config)
+{
+	spmi_write8(SPMI_ADDR(config->smb_slave_addr, SCHG_DCDC_OTG_CFG), OTG_BUCK_CFG);
+}
+
 /* Initialization of DWC3 Core and PHY */
 static void setup_usb_host(struct usb_dwc3_cfg *dwc3)
 {
@@ -587,6 +596,8 @@ static void setup_usb_host(struct usb_dwc3_cfg *dwc3)
 		printk(BIOS_ERR, "SS0 QMP PHY initialization failed\n");
 		high_speed_only_primary = true;
 	}
+	/* Configure OTG buck */
+	usb_configure_otg_buck(&prim_config);
 	/* Enable VBUS for C0 */
 	enable_vbus_ss(&prim_config);
 	udelay(50);
@@ -618,6 +629,8 @@ static void setup_usb_host(struct usb_dwc3_cfg *dwc3)
 		printk(BIOS_ERR, "SS1 QMP PHY initialization failed\n");
 		high_speed_only_secondary = true;
 	}
+	/* Configure OTG buck */
+	usb_configure_otg_buck(&sec_config);
 	/* Enable VBUS for C1 */
 	enable_vbus_ss(&sec_config);
 	udelay(50);

From c222118cbf0507eed08e5a911b5531bed877998a Mon Sep 17 00:00:00 2001
From: Kapil Porwal <kapilporwal@google.com>
Date: Mon, 2 Mar 2026 12:10:51 +0530
Subject: [PATCH 3554/3886] soc/qualcomm/x1p42100: Remove redundant VBUS
 enablement logic

The current VBUS enablement logic was found to be unnecessary for
USB host functionality on x1p42100. Forcing VBUS power via the PMIC's
OTG buck is not required for the current hardware configuration and
could lead to incorrect power state management.

Remove the enable_vbus_ss() function and associated SCHG DCDC
register definitions from the SoC driver. This streamlines the
USB initialization path to focus solely on PHY and controller
setup.

TEST=Verify USB detection in the depthcharge on Google/Quartz.

Change-Id: Ie30878802831419f3d70ea921f7f46a262db99bb
Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91502
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
---
 .../qualcomm/x1p42100/include/soc/usb/usb.h   | 14 -----
 src/soc/qualcomm/x1p42100/usb/usb.c           | 52 -------------------
 2 files changed, 66 deletions(-)

diff --git a/src/soc/qualcomm/x1p42100/include/soc/usb/usb.h b/src/soc/qualcomm/x1p42100/include/soc/usb/usb.h
index f810944542..b6d1ff50dd 100644
--- a/src/soc/qualcomm/x1p42100/include/soc/usb/usb.h
+++ b/src/soc/qualcomm/x1p42100/include/soc/usb/usb.h
@@ -103,25 +103,13 @@
 #define SMB2_SLAVE_ID 0x0A
 
 /* SCHG DCDC register offsets */
-#define SCHG_DCDC_CMD_OTG 0x2740
 #define SCHG_DCDC_OTG_CFG 0x2753
-#define SCHG_DCDC_OTG_STATUS 0x270D
-#define SCHG_DCDC_ENG_SDCDC_CFG7 0x27C7
-#define SCHG_DCDC_ENG_SDCDC_GM_CLOOP_PD_OTG_BUCK_MASK 0x30
-
-/* OTG Status register bit definitions */
-#define OTG_STATE_MASK 0x07
-#define OTG_STATE_ENABLED 0x02
-#define OTG_STATUS_TIMEOUT_MS 20
-#define OTG_STATUS_POLL_DELAY_MS 2
 #define OTG_BUCK_CFG 0x26
 
 /* Type-C register offsets */
 #define SCHG_TYPE_C_TYPE_C_MISC_STATUS 0x2B0B
 #define SCHG_TYPE_C_TYPE_C_SRC_STATUS 0x2B08
 #define SCHG_TYPE_C_TYPE_C_MODE_CFG 0x2B44
-#define TYPEC_VBUS_STATUS_MASK BIT(5)
-#define TYPEC_SNK_SRC_MODE BIT(6)
 #define CCOUT_INVERT_POLARITY 0x03
 
 /* USB Repeater SPMI Tune register offsets */
@@ -152,8 +140,6 @@ int qcom_enable_usb_clk(void);
 void enable_clock_tcsr(void);
 /* Enable TCSR CLKREF */
 void usb_update_refclk_for_core(u32 core_num, bool enable);
-/* Enables VBUS SuperSpeed for specified USB core */
-void enable_vbus_ss(const struct dwc3_controller_config *config);
 /* Reads comprehensive Type-C status from PMIC */
 void usb_typec_status_check(const struct dwc3_controller_config *config);
 /* Performs mainboard-specific USB Type-C configuration */
diff --git a/src/soc/qualcomm/x1p42100/usb/usb.c b/src/soc/qualcomm/x1p42100/usb/usb.c
index b135b0a0e9..afc44e6a5f 100644
--- a/src/soc/qualcomm/x1p42100/usb/usb.c
+++ b/src/soc/qualcomm/x1p42100/usb/usb.c
@@ -598,9 +598,6 @@ static void setup_usb_host(struct usb_dwc3_cfg *dwc3)
 	}
 	/* Configure OTG buck */
 	usb_configure_otg_buck(&prim_config);
-	/* Enable VBUS for C0 */
-	enable_vbus_ss(&prim_config);
-	udelay(50);
 	usb_typec_status_check(&prim_config);
 	mainboard_usb_typec_configure(0, polarity_prim);
 
@@ -631,9 +628,6 @@ static void setup_usb_host(struct usb_dwc3_cfg *dwc3)
 	}
 	/* Configure OTG buck */
 	usb_configure_otg_buck(&sec_config);
-	/* Enable VBUS for C1 */
-	enable_vbus_ss(&sec_config);
-	udelay(50);
 	usb_typec_status_check(&sec_config);
 	mainboard_usb_typec_configure(1, polarity_sec);
 
@@ -685,52 +679,6 @@ void usb_update_refclk_for_core(u32 core_num, bool enable)
 	}
 }
 
-/*
- * enable_vbus_ss - Enables VBUS SuperSpeed for specified USB core
- * @config: Controller configuration containing SMB slave address
- */
-void enable_vbus_ss(const struct dwc3_controller_config *config)
-{
-	u8 slave = config->smb_slave_addr;
-	u8 misc_status, otg_status = 0, otg_state = 0;
-	struct stopwatch sw;
-
-	printk(BIOS_INFO, "Enabling %s VBUS SuperSpeed\n", config->name);
-
-	/* Configure SDCDC CFG7 register before enabling OTG */
-	spmi_write8(SPMI_ADDR(slave, SCHG_DCDC_ENG_SDCDC_CFG7),
-		    SCHG_DCDC_ENG_SDCDC_GM_CLOOP_PD_OTG_BUCK_MASK);
-
-	spmi_write8(SPMI_ADDR(slave, SCHG_DCDC_OTG_CFG), 0x20);
-	spmi_write8(SPMI_ADDR(slave, SCHG_DCDC_CMD_OTG), 0x1);
-
-	/* Check Type-C mode */
-	misc_status = spmi_read8(SPMI_ADDR(slave, SCHG_TYPE_C_TYPE_C_MISC_STATUS));
-
-	/* Check SNK_SRC_MODE bit (bit 6): 0 = SNK, 1 = SRC */
-	if (misc_status & TYPEC_SNK_SRC_MODE) {
-		/* In SRC mode, poll OTG status until enabled */
-		stopwatch_init_msecs_expire(&sw, OTG_STATUS_TIMEOUT_MS);
-		while (!stopwatch_expired(&sw)) {
-			otg_status = spmi_read8(SPMI_ADDR(slave, SCHG_DCDC_OTG_STATUS));
-			otg_state = otg_status & OTG_STATE_MASK;
-
-			if (otg_state == OTG_STATE_ENABLED) {
-				printk(BIOS_INFO, "%s in SRC mode - OTG Status: 0x%02x, State: 0x%02x (OTG Enabled)\n",
-				       config->name, otg_status, otg_state);
-				return;
-			}
-			mdelay(OTG_STATUS_POLL_DELAY_MS);
-		}
-
-		/* Timeout - log final state */
-		printk(BIOS_INFO, "%s in SRC mode - OTG Status: 0x%02x, State: 0x%02x - Timeout after %d ms\n",
-		       config->name, otg_status, otg_state, OTG_STATUS_TIMEOUT_MS);
-	} else {
-		printk(BIOS_INFO, "%s in SNK mode - skipping OTG status read\n", config->name);
-	}
-}
-
 /*
  * usb_typec_status_check - Reads comprehensive Type-C status from PMIC
  * @config: Controller configuration containing SMB slave address

From ca9b46d341daa59109f327b32029d57f44abb02e Mon Sep 17 00:00:00 2001
From: Yidi Lin <yidilin@google.com>
Date: Wed, 25 Feb 2026 19:00:41 +0800
Subject: [PATCH 3555/3886] soc/mediatek: Add common low battery poweroff
 handling

Add a common low battery poweroff implementation in
soc/mediatek/common/low_battery.c. This implementation checks
if a low battery shutdown is needed and triggers a poweroff
via Chrome EC if necessary.

Also enable this for mt8196 in ramstage.

BUG=b:424707341
TEST=The FW draws low battery indicator and powers off the DUT after 5
     seconds.
TEST=Use `elogtool list` and see `Low Battery boot | Power Off`

Change-Id: I2fcd242fbf26bdebc4acfb477c95c381adf645f5
Signed-off-by: Yidi Lin <yidilin@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91431
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Chen-Tsung Hsieh <chentsung@google.com>
---
 src/soc/mediatek/common/low_battery.c | 28 +++++++++++++++++++++++++++
 src/soc/mediatek/mt8196/Makefile.mk   |  1 +
 2 files changed, 29 insertions(+)
 create mode 100644 src/soc/mediatek/common/low_battery.c

diff --git a/src/soc/mediatek/common/low_battery.c b/src/soc/mediatek/common/low_battery.c
new file mode 100644
index 0000000000..7a00341d8e
--- /dev/null
+++ b/src/soc/mediatek/common/low_battery.c
@@ -0,0 +1,28 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <bootsplash.h>
+#include <bootstate.h>
+#include <delay.h>
+#include <ec/google/chromeec/ec.h>
+#include <elog.h>
+#include <halt.h>
+
+void __weak poweroff(void)
+{
+	if (!CONFIG(EC_GOOGLE_CHROMEEC))
+		return;
+	google_chromeec_ap_poweroff();
+}
+
+static void low_battery_poweroff(void *unused)
+{
+	if (!platform_is_low_battery_shutdown_needed())
+		return;
+
+	printk(BIOS_INFO, "%s: powering off...\n", __func__);
+
+	platform_handle_emergency_low_battery();
+	poweroff();
+}
+
+BOOT_STATE_INIT_ENTRY(BS_POST_DEVICE, BS_ON_EXIT, low_battery_poweroff, NULL);
diff --git a/src/soc/mediatek/mt8196/Makefile.mk b/src/soc/mediatek/mt8196/Makefile.mk
index 47f9592bc8..1a6159079e 100644
--- a/src/soc/mediatek/mt8196/Makefile.mk
+++ b/src/soc/mediatek/mt8196/Makefile.mk
@@ -69,6 +69,7 @@ ramstage-y += ../common/early_init.c
 ramstage-y += ../common/emi.c
 ramstage-y += gpueb.c
 ramstage-y += l2c_ops.c
+ramstage-y += ../common/low_battery.c
 ramstage-y += ../common/mcu.c mcupm.c
 ramstage-y += ../common/mmu_operations.c
 ramstage-y += ../common/mtk_mipi_dphy.c mtk_mipi_dphy.c

From fb2e8b5e1e5b5ed1c9926f4304009f207bb51cbc Mon Sep 17 00:00:00 2001
From: Jayvik Desai <jayvik@google.com>
Date: Mon, 2 Mar 2026 14:42:04 +0530
Subject: [PATCH 3556/3886] mainboard/google/bluey: Enable charging debug
 access in common path

The charging debug access port was previously only configured during
slow battery charging. Move this configuration into a dedicated
function, configure_charging_debug_access(), and call it within the
common mainboard_init() path.

This ensures the debug access port is consistently configured during
mainboard initialization, following the same pattern as parallel
charging.

BUG=b:488143407
TEST=Build Bluey/Quartz

Change-Id: Idacffd61834e0700619b240dfe362f3be90badb9
Signed-off-by: Jayvik Desai <jayvik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91505
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
---
 src/mainboard/google/bluey/board.h     |  1 +
 src/mainboard/google/bluey/charging.c  | 15 ++++++++++++---
 src/mainboard/google/bluey/mainboard.c |  1 +
 3 files changed, 14 insertions(+), 3 deletions(-)

diff --git a/src/mainboard/google/bluey/board.h b/src/mainboard/google/bluey/board.h
index 98e34fc64b..0544381e69 100644
--- a/src/mainboard/google/bluey/board.h
+++ b/src/mainboard/google/bluey/board.h
@@ -57,6 +57,7 @@ void setup_chromeos_gpios(void);
 bool is_off_mode(void);
 void configure_parallel_charging(void);
 void configure_parallel_charging_late(void);
+void configure_charging_debug_access(void);
 void enable_slow_battery_charging(void);
 void disable_slow_battery_charging(void);
 void launch_charger_applet(void);
diff --git a/src/mainboard/google/bluey/charging.c b/src/mainboard/google/bluey/charging.c
index f1af963ec2..690f30964f 100644
--- a/src/mainboard/google/bluey/charging.c
+++ b/src/mainboard/google/bluey/charging.c
@@ -139,6 +139,18 @@ void configure_parallel_charging(void)
 	spmi_write8(SPMI_ADDR(PMC8380F_SLAVE_ID, GPIO09_MODE_CTL), MODE_OUTPUT);
 }
 
+/*
+ * Enable SMB1 charging debug access port.
+ */
+void configure_charging_debug_access(void)
+{
+	if (!CONFIG(HAVE_CHARGING_DEBUG_ACCESS_PORT))
+		return;
+
+	printk(BIOS_INFO, "Enable charging debug access port support\n");
+	spmi_write8(SMB1_SCHG_TYPE_C_TYPE_C_DEBUG_ACCESS_SNK_CFG, EN_DEBUG_ACCESS_SNK);
+}
+
 /*
  * Late configuration for parallel charging.
  */
@@ -161,9 +173,6 @@ void enable_slow_battery_charging(void)
 	spmi_write8(SMB2_CHGR_MAX_FCC_CFG, FCC_1A_STEP_50MA);
 	spmi_write8(SMB1_CHGR_CHRG_EN_CMD, CHRG_ENABLE);
 	spmi_write8(SMB2_CHGR_CHRG_EN_CMD, CHRG_ENABLE);
-
-	if (CONFIG(HAVE_CHARGING_DEBUG_ACCESS_PORT))
-		spmi_write8(SMB1_SCHG_TYPE_C_TYPE_C_DEBUG_ACCESS_SNK_CFG, EN_DEBUG_ACCESS_SNK);
 }
 
 /*
diff --git a/src/mainboard/google/bluey/mainboard.c b/src/mainboard/google/bluey/mainboard.c
index 223daf89c8..64212d0e84 100644
--- a/src/mainboard/google/bluey/mainboard.c
+++ b/src/mainboard/google/bluey/mainboard.c
@@ -161,6 +161,7 @@ static void trigger_critical_battery_shutdown(void)
 static void mainboard_init(struct device *dev)
 {
 	configure_parallel_charging();
+	configure_charging_debug_access();
 
 	display_startup();
 

From ba6de6c866e714c304aa3e514f90799ebabf38b3 Mon Sep 17 00:00:00 2001
From: Luca Lai <luca.lai@lcfc.corp-partner.google.com>
Date: Thu, 26 Feb 2026 10:32:13 +0800
Subject: [PATCH 3557/3886] mb/google/fatcat/var/ruby: Set ISH GP1 gpio pin to
 NC

Because GPP_B05 is not required for EC or ISH interrupts,
it should be set to NC in coreboot to minimize power impact.

BUG=b:475879711
TEST=Build and boot to OS.

Change-Id: Ic56e16ca89968c8e2204d1609812f1d8d3548512
Signed-off-by: Luca Lai <luca.lai@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91427
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Derek Huang <derekhuang@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
---
 src/mainboard/google/fatcat/variants/ruby/gpio.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/src/mainboard/google/fatcat/variants/ruby/gpio.c b/src/mainboard/google/fatcat/variants/ruby/gpio.c
index 215bf9c61a..9c80074255 100644
--- a/src/mainboard/google/fatcat/variants/ruby/gpio.c
+++ b/src/mainboard/google/fatcat/variants/ruby/gpio.c
@@ -55,7 +55,8 @@ static const struct pad_config gpio_table[] = {
 	PAD_NC(GPP_B02, NONE),
 	/* GPP_B03:     NC */
 	PAD_NC(GPP_B03, NONE),
-
+	/* GPP_B05:     NONE */
+	PAD_NC(GPP_B05, NONE),
 	/* GPP_B06:     NC */
 	PAD_NC(GPP_B06, NONE),
 	/* GPP_B07:     NC */

From 08e3ad9e030c492c5a3cc318121a3a7b6f2b9668 Mon Sep 17 00:00:00 2001
From: David Wu <david_wu@quanta.corp-partner.google.com>
Date: Mon, 2 Mar 2026 16:12:12 +0800
Subject: [PATCH 3558/3886] mb/google/brox/var/juchi: Add 2 memory parts and
 generate DRAM IDs

Add two new memory parts
1. Mircon MT62F1G32D2DS-023 WT:C
2. Samsung K3KL8L80DM-MGCU

BUG=b:481602501
TEST=Run part_id_gen tool and check the generated files.

Change-Id: Ibce661a09f8ad7daec8582508d775e0d7ac4e51f
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91504
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
---
 src/mainboard/google/brox/variants/juchi/memory/Makefile.mk     | 2 +-
 .../google/brox/variants/juchi/memory/dram_id.generated.txt     | 2 ++
 .../google/brox/variants/juchi/memory/mem_parts_used.txt        | 2 ++
 3 files changed, 5 insertions(+), 1 deletion(-)

diff --git a/src/mainboard/google/brox/variants/juchi/memory/Makefile.mk b/src/mainboard/google/brox/variants/juchi/memory/Makefile.mk
index bcb5920648..56f44e554b 100644
--- a/src/mainboard/google/brox/variants/juchi/memory/Makefile.mk
+++ b/src/mainboard/google/brox/variants/juchi/memory/Makefile.mk
@@ -6,5 +6,5 @@
 SPD_SOURCES =
 SPD_SOURCES += spd/lp5/set-0/spd-1.hex      # ID = 0(0b0000)  Parts = MT62F512M32D2DR-031 WT:B, H9JCNNNBK3MLYR-N6E
 SPD_SOURCES += spd/lp5/set-0/spd-2.hex      # ID = 1(0b0001)  Parts = MT62F1G32D4DR-031 WT:B
-SPD_SOURCES += spd/lp5/set-0/spd-11.hex      # ID = 2(0b0010)  Parts = MT62F1G32D2DS-023 WT:B, H58G56BK8BX068, H58G56CK8BX146
+SPD_SOURCES += spd/lp5/set-0/spd-11.hex      # ID = 2(0b0010)  Parts = MT62F1G32D2DS-023 WT:B, H58G56BK8BX068, H58G56CK8BX146, MT62F1G32D2DS-023 WT:C, K3KL8L80DM-MGCU
 SPD_SOURCES += spd/lp5/set-0/spd-7.hex      # ID = 3(0b0011)  Parts = K3KL8L80CM-MGCT
diff --git a/src/mainboard/google/brox/variants/juchi/memory/dram_id.generated.txt b/src/mainboard/google/brox/variants/juchi/memory/dram_id.generated.txt
index 2acaeaed86..0420329929 100644
--- a/src/mainboard/google/brox/variants/juchi/memory/dram_id.generated.txt
+++ b/src/mainboard/google/brox/variants/juchi/memory/dram_id.generated.txt
@@ -11,3 +11,5 @@ MT62F1G32D2DS-023 WT:B         2 (0010)
 H58G56BK8BX068                 2 (0010)
 K3KL8L80CM-MGCT                3 (0011)
 H58G56CK8BX146                 2 (0010)
+MT62F1G32D2DS-023 WT:C         2 (0010)
+K3KL8L80DM-MGCU                2 (0010)
diff --git a/src/mainboard/google/brox/variants/juchi/memory/mem_parts_used.txt b/src/mainboard/google/brox/variants/juchi/memory/mem_parts_used.txt
index a1a7a9932f..23f29e450a 100644
--- a/src/mainboard/google/brox/variants/juchi/memory/mem_parts_used.txt
+++ b/src/mainboard/google/brox/variants/juchi/memory/mem_parts_used.txt
@@ -5,3 +5,5 @@ MT62F1G32D2DS-023 WT:B
 H58G56BK8BX068
 K3KL8L80CM-MGCT
 H58G56CK8BX146
+MT62F1G32D2DS-023 WT:C
+K3KL8L80DM-MGCU

From ea1a722d2b00bf9ba7fec23208fd43b8924138f9 Mon Sep 17 00:00:00 2001
From: Patrick Rudolph <patrick.rudolph@9elements.com>
Date: Sat, 24 Jan 2026 09:56:08 +0100
Subject: [PATCH 3559/3886] soc/intel/xeon_sp: Move microcode loading
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Move loading of microcode to pre_mp_init() as found on other
Intel CPU drivers. There’s no need to cache the microcode location
since intel_microcode_find() already caches it.

No function change, thus untested.

Change-Id: I05bbb074d189594027916c6a3b04270bd3b6edd1
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90892
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
---
 src/soc/intel/xeon_sp/cpx/cpu.c | 12 +++---------
 src/soc/intel/xeon_sp/gnr/cpu.c |  8 +++-----
 src/soc/intel/xeon_sp/skx/cpu.c | 10 +++-------
 src/soc/intel/xeon_sp/spr/cpu.c |  8 +++-----
 4 files changed, 12 insertions(+), 26 deletions(-)

diff --git a/src/soc/intel/xeon_sp/cpx/cpu.c b/src/soc/intel/xeon_sp/cpx/cpu.c
index 5df399a61b..c6375ecfdb 100644
--- a/src/soc/intel/xeon_sp/cpx/cpu.c
+++ b/src/soc/intel/xeon_sp/cpx/cpu.c
@@ -25,8 +25,6 @@
 
 #include "chip.h"
 
-static const void *microcode_patch;
-
 static const config_t *chip_config = NULL;
 
 bool cpu_soc_is_in_untrusted_mode(void)
@@ -167,6 +165,9 @@ static void set_max_turbo_freq(void)
  */
 static void pre_mp_init(void)
 {
+	const void *microcode_patch = intel_microcode_find();
+	intel_microcode_load_unlocked(microcode_patch);
+
 	x86_setup_mtrrs_with_detect();
 	x86_mtrr_check();
 }
@@ -195,13 +196,6 @@ static const struct mp_ops mp_ops = {
 
 void mp_init_cpus(struct bus *bus)
 {
-	microcode_patch = intel_microcode_find();
-
-	if (!microcode_patch)
-		printk(BIOS_ERR, "microcode not found in CBFS!\n");
-
-	intel_microcode_load_unlocked(microcode_patch);
-
 	/* TODO: Handle mp_init_with_smm failure? */
 	mp_init_with_smm(bus, &mp_ops);
 
diff --git a/src/soc/intel/xeon_sp/gnr/cpu.c b/src/soc/intel/xeon_sp/gnr/cpu.c
index 44f466d2e5..2e645a53d7 100644
--- a/src/soc/intel/xeon_sp/gnr/cpu.c
+++ b/src/soc/intel/xeon_sp/gnr/cpu.c
@@ -13,8 +13,6 @@
 
 #include "chip.h"
 
-static const void *microcode_patch;
-
 static const config_t *chip_config = NULL;
 
 bool cpu_soc_is_in_untrusted_mode(void)
@@ -59,6 +57,9 @@ static const struct cpu_driver driver __cpu_driver = {
  */
 static void pre_mp_init(void)
 {
+	const void *microcode_patch = intel_microcode_find();
+	intel_microcode_load_unlocked(microcode_patch);
+
 	x86_setup_mtrrs_with_detect();
 	x86_mtrr_check();
 }
@@ -89,9 +90,6 @@ void mp_init_cpus(struct bus *bus)
 	 */
 	chip_config = bus->dev->chip_info;
 
-	microcode_patch = intel_microcode_find();
-	intel_microcode_load_unlocked(microcode_patch);
-
 	enum cb_err ret = mp_init_with_smm(bus, &mp_ops);
 	if (ret != CB_SUCCESS)
 		printk(BIOS_ERR, "MP initialization failure %d.\n", ret);
diff --git a/src/soc/intel/xeon_sp/skx/cpu.c b/src/soc/intel/xeon_sp/skx/cpu.c
index e829aa988c..48054baada 100644
--- a/src/soc/intel/xeon_sp/skx/cpu.c
+++ b/src/soc/intel/xeon_sp/skx/cpu.c
@@ -246,6 +246,9 @@ static void pre_mp_init(void)
 {
 	printk(BIOS_DEBUG, "%s: entry\n", __func__);
 
+	const void *microcode_patch = intel_microcode_find();
+	intel_microcode_load_unlocked(microcode_patch);
+
 	x86_setup_mtrrs_with_detect();
 	x86_mtrr_check();
 }
@@ -279,13 +282,6 @@ void mp_init_cpus(struct bus *bus)
 {
 	FUNC_ENTER();
 
-	const void *microcode_patch = intel_microcode_find();
-
-	if (!microcode_patch)
-		printk(BIOS_ERR, "microcode not found in CBFS!\n");
-
-	intel_microcode_load_unlocked(microcode_patch);
-
 	/*
 	 * This gets used in cpu device callback. Other than cpu 0,
 	 * rest of the CPU devices do not have
diff --git a/src/soc/intel/xeon_sp/spr/cpu.c b/src/soc/intel/xeon_sp/spr/cpu.c
index cafdc37970..feaac904a2 100644
--- a/src/soc/intel/xeon_sp/spr/cpu.c
+++ b/src/soc/intel/xeon_sp/spr/cpu.c
@@ -17,8 +17,6 @@
 
 #include "chip.h"
 
-static const void *microcode_patch;
-
 static const config_t *chip_config = NULL;
 
 bool cpu_soc_is_in_untrusted_mode(void)
@@ -219,6 +217,9 @@ static void set_max_turbo_freq(void)
  */
 static void pre_mp_init(void)
 {
+	const void *microcode_patch = intel_microcode_find();
+	intel_microcode_load_unlocked(microcode_patch);
+
 	x86_setup_mtrrs_with_detect();
 	x86_mtrr_check();
 }
@@ -255,9 +256,6 @@ void mp_init_cpus(struct bus *bus)
 	 */
 	chip_config = bus->dev->chip_info;
 
-	microcode_patch = intel_microcode_find();
-	intel_microcode_load_unlocked(microcode_patch);
-
 	enum cb_err ret = mp_init_with_smm(bus, &mp_ops);
 	if (ret != CB_SUCCESS)
 		printk(BIOS_ERR, "MP initialization failure %d.\n", ret);

From 484e39c0680d8129ef0b1a591340e731eab25097 Mon Sep 17 00:00:00 2001
From: Patrick Rudolph <patrick.rudolph@9elements.com>
Date: Sat, 24 Jan 2026 10:37:51 +0100
Subject: [PATCH 3560/3886] mp_init: Pass microcode size to MPinit

Extend get_microcode_info() to return the microcode size.
This is being used in the following commit which uses the size
to copy the microcode update to RAM in order to speed up MPinit.

Depending on the SPI flash interface speed, the microcode size and
the number of APs this can improve boot time by seconds.

Since microcode size isn't used yet this is not a functional change.

Change-Id: I1385e04c56e1411f0847a1c201c17e460c957477
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90894
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/cpu/intel/haswell/haswell_init.c                 | 12 +++++++-----
 src/cpu/intel/model_1067x/mp_init.c                  |  8 ++++++--
 src/cpu/intel/model_2065x/model_2065x_init.c         |  8 ++++++--
 src/cpu/intel/model_206ax/model_206ax_init.c         |  8 ++++++--
 src/cpu/intel/model_f2x/mp_init.c                    |  8 ++++++--
 src/cpu/x86/mp_init.c                                |  3 +++
 src/include/cpu/x86/mp.h                             |  2 +-
 src/soc/intel/apollolake/cpu.c                       |  8 ++++++--
 src/soc/intel/baytrail/cpu.c                         |  8 ++++++--
 src/soc/intel/braswell/cpu.c                         |  8 ++++++--
 src/soc/intel/common/block/cpu/mp_init.c             |  8 ++++++--
 .../intel/common/block/include/intelblocks/mp_init.h |  2 +-
 src/soc/intel/xeon_sp/cpx/cpu.c                      |  8 ++++++--
 src/soc/intel/xeon_sp/gnr/cpu.c                      |  8 ++++++--
 src/soc/intel/xeon_sp/skx/cpu.c                      |  9 +++++++--
 src/soc/intel/xeon_sp/spr/cpu.c                      |  8 ++++++--
 16 files changed, 85 insertions(+), 31 deletions(-)

diff --git a/src/cpu/intel/haswell/haswell_init.c b/src/cpu/intel/haswell/haswell_init.c
index a54a01ad8f..bd8932a039 100644
--- a/src/cpu/intel/haswell/haswell_init.c
+++ b/src/cpu/intel/haswell/haswell_init.c
@@ -502,8 +502,6 @@ static void cpu_core_init(struct device *cpu)
 }
 
 /* MP initialization support. */
-static const void *microcode_patch;
-
 static void pre_mp_init(void)
 {
 	/* Setup MTRRs based on physical address size. */
@@ -534,10 +532,13 @@ static int get_cpu_count(void)
 	return num_threads;
 }
 
-static void get_microcode_info(const void **microcode, int *parallel)
+static void get_microcode_info(const void **microcode, size_t *size, int *parallel)
 {
-	microcode_patch = intel_microcode_find();
-	*microcode = microcode_patch;
+	const struct microcode *microcode_file = intel_microcode_find();
+	if (microcode_file != NULL)
+		*size = get_microcode_size(microcode_file);
+
+	*microcode = microcode_file;
 	*parallel = 1;
 }
 
@@ -547,6 +548,7 @@ static void per_cpu_smm_trigger(void)
 	smm_relocate();
 
 	/* After SMM relocation a 2nd microcode load is required. */
+	const void *microcode_patch = intel_microcode_find();
 	intel_microcode_load_unlocked(microcode_patch);
 }
 
diff --git a/src/cpu/intel/model_1067x/mp_init.c b/src/cpu/intel/model_1067x/mp_init.c
index def136e689..f2a702c2ca 100644
--- a/src/cpu/intel/model_1067x/mp_init.c
+++ b/src/cpu/intel/model_1067x/mp_init.c
@@ -30,9 +30,13 @@ static int get_cpu_count(void)
 	return cores;
 }
 
-static void get_microcode_info(const void **microcode, int *parallel)
+static void get_microcode_info(const void **microcode, size_t *size, int *parallel)
 {
-	*microcode = intel_microcode_find();
+	const struct microcode *microcode_file = intel_microcode_find();
+	if (microcode_file != NULL)
+		*size = get_microcode_size(microcode_file);
+
+	*microcode = microcode_file;
 	*parallel = !intel_ht_supported();
 }
 
diff --git a/src/cpu/intel/model_2065x/model_2065x_init.c b/src/cpu/intel/model_2065x/model_2065x_init.c
index d02c70bdfa..f8fb589159 100644
--- a/src/cpu/intel/model_2065x/model_2065x_init.c
+++ b/src/cpu/intel/model_2065x/model_2065x_init.c
@@ -129,9 +129,13 @@ static int get_cpu_count(void)
 	return num_threads;
 }
 
-static void get_microcode_info(const void **microcode, int *parallel)
+static void get_microcode_info(const void **microcode, size_t *size, int *parallel)
 {
-	*microcode = intel_microcode_find();
+	const struct microcode *microcode_file = intel_microcode_find();
+	if (microcode_file != NULL)
+		*size = get_microcode_size(microcode_file);
+
+	*microcode = microcode_file;
 	*parallel = !intel_ht_supported();
 }
 
diff --git a/src/cpu/intel/model_206ax/model_206ax_init.c b/src/cpu/intel/model_206ax/model_206ax_init.c
index 162c674e0f..0fdbacbe8d 100644
--- a/src/cpu/intel/model_206ax/model_206ax_init.c
+++ b/src/cpu/intel/model_206ax/model_206ax_init.c
@@ -509,9 +509,13 @@ static int get_cpu_count(void)
 	return num_threads;
 }
 
-static void get_microcode_info(const void **microcode, int *parallel)
+static void get_microcode_info(const void **microcode, size_t *size, int *parallel)
 {
-	*microcode = intel_microcode_find();
+	const struct microcode *microcode_file = intel_microcode_find();
+	if (microcode_file != NULL)
+		*size = get_microcode_size(microcode_file);
+
+	*microcode = microcode_file;
 	*parallel = !intel_ht_supported();
 }
 
diff --git a/src/cpu/intel/model_f2x/mp_init.c b/src/cpu/intel/model_f2x/mp_init.c
index c8d38c59ff..010b1770c1 100644
--- a/src/cpu/intel/model_f2x/mp_init.c
+++ b/src/cpu/intel/model_f2x/mp_init.c
@@ -27,9 +27,13 @@ static int get_cpu_count(void)
 	return CONFIG_MAX_CPUS;
 }
 
-static void get_microcode_info(const void **microcode, int *parallel)
+static void get_microcode_info(const void **microcode, size_t *size, int *parallel)
 {
-	*microcode = intel_microcode_find();
+	const struct microcode *microcode_file = intel_microcode_find();
+	if (microcode_file != NULL)
+		*size = get_microcode_size(microcode_file);
+
+	*microcode = microcode_file;
 	*parallel = !intel_ht_supported();
 }
 
diff --git a/src/cpu/x86/mp_init.c b/src/cpu/x86/mp_init.c
index 23880c74c8..ed2005e91e 100644
--- a/src/cpu/x86/mp_init.c
+++ b/src/cpu/x86/mp_init.c
@@ -77,6 +77,7 @@ struct mp_params {
 	int num_cpus; /* Total cpus include BSP */
 	int parallel_microcode_load;
 	const void *microcode_pointer;
+	size_t microcode_size;
 	/* Flight plan  for APs and BSP. */
 	struct mp_flight_record *flight_plan;
 	int num_records;
@@ -1145,9 +1146,11 @@ static enum cb_err do_mp_init_with_smm(struct bus *cpu_bus, const struct mp_ops
 		printk(BIOS_INFO, "Will perform SMM setup.\n");
 
 	mp_params.num_cpus = mp_state.cpu_count;
+
 	/* Gather microcode information. */
 	if (mp_state.ops.get_microcode_info != NULL)
 		mp_state.ops.get_microcode_info(&mp_params.microcode_pointer,
+			&mp_params.microcode_size,
 			&mp_params.parallel_microcode_load);
 	mp_params.flight_plan = &mp_steps[0];
 	mp_params.num_records = ARRAY_SIZE(mp_steps);
diff --git a/src/include/cpu/x86/mp.h b/src/include/cpu/x86/mp.h
index dd86dce2c5..ec4297e105 100644
--- a/src/include/cpu/x86/mp.h
+++ b/src/include/cpu/x86/mp.h
@@ -47,7 +47,7 @@ struct mp_ops {
 	 * Optionally fill in pointer to microcode and indicate if the APs
 	 * can load the microcode in parallel.
 	 */
-	void (*get_microcode_info)(const void **microcode, int *parallel);
+	void (*get_microcode_info)(const void **microcode, size_t *size, int *parallel);
 	/*
 	 * Optionally provide a callback prior to the APs starting SMM
 	 * relocation or CPU driver initialization. However, note that
diff --git a/src/soc/intel/apollolake/cpu.c b/src/soc/intel/apollolake/cpu.c
index 67450b2d5d..ee003805fd 100644
--- a/src/soc/intel/apollolake/cpu.c
+++ b/src/soc/intel/apollolake/cpu.c
@@ -193,9 +193,13 @@ int get_cpu_count(void)
 	return num_virt_cores;
 }
 
-void get_microcode_info(const void **microcode, int *parallel)
+void get_microcode_info(const void **microcode, size_t *size, int *parallel)
 {
-	*microcode = intel_microcode_find();
+	const struct microcode *microcode_file = intel_microcode_find();
+	if (microcode_file != NULL)
+		*size = get_microcode_size(microcode_file);
+
+	*microcode = microcode_file;
 	*parallel = 1;
 }
 #endif
diff --git a/src/soc/intel/baytrail/cpu.c b/src/soc/intel/baytrail/cpu.c
index 2a4616cec3..7408eb7c64 100644
--- a/src/soc/intel/baytrail/cpu.c
+++ b/src/soc/intel/baytrail/cpu.c
@@ -146,11 +146,15 @@ static void get_smm_info(uintptr_t *perm_smbase, size_t *perm_smsize,
 	*smm_save_state_size = sizeof(em64t100_smm_state_save_area_t);
 }
 
-static void get_microcode_info(const void **microcode, int *parallel)
+static void get_microcode_info(const void **microcode, size_t *size, int *parallel)
 {
 	const struct pattrs *pattrs = pattrs_get();
+	const struct microcode *microcode_file = pattrs->microcode_patch;
 
-	*microcode = pattrs->microcode_patch;
+	if (microcode_file != NULL)
+		*size = get_microcode_size(microcode_file);
+
+	*microcode = microcode_file;
 	*parallel = !intel_ht_supported();
 }
 
diff --git a/src/soc/intel/braswell/cpu.c b/src/soc/intel/braswell/cpu.c
index 23663c3c71..f5e985396b 100644
--- a/src/soc/intel/braswell/cpu.c
+++ b/src/soc/intel/braswell/cpu.c
@@ -146,11 +146,15 @@ static void get_smm_info(uintptr_t *perm_smbase, size_t *perm_smsize,
 	*smm_save_state_size = sizeof(em64t100_smm_state_save_area_t);
 }
 
-static void get_microcode_info(const void **microcode, int *parallel)
+static void get_microcode_info(const void **microcode, size_t *size, int *parallel)
 {
 	const struct pattrs *pattrs = pattrs_get();
+	const struct microcode *microcode_file = pattrs->microcode_patch;
 
-	*microcode = pattrs->microcode_patch;
+	if (microcode_file != NULL)
+		*size = get_microcode_size(microcode_file);
+
+	*microcode = microcode_file;
 	*parallel = !intel_ht_supported();
 }
 
diff --git a/src/soc/intel/common/block/cpu/mp_init.c b/src/soc/intel/common/block/cpu/mp_init.c
index dd8a31592e..12d9b95cbd 100644
--- a/src/soc/intel/common/block/cpu/mp_init.c
+++ b/src/soc/intel/common/block/cpu/mp_init.c
@@ -137,9 +137,13 @@ int get_cpu_count(void)
  * sets the argument *parallel to 1, which allows microcode loading in all
  * APs to occur in parallel during MP Init.
  */
-void get_microcode_info(const void **microcode, int *parallel)
+void get_microcode_info(const void **microcode, size_t *size, int *parallel)
 {
-	*microcode = intel_microcode_find();
+	const struct microcode *microcode_file = intel_microcode_find();
+	if (microcode_file != NULL)
+		*size = get_microcode_size(microcode_file);
+
+	*microcode = microcode_file;
 	*parallel = 1;
 }
 
diff --git a/src/soc/intel/common/block/include/intelblocks/mp_init.h b/src/soc/intel/common/block/include/intelblocks/mp_init.h
index 0dd2109e4a..a0579b7db2 100644
--- a/src/soc/intel/common/block/include/intelblocks/mp_init.h
+++ b/src/soc/intel/common/block/include/intelblocks/mp_init.h
@@ -21,7 +21,7 @@ int get_cpu_count(void);
  * sets the argument *parallel to 1, which allows microcode loading in all
  * APs to occur in parallel during MP Init.
  */
-void get_microcode_info(const void **microcode, int *parallel);
+void get_microcode_info(const void **microcode, size_t *size, int *parallel);
 
 /*
  * Perform BSP and AP initialization
diff --git a/src/soc/intel/xeon_sp/cpx/cpu.c b/src/soc/intel/xeon_sp/cpx/cpu.c
index c6375ecfdb..57f9ea9a29 100644
--- a/src/soc/intel/xeon_sp/cpx/cpu.c
+++ b/src/soc/intel/xeon_sp/cpx/cpu.c
@@ -66,9 +66,13 @@ static void xeon_configure_mca(void)
  * the BSP. Loading MCU on AP in parallel seems to fail in 10% of the cases
  * so do it serialized.
  */
-void get_microcode_info(const void **microcode, int *parallel)
+void get_microcode_info(const void **microcode, size_t *size, int *parallel)
 {
-	*microcode = intel_microcode_find();
+	const struct microcode *microcode_file = intel_microcode_find();
+	if (microcode_file != NULL)
+		*size = get_microcode_size(microcode_file);
+
+	*microcode = microcode_file;
 	*parallel = 0;
 }
 
diff --git a/src/soc/intel/xeon_sp/gnr/cpu.c b/src/soc/intel/xeon_sp/gnr/cpu.c
index 2e645a53d7..9969287b3c 100644
--- a/src/soc/intel/xeon_sp/gnr/cpu.c
+++ b/src/soc/intel/xeon_sp/gnr/cpu.c
@@ -21,9 +21,13 @@ bool cpu_soc_is_in_untrusted_mode(void)
 	return false;
 }
 
-void get_microcode_info(const void **microcode, int *parallel)
+void get_microcode_info(const void **microcode, size_t *size, int *parallel)
 {
-	*microcode = intel_microcode_find();
+	const struct microcode *microcode_file = intel_microcode_find();
+	if (microcode_file != NULL)
+		*size = get_microcode_size(microcode_file);
+
+	*microcode = microcode_file;
 	*parallel = 0;
 }
 
diff --git a/src/soc/intel/xeon_sp/skx/cpu.c b/src/soc/intel/xeon_sp/skx/cpu.c
index 48054baada..ddb509bfb4 100644
--- a/src/soc/intel/xeon_sp/skx/cpu.c
+++ b/src/soc/intel/xeon_sp/skx/cpu.c
@@ -13,6 +13,7 @@
 #include <cpu/intel/smm_reloc.h>
 #include <cpu/intel/em64t101_save_state.h>
 #include <intelblocks/cpulib.h>
+#include <intelblocks/mp_init.h>
 #include <intelpch/lockdown.h>
 #include <soc/msr.h>
 #include <soc/pm.h>
@@ -70,9 +71,13 @@ static void xeon_configure_mca(void)
  * FSP-S updates microcodes serialized, so do the same.
  *
  */
-static void get_microcode_info(const void **microcode, int *parallel)
+void get_microcode_info(const void **microcode, size_t *size, int *parallel)
 {
-	*microcode = intel_microcode_find();
+	const struct microcode *microcode_file = intel_microcode_find();
+	if (microcode_file != NULL)
+		*size = get_microcode_size(microcode_file);
+
+	*microcode = microcode_file;
 	*parallel = 0;
 }
 
diff --git a/src/soc/intel/xeon_sp/spr/cpu.c b/src/soc/intel/xeon_sp/spr/cpu.c
index feaac904a2..55568cc8ff 100644
--- a/src/soc/intel/xeon_sp/spr/cpu.c
+++ b/src/soc/intel/xeon_sp/spr/cpu.c
@@ -56,9 +56,13 @@ static void xeon_configure_mca(void)
  * the BSP. Loading MCU on AP in parallel seems to fail in 10% of the cases
  * so do it serialized.
  */
-void get_microcode_info(const void **microcode, int *parallel)
+void get_microcode_info(const void **microcode, size_t *size, int *parallel)
 {
-	*microcode = intel_microcode_find();
+	const struct microcode *microcode_file = intel_microcode_find();
+	if (microcode_file != NULL)
+		*size = get_microcode_size(microcode_file);
+
+	*microcode = microcode_file;
 	*parallel = 0;
 }
 

From 3fa3818e411bf80bf7103942ecc163a5bc0a7017 Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Mon, 16 Feb 2026 21:30:46 +0000
Subject: [PATCH 3561/3886] starlabs: add ACPI SMI bridge for EFI options

Add a Device NVS (DNVS) protocol and SMM handler to let ACPI read and
write a restricted set of coreboot options stored in the UEFI variable
store.

ACPI fills DNVS and triggers an SMI via APM_CNT (0xB2). SMM performs
the requested operation and updates DNVS with status and, for reads,
the returned value.

Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: Ice0ac36f6d0e1de88daf7010cb1771453547619e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91303
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/starlabs/common/Kconfig         |  11 +-
 src/mainboard/starlabs/common/Makefile.mk     |   3 +
 src/mainboard/starlabs/common/gnvs.c          |  11 +
 .../common/include/starlabs/efi_option_smi.h  |  38 ++++
 src/mainboard/starlabs/common/smihandler.c    | 188 ++++++++++++++++++
 5 files changed, 249 insertions(+), 2 deletions(-)
 create mode 100644 src/mainboard/starlabs/common/gnvs.c
 create mode 100644 src/mainboard/starlabs/common/include/starlabs/efi_option_smi.h
 create mode 100644 src/mainboard/starlabs/common/smihandler.c

diff --git a/src/mainboard/starlabs/common/Kconfig b/src/mainboard/starlabs/common/Kconfig
index adeda59bdf..8a670142c0 100644
--- a/src/mainboard/starlabs/common/Kconfig
+++ b/src/mainboard/starlabs/common/Kconfig
@@ -17,8 +17,15 @@ config MB_COMMON_DIR
 	string
 	default "starlabs/common"
 
-config SOC_INTEL_COMMON_BLOCK_SMM_TCO_INTRUDER_SMI_ENABLE
-	default n
+config STARLABS_ACPI_EFI_OPTION_SMI
+	bool "Expose coreboot options to ACPI via SMI (UEFI var store)"
+	depends on USE_UEFI_VARIABLE_STORE
+	depends on HAVE_ACPI_TABLES
+	default y
+	help
+	  Provide ACPI methods that proxy a restricted set of coreboot options
+	  (e.g. keyboard backlight and trackpad state) to the UEFI variable
+	  store via an SMM APMC SMI handler.
 
 source "src/mainboard/starlabs/common/hda/Kconfig"
 
diff --git a/src/mainboard/starlabs/common/Makefile.mk b/src/mainboard/starlabs/common/Makefile.mk
index 90c0d94d5a..b12b7610d3 100644
--- a/src/mainboard/starlabs/common/Makefile.mk
+++ b/src/mainboard/starlabs/common/Makefile.mk
@@ -7,3 +7,6 @@ subdirs-$(CONFIG_VENDOR_STARLABS) += pin_mux
 subdirs-$(CONFIG_VENDOR_STARLABS) += smbios
 
 CPPFLAGS_common += -I$(src)/mainboard/starlabs/common/include
+
+ramstage-$(CONFIG_STARLABS_ACPI_EFI_OPTION_SMI) += gnvs.c
+smm-$(CONFIG_STARLABS_ACPI_EFI_OPTION_SMI) += smihandler.c
diff --git a/src/mainboard/starlabs/common/gnvs.c b/src/mainboard/starlabs/common/gnvs.c
new file mode 100644
index 0000000000..7e119470ab
--- /dev/null
+++ b/src/mainboard/starlabs/common/gnvs.c
@@ -0,0 +1,11 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <stddef.h>
+
+#include <acpi/acpi_gnvs.h>
+#include <starlabs/efi_option_smi.h>
+
+size_t size_of_dnvs(void)
+{
+	return sizeof(struct starlabs_dnvs_efiopt);
+}
diff --git a/src/mainboard/starlabs/common/include/starlabs/efi_option_smi.h b/src/mainboard/starlabs/common/include/starlabs/efi_option_smi.h
new file mode 100644
index 0000000000..cdd6bf4a89
--- /dev/null
+++ b/src/mainboard/starlabs/common/include/starlabs/efi_option_smi.h
@@ -0,0 +1,38 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef STARLABS_EFI_OPTION_SMI_H
+#define STARLABS_EFI_OPTION_SMI_H
+
+#include <types.h>
+
+/*
+ * ACPI <-> SMM protocol for reading/writing a restricted set of coreboot
+ * options in the UEFI variable store.
+ *
+ * ACPI fills DNVS, then triggers an APMC SMI by writing STARLABS_APMC_CMD
+ * to the APM_CNT port (0xB2). SMM reads DNVS, performs the operation, and
+ * updates DNVS with status and (for reads) the returned value.
+ */
+
+#define STARLABS_APMC_CMD_EFI_OPTION 0xE2
+
+enum starlabs_efiopt_cmd {
+	STARLABS_EFIOPT_CMD_GET = 1,
+	STARLABS_EFIOPT_CMD_SET = 2,
+};
+
+enum starlabs_efiopt_id {
+	STARLABS_EFIOPT_ID_FN_LOCK_STATE = 1,
+	STARLABS_EFIOPT_ID_TRACKPAD_STATE = 2,
+	STARLABS_EFIOPT_ID_KBL_BRIGHTNESS = 3,
+	STARLABS_EFIOPT_ID_KBL_STATE = 4,
+};
+
+struct starlabs_dnvs_efiopt {
+	uint32_t cmd;
+	uint32_t id;
+	uint32_t value;
+	uint32_t status;
+} __packed;
+
+#endif /* STARLABS_EFI_OPTION_SMI_H */
diff --git a/src/mainboard/starlabs/common/smihandler.c b/src/mainboard/starlabs/common/smihandler.c
new file mode 100644
index 0000000000..d74cce1008
--- /dev/null
+++ b/src/mainboard/starlabs/common/smihandler.c
@@ -0,0 +1,188 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <acpi/acpi_gnvs.h>
+#include <commonlib/helpers.h>
+#include <cpu/x86/smm.h>
+#include <ec/starlabs/merlin/ec.h>
+#if CONFIG(SOC_INTEL_COMMON_BLOCK_FAST_SPI)
+#include <cpu/intel/msr.h>
+#include <cpu/x86/msr.h>
+#include <device/mmio.h>
+#include <intelblocks/fast_spi.h>
+#endif
+#include <option.h>
+#include <soc/nvs.h>
+#include <starlabs/efi_option_smi.h>
+#include <types.h>
+
+#if CONFIG(SOC_INTEL_COMMON_BLOCK_FAST_SPI)
+static void set_insmm_sts(const bool enable_writes)
+{
+	msr_t msr = {
+		.lo = read32p(0xfed30880),
+		.hi = 0,
+	};
+
+	if (enable_writes)
+		msr.lo |= 1;
+	else
+		msr.lo &= ~1;
+
+	wrmsr(MSR_SPCL_CHIPSET_USAGE, msr);
+}
+#endif
+
+static bool chipset_disable_wp(void)
+{
+#if CONFIG(SOC_INTEL_COMMON_BLOCK_FAST_SPI)
+	const bool wp_enabled = !fast_spi_wpd_status();
+
+	if (wp_enabled) {
+		set_insmm_sts(true);
+		/*
+		 * As per BWG, clearing "SPI_BIOS_CONTROL_SYNC_SS"
+		 * bit is a must prior setting SPI_BIOS_CONTROL_WPD" bit
+		 * to avoid 3-strike error.
+		 */
+		fast_spi_clear_sync_smi_status();
+		fast_spi_disable_wp();
+	}
+
+	return wp_enabled;
+#endif
+
+	return false;
+}
+
+static void chipset_enable_wp(void)
+{
+#if CONFIG(SOC_INTEL_COMMON_BLOCK_FAST_SPI)
+	fast_spi_enable_wp();
+	set_insmm_sts(false);
+#endif
+}
+
+static struct starlabs_dnvs_efiopt *get_starlabs_dnvs_efiopt(void)
+{
+	if (!gnvs)
+		return NULL;
+
+	const size_t gnvs_size = ALIGN_UP(sizeof(struct global_nvs), sizeof(uint64_t));
+
+	uint8_t *base = (uint8_t *)gnvs;
+	base += gnvs_size;
+	return (struct starlabs_dnvs_efiopt *)base;
+}
+
+struct starlabs_efiopt_entry {
+	const char *name;
+	enum starlabs_efiopt_id id;
+	uint32_t fallback;
+};
+
+static const struct starlabs_efiopt_entry *find_efiopt(enum starlabs_efiopt_id id)
+{
+	static const struct starlabs_efiopt_entry opts[] = {
+		{
+			.name = "fn_lock_state",
+			.id = STARLABS_EFIOPT_ID_FN_LOCK_STATE,
+			.fallback = LOCKED,
+		},
+		{
+			.name = "trackpad_state",
+			.id = STARLABS_EFIOPT_ID_TRACKPAD_STATE,
+			.fallback = TRACKPAD_ENABLED,
+		},
+		{
+			.name = "kbl_brightness",
+			.id = STARLABS_EFIOPT_ID_KBL_BRIGHTNESS,
+			.fallback = CONFIG(EC_STARLABS_KBL_LEVELS) ? KBL_LOW : KBL_ON,
+		},
+		{
+			.name = "kbl_state",
+			.id = STARLABS_EFIOPT_ID_KBL_STATE,
+			.fallback = KBL_ENABLED,
+		},
+	};
+
+	for (size_t i = 0; i < ARRAY_SIZE(opts); i++) {
+		if (opts[i].id == id)
+			return &opts[i];
+	}
+
+	return NULL;
+}
+
+static enum cb_err normalize_value(enum starlabs_efiopt_id id, uint32_t *value)
+{
+	if (!value)
+		return CB_ERR_ARG;
+
+	switch (id) {
+	case STARLABS_EFIOPT_ID_FN_LOCK_STATE:
+		if (*value == UNLOCKED || *value == LOCKED)
+			return CB_SUCCESS;
+		return CB_ERR_ARG;
+	case STARLABS_EFIOPT_ID_TRACKPAD_STATE:
+		/* Normalize "re-enabled" to "enabled". */
+		if (*value == 0x11)
+			*value = TRACKPAD_ENABLED;
+		if (*value == TRACKPAD_ENABLED || *value == TRACKPAD_DISABLED)
+			return CB_SUCCESS;
+		return CB_ERR_ARG;
+	case STARLABS_EFIOPT_ID_KBL_BRIGHTNESS:
+		if (*value == KBL_ON || *value == KBL_OFF || *value == KBL_LOW ||
+		    *value == KBL_HIGH)
+			return CB_SUCCESS;
+		return CB_ERR_ARG;
+	case STARLABS_EFIOPT_ID_KBL_STATE:
+		if (*value == KBL_DISABLED || *value == KBL_ENABLED)
+			return CB_SUCCESS;
+		return CB_ERR_ARG;
+	default:
+		return CB_ERR_ARG;
+	}
+}
+
+int mainboard_smi_apmc(u8 data)
+{
+	if (data != STARLABS_APMC_CMD_EFI_OPTION)
+		return 0;
+
+	struct starlabs_dnvs_efiopt *dnvs = get_starlabs_dnvs_efiopt();
+	if (!dnvs)
+		return 0;
+
+	const enum starlabs_efiopt_cmd cmd = dnvs->cmd;
+	const enum starlabs_efiopt_id id = dnvs->id;
+	const struct starlabs_efiopt_entry *opt = find_efiopt(id);
+
+	if (!opt) {
+		dnvs->status = CB_ERR_ARG;
+		return 1;
+	}
+
+	switch (cmd) {
+	case STARLABS_EFIOPT_CMD_GET:
+		dnvs->value = get_uint_option(opt->name, opt->fallback);
+		dnvs->status = CB_SUCCESS;
+		break;
+	case STARLABS_EFIOPT_CMD_SET: {
+		uint32_t value = dnvs->value;
+		dnvs->status = normalize_value(id, &value);
+		if (dnvs->status != CB_SUCCESS)
+			break;
+
+		const bool wp_enabled = chipset_disable_wp();
+		dnvs->status = set_uint_option(opt->name, value);
+		if (wp_enabled)
+			chipset_enable_wp();
+		break;
+	}
+	default:
+		dnvs->status = CB_ERR_ARG;
+		break;
+	}
+
+	return 1;
+}

From 9dac2b9e539cada107b276592d9347b3e4d04d46 Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Mon, 16 Feb 2026 21:32:24 +0000
Subject: [PATCH 3562/3886] ec/starlabs/merlin: persist settings via EFI
 options

When STARLABS_ACPI_EFI_OPTION_SMI is enabled, store and restore
trackpad and keyboard backlight state across S4/S5 using the EFI
variable store SMI bridge instead of CMOS.

Also make the EC init paths treat CMOS as an index mapping and
prefer the option backend when CMOS options are not in use.

Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: Ia31ac0440eba1334be48030ce7fe03dc84193ac3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91304
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/ec/starlabs/merlin/acpi/suspend.asl | 139 +++++++++++++++--
 src/ec/starlabs/merlin/ite.c            | 189 +++++++-----------------
 src/ec/starlabs/merlin/nuvoton.c        | 161 ++++++++------------
 3 files changed, 246 insertions(+), 243 deletions(-)

diff --git a/src/ec/starlabs/merlin/acpi/suspend.asl b/src/ec/starlabs/merlin/acpi/suspend.asl
index 966362f8a4..0ccce6f84b 100644
--- a/src/ec/starlabs/merlin/acpi/suspend.asl
+++ b/src/ec/starlabs/merlin/acpi/suspend.asl
@@ -1,8 +1,75 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
+#if CONFIG(STARLABS_ACPI_EFI_OPTION_SMI)
+Field (\DNVS, ByteAcc, NoLock, Preserve)
+{
+	EOCM, 32,	// EFI option command
+	EOID, 32,	// EFI option ID
+	EOVL, 32,	// EFI option value
+	EORS, 32,	// EFI option status
+}
+
+Name (EOAP, 0xE2)	// STARLABS_APMC_CMD_EFI_OPTION
+
+Name (EOFL, 0x1)	// STARLABS_EFIOPT_ID_FN_LOCK_STATE
+Name (EOTP, 0x2)	// STARLABS_EFIOPT_ID_TRACKPAD_STATE
+Name (EOKB, 0x3)	// STARLABS_EFIOPT_ID_KBL_BRIGHTNESS
+Name (EOKS, 0x4)	// STARLABS_EFIOPT_ID_KBL_STATE
+
+Mutex (EOMX, 0x00)
+
+Method (EOGT, 1, Serialized)
+{
+	If (Acquire (EOMX, 1000))
+	{
+		Return (0xFFFFFFFF)
+	}
+
+	Store (0x01, EOCM)
+	Store (Arg0, EOID)
+	Store (0x00, EORS)
+	Store (EOAP, \_SB.PCI0.LPCB.EC.SMB2)
+
+	Store (EOVL, Local0)
+	Release (EOMX)
+	Return (Local0)
+}
+
+Method (EOSV, 2, Serialized)
+{
+	If (Acquire (EOMX, 1000))
+	{
+		Return (0x01)
+	}
+
+	Store (0x02, EOCM)
+	Store (Arg0, EOID)
+	Store (Arg1, EOVL)
+	Store (0x00, EORS)
+	Store (EOAP, \_SB.PCI0.LPCB.EC.SMB2)
+
+	Store (EORS, Local0)
+	Release (EOMX)
+	Return (Local0)
+}
+#endif
+
 Method (RPTS, 1, Serialized)
 {
 
+#if CONFIG(STARLABS_ACPI_EFI_OPTION_SMI)
+	/* Store current EC settings in UEFI variable store */
+	Store (\_SB.PCI0.LPCB.EC.ECRD (RefOf (\_SB.PCI0.LPCB.EC.TPLE)), Local0)
+	If (Local0 == 0x11)
+	{
+		Store (0x00, Local0)
+	}
+	EOSV (EOTP, Local0)
+
+	EOSV (EOFL, \_SB.PCI0.LPCB.EC.ECRD (RefOf (\_SB.PCI0.LPCB.EC.FLKE)))
+	EOSV (EOKS, \_SB.PCI0.LPCB.EC.ECRD (RefOf (\_SB.PCI0.LPCB.EC.KLSE)))
+	EOSV (EOKB, \_SB.PCI0.LPCB.EC.ECRD (RefOf (\_SB.PCI0.LPCB.EC.KLBE)))
+#else
 	/* Store current EC settings in CMOS */
 	Switch (ToInteger (\_SB.PCI0.LPCB.EC.ECRD (RefOf (\_SB.PCI0.LPCB.EC.TPLE))))
 	{
@@ -11,20 +78,19 @@ Method (RPTS, 1, Serialized)
 		// 0x22 == Disabled   == 0x01
 		Case (0x00)
 		{
-			\_SB.PCI0.LPCB.TPLC = 0x00
+			Store (0x00, \_SB.PCI0.LPCB.TPLC)
 		}
 		Case (0x11)
 		{
-			\_SB.PCI0.LPCB.TPLC = 0x00
+			Store (0x00, \_SB.PCI0.LPCB.TPLC)
 		}
 		Case (0x22)
 		{
-			\_SB.PCI0.LPCB.TPLC = 0x01
+			Store (0x01, \_SB.PCI0.LPCB.TPLC)
 		}
 	}
 
-	\_SB.PCI0.LPCB.FLKC =
-		\_SB.PCI0.LPCB.EC.ECRD (RefOf (\_SB.PCI0.LPCB.EC.FLKE))
+	Store (\_SB.PCI0.LPCB.EC.ECRD (RefOf (\_SB.PCI0.LPCB.EC.FLKE)), \_SB.PCI0.LPCB.FLKC)
 
 	Switch (ToInteger (\_SB.PCI0.LPCB.EC.ECRD (RefOf (\_SB.PCI0.LPCB.EC.KLSE))))
 	{
@@ -32,11 +98,11 @@ Method (RPTS, 1, Serialized)
 		// 0xdd == Enabled  == 0x01
 		Case (0x00)
 		{
-			\_SB.PCI0.LPCB.KLSC = 0x00
+			Store (0x00, \_SB.PCI0.LPCB.KLSC)
 		}
 		Case (0xdd)
 		{
-			\_SB.PCI0.LPCB.KLSC = 0x01
+			Store (0x01, \_SB.PCI0.LPCB.KLSC)
 		}
 	}
 
@@ -48,27 +114,30 @@ Method (RPTS, 1, Serialized)
 		// 0xaa == High == 0x03
 		Case (0xdd)
 		{
-			\_SB.PCI0.LPCB.KLBC = 0x00
+			Store (0x00, \_SB.PCI0.LPCB.KLBC)
 		}
 		Case (0xcc)
 		{
-			\_SB.PCI0.LPCB.KLBC = 0x01
+			Store (0x01, \_SB.PCI0.LPCB.KLBC)
 		}
 		Case (0xbb)
 		{
-			\_SB.PCI0.LPCB.KLBC = 0x02
+			Store (0x02, \_SB.PCI0.LPCB.KLBC)
 		}
 		Case (0xaa)
 		{
-			\_SB.PCI0.LPCB.KLBC = 0x03
+			Store (0x03, \_SB.PCI0.LPCB.KLBC)
 		}
 	}
+#endif
 
 	/*
 	 * Disable ACPI support.
 	 * This should always be the last action before entering a sleep state.
 	 */
 	\_SB.PCI0.LPCB.EC.ECWR(0x00, RefOf(\_SB.PCI0.LPCB.EC.OSFG))
+
+	Return (Arg0)
 }
 
 Method (RWAK, 1, Serialized)
@@ -79,6 +148,51 @@ Method (RWAK, 1, Serialized)
 	 */
 	\_SB.PCI0.LPCB.EC.ECWR(0x01, RefOf(\_SB.PCI0.LPCB.EC.OSFG))
 
+#if CONFIG(STARLABS_ACPI_EFI_OPTION_SMI)
+	/* Restore EC settings from UEFI variable store */
+	Store (EOGT (EOTP), Local0)
+	If (Local0 == 0x22)
+	{
+		\_SB.PCI0.LPCB.EC.ECWR (0x22, RefOf(\_SB.PCI0.LPCB.EC.TPLE))
+	}
+	Else
+	{
+		\_SB.PCI0.LPCB.EC.ECWR (0x00, RefOf(\_SB.PCI0.LPCB.EC.TPLE))
+	}
+
+	\_SB.PCI0.LPCB.EC.ECWR (EOGT (EOFL), RefOf(\_SB.PCI0.LPCB.EC.FLKE))
+
+	Store (EOGT (EOKS), Local0)
+	If (Local0 == 0xdd)
+	{
+		\_SB.PCI0.LPCB.EC.ECWR (0xdd, RefOf(\_SB.PCI0.LPCB.EC.KLSE))
+	}
+	Else
+	{
+		\_SB.PCI0.LPCB.EC.ECWR (0x00, RefOf(\_SB.PCI0.LPCB.EC.KLSE))
+	}
+
+	Store (EOGT (EOKB), Local0)
+	Switch (ToInteger (Local0))
+	{
+		Case (0xdd)
+		{
+			\_SB.PCI0.LPCB.EC.ECWR (0xdd, RefOf(\_SB.PCI0.LPCB.EC.KLBE))
+		}
+		Case (0xcc)
+		{
+			\_SB.PCI0.LPCB.EC.ECWR (0xcc, RefOf(\_SB.PCI0.LPCB.EC.KLBE))
+		}
+		Case (0xbb)
+		{
+			\_SB.PCI0.LPCB.EC.ECWR (0xbb, RefOf(\_SB.PCI0.LPCB.EC.KLBE))
+		}
+		Case (0xaa)
+		{
+			\_SB.PCI0.LPCB.EC.ECWR (0xaa, RefOf(\_SB.PCI0.LPCB.EC.KLBE))
+		}
+	}
+#else
 	/* Restore EC settings from CMOS */
 	Switch (ToInteger (\_SB.PCI0.LPCB.TPLC))
 	{
@@ -134,4 +248,7 @@ Method (RWAK, 1, Serialized)
 			\_SB.PCI0.LPCB.EC.ECWR (0xaa,  RefOf(\_SB.PCI0.LPCB.EC.KLBE))
 		}
 	}
+#endif
+
+	Return (Arg0)
 }
diff --git a/src/ec/starlabs/merlin/ite.c b/src/ec/starlabs/merlin/ite.c
index 8ce556a308..4240d7dbef 100644
--- a/src/ec/starlabs/merlin/ite.c
+++ b/src/ec/starlabs/merlin/ite.c
@@ -12,8 +12,8 @@
 #include "option_table.h"
 #include "ec.h"
 
-#define ITE_IT5570	0x5570
-#define ITE_IT8987	0x8987
+#define ITE_IT5570 0x5570
+#define ITE_IT8987 0x8987
 
 uint16_t ec_get_version(void)
 {
@@ -25,20 +25,17 @@ static uint8_t get_cmos_value(uint32_t bit, uint32_t length)
 	uint32_t byte, byte_bit;
 	uint8_t uchar;
 
-	byte = bit / 8; // find the byte where the data starts
+	byte = bit / 8;     // find the byte where the data starts
 	byte_bit = bit % 8; // find the bit in the byte where the data starts
 
 	uchar = cmos_read(byte); // load the byte
-	uchar >>= byte_bit;     // shift the bits to byte align
+	uchar >>= byte_bit;      // shift the bits to byte align
 	// clear unspecified bits
 	return uchar & ((1U << length) - 1);
 }
 
-static uint8_t get_ec_value_from_option(const char *name,
-					uint32_t fallback,
-					const uint8_t *lut,
-					size_t lut_size,
-					uint32_t cmos_start_bit,
+static uint8_t get_ec_value_from_option(const char *name, uint32_t fallback, const uint8_t *lut,
+					size_t lut_size, uint32_t cmos_start_bit,
 					uint32_t cmos_length)
 {
 	/*
@@ -69,8 +66,7 @@ static uint8_t get_ec_value_from_option(const char *name,
 
 static uint16_t ec_get_chip_id(unsigned int port)
 {
-	return (pnp_read_index(port, ITE_CHIPID1) << 8) |
-		pnp_read_index(port, ITE_CHIPID2);
+	return (pnp_read_index(port, ITE_CHIPID1) << 8) | pnp_read_index(port, ITE_CHIPID2);
 }
 
 static void merlin_init(struct device *dev)
@@ -122,21 +118,11 @@ static void merlin_init(struct device *dev)
 	 * Default:	30 Seconds
 	 *
 	 */
-	const uint8_t kbl_timeout[] = {
-		SEC_30,
-		MIN_1,
-		MIN_3,
-		MIN_5,
-		NEVER
-	};
+	const uint8_t kbl_timeout[] = {SEC_30, MIN_1, MIN_3, MIN_5, NEVER};
 
 	ec_write(ECRAM_KBL_TIMEOUT,
-		get_ec_value_from_option("kbl_timeout",
-					 SEC_30,
-					 kbl_timeout,
-					 ARRAY_SIZE(kbl_timeout),
-					 UINT_MAX,
-					 UINT_MAX));
+		 get_ec_value_from_option("kbl_timeout", SEC_30, kbl_timeout,
+					  ARRAY_SIZE(kbl_timeout), UINT_MAX, UINT_MAX));
 
 	/*
 	 * Fn Ctrl Reverse
@@ -147,18 +133,11 @@ static void merlin_init(struct device *dev)
 	 * Default:	Disabled
 	 *
 	 */
-	const uint8_t fn_ctrl_swap[] = {
-		FN_CTRL,
-		CTRL_FN
-	};
+	const uint8_t fn_ctrl_swap[] = {FN_CTRL, CTRL_FN};
 
 	ec_write(ECRAM_FN_CTRL_REVERSE,
-		get_ec_value_from_option("fn_ctrl_swap",
-					 FN_CTRL,
-					 fn_ctrl_swap,
-					 ARRAY_SIZE(fn_ctrl_swap),
-					 UINT_MAX,
-					 UINT_MAX));
+		 get_ec_value_from_option("fn_ctrl_swap", FN_CTRL, fn_ctrl_swap,
+					  ARRAY_SIZE(fn_ctrl_swap), UINT_MAX, UINT_MAX));
 
 	/*
 	 * Maximum Charge Level
@@ -169,20 +148,12 @@ static void merlin_init(struct device *dev)
 	 * Default:	100%
 	 *
 	 */
-	const uint8_t max_charge[] = {
-		CHARGE_100,
-		CHARGE_80,
-		CHARGE_60
-	};
+	const uint8_t max_charge[] = {CHARGE_100, CHARGE_80, CHARGE_60};
 
 	if (CONFIG(EC_STARLABS_MAX_CHARGE))
 		ec_write(ECRAM_MAX_CHARGE,
-			get_ec_value_from_option("max_charge",
-						 CHARGE_100,
-						 max_charge,
-						 ARRAY_SIZE(max_charge),
-						 UINT_MAX,
-						 UINT_MAX));
+			 get_ec_value_from_option("max_charge", CHARGE_100, max_charge,
+						  ARRAY_SIZE(max_charge), UINT_MAX, UINT_MAX));
 
 	/*
 	 * Fan Mode
@@ -193,21 +164,12 @@ static void merlin_init(struct device *dev)
 	 * Default:	Normal
 	 *
 	 */
-	const uint8_t fan_mode[] = {
-		FAN_NORMAL,
-		FAN_AGGRESSIVE,
-		FAN_QUIET,
-		FAN_DISABLED
-	};
+	const uint8_t fan_mode[] = {FAN_NORMAL, FAN_AGGRESSIVE, FAN_QUIET, FAN_DISABLED};
 
 	if (CONFIG(EC_STARLABS_FAN))
 		ec_write(ECRAM_FAN_MODE,
-			get_ec_value_from_option("fan_mode",
-						 FAN_NORMAL,
-						 fan_mode,
-						 ARRAY_SIZE(fan_mode),
-						 UINT_MAX,
-						 UINT_MAX));
+			 get_ec_value_from_option("fan_mode", FAN_NORMAL, fan_mode,
+						  ARRAY_SIZE(fan_mode), UINT_MAX, UINT_MAX));
 
 	/*
 	 * Function Lock
@@ -219,18 +181,13 @@ static void merlin_init(struct device *dev)
 	 *
 	 */
 #ifdef CMOS_VLEN_fn_lock_state
-	const uint8_t fn_lock_state[] = {
-		UNLOCKED,
-		LOCKED
-	};
+	const uint8_t fn_lock_state[] = {UNLOCKED, LOCKED};
 
 	ec_write(ECRAM_FN_LOCK_STATE,
-		get_ec_value_from_option("fn_lock_state",
-					 UNLOCKED,
-					 fn_lock_state,
-					 ARRAY_SIZE(fn_lock_state),
-					 CMOS_VSTART_fn_lock_state,
-					 CMOS_VLEN_fn_lock_state));
+		 get_ec_value_from_option(
+			 "fn_lock_state", UNLOCKED, fn_lock_state, ARRAY_SIZE(fn_lock_state),
+			 CONFIG(USE_OPTION_TABLE) ? CMOS_VSTART_fn_lock_state : UINT_MAX,
+			 CONFIG(USE_OPTION_TABLE) ? CMOS_VLEN_fn_lock_state : UINT_MAX));
 #endif
 
 	/*
@@ -243,18 +200,14 @@ static void merlin_init(struct device *dev)
 	 *
 	 */
 #ifdef CMOS_VSTART_trackpad_state
-	const uint8_t trackpad_state[] = {
-		TRACKPAD_ENABLED,
-		TRACKPAD_DISABLED
-	};
+	const uint8_t trackpad_state[] = {TRACKPAD_ENABLED, TRACKPAD_DISABLED};
 
 	ec_write(ECRAM_TRACKPAD_STATE,
-		get_ec_value_from_option("trackpad_state",
-					 TRACKPAD_ENABLED,
-					 trackpad_state,
-					 ARRAY_SIZE(trackpad_state),
-					 CMOS_VSTART_trackpad_state,
-					 CMOS_VLEN_trackpad_state));
+		 get_ec_value_from_option(
+			 "trackpad_state", TRACKPAD_ENABLED, trackpad_state,
+			 ARRAY_SIZE(trackpad_state),
+			 CONFIG(USE_OPTION_TABLE) ? CMOS_VSTART_trackpad_state : UINT_MAX,
+			 CONFIG(USE_OPTION_TABLE) ? CMOS_VLEN_trackpad_state : UINT_MAX));
 #endif
 
 	/*
@@ -267,24 +220,19 @@ static void merlin_init(struct device *dev)
 	 *
 	 */
 #ifdef CMOS_VSTART_kbl_brightness
-	const uint8_t kbl_brightness[] = {
-		KBL_ON,
-		KBL_OFF,
-		KBL_LOW,
-		KBL_HIGH
-	};
+	const uint8_t kbl_brightness[] = {KBL_ON, KBL_OFF, KBL_LOW, KBL_HIGH};
 
 	ec_write(ECRAM_KBL_BRIGHTNESS,
-		get_ec_value_from_option("kbl_brightness",
-			CONFIG(EC_STARLABS_KBL_LEVELS) ? 2 : 0,
-			kbl_brightness,
-			ARRAY_SIZE(kbl_brightness),
-			CMOS_VSTART_kbl_brightness,
-			CMOS_VLEN_kbl_brightness));
-
+		 get_ec_value_from_option(
+			 "kbl_brightness",
+			 CONFIG(USE_OPTION_TABLE) ?
+				 (CONFIG(EC_STARLABS_KBL_LEVELS) ? 2 : 0) :
+				 (CONFIG(EC_STARLABS_KBL_LEVELS) ? KBL_LOW : KBL_ON),
+			 kbl_brightness, ARRAY_SIZE(kbl_brightness),
+			 CONFIG(USE_OPTION_TABLE) ? CMOS_VSTART_kbl_brightness : UINT_MAX,
+			 CONFIG(USE_OPTION_TABLE) ? CMOS_VLEN_kbl_brightness : UINT_MAX));
 #endif
 
-
 	/*
 	 * Keyboard Backlight State
 	 *
@@ -308,20 +256,13 @@ static void merlin_init(struct device *dev)
 	 * Default:	0.5C
 	 *
 	 */
-	const uint8_t charging_speed[] = {
-		SPEED_1_0C,
-		SPEED_0_5C,
-		SPEED_0_2C
-	};
+	const uint8_t charging_speed[] = {SPEED_1_0C, SPEED_0_5C, SPEED_0_2C};
 
 	if (CONFIG(EC_STARLABS_CHARGING_SPEED))
 		ec_write(ECRAM_CHARGING_SPEED,
-			get_ec_value_from_option("charging_speed",
-				SPEED_0_5C,
-				charging_speed,
-				ARRAY_SIZE(charging_speed),
-				UINT_MAX,
-				UINT_MAX));
+			 get_ec_value_from_option("charging_speed", SPEED_0_5C, charging_speed,
+						  ARRAY_SIZE(charging_speed), UINT_MAX,
+						  UINT_MAX));
 
 	/*
 	 * Lid Switch
@@ -332,20 +273,12 @@ static void merlin_init(struct device *dev)
 	 * Default:	0
 	 *
 	 */
-	const uint8_t lid_switch[] = {
-		SWITCH_NORMAL,
-		SWITCH_SLEEP_ONLY,
-		SWITCH_DISABLED
-	};
+	const uint8_t lid_switch[] = {SWITCH_NORMAL, SWITCH_SLEEP_ONLY, SWITCH_DISABLED};
 
 	if (CONFIG(EC_STARLABS_LID_SWITCH))
 		ec_write(ECRAM_LID_SWITCH,
-			get_ec_value_from_option("lid_switch",
-				SWITCH_NORMAL,
-				lid_switch,
-				ARRAY_SIZE(lid_switch),
-				UINT_MAX,
-				UINT_MAX));
+			 get_ec_value_from_option("lid_switch", SWITCH_NORMAL, lid_switch,
+						  ARRAY_SIZE(lid_switch), UINT_MAX, UINT_MAX));
 
 	/*
 	 * Power LED Brightness
@@ -356,20 +289,13 @@ static void merlin_init(struct device *dev)
 	 * Default:	0
 	 *
 	 */
-	const uint8_t led_brightness[] = {
-		LED_NORMAL,
-		LED_REDUCED,
-		LED_OFF
-	};
+	const uint8_t led_brightness[] = {LED_NORMAL, LED_REDUCED, LED_OFF};
 
 	if (CONFIG(EC_STARLABS_POWER_LED))
 		ec_write(ECRAM_POWER_LED,
-			get_ec_value_from_option("power_led",
-				LED_NORMAL,
-				led_brightness,
-				ARRAY_SIZE(led_brightness),
-				UINT_MAX,
-				UINT_MAX));
+			 get_ec_value_from_option("power_led", LED_NORMAL, led_brightness,
+						  ARRAY_SIZE(led_brightness), UINT_MAX,
+						  UINT_MAX));
 
 	/*
 	 * Charge LED Brightness
@@ -383,18 +309,15 @@ static void merlin_init(struct device *dev)
 
 	if (CONFIG(EC_STARLABS_CHARGE_LED))
 		ec_write(ECRAM_CHARGE_LED,
-			get_ec_value_from_option("charge_led",
-				LED_NORMAL,
-				led_brightness,
-				ARRAY_SIZE(led_brightness),
-				UINT_MAX,
-				UINT_MAX));
+			 get_ec_value_from_option("charge_led", LED_NORMAL, led_brightness,
+						  ARRAY_SIZE(led_brightness), UINT_MAX,
+						  UINT_MAX));
 }
 
 static struct device_operations ops = {
-	.init		= merlin_init,
-	.read_resources	= noop_read_resources,
-	.set_resources	= noop_set_resources,
+	.init = merlin_init,
+	.read_resources = noop_read_resources,
+	.set_resources = noop_set_resources,
 };
 
 static struct pnp_info pnp_dev_info[] = {
diff --git a/src/ec/starlabs/merlin/nuvoton.c b/src/ec/starlabs/merlin/nuvoton.c
index 6b39fe0ebf..36212f63c4 100644
--- a/src/ec/starlabs/merlin/nuvoton.c
+++ b/src/ec/starlabs/merlin/nuvoton.c
@@ -12,7 +12,6 @@
 #include "option_table.h"
 #include "ec.h"
 
-
 uint16_t ec_get_version(void)
 {
 	return (ec_read(ECRAM_MAJOR_VERSION) << 8) | ec_read(ECRAM_MINOR_VERSION);
@@ -23,32 +22,43 @@ static uint8_t get_cmos_value(uint32_t bit, uint32_t length)
 	uint32_t byte, byte_bit;
 	uint8_t uchar;
 
-	byte = bit / 8; // find the byte where the data starts
+	byte = bit / 8;     // find the byte where the data starts
 	byte_bit = bit % 8; // find the bit in the byte where the data starts
 
 	uchar = cmos_read(byte); // load the byte
-	uchar >>= byte_bit;     // shift the bits to byte align
+	uchar >>= byte_bit;      // shift the bits to byte align
 	// clear unspecified bits
 	return uchar & ((1U << length) - 1);
 }
 
-static uint8_t get_ec_value_from_option(const char *name,
-					uint32_t fallback,
-					const uint8_t *lut,
-					size_t lut_size,
-					uint32_t cmos_start_bit,
+static uint8_t get_ec_value_from_option(const char *name, uint32_t fallback, const uint8_t *lut,
+					size_t lut_size, uint32_t cmos_start_bit,
 					uint32_t cmos_length)
 {
-	unsigned int index;
+	/*
+	 * CMOS-backed EC options store an index (see cmos.layout and ACPI
+	 * RPTS/RWAK mappings), while the option backend stores the EC's raw
+	 * values (e.g. 0xaa/0xbb/0xdd).
+	 */
+	if (cmos_start_bit != UINT_MAX) {
+		unsigned int index = get_cmos_value(cmos_start_bit, cmos_length);
 
-	if (cmos_start_bit != UINT_MAX)
-		index = get_cmos_value(cmos_start_bit, cmos_length);
-	else
-		index = get_uint_option(name, fallback);
+		if (index >= lut_size)
+			index = fallback;
+		if (index >= lut_size)
+			index = 0;
 
-	if (index >= lut_size)
-		index = fallback;
-	return lut[index];
+		return lut[index];
+	}
+
+	const uint8_t value = get_uint_option(name, fallback);
+
+	/* Check if the value exists in the LUT array */
+	for (size_t i = 0; i < lut_size; i++)
+		if (lut[i] == value)
+			return value;
+
+	return fallback;
 }
 
 static uint16_t ec_get_chip_id(unsigned int port)
@@ -77,7 +87,7 @@ static void merlin_init(struct device *dev)
 
 	if (chip_id != NUVOTON_CHIPID_VAL) {
 		printk(BIOS_ERR, "NUVOTON: Expected chip ID 0x%04x, but got 0x%04x instead.\n",
-			NUVOTON_CHIPID_VAL, chip_id);
+		       NUVOTON_CHIPID_VAL, chip_id);
 		return;
 	}
 
@@ -103,21 +113,11 @@ static void merlin_init(struct device *dev)
 	 * Default:	30 Seconds
 	 *
 	 */
-	const uint8_t kbl_timeout[] = {
-		SEC_30,
-		MIN_1,
-		MIN_3,
-		MIN_5,
-		NEVER
-	};
+	const uint8_t kbl_timeout[] = {SEC_30, MIN_1, MIN_3, MIN_5, NEVER};
 
 	ec_write(ECRAM_KBL_TIMEOUT,
-		get_ec_value_from_option("kbl_timeout",
-					 0,
-					 kbl_timeout,
-					 ARRAY_SIZE(kbl_timeout),
-					 UINT_MAX,
-					 UINT_MAX));
+		 get_ec_value_from_option("kbl_timeout", 0, kbl_timeout,
+					  ARRAY_SIZE(kbl_timeout), UINT_MAX, UINT_MAX));
 
 	/*
 	 * Fn Ctrl Reverse
@@ -128,18 +128,11 @@ static void merlin_init(struct device *dev)
 	 * Default:	Disabled
 	 *
 	 */
-	const uint8_t fn_ctrl_swap[] = {
-		FN_CTRL,
-		CTRL_FN
-	};
+	const uint8_t fn_ctrl_swap[] = {FN_CTRL, CTRL_FN};
 
 	ec_write(ECRAM_FN_CTRL_REVERSE,
-		get_ec_value_from_option("fn_ctrl_swap",
-					 0,
-					 fn_ctrl_swap,
-					 ARRAY_SIZE(fn_ctrl_swap),
-					 UINT_MAX,
-					 UINT_MAX));
+		 get_ec_value_from_option("fn_ctrl_swap", 0, fn_ctrl_swap,
+					  ARRAY_SIZE(fn_ctrl_swap), UINT_MAX, UINT_MAX));
 
 	/*
 	 * Maximum Charge Level
@@ -150,20 +143,12 @@ static void merlin_init(struct device *dev)
 	 * Default:	100%
 	 *
 	 */
-	const uint8_t max_charge[] = {
-		CHARGE_100,
-		CHARGE_80,
-		CHARGE_60
-	};
+	const uint8_t max_charge[] = {CHARGE_100, CHARGE_80, CHARGE_60};
 
 	if (CONFIG(EC_STARLABS_MAX_CHARGE))
 		ec_write(ECRAM_MAX_CHARGE,
-			get_ec_value_from_option("max_charge",
-						 0,
-						 max_charge,
-						 ARRAY_SIZE(max_charge),
-						 UINT_MAX,
-						 UINT_MAX));
+			 get_ec_value_from_option("max_charge", 0, max_charge,
+						  ARRAY_SIZE(max_charge), UINT_MAX, UINT_MAX));
 
 	/*
 	 * Fan Mode
@@ -174,20 +159,12 @@ static void merlin_init(struct device *dev)
 	 * Default:	Normal
 	 *
 	 */
-	const uint8_t fan_mode[] = {
-		FAN_NORMAL,
-		FAN_AGGRESSIVE,
-		FAN_QUIET
-	};
+	const uint8_t fan_mode[] = {FAN_NORMAL, FAN_AGGRESSIVE, FAN_QUIET};
 
 	if (CONFIG(EC_STARLABS_FAN))
 		ec_write(ECRAM_FAN_MODE,
-			get_ec_value_from_option("fan_mode",
-						 0,
-						 fan_mode,
-						 ARRAY_SIZE(fan_mode),
-						 UINT_MAX,
-						 UINT_MAX));
+			 get_ec_value_from_option("fan_mode", 0, fan_mode, ARRAY_SIZE(fan_mode),
+						  UINT_MAX, UINT_MAX));
 
 	/*
 	 * Function Lock
@@ -199,18 +176,13 @@ static void merlin_init(struct device *dev)
 	 *
 	 */
 #ifdef CMOS_VLEN_fn_lock_state
-	const uint8_t fn_lock_state[] = {
-		UNLOCKED,
-		LOCKED
-	};
+	const uint8_t fn_lock_state[] = {UNLOCKED, LOCKED};
 
 	ec_write(ECRAM_FN_LOCK_STATE,
-		get_ec_value_from_option("fn_lock_state",
-					 1,
-					 fn_lock_state,
-					 ARRAY_SIZE(fn_lock_state),
-					 CMOS_VSTART_fn_lock_state,
-					 CMOS_VLEN_fn_lock_state));
+		 get_ec_value_from_option(
+			 "fn_lock_state", 1, fn_lock_state, ARRAY_SIZE(fn_lock_state),
+			 CONFIG(USE_OPTION_TABLE) ? CMOS_VSTART_fn_lock_state : UINT_MAX,
+			 CONFIG(USE_OPTION_TABLE) ? CMOS_VLEN_fn_lock_state : UINT_MAX));
 #endif
 
 	/*
@@ -223,18 +195,13 @@ static void merlin_init(struct device *dev)
 	 *
 	 */
 #ifdef CMOS_VSTART_trackpad_state
-	const uint8_t trackpad_state[] = {
-		TRACKPAD_ENABLED,
-		TRACKPAD_DISABLED
-	};
+	const uint8_t trackpad_state[] = {TRACKPAD_ENABLED, TRACKPAD_DISABLED};
 
 	ec_write(ECRAM_TRACKPAD_STATE,
-		get_ec_value_from_option("trackpad_state",
-					 0,
-					 trackpad_state,
-					 ARRAY_SIZE(trackpad_state),
-					 CMOS_VSTART_trackpad_state,
-					 CMOS_VLEN_trackpad_state));
+		 get_ec_value_from_option(
+			 "trackpad_state", 0, trackpad_state, ARRAY_SIZE(trackpad_state),
+			 CONFIG(USE_OPTION_TABLE) ? CMOS_VSTART_trackpad_state : UINT_MAX,
+			 CONFIG(USE_OPTION_TABLE) ? CMOS_VLEN_trackpad_state : UINT_MAX));
 #endif
 
 	/*
@@ -247,24 +214,20 @@ static void merlin_init(struct device *dev)
 	 *
 	 */
 #ifdef CMOS_VSTART_kbl_brightness
-	const uint8_t kbl_brightness[] = {
-		KBL_ON,
-		KBL_OFF,
-		KBL_LOW,
-		KBL_HIGH
-	};
+	const uint8_t kbl_brightness[] = {KBL_ON, KBL_OFF, KBL_LOW, KBL_HIGH};
 
 	ec_write(ECRAM_KBL_BRIGHTNESS,
-		get_ec_value_from_option("kbl_brightness",
-			CONFIG(EC_STARLABS_KBL_LEVELS) ? 2 : 0,
-			kbl_brightness,
-			ARRAY_SIZE(kbl_brightness),
-			CMOS_VSTART_kbl_brightness,
-			CMOS_VLEN_kbl_brightness));
+		 get_ec_value_from_option(
+			 "kbl_brightness",
+			 CONFIG(USE_OPTION_TABLE) ?
+				 (CONFIG(EC_STARLABS_KBL_LEVELS) ? 2 : 0) :
+				 (CONFIG(EC_STARLABS_KBL_LEVELS) ? KBL_LOW : KBL_ON),
+			 kbl_brightness, ARRAY_SIZE(kbl_brightness),
+			 CONFIG(USE_OPTION_TABLE) ? CMOS_VSTART_kbl_brightness : UINT_MAX,
+			 CONFIG(USE_OPTION_TABLE) ? CMOS_VLEN_kbl_brightness : UINT_MAX));
 
 #endif
 
-
 	/*
 	 * Keyboard Backlight State
 	 *
@@ -281,9 +244,9 @@ static void merlin_init(struct device *dev)
 }
 
 static struct device_operations ops = {
-	.init		= merlin_init,
-	.read_resources	= noop_read_resources,
-	.set_resources	= noop_set_resources,
+	.init = merlin_init,
+	.read_resources = noop_read_resources,
+	.set_resources = noop_set_resources,
 };
 
 static struct pnp_info pnp_dev_info[] = {
@@ -299,7 +262,7 @@ static struct pnp_info pnp_dev_info[] = {
 	{ NULL, NUVOTON_PM1,	PNP_IO0 | PNP_IO1 | PNP_IRQ0,	0x07ff,	0x07ff,	},
 	/* Power Management I/F Channel 2 (PMC2) */
 	{ NULL, NUVOTON_PM2,	PNP_IO0 | PNP_IO1 | PNP_IO2 | PNP_IRQ0,	0x07fc,
-				0x07fc, 0xfff0,					},
+					0x07fc, 0xfff0,					},
 	/* Power Management I/F Channel 3 (PMC3) */
 	{ NULL, NUVOTON_PM3,	PNP_IO0 | PNP_IO1 | PNP_IRQ0,	0x07ff,	0x07ff,	},
 	/* Extended Shared Memory (ESHM) */

From cfbf8f3953add1a1f6280e2e754682b517803c60 Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Mon, 2 Mar 2026 10:21:41 +0000
Subject: [PATCH 3563/3886] starlabs: drop CMOS option tables

Remove CMOS option tables and defaults from Star Labs boards now that
EC state is persisted through EFI variable store options.

Drop remaining Merlin EC CMOS plumbing (RTC reads and ACPI fields) and
read settings only via the option backend.

Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I3cc7f6240adc4b396912d566c7de176d4d2cb92b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91305
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
---
 src/ec/starlabs/merlin/acpi/cmos.asl          |  17 ---
 src/ec/starlabs/merlin/acpi/ec.asl            |   2 -
 src/ec/starlabs/merlin/acpi/suspend.asl       | 116 ------------------
 src/ec/starlabs/merlin/ite.c                  |  83 +++----------
 src/ec/starlabs/merlin/nuvoton.c              |  74 +++--------
 src/mainboard/starlabs/adl/Kconfig            |   2 -
 src/mainboard/starlabs/adl/cmos.default       |   6 -
 .../starlabs/adl/variants/hz/cmos.layout      |  46 -------
 .../starlabs/adl/variants/i5/cmos.layout      |  36 ------
 .../starlabs/adl/variants/y2/cmos.layout      |  36 ------
 src/mainboard/starlabs/lite/Kconfig           |   2 -
 src/mainboard/starlabs/lite/cmos.default      |   6 -
 src/mainboard/starlabs/lite/cmos.layout       |  43 -------
 src/mainboard/starlabs/starbook/Kconfig       |   2 -
 src/mainboard/starlabs/starbook/cmos.default  |   6 -
 src/mainboard/starlabs/starbook/cmos.layout   |  46 -------
 src/mainboard/starlabs/starfighter/Kconfig    |   2 -
 .../starlabs/starfighter/cmos.default         |   6 -
 .../starlabs/starfighter/cmos.layout          |  46 -------
 19 files changed, 32 insertions(+), 545 deletions(-)
 delete mode 100644 src/ec/starlabs/merlin/acpi/cmos.asl
 delete mode 100644 src/mainboard/starlabs/adl/cmos.default
 delete mode 100644 src/mainboard/starlabs/adl/variants/hz/cmos.layout
 delete mode 100644 src/mainboard/starlabs/adl/variants/i5/cmos.layout
 delete mode 100644 src/mainboard/starlabs/adl/variants/y2/cmos.layout
 delete mode 100644 src/mainboard/starlabs/lite/cmos.default
 delete mode 100644 src/mainboard/starlabs/lite/cmos.layout
 delete mode 100644 src/mainboard/starlabs/starbook/cmos.default
 delete mode 100644 src/mainboard/starlabs/starbook/cmos.layout
 delete mode 100644 src/mainboard/starlabs/starfighter/cmos.default
 delete mode 100644 src/mainboard/starlabs/starfighter/cmos.layout

diff --git a/src/ec/starlabs/merlin/acpi/cmos.asl b/src/ec/starlabs/merlin/acpi/cmos.asl
deleted file mode 100644
index 7ff0102b37..0000000000
--- a/src/ec/starlabs/merlin/acpi/cmos.asl
+++ /dev/null
@@ -1,17 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-OperationRegion (CMS2, SystemIO, 0x72, 0x2)
-Field (CMS2, ByteAcc, NoLock, Preserve)
-{
-	IND2, 8,
-	DAT2, 8,
-}
-
-IndexField (IND2, DAT2, ByteAcc, NoLock, Preserve)
-{
-	Offset (0x80),
-	FLKC, 8,		// Function Lock State
-	TPLC, 8,		// Trackpad State
-	KLBC, 8,		// Keyboard Backlight Brightness
-	KLSC, 8,		// Keyboard Backlight State
-}
diff --git a/src/ec/starlabs/merlin/acpi/ec.asl b/src/ec/starlabs/merlin/acpi/ec.asl
index ae5092772f..84113c343d 100644
--- a/src/ec/starlabs/merlin/acpi/ec.asl
+++ b/src/ec/starlabs/merlin/acpi/ec.asl
@@ -2,8 +2,6 @@
 
 Scope (\_SB.PCI0.LPCB)
 {
-	#include "cmos.asl"
-
 	Device (EC)
 	{
 		Name (_HID, EisaId ("PNP0C09"))
diff --git a/src/ec/starlabs/merlin/acpi/suspend.asl b/src/ec/starlabs/merlin/acpi/suspend.asl
index 0ccce6f84b..9c280dba6f 100644
--- a/src/ec/starlabs/merlin/acpi/suspend.asl
+++ b/src/ec/starlabs/merlin/acpi/suspend.asl
@@ -69,66 +69,6 @@ Method (RPTS, 1, Serialized)
 	EOSV (EOFL, \_SB.PCI0.LPCB.EC.ECRD (RefOf (\_SB.PCI0.LPCB.EC.FLKE)))
 	EOSV (EOKS, \_SB.PCI0.LPCB.EC.ECRD (RefOf (\_SB.PCI0.LPCB.EC.KLSE)))
 	EOSV (EOKB, \_SB.PCI0.LPCB.EC.ECRD (RefOf (\_SB.PCI0.LPCB.EC.KLBE)))
-#else
-	/* Store current EC settings in CMOS */
-	Switch (ToInteger (\_SB.PCI0.LPCB.EC.ECRD (RefOf (\_SB.PCI0.LPCB.EC.TPLE))))
-	{
-		// 0x00 == Enabled    == 0x00
-		// 0x11 == Re-enabled == 0x00
-		// 0x22 == Disabled   == 0x01
-		Case (0x00)
-		{
-			Store (0x00, \_SB.PCI0.LPCB.TPLC)
-		}
-		Case (0x11)
-		{
-			Store (0x00, \_SB.PCI0.LPCB.TPLC)
-		}
-		Case (0x22)
-		{
-			Store (0x01, \_SB.PCI0.LPCB.TPLC)
-		}
-	}
-
-	Store (\_SB.PCI0.LPCB.EC.ECRD (RefOf (\_SB.PCI0.LPCB.EC.FLKE)), \_SB.PCI0.LPCB.FLKC)
-
-	Switch (ToInteger (\_SB.PCI0.LPCB.EC.ECRD (RefOf (\_SB.PCI0.LPCB.EC.KLSE))))
-	{
-		// 0x00 == Disabled == 0x00
-		// 0xdd == Enabled  == 0x01
-		Case (0x00)
-		{
-			Store (0x00, \_SB.PCI0.LPCB.KLSC)
-		}
-		Case (0xdd)
-		{
-			Store (0x01, \_SB.PCI0.LPCB.KLSC)
-		}
-	}
-
-	Switch (ToInteger (\_SB.PCI0.LPCB.EC.ECRD (RefOf (\_SB.PCI0.LPCB.EC.KLBE))))
-	{
-		// 0xdd == On   == 0x00
-		// 0xcc == Off  == 0x01
-		// 0xbb == Low  == 0x02
-		// 0xaa == High == 0x03
-		Case (0xdd)
-		{
-			Store (0x00, \_SB.PCI0.LPCB.KLBC)
-		}
-		Case (0xcc)
-		{
-			Store (0x01, \_SB.PCI0.LPCB.KLBC)
-		}
-		Case (0xbb)
-		{
-			Store (0x02, \_SB.PCI0.LPCB.KLBC)
-		}
-		Case (0xaa)
-		{
-			Store (0x03, \_SB.PCI0.LPCB.KLBC)
-		}
-	}
 #endif
 
 	/*
@@ -192,62 +132,6 @@ Method (RWAK, 1, Serialized)
 			\_SB.PCI0.LPCB.EC.ECWR (0xaa, RefOf(\_SB.PCI0.LPCB.EC.KLBE))
 		}
 	}
-#else
-	/* Restore EC settings from CMOS */
-	Switch (ToInteger (\_SB.PCI0.LPCB.TPLC))
-	{
-		// 0x00 == Enabled    == 0x00
-		// 0x00 == Re-enabled == 0x11
-		// 0x01 == Disabled   == 0x22
-		Case (0x00)
-		{
-			\_SB.PCI0.LPCB.EC.ECWR (0x00,  RefOf(\_SB.PCI0.LPCB.EC.TPLE))
-		}
-		Case (0x01)
-		{
-			\_SB.PCI0.LPCB.EC.ECWR (0x22,  RefOf(\_SB.PCI0.LPCB.EC.TPLE))
-		}
-	}
-
-	\_SB.PCI0.LPCB.EC.ECWR (\_SB.PCI0.LPCB.FLKC,  RefOf(\_SB.PCI0.LPCB.EC.FLKE))
-
-	Switch (ToInteger (\_SB.PCI0.LPCB.KLSC))
-	{
-		// 0x00 == Disabled == 0x00
-		// 0x01 == Enabled  == 0xdd
-		Case (0x00)
-		{
-			\_SB.PCI0.LPCB.EC.ECWR (0x00,  RefOf(\_SB.PCI0.LPCB.EC.KLSE))
-		}
-		Case (0x01)
-		{
-			\_SB.PCI0.LPCB.EC.ECWR (0xdd,  RefOf(\_SB.PCI0.LPCB.EC.KLSE))
-		}
-	}
-
-	Switch (ToInteger (\_SB.PCI0.LPCB.KLBC))
-	{
-		// 0x00 == On   == 0xdd
-		// 0x01 == Off  == 0xcc
-		// 0x02 == Low  == 0xbb
-		// 0x03 == High == 0xaa
-		Case (0x00)
-		{
-			\_SB.PCI0.LPCB.EC.ECWR (0xdd,  RefOf(\_SB.PCI0.LPCB.EC.KLBE))
-		}
-		Case (0x01)
-		{
-			\_SB.PCI0.LPCB.EC.ECWR (0xcc,  RefOf(\_SB.PCI0.LPCB.EC.KLBE))
-		}
-		Case (0x02)
-		{
-			\_SB.PCI0.LPCB.EC.ECWR (0xbb,  RefOf(\_SB.PCI0.LPCB.EC.KLBE))
-		}
-		Case (0x03)
-		{
-			\_SB.PCI0.LPCB.EC.ECWR (0xaa,  RefOf(\_SB.PCI0.LPCB.EC.KLBE))
-		}
-	}
 #endif
 
 	Return (Arg0)
diff --git a/src/ec/starlabs/merlin/ite.c b/src/ec/starlabs/merlin/ite.c
index 4240d7dbef..a3369700c3 100644
--- a/src/ec/starlabs/merlin/ite.c
+++ b/src/ec/starlabs/merlin/ite.c
@@ -5,11 +5,9 @@
 #include <device/pnp.h>
 #include <ec/acpi/ec.h>
 #include <option.h>
-#include <pc80/mc146818rtc.h>
 #include <halt.h>
 
 #include "ecdefs.h"
-#include "option_table.h"
 #include "ec.h"
 
 #define ITE_IT5570 0x5570
@@ -20,40 +18,9 @@ uint16_t ec_get_version(void)
 	return (ec_read(ECRAM_MAJOR_VERSION) << 8) | ec_read(ECRAM_MINOR_VERSION);
 }
 
-static uint8_t get_cmos_value(uint32_t bit, uint32_t length)
+static uint8_t get_ec_value_from_option(const char *name, uint8_t fallback, const uint8_t *lut,
+					size_t lut_size)
 {
-	uint32_t byte, byte_bit;
-	uint8_t uchar;
-
-	byte = bit / 8;     // find the byte where the data starts
-	byte_bit = bit % 8; // find the bit in the byte where the data starts
-
-	uchar = cmos_read(byte); // load the byte
-	uchar >>= byte_bit;      // shift the bits to byte align
-	// clear unspecified bits
-	return uchar & ((1U << length) - 1);
-}
-
-static uint8_t get_ec_value_from_option(const char *name, uint32_t fallback, const uint8_t *lut,
-					size_t lut_size, uint32_t cmos_start_bit,
-					uint32_t cmos_length)
-{
-	/*
-	 * CMOS-backed EC options store an index (see cmos.layout and ACPI
-	 * RPTS/RWAK mappings), while the option backend stores the EC's raw
-	 * values (e.g. 0xaa/0xbb/0xdd).
-	 */
-	if (cmos_start_bit != UINT_MAX) {
-		unsigned int index = get_cmos_value(cmos_start_bit, cmos_length);
-
-		if (index >= lut_size)
-			index = fallback;
-		if (index >= lut_size)
-			index = 0;
-
-		return lut[index];
-	}
-
 	const uint8_t value = get_uint_option(name, fallback);
 
 	/* Check if the value exists in the LUT array */
@@ -94,7 +61,7 @@ static void merlin_init(struct device *dev)
 	}
 
 	/*
-	 * Restore settings from CMOS into EC RAM:
+	 * Restore settings from options into EC RAM:
 	 *
 	 * kbl_timeout
 	 * fn_ctrl_swap
@@ -122,7 +89,7 @@ static void merlin_init(struct device *dev)
 
 	ec_write(ECRAM_KBL_TIMEOUT,
 		 get_ec_value_from_option("kbl_timeout", SEC_30, kbl_timeout,
-					  ARRAY_SIZE(kbl_timeout), UINT_MAX, UINT_MAX));
+					  ARRAY_SIZE(kbl_timeout)));
 
 	/*
 	 * Fn Ctrl Reverse
@@ -137,7 +104,7 @@ static void merlin_init(struct device *dev)
 
 	ec_write(ECRAM_FN_CTRL_REVERSE,
 		 get_ec_value_from_option("fn_ctrl_swap", FN_CTRL, fn_ctrl_swap,
-					  ARRAY_SIZE(fn_ctrl_swap), UINT_MAX, UINT_MAX));
+					  ARRAY_SIZE(fn_ctrl_swap)));
 
 	/*
 	 * Maximum Charge Level
@@ -153,7 +120,7 @@ static void merlin_init(struct device *dev)
 	if (CONFIG(EC_STARLABS_MAX_CHARGE))
 		ec_write(ECRAM_MAX_CHARGE,
 			 get_ec_value_from_option("max_charge", CHARGE_100, max_charge,
-						  ARRAY_SIZE(max_charge), UINT_MAX, UINT_MAX));
+						  ARRAY_SIZE(max_charge)));
 
 	/*
 	 * Fan Mode
@@ -169,7 +136,7 @@ static void merlin_init(struct device *dev)
 	if (CONFIG(EC_STARLABS_FAN))
 		ec_write(ECRAM_FAN_MODE,
 			 get_ec_value_from_option("fan_mode", FAN_NORMAL, fan_mode,
-						  ARRAY_SIZE(fan_mode), UINT_MAX, UINT_MAX));
+						  ARRAY_SIZE(fan_mode)));
 
 	/*
 	 * Function Lock
@@ -180,15 +147,11 @@ static void merlin_init(struct device *dev)
 	 * Default:	Locked
 	 *
 	 */
-#ifdef CMOS_VLEN_fn_lock_state
 	const uint8_t fn_lock_state[] = {UNLOCKED, LOCKED};
 
 	ec_write(ECRAM_FN_LOCK_STATE,
 		 get_ec_value_from_option(
-			 "fn_lock_state", UNLOCKED, fn_lock_state, ARRAY_SIZE(fn_lock_state),
-			 CONFIG(USE_OPTION_TABLE) ? CMOS_VSTART_fn_lock_state : UINT_MAX,
-			 CONFIG(USE_OPTION_TABLE) ? CMOS_VLEN_fn_lock_state : UINT_MAX));
-#endif
+			 "fn_lock_state", UNLOCKED, fn_lock_state, ARRAY_SIZE(fn_lock_state)));
 
 	/*
 	 * Trackpad State
@@ -199,16 +162,12 @@ static void merlin_init(struct device *dev)
 	 * Default:	Enabled
 	 *
 	 */
-#ifdef CMOS_VSTART_trackpad_state
 	const uint8_t trackpad_state[] = {TRACKPAD_ENABLED, TRACKPAD_DISABLED};
 
 	ec_write(ECRAM_TRACKPAD_STATE,
 		 get_ec_value_from_option(
 			 "trackpad_state", TRACKPAD_ENABLED, trackpad_state,
-			 ARRAY_SIZE(trackpad_state),
-			 CONFIG(USE_OPTION_TABLE) ? CMOS_VSTART_trackpad_state : UINT_MAX,
-			 CONFIG(USE_OPTION_TABLE) ? CMOS_VLEN_trackpad_state : UINT_MAX));
-#endif
+			 ARRAY_SIZE(trackpad_state)));
 
 	/*
 	 * Keyboard Backlight Brightness
@@ -219,19 +178,16 @@ static void merlin_init(struct device *dev)
 	 * Default:	Low
 	 *
 	 */
-#ifdef CMOS_VSTART_kbl_brightness
 	const uint8_t kbl_brightness[] = {KBL_ON, KBL_OFF, KBL_LOW, KBL_HIGH};
 
+	const uint8_t kbl_brightness_fallback =
+		CONFIG(EC_STARLABS_KBL_LEVELS) ? KBL_LOW : KBL_ON;
+
 	ec_write(ECRAM_KBL_BRIGHTNESS,
 		 get_ec_value_from_option(
 			 "kbl_brightness",
-			 CONFIG(USE_OPTION_TABLE) ?
-				 (CONFIG(EC_STARLABS_KBL_LEVELS) ? 2 : 0) :
-				 (CONFIG(EC_STARLABS_KBL_LEVELS) ? KBL_LOW : KBL_ON),
-			 kbl_brightness, ARRAY_SIZE(kbl_brightness),
-			 CONFIG(USE_OPTION_TABLE) ? CMOS_VSTART_kbl_brightness : UINT_MAX,
-			 CONFIG(USE_OPTION_TABLE) ? CMOS_VLEN_kbl_brightness : UINT_MAX));
-#endif
+			 kbl_brightness_fallback,
+			 kbl_brightness, ARRAY_SIZE(kbl_brightness)));
 
 	/*
 	 * Keyboard Backlight State
@@ -261,8 +217,7 @@ static void merlin_init(struct device *dev)
 	if (CONFIG(EC_STARLABS_CHARGING_SPEED))
 		ec_write(ECRAM_CHARGING_SPEED,
 			 get_ec_value_from_option("charging_speed", SPEED_0_5C, charging_speed,
-						  ARRAY_SIZE(charging_speed), UINT_MAX,
-						  UINT_MAX));
+						  ARRAY_SIZE(charging_speed)));
 
 	/*
 	 * Lid Switch
@@ -278,7 +233,7 @@ static void merlin_init(struct device *dev)
 	if (CONFIG(EC_STARLABS_LID_SWITCH))
 		ec_write(ECRAM_LID_SWITCH,
 			 get_ec_value_from_option("lid_switch", SWITCH_NORMAL, lid_switch,
-						  ARRAY_SIZE(lid_switch), UINT_MAX, UINT_MAX));
+						  ARRAY_SIZE(lid_switch)));
 
 	/*
 	 * Power LED Brightness
@@ -294,8 +249,7 @@ static void merlin_init(struct device *dev)
 	if (CONFIG(EC_STARLABS_POWER_LED))
 		ec_write(ECRAM_POWER_LED,
 			 get_ec_value_from_option("power_led", LED_NORMAL, led_brightness,
-						  ARRAY_SIZE(led_brightness), UINT_MAX,
-						  UINT_MAX));
+						  ARRAY_SIZE(led_brightness)));
 
 	/*
 	 * Charge LED Brightness
@@ -310,8 +264,7 @@ static void merlin_init(struct device *dev)
 	if (CONFIG(EC_STARLABS_CHARGE_LED))
 		ec_write(ECRAM_CHARGE_LED,
 			 get_ec_value_from_option("charge_led", LED_NORMAL, led_brightness,
-						  ARRAY_SIZE(led_brightness), UINT_MAX,
-						  UINT_MAX));
+						  ARRAY_SIZE(led_brightness)));
 }
 
 static struct device_operations ops = {
diff --git a/src/ec/starlabs/merlin/nuvoton.c b/src/ec/starlabs/merlin/nuvoton.c
index 36212f63c4..398b12619b 100644
--- a/src/ec/starlabs/merlin/nuvoton.c
+++ b/src/ec/starlabs/merlin/nuvoton.c
@@ -5,11 +5,9 @@
 #include <device/pnp.h>
 #include <ec/acpi/ec.h>
 #include <option.h>
-#include <pc80/mc146818rtc.h>
 #include <halt.h>
 
 #include "ecdefs.h"
-#include "option_table.h"
 #include "ec.h"
 
 uint16_t ec_get_version(void)
@@ -17,40 +15,9 @@ uint16_t ec_get_version(void)
 	return (ec_read(ECRAM_MAJOR_VERSION) << 8) | ec_read(ECRAM_MINOR_VERSION);
 }
 
-static uint8_t get_cmos_value(uint32_t bit, uint32_t length)
+static uint8_t get_ec_value_from_option(const char *name, uint8_t fallback, const uint8_t *lut,
+					size_t lut_size)
 {
-	uint32_t byte, byte_bit;
-	uint8_t uchar;
-
-	byte = bit / 8;     // find the byte where the data starts
-	byte_bit = bit % 8; // find the bit in the byte where the data starts
-
-	uchar = cmos_read(byte); // load the byte
-	uchar >>= byte_bit;      // shift the bits to byte align
-	// clear unspecified bits
-	return uchar & ((1U << length) - 1);
-}
-
-static uint8_t get_ec_value_from_option(const char *name, uint32_t fallback, const uint8_t *lut,
-					size_t lut_size, uint32_t cmos_start_bit,
-					uint32_t cmos_length)
-{
-	/*
-	 * CMOS-backed EC options store an index (see cmos.layout and ACPI
-	 * RPTS/RWAK mappings), while the option backend stores the EC's raw
-	 * values (e.g. 0xaa/0xbb/0xdd).
-	 */
-	if (cmos_start_bit != UINT_MAX) {
-		unsigned int index = get_cmos_value(cmos_start_bit, cmos_length);
-
-		if (index >= lut_size)
-			index = fallback;
-		if (index >= lut_size)
-			index = 0;
-
-		return lut[index];
-	}
-
 	const uint8_t value = get_uint_option(name, fallback);
 
 	/* Check if the value exists in the LUT array */
@@ -92,7 +59,7 @@ static void merlin_init(struct device *dev)
 	}
 
 	/*
-	 * Restore settings from CMOS into EC RAM:
+	 * Restore settings from options into EC RAM:
 	 *
 	 * kbl_timeout
 	 * fn_ctrl_swap
@@ -117,7 +84,7 @@ static void merlin_init(struct device *dev)
 
 	ec_write(ECRAM_KBL_TIMEOUT,
 		 get_ec_value_from_option("kbl_timeout", 0, kbl_timeout,
-					  ARRAY_SIZE(kbl_timeout), UINT_MAX, UINT_MAX));
+					  ARRAY_SIZE(kbl_timeout)));
 
 	/*
 	 * Fn Ctrl Reverse
@@ -132,7 +99,7 @@ static void merlin_init(struct device *dev)
 
 	ec_write(ECRAM_FN_CTRL_REVERSE,
 		 get_ec_value_from_option("fn_ctrl_swap", 0, fn_ctrl_swap,
-					  ARRAY_SIZE(fn_ctrl_swap), UINT_MAX, UINT_MAX));
+					  ARRAY_SIZE(fn_ctrl_swap)));
 
 	/*
 	 * Maximum Charge Level
@@ -148,7 +115,7 @@ static void merlin_init(struct device *dev)
 	if (CONFIG(EC_STARLABS_MAX_CHARGE))
 		ec_write(ECRAM_MAX_CHARGE,
 			 get_ec_value_from_option("max_charge", 0, max_charge,
-						  ARRAY_SIZE(max_charge), UINT_MAX, UINT_MAX));
+						  ARRAY_SIZE(max_charge)));
 
 	/*
 	 * Fan Mode
@@ -163,8 +130,7 @@ static void merlin_init(struct device *dev)
 
 	if (CONFIG(EC_STARLABS_FAN))
 		ec_write(ECRAM_FAN_MODE,
-			 get_ec_value_from_option("fan_mode", 0, fan_mode, ARRAY_SIZE(fan_mode),
-						  UINT_MAX, UINT_MAX));
+			 get_ec_value_from_option("fan_mode", 0, fan_mode, ARRAY_SIZE(fan_mode)));
 
 	/*
 	 * Function Lock
@@ -175,15 +141,11 @@ static void merlin_init(struct device *dev)
 	 * Default:	Locked
 	 *
 	 */
-#ifdef CMOS_VLEN_fn_lock_state
 	const uint8_t fn_lock_state[] = {UNLOCKED, LOCKED};
 
 	ec_write(ECRAM_FN_LOCK_STATE,
 		 get_ec_value_from_option(
-			 "fn_lock_state", 1, fn_lock_state, ARRAY_SIZE(fn_lock_state),
-			 CONFIG(USE_OPTION_TABLE) ? CMOS_VSTART_fn_lock_state : UINT_MAX,
-			 CONFIG(USE_OPTION_TABLE) ? CMOS_VLEN_fn_lock_state : UINT_MAX));
-#endif
+			 "fn_lock_state", 1, fn_lock_state, ARRAY_SIZE(fn_lock_state)));
 
 	/*
 	 * Trackpad State
@@ -194,15 +156,11 @@ static void merlin_init(struct device *dev)
 	 * Default:	Enabled
 	 *
 	 */
-#ifdef CMOS_VSTART_trackpad_state
 	const uint8_t trackpad_state[] = {TRACKPAD_ENABLED, TRACKPAD_DISABLED};
 
 	ec_write(ECRAM_TRACKPAD_STATE,
 		 get_ec_value_from_option(
-			 "trackpad_state", 0, trackpad_state, ARRAY_SIZE(trackpad_state),
-			 CONFIG(USE_OPTION_TABLE) ? CMOS_VSTART_trackpad_state : UINT_MAX,
-			 CONFIG(USE_OPTION_TABLE) ? CMOS_VLEN_trackpad_state : UINT_MAX));
-#endif
+			 "trackpad_state", 0, trackpad_state, ARRAY_SIZE(trackpad_state)));
 
 	/*
 	 * Keyboard Backlight Brightness
@@ -213,20 +171,16 @@ static void merlin_init(struct device *dev)
 	 * Default:	Low
 	 *
 	 */
-#ifdef CMOS_VSTART_kbl_brightness
 	const uint8_t kbl_brightness[] = {KBL_ON, KBL_OFF, KBL_LOW, KBL_HIGH};
 
+	const uint8_t kbl_brightness_fallback =
+		CONFIG(EC_STARLABS_KBL_LEVELS) ? KBL_LOW : KBL_ON;
+
 	ec_write(ECRAM_KBL_BRIGHTNESS,
 		 get_ec_value_from_option(
 			 "kbl_brightness",
-			 CONFIG(USE_OPTION_TABLE) ?
-				 (CONFIG(EC_STARLABS_KBL_LEVELS) ? 2 : 0) :
-				 (CONFIG(EC_STARLABS_KBL_LEVELS) ? KBL_LOW : KBL_ON),
-			 kbl_brightness, ARRAY_SIZE(kbl_brightness),
-			 CONFIG(USE_OPTION_TABLE) ? CMOS_VSTART_kbl_brightness : UINT_MAX,
-			 CONFIG(USE_OPTION_TABLE) ? CMOS_VLEN_kbl_brightness : UINT_MAX));
-
-#endif
+			 kbl_brightness_fallback,
+			 kbl_brightness, ARRAY_SIZE(kbl_brightness)));
 
 	/*
 	 * Keyboard Backlight State
diff --git a/src/mainboard/starlabs/adl/Kconfig b/src/mainboard/starlabs/adl/Kconfig
index 50d56bfa98..b39f9c914d 100644
--- a/src/mainboard/starlabs/adl/Kconfig
+++ b/src/mainboard/starlabs/adl/Kconfig
@@ -9,7 +9,6 @@ config BOARD_STARLABS_ADL_SERIES
 	select EC_STARLABS_MERLIN
 	select HAVE_ACPI_RESUME
 	select HAVE_ACPI_TABLES
-	select HAVE_OPTION_TABLE
 	select INTEL_GMA_HAVE_VBT
 	select INTEL_LPSS_UART_FOR_CONSOLE
 	select NO_UART_ON_SUPERIO
@@ -27,7 +26,6 @@ config BOARD_STARLABS_ADL_HORIZON
 	select BOARD_STARLABS_ADL_SERIES
 	select DRIVERS_GFX_GENERIC
 	select DRIVERS_I2C_HID
-	select HAVE_CMOS_DEFAULT
 	select HAVE_HDA_DMIC
 	select HAVE_SPD_IN_CBFS
 	select MAINBOARD_HAS_TPM2
diff --git a/src/mainboard/starlabs/adl/cmos.default b/src/mainboard/starlabs/adl/cmos.default
deleted file mode 100644
index 49faae3e6a..0000000000
--- a/src/mainboard/starlabs/adl/cmos.default
+++ /dev/null
@@ -1,6 +0,0 @@
-## SPDX-License-Identifier: GPL-2.0-only
-# Functions
-fn_lock_state=0x1
-trackpad_state=0x1
-kbl_brightness=0x0
-kbl_state=0x1
diff --git a/src/mainboard/starlabs/adl/variants/hz/cmos.layout b/src/mainboard/starlabs/adl/variants/hz/cmos.layout
deleted file mode 100644
index ebba7fbd5d..0000000000
--- a/src/mainboard/starlabs/adl/variants/hz/cmos.layout
+++ /dev/null
@@ -1,46 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0-only
-
-# -----------------------------------------------------------------
-entries
-
-# Bank: 1
-# -----------------------------------------------------------------
-0	120	r	0	reserved_memory
-
-# -----------------------------------------------------------------
-# coreboot config options: ramtop
-304	80	h	0	ramtop
-
-# RTC_BOOT_BYTE (coreboot hardcoded)
-388	4	h	0	reboot_counter
-
-# coreboot config options: cpu
-#400	8	r	0	reserved for century byte
-
-# coreboot config options: check sums
-984	16	h	0	check_sum
-
-# Bank: 2
-# embedded controller settings (outside the checksummed area)
-1024	8	h	1	fn_lock_state
-1032	8	h	1	trackpad_state
-1040	8	h	2	kbl_brightness
-1048	8	h	1	kbl_state
-
-# -----------------------------------------------------------------
-
-enumerations
-
-#ID	value	text
-1	0	Disable
-1	1	Enable
-
-2	0	Off
-2	1	Low
-2	2	High
-2	3	On
-
-# -----------------------------------------------------------------
-checksums
-
-checksum 392 983 984
diff --git a/src/mainboard/starlabs/adl/variants/i5/cmos.layout b/src/mainboard/starlabs/adl/variants/i5/cmos.layout
deleted file mode 100644
index f78701f5d6..0000000000
--- a/src/mainboard/starlabs/adl/variants/i5/cmos.layout
+++ /dev/null
@@ -1,36 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0-only
-
-# -----------------------------------------------------------------
-entries
-
-# Bank: 1
-# -----------------------------------------------------------------
-0	120	r	0	reserved_memory
-
-# -----------------------------------------------------------------
-# coreboot config options: ramtop
-304	80	h	0	ramtop
-
-# RTC_BOOT_BYTE (coreboot hardcoded)
-388	4	h	0	reboot_counter
-
-# coreboot config options: cpu
-#400	8	r	0	reserved for century byte
-
-# coreboot config options: check sums
-984	16	h	0	check_sum
-
-# Bank: 2
-# embedded controller settings (outside the checksummed area)
-# -----------------------------------------------------------------
-
-enumerations
-
-#ID	value	text
-1	0	Disable
-1	1	Enable
-
-# -----------------------------------------------------------------
-checksums
-
-checksum 392 983 984
diff --git a/src/mainboard/starlabs/adl/variants/y2/cmos.layout b/src/mainboard/starlabs/adl/variants/y2/cmos.layout
deleted file mode 100644
index f78701f5d6..0000000000
--- a/src/mainboard/starlabs/adl/variants/y2/cmos.layout
+++ /dev/null
@@ -1,36 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0-only
-
-# -----------------------------------------------------------------
-entries
-
-# Bank: 1
-# -----------------------------------------------------------------
-0	120	r	0	reserved_memory
-
-# -----------------------------------------------------------------
-# coreboot config options: ramtop
-304	80	h	0	ramtop
-
-# RTC_BOOT_BYTE (coreboot hardcoded)
-388	4	h	0	reboot_counter
-
-# coreboot config options: cpu
-#400	8	r	0	reserved for century byte
-
-# coreboot config options: check sums
-984	16	h	0	check_sum
-
-# Bank: 2
-# embedded controller settings (outside the checksummed area)
-# -----------------------------------------------------------------
-
-enumerations
-
-#ID	value	text
-1	0	Disable
-1	1	Enable
-
-# -----------------------------------------------------------------
-checksums
-
-checksum 392 983 984
diff --git a/src/mainboard/starlabs/lite/Kconfig b/src/mainboard/starlabs/lite/Kconfig
index 1b03c054b2..a9fcd13ed7 100644
--- a/src/mainboard/starlabs/lite/Kconfig
+++ b/src/mainboard/starlabs/lite/Kconfig
@@ -9,8 +9,6 @@ config BOARD_STARLABS_LITE_SERIES
 	select DRIVERS_I2C_HID
 	select HAVE_ACPI_RESUME
 	select HAVE_ACPI_TABLES
-	select HAVE_CMOS_DEFAULT
-	select HAVE_OPTION_TABLE
 	select HAVE_INTEL_PTT
 	select INTEL_GMA_HAVE_VBT
 	select INTEL_LPSS_UART_FOR_CONSOLE
diff --git a/src/mainboard/starlabs/lite/cmos.default b/src/mainboard/starlabs/lite/cmos.default
deleted file mode 100644
index 49faae3e6a..0000000000
--- a/src/mainboard/starlabs/lite/cmos.default
+++ /dev/null
@@ -1,6 +0,0 @@
-## SPDX-License-Identifier: GPL-2.0-only
-# Functions
-fn_lock_state=0x1
-trackpad_state=0x1
-kbl_brightness=0x0
-kbl_state=0x1
diff --git a/src/mainboard/starlabs/lite/cmos.layout b/src/mainboard/starlabs/lite/cmos.layout
deleted file mode 100644
index 3057effc83..0000000000
--- a/src/mainboard/starlabs/lite/cmos.layout
+++ /dev/null
@@ -1,43 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0-only
-
-# -----------------------------------------------------------------
-entries
-
-# Bank: 1
-# -----------------------------------------------------------------
-0	120	r	0	reserved_memory
-
-# -----------------------------------------------------------------
-# RTC_BOOT_BYTE (coreboot hardcoded)
-388	4	h	0	reboot_counter
-
-# coreboot config options: cpu
-#400	8	r	0	reserved for century byte
-
-# coreboot config options: check sums
-984	16	h	0	check_sum
-
-# Bank: 2
-# embedded controller settings (outside the checksummed area)
-1024	8	h	1	fn_lock_state
-1032	8	h	1	trackpad_state
-1040	8	h	2	kbl_brightness
-1048	8	h	1	kbl_state
-
-# -----------------------------------------------------------------
-
-enumerations
-
-#ID	value	text
-1	0	Disable
-1	1	Enable
-
-2	0	Off
-2	1	Low
-2	2	High
-2	3	On
-
-# -----------------------------------------------------------------
-checksums
-
-checksum 392 983 984
diff --git a/src/mainboard/starlabs/starbook/Kconfig b/src/mainboard/starlabs/starbook/Kconfig
index cb9bccd3a4..7dee1e3ecf 100644
--- a/src/mainboard/starlabs/starbook/Kconfig
+++ b/src/mainboard/starlabs/starbook/Kconfig
@@ -10,9 +10,7 @@ config BOARD_STARLABS_STARBOOK_SERIES
 	select EC_STARLABS_FAN
 	select HAVE_ACPI_RESUME
 	select HAVE_ACPI_TABLES
-	select HAVE_CMOS_DEFAULT
 	select HAVE_HDA_DMIC
-	select HAVE_OPTION_TABLE
 	select INTEL_GMA_HAVE_VBT
 	select INTEL_LPSS_UART_FOR_CONSOLE
 	select NO_UART_ON_SUPERIO
diff --git a/src/mainboard/starlabs/starbook/cmos.default b/src/mainboard/starlabs/starbook/cmos.default
deleted file mode 100644
index 49faae3e6a..0000000000
--- a/src/mainboard/starlabs/starbook/cmos.default
+++ /dev/null
@@ -1,6 +0,0 @@
-## SPDX-License-Identifier: GPL-2.0-only
-# Functions
-fn_lock_state=0x1
-trackpad_state=0x1
-kbl_brightness=0x0
-kbl_state=0x1
diff --git a/src/mainboard/starlabs/starbook/cmos.layout b/src/mainboard/starlabs/starbook/cmos.layout
deleted file mode 100644
index ebba7fbd5d..0000000000
--- a/src/mainboard/starlabs/starbook/cmos.layout
+++ /dev/null
@@ -1,46 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0-only
-
-# -----------------------------------------------------------------
-entries
-
-# Bank: 1
-# -----------------------------------------------------------------
-0	120	r	0	reserved_memory
-
-# -----------------------------------------------------------------
-# coreboot config options: ramtop
-304	80	h	0	ramtop
-
-# RTC_BOOT_BYTE (coreboot hardcoded)
-388	4	h	0	reboot_counter
-
-# coreboot config options: cpu
-#400	8	r	0	reserved for century byte
-
-# coreboot config options: check sums
-984	16	h	0	check_sum
-
-# Bank: 2
-# embedded controller settings (outside the checksummed area)
-1024	8	h	1	fn_lock_state
-1032	8	h	1	trackpad_state
-1040	8	h	2	kbl_brightness
-1048	8	h	1	kbl_state
-
-# -----------------------------------------------------------------
-
-enumerations
-
-#ID	value	text
-1	0	Disable
-1	1	Enable
-
-2	0	Off
-2	1	Low
-2	2	High
-2	3	On
-
-# -----------------------------------------------------------------
-checksums
-
-checksum 392 983 984
diff --git a/src/mainboard/starlabs/starfighter/Kconfig b/src/mainboard/starlabs/starfighter/Kconfig
index f32a9a8153..07a810ec63 100644
--- a/src/mainboard/starlabs/starfighter/Kconfig
+++ b/src/mainboard/starlabs/starfighter/Kconfig
@@ -15,9 +15,7 @@ config BOARD_STARLABS_STARFIGHTER_SERIES
 	select EC_STARLABS_MERLIN
 	select HAVE_ACPI_RESUME
 	select HAVE_ACPI_TABLES
-	select HAVE_CMOS_DEFAULT
 	select HAVE_HDA_DMIC
-	select HAVE_OPTION_TABLE
 	select HAVE_SPD_IN_CBFS
 	select INTEL_GMA_HAVE_VBT
 	select INTEL_LPSS_UART_FOR_CONSOLE
diff --git a/src/mainboard/starlabs/starfighter/cmos.default b/src/mainboard/starlabs/starfighter/cmos.default
deleted file mode 100644
index 49faae3e6a..0000000000
--- a/src/mainboard/starlabs/starfighter/cmos.default
+++ /dev/null
@@ -1,6 +0,0 @@
-## SPDX-License-Identifier: GPL-2.0-only
-# Functions
-fn_lock_state=0x1
-trackpad_state=0x1
-kbl_brightness=0x0
-kbl_state=0x1
diff --git a/src/mainboard/starlabs/starfighter/cmos.layout b/src/mainboard/starlabs/starfighter/cmos.layout
deleted file mode 100644
index ebba7fbd5d..0000000000
--- a/src/mainboard/starlabs/starfighter/cmos.layout
+++ /dev/null
@@ -1,46 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0-only
-
-# -----------------------------------------------------------------
-entries
-
-# Bank: 1
-# -----------------------------------------------------------------
-0	120	r	0	reserved_memory
-
-# -----------------------------------------------------------------
-# coreboot config options: ramtop
-304	80	h	0	ramtop
-
-# RTC_BOOT_BYTE (coreboot hardcoded)
-388	4	h	0	reboot_counter
-
-# coreboot config options: cpu
-#400	8	r	0	reserved for century byte
-
-# coreboot config options: check sums
-984	16	h	0	check_sum
-
-# Bank: 2
-# embedded controller settings (outside the checksummed area)
-1024	8	h	1	fn_lock_state
-1032	8	h	1	trackpad_state
-1040	8	h	2	kbl_brightness
-1048	8	h	1	kbl_state
-
-# -----------------------------------------------------------------
-
-enumerations
-
-#ID	value	text
-1	0	Disable
-1	1	Enable
-
-2	0	Off
-2	1	Low
-2	2	High
-2	3	On
-
-# -----------------------------------------------------------------
-checksums
-
-checksum 392 983 984

From 0306eb07234858ce1d6be9b4a1ac58a7d44b582d Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Wed, 28 Jan 2026 12:10:00 +0000
Subject: [PATCH 3564/3886] mb/starlabs/common: add NVMe power sequencing
 helper

Add a shared helper (behind Kconfig) that owns the ramstage bootstate
ordering for the Star Labs NVMe/M.2 slot power sequence (PWREN, PERST#,
CLKREQ#).

Boards/variants provide pad configs for stage 2 and stage 3 either by
implementing the `variant_nvme_power_sequence_*()` helpers or by
providing pad tables via `variant_nvme_power_sequence_pads()` and
`variant_nvme_power_sequence_post_pads()`.

Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I3d518c35c26f3d3ee1dd72b4a35861d19cdb85ab
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90973
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/starlabs/common/Kconfig         | 21 +++++++
 src/mainboard/starlabs/common/Makefile.mk     |  2 +
 .../starlabs/common/include/common/nvme_seq.h | 15 +++++
 src/mainboard/starlabs/common/nvme_seq.c      | 62 +++++++++++++++++++
 4 files changed, 100 insertions(+)
 create mode 100644 src/mainboard/starlabs/common/include/common/nvme_seq.h
 create mode 100644 src/mainboard/starlabs/common/nvme_seq.c

diff --git a/src/mainboard/starlabs/common/Kconfig b/src/mainboard/starlabs/common/Kconfig
index 8a670142c0..5501d43efe 100644
--- a/src/mainboard/starlabs/common/Kconfig
+++ b/src/mainboard/starlabs/common/Kconfig
@@ -13,6 +13,27 @@ config BOOTMEDIA_SMM_BWP_RUNTIME_OPTION
 config DRIVERS_EFI_FW_INFO
 	def_bool y
 
+config STARLABS_NVME_POWER_SEQUENCE
+	bool "Enable NVMe/M.2 slot power sequence"
+	depends on SOC_INTEL_COMMON_BLOCK_GPIO
+	default n
+	help
+	  Enable Fatcat-style 3-stage NVMe/M.2 slot sequencing using PWREN, PERST#
+	  and CLKREQ# pads.
+
+	  The sequencing is:
+	    1) pre-mem: PERST# asserted; PWREN=0; CLKREQ# disabled
+	    2) BS_PRE_DEVICE exit: PERST# still asserted; PWREN=1; CLKREQ# native
+	    3) BS_DEV_INIT_CHIPS entry: PERST# deasserted
+
+	  Boards selecting this option must provide their own pad configs and
+	  implement stage 1 (pre-mem) in their early pad configuration.
+
+	  For stage 2 and stage 3, boards must either implement the
+	  `variant_nvme_power_sequence_*()` helpers or provide pad tables via
+	  `variant_nvme_power_sequence_pads()` and
+	  `variant_nvme_power_sequence_post_pads()`.
+
 config MB_COMMON_DIR
 	string
 	default "starlabs/common"
diff --git a/src/mainboard/starlabs/common/Makefile.mk b/src/mainboard/starlabs/common/Makefile.mk
index b12b7610d3..6887c47a7d 100644
--- a/src/mainboard/starlabs/common/Makefile.mk
+++ b/src/mainboard/starlabs/common/Makefile.mk
@@ -6,6 +6,8 @@ subdirs-$(CONFIG_VENDOR_STARLABS) += powercap
 subdirs-$(CONFIG_VENDOR_STARLABS) += pin_mux
 subdirs-$(CONFIG_VENDOR_STARLABS) += smbios
 
+ramstage-$(CONFIG_STARLABS_NVME_POWER_SEQUENCE) += nvme_seq.c
+
 CPPFLAGS_common += -I$(src)/mainboard/starlabs/common/include
 
 ramstage-$(CONFIG_STARLABS_ACPI_EFI_OPTION_SMI) += gnvs.c
diff --git a/src/mainboard/starlabs/common/include/common/nvme_seq.h b/src/mainboard/starlabs/common/include/common/nvme_seq.h
new file mode 100644
index 0000000000..fcd1838045
--- /dev/null
+++ b/src/mainboard/starlabs/common/include/common/nvme_seq.h
@@ -0,0 +1,15 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef _STARLABS_CMN_NVME_SEQ_H_
+#define _STARLABS_CMN_NVME_SEQ_H_
+
+#include <stddef.h>
+#include <soc/gpio.h>
+
+const struct pad_config *variant_nvme_power_sequence_pads(size_t *num);
+const struct pad_config *variant_nvme_power_sequence_post_pads(size_t *num);
+
+void variant_nvme_power_sequence_configure(void);
+void variant_nvme_power_sequence_post_gpio_configure(void);
+
+#endif /* _STARLABS_CMN_NVME_SEQ_H_ */
diff --git a/src/mainboard/starlabs/common/nvme_seq.c b/src/mainboard/starlabs/common/nvme_seq.c
new file mode 100644
index 0000000000..5fef80865a
--- /dev/null
+++ b/src/mainboard/starlabs/common/nvme_seq.c
@@ -0,0 +1,62 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <bootstate.h>
+#include <commonlib/bsd/compiler.h>
+#include <common/nvme_seq.h>
+#include <intelblocks/gpio.h>
+
+#if ENV_RAMSTAGE
+const __weak struct pad_config *variant_nvme_power_sequence_pads(size_t *num)
+{
+	*num = 0;
+	return NULL;
+}
+
+const __weak struct pad_config *variant_nvme_power_sequence_post_pads(size_t *num)
+{
+	*num = 0;
+	return NULL;
+}
+
+__weak void variant_nvme_power_sequence_configure(void)
+{
+	size_t num;
+	const struct pad_config *pads = variant_nvme_power_sequence_pads(&num);
+
+	if (pads && num)
+		gpio_configure_pads(pads, num);
+}
+
+__weak void variant_nvme_power_sequence_post_gpio_configure(void)
+{
+	size_t num;
+	const struct pad_config *pads = variant_nvme_power_sequence_post_pads(&num);
+
+	if (pads && num)
+		gpio_configure_pads(pads, num);
+}
+#endif
+
+/*
+ * Star Labs NVMe/M.2 slot power sequence glue.
+ *
+ * Boards/variants provide the actual pad configs (PWREN, PERST#, CLKREQ#).
+ *
+ * This file only owns the ramstage ordering so the staged overrides happen
+ * before PCIe enumeration/link training.
+ */
+
+static void starlabs_nvme_power_sequence_step2(void *unused)
+{
+	/* Stage 2: power on + enable CLKREQ#, keep PERST# asserted. */
+	variant_nvme_power_sequence_configure();
+}
+
+static void starlabs_nvme_power_sequence_step3(void *unused)
+{
+	/* Stage 3: deassert PERST# after GPIO configuration, before device init. */
+	variant_nvme_power_sequence_post_gpio_configure();
+}
+
+BOOT_STATE_INIT_ENTRY(BS_PRE_DEVICE, BS_ON_EXIT, starlabs_nvme_power_sequence_step2, NULL);
+BOOT_STATE_INIT_ENTRY(BS_DEV_INIT_CHIPS, BS_ON_ENTRY, starlabs_nvme_power_sequence_step3, NULL);

From 279406cd14d9764b54084f8deba8cadc81093589 Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Wed, 28 Jan 2026 11:16:01 +0000
Subject: [PATCH 3565/3886] mb/starlabs/starfighter: Add NVMe port power
 sequence

Implement Fatcat-style 3-stage M.2 NVMe slot sequencing
(PWREN, PERST#, CLKREQ#) for StarFighter and apply it to
all NVMe-capable ports (both Gen3 and Gen4).

This addresses intermittent NVMe detection problems on
cold/warm boot and improves PCIe link speed negotiation
by ensuring the device is held in reset with clocks gated
until slot power is enabled and coreboot is about to
initialize devices.

Sequence per NVMe port:
  1) pre-mem: disable CLKREQ#, assert PERST#, PWREN=0
  2) BS_PRE_DEVICE exit: PWREN=1, enable CLKREQ# native,
     keep PERST# asserted
  3) BS_DEV_INIT_CHIPS entry: deassert PERST#

Also update the variant gpio_table defaults so PWREN stays
off and CLKREQ# stays disconnected until the sequencing
code enables them.

Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: Ic34e9e755e167e301348fbe7c75649401300f53b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90974
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/starlabs/starfighter/Kconfig    |  1 +
 .../starlabs/starfighter/mainboard.c          |  9 +--
 .../starlabs/starfighter/variants/mtl/gpio.c  | 65 +++++++++++++++---
 .../starlabs/starfighter/variants/rpl/gpio.c  | 67 ++++++++++++++++---
 4 files changed, 120 insertions(+), 22 deletions(-)

diff --git a/src/mainboard/starlabs/starfighter/Kconfig b/src/mainboard/starlabs/starfighter/Kconfig
index 07a810ec63..b7795cc6aa 100644
--- a/src/mainboard/starlabs/starfighter/Kconfig
+++ b/src/mainboard/starlabs/starfighter/Kconfig
@@ -32,6 +32,7 @@ config BOARD_STARLABS_STARFIGHTER_SERIES
 	select SYSTEM_TYPE_LAPTOP
 	select TPM_MEASURED_BOOT
 	select VALIDATE_INTEL_DESCRIPTOR
+	select STARLABS_NVME_POWER_SEQUENCE
 
 config BOARD_STARLABS_STARFIGHTER_RPL
 	select BOARD_STARLABS_STARFIGHTER_SERIES
diff --git a/src/mainboard/starlabs/starfighter/mainboard.c b/src/mainboard/starlabs/starfighter/mainboard.c
index cd46529c0f..e0b6ffae49 100644
--- a/src/mainboard/starlabs/starfighter/mainboard.c
+++ b/src/mainboard/starlabs/starfighter/mainboard.c
@@ -1,10 +1,11 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
+#include <bootstate.h>
 #include <device/device.h>
 #include <soc/ramstage.h>
 #include <variants.h>
 
-static void init_mainboard(void *chip_info)
+static void starlabs_configure_gpios(void *unused)
 {
 	const struct pad_config *pads;
 	size_t num;
@@ -13,6 +14,6 @@ static void init_mainboard(void *chip_info)
 	gpio_configure_pads(pads, num);
 }
 
-struct chip_operations mainboard_ops = {
-	.init = init_mainboard,
-};
+BOOT_STATE_INIT_ENTRY(BS_PRE_DEVICE, BS_ON_ENTRY, starlabs_configure_gpios, NULL);
+
+struct chip_operations mainboard_ops = {};
diff --git a/src/mainboard/starlabs/starfighter/variants/mtl/gpio.c b/src/mainboard/starlabs/starfighter/variants/mtl/gpio.c
index 63d8218f80..32e7a5f6bc 100644
--- a/src/mainboard/starlabs/starfighter/variants/mtl/gpio.c
+++ b/src/mainboard/starlabs/starfighter/variants/mtl/gpio.c
@@ -1,8 +1,42 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
 #include <variants.h>
+#include <common/nvme_seq.h>
+
+#if ENV_RAMSTAGE
+static const struct pad_config nvme_pads[] = {
+	PAD_CFG_GPO(GPP_H07, 1, DEEP),
+	PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_D20, NONE, PLTRST, NF1),
+	PAD_CFG_GPO(GPP_A20, 0, PLTRST),
+	PAD_CFG_GPO(GPP_D22, 1, DEEP),
+	PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_C10, NONE, PLTRST, NF1),
+	PAD_CFG_GPO(GPP_H00, 0, PLTRST),
+	PAD_CFG_GPO(GPP_B19, 1, DEEP),
+	PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_D21, NONE, PLTRST, NF2),
+	PAD_CFG_GPO(GPP_H02, 0, PLTRST),
+};
+
+static const struct pad_config post_nvme_pads[] = {
+	PAD_CFG_GPO(GPP_A20, 1, PLTRST),
+	PAD_CFG_GPO(GPP_H00, 1, PLTRST),
+	PAD_CFG_GPO(GPP_H02, 1, PLTRST),
+};
+
+const struct pad_config *variant_nvme_power_sequence_pads(size_t *num)
+{
+	*num = ARRAY_SIZE(nvme_pads);
+	return nvme_pads;
+}
+
+const struct pad_config *variant_nvme_power_sequence_post_pads(size_t *num)
+{
+	*num = ARRAY_SIZE(post_nvme_pads);
+	return post_nvme_pads;
+}
+#endif
 
 /* Early pad configuration in bootblock */
+/* clang-format off */
 const struct pad_config early_gpio_table[] = {
 	/* Debug Connector */
 	PAD_CFG_NF(GPP_H08, NONE, DEEP, NF1),				/* RXD */
@@ -17,7 +51,18 @@ const struct pad_config early_gpio_table[] = {
 	PAD_CFG_GPI_LOCK(GPP_B06, NONE, LOCK_CONFIG),
 	PAD_CFG_GPI_LOCK(GPP_B07, NONE, LOCK_CONFIG),
 	PAD_CFG_GPI_LOCK(GPP_B08, NONE, LOCK_CONFIG),
+
+	PAD_CFG_GPI(GPP_D20, NONE, PLTRST),					/* Clock Request 8 */
+	PAD_CFG_GPO(GPP_A20, 0, PLTRST),					/* Reset (PERST# asserted) */
+	PAD_CFG_GPO(GPP_H07, 0, DEEP),						/* Enable (PWREN off) */
+	PAD_CFG_GPI(GPP_C10, NONE, PLTRST),					/* Clock Request 1 */
+	PAD_CFG_GPO(GPP_H00, 0, PLTRST),					/* Reset (PERST# asserted) */
+	PAD_CFG_GPO(GPP_D22, 0, DEEP),						/* Enable (PWREN off) */
+	PAD_CFG_GPI(GPP_D21, NONE, PLTRST),					/* Clock Request 5 */
+	PAD_CFG_GPO(GPP_H02, 0, PLTRST),					/* Reset asserted */
+	PAD_CFG_GPO(GPP_B19, 0, DEEP),						/* WiFi disabled */
 };
+/* clang-format on */
 
 const struct pad_config *variant_early_gpio_table(size_t *num)
 {
@@ -26,6 +71,7 @@ const struct pad_config *variant_early_gpio_table(size_t *num)
 }
 
 /* Pad configuration in ramstage. */
+/* clang-format off */
 const struct pad_config gpio_table[] = {
 	/* General Purpose I/O Deep */
 	PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_V00, NONE, DEEP, NF1),		/* Battery Low */
@@ -50,19 +96,19 @@ const struct pad_config gpio_table[] = {
 	PAD_CFG_GPI_APIC(GPP_B00, NONE, DEEP, LEVEL, INVERT),		/* Interrupt */
 
 	/* SSD (CPU)*/
-	PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_D20, NONE, PLTRST, NF1),	/* Clock Request 8 */
-	PAD_CFG_GPO(GPP_A20, 1, PLTRST),				/* Reset */
-	PAD_CFG_GPO(GPP_H07, 1, DEEP),					/* Enable */
+	PAD_NC(GPP_D20, NONE),						/* Clock Request 8 */
+	PAD_CFG_GPO(GPP_A20, 0, PLTRST),				/* Reset (PERST# asserted) */
+	PAD_CFG_GPO(GPP_H07, 0, DEEP),					/* Enable (PWREN off) */
 
 	/* SSD (PCH) */
-	PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_C10, NONE, PLTRST, NF1),	/* Clock Request 1 */
-	PAD_CFG_GPO(GPP_H00, 1, PLTRST),				/* Reset */
-	PAD_CFG_GPO(GPP_D22, 1, DEEP),					/* Enable */
+	PAD_NC(GPP_C10, NONE),						/* Clock Request 1 */
+	PAD_CFG_GPO(GPP_H00, 0, PLTRST),				/* Reset (PERST# asserted) */
+	PAD_CFG_GPO(GPP_D22, 0, DEEP),					/* Enable (PWREN off) */
 
 	/* Wireless */
-	PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_D21, NONE, PLTRST, NF2),	/* Clock Request 5 */
-	PAD_CFG_GPO(GPP_H02, 1, PLTRST),				/* Reset */
-	PAD_CFG_GPO(GPP_B19, 1, DEEP),					/* WiFi RF Kill */
+	PAD_NC(GPP_D21, NONE),						/* Clock Request 5 */
+	PAD_CFG_GPO(GPP_H02, 0, PLTRST),				/* Reset asserted */
+	PAD_CFG_GPO(GPP_B19, 0, DEEP),					/* WiFi disabled */
 	PAD_CFG_GPO(GPP_B18, 1, DEEP),					/* Bluetooth RF Kill */
 
 	/* Display */
@@ -252,6 +298,7 @@ const struct pad_config gpio_table[] = {
 	PAD_NC(GPP_D19, NONE),
 	PAD_NC(GPP_D23, NONE),
 };
+/* clang-format on */
 
 const struct pad_config *variant_gpio_table(size_t *num)
 {
diff --git a/src/mainboard/starlabs/starfighter/variants/rpl/gpio.c b/src/mainboard/starlabs/starfighter/variants/rpl/gpio.c
index d58121e83a..d1b7f60df6 100644
--- a/src/mainboard/starlabs/starfighter/variants/rpl/gpio.c
+++ b/src/mainboard/starlabs/starfighter/variants/rpl/gpio.c
@@ -1,8 +1,44 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
 #include <variants.h>
+#include <common/nvme_seq.h>
+
+#if ENV_RAMSTAGE
+/* clang-format off */
+static const struct pad_config nvme_pads[] = {
+	PAD_CFG_GPO(GPP_D14, 1, DEEP),
+	PAD_CFG_NF(GPP_D6, NONE, DEEP, NF1),
+	PAD_CFG_GPO(GPP_F20, 0, PLTRST),
+	PAD_CFG_GPO(GPP_D16, 1, PLTRST),
+	PAD_CFG_NF(GPP_H19, NONE, DEEP, NF1),
+	PAD_CFG_GPO(GPP_H0, 0, PLTRST),
+	PAD_CFG_GPO(GPP_E3, 1, DEEP),
+	PAD_CFG_NF(GPP_D7, NONE, DEEP, NF1),
+	PAD_CFG_GPO(GPP_H2, 0, PLTRST),
+};
+
+static const struct pad_config post_nvme_pads[] = {
+	PAD_CFG_GPO(GPP_F20, 1, PLTRST),
+	PAD_CFG_GPO(GPP_H0, 1, PLTRST),
+	PAD_CFG_GPO(GPP_H2, 1, PLTRST),
+};
+/* clang-format on */
+
+const struct pad_config *variant_nvme_power_sequence_pads(size_t *num)
+{
+	*num = ARRAY_SIZE(nvme_pads);
+	return nvme_pads;
+}
+
+const struct pad_config *variant_nvme_power_sequence_post_pads(size_t *num)
+{
+	*num = ARRAY_SIZE(post_nvme_pads);
+	return post_nvme_pads;
+}
+#endif
 
 /* Early pad configuration in bootblock */
+/* clang-format off */
 const struct pad_config early_gpio_table[] = {
 	/* Debug Connector */
 	PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2),				/* RXD */
@@ -13,7 +49,18 @@ const struct pad_config early_gpio_table[] = {
 	PAD_CFG_GPI_LOCK(GPP_F13, NONE, LOCK_CONFIG),
 	PAD_CFG_GPI_LOCK(GPP_F14, NONE, LOCK_CONFIG),
 	PAD_CFG_GPI_LOCK(GPP_F15, NONE, LOCK_CONFIG),
+
+	PAD_CFG_GPI(GPP_D6, NONE, DEEP),					/* Clock Request 5 */
+	PAD_CFG_GPO(GPP_F20, 0, PLTRST),					/* Reset (PERST# asserted) */
+	PAD_CFG_GPO(GPP_D14, 0, DEEP),						/* Enable (PWREN off) */
+	PAD_CFG_GPI(GPP_H19, NONE, DEEP),					/* Clock Request 2 */
+	PAD_CFG_GPO(GPP_H0, 0, PLTRST),						/* Reset (PERST# asserted) */
+	PAD_CFG_GPO(GPP_D16, 0, PLTRST),					/* Enable (PWREN off) */
+	PAD_CFG_GPI(GPP_D7, NONE, DEEP),					/* Clock Request 1 */
+	PAD_CFG_GPO(GPP_H2, 0, PLTRST),						/* Reset asserted */
+	PAD_CFG_GPO(GPP_E3, 0, DEEP),						/* WiFi disabled */
 };
+/* clang-format on */
 
 const struct pad_config *variant_early_gpio_table(size_t *num)
 {
@@ -22,6 +69,7 @@ const struct pad_config *variant_early_gpio_table(size_t *num)
 }
 
 /* Pad configuration in ramstage. */
+/* clang-format off */
 const struct pad_config gpio_table[] = {
 	/* General Purpose I/O Deep */
 	PAD_CFG_NF(GPD0, NONE, DEEP, NF1),				/* Battery Low */
@@ -46,19 +94,19 @@ const struct pad_config gpio_table[] = {
 	PAD_CFG_GPI_APIC_LOW(GPP_D11, NONE, PLTRST),			/* Interrupt */
 
 	/* SSD */
-	PAD_CFG_NF(GPP_D6, NONE, DEEP, NF1),				/* Clock Request 5 */
-	PAD_CFG_GPO(GPP_F20, 1, PLTRST),				/* Reset */
-	PAD_CFG_GPO(GPP_D14, 1, DEEP),					/* Enable */
+	PAD_NC(GPP_D6, NONE),						/* Clock Request 5 */
+	PAD_CFG_GPO(GPP_F20, 0, PLTRST),				/* Reset (PERST# asserted) */
+	PAD_CFG_GPO(GPP_D14, 0, DEEP),					/* Enable (PWREN off) */
 
 	/* SSD 2 */
-	PAD_CFG_NF(GPP_H19, NONE, DEEP, NF1),				/* Clock Request 2 */
-	PAD_CFG_GPO(GPP_H0, 1, PLTRST),					/* Reset */
-	PAD_CFG_GPO(GPP_D16, 1, PLTRST),				/* Enable */
+	PAD_NC(GPP_H19, NONE),						/* Clock Request 2 */
+	PAD_CFG_GPO(GPP_H0, 0, PLTRST),					/* Reset (PERST# asserted) */
+	PAD_CFG_GPO(GPP_D16, 0, PLTRST),				/* Enable (PWREN off) */
 
 	/* Wireless */
-	PAD_CFG_NF(GPP_D7, NONE, DEEP, NF1),				/* Clock Request 1 */
-	PAD_CFG_GPO(GPP_H2, 1, PLTRST),					/* Reset */
-	PAD_CFG_GPO(GPP_E3, 1, DEEP),					/* WiFi RF Kill */
+	PAD_NC(GPP_D7, NONE),						/* Clock Request 1 */
+	PAD_CFG_GPO(GPP_H2, 0, PLTRST),					/* Reset asserted */
+	PAD_CFG_GPO(GPP_E3, 0, DEEP),					/* WiFi disabled */
 	PAD_CFG_GPO(GPP_A13, 1, DEEP),					/* Bluetooth RF Kill */
 
 	/* Display */
@@ -265,6 +313,7 @@ const struct pad_config gpio_table[] = {
 	PAD_NC(GPP_R6, NONE),
 	PAD_NC(GPP_R7, NONE),
 };
+/* clang-format on */
 
 const struct pad_config *variant_gpio_table(size_t *num)
 {

From 49a5b949ca5c4e8933fa63356d48674c452b73bc Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Thu, 29 Jan 2026 12:06:46 +0000
Subject: [PATCH 3566/3886] mb/starlabs/starbook: Add NVMe/WiFi power
 sequencing

Provide staged GPIO pad configuration for the M.2 NVMe SSD and the
(discrete) M.2 2230 wireless module on supported StarBook variants.

Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I6b3b607e73a2b1c437349f31cc6faaf662365da7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90993
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
---
 src/mainboard/starlabs/starbook/Kconfig       |  1 +
 src/mainboard/starlabs/starbook/mainboard.c   |  9 +--
 .../starlabs/starbook/variants/adl/gpio.c     | 58 +++++++++++++++++--
 .../starlabs/starbook/variants/adl_n/gpio.c   | 58 +++++++++++++++++--
 .../starlabs/starbook/variants/mtl/gpio.c     | 58 +++++++++++++++++--
 .../starlabs/starbook/variants/rpl/gpio.c     | 58 +++++++++++++++++--
 .../starlabs/starbook/variants/tgl/gpio.c     | 42 +++++++++++++-
 7 files changed, 253 insertions(+), 31 deletions(-)

diff --git a/src/mainboard/starlabs/starbook/Kconfig b/src/mainboard/starlabs/starbook/Kconfig
index 7dee1e3ecf..bae92d0239 100644
--- a/src/mainboard/starlabs/starbook/Kconfig
+++ b/src/mainboard/starlabs/starbook/Kconfig
@@ -16,6 +16,7 @@ config BOARD_STARLABS_STARBOOK_SERIES
 	select NO_UART_ON_SUPERIO
 	select SPD_READ_BY_WORD
 	select SOC_INTEL_COMMON_BLOCK_HDA_VERB
+	select STARLABS_NVME_POWER_SEQUENCE
 	select SYSTEM_TYPE_LAPTOP
 	select VALIDATE_INTEL_DESCRIPTOR
 
diff --git a/src/mainboard/starlabs/starbook/mainboard.c b/src/mainboard/starlabs/starbook/mainboard.c
index f392ed8759..8916dda296 100644
--- a/src/mainboard/starlabs/starbook/mainboard.c
+++ b/src/mainboard/starlabs/starbook/mainboard.c
@@ -1,12 +1,13 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
+#include <bootstate.h>
 #include <device/device.h>
 #include <drivers/intel/gma/opregion.h>
 #include <soc/ramstage.h>
 #include <option.h>
 #include <variants.h>
 
-static void init_mainboard(void *chip_info)
+static void starlabs_configure_gpios(void *unused)
 {
 	const struct pad_config *pads;
 	size_t num;
@@ -15,9 +16,9 @@ static void init_mainboard(void *chip_info)
 	gpio_configure_pads(pads, num);
 }
 
-struct chip_operations mainboard_ops = {
-	.init = init_mainboard,
-};
+BOOT_STATE_INIT_ENTRY(BS_PRE_DEVICE, BS_ON_ENTRY, starlabs_configure_gpios, NULL);
+
+struct chip_operations mainboard_ops = {};
 
 const char *mainboard_vbt_filename(void)
 {
diff --git a/src/mainboard/starlabs/starbook/variants/adl/gpio.c b/src/mainboard/starlabs/starbook/variants/adl/gpio.c
index f2d33b6458..2bad34dc52 100644
--- a/src/mainboard/starlabs/starbook/variants/adl/gpio.c
+++ b/src/mainboard/starlabs/starbook/variants/adl/gpio.c
@@ -1,13 +1,57 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
 #include <variants.h>
+#include <common/nvme_seq.h>
+
+#if ENV_RAMSTAGE
+/* clang-format off */
+static const struct pad_config nvme_pads[] = {
+	PAD_CFG_GPO(GPP_D16, 1, DEEP),					/* Enable */
+	PAD_CFG_NF(GPP_D6, NONE, DEEP, NF1),				/* Clock Request 1 */
+	PAD_CFG_GPO(GPP_H0, 0, PLTRST),					/* Reset asserted */
+
+	PAD_CFG_GPO(GPP_E3, 1, DEEP),					/* WiFi RF Kill */
+	PAD_CFG_NF(GPP_D7, NONE, DEEP, NF1),				/* Clock Request 2 */
+	PAD_CFG_GPO(GPP_H2, 0, PLTRST),					/* Reset asserted */
+};
+
+static const struct pad_config post_nvme_pads[] = {
+	PAD_CFG_GPO(GPP_H0, 1, PLTRST),					/* Reset deasserted */
+	PAD_CFG_GPO(GPP_H2, 1, PLTRST),					/* Reset deasserted */
+};
+/* clang-format on */
+
+const struct pad_config *variant_nvme_power_sequence_pads(size_t *num)
+{
+	*num = ARRAY_SIZE(nvme_pads);
+	return nvme_pads;
+}
+
+const struct pad_config *variant_nvme_power_sequence_post_pads(size_t *num)
+{
+	*num = ARRAY_SIZE(post_nvme_pads);
+	return post_nvme_pads;
+}
+#endif
 
 /* Early pad configuration in bootblock */
+/* clang-format off */
 const struct pad_config early_gpio_table[] = {
 	/* Debug Connector */
 	PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2),				/* RXD */
 	PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2),				/* TXD */
+
+	/* SSD */
+	PAD_CFG_GPI(GPP_D6, NONE, DEEP),					/* Clock Request 1 */
+	PAD_CFG_GPO(GPP_H0, 0, PLTRST),					/* Reset asserted */
+	PAD_CFG_GPO(GPP_D16, 0, DEEP),					/* Enable (PWREN off) */
+
+	/* Wireless */
+	PAD_CFG_GPI(GPP_D7, NONE, DEEP),					/* Clock Request 2 */
+	PAD_CFG_GPO(GPP_H2, 0, PLTRST),					/* Reset asserted */
+	PAD_CFG_GPO(GPP_E3, 0, DEEP),					/* WiFi disabled */
 };
+/* clang-format on */
 
 const struct pad_config *variant_early_gpio_table(size_t *num)
 {
@@ -16,6 +60,7 @@ const struct pad_config *variant_early_gpio_table(size_t *num)
 }
 
 /* Pad configuration in ramstage. */
+/* clang-format off */
 const struct pad_config gpio_table[] = {
 	/* General Purpose I/O Deep */
 	PAD_CFG_NF(GPD0, NONE, DEEP, NF1),				/* Battery Low */
@@ -40,16 +85,16 @@ const struct pad_config gpio_table[] = {
 	PAD_CFG_GPI_APIC_LOW(GPP_E12, NONE, PLTRST),			/* Interrupt */
 
 	/* SSD */
-	PAD_CFG_NF(GPP_D6, NONE, DEEP, NF1),				/* Clock Request 1 */
-	PAD_CFG_GPO(GPP_H0, 1, PLTRST),					/* Reset */
-	PAD_CFG_GPO(GPP_D16, 1, DEEP),					/* Enable */
+	PAD_NC(GPP_D6, NONE),						/* Clock Request 1 */
+	PAD_CFG_GPO(GPP_H0, 0, PLTRST),					/* Reset asserted */
+	PAD_CFG_GPO(GPP_D16, 0, DEEP),					/* Enable (PWREN off) */
 	PAD_CFG_NF(GPP_H13, NONE, DEEP, NF5),				/* Device Sleep */
 	PAD_CFG_NF(GPP_A12, NONE, DEEP, NF1),				/* PEDET */
 
 	/* Wireless */
-	PAD_CFG_NF(GPP_D7, NONE, DEEP, NF1),				/* Clock Request 2 */
-	PAD_CFG_GPO(GPP_H2, 1, PLTRST),					/* Reset */
-	PAD_CFG_GPO(GPP_E3, 1, DEEP),					/* WiFi RF Kill */
+	PAD_NC(GPP_D7, NONE),						/* Clock Request 2 */
+	PAD_CFG_GPO(GPP_H2, 0, PLTRST),					/* Reset asserted */
+	PAD_CFG_GPO(GPP_E3, 0, DEEP),					/* WiFi disabled */
 	PAD_CFG_GPO(GPP_A13, 1, DEEP),					/* Bluetooth RF Kill */
 
 	/* Display */
@@ -261,6 +306,7 @@ const struct pad_config gpio_table[] = {
 	PAD_NC(GPP_R6, NONE),
 	PAD_NC(GPP_R7, NONE),
 };
+/* clang-format on */
 
 const struct pad_config *variant_gpio_table(size_t *num)
 {
diff --git a/src/mainboard/starlabs/starbook/variants/adl_n/gpio.c b/src/mainboard/starlabs/starbook/variants/adl_n/gpio.c
index fc44208bac..3a8afd2b4d 100644
--- a/src/mainboard/starlabs/starbook/variants/adl_n/gpio.c
+++ b/src/mainboard/starlabs/starbook/variants/adl_n/gpio.c
@@ -1,13 +1,57 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
 #include <variants.h>
+#include <common/nvme_seq.h>
+
+#if ENV_RAMSTAGE
+/* clang-format off */
+static const struct pad_config nvme_pads[] = {
+	PAD_CFG_GPO(GPP_D16, 1, DEEP),					/* Enable */
+	PAD_CFG_NF(GPP_D5, NONE, DEEP, NF1),				/* Clock Request 0 */
+	PAD_CFG_GPO(GPP_H0, 0, PLTRST),					/* Reset asserted */
+
+	PAD_CFG_GPO(GPP_E3, 1, DEEP),					/* WiFi RF Kill */
+	PAD_CFG_NF(GPP_D6, NONE, DEEP, NF1),				/* Clock Request 1 */
+	PAD_CFG_GPO(GPP_H2, 0, PLTRST),					/* Reset asserted */
+};
+
+static const struct pad_config post_nvme_pads[] = {
+	PAD_CFG_GPO(GPP_H0, 1, PLTRST),					/* Reset deasserted */
+	PAD_CFG_GPO(GPP_H2, 1, PLTRST),					/* Reset deasserted */
+};
+/* clang-format on */
+
+const struct pad_config *variant_nvme_power_sequence_pads(size_t *num)
+{
+	*num = ARRAY_SIZE(nvme_pads);
+	return nvme_pads;
+}
+
+const struct pad_config *variant_nvme_power_sequence_post_pads(size_t *num)
+{
+	*num = ARRAY_SIZE(post_nvme_pads);
+	return post_nvme_pads;
+}
+#endif
 
 /* Early pad configuration in bootblock */
+/* clang-format off */
 const struct pad_config early_gpio_table[] = {
 	/* Debug Connector */
 	PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2),				/* RXD */
 	PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2),				/* TXD */
+
+	/* SSD */
+	PAD_CFG_GPI(GPP_D5, NONE, DEEP),					/* Clock Request 0 */
+	PAD_CFG_GPO(GPP_H0, 0, PLTRST),					/* Reset asserted */
+	PAD_CFG_GPO(GPP_D16, 0, DEEP),					/* Enable (PWREN off) */
+
+	/* Wireless */
+	PAD_CFG_GPI(GPP_D6, NONE, DEEP),					/* Clock Request 1 */
+	PAD_CFG_GPO(GPP_H2, 0, PLTRST),					/* Reset asserted */
+	PAD_CFG_GPO(GPP_E3, 0, DEEP),					/* WiFi disabled */
 };
+/* clang-format on */
 
 const struct pad_config *variant_early_gpio_table(size_t *num)
 {
@@ -16,6 +60,7 @@ const struct pad_config *variant_early_gpio_table(size_t *num)
 }
 
 /* Pad configuration in ramstage. */
+/* clang-format off */
 const struct pad_config gpio_table[] = {
 	/* General Purpose I/O Deep */
 	PAD_CFG_NF(GPD0, NONE, DEEP, NF1),				/* Battery Low */
@@ -40,14 +85,14 @@ const struct pad_config gpio_table[] = {
 	PAD_CFG_GPI_APIC_LOW(GPP_E12, NONE, PLTRST),			/* Interrupt */
 
 	/* SSD */
-	PAD_CFG_NF(GPP_D5, NONE, DEEP, NF1),				/* Clock Request 0 */
-	PAD_CFG_GPO(GPP_H0, 1, PLTRST),					/* Reset */
-	PAD_CFG_GPO(GPP_D16, 1, DEEP),					/* Enable */
+	PAD_NC(GPP_D5, NONE),						/* Clock Request 0 */
+	PAD_CFG_GPO(GPP_H0, 0, PLTRST),					/* Reset asserted */
+	PAD_CFG_GPO(GPP_D16, 0, DEEP),					/* Enable (PWREN off) */
 
 	/* Wireless */
-	PAD_CFG_NF(GPP_D6, NONE, DEEP, NF1),				/* Clock Request 1 */
-	PAD_CFG_GPO(GPP_H2, 1, PLTRST),					/* Reset */
-	PAD_CFG_GPO(GPP_E3, 1, DEEP),					/* WiFi RF Kill */
+	PAD_NC(GPP_D6, NONE),						/* Clock Request 1 */
+	PAD_CFG_GPO(GPP_H2, 0, PLTRST),					/* Reset asserted */
+	PAD_CFG_GPO(GPP_E3, 0, DEEP),					/* WiFi disabled */
 	PAD_CFG_GPO(GPP_A13, 1, DEEP),					/* Bluetooth RF Kill */
 
 	/* Display */
@@ -258,6 +303,7 @@ const struct pad_config gpio_table[] = {
 	PAD_NC(GPP_R6, NONE),
 	PAD_NC(GPP_R7, NONE),
 };
+/* clang-format on */
 
 const struct pad_config *variant_gpio_table(size_t *num)
 {
diff --git a/src/mainboard/starlabs/starbook/variants/mtl/gpio.c b/src/mainboard/starlabs/starbook/variants/mtl/gpio.c
index 944c1452f8..72c5d637a3 100644
--- a/src/mainboard/starlabs/starbook/variants/mtl/gpio.c
+++ b/src/mainboard/starlabs/starbook/variants/mtl/gpio.c
@@ -1,8 +1,41 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
 #include <variants.h>
+#include <common/nvme_seq.h>
+
+#if ENV_RAMSTAGE
+/* clang-format off */
+static const struct pad_config nvme_pads[] = {
+	PAD_CFG_GPO(GPP_H07, 1, DEEP),					/* Enable */
+	PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_D20, NONE, PLTRST, NF1),	/* Clock Request 8 */
+	PAD_CFG_GPO(GPP_A20, 0, PLTRST),				/* Reset asserted */
+
+	PAD_CFG_GPO(GPP_B19, 1, DEEP),					/* WiFi RF Kill */
+	PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_D21, NONE, PLTRST, NF2),	/* Clock Request 5 */
+	PAD_CFG_GPO(GPP_H02, 0, PLTRST),				/* Reset asserted */
+};
+
+static const struct pad_config post_nvme_pads[] = {
+	PAD_CFG_GPO(GPP_A20, 1, PLTRST),				/* Reset deasserted */
+	PAD_CFG_GPO(GPP_H02, 1, PLTRST),				/* Reset deasserted */
+};
+/* clang-format on */
+
+const struct pad_config *variant_nvme_power_sequence_pads(size_t *num)
+{
+	*num = ARRAY_SIZE(nvme_pads);
+	return nvme_pads;
+}
+
+const struct pad_config *variant_nvme_power_sequence_post_pads(size_t *num)
+{
+	*num = ARRAY_SIZE(post_nvme_pads);
+	return post_nvme_pads;
+}
+#endif
 
 /* Early pad configuration in bootblock */
+/* clang-format off */
 const struct pad_config early_gpio_table[] = {
 	/* Debug Connector */
 	PAD_CFG_NF(GPP_H08, NONE, DEEP, NF1),				/* RXD */
@@ -11,7 +44,18 @@ const struct pad_config early_gpio_table[] = {
 	/* SMBus */
 	PAD_CFG_NF(GPP_C00, NONE, DEEP, NF1),				/* Clock */
 	PAD_CFG_NF(GPP_C01, NONE, DEEP, NF1),				/* Data */
+
+	/* SSD */
+	PAD_CFG_GPI(GPP_D20, NONE, PLTRST),					/* Clock Request 8 */
+	PAD_CFG_GPO(GPP_A20, 0, PLTRST),				/* Reset asserted */
+	PAD_CFG_GPO(GPP_H07, 0, DEEP),					/* Enable (PWREN off) */
+
+	/* Wireless */
+	PAD_CFG_GPI(GPP_D21, NONE, PLTRST),					/* Clock Request 5 */
+	PAD_CFG_GPO(GPP_H02, 0, PLTRST),				/* Reset asserted */
+	PAD_CFG_GPO(GPP_B19, 0, DEEP),					/* WiFi disabled */
 };
+/* clang-format on */
 
 const struct pad_config *variant_early_gpio_table(size_t *num)
 {
@@ -20,6 +64,7 @@ const struct pad_config *variant_early_gpio_table(size_t *num)
 }
 
 /* Pad configuration in ramstage. */
+/* clang-format off */
 const struct pad_config gpio_table[] = {
 	/* General Purpose I/O Deep */
 	PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_V00, NONE, DEEP, NF1),		/* Battery Low */
@@ -44,14 +89,14 @@ const struct pad_config gpio_table[] = {
 	PAD_CFG_GPI_APIC(GPP_B00, NONE, DEEP, LEVEL, INVERT),		/* Interrupt */
 
 	/* SSD */
-	PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_D20, NONE, PLTRST, NF1),	/* Clock Request 8 */
-	PAD_CFG_GPO(GPP_A20, 1, PLTRST),				/* Reset */
-	PAD_CFG_GPO(GPP_H07, 1, DEEP),					/* Enable */
+	PAD_NC(GPP_D20, NONE),						/* Clock Request 8 */
+	PAD_CFG_GPO(GPP_A20, 0, PLTRST),				/* Reset asserted */
+	PAD_CFG_GPO(GPP_H07, 0, DEEP),					/* Enable (PWREN off) */
 
 	/* Wireless */
-	PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_D21, NONE, PLTRST, NF2),	/* Clock Request 5 */
-	PAD_CFG_GPO(GPP_H02, 1, PLTRST),				/* Reset */
-	PAD_CFG_GPO(GPP_B19, 1, DEEP),					/* WiFi RF Kill */
+	PAD_NC(GPP_D21, NONE),						/* Clock Request 5 */
+	PAD_CFG_GPO(GPP_H02, 0, PLTRST),				/* Reset asserted */
+	PAD_CFG_GPO(GPP_B19, 0, DEEP),					/* WiFi disabled */
 	PAD_CFG_GPO(GPP_B18, 1, DEEP),					/* Bluetooth RF Kill */
 
 	/* Display */
@@ -246,6 +291,7 @@ const struct pad_config gpio_table[] = {
 	PAD_NC(GPP_D22, NONE),
 	PAD_NC(GPP_D23, NONE),
 };
+/* clang-format on */
 
 const struct pad_config *variant_gpio_table(size_t *num)
 {
diff --git a/src/mainboard/starlabs/starbook/variants/rpl/gpio.c b/src/mainboard/starlabs/starbook/variants/rpl/gpio.c
index 0625675f10..339e771544 100644
--- a/src/mainboard/starlabs/starbook/variants/rpl/gpio.c
+++ b/src/mainboard/starlabs/starbook/variants/rpl/gpio.c
@@ -1,13 +1,57 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
 #include <variants.h>
+#include <common/nvme_seq.h>
+
+#if ENV_RAMSTAGE
+/* clang-format off */
+static const struct pad_config nvme_pads[] = {
+	PAD_CFG_GPO(GPP_D14, 1, DEEP),					/* Enable */
+	PAD_CFG_NF(GPP_H19, NONE, DEEP, NF1),				/* Clock Request 4 */
+	PAD_CFG_GPO(GPP_F20, 0, PLTRST),				/* Reset asserted */
+
+	PAD_CFG_GPO(GPP_E3, 1, DEEP),					/* WiFi RF Kill */
+	PAD_CFG_NF(GPP_D7, NONE, DEEP, NF1),				/* Clock Request 2 */
+	PAD_CFG_GPO(GPP_H2, 0, PLTRST),					/* Reset asserted */
+};
+
+static const struct pad_config post_nvme_pads[] = {
+	PAD_CFG_GPO(GPP_F20, 1, PLTRST),				/* Reset deasserted */
+	PAD_CFG_GPO(GPP_H2, 1, PLTRST),					/* Reset deasserted */
+};
+/* clang-format on */
+
+const struct pad_config *variant_nvme_power_sequence_pads(size_t *num)
+{
+	*num = ARRAY_SIZE(nvme_pads);
+	return nvme_pads;
+}
+
+const struct pad_config *variant_nvme_power_sequence_post_pads(size_t *num)
+{
+	*num = ARRAY_SIZE(post_nvme_pads);
+	return post_nvme_pads;
+}
+#endif
 
 /* Early pad configuration in bootblock */
+/* clang-format off */
 const struct pad_config early_gpio_table[] = {
 	/* Debug Connector */
 	PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2),				/* RXD */
 	PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2),				/* TXD */
+
+	/* SSD */
+	PAD_CFG_GPI(GPP_H19, NONE, DEEP),					/* Clock Request 4 */
+	PAD_CFG_GPO(GPP_F20, 0, PLTRST),				/* Reset asserted */
+	PAD_CFG_GPO(GPP_D14, 0, DEEP),					/* Enable (PWREN off) */
+
+	/* Wireless */
+	PAD_CFG_GPI(GPP_D7, NONE, DEEP),					/* Clock Request 2 */
+	PAD_CFG_GPO(GPP_H2, 0, PLTRST),					/* Reset asserted */
+	PAD_CFG_GPO(GPP_E3, 0, DEEP),					/* WiFi disabled */
 };
+/* clang-format on */
 
 const struct pad_config *variant_early_gpio_table(size_t *num)
 {
@@ -16,6 +60,7 @@ const struct pad_config *variant_early_gpio_table(size_t *num)
 }
 
 /* Pad configuration in ramstage. */
+/* clang-format off */
 const struct pad_config gpio_table[] = {
 	/* General Purpose I/O Deep */
 	PAD_CFG_NF(GPD0, NONE, DEEP, NF1),				/* Battery Low */
@@ -40,14 +85,14 @@ const struct pad_config gpio_table[] = {
 	PAD_CFG_GPI_APIC_LOW(GPP_E12, NONE, PLTRST),			/* Interrupt */
 
 	/* SSD */
-	PAD_CFG_NF(GPP_H19, NONE, DEEP, NF1),				/* Clock Request 4 */
-	PAD_CFG_GPO(GPP_F20, 1, PLTRST),				/* Reset */
-	PAD_CFG_GPO(GPP_D14, 1, DEEP),					/* Enable */
+	PAD_NC(GPP_H19, NONE),						/* Clock Request 4 */
+	PAD_CFG_GPO(GPP_F20, 0, PLTRST),				/* Reset asserted */
+	PAD_CFG_GPO(GPP_D14, 0, DEEP),					/* Enable (PWREN off) */
 
 	/* Wireless */
-	PAD_CFG_NF(GPP_D7, NONE, DEEP, NF1),				/* Clock Request 2 */
-	PAD_CFG_GPO(GPP_H2, 1, PLTRST),					/* Reset */
-	PAD_CFG_GPO(GPP_E3, 1, DEEP),					/* WiFi RF Kill */
+	PAD_NC(GPP_D7, NONE),						/* Clock Request 2 */
+	PAD_CFG_GPO(GPP_H2, 0, PLTRST),					/* Reset asserted */
+	PAD_CFG_GPO(GPP_E3, 0, DEEP),					/* WiFi disabled */
 	PAD_CFG_GPO(GPP_A13, 1, DEEP),					/* Bluetooth RF Kill */
 
 	/* Display */
@@ -260,6 +305,7 @@ const struct pad_config gpio_table[] = {
 	PAD_NC(GPP_R6, NONE),
 	PAD_NC(GPP_R7, NONE),
 };
+/* clang-format on */
 
 const struct pad_config *variant_gpio_table(size_t *num)
 {
diff --git a/src/mainboard/starlabs/starbook/variants/tgl/gpio.c b/src/mainboard/starlabs/starbook/variants/tgl/gpio.c
index 0bf5afba78..58fc4b4664 100644
--- a/src/mainboard/starlabs/starbook/variants/tgl/gpio.c
+++ b/src/mainboard/starlabs/starbook/variants/tgl/gpio.c
@@ -1,13 +1,47 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
 #include <variants.h>
+#include <common/nvme_seq.h>
+
+#if ENV_RAMSTAGE
+/* clang-format off */
+static const struct pad_config nvme_pads[] = {
+	PAD_CFG_GPO(GPP_D16, 1, PLTRST),				/* Enable */
+	PAD_CFG_NF(GPP_D8, NONE, DEEP, NF1),				/* Clock Request 3 */
+	PAD_CFG_GPO(GPP_A11, 0, PLTRST),				/* Reset asserted */
+};
+
+static const struct pad_config post_nvme_pads[] = {
+	PAD_CFG_GPO(GPP_A11, 1, PLTRST),				/* Reset deasserted */
+};
+/* clang-format on */
+
+const struct pad_config *variant_nvme_power_sequence_pads(size_t *num)
+{
+	*num = ARRAY_SIZE(nvme_pads);
+	return nvme_pads;
+}
+
+const struct pad_config *variant_nvme_power_sequence_post_pads(size_t *num)
+{
+	*num = ARRAY_SIZE(post_nvme_pads);
+	return post_nvme_pads;
+}
+#endif
 
 /* Early pad configuration in bootblock */
+/* clang-format off */
 const struct pad_config early_gpio_table[] = {
 	/* Debug Connector */
 	PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1),				/* RXD */
 	PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1),				/* TXD */
+
+	/* SSD */
+	PAD_CFG_GPI(GPP_D8, NONE, DEEP),					/* Clock Request 3 */
+	PAD_CFG_GPO(GPP_A11, 0, PLTRST),				/* Reset asserted */
+	PAD_CFG_GPO(GPP_D16, 0, PLTRST),				/* Enable (PWREN off) */
 };
+/* clang-format on */
 
 const struct pad_config *variant_early_gpio_table(size_t *num)
 {
@@ -16,6 +50,7 @@ const struct pad_config *variant_early_gpio_table(size_t *num)
 }
 
 /* Pad configuration in ramstage. */
+/* clang-format off */
 const struct pad_config gpio_table[] = {
 	/* General Purpose I/O Deep */
 	PAD_CFG_NF(GPD0, NONE, DEEP, NF1),				/* Battery Low */
@@ -40,9 +75,9 @@ const struct pad_config gpio_table[] = {
 	PAD_CFG_GPI_APIC(GPP_C8, NONE, DEEP, LEVEL, INVERT),		/* Interrupt */
 
 	/* SSD */
-	PAD_CFG_NF(GPP_D8, NONE, DEEP, NF1),				/* Clock Request 3 */
-	PAD_CFG_GPO(GPP_A11, 1, PLTRST),				/* Reset */
-	PAD_CFG_GPO(GPP_D16, 1, PLTRST),				/* Enable */
+	PAD_NC(GPP_D8, NONE),						/* Clock Request 3 */
+	PAD_CFG_GPO(GPP_A11, 0, PLTRST),				/* Reset asserted */
+	PAD_CFG_GPO(GPP_D16, 0, PLTRST),				/* Enable (PWREN off) */
 
 	/* SATA */
 	PAD_CFG_NF(GPP_A12, UP_20K, DEEP, NF1),				/* PEDET */
@@ -250,6 +285,7 @@ const struct pad_config gpio_table[] = {
 	PAD_NC(GPP_U4, NONE),
 	PAD_NC(GPP_U5, NONE),
 };
+/* clang-format on */
 
 const struct pad_config *variant_gpio_table(size_t *num)
 {

From baadfed9990a66326c2531fc45bd2a0213bce0de Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Thu, 29 Jan 2026 11:59:36 +0000
Subject: [PATCH 3567/3886] mb/starlabs/adl: Add NVMe power sequencing

Enable STARLABS_NVME_POWER_SEQUENCE and provide staged GPIO pad
configuration for the SSD slot (PWREN, PERST#, CLKREQ#).

Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I22f1f8786db38b2720c544748cef58eb7259f239
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90991
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/starlabs/adl/Kconfig            |  1 +
 src/mainboard/starlabs/adl/mainboard.c        |  6 ++--
 src/mainboard/starlabs/adl/variants/hz/gpio.c | 36 +++++++++++++++++--
 src/mainboard/starlabs/adl/variants/i5/gpio.c | 36 +++++++++++++++++--
 src/mainboard/starlabs/adl/variants/y2/gpio.c | 36 +++++++++++++++++--
 5 files changed, 104 insertions(+), 11 deletions(-)

diff --git a/src/mainboard/starlabs/adl/Kconfig b/src/mainboard/starlabs/adl/Kconfig
index b39f9c914d..479ec79165 100644
--- a/src/mainboard/starlabs/adl/Kconfig
+++ b/src/mainboard/starlabs/adl/Kconfig
@@ -19,6 +19,7 @@ config BOARD_STARLABS_ADL_SERIES
 	select SOC_INTEL_CRASHLOG
 	select SPD_READ_BY_WORD
 	select SPI_FLASH_WINBOND
+	select STARLABS_NVME_POWER_SEQUENCE
 	select TPM2
 	select VALIDATE_INTEL_DESCRIPTOR
 
diff --git a/src/mainboard/starlabs/adl/mainboard.c b/src/mainboard/starlabs/adl/mainboard.c
index f8c9aea3ae..940584b151 100644
--- a/src/mainboard/starlabs/adl/mainboard.c
+++ b/src/mainboard/starlabs/adl/mainboard.c
@@ -1,11 +1,12 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
+#include <bootstate.h>
 #include <device/device.h>
 #include <drivers/intel/gma/opregion.h>
 #include <soc/ramstage.h>
 #include <variants.h>
 
-static void init_mainboard(void *chip_info)
+static void starlabs_configure_mainboard(void *unused)
 {
 	const struct pad_config *pads;
 	size_t num;
@@ -16,6 +17,8 @@ static void init_mainboard(void *chip_info)
 	devtree_update();
 }
 
+BOOT_STATE_INIT_ENTRY(BS_PRE_DEVICE, BS_ON_ENTRY, starlabs_configure_mainboard, NULL);
+
 void __weak starlabs_adl_mainboard_fill_ssdt(const struct device *dev)
 {
 	(void)dev;
@@ -27,6 +30,5 @@ static void enable_mainboard(struct device *dev)
 }
 
 struct chip_operations mainboard_ops = {
-	.init = init_mainboard,
 	.enable_dev = enable_mainboard,
 };
diff --git a/src/mainboard/starlabs/adl/variants/hz/gpio.c b/src/mainboard/starlabs/adl/variants/hz/gpio.c
index e214a14cec..4cb0af527d 100644
--- a/src/mainboard/starlabs/adl/variants/hz/gpio.c
+++ b/src/mainboard/starlabs/adl/variants/hz/gpio.c
@@ -1,12 +1,42 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
 #include <variants.h>
+#include <common/nvme_seq.h>
+
+#if ENV_RAMSTAGE
+static const struct pad_config nvme_pads[] = {
+	PAD_CFG_GPO(GPP_D16, 1, DEEP),				/* Enable */
+	PAD_CFG_NF(GPP_D5, NONE, DEEP, NF1),			/* Clock Request 0 */
+	PAD_CFG_GPO(GPP_H0, 0, PLTRST),				/* Reset asserted */
+};
+
+static const struct pad_config post_nvme_pads[] = {
+	PAD_CFG_GPO(GPP_H0, 1, PLTRST),				/* Reset deasserted */
+};
+
+const struct pad_config *variant_nvme_power_sequence_pads(size_t *num)
+{
+	*num = ARRAY_SIZE(nvme_pads);
+	return nvme_pads;
+}
+
+const struct pad_config *variant_nvme_power_sequence_post_pads(size_t *num)
+{
+	*num = ARRAY_SIZE(post_nvme_pads);
+	return post_nvme_pads;
+}
+#endif
 
 /* Early pad configuration in bootblock */
 const struct pad_config early_gpio_table[] = {
 	/* Debug Connector */
 	PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2),				/* RXD */
 	PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2),				/* TXD */
+
+	/* SSD */
+	PAD_CFG_GPI(GPP_D5, NONE, DEEP),					/* Clock Request 0 */
+	PAD_CFG_GPO(GPP_H0, 0, PLTRST),					/* Reset asserted */
+	PAD_CFG_GPO(GPP_D16, 0, DEEP),					/* Enable (PWREN off) */
 };
 
 const struct pad_config *variant_early_gpio_table(size_t *num)
@@ -40,9 +70,9 @@ const struct pad_config gpio_table[] = {
 	PAD_CFG_GPI_APIC_LOW(GPP_E12, NONE, PLTRST),			/* Interrupt */
 
 	/* SSD */
-	PAD_CFG_NF(GPP_D5, NONE, DEEP, NF1),				/* Clock Request 0 */
-	PAD_CFG_GPO(GPP_H0, 1, PLTRST),					/* Reset */
-	PAD_CFG_GPO(GPP_D16, 1, DEEP),					/* Enable */
+	PAD_NC(GPP_D5, NONE),						/* Clock Request 0 */
+	PAD_CFG_GPO(GPP_H0, 0, PLTRST),					/* Reset asserted */
+	PAD_CFG_GPO(GPP_D16, 0, DEEP),					/* Enable (PWREN off) */
 
 	/* Wireless */
 	PAD_CFG_NF(GPP_F0, NONE, DEEP, NF1),				/* BRI Data */
diff --git a/src/mainboard/starlabs/adl/variants/i5/gpio.c b/src/mainboard/starlabs/adl/variants/i5/gpio.c
index e6c03fd9c0..12b61daf05 100644
--- a/src/mainboard/starlabs/adl/variants/i5/gpio.c
+++ b/src/mainboard/starlabs/adl/variants/i5/gpio.c
@@ -1,12 +1,42 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
 #include <variants.h>
+#include <common/nvme_seq.h>
+
+#if ENV_RAMSTAGE
+static const struct pad_config nvme_pads[] = {
+	PAD_CFG_GPO(GPP_D16, 1, DEEP),       /* Enable */
+	PAD_CFG_NF(GPP_D5, NONE, DEEP, NF1), /* Clock Request 0 */
+	PAD_CFG_GPO(GPP_H0, 0, PLTRST),      /* Reset asserted */
+};
+
+static const struct pad_config post_nvme_pads[] = {
+	PAD_CFG_GPO(GPP_H0, 1, PLTRST), /* Reset deasserted */
+};
+
+const struct pad_config *variant_nvme_power_sequence_pads(size_t *num)
+{
+	*num = ARRAY_SIZE(nvme_pads);
+	return nvme_pads;
+}
+
+const struct pad_config *variant_nvme_power_sequence_post_pads(size_t *num)
+{
+	*num = ARRAY_SIZE(post_nvme_pads);
+	return post_nvme_pads;
+}
+#endif
 
 /* Early pad configuration in bootblock */
 const struct pad_config early_gpio_table[] = {
 	/* Debug Connector */
 	PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2), /* RXD */
 	PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2), /* TXD */
+
+	/* SSD */
+	PAD_CFG_GPI(GPP_D5, NONE, DEEP), /* Clock Request 0 */
+	PAD_CFG_GPO(GPP_H0, 0, PLTRST),  /* Reset asserted */
+	PAD_CFG_GPO(GPP_D16, 0, DEEP),   /* Enable (PWREN off) */
 };
 
 const struct pad_config *variant_early_gpio_table(size_t *num)
@@ -49,9 +79,9 @@ const struct pad_config gpio_table[] = {
 	PAD_CFG_GPI_SMI_LOW(GPP_F15, NONE, DEEP, EDGE_BOTH), /* Detect */
 
 	/* SSD */
-	PAD_CFG_NF(GPP_D5, NONE, DEEP, NF1), /* Clock Request 0 */
-	PAD_CFG_GPO(GPP_H0, 1, PLTRST),      /* Reset */
-	PAD_CFG_GPO(GPP_D16, 1, DEEP),       /* Enable */
+	PAD_NC(GPP_D5, NONE),                /* Clock Request 0 */
+	PAD_CFG_GPO(GPP_H0, 0, PLTRST),      /* Reset asserted */
+	PAD_CFG_GPO(GPP_D16, 0, DEEP),       /* Enable (PWREN off) */
 
 	/* Wireless */
 	PAD_CFG_NF(GPP_F0, NONE, DEEP, NF1),   /* BRI Data */
diff --git a/src/mainboard/starlabs/adl/variants/y2/gpio.c b/src/mainboard/starlabs/adl/variants/y2/gpio.c
index 12d9bcb472..849daadd57 100644
--- a/src/mainboard/starlabs/adl/variants/y2/gpio.c
+++ b/src/mainboard/starlabs/adl/variants/y2/gpio.c
@@ -1,12 +1,42 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
 #include <variants.h>
+#include <common/nvme_seq.h>
+
+#if ENV_RAMSTAGE
+static const struct pad_config nvme_pads[] = {
+	PAD_CFG_GPO(GPP_D16, 1, DEEP),				/* Enable */
+	PAD_CFG_NF(GPP_D5, NONE, DEEP, NF1),			/* Clock Request 0 */
+	PAD_CFG_GPO(GPP_H0, 0, PLTRST),				/* Reset asserted */
+};
+
+static const struct pad_config post_nvme_pads[] = {
+	PAD_CFG_GPO(GPP_H0, 1, PLTRST),				/* Reset deasserted */
+};
+
+const struct pad_config *variant_nvme_power_sequence_pads(size_t *num)
+{
+	*num = ARRAY_SIZE(nvme_pads);
+	return nvme_pads;
+}
+
+const struct pad_config *variant_nvme_power_sequence_post_pads(size_t *num)
+{
+	*num = ARRAY_SIZE(post_nvme_pads);
+	return post_nvme_pads;
+}
+#endif
 
 /* Early pad configuration in bootblock */
 const struct pad_config early_gpio_table[] = {
 	/* Debug Connector */
 	PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2),				/* RXD */
 	PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2),				/* TXD */
+
+	/* SSD */
+	PAD_CFG_GPI(GPP_D5, NONE, DEEP),					/* Clock Request 0 */
+	PAD_CFG_GPO(GPP_H0, 0, PLTRST),					/* Reset asserted */
+	PAD_CFG_GPO(GPP_D16, 0, DEEP),					/* Enable (PWREN off) */
 };
 
 const struct pad_config *variant_early_gpio_table(size_t *num)
@@ -36,9 +66,9 @@ const struct pad_config gpio_table[] = {
 	// PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_A10, NONE, DEEP, NF1),	/* eSPI Reset */
 
 	/* SSD */
-	PAD_CFG_NF(GPP_D5, NONE, DEEP, NF1),				/* Clock Request 0 */
-	PAD_CFG_GPO(GPP_H0, 1, PLTRST),					/* Reset */
-	PAD_CFG_GPO(GPP_D16, 1, DEEP),					/* Enable */
+	PAD_NC(GPP_D5, NONE),						/* Clock Request 0 */
+	PAD_CFG_GPO(GPP_H0, 0, PLTRST),					/* Reset asserted */
+	PAD_CFG_GPO(GPP_D16, 0, DEEP),					/* Enable (PWREN off) */
 	PAD_CFG_NF(GPP_H13, NONE, DEEP, NF5),				/* Device Sleep */
 	PAD_CFG_NF(GPP_A12, NONE, DEEP, NF1),				/* PEDET */
 

From 61c69ebfa899867a7d0e19b422b53d0a7b75d8e9 Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Thu, 29 Jan 2026 12:09:35 +0000
Subject: [PATCH 3568/3886] mb/starlabs: Drop PCIe detect-timeout/hotplug
 workarounds

With proper staged M.2 slot power sequencing in place, remove the
root-port detect-timeout overrides and the StarBook ADL PCI hot-plug
CFR option.

Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I50820c776011508f4d6bfa7053e827d7c53700b6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90994
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/starlabs/adl/variants/i5/devicetree.cb      | 1 -
 src/mainboard/starlabs/adl/variants/y2/devicetree.cb      | 1 -
 src/mainboard/starlabs/common/include/common/cfr.h        | 8 --------
 src/mainboard/starlabs/starbook/cfr.c                     | 3 ---
 .../starlabs/starbook/variants/adl/devicetree.cb          | 1 -
 src/mainboard/starlabs/starbook/variants/adl/ramstage.c   | 8 --------
 .../starlabs/starbook/variants/adl_n/devicetree.cb        | 1 -
 .../starlabs/starfighter/variants/mtl/devicetree.cb       | 1 -
 .../starlabs/starfighter/variants/rpl/devicetree.cb       | 1 -
 9 files changed, 25 deletions(-)

diff --git a/src/mainboard/starlabs/adl/variants/i5/devicetree.cb b/src/mainboard/starlabs/adl/variants/i5/devicetree.cb
index b0080bd292..155ed5c08e 100644
--- a/src/mainboard/starlabs/adl/variants/i5/devicetree.cb
+++ b/src/mainboard/starlabs/adl/variants/i5/devicetree.cb
@@ -199,7 +199,6 @@ chip soc/intel/alderlake
 				.flags					= PCIE_RP_LTR | PCIE_RP_AER,
 				.pcie_rp_aspm				= ASPM_L0S_L1,
 				.PcieRpL1Substates			= L1_SS_L1_2,
-				.pcie_rp_detect_timeout_ms		= 50,
 			}"
 
 			smbios_slot_desc				"SlotTypeM2Socket3"
diff --git a/src/mainboard/starlabs/adl/variants/y2/devicetree.cb b/src/mainboard/starlabs/adl/variants/y2/devicetree.cb
index 0ea50a4f36..c8d856cc03 100644
--- a/src/mainboard/starlabs/adl/variants/y2/devicetree.cb
+++ b/src/mainboard/starlabs/adl/variants/y2/devicetree.cb
@@ -189,7 +189,6 @@ chip soc/intel/alderlake
 				.flags					= PCIE_RP_LTR | PCIE_RP_AER,
 				.pcie_rp_aspm				= ASPM_L0S_L1,
 				.PcieRpL1Substates			= L1_SS_L1_2,
-				.pcie_rp_detect_timeout_ms		= 50,
 			}"
 			smbios_slot_desc				"SlotTypePciExpressGen3X4"
 									"SlotLengthLong"
diff --git a/src/mainboard/starlabs/common/include/common/cfr.h b/src/mainboard/starlabs/common/include/common/cfr.h
index 89405fd2b7..de4f108404 100644
--- a/src/mainboard/starlabs/common/include/common/cfr.h
+++ b/src/mainboard/starlabs/common/include/common/cfr.h
@@ -91,14 +91,6 @@ static const struct sm_object microphone = SM_DECLARE_BOOL({
 	.default_value	= true,
 });
 
-static const struct sm_object pci_hot_plug = SM_DECLARE_BOOL({
-	.opt_name	= "pci_hot_plug",
-	.ui_name	= "Third-Party SSD Support",
-	.ui_helptext	= "Enables PCI Hot Plug, which slows down the SSD initialization. It"
-			  " is required for certain third-party SSDs to be detected.",
-	.default_value	= false,
-});
-
 static const struct sm_object power_profile = SM_DECLARE_ENUM({
 	.opt_name	= "power_profile",
 	.ui_name	= "Power Profile",
diff --git a/src/mainboard/starlabs/starbook/cfr.c b/src/mainboard/starlabs/starbook/cfr.c
index 10263c45fa..d2e8b7c9ae 100644
--- a/src/mainboard/starlabs/starbook/cfr.c
+++ b/src/mainboard/starlabs/starbook/cfr.c
@@ -50,9 +50,6 @@ static struct sm_obj_form io_expansion_group = {
 	.ui_name = "I/O / Expansion",
 	.obj_list = (const struct sm_object *[]) {
 		&card_reader,
-		#if CONFIG(BOARD_STARLABS_STARBOOK_ADL)
-		&pci_hot_plug,
-		#endif
 		#if CONFIG(DRIVERS_INTEL_USB4_RETIMER)
 		&thunderbolt,
 		#endif
diff --git a/src/mainboard/starlabs/starbook/variants/adl/devicetree.cb b/src/mainboard/starlabs/starbook/variants/adl/devicetree.cb
index 675cc27d3b..55cc2d5cb5 100644
--- a/src/mainboard/starlabs/starbook/variants/adl/devicetree.cb
+++ b/src/mainboard/starlabs/starbook/variants/adl/devicetree.cb
@@ -199,7 +199,6 @@ chip soc/intel/alderlake
 				.flags					= PCIE_RP_LTR | PCIE_RP_AER,
 				.pcie_rp_aspm				= ASPM_L0S_L1,
 				.PcieRpL1Substates			= L1_SS_L1_2,
-				.pcie_rp_detect_timeout_ms		= 50,
 
 			}"
 			smbios_slot_desc				"SlotTypeM2Socket3"
diff --git a/src/mainboard/starlabs/starbook/variants/adl/ramstage.c b/src/mainboard/starlabs/starbook/variants/adl/ramstage.c
index 1dbad4fc98..3e9cfb13c4 100644
--- a/src/mainboard/starlabs/starbook/variants/adl/ramstage.c
+++ b/src/mainboard/starlabs/starbook/variants/adl/ramstage.c
@@ -1,17 +1,9 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
-#include <option.h>
 #include <soc/ramstage.h>
 #include <common/pin_mux.h>
 
 void mainboard_silicon_init_params(FSP_S_CONFIG *supd)
 {
 	configure_pin_mux(supd);
-
-	/*
-	 * Enable Hot Plug on RP5 to slow down coreboot so that
-	 * third-party drives are detected.
-	 */
-	if (get_uint_option("pci_hot_plug", 0) == 1)
-		supd->PcieRpHotPlug[8] = 1;
 }
diff --git a/src/mainboard/starlabs/starbook/variants/adl_n/devicetree.cb b/src/mainboard/starlabs/starbook/variants/adl_n/devicetree.cb
index f0f16c4337..ca436a0d40 100644
--- a/src/mainboard/starlabs/starbook/variants/adl_n/devicetree.cb
+++ b/src/mainboard/starlabs/starbook/variants/adl_n/devicetree.cb
@@ -184,7 +184,6 @@ chip soc/intel/alderlake
 				.flags					= PCIE_RP_LTR | PCIE_RP_AER,
 				.pcie_rp_aspm				= ASPM_L0S_L1,
 				.PcieRpL1Substates			= L1_SS_L1_2,
-				.pcie_rp_detect_timeout_ms		= 50,
 
 			}"
 			smbios_slot_desc				"SlotTypeM2Socket3"
diff --git a/src/mainboard/starlabs/starfighter/variants/mtl/devicetree.cb b/src/mainboard/starlabs/starfighter/variants/mtl/devicetree.cb
index b7b8cedf85..11384b8f13 100644
--- a/src/mainboard/starlabs/starfighter/variants/mtl/devicetree.cb
+++ b/src/mainboard/starlabs/starfighter/variants/mtl/devicetree.cb
@@ -250,7 +250,6 @@ chip soc/intel/meteorlake
 				.flags					= PCIE_RP_LTR | PCIE_RP_AER,
 				.pcie_rp_aspm				= ASPM_L0S_L1,
 				.PcieRpL1Substates			= L1_SS_L1_2,
-				.pcie_rp_detect_timeout_ms		= 15,
 			}"
 
 			smbios_slot_desc				"SlotTypeM2Socket3"
diff --git a/src/mainboard/starlabs/starfighter/variants/rpl/devicetree.cb b/src/mainboard/starlabs/starfighter/variants/rpl/devicetree.cb
index 080bde0a19..20d2e3ba67 100644
--- a/src/mainboard/starlabs/starfighter/variants/rpl/devicetree.cb
+++ b/src/mainboard/starlabs/starfighter/variants/rpl/devicetree.cb
@@ -253,7 +253,6 @@ chip soc/intel/alderlake
 				.flags					= PCIE_RP_LTR | PCIE_RP_AER,
 				.pcie_rp_aspm				= ASPM_L0S_L1,
 				.PcieRpL1Substates			= L1_SS_L1_2,
-				.pcie_rp_detect_timeout_ms		= 50,
 			}"
 
 			smbios_slot_desc				"SlotTypeM2Socket3"

From f5c9c1c166577c1eaf324a9de16b0adb395f5a86 Mon Sep 17 00:00:00 2001
From: Venkateshwar S <vens@qualcomm.corp-partner.google.com>
Date: Wed, 18 Feb 2026 04:01:58 -0800
Subject: [PATCH 3569/3886] mb/google/bluey: Move ADSP QUP-I2C init to normal
 boot path

The ADSP I2C initialization for charger/fuel-gauge is needed in both
normal boot and the off-mode/low-battery charging path. This patch
moves it before the conditional mainboard initialization skip, so it
runs in all cases.

BUG=b:436391478
TEST=Able to build and boot google/bluey.

Change-Id: I7a5c4e9c2a066a2ae43d57a87902528c93faecc5
Signed-off-by: Venkateshwar S <vens@qualcomm.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91365
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/google/bluey/mainboard.c | 7 +++----
 1 file changed, 3 insertions(+), 4 deletions(-)

diff --git a/src/mainboard/google/bluey/mainboard.c b/src/mainboard/google/bluey/mainboard.c
index 64212d0e84..ac80ceef80 100644
--- a/src/mainboard/google/bluey/mainboard.c
+++ b/src/mainboard/google/bluey/mainboard.c
@@ -172,6 +172,9 @@ static void mainboard_init(struct device *dev)
 	if (get_boot_mode() == LB_BOOT_MODE_LOW_BATTERY)
 		trigger_critical_battery_shutdown();
 
+	/* ADSP I2C (Charger/Fuel gauge) */
+	qupv3_se_fw_load_and_init(QUPV3_2_SE4, SE_PROTOCOL_I2C, MIXED);
+
 	configure_parallel_charging_late();
 
 	/* Skip mainboard initialization if boot mode is "low-battery" or "off-mode charging" */
@@ -206,10 +209,6 @@ static void mainboard_init(struct device *dev)
 	qupv3_se_fw_load_and_init(QUPV3_1_SE6, SE_PROTOCOL_UART, FIFO); /* BT UART */
 	qupv3_se_fw_load_and_init(QUPV3_0_SE0, SE_PROTOCOL_I2C, MIXED); /* Trackpad I2C */
 
-	/* ADSP I2C (Charger/Fuel gauge) */
-	qupv3_se_fw_load_and_init(QUPV3_2_SE4, SE_PROTOCOL_I2C, MIXED);
-
-
 	if (CONFIG(MAINBOARD_HAS_PS8820_RETIMER)) {
 		i2c_init(QUPV3_0_SE3, I2C_SPEED_FAST); /* USB-C0 Re-Timer I2C */
 		i2c_init(QUPV3_0_SE7, I2C_SPEED_FAST); /* USB-C1 Re-Timer I2C */

From 036af49b1db1d45ed5d5ada4efbae2de4fbde071 Mon Sep 17 00:00:00 2001
From: "Evie (Ivi) Ballou" <iviballou@gmail.com>
Date: Sun, 1 Feb 2026 01:44:40 +0200
Subject: [PATCH 3570/3886] mb/emul/qemu-q35: Add a _DIS method for gsi_link
 devices

This solves the remark:
```
dsdt.asl    430-437:   Device(GSIA-H) { Name(_HID, EISAID("PNP0C0F")) Name(_UID, 0) Name(_PRS, ResourceTemplate() { Interrupt(, Level, ActiveHigh, Shared) { 0x17 } }) Name(_CRS, ResourceTemplate() { Interrupt(, Level, ActiveHigh, Shared) { 0x17 } }) Method(_SRS, 1, NotSerialized
[*** iASL: Very long input line, message below refers to column 13 ***]
Remark   2141 -    Missing dependency (Device has a _SRS, no corresponding _DIS)
```

Change-Id: I5c30ed8e7eef324373c3cec6bf16ddcc056c055b
Signed-off-by: Evie (Ivi) Ballou <iviballou@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91034
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/emulation/qemu-q35/dsdt.asl | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/src/mainboard/emulation/qemu-q35/dsdt.asl b/src/mainboard/emulation/qemu-q35/dsdt.asl
index d65f2de0ec..3fb615050a 100644
--- a/src/mainboard/emulation/qemu-q35/dsdt.asl
+++ b/src/mainboard/emulation/qemu-q35/dsdt.asl
@@ -350,6 +350,8 @@ DefinitionBlock (
 			})                                                  \
 			Method(_SRS, 1, NotSerialized) {                    \
 			}                                                   \
+			Method(_DIS, 0, NotSerialized) {                    \
+			}                                                   \
 		}
 
 		define_gsi_link(GSIA, 0, 0x10)

From 93444a0ce0652750c7c457229a38b5a1845fe772 Mon Sep 17 00:00:00 2001
From: "Evie (Ivi) Ballou" <iviballou@gmail.com>
Date: Sat, 31 Jan 2026 23:04:42 +0200
Subject: [PATCH 3571/3886] mb/emul/qemu-[q35,i440fx]: Create ICQR interrupt
 resource locally and use defined offset

This changes out the PRR0 named object for a method local variable
and avoids the use of a hardcoded offset

This solves the remark:
```
dsdt.asl    415:    Name(PRR0, ResourceTemplate() {
Remark   2173 -            ^ Creation of named objects within a method is highly inefficient, use globals or method local variables instead (\_SB.IQCR)
```

The IQCR function was tested, by evaluating it in the new
`dsdt.aml` file, as well as the old one with `acpiexec`:
`acpiexec -b "Evaluate _SB.IQCR $4bit_num_dec" dsdt.aml`,
where `$4bit_num_in_dec`, is a number between 0 and 15.

Expected output:
```
Evaluation of \_SB.IQCR returned object 0x5648f23cedd0, external buffer length 28
  [Buffer] Length 0B =     0000: 89 06 00 09 01 $4bit_num_hex 00 00 00 79 00                 // .........y.
```

Change-Id: I007d6b8df4eef4e8cb13cef45b95da7659d62cef
Signed-off-by: Evie (Ivi) Ballou <iviballou@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91033
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
---
 src/mainboard/emulation/qemu-i440fx/dsdt.asl | 15 ++++++++-------
 src/mainboard/emulation/qemu-q35/dsdt.asl    | 13 +++++++------
 2 files changed, 15 insertions(+), 13 deletions(-)

diff --git a/src/mainboard/emulation/qemu-i440fx/dsdt.asl b/src/mainboard/emulation/qemu-i440fx/dsdt.asl
index 749ecfe664..89f9d5fad0 100644
--- a/src/mainboard/emulation/qemu-i440fx/dsdt.asl
+++ b/src/mainboard/emulation/qemu-i440fx/dsdt.asl
@@ -218,16 +218,17 @@ DefinitionBlock (
 			}
 			Return (0x0B)
 		}
+
 		Method(IQCR, 1, Serialized) {
 			// _CRS method - get current settings
-			Name(PRR0, ResourceTemplate() {
-				Interrupt(, Level, ActiveHigh, Shared) { 0 }
-			})
-			CreateDWordField(PRR0, 0x05, PRRI)
-			If (Arg0 < 0x80) {
-				PRRI = Arg0
+			Local0 = ResourceTemplate() {
+				Interrupt(, Level, ActiveHigh, Shared,,, IRQ0) { 0 }
 			}
-			Return (PRR0)
+			CreateDWordField(Local0, IRQ0._INT, IRQV)
+			If (Arg0 < 0x80) {
+				IRQV = Arg0
+			}
+			Return (Local0)
 		}
 
 #define define_link(link, uid, reg)                             \
diff --git a/src/mainboard/emulation/qemu-q35/dsdt.asl b/src/mainboard/emulation/qemu-q35/dsdt.asl
index 3fb615050a..da809d6e61 100644
--- a/src/mainboard/emulation/qemu-q35/dsdt.asl
+++ b/src/mainboard/emulation/qemu-q35/dsdt.asl
@@ -291,14 +291,15 @@ DefinitionBlock (
 			}
 			Return (0x0B)
 		}
+
 		Method(IQCR, 1, Serialized) {
 			// _CRS method - get current settings
-			Name(PRR0, ResourceTemplate() {
-				Interrupt(, Level, ActiveHigh, Shared) { 0 }
-			})
-			CreateDWordField(PRR0, 0x05, PRRI)
-			PRRI = Arg0 & 0x0F
-			Return (PRR0)
+			Local0 = ResourceTemplate() {
+				Interrupt(, Level, ActiveHigh, Shared,,, IRQ0) { 0 }
+			}
+			CreateDWordField(Local0, IRQ0._INT, IRQV)
+			IRQV = Arg0 & 0x0F
+			Return (Local0)
 		}
 
 #define define_link(link, uid, reg)                             \

From 26006cc2176a8478414f5264d08b6755b4d52931 Mon Sep 17 00:00:00 2001
From: "Evie (Ivi) Ballou" <iviballou@gmail.com>
Date: Tue, 27 Jan 2026 03:18:20 +0200
Subject: [PATCH 3572/3886] util/ifdtool: show overlapping region name and
 range details

When updating regions using a flashrom file with overlapping regions
the error message now shows overlapping region names and their ranges.

e.g:

    Regions would overlap:
           IE : 7fff000-7ffffff
      10GbE_0 : 7fff000-7ffffff

Change-Id: Ie2417e477924f0085839306a8a51d1241e20a338
Signed-off-by: Evie (Ivi) Ballou <iviballou@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90940
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
---
 util/ifdtool/ifdtool.c | 13 ++++++++++++-
 1 file changed, 12 insertions(+), 1 deletion(-)

diff --git a/util/ifdtool/ifdtool.c b/util/ifdtool/ifdtool.c
index 0592785bf6..c741e1d7c5 100644
--- a/util/ifdtool/ifdtool.c
+++ b/util/ifdtool/ifdtool.c
@@ -2094,7 +2094,18 @@ static void new_layout(const char *filename, char *image, int size,
 
 		for (j = i + 1; j < max_regions; j++) {
 			if (regions_collide(&new_regions[i], &new_regions[j])) {
-				fprintf(stderr, "Regions would overlap.\n");
+				fprintf(stderr, "Regions would overlap:\n");
+
+				/* See which string is longer and make sure we pad the shorter one */
+				int region_name_len_i = strlen(region_name(i));
+				int region_name_len_j = strlen(region_name(j));
+				int padding = MAX(region_name_len_i, region_name_len_j);
+
+				/* Print the regions that overlap, and where each region is */
+				fprintf(stderr, "  %*s : %x-%x\n", padding, region_name(i),
+					new_regions[i].base, new_regions[i].limit);
+				fprintf(stderr, "  %*s : %x-%x\n", padding, region_name(j),
+					new_regions[j].base, new_regions[j].limit);
 				exit(EXIT_FAILURE);
 			}
 		}

From 343f439801225353201d8157b17e2eaa30da85ee Mon Sep 17 00:00:00 2001
From: Ivi Ballou <iviballou@gmail.com>
Date: Wed, 25 Feb 2026 17:58:50 +0200
Subject: [PATCH 3573/3886] util/inteltool: set amb registers dumping error
 print to stdout

Set the "Error: Dumping AMBs on this MCH is not (yet) supported."
message to stdout. All other "dumping ... not (yet) supported"
errors use stdout, which makes them usable with pagers like less.

The current behavior prints the AMB dumping error in stderr,
which breaks pagers. This change aims to fix this discrepancy.

Change-Id: I502e9f8d5c71953e844bdc7174b3c7bd2987d00f
Signed-off-by: Ivi Ballou <iviballou@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91419
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
---
 util/inteltool/amb.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/util/inteltool/amb.c b/util/inteltool/amb.c
index 961c0abf36..b01ea4326b 100644
--- a/util/inteltool/amb.c
+++ b/util/inteltool/amb.c
@@ -431,7 +431,7 @@ int print_ambs(struct pci_dev *dev, struct pci_access *pacc)
 		break;
 
 	default:
-		fprintf(stderr, "Error: Dumping AMBs on this MCH is not (yet) supported.\n");
+		printf("Error: Dumping AMBs on this MCH is not (yet) supported.\n");
 		return 1;
 	}
 

From 8998999eb31a35efbc987d5bc597156fb5c50042 Mon Sep 17 00:00:00 2001
From: Angel Pons <th3fanbus@gmail.com>
Date: Sat, 28 Feb 2026 20:22:49 +0100
Subject: [PATCH 3574/3886] Haswell NRI: Add dumping of CAPID registers

If `CONFIG(DEBUG_RAM_SETUP)`, dump the values of the CAPID0_A and
CAPID0_B registers to the log. This is useful debugging information.

Dump the CAPID registers' values before native chipset init, because
dynamic fusing changes the CAPID values.

Tested on ASRock Z97 Extreme6 with a PCIe card plugged into the PCIE4
slot (forcing PEG to be bifurcated as x8+x8). The CPU and PCH are:

    CPU id(306c3) ucode:00000028 Intel(R) Core(TM) i7-4770S CPU @ 3.10GHz
    AES supported, TXT supported, VT supported
    PCH type: Z97, device id: 8cc4, rev id 0

CAPID values before dynamic fusing are shown below:

CAPID0_A: 0x6204e861
    DDR3L 1.35V:        Yes
    DDR Write Vref:     No
    OC enabled (DSKU):  No
    DDR overclock:      No
    Compatibility RID:  0x6
    Capability DID:     Desktop
    DID override:       No
    Integrated GPU:     No
    Dual channel:       Yes
    X2APIC support:     Yes
    DIMMs per channel:  1
    Camarillo device:   No
    Full ULT info:      Yes
    DDR 1N mode:        Yes
    PCIe ratio:         No
    Max channel size:   16 GiB
    PEG Gen2 support:   Yes
    DMI Gen2 support:   Yes
    VT-d support:       Yes
    ECC forced:         No
    ECC supported:      No
    DMI width:          x4
    Width upconfig:     Yes
    PEG function 0:     Yes
    PEG function 1:     No
    PEG function 2:     No
    Disp HD audio:      Yes

CAPID0_B: 0x565400d0
    PEG for GFX single: Unlimited width
    PEG for GFX multi:  Unlimited width
    133 MHz ref clock:  Up to DDR3-1600
    Silicon mode:       Production
    HDCP capable:       Yes
    Num PEG lanes:      16
    Add. GFX capable:   Yes
    Add. GFX enable:    Yes
    CPU Package Type:   0
    PEG Gen3 support:   No
    100 MHz ref clock:  Up to DDR3-1600
    Soft Bin capable:   No
    Cache size:         3
    SMT support:        Yes
    OC enabled (SSKU):  No
    OC controlled by:   SSKU

CAPID values after dynamic fusing are shown below, with manually
added arrows to indicate which values have changed:

CAPID0_A: 0x4204a06d
    DDR3L 1.35V:        Yes
    DDR Write Vref:     No
    OC enabled (DSKU):  Yes              <-----
    DDR overclock:      Yes              <-----
    Compatibility RID:  0x6
    Capability DID:     Desktop
    DID override:       No
    Integrated GPU:     Yes              <-----
    Dual channel:       Yes
    X2APIC support:     Yes
    DIMMs per channel:  2                <-----
    Camarillo device:   No
    Full ULT info:      Yes
    DDR 1N mode:        Yes
    PCIe ratio:         No
    Max channel size:   16 GiB
    PEG Gen2 support:   Yes
    DMI Gen2 support:   Yes
    VT-d support:       Yes
    ECC forced:         No
    ECC supported:      No
    DMI width:          x4
    Width upconfig:     Yes
    PEG function 0:     Yes
    PEG function 1:     Yes              <-----
    PEG function 2:     No
    Disp HD audio:      Yes

CAPID0_B: 0x564400d0
    PEG for GFX single: Unlimited width
    PEG for GFX multi:  Unlimited width
    133 MHz ref clock:  Up to DDR3-1600
    Silicon mode:       Production
    HDCP capable:       Yes
    Num PEG lanes:      16
    Add. GFX capable:   Yes
    Add. GFX enable:    Yes
    CPU Package Type:   0
    PEG Gen3 support:   Yes              <-----
    100 MHz ref clock:  Up to DDR3-1600
    Soft Bin capable:   No
    Cache size:         3
    SMT support:        Yes
    OC enabled (SSKU):  No
    OC controlled by:   SSKU

Change-Id: I46f27c54a7ec7fd9fc79fdabaa59a44a591168b8
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91478
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
---
 .../intel/haswell/native_raminit/Makefile.mk  |   2 +
 .../intel/haswell/native_raminit/info_dumps.c | 115 ++++++++++++++++++
 .../haswell/native_raminit/raminit_native.c   |   5 +
 .../haswell/native_raminit/raminit_native.h   |   2 +
 .../haswell/native_raminit/reg_structs.h      |  59 +++++++++
 5 files changed, 183 insertions(+)
 create mode 100644 src/northbridge/intel/haswell/native_raminit/info_dumps.c

diff --git a/src/northbridge/intel/haswell/native_raminit/Makefile.mk b/src/northbridge/intel/haswell/native_raminit/Makefile.mk
index c7a5f4ba5a..7a3346ca78 100644
--- a/src/northbridge/intel/haswell/native_raminit/Makefile.mk
+++ b/src/northbridge/intel/haswell/native_raminit/Makefile.mk
@@ -23,3 +23,5 @@ romstage-y += train_jedec_write_leveling.c
 romstage-y += train_read_mpr.c
 romstage-y += train_receive_enable.c
 romstage-y += train_sense_amp_offset.c
+
+romstage-$(CONFIG_DEBUG_RAM_SETUP) += info_dumps.c
diff --git a/src/northbridge/intel/haswell/native_raminit/info_dumps.c b/src/northbridge/intel/haswell/native_raminit/info_dumps.c
new file mode 100644
index 0000000000..5ff6306e7e
--- /dev/null
+++ b/src/northbridge/intel/haswell/native_raminit/info_dumps.c
@@ -0,0 +1,115 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <console/console.h>
+#include <device/pci_ops.h>
+#include <northbridge/intel/haswell/haswell.h>
+#include <types.h>
+
+#include "raminit_native.h"
+
+void dump_capid_values(void)
+{
+	static const char *const no_yes[] = {
+		[0] = "No",
+		[1] = "Yes",
+	};
+	static const char *const cdid_decoder[] = {
+		[0] = "Desktop",
+		[1] = "Server",
+		[2] = "Mobile",
+		[3] = "Marketing Spare",
+	};
+	static const char *const ddrsz_lut[] = {
+		[0] = "16",
+		[1] = "8",
+		[2] = "2",
+		[3] = "0.5",
+	};
+	static const char *const pegfx1_lut[] = {
+		[0] = "Unlimited width",
+		[1] = "Limited to x1",
+	};
+	static const char *const dmfc_lut[] = {
+		[0] = "Unlimited",
+		[1] = "Up to DDR3-2667",
+		[2] = "Up to DDR3-2400",
+		[3] = "Up to DDR3-2133",
+		[4] = "Up to DDR3-1867",
+		[5] = "Up to DDR3-1600",
+		[6] = "Up to DDR3-1333",
+		[7] = "Up to DDR3-1067",
+	};
+	static const char *const ddd_lut[] = {
+		[0] = "Debug",
+		[1] = "Production",
+	};
+	static const char *const pll100_lut[] = {
+		[0] = "Not supported",
+		[1] = "Up to DDR3-1400",
+		[2] = "Up to DDR3-1600",
+		[3] = "Up to DDR3-1800",
+		[4] = "Up to DDR3-2000",
+		[5] = "Up to DDR3-2200",
+		[6] = "Up to DDR3-2400",
+		[7] = "Unlimited",
+	};
+	static const char *const occtl_lut[] = {
+		[0] = "DSKU",
+		[1] = "SSKU",
+	};
+
+	const union pci_capid0_a_reg capid0_a = {
+		.raw = pci_read_config32(HOST_BRIDGE, CAPID0_A)
+	};
+	const union pci_capid0_b_reg capid0_b = {
+		.raw = pci_read_config32(HOST_BRIDGE, CAPID0_B)
+	};
+	printk(BIOS_DEBUG, "\n");
+	printk(BIOS_DEBUG, "CAPID0_A: 0x%08x\n", capid0_a.raw);
+	printk(BIOS_DEBUG, "    DDR3L 1.35V:        %s\n", no_yes[capid0_a.DDR3L_EN]);
+	printk(BIOS_DEBUG, "    DDR Write Vref:     %s\n", no_yes[capid0_a.DDR_WRTVREF]);
+	printk(BIOS_DEBUG, "    OC enabled (DSKU):  %s\n", no_yes[capid0_a.OC_ENABLED_DSKU]);
+	printk(BIOS_DEBUG, "    DDR overclock:      %s\n", no_yes[capid0_a.DDR_OVERCLOCK]);
+	printk(BIOS_DEBUG, "    Compatibility RID:  0x%01x\n", capid0_a.CRID);
+	printk(BIOS_DEBUG, "    Capability DID:     %s\n", cdid_decoder[capid0_a.CDID]);
+	printk(BIOS_DEBUG, "    DID override:       %s\n", no_yes[capid0_a.DIDOE]);
+	printk(BIOS_DEBUG, "    Integrated GPU:     %s\n", no_yes[!capid0_a.IGD]);
+	printk(BIOS_DEBUG, "    Dual channel:       %s\n", no_yes[!capid0_a.PDCD]);
+	printk(BIOS_DEBUG, "    X2APIC support:     %s\n", no_yes[capid0_a.X2APIC_EN]);
+	printk(BIOS_DEBUG, "    DIMMs per channel:  %u\n", capid0_a.DDPCD ? 1 : 2);
+	printk(BIOS_DEBUG, "    Camarillo device:   %s\n", no_yes[!capid0_a.CDD]);
+	printk(BIOS_DEBUG, "    Full ULT info:      %s\n", no_yes[!capid0_a.FUFRD]);
+	printk(BIOS_DEBUG, "    DDR 1N mode:        %s\n", no_yes[!capid0_a.D1NM]);
+	printk(BIOS_DEBUG, "    PCIe ratio:         %s\n", no_yes[!capid0_a.PCIE_RATIO_DIS]);
+	printk(BIOS_DEBUG, "    Max channel size:   %s GiB\n", ddrsz_lut[capid0_a.DDRSZ]);
+	printk(BIOS_DEBUG, "    PEG Gen2 support:   %s\n", no_yes[!capid0_a.PEGG2DIS]);
+	printk(BIOS_DEBUG, "    DMI Gen2 support:   %s\n", no_yes[!capid0_a.DMIG2DIS]);
+	printk(BIOS_DEBUG, "    VT-d support:       %s\n", no_yes[!capid0_a.VTDD]);
+	printk(BIOS_DEBUG, "    ECC forced:         %s\n", no_yes[capid0_a.FDEE]);
+	printk(BIOS_DEBUG, "    ECC supported:      %s\n", no_yes[!capid0_a.ECCDIS]);
+	printk(BIOS_DEBUG, "    DMI width:          x%u\n", capid0_a.DW ? 2 : 4);
+	printk(BIOS_DEBUG, "    Width upconfig:     %s\n", no_yes[!capid0_a.PELWUD]);
+	printk(BIOS_DEBUG, "    PEG function 0:     %s\n", no_yes[!capid0_a.PEG10D]);
+	printk(BIOS_DEBUG, "    PEG function 1:     %s\n", no_yes[!capid0_a.PEG11D]);
+	printk(BIOS_DEBUG, "    PEG function 2:     %s\n", no_yes[!capid0_a.PEG12D]);
+	printk(BIOS_DEBUG, "    Disp HD audio:      %s\n", no_yes[!capid0_a.DHDAD]);
+	printk(BIOS_DEBUG, "\n");
+	printk(BIOS_DEBUG, "CAPID0_B: 0x%08x\n", capid0_b.raw);
+	printk(BIOS_DEBUG, "    PEG for GFX single: %s\n", pegfx1_lut[capid0_b.SPEGFX1]);
+	printk(BIOS_DEBUG, "    PEG for GFX multi:  %s\n", pegfx1_lut[capid0_b.DPEGFX1]);
+	printk(BIOS_DEBUG, "    133 MHz ref clock:  %s\n", dmfc_lut[capid0_b.DMFC]);
+	printk(BIOS_DEBUG, "    Silicon mode:       %s\n", ddd_lut[capid0_b.DDD]);
+	printk(BIOS_DEBUG, "    HDCP capable:       %s\n", no_yes[!capid0_b.HDCPD]);
+	printk(BIOS_DEBUG, "    Num PEG lanes:      %u\n", capid0_b.PEGX16D ? 8 : 16);
+	printk(BIOS_DEBUG, "    Add. GFX capable:   %s\n", no_yes[!capid0_b.ADDGFXCAP]);
+	printk(BIOS_DEBUG, "    Add. GFX enable:    %s\n", no_yes[capid0_b.ADDGFXEN]);
+	printk(BIOS_DEBUG, "    CPU Package Type:   %u\n", capid0_b.PKGTYP);
+	printk(BIOS_DEBUG, "    PEG Gen3 support:   %s\n", no_yes[!capid0_b.PEGG3_DIS]);
+	printk(BIOS_DEBUG, "    100 MHz ref clock:  %s\n", pll100_lut[capid0_b.PLL_REF100_CFG]);
+	printk(BIOS_DEBUG, "    Soft Bin capable:   %s\n", no_yes[capid0_b.SOFTBIN]);
+	printk(BIOS_DEBUG, "    Cache size:         %u\n", capid0_b.CACHESZ);
+	printk(BIOS_DEBUG, "    SMT support:        %s\n", no_yes[capid0_b.SMT]);
+	printk(BIOS_DEBUG, "    OC enabled (SSKU):  %s\n", no_yes[capid0_b.OC_ENABLED_SSKU]);
+	printk(BIOS_DEBUG, "    OC controlled by:   %s\n", occtl_lut[capid0_b.OC_CTL_DSKU_DIS]);
+	printk(BIOS_DEBUG, "\n");
+}
diff --git a/src/northbridge/intel/haswell/native_raminit/raminit_native.c b/src/northbridge/intel/haswell/native_raminit/raminit_native.c
index d5b5c117d6..ab1e4ff1a3 100644
--- a/src/northbridge/intel/haswell/native_raminit/raminit_native.c
+++ b/src/northbridge/intel/haswell/native_raminit/raminit_native.c
@@ -171,6 +171,11 @@ void perform_raminit(const bool s3resume)
 	 */
 	const enum raminit_boot_mode orig_bootmode = get_boot_mode();
 
+	if (CONFIG(DEBUG_RAM_SETUP)) {
+		/* Log CAPID values before dynamic fusing takes place */
+		dump_capid_values();
+	}
+
 	const bool cpu_replaced = early_init_native(s3resume ? BOOTMODE_S3 : orig_bootmode);
 
 	wait_txt_clear();
diff --git a/src/northbridge/intel/haswell/native_raminit/raminit_native.h b/src/northbridge/intel/haswell/native_raminit/raminit_native.h
index 123f579a76..59dee35abe 100644
--- a/src/northbridge/intel/haswell/native_raminit/raminit_native.h
+++ b/src/northbridge/intel/haswell/native_raminit/raminit_native.h
@@ -703,4 +703,6 @@ uint8_t get_tCWL(uint32_t mem_clock_mhz);
 uint32_t get_tREFI(uint32_t mem_clock_mhz);
 uint32_t get_tXP(uint32_t mem_clock_mhz);
 
+void dump_capid_values(void);
+
 #endif
diff --git a/src/northbridge/intel/haswell/native_raminit/reg_structs.h b/src/northbridge/intel/haswell/native_raminit/reg_structs.h
index b0a121fa1a..9a64b2903a 100644
--- a/src/northbridge/intel/haswell/native_raminit/reg_structs.h
+++ b/src/northbridge/intel/haswell/native_raminit/reg_structs.h
@@ -3,6 +3,65 @@
 #ifndef HASWELL_RAMINIT_REG_STRUCTS_H
 #define HASWELL_RAMINIT_REG_STRUCTS_H
 
+union pci_capid0_a_reg {
+	struct __packed {
+		uint32_t DDR3L_EN        : 1; // Bits  0:0
+		uint32_t DDR_WRTVREF     : 1; // Bits  1:1
+		uint32_t OC_ENABLED_DSKU : 1; // Bits  2:2
+		uint32_t DDR_OVERCLOCK   : 1; // Bits  3:3
+		uint32_t CRID            : 4; // Bits  7:4
+		uint32_t CDID            : 2; // Bits  9:8
+		uint32_t DIDOE           : 1; // Bits 10:10
+		uint32_t IGD             : 1; // Bits 11:11
+		uint32_t PDCD            : 1; // Bits 12:12
+		uint32_t X2APIC_EN       : 1; // Bits 13:13
+		uint32_t DDPCD           : 1; // Bits 14:14
+		uint32_t CDD             : 1; // Bits 15:15
+		uint32_t FUFRD           : 1; // Bits 16:16
+		uint32_t D1NM            : 1; // Bits 17:17
+		uint32_t PCIE_RATIO_DIS  : 1; // Bits 18:18
+		uint32_t DDRSZ           : 2; // Bits 20:19
+		uint32_t PEGG2DIS        : 1; // Bits 21:21
+		uint32_t DMIG2DIS        : 1; // Bits 22:22
+		uint32_t VTDD            : 1; // Bits 23:23
+		uint32_t FDEE            : 1; // Bits 24:24
+		uint32_t ECCDIS          : 1; // Bits 25:25
+		uint32_t DW              : 1; // Bits 26:26
+		uint32_t PELWUD          : 1; // Bits 27:27
+		uint32_t PEG10D          : 1; // Bits 28:28
+		uint32_t PEG11D          : 1; // Bits 29:29
+		uint32_t PEG12D          : 1; // Bits 30:30
+		uint32_t DHDAD           : 1; // Bits 31:31
+	};
+	uint32_t raw;
+};
+
+union pci_capid0_b_reg {
+	struct __packed {
+		uint32_t SPEGFX1         : 1; // Bits  0:0
+		uint32_t DPEGFX1         : 1; // Bits  1:1
+		uint32_t                 : 2; // Bits  3:2
+		uint32_t DMFC            : 3; // Bits  6:4
+		uint32_t DDD             : 1; // Bits  7:7
+		uint32_t                 : 3; // Bits 10:8
+		uint32_t HDCPD           : 1; // Bits 11:11
+		uint32_t                 : 4; // Bits 15:12
+		uint32_t PEGX16D         : 1; // Bits 16:16
+		uint32_t ADDGFXCAP       : 1; // Bits 17:17
+		uint32_t ADDGFXEN        : 1; // Bits 18:18
+		uint32_t PKGTYP          : 1; // Bits 19:19
+		uint32_t PEGG3_DIS       : 1; // Bits 20:20
+		uint32_t PLL_REF100_CFG  : 3; // Bits 23:21
+		uint32_t SOFTBIN         : 1; // Bits 24:24
+		uint32_t CACHESZ         : 3; // Bits 27:25
+		uint32_t SMT             : 1; // Bits 28:28
+		uint32_t OC_ENABLED_SSKU : 1; // Bits 29:29
+		uint32_t OC_CTL_DSKU_DIS : 1; // Bits 30:30
+		uint32_t                 : 1; // Bits 31:31
+	};
+	uint32_t raw;
+};
+
 union ddr_data_rx_train_rank_reg {
 	struct __packed {
 		uint32_t rcven : 9; // Bits  8:0

From 56e645d942572c1580d4546be843971f953e3291 Mon Sep 17 00:00:00 2001
From: Cliff Huang <cliff.huang@intel.com>
Date: Fri, 20 Feb 2026 15:26:21 -0800
Subject: [PATCH 3575/3886] mb/google/fatcat: Change Gen4 and Gen5 NVMe power
 sequence

Turn off Gen4 and Gen5 NVMe power at bootblock and turn on at romstage
to address device enumeration and link speed issues observed after power
cycles and warm/cold reboots. This change specifically resolves issues
seen with certain NVMe devices, particularly the Micron 3500, where
improper power sequencing can cause enumeration failures or incorrect
link speed negotiation.

BUG=none
TEST=Boot Fatcat board with Micron 3500 NVMe in Gen4/Gen5 M.2
slots. Perform multiple power cycles and warm/cold reboots. Verify
consistent NVMe enumeration and proper link speed using lspci output.

Signed-off-by: Cliff Huang <cliff.huang@intel.com>
Change-Id: Ie929a3010acd74237d29a77c7582f1cae837a2e2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91369
Reviewed-by: Pranava Y N <pranavayn@google.com>
Reviewed-by: Guvendik, Bora <bora.guvendik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 .../google/fatcat/variants/fatcat/fw_config.c | 23 ++++++++-----------
 .../google/fatcat/variants/fatcat/gpio.c      |  5 ++++
 2 files changed, 15 insertions(+), 13 deletions(-)

diff --git a/src/mainboard/google/fatcat/variants/fatcat/fw_config.c b/src/mainboard/google/fatcat/variants/fatcat/fw_config.c
index ccece4647f..329df7e09a 100644
--- a/src/mainboard/google/fatcat/variants/fatcat/fw_config.c
+++ b/src/mainboard/google/fatcat/variants/fatcat/fw_config.c
@@ -287,12 +287,10 @@ static const struct pad_config wwan_disable_pads[] = {
 /* Gen4 NVME: at the top M.2 slot */
 static const struct pad_config pre_mem_gen4_ssd_pwr_pads[] = {
 	/* GPP_B10:     GEN4_SSD_PWREN */
-	PAD_CFG_GPO(GPP_B10, 0, PLTRST),
+	PAD_CFG_GPO(GPP_B10, 1, PLTRST),
 };
 
 static const struct pad_config gen4_ssd_pads[] = {
-	/* GPP_B10:     GEN4_SSD_PWREN */
-	PAD_CFG_GPO(GPP_B10, 1, PLTRST),
 	/* GPP_B09:     M2_GEN4_SSD_RESET_N */
 	PAD_CFG_GPO(GPP_B09, 1, PLTRST),
 };
@@ -300,7 +298,7 @@ static const struct pad_config gen4_ssd_pads[] = {
 /* Gen5 NVME: at the bottom M.2 slot */
 static const struct pad_config pre_mem_gen5_ssd_pwr_pads[] = {
 	/* GPP_B16:     GEN5_SSD_PWREN */
-	PAD_CFG_GPO(GPP_B16, 0, PLTRST),
+	PAD_CFG_GPO(GPP_B16, 1, PLTRST),
 };
 
 static const struct pad_config gen5_ssd_pads[] = {
@@ -617,15 +615,6 @@ void fw_config_configure_pre_mem_gpio(void)
 	if (!fw_config_probe(FW_CONFIG(CELLULAR, CELLULAR_ABSENT)))
 		GPIO_CONFIGURE_PADS(pre_mem_wwan_pwr_seq1_pads);
 
-	if (fw_config_probe(FW_CONFIG(STORAGE, STORAGE_NVME_GEN4))) {
-		GPIO_CONFIGURE_PADS(pre_mem_gen4_ssd_pwr_pads);
-	} else if (fw_config_probe(FW_CONFIG(STORAGE, STORAGE_NVME_GEN5))) {
-		GPIO_CONFIGURE_PADS(pre_mem_gen5_ssd_pwr_pads);
-	} else if (fw_config_probe(FW_CONFIG(STORAGE, STORAGE_UNKNOWN))) {
-		GPIO_CONFIGURE_PADS(pre_mem_gen4_ssd_pwr_pads);
-		GPIO_CONFIGURE_PADS(pre_mem_gen5_ssd_pwr_pads);
-	}
-
 	if (!fw_config_probe(FW_CONFIG(SD, SD_NONE)))
 		GPIO_CONFIGURE_PADS(pre_mem_x1slot_pads);
 
@@ -645,6 +634,14 @@ void fw_config_configure_pre_mem_gpio(void)
 	if (fw_config_probe(FW_CONFIG(FP, FP_PRESENT)))
 		GPIO_CONFIGURE_PADS(pre_mem_fp_enable_pads);
 
+	if (fw_config_probe(FW_CONFIG(STORAGE, STORAGE_NVME_GEN4))) {
+		GPIO_CONFIGURE_PADS(pre_mem_gen4_ssd_pwr_pads);
+	} else if (fw_config_probe(FW_CONFIG(STORAGE, STORAGE_NVME_GEN5))) {
+		GPIO_CONFIGURE_PADS(pre_mem_gen5_ssd_pwr_pads);
+	} else if (fw_config_probe(FW_CONFIG(STORAGE, STORAGE_UNKNOWN))) {
+		GPIO_CONFIGURE_PADS(pre_mem_gen4_ssd_pwr_pads);
+		GPIO_CONFIGURE_PADS(pre_mem_gen5_ssd_pwr_pads);
+	}
 }
 
 void fw_config_gpio_padbased_override(struct pad_config *padbased_table)
diff --git a/src/mainboard/google/fatcat/variants/fatcat/gpio.c b/src/mainboard/google/fatcat/variants/fatcat/gpio.c
index 13e6bbe1e3..1d12f5629f 100644
--- a/src/mainboard/google/fatcat/variants/fatcat/gpio.c
+++ b/src/mainboard/google/fatcat/variants/fatcat/gpio.c
@@ -366,6 +366,11 @@ static const struct pad_config early_gpio_table[] = {
 	PAD_CFG_NF(GPP_H07, NONE, DEEP, NF1),
 	/* GPP_D15: SPI_TPM_INT_N */
 	PAD_CFG_GPI_APIC(GPP_D15, NONE, PLTRST, LEVEL, INVERT),
+
+	/* GPP_B10:     GEN4_SSD_PWREN */
+	PAD_CFG_GPO(GPP_B10, 0, PLTRST),
+	/* GPP_B16:     GEN5_SSD_PWREN */
+	PAD_CFG_GPO(GPP_B16, 0, PLTRST),
 };
 
 /* Pad configuration in romstage */

From 13bf2d95665bfa338b31920b51e5320249195e5f Mon Sep 17 00:00:00 2001
From: Bora Guvendik <bora.guvendik@intel.com>
Date: Fri, 27 Feb 2026 13:18:58 -0800
Subject: [PATCH 3576/3886] mb/google/fatcat: Enable C1 and package C-state
 auto-demotion

Remove explicit overrides for disable_c1_state_auto_demotion and
disable_package_c_state_demotion, reverting to the SoC default behavior
which allows the hardware to autonomously demote C1 and package
C-states.

BUG=b:455612673
TEST=Boot to OS on Google fatcat

Change-Id: Ica9348e668c64ac2b27f3970b23f963ba0a2e753
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91457
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
---
 .../google/fatcat/variants/baseboard/fatcat/devicetree.cb    | 5 -----
 1 file changed, 5 deletions(-)

diff --git a/src/mainboard/google/fatcat/variants/baseboard/fatcat/devicetree.cb b/src/mainboard/google/fatcat/variants/baseboard/fatcat/devicetree.cb
index c9b9ddb293..14dbd34db6 100644
--- a/src/mainboard/google/fatcat/variants/baseboard/fatcat/devicetree.cb
+++ b/src/mainboard/google/fatcat/variants/baseboard/fatcat/devicetree.cb
@@ -62,11 +62,6 @@ chip soc/intel/pantherlake
 	# Setting TCC of 100C = Tj max (110) - TCC_Offset (10)
 	register "tcc_offset" = "10"
 
-	# Disable C1 C-state auto-demotion
-	register "disable_c1_state_auto_demotion" = "true"
-	# Disable PKGC-state auto-demotion
-	register "disable_package_c_state_demotion" = "true"
-
 	# Enable Energy Reporting
 	register "pch_pm_energy_report_enable" = "true"
 

From b6ebb24a48d0658b75d9fa967fb052ef145abea7 Mon Sep 17 00:00:00 2001
From: Bora Guvendik <bora.guvendik@intel.com>
Date: Thu, 22 Jan 2026 08:17:08 -0800
Subject: [PATCH 3577/3886] util/spd_tools/src/spd_gen/lp5.go: Support LP5X
 9600Mbps
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Add support for LP5X 9600Mbps in SPD tool.

BUG=None
TEST=util/spd_tools/bin/spd_gen spd/lp5/memory_parts.json lp5

Change-Id: I1425fe08e3891f4a0a0627c8ab429ec72c06ffc5
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90867
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Ma, Zhixing <zhixing.ma@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
---
 util/spd_tools/src/spd_gen/lp5.go | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/util/spd_tools/src/spd_gen/lp5.go b/util/spd_tools/src/spd_gen/lp5.go
index f3586c7539..acb10abc66 100644
--- a/util/spd_tools/src/spd_gen/lp5.go
+++ b/util/spd_tools/src/spd_gen/lp5.go
@@ -209,6 +209,7 @@ var LP5SetInfo = map[int]LP5Set{
 		 *            = 1 / (speed grade / 2 / WCK:CK)      // "double data rate"
 		 */
 		speedToTCKMinPs: map[int]int{
+			9600: 833,  /* 1 / (9600 / 2 / 4) */
 			8533: 937,  /* 1 / (8533 / 2 / 4) */
 			7500: 1066, /* 1 / (7500 / 2 / 4) */
 			6400: 1250, /* 1 / (6400 / 2 / 4) */
@@ -374,6 +375,10 @@ var LP5BankArchToSPDEncoding = map[int]LP5BankArchParams{
  * From Table 220 of JESD209-5B, using a 4:1 WCK:CK ratio and Set 0.
  */
 var LP5SpeedMbpsToSPDEncoding = map[int]LP5SpeedParams{
+	9600: {
+		defaultTCKMinPs: 208, /* 1 / (9600 / 2) */
+		MaxCASLatency:   26,
+	},
 	8533: {
 		defaultTCKMinPs: 234, /* 1 / (8533 / 2) */
 		MaxCASLatency:   23,

From bce8d28a59b64e2d02ce804989955cf663770964 Mon Sep 17 00:00:00 2001
From: Nicholas Chin <nic.c3.14@gmail.com>
Date: Sun, 1 Mar 2026 09:56:00 -0700
Subject: [PATCH 3578/3886] MAINTAINERS: Add Nicholas Chin for autoport
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

I do push patches for autoport somewhat often (by autoport standards)
and have reviewed many patches for it in the past couple of years, so
add myself as a maintainer.

Change-Id: I897032eea898ff254d02df4d100e27966a6fc6ae
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91493
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jan Philipp Groß <jeangrande@mailbox.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
---
 MAINTAINERS | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/MAINTAINERS b/MAINTAINERS
index ce9b93d949..bd26cac7f4 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1040,6 +1040,11 @@ M:	Martin Roth <gaumless@gmail.com>
 S:	Supported
 F:	util/abuild/
 
+AUTOPORT
+M:	Nicholas Chin <nic.c3.14@gmail.com>
+S:	Maintained
+F:	util/autoport/
+
 BOARD STATUS
 F:	util/board_status/
 

From e0715bc0f9c707877891604aad14d6f75f67c387 Mon Sep 17 00:00:00 2001
From: Simon Yang <simon1.yang@intel.com>
Date: Tue, 2 Dec 2025 14:42:12 +0800
Subject: [PATCH 3579/3886] soc/intel/pantherlake: Disable PCIe PM in
 compliance test mode
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

When SOC_INTEL_COMPLIANCE_TEST_MODE is enabled, disable PCIe clock
gating and power gating to prevent the controller from entering power
management states that would interfere with PCIe compliance testing.

This ensures stable operation during PCIe TX compliance tests by
keeping the PCIe controller in an active state throughout the test
process.

Affected/Verified Platforms:
  - PTL: Lapis, Ruby
  - WCL: Matsu, Ocicat, Kodkod

BUG=b:451560515
TEST="Run PCIe Compliance TX test successfully"

Change-Id: I92f442d24219af78310ce04b782735beed9c58e6
Signed-off-by: Simon Yang <simon1.yang@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90325
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/soc/intel/pantherlake/fsp_params.c | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/src/soc/intel/pantherlake/fsp_params.c b/src/soc/intel/pantherlake/fsp_params.c
index d447879475..226ae1677a 100644
--- a/src/soc/intel/pantherlake/fsp_params.c
+++ b/src/soc/intel/pantherlake/fsp_params.c
@@ -589,6 +589,10 @@ static void fill_fsps_pcie_params(FSP_S_CONFIG *s_cfg,
 	uint32_t enable_mask = pcie_rp_enable_mask(get_pcie_rp_table());
 
 	for (size_t i = 0; i < CONFIG_MAX_ROOT_PORTS; i++) {
+		if (CONFIG(SOC_INTEL_COMPLIANCE_TEST_MODE)) {
+			s_cfg->PcieClockGating[i] = 0;
+			s_cfg->PciePowerGating[i] = 0;
+		}
 		if (!(enable_mask & BIT(i)))
 			continue;
 		const struct pcie_rp_config *rp_cfg = &config->pcie_rp[i];

From 0e9c2f53b0128c0802b70d4f89dd68352665155f Mon Sep 17 00:00:00 2001
From: Angel Pons <th3fanbus@gmail.com>
Date: Fri, 27 Feb 2026 20:08:11 +0100
Subject: [PATCH 3580/3886] haswell/broadwell: Move CPU bus ops to CPU code

Commit 4c4bd3cd973f ("soc/intel/broadwell: Hook up PCI domain and CPU
cluster ops to devicetree") and commit 600fa266bdc8 ("nb/intel/haswell:
Hook up PCI domain and CPU cluster ops to devicetree") decoupled the CPU
bus device operations from northbridge code. Since Haswell and Broadwell
both use the same CPU code, move the CPU bus ops to CPU code in order to
deduplicate them.

Change-Id: I11cbff3d87e233f40a40f2fc70840f6bf35b0cb9
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91463
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/cpu/intel/haswell/haswell_init.c            | 7 +++++++
 src/mainboard/google/auron/devicetree.cb        | 2 +-
 src/mainboard/google/jecht/devicetree.cb        | 2 +-
 src/mainboard/hp/elitebook_820_g2/devicetree.cb | 2 +-
 src/mainboard/intel/wtm2/devicetree.cb          | 2 +-
 src/mainboard/purism/librem_bdw/devicetree.cb   | 2 +-
 src/northbridge/intel/haswell/northbridge.c     | 7 -------
 src/soc/intel/broadwell/northbridge.c           | 7 -------
 8 files changed, 12 insertions(+), 19 deletions(-)

diff --git a/src/cpu/intel/haswell/haswell_init.c b/src/cpu/intel/haswell/haswell_init.c
index bd8932a039..c21f3c09f8 100644
--- a/src/cpu/intel/haswell/haswell_init.c
+++ b/src/cpu/intel/haswell/haswell_init.c
@@ -606,6 +606,13 @@ static const struct cpu_device_id cpu_table[] = {
 	CPU_TABLE_END
 };
 
+struct device_operations haswell_cpu_bus_ops = {
+	.read_resources   = noop_read_resources,
+	.set_resources    = noop_set_resources,
+	.init             = mp_cpu_bus_init,
+	.acpi_fill_ssdt   = generate_cpu_entries,
+};
+
 static const struct cpu_driver driver __cpu_driver = {
 	.ops      = &cpu_dev_ops,
 	.id_table = cpu_table,
diff --git a/src/mainboard/google/auron/devicetree.cb b/src/mainboard/google/auron/devicetree.cb
index 49db518760..6d42e1f810 100644
--- a/src/mainboard/google/auron/devicetree.cb
+++ b/src/mainboard/google/auron/devicetree.cb
@@ -15,7 +15,7 @@ chip soc/intel/broadwell
 	register "ec_present" = "true"
 
 	chip cpu/intel/haswell
-		device cpu_cluster 0 on ops broadwell_cpu_bus_ops end
+		device cpu_cluster 0 on ops haswell_cpu_bus_ops end
 
 		register "s0ix_enable" = "true"
 	end
diff --git a/src/mainboard/google/jecht/devicetree.cb b/src/mainboard/google/jecht/devicetree.cb
index ba8167cda2..cdde70f503 100644
--- a/src/mainboard/google/jecht/devicetree.cb
+++ b/src/mainboard/google/jecht/devicetree.cb
@@ -12,7 +12,7 @@ chip soc/intel/broadwell
 	register "dq_pins_interleaved" = "true"
 
 	chip cpu/intel/haswell
-		device cpu_cluster 0 on ops broadwell_cpu_bus_ops end
+		device cpu_cluster 0 on ops haswell_cpu_bus_ops end
 	end
 
 	device domain 0 on
diff --git a/src/mainboard/hp/elitebook_820_g2/devicetree.cb b/src/mainboard/hp/elitebook_820_g2/devicetree.cb
index d6cb2ed016..626e6d56a7 100644
--- a/src/mainboard/hp/elitebook_820_g2/devicetree.cb
+++ b/src/mainboard/hp/elitebook_820_g2/devicetree.cb
@@ -2,7 +2,7 @@
 
 chip soc/intel/broadwell
 	chip cpu/intel/haswell
-		device cpu_cluster 0 on ops broadwell_cpu_bus_ops end
+		device cpu_cluster 0 on ops haswell_cpu_bus_ops end
 	end
 	device domain 0 on
 		ops broadwell_pci_domain_ops
diff --git a/src/mainboard/intel/wtm2/devicetree.cb b/src/mainboard/intel/wtm2/devicetree.cb
index 3b3a9750aa..9e1e8a03cb 100644
--- a/src/mainboard/intel/wtm2/devicetree.cb
+++ b/src/mainboard/intel/wtm2/devicetree.cb
@@ -10,7 +10,7 @@ chip soc/intel/broadwell
 	register "gpu_dp_b_hotplug" = "0x06"
 
 	chip cpu/intel/haswell
-		device cpu_cluster 0 on ops broadwell_cpu_bus_ops end
+		device cpu_cluster 0 on ops haswell_cpu_bus_ops end
 	end
 	device domain 0 on
 		ops broadwell_pci_domain_ops
diff --git a/src/mainboard/purism/librem_bdw/devicetree.cb b/src/mainboard/purism/librem_bdw/devicetree.cb
index 45350b6c13..f663afdd4c 100644
--- a/src/mainboard/purism/librem_bdw/devicetree.cb
+++ b/src/mainboard/purism/librem_bdw/devicetree.cb
@@ -21,7 +21,7 @@ chip soc/intel/broadwell
 	}"
 
 	chip cpu/intel/haswell
-		device cpu_cluster 0 on ops broadwell_cpu_bus_ops end
+		device cpu_cluster 0 on ops haswell_cpu_bus_ops end
 	end
 	device domain 0 on
 		ops broadwell_pci_domain_ops
diff --git a/src/northbridge/intel/haswell/northbridge.c b/src/northbridge/intel/haswell/northbridge.c
index c544ad3c38..e819838175 100644
--- a/src/northbridge/intel/haswell/northbridge.c
+++ b/src/northbridge/intel/haswell/northbridge.c
@@ -534,13 +534,6 @@ static const struct pci_driver mc_driver_hsw __pci_driver = {
 	.devices = mc_pci_device_ids,
 };
 
-struct device_operations haswell_cpu_bus_ops = {
-	.read_resources   = noop_read_resources,
-	.set_resources    = noop_set_resources,
-	.init             = mp_cpu_bus_init,
-	.acpi_fill_ssdt   = generate_cpu_entries,
-};
-
 struct chip_operations northbridge_intel_haswell_ops = {
 	.name = "Intel Haswell integrated Northbridge",
 };
diff --git a/src/soc/intel/broadwell/northbridge.c b/src/soc/intel/broadwell/northbridge.c
index 3d2574ba6d..c869b31035 100644
--- a/src/soc/intel/broadwell/northbridge.c
+++ b/src/soc/intel/broadwell/northbridge.c
@@ -406,13 +406,6 @@ struct device_operations broadwell_pci_domain_ops = {
 #endif
 };
 
-struct device_operations broadwell_cpu_bus_ops = {
-	.read_resources   = noop_read_resources,
-	.set_resources    = noop_set_resources,
-	.init             = mp_cpu_bus_init,
-	.acpi_fill_ssdt   = generate_cpu_entries,
-};
-
 static void broadwell_init_pre_device(void *chip_info)
 {
 	broadwell_run_reference_code();

From 6953c591bacc93f1fc210f0d5b9e0791bbc0d7b6 Mon Sep 17 00:00:00 2001
From: Angel Pons <th3fanbus@gmail.com>
Date: Fri, 27 Feb 2026 21:51:57 +0100
Subject: [PATCH 3581/3886] sb/intel/lynxpoint/acpi/serialio.asl: Add more
 _PS0/_PS3 methods

Implementation taken from Wildcat Point (Broadwell) code. This reduces
differences between both platforms.

Change-Id: Id3b6efcbc416929245fcaf329521d49fee0b457f
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91464
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
---
 .../intel/lynxpoint/acpi/serialio.asl         | 130 +++++++++++++-----
 1 file changed, 96 insertions(+), 34 deletions(-)

diff --git a/src/southbridge/intel/lynxpoint/acpi/serialio.asl b/src/southbridge/intel/lynxpoint/acpi/serialio.asl
index 845949ce98..4d26152d97 100644
--- a/src/southbridge/intel/lynxpoint/acpi/serialio.asl
+++ b/src/southbridge/intel/lynxpoint/acpi/serialio.asl
@@ -16,6 +16,28 @@ External (\S5EN)
 External (\S6EN)
 External (\S7EN)
 
+// Put SerialIO device in D0 state
+// Arg0 - Ref to offset 0x84 of device's PCI config space
+Method (LPD0, 1, Serialized)
+{
+	Arg0 = DeRefOf (Arg0) & 0xFFFFFFFC
+	Local0 = DeRefOf (Arg0) // Read back after writing
+
+	// Use Local0 to avoid iasl warning: Method Local is set but never used
+	Local0 &= Ones
+}
+
+// Put SerialIO device in D3 state
+// Arg0 - Ref to offset 0x84 of device's PCI config space
+Method (LPD3, 1, Serialized)
+{
+	Arg0 = DeRefOf (Arg0) | 0x3
+	Local0 = DeRefOf (Arg0) // Read back after writing
+
+	// Use Local0 to avoid iasl warning: Method Local is set but never used
+	Local0 &= Ones
+}
+
 // Serial IO Resource Consumption for BAR1
 Device (SIOR)
 {
@@ -193,32 +215,20 @@ Device (I2C0)
 		}
 	}
 
-	// Access to PCI Config in ACPI mode
-	OperationRegion (KEYS, SystemMemory, \S1B1, 0x100)
-	Field (KEYS, DWordAcc, NoLock, Preserve)
+	OperationRegion (SPRT, SystemMemory, \S1B1 + 0x84, 4)
+	Field (SPRT, DWordAcc, NoLock, Preserve)
 	{
-		Offset (0x84),
-		PSAT, 32,
+		SPCS, 32
 	}
 
-	// Put controller in D0 state
 	Method (_PS0, 0, Serialized)
 	{
-		^PSAT &= 0xfffffffc
-		Local0 = ^PSAT // Read back after writing
-
-		// Use Local0 to avoid iasl warning: Method Local is set but never used
-		Local0 &= Ones
+		^^LPD0 (RefOf (SPCS))
 	}
 
-	// Put controller in D3Hot state
 	Method (_PS3, 0, Serialized)
 	{
-		^PSAT |= 0x00000003
-		Local0 = ^PSAT // Read back after writing
-
-		// Use Local0 to avoid iasl warning: Method Local is set but never used
-		Local0 &= Ones
+		^^LPD3 (RefOf (SPCS))
 	}
 }
 
@@ -273,32 +283,20 @@ Device (I2C1)
 		}
 	}
 
-	// Access to PCI Config in ACPI mode
-	OperationRegion (KEYS, SystemMemory, \S2B1, 0x100)
-	Field (KEYS, DWordAcc, NoLock, Preserve)
+	OperationRegion (SPRT, SystemMemory, \S2B1 + 0x84, 4)
+	Field (SPRT, DWordAcc, NoLock, Preserve)
 	{
-		Offset (0x84),
-		PSAT, 32,
+		SPCS, 32
 	}
 
-	// Put controller in D0 state
 	Method (_PS0, 0, Serialized)
 	{
-		^PSAT &= 0xfffffffc
-		Local0 = ^PSAT // Read back after writing
-
-		// Use Local0 to avoid iasl warning: Method Local is set but never used
-		Local0 &= Ones
+		^^LPD0 (RefOf (SPCS))
 	}
 
-	// Put controller in D3Hot state
 	Method (_PS3, 0, Serialized)
 	{
-		^PSAT |= 0x00000003
-		Local0 = ^PSAT // Read back after writing
-
-		// Use Local0 to avoid iasl warning: Method Local is set but never used
-		Local0 &= Ones
+		^^LPD3 (RefOf (SPCS))
 	}
 }
 
@@ -337,6 +335,22 @@ Device (SPI0)
 			Return (0xF)
 		}
 	}
+
+	OperationRegion (SPRT, SystemMemory, \S3B1 + 0x84, 4)
+	Field (SPRT, DWordAcc, NoLock, Preserve)
+	{
+		SPCS, 32
+	}
+
+	Method (_PS0, 0, Serialized)
+	{
+		^^LPD0 (RefOf (SPCS))
+	}
+
+	Method (_PS3, 0, Serialized)
+	{
+		^^LPD3 (RefOf (SPCS))
+	}
 }
 
 Device (SPI1)
@@ -386,6 +400,22 @@ Device (SPI1)
 			Return (0xF)
 		}
 	}
+
+	OperationRegion (SPRT, SystemMemory, \S4B1 + 0x84, 4)
+	Field (SPRT, DWordAcc, NoLock, Preserve)
+	{
+		SPCS, 32
+	}
+
+	Method (_PS0, 0, Serialized)
+	{
+		^^LPD0 (RefOf (SPCS))
+	}
+
+	Method (_PS3, 0, Serialized)
+	{
+		^^LPD3 (RefOf (SPCS))
+	}
 }
 
 Device (UAR0)
@@ -435,6 +465,22 @@ Device (UAR0)
 			Return (0xF)
 		}
 	}
+
+	OperationRegion (SPRT, SystemMemory, \S5B1 + 0x84, 4)
+	Field (SPRT, DWordAcc, NoLock, Preserve)
+	{
+		SPCS, 32
+	}
+
+	Method (_PS0, 0, Serialized)
+	{
+		^^LPD0 (RefOf (SPCS))
+	}
+
+	Method (_PS3, 0, Serialized)
+	{
+		^^LPD3 (RefOf (SPCS))
+	}
 }
 
 Device (UAR1)
@@ -472,6 +518,22 @@ Device (UAR1)
 			Return (0xF)
 		}
 	}
+
+	OperationRegion (SPRT, SystemMemory, \S6B1 + 0x84, 4)
+	Field (SPRT, DWordAcc, NoLock, Preserve)
+	{
+		SPCS, 32
+	}
+
+	Method (_PS0, 0, Serialized)
+	{
+		^^LPD0 (RefOf (SPCS))
+	}
+
+	Method (_PS3, 0, Serialized)
+	{
+		^^LPD3 (RefOf (SPCS))
+	}
 }
 
 Device (SDIO)

From 381ce51ec4546e690e8760a825de0876a14a3b4b Mon Sep 17 00:00:00 2001
From: Angel Pons <th3fanbus@gmail.com>
Date: Fri, 27 Feb 2026 20:58:06 +0100
Subject: [PATCH 3582/3886] sb/intel/lynxpoint/acpi: Add HIDs for Wildcat Point

Prepare to unify ACPI code for Lynx Point and Wildcat Point.

Change-Id: I0d70e5c8ca585d0225227831d18874cdd2cbf09d
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91465
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/southbridge/intel/lynxpoint/acpi/gpio.asl | 10 ++-
 .../intel/lynxpoint/acpi/serialio.asl         | 70 +++++++++++++++++--
 2 files changed, 72 insertions(+), 8 deletions(-)

diff --git a/src/southbridge/intel/lynxpoint/acpi/gpio.asl b/src/southbridge/intel/lynxpoint/acpi/gpio.asl
index a673b25604..f18c5486d9 100644
--- a/src/southbridge/intel/lynxpoint/acpi/gpio.asl
+++ b/src/southbridge/intel/lynxpoint/acpi/gpio.asl
@@ -3,7 +3,15 @@
 Device (GPIO)
 {
 	// GPIO Controller
-	Name (_HID, "INT33C7")
+	Method (_HID)
+	{
+		If (\ISWP ()) {
+			// WildcatPoint
+			Return ("INT3437")
+		}
+		// LynxPoint-LP
+		Return ("INT33C7")
+	}
 	Name (_CID, "INT33C7")
 	Name (_UID, 1)
 
diff --git a/src/southbridge/intel/lynxpoint/acpi/serialio.asl b/src/southbridge/intel/lynxpoint/acpi/serialio.asl
index 4d26152d97..95a3466709 100644
--- a/src/southbridge/intel/lynxpoint/acpi/serialio.asl
+++ b/src/southbridge/intel/lynxpoint/acpi/serialio.asl
@@ -167,7 +167,15 @@ Device (SDMA)
 Device (I2C0)
 {
 	// Serial IO I2C0 Controller
-	Name (_HID, "INT33C2")
+	Method (_HID)
+	{
+		If (\ISWP ()) {
+			// WildcatPoint
+			Return ("INT3432")
+		}
+		// LynxPoint-LP
+		Return ("INT33C2")
+	}
 	Name (_CID, "INT33C2")
 	Name (_UID, 1)
 
@@ -235,7 +243,15 @@ Device (I2C0)
 Device (I2C1)
 {
 	// Serial IO I2C1 Controller
-	Name (_HID, "INT33C3")
+	Method (_HID)
+	{
+		If (\ISWP ()) {
+			// WildcatPoint
+			Return ("INT3433")
+		}
+		// LynxPoint-LP
+		Return ("INT33C3")
+	}
 	Name (_CID, "INT33C3")
 	Name (_UID, 1)
 
@@ -303,7 +319,15 @@ Device (I2C1)
 Device (SPI0)
 {
 	// Serial IO SPI0 Controller
-	Name (_HID, "INT33C0")
+	Method (_HID)
+	{
+		If (\ISWP ()) {
+			// WildcatPoint
+			Return ("INT3430")
+		}
+		// LynxPoint-LP
+		Return ("INT33C0")
+	}
 	Name (_CID, "INT33C0")
 	Name (_UID, 1)
 
@@ -356,7 +380,15 @@ Device (SPI0)
 Device (SPI1)
 {
 	// Serial IO SPI1 Controller
-	Name (_HID, "INT33C1")
+	Method (_HID)
+	{
+		If (\ISWP ()) {
+			// WildcatPoint
+			Return ("INT3431")
+		}
+		// LynxPoint-LP
+		Return ("INT33C1")
+	}
 	Name (_CID, "INT33C1")
 	Name (_UID, 1)
 
@@ -421,7 +453,15 @@ Device (SPI1)
 Device (UAR0)
 {
 	// Serial IO UART0 Controller
-	Name (_HID, "INT33C4")
+	Method (_HID)
+	{
+		If (\ISWP ()) {
+			// WildcatPoint
+			Return ("INT3434")
+		}
+		// LynxPoint-LP
+		Return ("INT33C4")
+	}
 	Name (_CID, "INT33C4")
 	Name (_UID, 1)
 
@@ -486,7 +526,15 @@ Device (UAR0)
 Device (UAR1)
 {
 	// Serial IO UART1 Controller
-	Name (_HID, "INT33C5")
+	Method (_HID)
+	{
+		If (\ISWP ()) {
+			// WildcatPoint
+			Return ("INT3435")
+		}
+		// LynxPoint-LP
+		Return ("INT33C5")
+	}
 	Name (_CID, "INT33C5")
 	Name (_UID, 1)
 
@@ -539,7 +587,15 @@ Device (UAR1)
 Device (SDIO)
 {
 	// Serial IO SDIO Controller
-	Name (_HID, "INT33C6")
+	Method (_HID)
+	{
+		If (\ISWP ()) {
+			// WildcatPoint
+			Return ("INT3436")
+		}
+		// LynxPoint-LP
+		Return ("INT33C6")
+	}
 	Name (_CID, "PNP0D40")
 	Name (_UID, 1)
 

From 8b69dcccb2f93a974e80dad82220d802a11c6d42 Mon Sep 17 00:00:00 2001
From: Angel Pons <th3fanbus@gmail.com>
Date: Sat, 28 Feb 2026 00:15:31 +0100
Subject: [PATCH 3583/3886] sb/intel/lynxpoint/pcie.c: Add additional disable
 steps

Taken from Wildcat Point and checked against version 1.9.1 of PCH
reference code. Note down a few TODOs to be done after Lynx Point
and Wildcat Point code has been unified.

Change-Id: I91aa3f0a5ea67bd43a625f37527c9d41c277b990
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91466
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
---
 src/southbridge/intel/lynxpoint/pcie.c | 21 +++++++++++++++++++++
 1 file changed, 21 insertions(+)

diff --git a/src/southbridge/intel/lynxpoint/pcie.c b/src/southbridge/intel/lynxpoint/pcie.c
index 7aff60895c..19a1bcf203 100644
--- a/src/southbridge/intel/lynxpoint/pcie.c
+++ b/src/southbridge/intel/lynxpoint/pcie.c
@@ -3,6 +3,7 @@
 #include <assert.h>
 #include <commonlib/helpers.h>
 #include <console/console.h>
+#include <delay.h>
 #include <device/device.h>
 #include <device/pci.h>
 #include <device/pciexp.h>
@@ -326,6 +327,26 @@ static void root_port_commit_config(void)
 		pci_and_config16(dev, PCI_COMMAND,
 				~(PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO));
 
+		/* 8.2 Configuration of PCI Express Root Ports */
+		/* TODO: This should not be done if a card is detected */
+		pci_or_config32(dev, 0x338, 1 << 26);
+
+		/* TODO: BWG specifies 50 ms timeout */
+		int n = 0;
+		do {
+			u32 reg32 = pci_read_config32(dev, 0x328);
+			n++;
+			if (((reg32 & 0xff000000) == 0x01000000) || (n > 50))
+				break;
+			udelay(100);
+		} while (1);
+
+		if (n > 50)
+			printk(BIOS_DEBUG, "%s: Timeout waiting for 328h\n",
+				dev_path(dev));
+
+		pci_or_config32(dev, 0x408, 1 << 27);
+
 		/* Disable this device if possible */
 		pch_disable_devfn(dev);
 	}

From 0d2a0512fd28c179e4807d87b2860a5341fc0ab8 Mon Sep 17 00:00:00 2001
From: Angel Pons <th3fanbus@gmail.com>
Date: Sat, 28 Feb 2026 00:56:34 +0100
Subject: [PATCH 3584/3886] sb/intel/lynxpoint: Configure IOSF Port and Grant
 Count

Based on Wildcat Point and checked against version 1.9.1 of PCH
reference code. Note that this runs later in the init sequence,
compared to Wildcat Point, as it is easier to get the values of
the STRPFUSECFG registers this way.

Change-Id: I0fadd33d043e66c10d29dcf8ba9724723ad70a9b
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91467
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/southbridge/intel/lynxpoint/pcie.c | 26 ++++++++++++++++++++++++++
 1 file changed, 26 insertions(+)

diff --git a/src/southbridge/intel/lynxpoint/pcie.c b/src/southbridge/intel/lynxpoint/pcie.c
index 19a1bcf203..969095207d 100644
--- a/src/southbridge/intel/lynxpoint/pcie.c
+++ b/src/southbridge/intel/lynxpoint/pcie.c
@@ -132,6 +132,29 @@ static void update_num_ports(void)
 	       rpc.num_ports);
 }
 
+static u16 get_port_grant(u32 strpfusecfg)
+{
+	switch ((strpfusecfg >> 14) & 0x3) {
+	case 1: /* 2+1+1 */
+	case 3: /* 4 */
+		return 0x02;
+	case 2: /* 2+2 */
+		return 0x22;
+	case 0: /* 1+1+1+1 */
+	default:
+		return 0x00;
+	}
+}
+
+static void set_iosf_port_grant_count(void)
+{
+	u16 reg16 = get_port_grant(rpc.strpfusecfg1) << 0;
+	if (!pch_is_lp())
+		reg16 |= get_port_grant(rpc.strpfusecfg2) << 8;
+
+	RCBA16(0x103c) = reg16;
+}
+
 static void root_port_init_config(struct device *dev)
 {
 	int rp;
@@ -308,6 +331,9 @@ static void root_port_commit_config(void)
 	/* Perform clock gating configuration. */
 	pcie_enable_clock_gating();
 
+	/* 8.13 IOSF Port Configuration and Grant Count Programming */
+	set_iosf_port_grant_count();
+
 	for (i = 0; i < rpc.num_ports; i++) {
 		struct device *dev;
 

From d740cee2d9bd25c7d6f003e4b611218f0f37d5dd Mon Sep 17 00:00:00 2001
From: Angel Pons <th3fanbus@gmail.com>
Date: Mon, 23 Feb 2026 21:17:38 +0100
Subject: [PATCH 3585/3886] soc/intel/broadwell/pch: Move to
 sb/intel/wildcatpoint

The PCH split was done many moons ago, in order to unify two codebases
with overlapping hardware support: Haswell + Lynx Point and Broadwell.
The on-package PCH found in Broadwell ULT/ULX CPUs is Wildcat Point.

This change only moves the files, and does the minimal amount of edits
so that boards still build. Most of those edits boil down to "find and
replace".

Change-Id: I29235b47970f81b5db6717801f2ab771ff980476
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91396
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/google/auron/devicetree.cb      |  2 +-
 src/mainboard/google/auron/dsdt.asl           |  4 +-
 .../variants/auron_paine/overridetree.cb      |  2 +-
 .../auron/variants/auron_yuna/overridetree.cb |  2 +-
 .../auron/variants/buddy/overridetree.cb      |  2 +-
 .../auron/variants/gandof/overridetree.cb     |  2 +-
 .../auron/variants/lulu/overridetree.cb       |  2 +-
 .../auron/variants/samus/overridetree.cb      |  2 +-
 src/mainboard/google/jecht/devicetree.cb      |  2 +-
 src/mainboard/google/jecht/dsdt.asl           |  4 +-
 .../hp/elitebook_820_g2/devicetree.cb         |  2 +-
 src/mainboard/hp/elitebook_820_g2/dsdt.asl    |  4 +-
 src/mainboard/intel/wtm2/devicetree.cb        |  2 +-
 src/mainboard/intel/wtm2/dsdt.asl             |  4 +-
 src/mainboard/purism/librem_bdw/devicetree.cb |  2 +-
 src/mainboard/purism/librem_bdw/dsdt.asl      |  4 +-
 .../variants/librem13v1/overridetree.cb       |  2 +-
 .../variants/librem15v2/overridetree.cb       |  2 +-
 src/soc/intel/broadwell/Kconfig               |  4 +-
 src/soc/intel/broadwell/pch/Makefile.mk       | 45 -----------------
 .../intel/wildcatpoint}/Kconfig               | 11 +++-
 .../intel/wildcatpoint/Makefile.mk            | 50 +++++++++++++++++++
 .../intel/wildcatpoint}/acpi/adsp.asl         |  0
 .../intel/wildcatpoint}/acpi/globalnvs.asl    |  0
 .../intel/wildcatpoint}/acpi/gpio.asl         |  0
 .../intel/wildcatpoint}/acpi/lpc.asl          |  0
 .../intel/wildcatpoint}/acpi/pch.asl          |  0
 .../intel/wildcatpoint}/acpi/pci_irqs.asl     |  0
 .../intel/wildcatpoint}/acpi/serialio.asl     |  0
 .../intel/wildcatpoint}/acpi/xhci.asl         |  0
 .../intel/wildcatpoint}/adsp.c                |  4 +-
 .../intel/wildcatpoint}/bootblock.c           |  0
 .../intel/wildcatpoint}/chip.h                |  2 +-
 .../intel/wildcatpoint}/early_pch.c           |  4 +-
 .../intel/wildcatpoint}/elog.c                |  0
 .../intel/wildcatpoint}/fadt.c                |  0
 .../intel/wildcatpoint}/finalize.c            |  0
 .../intel/wildcatpoint}/hda.c                 |  0
 .../intel/wildcatpoint}/lpc.c                 |  8 +--
 .../intel/wildcatpoint}/me.c                  |  4 +-
 .../intel/wildcatpoint}/me_status.c           |  0
 .../intel/wildcatpoint}/pch.c                 |  2 +-
 .../intel/wildcatpoint}/pcie.c                |  6 +--
 .../intel/wildcatpoint}/pmutil.c              |  0
 .../intel/wildcatpoint}/power_state.c         |  0
 .../intel/wildcatpoint}/ramstage.c            |  0
 .../intel/wildcatpoint}/sata.c                |  6 +--
 .../intel/wildcatpoint}/serialio.c            |  4 +-
 .../intel/wildcatpoint}/smi.c                 |  0
 .../intel/wildcatpoint}/smihandler.c          |  0
 .../intel/wildcatpoint}/usb_debug.c           |  0
 .../intel/wildcatpoint}/usb_ehci.c            |  0
 .../intel/wildcatpoint}/usb_xhci.c            |  0
 53 files changed, 104 insertions(+), 92 deletions(-)
 delete mode 100644 src/soc/intel/broadwell/pch/Makefile.mk
 rename src/{soc/intel/broadwell/pch => southbridge/intel/wildcatpoint}/Kconfig (93%)
 create mode 100644 src/southbridge/intel/wildcatpoint/Makefile.mk
 rename src/{soc/intel/broadwell/pch => southbridge/intel/wildcatpoint}/acpi/adsp.asl (100%)
 rename src/{soc/intel/broadwell/pch => southbridge/intel/wildcatpoint}/acpi/globalnvs.asl (100%)
 rename src/{soc/intel/broadwell/pch => southbridge/intel/wildcatpoint}/acpi/gpio.asl (100%)
 rename src/{soc/intel/broadwell/pch => southbridge/intel/wildcatpoint}/acpi/lpc.asl (100%)
 rename src/{soc/intel/broadwell/pch => southbridge/intel/wildcatpoint}/acpi/pch.asl (100%)
 rename src/{soc/intel/broadwell/pch => southbridge/intel/wildcatpoint}/acpi/pci_irqs.asl (100%)
 rename src/{soc/intel/broadwell/pch => southbridge/intel/wildcatpoint}/acpi/serialio.asl (100%)
 rename src/{soc/intel/broadwell/pch => southbridge/intel/wildcatpoint}/acpi/xhci.asl (100%)
 rename src/{soc/intel/broadwell/pch => southbridge/intel/wildcatpoint}/adsp.c (96%)
 rename src/{soc/intel/broadwell/pch => southbridge/intel/wildcatpoint}/bootblock.c (100%)
 rename src/{soc/intel/broadwell/pch => southbridge/intel/wildcatpoint}/chip.h (97%)
 rename src/{soc/intel/broadwell/pch => southbridge/intel/wildcatpoint}/early_pch.c (95%)
 rename src/{soc/intel/broadwell/pch => southbridge/intel/wildcatpoint}/elog.c (100%)
 rename src/{soc/intel/broadwell/pch => southbridge/intel/wildcatpoint}/fadt.c (100%)
 rename src/{soc/intel/broadwell/pch => southbridge/intel/wildcatpoint}/finalize.c (100%)
 rename src/{soc/intel/broadwell/pch => southbridge/intel/wildcatpoint}/hda.c (100%)
 rename src/{soc/intel/broadwell/pch => southbridge/intel/wildcatpoint}/lpc.c (98%)
 rename src/{soc/intel/broadwell/pch => southbridge/intel/wildcatpoint}/me.c (99%)
 rename src/{soc/intel/broadwell/pch => southbridge/intel/wildcatpoint}/me_status.c (100%)
 rename src/{soc/intel/broadwell/pch => southbridge/intel/wildcatpoint}/pch.c (98%)
 rename src/{soc/intel/broadwell/pch => southbridge/intel/wildcatpoint}/pcie.c (98%)
 rename src/{soc/intel/broadwell/pch => southbridge/intel/wildcatpoint}/pmutil.c (100%)
 rename src/{soc/intel/broadwell/pch => southbridge/intel/wildcatpoint}/power_state.c (100%)
 rename src/{soc/intel/broadwell/pch => southbridge/intel/wildcatpoint}/ramstage.c (100%)
 rename src/{soc/intel/broadwell/pch => southbridge/intel/wildcatpoint}/sata.c (97%)
 rename src/{soc/intel/broadwell/pch => southbridge/intel/wildcatpoint}/serialio.c (98%)
 rename src/{soc/intel/broadwell/pch => southbridge/intel/wildcatpoint}/smi.c (100%)
 rename src/{soc/intel/broadwell/pch => southbridge/intel/wildcatpoint}/smihandler.c (100%)
 rename src/{soc/intel/broadwell/pch => southbridge/intel/wildcatpoint}/usb_debug.c (100%)
 rename src/{soc/intel/broadwell/pch => southbridge/intel/wildcatpoint}/usb_ehci.c (100%)
 rename src/{soc/intel/broadwell/pch => southbridge/intel/wildcatpoint}/usb_xhci.c (100%)

diff --git a/src/mainboard/google/auron/devicetree.cb b/src/mainboard/google/auron/devicetree.cb
index 6d42e1f810..ff179c2ceb 100644
--- a/src/mainboard/google/auron/devicetree.cb
+++ b/src/mainboard/google/auron/devicetree.cb
@@ -26,7 +26,7 @@ chip soc/intel/broadwell
 		device pci 02.0 on  end # vga controller
 		device pci 03.0 on  end # mini-hd audio
 
-		chip soc/intel/broadwell/pch
+		chip southbridge/intel/wildcatpoint
 			# EC range is 0x800-0x9ff
 			register "gen1_dec" = "0x00fc0801"
 			register "gen2_dec" = "0x00fc0901"
diff --git a/src/mainboard/google/auron/dsdt.asl b/src/mainboard/google/auron/dsdt.asl
index ba7f1e4324..c6453e9a24 100644
--- a/src/mainboard/google/auron/dsdt.asl
+++ b/src/mainboard/google/auron/dsdt.asl
@@ -17,7 +17,7 @@ DefinitionBlock(
 	#include "acpi/thermal.asl"
 
 	// global NVS and variables
-	#include <soc/intel/broadwell/pch/acpi/globalnvs.asl>
+	#include <southbridge/intel/wildcatpoint/acpi/globalnvs.asl>
 
 	// CPU
 	#include <cpu/intel/common/acpi/cpu.asl>
@@ -26,7 +26,7 @@ DefinitionBlock(
 		Device (PCI0)
 		{
 			#include <northbridge/intel/haswell/acpi/hostbridge.asl>
-			#include <soc/intel/broadwell/pch/acpi/pch.asl>
+			#include <southbridge/intel/wildcatpoint/acpi/pch.asl>
 			#include <drivers/intel/gma/acpi/default_brightness_levels.asl>
 		}
 	}
diff --git a/src/mainboard/google/auron/variants/auron_paine/overridetree.cb b/src/mainboard/google/auron/variants/auron_paine/overridetree.cb
index 62e42b1718..b968ddb6bd 100644
--- a/src/mainboard/google/auron/variants/auron_paine/overridetree.cb
+++ b/src/mainboard/google/auron/variants/auron_paine/overridetree.cb
@@ -10,7 +10,7 @@ chip soc/intel/broadwell
 	}"
 
 	device domain 0 on
-		chip soc/intel/broadwell/pch
+		chip southbridge/intel/wildcatpoint
 			# DTLE DATA / EDGE values
 			register "sata_port0_gen3_dtle" = "0x5"
 			register "sata_port1_gen3_dtle" = "0x5"
diff --git a/src/mainboard/google/auron/variants/auron_yuna/overridetree.cb b/src/mainboard/google/auron/variants/auron_yuna/overridetree.cb
index 174463d0b7..c9d9078c46 100644
--- a/src/mainboard/google/auron/variants/auron_yuna/overridetree.cb
+++ b/src/mainboard/google/auron/variants/auron_yuna/overridetree.cb
@@ -10,7 +10,7 @@ chip soc/intel/broadwell
 	}"
 
 	device domain 0 on
-		chip soc/intel/broadwell/pch
+		chip southbridge/intel/wildcatpoint
 			# DTLE DATA / EDGE values
 			register "sata_port0_gen3_dtle" = "0x7"
 			register "sata_port1_gen3_dtle" = "0x5"
diff --git a/src/mainboard/google/auron/variants/buddy/overridetree.cb b/src/mainboard/google/auron/variants/buddy/overridetree.cb
index d1e217b8aa..e1bf686cc8 100644
--- a/src/mainboard/google/auron/variants/buddy/overridetree.cb
+++ b/src/mainboard/google/auron/variants/buddy/overridetree.cb
@@ -18,7 +18,7 @@ chip soc/intel/broadwell
 	end
 
 	device domain 0 on
-		chip soc/intel/broadwell/pch
+		chip southbridge/intel/wildcatpoint
 			register "sata_devslp_disable" = "0x1"
 
 			register "sio_i2c0_voltage" = "1" # 1.8V
diff --git a/src/mainboard/google/auron/variants/gandof/overridetree.cb b/src/mainboard/google/auron/variants/gandof/overridetree.cb
index ca5d616659..ddb7a35dfa 100644
--- a/src/mainboard/google/auron/variants/gandof/overridetree.cb
+++ b/src/mainboard/google/auron/variants/gandof/overridetree.cb
@@ -10,7 +10,7 @@ chip soc/intel/broadwell
 	}"
 
 	device domain 0 on
-		chip soc/intel/broadwell/pch
+		chip southbridge/intel/wildcatpoint
 			# DTLE DATA / EDGE values
 			register "sata_port0_gen3_dtle" = "0x5"
 			register "sata_port1_gen3_dtle" = "0x5"
diff --git a/src/mainboard/google/auron/variants/lulu/overridetree.cb b/src/mainboard/google/auron/variants/lulu/overridetree.cb
index 62e42b1718..b968ddb6bd 100644
--- a/src/mainboard/google/auron/variants/lulu/overridetree.cb
+++ b/src/mainboard/google/auron/variants/lulu/overridetree.cb
@@ -10,7 +10,7 @@ chip soc/intel/broadwell
 	}"
 
 	device domain 0 on
-		chip soc/intel/broadwell/pch
+		chip southbridge/intel/wildcatpoint
 			# DTLE DATA / EDGE values
 			register "sata_port0_gen3_dtle" = "0x5"
 			register "sata_port1_gen3_dtle" = "0x5"
diff --git a/src/mainboard/google/auron/variants/samus/overridetree.cb b/src/mainboard/google/auron/variants/samus/overridetree.cb
index b0b8a603f6..b9a6431d0e 100644
--- a/src/mainboard/google/auron/variants/samus/overridetree.cb
+++ b/src/mainboard/google/auron/variants/samus/overridetree.cb
@@ -26,7 +26,7 @@ chip soc/intel/broadwell
 	end
 
 	device domain 0 on
-		chip soc/intel/broadwell/pch
+		chip southbridge/intel/wildcatpoint
 			register "sata_port0_gen3_tx" = "0x72"
 
 			# Set I2C0 to 1.8V
diff --git a/src/mainboard/google/jecht/devicetree.cb b/src/mainboard/google/jecht/devicetree.cb
index cdde70f503..2f8ccdc365 100644
--- a/src/mainboard/google/jecht/devicetree.cb
+++ b/src/mainboard/google/jecht/devicetree.cb
@@ -21,7 +21,7 @@ chip soc/intel/broadwell
 		device pci 02.0 on end # vga controller
 		device pci 03.0 on end # mini-hd audio
 
-		chip soc/intel/broadwell/pch
+		chip southbridge/intel/wildcatpoint
 			# SuperIO range is 0x700-0x73f
 			register "gen2_dec" = "0x003c0701"
 
diff --git a/src/mainboard/google/jecht/dsdt.asl b/src/mainboard/google/jecht/dsdt.asl
index 1aeb08cdce..7cc8c7b9f4 100644
--- a/src/mainboard/google/jecht/dsdt.asl
+++ b/src/mainboard/google/jecht/dsdt.asl
@@ -18,7 +18,7 @@ DefinitionBlock(
 	#include <variant/acpi/thermal.asl>
 
 	// global NVS and variables
-	#include <soc/intel/broadwell/pch/acpi/globalnvs.asl>
+	#include <southbridge/intel/wildcatpoint/acpi/globalnvs.asl>
 	#include <soc/intel/broadwell/acpi/device_nvs.asl>
 
 	// CPU
@@ -28,7 +28,7 @@ DefinitionBlock(
 		Device (PCI0)
 		{
 			#include <northbridge/intel/haswell/acpi/hostbridge.asl>
-			#include <soc/intel/broadwell/pch/acpi/pch.asl>
+			#include <southbridge/intel/wildcatpoint/acpi/pch.asl>
 		}
 	}
 
diff --git a/src/mainboard/hp/elitebook_820_g2/devicetree.cb b/src/mainboard/hp/elitebook_820_g2/devicetree.cb
index 626e6d56a7..63df5d16d9 100644
--- a/src/mainboard/hp/elitebook_820_g2/devicetree.cb
+++ b/src/mainboard/hp/elitebook_820_g2/devicetree.cb
@@ -24,7 +24,7 @@ chip soc/intel/broadwell
 		end
 		device pci 03.0 on end # Mini-HD audio
 
-		chip soc/intel/broadwell/pch # Wildcat Point PCH
+		chip southbridge/intel/wildcatpoint # Wildcat Point PCH
 			device pci 13.0 off end # Smart Sound Audio DSP
 			device pci 14.0 on  end # xHCI Controller
 			device pci 15.0 off end # Serial I/O DMA
diff --git a/src/mainboard/hp/elitebook_820_g2/dsdt.asl b/src/mainboard/hp/elitebook_820_g2/dsdt.asl
index 6d7555d02e..6b1b4267d5 100644
--- a/src/mainboard/hp/elitebook_820_g2/dsdt.asl
+++ b/src/mainboard/hp/elitebook_820_g2/dsdt.asl
@@ -17,7 +17,7 @@ DefinitionBlock(
 	#include "acpi/platform.asl"
 	#include <soc/intel/common/acpi/acpi_wake_source.asl>
 
-	#include <soc/intel/broadwell/pch/acpi/globalnvs.asl>
+	#include <southbridge/intel/wildcatpoint/acpi/globalnvs.asl>
 	#include <soc/intel/broadwell/acpi/device_nvs.asl>
 	#include <cpu/intel/common/acpi/cpu.asl>
 	#include <southbridge/intel/common/acpi/sleepstates.asl>
@@ -25,7 +25,7 @@ DefinitionBlock(
 	Device (\_SB.PCI0)
 	{
 		#include <northbridge/intel/haswell/acpi/hostbridge.asl>
-		#include <soc/intel/broadwell/pch/acpi/pch.asl>
+		#include <southbridge/intel/wildcatpoint/acpi/pch.asl>
 		#include <drivers/intel/gma/acpi/default_brightness_levels.asl>
 	}
 }
diff --git a/src/mainboard/intel/wtm2/devicetree.cb b/src/mainboard/intel/wtm2/devicetree.cb
index 9e1e8a03cb..0b8bd36085 100644
--- a/src/mainboard/intel/wtm2/devicetree.cb
+++ b/src/mainboard/intel/wtm2/devicetree.cb
@@ -18,7 +18,7 @@ chip soc/intel/broadwell
 		device pci 02.0 on  end	# vga controller
 		device pci 03.0 on  end	# mini-hd audio
 
-		chip soc/intel/broadwell/pch
+		chip southbridge/intel/wildcatpoint
 			register "alt_gp_smi_en" = "0x0000"
 			register "gpe0_en_1" = "0x00000400"
 			register "gpe0_en_2" = "0x00000000"
diff --git a/src/mainboard/intel/wtm2/dsdt.asl b/src/mainboard/intel/wtm2/dsdt.asl
index 9e06eb7202..26ed596067 100644
--- a/src/mainboard/intel/wtm2/dsdt.asl
+++ b/src/mainboard/intel/wtm2/dsdt.asl
@@ -18,7 +18,7 @@ DefinitionBlock(
 	#include "acpi/platform.asl"
 
 	// global NVS and variables
-	#include <soc/intel/broadwell/pch/acpi/globalnvs.asl>
+	#include <southbridge/intel/wildcatpoint/acpi/globalnvs.asl>
 	#include <soc/intel/broadwell/acpi/device_nvs.asl>
 
 	// CPU
@@ -28,7 +28,7 @@ DefinitionBlock(
 		Device (PCI0)
 		{
 			#include <northbridge/intel/haswell/acpi/hostbridge.asl>
-			#include <soc/intel/broadwell/pch/acpi/pch.asl>
+			#include <southbridge/intel/wildcatpoint/acpi/pch.asl>
 		}
 	}
 
diff --git a/src/mainboard/purism/librem_bdw/devicetree.cb b/src/mainboard/purism/librem_bdw/devicetree.cb
index f663afdd4c..934fd7eb8b 100644
--- a/src/mainboard/purism/librem_bdw/devicetree.cb
+++ b/src/mainboard/purism/librem_bdw/devicetree.cb
@@ -29,7 +29,7 @@ chip soc/intel/broadwell
 		device pci 02.0 on  end # vga controller
 		device pci 03.0 on  end # mini-hd audio
 
-		chip soc/intel/broadwell/pch
+		chip southbridge/intel/wildcatpoint
 			# EC host command ranges are in 0x380-0x383 & 0x80-0x8f
 			register "gen1_dec" = "0x00000381"
 
diff --git a/src/mainboard/purism/librem_bdw/dsdt.asl b/src/mainboard/purism/librem_bdw/dsdt.asl
index a631e5a5a5..2e8b5c57e2 100644
--- a/src/mainboard/purism/librem_bdw/dsdt.asl
+++ b/src/mainboard/purism/librem_bdw/dsdt.asl
@@ -12,14 +12,14 @@ DefinitionBlock(
 {
 	#include <acpi/dsdt_top.asl>
 	#include <soc/intel/broadwell/acpi/platform.asl>
-	#include <soc/intel/broadwell/pch/acpi/globalnvs.asl>
+	#include <southbridge/intel/wildcatpoint/acpi/globalnvs.asl>
 	#include <cpu/intel/common/acpi/cpu.asl>
 
 	Scope (\_SB) {
 		Device (PCI0)
 		{
 			#include <northbridge/intel/haswell/acpi/hostbridge.asl>
-			#include <soc/intel/broadwell/pch/acpi/pch.asl>
+			#include <southbridge/intel/wildcatpoint/acpi/pch.asl>
 			#include <drivers/intel/gma/acpi/default_brightness_levels.asl>
 		}
 	}
diff --git a/src/mainboard/purism/librem_bdw/variants/librem13v1/overridetree.cb b/src/mainboard/purism/librem_bdw/variants/librem13v1/overridetree.cb
index 256077cbd9..9d47ae8055 100644
--- a/src/mainboard/purism/librem_bdw/variants/librem13v1/overridetree.cb
+++ b/src/mainboard/purism/librem_bdw/variants/librem13v1/overridetree.cb
@@ -1,7 +1,7 @@
 chip soc/intel/broadwell
 
 	device domain 0 on
-		chip soc/intel/broadwell/pch
+		chip southbridge/intel/wildcatpoint
 			# Port 0 is HDD
 			# Port 3 is M.2 NGFF
 			register "sata_port_map" = "0x9"
diff --git a/src/mainboard/purism/librem_bdw/variants/librem15v2/overridetree.cb b/src/mainboard/purism/librem_bdw/variants/librem15v2/overridetree.cb
index 76737cc5e2..01d317e6b5 100644
--- a/src/mainboard/purism/librem_bdw/variants/librem15v2/overridetree.cb
+++ b/src/mainboard/purism/librem_bdw/variants/librem15v2/overridetree.cb
@@ -3,7 +3,7 @@ chip soc/intel/broadwell
 	register "dq_pins_interleaved" = "true"
 
 	device domain 0 on
-		chip soc/intel/broadwell/pch
+		chip southbridge/intel/wildcatpoint
 			# Port 0 is HDD
 			# Port 1 is M.2 NGFF
 			register "sata_port_map" = "0x3"
diff --git a/src/soc/intel/broadwell/Kconfig b/src/soc/intel/broadwell/Kconfig
index 74650ff212..e20ac3f1d7 100644
--- a/src/soc/intel/broadwell/Kconfig
+++ b/src/soc/intel/broadwell/Kconfig
@@ -10,7 +10,7 @@ config SOC_INTEL_BROADWELL
 	select MRC_SETTINGS_PROTECT
 	select REG_SCRIPT
 	select TCO_SPACE_NOT_YET_SPLIT
-	select INTEL_LYNXPOINT_LP
+	select SOUTHBRIDGE_INTEL_WILDCATPOINT
 	help
 	  Intel Broadwell and Haswell ULT support.
 
@@ -117,6 +117,4 @@ config REFCODE_BLOB_FILE
 
 endif # HAVE_REFCODE_BLOB
 
-source "src/soc/intel/broadwell/pch/Kconfig"
-
 endif
diff --git a/src/soc/intel/broadwell/pch/Makefile.mk b/src/soc/intel/broadwell/pch/Makefile.mk
deleted file mode 100644
index be2f4a4292..0000000000
--- a/src/soc/intel/broadwell/pch/Makefile.mk
+++ /dev/null
@@ -1,45 +0,0 @@
-## SPDX-License-Identifier: GPL-2.0-only
-bootblock-y += bootblock.c
-
-ramstage-y += adsp.c
-romstage-y += early_pch.c
-ramstage-$(CONFIG_ELOG) += elog.c
-ramstage-y += finalize.c
-ramstage-y += ../../../../southbridge/intel/lynxpoint/lp_gpio.c
-romstage-y += ../../../../southbridge/intel/lynxpoint/lp_gpio.c
-verstage-y += ../../../../southbridge/intel/lynxpoint/lp_gpio.c
-smm-y      += ../../../../southbridge/intel/lynxpoint/lp_gpio.c
-ramstage-y += hda.c
-ramstage-y += ../../../../southbridge/intel/lynxpoint/hda_verb.c
-ramstage-y += ../../../../southbridge/intel/lynxpoint/iobp.c
-romstage-y += ../../../../southbridge/intel/lynxpoint/iobp.c
-ramstage-y += fadt.c
-ramstage-y += lpc.c
-ramstage-y += me.c
-ramstage-y += me_status.c
-romstage-y += me_status.c
-ramstage-y += pch.c
-romstage-y += pch.c
-ramstage-y += pcie.c
-ramstage-y += pmutil.c
-romstage-y += pmutil.c
-smm-y      += pmutil.c
-verstage-y += pmutil.c
-romstage-y += power_state.c
-ramstage-y += ramstage.c
-ramstage-y += sata.c
-ramstage-y += serialio.c
-ramstage-y += ../../../../southbridge/intel/lynxpoint/smbus.c
-ramstage-y += smi.c
-smm-y      += smihandler.c
-bootblock-y += usb_debug.c
-romstage-y += usb_debug.c
-ramstage-y += usb_debug.c
-ramstage-y += usb_ehci.c
-ramstage-y += usb_xhci.c
-smm-y      += usb_xhci.c
-
-bootblock-$(CONFIG_SERIALIO_UART_CONSOLE) += ../../../../southbridge/intel/lynxpoint/iobp.c
-bootblock-$(CONFIG_SERIALIO_UART_CONSOLE) += ../../../../southbridge/intel/lynxpoint/uart_init.c
-all-$(CONFIG_SERIALIO_UART_CONSOLE) += ../../../../southbridge/intel/lynxpoint/uart.c
-smm-$(CONFIG_SERIALIO_UART_CONSOLE) += ../../../../southbridge/intel/lynxpoint/uart.c
diff --git a/src/soc/intel/broadwell/pch/Kconfig b/src/southbridge/intel/wildcatpoint/Kconfig
similarity index 93%
rename from src/soc/intel/broadwell/pch/Kconfig
rename to src/southbridge/intel/wildcatpoint/Kconfig
index a671207b67..424b91d832 100644
--- a/src/soc/intel/broadwell/pch/Kconfig
+++ b/src/southbridge/intel/wildcatpoint/Kconfig
@@ -1,6 +1,6 @@
 ## SPDX-License-Identifier: GPL-2.0-only
 
-config INTEL_LYNXPOINT_LP
+config SOUTHBRIDGE_INTEL_WILDCATPOINT
 	bool
 	select ACPI_COMMON_MADT_IOAPIC
 	select ACPI_COMMON_MADT_LAPIC
@@ -14,6 +14,7 @@ config INTEL_LYNXPOINT_LP
 	select HAVE_SMI_HANDLER
 	select HAVE_USBDEBUG
 	select INTEL_DESCRIPTOR_MODE_CAPABLE
+	select INTEL_LYNXPOINT_LP
 	select RTC
 	select SOUTHBRIDGE_INTEL_COMMON_EARLY_SMBUS
 	select SOUTHBRIDGE_INTEL_COMMON_RESET
@@ -23,6 +24,12 @@ config INTEL_LYNXPOINT_LP
 	select SPI_FLASH
 	select TCO_SPACE_NOT_YET_SPLIT
 
+if SOUTHBRIDGE_INTEL_WILDCATPOINT
+
+# Placeholder
+config INTEL_LYNXPOINT_LP
+	bool
+
 config EHCI_BAR
 	hex
 	default 0xd8000000
@@ -72,3 +79,5 @@ config DISABLE_ME_PCI
 	  Disable and hide the ME PCI interface during finalize stage of boot.
 	  This will prevent the OS (and userspace apps) from interacting with
 	  the ME via the PCI interface after boot.
+
+endif
diff --git a/src/southbridge/intel/wildcatpoint/Makefile.mk b/src/southbridge/intel/wildcatpoint/Makefile.mk
new file mode 100644
index 0000000000..ee631d44cd
--- /dev/null
+++ b/src/southbridge/intel/wildcatpoint/Makefile.mk
@@ -0,0 +1,50 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
+ifeq ($(CONFIG_SOUTHBRIDGE_INTEL_WILDCATPOINT),y)
+
+bootblock-y += bootblock.c
+
+ramstage-y += adsp.c
+romstage-y += early_pch.c
+ramstage-$(CONFIG_ELOG) += elog.c
+ramstage-y += finalize.c
+ramstage-y += ../lynxpoint/lp_gpio.c
+romstage-y += ../lynxpoint/lp_gpio.c
+verstage-y += ../lynxpoint/lp_gpio.c
+smm-y      += ../lynxpoint/lp_gpio.c
+ramstage-y += hda.c
+ramstage-y += ../lynxpoint/hda_verb.c
+ramstage-y += ../lynxpoint/iobp.c
+romstage-y += ../lynxpoint/iobp.c
+ramstage-y += fadt.c
+ramstage-y += lpc.c
+ramstage-y += me.c
+ramstage-y += me_status.c
+romstage-y += me_status.c
+ramstage-y += pch.c
+romstage-y += pch.c
+ramstage-y += pcie.c
+ramstage-y += pmutil.c
+romstage-y += pmutil.c
+smm-y      += pmutil.c
+verstage-y += pmutil.c
+romstage-y += power_state.c
+ramstage-y += ramstage.c
+ramstage-y += sata.c
+ramstage-y += serialio.c
+ramstage-y += ../lynxpoint/smbus.c
+ramstage-y += smi.c
+smm-y      += smihandler.c
+bootblock-y += usb_debug.c
+romstage-y += usb_debug.c
+ramstage-y += usb_debug.c
+ramstage-y += usb_ehci.c
+ramstage-y += usb_xhci.c
+smm-y      += usb_xhci.c
+
+bootblock-$(CONFIG_SERIALIO_UART_CONSOLE) += ../lynxpoint/iobp.c
+bootblock-$(CONFIG_SERIALIO_UART_CONSOLE) += ../lynxpoint/uart_init.c
+all-$(CONFIG_SERIALIO_UART_CONSOLE) += ../lynxpoint/uart.c
+smm-$(CONFIG_SERIALIO_UART_CONSOLE) += ../lynxpoint/uart.c
+
+endif
diff --git a/src/soc/intel/broadwell/pch/acpi/adsp.asl b/src/southbridge/intel/wildcatpoint/acpi/adsp.asl
similarity index 100%
rename from src/soc/intel/broadwell/pch/acpi/adsp.asl
rename to src/southbridge/intel/wildcatpoint/acpi/adsp.asl
diff --git a/src/soc/intel/broadwell/pch/acpi/globalnvs.asl b/src/southbridge/intel/wildcatpoint/acpi/globalnvs.asl
similarity index 100%
rename from src/soc/intel/broadwell/pch/acpi/globalnvs.asl
rename to src/southbridge/intel/wildcatpoint/acpi/globalnvs.asl
diff --git a/src/soc/intel/broadwell/pch/acpi/gpio.asl b/src/southbridge/intel/wildcatpoint/acpi/gpio.asl
similarity index 100%
rename from src/soc/intel/broadwell/pch/acpi/gpio.asl
rename to src/southbridge/intel/wildcatpoint/acpi/gpio.asl
diff --git a/src/soc/intel/broadwell/pch/acpi/lpc.asl b/src/southbridge/intel/wildcatpoint/acpi/lpc.asl
similarity index 100%
rename from src/soc/intel/broadwell/pch/acpi/lpc.asl
rename to src/southbridge/intel/wildcatpoint/acpi/lpc.asl
diff --git a/src/soc/intel/broadwell/pch/acpi/pch.asl b/src/southbridge/intel/wildcatpoint/acpi/pch.asl
similarity index 100%
rename from src/soc/intel/broadwell/pch/acpi/pch.asl
rename to src/southbridge/intel/wildcatpoint/acpi/pch.asl
diff --git a/src/soc/intel/broadwell/pch/acpi/pci_irqs.asl b/src/southbridge/intel/wildcatpoint/acpi/pci_irqs.asl
similarity index 100%
rename from src/soc/intel/broadwell/pch/acpi/pci_irqs.asl
rename to src/southbridge/intel/wildcatpoint/acpi/pci_irqs.asl
diff --git a/src/soc/intel/broadwell/pch/acpi/serialio.asl b/src/southbridge/intel/wildcatpoint/acpi/serialio.asl
similarity index 100%
rename from src/soc/intel/broadwell/pch/acpi/serialio.asl
rename to src/southbridge/intel/wildcatpoint/acpi/serialio.asl
diff --git a/src/soc/intel/broadwell/pch/acpi/xhci.asl b/src/southbridge/intel/wildcatpoint/acpi/xhci.asl
similarity index 100%
rename from src/soc/intel/broadwell/pch/acpi/xhci.asl
rename to src/southbridge/intel/wildcatpoint/acpi/xhci.asl
diff --git a/src/soc/intel/broadwell/pch/adsp.c b/src/southbridge/intel/wildcatpoint/adsp.c
similarity index 96%
rename from src/soc/intel/broadwell/pch/adsp.c
rename to src/southbridge/intel/wildcatpoint/adsp.c
index 05b1e60af2..c56f9cc584 100644
--- a/src/soc/intel/broadwell/pch/adsp.c
+++ b/src/southbridge/intel/wildcatpoint/adsp.c
@@ -11,13 +11,13 @@
 #include <soc/device_nvs.h>
 #include <soc/pch.h>
 #include <soc/rcba.h>
-#include <soc/intel/broadwell/pch/chip.h>
+#include <southbridge/intel/wildcatpoint/chip.h>
 #include <southbridge/intel/lynxpoint/iobp.h>
 #include <stdbool.h>
 
 static void adsp_init(struct device *dev)
 {
-	const struct soc_intel_broadwell_pch_config *config = config_of(dev);
+	const struct southbridge_intel_wildcatpoint_config *config = config_of(dev);
 	struct resource *bar0, *bar1;
 	u32 tmp32;
 
diff --git a/src/soc/intel/broadwell/pch/bootblock.c b/src/southbridge/intel/wildcatpoint/bootblock.c
similarity index 100%
rename from src/soc/intel/broadwell/pch/bootblock.c
rename to src/southbridge/intel/wildcatpoint/bootblock.c
diff --git a/src/soc/intel/broadwell/pch/chip.h b/src/southbridge/intel/wildcatpoint/chip.h
similarity index 97%
rename from src/soc/intel/broadwell/pch/chip.h
rename to src/southbridge/intel/wildcatpoint/chip.h
index 84ad8fe820..dd31645849 100644
--- a/src/soc/intel/broadwell/pch/chip.h
+++ b/src/southbridge/intel/wildcatpoint/chip.h
@@ -5,7 +5,7 @@
 
 #include <types.h>
 
-struct soc_intel_broadwell_pch_config {
+struct southbridge_intel_wildcatpoint_config {
 	/* GPE configuration */
 	uint32_t gpe0_en_1;
 	uint32_t gpe0_en_2;
diff --git a/src/soc/intel/broadwell/pch/early_pch.c b/src/southbridge/intel/wildcatpoint/early_pch.c
similarity index 95%
rename from src/soc/intel/broadwell/pch/early_pch.c
rename to src/southbridge/intel/wildcatpoint/early_pch.c
index cb45971772..adb65e6145 100644
--- a/src/soc/intel/broadwell/pch/early_pch.c
+++ b/src/southbridge/intel/wildcatpoint/early_pch.c
@@ -11,7 +11,7 @@
 #include <soc/pm.h>
 #include <soc/rcba.h>
 #include <soc/romstage.h>
-#include <soc/intel/broadwell/pch/chip.h>
+#include <southbridge/intel/wildcatpoint/chip.h>
 
 static void pch_route_interrupts(void)
 {
@@ -56,7 +56,7 @@ static void pch_enable_lpc(void)
 	if (!dev || !dev->chip_info)
 		return;
 
-	const struct soc_intel_broadwell_pch_config *config = dev->chip_info;
+	const struct southbridge_intel_wildcatpoint_config *config = dev->chip_info;
 
 	pci_write_config32(PCH_DEV_LPC, LPC_GEN1_DEC, config->gen1_dec);
 	pci_write_config32(PCH_DEV_LPC, LPC_GEN2_DEC, config->gen2_dec);
diff --git a/src/soc/intel/broadwell/pch/elog.c b/src/southbridge/intel/wildcatpoint/elog.c
similarity index 100%
rename from src/soc/intel/broadwell/pch/elog.c
rename to src/southbridge/intel/wildcatpoint/elog.c
diff --git a/src/soc/intel/broadwell/pch/fadt.c b/src/southbridge/intel/wildcatpoint/fadt.c
similarity index 100%
rename from src/soc/intel/broadwell/pch/fadt.c
rename to src/southbridge/intel/wildcatpoint/fadt.c
diff --git a/src/soc/intel/broadwell/pch/finalize.c b/src/southbridge/intel/wildcatpoint/finalize.c
similarity index 100%
rename from src/soc/intel/broadwell/pch/finalize.c
rename to src/southbridge/intel/wildcatpoint/finalize.c
diff --git a/src/soc/intel/broadwell/pch/hda.c b/src/southbridge/intel/wildcatpoint/hda.c
similarity index 100%
rename from src/soc/intel/broadwell/pch/hda.c
rename to src/southbridge/intel/wildcatpoint/hda.c
diff --git a/src/soc/intel/broadwell/pch/lpc.c b/src/southbridge/intel/wildcatpoint/lpc.c
similarity index 98%
rename from src/soc/intel/broadwell/pch/lpc.c
rename to src/southbridge/intel/wildcatpoint/lpc.c
index 49a36b148a..9dd2350c93 100644
--- a/src/soc/intel/broadwell/pch/lpc.c
+++ b/src/southbridge/intel/wildcatpoint/lpc.c
@@ -17,7 +17,7 @@
 #include <soc/pci_devs.h>
 #include <soc/pm.h>
 #include <soc/rcba.h>
-#include <soc/intel/broadwell/pch/chip.h>
+#include <southbridge/intel/wildcatpoint/chip.h>
 #include <acpi/acpigen.h>
 #include <southbridge/intel/common/rtc.h>
 #include <southbridge/intel/lynxpoint/iobp.h>
@@ -162,7 +162,7 @@ static void pch_power_options(struct device *dev)
 	printk(BIOS_INFO, "Set power %s after power failure.\n", state);
 
 	if (dev->chip_info) {
-		const struct soc_intel_broadwell_pch_config *config = dev->chip_info;
+		const struct southbridge_intel_wildcatpoint_config *config = dev->chip_info;
 
 		/* GPE setup based on device tree configuration */
 		enable_all_gpe(config->gpe0_en_1, config->gpe0_en_2,
@@ -326,7 +326,7 @@ static void pch_enable_mphy(void)
 
 static void pch_init_deep_sx(struct device *dev)
 {
-	const struct soc_intel_broadwell_pch_config *config = dev->chip_info;
+	const struct southbridge_intel_wildcatpoint_config *config = dev->chip_info;
 
 	if (!config)
 		return;
@@ -575,7 +575,7 @@ static void pch_lpc_add_io_resources(struct device *dev)
 
 	/* LPC Generic IO Decode range. */
 	if (dev->chip_info) {
-		const struct soc_intel_broadwell_pch_config *config = dev->chip_info;
+		const struct southbridge_intel_wildcatpoint_config *config = dev->chip_info;
 		pch_lpc_add_gen_io_resources(dev, config->gen1_dec, LPC_GEN1_DEC);
 		pch_lpc_add_gen_io_resources(dev, config->gen2_dec, LPC_GEN2_DEC);
 		pch_lpc_add_gen_io_resources(dev, config->gen3_dec, LPC_GEN3_DEC);
diff --git a/src/soc/intel/broadwell/pch/me.c b/src/southbridge/intel/wildcatpoint/me.c
similarity index 99%
rename from src/soc/intel/broadwell/pch/me.c
rename to src/southbridge/intel/wildcatpoint/me.c
index 5756bdb00d..33bf915fae 100644
--- a/src/soc/intel/broadwell/pch/me.c
+++ b/src/southbridge/intel/wildcatpoint/me.c
@@ -25,7 +25,7 @@
 #include <soc/pch.h>
 #include <soc/pci_devs.h>
 #include <soc/rcba.h>
-#include <soc/intel/broadwell/pch/chip.h>
+#include <southbridge/intel/wildcatpoint/chip.h>
 
 #include <vendorcode/google/chromeos/chromeos.h>
 
@@ -948,7 +948,7 @@ static int intel_me_read_mbp(me_bios_payload *mbp_data, struct device *dev)
 /* Check whether ME is present and do basic init */
 static void intel_me_init(struct device *dev)
 {
-	const struct soc_intel_broadwell_pch_config *config = config_of(dev);
+	const struct southbridge_intel_wildcatpoint_config *config = config_of(dev);
 	me_bios_path path = intel_me_path(dev);
 	me_bios_payload mbp_data;
 	int mbp_ret;
diff --git a/src/soc/intel/broadwell/pch/me_status.c b/src/southbridge/intel/wildcatpoint/me_status.c
similarity index 100%
rename from src/soc/intel/broadwell/pch/me_status.c
rename to src/southbridge/intel/wildcatpoint/me_status.c
diff --git a/src/soc/intel/broadwell/pch/pch.c b/src/southbridge/intel/wildcatpoint/pch.c
similarity index 98%
rename from src/soc/intel/broadwell/pch/pch.c
rename to src/southbridge/intel/wildcatpoint/pch.c
index fa03d7359a..3714a7d8a7 100644
--- a/src/soc/intel/broadwell/pch/pch.c
+++ b/src/southbridge/intel/wildcatpoint/pch.c
@@ -196,7 +196,7 @@ static void broadwell_pch_enable_dev(struct device *dev)
 	}
 }
 
-struct chip_operations soc_intel_broadwell_pch_ops = {
+struct chip_operations southbridge_intel_wildcatpoint_ops = {
 	.name = "Intel Broadwell PCH",
 	.enable_dev = &broadwell_pch_enable_dev,
 };
diff --git a/src/soc/intel/broadwell/pch/pcie.c b/src/southbridge/intel/wildcatpoint/pcie.c
similarity index 98%
rename from src/soc/intel/broadwell/pch/pcie.c
rename to src/southbridge/intel/wildcatpoint/pcie.c
index 4847da6788..9262d3c628 100644
--- a/src/soc/intel/broadwell/pch/pcie.c
+++ b/src/southbridge/intel/wildcatpoint/pcie.c
@@ -12,7 +12,7 @@
 #include <soc/pch.h>
 #include <soc/pci_devs.h>
 #include <soc/rcba.h>
-#include <soc/intel/broadwell/pch/chip.h>
+#include <southbridge/intel/wildcatpoint/chip.h>
 #include <southbridge/intel/lynxpoint/iobp.h>
 #include <southbridge/intel/lynxpoint/lp_gpio.h>
 #include <types.h>
@@ -121,7 +121,7 @@ static void root_port_init_config(struct device *dev)
 		root_port_config_update_gbe_port();
 
 		pci_or_config8(dev, 0xe2, 3 << 4);
-		const struct soc_intel_broadwell_pch_config *config = config_of(dev);
+		const struct southbridge_intel_wildcatpoint_config *config = config_of(dev);
 		rpc.coalesce = config->pcie_port_coalesce;
 	}
 
@@ -435,7 +435,7 @@ static void pcie_add_0x0202000_iobp(u32 reg)
 
 static void pch_pcie_early(struct device *dev)
 {
-	const struct soc_intel_broadwell_pch_config *config = config_of(dev);
+	const struct southbridge_intel_wildcatpoint_config *config = config_of(dev);
 	int do_aspm = 0;
 	int rp = root_port_number(dev);
 
diff --git a/src/soc/intel/broadwell/pch/pmutil.c b/src/southbridge/intel/wildcatpoint/pmutil.c
similarity index 100%
rename from src/soc/intel/broadwell/pch/pmutil.c
rename to src/southbridge/intel/wildcatpoint/pmutil.c
diff --git a/src/soc/intel/broadwell/pch/power_state.c b/src/southbridge/intel/wildcatpoint/power_state.c
similarity index 100%
rename from src/soc/intel/broadwell/pch/power_state.c
rename to src/southbridge/intel/wildcatpoint/power_state.c
diff --git a/src/soc/intel/broadwell/pch/ramstage.c b/src/southbridge/intel/wildcatpoint/ramstage.c
similarity index 100%
rename from src/soc/intel/broadwell/pch/ramstage.c
rename to src/southbridge/intel/wildcatpoint/ramstage.c
diff --git a/src/soc/intel/broadwell/pch/sata.c b/src/southbridge/intel/wildcatpoint/sata.c
similarity index 97%
rename from src/soc/intel/broadwell/pch/sata.c
rename to src/southbridge/intel/wildcatpoint/sata.c
index 92d34c302c..d2bb5d37a1 100644
--- a/src/soc/intel/broadwell/pch/sata.c
+++ b/src/southbridge/intel/wildcatpoint/sata.c
@@ -9,7 +9,7 @@
 #include <delay.h>
 #include <soc/rcba.h>
 #include <soc/sata.h>
-#include <soc/intel/broadwell/pch/chip.h>
+#include <southbridge/intel/wildcatpoint/chip.h>
 #include <southbridge/intel/lynxpoint/iobp.h>
 
 static inline u32 sir_read(struct device *dev, int idx)
@@ -26,7 +26,7 @@ static inline void sir_write(struct device *dev, int idx, u32 value)
 
 static void sata_init(struct device *dev)
 {
-	const struct soc_intel_broadwell_pch_config *config = config_of(dev);
+	const struct southbridge_intel_wildcatpoint_config *config = config_of(dev);
 	u32 reg32;
 	u8 *abar;
 	u16 reg16;
@@ -259,7 +259,7 @@ static void sata_init(struct device *dev)
 static void sata_enable(struct device *dev)
 {
 	/* Get the chip configuration */
-	const struct soc_intel_broadwell_pch_config *config = config_of(dev);
+	const struct southbridge_intel_wildcatpoint_config *config = config_of(dev);
 	u16 map = 0x0060;
 
 	map |= (config->sata_port_map ^ 0xf) << 8;
diff --git a/src/soc/intel/broadwell/pch/serialio.c b/src/southbridge/intel/wildcatpoint/serialio.c
similarity index 98%
rename from src/soc/intel/broadwell/pch/serialio.c
rename to src/southbridge/intel/wildcatpoint/serialio.c
index 336b501b32..bc86db3098 100644
--- a/src/soc/intel/broadwell/pch/serialio.c
+++ b/src/southbridge/intel/wildcatpoint/serialio.c
@@ -12,7 +12,7 @@
 #include <soc/pch.h>
 #include <soc/rcba.h>
 #include <soc/serialio.h>
-#include <soc/intel/broadwell/pch/chip.h>
+#include <southbridge/intel/wildcatpoint/chip.h>
 #include <southbridge/intel/lynxpoint/iobp.h>
 #include <types.h>
 
@@ -156,7 +156,7 @@ static void serialio_init_once(int acpi_mode)
 
 static void serialio_init(struct device *dev)
 {
-	const struct soc_intel_broadwell_pch_config *config = config_of(dev);
+	const struct southbridge_intel_wildcatpoint_config *config = config_of(dev);
 	struct resource *bar0, *bar1;
 	int sio_index = -1;
 
diff --git a/src/soc/intel/broadwell/pch/smi.c b/src/southbridge/intel/wildcatpoint/smi.c
similarity index 100%
rename from src/soc/intel/broadwell/pch/smi.c
rename to src/southbridge/intel/wildcatpoint/smi.c
diff --git a/src/soc/intel/broadwell/pch/smihandler.c b/src/southbridge/intel/wildcatpoint/smihandler.c
similarity index 100%
rename from src/soc/intel/broadwell/pch/smihandler.c
rename to src/southbridge/intel/wildcatpoint/smihandler.c
diff --git a/src/soc/intel/broadwell/pch/usb_debug.c b/src/southbridge/intel/wildcatpoint/usb_debug.c
similarity index 100%
rename from src/soc/intel/broadwell/pch/usb_debug.c
rename to src/southbridge/intel/wildcatpoint/usb_debug.c
diff --git a/src/soc/intel/broadwell/pch/usb_ehci.c b/src/southbridge/intel/wildcatpoint/usb_ehci.c
similarity index 100%
rename from src/soc/intel/broadwell/pch/usb_ehci.c
rename to src/southbridge/intel/wildcatpoint/usb_ehci.c
diff --git a/src/soc/intel/broadwell/pch/usb_xhci.c b/src/southbridge/intel/wildcatpoint/usb_xhci.c
similarity index 100%
rename from src/soc/intel/broadwell/pch/usb_xhci.c
rename to src/southbridge/intel/wildcatpoint/usb_xhci.c

From 0bc5746188e48f61f093737284d9552fa922428b Mon Sep 17 00:00:00 2001
From: Angel Pons <th3fanbus@gmail.com>
Date: Mon, 23 Feb 2026 21:25:27 +0100
Subject: [PATCH 3586/3886] soc/intel/broadwell: Move to nb/intel/broadwell

In preparation to unify the Haswell and Broadwell codebases, move the
remaining Broadwell SoC code to the northbridge folder.

This change only moves the files, and does the minimal amount of edits
so that boards still build. Most of those edits boil down to "find and
replace".

Change-Id: I5bde032ee824a90328a78403ea03d39ad20f2b09
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91397
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
---
 src/mainboard/google/auron/devicetree.cb               |  2 +-
 src/mainboard/google/auron/dsdt.asl                    |  2 +-
 .../google/auron/variants/auron_paine/overridetree.cb  |  2 +-
 .../google/auron/variants/auron_yuna/overridetree.cb   |  2 +-
 .../google/auron/variants/buddy/overridetree.cb        |  2 +-
 .../google/auron/variants/gandof/overridetree.cb       |  2 +-
 .../google/auron/variants/lulu/overridetree.cb         |  2 +-
 .../google/auron/variants/samus/overridetree.cb        |  2 +-
 src/mainboard/google/jecht/devicetree.cb               |  2 +-
 src/mainboard/google/jecht/dsdt.asl                    |  2 +-
 src/mainboard/hp/elitebook_820_g2/devicetree.cb        |  2 +-
 src/mainboard/hp/elitebook_820_g2/dsdt.asl             |  2 +-
 src/mainboard/intel/wtm2/devicetree.cb                 |  2 +-
 src/mainboard/intel/wtm2/dsdt.asl                      |  2 +-
 src/mainboard/purism/librem_bdw/devicetree.cb          |  2 +-
 src/mainboard/purism/librem_bdw/dsdt.asl               |  2 +-
 .../librem_bdw/variants/librem13v1/overridetree.cb     |  2 +-
 .../librem_bdw/variants/librem15v2/overridetree.cb     |  2 +-
 src/{soc => northbridge}/intel/broadwell/Kconfig       |  0
 src/{soc => northbridge}/intel/broadwell/Makefile.mk   |  5 ++---
 src/{soc => northbridge}/intel/broadwell/acpi.c        |  2 +-
 .../intel/broadwell/acpi/device_nvs.asl                |  0
 .../intel/broadwell/acpi/platform.asl                  |  2 +-
 src/{soc => northbridge}/intel/broadwell/bootblock.c   |  0
 src/{soc => northbridge}/intel/broadwell/chip.h        |  2 +-
 src/{soc => northbridge}/intel/broadwell/early_init.c  |  0
 src/{soc => northbridge}/intel/broadwell/finalize.c    |  0
 src/{soc => northbridge}/intel/broadwell/gma.c         | 10 +++++-----
 .../intel/broadwell/include/soc/acpi.h                 |  0
 .../intel/broadwell/include/soc/adsp.h                 |  0
 .../intel/broadwell/include/soc/cfr.h                  |  2 +-
 .../intel/broadwell/include/soc/chromeos.h             |  0
 .../intel/broadwell/include/soc/device_nvs.h           |  0
 .../intel/broadwell/include/soc/ehci.h                 |  0
 .../intel/broadwell/include/soc/gpio.h                 |  0
 .../intel/broadwell/include/soc/igd.h                  |  0
 .../intel/broadwell/include/soc/iomap.h                |  0
 .../intel/broadwell/include/soc/lpc.h                  |  0
 .../intel/broadwell/include/soc/me.h                   |  0
 .../intel/broadwell/include/soc/nvs.h                  |  0
 .../intel/broadwell/include/soc/pch.h                  |  0
 .../intel/broadwell/include/soc/pci_devs.h             |  0
 .../intel/broadwell/include/soc/pei_data.h             |  0
 .../intel/broadwell/include/soc/pei_wrapper.h          |  0
 .../intel/broadwell/include/soc/pm.h                   |  0
 .../intel/broadwell/include/soc/rcba.h                 |  0
 .../intel/broadwell/include/soc/refcode.h              |  0
 .../intel/broadwell/include/soc/romstage.h             |  0
 .../intel/broadwell/include/soc/sata.h                 |  0
 .../intel/broadwell/include/soc/serialio.h             |  0
 .../intel/broadwell/include/soc/spi.h                  |  0
 .../intel/broadwell/include/soc/systemagent.h          |  0
 .../intel/broadwell/include/soc/xhci.h                 |  0
 src/{soc => northbridge}/intel/broadwell/memmap.c      |  0
 src/{soc => northbridge}/intel/broadwell/minihd.c      |  0
 src/{soc => northbridge}/intel/broadwell/northbridge.c |  2 +-
 src/{soc => northbridge}/intel/broadwell/pei_data.c    |  4 ++--
 src/{soc => northbridge}/intel/broadwell/raminit.c     |  0
 src/{soc => northbridge}/intel/broadwell/refcode.c     |  0
 .../intel/broadwell/report_platform.c                  |  0
 src/{soc => northbridge}/intel/broadwell/romstage.c    |  0
 src/{soc => northbridge}/intel/broadwell/spd.c         |  0
 src/southbridge/intel/wildcatpoint/ramstage.c          |  2 +-
 63 files changed, 33 insertions(+), 34 deletions(-)
 rename src/{soc => northbridge}/intel/broadwell/Kconfig (100%)
 rename src/{soc => northbridge}/intel/broadwell/Makefile.mk (94%)
 rename src/{soc => northbridge}/intel/broadwell/acpi.c (98%)
 rename src/{soc => northbridge}/intel/broadwell/acpi/device_nvs.asl (100%)
 rename src/{soc => northbridge}/intel/broadwell/acpi/platform.asl (90%)
 rename src/{soc => northbridge}/intel/broadwell/bootblock.c (100%)
 rename src/{soc => northbridge}/intel/broadwell/chip.h (94%)
 rename src/{soc => northbridge}/intel/broadwell/early_init.c (100%)
 rename src/{soc => northbridge}/intel/broadwell/finalize.c (100%)
 rename src/{soc => northbridge}/intel/broadwell/gma.c (98%)
 rename src/{soc => northbridge}/intel/broadwell/include/soc/acpi.h (100%)
 rename src/{soc => northbridge}/intel/broadwell/include/soc/adsp.h (100%)
 rename src/{soc => northbridge}/intel/broadwell/include/soc/cfr.h (95%)
 rename src/{soc => northbridge}/intel/broadwell/include/soc/chromeos.h (100%)
 rename src/{soc => northbridge}/intel/broadwell/include/soc/device_nvs.h (100%)
 rename src/{soc => northbridge}/intel/broadwell/include/soc/ehci.h (100%)
 rename src/{soc => northbridge}/intel/broadwell/include/soc/gpio.h (100%)
 rename src/{soc => northbridge}/intel/broadwell/include/soc/igd.h (100%)
 rename src/{soc => northbridge}/intel/broadwell/include/soc/iomap.h (100%)
 rename src/{soc => northbridge}/intel/broadwell/include/soc/lpc.h (100%)
 rename src/{soc => northbridge}/intel/broadwell/include/soc/me.h (100%)
 rename src/{soc => northbridge}/intel/broadwell/include/soc/nvs.h (100%)
 rename src/{soc => northbridge}/intel/broadwell/include/soc/pch.h (100%)
 rename src/{soc => northbridge}/intel/broadwell/include/soc/pci_devs.h (100%)
 rename src/{soc => northbridge}/intel/broadwell/include/soc/pei_data.h (100%)
 rename src/{soc => northbridge}/intel/broadwell/include/soc/pei_wrapper.h (100%)
 rename src/{soc => northbridge}/intel/broadwell/include/soc/pm.h (100%)
 rename src/{soc => northbridge}/intel/broadwell/include/soc/rcba.h (100%)
 rename src/{soc => northbridge}/intel/broadwell/include/soc/refcode.h (100%)
 rename src/{soc => northbridge}/intel/broadwell/include/soc/romstage.h (100%)
 rename src/{soc => northbridge}/intel/broadwell/include/soc/sata.h (100%)
 rename src/{soc => northbridge}/intel/broadwell/include/soc/serialio.h (100%)
 rename src/{soc => northbridge}/intel/broadwell/include/soc/spi.h (100%)
 rename src/{soc => northbridge}/intel/broadwell/include/soc/systemagent.h (100%)
 rename src/{soc => northbridge}/intel/broadwell/include/soc/xhci.h (100%)
 rename src/{soc => northbridge}/intel/broadwell/memmap.c (100%)
 rename src/{soc => northbridge}/intel/broadwell/minihd.c (100%)
 rename src/{soc => northbridge}/intel/broadwell/northbridge.c (99%)
 rename src/{soc => northbridge}/intel/broadwell/pei_data.c (89%)
 rename src/{soc => northbridge}/intel/broadwell/raminit.c (100%)
 rename src/{soc => northbridge}/intel/broadwell/refcode.c (100%)
 rename src/{soc => northbridge}/intel/broadwell/report_platform.c (100%)
 rename src/{soc => northbridge}/intel/broadwell/romstage.c (100%)
 rename src/{soc => northbridge}/intel/broadwell/spd.c (100%)

diff --git a/src/mainboard/google/auron/devicetree.cb b/src/mainboard/google/auron/devicetree.cb
index ff179c2ceb..3534ac9ea2 100644
--- a/src/mainboard/google/auron/devicetree.cb
+++ b/src/mainboard/google/auron/devicetree.cb
@@ -1,4 +1,4 @@
-chip soc/intel/broadwell
+chip northbridge/intel/broadwell
 
 	# IGD Displays
 	register "gfx" = "GMA_STATIC_DISPLAYS(0)"
diff --git a/src/mainboard/google/auron/dsdt.asl b/src/mainboard/google/auron/dsdt.asl
index c6453e9a24..9505158f3c 100644
--- a/src/mainboard/google/auron/dsdt.asl
+++ b/src/mainboard/google/auron/dsdt.asl
@@ -11,7 +11,7 @@ DefinitionBlock(
 )
 {
 	#include <acpi/dsdt_top.asl>
-	#include <soc/intel/broadwell/acpi/platform.asl>
+	#include <northbridge/intel/broadwell/acpi/platform.asl>
 
 	// Thermal handler
 	#include "acpi/thermal.asl"
diff --git a/src/mainboard/google/auron/variants/auron_paine/overridetree.cb b/src/mainboard/google/auron/variants/auron_paine/overridetree.cb
index b968ddb6bd..b18f1d77a3 100644
--- a/src/mainboard/google/auron/variants/auron_paine/overridetree.cb
+++ b/src/mainboard/google/auron/variants/auron_paine/overridetree.cb
@@ -1,4 +1,4 @@
-chip soc/intel/broadwell
+chip northbridge/intel/broadwell
 
 	register "panel_cfg" = "{
 		.up_delay_ms		=  40,
diff --git a/src/mainboard/google/auron/variants/auron_yuna/overridetree.cb b/src/mainboard/google/auron/variants/auron_yuna/overridetree.cb
index c9d9078c46..d658643130 100644
--- a/src/mainboard/google/auron/variants/auron_yuna/overridetree.cb
+++ b/src/mainboard/google/auron/variants/auron_yuna/overridetree.cb
@@ -1,4 +1,4 @@
-chip soc/intel/broadwell
+chip northbridge/intel/broadwell
 
 	register "panel_cfg" = "{
 		.up_delay_ms		=  40,
diff --git a/src/mainboard/google/auron/variants/buddy/overridetree.cb b/src/mainboard/google/auron/variants/buddy/overridetree.cb
index e1bf686cc8..81fecac9c7 100644
--- a/src/mainboard/google/auron/variants/buddy/overridetree.cb
+++ b/src/mainboard/google/auron/variants/buddy/overridetree.cb
@@ -1,4 +1,4 @@
-chip soc/intel/broadwell
+chip northbridge/intel/broadwell
 
 	register "panel_cfg" = "{
 		.up_delay_ms		=  40,
diff --git a/src/mainboard/google/auron/variants/gandof/overridetree.cb b/src/mainboard/google/auron/variants/gandof/overridetree.cb
index ddb7a35dfa..c74f9f80b4 100644
--- a/src/mainboard/google/auron/variants/gandof/overridetree.cb
+++ b/src/mainboard/google/auron/variants/gandof/overridetree.cb
@@ -1,4 +1,4 @@
-chip soc/intel/broadwell
+chip northbridge/intel/broadwell
 
 	register "panel_cfg" = "{
 		.up_delay_ms		=  40,
diff --git a/src/mainboard/google/auron/variants/lulu/overridetree.cb b/src/mainboard/google/auron/variants/lulu/overridetree.cb
index b968ddb6bd..b18f1d77a3 100644
--- a/src/mainboard/google/auron/variants/lulu/overridetree.cb
+++ b/src/mainboard/google/auron/variants/lulu/overridetree.cb
@@ -1,4 +1,4 @@
-chip soc/intel/broadwell
+chip northbridge/intel/broadwell
 
 	register "panel_cfg" = "{
 		.up_delay_ms		=  40,
diff --git a/src/mainboard/google/auron/variants/samus/overridetree.cb b/src/mainboard/google/auron/variants/samus/overridetree.cb
index b9a6431d0e..013c3133ea 100644
--- a/src/mainboard/google/auron/variants/samus/overridetree.cb
+++ b/src/mainboard/google/auron/variants/samus/overridetree.cb
@@ -1,4 +1,4 @@
-chip soc/intel/broadwell
+chip northbridge/intel/broadwell
 
 	# Enable DDI2 Hotplug with 6ms pulse
 	register "gpu_dp_c_hotplug" = "0x06"
diff --git a/src/mainboard/google/jecht/devicetree.cb b/src/mainboard/google/jecht/devicetree.cb
index 2f8ccdc365..8de489c0ee 100644
--- a/src/mainboard/google/jecht/devicetree.cb
+++ b/src/mainboard/google/jecht/devicetree.cb
@@ -1,4 +1,4 @@
-chip soc/intel/broadwell
+chip northbridge/intel/broadwell
 
 	# Disable eDP Hotplug
 	register "gpu_dp_d_hotplug" = "0x00"
diff --git a/src/mainboard/google/jecht/dsdt.asl b/src/mainboard/google/jecht/dsdt.asl
index 7cc8c7b9f4..8e76080411 100644
--- a/src/mainboard/google/jecht/dsdt.asl
+++ b/src/mainboard/google/jecht/dsdt.asl
@@ -19,7 +19,7 @@ DefinitionBlock(
 
 	// global NVS and variables
 	#include <southbridge/intel/wildcatpoint/acpi/globalnvs.asl>
-	#include <soc/intel/broadwell/acpi/device_nvs.asl>
+	#include <northbridge/intel/broadwell/acpi/device_nvs.asl>
 
 	// CPU
 	#include <cpu/intel/common/acpi/cpu.asl>
diff --git a/src/mainboard/hp/elitebook_820_g2/devicetree.cb b/src/mainboard/hp/elitebook_820_g2/devicetree.cb
index 63df5d16d9..1641472522 100644
--- a/src/mainboard/hp/elitebook_820_g2/devicetree.cb
+++ b/src/mainboard/hp/elitebook_820_g2/devicetree.cb
@@ -1,6 +1,6 @@
 # SPDX-License-Identifier: GPL-2.0-or-later
 
-chip soc/intel/broadwell
+chip northbridge/intel/broadwell
 	chip cpu/intel/haswell
 		device cpu_cluster 0 on ops haswell_cpu_bus_ops end
 	end
diff --git a/src/mainboard/hp/elitebook_820_g2/dsdt.asl b/src/mainboard/hp/elitebook_820_g2/dsdt.asl
index 6b1b4267d5..bb744911a3 100644
--- a/src/mainboard/hp/elitebook_820_g2/dsdt.asl
+++ b/src/mainboard/hp/elitebook_820_g2/dsdt.asl
@@ -18,7 +18,7 @@ DefinitionBlock(
 	#include <soc/intel/common/acpi/acpi_wake_source.asl>
 
 	#include <southbridge/intel/wildcatpoint/acpi/globalnvs.asl>
-	#include <soc/intel/broadwell/acpi/device_nvs.asl>
+	#include <northbridge/intel/broadwell/acpi/device_nvs.asl>
 	#include <cpu/intel/common/acpi/cpu.asl>
 	#include <southbridge/intel/common/acpi/sleepstates.asl>
 
diff --git a/src/mainboard/intel/wtm2/devicetree.cb b/src/mainboard/intel/wtm2/devicetree.cb
index 0b8bd36085..453a45a70a 100644
--- a/src/mainboard/intel/wtm2/devicetree.cb
+++ b/src/mainboard/intel/wtm2/devicetree.cb
@@ -1,4 +1,4 @@
-chip soc/intel/broadwell
+chip northbridge/intel/broadwell
 
 	# Enable DisplayPort 1 Hotplug with 6ms pulse
 	register "gpu_dp_d_hotplug" = "0x06"
diff --git a/src/mainboard/intel/wtm2/dsdt.asl b/src/mainboard/intel/wtm2/dsdt.asl
index 26ed596067..efa50eb92d 100644
--- a/src/mainboard/intel/wtm2/dsdt.asl
+++ b/src/mainboard/intel/wtm2/dsdt.asl
@@ -19,7 +19,7 @@ DefinitionBlock(
 
 	// global NVS and variables
 	#include <southbridge/intel/wildcatpoint/acpi/globalnvs.asl>
-	#include <soc/intel/broadwell/acpi/device_nvs.asl>
+	#include <northbridge/intel/broadwell/acpi/device_nvs.asl>
 
 	// CPU
 	#include <cpu/intel/common/acpi/cpu.asl>
diff --git a/src/mainboard/purism/librem_bdw/devicetree.cb b/src/mainboard/purism/librem_bdw/devicetree.cb
index 934fd7eb8b..86d2cc2bbd 100644
--- a/src/mainboard/purism/librem_bdw/devicetree.cb
+++ b/src/mainboard/purism/librem_bdw/devicetree.cb
@@ -1,4 +1,4 @@
-chip soc/intel/broadwell
+chip northbridge/intel/broadwell
 
 	# IGD Displays
 	register "gfx" = "GMA_STATIC_DISPLAYS(0)"
diff --git a/src/mainboard/purism/librem_bdw/dsdt.asl b/src/mainboard/purism/librem_bdw/dsdt.asl
index 2e8b5c57e2..7439e941de 100644
--- a/src/mainboard/purism/librem_bdw/dsdt.asl
+++ b/src/mainboard/purism/librem_bdw/dsdt.asl
@@ -11,7 +11,7 @@ DefinitionBlock(
 )
 {
 	#include <acpi/dsdt_top.asl>
-	#include <soc/intel/broadwell/acpi/platform.asl>
+	#include <northbridge/intel/broadwell/acpi/platform.asl>
 	#include <southbridge/intel/wildcatpoint/acpi/globalnvs.asl>
 	#include <cpu/intel/common/acpi/cpu.asl>
 
diff --git a/src/mainboard/purism/librem_bdw/variants/librem13v1/overridetree.cb b/src/mainboard/purism/librem_bdw/variants/librem13v1/overridetree.cb
index 9d47ae8055..1a8a469ea4 100644
--- a/src/mainboard/purism/librem_bdw/variants/librem13v1/overridetree.cb
+++ b/src/mainboard/purism/librem_bdw/variants/librem13v1/overridetree.cb
@@ -1,4 +1,4 @@
-chip soc/intel/broadwell
+chip northbridge/intel/broadwell
 
 	device domain 0 on
 		chip southbridge/intel/wildcatpoint
diff --git a/src/mainboard/purism/librem_bdw/variants/librem15v2/overridetree.cb b/src/mainboard/purism/librem_bdw/variants/librem15v2/overridetree.cb
index 01d317e6b5..e2a66d8357 100644
--- a/src/mainboard/purism/librem_bdw/variants/librem15v2/overridetree.cb
+++ b/src/mainboard/purism/librem_bdw/variants/librem15v2/overridetree.cb
@@ -1,4 +1,4 @@
-chip soc/intel/broadwell
+chip northbridge/intel/broadwell
 
 	register "dq_pins_interleaved" = "true"
 
diff --git a/src/soc/intel/broadwell/Kconfig b/src/northbridge/intel/broadwell/Kconfig
similarity index 100%
rename from src/soc/intel/broadwell/Kconfig
rename to src/northbridge/intel/broadwell/Kconfig
diff --git a/src/soc/intel/broadwell/Makefile.mk b/src/northbridge/intel/broadwell/Makefile.mk
similarity index 94%
rename from src/soc/intel/broadwell/Makefile.mk
rename to src/northbridge/intel/broadwell/Makefile.mk
index 3565cd180b..16576371ae 100644
--- a/src/soc/intel/broadwell/Makefile.mk
+++ b/src/northbridge/intel/broadwell/Makefile.mk
@@ -1,7 +1,6 @@
 ## SPDX-License-Identifier: GPL-2.0-only
-ifeq ($(CONFIG_SOC_INTEL_BROADWELL),y)
 
-subdirs-y += pch
+ifeq ($(CONFIG_SOC_INTEL_BROADWELL),y)
 
 bootblock-y += bootblock.c
 
@@ -23,7 +22,7 @@ ramstage-y += pei_data.c
 romstage-y += pei_data.c
 ramstage-$(CONFIG_HAVE_REFCODE_BLOB) += refcode.c
 
-CPPFLAGS_common += -Isrc/soc/intel/broadwell/include
+CPPFLAGS_common += -Isrc/northbridge/intel/broadwell/include
 
 # If an MRC file is an ELF file determine the entry address and first loadable
 # section offset in the file. Subtract the offset from the entry address to
diff --git a/src/soc/intel/broadwell/acpi.c b/src/northbridge/intel/broadwell/acpi.c
similarity index 98%
rename from src/soc/intel/broadwell/acpi.c
rename to src/northbridge/intel/broadwell/acpi.c
index 4c1cdf3392..7ca60c1f59 100644
--- a/src/soc/intel/broadwell/acpi.c
+++ b/src/northbridge/intel/broadwell/acpi.c
@@ -18,7 +18,7 @@
 #include <soc/pci_devs.h>
 #include <soc/pm.h>
 #include <soc/systemagent.h>
-#include <soc/intel/broadwell/chip.h>
+#include <northbridge/intel/broadwell/chip.h>
 
 static unsigned long acpi_fill_dmar(unsigned long current)
 {
diff --git a/src/soc/intel/broadwell/acpi/device_nvs.asl b/src/northbridge/intel/broadwell/acpi/device_nvs.asl
similarity index 100%
rename from src/soc/intel/broadwell/acpi/device_nvs.asl
rename to src/northbridge/intel/broadwell/acpi/device_nvs.asl
diff --git a/src/soc/intel/broadwell/acpi/platform.asl b/src/northbridge/intel/broadwell/acpi/platform.asl
similarity index 90%
rename from src/soc/intel/broadwell/acpi/platform.asl
rename to src/northbridge/intel/broadwell/acpi/platform.asl
index fe254ff6f0..3a57f995d1 100644
--- a/src/soc/intel/broadwell/acpi/platform.asl
+++ b/src/northbridge/intel/broadwell/acpi/platform.asl
@@ -1,6 +1,6 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
-#include <soc/intel/broadwell/acpi/device_nvs.asl>
+#include <northbridge/intel/broadwell/acpi/device_nvs.asl>
 #include <southbridge/intel/common/acpi/platform.asl>
 
 /*
diff --git a/src/soc/intel/broadwell/bootblock.c b/src/northbridge/intel/broadwell/bootblock.c
similarity index 100%
rename from src/soc/intel/broadwell/bootblock.c
rename to src/northbridge/intel/broadwell/bootblock.c
diff --git a/src/soc/intel/broadwell/chip.h b/src/northbridge/intel/broadwell/chip.h
similarity index 94%
rename from src/soc/intel/broadwell/chip.h
rename to src/northbridge/intel/broadwell/chip.h
index 2b5cccd56e..6b02f59ed3 100644
--- a/src/soc/intel/broadwell/chip.h
+++ b/src/northbridge/intel/broadwell/chip.h
@@ -6,7 +6,7 @@
 #include <drivers/intel/gma/gma.h>
 #include <stdint.h>
 
-struct soc_intel_broadwell_config {
+struct northbridge_intel_broadwell_config {
 	/*
 	 * Digital Port Hotplug Enable:
 	 *  0x04 = Enabled, 2ms short pulse
diff --git a/src/soc/intel/broadwell/early_init.c b/src/northbridge/intel/broadwell/early_init.c
similarity index 100%
rename from src/soc/intel/broadwell/early_init.c
rename to src/northbridge/intel/broadwell/early_init.c
diff --git a/src/soc/intel/broadwell/finalize.c b/src/northbridge/intel/broadwell/finalize.c
similarity index 100%
rename from src/soc/intel/broadwell/finalize.c
rename to src/northbridge/intel/broadwell/finalize.c
diff --git a/src/soc/intel/broadwell/gma.c b/src/northbridge/intel/broadwell/gma.c
similarity index 98%
rename from src/soc/intel/broadwell/gma.c
rename to src/northbridge/intel/broadwell/gma.c
index 639a945d75..a166b7998b 100644
--- a/src/soc/intel/broadwell/gma.c
+++ b/src/northbridge/intel/broadwell/gma.c
@@ -19,7 +19,7 @@
 #include <drivers/intel/gma/opregion.h>
 #include <soc/pm.h>
 #include <soc/systemagent.h>
-#include <soc/intel/broadwell/chip.h>
+#include <northbridge/intel/broadwell/chip.h>
 #include <security/vboot/vbnv.h>
 #include <soc/igd.h>
 #include <types.h>
@@ -285,7 +285,7 @@ int gtt_poll(u32 reg, u32 mask, u32 value)
 
 static void gma_setup_panel(struct device *dev)
 {
-	struct soc_intel_broadwell_config *conf = config_of(dev);
+	struct northbridge_intel_broadwell_config *conf = config_of(dev);
 	const struct i915_gpu_panel_config *panel_cfg = &conf->panel_cfg;
 	u32 reg32;
 
@@ -362,7 +362,7 @@ static void gma_setup_panel(struct device *dev)
 static int igd_get_cdclk_haswell(u32 *const cdsel, int *const inform_pc,
 				 struct device *const dev)
 {
-	const struct soc_intel_broadwell_config *const conf = config_of(dev);
+	const struct northbridge_intel_broadwell_config *const conf = config_of(dev);
 	int cdclk = conf->cdclk;
 
 	/* Check for ULX GT1 or GT2 */
@@ -397,7 +397,7 @@ static int igd_get_cdclk_broadwell(u32 *const cdsel, int *const inform_pc,
 				   struct device *const dev)
 {
 	static const u32 cdsel_by_cdclk[] = { 0, 2, 0, 1, 3 };
-	const struct soc_intel_broadwell_config *const conf = config_of(dev);
+	const struct northbridge_intel_broadwell_config *const conf = config_of(dev);
 	int cdclk = conf->cdclk;
 
 	/* Check for ULX */
@@ -576,7 +576,7 @@ static void igd_init(struct device *dev)
 
 static void gma_generate_ssdt(const struct device *dev)
 {
-	const struct soc_intel_broadwell_config *chip = dev->chip_info;
+	const struct northbridge_intel_broadwell_config *chip = dev->chip_info;
 
 	drivers_intel_gma_displays_ssdt_generate(&chip->gfx);
 }
diff --git a/src/soc/intel/broadwell/include/soc/acpi.h b/src/northbridge/intel/broadwell/include/soc/acpi.h
similarity index 100%
rename from src/soc/intel/broadwell/include/soc/acpi.h
rename to src/northbridge/intel/broadwell/include/soc/acpi.h
diff --git a/src/soc/intel/broadwell/include/soc/adsp.h b/src/northbridge/intel/broadwell/include/soc/adsp.h
similarity index 100%
rename from src/soc/intel/broadwell/include/soc/adsp.h
rename to src/northbridge/intel/broadwell/include/soc/adsp.h
diff --git a/src/soc/intel/broadwell/include/soc/cfr.h b/src/northbridge/intel/broadwell/include/soc/cfr.h
similarity index 95%
rename from src/soc/intel/broadwell/include/soc/cfr.h
rename to src/northbridge/intel/broadwell/include/soc/cfr.h
index 91dc9048c7..7f1e604e14 100644
--- a/src/soc/intel/broadwell/include/soc/cfr.h
+++ b/src/northbridge/intel/broadwell/include/soc/cfr.h
@@ -1,7 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
 /*
- * CFR enums and structs for soc/intel/broadwell
+ * CFR enums and structs for northbridge/intel/broadwell
  */
 
 #ifndef _BROADWELL_CFR_H_
diff --git a/src/soc/intel/broadwell/include/soc/chromeos.h b/src/northbridge/intel/broadwell/include/soc/chromeos.h
similarity index 100%
rename from src/soc/intel/broadwell/include/soc/chromeos.h
rename to src/northbridge/intel/broadwell/include/soc/chromeos.h
diff --git a/src/soc/intel/broadwell/include/soc/device_nvs.h b/src/northbridge/intel/broadwell/include/soc/device_nvs.h
similarity index 100%
rename from src/soc/intel/broadwell/include/soc/device_nvs.h
rename to src/northbridge/intel/broadwell/include/soc/device_nvs.h
diff --git a/src/soc/intel/broadwell/include/soc/ehci.h b/src/northbridge/intel/broadwell/include/soc/ehci.h
similarity index 100%
rename from src/soc/intel/broadwell/include/soc/ehci.h
rename to src/northbridge/intel/broadwell/include/soc/ehci.h
diff --git a/src/soc/intel/broadwell/include/soc/gpio.h b/src/northbridge/intel/broadwell/include/soc/gpio.h
similarity index 100%
rename from src/soc/intel/broadwell/include/soc/gpio.h
rename to src/northbridge/intel/broadwell/include/soc/gpio.h
diff --git a/src/soc/intel/broadwell/include/soc/igd.h b/src/northbridge/intel/broadwell/include/soc/igd.h
similarity index 100%
rename from src/soc/intel/broadwell/include/soc/igd.h
rename to src/northbridge/intel/broadwell/include/soc/igd.h
diff --git a/src/soc/intel/broadwell/include/soc/iomap.h b/src/northbridge/intel/broadwell/include/soc/iomap.h
similarity index 100%
rename from src/soc/intel/broadwell/include/soc/iomap.h
rename to src/northbridge/intel/broadwell/include/soc/iomap.h
diff --git a/src/soc/intel/broadwell/include/soc/lpc.h b/src/northbridge/intel/broadwell/include/soc/lpc.h
similarity index 100%
rename from src/soc/intel/broadwell/include/soc/lpc.h
rename to src/northbridge/intel/broadwell/include/soc/lpc.h
diff --git a/src/soc/intel/broadwell/include/soc/me.h b/src/northbridge/intel/broadwell/include/soc/me.h
similarity index 100%
rename from src/soc/intel/broadwell/include/soc/me.h
rename to src/northbridge/intel/broadwell/include/soc/me.h
diff --git a/src/soc/intel/broadwell/include/soc/nvs.h b/src/northbridge/intel/broadwell/include/soc/nvs.h
similarity index 100%
rename from src/soc/intel/broadwell/include/soc/nvs.h
rename to src/northbridge/intel/broadwell/include/soc/nvs.h
diff --git a/src/soc/intel/broadwell/include/soc/pch.h b/src/northbridge/intel/broadwell/include/soc/pch.h
similarity index 100%
rename from src/soc/intel/broadwell/include/soc/pch.h
rename to src/northbridge/intel/broadwell/include/soc/pch.h
diff --git a/src/soc/intel/broadwell/include/soc/pci_devs.h b/src/northbridge/intel/broadwell/include/soc/pci_devs.h
similarity index 100%
rename from src/soc/intel/broadwell/include/soc/pci_devs.h
rename to src/northbridge/intel/broadwell/include/soc/pci_devs.h
diff --git a/src/soc/intel/broadwell/include/soc/pei_data.h b/src/northbridge/intel/broadwell/include/soc/pei_data.h
similarity index 100%
rename from src/soc/intel/broadwell/include/soc/pei_data.h
rename to src/northbridge/intel/broadwell/include/soc/pei_data.h
diff --git a/src/soc/intel/broadwell/include/soc/pei_wrapper.h b/src/northbridge/intel/broadwell/include/soc/pei_wrapper.h
similarity index 100%
rename from src/soc/intel/broadwell/include/soc/pei_wrapper.h
rename to src/northbridge/intel/broadwell/include/soc/pei_wrapper.h
diff --git a/src/soc/intel/broadwell/include/soc/pm.h b/src/northbridge/intel/broadwell/include/soc/pm.h
similarity index 100%
rename from src/soc/intel/broadwell/include/soc/pm.h
rename to src/northbridge/intel/broadwell/include/soc/pm.h
diff --git a/src/soc/intel/broadwell/include/soc/rcba.h b/src/northbridge/intel/broadwell/include/soc/rcba.h
similarity index 100%
rename from src/soc/intel/broadwell/include/soc/rcba.h
rename to src/northbridge/intel/broadwell/include/soc/rcba.h
diff --git a/src/soc/intel/broadwell/include/soc/refcode.h b/src/northbridge/intel/broadwell/include/soc/refcode.h
similarity index 100%
rename from src/soc/intel/broadwell/include/soc/refcode.h
rename to src/northbridge/intel/broadwell/include/soc/refcode.h
diff --git a/src/soc/intel/broadwell/include/soc/romstage.h b/src/northbridge/intel/broadwell/include/soc/romstage.h
similarity index 100%
rename from src/soc/intel/broadwell/include/soc/romstage.h
rename to src/northbridge/intel/broadwell/include/soc/romstage.h
diff --git a/src/soc/intel/broadwell/include/soc/sata.h b/src/northbridge/intel/broadwell/include/soc/sata.h
similarity index 100%
rename from src/soc/intel/broadwell/include/soc/sata.h
rename to src/northbridge/intel/broadwell/include/soc/sata.h
diff --git a/src/soc/intel/broadwell/include/soc/serialio.h b/src/northbridge/intel/broadwell/include/soc/serialio.h
similarity index 100%
rename from src/soc/intel/broadwell/include/soc/serialio.h
rename to src/northbridge/intel/broadwell/include/soc/serialio.h
diff --git a/src/soc/intel/broadwell/include/soc/spi.h b/src/northbridge/intel/broadwell/include/soc/spi.h
similarity index 100%
rename from src/soc/intel/broadwell/include/soc/spi.h
rename to src/northbridge/intel/broadwell/include/soc/spi.h
diff --git a/src/soc/intel/broadwell/include/soc/systemagent.h b/src/northbridge/intel/broadwell/include/soc/systemagent.h
similarity index 100%
rename from src/soc/intel/broadwell/include/soc/systemagent.h
rename to src/northbridge/intel/broadwell/include/soc/systemagent.h
diff --git a/src/soc/intel/broadwell/include/soc/xhci.h b/src/northbridge/intel/broadwell/include/soc/xhci.h
similarity index 100%
rename from src/soc/intel/broadwell/include/soc/xhci.h
rename to src/northbridge/intel/broadwell/include/soc/xhci.h
diff --git a/src/soc/intel/broadwell/memmap.c b/src/northbridge/intel/broadwell/memmap.c
similarity index 100%
rename from src/soc/intel/broadwell/memmap.c
rename to src/northbridge/intel/broadwell/memmap.c
diff --git a/src/soc/intel/broadwell/minihd.c b/src/northbridge/intel/broadwell/minihd.c
similarity index 100%
rename from src/soc/intel/broadwell/minihd.c
rename to src/northbridge/intel/broadwell/minihd.c
diff --git a/src/soc/intel/broadwell/northbridge.c b/src/northbridge/intel/broadwell/northbridge.c
similarity index 99%
rename from src/soc/intel/broadwell/northbridge.c
rename to src/northbridge/intel/broadwell/northbridge.c
index c869b31035..771df81044 100644
--- a/src/soc/intel/broadwell/northbridge.c
+++ b/src/northbridge/intel/broadwell/northbridge.c
@@ -411,7 +411,7 @@ static void broadwell_init_pre_device(void *chip_info)
 	broadwell_run_reference_code();
 }
 
-struct chip_operations soc_intel_broadwell_ops = {
+struct chip_operations northbridge_intel_broadwell_ops = {
 	.name = "Intel Broadwell",
 	.init       = &broadwell_init_pre_device,
 };
diff --git a/src/soc/intel/broadwell/pei_data.c b/src/northbridge/intel/broadwell/pei_data.c
similarity index 89%
rename from src/soc/intel/broadwell/pei_data.c
rename to src/northbridge/intel/broadwell/pei_data.c
index 4853294e90..28adb30e15 100644
--- a/src/soc/intel/broadwell/pei_data.c
+++ b/src/northbridge/intel/broadwell/pei_data.c
@@ -5,7 +5,7 @@
 #include <soc/iomap.h>
 #include <soc/pei_data.h>
 #include <soc/pei_wrapper.h>
-#include <soc/intel/broadwell/chip.h>
+#include <northbridge/intel/broadwell/chip.h>
 #include <static.h>
 
 static void ABI_X86 send_to_console(unsigned char b)
@@ -15,7 +15,7 @@ static void ABI_X86 send_to_console(unsigned char b)
 
 void broadwell_fill_pei_data(struct pei_data *pei_data)
 {
-	const struct soc_intel_broadwell_config *cfg = config_of_soc();
+	const struct northbridge_intel_broadwell_config *cfg = config_of_soc();
 
 	pei_data->pei_version = PEI_VERSION;
 	pei_data->board_type = BOARD_TYPE_ULT;
diff --git a/src/soc/intel/broadwell/raminit.c b/src/northbridge/intel/broadwell/raminit.c
similarity index 100%
rename from src/soc/intel/broadwell/raminit.c
rename to src/northbridge/intel/broadwell/raminit.c
diff --git a/src/soc/intel/broadwell/refcode.c b/src/northbridge/intel/broadwell/refcode.c
similarity index 100%
rename from src/soc/intel/broadwell/refcode.c
rename to src/northbridge/intel/broadwell/refcode.c
diff --git a/src/soc/intel/broadwell/report_platform.c b/src/northbridge/intel/broadwell/report_platform.c
similarity index 100%
rename from src/soc/intel/broadwell/report_platform.c
rename to src/northbridge/intel/broadwell/report_platform.c
diff --git a/src/soc/intel/broadwell/romstage.c b/src/northbridge/intel/broadwell/romstage.c
similarity index 100%
rename from src/soc/intel/broadwell/romstage.c
rename to src/northbridge/intel/broadwell/romstage.c
diff --git a/src/soc/intel/broadwell/spd.c b/src/northbridge/intel/broadwell/spd.c
similarity index 100%
rename from src/soc/intel/broadwell/spd.c
rename to src/northbridge/intel/broadwell/spd.c
diff --git a/src/southbridge/intel/wildcatpoint/ramstage.c b/src/southbridge/intel/wildcatpoint/ramstage.c
index 027b3bb1c9..19105ff799 100644
--- a/src/southbridge/intel/wildcatpoint/ramstage.c
+++ b/src/southbridge/intel/wildcatpoint/ramstage.c
@@ -7,7 +7,7 @@
 #include <device/device.h>
 #include <soc/nvs.h>
 #include <soc/pm.h>
-#include <soc/intel/broadwell/chip.h>
+#include <northbridge/intel/broadwell/chip.h>
 
 /* Save bit index for PM1_STS and GPE_STS for ACPI _SWS */
 static void pm_fill_gnvs(struct global_nvs *gnvs, const struct chipset_power_state *ps)

From 4eb0fd7bea3fbee4fe46e84b4b3d26844e3a2ce0 Mon Sep 17 00:00:00 2001
From: Angel Pons <th3fanbus@gmail.com>
Date: Mon, 23 Feb 2026 21:43:00 +0100
Subject: [PATCH 3587/3886] nb/intel/broadwell: Move PCH headers to
 wildcatpoint

Since this used to be a SoC (no distinction between CPU/NB/SB parts),
all the headers were in a single place. Move headers about PCH things
to where they belong.

Change-Id: I296f57f5575d026ad87698e972eb9f448d54d09b
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91398
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
---
 src/southbridge/intel/wildcatpoint/Makefile.mk                  | 2 ++
 .../intel/wildcatpoint}/include/soc/adsp.h                      | 0
 .../intel/wildcatpoint}/include/soc/cfr.h                       | 0
 .../intel/wildcatpoint}/include/soc/chromeos.h                  | 0
 .../intel/wildcatpoint}/include/soc/ehci.h                      | 0
 .../intel/wildcatpoint}/include/soc/gpio.h                      | 0
 .../intel/wildcatpoint}/include/soc/iomap.h                     | 0
 .../intel/wildcatpoint}/include/soc/lpc.h                       | 0
 .../intel/wildcatpoint}/include/soc/me.h                        | 0
 .../intel/wildcatpoint}/include/soc/nvs.h                       | 0
 .../intel/wildcatpoint}/include/soc/pch.h                       | 0
 .../intel/wildcatpoint}/include/soc/pm.h                        | 0
 .../intel/wildcatpoint}/include/soc/rcba.h                      | 0
 .../intel/wildcatpoint}/include/soc/sata.h                      | 0
 .../intel/wildcatpoint}/include/soc/serialio.h                  | 0
 .../intel/wildcatpoint}/include/soc/spi.h                       | 0
 .../intel/wildcatpoint}/include/soc/xhci.h                      | 0
 17 files changed, 2 insertions(+)
 rename src/{northbridge/intel/broadwell => southbridge/intel/wildcatpoint}/include/soc/adsp.h (100%)
 rename src/{northbridge/intel/broadwell => southbridge/intel/wildcatpoint}/include/soc/cfr.h (100%)
 rename src/{northbridge/intel/broadwell => southbridge/intel/wildcatpoint}/include/soc/chromeos.h (100%)
 rename src/{northbridge/intel/broadwell => southbridge/intel/wildcatpoint}/include/soc/ehci.h (100%)
 rename src/{northbridge/intel/broadwell => southbridge/intel/wildcatpoint}/include/soc/gpio.h (100%)
 rename src/{northbridge/intel/broadwell => southbridge/intel/wildcatpoint}/include/soc/iomap.h (100%)
 rename src/{northbridge/intel/broadwell => southbridge/intel/wildcatpoint}/include/soc/lpc.h (100%)
 rename src/{northbridge/intel/broadwell => southbridge/intel/wildcatpoint}/include/soc/me.h (100%)
 rename src/{northbridge/intel/broadwell => southbridge/intel/wildcatpoint}/include/soc/nvs.h (100%)
 rename src/{northbridge/intel/broadwell => southbridge/intel/wildcatpoint}/include/soc/pch.h (100%)
 rename src/{northbridge/intel/broadwell => southbridge/intel/wildcatpoint}/include/soc/pm.h (100%)
 rename src/{northbridge/intel/broadwell => southbridge/intel/wildcatpoint}/include/soc/rcba.h (100%)
 rename src/{northbridge/intel/broadwell => southbridge/intel/wildcatpoint}/include/soc/sata.h (100%)
 rename src/{northbridge/intel/broadwell => southbridge/intel/wildcatpoint}/include/soc/serialio.h (100%)
 rename src/{northbridge/intel/broadwell => southbridge/intel/wildcatpoint}/include/soc/spi.h (100%)
 rename src/{northbridge/intel/broadwell => southbridge/intel/wildcatpoint}/include/soc/xhci.h (100%)

diff --git a/src/southbridge/intel/wildcatpoint/Makefile.mk b/src/southbridge/intel/wildcatpoint/Makefile.mk
index ee631d44cd..ec54db4632 100644
--- a/src/southbridge/intel/wildcatpoint/Makefile.mk
+++ b/src/southbridge/intel/wildcatpoint/Makefile.mk
@@ -47,4 +47,6 @@ bootblock-$(CONFIG_SERIALIO_UART_CONSOLE) += ../lynxpoint/uart_init.c
 all-$(CONFIG_SERIALIO_UART_CONSOLE) += ../lynxpoint/uart.c
 smm-$(CONFIG_SERIALIO_UART_CONSOLE) += ../lynxpoint/uart.c
 
+CPPFLAGS_common += -Isrc/southbridge/intel/wildcatpoint/include
+
 endif
diff --git a/src/northbridge/intel/broadwell/include/soc/adsp.h b/src/southbridge/intel/wildcatpoint/include/soc/adsp.h
similarity index 100%
rename from src/northbridge/intel/broadwell/include/soc/adsp.h
rename to src/southbridge/intel/wildcatpoint/include/soc/adsp.h
diff --git a/src/northbridge/intel/broadwell/include/soc/cfr.h b/src/southbridge/intel/wildcatpoint/include/soc/cfr.h
similarity index 100%
rename from src/northbridge/intel/broadwell/include/soc/cfr.h
rename to src/southbridge/intel/wildcatpoint/include/soc/cfr.h
diff --git a/src/northbridge/intel/broadwell/include/soc/chromeos.h b/src/southbridge/intel/wildcatpoint/include/soc/chromeos.h
similarity index 100%
rename from src/northbridge/intel/broadwell/include/soc/chromeos.h
rename to src/southbridge/intel/wildcatpoint/include/soc/chromeos.h
diff --git a/src/northbridge/intel/broadwell/include/soc/ehci.h b/src/southbridge/intel/wildcatpoint/include/soc/ehci.h
similarity index 100%
rename from src/northbridge/intel/broadwell/include/soc/ehci.h
rename to src/southbridge/intel/wildcatpoint/include/soc/ehci.h
diff --git a/src/northbridge/intel/broadwell/include/soc/gpio.h b/src/southbridge/intel/wildcatpoint/include/soc/gpio.h
similarity index 100%
rename from src/northbridge/intel/broadwell/include/soc/gpio.h
rename to src/southbridge/intel/wildcatpoint/include/soc/gpio.h
diff --git a/src/northbridge/intel/broadwell/include/soc/iomap.h b/src/southbridge/intel/wildcatpoint/include/soc/iomap.h
similarity index 100%
rename from src/northbridge/intel/broadwell/include/soc/iomap.h
rename to src/southbridge/intel/wildcatpoint/include/soc/iomap.h
diff --git a/src/northbridge/intel/broadwell/include/soc/lpc.h b/src/southbridge/intel/wildcatpoint/include/soc/lpc.h
similarity index 100%
rename from src/northbridge/intel/broadwell/include/soc/lpc.h
rename to src/southbridge/intel/wildcatpoint/include/soc/lpc.h
diff --git a/src/northbridge/intel/broadwell/include/soc/me.h b/src/southbridge/intel/wildcatpoint/include/soc/me.h
similarity index 100%
rename from src/northbridge/intel/broadwell/include/soc/me.h
rename to src/southbridge/intel/wildcatpoint/include/soc/me.h
diff --git a/src/northbridge/intel/broadwell/include/soc/nvs.h b/src/southbridge/intel/wildcatpoint/include/soc/nvs.h
similarity index 100%
rename from src/northbridge/intel/broadwell/include/soc/nvs.h
rename to src/southbridge/intel/wildcatpoint/include/soc/nvs.h
diff --git a/src/northbridge/intel/broadwell/include/soc/pch.h b/src/southbridge/intel/wildcatpoint/include/soc/pch.h
similarity index 100%
rename from src/northbridge/intel/broadwell/include/soc/pch.h
rename to src/southbridge/intel/wildcatpoint/include/soc/pch.h
diff --git a/src/northbridge/intel/broadwell/include/soc/pm.h b/src/southbridge/intel/wildcatpoint/include/soc/pm.h
similarity index 100%
rename from src/northbridge/intel/broadwell/include/soc/pm.h
rename to src/southbridge/intel/wildcatpoint/include/soc/pm.h
diff --git a/src/northbridge/intel/broadwell/include/soc/rcba.h b/src/southbridge/intel/wildcatpoint/include/soc/rcba.h
similarity index 100%
rename from src/northbridge/intel/broadwell/include/soc/rcba.h
rename to src/southbridge/intel/wildcatpoint/include/soc/rcba.h
diff --git a/src/northbridge/intel/broadwell/include/soc/sata.h b/src/southbridge/intel/wildcatpoint/include/soc/sata.h
similarity index 100%
rename from src/northbridge/intel/broadwell/include/soc/sata.h
rename to src/southbridge/intel/wildcatpoint/include/soc/sata.h
diff --git a/src/northbridge/intel/broadwell/include/soc/serialio.h b/src/southbridge/intel/wildcatpoint/include/soc/serialio.h
similarity index 100%
rename from src/northbridge/intel/broadwell/include/soc/serialio.h
rename to src/southbridge/intel/wildcatpoint/include/soc/serialio.h
diff --git a/src/northbridge/intel/broadwell/include/soc/spi.h b/src/southbridge/intel/wildcatpoint/include/soc/spi.h
similarity index 100%
rename from src/northbridge/intel/broadwell/include/soc/spi.h
rename to src/southbridge/intel/wildcatpoint/include/soc/spi.h
diff --git a/src/northbridge/intel/broadwell/include/soc/xhci.h b/src/southbridge/intel/wildcatpoint/include/soc/xhci.h
similarity index 100%
rename from src/northbridge/intel/broadwell/include/soc/xhci.h
rename to src/southbridge/intel/wildcatpoint/include/soc/xhci.h

From 7240bbabe9f87d795ec3e64ad0993507d26b224b Mon Sep 17 00:00:00 2001
From: Angel Pons <th3fanbus@gmail.com>
Date: Mon, 23 Feb 2026 21:56:07 +0100
Subject: [PATCH 3588/3886] nb/intel/broadwell/acpi.c: Drop unneeded includes

Tested with BUILD_TIMELESS=1, Purism Librem 15 v2 remains identical.

Change-Id: Iac166dd1a59e6e35101dd7076cc3f96d33d4eb64
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91399
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/northbridge/intel/broadwell/acpi.c | 12 ++----------
 1 file changed, 2 insertions(+), 10 deletions(-)

diff --git a/src/northbridge/intel/broadwell/acpi.c b/src/northbridge/intel/broadwell/acpi.c
index 7ca60c1f59..691bcdec31 100644
--- a/src/northbridge/intel/broadwell/acpi.c
+++ b/src/northbridge/intel/broadwell/acpi.c
@@ -2,23 +2,15 @@
 
 #include <acpi/acpi.h>
 #include <acpi/acpi_gnvs.h>
-#include <acpi/acpigen.h>
 #include <arch/ioapic.h>
-#include <arch/smp/mpspec.h>
-#include <cpu/intel/haswell/haswell.h>
-#include <device/pci_ops.h>
 #include <console/console.h>
 #include <device/device.h>
-#include <types.h>
-#include <cpu/intel/turbo.h>
+#include <device/pci_ops.h>
 #include <soc/acpi.h>
 #include <soc/device_nvs.h>
-#include <soc/iomap.h>
-#include <soc/lpc.h>
 #include <soc/pci_devs.h>
-#include <soc/pm.h>
 #include <soc/systemagent.h>
-#include <northbridge/intel/broadwell/chip.h>
+#include <types.h>
 
 static unsigned long acpi_fill_dmar(unsigned long current)
 {

From 3d4f2efcf759626c42fa761d34fd79998b8aabde Mon Sep 17 00:00:00 2001
From: Angel Pons <th3fanbus@gmail.com>
Date: Mon, 23 Feb 2026 22:03:33 +0100
Subject: [PATCH 3589/3886] nb/intel/broadwell/bootblock.c: Use Haswell's file

Tested with BUILD_TIMELESS=1, Purism Librem 15 v2 remains identical.

Change-Id: Ie583224b4cfc4116e6cdb511793b8c39e8bf679e
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91400
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/northbridge/intel/broadwell/Makefile.mk |  2 +-
 src/northbridge/intel/broadwell/bootblock.c | 34 ---------------------
 2 files changed, 1 insertion(+), 35 deletions(-)
 delete mode 100644 src/northbridge/intel/broadwell/bootblock.c

diff --git a/src/northbridge/intel/broadwell/Makefile.mk b/src/northbridge/intel/broadwell/Makefile.mk
index 16576371ae..e067285881 100644
--- a/src/northbridge/intel/broadwell/Makefile.mk
+++ b/src/northbridge/intel/broadwell/Makefile.mk
@@ -2,7 +2,7 @@
 
 ifeq ($(CONFIG_SOC_INTEL_BROADWELL),y)
 
-bootblock-y += bootblock.c
+bootblock-y += ../haswell/bootblock.c
 
 romstage-y += early_init.c
 romstage-y += raminit.c
diff --git a/src/northbridge/intel/broadwell/bootblock.c b/src/northbridge/intel/broadwell/bootblock.c
deleted file mode 100644
index 8c851cac5d..0000000000
--- a/src/northbridge/intel/broadwell/bootblock.c
+++ /dev/null
@@ -1,34 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <arch/bootblock.h>
-#include <assert.h>
-#include <device/pci_ops.h>
-#include <soc/pci_devs.h>
-#include <soc/systemagent.h>
-
-static uint32_t encode_pciexbar_length(void)
-{
-	switch (CONFIG_ECAM_MMCONF_BUS_NUMBER) {
-		case 256: return 0 << 1;
-		case 128: return 1 << 1;
-		case  64: return 2 << 1;
-		default:  return dead_code_t(uint32_t);
-	}
-}
-
-void bootblock_early_northbridge_init(void)
-{
-	/*
-	 * The "io" variant of the config access is explicitly used to setup the
-	 * PCIEXBAR because CONFIG(ECAM_MMCONF_SUPPORT) is set to true. That way, all
-	 * subsequent non-explicit config accesses use MCFG. This code also assumes
-	 * that bootblock_northbridge_init() is the first thing called in the non-asm
-	 * boot block code. The final assumption is that no assembly code is using the
-	 * CONFIG(ECAM_MMCONF_SUPPORT) option to do PCI config accesses.
-	 *
-	 * The PCIEXBAR is assumed to live in the memory mapped IO space under 4GiB.
-	 */
-	const uint32_t reg = CONFIG_ECAM_MMCONF_BASE_ADDRESS | encode_pciexbar_length() | 1;
-	pci_io_write_config32(HOST_BRIDGE, PCIEXBAR + 4, 0);
-	pci_io_write_config32(HOST_BRIDGE, PCIEXBAR, reg);
-}

From 35694d2ea491c2009dcc8e335c2588848258484e Mon Sep 17 00:00:00 2001
From: Angel Pons <th3fanbus@gmail.com>
Date: Mon, 23 Feb 2026 22:08:25 +0100
Subject: [PATCH 3590/3886] nb/intel/broadwell: Move device NVS to southbridge

Device NVS is only used in southbridge code. Also move the platform.asl
file since it is mostly about southbridge stuff.

Tested with BUILD_TIMELESS=1, Purism Librem 15 v2 remains identical.

Change-Id: Ia0d301f6b77f7084a6d1dfe1238693c76c62ef7a
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91401
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/google/auron/dsdt.asl                             | 2 +-
 src/mainboard/google/jecht/dsdt.asl                             | 2 +-
 src/mainboard/hp/elitebook_820_g2/dsdt.asl                      | 2 +-
 src/mainboard/intel/wtm2/dsdt.asl                               | 2 +-
 src/mainboard/purism/librem_bdw/dsdt.asl                        | 2 +-
 .../intel/wildcatpoint}/acpi/device_nvs.asl                     | 0
 .../intel/wildcatpoint}/acpi/platform.asl                       | 2 +-
 .../intel/wildcatpoint}/include/soc/device_nvs.h                | 0
 8 files changed, 6 insertions(+), 6 deletions(-)
 rename src/{northbridge/intel/broadwell => southbridge/intel/wildcatpoint}/acpi/device_nvs.asl (100%)
 rename src/{northbridge/intel/broadwell => southbridge/intel/wildcatpoint}/acpi/platform.asl (90%)
 rename src/{northbridge/intel/broadwell => southbridge/intel/wildcatpoint}/include/soc/device_nvs.h (100%)

diff --git a/src/mainboard/google/auron/dsdt.asl b/src/mainboard/google/auron/dsdt.asl
index 9505158f3c..eebeeeacee 100644
--- a/src/mainboard/google/auron/dsdt.asl
+++ b/src/mainboard/google/auron/dsdt.asl
@@ -11,7 +11,7 @@ DefinitionBlock(
 )
 {
 	#include <acpi/dsdt_top.asl>
-	#include <northbridge/intel/broadwell/acpi/platform.asl>
+	#include <southbridge/intel/wildcatpoint/acpi/platform.asl>
 
 	// Thermal handler
 	#include "acpi/thermal.asl"
diff --git a/src/mainboard/google/jecht/dsdt.asl b/src/mainboard/google/jecht/dsdt.asl
index 8e76080411..62c8b58fe6 100644
--- a/src/mainboard/google/jecht/dsdt.asl
+++ b/src/mainboard/google/jecht/dsdt.asl
@@ -19,7 +19,7 @@ DefinitionBlock(
 
 	// global NVS and variables
 	#include <southbridge/intel/wildcatpoint/acpi/globalnvs.asl>
-	#include <northbridge/intel/broadwell/acpi/device_nvs.asl>
+	#include <southbridge/intel/wildcatpoint/acpi/device_nvs.asl>
 
 	// CPU
 	#include <cpu/intel/common/acpi/cpu.asl>
diff --git a/src/mainboard/hp/elitebook_820_g2/dsdt.asl b/src/mainboard/hp/elitebook_820_g2/dsdt.asl
index bb744911a3..95012ce708 100644
--- a/src/mainboard/hp/elitebook_820_g2/dsdt.asl
+++ b/src/mainboard/hp/elitebook_820_g2/dsdt.asl
@@ -18,7 +18,7 @@ DefinitionBlock(
 	#include <soc/intel/common/acpi/acpi_wake_source.asl>
 
 	#include <southbridge/intel/wildcatpoint/acpi/globalnvs.asl>
-	#include <northbridge/intel/broadwell/acpi/device_nvs.asl>
+	#include <southbridge/intel/wildcatpoint/acpi/device_nvs.asl>
 	#include <cpu/intel/common/acpi/cpu.asl>
 	#include <southbridge/intel/common/acpi/sleepstates.asl>
 
diff --git a/src/mainboard/intel/wtm2/dsdt.asl b/src/mainboard/intel/wtm2/dsdt.asl
index efa50eb92d..764d442d5f 100644
--- a/src/mainboard/intel/wtm2/dsdt.asl
+++ b/src/mainboard/intel/wtm2/dsdt.asl
@@ -19,7 +19,7 @@ DefinitionBlock(
 
 	// global NVS and variables
 	#include <southbridge/intel/wildcatpoint/acpi/globalnvs.asl>
-	#include <northbridge/intel/broadwell/acpi/device_nvs.asl>
+	#include <southbridge/intel/wildcatpoint/acpi/device_nvs.asl>
 
 	// CPU
 	#include <cpu/intel/common/acpi/cpu.asl>
diff --git a/src/mainboard/purism/librem_bdw/dsdt.asl b/src/mainboard/purism/librem_bdw/dsdt.asl
index 7439e941de..18719a8f1e 100644
--- a/src/mainboard/purism/librem_bdw/dsdt.asl
+++ b/src/mainboard/purism/librem_bdw/dsdt.asl
@@ -11,7 +11,7 @@ DefinitionBlock(
 )
 {
 	#include <acpi/dsdt_top.asl>
-	#include <northbridge/intel/broadwell/acpi/platform.asl>
+	#include <southbridge/intel/wildcatpoint/acpi/platform.asl>
 	#include <southbridge/intel/wildcatpoint/acpi/globalnvs.asl>
 	#include <cpu/intel/common/acpi/cpu.asl>
 
diff --git a/src/northbridge/intel/broadwell/acpi/device_nvs.asl b/src/southbridge/intel/wildcatpoint/acpi/device_nvs.asl
similarity index 100%
rename from src/northbridge/intel/broadwell/acpi/device_nvs.asl
rename to src/southbridge/intel/wildcatpoint/acpi/device_nvs.asl
diff --git a/src/northbridge/intel/broadwell/acpi/platform.asl b/src/southbridge/intel/wildcatpoint/acpi/platform.asl
similarity index 90%
rename from src/northbridge/intel/broadwell/acpi/platform.asl
rename to src/southbridge/intel/wildcatpoint/acpi/platform.asl
index 3a57f995d1..af60f5cee7 100644
--- a/src/northbridge/intel/broadwell/acpi/platform.asl
+++ b/src/southbridge/intel/wildcatpoint/acpi/platform.asl
@@ -1,6 +1,6 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
-#include <northbridge/intel/broadwell/acpi/device_nvs.asl>
+#include <southbridge/intel/wildcatpoint/acpi/device_nvs.asl>
 #include <southbridge/intel/common/acpi/platform.asl>
 
 /*
diff --git a/src/northbridge/intel/broadwell/include/soc/device_nvs.h b/src/southbridge/intel/wildcatpoint/include/soc/device_nvs.h
similarity index 100%
rename from src/northbridge/intel/broadwell/include/soc/device_nvs.h
rename to src/southbridge/intel/wildcatpoint/include/soc/device_nvs.h

From 958bc5cdffa6b0a4e4824bad02861f9907636eb1 Mon Sep 17 00:00:00 2001
From: Angel Pons <th3fanbus@gmail.com>
Date: Mon, 23 Feb 2026 22:13:16 +0100
Subject: [PATCH 3591/3886] nb/intel/broadwell: Move `size_of_dnvs()` to
 southbridge

Device NVS is only used in southbridge code. This change is
non-reproducible.

Change-Id: I60ce9a80d6e3e0ce0c13037d4caae473d3d092a9
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91402
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/northbridge/intel/broadwell/acpi.c         |  7 -------
 src/southbridge/intel/wildcatpoint/Makefile.mk |  1 +
 src/southbridge/intel/wildcatpoint/acpi.c      | 10 ++++++++++
 3 files changed, 11 insertions(+), 7 deletions(-)
 create mode 100644 src/southbridge/intel/wildcatpoint/acpi.c

diff --git a/src/northbridge/intel/broadwell/acpi.c b/src/northbridge/intel/broadwell/acpi.c
index 691bcdec31..453c77a235 100644
--- a/src/northbridge/intel/broadwell/acpi.c
+++ b/src/northbridge/intel/broadwell/acpi.c
@@ -1,13 +1,11 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
 #include <acpi/acpi.h>
-#include <acpi/acpi_gnvs.h>
 #include <arch/ioapic.h>
 #include <console/console.h>
 #include <device/device.h>
 #include <device/pci_ops.h>
 #include <soc/acpi.h>
-#include <soc/device_nvs.h>
 #include <soc/pci_devs.h>
 #include <soc/systemagent.h>
 #include <types.h>
@@ -87,8 +85,3 @@ unsigned long northbridge_write_acpi_tables(const struct device *const dev,
 
 	return current;
 }
-
-size_t size_of_dnvs(void)
-{
-	return sizeof(struct device_nvs);
-}
diff --git a/src/southbridge/intel/wildcatpoint/Makefile.mk b/src/southbridge/intel/wildcatpoint/Makefile.mk
index ec54db4632..59f48805ce 100644
--- a/src/southbridge/intel/wildcatpoint/Makefile.mk
+++ b/src/southbridge/intel/wildcatpoint/Makefile.mk
@@ -4,6 +4,7 @@ ifeq ($(CONFIG_SOUTHBRIDGE_INTEL_WILDCATPOINT),y)
 
 bootblock-y += bootblock.c
 
+ramstage-y += acpi.c
 ramstage-y += adsp.c
 romstage-y += early_pch.c
 ramstage-$(CONFIG_ELOG) += elog.c
diff --git a/src/southbridge/intel/wildcatpoint/acpi.c b/src/southbridge/intel/wildcatpoint/acpi.c
new file mode 100644
index 0000000000..091bb50319
--- /dev/null
+++ b/src/southbridge/intel/wildcatpoint/acpi.c
@@ -0,0 +1,10 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <acpi/acpi_gnvs.h>
+#include <soc/device_nvs.h>
+#include <types.h>
+
+size_t size_of_dnvs(void)
+{
+	return sizeof(struct device_nvs);
+}

From 3e89a234ef527b20469ad2b4161e02bab4379372 Mon Sep 17 00:00:00 2001
From: Angel Pons <th3fanbus@gmail.com>
Date: Mon, 23 Feb 2026 22:15:29 +0100
Subject: [PATCH 3592/3886] nb/intel/broadwell/acpi.c: Align with Haswell

The idea is to use Haswell's acpi.c file in the next commit, and this
little difference affects reproducibility.

Change-Id: Ib2641586fbb9e8ed175eeca0bd665057f5049c0e
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91403
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
---
 src/northbridge/intel/broadwell/acpi.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/northbridge/intel/broadwell/acpi.c b/src/northbridge/intel/broadwell/acpi.c
index 453c77a235..5da7bd3476 100644
--- a/src/northbridge/intel/broadwell/acpi.c
+++ b/src/northbridge/intel/broadwell/acpi.c
@@ -12,7 +12,7 @@
 
 static unsigned long acpi_fill_dmar(unsigned long current)
 {
-	struct device *const igfx_dev = pcidev_path_on_root(SA_DEVFN_IGD);
+	struct device *const igfx_dev = pcidev_on_root(2, 0);
 	const u32 gfxvtbar = mchbar_read32(GFXVTBAR) & ~0xfff;
 	const u32 vtvc0bar = mchbar_read32(VTVC0BAR) & ~0xfff;
 	const bool gfxvten = mchbar_read32(GFXVTBAR) & 0x1;

From bacb55e348675235adab3c750c227d51910388e2 Mon Sep 17 00:00:00 2001
From: Angel Pons <th3fanbus@gmail.com>
Date: Mon, 23 Feb 2026 22:17:32 +0100
Subject: [PATCH 3593/3886] nb/intel/broadwell/acpi.c: Use Haswell's file

Tested with BUILD_TIMELESS=1, Purism Librem 15 v2 remains identical.

Change-Id: Ie44227273210c3074343e1d9ccadb63fc2a931d2
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91404
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/northbridge/intel/broadwell/Makefile.mk |  2 +-
 src/northbridge/intel/broadwell/acpi.c      | 87 ---------------------
 2 files changed, 1 insertion(+), 88 deletions(-)
 delete mode 100644 src/northbridge/intel/broadwell/acpi.c

diff --git a/src/northbridge/intel/broadwell/Makefile.mk b/src/northbridge/intel/broadwell/Makefile.mk
index e067285881..ce037157e2 100644
--- a/src/northbridge/intel/broadwell/Makefile.mk
+++ b/src/northbridge/intel/broadwell/Makefile.mk
@@ -10,7 +10,7 @@ romstage-y += report_platform.c
 romstage-y += romstage.c
 romstage-$(CONFIG_HAVE_SPD_IN_CBFS) += spd.c
 
-ramstage-y += acpi.c
+ramstage-y += ../haswell/acpi.c
 ramstage-y += finalize.c
 ramstage-y += gma.c
 ramstage-y += memmap.c
diff --git a/src/northbridge/intel/broadwell/acpi.c b/src/northbridge/intel/broadwell/acpi.c
deleted file mode 100644
index 5da7bd3476..0000000000
--- a/src/northbridge/intel/broadwell/acpi.c
+++ /dev/null
@@ -1,87 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <acpi/acpi.h>
-#include <arch/ioapic.h>
-#include <console/console.h>
-#include <device/device.h>
-#include <device/pci_ops.h>
-#include <soc/acpi.h>
-#include <soc/pci_devs.h>
-#include <soc/systemagent.h>
-#include <types.h>
-
-static unsigned long acpi_fill_dmar(unsigned long current)
-{
-	struct device *const igfx_dev = pcidev_on_root(2, 0);
-	const u32 gfxvtbar = mchbar_read32(GFXVTBAR) & ~0xfff;
-	const u32 vtvc0bar = mchbar_read32(VTVC0BAR) & ~0xfff;
-	const bool gfxvten = mchbar_read32(GFXVTBAR) & 0x1;
-	const bool vtvc0en = mchbar_read32(VTVC0BAR) & 0x1;
-
-	/* iGFX has to be enabled; GFXVTBAR set, enabled, in 32-bit space */
-	const bool emit_igd =
-			igfx_dev && igfx_dev->enabled &&
-			gfxvtbar && gfxvten &&
-			!mchbar_read32(GFXVTBAR + 4);
-
-	/* First, add DRHD entries */
-	if (emit_igd) {
-		const unsigned long tmp = current;
-
-		current += acpi_create_dmar_drhd_4k(current, 0, 0, gfxvtbar);
-		current += acpi_create_dmar_ds_pci(current, 0, 2, 0);
-
-		acpi_dmar_drhd_fixup(tmp, current);
-	}
-
-	/* VTVC0BAR has to be set, enabled, and in 32-bit space */
-	if (vtvc0bar && vtvc0en && !mchbar_read32(VTVC0BAR + 4)) {
-		const unsigned long tmp = current;
-		current += acpi_create_dmar_drhd_4k(current,
-				DRHD_INCLUDE_PCI_ALL, 0, vtvc0bar);
-		current += acpi_create_dmar_ds_ioapic_from_hw(current,
-				IO_APIC_ADDR, PCH_IOAPIC_PCI_BUS, PCH_IOAPIC_PCI_SLOT, 0);
-		size_t i;
-		for (i = 0; i < 8; ++i)
-			current += acpi_create_dmar_ds_msi_hpet(current,
-					0, PCH_HPET_PCI_BUS,
-					PCH_HPET_PCI_SLOT, i);
-		acpi_dmar_drhd_fixup(tmp, current);
-	}
-
-	/* Then, add RMRR entries after all DRHD entries */
-	if (emit_igd) {
-		const unsigned long tmp = current;
-
-		const struct device *sa_dev = pcidev_on_root(0, 0);
-
-		/* Bit 0 is lock bit, not part of address */
-		const u32 tolud = pci_read_config32(sa_dev, TOLUD) & ~1;
-		const u32 bgsm  = pci_read_config32(sa_dev,  BGSM) & ~1;
-
-		current += acpi_create_dmar_rmrr(current, 0, bgsm, tolud - 1);
-		current += acpi_create_dmar_ds_pci(current, 0, 2, 0);
-		acpi_dmar_rmrr_fixup(tmp, current);
-	}
-
-	return current;
-}
-
-unsigned long northbridge_write_acpi_tables(const struct device *const dev,
-					    unsigned long current,
-					    struct acpi_rsdp *const rsdp)
-{
-	/* Create DMAR table only if we have VT-d capability. */
-	const u32 capid0_a = pci_read_config32(dev, CAPID0_A);
-	if (capid0_a & VTD_DISABLE)
-		return current;
-
-	acpi_dmar_t *const dmar = (acpi_dmar_t *)current;
-	printk(BIOS_DEBUG, "ACPI:    * DMAR\n");
-	acpi_create_dmar(dmar, DMAR_INTR_REMAP, acpi_fill_dmar);
-	current += dmar->header.length;
-	current = acpi_align_current(current);
-	acpi_add_table(rsdp, dmar);
-
-	return current;
-}

From fec793e01dd9dd9ccebbb6e82e20d5a6e79b53a0 Mon Sep 17 00:00:00 2001
From: Angel Pons <th3fanbus@gmail.com>
Date: Fri, 27 Feb 2026 21:00:58 +0100
Subject: [PATCH 3594/3886] sb/intel/wildcatpoint/acpi: Add CID for GPIO device

Wildcat Point's GPIOs work the same as Lynx Point LP's GPIOs.

Change-Id: I64963937a5b40bcab605acb826567d63af512427
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91468
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/southbridge/intel/wildcatpoint/acpi/gpio.asl | 1 +
 1 file changed, 1 insertion(+)

diff --git a/src/southbridge/intel/wildcatpoint/acpi/gpio.asl b/src/southbridge/intel/wildcatpoint/acpi/gpio.asl
index bd9f581cf6..48167bfae5 100644
--- a/src/southbridge/intel/wildcatpoint/acpi/gpio.asl
+++ b/src/southbridge/intel/wildcatpoint/acpi/gpio.asl
@@ -13,6 +13,7 @@ Device (GPIO)
 		// LynxPoint-LP
 		Return ("INT33C7")
 	}
+	Name (_CID, "INT33C7")
 	Name (_UID, 1)
 
 	Name (RBUF, ResourceTemplate ()

From e160f3c50695f7d46fdcad525a10dd08aa3a6114 Mon Sep 17 00:00:00 2001
From: Jeremy Compostella <jeremy.compostella@intel.com>
Date: Fri, 13 Feb 2026 23:35:05 -0800
Subject: [PATCH 3595/3886] soc/intel/common/feature: Add common PMC lockdown
 driver

This commit introduces common PMC (Power Management Controller) lockdown
infrastructure to consolidate duplicate lockdown code across multiple
Intel platform generations (Alder Lake, Meteor Lake, and Panther Lake).

Key features implemented:
- PMSYNC TPR configuration and locking
- ABASE and sleep stretching policy locks
- SMI locking (when coreboot handles chipset lockdown)
- ST_FDIS_LOCK, SSML, and PM_CFG register configuration
- IOSF Primary Trunk Clock Gating
- PMC IPC notification for BIOS reset and PCI enumeration

Platform-specific differences are handled through the PMC_FDIS_LOCK_REG
define that each SoC provides in its soc/pmc.h header:
- Alder Lake: PMC_FDIS_LOCK_REG = ST_PG_FDIS1 (0x1e20)
- Meteor Lake: PMC_FDIS_LOCK_REG = GEN_PMCON_B (0x1024)
- Panther Lake: PMC_FDIS_LOCK_REG = GEN_PMCON_B (0x1024)

This consolidation eliminates ~150 lines of duplicated code, ensures
consistent lockdown behavior across platforms, and simplifies
maintenance.

Change-Id: I215d834b66f7cb0f50f804eaaff3ea0e60d4340f
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91204
Reviewed-by: Jakub "Kuba" Czapiga <czapiga@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/soc/intel/common/feature/lockdown/Kconfig |  8 +++
 .../intel/common/feature/lockdown/Makefile.mk |  3 +
 .../intel/common/feature/lockdown/lockdown.c  | 55 +++++++++++++++++++
 3 files changed, 66 insertions(+)
 create mode 100644 src/soc/intel/common/feature/lockdown/Kconfig
 create mode 100644 src/soc/intel/common/feature/lockdown/Makefile.mk
 create mode 100644 src/soc/intel/common/feature/lockdown/lockdown.c

diff --git a/src/soc/intel/common/feature/lockdown/Kconfig b/src/soc/intel/common/feature/lockdown/Kconfig
new file mode 100644
index 0000000000..75a59b0d62
--- /dev/null
+++ b/src/soc/intel/common/feature/lockdown/Kconfig
@@ -0,0 +1,8 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
+config SOC_INTEL_COMMON_FEATURE_LOCKDOWN
+	bool
+	help
+	  Include common PMC lockdown driver for Intel SoCs. This driver
+	  consolidates the nearly identical PMC lockdown implementations
+	  across multiple Intel platform generations.
diff --git a/src/soc/intel/common/feature/lockdown/Makefile.mk b/src/soc/intel/common/feature/lockdown/Makefile.mk
new file mode 100644
index 0000000000..6a39d8a309
--- /dev/null
+++ b/src/soc/intel/common/feature/lockdown/Makefile.mk
@@ -0,0 +1,3 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
+ramstage-$(CONFIG_SOC_INTEL_COMMON_FEATURE_LOCKDOWN) += lockdown.c
diff --git a/src/soc/intel/common/feature/lockdown/lockdown.c b/src/soc/intel/common/feature/lockdown/lockdown.c
new file mode 100644
index 0000000000..5da2bd93bd
--- /dev/null
+++ b/src/soc/intel/common/feature/lockdown/lockdown.c
@@ -0,0 +1,55 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <device/mmio.h>
+#include <intelblocks/cfg.h>
+#include <intelblocks/pcr.h>
+#include <intelblocks/pmclib.h>
+#include <intelpch/lockdown.h>
+#include <soc/pcr_ids.h>
+#include <soc/pm.h>
+#include <soc/pmc.h>
+#include <stdint.h>
+
+/* PCR PSTH Control Register */
+#define PCR_PSTH_CTRLREG		0x1d00
+#define PSTH_CTRLREG_IOSFPTCGE		BIT(2)
+
+static void pmc_lockdown_config(int chipset_lockdown)
+{
+	uint8_t *pmcbase = pmc_mmio_regs();
+
+	/* PMSYNC */
+	setbits32(pmcbase + PMSYNC_TPR_CFG, PCH2CPU_TPR_CFG_LOCK);
+	/* Lock down ABASE and sleep stretching policy */
+	setbits32(pmcbase + GEN_PMCON_B, SLP_STR_POL_LOCK | ACPI_BASE_LOCK);
+
+	if (chipset_lockdown == CHIPSET_LOCKDOWN_COREBOOT)
+		setbits32(pmcbase + GEN_PMCON_B, SMI_LOCK);
+
+	if (!CONFIG(USE_FSP_NOTIFY_PHASE_POST_PCI_ENUM)) {
+		setbits32(pmcbase + PMC_FDIS_LOCK_REG, ST_FDIS_LOCK);
+		setbits32(pmcbase + SSML, SSML_SSL_EN);
+		setbits32(pmcbase + PM_CFG, PM_CFG_DBG_MODE_LOCK |
+					 PM_CFG_XRAM_READ_DISABLE);
+	}
+
+	/* Send PMC IPC to inform about both BIOS Reset and PCI enumeration done */
+	pmc_send_bios_reset_pci_enum_done();
+}
+
+static void soc_die_lockdown_cfg(void)
+{
+	if (CONFIG(USE_FSP_NOTIFY_PHASE_POST_PCI_ENUM))
+		return;
+
+	/* Enable IOSF Primary Trunk Clock Gating */
+	pcr_rmw32(PID_PSTH, PCR_PSTH_CTRLREG, ~0, PSTH_CTRLREG_IOSFPTCGE);
+}
+
+void soc_lockdown_config(int chipset_lockdown)
+{
+	/* PMC lock down configuration */
+	pmc_lockdown_config(chipset_lockdown);
+	/* SOC/PCH die lock down configuration */
+	soc_die_lockdown_cfg();
+}

From 19fe81f08f5eff7377b0f8595a1763874f0aeec3 Mon Sep 17 00:00:00 2001
From: Jeremy Compostella <jeremy.compostella@intel.com>
Date: Fri, 13 Feb 2026 23:35:32 -0800
Subject: [PATCH 3596/3886] soc/intel/alderlake: Switch to common PMC lockdown
 driver

Replace platform-specific lockdown.c with the common PMC lockdown
driver introduced in the previous commit.

Changes:
- Remove src/soc/intel/alderlake/lockdown.c
- Add PMC_FDIS_LOCK_REG define pointing to ST_PG_FDIS1 in soc/pmc.h
- Enable SOC_INTEL_COMMON_FEATURE_PMC_LOCKDOWN in Kconfig
- Update Makefile.mk to remove lockdown.c from build

Alder Lake uses the ST_PG_FDIS1 register (0x1e20) for ST_FDIS_LOCK,
which differs from newer platforms that use GEN_PMCON_B. This
difference is handled through the PMC_FDIS_LOCK_REG define.

Change-Id: Ic80aca618dcbe5a4fef54f4802e6f4ce6f4ebd44
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91205
Reviewed-by: Huang, Cliff <cliff.huang@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/soc/intel/alderlake/Kconfig           |  1 +
 src/soc/intel/alderlake/Makefile.mk       |  1 -
 src/soc/intel/alderlake/include/soc/pmc.h |  3 ++
 src/soc/intel/alderlake/lockdown.c        | 60 -----------------------
 4 files changed, 4 insertions(+), 61 deletions(-)
 delete mode 100644 src/soc/intel/alderlake/lockdown.c

diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig
index a925cf09a0..9198377291 100644
--- a/src/soc/intel/alderlake/Kconfig
+++ b/src/soc/intel/alderlake/Kconfig
@@ -87,6 +87,7 @@ config SOC_INTEL_ALDERLAKE
 	select SOC_INTEL_COMMON_FEATURE
 	select SOC_INTEL_COMMON_FEATURE_ESPI
 	select SOC_INTEL_COMMON_FEATURE_GSPI_DEVFN
+	select SOC_INTEL_COMMON_FEATURE_LOCKDOWN
 	select SOC_INTEL_COMMON_FEATURE_PMUTIL
 	select SOC_INTEL_COMMON_FEATURE_SMIHANDLER
 	select SOC_INTEL_COMMON_FEATURE_SOUNDWIRE
diff --git a/src/soc/intel/alderlake/Makefile.mk b/src/soc/intel/alderlake/Makefile.mk
index 45c374849d..cbfa1ebda5 100644
--- a/src/soc/intel/alderlake/Makefile.mk
+++ b/src/soc/intel/alderlake/Makefile.mk
@@ -25,7 +25,6 @@ ramstage-y += finalize.c
 ramstage-y += fsp_params.c
 ramstage-y += graphics.c
 ramstage-y += hsphy.c
-ramstage-y += lockdown.c
 ramstage-y += p2sb.c
 ramstage-y += pcie_rp.c
 ramstage-y += pmc.c
diff --git a/src/soc/intel/alderlake/include/soc/pmc.h b/src/soc/intel/alderlake/include/soc/pmc.h
index 81a99e00ec..aa7df21bee 100644
--- a/src/soc/intel/alderlake/include/soc/pmc.h
+++ b/src/soc/intel/alderlake/include/soc/pmc.h
@@ -168,6 +168,9 @@ extern struct device_operations pmc_ops;
 #define ST_PG_FDIS1			0x1e20
 #define   ST_FDIS_LOCK			(1 << 31)
 
+/* PMC lockdown configuration register for ST_FDIS_LOCK */
+#define PMC_FDIS_LOCK_REG		ST_PG_FDIS1
+
 #define  SCIS_IRQ9			0
 #define  SCIS_IRQ10			1
 #define  SCIS_IRQ11			2
diff --git a/src/soc/intel/alderlake/lockdown.c b/src/soc/intel/alderlake/lockdown.c
deleted file mode 100644
index 59fa065b3d..0000000000
--- a/src/soc/intel/alderlake/lockdown.c
+++ /dev/null
@@ -1,60 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-/*
- * This file is created based on Intel Alder Lake Processor PCH Datasheet
- * Document number: 621483
- * Chapter number: 4
- */
-
-#include <device/mmio.h>
-#include <intelblocks/cfg.h>
-#include <intelblocks/pcr.h>
-#include <intelblocks/pmclib.h>
-#include <intelpch/lockdown.h>
-#include <soc/pcr_ids.h>
-#include <soc/pm.h>
-#include <stdint.h>
-
-/* PCR PSTH Control Register */
-#define PCR_PSTH_CTRLREG		0x1d00
-#define   PSTH_CTRLREG_IOSFPTCGE	(1 << 2)
-
-static void pmc_lockdown_cfg(int chipset_lockdown)
-{
-	uint8_t *pmcbase = pmc_mmio_regs();
-
-	/* PMSYNC */
-	setbits32(pmcbase + PMSYNC_TPR_CFG, PCH2CPU_TPR_CFG_LOCK);
-	/* Lock down ABASE and sleep stretching policy */
-	setbits32(pmcbase + GEN_PMCON_B, SLP_STR_POL_LOCK | ACPI_BASE_LOCK);
-
-	if (chipset_lockdown == CHIPSET_LOCKDOWN_COREBOOT)
-		setbits32(pmcbase + GEN_PMCON_B, SMI_LOCK);
-
-	if (!CONFIG(USE_FSP_NOTIFY_PHASE_POST_PCI_ENUM)) {
-		setbits32(pmcbase + ST_PG_FDIS1, ST_FDIS_LOCK);
-		setbits32(pmcbase + SSML, SSML_SSL_EN);
-		setbits32(pmcbase + PM_CFG, PM_CFG_DBG_MODE_LOCK |
-					 PM_CFG_XRAM_READ_DISABLE);
-	}
-
-	/* Send PMC IPC to inform about both BIOS Reset and PCI enumeration done */
-	pmc_send_bios_reset_pci_enum_done();
-}
-
-static void pch_lockdown_cfg(void)
-{
-	if (CONFIG(USE_FSP_NOTIFY_PHASE_POST_PCI_ENUM))
-		return;
-
-	/* Enable IOSF Primary Trunk Clock Gating */
-	pcr_rmw32(PID_PSTH, PCR_PSTH_CTRLREG, ~0, PSTH_CTRLREG_IOSFPTCGE);
-}
-
-void soc_lockdown_config(int chipset_lockdown)
-{
-	/* PMC lock down configuration */
-	pmc_lockdown_cfg(chipset_lockdown);
-	/* PCH lock down configuration */
-	pch_lockdown_cfg();
-}

From 4da2622964a3fab05674f2514cdb0a727e5f5ea8 Mon Sep 17 00:00:00 2001
From: Jeremy Compostella <jeremy.compostella@intel.com>
Date: Fri, 13 Feb 2026 23:35:41 -0800
Subject: [PATCH 3597/3886] soc/intel/meteorlake: Switch to common PMC lockdown
 driver

Replace platform-specific lockdown.c with the common PMC lockdown
driver.

Changes:
- Remove src/soc/intel/meteorlake/lockdown.c
- Add PMC_FDIS_LOCK_REG define pointing to GEN_PMCON_B in soc/pmc.h
- Enable SOC_INTEL_COMMON_FEATURE_LOCKDOWN in Kconfig
- Update Makefile.mk to remove lockdown.c from build

Meteor Lake uses GEN_PMCON_B for ST_FDIS_LOCK (bit 21), the same
approach as Panther Lake.

Change-Id: Iecccc482f04d85cfec738dd57dc1473eaf82cfcc
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91206
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Huang, Cliff <cliff.huang@intel.com>
---
 src/soc/intel/meteorlake/Kconfig           |  1 +
 src/soc/intel/meteorlake/Makefile.mk       |  1 -
 src/soc/intel/meteorlake/include/soc/pmc.h |  3 ++
 src/soc/intel/meteorlake/lockdown.c        | 54 ----------------------
 4 files changed, 4 insertions(+), 55 deletions(-)
 delete mode 100644 src/soc/intel/meteorlake/lockdown.c

diff --git a/src/soc/intel/meteorlake/Kconfig b/src/soc/intel/meteorlake/Kconfig
index 25d9d68e44..7dc41fc752 100644
--- a/src/soc/intel/meteorlake/Kconfig
+++ b/src/soc/intel/meteorlake/Kconfig
@@ -89,6 +89,7 @@ config SOC_INTEL_METEORLAKE
 	select SOC_INTEL_COMMON_FEATURE
 	select SOC_INTEL_COMMON_FEATURE_ESPI
 	select SOC_INTEL_COMMON_FEATURE_GSPI_DEVFN
+	select SOC_INTEL_COMMON_FEATURE_LOCKDOWN
 	select SOC_INTEL_COMMON_FEATURE_PMUTIL
 	select SOC_INTEL_COMMON_FEATURE_SMIHANDLER
 	select SOC_INTEL_COMMON_FEATURE_SOUNDWIRE
diff --git a/src/soc/intel/meteorlake/Makefile.mk b/src/soc/intel/meteorlake/Makefile.mk
index b2c2429476..03463ff393 100644
--- a/src/soc/intel/meteorlake/Makefile.mk
+++ b/src/soc/intel/meteorlake/Makefile.mk
@@ -29,7 +29,6 @@ ramstage-y += elog.c
 ramstage-y += finalize.c
 ramstage-y += fsp_params.c
 ramstage-y += graphics.c
-ramstage-y += lockdown.c
 ramstage-y += p2sb.c
 ramstage-y += pcie_rp.c
 ramstage-y += pmc.c
diff --git a/src/soc/intel/meteorlake/include/soc/pmc.h b/src/soc/intel/meteorlake/include/soc/pmc.h
index 6c40b4a5ee..19365ea122 100644
--- a/src/soc/intel/meteorlake/include/soc/pmc.h
+++ b/src/soc/intel/meteorlake/include/soc/pmc.h
@@ -62,6 +62,9 @@ extern struct device_operations ioe_pmc_ops;
 #define   SMI_LOCK			(1 << 4)
 #define   RTC_BATTERY_DEAD		(1 << 2)
 
+/* PMC lockdown configuration register for ST_FDIS_LOCK */
+#define PMC_FDIS_LOCK_REG		GEN_PMCON_B
+
 #define ETR				0x1048
 #define   CF9_LOCK			(1 << 31)
 #define   CF9_GLB_RST			(1 << 20)
diff --git a/src/soc/intel/meteorlake/lockdown.c b/src/soc/intel/meteorlake/lockdown.c
deleted file mode 100644
index 324c37ba38..0000000000
--- a/src/soc/intel/meteorlake/lockdown.c
+++ /dev/null
@@ -1,54 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <device/mmio.h>
-#include <intelblocks/cfg.h>
-#include <intelblocks/pcr.h>
-#include <intelblocks/pmclib.h>
-#include <intelpch/lockdown.h>
-#include <soc/pcr_ids.h>
-#include <soc/pm.h>
-#include <stdint.h>
-
-/* PCR PSTH Control Register */
-#define PCR_PSTH_CTRLREG	0x1d00
-#define PSTH_CTRLREG_IOSFPTCGE	(1 << 2)
-
-static void pmc_lockdown_cfg(int chipset_lockdown)
-{
-	uint8_t *pmcbase = pmc_mmio_regs();
-
-	/* PMSYNC */
-	setbits32(pmcbase + PMSYNC_TPR_CFG, PCH2CPU_TPR_CFG_LOCK);
-	/* Lock down ABASE and sleep stretching policy */
-	setbits32(pmcbase + GEN_PMCON_B, SLP_STR_POL_LOCK | ACPI_BASE_LOCK);
-
-	if (chipset_lockdown == CHIPSET_LOCKDOWN_COREBOOT)
-		setbits32(pmcbase + GEN_PMCON_B, SMI_LOCK);
-
-	if (!CONFIG(USE_FSP_NOTIFY_PHASE_POST_PCI_ENUM)) {
-		setbits32(pmcbase + GEN_PMCON_B, ST_FDIS_LOCK);
-		setbits32(pmcbase + SSML, SSML_SSL_EN);
-		setbits32(pmcbase + PM_CFG, PM_CFG_DBG_MODE_LOCK |
-					 PM_CFG_XRAM_READ_DISABLE);
-	}
-
-	/* Send PMC IPC to inform about both BIOS Reset and PCI enumeration done */
-	pmc_send_bios_reset_pci_enum_done();
-}
-
-static void soc_die_lockdown_cfg(void)
-{
-	if (CONFIG(USE_FSP_NOTIFY_PHASE_POST_PCI_ENUM))
-		return;
-
-	/* Enable IOSF Primary Trunk Clock Gating */
-	pcr_rmw32(PID_PSTH, PCR_PSTH_CTRLREG, ~0, PSTH_CTRLREG_IOSFPTCGE);
-}
-
-void soc_lockdown_config(int chipset_lockdown)
-{
-	/* PMC lock down configuration */
-	pmc_lockdown_cfg(chipset_lockdown);
-	/* SOC Die lock down configuration */
-	soc_die_lockdown_cfg();
-}

From 7d8acb88c5b8fd5309ea736861dd1e6c98239d9c Mon Sep 17 00:00:00 2001
From: Jeremy Compostella <jeremy.compostella@intel.com>
Date: Fri, 13 Feb 2026 23:35:49 -0800
Subject: [PATCH 3598/3886] soc/intel/pantherlake: Switch to common PMC
 lockdown driver

Replace platform-specific lockdown.c with the common PMC lockdown
driver.

Changes:
- Remove src/soc/intel/pantherlake/lockdown.c
- Add PMC_FDIS_LOCK_REG define pointing to GEN_PMCON_B in soc/pmc.h
- Enable SOC_INTEL_COMMON_FEATURE_PMC_LOCKDOWN in Kconfig
- Update Makefile.mk to remove lockdown.c from build

Panther Lake uses GEN_PMCON_B for ST_FDIS_LOCK (bit 21), the same
approach as Meteor Lake.

Change-Id: I9becbedbb1bcbc19f60d3ebb024dd5e43c7cee29
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91207
Reviewed-by: Huang, Cliff <cliff.huang@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/soc/intel/pantherlake/Kconfig           |  1 +
 src/soc/intel/pantherlake/Makefile.mk       |  1 -
 src/soc/intel/pantherlake/include/soc/pmc.h |  3 ++
 src/soc/intel/pantherlake/lockdown.c        | 54 ---------------------
 4 files changed, 4 insertions(+), 55 deletions(-)
 delete mode 100644 src/soc/intel/pantherlake/lockdown.c

diff --git a/src/soc/intel/pantherlake/Kconfig b/src/soc/intel/pantherlake/Kconfig
index decd4c84c6..6b68c95dde 100644
--- a/src/soc/intel/pantherlake/Kconfig
+++ b/src/soc/intel/pantherlake/Kconfig
@@ -99,6 +99,7 @@ config SOC_INTEL_PANTHERLAKE_BASE
 	select SOC_INTEL_COMMON_FEATURE
 	select SOC_INTEL_COMMON_FEATURE_ESPI
 	select SOC_INTEL_COMMON_FEATURE_GSPI_DEVFN
+	select SOC_INTEL_COMMON_FEATURE_LOCKDOWN
 	select SOC_INTEL_COMMON_FEATURE_PMUTIL
 	select SOC_INTEL_COMMON_FEATURE_SMIHANDLER
 	select SOC_INTEL_COMMON_FEATURE_SOUNDWIRE
diff --git a/src/soc/intel/pantherlake/Makefile.mk b/src/soc/intel/pantherlake/Makefile.mk
index 7349987e28..868ae605cd 100644
--- a/src/soc/intel/pantherlake/Makefile.mk
+++ b/src/soc/intel/pantherlake/Makefile.mk
@@ -27,7 +27,6 @@ ramstage-$(CONFIG_SOC_INTEL_CRASHLOG) += crashlog.c
 ramstage-y += elog.c
 ramstage-y += finalize.c
 ramstage-y += fsp_params.c
-ramstage-y += lockdown.c
 ramstage-y += p2sb.c
 ramstage-y += pcie_rp.c
 ramstage-y += pmc.c
diff --git a/src/soc/intel/pantherlake/include/soc/pmc.h b/src/soc/intel/pantherlake/include/soc/pmc.h
index 415bf074fb..bf0f6b5978 100644
--- a/src/soc/intel/pantherlake/include/soc/pmc.h
+++ b/src/soc/intel/pantherlake/include/soc/pmc.h
@@ -62,6 +62,9 @@ extern struct device_operations pmc_ops;
 #define   SMI_LOCK			BIT(4)
 #define   RTC_BATTERY_DEAD		BIT(2)
 
+/* PMC lockdown configuration register for ST_FDIS_LOCK */
+#define PMC_FDIS_LOCK_REG		GEN_PMCON_B
+
 /* Extended Test Mode Register */
 #define ETR				0x1048
 #define   CF9_LOCK			BIT(31)
diff --git a/src/soc/intel/pantherlake/lockdown.c b/src/soc/intel/pantherlake/lockdown.c
deleted file mode 100644
index 2994952d00..0000000000
--- a/src/soc/intel/pantherlake/lockdown.c
+++ /dev/null
@@ -1,54 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <device/mmio.h>
-#include <intelblocks/cfg.h>
-#include <intelblocks/pcr.h>
-#include <intelblocks/pmclib.h>
-#include <intelpch/lockdown.h>
-#include <soc/pcr_ids.h>
-#include <soc/pm.h>
-#include <stdint.h>
-
-/* PCR PSTH Control Register */
-#define PCR_PSTH_CTRLREG	0x1d00
-#define  PSTH_CTRLREG_IOSFPTCGE	BIT(2)
-
-static void pmc_lockdown_cfg(int chipset_lockdown)
-{
-	uint8_t *pmcbase = pmc_mmio_regs();
-
-	/* PMSYNC */
-	setbits32(pmcbase + PMSYNC_TPR_CFG, PCH2CPU_TPR_CFG_LOCK);
-	/* Lock down ABASE and sleep stretching policy */
-	setbits32(pmcbase + GEN_PMCON_B, SLP_STR_POL_LOCK | ACPI_BASE_LOCK);
-
-	if (chipset_lockdown == CHIPSET_LOCKDOWN_COREBOOT)
-		setbits32(pmcbase + GEN_PMCON_B, SMI_LOCK);
-
-	if (!CONFIG(USE_FSP_NOTIFY_PHASE_POST_PCI_ENUM)) {
-		setbits32(pmcbase + GEN_PMCON_B, ST_FDIS_LOCK);
-		setbits32(pmcbase + SSML, SSML_SSL_EN);
-		setbits32(pmcbase + PM_CFG, PM_CFG_DBG_MODE_LOCK |
-					 PM_CFG_XRAM_READ_DISABLE);
-	}
-
-	/* Send PMC IPC to inform about both BIOS Reset and PCI enumeration done */
-	pmc_send_bios_reset_pci_enum_done();
-}
-
-static void soc_die_lockdown_cfg(void)
-{
-	if (CONFIG(USE_FSP_NOTIFY_PHASE_POST_PCI_ENUM))
-		return;
-
-	/* Enable IOSF Primary Trunk Clock Gating */
-	pcr_rmw32(PID_PSTH, PCR_PSTH_CTRLREG, ~0, PSTH_CTRLREG_IOSFPTCGE);
-}
-
-void soc_lockdown_config(int chipset_lockdown)
-{
-	/* PMC lock down configuration */
-	pmc_lockdown_cfg(chipset_lockdown);
-	/* SOC Die lock down configuration */
-	soc_die_lockdown_cfg();
-}

From e4ea8401143466365c0b84c9228b468c3a0f848a Mon Sep 17 00:00:00 2001
From: Jeremy Compostella <jeremy.compostella@intel.com>
Date: Fri, 13 Feb 2026 23:59:57 -0800
Subject: [PATCH 3599/3886] soc/intel/common: Add common global reset
 implementation

This introduces a common implementation of do_global_reset() that
uses CSE (Converged Security Engine) with PMC (Power Management
Controller) fallback. This implementation is identical across 7
Intel client platforms.

The function attempts to request a global reset from the CSE first,
which is the preferred method. If CSE is unavailable or the request
fails, it falls back to enabling PMC-based global reset and
triggering a full reset.

This consolidates the global reset handling and eliminates duplicate
code across multiple platforms. The common implementation is enabled
via the SOC_INTEL_COMMON_RESET_GLOBAL_RESET_CSE_PMC Kconfig option.

Platforms that will use this common implementation:
- Alder Lake
- Meteor Lake
- Panther Lake
- Tiger Lake
- Cannon Lake
- Jasper Lake
- Elkhart Lake

Change-Id: Ida59bc2df483db5397ee043f66fdee56508bd0df
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91208
Reviewed-by: Guvendik, Bora <bora.guvendik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 .../intel/common/feature/globalreset/Kconfig    |  9 +++++++++
 .../common/feature/globalreset/Makefile.mk      |  3 +++
 .../feature/globalreset/global_reset_cse_pmc.c  | 17 +++++++++++++++++
 3 files changed, 29 insertions(+)
 create mode 100644 src/soc/intel/common/feature/globalreset/Kconfig
 create mode 100644 src/soc/intel/common/feature/globalreset/Makefile.mk
 create mode 100644 src/soc/intel/common/feature/globalreset/global_reset_cse_pmc.c

diff --git a/src/soc/intel/common/feature/globalreset/Kconfig b/src/soc/intel/common/feature/globalreset/Kconfig
new file mode 100644
index 0000000000..77c695d51a
--- /dev/null
+++ b/src/soc/intel/common/feature/globalreset/Kconfig
@@ -0,0 +1,9 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
+config SOC_INTEL_COMMON_FEATURE_GLOBAL_RESET_CSE_PMC
+	bool
+	help
+	  Include common implementation of do_global_reset() that uses CSE
+	  (Converged Security Engine) with PMC (Power Management Controller)
+	  fallback. This implementation is identical across multiple Intel
+	  client platforms.
diff --git a/src/soc/intel/common/feature/globalreset/Makefile.mk b/src/soc/intel/common/feature/globalreset/Makefile.mk
new file mode 100644
index 0000000000..cff5f7a5e5
--- /dev/null
+++ b/src/soc/intel/common/feature/globalreset/Makefile.mk
@@ -0,0 +1,3 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
+all-$(CONFIG_SOC_INTEL_COMMON_FEATURE_GLOBAL_RESET_CSE_PMC) += global_reset_cse_pmc.c
diff --git a/src/soc/intel/common/feature/globalreset/global_reset_cse_pmc.c b/src/soc/intel/common/feature/globalreset/global_reset_cse_pmc.c
new file mode 100644
index 0000000000..3c13f6dfe5
--- /dev/null
+++ b/src/soc/intel/common/feature/globalreset/global_reset_cse_pmc.c
@@ -0,0 +1,17 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <cf9_reset.h>
+#include <intelblocks/cse.h>
+#include <intelblocks/pmclib.h>
+#include <soc/intel/common/reset.h>
+
+void do_global_reset(void)
+{
+	/* Ask CSE to do the global reset */
+	if (cse_request_global_reset() == CSE_TX_RX_SUCCESS)
+		return;
+
+	/* global reset if CSE fail to reset */
+	pmc_global_reset_enable(1);
+	do_full_reset();
+}

From b2a533c918d99e7bc417dc747d1158b13389139a Mon Sep 17 00:00:00 2001
From: Jeremy Compostella <jeremy.compostella@intel.com>
Date: Sat, 14 Feb 2026 00:00:08 -0800
Subject: [PATCH 3600/3886] soc/intel/alderlake: Switch to common global reset
 implementation

Replace platform-specific reset.c with the common global reset
implementation using CSE with PMC fallback.

Changes:
- Remove src/soc/intel/alderlake/reset.c
- Enable SOC_INTEL_COMMON_FEATURE_GLOBAL_RESET_CSE_PMC in Kconfig
- Update Makefile.mk to remove reset.c from build

The global reset implementation was identical to 6 other platforms,
making it an ideal candidate for consolidation.

Change-Id: Iebaf5bafd5a97dde37ffc435b2ad8b6a8dcfecd0
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91209
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Guvendik, Bora <bora.guvendik@intel.com>
---
 src/soc/intel/alderlake/Kconfig     |  1 +
 src/soc/intel/alderlake/Makefile.mk |  2 --
 src/soc/intel/alderlake/reset.c     | 17 -----------------
 3 files changed, 1 insertion(+), 19 deletions(-)
 delete mode 100644 src/soc/intel/alderlake/reset.c

diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig
index 9198377291..91058e8ed3 100644
--- a/src/soc/intel/alderlake/Kconfig
+++ b/src/soc/intel/alderlake/Kconfig
@@ -86,6 +86,7 @@ config SOC_INTEL_ALDERLAKE
 	select SOC_INTEL_COMMON_BLOCK_XHCI_ELOG
 	select SOC_INTEL_COMMON_FEATURE
 	select SOC_INTEL_COMMON_FEATURE_ESPI
+	select SOC_INTEL_COMMON_FEATURE_GLOBAL_RESET_CSE_PMC
 	select SOC_INTEL_COMMON_FEATURE_GSPI_DEVFN
 	select SOC_INTEL_COMMON_FEATURE_LOCKDOWN
 	select SOC_INTEL_COMMON_FEATURE_PMUTIL
diff --git a/src/soc/intel/alderlake/Makefile.mk b/src/soc/intel/alderlake/Makefile.mk
index cbfa1ebda5..5ca354832d 100644
--- a/src/soc/intel/alderlake/Makefile.mk
+++ b/src/soc/intel/alderlake/Makefile.mk
@@ -15,7 +15,6 @@ bootblock-$(CONFIG_ALDERLAKE_CONFIGURE_DESCRIPTOR) += bootblock/update_descripto
 romstage-$(CONFIG_SOC_INTEL_CSE_PRE_CPU_RESET_TELEMETRY) += cse_telemetry.c
 romstage-y += meminit.c
 romstage-y += pcie_rp.c
-romstage-y += reset.c
 
 ramstage-y += acpi.c
 ramstage-y += chip.c
@@ -28,7 +27,6 @@ ramstage-y += hsphy.c
 ramstage-y += p2sb.c
 ramstage-y += pcie_rp.c
 ramstage-y += pmc.c
-ramstage-y += reset.c
 ramstage-$(CONFIG_SOC_INTEL_ALDERLAKE_TCSS_USB4_SUPPORT) += retimer.c
 ramstage-y += systemagent.c
 ramstage-y += tcss.c
diff --git a/src/soc/intel/alderlake/reset.c b/src/soc/intel/alderlake/reset.c
deleted file mode 100644
index 3c13f6dfe5..0000000000
--- a/src/soc/intel/alderlake/reset.c
+++ /dev/null
@@ -1,17 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <cf9_reset.h>
-#include <intelblocks/cse.h>
-#include <intelblocks/pmclib.h>
-#include <soc/intel/common/reset.h>
-
-void do_global_reset(void)
-{
-	/* Ask CSE to do the global reset */
-	if (cse_request_global_reset() == CSE_TX_RX_SUCCESS)
-		return;
-
-	/* global reset if CSE fail to reset */
-	pmc_global_reset_enable(1);
-	do_full_reset();
-}

From 5c85dcda7f9d223c18032319b7ca01798361bd8d Mon Sep 17 00:00:00 2001
From: Jeremy Compostella <jeremy.compostella@intel.com>
Date: Sat, 14 Feb 2026 00:00:08 -0800
Subject: [PATCH 3601/3886] soc/intel/meteorlake: Switch to common global reset
 implementation

Replace platform-specific reset.c with the common global reset
implementation using CSE with PMC fallback.

Changes:
- Remove src/soc/intel/meteorlake/reset.c
- Enable SOC_INTEL_COMMON_FEATURE_GLOBAL_RESET_CSE_PMC in Kconfig
- Update Makefile.mk to remove reset.c from build

The global reset implementation was identical to 6 other platforms,
making it an ideal candidate for consolidation.

Change-Id: I0ad75bbeb1fad7352b2b898487a5b54eff496d0b
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91210
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Guvendik, Bora <bora.guvendik@intel.com>
---
 src/soc/intel/meteorlake/Kconfig     |  1 +
 src/soc/intel/meteorlake/Makefile.mk |  2 --
 src/soc/intel/meteorlake/reset.c     | 17 -----------------
 3 files changed, 1 insertion(+), 19 deletions(-)
 delete mode 100644 src/soc/intel/meteorlake/reset.c

diff --git a/src/soc/intel/meteorlake/Kconfig b/src/soc/intel/meteorlake/Kconfig
index 7dc41fc752..4d4fe30fd5 100644
--- a/src/soc/intel/meteorlake/Kconfig
+++ b/src/soc/intel/meteorlake/Kconfig
@@ -88,6 +88,7 @@ config SOC_INTEL_METEORLAKE
 	select SOC_INTEL_COMMON_BLOCK_XHCI_ELOG
 	select SOC_INTEL_COMMON_FEATURE
 	select SOC_INTEL_COMMON_FEATURE_ESPI
+	select SOC_INTEL_COMMON_FEATURE_GLOBAL_RESET_CSE_PMC
 	select SOC_INTEL_COMMON_FEATURE_GSPI_DEVFN
 	select SOC_INTEL_COMMON_FEATURE_LOCKDOWN
 	select SOC_INTEL_COMMON_FEATURE_PMUTIL
diff --git a/src/soc/intel/meteorlake/Makefile.mk b/src/soc/intel/meteorlake/Makefile.mk
index 03463ff393..1ee64e2973 100644
--- a/src/soc/intel/meteorlake/Makefile.mk
+++ b/src/soc/intel/meteorlake/Makefile.mk
@@ -17,7 +17,6 @@ bootblock-y += soc_info.c
 romstage-$(CONFIG_SOC_INTEL_CSE_PRE_CPU_RESET_TELEMETRY) += cse_telemetry.c
 romstage-y += meminit.c
 romstage-y += pcie_rp.c
-romstage-y += reset.c
 romstage-y += soc_info.c
 
 ramstage-y += acpi.c
@@ -32,7 +31,6 @@ ramstage-y += graphics.c
 ramstage-y += p2sb.c
 ramstage-y += pcie_rp.c
 ramstage-y += pmc.c
-ramstage-y += reset.c
 ramstage-y += retimer.c
 ramstage-y += systemagent.c
 ramstage-y += tcss.c
diff --git a/src/soc/intel/meteorlake/reset.c b/src/soc/intel/meteorlake/reset.c
deleted file mode 100644
index 3c13f6dfe5..0000000000
--- a/src/soc/intel/meteorlake/reset.c
+++ /dev/null
@@ -1,17 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <cf9_reset.h>
-#include <intelblocks/cse.h>
-#include <intelblocks/pmclib.h>
-#include <soc/intel/common/reset.h>
-
-void do_global_reset(void)
-{
-	/* Ask CSE to do the global reset */
-	if (cse_request_global_reset() == CSE_TX_RX_SUCCESS)
-		return;
-
-	/* global reset if CSE fail to reset */
-	pmc_global_reset_enable(1);
-	do_full_reset();
-}

From 0d4b9347261b2f2d9712251e7126c4fcc044591f Mon Sep 17 00:00:00 2001
From: Jeremy Compostella <jeremy.compostella@intel.com>
Date: Sat, 14 Feb 2026 00:00:08 -0800
Subject: [PATCH 3602/3886] soc/intel/pantherlake: Switch to common global
 reset implementation

Replace platform-specific reset.c with the common global reset
implementation using CSE with PMC fallback.

Changes:
- Remove src/soc/intel/pantherlake/reset.c
- Enable SOC_INTEL_COMMON_FEATURE_GLOBAL_RESET_CSE_PMC in Kconfig
- Update Makefile.mk to remove reset.c from build

The global reset implementation was identical to 6 other platforms,
making it an ideal candidate for consolidation.

Change-Id: I9bd0dae5bbfc0ec2e9101e848de2037760314456
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91211
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Guvendik, Bora <bora.guvendik@intel.com>
---
 src/soc/intel/pantherlake/Kconfig     |  1 +
 src/soc/intel/pantherlake/Makefile.mk |  2 --
 src/soc/intel/pantherlake/reset.c     | 17 -----------------
 3 files changed, 1 insertion(+), 19 deletions(-)
 delete mode 100644 src/soc/intel/pantherlake/reset.c

diff --git a/src/soc/intel/pantherlake/Kconfig b/src/soc/intel/pantherlake/Kconfig
index 6b68c95dde..279cc68b7d 100644
--- a/src/soc/intel/pantherlake/Kconfig
+++ b/src/soc/intel/pantherlake/Kconfig
@@ -98,6 +98,7 @@ config SOC_INTEL_PANTHERLAKE_BASE
 	select SOC_INTEL_COMMON_BLOCK_XHCI_ELOG
 	select SOC_INTEL_COMMON_FEATURE
 	select SOC_INTEL_COMMON_FEATURE_ESPI
+	select SOC_INTEL_COMMON_FEATURE_GLOBAL_RESET_CSE_PMC
 	select SOC_INTEL_COMMON_FEATURE_GSPI_DEVFN
 	select SOC_INTEL_COMMON_FEATURE_LOCKDOWN
 	select SOC_INTEL_COMMON_FEATURE_PMUTIL
diff --git a/src/soc/intel/pantherlake/Makefile.mk b/src/soc/intel/pantherlake/Makefile.mk
index 868ae605cd..04afc634d8 100644
--- a/src/soc/intel/pantherlake/Makefile.mk
+++ b/src/soc/intel/pantherlake/Makefile.mk
@@ -16,7 +16,6 @@ bootblock-y += bootblock/report_platform.c
 romstage-$(CONFIG_SOC_INTEL_CSE_PRE_CPU_RESET_TELEMETRY) += cse_telemetry.c
 romstage-y += meminit.c
 romstage-y += pcie_rp.c
-romstage-y += reset.c
 romstage-y += tdp.c
 
 ramstage-y += acpi.c
@@ -30,7 +29,6 @@ ramstage-y += fsp_params.c
 ramstage-y += p2sb.c
 ramstage-y += pcie_rp.c
 ramstage-y += pmc.c
-ramstage-y += reset.c
 ramstage-y += retimer.c
 ramstage-y += systemagent.c
 ramstage-y += tcss.c
diff --git a/src/soc/intel/pantherlake/reset.c b/src/soc/intel/pantherlake/reset.c
deleted file mode 100644
index 3c13f6dfe5..0000000000
--- a/src/soc/intel/pantherlake/reset.c
+++ /dev/null
@@ -1,17 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <cf9_reset.h>
-#include <intelblocks/cse.h>
-#include <intelblocks/pmclib.h>
-#include <soc/intel/common/reset.h>
-
-void do_global_reset(void)
-{
-	/* Ask CSE to do the global reset */
-	if (cse_request_global_reset() == CSE_TX_RX_SUCCESS)
-		return;
-
-	/* global reset if CSE fail to reset */
-	pmc_global_reset_enable(1);
-	do_full_reset();
-}

From 2ff987f906f0df3e431f3185a26cd5399dd8b6de Mon Sep 17 00:00:00 2001
From: Jeremy Compostella <jeremy.compostella@intel.com>
Date: Sat, 14 Feb 2026 00:00:08 -0800
Subject: [PATCH 3603/3886] soc/intel/tigerlake: Switch to common global reset
 implementation

Replace platform-specific reset.c with the common global reset
implementation using CSE with PMC fallback.

Changes:
- Remove src/soc/intel/tigerlake/reset.c
- Enable SOC_INTEL_COMMON_FEATURE_GLOBAL_RESET_CSE_PMC in Kconfig
- Update Makefile.mk to remove reset.c from build

The global reset implementation was identical to 6 other platforms,
making it an ideal candidate for consolidation.

Change-Id: I1bf9d4eeab0fecbb33d122a32ecdeef85af059fa
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91212
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Guvendik, Bora <bora.guvendik@intel.com>
---
 src/soc/intel/tigerlake/Kconfig     |  1 +
 src/soc/intel/tigerlake/Makefile.mk |  2 --
 src/soc/intel/tigerlake/reset.c     | 17 -----------------
 3 files changed, 1 insertion(+), 19 deletions(-)
 delete mode 100644 src/soc/intel/tigerlake/reset.c

diff --git a/src/soc/intel/tigerlake/Kconfig b/src/soc/intel/tigerlake/Kconfig
index 192444ec11..81f01e3363 100644
--- a/src/soc/intel/tigerlake/Kconfig
+++ b/src/soc/intel/tigerlake/Kconfig
@@ -74,6 +74,7 @@ config SOC_INTEL_TIGERLAKE
 	select SOC_INTEL_COMMON_BLOCK_XHCI_ELOG
 	select SOC_INTEL_COMMON_FEATURE
 	select SOC_INTEL_COMMON_FEATURE_ESPI
+	select SOC_INTEL_COMMON_FEATURE_GLOBAL_RESET_CSE_PMC
 	select SOC_INTEL_COMMON_FEATURE_GSPI_DEVFN
 	select SOC_INTEL_COMMON_FEATURE_SMIHANDLER
 	select SOC_INTEL_COMMON_FEATURE_SOUNDWIRE
diff --git a/src/soc/intel/tigerlake/Makefile.mk b/src/soc/intel/tigerlake/Makefile.mk
index 5caff77277..09b02a96d4 100644
--- a/src/soc/intel/tigerlake/Makefile.mk
+++ b/src/soc/intel/tigerlake/Makefile.mk
@@ -15,7 +15,6 @@ bootblock-y += p2sb.c
 
 romstage-y += meminit.c
 romstage-y += pcie_rp.c
-romstage-y += reset.c
 
 ramstage-y += acpi.c
 ramstage-y += chip.c
@@ -29,7 +28,6 @@ ramstage-y += lpm.c
 ramstage-y += p2sb.c
 ramstage-y += pcie_rp.c
 ramstage-y += pmc.c
-ramstage-y += reset.c
 ramstage-y += retimer.c
 ramstage-y += systemagent.c
 ramstage-y += tcss.c
diff --git a/src/soc/intel/tigerlake/reset.c b/src/soc/intel/tigerlake/reset.c
deleted file mode 100644
index 3c13f6dfe5..0000000000
--- a/src/soc/intel/tigerlake/reset.c
+++ /dev/null
@@ -1,17 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <cf9_reset.h>
-#include <intelblocks/cse.h>
-#include <intelblocks/pmclib.h>
-#include <soc/intel/common/reset.h>
-
-void do_global_reset(void)
-{
-	/* Ask CSE to do the global reset */
-	if (cse_request_global_reset() == CSE_TX_RX_SUCCESS)
-		return;
-
-	/* global reset if CSE fail to reset */
-	pmc_global_reset_enable(1);
-	do_full_reset();
-}

From 0277c75bddfa8cd6b26eb23422fd349fba6c09e5 Mon Sep 17 00:00:00 2001
From: Jeremy Compostella <jeremy.compostella@intel.com>
Date: Sat, 14 Feb 2026 00:00:08 -0800
Subject: [PATCH 3604/3886] soc/intel/cannonlake: Switch to common global reset
 implementation

Replace platform-specific reset.c with the common global reset
implementation using CSE with PMC fallback.

Changes:
- Remove src/soc/intel/cannonlake/reset.c
- Enable SOC_INTEL_COMMON_FEATURE_GLOBAL_RESET_CSE_PMC in Kconfig
- Update Makefile.mk to remove reset.c from build

The global reset implementation was identical to 6 other platforms,
making it an ideal candidate for consolidation.

Change-Id: If5a70a0e05c50ab893ba8861e200b078982dfad9
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91213
Reviewed-by: Guvendik, Bora <bora.guvendik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/soc/intel/cannonlake/Kconfig     |  1 +
 src/soc/intel/cannonlake/Makefile.mk |  2 --
 src/soc/intel/cannonlake/reset.c     | 17 -----------------
 3 files changed, 1 insertion(+), 19 deletions(-)
 delete mode 100644 src/soc/intel/cannonlake/reset.c

diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig
index 0389d58f9c..cd1eb24760 100644
--- a/src/soc/intel/cannonlake/Kconfig
+++ b/src/soc/intel/cannonlake/Kconfig
@@ -60,6 +60,7 @@ config SOC_INTEL_CANNONLAKE_BASE
 	select SOC_INTEL_COMMON_BLOCK_XHCI
 	select SOC_INTEL_COMMON_BLOCK_XHCI_ELOG
 	select SOC_INTEL_COMMON_FEATURE
+	select SOC_INTEL_COMMON_FEATURE_GLOBAL_RESET_CSE_PMC
 	select SOC_INTEL_COMMON_FEATURE_GSPI_DEVFN
 	select SOC_INTEL_COMMON_FEATURE_I2C_DEVFN
 	select SOC_INTEL_COMMON_FEATURE_UART_DEVICES
diff --git a/src/soc/intel/cannonlake/Makefile.mk b/src/soc/intel/cannonlake/Makefile.mk
index a281068425..f869176ca7 100644
--- a/src/soc/intel/cannonlake/Makefile.mk
+++ b/src/soc/intel/cannonlake/Makefile.mk
@@ -18,7 +18,6 @@ romstage-y += cnl_memcfg_init.c
 romstage-y += lpc.c
 romstage-y += pcie_rp.c
 romstage-y += pmutil.c
-romstage-y += reset.c
 romstage-y += spi.c
 
 ramstage-y += acpi.c
@@ -35,7 +34,6 @@ ramstage-y += p2sb.c
 ramstage-y += pcie_rp.c
 ramstage-y += pmc.c
 ramstage-y += pmutil.c
-ramstage-y += reset.c
 ramstage-y += spi.c
 ramstage-y += systemagent.c
 ramstage-y += vr_config.c
diff --git a/src/soc/intel/cannonlake/reset.c b/src/soc/intel/cannonlake/reset.c
deleted file mode 100644
index 3c13f6dfe5..0000000000
--- a/src/soc/intel/cannonlake/reset.c
+++ /dev/null
@@ -1,17 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <cf9_reset.h>
-#include <intelblocks/cse.h>
-#include <intelblocks/pmclib.h>
-#include <soc/intel/common/reset.h>
-
-void do_global_reset(void)
-{
-	/* Ask CSE to do the global reset */
-	if (cse_request_global_reset() == CSE_TX_RX_SUCCESS)
-		return;
-
-	/* global reset if CSE fail to reset */
-	pmc_global_reset_enable(1);
-	do_full_reset();
-}

From 73e89322ce87159e5b89e6e5899dc9a99ac262a0 Mon Sep 17 00:00:00 2001
From: Jeremy Compostella <jeremy.compostella@intel.com>
Date: Sat, 14 Feb 2026 00:00:09 -0800
Subject: [PATCH 3605/3886] soc/intel/jasperlake: Switch to common global reset
 implementation

Replace platform-specific reset.c with the common global reset
implementation using CSE with PMC fallback.

Changes:
- Remove src/soc/intel/jasperlake/reset.c
- Enable SOC_INTEL_COMMON_FEATURE_GLOBAL_RESET_CSE_PMC in Kconfig
- Update Makefile.mk to remove reset.c from build

The global reset implementation was identical to 6 other platforms,
making it an ideal candidate for consolidation.

Change-Id: Ia039b25b21b4af5912dd5e8af9ef06a66c00a7bd
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91214
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Guvendik, Bora <bora.guvendik@intel.com>
---
 src/soc/intel/jasperlake/Kconfig     |  1 +
 src/soc/intel/jasperlake/Makefile.mk |  2 --
 src/soc/intel/jasperlake/reset.c     | 17 -----------------
 3 files changed, 1 insertion(+), 19 deletions(-)
 delete mode 100644 src/soc/intel/jasperlake/reset.c

diff --git a/src/soc/intel/jasperlake/Kconfig b/src/soc/intel/jasperlake/Kconfig
index 7bcd734887..6f90f28a95 100644
--- a/src/soc/intel/jasperlake/Kconfig
+++ b/src/soc/intel/jasperlake/Kconfig
@@ -57,6 +57,7 @@ config SOC_INTEL_JASPERLAKE
 	select SOC_INTEL_COMMON_BLOCK_XHCI_ELOG
 	select SOC_INTEL_COMMON_FEATURE
 	select SOC_INTEL_COMMON_FEATURE_ESPI
+	select SOC_INTEL_COMMON_FEATURE_GLOBAL_RESET_CSE_PMC
 	select SOC_INTEL_COMMON_FEATURE_GSPI_DEVFN
 	select SOC_INTEL_COMMON_FEATURE_SPI_DEVFN
 	select SOC_INTEL_COMMON_FEATURE_I2C_DEVFN
diff --git a/src/soc/intel/jasperlake/Makefile.mk b/src/soc/intel/jasperlake/Makefile.mk
index 05288ee8a1..bff546748e 100644
--- a/src/soc/intel/jasperlake/Makefile.mk
+++ b/src/soc/intel/jasperlake/Makefile.mk
@@ -17,7 +17,6 @@ bootblock-y += p2sb.c
 romstage-y += gpio.c
 romstage-y += meminit.c
 romstage-y += pcie_rp.c
-romstage-y += reset.c
 
 ramstage-y += acpi.c
 ramstage-y += chip.c
@@ -31,7 +30,6 @@ ramstage-y += lockdown.c
 ramstage-y += p2sb.c
 ramstage-y += pcie_rp.c
 ramstage-y += pmc.c
-ramstage-y += reset.c
 ramstage-y += systemagent.c
 ramstage-y += sd.c
 ramstage-y += xhci.c
diff --git a/src/soc/intel/jasperlake/reset.c b/src/soc/intel/jasperlake/reset.c
deleted file mode 100644
index 3c13f6dfe5..0000000000
--- a/src/soc/intel/jasperlake/reset.c
+++ /dev/null
@@ -1,17 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <cf9_reset.h>
-#include <intelblocks/cse.h>
-#include <intelblocks/pmclib.h>
-#include <soc/intel/common/reset.h>
-
-void do_global_reset(void)
-{
-	/* Ask CSE to do the global reset */
-	if (cse_request_global_reset() == CSE_TX_RX_SUCCESS)
-		return;
-
-	/* global reset if CSE fail to reset */
-	pmc_global_reset_enable(1);
-	do_full_reset();
-}

From c9ba628d512e1cb8693e1fc7b2b2b1e661d7a309 Mon Sep 17 00:00:00 2001
From: Jeremy Compostella <jeremy.compostella@intel.com>
Date: Sat, 14 Feb 2026 00:00:09 -0800
Subject: [PATCH 3606/3886] soc/intel/elkhartlake: Switch to common global
 reset implementation

Replace platform-specific reset.c with the common global reset
implementation using CSE with PMC fallback.

Changes:
- Remove src/soc/intel/elkhartlake/reset.c
- Enable SOC_INTEL_COMMON_FEATURE_GLOBAL_RESET_CSE_PMC in Kconfig
- Update Makefile.mk to remove reset.c from build

The global reset implementation was identical to 6 other platforms,
making it an ideal candidate for consolidation.

Change-Id: I635347f15e35ec8e69c24edcec8c45c55a496ffd
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91215
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Guvendik, Bora <bora.guvendik@intel.com>
---
 src/soc/intel/elkhartlake/Kconfig     |  1 +
 src/soc/intel/elkhartlake/Makefile.mk |  2 --
 src/soc/intel/elkhartlake/reset.c     | 17 -----------------
 3 files changed, 1 insertion(+), 19 deletions(-)
 delete mode 100644 src/soc/intel/elkhartlake/reset.c

diff --git a/src/soc/intel/elkhartlake/Kconfig b/src/soc/intel/elkhartlake/Kconfig
index e8629039a2..a3abfe650d 100644
--- a/src/soc/intel/elkhartlake/Kconfig
+++ b/src/soc/intel/elkhartlake/Kconfig
@@ -57,6 +57,7 @@ config SOC_INTEL_ELKHARTLAKE
 	select SOC_INTEL_COMMON_BLOCK_SMM_IO_TRAP
 	select SOC_INTEL_COMMON_FEATURE
 	select SOC_INTEL_COMMON_FEATURE_ESPI
+	select SOC_INTEL_COMMON_FEATURE_GLOBAL_RESET_CSE_PMC
 	select SOC_INTEL_COMMON_FEATURE_GSPI_DEVFN
 	select SOC_INTEL_COMMON_FEATURE_I2C_DEVFN
 	select SOC_INTEL_COMMON_FEATURE_UART_DEVICES
diff --git a/src/soc/intel/elkhartlake/Makefile.mk b/src/soc/intel/elkhartlake/Makefile.mk
index e46946f0bb..5fc5336723 100644
--- a/src/soc/intel/elkhartlake/Makefile.mk
+++ b/src/soc/intel/elkhartlake/Makefile.mk
@@ -18,7 +18,6 @@ bootblock-y += p2sb.c
 romstage-y += gpio.c
 romstage-y += meminit.c
 romstage-y += pcie_rp.c
-romstage-y += reset.c
 
 ramstage-y += acpi.c
 ramstage-y += chip.c
@@ -30,7 +29,6 @@ ramstage-y += lockdown.c
 ramstage-y += p2sb.c
 ramstage-y += pcie_rp.c
 ramstage-y += pmc.c
-ramstage-y += reset.c
 ramstage-y += systemagent.c
 ramstage-y += sd.c
 ramstage-$(CONFIG_EHL_TSN_DRIVER) += tsn_gbe.c
diff --git a/src/soc/intel/elkhartlake/reset.c b/src/soc/intel/elkhartlake/reset.c
deleted file mode 100644
index 3c13f6dfe5..0000000000
--- a/src/soc/intel/elkhartlake/reset.c
+++ /dev/null
@@ -1,17 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <cf9_reset.h>
-#include <intelblocks/cse.h>
-#include <intelblocks/pmclib.h>
-#include <soc/intel/common/reset.h>
-
-void do_global_reset(void)
-{
-	/* Ask CSE to do the global reset */
-	if (cse_request_global_reset() == CSE_TX_RX_SUCCESS)
-		return;
-
-	/* global reset if CSE fail to reset */
-	pmc_global_reset_enable(1);
-	do_full_reset();
-}

From ae932349bfeac758b09b90114fd75c16e44b4ebf Mon Sep 17 00:00:00 2001
From: Jeremy Compostella <jeremy.compostella@intel.com>
Date: Sat, 14 Feb 2026 21:25:04 -0800
Subject: [PATCH 3607/3886] soc/intel/common/block: Add common finalize
 implementation

This introduces a common finalize implementation for Intel SoCs that
consolidates the nearly identical finalize.c files across Meteor Lake
and Panther Lake platforms.

The implementation includes:
- pch_finalize(): TCO lockdown and PMC status clearing
- tbt_finalize(): Disable Thunderbolt PCIe root ports bus master
- sa_finalize(): Lock system agent PAM regions when coreboot handles
  chipset lockdown
- heci_finalize(): Set HECI to D0i3 and optionally disable HECI1
- soc_finalize(): Main finalization sequence coordinating all the above

This consolidation eliminates duplicate code and ensures consistent
finalization behavior across platforms. Alder Lake is intentionally
excluded as it has additional platform-specific camera clock (ISCLK)
configuration that would complicate the common implementation.

The common driver is enabled via the SOC_INTEL_COMMON_FEATURE_FINALIZE
Kconfig option.

Platforms that will use this common implementation:
- Meteor Lake
- Panther Lake

Change-Id: I4dd9ccf7e14fecdded92da6bf366e6ff56d866a4
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91227
Reviewed-by: Huang, Cliff <cliff.huang@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/soc/intel/common/feature/finalize/Kconfig |  8 ++
 .../intel/common/feature/finalize/Makefile.mk |  3 +
 .../intel/common/feature/finalize/finalize.c  | 79 +++++++++++++++++++
 3 files changed, 90 insertions(+)
 create mode 100644 src/soc/intel/common/feature/finalize/Kconfig
 create mode 100644 src/soc/intel/common/feature/finalize/Makefile.mk
 create mode 100644 src/soc/intel/common/feature/finalize/finalize.c

diff --git a/src/soc/intel/common/feature/finalize/Kconfig b/src/soc/intel/common/feature/finalize/Kconfig
new file mode 100644
index 0000000000..87a48b22a4
--- /dev/null
+++ b/src/soc/intel/common/feature/finalize/Kconfig
@@ -0,0 +1,8 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
+config SOC_INTEL_COMMON_FEATURE_FINALIZE
+	bool
+	help
+	  Include common finalize implementation for Intel SoCs. This driver
+	  consolidates the nearly identical finalize implementations across
+	  Meteor Lake and Panther Lake platforms.
diff --git a/src/soc/intel/common/feature/finalize/Makefile.mk b/src/soc/intel/common/feature/finalize/Makefile.mk
new file mode 100644
index 0000000000..7f56bee857
--- /dev/null
+++ b/src/soc/intel/common/feature/finalize/Makefile.mk
@@ -0,0 +1,3 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
+ramstage-$(CONFIG_SOC_INTEL_COMMON_FEATURE_FINALIZE) += finalize.c
diff --git a/src/soc/intel/common/feature/finalize/finalize.c b/src/soc/intel/common/feature/finalize/finalize.c
new file mode 100644
index 0000000000..7830fb8e63
--- /dev/null
+++ b/src/soc/intel/common/feature/finalize/finalize.c
@@ -0,0 +1,79 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <bootstate.h>
+#include <console/console.h>
+#include <cpu/x86/smm.h>
+#include <device/pci.h>
+#include <intelblocks/cfg.h>
+#include <intelblocks/cse.h>
+#include <intelblocks/pmclib.h>
+#include <intelblocks/systemagent.h>
+#include <intelblocks/tco.h>
+#include <intelpch/lockdown.h>
+#include <soc/pci_devs.h>
+#include <soc/systemagent.h>
+
+/*
+ * Common finalize implementation for Intel SoCs.
+ * This consolidates the nearly identical finalize.c implementations
+ * across Meteor Lake and Panther Lake platforms.
+ */
+
+static void pch_finalize(void)
+{
+	/* TCO Lock down */
+	tco_lockdown();
+
+	/* TODO: Add Thermal Configuration */
+
+	pmc_clear_pmcon_sts();
+}
+
+static void tbt_finalize(void)
+{
+	int i;
+	const struct device *dev;
+
+	/* Disable Thunderbolt PCIe root ports bus master */
+	for (i = 0; i < NUM_TBT_FUNCTIONS; i++) {
+		dev = pcidev_path_on_root(PCI_DEVFN_TBT(i));
+		if (dev)
+			pci_dev_disable_bus_master(dev);
+	}
+}
+
+static void sa_finalize(void)
+{
+	if (get_lockdown_config() == CHIPSET_LOCKDOWN_COREBOOT)
+		sa_lock_pam();
+}
+
+static void heci_finalize(void)
+{
+	heci_set_to_d0i3();
+	if (CONFIG(DISABLE_HECI1_AT_PRE_BOOT))
+		heci1_disable();
+}
+
+static void soc_finalize(void *unused)
+{
+	printk(BIOS_DEBUG, "Finalizing chipset.\n");
+
+	pch_finalize();
+	apm_control(APM_CNT_FINALIZE);
+	tbt_finalize();
+	sa_finalize();
+	if (CONFIG(USE_FSP_NOTIFY_PHASE_READY_TO_BOOT) &&
+			 CONFIG(USE_FSP_NOTIFY_PHASE_END_OF_FIRMWARE))
+		heci_finalize();
+
+	/* Indicate finalize step with post code */
+	post_code(POSTCODE_OS_BOOT);
+}
+
+BOOT_STATE_INIT_ENTRY(BS_OS_RESUME, BS_ON_ENTRY, soc_finalize, NULL);
+/*
+ * The purpose of this change is to accommodate more time to push out sending
+ * CSE EOP messages at post.
+ */
+BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_BOOT, BS_ON_ENTRY, soc_finalize, NULL);

From 5c56b9ff72e50fb8e9717a2d1c1ad1e97675d90e Mon Sep 17 00:00:00 2001
From: Jeremy Compostella <jeremy.compostella@intel.com>
Date: Sat, 14 Feb 2026 21:25:17 -0800
Subject: [PATCH 3608/3886] soc/intel/meteorlake: Switch to common finalize
 implementation

Replace platform-specific finalize.c with the common finalize
implementation.

Changes:
- Remove src/soc/intel/meteorlake/finalize.c
- Enable SOC_INTEL_COMMON_FEATURE_FINALIZE in Kconfig
- Update Makefile.mk to remove finalize.c from build

The finalize implementation was identical to Panther Lake, making
it an ideal candidate for consolidation.

Change-Id: Id0c3bde3b721b7a3e497711cfc6dd21efbfda4c5
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91228
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Huang, Cliff <cliff.huang@intel.com>
---
 src/soc/intel/meteorlake/Kconfig     |  1 +
 src/soc/intel/meteorlake/Makefile.mk |  1 -
 src/soc/intel/meteorlake/finalize.c  | 83 ----------------------------
 3 files changed, 1 insertion(+), 84 deletions(-)
 delete mode 100644 src/soc/intel/meteorlake/finalize.c

diff --git a/src/soc/intel/meteorlake/Kconfig b/src/soc/intel/meteorlake/Kconfig
index 4d4fe30fd5..9bdeea0b8d 100644
--- a/src/soc/intel/meteorlake/Kconfig
+++ b/src/soc/intel/meteorlake/Kconfig
@@ -88,6 +88,7 @@ config SOC_INTEL_METEORLAKE
 	select SOC_INTEL_COMMON_BLOCK_XHCI_ELOG
 	select SOC_INTEL_COMMON_FEATURE
 	select SOC_INTEL_COMMON_FEATURE_ESPI
+	select SOC_INTEL_COMMON_FEATURE_FINALIZE
 	select SOC_INTEL_COMMON_FEATURE_GLOBAL_RESET_CSE_PMC
 	select SOC_INTEL_COMMON_FEATURE_GSPI_DEVFN
 	select SOC_INTEL_COMMON_FEATURE_LOCKDOWN
diff --git a/src/soc/intel/meteorlake/Makefile.mk b/src/soc/intel/meteorlake/Makefile.mk
index 1ee64e2973..9d6e840369 100644
--- a/src/soc/intel/meteorlake/Makefile.mk
+++ b/src/soc/intel/meteorlake/Makefile.mk
@@ -25,7 +25,6 @@ ramstage-y += cpu.c
 ramstage-$(CONFIG_SOC_INTEL_CRASHLOG) += crashlog.c
 ramstage-y += ioe_pmc.c
 ramstage-y += elog.c
-ramstage-y += finalize.c
 ramstage-y += fsp_params.c
 ramstage-y += graphics.c
 ramstage-y += p2sb.c
diff --git a/src/soc/intel/meteorlake/finalize.c b/src/soc/intel/meteorlake/finalize.c
deleted file mode 100644
index 1fd1d98fb5..0000000000
--- a/src/soc/intel/meteorlake/finalize.c
+++ /dev/null
@@ -1,83 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <device/mmio.h>
-#include <bootstate.h>
-#include <console/console.h>
-#include <cpu/x86/smm.h>
-#include <device/pci.h>
-#include <gpio.h>
-#include <intelblocks/cse.h>
-#include <intelblocks/lpc_lib.h>
-#include <intelblocks/pcr.h>
-#include <intelblocks/pmclib.h>
-#include <intelblocks/systemagent.h>
-#include <intelblocks/tco.h>
-#include <intelblocks/thermal.h>
-#include <spi-generic.h>
-#include <intelpch/lockdown.h>
-#include <soc/p2sb.h>
-#include <soc/pci_devs.h>
-#include <soc/pcr_ids.h>
-#include <soc/pm.h>
-#include <soc/smbus.h>
-#include <soc/soc_chip.h>
-#include <soc/systemagent.h>
-
-static void pch_finalize(void)
-{
-	/* TCO Lock down */
-	tco_lockdown();
-
-	/* TODO: Add Thermal Configuration */
-
-	pmc_clear_pmcon_sts();
-}
-
-static void tbt_finalize(void)
-{
-	int i;
-	const struct device *dev;
-
-	/* Disable Thunderbolt PCIe root ports bus master */
-	for (i = 0; i < NUM_TBT_FUNCTIONS; i++) {
-		dev = pcidev_path_on_root(PCI_DEVFN_TBT(i));
-		if (dev)
-			pci_dev_disable_bus_master(dev);
-	}
-}
-
-static void sa_finalize(void)
-{
-	if (get_lockdown_config() == CHIPSET_LOCKDOWN_COREBOOT)
-		sa_lock_pam();
-}
-
-static void heci_finalize(void)
-{
-	heci_set_to_d0i3();
-	if (CONFIG(DISABLE_HECI1_AT_PRE_BOOT))
-		heci1_disable();
-}
-
-static void soc_finalize(void *unused)
-{
-	printk(BIOS_DEBUG, "Finalizing chipset.\n");
-
-	pch_finalize();
-	apm_control(APM_CNT_FINALIZE);
-	tbt_finalize();
-	sa_finalize();
-	if (CONFIG(USE_FSP_NOTIFY_PHASE_READY_TO_BOOT) &&
-			 CONFIG(USE_FSP_NOTIFY_PHASE_END_OF_FIRMWARE))
-		heci_finalize();
-
-	/* Indicate finalize step with post code */
-	post_code(POSTCODE_OS_BOOT);
-}
-
-BOOT_STATE_INIT_ENTRY(BS_OS_RESUME, BS_ON_ENTRY, soc_finalize, NULL);
-/*
- * The purpose of this change is to accommodate more time to push out sending
- * CSE EOP messages at post.
- */
-BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_BOOT, BS_ON_ENTRY, soc_finalize, NULL);

From b52236fe9e210327fc26cf7c750948ff49066891 Mon Sep 17 00:00:00 2001
From: Jeremy Compostella <jeremy.compostella@intel.com>
Date: Sat, 14 Feb 2026 21:25:27 -0800
Subject: [PATCH 3609/3886] soc/intel/pantherlake: Switch to common finalize
 implementation

Replace platform-specific finalize.c with the common finalize
implementation.

Changes:
- Remove src/soc/intel/pantherlake/finalize.c
- Enable SOC_INTEL_COMMON_FEATURE_FINALIZE in Kconfig
- Update Makefile.mk to remove finalize.c from build

The finalize implementation was identical to Meteor Lake, making
it an ideal candidate for consolidation.

Change-Id: I749eea246fdc7ab89848ed4160c61666e8944095
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91229
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Huang, Cliff <cliff.huang@intel.com>
---
 src/soc/intel/pantherlake/Kconfig     |  1 +
 src/soc/intel/pantherlake/Makefile.mk |  1 -
 src/soc/intel/pantherlake/finalize.c  | 82 ---------------------------
 3 files changed, 1 insertion(+), 83 deletions(-)
 delete mode 100644 src/soc/intel/pantherlake/finalize.c

diff --git a/src/soc/intel/pantherlake/Kconfig b/src/soc/intel/pantherlake/Kconfig
index 279cc68b7d..e85d80cddd 100644
--- a/src/soc/intel/pantherlake/Kconfig
+++ b/src/soc/intel/pantherlake/Kconfig
@@ -98,6 +98,7 @@ config SOC_INTEL_PANTHERLAKE_BASE
 	select SOC_INTEL_COMMON_BLOCK_XHCI_ELOG
 	select SOC_INTEL_COMMON_FEATURE
 	select SOC_INTEL_COMMON_FEATURE_ESPI
+	select SOC_INTEL_COMMON_FEATURE_FINALIZE
 	select SOC_INTEL_COMMON_FEATURE_GLOBAL_RESET_CSE_PMC
 	select SOC_INTEL_COMMON_FEATURE_GSPI_DEVFN
 	select SOC_INTEL_COMMON_FEATURE_LOCKDOWN
diff --git a/src/soc/intel/pantherlake/Makefile.mk b/src/soc/intel/pantherlake/Makefile.mk
index 04afc634d8..b7ea31b1f6 100644
--- a/src/soc/intel/pantherlake/Makefile.mk
+++ b/src/soc/intel/pantherlake/Makefile.mk
@@ -24,7 +24,6 @@ ramstage-y += chip.c
 ramstage-y += cpu.c
 ramstage-$(CONFIG_SOC_INTEL_CRASHLOG) += crashlog.c
 ramstage-y += elog.c
-ramstage-y += finalize.c
 ramstage-y += fsp_params.c
 ramstage-y += p2sb.c
 ramstage-y += pcie_rp.c
diff --git a/src/soc/intel/pantherlake/finalize.c b/src/soc/intel/pantherlake/finalize.c
deleted file mode 100644
index 05ec3eaaca..0000000000
--- a/src/soc/intel/pantherlake/finalize.c
+++ /dev/null
@@ -1,82 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <arch/io.h>
-#include <bootstate.h>
-#include <console/console.h>
-#include <cpu/x86/smm.h>
-#include <device/mmio.h>
-#include <device/pci.h>
-#include <intelblocks/cse.h>
-#include <intelblocks/lpc_lib.h>
-#include <intelblocks/pcr.h>
-#include <intelblocks/pmclib.h>
-#include <intelblocks/systemagent.h>
-#include <intelblocks/tco.h>
-#include <intelblocks/thermal.h>
-#include <intelpch/lockdown.h>
-#include <soc/p2sb.h>
-#include <soc/pci_devs.h>
-#include <soc/pcr_ids.h>
-#include <soc/pm.h>
-#include <soc/smbus.h>
-#include <soc/soc_chip.h>
-#include <soc/systemagent.h>
-#include <spi-generic.h>
-#include <timer.h>
-
-static void pch_finalize(void)
-{
-	/* TCO Lock down */
-	tco_lockdown();
-
-	pmc_clear_pmcon_sts();
-}
-
-static void tbt_finalize(void)
-{
-	int i;
-	const struct device *dev;
-
-	/* Disable Thunderbolt PCIe root ports bus master */
-	for (i = 0; i < NUM_TBT_FUNCTIONS; i++) {
-		dev = pcidev_path_on_root(PCI_DEVFN_TBT(i));
-		if (dev)
-			pci_dev_disable_bus_master(dev);
-	}
-}
-
-static void sa_finalize(void)
-{
-	if (get_lockdown_config() == CHIPSET_LOCKDOWN_COREBOOT)
-		sa_lock_pam();
-}
-
-static void heci_finalize(void)
-{
-	heci_set_to_d0i3();
-	if (CONFIG(DISABLE_HECI1_AT_PRE_BOOT))
-		heci1_disable();
-}
-
-static void soc_finalize(void *unused)
-{
-	printk(BIOS_DEBUG, "Finalizing chipset.\n");
-
-	pch_finalize();
-	apm_control(APM_CNT_FINALIZE);
-	tbt_finalize();
-	sa_finalize();
-	if (CONFIG(USE_FSP_NOTIFY_PHASE_READY_TO_BOOT) &&
-			 CONFIG(USE_FSP_NOTIFY_PHASE_END_OF_FIRMWARE))
-		heci_finalize();
-
-	/* Indicate finalize step with post code */
-	post_code(POSTCODE_OS_BOOT);
-}
-
-BOOT_STATE_INIT_ENTRY(BS_OS_RESUME, BS_ON_ENTRY, soc_finalize, NULL);
-/*
- * The purpose of this change is to accommodate more time to push out sending
- * CSE EOP messages at post.
- */
-BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_BOOT, BS_ON_ENTRY, soc_finalize, NULL);

From 1b5df51c51101826b4a0fd731884fcd4b69f931e Mon Sep 17 00:00:00 2001
From: Jeremy Compostella <jeremy.compostella@intel.com>
Date: Mon, 2 Mar 2026 13:22:43 -0800
Subject: [PATCH 3610/3886] soc/intel: Fix Kconfig select order

Sort the SOC_INTEL_COMMON_FEATURE_* select statements alphabetically.

Change-Id: I314bbced381ecea969054a0d2b841ef68f1efc58
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91513
Reviewed-by: Pranava Y N <pranavayn@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Huang, Cliff <cliff.huang@intel.com>
---
 src/soc/intel/alderlake/Kconfig   | 2 +-
 src/soc/intel/jasperlake/Kconfig  | 2 +-
 src/soc/intel/meteorlake/Kconfig  | 2 +-
 src/soc/intel/pantherlake/Kconfig | 2 +-
 src/soc/intel/tigerlake/Kconfig   | 2 +-
 5 files changed, 5 insertions(+), 5 deletions(-)

diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig
index 91058e8ed3..334ea26e5b 100644
--- a/src/soc/intel/alderlake/Kconfig
+++ b/src/soc/intel/alderlake/Kconfig
@@ -88,13 +88,13 @@ config SOC_INTEL_ALDERLAKE
 	select SOC_INTEL_COMMON_FEATURE_ESPI
 	select SOC_INTEL_COMMON_FEATURE_GLOBAL_RESET_CSE_PMC
 	select SOC_INTEL_COMMON_FEATURE_GSPI_DEVFN
+	select SOC_INTEL_COMMON_FEATURE_I2C_DEVFN
 	select SOC_INTEL_COMMON_FEATURE_LOCKDOWN
 	select SOC_INTEL_COMMON_FEATURE_PMUTIL
 	select SOC_INTEL_COMMON_FEATURE_SMIHANDLER
 	select SOC_INTEL_COMMON_FEATURE_SOUNDWIRE
 	select SOC_INTEL_COMMON_FEATURE_SPI_DEVFN
 	select SOC_INTEL_COMMON_FEATURE_SPI_DEVFN_PSF
-	select SOC_INTEL_COMMON_FEATURE_I2C_DEVFN
 	select SOC_INTEL_COMMON_FEATURE_UART_DEVICES
 	select SOC_INTEL_COMMON_FSP_RESET
 	select SOC_INTEL_COMMON_PCH_CLIENT
diff --git a/src/soc/intel/jasperlake/Kconfig b/src/soc/intel/jasperlake/Kconfig
index 6f90f28a95..a9b19b9a12 100644
--- a/src/soc/intel/jasperlake/Kconfig
+++ b/src/soc/intel/jasperlake/Kconfig
@@ -59,8 +59,8 @@ config SOC_INTEL_JASPERLAKE
 	select SOC_INTEL_COMMON_FEATURE_ESPI
 	select SOC_INTEL_COMMON_FEATURE_GLOBAL_RESET_CSE_PMC
 	select SOC_INTEL_COMMON_FEATURE_GSPI_DEVFN
-	select SOC_INTEL_COMMON_FEATURE_SPI_DEVFN
 	select SOC_INTEL_COMMON_FEATURE_I2C_DEVFN
+	select SOC_INTEL_COMMON_FEATURE_SPI_DEVFN
 	select SOC_INTEL_COMMON_FEATURE_UART_DEVICES
 	select SOC_INTEL_COMMON_FSP_RESET
 	select SOC_INTEL_COMMON_PCH_CLIENT
diff --git a/src/soc/intel/meteorlake/Kconfig b/src/soc/intel/meteorlake/Kconfig
index 9bdeea0b8d..e5abfc0762 100644
--- a/src/soc/intel/meteorlake/Kconfig
+++ b/src/soc/intel/meteorlake/Kconfig
@@ -91,13 +91,13 @@ config SOC_INTEL_METEORLAKE
 	select SOC_INTEL_COMMON_FEATURE_FINALIZE
 	select SOC_INTEL_COMMON_FEATURE_GLOBAL_RESET_CSE_PMC
 	select SOC_INTEL_COMMON_FEATURE_GSPI_DEVFN
+	select SOC_INTEL_COMMON_FEATURE_I2C_DEVFN
 	select SOC_INTEL_COMMON_FEATURE_LOCKDOWN
 	select SOC_INTEL_COMMON_FEATURE_PMUTIL
 	select SOC_INTEL_COMMON_FEATURE_SMIHANDLER
 	select SOC_INTEL_COMMON_FEATURE_SOUNDWIRE
 	select SOC_INTEL_COMMON_FEATURE_SPI_DEVFN
 	select SOC_INTEL_COMMON_FEATURE_SPI_DEVFN_PSF
-	select SOC_INTEL_COMMON_FEATURE_I2C_DEVFN
 	select SOC_INTEL_COMMON_FEATURE_UART_DEVICES
 	select SOC_INTEL_COMMON_BASECODE
 	select SOC_INTEL_COMMON_BASECODE_RAMTOP
diff --git a/src/soc/intel/pantherlake/Kconfig b/src/soc/intel/pantherlake/Kconfig
index e85d80cddd..00616f14a5 100644
--- a/src/soc/intel/pantherlake/Kconfig
+++ b/src/soc/intel/pantherlake/Kconfig
@@ -101,13 +101,13 @@ config SOC_INTEL_PANTHERLAKE_BASE
 	select SOC_INTEL_COMMON_FEATURE_FINALIZE
 	select SOC_INTEL_COMMON_FEATURE_GLOBAL_RESET_CSE_PMC
 	select SOC_INTEL_COMMON_FEATURE_GSPI_DEVFN
+	select SOC_INTEL_COMMON_FEATURE_I2C_DEVFN
 	select SOC_INTEL_COMMON_FEATURE_LOCKDOWN
 	select SOC_INTEL_COMMON_FEATURE_PMUTIL
 	select SOC_INTEL_COMMON_FEATURE_SMIHANDLER
 	select SOC_INTEL_COMMON_FEATURE_SOUNDWIRE
 	select SOC_INTEL_COMMON_FEATURE_SPI_DEVFN
 	select SOC_INTEL_COMMON_FEATURE_SPI_DEVFN_PSF
-	select SOC_INTEL_COMMON_FEATURE_I2C_DEVFN
 	select SOC_INTEL_COMMON_FEATURE_UART_DEVICES
 	select SOC_INTEL_COMMON_FSP_RESET
 	select SOC_INTEL_COMMON_PCH_CLIENT
diff --git a/src/soc/intel/tigerlake/Kconfig b/src/soc/intel/tigerlake/Kconfig
index 81f01e3363..406d3ffb93 100644
--- a/src/soc/intel/tigerlake/Kconfig
+++ b/src/soc/intel/tigerlake/Kconfig
@@ -76,11 +76,11 @@ config SOC_INTEL_TIGERLAKE
 	select SOC_INTEL_COMMON_FEATURE_ESPI
 	select SOC_INTEL_COMMON_FEATURE_GLOBAL_RESET_CSE_PMC
 	select SOC_INTEL_COMMON_FEATURE_GSPI_DEVFN
+	select SOC_INTEL_COMMON_FEATURE_I2C_DEVFN
 	select SOC_INTEL_COMMON_FEATURE_SMIHANDLER
 	select SOC_INTEL_COMMON_FEATURE_SOUNDWIRE
 	select SOC_INTEL_COMMON_FEATURE_SPI_DEVFN
 	select SOC_INTEL_COMMON_FEATURE_SPI_DEVFN_PSF
-	select SOC_INTEL_COMMON_FEATURE_I2C_DEVFN
 	select SOC_INTEL_COMMON_FEATURE_UART_DEVICES
 	select SOC_INTEL_COMMON_FSP_RESET
 	select SOC_INTEL_COMMON_PCH_CLIENT

From 2f88fec014074b19fdd55c17dcc43f9770340a6b Mon Sep 17 00:00:00 2001
From: KangMin Wang <kangmin.wang@luxshare.corp-partner.google.com>
Date: Tue, 3 Mar 2026 14:54:35 +0800
Subject: [PATCH 3611/3886] mb/google/bluey/mica: Add TPM I2C and EC SPI
 configuration

Communication with GSC and EC is abnormal because Mica is
missing the following configurations: DRIVER_TPM_I2C_BUS,
EC_GOOGLE_CHROMEEC_SPI_BUS,and MAINBOARD_GPIO_PIN_FOR_GSC_AP_INTERRUPT.

BUG=b:489062509,b:489264026
TEST=build mica board, flash to Quenbi to verify the GSC and
EC communication functionality.
Check if there are any further abnormalities in the bootup log:
For GSC:
Probing TPM I2C: Cr50 TPM IRQ timeout!
For EC:
crosec_spi_io: Timeout waiting for framing byte.

Change-Id: I2ff158968f946eb780d593c8b1d1e8b07f95ce8a
Signed-off-by: KangMin Wang <kangmin.wang@luxshare.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91517
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Derek Huang <derekhuang@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
---
 src/mainboard/google/bluey/Kconfig | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/src/mainboard/google/bluey/Kconfig b/src/mainboard/google/bluey/Kconfig
index 45017a4e01..c76878cf1b 100644
--- a/src/mainboard/google/bluey/Kconfig
+++ b/src/mainboard/google/bluey/Kconfig
@@ -175,6 +175,7 @@ config DRIVER_TPM_I2C_BUS
 	hex
 	default 0xa if BOARD_GOOGLE_MODEL_QUENBI
 	default 0xa if BOARD_GOOGLE_MODEL_QUARTZ
+	default 0xa if BOARD_GOOGLE_MODEL_MICA
 	default 0x10
 
 config DRIVER_TPM_I2C_ADDR
@@ -185,6 +186,7 @@ config EC_GOOGLE_CHROMEEC_SPI_BUS
 	hex
 	default 0xd if BOARD_GOOGLE_MODEL_QUENBI
 	default 0xd if BOARD_GOOGLE_MODEL_QUARTZ
+	default 0xd if BOARD_GOOGLE_MODEL_MICA
 	default 0xb
 
 config MAINBOARD_GPIO_PIN_FOR_TOUCHPAD_POWER
@@ -200,6 +202,7 @@ config MAINBOARD_GPIO_PIN_FOR_GSC_AP_INTERRUPT
 	int
 	default 91 if BOARD_GOOGLE_MODEL_QUENBI
 	default 91 if BOARD_GOOGLE_MODEL_QUARTZ
+	default 91 if BOARD_GOOGLE_MODEL_MICA
 	default 34
 	help
 	  This option specifies the GPIO pin number on the mainboard that is

From 510e43d8bd233b7221e8431f95ed70dc2aea9b9f Mon Sep 17 00:00:00 2001
From: Jarried Lin <jarried.lin@mediatek.corp-partner.google.com>
Date: Wed, 4 Mar 2026 12:52:10 +0800
Subject: [PATCH 3612/3886] soc/mediatek/mt8196: Move WATCHDOG_TOMBSTONE from
 SRAM to SRAM_L2C

The purpose of the WATCHDOG_TOMBSTONE section is to temporarily record
the watchdog timeout event, before triggering the reboot. Then, in the
next boot, if WATCHDOG_TOMBSTONE contains the watchdog event magic, then
a watchdog event will be added to the event log.

The flow relies on the fact that the WATCHDOG_TOMBSTONE section can be
preserved across AP resets. However, for MT8196, the whole SRAM region
will be powered down during AP reset via GPIO AP_SYSRST_ODL (SYSRSTB).

On MT8196, L3C (used as SRAM_L2C) is powered on by default. Also, per
MT8196 PMIC configuration, a SYSRSTB reset will retain the L3C power.
Therefore, region data in SRAM_L2C can be preserved across AP resets.

Fix the WATCHDOG_TOMBSTONE preservation by moving it to SRAM_L2C.
Reduce PRERAM_CBMEM_CONSOLE by 1K for WATCHDOG_TOMBSTONE.

BUG=b:481854714
TEST=watchdog event added to eventlog on WDT timeout:
17 | 2026-03-04 08:57:17+0000 | Hardware watchdog reset
TEST=cbmem logs preserved on WDT timeout

Change-Id: I630d1749e1a743069f2d814efe0a4994889a2a3f
Signed-off-by: Jarried Lin <jarried.lin@mediatek.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91540
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/soc/mediatek/mt8196/include/soc/memlayout.ld | 9 ++++++---
 1 file changed, 6 insertions(+), 3 deletions(-)

diff --git a/src/soc/mediatek/mt8196/include/soc/memlayout.ld b/src/soc/mediatek/mt8196/include/soc/memlayout.ld
index 2bd3a26b71..48f4dc77ce 100644
--- a/src/soc/mediatek/mt8196/include/soc/memlayout.ld
+++ b/src/soc/mediatek/mt8196/include/soc/memlayout.ld
@@ -13,13 +13,15 @@
 
 SECTIONS
 {
-	/* MT8196 has 256KB SRAM. */
+	/* MT8196 has 256KB SRAM. Per HW design, on SoC reset via GPIO
+	 * AP_SYSRST_ODL (SYSRSTB), SRAM will be powered down. That means
+	 * SRAM data will be lost across SoC resets.
+	 */
 	SRAM_START(0x00100000)
 	/* Regions that need to stay in SRAM. */
 	TTB(0x00100000, 28K)
 	DMA_COHERENT(0x00107000, 4K)
 	STACK(0x00108000, 15K)
-	WATCHDOG_TOMBSTONE(0x0010bc00, 4)
 	EARLY_INIT(0x0010bc10, 128)
 	/* EMPTY(0x0010bc90, 29K - 144) */
 	/*
@@ -56,7 +58,8 @@ SECTIONS
 	#endif
 	OVERLAP_DECOMPRESSOR_VERSTAGE_ROMSTAGE(0x02096000, 272K)
 	PRERAM_CBFS_CACHE(0x020DA000, 48K)
-	PRERAM_CBMEM_CONSOLE(0x020E6000, 340K)
+	PRERAM_CBMEM_CONSOLE(0x020E6000, 339K)
+	WATCHDOG_TOMBSTONE(0x0213AC00, 4)
 	FSP_ROMSTAGE_INIT_CODE(0x02140000, 64K)
 	SRAM_L2C_END(0x02200000)
 

From a300b135c37bfee521282ccecb3bee4a8311f3c0 Mon Sep 17 00:00:00 2001
From: Jarried Lin <jarried.lin@mediatek.corp-partner.google.com>
Date: Wed, 4 Mar 2026 13:06:14 +0800
Subject: [PATCH 3613/3886] soc/mediatek/mt8196: Call mtk_mmu_disable_l2c_sram
 via boot state

The commit 7072f42c08f7 ("soc/mediatek/mt8196: Move WATCHDOG_TOMBSTONE
from SRAM to SRAM_L2C") move WATCHDOG_TOMBSTONE from SRAM to SRAM_L2C
causes elog_handle_watchdog_tombstone (BS_POST_DEVICE, BS_ON_ENTRY) to
be invoked after mtk_mmu_disable_l2c_sram. As a result, the watchdog
event magic value in WATCHDOG_TOMBSTONE is cleared before it can be
processed, which is incorrect behavior.

So we refactor the mtk_mmu_disable_l2c_sram to be called as a boot state
entry (BS_POST_DEVICE, BS_ON_EXIT) instead of directly from soc_init.
This ensures that mtk_mmu_disable_l2c_sram will be executed after
elog_handle_watchdog_tombstone.

BUG=b:481854714
TEST=watchdog event added to eventlog on WDT timeout (triggered via echo > /dev/watchdog)
TEST=cbmem logs preserved on WDT timeout

Change-Id: I69ef567ab73f2f7006bb249cb577f377d4720909
Signed-off-by: Jarried Lin <jarried.lin@mediatek.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91539
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
---
 src/soc/mediatek/mt8196/soc.c | 7 ++++++-
 1 file changed, 6 insertions(+), 1 deletion(-)

diff --git a/src/soc/mediatek/mt8196/soc.c b/src/soc/mediatek/mt8196/soc.c
index c739998383..1e228c8a54 100644
--- a/src/soc/mediatek/mt8196/soc.c
+++ b/src/soc/mediatek/mt8196/soc.c
@@ -70,10 +70,15 @@ static void fsp_init(void *arg)
 
 BOOT_STATE_INIT_ENTRY(BS_DEV_INIT, BS_ON_ENTRY, fsp_init, NULL);
 
-static void soc_init(struct device *dev)
+static void mmu_disable_l2c_sram(void *unused)
 {
 	mtk_mmu_disable_l2c_sram();
+}
 
+BOOT_STATE_INIT_ENTRY(BS_POST_DEVICE, BS_ON_EXIT, mmu_disable_l2c_sram, NULL);
+
+static void soc_init(struct device *dev)
+{
 	if (dpm_init())
 		printk(BIOS_ERR, "dpm init failed, DVFS may not work\n");
 	if (spm_init())

From 8a4937bf8fffd08ecf9643d8b3217df6aa1cc855 Mon Sep 17 00:00:00 2001
From: Yang Wu <wuyang5@huaqin.corp-partner.google.com>
Date: Fri, 13 Feb 2026 16:05:54 +0800
Subject: [PATCH 3614/3886] soc/mediatek: Add mtk_mipi_panel_poweroff()

Introduce mtk_mipi_panel_poweroff() in common display layer and
mtk_dsi_panel_poweroff() in DSI driver. The DSI mode flags are
saved during init and reused for the power-off command path.

BUG=b:474187570
TEST=emerge-jedi coreboot chromeos-bootimage
BRANCH=skywalker

Change-Id: Ic684822bc5f20d3e2f5ce3d44035c902a2b44184
Signed-off-by: Yang Wu <wuyang5@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91432
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Zhengqiao Xia <xiazhengqiao@huaqin.corp-partner.google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
---
 src/soc/mediatek/common/display.c             | 11 +++++
 src/soc/mediatek/common/dsi_common.c          | 47 +++++++++++++++++++
 src/soc/mediatek/common/include/soc/display.h |  1 +
 .../mediatek/common/include/soc/display_dsi.h |  1 +
 4 files changed, 60 insertions(+)

diff --git a/src/soc/mediatek/common/display.c b/src/soc/mediatek/common/display.c
index 3b9d8be96c..d1fce217a6 100644
--- a/src/soc/mediatek/common/display.c
+++ b/src/soc/mediatek/common/display.c
@@ -16,6 +16,7 @@
 #include <symbols.h>
 #include <timestamp.h>
 
+static u32 dsi_mode_flags;
 static struct panel_serializable_data *mipi_data;
 
 static struct panel_serializable_data *get_mipi_cmd_from_cbfs(struct panel_description *desc)
@@ -172,6 +173,8 @@ int mtk_display_init(void)
 			lanes = 4;
 		}
 
+		dsi_mode_flags = mipi_dsi_flags;
+
 		if (mtk_dsi_init(mipi_dsi_flags, MIPI_DSI_FMT_RGB888, lanes, &edid,
 				 mipi_data ? mipi_data->init : NULL) < 0) {
 			printk(BIOS_ERR, "%s: Failed in DSI init\n", __func__);
@@ -219,6 +222,14 @@ int mtk_display_init(void)
 	return 0;
 }
 
+int mtk_mipi_panel_poweroff(void)
+{
+	if (!mipi_data)
+		return 0;
+
+	return mtk_dsi_panel_poweroff(dsi_mode_flags, mipi_data->poweroff);
+}
+
 u32 mtk_get_vrefresh(const struct edid *edid)
 {
 	u32 width = edid->mode.ha;
diff --git a/src/soc/mediatek/common/dsi_common.c b/src/soc/mediatek/common/dsi_common.c
index 6f8d640845..04dc0a85c3 100644
--- a/src/soc/mediatek/common/dsi_common.c
+++ b/src/soc/mediatek/common/dsi_common.c
@@ -444,6 +444,11 @@ static void mtk_dsi_reset_phy(struct dsi_regs *const dsi_reg)
 	clrbits32(&dsi_reg->dsi_con_ctrl, DPHY_RESET);
 }
 
+static void mtk_dsi_stop(struct dsi_regs *dsi)
+{
+	write32(&dsi->dsi_start, 0);
+}
+
 int mtk_dsi_init(u32 mode_flags, u32 format, u32 lanes, const struct edid *edid,
 		 const u8 *init_commands)
 {
@@ -502,3 +507,45 @@ int mtk_dsi_init(u32 mode_flags, u32 format, u32 lanes, const struct edid *edid,
 
 	return 0;
 }
+
+int mtk_dsi_panel_poweroff(u32 mode_flags, const u8 *poweroff_cmds)
+{
+	int ret;
+	unsigned int num_dsi = (mode_flags & MIPI_DSI_DUAL_CHANNEL) ? 2 : 1;
+
+	/* Stop DSI-0 engine */
+	mtk_dsi_stop(dsi_mipi_regs[0].dsi_reg);
+
+	/* Wait for DSI engines to become idle */
+	for (unsigned int i = 0; i < num_dsi; i++) {
+		struct dsi_regs *dsi = dsi_mipi_regs[i].dsi_reg;
+
+		if (!wait_ms(20, !(read32(&dsi->dsi_intsta) & DSI_BUSY))) {
+			u32 intsta = read32(&dsi->dsi_intsta);
+
+			printk(BIOS_ERR, "%s: Timeout (20ms) waiting for DSI-%d idle "
+			       "and the panel may not power-off properly. "
+			       "DSI_INTSTA=0x%08x.\n",
+			       __func__, i, intsta);
+			return -1;
+		}
+
+		write32(&dsi->dsi_intsta, 0);
+		write32(&dsi->dsi_mode_ctrl, CMD_MODE);
+	}
+
+	/* Send panel poweroff commands */
+	ret = mipi_panel_parse_commands(poweroff_cmds, mtk_dsi_cmdq,
+					&mode_flags);
+
+	/* Final shutdown: stop + disable PHY */
+	mtk_dsi_stop(dsi_mipi_regs[0].dsi_reg);
+
+	for (unsigned int i = 0; i < num_dsi; i++) {
+		struct dsi_regs *dsi = dsi_mipi_regs[i].dsi_reg;
+
+		write32(&dsi->dsi_phy_lccon, 0x0);
+	}
+
+	return ret;
+}
diff --git a/src/soc/mediatek/common/include/soc/display.h b/src/soc/mediatek/common/include/soc/display.h
index 3e3b4a2164..87a6a04d9d 100644
--- a/src/soc/mediatek/common/include/soc/display.h
+++ b/src/soc/mediatek/common/include/soc/display.h
@@ -32,6 +32,7 @@ struct panel_description {
 struct panel_description *get_active_panel(void);
 void mtk_display_disable_secure_mode(void);
 int mtk_display_init(void);
+int mtk_mipi_panel_poweroff(void);
 
 void mtk_ddp_init(void);
 u32 mtk_get_vrefresh(const struct edid *edid);
diff --git a/src/soc/mediatek/common/include/soc/display_dsi.h b/src/soc/mediatek/common/include/soc/display_dsi.h
index 62bdb3cca3..6a51dca55a 100644
--- a/src/soc/mediatek/common/include/soc/display_dsi.h
+++ b/src/soc/mediatek/common/include/soc/display_dsi.h
@@ -51,5 +51,6 @@ enum {
 /* Public API for common display code (display.c). */
 int mtk_dsi_init(u32 mode_flags, u32 format, u32 lanes, const struct edid *edid,
 		 const u8 *init_commands);
+int mtk_dsi_panel_poweroff(u32 mode_flags, const u8 *poweroff_cmds);
 
 #endif /* SOC_MEDIATEK_DISPLAY_DSI_H */

From b5a703e5a0fe8fc953b3e351983105d140dd33ba Mon Sep 17 00:00:00 2001
From: Yang Wu <wuyang5@huaqin.corp-partner.google.com>
Date: Mon, 2 Mar 2026 20:26:54 +0800
Subject: [PATCH 3615/3886] mb/google/skywalker: Add
 mainboard_prepare_cr50_reset()

The LCD MIPI panel requires proper power-off commands before reset.
Skipping them may cause overpotential conditions, leading to image
stickiness or flicker.

On MTK platforms, CR50 reset is the only reboot path in coreboot.
Add mainboard_prepare_cr50_reset() implementation on skywalker to
power off the MIPI panel before issuing CR50 reset.

BUG=b:474187570
TEST=emerge-jedi coreboot chromeos-bootimage
BRANCH=skywalker

Change-Id: I46a654e03ca2e7374cdaf05729f12b182669a64f
Signed-off-by: Yang Wu <wuyang5@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91507
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Zhengqiao Xia <xiazhengqiao@huaqin.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/google/skywalker/mainboard.c | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/src/mainboard/google/skywalker/mainboard.c b/src/mainboard/google/skywalker/mainboard.c
index a36e3fa7a2..f7191e9140 100644
--- a/src/mainboard/google/skywalker/mainboard.c
+++ b/src/mainboard/google/skywalker/mainboard.c
@@ -19,6 +19,7 @@
 #include <soc/spm_common.h>
 #include <soc/storage.h>
 #include <soc/usb.h>
+#include <vendorcode/google/chromeos/chromeos.h>
 
 #include "gpio.h"
 #include "panel.h"
@@ -107,6 +108,13 @@ static void power_on_fpmcu(void)
 	gpio_output(GPIO_FP_RST_1V8_S3_L, 1);
 }
 
+void mainboard_prepare_cr50_reset(void)
+{
+	printk(BIOS_INFO, "%s: Powering MIPI panel off\n", __func__);
+	if (mtk_mipi_panel_poweroff() < 0)
+		printk(BIOS_ERR, "%s: Failed to power off MIPI panel\n", __func__);
+}
+
 enum mtk_storage_type mainboard_get_storage_type(void)
 {
 	uint32_t index = storage_id();

From 23db1b368635fe0371c93ff26a729f63ca0bfdbd Mon Sep 17 00:00:00 2001
From: KangMin Wang <kangmin.wang@luxshare.corp-partner.google.com>
Date: Wed, 4 Mar 2026 11:07:27 +0800
Subject: [PATCH 3616/3886] mb/google/bluey/mica: Add mainboard part number

Add MAINBOARD_PART_NUMBER config for mica variant.

BUG=none
TEST=emerge-bluey coreboot

Change-Id: I96ace7c6ed9b9f4892ed110134b2580516ec36bd
Signed-off-by: KangMin Wang <kangmin.wang@luxshare.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91538
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Derek Huang <derekhuang@google.com>
---
 src/mainboard/google/bluey/Kconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/src/mainboard/google/bluey/Kconfig b/src/mainboard/google/bluey/Kconfig
index c76878cf1b..d5ecf88a26 100644
--- a/src/mainboard/google/bluey/Kconfig
+++ b/src/mainboard/google/bluey/Kconfig
@@ -169,6 +169,7 @@ config MAINBOARD_PART_NUMBER
 	default "Quenbi" if BOARD_GOOGLE_QUENBI
 	default "QuenbiH" if BOARD_GOOGLE_QUENBIH
 	default "Quartz" if BOARD_GOOGLE_MODEL_QUARTZ
+	default "Mica" if BOARD_GOOGLE_MODEL_MICA
 
 config DRIVER_TPM_I2C_BUS
 	depends on I2C_TPM

From dfc2c45ff4e22a150593d5274186d4271a6b606c Mon Sep 17 00:00:00 2001
From: Ivi Ballou <iviballou@gmail.com>
Date: Wed, 25 Feb 2026 17:59:57 +0200
Subject: [PATCH 3617/3886] util/inteltool: Add support for Wellsburg

Added Wellsburg (C610 / X99) support for the following tables:
- GPIOS
- RCBA
- PMBASE
- LPC
- SPI

Change-Id: I1ee52b50b0093f38b00bfbaa003eecc96bd1874e
Signed-off-by: Ivi Ballou <iviballou@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91417
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 util/inteltool/gpio.c      |  5 +++-
 util/inteltool/inteltool.c |  3 ++
 util/inteltool/inteltool.h |  3 ++
 util/inteltool/lpc.c       | 59 ++++++++++++++++++++++++++++++++++++++
 util/inteltool/powermgt.c  |  6 +++-
 util/inteltool/rootcmplx.c |  3 ++
 util/inteltool/spi.c       |  6 ++++
 7 files changed, 83 insertions(+), 2 deletions(-)

diff --git a/util/inteltool/gpio.c b/util/inteltool/gpio.c
index c0005bf802..891b3abffd 100644
--- a/util/inteltool/gpio.c
+++ b/util/inteltool/gpio.c
@@ -228,7 +228,7 @@ static const io_register_t pch_gpio_registers[] = {
 	{ 0x40, 4, "GPIO_USE_SEL3" },
 	{ 0x44, 4, "GP_IO_SEL3" },
 	{ 0x48, 4, "GP_LVL3" },
-	{ 0x4c, 4, "RESERVED" },
+	{ 0x4c, 4, "GPI_INV2" }, // GPIO Signal Invert 2
 	{ 0x50, 4, "RESERVED" },
 	{ 0x54, 4, "RESERVED" },
 	{ 0x58, 4, "RESERVED" },
@@ -861,6 +861,9 @@ int print_gpios(struct pci_dev *sb, int show_all, int show_diffs)
 	case PCI_DEVICE_ID_INTEL_HM97:
 	case PCI_DEVICE_ID_INTEL_Z97:
 	case PCI_DEVICE_ID_INTEL_H97:
+	case PCI_DEVICE_ID_INTEL_WELLSBURG_SUPER:
+	case PCI_DEVICE_ID_INTEL_WELLSBURG_C612:
+	case PCI_DEVICE_ID_INTEL_WELLSBURG_X99:
 		gpiobase = pci_read_word(sb, 0x48) & 0xfffc;
 		gpio_registers = pch_gpio_registers;
 		size = ARRAY_SIZE(pch_gpio_registers);
diff --git a/util/inteltool/inteltool.c b/util/inteltool/inteltool.c
index 66d42a903d..05d5c092fd 100644
--- a/util/inteltool/inteltool.c
+++ b/util/inteltool/inteltool.c
@@ -447,6 +447,9 @@ static const struct {
 	{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_Z97, "Z97"},
 	{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_H97, "H97"},
 	{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_APL_LPC, "Apollo Lake" },
+	{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WELLSBURG_SUPER, "Wellsburg Super SKU" },
+	{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WELLSBURG_C612, "Wellsburg C612" },
+	{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WELLSBURG_X99, "Wellsburg X99" },
 	{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_DNV_LPC, "Denverton" },
 	{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_GLK_LPC, "Gemini Lake" },
 	{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_H510, "H510" },
diff --git a/util/inteltool/inteltool.h b/util/inteltool/inteltool.h
index 3a173da19c..e38fb190bb 100644
--- a/util/inteltool/inteltool.h
+++ b/util/inteltool/inteltool.h
@@ -309,6 +309,9 @@ static inline uint32_t inl(unsigned port)
 #define PCI_DEVICE_ID_INTEL_HM97		0x8cc3
 #define PCI_DEVICE_ID_INTEL_Z97			0x8cc4
 #define PCI_DEVICE_ID_INTEL_H97			0x8cc6
+#define PCI_DEVICE_ID_INTEL_WELLSBURG_SUPER		0x8d40
+#define PCI_DEVICE_ID_INTEL_WELLSBURG_C612		0x8d44
+#define PCI_DEVICE_ID_INTEL_WELLSBURG_X99		0x8d47
 
 #define PCI_DEVICE_ID_INTEL_82X58		0x3405
 #define PCI_DEVICE_ID_INTEL_SCH_POULSBO	0x8100
diff --git a/util/inteltool/lpc.c b/util/inteltool/lpc.c
index 0d21bedc80..af452a24d1 100644
--- a/util/inteltool/lpc.c
+++ b/util/inteltool/lpc.c
@@ -9,6 +9,47 @@
 
 #define SUNRISE_LPC_BC	0xdc
 
+static const io_register_t c610_lpc_cfg_registers[] = {
+	{0x00, 2, "VID"},          // Vendor Identification
+	{0x02, 2, "DID"},          // Device Identification
+	{0x04, 2, "PCICMD"},       // PCI Command
+	{0x06, 2, "PCISTS"},       // PCI Status
+	{0x08, 1, "RID"},          // Revision Identification
+	{0x09, 1, "PI"},           // Programming Interface
+	{0x0A, 1, "SCC"},          // Sub Class Code
+	{0x0B, 1, "BCC"},          // Base Class Code
+	{0x0D, 1, "PLT"},          // Primary Latency Timer
+	{0x0E, 1, "HEADTYP"},      // Header Type
+	{0x2C, 4, "SS"},           // Sub System Identifiers
+	{0x40, 4, "PMBASE"},       // ACPI Base Address
+	{0x44, 1, "ACPI_CNTL"},    // ACPI Control
+	{0x48, 4, "GPIOBASE"},     // ACPI Base Address
+	{0x4C, 1, "GC"},           // GPIO Control
+	{0x60, 4, "PIRQ[n]_ROUT"}, // PIRQ[A-D] Routing Control
+	{0x64, 1, "SIRQ_CNTL"},    // Serial IRQ Control
+	{0x68, 4, "PIRQ[n]_ROUT"}, // PIRQ[E-H] Routing Control
+	{0x6C, 2, "LPC_IBDF"},     // IOxAPIC Bus:Device:Function
+	{0x70, 8, "LPC_HnBDF"},    // HPET Configuration
+	{0x80, 1, "LPC_I/O_DEC"},  // I/O Decode
+	{0x82, 2, "LPC_EN"},       // LPC I/F Enables
+	{0x84, 4, "GEN1_DEC"},     // LPC I/F Generic Decode Range 1
+	{0x88, 4, "GEN2_DEC"},     // LPC I/F Generic Decode Range 2
+	{0x8C, 4, "GEN3_DEC"},     // LPC I/F Generic Decode Range 3
+	{0x90, 4, "GEN4_DEC"},     // LPC I/F Generic Decode Range 4 00000000h R/W
+	{0x94, 4, "ULKMC"},        // USB Legacy Keyboard / Mouse Control 00000000h RO, R/WC, R/W, RW1L
+	{0x98, 4, "LGMR LPC"},     // I/F Generic Memory Range 00000000h R/W
+	{0xD0, 4, "BIOS_SEL1"},    // BIOS Select
+	{0xD4, 2, "BIOS_SEL2"},    // BIOS Select
+	{0xD8, 2, "BIOS_DEC_EN1"}, // BIOS Decode Enable
+	{0xDC, 1, "BIOS_CNTL"},    // BIOS Control
+	{0xE0, 2, "FDCAP"},        // Feature Detection Capability ID
+	{0xE2, 1, "FDLEN"},        // Feature Detection Capability Length
+	{0xE3, 1, "FDVER"},        // Feature Detection Version
+	{0xE4, 4, "FVECIDX"},      // Feature Vector Index
+	{0xE8, 4, "FVECD"},        // Feature Vector Data
+	{0xF0, 4, "RCBA"},         // Root Complex Base Address
+};
+
 static const io_register_t sunrise_lpc_cfg_registers[] = {
 	{0x00, 4, "ID"},
 	{0x04, 2, "CMD"},
@@ -109,6 +150,17 @@ int print_lpc(struct pci_dev *sb, struct pci_access *pacc)
 	printf("\n========== LPC/eSPI =========\n\n");
 
 	switch (sb->device_id) {
+	case PCI_DEVICE_ID_INTEL_WELLSBURG_SUPER:
+	case PCI_DEVICE_ID_INTEL_WELLSBURG_C612:
+	case PCI_DEVICE_ID_INTEL_WELLSBURG_X99:
+		dev = pci_get_dev(pacc, sb->domain, sb->bus, sb->dev, 0);
+		if (!dev) {
+			printf("LPC interface not found.\n");
+			return 1;
+		}
+		cfg_registers = c610_lpc_cfg_registers;
+		cfg_registers_size = ARRAY_SIZE(c610_lpc_cfg_registers);
+		break;
 	case PCI_DEVICE_ID_INTEL_H110:
 	case PCI_DEVICE_ID_INTEL_H170:
 	case PCI_DEVICE_ID_INTEL_Z170:
@@ -212,6 +264,13 @@ int print_lpc(struct pci_dev *sb, struct pci_access *pacc)
 				pci_read_long(dev, cfg_registers[i].addr),
 				cfg_registers[i].name);
 			break;
+		case 3:
+			printf("0x%04x: 0x%04x%02x   (%s)\n",
+				cfg_registers[i].addr,
+				pci_read_word(dev, cfg_registers[i].addr),
+				pci_read_byte(dev, cfg_registers[i].addr + 2),
+				cfg_registers[i].name);
+			break;
 		case 2:
 			printf("0x%04x: 0x%04x     (%s)\n",
 				cfg_registers[i].addr,
diff --git a/util/inteltool/powermgt.c b/util/inteltool/powermgt.c
index 716b85ce03..31b3325223 100644
--- a/util/inteltool/powermgt.c
+++ b/util/inteltool/powermgt.c
@@ -97,7 +97,8 @@ static const io_register_t pch_pm_registers[] = {
 	{ 0x52, 2, "RESERVED" },
 	{ 0x54, 4, "RESERVED" },
 	{ 0x58, 4, "RESERVED" },
-	{ 0x5c, 4, "RESERVED" },
+	{ 0x5c, 2, "ALT_GPI_SMI_EN2" }, // Alternate GPI SMI Enable 2 Register
+	{ 0x5e, 2, "ALT_GPI_SMI_STS2" }, // Alternate GPI SMI Status 2 Register
 	/* The TCO registers start here. */
 	{ 0x60, 2, "TCO_RLD" },
 	{ 0x62, 1, "TCO_DAT_IN" },
@@ -771,6 +772,9 @@ int print_pmbase(struct pci_dev *sb, struct pci_access *pacc)
 	case PCI_DEVICE_ID_INTEL_HM97:
 	case PCI_DEVICE_ID_INTEL_Z97:
 	case PCI_DEVICE_ID_INTEL_H97:
+	case PCI_DEVICE_ID_INTEL_WELLSBURG_SUPER:
+	case PCI_DEVICE_ID_INTEL_WELLSBURG_C612:
+	case PCI_DEVICE_ID_INTEL_WELLSBURG_X99:
 		pmbase = pci_read_word(sb, 0x40) & 0xff80;
 		pm_registers = pch_pm_registers;
 		pm_registers_size = ARRAY_SIZE(pch_pm_registers);
diff --git a/util/inteltool/rootcmplx.c b/util/inteltool/rootcmplx.c
index 46f7858feb..965c492e8d 100644
--- a/util/inteltool/rootcmplx.c
+++ b/util/inteltool/rootcmplx.c
@@ -106,6 +106,9 @@ int print_rcba(struct pci_dev *sb)
 	case PCI_DEVICE_ID_INTEL_HM97:
 	case PCI_DEVICE_ID_INTEL_Z97:
 	case PCI_DEVICE_ID_INTEL_H97:
+	case PCI_DEVICE_ID_INTEL_WELLSBURG_SUPER:
+	case PCI_DEVICE_ID_INTEL_WELLSBURG_C612:
+	case PCI_DEVICE_ID_INTEL_WELLSBURG_X99:
 	case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_PRE:
 	case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_BASE_SKL:
 	case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_Y_PREM_SKL:
diff --git a/util/inteltool/spi.c b/util/inteltool/spi.c
index 6e869a2da9..6d6b500eeb 100644
--- a/util/inteltool/spi.c
+++ b/util/inteltool/spi.c
@@ -321,6 +321,9 @@ static int print_bioscntl(struct pci_dev *sb)
 	case PCI_DEVICE_ID_INTEL_HM97:
 	case PCI_DEVICE_ID_INTEL_Z97:
 	case PCI_DEVICE_ID_INTEL_H97:
+	case PCI_DEVICE_ID_INTEL_WELLSBURG_SUPER:
+	case PCI_DEVICE_ID_INTEL_WELLSBURG_C612:
+	case PCI_DEVICE_ID_INTEL_WELLSBURG_X99:
 	case PCI_DEVICE_ID_INTEL_H110:
 	case PCI_DEVICE_ID_INTEL_H170:
 	case PCI_DEVICE_ID_INTEL_Z170:
@@ -509,6 +512,9 @@ static int print_spibar(struct pci_dev *sb, struct pci_access *pacc) {
 	case PCI_DEVICE_ID_INTEL_HM97:
 	case PCI_DEVICE_ID_INTEL_Z97:
 	case PCI_DEVICE_ID_INTEL_H97:
+	case PCI_DEVICE_ID_INTEL_WELLSBURG_SUPER:
+	case PCI_DEVICE_ID_INTEL_WELLSBURG_C612:
+	case PCI_DEVICE_ID_INTEL_WELLSBURG_X99:
 	case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_PRE:
 	case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_BASE_SKL:
 	case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_Y_PREM_SKL:

From c772a88b1d5a81fdaf1820e6d928a2e7078d877b Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Wed, 4 Mar 2026 09:27:30 +0000
Subject: [PATCH 3618/3886] configs: Remove starbook/adl option table config

This board no longer uses option table, so the config is invalid.

Change-Id: I62268472e9a2020e81c352933aa9bac8bb2fcddd
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91541
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 configs/config.starlabs_starbook_adl_option_table | 8 --------
 1 file changed, 8 deletions(-)
 delete mode 100644 configs/config.starlabs_starbook_adl_option_table

diff --git a/configs/config.starlabs_starbook_adl_option_table b/configs/config.starlabs_starbook_adl_option_table
deleted file mode 100644
index 56211266a1..0000000000
--- a/configs/config.starlabs_starbook_adl_option_table
+++ /dev/null
@@ -1,8 +0,0 @@
-CONFIG_VENDOR_STARLABS=y
-CONFIG_BOARD_STARLABS_STARBOOK_ADL=y
-CONFIG_MAINBOARD_SERIAL_NUMBER="B6I0000"
-CONFIG_USE_OPTION_TABLE=y
-CONFIG_LOCALVERSION="8.42"
-CONFIG_MAINBOARD_USE_LIBGFXINIT=n
-CONFIG_SMMSTORE=y
-CONFIG_SMMSTORE_V2=y

From f12d2997fcde22afdf681a09262f3f819f241055 Mon Sep 17 00:00:00 2001
From: Patrick Rudolph <patrick.rudolph@9elements.com>
Date: Sun, 22 Feb 2026 16:40:28 +0100
Subject: [PATCH 3619/3886] lib/cbfs: Don't include unused LZ4 code to shrink
 postcar stage

When ramstage is not LZ4 compressed then don't include the LZ4
decompressor into postcar stage.

TEST=Reduces postcar size on Lenovo x220 by 1224 bytes.

Change-Id: I51e25d94213b42474c8cedd9e7bae9e81568566d
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91385
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
---
 src/lib/cbfs.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/src/lib/cbfs.c b/src/lib/cbfs.c
index 0c602474b3..25a29a2885 100644
--- a/src/lib/cbfs.c
+++ b/src/lib/cbfs.c
@@ -137,6 +137,9 @@ static inline bool cbfs_lz4_enabled(void)
 	if (ENV_SMM)
 		return false;
 
+	if (ENV_RAMSTAGE_LOADER && !CONFIG(COMPRESS_RAMSTAGE_LZ4))
+		return false;
+
 	return true;
 }
 

From aaddb83491a26f3f6e193d0a287e272485f0b3f7 Mon Sep 17 00:00:00 2001
From: Sowmya Aralguppe <sowmya.aralguppe@intel.com>
Date: Sat, 28 Feb 2026 00:11:52 +0530
Subject: [PATCH 3620/3886] soc/intel/pantherlake: Configure TDC IRMS mode for
 WCL IA domain

Set IA voltage regulator to use IRMS mode with 28 second time window
for more accurate thermal design current measurement.

Ref=:830097_WCL_PDG_SchChk_Rev1p5
BUG=b:None
TEST=Build ocelot and verify that the system boots with the following
VR parameter

[SPEW ]  TdcMode[0]:0x1
[SPEW ]  TdcMode[1]:0x0
[SPEW ]  TdcMode[2]:0x0
[SPEW ]  TdcMode[3]:0x0
[SPEW ]  TdcTimeWindow[0]:0x6D60
[SPEW ]  TdcTimeWindow[1]:0x0
[SPEW ]  TdcTimeWindow[2]:0x0
[SPEW ]  TdcTimeWindow[3]:0x0

Change-Id: I4b7b9484d47cf9d98548cfc8b53e47be4e21c4d1
Signed-off-by: Sowmya Aralguppe <sowmya.aralguppe@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91455
Reviewed-by: Pranava Y N <pranavayn@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/soc/intel/pantherlake/chipset_wcl.cb | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/src/soc/intel/pantherlake/chipset_wcl.cb b/src/soc/intel/pantherlake/chipset_wcl.cb
index 4d8d296aa5..ed32d4826d 100644
--- a/src/soc/intel/pantherlake/chipset_wcl.cb
+++ b/src/soc/intel/pantherlake/chipset_wcl.cb
@@ -12,6 +12,9 @@ chip soc/intel/pantherlake
 		[VR_DOMAIN_GT] = 36 * 4,
 	}"
 
+	register "tdc_mode[VR_DOMAIN_IA]" = "TDC_IRMS"
+	register "tdc_time_window_ms[VR_DOMAIN_IA]" = "28000"
+
 	# Reduce the size of BasicMemoryTests to speed up the boot time.
 	register "lower_basic_mem_test_size" = "true"
 

From c97e7409816fcffe8b8c279e2b631dd5351fc12e Mon Sep 17 00:00:00 2001
From: Sowmya Aralguppe <sowmya.aralguppe@intel.com>
Date: Fri, 27 Feb 2026 11:56:30 +0530
Subject: [PATCH 3621/3886] mb/google/ocelot: Fix fast_vmode_i_trip indexing in
 devicetree

This aligns with the corrected indexing scheme used in the SoC VR
configuration code.

Ref=:830097_WCL_PDG_SchChk_Rev1p5
BUG=b:None
TEST=Build ocelot and verify that the system boots

Change-Id: I948c9233f4a5518992891b90fb9bb6a3793baa5f
Signed-off-by: Sowmya Aralguppe <sowmya.aralguppe@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91449
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Pranava Y N <pranavayn@google.com>
---
 .../google/ocelot/variants/baseboard/ocelot/devicetree.cb       | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/mainboard/google/ocelot/variants/baseboard/ocelot/devicetree.cb b/src/mainboard/google/ocelot/variants/baseboard/ocelot/devicetree.cb
index b53380c2ee..299c770d5e 100644
--- a/src/mainboard/google/ocelot/variants/baseboard/ocelot/devicetree.cb
+++ b/src/mainboard/google/ocelot/variants/baseboard/ocelot/devicetree.cb
@@ -73,7 +73,7 @@ chip soc/intel/pantherlake
 	# TODO: Update with actual i_trip values.
 	register "enable_fast_vmode[VR_DOMAIN_GT]" = "true"
 	register "cep_enable[VR_DOMAIN_GT]" = "true"
-	register "fast_vmode_i_trip[WCL_CORE]" = "{
+	register "fast_vmode_i_trip[WCL_SKU_1]" = "{
 		[VR_DOMAIN_GT] = 25 * 4,
 	}"
 

From 8aa0ea4062ad9b098cb9751bbb71391e945b3d5c Mon Sep 17 00:00:00 2001
From: Sowmya Aralguppe <sowmya.aralguppe@intel.com>
Date: Mon, 2 Mar 2026 13:33:48 +0530
Subject: [PATCH 3622/3886] soc/intel/pantherlake: Keep default values for
 TdcTimeWindow

This patch prevents coreboot from overwriting FSP defaults with zeros
for unconfigured VR domains.

Ref=:830097_WCL_PDG_SchChk_Rev1p5
BUG=b:None
TEST=Build ocelot and verify that the system boots with correct
VR parameter
[SPEW ]   TdcTimeWindow[0]:0x6D60
[SPEW ]   TdcTimeWindow[1]:0x0
[SPEW ]   TdcTimeWindow[2]:0x0
[SPEW ]   TdcTimeWindow[3]:0x0
[SPEW ]   Override TdcTimeWindow[0] = 28000
[SPEW ]   Override TdcTimeWindow[1] = 1000
[SPEW ]   Override TdcTimeWindow[2] = 0
[SPEW ]   Override TdcTimeWindow[3] = 1000

FSP defaults:
[SPEW ]   Override TdcTimeWindow[0] = 28000
[SPEW ]   Override TdcTimeWindow[1] = 1000
[SPEW ]   Override TdcTimeWindow[2] = 0
[SPEW ]   Override TdcTimeWindow[3] = 1000

Added print in the coreboot code
[DEBUG]  VR[0]: Setting TdcTimeWindow to 28000
[DEBUG]  VR[1]: Setting TdcTimeWindow to 0
[DEBUG]  VR[2]: Setting TdcTimeWindow to 0
[DEBUG]  VR[3]: Setting TdcTimeWindow to 0

Change-Id: Ib2531b908ddf80c40c52f620229852487d3425e9
Signed-off-by: Sowmya Aralguppe <sowmya.aralguppe@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91503
Reviewed-by: Pranava Y N <pranavayn@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
---
 src/soc/intel/pantherlake/romstage/fsp_params.c | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/src/soc/intel/pantherlake/romstage/fsp_params.c b/src/soc/intel/pantherlake/romstage/fsp_params.c
index d143d95688..5e652da187 100644
--- a/src/soc/intel/pantherlake/romstage/fsp_params.c
+++ b/src/soc/intel/pantherlake/romstage/fsp_params.c
@@ -366,8 +366,10 @@ static void fill_fspm_vr_config_params(FSP_M_CONFIG *m_cfg,
 	}
 
 	for (size_t i = 0; i < ARRAY_SIZE(config->tdc_mode); i++) {
-		m_cfg->TdcMode[i] = config->tdc_mode[i];
-		m_cfg->TdcTimeWindow[i] = config->tdc_time_window_ms[i];
+		if (config->tdc_mode[i])
+			m_cfg->TdcMode[i] = config->tdc_mode[i];
+		if (config->tdc_time_window_ms[i])
+			m_cfg->TdcTimeWindow[i] = config->tdc_time_window_ms[i];
 	}
 
 	for (size_t i = 0; i < ARRAY_SIZE(config->ps1_threshold); i++) {

From 61657cff8f4bc494f0e8647c9aede53f7d351000 Mon Sep 17 00:00:00 2001
From: Bora Guvendik <bora.guvendik@intel.com>
Date: Wed, 21 Jan 2026 11:36:12 -0800
Subject: [PATCH 3623/3886] spd/lp5: Add SPD for SK hynix H58G56DK9BX068

Add H58G56DK9BX068 in the memory_parts.json and re-generate the SPD.

BUG=none
TEST= Booted successfully on nvlrvp board using H58G56DK9BX068.
      util/spd_tools/bin/spd_gen spd/lp5/memory_parts.json lp5

Change-Id: I7f8e13c2dac50b108f3ded1528a48b641eafbeec
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90856
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 spd/lp5/memory_parts.json                      | 11 +++++++++++
 spd/lp5/set-0/parts_spd_manifest.generated.txt |  1 +
 spd/lp5/set-0/spd-14.hex                       |  6 +++---
 spd/lp5/set-1/parts_spd_manifest.generated.txt |  1 +
 spd/lp5/set-1/spd-14.hex                       |  4 ++--
 5 files changed, 18 insertions(+), 5 deletions(-)

diff --git a/spd/lp5/memory_parts.json b/spd/lp5/memory_parts.json
index 4c21c7bb28..a38e0ac23f 100644
--- a/spd/lp5/memory_parts.json
+++ b/spd/lp5/memory_parts.json
@@ -456,6 +456,17 @@
             "speedMbps": 8533,
             "lp5x": true
         }
+    },
+    {
+        "name": "H58G56DK9BX068",
+        "attribs": {
+            "densityPerDieGb": 16,
+            "diesPerPackage": 2,
+            "bitWidthPerChannel": 16,
+            "ranksPerChannel": 1,
+            "speedMbps": 9600,
+            "lp5x": true
+        }
     }
     ]
 }
diff --git a/spd/lp5/set-0/parts_spd_manifest.generated.txt b/spd/lp5/set-0/parts_spd_manifest.generated.txt
index 11221ec42c..ac104fc010 100644
--- a/spd/lp5/set-0/parts_spd_manifest.generated.txt
+++ b/spd/lp5/set-0/parts_spd_manifest.generated.txt
@@ -44,3 +44,4 @@ MT62F2G32D4DS-031RF WT:C,spd-6.hex
 RS1G32LO5D2FDB-23BT,spd-11.hex
 BWMYAX32P8A-32G,spd-7.hex
 MT62F2G32D4DS-020 WT:D,spd-10.hex
+H58G56DK9BX068,spd-14.hex
diff --git a/spd/lp5/set-0/spd-14.hex b/spd/lp5/set-0/spd-14.hex
index fb1b5a43c4..f9bb5a2eaf 100644
--- a/spd/lp5/set-0/spd-14.hex
+++ b/spd/lp5/set-0/spd-14.hex
@@ -1,11 +1,11 @@
-23 10 15 0E 16 22 91 08 00 00 00 00 0A 01 00 00
-00 00 08 00 00 00 00 00 AD 00 90 A8 90 C0 08 60
+23 10 15 0E 16 22 95 08 00 00 00 00 02 01 00 00
+00 00 07 00 00 00 00 00 AE 00 90 A8 90 C0 08 60
 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 B6 00 C1 00 00
+00 00 00 00 00 00 00 00 00 00 00 A4 00 D6 00 00
 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
diff --git a/spd/lp5/set-1/parts_spd_manifest.generated.txt b/spd/lp5/set-1/parts_spd_manifest.generated.txt
index 11221ec42c..ac104fc010 100644
--- a/spd/lp5/set-1/parts_spd_manifest.generated.txt
+++ b/spd/lp5/set-1/parts_spd_manifest.generated.txt
@@ -44,3 +44,4 @@ MT62F2G32D4DS-031RF WT:C,spd-6.hex
 RS1G32LO5D2FDB-23BT,spd-11.hex
 BWMYAX32P8A-32G,spd-7.hex
 MT62F2G32D4DS-020 WT:D,spd-10.hex
+H58G56DK9BX068,spd-14.hex
diff --git a/spd/lp5/set-1/spd-14.hex b/spd/lp5/set-1/spd-14.hex
index 37203cc057..8ecc7a190c 100644
--- a/spd/lp5/set-1/spd-14.hex
+++ b/spd/lp5/set-1/spd-14.hex
@@ -1,11 +1,11 @@
-23 11 13 0E 86 21 91 18 00 40 00 00 0A 02 00 00
+23 11 13 0E 86 21 95 18 00 40 00 00 02 02 00 00
 00 00 02 00 00 00 00 00 2C 00 90 A8 90 C0 08 60
 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 8A 00 F0 00 00
+00 00 00 00 00 00 00 00 00 00 00 A4 00 D6 00 00
 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00

From 762b564f3b78f12cae1e9534085cefffecf6d133 Mon Sep 17 00:00:00 2001
From: Subrata Banik <subratabanik@google.com>
Date: Thu, 5 Mar 2026 14:15:26 +0530
Subject: [PATCH 3624/3886] mb/google/bluey: Add timeout for charging rail
 stabilization

In the charger applet, it is possible for the PMIC to take some time
to negotiate and enable the charging current. Previously, the code
proceeded immediately, which could lead to false-positive power-off
triggers if current hadn't started flowing yet.

This change:
1. Implements a 3000ms stopwatch-based timeout.
2. Polls get_battery_icurr_ma() until a non-zero current is detected.
3. Aborts the applet if current fails to stabilize within the window.
4. Adds logging to track the actual duration of the power-up sequence.

BUG=none
BRANCH=none
TEST=Verified that the system enters off-mode charging more reliably
without powering off.

```
[INFO ]  Inside launch_charger_applet. Initiating charging
...
...
[INFO ]  Issuing power-off due to change in charging state.
...
...
```

Change-Id: Ie3501dff06aadf81d527658c4042de7c92de24b5
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91547
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
---
 src/mainboard/google/bluey/charging.c | 16 ++++++++++++++++
 1 file changed, 16 insertions(+)

diff --git a/src/mainboard/google/bluey/charging.c b/src/mainboard/google/bluey/charging.c
index 690f30964f..f81d5b9650 100644
--- a/src/mainboard/google/bluey/charging.c
+++ b/src/mainboard/google/bluey/charging.c
@@ -7,6 +7,7 @@
 #include <reset.h>
 #include <soc/pmic.h>
 #include <soc/qcom_spmi.h>
+#include <timer.h>
 #include <types.h>
 
 #define SMB1_SLAVE_ID 0x07
@@ -41,6 +42,7 @@
 #define PERPH_EN		0x80
 
 #define DELAY_CHARGING_APPLET_MS 2000 /* 2sec */
+#define CHARGING_RAIL_STABILIZATION_DELAY_MS 3000 /* 3sec */
 
 enum charging_status {
 	CHRG_DISABLE,
@@ -86,11 +88,25 @@ void launch_charger_applet(void)
 	if (!CONFIG(EC_GOOGLE_CHROMEEC))
 		return;
 
+	static const long charging_enable_timeout_ms = CHARGING_RAIL_STABILIZATION_DELAY_MS;
+	struct stopwatch sw;
+
 	printk(BIOS_INFO, "Inside %s. Initiating charging\n", __func__);
 
 	/* clear any pending power button press and lid open event */
 	clear_ec_manual_poweron_event();
 
+	stopwatch_init_msecs_expire(&sw, charging_enable_timeout_ms);
+	while (!get_battery_icurr_ma()) {
+		if (stopwatch_expired(&sw)) {
+			printk(BIOS_WARNING, "Charging not enabled %ld ms. Abort.\n",
+					charging_enable_timeout_ms);
+			return;
+		}
+		mdelay(200);
+	}
+	printk(BIOS_INFO, "Charging ready after %lld ms\n", stopwatch_duration_msecs(&sw));
+
 	do {
 		/* Add static delay before reading the charging applet pre-requisites */
 		mdelay(DELAY_CHARGING_APPLET_MS);

From 9541171de49fbd986d0fa24b4113372bd9ff0081 Mon Sep 17 00:00:00 2001
From: Angel Pons <th3fanbus@gmail.com>
Date: Fri, 27 Feb 2026 22:14:08 +0100
Subject: [PATCH 3625/3886] sb/intel/wildcatpoint/acpi: Move platform.asl to
 mainboards

The chipset platform.asl only provided empty _PTS/_WAK stubs and _SWS
methods, which mainboards needing custom sleep/wake behavior (e.g. EC
methods) cannot use. Only 2 of 5 Wildcat Point boards used it. Move the
content to mainboard code and inline the device_nvs and common platform
includes in dsdt.asl to align with other Wildcat Point and Lynx Point
boards. Keeping device NVS in mainboard code also simplifies future
Lynx/Wildcat unification.

Tested with BUILD_TIMELESS=1, Purism Librem 15 v2 remains identical.

Change-Id: I753302a13567efb3b7903364be8cef486d2b76e5
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91469
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
---
 .../google/auron}/acpi/platform.asl           |  3 --
 src/mainboard/google/auron/dsdt.asl           |  4 ++-
 .../purism/librem_bdw/acpi/platform.asl       | 35 +++++++++++++++++++
 src/mainboard/purism/librem_bdw/dsdt.asl      |  4 ++-
 4 files changed, 41 insertions(+), 5 deletions(-)
 rename src/{southbridge/intel/wildcatpoint => mainboard/google/auron}/acpi/platform.asl (81%)
 create mode 100644 src/mainboard/purism/librem_bdw/acpi/platform.asl

diff --git a/src/southbridge/intel/wildcatpoint/acpi/platform.asl b/src/mainboard/google/auron/acpi/platform.asl
similarity index 81%
rename from src/southbridge/intel/wildcatpoint/acpi/platform.asl
rename to src/mainboard/google/auron/acpi/platform.asl
index af60f5cee7..a0a94ef3cc 100644
--- a/src/southbridge/intel/wildcatpoint/acpi/platform.asl
+++ b/src/mainboard/google/auron/acpi/platform.asl
@@ -1,8 +1,5 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
-#include <southbridge/intel/wildcatpoint/acpi/device_nvs.asl>
-#include <southbridge/intel/common/acpi/platform.asl>
-
 /*
  * The _PTS method (Prepare To Sleep) is called before the OS is
  * entering a sleep state. The sleep state number is passed in Arg0
diff --git a/src/mainboard/google/auron/dsdt.asl b/src/mainboard/google/auron/dsdt.asl
index eebeeeacee..97de5cd2e6 100644
--- a/src/mainboard/google/auron/dsdt.asl
+++ b/src/mainboard/google/auron/dsdt.asl
@@ -11,7 +11,9 @@ DefinitionBlock(
 )
 {
 	#include <acpi/dsdt_top.asl>
-	#include <southbridge/intel/wildcatpoint/acpi/platform.asl>
+	#include <southbridge/intel/wildcatpoint/acpi/device_nvs.asl>
+	#include <southbridge/intel/common/acpi/platform.asl>
+	#include "acpi/platform.asl"
 
 	// Thermal handler
 	#include "acpi/thermal.asl"
diff --git a/src/mainboard/purism/librem_bdw/acpi/platform.asl b/src/mainboard/purism/librem_bdw/acpi/platform.asl
new file mode 100644
index 0000000000..a0a94ef3cc
--- /dev/null
+++ b/src/mainboard/purism/librem_bdw/acpi/platform.asl
@@ -0,0 +1,35 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+/*
+ * The _PTS method (Prepare To Sleep) is called before the OS is
+ * entering a sleep state. The sleep state number is passed in Arg0
+ */
+
+Method (_PTS, 1)
+{
+}
+
+/* The _WAK method is called on system wakeup */
+
+Method (_WAK, 1)
+{
+	Return (Package (){ 0, 0 })
+}
+
+Scope (\_SB)
+{
+	Method (_SWS)
+	{
+		/* Index into PM1 for device that caused wake */
+		Return (\PM1I)
+	}
+}
+
+Scope (\_GPE)
+{
+	Method (_SWS)
+	{
+		/* Index into GPE for device that caused wake */
+		Return (\GPEI)
+	}
+}
diff --git a/src/mainboard/purism/librem_bdw/dsdt.asl b/src/mainboard/purism/librem_bdw/dsdt.asl
index 18719a8f1e..23d3df1280 100644
--- a/src/mainboard/purism/librem_bdw/dsdt.asl
+++ b/src/mainboard/purism/librem_bdw/dsdt.asl
@@ -11,7 +11,9 @@ DefinitionBlock(
 )
 {
 	#include <acpi/dsdt_top.asl>
-	#include <southbridge/intel/wildcatpoint/acpi/platform.asl>
+	#include <southbridge/intel/wildcatpoint/acpi/device_nvs.asl>
+	#include <southbridge/intel/common/acpi/platform.asl>
+	#include "acpi/platform.asl"
 	#include <southbridge/intel/wildcatpoint/acpi/globalnvs.asl>
 	#include <cpu/intel/common/acpi/cpu.asl>
 

From d74570b01e413b946b591c7b5673526d4793b4be Mon Sep 17 00:00:00 2001
From: Angel Pons <th3fanbus@gmail.com>
Date: Fri, 27 Feb 2026 20:48:02 +0100
Subject: [PATCH 3626/3886] sb/intel/wildcatpoint/acpi: Use Lynx Point files

Prepare to unify both southbridges by deduplicating the ASL files. This
change is meant to be reproducible, so there is some preprocessor usage
to achieve this. It will be tidied up in follow-up changes.

Tested with BUILD_TIMELESS=1, Purism Librem 15 v2 remains identical.

Change-Id: Ibbb2d76448d87fad7f9d765cd659d60f54c54703
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91470
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
---
 src/mainboard/google/auron/dsdt.asl           |   2 +-
 src/mainboard/google/jecht/dsdt.asl           |   2 +-
 src/mainboard/hp/elitebook_820_g2/dsdt.asl    |   2 +-
 src/mainboard/intel/wtm2/dsdt.asl             |   2 +-
 src/mainboard/purism/librem_bdw/dsdt.asl      |   2 +-
 .../{wildcatpoint => lynxpoint}/acpi/adsp.asl |   0
 src/southbridge/intel/lynxpoint/acpi/pch.asl  |  16 +-
 .../intel/lynxpoint/acpi/serialio.asl         |   3 +
 .../acpi/wpt_lp_pci_irqs.asl}                 |   0
 .../intel/wildcatpoint/acpi/gpio.asl          | 126 ----
 .../intel/wildcatpoint/acpi/lpc.asl           | 180 -----
 .../intel/wildcatpoint/acpi/pch.asl           |  80 ---
 .../intel/wildcatpoint/acpi/serialio.asl      | 626 ------------------
 .../intel/wildcatpoint/acpi/xhci.asl          | 360 ----------
 14 files changed, 23 insertions(+), 1378 deletions(-)
 rename src/southbridge/intel/{wildcatpoint => lynxpoint}/acpi/adsp.asl (100%)
 rename src/southbridge/intel/{wildcatpoint/acpi/pci_irqs.asl => lynxpoint/acpi/wpt_lp_pci_irqs.asl} (100%)
 delete mode 100644 src/southbridge/intel/wildcatpoint/acpi/gpio.asl
 delete mode 100644 src/southbridge/intel/wildcatpoint/acpi/lpc.asl
 delete mode 100644 src/southbridge/intel/wildcatpoint/acpi/pch.asl
 delete mode 100644 src/southbridge/intel/wildcatpoint/acpi/serialio.asl
 delete mode 100644 src/southbridge/intel/wildcatpoint/acpi/xhci.asl

diff --git a/src/mainboard/google/auron/dsdt.asl b/src/mainboard/google/auron/dsdt.asl
index 97de5cd2e6..697a8ee719 100644
--- a/src/mainboard/google/auron/dsdt.asl
+++ b/src/mainboard/google/auron/dsdt.asl
@@ -28,7 +28,7 @@ DefinitionBlock(
 		Device (PCI0)
 		{
 			#include <northbridge/intel/haswell/acpi/hostbridge.asl>
-			#include <southbridge/intel/wildcatpoint/acpi/pch.asl>
+			#include <southbridge/intel/lynxpoint/acpi/pch.asl>
 			#include <drivers/intel/gma/acpi/default_brightness_levels.asl>
 		}
 	}
diff --git a/src/mainboard/google/jecht/dsdt.asl b/src/mainboard/google/jecht/dsdt.asl
index 62c8b58fe6..a635ff4805 100644
--- a/src/mainboard/google/jecht/dsdt.asl
+++ b/src/mainboard/google/jecht/dsdt.asl
@@ -28,7 +28,7 @@ DefinitionBlock(
 		Device (PCI0)
 		{
 			#include <northbridge/intel/haswell/acpi/hostbridge.asl>
-			#include <southbridge/intel/wildcatpoint/acpi/pch.asl>
+			#include <southbridge/intel/lynxpoint/acpi/pch.asl>
 		}
 	}
 
diff --git a/src/mainboard/hp/elitebook_820_g2/dsdt.asl b/src/mainboard/hp/elitebook_820_g2/dsdt.asl
index 95012ce708..71267c539e 100644
--- a/src/mainboard/hp/elitebook_820_g2/dsdt.asl
+++ b/src/mainboard/hp/elitebook_820_g2/dsdt.asl
@@ -25,7 +25,7 @@ DefinitionBlock(
 	Device (\_SB.PCI0)
 	{
 		#include <northbridge/intel/haswell/acpi/hostbridge.asl>
-		#include <southbridge/intel/wildcatpoint/acpi/pch.asl>
+		#include <southbridge/intel/lynxpoint/acpi/pch.asl>
 		#include <drivers/intel/gma/acpi/default_brightness_levels.asl>
 	}
 }
diff --git a/src/mainboard/intel/wtm2/dsdt.asl b/src/mainboard/intel/wtm2/dsdt.asl
index 764d442d5f..2d223e3c13 100644
--- a/src/mainboard/intel/wtm2/dsdt.asl
+++ b/src/mainboard/intel/wtm2/dsdt.asl
@@ -28,7 +28,7 @@ DefinitionBlock(
 		Device (PCI0)
 		{
 			#include <northbridge/intel/haswell/acpi/hostbridge.asl>
-			#include <southbridge/intel/wildcatpoint/acpi/pch.asl>
+			#include <southbridge/intel/lynxpoint/acpi/pch.asl>
 		}
 	}
 
diff --git a/src/mainboard/purism/librem_bdw/dsdt.asl b/src/mainboard/purism/librem_bdw/dsdt.asl
index 23d3df1280..5d203093bd 100644
--- a/src/mainboard/purism/librem_bdw/dsdt.asl
+++ b/src/mainboard/purism/librem_bdw/dsdt.asl
@@ -21,7 +21,7 @@ DefinitionBlock(
 		Device (PCI0)
 		{
 			#include <northbridge/intel/haswell/acpi/hostbridge.asl>
-			#include <southbridge/intel/wildcatpoint/acpi/pch.asl>
+			#include <southbridge/intel/lynxpoint/acpi/pch.asl>
 			#include <drivers/intel/gma/acpi/default_brightness_levels.asl>
 		}
 	}
diff --git a/src/southbridge/intel/wildcatpoint/acpi/adsp.asl b/src/southbridge/intel/lynxpoint/acpi/adsp.asl
similarity index 100%
rename from src/southbridge/intel/wildcatpoint/acpi/adsp.asl
rename to src/southbridge/intel/lynxpoint/acpi/adsp.asl
diff --git a/src/southbridge/intel/lynxpoint/acpi/pch.asl b/src/southbridge/intel/lynxpoint/acpi/pch.asl
index 7ac35d693f..8dd2c118f7 100644
--- a/src/southbridge/intel/lynxpoint/acpi/pch.asl
+++ b/src/southbridge/intel/lynxpoint/acpi/pch.asl
@@ -1,6 +1,12 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
-/* Intel Lynx Point PCH support */
+/* Intel Lynx Point and Wildcat Point PCH support */
+
+/* TODO: Replace static routing info with runtime-generated SSDT */
+#if CONFIG(SOUTHBRIDGE_INTEL_WILDCATPOINT)
+/* PCI IRQ assignment */
+#include "wpt_lp_pci_irqs.asl"
+#endif
 
 #if CONFIG(INTEL_LYNXPOINT_LP)
 #define DEFAULT_PRW_VALUE	0x6d
@@ -43,6 +49,14 @@ Scope (\)
 // High Definition Audio (Azalia) 0:1b.0
 #include "audio.asl"
 
+// TODO: Check if this also applies to Lynx Point-LP
+#if CONFIG(SOUTHBRIDGE_INTEL_WILDCATPOINT)
+#if CONFIG(INTEL_LYNXPOINT_LP)
+// ADSP/SST 0:13.0
+#include "adsp.asl"
+#endif
+#endif
+
 // PCI Express Ports 0:1c.x
 #include <southbridge/intel/common/acpi/pcie.asl>
 
diff --git a/src/southbridge/intel/lynxpoint/acpi/serialio.asl b/src/southbridge/intel/lynxpoint/acpi/serialio.asl
index 95a3466709..c9b215d8b1 100644
--- a/src/southbridge/intel/lynxpoint/acpi/serialio.asl
+++ b/src/southbridge/intel/lynxpoint/acpi/serialio.asl
@@ -5,6 +5,8 @@
 // Serial IO Device BAR0 and BAR1 is 4KB
 #define SIO_BAR_LEN 0x1000
 
+// TODO: Replace this with some HAVE_DEVICE_NVS Kconfig
+#if !CONFIG(SOUTHBRIDGE_INTEL_WILDCATPOINT)
 // This is defined in SSDT2 which is generated at boot based
 // on whether or not the device is enabled in ACPI mode.
 External (\S0EN)
@@ -15,6 +17,7 @@ External (\S4EN)
 External (\S5EN)
 External (\S6EN)
 External (\S7EN)
+#endif
 
 // Put SerialIO device in D0 state
 // Arg0 - Ref to offset 0x84 of device's PCI config space
diff --git a/src/southbridge/intel/wildcatpoint/acpi/pci_irqs.asl b/src/southbridge/intel/lynxpoint/acpi/wpt_lp_pci_irqs.asl
similarity index 100%
rename from src/southbridge/intel/wildcatpoint/acpi/pci_irqs.asl
rename to src/southbridge/intel/lynxpoint/acpi/wpt_lp_pci_irqs.asl
diff --git a/src/southbridge/intel/wildcatpoint/acpi/gpio.asl b/src/southbridge/intel/wildcatpoint/acpi/gpio.asl
deleted file mode 100644
index 48167bfae5..0000000000
--- a/src/southbridge/intel/wildcatpoint/acpi/gpio.asl
+++ /dev/null
@@ -1,126 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-Device (GPIO)
-{
-	// GPIO Controller
-	Method (_HID)
-	{
-		If (\ISWP ()) {
-			// WildcatPoint
-			Return ("INT3437")
-		}
-
-		// LynxPoint-LP
-		Return ("INT33C7")
-	}
-	Name (_CID, "INT33C7")
-	Name (_UID, 1)
-
-	Name (RBUF, ResourceTemplate ()
-	{
-		DWordIo (ResourceProducer,
-			MinFixed,    // IsMinFixed
-			MaxFixed,    // IsMaxFixed
-			PosDecode,   // Decode
-			EntireRange, // ISARanges
-			0x00000000,  // AddressGranularity
-			0x00000000,  // AddressMinimum
-			0x00000000,  // AddressMaximum
-			0x00000000,  // AddressTranslation
-			0x00000000,  // RangeLength
-			,            // ResourceSourceIndex
-			,            // ResourceSource
-			BAR0)
-		// Disabled due to IRQ storm: http://crosbug.com/p/29548
-		//Interrupt (ResourceConsumer,
-		//	Level, ActiveHigh, Shared, , , ) {14}
-	})
-
-	Method (_CRS, 0, NotSerialized)
-	{
-		CreateDwordField (^RBUF, ^BAR0._MIN, BMIN)
-		CreateDwordField (^RBUF, ^BAR0._MAX, BMAX)
-		CreateDwordField (^RBUF, ^BAR0._LEN, BLEN)
-
-		BLEN = GPIO_BASE_SIZE
-		BMIN = GPIO_BASE_ADDRESS
-		BMAX = GPIO_BASE_ADDRESS + GPIO_BASE_SIZE - 1
-
-		Return (RBUF)
-	}
-
-	Method (_STA, 0, NotSerialized)
-	{
-		Return (0xF)
-	}
-
-	// GWAK: Setup GPIO as ACPI GPE for Wake
-	// Arg0: GPIO Number
-	Method (GWAK, 1, Serialized)
-	{
-		// Local0 = GPIO Base Address
-		Local0 = GPBS & ~1
-
-		// Local1 = BANK, Local2 = OFFSET
-		Local2 = Arg0 % 32
-		Local1 = Arg0 / 32
-
-		//
-		// Set OWNER to ACPI
-		//
-
-		// Local3 = GPIOBASE + GPIO_OWN(BANK)
-		Local3 = Local0 + (Local1 * 4)
-
-		// GPIO_OWN(BANK)
-		OperationRegion (IOWN, SystemIO, Local3, 4)
-		Field (IOWN, AnyAcc, NoLock, Preserve) {
-			GOWN, 32,
-		}
-
-		// GPIO_OWN[GPIO] = 0 (ACPI)
-		GOWN = GOWN & ~(1 << Local2)
-
-		//
-		// Set ROUTE to SCI
-		//
-
-		// Local3 = GPIOBASE + GPIO_ROUTE(BANK)
-		Local3 = Local0 + 0x30  + (Local1 * 4)
-
-		// GPIO_ROUTE(BANK)
-		OperationRegion (IROU, SystemIO, Local3, 4)
-		Field (IROU, AnyAcc, NoLock, Preserve) {
-			GROU, 32,
-		}
-
-		// GPIO_ROUTE[GPIO] = 0 (SCI)
-		GROU = GROU & ~(1 << Local2)
-
-		//
-		// Set GPnCONFIG to GPIO|INPUT|INVERT
-		//
-
-		// Local3 = GPIOBASE + GPnCONFIG0(GPIO)
-		Local3 = Local0 + 0x100 + (Arg0 * 8)
-
-		// GPnCONFIG(GPIO)
-		OperationRegion (GPNC, SystemIO, Local3, 8)
-		Field (GPNC, AnyAcc, NoLock, Preserve) {
-			GMOD, 1,  // MODE:   0=NATIVE 1=GPIO
-			, 1,
-			GIOS, 1,  // IO_SEL: 0=OUTPUT 1=INPUT
-			GINV, 1,  // INVERT: 0=NORMAL 1=INVERT
-			GLES, 1,  // LxEB:   0=EDGE 1=LEVEL
-			, 24,
-			ILVL, 1,  // INPUT:  0=LOW 1=HIGH
-			OLVL, 1,  // OUTPUT: 0=LOW 1=HIGH
-			GPWP, 2,  // PULLUP: 00=NONE 01=DOWN 10=UP 11=INVALID
-			ISEN, 1,  // SENSE:  0=ENABLE 1=DISABLE
-		}
-
-		GMOD = 1 // GPIO
-		GIOS = 1 // INPUT
-		GINV = 1 // INVERT
-	}
-}
diff --git a/src/southbridge/intel/wildcatpoint/acpi/lpc.asl b/src/southbridge/intel/wildcatpoint/acpi/lpc.asl
deleted file mode 100644
index b6b77c8ed2..0000000000
--- a/src/southbridge/intel/wildcatpoint/acpi/lpc.asl
+++ /dev/null
@@ -1,180 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <arch/hpet.h>
-
-// Intel LPC Bus Device  - 0:1f.0
-
-Device (LPCB)
-{
-	Name (_ADR, 0x001f0000)
-
-	OperationRegion (LPC0, PCI_Config, 0, 0x100)
-	Field (LPC0, AnyAcc, NoLock, Preserve)
-	{
-		Offset (0x02),
-		PDID,	16,	// Device ID
-		Offset (0x40),
-		PMBS,	16,	// PMBASE
-		Offset (0x48),
-		GPBS,	16,	// GPIOBASE
-		Offset (0x60),	// Interrupt Routing Registers
-		PRTA,	8,
-		PRTB,	8,
-		PRTC,	8,
-		PRTD,	8,
-		Offset (0x68),
-		PRTE,	8,
-		PRTF,	8,
-		PRTG,	8,
-		PRTH,	8,
-
-		Offset (0x80),	// IO Decode Ranges
-		IOD0,	8,
-		IOD1,	8,
-	}
-
-	#include <southbridge/intel/common/acpi/irqlinks.asl>
-
-	#include "acpi/ec.asl"
-
-	Device (DMAC)	// DMA Controller
-	{
-		Name (_HID, EISAID ("PNP0200"))
-		Name (_CRS, ResourceTemplate ()
-		{
-			IO (Decode16, 0x00, 0x00, 0x01, 0x20)
-			IO (Decode16, 0x81, 0x81, 0x01, 0x11)
-			IO (Decode16, 0x93, 0x93, 0x01, 0x0d)
-			IO (Decode16, 0xc0, 0xc0, 0x01, 0x20)
-			DMA (Compatibility, NotBusMaster, Transfer8_16) { 4 }
-		})
-	}
-
-	Device (FWH)	// Firmware Hub
-	{
-		Name (_HID, EISAID ("INT0800"))
-		Name (_CRS, ResourceTemplate ()
-		{
-			Memory32Fixed (ReadOnly, 0xff000000, 0x01000000)
-		})
-	}
-
-	Device (HPET)
-	{
-		Name (_HID, EISAID ("PNP0103"))
-		Name (_CID, 0x010CD041)
-
-		Name (BUF0, ResourceTemplate ()
-		{
-			Memory32Fixed (ReadOnly, HPET_BASE_ADDRESS, 0x400, FED0)
-		})
-
-		Method (_STA, 0)	// Device Status
-		{
-			Return (\HPTS(HPTE))
-		}
-
-		Method (_CRS, 0, Serialized) // Current resources
-		{
-			If (HPTE) {
-				CreateDWordField (BUF0, \_SB.PCI0.LPCB.HPET.FED0._BAS, HPT0)
-				If (HPAS == 1) {
-					HPT0 = HPET_BASE_ADDRESS + 0x1000
-				}
-
-				If (HPAS == 2) {
-					HPT0 = HPET_BASE_ADDRESS + 0x2000
-				}
-
-				If (HPAS == 3) {
-					HPT0 = HPET_BASE_ADDRESS + 0x3000
-				}
-			}
-
-			Return (BUF0)
-		}
-	}
-
-	Device (PIC)	// 8259 Interrupt Controller
-	{
-		Name (_HID,EISAID ("PNP0000"))
-		Name (_CRS, ResourceTemplate ()
-		{
-			IO (Decode16, 0x20, 0x20, 0x01, 0x02)
-			IO (Decode16, 0x24, 0x24, 0x01, 0x02)
-			IO (Decode16, 0x28, 0x28, 0x01, 0x02)
-			IO (Decode16, 0x2c, 0x2c, 0x01, 0x02)
-			IO (Decode16, 0x30, 0x30, 0x01, 0x02)
-			IO (Decode16, 0x34, 0x34, 0x01, 0x02)
-			IO (Decode16, 0x38, 0x38, 0x01, 0x02)
-			IO (Decode16, 0x3c, 0x3c, 0x01, 0x02)
-			IO (Decode16, 0xa0, 0xa0, 0x01, 0x02)
-			IO (Decode16, 0xa4, 0xa4, 0x01, 0x02)
-			IO (Decode16, 0xa8, 0xa8, 0x01, 0x02)
-			IO (Decode16, 0xac, 0xac, 0x01, 0x02)
-			IO (Decode16, 0xb0, 0xb0, 0x01, 0x02)
-			IO (Decode16, 0xb4, 0xb4, 0x01, 0x02)
-			IO (Decode16, 0xb8, 0xb8, 0x01, 0x02)
-			IO (Decode16, 0xbc, 0xbc, 0x01, 0x02)
-			IO (Decode16, 0x4d0, 0x4d0, 0x01, 0x02)
-			IRQNoFlags () { 2 }
-		})
-	}
-
-	Device (MATH)	// FPU
-	{
-		Name (_HID, EISAID ("PNP0C04"))
-		Name (_CRS, ResourceTemplate ()
-		{
-			IO (Decode16, 0xf0, 0xf0, 0x01, 0x01)
-			IRQNoFlags () { 13 }
-		})
-	}
-
-	Device (LDRC)	// LPC device: Resource consumption
-	{
-		Name (_HID, EISAID ("PNP0C02"))
-		Name (_UID, 2)
-
-		Name (RBUF, ResourceTemplate ()
-		{
-			IO (Decode16, 0x2e, 0x2e, 0x1, 0x02) // First SuperIO
-			IO (Decode16, 0x4e, 0x4e, 0x1, 0x02) // Second SuperIO
-			IO (Decode16, 0x61, 0x61, 0x1, 0x01) // NMI Status
-			IO (Decode16, 0x63, 0x63, 0x1, 0x01) // CPU Reserved
-			IO (Decode16, 0x65, 0x65, 0x1, 0x01) // CPU Reserved
-			IO (Decode16, 0x67, 0x67, 0x1, 0x01) // CPU Reserved
-			IO (Decode16, 0x80, 0x80, 0x1, 0x01) // Port 80 Post
-			IO (Decode16, 0x92, 0x92, 0x1, 0x01) // CPU Reserved
-			IO (Decode16, 0xb2, 0xb2, 0x1, 0x02) // SWSMI
-			IO (Decode16, ACPI_BASE_ADDRESS, ACPI_BASE_ADDRESS, 0x1, 0xff)
-		})
-
-		Method (_CRS, 0, NotSerialized)
-		{
-			Return (RBUF)
-		}
-	}
-
-	Device (RTC)	// Real Time Clock
-	{
-		Name (_HID, EISAID ("PNP0B00"))
-		Name (_CRS, ResourceTemplate ()
-		{
-			IO (Decode16, 0x70, 0x70, 1, 8)
-		})
-	}
-
-	Device (TIMR)	// Intel 8254 timer
-	{
-		Name (_HID, EISAID ("PNP0100"))
-		Name (_CRS, ResourceTemplate () {
-			IO (Decode16, 0x40, 0x40, 0x01, 0x04)
-			IO (Decode16, 0x50, 0x50, 0x10, 0x04)
-			IRQNoFlags () {0}
-		})
-	}
-
-	#include "gpio.asl"
-	#include "acpi/superio.asl"
-}
diff --git a/src/southbridge/intel/wildcatpoint/acpi/pch.asl b/src/southbridge/intel/wildcatpoint/acpi/pch.asl
deleted file mode 100644
index 5e1f7206d6..0000000000
--- a/src/southbridge/intel/wildcatpoint/acpi/pch.asl
+++ /dev/null
@@ -1,80 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <soc/iomap.h>
-
-/* PCI IRQ assignment */
-#include "pci_irqs.asl"
-
-#define DEFAULT_PRW_VALUE	0x6d
-
-Scope (\)
-{
-	// Root Complex Register Block
-	OperationRegion (RCRB, SystemMemory, CONFIG_FIXED_RCBA_MMIO_BASE, CONFIG_RCBA_LENGTH)
-	Field (RCRB, DWordAcc, Lock, Preserve)
-	{
-		Offset (0x3404), // High Performance Timer Configuration
-		HPAS, 2,	// Address Select
-		, 5,
-		HPTE, 1,	// Address Enable
-	}
-
-	/*
-	 * Check PCH type
-	 * Return 1 if PCH is WildcatPoint
-	 * Return 0 if PCH is LynxPoint
-	 */
-	Method (ISWP)
-	{
-		Local0 = \_SB.PCI0.LPCB.PDID & 0xfff0
-		If (Local0 == 0x9cc0) {
-			Return (1)
-		} Else {
-			Return (0)
-		}
-	}
-}
-
-// High Definition Audio (Azalia) 0:1b.0
-#include <southbridge/intel/lynxpoint/acpi/audio.asl>
-
-// ADSP/SST 0:13.0
-#include "adsp.asl"
-
-// PCI Express Ports 0:1c.x
-#include <southbridge/intel/common/acpi/pcie.asl>
-
-// USB EHCI 0:1d.0
-#include <southbridge/intel/lynxpoint/acpi/ehci.asl>
-
-// USB XHCI 0:14.0
-#include "xhci.asl"
-
-// LPC Bridge 0:1f.0
-#include "lpc.asl"
-
-// SATA 0:1f.2
-#include <southbridge/intel/lynxpoint/acpi/sata.asl>
-
-// SMBus 0:1f.3
-#include <southbridge/intel/common/acpi/smbus.asl>
-
-// Serial IO
-#include "serialio.asl"
-
-Method (_OSC, 4)
-{
-	/* Check for proper GUID */
-	If (Arg0 == ToUUID ("33DB4D5B-1FF7-401C-9657-7441C03DD766"))
-	{
-		/* Let OS control everything */
-		Return (Arg3)
-	}
-	Else
-	{
-		/* Unrecognized UUID */
-		CreateDWordField (Arg3, 0, CDW1)
-		CDW1 |= 4
-		Return (Arg3)
-	}
-}
diff --git a/src/southbridge/intel/wildcatpoint/acpi/serialio.asl b/src/southbridge/intel/wildcatpoint/acpi/serialio.asl
deleted file mode 100644
index d28fb70930..0000000000
--- a/src/southbridge/intel/wildcatpoint/acpi/serialio.asl
+++ /dev/null
@@ -1,626 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-// Intel Serial IO Devices in ACPI Mode
-
-// Serial IO Device BAR0 and BAR1 is 4KB
-#define SIO_BAR_LEN 0x1000
-
-// Put SerialIO device in D0 state
-// Arg0 - Ref to offset 0x84 of device's PCI config space
-Method (LPD0, 1, Serialized)
-{
-	Arg0 = DeRefOf (Arg0) & 0xFFFFFFFC
-	Local0 = DeRefOf (Arg0) // Read back after writing
-
-	// Use Local0 to avoid iasl warning: Method Local is set but never used
-	Local0 &= Ones
-}
-
-// Put SerialIO device in D3 state
-// Arg0 - Ref to offset 0x84 of device's PCI config space
-Method (LPD3, 1, Serialized)
-{
-	Arg0 = DeRefOf (Arg0) | 0x3
-	Local0 = DeRefOf (Arg0) // Read back after writing
-
-	// Use Local0 to avoid iasl warning: Method Local is set but never used
-	Local0 &= Ones
-}
-
-// Serial IO Resource Consumption for BAR1
-Device (SIOR)
-{
-	Name (_HID, EISAID ("PNP0C02"))
-	Name (_UID, 4)
-
-	Name (RBUF, ResourceTemplate ()
-	{
-		// Serial IO BAR1 (PCI config space) resources
-		Memory32Fixed (ReadWrite, 0x00000000, 0x00000000, B1D0) // SDMA
-		Memory32Fixed (ReadWrite, 0x00000000, 0x00000000, B1D1) // I2C0
-		Memory32Fixed (ReadWrite, 0x00000000, 0x00000000, B1D2) // I2C1
-		Memory32Fixed (ReadWrite, 0x00000000, 0x00000000, B1D3) // SPI0
-		Memory32Fixed (ReadWrite, 0x00000000, 0x00000000, B1D4) // SPI1
-		Memory32Fixed (ReadWrite, 0x00000000, 0x00000000, B1D5) // UART0
-		Memory32Fixed (ReadWrite, 0x00000000, 0x00000000, B1D6) // UART1
-		Memory32Fixed (ReadWrite, 0x00000000, 0x00000000, B1D7) // SDIO
-	})
-
-	// Update BAR1 address and length if set in NVS
-	Method (_CRS, 0, NotSerialized)
-	{
-		// SDMA
-		If (\S0B1 != 0) {
-			CreateDwordField (^RBUF, ^B1D0._BAS, B0AD)
-			CreateDwordField (^RBUF, ^B1D0._LEN, B0LN)
-			B0AD = \S0B1
-			B0LN = SIO_BAR_LEN
-		}
-
-		// I2C0
-		If (\S1B1 != 0) {
-			CreateDwordField (^RBUF, ^B1D1._BAS, B1AD)
-			CreateDwordField (^RBUF, ^B1D1._LEN, B1LN)
-			B1AD = \S1B1
-			B1LN = SIO_BAR_LEN
-		}
-
-		// I2C1
-		If (\S2B1 != 0) {
-			CreateDwordField (^RBUF, ^B1D2._BAS, B2AD)
-			CreateDwordField (^RBUF, ^B1D2._LEN, B2LN)
-			B2AD = \S2B1
-			B2LN = SIO_BAR_LEN
-		}
-
-		// SPI0
-		If (\S3B1 != 0) {
-			CreateDwordField (^RBUF, ^B1D3._BAS, B3AD)
-			CreateDwordField (^RBUF, ^B1D3._LEN, B3LN)
-			B3AD = \S3B1
-			B3LN = SIO_BAR_LEN
-		}
-
-		// SPI1
-		If (\S4B1 != 0) {
-			CreateDwordField (^RBUF, ^B1D4._BAS, B4AD)
-			CreateDwordField (^RBUF, ^B1D4._LEN, B4LN)
-			B4AD = \S4B1
-			B4LN = SIO_BAR_LEN
-		}
-
-		// UART0
-		If (\S5B1 != 0) {
-			CreateDwordField (^RBUF, ^B1D5._BAS, B5AD)
-			CreateDwordField (^RBUF, ^B1D5._LEN, B5LN)
-			B5AD = \S5B1
-			B5LN = SIO_BAR_LEN
-		}
-
-		// UART1
-		If (\S6B1 != 0) {
-			CreateDwordField (^RBUF, ^B1D6._BAS, B6AD)
-			CreateDwordField (^RBUF, ^B1D6._LEN, B6LN)
-			B6AD = \S6B1
-			B6LN = SIO_BAR_LEN
-		}
-
-		// SDIO
-		If (\S7B1 != 0) {
-			CreateDwordField (^RBUF, ^B1D7._BAS, B7AD)
-			CreateDwordField (^RBUF, ^B1D7._LEN, B7LN)
-			B7AD = \S7B1
-			B7LN = SIO_BAR_LEN
-		}
-
-		Return (RBUF)
-	}
-}
-
-Device (SDMA)
-{
-	// Serial IO DMA Controller
-	Name (_HID, "INTL9C60")
-	Name (_UID, 1)
-
-	// BAR0 is assigned during PCI enumeration and saved into NVS
-	Name (RBUF, ResourceTemplate ()
-	{
-		Memory32Fixed (ReadWrite, 0x00000000, 0x00000000, BAR0)
-		Interrupt (ResourceConsumer, Level, ActiveLow, Shared, , , ) {7}
-	})
-
-	Method (_CRS, 0, NotSerialized)
-	{
-		// Update BAR0 address and length if set in NVS
-		If (\S0B0 != 0) {
-			CreateDwordField (^RBUF, ^BAR0._BAS, B0AD)
-			CreateDwordField (^RBUF, ^BAR0._LEN, B0LN)
-			B0AD = \S0B0
-			B0LN = SIO_BAR_LEN
-		}
-
-		Return (RBUF)
-	}
-
-	Method (_STA, 0, NotSerialized)
-	{
-		If (\S0EN == 0) {
-			Return (0x0)
-		} Else {
-			Return (0xF)
-		}
-	}
-}
-
-Device (I2C0)
-{
-	// Serial IO I2C0 Controller
-	Method (_HID)
-	{
-		If (\ISWP ()) {
-			// WildcatPoint
-			Return ("INT3432")
-		}
-
-		// LynxPoint-LP
-		Return ("INT33C2")
-	}
-	Name (_CID, "INT33C2")
-	Name (_UID, 1)
-
-	Name (SSCN, Package () { 432, 507, 30 })
-	Name (FMCN, Package () { 72, 160, 30 })
-
-	// BAR0 is assigned during PCI enumeration and saved into NVS
-	Name (RBUF, ResourceTemplate ()
-	{
-		Memory32Fixed (ReadWrite, 0x00000000, 0x00000000, BAR0)
-		Interrupt (ResourceConsumer, Level, ActiveLow, Shared, , , ) {7}
-	})
-
-	// DMA channels are only used if Serial IO DMA controller is enabled
-	Name (DBUF, ResourceTemplate ()
-	{
-		FixedDMA (0x18, 4, Width32Bit, DMA1) // Tx
-		FixedDMA (0x19, 5, Width32Bit, DMA2) // Rx
-	})
-
-	Method (_CRS, 0, NotSerialized)
-	{
-		// Update BAR0 address and length if set in NVS
-		If (\S1B0 != 0) {
-			CreateDwordField (^RBUF, ^BAR0._BAS, B0AD)
-			CreateDwordField (^RBUF, ^BAR0._LEN, B0LN)
-			B0AD = \S1B0
-			B0LN = SIO_BAR_LEN
-		}
-
-		// Check if Serial IO DMA Controller is enabled
-		If (\_SB.PCI0.SDMA._STA != 0) {
-			Return (ConcatenateResTemplate (RBUF, DBUF))
-		} Else {
-			Return (RBUF)
-		}
-	}
-
-	Method (_STA, 0, NotSerialized)
-	{
-		If (\S1EN == 0) {
-			Return (0x0)
-		} Else {
-			Return (0xF)
-		}
-	}
-
-	OperationRegion (SPRT, SystemMemory, \S1B1 + 0x84, 4)
-	Field (SPRT, DWordAcc, NoLock, Preserve)
-	{
-		SPCS, 32
-	}
-
-	Method (_PS0, 0, Serialized)
-	{
-		^^LPD0 (RefOf (SPCS))
-	}
-
-	Method (_PS3, 0, Serialized)
-	{
-		^^LPD3 (RefOf (SPCS))
-	}
-}
-
-Device (I2C1)
-{
-	// Serial IO I2C1 Controller
-	Method (_HID)
-	{
-		If (\ISWP ()) {
-			// WildcatPoint
-			Return ("INT3433")
-		}
-
-		// LynxPoint-LP
-		Return ("INT33C3")
-	}
-	Name (_CID, "INT33C3")
-	Name (_UID, 1)
-
-	Name (SSCN, Package () { 432, 507, 30 })
-	Name (FMCN, Package () { 72, 160, 30 })
-
-	// BAR0 is assigned during PCI enumeration and saved into NVS
-	Name (RBUF, ResourceTemplate ()
-	{
-		Memory32Fixed (ReadWrite, 0x00000000, 0x00000000, BAR0)
-		Interrupt (ResourceConsumer, Level, ActiveLow, Shared, , , ) {7}
-	})
-
-	// DMA channels are only used if Serial IO DMA controller is enabled
-	Name (DBUF, ResourceTemplate ()
-	{
-		FixedDMA (0x1A, 6, Width32Bit, DMA1) // Tx
-		FixedDMA (0x1B, 7, Width32Bit, DMA2) // Rx
-	})
-
-	Method (_CRS, 0, NotSerialized)
-	{
-		// Update BAR0 address and length if set in NVS
-		If (\S2B0 != 0) {
-			CreateDwordField (^RBUF, ^BAR0._BAS, B0AD)
-			CreateDwordField (^RBUF, ^BAR0._LEN, B0LN)
-			B0AD = \S2B0
-			B0LN = SIO_BAR_LEN
-		}
-
-		// Check if Serial IO DMA Controller is enabled
-		If (\_SB.PCI0.SDMA._STA != 0) {
-			Return (ConcatenateResTemplate (RBUF, DBUF))
-		} Else {
-			Return (RBUF)
-		}
-	}
-
-	Method (_STA, 0, NotSerialized)
-	{
-		If (\S2EN == 0) {
-			Return (0x0)
-		} Else {
-			Return (0xF)
-		}
-	}
-
-	OperationRegion (SPRT, SystemMemory, \S2B1 + 0x84, 4)
-	Field (SPRT, DWordAcc, NoLock, Preserve)
-	{
-		SPCS, 32
-	}
-
-	Method (_PS0, 0, Serialized)
-	{
-		^^LPD0 (RefOf (SPCS))
-	}
-
-	Method (_PS3, 0, Serialized)
-	{
-		^^LPD3 (RefOf (SPCS))
-	}
-}
-
-Device (SPI0)
-{
-	// Serial IO SPI0 Controller
-	Method (_HID)
-	{
-		If (\ISWP ()) {
-			// WildcatPoint
-			Return ("INT3430")
-		}
-
-		// LynxPoint-LP
-		Return ("INT33C0")
-	}
-	Name (_CID, "INT33C0")
-	Name (_UID, 1)
-
-	// BAR0 is assigned during PCI enumeration and saved into NVS
-	Name (RBUF, ResourceTemplate ()
-	{
-		Memory32Fixed (ReadWrite, 0x00000000, 0x00000000, BAR0)
-		Interrupt (ResourceConsumer, Level, ActiveLow, Shared, , , ) {7}
-	})
-
-	Method (_CRS, 0, NotSerialized)
-	{
-		// Update BAR0 address and length if set in NVS
-		If (\S3B0 != 0) {
-			CreateDwordField (^RBUF, ^BAR0._BAS, B0AD)
-			CreateDwordField (^RBUF, ^BAR0._LEN, B0LN)
-			B0AD = \S3B0
-			B0LN = SIO_BAR_LEN
-		}
-
-		Return (RBUF)
-	}
-
-	Method (_STA, 0, NotSerialized)
-	{
-		If (\S3EN == 0) {
-			Return (0x0)
-		} Else {
-			Return (0xF)
-		}
-	}
-
-	OperationRegion (SPRT, SystemMemory, \S3B1 + 0x84, 4)
-	Field (SPRT, DWordAcc, NoLock, Preserve)
-	{
-		SPCS, 32
-	}
-
-	Method (_PS0, 0, Serialized)
-	{
-		^^LPD0 (RefOf (SPCS))
-	}
-
-	Method (_PS3, 0, Serialized)
-	{
-		^^LPD3 (RefOf (SPCS))
-	}
-}
-
-Device (SPI1)
-{
-	// Serial IO SPI1 Controller
-	Method (_HID)
-	{
-		If (\ISWP ()) {
-			// WildcatPoint
-			Return ("INT3431")
-		}
-
-		// LynxPoint-LP
-		Return ("INT33C1")
-	}
-	Name (_CID, "INT33C1")
-	Name (_UID, 1)
-
-	// BAR0 is assigned during PCI enumeration and saved into NVS
-	Name (RBUF, ResourceTemplate ()
-	{
-		Memory32Fixed (ReadWrite, 0x00000000, 0x00000000, BAR0)
-		Interrupt (ResourceConsumer, Level, ActiveLow, Shared, , , ) {7}
-	})
-
-	// DMA channels are only used if Serial IO DMA controller is enabled
-	Name (DBUF, ResourceTemplate ()
-	{
-		FixedDMA (0x10, 0, Width32Bit, DMA1) // Tx
-		FixedDMA (0x11, 1, Width32Bit, DMA2) // Rx
-	})
-
-	Method (_CRS, 0, NotSerialized)
-	{
-		// Update BAR0 address and length if set in NVS
-		If (\S4B0 != 0) {
-			CreateDwordField (^RBUF, ^BAR0._BAS, B0AD)
-			CreateDwordField (^RBUF, ^BAR0._LEN, B0LN)
-			B0AD = \S4B0
-			B0LN = SIO_BAR_LEN
-		}
-
-		// Check if Serial IO DMA Controller is enabled
-		If (\_SB.PCI0.SDMA._STA != 0) {
-			Return (ConcatenateResTemplate (RBUF, DBUF))
-		} Else {
-			Return (RBUF)
-		}
-	}
-
-	Method (_STA, 0, NotSerialized)
-	{
-		If (\S4EN == 0) {
-			Return (0x0)
-		} Else {
-			Return (0xF)
-		}
-	}
-
-	OperationRegion (SPRT, SystemMemory, \S4B1 + 0x84, 4)
-	Field (SPRT, DWordAcc, NoLock, Preserve)
-	{
-		SPCS, 32
-	}
-
-	Method (_PS0, 0, Serialized)
-	{
-		^^LPD0 (RefOf (SPCS))
-	}
-
-	Method (_PS3, 0, Serialized)
-	{
-		^^LPD3 (RefOf (SPCS))
-	}
-}
-
-Device (UAR0)
-{
-	// Serial IO UART0 Controller
-	Method (_HID)
-	{
-		If (\ISWP ()) {
-			// WildcatPoint
-			Return ("INT3434")
-		}
-
-		// LynxPoint-LP
-		Return ("INT33C4")
-	}
-	Name (_CID, "INT33C4")
-	Name (_UID, 1)
-
-	// BAR0 is assigned during PCI enumeration and saved into NVS
-	Name (RBUF, ResourceTemplate ()
-	{
-		Memory32Fixed (ReadWrite, 0x00000000, 0x00000000, BAR0)
-		Interrupt (ResourceConsumer, Level, ActiveLow, Shared, , , ) {13}
-	})
-
-	// DMA channels are only used if Serial IO DMA controller is enabled
-	Name (DBUF, ResourceTemplate ()
-	{
-		FixedDMA (0x16, 2, Width32Bit, DMA1) // Tx
-		FixedDMA (0x17, 3, Width32Bit, DMA2) // Rx
-	})
-
-	Method (_CRS, 0, NotSerialized)
-	{
-		// Update BAR0 address and length if set in NVS
-		If (\S5B0 != 0) {
-			CreateDwordField (^RBUF, ^BAR0._BAS, B0AD)
-			CreateDwordField (^RBUF, ^BAR0._LEN, B0LN)
-			B0AD = \S5B0
-			B0LN = SIO_BAR_LEN
-		}
-
-		// Check if Serial IO DMA Controller is enabled
-		If (\_SB.PCI0.SDMA._STA != 0) {
-			Return (ConcatenateResTemplate (RBUF, DBUF))
-		} Else {
-			Return (RBUF)
-		}
-	}
-
-	Method (_STA, 0, NotSerialized)
-	{
-		If (\S5EN == 0) {
-			Return (0x0)
-		} Else {
-			Return (0xF)
-		}
-	}
-
-	OperationRegion (SPRT, SystemMemory, \S5B1 + 0x84, 4)
-	Field (SPRT, DWordAcc, NoLock, Preserve)
-	{
-		SPCS, 32
-	}
-
-	Method (_PS0, 0, Serialized)
-	{
-		^^LPD0 (RefOf (SPCS))
-	}
-
-	Method (_PS3, 0, Serialized)
-	{
-		^^LPD3 (RefOf (SPCS))
-	}
-}
-
-Device (UAR1)
-{
-	// Serial IO UART1 Controller
-	Method (_HID)
-	{
-		If (\ISWP ()) {
-			// WildcatPoint
-			Return ("INT3435")
-		}
-
-		// LynxPoint-LP
-		Return ("INT33C5")
-	}
-	Name (_CID, "INT33C5")
-	Name (_UID, 1)
-
-	// BAR0 is assigned during PCI enumeration and saved into NVS
-	Name (RBUF, ResourceTemplate ()
-	{
-		Memory32Fixed (ReadWrite, 0x00000000, 0x00000000, BAR0)
-		Interrupt (ResourceConsumer, Level, ActiveLow, Shared, , , ) {13}
-	})
-
-	Method (_CRS, 0, NotSerialized)
-	{
-		// Update BAR0 address and length if set in NVS
-		If (\S6B0 != 0) {
-			CreateDwordField (^RBUF, ^BAR0._BAS, B0AD)
-			CreateDwordField (^RBUF, ^BAR0._LEN, B0LN)
-			B0AD = \S6B0
-			B0LN = SIO_BAR_LEN
-		}
-
-		Return (RBUF)
-	}
-
-	Method (_STA, 0, NotSerialized)
-	{
-		If (\S6EN == 0) {
-			Return (0x0)
-		} Else {
-			Return (0xF)
-		}
-	}
-
-	OperationRegion (SPRT, SystemMemory, \S6B1 + 0x84, 4)
-	Field (SPRT, DWordAcc, NoLock, Preserve)
-	{
-		SPCS, 32
-	}
-
-	Method (_PS0, 0, Serialized)
-	{
-		^^LPD0 (RefOf (SPCS))
-	}
-
-	Method (_PS3, 0, Serialized)
-	{
-		^^LPD3 (RefOf (SPCS))
-	}
-}
-
-Device (SDIO)
-{
-	// Serial IO SDIO Controller
-	Method (_HID)
-	{
-		If (\ISWP ()) {
-			// WildcatPoint
-			Return ("INT3436")
-		}
-
-		// LynxPoint-LP
-		Return ("INT33C6")
-	}
-	Name (_CID, "PNP0D40")
-	Name (_UID, 1)
-
-	// BAR0 is assigned during PCI enumeration and saved into NVS
-	Name (RBUF, ResourceTemplate ()
-	{
-		Memory32Fixed (ReadWrite, 0x00000000, 0x00000000, BAR0)
-		Interrupt (ResourceConsumer, Level, ActiveLow, Shared, , , ) {5}
-	})
-
-	Method (_CRS, 0, NotSerialized)
-	{
-		// Update BAR0 address and length if set in NVS
-		If (\S7B0 != 0) {
-			CreateDwordField (^RBUF, ^BAR0._BAS, B0AD)
-			CreateDwordField (^RBUF, ^BAR0._LEN, B0LN)
-			B0AD = \S7B0
-			B0LN = SIO_BAR_LEN
-		}
-
-		Return (RBUF)
-	}
-
-	Method (_STA, 0, NotSerialized)
-	{
-		If (\S7EN == 0) {
-			Return (0x0)
-		} Else {
-			Return (0xF)
-		}
-	}
-}
diff --git a/src/southbridge/intel/wildcatpoint/acpi/xhci.asl b/src/southbridge/intel/wildcatpoint/acpi/xhci.asl
deleted file mode 100644
index d040201e5b..0000000000
--- a/src/southbridge/intel/wildcatpoint/acpi/xhci.asl
+++ /dev/null
@@ -1,360 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-// XHCI Controller 0:14.0
-
-Device (XHCI)
-{
-	Name (_ADR, 0x00140000)
-
-	OperationRegion (XPRT, PCI_Config, 0, 0x100)
-	Field (XPRT, AnyAcc, NoLock, Preserve)
-	{
-		DVID, 16,
-		Offset (0x10),
-		, 16,
-		XMEM, 16, // MEM_BASE
-		Offset (0x40),
-		, 11,
-		SWAI, 1,
-		, 20,
-		Offset (0x44),
-		, 12,
-		SAIP, 2,
-		, 18,
-		Offset (0x74),
-		D0D3, 2,
-		, 6,
-		PMEE, 1,  // PME_EN
-		, 6,
-		PMES, 1,  // PME_STS
-		Offset (0xb0),
-		, 13,
-		MB13, 1,
-		MB14, 1,
-		Offset (0xd0),
-		PR2R, 32,  // USB2PR
-		PR2M, 32,  // USB2PRM
-		PR3R, 32,  // USB3PR
-		PR3M, 32,  // USB3PRM
-	}
-
-	// Clear status bits
-	Method (LPCL, 0, Serialized)
-	{
-		OperationRegion (XREG, SystemMemory, ^XMEM << 16, 0x600)
-		Field (XREG, DWordAcc, Lock, Preserve)
-		{
-			Offset (0x510), // PORTSCNUSB3[0]
-			PSC0, 32,
-			Offset (0x520), // PORTSCNUSB3[1]
-			PSC1, 32,
-			Offset (0x530), // PORTSCNUSB3[2]
-			PSC2, 32,
-			Offset (0x540), // PORTSCNUSB3[3]
-			PSC3, 32,
-		}
-
-#define PSC_PORT_ENABLED	(1 << 1)
-#define PSC_PORT_CHANGE_BITS	(0x7f << 17)
-
-		// Port 0
-		Local0 = PSC0 & ~PSC_PORT_ENABLED
-		PSC0 = Local0 | PSC_PORT_CHANGE_BITS
-
-		// Port 1
-		Local0 = PSC1 & ~PSC_PORT_ENABLED
-		PSC1 = Local0 | PSC_PORT_CHANGE_BITS
-
-		// Port 2
-		Local0 = PSC2 & ~PSC_PORT_ENABLED
-		PSC2 = Local0 | PSC_PORT_CHANGE_BITS
-
-		// Port 3
-		Local0 = PSC3 & ~PSC_PORT_ENABLED
-		PSC3 = Local0 | PSC_PORT_CHANGE_BITS
-	}
-
-	Method (LPS0, 0, Serialized)
-	{
-		OperationRegion (XREG, SystemMemory, ^XMEM << 16, 0x600)
-		Field (XREG, DWordAcc, Lock, Preserve)
-		{
-			Offset (0x510), // PORTSCNUSB3
-			, 5,
-			PLS1, 4,	// [8:5] Port Link State
-			PPR1, 1,	// [9] Port Power
-			, 7,
-			CSC1, 1,	// [17] Connect Status Change
-			, 1,
-			WRC1, 1,	// [19] Warm Port Reset Change
-			, 11,
-			WPR1, 1,	// [31] Warm Port Reset
-			Offset (0x520), // PORTSCNUSB3
-			, 5,
-			PLS2, 4,	// [8:5] Port Link State
-			PPR2, 1,	// [9] Port Power
-			, 7,
-			CSC2, 1,	// [17] Connect Status Change
-			, 1,
-			WRC2, 1,	// [19] Warm Port Reset Change
-			, 11,
-			WPR2, 1,	// [31] Warm Port Reset
-			Offset (0x530), // PORTSCNUSB3
-			, 5,
-			PLS3, 4,	// [8:5] Port Link State
-			PPR3, 1,	// [9] Port Power
-			, 7,
-			CSC3, 1,	// [17] Connect Status Change
-			, 1,
-			WRC3, 1,	// [19] Warm Port Reset Change
-			, 11,
-			WPR3, 1,	// [31] Warm Port Reset
-			Offset (0x540), // PORTSCNUSB3
-			, 5,
-			PLS4, 4,	// [8:5] Port Link State
-			PPR4, 1,	// [9] Port Power
-			, 7,
-			CSC4, 1,	// [17] Connect Status Change
-			, 1,
-			WRC4, 1,	// [19] Warm Port Reset Change
-			, 11,
-			WPR4, 1,	// [31] Warm Port Reset
-		}
-
-#define PLS_POLLING 7
-
-		// Wait for all powered ports to finish polling
-		Local0 = 10
-		While ((PPR1 == 1 && PLS1 == PLS_POLLING || PPR2 == 1 && PLS2 == PLS_POLLING) ||
-		       (PPR3 == 1 && PLS3 == PLS_POLLING || PPR4 == 1 && PLS4 == PLS_POLLING))
-		{
-			If (Local0 == 0) {
-				Break
-			}
-			Local0--
-			Stall (10)
-		}
-
-		// For each USB3 Port:
-		//   If port is disconnected (PLS=5 PP=1 CSC=0)
-		//     1) Issue warm reset (WPR=1)
-		//     2) Poll for warm reset complete (WRC=0)
-		//     3) Write 1 to port status to clear
-
-		// Local# indicate if port is reset
-		Local1 = 0
-		Local2 = 0
-		Local3 = 0
-		Local4 = 0
-
-#define PLS_RX_DETECT 5
-
-		If (PLS1 == PLS_RX_DETECT && (CSC1 == 0 && PPR1 == 1)) {
-			WPR1 = 1	// Issue warm reset
-			Local1 = 1
-		}
-		If (PLS2 == PLS_RX_DETECT && (CSC2 == 0 && PPR2 == 1)) {
-			WPR2 = 1	// Issue warm reset
-			Local2 = 1
-		}
-		If (PLS3 == PLS_RX_DETECT && (CSC3 == 0 && PPR3 == 1)) {
-			WPR3 = 1	// Issue warm reset
-			Local3 = 1
-		}
-		If (PLS4 == PLS_RX_DETECT && (CSC4 == 0 && PPR4 == 1)) {
-			WPR4 = 1	// Issue warm reset
-			Local4 = 1
-		}
-
-		// Poll for warm reset complete on all ports that were reset
-		Local0 = 10
-		While ((Local1 == 1 && WRC1 == 0 || Local2 == 1 && WRC2 == 0) ||
-		       (Local3 == 1 && WRC3 == 0 || Local4 == 1 && WRC4 == 0))
-		{
-			If (Local0 == 0) {
-				Break
-			}
-			Local0--
-			Stall (10)
-		}
-
-		// Clear status bits in all ports
-		LPCL ()
-	}
-
-	Method (_PSC, 0, NotSerialized)
-	{
-		Return (^D0D3)
-	}
-
-	Method (_PS0, 0, Serialized)
-	{
-		If (^DVID == 0xFFFF) {
-			Return ()
-		}
-		If (^XMEM == 0xFFFF || ^XMEM == 0) {
-			Return ()
-		}
-
-		OperationRegion (XREG, SystemMemory, (^XMEM << 16) + 0x8000, 0x200)
-		Field (XREG, DWordAcc, Lock, Preserve)
-		{
-			Offset (0x0e0), // AUX Reset Control 1
-			, 15,
-			AX15, 1,
-			Offset (0x154), // AUX Domain PM Control Register 2
-			, 31,
-			CLK2, 1,
-			Offset (0x16c), // AUX Clock Control
-			, 2,
-			CLK0, 1,
-			, 11,
-			CLK1, 1, // USB3 Port Aux/Core Clock Gating Enable
-		}
-
-		// If device is in D3, set back to D0
-		Local0 = ^D0D3
-		if (Local0 == 3) {
-			^D0D3 = 0
-		}
-
-		If (!\ISWP()) {
-			// Clear PCI 0xB0[14:13]
-			^MB13 = 0
-			^MB14 = 0
-
-			// Clear MMIO 0x816C[14,2]
-			CLK0 = 0
-			CLK1 = 0
-
-			// Set MMIO 0x8154[31]
-			CLK2 = 1
-
-			// Handle per-port reset if needed
-			LPS0 ()
-
-			// Set MMIO 0x80e0[15]
-			AX15 = 1
-
-			// Clear PCI CFG offset 0x40[11]
-			^SWAI = 0
-
-			// Clear PCI CFG offset 0x44[13:12]
-			^SAIP = 0
-		}
-
-		Return ()
-	}
-
-	Method (_PS3, 0, Serialized)
-	{
-		If (^DVID == 0xFFFF) {
-			Return ()
-		}
-		If (^XMEM == 0xFFFF || ^XMEM == 0) {
-			Return ()
-		}
-
-		OperationRegion (XREG, SystemMemory, (^XMEM << 16) + 0x8000, 0x200)
-		Field (XREG, DWordAcc, Lock, Preserve)
-		{
-			Offset (0x0e0), // AUX Reset Control 1
-			, 15,
-			AX15, 1,
-			Offset (0x154), // AUX Domain PM Control Register 2
-			, 31,
-			CLK2, 1,
-			Offset (0x16c), // AUX Clock Control
-			, 2,
-			CLK0, 1,
-			, 11,
-			CLK1, 1, // USB3 Port Aux/Core Clock Gating Enable
-		}
-
-		^PMES = 1 // Clear PME Status
-		^PMEE = 1 // Enable PME
-
-		// If device is in D3, set back to D0
-		Local0 = ^D0D3
-		if (Local0 == 3) {
-			^D0D3 = 0
-		}
-
-		If (!\ISWP()) {
-			// Set PCI 0xB0[14:13]
-			^MB13 = 1
-			^MB14 = 1
-
-			// Set MMIO 0x816C[14,2]
-			CLK0 = 1
-			CLK1 = 1
-
-			// Clear MMIO 0x8154[31]
-			CLK2 = 0
-
-			// Clear MMIO 0x80e0[15]
-			AX15 = 0
-
-			// Set PCI CFG offset 0x40[11]
-			^SWAI = 1
-
-			// Set PCI CFG offset 0x44[13:12]
-			^SAIP = 1
-		}
-
-		// Put device in D3
-		^D0D3 = 3
-
-		Return ()
-	}
-
-	Name (_PRW, Package (){ 0x6d, 3 })
-
-	// Leave USB ports on for to allow Wake from USB
-
-	Method (_S3D, 0)	// Highest D State in S3 State
-	{
-		Return (3)
-	}
-
-	Method (_S4D, 0)	// Highest D State in S4 State
-	{
-		Return (3)
-	}
-
-	Device (HUB7)
-	{
-		Name (_ADR, 0)
-
-		// GPLD: Generate Port Location Data (PLD)
-		Method (GPLD, 1, Serialized) {
-			Local0 = Package () {
-				Buffer (0x10) {}
-			}
-
-			// REV: Revision 2 for ACPI 5.0
-			CreateField (DerefOf (Local0[0]), 0, 7, REV)
-			REV = 2
-
-			// VISI: Port visibility to user per port
-			CreateField (DerefOf (Local0[0]), 0x40, 1, VISI)
-			VISI = Arg0
-			Return (Local0)
-		}
-
-		Device (PRT1) { Name (_ADR, 1) } // USB Port 0
-		Device (PRT2) { Name (_ADR, 2) } // USB Port 1
-		Device (PRT3) { Name (_ADR, 3) } // USB Port 2
-		Device (PRT4) { Name (_ADR, 4) } // USB Port 3
-		Device (PRT5) { Name (_ADR, 5) } // USB Port 4
-		Device (PRT6) { Name (_ADR, 6) } // USB Port 5
-		Device (PRT7) { Name (_ADR, 7) } // USB Port 6
-		Device (PRT8) { Name (_ADR, 8) } // USB Port 7
-		Device (SSP1) { Name (_ADR, 10) } // USB Port 10
-		Device (SSP2) { Name (_ADR, 11) } // USB Port 11
-		Device (SSP3) { Name (_ADR, 12) } // USB Port 12
-		Device (SSP4) { Name (_ADR, 13) } // USB Port 13
-		Device (SSP5) { Name (_ADR, 14) } // USB Port 14
-		Device (SSP6) { Name (_ADR, 15) } // USB Port 15
-	}
-}

From 44901340bf88f2e16463b1e14b03a9f4e3bf0984 Mon Sep 17 00:00:00 2001
From: Angel Pons <th3fanbus@gmail.com>
Date: Fri, 27 Feb 2026 22:43:48 +0100
Subject: [PATCH 3627/3886] sb/intel/wildcatpoint/pcie.c: Ensure OBFF is
 disabled

For consistency with Lynx Point, ensure OBFF is disabled in DCTL2.

Change-Id: Id726ade900adfce513ad58c77027de8862bd271b
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91471
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
---
 src/southbridge/intel/wildcatpoint/pcie.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/southbridge/intel/wildcatpoint/pcie.c b/src/southbridge/intel/wildcatpoint/pcie.c
index 9262d3c628..ada269fc73 100644
--- a/src/southbridge/intel/wildcatpoint/pcie.c
+++ b/src/southbridge/intel/wildcatpoint/pcie.c
@@ -517,7 +517,7 @@ static void pch_pcie_early(struct device *dev)
 
 	/* Enable LTR in Root Port. Disable OBFF. */
 	pci_update_config32(dev, 0x64, ~(3 << 18), (1 << 11));
-	pci_or_config32(dev, 0x68, 1 << 10);
+	pci_update_config16(dev, 0x68, ~(3 << 13), 1 << 10);
 
 	pci_update_config32(dev, 0x318, ~(0xffff << 16), (0x1414 << 16));
 

From 59ac2cb2c08f6951fa6a8ff63ff36009b65afa69 Mon Sep 17 00:00:00 2001
From: Angel Pons <th3fanbus@gmail.com>
Date: Fri, 27 Feb 2026 22:59:21 +0100
Subject: [PATCH 3628/3886] sb/intel/wildcatpoint/pcie.c: Drop redundant write

This write is already done later on, in `pcie_enable_clock_gating()`.

Change-Id: Id152e1358f581e2a3ef6871a909be366f309c1dd
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91472
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/southbridge/intel/wildcatpoint/pcie.c | 1 -
 1 file changed, 1 deletion(-)

diff --git a/src/southbridge/intel/wildcatpoint/pcie.c b/src/southbridge/intel/wildcatpoint/pcie.c
index ada269fc73..1af776d7d8 100644
--- a/src/southbridge/intel/wildcatpoint/pcie.c
+++ b/src/southbridge/intel/wildcatpoint/pcie.c
@@ -120,7 +120,6 @@ static void root_port_init_config(struct device *dev)
 		rpc.pin_ownership = pci_read_config32(dev, 0x410);
 		root_port_config_update_gbe_port();
 
-		pci_or_config8(dev, 0xe2, 3 << 4);
 		const struct southbridge_intel_wildcatpoint_config *config = config_of(dev);
 		rpc.coalesce = config->pcie_port_coalesce;
 	}

From 2ac2df0edaa75eb88333e231344cb0db801045d7 Mon Sep 17 00:00:00 2001
From: Angel Pons <th3fanbus@gmail.com>
Date: Fri, 27 Feb 2026 23:56:38 +0100
Subject: [PATCH 3629/3886] sb/intel/wildcatpoint/pcie.c: Reorder some steps

Run some steps a bit earlier for consistency with Lynx Point.

Change-Id: I819f95275b23867c83d0991f1eaab3d2e8947abc
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91473
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/southbridge/intel/wildcatpoint/pcie.c | 12 ++++++------
 1 file changed, 6 insertions(+), 6 deletions(-)

diff --git a/src/southbridge/intel/wildcatpoint/pcie.c b/src/southbridge/intel/wildcatpoint/pcie.c
index 1af776d7d8..37d24ef2ee 100644
--- a/src/southbridge/intel/wildcatpoint/pcie.c
+++ b/src/southbridge/intel/wildcatpoint/pcie.c
@@ -538,6 +538,12 @@ static void pch_pcie_early(struct device *dev)
 
 	pci_and_config8(dev, 0xf5, 0x0f);
 
+	if (rp == 1 || rp == 5 || rp == 6)
+		pci_and_config8(dev, 0xf7, ~0x0c);
+
+	/* Set EOI forwarding disable. */
+	pci_or_config32(dev, 0xd4, 1 << 1);
+
 	/* Set AER Extended Cap ID to 01h and Next Cap Pointer to 200h. */
 	if (CONFIG(PCIEXP_AER))
 		pci_update_config32(dev, 0x100, ~0xfffff, (1 << 29) | 0x10001);
@@ -555,12 +561,6 @@ static void pch_pcie_early(struct device *dev)
 	/* Enable Relaxed Order from Root Port. */
 	pci_or_config32(dev, 0x320, 3 << 23);
 
-	if (rp == 1 || rp == 5 || rp == 6)
-		pci_update_config8(dev, 0xf7, ~0xc, 0);
-
-	/* Set EOI forwarding disable. */
-	pci_update_config32(dev, 0xd4, ~0, (1 << 1));
-
 	/* Read and write back write-once capability registers. */
 	pci_update_config32(dev, 0x34, ~0, 0);
 	pci_update_config32(dev, 0x40, ~0, 0);

From fd6c0aa55bf8a2921c357eee44c5286a0d758efd Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Tue, 28 Oct 2025 10:56:47 +0000
Subject: [PATCH 3630/3886] util/scripts: Add spd-decode for LPDDR5 SPD hex

Decode LPDDR5/LPDDR5X .spd.hex dumps into spd_tools-compatible JSON.
The default output is a single-part memory_parts.json-style document
without the bits that spd_gen adds automatically.

Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I49874bcd42cf3981277abbfa997ec185088f0715
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89785
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 util/scripts/spd-decode-ddr5 | 311 +++++++++++++++++++++++++++++++++++
 1 file changed, 311 insertions(+)
 create mode 100755 util/scripts/spd-decode-ddr5

diff --git a/util/scripts/spd-decode-ddr5 b/util/scripts/spd-decode-ddr5
new file mode 100755
index 0000000000..a0080b0e7b
--- /dev/null
+++ b/util/scripts/spd-decode-ddr5
@@ -0,0 +1,311 @@
+#!/usr/bin/env python3
+#
+# SPDX-License-Identifier: GPL-2.0-or-later
+"""
+Decode an LPDDR5/LPDDR5X SPD text hex file into JSON.
+
+Default output format is compatible with coreboot's spd_tools `spd_gen`:
+it emits a `memory_parts.json` containing a single part entry.
+
+This tool is intentionally named `spd-decode` even though it currently only
+supports LPDDR5/LPDDR5X SPDs, so it can be extended to other SPD types later.
+
+Usage:
+  spd-decode <path/to/spd.hex> [--pretty] [--name NAME]
+            [--include-nondefault-timings]
+  spd-decode <path/to/spd.hex> --format raw [--pretty]
+
+Options:
+  --format spd_gen      Output a `memory_parts.json`-style document for
+                        coreboot's spd_tools `spd_gen`.
+  --format raw          Output the fully decoded SPD fields as JSON.
+  --name NAME           Override the part name in spd_gen output.
+  --include-nondefault-timings
+                        Include timing fields in spd_gen output only when they
+                        differ from spd_gen defaults.
+  --pretty              Pretty-print JSON (tabs) and include a command header.
+
+Only LPDDR5 (0x13) and LPDDR5X (0x15) SPDs are supported.
+"""
+
+import argparse
+import json
+import os
+import sys
+from typing import Dict, List, Optional
+
+
+def _json_dumps_tabs(obj) -> str:
+	# Dump JSON with one-space indent and convert leading spaces to tabs.
+	s = json.dumps(obj, indent=1, separators=(",", ": "), ensure_ascii=False)
+	lines = []
+	for line in s.splitlines():
+		n = 0
+		while n < len(line) and line[n] == " ":
+			n += 1
+		if n:
+			line = ("\t" * n) + line[n:]
+		lines.append(line)
+	return "\n".join(lines) + "\n"
+
+
+def _to_signed_byte(b: int) -> int:
+	return b - 256 if b >= 128 else b
+
+
+def _parse_hex_file(path: str) -> List[int]:
+	data: List[int] = []
+	with open(path, "r", encoding="utf-8") as f:
+		for line in f:
+			line = line.strip()
+			if not line:
+				continue
+			for p in line.split():
+				if len(p) != 2:
+					raise ValueError(f"Invalid hex byte '{p}' in {path}")
+				data.append(int(p, 16))
+	return data
+
+
+def _decode_time_ps(mtb_byte: int, ftb_byte: int) -> int:
+	# MTB unit = 125 ps. FTB is signed 8-bit offset in ps.
+	return (mtb_byte * 125) + _to_signed_byte(ftb_byte)
+
+
+def _decode_time_ns_from_16bit_mtb(lsb: int, msb: int) -> float:
+	# 16-bit MTB value in units of 125ps -> convert to ns (float)
+	mtb = (msb << 8) | lsb
+	ps = mtb * 125
+	return ps / 1000.0
+
+
+def _round_int(x: float) -> int:
+	return int(round(x))
+
+
+def _closest_speed_from_tck_ps(tck_ps: int, set_rev: int) -> int:
+	# Allowed LP5 speed bins in Mbps
+	bins = [5500, 6400, 7500, 8533]
+	if set_rev == 0x10:
+		# ADL set encodes CK tCKmin = 1 / (WCK rate / 4) = 8e6 / speed
+		guess = 8_000_000.0 / max(tck_ps, 1)
+	else:
+		# Default SPD encodes WCK tCKmin = 2e6 / speed
+		guess = 2_000_000.0 / max(tck_ps, 1)
+	return int(min(bins, key=lambda b: abs(b - guess)))
+
+
+def _default_part_name_from_path(path: str) -> str:
+	base = os.path.basename(path)
+	for suffix in (".spd.hex", ".hex"):
+		if base.endswith(suffix):
+			base = base[: -len(suffix)]
+			break
+	return base
+
+
+def _lp5_defaults_for_optional_attribs(density_gb: Optional[int]) -> Dict[str, int]:
+	# Match util/spd_tools/src/spd_gen/lp5.go defaults.
+	trfc = {
+		4: (180, 90),
+		6: (210, 120),
+		8: (210, 120),
+		12: (280, 140),
+		16: (280, 140),
+		24: (380, 190),
+		32: (380, 190),
+	}
+	trfcab, trfcpb = trfc.get(density_gb, (0, 0))
+	return {
+		"trfcabNs": trfcab,
+		"trfcpbNs": trfcpb,
+		"trcdMinNs": 18,
+		"trpabMinNs": 21,
+		"trppbMinNs": 18,
+	}
+
+
+def decode_lp5(spd: List[int]) -> Dict:
+	if len(spd) < 349:
+		raise ValueError("LPDDR5 SPD must contain at least 349 bytes")
+
+	# Byte indices (match util/spd_tools/src/spd_gen/lp5.go)
+	IDX = {
+		"REV": 1,
+		"MEM_TYPE": 2,
+		"DENSITY_BANKS": 4,
+		"ADDR": 5,
+		"PKG_TYPE": 6,
+		"OPT_FEATURES": 7,
+		"OTHER_OPT_FEATURES": 9,
+		"MODULE_ORG": 12,
+		"BUS_WIDTH": 13,
+		"TIMEBASES": 17,
+		"TCK_MIN": 18,
+		"TAA_MIN": 24,
+		"TRCD_MIN": 26,
+		"TRPAB_MIN": 27,
+		"TRPPB_MIN": 28,
+		"TRFCAB_LSB": 29,
+		"TRFCAB_MSB": 30,
+		"TRFCPB_LSB": 31,
+		"TRFCPB_MSB": 32,
+		"TRPPB_FINE": 120,
+		"TRPAB_FINE": 121,
+		"TRCD_FINE": 122,
+		"TAA_FINE": 123,
+		"TCK_FINE": 125,
+		"MPN_START": 329,
+		"MPN_END": 348,
+	}
+
+	mem_type = spd[IDX["MEM_TYPE"]]
+	rev = spd[IDX["REV"]]
+	if mem_type == 0x13:
+		mem_type_str = "LPDDR5"
+		lp5x = False
+	elif mem_type == 0x15:
+		mem_type_str = "LPDDR5X"
+		lp5x = True
+	else:
+		mem_type_str = f"Unknown(0x{mem_type:02x})"
+		lp5x = False
+
+	density_code = spd[IDX["DENSITY_BANKS"]] & 0x0F
+	density_map = {
+		0x4: 4,
+		0xB: 6,
+		0x5: 8,
+		0x8: 12,
+		0x6: 16,
+		0x9: 24,
+		0x7: 32,
+	}
+	density_per_die_gb = density_map.get(density_code)
+
+	dies_per_package = ((spd[IDX["PKG_TYPE"]] >> 4) & 0x7) + 1
+	ranks_per_channel = ((spd[IDX["MODULE_ORG"]] >> 3) & 0x7) + 1
+	bit_width_per_channel = (spd[IDX["MODULE_ORG"]] & 0x7) * 8
+	channels_per_pkg = 1 << ((spd[IDX["PKG_TYPE"]] >> 2) & 0x3)
+
+	tck_ps = _decode_time_ps(spd[IDX["TCK_MIN"]], spd[IDX["TCK_FINE"]])
+	speed_mbps = _closest_speed_from_tck_ps(tck_ps, rev)
+	if not lp5x and speed_mbps >= 7500:
+		lp5x = True
+
+	taa_ps = _decode_time_ps(spd[IDX["TAA_MIN"]], spd[IDX["TAA_FINE"]])
+	trcd_ns = _round_int(_decode_time_ps(spd[IDX["TRCD_MIN"]], spd[IDX["TRCD_FINE"]]) / 1000.0)
+	trpab_ns = _round_int(_decode_time_ps(spd[IDX["TRPAB_MIN"]], spd[IDX["TRPAB_FINE"]]) / 1000.0)
+	trppb_ns = _round_int(_decode_time_ps(spd[IDX["TRPPB_MIN"]], spd[IDX["TRPPB_FINE"]]) / 1000.0)
+	trfcab_ns = _round_int(_decode_time_ns_from_16bit_mtb(spd[IDX["TRFCAB_LSB"]], spd[IDX["TRFCAB_MSB"]]))
+	trfcpb_ns = _round_int(_decode_time_ns_from_16bit_mtb(spd[IDX["TRFCPB_LSB"]], spd[IDX["TRFCPB_MSB"]]))
+
+	mpn_bytes = spd[IDX["MPN_START"] : IDX["MPN_END"] + 1]
+	try:
+		mpn = bytes(mpn_bytes).decode("ascii").strip()
+	except Exception:
+		mpn = ""
+
+	return {
+		"memoryType": mem_type_str,
+		"revision": f"0x{rev:02x}",
+		"channelsPerPackage": channels_per_pkg,
+		"manufacturerPartNumber": mpn or None,
+		"attributes": {
+			"densityPerDieGb": density_per_die_gb,
+			"diesPerPackage": dies_per_package,
+			"bitWidthPerChannel": bit_width_per_channel,
+			"ranksPerChannel": ranks_per_channel,
+			"speedMbps": speed_mbps,
+			"lp5x": lp5x,
+			"tckMinPs": tck_ps,
+			"taaMinPs": taa_ps,
+			"trcdMinNs": trcd_ns,
+			"trpabMinNs": trpab_ns,
+			"trppbMinNs": trppb_ns,
+			"trfcabNs": trfcab_ns,
+			"trfcpbNs": trfcpb_ns,
+		},
+	}
+
+
+def detect_and_decode(spd: List[int]) -> Dict:
+	if len(spd) < 3:
+		raise ValueError("SPD data too short")
+	mem_type = spd[2]
+	if mem_type in (0x13, 0x15):
+		return decode_lp5(spd)
+	raise NotImplementedError(f"Unsupported or unknown SPD memory type 0x{mem_type:02x}")
+
+
+def _to_spd_gen_memory_parts(decoded: Dict, part_name: str, include_nondefault_timings: bool) -> Dict:
+	attribs_in = decoded.get("attributes", {})
+
+	attribs_out = {
+		"densityPerDieGb": attribs_in.get("densityPerDieGb"),
+		"diesPerPackage": attribs_in.get("diesPerPackage"),
+		"bitWidthPerChannel": attribs_in.get("bitWidthPerChannel"),
+		"ranksPerChannel": attribs_in.get("ranksPerChannel"),
+		"speedMbps": attribs_in.get("speedMbps"),
+	}
+
+	if attribs_in.get("lp5x"):
+		attribs_out["lp5x"] = True
+
+	if include_nondefault_timings:
+		defaults = _lp5_defaults_for_optional_attribs(attribs_in.get("densityPerDieGb"))
+		for k in ("trfcabNs", "trfcpbNs", "trcdMinNs", "trpabMinNs", "trppbMinNs"):
+			v = attribs_in.get(k)
+			if v is None:
+				continue
+			if defaults.get(k) and v != defaults[k]:
+				attribs_out[k] = v
+
+	part = {"name": part_name, "attribs": attribs_out}
+	return {"parts": [part]}
+
+
+def main(argv: List[str]) -> int:
+	ap = argparse.ArgumentParser(description="Decode LPDDR5 SPD .hex file to JSON")
+	ap.add_argument("hexfile", help="Path to SPD hex file (text with space-separated bytes)")
+	ap.add_argument(
+		"--format",
+		choices=("spd_gen", "raw"),
+		default="spd_gen",
+		help="Output JSON format: spd_gen (memory_parts.json) or raw",
+	)
+	ap.add_argument(
+		"--name",
+		help="Part name for spd_gen output (defaults to MPN or input filename)",
+	)
+	ap.add_argument(
+		"--include-nondefault-timings",
+		action="store_true",
+		help="Include timing fields only when they differ from spd_gen defaults (spd_gen output only)",
+	)
+	ap.add_argument(
+		"--pretty",
+		action="store_true",
+		help="Pretty-print JSON output with a command header",
+	)
+	args = ap.parse_args(argv)
+
+	spd = _parse_hex_file(args.hexfile)
+	decoded = detect_and_decode(spd)
+
+	if args.format == "raw":
+		out_obj = decoded
+	else:
+		part_name = args.name or decoded.get("manufacturerPartNumber") or _default_part_name_from_path(args.hexfile)
+		out_obj = _to_spd_gen_memory_parts(decoded, part_name, args.include_nondefault_timings)
+
+	if args.pretty:
+		header = f"// Generated by:\n// {' '.join([sys.argv[0]] + argv)}\n\n"
+		print(header + _json_dumps_tabs(out_obj), end="")
+	else:
+		print(json.dumps(out_obj, separators=(",", ":"), ensure_ascii=False))
+	return 0
+
+
+if __name__ == "__main__":
+	raise SystemExit(main(sys.argv[1:]))

From 346a4ccaef8eb04e1b7ebb763a11c4cf57902139 Mon Sep 17 00:00:00 2001
From: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
Date: Thu, 5 Mar 2026 15:45:45 +0800
Subject: [PATCH 3631/3886] mb/google/fatcat/moonstone: Add Samsung LPDDR5
 memory parts

Add Samsung K3KL8L80EM-MGCU and K3KL9L90EM-MGCU to the supported
memory parts list for the moonstone variant.

BUG=None
BRANCH=None
TEST=Regenerate SPD ID for moonstone via spd_tools

Change-Id: Iefde607ef703b7355b4516bf8f4fbe0129f7150d
Signed-off-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91559
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 .../google/fatcat/variants/moonstone/memory/Makefile.mk       | 4 ++--
 .../fatcat/variants/moonstone/memory/dram_id.generated.txt    | 2 ++
 .../fatcat/variants/moonstone/memory/mem_parts_used.txt       | 2 ++
 3 files changed, 6 insertions(+), 2 deletions(-)

diff --git a/src/mainboard/google/fatcat/variants/moonstone/memory/Makefile.mk b/src/mainboard/google/fatcat/variants/moonstone/memory/Makefile.mk
index 4b3374bf05..099824e798 100644
--- a/src/mainboard/google/fatcat/variants/moonstone/memory/Makefile.mk
+++ b/src/mainboard/google/fatcat/variants/moonstone/memory/Makefile.mk
@@ -5,5 +5,5 @@
 
 SPD_SOURCES =
 SPD_SOURCES += spd/lp5/set-0/spd-7.hex      # ID = 0(0b0000)  Parts = H58G56BK7BX068
-SPD_SOURCES += spd/lp5/set-0/spd-11.hex      # ID = 1(0b0001)  Parts = MT62F1G32D2DS-023 WT:C, H58G56CK8BX146
-SPD_SOURCES += spd/lp5/set-0/spd-10.hex      # ID = 2(0b0010)  Parts = MT62F2G32D4DS-020 WT:F, MT62F2G32D4DS-023 WT:C, H58G66CK8BX147
+SPD_SOURCES += spd/lp5/set-0/spd-11.hex      # ID = 1(0b0001)  Parts = MT62F1G32D2DS-023 WT:C, H58G56CK8BX146, K3KL8L80EM-MGCU
+SPD_SOURCES += spd/lp5/set-0/spd-10.hex      # ID = 2(0b0010)  Parts = MT62F2G32D4DS-020 WT:F, MT62F2G32D4DS-023 WT:C, H58G66CK8BX147, K3KL9L90EM-MGCU
diff --git a/src/mainboard/google/fatcat/variants/moonstone/memory/dram_id.generated.txt b/src/mainboard/google/fatcat/variants/moonstone/memory/dram_id.generated.txt
index b1e522b4f7..01e2fa51ca 100644
--- a/src/mainboard/google/fatcat/variants/moonstone/memory/dram_id.generated.txt
+++ b/src/mainboard/google/fatcat/variants/moonstone/memory/dram_id.generated.txt
@@ -10,3 +10,5 @@ MT62F2G32D4DS-020 WT:F         2 (0010)
 H58G56CK8BX146                 1 (0001)
 MT62F2G32D4DS-023 WT:C         2 (0010)
 H58G66CK8BX147                 2 (0010)
+K3KL8L80EM-MGCU                1 (0001)
+K3KL9L90EM-MGCU                2 (0010)
diff --git a/src/mainboard/google/fatcat/variants/moonstone/memory/mem_parts_used.txt b/src/mainboard/google/fatcat/variants/moonstone/memory/mem_parts_used.txt
index a78826b02c..4cb77f9477 100644
--- a/src/mainboard/google/fatcat/variants/moonstone/memory/mem_parts_used.txt
+++ b/src/mainboard/google/fatcat/variants/moonstone/memory/mem_parts_used.txt
@@ -15,3 +15,5 @@ MT62F2G32D4DS-020 WT:F
 H58G56CK8BX146
 MT62F2G32D4DS-023 WT:C
 H58G66CK8BX147
+K3KL8L80EM-MGCU
+K3KL9L90EM-MGCU

From b1194a838b32d0b3f2220f671314d1ba59c112fe Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Thu, 5 Mar 2026 15:09:25 -0600
Subject: [PATCH 3632/3886] mb/starlabs: Use common devtree_update mechanism

Remove the explicit devtree_update() call from mainboard configuration.
The devtree_update hook is provided by src/lib/devtree_update.c and runs
at BS_PRE_DEVICE. Drop the variant declarations from variants.h and add
the devtree_update header in each variant devtree.c so their overrides
are used via the common mechanism.

TEST=build/boot Starlabs Starfighter MTL

Change-Id: Ia7ceaaefe717566c6411f86d81d3a76bdfb2b2ea
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91573
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/starlabs/adl/include/variants.h             | 2 --
 src/mainboard/starlabs/adl/mainboard.c                    | 2 --
 src/mainboard/starlabs/adl/variants/hz/devtree.c          | 1 +
 src/mainboard/starlabs/adl/variants/i5/devtree.c          | 1 +
 src/mainboard/starlabs/adl/variants/y2/devtree.c          | 1 +
 src/mainboard/starlabs/lite/devtree.c                     | 1 +
 src/mainboard/starlabs/lite/include/variants.h            | 2 --
 src/mainboard/starlabs/starbook/include/variants.h        | 2 --
 src/mainboard/starlabs/starbook/variants/adl/devtree.c    | 1 +
 src/mainboard/starlabs/starbook/variants/adl_n/devtree.c  | 1 +
 src/mainboard/starlabs/starbook/variants/cml/devtree.c    | 1 +
 src/mainboard/starlabs/starbook/variants/kbl/devtree.c    | 1 +
 src/mainboard/starlabs/starbook/variants/mtl/devtree.c    | 1 +
 src/mainboard/starlabs/starbook/variants/rpl/devtree.c    | 1 +
 src/mainboard/starlabs/starbook/variants/tgl/devtree.c    | 1 +
 src/mainboard/starlabs/starfighter/include/variants.h     | 2 --
 src/mainboard/starlabs/starfighter/variants/mtl/devtree.c | 1 +
 src/mainboard/starlabs/starfighter/variants/rpl/devtree.c | 1 +
 18 files changed, 13 insertions(+), 10 deletions(-)

diff --git a/src/mainboard/starlabs/adl/include/variants.h b/src/mainboard/starlabs/adl/include/variants.h
index 536ac891ae..f9dc0ee73b 100644
--- a/src/mainboard/starlabs/adl/include/variants.h
+++ b/src/mainboard/starlabs/adl/include/variants.h
@@ -13,8 +13,6 @@
 const struct pad_config *variant_gpio_table(size_t *num);
 const struct pad_config *variant_early_gpio_table(size_t *num);
 
-void devtree_update(void);
-
 void starlabs_adl_mainboard_fill_ssdt(const struct device *dev);
 
 #endif /* _BASEBOARD_VARIANTS_H_ */
diff --git a/src/mainboard/starlabs/adl/mainboard.c b/src/mainboard/starlabs/adl/mainboard.c
index 940584b151..d7a0dab9a8 100644
--- a/src/mainboard/starlabs/adl/mainboard.c
+++ b/src/mainboard/starlabs/adl/mainboard.c
@@ -13,8 +13,6 @@ static void starlabs_configure_mainboard(void *unused)
 
 	pads = variant_gpio_table(&num);
 	gpio_configure_pads(pads, num);
-
-	devtree_update();
 }
 
 BOOT_STATE_INIT_ENTRY(BS_PRE_DEVICE, BS_ON_ENTRY, starlabs_configure_mainboard, NULL);
diff --git a/src/mainboard/starlabs/adl/variants/hz/devtree.c b/src/mainboard/starlabs/adl/variants/hz/devtree.c
index 3ae2d08956..7f1ddfc9ec 100644
--- a/src/mainboard/starlabs/adl/variants/hz/devtree.c
+++ b/src/mainboard/starlabs/adl/variants/hz/devtree.c
@@ -4,6 +4,7 @@
 #include <cpu/intel/turbo.h>
 #include <device/device.h>
 #include <device/pci_def.h>
+#include <devtree_update.h>
 #include <option.h>
 #include <static.h>
 #include <types.h>
diff --git a/src/mainboard/starlabs/adl/variants/i5/devtree.c b/src/mainboard/starlabs/adl/variants/i5/devtree.c
index 4a13543bf6..6dee98c4df 100644
--- a/src/mainboard/starlabs/adl/variants/i5/devtree.c
+++ b/src/mainboard/starlabs/adl/variants/i5/devtree.c
@@ -4,6 +4,7 @@
 #include <cpu/intel/turbo.h>
 #include <device/device.h>
 #include <device/pci_def.h>
+#include <devtree_update.h>
 #include <option.h>
 #include <static.h>
 #include <types.h>
diff --git a/src/mainboard/starlabs/adl/variants/y2/devtree.c b/src/mainboard/starlabs/adl/variants/y2/devtree.c
index aaa5fdafae..607f1374ed 100644
--- a/src/mainboard/starlabs/adl/variants/y2/devtree.c
+++ b/src/mainboard/starlabs/adl/variants/y2/devtree.c
@@ -4,6 +4,7 @@
 #include <cpu/intel/turbo.h>
 #include <device/device.h>
 #include <device/pci_def.h>
+#include <devtree_update.h>
 #include <option.h>
 #include <static.h>
 #include <types.h>
diff --git a/src/mainboard/starlabs/lite/devtree.c b/src/mainboard/starlabs/lite/devtree.c
index afbd1bba11..b453196788 100644
--- a/src/mainboard/starlabs/lite/devtree.c
+++ b/src/mainboard/starlabs/lite/devtree.c
@@ -3,6 +3,7 @@
 #include <cpu/intel/turbo.h>
 #include <device/device.h>
 #include <device/pci_def.h>
+#include <devtree_update.h>
 #include <option.h>
 #include <static.h>
 #include <types.h>
diff --git a/src/mainboard/starlabs/lite/include/variants.h b/src/mainboard/starlabs/lite/include/variants.h
index 781a8313f2..ef4ecf7409 100644
--- a/src/mainboard/starlabs/lite/include/variants.h
+++ b/src/mainboard/starlabs/lite/include/variants.h
@@ -12,6 +12,4 @@
 const struct pad_config *variant_gpio_table(size_t *num);
 const struct pad_config *variant_early_gpio_table(size_t *num);
 
-void devtree_update(void);
-
 #endif /* _BASEBOARD_VARIANTS_H_ */
diff --git a/src/mainboard/starlabs/starbook/include/variants.h b/src/mainboard/starlabs/starbook/include/variants.h
index 781a8313f2..ef4ecf7409 100644
--- a/src/mainboard/starlabs/starbook/include/variants.h
+++ b/src/mainboard/starlabs/starbook/include/variants.h
@@ -12,6 +12,4 @@
 const struct pad_config *variant_gpio_table(size_t *num);
 const struct pad_config *variant_early_gpio_table(size_t *num);
 
-void devtree_update(void);
-
 #endif /* _BASEBOARD_VARIANTS_H_ */
diff --git a/src/mainboard/starlabs/starbook/variants/adl/devtree.c b/src/mainboard/starlabs/starbook/variants/adl/devtree.c
index 3379e02dae..8c51abe73c 100644
--- a/src/mainboard/starlabs/starbook/variants/adl/devtree.c
+++ b/src/mainboard/starlabs/starbook/variants/adl/devtree.c
@@ -4,6 +4,7 @@
 #include <cpu/intel/turbo.h>
 #include <device/device.h>
 #include <device/pci_def.h>
+#include <devtree_update.h>
 #include <option.h>
 #include <static.h>
 #include <types.h>
diff --git a/src/mainboard/starlabs/starbook/variants/adl_n/devtree.c b/src/mainboard/starlabs/starbook/variants/adl_n/devtree.c
index 1b01e25cb0..001965d1ea 100644
--- a/src/mainboard/starlabs/starbook/variants/adl_n/devtree.c
+++ b/src/mainboard/starlabs/starbook/variants/adl_n/devtree.c
@@ -4,6 +4,7 @@
 #include <cpu/intel/turbo.h>
 #include <device/device.h>
 #include <device/pci_def.h>
+#include <devtree_update.h>
 #include <option.h>
 #include <static.h>
 #include <types.h>
diff --git a/src/mainboard/starlabs/starbook/variants/cml/devtree.c b/src/mainboard/starlabs/starbook/variants/cml/devtree.c
index 980a472abc..6ed8999261 100644
--- a/src/mainboard/starlabs/starbook/variants/cml/devtree.c
+++ b/src/mainboard/starlabs/starbook/variants/cml/devtree.c
@@ -4,6 +4,7 @@
 #include <cpu/intel/turbo.h>
 #include <device/device.h>
 #include <device/pci_def.h>
+#include <devtree_update.h>
 #include <option.h>
 #include <static.h>
 #include <types.h>
diff --git a/src/mainboard/starlabs/starbook/variants/kbl/devtree.c b/src/mainboard/starlabs/starbook/variants/kbl/devtree.c
index 2dd0f995ab..851a083fb0 100644
--- a/src/mainboard/starlabs/starbook/variants/kbl/devtree.c
+++ b/src/mainboard/starlabs/starbook/variants/kbl/devtree.c
@@ -4,6 +4,7 @@
 #include <cpu/intel/turbo.h>
 #include <device/device.h>
 #include <device/pci_def.h>
+#include <devtree_update.h>
 #include <option.h>
 #include <static.h>
 #include <types.h>
diff --git a/src/mainboard/starlabs/starbook/variants/mtl/devtree.c b/src/mainboard/starlabs/starbook/variants/mtl/devtree.c
index 0b2cd1b959..0eedb7c599 100644
--- a/src/mainboard/starlabs/starbook/variants/mtl/devtree.c
+++ b/src/mainboard/starlabs/starbook/variants/mtl/devtree.c
@@ -4,6 +4,7 @@
 #include <cpu/intel/turbo.h>
 #include <device/device.h>
 #include <device/pci_def.h>
+#include <devtree_update.h>
 #include <option.h>
 #include <static.h>
 #include <types.h>
diff --git a/src/mainboard/starlabs/starbook/variants/rpl/devtree.c b/src/mainboard/starlabs/starbook/variants/rpl/devtree.c
index fe9ec1b3e2..6fe7fcf812 100644
--- a/src/mainboard/starlabs/starbook/variants/rpl/devtree.c
+++ b/src/mainboard/starlabs/starbook/variants/rpl/devtree.c
@@ -4,6 +4,7 @@
 #include <cpu/intel/turbo.h>
 #include <device/device.h>
 #include <device/pci_def.h>
+#include <devtree_update.h>
 #include <option.h>
 #include <static.h>
 #include <types.h>
diff --git a/src/mainboard/starlabs/starbook/variants/tgl/devtree.c b/src/mainboard/starlabs/starbook/variants/tgl/devtree.c
index 796624e1c6..ef23fb632e 100644
--- a/src/mainboard/starlabs/starbook/variants/tgl/devtree.c
+++ b/src/mainboard/starlabs/starbook/variants/tgl/devtree.c
@@ -4,6 +4,7 @@
 #include <cpu/intel/turbo.h>
 #include <device/device.h>
 #include <device/pci_def.h>
+#include <devtree_update.h>
 #include <option.h>
 #include <static.h>
 #include <types.h>
diff --git a/src/mainboard/starlabs/starfighter/include/variants.h b/src/mainboard/starlabs/starfighter/include/variants.h
index b3334870b1..0bdd25bd9d 100644
--- a/src/mainboard/starlabs/starfighter/include/variants.h
+++ b/src/mainboard/starlabs/starfighter/include/variants.h
@@ -14,6 +14,4 @@ uint8_t get_memory_config_straps(void);
 const struct pad_config *variant_gpio_table(size_t *num);
 const struct pad_config *variant_early_gpio_table(size_t *num);
 
-void devtree_update(void);
-
 #endif /* _BASEBOARD_VARIANTS_H_ */
diff --git a/src/mainboard/starlabs/starfighter/variants/mtl/devtree.c b/src/mainboard/starlabs/starfighter/variants/mtl/devtree.c
index 5ac632b4b7..fc41e37e7d 100644
--- a/src/mainboard/starlabs/starfighter/variants/mtl/devtree.c
+++ b/src/mainboard/starlabs/starfighter/variants/mtl/devtree.c
@@ -4,6 +4,7 @@
 #include <cpu/intel/turbo.h>
 #include <device/device.h>
 #include <device/pci_def.h>
+#include <devtree_update.h>
 #include <option.h>
 #include <static.h>
 #include <types.h>
diff --git a/src/mainboard/starlabs/starfighter/variants/rpl/devtree.c b/src/mainboard/starlabs/starfighter/variants/rpl/devtree.c
index aea5d89b40..f2d497fa2f 100644
--- a/src/mainboard/starlabs/starfighter/variants/rpl/devtree.c
+++ b/src/mainboard/starlabs/starfighter/variants/rpl/devtree.c
@@ -4,6 +4,7 @@
 #include <cpu/intel/turbo.h>
 #include <device/device.h>
 #include <device/pci_def.h>
+#include <devtree_update.h>
 #include <option.h>
 #include <static.h>
 #include <types.h>

From 00e3b9989c9506133956b54d501f04cb5b75d9cb Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Thu, 5 Mar 2026 09:37:34 -0600
Subject: [PATCH 3633/3886] lib: Rename devtree_update to mb_devtree_update

Rename the devtree_update() bootstate hook added in commit f8494fbeae6b
("lib: Add devtree_update bootstate hook") to mb_devtree_update()
for clarity, since it is a mainboard-provided hook.

Update all declarations, definitions, and call sites accordingly.

TEST=build Starlabs Starfighter MTL

Change-Id: Id7fd9811433a668905d8439b90a8ee34a472d117
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91570
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
---
 src/include/devtree_update.h                              | 2 +-
 src/lib/devtree_update.c                                  | 4 ++--
 src/mainboard/starlabs/adl/variants/hz/devtree.c          | 2 +-
 src/mainboard/starlabs/adl/variants/i5/devtree.c          | 2 +-
 src/mainboard/starlabs/adl/variants/y2/devtree.c          | 2 +-
 src/mainboard/starlabs/lite/devtree.c                     | 2 +-
 src/mainboard/starlabs/starbook/variants/adl/devtree.c    | 2 +-
 src/mainboard/starlabs/starbook/variants/adl_n/devtree.c  | 2 +-
 src/mainboard/starlabs/starbook/variants/cml/devtree.c    | 2 +-
 src/mainboard/starlabs/starbook/variants/kbl/devtree.c    | 2 +-
 src/mainboard/starlabs/starbook/variants/mtl/devtree.c    | 2 +-
 src/mainboard/starlabs/starbook/variants/rpl/devtree.c    | 2 +-
 src/mainboard/starlabs/starbook/variants/tgl/devtree.c    | 2 +-
 src/mainboard/starlabs/starfighter/variants/mtl/devtree.c | 2 +-
 src/mainboard/starlabs/starfighter/variants/rpl/devtree.c | 2 +-
 15 files changed, 16 insertions(+), 16 deletions(-)

diff --git a/src/include/devtree_update.h b/src/include/devtree_update.h
index b99b689b99..2392b7a3c4 100644
--- a/src/include/devtree_update.h
+++ b/src/include/devtree_update.h
@@ -9,6 +9,6 @@
  *
  * This function is called early in ramstage at BS_PRE_DEVICE.
  */
-void devtree_update(void);
+void mb_devtree_update(void);
 
 #endif /* __DEVTREE_UPDATE_H__ */
diff --git a/src/lib/devtree_update.c b/src/lib/devtree_update.c
index 1b454a2580..d6d402402d 100644
--- a/src/lib/devtree_update.c
+++ b/src/lib/devtree_update.c
@@ -4,13 +4,13 @@
 #include <commonlib/bsd/compiler.h>
 #include <devtree_update.h>
 
-__weak void devtree_update(void)
+__weak void mb_devtree_update(void)
 {
 }
 
 static void run_devtree_update(void *unused)
 {
-	devtree_update();
+	mb_devtree_update();
 }
 
 BOOT_STATE_INIT_ENTRY(BS_PRE_DEVICE, BS_ON_ENTRY, run_devtree_update, NULL);
diff --git a/src/mainboard/starlabs/adl/variants/hz/devtree.c b/src/mainboard/starlabs/adl/variants/hz/devtree.c
index 7f1ddfc9ec..c53fbb3bd0 100644
--- a/src/mainboard/starlabs/adl/variants/hz/devtree.c
+++ b/src/mainboard/starlabs/adl/variants/hz/devtree.c
@@ -11,7 +11,7 @@
 #include <variants.h>
 #include <common/powercap.h>
 
-void devtree_update(void)
+void mb_devtree_update(void)
 {
 	config_t *cfg = config_of_soc();
 	update_power_limits(cfg);
diff --git a/src/mainboard/starlabs/adl/variants/i5/devtree.c b/src/mainboard/starlabs/adl/variants/i5/devtree.c
index 6dee98c4df..4d76c77bb8 100644
--- a/src/mainboard/starlabs/adl/variants/i5/devtree.c
+++ b/src/mainboard/starlabs/adl/variants/i5/devtree.c
@@ -11,7 +11,7 @@
 #include <variants.h>
 #include <common/powercap.h>
 
-void devtree_update(void)
+void mb_devtree_update(void)
 {
 	config_t *cfg = config_of_soc();
 	update_power_limits(cfg);
diff --git a/src/mainboard/starlabs/adl/variants/y2/devtree.c b/src/mainboard/starlabs/adl/variants/y2/devtree.c
index 607f1374ed..3824fe9a7e 100644
--- a/src/mainboard/starlabs/adl/variants/y2/devtree.c
+++ b/src/mainboard/starlabs/adl/variants/y2/devtree.c
@@ -11,7 +11,7 @@
 #include <variants.h>
 #include <common/powercap.h>
 
-void devtree_update(void)
+void mb_devtree_update(void)
 {
 	config_t *cfg = config_of_soc();
 	update_power_limits(cfg);
diff --git a/src/mainboard/starlabs/lite/devtree.c b/src/mainboard/starlabs/lite/devtree.c
index b453196788..7234cbd07f 100644
--- a/src/mainboard/starlabs/lite/devtree.c
+++ b/src/mainboard/starlabs/lite/devtree.c
@@ -12,7 +12,7 @@
 
 #include "soc/intel/apollolake/chip.h"
 
-void devtree_update(void)
+void mb_devtree_update(void)
 {
 	config_t *cfg = config_of_soc();
 
diff --git a/src/mainboard/starlabs/starbook/variants/adl/devtree.c b/src/mainboard/starlabs/starbook/variants/adl/devtree.c
index 8c51abe73c..c98504a60f 100644
--- a/src/mainboard/starlabs/starbook/variants/adl/devtree.c
+++ b/src/mainboard/starlabs/starbook/variants/adl/devtree.c
@@ -11,7 +11,7 @@
 #include <variants.h>
 #include <common/powercap.h>
 
-void devtree_update(void)
+void mb_devtree_update(void)
 {
 	config_t *cfg = config_of_soc();
 	update_power_limits(cfg);
diff --git a/src/mainboard/starlabs/starbook/variants/adl_n/devtree.c b/src/mainboard/starlabs/starbook/variants/adl_n/devtree.c
index 001965d1ea..11aa0f42f3 100644
--- a/src/mainboard/starlabs/starbook/variants/adl_n/devtree.c
+++ b/src/mainboard/starlabs/starbook/variants/adl_n/devtree.c
@@ -11,7 +11,7 @@
 #include <variants.h>
 #include <common/powercap.h>
 
-void devtree_update(void)
+void mb_devtree_update(void)
 {
 	config_t *cfg = config_of_soc();
 	update_power_limits(cfg);
diff --git a/src/mainboard/starlabs/starbook/variants/cml/devtree.c b/src/mainboard/starlabs/starbook/variants/cml/devtree.c
index 6ed8999261..c6ebe0a384 100644
--- a/src/mainboard/starlabs/starbook/variants/cml/devtree.c
+++ b/src/mainboard/starlabs/starbook/variants/cml/devtree.c
@@ -11,7 +11,7 @@
 #include <variants.h>
 #include <common/powercap.h>
 
-void devtree_update(void)
+void mb_devtree_update(void)
 {
 	config_t *cfg = config_of_soc();
 	update_power_limits(cfg);
diff --git a/src/mainboard/starlabs/starbook/variants/kbl/devtree.c b/src/mainboard/starlabs/starbook/variants/kbl/devtree.c
index 851a083fb0..a2c42c3d3b 100644
--- a/src/mainboard/starlabs/starbook/variants/kbl/devtree.c
+++ b/src/mainboard/starlabs/starbook/variants/kbl/devtree.c
@@ -11,7 +11,7 @@
 #include <variants.h>
 #include <common/powercap.h>
 
-void devtree_update(void)
+void mb_devtree_update(void)
 {
 	config_t *cfg = config_of_soc();
 	update_power_limits(cfg);
diff --git a/src/mainboard/starlabs/starbook/variants/mtl/devtree.c b/src/mainboard/starlabs/starbook/variants/mtl/devtree.c
index 0eedb7c599..ceeac0e33d 100644
--- a/src/mainboard/starlabs/starbook/variants/mtl/devtree.c
+++ b/src/mainboard/starlabs/starbook/variants/mtl/devtree.c
@@ -11,7 +11,7 @@
 #include <variants.h>
 #include <common/powercap.h>
 
-void devtree_update(void)
+void mb_devtree_update(void)
 {
 	config_t *cfg = config_of_soc();
 	update_power_limits(cfg);
diff --git a/src/mainboard/starlabs/starbook/variants/rpl/devtree.c b/src/mainboard/starlabs/starbook/variants/rpl/devtree.c
index 6fe7fcf812..e7ced59fdc 100644
--- a/src/mainboard/starlabs/starbook/variants/rpl/devtree.c
+++ b/src/mainboard/starlabs/starbook/variants/rpl/devtree.c
@@ -11,7 +11,7 @@
 #include <variants.h>
 #include <common/powercap.h>
 
-void devtree_update(void)
+void mb_devtree_update(void)
 {
 	config_t *cfg = config_of_soc();
 	update_power_limits(cfg);
diff --git a/src/mainboard/starlabs/starbook/variants/tgl/devtree.c b/src/mainboard/starlabs/starbook/variants/tgl/devtree.c
index ef23fb632e..3221a73a20 100644
--- a/src/mainboard/starlabs/starbook/variants/tgl/devtree.c
+++ b/src/mainboard/starlabs/starbook/variants/tgl/devtree.c
@@ -11,7 +11,7 @@
 #include <variants.h>
 #include <common/powercap.h>
 
-void devtree_update(void)
+void mb_devtree_update(void)
 {
 	config_t *cfg = config_of_soc();
 	update_power_limits(cfg);
diff --git a/src/mainboard/starlabs/starfighter/variants/mtl/devtree.c b/src/mainboard/starlabs/starfighter/variants/mtl/devtree.c
index fc41e37e7d..a7ed4a749f 100644
--- a/src/mainboard/starlabs/starfighter/variants/mtl/devtree.c
+++ b/src/mainboard/starlabs/starfighter/variants/mtl/devtree.c
@@ -11,7 +11,7 @@
 #include <variants.h>
 #include <common/powercap.h>
 
-void devtree_update(void)
+void mb_devtree_update(void)
 {
 	config_t *cfg = config_of_soc();
 	update_power_limits(cfg);
diff --git a/src/mainboard/starlabs/starfighter/variants/rpl/devtree.c b/src/mainboard/starlabs/starfighter/variants/rpl/devtree.c
index f2d497fa2f..7609e0c515 100644
--- a/src/mainboard/starlabs/starfighter/variants/rpl/devtree.c
+++ b/src/mainboard/starlabs/starfighter/variants/rpl/devtree.c
@@ -11,7 +11,7 @@
 #include <variants.h>
 #include <common/powercap.h>
 
-void devtree_update(void)
+void mb_devtree_update(void)
 {
 	config_t *cfg = config_of_soc();
 	update_power_limits(cfg);

From 89048780c0f87239ec0010f526484f95f06529da Mon Sep 17 00:00:00 2001
From: Yu-Ping Wu <yupingso@google.com>
Date: Wed, 4 Mar 2026 15:55:41 +0800
Subject: [PATCH 3634/3886] commonlib/list: Add list_move()

This function transfers all elements from one list head to another. The
The destination list head takes ownership of all nodes from the source
list head. The source list head is reinitialized to an empty list.

This is useful for efficiently moving list contents without element-wise
relinking, particularly in contexts like device tree overlay application
where node structures are incorporated from a temporary tree.

BUG=b:434080284
TEST=emerge-rauru coreboot libpayload
BRANCH=none

Change-Id: I143394e381fa72bcba692b7727f57dfc09fda70e
Signed-off-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91557
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jakub "Kuba" Czapiga <czapiga@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
---
 src/commonlib/include/commonlib/list.h | 11 ++++++
 src/commonlib/list.c                   | 25 +++++++++++-
 tests/commonlib/list-test.c            | 54 ++++++++++++++++++++++++++
 3 files changed, 89 insertions(+), 1 deletion(-)

diff --git a/src/commonlib/include/commonlib/list.h b/src/commonlib/include/commonlib/list.h
index a6c87ceee2..33875bc10b 100644
--- a/src/commonlib/include/commonlib/list.h
+++ b/src/commonlib/include/commonlib/list.h
@@ -72,6 +72,17 @@ static inline struct list_node *list_last(const struct list_node *head)
 // Get the number of list elements.
 size_t list_length(const struct list_node *head);
 
+/*
+ * Move all elements from list src_head to list dst_head.
+ *
+ * @param dst_head	Destination list to fill. This MUST be empty.
+ * @param src_head	Source list to be moved. This will be cleared after the call.
+ *
+ * After the call, the ownership of the src list elements passes to the dst list.
+ * Callers must NOT free the src list elements afterwards.
+ */
+void list_move(struct list_node *dst_head, struct list_node *src_head);
+
 /*
  * Explanation of `ptr` initialization:
  * 1. head.next != NULL: This means the list isn't empty. As the implementation ensures that
diff --git a/src/commonlib/list.c b/src/commonlib/list.c
index 93a9b12887..31c6a1d06d 100644
--- a/src/commonlib/list.c
+++ b/src/commonlib/list.c
@@ -7,11 +7,16 @@
 #define NEXT(ptr) ((ptr)->_internal_do_not_access.next)
 #define PREV(ptr) ((ptr)->_internal_do_not_access.prev)
 
+static inline void list_clear(struct list_node *head)
+{
+	PREV(head) = NEXT(head) = head;
+}
+
 void _list_init(struct list_node *head)
 {
 	if (!NEXT(head)) {
 		assert(!PREV(head));
-		PREV(head) = NEXT(head) = head;
+		list_clear(head);
 	}
 }
 
@@ -57,5 +62,23 @@ size_t list_length(const struct list_node *head)
 	return len;
 }
 
+void list_move(struct list_node *dst_head, struct list_node *src_head)
+{
+	assert(list_is_empty(dst_head));
+
+	if (list_is_empty(src_head))
+		return;
+
+	NEXT(dst_head) = NEXT(src_head);
+	PREV(dst_head) = PREV(src_head);
+
+	/* The elements formerly in src_head's list must now point back to dst_head. */
+	NEXT(PREV(dst_head)) = dst_head;
+	PREV(NEXT(dst_head)) = dst_head;
+
+	/* Clear src_head to be empty. */
+	list_clear(src_head);
+}
+
 #undef NEXT
 #undef PREV
diff --git a/tests/commonlib/list-test.c b/tests/commonlib/list-test.c
index e4dbd8e14a..0c0e59530b 100644
--- a/tests/commonlib/list-test.c
+++ b/tests/commonlib/list-test.c
@@ -176,6 +176,57 @@ static void test_list_append(void **state)
 	assert_int_equal(3, list_length(&head));
 }
 
+static void test_list_move(void **state)
+{
+	size_t idx;
+	struct test_container *node;
+	struct list_node src_head = {};
+	struct list_node dst_head = {};
+	struct test_container nodes[] = {
+		{1}, {2}, {3}
+	};
+
+	for (idx = 0; idx < ARRAY_SIZE(nodes); ++idx)
+		list_append(&nodes[idx].list_node, &src_head);
+
+	list_move(&dst_head, &src_head);
+
+	/* Check src_head is cleared. */
+	assert_true(list_is_empty(&src_head));
+
+	/* Check dst_head has all elements */
+	idx = 0;
+	list_for_each(node, dst_head, list_node) {
+		assert_true(idx < ARRAY_SIZE(nodes));
+		assert_ptr_equal(node, &nodes[idx]);
+		idx++;
+	}
+}
+
+static void test_list_move_empty(void **state)
+{
+	struct list_node src_head = {};
+	struct list_node dst_head = {};
+
+	/* Test moving an empty list. */
+	list_move(&dst_head, &src_head);
+
+	assert_true(list_is_empty(&src_head));
+	assert_true(list_is_empty(&dst_head));
+}
+
+static void test_list_move_invalid(void **state)
+{
+	struct list_node src_head = {};
+	struct list_node dst_head = {};
+	struct test_container c = { .value = 1 };
+
+	list_append(&c.list_node, &dst_head);
+
+	/* Test moving to a non-empty dst. */
+	expect_assert_failure(list_move(&dst_head, &src_head));
+}
+
 int main(void)
 {
 	const struct CMUnitTest tests[] = {
@@ -187,6 +238,9 @@ int main(void)
 		cmocka_unit_test(test_list_remove),
 		cmocka_unit_test(test_list_remove_head),
 		cmocka_unit_test(test_list_append),
+		cmocka_unit_test(test_list_move),
+		cmocka_unit_test(test_list_move_empty),
+		cmocka_unit_test(test_list_move_invalid),
 	};
 
 	return cb_run_group_tests(tests, NULL, NULL);

From 1e1b63c23b76ea21fa77b366812faaa247bfd1ad Mon Sep 17 00:00:00 2001
From: Yu-Ping Wu <yupingso@google.com>
Date: Wed, 4 Mar 2026 15:56:01 +0800
Subject: [PATCH 3635/3886] commonlib/device_tree: Utilize list_move() in
 dt_copy_subtree()

In dt_copy_subtree(), the device_tree_node copying

 *dst_node = *src_node;

doesn't work correctly for circular linked lists [1], because the 'next'
pointer of the last element isn't modified to point to the dst head.

As the only public caller of dt_copy_subtree() is dt_apply_overlay(),
and the dt_apply_overlay() function comment already explicitly disallows
'overlay' accesses after the call, fix the problem by utilizing
list_move() for copying device tree node properties and children.

Also add a new test case test_dt_apply_overlay.

[1] commit 23c41622a90f ("commonlib/list: Change to circular list")

BUG=b:434080284
TEST=emerge-rauru coreboot libpayload
BRANCH=none

Change-Id: I166ab74c9de67330d52f94e92b5d7ce5ddefa82b
Signed-off-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91558
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Jakub "Kuba" Czapiga <czapiga@google.com>
---
 src/commonlib/device_tree.c        |   5 +-
 tests/commonlib/Makefile.mk        |   2 +
 tests/commonlib/device_tree-test.c | 122 +++++++++++++++++++++++++++++
 3 files changed, 128 insertions(+), 1 deletion(-)

diff --git a/src/commonlib/device_tree.c b/src/commonlib/device_tree.c
index 7d5161db23..66a4dd1d53 100644
--- a/src/commonlib/device_tree.c
+++ b/src/commonlib/device_tree.c
@@ -2001,7 +2001,10 @@ static void dt_copy_subtree(struct device_tree_node *dst,
 
 		if (!dst_node) {
 			dst_node = alloc_node();
-			*dst_node = *src_node;
+			dst_node->name = src_node->name;
+			dst_node->phandle = src_node->phandle;
+			list_move(&dst_node->properties, &src_node->properties);
+			list_move(&dst_node->children, &src_node->children);
 			list_insert_after(&dst_node->list_node, &dst->children);
 		} else {
 			dt_copy_subtree(dst_node, src_node, upd);
diff --git a/tests/commonlib/Makefile.mk b/tests/commonlib/Makefile.mk
index e593b14404..4941aa3d5c 100644
--- a/tests/commonlib/Makefile.mk
+++ b/tests/commonlib/Makefile.mk
@@ -9,7 +9,9 @@ tests-y += device_tree-test
 
 device_tree-test-srcs += tests/commonlib/device_tree-test.c
 device_tree-test-srcs += tests/stubs/console.c
+device_tree-test-srcs += src/commonlib/bsd/string.c
 device_tree-test-srcs += src/commonlib/device_tree.c
+device_tree-test-srcs += src/commonlib/list.c
 device_tree-test-syssrcs += tests/helpers/file.c
 
 list-test-srcs += tests/commonlib/list-test.c
diff --git a/tests/commonlib/device_tree-test.c b/tests/commonlib/device_tree-test.c
index 0c1e2dd8f3..a47acf0c69 100644
--- a/tests/commonlib/device_tree-test.c
+++ b/tests/commonlib/device_tree-test.c
@@ -10,6 +10,21 @@
 #include <string.h>
 #include <tests/test.h>
 
+static struct device_tree *new_device_tree(void)
+{
+	struct device_tree *tree = xzalloc(sizeof(*tree));
+	tree->root = xzalloc(sizeof(*tree->root));
+	tree->root->name = "root";
+	return tree;
+}
+
+static void free_device_tree(struct device_tree *tree)
+{
+	assert_non_null(tree);
+	free(tree->root);
+	free(tree);
+}
+
 static int setup_device_tree_test_group(void **state)
 {
 	/*
@@ -117,6 +132,112 @@ static void test_fdt_read_reg_prop(void **state)
 	assert_int_equal(0x00010000, regions[0].size);
 }
 
+static void test_dt_apply_overlay(void **state)
+{
+	struct device_tree *base = new_device_tree();
+	struct device_tree *overlay = new_device_tree();
+	assert_non_null(base);
+	assert_non_null(overlay);
+
+	/* Add content to base tree BEFORE overlay */
+	struct device_tree_node *base_existing = dt_find_node_by_path(
+		base, "/preexisting", NULL, NULL, 1);
+	assert_non_null(base_existing);
+	dt_add_string_prop(base_existing, "base_prop", "base_val");
+
+	/*
+	 * Overlay:
+	 *
+	 * /fragment@0 {
+	 *   target-path = "/";
+	 *   __overlay__ {
+	 *     new_parent {
+	 *       parent_prop = "parent_val";
+	 *       new_child {
+	 *         child_prop = "child_val";
+	 *       };
+	 *     };
+	 *   };
+	 * };
+	 */
+	struct device_tree_node *frag = dt_find_node_by_path(
+		overlay, "/fragment@0", NULL, NULL, 1);
+	assert_non_null(frag);
+	dt_add_string_prop(frag, "target-path", "/");
+
+	/* Path to new_parent in overlay. */
+	static const char *const parent_path[] = {
+		"fragment@0",
+		"__overlay__",
+		"new_parent",
+		NULL,
+	};
+	struct device_tree_node *ovl_parent = dt_find_node(
+		overlay->root, parent_path, NULL, NULL, 1);
+	assert_non_null(ovl_parent);
+	dt_add_string_prop(ovl_parent, "parent_prop", "parent_val");
+
+	/* Path to new_child in overlay. */
+	static const char *const child_path[] = {
+		"fragment@0",
+		"__overlay__",
+		"new_parent",
+		"new_child",
+		NULL,
+	};
+	struct device_tree_node *ovl_child = dt_find_node(
+		overlay->root, child_path, NULL, NULL, 1);
+	assert_non_null(ovl_child);
+	dt_add_string_prop(ovl_child, "child_prop", "child_val");
+
+	int ret = dt_apply_overlay(base, overlay);
+	assert_int_equal(ret, 0);
+
+	/* Check base tree for the preexisting node. */
+	struct device_tree_node *check_preexisting = dt_find_node_by_path(
+		base, "/preexisting", NULL, NULL, 0);
+	assert_non_null(check_preexisting);
+	const char *preexisting_val = dt_find_string_prop(check_preexisting, "base_prop");
+	assert_string_equal(preexisting_val, "base_val");
+
+	/* Check base tree for the new structure. */
+	struct device_tree_node *new_parent = dt_find_node_by_path(
+		base, "/new_parent", NULL, NULL, 0);
+	assert_non_null(new_parent);
+	const char *parent_val = dt_find_string_prop(new_parent, "parent_prop");
+	assert_string_equal(parent_val, "parent_val");
+
+	struct device_tree_node *new_child = dt_find_node_by_path(
+		base, "/new_parent/new_child", NULL, NULL, 0);
+	assert_non_null(new_child);
+	const char *child_val = dt_find_string_prop(new_child, "child_prop");
+	assert_string_equal(child_val, "child_val");
+
+	/* Check that list_for_each works on the new nodes. */
+	struct device_tree_node *node;
+	int child_count = 0;
+	list_for_each(node, new_parent->children, list_node) {
+		child_count++;
+		assert_ptr_equal(node, new_child);
+	}
+	assert_int_equal(child_count, 1);
+
+	struct device_tree_property *prop_iter;
+	int parent_prop_count = 0;
+	list_for_each(prop_iter, new_parent->properties, list_node) {
+		parent_prop_count++;
+	}
+	assert_int_equal(parent_prop_count, 1);
+
+	int child_prop_count = 0;
+	list_for_each(prop_iter, new_child->properties, list_node) {
+		child_prop_count++;
+	}
+	assert_int_equal(child_prop_count, 1);
+
+	free_device_tree(base);
+}
+
 int main(void)
 {
 	const struct CMUnitTest tests[] = {
@@ -125,6 +246,7 @@ int main(void)
 		cmocka_unit_test(test_fdt_find_node_by_alias),
 		cmocka_unit_test(test_fdt_find_prop_in_node),
 		cmocka_unit_test(test_fdt_read_reg_prop),
+		cmocka_unit_test(test_dt_apply_overlay),
 	};
 
 	return cb_run_group_tests(tests, setup_device_tree_test_group,

From 1d8c536d7961bb0733b6635e635f39261554648a Mon Sep 17 00:00:00 2001
From: Swathi Tamilselvan <tswathi@qualcomm.corp-partner.google.com>
Date: Thu, 26 Feb 2026 10:06:07 +0530
Subject: [PATCH 3636/3886] soc/qualcomm/x1p42100: Add API to configure LPASS
 GPIO

Introduce a new API to handle configuration of LPASS GPIOs. The TLMM
GPIOs include an eGPIO enable bit that determines which subsystem
controls the GPIO. When set, the APPS processor controls the GPIO.
When cleared, the GPIO is controlled by the LPASS subsystem.

For GPIOs intended for LPASS, this API avoids enabling the eGPIO bit,
ensuring the GPIO remains controlled by the LPASS subsystem.

Test=Create an image.serial.bin and verify it boots successfully on
X1P42100.

Change-Id: Iccb51d3f5e6be4c1fadfdc7b9778805ae3e66af7
Signed-off-by: Swathi Tamilselvan <tswathi@qualcomm.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91560
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
---
 src/soc/qualcomm/common/gpio.c                    | 14 ++++++++++++++
 src/soc/qualcomm/common/include/soc/gpio_common.h |  2 ++
 2 files changed, 16 insertions(+)

diff --git a/src/soc/qualcomm/common/gpio.c b/src/soc/qualcomm/common/gpio.c
index 5053f3ba5f..575e7656e5 100644
--- a/src/soc/qualcomm/common/gpio.c
+++ b/src/soc/qualcomm/common/gpio.c
@@ -23,6 +23,20 @@ void gpio_configure(gpio_t gpio, uint32_t func, uint32_t pull,
 	write32(&regs->cfg, reg_val);
 }
 
+void gpio_configure_no_egpio(gpio_t gpio, uint32_t func, uint32_t pull,
+				uint32_t drive_str, uint32_t enable)
+{
+	struct tlmm_gpio *regs = (void *)(uintptr_t)gpio.addr;
+	uint32_t reg_val;
+
+	reg_val = ((enable & GPIO_BMSK) << GPIO_CFG_OE_SHFT) |
+		  ((drive_str & GPIO_CFG_DRV_BMSK) << GPIO_CFG_DRV_SHFT) |
+		  ((func & GPIO_CFG_FUNC_BMSK) << GPIO_CFG_FUNC_SHFT) |
+		  ((pull & GPIO_CFG_PULL_BMSK) << GPIO_CFG_PULL_SHFT);
+
+	write32(&regs->cfg, reg_val);
+}
+
 void gpio_set(gpio_t gpio, int value)
 {
 	struct tlmm_gpio *regs = (void *)(uintptr_t)gpio.addr;
diff --git a/src/soc/qualcomm/common/include/soc/gpio_common.h b/src/soc/qualcomm/common/include/soc/gpio_common.h
index 18cd040269..413422bc7f 100644
--- a/src/soc/qualcomm/common/include/soc/gpio_common.h
+++ b/src/soc/qualcomm/common/include/soc/gpio_common.h
@@ -99,6 +99,8 @@ struct tlmm_gpio {
 
 void gpio_configure(gpio_t gpio, uint32_t func, uint32_t pull,
 				uint32_t drive_str, uint32_t enable);
+void gpio_configure_no_egpio(gpio_t gpio, uint32_t func, uint32_t pull,
+				uint32_t drive_str, uint32_t enable);
 void gpio_input_irq(gpio_t gpio, enum gpio_irq_type type, uint32_t pull);
 int gpio_irq_status(gpio_t gpio);
 

From 6200d53e312392673bb478f45adc5ed08f1dc015 Mon Sep 17 00:00:00 2001
From: Swathi Tamilselvan <tswathi@qualcomm.corp-partner.google.com>
Date: Thu, 26 Feb 2026 10:41:15 +0530
Subject: [PATCH 3637/3886] mb/google/bluey: Use LPASS GPIO configure API for
 Soundwire GPIOs

Update the API used to configure Soundwire GPIOs to the LPASS GPIO
configure API, as these GPIOs are controlled by the LPASS subsystem.

Applies to the Soundwire amplifier GPIOs:
  - GPIO_SNDW_AMP_0_ENABLE (GPIO 204)
  - GPIO_SNDW_AMP_1_ENABLE (GPIO 205)
  - GPIO_SNDW_0_SCL (GPIO 202)
  - GPIO_SNDW_0_SDA (GPIO 203)

Test=1. Create an image.serial.bin and verify it boots successfully on
X1P42100.
2. Dump the corresponding TLMM GPIO CFG register and verify if the
eGPIO bit is disabled. The register details are part of HRD-X1P42100-S1
document.
https://docs.qualcomm.com/bundle/resource/topics/HRD-X1P42100-S1/

Change-Id: I9cc16b659fc5302ef81951ffbad8e62ce90e2890
Signed-off-by: Swathi Tamilselvan <tswathi@qualcomm.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91561
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
---
 src/mainboard/google/bluey/board.h     |  4 ++++
 src/mainboard/google/bluey/chromeos.c  |  3 ---
 src/mainboard/google/bluey/mainboard.c | 22 ++++++++++++++++++++++
 3 files changed, 26 insertions(+), 3 deletions(-)

diff --git a/src/mainboard/google/bluey/board.h b/src/mainboard/google/bluey/board.h
index 0544381e69..361aa6587c 100644
--- a/src/mainboard/google/bluey/board.h
+++ b/src/mainboard/google/bluey/board.h
@@ -28,6 +28,10 @@
 #endif
 
 /* Soundwire AMP GPIOs */
+#define GPIO_SNDW_0_SCL GPIO(202)
+#define GPIO_FUN_SNDW_0_SCL 4	/* 4=LPASS_10:WSA_SWR_CLK, Also try 1=ENTERPRISEMGMT_11 */
+#define GPIO_SNDW_0_SDA GPIO(203)
+#define GPIO_FUN_SNDW_0_SDA 3	/* 3=LPASS_11:WSA_SWR_DATA */
 #define GPIO_SNDW_AMP_0_ENABLE	GPIO(204)
 #define GPIO_SNDW_AMP_1_ENABLE	GPIO(205)
 
diff --git a/src/mainboard/google/bluey/chromeos.c b/src/mainboard/google/bluey/chromeos.c
index 0f2b7da21f..e8609d4c06 100644
--- a/src/mainboard/google/bluey/chromeos.c
+++ b/src/mainboard/google/bluey/chromeos.c
@@ -21,9 +21,6 @@ void setup_chromeos_gpios(void)
 			gpio_input_irq(GPIO_FPMCU_INT, IRQ_TYPE_LEVEL, GPIO_PULL_UP);
 		}
 	}
-
-	gpio_output(GPIO_SNDW_AMP_0_ENABLE, 0);
-	gpio_output(GPIO_SNDW_AMP_1_ENABLE, 0);
 }
 
 void fill_lb_gpios(struct lb_gpios *gpios)
diff --git a/src/mainboard/google/bluey/mainboard.c b/src/mainboard/google/bluey/mainboard.c
index ac80ceef80..3bc7557519 100644
--- a/src/mainboard/google/bluey/mainboard.c
+++ b/src/mainboard/google/bluey/mainboard.c
@@ -92,6 +92,25 @@ static void setup_usb_typec(void)
 	gpio_output(GPIO_USB_C1_RETIMER_RESET_L, 1);
 }
 
+static void setup_audio_gpios(void)
+{
+	gpio_configure_no_egpio(GPIO_SNDW_AMP_0_ENABLE, GPIO_FUNC_GPIO,
+				GPIO_NO_PULL, GPIO_2MA, GPIO_OUTPUT);
+	gpio_set(GPIO_SNDW_AMP_0_ENABLE, 0);
+	gpio_configure_no_egpio(GPIO_SNDW_AMP_1_ENABLE, GPIO_FUNC_GPIO,
+				GPIO_NO_PULL, GPIO_2MA, GPIO_OUTPUT);
+	gpio_set(GPIO_SNDW_AMP_1_ENABLE, 0);
+	gpio_configure_no_egpio(GPIO_SNDW_0_SCL, GPIO_FUN_SNDW_0_SCL,
+		GPIO_NO_PULL, GPIO_16MA, GPIO_OUTPUT);
+	gpio_configure_no_egpio(GPIO_SNDW_0_SDA, GPIO_FUN_SNDW_0_SDA,
+		GPIO_NO_PULL, GPIO_16MA, GPIO_OUTPUT);
+}
+
+static void setup_audio(void)
+{
+	setup_audio_gpios();
+}
+
 static void setup_usb(void)
 {
 	setup_usb_typec();
@@ -236,6 +255,9 @@ static void mainboard_init(struct device *dev)
 
 	/* Setup USB related initial config */
 	setup_usb();
+
+	/* Setup audio related initial config */
+	setup_audio();
 }
 
 static void mainboard_enable(struct device *dev)

From fd5f06244692fd536468a4e2d17817a1339ede13 Mon Sep 17 00:00:00 2001
From: Keith Hui <buurin@gmail.com>
Date: Mon, 16 Feb 2026 21:08:59 -0500
Subject: [PATCH 3638/3886] mb/asus/p8x7x-series/*tree.cb: Consolidate gen1_dec
 into baseboard

It sets the PCH generic I/O decode range #1, meant for hardware monitor
functionalities, which are same across all variants with no reason to
deviate from. Move it into baseboard devicetree.cb.

TEST=Timeless binaries remain identical for all variants.

Change-Id: I7eecb81c02ed8c4b9bceb4cf9aff92a2bbe54ad7
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91306
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/asus/p8x7x-series/devicetree.cb                   | 1 +
 src/mainboard/asus/p8x7x-series/variants/p8c_ws/overridetree.cb | 1 -
 .../asus/p8x7x-series/variants/p8h77-v/overridetree.cb          | 1 -
 .../asus/p8x7x-series/variants/p8z77-m/overridetree.cb          | 1 -
 .../asus/p8x7x-series/variants/p8z77-m_pro/overridetree.cb      | 1 -
 .../asus/p8x7x-series/variants/p8z77-v/overridetree.cb          | 1 -
 .../asus/p8x7x-series/variants/p8z77-v_le_plus/overridetree.cb  | 1 -
 .../asus/p8x7x-series/variants/p8z77-v_lx2/overridetree.cb      | 2 --
 8 files changed, 1 insertion(+), 8 deletions(-)

diff --git a/src/mainboard/asus/p8x7x-series/devicetree.cb b/src/mainboard/asus/p8x7x-series/devicetree.cb
index eb7a243ba0..edf1e6dc77 100644
--- a/src/mainboard/asus/p8x7x-series/devicetree.cb
+++ b/src/mainboard/asus/p8x7x-series/devicetree.cb
@@ -21,6 +21,7 @@ chip northbridge/intel/sandybridge
 			register "spi_uvscc" = "0x2005"
 			register "superspeed_capable_ports" = "0x0000000f"
 			register "xhci_switchable_ports"    = "0x0000000f"
+			register "gen1_dec" = "0x000c0291" # Hardware Monitor
 
 			device ref xhci on  end
 			device ref ehci2 on  end
diff --git a/src/mainboard/asus/p8x7x-series/variants/p8c_ws/overridetree.cb b/src/mainboard/asus/p8x7x-series/variants/p8c_ws/overridetree.cb
index c0d38b6dc9..a8e6029998 100644
--- a/src/mainboard/asus/p8x7x-series/variants/p8c_ws/overridetree.cb
+++ b/src/mainboard/asus/p8x7x-series/variants/p8c_ws/overridetree.cb
@@ -6,7 +6,6 @@ chip northbridge/intel/sandybridge
 		device ref peg60 on  end	# PCIEX16_3 (electrical x4)
 		subsystemid 0x1043 0x84ca inherit
 		chip southbridge/intel/bd82x6x
-			register "gen1_dec" = "0x000c0291"
 			register "usb_port_config" = "{
 				{ 1, 0, 0 },
 				{ 1, 0, 0 },
diff --git a/src/mainboard/asus/p8x7x-series/variants/p8h77-v/overridetree.cb b/src/mainboard/asus/p8x7x-series/variants/p8h77-v/overridetree.cb
index f1decba0ca..ba18f3cd45 100644
--- a/src/mainboard/asus/p8x7x-series/variants/p8h77-v/overridetree.cb
+++ b/src/mainboard/asus/p8x7x-series/variants/p8h77-v/overridetree.cb
@@ -20,7 +20,6 @@ chip northbridge/intel/sandybridge
 				{ 1, 0, 5 },
 				{ 1, 0, 6 }
 			}"
-			register "gen1_dec" = "0x000c0291"
 			device ref pcie_rp1 on  end	# PCIEX16_2 (electrical x4)
 			device ref pcie_rp5 on  end	# AR8161 GbE NIC
 			device ref pcie_rp6 on  end	# ASM1083 PCI Bridge
diff --git a/src/mainboard/asus/p8x7x-series/variants/p8z77-m/overridetree.cb b/src/mainboard/asus/p8x7x-series/variants/p8z77-m/overridetree.cb
index 058ce7644b..9fb5b6f766 100644
--- a/src/mainboard/asus/p8x7x-series/variants/p8z77-m/overridetree.cb
+++ b/src/mainboard/asus/p8x7x-series/variants/p8z77-m/overridetree.cb
@@ -5,7 +5,6 @@ chip northbridge/intel/sandybridge
 		subsystemid 0x1043 0x84ca inherit
 		device ref peg11 hidden end # These don't exist on this board
 		chip southbridge/intel/bd82x6x # Intel Series 7 Panther Point PCH
-			register "gen1_dec" = "0x000c0291"
 			register "usb_port_config" = "{
 				{1, 8, 0}, /* Port 0: USB3 front internal header, top */
 				{1, 8, 0}, /* Port 1: USB3 front internal header, bottom */
diff --git a/src/mainboard/asus/p8x7x-series/variants/p8z77-m_pro/overridetree.cb b/src/mainboard/asus/p8x7x-series/variants/p8z77-m_pro/overridetree.cb
index 5cbfaa2b02..0689696da2 100644
--- a/src/mainboard/asus/p8x7x-series/variants/p8z77-m_pro/overridetree.cb
+++ b/src/mainboard/asus/p8x7x-series/variants/p8z77-m_pro/overridetree.cb
@@ -4,7 +4,6 @@ chip northbridge/intel/sandybridge
 	device domain 0 on
 		subsystemid 0x1043 0x84ca inherit
 		chip southbridge/intel/bd82x6x
-			register "gen1_dec" = "0x000c0291"
 			register "gen4_dec" = "0x0000ff29"
 			register "pcie_port_coalesce" = "true"
 			register "usb_port_config" = "{
diff --git a/src/mainboard/asus/p8x7x-series/variants/p8z77-v/overridetree.cb b/src/mainboard/asus/p8x7x-series/variants/p8z77-v/overridetree.cb
index adbb10a3b6..320e719964 100644
--- a/src/mainboard/asus/p8x7x-series/variants/p8z77-v/overridetree.cb
+++ b/src/mainboard/asus/p8x7x-series/variants/p8z77-v/overridetree.cb
@@ -21,7 +21,6 @@ chip northbridge/intel/sandybridge
 				{ 1, 2, 5 },
 				{ 1, 2, 6 }
 			}"
-			register "gen1_dec" = "0x000c0291"
 
 			device ref gbe on  end
 			device ref pcie_rp1 on  end	# PCIEX_16_3 (electrical x1 or x4)
diff --git a/src/mainboard/asus/p8x7x-series/variants/p8z77-v_le_plus/overridetree.cb b/src/mainboard/asus/p8x7x-series/variants/p8z77-v_le_plus/overridetree.cb
index 66c8467935..31edc0baab 100644
--- a/src/mainboard/asus/p8x7x-series/variants/p8z77-v_le_plus/overridetree.cb
+++ b/src/mainboard/asus/p8x7x-series/variants/p8z77-v_le_plus/overridetree.cb
@@ -23,7 +23,6 @@ chip northbridge/intel/sandybridge
 				{ 1, 0xa53, 5 },
 				{ 1, 0xa53, 6 }
 			}"
-			register "gen1_dec" = "0x000c0291" # NCT6779 HWM
 			register "gen4_dec" = "0x0000ff29" # Could be for KB3722 EC
 
 			device ref pcie_rp1 on	# PCIEX_16_3 (electrical x2 or x4)
diff --git a/src/mainboard/asus/p8x7x-series/variants/p8z77-v_lx2/overridetree.cb b/src/mainboard/asus/p8x7x-series/variants/p8z77-v_lx2/overridetree.cb
index 4d8124a236..926d9d1c15 100644
--- a/src/mainboard/asus/p8x7x-series/variants/p8z77-v_lx2/overridetree.cb
+++ b/src/mainboard/asus/p8x7x-series/variants/p8z77-v_lx2/overridetree.cb
@@ -21,8 +21,6 @@ chip northbridge/intel/sandybridge
 				{ 1, 0, 6 }
 }"
 
-			register "gen1_dec" = "0x000c0291"
-
 			device ref pcie_rp1 on  end	# PCIEX16_2 (electrical x4)
 			device ref pcie_rp5 on  end	# RTL8111 GbE NIC
 			device ref pcie_rp6 on  end	# ASM1083 PCI Bridge

From 4caf5ab903341be66c48b865e3c9f5dc0edca96d Mon Sep 17 00:00:00 2001
From: Kapil Porwal <kapilporwal@google.com>
Date: Fri, 6 Mar 2026 14:56:31 +0530
Subject: [PATCH 3639/3886] soc/qualcomm/sc7280: Fix extended EDID read over
 I2C-over-AUX

The eDP AUX controller currently sets the NO_SEND_STOP flag for all
I2C-over-AUX transactions. This prevents the controller from issuing
an I2C STOP condition, which is required for proper completion of
multi-block (extended) EDID reads.

Update edp_msg_fifo_tx() to only set the EDP_AUX_TRANS_CTRL_NO_SEND_STOP
flag when the DP_AUX_I2C_MOT (Middle-of-Transaction) bit is set in the
request. This allows the I2C transaction to correctly finalize with a
STOP condition when MOT is not present, enabling successful reads of
EDID extension blocks.

BUG=none
TEST=Verify extended EDID is correctly read on Google/Quartz.

Change-Id: I4b637a750ef16148895332abfd9ca202b5a35408
Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91579
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/soc/qualcomm/sc7280/display/edp_aux.c | 10 +++++++---
 1 file changed, 7 insertions(+), 3 deletions(-)

diff --git a/src/soc/qualcomm/sc7280/display/edp_aux.c b/src/soc/qualcomm/sc7280/display/edp_aux.c
index 0f37c21b47..593f1731a4 100644
--- a/src/soc/qualcomm/sc7280/display/edp_aux.c
+++ b/src/soc/qualcomm/sc7280/display/edp_aux.c
@@ -88,9 +88,13 @@ static int edp_msg_fifo_tx(unsigned int address, u8 request, void *buffer, size_
 	write32(&edp_phy->aux_interrupt_clr, 0x0);
 
 	reg = 0; /* Transaction number is always 1 */
-	if (!native) /* i2c */
-		reg |= EDP_AUX_TRANS_CTRL_I2C | EDP_AUX_TRANS_CTRL_NO_SEND_ADDR |
-			EDP_AUX_TRANS_CTRL_NO_SEND_STOP;
+	if (!native) { /* i2c */
+		reg |= EDP_AUX_TRANS_CTRL_I2C | EDP_AUX_TRANS_CTRL_NO_SEND_ADDR;
+		/* EDP_AUX_TRANS_CTRL_NO_SEND_STOP should be set ONLY if DP_AUX_I2C_MOT is used. */
+		if (request & DP_AUX_I2C_MOT) {
+			reg |= EDP_AUX_TRANS_CTRL_NO_SEND_STOP;
+		}
+	}
 
 	reg |= EDP_AUX_TRANS_CTRL_GO;
 	write32(&edp_auxclk->aux_trans_ctrl, reg);

From 92a430baeed45dcb7442af5c979a08dca5a15356 Mon Sep 17 00:00:00 2001
From: Hualin Wei <weihualin@huaqin.corp-partner.google.com>
Date: Thu, 5 Mar 2026 16:32:49 +0800
Subject: [PATCH 3640/3886] mb/google/fatcat/var/lapis: Modify parameters to
 reduce acoustic noise

The acoustic noise test fail on lapis, based on power engineer's suggestion, modify the relevant parameters in overridetree.cb.

BUG=b:482855004
TEST=emerge-fatcat coreboot, test pass by power engineer

Change-Id: I5ab48ed56fc04d57dd5c02d5512891b17147d391
Signed-off-by: Hualin Wei <weihualin@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91562
Reviewed-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 .../fatcat/variants/lapis/overridetree.cb     | 37 +++++++++++--------
 1 file changed, 22 insertions(+), 15 deletions(-)

diff --git a/src/mainboard/google/fatcat/variants/lapis/overridetree.cb b/src/mainboard/google/fatcat/variants/lapis/overridetree.cb
index 6855616bb9..3353bf5c8d 100644
--- a/src/mainboard/google/fatcat/variants/lapis/overridetree.cb
+++ b/src/mainboard/google/fatcat/variants/lapis/overridetree.cb
@@ -64,21 +64,6 @@ chip soc/intel/pantherlake
 	register "pmc_gpe0_dw1" = "GPP_F"
 	register "pmc_gpe0_dw2" = "GPP_E"
 
-	register "power_limits_config[PTL_CORE_1]" = "{
-		.tdp_pl1_override = 15,
-		.tdp_pl2_override = 25,
-	}"
-
-	register "power_limits_config[PTL_CORE_3]" = "{
-		.tdp_pl1_override = 25,
-		.tdp_pl2_override = 25,
-	}"
-
-	register "power_limits_config[PTL_CORE_4]" = "{
-		.tdp_pl1_override = 25,
-		.tdp_pl2_override = 25,
-	}"
-
 	register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC_SKIP)" # USB2_C0
 	register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC_SKIP)" # USB2_C1
 	register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # LED
@@ -128,6 +113,28 @@ chip soc/intel/pantherlake
 		},
 	}"
 
+	# As per document 813278, the following PTL SoC supports Fast
+	# V-Mode (FVM) on cores (IA), Graphics (GT), and System Agent
+	# (SA). The ICC Limit is represented in 1/4 A increments,
+	# i.e., a value of 400 = 100A.
+	register "enable_fast_vmode[VR_DOMAIN_IA]" = "false"
+	register "cep_enable[VR_DOMAIN_IA]" = "false"
+	register "enable_fast_vmode[VR_DOMAIN_GT]" = "false"
+	register "cep_enable[VR_DOMAIN_GT]" = "false"
+	register "enable_fast_vmode[VR_DOMAIN_SA]" = "false"
+	register "cep_enable[VR_DOMAIN_SA]" = "false"
+
+	# Acoustic Noise settings and slew rate configuration:
+	register "enable_acoustic_noise_mitigation" = "true"
+	register "disable_fast_pkgc_ramp[VR_DOMAIN_IA]" = "false"
+	register "slow_slew_rate_config[VR_DOMAIN_IA]" = "SLEW_FAST_4"
+	register "disable_fast_pkgc_ramp[VR_DOMAIN_GT]" = "true"
+	register "slow_slew_rate_config[VR_DOMAIN_GT]" = "SLEW_FAST_8"
+	register "disable_fast_pkgc_ramp[VR_DOMAIN_SA]" = "false"
+	register "slow_slew_rate_config[VR_DOMAIN_SA]" = "SLEW_FAST_4"
+	register "pcore_hysteresis_window_ms" = "50"	#ms
+	register "ecore_hysteresis_window_ms" = "50"	#ms
+
 	device domain 0 on
 		subsystemid 0x1043 0x15e4 inherit
 		device ref dtt on

From ea58a467f119ef9e69e7cdb903fb65f1a1e334c8 Mon Sep 17 00:00:00 2001
From: Avi Uday <aviuday@google.com>
Date: Fri, 6 Mar 2026 10:34:10 +0530
Subject: [PATCH 3641/3886] Revert "soc/intel/pantherlake: Fill in SPD data on
 both channels of DDR5 memory"

This reverts commit 42210fdb2849ecdeca29de875201cf92eb2462d0, which was causing the
ocelot DDR5 RVP to not boot. Reverting until further debugging.

BUG=b:490040385

Change-Id: I5185a036ccbd6cca19eb1a3fd762686ed03919e8
Signed-off-by: Avi Uday <aviuday@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91576
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Pranava Y N <pranavayn@google.com>
---
 src/soc/intel/pantherlake/meminit.c | 31 ++++++++++++-----------------
 1 file changed, 13 insertions(+), 18 deletions(-)

diff --git a/src/soc/intel/pantherlake/meminit.c b/src/soc/intel/pantherlake/meminit.c
index 894ec30643..f9f8bac8da 100644
--- a/src/soc/intel/pantherlake/meminit.c
+++ b/src/soc/intel/pantherlake/meminit.c
@@ -70,8 +70,7 @@ static const struct soc_mem_cfg soc_mem_cfg[] = {
 	},
 };
 
-static void mem_init_spd_upds(FSP_M_CONFIG *mem_cfg, const struct mem_channel_data *data,
-				bool expand_channels)
+static void mem_init_spd_upds(FSP_M_CONFIG *mem_cfg, const struct mem_channel_data *data)
 {
 	uint64_t *spd_upds[MRC_CHANNELS][CONFIG_DIMMS_PER_CHANNEL] = {
 		[0] = { &mem_cfg->MemorySpdPtr000, &mem_cfg->MemorySpdPtr001, },
@@ -104,19 +103,7 @@ static void mem_init_spd_upds(FSP_M_CONFIG *mem_cfg, const struct mem_channel_da
 		for (dimm = 0; dimm < CONFIG_DIMMS_PER_CHANNEL; dimm++) {
 			uint64_t *spd_ptr = spd_upds[ch][dimm];
 
-			/*
-			 * In DDR5 systems, since each DIMM has 2 channels,
-			 * we need to copy the SPD data such that:
-			 * Channel 0 data is used by channel 0 and 1
-			 * Channel 2 data is used by channel 2 and 3
-			 * Channel 4 data is used by channel 4 and 5
-			 * Channel 6 data is used by channel 6 and 7
-			 */
-			if (expand_channels)
-				*spd_ptr = data->spd[ch & ~1][dimm];
-			else
-				*spd_ptr = data->spd[ch][dimm];
-
+			*spd_ptr = data->spd[ch][dimm];
 			if (*spd_ptr)
 				enable_channel = 1;
 		}
@@ -197,7 +184,6 @@ void memcfg_init(FSPM_UPD *memupd, const struct mb_cfg *mb_cfg,
 {
 	struct mem_channel_data data;
 	bool dq_dqs_auto_detect = false;
-	bool expand_channels = false;
 	FSP_M_CONFIG *mem_cfg = &memupd->FspmConfig;
 
 	mem_cfg->ECT = mb_cfg->ect;
@@ -209,7 +195,16 @@ void memcfg_init(FSPM_UPD *memupd, const struct mb_cfg *mb_cfg,
 		printk(BIOS_DEBUG, "%s: module type is DDR5\n", __func__);
 		meminit_ddr(mem_cfg, &mb_cfg->ddr_config);
 		dq_dqs_auto_detect = true;
-		expand_channels = true;
+		/*
+		 * TODO: Drop this workaround once SMBus driver in coreboot is
+		 * updated to support DDR5 EEPROM reading.
+		 */
+		if (spd_info->topo == MEM_TOPO_DIMM_MODULE) {
+			fill_dimm_module_info(mem_cfg, mb_cfg, spd_info);
+			mem_init_dq_upds(mem_cfg, NULL, mb_cfg, true);
+			mem_init_dqs_upds(mem_cfg, NULL, mb_cfg, true);
+			return;
+		}
 		break;
 	case MEM_TYPE_LP5X:
 		meminit_lp5x(mem_cfg, &mb_cfg->lp5x_config);
@@ -223,7 +218,7 @@ void memcfg_init(FSPM_UPD *memupd, const struct mb_cfg *mb_cfg,
 
 	mem_populate_channel_data(memupd, &soc_mem_cfg[mb_cfg->type], spd_info,
 				  half_populated, &data);
-	mem_init_spd_upds(mem_cfg, &data, expand_channels);
+	mem_init_spd_upds(mem_cfg, &data);
 	mem_init_dq_upds(mem_cfg, &data, mb_cfg, dq_dqs_auto_detect);
 	mem_init_dqs_upds(mem_cfg, &data, mb_cfg, dq_dqs_auto_detect);
 }

From 50ce94d7151c93490d2cc3dd6675561eee6ba374 Mon Sep 17 00:00:00 2001
From: Avi Uday <aviuday@google.com>
Date: Fri, 6 Mar 2026 10:43:00 +0530
Subject: [PATCH 3642/3886] Revert "soc/intel/pantherlake: Fix DDR5 channel
 mapping"

This reverts commit 835b63980d113232b74b92bc7d1349d3e37d8747, which was causing a boot failure on the ocelot DDR5 RVP. Reverting until further debugging.

BUG=b:490040385

Change-Id: I6fa397d26c57c5fb2dd415eaf8ebe5c20476b5f3
Signed-off-by: Avi Uday <aviuday@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91577
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Pranava Y N <pranavayn@google.com>
---
 src/soc/intel/pantherlake/meminit.c | 14 ++++++++------
 1 file changed, 8 insertions(+), 6 deletions(-)

diff --git a/src/soc/intel/pantherlake/meminit.c b/src/soc/intel/pantherlake/meminit.c
index f9f8bac8da..eef4adf5f0 100644
--- a/src/soc/intel/pantherlake/meminit.c
+++ b/src/soc/intel/pantherlake/meminit.c
@@ -35,16 +35,18 @@ static const struct soc_mem_cfg soc_mem_cfg[] = {
 		.num_phys_channels = DDR5_CHANNELS,
 		.phys_to_mrc_map = {
 			[0] = 0,
-			[1] = 4,
+			[1] = 1,
+			[2] = 4,
+			[3] = 5,
 		},
 		.md_phy_masks = {
 			/*
-			 * Only channel 0 is populated in case of half-populated
-			 * configuration.
+			 * Physical channels 0 and 1 are populated in case of
+			 * half-populated configurations.
 			 */
-			.half_channel = BIT(0),
-			/* In mixed topologies, either channel 0 or 1 can be memory-down. */
-			.mixed_topo = BIT(0) | BIT(1),
+			.half_channel = BIT(0) | BIT(1),
+			/* In mixed topology, channels 2 and 3 are always memory-down. */
+			.mixed_topo = BIT(2) | BIT(3),
 		},
 	},
 	[MEM_TYPE_LP5X] = {

From 1965a8740d14fcf4775daf61119ed374538b4f8c Mon Sep 17 00:00:00 2001
From: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Date: Wed, 4 Mar 2026 09:12:15 +0800
Subject: [PATCH 3643/3886] mb/google/brox/var/caboc: Set LGD touchscreen HID
 address to 0x01

Follow vendor design change.

BUG=b:483588481
TEST=build brox coreboot image

Change-Id: Idb8147974562fdbacd83fe2bd075c59585f77e21
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91537
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com>
---
 src/mainboard/google/brox/variants/caboc/overridetree.cb | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/mainboard/google/brox/variants/caboc/overridetree.cb b/src/mainboard/google/brox/variants/caboc/overridetree.cb
index cded4fd875..9fac6422c4 100644
--- a/src/mainboard/google/brox/variants/caboc/overridetree.cb
+++ b/src/mainboard/google/brox/variants/caboc/overridetree.cb
@@ -432,7 +432,7 @@ chip soc/intel/alderlake
 				register "generic.enable_delay_ms" = "1"
 				register "generic.has_power_resource" = "1"
 				register "generic.use_gpio_for_status" = "true"
-				register "hid_desc_reg_offset" = "0x00"
+				register "hid_desc_reg_offset" = "0x01"
 				device i2c 10 on
 					probe PANEL TOUCH_LGD_HID_I2C
 				end

From 1bdfc97c5413de9b7425de1ecab1b23d5e851d38 Mon Sep 17 00:00:00 2001
From: Jayvik Desai <jayvik@google.com>
Date: Fri, 6 Mar 2026 21:15:45 +0530
Subject: [PATCH 3644/3886] lib/cbfs: Enable LZ4 decompression in pre-RAM
 stages

LZ4 decompression was being incorrectly disabled in romstage when a
separate romstage was used and CONFIG_COMPRESS_RAMSTAGE_LZ4 was not
enabled. This occurred because ENV_RAMSTAGE_LOADER is defined as
ENV_SEPARATE_ROMSTAGE in such configurations, causing
cbfs_lz4_enabled() to hit the ramstage-loader check and return false.

This regression was introduced by commit f12d2997fcde ("lib/cbfs:
Don't include unused LZ4 code to shrink postcar stage"), which added
the ramstage-loader check to avoid including the LZ4 decompressor in
the postcar stage when it's not needed for the ramstage.

This patch adds an explicit check for ENV_ROMSTAGE_OR_BEFORE and
CONFIG_COMPRESS_PRERAM_STAGES to ensure LZ4 remains enabled in these
stages regardless of the ramstage compression settings.

BUG=none
TEST=Verified on Quartz

Change-Id: Icf5a2848ffe4c830bd462ab5dc7782afea3616e5
Signed-off-by: Jayvik Desai <jayvik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91581
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/lib/cbfs.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/lib/cbfs.c b/src/lib/cbfs.c
index 25a29a2885..07bd3f4a28 100644
--- a/src/lib/cbfs.c
+++ b/src/lib/cbfs.c
@@ -131,8 +131,8 @@ static inline bool cbfs_lz4_enabled(void)
 	if (fspm_env() && CONFIG(FSP_COMPRESS_FSP_M_LZ4))
 		return true;
 
-	if ((ENV_BOOTBLOCK || ENV_SEPARATE_VERSTAGE) && !CONFIG(COMPRESS_PRERAM_STAGES))
-		return false;
+	if (ENV_ROMSTAGE_OR_BEFORE && CONFIG(COMPRESS_PRERAM_STAGES))
+		return true;
 
 	if (ENV_SMM)
 		return false;

From d251282f2d418b58e67c37d7ea7caa41c29ac647 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Micha=C5=82=20=C5=BBygowski?= <michal.zygowski@3mdeb.com>
Date: Mon, 2 Mar 2026 15:02:39 +0100
Subject: [PATCH 3645/3886] Kconfig: move IOAPIC option to x86 Kconfig
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

IOAPIC is x86-exclusive, so move the IOAPIC options to arch/x86/Kconfig
file.

Change-Id: Ib0b30a1929f6f4f6bcc6355cce6ceea067905a2c
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91510
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/Kconfig          | 12 ------------
 src/arch/x86/Kconfig | 12 ++++++++++++
 2 files changed, 12 insertions(+), 12 deletions(-)

diff --git a/src/Kconfig b/src/Kconfig
index dfd703630c..93df67ed3d 100644
--- a/src/Kconfig
+++ b/src/Kconfig
@@ -933,18 +933,6 @@ config PCI_IO_CFG_EXT
 	bool
 	default n
 
-config IOAPIC
-	bool
-	default y if SMP
-	default n
-
-config IOAPIC_8BIT_ID
-	bool
-	default n
-	depends on IOAPIC
-	help
-	  Select this option if the hardware support 8bit long IOAPIC IDs.
-
 config USE_WATCHDOG_ON_BOOT
 	bool
 	default n
diff --git a/src/arch/x86/Kconfig b/src/arch/x86/Kconfig
index 8e6babceb3..7f10f9a20f 100644
--- a/src/arch/x86/Kconfig
+++ b/src/arch/x86/Kconfig
@@ -466,4 +466,16 @@ config SOC_BERT_SIZEOF_ERROR_SECTION
 	help
 	  SoC selects this if it implements soc_bert_sizeof_error_section.
 
+config IOAPIC
+	bool
+	default y if SMP
+	default n
+
+config IOAPIC_8BIT_ID
+	bool
+	default n
+	depends on IOAPIC
+	help
+	  Select this option if the hardware support 8bit long IOAPIC IDs.
+
 endif

From 026bac6de7154c5c529c260bfef462eb735b38f9 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Micha=C5=82=20=C5=BBygowski?= <michal.zygowski@3mdeb.com>
Date: Mon, 6 Oct 2025 10:52:32 +0200
Subject: [PATCH 3646/3886] arch/x86/ioapic: Add Kconfig option to keep
 pre-allocated IOAPIC ID
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Introduce IOAPIC_USE_PRESET_ID Kconfig option to instruct coreboot to
keep the IOAPIC ID programmed in the silicon initialization modules.
For example, OpenSIL already programs the IOAPIC IDs.

TEST=See IOAPIC IDs are starting with 240 on Gigabyte MZ33-AR1 as set
by OpenSIL.

Change-Id: Idb44c1aa663d7e351b011f4dd13f0b6b426566bb
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89477
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
---
 src/arch/x86/Kconfig  | 8 ++++++++
 src/arch/x86/ioapic.c | 6 ++++--
 2 files changed, 12 insertions(+), 2 deletions(-)

diff --git a/src/arch/x86/Kconfig b/src/arch/x86/Kconfig
index 7f10f9a20f..e7328b6375 100644
--- a/src/arch/x86/Kconfig
+++ b/src/arch/x86/Kconfig
@@ -478,4 +478,12 @@ config IOAPIC_8BIT_ID
 	help
 	  Select this option if the hardware support 8bit long IOAPIC IDs.
 
+config IOAPIC_USE_PRESET_ID
+	bool
+	default n
+	depends on IOAPIC
+	help
+	  Select this option if coreboot should keep IOAPIC IDs programmed
+	  by silicon vendor initialization code.
+
 endif
diff --git a/src/arch/x86/ioapic.c b/src/arch/x86/ioapic.c
index 792ba3e65e..b90ba94fcb 100644
--- a/src/arch/x86/ioapic.c
+++ b/src/arch/x86/ioapic.c
@@ -230,13 +230,15 @@ void setup_ioapic(uintptr_t ioapic_base, u8 ioapic_id)
 
 void register_new_ioapic_gsi0(uintptr_t ioapic_base)
 {
-	setup_ioapic(ioapic_base, 0);
+	setup_ioapic(ioapic_base, CONFIG(IOAPIC_USE_PRESET_ID) ?
+				  get_ioapic_id(ioapic_base) : 0);
 }
 
 void register_new_ioapic(uintptr_t ioapic_base)
 {
 	static u8 ioapic_id;
 	ioapic_id++;
-	set_ioapic_id(ioapic_base, ioapic_id);
+	set_ioapic_id(ioapic_base, CONFIG(IOAPIC_USE_PRESET_ID) ?
+				   get_ioapic_id(ioapic_base) : ioapic_id);
 	clear_vectors(ioapic_base, 0, ioapic_get_max_vectors(ioapic_base) - 1);
 }

From bf6b14e4f709650e9f95846192a597bf4424040b Mon Sep 17 00:00:00 2001
From: Sowmya Aralguppe <sowmya.aralguppe@intel.com>
Date: Fri, 27 Feb 2026 13:33:14 +0530
Subject: [PATCH 3647/3886] mb/google/ocelot: Add VR_DOMAIN_IA for
 fast_vmode_i_trip

Extend fast voltage mode configuration to IA Domain

Ref=830097_WCL_PDG_SchChk_Rev1p5
BUG=b:None
TEST=Build ocelot and verify that the system boots with following
VR parameter
[SPEW ]   IccMaxItrip[0] = 152

Change-Id: Iced5cea1bed8f215602ac1455ded214fa1f72c72
Signed-off-by: Sowmya Aralguppe <sowmya.aralguppe@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91450
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
---
 .../google/ocelot/variants/baseboard/ocelot/devicetree.cb  | 7 ++++---
 1 file changed, 4 insertions(+), 3 deletions(-)

diff --git a/src/mainboard/google/ocelot/variants/baseboard/ocelot/devicetree.cb b/src/mainboard/google/ocelot/variants/baseboard/ocelot/devicetree.cb
index 299c770d5e..016f531e38 100644
--- a/src/mainboard/google/ocelot/variants/baseboard/ocelot/devicetree.cb
+++ b/src/mainboard/google/ocelot/variants/baseboard/ocelot/devicetree.cb
@@ -67,13 +67,14 @@ chip soc/intel/pantherlake
 	# Enable Energy Reporting
 	register "pch_pm_energy_report_enable" = "true"
 
-	# Reference: 844458 MOW WW03
+	# Reference: 844458 MOW WW03, 8300097
 	# fast_vmode_i_trip values are derived from ICCMax with a safety margin.
-	# ITRIP_NOM is approximately 0.70 of ICCMax
-	# TODO: Update with actual i_trip values.
+	register "enable_fast_vmode[VR_DOMAIN_IA]" = "true"
+	register "cep_enable[VR_DOMAIN_IA]" = "true"
 	register "enable_fast_vmode[VR_DOMAIN_GT]" = "true"
 	register "cep_enable[VR_DOMAIN_GT]" = "true"
 	register "fast_vmode_i_trip[WCL_SKU_1]" = "{
+		[VR_DOMAIN_IA] = 38 * 4,
 		[VR_DOMAIN_GT] = 25 * 4,
 	}"
 

From eb5bdf06b92534b6f66f612297a4ccb69008b4ac Mon Sep 17 00:00:00 2001
From: Sowmya Aralguppe <sowmya.aralguppe@intel.com>
Date: Fri, 27 Feb 2026 14:40:04 +0530
Subject: [PATCH 3648/3886] soc/intel/pantherlake: Add power state thresholds
 for WCL

Configure power state thresholds (PS1, PS2, PS3) according to the
platform design specification. These thresholds define current limits
at which the voltage regulator domains transition between different
power states for optimal power management.

Ref=830097_WCL_PDG_SchChk_Rev1p5
BUG=b:None
TEST=Build ocelot and verify that the system boots with following
VR parameter
[SPEW ]  (MAILBOX) PS1Threshold         = 80 (1/4 Amp)
[SPEW ]  (MAILBOX) PS2Threshold         = 20 (1/4 Amp)
[SPEW ]  (MAILBOX) PS3Threshold         = 4 (1/4 Amp)

Change-Id: I8ecb55741901eb997d78a3f1fd09175c3ce31544
Signed-off-by: Sowmya Aralguppe <sowmya.aralguppe@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91454
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
---
 src/soc/intel/pantherlake/chipset_wcl.cb | 17 +++++++++++++++++
 1 file changed, 17 insertions(+)

diff --git a/src/soc/intel/pantherlake/chipset_wcl.cb b/src/soc/intel/pantherlake/chipset_wcl.cb
index ed32d4826d..808d9c7e51 100644
--- a/src/soc/intel/pantherlake/chipset_wcl.cb
+++ b/src/soc/intel/pantherlake/chipset_wcl.cb
@@ -14,6 +14,23 @@ chip soc/intel/pantherlake
 
 	register "tdc_mode[VR_DOMAIN_IA]" = "TDC_IRMS"
 	register "tdc_time_window_ms[VR_DOMAIN_IA]" = "28000"
+	# Set the power state thresholds according to document 830097
+	# Wildcat Lake Platform - Design Guide - Rev 1.5
+	register "ps1_threshold" = "{
+		[VR_DOMAIN_IA] = 20 * 4,
+		[VR_DOMAIN_GT] = 20 * 4,
+		[VR_DOMAIN_SA] = 20 * 4
+	}"
+	register "ps2_threshold" = "{
+		[VR_DOMAIN_IA] = 5 * 4,
+		[VR_DOMAIN_GT] = 5 * 4,
+		[VR_DOMAIN_SA] = 5 * 4
+	}"
+	register "ps3_threshold" = "{
+		[VR_DOMAIN_IA] = 1 * 4,
+		[VR_DOMAIN_GT] = 1 * 4,
+		[VR_DOMAIN_SA] = 1 * 4
+	}"
 
 	# Reduce the size of BasicMemoryTests to speed up the boot time.
 	register "lower_basic_mem_test_size" = "true"

From a1173d9bc1e39c9a32138dbd8a8cc62f349273d0 Mon Sep 17 00:00:00 2001
From: Subrata Banik <subratabanik@google.com>
Date: Sun, 8 Mar 2026 08:22:46 +0000
Subject: [PATCH 3649/3886] mb/google/bluey: Enable ChromeEC LED control for
 Quartz and Mica

Select EC_GOOGLE_CHROMEEC_LED_CONTROL for both BOARD_GOOGLE_MODEL_QUARTZ
and BOARD_GOOGLE_MODEL_MICA. This allows the firmware to communicate
with the EC to manage system LED states.

BUG=none
BRANCH=none
TEST=Build and boot on Bluey baseboard variants.

Change-Id: I53270c6a917c57ba8500f1fae46aac78ba43b351
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91596
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/google/bluey/Kconfig | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/src/mainboard/google/bluey/Kconfig b/src/mainboard/google/bluey/Kconfig
index d5ecf88a26..a223be1077 100644
--- a/src/mainboard/google/bluey/Kconfig
+++ b/src/mainboard/google/bluey/Kconfig
@@ -41,6 +41,7 @@ config BOARD_GOOGLE_MODEL_QUARTZ
 	select BOARD_GOOGLE_BASEBOARD_BLUEY
 	select BOARD_ROMSIZE_KB_32768
 	select EC_GOOGLE_CHROMEEC_BATTERY_SOC_DYNAMIC
+	select EC_GOOGLE_CHROMEEC_LED_CONTROL
 	select MAINBOARD_HAS_CHROME_EC
 	select MAINBOARD_HAS_FINGERPRINT_VIA_SPI
 	select MAINBOARD_HAS_GOOGLE_TPM
@@ -65,6 +66,7 @@ config BOARD_GOOGLE_MODEL_MICA
 	def_bool n
 	select BOARD_GOOGLE_BASEBOARD_BLUEY
 	select BOARD_ROMSIZE_KB_32768
+	select EC_GOOGLE_CHROMEEC_LED_CONTROL
 	select EC_GOOGLE_CHROMEEC_BATTERY_SOC_DYNAMIC
 	select MAINBOARD_HAS_CHROME_EC
 	select MAINBOARD_HAS_FINGERPRINT_VIA_USB

From ddac3082eaf1cdb4f48822489c17dd4ec6d1c983 Mon Sep 17 00:00:00 2001
From: Subrata Banik <subratabanik@google.com>
Date: Sun, 8 Mar 2026 08:23:57 +0000
Subject: [PATCH 3650/3886] mb/google/fatcat: Enable ChromeOS EC LED control
 for variants

Select EC_GOOGLE_CHROMEEC_LED_CONTROL for the following Fatcat
variants:
- Lapis
- Moonstone
- Ruby

This enables the firmware to drive system LED behavior via the
ChromeOS EC.

BUG=none
BRANCH=none
TEST=Build and boot on fatcat variants, verify LED functionality.

Change-Id: I506420c8594f5cd183cdd02c8516c053205423e3
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91597
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Avi Uday <aviuday@google.com>
Reviewed-by: Jayvik Desai <jayvik@google.com>
---
 src/mainboard/google/fatcat/Kconfig | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/src/mainboard/google/fatcat/Kconfig b/src/mainboard/google/fatcat/Kconfig
index 8f9029b2fc..2b5779bbfc 100644
--- a/src/mainboard/google/fatcat/Kconfig
+++ b/src/mainboard/google/fatcat/Kconfig
@@ -140,6 +140,7 @@ config BOARD_GOOGLE_LAPIS
 	select DRIVERS_SOUNDWIRE_CS42L43
 	select EC_GOOGLE_CHROMEEC_FW_CONFIG_FROM_UFSC
 	select EC_GOOGLE_CHROMEEC_RTK
+	select EC_GOOGLE_CHROMEEC_LED_CONTROL
 	select EC_GOOGLE_CHROMEEC_LPC_GENERIC_MEMORY_RANGE
 	select HAVE_SLP_S0_GATE
 	select MAINBOARD_HAS_GOOGLE_STRAUSS_KEYBOARD
@@ -149,6 +150,7 @@ config BOARD_GOOGLE_MOONSTONE
 	select BOARD_GOOGLE_BASEBOARD_FATCAT
 	select DRIVERS_SOUNDWIRE_ALC1320
 	select EC_GOOGLE_CHROMEEC_FW_CONFIG_FROM_UFSC
+	select EC_GOOGLE_CHROMEEC_LED_CONTROL
 	select FSP_UGOP_EARLY_SIGN_OF_LIFE
 	select HAVE_SLP_S0_GATE
 	select MAINBOARD_HAS_GOOGLE_STRAUSS_KEYBOARD
@@ -158,6 +160,7 @@ config BOARD_GOOGLE_MODEL_RUBY
 	select BOARD_GOOGLE_BASEBOARD_FATCAT
 	select DRIVERS_I2C_TAS2563
 	select EC_GOOGLE_CHROMEEC_FW_CONFIG_FROM_UFSC
+	select EC_GOOGLE_CHROMEEC_LED_CONTROL
 	select FSP_UGOP_EARLY_SIGN_OF_LIFE
 	select HAVE_SLP_S0_GATE
 	select MAINBOARD_HAS_GOOGLE_STRAUSS_KEYBOARD

From b7ca29ba92873deae2c21614214c763909dc3a32 Mon Sep 17 00:00:00 2001
From: Subrata Banik <subratabanik@google.com>
Date: Sun, 8 Mar 2026 09:02:16 +0000
Subject: [PATCH 3651/3886] mb/google/bluey: Power off if charger applet fails
 to enable charging

When the charger applet times out waiting for charging to enable, the
previous behavior was to simply return. This caused a boot hang because
the system would attempt to continue mainboard initialization without
properly initialized IPs or sufficient power.

Update the timeout handler to trigger a system power-off via
google_chromeec_ap_poweroff(). This ensures the device enters a clean
G3 state if charging cannot be established, preventing a partial-boot
hang and unnecessary power drain.

BUG=none
BRANCH=none
TEST=Verified on Bluey that a charging timeout results in a clean
power-off instead of a system hang.

Change-Id: Iae00e6df39e9d78cd5d27770b871ff2e8c4c9b7c
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91598
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
---
 src/mainboard/google/bluey/charging.c | 9 ++++++++-
 1 file changed, 8 insertions(+), 1 deletion(-)

diff --git a/src/mainboard/google/bluey/charging.c b/src/mainboard/google/bluey/charging.c
index f81d5b9650..f6f1c9f376 100644
--- a/src/mainboard/google/bluey/charging.c
+++ b/src/mainboard/google/bluey/charging.c
@@ -101,7 +101,14 @@ void launch_charger_applet(void)
 		if (stopwatch_expired(&sw)) {
 			printk(BIOS_WARNING, "Charging not enabled %ld ms. Abort.\n",
 					charging_enable_timeout_ms);
-			return;
+			/*
+			 * If firmware-based charging fails to enable within the timeout,
+			 * do not simply return, as this leaves IPs uninitialized and
+			 * causes a boot hang. Instead, issue a shutdown if not charging.
+			 */
+			printk(BIOS_INFO, "Issuing power-off.\n");
+			google_chromeec_offmode_heartbeat();
+			google_chromeec_ap_poweroff();
 		}
 		mdelay(200);
 	}

From 0449fb45a690adc303abb899059441cabae88dcf Mon Sep 17 00:00:00 2001
From: Subrata Banik <subratabanik@google.com>
Date: Sun, 8 Mar 2026 09:06:57 +0000
Subject: [PATCH 3652/3886] mb/google/bluey: Refactor and secure low-power
 charging boot path

Refactor the low-power/off-mode charging logic into a dedicated
helper function `handle_low_power_charging_boot`.

Additionally, replace the `return` statement with `halt()` after
the charging applet logic. This ensures that if the system is in
a low-power charging state, it cannot accidentally proceed with
the rest of the mainboard initialization, which could lead to
unstable behavior or power-sequencing issues.

Included <halt.h> to provide the necessary definition.

BUG=none
BRANCH=none
TEST=Build and boot on google/quartz. Verify that low-battery boot
correctly enters the charging applet and does not proceed to full init.

Change-Id: I4bf9bb0f89d117fea9b81a5f8369fa23043a1e82
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91599
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
---
 src/mainboard/google/bluey/mainboard.c | 38 +++++++++++++++++---------
 1 file changed, 25 insertions(+), 13 deletions(-)

diff --git a/src/mainboard/google/bluey/mainboard.c b/src/mainboard/google/bluey/mainboard.c
index 3bc7557519..12e180af54 100644
--- a/src/mainboard/google/bluey/mainboard.c
+++ b/src/mainboard/google/bluey/mainboard.c
@@ -13,6 +13,7 @@
 #include <device/i2c_simple.h>
 #include <ec/google/chromeec/ec.h>
 #include <gpio.h>
+#include <halt.h>
 #include <soc/clock.h>
 #include <soc/pcie.h>
 #include <soc/qupv3_config_common.h>
@@ -177,6 +178,28 @@ static void trigger_critical_battery_shutdown(void)
 	google_chromeec_ap_poweroff();
 }
 
+/*
+ * Handle charging and UI states for low-power or off-mode boot scenarios.
+ * This function handles the transitions needed when the device is powered
+ * solely to show a charging status rather than a full OS boot.
+ */
+static void handle_low_power_charging_boot(void)
+{
+	/* TODO: enable fast charging */
+	enable_slow_battery_charging();
+
+	/*
+	 * Disable the lightbar for Low-Battery or Off-Mode charging sequences.
+	 * This maintains visual consistency between the built-in display
+	 * indicators and the external lightbar.
+	 */
+	if (CONFIG(EC_GOOGLE_CHROMEEC_LED_CONTROL))
+		google_chromeec_lightbar_off();
+
+	/* Boot to charging applet; if this fails, the applet should trigger a reset */
+	launch_charger_applet();
+}
+
 static void mainboard_init(struct device *dev)
 {
 	configure_parallel_charging();
@@ -198,19 +221,8 @@ static void mainboard_init(struct device *dev)
 
 	/* Skip mainboard initialization if boot mode is "low-battery" or "off-mode charging" */
 	if (is_low_power_boot_with_charger()) {
-		/* TODO: enable fast charging */
-		enable_slow_battery_charging();
-
-		/* Disable the lightbar for Low-Battery or Off-Mode charging sequences.
-		 * This maintains visual consistency between the built-in display
-		 * indicators and the external lightbar.
-		 */
-		if (CONFIG(EC_GOOGLE_CHROMEEC_LED_CONTROL))
-			google_chromeec_lightbar_off();
-
-		/* Boot to charging applet */
-		launch_charger_applet();
-		return;
+		handle_low_power_charging_boot();
+		halt();
 	}
 
 	gpi_firmware_load(QUP_0_GSI_BASE);

From ee3aef1c72e91901d75fbc7afac7cdf36b191fe9 Mon Sep 17 00:00:00 2001
From: Subrata Banik <subratabanik@google.com>
Date: Sun, 8 Mar 2026 12:29:21 +0000
Subject: [PATCH 3653/3886] mb/google/bluey: Add AC unplug detection and
 charging status indication

Implement logic to detect and clear ChromeOS EC AC-unplug events and
provide visual feedback via the LEDs before system shutdown.

Key changes:
- Added `detect_ac_unplug_event` and `clear_ac_unplug_event` to
  monitor power source changes via EC host events.
- Implemented `indicate_charging_status` to provide a 4-second
  notification to the user before the AP powers off.
- Integrated these helpers into `launch_charger_applet` to ensure
  the event state is clean upon entry and the user is notified
  before the system issues a power-off due to charging timeouts or
  state changes.

BUG=none
BRANCH=none
TEST=On Bluey, verify the LED turns on for 4 seconds when
charging fails or AC is removed during the charging applet
before the device powers off.

Change-Id: Ie1ff5ba6f158fe7302e523f984c5e5d5f05d6eae
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91602
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
---
 src/mainboard/google/bluey/charging.c | 42 +++++++++++++++++++++++++++
 1 file changed, 42 insertions(+)

diff --git a/src/mainboard/google/bluey/charging.c b/src/mainboard/google/bluey/charging.c
index f6f1c9f376..c99bf020a1 100644
--- a/src/mainboard/google/bluey/charging.c
+++ b/src/mainboard/google/bluey/charging.c
@@ -43,6 +43,7 @@
 
 #define DELAY_CHARGING_APPLET_MS 2000 /* 2sec */
 #define CHARGING_RAIL_STABILIZATION_DELAY_MS 3000 /* 3sec */
+#define DELAY_CHARGING_ACTIVE_LB_MS 4000 /* 4sec */
 
 enum charging_status {
 	CHRG_DISABLE,
@@ -83,6 +84,41 @@ static int detect_ec_manual_poweron_event(void)
 	return 0;
 }
 
+static void clear_ac_unplug_event(void)
+{
+	const uint64_t ac_unplug_event =
+		EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_DISCONNECTED);
+	google_chromeec_clear_events_b(ac_unplug_event);
+}
+
+static int detect_ac_unplug_event(void)
+{
+	const uint64_t ac_unplug_event_mask =
+		EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_DISCONNECTED);
+	uint64_t events = google_chromeec_get_events_b();
+
+	if (!!(events & ac_unplug_event_mask))
+		return 1;
+
+	return 0;
+}
+
+/*
+ * Provides visual feedback via the LEDs and clears the AC unplug
+ * event to acknowledge the transition into a charging state.
+ */
+static void indicate_charging_status(void)
+{
+	/* Turn on LEDs to alert user of power state change */
+	if (CONFIG(EC_GOOGLE_CHROMEEC_LED_CONTROL)) {
+		google_chromeec_lightbar_on();
+		mdelay(DELAY_CHARGING_ACTIVE_LB_MS);
+	}
+
+	/* Clear the event to prevent re-triggering in the next iteration */
+	clear_ac_unplug_event();
+}
+
 void launch_charger_applet(void)
 {
 	if (!CONFIG(EC_GOOGLE_CHROMEEC))
@@ -93,6 +129,8 @@ void launch_charger_applet(void)
 
 	printk(BIOS_INFO, "Inside %s. Initiating charging\n", __func__);
 
+	/* Reset AC-unplug detection state and lightbar status before entering loop */
+	clear_ac_unplug_event();
 	/* clear any pending power button press and lid open event */
 	clear_ec_manual_poweron_event();
 
@@ -107,6 +145,8 @@ void launch_charger_applet(void)
 			 * causes a boot hang. Instead, issue a shutdown if not charging.
 			 */
 			printk(BIOS_INFO, "Issuing power-off.\n");
+			if (detect_ac_unplug_event())
+				indicate_charging_status();
 			google_chromeec_offmode_heartbeat();
 			google_chromeec_ap_poweroff();
 		}
@@ -123,6 +163,8 @@ void launch_charger_applet(void)
 		 */
 		if (!get_battery_icurr_ma()) {
 			printk(BIOS_INFO, "Issuing power-off due to change in charging state.\n");
+			if (detect_ac_unplug_event())
+				indicate_charging_status();
 			google_chromeec_offmode_heartbeat();
 			google_chromeec_ap_poweroff();
 		}

From bf5aa04d8bb086860f66efd7339ed2083f1a40d9 Mon Sep 17 00:00:00 2001
From: Kapil Porwal <kapilporwal@google.com>
Date: Wed, 28 Jan 2026 15:15:35 +0530
Subject: [PATCH 3654/3886] soc/qc/common: Configure framebuffer as uncacheable

Configure the framebuffer as uncacheable so that all write
operations bypass the cache and update memory instantly.

BUG=b:427387842
TEST=Verify firmware splash screen on Google/Quartz.

Change-Id: I47188eb51c4b1f90ff7a611e5712947e73180add
Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90969
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
---
 src/soc/qualcomm/common/mmu.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/src/soc/qualcomm/common/mmu.c b/src/soc/qualcomm/common/mmu.c
index 480b7a9fea..c3f89a24c1 100644
--- a/src/soc/qualcomm/common/mmu.c
+++ b/src/soc/qualcomm/common/mmu.c
@@ -79,4 +79,7 @@ void qc_mmu_dram_config_post_dram_init(size_t ddr_size)
 
 	if (REGION_SIZE(dram_aop_cmd_db) != 0)
 		mmu_config_range((void *)_dram_aop_cmd_db, REGION_SIZE(dram_aop_cmd_db), UNCACHED_RAM);
+
+	if (REGION_SIZE(framebuffer))
+		mmu_config_range((void *)_framebuffer, REGION_SIZE(framebuffer), UNCACHED_RAM);
 }

From 0be9f20be45d3e8ed2ceab9a1382d9eac2fea66c Mon Sep 17 00:00:00 2001
From: Sowmya Aralguppe <sowmya.aralguppe@intel.com>
Date: Fri, 27 Feb 2026 14:18:53 +0530
Subject: [PATCH 3655/3886] soc/intel/pantherlake: Add icc_max settings for WCL
 SKU
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Add icc maximum configuration to include all voltage regulator domains
for WCL_SKU_1

Ref=830097_WCL_PDG_SchChk_Rev1p5
BUG=b:None
TEST=Build ocelot and verify that the system boots with following
VR parameter
[SPEW ]  (MAILBOX) IccMax    = 200 (1/4 A)
[SPEW ]   Override IccMax[1] = 144
[SPEW ]  (MAILBOX) IccMax    = 144 (1/4 A)
[SPEW ]   Override IccMax[2] = 140
[SPEW ]  (MAILBOX) IccMax    = 140 (1/4 A)
[SPEW ]   Override IccMax[3] = 112
[SPEW ]  (MAILBOX) IccMax    = 112 (1/4 A)

Change-Id: Ic1a17834a3164c7d0747d1aa0cde01de637535a3
Signed-off-by: Sowmya Aralguppe <sowmya.aralguppe@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91453
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Pranava Y N <pranavayn@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/soc/intel/pantherlake/chipset_wcl.cb | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/src/soc/intel/pantherlake/chipset_wcl.cb b/src/soc/intel/pantherlake/chipset_wcl.cb
index 808d9c7e51..6b4e0f780f 100644
--- a/src/soc/intel/pantherlake/chipset_wcl.cb
+++ b/src/soc/intel/pantherlake/chipset_wcl.cb
@@ -9,7 +9,10 @@ chip soc/intel/pantherlake
 	}"
 
 	register "icc_max[WCL_SKU_1]" = "{
+		[VR_DOMAIN_IA] = 50 * 4,
 		[VR_DOMAIN_GT] = 36 * 4,
+		[VR_DOMAIN_SA] = 35 * 4,
+		[VR_DOMAIN_ATOM] = 28 * 4
 	}"
 
 	register "tdc_mode[VR_DOMAIN_IA]" = "TDC_IRMS"

From 4734da172bcd68dfdb7dfff379bbc397e0e97497 Mon Sep 17 00:00:00 2001
From: Venkateshwar S <vens@qualcomm.corp-partner.google.com>
Date: Tue, 17 Feb 2026 23:04:48 -0800
Subject: [PATCH 3656/3886] memlayout: Introduce PRERAM and POSTRAM TTB regions
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Refactor the TTB memory region definition to support stage-specific
usage. Certain boot modes require separate TTB regions for early stages
(such as bootblock or romstage) and for later ramstage usage. On Bluey,
the off-mode/low-battery charging path requires this separation because
the boot IMEM, where the early-stage TTB resides, becomes unavailable
once the ADSP comes out of reset.

This change ensures that the correct TTB region is selected for each
stage and prevents early‑stage memory constraints from impacting the
ramstage boot flow.

BUG=b:436391478
TEST=Able to build and boot google/bluey.

Change-Id: I8cedab8c744220599527de1c303a777f9ff8b1da
Signed-off-by: Venkateshwar S <vens@qualcomm.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91361
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
---
 src/arch/arm64/include/arch/memlayout.h | 18 ++++++++++++++++++
 src/include/symbols.h                   |  2 ++
 2 files changed, 20 insertions(+)

diff --git a/src/arch/arm64/include/arch/memlayout.h b/src/arch/arm64/include/arch/memlayout.h
index d84e7714fc..5c938517be 100644
--- a/src/arch/arm64/include/arch/memlayout.h
+++ b/src/arch/arm64/include/arch/memlayout.h
@@ -9,6 +9,24 @@
 	REGION(ttb, addr, size, 4K) \
 	_ = ASSERT(size % 4K == 0, "TTB size must be divisible by 4K!");
 
+#if ENV_ROMSTAGE_OR_BEFORE
+	#define PRERAM_TTB(addr, size) \
+		REGION(preram_ttb, addr, size, 4K) \
+		_ = ASSERT(size % 4K == 0, "preram_ttb size must be divisible by 4K!"); \
+		ALIAS_REGION(preram_ttb, ttb)
+	#define POSTRAM_TTB(addr, size) \
+		REGION(postram_ttb, addr, size, 4K) \
+		_ = ASSERT(size >= _preram_ttb_size, "The postram_ttb size cannot be smaller than the preram_ttb size.");
+#else
+	#define PRERAM_TTB(addr, size) \
+		REGION(preram_ttb, addr, size, 4K)
+	#define POSTRAM_TTB(addr, size) \
+		REGION(postram_ttb, addr, size, 4K) \
+		_ = ASSERT(size % 4K == 0, "postram_ttb size must be divisible by 4K!"); \
+		_ = ASSERT(size >= _preram_ttb_size, "The postram_ttb size cannot be smaller than the preram_ttb size."); \
+		ALIAS_REGION(postram_ttb, ttb)
+#endif
+
 #define FRAMEBUFFER(addr, size) \
 	REGION(framebuffer, addr, size, 1M) \
 	_ = ASSERT(size % 1M == 0, \
diff --git a/src/include/symbols.h b/src/include/symbols.h
index 53dbfb94a3..b9bde838fc 100644
--- a/src/include/symbols.h
+++ b/src/include/symbols.h
@@ -74,6 +74,8 @@ DECLARE_REGION(ramstage)
 
 DECLARE_REGION(pagetables)
 DECLARE_REGION(ttb)
+DECLARE_OPTIONAL_REGION(preram_ttb)
+DECLARE_OPTIONAL_REGION(postram_ttb)
 DECLARE_OPTIONAL_REGION(ttb_subtables)
 DECLARE_OPTIONAL_REGION(preram_dma_coherent)
 DECLARE_OPTIONAL_REGION(postram_dma_coherent)

From 35dbfac13ae0b06848fbe07685211648b8f81eb8 Mon Sep 17 00:00:00 2001
From: Kenneth Chan <kenneth.chan@quanta.corp-partner.google.com>
Date: Tue, 10 Mar 2026 16:03:14 +0800
Subject: [PATCH 3657/3886] mb/google/rex/var/karis: Add H58G56CK8BX146 to RAM
 ID table

Add the new memory support: Hynix H58G56CK8BX146

BUG=b:442335706
TEST=Run part_id_gen tool and check the generated files.

Change-Id: Icd2643f8f5d4e7d7860ab20fa6964762e7c13713
Signed-off-by: Kenneth Chan <kenneth.chan@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91636
Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
---
 src/mainboard/google/rex/variants/karis/memory/Makefile.mk      | 2 +-
 .../google/rex/variants/karis/memory/dram_id.generated.txt      | 1 +
 .../google/rex/variants/karis/memory/mem_parts_used.txt         | 1 +
 3 files changed, 3 insertions(+), 1 deletion(-)

diff --git a/src/mainboard/google/rex/variants/karis/memory/Makefile.mk b/src/mainboard/google/rex/variants/karis/memory/Makefile.mk
index 45f30a7e89..eba4ccde8d 100644
--- a/src/mainboard/google/rex/variants/karis/memory/Makefile.mk
+++ b/src/mainboard/google/rex/variants/karis/memory/Makefile.mk
@@ -4,7 +4,7 @@
 # util/spd_tools/bin/part_id_gen MTL lp5 src/mainboard/google/rex/variants/karis/memory src/mainboard/google/rex/variants/karis/memory/mem_parts_used.txt
 
 SPD_SOURCES =
-SPD_SOURCES += spd/lp5/set-0/spd-11.hex      # ID = 0(0b0000)  Parts = MT62F1G32D2DS-023 WT:B, H58G56BK8BX068, K3KL8L80EM-MGCU
+SPD_SOURCES += spd/lp5/set-0/spd-11.hex      # ID = 0(0b0000)  Parts = MT62F1G32D2DS-023 WT:B, H58G56BK8BX068, K3KL8L80EM-MGCU, H58G56CK8BX146
 SPD_SOURCES += spd/lp5/set-0/spd-1.hex      # ID = 1(0b0001)  Parts = H9JCNNNBK3MLYR-N6E, MT62F512M32D2DR-031 WT:B
 SPD_SOURCES += spd/lp5/set-0/spd-7.hex      # ID = 2(0b0010)  Parts = K3KL8L80CM-MGCT
 SPD_SOURCES += spd/lp5/set-0/spd-10.hex      # ID = 3(0b0011)  Parts = H58G66CK8BX147
diff --git a/src/mainboard/google/rex/variants/karis/memory/dram_id.generated.txt b/src/mainboard/google/rex/variants/karis/memory/dram_id.generated.txt
index d7b77d7c83..d5845751b2 100644
--- a/src/mainboard/google/rex/variants/karis/memory/dram_id.generated.txt
+++ b/src/mainboard/google/rex/variants/karis/memory/dram_id.generated.txt
@@ -11,3 +11,4 @@ K3KL8L80CM-MGCT                2 (0010)
 MT62F512M32D2DR-031 WT:B       1 (0001)
 H58G66CK8BX147                 3 (0011)
 K3KL8L80EM-MGCU                0 (0000)
+H58G56CK8BX146                 0 (0000)
diff --git a/src/mainboard/google/rex/variants/karis/memory/mem_parts_used.txt b/src/mainboard/google/rex/variants/karis/memory/mem_parts_used.txt
index e839b0975c..8762cdb999 100644
--- a/src/mainboard/google/rex/variants/karis/memory/mem_parts_used.txt
+++ b/src/mainboard/google/rex/variants/karis/memory/mem_parts_used.txt
@@ -16,3 +16,4 @@ K3KL8L80CM-MGCT
 MT62F512M32D2DR-031 WT:B
 H58G66CK8BX147
 K3KL8L80EM-MGCU
+H58G56CK8BX146

From 40abf7946c4defe0b917e5e211af68debbfda1d0 Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Mon, 9 Mar 2026 13:49:58 +0000
Subject: [PATCH 3658/3886] mb/starlabs/adl/hz: Add missing cnvi_bt_core
 parameter

`register "cnvi_bt_core"` was missed in the upstream patch, so re-add
it.

Change-Id: I2be5303563f22a642c03719a16b1c88cd8d196a7
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91613
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
---
 src/mainboard/starlabs/adl/variants/hz/devicetree.cb | 1 +
 1 file changed, 1 insertion(+)

diff --git a/src/mainboard/starlabs/adl/variants/hz/devicetree.cb b/src/mainboard/starlabs/adl/variants/hz/devicetree.cb
index c06ad29b9a..5fe89a5dbe 100644
--- a/src/mainboard/starlabs/adl/variants/hz/devicetree.cb
+++ b/src/mainboard/starlabs/adl/variants/hz/devicetree.cb
@@ -1,5 +1,6 @@
 chip soc/intel/alderlake
 	# FSP UPDs
+	register "cnvi_bt_core"			= "true"
 	register "eist_enable"			= "true"
 	register "enable_c6dram"		= "true"
 	register "energy_efficient_turbo"	= "true"

From baae037f25625c71b1a71e617a16e4e958ca260d Mon Sep 17 00:00:00 2001
From: KangMin Wang <kangmin.wang@luxshare.corp-partner.google.com>
Date: Mon, 9 Mar 2026 19:10:22 +0800
Subject: [PATCH 3659/3886] mb/google/bluey/mica: Add PS8820 re-timer
 configuration

Add Kconfig options to support PS8820 re-timer for the mica variant.

BUG=b:491021369
TEST=emerge-bluey coreboot

Change-Id: I7cb0d452da077ceaded18641477512c96188e270
Signed-off-by: KangMin Wang <kangmin.wang@luxshare.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91607
Reviewed-by: Derek Huang <derekhuang@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
---
 src/mainboard/google/bluey/Kconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/src/mainboard/google/bluey/Kconfig b/src/mainboard/google/bluey/Kconfig
index a223be1077..9fe281bca9 100644
--- a/src/mainboard/google/bluey/Kconfig
+++ b/src/mainboard/google/bluey/Kconfig
@@ -74,6 +74,7 @@ config BOARD_GOOGLE_MODEL_MICA
 
 config BOARD_GOOGLE_MICA
 	select BOARD_GOOGLE_MODEL_MICA
+	select MAINBOARD_HAS_PS8820_RETIMER
 	select SOC_QUALCOMM_HAMOA
 
 if BOARD_GOOGLE_BLUEY_COMMON

From fc312590d1750ffd5a136ef1e484e7efd85d3622 Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Wed, 21 Jan 2026 22:08:37 +0000
Subject: [PATCH 3660/3886] drivers/efi: Derive ESRT version from LOCALVERSION
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

fwupd shows the ESRT (UEFI System Resource Table) version as 0 when
DRIVERS_EFI_MAIN_FW_VERSION is left at the default. That makes it easy
to ship firmware with no meaningful ESRT version and forces maintainers
to duplicate versioning in multiple places.

If DRIVERS_EFI_MAIN_FW_VERSION is 0, parse a leading "<major>.<minor>"
from LOCALVERSION (ignoring non-digits before/after) and encode it as
(major << 16) | minor (e.g. "v26.01-rc1" -> 0x001A0001).

If DRIVERS_EFI_MAIN_FW_LSV is 0, default it to the effective firmware
version. This provides a sane, more secure default (prevents accidental
rollback to older versions) while still allowing platforms to override
LSV explicitly when rollback is desired.

Test=boot adl/horizon and check `fwupdmgr get-devices` shows a
version:
    ├─System Firmware:
    │     Device ID:          f48f261c7fc0724729b817bfd4e8340e3195a6bc
    │     Current version:    26.3


Change-Id: I3f47ee7a38e79312532f4ed5d4516c57911f727e
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90861
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/drivers/efi/Kconfig | 11 +++++++++
 src/drivers/efi/info.c  | 50 +++++++++++++++++++++++++++++++++++++++--
 2 files changed, 59 insertions(+), 2 deletions(-)

diff --git a/src/drivers/efi/Kconfig b/src/drivers/efi/Kconfig
index 9f63938a3a..9effc0d778 100644
--- a/src/drivers/efi/Kconfig
+++ b/src/drivers/efi/Kconfig
@@ -29,6 +29,15 @@ config DRIVERS_EFI_MAIN_FW_VERSION
 	help
 	  32-bit unsigned integer representing current firmware's version.
 
+	  If set to 0, coreboot will try to derive a version from LOCALVERSION by
+	  parsing a leading "<major>.<minor>" and encoding it as
+	  (major << 16) | minor.
+
+	  Non-digits before and after "<major>.<minor>" are ignored.
+	  Examples:
+	  - "26.01" -> 0x001A0001
+	  - "v26.01-rc1" -> 0x001A0001
+
 config DRIVERS_EFI_MAIN_FW_LSV
 	hex "Lowest supported firmware version"
 	range 0x00000000 0xFFFFFFFF
@@ -39,6 +48,8 @@ config DRIVERS_EFI_MAIN_FW_LSV
 	  that is allowed to replace the current one.  Can be used to forbid
 	  bugged versions.
 
+	  If set to 0, coreboot uses DRIVERS_EFI_MAIN_FW_VERSION.
+
 config DRIVERS_EFI_UPDATE_CAPSULES
 	bool "Include EFI update capsules driver"
 	depends on DRIVERS_EFI_VARIABLE_STORE && SMMSTORE_V2 && DRIVERS_EFI_FW_INFO
diff --git a/src/drivers/efi/info.c b/src/drivers/efi/info.c
index fc1cfea573..ca4dd42a1f 100644
--- a/src/drivers/efi/info.c
+++ b/src/drivers/efi/info.c
@@ -6,10 +6,42 @@
 #include <string.h>
 #include <uuid.h>
 
+static uint32_t efi_fw_version_from_localversion(void)
+{
+	const char *localversion = CONFIG_LOCALVERSION;
+	uint32_t major = 0;
+	uint32_t minor = 0;
+	const char *p = localversion;
+
+	while (*p != '\0' && (*p < '0' || *p > '9'))
+		p++;
+
+	while (*p >= '0' && *p <= '9') {
+		major = major * 10 + (*p - '0');
+		p++;
+	}
+
+	if (*p != '.')
+		return 0;
+	p++;
+
+	while (*p >= '0' && *p <= '9') {
+		minor = minor * 10 + (*p - '0');
+		p++;
+	}
+
+	if (major > 0xffff || minor > 0xffff)
+		return 0;
+
+	return (major << 16) | minor;
+}
+
 void lb_efi_fw_info(struct lb_header *header)
 {
 	uint8_t guid[16];
 	struct lb_efi_fw_info *fw_info;
+	uint32_t fw_version;
+	uint32_t lsv;
 
 	if (parse_uuid(guid, CONFIG_DRIVERS_EFI_MAIN_FW_GUID)) {
 		printk(BIOS_ERR, "%s(): failed to parse firmware's GUID: '%s'\n", __func__,
@@ -22,7 +54,21 @@ void lb_efi_fw_info(struct lb_header *header)
 	fw_info->size = sizeof(*fw_info);
 
 	memcpy(fw_info->guid, guid, sizeof(guid));
-	fw_info->version = CONFIG_DRIVERS_EFI_MAIN_FW_VERSION;
-	fw_info->lowest_supported_version = CONFIG_DRIVERS_EFI_MAIN_FW_LSV;
+
+	fw_version = CONFIG_DRIVERS_EFI_MAIN_FW_VERSION;
+	if (fw_version == 0) {
+		fw_version = efi_fw_version_from_localversion();
+		if (fw_version != 0)
+			printk(BIOS_DEBUG,
+			       "EFI FW version derived from CONFIG_LOCALVERSION '%s': 0x%08x\n",
+			       CONFIG_LOCALVERSION, fw_version);
+	}
+
+	lsv = CONFIG_DRIVERS_EFI_MAIN_FW_LSV;
+	if (lsv == 0)
+		lsv = fw_version;
+
+	fw_info->version = fw_version;
+	fw_info->lowest_supported_version = lsv;
 	fw_info->fw_size = CONFIG_ROM_SIZE;
 }

From bbbc655b152b6900b8a9c308d32bdfcdb710a0d2 Mon Sep 17 00:00:00 2001
From: Kapil Porwal <kapilporwal@google.com>
Date: Tue, 10 Mar 2026 21:19:37 +0530
Subject: [PATCH 3661/3886] Revert "mb/google/bluey: Configure GPIOs for USB
 camera"

This reverts commit d912ae91b0a8174a93d7701ae1c620df6fd45029.

Reason for revert: These GPIOs will be managed by the OS.
BUG=b:481123667

Change-Id: Ieab7a9eba09c6a1128fe4709603f3b9d64e72e93
Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91639
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
---
 src/mainboard/google/bluey/board.h     | 4 ----
 src/mainboard/google/bluey/mainboard.c | 8 --------
 2 files changed, 12 deletions(-)

diff --git a/src/mainboard/google/bluey/board.h b/src/mainboard/google/bluey/board.h
index 361aa6587c..65436b60d7 100644
--- a/src/mainboard/google/bluey/board.h
+++ b/src/mainboard/google/bluey/board.h
@@ -47,10 +47,6 @@
 #define GPIO_SD_CD_L		GPIO(71)
 #endif
 
-/* USB Camera specific GPIOs */
-#define GPIO_USB_CAM_RESET_L	GPIO(10)
-#define GPIO_USB_CAM_ENABLE	GPIO(206)
-
 /* USB-C1 port specific GPIOs */
 #define GPIO_USB_C1_EN_PP3300		GPIO(186)
 #define GPIO_USB_C1_EN_PP1800		GPIO(175)
diff --git a/src/mainboard/google/bluey/mainboard.c b/src/mainboard/google/bluey/mainboard.c
index 12e180af54..b9c055e6d5 100644
--- a/src/mainboard/google/bluey/mainboard.c
+++ b/src/mainboard/google/bluey/mainboard.c
@@ -76,12 +76,6 @@ static bool is_low_power_boot_with_charger(void)
 	return ret;
 }
 
-static void enable_usb_camera(void)
-{
-	gpio_output(GPIO_USB_CAM_RESET_L, 1);
-	gpio_output(GPIO_USB_CAM_ENABLE, 1);
-}
-
 static void setup_usb_typec(void)
 {
 	gpio_output(GPIO_USB_C1_EN_PP3300, 1);
@@ -115,8 +109,6 @@ static void setup_audio(void)
 static void setup_usb(void)
 {
 	setup_usb_typec();
-
-	enable_usb_camera();
 }
 
 static void setup_usb_late(void *unused)

From a402a87405794f01e01c1c9a78e12fbd41368e4b Mon Sep 17 00:00:00 2001
From: Keith Hui <buurin@gmail.com>
Date: Fri, 6 Mar 2026 00:15:06 -0500
Subject: [PATCH 3662/3886] mb/asus/p8z77-v_le_plus/cmos.layout: Extend
 checksummed area

Three more recent nvram options were not covered by checksum.

Change-Id: I69dcd3f0b57464e284965e31153e2ee0a1a80631
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91578
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
---
 .../asus/p8x7x-series/variants/p8z77-v_le_plus/cmos.layout      | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/mainboard/asus/p8x7x-series/variants/p8z77-v_le_plus/cmos.layout b/src/mainboard/asus/p8x7x-series/variants/p8z77-v_le_plus/cmos.layout
index 86cbffd918..26354b17fa 100644
--- a/src/mainboard/asus/p8x7x-series/variants/p8z77-v_le_plus/cmos.layout
+++ b/src/mainboard/asus/p8x7x-series/variants/p8z77-v_le_plus/cmos.layout
@@ -98,4 +98,4 @@ enumerations
 # -----------------------------------------------------------------
 checksums
 
-checksum 392 423 984
+checksum 392 431 984

From df470521a7629f27ffe08365dee60fe10e14bade Mon Sep 17 00:00:00 2001
From: Keith Hui <buurin@gmail.com>
Date: Fri, 12 Apr 2024 22:17:28 -0400
Subject: [PATCH 3663/3886] mb/asus/p8x7x-series: Enable single PS/2 port role
 control

Add HAVE_SHARED_PS2_PORT Kconfig, associated cmos.[layout,default]
and CFR entries to p8z77-m[_pro], p8z77-v[_le_plus], p8h77-v,
where their owners manual indicate a single shared PS/2 port, to enable
control of this one port's role. Adds an "auto" option if PS/2 keyboard
init is enabled in Kconfig, to enable switching role automatically if
a device (ie. mouse) is detected on auxiliary channel.

TEST=Logitech M-S48 PS/2 mouse and various PS/2 keyboards all work with
correctly set port role and "auto" on asus/p8z77-m under a Linux
Mint 22.2 live environment.

Change-Id: I21b73da99168e751b1a23485d4b1695963f9eef5
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81885
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
---
 src/mainboard/asus/p8x7x-series/Kconfig        |  4 ++++
 src/mainboard/asus/p8x7x-series/cfr.c          | 18 ++++++++++++++++++
 .../p8x7x-series/variants/p8h77-v/cmos.default |  1 +
 .../p8x7x-series/variants/p8h77-v/cmos.layout  |  7 +++++++
 .../p8x7x-series/variants/p8z77-m/cmos.default |  1 +
 .../p8x7x-series/variants/p8z77-m/cmos.layout  |  6 ++++++
 .../variants/p8z77-m_pro/cmos.default          |  1 +
 .../variants/p8z77-m_pro/cmos.layout           |  7 +++++++
 .../p8x7x-series/variants/p8z77-v/cmos.default |  1 +
 .../p8x7x-series/variants/p8z77-v/cmos.layout  |  9 ++++++++-
 .../variants/p8z77-v_le_plus/cmos.default      |  1 +
 .../variants/p8z77-v_le_plus/cmos.layout       |  6 ++++++
 12 files changed, 61 insertions(+), 1 deletion(-)

diff --git a/src/mainboard/asus/p8x7x-series/Kconfig b/src/mainboard/asus/p8x7x-series/Kconfig
index ee4ee3eeb2..68b8d92486 100644
--- a/src/mainboard/asus/p8x7x-series/Kconfig
+++ b/src/mainboard/asus/p8x7x-series/Kconfig
@@ -26,6 +26,7 @@ config BOARD_ASUS_P8H77_V
 	select SUPERIO_NUVOTON_NCT6779D
 	select USE_NATIVE_RAMINIT
 	select POWER_LED_USES_GPIO8
+	select HAVE_SHARED_PS2_PORT
 
 config BOARD_ASUS_P8Z77_M_PRO
 	select BOARD_ASUS_P8X7X_SERIES
@@ -34,6 +35,7 @@ config BOARD_ASUS_P8Z77_M_PRO
 	select MEMORY_MAPPED_TPM
 	select SUPERIO_NUVOTON_NCT6779D
 	select SUPERIO_NUVOTON_COMMON_COM_A
+	select HAVE_SHARED_PS2_PORT
 
 config BOARD_ASUS_P8Z77_V_LX2
 	select BOARD_ASUS_P8X7X_SERIES
@@ -51,6 +53,7 @@ config BOARD_ASUS_P8Z77_V
 	select MAINBOARD_USES_IFD_GBE_REGION
 	select SUPERIO_NUVOTON_NCT6779D
 	select USE_NATIVE_RAMINIT
+	select HAVE_SHARED_PS2_PORT
 
 config BOARD_ASUS_P8Z77_M
 	select BOARD_ASUS_P8X7X_SERIES
@@ -58,6 +61,7 @@ config BOARD_ASUS_P8Z77_M
 	select MEMORY_MAPPED_TPM
 	select SUPERIO_NUVOTON_NCT6779D
 	select SUPERIO_NUVOTON_COMMON_COM_A
+	select HAVE_SHARED_PS2_PORT
 
 config BOARD_ASUS_P8Z77_V_LE_PLUS
 	select BOARD_ASUS_P8X7X_SERIES
diff --git a/src/mainboard/asus/p8x7x-series/cfr.c b/src/mainboard/asus/p8x7x-series/cfr.c
index bba60a6610..4412a1eb23 100644
--- a/src/mainboard/asus/p8x7x-series/cfr.c
+++ b/src/mainboard/asus/p8x7x-series/cfr.c
@@ -5,6 +5,7 @@
 #include <console/cfr.h>
 #include <northbridge/intel/sandybridge/cfr.h>
 #include <southbridge/intel/bd82x6x/cfr.h>
+#include <superio/nuvoton/common/nuvoton.h>
 
 #if CONFIG(USE_NATIVE_RAMINIT)
 static struct sm_obj_form sysagent = {
@@ -74,6 +75,20 @@ static const struct sm_object spdif_dest = SM_DECLARE_ENUM({
 				SM_ENUM_VALUE_END	},
 });
 #endif
+#if CONFIG(HAVE_SHARED_PS2_PORT)
+static const struct sm_object ps2_port_role = SM_DECLARE_ENUM({
+	.opt_name	= "ps2_port_role",
+	.ui_name	= "PS/2 Port Role",
+	.default_value	= 0,
+	.values		= (const struct sm_enum_value[]) {
+				{ "Keyboard",	PS2_PORT_ROLE_KEYBOARD },
+				{ "Mouse",	PS2_PORT_ROLE_MOUSE },
+#if CONFIG(DRIVERS_PS2_KEYBOARD)
+				{ "Auto",	PS2_PORT_ROLE_AUTO },
+#endif
+				SM_ENUM_VALUE_END },
+});
+#endif
 
 static struct sm_obj_form onboard_devices = {
 	.ui_name = "Onboard Devices Configuration",
@@ -82,6 +97,9 @@ static struct sm_obj_form onboard_devices = {
 		&audio_panel_type,
 #if CONFIG(BOARD_ASUS_P8Z77_V_LE_PLUS)
 		&spdif_dest,
+#endif
+#if CONFIG(HAVE_SHARED_PS2_PORT)
+		&ps2_port_role,
 #endif
 		NULL
 	},
diff --git a/src/mainboard/asus/p8x7x-series/variants/p8h77-v/cmos.default b/src/mainboard/asus/p8x7x-series/variants/p8h77-v/cmos.default
index 4501aa4904..8e4aeaf4d6 100644
--- a/src/mainboard/asus/p8x7x-series/variants/p8h77-v/cmos.default
+++ b/src/mainboard/asus/p8x7x-series/variants/p8h77-v/cmos.default
@@ -6,3 +6,4 @@ nmi=Disable
 power_on_after_fail=Disable
 sata_mode=AHCI
 gfx_uma_size=64M
+ps2_port_role=Keyboard
diff --git a/src/mainboard/asus/p8x7x-series/variants/p8h77-v/cmos.layout b/src/mainboard/asus/p8x7x-series/variants/p8h77-v/cmos.layout
index 58e2f1f6a6..b72dbead0a 100644
--- a/src/mainboard/asus/p8x7x-series/variants/p8h77-v/cmos.layout
+++ b/src/mainboard/asus/p8x7x-series/variants/p8h77-v/cmos.layout
@@ -24,6 +24,8 @@ entries
 # coreboot config options: northbridge
 416	5	e	6	gfx_uma_size
 
+426	2	e	7	ps2_port_role
+
 # coreboot config options: check sums
 984	16	h	0	check_sum
 
@@ -79,6 +81,11 @@ enumerations
 6	14	480M
 6	15	512M
 
+# ps2_port_role
+7	0	Keyboard
+7	1	Mouse
+7	2	Auto
+
 # -----------------------------------------------------------------
 checksums
 
diff --git a/src/mainboard/asus/p8x7x-series/variants/p8z77-m/cmos.default b/src/mainboard/asus/p8x7x-series/variants/p8z77-m/cmos.default
index 79ea560466..439d67d4a9 100644
--- a/src/mainboard/asus/p8x7x-series/variants/p8z77-m/cmos.default
+++ b/src/mainboard/asus/p8x7x-series/variants/p8z77-m/cmos.default
@@ -10,3 +10,4 @@ usb3_mode=Enable
 usb3_drv=Enable
 usb3_streams=Enable
 audio_panel_type=HDA
+ps2_port_role=Keyboard
diff --git a/src/mainboard/asus/p8x7x-series/variants/p8z77-m/cmos.layout b/src/mainboard/asus/p8x7x-series/variants/p8z77-m/cmos.layout
index ca77a82cec..7f3e537208 100644
--- a/src/mainboard/asus/p8x7x-series/variants/p8z77-m/cmos.layout
+++ b/src/mainboard/asus/p8x7x-series/variants/p8z77-m/cmos.layout
@@ -55,6 +55,7 @@ entries
 # HD Audio or AC'97
 #
 425          1       e       9        audio_panel_type
+426          2       e       10       ps2_port_role
 
 # -----------------------------------------------------------------
 # Sandy/Ivy Bridge MRC Scrambler Seed values
@@ -119,6 +120,11 @@ enumerations
 7     14    480M
 7     15    512M
 
+# ps2_port_role
+10	0	Keyboard
+10	1	Mouse
+10	2	Auto
+
 # usb3_mode
 # Disable = Use the port always as USB 2.0 for compatibility
 # Enable = Use the port always as USB 3.0 for speed
diff --git a/src/mainboard/asus/p8x7x-series/variants/p8z77-m_pro/cmos.default b/src/mainboard/asus/p8x7x-series/variants/p8z77-m_pro/cmos.default
index 6811b0b076..83ceed0a31 100644
--- a/src/mainboard/asus/p8x7x-series/variants/p8z77-m_pro/cmos.default
+++ b/src/mainboard/asus/p8x7x-series/variants/p8z77-m_pro/cmos.default
@@ -9,3 +9,4 @@ sata_mode=AHCI
 usb3_mode=Enable
 usb3_drv=Enable
 usb3_streams=Enable
+ps2_port_role=Keyboard
diff --git a/src/mainboard/asus/p8x7x-series/variants/p8z77-m_pro/cmos.layout b/src/mainboard/asus/p8x7x-series/variants/p8z77-m_pro/cmos.layout
index a256ed9ddb..8e9875d33c 100644
--- a/src/mainboard/asus/p8x7x-series/variants/p8z77-m_pro/cmos.layout
+++ b/src/mainboard/asus/p8x7x-series/variants/p8z77-m_pro/cmos.layout
@@ -52,6 +52,8 @@ entries
 #
 424	1	e	1	usb3_streams
 
+426	2	e	10	ps2_port_role
+
 # -----------------------------------------------------------------
 # Sandy/Ivy Bridge MRC Scrambler Seed values
 # note: MUST NOT be covered by checksum!
@@ -114,6 +116,11 @@ enumerations
 7	14	480M
 7	15	512M
 
+# ps2_port_role
+10	0	Keyboard
+10	1	Mouse
+10	2	Auto
+
 # usb3_mode
 # Disable = Use the port always as USB 2.0 for compatibility
 # Enable = Use the port always as USB 3.0 for speed
diff --git a/src/mainboard/asus/p8x7x-series/variants/p8z77-v/cmos.default b/src/mainboard/asus/p8x7x-series/variants/p8z77-v/cmos.default
index 4501aa4904..8e4aeaf4d6 100644
--- a/src/mainboard/asus/p8x7x-series/variants/p8z77-v/cmos.default
+++ b/src/mainboard/asus/p8x7x-series/variants/p8z77-v/cmos.default
@@ -6,3 +6,4 @@ nmi=Disable
 power_on_after_fail=Disable
 sata_mode=AHCI
 gfx_uma_size=64M
+ps2_port_role=Keyboard
diff --git a/src/mainboard/asus/p8x7x-series/variants/p8z77-v/cmos.layout b/src/mainboard/asus/p8x7x-series/variants/p8z77-v/cmos.layout
index 58e2f1f6a6..e229c86e0d 100644
--- a/src/mainboard/asus/p8x7x-series/variants/p8z77-v/cmos.layout
+++ b/src/mainboard/asus/p8x7x-series/variants/p8z77-v/cmos.layout
@@ -24,6 +24,8 @@ entries
 # coreboot config options: northbridge
 416	5	e	6	gfx_uma_size
 
+428	1	e	12	ps2_port_role
+
 # coreboot config options: check sums
 984	16	h	0	check_sum
 
@@ -79,7 +81,12 @@ enumerations
 6	14	480M
 6	15	512M
 
+# ps2_port_role
+12	0	Keyboard
+12	1	Mouse
+12	2	Auto
+
 # -----------------------------------------------------------------
 checksums
 
-checksum 392 423 984
+checksum 392 431 984
diff --git a/src/mainboard/asus/p8x7x-series/variants/p8z77-v_le_plus/cmos.default b/src/mainboard/asus/p8x7x-series/variants/p8z77-v_le_plus/cmos.default
index ae789bb470..43825525e4 100644
--- a/src/mainboard/asus/p8x7x-series/variants/p8z77-v_le_plus/cmos.default
+++ b/src/mainboard/asus/p8x7x-series/variants/p8z77-v_le_plus/cmos.default
@@ -10,3 +10,4 @@ gfx_uma_size=64M
 audio_panel_type=HDA
 spdif_dest=SPDIF_OUT
 pciex16_3_bandwidth=x2
+ps2_port_role=Keyboard
diff --git a/src/mainboard/asus/p8x7x-series/variants/p8z77-v_le_plus/cmos.layout b/src/mainboard/asus/p8x7x-series/variants/p8z77-v_le_plus/cmos.layout
index 26354b17fa..bf52a2caf4 100644
--- a/src/mainboard/asus/p8x7x-series/variants/p8z77-v_le_plus/cmos.layout
+++ b/src/mainboard/asus/p8x7x-series/variants/p8z77-v_le_plus/cmos.layout
@@ -28,6 +28,7 @@ entries
 425	1	e	9	audio_panel_type
 426	1	e	10	spdif_dest
 427	1	e	11	pciex16_3_bandwidth
+428	1	e	12	ps2_port_role
 # coreboot config options: check sums
 984	16	h	0	check_sum
 
@@ -95,6 +96,11 @@ enumerations
 11	0	x2
 11	1	x4
 
+# ps2_port_role
+12	0	Keyboard
+12	1	Mouse
+12	2	Auto
+
 # -----------------------------------------------------------------
 checksums
 

From 391d5f3cb4bae451dfe7ace9c4ad4e633027e51a Mon Sep 17 00:00:00 2001
From: Varun Upadhyay <varun.upadhyay@intel.com>
Date: Wed, 18 Feb 2026 16:11:33 +0530
Subject: [PATCH 3664/3886] mb/google/ocelot/var/ojal: Enable dtt and ish based
 on FW config

This patch enables dtt and ish in devicetree for ojal and updates
FW config for GPIO's config according to schematics revision 0.9.
RDC kit no:840138

BUG=b:437459757
TEST=Build ojal board and check dmesg for errors.

Change-Id: If2ece13575ebad661cc7de78e77e3bf2f30e69e1
Signed-off-by: Varun Upadhyay <varun.upadhyay@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91334
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aralguppe, Sowmya <sowmya.aralguppe@intel.com>
Reviewed-by: Bhat D, Krishna P <krishna.p.bhat.d@intel.com>
---
 .../google/ocelot/variants/ojal/fw_config.c   |  36 +++++
 .../ocelot/variants/ojal/overridetree.cb      | 139 ++++++++++++++++++
 2 files changed, 175 insertions(+)

diff --git a/src/mainboard/google/ocelot/variants/ojal/fw_config.c b/src/mainboard/google/ocelot/variants/ojal/fw_config.c
index 39762a967c..a0e1f60ecc 100644
--- a/src/mainboard/google/ocelot/variants/ojal/fw_config.c
+++ b/src/mainboard/google/ocelot/variants/ojal/fw_config.c
@@ -142,6 +142,36 @@ static const struct pad_config cnvi_disable_pads[] = {
 	PAD_NC(GPP_F05, NONE),
 };
 
+static const struct pad_config ish_disable_pads[] = {
+	/* GPP_B06:     C_EC_ISH_ALRT */
+	PAD_NC(GPP_B06, NONE),
+	/* GPP_B07:     SLATEMODE_HALLOUT_SNSR_R */
+	PAD_NC(GPP_B07, NONE),
+	/* GPP_B18:     ISH_I2C2_SDA_SNSR_HDR */
+	PAD_NC(GPP_B18, NONE),
+	/* GPP_B19:     ISH_I2C2_SCL_SNSR_HDR */
+	PAD_NC(GPP_B19, NONE),
+	/* GPP_B23:     ISH_GP_6_SNSR_HDR */
+	PAD_NC(GPP_B23, NONE),
+	/* GPP_D06:     ISH_UART0_ECAIC_TXD */
+	PAD_NC(GPP_D06, NONE),
+};
+
+static const struct pad_config ish_enable_pads[] = {
+	/* GPP_B06:     C_EC_ISH_ALRT */
+	PAD_CFG_NF(GPP_B06, NONE, DEEP, NF4),
+	/* GPP_B07:     SLATEMODE_HALLOUT_SNSR_R */
+	PAD_CFG_NF(GPP_B07, NONE, DEEP, NF4),
+	/* GPP_B18:     ISH_I2C2_SDA_SNSR_HDR */
+	PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_B18, NONE, DEEP, NF1),
+	/* GPP_B19:     ISH_I2C2_SCL_SNSR_HDR */
+	PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_B19, NONE, DEEP, NF1),
+	/* GPP_B23:     ISH_GP_6_SNSR_HDR */
+	PAD_CFG_NF(GPP_B23, NONE, DEEP, NF4),
+	/* GPP_D06:     ISH_UART0_ECAIC_TXD */
+	PAD_CFG_NF(GPP_D06, NONE, DEEP, NF2),
+};
+
 static const struct pad_config touchpad_lpss_i2c_enable_pads[] = {
 	/* GPP_H20:     SOC_I2C_0_SCL */
 	PAD_CFG_NF(GPP_H20, NONE, DEEP, NF1),
@@ -265,6 +295,12 @@ void fw_config_gpio_padbased_override(struct pad_config *padbased_table)
 		GPIO_PADBASED_OVERRIDE(padbased_table, touchpad_i2c_disable_pads);
 	}
 
+	if (fw_config_probe(FW_CONFIG(ISH, ISH_ENABLE))) {
+		GPIO_PADBASED_OVERRIDE(padbased_table, ish_enable_pads);
+	} else {
+		GPIO_PADBASED_OVERRIDE(padbased_table, ish_disable_pads);
+	}
+
 	if (fw_config_probe(FW_CONFIG(FP, FP_PRESENT))) {
 		GPIO_PADBASED_OVERRIDE(padbased_table, fp_enable_pads);
 	} else {
diff --git a/src/mainboard/google/ocelot/variants/ojal/overridetree.cb b/src/mainboard/google/ocelot/variants/ojal/overridetree.cb
index adb8ece6a1..b548c3c468 100644
--- a/src/mainboard/google/ocelot/variants/ojal/overridetree.cb
+++ b/src/mainboard/google/ocelot/variants/ojal/overridetree.cb
@@ -38,6 +38,11 @@ end
 
 chip soc/intel/pantherlake
 
+	register "power_limits_config[WCL_CORE]" = "{
+                .tdp_pl1_override = 10,
+                .tdp_pl2_override = 35,
+        }"
+
 	register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Type C port - various configurations - TCP0
 	register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Type C port - various configurations - TCP1
 	register "usb2_ports[2]" = "USB2_PORT_MID(OC0)" # USB3.2 Gen2x1 Type-A Port
@@ -129,6 +134,132 @@ chip soc/intel/pantherlake
 
 		device ref iaa off end
 
+		device ref dtt on
+                        chip drivers/intel/dptf
+                                ## sensor information
+                                register "options.tsr[0].desc" = ""DDR_SOC""
+                                register "options.tsr[1].desc" = ""Ambient""
+                                register "options.tsr[2].desc" = ""Charger""
+                                register "options.tsr[3].desc" = ""wwan""
+
+				 ## Active Policy
+                                # FIXME: below values are initial reference values only
+                                register "policies.active" = "{
+                                                [0] = {
+                                                        .target = DPTF_TEMP_SENSOR_0,
+                                                        .thresholds = {
+                                                                        TEMP_PCT(70, 97),
+                                                                        TEMP_PCT(65, 90),
+                                                                        TEMP_PCT(60, 80),
+                                                                        TEMP_PCT(55, 75),
+                                                                        TEMP_PCT(50, 65),
+                                                                        TEMP_PCT(45, 45),
+                                                                        TEMP_PCT(43, 30),
+                                                                }
+                                                        },
+                                                [1] = {
+                                                        .target = DPTF_TEMP_SENSOR_1,
+                                                        .thresholds = {
+                                                                        TEMP_PCT(70, 97),
+                                                                        TEMP_PCT(65, 90),
+                                                                        TEMP_PCT(60, 80),
+                                                                        TEMP_PCT(55, 75),
+                                                                        TEMP_PCT(50, 65),
+                                                                        TEMP_PCT(45, 45),
+                                                                        TEMP_PCT(43, 30),
+                                                                }
+                                                        },
+                                                [2] = {
+                                                        .target = DPTF_TEMP_SENSOR_2,
+                                                        .thresholds = {
+                                                                        TEMP_PCT(75, 90),
+                                                                        TEMP_PCT(70, 80),
+                                                                        TEMP_PCT(65, 70),
+                                                                        TEMP_PCT(60, 50),
+                                                                }
+                                                        },
+                                                [3] = {
+                                                        .target = DPTF_TEMP_SENSOR_3,
+                                                        .thresholds = {
+                                                                        TEMP_PCT(75, 90),
+                                                                        TEMP_PCT(70, 80),
+                                                                        TEMP_PCT(65, 70),
+                                                                        TEMP_PCT(60, 60),
+                                                                        TEMP_PCT(55, 50),
+                                                                        TEMP_PCT(50, 40),
+                                                                        TEMP_PCT(45, 30),
+                                                                }
+                                                        }
+                                }"
+
+				 ## Passive Policy
+				 # TODO: below values are initial reference values only
+                                register "policies.passive" = "{
+                                                [0] = DPTF_PASSIVE(CPU,         CPU,           95, 5000),
+                                                [1] = DPTF_PASSIVE(CPU,         TEMP_SENSOR_0, 80, 5000),
+                                                [2] = DPTF_PASSIVE(CPU,         TEMP_SENSOR_1, 80, 5000),
+                                                [3] = DPTF_PASSIVE(CHARGER,     TEMP_SENSOR_2, 75, 5000),
+                                                [4] = DPTF_PASSIVE(CPU,         TEMP_SENSOR_3, 80, 5000),
+                                }"
+
+                                ## Critical Policy
+                                # TODO: below values are initial reference values only
+                                register "policies.critical" = "{
+                                                [0] = DPTF_CRITICAL(CPU,          105, SHUTDOWN),
+                                                [1] = DPTF_CRITICAL(TEMP_SENSOR_0, 85, SHUTDOWN),
+                                                [2] = DPTF_CRITICAL(TEMP_SENSOR_1, 85, SHUTDOWN),
+                                                [3] = DPTF_CRITICAL(TEMP_SENSOR_2, 85, SHUTDOWN),
+                                                [4] = DPTF_CRITICAL(TEMP_SENSOR_3, 85, SHUTDOWN),
+                                }"
+
+                                ## Power Limits Control
+                                register "controls.power_limits" = "{
+                                                .pl1 = {
+                                                        .min_power = 25000,
+                                                        .max_power = 25000,
+                                                        .time_window_min = 28 * MSECS_PER_SEC,
+                                                        .time_window_max = 32 * MSECS_PER_SEC,
+                                                        .granularity = 200,
+                                                },
+                                                .pl2 = {
+                                                        .min_power = 95000,
+                                                        .max_power = 95000,
+                                                        .time_window_min = 28 * MSECS_PER_SEC,
+                                                        .time_window_max = 32 * MSECS_PER_SEC,
+                                                        .granularity = 1000,
+                                                }
+                                }"
+
+                                ## Charger Performance Control (Control, mA)
+                                register "controls.charger_perf" = "{
+                                                [0] = { 255, 3000 },
+                                                [1] = {  24, 1500 },
+                                                [2] = {  16, 1000 },
+                                                [3] = {   8,  500 }
+                                }"
+
+                                ## Fan Performance Control (Percent, Speed, Noise, Power)
+                                register "controls.fan_perf" = "{
+                                                [0] = {  90, 6700, 220, 2200, },
+                                                [1] = {  80, 5800, 180, 1800, },
+                                                [2] = {  70, 5000, 145, 1450, },
+                                                [3] = {  60, 4900, 115, 1150, },
+                                                [4] = {  50, 3838,  90,  900, },
+                                                [5] = {  40, 2904,  55,  550, },
+                                                [6] = {  30, 2337,  30,  300, },
+                                                [7] = {  20, 1608,  15,  150, },
+                                                [8] = {  10,  800,  10,  100, },
+                                                [9] = {   0,    0,   0,   50, }
+                                }"
+
+                                ## Fan options
+                                register "options.fan.fine_grained_control" = "true"
+                                register "options.fan.step_size" = "2"
+
+                                device generic 0 alias dptf_policy on end
+                        end
+                end
+
 		device ref tbt_pcie_rp0 on end
 		device ref tbt_pcie_rp1 on end
 		device ref tcss_xhci on
@@ -163,6 +294,14 @@ chip soc/intel/pantherlake
 			end
 		end
 
+		 device ref ish on
+			probe ISH ISH_ENABLE
+			chip drivers/intel/ish
+				register "add_acpi_dma_property" = "true"
+				device generic 0 on end
+			end
+		end
+
 		device ref xhci on
 			chip drivers/usb/acpi
 				device ref xhci_root_hub on

From 5d6061d0ba73ce268f1d45f434827d8df7466700 Mon Sep 17 00:00:00 2001
From: Felix Held <felix-coreboot@felixheld.de>
Date: Tue, 10 Mar 2026 15:30:05 +0100
Subject: [PATCH 3665/3886] util/amdfwtool: add support for Strix Halo SoC

For amdfwtool, the Strix Halo SoC is similar to the Glinda SoC. Main
difference is the ISH PSP ID which was taken from the ISH table from the
UEFI reference implementation.

Change-Id: I6262dc8d72144ccdcd814586ef72684c15d3561d
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91638
Reviewed-by: Ritul Guru <rguru@amd.com>
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 util/amdfwtool/amdfwtool.c  | 7 +++++++
 util/amdfwtool/amdfwtool.h  | 1 +
 util/amdfwtool/data_parse.c | 6 +++++-
 util/amdfwtool/signed_psp.c | 1 +
 4 files changed, 14 insertions(+), 1 deletion(-)

diff --git a/util/amdfwtool/amdfwtool.c b/util/amdfwtool/amdfwtool.c
index af24697bca..6cd991110a 100644
--- a/util/amdfwtool/amdfwtool.c
+++ b/util/amdfwtool/amdfwtool.c
@@ -675,6 +675,7 @@ static void fill_psp_directory_to_efs(embedded_firmware *amd_romsig, void *pspdi
 	case PLATFORM_RENOIR:
 	case PLATFORM_GENOA:
 	case PLATFORM_FAEGAN:
+	case PLATFORM_STRIXHALO:
 	default:
 		/* for combo, it is also combo_psp_directory */
 		amd_romsig->new_psp_directory =
@@ -707,6 +708,7 @@ static void fill_bios_directory_to_efs(embedded_firmware *amd_romsig, void *bios
 	case PLATFORM_PHOENIX:
 	case PLATFORM_GLINDA:
 	case PLATFORM_FAEGAN:
+	case PLATFORM_STRIXHALO:
 		break;
 	case PLATFORM_CARRIZO:
 	case PLATFORM_STONEYRIDGE:
@@ -752,6 +754,9 @@ static uint32_t get_psp_id(enum platform soc_id)
 	case PLATFORM_FAEGAN:
 		psp_id = 0xbc0e1000;
 		break;
+	case PLATFORM_STRIXHALO:
+		psp_id = 0xbc0e0900;
+		break;
 	case PLATFORM_CARRIZO:
 	default:
 		psp_id = 0;
@@ -1620,6 +1625,7 @@ static int set_efs_table(uint8_t soc_id, amd_cb_config *cb_config,
 	case PLATFORM_GLINDA:
 	case PLATFORM_GENOA:
 	case PLATFORM_FAEGAN:
+	case PLATFORM_STRIXHALO:
 		amd_romsig->spi_readmode_f17_mod_30_3f = cb_config->efs_spi_readmode;
 		amd_romsig->spi_fastspeed_f17_mod_30_3f = cb_config->efs_spi_speed;
 		switch (cb_config->efs_spi_micron_flag) {
@@ -1679,6 +1685,7 @@ static bool is_initial_alignment_required(enum platform soc_id)
 	case PLATFORM_PHOENIX:
 	case PLATFORM_GLINDA:
 	case PLATFORM_FAEGAN:
+	case PLATFORM_STRIXHALO:
 		return false;
 	default:
 		return true;
diff --git a/util/amdfwtool/amdfwtool.h b/util/amdfwtool/amdfwtool.h
index fe3f72b85d..e0fae5e697 100644
--- a/util/amdfwtool/amdfwtool.h
+++ b/util/amdfwtool/amdfwtool.h
@@ -35,6 +35,7 @@ enum platform {
 	PLATFORM_GLINDA,
 	PLATFORM_GENOA,
 	PLATFORM_FAEGAN,
+	PLATFORM_STRIXHALO,
 };
 
 typedef enum _amd_fw_type {
diff --git a/util/amdfwtool/data_parse.c b/util/amdfwtool/data_parse.c
index 2ea37efd67..961b6a1c18 100644
--- a/util/amdfwtool/data_parse.c
+++ b/util/amdfwtool/data_parse.c
@@ -119,6 +119,8 @@ static enum platform identify_platform(char *soc_name)
 		return PLATFORM_GENOA;
 	else if (!strcasecmp(soc_name, "Faegan"))
 		return PLATFORM_FAEGAN;
+	else if (!strcasecmp(soc_name, "Strixhalo"))
+		return PLATFORM_STRIXHALO;
 	else
 		return PLATFORM_UNKNOWN;
 }
@@ -791,7 +793,8 @@ static uint8_t process_one_line(char *oneline, regmatch_t *match, char *dir,
 static bool needs_ish(enum platform platform_type)
 {
 	if (platform_type == PLATFORM_MENDOCINO || platform_type == PLATFORM_PHOENIX ||
-		platform_type == PLATFORM_GLINDA || platform_type == PLATFORM_FAEGAN)
+		platform_type == PLATFORM_GLINDA || platform_type == PLATFORM_FAEGAN ||
+		platform_type == PLATFORM_STRIXHALO)
 		return true;
 	else
 		return false;
@@ -818,6 +821,7 @@ static bool is_second_gen(enum platform platform_type)
 	case PLATFORM_GLINDA:
 	case PLATFORM_GENOA:
 	case PLATFORM_FAEGAN:
+	case PLATFORM_STRIXHALO:
 		return true;
 	case PLATFORM_UNKNOWN:
 	default:
diff --git a/util/amdfwtool/signed_psp.c b/util/amdfwtool/signed_psp.c
index 18215a04c2..14d0a13b9b 100644
--- a/util/amdfwtool/signed_psp.c
+++ b/util/amdfwtool/signed_psp.c
@@ -41,6 +41,7 @@ static uint16_t get_psp_fw_type(enum platform soc_id, struct amd_fw_header *head
 	case PLATFORM_PHOENIX:
 	case PLATFORM_GLINDA:
 	case PLATFORM_FAEGAN:
+	case PLATFORM_STRIXHALO:
 		/* Fallback to fw_type if fw_id is not populated, which serves the same
 		   purpose on older SoCs. */
 		return header->fw_id ? header->fw_id : header->fw_type;

From 0be563503ad88796aa030247392dfc4886aa6ddb Mon Sep 17 00:00:00 2001
From: Wentao Qin <qinwentao@huaqin.corp-partner.google.com>
Date: Wed, 25 Feb 2026 21:43:38 +0800
Subject: [PATCH 3666/3886] mb/google/rauru: Support new bias IC TPS65130RGER
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

The panel uses TPS65130RGER as the bias IC, with supply set to ±5.9V.
Configure TPS65130RGER initialization and power-on sequence according
to the tps65130.pdf.
The tps65132s driver is no longer used on this platform and remove it
from the build.

[INFO ]  mtk_display_init: 'BOE NS130069' 3504x2190@120Hz bpp 4

BUG=b:463911061
TEST=Check display initialization log and display are normal
BRANCH=none

Change-Id: Idfc19597c4357adb818ca008f93bac2e7ebe3edb
Signed-off-by: Wentao Qin <qinwentao@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91424
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
---
 src/mainboard/google/rauru/Makefile.mk       |  1 -
 src/mainboard/google/rauru/panel.h           | 12 -------
 src/mainboard/google/rauru/panel_sapphire.c  | 22 ++++++++----
 src/mainboard/google/rauru/panel_tps65132s.c | 38 --------------------
 src/soc/mediatek/mt8196/Makefile.mk          |  1 -
 5 files changed, 15 insertions(+), 59 deletions(-)
 delete mode 100644 src/mainboard/google/rauru/panel_tps65132s.c

diff --git a/src/mainboard/google/rauru/Makefile.mk b/src/mainboard/google/rauru/Makefile.mk
index 0d44451727..b13c77ecf6 100644
--- a/src/mainboard/google/rauru/Makefile.mk
+++ b/src/mainboard/google/rauru/Makefile.mk
@@ -11,7 +11,6 @@ romstage-y += romstage.c
 ramstage-y += boardid.c
 ramstage-y += mainboard.c
 ramstage-y += panel.c
-ramstage-y += panel_tps65132s.c
 ramstage-y += regulator.c
 
 ramstage-$(CONFIG_BOARD_GOOGLE_SAPPHIRE) += panel_sapphire.c
diff --git a/src/mainboard/google/rauru/panel.h b/src/mainboard/google/rauru/panel.h
index 954a2e8405..d44ff10774 100644
--- a/src/mainboard/google/rauru/panel.h
+++ b/src/mainboard/google/rauru/panel.h
@@ -3,22 +3,10 @@
 #ifndef __MAINBOARD_GOOGLE_RAURU_PANEL_H__
 #define __MAINBOARD_GOOGLE_RAURU_PANEL_H__
 
-#include <gpio.h>
 #include <soc/display.h>
-#include <soc/i2c.h>
-#include <soc/tps65132s.h>
-
-#define PMIC_TRS65132S_SLAVE	0x3e
-#define PMIC_I2C_BUS		I2C7
-
-struct tps65132s_config {
-	uint32_t i2c_bus;
-	gpio_t en;
-};
 
 uint32_t panel_id(void);
 void configure_backlight(bool enable);
-void tps65132s_power_on(struct tps65132s_cfg *config);
 
 /* Return the MIPI panel description */
 struct panel_description *get_panel_description(void);
diff --git a/src/mainboard/google/rauru/panel_sapphire.c b/src/mainboard/google/rauru/panel_sapphire.c
index a832f7d6d1..829ef0c54f 100644
--- a/src/mainboard/google/rauru/panel_sapphire.c
+++ b/src/mainboard/google/rauru/panel_sapphire.c
@@ -1,19 +1,27 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
 #include <console/console.h>
-#include <soc/tps65132s.h>
+#include <delay.h>
+#include <gpio.h>
+#include <soc/mt6363.h>
 
 #include "gpio.h"
 #include "panel.h"
 
 static void mipi_panel_power_on(void)
 {
-	struct tps65132s_cfg config = {
-		.i2c_bus = PMIC_I2C_BUS,
-		.en = GPIO_EN_PP3300_EDP_X,
-		.sync = GPIO_EN_PPVAR_MIPI_DISP,
-	};
-	tps65132s_power_on(&config);
+	mt6363_enable_vrf18(true); /* VDD */
+	mdelay(3); /* tsVSP */
+	gpio_output(GPIO_EN_PP3300_EDP_X, 1); /* AVDD */
+	mdelay(2); /* tPON1 */
+	gpio_output(GPIO_EN_PPVAR_MIPI_DISP, 1); /* AVEE */
+	mdelay(2);
+	mdelay(10); /* tRW */
+	gpio_output(GPIO_LCM_RST_1V8_L, 1); /* RESX */
+	mdelay(5);
+	gpio_output(GPIO_LCM_RST_1V8_L, 0);
+	mdelay(5);
+	gpio_output(GPIO_LCM_RST_1V8_L, 1);
 }
 
 static struct panel_description sapphire_panels[] = {
diff --git a/src/mainboard/google/rauru/panel_tps65132s.c b/src/mainboard/google/rauru/panel_tps65132s.c
deleted file mode 100644
index 85677ea02d..0000000000
--- a/src/mainboard/google/rauru/panel_tps65132s.c
+++ /dev/null
@@ -1,38 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <console/console.h>
-#include <delay.h>
-#include <gpio.h>
-#include <soc/regulator.h>
-#include <soc/tps65132s.h>
-#include <soc/mt6363.h>
-
-#include "gpio.h"
-#include "panel.h"
-
-void tps65132s_power_on(struct tps65132s_cfg *config)
-{
-	const struct tps65132s_reg_setting reg_settings[] = {
-		{ PMIC_TPS65132_VPOS, 0x14, 0x1F },
-		{ PMIC_TPS65132_VNEG, 0x14, 0x1F },
-		{ PMIC_TPS65132_DLYX, 0x95, 0xFF },
-		{ PMIC_TPS65132_ASSDD, 0x5B, 0xFF },
-	};
-
-	mt6363_enable_vrf18(true);
-	config->settings = reg_settings;
-	config->setting_counts = ARRAY_SIZE(reg_settings);
-
-	mtk_i2c_bus_init(config->i2c_bus, I2C_SPEED_FAST);
-
-	if (tps65132s_setup(config) != CB_SUCCESS)
-		printk(BIOS_ERR, "Failed to set up tps65132s\n");
-
-	/* DISP_RST_1V8_L */
-	mdelay(10);
-	gpio_output(GPIO_LCM_RST_1V8_L, 1);
-	mdelay(10);
-	gpio_output(GPIO_LCM_RST_1V8_L, 0);
-	mdelay(10);
-	gpio_output(GPIO_LCM_RST_1V8_L, 1);
-}
diff --git a/src/soc/mediatek/mt8196/Makefile.mk b/src/soc/mediatek/mt8196/Makefile.mk
index 1a6159079e..dacbd855b0 100644
--- a/src/soc/mediatek/mt8196/Makefile.mk
+++ b/src/soc/mediatek/mt8196/Makefile.mk
@@ -90,7 +90,6 @@ ramstage-y += ../common/pmif_clk.c pmif_clk.c
 ramstage-y += ../common/pmif.c pmif_init.c
 ramstage-y += ../common/pmif_spmi_v2.c pmif_spmi.c
 ramstage-y += ../common/rtc.c ../common/rtc_osc_init.c
-ramstage-y += ../common/tps65132s.c
 ramstage-y += ../common/usb.c usb.c
 
 BL31_MAKEARGS += PLAT=mt8196

From 9bb822dbf89a7e6d0f883e4a35a6c88c16f26533 Mon Sep 17 00:00:00 2001
From: Mike Banon <mikebdp2@gmail.com>
Date: Tue, 10 Mar 2026 18:07:43 +0300
Subject: [PATCH 3667/3886] Update vboot submodule from 2024 to upstream main
 2026

Updating from commit id 3f94e2c7ed58:
2024-12-18 - Makefile: Allow cross-compilation for RISC-V

to commit id 5c360ef458b0:
2026-03-10 - lib20: Add vb2api_verify_kernel_data back

This brings in 182 new commits listed below. Build tests for AMD AGESA
boards that I am maintaining with restore_agesa.sh - are successful.

5c360ef458b0 lib20: Add vb2api_verify_kernel_data back
24655cd2309e cbfstool: fix const-discarding warning in extract_config_value
b9ea1075a7d2 firmware/2lib: Remove unused vb2_sha256_extend function
7934c1c9c991 firmware/2lib: Remove dead kernel verification function references
25083888d265 Add .editorconfig
3109519e8841 tests: Remove unused sha_tests.c
850cf0fbe5b5 tests/tpm_lite: Remove unused files
42f5313871c6 firmware: Do not allow for dev mode with oem_lock enabled
c16e6afaced4 firmware: host: Add OEM Lock flag to nvstorage dev field
ed6cb4054134 tests: add test cases for booting OTA recovery partition
606ca738a7d3 vboot: Implement Network Based Recovery (NBR) using OTA recovery partition
7529e2837c55 2lib: rename functions & variables related to MiniOS
6aba77a84c2b vboot: Add GPT_DISK_UUID_RECOVERY marker
ec74b34cd6ce vboot: Add declaration of vb2ex_slice_disk() callback
e388d1f93c95 futility: Print programmer in logs
a1f54de5001c Skip ec.config if there is no space
5040bde7243f futility: Prioritize identity.csv over Android property ro.product.name
a5f6ef5e327e sign_uefi: Use the v2 crdyshim key for signing crdyboot
fa13af3ccc36 futility: Support model detection by Android property ro.product.name
cca9e4a676f3 vb2_sha: Use uint64_t for total size in SHA-2
0ee734db27fe test: fix problem with load android test cases
5a45a5f32dcf Android.bp: allow libvboot_host to be built as a shared library
89b720193a09 tests: initialize cmdline for AVB verify data
c851dfa1e384 tests: add vboot avb test cases
86e3d6b720cb tests: add test cases to boot android kernel
461398242604 Fix OpenSSL memory leaks and incorrect free() usage
7b8a96024b7c crossystem: Use libflashrom instead of flashrom CLI for USE_FLASHROM=1
dd0bab314680 futility/updater: Check FMAP compatibility
4f3a73dd50f0 tests/futility/test_update: Make FROM_IMAGE and TO_IMAGE same board
93711fc01e5a 2lib: Implement rollback protection for Android
ad3b7b64283b sign_uefi: Update handling for presigned crdyboot builds
6e8977429f53 avb: adjust Makefile for changes in AVB repo
f963a5069755 host/flashrom_drv: refactor flashrom initialization
1de7d46170ea tests/futility/test_update: Dynamically calculate image size
ac9e57cffd22 tests/futility/run_test_scripts: Filter tests via FUTIL_TEST_SCRIPT
b3780bbaaced crossystem: Fix crossystem lock file unlocking
6b8337fb608b Add 'runfutiltestscripts' make target
5d6a647a1f29 tests/vb2_avb_tests.c: add key validation tests
d3f2d712c205 avb: Fix format specifier for debug messages
67fb9d2b799a futility: Add missing gscvd.c file to futility_srcs for Soong
4ce2c1a44c95 futility: add check-fwid flag to update command
3c47ec0a951b firmware/2lib: Move base DTB image into dtbo partition
0413878d374c futility: Support RO_GSCVD region for 'futility show'
ffab62e169e8 futility: Add futil_valid_gscvd_header()
6c242361a867 sign_uefi: Skip crdyboot signing if already signed
7a2ba18765eb 2lib: remove partition_number variable
5f958f17f4b6 2lib: use correct structure for guid
a11ad5ccdeae lib20: remove unused code
f290e75b7441 futility: Utilize identity.csv for remote device
24e62a619e81 futility: Add --frid and --sku-id arguments
f80af2766ecb firmware: GBB flag to ignore rollback applies to kernel too
34431212e1e9 futility: Update --model help text
a086faa63858 vboot: Rename vb2ex_get_android_bootmode to vb2ex_handle_android_misc_partition
f90a1c7ab168 tests/vb2_host_flashrom_tests: Fix missing '\0' for strncpy call
ed024e5cc5a7 Makefile: fix runtests fails when USE_FLASHROM=0
9cce699aa655 host/lib/flashrom_drv: Change the return type from int to vb2_error_t
14cee0b25665 make_dev_ssd: Add crash_kexec_post_notifiers with kdump
5659718d037e avb: Use hardware-accelerated SHA256
a549dc16e50a 2lib: Rename vboot_cmdline related buffers
5ffc2321290d Makefile: include vb2_host_nvdata_flashrom_tests in run2tests target
59cb8b6e6dbf Makefile: include vb2_host_flashrom_tests in run2tests target
60c75230ab6f Makefile: include vb2_recovery_reasons_tests in run2tests target
f344c1f022fe make_dev_ssd: Add --minios_key
9daff4f9319e avb/vboot_avb_ops: Refactor reserve_buffers to reduce code duplication
b97b60477b60 2api: Add support to load DTB/DTBO images from GPT partitions
90e322680f66 Reland "firmware/lib/cgptlib: Add GPT partition name for DTB/DTBO partitions"
2aae1741d8b8 avb/vboot_avb_ops: Continue without buffer for optional partitions
136e1229054c futility: Add unit tests for misc
47fa4d7227de treewide: Remove the space before labels
dd3c8066cda7 2load_android_kernel: Fix VB2_GBB_FLAG_FORCE_UNLOCK_FASTBOOT usage
3f578eceb517 Revert "2api: Add support to load DTB/DTBO images from GPT partitions"
a3e0e039a9a4 Revert "firmware/lib/cgptlib: Add GPT partition name for DTB/DTBO partitions"
0ed3061c8343 futility: Extract unit test utils into separate header
9fbd15cce715 2api: Add support to load DTB/DTBO images from GPT partitions
2f200d714993 firmware/lib/cgptlib: Add GPT partition name for DTB/DTBO partitions
db4e4c16938c gpt: Cleanup GPT constants
e4e2a4648678 host: Add error messages to NV read/write
d3bdaba00d45 futility: Add unit tests for updater utils
e0cef21436af crossystem/GetAcpiSysfsPath: Add stat check for current_path
05353d26e826 cgptlib: Expose GptModified as external API
63ebdf94d2ef futility/updater: Utilize identity.csv or crosid for --detect-model-only
b10850ad6e19 futility/updater: Support model identification with identity.csv
30e5f1a11302 Update kernel command line with `cros_part_hash` for specific partitions
c37d42900911 Delete `resign_kernel_partition.sh`
8f7b522a4b72 Remove deprecated stateful partition vblock update
015c6eedb91e Fix array iteration in `ensure_no_nonrelease_files.sh`
b20dfa89a76b Always mount ESP as read-write
485bf8061f51 futility: remove unused variable
9510c7f8eeb0 Reorder recovery kernel hash updates after MiniOS resigning
42a6ca910398 Remove engeg@ from scripts/OWNERS
26130316a50b futility/archive: Add libziparchive support on Android
87401a655f5c futility: Extract archive implementations to separate files
9b362962860c cgptlib: Make IsBootableEntry available for depthcharge
ac6cc721c1ef 2lib: Get Android boot mode
9863e6ea9410 2lib: Introduce FORCE_UNLOCK_FASTBOOT GBB flag
6cf177721568 cgptlib: Move cgptlib.h to firmware/include dir
4ab8d0085e8d futility/updater: Add load_system_frid() and get_model_from_frid()
f5e37de5b6b8 host/lib/flashrom: Free image data on flashrom_read_* failure
85ace4b96d6a futility/updater_dut: Introduce DUT_PROP_SKU_ID
6b93d66ec4a6 futility/updater_dut: Extend property type from int to int64_t
de036f432202 common: make optional arg actually optional
e8e6493e1f92 2lib: Modify logic of setting secdata kernel version
3d5855fa8da3 2lib: Move kernel secdata update to vb2api_load_kernel()
d89559b1f1fa gpt_misc: Validate pointer before usage
ee209148a4ff host/crossystem: Introduce VbGetSystemSkuId()
e3f41133afcb host/arch/arm/crossystem: Fix return type of ReadFdtInt
c8facc216cec host/arch/stub/crossystem: Fix "const char* name"
10316632b505 host: crossystem: gpio: Use correct GPIO controller offset
dcf300d273f2 OWNERS: Add bernacki
f1619fa67e15 futility/cmd_gbb_utility: add --verbose
92c264a42bed gpio_uapi: remove unused variable
68ec7968e66e Android.bp: Fix vb2_sha256_x86_tests target config
88ac12115cb1 crossystem: Remove wpsw_cur fallback to VDAT_INT_HW_WPSW_BOOT
f1f6b42aa4e0 crossystem: x86: Remove deprecated GPIO SYSFS code
d35aee8d15fc crossystem: host: Add support for reading GPIO from /dev/gpiochipX
2e1ed1f914ed dts: Add cc_test for x86 sha tests
8bf055106225 dts: add filegroup for devkeys
42e098dc402c avb: Implement unaligned read in load_partition
cb9f18bcfbca futility/updater: Add warning for full firmware update without WP
357561a2a82e futility/update: Assume WP is off for all remote operations
50bb82087123 avb: Add pvmfw verification and loading to memory.
a0a2affafcc0 2api: Expand vb2_kernel_params for pvmfw loading
b5fb33f01c34 tlcl: Increase TPM buffer size
dbdf50adc5e6 2load_android_kernel: Set VB2_SD_FLAG_KERNEL_SIGNED on verify success
9080ef62a9c9 uefi: add --keyform engine for pkcs11
c67404f06dfb swap_ec_rw: Support legacy EC image
9bd1a6dab45e Revert "Handle both RW_FW and EC_RW sections"
fcbc0a884ddd Update crdyshim keygen script to use ECDSA
af71ac87e4a4 host: Fix compilation error with GCC
c5ac68e4d273 futility: updater: Allow --quirks=preserve_me=2 to force preserving ME
ec4d7436be0c vb21: load private key before signing
39f6104b29e1 swap_ec_rw: Support giving a raw EC RW image
b7adaa2b97fe 2lib: Add androidboot parameters
b3b414cc307f 2lib: Drop unused ramdisk fragments based on BCB command
093e3608a529 2lib: Load Android kernel
a682da7d92db 2lib: Rearrange buffers with android partitions
076d4d38f9f6 2lib: Load and verify android partitions
f1df391e6d05 avb: Get preloaded partitions
45176543c260 avb: Add callback for public key verification
6dc845b9b4c9 avb: Add avb_ops for IO operations
911e5a6e4603 avb: Implement basic AVB callbacks
1fe2d7b5e555 futility: Fix load_firmware_image() for empty file name
44dc81ca128b 2lib: Make need_valid_keyblock() function global
35ea5c842733 2lib: Rename kernel type macros
c51cbc4ace85 tests: fix build errors with USE_FLASHROM=0
3f36817a50e3 cgptlib: Allow to boot from Android vbmeta
34cb9f619615 cgptlib: Add helper functions for partition loading
0130a541cb06 android: Port image headers definition
af0a2547170e vboot.rc: Fix TMPFS mounting and unmounting
ea4986b060ad cgpt: Add Gpt prefix to StrToGuid() function
015ee35a494c cgpt: Move GuidToStr to firmware code
2df1fe56f588 cgpt: Reformat code using clang-format
e9d7bd044a43 sign_gsc_firmware.sh: sing ECDSA only image for NT
8c2235b52196 crossystem: Add support for additional GPIO communities
2955db3c48bd futility: dump_fmap: Fix gap calculation
4134ab60ea70 tests/futility/test_dump_fmap: Allow easier expected output updates
1655f1a9f9a2 swap_ec_rw: Extract ecrw version to correct file
1c7a767b3353 Handle both RW_FW and EC_RW sections
8786d36c388c sign_gsc_firmware: extend to support signing NT images
4a9586937f19 swap_ec_rw: Support swap from AP image
44db1807c246 gsc: fix typo in calling out to script
06d58e2132d3 swap_ec_rw: Check ecrw.version/config exist before removal
a57167e79e4b pkcs11: add ID field
d6e67ecf0824 gsc: add env var support
8eea96333f62 2secdata_kernel: Improve log about incomplete secdata_kernel
bf4b21294a1c Include ec.config when swapping
9038039fbb32 futility: updater: Cap try count to 15
ae6ceb20d5e2 Android.bp: Make crossystem default to /vendor partition
2dde4ce9badc cgpt: repair: handle drive size expansion
993e0bf7bdbc cgpt: create: calculate Last Usable LBA in DriveLastUsableLBA()
3a37ae87f637 firmware/2lib: Refactor ec_sync_phase1 for clarity
6caf4cd6225f firmware/2lib: Remove redundant EC sync check in recovery
1f8153d95a93 scripts/image_signing/swap_ec_rw: Print the versions of the AP image
6f63b28162cd Makefile: Optimize dirname invocation
177c0582ad4f Makefile: Remove $(shell) invocations from CFLAGS
621899d6e89f vboot: modify GptNextKernelEntry function
993ef3126919 uefi: only check for key existence in local key mode
7fdca50ac14f Introduce new entry type for vbmeta
2e00eae8f9a0 firmware/2lib: Add a log for try_count used up
7e5bda8a8210 futility: updater: Increase try count from 13 to 17
3498c54d26a9 signing: add condition for flexor
c3f20ccfcf30 Makefile: Export swap_ec_rw script to OS image

Change-Id: Iad381e717ccf3db6cb5f0a3d408e0033fdba0538
Signed-off-by: Mike Banon <mikebdp2@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91640
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Erik van den Bogaert <ebogaert@eltan.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
---
 3rdparty/vboot | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/3rdparty/vboot b/3rdparty/vboot
index 3f94e2c7ed..5c360ef458 160000
--- a/3rdparty/vboot
+++ b/3rdparty/vboot
@@ -1 +1 @@
-Subproject commit 3f94e2c7ed58c4e67d6e7dc6052ec615dbbb9bb4
+Subproject commit 5c360ef458b0a013d8a6d47724bb0fffb5accbcf

From 4d9cb5336f04a84fb7b4cf916b7b2b4fb0fdcabf Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Wed, 4 Mar 2026 09:46:29 +0000
Subject: [PATCH 3668/3886] mainboard/starlabs: drop display_native_res VBT
 toggle

A local patch providing basic 2x scaling in edk2 means that the
fixed resolution VBTs are no longer needed so always use the
native-resolution VBT by default,

Remove the CFR option to pick which VBT to use, so only the native
resolution VBTs are used and included.

Change-Id: Ib7f4c546a01ebfba963b7591af9d5e24c0611206
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91618
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/starlabs/adl/cfr.c              |  13 ++-----------
 .../starlabs/adl/variants/hz/Makefile.mk      |   2 --
 .../starlabs/adl/variants/hz/data.vbt         | Bin 9216 -> 9216 bytes
 .../adl/variants/hz/data_native_res.vbt       | Bin 9216 -> 0 bytes
 .../starlabs/adl/variants/hz/ramstage.c       |   4 ----
 .../starlabs/adl/variants/i5/Makefile.mk      |   2 --
 .../starlabs/adl/variants/i5/data.vbt         | Bin 9216 -> 9216 bytes
 .../adl/variants/i5/data_native_res.vbt       | Bin 9216 -> 0 bytes
 .../starlabs/adl/variants/i5/ramstage.c       |   4 ----
 .../starlabs/common/include/common/cfr.h      |   8 --------
 src/mainboard/starlabs/starbook/cfr.c         |  13 -------------
 src/mainboard/starlabs/starbook/mainboard.c   |   4 ----
 .../starbook/variants/adl_n/Makefile.mk       |   2 --
 .../starlabs/starbook/variants/adl_n/data.vbt | Bin 9216 -> 9216 bytes
 .../variants/adl_n/data_native_res.vbt        | Bin 9216 -> 0 bytes
 .../starbook/variants/mtl/Makefile.mk         |   2 --
 .../starlabs/starbook/variants/mtl/data.vbt   | Bin 7680 -> 7680 bytes
 .../starbook/variants/mtl/data_native_res.vbt | Bin 7680 -> 0 bytes
 src/mainboard/starlabs/starfighter/cfr.c      |   9 ---------
 .../starfighter/variants/mtl/Makefile.mk      |   2 --
 .../starfighter/variants/mtl/data.vbt         | Bin 7680 -> 7680 bytes
 .../variants/mtl/data_native_res.vbt          | Bin 7680 -> 0 bytes
 .../starfighter/variants/mtl/ramstage.c       |   5 -----
 .../starfighter/variants/rpl/Makefile.mk      |   2 --
 .../starfighter/variants/rpl/data.vbt         | Bin 9216 -> 9216 bytes
 .../variants/rpl/data_native_res.vbt          | Bin 9216 -> 0 bytes
 .../starfighter/variants/rpl/ramstage.c       |   3 ---
 27 files changed, 2 insertions(+), 73 deletions(-)
 delete mode 100644 src/mainboard/starlabs/adl/variants/hz/data_native_res.vbt
 delete mode 100644 src/mainboard/starlabs/adl/variants/i5/data_native_res.vbt
 delete mode 100644 src/mainboard/starlabs/starbook/variants/adl_n/data_native_res.vbt
 delete mode 100644 src/mainboard/starlabs/starbook/variants/mtl/data_native_res.vbt
 delete mode 100644 src/mainboard/starlabs/starfighter/variants/mtl/data_native_res.vbt
 delete mode 100644 src/mainboard/starlabs/starfighter/variants/rpl/data_native_res.vbt

diff --git a/src/mainboard/starlabs/adl/cfr.c b/src/mainboard/starlabs/adl/cfr.c
index 8c8f5f601f..89f7730e45 100644
--- a/src/mainboard/starlabs/adl/cfr.c
+++ b/src/mainboard/starlabs/adl/cfr.c
@@ -58,23 +58,16 @@ static struct sm_obj_form keyboard_group = {
 };
 #endif
 
-#if CONFIG(SYSTEM_TYPE_LAPTOP) || CONFIG(SYSTEM_TYPE_DETACHABLE)
+#if CONFIG(BOARD_STARLABS_LITE_ADL)
 static struct sm_obj_form display_group = {
 	.ui_name = "Display",
 	.obj_list =
 		(const struct sm_object *[]){
-#if CONFIG(BOARD_STARLABS_LITE_ADL)
 					     &accelerometer,
-#endif
-					     &display_native_res,
-#if CONFIG(BOARD_STARLABS_LITE_ADL)
 					     &touchscreen,
-#endif
 					     NULL, },
 };
-#endif
 
-#if CONFIG(BOARD_STARLABS_LITE_ADL)
 static struct sm_obj_form io_expansion_group = {
 	.ui_name = "I/O / Expansion",
 	.obj_list =
@@ -140,10 +133,8 @@ static struct sm_obj_form *sm_root[] = {
 #endif
 	&battery_group,
 	&debug_group,
-#if CONFIG(SYSTEM_TYPE_LAPTOP) || CONFIG(SYSTEM_TYPE_DETACHABLE)
-	&display_group,
-#endif
 #if CONFIG(BOARD_STARLABS_LITE_ADL)
+	&display_group,
 	&io_expansion_group,
 #endif
 #if CONFIG(SYSTEM_TYPE_LAPTOP)
diff --git a/src/mainboard/starlabs/adl/variants/hz/Makefile.mk b/src/mainboard/starlabs/adl/variants/hz/Makefile.mk
index bfea7ef255..9abc069b38 100644
--- a/src/mainboard/starlabs/adl/variants/hz/Makefile.mk
+++ b/src/mainboard/starlabs/adl/variants/hz/Makefile.mk
@@ -8,5 +8,3 @@ ramstage-y += devtree.c
 ramstage-y += gpio.c
 ramstage-y += hda_verb.c
 ramstage-y += ramstage.c
-
-$(call add_vbt_to_cbfs, vbt_native_res.bin, data_native_res.vbt)
diff --git a/src/mainboard/starlabs/adl/variants/hz/data.vbt b/src/mainboard/starlabs/adl/variants/hz/data.vbt
index 8c22ab4f40c953db62bbe3744709b4430e547cff..a101af780b8ecc78fff9335c3dc0cab7239b2250 100644
GIT binary patch
delta 45
ucmZqhXz-XI#azT-Fu9OXc%#7s0UibzFfn7^EFkoPak7BWm(4$fIRpR%$_sx0

delta 45
zcmZqhXz-XI#cal4Fu9OXc%#7s0UpLTEDQ`D%nS@BX3U!fgkCUC77+Tf`G+uv000?`
B41WLs

diff --git a/src/mainboard/starlabs/adl/variants/hz/data_native_res.vbt b/src/mainboard/starlabs/adl/variants/hz/data_native_res.vbt
deleted file mode 100644
index a101af780b8ecc78fff9335c3dc0cab7239b2250..0000000000000000000000000000000000000000
GIT binary patch
literal 0
HcmV?d00001

literal 9216
zcmeHMUrbw782`?_ZRu)}ZlLRM!vkBe;DAfnkP(vI^3QdH(E=k~qM>80N@N2WGt8Lm
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zF>qh`9N(+$3rwRa=xC^ivn(hH7P478XCBBZZJs=t`LmF%um~+cR+}eF%_^ijG(`u>
zlFgqdyVK8T#J<RS$%HLckcopZ`~v@!Vq`iJq!9;Z)ta42$js9U86}o%$+jP!TfZWO
z%$8u3u%}pvuF{-Z15E3TEo8z6-LXtw3PTnX+F;ASt>Th|{6MLQO9DrFSflPntz29x
ux`i!X_})NmwuU@Auf2ypapD&_E^?H^7WqFw#`Avt_aw*=wjw>b5%?PomVhn*

diff --git a/src/mainboard/starlabs/adl/variants/hz/ramstage.c b/src/mainboard/starlabs/adl/variants/hz/ramstage.c
index 370f5c8769..de25c0a7e5 100644
--- a/src/mainboard/starlabs/adl/variants/hz/ramstage.c
+++ b/src/mainboard/starlabs/adl/variants/hz/ramstage.c
@@ -2,7 +2,6 @@
 
 #include <drivers/intel/gma/opregion.h>
 #include <soc/ramstage.h>
-#include <option.h>
 #include <common/pin_mux.h>
 
 void mainboard_silicon_init_params(FSP_S_CONFIG *supd)
@@ -12,8 +11,5 @@ void mainboard_silicon_init_params(FSP_S_CONFIG *supd)
 
 const char *mainboard_vbt_filename(void)
 {
-	if (get_uint_option("display_native_res", 0) == 1)
-		return "vbt_native_res.bin";
-
 	return "vbt.bin";
 }
diff --git a/src/mainboard/starlabs/adl/variants/i5/Makefile.mk b/src/mainboard/starlabs/adl/variants/i5/Makefile.mk
index d6e2d5b29d..4bd5ef44c0 100644
--- a/src/mainboard/starlabs/adl/variants/i5/Makefile.mk
+++ b/src/mainboard/starlabs/adl/variants/i5/Makefile.mk
@@ -9,5 +9,3 @@ ramstage-y += gpio.c
 ramstage-y += hda_verb.c
 ramstage-y += mainboard_ssdt.c
 ramstage-y += ramstage.c
-
-$(call add_vbt_to_cbfs, vbt_native_res.bin, data_native_res.vbt)
diff --git a/src/mainboard/starlabs/adl/variants/i5/data.vbt b/src/mainboard/starlabs/adl/variants/i5/data.vbt
index 3b0236d896639cc33734710dc8a4527cc631e290..13c5b92d61f599b4168691619efc28a28e05e7f4 100644
GIT binary patch
delta 45
ucmZqhXz-XI#oWYTFu9OXc%#7s0UibzFfn7^EFkoPak7BWm(4$fIRpR)DhrPQ

delta 45
zcmZqhXz-XI#azr_Fu9OXc%#7s0UkyR76yh3ObiSrX3U!fgkCUC77+Tf`G+uv000~s
B437W+

diff --git a/src/mainboard/starlabs/adl/variants/i5/data_native_res.vbt b/src/mainboard/starlabs/adl/variants/i5/data_native_res.vbt
deleted file mode 100644
index 13c5b92d61f599b4168691619efc28a28e05e7f4..0000000000000000000000000000000000000000
GIT binary patch
literal 0
HcmV?d00001

literal 9216
zcmeHMUrbw782`?_ZRu)}ZlLRM!vkBe;DAfnkP(vI^3QdH(E=k~qM>80j>rZwW|%SA
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diff --git a/src/mainboard/starlabs/adl/variants/i5/ramstage.c b/src/mainboard/starlabs/adl/variants/i5/ramstage.c
index 370f5c8769..de25c0a7e5 100644
--- a/src/mainboard/starlabs/adl/variants/i5/ramstage.c
+++ b/src/mainboard/starlabs/adl/variants/i5/ramstage.c
@@ -2,7 +2,6 @@
 
 #include <drivers/intel/gma/opregion.h>
 #include <soc/ramstage.h>
-#include <option.h>
 #include <common/pin_mux.h>
 
 void mainboard_silicon_init_params(FSP_S_CONFIG *supd)
@@ -12,8 +11,5 @@ void mainboard_silicon_init_params(FSP_S_CONFIG *supd)
 
 const char *mainboard_vbt_filename(void)
 {
-	if (get_uint_option("display_native_res", 0) == 1)
-		return "vbt_native_res.bin";
-
 	return "vbt.bin";
 }
diff --git a/src/mainboard/starlabs/common/include/common/cfr.h b/src/mainboard/starlabs/common/include/common/cfr.h
index de4f108404..1a0dabbe86 100644
--- a/src/mainboard/starlabs/common/include/common/cfr.h
+++ b/src/mainboard/starlabs/common/include/common/cfr.h
@@ -40,14 +40,6 @@ static const struct sm_object card_reader = SM_DECLARE_BOOL({
 	.default_value	= !CONFIG(BOARD_STARLABS_LITE_ADL),
 }, WITH_CALLBACK(cfr_card_reader_update));
 
-static const struct sm_object display_native_res = SM_DECLARE_BOOL({
-	.opt_name	= "display_native_res",
-	.ui_name	= "Display: Use Native Resolution",
-	.ui_helptext	= "Enabled: use the native panel resolution at boot.\n"
-			  "Disabled: use a fixed/scaled video mode at boot.",
-	.default_value	= false,
-});
-
 static const struct sm_object fingerprint_reader = SM_DECLARE_BOOL({
 	.opt_name	= "fingerprint_reader",
 	.ui_name	= "Fingerprint Reader",
diff --git a/src/mainboard/starlabs/starbook/cfr.c b/src/mainboard/starlabs/starbook/cfr.c
index d2e8b7c9ae..a561666812 100644
--- a/src/mainboard/starlabs/starbook/cfr.c
+++ b/src/mainboard/starlabs/starbook/cfr.c
@@ -36,16 +36,6 @@ static struct sm_obj_form debug_group = {
 	},
 };
 
-#if CONFIG(BOARD_USES_FIXED_MODE_VBT)
-static struct sm_obj_form display_group = {
-	.ui_name = "Display",
-	.obj_list = (const struct sm_object *[]) {
-		&display_native_res,
-		NULL
-	},
-};
-#endif
-
 static struct sm_obj_form io_expansion_group = {
 	.ui_name = "I/O / Expansion",
 	.obj_list = (const struct sm_object *[]) {
@@ -156,9 +146,6 @@ static struct sm_obj_form *sm_root[] = {
 	&audio_video_group,
 	&battery_group,
 	&debug_group,
-	#if CONFIG(BOARD_USES_FIXED_MODE_VBT)
-	&display_group,
-	#endif
 	&io_expansion_group,
 	&keyboard_group,
 	&leds_group,
diff --git a/src/mainboard/starlabs/starbook/mainboard.c b/src/mainboard/starlabs/starbook/mainboard.c
index 8916dda296..93982cf807 100644
--- a/src/mainboard/starlabs/starbook/mainboard.c
+++ b/src/mainboard/starlabs/starbook/mainboard.c
@@ -4,7 +4,6 @@
 #include <device/device.h>
 #include <drivers/intel/gma/opregion.h>
 #include <soc/ramstage.h>
-#include <option.h>
 #include <variants.h>
 
 static void starlabs_configure_gpios(void *unused)
@@ -22,8 +21,5 @@ struct chip_operations mainboard_ops = {};
 
 const char *mainboard_vbt_filename(void)
 {
-	if (CONFIG(BOARD_USES_FIXED_MODE_VBT) && get_uint_option("display_native_res", 0) == 1)
-		return "vbt_native_res.bin";
-
 	return "vbt.bin";
 }
diff --git a/src/mainboard/starlabs/starbook/variants/adl_n/Makefile.mk b/src/mainboard/starlabs/starbook/variants/adl_n/Makefile.mk
index bfea7ef255..9abc069b38 100644
--- a/src/mainboard/starlabs/starbook/variants/adl_n/Makefile.mk
+++ b/src/mainboard/starlabs/starbook/variants/adl_n/Makefile.mk
@@ -8,5 +8,3 @@ ramstage-y += devtree.c
 ramstage-y += gpio.c
 ramstage-y += hda_verb.c
 ramstage-y += ramstage.c
-
-$(call add_vbt_to_cbfs, vbt_native_res.bin, data_native_res.vbt)
diff --git a/src/mainboard/starlabs/starbook/variants/adl_n/data.vbt b/src/mainboard/starlabs/starbook/variants/adl_n/data.vbt
index 70c3e07ea6ca12b647ed82e96d25eb46fd38ebe6..0cd0ec4b7773a3710b525f434dbf9050e4800bb7 100644
GIT binary patch
delta 56
xcmZqhXz-XI#oWSRFgcM?c%#7~0Um}1b_NCu76t|rGv>(&!d2*abAs>!0RXc)5I+C_

delta 56
xcmZqhXz-XI#oWwbFgcM?c%#7~0UpK%b_NCu76t|rGv>(&!d2*abAs>!0RXcu5I+C_

diff --git a/src/mainboard/starlabs/starbook/variants/adl_n/data_native_res.vbt b/src/mainboard/starlabs/starbook/variants/adl_n/data_native_res.vbt
deleted file mode 100644
index 0cd0ec4b7773a3710b525f434dbf9050e4800bb7..0000000000000000000000000000000000000000
GIT binary patch
literal 0
HcmV?d00001

literal 9216
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z>x|{_TtxQ_$~hoyP%)VV!atmoh=WQvA_@dM&%=w`<&+5W-MUNf6s;^9O#B~#5HD(#
z^Fd7V&1bdJ7Wcf_T5p8vvtywW&Y!{t9GSQNU(^~Dj#Fva?Z$Cbkn}?CXRh9!;8^g?
zg=nn*%=ze3@L)Okc+*tsr6#5wUnVWI`1n$BPQ9NLMcD<;kT|vq#)(<xYtQ-SVoj3k
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z@?*`Ne?4!;5+27^(uxJ~a0`|l6RUt+5Z47bm1>t!7fY|OawUDq77J;~l^5H~Fo<F>
zHzS{q9NvlQo)$(`6BoR=D2~<m$P0COokU*fIUBn|v>*KpyTh#CeCgjWWk)8rq)BSM
zX`KLaW!wDe=#W#BXRB@QN5T9;1PT!-M4%9XLIesCC`6zTf&VZ9ZJ#T9>D6)EITaJH
zs=~C&_Tk%}{Q5~r7-n3@msOQm4aF%0U53|kf|B4{_mJ2O=An7Ky{^VfG7S~L0<V67
zchmL-rqdL3bhN`=7L)`F*{q#2H)Q2DcaF^bS;$sdh!!BL&XKLmDr9K7VgO~y=FO4a
z?PD}*Ut~RG!j=liEIZ@q@23?;rj{U`I4~<Rb|xV+Pbs)>Te2lv6+E{-I|`XC!6;#0
zVL`e|b800ptvj}m2_Fn?nLIQISwv`qE&n!)OA_(}#Ud^VT<Kwrx*M&saVhH(ws_!s
oJ?{VYId)!q4`brM=W_f=D}^oc-M@_I!^ZDvkRfaZ`oBitFJ`87E&u=k

diff --git a/src/mainboard/starlabs/starbook/variants/mtl/Makefile.mk b/src/mainboard/starlabs/starbook/variants/mtl/Makefile.mk
index bfea7ef255..9abc069b38 100644
--- a/src/mainboard/starlabs/starbook/variants/mtl/Makefile.mk
+++ b/src/mainboard/starlabs/starbook/variants/mtl/Makefile.mk
@@ -8,5 +8,3 @@ ramstage-y += devtree.c
 ramstage-y += gpio.c
 ramstage-y += hda_verb.c
 ramstage-y += ramstage.c
-
-$(call add_vbt_to_cbfs, vbt_native_res.bin, data_native_res.vbt)
diff --git a/src/mainboard/starlabs/starbook/variants/mtl/data.vbt b/src/mainboard/starlabs/starbook/variants/mtl/data.vbt
index 680f2cfe2397cedbc981e3f30c629e8559220d0a..f855dabf240a70571e2c1c25eeae7efd490739cf 100644
GIT binary patch
delta 25
gcmZp$X|S0f#r&JWU~(a&@J0hIK}Lqn(Sl2P0B1}GRsaA1

delta 25
gcmZp$X|S0f#r%uGU~(a&@J0hIK}N>S(Sl2P0B1l4RsaA1

diff --git a/src/mainboard/starlabs/starbook/variants/mtl/data_native_res.vbt b/src/mainboard/starlabs/starbook/variants/mtl/data_native_res.vbt
deleted file mode 100644
index f855dabf240a70571e2c1c25eeae7efd490739cf..0000000000000000000000000000000000000000
GIT binary patch
literal 0
HcmV?d00001

literal 7680
zcmeHMO>7%Q6n?YobzI{Rw+Ylu(=en}aMC8(IBiIyNL}Zzb(=KKPa{`CiksTdK-z>f
zMJYn6fgEx{+6#~tBn%P~3YT0salj`O#3d@?=KxY}R23IQZ*60~ne|VdG^s(Pw3VOr
zc4qdy`R2Vhvomkk`-a<xcyHHGSKmO7|3nuT6d|2Hs<@5odTI~!4UTmBhx{Y$J$)S~
zxW=BPS1VR;5=9u><!aQM^}vPc=(u;FhWAd4j*UkfI-?g~o1U2D!Hxj;pFJBLk4~ML
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z4i`H+yE^)MgMl9ZP@wN5?;GHqfkFS^U{`N@&uJbU=sOl@4-9p67CUoX=$M$iJT>;p
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z+sRE1vVjdSN6o-blpJkBNoW&V8<X-rQ=sQ{klk~y7RFT3PDsGCfYWL$T~C!oR+)e)
zJR^dhjjo5u?WV7HyX9@@DX2h?ah6e}RfE1gC-i<!=@qBP4X5;k6-28%rT14#uf%dM
zL6f<9ax~zTR9NF~C(_VAL9yI%g)w5>{VBatBD>TxbM>UH&^wya6Wu`T#+8!-y|Zie
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z;%Z2FFhab9Q)8%tdt+r81i9A(LF``-Mu_Yp!%x+^XRg^o@HAghWx4<ajcfv;4d?d8
zUg)(n-%q-sPvYDa1TWB0)Lb)Kd0q%JyuaLSxbHz=ra0>JMfjp&W~INp+6c{OZD6KI
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zy(}9{JdZ$#6}8CqAQt(?t6FJ|d0ua+GeULQxljq2s;~hG_Jf~`8iT?yDh<2c$Xf+T
zFXWl$>gf)S1kYTEj-NbpKKcYSEC;vtnoRC*WcK4rWDhND-BskW_mZM0JHQzdsjXmS
z)v`>t^DV`mB=@CMnQrG>I@S<iHl+h|^hY-|0!YtKQ4n??U?0#86~~W7a6{6LH6-qD
zioA(X^c-D7MD;qOxePrXRm;hAARc<zgv~#OL#PE?>A_}fSSI!lxs|SoelmGP&X?G<
zg_X;xcX_b|mt1-7NExPIEQ5`xt&JSMvFh$-MtjFD`0yG!;%y@z)aA=6%EHLm*cGDv
z-><M+%=*oh{_|RPW^!wGNiEl{+#y%?n70nUW3yvFC{Q5+g$NWP@c%@h^)sb{UK&M?
zqL_Fo3eyVPgD=hUdpspzlkqVTSBZHkMj_}jyZ{PHfN$Kz#bz)M&EY#qHD1T;xB)Ei
z%IEkBqRlg%CZVIFpS9N|QnDG1GdE=AHg}H9{FTv+w!%U*4_S4NY<Wf@!>%g^Mqjk~
za%6XU84YU-teZ^OQVE%5XAI;0vdqY|$MH872WDl)&IDxUX$AS2C0n%Zh3D2sa3QnB
z8O60_7Nn~*t5yNi%E^RG_-ELc$V2^*MT9nZ^SC4+-&ZW+5=ROMYt)_Sm5obTr?ABX
p-|LVs*5%lF?QP771ApS+NA^<KBEK@pdDv|Jo&*`fR-mnpz~6Yui7o&D

diff --git a/src/mainboard/starlabs/starfighter/cfr.c b/src/mainboard/starlabs/starfighter/cfr.c
index 6cdd98b189..2d3c6c3967 100644
--- a/src/mainboard/starlabs/starfighter/cfr.c
+++ b/src/mainboard/starlabs/starfighter/cfr.c
@@ -28,14 +28,6 @@ static struct sm_obj_form debug_group = {
 	},
 };
 
-static struct sm_obj_form display_group = {
-	.ui_name = "Display",
-	.obj_list = (const struct sm_object *[]) {
-		&display_native_res,
-		NULL
-	},
-};
-
 #if CONFIG(DRIVERS_INTEL_USB4_RETIMER)
 static struct sm_obj_form io_expansion_group = {
 	.ui_name = "I/O / Expansion",
@@ -138,7 +130,6 @@ static struct sm_obj_form wireless_group = {
 static struct sm_obj_form *sm_root[] = {
 	&battery_group,
 	&debug_group,
-	&display_group,
 	#if CONFIG(DRIVERS_INTEL_USB4_RETIMER)
 	&io_expansion_group,
 	#endif
diff --git a/src/mainboard/starlabs/starfighter/variants/mtl/Makefile.mk b/src/mainboard/starlabs/starfighter/variants/mtl/Makefile.mk
index c32caa48e9..93240a1307 100644
--- a/src/mainboard/starlabs/starfighter/variants/mtl/Makefile.mk
+++ b/src/mainboard/starlabs/starfighter/variants/mtl/Makefile.mk
@@ -10,6 +10,4 @@ ramstage-y += devtree.c
 ramstage-y += gpio.c
 ramstage-y += hda_verb.c
 ramstage-y += ramstage.c
-
-$(call add_vbt_to_cbfs, vbt_native_res.bin, data_native_res.vbt)
 $(call add_vbt_to_cbfs, vbt_qhd.bin, data_qhd.vbt)
diff --git a/src/mainboard/starlabs/starfighter/variants/mtl/data.vbt b/src/mainboard/starlabs/starfighter/variants/mtl/data.vbt
index af525583dddaf60d143a663e70787402123461a5..cd70aad5d9189f370421e197dac094e155763603 100644
GIT binary patch
delta 25
gcmZp$X|S0f#oWwbFu9OXc%y-qAS1)(Xu+jC0AAb%-T(jq

delta 25
gcmZp$X|S0f#oWYTFu9OXc%y-qAS2`EXu+jC0AA1r-T(jq

diff --git a/src/mainboard/starlabs/starfighter/variants/mtl/data_native_res.vbt b/src/mainboard/starlabs/starfighter/variants/mtl/data_native_res.vbt
deleted file mode 100644
index cd70aad5d9189f370421e197dac094e155763603..0000000000000000000000000000000000000000
GIT binary patch
literal 0
HcmV?d00001

literal 7680
zcmeHMO>7%Q6n?YobzI{Rw+Ylu(=en}aMC8(IBiIyNL}Zzb(=KKPa{`CiksTdK-z>f
zMJYn6p*iG&v=<;PNEjp}6fU`N;($*mh)Yz&&jF;|s46aq-e_aKne|VdG^s(Pw3VOr
zc4qdy`R2Vhvomkk`-a<xcyHHGSKmO7|3nuT6d|2HthkEndTI~!4UTmBhx{Y$J$)S~
zxW=BPS1VR;5k(l=<!aQM^}vPc=(u;FhWAd4j*UkfI-?g~o1U2D!Hxj;pFJBLk4~ML
zjz;+4@KHY(c*V~4OJm~^e)7`!(dbkwZ`5@i+Pv{#ebYhCeJ?iXO$|Q1@em}fjm@ox
z4i`H+yE^)MgMl9ZP@wN5?;GHqfkFS^U{`N@&uJbU=sOl@4-9p67CUoX=$M$iJT>;p
zxoPh0sNp`0Qzvny$-HA?YO<dD$H)1A(7DJ5q8Fo6Z$u;Y#ZCc~Acu_+F(;KI2o*th
z+sRE1vVjdSN6o-blpJkBNoW&V8<X-LQ=sQ{klk~y7RFT3PDsGCfYWL$T~C!oR+)e)
zJR^dhjc$a=?WV7GyX9@@DX2h?ah6e}RfE1cC-i<w=@qBP4X5;k6-28%rT1q_uf%dM
zL6f<9ax~zTR9NF~C(_VAL9yI%g)w5>{VBatBD>TxbM>UH&^wya6Wu`T#+8!-y|Zie
zDAzvOJCDnqH=&dY6eA{x=ox0L>-vMbwC-M1bJ7I(GWaU^UGN9sPrzS*zXX2`{ucZ_
z_*d|6;6K2Bfwx64wjw5M%dSa~^E=8sBgtgii^sL*Dy8Fi<Wxu7Y=!jY6jAcyvIVkR
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zin2Frhqaip!eZN>mgk>i%7v#eq_|{xo4HYHB`;7i`Qx^j$yfHc9pNggcV+VxoDZVz
z;%Z2FFhab9Q)8%tdt+r81i9A(LF``-Mu_Yp!%x+^XRg^o@HAghWx4<ajcfv;4d?d8
zUg)(n-%q-sPvYDa1TWB0)Lb)Kd0q%JyuaLSxbHz=ra0>JMfkj7W~INp+6c{OZD6KI
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zioA(X^c-D7MD;qOxePrXRm;hAARc<zgv~#OLue6O>A_}fSSI!lxs|SoelmGP&X?G<
zg_X;xcX_b|mt1-7NExPIEQ5`xt&JSMvFh$-MtjFD`0yG!;%y@z)aA=6%EHLm*cGDv
z-><OS%=*oh{_|RPW^!wGNi8?5+#y%?n70nUW3yvFC{Q5+g$NWP@c%@h^;4ySUK&M?
zqL_Fo3eyVPgD=hUdpspzlkpJ|SBZHkMj_}jyZ{PHfN$Q##bz)M&EY#qHD1T;xB)Ei
z%4hfrqRlg%CZVIFpS9N|QnDG1GdE=AHg}H9{Dsksw!%U*4_S4NY<Wf@!>%g^Mqjk~
za%6XU84YU-teZ^OQVE%5XAI;0yv)e7$MH872WDl)&IDxUX$AS2C0n%Zh3D2sa3QnB
z8O60_7Nl!5t5yNi%E^RG_-ELc$V2^*MT9nZ^SC4+-&ZW+5=ROMYt)_Sm5obTr?ABX
q-|MKwR+nSv^|vu64*ZFOAK6P`i~PzY=V7z?dlF;_TY<JZ0)GQv`H3z7

diff --git a/src/mainboard/starlabs/starfighter/variants/mtl/ramstage.c b/src/mainboard/starlabs/starfighter/variants/mtl/ramstage.c
index b58fda0204..269878c746 100644
--- a/src/mainboard/starlabs/starfighter/variants/mtl/ramstage.c
+++ b/src/mainboard/starlabs/starfighter/variants/mtl/ramstage.c
@@ -1,6 +1,5 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
-#include <option.h>
 #include <drivers/intel/gma/opregion.h>
 #include <soc/ramstage.h>
 #include <variants.h>
@@ -14,10 +13,6 @@ void mainboard_silicon_init_params(FSP_S_CONFIG *supd)
 
 const char *mainboard_vbt_filename(void)
 {
-	if (get_uint_option("display_native_res", 0) == 1)
-		return "vbt_native_res.bin";
-
-
 	if (get_memory_config_straps() == 13)
 		return "vbt_qhd.bin";
 	return "vbt.bin";
diff --git a/src/mainboard/starlabs/starfighter/variants/rpl/Makefile.mk b/src/mainboard/starlabs/starfighter/variants/rpl/Makefile.mk
index bfea7ef255..9abc069b38 100644
--- a/src/mainboard/starlabs/starfighter/variants/rpl/Makefile.mk
+++ b/src/mainboard/starlabs/starfighter/variants/rpl/Makefile.mk
@@ -8,5 +8,3 @@ ramstage-y += devtree.c
 ramstage-y += gpio.c
 ramstage-y += hda_verb.c
 ramstage-y += ramstage.c
-
-$(call add_vbt_to_cbfs, vbt_native_res.bin, data_native_res.vbt)
diff --git a/src/mainboard/starlabs/starfighter/variants/rpl/data.vbt b/src/mainboard/starlabs/starfighter/variants/rpl/data.vbt
index 9377482170c89d789297f36e23526eae38141a2c..b0222677f63a502e639ba65c929273bee5409d70 100644
GIT binary patch
delta 56
xcmZqhXz-XI#mvNDFu9OXc%#7~0Um}1b_RwGEDQ`LX3Uclgsaf;<^<sd0syQi5Jdn0

delta 56
xcmZqhXz-XI#mvZHFu9OXc%#7~0UpK%b_RwGEDQ`LX3Uclgsaf;<^<sd0syQW5Jdn0

diff --git a/src/mainboard/starlabs/starfighter/variants/rpl/data_native_res.vbt b/src/mainboard/starlabs/starfighter/variants/rpl/data_native_res.vbt
deleted file mode 100644
index b0222677f63a502e639ba65c929273bee5409d70..0000000000000000000000000000000000000000
GIT binary patch
literal 0
HcmV?d00001

literal 9216
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zfmc-#T4($4ZBKsvq!b*}Kf{+*l~@BMC=6YO*K&eV;G1{xu;|Q9i+FookC$XNRKON^
z{VTkiwk|P^W}u^?9qzKA6j;dSt(>_atG2ibWX8`zw$8$|1X+E7Y;9g4-KHrztgKkP
z1+qH>jK;0Ytd9)%QUjUkX9E5Gw8qG=B}pR=n>9H<Q;->_6x_E>*@~qOk(-|#h0Ky<
zl(ep~5M7}KwH7wbJGPLC7<AhzxoH@(sL%$R@oj}m3i1Qx0+%GN^zcUAjaGSFssh3n
rH)3z54oh=^pI6_<nAq_h96z#E!Wa4OU*h?o@p~F%fUQLTR|Nh7ydZZj

diff --git a/src/mainboard/starlabs/starfighter/variants/rpl/ramstage.c b/src/mainboard/starlabs/starfighter/variants/rpl/ramstage.c
index d17549ec3a..6e4471589e 100644
--- a/src/mainboard/starlabs/starfighter/variants/rpl/ramstage.c
+++ b/src/mainboard/starlabs/starfighter/variants/rpl/ramstage.c
@@ -15,8 +15,5 @@ void mainboard_silicon_init_params(FSP_S_CONFIG *supd)
 
 const char *mainboard_vbt_filename(void)
 {
-	if (get_uint_option("display_native_res", 0) == 1)
-		return "vbt_native_res.bin";
-
 	return "vbt.bin";
 }

From 1d17c9522fb342acc46da12b84591b736db388ef Mon Sep 17 00:00:00 2001
From: Eren Peng <peng.eren@inventec.corp-partner.google.com>
Date: Wed, 11 Mar 2026 13:52:42 +0800
Subject: [PATCH 3669/3886] mb/google/trulo/var/kaladin: Add LGD touchscreen

Add LGD touchscreen for kaladin

BUG=b:484114852
TEST=build and flash on kaladin,verify touch function works normally

Change-Id: I1f204569767e7eab17bc44dcd060d606ba87a38e
Signed-off-by: Eren Peng <peng.eren@inventec.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91647
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
---
 .../brya/variants/kaladin/overridetree.cb     | 21 ++++++++++++++++++-
 1 file changed, 20 insertions(+), 1 deletion(-)

diff --git a/src/mainboard/google/brya/variants/kaladin/overridetree.cb b/src/mainboard/google/brya/variants/kaladin/overridetree.cb
index 8f7f8e2be5..226b4f41bc 100644
--- a/src/mainboard/google/brya/variants/kaladin/overridetree.cb
+++ b/src/mainboard/google/brya/variants/kaladin/overridetree.cb
@@ -11,11 +11,12 @@ fw_config
 		option MB_USB_1C_1A 0
 		option MB_USB_2C_1A 1
 	end
-	field TOUCH_PANEL 4 5
+	field TOUCH_PANEL 4 8
 		option TOUCH_ELAN_TOP   	0
 		option TOUCH_ELAN_DBTS  	1
 		option TOUCH_GTH1563_TOP	2
 		option TOUCH_GTH7503_TOP	3
+		option TOUCH_LXST2024_TOP	4
 	end
 	field WIFI_SAR 13 15
 		option WIFI_SAR_ID_0 0
@@ -600,6 +601,24 @@ chip soc/intel/alderlake
 					probe TOUCH_PANEL TOUCH_ELAN_DBTS
 				end
 			end
+			chip drivers/i2c/hid
+				register "generic.hid" = ""LXST2024""
+				register "generic.desc" = ""LGD Touchscreen""
+				register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_E11_IRQ)"
+				register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C1)"
+				register "generic.reset_delay_ms" = "20"
+				register "generic.reset_off_delay_ms" = "2"
+				register "generic.stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C4)"
+				register "generic.stop_delay_ms" = "280"
+				register "generic.stop_off_delay_ms" = "2"
+				register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C0)"
+				register "generic.enable_delay_ms" = "1"
+				register "generic.has_power_resource" = "1"
+				register "hid_desc_reg_offset" = "0x01"
+				device i2c 10 on
+					probe TOUCH_PANEL TOUCH_LXST2024_TOP
+				end
+			end
 		end #I2C1
 		device ref i2c5 on
 			chip drivers/i2c/generic

From 2107e48c09f80d17ce0b47124139c5ab36c046b7 Mon Sep 17 00:00:00 2001
From: Qinghong Zeng <zengqinghong@huaqin.corp-partner.google.com>
Date: Mon, 2 Mar 2026 21:00:49 +0800
Subject: [PATCH 3670/3886] mb/google/nissa/var/telith: Generate RAM ID for
 BWMYAX32P8A-32G

Generate RAM ID for BWMYAX32P8A-32G

DRAM Part Name                 ID to assign
BWMYAX32P8A-32G                4 (0100)

BUG=b:488993502
BRANCH=firmware-nissa-15217.B
TEST=emerge-nissa coreboot

Change-Id: I496292fa20884262c32d339b8448490f09c7b12b
Signed-off-by: Qinghong Zeng <zengqinghong@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91508
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kun Liu <liukun11@huaqin.corp-partner.google.com>
---
 src/mainboard/google/brya/variants/telith/memory/Makefile.mk    | 2 +-
 .../google/brya/variants/telith/memory/dram_id.generated.txt    | 1 +
 .../google/brya/variants/telith/memory/mem_parts_used.txt       | 1 +
 3 files changed, 3 insertions(+), 1 deletion(-)

diff --git a/src/mainboard/google/brya/variants/telith/memory/Makefile.mk b/src/mainboard/google/brya/variants/telith/memory/Makefile.mk
index 948e9947b6..853671baac 100644
--- a/src/mainboard/google/brya/variants/telith/memory/Makefile.mk
+++ b/src/mainboard/google/brya/variants/telith/memory/Makefile.mk
@@ -8,7 +8,7 @@ SPD_SOURCES += spd/lp5/set-0/spd-1.hex      # ID = 0(0b0000)  Parts = MT62F512M3
 SPD_SOURCES += spd/lp5/set-0/spd-2.hex      # ID = 1(0b0001)  Parts = H9JCNNNCP3MLYR-N6E, MT62F1G32D4DR-031 WT:B
 SPD_SOURCES += spd/lp5/set-0/spd-4.hex      # ID = 2(0b0010)  Parts = H9JCNNNFA5MLYR-N6E, MT62F2G32D8DR-031 WT:B
 SPD_SOURCES += spd/lp5/set-0/spd-9.hex      # ID = 3(0b0011)  Parts = K3KL6L60GM-MGCT
-SPD_SOURCES += spd/lp5/set-0/spd-7.hex      # ID = 4(0b0100)  Parts = MT62F1G32D2DS-026 WT:B, K3KL8L80CM-MGCT, H58G56BK7BX068
+SPD_SOURCES += spd/lp5/set-0/spd-7.hex      # ID = 4(0b0100)  Parts = MT62F1G32D2DS-026 WT:B, K3KL8L80CM-MGCT, H58G56BK7BX068, BWMYAX32P8A-32G
 SPD_SOURCES += spd/lp5/set-0/spd-8.hex      # ID = 5(0b0101)  Parts = MT62F2G32D4DS-026 WT:B, K3KL9L90CM-MGCT, H58G66BK7BX067
 SPD_SOURCES += spd/lp5/set-0/spd-11.hex      # ID = 6(0b0110)  Parts = H58G56CK8BX146
 SPD_SOURCES += spd/lp5/set-0/spd-10.hex      # ID = 7(0b0111)  Parts = H58G66CK8BX147
diff --git a/src/mainboard/google/brya/variants/telith/memory/dram_id.generated.txt b/src/mainboard/google/brya/variants/telith/memory/dram_id.generated.txt
index 2eb20d169e..68925705ec 100644
--- a/src/mainboard/google/brya/variants/telith/memory/dram_id.generated.txt
+++ b/src/mainboard/google/brya/variants/telith/memory/dram_id.generated.txt
@@ -19,3 +19,4 @@ K3KL9L90CM-MGCT                5 (0101)
 H58G66BK7BX067                 5 (0101)
 H58G56CK8BX146                 6 (0110)
 H58G66CK8BX147                 7 (0111)
+BWMYAX32P8A-32G                4 (0100)
diff --git a/src/mainboard/google/brya/variants/telith/memory/mem_parts_used.txt b/src/mainboard/google/brya/variants/telith/memory/mem_parts_used.txt
index 4566426d26..ee4f2685c8 100644
--- a/src/mainboard/google/brya/variants/telith/memory/mem_parts_used.txt
+++ b/src/mainboard/google/brya/variants/telith/memory/mem_parts_used.txt
@@ -24,3 +24,4 @@ K3KL9L90CM-MGCT
 H58G66BK7BX067
 H58G56CK8BX146
 H58G66CK8BX147
+BWMYAX32P8A-32G

From 5e8cf4184506b0858a126e8e869be23610be650e Mon Sep 17 00:00:00 2001
From: KangMin Wang <kangmin.wang@luxshare.corp-partner.google.com>
Date: Tue, 10 Mar 2026 14:39:56 +0800
Subject: [PATCH 3671/3886] mb/google/bluey/mica: Add MAINBOARD_NO_USB_A_PORT
 configuration

Since USB-A was removed from the mica hardware design, the Kconfig has
been configured to skip the relevant initialization.

BUG=b:488906616
TEST=emerge-bluey coreboot

Change-Id: I69cc994c83d78da87ddb95cbf471726a492512ef
Signed-off-by: KangMin Wang <kangmin.wang@luxshare.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91635
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Derek Huang <derekhuang@google.com>
---
 src/mainboard/google/bluey/Kconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/src/mainboard/google/bluey/Kconfig b/src/mainboard/google/bluey/Kconfig
index 9fe281bca9..9d7a5df5a9 100644
--- a/src/mainboard/google/bluey/Kconfig
+++ b/src/mainboard/google/bluey/Kconfig
@@ -75,6 +75,7 @@ config BOARD_GOOGLE_MODEL_MICA
 config BOARD_GOOGLE_MICA
 	select BOARD_GOOGLE_MODEL_MICA
 	select MAINBOARD_HAS_PS8820_RETIMER
+	select MAINBOARD_NO_USB_A_PORT
 	select SOC_QUALCOMM_HAMOA
 
 if BOARD_GOOGLE_BLUEY_COMMON

From bd2c7443f300b81811308d48a0a8fcb28c374f3a Mon Sep 17 00:00:00 2001
From: Cliff Huang <cliff.huang@intel.com>
Date: Sun, 1 Mar 2026 00:23:03 -0800
Subject: [PATCH 3672/3886] soc/intel/ptl: Add ISCLK for controlling PCIe clock
 source
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Add two functions for disabling/enabling PCIe clocks to devices
connected to root ports. These functions are used during device power
sequencing at boot to ensure clocks are not driven to devices when
their power is off. This prevents potential issues with PCIe link
training and ensures proper power-on sequencing for connected devices.

BUG=none
TEST=Build and boot Panther Lake platform. Verify PCIe devices enumerate
correctly and clock management functions properly during power sequences

Signed-off-by: Cliff Huang <cliff.huang@intel.com>
Change-Id: I63f8e331b6ab18172fa32ff5c1539c71823aa247
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91550
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/soc/intel/pantherlake/Makefile.mk         |  1 +
 src/soc/intel/pantherlake/include/soc/isclk.h | 14 +++++++++++++
 src/soc/intel/pantherlake/isclk.c             | 20 +++++++++++++++++++
 3 files changed, 35 insertions(+)
 create mode 100644 src/soc/intel/pantherlake/include/soc/isclk.h
 create mode 100644 src/soc/intel/pantherlake/isclk.c

diff --git a/src/soc/intel/pantherlake/Makefile.mk b/src/soc/intel/pantherlake/Makefile.mk
index b7ea31b1f6..24ef2e9d27 100644
--- a/src/soc/intel/pantherlake/Makefile.mk
+++ b/src/soc/intel/pantherlake/Makefile.mk
@@ -8,6 +8,7 @@ subdirs-y += ../../../cpu/intel/turbo
 
 # all (bootblock, verstage, romstage, postcar, ramstage)
 all-y += gpio.c
+all-y += isclk.c
 
 bootblock-y += bootblock/bootblock.c
 bootblock-y += bootblock/pcd.c
diff --git a/src/soc/intel/pantherlake/include/soc/isclk.h b/src/soc/intel/pantherlake/include/soc/isclk.h
new file mode 100644
index 0000000000..dfa072eb5a
--- /dev/null
+++ b/src/soc/intel/pantherlake/include/soc/isclk.h
@@ -0,0 +1,14 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#ifndef _SOC_PANTHERLAKE_ISCLK_H_
+#define _SOC_PANTHERLAKE_ISCLK_H_
+
+#include <types.h>
+
+/* Disable PCIe clock source; clock_number: 0-based */
+void soc_disable_pcie_clock_out(size_t clock_number);
+
+/* Enable PCIe clock source; clock_number: 0-based */
+void soc_enable_pcie_clock_out(size_t clock_number);
+
+#endif /* _SOC_PANTHERLAKE_ISCLK_H_ */
diff --git a/src/soc/intel/pantherlake/isclk.c b/src/soc/intel/pantherlake/isclk.c
new file mode 100644
index 0000000000..649dcc843b
--- /dev/null
+++ b/src/soc/intel/pantherlake/isclk.c
@@ -0,0 +1,20 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <intelblocks/pcr.h>
+#include <soc/iomap.h>
+#include <soc/isclk.h>
+#include <soc/pcr_ids.h>
+
+#define ISCLK_PCR_BIOS_BUFFEN_H 0x8080
+
+/* Disable PCIe clock source; clock_number: 0-based */
+void soc_disable_pcie_clock_out(size_t clock_number)
+{
+	pcr_rmw32(PID_ISCLK, ISCLK_PCR_BIOS_BUFFEN_H, ~BIT(clock_number), 0);
+}
+
+/* Enable PCIe clock source; clock_number: 0-based */
+void soc_enable_pcie_clock_out(size_t clock_number)
+{
+	pcr_or32(PID_ISCLK, ISCLK_PCR_BIOS_BUFFEN_H, BIT(clock_number));
+}

From 5458b34de68174567e8141390e5cd7e61a7a9bb3 Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Sun, 19 Oct 2025 19:48:44 +0100
Subject: [PATCH 3673/3886] soc/intel/meteorlake: Use Arrow Lake FSP

The FSP for Arrow Lake supports Meteor Lake, so re-point coreboot
at that, as it's, simply, newer and better.

Change-Id: I524dc7c0632c9f38b178ad95563128b56f94f983
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89639
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
---
 src/soc/intel/meteorlake/Kconfig | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/soc/intel/meteorlake/Kconfig b/src/soc/intel/meteorlake/Kconfig
index e5abfc0762..0fa2facbe7 100644
--- a/src/soc/intel/meteorlake/Kconfig
+++ b/src/soc/intel/meteorlake/Kconfig
@@ -367,14 +367,14 @@ config FSP_TYPE_IOT
 
 config FSP_HEADER_PATH
 	string "Location of FSP headers"
-	default "3rdparty/fsp/MeteorLakeFspBinPkg/IoT/MeteorLake/Include" if FSP_USE_REPO && FSP_TYPE_IOT
+	default "3rdparty/fsp/ArrowLakeFspBinPkg/IoT/ArrowLakeUH/Include" if FSP_USE_REPO && FSP_TYPE_IOT
 	default "src/vendorcode/intel/fsp/fsp2_0/meteorlake/x86_64/" if HAVE_X86_64_SUPPORT
 	default "src/vendorcode/intel/fsp/fsp2_0/meteorlake/x86_32/"
 
 config FSP_FD_PATH
 	string
 	depends on FSP_USE_REPO
-	default "3rdparty/fsp/MeteorLakeFspBinPkg/IoT/MeteorLake/Fsp.fd" if FSP_TYPE_IOT
+	default "3rdparty/fsp/ArrowLakeFspBinPkg/IoT/ArrowLakeUH/Fsp.fd" if FSP_TYPE_IOT
 	default "3rdparty/fsp/MeteorLakeFspBinPkg/Fsp.fd"
 
 # Override platform debug consent value:

From 6ce607eee4b33298e1750dedc86828baf8c6b07d Mon Sep 17 00:00:00 2001
From: Arthur Heymans <arthur@aheymans.xyz>
Date: Wed, 11 Mar 2026 12:57:45 +0100
Subject: [PATCH 3674/3886] mb/emu/qemu-sbsa: Add missing PCIe ACPI methods

Linux complains about these missing.

Tested with fedora 43 and CrabEFI payload.

Change-Id: I4c65760e64d8dc9b953f6a5b7f1bdcde0ce946a0
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91649
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/emulation/qemu-sbsa/dsdt.asl | 21 ++++++++++++++-------
 1 file changed, 14 insertions(+), 7 deletions(-)

diff --git a/src/mainboard/emulation/qemu-sbsa/dsdt.asl b/src/mainboard/emulation/qemu-sbsa/dsdt.asl
index 8280cb7431..3b38adb6fc 100644
--- a/src/mainboard/emulation/qemu-sbsa/dsdt.asl
+++ b/src/mainboard/emulation/qemu-sbsa/dsdt.asl
@@ -1,12 +1,19 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
-#define LINK_DEVICE(Uid, LinkName, Irq)                                                    \
-	Device (LinkName) {                                                                \
-		Name (_HID, EISAID("PNP0C0F"))                                             \
-		Name (_UID, Uid)                                                           \
-		Name (_CRS, ResourceTemplate() {                                           \
-			Interrupt (ResourceProducer, Level, ActiveHigh, Exclusive) { Irq } \
-		})                                                                         \
+#define LINK_DEVICE(Uid, LinkName, Irq)                                                     \
+	Device (LinkName) {                                                                 \
+		Name (_HID, EISAID("PNP0C0F"))                                              \
+		Name (_UID, Uid)                                                            \
+		Name (_PRS, ResourceTemplate() {                                            \
+			Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive) { Irq }  \
+		})                                                                          \
+		Name (_CRS, ResourceTemplate() {                                            \
+			Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive) { Irq }  \
+		})                                                                          \
+		Method (_SRS, 1, NotSerialized) {                                           \
+		}                                                                           \
+		Method (_DIS, 0, NotSerialized) {                                           \
+		}                                                                           \
 	}
 
 #define USB_PORT(PortName, Adr)                                                 \

From 39017d2257c1d0316f31f751013dddbd591ba924 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Micha=C5=82=20=C5=BBygowski?= <michal.zygowski@3mdeb.com>
Date: Tue, 9 Sep 2025 10:06:52 +0200
Subject: [PATCH 3675/3886] amd/microcode: Add API to obtain address on
 microcode update block
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Expose API to return the microcode update block address. It will be
used to provide a pointer to microcode update to the OpenSIL.

Change-Id: I1a5a89a5ff2ed29621e856cf274434803005aff8
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89108
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/include/cpu/amd/microcode.h                 | 1 +
 src/soc/amd/common/block/cpu/update_microcode.c | 7 +++++++
 2 files changed, 8 insertions(+)

diff --git a/src/include/cpu/amd/microcode.h b/src/include/cpu/amd/microcode.h
index 96cac59db9..3adce94db6 100644
--- a/src/include/cpu/amd/microcode.h
+++ b/src/include/cpu/amd/microcode.h
@@ -7,5 +7,6 @@ void amd_update_microcode_from_cbfs(void);
 void amd_load_microcode_from_cbfs(void);
 void amd_free_microcode(void);
 void amd_apply_microcode_patch(void);
+void *amd_microcode_find(void);
 
 #endif /* CPU_AMD_MICROCODE_H */
diff --git a/src/soc/amd/common/block/cpu/update_microcode.c b/src/soc/amd/common/block/cpu/update_microcode.c
index e80339bd5f..95ba79c75c 100644
--- a/src/soc/amd/common/block/cpu/update_microcode.c
+++ b/src/soc/amd/common/block/cpu/update_microcode.c
@@ -119,3 +119,10 @@ void amd_free_microcode(void)
 		ucode = NULL;
 	}
 }
+
+void *amd_microcode_find(void)
+{
+	amd_load_microcode_from_cbfs();
+
+	return (void *)ucode;
+}

From 88eea9da6d71c28f6a6ee8a3876367c0f5acf426 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Micha=C5=82=20=C5=BBygowski?= <michal.zygowski@3mdeb.com>
Date: Tue, 9 Sep 2025 10:35:48 +0200
Subject: [PATCH 3676/3886] vendorcode/amd/opensil/turin_poc: Pass microcode
 pointer to OpenSIL
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Use the new API to pass the microcode update pointer to the OpenSIL
so that OpenSIL can update microcode on all cores/threads during CCX
initialization.

TEST=See microcode is updated on BSP in OpenSIL on Gigabyte MZ33-AR1.

Change-Id: Ic35784583a1494ea162dc4a0d2fea8c9c3e1ef5f
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89109
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
---
 src/vendorcode/amd/opensil/turin_poc/ramstage.c | 12 ++++++++++++
 1 file changed, 12 insertions(+)

diff --git a/src/vendorcode/amd/opensil/turin_poc/ramstage.c b/src/vendorcode/amd/opensil/turin_poc/ramstage.c
index f206ef5f58..27bc22e539 100644
--- a/src/vendorcode/amd/opensil/turin_poc/ramstage.c
+++ b/src/vendorcode/amd/opensil/turin_poc/ramstage.c
@@ -15,6 +15,7 @@
 #include <amdblocks/reset.h>
 #include <bootstate.h>
 #include <cbmem.h>
+#include <cpu/amd/microcode.h>
 #include <cpu/cpu.h>
 #include <cpu/x86/smm.h>
 #include <device/device.h>
@@ -293,6 +294,8 @@ static void configure_sdxi(void)
 static void configure_ccx(void)
 {
 	CCXCLASS_DATA_BLK *ccx_data = SilFindStructure(SilId_CcxClass, 0);
+	UCODEPATCH_BIOSENTRYINFO *ucode_info;
+	void *ucode;
 
 	if (CONFIG(XAPIC_ONLY) || CONFIG(X2APIC_LATE_WORKAROUND))
 		ccx_data->CcxInputBlock.AmdApicMode = xApicMode;
@@ -305,6 +308,15 @@ static void configure_ccx(void)
 	ccx_data->CcxInputBlock.EnableSvmX2AVIC = 1;
 	ccx_data->CcxInputBlock.EnableSvmAVIC = true;
 	ccx_data->CcxInputBlock.AmdCStateIoBaseAddress = ACPI_CSTATE_CONTROL;
+
+	ucode = amd_microcode_find();
+	if (!ucode) {
+		printk(BIOS_ERR, "OpenSIL: CPU microcode not found\n");
+		return;
+	}
+
+	ucode_info = &ccx_data->CcxInputBlock.UcodePatchEntryInfo;
+	ucode_info->UcodePatchEntryAddress = (uint64_t)ucode;
 }
 
 void setup_opensil(void)

From 3249ad1d7f28efa58653304355d624644dbce904 Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Thu, 5 Mar 2026 10:50:09 -0600
Subject: [PATCH 3677/3886] mb/google/rex: Add SOF chip driver to screebo,
 kanix, karis

screebo/kanix use rt1019 speaker, rt5682 headphone. karis uses rt5650
speaker and rt5650_hp headphone. All of them use 2ch-pdm0 for dmic.

This configuration is used for CoolStar's Windows audio drivers on
these devices.

TEST=build/boot Win11 on screebo, verify built-in audio functional with
coolstar's drivers.

Change-Id: Ie0be2b2d7cc41548bbe3e5b47a8e0f6039c4b2d9
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91571
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jakub "Kuba" Czapiga <czapiga@google.com>
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
---
 src/mainboard/google/rex/Kconfig                         | 3 +++
 src/mainboard/google/rex/variants/kanix/overridetree.cb  | 9 ++++++++-
 src/mainboard/google/rex/variants/karis/overridetree.cb  | 9 ++++++++-
 .../google/rex/variants/screebo/overridetree.cb          | 6 ++++++
 4 files changed, 25 insertions(+), 2 deletions(-)

diff --git a/src/mainboard/google/rex/Kconfig b/src/mainboard/google/rex/Kconfig
index b5f8858033..2ff9a04102 100644
--- a/src/mainboard/google/rex/Kconfig
+++ b/src/mainboard/google/rex/Kconfig
@@ -73,6 +73,7 @@ config BOARD_GOOGLE_MODEL_DEKU
 config BOARD_GOOGLE_MODEL_KANIX
 	def_bool n
 	select BOARD_GOOGLE_BASEBOARD_REX
+	select DRIVERS_AUDIO_SOF
 	select DRIVERS_GENERIC_ALC1015
 	select MAINBOARD_HAS_GOOGLE_STRAUSS_KEYBOARD
 	select RT8168_GEN_ACPI_POWER_RESOURCE
@@ -85,6 +86,7 @@ config BOARD_GOOGLE_MODEL_KANIX
 config BOARD_GOOGLE_MODEL_KARIS
 	def_bool n
 	select BOARD_GOOGLE_BASEBOARD_REX
+	select DRIVERS_AUDIO_SOF
 	select SOC_INTEL_CSE_LITE_SKU
 	select SOC_INTEL_CSE_PRE_CPU_RESET_TELEMETRY_V2
 	select SOC_INTEL_CSE_SEND_EOP_ASYNC
@@ -116,6 +118,7 @@ config BOARD_GOOGLE_MODEL_REX_EC_ISH
 config BOARD_GOOGLE_MODEL_SCREEBO
 	def_bool n
 	select BOARD_GOOGLE_BASEBOARD_REX
+	select DRIVERS_AUDIO_SOF
 	select DRIVERS_GENERIC_ALC1015
 	select DRIVERS_GENESYSLOGIC_GL9750
 	select SOC_INTEL_CSE_LITE_SKU
diff --git a/src/mainboard/google/rex/variants/kanix/overridetree.cb b/src/mainboard/google/rex/variants/kanix/overridetree.cb
index 37f3d7ca0a..c9b28c1aeb 100644
--- a/src/mainboard/google/rex/variants/kanix/overridetree.cb
+++ b/src/mainboard/google/rex/variants/kanix/overridetree.cb
@@ -664,6 +664,13 @@ chip soc/intel/meteorlake
 				end
 			end
 		end
-		device ref hda on end
+		device ref hda on
+			chip drivers/sof
+				register "spkr_tplg" = "rt1019"
+				register "jack_tplg" = "rt5682"
+				register "mic_tplg" = "_2ch_pdm0"
+				device generic 0 on end
+			end
+		end
 	end
 end
diff --git a/src/mainboard/google/rex/variants/karis/overridetree.cb b/src/mainboard/google/rex/variants/karis/overridetree.cb
index c24c7c7cd7..18a647bb2f 100644
--- a/src/mainboard/google/rex/variants/karis/overridetree.cb
+++ b/src/mainboard/google/rex/variants/karis/overridetree.cb
@@ -604,6 +604,13 @@ chip soc/intel/meteorlake
 				end
 			end
 		end
-		device ref hda on end
+		device ref hda on
+			chip drivers/sof
+				register "spkr_tplg" = "rt5650_sp"
+				register "jack_tplg" = "rt5650_hp"
+				register "mic_tplg" = "_2ch_pdm0"
+				device generic 0 on end
+			end
+		end
 	end
 end
diff --git a/src/mainboard/google/rex/variants/screebo/overridetree.cb b/src/mainboard/google/rex/variants/screebo/overridetree.cb
index 60d28bcaa5..6e117bbe6e 100644
--- a/src/mainboard/google/rex/variants/screebo/overridetree.cb
+++ b/src/mainboard/google/rex/variants/screebo/overridetree.cb
@@ -632,6 +632,12 @@ chip soc/intel/meteorlake
 					probe AUDIO ALC1019_ALC5682I_I2S
 				end
 			end
+			chip drivers/sof
+				register "spkr_tplg" = "rt1019"
+				register "jack_tplg" = "rt5682"
+				register "mic_tplg" = "_2ch_pdm0"
+				device generic 0 on end
+			end
 		end
 	end
 end

From 9a8d22dcaae414c5d6bb556c80a1251177ca3830 Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Tue, 28 Oct 2025 20:20:23 +0000
Subject: [PATCH 3678/3886] util/spd_tools: Improve spd_gen CLI for Make

Add options that simplify integrating spd_gen into build systems:
- Allow choosing an output directory via -out/--out.
- Allow writing a single SPD hex file from a single-part JSON input.
- Accept either {name, attribs/attributes} or a single-part
  memory_parts.json.
- Strip // and /* */ comments from JSON inputs.
- Allow selecting the SPD set number for single-file output via
  -set/--set (default: 0).

The set number selects which set-N attributes are used when generating a
single output .hex file.

Change-Id: Iebbdcdaea7dc69e37b048ad2113007fae5471bad
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89799
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
---
 util/spd_tools/README.md              |   4 +-
 util/spd_tools/src/spd_gen/spd_gen.go | 154 ++++++++++++++++++++++++--
 2 files changed, 148 insertions(+), 10 deletions(-)

diff --git a/util/spd_tools/README.md b/util/spd_tools/README.md
index e7772c9827..4d5e051ef9 100644
--- a/util/spd_tools/README.md
+++ b/util/spd_tools/README.md
@@ -563,7 +563,7 @@ make -C util/spd_tools
 Usage:
 
 ```
-util/spd_tools/bin/spd_gen <mem_parts_list_json> <mem_technology>
+util/spd_tools/bin/spd_gen [ -o <output_dir> ] <mem_parts_list_json> <mem_technology> [<output_dir>|<output_hex>]
 ```
 
 Usage Examples:
@@ -572,6 +572,8 @@ Usage Examples:
 util/spd_tools/bin/spd_gen spd/ddr4/memory_parts.json ddr4
 util/spd_tools/bin/spd_gen spd/lp4x/memory_parts.json lp4x
 util/spd_tools/bin/spd_gen spd/lp5/memory_parts.json lp5
+util/spd_tools/bin/spd_gen -o out/lp5 spd/lp5/memory_parts.json lp5
+util/spd_tools/bin/spd_gen --set 0 part.spd.json lp5 out/spd.hex
 ```
 
 ### `part_id_gen`
diff --git a/util/spd_tools/src/spd_gen/spd_gen.go b/util/spd_tools/src/spd_gen/spd_gen.go
index 5c7ed79b15..a516b86337 100644
--- a/util/spd_tools/src/spd_gen/spd_gen.go
+++ b/util/spd_tools/src/spd_gen/spd_gen.go
@@ -3,7 +3,10 @@ package main
 
 import (
 	"encoding/json"
+	"errors"
+	"flag"
 	"fmt"
+	"io"
 	"io/ioutil"
 	"log"
 	"os"
@@ -163,18 +166,29 @@ func findIndex(dedupedAttribs []interface{}, newSPDAttribs interface{}) int {
 	return -1
 }
 
+// readJSONNoComments reads a JSON file and strips supported comment styles:
+// - line comments: "// ..." (on their own line, with optional leading spaces)
+// - block comments: "/* ... */"
+func readJSONNoComments(path string) ([]byte, error) {
+	dataBytes, err := ioutil.ReadFile(path)
+	if err != nil {
+		return nil, err
+	}
+	re := regexp.MustCompile(`(?m)^\s*//.*`)
+	dataBytes = re.ReplaceAll(dataBytes, []byte(""))
+	reBlock := regexp.MustCompile(`(?s)/\*.*?\*/`)
+	dataBytes = reBlock.ReplaceAll(dataBytes, []byte(""))
+	return dataBytes, nil
+}
+
 func readMemParts(memPartsFilePath string) (memParts, error) {
 	var memParts memParts
 
-	dataBytes, err := ioutil.ReadFile(memPartsFilePath)
+	dataBytes, err := readJSONNoComments(memPartsFilePath)
 	if err != nil {
 		return memParts, err
 	}
 
-	// Strip comments from json file
-	re := regexp.MustCompile(`(?m)^\s*//.*`)
-	dataBytes = re.ReplaceAll(dataBytes, []byte(""))
-
 	if err := json.Unmarshal(dataBytes, &memParts); err != nil {
 		return memParts, err
 	}
@@ -182,6 +196,73 @@ func readMemParts(memPartsFilePath string) (memParts, error) {
 	return memParts, nil
 }
 
+func readSingleAttributes(path string) (string, interface{}, error) {
+	dataBytes, err := readJSONNoComments(path)
+	if err != nil {
+		return "", nil, err
+	}
+
+	var root interface{}
+	if err := json.Unmarshal(dataBytes, &root); err != nil {
+		return "", nil, err
+	}
+
+	m, ok := root.(map[string]interface{})
+	if !ok {
+		return "", nil, errors.New("expected JSON object at top-level")
+	}
+
+	baseName := ""
+	{
+		base := filepath.Base(path)
+		if i := strings.LastIndex(base, "."); i >= 0 {
+			base = base[:i]
+		}
+		baseName = base
+	}
+
+	// Accept either:
+	//  1) {"name": "...", "attributes": {...}} (or "attribs")
+	//  2) {"parts":[{"name":"...","attribs":{...}}]} (single-part memory_parts.json)
+	if partsRaw, ok := m["parts"]; ok {
+		parts, ok := partsRaw.([]interface{})
+		if !ok || len(parts) == 0 {
+			return "", nil, errors.New("expected non-empty 'parts' array")
+		}
+		if len(parts) != 1 {
+			return "", nil, errors.New("expected exactly one part in 'parts' array")
+		}
+		p, ok := parts[0].(map[string]interface{})
+		if !ok {
+			return "", nil, errors.New("expected part entry to be a JSON object")
+		}
+		name, _ := p["name"].(string)
+		if name == "" {
+			name = baseName
+		}
+		if a, ok := p["attributes"]; ok {
+			return name, a, nil
+		}
+		if a, ok := p["attribs"]; ok {
+			return name, a, nil
+		}
+		return "", nil, errors.New("missing 'attribs'/'attributes' in part entry")
+	}
+
+	name, _ := m["name"].(string)
+	if name == "" {
+		name = baseName
+	}
+	if a, ok := m["attributes"]; ok {
+		return name, a, nil
+	}
+	if a, ok := m["attribs"]; ok {
+		return name, a, nil
+	}
+
+	return "", nil, errors.New("missing 'attribs'/'attributes' in JSON")
+}
+
 func createSPD(memAttribs interface{}, t memTech) string {
 	var s string
 
@@ -249,33 +330,88 @@ func writeSetMap(setMap map[int][]int, SPDDirName string) {
 }
 
 func usage() {
-	fmt.Printf("\nUsage: %s <mem_parts_list_json> <mem_technology>\n\n", os.Args[0])
+	fmt.Printf("\nUsage: %s [options] <mem_parts_list_json> <mem_technology> [<output_dir>|<output_hex>]\n\n", os.Args[0])
 	fmt.Printf("   where,\n")
 	fmt.Printf("   mem_parts_list_json = JSON File containing list of memory parts and attributes\n")
 	fmt.Printf("   mem_technology = Memory technology for which to generate SPDs\n")
 	fmt.Printf("                    supported technologies: %v\n\n\n",
 		reflect.ValueOf(memTechMap).MapKeys())
+	fmt.Printf("Options:\n")
+	fmt.Printf("   -out <output_dir>           Output directory (default: directory of JSON input)\n")
+	fmt.Printf("   -set <n>                    Set number when writing a single output_hex (default: 0)\n\n")
 }
 
 func main() {
-	if len(os.Args) != 3 {
+	fs := flag.NewFlagSet(os.Args[0], flag.ContinueOnError)
+	fs.SetOutput(io.Discard)
+	fs.Usage = usage
+
+	outOpt := fs.String("out", "", "Output directory (default: directory of JSON input)")
+	setOpt := fs.Int("set", 0, "Set number when writing a single output_hex (default: 0)")
+
+	if err := fs.Parse(os.Args[1:]); err != nil {
+		usage()
+		os.Exit(2)
+	}
+
+	if *setOpt < 0 {
+		log.Fatal("Invalid -set value: ", *setOpt)
+	}
+
+	varPos := fs.Args()
+	if len(varPos) != 2 && len(varPos) != 3 {
 		usage()
 		log.Fatal("Incorrect number of arguments")
 	}
 
 	var t memTech
-	memPartsFilePath, memTechnology := os.Args[1], os.Args[2]
+	memPartsFilePath, memTechnology := varPos[0], varPos[1]
 
 	t, ok := memTechMap[strings.ToLower(memTechnology)]
 	if !ok {
 		log.Fatal("Unsupported memory technology ", memTechnology)
 	}
 
-	SPDDir, err := filepath.Abs(filepath.Dir(memPartsFilePath))
+	var SPDDir string
+	fileOutput := false
+	SPDOutFile := ""
+	var err error
+	if len(varPos) == 3 && strings.HasSuffix(strings.ToLower(varPos[2]), ".hex") {
+		fileOutput = true
+		SPDOutFile, err = filepath.Abs(varPos[2])
+	} else if *outOpt != "" {
+		SPDDir, err = filepath.Abs(*outOpt)
+	} else if len(varPos) == 3 {
+		SPDDir, err = filepath.Abs(varPos[2])
+	} else {
+		SPDDir, err = filepath.Abs(filepath.Dir(memPartsFilePath))
+	}
 	if err != nil {
 		log.Fatal(err)
 	}
 
+	if fileOutput {
+		name, attrs, err := readSingleAttributes(memPartsFilePath)
+		if err != nil {
+			log.Fatal(err)
+		}
+		if err := t.addNewPart(name, attrs); err != nil {
+			log.Fatal(err)
+		}
+		spdAttribs, err := t.getSPDAttribs(name, *setOpt)
+		if err != nil {
+			log.Fatal(err)
+		}
+		s := createSPD(spdAttribs, t)
+		if err := os.MkdirAll(filepath.Dir(SPDOutFile), os.ModePerm); err != nil {
+			log.Fatal(err)
+		}
+		if err := ioutil.WriteFile(SPDOutFile, []byte(s), 0644); err != nil {
+			log.Fatal(err)
+		}
+		return
+	}
+
 	memParts, err := readMemParts(memPartsFilePath)
 	if err != nil {
 		log.Fatal(err)

From 2c9f1600e0553a95ecf8b1b1945c232366b570f8 Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Sun, 15 Feb 2026 21:12:31 +0000
Subject: [PATCH 3679/3886] src/lib: Generate spd.hex from JSON at build time

Allow mainboards to provide SPD sources as .spd.json alongside existing
.spd.hex files. When a JSON source is used, spd_gen is invoked at build
time to generate the corresponding .spd.hex in the build directory.

Change-Id: Ie1f2b81bcc15af65f1402b31f5c1f0553217fdda
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91251
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
---
 src/lib/Makefile.mk | 34 ++++++++++++++++++++++++++++++----
 1 file changed, 30 insertions(+), 4 deletions(-)

diff --git a/src/lib/Makefile.mk b/src/lib/Makefile.mk
index 0dc41ce921..756956aca5 100644
--- a/src/lib/Makefile.mk
+++ b/src/lib/Makefile.mk
@@ -375,17 +375,43 @@ romstage-y += spd_bin.c
 ifeq ($(CONFIG_HAVE_SPD_IN_CBFS),y)
 LIB_SPD_BIN = $(obj)/spd.bin
 
-LIB_SPD_DEPS = $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/spd/$(f).spd.hex)
+SPD_SRC_DIR := src/mainboard/$(MAINBOARDDIR)/spd
+SPD_OBJ_DIR := $(obj)/spd
+SPD_GEN_TOOL := util/spd_tools/bin/spd_gen
+
+SPD_GEN_MEM_TECH ?=
+SPD_GEN_SET ?= 0
+
+# Some boards set SPD_SOURCES to the sentinel value "placeholder" to request
+# a minimal spd.bin without any dependencies.
+SPD_SOURCES_IS_PLACEHOLDER = \
+	$(if $(filter placeholder,$(SPD_SOURCES)), \
+		$(if $(filter-out placeholder,$(SPD_SOURCES)),,y))
+
+define spd_hex_dep
+$(if $(wildcard $(SPD_SRC_DIR)/$(1).spd.hex),$(SPD_SRC_DIR)/$(1).spd.hex,$(SPD_OBJ_DIR)/$(1).spd.hex)
+endef
+
+LIB_SPD_DEPS = $(foreach f, $(SPD_SOURCES), $(call spd_hex_dep,$(f)))
+
+$(SPD_GEN_TOOL):
+	$(MAKE) -C util/spd_tools bin/spd_gen
+
+$(SPD_OBJ_DIR)/%.spd.hex: $(SPD_SRC_DIR)/%.spd.json | $(SPD_GEN_TOOL)
+	test -n "$(SPD_GEN_MEM_TECH)" || \
+	    (echo "SPD_GEN_MEM_TECH must be set to generate SPD hex from JSON" >&2 && exit 1)
+	mkdir -p $(SPD_OBJ_DIR)
+	$(SPD_GEN_TOOL) --set $(SPD_GEN_SET) $< $(SPD_GEN_MEM_TECH) $@
 
 # Include spd ROM data
-$(LIB_SPD_BIN): $(LIB_SPD_DEPS)
+$(LIB_SPD_BIN): $$(if $$(SPD_SOURCES_IS_PLACEHOLDER),,$$(LIB_SPD_DEPS))
 	test -n "$(SPD_SOURCES)" || \
 	    (echo "HAVE_SPD_IN_CBFS is set but SPD_SOURCES is empty" && exit 1)
-	test -n "$(LIB_SPD_DEPS)" || \
-	    (echo "SPD_SOURCES is set but no SPD file was found" && exit 1)
 	if [ "$(SPD_SOURCES)" = "placeholder" ]; then \
 	    printf '\0'; \
 	else \
+	    test -n "$(LIB_SPD_DEPS)" || \
+	        (echo "SPD_SOURCES is set but no SPD file was found" && exit 1); \
 	    for f in $(LIB_SPD_DEPS); do \
 	        if [ ! -f $$f ]; then \
 	            echo "File not found: $$f" >&2; \

From 5202b1371dd91b5146cbc441a74aa486409d124d Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Sun, 15 Feb 2026 21:21:54 +0000
Subject: [PATCH 3680/3886] mainboard/starlabs/adl: Convert i5 SPD sources to
 JSON

Replace checked-in mt62f2g64d8 .spd.hex blobs with .spd.json attribute
descriptions and generate the .spd.hex at build time via spd_gen.

Change-Id: I383b044f87c7ff9eaa57da580cd39a67c36c7b32
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91252
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
---
 src/mainboard/starlabs/adl/spd/Makefile.mk    |  2 ++
 .../starlabs/adl/spd/mt62f2g64d8-5500.spd.hex | 32 -------------------
 .../adl/spd/mt62f2g64d8-5500.spd.json         | 18 +++++++++++
 .../starlabs/adl/spd/mt62f2g64d8-6400.spd.hex | 32 -------------------
 .../adl/spd/mt62f2g64d8-6400.spd.json         | 18 +++++++++++
 .../starlabs/adl/spd/mt62f2g64d8-7500.spd.hex | 32 -------------------
 .../adl/spd/mt62f2g64d8-7500.spd.json         | 18 +++++++++++
 7 files changed, 56 insertions(+), 96 deletions(-)
 delete mode 100644 src/mainboard/starlabs/adl/spd/mt62f2g64d8-5500.spd.hex
 create mode 100644 src/mainboard/starlabs/adl/spd/mt62f2g64d8-5500.spd.json
 delete mode 100644 src/mainboard/starlabs/adl/spd/mt62f2g64d8-6400.spd.hex
 create mode 100644 src/mainboard/starlabs/adl/spd/mt62f2g64d8-6400.spd.json
 delete mode 100644 src/mainboard/starlabs/adl/spd/mt62f2g64d8-7500.spd.hex
 create mode 100644 src/mainboard/starlabs/adl/spd/mt62f2g64d8-7500.spd.json

diff --git a/src/mainboard/starlabs/adl/spd/Makefile.mk b/src/mainboard/starlabs/adl/spd/Makefile.mk
index f02db92001..51bfa8b1d5 100644
--- a/src/mainboard/starlabs/adl/spd/Makefile.mk
+++ b/src/mainboard/starlabs/adl/spd/Makefile.mk
@@ -1,5 +1,7 @@
 ## SPDX-License-Identifier: GPL-2.0-only
 
+SPD_GEN_MEM_TECH := lp5
+
 ifeq ($(VARIANT_DIR),hz)
 SPD_SOURCES = rs4g32l05d8fdb-5500
 SPD_SOURCES += rs4g32l05d8fdb-6400
diff --git a/src/mainboard/starlabs/adl/spd/mt62f2g64d8-5500.spd.hex b/src/mainboard/starlabs/adl/spd/mt62f2g64d8-5500.spd.hex
deleted file mode 100644
index 5236064650..0000000000
--- a/src/mainboard/starlabs/adl/spd/mt62f2g64d8-5500.spd.hex
+++ /dev/null
@@ -1,32 +0,0 @@
-23 10 15 0E 16 22 F9 08 00 00 00 00 0A 01 00 00
-00 00 0C 00 00 00 00 00 AF 00 90 A8 90 C0 08 60
-04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 CE 00 D3 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 20 20 20 20 20 20 20
-20 20 20 20 20 20 20 20 20 20 20 20 20 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
diff --git a/src/mainboard/starlabs/adl/spd/mt62f2g64d8-5500.spd.json b/src/mainboard/starlabs/adl/spd/mt62f2g64d8-5500.spd.json
new file mode 100644
index 0000000000..84efbbbe09
--- /dev/null
+++ b/src/mainboard/starlabs/adl/spd/mt62f2g64d8-5500.spd.json
@@ -0,0 +1,18 @@
+// Generated by:
+// util/scripts/spd-decode src/mainboard/starlabs/adl/spd/mt62f2g64d8-5500.spd.hex --pretty
+
+{
+	"parts": [
+		{
+			"name": "mt62f2g64d8-5500",
+			"attribs": {
+				"densityPerDieGb": 16,
+				"diesPerPackage": 8,
+				"bitWidthPerChannel": 16,
+				"ranksPerChannel": 2,
+				"speedMbps": 5500,
+				"lp5x": true
+			}
+		}
+	]
+}
diff --git a/src/mainboard/starlabs/adl/spd/mt62f2g64d8-6400.spd.hex b/src/mainboard/starlabs/adl/spd/mt62f2g64d8-6400.spd.hex
deleted file mode 100644
index d1d4ccf444..0000000000
--- a/src/mainboard/starlabs/adl/spd/mt62f2g64d8-6400.spd.hex
+++ /dev/null
@@ -1,32 +0,0 @@
-23 10 15 0E 16 22 F9 08 00 00 00 00 0A 01 00 00
-00 00 0A 00 00 00 00 00 AA 00 90 A8 90 C0 08 60
-04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 20 20 20 20 20 20 20
-20 20 20 20 20 20 20 20 20 20 20 20 20 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
diff --git a/src/mainboard/starlabs/adl/spd/mt62f2g64d8-6400.spd.json b/src/mainboard/starlabs/adl/spd/mt62f2g64d8-6400.spd.json
new file mode 100644
index 0000000000..462d6579f4
--- /dev/null
+++ b/src/mainboard/starlabs/adl/spd/mt62f2g64d8-6400.spd.json
@@ -0,0 +1,18 @@
+// Generated by:
+// util/scripts/spd-decode src/mainboard/starlabs/adl/spd/mt62f2g64d8-6400.spd.hex --pretty
+
+{
+	"parts": [
+		{
+			"name": "mt62f2g64d8-6400",
+			"attribs": {
+				"densityPerDieGb": 16,
+				"diesPerPackage": 8,
+				"bitWidthPerChannel": 16,
+				"ranksPerChannel": 2,
+				"speedMbps": 6400,
+				"lp5x": true
+			}
+		}
+	]
+}
diff --git a/src/mainboard/starlabs/adl/spd/mt62f2g64d8-7500.spd.hex b/src/mainboard/starlabs/adl/spd/mt62f2g64d8-7500.spd.hex
deleted file mode 100644
index 7f699a01ed..0000000000
--- a/src/mainboard/starlabs/adl/spd/mt62f2g64d8-7500.spd.hex
+++ /dev/null
@@ -1,32 +0,0 @@
-23 10 15 0E 16 22 F9 08 00 00 00 00 0A 01 00 00
-00 00 09 00 00 00 00 00 AB 00 90 A8 90 C0 08 60
-04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 C9 00 C5 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 20 20 20 20 20 20 20
-20 20 20 20 20 20 20 20 20 20 20 20 20 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
diff --git a/src/mainboard/starlabs/adl/spd/mt62f2g64d8-7500.spd.json b/src/mainboard/starlabs/adl/spd/mt62f2g64d8-7500.spd.json
new file mode 100644
index 0000000000..02b6aff63c
--- /dev/null
+++ b/src/mainboard/starlabs/adl/spd/mt62f2g64d8-7500.spd.json
@@ -0,0 +1,18 @@
+// Generated by:
+// util/scripts/spd-decode src/mainboard/starlabs/adl/spd/mt62f2g64d8-7500.spd.hex --pretty
+
+{
+	"parts": [
+		{
+			"name": "mt62f2g64d8-7500",
+			"attribs": {
+				"densityPerDieGb": 16,
+				"diesPerPackage": 8,
+				"bitWidthPerChannel": 16,
+				"ranksPerChannel": 2,
+				"speedMbps": 7500,
+				"lp5x": true
+			}
+		}
+	]
+}

From dda351b8958d3e668b02d45a1670a8ff3047fab1 Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Mon, 16 Feb 2026 20:22:02 +0000
Subject: [PATCH 3681/3886] mainboard/starlabs/adl: Convert SPD sources to JSON

Replace checked-in .spd.hex blobs with .spd.json attribute descriptions
and generate the .spd.hex at build time via spd_gen.

Change-Id: Ibfe5672ba9c4ffb3dcd328d9bf7df81395a3d93f
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91291
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
---
 .../adl/spd/rs4g32l05d8fdb-5500.spd.hex       | 32 -------------------
 .../adl/spd/rs4g32l05d8fdb-5500.spd.json      | 17 ++++++++++
 .../adl/spd/rs4g32l05d8fdb-6400.spd.hex       | 32 -------------------
 .../adl/spd/rs4g32l05d8fdb-6400.spd.json      | 17 ++++++++++
 .../adl/spd/rs4g32l05d8fdb-7500.spd.hex       | 32 -------------------
 .../adl/spd/rs4g32l05d8fdb-7500.spd.json      | 18 +++++++++++
 6 files changed, 52 insertions(+), 96 deletions(-)
 delete mode 100644 src/mainboard/starlabs/adl/spd/rs4g32l05d8fdb-5500.spd.hex
 create mode 100644 src/mainboard/starlabs/adl/spd/rs4g32l05d8fdb-5500.spd.json
 delete mode 100644 src/mainboard/starlabs/adl/spd/rs4g32l05d8fdb-6400.spd.hex
 create mode 100644 src/mainboard/starlabs/adl/spd/rs4g32l05d8fdb-6400.spd.json
 delete mode 100644 src/mainboard/starlabs/adl/spd/rs4g32l05d8fdb-7500.spd.hex
 create mode 100644 src/mainboard/starlabs/adl/spd/rs4g32l05d8fdb-7500.spd.json

diff --git a/src/mainboard/starlabs/adl/spd/rs4g32l05d8fdb-5500.spd.hex b/src/mainboard/starlabs/adl/spd/rs4g32l05d8fdb-5500.spd.hex
deleted file mode 100644
index a52441a71b..0000000000
--- a/src/mainboard/starlabs/adl/spd/rs4g32l05d8fdb-5500.spd.hex
+++ /dev/null
@@ -1,32 +0,0 @@
-23 10 13 0E 16 2A 91 08 00 00 00 00 09 01 00 00
-00 00 0B 00 00 00 00 00 AE 00 90 A8 90 C0 08 60
-04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 4B 00 50 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 20 20 20 20 20 20 20
-20 20 20 20 20 20 20 20 20 20 20 20 20 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
diff --git a/src/mainboard/starlabs/adl/spd/rs4g32l05d8fdb-5500.spd.json b/src/mainboard/starlabs/adl/spd/rs4g32l05d8fdb-5500.spd.json
new file mode 100644
index 0000000000..80317b3dd4
--- /dev/null
+++ b/src/mainboard/starlabs/adl/spd/rs4g32l05d8fdb-5500.spd.json
@@ -0,0 +1,17 @@
+// Generated by:
+// util/scripts/spd-decode src/mainboard/starlabs/adl/spd/rs4g32l05d8fdb-5500.spd.hex --pretty --name rs4g32l05d8fdb-5500
+
+{
+	"parts": [
+		{
+			"name": "rs4g32l05d8fdb-5500",
+			"attribs": {
+				"densityPerDieGb": 16,
+				"diesPerPackage": 2,
+				"bitWidthPerChannel": 8,
+				"ranksPerChannel": 2,
+				"speedMbps": 5500
+			}
+		}
+	]
+}
diff --git a/src/mainboard/starlabs/adl/spd/rs4g32l05d8fdb-6400.spd.hex b/src/mainboard/starlabs/adl/spd/rs4g32l05d8fdb-6400.spd.hex
deleted file mode 100644
index 0969d01568..0000000000
--- a/src/mainboard/starlabs/adl/spd/rs4g32l05d8fdb-6400.spd.hex
+++ /dev/null
@@ -1,32 +0,0 @@
-23 10 13 0E 16 2A 91 08 00 00 00 00 09 01 00 00
-00 00 0A 00 00 00 00 00 AA 00 90 A8 90 C0 08 60
-04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 20 20 20 20 20 20 20
-20 20 20 20 20 20 20 20 20 20 20 20 20 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
diff --git a/src/mainboard/starlabs/adl/spd/rs4g32l05d8fdb-6400.spd.json b/src/mainboard/starlabs/adl/spd/rs4g32l05d8fdb-6400.spd.json
new file mode 100644
index 0000000000..f492a2b4aa
--- /dev/null
+++ b/src/mainboard/starlabs/adl/spd/rs4g32l05d8fdb-6400.spd.json
@@ -0,0 +1,17 @@
+// Generated by:
+// util/scripts/spd-decode src/mainboard/starlabs/adl/spd/rs4g32l05d8fdb-6400.spd.hex --pretty --name rs4g32l05d8fdb-6400
+
+{
+	"parts": [
+		{
+			"name": "rs4g32l05d8fdb-6400",
+			"attribs": {
+				"densityPerDieGb": 16,
+				"diesPerPackage": 2,
+				"bitWidthPerChannel": 8,
+				"ranksPerChannel": 2,
+				"speedMbps": 6400
+			}
+		}
+	]
+}
diff --git a/src/mainboard/starlabs/adl/spd/rs4g32l05d8fdb-7500.spd.hex b/src/mainboard/starlabs/adl/spd/rs4g32l05d8fdb-7500.spd.hex
deleted file mode 100644
index c132efab8c..0000000000
--- a/src/mainboard/starlabs/adl/spd/rs4g32l05d8fdb-7500.spd.hex
+++ /dev/null
@@ -1,32 +0,0 @@
-23 10 13 0E 16 2A 91 08 00 00 00 00 09 01 00 00
-00 00 08 00 00 00 00 00 AA 00 90 A8 90 C0 08 60
-04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 46 00 42 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 20 20 20 20 20 20 20
-20 20 20 20 20 20 20 20 20 20 20 20 20 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
diff --git a/src/mainboard/starlabs/adl/spd/rs4g32l05d8fdb-7500.spd.json b/src/mainboard/starlabs/adl/spd/rs4g32l05d8fdb-7500.spd.json
new file mode 100644
index 0000000000..a9a9760de1
--- /dev/null
+++ b/src/mainboard/starlabs/adl/spd/rs4g32l05d8fdb-7500.spd.json
@@ -0,0 +1,18 @@
+// Generated by:
+// util/scripts/spd-decode src/mainboard/starlabs/adl/spd/rs4g32l05d8fdb-7500.spd.hex --pretty --name rs4g32l05d8fdb-7500
+
+{
+	"parts": [
+		{
+			"name": "rs4g32l05d8fdb-7500",
+			"attribs": {
+				"densityPerDieGb": 16,
+				"diesPerPackage": 2,
+				"bitWidthPerChannel": 8,
+				"ranksPerChannel": 2,
+				"speedMbps": 7500,
+				"lp5x": true
+			}
+		}
+	]
+}

From 975613717ae938267e3f66950225573c6544293c Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Mon, 16 Feb 2026 20:22:15 +0000
Subject: [PATCH 3682/3886] mainboard/starlabs/starfighter: Convert SPD sources
 to JSON

Replace checked-in .spd.hex blobs with .spd.json attribute descriptions
and generate the .spd.hex at build time via spd_gen.

Change-Id: I777b12df911576c684ee8146f5ec69e61b0cc772
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91292
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 .../starfighter/spd/16gb-5500.spd.hex         | 32 -------------------
 .../starfighter/spd/16gb-5500.spd.json        | 17 ++++++++++
 .../starfighter/spd/16gb-6400.spd.hex         | 32 -------------------
 .../starfighter/spd/16gb-6400.spd.json        | 17 ++++++++++
 .../starfighter/spd/16gb-7500.spd.hex         | 32 -------------------
 .../starfighter/spd/16gb-7500.spd.json        | 18 +++++++++++
 .../starfighter/spd/32gb-5500.spd.hex         | 32 -------------------
 .../starfighter/spd/32gb-5500.spd.json        | 17 ++++++++++
 .../starfighter/spd/32gb-6400.spd.hex         | 32 -------------------
 .../starfighter/spd/32gb-6400.spd.json        | 17 ++++++++++
 .../starfighter/spd/32gb-7500.spd.hex         | 32 -------------------
 .../starfighter/spd/32gb-7500.spd.json        | 18 +++++++++++
 .../starfighter/spd/32gb-mtl-5500.spd.hex     | 32 -------------------
 .../starfighter/spd/32gb-mtl-5500.spd.json    | 17 ++++++++++
 .../starfighter/spd/32gb-mtl-6400.spd.hex     | 32 -------------------
 .../starfighter/spd/32gb-mtl-6400.spd.json    | 17 ++++++++++
 .../starfighter/spd/32gb-mtl-7500.spd.hex     | 32 -------------------
 .../starfighter/spd/32gb-mtl-7500.spd.json    | 18 +++++++++++
 .../starfighter/spd/64gb-5500.spd.hex         | 32 -------------------
 .../starfighter/spd/64gb-5500.spd.json        | 18 +++++++++++
 .../starfighter/spd/64gb-6400.spd.hex         | 32 -------------------
 .../starfighter/spd/64gb-6400.spd.json        | 18 +++++++++++
 .../starfighter/spd/64gb-7500.spd.hex         | 32 -------------------
 .../starfighter/spd/64gb-7500.spd.json        | 18 +++++++++++
 .../starfighter/spd/64gb-mtl-5500.spd.hex     | 32 -------------------
 .../starfighter/spd/64gb-mtl-5500.spd.json    | 18 +++++++++++
 .../starfighter/spd/64gb-mtl-6400.spd.hex     | 32 -------------------
 .../starfighter/spd/64gb-mtl-6400.spd.json    | 18 +++++++++++
 .../starfighter/spd/64gb-mtl-7500.spd.hex     | 32 -------------------
 .../starfighter/spd/64gb-mtl-7500.spd.json    | 18 +++++++++++
 .../starlabs/starfighter/spd/Makefile.mk      |  2 ++
 31 files changed, 266 insertions(+), 480 deletions(-)
 delete mode 100644 src/mainboard/starlabs/starfighter/spd/16gb-5500.spd.hex
 create mode 100644 src/mainboard/starlabs/starfighter/spd/16gb-5500.spd.json
 delete mode 100644 src/mainboard/starlabs/starfighter/spd/16gb-6400.spd.hex
 create mode 100644 src/mainboard/starlabs/starfighter/spd/16gb-6400.spd.json
 delete mode 100644 src/mainboard/starlabs/starfighter/spd/16gb-7500.spd.hex
 create mode 100644 src/mainboard/starlabs/starfighter/spd/16gb-7500.spd.json
 delete mode 100644 src/mainboard/starlabs/starfighter/spd/32gb-5500.spd.hex
 create mode 100644 src/mainboard/starlabs/starfighter/spd/32gb-5500.spd.json
 delete mode 100644 src/mainboard/starlabs/starfighter/spd/32gb-6400.spd.hex
 create mode 100644 src/mainboard/starlabs/starfighter/spd/32gb-6400.spd.json
 delete mode 100644 src/mainboard/starlabs/starfighter/spd/32gb-7500.spd.hex
 create mode 100644 src/mainboard/starlabs/starfighter/spd/32gb-7500.spd.json
 delete mode 100644 src/mainboard/starlabs/starfighter/spd/32gb-mtl-5500.spd.hex
 create mode 100644 src/mainboard/starlabs/starfighter/spd/32gb-mtl-5500.spd.json
 delete mode 100644 src/mainboard/starlabs/starfighter/spd/32gb-mtl-6400.spd.hex
 create mode 100644 src/mainboard/starlabs/starfighter/spd/32gb-mtl-6400.spd.json
 delete mode 100644 src/mainboard/starlabs/starfighter/spd/32gb-mtl-7500.spd.hex
 create mode 100644 src/mainboard/starlabs/starfighter/spd/32gb-mtl-7500.spd.json
 delete mode 100644 src/mainboard/starlabs/starfighter/spd/64gb-5500.spd.hex
 create mode 100644 src/mainboard/starlabs/starfighter/spd/64gb-5500.spd.json
 delete mode 100644 src/mainboard/starlabs/starfighter/spd/64gb-6400.spd.hex
 create mode 100644 src/mainboard/starlabs/starfighter/spd/64gb-6400.spd.json
 delete mode 100644 src/mainboard/starlabs/starfighter/spd/64gb-7500.spd.hex
 create mode 100644 src/mainboard/starlabs/starfighter/spd/64gb-7500.spd.json
 delete mode 100644 src/mainboard/starlabs/starfighter/spd/64gb-mtl-5500.spd.hex
 create mode 100644 src/mainboard/starlabs/starfighter/spd/64gb-mtl-5500.spd.json
 delete mode 100644 src/mainboard/starlabs/starfighter/spd/64gb-mtl-6400.spd.hex
 create mode 100644 src/mainboard/starlabs/starfighter/spd/64gb-mtl-6400.spd.json
 delete mode 100644 src/mainboard/starlabs/starfighter/spd/64gb-mtl-7500.spd.hex
 create mode 100644 src/mainboard/starlabs/starfighter/spd/64gb-mtl-7500.spd.json

diff --git a/src/mainboard/starlabs/starfighter/spd/16gb-5500.spd.hex b/src/mainboard/starlabs/starfighter/spd/16gb-5500.spd.hex
deleted file mode 100644
index 77a62517e3..0000000000
--- a/src/mainboard/starlabs/starfighter/spd/16gb-5500.spd.hex
+++ /dev/null
@@ -1,32 +0,0 @@
-23 10 13 0E 15 1A B5 08 00 40 00 00 0A 01 00 00
-48 00 0B FF 92 55 05 00 AE 00 90 A8 90 90 06 C0
-03 08 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 16 36 16 36
-16 36 16 36 00 00 16 36 16 36 16 36 16 36 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 9C 00 00 00 00 4B 7F 50 69 9A
-11 01 40 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 D8 53
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-80 2C 25 20 02 F0 E6 A8 9B 38 41 54 46 31 47 36
-34 41 5A 2D 33 47 32 45 31 20 20 20 20 31 80 2C
-45 48 4D 30 30 30 30 33 37 30 33 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
diff --git a/src/mainboard/starlabs/starfighter/spd/16gb-5500.spd.json b/src/mainboard/starlabs/starfighter/spd/16gb-5500.spd.json
new file mode 100644
index 0000000000..fa1a870a24
--- /dev/null
+++ b/src/mainboard/starlabs/starfighter/spd/16gb-5500.spd.json
@@ -0,0 +1,17 @@
+// Generated by:
+// util/scripts/spd-decode src/mainboard/starlabs/starfighter/spd/16gb-5500.spd.hex --pretty --name 16gb-5500
+
+{
+	"parts": [
+		{
+			"name": "16gb-5500",
+			"attribs": {
+				"densityPerDieGb": 8,
+				"diesPerPackage": 4,
+				"bitWidthPerChannel": 16,
+				"ranksPerChannel": 2,
+				"speedMbps": 5500
+			}
+		}
+	]
+}
diff --git a/src/mainboard/starlabs/starfighter/spd/16gb-6400.spd.hex b/src/mainboard/starlabs/starfighter/spd/16gb-6400.spd.hex
deleted file mode 100644
index 642023b380..0000000000
--- a/src/mainboard/starlabs/starfighter/spd/16gb-6400.spd.hex
+++ /dev/null
@@ -1,32 +0,0 @@
-23 10 13 0E 15 1A B5 08 00 40 00 00 0A 01 00 00
-48 00 0A FF 92 55 05 00 AA 00 90 A8 90 90 06 C0
-03 08 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 16 36 16 36
-16 36 16 36 00 00 16 36 16 36 16 36 16 36 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 9C 00 00 00 00 00 7F 00 69 9A
-11 01 40 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 D8 53
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-80 2C 25 20 02 F0 E6 A8 9B 38 41 54 46 31 47 36
-34 41 5A 2D 33 47 32 45 31 20 20 20 20 31 80 2C
-45 48 4D 30 30 30 30 33 37 30 33 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
diff --git a/src/mainboard/starlabs/starfighter/spd/16gb-6400.spd.json b/src/mainboard/starlabs/starfighter/spd/16gb-6400.spd.json
new file mode 100644
index 0000000000..aec357227b
--- /dev/null
+++ b/src/mainboard/starlabs/starfighter/spd/16gb-6400.spd.json
@@ -0,0 +1,17 @@
+// Generated by:
+// util/scripts/spd-decode src/mainboard/starlabs/starfighter/spd/16gb-6400.spd.hex --pretty --name 16gb-6400
+
+{
+	"parts": [
+		{
+			"name": "16gb-6400",
+			"attribs": {
+				"densityPerDieGb": 8,
+				"diesPerPackage": 4,
+				"bitWidthPerChannel": 16,
+				"ranksPerChannel": 2,
+				"speedMbps": 6400
+			}
+		}
+	]
+}
diff --git a/src/mainboard/starlabs/starfighter/spd/16gb-7500.spd.hex b/src/mainboard/starlabs/starfighter/spd/16gb-7500.spd.hex
deleted file mode 100644
index 110d974afa..0000000000
--- a/src/mainboard/starlabs/starfighter/spd/16gb-7500.spd.hex
+++ /dev/null
@@ -1,32 +0,0 @@
-23 10 13 0E 15 1A B5 08 00 40 00 00 0A 01 00 00
-48 00 08 FF 92 55 05 00 AA 00 90 A8 90 90 06 C0
-03 08 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 16 36 16 36
-16 36 16 36 00 00 16 36 16 36 16 36 16 36 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 9C 00 00 00 00 46 7F 42 69 9A
-11 01 40 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 D8 53
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-80 2C 25 20 02 F0 E6 A8 9B 38 41 54 46 31 47 36
-34 41 5A 2D 33 47 32 45 31 20 20 20 20 31 80 2C
-45 48 4D 30 30 30 30 33 37 30 33 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
diff --git a/src/mainboard/starlabs/starfighter/spd/16gb-7500.spd.json b/src/mainboard/starlabs/starfighter/spd/16gb-7500.spd.json
new file mode 100644
index 0000000000..cff5be57a2
--- /dev/null
+++ b/src/mainboard/starlabs/starfighter/spd/16gb-7500.spd.json
@@ -0,0 +1,18 @@
+// Generated by:
+// util/scripts/spd-decode src/mainboard/starlabs/starfighter/spd/16gb-7500.spd.hex --pretty --name 16gb-7500
+
+{
+	"parts": [
+		{
+			"name": "16gb-7500",
+			"attribs": {
+				"densityPerDieGb": 8,
+				"diesPerPackage": 4,
+				"bitWidthPerChannel": 16,
+				"ranksPerChannel": 2,
+				"speedMbps": 7500,
+				"lp5x": true
+			}
+		}
+	]
+}
diff --git a/src/mainboard/starlabs/starfighter/spd/32gb-5500.spd.hex b/src/mainboard/starlabs/starfighter/spd/32gb-5500.spd.hex
deleted file mode 100644
index 09f6a03464..0000000000
--- a/src/mainboard/starlabs/starfighter/spd/32gb-5500.spd.hex
+++ /dev/null
@@ -1,32 +0,0 @@
-23 10 13 0E 16 22 B5 08 00 40 00 00 0A 01 00 00
-48 00 0B FF 92 55 05 00 AE 00 90 A8 90 C0 08 60
-04 08 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 16 36 16 36
-16 36 16 36 00 00 16 36 16 36 16 36 16 36 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 9C 00 00 00 00 4B 7F 50 69 9A
-11 01 40 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 D8 53
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-80 2C 25 20 02 F0 E6 A8 9B 38 41 54 46 31 47 36
-34 41 5A 2D 33 47 32 45 31 20 20 20 20 31 80 2C
-45 48 4D 30 30 30 30 33 37 30 33 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
diff --git a/src/mainboard/starlabs/starfighter/spd/32gb-5500.spd.json b/src/mainboard/starlabs/starfighter/spd/32gb-5500.spd.json
new file mode 100644
index 0000000000..0ee126004f
--- /dev/null
+++ b/src/mainboard/starlabs/starfighter/spd/32gb-5500.spd.json
@@ -0,0 +1,17 @@
+// Generated by:
+// util/scripts/spd-decode src/mainboard/starlabs/starfighter/spd/32gb-5500.spd.hex --pretty --name 32gb-5500
+
+{
+	"parts": [
+		{
+			"name": "32gb-5500",
+			"attribs": {
+				"densityPerDieGb": 16,
+				"diesPerPackage": 4,
+				"bitWidthPerChannel": 16,
+				"ranksPerChannel": 2,
+				"speedMbps": 5500
+			}
+		}
+	]
+}
diff --git a/src/mainboard/starlabs/starfighter/spd/32gb-6400.spd.hex b/src/mainboard/starlabs/starfighter/spd/32gb-6400.spd.hex
deleted file mode 100644
index 00bc34ba02..0000000000
--- a/src/mainboard/starlabs/starfighter/spd/32gb-6400.spd.hex
+++ /dev/null
@@ -1,32 +0,0 @@
-23 10 13 0E 16 22 B5 08 00 40 00 00 0A 01 00 00
-48 00 0A FF 92 55 05 00 AA 00 90 A8 90 C0 08 60
-04 08 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 16 36 16 36
-16 36 16 36 00 00 16 36 16 36 16 36 16 36 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 9C 00 00 00 00 00 7F 00 69 9A
-11 01 40 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 D8 53
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-80 2C 25 20 02 F0 E6 A8 9B 38 41 54 46 31 47 36
-34 41 5A 2D 33 47 32 45 31 20 20 20 20 31 80 2C
-45 48 4D 30 30 30 30 33 37 30 33 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
diff --git a/src/mainboard/starlabs/starfighter/spd/32gb-6400.spd.json b/src/mainboard/starlabs/starfighter/spd/32gb-6400.spd.json
new file mode 100644
index 0000000000..f51338db9e
--- /dev/null
+++ b/src/mainboard/starlabs/starfighter/spd/32gb-6400.spd.json
@@ -0,0 +1,17 @@
+// Generated by:
+// util/scripts/spd-decode src/mainboard/starlabs/starfighter/spd/32gb-6400.spd.hex --pretty --name 32gb-6400
+
+{
+	"parts": [
+		{
+			"name": "32gb-6400",
+			"attribs": {
+				"densityPerDieGb": 16,
+				"diesPerPackage": 4,
+				"bitWidthPerChannel": 16,
+				"ranksPerChannel": 2,
+				"speedMbps": 6400
+			}
+		}
+	]
+}
diff --git a/src/mainboard/starlabs/starfighter/spd/32gb-7500.spd.hex b/src/mainboard/starlabs/starfighter/spd/32gb-7500.spd.hex
deleted file mode 100644
index c946476aa6..0000000000
--- a/src/mainboard/starlabs/starfighter/spd/32gb-7500.spd.hex
+++ /dev/null
@@ -1,32 +0,0 @@
-23 10 13 0E 16 22 B5 08 00 40 00 00 0A 01 00 00
-48 00 08 FF 92 55 05 00 AA 00 90 A8 90 C0 08 60
-04 08 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 16 36 16 36
-16 36 16 36 00 00 16 36 16 36 16 36 16 36 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 9C 00 00 00 00 46 7F 42 69 9A
-11 01 40 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 D8 53
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-80 2C 25 20 02 F0 E6 A8 9B 38 41 54 46 31 47 36
-34 41 5A 2D 33 47 32 45 31 20 20 20 20 31 80 2C
-45 48 4D 30 30 30 30 33 37 30 33 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
diff --git a/src/mainboard/starlabs/starfighter/spd/32gb-7500.spd.json b/src/mainboard/starlabs/starfighter/spd/32gb-7500.spd.json
new file mode 100644
index 0000000000..d7971f8f80
--- /dev/null
+++ b/src/mainboard/starlabs/starfighter/spd/32gb-7500.spd.json
@@ -0,0 +1,18 @@
+// Generated by:
+// util/scripts/spd-decode src/mainboard/starlabs/starfighter/spd/32gb-7500.spd.hex --pretty --name 32gb-7500
+
+{
+	"parts": [
+		{
+			"name": "32gb-7500",
+			"attribs": {
+				"densityPerDieGb": 16,
+				"diesPerPackage": 4,
+				"bitWidthPerChannel": 16,
+				"ranksPerChannel": 2,
+				"speedMbps": 7500,
+				"lp5x": true
+			}
+		}
+	]
+}
diff --git a/src/mainboard/starlabs/starfighter/spd/32gb-mtl-5500.spd.hex b/src/mainboard/starlabs/starfighter/spd/32gb-mtl-5500.spd.hex
deleted file mode 100644
index de89ca1b80..0000000000
--- a/src/mainboard/starlabs/starfighter/spd/32gb-mtl-5500.spd.hex
+++ /dev/null
@@ -1,32 +0,0 @@
-23 10 13 0E 16 22 B5 08 00 40 00 00 0A 01 00 00
-48 00 0B FF 92 55 05 00 AE 00 90 A8 90 C0 08 60
-04 08 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 4B 7F 50 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 20 00 00 00 20 20 20 20 20 20 20
-20 20 20 20 20 20 20 20 20 20 20 20 20 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
diff --git a/src/mainboard/starlabs/starfighter/spd/32gb-mtl-5500.spd.json b/src/mainboard/starlabs/starfighter/spd/32gb-mtl-5500.spd.json
new file mode 100644
index 0000000000..553728d775
--- /dev/null
+++ b/src/mainboard/starlabs/starfighter/spd/32gb-mtl-5500.spd.json
@@ -0,0 +1,17 @@
+// Generated by:
+// util/scripts/spd-decode src/mainboard/starlabs/starfighter/spd/32gb-mtl-5500.spd.hex --pretty --name 32gb-mtl-5500
+
+{
+	"parts": [
+		{
+			"name": "32gb-mtl-5500",
+			"attribs": {
+				"densityPerDieGb": 16,
+				"diesPerPackage": 4,
+				"bitWidthPerChannel": 16,
+				"ranksPerChannel": 2,
+				"speedMbps": 5500
+			}
+		}
+	]
+}
diff --git a/src/mainboard/starlabs/starfighter/spd/32gb-mtl-6400.spd.hex b/src/mainboard/starlabs/starfighter/spd/32gb-mtl-6400.spd.hex
deleted file mode 100644
index d38329a777..0000000000
--- a/src/mainboard/starlabs/starfighter/spd/32gb-mtl-6400.spd.hex
+++ /dev/null
@@ -1,32 +0,0 @@
-23 10 13 0E 16 22 B5 08 00 40 00 00 0A 01 00 00
-48 00 0A FF 92 55 05 00 AA 00 90 A8 90 C0 08 60
-04 08 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 7F 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 20 00 00 00 20 20 20 20 20 20 20
-20 20 20 20 20 20 20 20 20 20 20 20 20 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
diff --git a/src/mainboard/starlabs/starfighter/spd/32gb-mtl-6400.spd.json b/src/mainboard/starlabs/starfighter/spd/32gb-mtl-6400.spd.json
new file mode 100644
index 0000000000..b89a94743b
--- /dev/null
+++ b/src/mainboard/starlabs/starfighter/spd/32gb-mtl-6400.spd.json
@@ -0,0 +1,17 @@
+// Generated by:
+// util/scripts/spd-decode src/mainboard/starlabs/starfighter/spd/32gb-mtl-6400.spd.hex --pretty --name 32gb-mtl-6400
+
+{
+	"parts": [
+		{
+			"name": "32gb-mtl-6400",
+			"attribs": {
+				"densityPerDieGb": 16,
+				"diesPerPackage": 4,
+				"bitWidthPerChannel": 16,
+				"ranksPerChannel": 2,
+				"speedMbps": 6400
+			}
+		}
+	]
+}
diff --git a/src/mainboard/starlabs/starfighter/spd/32gb-mtl-7500.spd.hex b/src/mainboard/starlabs/starfighter/spd/32gb-mtl-7500.spd.hex
deleted file mode 100644
index 8f4c71530a..0000000000
--- a/src/mainboard/starlabs/starfighter/spd/32gb-mtl-7500.spd.hex
+++ /dev/null
@@ -1,32 +0,0 @@
-23 10 13 0E 16 22 B5 08 00 40 00 00 0A 01 00 00
-48 00 08 FF 92 55 05 00 AA 00 90 A8 90 C0 08 60
-04 08 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 46 7F 42 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 20 00 00 00 20 20 20 20 20 20 20
-20 20 20 20 20 20 20 20 20 20 20 20 20 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
diff --git a/src/mainboard/starlabs/starfighter/spd/32gb-mtl-7500.spd.json b/src/mainboard/starlabs/starfighter/spd/32gb-mtl-7500.spd.json
new file mode 100644
index 0000000000..475a01cf99
--- /dev/null
+++ b/src/mainboard/starlabs/starfighter/spd/32gb-mtl-7500.spd.json
@@ -0,0 +1,18 @@
+// Generated by:
+// util/scripts/spd-decode src/mainboard/starlabs/starfighter/spd/32gb-mtl-7500.spd.hex --pretty --name 32gb-mtl-7500
+
+{
+	"parts": [
+		{
+			"name": "32gb-mtl-7500",
+			"attribs": {
+				"densityPerDieGb": 16,
+				"diesPerPackage": 4,
+				"bitWidthPerChannel": 16,
+				"ranksPerChannel": 2,
+				"speedMbps": 7500,
+				"lp5x": true
+			}
+		}
+	]
+}
diff --git a/src/mainboard/starlabs/starfighter/spd/64gb-5500.spd.hex b/src/mainboard/starlabs/starfighter/spd/64gb-5500.spd.hex
deleted file mode 100644
index c0ecc15077..0000000000
--- a/src/mainboard/starlabs/starfighter/spd/64gb-5500.spd.hex
+++ /dev/null
@@ -1,32 +0,0 @@
-23 10 15 0E 16 2A F9 08 00 40 00 00 09 01 00 00
-48 00 0B FF 92 55 05 00 AE 00 90 A8 90 C0 08 60
-04 08 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 16 36 16 36
-16 36 16 36 00 00 16 36 16 36 16 36 16 36 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 9C 00 00 00 00 4B 7F 50 69 9A
-11 01 40 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 D8 53
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-80 2C 25 20 02 F0 E6 A8 9B 38 41 54 46 31 47 36
-34 41 5A 2D 33 47 32 45 31 20 20 20 20 31 80 2C
-45 48 4D 30 30 30 30 33 37 30 33 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
diff --git a/src/mainboard/starlabs/starfighter/spd/64gb-5500.spd.json b/src/mainboard/starlabs/starfighter/spd/64gb-5500.spd.json
new file mode 100644
index 0000000000..f131bcaf21
--- /dev/null
+++ b/src/mainboard/starlabs/starfighter/spd/64gb-5500.spd.json
@@ -0,0 +1,18 @@
+// Generated by:
+// util/scripts/spd-decode src/mainboard/starlabs/starfighter/spd/64gb-5500.spd.hex --pretty --name 64gb-5500
+
+{
+	"parts": [
+		{
+			"name": "64gb-5500",
+			"attribs": {
+				"densityPerDieGb": 16,
+				"diesPerPackage": 8,
+				"bitWidthPerChannel": 8,
+				"ranksPerChannel": 2,
+				"speedMbps": 5500,
+				"lp5x": true
+			}
+		}
+	]
+}
diff --git a/src/mainboard/starlabs/starfighter/spd/64gb-6400.spd.hex b/src/mainboard/starlabs/starfighter/spd/64gb-6400.spd.hex
deleted file mode 100644
index bdeb4c2501..0000000000
--- a/src/mainboard/starlabs/starfighter/spd/64gb-6400.spd.hex
+++ /dev/null
@@ -1,32 +0,0 @@
-23 10 15 0E 16 2A F9 08 00 40 00 00 09 01 00 00
-48 00 0A FF 92 55 05 00 AA 00 90 A8 90 C0 08 60
-04 08 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 16 36 16 36
-16 36 16 36 00 00 16 36 16 36 16 36 16 36 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 9C 00 00 00 00 00 7F 00 69 9A
-11 01 40 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 D8 53
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-80 2C 25 20 02 F0 E6 A8 9B 38 41 54 46 31 47 36
-34 41 5A 2D 33 47 32 45 31 20 20 20 20 31 80 2C
-45 48 4D 30 30 30 30 33 37 30 33 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
diff --git a/src/mainboard/starlabs/starfighter/spd/64gb-6400.spd.json b/src/mainboard/starlabs/starfighter/spd/64gb-6400.spd.json
new file mode 100644
index 0000000000..cf1d057df0
--- /dev/null
+++ b/src/mainboard/starlabs/starfighter/spd/64gb-6400.spd.json
@@ -0,0 +1,18 @@
+// Generated by:
+// util/scripts/spd-decode src/mainboard/starlabs/starfighter/spd/64gb-6400.spd.hex --pretty --name 64gb-6400
+
+{
+	"parts": [
+		{
+			"name": "64gb-6400",
+			"attribs": {
+				"densityPerDieGb": 16,
+				"diesPerPackage": 8,
+				"bitWidthPerChannel": 8,
+				"ranksPerChannel": 2,
+				"speedMbps": 6400,
+				"lp5x": true
+			}
+		}
+	]
+}
diff --git a/src/mainboard/starlabs/starfighter/spd/64gb-7500.spd.hex b/src/mainboard/starlabs/starfighter/spd/64gb-7500.spd.hex
deleted file mode 100644
index 0d17713a1e..0000000000
--- a/src/mainboard/starlabs/starfighter/spd/64gb-7500.spd.hex
+++ /dev/null
@@ -1,32 +0,0 @@
-23 10 15 0E 16 2A F9 08 00 40 00 00 09 01 00 00
-48 00 08 FF 92 55 05 00 AA 00 90 A8 90 C0 08 60
-04 08 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 16 36 16 36
-16 36 16 36 00 00 16 36 16 36 16 36 16 36 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 9C 00 00 00 00 00 7F 43 69 9A
-11 01 40 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 D8 53
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-80 2C 25 20 02 F0 E6 A8 9B 38 41 54 46 31 47 36
-34 41 5A 2D 33 47 32 45 31 20 20 20 20 31 80 2C
-45 48 4D 30 30 30 30 33 37 30 33 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
diff --git a/src/mainboard/starlabs/starfighter/spd/64gb-7500.spd.json b/src/mainboard/starlabs/starfighter/spd/64gb-7500.spd.json
new file mode 100644
index 0000000000..0e045b628c
--- /dev/null
+++ b/src/mainboard/starlabs/starfighter/spd/64gb-7500.spd.json
@@ -0,0 +1,18 @@
+// Generated by:
+// util/scripts/spd-decode src/mainboard/starlabs/starfighter/spd/64gb-7500.spd.hex --pretty --name 64gb-7500
+
+{
+	"parts": [
+		{
+			"name": "64gb-7500",
+			"attribs": {
+				"densityPerDieGb": 16,
+				"diesPerPackage": 8,
+				"bitWidthPerChannel": 8,
+				"ranksPerChannel": 2,
+				"speedMbps": 7500,
+				"lp5x": true
+			}
+		}
+	]
+}
diff --git a/src/mainboard/starlabs/starfighter/spd/64gb-mtl-5500.spd.hex b/src/mainboard/starlabs/starfighter/spd/64gb-mtl-5500.spd.hex
deleted file mode 100644
index c2934a2c6e..0000000000
--- a/src/mainboard/starlabs/starfighter/spd/64gb-mtl-5500.spd.hex
+++ /dev/null
@@ -1,32 +0,0 @@
-23 10 15 0E 16 2A F9 08 00 40 00 00 09 01 00 00
-48 00 0B FF 92 55 05 00 AE 00 90 A8 90 C0 08 60
-04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 4B 00 50 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 7F 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 20 00 00 00 20 20 20 20 20 20 20
-20 20 20 20 20 20 20 20 20 20 20 20 20 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
diff --git a/src/mainboard/starlabs/starfighter/spd/64gb-mtl-5500.spd.json b/src/mainboard/starlabs/starfighter/spd/64gb-mtl-5500.spd.json
new file mode 100644
index 0000000000..4f1f8f19ae
--- /dev/null
+++ b/src/mainboard/starlabs/starfighter/spd/64gb-mtl-5500.spd.json
@@ -0,0 +1,18 @@
+// Generated by:
+// util/scripts/spd-decode src/mainboard/starlabs/starfighter/spd/64gb-mtl-5500.spd.hex --pretty --name 64gb-mtl-5500
+
+{
+	"parts": [
+		{
+			"name": "64gb-mtl-5500",
+			"attribs": {
+				"densityPerDieGb": 16,
+				"diesPerPackage": 8,
+				"bitWidthPerChannel": 8,
+				"ranksPerChannel": 2,
+				"speedMbps": 5500,
+				"lp5x": true
+			}
+		}
+	]
+}
diff --git a/src/mainboard/starlabs/starfighter/spd/64gb-mtl-6400.spd.hex b/src/mainboard/starlabs/starfighter/spd/64gb-mtl-6400.spd.hex
deleted file mode 100644
index a3ca8d3afd..0000000000
--- a/src/mainboard/starlabs/starfighter/spd/64gb-mtl-6400.spd.hex
+++ /dev/null
@@ -1,32 +0,0 @@
-23 10 15 0E 16 2A F9 08 00 40 00 00 09 01 00 00
-48 00 0A FF 92 55 05 00 AA 00 90 A8 90 C0 08 60
-04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 7F 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 20 00 00 00 20 20 20 20 20 20 20
-20 20 20 20 20 20 20 20 20 20 20 20 20 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
diff --git a/src/mainboard/starlabs/starfighter/spd/64gb-mtl-6400.spd.json b/src/mainboard/starlabs/starfighter/spd/64gb-mtl-6400.spd.json
new file mode 100644
index 0000000000..42da8cf8a6
--- /dev/null
+++ b/src/mainboard/starlabs/starfighter/spd/64gb-mtl-6400.spd.json
@@ -0,0 +1,18 @@
+// Generated by:
+// util/scripts/spd-decode src/mainboard/starlabs/starfighter/spd/64gb-mtl-6400.spd.hex --pretty --name 64gb-mtl-6400
+
+{
+	"parts": [
+		{
+			"name": "64gb-mtl-6400",
+			"attribs": {
+				"densityPerDieGb": 16,
+				"diesPerPackage": 8,
+				"bitWidthPerChannel": 8,
+				"ranksPerChannel": 2,
+				"speedMbps": 6400,
+				"lp5x": true
+			}
+		}
+	]
+}
diff --git a/src/mainboard/starlabs/starfighter/spd/64gb-mtl-7500.spd.hex b/src/mainboard/starlabs/starfighter/spd/64gb-mtl-7500.spd.hex
deleted file mode 100644
index ee280c8ca2..0000000000
--- a/src/mainboard/starlabs/starfighter/spd/64gb-mtl-7500.spd.hex
+++ /dev/null
@@ -1,32 +0,0 @@
-23 10 15 0E 16 2A F9 08 00 40 00 00 09 01 00 00
-48 00 08 FF 92 55 05 00 AA 00 90 A8 90 C0 08 60
-04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 7F 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 20 00 00 00 20 20 20 20 20 20 20
-20 20 20 20 20 20 20 20 20 20 20 20 20 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
diff --git a/src/mainboard/starlabs/starfighter/spd/64gb-mtl-7500.spd.json b/src/mainboard/starlabs/starfighter/spd/64gb-mtl-7500.spd.json
new file mode 100644
index 0000000000..d7efe0cbcf
--- /dev/null
+++ b/src/mainboard/starlabs/starfighter/spd/64gb-mtl-7500.spd.json
@@ -0,0 +1,18 @@
+// Generated by:
+// util/scripts/spd-decode src/mainboard/starlabs/starfighter/spd/64gb-mtl-7500.spd.hex --pretty --name 64gb-mtl-7500
+
+{
+	"parts": [
+		{
+			"name": "64gb-mtl-7500",
+			"attribs": {
+				"densityPerDieGb": 16,
+				"diesPerPackage": 8,
+				"bitWidthPerChannel": 8,
+				"ranksPerChannel": 2,
+				"speedMbps": 7500,
+				"lp5x": true
+			}
+		}
+	]
+}
diff --git a/src/mainboard/starlabs/starfighter/spd/Makefile.mk b/src/mainboard/starlabs/starfighter/spd/Makefile.mk
index 4bce4845b9..6684c6db83 100644
--- a/src/mainboard/starlabs/starfighter/spd/Makefile.mk
+++ b/src/mainboard/starlabs/starfighter/spd/Makefile.mk
@@ -1,5 +1,7 @@
 ## SPDX-License-Identifier: GPL-2.0-only
 
+SPD_GEN_MEM_TECH := lp5
+
 ifeq ($(CONFIG_BOARD_STARLABS_STARFIGHTER_RPL),y)
 # RPL memory configs (selected by straps) with runtime speed selection.
 # CBFS index order is (per config): 5500, 6400, 7500.

From 94168f10bce1e06699acea65419416f8af4fa10e Mon Sep 17 00:00:00 2001
From: Subrata Banik <subratabanik@google.com>
Date: Thu, 12 Mar 2026 17:57:00 +0000
Subject: [PATCH 3683/3886] Reland "mb/google/bluey: Configure GPIOs for USB
 camera"

Additionally, guard USB camera GPIO enablement using dedicated
Kconfig option.

This reverts commit bbbc655b152b6900b8a9c308d32bdfcdb710a0d2.

Reason for revert: FW should enable the GPIO_USB_CAM_ENABLE (206).

Change-Id: I7966240939c51a4be7027debb0a66d3e11cb75cc
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91660
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
---
 src/mainboard/google/bluey/Kconfig     | 10 ++++++++++
 src/mainboard/google/bluey/board.h     |  4 ++++
 src/mainboard/google/bluey/mainboard.c |  9 +++++++++
 3 files changed, 23 insertions(+)

diff --git a/src/mainboard/google/bluey/Kconfig b/src/mainboard/google/bluey/Kconfig
index 9d7a5df5a9..727e1e8f7a 100644
--- a/src/mainboard/google/bluey/Kconfig
+++ b/src/mainboard/google/bluey/Kconfig
@@ -32,6 +32,7 @@ config BOARD_GOOGLE_MODEL_QUENBI
 	select BOARD_GOOGLE_BASEBOARD_BLUEY
 	select BOARD_ROMSIZE_KB_32768
 	select EC_GOOGLE_CHROMEEC_BATTERY_SOC_DYNAMIC
+	select MAINBOARD_HAS_CAMERA_VIA_USB
 	select MAINBOARD_HAS_CHROME_EC
 	select MAINBOARD_HAS_FINGERPRINT_VIA_SPI
 	select MAINBOARD_HAS_GOOGLE_TPM
@@ -42,6 +43,7 @@ config BOARD_GOOGLE_MODEL_QUARTZ
 	select BOARD_ROMSIZE_KB_32768
 	select EC_GOOGLE_CHROMEEC_BATTERY_SOC_DYNAMIC
 	select EC_GOOGLE_CHROMEEC_LED_CONTROL
+	select MAINBOARD_HAS_CAMERA_VIA_USB
 	select MAINBOARD_HAS_CHROME_EC
 	select MAINBOARD_HAS_FINGERPRINT_VIA_SPI
 	select MAINBOARD_HAS_GOOGLE_TPM
@@ -68,6 +70,7 @@ config BOARD_GOOGLE_MODEL_MICA
 	select BOARD_ROMSIZE_KB_32768
 	select EC_GOOGLE_CHROMEEC_LED_CONTROL
 	select EC_GOOGLE_CHROMEEC_BATTERY_SOC_DYNAMIC
+	select MAINBOARD_HAS_CAMERA_VIA_USB
 	select MAINBOARD_HAS_CHROME_EC
 	select MAINBOARD_HAS_FINGERPRINT_VIA_USB
 	select MAINBOARD_HAS_GOOGLE_TPM
@@ -154,6 +157,13 @@ config MAINBOARD_HAS_CHROME_EC
 	help
 	  Enable this option if your mainboard is equipped with Chrome EC.
 
+config MAINBOARD_HAS_CAMERA_VIA_USB
+	bool
+	default n
+	help
+	  Enable this option if your mainboard's onboard camera
+	  is connected via the USB interface.
+
 config MAINBOARD_VENDOR
 	string
 	default "Google"
diff --git a/src/mainboard/google/bluey/board.h b/src/mainboard/google/bluey/board.h
index 65436b60d7..361aa6587c 100644
--- a/src/mainboard/google/bluey/board.h
+++ b/src/mainboard/google/bluey/board.h
@@ -47,6 +47,10 @@
 #define GPIO_SD_CD_L		GPIO(71)
 #endif
 
+/* USB Camera specific GPIOs */
+#define GPIO_USB_CAM_RESET_L	GPIO(10)
+#define GPIO_USB_CAM_ENABLE	GPIO(206)
+
 /* USB-C1 port specific GPIOs */
 #define GPIO_USB_C1_EN_PP3300		GPIO(186)
 #define GPIO_USB_C1_EN_PP1800		GPIO(175)
diff --git a/src/mainboard/google/bluey/mainboard.c b/src/mainboard/google/bluey/mainboard.c
index b9c055e6d5..f4f076ef2e 100644
--- a/src/mainboard/google/bluey/mainboard.c
+++ b/src/mainboard/google/bluey/mainboard.c
@@ -76,6 +76,12 @@ static bool is_low_power_boot_with_charger(void)
 	return ret;
 }
 
+static void enable_usb_camera(void)
+{
+	gpio_output(GPIO_USB_CAM_RESET_L, 1);
+	gpio_output(GPIO_USB_CAM_ENABLE, 1);
+}
+
 static void setup_usb_typec(void)
 {
 	gpio_output(GPIO_USB_C1_EN_PP3300, 1);
@@ -109,6 +115,9 @@ static void setup_audio(void)
 static void setup_usb(void)
 {
 	setup_usb_typec();
+
+	if (CONFIG(MAINBOARD_HAS_CAMERA_VIA_USB))
+		enable_usb_camera();
 }
 
 static void setup_usb_late(void *unused)

From 07e4cc0cc362a7930d750bf9c1155c09a7010271 Mon Sep 17 00:00:00 2001
From: Subrata Banik <subratabanik@google.com>
Date: Wed, 11 Mar 2026 14:16:11 +0530
Subject: [PATCH 3684/3886] mb/google/fatcat: Set CPU ratio override in
 devicetree

Configure "cpu_ratio_override" to 0x20 (32) for the Fatcat baseboard.
This ensures the Panther Lake SoC initializes with the correct
base frequency ratio to meet the performance and thermal targets
defined for this hardware revision.

BUG=none
BRANCH=none
TEST=Build and boot Fatcat; verify CPU base frequency has updated.

Change-Id: I7ea6c7dccaf731bab1256b3297d83518ceea532c
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91648
Reviewed-by: Pranava Y N <pranavayn@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 .../google/fatcat/variants/baseboard/fatcat/devicetree.cb      | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/src/mainboard/google/fatcat/variants/baseboard/fatcat/devicetree.cb b/src/mainboard/google/fatcat/variants/baseboard/fatcat/devicetree.cb
index 14dbd34db6..7369239307 100644
--- a/src/mainboard/google/fatcat/variants/baseboard/fatcat/devicetree.cb
+++ b/src/mainboard/google/fatcat/variants/baseboard/fatcat/devicetree.cb
@@ -62,6 +62,9 @@ chip soc/intel/pantherlake
 	# Setting TCC of 100C = Tj max (110) - TCC_Offset (10)
 	register "tcc_offset" = "10"
 
+	# CPU Ratio Override
+	register "cpu_ratio_override" = "0x20"
+
 	# Enable Energy Reporting
 	register "pch_pm_energy_report_enable" = "true"
 

From faf12bcacdb777f4cc949a9d17d86dd44e4e6c4c Mon Sep 17 00:00:00 2001
From: Lukas Wunner <lukas@wunner.de>
Date: Sun, 15 Feb 2026 14:43:49 +0100
Subject: [PATCH 3685/3886] soc/intel/skl: Allow disabling CLKREQ#
 independently of SrcClk

On Skylake mainboards, enablement of the Source Clock of a PCIe Root
Port is currently dependent on enablement of CLKREQ# in the devicetree.

However it may be desirable to disable CLKREQ# but still keep the Source
Clock enabled.  Specifically, that's the recommended workaround for
erratum 47 of Sunrise Point-LP PCHs, which concerns exit instability from
ASPM L1 state:

   "disable the associated PCH SRCCLKREQ# signal to keep the PCIe clock
    active during L1"
    https://www.intel.de/content/dam/www/public/us/en/documents/specification-updates/100-series-chipset-spec-update.pdf

Therefore, key Source Clock enablement off of Root Port enablement in
the devicetree, rather than CLKREQ# enablement.  A subsequent commit
takes advantage of this to implement the workaround on Google Pixelbook
Eve mainboards.

Change-Id: I9b69357c59bad3392da85e0629a9d368524daffd
Signed-off-by: Lukas Wunner <lukas@wunner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91650
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
---
 src/soc/intel/skylake/chip.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/src/soc/intel/skylake/chip.c b/src/soc/intel/skylake/chip.c
index a884035f59..964c1264aa 100644
--- a/src/soc/intel/skylake/chip.c
+++ b/src/soc/intel/skylake/chip.c
@@ -310,8 +310,9 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
 	 * all the enabled PCIe root ports, invalid(0x1F) is set for
 	 * disabled PCIe root ports.
 	 */
+	u32 enable_mask = pcie_rp_enable_mask(get_pch_pcie_rp_table());
 	for (i = 0; i < CONFIG_MAX_ROOT_PORTS; i++) {
-		if (config->PcieRpClkReqSupport[i])
+		if (enable_mask & BIT(i))
 			params->PcieRpClkSrcNumber[i] =
 				config->PcieRpClkSrcNumber[i];
 		else

From 71effade585632acbd6ed5181067287afca2e338 Mon Sep 17 00:00:00 2001
From: Lukas Wunner <lukas@wunner.de>
Date: Tue, 10 Feb 2026 17:29:47 +0100
Subject: [PATCH 3686/3886] mb/google/eve: Work around CLKREQ# timing erratum
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

The Sunrise Point-LP PCH built into the Google Pixelbook Eve suffers
from an erratum where the "CLKREQ# asserted to clock active timing" may
exceed the maximum specification, resulting in exit instability from
ASPM L1 state.

This is documented in erratum 47 of the "Intel 100 Series and C230
Series Chipset Family Platform Controller Hub Specification Update"
(Revision 015, December 2018):

https://www.intel.de/content/dam/www/public/us/en/documents/specification-updates/100-series-chipset-spec-update.pdf

The Specification Update constrains applicability of the erratum to
Endpoints which do not support LTR or advertise an LTR value of less
than 1 usec.  The reason is that the PCH needs about 1 usec for the
clock to become active after CLKREQ# asserted.  For devices without LTR
support, the maximum is 400 nsec (T_CRLon, PCIe CEM r6.0.1 sec 2.11.2).

The Pixelbook Eve has an Intel 7265 Stone Peak wifi card attached to
Root Port 1.  It seems this wifi card triggers the erratum:  There are
several reports that the wifi card is no longer usable since commit
torvalds/linux@4d4c10f763d7 ("PCI: Explicitly put devices into D0 when
initializing").

Briefly, coreboot enables all ASPM features on boot, the kernel used to
disable certain ASPM features prior to the commit, now no longer does
and the erratum is thus exposed.  (The commit changed the cached power
state of the wifi card from PCI_UNKNOWN to PCI_D0, which now causes
pcie_config_aspm_link() to no longer disable L1 PCI PM.)

Apply the recommended workaround, which is to disable the associated PCH
CLKREQ# signal to keep the PCIe clock active during L1.

BUG=https://github.com/MrChromebox/firmware/issues/786
TEST=https://bugzilla.kernel.org/show_bug.cgi?id=220705#c31

Change-Id: I00c6555c2b93f46971ea8e4344f8990f86b03a3d
Signed-off-by: Lukas Wunner <lukas@wunner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91651
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
---
 src/mainboard/google/eve/devicetree.cb | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/src/mainboard/google/eve/devicetree.cb b/src/mainboard/google/eve/devicetree.cb
index 41c5cb0377..8dbb25fe34 100644
--- a/src/mainboard/google/eve/devicetree.cb
+++ b/src/mainboard/google/eve/devicetree.cb
@@ -336,7 +336,9 @@ chip soc/intel/skylake
 			end
 		end # I2C #4
 		device ref pcie_rp1	on
-			register "PcieRpClkReqSupport[0]" = "true"
+			# Disable CLKREQ# to keep PCIe clock active during L1
+			# (Erratum 47, Intel 100 Series Chipset Spec Update)
+			register "PcieRpClkReqSupport[0]" = "false"
 			register "PcieRpClkReqNumber[0]" = "1"
 			register "PcieRpAdvancedErrorReporting[0]" = "1"
 			register "PcieRpLtrEnable[0]" = "true"

From a616a589a236147fac24f1ac718afab11f2bc035 Mon Sep 17 00:00:00 2001
From: Alicja Michalska <alicja.michalska@9elements.com>
Date: Sun, 1 Mar 2026 00:40:09 +0100
Subject: [PATCH 3687/3886] vc/amd/opensil: Add Phoenix OpenSIL POC directory
 as a copy of Genoa

Based on genoa_poc, this patch adds directory structure for Phoenix
OpenSIL as well as git submodule needed to build it.

Subsequent patches will begin adjusting this directory to Phoenix (Zen4)
silicon.

Change-Id: I04de276c1567c20d1e852efe220efa8131f53843
Signed-off-by: Alicja Michalska <alicja.michalska@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91480
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 .gitmodules                                   |   5 +
 src/vendorcode/amd/opensil/Kconfig            |   8 +
 src/vendorcode/amd/opensil/Makefile.mk        |   1 +
 .../amd/opensil/phoenix_poc/Makefile.mk       |  18 ++
 src/vendorcode/amd/opensil/phoenix_poc/acpi.c |  24 +++
 .../amd/opensil/phoenix_poc/filter.h          |  23 ++
 .../amd/opensil/phoenix_poc/memmap.c          |  57 +++++
 .../opensil/phoenix_poc/meson_cross.template  |  35 +++
 .../amd/opensil/phoenix_poc/mpio/Makefile.mk  |   5 +
 .../amd/opensil/phoenix_poc/mpio/chip.c       | 202 ++++++++++++++++++
 .../amd/opensil/phoenix_poc/mpio/chip.h       |  71 ++++++
 .../amd/opensil/phoenix_poc/opensil           |   1 +
 .../phoenix_poc/opensil_config.template       |   5 +
 .../amd/opensil/phoenix_poc/opensil_console.c |  44 ++++
 .../amd/opensil/phoenix_poc/opensil_console.h |   9 +
 .../amd/opensil/phoenix_poc/ramstage.c        | 180 ++++++++++++++++
 .../amd/opensil/phoenix_poc/romstage.c        |  17 ++
 17 files changed, 705 insertions(+)
 create mode 100644 src/vendorcode/amd/opensil/phoenix_poc/Makefile.mk
 create mode 100644 src/vendorcode/amd/opensil/phoenix_poc/acpi.c
 create mode 100644 src/vendorcode/amd/opensil/phoenix_poc/filter.h
 create mode 100644 src/vendorcode/amd/opensil/phoenix_poc/memmap.c
 create mode 100644 src/vendorcode/amd/opensil/phoenix_poc/meson_cross.template
 create mode 100644 src/vendorcode/amd/opensil/phoenix_poc/mpio/Makefile.mk
 create mode 100644 src/vendorcode/amd/opensil/phoenix_poc/mpio/chip.c
 create mode 100644 src/vendorcode/amd/opensil/phoenix_poc/mpio/chip.h
 create mode 160000 src/vendorcode/amd/opensil/phoenix_poc/opensil
 create mode 100644 src/vendorcode/amd/opensil/phoenix_poc/opensil_config.template
 create mode 100644 src/vendorcode/amd/opensil/phoenix_poc/opensil_console.c
 create mode 100644 src/vendorcode/amd/opensil/phoenix_poc/opensil_console.h
 create mode 100644 src/vendorcode/amd/opensil/phoenix_poc/ramstage.c
 create mode 100644 src/vendorcode/amd/opensil/phoenix_poc/romstage.c

diff --git a/.gitmodules b/.gitmodules
index 7a8d618619..dcb6541191 100644
--- a/.gitmodules
+++ b/.gitmodules
@@ -70,7 +70,12 @@
 [submodule "3rdparty/open-power-signing-utils"]
 	path = 3rdparty/open-power-signing-utils
 	url = https://review.coreboot.org/open-power-signing-utils.git
+[submodule "src/vendorcode/amd/opensil/phoenix_poc/opensil"]
+	path = src/vendorcode/amd/opensil/phoenix_poc/opensil
+	url = https://github.com/openSIL/openSIL.git
+	branch = phoenix_poc
 [submodule "src/vendorcode/amd/opensil/turin_poc/opensil"]
 	path = src/vendorcode/amd/opensil/turin_poc/opensil
 	url = https://github.com/openSIL/openSIL.git
 	branch = turin_poc
+
diff --git a/src/vendorcode/amd/opensil/Kconfig b/src/vendorcode/amd/opensil/Kconfig
index 735d6e1feb..580ea83159 100644
--- a/src/vendorcode/amd/opensil/Kconfig
+++ b/src/vendorcode/amd/opensil/Kconfig
@@ -15,6 +15,12 @@ config SOC_AMD_OPENSIL_GENOA_POC
 	  Select this on SoCs that use the Genoa proof of concept version of
 	  openSIL.
 
+config SOC_AMD_OPENSIL_PHOENIX_POC
+	bool
+	help
+	  Select this on SoCs that use the Phoenix proof of concept version of
+	  openSIL.
+
 config SOC_AMD_OPENSIL_TURIN_POC
 	bool
 	help
@@ -25,6 +31,7 @@ config AMD_OPENSIL_PATH
 	string "Path to openSIL source"
 	depends on !SOC_AMD_OPENSIL_STUB
 	default "$(top)/src/vendorcode/amd/opensil/genoa_poc/opensil" if SOC_AMD_OPENSIL_GENOA_POC
+	default "$(top)/src/vendorcode/amd/opensil/phoenix_poc/opensil" if SOC_AMD_OPENSIL_PHOENIX_POC
 	default "$(top)/src/vendorcode/amd/opensil/turin_poc/opensil" if SOC_AMD_OPENSIL_TURIN_POC
 	help
 	  Set to the path of the openSIL directory containing meson.build.
@@ -33,6 +40,7 @@ config AMD_OPENSIL_PATH
 config AMD_OPENSIL_MPIO_CHIP_H_FILE
 	string "Location of specific MPIO chip.h implementation"
 	default "$(top)/src/vendorcode/amd/opensil/genoa_poc/mpio/chip.h" if SOC_AMD_OPENSIL_GENOA_POC
+	default "$(top)/src/vendorcode/amd/opensil/phoenix_poc/mpio/chip.h" if SOC_AMD_OPENSIL_PHOENIX_POC
 	default "$(top)/src/vendorcode/amd/opensil/turin_poc/mpio/chip.h" if SOC_AMD_OPENSIL_TURIN_POC
 	default "$(top)/src/vendorcode/amd/opensil/stub/mpio/chip.h"
 	help
diff --git a/src/vendorcode/amd/opensil/Makefile.mk b/src/vendorcode/amd/opensil/Makefile.mk
index beebaf5782..751e6ebf4b 100644
--- a/src/vendorcode/amd/opensil/Makefile.mk
+++ b/src/vendorcode/amd/opensil/Makefile.mk
@@ -15,6 +15,7 @@ endif
 opensil_dir := $(call strip_quotes,$(CONFIG_AMD_OPENSIL_PATH))
 
 subdirs-$(CONFIG_SOC_AMD_OPENSIL_GENOA_POC) += genoa_poc
+subdirs-$(CONFIG_SOC_AMD_OPENSIL_PHOENIX_POC) += phoenix_poc
 subdirs-$(CONFIG_SOC_AMD_OPENSIL_TURIN_POC) += turin_poc
 
 ifeq ($(CONFIG_ARCH_RAMSTAGE_X86_32),y)
diff --git a/src/vendorcode/amd/opensil/phoenix_poc/Makefile.mk b/src/vendorcode/amd/opensil/phoenix_poc/Makefile.mk
new file mode 100644
index 0000000000..5d36d56f93
--- /dev/null
+++ b/src/vendorcode/amd/opensil/phoenix_poc/Makefile.mk
@@ -0,0 +1,18 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
+subdirs-y += mpio
+
+CPPFLAGS_common += -I$(opensil_dir)/Include -I$(opensil_dir)/xUSL -I$(opensil_dir)/xUSL/Include -I$(opensil_dir)/xUSL/FCH -I$(opensil_dir)/xUSL/FCH/Common -I$(opensil_dir)/xSIM -I$(opensil_dir)/xPRF
+
+romstage-y += opensil_console.c
+romstage-y += romstage.c
+
+ramstage-y += acpi.c
+ramstage-y += memmap.c
+ramstage-y += opensil_console.c
+ramstage-y += ramstage.c
+
+$(obj)/romstage/vendorcode/amd/opensil/phoenix_poc/opensil_console.o: CFLAGS_romstage += -D_MSC_EXTENSIONS=0 -DHAS_STRING_H=1 -Wno-unknown-pragmas
+$(obj)/romstage/vendorcode/amd/opensil/phoenix_poc/romstage.o: CFLAGS_romstage += -D_MSC_EXTENSIONS=0 -DHAS_STRING_H=1 -Wno-unknown-pragmas
+
+$(obj)/ramstage/vendorcode/amd/opensil/phoenix_poc/opensil_console.o: CFLAGS_ramstage += -D_MSC_EXTENSIONS=0 -DHAS_STRING_H=1 -Wno-unknown-pragmas
diff --git a/src/vendorcode/amd/opensil/phoenix_poc/acpi.c b/src/vendorcode/amd/opensil/phoenix_poc/acpi.c
new file mode 100644
index 0000000000..fcdf167c12
--- /dev/null
+++ b/src/vendorcode/amd/opensil/phoenix_poc/acpi.c
@@ -0,0 +1,24 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <acpi/acpi.h>
+#include <Sil-api.h>
+#include <SilCommon.h>
+#include <xSIM-api.h>
+#include <FCH/Common/FchCommonCfg.h>
+
+#include "../opensil.h"
+
+void opensil_fill_fadt(acpi_fadt_t *fadt)
+{
+	FCHHWACPI_INPUT_BLK *blk = SilFindStructure(SilId_FchHwAcpiP,  0);
+
+	fadt->pm1a_evt_blk = blk->AcpiPm1EvtBlkAddr;
+	fadt->pm1a_cnt_blk = blk->AcpiPm1CntBlkAddr;
+	fadt->pm_tmr_blk = blk->AcpiPmTmrBlkAddr;
+	fadt->gpe0_blk = blk->AcpiGpe0BlkAddr;
+}
+
+unsigned long add_opensil_acpi_table(unsigned long current, acpi_rsdp_t *rsdp)
+{
+	return current;
+}
diff --git a/src/vendorcode/amd/opensil/phoenix_poc/filter.h b/src/vendorcode/amd/opensil/phoenix_poc/filter.h
new file mode 100644
index 0000000000..f0817f7502
--- /dev/null
+++ b/src/vendorcode/amd/opensil/phoenix_poc/filter.h
@@ -0,0 +1,23 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+/* Keep this in sync with openSIL SilCommon.h file */
+#define DEBUG_FILTER_APOB       0x00000001UL
+#define DEBUG_FILTER_NBIO       0x00000002UL
+#define DEBUG_FILTER_CCX        0x00000004UL
+#define DEBUG_FILTER_SMU        0x00000008UL
+#define DEBUG_FILTER_DF         0x00000010UL
+#define DEBUG_FILTER_MEM        0x00000040UL
+#define DEBUG_FILTER_FCH        0x00000080UL
+#define DEBUG_FILTER_RAS        0x00000100UL
+
+#define SIL_DEBUG(topic) (CONFIG(OPENSIL_DEBUG_##topic) ? DEBUG_FILTER_##topic : 0)
+
+#define SIL_DEBUG_MODULE_FILTER ( \
+	  SIL_DEBUG(APOB) | \
+	  SIL_DEBUG(NBIO) | \
+	  SIL_DEBUG(CCX) | \
+	  SIL_DEBUG(SMU) | \
+	  SIL_DEBUG(DF) | \
+	  SIL_DEBUG(MEM) | \
+	  SIL_DEBUG(FCH) | \
+	  SIL_DEBUG(RAS) )
diff --git a/src/vendorcode/amd/opensil/phoenix_poc/memmap.c b/src/vendorcode/amd/opensil/phoenix_poc/memmap.c
new file mode 100644
index 0000000000..eed1be7e5f
--- /dev/null
+++ b/src/vendorcode/amd/opensil/phoenix_poc/memmap.c
@@ -0,0 +1,57 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <SilCommon.h>
+#include <Sil-api.h> // needed above ApobCmn.h
+#include <ApobCmn.h>
+#include <xPRF-api.h>
+
+#include "../opensil.h"
+
+_Static_assert(sizeof(uint32_t) == sizeof(((MEMORY_HOLE_DESCRIPTOR){0}).Type),
+	"Unexpected size of MEMORY_HOLE_TYPES in the MEMORY_HOLE_DESCRIPTOR "
+	"struct which doesn't match the code in drivers/amd/opensil/memmap.c");
+
+const char *opensil_get_hole_info_type(uint32_t type)
+{
+	const struct hole_type {
+		MEMORY_HOLE_TYPES type;
+		const char *string;
+	} types[] = {
+		{UMA, "UMA"},
+		{MMIO, "MMIO"},
+		{PrivilegedDRAM, "PrivilegedDRAM"},
+		{Reserved1TbRemap, "Reserved1TbRemap"},
+		{ReservedSLink, "ReservedSLink"},
+		{ReservedSLinkAlignment, "ReservedSLinkAlignment"},
+		{ReservedDrtm, "ReservedDrtm"},
+		{ReservedCvip, "ReservedCvip"},
+		{ReservedSmuFeatures, "ReservedSmuFeatures"},
+		{ReservedFwtpm, "ReservedFwtpm"},
+		{ReservedMpioC20, "ReservedMpioC20"},
+		{ReservedNbif, "ReservedNbif"},
+		{ReservedCxl, "ReservedCxl"},
+		{ReservedCxlAlignment, "ReservedCxlAlignment"},
+		{ReservedCpuTmr, "ReservedCpuTmr"},
+		{ReservedRasEinj, "ReservedRasEinj"},
+		{MaxMemoryHoleTypes, "MaxMemoryHoleTypes"},
+	};
+
+	int i;
+	MEMORY_HOLE_TYPES enum_type = (MEMORY_HOLE_TYPES)type; // Cast int to enum
+	for (i = 0; i < ARRAY_SIZE(types); i++)
+		if (enum_type == types[i].type)
+			return types[i].string;
+	return "Unknown type";
+}
+
+void opensil_get_hole_info(uint32_t *n_holes, uint64_t *top_of_mem, void **hole_info)
+{
+        SIL_STATUS status = xPrfGetSystemMemoryMap(n_holes, top_of_mem, hole_info);
+	SIL_STATUS_report("xPrfGetSystemMemoryMap", status);
+	// Make sure hole_info does not get initialized to something odd by xPRF on failure
+	if (status != SilPass) {
+		*hole_info = NULL;
+		*n_holes = 0;
+		*top_of_mem = 0;
+	}
+}
diff --git a/src/vendorcode/amd/opensil/phoenix_poc/meson_cross.template b/src/vendorcode/amd/opensil/phoenix_poc/meson_cross.template
new file mode 100644
index 0000000000..6473b65225
--- /dev/null
+++ b/src/vendorcode/amd/opensil/phoenix_poc/meson_cross.template
@@ -0,0 +1,35 @@
+[binaries]
+c = '##COMPILER##'
+ar = '##AR##'
+nasm = '##NASM##'
+
+[built-in options]
+c_args = ['-nostdinc',
+          '-I##OBJPATH##',
+          '-I##COREBOOT_DIR##/src/include',
+          '-I##COREBOOT_DIR##/src/arch/x86/include',
+          '-I##COREBOOT_DIR##/src/commonlib/include',
+          '-I##COREBOOT_DIR##/src/commonlib/bsd/include',
+          '-include', '##COREBOOT_DIR##/src/include/kconfig.h',
+          '-include', '##OBJPATH##/config.h',
+          '-include', '##COREBOOT_DIR##/src/commonlib/bsd/include/commonlib/bsd/compiler.h',
+          '-include', '##OPENSIL_DIR##/../filter.h',
+          '-DHAS_STRING_H=1',
+          # openSIL isn't compatible with coreboot's assert implementation, so use special case
+          '-D_PORTING_H_=1',
+          '-DSIL_DEBUG_ENABLE=##SIL_DEBUG_ENABLE##',
+          # openSIL uses coreboot assert which uses printk which warns about unused-param
+          '-Wno-unused-parameter',
+          # ubiquitous problem in openSIL
+          '-Wno-missing-field-initializers',
+          ##CLANG_ARGS##
+         ]
+
+[host_machine]
+system = 'linux'
+cpu_family = '##CPU_FAMILY##'
+cpu = '##CPU##'
+endian = 'little'
+
+[properties]
+is32bit = ##IS32BIT##
diff --git a/src/vendorcode/amd/opensil/phoenix_poc/mpio/Makefile.mk b/src/vendorcode/amd/opensil/phoenix_poc/mpio/Makefile.mk
new file mode 100644
index 0000000000..523ebe73c8
--- /dev/null
+++ b/src/vendorcode/amd/opensil/phoenix_poc/mpio/Makefile.mk
@@ -0,0 +1,5 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
+ramstage-y += chip.c
+
+$(obj)/ramstage/vendorcode/amd/opensil/phoenix_poc/mpio/chip.o: CFLAGS_ramstage += -D_MSC_EXTENSIONS=0 -DHAS_STRING_H=1 -Wno-unknown-pragmas
diff --git a/src/vendorcode/amd/opensil/phoenix_poc/mpio/chip.c b/src/vendorcode/amd/opensil/phoenix_poc/mpio/chip.c
new file mode 100644
index 0000000000..587ab81e02
--- /dev/null
+++ b/src/vendorcode/amd/opensil/phoenix_poc/mpio/chip.c
@@ -0,0 +1,202 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <device/device.h>
+#include <device/pci_def.h>
+#include <Mpio/Common/MpioStructs.h>
+#include <Mpio/MpioClass-api.h>
+#include <NBIO/NbioClass-api.h>
+#include <RcMgr/DfX/RcManager4-api.h>
+#include <vendorcode/amd/opensil/opensil.h>
+#include <xSIM-api.h>
+
+#include "chip.h"
+
+static void mpio_params_config(void)
+{
+	MPIOCLASS_INPUT_BLK *mpio_data = SilFindStructure(SilId_MpioClass, 0);
+	mpio_data->CfgDxioClockGating                  = 1;
+	mpio_data->PcieDxioTimingControlEnable         = 0;
+	mpio_data->PCIELinkReceiverDetectionPolling    = 0;
+	mpio_data->PCIELinkResetToTrainingTime         = 0;
+	mpio_data->PCIELinkL0Polling                   = 0;
+	mpio_data->PCIeExactMatchEnable                = 0;
+	mpio_data->DxioPhyValid                        = 1;
+	mpio_data->DxioPhyProgramming                  = 1;
+	mpio_data->CfgSkipPspMessage                   = 1;
+	mpio_data->DxioSaveRestoreModes                = 0xff;
+	mpio_data->AmdAllowCompliance                  = 0;
+	mpio_data->AmdAllowCompliance                  = 0xff;
+	mpio_data->SrisEnableMode                      = 0xff;
+	mpio_data->SrisSkipInterval                    = 0;
+	mpio_data->SrisSkpIntervalSel                  = 1;
+	mpio_data->SrisCfgType                         = 0;
+	mpio_data->SrisAutoDetectMode                  = 0xff;
+	mpio_data->SrisAutodetectFactor                = 0;
+	mpio_data->SrisLowerSkpOsGenSup                = 0;
+	mpio_data->SrisLowerSkpOsRcvSup                = 0;
+	mpio_data->AmdCxlOnAllPorts                    = 1;
+	mpio_data->CxlCorrectableErrorLogging          = 1;
+	mpio_data->CxlUnCorrectableErrorLogging        = 1;
+	  // This is also available in Nbio. How to handle duplicate entries?
+	mpio_data->CfgAEREnable                        = 1;
+	mpio_data->CfgMcCapEnable                      = 0;
+	mpio_data->CfgRcvErrEnable                     = 0;
+	mpio_data->EarlyBmcLinkTraining                = 1;
+	mpio_data->SurpriseDownFeature                 = 1;
+	mpio_data->LcMultAutoSpdChgOnLastRateEnable    = 0;
+	mpio_data->AmdRxMarginEnabled                  = 1;
+	mpio_data->CfgPcieCVTestWA                     = 1;
+	mpio_data->CfgPcieAriSupport                   = 1;
+	mpio_data->CfgNbioCTOtoSC                      = 0;
+	mpio_data->CfgNbioCTOIgnoreError               = 1;
+	mpio_data->CfgNbioSsid                         = 0;
+	mpio_data->CfgIommuSsid                        = 0;
+	mpio_data->CfgPspccpSsid                       = 0;
+	mpio_data->CfgNtbccpSsid                       = 0;
+	mpio_data->CfgNbifF0Ssid                       = 0;
+	mpio_data->CfgNtbSsid                          = 0;
+	mpio_data->AmdPcieSubsystemDeviceID            = 0x1453;
+	mpio_data->AmdPcieSubsystemVendorID            = 0x1022;
+	mpio_data->GppAtomicOps                        = 1;
+	mpio_data->GfxAtomicOps                        = 1;
+	mpio_data->AmdNbioReportEdbErrors              = 0;
+	mpio_data->OpnSpare                            = 0;
+	mpio_data->AmdPreSilCtrl0                      = 0;
+	mpio_data->MPIOAncDataSupport                  = 1;
+	mpio_data->AfterResetDelay                     = 0;
+	mpio_data->CfgEarlyLink                        = 0;
+	mpio_data->AmdCfgExposeUnusedPciePorts         = 1; // Show all ports
+	mpio_data->CfgForcePcieGenSpeed                = 0;
+	mpio_data->CfgSataPhyTuning                    = 0;
+	mpio_data->PcieLinkComplianceModeAllPorts      = 0;
+	mpio_data->AmdMCTPEnable                       = 0;
+	mpio_data->SbrBrokenLaneAvoidanceSup           = 1;
+	mpio_data->AutoFullMarginSup                   = 1;
+	  // A getter and setter, both are needed for this PCD.
+	mpio_data->AmdPciePresetMask8GtAllPort         = 0xffffffff;
+	  // A getter and setter, both are needed for this PCD.
+	mpio_data->AmdPciePresetMask16GtAllPort        = 0xffffffff;
+	  // A getter and setter, both are needed for this PCD.
+	mpio_data->AmdPciePresetMask32GtAllPort        = 0xffffffff;
+	mpio_data->PcieLinkAspmAllPort                 = 0xff;
+
+	mpio_data->SyncHeaderByPass                    = 1;
+	mpio_data->CxlTempGen5AdvertAltPtcl            = 0;
+
+	/* TODO handle this differently on multisocket */
+	mpio_data->PcieTopologyData.PlatformData[0].Flags = DESCRIPTOR_TERMINATE_LIST;
+	mpio_data->PcieTopologyData.PlatformData[0].PciePortList = mpio_data->PcieTopologyData.PortList;
+}
+
+static void nbio_params_config(void)
+{
+	NBIOCLASS_DATA_BLOCK *nbio_data = SilFindStructure(SilId_NbioClass, 0);
+	NBIOCLASS_INPUT_BLK *input = &nbio_data->NbioInputBlk;
+	input->CfgHdAudioEnable           = false;
+	input->EsmEnableAllRootPorts      = false;
+	input->EsmTargetSpeed             = 16;
+	input->CfgRxMarginPersistenceMode = 1;
+	input->CfgDxioFrequencyVetting    = false;
+	input->CfgSkipPspMessage          = 1;
+	input->CfgEarlyTrainTwoPcieLinks  = false;
+	input->EarlyBmcLinkTraining       = true;
+	input->EdpcEnable                 = 0;
+	input->PcieAerReportMechanism     = 2;
+	input->SevSnpSupport              = false;
+}
+
+static void setup_bmc_lanes(uint8_t lane, uint8_t socket)
+{
+	DFX_RCMGR_INPUT_BLK *rc_mgr_input_block = SilFindStructure(SilId_RcManager,  0);
+	rc_mgr_input_block->BmcSocket = socket;
+	rc_mgr_input_block->EarlyBmcLinkLaneNum = lane;
+
+	NBIOCLASS_DATA_BLOCK *nbio_data = SilFindStructure(SilId_NbioClass, 0);
+	NBIOCLASS_INPUT_BLK *nbio_input = &nbio_data->NbioInputBlk;
+	nbio_input->EarlyBmcLinkSocket         = socket;
+	nbio_input->EarlyBmcLinkLaneNum        = lane;
+	nbio_input->EarlyBmcLinkDie            = 0;
+
+	MPIOCLASS_INPUT_BLK *mpio_data = SilFindStructure(SilId_MpioClass, 0);
+	mpio_data->EarlyBmcLinkSocket                  = socket;
+	mpio_data->EarlyBmcLinkLaneNum                 = lane;
+	mpio_data->EarlyBmcLinkDie                     = 0;
+}
+
+void opensil_mpio_per_device_config(struct device *dev)
+{
+	/* Cache *mpio_data from SilFindStructure */
+	static MPIOCLASS_INPUT_BLK *mpio_data = NULL;
+	if (mpio_data == NULL) {
+		mpio_data = SilFindStructure(SilId_MpioClass, 0);
+	}
+
+	static uint32_t slot_num;
+	const uint32_t domain = dev_get_domain_id(dev);
+	const uint32_t devfn = dev->path.pci.devfn;
+	const struct drivers_amd_opensil_mpio_config *const config = dev->chip_info;
+	printk(BIOS_DEBUG, "Setting MPIO port for domain 0x%x, PCI %d:%d\n",
+	       domain, PCI_SLOT(devfn), PCI_FUNC(devfn));
+
+	if (config->type == IFTYPE_UNUSED) {
+		if (is_dev_enabled(dev)) {
+			printk(BIOS_WARNING, "Unused MPIO chip, disabling PCI device.\n");
+			dev->enabled = false;
+		} else {
+			printk(BIOS_DEBUG, "Unused MPIO chip, skipping.\n");
+		}
+		return;
+	}
+
+	if (config->bmc) {
+		setup_bmc_lanes(config->start_lane, 0); // TODO support multiple sockets
+		return;
+	}
+
+	static int mpio_port = 0;
+	MPIO_PORT_DESCRIPTOR port = { .Flags = DESCRIPTOR_TERMINATE_LIST };
+	if (config->type == IFTYPE_PCIE) {
+		const MPIO_ENGINE_DATA engine_data =
+			MPIO_ENGINE_DATA_INITIALIZER(MpioPcieEngine,
+						     config->start_lane, config->end_lane,
+						     config->hotplug == HotplugDisabled ? 0 : 1,
+						     config->gpio_group);
+		port.EngineData = engine_data;
+		const MPIO_PORT_DATA port_data =
+			MPIO_PORT_DATA_INITIALIZER_PCIE(is_dev_enabled(dev) ?
+								MpioPortEnabled : MpioPortDisabled,
+							PCI_SLOT(devfn),
+							PCI_FUNC(devfn),
+							config->hotplug,
+							config->speed,
+							0, // No backup PCIe speed
+							config->aspm,
+							config->aspm_l1_1,
+							config->aspm_l1_2,
+							config->clock_pm);
+		port.Port = port_data;
+	} else if (config->type == IFTYPE_SATA) {
+		const MPIO_ENGINE_DATA engine_data =
+			MPIO_ENGINE_DATA_INITIALIZER(MpioSATAEngine,
+						     config->start_lane, config->end_lane,
+						     0, // meaningless field
+						     config->gpio_group);
+		port.EngineData = engine_data;
+		const MPIO_PORT_DATA port_data = { .PortPresent = 1 };
+		port.Port = port_data;
+
+	}
+	port.Port.AlwaysExpose = 1;
+	port.Port.SlotNum = ++slot_num;
+	mpio_data->PcieTopologyData.PortList[mpio_port] = port;
+	/* Update TERMINATE list */
+	if (mpio_port > 0)
+		mpio_data->PcieTopologyData.PortList[mpio_port - 1].Flags = 0;
+	mpio_port++;
+}
+
+void opensil_mpio_global_config(void)
+{
+	mpio_params_config();
+	nbio_params_config();
+}
diff --git a/src/vendorcode/amd/opensil/phoenix_poc/mpio/chip.h b/src/vendorcode/amd/opensil/phoenix_poc/mpio/chip.h
new file mode 100644
index 0000000000..0e0e160ce2
--- /dev/null
+++ b/src/vendorcode/amd/opensil/phoenix_poc/mpio/chip.h
@@ -0,0 +1,71 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef OPENSIL_PHOENIX_POC_MPIO_CHIP_H
+#define OPENSIL_PHOENIX_POC_MPIO_CHIP_H
+
+#include <stdint.h>
+
+/*
+ * PHOENIX MPIO mapping
+ * P0 -> [0-15]
+ * G0 -> [16-31]
+ * P1 -> [32-47]
+ * G1 -> [48-63]
+ * P2 -> [64-79]
+ * G2 -> [80-95]
+ * P3 -> [96-111]
+ * G3 -> [112-127]
+ * P4 -> [128-131]
+ * P5 -> [132-136]
+ */
+
+enum mpio_type {
+	IFTYPE_UNUSED,
+	IFTYPE_PCIE,
+	IFTYPE_SATA,
+};
+
+/* Sync with PCIE_HOTPLUG_TYPE */
+enum mpio_hotplug {
+	HotplugDisabled,                             ///< Hotplug disable
+	Basic,                                       ///< Basic Hotplug
+	ServerExpress,                               ///< Server Hotplug Express Module
+	Enhanced,                                    ///< Enhanced
+	Inboard,                                     ///< Inboard
+	ServerEntSSD,                                ///< Server Hotplug Enterprise SSD
+	UBM,                                         ///< UBM Backplane
+	OCP,                                         ///< OCP NIC 3.0
+};
+
+enum pcie_link_speed {
+	MaxSupported,
+	Gen1,
+	Gen2,
+	Gen3,
+	Gen4,
+	Gen5,
+};
+
+/* Sync with PCIE_ASPM_TYPE */
+enum pcie_aspm {
+	aspm_disabled,
+	L0s,
+	L1,
+	L0sL1,
+};
+
+struct drivers_amd_opensil_mpio_config {
+	enum mpio_type type;
+	uint8_t start_lane;
+	uint8_t end_lane;
+	uint8_t gpio_group;
+	enum mpio_hotplug hotplug;
+	enum pcie_link_speed speed;
+	enum pcie_aspm aspm;
+	uint8_t aspm_l1_1 : 1;
+	uint8_t aspm_l1_2 : 1;
+	uint8_t clock_pm : 1;
+	uint8_t bmc : 1;
+};
+
+#endif /* OPENSIL_PHOENIX_POC_MPIO_CHIP_H */
diff --git a/src/vendorcode/amd/opensil/phoenix_poc/opensil b/src/vendorcode/amd/opensil/phoenix_poc/opensil
new file mode 160000
index 0000000000..52b83c56a3
--- /dev/null
+++ b/src/vendorcode/amd/opensil/phoenix_poc/opensil
@@ -0,0 +1 @@
+Subproject commit 52b83c56a3a653c287f5839a5986eda22677f304
diff --git a/src/vendorcode/amd/opensil/phoenix_poc/opensil_config.template b/src/vendorcode/amd/opensil/phoenix_poc/opensil_config.template
new file mode 100644
index 0000000000..2ddd3b4ec1
--- /dev/null
+++ b/src/vendorcode/amd/opensil/phoenix_poc/opensil_config.template
@@ -0,0 +1,5 @@
+CONFIG_PLAT_APOB_ADDRESS=##APOB_BASE##
+CONFIG_PSP_BIOS_BIN_BASE=##BIOS_ENTRY_BASE##
+CONFIG_PSP_BIOS_BIN_SIZE=##BIOS_ENTRY_SIZE##
+CONFIG_PLAT_NUMBER_SOCKETS=1
+CONFIG_SOC_F19M10=y
diff --git a/src/vendorcode/amd/opensil/phoenix_poc/opensil_console.c b/src/vendorcode/amd/opensil/phoenix_poc/opensil_console.c
new file mode 100644
index 0000000000..35e5eeb2b4
--- /dev/null
+++ b/src/vendorcode/amd/opensil/phoenix_poc/opensil_console.c
@@ -0,0 +1,44 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <stdint.h>
+#include <stdio.h>
+#include <string.h>
+#include <console/console.h>
+#include "opensil_console.h"
+#include <SilCommon.h>
+
+static int translate_opensil_debug_level(size_t MsgLevel)
+{
+	switch (MsgLevel) {
+	case SIL_TRACE_ERROR:
+		return BIOS_ERR;
+	case SIL_TRACE_WARNING:
+		return BIOS_WARNING;
+	case SIL_TRACE_ENTRY:
+	case SIL_TRACE_EXIT:
+		return BIOS_SPEW;
+	case SIL_TRACE_INFO:
+		return BIOS_DEBUG;
+	default:
+		return BIOS_NEVER;
+	}
+}
+
+void HostDebugService(size_t MsgLevel, const char *SilPrefix, const char *Message,
+				 const char *Function, size_t Line, ...)
+{
+	if (!CONFIG(OPENSIL_DEBUG_OUTPUT))
+		return;
+
+	const int loglevel = translate_opensil_debug_level(MsgLevel);
+
+	/* print fomatted prefix */
+	if (CONFIG(OPENSIL_DEBUG_PREFIX))
+		printk(loglevel, "%s%s:%zu:", SilPrefix, Function, Line);
+
+	/* print formatted message */
+	va_list args;
+	va_start(args, Line);
+	vprintk(loglevel, Message, args);
+	va_end(args);
+}
diff --git a/src/vendorcode/amd/opensil/phoenix_poc/opensil_console.h b/src/vendorcode/amd/opensil/phoenix_poc/opensil_console.h
new file mode 100644
index 0000000000..d3ffb6857f
--- /dev/null
+++ b/src/vendorcode/amd/opensil/phoenix_poc/opensil_console.h
@@ -0,0 +1,9 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef _VENDORCODE_AND_OPENSIL_CONSOLE
+#define _VENDORCODE_AND_OPENSIL_CONSOLE
+
+void HostDebugService(size_t MsgLevel, const char *SilPrefix, const char *Message,
+		      const char *Function, size_t Line, ...);
+
+#endif
diff --git a/src/vendorcode/amd/opensil/phoenix_poc/ramstage.c b/src/vendorcode/amd/opensil/phoenix_poc/ramstage.c
new file mode 100644
index 0000000000..5a037fecb5
--- /dev/null
+++ b/src/vendorcode/amd/opensil/phoenix_poc/ramstage.c
@@ -0,0 +1,180 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <FCH/Common/FchCommonCfg.h>
+#include <FCH/Common/FchCore/FchSata/FchSata.h>
+#include <RcMgr/DfX/RcManager4-api.h>
+#include <amdblocks/reset.h>
+#include <bootstate.h>
+#include <cbmem.h>
+#include <cpu/cpu.h>
+#include <device/device.h>
+#include <soc/soc_chip.h>
+#include <static.h>
+#include <stdio.h>
+#include <xSIM-api.h>
+
+#include "opensil_console.h"
+#include "../opensil.h"
+
+void SIL_STATUS_report(const char *function, const int status)
+{
+	const int log_level = status == SilPass ? BIOS_DEBUG : BIOS_ERR;
+	const char *error_string = "Unknown error";
+
+	const struct error_string_entry {
+		SIL_STATUS status;
+		const char *string;
+	} errors[] = {
+		{SilPass, "SilPass"},
+		{SilUnsupportedHardware, "SilUnsupportedHardware"},
+		{SilUnsupported, "SilUnsupported"},
+		{SilInvalidParameter, "SilInvalidParameter"},
+		{SilAborted, "SilAborted"},
+		{SilOutOfResources, "SilOutOfResources"},
+		{SilNotFound, "SilNotFound"},
+		{SilOutOfBounds, "SilOutOfBounds"},
+		{SilDeviceError, "SilDeviceError"},
+		{SilResetRequestColdImm, "SilResetRequestColdImm"},
+		{SilResetRequestColdDef, "SilResetRequestColdDef"},
+		{SilResetRequestWarmImm, "SilResetRequestWarmImm"},
+		{SilResetRequestWarmDef, "SilResetRequestWarmDef"},
+	};
+
+	int i;
+	for (i = 0; i < ARRAY_SIZE(errors); i++) {
+		if (errors[i].status == status)
+			error_string = errors[i].string;
+	}
+	printk(log_level, "%s returned %d (%s)\n", function, status, error_string);
+}
+
+static void setup_rc_manager_default(void)
+{
+	DFX_RCMGR_INPUT_BLK *rc_mgr_input_block = SilFindStructure(SilId_RcManager,  0);
+	/* Let openSIL distribute the resources to the different PCI roots */
+	rc_mgr_input_block->SetRcBasedOnNv = false;
+
+	/* Currently 1P is the only supported configuration */
+	rc_mgr_input_block->SocketNumber = 1;
+	rc_mgr_input_block->RbsPerSocket = 4; /* PCI root bridges per socket */
+	rc_mgr_input_block->McptEnable = true;
+	rc_mgr_input_block->PciExpressBaseAddress = CONFIG_ECAM_MMCONF_BASE_ADDRESS;
+	rc_mgr_input_block->BottomMmioReservedForPrimaryRb = 4ull * GiB - 32 * MiB;
+	rc_mgr_input_block->MmioSizePerRbForNonPciDevice = 16 * MiB;
+	/* MmioAbove4GLimit will be adjusted down in openSIL */
+	rc_mgr_input_block->MmioAbove4GLimit = POWER_OF_2(cpu_phys_address_size());
+	rc_mgr_input_block->Above4GMmioSizePerRbForNonPciDevice = 0;
+}
+
+#define NUM_XHCI_CONTROLLERS 2
+static void configure_usb(void)
+{
+	const struct soc_amd_phoenix_poc_config *soc_config = config_of_soc();
+	const struct soc_usb_config *usb = &soc_config->usb;
+
+	FCHUSB_INPUT_BLK *fch_usb_data = SilFindStructure(SilId_FchUsb, 0);
+	fch_usb_data->Xhci0Enable = usb->xhci0_enable;
+	fch_usb_data->Xhci1Enable = usb->xhci1_enable;
+	fch_usb_data->Xhci2Enable = false; /* there's no XHCI2 on this SoC */
+	for (int i = 0; i < NUM_XHCI_CONTROLLERS; i++) {
+		memcpy(&fch_usb_data->XhciOCpinSelect[i].Usb20OcPin, &usb->usb2_oc_pins[i],
+		       sizeof(fch_usb_data->XhciOCpinSelect[i].Usb20OcPin));
+		memcpy(&fch_usb_data->XhciOCpinSelect[i].Usb31OcPin, &usb->usb3_oc_pins[i],
+		       sizeof(fch_usb_data->XhciOCpinSelect[i].Usb31OcPin));
+	}
+	fch_usb_data->XhciOcPolarityCfgLow = usb->polarity_cfg_low;
+	fch_usb_data->Usb3PortForceGen1 = usb->usb3_force_gen1.raw;
+
+	/* Instead of overwriting the whole OemUsbConfigurationTable, only copy the relevant
+	   fields to the pre-populated data structure */
+	fch_usb_data->OemUsbConfigurationTable.Usb31PhyEnable = usb->usb31_phy_enable;
+	if (usb->usb31_phy_enable)
+		memcpy(&fch_usb_data->OemUsbConfigurationTable.Usb31PhyPort, usb->usb31_phy,
+		       sizeof(fch_usb_data->OemUsbConfigurationTable.Usb31PhyPort));
+	fch_usb_data->OemUsbConfigurationTable.Usb31PhyEnable = usb->s1_usb31_phy_enable;
+	if (usb->s1_usb31_phy_enable)
+		memcpy(&fch_usb_data->OemUsbConfigurationTable.S1Usb31PhyPort, usb->s1_usb31_phy,
+		       sizeof(fch_usb_data->OemUsbConfigurationTable.S1Usb31PhyPort));
+}
+
+#define NUM_SATA_CONTROLLERS 4
+static void configure_sata(void)
+{
+	FCHSATA_INPUT_BLK *fch_sata_data = SilFindStructure(SilId_FchSata, 0);
+	FCH_SATA2 *fch_sata_defaults = GetFchSataData();
+	for (int i = 0; i < NUM_SATA_CONTROLLERS; i++) {
+		fch_sata_data[i] = fch_sata_defaults[i];
+		fch_sata_data[i].SataSetMaxGen2 = false;
+		fch_sata_data[i].SataMsiEnable = true;
+		fch_sata_data[i].SataEspPort = 0xFF;
+		fch_sata_data[i].SataRasSupport = true;
+		fch_sata_data[i].SataDevSlpPort1Num = 1;
+		fch_sata_data[i].SataMsiEnable = true;
+		fch_sata_data[i].SataControllerAutoShutdown = true;
+		fch_sata_data[i].SataRxPolarity = 0xFF;
+	}
+}
+
+void setup_opensil(void)
+{
+	const SIL_STATUS debug_ret = SilDebugSetup(HostDebugService);
+	SIL_STATUS_report("SilDebugSetup", debug_ret);
+	const size_t mem_req = xSimQueryMemoryRequirements();
+	void *buf = cbmem_add(CBMEM_ID_AMD_OPENSIL, mem_req);
+	assert(buf);
+	/* We run all openSIL timepoints in the same stage so using TP1 as argument is fine. */
+	const SIL_STATUS assign_mem_ret = xSimAssignMemoryTp1(buf, mem_req);
+	SIL_STATUS_report("xSimAssignMemory", assign_mem_ret);
+
+	setup_rc_manager_default();
+	configure_usb();
+	configure_sata();
+}
+
+static void opensil_entry(SIL_TIMEPOINT timepoint)
+{
+	SIL_STATUS ret;
+	SIL_TIMEPOINT tp = (uintptr_t)timepoint;
+
+	switch (tp) {
+	case SIL_TP1:
+		ret = InitializeSiTp1();
+		break;
+	case SIL_TP2:
+		ret = InitializeSiTp2();
+		break;
+	case SIL_TP3:
+		ret = InitializeSiTp3();
+		break;
+	default:
+		printk(BIOS_ERR, "Unknown openSIL timepoint\n");
+		return;
+	}
+	char opensil_function[16];
+	snprintf(opensil_function, sizeof(opensil_function), "InitializeSiTp%d", tp + 1);
+	SIL_STATUS_report(opensil_function, ret);
+	if (ret == SilResetRequestColdImm || ret == SilResetRequestColdDef) {
+		printk(BIOS_INFO, "openSIL requested a cold reset");
+		do_cold_reset();
+	} else if (ret == SilResetRequestWarmImm || ret == SilResetRequestWarmDef) {
+		printk(BIOS_INFO, "openSIL requested a warm reset");
+		do_warm_reset();
+	}
+}
+
+void opensil_xSIM_timepoint_1(void)
+{
+	opensil_entry(SIL_TP1);
+}
+
+void opensil_xSIM_timepoint_2(void)
+{
+	opensil_entry(SIL_TP2);
+}
+
+void opensil_xSIM_timepoint_3(void)
+{
+	opensil_entry(SIL_TP3);
+}
+
+/* TODO: also call timepoints 2 and 3 from coreboot. Are they NOOP? */
diff --git a/src/vendorcode/amd/opensil/phoenix_poc/romstage.c b/src/vendorcode/amd/opensil/phoenix_poc/romstage.c
new file mode 100644
index 0000000000..5b871f6025
--- /dev/null
+++ b/src/vendorcode/amd/opensil/phoenix_poc/romstage.c
@@ -0,0 +1,17 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <console/console.h>
+#include "opensil_console.h"
+#include <xSIM-api.h>
+#include <xPRF-api.h>
+
+#include "../opensil.h"
+
+uintptr_t opensil_get_low_usable_dram_address(void)
+{
+	SilDebugSetup(HostDebugService);
+	uintptr_t low_usable_dram_addr = xPrfGetLowUsableDramAddress(0);
+	printk(BIOS_DEBUG, "xPrfGetLowUsableDramAddress: 0x%lx\n", low_usable_dram_addr);
+
+	return low_usable_dram_addr;
+}

From 513899c3c8881d8ae7463a7ac667c564acf7997d Mon Sep 17 00:00:00 2001
From: Alicja Michalska <alicja.michalska@9elements.com>
Date: Sun, 1 Mar 2026 02:48:49 +0100
Subject: [PATCH 3688/3886] vc/amd/opensil/phoenix_poc: Adjust headers from
 Genoa to Phoenix

As directory was copied from genoa_poc, we need to adjust headers to
correspond to phoenix_poc repository.

Change-Id: Id3aeaf6ecf138ea94282ae2a308a45c77ff73b02
Signed-off-by: Alicja Michalska <alicja.michalska@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91481
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/vendorcode/amd/opensil/phoenix_poc/acpi.c              | 2 +-
 src/vendorcode/amd/opensil/phoenix_poc/memmap.c            | 3 +--
 src/vendorcode/amd/opensil/phoenix_poc/mpio/chip.c         | 4 ++--
 .../amd/opensil/phoenix_poc/opensil_config.template        | 2 --
 src/vendorcode/amd/opensil/phoenix_poc/ramstage.c          | 7 +++----
 5 files changed, 7 insertions(+), 11 deletions(-)

diff --git a/src/vendorcode/amd/opensil/phoenix_poc/acpi.c b/src/vendorcode/amd/opensil/phoenix_poc/acpi.c
index fcdf167c12..75249b064d 100644
--- a/src/vendorcode/amd/opensil/phoenix_poc/acpi.c
+++ b/src/vendorcode/amd/opensil/phoenix_poc/acpi.c
@@ -4,7 +4,7 @@
 #include <Sil-api.h>
 #include <SilCommon.h>
 #include <xSIM-api.h>
-#include <FCH/Common/FchCommonCfg.h>
+#include <FCH/Common/FchCommon.h>
 
 #include "../opensil.h"
 
diff --git a/src/vendorcode/amd/opensil/phoenix_poc/memmap.c b/src/vendorcode/amd/opensil/phoenix_poc/memmap.c
index eed1be7e5f..a9e8d1d2b7 100644
--- a/src/vendorcode/amd/opensil/phoenix_poc/memmap.c
+++ b/src/vendorcode/amd/opensil/phoenix_poc/memmap.c
@@ -2,7 +2,7 @@
 
 #include <SilCommon.h>
 #include <Sil-api.h> // needed above ApobCmn.h
-#include <ApobCmn.h>
+#include <APOB/Common/ApobCmn.h>
 #include <xPRF-api.h>
 
 #include "../opensil.h"
@@ -32,7 +32,6 @@ const char *opensil_get_hole_info_type(uint32_t type)
 		{ReservedCxl, "ReservedCxl"},
 		{ReservedCxlAlignment, "ReservedCxlAlignment"},
 		{ReservedCpuTmr, "ReservedCpuTmr"},
-		{ReservedRasEinj, "ReservedRasEinj"},
 		{MaxMemoryHoleTypes, "MaxMemoryHoleTypes"},
 	};
 
diff --git a/src/vendorcode/amd/opensil/phoenix_poc/mpio/chip.c b/src/vendorcode/amd/opensil/phoenix_poc/mpio/chip.c
index 587ab81e02..cdfe29fddd 100644
--- a/src/vendorcode/amd/opensil/phoenix_poc/mpio/chip.c
+++ b/src/vendorcode/amd/opensil/phoenix_poc/mpio/chip.c
@@ -4,8 +4,8 @@
 #include <device/pci_def.h>
 #include <Mpio/Common/MpioStructs.h>
 #include <Mpio/MpioClass-api.h>
-#include <NBIO/NbioClass-api.h>
-#include <RcMgr/DfX/RcManager4-api.h>
+#include <Nbio/NbioClass-api.h>
+#include <RcMgr/DfX/RcManager-api.h>
 #include <vendorcode/amd/opensil/opensil.h>
 #include <xSIM-api.h>
 
diff --git a/src/vendorcode/amd/opensil/phoenix_poc/opensil_config.template b/src/vendorcode/amd/opensil/phoenix_poc/opensil_config.template
index 2ddd3b4ec1..a93eaeed6a 100644
--- a/src/vendorcode/amd/opensil/phoenix_poc/opensil_config.template
+++ b/src/vendorcode/amd/opensil/phoenix_poc/opensil_config.template
@@ -1,5 +1,3 @@
 CONFIG_PLAT_APOB_ADDRESS=##APOB_BASE##
 CONFIG_PSP_BIOS_BIN_BASE=##BIOS_ENTRY_BASE##
 CONFIG_PSP_BIOS_BIN_SIZE=##BIOS_ENTRY_SIZE##
-CONFIG_PLAT_NUMBER_SOCKETS=1
-CONFIG_SOC_F19M10=y
diff --git a/src/vendorcode/amd/opensil/phoenix_poc/ramstage.c b/src/vendorcode/amd/opensil/phoenix_poc/ramstage.c
index 5a037fecb5..243236a9ab 100644
--- a/src/vendorcode/amd/opensil/phoenix_poc/ramstage.c
+++ b/src/vendorcode/amd/opensil/phoenix_poc/ramstage.c
@@ -1,14 +1,13 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
-#include <FCH/Common/FchCommonCfg.h>
-#include <FCH/Common/FchCore/FchSata/FchSata.h>
-#include <RcMgr/DfX/RcManager4-api.h>
+#include <FCH/Common/FchCommon.h>
+#include <RcMgr/DfX/RcManager-api.h>
 #include <amdblocks/reset.h>
 #include <bootstate.h>
 #include <cbmem.h>
 #include <cpu/cpu.h>
 #include <device/device.h>
-#include <soc/soc_chip.h>
+#include <soc/amd/phoenix/chip.h>
 #include <static.h>
 #include <stdio.h>
 #include <xSIM-api.h>

From deb510afeb8e433bdb6290e00c5a2ec5db2b4f77 Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Sun, 1 Feb 2026 21:11:34 +0000
Subject: [PATCH 3689/3886] cpu/x86/smm: add OPAL S3 CBMEM scratch

Provide an optional, coreboot-managed CBMEM scratch buffer for SMM code.

CBMEM is reserved from the OS via the memory map and persists across S3,
so it is suitable for firmware-owned DMA buffers used during resume.
SMRAM is not device DMA-accessible, so this scratch buffer must live
outside SMRAM.

Pass the base/size to SMM via smm_runtime so SMM code can validate
placement and avoid relying on untrusted pointers.

The CBMEM region size is configurable via SMM_OPAL_S3_SCRATCH_SIZE,
defaulting to 16 KiB as a safe value.

TEST=tested with rest of patch train

Change-Id: I79ae5327f27e574b151b7cf456761fa0d7038f2f
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91042
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
---
 .../bsd/include/commonlib/bsd/cbmem_id.h      |  2 ++
 src/cpu/x86/Kconfig                           | 18 +++++++++++++++++
 src/cpu/x86/smm/smm_module_handler.c          |  8 ++++++++
 src/cpu/x86/smm/smm_module_loader.c           | 20 +++++++++++++++++++
 src/include/cpu/x86/smm.h                     |  7 +++++++
 5 files changed, 55 insertions(+)

diff --git a/src/commonlib/bsd/include/commonlib/bsd/cbmem_id.h b/src/commonlib/bsd/include/commonlib/bsd/cbmem_id.h
index 0431626f2c..df0e0d0b67 100644
--- a/src/commonlib/bsd/include/commonlib/bsd/cbmem_id.h
+++ b/src/commonlib/bsd/include/commonlib/bsd/cbmem_id.h
@@ -7,6 +7,7 @@
 #define CBMEM_ID_ACPI_BERT	0x42455254
 #define CBMEM_ID_ACPI_CNVS	0x434e5653
 #define CBMEM_ID_ACPI_GNVS	0x474e5653
+#define CBMEM_ID_OPAL_S3_SCRATCH 0x3353504f /* 'OPS3' */
 #define CBMEM_ID_ACPI_HEST	0x48455354
 #define CBMEM_ID_ACPI_UCSI	0x55435349
 #define CBMEM_ID_AFTER_CAR	0xc4787a93
@@ -100,6 +101,7 @@
 	{ CBMEM_ID_ACPI_BERT,		"ACPI BERT  " }, \
 	{ CBMEM_ID_ACPI_CNVS,		"CHROMEOS NVS" }, \
 	{ CBMEM_ID_ACPI_GNVS,		"ACPI GNVS  " }, \
+	{ CBMEM_ID_OPAL_S3_SCRATCH,	"OPAL S3 SCR" }, \
 	{ CBMEM_ID_ACPI_HEST,		"ACPI HEST  " }, \
 	{ CBMEM_ID_ACPI_UCSI,		"ACPI UCSI  " }, \
 	{ CBMEM_ID_AGESA_RUNTIME,	"AGESA RSVD " }, \
diff --git a/src/cpu/x86/Kconfig b/src/cpu/x86/Kconfig
index 7a701bb9d6..c049d4b124 100644
--- a/src/cpu/x86/Kconfig
+++ b/src/cpu/x86/Kconfig
@@ -196,6 +196,24 @@ config SMM_MODULE_STACK_SIZE
 	  This option determines the size of the stack within the SMM handler
 	  modules.
 
+config SMM_OPAL_S3_SCRATCH_CBMEM
+	bool
+	depends on HAVE_ACPI_RESUME
+	default n
+	help
+	  Allocate a coreboot-managed CBMEM region that can be used as a
+	  persistent (across S3) scratch buffer by SMM code performing OPAL/NVMe
+	  unlock on resume. The region is in CBMEM and therefore reserved from
+	  the OS via the memory map.
+
+config SMM_OPAL_S3_SCRATCH_SIZE
+	hex "OPAL S3 scratch size (bytes)"
+	depends on SMM_OPAL_S3_SCRATCH_CBMEM
+	default 0x4000
+	help
+	  Size of the CBMEM scratch buffer provided to the OPAL S3 unlock SMM
+	  handler. This buffer must be DMA-safe and persistent across S3.
+
 endif
 
 config SMM_LAPIC_REMAP_MITIGATION
diff --git a/src/cpu/x86/smm/smm_module_handler.c b/src/cpu/x86/smm/smm_module_handler.c
index 8bcda32b33..3f14d970d8 100644
--- a/src/cpu/x86/smm/smm_module_handler.c
+++ b/src/cpu/x86/smm/smm_module_handler.c
@@ -66,6 +66,14 @@ void smm_get_smmstore_com_buffer(uintptr_t *base, size_t *size)
 	*size = smm_runtime.smmstore_com_buffer_size;
 }
 
+#if CONFIG(SMM_OPAL_S3_SCRATCH_CBMEM)
+void smm_get_opal_s3_scratch_buffer(uintptr_t *base, size_t *size)
+{
+	*base = smm_runtime.opal_s3_scratch_base;
+	*size = smm_runtime.opal_s3_scratch_size;
+}
+#endif
+
 void smm_get_cbmemc_buffer(void **buffer_out, size_t *size_out)
 {
 	*buffer_out = smm_runtime.cbmemc;
diff --git a/src/cpu/x86/smm/smm_module_loader.c b/src/cpu/x86/smm/smm_module_loader.c
index dff2dde857..4946fe5a0f 100644
--- a/src/cpu/x86/smm/smm_module_loader.c
+++ b/src/cpu/x86/smm/smm_module_loader.c
@@ -366,6 +366,26 @@ static void setup_smihandler_params(struct smm_runtime *mod_params,
 		mod_params->smmstore_com_buffer_base = (uintptr_t)ptr;
 		mod_params->smmstore_com_buffer_size = info.block_size;
 	}
+
+#if CONFIG(SMM_OPAL_S3_SCRATCH_CBMEM)
+	/*
+	 * Provide a small, coreboot-managed CBMEM scratch region for SMM code.
+	 * CBMEM is reserved in the memory map, and persists across S3, making
+	 * it suitable for firmware-owned DMA buffers on resume. SMRAM is not
+	 * accessible to devices for DMA, so this scratch buffer must live
+	 * outside SMRAM.
+	 */
+	const size_t opal_s3_scratch_size = CONFIG_SMM_OPAL_S3_SCRATCH_SIZE;
+	void *scratch = cbmem_add(CBMEM_ID_OPAL_S3_SCRATCH, opal_s3_scratch_size);
+	if (!scratch) {
+		printk(BIOS_ERR, "SMM: Failed to allocate OPAL S3 scratch\n");
+		mod_params->opal_s3_scratch_base = 0;
+		mod_params->opal_s3_scratch_size = 0;
+	} else {
+		mod_params->opal_s3_scratch_base = (uintptr_t)scratch;
+		mod_params->opal_s3_scratch_size = opal_s3_scratch_size;
+	}
+#endif
 }
 
 static void print_region(const char *name, const struct region region)
diff --git a/src/include/cpu/x86/smm.h b/src/include/cpu/x86/smm.h
index 8c41623817..913bd37205 100644
--- a/src/include/cpu/x86/smm.h
+++ b/src/include/cpu/x86/smm.h
@@ -96,6 +96,10 @@ struct smm_runtime {
 	int smm_log_level;
 	uintptr_t smmstore_com_buffer_base;
 	size_t smmstore_com_buffer_size;
+#if CONFIG(SMM_OPAL_S3_SCRATCH_CBMEM)
+	uintptr_t opal_s3_scratch_base;
+	size_t opal_s3_scratch_size;
+#endif
 } __packed;
 
 struct smm_module_params {
@@ -238,5 +242,8 @@ bool smm_pci_resource_store_fill_resources(struct smm_pci_resource_info *slots,
 void smm_pci_resource_store_init(struct smm_runtime *smm_runtime);
 
 void smm_get_smmstore_com_buffer(uintptr_t *base, size_t *size);
+#if CONFIG(SMM_OPAL_S3_SCRATCH_CBMEM)
+void smm_get_opal_s3_scratch_buffer(uintptr_t *base, size_t *size);
+#endif
 
 #endif /* CPU_X86_SMM_H */

From e6fb0faf7b9cac1a960f475fce8c8abb0135fb92 Mon Sep 17 00:00:00 2001
From: Subrata Banik <subratabanik@google.com>
Date: Wed, 18 Feb 2026 12:37:31 +0530
Subject: [PATCH 3690/3886] soc/qualcomm/x1p42100: Skip redundant MMU toggling
 for QCLib

Enable SOC_QUALCOMM_QCLIB_SKIP_MMU_TOGGLE for the x1p42100 SoC to
optimize boot performance.

BUG=b:449871690, b:477139887
TEST=TBD.

Change-Id: Ide19857e37fe04e97733aa91a5c1fc4e02911ea4
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91331
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
---
 src/soc/qualcomm/x1p42100/Kconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/src/soc/qualcomm/x1p42100/Kconfig b/src/soc/qualcomm/x1p42100/Kconfig
index 7107720391..b2244358aa 100644
--- a/src/soc/qualcomm/x1p42100/Kconfig
+++ b/src/soc/qualcomm/x1p42100/Kconfig
@@ -29,6 +29,7 @@ config SOC_QUALCOMM_BASE
 	select NO_ECAM_MMCONF_SUPPORT
 	select SDHCI_CONTROLLER
 	select SOC_QUALCOMM_COMMON
+	select SOC_QUALCOMM_QCLIB_SKIP_MMU_TOGGLE
 
 config SOC_QUALCOMM_X1P42100
 	bool

From 19e1b5c44bdab04fe5bc14f6d67ae50f13576d27 Mon Sep 17 00:00:00 2001
From: Guangjie Song <guangjie.song@mediatek.corp-partner.google.com>
Date: Wed, 11 Mar 2026 17:07:06 +0800
Subject: [PATCH 3691/3886] soc/mediatek/mt8196: Change dsi-phy1 & dsi-phy2
 control method

dsi-phy1 and dsi-phy2 are currently controlled using hardware voting,
however there is a low probability of power-off failure during the boot
process. Since dsi-phy1 and dsi-phy2 are not shared with different XPUs,
there is no need to control them using hardware voting. Change the
control method of dsi-phy1 and dsi-phy2 from hardware voting to software
control to fix the power-off failure issue.

BUG=b:477096462
TEST=Build Pass, Bootup OK and Suspend/Resume OK

Change-Id: I33ebbac0dd6d0d0d352697c14de9ecef28ba08cb
Signed-off-by: Guangjie Song <guangjie.song@mediatek.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91659
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
---
 src/soc/mediatek/mt8196/mtcmos.c | 29 +++++++++++++++++++----------
 1 file changed, 19 insertions(+), 10 deletions(-)

diff --git a/src/soc/mediatek/mt8196/mtcmos.c b/src/soc/mediatek/mt8196/mtcmos.c
index e274be8639..be31a56e68 100644
--- a/src/soc/mediatek/mt8196/mtcmos.c
+++ b/src/soc/mediatek/mt8196/mtcmos.c
@@ -30,9 +30,12 @@
 #define SPM_PBUS_BUS_MSB_PROTECT_EN_CLR		((void *)(SPM_PBUS_BASE + 0x00EC))
 #define SPM_PBUS_BUS_MSB_PROTECT_RDY_STA	((void *)(SPM_PBUS_BASE + 0x020C))
 
+#define MMPC_MTCMOS_SEL_GP0		((void *)(MMPC_BASE + 0x00BC))
 #define MM_BUCK_ISO_CON_CLR		((void *)(MMPC_BASE + 0x00C8))
 #define DISP_AO_PWR_CON			((void *)(MMPC_BASE + 0x00E8))
 #define MMPC_BUS_PROTECT_EN_1_CLR	((void *)(MMPC_BASE + 0x0188))
+#define MMPC_DSI1_PWR_CON		((void *)(MMPC_BASE + 0x00F4))
+#define MMPC_DSI2_PWR_CON		((void *)(MMPC_BASE + 0x00F8))
 
 #define MMVOTE_MTCMOS_0_SET		((void *)(MMVOTE_BASE + 0x0218))
 #define MMVOTE_MTCMOS_0_CLR		((void *)(MMVOTE_BASE + 0x021C))
@@ -291,6 +294,12 @@ static struct mtcmos_data mds[MTCMOS_ID_NUM] = {
 	[MTCMOS_ID_SSRSYS] = {
 		ssrsys_bp, &mtk_spm_mtcmos->ssrsys_pwr_con, 0, 1
 	},
+	[MTCMOS_ID_DSI_PHY1] = {
+		NULL, MMPC_DSI1_PWR_CON, MTK_SCPD_NO_SRAM, 0
+	},
+	[MTCMOS_ID_DSI_PHY2] = {
+		NULL, MMPC_DSI2_PWR_CON, MTK_SCPD_NO_SRAM, 0
+	},
 };
 
 static struct mtcmos_vote_data vote_mds[MTCMOS_ID_NUM] = {
@@ -338,16 +347,14 @@ static struct mtcmos_vote_data vote_mds[MTCMOS_ID_NUM] = {
 		MMVOTE_MTCMOS_1_SET, MMVOTE_MTCMOS_1_CLR, MMVOTE_MTCMOS_1_DONE,
 		MMVOTE_MTCMOS_1_PM_ACK, DSI_PHY0_VOTE_BIT
 	},
-	[MTCMOS_ID_DSI_PHY1] = {
-		MMVOTE_MTCMOS_1_SET, MMVOTE_MTCMOS_1_CLR, MMVOTE_MTCMOS_1_DONE,
-		MMVOTE_MTCMOS_1_PM_ACK, DSI_PHY1_VOTE_BIT
-	},
-	[MTCMOS_ID_DSI_PHY2] = {
-		MMVOTE_MTCMOS_1_SET, MMVOTE_MTCMOS_1_CLR, MMVOTE_MTCMOS_1_DONE,
-		MMVOTE_MTCMOS_1_PM_ACK, DSI_PHY2_VOTE_BIT
-	},
 };
 
+static inline bool use_voting(enum mtcmos_id id)
+{
+	return id > MTCMOS_ID_SSRSYS &&
+	       id != MTCMOS_ID_DSI_PHY1 && id != MTCMOS_ID_DSI_PHY2;
+}
+
 int mtcmos_cb_register(enum mtcmos_id id, const struct mtcmos_cb *cb)
 {
 	if (id >= MTCMOS_ID_NUM) {
@@ -355,7 +362,7 @@ int mtcmos_cb_register(enum mtcmos_id id, const struct mtcmos_cb *cb)
 		return -1;
 	}
 
-	if (id <= MTCMOS_ID_SSRSYS)
+	if (!use_voting(id))
 		mds[id].cb = cb;
 	else
 		vote_mds[id].cb = cb;
@@ -692,7 +699,7 @@ void mtcmos_ctrl(enum mtcmos_id id, enum mtcmos_state state)
 		return;
 	}
 
-	if (id <= MTCMOS_ID_SSRSYS)
+	if (!use_voting(id))
 		ret = mtcmos_onoff(id, state);
 	else
 		ret = mtcmos_vote_onoff(id, state);
@@ -734,6 +741,8 @@ void mtcmos_init(void)
 
 void mtcmos_post_init(void)
 {
+	write32(MMPC_MTCMOS_SEL_GP0, 0xFFFFE7FF);
+
 	if (mtcmos_cb_register(MTCMOS_ID_DISP_VCORE, &disp_vcore_cb))
 		printk(BIOS_ERR, "register disp_vcore failed\n");
 

From e9e4f7609cfda6d295775a441e026626c71669fa Mon Sep 17 00:00:00 2001
From: Hari L <haril@qualcomm.corp-partner.google.com>
Date: Tue, 10 Mar 2026 17:30:11 +0530
Subject: [PATCH 3692/3886] mb/google/bluey: Move QUP-GSI init/load to normal
 boot path

The ADSP GSI initialization/loading is needed in both
normal boot and the off-mode/low-battery charging path. This patch
moves it before the conditional mainboard initialization skip, so it
runs in all cases.

TEST=Able to build and boot google/bluey.

Change-Id: I6237154f8701d5f7f9e1e0b20378cb8e8be39fca
Signed-off-by: Hari L <haril@qualcomm.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91637
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
---
 src/mainboard/google/bluey/mainboard.c | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/src/mainboard/google/bluey/mainboard.c b/src/mainboard/google/bluey/mainboard.c
index f4f076ef2e..93a3681d5d 100644
--- a/src/mainboard/google/bluey/mainboard.c
+++ b/src/mainboard/google/bluey/mainboard.c
@@ -218,6 +218,10 @@ static void mainboard_init(struct device *dev)
 	/* ADSP I2C (Charger/Fuel gauge) */
 	qupv3_se_fw_load_and_init(QUPV3_2_SE4, SE_PROTOCOL_I2C, MIXED);
 
+	gpi_firmware_load(QUP_0_GSI_BASE);
+	gpi_firmware_load(QUP_1_GSI_BASE);
+	gpi_firmware_load(QUP_2_GSI_BASE);
+
 	configure_parallel_charging_late();
 
 	/* Skip mainboard initialization if boot mode is "low-battery" or "off-mode charging" */
@@ -226,10 +230,6 @@ static void mainboard_init(struct device *dev)
 		halt();
 	}
 
-	gpi_firmware_load(QUP_0_GSI_BASE);
-	gpi_firmware_load(QUP_1_GSI_BASE);
-	gpi_firmware_load(QUP_2_GSI_BASE);
-
 	/*
 	 * Load console UART QUP firmware.
 	 * This is required even if coreboot's serial output is disabled.

From dc7bf7e3f9913ada738af40ac9695700622e85e7 Mon Sep 17 00:00:00 2001
From: Kapil Porwal <kapilporwal@google.com>
Date: Fri, 13 Mar 2026 23:31:20 +0530
Subject: [PATCH 3693/3886] mb/google/bluey: Enable source mode on debug access
 port

The current implementation only supports sink mode on the debug access
port, which is used for charging. To enhance debugging capabilities,
expand the support to include source mode.

Refactor the Kconfig option to HAVE_DEBUG_ACCESS_PORT_SOURCE_SINK and
update the initialization logic to configure both SRC and SNK modes
via the PMIC's SCHG_TYPE_C_DEBUG_ACCESS registers. This allows the
debug port to serve as a power source or sink as required by the
attached debug hardware.

BUG=none
TEST=Verify debug port modes on Google/Quartz.

Change-Id: I3ec45d9cdc0ec6e723d10792f4e347462cecd2ed
Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91670
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jayvik Desai <jayvik@google.com>
---
 src/mainboard/google/bluey/Kconfig     |  6 +++---
 src/mainboard/google/bluey/board.h     |  2 +-
 src/mainboard/google/bluey/charging.c  | 13 +++++++++----
 src/mainboard/google/bluey/mainboard.c |  2 +-
 4 files changed, 14 insertions(+), 9 deletions(-)

diff --git a/src/mainboard/google/bluey/Kconfig b/src/mainboard/google/bluey/Kconfig
index 727e1e8f7a..ddb033d939 100644
--- a/src/mainboard/google/bluey/Kconfig
+++ b/src/mainboard/google/bluey/Kconfig
@@ -58,7 +58,7 @@ config BOARD_GOOGLE_QUENBIH
 
 config BOARD_GOOGLE_QUARTZ
 	select BOARD_GOOGLE_MODEL_QUARTZ
-	select HAVE_CHARGING_DEBUG_ACCESS_PORT
+	select HAVE_DEBUG_ACCESS_PORT_SOURCE_SINK
 	select SOC_QUALCOMM_HAMOA
 	select MAINBOARD_HAS_PS8820_RETIMER
 	select MAINBOARD_NO_USB_A_PORT
@@ -131,11 +131,11 @@ config MAINBOARD_SUPPORTS_PARALLEL_CHARGING
 	help
 	  Enable this option if your mainboard supports parallel charging.
 
-config HAVE_CHARGING_DEBUG_ACCESS_PORT
+config HAVE_DEBUG_ACCESS_PORT_SOURCE_SINK
 	bool
 	default n
 	help
-	  Enable this option to allow charging on the debug access port.
+	  Enable this option to allow source and sink modes on the debug access port.
 
 config MAINBOARD_HAS_GOOGLE_TPM
 	bool
diff --git a/src/mainboard/google/bluey/board.h b/src/mainboard/google/bluey/board.h
index 361aa6587c..04ef0ca3c1 100644
--- a/src/mainboard/google/bluey/board.h
+++ b/src/mainboard/google/bluey/board.h
@@ -61,7 +61,7 @@ void setup_chromeos_gpios(void);
 bool is_off_mode(void);
 void configure_parallel_charging(void);
 void configure_parallel_charging_late(void);
-void configure_charging_debug_access(void);
+void configure_debug_access_port(void);
 void enable_slow_battery_charging(void);
 void disable_slow_battery_charging(void);
 void launch_charger_applet(void);
diff --git a/src/mainboard/google/bluey/charging.c b/src/mainboard/google/bluey/charging.c
index c99bf020a1..2e0fcb2baf 100644
--- a/src/mainboard/google/bluey/charging.c
+++ b/src/mainboard/google/bluey/charging.c
@@ -21,6 +21,9 @@
 #define SMB2_CHGR_CHRG_EN_CMD ((SMB2_SLAVE_ID << 16) | SCHG_CHGR_CHARGING_ENABLE_CMD)
 #define SMB1_SCHG_TYPE_C_TYPE_C_DEBUG_ACCESS_SNK_CFG \
 ((SMB1_SLAVE_ID << 16) | SCHG_TYPE_C_TYPE_C_DEBUG_ACCESS_SNK_CFG)
+#define SCHG_TYPE_C_TYPE_C_DEBUG_ACCESS_SRC_CFG 0x2B4C
+#define SMB1_SCHG_TYPE_C_TYPE_C_DEBUG_ACCESS_SRC_CFG \
+((SMB1_SLAVE_ID << 16) | SCHG_TYPE_C_TYPE_C_DEBUG_ACCESS_SRC_CFG)
 #define SCHG_CHGR_CHARGING_FCC 0x260A
 #define SMB1_CHGR_CHARGING_FCC ((SMB1_SLAVE_ID << 16) | SCHG_CHGR_CHARGING_FCC)
 #define SMB2_CHGR_CHARGING_FCC ((SMB2_SLAVE_ID << 16) | SCHG_CHGR_CHARGING_FCC)
@@ -28,6 +31,7 @@
 #define FCC_1A_STEP_50MA 0x14
 #define FCC_DISABLE 0x8c
 #define EN_DEBUG_ACCESS_SNK 0x1B
+#define EN_DEBUG_ACCESS_SRC 0x01
 
 #define PMC8380F_SLAVE_ID	0x05
 #define GPIO07_MODE_CTL			0x8E40
@@ -205,14 +209,15 @@ void configure_parallel_charging(void)
 }
 
 /*
- * Enable SMB1 charging debug access port.
+ * Configure debug access port to support source and sink modes.
  */
-void configure_charging_debug_access(void)
+void configure_debug_access_port(void)
 {
-	if (!CONFIG(HAVE_CHARGING_DEBUG_ACCESS_PORT))
+	if (!CONFIG(HAVE_DEBUG_ACCESS_PORT_SOURCE_SINK))
 		return;
 
-	printk(BIOS_INFO, "Enable charging debug access port support\n");
+	printk(BIOS_INFO, "Enable support of source and sink modes for debug access port\n");
+	spmi_write8(SMB1_SCHG_TYPE_C_TYPE_C_DEBUG_ACCESS_SRC_CFG, EN_DEBUG_ACCESS_SRC);
 	spmi_write8(SMB1_SCHG_TYPE_C_TYPE_C_DEBUG_ACCESS_SNK_CFG, EN_DEBUG_ACCESS_SNK);
 }
 
diff --git a/src/mainboard/google/bluey/mainboard.c b/src/mainboard/google/bluey/mainboard.c
index 93a3681d5d..891967f3e3 100644
--- a/src/mainboard/google/bluey/mainboard.c
+++ b/src/mainboard/google/bluey/mainboard.c
@@ -204,7 +204,7 @@ static void handle_low_power_charging_boot(void)
 static void mainboard_init(struct device *dev)
 {
 	configure_parallel_charging();
-	configure_charging_debug_access();
+	configure_debug_access_port();
 
 	display_startup();
 

From e69bfef7c0eabda20c322eea7fadc347d0ed5076 Mon Sep 17 00:00:00 2001
From: Arthur Heymans <arthur@aheymans.xyz>
Date: Fri, 13 Mar 2026 13:41:54 +0100
Subject: [PATCH 3694/3886] mb/emu/qemu-sbsa: Set io_port_mmio_base for PCI I/O
 port support

The QEMU sbsa-ref machine maps PCI I/O port space at 0x7fff0000.
Set io_port_mmio_base so that PCI I/O port accesses are correctly
translated to MMIO on aarch64.

This is needed for PCI device drivers that may use I/O port BARs,
such as the QEMU bochs display driver which already compiles and
links for this target via the existing DRIVERS_EMULATION_QEMU_BOCHS
Kconfig.

Change-Id: I6a06c4c3a48c5d3409009f10b089a3537ccec8a6
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91667
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
---
 src/mainboard/emulation/qemu-sbsa/mmio.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/src/mainboard/emulation/qemu-sbsa/mmio.c b/src/mainboard/emulation/qemu-sbsa/mmio.c
index 6b50856b94..5ac2d7bcf6 100644
--- a/src/mainboard/emulation/qemu-sbsa/mmio.c
+++ b/src/mainboard/emulation/qemu-sbsa/mmio.c
@@ -3,6 +3,8 @@
 #include <console/uart.h>
 #include <mainboard/addressmap.h>
 
+uintptr_t io_port_mmio_base = SBSA_PCIE_PIO_BASE;
+
 uintptr_t uart_platform_base(unsigned int idx)
 {
 	return SBSA_UART_BASE;

From bf037f3961c352e96798eda7967cebf9c3bdd81f Mon Sep 17 00:00:00 2001
From: Arthur Heymans <arthur@aheymans.xyz>
Date: Fri, 13 Mar 2026 13:42:06 +0100
Subject: [PATCH 3695/3886] mb/emu/qemu-sbsa: Add GIC ITS and IORT for PCI MSI
 support

The QEMU sbsa-ref machine has a GICv3 ITS at 0x44081000 that handles
MSI/MSI-X translation for PCI devices. Without describing the ITS in
ACPI tables, Linux cannot set up MSI interrupts, causing warnings like:

  WARNING: CPU: 1 PID: 1 at drivers/pci/msi/msi.h:121 pci_msi_setup_msi_irqs+0x40/0x58
  xhci_hcd 0000:00:04.0: xHCI Host Controller

Add GIC ITS base address to the address map and implement
platform_get_gic_its() so the common MADT generation code emits
a GIC ITS entry.

Select ACPI_IORT and implement acpi_soc_fill_iort() to generate an
IORT table with an ITS Group node and a Root Complex node that maps
all PCI RIDs 1:1 to ITS device IDs.

Tested with Fedora 41 and a qemu-xhci USB controller.

Change-Id: I9366968aac855dae808f6f0c73f1d3ec644bbeff
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91668
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/emulation/qemu-sbsa/Kconfig     |  1 +
 src/mainboard/emulation/qemu-sbsa/acpi.c      | 40 +++++++++++++++++++
 .../qemu-sbsa/include/mainboard/addressmap.h  |  1 +
 3 files changed, 42 insertions(+)

diff --git a/src/mainboard/emulation/qemu-sbsa/Kconfig b/src/mainboard/emulation/qemu-sbsa/Kconfig
index a28ae62290..2bdac1406f 100644
--- a/src/mainboard/emulation/qemu-sbsa/Kconfig
+++ b/src/mainboard/emulation/qemu-sbsa/Kconfig
@@ -21,6 +21,7 @@ config BOARD_SPECIFIC_OPTIONS
 	select PCI
 	select HAVE_ACPI_TABLES
 	select ACPI_GTDT
+	select ACPI_IORT
 	select ACPI_COMMON_MADT_GICC_V3
 	select GENERATE_SMBIOS_TABLES
 
diff --git a/src/mainboard/emulation/qemu-sbsa/acpi.c b/src/mainboard/emulation/qemu-sbsa/acpi.c
index 1dae24277f..2f1d39a7be 100644
--- a/src/mainboard/emulation/qemu-sbsa/acpi.c
+++ b/src/mainboard/emulation/qemu-sbsa/acpi.c
@@ -1,6 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
 #include <acpi/acpi.h>
+#include <acpi/acpi_iort.h>
 #include <mainboard/addressmap.h>
 
 
@@ -24,6 +25,45 @@ uintptr_t platform_get_gicr_base(void)
 	return SBSA_GIC_REDIST;
 }
 
+static uintptr_t gic_its[] = {
+	SBSA_GIC_ITS,
+};
+
+int platform_get_gic_its(uintptr_t **base)
+{
+	*base = gic_its;
+	return ARRAY_SIZE(gic_its);
+}
+
+unsigned long acpi_soc_fill_iort(acpi_iort_t *iort, unsigned long current)
+{
+	acpi_iort_node_t *its, *rc;
+	u32 its_reference;
+	u32 identifiers[] = {0};	/* GIC ITS ID 0 */
+
+	/* ITS Group node */
+	current = acpi_iort_its_entry(current, iort, &its, 1, identifiers);
+	its_reference = (unsigned long)its - (unsigned long)iort;
+
+	/* Root Complex node for PCIe host bridge (segment 0) */
+	current = acpi_iort_rc_entry(current, iort, &rc,
+				     0,		/* memory_properties */
+				     0,		/* ats_attribute */
+				     0,		/* pci_segment_number */
+				     0x30,	/* memory_address_limit (48-bit) */
+				     0);	/* pasid_capabilities */
+
+	/* Map all PCI RIDs (0-0xFFFF) 1:1 to ITS device IDs */
+	current = acpi_iort_id_map_entry(current, rc,
+					 0,		/* input_base */
+					 0x10000,	/* id_count (65536 RIDs) */
+					 0,		/* output_base */
+					 its_reference,	/* output_reference */
+					 0);		/* flags */
+
+	return current;
+}
+
 #define SEC_EL1_TIMER_GISV 0x1d
 #define NONSEC_EL1_TIMER_GSIV 0x1e
 #define VIRTUAL_TIMER_GSIV 0x1b
diff --git a/src/mainboard/emulation/qemu-sbsa/include/mainboard/addressmap.h b/src/mainboard/emulation/qemu-sbsa/include/mainboard/addressmap.h
index 84c2d05bca..67d9e7e39f 100644
--- a/src/mainboard/emulation/qemu-sbsa/include/mainboard/addressmap.h
+++ b/src/mainboard/emulation/qemu-sbsa/include/mainboard/addressmap.h
@@ -16,6 +16,7 @@
 #define SBSA_GPIO_BASE            0x60020000
 #define SBSA_SECURE_UART_BASE     0x60030000
 #define SBSA_SMMU_BASE            0x60050000
+#define SBSA_GIC_ITS              0x44081000
 #define SBSA_AHCI_BASE            0x60100000
 #define SBSA_EHCI_BASE            0x60110000
 #define SBSA_SECMEM_BASE          0x20000000

From 817394f12cea2bdd46cfaaea7e3fcaa721b03737 Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Wed, 21 Jan 2026 22:17:33 +0000
Subject: [PATCH 3696/3886] Makefile.mk: generate EDK2 update capsule

Generate a signed UEFI capsule from the final coreboot ROM image using
EDK2 BaseTools.

When using an EDK2 payload and enabling DRIVERS_EFI_UPDATE_CAPSULES and
DRIVERS_EFI_GENERATE_CAPSULE, the build produces build/coreboot.cap once
the ROM is finalised (after all files were added to CBFS). The capsule
can also be generated explicitly with `make capsule`.

Move the capsule generation and certificate preparation into
payloads/external/edk2/Makefile, including generating the trusted root
certificate PCD include via BinToPcd.

Support capsule flows with an embedded FmpDxe driver by optionally
embedding FmpDxe.efi into generated capsules, and wiring the
embedded-driver Kconfig options through to the EDK2 payload build and
capsule generation.

Always set PersistAcrossReset on the capsule. Make InitiateReset
configurable (default off) because Linux rejects capsules with
InitiateReset when writing via /dev/efi_capsule_loader.

Use CONFIG_DRIVERS_EFI_MAIN_FW_VERSION for GenerateCapsule
--fw-version, but fall back to parsing a leading <major>.<minor> from
CONFIG_LOCALVERSION when it is left at 0. If
CONFIG_DRIVERS_EFI_MAIN_FW_LSV is 0, use the resolved firmware version.

Document capsule generation and embedded driver configuration.

Corresponding edk2 patches can be found at:
https://github.com/tianocore/edk2/pull/12053

Change-Id: I5f56b894d40ddb49f3158bb72f0143d0ebe9c34c
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90862
Reviewed-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 .../drivers/efi_capsule_generation.md         |  77 +++++++++++++
 Documentation/drivers/index.md                |   1 +
 Makefile.mk                                   |  22 +++-
 payloads/external/Makefile.mk                 |  22 ++++
 payloads/external/edk2/Makefile               | 105 +++++++++++++++++-
 src/drivers/efi/Kconfig                       |  90 +++++++++++++++
 6 files changed, 315 insertions(+), 2 deletions(-)
 create mode 100644 Documentation/drivers/efi_capsule_generation.md

diff --git a/Documentation/drivers/efi_capsule_generation.md b/Documentation/drivers/efi_capsule_generation.md
new file mode 100644
index 0000000000..84d2c86f9a
--- /dev/null
+++ b/Documentation/drivers/efi_capsule_generation.md
@@ -0,0 +1,77 @@
+# Generating signed UEFI capsules with EDK2
+
+coreboot can cooperate with an EDK2 payload to support firmware updates via the UEFI
+ESRT/FMP capsule mechanism.
+
+This document covers generating a *signed* capsule during the coreboot build.
+
+At present, capsule generation requires a compatible EDK2 tree with the
+corresponding payload-side changes. Upstream support is being tracked in:
+
+https://github.com/tianocore/edk2/pull/12053
+
+Older EDK2 trees may be missing pieces required by this integration.
+
+## Build-time capsule generation
+
+Enable capsule support and use an EDK2 payload:
+
+- `CONFIG_DRIVERS_EFI_UPDATE_CAPSULES`: enable coreboot capsule update support.
+- `CONFIG_DRIVERS_EFI_GENERATE_CAPSULE`: generate `build/coreboot.cap` after the ROM is finalised.
+- `CONFIG_PAYLOAD_EDK2`: build an EDK2 payload.
+
+When enabled, the coreboot build generates `build/coreboot.cap` after the ROM image is
+finalised. The capsule can also be generated explicitly with `make capsule`.
+
+Configure the FMAP allowlist embedded into the ROM as a manifest:
+
+- `CONFIG_DRIVERS_EFI_CAPSULE_REGIONS`: whitespace-separated FMAP region allowlist embedded into
+  the ROM as a manifest (e.g. `COREBOOT EC`).
+
+Configure the ESRT/FMP firmware identity used by the capsule:
+
+- `CONFIG_DRIVERS_EFI_MAIN_FW_GUID`: GUID of the firmware
+- `CONFIG_DRIVERS_EFI_MAIN_FW_VERSION`: firmware version encoded in the capsule header;
+  if set to `0`, derive a value from the leading `<major>.<minor>` in
+  `CONFIG_LOCALVERSION` when possible
+- `CONFIG_DRIVERS_EFI_MAIN_FW_LSV`: lowest supported firmware version; if set to `0`,
+  use the resolved firmware version
+
+Reset behavior during capsule application:
+
+- `CONFIG_DRIVERS_EFI_CAPSULE_INITIATE_RESET`: add the capsule `InitiateReset` flag.
+  This is disabled by default because Linux rejects capsules with `InitiateReset` when using
+  `/dev/efi_capsule_loader`.
+
+## Embedded drivers (FmpDxe in capsule)
+
+Some EDK2 capsule update flows use an embedded `FmpDxe.efi` driver inside the capsule.
+
+To generate capsules with an embedded `FmpDxe.efi`, enable:
+
+- `CONFIG_DRIVERS_EFI_CAPSULE_EMBED_FMP_DXE`: embed `FmpDxe.efi` into generated capsules.
+- `CONFIG_DRIVERS_EFI_CAPSULE_ACCEPT_EMBEDDED_DRIVERS`: configure the EDK2 payload to accept
+  capsules with embedded drivers (sets `PcdCapsuleEmbeddedDriverSupport=TRUE`).
+
+Note: if Secure Boot is enabled, the embedded driver must be signed by a key trusted by the
+running firmware, otherwise capsule processing may fail when loading the embedded driver.
+
+## Capsule signing certificates
+
+`GenerateCapsule` can sign the FMP payload (PKCS#7). Many platforms require signed capsules.
+
+coreboot exposes three Kconfig options for the certificate chain:
+
+- `CONFIG_DRIVERS_EFI_CAPSULE_SIGNER_PRIVATE_CERT`: PEM containing the signing private key and
+  leaf certificate
+- `CONFIG_DRIVERS_EFI_CAPSULE_OTHER_PUBLIC_CERT`: PEM intermediate certificate
+- `CONFIG_DRIVERS_EFI_CAPSULE_TRUSTED_PUBLIC_CERT`: PEM trusted root certificate
+
+If a configured path is relative, it is interpreted relative to the configured EDK2 repository
+inside `payloads/external/edk2/workspace`.
+
+The defaults use the EDK2 BaseTools test certificate chain. Do not use the test keys for
+production firmware updates.
+
+To generate your own certificate chain and convert it into the required PEM files, see:
+`BaseTools/Source/Python/Pkcs7Sign/Readme.md` in the EDK2 tree.
diff --git a/Documentation/drivers/index.md b/Documentation/drivers/index.md
index 381685e068..e0142a8e4d 100644
--- a/Documentation/drivers/index.md
+++ b/Documentation/drivers/index.md
@@ -29,4 +29,5 @@ SMMSTOREv2 <smmstorev2.md>
 SoundWire <soundwire.md>
 USB4 Retimer <retimer.md>
 CBFS SMBIOS hooks <cbfs_smbios.md>
+EDK2 capsule generation <efi_capsule_generation.md>
 ```
diff --git a/Makefile.mk b/Makefile.mk
index 5fccb4a52d..b5e988195f 100644
--- a/Makefile.mk
+++ b/Makefile.mk
@@ -73,11 +73,31 @@ build_complete:: | coreboot
 .PHONY: files_added
 files_added:: | build_complete
 
+# This target can be used to run rules once the ROM is fully finalised
+# (after all files were added to CBFS, and any files_added hooks ran).
+.PHONY: finalised_rom
+finalised_rom:: | files_added
+
+# Optional post-build targets.
+.PHONY: capsule
+capsule::
+
+ifeq ($(CONFIG_PAYLOAD_EDK2)$(CONFIG_DRIVERS_EFI_UPDATE_CAPSULES)$(CONFIG_DRIVERS_EFI_GENERATE_CAPSULE),yyy)
+finalised_rom:: $(obj)/coreboot.cap
+capsule:: $(obj)/coreboot.cap
+
+$(obj)/coreboot.cap: $(obj)/coreboot.rom $(DOTCONFIG) | files_added
+	$(MAKE) -C payloads/external/edk2 coreboot_capsule \
+		COREBOOT_ROM="$(abspath $<)" \
+		COREBOOT_CAPSULE_OUT="$(abspath $@)" \
+		$(EDK2_CAPSULE_ARGS)
+endif
+
 # This target should come just before the show_notices target.  If there
 # are no notices, the build should finish with the text of what was just
 # built.
 .PHONY: show_coreboot
-show_coreboot: | files_added
+show_coreboot: | finalised_rom
 	$(CBFSTOOL) $(obj)/coreboot.rom print -r $(subst $(spc),$(comma),$(all-regions))
 	printf "\nBuilt %s (%s)\n" $(MAINBOARDDIR) $(CONFIG_MAINBOARD_PART_NUMBER)
 	if [ -f "$(CCACHE_STATSLOG)" ]; then \
diff --git a/payloads/external/Makefile.mk b/payloads/external/Makefile.mk
index 429c0b2a85..49428201de 100644
--- a/payloads/external/Makefile.mk
+++ b/payloads/external/Makefile.mk
@@ -176,6 +176,25 @@ warn_no_option_cfr_enabled:
 endif
 endif
 
+EDK2_CAPSULE_ARGS = \
+	CONFIG_EDK2_REPOSITORY=$(CONFIG_EDK2_REPOSITORY) \
+	CONFIG_EDK2_TAG_OR_REV=$(CONFIG_EDK2_TAG_OR_REV) \
+	CONFIG_EDK2_USE_EDK2_PLATFORMS=$(CONFIG_EDK2_USE_EDK2_PLATFORMS) \
+	CONFIG_EDK2_PLATFORMS_REPOSITORY=$(CONFIG_EDK2_PLATFORMS_REPOSITORY) \
+	CONFIG_EDK2_PLATFORMS_TAG_OR_REV=$(CONFIG_EDK2_PLATFORMS_TAG_OR_REV) \
+	CONFIG_EDK2_DEBUG=$(CONFIG_EDK2_DEBUG) \
+	CONFIG_DRIVERS_EFI_MAIN_FW_GUID=$(CONFIG_DRIVERS_EFI_MAIN_FW_GUID) \
+	CONFIG_LOCALVERSION=$(CONFIG_LOCALVERSION) \
+	CONFIG_DRIVERS_EFI_MAIN_FW_VERSION=$(CONFIG_DRIVERS_EFI_MAIN_FW_VERSION) \
+	CONFIG_DRIVERS_EFI_MAIN_FW_LSV=$(CONFIG_DRIVERS_EFI_MAIN_FW_LSV) \
+	CONFIG_DRIVERS_EFI_CAPSULE_ACCEPT_EMBEDDED_DRIVERS=$(CONFIG_DRIVERS_EFI_CAPSULE_ACCEPT_EMBEDDED_DRIVERS) \
+	CONFIG_DRIVERS_EFI_CAPSULE_EMBED_FMP_DXE=$(CONFIG_DRIVERS_EFI_CAPSULE_EMBED_FMP_DXE) \
+	CONFIG_DRIVERS_EFI_CAPSULE_INITIATE_RESET=$(CONFIG_DRIVERS_EFI_CAPSULE_INITIATE_RESET) \
+	CONFIG_DRIVERS_EFI_CAPSULE_REGIONS=$(CONFIG_DRIVERS_EFI_CAPSULE_REGIONS) \
+	CONFIG_DRIVERS_EFI_CAPSULE_SIGNER_PRIVATE_CERT=$(CONFIG_DRIVERS_EFI_CAPSULE_SIGNER_PRIVATE_CERT) \
+	CONFIG_DRIVERS_EFI_CAPSULE_OTHER_PUBLIC_CERT=$(CONFIG_DRIVERS_EFI_CAPSULE_OTHER_PUBLIC_CERT) \
+	CONFIG_DRIVERS_EFI_CAPSULE_TRUSTED_PUBLIC_CERT=$(CONFIG_DRIVERS_EFI_CAPSULE_TRUSTED_PUBLIC_CERT)
+
 $(obj)/UEFIPAYLOAD.fd: $(DOTCONFIG) $(IPXE_EFI)
 	$(MAKE) -C payloads/external/edk2 UefiPayloadPkg \
 		HOSTCC="$(HOSTCC)" \
@@ -220,6 +239,9 @@ $(obj)/UEFIPAYLOAD.fd: $(DOTCONFIG) $(IPXE_EFI)
 		CONFIG_SOC_AMD_COMMON_BLOCK_PSP_GEN2=$(CONFIG_SOC_AMD_COMMON_BLOCK_PSP_GEN2) \
 		CONFIG_DRIVERS_EFI_UPDATE_CAPSULES=$(CONFIG_DRIVERS_EFI_UPDATE_CAPSULES) \
 		CONFIG_DRIVERS_EFI_MAIN_FW_GUID=$(CONFIG_DRIVERS_EFI_MAIN_FW_GUID) \
+		CONFIG_DRIVERS_EFI_CAPSULE_ACCEPT_EMBEDDED_DRIVERS=$(CONFIG_DRIVERS_EFI_CAPSULE_ACCEPT_EMBEDDED_DRIVERS) \
+		CONFIG_DRIVERS_EFI_CAPSULE_EMBED_FMP_DXE=$(CONFIG_DRIVERS_EFI_CAPSULE_EMBED_FMP_DXE) \
+		CONFIG_DRIVERS_EFI_CAPSULE_TRUSTED_PUBLIC_CERT=$(CONFIG_DRIVERS_EFI_CAPSULE_TRUSTED_PUBLIC_CERT) \
 		GCC_CC_x86_32=$(GCC_CC_x86_32) \
 		GCC_CC_x86_64=$(GCC_CC_x86_64) \
 		GCC_CC_arm=$(GCC_CC_arm) \
diff --git a/payloads/external/edk2/Makefile b/payloads/external/edk2/Makefile
index c9bd36a27f..09c38d8cf8 100644
--- a/payloads/external/edk2/Makefile
+++ b/payloads/external/edk2/Makefile
@@ -5,7 +5,17 @@ export SHELL := env bash
 
 project_name = edk2
 export WORKSPACE := $(CURDIR)/workspace
-export EDK2_PATH := $(WORKSPACE)/$(word 3,$(subst /, ,$(CONFIG_EDK2_REPOSITORY)))
+
+strip_quotes = $(subst ",,$(1))
+
+EDK2_REPOSITORY := $(call strip_quotes,$(CONFIG_EDK2_REPOSITORY))
+EDK2_PLATFORMS_REPOSITORY := $(call strip_quotes,$(CONFIG_EDK2_PLATFORMS_REPOSITORY))
+EDK2_PATH_REPO_ROOT := $(word 3,$(subst /, ,$(EDK2_REPOSITORY)))
+export EDK2_PATH := $(WORKSPACE)/$(EDK2_PATH_REPO_ROOT)
+
+define edk2_abspath
+$(if $(filter /%,$(1)),$(1),$(EDK2_PATH)/$(1))
+endef
 
 ifeq ($(CONFIG_EDK2_USE_EDK2_PLATFORMS),y)
 BUILD_STR += -D USE_EDK2_PLATFORMS=TRUE
@@ -128,6 +138,39 @@ ifeq ($(CONFIG_DRIVERS_EFI_UPDATE_CAPSULES),y)
 BUILD_STR += -D CAPSULE_SUPPORT=TRUE
 BUILD_STR += -D CAPSULE_MAIN_FW_GUID=$(CONFIG_DRIVERS_EFI_MAIN_FW_GUID)
 endif
+ifeq ($(CONFIG_DRIVERS_EFI_CAPSULE_ACCEPT_EMBEDDED_DRIVERS),y)
+BUILD_STR += --pcd gEfiMdeModulePkgTokenSpaceGuid.PcdCapsuleEmbeddedDriverSupport=TRUE
+endif
+ifeq ($(CONFIG_DRIVERS_EFI_CAPSULE_EMBED_FMP_DXE),y)
+BUILD_STR += -D CAPSULE_EMBED_FMP_DXE=TRUE
+endif
+
+CAPSULE_PCD_INC_REL := BaseTools/Source/Python/Pkcs7Sign/TestRoot.cer.gFmpDevicePkgTokenSpaceGuid.PcdFmpDevicePkcs7CertBufferXdr.inc
+CAPSULE_PCD_INC := $(EDK2_PATH)/$(CAPSULE_PCD_INC_REL)
+CAPSULE_PCD_NAME := gFmpDevicePkgTokenSpaceGuid.PcdFmpDevicePkcs7CertBufferXdr
+
+CAPSULE_GUID := $(call strip_quotes,$(CONFIG_DRIVERS_EFI_MAIN_FW_GUID))
+CAPSULE_REGIONS := $(call strip_quotes,$(CONFIG_DRIVERS_EFI_CAPSULE_REGIONS))
+CAPSULE_LOCALVERSION := $(call strip_quotes,$(CONFIG_LOCALVERSION))
+CAPSULE_SIGNER_PRIVATE_CERT := $(call strip_quotes,$(CONFIG_DRIVERS_EFI_CAPSULE_SIGNER_PRIVATE_CERT))
+CAPSULE_OTHER_PUBLIC_CERT := $(call strip_quotes,$(CONFIG_DRIVERS_EFI_CAPSULE_OTHER_PUBLIC_CERT))
+CAPSULE_TRUSTED_PUBLIC_CERT := $(call strip_quotes,$(CONFIG_DRIVERS_EFI_CAPSULE_TRUSTED_PUBLIC_CERT))
+
+CAPSULE_SIGNER_PRIVATE_CERT_PATH := $(call edk2_abspath,$(CAPSULE_SIGNER_PRIVATE_CERT))
+CAPSULE_OTHER_PUBLIC_CERT_PATH := $(call edk2_abspath,$(CAPSULE_OTHER_PUBLIC_CERT))
+CAPSULE_TRUSTED_PUBLIC_CERT_PATH := $(call edk2_abspath,$(CAPSULE_TRUSTED_PUBLIC_CERT))
+
+# AppendRmapManifest.py moved from BaseTools/Scripts to UefiPayloadPkg/Tools in
+# newer edk2 trees.
+EDK2_APPEND_RMAP_MANIFEST = $(firstword $(wildcard \
+	$(EDK2_PATH)/UefiPayloadPkg/Tools/AppendRmapManifest.py \
+	$(EDK2_PATH)/BaseTools/Scripts/AppendRmapManifest.py \
+))
+
+# If FmpDxe is built, edk2 also places it in the top-level X64 output dir.
+EDK2_FMP_DXE = $(WORKSPACE)/Build/UefiPayloadPkgX64/$(RELEASE_STR)_GCC/X64/FmpDxe.efi
+
+CAPSULE_ROOT_CERT_DER := $(WORKSPACE)/capsule_trusted_root.der
 
 #
 # One or more downstream edk2 repositories support the following additional options:
@@ -223,6 +266,10 @@ $(EDK2_PATH): $(WORKSPACE)
 	fi
 	cd $(EDK2_PATH); \
 		git checkout MdeModulePkg/Logo/Logo.bmp > /dev/null 2>&1 || true; \
+		git checkout "$(CAPSULE_PCD_INC_REL)" > /dev/null 2>&1 || true; \
+		if ! git ls-files --error-unmatch "$(CAPSULE_PCD_INC_REL)" >/dev/null 2>&1; then \
+			rm -f "$(CAPSULE_PCD_INC_REL)" || true; \
+		fi; \
 		if [ -e UefiPayloadPkg/ShimLayer/UniversalPayload.o ]; then \
 			rm UefiPayloadPkg/ShimLayer/UniversalPayload.o; \
 		fi; \
@@ -286,6 +333,19 @@ checktools:
 		exit 1; \
 	fi
 
+ifeq ($(CONFIG_DRIVERS_EFI_UPDATE_CAPSULES)$(CONFIG_DRIVERS_EFI_GENERATE_CAPSULE),yy)
+capsule_keys: $(EDK2_PATH)
+	type openssl > /dev/null 2>&1 || ( echo "ERROR: Please install openssl."; exit 1 )
+	test -f "$(CAPSULE_TRUSTED_PUBLIC_CERT_PATH)"
+	test -f "$(EDK2_PATH)/BaseTools/Scripts/BinToPcd.py"
+	mkdir -p "$(dir $(CAPSULE_PCD_INC))"
+	openssl x509 -in "$(CAPSULE_TRUSTED_PUBLIC_CERT_PATH)" -outform der -out "$(CAPSULE_ROOT_CERT_DER)"
+	python3 "$(EDK2_PATH)/BaseTools/Scripts/BinToPcd.py" -q -x \
+		-i "$(CAPSULE_ROOT_CERT_DER)" -o "$(CAPSULE_PCD_INC)" -p "$(CAPSULE_PCD_NAME)"
+
+prep: capsule_keys
+endif
+
 print:
 	echo "   ##### $(project_name) Build Summary #####"
 	echo "   Repository:     $(CONFIG_EDK2_REPOSITORY)"
@@ -359,3 +419,46 @@ distclean:
 	rm -rf $(WORKSPACE)
 
 .PHONY: $(EDK2_PATH) checktools logo UefiPayloadPkg UniversalPayload clean distclean
+
+.PHONY: coreboot_capsule capsule_keys
+
+coreboot_capsule: $(EDK2_PATH)
+	test -n "$(COREBOOT_ROM)"
+	test -n "$(COREBOOT_CAPSULE_OUT)"
+	test -f "$(COREBOOT_ROM)"
+	test -f "$(EDK2_APPEND_RMAP_MANIFEST)"
+	test -x "$(EDK2_PATH)/BaseTools/BinWrappers/PosixLike/GenerateCapsule"
+	test -f "$(CAPSULE_SIGNER_PRIVATE_CERT_PATH)"
+	test -f "$(CAPSULE_OTHER_PUBLIC_CERT_PATH)"
+	test -f "$(CAPSULE_TRUSTED_PUBLIC_CERT_PATH)"
+	rmap_rom="$${COREBOOT_CAPSULE_OUT%.cap}.rmap.rom"; \
+	set -e; \
+	python3 "$(EDK2_APPEND_RMAP_MANIFEST)" -o "$$rmap_rom" $(foreach r,$(CAPSULE_REGIONS),-r $(r)) "$(COREBOOT_ROM)"; \
+	embedded_driver_args=(); \
+	if [ "$(CONFIG_DRIVERS_EFI_CAPSULE_EMBED_FMP_DXE)" = "y" ]; then \
+		test -f "$(EDK2_FMP_DXE)"; \
+		embedded_driver_args=( --embedded-driver "$(EDK2_FMP_DXE)" ); \
+	fi; \
+	fw_version=$$(( $(CONFIG_DRIVERS_EFI_MAIN_FW_VERSION) )); \
+	if [ $$fw_version -eq 0 ]; then \
+		if [[ "$(CAPSULE_LOCALVERSION)" =~ ^[^0-9]*([0-9]+)[.]([0-9]+) ]]; then \
+			fw_version=$$(( (10#$${BASH_REMATCH[1]} << 16) | 10#$${BASH_REMATCH[2]} )); \
+		fi; \
+	fi; \
+	lsv=$$(( $(CONFIG_DRIVERS_EFI_MAIN_FW_LSV) )); \
+	if [ $$lsv -eq 0 ]; then \
+		lsv=$$fw_version; \
+	fi; \
+	capflags=( --capflag PersistAcrossReset ); \
+	if [ "$(CONFIG_DRIVERS_EFI_CAPSULE_INITIATE_RESET)" = "y" ]; then \
+		capflags+=( --capflag InitiateReset ); \
+	fi; \
+	"$(EDK2_PATH)/BaseTools/BinWrappers/PosixLike/GenerateCapsule" -e -o "$(COREBOOT_CAPSULE_OUT)" \
+		--guid "$(CAPSULE_GUID)" \
+		"$${capflags[@]}" \
+		--fw-version $$fw_version --lsv $$lsv \
+		--signer-private-cert "$(CAPSULE_SIGNER_PRIVATE_CERT_PATH)" \
+		--other-public-cert "$(CAPSULE_OTHER_PUBLIC_CERT_PATH)" \
+		--trusted-public-cert "$(CAPSULE_TRUSTED_PUBLIC_CERT_PATH)" \
+		"$${embedded_driver_args[@]}" \
+		"$$rmap_rom"
diff --git a/src/drivers/efi/Kconfig b/src/drivers/efi/Kconfig
index 9effc0d778..8730290922 100644
--- a/src/drivers/efi/Kconfig
+++ b/src/drivers/efi/Kconfig
@@ -57,3 +57,93 @@ config DRIVERS_EFI_UPDATE_CAPSULES
 	  Adds a driver that is able to parse CapsuleUpdateData* EFI variables
 	  to discover firmware updates and expose them for tianocore thorough
 	  CBMEM for execution.  tianocore is responsible for erasing the variables.
+
+config DRIVERS_EFI_CAPSULE_ACCEPT_EMBEDDED_DRIVERS
+	bool "Allow embedded drivers in update capsules"
+	depends on PAYLOAD_EDK2 && DRIVERS_EFI_UPDATE_CAPSULES
+	help
+	  Allow the EDK2 payload's capsule processing to load embedded drivers
+	  from capsules (PcdCapsuleEmbeddedDriverSupport).
+
+	  This is required for capsules that contain embedded drivers.
+
+	  Note: if Secure Boot is enabled, the embedded driver must be signed by a
+	  key trusted by the running firmware (or capsule processing may fail).
+
+config DRIVERS_EFI_GENERATE_CAPSULE
+	bool "Generate an update capsule during the build"
+	depends on PAYLOAD_EDK2 && DRIVERS_EFI_UPDATE_CAPSULES
+	help
+	  Generates a UEFI capsule from the final ROM image using EDK2 BaseTools.
+	  This is intended for fwupd update workflows that use the ESRT/FMP
+	  mechanism.
+
+config DRIVERS_EFI_CAPSULE_EMBED_FMP_DXE
+	bool "Embed FmpDxe driver into generated capsules"
+	depends on DRIVERS_EFI_GENERATE_CAPSULE
+	depends on DRIVERS_EFI_CAPSULE_ACCEPT_EMBEDDED_DRIVERS
+	help
+	  When generating build/coreboot.cap, embed the built FmpDxe.efi as an
+	  embedded driver in the capsule.
+
+
+config DRIVERS_EFI_CAPSULE_INITIATE_RESET
+	bool "Request reset after capsule is applied"
+	default n
+	depends on DRIVERS_EFI_GENERATE_CAPSULE
+	help
+	  Add the InitiateReset capsule flag when generating build/coreboot.cap.
+
+	  Note: Linux rejects capsules with InitiateReset when using
+	  /dev/efi_capsule_loader.
+
+
+config DRIVERS_EFI_CAPSULE_REGIONS
+	string "FMAP regions to include in the capsule manifest"
+	default "COREBOOT"
+	depends on DRIVERS_EFI_GENERATE_CAPSULE
+	help
+	  Whitespace-separated list of FMAP regions that the update capsule is
+	  allowed to modify. The list is embedded as a manifest inside the ROM
+	  image prior to building the capsule.
+
+menu "Capsule signing certificates"
+	depends on DRIVERS_EFI_GENERATE_CAPSULE
+
+config DRIVERS_EFI_CAPSULE_SIGNER_PRIVATE_CERT
+	string "PEM file used to sign generated capsules"
+	default "BaseTools/Source/Python/Pkcs7Sign/TestCert.pem"
+	depends on DRIVERS_EFI_GENERATE_CAPSULE
+	help
+	  Path to a PEM file containing the private key and leaf certificate used
+	  when signing the capsule with EDK2 GenerateCapsule.
+
+	  If the path is relative, it is interpreted relative to the configured
+	  EDK2 repository (payloads/external/edk2 workspace).
+
+	  See Documentation/drivers/efi_capsule_generation.md and
+	  BaseTools/Source/Python/Pkcs7Sign/Readme.md in the EDK2 tree.
+
+config DRIVERS_EFI_CAPSULE_OTHER_PUBLIC_CERT
+	string "Intermediate certificate for capsule signing (PEM)"
+	default "BaseTools/Source/Python/Pkcs7Sign/TestSub.pub.pem"
+	depends on DRIVERS_EFI_GENERATE_CAPSULE
+	help
+	  Path to the intermediate certificate (PEM) used when generating a PKCS#7
+	  signature for the capsule.
+
+	  If the path is relative, it is interpreted relative to the configured
+	  EDK2 repository (payloads/external/edk2 workspace).
+
+config DRIVERS_EFI_CAPSULE_TRUSTED_PUBLIC_CERT
+	string "Trusted root certificate for capsule signing (PEM)"
+	default "BaseTools/Source/Python/Pkcs7Sign/TestRoot.pub.pem"
+	depends on DRIVERS_EFI_GENERATE_CAPSULE
+	help
+	  Path to the trusted root certificate (PEM) used when generating a PKCS#7
+	  signature for the capsule.
+
+	  If the path is relative, it is interpreted relative to the configured
+	  EDK2 repository (payloads/external/edk2 workspace).
+
+endmenu

From 5c20d9ce764b906d9597b07e5ae280a93a3f1768 Mon Sep 17 00:00:00 2001
From: Felix Held <felix-coreboot@felixheld.de>
Date: Fri, 13 Mar 2026 16:01:35 +0100
Subject: [PATCH 3697/3886] 3rdparty/amd_blobs: advance submodule pointer

This pulls in the following changes from the submodule:
- README.md: Add psirt email address
- MDN: Update ABL to version 3516B01Bh
- MDN: Upgrade microcode patch to 08A0000Bh
- cezanne: Update ABL to 0x23216072
- cezanne: Upgrade microcode patch to 0A500014h
- Upgrade microcode patch of PCO to 0810810Eh, Pollock to 08200105
- Picasso/Pollock/Dali: Update SMU Fimemware
- Update Phoenix FP7/FP8 binaries to PI release 1.2.0.0d
- Add Phoenix AM5 binaries from PI release 1.2.7.0
- MDN: Update mendocino SMU to 90.49.0
- MDN: Upgrade microcode patch to 08A0000Ch
- MDN: Upgrade ABL to 3516B021
- CZN: Updata PSP stage 2 to E5.11.11.75
- PCO: Upgrade ABL to CABLRV26012800
- add binaries for Strix, Krackan, and Krackan2e
- MDN: Update PSP to v00.3C.04.18
- CZN: Upgrade ABL to RABLCZN23216073
- FWDEV-177733: Upgrade PSP version to 75.11.11.20
- move the Phoenix AM5 files to a location more in line with the rest
- add binaries for Strix Halo

Change-Id: I7404a53b0c3b27d73d6e0633520e6040539e992f
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91669
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 3rdparty/amd_blobs | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/3rdparty/amd_blobs b/3rdparty/amd_blobs
index 26c572974b..0a6d270fb3 160000
--- a/3rdparty/amd_blobs
+++ b/3rdparty/amd_blobs
@@ -1 +1 @@
-Subproject commit 26c572974bcf7255930b0e9a51da3144ed0104b5
+Subproject commit 0a6d270fb36f726b26909c3369f155e44afeedc4

From 1172a4e6ee634b42a28b10282d0c36aa975cbc0e Mon Sep 17 00:00:00 2001
From: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Date: Mon, 16 Mar 2026 09:45:52 +0800
Subject: [PATCH 3698/3886] mb/google/brya/var/yavilla: Set LGD touchscreen HID
 address to 0x01

Follow vendor design change.

BUG=b:483762467
TEST=build nissa coreboot image
     touchscreen is working

Change-Id: I5aaf45ccd8f930fb503a39dd9f66a913f1722297
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91682
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/google/brya/variants/yavilla/overridetree.cb | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/mainboard/google/brya/variants/yavilla/overridetree.cb b/src/mainboard/google/brya/variants/yavilla/overridetree.cb
index 3686de90e9..948353443a 100644
--- a/src/mainboard/google/brya/variants/yavilla/overridetree.cb
+++ b/src/mainboard/google/brya/variants/yavilla/overridetree.cb
@@ -344,7 +344,7 @@ chip soc/intel/alderlake
 				register "generic.enable_delay_ms" = "1"
 				register "generic.has_power_resource" = "1"
 				register "generic.use_gpio_for_status" = "true"
-				register "hid_desc_reg_offset" = "0x00"
+				register "hid_desc_reg_offset" = "0x01"
 				device i2c 34 on end
 			end
 			chip drivers/i2c/hid

From 53bc76856c0134078180a640d5dc6d8b1157b5f6 Mon Sep 17 00:00:00 2001
From: Angel Pons <th3fanbus@gmail.com>
Date: Sun, 8 Mar 2026 17:25:46 +0100
Subject: [PATCH 3699/3886] nb/intel/broadwell/gma.c: Retype some variables

Use `bool` and `u16` instead of `int` where appropriate.

Change-Id: I813b7bbebdd26547941d1a5b48a2dd08ff10e753
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91619
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
---
 src/northbridge/intel/broadwell/gma.c | 23 ++++++++++++-----------
 1 file changed, 12 insertions(+), 11 deletions(-)

diff --git a/src/northbridge/intel/broadwell/gma.c b/src/northbridge/intel/broadwell/gma.c
index a166b7998b..53ff053e10 100644
--- a/src/northbridge/intel/broadwell/gma.c
+++ b/src/northbridge/intel/broadwell/gma.c
@@ -359,16 +359,16 @@ static void gma_setup_panel(struct device *dev)
 	}
 }
 
-static int igd_get_cdclk_haswell(u32 *const cdsel, int *const inform_pc,
+static int igd_get_cdclk_haswell(u32 *const cdsel, bool *const inform_pc,
 				 struct device *const dev)
 {
 	const struct northbridge_intel_broadwell_config *const conf = config_of(dev);
 	int cdclk = conf->cdclk;
 
 	/* Check for ULX GT1 or GT2 */
-	const int devid = pci_read_config16(dev, PCI_DEVICE_ID);
-	const int cpu_is_ult = cpu_family_model() == HASWELL_FAMILY_ULT;
-	const int gpu_is_ulx = devid == IGD_HASWELL_ULX_GT1 ||
+	const u16 devid = pci_read_config16(dev, PCI_DEVICE_ID);
+	const bool cpu_is_ult = cpu_family_model() == HASWELL_FAMILY_ULT;
+	const bool gpu_is_ulx = devid == IGD_HASWELL_ULX_GT1 ||
 				devid == IGD_HASWELL_ULX_GT2;
 
 	/* Check for fixed fused clock */
@@ -393,7 +393,7 @@ static int igd_get_cdclk_haswell(u32 *const cdsel, int *const inform_pc,
 	return cdclk;
 }
 
-static int igd_get_cdclk_broadwell(u32 *const cdsel, int *const inform_pc,
+static int igd_get_cdclk_broadwell(u32 *const cdsel, bool *const inform_pc,
 				   struct device *const dev)
 {
 	static const u32 cdsel_by_cdclk[] = { 0, 2, 0, 1, 3 };
@@ -401,9 +401,9 @@ static int igd_get_cdclk_broadwell(u32 *const cdsel, int *const inform_pc,
 	int cdclk = conf->cdclk;
 
 	/* Check for ULX */
-	const int devid = pci_read_config16(dev, PCI_DEVICE_ID);
-	const int cpu_is_ult = cpu_family_model() == BROADWELL_FAMILY_ULT;
-	const int gpu_is_ulx = devid == IGD_BROADWELL_Y_GT2;
+	const u16 devid = pci_read_config16(dev, PCI_DEVICE_ID);
+	const bool cpu_is_ult = cpu_family_model() == BROADWELL_FAMILY_ULT;
+	const bool gpu_is_ulx = devid == IGD_BROADWELL_Y_GT2;
 
 	/* Inform power controller of upcoming frequency change */
 	gtt_write(0x138128, 0);
@@ -442,10 +442,11 @@ static int igd_get_cdclk_broadwell(u32 *const cdsel, int *const inform_pc,
 	return cdclk;
 }
 
-static void igd_cdclk_init(struct device *dev, const int is_broadwell)
+static void igd_cdclk_init(struct device *dev, const bool is_broadwell)
 {
 	u32 dpdiv, cdsel, cdval;
-	int cdclk, inform_pc;
+	int cdclk;
+	bool inform_pc;
 
 	if (is_broadwell)
 		cdclk = igd_get_cdclk_broadwell(&cdsel, &inform_pc, dev);
@@ -502,7 +503,7 @@ static void igd_cdclk_init(struct device *dev, const int is_broadwell)
 
 static void igd_init(struct device *dev)
 {
-	int is_broadwell = !!(cpu_family_model() == BROADWELL_FAMILY_ULT);
+	bool is_broadwell = !!(cpu_family_model() == BROADWELL_FAMILY_ULT);
 	u32 rp1_gfx_freq;
 
 	intel_gma_init_igd_opregion();

From 31f4c30a0853df7687a3abff91609bbc943b7d15 Mon Sep 17 00:00:00 2001
From: Angel Pons <th3fanbus@gmail.com>
Date: Sun, 8 Mar 2026 17:51:18 +0100
Subject: [PATCH 3700/3886] nb/intel/broadwell: Clean up cosmetics

Yes, the "Coding Style" page of the coreboot docs states the following:

    Bulk style changes to existing code ("cleanup patches") should
    avoid changing existing style choices unless they actually
    violate this style guide, or there is broad consensus that the
    new version is an improvement. By default the style choices of
    the original author should be honored.

However, when attempting to unify two codebases (Haswell and Broadwell),
style differences only make it harder to find the functional differences
between the codebases. So, it makes sense to unify the code style first,
so that only functional differences remain. Especially if these cosmetic
alignment changes are reproducible, i.e. they don't change the resulting
coreboot.rom when using `make BUILD_TIMELESS=1` to build.

Sort includes alphabetically, unbreak some long lines that are less than
96 characters long, combine variable declaration and initialisation, use
C-style comments, use one line for printk strings (easier to use grep to
find them this way), constify some values the compiler already knew they
were constant (they get inlined anyway), remove unnecessary parentheses,
fix space usage around operators, align some comments with Haswell code,
rename a few things for consistency with Haswell, use an early return in
place of an if-block (like Haswell does), drop a few unused includes and
include `types.h` from files that need it.

Tested with BUILD_TIMELESS=1, Purism Librem 15 v2 remains identical.

Change-Id: I872068e93f1960d90a914193ccb346fc77652220
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91620
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
---
 src/northbridge/intel/broadwell/chip.h        |   2 +-
 src/northbridge/intel/broadwell/early_init.c  |  35 ++-
 src/northbridge/intel/broadwell/gma.c         |  69 +++---
 .../intel/broadwell/include/soc/pei_wrapper.h |  10 +-
 src/northbridge/intel/broadwell/memmap.c      |   5 +-
 src/northbridge/intel/broadwell/northbridge.c | 219 ++++++++----------
 src/northbridge/intel/broadwell/pei_data.c    |   2 +-
 src/northbridge/intel/broadwell/raminit.c     |  29 +--
 src/northbridge/intel/broadwell/refcode.c     |  10 +-
 .../intel/broadwell/report_platform.c         |  46 ++--
 src/northbridge/intel/broadwell/romstage.c    |   4 +-
 src/northbridge/intel/broadwell/spd.c         |   7 +-
 12 files changed, 192 insertions(+), 246 deletions(-)

diff --git a/src/northbridge/intel/broadwell/chip.h b/src/northbridge/intel/broadwell/chip.h
index 6b02f59ed3..adba15ff25 100644
--- a/src/northbridge/intel/broadwell/chip.h
+++ b/src/northbridge/intel/broadwell/chip.h
@@ -4,7 +4,7 @@
 #define _SOC_INTEL_BROADWELL_CHIP_H_
 
 #include <drivers/intel/gma/gma.h>
-#include <stdint.h>
+#include <types.h>
 
 struct northbridge_intel_broadwell_config {
 	/*
diff --git a/src/northbridge/intel/broadwell/early_init.c b/src/northbridge/intel/broadwell/early_init.c
index 8b9028baff..ad70070149 100644
--- a/src/northbridge/intel/broadwell/early_init.c
+++ b/src/northbridge/intel/broadwell/early_init.c
@@ -30,29 +30,28 @@ static void broadwell_setup_bars(void)
 
 void systemagent_early_init(void)
 {
-	const bool vtd_capable =
-		!(pci_read_config32(HOST_BRIDGE, CAPID0_A) & VTD_DISABLE);
+	const bool vtd_capable = !(pci_read_config32(HOST_BRIDGE, CAPID0_A) & VTD_DISABLE);
 
 	broadwell_setup_bars();
 
 	/* Device enable: IGD and Mini-HD */
 	pci_write_config32(HOST_BRIDGE, DEVEN, DEVEN_D0EN | DEVEN_D2EN | DEVEN_D3EN);
 
-	if (vtd_capable) {
-		/* setup BARs: zeroize top 32 bits; set enable bit */
-		mchbar_write32(GFXVTBAR + 4, GFXVT_BASE_ADDRESS >> 32);
-		mchbar_write32(GFXVTBAR + 0, GFXVT_BASE_ADDRESS | 1);
-		mchbar_write32(VTVC0BAR + 4, VTVC0_BASE_ADDRESS >> 32);
-		mchbar_write32(VTVC0BAR + 0, VTVC0_BASE_ADDRESS | 1);
+	if (!vtd_capable)
+		return;
 
-		/* set PRSCAPDIS, lock GFXVTBAR policy cfg registers */
-		u32 reg32;
-		reg32 = read32p(GFXVT_BASE_ADDRESS + ARCHDIS);
-		write32p(GFXVT_BASE_ADDRESS + ARCHDIS,
-				reg32 | DMAR_LCKDN | PRSCAPDIS);
-		/* lock VTVC0BAR policy cfg registers */
-		reg32 = read32p(VTVC0_BASE_ADDRESS + ARCHDIS);
-		write32p(VTVC0_BASE_ADDRESS + ARCHDIS,
-				reg32 | DMAR_LCKDN);
-	}
+	/* Setup BARs: zeroize top 32 bits; set enable bit */
+	mchbar_write32(GFXVTBAR + 4, GFXVT_BASE_ADDRESS >> 32);
+	mchbar_write32(GFXVTBAR + 0, GFXVT_BASE_ADDRESS | 1);
+	mchbar_write32(VTVC0BAR + 4, VTVC0_BASE_ADDRESS >> 32);
+	mchbar_write32(VTVC0BAR + 0, VTVC0_BASE_ADDRESS | 1);
+
+	/* Set PRSCAPDIS, lock GFXVTBAR policy config registers */
+	u32 reg32;
+	reg32 = read32p(GFXVT_BASE_ADDRESS + ARCHDIS);
+	write32p(GFXVT_BASE_ADDRESS + ARCHDIS, reg32 | DMAR_LCKDN | PRSCAPDIS);
+
+	/* lock VTVC0BAR policy cfg registers */
+	reg32 = read32p(VTVC0_BASE_ADDRESS + ARCHDIS);
+	write32p(VTVC0_BASE_ADDRESS + ARCHDIS, reg32 | DMAR_LCKDN);
 }
diff --git a/src/northbridge/intel/broadwell/gma.c b/src/northbridge/intel/broadwell/gma.c
index 53ff053e10..9ea8ac154c 100644
--- a/src/northbridge/intel/broadwell/gma.c
+++ b/src/northbridge/intel/broadwell/gma.c
@@ -1,6 +1,5 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
-#include <acpi/acpi.h>
 #include <device/mmio.h>
 #include <device/pci_ops.h>
 #include <bootmode.h>
@@ -11,20 +10,20 @@
 #include <device/device.h>
 #include <device/pci.h>
 #include <device/pci_ids.h>
-#include <string.h>
-#include <reg_script.h>
 #include <drivers/intel/gma/i915.h>
 #include <drivers/intel/gma/i915_reg.h>
 #include <drivers/intel/gma/libgfxinit.h>
 #include <drivers/intel/gma/opregion.h>
-#include <soc/pm.h>
-#include <soc/systemagent.h>
+#include <reg_script.h>
 #include <northbridge/intel/broadwell/chip.h>
 #include <security/vboot/vbnv.h>
 #include <soc/igd.h>
+#include <soc/pm.h>
+#include <soc/systemagent.h>
+#include <string.h>
 #include <types.h>
 
-#define GT_RETRY		1000
+#define GTT_RETRY		1000
 enum {
 	GT_CDCLK_DEFAULT = 0,
 	GT_CDCLK_337,
@@ -43,7 +42,7 @@ struct reg_script haswell_early_init_script[] = {
 	/* Enable Force Wake */
 	REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0xa180, 0x00000020),
 	REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0xa188, 0x00010001),
-	REG_RES_POLL32(PCI_BASE_ADDRESS_0, FORCEWAKE_ACK_HSW, 1, 1, GT_RETRY),
+	REG_RES_POLL32(PCI_BASE_ADDRESS_0, FORCEWAKE_ACK_HSW, 1, 1, GTT_RETRY),
 
 	/* Enable Counters */
 	REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xa248, 0x00000016),
@@ -104,10 +103,10 @@ struct reg_script haswell_early_init_script[] = {
 	REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0xa00c, 0x08000000),
 
 	/* Set RC6 VIDs */
-	REG_RES_POLL32(PCI_BASE_ADDRESS_0, 0x138124, (1 << 31), 0, GT_RETRY),
+	REG_RES_POLL32(PCI_BASE_ADDRESS_0, 0x138124, (1 << 31), 0, GTT_RETRY),
 	REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0x138128, 0),
 	REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0x138124, 0x80000004),
-	REG_RES_POLL32(PCI_BASE_ADDRESS_0, 0x138124, (1 << 31), 0, GT_RETRY),
+	REG_RES_POLL32(PCI_BASE_ADDRESS_0, 0x138124, (1 << 31), 0, GTT_RETRY),
 
 	/* Enable PM Interrupts */
 	REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0x4402c, 0x03000076),
@@ -127,13 +126,12 @@ static const struct reg_script haswell_late_init_script[] = {
 
 	/* Disable Force Wake */
 	REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0xa188, 0x00010000),
-	REG_RES_POLL32(PCI_BASE_ADDRESS_0, FORCEWAKE_ACK_HSW, 1, 0, GT_RETRY),
+	REG_RES_POLL32(PCI_BASE_ADDRESS_0, FORCEWAKE_ACK_HSW, 1, 0, GTT_RETRY),
 	REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0xa188, 0x00000001),
 
 	/* Enable power well for DP and Audio */
 	REG_RES_OR32(PCI_BASE_ADDRESS_0, 0x45400, (1 << 31)),
-	REG_RES_POLL32(PCI_BASE_ADDRESS_0, 0x45400,
-		       (1 << 30), (1 << 30), GT_RETRY),
+	REG_RES_POLL32(PCI_BASE_ADDRESS_0, 0x45400, (1 << 30), (1 << 30), GTT_RETRY),
 
 	REG_SCRIPT_END
 };
@@ -141,7 +139,7 @@ static const struct reg_script haswell_late_init_script[] = {
 static const struct reg_script broadwell_early_init_script[] = {
 	/* Enable Force Wake */
 	REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0xa188, 0x00010001),
-	REG_RES_POLL32(PCI_BASE_ADDRESS_0, FORCEWAKE_ACK_HSW, 1, 1, GT_RETRY),
+	REG_RES_POLL32(PCI_BASE_ADDRESS_0, FORCEWAKE_ACK_HSW, 1, 1, GTT_RETRY),
 
 	/* Enable push bus metric control and shift */
 	REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0xa248, 0x00000004),
@@ -206,10 +204,10 @@ static const struct reg_script broadwell_early_init_script[] = {
 	REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0xa090, 0x90040000),
 
 	/* Set RC6 VIDs */
-	REG_RES_POLL32(PCI_BASE_ADDRESS_0, 0x138124, (1 << 31), 0, GT_RETRY),
+	REG_RES_POLL32(PCI_BASE_ADDRESS_0, 0x138124, (1 << 31), 0, GTT_RETRY),
 	REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0x138128, 0),
 	REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0x138124, 0x80000004),
-	REG_RES_POLL32(PCI_BASE_ADDRESS_0, 0x138124, (1 << 31), 0, GT_RETRY),
+	REG_RES_POLL32(PCI_BASE_ADDRESS_0, 0x138124, (1 << 31), 0, GTT_RETRY),
 
 	/* Enable PM Interrupts */
 	REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0x4402c, 0x03000076),
@@ -228,12 +226,11 @@ static const struct reg_script broadwell_late_init_script[] = {
 
 	/* Disable Force Wake */
 	REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0xa188, 0x00010000),
-	REG_RES_POLL32(PCI_BASE_ADDRESS_0, FORCEWAKE_ACK_HSW, 1, 0, GT_RETRY),
+	REG_RES_POLL32(PCI_BASE_ADDRESS_0, FORCEWAKE_ACK_HSW, 1, 0, GTT_RETRY),
 
 	/* Enable power well for DP and Audio */
 	REG_RES_OR32(PCI_BASE_ADDRESS_0, 0x45400, (1 << 31)),
-	REG_RES_POLL32(PCI_BASE_ADDRESS_0, 0x45400,
-		       (1 << 30), (1 << 30), GT_RETRY),
+	REG_RES_POLL32(PCI_BASE_ADDRESS_0, 0x45400, (1 << 30), (1 << 30), GTT_RETRY),
 
 	REG_SCRIPT_END
 };
@@ -269,7 +266,8 @@ static inline void gtt_rmw(u32 reg, u32 andmask, u32 ormask)
 }
 
 int gtt_poll(u32 reg, u32 mask, u32 value)
-{	unsigned int try = GT_RETRY;
+{
+	unsigned int try = GTT_RETRY;
 	u32 data;
 
 	while (try--) {
@@ -322,13 +320,16 @@ static void gma_setup_panel(struct device *dev)
 		gtt_write(PCH_PP_DIVISOR, reg32);
 	}
 
-	/* So far all devices seem to use the PCH PWM function.
-	   The CPU PWM registers are all zero after reset.      */
+	/*
+	 * So far all devices seem to use the PCH PWM function.
+	 * The CPU PWM registers are all zero after reset.
+	 */
 	if (panel_cfg->backlight_pwm_hz) {
-		/* For Lynx Point-LP:
-		   Reference clock is 24MHz. We can choose either a 16
-		   or a 128 step increment. Use 16 if we would have less
-		   than 100 steps otherwise. */
+		/*
+		 * For Lynx Point-LP:
+		 * Reference clock is 24MHz. We can choose either a 16 or a 128 step
+		 * increment. Use 16 if we would have less than 100 steps otherwise.
+		 */
 		const unsigned int refclock = 24 * MHz;
 		const unsigned int hz_limit = refclock / 128 / 100;
 		unsigned int pwm_increment, pwm_period;
@@ -350,7 +351,7 @@ static void gma_setup_panel(struct device *dev)
 			refclock / MHz, pwm_increment, pwm_period,
 			DIV_ROUND_CLOSEST(refclock, pwm_increment * pwm_period));
 
-		/* Start with a 50% duty cycle. */
+		/* Start with a 50% duty cycle */
 		gtt_write(BLC_PWM_PCH_CTL2, pwm_period << 16 | pwm_period / 2);
 
 		gtt_write(BLC_PWM_PCH_CTL1,
@@ -382,8 +383,7 @@ static int igd_get_cdclk_haswell(u32 *const cdsel, bool *const inform_pc,
 	 */
 	if (gpu_is_ulx && cdclk <= GT_CDCLK_337)
 		cdclk = GT_CDCLK_337;
-	else if (gpu_is_ulx || cpu_is_ult ||
-			cdclk == GT_CDCLK_337 || cdclk == GT_CDCLK_450)
+	else if (gpu_is_ulx || cpu_is_ult || cdclk == GT_CDCLK_337 || cdclk == GT_CDCLK_450)
 		cdclk = GT_CDCLK_450;
 	else
 		cdclk = GT_CDCLK_540;
@@ -429,8 +429,7 @@ static int igd_get_cdclk_broadwell(u32 *const cdsel, bool *const inform_pc,
 	 */
 	if (cdclk == GT_CDCLK_337)
 		cdclk = GT_CDCLK_337;
-	else if (cdclk == GT_CDCLK_450 ||
-			(gpu_is_ulx && cdclk == GT_CDCLK_DEFAULT))
+	else if (cdclk == GT_CDCLK_450 || (gpu_is_ulx && cdclk == GT_CDCLK_DEFAULT))
 		cdclk = GT_CDCLK_450;
 	else if (cdclk == GT_CDCLK_540 || gpu_is_ulx ||
 			(cpu_is_ult && cdclk == GT_CDCLK_DEFAULT))
@@ -501,7 +500,7 @@ static void igd_cdclk_init(struct device *dev, const bool is_broadwell)
 	gtt_rmw(0x64810, 0xfffff800, dpdiv);
 }
 
-static void igd_init(struct device *dev)
+static void gma_init(struct device *dev)
 {
 	bool is_broadwell = !!(cpu_family_model() == BROADWELL_FAMILY_ULT);
 	u32 rp1_gfx_freq;
@@ -582,11 +581,11 @@ static void gma_generate_ssdt(const struct device *dev)
 	drivers_intel_gma_displays_ssdt_generate(&chip->gfx);
 }
 
-static struct device_operations igd_ops = {
+static struct device_operations gma_ops = {
 	.read_resources		= pci_dev_read_resources,
 	.set_resources		= pci_dev_set_resources,
 	.enable_resources	= pci_dev_enable_resources,
-	.init			= igd_init,
+	.init			= gma_init,
 	.acpi_fill_ssdt		= gma_generate_ssdt,
 	.ops_pci		= &pci_dev_ops_pci,
 };
@@ -606,7 +605,7 @@ static const unsigned short pci_device_ids[] = {
 };
 
 static const struct pci_driver igd_driver __pci_driver = {
-	.ops	 = &igd_ops,
-	.vendor	 = PCI_VID_INTEL,
+	.ops     = &gma_ops,
+	.vendor  = PCI_VID_INTEL,
 	.devices = pci_device_ids,
 };
diff --git a/src/northbridge/intel/broadwell/include/soc/pei_wrapper.h b/src/northbridge/intel/broadwell/include/soc/pei_wrapper.h
index 0b7b85155d..de3a33ffa8 100644
--- a/src/northbridge/intel/broadwell/include/soc/pei_wrapper.h
+++ b/src/northbridge/intel/broadwell/include/soc/pei_wrapper.h
@@ -7,9 +7,8 @@
 
 typedef int ABI_X86(*pei_wrapper_entry_t)(struct pei_data *pei_data);
 
-static inline void pei_data_usb2_port(struct pei_data *pei_data, int port,
-				      uint16_t length, uint8_t enable,
-				      uint8_t oc_pin, uint8_t location)
+static inline void pei_data_usb2_port(struct pei_data *pei_data, int port, uint16_t length,
+				      uint8_t enable, uint8_t oc_pin, uint8_t location)
 {
 	pei_data->usb2_ports[port].length   = length;
 	pei_data->usb2_ports[port].enable   = enable;
@@ -17,9 +16,8 @@ static inline void pei_data_usb2_port(struct pei_data *pei_data, int port,
 	pei_data->usb2_ports[port].location = location;
 }
 
-static inline void pei_data_usb3_port(struct pei_data *pei_data, int port,
-				      uint8_t enable, uint8_t oc_pin,
-				      uint8_t fixed_eq)
+static inline void pei_data_usb3_port(struct pei_data *pei_data, int port, uint8_t enable,
+				      uint8_t oc_pin, uint8_t fixed_eq)
 {
 	pei_data->usb3_ports[port].enable   = enable;
 	pei_data->usb3_ports[port].oc_pin   = oc_pin;
diff --git a/src/northbridge/intel/broadwell/memmap.c b/src/northbridge/intel/broadwell/memmap.c
index 770201baf0..2f1c230b0c 100644
--- a/src/northbridge/intel/broadwell/memmap.c
+++ b/src/northbridge/intel/broadwell/memmap.c
@@ -10,7 +10,7 @@
 #include <device/pci_ops.h>
 #include <soc/pci_devs.h>
 #include <soc/systemagent.h>
-#include <stdint.h>
+#include <types.h>
 
 static uintptr_t dpr_region_start(void)
 {
@@ -52,6 +52,5 @@ void fill_postcar_frame(struct postcar_frame *pcf)
 	 * with different TSEG size configurations.
 	 */
 	const uintptr_t top_of_ram = ALIGN_DOWN(cbmem_top(), 8 * MiB);
-	postcar_frame_add_mtrr(pcf, top_of_ram - 8*MiB, 16*MiB,
-			MTRR_TYPE_WRBACK);
+	postcar_frame_add_mtrr(pcf, top_of_ram - 8 * MiB, 16 * MiB, MTRR_TYPE_WRBACK);
 }
diff --git a/src/northbridge/intel/broadwell/northbridge.c b/src/northbridge/intel/broadwell/northbridge.c
index 771df81044..eec9e325c7 100644
--- a/src/northbridge/intel/broadwell/northbridge.c
+++ b/src/northbridge/intel/broadwell/northbridge.c
@@ -2,18 +2,17 @@
 
 #include <console/console.h>
 #include <cpu/intel/haswell/haswell.h>
-#include <acpi/acpi.h>
-#include <device/pci_ops.h>
-#include <stdint.h>
 #include <delay.h>
 #include <device/device.h>
 #include <device/pci.h>
 #include <device/pci_ids.h>
+#include <device/pci_ops.h>
 #include <soc/acpi.h>
 #include <soc/iomap.h>
 #include <soc/pci_devs.h>
 #include <soc/refcode.h>
 #include <soc/systemagent.h>
+#include <types.h>
 
 u8 systemagent_revision(void)
 {
@@ -21,8 +20,7 @@ u8 systemagent_revision(void)
 	return pci_read_config8(sa_dev, PCI_REVISION_ID);
 }
 
-static int get_pcie_bar(struct device *dev, unsigned int index, u32 *base,
-			u32 *len)
+static int get_pcie_bar(struct device *dev, unsigned int index, u32 *base, u32 *len)
 {
 	u32 pciexbar_reg;
 
@@ -35,20 +33,18 @@ static int get_pcie_bar(struct device *dev, unsigned int index, u32 *base,
 		return 0;
 
 	switch ((pciexbar_reg >> 1) & 3) {
-	case 0: // 256MB
-		*base = pciexbar_reg & ((1 << 31)|(1 << 30)|(1 << 29)|
-					(1 << 28));
-		*len = 256 * 1024 * 1024;
+	case 0: /* 256 MiB */
+		*base = pciexbar_reg & (1 << 31 | 1 << 30 | 1 << 29 | 1 << 28);
+		*len = 256 * MiB;
 		return 1;
-	case 1: // 128M
-		*base = pciexbar_reg & ((1 << 31)|(1 << 30)|(1 << 29)|
-					(1 << 28)|(1 << 27));
-		*len = 128 * 1024 * 1024;
+	case 1: /* 128M */
+		*base = pciexbar_reg & (1 << 31 | 1 << 30 | 1 << 29 | 1 << 28 | 1 << 27);
+		*len = 128 * MiB;
 		return 1;
-	case 2: // 64M
-		*base = pciexbar_reg & ((1 << 31)|(1 << 30)|(1 << 29)|
-					(1 << 28)|(1 << 27)|(1 << 26));
-		*len = 64 * 1024 * 1024;
+	case 2: /* 64M */
+		*base = pciexbar_reg & (1 << 31 | 1 << 30 | 1 << 29 |
+					1 << 28 | 1 << 27 | 1 << 26);
+		*len = 64 * MiB;
 		return 1;
 	}
 
@@ -57,35 +53,31 @@ static int get_pcie_bar(struct device *dev, unsigned int index, u32 *base,
 
 static int get_bar(struct device *dev, unsigned int index, u32 *base, u32 *len)
 {
-	u32 bar;
+	u32 bar = pci_read_config32(dev, index);
 
-	bar = pci_read_config32(dev, index);
-
-	/* If not enabled don't report it. */
+	/* If not enabled don't report it */
 	if (!(bar & 0x1))
 		return 0;
 
-	/* Knock down the enable bit. */
+	/* Knock down the enable bit */
 	*base = bar & ~1;
 
 	return 1;
 }
 
-/* There are special BARs that actually are programmed in the MCHBAR. These
- * Intel special features, but they do consume resources that need to be
- * accounted for. */
-static int get_bar_in_mchbar(struct device *dev, unsigned int index, u32 *base,
-			     u32 *len)
+/*
+ * There are special BARs that actually are programmed in the MCHBAR. These Intel special
+ * features, but they do consume resources that need to be accounted for.
+ */
+static int get_bar_in_mchbar(struct device *dev, unsigned int index, u32 *base, u32 *len)
 {
-	u32 bar;
+	u32 bar = mchbar_read32(index);
 
-	bar = mchbar_read32(index);
-
-	/* If not enabled don't report it. */
+	/* If not enabled don't report it */
 	if (!(bar & 0x1))
 		return 0;
 
-	/* Knock down the enable bit. */
+	/* Knock down the enable bit */
 	*base = bar & ~1;
 
 	return 1;
@@ -94,8 +86,7 @@ static int get_bar_in_mchbar(struct device *dev, unsigned int index, u32 *base,
 struct fixed_mmio_descriptor {
 	unsigned int index;
 	u32 size;
-	int (*get_resource)(struct device *dev, unsigned int index,
-			    u32 *base, u32 *size);
+	int (*get_resource)(struct device *dev, unsigned int index, u32 *base, u32 *size);
 	const char *description;
 };
 
@@ -108,10 +99,7 @@ struct fixed_mmio_descriptor mc_fixed_resources[] = {
 	{ EDRAMBAR, EDRAM_BASE_SIZE, get_bar_in_mchbar, "EDRAMBAR" },
 };
 
-/*
- * Add all known fixed MMIO ranges that hang off the host bridge/memory
- * controller device.
- */
+/* Add all known fixed MMIO ranges that hang off the host bridge/memory controller device. */
 static void mc_add_fixed_mmio_resources(struct device *dev)
 {
 	int i;
@@ -124,23 +112,22 @@ static void mc_add_fixed_mmio_resources(struct device *dev)
 
 		size = mc_fixed_resources[i].size;
 		index = mc_fixed_resources[i].index;
-		if (!mc_fixed_resources[i].get_resource(dev, index,
-							&base, &size))
+		if (!mc_fixed_resources[i].get_resource(dev, index, &base, &size))
 			continue;
 
 		resource = new_resource(dev, mc_fixed_resources[i].index);
 		resource->base = base;
 		resource->size = size;
-		resource->flags = IORESOURCE_MEM | IORESOURCE_FIXED |
-				  IORESOURCE_STORED | IORESOURCE_RESERVE |
-				  IORESOURCE_ASSIGNED;
+		resource->flags = IORESOURCE_MEM | IORESOURCE_FIXED | IORESOURCE_STORED |
+				  IORESOURCE_RESERVE | IORESOURCE_ASSIGNED;
 		printk(BIOS_DEBUG, "%s: Adding %s @ %x 0x%08lx-0x%08lx.\n",
 		       __func__, mc_fixed_resources[i].description, index,
 		       (unsigned long)base, (unsigned long)(base + size - 1));
 	}
 }
 
-/* Host Memory Map:
+/*
+ * Host Memory Map:
  *
  * +--------------------------+ TOUUD
  * |                          |
@@ -153,13 +140,15 @@ static void mc_add_fixed_mmio_resources(struct device *dev)
  * +--------------------------+ BGSM
  * |     TSEG                 |
  * +--------------------------+ TSEGMB
+ * |     DPR                  |
+ * +--------------------------+ (DPR top - DPR size)
  * |     Usage DRAM           |
  * +--------------------------+ 0
  *
- * Some of the base registers above can be equal making the size of those
- * regions 0. The reason is because the memory controller internally subtracts
- * the base registers from each other to determine sizes of the regions. In
- * other words, the memory map is in a fixed order no matter what.
+ * Some of the base registers above can be equal, making the size of the regions within 0.
+ * This is because the memory controller internally subtracts the base registers from each
+ * other to determine sizes of the regions. In other words, the memory map regions are always
+ * in a fixed order, no matter what sizes they have.
  */
 
 struct map_entry {
@@ -169,17 +158,12 @@ struct map_entry {
 	const char *description;
 };
 
-static void read_map_entry(struct device *dev, struct map_entry *entry,
-			   uint64_t *result)
+static void read_map_entry(struct device *dev, struct map_entry *entry, uint64_t *result)
 {
-	uint64_t value;
-	uint64_t mask;
+	/* All registers are on a 1MiB granularity */
+	const uint64_t mask = ~((1ULL << 20) - 1);
 
-	/* All registers are on a 1MiB granularity. */
-	mask = ((1ULL<<20)-1);
-	mask = ~mask;
-
-	value = 0;
+	uint64_t value = 0;
 
 	if (entry->is_64_bit) {
 		value = pci_read_config32(dev, entry->reg + 4);
@@ -203,12 +187,9 @@ static void read_map_entry(struct device *dev, struct map_entry *entry,
 		.description = desc_,  \
 	}
 
-#define MAP_ENTRY_BASE_64(reg_, desc_) \
-	MAP_ENTRY(reg_, 1, 0, desc_)
-#define MAP_ENTRY_LIMIT_64(reg_, desc_) \
-	MAP_ENTRY(reg_, 1, 1, desc_)
-#define MAP_ENTRY_BASE_32(reg_, desc_) \
-	MAP_ENTRY(reg_, 0, 0, desc_)
+#define MAP_ENTRY_BASE_32(reg_, desc_)	MAP_ENTRY(reg_, 0, 0, desc_)
+#define MAP_ENTRY_BASE_64(reg_, desc_)	MAP_ENTRY(reg_, 1, 0, desc_)
+#define MAP_ENTRY_LIMIT_64(reg_, desc_)	MAP_ENTRY(reg_, 1, 1, desc_)
 
 enum {
 	TOM_REG,
@@ -221,59 +202,55 @@ enum {
 	BGSM_REG,
 	BDSM_REG,
 	TSEG_REG,
-	// Must be last.
-	NUM_MAP_ENTRIES
+	/* Must be last */
+	NUM_MAP_ENTRIES,
 };
 
 static struct map_entry memory_map[NUM_MAP_ENTRIES] = {
-	[TOM_REG] = MAP_ENTRY_BASE_64(TOM, "TOM"),
-	[TOUUD_REG] = MAP_ENTRY_BASE_64(TOUUD, "TOUUD"),
-	[MESEG_BASE_REG] = MAP_ENTRY_BASE_64(MESEG_BASE, "MESEG_BASE"),
+	[TOM_REG]         = MAP_ENTRY_BASE_64(TOM, "TOM"),
+	[TOUUD_REG]       = MAP_ENTRY_BASE_64(TOUUD, "TOUUD"),
+	[MESEG_BASE_REG]  = MAP_ENTRY_BASE_64(MESEG_BASE, "MESEG_BASE"),
 	[MESEG_LIMIT_REG] = MAP_ENTRY_LIMIT_64(MESEG_LIMIT, "MESEG_LIMIT"),
-	[REMAP_BASE_REG] = MAP_ENTRY_BASE_64(REMAPBASE, "REMAP_BASE"),
+	[REMAP_BASE_REG]  = MAP_ENTRY_BASE_64(REMAPBASE, "REMAP_BASE"),
 	[REMAP_LIMIT_REG] = MAP_ENTRY_LIMIT_64(REMAPLIMIT, "REMAP_LIMIT"),
-	[TOLUD_REG] = MAP_ENTRY_BASE_32(TOLUD, "TOLUD"),
-	[BDSM_REG] = MAP_ENTRY_BASE_32(BDSM, "BDSM"),
-	[BGSM_REG] = MAP_ENTRY_BASE_32(BGSM, "BGSM"),
-	[TSEG_REG] = MAP_ENTRY_BASE_32(TSEG, "TSEGMB"),
+	[TOLUD_REG]       = MAP_ENTRY_BASE_32(TOLUD, "TOLUD"),
+	[BDSM_REG]        = MAP_ENTRY_BASE_32(BDSM, "BDSM"),
+	[BGSM_REG]        = MAP_ENTRY_BASE_32(BGSM, "BGSM"),
+	[TSEG_REG]        = MAP_ENTRY_BASE_32(TSEG, "TSEGMB"),
 };
 
 static void mc_read_map_entries(struct device *dev, uint64_t *values)
 {
-	int i;
-	for (i = 0; i < NUM_MAP_ENTRIES; i++)
+	for (int i = 0; i < NUM_MAP_ENTRIES; i++)
 		read_map_entry(dev, &memory_map[i], &values[i]);
 }
 
 static void mc_report_map_entries(struct device *dev, uint64_t *values)
 {
-	int i;
-	for (i = 0; i < NUM_MAP_ENTRIES; i++) {
+	for (int i = 0; i < NUM_MAP_ENTRIES; i++) {
 		printk(BIOS_DEBUG, "MC MAP: %s: 0x%llx\n",
 		       memory_map[i].description, values[i]);
 	}
-	/* One can validate the BDSM and BGSM against the GGC. */
+	/* One can validate the BDSM and BGSM against the GGC */
 	printk(BIOS_DEBUG, "MC MAP: GGC: 0x%x\n", pci_read_config16(dev, GGC));
 }
 
 static void mc_add_dram_resources(struct device *dev, int *resource_cnt)
 {
-	unsigned long index;
 	uint64_t mc_values[NUM_MAP_ENTRIES];
-	unsigned long dpr_size = 0;
-	u32 dpr_reg;
 
-	/* Read in the MAP registers and report their values. */
-	mc_read_map_entries(dev, &mc_values[0]);
-	mc_report_map_entries(dev, &mc_values[0]);
+	/* Read in the MAP registers and report their values */
+	mc_read_map_entries(dev, mc_values);
+	mc_report_map_entries(dev, mc_values);
 
 	/*
 	 * DMA Protected Range can be reserved below TSEG for PCODE patch
-	 * or TXT/Boot Guard related data.  Rather than report a base address
+	 * or TXT/Boot Guard related data.  Rather than report a base address,
 	 * the DPR register reports the TOP of the region, which is the same
-	 * as TSEG base.  The region size is reported in MiB in bits 11:4.
+	 * as TSEG base. The region size is reported in MiB in bits 11:4.
 	 */
-	dpr_reg = pci_read_config32(dev, DPR);
+	u32 dpr_reg = pci_read_config32(dev, DPR);
+	unsigned long dpr_size = 0;
 	if (dpr_reg & DPR_EPM) {
 		dpr_size = (dpr_reg & DPR_SIZE_MASK) << 26;
 		printk(BIOS_INFO, "DPR SIZE: 0x%lx\n", dpr_size);
@@ -281,36 +258,31 @@ static void mc_add_dram_resources(struct device *dev, int *resource_cnt)
 
 	/*
 	 * These are the host memory ranges that should be added:
-	 * - 0 -> 0xa0000: cacheable
-	 * - 0xc0000 -> TSEG : cacheable
-	 * - TESG -> BGSM: cacheable with standard MTRRs and reserved
-	 * - BGSM -> TOLUD: not cacheable with standard MTRRs and reserved
-	 * - 4GiB -> TOUUD: cacheable
+	 * - 0 -> 0xa0000:    cacheable
+	 * - 0xc0000 -> TSEG: cacheable
+	 * - TSEG -> BGSM:    cacheable with standard MTRRs and reserved
+	 * - BGSM -> TOLUD:   not cacheable with standard MTRRs and reserved
+	 * - 4GiB -> TOUUD:   cacheable
 	 *
-	 * The default SMRAM space is reserved so that the range doesn't
-	 * have to be saved during S3 Resume. Once marked reserved the OS
-	 * cannot use the memory. This is a bit of an odd place to reserve
-	 * the region, but the CPU devices don't have dev_ops->read_resources()
-	 * called on them.
+	 * The default SMRAM space is reserved so that the range doesn't have to be saved
+	 * during S3 Resume. Once marked reserved the OS cannot use the memory. This is a
+	 * bit of an odd place to reserve the region, but the CPU devices don't have
+	 * dev_ops->read_resources() called on them.
 	 *
-	 * The range 0xa0000 -> 0xc0000 does not have any resources
-	 * associated with it to handle legacy VGA memory. If this range
-	 * is not omitted the mtrr code will setup the area as cacheable
-	 * causing VGA access to not work.
+	 * The range 0xa0000 -> 0xc0000 does not have any resources associated with it to
+	 * handle legacy VGA memory. If this range is not omitted the mtrr code will setup
+	 * the area as cacheable, causing VGA access to not work.
 	 *
-	 * The TSEG region is mapped as cacheable so that one can perform
-	 * SMRAM relocation faster. Once the SMRR is enabled the SMRR takes
-	 * precedence over the existing MTRRs covering this region.
+	 * The TSEG region is mapped as cacheable so that one can perform SMRAM relocation
+	 * faster. Once the SMRR is enabled, the SMRR takes precedence over the existing
+	 * MTRRs covering this region.
 	 *
-	 * It should be noted that cacheable entry types need to be added in
-	 * order. The reason is that the current MTRR code assumes this and
-	 * falls over itself if it isn't.
+	 * It should be noted that cacheable entry types need to be added in order. The reason
+	 * is that the current MTRR code assumes this and falls over itself if it isn't.
 	 *
-	 * The resource index starts low and should not meet or exceed
-	 * PCI_BASE_ADDRESS_0.
+	 * The resource index starts low and should not meet or exceed PCI_BASE_ADDRESS_0.
 	 */
-	index = *resource_cnt;
-
+	unsigned long index = *resource_cnt;
 
 	/*
 	 * 0 - > 0xa0000: RAM
@@ -339,22 +311,21 @@ static void mc_add_dram_resources(struct device *dev, int *resource_cnt)
 static void systemagent_read_resources(struct device *dev)
 {
 	int index = 0;
-	const bool vtd_capable =
-		!(pci_read_config32(dev, CAPID0_A) & VTD_DISABLE);
+	const bool vtd_capable = !(pci_read_config32(dev, CAPID0_A) & VTD_DISABLE);
 
-	/* Read standard PCI resources. */
+	/* Read standard PCI resources */
 	pci_dev_read_resources(dev);
 
-	/* Add all fixed MMIO resources. */
+	/* Add all fixed MMIO resources */
 	mc_add_fixed_mmio_resources(dev);
 
-	/* Add VT-d MMIO resources if capable */
+	/* Add VT-d MMIO resources, if capable */
 	if (vtd_capable) {
 		mmio_range(dev, index++, GFXVT_BASE_ADDRESS, GFXVT_BASE_SIZE);
 		mmio_range(dev, index++, VTVC0_BASE_ADDRESS, VTVC0_BASE_SIZE);
 	}
 
-	/* Calculate and add DRAM resources. */
+	/* Calculate and add DRAM resources */
 	mc_add_dram_resources(dev, &index);
 }
 
@@ -364,8 +335,8 @@ static void systemagent_init(struct device *dev)
 	mchbar_clrsetbits8(MCH_PAIR, 0x7, 0x4);	/* Clear 2:0, set Fixed Priority */
 
 	/*
-	 * Set bits 0+1 of BIOS_RESET_CPL to indicate to the CPU
-	 * that BIOS has initialized memory and power management
+	 * Set bits 0 + 1 of BIOS_RESET_CPL to indicate to the CPU
+	 * that BIOS has initialized memory and power management.
 	 */
 	mchbar_setbits8(BIOS_RESET_CPL, 3);
 	printk(BIOS_DEBUG, "Set BIOS_RESET_CPL\n");
@@ -398,11 +369,11 @@ static const struct pci_driver systemagent_driver __pci_driver = {
 };
 
 struct device_operations broadwell_pci_domain_ops = {
-	.read_resources    = &pci_domain_read_resources,
-	.set_resources     = &pci_domain_set_resources,
-	.scan_bus          = &pci_host_bridge_scan_bus,
+	.read_resources    = pci_domain_read_resources,
+	.set_resources     = pci_domain_set_resources,
+	.scan_bus          = pci_host_bridge_scan_bus,
 #if CONFIG(HAVE_ACPI_TABLES)
-	.write_acpi_tables = &northbridge_write_acpi_tables,
+	.write_acpi_tables = northbridge_write_acpi_tables,
 #endif
 };
 
@@ -413,5 +384,5 @@ static void broadwell_init_pre_device(void *chip_info)
 
 struct chip_operations northbridge_intel_broadwell_ops = {
 	.name = "Intel Broadwell",
-	.init       = &broadwell_init_pre_device,
+	.init = broadwell_init_pre_device,
 };
diff --git a/src/northbridge/intel/broadwell/pei_data.c b/src/northbridge/intel/broadwell/pei_data.c
index 28adb30e15..fe2002fb1f 100644
--- a/src/northbridge/intel/broadwell/pei_data.c
+++ b/src/northbridge/intel/broadwell/pei_data.c
@@ -2,10 +2,10 @@
 
 #include <console/streams.h>
 #include <device/device.h>
+#include <northbridge/intel/broadwell/chip.h>
 #include <soc/iomap.h>
 #include <soc/pei_data.h>
 #include <soc/pei_wrapper.h>
-#include <northbridge/intel/broadwell/chip.h>
 #include <static.h>
 
 static void ABI_X86 send_to_console(unsigned char b)
diff --git a/src/northbridge/intel/broadwell/raminit.c b/src/northbridge/intel/broadwell/raminit.c
index 9dc7973ec1..d8ed97fdd1 100644
--- a/src/northbridge/intel/broadwell/raminit.c
+++ b/src/northbridge/intel/broadwell/raminit.c
@@ -9,7 +9,6 @@
 #include <memory_info.h>
 #include <mrc_cache.h>
 #include <string.h>
-#include <soc/iomap.h>
 #include <soc/pei_data.h>
 #include <soc/pei_wrapper.h>
 #include <soc/pm.h>
@@ -84,25 +83,19 @@ static void report_memory_config(void)
  */
 static void sdram_initialize(struct pei_data *pei_data)
 {
-	size_t mrc_size;
-	pei_wrapper_entry_t entry;
-	int ret;
-
 	broadwell_fill_pei_data(pei_data);
 
 	/* Assume boot device is memory mapped. */
 	assert(CONFIG(BOOT_DEVICE_MEMORY_MAPPED));
 
-	pei_data->saved_data =
-		mrc_cache_current_mmap_leak(MRC_TRAINING_DATA, 0,
-					    &mrc_size);
+	size_t mrc_size;
+	pei_data->saved_data = mrc_cache_current_mmap_leak(MRC_TRAINING_DATA, 0, &mrc_size);
 	if (pei_data->saved_data) {
 		/* MRC cache found */
 		pei_data->saved_data_size = mrc_size;
 	} else if (pei_data->boot_mode == ACPI_S3) {
 		/* Waking from S3 and no cache. */
-		printk(BIOS_DEBUG,
-		       "No MRC cache found in S3 resume path.\n");
+		printk(BIOS_DEBUG, "No MRC cache found in S3 resume path.\n");
 		post_code(POSTCODE_RESUME_FAILURE);
 		system_reset();
 	} else {
@@ -110,7 +103,7 @@ static void sdram_initialize(struct pei_data *pei_data)
 	}
 
 	/*
-	 * Do not use saved pei data.  Can be set by mainboard romstage
+	 * Do not use saved pei data. Can be set by mainboard romstage
 	 * to force a full train of memory on every boot.
 	 */
 	if (pei_data->disable_saved_data) {
@@ -120,13 +113,13 @@ static void sdram_initialize(struct pei_data *pei_data)
 	}
 
 	/* We don't care about leaking the mapping */
-	entry = cbfs_ro_map("mrc.bin", NULL);
+	pei_wrapper_entry_t entry = cbfs_ro_map("mrc.bin", NULL);
 	if (entry == NULL)
 		die("mrc.bin not found!");
 
 	printk(BIOS_DEBUG, "Starting Memory Reference Code\n");
 
-	ret = entry(pei_data);
+	int ret = entry(pei_data);
 	if (ret < 0)
 		die("pei_data version mismatch\n");
 
@@ -141,10 +134,8 @@ static void sdram_initialize(struct pei_data *pei_data)
 
 static void setup_sdram_meminfo(struct pei_data *pei_data)
 {
-	struct memory_info *mem_info;
-
 	printk(BIOS_DEBUG, "create cbmem for dimm information\n");
-	mem_info = cbmem_add(CBMEM_ID_MEMINFO, sizeof(struct memory_info));
+	struct memory_info *mem_info = cbmem_add(CBMEM_ID_MEMINFO, sizeof(*mem_info));
 
 	if (!mem_info) {
 		printk(BIOS_ERR, "Error! Failed to add mem_info to cbmem\n");
@@ -156,8 +147,7 @@ static void setup_sdram_meminfo(struct pei_data *pei_data)
 	mem_info->dimm_cnt = pei_data->meminfo.dimm_cnt;
 	for (int i = 0; i < MIN(DIMM_INFO_TOTAL, PEI_DIMM_INFO_TOTAL); i++) {
 		struct dimm_info *dimm = &mem_info->dimm[i];
-		const struct pei_dimm_info *pei_dimm =
-			&pei_data->meminfo.dimm[i];
+		const struct pei_dimm_info *pei_dimm = &pei_data->meminfo.dimm[i];
 		dimm->dimm_size = pei_dimm->dimm_size;
 		dimm->ddr_type = pei_dimm->ddr_type;
 		dimm->ddr_frequency = pei_dimm->ddr_frequency;
@@ -167,8 +157,7 @@ static void setup_sdram_meminfo(struct pei_data *pei_data)
 		dimm->bank_locator = pei_dimm->bank_locator;
 		memcpy(&dimm->serial, &pei_dimm->serial,
 			MIN(sizeof(dimm->serial), sizeof(pei_dimm->serial)));
-		memcpy(&dimm->module_part_number,
-			&pei_dimm->module_part_number,
+		memcpy(&dimm->module_part_number, &pei_dimm->module_part_number,
 			MIN(sizeof(dimm->module_part_number),
 			sizeof(pei_dimm->module_part_number)));
 		dimm->module_part_number[DIMM_INFO_PART_NUMBER_SIZE - 1] = '\0';
diff --git a/src/northbridge/intel/broadwell/refcode.c b/src/northbridge/intel/broadwell/refcode.c
index ee54f19cbf..0497aa9bb4 100644
--- a/src/northbridge/intel/broadwell/refcode.c
+++ b/src/northbridge/intel/broadwell/refcode.c
@@ -21,8 +21,7 @@ static pei_wrapper_entry_t load_reference_code(void)
 		return prog_entry(&prog);
 	}
 
-	struct prog prog =
-		PROG_INIT(PROG_REFCODE, CONFIG_CBFS_PREFIX "/refcode");
+	struct prog prog = PROG_INIT(PROG_REFCODE, CONFIG_CBFS_PREFIX "/refcode");
 	struct rmod_stage_load refcode = {
 		.cbmem_id = CBMEM_ID_REFCODE,
 		.prog = &prog,
@@ -41,9 +40,8 @@ static pei_wrapper_entry_t load_reference_code(void)
 
 void broadwell_run_reference_code(void)
 {
-	int ret, dummy;
+	int dummy;
 	struct pei_data pei_data;
-	pei_wrapper_entry_t entry;
 
 	memset(&pei_data, 0, sizeof(pei_data));
 	mainboard_fill_pei_data(&pei_data);
@@ -52,14 +50,14 @@ void broadwell_run_reference_code(void)
 	pei_data.boot_mode = acpi_is_wakeup_s3() ? ACPI_S3 : 0;
 	pei_data.saved_data = (void *)&dummy;
 
-	entry = load_reference_code();
+	pei_wrapper_entry_t entry = load_reference_code();
 	if (entry == NULL) {
 		printk(BIOS_ERR, "Reference code not found\n");
 		return;
 	}
 
 	/* Call into reference code. */
-	ret = entry(&pei_data);
+	int ret = entry(&pei_data);
 	if (ret != 0) {
 		printk(BIOS_ERR, "Reference code returned %d\n", ret);
 		return;
diff --git a/src/northbridge/intel/broadwell/report_platform.c b/src/northbridge/intel/broadwell/report_platform.c
index 5dbe196633..d64d53e9ae 100644
--- a/src/northbridge/intel/broadwell/report_platform.c
+++ b/src/northbridge/intel/broadwell/report_platform.c
@@ -74,20 +74,19 @@ static struct {
 
 static void report_cpu_info(void)
 {
-	struct cpuid_result cpuidr;
-	u32 i, index, cpu_id, cpu_feature_flag;
-	char cpu_string[50], *cpu_name = cpu_string; /* 48 bytes are reported */
-	int vt, txt, aes;
 	const char *mode[] = {"NOT ", ""};
 	const char *cpu_type = "Unknown";
 
-	index = 0x80000000;
-	cpuidr = cpuid(index);
+	char cpu_string[50];
+	char *cpu_name = cpu_string; /* 48 bytes are reported */
+
+	const u32 index = 0x80000000;
+	struct cpuid_result cpuidr = cpuid(index);
 	if (cpuidr.eax < 0x80000004) {
 		strcpy(cpu_string, "Platform info not available");
 	} else {
 		u32 *p = (u32 *)cpu_string;
-		for (i = 2; i <= 4 ; i++) {
+		for (unsigned int i = 2; i <= 4; i++) {
 			cpuidr = cpuid(index + i);
 			*p++ = cpuidr.eax;
 			*p++ = cpuidr.ebx;
@@ -99,10 +98,10 @@ static void report_cpu_info(void)
 	while (cpu_name[0] == ' ')
 		cpu_name++;
 
-	cpu_id = cpu_get_cpuid();
+	const u32 cpu_id = cpu_get_cpuid();
 
 	/* Look for string to match the name */
-	for (i = 0; i < ARRAY_SIZE(cpu_table); i++) {
+	for (unsigned int i = 0; i < ARRAY_SIZE(cpu_table); i++) {
 		if (cpu_table[i].cpuid == cpu_id) {
 			cpu_type = cpu_table[i].name;
 			break;
@@ -113,24 +112,23 @@ static void report_cpu_info(void)
 	printk(BIOS_DEBUG, "CPU: ID %x, %s, ucode: %08x\n",
 	       cpu_id, cpu_type, get_current_microcode_rev());
 
-	cpu_feature_flag = cpu_get_feature_flags_ecx();
-	aes = (cpu_feature_flag & CPUID_AES) ? 1 : 0;
-	txt = (cpu_feature_flag & CPUID_SMX) ? 1 : 0;
-	vt = (cpu_feature_flag & CPUID_VMX) ? 1 : 0;
-	printk(BIOS_DEBUG, "CPU: AES %ssupported, TXT %ssupported, "
-	       "VT %ssupported\n", mode[aes], mode[txt], mode[vt]);
+	const u32 cpu_feature_flag = cpu_get_feature_flags_ecx();
+	const bool aes = (cpu_feature_flag & CPUID_AES);
+	const bool txt = (cpu_feature_flag & CPUID_SMX);
+	const bool vt  = (cpu_feature_flag & CPUID_VMX);
+	printk(BIOS_DEBUG, "CPU: AES %ssupported, TXT %ssupported, VT %ssupported\n",
+	       mode[aes], mode[txt], mode[vt]);
 }
 
 static void report_mch_info(void)
 {
-	int i;
-	u16 mch_device = pci_read_config16(HOST_BRIDGE, PCI_DEVICE_ID);
-	u8 mch_revision = pci_read_config8(HOST_BRIDGE, PCI_REVISION_ID);
+	const u16 mch_device = pci_read_config16(HOST_BRIDGE, PCI_DEVICE_ID);
+	const u8 mch_revision = pci_read_config8(HOST_BRIDGE, PCI_REVISION_ID);
 	const char *mch_type = "Unknown";
 
 	/* Look for string to match the revision for Broadwell U/Y */
 	if (mch_device == MCH_BROADWELL_ID_U_Y) {
-		for (i = 0; i < ARRAY_SIZE(mch_rev_table); i++) {
+		for (unsigned int i = 0; i < ARRAY_SIZE(mch_rev_table); i++) {
 			if (mch_rev_table[i].revid == mch_revision) {
 				mch_type = mch_rev_table[i].name;
 				break;
@@ -144,11 +142,10 @@ static void report_mch_info(void)
 
 static void report_pch_info(void)
 {
-	int i;
-	u16 lpcid = pch_type();
+	const u16 lpcid = pch_type();
 	const char *pch_type = "Unknown";
 
-	for (i = 0; i < ARRAY_SIZE(pch_table); i++) {
+	for (unsigned int i = 0; i < ARRAY_SIZE(pch_table); i++) {
 		if (pch_table[i].lpcid == lpcid) {
 			pch_type = pch_table[i].name;
 			break;
@@ -160,11 +157,10 @@ static void report_pch_info(void)
 
 static void report_igd_info(void)
 {
-	int i;
-	u16 igdid = pci_read_config16(SA_DEV_IGD, PCI_DEVICE_ID);
+	const u16 igdid = pci_read_config16(SA_DEV_IGD, PCI_DEVICE_ID);
 	const char *igd_type = "Unknown";
 
-	for (i = 0; i < ARRAY_SIZE(igd_table); i++) {
+	for (unsigned int i = 0; i < ARRAY_SIZE(igd_table); i++) {
 		if (igd_table[i].igdid == igdid) {
 			igd_type = igd_table[i].name;
 			break;
diff --git a/src/northbridge/intel/broadwell/romstage.c b/src/northbridge/intel/broadwell/romstage.c
index 4e2cb6a403..2f42fd0159 100644
--- a/src/northbridge/intel/broadwell/romstage.c
+++ b/src/northbridge/intel/broadwell/romstage.c
@@ -1,6 +1,5 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
-#include <acpi/acpi.h>
 #include <arch/romstage.h>
 #include <console/console.h>
 #include <cpu/intel/haswell/haswell.h>
@@ -47,8 +46,7 @@ void mainboard_romstage_entry(void)
 	intel_me_status();
 
 	/* Save ME HSIO version */
-	intel_me_hsio_version(&power_state->hsio_version,
-			      &power_state->hsio_checksum);
+	intel_me_hsio_version(&power_state->hsio_version, &power_state->hsio_checksum);
 
 	perform_raminit(power_state);
 
diff --git a/src/northbridge/intel/broadwell/spd.c b/src/northbridge/intel/broadwell/spd.c
index 419334db70..d4195df354 100644
--- a/src/northbridge/intel/broadwell/spd.c
+++ b/src/northbridge/intel/broadwell/spd.c
@@ -52,10 +52,9 @@ static void print_spd_info(uint8_t spd[])
 	spd_name[SPD_DDR3_PART_LEN] = 0;
 	printk(BIOS_INFO, "SPD: module part is %s\n", spd_name);
 
-	printk(BIOS_INFO, "SPD: banks %d, ranks %d, rows %d, columns %d, "
-	       "density %d Mb\n", banks, ranks, rows, cols, capmb);
-	printk(BIOS_INFO, "SPD: device width %d bits, bus width %d bits\n",
-	       devw, busw);
+	printk(BIOS_INFO, "SPD: banks %d, ranks %d, rows %d, columns %d, density %d Mb\n",
+	       banks, ranks, rows, cols, capmb);
+	printk(BIOS_INFO, "SPD: device width %d bits, bus width %d bits\n", devw, busw);
 
 	if (capmb > 0 && busw > 0 && devw > 0 && ranks > 0) {
 		/* SIZE = DENSITY / 8 * BUS_WIDTH / SDRAM_WIDTH * RANKS */

From 342d77a0dd3a12372be16bdb1fd177820d19352c Mon Sep 17 00:00:00 2001
From: Angel Pons <th3fanbus@gmail.com>
Date: Mon, 9 Mar 2026 16:34:43 +0100
Subject: [PATCH 3701/3886] nb/intel/broadwell: Rename `MCH_PAIR` to
 `INTRDIRCTL`

The register at MCHBAR offset 0x5418 is named `INTRDIRCTL` on Haswell,
as well as earlier platforms. Sync the Haswell and Broadwell codebases
by renaming `MCH_PAIR` to `INTRDIRCTL` on Broadwell.

Tested with BUILD_TIMELESS=1, Purism Librem 15 v2 remains identical.

Change-Id: I0b37927ebec634b6e48623f75789723cf518c3ef
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91621
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
---
 src/northbridge/intel/broadwell/include/soc/systemagent.h | 2 +-
 src/northbridge/intel/broadwell/northbridge.c             | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/northbridge/intel/broadwell/include/soc/systemagent.h b/src/northbridge/intel/broadwell/include/soc/systemagent.h
index 0230f5f4e5..afdf1a9f6f 100644
--- a/src/northbridge/intel/broadwell/include/soc/systemagent.h
+++ b/src/northbridge/intel/broadwell/include/soc/systemagent.h
@@ -95,7 +95,7 @@
 #define GFXVTBAR		0x5400
 #define EDRAMBAR		0x5408
 #define VTVC0BAR		0x5410
-#define MCH_PAIR		0x5418
+#define INTRDIRCTL		0x5418
 #define GDXCBAR			0x5420
 
 #define MCH_DDR_POWER_LIMIT_LO	0x58e0
diff --git a/src/northbridge/intel/broadwell/northbridge.c b/src/northbridge/intel/broadwell/northbridge.c
index eec9e325c7..bb45c374a8 100644
--- a/src/northbridge/intel/broadwell/northbridge.c
+++ b/src/northbridge/intel/broadwell/northbridge.c
@@ -332,7 +332,7 @@ static void systemagent_read_resources(struct device *dev)
 static void systemagent_init(struct device *dev)
 {
 	/* Enable Power Aware Interrupt Routing. */
-	mchbar_clrsetbits8(MCH_PAIR, 0x7, 0x4);	/* Clear 2:0, set Fixed Priority */
+	mchbar_clrsetbits8(INTRDIRCTL, 0x7, 0x4);	/* Clear 2:0, set Fixed Priority */
 
 	/*
 	 * Set bits 0 + 1 of BIOS_RESET_CPL to indicate to the CPU

From 4ea3450e450a1a2a7db4838dbc7d75ca9c6c0fe8 Mon Sep 17 00:00:00 2001
From: Angel Pons <th3fanbus@gmail.com>
Date: Mon, 9 Mar 2026 17:00:48 +0100
Subject: [PATCH 3702/3886] nb/intel/broadwell: Use registers from Haswell

Tested with BUILD_TIMELESS=1, Purism Librem 15 v2 remains identical.

Change-Id: I7d08231b844428390734bd779b19d80e61a66efd
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91622
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
---
 .../intel/broadwell/include/soc/systemagent.h | 104 +-----------------
 1 file changed, 2 insertions(+), 102 deletions(-)

diff --git a/src/northbridge/intel/broadwell/include/soc/systemagent.h b/src/northbridge/intel/broadwell/include/soc/systemagent.h
index afdf1a9f6f..5cb8eea393 100644
--- a/src/northbridge/intel/broadwell/include/soc/systemagent.h
+++ b/src/northbridge/intel/broadwell/include/soc/systemagent.h
@@ -3,8 +3,6 @@
 #ifndef _BROADWELL_SYSTEMAGENT_H_
 #define _BROADWELL_SYSTEMAGENT_H_
 
-#include <soc/iomap.h>
-
 #define SA_IGD_OPROM_VENDEV	0x80860406
 
 #define IGD_HASWELL_ULT_GT1	0x0a06
@@ -25,112 +23,14 @@
 #define MCH_BROADWELL_REV_E0	0x08
 #define MCH_BROADWELL_REV_F0	0x09
 
-/* Device 0:0.0 PCI configuration space */
-
-#define EPBAR		0x40
-#define MCHBAR		0x48
-#define GGC		0x50	/* GMCH Graphics Control */
-#define DEVEN		0x54	/* Device Enable */
-#define  DEVEN_D7EN	(1 << 14)
-#define  DEVEN_D4EN	(1 << 7)
-#define  DEVEN_D3EN	(1 << 5)
-#define  DEVEN_D2EN	(1 << 4)
-#define  DEVEN_D1F0EN	(1 << 3)
-#define  DEVEN_D1F1EN	(1 << 2)
-#define  DEVEN_D1F2EN	(1 << 1)
-#define  DEVEN_D0EN	(1 << 0)
-#define DPR		0x5c
-#define  DPR_EPM	(1 << 2)
-#define  DPR_PRS	(1 << 1)
-#define  DPR_SIZE_MASK	0xff0
-#define PCIEXBAR	0x60
-#define DMIBAR		0x68
-
-#define MESEG_BASE	0x70	/* Management Engine Base. */
-#define MESEG_LIMIT	0x78	/* Management Engine Limit. */
-
-#define PAM0		0x80
-#define PAM1		0x81
-#define PAM2		0x82
-#define PAM3		0x83
-#define PAM4		0x84
-#define PAM5		0x85
-#define PAM6		0x86
-
-#define SMRAM		0x88	/* System Management RAM Control */
-#define  D_OPEN		(1 << 6)
-#define  D_CLS		(1 << 5)
-#define  D_LCK		(1 << 4)
-#define  G_SMRAME	(1 << 3)
-#define  C_BASE_SEG	((0 << 2) | (1 << 1) | (0 << 0))
-
-#define REMAPBASE	0x90	/* Remap base. */
-#define REMAPLIMIT	0x98	/* Remap limit. */
-#define TOM		0xa0	/* Top of DRAM in memory controller space. */
-#define TOUUD		0xa8	/* Top of Upper Usable DRAM */
-#define BDSM		0xb0	/* Base Data Stolen Memory */
-#define BGSM		0xb4	/* Base GTT Stolen Memory */
-#define TSEG		0xb8	/* TSEG base */
-#define TOLUD		0xbc	/* Top of Low Used Memory */
-#define SKPAD		0xdc	/* Scratchpad Data */
-
-#define CAPID0_A	0xe4
-#define  VTD_DISABLE	(1 << 23)
+#include <northbridge/intel/haswell/registers/host_bridge.h>
 
 #define ARCHDIS		0xff0	/* DMA Remap Engine Policy Control */
 #define  DMAR_LCKDN	(1 << 31)
 #define  PRSCAPDIS	(1 << 2)
 
-/* MCHBAR */
 #include <northbridge/intel/common/fixed_bars.h>
-
-/* Memory controller characteristics */
-#define NUM_CHANNELS	2
-
-#define MAD_CHNL		0x5000
-#define MAD_DIMM(ch)		(0x5004 + 4 * (ch))
-
-#define MRC_REVISION		0x5034
-
-#define GFXVTBAR		0x5400
-#define EDRAMBAR		0x5408
-#define VTVC0BAR		0x5410
-#define INTRDIRCTL		0x5418
-#define GDXCBAR			0x5420
-
-#define MCH_DDR_POWER_LIMIT_LO	0x58e0
-#define MCH_DDR_POWER_LIMIT_HI	0x58e4
-
-#define MCH_PKG_POWER_LIMIT_LO	0x59a0
-#define MCH_PKG_POWER_LIMIT_HI	0x59a4
-
-/* PCODE MMIO communications live in the MCHBAR */
-#define BIOS_MAILBOX_DATA	0x5da0
-
-#define BIOS_MAILBOX_INTERFACE	0x5da4
-#define  MAILBOX_RUN_BUSY			(1 << 31)
-#define  MAILBOX_BIOS_CMD_READ_PCS		1
-#define  MAILBOX_BIOS_CMD_WRITE_PCS		2
-#define  MAILBOX_BIOS_CMD_READ_CALIBRATION	0x509
-#define  MAILBOX_BIOS_CMD_FSM_MEASURE_INTVL	0x909
-#define  MAILBOX_BIOS_CMD_READ_PCH_POWER	0xa
-#define  MAILBOX_BIOS_CMD_READ_PCH_POWER_EXT	0xb
-#define  MAILBOX_BIOS_CMD_READ_C9C10_VOLTAGE	0x26
-#define  MAILBOX_BIOS_CMD_WRITE_C9C10_VOLTAGE	0x27
-
-/* Errors are returned back in bits 7:0 */
-#define  MAILBOX_BIOS_ERROR_NONE		0
-#define  MAILBOX_BIOS_ERROR_INVALID_COMMAND	1
-#define  MAILBOX_BIOS_ERROR_TIMEOUT		2
-#define  MAILBOX_BIOS_ERROR_ILLEGAL_DATA	3
-#define  MAILBOX_BIOS_ERROR_RESERVED		4
-#define  MAILBOX_BIOS_ERROR_ILLEGAL_VR_ID	5
-#define  MAILBOX_BIOS_ERROR_VR_INTERFACE_LOCKED	6
-#define  MAILBOX_BIOS_ERROR_VR_ERROR		7
-
-#define BIOS_RESET_CPL		0x5da8
-
-#define MC_BIOS_DATA		0x5e04
+#include <northbridge/intel/haswell/registers/mchbar.h>
 
 /* System Agent identification */
 u8 systemagent_revision(void);

From 7c35218c8853ee07ac7334b1e83e83c72a7c67a8 Mon Sep 17 00:00:00 2001
From: Angel Pons <th3fanbus@gmail.com>
Date: Mon, 9 Mar 2026 17:49:33 +0100
Subject: [PATCH 3703/3886] nb/intel/broadwell/report_platform.c: Constify
 string array

Checkpatch suggests these changes when touching this code.

Change-Id: Ib85f4ca43b92a160519bd9e600054accaccc0e94
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91623
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
---
 src/northbridge/intel/broadwell/report_platform.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/northbridge/intel/broadwell/report_platform.c b/src/northbridge/intel/broadwell/report_platform.c
index d64d53e9ae..2f5293a3e2 100644
--- a/src/northbridge/intel/broadwell/report_platform.c
+++ b/src/northbridge/intel/broadwell/report_platform.c
@@ -74,7 +74,7 @@ static struct {
 
 static void report_cpu_info(void)
 {
-	const char *mode[] = {"NOT ", ""};
+	static const char *const mode[] = {"NOT ", ""};
 	const char *cpu_type = "Unknown";
 
 	char cpu_string[50];

From 96ab0c994252c8cbd02a1844a6cab3c0c266304a Mon Sep 17 00:00:00 2001
From: Angel Pons <th3fanbus@gmail.com>
Date: Mon, 9 Mar 2026 17:51:50 +0100
Subject: [PATCH 3704/3886] nb/intel/broadwell: Move `report_cpu_info()` to CPU
 code

This function prints CPU information, so it makes sense for it to be
part of CPU code. Subsequent commits will update the CPUID table and
make the Haswell northbridge code also use it.

For now, rename the static function in `nb/intel/haswell` to avoid a
name clash. It will be dropped in a follow-up anyway.

Change-Id: I6b26fddd4e899b692f4122921db1c70f4b16b4f2
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91624
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/cpu/intel/haswell/Makefile.mk             |  1 +
 src/cpu/intel/haswell/haswell.h               |  3 +
 src/cpu/intel/haswell/report_cpu_info.c       | 73 +++++++++++++++++++
 .../intel/broadwell/report_platform.c         | 67 -----------------
 .../intel/haswell/report_platform.c           |  4 +-
 5 files changed, 79 insertions(+), 69 deletions(-)
 create mode 100644 src/cpu/intel/haswell/report_cpu_info.c

diff --git a/src/cpu/intel/haswell/Makefile.mk b/src/cpu/intel/haswell/Makefile.mk
index 41ca9c9d98..65e411df63 100644
--- a/src/cpu/intel/haswell/Makefile.mk
+++ b/src/cpu/intel/haswell/Makefile.mk
@@ -6,6 +6,7 @@ bootblock-y += ../car/bootblock.c
 bootblock-y += ../../x86/early_reset.S
 
 romstage-y += pcode_mailbox.c
+romstage-y += report_cpu_info.c
 romstage-y += romstage.c
 romstage-y += ../car/romstage.c
 
diff --git a/src/cpu/intel/haswell/haswell.h b/src/cpu/intel/haswell/haswell.h
index d24cbe1975..0a64149f28 100644
--- a/src/cpu/intel/haswell/haswell.h
+++ b/src/cpu/intel/haswell/haswell.h
@@ -172,6 +172,9 @@ int pcode_ready(void);
 u32 pcode_mailbox_read(u32 command);
 int pcode_mailbox_write(u32 command, u32 data);
 
+/* report_cpu_info.c */
+void report_cpu_info(void);
+
 /* CPU identification */
 static inline u32 cpu_family_model(void)
 {
diff --git a/src/cpu/intel/haswell/report_cpu_info.c b/src/cpu/intel/haswell/report_cpu_info.c
new file mode 100644
index 0000000000..9f93cd7002
--- /dev/null
+++ b/src/cpu/intel/haswell/report_cpu_info.c
@@ -0,0 +1,73 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <console/console.h>
+#include <cpu/cpu.h>
+#include <cpu/intel/haswell/haswell.h>
+#include <cpu/intel/microcode.h>
+#include <cpu/x86/msr.h>
+#include <string.h>
+#include <types.h>
+
+/* FIXME: Needs an update */
+static struct {
+	u32 cpuid;
+	const char *name;
+} cpu_table[] = {
+	{ CPUID_HASWELL_A0,       "Haswell A0" },
+	{ CPUID_HASWELL_B0,       "Haswell B0" },
+	{ CPUID_HASWELL_C0,       "Haswell C0" },
+	{ CPUID_HASWELL_ULT_B0,   "Haswell ULT B0" },
+	{ CPUID_HASWELL_ULT_C0,   "Haswell ULT C0 or D0" },
+	{ CPUID_CRYSTALWELL_C0,   "Haswell Perf Halo" },
+	{ CPUID_BROADWELL_ULT_C0, "Broadwell C0" },
+	{ CPUID_BROADWELL_ULT_D0, "Broadwell D0" },
+	{ CPUID_BROADWELL_ULT_E0, "Broadwell E0 or F0" },
+};
+
+void report_cpu_info(void)
+{
+	static const char *const mode[] = {"NOT ", ""};
+	const char *cpu_type = "Unknown";
+
+	char cpu_string[50];
+	char *cpu_name = cpu_string; /* 48 bytes are reported */
+
+	const u32 index = 0x80000000;
+	struct cpuid_result cpuidr = cpuid(index);
+	if (cpuidr.eax < 0x80000004) {
+		strcpy(cpu_string, "Platform info not available");
+	} else {
+		u32 *p = (u32 *)cpu_string;
+		for (unsigned int i = 2; i <= 4; i++) {
+			cpuidr = cpuid(index + i);
+			*p++ = cpuidr.eax;
+			*p++ = cpuidr.ebx;
+			*p++ = cpuidr.ecx;
+			*p++ = cpuidr.edx;
+		}
+	}
+	/* Skip leading spaces in CPU name string */
+	while (cpu_name[0] == ' ')
+		cpu_name++;
+
+	const u32 cpu_id = cpu_get_cpuid();
+
+	/* Look for string to match the name */
+	for (unsigned int i = 0; i < ARRAY_SIZE(cpu_table); i++) {
+		if (cpu_table[i].cpuid == cpu_id) {
+			cpu_type = cpu_table[i].name;
+			break;
+		}
+	}
+
+	printk(BIOS_DEBUG, "CPU: %s\n", cpu_name);
+	printk(BIOS_DEBUG, "CPU: ID %x, %s, ucode: %08x\n",
+	       cpu_id, cpu_type, get_current_microcode_rev());
+
+	const u32 cpu_feature_flag = cpu_get_feature_flags_ecx();
+	const bool aes = (cpu_feature_flag & CPUID_AES);
+	const bool txt = (cpu_feature_flag & CPUID_SMX);
+	const bool vt  = (cpu_feature_flag & CPUID_VMX);
+	printk(BIOS_DEBUG, "CPU: AES %ssupported, TXT %ssupported, VT %ssupported\n",
+	       mode[aes], mode[txt], mode[vt]);
+}
diff --git a/src/northbridge/intel/broadwell/report_platform.c b/src/northbridge/intel/broadwell/report_platform.c
index 2f5293a3e2..311ab35081 100644
--- a/src/northbridge/intel/broadwell/report_platform.c
+++ b/src/northbridge/intel/broadwell/report_platform.c
@@ -1,10 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
 #include <console/console.h>
-#include <cpu/cpu.h>
 #include <cpu/intel/haswell/haswell.h>
-#include <cpu/intel/microcode.h>
-#include <cpu/x86/msr.h>
 #include <device/pci.h>
 #include <device/pci_ops.h>
 #include <soc/pch.h>
@@ -13,22 +10,6 @@
 #include <soc/systemagent.h>
 #include <string.h>
 
-/* FIXME: Needs an update */
-static struct {
-	u32 cpuid;
-	const char *name;
-} cpu_table[] = {
-	{ CPUID_HASWELL_A0,       "Haswell A0" },
-	{ CPUID_HASWELL_B0,       "Haswell B0" },
-	{ CPUID_HASWELL_C0,       "Haswell C0" },
-	{ CPUID_HASWELL_ULT_B0,   "Haswell ULT B0" },
-	{ CPUID_HASWELL_ULT_C0,   "Haswell ULT C0 or D0" },
-	{ CPUID_CRYSTALWELL_C0,   "Haswell Perf Halo" },
-	{ CPUID_BROADWELL_ULT_C0, "Broadwell C0" },
-	{ CPUID_BROADWELL_ULT_D0, "Broadwell D0" },
-	{ CPUID_BROADWELL_ULT_E0, "Broadwell E0 or F0" },
-};
-
 static struct {
 	u8 revid;
 	const char *name;
@@ -72,54 +53,6 @@ static struct {
 	{ IGD_BROADWELL_H_GT3,     "Broadwell U GT3" },
 };
 
-static void report_cpu_info(void)
-{
-	static const char *const mode[] = {"NOT ", ""};
-	const char *cpu_type = "Unknown";
-
-	char cpu_string[50];
-	char *cpu_name = cpu_string; /* 48 bytes are reported */
-
-	const u32 index = 0x80000000;
-	struct cpuid_result cpuidr = cpuid(index);
-	if (cpuidr.eax < 0x80000004) {
-		strcpy(cpu_string, "Platform info not available");
-	} else {
-		u32 *p = (u32 *)cpu_string;
-		for (unsigned int i = 2; i <= 4; i++) {
-			cpuidr = cpuid(index + i);
-			*p++ = cpuidr.eax;
-			*p++ = cpuidr.ebx;
-			*p++ = cpuidr.ecx;
-			*p++ = cpuidr.edx;
-		}
-	}
-	/* Skip leading spaces in CPU name string */
-	while (cpu_name[0] == ' ')
-		cpu_name++;
-
-	const u32 cpu_id = cpu_get_cpuid();
-
-	/* Look for string to match the name */
-	for (unsigned int i = 0; i < ARRAY_SIZE(cpu_table); i++) {
-		if (cpu_table[i].cpuid == cpu_id) {
-			cpu_type = cpu_table[i].name;
-			break;
-		}
-	}
-
-	printk(BIOS_DEBUG, "CPU: %s\n", cpu_name);
-	printk(BIOS_DEBUG, "CPU: ID %x, %s, ucode: %08x\n",
-	       cpu_id, cpu_type, get_current_microcode_rev());
-
-	const u32 cpu_feature_flag = cpu_get_feature_flags_ecx();
-	const bool aes = (cpu_feature_flag & CPUID_AES);
-	const bool txt = (cpu_feature_flag & CPUID_SMX);
-	const bool vt  = (cpu_feature_flag & CPUID_VMX);
-	printk(BIOS_DEBUG, "CPU: AES %ssupported, TXT %ssupported, VT %ssupported\n",
-	       mode[aes], mode[txt], mode[vt]);
-}
-
 static void report_mch_info(void)
 {
 	const u16 mch_device = pci_read_config16(HOST_BRIDGE, PCI_DEVICE_ID);
diff --git a/src/northbridge/intel/haswell/report_platform.c b/src/northbridge/intel/haswell/report_platform.c
index 28d2f01323..1227292a0c 100644
--- a/src/northbridge/intel/haswell/report_platform.c
+++ b/src/northbridge/intel/haswell/report_platform.c
@@ -9,7 +9,7 @@
 #include <cpu/x86/msr.h>
 #include "haswell.h"
 
-static void report_cpu_info(void)
+static void haswell_report_cpu_info(void)
 {
 	struct cpuid_result cpuidr;
 	u32 i, index, cpu_id, cpu_feature_flag;
@@ -96,6 +96,6 @@ static void report_pch_info(void)
 
 void report_platform_info(void)
 {
-	report_cpu_info();
+	haswell_report_cpu_info();
 	report_pch_info();
 }

From f249991e9d2f4607382032983ce8c443abd17450 Mon Sep 17 00:00:00 2001
From: Angel Pons <th3fanbus@gmail.com>
Date: Mon, 9 Mar 2026 18:00:20 +0100
Subject: [PATCH 3705/3886] cpu/intel/haswell: Fix CPUID macros

Commit 8b0636e06f0e ("cpu/intel/haswell: Clean up CPUID definitions")
used the wrong value for the `CRYSTALWELL_FAMILY` macro. Also, as per
Intel document 634961-024 (Broadwell-H Specification Update), the one
production Broadwell Trad stepping is G0, not C0. And for the sake of
completeness, add the `BROADWELL_FAMILY_TRAD` macro.

Tested with BUILD_TIMELESS=1, Purism Librem 15 v2 remains identical.

Change-Id: I25be5289997000e116cc36cf427a9d4970a3ec1b
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91625
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
---
 src/cpu/intel/haswell/haswell.h      | 5 +++--
 src/cpu/intel/haswell/haswell_init.c | 2 +-
 2 files changed, 4 insertions(+), 3 deletions(-)

diff --git a/src/cpu/intel/haswell/haswell.h b/src/cpu/intel/haswell/haswell.h
index 0a64149f28..1625329b37 100644
--- a/src/cpu/intel/haswell/haswell.h
+++ b/src/cpu/intel/haswell/haswell.h
@@ -10,7 +10,8 @@
 /* CPU types without stepping */
 #define HASWELL_FAMILY_TRAD	0x306c0
 #define HASWELL_FAMILY_ULT	0x40650
-#define CRYSTALWELL_FAMILY	0x306c0
+#define CRYSTALWELL_FAMILY	0x40660
+#define BROADWELL_FAMILY_TRAD	0x40670
 #define BROADWELL_FAMILY_ULT	0x306d0
 
 /* Haswell CPUIDs */
@@ -26,7 +27,7 @@
 #define CPUID_CRYSTALWELL_C0	0x40661
 
 /* Broadwell CPUIDs */
-#define CPUID_BROADWELL_C0	0x40671
+#define CPUID_BROADWELL_G0	0x40671
 
 #define CPUID_BROADWELL_ULT_C0	0x306d2
 #define CPUID_BROADWELL_ULT_D0	0x306d3
diff --git a/src/cpu/intel/haswell/haswell_init.c b/src/cpu/intel/haswell/haswell_init.c
index c21f3c09f8..7d58795db0 100644
--- a/src/cpu/intel/haswell/haswell_init.c
+++ b/src/cpu/intel/haswell/haswell_init.c
@@ -599,7 +599,7 @@ static const struct cpu_device_id cpu_table[] = {
 	{ X86_VENDOR_INTEL, CPUID_HASWELL_ULT_C0, CPUID_EXACT_MATCH_MASK },
 	{ X86_VENDOR_INTEL, CPUID_CRYSTALWELL_B0, CPUID_EXACT_MATCH_MASK },
 	{ X86_VENDOR_INTEL, CPUID_CRYSTALWELL_C0, CPUID_EXACT_MATCH_MASK },
-	{ X86_VENDOR_INTEL, CPUID_BROADWELL_C0, CPUID_EXACT_MATCH_MASK },
+	{ X86_VENDOR_INTEL, CPUID_BROADWELL_G0, CPUID_EXACT_MATCH_MASK },
 	{ X86_VENDOR_INTEL, CPUID_BROADWELL_ULT_C0, CPUID_EXACT_MATCH_MASK },
 	{ X86_VENDOR_INTEL, CPUID_BROADWELL_ULT_D0, CPUID_EXACT_MATCH_MASK },
 	{ X86_VENDOR_INTEL, CPUID_BROADWELL_ULT_E0, CPUID_EXACT_MATCH_MASK },

From f730ec6992148a0e777d92784015ba9524b1dfc7 Mon Sep 17 00:00:00 2001
From: Angel Pons <th3fanbus@gmail.com>
Date: Mon, 9 Mar 2026 18:37:41 +0100
Subject: [PATCH 3706/3886] cpu/intel/haswell/report_cpu_info.c: Update CPUID
 info

Update the entries for Crystalwell and Broadwell ULT, and add the CPUIDs
for Crystalwell B0 and Broadwell G0. Also drop a now-done FIXME comment.

Change-Id: Ib5293b5a0ef3321678c68363fb4bc8999b10cd01
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91626
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/cpu/intel/haswell/report_cpu_info.c | 11 ++++++-----
 1 file changed, 6 insertions(+), 5 deletions(-)

diff --git a/src/cpu/intel/haswell/report_cpu_info.c b/src/cpu/intel/haswell/report_cpu_info.c
index 9f93cd7002..72644c565c 100644
--- a/src/cpu/intel/haswell/report_cpu_info.c
+++ b/src/cpu/intel/haswell/report_cpu_info.c
@@ -8,7 +8,6 @@
 #include <string.h>
 #include <types.h>
 
-/* FIXME: Needs an update */
 static struct {
 	u32 cpuid;
 	const char *name;
@@ -18,10 +17,12 @@ static struct {
 	{ CPUID_HASWELL_C0,       "Haswell C0" },
 	{ CPUID_HASWELL_ULT_B0,   "Haswell ULT B0" },
 	{ CPUID_HASWELL_ULT_C0,   "Haswell ULT C0 or D0" },
-	{ CPUID_CRYSTALWELL_C0,   "Haswell Perf Halo" },
-	{ CPUID_BROADWELL_ULT_C0, "Broadwell C0" },
-	{ CPUID_BROADWELL_ULT_D0, "Broadwell D0" },
-	{ CPUID_BROADWELL_ULT_E0, "Broadwell E0 or F0" },
+	{ CPUID_CRYSTALWELL_B0,   "Crystalwell B0" },
+	{ CPUID_CRYSTALWELL_C0,   "Crystalwell C0" },
+	{ CPUID_BROADWELL_G0,     "Broadwell G0" },
+	{ CPUID_BROADWELL_ULT_C0, "Broadwell ULT C0" },
+	{ CPUID_BROADWELL_ULT_D0, "Broadwell ULT D0" },
+	{ CPUID_BROADWELL_ULT_E0, "Broadwell ULT E0 or F0" },
 };
 
 void report_cpu_info(void)

From e7cfcec7a7273b286acf7ba3d3e1d24cb1a263c4 Mon Sep 17 00:00:00 2001
From: Angel Pons <th3fanbus@gmail.com>
Date: Mon, 9 Mar 2026 18:44:07 +0100
Subject: [PATCH 3707/3886] nb/intel/haswell: Use `report_cpu_info()` from CPU
 code

This function prints CPU information, so it makes sense for it to be
part of CPU code. The version in CPU code prints a bit more info but
is otherwise equivalent. After all, this is just logging some info.

Change-Id: I2a9d8a42f78efab6206710fada1d64fa79e8056e
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91627
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-by: Abdelkader Boudih <coreboot@seuros.com>
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 .../intel/haswell/report_platform.c           | 48 ++-----------------
 1 file changed, 4 insertions(+), 44 deletions(-)

diff --git a/src/northbridge/intel/haswell/report_platform.c b/src/northbridge/intel/haswell/report_platform.c
index 1227292a0c..df0dab7612 100644
--- a/src/northbridge/intel/haswell/report_platform.c
+++ b/src/northbridge/intel/haswell/report_platform.c
@@ -1,52 +1,12 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
 #include <console/console.h>
-#include <arch/cpu.h>
-#include <cpu/intel/microcode.h>
-#include <string.h>
-#include <southbridge/intel/lynxpoint/pch.h>
 #include <device/pci_ops.h>
-#include <cpu/x86/msr.h>
+#include <cpu/intel/haswell/haswell.h>
+#include <southbridge/intel/lynxpoint/pch.h>
+
 #include "haswell.h"
 
-static void haswell_report_cpu_info(void)
-{
-	struct cpuid_result cpuidr;
-	u32 i, index, cpu_id, cpu_feature_flag;
-	char cpu_string[50], *cpu_name = cpu_string; /* 48 bytes are reported */
-	int vt, txt, aes;
-	const char *mode[] = {"NOT ", ""};
-
-	index = 0x80000000;
-	cpuidr = cpuid(index);
-	if (cpuidr.eax < 0x80000004) {
-		strcpy(cpu_string, "Platform info not available");
-	} else {
-		u32 *p = (u32 *)cpu_string;
-		for (i = 2; i <= 4; i++) {
-			cpuidr = cpuid(index + i);
-			*p++ = cpuidr.eax;
-			*p++ = cpuidr.ebx;
-			*p++ = cpuidr.ecx;
-			*p++ = cpuidr.edx;
-		}
-	}
-	/* Skip leading spaces in CPU name string */
-	while (cpu_name[0] == ' ')
-		cpu_name++;
-
-	cpu_id = cpu_get_cpuid();
-	printk(BIOS_DEBUG, "CPU id(%x) ucode:%08x %s\n", cpu_id,
-		get_current_microcode_rev(), cpu_name);
-
-	cpu_feature_flag = cpu_get_feature_flags_ecx();
-	aes = (cpu_feature_flag & CPUID_AES) ? 1 : 0;
-	txt = (cpu_feature_flag & CPUID_SMX) ? 1 : 0;
-	vt = (cpu_feature_flag & CPUID_VMX) ? 1 : 0;
-	printk(BIOS_DEBUG, "AES %ssupported, TXT %ssupported, VT %ssupported\n",
-	       mode[aes], mode[txt], mode[vt]);
-}
-
 /* The PCI id name match comes from Intel document 472178 */
 static struct {
 	u16 dev_id;
@@ -96,6 +56,6 @@ static void report_pch_info(void)
 
 void report_platform_info(void)
 {
-	haswell_report_cpu_info();
+	report_cpu_info();
 	report_pch_info();
 }

From 76290e8cdc56c942c4fbb55848f613f0149a1705 Mon Sep 17 00:00:00 2001
From: Angel Pons <th3fanbus@gmail.com>
Date: Mon, 9 Mar 2026 19:02:45 +0100
Subject: [PATCH 3708/3886] nb/intel/haswell: Move PEG device macros to header

These can and will be used in other files in subsequent commits.

Change-Id: Iba0515151252b22f0211e8ab1470c70dfd172929
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91628
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
---
 src/northbridge/intel/haswell/early_init.c | 4 ++--
 src/northbridge/intel/haswell/early_pcie.c | 4 ----
 src/northbridge/intel/haswell/haswell.h    | 5 +++++
 3 files changed, 7 insertions(+), 6 deletions(-)

diff --git a/src/northbridge/intel/haswell/early_init.c b/src/northbridge/intel/haswell/early_init.c
index e47deb5da6..386c2897cc 100644
--- a/src/northbridge/intel/haswell/early_init.c
+++ b/src/northbridge/intel/haswell/early_init.c
@@ -8,7 +8,7 @@
 
 #include "haswell.h"
 
-static bool peg_hidden[3];
+static bool peg_hidden[MAX_PEG_FUNC];
 
 static void haswell_setup_bars(void)
 {
@@ -111,7 +111,7 @@ void haswell_unhide_peg(void)
 {
 	u32 deven = pci_read_config32(HOST_BRIDGE, DEVEN);
 
-	for (u8 fn = 0; fn <= 2; fn++) {
+	for (u8 fn = 0; fn < MAX_PEG_FUNC; fn++) {
 		if (peg_hidden[fn]) {
 			deven |= DEVEN_D1F0EN >> fn;
 			peg_hidden[fn] = false;
diff --git a/src/northbridge/intel/haswell/early_pcie.c b/src/northbridge/intel/haswell/early_pcie.c
index 3fc8713d29..2b244c5a69 100644
--- a/src/northbridge/intel/haswell/early_pcie.c
+++ b/src/northbridge/intel/haswell/early_pcie.c
@@ -7,10 +7,6 @@
 #include <northbridge/intel/haswell/vcu_mailbox.h>
 #include <types.h>
 
-#define PEG_DEV(func)		PCI_DEV(0, 1, func)
-
-#define MAX_PEG_FUNC		3
-
 static void peg_dmi_unset_and_set_mask_pcicfg(
 	volatile union pci_bank *const bank,
 	const uint32_t offset,
diff --git a/src/northbridge/intel/haswell/haswell.h b/src/northbridge/intel/haswell/haswell.h
index 30b4abd0a7..bd271f4b06 100644
--- a/src/northbridge/intel/haswell/haswell.h
+++ b/src/northbridge/intel/haswell/haswell.h
@@ -16,6 +16,11 @@
 /* Device 0:0.0 PCI configuration space (Host Bridge) */
 #define HOST_BRIDGE	PCI_DEV(0, 0, 0)
 
+/* Device 0:1.x PCI configuration space (PCI Express Graphics) */
+#define PEG_DEV(func)		PCI_DEV(0, 1, func)
+
+#define MAX_PEG_FUNC		3
+
 /* Device 0:2.0 PCI configuration space (Graphics Device) */
 
 #define MSAC		0x62	/* Multi Size Aperture Control */

From fed6f9494dbbf2f45835b8be69e965b1aec208a6 Mon Sep 17 00:00:00 2001
From: Angel Pons <th3fanbus@gmail.com>
Date: Mon, 9 Mar 2026 18:59:49 +0100
Subject: [PATCH 3709/3886] nb/intel/haswell: Move early PEG stuff to separate
 file

Only Haswell / Broadwell Trad have PEG devices. So, don't include
PEG-related code when building for Haswell / Broadwell ULT.

Change-Id: I478f5c6d5850e6fb7cecc04ae5e2aae51d20fc92
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91629
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
---
 src/northbridge/intel/haswell/Makefile.mk  |  4 ++
 src/northbridge/intel/haswell/early_init.c | 78 +--------------------
 src/northbridge/intel/haswell/early_peg.c  | 81 ++++++++++++++++++++++
 src/northbridge/intel/haswell/haswell.h    |  4 +-
 src/northbridge/intel/haswell/romstage.c   |  3 +-
 5 files changed, 93 insertions(+), 77 deletions(-)
 create mode 100644 src/northbridge/intel/haswell/early_peg.c

diff --git a/src/northbridge/intel/haswell/Makefile.mk b/src/northbridge/intel/haswell/Makefile.mk
index bc8cf42046..c5cc82fc16 100644
--- a/src/northbridge/intel/haswell/Makefile.mk
+++ b/src/northbridge/intel/haswell/Makefile.mk
@@ -20,6 +20,10 @@ romstage-y += raminit_shared.c
 
 postcar-y += memmap.c
 
+ifneq ($(CONFIG_INTEL_LYNXPOINT_LP),y)
+romstage-y += early_peg.c
+endif
+
 ifeq ($(CONFIG_USE_NATIVE_RAMINIT),y)
 romstage-y += early_dmi.c early_pcie.c vcu_mailbox.c
 subdirs-y  += native_raminit
diff --git a/src/northbridge/intel/haswell/early_init.c b/src/northbridge/intel/haswell/early_init.c
index 386c2897cc..d52a9d1b85 100644
--- a/src/northbridge/intel/haswell/early_init.c
+++ b/src/northbridge/intel/haswell/early_init.c
@@ -8,8 +8,6 @@
 
 #include "haswell.h"
 
-static bool peg_hidden[MAX_PEG_FUNC];
-
 static void haswell_setup_bars(void)
 {
 	printk(BIOS_DEBUG, "Setting up static northbridge registers...");
@@ -64,78 +62,6 @@ static void haswell_setup_igd(void)
 	pci_update_config8(PCI_DEV(0, 2, 0), MSAC, ~0x06, 0x02);
 }
 
-static void start_peg2_link_training(const pci_devfn_t dev)
-{
-	u32 mask;
-
-	switch (dev) {
-	case PCI_DEV(0, 1, 2):
-		mask = DEVEN_D1F2EN;
-		break;
-	case PCI_DEV(0, 1, 1):
-		mask = DEVEN_D1F1EN;
-		break;
-	case PCI_DEV(0, 1, 0):
-		mask = DEVEN_D1F0EN;
-		break;
-	default:
-		printk(BIOS_ERR, "Link training tried on a non-PEG device!\n");
-		return;
-	}
-
-	pci_update_config32(dev, 0xc24, ~(1 << 16), 1 << 5);
-	printk(BIOS_DEBUG, "Started PEG1%d link training.\n", PCI_FUNC(PCI_DEV2DEVFN(dev)));
-
-	/*
-	 * The MRC will perform PCI enumeration, and if it detects a VGA
-	 * device in a PEG slot, it will disable the IGD and not reserve
-	 * any memory for it. Since the memory map is locked by the time
-	 * MRC finishes, the IGD can't be enabled afterwards. Wonderful.
-	 *
-	 * If one really wants to enable the Intel iGPU as primary, hide
-	 * all PEG devices during MRC execution. This will trick the MRC
-	 * into thinking there aren't any, and will enable the IGD. Note
-	 * that PEG AFE settings will not be programmed, which may cause
-	 * stability problems at higher PCIe link speeds. The most ideal
-	 * way to fix this problem for good is to implement native init.
-	 */
-	if (CONFIG(HASWELL_HIDE_PEG_FROM_MRC)) {
-		pci_update_config32(HOST_BRIDGE, DEVEN, ~mask, 0);
-		peg_hidden[PCI_FUNC(PCI_DEV2DEVFN(dev))] = true;
-		printk(BIOS_DEBUG, "Temporarily hiding PEG1%d.\n",
-		       PCI_FUNC(PCI_DEV2DEVFN(dev)));
-	}
-}
-
-void haswell_unhide_peg(void)
-{
-	u32 deven = pci_read_config32(HOST_BRIDGE, DEVEN);
-
-	for (u8 fn = 0; fn < MAX_PEG_FUNC; fn++) {
-		if (peg_hidden[fn]) {
-			deven |= DEVEN_D1F0EN >> fn;
-			peg_hidden[fn] = false;
-			printk(BIOS_DEBUG, "Unhiding PEG1%d.\n", fn);
-		}
-	}
-
-	pci_write_config32(HOST_BRIDGE, DEVEN, deven);
-}
-
-static void haswell_setup_peg(void)
-{
-	u32 deven = pci_read_config32(HOST_BRIDGE, DEVEN);
-
-	if (deven & DEVEN_D1F2EN)
-		start_peg2_link_training(PCI_DEV(0, 1, 2));
-
-	if (deven & DEVEN_D1F1EN)
-		start_peg2_link_training(PCI_DEV(0, 1, 1));
-
-	if (deven & DEVEN_D1F0EN)
-		start_peg2_link_training(PCI_DEV(0, 1, 0));
-}
-
 static void haswell_setup_misc(void)
 {
 	u32 reg32;
@@ -188,7 +114,9 @@ void haswell_early_initialization(void)
 	/* Setup IOMMU BARs */
 	haswell_setup_iommu();
 
-	haswell_setup_peg();
+	if (!CONFIG(INTEL_LYNXPOINT_LP))
+		northbridge_setup_peg();
+
 	haswell_setup_igd();
 
 	haswell_setup_misc();
diff --git a/src/northbridge/intel/haswell/early_peg.c b/src/northbridge/intel/haswell/early_peg.c
new file mode 100644
index 0000000000..4be9994629
--- /dev/null
+++ b/src/northbridge/intel/haswell/early_peg.c
@@ -0,0 +1,81 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <console/console.h>
+#include <device/pci_def.h>
+#include <device/pci_ops.h>
+#include <northbridge/intel/haswell/haswell.h>
+#include <types.h>
+
+static bool peg_hidden[MAX_PEG_FUNC];
+
+static void start_peg2_link_training(const pci_devfn_t dev)
+{
+	u32 mask;
+
+	switch (dev) {
+	case PCI_DEV(0, 1, 2):
+		mask = DEVEN_D1F2EN;
+		break;
+	case PCI_DEV(0, 1, 1):
+		mask = DEVEN_D1F1EN;
+		break;
+	case PCI_DEV(0, 1, 0):
+		mask = DEVEN_D1F0EN;
+		break;
+	default:
+		printk(BIOS_ERR, "Link training tried on a non-PEG device!\n");
+		return;
+	}
+
+	pci_update_config32(dev, 0xc24, ~(1 << 16), 1 << 5);
+	printk(BIOS_DEBUG, "Started PEG1%d link training.\n", PCI_FUNC(PCI_DEV2DEVFN(dev)));
+
+	/*
+	 * The MRC will perform PCI enumeration, and if it detects a VGA
+	 * device in a PEG slot, it will disable the IGD and not reserve
+	 * any memory for it. Since the memory map is locked by the time
+	 * MRC finishes, the IGD can't be enabled afterwards. Wonderful.
+	 *
+	 * If one really wants to enable the Intel iGPU as primary, hide
+	 * all PEG devices during MRC execution. This will trick the MRC
+	 * into thinking there aren't any, and will enable the IGD. Note
+	 * that PEG AFE settings will not be programmed, which may cause
+	 * stability problems at higher PCIe link speeds. The most ideal
+	 * way to fix this problem for good is to implement native init.
+	 */
+	if (CONFIG(HASWELL_HIDE_PEG_FROM_MRC)) {
+		pci_update_config32(HOST_BRIDGE, DEVEN, ~mask, 0);
+		peg_hidden[PCI_FUNC(PCI_DEV2DEVFN(dev))] = true;
+		printk(BIOS_DEBUG, "Temporarily hiding PEG1%d.\n",
+		       PCI_FUNC(PCI_DEV2DEVFN(dev)));
+	}
+}
+
+void northbridge_unhide_peg(void)
+{
+	u32 deven = pci_read_config32(HOST_BRIDGE, DEVEN);
+
+	for (u8 fn = 0; fn < MAX_PEG_FUNC; fn++) {
+		if (peg_hidden[fn]) {
+			deven |= DEVEN_D1F0EN >> fn;
+			peg_hidden[fn] = false;
+			printk(BIOS_DEBUG, "Unhiding PEG1%d.\n", fn);
+		}
+	}
+
+	pci_write_config32(HOST_BRIDGE, DEVEN, deven);
+}
+
+void northbridge_setup_peg(void)
+{
+	u32 deven = pci_read_config32(HOST_BRIDGE, DEVEN);
+
+	if (deven & DEVEN_D1F2EN)
+		start_peg2_link_training(PCI_DEV(0, 1, 2));
+
+	if (deven & DEVEN_D1F1EN)
+		start_peg2_link_training(PCI_DEV(0, 1, 1));
+
+	if (deven & DEVEN_D1F0EN)
+		start_peg2_link_training(PCI_DEV(0, 1, 0));
+}
diff --git a/src/northbridge/intel/haswell/haswell.h b/src/northbridge/intel/haswell/haswell.h
index bd271f4b06..aeedd421e1 100644
--- a/src/northbridge/intel/haswell/haswell.h
+++ b/src/northbridge/intel/haswell/haswell.h
@@ -37,7 +37,9 @@ void mb_late_romstage_setup(void); /* optional */
 
 void haswell_early_initialization(void);
 void haswell_late_initialization(void);
-void haswell_unhide_peg(void);
+
+void northbridge_setup_peg(void);
+void northbridge_unhide_peg(void);
 
 void dmi_early_init(void);
 void peg_dmi_recipe(const bool is_peg, const pci_devfn_t dev);
diff --git a/src/northbridge/intel/haswell/romstage.c b/src/northbridge/intel/haswell/romstage.c
index 85fe967c7d..a6726f7f06 100644
--- a/src/northbridge/intel/haswell/romstage.c
+++ b/src/northbridge/intel/haswell/romstage.c
@@ -56,7 +56,8 @@ void mainboard_romstage_entry(void)
 		txt_dump_regions();
 	}
 
-	haswell_unhide_peg();
+	if (!CONFIG(INTEL_LYNXPOINT_LP))
+		northbridge_unhide_peg();
 
 	romstage_handoff_init(s3resume);
 

From 60994cf3952ec6943fdb8812346186dedf8409e4 Mon Sep 17 00:00:00 2001
From: Angel Pons <th3fanbus@gmail.com>
Date: Mon, 9 Mar 2026 19:52:11 +0100
Subject: [PATCH 3710/3886] nb/intel/haswell/early_peg.c: Simplify
 implementation

Instead of open-coding function-to-DEVEN-bit mapping thrice (using
a different implementation each time), introduce `deven_for_peg()`
to map the PCI function number to the corresponding DEVEN bit. Use
the PCI function number as primary parameter, instead of passing a
`pci_devfn_t` around and getting the PCI function number from that
using two macros.

Change-Id: Ia2f7cdcff3c95f831269fa51f9bfc60bef0907a1
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91630
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/northbridge/intel/haswell/early_peg.c | 71 ++++++++++-------------
 1 file changed, 31 insertions(+), 40 deletions(-)

diff --git a/src/northbridge/intel/haswell/early_peg.c b/src/northbridge/intel/haswell/early_peg.c
index 4be9994629..4b923bb708 100644
--- a/src/northbridge/intel/haswell/early_peg.c
+++ b/src/northbridge/intel/haswell/early_peg.c
@@ -8,27 +8,22 @@
 
 static bool peg_hidden[MAX_PEG_FUNC];
 
-static void start_peg2_link_training(const pci_devfn_t dev)
+static u32 deven_for_peg(const u8 func)
 {
-	u32 mask;
-
-	switch (dev) {
-	case PCI_DEV(0, 1, 2):
-		mask = DEVEN_D1F2EN;
-		break;
-	case PCI_DEV(0, 1, 1):
-		mask = DEVEN_D1F1EN;
-		break;
-	case PCI_DEV(0, 1, 0):
-		mask = DEVEN_D1F0EN;
-		break;
-	default:
-		printk(BIOS_ERR, "Link training tried on a non-PEG device!\n");
-		return;
+	switch (func) {
+		case 0:  return DEVEN_D1F0EN;
+		case 1:  return DEVEN_D1F1EN;
+		case 2:  return DEVEN_D1F2EN;
+		default: return 0;
 	}
+}
+
+static void start_peg2_link_training(const u8 func)
+{
+	const pci_devfn_t dev = PEG_DEV(func);
 
 	pci_update_config32(dev, 0xc24, ~(1 << 16), 1 << 5);
-	printk(BIOS_DEBUG, "Started PEG1%d link training.\n", PCI_FUNC(PCI_DEV2DEVFN(dev)));
+	printk(BIOS_DEBUG, "Started PEG1%u link training.\n", func);
 
 	/*
 	 * The MRC will perform PCI enumeration, and if it detects a VGA
@@ -44,10 +39,20 @@ static void start_peg2_link_training(const pci_devfn_t dev)
 	 * way to fix this problem for good is to implement native init.
 	 */
 	if (CONFIG(HASWELL_HIDE_PEG_FROM_MRC)) {
-		pci_update_config32(HOST_BRIDGE, DEVEN, ~mask, 0);
-		peg_hidden[PCI_FUNC(PCI_DEV2DEVFN(dev))] = true;
-		printk(BIOS_DEBUG, "Temporarily hiding PEG1%d.\n",
-		       PCI_FUNC(PCI_DEV2DEVFN(dev)));
+		pci_and_config32(HOST_BRIDGE, DEVEN, ~deven_for_peg(func));
+		peg_hidden[func] = true;
+		printk(BIOS_DEBUG, "Temporarily hiding PEG1%u.\n", func);
+	}
+}
+
+void northbridge_setup_peg(void)
+{
+	const u32 deven = pci_read_config32(HOST_BRIDGE, DEVEN);
+
+	for (u8 func = 0; func < MAX_PEG_FUNC; func++) {
+		if (deven & deven_for_peg(func)) {
+			start_peg2_link_training(func);
+		}
 	}
 }
 
@@ -55,27 +60,13 @@ void northbridge_unhide_peg(void)
 {
 	u32 deven = pci_read_config32(HOST_BRIDGE, DEVEN);
 
-	for (u8 fn = 0; fn < MAX_PEG_FUNC; fn++) {
-		if (peg_hidden[fn]) {
-			deven |= DEVEN_D1F0EN >> fn;
-			peg_hidden[fn] = false;
-			printk(BIOS_DEBUG, "Unhiding PEG1%d.\n", fn);
+	for (u8 func = 0; func < MAX_PEG_FUNC; func++) {
+		if (peg_hidden[func]) {
+			deven |= deven_for_peg(func);
+			peg_hidden[func] = false;
+			printk(BIOS_DEBUG, "Unhiding PEG1%u.\n", func);
 		}
 	}
 
 	pci_write_config32(HOST_BRIDGE, DEVEN, deven);
 }
-
-void northbridge_setup_peg(void)
-{
-	u32 deven = pci_read_config32(HOST_BRIDGE, DEVEN);
-
-	if (deven & DEVEN_D1F2EN)
-		start_peg2_link_training(PCI_DEV(0, 1, 2));
-
-	if (deven & DEVEN_D1F1EN)
-		start_peg2_link_training(PCI_DEV(0, 1, 1));
-
-	if (deven & DEVEN_D1F0EN)
-		start_peg2_link_training(PCI_DEV(0, 1, 0));
-}

From a0be26ef5f9a536f90dfbfadb1f30d4f9f9d2704 Mon Sep 17 00:00:00 2001
From: Angel Pons <th3fanbus@gmail.com>
Date: Mon, 9 Mar 2026 21:28:26 +0100
Subject: [PATCH 3711/3886] nb/intel/haswell: Fix IOMMU early init

Intel Document 492662 (Haswell System Agent BIOS Spec), Rev 1.6.0 states
that `ARCHDIS` (VT engine BAR, offset 0xff0) has to be written fully, as
well as several other things that were not done properly in coreboot. As
these steps are Haswell-specific, introduce two helper functions to test
if the CPU is Haswell or Broadwell.

Intel Document 535094 (Broadwell BIOS Spec), Rev 2.2.0 contains the same
steps for Broadwell. To permit unifying Haswell and Broadwell, implement
the Broadwell steps as well.

Change-Id: I077e064754720d9f9f627733c954712a2b24b5b7
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91631
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
---
 src/cpu/intel/haswell/haswell.h            | 23 +++++++++++
 src/northbridge/intel/haswell/early_init.c | 46 ++++++++++++++++------
 src/northbridge/intel/haswell/haswell.h    |  3 --
 3 files changed, 56 insertions(+), 16 deletions(-)

diff --git a/src/cpu/intel/haswell/haswell.h b/src/cpu/intel/haswell/haswell.h
index 1625329b37..b8cc98a570 100644
--- a/src/cpu/intel/haswell/haswell.h
+++ b/src/cpu/intel/haswell/haswell.h
@@ -192,4 +192,27 @@ static inline bool haswell_is_ult(void)
 	return CONFIG(INTEL_LYNXPOINT_LP);
 }
 
+static inline bool cpu_is_haswell(void)
+{
+	switch (cpu_family_model()) {
+	case HASWELL_FAMILY_TRAD:
+	case HASWELL_FAMILY_ULT:
+	case CRYSTALWELL_FAMILY:
+		return true;
+	default:
+		return false;
+	}
+}
+
+static inline bool cpu_is_broadwell(void)
+{
+	switch (cpu_family_model()) {
+	case BROADWELL_FAMILY_TRAD:
+	case BROADWELL_FAMILY_ULT:
+		return true;
+	default:
+		return false;
+	}
+}
+
 #endif
diff --git a/src/northbridge/intel/haswell/early_init.c b/src/northbridge/intel/haswell/early_init.c
index d52a9d1b85..1b5059adb8 100644
--- a/src/northbridge/intel/haswell/early_init.c
+++ b/src/northbridge/intel/haswell/early_init.c
@@ -1,10 +1,11 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
-#include <stdint.h>
 #include <console/console.h>
+#include <cpu/intel/haswell/haswell.h>
 #include <device/mmio.h>
 #include <device/pci_def.h>
 #include <device/pci_ops.h>
+#include <types.h>
 
 #include "haswell.h"
 
@@ -80,10 +81,9 @@ static void haswell_setup_misc(void)
 	mchbar_write32(INTRDIRCTL, reg32);
 }
 
-static void haswell_setup_iommu(void)
+static void northbridge_setup_iommu(void)
 {
 	const u32 capid0_a = pci_read_config32(HOST_BRIDGE, CAPID0_A);
-
 	if (capid0_a & VTD_DISABLE)
 		return;
 
@@ -93,17 +93,37 @@ static void haswell_setup_iommu(void)
 	mchbar_write32(VTVC0BAR + 4, VTVC0_BASE_ADDRESS >> 32);
 	mchbar_write32(VTVC0BAR + 0, VTVC0_BASE_ADDRESS | 1);
 
-	/* Set L3HIT2PEND_DIS, lock GFXVTBAR policy config registers */
-	u32 reg32;
-	reg32 = read32p(GFXVT_BASE_ADDRESS + ARCHDIS);
-	write32p(GFXVT_BASE_ADDRESS + ARCHDIS, reg32 | DMAR_LCKDN | L3HIT2PEND_DIS);
+	if (cpu_is_haswell()) {
+		/*
+		 * Intel Document 492662 (Haswell System Agent BIOS Spec), Rev 1.6.0
+		 * Section 11.3 - DMA Remapping Engine Configuration
+		 */
+		const u32 gfxvt_archdis = 0x02100000 | DMAR_LCKDN;
+		write32p(GFXVT_BASE_ADDRESS + ARCHDIS, gfxvt_archdis);
 
-	/* Clear SPCAPCTRL */
-	reg32 = read32p(VTVC0_BASE_ADDRESS + ARCHDIS) & ~SPCAPCTRL;
+		clrsetbits32p(VTVC0_BASE_ADDRESS + 0xf04, 0xf << 15, 1 << 15);
 
-	/* Set GLBIOTLBINV, GLBCTXTINV; lock VTVC0BAR policy config registers */
-	write32p(VTVC0_BASE_ADDRESS + ARCHDIS,
-			reg32 | DMAR_LCKDN | GLBIOTLBINV | GLBCTXTINV);
+		u32 vtvc0_archdis = 0x000a5003 | DMAR_LCKDN;
+		if (pci_read_config16(PCI_DEV(0, 2, 0), PCI_DEVICE_ID) == 0xffff) {
+			vtvc0_archdis |= SPCAPCTRL;
+		}
+		write32p(VTVC0_BASE_ADDRESS + ARCHDIS, vtvc0_archdis);
+	}
+	if (cpu_is_broadwell()) {
+		/*
+		 * Intel Document 535094 (Broadwell BIOS Spec), Rev 2.2.0
+		 * Section 17.3 - DMA Remapping Engine Configuration
+		 */
+
+		/* TODO: For steppings <= D0 (pre-production), also clear bit 0 */
+		setbits32p(GFXVT_BASE_ADDRESS + ARCHDIS, DMAR_LCKDN | PRSCAPDIS);
+
+		write32p(GFXVT_BASE_ADDRESS + 0x100, 0x50a);
+
+		clrsetbits32p(VTVC0_BASE_ADDRESS + 0xf04, 0xf << 15, 1 << 15);
+
+		setbits32p(VTVC0_BASE_ADDRESS + ARCHDIS, DMAR_LCKDN);
+	}
 }
 
 void haswell_early_initialization(void)
@@ -112,7 +132,7 @@ void haswell_early_initialization(void)
 	haswell_setup_bars();
 
 	/* Setup IOMMU BARs */
-	haswell_setup_iommu();
+	northbridge_setup_iommu();
 
 	if (!CONFIG(INTEL_LYNXPOINT_LP))
 		northbridge_setup_peg();
diff --git a/src/northbridge/intel/haswell/haswell.h b/src/northbridge/intel/haswell/haswell.h
index aeedd421e1..4d2da01788 100644
--- a/src/northbridge/intel/haswell/haswell.h
+++ b/src/northbridge/intel/haswell/haswell.h
@@ -28,10 +28,7 @@
 #define ARCHDIS		0xff0	/* DMA Remap Engine Policy Control */
 #define  DMAR_LCKDN	(1 << 31)
 #define  SPCAPCTRL	(1 << 25)
-#define  L3HIT2PEND_DIS	(1 << 20)
 #define  PRSCAPDIS	(1 << 2)
-#define  GLBIOTLBINV	(1 << 1)
-#define  GLBCTXTINV	(1 << 0)
 
 void mb_late_romstage_setup(void); /* optional */
 

From 5bb8b30c0385b119686d7255fd28c480af5e5837 Mon Sep 17 00:00:00 2001
From: Angel Pons <th3fanbus@gmail.com>
Date: Mon, 9 Mar 2026 22:39:51 +0100
Subject: [PATCH 3712/3886] nb/intel/haswell: Enable SA clock gating later

Reference code version 1.9.1 sets `SAPMCTL` bit 0 just before setting
`BIOS_RESET_CPL` bits 0 and 1. Do the same thing in coreboot.

Change-Id: I36e24d2a3bd754e56df59a1e996d285ec6bf5205
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91632
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
---
 src/northbridge/intel/haswell/early_init.c  | 4 ----
 src/northbridge/intel/haswell/northbridge.c | 3 +++
 2 files changed, 3 insertions(+), 4 deletions(-)

diff --git a/src/northbridge/intel/haswell/early_init.c b/src/northbridge/intel/haswell/early_init.c
index 1b5059adb8..6a5ce53a40 100644
--- a/src/northbridge/intel/haswell/early_init.c
+++ b/src/northbridge/intel/haswell/early_init.c
@@ -72,10 +72,6 @@ static void haswell_setup_misc(void)
 	reg32 |= (1 << 9) | (1 << 10);
 	mchbar_write32(SAPMCTL, reg32);
 
-	/* Enable SA Clock Gating */
-	reg32 = mchbar_read32(SAPMCTL);
-	mchbar_write32(SAPMCTL, reg32 | 1);
-
 	reg32 = mchbar_read32(INTRDIRCTL);
 	reg32 |= (1 << 4) | (1 << 5);
 	mchbar_write32(INTRDIRCTL, reg32);
diff --git a/src/northbridge/intel/haswell/northbridge.c b/src/northbridge/intel/haswell/northbridge.c
index e819838175..84d9fb5792 100644
--- a/src/northbridge/intel/haswell/northbridge.c
+++ b/src/northbridge/intel/haswell/northbridge.c
@@ -464,6 +464,9 @@ static void northbridge_init(struct device *dev)
 
 	disable_devices();
 
+	/* Enable SA Clock Gating */
+	mchbar_setbits32(SAPMCTL, 1 << 0);
+
 	/*
 	 * Set bits 0 + 1 of BIOS_RESET_CPL to indicate to the CPU
 	 * that BIOS has initialized memory and power management.

From 53222f1ccba7466572283a808d4c5c80555ee0ba Mon Sep 17 00:00:00 2001
From: Kenneth Chan <kenneth.chan@quanta.corp-partner.google.com>
Date: Tue, 17 Mar 2026 10:43:32 +0800
Subject: [PATCH 3713/3886] mb/google/brask/var/kulnex: Remove weak symbols for
 memory config

Remove __weak to ensure variant-specific memory functions properly
override the default implementations in the baseboard.

BUG=b:491711748
BRANCH=firmware-brya-14505.B
TEST=Build and boot on kulnex, verify memory initialization.

Change-Id: I61e33a215d41d25cc1f64866e653c0f1d4eb8ba8
Signed-off-by: Kenneth Chan <kenneth.chan@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91693
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
---
 src/mainboard/google/brya/variants/kulnex/memory.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/src/mainboard/google/brya/variants/kulnex/memory.c b/src/mainboard/google/brya/variants/kulnex/memory.c
index 742ce7fe3a..b1f4005454 100644
--- a/src/mainboard/google/brya/variants/kulnex/memory.c
+++ b/src/mainboard/google/brya/variants/kulnex/memory.c
@@ -27,17 +27,17 @@ static const struct mb_cfg ddr5_mem_config = {
 	},
 };
 
-const struct mb_cfg *__weak variant_memory_params(void)
+const struct mb_cfg *variant_memory_params(void)
 {
 	return &ddr5_mem_config;
 }
 
-bool __weak variant_is_half_populated(void)
+bool variant_is_half_populated(void)
 {
 	return false;
 }
 
-void __weak variant_get_spd_info(struct mem_spd *spd_info)
+void variant_get_spd_info(struct mem_spd *spd_info)
 {
 	spd_info->topo = MEM_TOPO_DIMM_MODULE;
 	spd_info->smbus[0].addr_dimm[0] = 0x50;

From 9422dacdb8440b3ed4e0847581242d8dd265c88c Mon Sep 17 00:00:00 2001
From: Kenneth Chan <kenneth.chan@quanta.corp-partner.google.com>
Date: Tue, 17 Mar 2026 11:29:06 +0800
Subject: [PATCH 3714/3886] mb/google/brask/var/moxoe: Remove weak symbols for
 memory config

Remove __weak to ensure variant-specific memory functions properly
override the default implementations in the baseboard.

BUG=b:481186489
BRANCH=firmware-brya-14505.B
TEST=Build and boot on moxoe, verify memory initialization.

Change-Id: Ifdd58963cbd0b108774708b085d73b6fb4af30aa
Signed-off-by: Kenneth Chan <kenneth.chan@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91695
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
---
 src/mainboard/google/brya/variants/moxoe/memory.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/src/mainboard/google/brya/variants/moxoe/memory.c b/src/mainboard/google/brya/variants/moxoe/memory.c
index 742ce7fe3a..b1f4005454 100644
--- a/src/mainboard/google/brya/variants/moxoe/memory.c
+++ b/src/mainboard/google/brya/variants/moxoe/memory.c
@@ -27,17 +27,17 @@ static const struct mb_cfg ddr5_mem_config = {
 	},
 };
 
-const struct mb_cfg *__weak variant_memory_params(void)
+const struct mb_cfg *variant_memory_params(void)
 {
 	return &ddr5_mem_config;
 }
 
-bool __weak variant_is_half_populated(void)
+bool variant_is_half_populated(void)
 {
 	return false;
 }
 
-void __weak variant_get_spd_info(struct mem_spd *spd_info)
+void variant_get_spd_info(struct mem_spd *spd_info)
 {
 	spd_info->topo = MEM_TOPO_DIMM_MODULE;
 	spd_info->smbus[0].addr_dimm[0] = 0x50;

From ce1db1f54a1f65834dbbf42d90681718b069f573 Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Fri, 13 Feb 2026 20:58:00 +0000
Subject: [PATCH 3715/3886] cpu/x86/smm: reserve SMRAM for OPAL S3 state

Reserve a small persistent SMRAM subregion for OPAL S3 unlock state, so
the payload-provided OPAL secret can survive SMM handler reload on S3
resume.

Expose the region base/size to SMM via smm_runtime and provide an
accessor for SMM code. Clear the region on cold boot/reboot, but
preserve it when waking from S3.

TEST=tested with rest of patch train

Change-Id: Ib1e92edb31c845367afe6185e5fa18ab1bc71108
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91414
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
---
 src/cpu/x86/Kconfig                  | 15 +++++++++++++++
 src/cpu/x86/smm/smm_module_handler.c |  8 ++++++++
 src/cpu/x86/smm/smm_module_loader.c  | 18 ++++++++++++++++++
 src/cpu/x86/smm/tseg_region.c        | 13 ++++++++++++-
 src/include/cpu/x86/smm.h            |  9 +++++++++
 5 files changed, 62 insertions(+), 1 deletion(-)

diff --git a/src/cpu/x86/Kconfig b/src/cpu/x86/Kconfig
index c049d4b124..5f6bf7bd18 100644
--- a/src/cpu/x86/Kconfig
+++ b/src/cpu/x86/Kconfig
@@ -196,6 +196,21 @@ config SMM_MODULE_STACK_SIZE
 	  This option determines the size of the stack within the SMM handler
 	  modules.
 
+config SMM_OPAL_S3_STATE_SMRAM
+	bool
+	help
+	  Reserve a small persistent region in SMRAM for OPAL S3 state so the
+	  OPAL secret survives SMM handler reload on S3 resume.
+
+config SMM_OPAL_S3_STATE_SMRAM_SIZE
+	hex
+	default 0x1000 if SMM_OPAL_S3_STATE_SMRAM
+	default 0x0
+	help
+	  Size in bytes of the persistent SMRAM region reserved for OPAL S3
+	  secret/state. Must be large enough to store the OPAL S3 state
+	  structure and should be kept minimal to reduce SMRAM pressure.
+
 config SMM_OPAL_S3_SCRATCH_CBMEM
 	bool
 	depends on HAVE_ACPI_RESUME
diff --git a/src/cpu/x86/smm/smm_module_handler.c b/src/cpu/x86/smm/smm_module_handler.c
index 3f14d970d8..36b68f6ba5 100644
--- a/src/cpu/x86/smm/smm_module_handler.c
+++ b/src/cpu/x86/smm/smm_module_handler.c
@@ -74,6 +74,14 @@ void smm_get_opal_s3_scratch_buffer(uintptr_t *base, size_t *size)
 }
 #endif
 
+#if CONFIG(SMM_OPAL_S3_STATE_SMRAM)
+void smm_get_opal_s3_state_buffer(uintptr_t *base, size_t *size)
+{
+	*base = smm_runtime.opal_s3_state_base;
+	*size = smm_runtime.opal_s3_state_size;
+}
+#endif
+
 void smm_get_cbmemc_buffer(void **buffer_out, size_t *size_out)
 {
 	*buffer_out = smm_runtime.cbmemc;
diff --git a/src/cpu/x86/smm/smm_module_loader.c b/src/cpu/x86/smm/smm_module_loader.c
index 4946fe5a0f..8476245b3c 100644
--- a/src/cpu/x86/smm/smm_module_loader.c
+++ b/src/cpu/x86/smm/smm_module_loader.c
@@ -1,5 +1,6 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
+#include <acpi/acpi.h>
 #include <acpi/acpi_gnvs.h>
 #include <cbmem.h>
 #include <commonlib/helpers.h>
@@ -386,6 +387,23 @@ static void setup_smihandler_params(struct smm_runtime *mod_params,
 		mod_params->opal_s3_scratch_size = opal_s3_scratch_size;
 	}
 #endif
+
+#if CONFIG(SMM_OPAL_S3_STATE_SMRAM)
+	uintptr_t state_base = 0;
+	size_t state_size = 0;
+	if (smm_subregion(SMM_SUBREGION_OPAL_S3_STATE, &state_base, &state_size)) {
+		printk(BIOS_ERR, "SMM: Failed to locate OPAL S3 state SMRAM region\n");
+		mod_params->opal_s3_state_base = 0;
+		mod_params->opal_s3_state_size = 0;
+	} else {
+		mod_params->opal_s3_state_base = state_base;
+		mod_params->opal_s3_state_size = state_size;
+
+		/* Clear any stale state on cold boot/reboot, but preserve it on S3 resume. */
+		if (!acpi_is_wakeup_s3())
+			memset((void *)state_base, 0, state_size);
+	}
+#endif
 }
 
 static void print_region(const char *name, const struct region region)
diff --git a/src/cpu/x86/smm/tseg_region.c b/src/cpu/x86/smm/tseg_region.c
index 90e61dc426..d02f9d8e08 100644
--- a/src/cpu/x86/smm/tseg_region.c
+++ b/src/cpu/x86/smm/tseg_region.c
@@ -15,6 +15,8 @@
  *     +-------------------------+
  *     |  External Stage Cache   | SMM_RESERVED_SIZE
  *     +-------------------------+
+ *     |   OPAL S3 State (opt)   | SMM_OPAL_S3_STATE_SMRAM_SIZE
+ *     +-------------------------+
  *     |      code and data      |
  *     |         (TSEG)          |
  *     +-------------------------+ TSEG
@@ -25,6 +27,7 @@ int smm_subregion(int sub, uintptr_t *start, size_t *size)
 	size_t sub_size;
 	const size_t ied_size = CONFIG_IED_REGION_SIZE;
 	const size_t cache_size = CONFIG_SMM_RESERVED_SIZE;
+	const size_t opal_state_size = CONFIG_SMM_OPAL_S3_STATE_SMRAM_SIZE;
 
 	if (CONFIG(SMM_TSEG))
 		smm_region(&sub_base, &sub_size);
@@ -34,13 +37,21 @@ int smm_subregion(int sub, uintptr_t *start, size_t *size)
 		return -1;
 
 	ASSERT(IS_ALIGNED(sub_base, sub_size));
-	ASSERT(sub_size > (cache_size + ied_size));
+	ASSERT(sub_size > (cache_size + ied_size + opal_state_size));
 
 	switch (sub) {
 	case SMM_SUBREGION_HANDLER:
 		/* Handler starts at the base of TSEG. */
 		sub_size -= ied_size;
 		sub_size -= cache_size;
+		sub_size -= opal_state_size;
+		break;
+	case SMM_SUBREGION_OPAL_S3_STATE:
+		if (!opal_state_size)
+			return -1;
+		/* Persistent OPAL S3 state lives below the external stage cache. */
+		sub_base += sub_size - (ied_size + cache_size + opal_state_size);
+		sub_size = opal_state_size;
 		break;
 	case SMM_SUBREGION_CACHE:
 		/* External cache is in the middle of TSEG. */
diff --git a/src/include/cpu/x86/smm.h b/src/include/cpu/x86/smm.h
index 913bd37205..26fc1d4abb 100644
--- a/src/include/cpu/x86/smm.h
+++ b/src/include/cpu/x86/smm.h
@@ -100,6 +100,10 @@ struct smm_runtime {
 	uintptr_t opal_s3_scratch_base;
 	size_t opal_s3_scratch_size;
 #endif
+#if CONFIG(SMM_OPAL_S3_STATE_SMRAM)
+	uintptr_t opal_s3_state_base;
+	size_t opal_s3_state_size;
+#endif
 } __packed;
 
 struct smm_module_params {
@@ -206,6 +210,8 @@ static inline void aseg_region(uintptr_t *start, size_t *size)
 enum {
 	/* SMM handler area. */
 	SMM_SUBREGION_HANDLER,
+	/* Persistent OPAL S3 state area. */
+	SMM_SUBREGION_OPAL_S3_STATE,
 	/* SMM cache region. */
 	SMM_SUBREGION_CACHE,
 	/* Chipset specific area. */
@@ -245,5 +251,8 @@ void smm_get_smmstore_com_buffer(uintptr_t *base, size_t *size);
 #if CONFIG(SMM_OPAL_S3_SCRATCH_CBMEM)
 void smm_get_opal_s3_scratch_buffer(uintptr_t *base, size_t *size);
 #endif
+#if CONFIG(SMM_OPAL_S3_STATE_SMRAM)
+void smm_get_opal_s3_state_buffer(uintptr_t *base, size_t *size);
+#endif
 
 #endif /* CPU_X86_SMM_H */

From 11e9550e0c9662831b62f8edbfd4d151212362ce Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Fri, 13 Feb 2026 21:01:39 +0000
Subject: [PATCH 3716/3886] soc/intel/common/smm: Use cpu/x86 save_state ops

Switch Intel common block smihandler to use the generic x86
smm_save_state_ops instead of its own custom struct. Replace
find_save_state() and get_io_misc_info with apmc_node; use
node-based get_reg/set_reg functions. Alias em64t100_ops and
em64t101_ops for cpu/x86 save_state.c consumers.

TEST=tested with rest of patch train

Change-Id: Ie64478ccfdc0a0bda4354641aba06705e2c8c70d
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91656
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
---
 .../block/include/intelblocks/smihandler.h    |  23 +-
 src/soc/intel/common/block/smm/smihandler.c   | 322 +++++++++++-------
 2 files changed, 209 insertions(+), 136 deletions(-)

diff --git a/src/soc/intel/common/block/include/intelblocks/smihandler.h b/src/soc/intel/common/block/include/intelblocks/smihandler.h
index 437c3215cf..c958f5b781 100644
--- a/src/soc/intel/common/block/include/intelblocks/smihandler.h
+++ b/src/soc/intel/common/block/include/intelblocks/smihandler.h
@@ -3,34 +3,13 @@
 #ifndef SOC_INTEL_COMMON_BLOCK_SMI_HANDLER_H
 #define SOC_INTEL_COMMON_BLOCK_SMI_HANDLER_H
 
+#include <cpu/x86/save_state.h>
 #include <device/device.h>
 #include <stdint.h>
 
 struct gpi_status;
 struct global_nvs;
 
-/*
- * The register value is used with get_reg and set_reg
- */
-enum smm_reg {
-	RAX,
-	RBX,
-	RCX,
-	RDX,
-};
-
-struct smm_save_state_ops {
-	/* return io_misc_info from SMM Save State Area */
-	uint32_t (*get_io_misc_info)(void *state);
-
-	/* return value of the requested register from
-	 * SMM Save State Area
-	 */
-	uint64_t (*get_reg)(void *state, enum smm_reg reg);
-
-	void (*set_reg)(void *state, enum smm_reg reg, uint64_t val);
-};
-
 typedef void (*smi_handler_t)(const struct smm_save_state_ops *save_state_ops);
 
 /*
diff --git a/src/soc/intel/common/block/smm/smihandler.c b/src/soc/intel/common/block/smm/smihandler.c
index 1af03739d2..e0fa13e581 100644
--- a/src/soc/intel/common/block/smm/smihandler.c
+++ b/src/soc/intel/common/block/smm/smihandler.c
@@ -8,6 +8,7 @@
 #include <cpu/x86/smm.h>
 #include <cpu/intel/em64t100_save_state.h>
 #include <cpu/intel/em64t101_save_state.h>
+#include <cpu/x86/save_state.h>
 #include <cpu/intel/msr.h>
 #include <delay.h>
 #include <device/mmio.h>
@@ -31,6 +32,8 @@
 #include <soc/smbus.h>
 #include <spi-generic.h>
 #include <stdint.h>
+#include <string.h>
+#include <types.h>
 
 /* SoC overrides. */
 
@@ -63,40 +66,6 @@ __weak void mainboard_smi_espi_handler(void)
 	/* no-op */
 }
 
-/* Common Functions */
-
-static void *find_save_state(const struct smm_save_state_ops *save_state_ops,
-	int cmd)
-{
-	int node;
-	void *state = NULL;
-	uint32_t io_misc_info;
-	uint8_t reg_al;
-
-	/* Check all nodes looking for the one that issued the IO */
-	for (node = 0; node < CONFIG_MAX_CPUS; node++) {
-		state = smm_get_save_state(node);
-
-		io_misc_info = save_state_ops->get_io_misc_info(state);
-
-		/* Check for Synchronous IO (bit0==1) */
-		if (!(io_misc_info & (1 << 0)))
-			continue;
-		/* Make sure it was a write (bit4==0) */
-		if (io_misc_info & (1 << 4))
-			continue;
-		/* Check for APMC IO port */
-		if (((io_misc_info >> 16) & 0xff) != APM_CNT)
-			continue;
-		/* Check AL against the requested command */
-		reg_al = save_state_ops->get_reg(state, RAX);
-		if (reg_al != cmd)
-			continue;
-		break;
-	}
-	return state;
-}
-
 /* Inherited from cpu/x86/smm.h resulting in a different signature */
 void southbridge_smi_set_eos(void)
 {
@@ -251,22 +220,23 @@ static void southbridge_smi_gsmi(
 	const struct smm_save_state_ops *save_state_ops)
 {
 	u8 sub_command, ret;
-	void *io_smi = NULL;
-	uint32_t reg_ebx;
+	int node;
+	uint32_t eax_val, reg_ebx;
 
-	io_smi = find_save_state(save_state_ops, APM_CNT_ELOG_GSMI);
-	if (!io_smi)
+	node = save_state_ops->apmc_node(APM_CNT_ELOG_GSMI);
+	if (node < 0)
+		return;
+	if (save_state_ops->get_reg(RAX, node, &eax_val, sizeof(eax_val)) != 0)
 		return;
 	/* Command and return value in EAX */
-	sub_command = (save_state_ops->get_reg(io_smi, RAX) >> 8)
-		& 0xff;
+	sub_command = (eax_val >> 8) & 0xff;
 
-	/* Parameter buffer in EBX */
-	reg_ebx = save_state_ops->get_reg(io_smi, RBX);
+	if (save_state_ops->get_reg(RBX, node, &reg_ebx, sizeof(reg_ebx)) != 0)
+		return;
 
 	/* drivers/elog/gsmi.c */
 	ret = gsmi_exec(sub_command, &reg_ebx);
-	save_state_ops->set_reg(io_smi, RAX, ret);
+	save_state_ops->set_reg(RAX, node, &ret, sizeof(ret));
 }
 
 static void set_insmm_sts(const bool enable_writes)
@@ -287,17 +257,19 @@ static void southbridge_smi_store(
 	const struct smm_save_state_ops *save_state_ops)
 {
 	u8 sub_command, ret;
-	void *io_smi;
-	uint32_t reg_ebx;
+	int node;
+	uint32_t eax_val, reg_ebx;
 
-	io_smi = find_save_state(save_state_ops, APM_CNT_SMMSTORE);
-	if (!io_smi)
+	node = save_state_ops->apmc_node(APM_CNT_SMMSTORE);
+	if (node < 0)
+		return;
+	if (save_state_ops->get_reg(RAX, node, &eax_val, sizeof(eax_val)) != 0)
 		return;
 	/* Command and return value in EAX */
-	sub_command = (save_state_ops->get_reg(io_smi, RAX) >> 8) & 0xff;
+	sub_command = (eax_val >> 8) & 0xff;
 
-	/* Parameter buffer in EBX */
-	reg_ebx = save_state_ops->get_reg(io_smi, RBX);
+	if (save_state_ops->get_reg(RBX, node, &reg_ebx, sizeof(reg_ebx)) != 0)
+		return;
 
 	const bool wp_enabled = !fast_spi_wpd_status();
 	if (wp_enabled) {
@@ -313,7 +285,7 @@ static void southbridge_smi_store(
 
 	/* drivers/smmstore/smi.c */
 	ret = smmstore_exec(sub_command, (void *)(uintptr_t)reg_ebx);
-	save_state_ops->set_reg(io_smi, RAX, ret);
+	save_state_ops->set_reg(RAX, node, &ret, sizeof(ret));
 
 	if (wp_enabled) {
 		fast_spi_enable_wp();
@@ -555,118 +527,240 @@ void southbridge_smi_handler(void)
 	}
 }
 
-static uint32_t em64t100_smm_save_state_get_io_misc_info(void *state)
+static int em64t100_get_reg(const enum cpu_reg reg, const int node, void *out, const uint8_t length)
 {
-	em64t100_smm_state_save_area_t *smm_state = state;
-	return smm_state->io_misc_info;
-}
+	em64t100_smm_state_save_area_t *state;
+	u64 value;
 
-static uint64_t em64t100_smm_save_state_get_reg(void *state, enum smm_reg reg)
-{
-	uintptr_t value = 0;
-	em64t100_smm_state_save_area_t *smm_state = state;
+	if (!out || length > sizeof(value))
+		return -1;
+
+	state = smm_get_save_state(node);
+	if (!state)
+		return -1;
 
 	switch (reg) {
 	case RAX:
-		value = smm_state->rax;
+		value = state->rax;
 		break;
 	case RBX:
-		value = smm_state->rbx;
+		value = state->rbx;
 		break;
 	case RCX:
-		value = smm_state->rcx;
+		value = state->rcx;
 		break;
 	case RDX:
-		value = smm_state->rdx;
+		value = state->rdx;
 		break;
 	default:
-		break;
+		return -1;
 	}
-	return value;
+
+	memcpy(out, &value, length);
+	return 0;
 }
 
-static void em64t100_smm_save_state_set_reg(void *state, enum smm_reg reg,
-	uint64_t val)
+static int em64t100_set_reg(const enum cpu_reg reg, const int node, void *in, const uint8_t length)
 {
-	em64t100_smm_state_save_area_t *smm_state = state;
-	switch (reg) {
-	case RAX:
-		smm_state->rax = val;
-		break;
-	case RBX:
-		smm_state->rbx = val;
-		break;
-	case RCX:
-		smm_state->rcx = val;
-		break;
-	case RDX:
-		smm_state->rdx = val;
-		break;
-	default:
-		break;
-	}
-}
+	em64t100_smm_state_save_area_t *state;
+	u64 value;
 
-static uint32_t em64t101_smm_save_state_get_io_misc_info(void *state)
-{
-	em64t101_smm_state_save_area_t *smm_state = state;
-	return smm_state->io_misc_info;
-}
+	if (!in || length > sizeof(value))
+		return -1;
 
-static uint64_t em64t101_smm_save_state_get_reg(void *state, enum smm_reg reg)
-{
-	uintptr_t value = 0;
-	em64t101_smm_state_save_area_t *smm_state = state;
+	state = smm_get_save_state(node);
+	if (!state)
+		return -1;
+
+	value = 0;
+	memcpy(&value, in, length);
 
 	switch (reg) {
 	case RAX:
-		value = smm_state->rax;
+		state->rax = value;
 		break;
 	case RBX:
-		value = smm_state->rbx;
+		state->rbx = value;
 		break;
 	case RCX:
-		value = smm_state->rcx;
+		state->rcx = value;
 		break;
 	case RDX:
-		value = smm_state->rdx;
+		state->rdx = value;
 		break;
 	default:
-		break;
+		return -1;
 	}
-	return value;
+
+	return 0;
 }
 
-static void em64t101_smm_save_state_set_reg(void *state, enum smm_reg reg,
-	uint64_t val)
+static int em64t100_apmc_node(u8 cmd)
 {
-	em64t101_smm_state_save_area_t *smm_state = state;
+	int node;
+
+	for (node = 0; node < CONFIG_MAX_CPUS; node++) {
+		em64t100_smm_state_save_area_t *state;
+		u32 io_misc_info;
+		u8 reg_al;
+
+		state = smm_get_save_state(node);
+		if (!state)
+			continue;
+
+		io_misc_info = state->io_misc_info;
+
+		/* Synchronous I/O (bit0 == 1). */
+		if (!(io_misc_info & (1 << 0)))
+			continue;
+
+		/* Write (bit4 == 0). */
+		if (io_misc_info & (1 << 4))
+			continue;
+
+		/* APMC port. */
+		if (((io_misc_info >> 16) & 0xff) != APM_CNT)
+			continue;
+
+		reg_al = (u8)state->rax;
+		if (reg_al != cmd)
+			continue;
+
+		return node;
+	}
+
+	return -1;
+}
+
+static int em64t101_get_reg(const enum cpu_reg reg, const int node, void *out, const uint8_t length)
+{
+	em64t101_smm_state_save_area_t *state;
+	u64 value;
+
+	if (!out || length > sizeof(value))
+		return -1;
+
+	state = smm_get_save_state(node);
+	if (!state)
+		return -1;
+
 	switch (reg) {
 	case RAX:
-		smm_state->rax = val;
+		value = state->rax;
 		break;
 	case RBX:
-		smm_state->rbx = val;
+		value = state->rbx;
 		break;
 	case RCX:
-		smm_state->rcx = val;
+		value = state->rcx;
 		break;
 	case RDX:
-		smm_state->rdx = val;
+		value = state->rdx;
 		break;
 	default:
-		break;
+		return -1;
 	}
+
+	memcpy(out, &value, length);
+	return 0;
 }
 
+static int em64t101_set_reg(const enum cpu_reg reg, const int node, void *in, const uint8_t length)
+{
+	em64t101_smm_state_save_area_t *state;
+	u64 value;
+
+	if (!in || length > sizeof(value))
+		return -1;
+
+	state = smm_get_save_state(node);
+	if (!state)
+		return -1;
+
+	value = 0;
+	memcpy(&value, in, length);
+
+	switch (reg) {
+	case RAX:
+		state->rax = value;
+		break;
+	case RBX:
+		state->rbx = value;
+		break;
+	case RCX:
+		state->rcx = value;
+		break;
+	case RDX:
+		state->rdx = value;
+		break;
+	default:
+		return -1;
+	}
+
+	return 0;
+}
+
+static int em64t101_apmc_node(u8 cmd)
+{
+	int node;
+
+	for (node = 0; node < CONFIG_MAX_CPUS; node++) {
+		em64t101_smm_state_save_area_t *state;
+		u32 io_misc_info;
+		u8 reg_al;
+
+		state = smm_get_save_state(node);
+		if (!state)
+			continue;
+
+		io_misc_info = state->io_misc_info;
+
+		/* Synchronous I/O (bit0 == 1). */
+		if (!(io_misc_info & (1 << 0)))
+			continue;
+
+		/* Write (bit4 == 0). */
+		if (io_misc_info & (1 << 4))
+			continue;
+
+		/* APMC port. */
+		if (((io_misc_info >> 16) & 0xff) != APM_CNT)
+			continue;
+
+		reg_al = (u8)state->rax;
+		if (reg_al != cmd)
+			continue;
+
+		return node;
+	}
+
+	return -1;
+}
+
+static const uint32_t em64t100_revision_table[] = {
+	0x30100,
+	SMM_REV_INVALID,
+};
+
+static const uint32_t em64t101_revision_table[] = {
+	0x30101,
+	SMM_REV_INVALID,
+};
+
 const struct smm_save_state_ops em64t100_smm_ops = {
-	.get_io_misc_info = em64t100_smm_save_state_get_io_misc_info,
-	.get_reg = em64t100_smm_save_state_get_reg,
-	.set_reg = em64t100_smm_save_state_set_reg,
+	.revision_table = em64t100_revision_table,
+	.get_reg = em64t100_get_reg,
+	.set_reg = em64t100_set_reg,
+	.apmc_node = em64t100_apmc_node,
 };
 
+
 const struct smm_save_state_ops em64t101_smm_ops = {
-	.get_io_misc_info = em64t101_smm_save_state_get_io_misc_info,
-	.get_reg = em64t101_smm_save_state_get_reg,
-	.set_reg = em64t101_smm_save_state_set_reg,
+	.revision_table = em64t101_revision_table,
+	.get_reg = em64t101_get_reg,
+	.set_reg = em64t101_set_reg,
+	.apmc_node = em64t101_apmc_node,
 };
+
+const struct smm_save_state_ops *em64t100_ops = &em64t100_smm_ops;
+const struct smm_save_state_ops *em64t101_ops = &em64t101_smm_ops;

From e17cc395af50db065f8304b95ea86ccfb0146826 Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Tue, 17 Mar 2026 12:38:39 -0500
Subject: [PATCH 3717/3886] soc/intel/alderlake/fsp_params: Drop !! in builtin
 root port check
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

The PCIE_RP_BUILT_IN flag test is used only as a boolean condition, so
the double-negation is unnecessary. Also fix the comment grammar.

Change-Id: I5e1ff5848d9cedb2385892c795297719ccc1d5cf
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91721
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
---
 src/soc/intel/alderlake/fsp_params.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/soc/intel/alderlake/fsp_params.c b/src/soc/intel/alderlake/fsp_params.c
index 396ea53c5a..3d6f824502 100644
--- a/src/soc/intel/alderlake/fsp_params.c
+++ b/src/soc/intel/alderlake/fsp_params.c
@@ -967,8 +967,8 @@ static void fill_fsps_pcie_params(FSP_S_CONFIG *s_cfg,
 		s_cfg->PcieRpHotPlug[i] = !!(rp_cfg->flags & PCIE_RP_HOTPLUG)
 				|| CONFIG(SOC_INTEL_COMPLIANCE_TEST_MODE);
 		s_cfg->PcieRpClkReqDetect[i] = !!(rp_cfg->flags & PCIE_RP_CLK_REQ_DETECT);
-		/* PcieRpSlotImplemented default to 1 (slot implemented) in FSP; 0: built-in */
-		if (!!(rp_cfg->flags & PCIE_RP_BUILT_IN))
+		/* PcieRpSlotImplemented defaults to 1 (slot implemented) in FSP; 0: built-in */
+		if (rp_cfg->flags & PCIE_RP_BUILT_IN)
 			s_cfg->PcieRpSlotImplemented[i] = false;
 		s_cfg->PcieRpDetectTimeoutMs[i] = rp_cfg->pcie_rp_detect_timeout_ms;
 		configure_pch_rp_power_management(s_cfg, rp_cfg, i);

From b03b42285e1e610dd9af822e5111c5d0b468fd5a Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Fri, 23 Jan 2026 11:28:14 -0600
Subject: [PATCH 3718/3886] soc/intel/{mtl,ptl}/fsp_params: Program
 PcieRpSlotImplemented
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

ADL programs this but MTL and PTL do not, so add it to the latter two
for consistency.

Change-Id: I8c982fcc810b3783cba4c66754df2b555bce6dfc
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90878
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
---
 src/soc/intel/meteorlake/fsp_params.c  | 3 +++
 src/soc/intel/pantherlake/fsp_params.c | 3 +++
 2 files changed, 6 insertions(+)

diff --git a/src/soc/intel/meteorlake/fsp_params.c b/src/soc/intel/meteorlake/fsp_params.c
index 5e7bdc53ab..b3dfaffa5d 100644
--- a/src/soc/intel/meteorlake/fsp_params.c
+++ b/src/soc/intel/meteorlake/fsp_params.c
@@ -641,6 +641,9 @@ static void fill_fsps_pcie_params(FSP_S_CONFIG *s_cfg,
 		s_cfg->PcieRpHotPlug[i] = !!(rp_cfg->flags & PCIE_RP_HOTPLUG)
 				|| CONFIG(SOC_INTEL_COMPLIANCE_TEST_MODE);
 		s_cfg->PcieRpClkReqDetect[i] = !!(rp_cfg->flags & PCIE_RP_CLK_REQ_DETECT);
+		/* PcieRpSlotImplemented defaults to 1 (slot implemented) in FSP; 0: built-in */
+		if (rp_cfg->flags & PCIE_RP_BUILT_IN)
+			s_cfg->PcieRpSlotImplemented[i] = false;
 		s_cfg->PcieRpDetectTimeoutMs[i] = rp_cfg->pcie_rp_detect_timeout_ms;
 		configure_pch_rp_power_management(s_cfg, rp_cfg, i);
 	}
diff --git a/src/soc/intel/pantherlake/fsp_params.c b/src/soc/intel/pantherlake/fsp_params.c
index 226ae1677a..e5fb896513 100644
--- a/src/soc/intel/pantherlake/fsp_params.c
+++ b/src/soc/intel/pantherlake/fsp_params.c
@@ -601,6 +601,9 @@ static void fill_fsps_pcie_params(FSP_S_CONFIG *s_cfg,
 		s_cfg->PcieRpHotPlug[i] =
 			!!(rp_cfg->flags & PCIE_RP_HOTPLUG) || CONFIG(SOC_INTEL_COMPLIANCE_TEST_MODE);
 		s_cfg->PcieRpClkReqDetect[i] = !!(rp_cfg->flags & PCIE_RP_CLK_REQ_DETECT);
+		/* PcieRpSlotImplemented defaults to 1 (slot implemented) in FSP; 0: built-in */
+		if (rp_cfg->flags & PCIE_RP_BUILT_IN)
+			s_cfg->PcieRpSlotImplemented[i] = false;
 		s_cfg->PcieRpDetectTimeoutMs[i] = rp_cfg->pcie_rp_detect_timeout_ms;
 		configure_pch_rp_power_management(s_cfg, rp_cfg, i);
 	}

From 674000732d0ec39f6416b8d5e0c7c1756be8b03c Mon Sep 17 00:00:00 2001
From: Arthur Heymans <arthur@aheymans.xyz>
Date: Mon, 16 Mar 2026 20:53:33 +0100
Subject: [PATCH 3719/3886] drivers/intel/dtbt: Skip mailbox commands on
 downstream bridges

Downstream bridges share the same PCI device ID as the upstream
bridge but have no firmware mailbox. Sending commands to them
causes timeouts. Add a forward declaration of dtbt_device_ops
to detect and skip bridges whose parent is also a dTBT device.

Tested on thinkpad t480: The 5s timeout is now gone.

Change-Id: I96febb0e52e0ffbe52a237212b8f708a7b05c6d7
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91689
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
---
 src/drivers/intel/dtbt/dtbt.c | 11 +++++++++++
 1 file changed, 11 insertions(+)

diff --git a/src/drivers/intel/dtbt/dtbt.c b/src/drivers/intel/dtbt/dtbt.c
index 695f44105e..59d7847bd2 100644
--- a/src/drivers/intel/dtbt/dtbt.c
+++ b/src/drivers/intel/dtbt/dtbt.c
@@ -11,6 +11,7 @@
 #include "chip.h"
 #include "dtbt.h"
 
+static struct device_operations dtbt_device_ops;
 
 /* Returns true on success, false on timeout or TBT2PCIE Error field non-zero */
 static bool dtbt_cmd(struct device *dev, u8 command, u32 data, u32 timeout)
@@ -183,6 +184,16 @@ static void dtbt_enable(struct device *dev)
 	if (!is_dev_enabled(dev) || dev->path.pci.devfn != 0)
 		return;
 
+	/*
+	 * Only the upstream bridge has the firmware mailbox (PCIE2TBT/TBT2PCIE
+	 * registers). Downstream bridges behind it share the same PCI device ID
+	 * but have no mailbox, so sending commands to them will timeout. Skip any
+	 * bridge whose parent is also a dTBT bridge (i.e. a downstream bridge).
+	 */
+	if (dev->upstream && dev->upstream->dev &&
+	    dev->upstream->dev->ops == &dtbt_device_ops)
+		return;
+
 	printk(BIOS_INFO, "dTBT controller found at %s\n", dev_path(dev));
 
 	/* Set security level (Table 37/428); failure aborts enable */

From 09d689561a68c5f3023953e07632411e85ed5172 Mon Sep 17 00:00:00 2001
From: Payne Lin <payne.lin@mediatek.corp-partner.google.com>
Date: Wed, 11 Mar 2026 15:43:15 +0800
Subject: [PATCH 3720/3886] soc/mediatek/common: dsi: Fix CPHY hfp_byte error
 check

In CPHY mode, mtk_dsi_cphy_vdo_timing previously packed multiple values
into hfp_byte:
- Bits [7:0]: actual HFP byte count
- Bits [30:16]: hs_vb_ps_wc
- Bit 31: HFP_HS_EN flag

The previous error check treated the entire compound value as the HFP
byte count, resulting in false error messages like:
"Calculated hfp_byte -1850408952 and hbp_byte 4 are too small"

This patch refactors mtk_dsi_cphy_vdo_timing to return hfp_byte and
the upper bits (hfp_wc_upper) separately:
- hfp_byte now consistently represents the actual HFP byte count for
both CPHY and DPHY modes
- hfp_wc_upper contains hs_vb_ps_wc and HFP_HS_EN for CPHY (0 for DPHY)
- The values are combined when writing to dsi_hfp_wc register

This approach:
- Eliminates the need for mask operations in the caller
- Simplifies hfp/hbp validation and adjustment logic
- Makes hfp_byte semantically consistent across CPHY/DPHY

BUG=b:489932059
TEST=Boot and verify display output on MT8189 CPHY panel
BRANCH=skywalker

Signed-off-by: Payne Lin <payne.lin@mediatek.com>
Change-Id: I46229c35f978a88276f4ae2a4582b2ea4164c1db
Signed-off-by: Cindy Lu <luyi8@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91683
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
---
 src/soc/mediatek/common/dsi_common.c             | 10 +++++++---
 src/soc/mediatek/common/include/soc/dsi_common.h |  3 ++-
 src/soc/mediatek/common/mtk_mipi_cphy.c          |  7 +++++--
 3 files changed, 14 insertions(+), 6 deletions(-)

diff --git a/src/soc/mediatek/common/dsi_common.c b/src/soc/mediatek/common/dsi_common.c
index 04dc0a85c3..4071cee41a 100644
--- a/src/soc/mediatek/common/dsi_common.c
+++ b/src/soc/mediatek/common/dsi_common.c
@@ -278,6 +278,8 @@ static void mtk_dsi_config_vdo_timing(struct dsi_regs *const dsi_reg, u32 mode_f
 	u32 hbp_offset;
 	bool is_cphy = !!(mode_flags & MIPI_DSI_MODE_CPHY);
 	bool is_dsc_enabled = !!(mode_flags & MIPI_DSI_DSC_MODE);
+	bool cphy_mode;
+	u32 hfp_wc_upper = 0;
 	int channels = !!(mode_flags & MIPI_DSI_DUAL_CHANNEL) ? 2 : 1;
 	int dsc_ratio = is_dsc_enabled ? COMPRESSION_RATIO : UNCOMPRESSED_RATIO;
 
@@ -301,9 +303,11 @@ static void mtk_dsi_config_vdo_timing(struct dsi_regs *const dsi_reg, u32 mode_f
 
 	hfp_byte = hfp * bytes_per_pixel;
 
-	if (CONFIG(MEDIATEK_DSI_CPHY) && is_cphy)
+	cphy_mode = CONFIG(MEDIATEK_DSI_CPHY) && is_cphy;
+
+	if (cphy_mode)
 		mtk_dsi_cphy_vdo_timing(lanes, edid, phy_timing, bytes_per_pixel, hbp, hfp,
-					&hbp_byte, &hfp_byte, &hsync_active_byte);
+					&hbp_byte, &hfp_byte, &hsync_active_byte, &hfp_wc_upper);
 	else
 		mtk_dsi_dphy_vdo_timing(mode_flags, lanes, edid, phy_timing, bytes_per_pixel,
 					hbp, hfp, &hbp_byte, &hfp_byte, &hsync_active_byte);
@@ -325,7 +329,7 @@ static void mtk_dsi_config_vdo_timing(struct dsi_regs *const dsi_reg, u32 mode_f
 
 	write32(&dsi_reg->dsi_hsa_wc, hsync_active_byte);
 	write32(&dsi_reg->dsi_hbp_wc, hbp_byte);
-	write32(&dsi_reg->dsi_hfp_wc, hfp_byte);
+	write32(&dsi_reg->dsi_hfp_wc, hfp_byte | hfp_wc_upper);
 
 	if (is_dsc_enabled)
 		packet_fmt = COMPRESSED_PIXEL_STREAM_V2;
diff --git a/src/soc/mediatek/common/include/soc/dsi_common.h b/src/soc/mediatek/common/include/soc/dsi_common.h
index 62bff790a9..f9ebd58866 100644
--- a/src/soc/mediatek/common/include/soc/dsi_common.h
+++ b/src/soc/mediatek/common/include/soc/dsi_common.h
@@ -179,7 +179,8 @@ void mtk_dsi_cphy_timing(struct dsi_regs *dsi_reg, u32 data_rate,
 void mtk_dsi_cphy_vdo_timing(const u32 lanes, const struct edid *edid,
 			     const struct mtk_phy_timing *phy_timing,
 			     const u32 bytes_per_pixel, const u32 hbp, const u32 hfp,
-			     s32 *hbp_byte, s32 *hfp_byte, u32 *hsync_active_byte);
+			     s32 *hbp_byte, s32 *hfp_byte, u32 *hsync_active_byte,
+			     u32 *hfp_wc_upper);
 void mtk_dsi_cphy_disable_ck_mode(struct mipi_tx_regs *mipi_tx_reg);
 void mtk_dsi_dphy_disable_ck_mode(struct mipi_tx_regs *mipi_tx_reg);
 void mtk_dsi_dphy_timing_calculation(u32 data_rate_mhz, struct mtk_phy_timing *timing);
diff --git a/src/soc/mediatek/common/mtk_mipi_cphy.c b/src/soc/mediatek/common/mtk_mipi_cphy.c
index ecf7915f67..1bf289abb9 100644
--- a/src/soc/mediatek/common/mtk_mipi_cphy.c
+++ b/src/soc/mediatek/common/mtk_mipi_cphy.c
@@ -91,7 +91,8 @@ void mtk_dsi_cphy_vdo_timing(const u32 lanes,
 			     const u32 hfp,
 			     s32 *hbp_byte,
 			     s32 *hfp_byte,
-			     u32 *hsync_active_byte)
+			     u32 *hsync_active_byte,
+			     u32 *hfp_wc_upper)
 {
 	s32 active_byte, phy_cycle, phy_trail, tmp;
 	u32 hs_vb_ps_wc, ps_wc, data_phy_cycles;
@@ -106,8 +107,10 @@ void mtk_dsi_cphy_vdo_timing(const u32 lanes,
 	phy_trail = 2 * (phy_timing->da_hs_trail + 1) * lanes - 6 * lanes - 14;
 	tmp = hfp * bytes_per_pixel - phy_cycle;
 	*hfp_byte = MIN(MAX(8, tmp), phy_trail);
+
+	/* Return upper bits separately for CPHY HFP_WC register */
 	ps_wc = edid->mode.ha * bytes_per_pixel;
 	hs_vb_ps_wc = ps_wc - (phy_timing->lpx + phy_timing->da_hs_exit +
 		phy_timing->da_hs_prepare + phy_timing->da_hs_zero + 2) * lanes;
-	*hfp_byte |= hs_vb_ps_wc << 16 | HFP_HS_EN;
+	*hfp_wc_upper = hs_vb_ps_wc << 16 | HFP_HS_EN;
 }

From d74cf143fe66fd86326f596066df930fe6b8a013 Mon Sep 17 00:00:00 2001
From: Kenneth Chan <kenneth.chan@quanta.corp-partner.google.com>
Date: Tue, 17 Mar 2026 12:15:11 +0800
Subject: [PATCH 3721/3886] mb/google/brask/var/kulnex: Disable SAGV

Since kulnex is a box product using DDR5 SODIMM, remove SAGV enable to
use the default disabled state for better memory stability.

BUG=b:480035819
TEST=Build and boot, verify SaGv is disabled via FSP logs.

Change-Id: I37d56a33a1ba48ef105e03ca1a24c11291646fc0
Signed-off-by: Kenneth Chan <kenneth.chan@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91697
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
---
 src/mainboard/google/brya/variants/kulnex/overridetree.cb | 2 --
 1 file changed, 2 deletions(-)

diff --git a/src/mainboard/google/brya/variants/kulnex/overridetree.cb b/src/mainboard/google/brya/variants/kulnex/overridetree.cb
index 71268f88ac..b91970bcec 100644
--- a/src/mainboard/google/brya/variants/kulnex/overridetree.cb
+++ b/src/mainboard/google/brya/variants/kulnex/overridetree.cb
@@ -28,8 +28,6 @@ chip soc/intel/alderlake
 		.enable_fast_vmode = 1,
 	}"
 
-	register "sagv" = "SaGv_Enabled"
-
 	register "usb2_ports[1]" = "USB2_PORT_EMPTY"	# Disable USB2 Port 1
 	register "usb2_ports[2]" = "USB2_PORT_EMPTY"	# Disable USB2 Port 2
 	register "usb2_ports[4]" = "USB2_PORT_EMPTY"	# Disable USB2 Port 4

From a6b7fa54742189fde9d278754c0f7958faa469a5 Mon Sep 17 00:00:00 2001
From: Kenneth Chan <kenneth.chan@quanta.corp-partner.google.com>
Date: Tue, 17 Mar 2026 12:04:58 +0800
Subject: [PATCH 3722/3886] mb/google/brask/var/moxoe: Disable SAGV

Since moxoe is a box product using DDR5 SODIMM, remove SAGV enable to
use the default disabled state for better memory stability.

BUG=b:481186489
TEST=Build and boot, verify SaGv is disabled via FSP logs.

Change-Id: I1e07f7cb32b7387a7b96c9666eb809983559f7f4
Signed-off-by: Kenneth Chan <kenneth.chan@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91696
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
---
 src/mainboard/google/brya/variants/moxoe/overridetree.cb | 2 --
 1 file changed, 2 deletions(-)

diff --git a/src/mainboard/google/brya/variants/moxoe/overridetree.cb b/src/mainboard/google/brya/variants/moxoe/overridetree.cb
index 71268f88ac..b91970bcec 100644
--- a/src/mainboard/google/brya/variants/moxoe/overridetree.cb
+++ b/src/mainboard/google/brya/variants/moxoe/overridetree.cb
@@ -28,8 +28,6 @@ chip soc/intel/alderlake
 		.enable_fast_vmode = 1,
 	}"
 
-	register "sagv" = "SaGv_Enabled"
-
 	register "usb2_ports[1]" = "USB2_PORT_EMPTY"	# Disable USB2 Port 1
 	register "usb2_ports[2]" = "USB2_PORT_EMPTY"	# Disable USB2 Port 2
 	register "usb2_ports[4]" = "USB2_PORT_EMPTY"	# Disable USB2 Port 4

From 42a114e23f11964a4a3f085840460685314ad5ec Mon Sep 17 00:00:00 2001
From: Qinghong Zeng <zengqinghong@huaqin.corp-partner.google.com>
Date: Mon, 16 Mar 2026 20:08:58 +0800
Subject: [PATCH 3723/3886] mb/google/nissa/var/teliks: Generate RAM ID for
 BWMYAX32P8A-32G

Generate RAM ID for BWMYAX32P8A-32G

DRAM Part Name                 ID to assign
BWMYAX32P8A-32G                4 (0100)

BUG=b:493358217
BRANCH=firmware-nissa-15217.B
TEST=emerge-nissa coreboot

Change-Id: Ia43dc45874e57c92c5b377c5afd073ef9ced7c57
Signed-off-by: Qinghong Zeng <zengqinghong@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91686
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Yanqiong Huang <huangyanqiong@huaqin.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/google/brya/variants/teliks/memory/Makefile.mk    | 2 +-
 .../google/brya/variants/teliks/memory/dram_id.generated.txt    | 1 +
 .../google/brya/variants/teliks/memory/mem_parts_used.txt       | 1 +
 3 files changed, 3 insertions(+), 1 deletion(-)

diff --git a/src/mainboard/google/brya/variants/teliks/memory/Makefile.mk b/src/mainboard/google/brya/variants/teliks/memory/Makefile.mk
index 3b7dc39124..0294778d43 100644
--- a/src/mainboard/google/brya/variants/teliks/memory/Makefile.mk
+++ b/src/mainboard/google/brya/variants/teliks/memory/Makefile.mk
@@ -8,5 +8,5 @@ SPD_SOURCES += spd/lp5/set-0/spd-1.hex      # ID = 0(0b0000)  Parts = MT62F512M3
 SPD_SOURCES += spd/lp5/set-0/spd-2.hex      # ID = 1(0b0001)  Parts = H9JCNNNCP3MLYR-N6E, MT62F1G32D4DR-031 WT:B
 SPD_SOURCES += spd/lp5/set-0/spd-4.hex      # ID = 2(0b0010)  Parts = H9JCNNNFA5MLYR-N6E, MT62F2G32D8DR-031 WT:B
 SPD_SOURCES += spd/lp5/set-0/spd-9.hex      # ID = 3(0b0011)  Parts = K3KL6L60GM-MGCT
-SPD_SOURCES += spd/lp5/set-0/spd-7.hex      # ID = 4(0b0100)  Parts = MT62F1G32D2DS-026 WT:B, K3KL8L80CM-MGCT, H58G56BK7BX068
+SPD_SOURCES += spd/lp5/set-0/spd-7.hex      # ID = 4(0b0100)  Parts = MT62F1G32D2DS-026 WT:B, K3KL8L80CM-MGCT, H58G56BK7BX068, BWMYAX32P8A-32G
 SPD_SOURCES += spd/lp5/set-0/spd-8.hex      # ID = 5(0b0101)  Parts = MT62F2G32D4DS-026 WT:B, K3KL9L90CM-MGCT, H58G66BK7BX067
diff --git a/src/mainboard/google/brya/variants/teliks/memory/dram_id.generated.txt b/src/mainboard/google/brya/variants/teliks/memory/dram_id.generated.txt
index 773f11b676..ee12a852c6 100644
--- a/src/mainboard/google/brya/variants/teliks/memory/dram_id.generated.txt
+++ b/src/mainboard/google/brya/variants/teliks/memory/dram_id.generated.txt
@@ -17,3 +17,4 @@ H58G56BK7BX068                 4 (0100)
 MT62F2G32D4DS-026 WT:B         5 (0101)
 K3KL9L90CM-MGCT                5 (0101)
 H58G66BK7BX067                 5 (0101)
+BWMYAX32P8A-32G                4 (0100)
diff --git a/src/mainboard/google/brya/variants/teliks/memory/mem_parts_used.txt b/src/mainboard/google/brya/variants/teliks/memory/mem_parts_used.txt
index 8aee4de40e..7198c14c2d 100644
--- a/src/mainboard/google/brya/variants/teliks/memory/mem_parts_used.txt
+++ b/src/mainboard/google/brya/variants/teliks/memory/mem_parts_used.txt
@@ -22,3 +22,4 @@ H58G56BK7BX068
 MT62F2G32D4DS-026 WT:B
 K3KL9L90CM-MGCT
 H58G66BK7BX067
+BWMYAX32P8A-32G

From fbd755341a45dc18a636d4c580e18f4343e16c82 Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Sun, 1 Feb 2026 21:21:57 +0000
Subject: [PATCH 3724/3886] security/tcg: add OPAL S3 unlock Kconfig

Add a generic configuration option for SMM-assisted TCG OPAL NVMe
unlock on S3 resume.

This also defines the APMC command IDs and the payload->SMM ABI
structure used to pass the OPAL password into SMM.

TEST=tested with rest of patch train

Change-Id: Id99ace7c17a311b65519023be4118c5b20ddecf9
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91043
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/include/cpu/x86/smm.h            |  2 ++
 src/include/security/tcg/opal_s3.h   | 47 ++++++++++++++++++++++++++++
 src/security/Kconfig                 |  1 +
 src/security/Makefile.mk             |  1 +
 src/security/tcg/Kconfig             |  7 +++++
 src/security/tcg/Makefile.mk         |  3 ++
 src/security/tcg/opal_s3/Kconfig     | 16 ++++++++++
 src/security/tcg/opal_s3/Makefile.mk |  1 +
 8 files changed, 78 insertions(+)
 create mode 100644 src/include/security/tcg/opal_s3.h
 create mode 100644 src/security/tcg/Kconfig
 create mode 100644 src/security/tcg/Makefile.mk
 create mode 100644 src/security/tcg/opal_s3/Kconfig
 create mode 100644 src/security/tcg/opal_s3/Makefile.mk

diff --git a/src/include/cpu/x86/smm.h b/src/include/cpu/x86/smm.h
index 26fc1d4abb..834874095f 100644
--- a/src/include/cpu/x86/smm.h
+++ b/src/include/cpu/x86/smm.h
@@ -28,6 +28,8 @@
 #define APM_CNT_MBI_UPDATE	0xeb
 #define APM_CNT_SMMINFO		0xec
 #define APM_CNT_SMMSTORE	0xed
+#define APM_CNT_OPAL_S3_UNLOCK	0xe9
+#define APM_CNT_OPAL_SVC	0xee
 #define APM_CNT_ELOG_GSMI	0xef
 #define APM_STS		0xb3
 
diff --git a/src/include/security/tcg/opal_s3.h b/src/include/security/tcg/opal_s3.h
new file mode 100644
index 0000000000..666723c596
--- /dev/null
+++ b/src/include/security/tcg/opal_s3.h
@@ -0,0 +1,47 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef SECURITY_TCG_OPAL_S3_H
+#define SECURITY_TCG_OPAL_S3_H
+
+#include <stddef.h>
+#include <types.h>
+
+/*
+ * ABI between payload software and the SMM OPAL S3 unlock handler.
+ *
+ * The payload is expected to place this structure in normal RAM and pass its
+ * address in RBX when calling call_smm(APM_CNT_OPAL_SVC, OPAL_SMM_SUBCMD_*, ctx).
+ */
+
+#define OPAL_SMM_SUBCMD_SET_SECRET   0x01
+#define OPAL_SMM_SUBCMD_CLEAR_SECRET 0x02
+
+#define OPAL_S3_SMM_CTX_SIGNATURE 0x3353504f /* "OPS3" */
+#define OPAL_S3_SMM_CTX_VERSION   0x0001
+/*
+ * Fixed size for a stable payload<->SMM ABI.
+ *
+ * Keep this as a constant (not a Kconfig option): changing it requires a
+ * coordinated payload update.
+ */
+#define OPAL_S3_MAX_PASSWORD_LEN 32
+
+struct opal_s3_smm_ctx {
+	u32 signature;
+	u16 version;
+	u16 size;
+
+	u8 bus;
+	u8 dev;
+	u8 func;
+	u8 reserved0;
+
+	u16 base_comid;
+	u16 reserved1;
+
+	u8 password_len;
+	u8 reserved2[3];
+	u8 password[OPAL_S3_MAX_PASSWORD_LEN];
+} __packed;
+
+#endif
diff --git a/src/security/Kconfig b/src/security/Kconfig
index abbd0b86b8..b2f08e46dd 100644
--- a/src/security/Kconfig
+++ b/src/security/Kconfig
@@ -6,6 +6,7 @@ source "src/lib/Kconfig.cbfs_verification"
 
 source "src/security/vboot/Kconfig"
 source "src/security/tpm/Kconfig"
+source "src/security/tcg/Kconfig"
 source "src/security/memory/Kconfig"
 source "src/security/intel/Kconfig"
 source "src/security/lockdown/Kconfig"
diff --git a/src/security/Makefile.mk b/src/security/Makefile.mk
index b7922d41d5..8892f0c1de 100644
--- a/src/security/Makefile.mk
+++ b/src/security/Makefile.mk
@@ -5,3 +5,4 @@ subdirs-y += tpm
 subdirs-y += memory
 subdirs-y += intel
 subdirs-y += lockdown
+subdirs-y += tcg
diff --git a/src/security/tcg/Kconfig b/src/security/tcg/Kconfig
new file mode 100644
index 0000000000..78f78f81c2
--- /dev/null
+++ b/src/security/tcg/Kconfig
@@ -0,0 +1,7 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
+menu "TCG storage"
+
+source "src/security/tcg/opal_s3/Kconfig"
+
+endmenu
diff --git a/src/security/tcg/Makefile.mk b/src/security/tcg/Makefile.mk
new file mode 100644
index 0000000000..69fc122b4e
--- /dev/null
+++ b/src/security/tcg/Makefile.mk
@@ -0,0 +1,3 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
+subdirs-y += opal_s3
diff --git a/src/security/tcg/opal_s3/Kconfig b/src/security/tcg/opal_s3/Kconfig
new file mode 100644
index 0000000000..a34f34234e
--- /dev/null
+++ b/src/security/tcg/opal_s3/Kconfig
@@ -0,0 +1,16 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
+config TCG_OPAL_S3_UNLOCK
+	bool "SMM-assisted OPAL NVMe unlock on S3 resume"
+	depends on ARCH_X86
+	depends on HAVE_SMI_HANDLER
+	depends on HAVE_ACPI_RESUME
+	depends on PCI
+	select SMM_OPAL_S3_SCRATCH_CBMEM
+	help
+	  Provide an SMM handler that accepts an OPAL password for the current
+	  sleep cycle and performs an NVMe Security Send/Receive unlock on S3
+	  resume.
+
+	  This is intended to be used by payloads which prompt the user for the
+	  OPAL password and pass it to SMM before entering S3.
diff --git a/src/security/tcg/opal_s3/Makefile.mk b/src/security/tcg/opal_s3/Makefile.mk
new file mode 100644
index 0000000000..dc3225a9ec
--- /dev/null
+++ b/src/security/tcg/opal_s3/Makefile.mk
@@ -0,0 +1 @@
+## SPDX-License-Identifier: GPL-2.0-only

From 537f2acc67e16d96fa06dc20da2e44bbcac85daf Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Wed, 11 Mar 2026 16:06:03 -0500
Subject: [PATCH 3725/3886] vc/intel: add TCG storage core subset for OPAL S3

Add the Intel TCG storage encoder subset used by the OPAL S3 unlock
path. Compiled only when TCG_OPAL_S3_UNLOCK is enabled.

TEST=tested with rest of patch train

Change-Id: Iecbe2011761e913b73541192ccb3a9e9cff6a87c
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91044
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/security/tcg/opal_s3/Makefile.mk          |    5 +
 .../intel/tcg_storage_core/tcg_storage_core.c | 1662 +++++++++++++++++
 .../tcg_storage_core/tcg_storage_core_lib.h   | 1287 +++++++++++++
 .../tcg_storage_core/tcg_storage_core_spec.h  |  389 ++++
 .../intel/tcg_storage_core/tcg_storage_util.c |  901 +++++++++
 .../intel/tcg_storage_core/tcg_uefi_compat.h  |   60 +
 6 files changed, 4304 insertions(+)
 create mode 100644 src/vendorcode/intel/tcg_storage_core/tcg_storage_core.c
 create mode 100644 src/vendorcode/intel/tcg_storage_core/tcg_storage_core_lib.h
 create mode 100644 src/vendorcode/intel/tcg_storage_core/tcg_storage_core_spec.h
 create mode 100644 src/vendorcode/intel/tcg_storage_core/tcg_storage_util.c
 create mode 100644 src/vendorcode/intel/tcg_storage_core/tcg_uefi_compat.h

diff --git a/src/security/tcg/opal_s3/Makefile.mk b/src/security/tcg/opal_s3/Makefile.mk
index dc3225a9ec..625d719d59 100644
--- a/src/security/tcg/opal_s3/Makefile.mk
+++ b/src/security/tcg/opal_s3/Makefile.mk
@@ -1 +1,6 @@
 ## SPDX-License-Identifier: GPL-2.0-only
+
+CPPFLAGS_common-$(CONFIG_TCG_OPAL_S3_UNLOCK) += -I$(src)/vendorcode/intel/tcg_storage_core
+
+smm-$(CONFIG_TCG_OPAL_S3_UNLOCK) += ../../../vendorcode/intel/tcg_storage_core/tcg_storage_core.c
+smm-$(CONFIG_TCG_OPAL_S3_UNLOCK) += ../../../vendorcode/intel/tcg_storage_core/tcg_storage_util.c
diff --git a/src/vendorcode/intel/tcg_storage_core/tcg_storage_core.c b/src/vendorcode/intel/tcg_storage_core/tcg_storage_core.c
new file mode 100644
index 0000000000..ca04c93bd5
--- /dev/null
+++ b/src/vendorcode/intel/tcg_storage_core/tcg_storage_core.c
@@ -0,0 +1,1662 @@
+/* SPDX-License-Identifier: BSD-2-Clause-Patent */
+
+#include "tcg_storage_core_lib.h"
+
+/**
+  Required to be called before calling any other Tcg functions with the TCG_CREATE_STRUCT.
+  Initializes the packet variables to NULL.  Additionally, the buffer will be memset.
+
+  @param [in/out]    CreateStruct    Structure to initialize
+  @param [in]        Buffer          Buffer allocated by client of library.  It will contain the Tcg encoded packet.  This cannot be null.
+  @param [in]        BufferSize      Size of buffer provided.  It cannot be 0.
+
+  @retval       Return the action result.
+**/
+TCG_RESULT
+EFIAPI
+TcgInitTcgCreateStruct (
+  TCG_CREATE_STRUCT  *CreateStruct,
+  VOID               *Buffer,
+  UINT32             BufferSize
+  )
+{
+  NULL_CHECK (CreateStruct);
+  NULL_CHECK (Buffer);
+
+  if (BufferSize == 0) {
+    DEBUG ((DEBUG_INFO, "BufferSize=0\n"));
+    return (TcgResultFailureZeroSize);
+  }
+
+  ZeroMem (Buffer, BufferSize);
+  CreateStruct->BufferSize   = BufferSize;
+  CreateStruct->Buffer       = Buffer;
+  CreateStruct->ComPacket    = NULL;
+  CreateStruct->CurPacket    = NULL;
+  CreateStruct->CurSubPacket = NULL;
+
+  return (TcgResultSuccess);
+}
+
+/**
+
+  Encodes the ComPacket header to the data structure.
+
+  @param[in/out]    CreateStruct          Structure to initialize
+  @param[in]        ComId                 ComID of the Tcg ComPacket.
+  @param[in]        ComIdExtension        ComID Extension of the Tcg ComPacket.
+
+**/
+TCG_RESULT
+EFIAPI
+TcgStartComPacket (
+  TCG_CREATE_STRUCT  *CreateStruct,
+  UINT16             ComId,
+  UINT16             ComIdExtension
+  )
+{
+  NULL_CHECK (CreateStruct);
+
+  if ((CreateStruct->ComPacket != NULL) ||
+      (CreateStruct->CurPacket != NULL) ||
+      (CreateStruct->CurSubPacket != NULL)
+      )
+  {
+    DEBUG ((
+      DEBUG_INFO,
+      "unexpected state: ComPacket=%p CurPacket=%p CurSubPacket=%p\n",
+      CreateStruct->ComPacket,
+      CreateStruct->CurPacket,
+      CreateStruct->CurSubPacket
+      ));
+    return (TcgResultFailureInvalidAction);
+  }
+
+  if (sizeof (TCG_COM_PACKET) > CreateStruct->BufferSize) {
+    DEBUG ((DEBUG_INFO, "BufferSize=0x%X\n", CreateStruct->BufferSize));
+    return (TcgResultFailureBufferTooSmall);
+  }
+
+  CreateStruct->ComPacket                   = (TCG_COM_PACKET *)CreateStruct->Buffer;
+  CreateStruct->ComPacket->ComIDBE          = SwapBytes16 (ComId);
+  CreateStruct->ComPacket->ComIDExtensionBE = SwapBytes16 (ComIdExtension);
+
+  return (TcgResultSuccess);
+}
+
+/**
+
+  Starts a new ComPacket in the Data structure.
+
+  @param [in/out]     CreateStruct    Structure used to add Tcg Packet
+  @param[in]          Tsn             Packet Tper session number
+  @param[in]          Hsn             Packet Host session number
+  @param[in]          SeqNumber       Packet Sequence Number
+  @param[in]          AckType         Packet Acknowledge Type
+  @param[in]          Ack             Packet Acknowledge
+
+**/
+TCG_RESULT
+EFIAPI
+TcgStartPacket (
+  TCG_CREATE_STRUCT  *CreateStruct,
+  UINT32             Tsn,
+  UINT32             Hsn,
+  UINT32             SeqNumber,
+  UINT16             AckType,
+  UINT32             Ack
+  )
+{
+  UINT32  AddedSize;
+
+  NULL_CHECK (CreateStruct);
+
+  AddedSize = 0;
+
+  if ((CreateStruct->ComPacket == NULL) ||
+      (CreateStruct->CurPacket != NULL) ||
+      (CreateStruct->CurSubPacket != NULL)
+      )
+  {
+    DEBUG ((DEBUG_INFO, "unexpected state: ComPacket=%p CurPacket=%p CurSubPacket=%p\n", CreateStruct->ComPacket, CreateStruct->CurPacket, CreateStruct->CurSubPacket));
+    return (TcgResultFailureInvalidAction);
+  }
+
+  // update TCG_COM_PACKET and packet lengths
+  AddedSize = sizeof (TCG_PACKET);
+
+  if ((SwapBytes32 (CreateStruct->ComPacket->LengthBE) + AddedSize) > CreateStruct->BufferSize) {
+    DEBUG ((DEBUG_INFO, "BufferSize=0x%X\n", CreateStruct->BufferSize));
+    return (TcgResultFailureBufferTooSmall);
+  }
+
+  CreateStruct->CurPacket = (TCG_PACKET *)(CreateStruct->ComPacket->Payload + SwapBytes32 (CreateStruct->ComPacket->LengthBE));
+
+  CreateStruct->CurPacket->TperSessionNumberBE = SwapBytes32 (Tsn);
+  CreateStruct->CurPacket->HostSessionNumberBE = SwapBytes32 (Hsn);
+  CreateStruct->CurPacket->SequenceNumberBE    = SwapBytes32 (SeqNumber);
+  CreateStruct->CurPacket->AckTypeBE           = SwapBytes16 (AckType);
+  CreateStruct->CurPacket->AcknowledgementBE   = SwapBytes32 (Ack);
+
+  CreateStruct->CurPacket->LengthBE = 0;
+
+  // update TCG_COM_PACKET Length for next pointer
+  CreateStruct->ComPacket->LengthBE = SwapBytes32 (SwapBytes32 (CreateStruct->ComPacket->LengthBE) + AddedSize);
+
+  return (TcgResultSuccess);
+}
+
+/**
+
+  Starts a new SubPacket in the Data structure.
+
+  @param[in/out]    CreateStruct        Structure used to start Tcg SubPacket
+  @param[in]        Kind                SubPacket kind
+
+**/
+TCG_RESULT
+EFIAPI
+TcgStartSubPacket (
+  TCG_CREATE_STRUCT  *CreateStruct,
+  UINT16             Kind
+  )
+{
+  UINT32  AddedSize;
+
+  NULL_CHECK (CreateStruct);
+
+  AddedSize = 0;
+
+  if ((CreateStruct->ComPacket == NULL) ||
+      (CreateStruct->CurPacket == NULL) ||
+      (CreateStruct->CurSubPacket != NULL)
+      )
+  {
+    DEBUG ((DEBUG_INFO, "unexpected state: ComPacket=%p CurPacket=%p CurSubPacket=%p\n", CreateStruct->ComPacket, CreateStruct->CurPacket, CreateStruct->CurSubPacket));
+    return (TcgResultFailureInvalidAction);
+  }
+
+  AddedSize = sizeof (TCG_SUB_PACKET);
+
+  if ((SwapBytes32 (CreateStruct->ComPacket->LengthBE) + AddedSize) > CreateStruct->BufferSize) {
+    DEBUG ((DEBUG_INFO, "BufferSize=0x%X\n", CreateStruct->BufferSize));
+    return (TcgResultFailureBufferTooSmall);
+  }
+
+  CreateStruct->CurSubPacket         = (TCG_SUB_PACKET *)(CreateStruct->CurPacket->Payload + SwapBytes32 (CreateStruct->CurPacket->LengthBE));
+  CreateStruct->CurSubPacket->KindBE = SwapBytes16 (Kind);
+
+  // update lengths
+  CreateStruct->CurSubPacket->LengthBE = 0;
+
+  // update TCG_COM_PACKET and packet lengths
+  CreateStruct->ComPacket->LengthBE = SwapBytes32 (SwapBytes32 (CreateStruct->ComPacket->LengthBE) + AddedSize);
+  CreateStruct->CurPacket->LengthBE = SwapBytes32 (SwapBytes32 (CreateStruct->CurPacket->LengthBE) + AddedSize);
+
+  return (TcgResultSuccess);
+}
+
+/**
+
+  Ends the current SubPacket in the Data structure.  This function will also perform the 4-byte padding
+  required for Subpackets.
+
+  @param[in/out]       CreateStruct        Structure used to end the current Tcg SubPacket
+
+**/
+TCG_RESULT
+EFIAPI
+TcgEndSubPacket (
+  TCG_CREATE_STRUCT  *CreateStruct
+  )
+{
+  UINT32  PadSize;
+
+  NULL_CHECK (CreateStruct);
+
+  PadSize = 0;
+
+  if ((CreateStruct->ComPacket == NULL) ||
+      (CreateStruct->CurPacket == NULL) ||
+      (CreateStruct->CurSubPacket == NULL)
+      )
+  {
+    DEBUG ((DEBUG_INFO, "unexpected state: ComPacket=%p CurPacket=%p CurSubPacket=%p\n", CreateStruct->ComPacket, CreateStruct->CurPacket, CreateStruct->CurSubPacket));
+    return (TcgResultFailureInvalidAction);
+  }
+
+  // align to 4-byte boundaries, so shift padding
+  // pad Size does not apply to subpacket Length
+  PadSize = TCG_SUBPACKET_ALIGNMENT - (SwapBytes32 (CreateStruct->CurSubPacket->LengthBE) & (TCG_SUBPACKET_ALIGNMENT - 1));
+
+  if (PadSize == TCG_SUBPACKET_ALIGNMENT) {
+    PadSize = 0;
+  }
+
+  if ((SwapBytes32 (CreateStruct->ComPacket->LengthBE) + PadSize) > CreateStruct->BufferSize) {
+    DEBUG ((DEBUG_INFO, "BufferSize=0x%X\n", CreateStruct->BufferSize));
+    return (TcgResultFailureBufferTooSmall);
+  }
+
+  CreateStruct->CurPacket->LengthBE = SwapBytes32 (SwapBytes32 (CreateStruct->CurPacket->LengthBE) + PadSize);
+  CreateStruct->ComPacket->LengthBE = SwapBytes32 (SwapBytes32 (CreateStruct->ComPacket->LengthBE) + PadSize);
+
+  CreateStruct->CurSubPacket = NULL;
+
+  return (TcgResultSuccess);
+}
+
+/**
+
+  Ends the current Packet in the Data structure.
+
+  @param[in/out]       CreateStruct        Structure used to end the current Tcg Packet
+
+**/
+TCG_RESULT
+EFIAPI
+TcgEndPacket (
+  TCG_CREATE_STRUCT  *CreateStruct
+  )
+{
+  NULL_CHECK (CreateStruct);
+
+  if ((CreateStruct->ComPacket == NULL) ||
+      (CreateStruct->CurPacket == NULL) ||
+      (CreateStruct->CurSubPacket != NULL)
+      )
+  {
+    DEBUG ((DEBUG_INFO, "unexpected state: ComPacket=%p CurPacket=%p CurSubPacket=%p\n", CreateStruct->ComPacket, CreateStruct->CurPacket, CreateStruct->CurSubPacket));
+    return (TcgResultFailureInvalidAction);
+  }
+
+  CreateStruct->CurPacket = NULL;
+
+  return (TcgResultSuccess);
+}
+
+/**
+
+  Ends the ComPacket in the Data structure and ret
+
+  @param [in/out]       CreateStruct       Structure used to end the Tcg ComPacket
+  @param [in/out]       Size               Describes the Size of the entire ComPacket (Header and payload). Filled out by function.
+
+**/
+TCG_RESULT
+EFIAPI
+TcgEndComPacket (
+  TCG_CREATE_STRUCT  *CreateStruct,
+  UINT32             *Size
+  )
+{
+  NULL_CHECK (CreateStruct);
+  NULL_CHECK (Size);
+
+  if ((CreateStruct->ComPacket == NULL) ||
+      (CreateStruct->CurPacket != NULL) ||
+      (CreateStruct->CurSubPacket != NULL)
+      )
+  {
+    DEBUG ((DEBUG_INFO, "unexpected state: ComPacket=%p CurPacket=%p CurSubPacket=%p\n", CreateStruct->ComPacket, CreateStruct->CurPacket, CreateStruct->CurSubPacket));
+    return (TcgResultFailureInvalidAction);
+  }
+
+  *Size                   = SwapBytes32 (CreateStruct->ComPacket->LengthBE) + sizeof (*CreateStruct->ComPacket);
+  CreateStruct->ComPacket = NULL;
+
+  return (TcgResultSuccess);
+}
+
+/**
+  Adds raw Data with optional Header
+
+  @param       CreateStruct       The create structure.
+  @param       Header             The header structure.
+  @param       HeaderSize         The header size.
+  @param       Data               The data need to add.
+  @param       DataSize           The data size.
+  @param       ByteSwapData       Whether byte or swap data.
+
+**/
+static TCG_RESULT
+TcgAddRawTokenData (
+  TCG_CREATE_STRUCT  *CreateStruct,
+  const VOID         *Header,
+  UINT8              HeaderSize,
+  const VOID         *Data,
+  UINT32             DataSize,
+  BOOLEAN            ByteSwapData
+  )
+{
+  UINT32       AddedSize;
+  UINT8        *Dest;
+  const UINT8  *DataBytes;
+  UINT32       Index;
+
+  AddedSize = 0;
+  Index     = 0;
+  Dest      = NULL;
+
+  NULL_CHECK (CreateStruct);
+
+  if (((HeaderSize != 0) && (Header == NULL)) ||
+      ((DataSize != 0) && (Data == NULL))
+      )
+  {
+    DEBUG ((DEBUG_INFO, "HeaderSize=0x%X Header=%p DataSize=0x%X Data=%p\n", HeaderSize, Header, DataSize, Data));
+    return (TcgResultFailureNullPointer);
+  }
+
+  if ((CreateStruct->ComPacket == NULL) ||
+      (CreateStruct->CurPacket == NULL) ||
+      (CreateStruct->CurSubPacket == NULL)
+      )
+  {
+    DEBUG ((DEBUG_INFO, "unexpected state: ComPacket=%p CurPacket=%p CurSubPacket=%p\n", CreateStruct->ComPacket, CreateStruct->CurPacket, CreateStruct->CurSubPacket));
+    return (TcgResultFailureInvalidAction);
+  }
+
+  // verify there is enough Buffer Size
+  AddedSize = HeaderSize + DataSize;
+  if ((SwapBytes32 (CreateStruct->ComPacket->LengthBE) + AddedSize) > CreateStruct->BufferSize) {
+    return (TcgResultFailureBufferTooSmall);
+  }
+
+  // Get a pointer to where the new bytes should go
+  Dest = CreateStruct->ComPacket->Payload + SwapBytes32 (CreateStruct->ComPacket->LengthBE);
+
+  switch (HeaderSize) {
+    case sizeof (TCG_SIMPLE_TOKEN_SHORT_ATOM):
+    case sizeof (TCG_SIMPLE_TOKEN_MEDIUM_ATOM):
+    case sizeof (TCG_SIMPLE_TOKEN_LONG_ATOM):
+      CopyMem (Dest, Header, HeaderSize);
+      Dest += HeaderSize;
+      break;
+    case 0: // no Header is valid
+      break;
+    // invalid Header Size
+    default:
+      DEBUG ((DEBUG_INFO, "unsupported HeaderSize=%u\n", HeaderSize));
+      return TcgResultFailure;
+  }
+
+  // copy the Data bytes
+  if (ByteSwapData) {
+    DataBytes = (const UINT8 *)Data;
+    for (Index = 0; Index < DataSize; Index++) {
+      Dest[Index] = DataBytes[DataSize - 1 - Index];
+    }
+  } else {
+    CopyMem (Dest, Data, DataSize);
+  }
+
+  // Update all the packet sizes
+  CreateStruct->ComPacket->LengthBE    = SwapBytes32 (SwapBytes32 (CreateStruct->ComPacket->LengthBE) + AddedSize);
+  CreateStruct->CurPacket->LengthBE    = SwapBytes32 (SwapBytes32 (CreateStruct->CurPacket->LengthBE) + AddedSize);
+  CreateStruct->CurSubPacket->LengthBE = SwapBytes32 (SwapBytes32 (CreateStruct->CurSubPacket->LengthBE) + AddedSize);
+
+  return (TcgResultSuccess);
+}
+
+/**
+
+  Adds a single raw token byte to the Data structure.
+
+  @param[in/out]   CreateStruct        Structure used to add the byte
+  @param[in]       Byte                Byte to add
+
+**/
+TCG_RESULT
+EFIAPI
+TcgAddRawByte (
+  TCG_CREATE_STRUCT  *CreateStruct,
+  UINT8              Byte
+  )
+{
+  return TcgAddRawTokenData (CreateStruct, NULL, 0, &Byte, 1, FALSE);
+}
+
+/**
+   simple tokens - atoms: tiny, short, medium, long and empty atoms.
+   tiny atom can be a signed or unsigned integer.
+   short, medium, long can be a signed or unsigned integer OR a complete or non-final byte sequence.
+
+  @param       CreateStruct       The create structure.
+  @param       Data               The data need to add.
+  @param       DataSize           The data size.
+  @param       ByteOrInt,         Data format is byte or int.
+  @param       SignOrCont         sign or cont.
+
+
+**/
+static TCG_RESULT
+TcgAddAtom (
+  TCG_CREATE_STRUCT  *CreateStruct,
+  const VOID         *Data,
+  UINT32             DataSize,
+  UINT8              ByteOrInt,
+  UINT8              SignOrCont
+  )
+{
+  const UINT8                   *DataBytes;
+  TCG_SIMPLE_TOKEN_TINY_ATOM    TinyAtom;
+  TCG_SIMPLE_TOKEN_SHORT_ATOM   ShortAtom;
+  TCG_SIMPLE_TOKEN_MEDIUM_ATOM  MediumAtom;
+  TCG_SIMPLE_TOKEN_LONG_ATOM    LongAtom;
+
+  NULL_CHECK (CreateStruct);
+
+  if (DataSize == 0) {
+    if (ByteOrInt == TCG_ATOM_TYPE_INTEGER) {
+      DEBUG ((DEBUG_INFO, "0-Size integer not allowed\n"));
+      return TcgResultFailure;
+    }
+  } else {
+    // if DataSize != 0, Data must be valid
+    NULL_CHECK (Data);
+  }
+
+  // encode Data using the shortest possible atom
+  DataBytes = (const UINT8 *)Data;
+  if ((DataSize == 1) &&
+      (ByteOrInt == TCG_ATOM_TYPE_INTEGER) &&
+      (((SignOrCont != 0) && ((TCG_TOKEN_TINYATOM_SIGNED_MIN_VALUE <= *(INT8 *)Data) && (*(INT8 *)Data <= TCG_TOKEN_TINYATOM_SIGNED_MAX_VALUE))) ||
+       ((SignOrCont == 0) && ((*DataBytes <= TCG_TOKEN_TINYATOM_UNSIGNED_MAX_VALUE))))
+      )
+  {
+    TinyAtom.TinyAtomBits.IsZero = 0;
+    TinyAtom.TinyAtomBits.Sign   = SignOrCont;
+    TinyAtom.TinyAtomBits.Data   = *DataBytes & TCG_TOKEN_TINYATOM_UNSIGNED_MAX_VALUE;
+    return TcgAddRawTokenData (CreateStruct, NULL, 0, (UINT8 *)&TinyAtom, sizeof (TCG_SIMPLE_TOKEN_TINY_ATOM), FALSE);
+  }
+
+  if (DataSize <= TCG_TOKEN_SHORTATOM_MAX_BYTE_SIZE) {
+    ShortAtom.ShortAtomBits.IsOne      = 1;
+    ShortAtom.ShortAtomBits.IsZero     = 0;
+    ShortAtom.ShortAtomBits.ByteOrInt  = ByteOrInt;
+    ShortAtom.ShortAtomBits.SignOrCont = SignOrCont;
+    ShortAtom.ShortAtomBits.Length     = DataSize & 0x0F;
+    return TcgAddRawTokenData (CreateStruct, &ShortAtom, sizeof (TCG_SIMPLE_TOKEN_SHORT_ATOM), Data, DataSize, ByteOrInt == TCG_ATOM_TYPE_INTEGER);
+  }
+
+  if (DataSize <= TCG_TOKEN_MEDIUMATOM_MAX_BYTE_SIZE) {
+    MediumAtom.MediumAtomBits.IsOne1     = 1;
+    MediumAtom.MediumAtomBits.IsOne2     = 1;
+    MediumAtom.MediumAtomBits.IsZero     = 0;
+    MediumAtom.MediumAtomBits.ByteOrInt  = ByteOrInt;
+    MediumAtom.MediumAtomBits.SignOrCont = SignOrCont;
+    MediumAtom.MediumAtomBits.LengthLow  = DataSize & 0xFF;
+    MediumAtom.MediumAtomBits.LengthHigh = (DataSize >> TCG_MEDIUM_ATOM_LENGTH_HIGH_SHIFT) & TCG_MEDIUM_ATOM_LENGTH_HIGH_MASK;
+    return TcgAddRawTokenData (CreateStruct, &MediumAtom, sizeof (TCG_SIMPLE_TOKEN_MEDIUM_ATOM), Data, DataSize, ByteOrInt == TCG_ATOM_TYPE_INTEGER);
+  }
+
+  LongAtom.LongAtomBits.IsOne1     = 1;
+  LongAtom.LongAtomBits.IsOne2     = 1;
+  LongAtom.LongAtomBits.IsOne3     = 1;
+  LongAtom.LongAtomBits.IsZero     = 0;
+  LongAtom.LongAtomBits.ByteOrInt  = ByteOrInt;
+  LongAtom.LongAtomBits.SignOrCont = SignOrCont;
+  LongAtom.LongAtomBits.LengthLow  = DataSize & 0xFF;
+  LongAtom.LongAtomBits.LengthMid  = (DataSize >> TCG_LONG_ATOM_LENGTH_MID_SHIFT) & 0xFF;
+  LongAtom.LongAtomBits.LengthHigh = (DataSize >> TCG_LONG_ATOM_LENGTH_HIGH_SHIFT) & 0xFF;
+  return TcgAddRawTokenData (CreateStruct, &LongAtom, sizeof (TCG_SIMPLE_TOKEN_LONG_ATOM), Data, DataSize, ByteOrInt == TCG_ATOM_TYPE_INTEGER);
+}
+
+/**
+
+  Adds the Data parameter as a byte sequence to the Data structure.
+
+  @param[in/out]    CreateStruct      Structure used to add the byte sequence
+  @param[in]        Data              Byte sequence that will be encoded and copied into Data structure
+  @param[in]        DataSize          Length of Data provided
+  @param[in]        Continued         TRUE if byte sequence is continued or
+                                      FALSE if the Data contains the entire byte sequence to be encoded
+
+**/
+TCG_RESULT
+EFIAPI
+TcgAddByteSequence (
+  TCG_CREATE_STRUCT  *CreateStruct,
+  const VOID         *Data,
+  UINT32             DataSize,
+  BOOLEAN            Continued
+  )
+{
+  return TcgAddAtom (CreateStruct, Data, DataSize, TCG_ATOM_TYPE_BYTE, Continued ? 1 : 0);
+}
+
+/**
+
+  Adds an arbitrary-Length integer to the Data structure.
+  The integer will be encoded using the shortest possible atom.
+
+  @param[in/out]     CreateStruct      Structure used to add the integer
+  @param[in]         Data              Integer in host byte order that will be encoded and copied into Data structure
+  @param[in]         DataSize          Length in bytes of the Data provided
+  @param[in]         SignedInteger     TRUE if the integer is signed or FALSE if the integer is unsigned
+
+**/
+TCG_RESULT
+EFIAPI
+TcgAddInteger (
+  TCG_CREATE_STRUCT  *CreateStruct,
+  const VOID         *Data,
+  UINT32             DataSize,
+  BOOLEAN            SignedInteger
+  )
+{
+  const UINT8  *DataBytes;
+  UINT32       ActualDataSize;
+  BOOLEAN      ValueIsNegative;
+
+  NULL_CHECK (CreateStruct);
+  NULL_CHECK (Data);
+
+  if (DataSize == 0) {
+    DEBUG ((DEBUG_INFO, "invalid DataSize=0\n"));
+    return TcgResultFailure;
+  }
+
+  DataBytes = (const UINT8 *)Data;
+
+  // integer should be represented by smallest atom possible
+  // so calculate real Data Size
+  ValueIsNegative = SignedInteger && DataBytes[DataSize - 1] & 0x80;
+
+  // assumes native Data is little endian
+  // shorten Data to smallest byte representation
+  for (ActualDataSize = DataSize; ActualDataSize > 1; ActualDataSize--) {
+    // ignore sign extended  FFs
+    if (ValueIsNegative && (DataBytes[ActualDataSize - 1] != 0xFF)) {
+      break;
+    } else if (!ValueIsNegative && (DataBytes[ActualDataSize - 1] != 0)) {
+      // ignore extended 00s
+      break;
+    }
+  }
+
+  return TcgAddAtom (CreateStruct, Data, ActualDataSize, TCG_ATOM_TYPE_INTEGER, SignedInteger ? 1 : 0);
+}
+
+/**
+  Adds an 8-bit unsigned integer to the Data structure.
+
+  @param[in/out]       CreateStruct        Structure used to add the integer
+  @param[in]           Value               Integer Value to add
+
+**/
+TCG_RESULT
+EFIAPI
+TcgAddUINT8 (
+  TCG_CREATE_STRUCT  *CreateStruct,
+  UINT8              Value
+  )
+{
+  return TcgAddInteger (CreateStruct, &Value, sizeof (Value), FALSE);
+}
+
+/**
+
+  Adds a 16-bit unsigned integer to the Data structure.
+
+  @param[in/out]       CreateStruct        Structure used to add the integer
+  @param[in]           Value               Integer Value to add
+
+**/
+TCG_RESULT
+EFIAPI
+TcgAddUINT16 (
+  TCG_CREATE_STRUCT  *CreateStruct,
+  UINT16             Value
+  )
+{
+  return TcgAddInteger (CreateStruct, &Value, sizeof (Value), FALSE);
+}
+
+/**
+
+  Adds a 32-bit unsigned integer to the Data structure.
+
+  @param[in/out]        CreateStruct        Structure used to add the integer
+  @param[in]            Value               Integer Value to add
+
+**/
+TCG_RESULT
+EFIAPI
+TcgAddUINT32 (
+  TCG_CREATE_STRUCT  *CreateStruct,
+  UINT32             Value
+  )
+{
+  return TcgAddInteger (CreateStruct, &Value, sizeof (Value), FALSE);
+}
+
+/**
+
+  Adds a 64-bit unsigned integer to the Data structure.
+
+  @param[in/out]      CreateStruct        Structure used to add the integer
+  @param[in]          Value               Integer Value to add
+
+**/
+TCG_RESULT
+EFIAPI
+TcgAddUINT64 (
+  TCG_CREATE_STRUCT  *CreateStruct,
+  UINT64             Value
+  )
+{
+  return TcgAddInteger (CreateStruct, &Value, sizeof (Value), FALSE);
+}
+
+/**
+  Adds a BOOLEAN to the Data structure.
+
+  @param[in/out]       CreateStruct     Structure used to add the integer
+  @param[in]           Value              BOOLEAN Value to add
+
+**/
+TCG_RESULT
+EFIAPI
+TcgAddBOOLEAN (
+  TCG_CREATE_STRUCT  *CreateStruct,
+  BOOLEAN            Value
+  )
+{
+  return TcgAddInteger (CreateStruct, &Value, sizeof (Value), FALSE);
+}
+
+/**
+  Add tcg uid info.
+
+  @param [in/out]       CreateStruct       Structure used to add the integer
+  @param                Uid                Input uid info.
+
+  @retval   return the action result.
+
+**/
+TCG_RESULT
+EFIAPI
+TcgAddTcgUid (
+  TCG_CREATE_STRUCT  *CreateStruct,
+  TCG_UID            Uid
+  )
+{
+  return TcgAddByteSequence (CreateStruct, &Uid, sizeof (TCG_UID), FALSE);
+}
+
+/**
+  Add start list.
+
+  @param [in/out]       CreateStruct       Structure used to add the integer
+
+  @retval   return the action result.
+
+**/
+TCG_RESULT
+EFIAPI
+TcgAddStartList (
+  TCG_CREATE_STRUCT  *CreateStruct
+  )
+{
+  return TcgAddRawByte (CreateStruct, TCG_TOKEN_STARTLIST);
+}
+
+/**
+  Add end list.
+
+  @param [in/out]       CreateStruct       Structure used to add the integer
+
+  @retval   return the action result.
+
+**/
+TCG_RESULT
+EFIAPI
+TcgAddEndList (
+  TCG_CREATE_STRUCT  *CreateStruct
+  )
+{
+  return TcgAddRawByte (CreateStruct, TCG_TOKEN_ENDLIST);
+}
+
+/**
+  Add start name.
+
+  @param [in/out]       CreateStruct       Structure used to add the integer
+
+  @retval   return the action result.
+
+**/
+TCG_RESULT
+EFIAPI
+TcgAddStartName (
+  TCG_CREATE_STRUCT  *CreateStruct
+  )
+{
+  return TcgAddRawByte (CreateStruct, TCG_TOKEN_STARTNAME);
+}
+
+/**
+  Add end name.
+
+  @param [in/out]       CreateStruct       Structure used to add the integer
+
+  @retval   return the action result.
+
+**/
+TCG_RESULT
+EFIAPI
+TcgAddEndName (
+  TCG_CREATE_STRUCT  *CreateStruct
+  )
+{
+  return TcgAddRawByte (CreateStruct, TCG_TOKEN_ENDNAME);
+}
+
+/**
+  Add end call.
+
+  @param [in/out]       CreateStruct       Structure used to add the integer
+
+  @retval   return the action result.
+
+**/
+TCG_RESULT
+EFIAPI
+TcgAddCall (
+  TCG_CREATE_STRUCT  *CreateStruct
+  )
+{
+  return TcgAddRawByte (CreateStruct, TCG_TOKEN_CALL);
+}
+
+/**
+  Add end of data.
+
+  @param [in/out]       CreateStruct       Structure used to add the integer
+
+  @retval   return the action result.
+
+**/
+TCG_RESULT
+EFIAPI
+TcgAddEndOfData (
+  TCG_CREATE_STRUCT  *CreateStruct
+  )
+{
+  return TcgAddRawByte (CreateStruct, TCG_TOKEN_ENDDATA);
+}
+
+/**
+  Add end of session.
+
+  @param [in/out]       CreateStruct       Structure used to add the integer
+
+  @retval   return the action result.
+
+**/
+TCG_RESULT
+EFIAPI
+TcgAddEndOfSession (
+  TCG_CREATE_STRUCT  *CreateStruct
+  )
+{
+  return TcgAddRawByte (CreateStruct, TCG_TOKEN_ENDSESSION);
+}
+
+/**
+  Add start transaction.
+
+  @param [in/out]       CreateStruct       Structure used to add the integer
+
+  @retval   return the action result.
+
+**/
+TCG_RESULT
+EFIAPI
+TcgAddStartTransaction (
+  TCG_CREATE_STRUCT  *CreateStruct
+  )
+{
+  return TcgAddRawByte (CreateStruct, TCG_TOKEN_STARTTRANSACTION);
+}
+
+/**
+  Add end transaction.
+
+  @param [in/out]       CreateStruct       Structure used to add the integer
+
+  @retval   return the action result.
+
+**/
+TCG_RESULT
+EFIAPI
+TcgAddEndTransaction (
+  TCG_CREATE_STRUCT  *CreateStruct
+  )
+{
+  return TcgAddRawByte (CreateStruct, TCG_TOKEN_ENDTRANSACTION);
+}
+
+/**
+  Initial the tcg parse structure.
+
+  @param    ParseStruct    Input parse structure.
+  @param    Buffer         Input buffer data.
+  @param    BufferSize     Input buffer size.
+
+  @retval   return the action result.
+
+**/
+TCG_RESULT
+EFIAPI
+TcgInitTcgParseStruct (
+  TCG_PARSE_STRUCT  *ParseStruct,
+  const VOID        *Buffer,
+  UINT32            BufferSize
+  )
+{
+  UINT32  ComPacketLength;
+  UINT32  PacketLength;
+
+  NULL_CHECK (ParseStruct);
+  NULL_CHECK (Buffer);
+
+  if (BufferSize < sizeof (TCG_COM_PACKET)) {
+    return (TcgResultFailureBufferTooSmall);
+  }
+
+  ParseStruct->ComPacket = (TCG_COM_PACKET *)Buffer;
+
+  ComPacketLength = SwapBytes32 (ParseStruct->ComPacket->LengthBE);
+
+  if ((BufferSize - sizeof (TCG_COM_PACKET)) < ComPacketLength) {
+    DEBUG ((DEBUG_INFO, "Buffer %u too small for ComPacket %u\n", BufferSize, ComPacketLength));
+    return (TcgResultFailureBufferTooSmall);
+  }
+
+  ParseStruct->BufferSize = BufferSize;
+  ParseStruct->Buffer     = Buffer;
+
+  ParseStruct->CurPacket    = NULL;
+  ParseStruct->CurSubPacket = NULL;
+  ParseStruct->CurPtr       = NULL;
+
+  // if payload > 0, then must have a packet
+  if (ComPacketLength != 0) {
+    if (ComPacketLength < sizeof (TCG_PACKET)) {
+      DEBUG ((DEBUG_INFO, "ComPacket too small for Packet\n"));
+      return (TcgResultFailureBufferTooSmall);
+    }
+
+    ParseStruct->CurPacket = (TCG_PACKET *)ParseStruct->ComPacket->Payload;
+
+    PacketLength = SwapBytes32 (ParseStruct->CurPacket->LengthBE);
+
+    if (PacketLength > 0) {
+      if (PacketLength < sizeof (TCG_SUB_PACKET)) {
+        DEBUG ((DEBUG_INFO, "Packet too small for SubPacket\n"));
+        return (TcgResultFailureBufferTooSmall);
+      }
+
+      ParseStruct->CurSubPacket = (TCG_SUB_PACKET *)ParseStruct->CurPacket->Payload;
+    }
+  }
+
+  // TODO should check for method status list at this point?
+
+  return (TcgResultSuccess);
+}
+
+/**
+  Get next token info.
+
+  @param    ParseStruct      Input parse structure info.
+  @param    TcgToken         return the tcg token info.
+
+  @retval   return the action result.
+
+**/
+TCG_RESULT
+EFIAPI
+TcgGetNextToken (
+  TCG_PARSE_STRUCT  *ParseStruct,
+  TCG_TOKEN         *TcgToken
+  )
+{
+  const UINT8                         *EndOfSubPacket;
+  UINT8                               *TokenEnd;
+  UINT8                               Hdr;
+  TCG_SIMPLE_TOKEN_SHORT_ATOM         *TmpShort;
+  const TCG_SIMPLE_TOKEN_MEDIUM_ATOM  *TmpMed;
+  const TCG_SIMPLE_TOKEN_LONG_ATOM    *TmpLong;
+
+  NULL_CHECK (ParseStruct);
+  NULL_CHECK (TcgToken);
+
+  if ((ParseStruct->ComPacket == NULL) ||
+      (ParseStruct->CurPacket == NULL) ||
+      (ParseStruct->CurSubPacket == NULL)
+      )
+  {
+    DEBUG ((DEBUG_INFO, "unexpected state: ComPacket=%p CurPacket=%p CurSubPacket=%p\n", ParseStruct->ComPacket, ParseStruct->CurPacket, ParseStruct->CurSubPacket));
+    return TcgResultFailureInvalidAction;
+  }
+
+  // initial call, start at sub packet
+  if (ParseStruct->CurPtr == NULL) {
+    ParseStruct->CurPtr = ParseStruct->CurSubPacket->Payload;
+  }
+
+  EndOfSubPacket = ParseStruct->CurSubPacket->Payload + SwapBytes32 (ParseStruct->CurSubPacket->LengthBE);
+  TokenEnd       = NULL;
+
+  // confirmed that subpacket Length falls within end of Buffer and TCG_COM_PACKET,
+  // so simply need to verify the loop stays within current subpacket
+  if (ParseStruct->CurPtr >= EndOfSubPacket) {
+    DEBUG ((DEBUG_INFO, "ParseStruct->CurPtr >= EndOfSubPacket\n"));
+    return (TcgResultFailureEndBuffer);
+  }
+
+  Hdr                = *ParseStruct->CurPtr;
+  TcgToken->HdrStart = ParseStruct->CurPtr;
+
+  // Tiny Atom range
+  if (Hdr <= 0x7F) {
+    // tiny atom Header is only 1 byte, so don't need to verify Size before cast and access
+    TcgToken->Type = TcgTokenTypeTinyAtom;
+
+    TokenEnd = TcgToken->HdrStart + sizeof (TCG_SIMPLE_TOKEN_TINY_ATOM);
+
+    // verify caller will have enough Size to reference token
+    if (TokenEnd >= EndOfSubPacket) {
+      DEBUG ((DEBUG_INFO, "Tiny Atom TokenEnd >= EndOfSubPacket\n"));
+      return (TcgResultFailureEndBuffer);
+    }
+  }
+  // Short Atom Range
+  else if ((0x80 <= Hdr) && (Hdr <= 0xBF)) {
+    // short atom Header is only 1 byte, so don't need to verify Size before cast and access
+    TmpShort       = (TCG_SIMPLE_TOKEN_SHORT_ATOM *)(ParseStruct->CurPtr);
+    TcgToken->Type = TcgTokenTypeShortAtom;
+
+    TokenEnd = (TcgToken->HdrStart + sizeof (TCG_SIMPLE_TOKEN_SHORT_ATOM) + TmpShort->ShortAtomBits.Length);
+
+    // verify caller will have enough Size to reference token
+    if (TokenEnd >= EndOfSubPacket) {
+      DEBUG ((DEBUG_INFO, "Short Atom TokenEnd >= EndOfSubPacket\n"));
+      return (TcgResultFailureEndBuffer);
+    }
+  }
+  // Medium Atom Range
+  else if ((0xC0 <= Hdr) && (Hdr <= 0xDF)) {
+    if (TcgToken->HdrStart + sizeof (TCG_SIMPLE_TOKEN_MEDIUM_ATOM) >= EndOfSubPacket) {
+      return (TcgResultFailureEndBuffer);
+    }
+
+    TmpMed         = (const TCG_SIMPLE_TOKEN_MEDIUM_ATOM *)ParseStruct->CurPtr;
+    TcgToken->Type = TcgTokenTypeMediumAtom;
+    TokenEnd       = TcgToken->HdrStart + sizeof (TCG_SIMPLE_TOKEN_MEDIUM_ATOM) +
+                     ((TmpMed->MediumAtomBits.LengthHigh << TCG_MEDIUM_ATOM_LENGTH_HIGH_SHIFT) |
+                      TmpMed->MediumAtomBits.LengthLow);
+
+    // verify caller will have enough Size to reference token
+    if (TokenEnd >= EndOfSubPacket) {
+      DEBUG ((DEBUG_INFO, "Medium Atom TokenEnd >= EndOfSubPacket\n"));
+      return (TcgResultFailureEndBuffer);
+    }
+  }
+  // Long Atom Range
+  else if ((0xE0 <= Hdr) && (Hdr <= 0xE3)) {
+    if (TcgToken->HdrStart + sizeof (TCG_SIMPLE_TOKEN_LONG_ATOM) >= EndOfSubPacket) {
+      return (TcgResultFailureEndBuffer);
+    }
+
+    TmpLong        = (const TCG_SIMPLE_TOKEN_LONG_ATOM *)ParseStruct->CurPtr;
+    TcgToken->Type = TcgTokenTypeLongAtom;
+
+    TokenEnd = TcgToken->HdrStart + sizeof (TCG_SIMPLE_TOKEN_LONG_ATOM) +
+               ((TmpLong->LongAtomBits.LengthHigh << TCG_LONG_ATOM_LENGTH_HIGH_SHIFT) |
+                (TmpLong->LongAtomBits.LengthMid << TCG_LONG_ATOM_LENGTH_MID_SHIFT)   |
+                TmpLong->LongAtomBits.LengthLow);
+
+    // verify caller will have enough Size to reference token
+    if (TokenEnd >= EndOfSubPacket) {
+      DEBUG ((DEBUG_INFO, "Long Atom TokenEnd >= EndOfSubPacket\n"));
+      return (TcgResultFailureEndBuffer);
+    }
+  } else {
+    // single byte tokens
+    switch (Hdr) {
+      case TCG_TOKEN_STARTLIST:
+        TcgToken->Type = TcgTokenTypeStartList;
+        break;
+      case TCG_TOKEN_ENDLIST:
+        TcgToken->Type = TcgTokenTypeEndList;
+        break;
+      case TCG_TOKEN_STARTNAME:
+        TcgToken->Type = TcgTokenTypeStartName;
+        break;
+      case TCG_TOKEN_ENDNAME:
+        TcgToken->Type = TcgTokenTypeEndName;
+        break;
+      case TCG_TOKEN_CALL:
+        TcgToken->Type = TcgTokenTypeCall;
+        break;
+      case TCG_TOKEN_ENDDATA:
+        TcgToken->Type = TcgTokenTypeEndOfData;
+        break;
+      case TCG_TOKEN_ENDSESSION:
+        TcgToken->Type = TcgTokenTypeEndOfSession;
+        break;
+      case TCG_TOKEN_STARTTRANSACTION:
+        TcgToken->Type = TcgTokenTypeStartTransaction;
+        break;
+      case TCG_TOKEN_ENDTRANSACTION:
+        TcgToken->Type = TcgTokenTypeEndTransaction;
+        break;
+      case TCG_TOKEN_EMPTY:
+        TcgToken->Type = TcgTokenTypeEmptyAtom;
+        break;
+      default:
+        DEBUG ((DEBUG_INFO, "WARNING: reserved token Type 0x%02X\n", Hdr));
+        TcgToken->Type = TcgTokenTypeReserved;
+        break;
+    }
+
+    ParseStruct->CurPtr++;
+    TokenEnd = TcgToken->HdrStart + 1;
+  }
+
+  // increment curptr for next call
+  ParseStruct->CurPtr = TokenEnd;
+  return (TcgResultSuccess);
+}
+
+/**
+  Get atom info.
+
+  @param    TcgToken          Input token info.
+  @param    HeaderLength      return the header length.
+  @param    DataLength        return the data length.
+  @param    ByteOrInt         return the atom Type.
+  @param    SignOrCont        return the sign or count info.
+
+  @retval   return the action result.
+
+**/
+TCG_RESULT
+EFIAPI
+TcgGetAtomInfo (
+  const TCG_TOKEN  *TcgToken,
+  UINT32           *HeaderLength,
+  UINT32           *DataLength,
+  UINT8            *ByteOrInt,
+  UINT8            *SignOrCont
+  )
+{
+  TCG_SIMPLE_TOKEN_TINY_ATOM    *TinyAtom;
+  TCG_SIMPLE_TOKEN_SHORT_ATOM   *ShortAtom;
+  TCG_SIMPLE_TOKEN_MEDIUM_ATOM  *MediumAtom;
+  TCG_SIMPLE_TOKEN_LONG_ATOM    *LongAtom;
+
+  NULL_CHECK (TcgToken);
+  NULL_CHECK (HeaderLength);
+  NULL_CHECK (DataLength);
+  NULL_CHECK (ByteOrInt);
+  NULL_CHECK (SignOrCont);
+
+  switch (TcgToken->Type) {
+    case TcgTokenTypeTinyAtom:
+    {
+      TinyAtom      = (TCG_SIMPLE_TOKEN_TINY_ATOM *)TcgToken->HdrStart;
+      *ByteOrInt    = TCG_ATOM_TYPE_INTEGER;
+      *SignOrCont   = TinyAtom->TinyAtomBits.Sign;
+      *HeaderLength = 0;
+      *DataLength   = 0;   // tiny atom must be handled as a special case - Header and Data in the same byte
+      return TcgResultSuccess;
+    }
+
+    case TcgTokenTypeShortAtom:
+    {
+      ShortAtom     = (TCG_SIMPLE_TOKEN_SHORT_ATOM *)TcgToken->HdrStart;
+      *ByteOrInt    = ShortAtom->ShortAtomBits.ByteOrInt;
+      *SignOrCont   = ShortAtom->ShortAtomBits.SignOrCont;
+      *HeaderLength = sizeof (TCG_SIMPLE_TOKEN_SHORT_ATOM);
+      *DataLength   = ShortAtom->ShortAtomBits.Length;
+      return TcgResultSuccess;
+    }
+
+    case TcgTokenTypeMediumAtom:
+    {
+      MediumAtom    = (TCG_SIMPLE_TOKEN_MEDIUM_ATOM *)TcgToken->HdrStart;
+      *ByteOrInt    = MediumAtom->MediumAtomBits.ByteOrInt;
+      *SignOrCont   = MediumAtom->MediumAtomBits.SignOrCont;
+      *HeaderLength = sizeof (TCG_SIMPLE_TOKEN_MEDIUM_ATOM);
+      *DataLength   = (MediumAtom->MediumAtomBits.LengthHigh << TCG_MEDIUM_ATOM_LENGTH_HIGH_SHIFT) | MediumAtom->MediumAtomBits.LengthLow;
+      return TcgResultSuccess;
+    }
+
+    case TcgTokenTypeLongAtom:
+    {
+      LongAtom      = (TCG_SIMPLE_TOKEN_LONG_ATOM *)TcgToken->HdrStart;
+      *ByteOrInt    = LongAtom->LongAtomBits.ByteOrInt;
+      *SignOrCont   = LongAtom->LongAtomBits.SignOrCont;
+      *HeaderLength = sizeof (TCG_SIMPLE_TOKEN_LONG_ATOM);
+      *DataLength   = (LongAtom->LongAtomBits.LengthHigh << TCG_LONG_ATOM_LENGTH_HIGH_SHIFT) |
+                      (LongAtom->LongAtomBits.LengthMid << TCG_LONG_ATOM_LENGTH_MID_SHIFT) |
+                      LongAtom->LongAtomBits.LengthLow;
+      return TcgResultSuccess;
+    }
+
+    default:
+      DEBUG ((DEBUG_INFO, "Token Type is not simple atom (%d)\n", TcgToken->Type));
+      return (TcgResultFailureInvalidType);
+  }
+}
+
+/**
+  Get token specified value.
+
+  @param    TcgToken   Input token info.
+  @param    Value      return the value.
+
+  @retval   return the action result.
+
+**/
+TCG_RESULT
+EFIAPI
+TcgGetTokenUINT64 (
+  const TCG_TOKEN  *TcgToken,
+  UINT64           *Value
+  )
+{
+  UINT32                      HdrLength;
+  UINT32                      DataLength;
+  UINT8                       ByteOrInt;
+  UINT8                       IsSigned;
+  TCG_SIMPLE_TOKEN_TINY_ATOM  *TmpTiny;
+  const UINT8                 *Data;
+  UINT32                      Index;
+
+  NULL_CHECK (TcgToken);
+  NULL_CHECK (Value);
+
+  Index  = 0;
+  *Value = 0;
+  ERROR_CHECK (TcgGetAtomInfo (TcgToken, &HdrLength, &DataLength, &ByteOrInt, &IsSigned));
+
+  if (ByteOrInt != TCG_ATOM_TYPE_INTEGER) {
+    DEBUG ((DEBUG_INFO, "Invalid Type, expected integer not byte sequence\n"));
+    return TcgResultFailureInvalidType;
+  }
+
+  if (IsSigned != 0) {
+    DEBUG ((DEBUG_INFO, "Integer is signed, expected unsigned\n"));
+    return TcgResultFailureInvalidType;
+  }
+
+  // special case for tiny atom
+  // Header and Data are in one byte, so extract only the Data bitfield
+  if (TcgToken->Type == TcgTokenTypeTinyAtom) {
+    TmpTiny = (TCG_SIMPLE_TOKEN_TINY_ATOM *)TcgToken->HdrStart;
+    *Value  = TmpTiny->TinyAtomBits.Data;
+    return TcgResultSuccess;
+  }
+
+  if (DataLength > sizeof (UINT64)) {
+    DEBUG ((DEBUG_INFO, "Length %d is greater than Size of UINT64\n", DataLength));
+    return TcgResultFailureBufferTooSmall;
+  }
+
+  // read big-endian integer
+  Data = TcgToken->HdrStart + HdrLength;
+  for (Index = 0; Index < DataLength; Index++) {
+    *Value = LShiftU64 (*Value, 8) | Data[Index];
+  }
+
+  return TcgResultSuccess;
+}
+
+/**
+  Get token byte sequence.
+
+  @param    TcgToken   Input token info.
+  @param    Length     Input the length info.
+
+  @retval   Return the value data.
+
+**/
+UINT8 *
+EFIAPI
+TcgGetTokenByteSequence (
+  const TCG_TOKEN  *TcgToken,
+  UINT32           *Length
+  )
+{
+  UINT32  HdrLength;
+  UINT8   ByteOrInt;
+  UINT8   SignOrCont;
+
+  if ((TcgToken == NULL) || (Length == NULL)) {
+    return NULL;
+  }
+
+  *Length = 0;
+  if (TcgGetAtomInfo (TcgToken, &HdrLength, Length, &ByteOrInt, &SignOrCont) != TcgResultSuccess) {
+    DEBUG ((DEBUG_INFO, "Failed to get simple token info\n"));
+    return NULL;
+  }
+
+  if (ByteOrInt != TCG_ATOM_TYPE_BYTE) {
+    DEBUG ((DEBUG_INFO, "Invalid Type, expected byte sequence not integer\n"));
+    return NULL;
+  }
+
+  return (TcgToken->HdrStart + HdrLength);
+}
+
+/**
+  Get next specify value.
+
+  @param    ParseStruct   Input parse structure.
+  @param    Value         Return value.
+
+  @retval   return the action result.
+
+**/
+TCG_RESULT
+EFIAPI
+TcgGetNextUINT8 (
+  TCG_PARSE_STRUCT  *ParseStruct,
+  UINT8             *Value
+  )
+{
+  UINT64     Value64;
+  TCG_TOKEN  Tok;
+
+  NULL_CHECK (Value);
+
+  ERROR_CHECK (TcgGetNextToken (ParseStruct, &Tok));
+  ERROR_CHECK (TcgGetTokenUINT64 (&Tok, &Value64));
+
+  if (Value64 > MAX_UINT8) {
+    return TcgResultFailure;
+  }
+
+  *Value = (UINT8)Value64;
+
+  return TcgResultSuccess;
+}
+
+/**
+  Get next specify value.
+
+  @param    ParseStruct   Input parse structure.
+  @param    Value         Return value.
+
+  @retval   return the action result.
+
+**/
+TCG_RESULT
+EFIAPI
+TcgGetNextUINT16 (
+  TCG_PARSE_STRUCT  *ParseStruct,
+  UINT16            *Value
+  )
+{
+  UINT64     Value64;
+  TCG_TOKEN  Tok;
+
+  NULL_CHECK (Value);
+
+  ERROR_CHECK (TcgGetNextToken (ParseStruct, &Tok));
+  ERROR_CHECK (TcgGetTokenUINT64 (&Tok, &Value64));
+
+  if (Value64 > MAX_UINT16) {
+    return TcgResultFailure;
+  }
+
+  *Value = (UINT16)Value64;
+
+  return TcgResultSuccess;
+}
+
+/**
+  Get next specify value.
+
+  @param    ParseStruct   Input parse structure.
+  @param    Value         Return value.
+
+  @retval   return the action result.
+
+**/
+TCG_RESULT
+EFIAPI
+TcgGetNextUINT32 (
+  TCG_PARSE_STRUCT  *ParseStruct,
+  UINT32            *Value
+  )
+{
+  UINT64     Value64;
+  TCG_TOKEN  Tok;
+
+  NULL_CHECK (Value);
+
+  ERROR_CHECK (TcgGetNextToken (ParseStruct, &Tok));
+  ERROR_CHECK (TcgGetTokenUINT64 (&Tok, &Value64));
+
+  if (Value64 > MAX_UINT32) {
+    return TcgResultFailure;
+  }
+
+  *Value = (UINT32)Value64;
+
+  return TcgResultSuccess;
+}
+
+/**
+  Get next specify value.
+
+  @param    ParseStruct   Input parse structure.
+  @param    Value         Return value.
+
+  @retval   return the action result.
+
+**/
+TCG_RESULT
+EFIAPI
+TcgGetNextUINT64 (
+  TCG_PARSE_STRUCT  *ParseStruct,
+  UINT64            *Value
+  )
+{
+  TCG_TOKEN  Tok;
+
+  ERROR_CHECK (TcgGetNextToken (ParseStruct, &Tok));
+  ERROR_CHECK (TcgGetTokenUINT64 (&Tok, Value));
+  return TcgResultSuccess;
+}
+
+/**
+  Get next specify value.
+
+  @param    ParseStruct   Input parse structure.
+  @param    Value         Return value.
+
+  @retval   return the action result.
+
+**/
+TCG_RESULT
+EFIAPI
+TcgGetNextBOOLEAN (
+  TCG_PARSE_STRUCT  *ParseStruct,
+  BOOLEAN           *Value
+  )
+{
+  UINT64     Value64;
+  TCG_TOKEN  Tok;
+
+  NULL_CHECK (Value);
+
+  ERROR_CHECK (TcgGetNextToken (ParseStruct, &Tok));
+  ERROR_CHECK (TcgGetTokenUINT64 (&Tok, &Value64));
+
+  if (Value64 > 1) {
+    return TcgResultFailure;
+  }
+
+  *Value = (BOOLEAN)Value64;
+
+  return TcgResultSuccess;
+}
+
+/**
+  Get next tcg uid info.
+
+  @param    ParseStruct    Input parse structure.
+  @param    Uid            Get the uid info.
+
+  @retval   return the action result.
+
+**/
+TCG_RESULT
+EFIAPI
+TcgGetNextTcgUid (
+  TCG_PARSE_STRUCT  *ParseStruct,
+  TCG_UID           *Uid
+  )
+{
+  TCG_TOKEN    Tok;
+  UINT32       Length;
+  const UINT8  *ByteSeq;
+
+  NULL_CHECK (Uid);
+
+  ERROR_CHECK (TcgGetNextToken (ParseStruct, &Tok));
+  ByteSeq = TcgGetTokenByteSequence (&Tok, &Length);
+
+  if (Length != sizeof (TCG_UID)) {
+    DEBUG ((DEBUG_INFO, "Token Length %u != TCG_UID Size %u\n", Length, (UINT32)sizeof (TCG_UID)));
+    return TcgResultFailure;
+  }
+
+  ASSERT (ByteSeq != NULL);
+
+  CopyMem (Uid, ByteSeq, sizeof (TCG_UID));
+
+  return TcgResultSuccess;
+}
+
+/**
+  Get next byte sequence.
+
+  @param    ParseStruct     Input parse structure.
+  @param    Data            return the data.
+  @param    Length          return the length.
+
+  @retval   return the action result.
+
+**/
+TCG_RESULT
+EFIAPI
+TcgGetNextByteSequence (
+  TCG_PARSE_STRUCT  *ParseStruct,
+  const VOID        **Data,
+  UINT32            *Length
+  )
+{
+  TCG_TOKEN    Tok;
+  const UINT8  *Bs;
+
+  ERROR_CHECK (TcgGetNextToken (ParseStruct, &Tok));
+  Bs = TcgGetTokenByteSequence (&Tok, Length);
+
+  if (Bs == NULL) {
+    return TcgResultFailure;
+  }
+
+  *Data = Bs;
+  return TcgResultSuccess;
+}
+
+/**
+  Get next token Type.
+
+  @param    ParseStruct    Input parse structure.
+  @param    Type           Input the type need to check.
+
+  @retval   return the action result.
+
+**/
+TCG_RESULT
+EFIAPI
+TcgGetNextTokenType (
+  TCG_PARSE_STRUCT  *ParseStruct,
+  TCG_TOKEN_TYPE    Type
+  )
+{
+  TCG_TOKEN  Tok;
+
+  ERROR_CHECK (TcgGetNextToken (ParseStruct, &Tok));
+  if (Tok.Type != Type) {
+    DEBUG ((DEBUG_INFO, "expected Type %u, got Type %u\n", Type, Tok.Type));
+    return TcgResultFailure;
+  }
+
+  return TcgResultSuccess;
+}
+
+/**
+  Get next start list.
+
+  @param    ParseStruct   Input parse structure.
+
+  @retval   return the action result.
+
+**/
+TCG_RESULT
+EFIAPI
+TcgGetNextStartList (
+  TCG_PARSE_STRUCT  *ParseStruct
+  )
+{
+  return TcgGetNextTokenType (ParseStruct, TcgTokenTypeStartList);
+}
+
+/**
+  Get next end list.
+
+  @param    ParseStruct   Input parse structure.
+
+  @retval   return the action result.
+
+**/
+TCG_RESULT
+EFIAPI
+TcgGetNextEndList (
+  TCG_PARSE_STRUCT  *ParseStruct
+  )
+{
+  return TcgGetNextTokenType (ParseStruct, TcgTokenTypeEndList);
+}
+
+/**
+  Get next start name.
+
+  @param    ParseStruct   Input parse structure.
+
+  @retval   return the action result.
+
+**/
+TCG_RESULT
+EFIAPI
+TcgGetNextStartName (
+  TCG_PARSE_STRUCT  *ParseStruct
+  )
+{
+  return TcgGetNextTokenType (ParseStruct, TcgTokenTypeStartName);
+}
+
+/**
+  Get next end name.
+
+  @param    ParseStruct   Input parse structure.
+
+  @retval   return the action result.
+
+**/
+TCG_RESULT
+EFIAPI
+TcgGetNextEndName (
+  TCG_PARSE_STRUCT  *ParseStruct
+  )
+{
+  return TcgGetNextTokenType (ParseStruct, TcgTokenTypeEndName);
+}
+
+/**
+  Get next call.
+
+  @param    ParseStruct   Input parse structure.
+
+  @retval   return the action result.
+
+**/
+TCG_RESULT
+EFIAPI
+TcgGetNextCall (
+  TCG_PARSE_STRUCT  *ParseStruct
+  )
+{
+  return TcgGetNextTokenType (ParseStruct, TcgTokenTypeCall);
+}
+
+/**
+  Get next end data.
+
+  @param    ParseStruct   Input parse structure.
+
+  @retval   return the action result.
+
+**/
+TCG_RESULT
+EFIAPI
+TcgGetNextEndOfData (
+  TCG_PARSE_STRUCT  *ParseStruct
+  )
+{
+  return TcgGetNextTokenType (ParseStruct, TcgTokenTypeEndOfData);
+}
+
+/**
+  Get next end of session.
+
+  @param    ParseStruct   Input parse structure.
+
+  @retval   return the action result.
+
+**/
+TCG_RESULT
+EFIAPI
+TcgGetNextEndOfSession (
+  TCG_PARSE_STRUCT  *ParseStruct
+  )
+{
+  return TcgGetNextTokenType (ParseStruct, TcgTokenTypeEndOfSession);
+}
+
+/**
+  Get next start transaction.
+
+  @param    ParseStruct   Input parse structure.
+
+  @retval   return the action result.
+
+**/
+TCG_RESULT
+EFIAPI
+TcgGetNextStartTransaction (
+  TCG_PARSE_STRUCT  *ParseStruct
+  )
+{
+  return TcgGetNextTokenType (ParseStruct, TcgTokenTypeStartTransaction);
+}
+
+/**
+  Get next end transaction.
+
+  @param    ParseStruct   Input parse structure.
+
+  @retval   return the action result.
+
+**/
+TCG_RESULT
+EFIAPI
+TcgGetNextEndTransaction (
+  TCG_PARSE_STRUCT  *ParseStruct
+  )
+{
+  return TcgGetNextTokenType (ParseStruct, TcgTokenTypeEndTransaction);
+}
diff --git a/src/vendorcode/intel/tcg_storage_core/tcg_storage_core_lib.h b/src/vendorcode/intel/tcg_storage_core/tcg_storage_core_lib.h
new file mode 100644
index 0000000000..fd7fac2952
--- /dev/null
+++ b/src/vendorcode/intel/tcg_storage_core/tcg_storage_core_lib.h
@@ -0,0 +1,1287 @@
+/* SPDX-License-Identifier: BSD-2-Clause-Patent */
+
+/** @file
+  Public API for the Tcg Core library to perform the lowest level TCG Data encoding.
+
+  (TCG Storage Architecture Core Specification, Version 2.01, Revision 1.00,
+  https://trustedcomputinggroup.org/tcg-storage-architecture-core-specification/)
+
+  Check http://trustedcomputinggroup.org for latest specification updates.
+
+Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.<BR>
+SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef _TCG_CORE_H_
+#define _TCG_CORE_H_
+
+#include "tcg_storage_core_spec.h"
+
+#define ERROR_CHECK(arg)                                                                  \
+  {                                                                                       \
+    TCG_RESULT ret = (arg);                                                               \
+    if (ret != TcgResultSuccess) {                                                        \
+      DEBUG ((DEBUG_INFO, "ERROR_CHECK failed at %a:%u\n", __FILE__, DEBUG_LINE_NUMBER)); \
+      return ret;                                                                         \
+    }                                                                                     \
+  }
+
+#define METHOD_STATUS_ERROR_CHECK(arg, failRet)                                                  \
+  if ((arg) != TCG_METHOD_STATUS_CODE_SUCCESS) {                                                 \
+    DEBUG ((DEBUG_INFO, "Method Status error: 0x%02X (%a)\n", arg, TcgMethodStatusString(arg))); \
+    return (failRet);                                                                            \
+  }
+
+#define NULL_CHECK(arg)                                                                            \
+  do {                                                                                             \
+    if ((arg) == NULL) {                                                                           \
+      DEBUG ((DEBUG_INFO, "NULL_CHECK(%a) failed at %a:%u\n", #arg, __FILE__, DEBUG_LINE_NUMBER)); \
+      return TcgResultFailureNullPointer;                                                          \
+    }                                                                                              \
+  } while (0)
+
+#pragma pack(1)
+
+/**
+Tcg result codes.
+
+The result code indicates if the Tcg function call was successful or not
+**/
+typedef enum {
+  //
+  // This is the return result upon successful completion of a Tcg function call
+  //
+  TcgResultSuccess,
+
+  //
+  // This is the return "catchall" result for the failure of a Tcg function call
+  //
+  TcgResultFailure,
+
+  //
+  // This is the return result if a required parameter was Null for a Tcg function call
+  //
+  TcgResultFailureNullPointer,
+
+  //
+  // This is the return result if a required buffersize was 0 for a Tcg function call
+  //
+  TcgResultFailureZeroSize,
+
+  //
+  // This is the return result if a Tcg function call was executed out of order.
+  // For instance, starting a Tcg subpacket before starting its Tcg packet.
+  //
+  TcgResultFailureInvalidAction,
+
+  //
+  // This is the return result if the buffersize provided is not big enough to add a requested Tcg encoded item.
+  //
+  TcgResultFailureBufferTooSmall,
+
+  //
+  // This is the return result for a Tcg parse function if the end of the parsed Buffer is reached, yet Data is still attempted to be retrieved.
+  // For instance, attempting to retrieve another Tcg token from the Buffer after it has reached the end of the Tcg subpacket payload.
+  //
+  TcgResultFailureEndBuffer,
+
+  //
+  // This is the return result for a Tcg parse function if the Tcg Token item requested is not the expected type.
+  // For instance, the caller requested to receive an integer and the Tcg token was a byte sequence.
+  //
+  TcgResultFailureInvalidType,
+} TCG_RESULT;
+
+//
+// Structure that is used to build the Tcg ComPacket.  It contains the start Buffer pointer and the current position of the
+// Tcg ComPacket, current Tcg Packet and Tcg SubPacket. This structure must be initialized
+// by calling tcgInitTcgCreateStruct before it is used as parameter to any other Tcg function.
+// This structure should NOT be directly modified by the client of this library.
+//
+//  NOTE:  WE MAY MAKE THIS AN ABSTRACT STRUCTURE WITH A DEFINED SIZE AND KEEP THE VARIABLES
+//         INTERNAL AND ONLY KNOWN TO THE TCG LIBRARY
+//
+// tcgInitTcgCreateStruct
+//
+typedef struct {
+  //
+  // Buffer allocated and freed by the client of the Tcg library.
+  // This is the Buffer that shall contain the final Tcg encoded compacket.
+  //
+  VOID              *Buffer;
+
+  //
+  // Size of the Buffer provided.
+  //
+  UINT32            BufferSize;
+
+  //
+  // Pointer to the start of the Tcg ComPacket.  It should point to a location within Buffer.
+  //
+  TCG_COM_PACKET    *ComPacket;
+
+  //
+  // Current Tcg Packet that is being created.  It should point to a location within Buffer.
+  //
+  TCG_PACKET        *CurPacket;
+
+  //
+  // Current Tcg SubPacket that is being created.  It should point to a location within Buffer.
+  //
+  TCG_SUB_PACKET    *CurSubPacket;
+
+  //
+  // Flag used to indicate if the Buffer of the structure should be filled out.
+  // This is intended to be used to support a use-case where the client of library
+  // can perform all the desired tcg calls to determine what the actual Size of the final compacket will be.
+  // Then the client can allocate the required Buffer Size and re-run the tcg calls.
+  // THIS MAY NOT BE IMPLEMENTED... REQUIRES MORE THOUGHT BECAUSE YOU CANNOT SOLVE ISSUE FOR RECEIVE
+  //
+  BOOLEAN    DryRun;
+} TCG_CREATE_STRUCT;
+
+//
+// Structure that is used to parse the Tcg response received.  It contains the response Buffer pointer
+// and the current position of the Tcg ComPacket, current Tcg Packet and Tcg SubPacket being parsed.
+// This structure must be initialized by calling tcgInitTcgParseStruct before it is used as parameter to any other Tcg parse function.
+// This structure should NOT be directly modified by the client of this library.
+//
+//  NOTE:  WE MAY MAKE THIS AN ABSTRACT STRUCTURE WITH A DEFINED SIZE AND KEEP THE VARIABLES
+//         INTERNAL AND ONLY KNOWN TO THE TCG LIBRARY
+//
+// @sa tcgInitTcgParseStruct
+//
+typedef struct  {
+  //
+  // Buffer allocated and freed by the client of the Tcg library.
+  // This is the Buffer that contains the Tcg response to decode/parse.
+  //
+  const VOID        *Buffer;
+
+  //
+  // Size of the Buffer provided.
+  //
+  UINT32            BufferSize;
+
+  //
+  // Pointer to the start of the Tcg ComPacket.  It should point to a location within Buffer.
+  //
+  TCG_COM_PACKET    *ComPacket;
+
+  //
+  // Current Tcg Packet that is being created.  It should point to a location within Buffer.
+  //
+  TCG_PACKET        *CurPacket;
+
+  //
+  // Current Tcg SubPacket that is being created.  It should point to a location within Buffer.
+  //
+  TCG_SUB_PACKET    *CurSubPacket;
+
+  //
+  // Current pointer within the current subpacket payload.
+  //
+  UINT8             *CurPtr;
+} TCG_PARSE_STRUCT;
+
+//
+// Structure that is used to represent a Tcg Token that is retrieved by Tcg parse functions.
+//
+typedef struct {
+  //
+  // Describes the type of Tcg token the Hdr start points to.
+  //
+  TCG_TOKEN_TYPE    Type;
+
+  //
+  // Pointer to the beginning of the Header of the Tcg token
+  //
+  UINT8             *HdrStart;
+} TCG_TOKEN;
+
+/**
+
+  Required to be called before calling any other Tcg functions with the TCG_CREATE_STRUCT.
+  Initializes the packet variables to NULL.  Additionally, the buffer will be memset.
+
+  @param[in/out]   CreateStruct   Structure to initialize
+  @param[in]       Buffer         Buffer allocated by client of library.  It will contain the Tcg encoded packet.  This cannot be null.
+  @param[in]       BufferSize     Size of buffer provided.  It cannot be 0.
+
+**/
+TCG_RESULT
+EFIAPI
+TcgInitTcgCreateStruct (
+  TCG_CREATE_STRUCT  *CreateStruct,
+  VOID               *Buffer,
+  UINT32             BufferSize
+  );
+
+/**
+
+  Encodes the ComPacket header to the data structure.
+
+  @param[in/out]    CreateStruct       Structure to initialize
+  @param[in]        ComId              ComID of the Tcg ComPacket.
+  @param[in]        ComIdExtension     ComID Extension of the Tcg ComPacket.
+
+**/
+TCG_RESULT
+EFIAPI
+TcgStartComPacket (
+  TCG_CREATE_STRUCT  *CreateStruct,
+  UINT16             ComId,
+  UINT16             ComIdExtension
+  );
+
+/**
+
+  Starts a new ComPacket in the Data structure.
+
+  @param[in/out]    CreateStruct       Structure used to add Tcg Packet
+  @param[in]        Tsn                Packet Tper session number
+  @param[in]        Hsn                Packet Host session number
+  @param[in]        SeqNumber          Packet Sequence Number
+  @param[in]        AckType            Packet Acknowledge Type
+  @param[in]        Ack                Packet Acknowledge
+
+**/
+TCG_RESULT
+EFIAPI
+TcgStartPacket (
+  TCG_CREATE_STRUCT  *CreateStruct,
+  UINT32             Tsn,
+  UINT32             Hsn,
+  UINT32             SeqNumber,
+  UINT16             AckType,
+  UINT32             Ack
+  );
+
+/**
+
+  Starts a new SubPacket in the Data structure.
+
+  @param[in/out]    CreateStruct       Structure used to start Tcg SubPacket
+  @param[in]        Kind               SubPacket kind
+
+**/
+TCG_RESULT
+EFIAPI
+TcgStartSubPacket (
+  TCG_CREATE_STRUCT  *CreateStruct,
+  UINT16             Kind
+  );
+
+/**
+
+  Ends the current SubPacket in the Data structure.  This function will also perform the 4-byte padding
+  required for Subpackets.
+
+  @param[in/out]        CreateStruct       Structure used to end the current Tcg SubPacket
+
+**/
+TCG_RESULT
+EFIAPI
+TcgEndSubPacket (
+  TCG_CREATE_STRUCT  *CreateStruct
+  );
+
+/**
+
+  Ends the current Packet in the Data structure.
+
+  @param[in/out]       CreateStruct        Structure used to end the current Tcg Packet
+
+**/
+TCG_RESULT
+EFIAPI
+TcgEndPacket (
+  TCG_CREATE_STRUCT  *CreateStruct
+  );
+
+/**
+
+  Ends the ComPacket in the Data structure and ret
+
+  @param[in/out]       CreateStruct    Structure used to end the Tcg ComPacket
+  @param[in/out]       Size                Describes the Size of the entire ComPacket (Header and payload). Filled out by function.
+
+**/
+TCG_RESULT
+EFIAPI
+TcgEndComPacket (
+  TCG_CREATE_STRUCT  *CreateStruct,
+  UINT32             *Size
+  );
+
+/**
+  Adds a single raw token byte to the Data structure.
+
+  @param[in/out]   CreateStruct      Structure used to add the byte
+  @param [in]      Byte              Byte to add
+
+**/
+TCG_RESULT
+EFIAPI
+TcgAddRawByte (
+  TCG_CREATE_STRUCT  *CreateStruct,
+  UINT8              Byte
+  );
+
+/**
+
+  Adds the Data parameter as a byte sequence to the Data structure.
+
+  @param [in/out]    CreateStruct   Structure used to add the byte sequence
+  @param[in]         Data           Byte sequence that will be encoded and copied into Data structure
+  @param[in]         DataSize       Length of Data provided
+  @param[in]         Continued      TRUE if byte sequence is continued or
+                                    FALSE if the Data contains the entire byte sequence to be encoded
+
+**/
+TCG_RESULT
+EFIAPI
+TcgAddByteSequence (
+  TCG_CREATE_STRUCT  *CreateStruct,
+  const VOID         *Data,
+  UINT32             DataSize,
+  BOOLEAN            Continued
+  );
+
+/**
+
+  Adds an arbitrary-Length integer to the Data structure.
+
+  The integer will be encoded using the shortest possible atom.
+
+  @param[in/out]     CreateStruct        Structure used to add the integer
+  @param[in]         Data                Integer in host byte order that will be encoded and copied into Data structure
+  @param[in]         DataSize            Length in bytes of the Data provided
+  @param[in]         SignedInteger       TRUE if the integer is signed or FALSE if the integer is unsigned
+
+**/
+TCG_RESULT
+EFIAPI
+TcgAddInteger (
+  TCG_CREATE_STRUCT  *CreateStruct,
+  const VOID         *Data,
+  UINT32             DataSize,
+  BOOLEAN            SignedInteger
+  );
+
+/**
+  Adds an 8-bit unsigned integer to the Data structure.
+
+  @param[in/out]     CreateStruct        Structure used to add the integer
+  @param[in]         Value               Integer Value to add
+
+**/
+TCG_RESULT
+EFIAPI
+TcgAddUINT8 (
+  TCG_CREATE_STRUCT  *CreateStruct,
+  UINT8              Value
+  );
+
+/**
+
+  Adds a 16-bit unsigned integer to the Data structure.
+
+  @param[in/out]       CreateStruct        Structure used to add the integer
+  @param[in]           Value               Integer Value to add
+
+**/
+TCG_RESULT
+EFIAPI
+TcgAddUINT16 (
+  TCG_CREATE_STRUCT  *CreateStruct,
+  UINT16             Value
+  );
+
+/**
+
+  Adds a 32-bit unsigned integer to the Data structure.
+
+  @param[in/out]        CreateStruct        Structure used to add the integer
+  @param[in]            Value               Integer Value to add
+
+**/
+TCG_RESULT
+EFIAPI
+TcgAddUINT32 (
+  TCG_CREATE_STRUCT  *CreateStruct,
+  UINT32             Value
+  );
+
+/**
+
+  Adds a 64-bit unsigned integer to the Data structure.
+
+  @param[in/out]      CreateStruct        Structure used to add the integer
+  @param[in]          Value               Integer Value to add
+
+**/
+TCG_RESULT
+EFIAPI
+TcgAddUINT64 (
+  TCG_CREATE_STRUCT  *CreateStruct,
+  UINT64             Value
+  );
+
+/**
+  Adds a BOOLEAN to the Data structure.
+
+  @param[in/out]       CreateStruct     Structure used to add the integer
+  @param[in]           Value              BOOLEAN Value to add
+
+**/
+TCG_RESULT
+EFIAPI
+TcgAddBOOLEAN (
+  TCG_CREATE_STRUCT  *CreateStruct,
+  BOOLEAN            Value
+  );
+
+/**
+  Add tcg uid info.
+
+  @param [in/out]       CreateStruct       Structure used to add the integer
+  @param                Uid                Input uid info.
+
+  @retval   return the action result.
+
+**/
+TCG_RESULT
+EFIAPI
+TcgAddTcgUid (
+  TCG_CREATE_STRUCT  *CreateStruct,
+  TCG_UID            Uid
+  );
+
+/**
+ Adds a Start List token to the Data structure.
+
+ @param[in/out]   CreateStruct      Structure used to add the token
+
+**/
+TCG_RESULT
+EFIAPI
+TcgAddStartList (
+  TCG_CREATE_STRUCT  *CreateStruct
+  );
+
+/**
+
+ Adds an End List token to the Data structure.
+
+ @param [in/out]    CreateStruct      Structure used to add the token
+
+**/
+TCG_RESULT
+EFIAPI
+TcgAddEndList (
+  TCG_CREATE_STRUCT  *CreateStruct
+  );
+
+/**
+ Adds a Start Name token to the Data structure.
+
+ @param[in/out]    CreateStruct    Structure used to add the token
+
+**/
+TCG_RESULT
+EFIAPI
+TcgAddStartName (
+  TCG_CREATE_STRUCT  *CreateStruct
+  );
+
+/**
+
+ Adds an End Name token to the Data structure.
+
+ @param [in/out]   CreateStruct      Structure used to add the token
+
+**/
+TCG_RESULT
+EFIAPI
+TcgAddEndName (
+  TCG_CREATE_STRUCT  *CreateStruct
+  );
+
+/**
+ Adds a Call token to the Data structure.
+
+ @param  [in/out]    CreateStruct    Structure used to add the token
+
+**/
+TCG_RESULT
+EFIAPI
+TcgAddCall (
+  TCG_CREATE_STRUCT  *CreateStruct
+  );
+
+/**
+
+Adds an End of Data token to the Data structure.
+
+@param[in/out]   CreateStruct    Structure used to add the token
+
+**/
+TCG_RESULT
+EFIAPI
+TcgAddEndOfData (
+  TCG_CREATE_STRUCT  *CreateStruct
+  );
+
+/**
+
+Adds an End of Session token to the Data structure.
+
+@param [in/out]    CreateStruct  Structure used to add the token
+
+**/
+TCG_RESULT
+EFIAPI
+TcgAddEndOfSession (
+  TCG_CREATE_STRUCT  *CreateStruct
+  );
+
+/**
+ Adds a Start Transaction token to the Data structure.
+
+ @param [in/out]    CreateStruct  Structure used to add the token
+
+**/
+TCG_RESULT
+EFIAPI
+TcgAddStartTransaction (
+  TCG_CREATE_STRUCT  *CreateStruct
+  );
+
+/**
+ Adds an End Transaction token to the Data structure.
+
+ @param[in/out]   CreateStruct   Structure used to add the token
+
+**/
+TCG_RESULT
+EFIAPI
+TcgAddEndTransaction (
+  TCG_CREATE_STRUCT  *CreateStruct
+  );
+
+/**
+  Initial the tcg parse structure.
+
+  @param    ParseStruct    Input parse structure.
+  @param    Buffer         Input buffer data.
+  @param    BufferSize     Input buffer size.
+
+  @retval   return the action result.
+
+**/
+TCG_RESULT
+EFIAPI
+TcgInitTcgParseStruct (
+  TCG_PARSE_STRUCT  *ParseStruct,
+  const VOID        *Buffer,
+  UINT32            BufferSize
+  );
+
+/**
+  Get next token info.
+
+  @param    ParseStruct      Input parse structure info.
+  @param    TcgToken         return the tcg token info.
+
+  @retval   return the action result.
+
+**/
+TCG_RESULT
+EFIAPI
+TcgGetNextToken (
+  TCG_PARSE_STRUCT  *ParseStruct,
+  TCG_TOKEN         *TcgToken
+  );
+
+/**
+  Get next token Type.
+
+  @param    ParseStruct    Input parse structure.
+  @param    Type           Input the type need to check.
+
+  @retval   return the action result.
+
+**/
+TCG_RESULT
+EFIAPI
+TcgGetNextTokenType (
+  TCG_PARSE_STRUCT  *ParseStruct,
+  TCG_TOKEN_TYPE    Type
+  );
+
+/**
+  Get atom info.
+
+  @param    TcgToken          Input token info.
+  @param    HeaderLength      return the header length.
+  @param    DataLength        return the data length.
+  @param    ByteOrInt         return the atom Type.
+  @param    SignOrCont        return the sign or count info.
+
+  @retval   return the action result.
+
+**/
+TCG_RESULT
+EFIAPI
+TcgGetAtomInfo (
+  const TCG_TOKEN  *TcgToken,
+  UINT32           *HeaderLength,
+  UINT32           *DataLength,
+  UINT8            *ByteOrInt,
+  UINT8            *SignOrCont
+  );
+
+/**
+  Get token byte sequence.
+
+  @param    TcgToken   Input token info.
+  @param    Length     Input the length info.
+
+  @retval   Return the value data.
+
+**/
+UINT8 *
+EFIAPI
+TcgGetTokenByteSequence (
+  const TCG_TOKEN  *TcgToken,
+  UINT32           *Length
+  );
+
+/**
+  Get token specified value.
+
+  @param    TcgToken   Input token info.
+  @param    Value      return the value.
+
+  @retval   return the action result.
+
+**/
+TCG_RESULT
+EFIAPI
+TcgGetTokenUINT64 (
+  const TCG_TOKEN  *TcgToken,
+  UINT64           *Value
+  );
+
+/**
+  Get next specify value.
+
+  @param    ParseStruct   Input parse structure.
+  @param    Value         Return value.
+
+  @retval   return the action result.
+
+**/
+TCG_RESULT
+EFIAPI
+TcgGetNextUINT8 (
+  TCG_PARSE_STRUCT  *ParseStruct,
+  UINT8             *Value
+  );
+
+/**
+  Get next specify value.
+
+  @param    ParseStruct   Input parse structure.
+  @param    Value         Return value.
+
+  @retval   return the action result.
+
+**/
+TCG_RESULT
+EFIAPI
+TcgGetNextUINT16 (
+  TCG_PARSE_STRUCT  *ParseStruct,
+  UINT16            *Value
+  );
+
+/**
+  Get next specify value.
+
+  @param    ParseStruct   Input parse structure.
+  @param    Value         Return value.
+
+  @retval   return the action result.
+
+**/
+TCG_RESULT
+EFIAPI
+TcgGetNextUINT32 (
+  TCG_PARSE_STRUCT  *ParseStruct,
+  UINT32            *Value
+  );
+
+/**
+  Get next specify value.
+
+  @param    ParseStruct   Input parse structure.
+  @param    Value         Return value.
+
+  @retval   return the action result.
+
+**/
+TCG_RESULT
+EFIAPI
+TcgGetNextUINT64 (
+  TCG_PARSE_STRUCT  *ParseStruct,
+  UINT64            *Value
+  );
+
+/**
+  Get next specify value.
+
+  @param    ParseStruct   Input parse structure.
+  @param    Value         Return value.
+
+  @retval   return the action result.
+
+**/
+TCG_RESULT
+EFIAPI
+TcgGetNextBOOLEAN (
+  TCG_PARSE_STRUCT  *ParseStruct,
+  BOOLEAN           *Value
+  );
+
+/**
+  Get next tcg uid info.
+
+  @param    ParseStruct    Input parse structure.
+  @param    Uid            Get the uid info.
+
+  @retval   return the action result.
+
+**/
+TCG_RESULT
+EFIAPI
+TcgGetNextTcgUid (
+  TCG_PARSE_STRUCT  *ParseStruct,
+  TCG_UID           *Uid
+  );
+
+/**
+  Get next byte sequence.
+
+  @param    ParseStruct     Input parse structure.
+  @param    Data            return the data.
+  @param    Length          return the length.
+
+  @retval   return the action result.
+
+**/
+TCG_RESULT
+EFIAPI
+TcgGetNextByteSequence (
+  TCG_PARSE_STRUCT  *ParseStruct,
+  const VOID        **Data,
+  UINT32            *Length
+  );
+
+/**
+  Get next start list.
+
+  @param    ParseStruct   Input parse structure.
+
+  @retval   return the action result.
+
+**/
+TCG_RESULT
+EFIAPI
+TcgGetNextStartList (
+  TCG_PARSE_STRUCT  *ParseStruct
+  );
+
+/**
+  Get next end list.
+
+  @param    ParseStruct   Input parse structure.
+
+  @retval   return the action result.
+
+**/
+TCG_RESULT
+EFIAPI
+TcgGetNextEndList (
+  TCG_PARSE_STRUCT  *ParseStruct
+  );
+
+/**
+  Get next start name.
+
+  @param    ParseStruct   Input parse structure.
+
+  @retval   return the action result.
+
+**/
+TCG_RESULT
+EFIAPI
+TcgGetNextStartName (
+  TCG_PARSE_STRUCT  *ParseStruct
+  );
+
+/**
+  Get next end name.
+
+  @param    ParseStruct   Input parse structure.
+
+  @retval   return the action result.
+
+**/
+TCG_RESULT
+EFIAPI
+TcgGetNextEndName (
+  TCG_PARSE_STRUCT  *ParseStruct
+  );
+
+/**
+  Get next call.
+
+  @param    ParseStruct   Input parse structure.
+
+  @retval   return the action result.
+
+**/
+TCG_RESULT
+EFIAPI
+TcgGetNextCall (
+  TCG_PARSE_STRUCT  *ParseStruct
+  );
+
+/**
+  Get next end data.
+
+  @param    ParseStruct   Input parse structure.
+
+  @retval   return the action result.
+
+**/
+TCG_RESULT
+EFIAPI
+TcgGetNextEndOfData (
+  TCG_PARSE_STRUCT  *ParseStruct
+  );
+
+/**
+  Get next end of session.
+
+  @param    ParseStruct   Input parse structure.
+
+  @retval   return the action result.
+
+**/
+TCG_RESULT
+EFIAPI
+TcgGetNextEndOfSession (
+  TCG_PARSE_STRUCT  *ParseStruct
+  );
+
+/**
+  Get next start transaction.
+
+  @param    ParseStruct   Input parse structure.
+
+  @retval   return the action result.
+
+**/
+TCG_RESULT
+EFIAPI
+TcgGetNextStartTransaction (
+  TCG_PARSE_STRUCT  *ParseStruct
+  );
+
+/**
+  Get next end transaction.
+
+  @param    ParseStruct   Input parse structure.
+
+  @retval   return the action result.
+
+**/
+TCG_RESULT
+EFIAPI
+TcgGetNextEndTransaction (
+  TCG_PARSE_STRUCT  *ParseStruct
+  );
+
+// end of parse functions
+
+typedef
+BOOLEAN
+(EFIAPI *TCG_LEVEL0_ENUM_CALLBACK)(
+  const TCG_LEVEL0_DISCOVERY_HEADER      *DiscoveryHeader,
+  TCG_LEVEL0_FEATURE_DESCRIPTOR_HEADER   *Feature,
+  UINTN                                  FeatureSize, // includes header
+  VOID                                   *Context
+  );
+
+/**
+  Adds call token and method Header (invoking id, and method id).
+
+  @param    CreateStruct             The input create structure.
+  @param    InvokingId               Invoking id.
+  @param    MethodId                 Method id.
+
+**/
+TCG_RESULT
+EFIAPI
+TcgStartMethodCall (
+  TCG_CREATE_STRUCT  *CreateStruct,
+  TCG_UID            InvokingId,
+  TCG_UID            MethodId
+  );
+
+/**
+  Adds START LIST token.
+
+  @param    CreateStruct        The input create structure.
+
+**/
+TCG_RESULT
+EFIAPI
+TcgStartParameters (
+  TCG_CREATE_STRUCT  *CreateStruct
+  );
+
+/**
+  Adds END LIST token.
+
+  @param    CreateStruct        The input create structure.
+
+**/
+TCG_RESULT
+EFIAPI
+TcgEndParameters (
+  TCG_CREATE_STRUCT  *CreateStruct
+  );
+
+/**
+  Adds END Data token and method list.
+
+  @param    CreateStruct        The input create structure.
+
+**/
+TCG_RESULT
+EFIAPI
+TcgEndMethodCall (
+  TCG_CREATE_STRUCT  *CreateStruct
+  );
+
+/**
+
+  Adds Start Session call to the data structure.  This creates the entire ComPacket structure and
+  returns the size of the entire compacket in the size parameter.
+
+  @param [in/out]    CreateStruct               Structure used to add the start session call
+  @param [in/out]    Size                       Describes the size of the entire ComPacket (header and payload). Filled out by function.
+  @param [in]        ComId                      ComID for the ComPacket
+  @param [in]        ComIdExtension             Extended ComID for the ComPacket
+  @param [in]        HostSessionId              Host Session ID
+  @param [in]        SpId                       Security Provider to start session with
+  @param [in]        Write                      Write option for start session.  TRUE = start session requests write access
+  @param [in]        HostChallengeLength        Length of the host challenge.  Length should be 0 if hostChallenge is NULL
+  @param [in]        HostChallenge              Host challenge for Host Signing Authority.  If NULL, then no Host Challenge shall be sent.
+  @param [in]        HostSigningAuthority       Host Signing Authority used for start session.  If NULL, then no Host Signing Authority shall be sent.
+
+**/
+TCG_RESULT
+EFIAPI
+TcgCreateStartSession (
+  TCG_CREATE_STRUCT  *CreateStruct,
+  UINT32             *Size,
+  UINT16             ComId,
+  UINT16             ComIdExtension,
+  UINT32             HostSessionId,
+  TCG_UID            SpId,
+  BOOLEAN            Write,
+  UINT32             HostChallengeLength,
+  const VOID         *HostChallenge,
+  TCG_UID            HostSigningAuthority
+  );
+
+/**
+  Creates ComPacket with a Method call that sets the PIN column for the row specified.
+  This assumes a start session has already been opened with the desired SP.
+
+  @param [in/out]   CreateStruct           Structure used to add method call.
+  @param [in/out]   Size                   Describes the size of the entire ComPacket (header and payload). Filled out by function.
+  @param [in]       ComId                  ComID for the ComPacket
+  @param [in]       ComIdExtension         Extended ComID for the ComPacket
+  @param [in]       TperSession            Tper Session ID for the Packet
+  @param [in]       HostSession            Host Session ID for the Packet
+  @param [in]       SidRow                 UID of row of current SP to set PIN column
+  @param [in]       Password               value of PIN to set
+  @param [in]       PasswordSize           Size of PIN
+
+**/
+TCG_RESULT
+EFIAPI
+TcgCreateSetCPin (
+  TCG_CREATE_STRUCT  *CreateStruct,
+  UINT32             *Size,
+  UINT16             ComId,
+  UINT16             ComIdExtension,
+  UINT32             TperSession,
+  UINT32             HostSession,
+  TCG_UID            SidRow,
+  const VOID         *Password,
+  UINT32             PasswordSize
+  );
+
+/**
+ Creates ComPacket with a Method call that sets the "Enabled" column for the row specified using the value specified.
+ This assumes a start session has already been opened with the desired SP.
+
+ @param [in/out]  CreateStruct          Structure used to add method call
+ @param [in/out]  Size                  Describes the size of the entire ComPacket (header and payload). Filled out by function.
+ @param [in]      ComId                 ComID for the ComPacket
+ @param [in]      ComIdExtension        Extended ComID for the ComPacket
+ @param [in]      TperSession           Tper Session ID for the Packet
+ @param [in]      HostSession           Host Session ID for the Packet
+ @param [in]      AuthorityUid          Authority UID to modify the "Enabled" column for
+ @param [in]      Enabled               Value to set the "Enabled" column to
+
+**/
+TCG_RESULT
+EFIAPI
+TcgSetAuthorityEnabled (
+  TCG_CREATE_STRUCT  *CreateStruct,
+  UINT32             *Size,
+  UINT16             ComId,
+  UINT16             ComIdExtension,
+  UINT32             TperSession,
+  UINT32             HostSession,
+  TCG_UID            AuthorityUid,
+  BOOLEAN            Enabled
+  );
+
+/**
+
+  Creates ComPacket with EndSession.
+  This assumes a start session has already been opened.
+
+  @param  [in/out]    CreateStruct        Structure used to add Endsession
+  @param  [in/out]    Size                Describes the size of the entire ComPacket (header and payload). Filled out by function.
+  @param  [in]        ComId               ComID for the ComPacket
+  @param  [in]        ComIdExtension      Extended ComID for the ComPacket
+  @param  [in]        HostSessionId         Host Session ID for the Packet
+  @param  [in]        TpSessionId         Tper Session ID for the Packet
+
+**/
+TCG_RESULT
+EFIAPI
+TcgCreateEndSession (
+  TCG_CREATE_STRUCT  *CreateStruct,
+  UINT32             *Size,
+  UINT16             ComId,
+  UINT16             ComIdExtension,
+  UINT32             HostSessionId,
+  UINT32             TpSessionId
+  );
+
+/**
+
+ Retrieves human-readable token type name.
+
+ @param[in]   Type  Token type to retrieve
+
+**/
+const CHAR8 *
+EFIAPI
+TcgTokenTypeString (
+  TCG_TOKEN_TYPE  Type
+  );
+
+/**
+ Returns the method status of the current subpacket.  Does not affect the current position
+ in the ComPacket.  In other words, it can be called whenever you have a valid SubPacket.
+
+ @param [in/out]  ParseStruct       Structure used to parse received TCG response
+ @param [in/out]  MethodStatus      Method status retrieved of the current SubPacket
+
+**/
+TCG_RESULT
+EFIAPI
+TcgGetMethodStatus (
+  const TCG_PARSE_STRUCT  *ParseStruct,
+  UINT8                   *MethodStatus
+  );
+
+/**
+  Returns a human-readable string representing a method status return code.
+
+  @param[in]  MethodStatus   Method status to translate to a string
+
+
+  @retval   return the string info.
+**/
+const CHAR8 *
+EFIAPI
+TcgMethodStatusString (
+  UINT8  MethodStatus
+  );
+
+/**
+  Retrieves the comID and Extended comID of the ComPacket in the Tcg response.
+  It is intended to be used to confirm the received Tcg response is intended for user that received it.
+
+  @param [in]        ParseStruct        Structure used to parse received TCG response.
+  @param [in/out]    ComId              comID retrieved from received ComPacket.
+  @param [in/out]    ComIdExtension     Extended comID retrieved from received ComPacket
+
+**/
+TCG_RESULT
+EFIAPI
+TcgGetComIds (
+  const TCG_PARSE_STRUCT  *ParseStruct,
+  UINT16                  *ComId,
+  UINT16                  *ComIdExtension
+  );
+
+/**
+  Checks if the ComIDs of the response match the expected values.
+
+  @param[in]   ParseStruct               Structure used to parse received TCG response
+  @param[in]   ExpectedComId             Expected comID
+  @param[in]   ExpectedComIdExtension    Expected extended comID
+
+**/
+TCG_RESULT
+EFIAPI
+TcgCheckComIds (
+  const TCG_PARSE_STRUCT  *ParseStruct,
+  UINT16                  ExpectedComId,
+  UINT16                  ExpectedComIdExtension
+  );
+
+/**
+ Parses the Sync Session response contained in the parseStruct to retrieve Tper session ID.  If the Sync Session response
+ parameters do not match the comID, extended ComID and host session ID then a failure is returned.
+
+ @param[in/out]   ParseStruct          Structure used to parse received TCG response, contains Sync Session response.
+ @param[in]       ComId                Expected ComID that is compared to actual ComID of response
+ @param[in]       ComIdExtension       Expected Extended ComID that is compared to actual Extended ComID of response
+ @param[in]       HostSessionId        Expected Host Session ID that is compared to actual  Host Session ID of response
+ @param[in/out]   TperSessionId        Tper Session ID retrieved from the Sync Session response.
+
+**/
+TCG_RESULT
+EFIAPI
+TcgParseSyncSession (
+  const TCG_PARSE_STRUCT  *ParseStruct,
+  UINT16                  ComId,
+  UINT16                  ComIdExtension,
+  UINT32                  HostSessionId,
+  UINT32                  *TperSessionId
+  );
+
+/**
+  Create set ace.
+
+  @param     CreateStruct      Input create structure.
+  @param     Size              size info.
+  @param     ComId             ComId info.
+  @param     ComIdExtension    ComId extension info.
+  @param     TperSession       Tper session data.
+  @param     HostSession       Host session data.
+  @param     AceRow            Ace row info.
+  @param     Authority1        Authority 1 info.
+  @param     LogicalOperator   Logical operator info.
+  @param     Authority2        Authority 2 info.
+
+  @retval    Return the action result.
+
+**/
+TCG_RESULT
+EFIAPI
+TcgCreateSetAce (
+  TCG_CREATE_STRUCT  *CreateStruct,
+  UINT32             *Size,
+  UINT16             ComId,
+  UINT16             ComIdExtension,
+  UINT32             TperSession,
+  UINT32             HostSession,
+  TCG_UID            AceRow,
+  TCG_UID            Authority1,
+  BOOLEAN            LogicalOperator,
+  TCG_UID            Authority2
+  );
+
+/**
+  Enum level 0 discovery.
+
+  @param     DiscoveryHeader   Discovery header.
+  @param     Callback          Callback function.
+  @param     Context           The context for the function.
+
+  @retval    return true if the callback return TRUE, else return FALSE.
+
+**/
+BOOLEAN
+EFIAPI
+TcgEnumLevel0Discovery (
+  const TCG_LEVEL0_DISCOVERY_HEADER  *DiscoveryHeader,
+  TCG_LEVEL0_ENUM_CALLBACK           Callback,
+  VOID                               *Context
+  );
+
+/**
+  Get Feature code from the header.
+
+  @param     DiscoveryHeader    The discovery header.
+  @param     FeatureCode        return the Feature code.
+  @param     FeatureSize        return the Feature size.
+
+  @retval    return the Feature code data.
+**/
+TCG_LEVEL0_FEATURE_DESCRIPTOR_HEADER *
+EFIAPI
+TcgGetFeature (
+  const TCG_LEVEL0_DISCOVERY_HEADER  *DiscoveryHeader,
+  UINT16                             FeatureCode,
+  UINTN                              *FeatureSize
+  );
+
+/**
+  Determines if the protocol provided is part of the provided supported protocol list.
+
+  @param[in]  ProtocolList     Supported protocol list to investigate
+  @param[in]  Protocol         Protocol value to determine if supported
+
+  @return TRUE = protocol is supported, FALSE = protocol is not supported
+**/
+BOOLEAN
+EFIAPI
+TcgIsProtocolSupported (
+  const TCG_SUPPORTED_SECURITY_PROTOCOLS  *ProtocolList,
+  UINT16                                  Protocol
+  );
+
+/**
+  Determines if the Locking Feature "Locked" bit is set in the level 0 discovery response.
+
+  @param[in]  Discovery              Level 0 discovery response
+
+  @return TRUE = Locked is set, FALSE = Locked is false
+
+**/
+BOOLEAN
+EFIAPI
+TcgIsLocked (
+  const TCG_LEVEL0_DISCOVERY_HEADER  *Discovery
+  );
+
+#pragma pack()
+
+#endif // _TCG_CORE_H_
diff --git a/src/vendorcode/intel/tcg_storage_core/tcg_storage_core_spec.h b/src/vendorcode/intel/tcg_storage_core/tcg_storage_core_spec.h
new file mode 100644
index 0000000000..2233edeb38
--- /dev/null
+++ b/src/vendorcode/intel/tcg_storage_core/tcg_storage_core_spec.h
@@ -0,0 +1,389 @@
+/* SPDX-License-Identifier: BSD-2-Clause-Patent */
+
+/** @file
+  TCG defined values and structures.
+
+  (TCG Storage Architecture Core Specification, Version 2.01, Revision 1.00,
+  https://trustedcomputinggroup.org/tcg-storage-architecture-core-specification/)
+
+  Check http://trustedcomputinggroup.org for latest specification updates.
+
+Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.<BR>
+SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef _TCG_STORAGE_CORE_H_
+#define _TCG_STORAGE_CORE_H_
+
+#include "tcg_uefi_compat.h"
+
+#pragma pack(1)
+
+/// UID in host native byte order
+typedef UINT64 TCG_UID;
+
+#define TCG_TO_UID(b0, b1, b2, b3, b4, b5, b6, b7)  (TCG_UID)(\
+  (UINT64)(b0)         | \
+  ((UINT64)(b1) << 8)  | \
+  ((UINT64)(b2) << 16) | \
+  ((UINT64)(b3) << 24) | \
+  ((UINT64)(b4) << 32) | \
+  ((UINT64)(b5) << 40) | \
+  ((UINT64)(b6) << 48) | \
+  ((UINT64)(b7) << 56))
+
+typedef struct {
+  UINT32    ReservedBE;
+  UINT16    ComIDBE;
+  UINT16    ComIDExtensionBE;
+  UINT32    OutstandingDataBE;
+  UINT32    MinTransferBE;
+  UINT32    LengthBE;
+  UINT8     Payload[0];
+} TCG_COM_PACKET;
+
+typedef struct {
+  UINT32    TperSessionNumberBE;
+  UINT32    HostSessionNumberBE;
+  UINT32    SequenceNumberBE;
+  UINT16    ReservedBE;
+  UINT16    AckTypeBE;
+  UINT32    AcknowledgementBE;
+  UINT32    LengthBE;
+  UINT8     Payload[0];
+} TCG_PACKET;
+
+#define TCG_SUBPACKET_ALIGNMENT  4// 4-byte alignment per spec
+
+typedef struct {
+  UINT8     ReservedBE[6];
+  UINT16    KindBE;
+  UINT32    LengthBE;
+  UINT8     Payload[0];
+} TCG_SUB_PACKET;
+
+#define SUBPACKET_KIND_DATA            0x0000
+#define SUBPACKET_KIND_CREDIT_CONTROL  0x8001
+
+#define TCG_ATOM_TYPE_INTEGER  0x0
+#define TCG_ATOM_TYPE_BYTE     0x1
+typedef struct {
+  UINT8    Data   : 6;
+  UINT8    Sign   : 1;
+  UINT8    IsZero : 1;
+} TCG_TINY_ATOM_BITS;
+
+typedef union {
+  UINT8                 Raw;
+  TCG_TINY_ATOM_BITS    TinyAtomBits;
+} TCG_SIMPLE_TOKEN_TINY_ATOM;
+
+typedef struct {
+  UINT8    Length     : 4;
+  UINT8    SignOrCont : 1;
+  UINT8    ByteOrInt  : 1;
+  UINT8    IsZero     : 1;
+  UINT8    IsOne      : 1;
+} TCG_SHORT_ATOM_BITS;
+
+typedef union {
+  UINT8                  RawHeader;
+  TCG_SHORT_ATOM_BITS    ShortAtomBits;
+} TCG_SIMPLE_TOKEN_SHORT_ATOM;
+
+#define TCG_MEDIUM_ATOM_LENGTH_HIGH_SHIFT  0x8
+#define TCG_MEDIUM_ATOM_LENGTH_HIGH_MASK   0x7
+
+typedef struct {
+  UINT8    LengthHigh : 3;
+  UINT8    SignOrCont : 1;
+  UINT8    ByteOrInt  : 1;
+  UINT8    IsZero     : 1;
+  UINT8    IsOne1     : 1;
+  UINT8    IsOne2     : 1;
+  UINT8    LengthLow;
+} TCG_MEDIUM_ATOM_BITS;
+
+typedef union {
+  UINT16                  RawHeader;
+  TCG_MEDIUM_ATOM_BITS    MediumAtomBits;
+} TCG_SIMPLE_TOKEN_MEDIUM_ATOM;
+
+#define TCG_LONG_ATOM_LENGTH_HIGH_SHIFT  16
+#define TCG_LONG_ATOM_LENGTH_MID_SHIFT   8
+
+typedef  struct {
+  UINT8    SignOrCont : 1;
+  UINT8    ByteOrInt  : 1;
+  UINT8    Reserved   : 2;
+  UINT8    IsZero     : 1;
+  UINT8    IsOne1     : 1;
+  UINT8    IsOne2     : 1;
+  UINT8    IsOne3     : 1;
+  UINT8    LengthHigh;
+  UINT8    LengthMid;
+  UINT8    LengthLow;
+} TCG_LONG_ATOM_BITS;
+
+typedef union {
+  UINT32                RawHeader;
+  TCG_LONG_ATOM_BITS    LongAtomBits;
+} TCG_SIMPLE_TOKEN_LONG_ATOM;
+
+// TCG Core Spec v2 - Table 04 - Token Types
+typedef enum {
+  TcgTokenTypeReserved,
+  TcgTokenTypeTinyAtom,
+  TcgTokenTypeShortAtom,
+  TcgTokenTypeMediumAtom,
+  TcgTokenTypeLongAtom,
+  TcgTokenTypeStartList,
+  TcgTokenTypeEndList,
+  TcgTokenTypeStartName,
+  TcgTokenTypeEndName,
+  TcgTokenTypeCall,
+  TcgTokenTypeEndOfData,
+  TcgTokenTypeEndOfSession,
+  TcgTokenTypeStartTransaction,
+  TcgTokenTypeEndTransaction,
+  TcgTokenTypeEmptyAtom,
+} TCG_TOKEN_TYPE;
+
+#pragma pack()
+
+#define TCG_TOKEN_SHORTATOM_MAX_BYTE_SIZE   0x0F
+#define TCG_TOKEN_MEDIUMATOM_MAX_BYTE_SIZE  0x7FF
+#define TCG_TOKEN_LONGATOM_MAX_BYTE_SIZE    0xFFFFFF
+
+#define TCG_TOKEN_TINYATOM_UNSIGNED_MAX_VALUE  0x3F
+#define TCG_TOKEN_TINYATOM_SIGNED_MAX_VALUE    0x1F
+#define TCG_TOKEN_TINYATOM_SIGNED_MIN_VALUE    -32
+
+// TOKEN TYPES
+#define TCG_TOKEN_TINYATOM          0x00
+#define TCG_TOKEN_TINYSIGNEDATOM    0x40
+#define TCG_TOKEN_SHORTATOM         0x80
+#define TCG_TOKEN_SHORTSIGNEDATOM   0x90
+#define TCG_TOKEN_SHORTBYTESATOM    0xA0
+#define TCG_TOKEN_MEDIUMATOM        0xC0
+#define TCG_TOKEN_MEDIUMSIGNEDATOM  0xC8
+#define TCG_TOKEN_MEDIUMBYTESATOM   0xD0
+#define TCG_TOKEN_LONGATOM          0xE0
+#define TCG_TOKEN_LONGSIGNEDATOM    0xE1
+#define TCG_TOKEN_LONGBYTESATOM     0xE2
+#define TCG_TOKEN_STARTLIST         0xF0
+#define TCG_TOKEN_ENDLIST           0xF1
+#define TCG_TOKEN_STARTNAME         0xF2
+#define TCG_TOKEN_ENDNAME           0xF3
+// 0xF4 - 0xF7 TCG Reserved
+#define TCG_TOKEN_CALL              0xF8
+#define TCG_TOKEN_ENDDATA           0xF9
+#define TCG_TOKEN_ENDSESSION        0xFA
+#define TCG_TOKEN_STARTTRANSACTION  0xFB
+#define TCG_TOKEN_ENDTRANSACTION    0xFC
+// 0xFD - 0xFE TCG Reserved
+#define TCG_TOKEN_EMPTY  0xFF
+
+// CELLBLOCK reserved Names
+#define TCG_CELL_BLOCK_TABLE_NAME         (UINT8)0x00
+#define TCG_CELL_BLOCK_START_ROW_NAME     (UINT8)0x01
+#define TCG_CELL_BLOCK_END_ROW_NAME       (UINT8)0x02
+#define TCG_CELL_BLOCK_START_COLUMN_NAME  (UINT8)0x03
+#define TCG_CELL_BLOCK_END_COLUMN_NAME    (UINT8)0x04
+
+// METHOD STATUS CODES
+#define TCG_METHOD_STATUS_CODE_SUCCESS                0x00
+#define TCG_METHOD_STATUS_CODE_NOT_AUTHORIZED         0x01
+#define TCG_METHOD_STATUS_CODE_OBSOLETE               0x02
+#define TCG_METHOD_STATUS_CODE_SP_BUSY                0x03
+#define TCG_METHOD_STATUS_CODE_SP_FAILED              0x04
+#define TCG_METHOD_STATUS_CODE_SP_DISABLED            0x05
+#define TCG_METHOD_STATUS_CODE_SP_FROZEN              0x06
+#define TCG_METHOD_STATUS_CODE_NO_SESSIONS_AVAILABLE  0x07
+#define TCG_METHOD_STATUS_CODE_UNIQUENESS_CONFLICT    0x08
+#define TCG_METHOD_STATUS_CODE_INSUFFICIENT_SPACE     0x09
+#define TCG_METHOD_STATUS_CODE_INSUFFICIENT_ROWS      0x0A
+#define TCG_METHOD_STATUS_CODE_INVALID_PARAMETER      0x0C
+#define TCG_METHOD_STATUS_CODE_OBSOLETE2              0x0D
+#define TCG_METHOD_STATUS_CODE_OBSOLETE3              0x0E
+#define TCG_METHOD_STATUS_CODE_TPER_MALFUNCTION       0x0F
+#define TCG_METHOD_STATUS_CODE_TRANSACTION_FAILURE    0x10
+#define TCG_METHOD_STATUS_CODE_RESPONSE_OVERFLOW      0x11
+#define TCG_METHOD_STATUS_CODE_AUTHORITY_LOCKED_OUT   0x12
+#define TCG_METHOD_STATUS_CODE_FAIL                   0x3F
+
+// Feature Codes
+#define TCG_FEATURE_INVALID             (UINT16)0x0000
+#define TCG_FEATURE_TPER                (UINT16)0x0001
+#define TCG_FEATURE_LOCKING             (UINT16)0x0002
+#define TCG_FEATURE_GEOMETRY_REPORTING  (UINT16)0x0003
+#define TCG_FEATURE_SINGLE_USER_MODE    (UINT16)0x0201
+#define TCG_FEATURE_DATASTORE_TABLE     (UINT16)0x0202
+#define TCG_FEATURE_OPAL_SSC_V1_0_0     (UINT16)0x0200
+#define TCG_FEATURE_OPAL_SSC_V2_0_0     (UINT16)0x0203
+#define TCG_FEATURE_OPAL_SSC_LITE       (UINT16)0x0301
+#define TCG_FEATURE_PYRITE_SSC          (UINT16)0x0302
+#define TCG_FEATURE_PYRITE_SSC_V2_0_0   (UINT16)0x0303
+#define TCG_FEATURE_BLOCK_SID           (UINT16)0x0402
+#define TCG_FEATURE_DATA_REMOVAL        (UINT16)0x0404
+
+// ACE Expression values
+#define TCG_ACE_EXPRESSION_AND  0x0
+#define TCG_ACE_EXPRESSION_OR   0x1
+
+/****************************************************************************
+TRUSTED RECEIVE - supported security protocols list (SP_Specific = 0000h)
+ATA 8 Rev6a Table 68 7.57.6.2
+****************************************************************************/
+// Security Protocol IDs
+#define TCG_SECURITY_PROTOCOL_INFO                    0x00
+#define TCG_OPAL_SECURITY_PROTOCOL_1                  0x01
+#define TCG_OPAL_SECURITY_PROTOCOL_2                  0x02
+#define TCG_SECURITY_PROTOCOL_TCG3                    0x03
+#define TCG_SECURITY_PROTOCOL_TCG4                    0x04
+#define TCG_SECURITY_PROTOCOL_TCG5                    0x05
+#define TCG_SECURITY_PROTOCOL_TCG6                    0x06
+#define TCG_SECURITY_PROTOCOL_CBCS                    0x07
+#define TCG_SECURITY_PROTOCOL_TAPE_DATA               0x20
+#define TCG_SECURITY_PROTOCOL_DATA_ENCRYPT_CONFIG     0x21
+#define TCG_SECURITY_PROTOCOL_SA_CREATION_CAPS        0x40
+#define TCG_SECURITY_PROTOCOL_IKEV2_SCSI              0x41
+#define TCG_SECURITY_PROTOCOL_JEDEC_UFS               0xEC
+#define TCG_SECURITY_PROTOCOL_SDCARD_SECURITY         0xED
+#define TCG_SECURITY_PROTOCOL_IEEE_1667               0xEE
+#define TCG_SECURITY_PROTOCOL_ATA_DEVICE_SERVER_PASS  0xEF
+
+// Security Protocol Specific IDs
+#define TCG_SP_SPECIFIC_PROTOCOL_LIST              0x0000
+#define TCG_SP_SPECIFIC_PROTOCOL_LEVEL0_DISCOVERY  0x0001
+
+#define TCG_RESERVED_COMID  0x0000
+
+// Defined in TCG Storage Feature Set:Block SID Authentication spec,
+// ComId used for BlockSid command is hardcode 0x0005.
+#define TCG_BLOCKSID_COMID  0x0005
+
+#pragma pack(1)
+typedef struct {
+  UINT8     Reserved[6];
+  UINT16    ListLength_BE; // 6 - 7
+  UINT8     List[504];     // 8...
+} TCG_SUPPORTED_SECURITY_PROTOCOLS;
+
+// Level 0 Discovery
+typedef struct {
+  UINT32    LengthBE; // number of valid bytes in discovery response, not including length field
+  UINT16    VerMajorBE;
+  UINT16    VerMinorBE;
+  UINT8     Reserved[8];
+  UINT8     VendorUnique[32];
+} TCG_LEVEL0_DISCOVERY_HEADER;
+
+typedef struct _TCG_LEVEL0_FEATURE_DESCRIPTOR_HEADER {
+  UINT16    FeatureCode_BE;
+  UINT8     Reserved : 4;
+  UINT8     Version  : 4;
+  UINT8     Length;  // length of feature dependent data in bytes
+} TCG_LEVEL0_FEATURE_DESCRIPTOR_HEADER;
+
+typedef struct {
+  TCG_LEVEL0_FEATURE_DESCRIPTOR_HEADER    Header;
+  UINT8                                   LockingSupported : 1;
+  UINT8                                   LockingEnabled   : 1; // means the locking security provider (SP) is enabled
+  UINT8                                   Locked           : 1; // means at least 1 locking range is enabled
+  UINT8                                   MediaEncryption  : 1;
+  UINT8                                   MbrEnabled       : 1;
+  UINT8                                   MbrDone          : 1;
+  UINT8                                   Reserved         : 2;
+  UINT8                                   Reserved515[11];
+} TCG_LOCKING_FEATURE_DESCRIPTOR;
+
+typedef struct {
+  TCG_LEVEL0_FEATURE_DESCRIPTOR_HEADER    Header;
+  UINT8                                   SIDValueState   : 1;
+  UINT8                                   SIDBlockedState : 1;
+  UINT8                                   Reserved4       : 6;
+  UINT8                                   HardwareReset   : 1;
+  UINT8                                   Reserved5       : 7;
+  UINT8                                   Reserved615[10];
+} TCG_BLOCK_SID_FEATURE_DESCRIPTOR;
+
+typedef struct {
+  TCG_LEVEL0_FEATURE_DESCRIPTOR_HEADER    Header;
+  UINT8                                   SyncSupported       : 1;
+  UINT8                                   AsyncSupported      : 1;
+  UINT8                                   AckNakSupported     : 1;
+  UINT8                                   BufferMgmtSupported : 1;
+  UINT8                                   StreamingSupported  : 1;
+  UINT8                                   Reserved4b5         : 1;
+  UINT8                                   ComIdMgmtSupported  : 1;
+  UINT8                                   Reserved4b7         : 1;
+  UINT8                                   Reserved515[11];
+} TCG_TPER_FEATURE_DESCRIPTOR;
+
+#pragma pack()
+
+// Special Purpose UIDs
+#define TCG_UID_NULL     TCG_TO_UID(0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00)
+#define TCG_UID_THIS_SP  TCG_TO_UID(0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01)
+#define TCG_UID_SMUID    TCG_TO_UID(0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFF)
+
+// Session Manager Method UIDS
+#define TCG_UID_SM_PROPERTIES             TCG_TO_UID(0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFF, 0x01)
+#define TCG_UID_SM_START_SESSION          TCG_TO_UID(0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFF, 0x02)
+#define TCG_UID_SM_SYNC_SESSION           TCG_TO_UID(0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFF, 0x03)
+#define TCG_UID_SM_START_TRUSTED_SESSION  TCG_TO_UID(0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFF, 0x04)
+#define TCG_UID_SM_SYNC_TRUSTED_SESSION   TCG_TO_UID(0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFF, 0x05)
+#define TCG_UID_SM_CLOSE_SESSION          TCG_TO_UID(0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFF, 0x06)
+
+// MethodID UIDs
+#define TCG_UID_METHOD_DELETE_SP          TCG_TO_UID(0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x00, 0x01)
+#define TCG_UID_METHOD_CREATE_TABLE       TCG_TO_UID(0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x00, 0x02)
+#define TCG_UID_METHOD_DELETE             TCG_TO_UID(0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x00, 0x03)
+#define TCG_UID_METHOD_CREATE_ROW         TCG_TO_UID(0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x00, 0x04)
+#define TCG_UID_METHOD_DELETE_ROW         TCG_TO_UID(0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x00, 0x05)
+#define TCG_UID_METHOD_NEXT               TCG_TO_UID(0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x00, 0x08)
+#define TCG_UID_METHOD_GET_FREE_SPACE     TCG_TO_UID(0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x00, 0x09)
+#define TCG_UID_METHOD_GET_FREE_ROWS      TCG_TO_UID(0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x00, 0x0A)
+#define TCG_UID_METHOD_DELETE_METHOD      TCG_TO_UID(0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x00, 0x0B)
+#define TCG_UID_METHOD_GET_ACL            TCG_TO_UID(0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x00, 0x0D)
+#define TCG_UID_METHOD_ADD_ACE            TCG_TO_UID(0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x00, 0x0E)
+#define TCG_UID_METHOD_REMOVE_ACE         TCG_TO_UID(0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x00, 0x0F)
+#define TCG_UID_METHOD_GEN_KEY            TCG_TO_UID(0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x00, 0x10)
+#define TCG_UID_METHOD_GET_PACKAGE        TCG_TO_UID(0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x00, 0x12)
+#define TCG_UID_METHOD_SET_PACKAGE        TCG_TO_UID(0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x00, 0x13)
+#define TCG_UID_METHOD_GET                TCG_TO_UID(0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x00, 0x16)
+#define TCG_UID_METHOD_SET                TCG_TO_UID(0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x00, 0x17)
+#define TCG_UID_METHOD_AUTHENTICATE       TCG_TO_UID(0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x00, 0x1C)
+#define TCG_UID_METHOD_ISSUE_SP           TCG_TO_UID(0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x02, 0x01)
+#define TCG_UID_METHOD_GET_CLOCK          TCG_TO_UID(0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x04, 0x01)
+#define TCG_UID_METHOD_RESET_CLOCK        TCG_TO_UID(0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x04, 0x02)
+#define TCG_UID_METHOD_SET_CLOCK_HIGH     TCG_TO_UID(0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x04, 0x03)
+#define TCG_UID_METHOD_SET_LAG_HIGH       TCG_TO_UID(0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x04, 0x04)
+#define TCG_UID_METHOD_SET_CLOCK_LOW      TCG_TO_UID(0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x04, 0x05)
+#define TCG_UID_METHOD_SET_LAG_LOW        TCG_TO_UID(0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFF, 0x06)
+#define TCG_UID_METHOD_INCREMENT_COUNTER  TCG_TO_UID(0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x04, 0x07)
+#define TCG_UID_METHOD_RANDOM             TCG_TO_UID(0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x06, 0x01)
+#define TCG_UID_METHOD_SALT               TCG_TO_UID(0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x06, 0x02)
+#define TCG_UID_METHOD_DECRYPT_INIT       TCG_TO_UID(0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x06, 0x03)
+#define TCG_UID_METHOD_DECRYPT            TCG_TO_UID(0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x06, 0x04)
+#define TCG_UID_METHOD_DECRYPT_FINALIZE   TCG_TO_UID(0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x06, 0x05)
+#define TCG_UID_METHOD_ENCRYPT_INIT       TCG_TO_UID(0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x06, 0x06)
+#define TCG_UID_METHOD_ENCRYPT            TCG_TO_UID(0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x06, 0x07)
+#define TCG_UID_METHOD_ENCRYPT_FINALIZE   TCG_TO_UID(0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x06, 0x08)
+#define TCG_UID_METHOD_HMAC_INIT          TCG_TO_UID(0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x06, 0x09)
+#define TCG_UID_METHOD_HMAC               TCG_TO_UID(0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x06, 0x0A)
+#define TCG_UID_METHOD_HMAC_FINALIZE      TCG_TO_UID(0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x06, 0x0B)
+#define TCG_UID_METHOD_HASH_INIT          TCG_TO_UID(0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x06, 0x0C)
+#define TCG_UID_METHOD_HASH               TCG_TO_UID(0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x06, 0x0D)
+#define TCG_UID_METHOD_HASH_FINALIZE      TCG_TO_UID(0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x06, 0x0E)
+#define TCG_UID_METHOD_SIGN               TCG_TO_UID(0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x06, 0x0F)
+#define TCG_UID_METHOD_VERIFY             TCG_TO_UID(0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x06, 0x10)
+#define TCG_UID_METHOD_XOR                TCG_TO_UID(0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x06, 0x11)
+#define TCG_UID_METHOD_ADD_LOG            TCG_TO_UID(0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x0A, 0x01)
+#define TCG_UID_METHOD_CREATE_LOG         TCG_TO_UID(0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x0A, 0x02)
+#define TCG_UID_METHOD_CLEAR_LOG          TCG_TO_UID(0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x0A, 0x03)
+#define TCG_UID_METHOD_FLUSH_LOG          TCG_TO_UID(0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x0A, 0x04)
+
+#endif // TCG_H_
diff --git a/src/vendorcode/intel/tcg_storage_core/tcg_storage_util.c b/src/vendorcode/intel/tcg_storage_core/tcg_storage_util.c
new file mode 100644
index 0000000000..db8ccff548
--- /dev/null
+++ b/src/vendorcode/intel/tcg_storage_core/tcg_storage_util.c
@@ -0,0 +1,901 @@
+/* SPDX-License-Identifier: BSD-2-Clause-Patent */
+
+#include "tcg_storage_core_lib.h"
+
+typedef struct {
+  UINT16                                  FeatureCode;
+  TCG_LEVEL0_FEATURE_DESCRIPTOR_HEADER    *Feature;
+  UINTN                                   FeatureSize;
+} TCG_FIND_FEATURE_CTX;
+
+/**
+  Returns a human-readable string representing a method status return code.
+
+  @param[in]  MethodStatus   Method status to translate to a string
+
+
+  @retval   return the string info.
+**/
+const CHAR8 *
+EFIAPI
+TcgMethodStatusString (
+  UINT8  MethodStatus
+  )
+{
+  switch (MethodStatus) {
+    #define C(status)  case TCG_METHOD_STATUS_CODE_ ## status: return #status
+    C (SUCCESS);
+    C (NOT_AUTHORIZED);
+    C (OBSOLETE);
+    C (SP_BUSY);
+    C (SP_FAILED);
+    C (SP_DISABLED);
+    C (SP_FROZEN);
+    C (NO_SESSIONS_AVAILABLE);
+    C (UNIQUENESS_CONFLICT);
+    C (INSUFFICIENT_SPACE);
+    C (INSUFFICIENT_ROWS);
+    C (INVALID_PARAMETER);
+    C (OBSOLETE2);
+    C (OBSOLETE3);
+    C (TPER_MALFUNCTION);
+    C (TRANSACTION_FAILURE);
+    C (RESPONSE_OVERFLOW);
+    C (AUTHORITY_LOCKED_OUT);
+    C (FAIL);
+    #undef C
+  }
+
+  return "unknown";
+}
+
+/**
+  adds call token and method Header (invoking id, and method id).
+
+  @param    CreateStruct             The input create structure.
+  @param    InvokingId               Invoking id.
+  @param    MethodId                 Method id.
+
+**/
+TCG_RESULT
+EFIAPI
+TcgStartMethodCall (
+  TCG_CREATE_STRUCT  *CreateStruct,
+  TCG_UID            InvokingId,
+  TCG_UID            MethodId
+  )
+{
+  NULL_CHECK (CreateStruct);
+
+  if ((CreateStruct->ComPacket == NULL) ||
+      (CreateStruct->CurPacket == NULL) ||
+      (CreateStruct->CurSubPacket == NULL)
+      )
+  {
+    DEBUG ((DEBUG_INFO, "unexpected state: ComPacket=%p CurPacket=%p CurSubPacket=%p\n", CreateStruct->ComPacket, CreateStruct->CurPacket, CreateStruct->CurSubPacket));
+    return (TcgResultFailureInvalidAction);
+  }
+
+  ERROR_CHECK (TcgAddCall (CreateStruct));
+  ERROR_CHECK (TcgAddTcgUid (CreateStruct, InvokingId));
+  ERROR_CHECK (TcgAddTcgUid (CreateStruct, MethodId));
+
+  return TcgResultSuccess;
+}
+
+/**
+  Adds START LIST token.
+
+  @param    CreateStruct        The input create structure.
+
+**/
+TCG_RESULT
+EFIAPI
+TcgStartParameters (
+  TCG_CREATE_STRUCT  *CreateStruct
+  )
+{
+  NULL_CHECK (CreateStruct);
+
+  if ((CreateStruct->ComPacket == NULL) ||
+      (CreateStruct->CurPacket == NULL) ||
+      (CreateStruct->CurSubPacket == NULL)
+      )
+  {
+    DEBUG ((DEBUG_INFO, "unexpected state: ComPacket=%p CurPacket=%p CurSubPacket=%p\n", CreateStruct->ComPacket, CreateStruct->CurPacket, CreateStruct->CurSubPacket));
+    return (TcgResultFailureInvalidAction);
+  }
+
+  return TcgAddStartList (CreateStruct);
+}
+
+/**
+  Adds END LIST token.
+
+  @param    CreateStruct        The input create structure.
+
+**/
+TCG_RESULT
+EFIAPI
+TcgEndParameters (
+  TCG_CREATE_STRUCT  *CreateStruct
+  )
+{
+  NULL_CHECK (CreateStruct);
+
+  if ((CreateStruct->ComPacket == NULL) ||
+      (CreateStruct->CurPacket == NULL) ||
+      (CreateStruct->CurSubPacket == NULL)
+      )
+  {
+    DEBUG ((DEBUG_INFO, "unexpected state: ComPacket=%p CurPacket=%p CurSubPacket=%p\n", CreateStruct->ComPacket, CreateStruct->CurPacket, CreateStruct->CurSubPacket));
+    return (TcgResultFailureInvalidAction);
+  }
+
+  return TcgAddEndList (CreateStruct);
+}
+
+/**
+  Adds END Data token and method list.
+
+  @param    CreateStruct        The input create structure.
+
+**/
+TCG_RESULT
+EFIAPI
+TcgEndMethodCall (
+  TCG_CREATE_STRUCT  *CreateStruct
+  )
+{
+  NULL_CHECK (CreateStruct);
+
+  if ((CreateStruct->ComPacket == NULL) ||
+      (CreateStruct->CurPacket == NULL) ||
+      (CreateStruct->CurSubPacket == NULL)
+      )
+  {
+    DEBUG ((DEBUG_INFO, "unexpected state: ComPacket=%p CurPacket=%p CurSubPacket=%p\n", CreateStruct->ComPacket, CreateStruct->CurPacket, CreateStruct->CurSubPacket));
+    return (TcgResultFailureInvalidAction);
+  }
+
+  ERROR_CHECK (TcgAddEndOfData (CreateStruct));
+
+  ERROR_CHECK (TcgAddStartList (CreateStruct));
+  ERROR_CHECK (TcgAddUINT8 (CreateStruct, 0x00));   // expected to complete properly
+  ERROR_CHECK (TcgAddUINT8 (CreateStruct, 0x00));   // reserved
+  ERROR_CHECK (TcgAddUINT8 (CreateStruct, 0x00));   // reserved
+  ERROR_CHECK (TcgAddEndList (CreateStruct));
+
+  return TcgResultSuccess;
+}
+
+/**
+  Retrieves the comID and Extended comID of the ComPacket in the Tcg response.
+  It is intended to be used to confirm the received Tcg response is intended for user that received it.
+
+  @param [in]        ParseStruct        Structure used to parse received TCG response.
+  @param [in/out]    ComId              comID retrieved from received ComPacket.
+  @param [in/out]    ComIdExtension     Extended comID retrieved from received ComPacket
+
+**/
+TCG_RESULT
+EFIAPI
+TcgGetComIds (
+  const TCG_PARSE_STRUCT  *ParseStruct,
+  UINT16                  *ComId,
+  UINT16                  *ComIdExtension
+  )
+{
+  NULL_CHECK (ParseStruct);
+  NULL_CHECK (ComId);
+  NULL_CHECK (ComIdExtension);
+
+  if (ParseStruct->ComPacket == NULL) {
+    DEBUG ((DEBUG_INFO, "unexpected state: ComPacket=%p\n", ParseStruct->ComPacket));
+    return TcgResultFailureInvalidAction;
+  }
+
+  *ComId          = SwapBytes16 (ParseStruct->ComPacket->ComIDBE);
+  *ComIdExtension = SwapBytes16 (ParseStruct->ComPacket->ComIDExtensionBE);
+
+  return TcgResultSuccess;
+}
+
+/**
+  Checks if the ComIDs of the response match the expected values.
+
+  @param[in]   ParseStruct               Structure used to parse received TCG response
+  @param[in]   ExpectedComId             Expected comID
+  @param[in]   ExpectedComIdExtension    Expected extended comID
+
+**/
+TCG_RESULT
+EFIAPI
+TcgCheckComIds (
+  const TCG_PARSE_STRUCT  *ParseStruct,
+  UINT16                  ExpectedComId,
+  UINT16                  ExpectedComIdExtension
+  )
+{
+  UINT16  ParseComId;
+  UINT16  ParseComIdExtension;
+
+  ERROR_CHECK (TcgGetComIds (ParseStruct, &ParseComId, &ParseComIdExtension));
+  if ((ParseComId != ExpectedComId) || (ParseComIdExtension != ExpectedComIdExtension)) {
+    DEBUG ((DEBUG_INFO, "Com ID: Actual 0x%02X Expected 0x%02X\n", ParseComId, ExpectedComId));
+    DEBUG ((DEBUG_INFO, "Extended Com ID: 0x%02X Expected 0x%02X\n", ParseComIdExtension, ExpectedComIdExtension));
+    return TcgResultFailure;
+  }
+
+  return TcgResultSuccess;
+}
+
+/**
+ Returns the method status of the current subpacket.  Does not affect the current position
+ in the ComPacket.  In other words, it can be called whenever you have a valid SubPacket.
+
+ @param [in/out]  ParseStruct       Structure used to parse received TCG response
+ @param [in/out]  MethodStatus      Method status retrieved of the current SubPacket
+
+**/
+TCG_RESULT
+EFIAPI
+TcgGetMethodStatus (
+  const TCG_PARSE_STRUCT  *ParseStruct,
+  UINT8                   *MethodStatus
+  )
+{
+  TCG_PARSE_STRUCT  TmpParseStruct;
+  TCG_TOKEN         TcgToken;
+  UINT8             Reserved1, Reserved2;
+
+  NULL_CHECK (ParseStruct);
+  NULL_CHECK (MethodStatus);
+
+  if ((ParseStruct->ComPacket == NULL) ||
+      (ParseStruct->CurPacket == NULL) ||
+      (ParseStruct->CurSubPacket == NULL)
+      )
+  {
+    DEBUG ((DEBUG_INFO, "unexpected state: ComPacket=%p CurPacket=%p CurSubPacket=%p\n", ParseStruct->ComPacket, ParseStruct->CurPacket, ParseStruct->CurSubPacket));
+    return TcgResultFailureInvalidAction;
+  }
+
+  // duplicate ParseStruct, then don't need to "reset" location cur ptr
+  CopyMem (&TmpParseStruct, ParseStruct, sizeof (TCG_PARSE_STRUCT));
+
+  // method status list exists after the end method call in the subpacket
+  // skip tokens until ENDDATA is found
+  do {
+    ERROR_CHECK (TcgGetNextToken (&TmpParseStruct, &TcgToken));
+  } while (TcgToken.Type != TcgTokenTypeEndOfData);
+
+  // only reach here if enddata is found
+  // at this point, the curptr is pointing at method status list beginning
+  ERROR_CHECK (TcgGetNextStartList (&TmpParseStruct));
+  ERROR_CHECK (TcgGetNextUINT8 (&TmpParseStruct, MethodStatus));
+  ERROR_CHECK (TcgGetNextUINT8 (&TmpParseStruct, &Reserved1));
+  ERROR_CHECK (TcgGetNextUINT8 (&TmpParseStruct, &Reserved2));
+  ERROR_CHECK (TcgGetNextEndList (&TmpParseStruct));
+
+  if (Reserved1 != 0) {
+    DEBUG ((DEBUG_INFO, "Method status reserved1 = 0x%02X (expected 0)\n", Reserved1));
+    return TcgResultFailure;
+  }
+
+  if (Reserved2 != 0) {
+    DEBUG ((DEBUG_INFO, "Method status reserved2 = 0x%02X (expected 0)\n", Reserved1));
+    return TcgResultFailure;
+  }
+
+  return TcgResultSuccess;
+}
+
+/**
+  Return the toke type string info.
+
+  @param    Type       Input the type info.
+
+  @retval   Return the string for this type.
+
+**/
+const CHAR8 *
+EFIAPI
+TcgTokenTypeString (
+  TCG_TOKEN_TYPE  Type
+  )
+{
+  switch (Type) {
+    case TcgTokenTypeReserved: return "Reserved";
+    case TcgTokenTypeTinyAtom: return "Tiny Atom";
+    case TcgTokenTypeShortAtom: return "Short Atom";
+    case TcgTokenTypeMediumAtom: return "Medium Atom";
+    case TcgTokenTypeLongAtom: return "Long Atom";
+    case TcgTokenTypeStartList: return "Start List";
+    case TcgTokenTypeEndList: return "End List";
+    case TcgTokenTypeStartName: return "Start Name";
+    case TcgTokenTypeEndName: return "End Name";
+    case TcgTokenTypeCall: return "Call";
+    case TcgTokenTypeEndOfData: return "End of Data";
+    case TcgTokenTypeEndOfSession: return "End of Session";
+    case TcgTokenTypeStartTransaction: return "Start Transaction";
+    case TcgTokenTypeEndTransaction: return "End Transaction";
+    case TcgTokenTypeEmptyAtom: return "Empty atom";
+  }
+
+  return "Unknown";
+}
+
+/**
+
+  Adds Start Session call to the data structure.  This creates the entire ComPacket structure and
+  returns the size of the entire compacket in the size parameter.
+
+  @param [in/out]    CreateStruct               Structure used to add the start session call
+  @param [in/out]    Size                       Describes the size of the entire ComPacket (header and payload). Filled out by function.
+  @param [in]        ComId                      ComID for the ComPacket
+  @param [in]        ComIdExtension             Extended ComID for the ComPacket
+  @param [in]        HostSessionId              Host Session ID
+  @param [in]        SpId                       Security Provider to start session with
+  @param [in]        Write                      Write option for start session.  TRUE = start session requests write access
+  @param [in]        HostChallengeLength        Length of the host challenge.  Length should be 0 if hostChallenge is NULL
+  @param [in]        HostChallenge              Host challenge for Host Signing Authority.  If NULL, then no Host Challenge shall be sent.
+  @param [in]        HostSigningAuthority       Host Signing Authority used for start session.  If NULL, then no Host Signing Authority shall be sent.
+
+**/
+TCG_RESULT
+EFIAPI
+TcgCreateStartSession (
+  TCG_CREATE_STRUCT  *CreateStruct,
+  UINT32             *Size,
+  UINT16             ComId,
+  UINT16             ComIdExtension,
+  UINT32             HostSessionId,
+  TCG_UID            SpId,
+  BOOLEAN            Write,
+  UINT32             HostChallengeLength,
+  const VOID         *HostChallenge,
+  TCG_UID            HostSigningAuthority
+  )
+{
+  ERROR_CHECK (TcgStartComPacket (CreateStruct, ComId, ComIdExtension));
+  ERROR_CHECK (TcgStartPacket (CreateStruct, 0x0, 0x0, 0x0, 0x0, 0x0));
+  ERROR_CHECK (TcgStartSubPacket (CreateStruct, 0x0));
+  ERROR_CHECK (TcgStartMethodCall (CreateStruct, TCG_UID_SMUID, TCG_UID_SM_START_SESSION));
+  ERROR_CHECK (TcgStartParameters (CreateStruct));
+  ERROR_CHECK (TcgAddUINT32 (CreateStruct, HostSessionId));
+  ERROR_CHECK (TcgAddTcgUid (CreateStruct, SpId));
+  ERROR_CHECK (TcgAddBOOLEAN (CreateStruct, Write));
+
+  // optional parameters
+  if ((HostChallenge != NULL) && (HostChallengeLength != 0)) {
+    ERROR_CHECK (TcgAddStartName (CreateStruct));
+    ERROR_CHECK (TcgAddUINT8 (CreateStruct, 0x00));   // TODO Create Enum for Method Optional Parameters?
+    ERROR_CHECK (TcgAddByteSequence (CreateStruct, HostChallenge, HostChallengeLength, FALSE));
+    ERROR_CHECK (TcgAddEndName (CreateStruct));
+  }
+
+  // optional parameters
+  if (HostSigningAuthority != 0) {
+    ERROR_CHECK (TcgAddStartName (CreateStruct));
+    ERROR_CHECK (TcgAddUINT8 (CreateStruct, 0x03));   // TODO Create Enum for Method Optional Parameters?
+    ERROR_CHECK (TcgAddTcgUid (CreateStruct, HostSigningAuthority));
+    ERROR_CHECK (TcgAddEndName (CreateStruct));
+  }
+
+  ERROR_CHECK (TcgEndParameters (CreateStruct));
+  ERROR_CHECK (TcgEndMethodCall (CreateStruct));
+  ERROR_CHECK (TcgEndSubPacket (CreateStruct));
+  ERROR_CHECK (TcgEndPacket (CreateStruct));
+  ERROR_CHECK (TcgEndComPacket (CreateStruct, Size));
+
+  return TcgResultSuccess;
+}
+
+/**
+ Parses the Sync Session response contained in the parseStruct to retrieve Tper session ID.  If the Sync Session response
+ parameters do not match the comID, extended ComID and host session ID then a failure is returned.
+
+ @param[in/out]   ParseStruct          Structure used to parse received TCG response, contains Sync Session response.
+ @param[in]       ComId                Expected ComID that is compared to actual ComID of response
+ @param[in]       ComIdExtension       Expected Extended ComID that is compared to actual Extended ComID of response
+ @param[in]       HostSessionId        Expected Host Session ID that is compared to actual  Host Session ID of response
+ @param[in/out]   TperSessionId        Tper Session ID retrieved from the Sync Session response.
+
+**/
+TCG_RESULT
+EFIAPI
+TcgParseSyncSession (
+  const TCG_PARSE_STRUCT  *ParseStruct,
+  UINT16                  ComId,
+  UINT16                  ComIdExtension,
+  UINT32                  HostSessionId,
+  UINT32                  *TperSessionId
+  )
+{
+  UINT8             MethodStatus;
+  TCG_PARSE_STRUCT  TmpParseStruct;
+  UINT16            ParseComId;
+  UINT16            ParseExtComId;
+  TCG_UID           InvokingUID;
+  TCG_UID           MethodUID;
+  UINT32            RecvHostSessionId;
+
+  NULL_CHECK (ParseStruct);
+  NULL_CHECK (TperSessionId);
+
+  CopyMem (&TmpParseStruct, ParseStruct, sizeof (TCG_PARSE_STRUCT));
+
+  // verify method status is good
+  ERROR_CHECK (TcgGetMethodStatus (&TmpParseStruct, &MethodStatus));
+  METHOD_STATUS_ERROR_CHECK (MethodStatus, TcgResultFailure);
+
+  // verify comids
+  ERROR_CHECK (TcgGetComIds (&TmpParseStruct, &ParseComId, &ParseExtComId));
+
+  if ((ComId != ParseComId) || (ComIdExtension != ParseExtComId)) {
+    DEBUG ((DEBUG_INFO, "unmatched comid (exp: 0x%X recv: 0x%X) or comid extension (exp: 0x%X recv: 0x%X)\n", ComId, ParseComId, ComIdExtension, ParseExtComId));
+    return TcgResultFailure;
+  }
+
+  ERROR_CHECK (TcgGetNextCall (&TmpParseStruct));
+  ERROR_CHECK (TcgGetNextTcgUid (&TmpParseStruct, &InvokingUID));
+  ERROR_CHECK (TcgGetNextTcgUid (&TmpParseStruct, &MethodUID));
+  ERROR_CHECK (TcgGetNextStartList (&TmpParseStruct));
+  ERROR_CHECK (TcgGetNextUINT32 (&TmpParseStruct, &RecvHostSessionId));
+  ERROR_CHECK (TcgGetNextUINT32 (&TmpParseStruct, TperSessionId));
+  ERROR_CHECK (TcgGetNextEndList (&TmpParseStruct));
+  ERROR_CHECK (TcgGetNextEndOfData (&TmpParseStruct));
+
+  if (InvokingUID != TCG_UID_SMUID) {
+    DEBUG ((DEBUG_INFO, "Invoking UID did not match UID_SMUID\n"));
+    return TcgResultFailure;
+  }
+
+  if (MethodUID != TCG_UID_SM_SYNC_SESSION) {
+    DEBUG ((DEBUG_INFO, "Method UID did not match UID_SM_SYNC_SESSION\n"));
+    return TcgResultFailure;
+  }
+
+  if (HostSessionId != RecvHostSessionId) {
+    DEBUG ((DEBUG_INFO, "unmatched HostSessionId (exp: 0x%X recv: 0x%X)\n", HostSessionId, RecvHostSessionId));
+    return TcgResultFailure;
+  }
+
+  return TcgResultSuccess;
+}
+
+/**
+
+  Creates ComPacket with EndSession.
+  This assumes a start session has already been opened.
+
+  @param  [in/out]    CreateStruct        Structure used to add Endsession
+  @param  [in/out]    Size                Describes the size of the entire ComPacket (header and payload). Filled out by function.
+  @param  [in]        ComId               ComID for the ComPacket
+  @param  [in]        ComIdExtension      Extended ComID for the ComPacket
+  @param  [in]        HostSessionId         Host Session ID for the Packet
+  @param  [in]        TpSessionId         Tper Session ID for the Packet
+
+**/
+TCG_RESULT
+EFIAPI
+TcgCreateEndSession (
+  TCG_CREATE_STRUCT  *CreateStruct,
+  UINT32             *Size,
+  UINT16             ComId,
+  UINT16             ComIdExtension,
+  UINT32             HostSessionId,
+  UINT32             TpSessionId
+  )
+{
+  ERROR_CHECK (TcgStartComPacket (CreateStruct, ComId, ComIdExtension));
+  ERROR_CHECK (TcgStartPacket (CreateStruct, TpSessionId, HostSessionId, 0x0, 0x0, 0x0));
+  ERROR_CHECK (TcgStartSubPacket (CreateStruct, 0x0));
+  ERROR_CHECK (TcgAddEndOfSession (CreateStruct));
+  ERROR_CHECK (TcgEndSubPacket (CreateStruct));
+  ERROR_CHECK (TcgEndPacket (CreateStruct));
+  ERROR_CHECK (TcgEndComPacket (CreateStruct, Size));
+
+  return TcgResultSuccess;
+}
+
+/**
+  Set start method.
+
+  @param     CreateStruct   Input create structure.
+  @param     Row            Input the row info.
+  @param     ColumnNumber   the column info.
+
+**/
+static TCG_RESULT
+EFIAPI
+TcgStartMethodSet (
+  TCG_CREATE_STRUCT  *CreateStruct,
+  TCG_UID            Row,
+  UINT32             ColumnNumber
+  )
+{
+  ERROR_CHECK (TcgStartMethodCall (CreateStruct, Row, TCG_UID_METHOD_SET));
+  ERROR_CHECK (TcgStartParameters (CreateStruct));
+  ERROR_CHECK (TcgAddStartName (CreateStruct));
+  ERROR_CHECK (TcgAddUINT8 (CreateStruct, 0x01)); // "Values"
+  ERROR_CHECK (TcgAddStartList (CreateStruct));
+  ERROR_CHECK (TcgAddStartName (CreateStruct));
+  ERROR_CHECK (TcgAddUINT32 (CreateStruct, ColumnNumber));
+  return TcgResultSuccess;
+}
+
+/**
+  Set end method.
+
+  @param     CreateStruct  Input create structure.
+
+**/
+static TCG_RESULT
+EFIAPI
+TcgEndMethodSet (
+  TCG_CREATE_STRUCT  *CreateStruct
+  )
+{
+  ERROR_CHECK (TcgAddEndName (CreateStruct));
+  ERROR_CHECK (TcgAddEndList (CreateStruct));
+  ERROR_CHECK (TcgAddEndName (CreateStruct));
+  ERROR_CHECK (TcgEndParameters (CreateStruct));
+  ERROR_CHECK (TcgEndMethodCall (CreateStruct));
+  return TcgResultSuccess;
+}
+
+/**
+  Creates ComPacket with a Method call that sets the PIN column for the row specified.
+  This assumes a start session has already been opened with the desired SP.
+
+  @param [in/out]   CreateStruct           Structure used to add method call.
+  @param [in/out]   Size                   Describes the size of the entire ComPacket (header and payload). Filled out by function.
+  @param [in]       ComId                  ComID for the ComPacket
+  @param [in]       ComIdExtension         Extended ComID for the ComPacket
+  @param [in]       TperSession            Tper Session ID for the Packet
+  @param [in]       HostSession            Host Session ID for the Packet
+  @param [in]       SidRow                 UID of row of current SP to set PIN column
+  @param [in]       Password               value of PIN to set
+  @param [in]       PasswordSize           Size of PIN
+
+**/
+TCG_RESULT
+EFIAPI
+TcgCreateSetCPin (
+  TCG_CREATE_STRUCT  *CreateStruct,
+  UINT32             *Size,
+  UINT16             ComId,
+  UINT16             ComIdExtension,
+  UINT32             TperSession,
+  UINT32             HostSession,
+  TCG_UID            SidRow,
+  const VOID         *Password,
+  UINT32             PasswordSize
+  )
+{
+  // set new SID Password
+  ERROR_CHECK (TcgStartComPacket (CreateStruct, ComId, ComIdExtension));
+  ERROR_CHECK (TcgStartPacket (CreateStruct, TperSession, HostSession, 0x0, 0x0, 0x0));
+  ERROR_CHECK (TcgStartSubPacket (CreateStruct, 0x0));
+  ERROR_CHECK (TcgStartMethodSet (CreateStruct, SidRow, 0x03)); // "PIN"
+  ERROR_CHECK (TcgAddByteSequence (CreateStruct, Password, PasswordSize, FALSE));
+  ERROR_CHECK (TcgEndMethodSet (CreateStruct));
+  ERROR_CHECK (TcgEndSubPacket (CreateStruct));
+  ERROR_CHECK (TcgEndPacket (CreateStruct));
+  ERROR_CHECK (TcgEndComPacket (CreateStruct, Size));
+  return TcgResultSuccess;
+}
+
+/**
+ Creates ComPacket with a Method call that sets the "Enabled" column for the row specified using the value specified.
+ This assumes a start session has already been opened with the desired SP.
+
+ @param [in/out]  CreateStruct          Structure used to add method call
+ @param [in/out]  Size                  Describes the size of the entire ComPacket (header and payload). Filled out by function.
+ @param [in]      ComId                 ComID for the ComPacket
+ @param [in]      ComIdExtension        Extended ComID for the ComPacket
+ @param [in]      TperSession           Tper Session ID for the Packet
+ @param [in]      HostSession           Host Session ID for the Packet
+ @param [in]      AuthorityUid          Authority UID to modify the "Enabled" column for
+ @param [in]      Enabled               Value to set the "Enabled" column to
+
+**/
+TCG_RESULT
+EFIAPI
+TcgSetAuthorityEnabled (
+  TCG_CREATE_STRUCT  *CreateStruct,
+  UINT32             *Size,
+  UINT16             ComId,
+  UINT16             ComIdExtension,
+  UINT32             TperSession,
+  UINT32             HostSession,
+  TCG_UID            AuthorityUid,
+  BOOLEAN            Enabled
+  )
+{
+  ERROR_CHECK (TcgStartComPacket (CreateStruct, ComId, ComIdExtension));
+  ERROR_CHECK (TcgStartPacket (CreateStruct, TperSession, HostSession, 0x0, 0x0, 0x0));
+  ERROR_CHECK (TcgStartSubPacket (CreateStruct, 0x0));
+  ERROR_CHECK (TcgStartMethodSet (CreateStruct, AuthorityUid, 0x05)); // "Enabled"
+  ERROR_CHECK (TcgAddBOOLEAN (CreateStruct, Enabled));
+  ERROR_CHECK (TcgEndMethodSet (CreateStruct));
+  ERROR_CHECK (TcgEndSubPacket (CreateStruct));
+  ERROR_CHECK (TcgEndPacket (CreateStruct));
+  ERROR_CHECK (TcgEndComPacket (CreateStruct, Size));
+  return TcgResultSuccess;
+}
+
+/**
+  Create set ace.
+
+  @param     CreateStruct      Input create structure.
+  @param     Size              size info.
+  @param     ComId             ComId info.
+  @param     ComIdExtension    ComId extension info.
+  @param     TperSession       Tper session data.
+  @param     HostSession       Host session data.
+  @param     AceRow            Ace row info.
+  @param     Authority1        Authority 1 info.
+  @param     LogicalOperator   Logical operator info.
+  @param     Authority2        Authority 2 info.
+
+  @retval    Return the action result.
+
+**/
+TCG_RESULT
+EFIAPI
+TcgCreateSetAce (
+  TCG_CREATE_STRUCT  *CreateStruct,
+  UINT32             *Size,
+  UINT16             ComId,
+  UINT16             ComIdExtension,
+  UINT32             TperSession,
+  UINT32             HostSession,
+  TCG_UID            AceRow,
+  TCG_UID            Authority1,
+  BOOLEAN            LogicalOperator,
+  TCG_UID            Authority2
+  )
+{
+  UINT8  HalfUidAuthorityObjectRef[4];
+  UINT8  HalfUidBooleanAce[4];
+
+  HalfUidAuthorityObjectRef[0] = 0x0;
+  HalfUidAuthorityObjectRef[1] = 0x0;
+  HalfUidAuthorityObjectRef[2] = 0xC;
+  HalfUidAuthorityObjectRef[3] = 0x5;
+
+  HalfUidBooleanAce[0] = 0x0;
+  HalfUidBooleanAce[1] = 0x0;
+  HalfUidBooleanAce[2] = 0x4;
+  HalfUidBooleanAce[3] = 0xE;
+
+  ERROR_CHECK (TcgStartComPacket (CreateStruct, ComId, ComIdExtension));
+  ERROR_CHECK (TcgStartPacket (CreateStruct, TperSession, HostSession, 0x0, 0x0, 0x0));
+  ERROR_CHECK (TcgStartSubPacket (CreateStruct, 0x0));
+  ERROR_CHECK (TcgStartMethodSet (CreateStruct, AceRow, 0x03));     // "BooleanExpr"
+  ERROR_CHECK (TcgAddStartList (CreateStruct));
+  ERROR_CHECK (TcgAddStartName (CreateStruct));
+  ERROR_CHECK (TcgAddByteSequence (CreateStruct, HalfUidAuthorityObjectRef, sizeof (HalfUidAuthorityObjectRef), FALSE));
+  ERROR_CHECK (TcgAddTcgUid (CreateStruct, Authority1));
+  ERROR_CHECK (TcgAddEndName (CreateStruct));
+  ERROR_CHECK (TcgAddStartName (CreateStruct));
+  ERROR_CHECK (TcgAddByteSequence (CreateStruct, HalfUidAuthorityObjectRef, sizeof (HalfUidAuthorityObjectRef), FALSE));
+  ERROR_CHECK (TcgAddTcgUid (CreateStruct, Authority2));
+  ERROR_CHECK (TcgAddEndName (CreateStruct));
+
+  ERROR_CHECK (TcgAddStartName (CreateStruct));
+  ERROR_CHECK (TcgAddByteSequence (CreateStruct, HalfUidBooleanAce, sizeof (HalfUidBooleanAce), FALSE));
+  ERROR_CHECK (TcgAddBOOLEAN (CreateStruct, LogicalOperator));
+  ERROR_CHECK (TcgAddEndName (CreateStruct));
+  ERROR_CHECK (TcgAddEndList (CreateStruct));
+  ERROR_CHECK (TcgEndMethodSet (CreateStruct));
+  ERROR_CHECK (TcgEndSubPacket (CreateStruct));
+  ERROR_CHECK (TcgEndPacket (CreateStruct));
+  ERROR_CHECK (TcgEndComPacket (CreateStruct, Size));
+  return TcgResultSuccess;
+}
+
+/**
+  Enum level 0 discovery.
+
+  @param     DiscoveryHeader   Discovery header.
+  @param     Callback          Callback function.
+  @param     Context           The context for the function.
+
+  @retval    return true if the callback return TRUE, else return FALSE.
+
+**/
+BOOLEAN
+EFIAPI
+TcgEnumLevel0Discovery (
+  const TCG_LEVEL0_DISCOVERY_HEADER  *DiscoveryHeader,
+  TCG_LEVEL0_ENUM_CALLBACK           Callback,
+  VOID                               *Context
+  )
+{
+  UINT32                                BytesLeft;
+  const UINT8                           *DiscoveryBufferPtr;
+  UINT32                                FeatLength;
+  TCG_LEVEL0_FEATURE_DESCRIPTOR_HEADER  *Feat;
+
+  //
+  // Total bytes including descriptors but not including the Length field
+  //
+  BytesLeft = SwapBytes32 (DiscoveryHeader->LengthBE);
+
+  //
+  // If discovery Header is not valid, exit
+  //
+  if (BytesLeft == 0) {
+    return FALSE;
+  }
+
+  //
+  // Subtract the Length of the Header, except the Length field, which is not included
+  //
+  BytesLeft -= (sizeof (TCG_LEVEL0_DISCOVERY_HEADER) - sizeof (DiscoveryHeader->LengthBE));
+
+  //
+  // Move ptr to first descriptor
+  //
+  DiscoveryBufferPtr = (const UINT8 *)DiscoveryHeader + sizeof (TCG_LEVEL0_DISCOVERY_HEADER);
+
+  while (BytesLeft > sizeof (TCG_LEVEL0_FEATURE_DESCRIPTOR_HEADER)) {
+    //
+    // Pointer to beginning of descriptor (including common Header)
+    //
+    Feat = (TCG_LEVEL0_FEATURE_DESCRIPTOR_HEADER *)DiscoveryBufferPtr;
+
+    FeatLength = Feat->Length + sizeof (TCG_LEVEL0_FEATURE_DESCRIPTOR_HEADER);
+
+    //
+    // Not enough bytes left for Feature descriptor
+    //
+    if (BytesLeft < FeatLength) {
+      break;
+    }
+
+    //
+    // Report the Feature to the callback
+    //
+    if (Callback (DiscoveryHeader, Feat, FeatLength, Context)) {
+      return TRUE;
+    }
+
+    //
+    // Descriptor Length only describes Data after common Header
+    //
+    BytesLeft          -= FeatLength;
+    DiscoveryBufferPtr += FeatLength;
+  }
+
+  return FALSE;
+}
+
+/**
+  The callback function for Get Feature function.
+
+  @param     DiscoveryHeader   Input discovery header.
+  @param     Feature           Input Feature.
+  @param     FeatureSize       Input Feature size.
+  @param     Context           The context.
+
+**/
+static BOOLEAN
+EFIAPI
+TcgFindFeatureCallback (
+  const TCG_LEVEL0_DISCOVERY_HEADER     *DiscoveryHeader,
+  TCG_LEVEL0_FEATURE_DESCRIPTOR_HEADER  *Feature,
+  UINTN                                 FeatureSize,
+  VOID                                  *Context
+  )
+{
+  TCG_FIND_FEATURE_CTX  *FindCtx;
+
+  FindCtx = (TCG_FIND_FEATURE_CTX *)Context;
+  if ( SwapBytes16 (Feature->FeatureCode_BE) == FindCtx->FeatureCode ) {
+    FindCtx->Feature     = Feature;
+    FindCtx->FeatureSize = FeatureSize;
+    return TRUE; // done enumerating features
+  }
+
+  return FALSE; // continue enumerating
+}
+
+/**
+  Get Feature code from the header.
+
+  @param     DiscoveryHeader    The discovery header.
+  @param     FeatureCode        return the Feature code.
+  @param     FeatureSize        return the Feature size.
+
+  @retval    return the Feature code data.
+**/
+TCG_LEVEL0_FEATURE_DESCRIPTOR_HEADER *
+EFIAPI
+TcgGetFeature (
+  const TCG_LEVEL0_DISCOVERY_HEADER  *DiscoveryHeader,
+  UINT16                             FeatureCode,
+  UINTN                              *FeatureSize
+  )
+{
+  TCG_FIND_FEATURE_CTX  FindCtx;
+
+  FindCtx.FeatureCode = FeatureCode;
+  FindCtx.Feature     = NULL;
+  FindCtx.FeatureSize = 0;
+
+  TcgEnumLevel0Discovery (DiscoveryHeader, TcgFindFeatureCallback, &FindCtx);
+  if (FeatureSize != NULL) {
+    *FeatureSize = FindCtx.FeatureSize;
+  }
+
+  return FindCtx.Feature;
+}
+
+/**
+  Determines if the protocol provided is part of the provided supported protocol list.
+
+  @param[in]  ProtocolList     Supported protocol list to investigate
+  @param[in]  Protocol         Protocol value to determine if supported
+
+  @return TRUE = protocol is supported, FALSE = protocol is not supported
+**/
+BOOLEAN
+EFIAPI
+TcgIsProtocolSupported (
+  const TCG_SUPPORTED_SECURITY_PROTOCOLS  *ProtocolList,
+  UINT16                                  Protocol
+  )
+{
+  UINT16  Index;
+  UINT16  ListLength;
+
+  ListLength = SwapBytes16 (ProtocolList->ListLength_BE);
+
+  if (ListLength > sizeof (ProtocolList->List)) {
+    DEBUG ((DEBUG_INFO, "WARNING: list Length is larger than max allowed Value; truncating\n"));
+    ListLength = sizeof (ProtocolList->List);
+  }
+
+  for (Index = 0; Index < ListLength; Index++) {
+    if (ProtocolList->List[Index] == Protocol) {
+      return TRUE;
+    }
+  }
+
+  return FALSE;
+}
+
+/**
+  Check whether lock or not.
+
+  @param     Discovery
+
+  @retval    TRUE if lock, FALSE if not lock.
+**/
+BOOLEAN
+EFIAPI
+TcgIsLocked (
+  const TCG_LEVEL0_DISCOVERY_HEADER  *Discovery
+  )
+{
+  UINTN                           Size;
+  TCG_LOCKING_FEATURE_DESCRIPTOR  *LockDescriptor;
+
+  Size           = 0;
+  LockDescriptor = (TCG_LOCKING_FEATURE_DESCRIPTOR *)TcgGetFeature (Discovery, TCG_FEATURE_LOCKING, &Size);
+
+  if ((LockDescriptor != NULL) && (Size >= sizeof (*LockDescriptor))) {
+    DEBUG ((DEBUG_INFO, "locked: %d\n", LockDescriptor->Locked));
+    return LockDescriptor->Locked;
+  }
+
+  //
+  // Descriptor was not found
+  //
+  return FALSE;
+}
diff --git a/src/vendorcode/intel/tcg_storage_core/tcg_uefi_compat.h b/src/vendorcode/intel/tcg_storage_core/tcg_uefi_compat.h
new file mode 100644
index 0000000000..e81690fb9d
--- /dev/null
+++ b/src/vendorcode/intel/tcg_storage_core/tcg_uefi_compat.h
@@ -0,0 +1,60 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef VENDORCODE_INTEL_TCG_STORAGE_CORE_UEFI_COMPAT_H
+#define VENDORCODE_INTEL_TCG_STORAGE_CORE_UEFI_COMPAT_H
+
+#include <string.h>
+#include <types.h>
+
+typedef u8  UINT8;
+typedef u16 UINT16;
+typedef u32 UINT32;
+typedef u64 UINT64;
+typedef s8  INT8;
+typedef s16 INT16;
+typedef s32 INT32;
+typedef s64 INT64;
+typedef char CHAR8;
+typedef size_t UINTN;
+typedef ptrdiff_t INTN;
+typedef void VOID;
+typedef bool BOOLEAN;
+
+#ifndef TRUE
+#define TRUE true
+#endif
+#ifndef FALSE
+#define FALSE false
+#endif
+
+#define EFIAPI
+
+#define CopyMem(d, s, n) memcpy((d), (s), (n))
+#define ZeroMem(d, n) memset((d), 0, (n))
+
+static inline UINT16 SwapBytes16(UINT16 v) { return __builtin_bswap16(v); }
+static inline UINT32 SwapBytes32(UINT32 v) { return __builtin_bswap32(v); }
+static inline UINT64 SwapBytes64(UINT64 v) { return __builtin_bswap64(v); }
+
+static inline UINT64 LShiftU64(UINT64 v, UINTN n) { return v << n; }
+
+#ifndef MAX_UINT8
+#define MAX_UINT8  ((UINT8)0xff)
+#endif
+#ifndef MAX_UINT16
+#define MAX_UINT16 ((UINT16)0xffff)
+#endif
+#ifndef MAX_UINT32
+#define MAX_UINT32 ((UINT32)0xffffffffu)
+#endif
+
+/* Keep DEBUG() calls compile-time silent in SMM. */
+#define DEBUG_INFO  0
+#define DEBUG_WARN  0
+#define DEBUG_ERROR 0
+#define DEBUG_LINE_NUMBER __LINE__
+#define DEBUG(x) do { } while (0)
+
+#define ASSERT(x) do { } while (0)
+
+#endif

From 9a40f080aca4de87fc30552e3c65cd9d6309ecaa Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Wed, 11 Mar 2026 16:06:10 -0500
Subject: [PATCH 3726/3886] security/tcg/opal_s3: add OPAL NVMe Security
 Send/Receive helpers

Add the minimal NVMe admin queue and Security Send/Receive helper code
used by the SMM resume unlock path.

TEST=tested with rest of patch train

Change-Id: Iaf4a9e23d399a093139edffc724f2b2661ca3bb1
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91657
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
---
 src/security/tcg/opal_s3/Makefile.mk   |   1 +
 src/security/tcg/opal_s3/opal_nvme.c   | 305 +++++++++++++++++++++++++
 src/security/tcg/opal_s3/opal_nvme.h   |  41 ++++
 src/security/tcg/opal_s3/opal_secure.h |  23 ++
 4 files changed, 370 insertions(+)
 create mode 100644 src/security/tcg/opal_s3/opal_nvme.c
 create mode 100644 src/security/tcg/opal_s3/opal_nvme.h
 create mode 100644 src/security/tcg/opal_s3/opal_secure.h

diff --git a/src/security/tcg/opal_s3/Makefile.mk b/src/security/tcg/opal_s3/Makefile.mk
index 625d719d59..9661b1a213 100644
--- a/src/security/tcg/opal_s3/Makefile.mk
+++ b/src/security/tcg/opal_s3/Makefile.mk
@@ -2,5 +2,6 @@
 
 CPPFLAGS_common-$(CONFIG_TCG_OPAL_S3_UNLOCK) += -I$(src)/vendorcode/intel/tcg_storage_core
 
+smm-$(CONFIG_TCG_OPAL_S3_UNLOCK) += opal_nvme.c
 smm-$(CONFIG_TCG_OPAL_S3_UNLOCK) += ../../../vendorcode/intel/tcg_storage_core/tcg_storage_core.c
 smm-$(CONFIG_TCG_OPAL_S3_UNLOCK) += ../../../vendorcode/intel/tcg_storage_core/tcg_storage_util.c
diff --git a/src/security/tcg/opal_s3/opal_nvme.c b/src/security/tcg/opal_s3/opal_nvme.c
new file mode 100644
index 0000000000..4623eaa196
--- /dev/null
+++ b/src/security/tcg/opal_s3/opal_nvme.c
@@ -0,0 +1,305 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include "opal_nvme.h"
+
+#include <console/console.h>
+#include <commonlib/bsd/helpers.h>
+#include <cpu/x86/smm.h>
+#include <delay.h>
+#include <device/mmio.h>
+#include <device/pci_def.h>
+#include <device/pci_ops.h>
+#include <string.h>
+#include <timer.h>
+
+#define NVME_ADMIN_SECURITY_SEND_CMD	0x81
+#define NVME_ADMIN_SECURITY_RECV_CMD	0x82
+
+#define NVME_CC_EN		(1U << 0)
+#define NVME_CC_CSS_NVM		(0U << 4)
+#define NVME_CC_MPS_4K		(0U << 7)
+#define NVME_CC_AMS_RR		(0U << 11)
+#define NVME_CC_SHN_NONE	(0U << 14)
+#define NVME_CC_IOSQES_64B	(6U << 16)
+#define NVME_CC_IOCQES_16B	(4U << 20)
+
+#define NVME_QUEUE_SIZE		2
+#define NVME_PAGE_SIZE		4096U
+#define NVME_SCRATCH_PAGES	3U
+#define NVME_SCRATCH_MIN_BYTES	(NVME_SCRATCH_PAGES * NVME_PAGE_SIZE)
+
+#define NVME_REGS_MIN_SIZE	0x2000U
+
+struct nvme_sq_entry {
+	u32 dw[16];
+};
+
+struct nvme_cq_entry {
+	u32 dw[4];
+};
+
+/* Use the public definition from opal_nvme.h. */
+
+static int nvme_wait_ready(u8 *regs, bool ready)
+{
+	const u64 cap = read64(regs + 0x0);
+	const int timeout_units = (cap >> 24) & 0xff;
+	int timeout_ms = MAX(timeout_units, 1) * 500;
+	struct stopwatch sw;
+
+	stopwatch_init_msecs_expire(&sw, timeout_ms);
+	while (!stopwatch_expired(&sw)) {
+		const u32 csts = read32(regs + 0x1c);
+		const bool rdy = !!(csts & 0x1);
+		const bool cfs = !!(csts & 0x2);
+
+		if (cfs)
+			return -1;
+		if (rdy == ready)
+			return 0;
+
+		mdelay(10);
+	}
+
+	return -1;
+}
+
+static int nvme_read_bar0(pci_devfn_t dev, u64 *bar_out)
+{
+	const u32 bar_low = pci_read_config32(dev, PCI_BASE_ADDRESS_0);
+	const bool is_mem = ((bar_low & PCI_BASE_ADDRESS_SPACE) == PCI_BASE_ADDRESS_SPACE_MEMORY);
+	const bool is_64 = ((bar_low & PCI_BASE_ADDRESS_MEM_LIMIT_MASK) ==
+				    PCI_BASE_ADDRESS_MEM_LIMIT_64);
+	u64 bar;
+
+	/*
+	 * Callers must ensure memory decoding is enabled before attempting to
+	 * access the BAR.
+	 */
+	if (!(pci_read_config16(dev, PCI_COMMAND) & PCI_COMMAND_MEMORY))
+		return -1;
+
+	if (bar_low == 0xffffffff)
+		return -1;
+
+	if (!is_mem)
+		return -1;
+
+	bar = bar_low & ~PCI_BASE_ADDRESS_MEM_ATTR_MASK;
+	if (is_64) {
+		const u32 bar_high = pci_read_config32(dev, PCI_BASE_ADDRESS_0 + 4);
+		bar |= ((u64)bar_high) << 32;
+
+		if (!ENV_X86_64 && bar_high)
+			return -1;
+	}
+
+	if (!bar)
+		return -1;
+
+	if (bar > (u64)(uintptr_t)~0)
+		return -1;
+
+	if (smm_points_to_smram((void *)(uintptr_t)bar, NVME_REGS_MIN_SIZE))
+		return -1;
+
+	*bar_out = bar;
+	return 0;
+}
+
+static int nvme_admin_cmd(struct opal_nvme *nvme, const struct nvme_sq_entry *cmd)
+{
+	struct nvme_sq_entry *s = &nvme->sq[nvme->sq_tail];
+	struct nvme_cq_entry *c = &nvme->cq[nvme->cq_head];
+	struct stopwatch sw;
+	bool timed_out = false;
+
+	memcpy(s, cmd, sizeof(*cmd));
+	nvme->sq_tail = (nvme->sq_tail + 1) & (NVME_QUEUE_SIZE - 1);
+	write32(nvme->sq_db, nvme->sq_tail);
+
+	/* Wait for phase toggle indicating a new completion entry. */
+	stopwatch_init_msecs_expire(&sw, 1000);
+	while ((((read32(&c->dw[3]) >> 16) & 0x1) == nvme->cq_phase)) {
+		if (stopwatch_expired(&sw)) {
+			timed_out = true;
+			break;
+		}
+		mdelay(1);
+	}
+
+	if (timed_out) {
+		printk(BIOS_ERR, "OPAL NVMe: admin cmd timeout\n");
+		return -1;
+	}
+
+	nvme->cq_head = (nvme->cq_head + 1) & (NVME_QUEUE_SIZE - 1);
+	write32(nvme->cq_db, nvme->cq_head);
+	if (nvme->cq_head == 0)
+		nvme->cq_phase ^= 1;
+
+	/* DW3 bits 31:17 are Status Field (SC + SCT + etc). */
+	return (int)(c->dw[3] >> 17);
+}
+
+int opal_nvme_init(struct opal_nvme *nvme, pci_devfn_t dev, void *scratch, size_t scratch_size)
+{
+	u64 regs;
+	u16 pmcap;
+	u8 *p = scratch;
+	u32 cc;
+	u32 csts;
+
+	memset(nvme, 0, sizeof(*nvme));
+	nvme->dev = dev;
+
+	if (pci_read_config16(dev, PCI_VENDOR_ID) == 0xffff)
+		return -1;
+
+	if (scratch_size < NVME_SCRATCH_MIN_BYTES)
+		return -1;
+
+	p = (u8 *)ALIGN_UP((uintptr_t)p, NVME_PAGE_SIZE);
+	if ((uintptr_t)p + NVME_SCRATCH_MIN_BYTES > (uintptr_t)scratch + scratch_size)
+		return -1;
+
+	nvme->sq = (struct nvme_sq_entry *)p;
+	p += NVME_PAGE_SIZE;
+	nvme->cq = (struct nvme_cq_entry *)p;
+	p += NVME_PAGE_SIZE;
+
+	/* Bring device to D0 if it supports PM capability. */
+	pmcap = pci_s_find_capability(dev, PCI_CAP_ID_PM);
+	if (pmcap) {
+		u16 pmcsr = pci_read_config16(dev, pmcap + PCI_PM_CTRL);
+		if ((pmcsr & PCI_PM_CTRL_STATE_MASK) != PCI_PM_CTRL_POWER_STATE_D0) {
+			pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
+			pci_write_config16(dev, pmcap + PCI_PM_CTRL, pmcsr);
+			udelay(1000);
+		}
+	}
+
+	pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
+
+	if (nvme_read_bar0(dev, &regs)) {
+		printk(BIOS_ERR, "OPAL NVMe: invalid BAR0\n");
+		pci_and_config16(dev, PCI_COMMAND, ~(PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER));
+		return -1;
+	}
+
+	nvme->regs = (u8 *)(uintptr_t)regs;
+	nvme->cap = read64(nvme->regs + 0x0);
+	nvme->dstrd_bytes = 4U << ((nvme->cap >> 32) & 0xf);
+	nvme->sq_db = (u32 *)(nvme->regs + 0x1000 + (0 * nvme->dstrd_bytes));
+	nvme->cq_db = (u32 *)(nvme->regs + 0x1000 + (1 * nvme->dstrd_bytes));
+
+	/*
+	 * If controller is already running, avoid disturbing it when it is
+	 * already configured for our private scratch queues and appears idle.
+	 * Otherwise, reinitialize to private queues to avoid interacting with
+	 * OS-owned admin queues.
+	 */
+	cc = read32(nvme->regs + 0x14);
+	csts = read32(nvme->regs + 0x1c);
+
+	if ((cc & NVME_CC_EN) && (csts & 0x1)) {
+		const u64 asq = read64(nvme->regs + 0x28);
+		const u64 acq = read64(nvme->regs + 0x30);
+		const u32 aqa = read32(nvme->regs + 0x24);
+		const u32 expected_aqa = ((NVME_QUEUE_SIZE - 1) << 16) | (NVME_QUEUE_SIZE - 1);
+		const u32 sq_tail = read32(nvme->sq_db) & 0xffff;
+		const u32 cq_head = read32(nvme->cq_db) & 0xffff;
+
+		if (asq == (u64)(uintptr_t)nvme->sq && acq == (u64)(uintptr_t)nvme->cq &&
+		    aqa == expected_aqa && sq_tail == 0 && cq_head == 0) {
+			nvme->sq_tail = 0;
+			nvme->cq_head = 0;
+			nvme->cq_phase = (read32(&nvme->cq[0].dw[3]) >> 16) & 0x1;
+			return 0;
+		}
+
+		printk(BIOS_DEBUG, "OPAL NVMe: controller running, reinitializing\n");
+	}
+
+	/* Disable controller and wait for RDY=0. */
+	write32(nvme->regs + 0x14, 0);
+	if (nvme_wait_ready(nvme->regs, false)) {
+		printk(BIOS_ERR, "OPAL NVMe: failed to disable controller\n");
+		return -1;
+	}
+
+	/* Now that the controller is disabled, it is safe to clear our queues. */
+	memset(nvme->sq, 0, NVME_PAGE_SIZE);
+	memset(nvme->cq, 0, NVME_PAGE_SIZE);
+
+	/* Admin queue attributes: (CQ size-1)<<16 | (SQ size-1). */
+	write32(nvme->regs + 0x24, ((NVME_QUEUE_SIZE - 1) << 16) | (NVME_QUEUE_SIZE - 1));
+	write64(nvme->regs + 0x28, (u64)(uintptr_t)nvme->sq);
+	write64(nvme->regs + 0x30, (u64)(uintptr_t)nvme->cq);
+
+	/* Enable controller. */
+	write32(nvme->regs + 0x14, NVME_CC_EN | NVME_CC_CSS_NVM | NVME_CC_MPS_4K |
+				 NVME_CC_AMS_RR | NVME_CC_SHN_NONE |
+				 NVME_CC_IOSQES_64B | NVME_CC_IOCQES_16B);
+	if (nvme_wait_ready(nvme->regs, true)) {
+		printk(BIOS_ERR, "OPAL NVMe: controller not ready\n");
+		return -1;
+	}
+	nvme->sq_tail = 0;
+	nvme->cq_head = 0;
+	nvme->cq_phase = 0;
+
+	return 0;
+}
+
+void opal_nvme_deinit(struct opal_nvme *nvme)
+{
+	/* Keep controller state as-is; OS will reinitialize if needed. */
+	(void)nvme;
+}
+
+static int nvme_security_cmd(struct opal_nvme *nvme, u8 opcode, u8 protocol, u16 sp_specific,
+			     const void *buf, size_t buf_size)
+{
+	struct nvme_sq_entry cmd = { 0 };
+	const u64 prp1 = (u64)(uintptr_t)buf;
+
+	cmd.dw[0] = opcode; /* CID is left as 0 */
+	cmd.dw[1] = 0;      /* NSID = 0 (controller) */
+	cmd.dw[6] = (u32)prp1;
+	cmd.dw[7] = (u32)(prp1 >> 32);
+	/*
+	 * NVMe command dwords are little-endian on x86. The Security Protocol
+	 * Specific field is a numeric value in the command; do not byte-swap it.
+	 */
+	cmd.dw[10] = ((u32)protocol << 24) | ((u32)sp_specific << 8);
+	cmd.dw[11] = (u32)buf_size;
+
+	return nvme_admin_cmd(nvme, &cmd);
+}
+
+int opal_nvme_security_send(struct opal_nvme *nvme, u8 protocol, u16 sp_specific,
+			    const void *buf, size_t buf_size)
+{
+	return nvme_security_cmd(nvme, NVME_ADMIN_SECURITY_SEND_CMD, protocol, sp_specific,
+				 buf, buf_size);
+}
+
+int opal_nvme_security_recv(struct opal_nvme *nvme, u8 protocol, u16 sp_specific,
+			    void *buf, size_t buf_size, size_t *xfer_out)
+{
+	int ret;
+
+	if (xfer_out)
+		*xfer_out = 0;
+
+	ret = nvme_security_cmd(nvme, NVME_ADMIN_SECURITY_RECV_CMD, protocol, sp_specific,
+				buf, buf_size);
+	if (ret)
+		return ret;
+
+	if (xfer_out)
+		*xfer_out = buf_size;
+
+	return 0;
+}
diff --git a/src/security/tcg/opal_s3/opal_nvme.h b/src/security/tcg/opal_s3/opal_nvme.h
new file mode 100644
index 0000000000..2e064c7094
--- /dev/null
+++ b/src/security/tcg/opal_s3/opal_nvme.h
@@ -0,0 +1,41 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef SECURITY_TCG_OPAL_S3_OPAL_NVME_H
+#define SECURITY_TCG_OPAL_S3_OPAL_NVME_H
+
+#include <device/pci_type.h>
+#include <types.h>
+
+struct nvme_sq_entry;
+struct nvme_cq_entry;
+
+struct opal_nvme {
+	pci_devfn_t dev;
+	u8 *regs;
+	u64 cap;
+	u32 dstrd_bytes;
+
+	struct nvme_sq_entry *sq;
+	struct nvme_cq_entry *cq;
+	u32 *sq_db;
+	u32 *cq_db;
+
+	u16 sq_tail;
+	u16 cq_head;
+	u8 cq_phase;
+};
+
+/*
+ * Initialize a minimal NVMe admin queue in the provided scratch buffer.
+ *
+ * The scratch memory must not be in SMRAM. It must be preserved across S3.
+ */
+int opal_nvme_init(struct opal_nvme *nvme, pci_devfn_t dev, void *scratch, size_t scratch_size);
+void opal_nvme_deinit(struct opal_nvme *nvme);
+
+int opal_nvme_security_send(struct opal_nvme *nvme, u8 protocol, u16 sp_specific,
+			    const void *buf, size_t buf_size);
+int opal_nvme_security_recv(struct opal_nvme *nvme, u8 protocol, u16 sp_specific,
+			    void *buf, size_t buf_size, size_t *xfer_out);
+
+#endif
diff --git a/src/security/tcg/opal_s3/opal_secure.h b/src/security/tcg/opal_s3/opal_secure.h
new file mode 100644
index 0000000000..888a30fbc1
--- /dev/null
+++ b/src/security/tcg/opal_s3/opal_secure.h
@@ -0,0 +1,23 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef SECURITY_TCG_OPAL_S3_OPAL_SECURE_H
+#define SECURITY_TCG_OPAL_S3_OPAL_SECURE_H
+
+#include <stddef.h>
+#include <types.h>
+
+static inline void opal_explicit_bzero(void *ptr, size_t len)
+{
+	volatile u8 *p = (volatile u8 *)ptr;
+
+	if (!ptr || !len)
+		return;
+
+	while (len--)
+		*p++ = 0;
+
+	/* Prevent the compiler from optimizing the stores away. */
+	__asm__ __volatile__("" : : "r"(ptr) : "memory");
+}
+
+#endif

From 4943cfe4d0d1509a329c8227f0c9988495be4df3 Mon Sep 17 00:00:00 2001
From: Sowmya Aralguppe <sowmya.aralguppe@intel.com>
Date: Fri, 27 Feb 2026 11:24:15 +0530
Subject: [PATCH 3727/3886] soc/intel/pantherlake: Remove unsupported WCL CPU
 ID mappings
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Remove WCL_ID_2 through WCL_ID_5 entries from the power mapping table
supports a single SKU configuration.

Ref=:830097_WCL_PDG_SchChk_Rev1p5
BUG=b:None
TEST=Build ocelot and verify that the system boots

Change-Id: I95a8069c9b637c35936e6c0e5de257f7acbd8463
Signed-off-by: Sowmya Aralguppe <sowmya.aralguppe@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91448
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/soc/intel/pantherlake/chip.h | 4 ----
 1 file changed, 4 deletions(-)

diff --git a/src/soc/intel/pantherlake/chip.h b/src/soc/intel/pantherlake/chip.h
index 0db0b14036..f3058faf33 100644
--- a/src/soc/intel/pantherlake/chip.h
+++ b/src/soc/intel/pantherlake/chip.h
@@ -115,10 +115,6 @@ static const struct soc_intel_pantherlake_power_map {
 	{ PCI_DID_INTEL_PTL_H_ID_7, PTL_CORE_4, TDP_25W, PTL_SKU_7, PTL_TDC_4 },
 	{ PCI_DID_INTEL_PTL_H_ID_8, PTL_CORE_3, TDP_25W, PTL_SKU_2, PTL_TDC_3 },
 	{ PCI_DID_INTEL_WCL_ID_1, WCL_CORE, TDP_15W, WCL_SKU_1, WCL_TDC_1 },
-	{ PCI_DID_INTEL_WCL_ID_2, WCL_CORE, TDP_15W, WCL_SKU_1, WCL_TDC_1 },
-	{ PCI_DID_INTEL_WCL_ID_3, WCL_CORE, TDP_15W, WCL_SKU_1, WCL_TDC_1 },
-	{ PCI_DID_INTEL_WCL_ID_4, WCL_CORE, TDP_15W, WCL_SKU_1, WCL_TDC_1 },
-	{ PCI_DID_INTEL_WCL_ID_5, WCL_CORE, TDP_15W, WCL_SKU_1, WCL_TDC_1 },
 };
 
 /* Types of display ports */

From a649c82f7ad611ac81dc87c7d9ce5f0428b5f973 Mon Sep 17 00:00:00 2001
From: Subrata Banik <subratabanik@google.com>
Date: Thu, 27 Mar 2025 22:50:10 +0530
Subject: [PATCH 3728/3886] security/vboot: Add option for enabling ADB via GBB
 flag

This patch introduces a new Kconfig option,
`CONFIG_GBB_FLAG_ENABLE_ADB`, to allow enabling ADB.

This option, when enabled, sets the corresponding GBB flag (0x80000000).
This flag can then be utilized by the operating system to enable the
ADB.

TEST=Able to connect the google/quenbih from host device using ADB cable.

Change-Id: I680c1f47045255a5ed49b0bb6c6fb94bc054c278
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91719
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/security/vboot/Kconfig     | 4 ++++
 src/security/vboot/Makefile.mk | 1 +
 2 files changed, 5 insertions(+)

diff --git a/src/security/vboot/Kconfig b/src/security/vboot/Kconfig
index ef7c24d879..d8f6779cb0 100644
--- a/src/security/vboot/Kconfig
+++ b/src/security/vboot/Kconfig
@@ -463,6 +463,10 @@ config GBB_FLAG_FORCE_CSE_SYNC
 	bool "Running tests; enforce CSE sync"
 	default n
 
+config GBB_FLAG_ENABLE_ADB
+	bool "Enable ADB"
+	default n
+
 endmenu # GBB
 
 menu "Vboot Keys"
diff --git a/src/security/vboot/Makefile.mk b/src/security/vboot/Makefile.mk
index eb75975d04..465205af42 100644
--- a/src/security/vboot/Makefile.mk
+++ b/src/security/vboot/Makefile.mk
@@ -267,6 +267,7 @@ GBB_FLAGS := $(call int-add, \
 	$(call bool-to-mask,$(CONFIG_GBB_FLAG_DISABLE_FWMP),0x8000) \
 	$(call bool-to-mask,$(CONFIG_GBB_FLAG_ENABLE_UDC),0x10000) \
 	$(call bool-to-mask,$(CONFIG_GBB_FLAG_FORCE_CSE_SYNC),0x20000) \
+	$(call bool-to-mask,$(CONFIG_GBB_FLAG_ENABLE_ADB),0x80000000) \
 	)
 
 ifneq ($(CONFIG_GBB_BMPFV_FILE),)

From 7bfad23a15170b59dfd415ac944e113d17a4a767 Mon Sep 17 00:00:00 2001
From: Subrata Banik <subratabanik@google.com>
Date: Tue, 17 Mar 2026 21:00:15 +0530
Subject: [PATCH 3729/3886] mb/google/bluey: Enable GBB_FLAG_ENABLE_ADB for
 development

Select GBB_FLAG_ENABLE_ADB in Kconfig for the Bluey board. This is
required to support ADB debugging during the current development
phase.

Note: This is intended as a temporary measure (FIXME) and should
likely be reverted before production.

Change-Id: I9c8c2a315fcf91e4b51d25ee4e00490db7e33486
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91720
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
---
 src/mainboard/google/bluey/Kconfig | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/src/mainboard/google/bluey/Kconfig b/src/mainboard/google/bluey/Kconfig
index ddb033d939..47c81e6e74 100644
--- a/src/mainboard/google/bluey/Kconfig
+++ b/src/mainboard/google/bluey/Kconfig
@@ -3,6 +3,8 @@
 config BOARD_GOOGLE_BLUEY_COMMON
 	def_bool n
 	select COMMON_CBFS_SPI_WRAPPER
+	# FIXME: keep ADB for development phase
+	select GBB_FLAG_ENABLE_ADB if VBOOT
 	select MAINBOARD_HAS_CHROMEOS
 	select SPI_FLASH
 	select SPI_FLASH_FORCE_4_BYTE_ADDR_MODE

From ac5722a66f6f616ee1598986a5447e31a9148268 Mon Sep 17 00:00:00 2001
From: Felix Singer <felix.singer@secunet.com>
Date: Tue, 17 Mar 2026 13:57:20 +0000
Subject: [PATCH 3730/3886] 3rdparty/fsp: Update to upstream master

Updating from commit id a5b3d0e056ad:
2025-12-22 09:38:25 +0800 - (Renaming directory back to "IoT" to fix the corrupted path)

to commit id 81399b3b6147:
2026-02-24 08:49:28 +0800 - (ECG BTL-S 12P PV (6311_62) FSP)

This brings in 13 new commits:
81399b3b6147 ECG BTL-S 12P PV (6311_62) FSP
53b5040674c2 Edge Platforms ARL -UH IPU 2026.2 (5385_51) FSP
635793898797 TWL IPU26.2 v6491_51
3aebe88923ec ASL IPU26.2 v6491_51
45e148caeda5 ADL-N IPU26.2 v6491_51
6749aee0aae0 ADL-N IPU26.2 6491_51
a230e1e778d1 FSP Integration Guide
77d47e8d6f64 FSP Integration Guide
23cf258760b0 Update README.md
d7ab4a17f30d Update README.md
57141c9f85f9 TWL MR2 IPU26.1 v6457_50
faea68792e93 ASL MR5 IPU26.1 v6457_50
309053b4ae5a Create AmstonLake folder

Change-Id: I52cb07feec06ee456b3aca40fbc049715da650cf
Signed-off-by: Felix Singer <felix.singer@secunet.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91715
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
---
 3rdparty/fsp | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/3rdparty/fsp b/3rdparty/fsp
index a5b3d0e056..81399b3b61 160000
--- a/3rdparty/fsp
+++ b/3rdparty/fsp
@@ -1 +1 @@
-Subproject commit a5b3d0e056ad713f0055334427bc424f91aa6602
+Subproject commit 81399b3b61479abc379c2d01362d4b6dc6f515c9

From 225fd5e448f458959aa786f974def137362c0def Mon Sep 17 00:00:00 2001
From: Felix Singer <felix.singer@secunet.com>
Date: Tue, 17 Mar 2026 13:55:39 +0000
Subject: [PATCH 3731/3886] 3rdparty/intel-microcode: Update to upstream main

Updating from commit id f910b0a225d6:
2025-11-10 16:26:35 -0600 - (microcode-20251111 Release)

to commit id 250941fb6706:
2026-02-27 10:50:11 -0600 - (microcode-20260227 Release)

This brings in 3 new commits:
250941fb6706 microcode-20260227 Release
439ddde999b0 microcode-20260210-rev1 Release
b24397c3611f microcode-20260210 Release

Change-Id: I9eb7a1e70f3c58e1964bd9ffe963f059c97a583e
Signed-off-by: Felix Singer <felix.singer@secunet.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91714
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 3rdparty/intel-microcode | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/3rdparty/intel-microcode b/3rdparty/intel-microcode
index f910b0a225..250941fb67 160000
--- a/3rdparty/intel-microcode
+++ b/3rdparty/intel-microcode
@@ -1 +1 @@
-Subproject commit f910b0a225d66a23a407710c61b0b63ee612b50f
+Subproject commit 250941fb670645d7d91f761cc63656ad3a1ec367

From db3e23d505bf9f62757f7ade5c2e2f90e2d04acc Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Sun, 14 Dec 2025 18:10:03 -0600
Subject: [PATCH 3732/3886] lib/fw_config: Add mainboard hook for selective
 probe override

Add fw_config_probe_mainboard_override() hook that allows mainboards
to selectively override specific fw_config probes. The hook returns
whether the function handed the probe or not. If set to true, the
hook's 'result' parameter is returned; otherwise, standard fw_config
logic is used automatically.

This enables mainboards to override probes based on runtime conditions
(e.g., CFR options) without reimplementing standard fw_config logic.
The change is backward compatible as the default hook doesn't handle
any probes.

TEST=tested with subsequent patch

Change-Id: I6b9207eb9097ef5296fb5c41d8d1acbfde68b445
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90741
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
---
 src/include/fw_config.h | 14 ++++++++++++++
 src/lib/fw_config.c     | 11 +++++++++++
 2 files changed, 25 insertions(+)

diff --git a/src/include/fw_config.h b/src/include/fw_config.h
index 1e1652efb6..266490bc7e 100644
--- a/src/include/fw_config.h
+++ b/src/include/fw_config.h
@@ -71,6 +71,20 @@ static inline bool fw_config_is_provisioned(void)
  */
 uint64_t fw_config_get_field(const struct fw_config_field *field);
 
+/**
+ * fw_config_probe_mainboard_override() - Mainboard hook to override specific probes
+ * @match: Structure containing field and option to probe
+ * @result: Output parameter - set to the probe result if this probe was handled
+ *
+ * Return: %true if this probe was handled, %false otherwise
+ *
+ * Mainboards can override this function to handle specific fw_config probes
+ * (e.g., based on CFR/CMOS options). If a probe is handled, return %true and
+ * set *result to the desired probe result. If not handled, return %false and
+ * the standard fw_config logic will be used.
+ */
+bool fw_config_probe_mainboard_override(const struct fw_config *match, bool *result);
+
 /**
  * fw_config_probe() - Check if field and option matches.
  * @match: Structure containing field and option to probe.
diff --git a/src/lib/fw_config.c b/src/lib/fw_config.c
index 74f3f8bc41..b2c1cd491d 100644
--- a/src/lib/fw_config.c
+++ b/src/lib/fw_config.c
@@ -72,8 +72,19 @@ uint64_t fw_config_get_field(const struct fw_config_field *field)
 	return value;
 }
 
+bool __weak fw_config_probe_mainboard_override(const struct fw_config *match, bool *result)
+{
+	return false;
+}
+
 bool fw_config_probe(const struct fw_config *match)
 {
+	bool result;
+
+	/* Give mainboard a chance to override this probe */
+	if (fw_config_probe_mainboard_override(match, &result))
+		return result;
+
 	/* If fw_config is not provisioned, then there is nothing to match. */
 	if (!fw_config_is_provisioned())
 		return false;

From e0bc32ce6195f8b7c44893ab69d739043e7275a7 Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Sun, 14 Dec 2025 18:13:21 -0600
Subject: [PATCH 3733/3886] mb/google/brya: Add CFR-based storage selection for
 taeko/taniks

Add support for selecting NVMe or eMMC storage via CFR option on
taeko and taniks variants. Override fw_config_probe() to check the
CFR "storage_device" option and enable/disable the appropriate PCIe
root port based on user selection.

This allows runtime configuration of storage devices while ensuring
only the selected device is initialized, since initializing both
causes neither to be detected.

TEST=build/boot taeko, verify both eMMC and NVMe M.2 storage modules
functional when correct type selected from setup menu.

Change-Id: Ic555f93763736adb5837534b8011aa9c123fea08
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90742
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
---
 src/mainboard/google/brya/cfr.c               | 29 ++++++++++++++
 .../google/brya/variants/taeko/Makefile.mk    |  1 +
 .../google/brya/variants/taeko/fw_config.c    | 38 +++++++++++++++++++
 .../google/brya/variants/taniks/Makefile.mk   |  1 +
 .../google/brya/variants/taniks/fw_config.c   | 37 ++++++++++++++++++
 5 files changed, 106 insertions(+)

diff --git a/src/mainboard/google/brya/cfr.c b/src/mainboard/google/brya/cfr.c
index 2128145042..31b3274933 100644
--- a/src/mainboard/google/brya/cfr.c
+++ b/src/mainboard/google/brya/cfr.c
@@ -6,6 +6,32 @@
 #include <intelblocks/cfr.h>
 #include <soc/cfr.h>
 
+#if CONFIG(BOARD_GOOGLE_TANIKS) || CONFIG(BOARD_GOOGLE_TAEKO)
+
+enum storage_device {
+	STORAGE_NVME = 0,
+	STORAGE_EMMC = 1,
+};
+
+static const struct sm_object storage_device_opt = SM_DECLARE_ENUM({
+	.opt_name	= "storage_device",
+	.ui_name	= "Storage Device",
+	.ui_helptext	= "Select which storage device to use (NVMe SSD or eMMC)",
+	.default_value	= STORAGE_NVME,
+	.values		= (const struct sm_enum_value[]) {
+				{ "NVMe SSD",		STORAGE_NVME	},
+				{ "eMMC",		STORAGE_EMMC	},
+				SM_ENUM_VALUE_END			},
+});
+static struct sm_obj_form devices = {
+	.ui_name = "Devices",
+	.obj_list = (const struct sm_object *[]) {
+		&storage_device_opt,
+		NULL
+	},
+};
+#endif
+
 static struct sm_obj_form system = {
 	.ui_name = "System",
 	.obj_list = (const struct sm_object *[]) {
@@ -37,6 +63,9 @@ static struct sm_obj_form ec = {
 
 static struct sm_obj_form *sm_root[] = {
 	&system,
+#if CONFIG(BOARD_GOOGLE_TANIKS) || CONFIG(BOARD_GOOGLE_TAEKO)
+	&devices,
+#endif
 	&ec,
 	NULL
 };
diff --git a/src/mainboard/google/brya/variants/taeko/Makefile.mk b/src/mainboard/google/brya/variants/taeko/Makefile.mk
index 47f0432aeb..f269b09163 100644
--- a/src/mainboard/google/brya/variants/taeko/Makefile.mk
+++ b/src/mainboard/google/brya/variants/taeko/Makefile.mk
@@ -8,6 +8,7 @@ romstage-y += memory.c
 
 ramstage-y += gpio.c
 
+romstage-$(CONFIG_FW_CONFIG) += fw_config.c
 ramstage-$(CONFIG_FW_CONFIG) += fw_config.c
 
 ramstage-$(CONFIG_FW_CONFIG) += variant.c
diff --git a/src/mainboard/google/brya/variants/taeko/fw_config.c b/src/mainboard/google/brya/variants/taeko/fw_config.c
index 5068f84581..fbf214db54 100644
--- a/src/mainboard/google/brya/variants/taeko/fw_config.c
+++ b/src/mainboard/google/brya/variants/taeko/fw_config.c
@@ -4,6 +4,44 @@
 #include <console/console.h>
 #include <fw_config.h>
 #include <gpio.h>
+#include <option.h>
+#include <string.h>
+#include <types.h>
+
+enum storage_device {
+	STORAGE_NVME = 0,
+	STORAGE_EMMC = 1,
+};
+
+/* Override fw_config_probe_mainboard_override to check CFR for storage selection */
+bool fw_config_probe_mainboard_override(const struct fw_config *match, bool *result)
+{
+	/* Check if this is a storage-related probe */
+	if (match->field_name) {
+		/* Read CFR option directly - default to NVMe if not available */
+		uint8_t storage_selection = get_uint_option("storage_device", STORAGE_NVME);
+		if (strcmp(match->field_name, "BOOT_NVME_MASK") == 0) {
+			/* NVMe is enabled if storage selection is NVMe */
+			*result = (storage_selection == STORAGE_NVME);
+			if (*result) {
+				printk(BIOS_INFO, "fw_config: NVMe enabled by CFR\n");
+			}
+			return true;
+		}
+		if (strcmp(match->field_name, "BOOT_EMMC_MASK") == 0) {
+			/* eMMC is enabled if storage selection is eMMC */
+			*result = (storage_selection == STORAGE_EMMC);
+			if (*result) {
+				printk(BIOS_INFO, "fw_config: eMMC enabled by CFR\n");
+			}
+			return true;
+		}
+	}
+
+	/* Not handled - use standard fw_config logic */
+	return false;
+}
+
 
 static const struct pad_config dmic_enable_pads[] = {
 	PAD_CFG_NF(GPP_S2, NONE, DEEP, NF2),	/* DMIC_CLK0_R */
diff --git a/src/mainboard/google/brya/variants/taniks/Makefile.mk b/src/mainboard/google/brya/variants/taniks/Makefile.mk
index 61a70ec0ef..a70ba96714 100644
--- a/src/mainboard/google/brya/variants/taniks/Makefile.mk
+++ b/src/mainboard/google/brya/variants/taniks/Makefile.mk
@@ -6,6 +6,7 @@ romstage-y += gpio.c
 romstage-y += memory.c
 
 ramstage-y += gpio.c
+romstage-$(CONFIG_FW_CONFIG) += fw_config.c
 ramstage-$(CONFIG_FW_CONFIG) += fw_config.c
 
 ramstage-$(CONFIG_FW_CONFIG) += variant.c
diff --git a/src/mainboard/google/brya/variants/taniks/fw_config.c b/src/mainboard/google/brya/variants/taniks/fw_config.c
index f79110391c..b29ea56d98 100644
--- a/src/mainboard/google/brya/variants/taniks/fw_config.c
+++ b/src/mainboard/google/brya/variants/taniks/fw_config.c
@@ -4,6 +4,43 @@
 #include <console/console.h>
 #include <fw_config.h>
 #include <gpio.h>
+#include <option.h>
+#include <string.h>
+#include <types.h>
+
+enum storage_device {
+	STORAGE_NVME = 0,
+	STORAGE_EMMC = 1,
+};
+
+/* Override fw_config_probe_mainboard_override to check CFR for storage selection */
+bool fw_config_probe_mainboard_override(const struct fw_config *match, bool *result)
+{
+	/* Check if this is a storage-related probe */
+	if (match->field_name) {
+		/* Read CFR option directly - default to NVMe if not available */
+		uint8_t storage_selection = get_uint_option("storage_device", STORAGE_NVME);
+		if (strcmp(match->field_name, "BOOT_NVME_MASK") == 0) {
+			/* NVMe is enabled if storage selection is NVMe */
+			*result = (storage_selection == STORAGE_NVME);
+			if (*result) {
+				printk(BIOS_INFO, "fw_config: NVMe enabled by CFR\n");
+			}
+			return true;
+		}
+		if (strcmp(match->field_name, "BOOT_EMMC_MASK") == 0) {
+			/* eMMC is enabled if storage selection is eMMC */
+			*result = (storage_selection == STORAGE_EMMC);
+			if (*result) {
+				printk(BIOS_INFO, "fw_config: eMMC enabled by CFR\n");
+			}
+			return true;
+		}
+	}
+
+	/* Not handled - use standard fw_config logic */
+	return false;
+}
 
 static const struct pad_config dmic_enable_pads[] = {
 	PAD_CFG_NF(GPP_S2, NONE, DEEP, NF2),	/* DMIC_CLK0_R */

From 49f53bbb387f04143c351b3207d3c29cd344d1d0 Mon Sep 17 00:00:00 2001
From: Angel Pons <th3fanbus@gmail.com>
Date: Mon, 23 Feb 2026 17:18:03 +0100
Subject: [PATCH 3734/3886] include/acpi/acpi_pld.h: Fix order of colour
 components

The colour components are in RGB order in the structure returned by the
ACPI `_PLD` method, so use the same order in the C struct as well. This
has no impact since nobody currently specifies port colours with this.

Change-Id: I11b486faaf73f5da37b973180f23e8b3f19f3f5e
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91389
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/include/acpi/acpi_pld.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/include/acpi/acpi_pld.h b/src/include/acpi/acpi_pld.h
index 98d7f9ebcf..b1c2444992 100644
--- a/src/include/acpi/acpi_pld.h
+++ b/src/include/acpi/acpi_pld.h
@@ -98,8 +98,8 @@ struct acpi_pld {
 	/* Color field can be explicitly ignored */
 	bool ignore_color;
 	uint8_t color_red;
-	uint8_t color_blue;
 	uint8_t color_green;
+	uint8_t color_blue;
 
 	/* Port characteristics */
 	bool visible;		/* Can be seen by the user */

From dc315c8f51fb4832a8992a8bbd48429bac6c87e1 Mon Sep 17 00:00:00 2001
From: Patrick Rudolph <patrick.rudolph@9elements.com>
Date: Thu, 26 Feb 2026 10:04:44 +0100
Subject: [PATCH 3735/3886] soc/amd/common/block/psp: Drop send_psp_command_smm

Drop send_psp_command_smm() and let the generic send_psp_command()
method handle SMM as special case. This allows to use the same
method in regular code and SMM.

Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Change-Id: I5dad79e80b97e9d4dfbcd0d84d49eb23ea3f83cc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91702
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
---
 src/soc/amd/common/block/psp/psp_def.h  |  3 +++
 src/soc/amd/common/block/psp/psp_gen1.c | 22 +++++++++++++++++-----
 src/soc/amd/common/block/psp/psp_gen2.c | 22 +++++++++++++++++-----
 src/soc/amd/common/block/psp/psp_smm.c  | 19 ++++---------------
 4 files changed, 41 insertions(+), 25 deletions(-)

diff --git a/src/soc/amd/common/block/psp/psp_def.h b/src/soc/amd/common/block/psp/psp_def.h
index 6120c92174..9d60c264bf 100644
--- a/src/soc/amd/common/block/psp/psp_def.h
+++ b/src/soc/amd/common/block/psp/psp_def.h
@@ -175,4 +175,7 @@ enum cb_err soc_read_c2p38(uint32_t *msg_38_value);
 
 void enable_psp_smi(void);
 
+void psp_set_smm_flag(void);
+void psp_clear_smm_flag(void);
+
 #endif /* __AMD_PSP_DEF_H__ */
diff --git a/src/soc/amd/common/block/psp/psp_gen1.c b/src/soc/amd/common/block/psp/psp_gen1.c
index b3815f9283..d57759fa2b 100644
--- a/src/soc/amd/common/block/psp/psp_gen1.c
+++ b/src/soc/amd/common/block/psp/psp_gen1.c
@@ -115,6 +115,7 @@ static int wait_command(struct pspv1_mbox *mbox)
 int send_psp_command(uint32_t command, void *buffer)
 {
 	struct pspv1_mbox *mbox = soc_get_mbox_address();
+	int ret = 0;
 	if (!mbox)
 		return -PSPSTS_NOBASE;
 
@@ -132,19 +133,30 @@ int send_psp_command(uint32_t command, void *buffer)
 	if (wait_command(mbox))
 		return -PSPSTS_CMD_TIMEOUT;
 
+	if (ENV_SMM)
+		psp_set_smm_flag();
+
 	/* set address of command-response buffer and write command register */
 	wr_mbox_cmd_resp(mbox, buffer);
 	wr_mbox_cmd(mbox, command);
 
 	/* PSP clears command register when complete */
-	if (wait_command(mbox))
-		return -PSPSTS_CMD_TIMEOUT;
+	if (wait_command(mbox)) {
+		ret = -PSPSTS_CMD_TIMEOUT;
+		goto out;
+	}
 
 	/* check delivery status */
-	if (rd_mbox_sts(mbox) & (PSPV1_STATUS_ERROR | PSPV1_STATUS_TERMINATED))
-		return -PSPSTS_SEND_ERROR;
+	if (rd_mbox_sts(mbox) & (PSPV1_STATUS_ERROR | PSPV1_STATUS_TERMINATED)) {
+		ret = -PSPSTS_SEND_ERROR;
+		goto out;
+	}
 
-	return 0;
+out:
+	if (ENV_SMM)
+		psp_clear_smm_flag();
+
+	return ret;
 }
 
 /*
diff --git a/src/soc/amd/common/block/psp/psp_gen2.c b/src/soc/amd/common/block/psp/psp_gen2.c
index 026d32f086..b3cb6ef8ed 100644
--- a/src/soc/amd/common/block/psp/psp_gen2.c
+++ b/src/soc/amd/common/block/psp/psp_gen2.c
@@ -152,6 +152,8 @@ static int wait_command(uintptr_t psp_mmio, bool wait_for_ready)
 int send_psp_command(uint32_t command, void *buffer)
 {
 	const uintptr_t psp_mmio = get_psp_mmio_base();
+	int ret = 0;
+
 	if (!psp_mmio)
 		return -PSPSTS_NOBASE;
 
@@ -161,20 +163,30 @@ int send_psp_command(uint32_t command, void *buffer)
 	if (wait_command(psp_mmio, true))
 		return -PSPSTS_CMD_TIMEOUT;
 
+	if (ENV_SMM)
+		psp_set_smm_flag();
+
 	/* set address of command-response buffer and write command register */
 	wr_mbox_buffer_ptr(psp_mmio, buffer);
 	wr_mbox_cmd(psp_mmio, command);
 
 	/* PSP clears command register when complete.  All commands except
 	 * SxInfo set the Ready bit. */
-	if (wait_command(psp_mmio, command != MBOX_BIOS_CMD_SX_INFO))
-		return -PSPSTS_CMD_TIMEOUT;
+	if (wait_command(psp_mmio, command != MBOX_BIOS_CMD_SX_INFO)) {
+		ret = -PSPSTS_CMD_TIMEOUT;
+		goto out;
+	}
 
 	/* check delivery status */
-	if (rd_mbox_sts(psp_mmio))
-		return -PSPSTS_SEND_ERROR;
+	if (rd_mbox_sts(psp_mmio)) {
+		ret = -PSPSTS_SEND_ERROR;
+		goto out;
+	}
 
-	return 0;
+out:
+	if (ENV_SMM)
+		psp_clear_smm_flag();
+	return ret;
 }
 
 enum cb_err psp_get_psp_capabilities(uint32_t *capabilities)
diff --git a/src/soc/amd/common/block/psp/psp_smm.c b/src/soc/amd/common/block/psp/psp_smm.c
index 7fade174d7..ef7a018827 100644
--- a/src/soc/amd/common/block/psp/psp_smm.c
+++ b/src/soc/amd/common/block/psp/psp_smm.c
@@ -36,27 +36,16 @@ struct {
  */
 static uint32_t smm_flag;
 
-static void set_smm_flag(void)
+void psp_set_smm_flag(void)
 {
 	smm_flag = 1;
 }
 
-static void clear_smm_flag(void)
+void psp_clear_smm_flag(void)
 {
 	smm_flag = 0;
 }
 
-static int send_psp_command_smm(uint32_t command, void *buffer)
-{
-	int cmd_status;
-
-	set_smm_flag();
-	cmd_status = send_psp_command(command, buffer);
-	clear_smm_flag();
-
-	return cmd_status;
-}
-
 /*
  * The MBOX_BIOS_CMD_SMM_INFO PSP mailbox command doesn't necessarily need be sent from SMM,
  * but doing so allows the linker to sort out the addresses of c2p_buffer, p2c_buffer and
@@ -101,7 +90,7 @@ int psp_notify_smm(void)
 
 	printk(BIOS_DEBUG, "PSP: Notify SMM info... ");
 
-	cmd_status = send_psp_command_smm(MBOX_BIOS_CMD_SMM_INFO, &buffer);
+	cmd_status = send_psp_command(MBOX_BIOS_CMD_SMM_INFO, &buffer);
 
 	/* buffer's status shouldn't change but report it if it does */
 	psp_print_cmd_status(cmd_status, &buffer.header);
@@ -129,7 +118,7 @@ void psp_notify_sx_info(uint8_t sleep_type)
 
 	buffer->sleep_type = sleep_type;
 
-	cmd_status = send_psp_command_smm(MBOX_BIOS_CMD_SX_INFO, buffer);
+	cmd_status = send_psp_command(MBOX_BIOS_CMD_SX_INFO, buffer);
 
 	/* buffer's status shouldn't change but report it if it does */
 	psp_print_cmd_status(cmd_status, &buffer->header);

From 1555a1a235a8c51d40ce88eeb88750bb89f24c0c Mon Sep 17 00:00:00 2001
From: Felix Held <felix-coreboot@felixheld.de>
Date: Tue, 10 Mar 2026 16:26:18 +0100
Subject: [PATCH 3736/3886] util/amdfwtool: rename Glinda SoC to Strix

Glinda is an alias for Strix. This only changes the SoC name in
amdfwtool; SoC folder will be renamed later once all remaining patches
have been upstreamed, since renaming the SoC folder right now, would
just make the upstreaming more difficult.

Change-Id: I10cb9c4a97dd2689fe02329262772b05d24a5896
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91716
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
---
 src/soc/amd/glinda/fw.cfg   |  2 +-
 util/amdfwtool/amdfwtool.c  | 10 +++++-----
 util/amdfwtool/amdfwtool.h  |  2 +-
 util/amdfwtool/data_parse.c |  8 ++++----
 util/amdfwtool/signed_psp.c |  2 +-
 5 files changed, 12 insertions(+), 12 deletions(-)

diff --git a/src/soc/amd/glinda/fw.cfg b/src/soc/amd/glinda/fw.cfg
index a689a7f0e0..88f79db453 100644
--- a/src/soc/amd/glinda/fw.cfg
+++ b/src/soc/amd/glinda/fw.cfg
@@ -1,7 +1,7 @@
 # PSP fw config file
 
 FIRMWARE_LOCATION          3rdparty/amd_blobs/glinda/psp
-SOC_NAME                   Glinda
+SOC_NAME                   Strix
 
 # type                     file
 AMD_PUBKEY_FILE            TypeId0x00_Root.tkn
diff --git a/util/amdfwtool/amdfwtool.c b/util/amdfwtool/amdfwtool.c
index 6cd991110a..96acb3601b 100644
--- a/util/amdfwtool/amdfwtool.c
+++ b/util/amdfwtool/amdfwtool.c
@@ -666,7 +666,7 @@ static void fill_psp_directory_to_efs(embedded_firmware *amd_romsig, void *pspdi
 	case PLATFORM_CEZANNE:
 	case PLATFORM_MENDOCINO:
 	case PLATFORM_PHOENIX:
-	case PLATFORM_GLINDA:
+	case PLATFORM_STRIX:
 	case PLATFORM_CARRIZO:
 	case PLATFORM_STONEYRIDGE:
 	case PLATFORM_RAVEN:
@@ -706,7 +706,7 @@ static void fill_bios_directory_to_efs(embedded_firmware *amd_romsig, void *bios
 		break;
 	case PLATFORM_MENDOCINO:
 	case PLATFORM_PHOENIX:
-	case PLATFORM_GLINDA:
+	case PLATFORM_STRIX:
 	case PLATFORM_FAEGAN:
 	case PLATFORM_STRIXHALO:
 		break;
@@ -742,7 +742,7 @@ static uint32_t get_psp_id(enum platform soc_id)
 	case PLATFORM_STONEYRIDGE:
 		psp_id = 0x10220B00;
 		break;
-	case PLATFORM_GLINDA:
+	case PLATFORM_STRIX:
 		psp_id = 0xBC0E0200;
 		break;
 	case PLATFORM_PHOENIX:
@@ -1622,7 +1622,7 @@ static int set_efs_table(uint8_t soc_id, amd_cb_config *cb_config,
 	case PLATFORM_CEZANNE:
 	case PLATFORM_MENDOCINO:
 	case PLATFORM_PHOENIX:
-	case PLATFORM_GLINDA:
+	case PLATFORM_STRIX:
 	case PLATFORM_GENOA:
 	case PLATFORM_FAEGAN:
 	case PLATFORM_STRIXHALO:
@@ -1683,7 +1683,7 @@ static bool is_initial_alignment_required(enum platform soc_id)
 	switch (soc_id) {
 	case PLATFORM_MENDOCINO:
 	case PLATFORM_PHOENIX:
-	case PLATFORM_GLINDA:
+	case PLATFORM_STRIX:
 	case PLATFORM_FAEGAN:
 	case PLATFORM_STRIXHALO:
 		return false;
diff --git a/util/amdfwtool/amdfwtool.h b/util/amdfwtool/amdfwtool.h
index e0fae5e697..6e5d495823 100644
--- a/util/amdfwtool/amdfwtool.h
+++ b/util/amdfwtool/amdfwtool.h
@@ -32,7 +32,7 @@ enum platform {
 	PLATFORM_MENDOCINO,
 	PLATFORM_LUCIENNE,
 	PLATFORM_PHOENIX,
-	PLATFORM_GLINDA,
+	PLATFORM_STRIX,
 	PLATFORM_GENOA,
 	PLATFORM_FAEGAN,
 	PLATFORM_STRIXHALO,
diff --git a/util/amdfwtool/data_parse.c b/util/amdfwtool/data_parse.c
index 961b6a1c18..57341d7fe9 100644
--- a/util/amdfwtool/data_parse.c
+++ b/util/amdfwtool/data_parse.c
@@ -113,8 +113,8 @@ static enum platform identify_platform(char *soc_name)
 		return PLATFORM_LUCIENNE;
 	else if (!strcasecmp(soc_name, "Phoenix"))
 		return PLATFORM_PHOENIX;
-	else if (!strcasecmp(soc_name, "Glinda"))
-		return PLATFORM_GLINDA;
+	else if (!strcasecmp(soc_name, "Strix"))
+		return PLATFORM_STRIX;
 	else if (!strcasecmp(soc_name, "Genoa"))
 		return PLATFORM_GENOA;
 	else if (!strcasecmp(soc_name, "Faegan"))
@@ -793,7 +793,7 @@ static uint8_t process_one_line(char *oneline, regmatch_t *match, char *dir,
 static bool needs_ish(enum platform platform_type)
 {
 	if (platform_type == PLATFORM_MENDOCINO || platform_type == PLATFORM_PHOENIX ||
-		platform_type == PLATFORM_GLINDA || platform_type == PLATFORM_FAEGAN ||
+		platform_type == PLATFORM_STRIX || platform_type == PLATFORM_FAEGAN ||
 		platform_type == PLATFORM_STRIXHALO)
 		return true;
 	else
@@ -818,7 +818,7 @@ static bool is_second_gen(enum platform platform_type)
 	case PLATFORM_CEZANNE:
 	case PLATFORM_MENDOCINO:
 	case PLATFORM_PHOENIX:
-	case PLATFORM_GLINDA:
+	case PLATFORM_STRIX:
 	case PLATFORM_GENOA:
 	case PLATFORM_FAEGAN:
 	case PLATFORM_STRIXHALO:
diff --git a/util/amdfwtool/signed_psp.c b/util/amdfwtool/signed_psp.c
index 14d0a13b9b..9d6bad0b0b 100644
--- a/util/amdfwtool/signed_psp.c
+++ b/util/amdfwtool/signed_psp.c
@@ -39,7 +39,7 @@ static uint16_t get_psp_fw_type(enum platform soc_id, struct amd_fw_header *head
 	switch (soc_id) {
 	case PLATFORM_MENDOCINO:
 	case PLATFORM_PHOENIX:
-	case PLATFORM_GLINDA:
+	case PLATFORM_STRIX:
 	case PLATFORM_FAEGAN:
 	case PLATFORM_STRIXHALO:
 		/* Fallback to fw_type if fw_id is not populated, which serves the same

From 30cd6efc29dd729437513fb6092a932d19f3afc9 Mon Sep 17 00:00:00 2001
From: Felix Held <felix-coreboot@felixheld.de>
Date: Thu, 12 Mar 2026 14:46:33 +0100
Subject: [PATCH 3737/3886] util/amdfwtool: rename Faegan SoC to Krackan2e

Faegan is an alias for Krackan2e. This only changes the SoC name in
amdfwtool; the Faegan SoC variant name in the glinda folder will be
renamed later once all remaining patches have been upstreamed, to not
make the upstreaming more difficult than necessary.

Change-Id: I051e163170d4363594dcff4b505d01cabfb3a190
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91717
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
---
 util/amdfwtool/amdfwtool.c  | 10 +++++-----
 util/amdfwtool/amdfwtool.h  |  2 +-
 util/amdfwtool/data_parse.c |  8 ++++----
 util/amdfwtool/signed_psp.c |  2 +-
 4 files changed, 11 insertions(+), 11 deletions(-)

diff --git a/util/amdfwtool/amdfwtool.c b/util/amdfwtool/amdfwtool.c
index 96acb3601b..15d2926fd3 100644
--- a/util/amdfwtool/amdfwtool.c
+++ b/util/amdfwtool/amdfwtool.c
@@ -674,7 +674,7 @@ static void fill_psp_directory_to_efs(embedded_firmware *amd_romsig, void *pspdi
 	case PLATFORM_LUCIENNE:
 	case PLATFORM_RENOIR:
 	case PLATFORM_GENOA:
-	case PLATFORM_FAEGAN:
+	case PLATFORM_KRACKAN2E:
 	case PLATFORM_STRIXHALO:
 	default:
 		/* for combo, it is also combo_psp_directory */
@@ -707,7 +707,7 @@ static void fill_bios_directory_to_efs(embedded_firmware *amd_romsig, void *bios
 	case PLATFORM_MENDOCINO:
 	case PLATFORM_PHOENIX:
 	case PLATFORM_STRIX:
-	case PLATFORM_FAEGAN:
+	case PLATFORM_KRACKAN2E:
 	case PLATFORM_STRIXHALO:
 		break;
 	case PLATFORM_CARRIZO:
@@ -751,7 +751,7 @@ static uint32_t get_psp_id(enum platform soc_id)
 	case PLATFORM_GENOA:
 		psp_id = 0xBC0C0111;
 		break;
-	case PLATFORM_FAEGAN:
+	case PLATFORM_KRACKAN2E:
 		psp_id = 0xbc0e1000;
 		break;
 	case PLATFORM_STRIXHALO:
@@ -1624,7 +1624,7 @@ static int set_efs_table(uint8_t soc_id, amd_cb_config *cb_config,
 	case PLATFORM_PHOENIX:
 	case PLATFORM_STRIX:
 	case PLATFORM_GENOA:
-	case PLATFORM_FAEGAN:
+	case PLATFORM_KRACKAN2E:
 	case PLATFORM_STRIXHALO:
 		amd_romsig->spi_readmode_f17_mod_30_3f = cb_config->efs_spi_readmode;
 		amd_romsig->spi_fastspeed_f17_mod_30_3f = cb_config->efs_spi_speed;
@@ -1684,7 +1684,7 @@ static bool is_initial_alignment_required(enum platform soc_id)
 	case PLATFORM_MENDOCINO:
 	case PLATFORM_PHOENIX:
 	case PLATFORM_STRIX:
-	case PLATFORM_FAEGAN:
+	case PLATFORM_KRACKAN2E:
 	case PLATFORM_STRIXHALO:
 		return false;
 	default:
diff --git a/util/amdfwtool/amdfwtool.h b/util/amdfwtool/amdfwtool.h
index 6e5d495823..bd973638ed 100644
--- a/util/amdfwtool/amdfwtool.h
+++ b/util/amdfwtool/amdfwtool.h
@@ -34,7 +34,7 @@ enum platform {
 	PLATFORM_PHOENIX,
 	PLATFORM_STRIX,
 	PLATFORM_GENOA,
-	PLATFORM_FAEGAN,
+	PLATFORM_KRACKAN2E,
 	PLATFORM_STRIXHALO,
 };
 
diff --git a/util/amdfwtool/data_parse.c b/util/amdfwtool/data_parse.c
index 57341d7fe9..314d741b6b 100644
--- a/util/amdfwtool/data_parse.c
+++ b/util/amdfwtool/data_parse.c
@@ -117,8 +117,8 @@ static enum platform identify_platform(char *soc_name)
 		return PLATFORM_STRIX;
 	else if (!strcasecmp(soc_name, "Genoa"))
 		return PLATFORM_GENOA;
-	else if (!strcasecmp(soc_name, "Faegan"))
-		return PLATFORM_FAEGAN;
+	else if (!strcasecmp(soc_name, "Krackan2e"))
+		return PLATFORM_KRACKAN2E;
 	else if (!strcasecmp(soc_name, "Strixhalo"))
 		return PLATFORM_STRIXHALO;
 	else
@@ -793,7 +793,7 @@ static uint8_t process_one_line(char *oneline, regmatch_t *match, char *dir,
 static bool needs_ish(enum platform platform_type)
 {
 	if (platform_type == PLATFORM_MENDOCINO || platform_type == PLATFORM_PHOENIX ||
-		platform_type == PLATFORM_STRIX || platform_type == PLATFORM_FAEGAN ||
+		platform_type == PLATFORM_STRIX || platform_type == PLATFORM_KRACKAN2E ||
 		platform_type == PLATFORM_STRIXHALO)
 		return true;
 	else
@@ -820,7 +820,7 @@ static bool is_second_gen(enum platform platform_type)
 	case PLATFORM_PHOENIX:
 	case PLATFORM_STRIX:
 	case PLATFORM_GENOA:
-	case PLATFORM_FAEGAN:
+	case PLATFORM_KRACKAN2E:
 	case PLATFORM_STRIXHALO:
 		return true;
 	case PLATFORM_UNKNOWN:
diff --git a/util/amdfwtool/signed_psp.c b/util/amdfwtool/signed_psp.c
index 9d6bad0b0b..8dbb596a01 100644
--- a/util/amdfwtool/signed_psp.c
+++ b/util/amdfwtool/signed_psp.c
@@ -40,7 +40,7 @@ static uint16_t get_psp_fw_type(enum platform soc_id, struct amd_fw_header *head
 	case PLATFORM_MENDOCINO:
 	case PLATFORM_PHOENIX:
 	case PLATFORM_STRIX:
-	case PLATFORM_FAEGAN:
+	case PLATFORM_KRACKAN2E:
 	case PLATFORM_STRIXHALO:
 		/* Fallback to fw_type if fw_id is not populated, which serves the same
 		   purpose on older SoCs. */

From 8ff1a9a08c95e73ea006fb43a514f53c7d30812c Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Wed, 11 Mar 2026 16:06:19 -0500
Subject: [PATCH 3738/3886] vc/tcg/opal: add OPAL packet builder for S3 unlock

Add the OPAL packet builder and unlock logic used by the SMM resume
path. Uses the TCG storage encoder and NVMe Security Send/Receive
helpers to perform the Admin1/User1 Set Global Range unlock sequence.

TEST=tested with rest of patch train

Change-Id: I4cdb16e13c1aeb89648db49672b77598a8b42fac
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91658
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
---
 src/security/tcg/opal_s3/Makefile.mk  |   4 +
 src/vendorcode/tcg/opal/opal_unlock.c | 461 ++++++++++++++++++++++++++
 src/vendorcode/tcg/opal/opal_unlock.h |  13 +
 3 files changed, 478 insertions(+)
 create mode 100644 src/vendorcode/tcg/opal/opal_unlock.c
 create mode 100644 src/vendorcode/tcg/opal/opal_unlock.h

diff --git a/src/security/tcg/opal_s3/Makefile.mk b/src/security/tcg/opal_s3/Makefile.mk
index 9661b1a213..944927ff27 100644
--- a/src/security/tcg/opal_s3/Makefile.mk
+++ b/src/security/tcg/opal_s3/Makefile.mk
@@ -2,6 +2,10 @@
 
 CPPFLAGS_common-$(CONFIG_TCG_OPAL_S3_UNLOCK) += -I$(src)/vendorcode/intel/tcg_storage_core
 
+ramstage-$(CONFIG_TCG_OPAL_S3_UNLOCK) += opal_s3_resume.c
+
+smm-$(CONFIG_TCG_OPAL_S3_UNLOCK) += opal_s3_smm.c
 smm-$(CONFIG_TCG_OPAL_S3_UNLOCK) += opal_nvme.c
+smm-$(CONFIG_TCG_OPAL_S3_UNLOCK) += ../../../vendorcode/tcg/opal/opal_unlock.c
 smm-$(CONFIG_TCG_OPAL_S3_UNLOCK) += ../../../vendorcode/intel/tcg_storage_core/tcg_storage_core.c
 smm-$(CONFIG_TCG_OPAL_S3_UNLOCK) += ../../../vendorcode/intel/tcg_storage_core/tcg_storage_util.c
diff --git a/src/vendorcode/tcg/opal/opal_unlock.c b/src/vendorcode/tcg/opal/opal_unlock.c
new file mode 100644
index 0000000000..6cae3a8c85
--- /dev/null
+++ b/src/vendorcode/tcg/opal/opal_unlock.c
@@ -0,0 +1,461 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include "opal_unlock.h"
+
+#include <vendorcode/intel/tcg_storage_core/tcg_storage_core_lib.h>
+
+#include <commonlib/bsd/helpers.h>
+#include <console/console.h>
+#include <cpu/x86/smm.h>
+#include <delay.h>
+#include <security/tcg/opal_s3/opal_nvme.h>
+#include <security/tcg/opal_s3/opal_secure.h>
+#include <string.h>
+#include <types.h>
+
+#define TCG_OPAL_SECURITY_PROTOCOL_1 0x01
+
+/* Minimal Opal UIDs needed for S3 unlock. */
+#define OPAL_UID_LOCKING_SP \
+	TCG_TO_UID(0x00, 0x00, 0x02, 0x05, 0x00, 0x00, 0x00, 0x02)
+#define OPAL_LOCKING_SP_ADMIN1_AUTHORITY \
+	TCG_TO_UID(0x00, 0x00, 0x00, 0x09, 0x00, 0x01, 0x00, 0x01)
+#define OPAL_LOCKING_SP_USER1_AUTHORITY \
+	TCG_TO_UID(0x00, 0x00, 0x00, 0x09, 0x00, 0x03, 0x00, 0x01)
+#define OPAL_LOCKING_SP_LOCKING_GLOBALRANGE \
+	TCG_TO_UID(0x00, 0x00, 0x08, 0x02, 0x00, 0x00, 0x00, 0x01)
+
+#define TRUSTED_COMMAND_TIMEOUT_NS ((u64)5 * 1000 * 1000 * 1000ULL)
+
+#define OPAL_NVME_PAGE_SIZE         4096U
+#define OPAL_NVME_QUEUE_PAGES       2U
+#define OPAL_NVME_SCRATCH_PAGES     3U
+#define OPAL_NVME_QUEUE_BYTES       (OPAL_NVME_QUEUE_PAGES * OPAL_NVME_PAGE_SIZE)
+#define OPAL_NVME_SCRATCH_MIN_BYTES (OPAL_NVME_SCRATCH_PAGES * OPAL_NVME_PAGE_SIZE)
+
+typedef struct {
+	UINT32 HostSessionId;
+	UINT32 TperSessionId;
+	UINT16 ComIdExtension;
+	UINT16 OpalBaseComId;
+	struct opal_nvme *Nvme;
+} OPAL_SESSION;
+
+static TCG_RESULT opal_trusted_send(OPAL_SESSION *Session, UINT8 SecurityProtocol,
+				    UINT16 SpSpecific, UINTN TransferLength,
+				    VOID *Buffer, UINTN BufferSize)
+{
+	const UINTN TransferLength512 = (TransferLength + 511) & ~(UINTN)511;
+
+	if (TransferLength512 > BufferSize)
+		return TcgResultFailureBufferTooSmall;
+
+	ZeroMem((UINT8 *)Buffer + TransferLength, TransferLength512 - TransferLength);
+
+	if (opal_nvme_security_send(Session->Nvme, SecurityProtocol, SpSpecific,
+				    Buffer, TransferLength512))
+		return TcgResultFailure;
+
+	return TcgResultSuccess;
+}
+
+static TCG_RESULT opal_trusted_recv(OPAL_SESSION *Session, UINT8 SecurityProtocol,
+				    UINT16 SpSpecific, VOID *Buffer, UINTN BufferSize,
+				    UINT32 EstimateTimeCost)
+{
+	UINTN TransferLength512 = BufferSize & ~(UINTN)511;
+	UINT32 Tries;
+	UINT32 Length;
+	UINT32 OutstandingData;
+	TCG_COM_PACKET *ComPacket;
+
+	if (TransferLength512 < sizeof(TCG_COM_PACKET))
+		return TcgResultFailureBufferTooSmall;
+
+	Tries = (EstimateTimeCost > 10) ? (EstimateTimeCost * 500) : 5000;
+
+	while (Tries-- > 0) {
+		size_t TransferSize = 0;
+
+		ZeroMem(Buffer, BufferSize);
+		if (opal_nvme_security_recv(Session->Nvme, SecurityProtocol, SpSpecific,
+					    Buffer, TransferLength512, &TransferSize))
+			return TcgResultFailure;
+
+		if (SecurityProtocol != TCG_OPAL_SECURITY_PROTOCOL_1)
+			return TcgResultSuccess;
+
+		ComPacket = (TCG_COM_PACKET *)Buffer;
+		Length = SwapBytes32(ComPacket->LengthBE);
+		OutstandingData = SwapBytes32(ComPacket->OutstandingDataBE);
+
+		if ((Length != 0) && (OutstandingData == 0))
+			return TcgResultSuccess;
+
+		udelay(2000);
+	}
+
+	return TcgResultFailure;
+}
+
+static TCG_RESULT opal_perform_method(OPAL_SESSION *Session, UINT32 SendSize, VOID *Buffer,
+				      UINT32 BufferSize, TCG_PARSE_STRUCT *ParseStruct,
+				      UINT8 *MethodStatus, UINT32 EstimateTimeCost)
+{
+	NULL_CHECK(Session);
+	NULL_CHECK(MethodStatus);
+
+	ERROR_CHECK(opal_trusted_send(Session, TCG_OPAL_SECURITY_PROTOCOL_1,
+				      Session->OpalBaseComId, SendSize, Buffer, BufferSize));
+	ERROR_CHECK(opal_trusted_recv(Session, TCG_OPAL_SECURITY_PROTOCOL_1,
+				      Session->OpalBaseComId, Buffer, BufferSize,
+				      EstimateTimeCost));
+
+	ERROR_CHECK(TcgInitTcgParseStruct(ParseStruct, Buffer, BufferSize));
+	ERROR_CHECK(TcgCheckComIds(ParseStruct, Session->OpalBaseComId,
+				   Session->ComIdExtension));
+	ERROR_CHECK(TcgGetMethodStatus(ParseStruct, MethodStatus));
+
+	return TcgResultSuccess;
+}
+
+static TCG_RESULT opal_start_session(OPAL_SESSION *Session, TCG_UID SpId, BOOLEAN Write,
+				     UINT32 HostChallengeLength, const VOID *HostChallenge,
+				     TCG_UID HostSigningAuthority, VOID *Buffer,
+				     UINT32 BufferSize, UINT8 *MethodStatus)
+{
+	TCG_CREATE_STRUCT CreateStruct;
+	TCG_PARSE_STRUCT ParseStruct;
+	UINT32 Size;
+	UINT16 ComIdExtension = 0;
+	UINT32 HostSessionId = 1;
+	TCG_RESULT Ret = TcgResultSuccess;
+
+	if (!Session || !MethodStatus || !Buffer)
+		return TcgResultFailureNullPointer;
+
+	if (BufferSize < 512)
+		return TcgResultFailureBufferTooSmall;
+
+	*MethodStatus = 0;
+
+	Session->ComIdExtension = ComIdExtension;
+	Session->HostSessionId = HostSessionId;
+
+	Ret = TcgInitTcgCreateStruct(&CreateStruct, Buffer, BufferSize);
+	if (Ret != TcgResultSuccess)
+		goto out;
+
+	Ret = TcgCreateStartSession(&CreateStruct, &Size, Session->OpalBaseComId,
+				    ComIdExtension, HostSessionId, SpId, Write,
+				    HostChallengeLength, HostChallenge, HostSigningAuthority);
+	if (Ret != TcgResultSuccess)
+		goto out;
+
+	Ret = opal_perform_method(Session, Size, Buffer, BufferSize, &ParseStruct, MethodStatus,
+				  0);
+	if (Ret != TcgResultSuccess)
+		goto out;
+	if (*MethodStatus != TCG_METHOD_STATUS_CODE_SUCCESS)
+		goto out;
+
+	if (TcgParseSyncSession(&ParseStruct, Session->OpalBaseComId, ComIdExtension,
+				HostSessionId, &Session->TperSessionId) != TcgResultSuccess) {
+		Ret = TcgResultFailure;
+		goto out;
+	}
+
+out:
+	opal_explicit_bzero(Buffer, BufferSize);
+	return Ret;
+}
+
+static TCG_RESULT opal_end_session(OPAL_SESSION *Session, VOID *Buffer, UINT32 BufferSize)
+{
+	TCG_CREATE_STRUCT CreateStruct;
+	UINT32 Size;
+	TCG_PARSE_STRUCT ParseStruct;
+	TCG_RESULT Ret = TcgResultSuccess;
+
+	if (!Session || !Buffer)
+		return TcgResultFailureNullPointer;
+
+	if (BufferSize < 512)
+		return TcgResultFailureBufferTooSmall;
+
+	Ret = TcgInitTcgCreateStruct(&CreateStruct, Buffer, BufferSize);
+	if (Ret != TcgResultSuccess)
+		goto out;
+
+	Ret = TcgCreateEndSession(&CreateStruct, &Size, Session->OpalBaseComId,
+				  Session->ComIdExtension, Session->HostSessionId,
+				  Session->TperSessionId);
+	if (Ret != TcgResultSuccess)
+		goto out;
+
+	Ret = opal_trusted_send(Session, TCG_OPAL_SECURITY_PROTOCOL_1, Session->OpalBaseComId,
+				Size, Buffer, BufferSize);
+	if (Ret != TcgResultSuccess)
+		goto out;
+
+	Ret = opal_trusted_recv(Session, TCG_OPAL_SECURITY_PROTOCOL_1, Session->OpalBaseComId,
+				Buffer, BufferSize, 0);
+	if (Ret != TcgResultSuccess)
+		goto out;
+
+	Ret = TcgInitTcgParseStruct(&ParseStruct, Buffer, BufferSize);
+	if (Ret != TcgResultSuccess)
+		goto out;
+
+	Ret = TcgCheckComIds(&ParseStruct, Session->OpalBaseComId, Session->ComIdExtension);
+	if (Ret != TcgResultSuccess)
+		goto out;
+
+	Ret = TcgGetNextEndOfSession(&ParseStruct);
+	if (Ret != TcgResultSuccess)
+		goto out;
+
+out:
+	opal_explicit_bzero(Buffer, BufferSize);
+	return Ret;
+}
+
+static TCG_RESULT opal_update_global_locking_range(OPAL_SESSION *Session, BOOLEAN ReadLocked,
+						   BOOLEAN WriteLocked, VOID *Buffer,
+						   UINT32 BufferSize, UINT8 *MethodStatus)
+{
+	TCG_CREATE_STRUCT CreateStruct;
+	TCG_PARSE_STRUCT ParseStruct;
+	UINT32 Size;
+	TCG_RESULT Ret = TcgResultSuccess;
+
+	if (!Session || !MethodStatus || !Buffer)
+		return TcgResultFailureNullPointer;
+
+	if (BufferSize < 512)
+		return TcgResultFailureBufferTooSmall;
+
+	Ret = TcgInitTcgCreateStruct(&CreateStruct, Buffer, BufferSize);
+	if (Ret != TcgResultSuccess)
+		goto out;
+
+	Ret = TcgStartComPacket(&CreateStruct, Session->OpalBaseComId,
+				Session->ComIdExtension);
+	if (Ret != TcgResultSuccess)
+		goto out;
+	Ret = TcgStartPacket(&CreateStruct, Session->TperSessionId,
+			     Session->HostSessionId, 0, 0, 0);
+	if (Ret != TcgResultSuccess)
+		goto out;
+	Ret = TcgStartSubPacket(&CreateStruct, 0);
+	if (Ret != TcgResultSuccess)
+		goto out;
+	Ret = TcgStartMethodCall(&CreateStruct,
+				 OPAL_LOCKING_SP_LOCKING_GLOBALRANGE,
+				 TCG_UID_METHOD_SET);
+	if (Ret != TcgResultSuccess)
+		goto out;
+	Ret = TcgStartParameters(&CreateStruct);
+	if (Ret != TcgResultSuccess)
+		goto out;
+
+	Ret = TcgAddStartName(&CreateStruct);
+	if (Ret != TcgResultSuccess)
+		goto out;
+	Ret = TcgAddUINT8(&CreateStruct, 0x01);
+	if (Ret != TcgResultSuccess)
+		goto out;
+	Ret = TcgAddStartList(&CreateStruct);
+	if (Ret != TcgResultSuccess)
+		goto out;
+
+	Ret = TcgAddStartName(&CreateStruct);
+	if (Ret != TcgResultSuccess)
+		goto out;
+	Ret = TcgAddUINT8(&CreateStruct, 0x07);
+	if (Ret != TcgResultSuccess)
+		goto out;
+	Ret = TcgAddBOOLEAN(&CreateStruct, ReadLocked);
+	if (Ret != TcgResultSuccess)
+		goto out;
+	Ret = TcgAddEndName(&CreateStruct);
+	if (Ret != TcgResultSuccess)
+		goto out;
+
+	Ret = TcgAddStartName(&CreateStruct);
+	if (Ret != TcgResultSuccess)
+		goto out;
+	Ret = TcgAddUINT8(&CreateStruct, 0x08);
+	if (Ret != TcgResultSuccess)
+		goto out;
+	Ret = TcgAddBOOLEAN(&CreateStruct, WriteLocked);
+	if (Ret != TcgResultSuccess)
+		goto out;
+	Ret = TcgAddEndName(&CreateStruct);
+	if (Ret != TcgResultSuccess)
+		goto out;
+
+	Ret = TcgAddEndList(&CreateStruct);
+	if (Ret != TcgResultSuccess)
+		goto out;
+	Ret = TcgAddEndName(&CreateStruct);
+	if (Ret != TcgResultSuccess)
+		goto out;
+	Ret = TcgEndParameters(&CreateStruct);
+	if (Ret != TcgResultSuccess)
+		goto out;
+	Ret = TcgEndMethodCall(&CreateStruct);
+	if (Ret != TcgResultSuccess)
+		goto out;
+	Ret = TcgEndSubPacket(&CreateStruct);
+	if (Ret != TcgResultSuccess)
+		goto out;
+	Ret = TcgEndPacket(&CreateStruct);
+	if (Ret != TcgResultSuccess)
+		goto out;
+	Ret = TcgEndComPacket(&CreateStruct, &Size);
+	if (Ret != TcgResultSuccess)
+		goto out;
+
+	Ret = opal_perform_method(Session, Size, Buffer, BufferSize, &ParseStruct,
+				  MethodStatus, 0);
+	if (Ret != TcgResultSuccess)
+		goto out;
+	if (*MethodStatus != TCG_METHOD_STATUS_CODE_SUCCESS) {
+		Ret = TcgResultSuccess;
+		goto out;
+	}
+
+out:
+	opal_explicit_bzero(Buffer, BufferSize);
+	return Ret;
+}
+
+static TCG_RESULT opal_util_update_global_locking_range(OPAL_SESSION *Session,
+							const VOID *Password,
+							UINT32 PasswordLength,
+							BOOLEAN ReadLocked,
+							BOOLEAN WriteLocked,
+							VOID *Buffer,
+							UINT32 BufferSize)
+{
+	UINT8 MethodStatus = 0;
+	TCG_RESULT Ret;
+
+	NULL_CHECK(Session);
+	NULL_CHECK(Password);
+	NULL_CHECK(Buffer);
+
+	/* Try admin1 authority. */
+	Ret = opal_start_session(Session, OPAL_UID_LOCKING_SP, TRUE, PasswordLength, Password,
+				 OPAL_LOCKING_SP_ADMIN1_AUTHORITY, Buffer, BufferSize,
+				 &MethodStatus);
+	if ((Ret == TcgResultSuccess) && (MethodStatus == TCG_METHOD_STATUS_CODE_SUCCESS)) {
+		Ret = opal_update_global_locking_range(Session, ReadLocked, WriteLocked,
+						       Buffer, BufferSize, &MethodStatus);
+		opal_end_session(Session, Buffer, BufferSize);
+		if ((Ret == TcgResultSuccess) &&
+		    (MethodStatus == TCG_METHOD_STATUS_CODE_SUCCESS))
+			return TcgResultSuccess;
+	}
+
+	/* Try user1 authority. */
+	Ret = opal_start_session(Session, OPAL_UID_LOCKING_SP, TRUE, PasswordLength, Password,
+				 OPAL_LOCKING_SP_USER1_AUTHORITY, Buffer, BufferSize,
+				 &MethodStatus);
+	if (Ret != TcgResultSuccess)
+		goto done;
+	if (MethodStatus != TCG_METHOD_STATUS_CODE_SUCCESS)
+		goto done;
+
+	Ret = opal_update_global_locking_range(Session, ReadLocked, WriteLocked, Buffer,
+					       BufferSize, &MethodStatus);
+	opal_end_session(Session, Buffer, BufferSize);
+
+done:
+	if ((Ret == TcgResultSuccess) && (MethodStatus != TCG_METHOD_STATUS_CODE_SUCCESS)) {
+		if (MethodStatus == TCG_METHOD_STATUS_CODE_AUTHORITY_LOCKED_OUT)
+			Ret = TcgResultFailureInvalidType;
+		else
+			Ret = TcgResultFailure;
+	}
+
+	return Ret;
+}
+
+u32 opal_nvme_opal_unlock(pci_devfn_t dev, u16 base_comid, const u8 *password,
+			  u8 password_len, void *scratch, size_t scratch_size)
+{
+	struct opal_nvme nvme;
+	OPAL_SESSION Session;
+	TCG_RESULT Ret;
+	u8 *io_buf;
+	u32 rc = 0;
+	u8 *queue_base;
+
+	if (!password || !password_len) {
+		printk(BIOS_ERR, "OPAL: missing password\n");
+		return 4;
+	}
+
+	if (!scratch || scratch_size < OPAL_NVME_SCRATCH_MIN_BYTES) {
+		printk(BIOS_ERR, "OPAL: invalid scratch buffer\n");
+		return 2;
+	}
+
+	if (smm_points_to_smram(scratch, scratch_size)) {
+		printk(BIOS_ERR, "OPAL: scratch overlaps SMRAM\n");
+		return 2;
+	}
+
+	queue_base = (u8 *)ALIGN_UP((uintptr_t)scratch, OPAL_NVME_PAGE_SIZE);
+	if ((uintptr_t)queue_base + OPAL_NVME_SCRATCH_MIN_BYTES >
+	    (uintptr_t)scratch + scratch_size) {
+		printk(BIOS_ERR, "OPAL: scratch alignment overflow\n");
+		rc = 2;
+		goto out_early;
+	}
+
+	/* Use a 4KiB IO buffer after the queue pages. */
+	io_buf = queue_base + OPAL_NVME_QUEUE_BYTES;
+
+	if (opal_nvme_init(&nvme, dev, scratch, scratch_size)) {
+		/* Fail closed and ensure stale DMA-visible buffers are cleared. */
+		opal_explicit_bzero(queue_base, OPAL_NVME_SCRATCH_MIN_BYTES);
+		return 1;
+	}
+
+	memset(&Session, 0, sizeof(Session));
+	Session.Nvme = &nvme;
+	Session.OpalBaseComId = base_comid;
+	Session.ComIdExtension = 0;
+
+	/* Best-effort unlock. */
+	Ret = opal_util_update_global_locking_range(&Session, password, password_len, FALSE,
+						    FALSE, io_buf, OPAL_NVME_PAGE_SIZE);
+
+	opal_explicit_bzero(io_buf, OPAL_NVME_PAGE_SIZE);
+
+	/* Clear DMA-visible admin queues as well. */
+	opal_explicit_bzero(queue_base, OPAL_NVME_QUEUE_BYTES);
+	opal_nvme_deinit(&nvme);
+
+	rc = (Ret == TcgResultSuccess) ? 0 : 3;
+	return rc;
+
+out_early:
+	{
+		const uintptr_t end = (uintptr_t)scratch + scratch_size;
+		const uintptr_t start = (uintptr_t)queue_base;
+
+		if (end > start) {
+			size_t safe = end - start;
+
+			if (safe > OPAL_NVME_SCRATCH_MIN_BYTES)
+				safe = OPAL_NVME_SCRATCH_MIN_BYTES;
+			opal_explicit_bzero(queue_base, safe);
+		}
+	}
+
+	return rc;
+}
diff --git a/src/vendorcode/tcg/opal/opal_unlock.h b/src/vendorcode/tcg/opal/opal_unlock.h
new file mode 100644
index 0000000000..2e0209f464
--- /dev/null
+++ b/src/vendorcode/tcg/opal/opal_unlock.h
@@ -0,0 +1,13 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef VENDORCODE_TCG_OPAL_UNLOCK_H
+#define VENDORCODE_TCG_OPAL_UNLOCK_H
+
+#include <device/pci_type.h>
+#include <stddef.h>
+#include <types.h>
+
+u32 opal_nvme_opal_unlock(pci_devfn_t dev, u16 base_comid, const u8 *password,
+			  u8 password_len, void *scratch, size_t scratch_size);
+
+#endif

From 1063e564e7744ec6652e8f5dab6a06d4671881e0 Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Wed, 18 Mar 2026 14:55:48 -0500
Subject: [PATCH 3739/3886] Documentation/vboot: Update list of vboot-enabled
 devices

Produced by running: util/vboot_list/vboot_list.sh

Change-Id: I2c59e921e1160c4df739ad827161ee0af40fec39
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91729
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
---
 Documentation/security/vboot/list_vboot.md | 60 ++++++++++++----------
 1 file changed, 34 insertions(+), 26 deletions(-)

diff --git a/Documentation/security/vboot/list_vboot.md b/Documentation/security/vboot/list_vboot.md
index 2c66a1e87c..77a7954707 100644
--- a/Documentation/security/vboot/list_vboot.md
+++ b/Documentation/security/vboot/list_vboot.md
@@ -24,7 +24,7 @@
 
 ## Google
 - Asurada
-- Hayato
+- Hayato (ASUS Chromebook Flip CM3 (CM3200))
 - Spherion (Acer Chromebook 514 (CB514-2H, CB514-2HT))
 - Auron_Paine (Acer C740 Chromebook)
 - Auron_Yuna (Acer Chromebook 15 (C910/CB5-531))
@@ -42,6 +42,7 @@
 - BlueyH
 - QuenbiH
 - Quartz
+- Mica
 - Brox
 - Brox RTK EC
 - Brox EC ISH
@@ -49,6 +50,7 @@
 - Caboc
 - Greenbayupoc
 - Jubilant (Multiple devices - See help text)
+- Juchi
 - Lotso (Lenovo Chromebook Plus 2-in-1)
 - Agah
 - Anahera (HP Elite c640 14 inch G3 Chromebook)
@@ -78,12 +80,14 @@
 - Kaladin
 - Kinox (Lenovo ThinkCentre M60q Chromebox)
 - Kuldax (ASUS Chromebox 5/5a (CN67))
+- Kulnex
 - Joxer (HP Chromebook x360 14b)
 - Lisbon (Multiple devices - See help text)
 - Marasov (ASUS Chromebook Plus CX34 CX3402)
 - Mithrax (ASUS Chromebook CX34 Flip (CX3401))
 - Moli (Acer Chromebox CXI5)
 - Moxie (Acer Chromebox CXI6)
+- Moxoe
 - Nivviks
 - Nereid
 - Nokris
@@ -131,21 +135,21 @@
 - Pujjocento
 - Butterfly (HP Pavilion Chromebook 14)
 - Cherry
-- Dojo
-- Tomato
+- Dojo (HP Chromebook x360 (13b-ca0002sa))
+- Tomato (Acer Chromebook Spin 513 (CP513-2H))
 - Kingler
 - Kyogre
 - Ponyta
-- Squirtle
-- Steelix
-- Voltorb
-- Chinchou
+- Squirtle (Acer Chromebook Spin 311 (R724T))
+- Steelix/Magneton (see help text for details)
+- Voltorb (Acer Chromebook 311 (C723/C732T))
+- Chinchou/Chinochou360 (see help text for details)
 - Krabby
 - Magikarp
 - Skitty
-- Tentacruel
+- Tentacruel/Tentacool (see help text for details)
 - Veluza
-- Starmie
+- Starmie (ASUS Chromebook Enterprise CM30 (CM3001))
 - Wugtrio
 - Wyrdeer
 - Banon (Acer Chromebook 15 (CB3-532))
@@ -159,7 +163,7 @@
 - Terra (ASUS Chromebook C202SA/C300SA/C301SA)
 - Ultima (Lenovo Yoga 11e G3)
 - Wizpig (Multiple devices - See help text)
-- Drallion
+- Drallion/Drallion360 (Dell Latitude 7410 Chromebook Enterprise)
 - Eve (Google Pixelbook)
 - Fatcat
 - Fatcat4ES
@@ -182,7 +186,7 @@
 - Foster
 - Gale (Google WiFi)
 - Geralt
-- Ciri
+- Ciri (Lenovo Chromebook Duet Gen9 (11M889))
 - Asuka (Dell Chromebook 13 3380)
 - Caroline (Samsung Chromebook Pro)
 - Cave (Asus Chromebook Flip C302SA)
@@ -232,23 +236,23 @@
 - Kukui
 - Krane (Lenovo Chromebook Duet/Lenovo IdeaPad Duet Chromebook)
 - Kodama (Lenovo 10e Chromebook Tablet)
-- Kakadu
+- Kakadu (ASUS Chromebook Detachable CM3)
 - Flapjack
 - Katsu (ASUS Chromebook Detachable CZ1)
 - Jacuzzi
 - Juniper (Acer Chromebook Spin 311 (CP311-3H))
-- Kappa
+- Kappa (HP Chromebook 11a)
 - Damu (ASUS Chromebook Flip CM3 (CM3200))
 - Cerise
 - Stern
-- Willow
+- Willow (Acer Chromebook 311 (C722/C722T))
 - Esche (HP Chromebook 11MK G9 EE)
 - Burnet (HP Chromebook x360 11MK G3 EE)
-- Fennel
+- Fennel (Lenovo IdeaPad 3 Chromebook)
 - Cozmo (Acer Chromebook 314 (CB314-2H/CB314-2HT))
-- Makomo
+- Makomo (Lenovo 100e Chromebook (2nd Gen))
 - Munna
-- Pico
+- Pico (Acer Chromebook Spin 311)
 - Link (Google Chromebook Pixel (2013))
 - Mistral
 - Myst
@@ -289,8 +293,8 @@
 - Puff
 - Scout (Series One Desk 27)
 - Wyvern (Multiple devices - See help text)
-- Hylia
-- Navi
+- Hylia (Acer Chromebook Plus Spin 514 (CP514-5HN/CPE594-2N))
+- Navi (Lenovo Chromebook Plus (14M9610))
 - Rauru
 - Sapphire
 - Reef/Electro (Acer Chromebook Spin 11 R751T)
@@ -323,10 +327,13 @@
 - Baze
 - Dooku
 - Grogu
+- Jaina
+- Mace
 - Obiwan
 - Padme
 - Skywalker
 - Tarkin
+- Vader
 - Yoda
 - Falco (HP Chromebook 14)
 - Leon (Toshiba Chromebook)
@@ -338,15 +345,15 @@
 - Bubs
 - Coachz (HP Chromebook x2 11-da0)
 - Gelarshie
-- Homestar
-- Kingoftown
+- Homestar (Lenovo IdeaPad Duet 5 Chromebook)
+- Kingoftown (HP Fortis 11 G9 Q Chromebook)
 - Lazor (Acer Chromebook Spin 513, CP513-1H/1HL, R841T/LT)
 - Marzipan
 - Mrbland
-- Pazquel
-- Pompom
+- Pazquel (see help text for details)
+- Pompom (Dynabook Chromebook C1)
 - Quackingstick (Acer Chromebook Tab 510 / Enterprise Tab 510)
-- Wormdingler
+- Wormdingler (Lenovo IdeaPad Duet 3 Chromebook)
 - Trogdor
 - Veyron_Jaq (Haier Chromebook 11)
 - Veyron_Jerry (Hisense Chromebook 11)
@@ -443,13 +450,13 @@
 - ThinkPad T410
 - ThinkPad T420
 - ThinkPad T420s
-- ThinkPad T430
 - ThinkPad T430s
 - ThinkPad T431s
 - ThinkPad T520
 - ThinkPad W520
 - ThinkPad T530
 - ThinkPad W530
+- ThinkPad T430
 - ThinkPad X131e
 - ThinkPad X1 carbon gen 1
 - ThinkPad X200 / X200s / X200t
@@ -498,8 +505,10 @@
 - MC APL7
 
 ## Star Labs
+- Star Labs StarBook Horizon (N305)
 - Star Labs Byte Mk II (N200)
 - Star Labs Byte Mk III (N355)
+- Star Labs Lite Mk V (N200/N350)
 - Star Labs Lite Mk III (N5000)
 - Star Labs Lite Mk IV (N5030)
 - Star Labs LabTop Mk III (i7-8550u)
@@ -511,7 +520,6 @@
 - Star Labs StarBook Mk VII (165H)
 - Star Labs StarFighter Mk I (i3-1315U, i7-13700H and i9-13900H)
 - Star Labs StarFighter Mk II (125H and 285H)
-- Star Labs Lite Mk V (N200/N355)
 
 ## Supermicro
 - X11SSH-TF

From 8791c5292d5bd62f2402e081038ff40a9f66d072 Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Wed, 18 Mar 2026 16:06:16 -0500
Subject: [PATCH 3740/3886] Documentation/releases: Update release notes for
 26.03 release

These are the preliminary release notes. They'll need to be updated
with any changes done this week. We'll need another patch after the tag
to capture the final statistics. The notes will be changed from
"Upcoming release" after the tag is done.

Change-Id: Id24c2d43c53db7976c98f5936d9d8866a7392ad2
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91731
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
---
 .../releases/coreboot-26.03-relnotes.md       | 215 +++++++++++++++---
 1 file changed, 180 insertions(+), 35 deletions(-)

diff --git a/Documentation/releases/coreboot-26.03-relnotes.md b/Documentation/releases/coreboot-26.03-relnotes.md
index d709bb0f0f..6e302db11e 100644
--- a/Documentation/releases/coreboot-26.03-relnotes.md
+++ b/Documentation/releases/coreboot-26.03-relnotes.md
@@ -1,27 +1,118 @@
 Upcoming release - coreboot 26.03
 ========================================================================
 
-The 26.03 release is scheduled for the end of March, 2026
+The coreboot project is pleased to announce the release of coreboot 26.03.
+This release incorporates 856 commits from 95 contributors, reflecting
+continued focus on runtime configuration, security hardening, platform
+enablement, and memory/display data reliability across supported systems.
 
+Key improvements include:
+- Full support for Intel PantherLake SoCs (released at CES 2026 this January)
+- Refinements to CFR-based runtime configuration, including clearer
+  dependency wiring and more platform-exposed options
+- Increased SMMSTORE capacity and improved handling of mmapped SMMSTORE reads
+- TPM and signed secure blob plumbing updates across multiple platforms
+- SPD/memory data generation refresh, including JSON-based sources and
+  build-time `spd.hex` generation
+- MediaTek MT8196 display pipeline improvements (DSI dual-channel support and
+  panel power-off handling)
+- Storage integrity and security hardening improvements, including COREBOOT/
+  BOOTBLOCK locking and CBFS verification redundancy support
 
-Update this document with changes that should be in the release notes.
-
-* Please use Markdown.
-* See the past few release notes for the general format.
-* The chip and board additions and removals will be updated right
-  before the release, so those do not need to be added.
-* Note that all changes before the release are done are marked upcoming.
-  A final version of the notes are done after the release.
+As always, the coreboot project extends our appreciation to everyone who
+contributed to this release. From experienced developers implementing
+hardware-focused platform changes to community members validating
+functionality and reporting issues, the combined effort drives the
+continued evolution of open firmware and more reliable system initialization.
 
+The next coreboot release, 26.06, is scheduled for the end of June 2026.
 
 
 Significant or interesting changes
 ----------------------------------
 
-* Add changes that need a full description here
+### drivers/option/cfr: Refine and extend runtime configuration options
 
-* This section should have full descriptions and can or should have
-  a link to the referenced commits.
+The coreboot Forms Representation (CFR) runtime option framework was
+refactored to make platform dependencies more explicit and to keep option
+selection consistent across Intel SoCs and the boards that expose CFR-based
+controls.
+
+Intel SoC CFR integration was simplified to use boolean dependency wiring
+instead of enum-based gating, and the option plumbing was cleaned up across
+multiple boards and variants. In addition to general stability and
+integration work, several platforms gained new CFR-exposed runtime options
+for PCIe/power configuration, input device identification, Bluetooth runtime
+configuration, and a number of firmware configuration controls used by
+payloads that support CFR-driven setup.
+
+
+### drivers/smmstore: Improve memory-mapped reads for SMMSTORE
+
+The SMMSTORE driver was adjusted to use `lookup_store()` for
+memory-mapped reads, improving consistency of mmapped access patterns across
+architectures and reducing the likelihood of stale mappings during runtime
+reads.
+
+
+### TPM and signed secure blobs: board wiring and common plumbing improvements
+
+TPM enablement received cross-platform updates that cover ACPI integration,
+PSP emulation paths, and board-specific wiring.
+
+ACPI received additional enums for the TPM2 start method. On Qualcomm
+platforms, logic was added to handle secure boot blob paths in support of
+signed secure blob flows (gated by new Kconfig for signed blobs). The
+AMD/PSP software stack gained support for an fTPM driver implementation for
+PSP emulated CRB TPMs.
+
+Several board implementations were updated to match expected TPM resource
+layouts, including moving TPM into the devicetree on Lenovo platforms and
+adding TPM I2C plus EC SPI configuration on supported ChromeOS boards.
+
+
+### Memory SPD generation refresh: JSON-based sources and LP5/LPDDR5 expandability
+
+SPD-related work focused on reducing the amount of manual SPD data
+maintenance while improving coverage for new memory parts.
+
+Starlabs platform SPD sources were converted to JSON, and the build system
+now generates `spd.hex` from these JSON inputs at build time. The SPD
+tooling also gained improvements to `spd_gen` for Make-driven builds, along
+with new SPD decode helpers used for newer LPDDR5/LP5 families.
+
+Additional fixes in the SPD parsing pipeline address DDR5 channel mapping and
+corner-case arithmetic issues, improving the reliability of generated memory
+configuration.
+
+
+### MediaTek MT8196 display pipeline updates (DSI dual channel, panel power-off)
+
+The MediaTek MT8196 display stack was extended for broader DSI topologies and
+more consistent panel power management.
+
+DSI support was expanded to handle dual-channel configurations, with updated
+DSI PHY control method integration. Panel command handling was extended with
+explicit power-off support via a shared panel power-off API, and the
+platform gained common low-battery power-off handling for consistent runtime
+behavior.
+
+These updates refine initialization sequencing and improve the timing
+interaction between boot-state based initialization and display bring-up.
+
+
+### Firmware security hardening: lockdown controls and CBFS redundancy verification
+
+Security and integrity controls were expanded across multiple platforms.
+
+Intel SoCs moved to a common PMC lockdown driver, and several platforms
+received a shared runtime control path for BIOS SMM write protection.
+coreboot also gained an option to lock COREBOOT and BOOTBLOCK contents,
+strengthening the expected tamper resistance during normal operation.
+
+On the storage integrity side, CBFS verification was extended with Top Swap
+redundancy support, improving robustness when payload redundancy is used as
+part of the platform update or recovery strategy.
 
 
 
@@ -31,7 +122,25 @@ Additional coreboot changes
 The following are changes across a number of patches, or changes worth
 noting, but not needing a full description.
 
-* Changes that only need a line or two of description go here.
+* Intel SPI flash robustness improvements including spinlock protection for fast
+  operations and prevention of transfers across 4KiB boundaries.
+* Additional Intel SoC initialization refactoring, including common late-stage
+  finalize implementation used by multiple x86 families.
+* PCIe and FSP parameter updates across several Intel SoCs, including
+  platform-specific root port programming and improved PCIe power management
+  configuration.
+* Panther Lake/WCL power management work, including additional power-state
+  threshold configuration and PCIe clock-control support.
+* ChromeOS platform boot/power robustness improvements, including secure
+  low-power charging path handling and improved behavior when charger applet
+  enablement fails.
+* Display and camera pipeline fixes, including sensor SSDB validation and
+  board-specific MIPI camera configuration updates where required.
+* Starlabs platform storage/power enablement including helper-based NVMe
+  power sequencing and additional card reader enablement controls.
+* Qualcomm x1p42100 enablement updates including secure boot blob path logic,
+  DMA/stack region adjustments, and SPI bus speed tuning.
+* RISC-V SMP correctness fixes, including resolution of a race in SMP bring-up.
 
 
 
@@ -40,48 +149,85 @@ Changes to external resources
 
 ### Toolchain updates
 
-
+* Upgrade clang used by coreboot's cross toolchain build to 21.1.8.
+* Cross-compilation fixes for toolchain selection and target arguments to
+  keep the build deterministic across host environments.
 
 ### Git submodule pointers
 
+* `amd_blobs` submodule pointer advanced for updated AMD firmware blobs.
+* `libgfxinit` submodule bumped to a newer revision.
+* `vboot` submodule updated from the 2024 snapshot to the upstream 2026
+  baseline.
 
 ### External payloads
 
-
+* EDK2 build now generates an optional update capsule in support of UEFI update
+  flows. Payload configuration updates include a new MrChromebox branch baseline
+  and serial-output adjustments.
+* Depthcharge default configuration updated to use a 64-bit libpayload setup.
+* libpayload extended to pass panel power-off commands to payloads, and
+  liblz4 constant definitions were exported to keep payload-side compression
+  logic in sync.
 
 Platform Updates
 ----------------
 
 ### Added mainboards:
-* To be filled in immediately before the release by the release team
+* Intel Pantherlake CRB
+* Qotom qdnv01
+* Siemens MC EHL7
+* Siemens MC EHL8
+* Star Labs Starbook Horizon
 
 
 ### Removed Mainboards
-* To be filled in immediately before the release by the release team
 
 
 ### Updated SoCs
-* To be filled in immediately before the release by the release team
-
-
-
-Plans to move platform support to a branch
-------------------------------------------
-* To be filled in immediately before the release by the release team
-
+* AMD Turin POC: Added SPI TPM SoC-specific initialization and aligned Turin
+  sources for the PoC platform.
+* Intel Alderlake: Dropped invalid builtin root port handling in FSP params,
+  migrated to common global reset and common PMC lockdown plumbing, and
+  cleaned up CFR dependency wiring.
+* Intel Cannonlake: Migrated to common global reset and standardized common
+  GSPI/I2C/UART device mapping plus shared CFR boolean wiring.
+* Intel Elkhartlake: Switched to common global reset and common eSPI/LPC
+  initialization with shared GSPI/I2C/UART devfn mappings.
+* Intel Jasperlake: Added IGD naming via `soc_acpi_name`, moved PCIe ModPHY
+  parameter wiring into shared pcie_rp.h, standardized common global
+  reset/eSPI initialization, and added an initial `chipset.cb`.
+* Intel Meteorlake: Switched to Arrow Lake FSP usage (including Arrow Lake
+  microcode binaries) and migrated to shared finalize/global reset/PMC
+  lockdown implementations, plus ARL-H 45W power entry support.
+* Intel Pantherlake: Tuned WCL SKU behavior (icc_max and power-state
+  thresholds, TdcTimeWindow defaults, and CD clock frequency control) while
+  moving the platform to shared finalize/global reset/PMC lockdown flows.
+* Intel Tigerlake: Migrated to common global reset and common PCH client
+  SMI handling, standardized eSPI/LPC initialization plus shared
+  SoundWire/SPI/I2C/UART device mapping, and replaced CFR enums with
+  booleans.
+* MediaTek MT8196: Expanded DSI to support dual-channel configurations,
+  improved display pipeline bring-up (including framebuffer sizing and MIPI
+  register control), and added support for dual-MIPI logo rendering and
+  common panel power-off handling.
+* Qualcomm x1p42100: Added secure boot blob path logic for signed secure
+  blob support, increased SPI bus frequency (75MHz), and adjusted DMA/stack
+  region layout; also extended LPASS-side APIs used for platform bring-up.
 
 
 Statistics from the 25.12 to the 26.03 release
 --------------------------------------------
-* To be filled in immediately before the release by the release team
-
-
-
-Significant Known and Open Issues
----------------------------------
-
-Issues from the coreboot bugtracker: <https://ticket.coreboot.org/>
-* To be filled in immediately before the release by the release team
+* Total Commits: 856
+* Average Commits per day: 9.42
+* Total lines added: 107457
+* Average lines added per commit: 125.53
+* Number of patches adding more than 100 lines: 72
+* Average lines added per small commit: 41.11
+* Total lines removed: 22154
+* Average lines removed per commit: 25.88
+* Total difference between added and removed: 85303
+* Total authors: 95
 
 
 
@@ -94,4 +240,3 @@ coreboot Links and Contact Information
 * Documentation: <https://doc.coreboot.org>
 * Issue tracker: <https://ticket.coreboot.org/projects/coreboot>
 * Donations: <https://coreboot.org/donate.html>
-

From e5c99fe9e0fe75c176186dde5194dd2bc6504a66 Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Wed, 18 Mar 2026 15:03:39 -0500
Subject: [PATCH 3741/3886] Documentation: Add coreboot release 26.06 template

This adds the release notes template for the upcoming June 2026
release of coreboot.

Change-Id: I4a436ba1b649ce1091c6e496768ef7dc41776668
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91730
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
---
 .../releases/coreboot-26.06-relnotes.md       | 96 +++++++++++++++++++
 Documentation/releases/index.md               |  3 +-
 2 files changed, 98 insertions(+), 1 deletion(-)
 create mode 100644 Documentation/releases/coreboot-26.06-relnotes.md

diff --git a/Documentation/releases/coreboot-26.06-relnotes.md b/Documentation/releases/coreboot-26.06-relnotes.md
new file mode 100644
index 0000000000..4f89398649
--- /dev/null
+++ b/Documentation/releases/coreboot-26.06-relnotes.md
@@ -0,0 +1,96 @@
+Upcoming release - coreboot 26.06
+========================================================================
+
+The 26.06 release is scheduled for the end of June, 2026
+
+
+Update this document with changes that should be in the release notes.
+
+* Please use Markdown.
+* See the past few release notes for the general format.
+* The chip and board additions and removals will be updated right
+  before the release, so those do not need to be added.
+* Note that all changes before the release are done are marked upcoming.
+  A final version of the notes are done after the release.
+
+
+
+Significant or interesting changes
+----------------------------------
+
+* Add changes that need a full description here
+
+* This section should have full descriptions and can or should have
+  a link to the referenced commits.
+
+
+
+Additional coreboot changes
+---------------------------
+
+The following are changes across a number of patches, or changes worth
+noting, but not needing a full description.
+
+* Changes that only need a line or two of description go here.
+
+
+
+Changes to external resources
+-----------------------------
+
+### Toolchain updates
+
+
+
+### Git submodule pointers
+
+
+### External payloads
+
+
+
+Platform Updates
+----------------
+
+### Added mainboards:
+* To be filled in immediately before the release by the release team
+
+
+### Removed Mainboards
+* To be filled in immediately before the release by the release team
+
+
+### Updated SoCs
+* To be filled in immediately before the release by the release team
+
+
+
+Plans to move platform support to a branch
+------------------------------------------
+* To be filled in immediately before the release by the release team
+
+
+
+Statistics from the 26.03 to the 26.06 release
+--------------------------------------------
+* To be filled in immediately before the release by the release team
+
+
+
+Significant Known and Open Issues
+---------------------------------
+
+Issues from the coreboot bugtracker: <https://ticket.coreboot.org/>
+* To be filled in immediately before the release by the release team
+
+
+
+coreboot Links and Contact Information
+--------------------------------------
+
+* Main Web site: <https://www.coreboot.org>
+* Downloads: <https://coreboot.org/downloads.html>
+* Source control: <https://review.coreboot.org>
+* Documentation: <https://doc.coreboot.org>
+* Issue tracker: <https://ticket.coreboot.org/projects/coreboot>
+* Donations: <https://coreboot.org/donate.html>
diff --git a/Documentation/releases/index.md b/Documentation/releases/index.md
index b6d53a94a6..5f7d9347f1 100644
--- a/Documentation/releases/index.md
+++ b/Documentation/releases/index.md
@@ -6,7 +6,7 @@ Please add to the release notes as changes are added:
 ```{toctree}
 :maxdepth: 1
 
-26.03  - March 2026 <coreboot-26.03-relnotes.md>
+26.06  - June 2026 <coreboot-26.06-relnotes.md>
 ```
 
 The [checklist] contains instructions to ensure that a release covers all
@@ -22,6 +22,7 @@ important is taken care of.
 ```{toctree}
 :maxdepth: 1
 
+26.03  - March 2026 <coreboot-26.03-relnotes.md>
 25.12  - December 2025 <coreboot-25.12-relnotes.md>
 25.09  - September 2025 <coreboot-25.09-relnotes.md>
 25.06  - June 2025 <coreboot-25.06-relnotes.md>

From 9e7c787f6db38a2b0ca0631615d7683c0bb2cba6 Mon Sep 17 00:00:00 2001
From: Kirubakaran E <kirue@qualcomm.corp-partner.google.com>
Date: Wed, 18 Mar 2026 00:02:50 -0700
Subject: [PATCH 3742/3886] soc/qualcomm/x1p42100: Add 806 MHz CPU clock
 definition

Add the required definition for the 806 MHz CPU clock (L_VAL_806MHz).
Update pll_init_and_set by removing the static qualifier so it can be
invoked from the mainboard code.

Test: Built image.serial.bin and verified successful boot on X1P42100.

Change-Id: I8871f6cd64cb386c1042ce42feec4c623e9804e9
Signed-off-by: Kirubakaran E <kirue@qualcomm.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91722
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/soc/qualcomm/x1p42100/clock.c             | 2 +-
 src/soc/qualcomm/x1p42100/include/soc/clock.h | 2 ++
 2 files changed, 3 insertions(+), 1 deletion(-)

diff --git a/src/soc/qualcomm/x1p42100/clock.c b/src/soc/qualcomm/x1p42100/clock.c
index eba4987217..76e964831f 100644
--- a/src/soc/qualcomm/x1p42100/clock.c
+++ b/src/soc/qualcomm/x1p42100/clock.c
@@ -612,7 +612,7 @@ enum cb_err usb_clock_configure_mux(enum clk_pipe_usb clk_type, u32 src_type)
 	return CB_SUCCESS;
 }
 
-static enum cb_err pll_init_and_set(struct x1p42100_ncc0_clock *ncc0, u32 l_val)
+enum cb_err pll_init_and_set(struct x1p42100_ncc0_clock *ncc0, u32 l_val)
 {
 	int ret;
 	struct alpha_pll_reg_val_config ncc0_pll_cfg = {0};
diff --git a/src/soc/qualcomm/x1p42100/include/soc/clock.h b/src/soc/qualcomm/x1p42100/include/soc/clock.h
index c126baac62..474852940b 100644
--- a/src/soc/qualcomm/x1p42100/include/soc/clock.h
+++ b/src/soc/qualcomm/x1p42100/include/soc/clock.h
@@ -20,6 +20,7 @@
 
 /* CPU PLL*/
 #define L_VAL_1363P2MHz		0x47
+#define L_VAL_806MHz		0x2A
 
 /* DISP PLL */
 #define L_VAL_1725MHz		0x59
@@ -892,6 +893,7 @@ enum cb_err mdss_clock_enable(enum clk_mdss clk_type);
 enum cb_err disp_pll_init_and_set(struct x1p42100_disp_pll_clock *disp_pll,
 		u32 l_val, u32 alpha_val);
 enum cb_err lpass_init(void);
+enum cb_err pll_init_and_set(struct x1p42100_ncc0_clock *ncc0, u32 l_val);
 
 void clock_configure_dfsr_table_x1p42100(int qup, struct clock_freq_config *clk_cfg,
 		uint32_t num_perfs);

From 53529b1d93e492fe8ce7c0b7c84af9efae7f4ad9 Mon Sep 17 00:00:00 2001
From: Kapil Porwal <kapilporwal@google.com>
Date: Mon, 9 Mar 2026 18:01:37 +0530
Subject: [PATCH 3743/3886] soc/qualcomm/common: Add Qualcomm TSENS support

Introduce a generic driver for the Qualcomm Temperature Sensor (TSENS)
V2 hardware block. This driver provides the infrastructure to read
temperature data from hardware status registers and monitor them
against software-defined thresholds.

The driver sign-extends the 12-bit raw temperature values and scales
the output to millidegrees Celsius for accurate monitoring.

TEST=Verify all x1p42100 thermal zones are readable on Google/Quartz.

Change-Id: I826df3f86edc30ac57d84f672b487a8b9b51728a
Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91609
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/soc/qualcomm/common/Kconfig               |  7 ++
 .../qualcomm/common/include/soc/qcom_tsens.h  | 41 +++++++++++
 src/soc/qualcomm/common/tsens.c               | 72 +++++++++++++++++++
 3 files changed, 120 insertions(+)
 create mode 100644 src/soc/qualcomm/common/include/soc/qcom_tsens.h
 create mode 100644 src/soc/qualcomm/common/tsens.c

diff --git a/src/soc/qualcomm/common/Kconfig b/src/soc/qualcomm/common/Kconfig
index 98760cec63..373ba51c40 100644
--- a/src/soc/qualcomm/common/Kconfig
+++ b/src/soc/qualcomm/common/Kconfig
@@ -54,4 +54,11 @@ config SOC_QUALCOMM_QCLIB_SKIP_MMU_TOGGLE
 	  flushes and TLB invalidations associated with mmu_disable() and
 	  mmu_enable() calls.
 
+config SOC_QUALCOMM_DEBUG_TSENS
+	bool
+	default n
+	help
+	  When enabled, a call to monitor TSENS will dump the sensor data on
+	  the debug console.
+
 endif
diff --git a/src/soc/qualcomm/common/include/soc/qcom_tsens.h b/src/soc/qualcomm/common/include/soc/qcom_tsens.h
new file mode 100644
index 0000000000..6bb82a5e30
--- /dev/null
+++ b/src/soc/qualcomm/common/include/soc/qcom_tsens.h
@@ -0,0 +1,41 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef _SOC_QUALCOMM_TSENS_H_
+#define _SOC_QUALCOMM_TSENS_H_
+
+#include <stddef.h>
+#include <stdbool.h>
+#include <stdint.h>
+
+#define TM_SN_STATUS_OFF    0x00a0
+#define SN_STATUS_VALID     (1 << 21)
+#define SN_STATUS_TEMP_MASK 0xFFF
+
+struct tsens_controller {
+	const char *name;
+	uintptr_t tm_base;
+	uintptr_t srot_base;
+	uint32_t sensor_count;
+};
+
+enum sensor_type {
+	TYPE_TSENS
+};
+
+struct thermal_zone_map {
+	const char *label;
+	enum sensor_type type;
+	const void *ctrl;
+	int hw_id;
+	int threshold;
+};
+
+/*
+ * Iterates through all defined zones and checks thresholds.
+ */
+void qcom_tsens_monitor_all(bool *has_crossed_threshold);
+
+/* External Data (Defined in SoC file) */
+extern const struct thermal_zone_map qcom_thermal_zones[];
+
+#endif /* _SOC_QUALCOMM_TSENS_H_ */
diff --git a/src/soc/qualcomm/common/tsens.c b/src/soc/qualcomm/common/tsens.c
new file mode 100644
index 0000000000..12f5ecdc5b
--- /dev/null
+++ b/src/soc/qualcomm/common/tsens.c
@@ -0,0 +1,72 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <arch/mmio.h>
+#include <commonlib/bsd/stdlib.h>
+#include <device/mmio.h>
+#include <soc/addressmap.h>
+#include <soc/qcom_tsens.h>
+
+#if CONFIG(SOC_QUALCOMM_DEBUG_TSENS)
+#define thermal_printk(fmt, ...) printk(BIOS_INFO, fmt, ##__VA_ARGS__)
+#else
+#define thermal_printk(fmt, ...) do { (void)(fmt); } while (0)
+#endif
+
+static int read_tsens(const struct thermal_zone_map *zone, int *out)
+{
+	if (!zone)
+		return -1;
+
+	const struct tsens_controller *ctrl = (const struct tsens_controller *)zone->ctrl;
+	if (!ctrl || (zone->hw_id >= (int)ctrl->sensor_count))
+		return -1;
+
+	uintptr_t status_addr = ctrl->tm_base + TM_SN_STATUS_OFF + (zone->hw_id * 4);
+
+	uint32_t status = read32p(status_addr);
+	if (!(status & SN_STATUS_VALID))
+		return -2;
+
+	/* Sign extend 12-bit temperature and scale to milli C */
+	*out = ((int32_t)((status & SN_STATUS_TEMP_MASK) << 20) >> 20) * 100;
+	return 0;
+}
+
+void qcom_tsens_monitor_all(bool *has_crossed_threshold)
+{
+	if (!has_crossed_threshold)
+		return;
+
+	*has_crossed_threshold = false;
+
+	thermal_printk("\n------------------ Thermal Sensor State --------------------\n");
+	thermal_printk("%-15s | %-10s | %-8s | %-10s\n", "Zone", "Type", "Temp (C)", "Status");
+	thermal_printk("------------------------------------------------------------\n");
+
+	for (const struct thermal_zone_map *zone = qcom_thermal_zones; zone->label != NULL; zone++) {
+		int data = 0, status = -1;
+		const char *type_str = "UNK";
+		(void)type_str;
+
+		if (zone->type == TYPE_TSENS) {
+			type_str = "SoC";
+			status = read_tsens(zone, &data);
+		}
+
+		if (status == 0) {
+			thermal_printk("%-15s | %-10s | %3d.%1d    | ",
+			       zone->label, type_str, data / 1000, (data % 1000) / 100);
+
+			if (data >= zone->threshold) {
+				*has_crossed_threshold = true;
+				thermal_printk("EXCEEDED\n");
+				if (!CONFIG(SOC_QUALCOMM_DEBUG_TSENS))
+					return;
+			} else {
+				thermal_printk("OK\n");
+			}
+		} else {
+			thermal_printk("%-15s | %-10s | [ERR %d]  | -\n", zone->label, type_str, status);
+		}
+	}
+}

From 657bd42548ab299dd2e3885da63e30278ea5a2e5 Mon Sep 17 00:00:00 2001
From: Kapil Porwal <kapilporwal@google.com>
Date: Mon, 9 Mar 2026 18:03:00 +0530
Subject: [PATCH 3744/3886] soc/qualcomm/x1p42100: Define TSENS controllers and
 thermal zones

Provide the SoC-specific hardware definitions for the x1p42100 TSENS
subsystem. This includes the register base addresses for the four
TSENS controllers and the complete mapping of sensor IDs to thermal
zones (including AOSS, CPU, GPU, and NSP).

Each zone is assigned a specific thermal threshold to allow for
emergency shutdown triggers.

TEST=Verify all x1p42100 thermal zones are readable on Google/Quartz.

Change-Id: Iffdd0589a3c5318b9754101d7cea40462435de5b
Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91610
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/soc/qualcomm/x1p42100/Makefile.mk |  2 +
 src/soc/qualcomm/x1p42100/tsens_map.c | 80 +++++++++++++++++++++++++++
 2 files changed, 82 insertions(+)
 create mode 100644 src/soc/qualcomm/x1p42100/tsens_map.c

diff --git a/src/soc/qualcomm/x1p42100/Makefile.mk b/src/soc/qualcomm/x1p42100/Makefile.mk
index 68eff9a46b..77412e4cd0 100644
--- a/src/soc/qualcomm/x1p42100/Makefile.mk
+++ b/src/soc/qualcomm/x1p42100/Makefile.mk
@@ -57,6 +57,8 @@ ramstage-y += ../common/rpmh.c ../common/rpmh_bcm.c ../common/rpmh_regulator.c .
 ramstage-y += rpmh_rsc_init.c
 ramstage-y += display/disp.c
 ramstage-y += lpass.c
+ramstage-y += ../common/tsens.c
+ramstage-y += tsens_map.c
 
 ################################################################################
 
diff --git a/src/soc/qualcomm/x1p42100/tsens_map.c b/src/soc/qualcomm/x1p42100/tsens_map.c
new file mode 100644
index 0000000000..dcd8a18043
--- /dev/null
+++ b/src/soc/qualcomm/x1p42100/tsens_map.c
@@ -0,0 +1,80 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * SoC Specific TSENS Map
+ */
+
+#include <soc/qcom_tsens.h>
+
+/* Controller Configuration for SoC TSENS */
+static const struct tsens_controller tsens_blocks[] = {
+	/* Name,   TM base,    SROT base,  Sensor count */
+	{"tsens0", 0x0c271000, 0x0c222000, 13},
+	{"tsens1", 0x0c272000, 0x0c223000, 11},
+	{"tsens2", 0x0c273000, 0x0c224000, 11},
+	{"tsens3", 0x0c274000, 0x0c225000, 15}
+};
+
+/* Sensor Definition Mapping */
+const struct thermal_zone_map qcom_thermal_zones[] = {
+	/* Label,     Type,       Controller,    HW ID, Threshold (in milli degree C) */
+	/* SoC TSENS Controller 0 */
+	{"aoss-0",    TYPE_TSENS, &tsens_blocks[0], 0,  105000},
+	{"cpu-0-0-0", TYPE_TSENS, &tsens_blocks[0], 1,  108000},
+	{"cpu-0-0-1", TYPE_TSENS, &tsens_blocks[0], 2,  108000},
+	{"cpu-0-1-0", TYPE_TSENS, &tsens_blocks[0], 3,  108000},
+	{"cpu-0-1-1", TYPE_TSENS, &tsens_blocks[0], 4,  108000},
+	{"cpu-0-2-0", TYPE_TSENS, &tsens_blocks[0], 5,  108000},
+	{"cpu-0-2-1", TYPE_TSENS, &tsens_blocks[0], 6,  108000},
+	{"cpu-0-3-0", TYPE_TSENS, &tsens_blocks[0], 7,  108000},
+	{"cpu-0-3-1", TYPE_TSENS, &tsens_blocks[0], 8,  108000},
+	{"cpuss-0-0", TYPE_TSENS, &tsens_blocks[0], 9,  105000},
+	{"cpuss-0-1", TYPE_TSENS, &tsens_blocks[0], 10, 105000},
+	{"ddr-0",     TYPE_TSENS, &tsens_blocks[0], 11, 105000},
+	{"video",     TYPE_TSENS, &tsens_blocks[0], 12, 105000},
+
+	/* SoC TSENS Controller 1 */
+	{"aoss-1",    TYPE_TSENS, &tsens_blocks[1], 0,  105000},
+	{"cpu-1-0-0", TYPE_TSENS, &tsens_blocks[1], 1,  108000},
+	{"cpu-1-0-1", TYPE_TSENS, &tsens_blocks[1], 2,  108000},
+	{"cpu-1-1-0", TYPE_TSENS, &tsens_blocks[1], 3,  108000},
+	{"cpu-1-1-1", TYPE_TSENS, &tsens_blocks[1], 4,  108000},
+	{"cpu-1-2-0", TYPE_TSENS, &tsens_blocks[1], 5,  108000},
+	{"cpu-1-2-1", TYPE_TSENS, &tsens_blocks[1], 6,  108000},
+	{"cpu-1-3-0", TYPE_TSENS, &tsens_blocks[1], 7,  108000},
+	{"cpu-1-3-1", TYPE_TSENS, &tsens_blocks[1], 8,  108000},
+	{"cpuss-1-0", TYPE_TSENS, &tsens_blocks[1], 9,  105000},
+	{"cpuss-1-1", TYPE_TSENS, &tsens_blocks[1], 10, 105000},
+
+	/* SoC TSENS Controller 2 */
+	{"aoss-2",    TYPE_TSENS, &tsens_blocks[2], 0,  105000},
+	{"cpu-2-0-0", TYPE_TSENS, &tsens_blocks[2], 1,  108000},
+	{"cpu-2-0-1", TYPE_TSENS, &tsens_blocks[2], 2,  108000},
+	{"cpu-2-1-0", TYPE_TSENS, &tsens_blocks[2], 3,  108000},
+	{"cpu-2-1-1", TYPE_TSENS, &tsens_blocks[2], 4,  108000},
+	{"cpu-2-2-0", TYPE_TSENS, &tsens_blocks[2], 5,  108000},
+	{"cpu-2-2-1", TYPE_TSENS, &tsens_blocks[2], 6,  108000},
+	{"cpu-2-3-0", TYPE_TSENS, &tsens_blocks[2], 7,  108000},
+	{"cpu-2-3-1", TYPE_TSENS, &tsens_blocks[2], 8,  108000},
+	{"cpuss-2-0", TYPE_TSENS, &tsens_blocks[2], 9,  105000},
+	{"cpuss-2-1", TYPE_TSENS, &tsens_blocks[2], 10, 105000},
+
+	/* SoC TSENS Controller 3 */
+	{"aoss-3",    TYPE_TSENS, &tsens_blocks[3], 0,  105000},
+	{"nsp-0",     TYPE_TSENS, &tsens_blocks[3], 1,  105000},
+	{"nsp-1",     TYPE_TSENS, &tsens_blocks[3], 2,  105000},
+	{"nsp-2",     TYPE_TSENS, &tsens_blocks[3], 3,  105000},
+	{"nsp-3",     TYPE_TSENS, &tsens_blocks[3], 4,  105000},
+	{"gpuss-0",   TYPE_TSENS, &tsens_blocks[3], 5,  95000},
+	{"gpuss-1",   TYPE_TSENS, &tsens_blocks[3], 6,  95000},
+	{"gpuss-2",   TYPE_TSENS, &tsens_blocks[3], 7,  95000},
+	{"gpuss-3",   TYPE_TSENS, &tsens_blocks[3], 8,  95000},
+	{"gpuss-4",   TYPE_TSENS, &tsens_blocks[3], 9,  95000},
+	{"gpuss-5",   TYPE_TSENS, &tsens_blocks[3], 10, 95000},
+	{"gpuss-6",   TYPE_TSENS, &tsens_blocks[3], 11, 95000},
+	{"gpuss-7",   TYPE_TSENS, &tsens_blocks[3], 12, 95000},
+	{"camera-0",  TYPE_TSENS, &tsens_blocks[3], 13, 105000},
+	{"camera-1",  TYPE_TSENS, &tsens_blocks[3], 14, 105000},
+
+	/* Sentinel */
+	{NULL, 0, NULL, 0, 0}
+};

From 86b3901ba5034c624b1a4a771adffe272200a293 Mon Sep 17 00:00:00 2001
From: Kapil Porwal <kapilporwal@google.com>
Date: Mon, 9 Mar 2026 18:03:59 +0530
Subject: [PATCH 3745/3886] mb/google/bluey: Monitor thermal sensors during
 charging

Integrate thermal monitoring into the low-battery and off-mode charging
flow.

During battery charging in the ramstage, the system now scans all
thermal zones. If any sensor trips its defined threshold, the system
executes an emergency power-off to protect the hardware from thermal
damage.

TEST=Verify all x1p42100 thermal zones are readable on Google/Quartz.
TEST=Verify system shutdown on a thermal trip on Google/Quartz.

Change-Id: Id45d5f097dfb0c7b01e0541e116f5356f59f8269
Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91611
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/google/bluey/charging.c | 10 +++++++++-
 1 file changed, 9 insertions(+), 1 deletion(-)

diff --git a/src/mainboard/google/bluey/charging.c b/src/mainboard/google/bluey/charging.c
index 2e0fcb2baf..cb4ecf2855 100644
--- a/src/mainboard/google/bluey/charging.c
+++ b/src/mainboard/google/bluey/charging.c
@@ -7,6 +7,7 @@
 #include <reset.h>
 #include <soc/pmic.h>
 #include <soc/qcom_spmi.h>
+#include <soc/qcom_tsens.h>
 #include <timer.h>
 #include <types.h>
 
@@ -130,6 +131,7 @@ void launch_charger_applet(void)
 
 	static const long charging_enable_timeout_ms = CHARGING_RAIL_STABILIZATION_DELAY_MS;
 	struct stopwatch sw;
+	bool has_crossed_threshold = false;
 
 	printk(BIOS_INFO, "Inside %s. Initiating charging\n", __func__);
 
@@ -187,7 +189,13 @@ void launch_charger_applet(void)
 			do_board_reset();
 		}
 
-		/* TODO: add Tsense support and issue a shutdown in the event of temperature trip */
+		/* Issue a shutdown in the event of temperature trip */
+		qcom_tsens_monitor_all(&has_crossed_threshold);
+		if (has_crossed_threshold) {
+			printk(BIOS_INFO, "Issuing power-off due to temperature trip.\n");
+			google_chromeec_offmode_heartbeat();
+			google_chromeec_ap_poweroff();
+		}
 	} while (true);
 }
 

From 5e146277aef8619a6b67e3f541e0dc9d10bb8e96 Mon Sep 17 00:00:00 2001
From: Angel Pons <th3fanbus@gmail.com>
Date: Thu, 19 Mar 2026 09:19:48 +0100
Subject: [PATCH 3746/3886] Doc/nb/intel/haswell: Drop outdated section about
 SPD addresses

The docs talk about left-shifting SPD addresses by 1. This was necessary
back when mainboard code would directly set the values of the members in
`struct pei_data`, which stopped being the case with commit 1e2821882f38
("nb/intel/haswell: Use unshifted SPD addresses in mainboards").

Given that `util/autoport` (which now supports Haswell / Lynx Point) has
documentation on how to figure out the SPD address mapping in a platform
agnostic format, drop the outdated section from Haswell-specific docs.

Change-Id: I3d118b2e116cf2cd0096c8ef27e2fd22e6e548ae
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91759
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
---
 .../northbridge/intel/haswell/mrc.bin.md      | 77 -------------------
 1 file changed, 77 deletions(-)

diff --git a/Documentation/northbridge/intel/haswell/mrc.bin.md b/Documentation/northbridge/intel/haswell/mrc.bin.md
index c24305eb7e..447d8fb391 100644
--- a/Documentation/northbridge/intel/haswell/mrc.bin.md
+++ b/Documentation/northbridge/intel/haswell/mrc.bin.md
@@ -27,83 +27,6 @@ Now, place `mrc.bin` in the root of the coreboot directory.
 Alternatively, place `mrc.bin` anywhere you want, and set `MRC_FILE` to
 its location when building coreboot.
 
-## SPD Addresses
-
-When porting a board from vendor firmware, the SPD addresses can be obtained
-through `i2c-tools`, which can be found in many GNU/Linux distributions. A more
-[detailed description](https://hannuhartikainen.fi/blog/hacking-ddr3-spd/) of
-the procedure and beyond can be found in
-[Hannu Hartikainen's blog](https://hannuhartikainen.fi).
-
-First load the kernel modules:
-
-```bash
-modprobe i2c-dev
-modprobe eeprom
-```
-
-Find the SMBus and the addresses of the DIMM's EEPROMs (example output):
-```bash
-$ decode-dimms | grep Decoding
-Decoding EEPROM: /sys/bus/i2c/drivers/eeprom/7-0050
-Decoding EEPROM: /sys/bus/i2c/drivers/eeprom/7-0052
-```
-
-Alternatively, look at the sys filesystem:
-```bash
-$ ls -l /sys/bus/i2c/drivers/eeprom/
-total 0
-lrwxrwxrwx 1 root root    0 Apr  4 01:46 6-0050 -> ../../../../devices/pci0000:00/0000:00:02.0/drm/card0/card0-eDP-1/i2c-6/6-0050/
-lrwxrwxrwx 1 root root    0 Apr  4 01:46 7-0050 -> ../../../../devices/pci0000:00/0000:00:1f.3/i2c-7/7-0050/
-lrwxrwxrwx 1 root root    0 Apr  4 01:46 7-0052 -> ../../../../devices/pci0000:00/0000:00:1f.3/i2c-7/7-0052/
---w------- 1 root root 4096 Apr  4 01:47 bind
-lrwxrwxrwx 1 root root    0 Apr  4 01:47 module -> ../../../../module/eeprom/
---w------- 1 root root 4096 Apr  4 01:46 uevent
---w------- 1 root root 4096 Apr  4 01:47 unbind
-```
-
-The correct I2C bus is 7 in this case, and the EEPROMs are at `0x50` and `0x52`.
-Note that the above values are actually hex values.
-
-You can check the correctness of the SMBus and the addresses of the EEPROMs via
-`i2cdetect`:
-
-```bash
-$ i2cdetect -l
-i2c-3   unknown         i915 gmbus dpc                          N/A
-i2c-1   unknown         i915 gmbus vga                          N/A
-i2c-6   unknown         DPDDC-A                                 N/A
-i2c-4   unknown         i915 gmbus dpb                          N/A
-i2c-2   unknown         i915 gmbus panel                        N/A
-i2c-0   unknown         i915 gmbus ssc                          N/A
-i2c-7   unknown         SMBus I801 adapter at f040              N/A
-i2c-5   unknown         i915 gmbus dpd                          N/A
-```
-
-Probing the SMBus:
-
-```bash
-$ i2cdetect -r 7
-WARNING! This program can confuse your I2C bus, cause data loss and worse!
-I will probe file /dev/i2c-7 using receive byte commands.
-I will probe address range 0x03-0x77.
-Continue? [Y/n]
-     0  1  2  3  4  5  6  7  8  9  a  b  c  d  e  f
-00:          -- -- -- -- -- -- -- -- -- -- -- -- --
-10: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-20: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-30: 30 -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-40: -- -- -- -- 44 -- -- -- -- -- -- -- -- -- -- --
-50: UU -- UU -- -- -- -- -- -- -- -- -- -- -- -- --
-60: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-70: -- -- -- -- -- -- -- --
-```
-
-The SPD addresses need to be left-shifted by 1 for `mrc.bin`, i.e., multiplied
-by 2. For example, if the addresses read through `i2c-tools` when booted from
-vendor firmware are `0x50` and `0x52`, the correct values would be `0xa0` and
-`0xa4`. This is because the I2C addresses are 7 bits long.
-
 ## ECC DRAM
 
 When `mrc.bin` has finished executing, ECC is active on the channels

From 0f30eed3e810b34ce698f156bd5f2742a95d367b Mon Sep 17 00:00:00 2001
From: Angel Pons <th3fanbus@gmail.com>
Date: Thu, 19 Mar 2026 09:45:49 +0100
Subject: [PATCH 3747/3886] Doc/nb/intel/haswell: Fix typo

Chomeboxes ---> Chromeboxes

Change-Id: Ifdd9a1374d4d021c2777694937da2c81d22004e7
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91760
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
---
 Documentation/northbridge/intel/haswell/mrc.bin.md | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/Documentation/northbridge/intel/haswell/mrc.bin.md b/Documentation/northbridge/intel/haswell/mrc.bin.md
index 447d8fb391..2f31da377a 100644
--- a/Documentation/northbridge/intel/haswell/mrc.bin.md
+++ b/Documentation/northbridge/intel/haswell/mrc.bin.md
@@ -31,6 +31,6 @@ its location when building coreboot.
 
 When `mrc.bin` has finished executing, ECC is active on the channels
 populated with ECC DIMMs. However, `mrc.bin` was tailored specifically
-for Haswell Chromebooks and Chomeboxes, none of which support ECC DRAM.
+for Haswell Chromebooks and Chromeboxes, none of which support ECC DRAM.
 While ECC likely functions correctly, it is advised to further validate
 the correct operation of ECC if data integrity is absolutely critical.

From 05246a59342ac21027ddce017401f73adeac7c43 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Jan=20Philipp=20Gro=C3=9F?= <jeangrande@mailbox.org>
Date: Sat, 14 Mar 2026 14:09:59 +0100
Subject: [PATCH 3748/3886] mb/asus: Add Maximus VII Impact (Haswell/Broadwell)
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Based on Autoport with subsequent manual tweaking. The system boots
with an Intel i7-4770K using Haswell NRI. Thanks to Angel Pons for
fixing S3 suspend/resume.

Working:
- Haswell CPUs
- Haswell NRI
- Both DDR3 DIMM slots
- HDMI Port
- DP Port
- All rear USB ports
- Audio Jack
- Ethernet port
- WiFi and M.2
- All SATA ports
- Discrete Graphics (tested with AMD R9 Nano)
- TPM 2.0
- S3 suspend and resume

Not working:
- Rear double-digit display does not show CPU temp.
- Known issue: Broadwell (non-ULT) CPUs are not yet supported in coreboot

Not (yet) tested:
- USB headers

Change-Id: I6813adce267af6bd449f72b0595dfec9277961bf
Signed-off-by: Jan Philipp Groß <jeangrande@mailbox.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91672
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/asus/maximus_vii_impact/Kconfig |  29 +++
 .../asus/maximus_vii_impact/Kconfig.name      |   4 +
 .../asus/maximus_vii_impact/Makefile.mk       |   5 +
 .../asus/maximus_vii_impact/acpi/ec.asl       |   3 +
 .../asus/maximus_vii_impact/acpi/platform.asl |  10 +
 .../asus/maximus_vii_impact/acpi/superio.asl  |   3 +
 .../asus/maximus_vii_impact/board_info.txt    |   7 +
 .../asus/maximus_vii_impact/data.vbt          | Bin 0 -> 6144 bytes
 .../asus/maximus_vii_impact/devicetree.cb     | 134 +++++++++++
 .../asus/maximus_vii_impact/dsdt.asl          |  27 +++
 .../asus/maximus_vii_impact/gma-mainboard.ads |  21 ++
 src/mainboard/asus/maximus_vii_impact/gpio.c  | 211 ++++++++++++++++++
 .../asus/maximus_vii_impact/hda_verb.c        |  33 +++
 .../asus/maximus_vii_impact/romstage.c        |  37 +++
 14 files changed, 524 insertions(+)
 create mode 100644 src/mainboard/asus/maximus_vii_impact/Kconfig
 create mode 100644 src/mainboard/asus/maximus_vii_impact/Kconfig.name
 create mode 100644 src/mainboard/asus/maximus_vii_impact/Makefile.mk
 create mode 100644 src/mainboard/asus/maximus_vii_impact/acpi/ec.asl
 create mode 100644 src/mainboard/asus/maximus_vii_impact/acpi/platform.asl
 create mode 100644 src/mainboard/asus/maximus_vii_impact/acpi/superio.asl
 create mode 100644 src/mainboard/asus/maximus_vii_impact/board_info.txt
 create mode 100644 src/mainboard/asus/maximus_vii_impact/data.vbt
 create mode 100644 src/mainboard/asus/maximus_vii_impact/devicetree.cb
 create mode 100644 src/mainboard/asus/maximus_vii_impact/dsdt.asl
 create mode 100644 src/mainboard/asus/maximus_vii_impact/gma-mainboard.ads
 create mode 100644 src/mainboard/asus/maximus_vii_impact/gpio.c
 create mode 100644 src/mainboard/asus/maximus_vii_impact/hda_verb.c
 create mode 100644 src/mainboard/asus/maximus_vii_impact/romstage.c

diff --git a/src/mainboard/asus/maximus_vii_impact/Kconfig b/src/mainboard/asus/maximus_vii_impact/Kconfig
new file mode 100644
index 0000000000..1e8be71e2f
--- /dev/null
+++ b/src/mainboard/asus/maximus_vii_impact/Kconfig
@@ -0,0 +1,29 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
+if BOARD_ASUS_MAXIMUS_VII_IMPACT
+
+config BOARD_SPECIFIC_OPTIONS
+	def_bool y
+	select BOARD_ROMSIZE_KB_8192
+	select HAVE_ACPI_RESUME
+	select HAVE_ACPI_TABLES
+	select INTEL_GMA_HAVE_VBT
+	select MEMORY_MAPPED_TPM
+	select MAINBOARD_HAS_LIBGFXINIT
+	select MAINBOARD_USES_IFD_GBE_REGION
+	select NORTHBRIDGE_INTEL_HASWELL
+	select SERIRQ_CONTINUOUS_MODE
+	select SOUTHBRIDGE_INTEL_LYNXPOINT
+	select SUPERIO_NUVOTON_NCT6791D
+	select USE_BROADWELL_MRC if !USE_NATIVE_RAMINIT
+
+config MAINBOARD_DIR
+	default "asus/maximus_vii_impact"
+
+config MAINBOARD_PART_NUMBER
+	default "Maximus VII IMPACT"
+
+config USBDEBUG_HCD_INDEX # FIXME: check this
+	int
+	default 2
+endif
diff --git a/src/mainboard/asus/maximus_vii_impact/Kconfig.name b/src/mainboard/asus/maximus_vii_impact/Kconfig.name
new file mode 100644
index 0000000000..d5a59d8f4c
--- /dev/null
+++ b/src/mainboard/asus/maximus_vii_impact/Kconfig.name
@@ -0,0 +1,4 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
+config BOARD_ASUS_MAXIMUS_VII_IMPACT
+	bool "Maximus VII IMPACT"
diff --git a/src/mainboard/asus/maximus_vii_impact/Makefile.mk b/src/mainboard/asus/maximus_vii_impact/Makefile.mk
new file mode 100644
index 0000000000..c9500cfe9b
--- /dev/null
+++ b/src/mainboard/asus/maximus_vii_impact/Makefile.mk
@@ -0,0 +1,5 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
+bootblock-y += gpio.c
+romstage-y += gpio.c
+ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads
diff --git a/src/mainboard/asus/maximus_vii_impact/acpi/ec.asl b/src/mainboard/asus/maximus_vii_impact/acpi/ec.asl
new file mode 100644
index 0000000000..16990d45f4
--- /dev/null
+++ b/src/mainboard/asus/maximus_vii_impact/acpi/ec.asl
@@ -0,0 +1,3 @@
+/* SPDX-License-Identifier: CC-PDDC */
+
+/* Please update the license if adding licensable material. */
diff --git a/src/mainboard/asus/maximus_vii_impact/acpi/platform.asl b/src/mainboard/asus/maximus_vii_impact/acpi/platform.asl
new file mode 100644
index 0000000000..aff432b6f4
--- /dev/null
+++ b/src/mainboard/asus/maximus_vii_impact/acpi/platform.asl
@@ -0,0 +1,10 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+Method(_WAK, 1)
+{
+	Return(Package() {0, 0})
+}
+
+Method(_PTS, 1)
+{
+}
diff --git a/src/mainboard/asus/maximus_vii_impact/acpi/superio.asl b/src/mainboard/asus/maximus_vii_impact/acpi/superio.asl
new file mode 100644
index 0000000000..16990d45f4
--- /dev/null
+++ b/src/mainboard/asus/maximus_vii_impact/acpi/superio.asl
@@ -0,0 +1,3 @@
+/* SPDX-License-Identifier: CC-PDDC */
+
+/* Please update the license if adding licensable material. */
diff --git a/src/mainboard/asus/maximus_vii_impact/board_info.txt b/src/mainboard/asus/maximus_vii_impact/board_info.txt
new file mode 100644
index 0000000000..2913218dfe
--- /dev/null
+++ b/src/mainboard/asus/maximus_vii_impact/board_info.txt
@@ -0,0 +1,7 @@
+Category: desktop
+Board URL: https://rog.asus.com/motherboards/rog-maximus/rog-maximus-vi-impact-model/
+ROM protocol: SPI
+Flashrom support: y
+ROM package: DIP-8
+ROM socketed: y
+Release year: 2014
diff --git a/src/mainboard/asus/maximus_vii_impact/data.vbt b/src/mainboard/asus/maximus_vii_impact/data.vbt
new file mode 100644
index 0000000000000000000000000000000000000000..04c363ae3fd45ed0952e76eab914af8ea675966f
GIT binary patch
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z{q{mKxvRYYd^eP7ZCPtByqL+X@ixM)6q1LxYqJwcUzx5Et6bx3+OjTV6d7kBqwu$6
zCWa?hAww0t3ji7HS>xp_PT0o_SP!38PF(FCU#Z1UF3U4;;HI{yI|^aYs`RPkcuMnj
zn_scC4;(H>%J2`@q`@GW40ck$C~o>-B2JcRq86ri8F}EcxF4|(8E2ER9v;6p+2)LQ
ze^ZT~sF|G$4m<_}mN3Ws`=U~ZWCn_pic&=HGW&ql6h$oX75>zO(Lp^Z&+P|CyRrrn
z=i8_7e_}z-xrd~B3B1>a-H74;#3qPC3aXjoaD%Iz1UQnHr^9?On~SZ*3@m0~F$0Sk
KSj@meW#DfwW(oQL

literal 0
HcmV?d00001

diff --git a/src/mainboard/asus/maximus_vii_impact/devicetree.cb b/src/mainboard/asus/maximus_vii_impact/devicetree.cb
new file mode 100644
index 0000000000..0e8b133311
--- /dev/null
+++ b/src/mainboard/asus/maximus_vii_impact/devicetree.cb
@@ -0,0 +1,134 @@
+## SPDX-License-Identifier: GPL-2.0-or-later
+
+chip northbridge/intel/haswell
+	register "gpu_dp_b_hotplug" = "4"
+	register "gpu_dp_c_hotplug" = "0"
+	register "gpu_dp_d_hotplug" = "4"
+	register "spd_addresses" = "{0x50, 0, 0x52, 0}"
+	register "usb_xhci_on_resume" = "false"
+
+	chip cpu/intel/haswell
+		device cpu_cluster 0 on
+			ops haswell_cpu_bus_ops
+		end
+	end
+
+	device domain 0 on
+		ops haswell_pci_domain_ops
+		subsystemid 0x1043 0x8534 inherit
+
+		device pci 00.0 on end		# Desktop Host bridge
+		device pci 01.0 on end		# PEG
+		device pci 02.0 on end		# iGPU
+		device pci 03.0 on end		# Mini-HD audio
+
+		chip southbridge/intel/lynxpoint # Intel 8 Series Lynx Point PCH
+			register "gen1_dec" = "0x003c0291"
+			register "gen2_dec" = "0x007c0a01"
+			register "gen3_dec" = "0x00040069"
+			register "gpe0_en_1" = "0x40002246"
+			register "gpe0_en_2" = "0x0"
+			register "sata_port0_gen3_dtle" = "0x2"
+			register "sata_port1_gen3_dtle" = "0x2"
+			register "sata_port_map" = "0x3f"
+
+			device pci 14.0 on  end		# xHCI Controller
+			device pci 16.0 on  end		# MEI #1
+			device pci 16.1 off end		# MEI #2
+			device pci 19.0 on		# Intel Gigabit Ethernet
+				subsystemid 0x1043 0x85c4
+			end
+			device pci 1a.0 on  end		# USB2 EHCI #2
+			device pci 1b.0 on		# High Definition Audio
+				subsystemid 0x1043 0x8603
+			end
+			device pci 1c.0 on  end		# RP #1
+			device pci 1c.1 off end		# RP #2
+			device pci 1c.2 off end		# RP #3
+			device pci 1c.3 on  end		# RP #4: mPCIe WiFi
+			device pci 1c.4 off end		# RP #5
+			device pci 1c.5 off end		# RP #6
+			device pci 1c.6 off end		# RP #7
+			device pci 1c.7 off end		# RP #8
+			device pci 1d.0 on  end		# USB2 EHCI #1
+			device pci 1f.0 on		# LPC bridge
+				chip superio/common
+					device pnp 2e.0 on
+						chip superio/nuvoton/nct6791d
+							device pnp 2e.1   off end	# Parallel
+							device pnp 2e.2   off end	# UART A
+							device pnp 2e.3   off end	# IR
+							device pnp 2e.5   on		# PS/2 Keyboard/Mouse
+								io  0x60 = 0x0060
+								io  0x62 = 0x0064
+								irq 0x70 = 1		# + Keyboard IRQ
+								irq 0x72 = 12		# + Mouse IRQ
+							end
+							device pnp 2e.6   off end	# CIR
+							device pnp 2e.7   off end	# GPIO6
+							device pnp 2e.107 off end	# GPIO7
+							device pnp 2e.207 off end	# GPIO8
+							device pnp 2e.8   off end	# WDT
+							device pnp 2e.108 on		# GPIO0
+							end
+							device pnp 2e.308 off end	# GPIO base
+							device pnp 2e.408 off end	# WDTMEM
+							device pnp 2e.708 on		# GPIO1
+								irq 0xf1 = 0xb3
+							end
+							device pnp 2e.9   on		# GPIO2
+								irq 0xe0 = 0xdf
+								irq 0xe1 = 0xd0
+							end
+							device pnp 2e.109 on		# GPIO3
+								irq 0xe5 = 0x10
+								irq 0xe7 = 0x70
+							end
+							device pnp 2e.209 on		# GPIO4
+								irq 0xf1 = 0x36
+							end
+							device pnp 2e.309 on		# GPIO5
+								irq 0xf4 = 0xef
+								irq 0xf5 = 0x68
+							end
+							device pnp 2e.a   on		# ACPI
+								# Power RAM in S3
+								irq 0xe4 = 0x10
+								irq 0xe6 = 0x0a
+								irq 0xe7 = 0x11
+								irq 0xec = 0x80
+								irq 0xed = 0x01
+								irq 0xee = 0x10
+								irq 0xf2 = 0x5d
+							end
+							device pnp 2e.b   on		# HWM, LED
+								irq 0x30 = 0x01		# + Fan RPM sense pins
+								io  0x60 = 0x0290	# + HWM base address
+								io  0x62 = 0
+								irq 0x70 = 0
+							end
+							device pnp 2e.d   off end	# BCLK, WDT2, WDT_MEM
+							device pnp 2e.e   off end	# CIR wake-up
+							device pnp 2e.f   off end	# GPIO PP/OD
+							device pnp 2e.14  off end	# SVID, Port 80 UART
+							device pnp 2e.16  off end	# DS5
+							device pnp 2e.116 off end	# DS3
+							device pnp 2e.316 off end	# PCHDSW
+							device pnp 2e.416 off end	# DSWWOPT
+							device pnp 2e.516 on  end	# DS3OPT
+							device pnp 2e.616 off end	# DSDSS
+							device pnp 2e.716 off end	# DSPU
+						end
+					end
+				end
+				chip drivers/pc80/tpm
+					device pnp 0c31.0 on end	# TPM
+				end
+			end
+			device pci 1f.2 on  end		# SATA Controller (AHCI)
+			device pci 1f.3 on  end		# SMBus
+			device pci 1f.5 off end		# SATA Controller (Legacy)
+			device pci 1f.6 off end		# Thermal
+		end
+	end
+end
diff --git a/src/mainboard/asus/maximus_vii_impact/dsdt.asl b/src/mainboard/asus/maximus_vii_impact/dsdt.asl
new file mode 100644
index 0000000000..2eb0805cf2
--- /dev/null
+++ b/src/mainboard/asus/maximus_vii_impact/dsdt.asl
@@ -0,0 +1,27 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <acpi/acpi.h>
+
+DefinitionBlock(
+	"dsdt.aml",
+	"DSDT",
+	ACPI_DSDT_REV_2,
+	OEM_ID,
+	ACPI_TABLE_CREATOR,
+	0x20141018
+)
+{
+	#include <acpi/dsdt_top.asl>
+	#include "acpi/platform.asl"
+	#include <cpu/intel/common/acpi/cpu.asl>
+	#include <southbridge/intel/common/acpi/platform.asl>
+	/* global NVS and variables. */
+	#include <southbridge/intel/lynxpoint/acpi/globalnvs.asl>
+	#include <southbridge/intel/common/acpi/sleepstates.asl>
+
+	Device (\_SB.PCI0)
+	{
+		#include <northbridge/intel/haswell/acpi/hostbridge.asl>
+		#include <southbridge/intel/lynxpoint/acpi/pch.asl>
+	}
+}
diff --git a/src/mainboard/asus/maximus_vii_impact/gma-mainboard.ads b/src/mainboard/asus/maximus_vii_impact/gma-mainboard.ads
new file mode 100644
index 0000000000..938687fac9
--- /dev/null
+++ b/src/mainboard/asus/maximus_vii_impact/gma-mainboard.ads
@@ -0,0 +1,21 @@
+-- SPDX-License-Identifier: GPL-2.0-or-later
+
+with HW.GFX.GMA;
+with HW.GFX.GMA.Display_Probing;
+
+use HW.GFX.GMA;
+use HW.GFX.GMA.Display_Probing;
+
+private package GMA.Mainboard is
+
+   -- FIXME: check this
+   ports : constant Port_List :=
+     (DP1,
+      DP2,
+      DP3,
+      HDMI1,
+      HDMI2,
+      HDMI3,
+      others => Disabled);
+
+end GMA.Mainboard;
diff --git a/src/mainboard/asus/maximus_vii_impact/gpio.c b/src/mainboard/asus/maximus_vii_impact/gpio.c
new file mode 100644
index 0000000000..7b4720c012
--- /dev/null
+++ b/src/mainboard/asus/maximus_vii_impact/gpio.c
@@ -0,0 +1,211 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <southbridge/intel/common/gpio.h>
+
+static const struct pch_gpio_set1 pch_gpio_set1_mode = {
+	.gpio0 = GPIO_MODE_GPIO,
+	.gpio1 = GPIO_MODE_GPIO,
+	.gpio2 = GPIO_MODE_GPIO,
+	.gpio3 = GPIO_MODE_GPIO,
+	.gpio4 = GPIO_MODE_GPIO,
+	.gpio5 = GPIO_MODE_GPIO,
+	.gpio6 = GPIO_MODE_GPIO,
+	.gpio7 = GPIO_MODE_GPIO,
+	.gpio8 = GPIO_MODE_GPIO,
+	.gpio9 = GPIO_MODE_NATIVE,
+	.gpio10 = GPIO_MODE_NATIVE,
+	.gpio11 = GPIO_MODE_NATIVE,
+	.gpio12 = GPIO_MODE_NATIVE,
+	.gpio13 = GPIO_MODE_GPIO,
+	.gpio14 = GPIO_MODE_GPIO,
+	.gpio15 = GPIO_MODE_GPIO,
+	.gpio16 = GPIO_MODE_NATIVE,
+	.gpio17 = GPIO_MODE_GPIO,
+	.gpio18 = GPIO_MODE_GPIO,
+	.gpio19 = GPIO_MODE_GPIO,
+	.gpio20 = GPIO_MODE_GPIO,
+	.gpio21 = GPIO_MODE_GPIO,
+	.gpio22 = GPIO_MODE_GPIO,
+	.gpio23 = GPIO_MODE_GPIO,
+	.gpio24 = GPIO_MODE_GPIO,
+	.gpio25 = GPIO_MODE_GPIO,
+	.gpio26 = GPIO_MODE_GPIO,
+	.gpio27 = GPIO_MODE_GPIO,
+	.gpio28 = GPIO_MODE_GPIO,
+	.gpio29 = GPIO_MODE_GPIO,
+	.gpio30 = GPIO_MODE_GPIO,
+	.gpio31 = GPIO_MODE_GPIO,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_direction = {
+	.gpio0 = GPIO_DIR_INPUT,
+	.gpio1 = GPIO_DIR_INPUT,
+	.gpio2 = GPIO_DIR_INPUT,
+	.gpio3 = GPIO_DIR_INPUT,
+	.gpio4 = GPIO_DIR_INPUT,
+	.gpio5 = GPIO_DIR_INPUT,
+	.gpio6 = GPIO_DIR_INPUT,
+	.gpio7 = GPIO_DIR_INPUT,
+	.gpio8 = GPIO_DIR_OUTPUT,
+	.gpio13 = GPIO_DIR_INPUT,
+	.gpio14 = GPIO_DIR_INPUT,
+	.gpio15 = GPIO_DIR_OUTPUT,
+	.gpio17 = GPIO_DIR_INPUT,
+	.gpio18 = GPIO_DIR_INPUT,
+	.gpio19 = GPIO_DIR_INPUT,
+	.gpio20 = GPIO_DIR_INPUT,
+	.gpio21 = GPIO_DIR_INPUT,
+	.gpio22 = GPIO_DIR_INPUT,
+	.gpio23 = GPIO_DIR_INPUT,
+	.gpio24 = GPIO_DIR_OUTPUT,
+	.gpio25 = GPIO_DIR_INPUT,
+	.gpio26 = GPIO_DIR_INPUT,
+	.gpio27 = GPIO_DIR_INPUT,
+	.gpio28 = GPIO_DIR_OUTPUT,
+	.gpio29 = GPIO_DIR_INPUT,
+	.gpio30 = GPIO_DIR_INPUT,
+	.gpio31 = GPIO_DIR_INPUT,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_level = {
+	.gpio8 = GPIO_LEVEL_HIGH,
+	.gpio15 = GPIO_LEVEL_LOW,
+	.gpio24 = GPIO_LEVEL_LOW,
+	.gpio28 = GPIO_LEVEL_LOW,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_reset = {
+	.gpio8 = GPIO_RESET_RSMRST,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_invert = {
+	.gpio2 = GPIO_INVERT,
+	.gpio4 = GPIO_INVERT,
+	.gpio6 = GPIO_INVERT,
+	.gpio13 = GPIO_INVERT,
+	.gpio14 = GPIO_INVERT,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_blink = {
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_mode = {
+	.gpio32 = GPIO_MODE_GPIO,
+	.gpio33 = GPIO_MODE_GPIO,
+	.gpio34 = GPIO_MODE_GPIO,
+	.gpio35 = GPIO_MODE_GPIO,
+	.gpio36 = GPIO_MODE_GPIO,
+	.gpio37 = GPIO_MODE_GPIO,
+	.gpio38 = GPIO_MODE_GPIO,
+	.gpio39 = GPIO_MODE_GPIO,
+	.gpio40 = GPIO_MODE_NATIVE,
+	.gpio41 = GPIO_MODE_NATIVE,
+	.gpio42 = GPIO_MODE_NATIVE,
+	.gpio43 = GPIO_MODE_NATIVE,
+	.gpio44 = GPIO_MODE_GPIO,
+	.gpio45 = GPIO_MODE_GPIO,
+	.gpio46 = GPIO_MODE_GPIO,
+	.gpio47 = GPIO_MODE_NATIVE,
+	.gpio48 = GPIO_MODE_GPIO,
+	.gpio49 = GPIO_MODE_NATIVE,
+	.gpio50 = GPIO_MODE_GPIO,
+	.gpio51 = GPIO_MODE_GPIO,
+	.gpio52 = GPIO_MODE_GPIO,
+	.gpio53 = GPIO_MODE_GPIO,
+	.gpio54 = GPIO_MODE_GPIO,
+	.gpio55 = GPIO_MODE_GPIO,
+	.gpio56 = GPIO_MODE_NATIVE,
+	.gpio57 = GPIO_MODE_GPIO,
+	.gpio58 = GPIO_MODE_NATIVE,
+	.gpio59 = GPIO_MODE_NATIVE,
+	.gpio60 = GPIO_MODE_NATIVE,
+	.gpio61 = GPIO_MODE_NATIVE,
+	.gpio62 = GPIO_MODE_NATIVE,
+	.gpio63 = GPIO_MODE_NATIVE,
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_direction = {
+	.gpio32 = GPIO_DIR_OUTPUT,
+	.gpio33 = GPIO_DIR_OUTPUT,
+	.gpio34 = GPIO_DIR_INPUT,
+	.gpio35 = GPIO_DIR_INPUT,
+	.gpio36 = GPIO_DIR_INPUT,
+	.gpio37 = GPIO_DIR_INPUT,
+	.gpio38 = GPIO_DIR_INPUT,
+	.gpio39 = GPIO_DIR_INPUT,
+	.gpio44 = GPIO_DIR_INPUT,
+	.gpio45 = GPIO_DIR_INPUT,
+	.gpio46 = GPIO_DIR_INPUT,
+	.gpio48 = GPIO_DIR_OUTPUT,
+	.gpio50 = GPIO_DIR_INPUT,
+	.gpio51 = GPIO_DIR_OUTPUT,
+	.gpio52 = GPIO_DIR_INPUT,
+	.gpio53 = GPIO_DIR_OUTPUT,
+	.gpio54 = GPIO_DIR_INPUT,
+	.gpio55 = GPIO_DIR_OUTPUT,
+	.gpio57 = GPIO_DIR_INPUT,
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_level = {
+	.gpio32 = GPIO_LEVEL_HIGH,
+	.gpio33 = GPIO_LEVEL_HIGH,
+	.gpio48 = GPIO_LEVEL_LOW,
+	.gpio51 = GPIO_LEVEL_HIGH,
+	.gpio53 = GPIO_LEVEL_HIGH,
+	.gpio55 = GPIO_LEVEL_HIGH,
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_reset = {
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_mode = {
+	.gpio64 = GPIO_MODE_NATIVE,
+	.gpio65 = GPIO_MODE_NATIVE,
+	.gpio66 = GPIO_MODE_NATIVE,
+	.gpio67 = GPIO_MODE_NATIVE,
+	.gpio68 = GPIO_MODE_GPIO,
+	.gpio69 = GPIO_MODE_GPIO,
+	.gpio70 = GPIO_MODE_GPIO,
+	.gpio71 = GPIO_MODE_GPIO,
+	.gpio72 = GPIO_MODE_GPIO,
+	.gpio73 = GPIO_MODE_NATIVE,
+	.gpio74 = GPIO_MODE_NATIVE,
+	.gpio75 = GPIO_MODE_NATIVE,
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_direction = {
+	.gpio68 = GPIO_DIR_INPUT,
+	.gpio69 = GPIO_DIR_INPUT,
+	.gpio70 = GPIO_DIR_INPUT,
+	.gpio71 = GPIO_DIR_INPUT,
+	.gpio72 = GPIO_DIR_INPUT,
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_level = {
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_reset = {
+};
+
+const struct pch_gpio_map mainboard_gpio_map = {
+	.set1 = {
+		.mode		= &pch_gpio_set1_mode,
+		.direction	= &pch_gpio_set1_direction,
+		.level		= &pch_gpio_set1_level,
+		.blink		= &pch_gpio_set1_blink,
+		.invert		= &pch_gpio_set1_invert,
+		.reset		= &pch_gpio_set1_reset,
+	},
+	.set2 = {
+		.mode		= &pch_gpio_set2_mode,
+		.direction	= &pch_gpio_set2_direction,
+		.level		= &pch_gpio_set2_level,
+		.reset		= &pch_gpio_set2_reset,
+	},
+	.set3 = {
+		.mode		= &pch_gpio_set3_mode,
+		.direction	= &pch_gpio_set3_direction,
+		.level		= &pch_gpio_set3_level,
+		.reset		= &pch_gpio_set3_reset,
+	},
+};
diff --git a/src/mainboard/asus/maximus_vii_impact/hda_verb.c b/src/mainboard/asus/maximus_vii_impact/hda_verb.c
new file mode 100644
index 0000000000..c310165c53
--- /dev/null
+++ b/src/mainboard/asus/maximus_vii_impact/hda_verb.c
@@ -0,0 +1,33 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <device/azalia_device.h>
+
+static const u32 realtek_alc900_verbs[] = {
+	AZALIA_SUBVENDOR(0, 0x10438603),
+	AZALIA_PIN_CFG(0, 0x11, 0x411111f0),
+	AZALIA_PIN_CFG(0, 0x14, 0x01014010),
+	AZALIA_PIN_CFG(0, 0x15, 0x411111f0),
+	AZALIA_PIN_CFG(0, 0x16, 0x411111f0),
+	AZALIA_PIN_CFG(0, 0x17, 0x4007c000),
+	AZALIA_PIN_CFG(0, 0x18, 0x01a19050),
+	AZALIA_PIN_CFG(0, 0x19, 0x02a19060),
+	AZALIA_PIN_CFG(0, 0x1a, 0x0181305f),
+	AZALIA_PIN_CFG(0, 0x1b, 0x0221401f),
+	AZALIA_PIN_CFG(0, 0x1e, 0x01456140),
+};
+
+const u32 pc_beep_verbs[0] = {};
+
+struct azalia_codec mainboard_azalia_codecs[] = {
+	{
+		.name         = "Realtek ALC900",
+		.vendor_id    = 0x10ec0900,
+		.subsystem_id = 0x10438603,
+		.address      = 0,
+		.verbs        = realtek_alc900_verbs,
+		.verb_count   = ARRAY_SIZE(realtek_alc900_verbs),
+	},
+	{ /* terminator */ }
+};
+
+AZALIA_ARRAY_SIZES;
diff --git a/src/mainboard/asus/maximus_vii_impact/romstage.c b/src/mainboard/asus/maximus_vii_impact/romstage.c
new file mode 100644
index 0000000000..cb0a045d15
--- /dev/null
+++ b/src/mainboard/asus/maximus_vii_impact/romstage.c
@@ -0,0 +1,37 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <stdint.h>
+#include <northbridge/intel/haswell/haswell.h>
+#include <southbridge/intel/lynxpoint/pch.h>
+
+void mainboard_config_rcba(void)
+{
+}
+
+const struct usb2_port_config mainboard_usb2_ports[MAX_USB2_PORTS] = {
+	/* FIXME: Length and Location are computed from IOBP values, may be inaccurate */
+	/* Length, Enable, OCn#, Location */
+	{ 0x0040, 1, 0, USB_PORT_BACK_PANEL },
+	{ 0x0040, 1, USB_OC_PIN_SKIP, USB_PORT_FLEX },
+	{ 0x0110, 1, 1, USB_PORT_BACK_PANEL },
+	{ 0x0110, 1, 1, USB_PORT_BACK_PANEL },
+	{ 0x0110, 1, 2, USB_PORT_BACK_PANEL },
+	{ 0x0040, 1, 2, USB_PORT_BACK_PANEL },
+	{ 0x0140, 1, 3, USB_PORT_BACK_PANEL },
+	{ 0x0040, 1, 3, USB_PORT_BACK_PANEL },
+	{ 0x0110, 1, 4, USB_PORT_BACK_PANEL },
+	{ 0x0110, 1, 4, USB_PORT_BACK_PANEL },
+	{ 0x0040, 1, 5, USB_PORT_BACK_PANEL },
+	{ 0x0040, 1, 5, USB_PORT_BACK_PANEL },
+	{ 0x0040, 1, 6, USB_PORT_BACK_PANEL },
+	{ 0x0040, 1, 6, USB_PORT_BACK_PANEL },
+};
+
+const struct usb3_port_config mainboard_usb3_ports[MAX_USB3_PORTS] = {
+	{ 1, 0 },
+	{ 1, 0 },
+	{ 1, 1 },
+	{ 1, 1 },
+	{ 1, 2 },
+	{ 1, 2 },
+};

From a7773d3ab3d1edceb12c017a4b0edffe517bc652 Mon Sep 17 00:00:00 2001
From: WeiHuaLin <weihualin@huaqin.corp-partner.google.com>
Date: Wed, 11 Mar 2026 11:01:59 +0800
Subject: [PATCH 3749/3886] mb/google/fatcat: Modifying parameters for AC only
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

In the "AC only" scenario, since the adapter is 65W,
the values of PL2 and PL4 need to be reduced to prevent
the machine from shutting down.

BUG=b:487170924
TEST=emerge-fatcat coreboot, test pass by power engineer

Change-Id: Id0b1f886205f26a5171f21ae43a9360791e0979b
Signed-off-by: WeiHuaLin <weihualin@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91646
Reviewed-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 .../variants/baseboard/fatcat/ramstage.c       | 18 +++++++++++++++---
 1 file changed, 15 insertions(+), 3 deletions(-)

diff --git a/src/mainboard/google/fatcat/variants/baseboard/fatcat/ramstage.c b/src/mainboard/google/fatcat/variants/baseboard/fatcat/ramstage.c
index 224dda7443..5745dd1efc 100644
--- a/src/mainboard/google/fatcat/variants/baseboard/fatcat/ramstage.c
+++ b/src/mainboard/google/fatcat/variants/baseboard/fatcat/ramstage.c
@@ -18,9 +18,9 @@
 #define COMMON_PTL_U_POWER_LIMITS	\
 	.pl1_min_power = 10000,		\
 	.pl1_max_power = 15000,		\
-	.pl2_min_power = 50000,		\
-	.pl2_max_power = 50000,		\
-	.pl4_power = 65000
+	.pl2_min_power = 25000,		\
+	.pl2_max_power = 25000,		\
+	.pl4_power = 25000
 const struct cpu_tdp_power_limits power_optimized_limits[] = {
 	{
 		.mch_id = PCI_DID_INTEL_PTL_H_ID_1,
@@ -88,6 +88,18 @@ const struct cpu_tdp_power_limits power_optimized_limits[] = {
 		.power_limits_index = PTL_CORE_2,
 		COMMON_PTL_U_POWER_LIMITS
 	},
+	{
+		.mch_id = PCI_DID_INTEL_PTL_U_ID_1,
+		.cpu_tdp = TDP_25W,
+		.power_limits_index = PTL_CORE_1,
+		COMMON_PTL_U_POWER_LIMITS
+	},
+	{
+		.mch_id = PCI_DID_INTEL_PTL_U_ID_2,
+		.cpu_tdp = TDP_25W,
+		.power_limits_index = PTL_CORE_2,
+		COMMON_PTL_U_POWER_LIMITS
+	},
 };
 
 /*

From a215e075338f07db0cbf07f94e333dbe4bc9868c Mon Sep 17 00:00:00 2001
From: David Wu <david_wu@quanta.corp-partner.google.com>
Date: Thu, 19 Mar 2026 17:05:27 +0800
Subject: [PATCH 3750/3886] mb/google/nissa/var/craask: Add H58G56CK8BX146 to
 RAM ID table

Add the new memory support: Hynix H58G56CK8BX146

BUG=b:404452285
TEST=Run part_id_gen tool and check the generated files.

Change-Id: I576865cfd7f11b0c413fb60523769170b0f9be42
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91761
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
---
 src/mainboard/google/brya/variants/craask/memory/Makefile.mk     | 1 +
 .../google/brya/variants/craask/memory/dram_id.generated.txt     | 1 +
 .../google/brya/variants/craask/memory/mem_parts_used.txt        | 1 +
 3 files changed, 3 insertions(+)

diff --git a/src/mainboard/google/brya/variants/craask/memory/Makefile.mk b/src/mainboard/google/brya/variants/craask/memory/Makefile.mk
index 34d01a6f5f..84d3ef1b97 100644
--- a/src/mainboard/google/brya/variants/craask/memory/Makefile.mk
+++ b/src/mainboard/google/brya/variants/craask/memory/Makefile.mk
@@ -8,3 +8,4 @@ SPD_SOURCES += spd/lp5/set-0/spd-2.hex      # ID = 0(0b0000)  Parts = MT62F1G32D
 SPD_SOURCES += spd/lp5/set-0/spd-1.hex      # ID = 1(0b0001)  Parts = MT62F512M32D2DR-031 WT:B, H9JCNNNBK3MLYR-N6E
 SPD_SOURCES += spd/lp5/set-0/spd-5.hex      # ID = 2(0b0010)  Parts = K3LKLKL0EM-MGCN
 SPD_SOURCES += spd/lp5/set-0/spd-3.hex      # ID = 3(0b0011)  Parts = K3LKBKB0BM-MGCP
+SPD_SOURCES += spd/lp5/set-0/spd-11.hex      # ID = 4(0b0100)  Parts = H58G56CK8BX146
diff --git a/src/mainboard/google/brya/variants/craask/memory/dram_id.generated.txt b/src/mainboard/google/brya/variants/craask/memory/dram_id.generated.txt
index e17b510c58..ab1193c594 100644
--- a/src/mainboard/google/brya/variants/craask/memory/dram_id.generated.txt
+++ b/src/mainboard/google/brya/variants/craask/memory/dram_id.generated.txt
@@ -10,3 +10,4 @@ H9JCNNNBK3MLYR-N6E             1 (0001)
 K3LKLKL0EM-MGCN                2 (0010)
 K3LKBKB0BM-MGCP                3 (0011)
 H9JCNNNCP3MLYR-N6E             0 (0000)
+H58G56CK8BX146                 4 (0100)
diff --git a/src/mainboard/google/brya/variants/craask/memory/mem_parts_used.txt b/src/mainboard/google/brya/variants/craask/memory/mem_parts_used.txt
index b08faac3e7..f78ce4598a 100644
--- a/src/mainboard/google/brya/variants/craask/memory/mem_parts_used.txt
+++ b/src/mainboard/google/brya/variants/craask/memory/mem_parts_used.txt
@@ -15,3 +15,4 @@ H9JCNNNBK3MLYR-N6E
 K3LKLKL0EM-MGCN
 K3LKBKB0BM-MGCP
 H9JCNNNCP3MLYR-N6E
+H58G56CK8BX146

From f3c656b76a321c77bc1b639fd0be3accc17f3d43 Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Wed, 18 Mar 2026 15:36:25 +0000
Subject: [PATCH 3751/3886] soc/intel/common/block/smm: drain sync smi around
 smmstore

Drain pending SPI sync SMIs before dropping write protect for SMMSTORE and once more after the command runs. This keeps a stale sync status from leaking into the next request.

Change-Id: I7ba21719a6dafa926b0d5986a253da9cff52575a
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91726
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
---
 src/soc/intel/common/block/smm/smihandler.c | 17 ++++++++++++++++-
 1 file changed, 16 insertions(+), 1 deletion(-)

diff --git a/src/soc/intel/common/block/smm/smihandler.c b/src/soc/intel/common/block/smm/smihandler.c
index e0fa13e581..58c980672c 100644
--- a/src/soc/intel/common/block/smm/smihandler.c
+++ b/src/soc/intel/common/block/smm/smihandler.c
@@ -66,6 +66,20 @@ __weak void mainboard_smi_espi_handler(void)
 	/* no-op */
 }
 
+#define SMMSTORE_SYNC_SMI_SETTLE_USEC 50
+#define SMMSTORE_SYNC_SMI_CLEAR_TRIES 8
+
+static void smmstore_drain_sync_smi(void)
+{
+	int i;
+
+	for (i = 0; i < SMMSTORE_SYNC_SMI_CLEAR_TRIES; i++) {
+		if (!fast_spi_clear_sync_smi_status())
+			return;
+		udelay(SMMSTORE_SYNC_SMI_SETTLE_USEC);
+	}
+}
+
 /* Inherited from cpu/x86/smm.h resulting in a different signature */
 void southbridge_smi_set_eos(void)
 {
@@ -279,12 +293,13 @@ static void southbridge_smi_store(
 		 * bit is a must prior setting SPI_BIOS_CONTROL_WPD" bit
 		 * to avoid 3-strike error.
 		 */
-		fast_spi_clear_sync_smi_status();
+		smmstore_drain_sync_smi();
 		fast_spi_disable_wp();
 	}
 
 	/* drivers/smmstore/smi.c */
 	ret = smmstore_exec(sub_command, (void *)(uintptr_t)reg_ebx);
+	smmstore_drain_sync_smi();
 	save_state_ops->set_reg(RAX, node, &ret, sizeof(ret));
 
 	if (wp_enabled) {

From 493770d7300f8017e12f5ef6432a107502e03e95 Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Thu, 12 Mar 2026 20:30:39 +0000
Subject: [PATCH 3752/3886] mb/starlabs/starfighter/mtl: add speaker idle CFR
 option

Realtek advised leaving the StarFighter speaker path idle with GPIO2
low and LINE2 EAPD disabled when no audio is playing.

Add a "Legacy Speaker Control" CFR option for the Meteor Lake variant
so coreboot can optionally boot the codec in that muted state. This
avoids the cold-boot / G3 speaker pop when paired with the Linux
runtime sequencing fix that asserts EAPD and GPIO2 only for playback.

Keep the option enabled by default so existing kernels continue to use
the legacy speaker setup. Without the matching Linux change, forcing
GPIO2 low at boot would leave the external speaker amp disabled and
result in no speaker output.

Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I62427d3f13b8a68a58bca4ed7896482da4abf23b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91662
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/starlabs/common/hda/dmic.c      |  3 +-
 src/mainboard/starlabs/starfighter/cfr.c      | 22 ++++++++++++++
 .../starfighter/variants/mtl/Makefile.mk      |  1 +
 .../starlabs/starfighter/variants/mtl/hda.c   | 30 +++++++++++++++++++
 4 files changed, 55 insertions(+), 1 deletion(-)
 create mode 100644 src/mainboard/starlabs/starfighter/variants/mtl/hda.c

diff --git a/src/mainboard/starlabs/common/hda/dmic.c b/src/mainboard/starlabs/common/hda/dmic.c
index cf1b243866..bf09f8a5f9 100644
--- a/src/mainboard/starlabs/common/hda/dmic.c
+++ b/src/mainboard/starlabs/common/hda/dmic.c
@@ -14,8 +14,9 @@ static void disable_microphone(uint8_t *base)
 	azalia_program_verb_table(base, override_verb, ARRAY_SIZE(override_verb));
 }
 
-void mainboard_azalia_program_runtime_verbs(uint8_t *base, uint32_t viddid)
+void __weak mainboard_azalia_program_runtime_verbs(uint8_t *base, uint32_t viddid)
 {
+	(void)viddid;
 	if (get_uint_option("microphone", 1) == 0)
 		disable_microphone(base);
 }
diff --git a/src/mainboard/starlabs/starfighter/cfr.c b/src/mainboard/starlabs/starfighter/cfr.c
index 2d3c6c3967..9f8132be96 100644
--- a/src/mainboard/starlabs/starfighter/cfr.c
+++ b/src/mainboard/starlabs/starfighter/cfr.c
@@ -8,6 +8,25 @@
 #include <variants.h>
 #include <common/cfr.h>
 
+#if CONFIG(BOARD_STARLABS_STARFIGHTER_MTL)
+static const struct sm_object legacy_speaker_control = SM_DECLARE_BOOL({
+	.opt_name	= "legacy_speaker_control",
+	.ui_name	= "Legacy Speaker Control",
+	.ui_helptext	= "Enabled: keep the default speaker initialization.\n"
+			  "Disabled: boot with GPIO2 low and LINE2 EAPD off "
+			  "so the speakers start muted.",
+	.default_value	= true,
+});
+
+static struct sm_obj_form audio_group = {
+	.ui_name = "Audio",
+	.obj_list = (const struct sm_object *[]) {
+		&legacy_speaker_control,
+		NULL
+	},
+};
+#endif
+
 static struct sm_obj_form battery_group = {
 	.ui_name = "Battery",
 	.obj_list = (const struct sm_object *[]) {
@@ -128,6 +147,9 @@ static struct sm_obj_form wireless_group = {
 };
 
 static struct sm_obj_form *sm_root[] = {
+	#if CONFIG(BOARD_STARLABS_STARFIGHTER_MTL)
+	&audio_group,
+	#endif
 	&battery_group,
 	&debug_group,
 	#if CONFIG(DRIVERS_INTEL_USB4_RETIMER)
diff --git a/src/mainboard/starlabs/starfighter/variants/mtl/Makefile.mk b/src/mainboard/starlabs/starfighter/variants/mtl/Makefile.mk
index 93240a1307..19f5cb80ff 100644
--- a/src/mainboard/starlabs/starfighter/variants/mtl/Makefile.mk
+++ b/src/mainboard/starlabs/starfighter/variants/mtl/Makefile.mk
@@ -8,6 +8,7 @@ romstage-y += romstage.c
 ramstage-y += board_id.c
 ramstage-y += devtree.c
 ramstage-y += gpio.c
+ramstage-y += hda.c
 ramstage-y += hda_verb.c
 ramstage-y += ramstage.c
 $(call add_vbt_to_cbfs, vbt_qhd.bin, data_qhd.vbt)
diff --git a/src/mainboard/starlabs/starfighter/variants/mtl/hda.c b/src/mainboard/starlabs/starfighter/variants/mtl/hda.c
new file mode 100644
index 0000000000..29e9c26396
--- /dev/null
+++ b/src/mainboard/starlabs/starfighter/variants/mtl/hda.c
@@ -0,0 +1,30 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <device/azalia_codec/realtek.h>
+#include <device/azalia_device.h>
+#include <option.h>
+
+/* Leave the speaker path muted so the OS can sequence EAPD and GPIO2 later. */
+static const uint32_t speaker_idle_verb[] = {
+	AZALIA_VERB_12B(0, 0x01, 0x716, 0x04),
+	AZALIA_VERB_12B(0, 0x01, 0x717, 0x04),
+	AZALIA_VERB_12B(0, 0x01, 0x715, 0x00),
+	AZALIA_VERB_12B(0, ALC269_LINE2, 0x70c, 0x00),
+};
+
+static const uint32_t microphone_disable_verb[] = {
+	AZALIA_PIN_CFG(0, ALC269_DMIC12, AZALIA_PIN_CFG_NC(0)),
+};
+
+void mainboard_azalia_program_runtime_verbs(uint8_t *base, uint32_t viddid)
+{
+	(void)viddid;
+
+	if (get_uint_option("microphone", 1) == 0)
+		azalia_program_verb_table(base, microphone_disable_verb,
+					  ARRAY_SIZE(microphone_disable_verb));
+
+	if (get_uint_option("legacy_speaker_control", 1) == 0)
+		azalia_program_verb_table(base, speaker_idle_verb,
+					  ARRAY_SIZE(speaker_idle_verb));
+}

From 99d409d3ba348aeebeb02288b62c97cd8cb336ee Mon Sep 17 00:00:00 2001
From: Kapil Porwal <kapilporwal@google.com>
Date: Fri, 20 Feb 2026 12:16:26 +0530
Subject: [PATCH 3753/3886] arch/arm64: Add support for TTB relocation to DRAM

When transitioning between boot stages, it is often necessary to move
the Translation Table Base (TTB) from a temporary pre-RAM location
to a permanent post-RAM region.

ARM64 page tables contain absolute physical addresses for lower-level
tables. When moving the TTB from one base address to another, these
internal pointers must be adjusted.

Implement mmu_relocate_ttb() to handle this transition. The logic
copies the tables from _preram_ttb to _postram_ttb and performs a
fixup on all descriptors to reflect the new offset. This ensures
memory mapping remains consistent after the TTB base changes.

BUG=b:436391478
TEST=Verify successful TTB relocation and stable MMU state on Quartz.

Change-Id: I7fdd69bfa82fc3dae919693f4d5d0314687cbef9
Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91367
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
---
 src/arch/arm64/armv8/mmu.c              | 81 +++++++++++++++++++++++--
 src/arch/arm64/include/armv8/arch/mmu.h |  2 +
 2 files changed, 78 insertions(+), 5 deletions(-)

diff --git a/src/arch/arm64/armv8/mmu.c b/src/arch/arm64/armv8/mmu.c
index 65d0f92e5d..044dd0cfbe 100644
--- a/src/arch/arm64/armv8/mmu.c
+++ b/src/arch/arm64/armv8/mmu.c
@@ -76,16 +76,25 @@ static const char *table_level_name(size_t xlat_size)
 	}
 }
 
+static int init_next_free_table(void *start, void *end)
+{
+	if ((void *)next_free_table < start || (void *)next_free_table >= end)
+		next_free_table = start;
+	while (next_free_table[0] != UNUSED_DESC) {
+		next_free_table += GRANULE_SIZE / sizeof(*next_free_table);
+		if ((void *)next_free_table >= end)
+			return -1;
+	}
+	return 0;
+}
+
 /* Func : setup_new_table
  * Desc : Get next free table from TTB and set it up to match old parent entry.
  */
 static uint64_t *setup_new_table(uint64_t desc, size_t xlat_size)
 {
-	while (next_free_table[0] != UNUSED_DESC) {
-		next_free_table += GRANULE_SIZE/sizeof(*next_free_table);
-		if (_ettb - (u8 *)next_free_table <= 0)
-			die("Ran out of page table space!");
-	}
+	if (init_next_free_table(_ttb, _ettb))
+		die("Ran out of page table space!");
 
 	void *frame_base = (void *)(desc & XLAT_ADDR_MASK);
 	const char *level_name = table_level_name(xlat_size);
@@ -243,6 +252,7 @@ void mmu_config_range(void *start, size_t size, uint64_t tag)
 	print_tag(BIOS_INFO, tag);
 
 	sanity_check(base_addr, temp_size);
+	assert(raw_read_ttbr0() == (uint64_t)_ttb);
 
 	while (temp_size)
 		temp_size -= init_xlat_table(base_addr + (size - temp_size),
@@ -326,3 +336,64 @@ void mmu_enable(void)
 
 	isb();
 }
+
+/*
+ * Func : mmu_relocate_ttb
+ * Desc : Relocates a Translation Table Base (TTB) from _preram_ttb
+ * to _postram_ttb. This involves copying the table data and updating
+ * all internal pointers within the translation table entries to reflect
+ * the new location.
+ */
+void mmu_relocate_ttb(void)
+{
+	const uintptr_t old_base = (uintptr_t)_preram_ttb;
+	const uintptr_t new_base = (uintptr_t)_postram_ttb;
+	const uintptr_t offset = new_base - old_base;
+
+	ASSERT_MSG(offset, "TTB relocation is not required.\n");
+
+	/* Ensure that next_free_table pointer is correct. */
+	init_next_free_table(_preram_ttb, _epreram_ttb);
+
+	const size_t used_size = (uintptr_t)next_free_table - old_base;
+	uint64_t *entry;
+	uint64_t *end = (uint64_t *)(new_base + used_size);
+
+	printk(BIOS_INFO, "Relocating TTB: 0x%lx -> 0x%lx (offset 0x%lx)\n",
+		old_base, new_base, offset);
+
+	/* Copy the used TTB region to the new location. */
+	memcpy((void *)new_base, (void *)old_base, used_size);
+
+	/*
+	 * Update all internal table pointers. Since the entire TTB region is
+	 * moved as a single block, every table pointer inside the descriptors
+	 * needs to be adjusted by the same relative offset.
+	 */
+	for (entry = (uint64_t *)new_base; entry < end; entry++) {
+		/*
+		 * In ARMv8, a descriptor with bits [1:0] == 0b11 can be either a
+		 * Table descriptor or a Page descriptor. To differentiate, we
+		 * check the Access Flag (bit 10). Table descriptors do not use
+		 * this bit, whereas we ensure all Page/Block descriptors have it
+		 * set. This relies on TCR.HAFT[42] remaining 0.
+		 */
+		if ((*entry & DESC_MASK) == TABLE_DESC && !(*entry & BLOCK_ACCESS))
+			*entry += offset;
+	}
+
+	/* Mark remaining table slots unused (first PTE == UNUSED_DESC). */
+	for (entry = end; (u8 *)entry < _epostram_ttb; entry += GRANULE_SIZE / sizeof(*entry))
+		*entry = UNUSED_DESC;
+
+	/* Update TTBR0 to point to the new base address. */
+	dsb();
+	raw_write_ttbr0((uintptr_t)new_base);
+	isb();
+
+	tlb_invalidate_all();
+	dsb();
+	isb();
+
+	printk(BIOS_INFO, "TTB relocation is complete.\n");
+}
diff --git a/src/arch/arm64/include/armv8/arch/mmu.h b/src/arch/arm64/include/armv8/arch/mmu.h
index 0db6d3ff28..739aa5e0b6 100644
--- a/src/arch/arm64/include/armv8/arch/mmu.h
+++ b/src/arch/arm64/include/armv8/arch/mmu.h
@@ -152,5 +152,7 @@ void mmu_config_range(void *start, size_t size, uint64_t tag);
 void mmu_enable(void);
 /* Disable the MMU (which also disables dcache but not icache). */
 void mmu_disable(void);
+/* Relocates a Translation Table Base (TTB) from _preram_ttb to _postram_ttb */
+void mmu_relocate_ttb(void);
 
 #endif /* __ARCH_ARM64_MMU_H__ */

From 4b227a4aa68433ee0e25e4d1dd89376ed9b82ab4 Mon Sep 17 00:00:00 2001
From: Kapil Porwal <kapilporwal@google.com>
Date: Tue, 24 Feb 2026 13:28:19 +0530
Subject: [PATCH 3754/3886] arch/arm64: Add debug API to dump MMU page table
 configuration

To validate complex memory layouts and verify the success of TTB
relocations, it is necessary to inspect the active page tables.

Implement print_mmu_range() to perform a software table walk. The
utility decodes architectural attributes (cacheability, permissions,
etc.) and merges contiguous mappings with identical attributes for
a concise console summary. This is guarded by ARCH_ARM64_DEBUG_MMU.

BUG=b:436391478
TEST=Dump and verify MMU configuration on Google/Quartz.

Logs:
```
[INFO ]  Dumping MMU entries for range [0x0000000000000:0x1000000000000)
[INFO ]    Mapping [0x0000000000000:0x0000000001000) -> PTE: 0x0000000000000000 (UNMAPPED)
[INFO ]    Mapping [0x0000000001000:0x0000000200000) -> PTE: 0x0040000000001403 (PAGE)
[INFO ]    Attributes: Secure | Read-Write | Accessed | Execute-Never | Non-Shareable | Device NGNRNE
[INFO ]    Mapping [0x0000000200000:0x000000b000000) -> PTE: 0x0040000000200401 (BLOCK)
[INFO ]    Attributes: Secure | Read-Write | Accessed | Execute-Never | Non-Shareable | Device NGNRNE
[INFO ]    Mapping [0x000000b000000:0x000000b018000) -> PTE: 0x000000000b000713 (PAGE)
[INFO ]    Attributes: Secure | Read-Write | Accessed | Executable | Inner-Shareable | Normal Cacheable (WBWAC)
[INFO ]    Mapping [0x000000b018000:0x000000b0e0000) -> PTE: 0x004000000b018403 (PAGE)
[INFO ]    Attributes: Secure | Read-Write | Accessed | Execute-Never | Non-Shareable | Device NGNRNE
[INFO ]    Mapping [0x000000b0e0000:0x000000b0e8000) -> PTE: 0x000000000b0e0713 (PAGE)
[INFO ]    Attributes: Secure | Read-Write | Accessed | Executable | Inner-Shareable | Normal Cacheable (WBWAC)
[INFO ]    Mapping [0x000000b0e8000:0x000000b200000) -> PTE: 0x004000000b0e8403 (PAGE)
[INFO ]    Attributes: Secure | Read-Write | Accessed | Execute-Never | Non-Shareable | Device NGNRNE
[INFO ]    Mapping [0x000000b200000:0x0000014600000) -> PTE: 0x004000000b200401 (BLOCK)
[INFO ]    Attributes: Secure | Read-Write | Accessed | Execute-Never | Non-Shareable | Device NGNRNE
[INFO ]    Mapping [0x0000014600000:0x0000014680000) -> PTE: 0x0040000014600403 (PAGE)
[INFO ]    Attributes: Secure | Read-Write | Accessed | Execute-Never | Non-Shareable | Device NGNRNE
[INFO ]    Mapping [0x0000014680000:0x00000146ac000) -> PTE: 0x0000000014680713 (PAGE)
[INFO ]    Attributes: Secure | Read-Write | Accessed | Executable | Inner-Shareable | Normal Cacheable (WBWAC)
[INFO ]    Mapping [0x00000146ac000:0x0000014800000) -> PTE: 0x00400000146ac403 (PAGE)
[INFO ]    Attributes: Secure | Read-Write | Accessed | Execute-Never | Non-Shareable | Device NGNRNE
[INFO ]    Mapping [0x0000014800000:0x0000014858000) -> PTE: 0x0000000014800713 (PAGE)
[INFO ]    Attributes: Secure | Read-Write | Accessed | Executable | Inner-Shareable | Normal Cacheable (WBWAC)
[INFO ]    Mapping [0x0000014858000:0x000001485a000) -> PTE: 0x000000001485870f (PAGE)
[INFO ]    Attributes: Secure | Read-Write | Accessed | Executable | Inner-Shareable | Normal Non-Cacheable
[INFO ]    Mapping [0x000001485a000:0x0000014a80000) -> PTE: 0x000000001485a713 (PAGE)
[INFO ]    Attributes: Secure | Read-Write | Accessed | Executable | Inner-Shareable | Normal Cacheable (WBWAC)
[INFO ]    Mapping [0x0000014a80000:0x0000014c00000) -> PTE: 0x0040000014a80403 (PAGE)
[INFO ]    Attributes: Secure | Read-Write | Accessed | Execute-Never | Non-Shareable | Device NGNRNE
[INFO ]    Mapping [0x0000014c00000:0x0000024000000) -> PTE: 0x0040000014c00401 (BLOCK)
[INFO ]    Attributes: Secure | Read-Write | Accessed | Execute-Never | Non-Shareable | Device NGNRNE
[INFO ]    Mapping [0x0000024000000:0x0000024200000) -> PTE: 0x0040000024000403 (PAGE)
[INFO ]    Attributes: Secure | Read-Write | Accessed | Execute-Never | Non-Shareable | Device NGNRNE
[INFO ]    Mapping [0x0000024200000:0x0000080000000) -> PTE: 0x0040000024200401 (BLOCK)
[INFO ]    Attributes: Secure | Read-Write | Accessed | Execute-Never | Non-Shareable | Device NGNRNE
[INFO ]    Mapping [0x0000080000000:0x000008000c000) -> PTE: 0x0000000080000713 (PAGE)
[INFO ]    Attributes: Secure | Read-Write | Accessed | Executable | Inner-Shareable | Normal Cacheable (WBWAC)
[INFO ]    Mapping [0x000008000c000:0x0000080010000) -> PTE: 0x000000008000c70f (PAGE)
[INFO ]    Attributes: Secure | Read-Write | Accessed | Executable | Inner-Shareable | Normal Non-Cacheable
[INFO ]    Mapping [0x0000080010000:0x0000080200000) -> PTE: 0x0000000080010713 (PAGE)
[INFO ]    Attributes: Secure | Read-Write | Accessed | Executable | Inner-Shareable | Normal Cacheable (WBWAC)
[INFO ]    Mapping [0x0000080200000:0x0000081c00000) -> PTE: 0x0000000080200711 (BLOCK)
[INFO ]    Attributes: Secure | Read-Write | Accessed | Executable | Inner-Shareable | Normal Cacheable (WBWAC)
[INFO ]    Mapping [0x0000081c00000:0x0000081c60000) -> PTE: 0x0000000081c00713 (PAGE)
[INFO ]    Attributes: Secure | Read-Write | Accessed | Executable | Inner-Shareable | Normal Cacheable (WBWAC)
[INFO ]    Mapping [0x0000081c60000:0x0000081c80000) -> PTE: 0x0000000081c6070f (PAGE)
[INFO ]    Attributes: Secure | Read-Write | Accessed | Executable | Inner-Shareable | Normal Non-Cacheable
[INFO ]    Mapping [0x0000081c80000:0x0000081e00000) -> PTE: 0x0000000081c80713 (PAGE)
[INFO ]    Attributes: Secure | Read-Write | Accessed | Executable | Inner-Shareable | Normal Cacheable (WBWAC)
[INFO ]    Mapping [0x0000081e00000:0x00000e0800000) -> PTE: 0x0000000081e00711 (BLOCK)
[INFO ]    Attributes: Secure | Read-Write | Accessed | Executable | Inner-Shareable | Normal Cacheable (WBWAC)
[INFO ]    Mapping [0x00000e0800000:0x00000e2800000) -> PTE: 0x00000000e080070d (BLOCK)
[INFO ]    Attributes: Secure | Read-Write | Accessed | Executable | Inner-Shareable | Normal Non-Cacheable
[INFO ]    Mapping [0x00000e2800000:0x0000100000000) -> PTE: 0x00000000e2800711 (BLOCK)
[INFO ]    Attributes: Secure | Read-Write | Accessed | Executable | Inner-Shareable | Normal Cacheable (WBWAC)
[INFO ]    Mapping [0x0000100000000:0x0000880000000) -> PTE: 0x0000000000000000 (UNMAPPED)
[INFO ]    Mapping [0x0000880000000:0x0001000000000) -> PTE: 0x0000000880000711 (BLOCK)
[INFO ]    Attributes: Secure | Read-Write | Accessed | Executable | Inner-Shareable | Normal Cacheable (WBWAC)
[INFO ]    Mapping [0x0001000000000:0x1000000000000) -> PTE: 0x0000000000000000 (UNMAPPED)
```

Change-Id: I0e21e4db463b66e006dcbe85ed9415264bf18acd
Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91408
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/arch/arm64/armv8/Kconfig            |  11 ++
 src/arch/arm64/armv8/mmu.c              | 168 ++++++++++++++++++++++++
 src/arch/arm64/include/armv8/arch/mmu.h |   1 +
 3 files changed, 180 insertions(+)

diff --git a/src/arch/arm64/armv8/Kconfig b/src/arch/arm64/armv8/Kconfig
index f53c16d156..d25ec14914 100644
--- a/src/arch/arm64/armv8/Kconfig
+++ b/src/arch/arm64/armv8/Kconfig
@@ -30,4 +30,15 @@ config ARCH_ARMV8_EXTENSION
 	  need to be changed unless specific features (e.g. new instructions)
 	  are used by the SoC's coreboot code.
 
+config ARCH_ARM64_DEBUG_MMU
+	bool "Debug MMU table"
+	default n
+	help
+	  When enabled, the MMU table walker will dump the translation
+	  table entries and their attributes to the debug console during
+	  initialization or range configuration.
+
+	  This is useful for verifying that memory ranges (Normal, Device,
+	  Read-Only, etc.) are being mapped correctly in the page tables.
+
 endif # ARCH_ARM64
diff --git a/src/arch/arm64/armv8/mmu.c b/src/arch/arm64/armv8/mmu.c
index 044dd0cfbe..c30fd5789a 100644
--- a/src/arch/arm64/armv8/mmu.c
+++ b/src/arch/arm64/armv8/mmu.c
@@ -236,6 +236,171 @@ static void assert_correct_ttb_mapping(void *addr)
 	       == BLOCK_INDEX_MEM_NORMAL && !(pte & BLOCK_NS));
 }
 
+
+/* Decodes and prints the architectural attributes of a PTE. */
+static void print_pte_attributes(uint64_t pte)
+{
+	/* Invalid/Unused entries */
+	if (pte == 0 || (pte & DESC_MASK) == INVALID_DESC)
+		return;
+
+	printk(BIOS_INFO, "  Attributes: ");
+	printk(BIOS_INFO, (pte & BLOCK_NS) ? "Non-Secure | " : "Secure | ");
+	printk(BIOS_INFO, (pte & BLOCK_AP_RO) ? "Read-Only | " : "Read-Write | ");
+	printk(BIOS_INFO, (pte & BLOCK_ACCESS) ? "Accessed | " : "Not Accessed | ");
+	printk(BIOS_INFO, (pte & BLOCK_XN) ? "Execute-Never | " : "Executable | ");
+
+	uint64_t sh = pte & BLOCK_SH_MASK;
+	switch (sh) {
+	case BLOCK_SH_NON_SHAREABLE:
+		printk(BIOS_INFO, "Non-Shareable | ");
+		break;
+	case BLOCK_SH_UNPREDICTABLE:
+		printk(BIOS_INFO, "Unpredictable Shareability | ");
+		break;
+	case BLOCK_SH_OUTER_SHAREABLE:
+		printk(BIOS_INFO, "Outer-Shareable | ");
+		break;
+	case BLOCK_SH_INNER_SHAREABLE:
+		printk(BIOS_INFO, "Inner-Shareable | ");
+		break;
+	default:
+		printk(BIOS_INFO, "Unknown Shareability (0x%llx) | ", sh);
+		break;
+	}
+
+	uint64_t index = (pte >> BLOCK_INDEX_SHIFT) & BLOCK_INDEX_MASK;
+	switch (index) {
+	case BLOCK_INDEX_MEM_DEV_NGNRNE:
+		printk(BIOS_INFO, "Device NGNRNE");
+		break;
+	case BLOCK_INDEX_MEM_DEV_NGNRE:
+		printk(BIOS_INFO, "Device NGNRE");
+		break;
+	case BLOCK_INDEX_MEM_DEV_GRE:
+		printk(BIOS_INFO, "Device GRE");
+		break;
+	case BLOCK_INDEX_MEM_NORMAL_NC:
+		printk(BIOS_INFO, "Normal Non-Cacheable");
+		break;
+	case BLOCK_INDEX_MEM_NORMAL:
+		printk(BIOS_INFO, "Normal Cacheable (WBWAC)");
+		break;
+	default:
+		printk(BIOS_INFO, "Unknown Memory Type Index (%llu)", index);
+		break;
+	}
+	printk(BIOS_INFO, "\n");
+}
+
+/* Structure to hold the state of the last printed range */
+struct last_mmu_entry {
+	uint64_t start;
+	uint64_t end;
+	uint64_t pte;
+	const char *desc_type;
+	bool valid;
+};
+
+/* Function to print the accumulated range and reset the state */
+static void print_and_reset_last_range(struct last_mmu_entry *last)
+{
+	if (last->valid) {
+		printk(BIOS_INFO, "  Mapping [" ADDR_FMT ":" ADDR_FMT ") -> PTE: 0x%016llx (%s)\n",
+			  (uintptr_t)last->start, (uintptr_t)last->end, last->pte, last->desc_type);
+		print_pte_attributes(last->pte);
+		last->valid = false;
+	}
+}
+
+/*
+ * Prints the MMU entries for a given address range, merging contiguous
+ * mappings with identical attributes.
+ */
+static void print_mmu_range(uint64_t base_addr, size_t size)
+{
+	if (!CONFIG(ARCH_ARM64_DEBUG_MMU))
+		return;
+
+	uint64_t current_addr = base_addr;
+	uint64_t end_addr = base_addr + size;
+
+	printk(BIOS_INFO, "Dumping MMU entries for range [" ADDR_FMT ":" ADDR_FMT ")\n",
+		(uintptr_t)base_addr, (uintptr_t)end_addr);
+
+	struct last_mmu_entry last = { .valid = false };
+
+	while (current_addr < end_addr) {
+		int shift = L0_ADDR_SHIFT;
+		uint64_t *pte_ptr = (uint64_t *)_ttb;
+		uint64_t pte = 0;
+		uint64_t mapped_size = 0;
+		const char *desc_type = "UNKNOWN";
+
+		/* Perform a table walk to find the terminal PTE and its size. */
+		while (shift >= L3_ADDR_SHIFT) {
+			int index = (current_addr >> shift) & ((1UL << BITS_RESOLVED_PER_LVL) - 1);
+			pte = pte_ptr[index];
+
+			if (pte == 0) {
+				desc_type = "UNMAPPED";
+				mapped_size = 1UL << shift;
+				break;
+			} else if ((pte & DESC_MASK) == TABLE_DESC) {
+				if (shift == L3_ADDR_SHIFT) {
+					/* At L3, TABLE_DESC (0x3) is actually PAGE_DESC */
+					desc_type = "PAGE";
+					mapped_size = GRANULE_SIZE;
+					break;
+				} else {
+					/* At L0, L1, L2, it means TABLE_DESC, continue walk */
+					pte_ptr = (uint64_t *)(pte & XLAT_ADDR_MASK);
+					shift -= BITS_RESOLVED_PER_LVL;
+				}
+			} else if ((pte & DESC_MASK) == BLOCK_DESC) {
+				desc_type = "BLOCK";
+				mapped_size = 1UL << shift;
+				break;
+			} else {
+				desc_type = "IMPOSSIBLE";
+				mapped_size = 1UL << shift;
+				printk(BIOS_ERR, "Unexpected descriptor (PTE: 0x%016llx) found!\n", pte);
+				break;
+			}
+		}
+
+		/* Align the start address to the beginning of the mapped block/page. */
+		uint64_t start_of_mapping = ALIGN_DOWN(current_addr, mapped_size);
+		uint64_t current_print_end = start_of_mapping + mapped_size;
+
+		if (last.valid && start_of_mapping == last.end &&
+			(pte & ~XLAT_ADDR_MASK) == (last.pte & ~XLAT_ADDR_MASK)) {
+			/* Extend the last range */
+			last.end = current_print_end;
+		} else {
+			/* Print the previous range */
+			print_and_reset_last_range(&last);
+			/* Start a new range */
+			last.start = start_of_mapping;
+			last.end = current_print_end;
+			last.pte = pte;
+			last.desc_type = desc_type;
+			last.valid = true;
+		}
+
+		/* Advance current_addr */
+		current_addr = start_of_mapping + mapped_size;
+		if (current_addr <= start_of_mapping) {
+			printk(BIOS_ERR, "Address overflow in %s!\n", __func__);
+			break;
+		}
+	}
+
+	/* Print the very last accumulated range */
+	print_and_reset_last_range(&last);
+	printk(BIOS_INFO, "\n");
+}
+
 /* Func : mmu_config_range
  * Desc : This function repeatedly calls init_xlat_table with the base
  * address. Based on size returned from init_xlat_table, base_addr is updated
@@ -263,6 +428,8 @@ void mmu_config_range(void *start, size_t size, uint64_t tag)
 	tlbiall();
 	dsb();
 	isb();
+
+	print_mmu_range(0, 1UL << BITS_PER_VA);
 }
 
 /* Func : mmu_init
@@ -396,4 +563,5 @@ void mmu_relocate_ttb(void)
 	isb();
 
 	printk(BIOS_INFO, "TTB relocation is complete.\n");
+	print_mmu_range(0, 1UL << BITS_PER_VA);
 }
diff --git a/src/arch/arm64/include/armv8/arch/mmu.h b/src/arch/arm64/include/armv8/arch/mmu.h
index 739aa5e0b6..c2c4bad19f 100644
--- a/src/arch/arm64/include/armv8/arch/mmu.h
+++ b/src/arch/arm64/include/armv8/arch/mmu.h
@@ -42,6 +42,7 @@
 
 #define BLOCK_XN                   (1UL << 54)
 
+#define BLOCK_SH_MASK                  (0x3 << BLOCK_SH_SHIFT)
 #define BLOCK_SH_SHIFT                 (8)
 #define BLOCK_SH_NON_SHAREABLE         (0 << BLOCK_SH_SHIFT)
 #define BLOCK_SH_UNPREDICTABLE         (1 << BLOCK_SH_SHIFT)

From 8a90e46346f13e8c9eba8101e935b3d4c40f6281 Mon Sep 17 00:00:00 2001
From: Subrata Banik <subratabanik@google.com>
Date: Tue, 17 Mar 2026 11:53:19 +0530
Subject: [PATCH 3755/3886] soc/qualcomm/x1p42100: Increase CBFS_MCACHE size to
 22K

Expand CBFS_MCACHE from 16K to 22K to provide more space for
metadata caching. To accommodate this, shift FMAP_CACHE from
0x14860400 to 0x14861800.

Updated the memory map diagram in memlayout.ld to reflect the
new base address for the FMAP_CACHE region.

TEST=No CBFS related error seen while booting google/quartz.

w/o patch:

```
[ERROR]  CBFS ERROR: mcache overflow, should increase CBFS_MCACHE size!
```

Change-Id: Ic3268c72a4755bd15c6811688eb330c7d753c5ac
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91698
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/soc/qualcomm/x1p42100/memlayout.ld | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/src/soc/qualcomm/x1p42100/memlayout.ld b/src/soc/qualcomm/x1p42100/memlayout.ld
index 2c06eccd24..20dc57dc53 100644
--- a/src/soc/qualcomm/x1p42100/memlayout.ld
+++ b/src/soc/qualcomm/x1p42100/memlayout.ld
@@ -132,7 +132,7 @@
  *               |                ... Usable memory ...                     |      |
  * 0x14860C00    +----------------------------------------------------------+      |
  *               |                     FMAP_CACHE                           |      |
- * 0x14860000    +----------------------------------------------------------+    BSRAM
+ * 0x14861800    +----------------------------------------------------------+    BSRAM
  *               |                    CBFS_MCACHE                           |      |
  * 0x1485C000    +----------------------------------------------------------+      |
  *               |                  qclib_serial_log                        |      |
@@ -217,8 +217,8 @@ SECTIONS
 	VBOOT2_WORK(0x14854000, 12K)
 	PRERAM_DMA_COHERENT(0x14858000, 8K)
 	REGION(qclib_serial_log, 0x1485B000, 4K, 4K)
-	CBFS_MCACHE(0x1485C000,16K)
-	FMAP_CACHE(0x14860400, 2K)
+	CBFS_MCACHE(0x1485C000,22K)
+	FMAP_CACHE(0x14861800, 2K)
 	REGION(dcb, 0x14862000, 56K, 4K)
 	REGION(dtb, 0x14870000, 32K, 4K)
 	REGION(ddr_training, 0x14878000, 64K, 4K)

From f1baed6f7983ce6f748bbce6e1b9686be5df50f4 Mon Sep 17 00:00:00 2001
From: Subrata Banik <subratabanik@google.com>
Date: Wed, 18 Mar 2026 13:49:32 +0530
Subject: [PATCH 3756/3886] soc/qualcomm/common: Implement asynchronous PCIe
 initialization

Introduce SOC_QUALCOMM_PCIE_ASYNCHRONOUS_INIT to allow the PCIe
link training to proceed without blocking the boot flow.

Refactor qcom_setup_pcie_host into two logical phases:
1. Initiate: Power on endpoints and trigger LTSSM (Romstage).
2. Verify: Wait for link-up status (Ramstage).

When the async Kconfig is enabled, the initiation happens in
romstage, but the blocking 'wait_link_up' call is deferred to
ramstage. This allows other SoC and mainboard initializations to
run in between the hardware link training, reducing overall boot time.

BUG=b:449871690
TEST=Verified PCIe link still enumerates correctly on Bluey with
asynchronous init enabled.

Change-Id: Idf368731325b5efcf4db0d1912a8c75417ef11ab
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91723
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/soc/qualcomm/common/Kconfig       | 10 +++++
 src/soc/qualcomm/common/pcie_common.c | 57 ++++++++++++++++++++++++++-
 2 files changed, 65 insertions(+), 2 deletions(-)

diff --git a/src/soc/qualcomm/common/Kconfig b/src/soc/qualcomm/common/Kconfig
index 373ba51c40..a572234cf6 100644
--- a/src/soc/qualcomm/common/Kconfig
+++ b/src/soc/qualcomm/common/Kconfig
@@ -61,4 +61,14 @@ config SOC_QUALCOMM_DEBUG_TSENS
 	  When enabled, a call to monitor TSENS will dump the sensor data on
 	  the debug console.
 
+config SOC_QUALCOMM_PCIE_ASYNCHRONOUS_INIT
+	bool
+	default n
+	help
+	  When enabled, qcom_setup_pcie_host will initiate the PCIe
+	  hardware power-up sequence but will not block the boot flow
+	  to wait for the link-up status. This can reduce overall
+	  boot time, but requires late-stage drivers to verify link
+	  readiness before access.
+
 endif
diff --git a/src/soc/qualcomm/common/pcie_common.c b/src/soc/qualcomm/common/pcie_common.c
index ab8af642d1..7485fe55cc 100644
--- a/src/soc/qualcomm/common/pcie_common.c
+++ b/src/soc/qualcomm/common/pcie_common.c
@@ -178,6 +178,9 @@ static enum cb_err qcom_pcie_dw_link_up(struct qcom_pcie_cntlr_t *pcie)
 	/* enable link training */
 	setbits32(pcie->cntlr_cfg->parf + PCIE_PARF_LTSSM, LTSSM_EN);
 
+	if (CONFIG(SOC_QUALCOMM_PCIE_ASYNCHRONOUS_INIT))
+		return CB_SUCCESS;
+
 	/* Check that link was established */
 	if (wait_link_up(pcie)) {
 		printk(BIOS_INFO, "PCIe link is up\n");
@@ -562,8 +565,7 @@ void qcom_pci_domain_read_resources(struct device *dev)
 	res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
 }
 
-/* PCI domain ops enable callback */
-void qcom_setup_pcie_host(struct device *dev)
+static enum cb_err pcie_initiate_link(void)
 {
 	gcom_pcie_get_config(&qcom_pcie_cfg);
 
@@ -576,6 +578,57 @@ void qcom_setup_pcie_host(struct device *dev)
 	qcom_pcie_configure_gpios(qcom_pcie_cfg.cntlr_cfg);
 
 	if (!qcom_dw_pcie_enable(&qcom_pcie_cfg))
+		return CB_SUCCESS;
+	else
+		return CB_ERR;
+}
+
+static enum cb_err pcie_verify_link_status(void)
+{
+	gcom_pcie_get_config(&qcom_pcie_cfg);
+
+	if (is_pcie_link_up(&qcom_pcie_cfg)) {
+		printk(BIOS_INFO, "PCIe Link is already up\n");
+		return CB_SUCCESS;
+	}
+
+	/* Check that link was established */
+	if (wait_link_up(&qcom_pcie_cfg)) {
+		printk(BIOS_INFO, "PCIe link is up\n");
+		return CB_SUCCESS;
+	}
+
+	/*
+	 * Link can be established in Gen 1 as it failed to establish in Gen2.
+	 * So allow some time to do it.
+	 */
+	udelay(100);
+
+	return is_pcie_link_up(&qcom_pcie_cfg) ? CB_SUCCESS : CB_ERR;
+}
+
+/* PCI domain ops enable callback */
+void qcom_setup_pcie_host(struct device *dev)
+{
+	/* STAGE 1: Initiate Hardware (Sync or Async)
+	 * In Romstage (or if Async is disabled), we always start the hardware.
+	 */
+	if (ENV_SEPARATE_ROMSTAGE || !CONFIG(SOC_QUALCOMM_PCIE_ASYNCHRONOUS_INIT)) {
+		if (pcie_initiate_link() != CB_SUCCESS) {
+			printk(BIOS_EMERG, "Failed to enable PCIe\n");
+			return;
+		}
+
+		/* Async in Romstage */
+		if (ENV_SEPARATE_ROMSTAGE)
+			return;
+	}
+
+	/* STAGE 2: Late Check (Async only)
+	 * If we are in Ramstage and Async is enabled, the hardware was already
+	 * kicked off in Romstage. Now we just verify the result.
+	 */
+	if (pcie_verify_link_status() == CB_SUCCESS)
 		printk(BIOS_NOTICE, "PCIe enumerated succussfully..\n");
 	else
 		printk(BIOS_EMERG, "Failed to enable PCIe\n");

From f56a936c5441b381a3cbb09ffdef0aa8cef727b0 Mon Sep 17 00:00:00 2001
From: Subrata Banik <subratabanik@google.com>
Date: Wed, 18 Mar 2026 13:58:06 +0530
Subject: [PATCH 3757/3886] soc/qualcomm/x1p42100: Allow asynchronous PCIe
 initialization

To support this early hardware initiation, add pcie_common.c and
soc-specific pcie.c to the romstage build when
SOC_QUALCOMM_PCIE_ASYNCHRONOUS_INIT and PCI Kconfigs are enabled.

This allows the SoC to kick off link training in romstage
and verify the link status later in ramstage.

BUG=b:449871690
TEST=Able to build and boot google/quenbih.

Change-Id: I6f81b88b36f51b55cb47846f9e81d0be8f987825
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91724
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
---
 src/soc/qualcomm/x1p42100/Makefile.mk | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/src/soc/qualcomm/x1p42100/Makefile.mk b/src/soc/qualcomm/x1p42100/Makefile.mk
index 77412e4cd0..117b8e1e4d 100644
--- a/src/soc/qualcomm/x1p42100/Makefile.mk
+++ b/src/soc/qualcomm/x1p42100/Makefile.mk
@@ -38,6 +38,10 @@ romstage-y += ../common/aop_load_reset.c
 romstage-$(CONFIG_DRIVERS_UART) += ../common/qupv3_uart.c
 romstage-y += ../common/spmi.c
 romstage-y += pmic.c
+ifeq ($(CONFIG_SOC_QUALCOMM_PCIE_ASYNCHRONOUS_INIT),y)
+romstage-$(CONFIG_PCI) += ../common/pcie_common.c
+romstage-$(CONFIG_PCI) += pcie.c
+endif
 
 ################################################################################
 ramstage-y += soc.c

From 1f2ea3c13e485bb0c0d6f0d799c33264b171677b Mon Sep 17 00:00:00 2001
From: Subrata Banik <subratabanik@google.com>
Date: Wed, 18 Mar 2026 14:00:48 +0530
Subject: [PATCH 3758/3886] mb/google/bluey: Initiate PCIe link training in
 romstage

Select SOC_QUALCOMM_PCIE_ASYNCHRONOUS_INIT for the Bluey board to allow
non-blocking PCIe link training.

Call qcom_setup_pcie_host() during platform_romstage_postram() when
performing a normal boot.

This takes advantage of the asynchronous PCIe initialization logic,
starting the link training early to save approximately 100ms of
blocking wait time in ramstage.

BUG=b:449871690
TEST=Able to save 100ms of the boot time (google/quenbih).

w/o patch:

```
5000:<unknown>         1,224,619 (662)
5001:<unknown>         1,324,851 (100,232)
```

w/ patch:

```
5000:<unknown>         1,098,810 (808)
5001:<unknown>         1,098,928 (118)
```

Change-Id: If758c2fb8f7a6a5bb8c5fe6c1d7b44e988858179
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91725
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
---
 src/mainboard/google/bluey/Kconfig    | 1 +
 src/mainboard/google/bluey/romstage.c | 5 +++++
 2 files changed, 6 insertions(+)

diff --git a/src/mainboard/google/bluey/Kconfig b/src/mainboard/google/bluey/Kconfig
index 47c81e6e74..6a2d3bfbab 100644
--- a/src/mainboard/google/bluey/Kconfig
+++ b/src/mainboard/google/bluey/Kconfig
@@ -6,6 +6,7 @@ config BOARD_GOOGLE_BLUEY_COMMON
 	# FIXME: keep ADB for development phase
 	select GBB_FLAG_ENABLE_ADB if VBOOT
 	select MAINBOARD_HAS_CHROMEOS
+	select SOC_QUALCOMM_PCIE_ASYNCHRONOUS_INIT
 	select SPI_FLASH
 	select SPI_FLASH_FORCE_4_BYTE_ADDR_MODE
 	select SPI_FLASH_INCLUDE_ALL_DRIVERS
diff --git a/src/mainboard/google/bluey/romstage.c b/src/mainboard/google/bluey/romstage.c
index 891809f045..042e69b9f0 100644
--- a/src/mainboard/google/bluey/romstage.c
+++ b/src/mainboard/google/bluey/romstage.c
@@ -10,6 +10,7 @@
 #include <gpio.h>
 #include <security/vboot/vboot_common.h>
 #include <soc/aop_common.h>
+#include <soc/pcie.h>
 #include <soc/pmic.h>
 #include <soc/qclib_common.h>
 #include <soc/shrm.h>
@@ -188,4 +189,8 @@ void platform_romstage_postram(void)
 		*boot_mode_ptr = boot_mode;
 		printk(BIOS_INFO, "Boot mode is %d\n", *boot_mode_ptr);
 	}
+
+	/* Perform PCIe setup early in async mode if supported to save 100ms */
+	if (boot_mode == LB_BOOT_MODE_NORMAL)
+		qcom_setup_pcie_host(NULL);
 }

From b00bfdd1e0e4bfd17eba8f6ad1f0aa40d1a66281 Mon Sep 17 00:00:00 2001
From: Subrata Banik <subratabanik@google.com>
Date: Tue, 17 Mar 2026 20:37:52 +0530
Subject: [PATCH 3759/3886] mb/google/bluey: Refactor SE firmware loading into
 early/late stages

Split the Qualcomm QUPV3 SE and GPI firmware loading into two helper
functions: load_qc_se_firmware_early() and load_qc_se_firmware_late().

- Early stage: Loads firmware for the ADSP I2C (Charger/Fuel gauge)
  and GPI instances. This is now called via mainboard_init.
  Off-mode charging is now part of the early stage operation.
- Late stage: Loads firmware for UART, USB-A retimers, and
  Fingerprint SPI. This is now called via mainboard_enable.

This restructure utilizes the chip_operations .init callback to ensure
critical charging-related operation is loaded before subsequent
initialization steps.

Change-Id: I54d41e76b162f80a80117bfe54943dc43b360dae
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91718
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
---
 src/mainboard/google/bluey/mainboard.c | 40 +++++++++++++++-----------
 1 file changed, 24 insertions(+), 16 deletions(-)

diff --git a/src/mainboard/google/bluey/mainboard.c b/src/mainboard/google/bluey/mainboard.c
index 891967f3e3..8b3fb9d6b6 100644
--- a/src/mainboard/google/bluey/mainboard.c
+++ b/src/mainboard/google/bluey/mainboard.c
@@ -201,7 +201,17 @@ static void handle_low_power_charging_boot(void)
 	launch_charger_applet();
 }
 
-static void mainboard_init(struct device *dev)
+static void load_qc_se_firmware_early(void)
+{
+	/* ADSP I2C (Charger/Fuel gauge) */
+	qupv3_se_fw_load_and_init(QUPV3_2_SE4, SE_PROTOCOL_I2C, MIXED);
+
+	gpi_firmware_load(QUP_0_GSI_BASE);
+	gpi_firmware_load(QUP_1_GSI_BASE);
+	gpi_firmware_load(QUP_2_GSI_BASE);
+}
+
+static void mainboard_init(void *chip_info)
 {
 	configure_parallel_charging();
 	configure_debug_access_port();
@@ -215,12 +225,7 @@ static void mainboard_init(struct device *dev)
 	if (get_boot_mode() == LB_BOOT_MODE_LOW_BATTERY)
 		trigger_critical_battery_shutdown();
 
-	/* ADSP I2C (Charger/Fuel gauge) */
-	qupv3_se_fw_load_and_init(QUPV3_2_SE4, SE_PROTOCOL_I2C, MIXED);
-
-	gpi_firmware_load(QUP_0_GSI_BASE);
-	gpi_firmware_load(QUP_1_GSI_BASE);
-	gpi_firmware_load(QUP_2_GSI_BASE);
+	load_qc_se_firmware_early();
 
 	configure_parallel_charging_late();
 
@@ -229,7 +234,10 @@ static void mainboard_init(struct device *dev)
 		handle_low_power_charging_boot();
 		halt();
 	}
+}
 
+static void load_qc_se_firmware_late(void)
+{
 	/*
 	 * Load console UART QUP firmware.
 	 * This is required even if coreboot's serial output is disabled.
@@ -251,18 +259,22 @@ static void mainboard_init(struct device *dev)
 
 	if (!CONFIG(MAINBOARD_NO_USB_A_PORT))
 		qupv3_se_fw_load_and_init(QUPV3_0_SE1, SE_PROTOCOL_I2C, MIXED); /* USB-A retimer */
+
 	qupv3_se_fw_load_and_init(QUPV3_0_SE5, SE_PROTOCOL_I2C, MIXED); /* eUSB repeater */
+
 	if (CONFIG(MAINBOARD_HAS_FINGERPRINT_VIA_SPI))
 		qupv3_se_fw_load_and_init(QUPV3_2_SE2, SE_PROTOCOL_SPI, MIXED); /* Fingerprint SPI */
+}
+
+static void mainboard_enable(struct device *dev)
+{
+	load_qc_se_firmware_late();
 
 	/* Enable touchpad power */
 	if (CONFIG_MAINBOARD_GPIO_PIN_FOR_TOUCHPAD_POWER)
 		gpio_output(GPIO_TP_POWER_EN, 1);
 
-	/*
-	 * Deassert FPMCU reset. Power applied in romstage
-	 * has now stabilized.
-	 */
+	/* Deassert FPMCU reset. Power applied in romstage has now stabilized. */
 	if (CONFIG(MAINBOARD_HAS_FINGERPRINT))
 		gpio_output(GPIO_FP_RST_L, 1);
 
@@ -273,11 +285,7 @@ static void mainboard_init(struct device *dev)
 	setup_audio();
 }
 
-static void mainboard_enable(struct device *dev)
-{
-	dev->ops->init = &mainboard_init;
-}
-
 struct chip_operations mainboard_ops = {
 	.enable_dev = mainboard_enable,
+	.init = mainboard_init,
 };

From 34f67580b53bd5b2baedf3aaa1e9d2c7527ab9b9 Mon Sep 17 00:00:00 2001
From: Subrata Banik <subratabanik@google.com>
Date: Thu, 19 Mar 2026 19:02:45 +0000
Subject: [PATCH 3760/3886] ec/google/chromeec: Add API to check for RTC host
 event

Add `google_chromeec_is_rtc_event()` to allow the AP to check if the
EC has posted an `EC_HOST_EVENT_RTC`. This is useful for identifying
wake-up or boot reasons triggered by the real-time clock.

BUG=b:493760057
BRANCH=none
TEST=Build and boot on a board using ChromeEC; verify the API
correctly detects RTC events.

Change-Id: Id62cb6942a5881932eec420c78389e9d78b1e7a9
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91763
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
---
 src/ec/google/chromeec/ec.c | 8 ++++++++
 src/ec/google/chromeec/ec.h | 8 ++++++++
 2 files changed, 16 insertions(+)

diff --git a/src/ec/google/chromeec/ec.c b/src/ec/google/chromeec/ec.c
index 5b89dac265..688d0f5140 100644
--- a/src/ec/google/chromeec/ec.c
+++ b/src/ec/google/chromeec/ec.c
@@ -1186,6 +1186,14 @@ bool google_chromeec_is_charger_present(void)
 		  EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_CONNECTED));
 }
 
+/* This API checks if RTC event. */
+bool google_chromeec_is_rtc_event(void)
+{
+	/* Check if the Chrome EC has an active RTC event. */
+	return !!(google_chromeec_get_events_b() &
+		  EC_HOST_EVENT_MASK(EC_HOST_EVENT_RTC));
+}
+
 /*
  * Using below scenarios to conclude if device has a barrel charger attached.
  * +-----------+-----------------+------------------+---------------------------------+
diff --git a/src/ec/google/chromeec/ec.h b/src/ec/google/chromeec/ec.h
index aadd51ff22..787b05b6cd 100644
--- a/src/ec/google/chromeec/ec.h
+++ b/src/ec/google/chromeec/ec.h
@@ -158,6 +158,14 @@ bool google_chromeec_is_usb_pd_attached(void);
  */
 bool google_chromeec_is_charger_present(void);
 
+/**
+ * Check if the Chrome EC has an active RTC event.
+ *
+ * @return		true: if the RTC event is present
+ *			false: if the RTC event is not present
+ */
+bool google_chromeec_is_rtc_event(void);
+
 /**
  * Check if barrel charger is present.
  *

From 941597e52feb498bb57d9327ccf546f862742b06 Mon Sep 17 00:00:00 2001
From: Subrata Banik <subratabanik@google.com>
Date: Thu, 19 Mar 2026 19:04:00 +0000
Subject: [PATCH 3761/3886] {commonlib, libpayload}: Add RTC_WAKE to
 boot_mode_t

Define CB_BOOT_MODE_RTC_WAKE and LB_BOOT_MODE_RTC_WAKE in the
coreboot table headers. This allows the firmware to communicate
to the payload (such as depthcharge) that the device started
up due to a Real-Time Clock alarm.

Synchronize the change across:
- payloads/libpayload/include/coreboot_tables.h
- src/commonlib/include/commonlib/coreboot_tables.h

BUG=b:493760057
BRANCH=none
TEST=Build coreboot and libpayload. Verify that the new boot mode
is accessible in the payload.

Change-Id: I8f5e118e6965f29498ab5bb46e153bc6d24bc116
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91764
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 payloads/libpayload/include/coreboot_tables.h     | 2 ++
 src/commonlib/include/commonlib/coreboot_tables.h | 2 ++
 2 files changed, 4 insertions(+)

diff --git a/payloads/libpayload/include/coreboot_tables.h b/payloads/libpayload/include/coreboot_tables.h
index 9864c2b5d4..12998de9db 100644
--- a/payloads/libpayload/include/coreboot_tables.h
+++ b/payloads/libpayload/include/coreboot_tables.h
@@ -464,6 +464,8 @@ enum boot_mode_t {
 	CB_BOOT_MODE_LOW_BATTERY_CHARGING,
 	/* Device is booting in due to charger insertion */
 	CB_BOOT_MODE_OFFMODE_CHARGING,
+	/* Device is booting in due to RTC alarm */
+	CB_BOOT_MODE_RTC_WAKE,
 };
 
 /*
diff --git a/src/commonlib/include/commonlib/coreboot_tables.h b/src/commonlib/include/commonlib/coreboot_tables.h
index cb16e65c5c..87da127ef9 100644
--- a/src/commonlib/include/commonlib/coreboot_tables.h
+++ b/src/commonlib/include/commonlib/coreboot_tables.h
@@ -647,6 +647,8 @@ enum boot_mode_t {
 	LB_BOOT_MODE_LOW_BATTERY_CHARGING,
 	/* Device is booting in due to charger insertion */
 	LB_BOOT_MODE_OFFMODE_CHARGING,
+	/* Device is booting in due to RTC alarm */
+	LB_BOOT_MODE_RTC_WAKE,
 };
 
 /*

From 444691603df5cb6a925072daa475b6b2a66a9da6 Mon Sep 17 00:00:00 2001
From: Subrata Banik <subratabanik@google.com>
Date: Thu, 19 Mar 2026 19:04:52 +0000
Subject: [PATCH 3762/3886] mb/google/bluey: Support RTC wake-up boot mode

Implement the logic to detect, set, and handle RTC wake-up events on
the Bluey mainboard.

Key changes:
- romstage: Use the new google_chromeec_is_rtc_event() API to set
  the boot mode to LB_BOOT_MODE_RTC_WAKE when an RTC alarm triggers
  the boot.
- mainboard: Update is_low_power_boot_with_charger() to include
  RTC_WAKE, ensuring the system follows the low-power initialization
  path (e.g., entering the charging applet).
- mainboard: Update display_startup() to skip display initialization
  during an RTC wake event to conserve power and maintain a "dark"
  wake-up state where appropriate.

BUG=b:493760057
BRANCH=none
TEST=Set an RTC alarm via the EC, verify the system boots into the
charging applet path and skips display initialization on Bluey.

Change-Id: Iaa9d1acffa0da014775e3397b877178c9c820ad5
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91765
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/google/bluey/mainboard.c | 6 ++++--
 src/mainboard/google/bluey/romstage.c  | 4 +++-
 2 files changed, 7 insertions(+), 3 deletions(-)

diff --git a/src/mainboard/google/bluey/mainboard.c b/src/mainboard/google/bluey/mainboard.c
index 8b3fb9d6b6..1b9b9955a2 100644
--- a/src/mainboard/google/bluey/mainboard.c
+++ b/src/mainboard/google/bluey/mainboard.c
@@ -70,7 +70,8 @@ static bool is_low_power_boot_with_charger(void)
 	bool ret = false;
 	enum boot_mode_t boot_mode = get_boot_mode();
 	if ((boot_mode == LB_BOOT_MODE_LOW_BATTERY_CHARGING) ||
-	    (boot_mode == LB_BOOT_MODE_OFFMODE_CHARGING))
+	    (boot_mode == LB_BOOT_MODE_OFFMODE_CHARGING) ||
+	    (boot_mode == LB_BOOT_MODE_RTC_WAKE))
 		ret = true;
 
 	return ret;
@@ -155,7 +156,8 @@ bool mainboard_needs_pcie_init(void)
 
 static void display_startup(void)
 {
-	if (!display_init_required() || (CONFIG(VBOOT_LID_SWITCH) && !get_lid_switch())) {
+	if ((get_boot_mode() == LB_BOOT_MODE_RTC_WAKE) || !display_init_required() ||
+		    (CONFIG(VBOOT_LID_SWITCH) && !get_lid_switch())) {
 		printk(BIOS_INFO, "Skipping display init.\n");
 		return;
 	}
diff --git a/src/mainboard/google/bluey/romstage.c b/src/mainboard/google/bluey/romstage.c
index 042e69b9f0..8fe088e350 100644
--- a/src/mainboard/google/bluey/romstage.c
+++ b/src/mainboard/google/bluey/romstage.c
@@ -41,7 +41,9 @@ static enum boot_mode_t set_boot_mode(void)
 
 	enum boot_mode_t boot_mode_new;
 
-	if (is_off_mode() && google_chromeec_is_battery_present()) {
+	if (google_chromeec_is_rtc_event()) {
+		boot_mode_new = LB_BOOT_MODE_RTC_WAKE;
+	} else if (is_off_mode() && google_chromeec_is_battery_present()) {
 		boot_mode_new = LB_BOOT_MODE_OFFMODE_CHARGING;
 	} else if (google_chromeec_is_below_critical_threshold()) {
 		if (google_chromeec_is_charger_present())

From 2f93e4331edd8915a739091bf01fe2acad0a54c9 Mon Sep 17 00:00:00 2001
From: Subrata Banik <subratabanik@google.com>
Date: Thu, 19 Mar 2026 19:53:58 +0000
Subject: [PATCH 3763/3886] soc/qualcomm/common: Add spmi_read8_safe helper
 with retry logic

Introduce `spmi_read8_safe` to handle transient SPMI bus errors that
can occur during early power sequencing. This helper implements a
retry mechanism (up to 6 attempts) with a 50ms delay between reads.

Providing a "safe" read wrapper prevents the system from misinterpreting
transient arbiter errors (ERROR_SPMI_READ_FAILED) as valid zero data,
which is critical for preventing premature power-offs when reading
input current .

BUG=b:436391478
BRANCH=none
TEST=Verified that SPMI read failures in the charging applet now
trigger the retry loop and successfully recover on Bluey.

Change-Id: Id1b770d2cd91ccb069933bd9b023b867a7507009
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91766
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
---
 .../qualcomm/common/include/soc/qcom_spmi.h   |  1 +
 src/soc/qualcomm/common/spmi.c                | 29 ++++++++++++++++++-
 2 files changed, 29 insertions(+), 1 deletion(-)

diff --git a/src/soc/qualcomm/common/include/soc/qcom_spmi.h b/src/soc/qualcomm/common/include/soc/qcom_spmi.h
index 65d2e17bba..ef22d22377 100644
--- a/src/soc/qualcomm/common/include/soc/qcom_spmi.h
+++ b/src/soc/qualcomm/common/include/soc/qcom_spmi.h
@@ -12,5 +12,6 @@
 int spmi_read8(uint32_t addr);
 int spmi_write8(uint32_t addr, uint8_t data);
 int spmi_read_bytes(uint32_t addr, uint8_t *data, uint32_t num_bytes);
+int spmi_read8_safe(uint32_t reg);
 
 #endif	// __SOC_QCOM_SPMI_H__
diff --git a/src/soc/qualcomm/common/spmi.c b/src/soc/qualcomm/common/spmi.c
index 2409cbbf23..295dbc1ecf 100644
--- a/src/soc/qualcomm/common/spmi.c
+++ b/src/soc/qualcomm/common/spmi.c
@@ -2,6 +2,7 @@
 
 #include <arch/mmio.h>
 #include <commonlib/bsd/stdlib.h>
+#include <delay.h>
 #include <soc/addressmap.h>
 #include <soc/qcom_spmi.h>
 #include <timer.h>
@@ -19,9 +20,14 @@
 
 #define ERROR_APID_NOT_FOUND	(-(int)BIT(8))
 #define ERROR_TIMEOUT		(-(int)BIT(9))
+/* Add this for your specific SPMI read error (-9) */
+#define ERROR_SPMI_READ_FAILED  (-9)
 
 #define ARB_COMMAND_TIMEOUT_MS	100
 
+#define MAX_SPMI_RETRIES    6
+#define SPMI_RETRY_DELAY_MS 50
+
 // Individual register block per APID
 struct qcom_spmi_regs {
 	uint32_t cmd;
@@ -101,7 +107,7 @@ int spmi_read8(uint32_t addr)
 	int ret = wait_for_done(regs);
 	if (ret != 0) {
 		printk(BIOS_ERR, "ERROR: SPMI_ARB read error [0x%x]: 0x%x\n", addr, ret);
-		return ret;
+		return ERROR_SPMI_READ_FAILED;
 	}
 
 	return read32(&regs->rdata0) & 0xff;
@@ -141,3 +147,24 @@ int spmi_read_bytes(uint32_t addr, uint8_t *data, uint32_t num_bytes)
 	}
 	return 0;
 }
+
+/* Helper to handle transient SPMI bus errors with retries */
+int spmi_read8_safe(uint32_t reg)
+{
+	int val;
+	int retries = 0;
+
+	do {
+		val = spmi_read8(reg);
+		if (val != ERROR_SPMI_READ_FAILED)
+			return val;
+
+		printk(BIOS_WARNING, "SPMI read error at 0x%x. Retry %d/%d in %dms\n",
+		       reg, retries + 1, MAX_SPMI_RETRIES, SPMI_RETRY_DELAY_MS);
+
+		mdelay(SPMI_RETRY_DELAY_MS);
+		retries++;
+	} while (retries < MAX_SPMI_RETRIES);
+
+	return ERROR_SPMI_READ_FAILED;
+}

From 3f46d6fd939c291e90c25d0767dbb0ad5aacbcfd Mon Sep 17 00:00:00 2001
From: Subrata Banik <subratabanik@google.com>
Date: Thu, 19 Mar 2026 19:57:35 +0000
Subject: [PATCH 3764/3886] mb/google/bluey: Use safe SPMI reads for battery
 current telemetry

Update `get_battery_icurr_ma` to use the newly introduced
`spmi_read8_safe` helper. This ensures that transient SPMI arbiter
errors (0xfffffff7) are handled via retries rather than being
immediately treated as zero current.

By validating both the primary (SMB1) and secondary (SMB2) charger
registers with retries, the system avoids entering the power-off
path caused by spurious 0mA readings during early boot or rail
stabilization.

Additionally, using 5ms delay before charger SMB1/2 register read.

BUG=b:436391478
BRANCH=none
TEST=On Bluey, verify that battery current is reported correctly
even if the initial SPMI read encounters a transient failure.

Change-Id: I8dee77ba83798e8e50f8884604c588fe4fda0e0a
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91767
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/google/bluey/charging.c | 15 +++++++++++----
 1 file changed, 11 insertions(+), 4 deletions(-)

diff --git a/src/mainboard/google/bluey/charging.c b/src/mainboard/google/bluey/charging.c
index cb4ecf2855..e567b68575 100644
--- a/src/mainboard/google/bluey/charging.c
+++ b/src/mainboard/google/bluey/charging.c
@@ -58,11 +58,18 @@ enum charging_status {
 static int get_battery_icurr_ma(void)
 {
 	/* Read battery i-current value */
-	int icurr = spmi_read8(SMB1_CHGR_CHARGING_FCC);
-	if (icurr <= 0)
-		icurr = spmi_read8(SMB2_CHGR_CHARGING_FCC);
-	if (icurr < 0)
+	mdelay(5);
+	int icurr = spmi_read8_safe(SMB1_CHGR_CHARGING_FCC);
+	if (icurr <= 0) {
+		mdelay(5);
+		icurr = spmi_read8_safe(SMB2_CHGR_CHARGING_FCC);
+	}
+
+	/* Final safety: if both failed (still negative), treat as 0 */
+	if (icurr < 0) {
+		printk(BIOS_ERR, "Critical: Both SMB registers failed to read.\n");
 		icurr = 0;
+	}
 
 	icurr *= 50;
 	return icurr;

From dc41e46b7f2e2fb279f070d6f791d3e1d0742530 Mon Sep 17 00:00:00 2001
From: Pranava Y N <pranavayn@google.com>
Date: Fri, 20 Mar 2026 14:34:03 +0530
Subject: [PATCH 3765/3886] google/fatcat: Move mainboard_pre_dev_init_chips
 hook to BS_ON_EXIT

The current implementation executes the mainboard_pre_dev_init_chips
hook at the entry of BS_DEV_INIT_CHIPS boot state. Move this to
the exit to add more delay in execution, change the function name
accordingly.

BUG=b:493322404
TEST=Able to build and boot fatcat

Change-Id: Icec47552f3331457c05cd255ecc1385ec70d6b94
Signed-off-by: Pranava Y N <pranavayn@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91777
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
---
 src/mainboard/google/fatcat/mainboard.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/mainboard/google/fatcat/mainboard.c b/src/mainboard/google/fatcat/mainboard.c
index b731f1d4d5..a9adbe3710 100644
--- a/src/mainboard/google/fatcat/mainboard.c
+++ b/src/mainboard/google/fatcat/mainboard.c
@@ -67,12 +67,12 @@ void __weak fw_config_post_gpio_configure(void)
 	/* default implementation does nothing */
 }
 
-static void mainboard_pre_dev_init_chips(void *unused)
+static void mainboard_post_dev_init_chips(void *unused)
 {
 	fw_config_post_gpio_configure();
 }
 
-BOOT_STATE_INIT_ENTRY(BS_DEV_INIT_CHIPS, BS_ON_ENTRY, mainboard_pre_dev_init_chips, NULL);
+BOOT_STATE_INIT_ENTRY(BS_DEV_INIT_CHIPS, BS_ON_EXIT, mainboard_post_dev_init_chips, NULL);
 
 void __weak baseboard_devtree_update(void)
 {

From aa27204240cc45a8fca30f67fc5c2b70da9c33b6 Mon Sep 17 00:00:00 2001
From: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
Date: Thu, 19 Mar 2026 16:20:28 +0800
Subject: [PATCH 3766/3886] mb/google/fatcat/variants/moonstone: Implement BOE
 touchscreen power timing

To comply with the Focal touchscreen module specification and prevent
interference during the power on init and self-calibration process,
the power-on sequence is implemented across different boot stages:

1. GPIO Initialization (Romstage/Ramstage):
   - Pull Touch Enable (GPP_F08) High in the early GPIO table (Romstage)
     to stabilize Vcc early.
   - Pull Touch Report Switch (GPP_E05) High while initializing Touch
     Reset (TCHSCR_RST_L, GPP_F16) to Low in the main GPIO table
     (Ramstage) to maintain the reset state.

2. Chip Config Stage (Reset De-assertion):
   - Implement fw_config_post_gpio_configure() to pull TCHSCR_RST_L High
     during the BS_DEV_INIT_CHIPS stage.
   - This ensures the reset is released only after Backlight (BL_ON) is
     enabled, satisfying the module's calibration requirements.

3. ACPI & Power Management:
   - Retain 'stop_gpio' (GPP_E05) in overridetree.cb for S0ix power
     saving while removing 'reset_gpio' and 'enable_gpio' to avoid
     driver conflicts with the manual boot sequence.

BUG=b:493322404
TEST=Build and boot on moonstone, verify touchscreen power-on
sequence with oscilloscope to match BOE requirements.
Verified on moonstone: Touchscreen is correctly detected and
functional after boot and S0ix resume.

Change-Id: I0fd323e56cd86ae85a40a489513e158b05be2233
Signed-off-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91753
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Pranava Y N <pranavayn@google.com>
---
 src/mainboard/google/fatcat/variants/moonstone/gpio.c    | 6 ++++--
 .../fatcat/variants/moonstone/include/variant/gpio.h     | 2 ++
 .../google/fatcat/variants/moonstone/overridetree.cb     | 6 ++----
 src/mainboard/google/fatcat/variants/moonstone/variant.c | 9 +++++++++
 4 files changed, 17 insertions(+), 6 deletions(-)

diff --git a/src/mainboard/google/fatcat/variants/moonstone/gpio.c b/src/mainboard/google/fatcat/variants/moonstone/gpio.c
index 7f6aa0cdb7..eb1db7839a 100644
--- a/src/mainboard/google/fatcat/variants/moonstone/gpio.c
+++ b/src/mainboard/google/fatcat/variants/moonstone/gpio.c
@@ -195,7 +195,7 @@ static const struct pad_config gpio_table[] = {
 	/* GPP_E03:     GEN5_SSD_RESET_N */
 	PAD_CFG_GPO(GPP_E03, 1, PLTRST),
 	/* GPP_E05:     TCHSCR_RPT_EN */
-	PAD_CFG_GPO(GPP_E05, 0, PLTRST),
+	PAD_CFG_GPO(GPP_E05, 1, PLTRST),
 	/* GPP_E06:     NC */
 	PAD_NC(GPP_E06, NONE),
 	/* GPP_E07 : [] ==> EC_SOC_INT_ODL */
@@ -256,7 +256,7 @@ static const struct pad_config gpio_table[] = {
 	/* GPP_F13:     TCHSCR_I2C5_SDA */
 	PAD_CFG_NF(GPP_F13, NONE, DEEP, NF8),
 	/* GPP_F16:     TCHSCR_RST_L */
-	PAD_CFG_GPO(GPP_F16, 1, DEEP),
+	PAD_CFG_GPO(GPP_F16, 0, DEEP),
 	/* GPP_F17:     NC */
 	PAD_NC(GPP_F17, NONE),
 	/* GPP_F18:     TCHSCR_INT_L */
@@ -392,6 +392,8 @@ static const struct pad_config romstage_gpio_table[] = {
 	PAD_CFG_NF(GPP_C01, NONE, DEEP, NF1),
 	/* GPP_E03:     GEN5_SSD_RESET_N */
 	PAD_CFG_GPO(GPP_E03, 1, PLTRST),
+	/* GPP_F08:     EN_TCHSCR_PWR */
+	PAD_CFG_GPO(GPP_F08, 1, DEEP),
 };
 
 const struct pad_config *variant_gpio_table(size_t *num)
diff --git a/src/mainboard/google/fatcat/variants/moonstone/include/variant/gpio.h b/src/mainboard/google/fatcat/variants/moonstone/include/variant/gpio.h
index cced66807a..277aca3050 100644
--- a/src/mainboard/google/fatcat/variants/moonstone/include/variant/gpio.h
+++ b/src/mainboard/google/fatcat/variants/moonstone/include/variant/gpio.h
@@ -8,4 +8,6 @@
 /* EC wake is LAN_WAKE# which is a special DeepSX wake pin */
 #define GPE_EC_WAKE	GPE0_LAN_WAK
 
+#define TCHSCR_RST_L	GPP_F16
+
 #endif /* __MAINBOARD_GPIO_H__ */
diff --git a/src/mainboard/google/fatcat/variants/moonstone/overridetree.cb b/src/mainboard/google/fatcat/variants/moonstone/overridetree.cb
index 28b2fec984..f714b4eafa 100644
--- a/src/mainboard/google/fatcat/variants/moonstone/overridetree.cb
+++ b/src/mainboard/google/fatcat/variants/moonstone/overridetree.cb
@@ -473,10 +473,8 @@ chip soc/intel/pantherlake
 				register "generic.desc" = ""Focal Touchscreen""
 				register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_F18_IRQ)"
 				register "generic.detect" = "1"
-				register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_F16)"
-				register "generic.reset_delay_ms" = "20"
-				register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_F08)"
-				register "generic.enable_delay_ms" = "6"
+				register "generic.stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_E05)"
+				register "generic.stop_off_delay_ms" = "1"
 				register "generic.has_power_resource" = "1"
 				register "generic.use_gpio_for_status" = "true"
 				register "hid_desc_reg_offset" = "0x01"
diff --git a/src/mainboard/google/fatcat/variants/moonstone/variant.c b/src/mainboard/google/fatcat/variants/moonstone/variant.c
index 17ce4d2c2f..4af4421449 100644
--- a/src/mainboard/google/fatcat/variants/moonstone/variant.c
+++ b/src/mainboard/google/fatcat/variants/moonstone/variant.c
@@ -5,6 +5,7 @@
 #include <console/console.h>
 #include <fw_config.h>
 #include <sar.h>
+#include <variant/gpio.h>
 
 const char *get_wifi_sar_cbfs_filename(void)
 {
@@ -66,3 +67,11 @@ void variant_update_soc_chip_config(struct soc_intel_pantherlake_config *config)
 		config->tcss_ports[3] = (struct tcss_port_config) TCSS_PORT_DEFAULT(OC_SKIP);
 	}
 }
+
+void fw_config_post_gpio_configure(void)
+{
+	/* ensures touchscreen reset pin is asserted at the correct stage,
+	   satisfying the requirement that reset must occur after BL_ON. */
+	gpio_output(TCHSCR_RST_L, 1);
+	printk(BIOS_INFO, "TSR: assert touchscreen reset pin ...\n");
+}

From 1928db74a1310f7e3ef95d64d161c0940c6d7ddc Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Fri, 20 Mar 2026 11:30:45 -0500
Subject: [PATCH 3767/3886] Documentation: Finalize 26.03 release notes

This removes the 'upcoming release' text and updates the statistics
for the 26.03 release tag.

Change-Id: Iecc233664d55b6b3b10a775a2990ec673b371754
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91782
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 .../releases/coreboot-26.03-relnotes.md       | 22 +++++++++----------
 1 file changed, 11 insertions(+), 11 deletions(-)

diff --git a/Documentation/releases/coreboot-26.03-relnotes.md b/Documentation/releases/coreboot-26.03-relnotes.md
index 6e302db11e..fc7c82fd16 100644
--- a/Documentation/releases/coreboot-26.03-relnotes.md
+++ b/Documentation/releases/coreboot-26.03-relnotes.md
@@ -1,8 +1,8 @@
-Upcoming release - coreboot 26.03
+coreboot 26.03 release
 ========================================================================
 
 The coreboot project is pleased to announce the release of coreboot 26.03.
-This release incorporates 856 commits from 95 contributors, reflecting
+This release incorporates 876 commits from 95 contributors, reflecting
 continued focus on runtime configuration, security hardening, platform
 enablement, and memory/display data reliability across supported systems.
 
@@ -218,15 +218,15 @@ Platform Updates
 
 Statistics from the 25.12 to the 26.03 release
 --------------------------------------------
-* Total Commits: 856
-* Average Commits per day: 9.42
-* Total lines added: 107457
-* Average lines added per commit: 125.53
-* Number of patches adding more than 100 lines: 72
-* Average lines added per small commit: 41.11
-* Total lines removed: 22154
-* Average lines removed per commit: 25.88
-* Total difference between added and removed: 85303
+* Total Commits: 876
+* Average Commits per day: 9.53
+* Total lines added: 113570
+* Average lines added per commit: 129.65
+* Number of patches adding more than 100 lines: 78
+* Average lines added per small commit: 40.96
+* Total lines removed: 22309
+* Average lines removed per commit: 25.47
+* Total difference between added and removed: 91261
 * Total authors: 95
 
 

From 8549c6894a2fcf88e9318c44e105997fd481a929 Mon Sep 17 00:00:00 2001
From: Patrick Rudolph <patrick.rudolph@9elements.com>
Date: Tue, 24 Feb 2026 15:18:59 +0100
Subject: [PATCH 3768/3886] amdfwtool: Make NVRAM regions writeable

When ROM Armor is enabled and PSP is not in "capsule update mode",
the PSP can only write to PSP directory entries that have the writable
bit set. As the fTPM PSP trustlet must write to NVRAM regions as part
of the fTPM operation, set the writable bit on such regions.

Fixes crash on PSP side when using ROM Armor and fTPM.

Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Change-Id: I5668976d687e5f9aa3fc62e91adf6bde5cadb5b8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91699
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
---
 util/amdfwtool/amdfwtool.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/util/amdfwtool/amdfwtool.c b/util/amdfwtool/amdfwtool.c
index 15d2926fd3..a5047d6830 100644
--- a/util/amdfwtool/amdfwtool.c
+++ b/util/amdfwtool/amdfwtool.c
@@ -1127,6 +1127,7 @@ static void integrate_psp_firmwares(context *ctx,
 			pspdir->entries[count].rsvd = 0;
 			pspdir->entries[count].size = size;
 			pspdir->entries[count].addr = addr;
+			pspdir->entries[count].writable = 1;
 
 			pspdir->entries[count].address_mode =
 				SET_ADDR_MODE(pspdir, AMD_ADDR_REL_BIOS);

From 8e04206f280c474e2cf8398e7deb6f590912bbf7 Mon Sep 17 00:00:00 2001
From: Patrick Rudolph <patrick.rudolph@9elements.com>
Date: Wed, 25 Feb 2026 11:55:43 +0100
Subject: [PATCH 3769/3886] amdfwtool: mark AMD_BIOS_APOB_NV BIOS directory
 entry as writable

When using ROM Armor, the AMD_BIOS_APOB_NV BIOS directory table
entry needs to be marked as writable. Add support for marking
BIOS directory table entries as writable and set all BIOS directory
files to RO, except for AMD_BIOS_APOB_NV (type 0x63), which is
written at end of coreboot based on the FMAP.

TEST=ROM Armor 3 enabled system can write APOB through PSP mailbox
     interface. When the writable bit is not set cannot write APOB
     through mailbox interface.

Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Change-Id: Idce7f4afbdd2246a5c0fc96d27c3c721e4a5b03a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91700
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 util/amdfwtool/amdfwtool.c | 7 +++++++
 util/amdfwtool/amdfwtool.h | 5 ++++-
 2 files changed, 11 insertions(+), 1 deletion(-)

diff --git a/util/amdfwtool/amdfwtool.c b/util/amdfwtool/amdfwtool.c
index a5047d6830..87b13fc183 100644
--- a/util/amdfwtool/amdfwtool.c
+++ b/util/amdfwtool/amdfwtool.c
@@ -1330,6 +1330,9 @@ static void integrate_bios_levels(context *ctx, amd_cb_config *cb_config)
 		ctx->biosdir->entries[count].dest = -1;
 		ctx->biosdir->entries[count].reset = 0;
 		ctx->biosdir->entries[count].ro = 0;
+		ctx->biosdir->entries[count].romid = 0;
+		ctx->biosdir->entries[count].writable = 0;
+		ctx->biosdir->entries[count].rsvd = 0;
 		count++;
 		fill_dir_header(ctx->biosdir, count, ctx);
 		ctx->current_table = current_table_save;
@@ -1451,6 +1454,9 @@ static void integrate_bios_firmwares(context *ctx,
 		biosdir->entries[count].compressed = fw_table[i].zlib;
 		biosdir->entries[count].inst = fw_table[i].inst;
 		biosdir->entries[count].subprog = fw_table[i].subpr;
+		biosdir->entries[count].romid = 0;
+		biosdir->entries[count].writable = 0;
+		biosdir->entries[count].rsvd = 0;
 
 		switch (fw_table[i].type) {
 		case AMD_BIOS_SIG:
@@ -1491,6 +1497,7 @@ static void integrate_bios_firmwares(context *ctx,
 					SET_ADDR_MODE(biosdir, AMD_ADDR_REL_BIOS);
 			}
 			biosdir->entries[count].size = fw_table[i].size;
+			biosdir->entries[count].writable = 1;
 			break;
 		case AMD_BIOS_BIN:
 			/* Don't make a 2nd copy, point to the same one */
diff --git a/util/amdfwtool/amdfwtool.h b/util/amdfwtool/amdfwtool.h
index bd973638ed..0d1a6a2e70 100644
--- a/util/amdfwtool/amdfwtool.h
+++ b/util/amdfwtool/amdfwtool.h
@@ -301,7 +301,10 @@ typedef struct _bios_directory_entry {
 	int ro:1;
 	int compressed:1;
 	int inst:4;
-	uint8_t subprog; /* b[7:3] reserved */
+	uint8_t subprog:3;
+	uint8_t romid:2;
+	uint8_t writable:1;
+	uint8_t rsvd:2;
 	uint32_t size;
 	uint64_t source:62;
 	uint64_t address_mode:2;

From b7faa4c51a54d79dc18b2745d644a15342a357e3 Mon Sep 17 00:00:00 2001
From: Patrick Rudolph <patrick.rudolph@9elements.com>
Date: Thu, 26 Feb 2026 10:38:43 +0100
Subject: [PATCH 3770/3886] amdfwtool: Allow to set bios entry 0x6d
 (AMD_BIOS_NV_ST)

Allow the build system to specify the variable store position in flash
and update BIOS entry 0x6d when set.

Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Change-Id: I3888810570897ea509a49fd4bc38d875d7d8be0c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91701
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
---
 util/amdfwtool/amdfwtool.c |   2 +
 util/amdfwtool/opts.c      | 146 ++++++++++++++++++++-----------------
 2 files changed, 83 insertions(+), 65 deletions(-)

diff --git a/util/amdfwtool/amdfwtool.c b/util/amdfwtool/amdfwtool.c
index 87b13fc183..4e0901cb7d 100644
--- a/util/amdfwtool/amdfwtool.c
+++ b/util/amdfwtool/amdfwtool.c
@@ -1391,6 +1391,7 @@ static void integrate_bios_firmwares(context *ctx,
 				fw_table[i].type != AMD_BIOS_APOB_NV &&
 				fw_table[i].type != AMD_BIOS_L2_PTR &&
 				fw_table[i].type != AMD_BIOS_BIN &&
+				fw_table[i].type != AMD_BIOS_NV_ST &&
 				fw_table[i].type != AMD_BIOS_PSP_SHARED_MEM))
 			continue;
 
@@ -1475,6 +1476,7 @@ static void integrate_bios_firmwares(context *ctx,
 			biosdir->entries[count].address_mode = SET_ADDR_MODE_BY_TABLE(biosdir);
 			break;
 		case AMD_BIOS_APOB_NV:
+		case AMD_BIOS_NV_ST:
 			if (has_apob_nv_quirk(cb_config->soc_id)) {
 				/*
 				 * once ROM3 mapping (>16MiB) is used on any SOC that
diff --git a/util/amdfwtool/opts.c b/util/amdfwtool/opts.c
index 158eb656aa..87f51a646d 100644
--- a/util/amdfwtool/opts.c
+++ b/util/amdfwtool/opts.c
@@ -61,6 +61,8 @@ enum {
 	AMDFW_OPT_SIGNED_OUTPUT,
 	AMDFW_OPT_SIGNED_ADDR,
 	AMDFW_OPT_BODY_LOCATION,
+	AMDFW_OPT_VARIABLE_NVRAM_BASE,
+	AMDFW_OPT_VARIABLE_NVRAM_SIZE,
 	/* begin after ASCII characters */
 	LONGOPT_SPI_READ_MODE	= 256,
 	LONGOPT_SPI_SPEED	= 257,
@@ -87,6 +89,8 @@ static struct option long_options[] = {
 	{"combo-config1",    required_argument, 0, AMDFW_OPT_COMBO1_CONFIG },
 	{"multilevel",             no_argument, 0, AMDFW_OPT_MULTILEVEL },
 	{"nvram",            required_argument, 0, AMDFW_OPT_NVRAM },
+	{"variable-nvram-base",     required_argument, 0, AMDFW_OPT_VARIABLE_NVRAM_BASE },
+	{"variable-nvram-size",     required_argument, 0, AMDFW_OPT_VARIABLE_NVRAM_SIZE },
 	{"nvram-base",       required_argument, 0, LONGOPT_NVRAM_BASE },
 	{"nvram-size",       required_argument, 0, LONGOPT_NVRAM_SIZE },
 	{"rpmc-nvram-base",  required_argument, 0, LONGOPT_RPMC_NVRAM_BASE },
@@ -141,78 +145,80 @@ static void usage(void)
 {
 	printf("amdfwtool: Create AMD Firmware combination\n");
 	printf("Usage: amdfwtool [options] --flashsize <size> --output <filename>\n");
-	printf("--xhci <FILE>                  Add XHCI blob\n");
-	printf("--imc <FILE>                   Add IMC blob\n");
-	printf("--gec <FILE>                   Add GEC blob\n");
+	printf("--xhci <FILE>                   Add XHCI blob\n");
+	printf("--imc <FILE>                    Add IMC blob\n");
+	printf("--gec <FILE>                    Add GEC blob\n");
 
 	printf("\nPSP options:\n");
-	printf("--use-combo                    Use the COMBO layout\n");
-	printf("--combo-config1 <config file>  Config for 1st combo entry\n");
-	printf("--multilevel                   Generate primary and secondary tables\n");
-	printf("--nvram <FILE>                 Add nvram binary\n");
-	printf("--soft-fuse                    Set soft fuse\n");
-	printf("--token-unlock                 Set token unlock\n");
-	printf("--nvram-base <HEX_VAL>         Base address of nvram\n");
-	printf("--nvram-size <HEX_VAL>         Size of nvram\n");
-	printf("--rpmc-nvram-base <HEX_VAL>    Base address of RPMC nvram\n");
-	printf("--rpmc-nvram-size <HEX_VAL>    Size of RPMC nvram\n");
-	printf("--whitelist                    Set if there is a whitelist\n");
-	printf("--use-pspsecureos              Set if psp secure OS is needed\n");
-	printf("--load-mp2-fw                  Set if load MP2 firmware\n");
-	printf("--load-s0i3                    Set if load s0i3 firmware\n");
-	printf("--verstage <FILE>              Add verstage\n");
-	printf("--verstage_sig                 Add verstage signature\n");
-	printf("--recovery-ab                  Use the recovery A/B layout\n");
+	printf("--use-combo                     Use the COMBO layout\n");
+	printf("--combo-config1 <config file>   Config for 1st combo entry\n");
+	printf("--multilevel                    Generate primary and secondary tables\n");
+	printf("--nvram <FILE>                  Add nvram binary\n");
+	printf("--soft-fuse                     Set soft fuse\n");
+	printf("--token-unlock                  Set token unlock\n");
+	printf("--nvram-base <HEX_VAL>          Base address of nvram\n");
+	printf("--nvram-size <HEX_VAL>          Size of nvram\n");
+	printf("--variable-nvram-base <HEX_VAL> Base address of variable nvram\n");
+	printf("--variable-nvram-size <HEX_VAL> Size of variable nvram\n");
+	printf("--rpmc-nvram-base <HEX_VAL>     Base address of RPMC nvram\n");
+	printf("--rpmc-nvram-size <HEX_VAL>     Size of RPMC nvram\n");
+	printf("--whitelist                     Set if there is a whitelist\n");
+	printf("--use-pspsecureos               Set if psp secure OS is needed\n");
+	printf("--load-mp2-fw                   Set if load MP2 firmware\n");
+	printf("--load-s0i3                     Set if load s0i3 firmware\n");
+	printf("--verstage <FILE>               Add verstage\n");
+	printf("--verstage_sig                  Add verstage signature\n");
+	printf("--recovery-ab                   Use the recovery A/B layout\n");
 	printf("\nBIOS options:\n");
-	printf("--instance <number>            Sets instance field for the next BIOS\n");
-	printf("                               firmware\n");
-	printf("--apcb <FILE>                  Add AGESA PSP customization block\n");
-	printf("--apcb-combo1 <FILE>           Add APCB for 1st combo\n");
-	printf("--apob-base <HEX_VAL>          Destination for AGESA PSP output block\n");
-	printf("--apob-nv-base <HEX_VAL>       Location of S3 resume data\n");
-	printf("--apob-nv-size <HEX_VAL>       Size of S3 resume data\n");
-	printf("--ucode <FILE>                 Add microcode patch\n");
-	printf("--bios-bin <FILE>              Add compressed image; auto source address\n");
-	printf("--bios-bin-src <HEX_VAL>       Address in flash of source if -V not used\n");
-	printf("--bios-bin-dest <HEX_VAL>      Destination for uncompressed BIOS\n");
-	printf("--bios-uncomp-size <HEX>       Uncompressed size of BIOS image\n");
-	printf("--output <filename>            output filename\n");
-	printf("--flashsize <HEX_VAL>          ROM size in bytes\n");
-	printf("                               size must be larger than %dKB\n",
+	printf("--instance <number>             Sets instance field for the next BIOS\n");
+	printf("                                firmware\n");
+	printf("--apcb <FILE>                   Add AGESA PSP customization block\n");
+	printf("--apcb-combo1 <FILE>            Add APCB for 1st combo\n");
+	printf("--apob-base <HEX_VAL>           Destination for AGESA PSP output block\n");
+	printf("--apob-nv-base <HEX_VAL>        Location of S3 resume data\n");
+	printf("--apob-nv-size <HEX_VAL>        Size of S3 resume data\n");
+	printf("--ucode <FILE>                  Add microcode patch\n");
+	printf("--bios-bin <FILE>               Add compressed image; auto source address\n");
+	printf("--bios-bin-src <HEX_VAL>        Address in flash of source if -V not used\n");
+	printf("--bios-bin-dest <HEX_VAL>       Destination for uncompressed BIOS\n");
+	printf("--bios-uncomp-size <HEX>        Uncompressed size of BIOS image\n");
+	printf("--output <filename>             output filename\n");
+	printf("--flashsize <HEX_VAL>           ROM size in bytes\n");
+	printf("                                size must be larger than %dKB\n",
 		MIN_ROM_KB);
-	printf("                               and must a multiple of 1024\n");
-	printf("--location                     Location of Directory\n");
-	printf("--anywhere                     Use any 64-byte aligned addr for Directory\n");
-	printf("--sharedmem                    Location of PSP/FW shared memory\n");
-	printf("--sharedmem-size               Maximum size of the PSP/FW shared memory\n");
-	printf("                               area\n");
-	printf("--output-manifest <FILE>       Writes a manifest with the blobs versions\n");
+	printf("                                and must a multiple of 1024\n");
+	printf("--location                      Location of Directory\n");
+	printf("--anywhere                      Use any 64-byte aligned addr for Directory\n");
+	printf("--sharedmem                     Location of PSP/FW shared memory\n");
+	printf("--sharedmem-size                Maximum size of the PSP/FW shared memory\n");
+	printf("                                area\n");
+	printf("--output-manifest <FILE>        Writes a manifest with the blobs versions\n");
 	printf("\nEmbedded Firmware Structure options used by the PSP:\n");
-	printf("--spi-speed <HEX_VAL>          SPI fast speed to place in EFS Table\n");
-	printf("                               0x0 66.66Mhz\n");
-	printf("                               0x1 33.33MHz\n");
-	printf("                               0x2 22.22MHz\n");
-	printf("                               0x3 16.66MHz\n");
-	printf("                               0x4 100MHz\n");
-	printf("                               0x5 800KHz\n");
-	printf("--spi-read-mode <HEX_VAL>      SPI read mode to place in EFS Table\n");
-	printf("                               0x0 Normal Read (up to 33M)\n");
-	printf("                               0x1 Reserved\n");
-	printf("                               0x2 Dual IO (1-1-2)\n");
-	printf("                               0x3 Quad IO (1-1-4)\n");
-	printf("                               0x4 Dual IO (1-2-2)\n");
-	printf("                               0x5 Quad IO (1-4-4)\n");
-	printf("                               0x6 Normal Read (up to 66M)\n");
-	printf("                               0x7 Fast Read\n");
-	printf("--spi-micron-flag <HEX_VAL>    Micron SPI part support for RV and later SOC\n");
-	printf("                               0x0 Micron parts are not used\n");
-	printf("                               0x1 Micron parts are always used\n");
-	printf("                               0x2 Micron parts optional, this option is only\n");
+	printf("--spi-speed <HEX_VAL>           SPI fast speed to place in EFS Table\n");
+	printf("                                0x0 66.66Mhz\n");
+	printf("                                0x1 33.33MHz\n");
+	printf("                                0x2 22.22MHz\n");
+	printf("                                0x3 16.66MHz\n");
+	printf("                                0x4 100MHz\n");
+	printf("                                0x5 800KHz\n");
+	printf("--spi-read-mode <HEX_VAL>       SPI read mode to place in EFS Table\n");
+	printf("                                0x0 Normal Read (up to 33M)\n");
+	printf("                                0x1 Reserved\n");
+	printf("                                0x2 Dual IO (1-1-2)\n");
+	printf("                                0x3 Quad IO (1-1-4)\n");
+	printf("                                0x4 Dual IO (1-2-2)\n");
+	printf("                                0x5 Quad IO (1-4-4)\n");
+	printf("                                0x6 Normal Read (up to 66M)\n");
+	printf("                                0x7 Fast Read\n");
+	printf("--spi-micron-flag <HEX_VAL>     Micron SPI part support for RV and later SOC\n");
+	printf("                                0x0 Micron parts are not used\n");
+	printf("                                0x1 Micron parts are always used\n");
+	printf("                                0x2 Micron parts optional, this option is only\n");
 	printf("                                   supported with RN/LCN SOC\n");
 	printf("\nGeneral options:\n");
-	printf("-c|--config <config file>      Config file\n");
-	printf("-d|--debug                     Print debug message\n");
-	printf("-h|--help                      Show this help\n");
+	printf("-c|--config <config file>       Config file\n");
+	printf("-d|--debug                      Print debug message\n");
+	printf("-h|--help                       Show this help\n");
 }
 
 extern amd_fw_entry amd_psp_fw_table[];
@@ -461,6 +467,16 @@ int amdfwtool_getopt(int argc, char *argv[], amd_cb_config *cb_config, context *
 			register_bios_fw_addr(AMD_BIOS_APOB_NV, 0, 0, optarg);
 			sub = instance = 0;
 			break;
+		case AMDFW_OPT_VARIABLE_NVRAM_BASE:
+			/* APOB variable NVRAM base */
+			register_bios_fw_addr(AMD_BIOS_NV_ST, optarg, 0, 0);
+			sub = instance = 0;
+			break;
+		case AMDFW_OPT_VARIABLE_NVRAM_SIZE:
+			/* APOB variable NVRAM size */
+			register_bios_fw_addr(AMD_BIOS_NV_ST, 0, 0, optarg);
+			sub = instance = 0;
+			break;
 		case AMDFW_OPT_BIOSBIN:
 			register_bdt_data(AMD_BIOS_BIN, sub, instance, optarg);
 			sub = instance = 0;

From e657f5da15758592d046d27923d21941dbc0451d Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Sun, 22 Mar 2026 19:58:05 +0000
Subject: [PATCH 3771/3886] mainboard/starlabs: drop redundant vbt.bin
 overrides

drivers/intel/gma/opregion already provides a weak
mainboard_vbt_filename() implementation that returns "vbt.bin".

Drop the Starlabs overrides that return the same filename and keep only
the remaining board-specific override that still selects an alternate
VBT. This also removes the now-dead overrides left behind after
display-native-resolution VBT selection was dropped.

Change-Id: I89ec4f55d4c4ed3265a8d429c3d399977ad466d7
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91814
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
---
 src/mainboard/starlabs/adl/variants/hz/ramstage.c          | 6 ------
 src/mainboard/starlabs/adl/variants/i5/ramstage.c          | 6 ------
 src/mainboard/starlabs/starbook/mainboard.c                | 5 -----
 src/mainboard/starlabs/starfighter/variants/rpl/ramstage.c | 6 ------
 4 files changed, 23 deletions(-)

diff --git a/src/mainboard/starlabs/adl/variants/hz/ramstage.c b/src/mainboard/starlabs/adl/variants/hz/ramstage.c
index de25c0a7e5..3e9cfb13c4 100644
--- a/src/mainboard/starlabs/adl/variants/hz/ramstage.c
+++ b/src/mainboard/starlabs/adl/variants/hz/ramstage.c
@@ -1,6 +1,5 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
-#include <drivers/intel/gma/opregion.h>
 #include <soc/ramstage.h>
 #include <common/pin_mux.h>
 
@@ -8,8 +7,3 @@ void mainboard_silicon_init_params(FSP_S_CONFIG *supd)
 {
 	configure_pin_mux(supd);
 }
-
-const char *mainboard_vbt_filename(void)
-{
-	return "vbt.bin";
-}
diff --git a/src/mainboard/starlabs/adl/variants/i5/ramstage.c b/src/mainboard/starlabs/adl/variants/i5/ramstage.c
index de25c0a7e5..3e9cfb13c4 100644
--- a/src/mainboard/starlabs/adl/variants/i5/ramstage.c
+++ b/src/mainboard/starlabs/adl/variants/i5/ramstage.c
@@ -1,6 +1,5 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
-#include <drivers/intel/gma/opregion.h>
 #include <soc/ramstage.h>
 #include <common/pin_mux.h>
 
@@ -8,8 +7,3 @@ void mainboard_silicon_init_params(FSP_S_CONFIG *supd)
 {
 	configure_pin_mux(supd);
 }
-
-const char *mainboard_vbt_filename(void)
-{
-	return "vbt.bin";
-}
diff --git a/src/mainboard/starlabs/starbook/mainboard.c b/src/mainboard/starlabs/starbook/mainboard.c
index 93982cf807..31ec59bb30 100644
--- a/src/mainboard/starlabs/starbook/mainboard.c
+++ b/src/mainboard/starlabs/starbook/mainboard.c
@@ -18,8 +18,3 @@ static void starlabs_configure_gpios(void *unused)
 BOOT_STATE_INIT_ENTRY(BS_PRE_DEVICE, BS_ON_ENTRY, starlabs_configure_gpios, NULL);
 
 struct chip_operations mainboard_ops = {};
-
-const char *mainboard_vbt_filename(void)
-{
-	return "vbt.bin";
-}
diff --git a/src/mainboard/starlabs/starfighter/variants/rpl/ramstage.c b/src/mainboard/starlabs/starfighter/variants/rpl/ramstage.c
index 6e4471589e..6ffe593f7f 100644
--- a/src/mainboard/starlabs/starfighter/variants/rpl/ramstage.c
+++ b/src/mainboard/starlabs/starfighter/variants/rpl/ramstage.c
@@ -1,7 +1,6 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
 #include <option.h>
-#include <drivers/intel/gma/opregion.h>
 #include <soc/ramstage.h>
 #include <common/pin_mux.h>
 
@@ -12,8 +11,3 @@ void mainboard_silicon_init_params(FSP_S_CONFIG *supd)
 	if (get_uint_option("thunderbolt", 1) == 0)
 		supd->UsbTcPortEn = 0;
 }
-
-const char *mainboard_vbt_filename(void)
-{
-	return "vbt.bin";
-}

From 7bc3561803ff78b9b9121b997ceea65924e8a76b Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Sun, 22 Mar 2026 20:00:22 +0000
Subject: [PATCH 3772/3886] ec/starlabs/merlin: Include stdint

These files use unit16_t and more, so this should be included.

Change-Id: If08dd6c3267b39cd72fcfaa9803c72260165337d
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91815
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/ec/starlabs/merlin/ec.h | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/src/ec/starlabs/merlin/ec.h b/src/ec/starlabs/merlin/ec.h
index 39c805cb48..753383fb32 100644
--- a/src/ec/starlabs/merlin/ec.h
+++ b/src/ec/starlabs/merlin/ec.h
@@ -7,6 +7,8 @@
 #ifndef _EC_STARLABS_EC_H
 #define _EC_STARLABS_EC_H
 
+#include <stdint.h>
+
 /*
  * Define the expected value of the PNP base address that is fixed through
  * the BADRSEL register controlled within the EC domain by the EC Firmware.

From b137044a39302f859c5f9579f2ac3c160480fba7 Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Wed, 18 Mar 2026 21:39:20 +0000
Subject: [PATCH 3773/3886] ec/starlabs/merlin: Remove unused halt.h

Change-Id: I68ca43218dd8702e5215827045f2cd62d52ea767
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91733
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
---
 src/ec/starlabs/merlin/ite.c     | 2 --
 src/ec/starlabs/merlin/nuvoton.c | 2 --
 2 files changed, 4 deletions(-)

diff --git a/src/ec/starlabs/merlin/ite.c b/src/ec/starlabs/merlin/ite.c
index a3369700c3..d1e7a41be7 100644
--- a/src/ec/starlabs/merlin/ite.c
+++ b/src/ec/starlabs/merlin/ite.c
@@ -5,8 +5,6 @@
 #include <device/pnp.h>
 #include <ec/acpi/ec.h>
 #include <option.h>
-#include <halt.h>
-
 #include "ecdefs.h"
 #include "ec.h"
 
diff --git a/src/ec/starlabs/merlin/nuvoton.c b/src/ec/starlabs/merlin/nuvoton.c
index 398b12619b..a435c2a49b 100644
--- a/src/ec/starlabs/merlin/nuvoton.c
+++ b/src/ec/starlabs/merlin/nuvoton.c
@@ -5,8 +5,6 @@
 #include <device/pnp.h>
 #include <ec/acpi/ec.h>
 #include <option.h>
-#include <halt.h>
-
 #include "ecdefs.h"
 #include "ec.h"
 

From d319b33114673736614647ea50605a54e31cdbdd Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Wed, 18 Mar 2026 21:39:35 +0000
Subject: [PATCH 3774/3886] mainboard/starlabs/common: Remove unused headers

Change-Id: I230f8180d308cc7e5692268741a2cb1fee98ba27
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91734
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
---
 src/mainboard/starlabs/common/gnvs.c          | 1 -
 src/mainboard/starlabs/common/smbios/smbios.c | 5 -----
 2 files changed, 6 deletions(-)

diff --git a/src/mainboard/starlabs/common/gnvs.c b/src/mainboard/starlabs/common/gnvs.c
index 7e119470ab..b95bf314ad 100644
--- a/src/mainboard/starlabs/common/gnvs.c
+++ b/src/mainboard/starlabs/common/gnvs.c
@@ -2,7 +2,6 @@
 
 #include <stddef.h>
 
-#include <acpi/acpi_gnvs.h>
 #include <starlabs/efi_option_smi.h>
 
 size_t size_of_dnvs(void)
diff --git a/src/mainboard/starlabs/common/smbios/smbios.c b/src/mainboard/starlabs/common/smbios/smbios.c
index 00e6f249c7..147dd9211e 100644
--- a/src/mainboard/starlabs/common/smbios/smbios.c
+++ b/src/mainboard/starlabs/common/smbios/smbios.c
@@ -1,13 +1,8 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
-#include <soc/soc_chip.h>
-#include <device/device.h>
-#include <device/pci_def.h>
 #include <ec/starlabs/merlin/ec.h>
 #include <smbios.h>
 #include <types.h>
-#include <uuid.h>
-#include <variants.h>
 
 /* Get the Embedded Controller firmware version */
 void smbios_ec_revision(uint8_t *ec_major_revision, uint8_t *ec_minor_revision)

From b0ff1cdd28437c407d9ff33fa004d3732aa7d3a3 Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Wed, 18 Mar 2026 21:39:40 +0000
Subject: [PATCH 3775/3886] mainboard/starlabs/adl: Remove unused headers

Change-Id: I0069c1023bfc257db9b86b1fabb661cfe32d80db
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91735
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/starlabs/adl/mainboard.c | 2 --
 1 file changed, 2 deletions(-)

diff --git a/src/mainboard/starlabs/adl/mainboard.c b/src/mainboard/starlabs/adl/mainboard.c
index d7a0dab9a8..711170fbeb 100644
--- a/src/mainboard/starlabs/adl/mainboard.c
+++ b/src/mainboard/starlabs/adl/mainboard.c
@@ -2,8 +2,6 @@
 
 #include <bootstate.h>
 #include <device/device.h>
-#include <drivers/intel/gma/opregion.h>
-#include <soc/ramstage.h>
 #include <variants.h>
 
 static void starlabs_configure_mainboard(void *unused)

From c4e44caef8587e853cf7be6395076363de70d2fd Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Wed, 18 Mar 2026 21:39:46 +0000
Subject: [PATCH 3776/3886] mainboard/starlabs/starbook: Remove unused headers

Change-Id: I0e082c822abf6264d9832790ae86e3cde3c950a2
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91736
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/starlabs/starbook/mainboard.c | 2 --
 1 file changed, 2 deletions(-)

diff --git a/src/mainboard/starlabs/starbook/mainboard.c b/src/mainboard/starlabs/starbook/mainboard.c
index 31ec59bb30..bd857d6ee6 100644
--- a/src/mainboard/starlabs/starbook/mainboard.c
+++ b/src/mainboard/starlabs/starbook/mainboard.c
@@ -2,8 +2,6 @@
 
 #include <bootstate.h>
 #include <device/device.h>
-#include <drivers/intel/gma/opregion.h>
-#include <soc/ramstage.h>
 #include <variants.h>
 
 static void starlabs_configure_gpios(void *unused)

From a19b5b4b17efd675305f44b5a3ce14b0d52ec341 Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Wed, 18 Mar 2026 21:39:51 +0000
Subject: [PATCH 3777/3886] mainboard/starlabs/starfighter: Remove unused
 header

Change-Id: Ida54f8b836b5be72284a6b8735b92ab577d580a5
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91737
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
---
 src/mainboard/starlabs/starfighter/mainboard.c | 1 -
 1 file changed, 1 deletion(-)

diff --git a/src/mainboard/starlabs/starfighter/mainboard.c b/src/mainboard/starlabs/starfighter/mainboard.c
index e0b6ffae49..bd857d6ee6 100644
--- a/src/mainboard/starlabs/starfighter/mainboard.c
+++ b/src/mainboard/starlabs/starfighter/mainboard.c
@@ -2,7 +2,6 @@
 
 #include <bootstate.h>
 #include <device/device.h>
-#include <soc/ramstage.h>
 #include <variants.h>
 
 static void starlabs_configure_gpios(void *unused)

From ab63331423d9ddfcfb50bc77c5711329574c8199 Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Wed, 18 Mar 2026 21:39:56 +0000
Subject: [PATCH 3778/3886] mainboard/starlabs/lite: Remove unused header

Change-Id: I7950c80cbdff2b1ede759681ed17c31c7ae22da8
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91738
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/starlabs/lite/mainboard.c | 1 -
 1 file changed, 1 deletion(-)

diff --git a/src/mainboard/starlabs/lite/mainboard.c b/src/mainboard/starlabs/lite/mainboard.c
index cd46529c0f..6113446481 100644
--- a/src/mainboard/starlabs/lite/mainboard.c
+++ b/src/mainboard/starlabs/lite/mainboard.c
@@ -1,7 +1,6 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
 #include <device/device.h>
-#include <soc/ramstage.h>
 #include <variants.h>
 
 static void init_mainboard(void *chip_info)

From ff7bc7d2d1a893313c56ed415150b3a2c0d0cd40 Mon Sep 17 00:00:00 2001
From: Patrick Rudolph <patrick.rudolph@9elements.com>
Date: Thu, 19 Mar 2026 16:15:28 +0100
Subject: [PATCH 3779/3886] drivers/amd/ftpm: Fix compilation

The function tlcl2_get_capability() is only linked when Kconfig TPM2
is being selected. Add a guard to not include the SMBIOS code when
TPM2 isn't selected.

TEST=Can compile the fTPM driver when TPM2 isn't selected.

Change-Id: I9385f15fc71c021f9be2bfb874898f76fa71fee4
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91775
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/drivers/amd/ftpm/tis.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/drivers/amd/ftpm/tis.c b/src/drivers/amd/ftpm/tis.c
index 0f0dd5c899..49ad0bd335 100644
--- a/src/drivers/amd/ftpm/tis.c
+++ b/src/drivers/amd/ftpm/tis.c
@@ -111,7 +111,7 @@ static const char *crb_tpm_acpi_name(const struct device *dev)
 	return "TPM2";
 }
 
-#if CONFIG(GENERATE_SMBIOS_TABLES)
+#if CONFIG(GENERATE_SMBIOS_TABLES) && CONFIG(TPM2)
 static tpm_result_t tpm_get_cap(uint32_t property, uint32_t *value)
 {
 	TPMS_CAPABILITY_DATA cap_data;
@@ -188,7 +188,7 @@ static struct device_operations __maybe_unused amd_crb_ops = {
 	.acpi_name = crb_tpm_acpi_name,
 	.acpi_fill_ssdt = crb_tpm_fill_ssdt,
 #endif
-#if CONFIG(GENERATE_SMBIOS_TABLES)
+#if CONFIG(GENERATE_SMBIOS_TABLES) && CONFIG(TPM2)
 	.get_smbios_data	= smbios_write_type43_tpm,
 #endif
 };

From 6c8a2a6ea1edde42d5f0eeb9604d1e278b80c7c3 Mon Sep 17 00:00:00 2001
From: Patrick Rudolph <patrick.rudolph@9elements.com>
Date: Thu, 19 Mar 2026 17:23:59 +0100
Subject: [PATCH 3780/3886] soc/amd/glinda: Use VBIOS from amd_blobs

Set defaults for VGA_BIOS_FILE and VGA_BIOS_ID.

TEST=Pre OS graphics init works on AMD/jaguar.

Change-Id: I3bf0e81b0de87abe4a03be8e10274936cf29e628
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91776
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
---
 src/soc/amd/glinda/Kconfig | 11 +++++++++++
 1 file changed, 11 insertions(+)

diff --git a/src/soc/amd/glinda/Kconfig b/src/soc/amd/glinda/Kconfig
index 70a1fc6331..29b404ac3d 100644
--- a/src/soc/amd/glinda/Kconfig
+++ b/src/soc/amd/glinda/Kconfig
@@ -114,6 +114,17 @@ config CHIPSET_DEVICETREE
 	string
 	default "soc/amd/glinda/chipset.cb"
 
+config VGA_BIOS_FILE
+	string
+	default "3rdparty/amd_blobs/strix_krackan/KRK2E_GENERIC_vbios.sbin" if SOC_AMD_FAEGAN
+
+config VGA_BIOS_ID
+	string
+	default "1002,1902"
+	help
+	  The default VGA BIOS PCI vendor/device ID should be set to the
+	  result of the map_oprom_vendev() function in graphics.c.
+
 config CPU_PT_ROM_MAP_GB
 	default 1024
 

From 92fa2bbd094a08496bfc0da1f9d993015fa36b78 Mon Sep 17 00:00:00 2001
From: Subrata Banik <subratabanik@google.com>
Date: Sat, 21 Mar 2026 17:22:14 +0530
Subject: [PATCH 3781/3886] soc/qualcomm/x1p42100: Disable compression for
 CPUCP payload

The CPUCP (CPU Control Processor) firmware for X1P42100 is being
loaded as a payload. Compressing this file in CBFS can lead to
loading delays with the early-stage.

Set the compression type to 'none' to ensure the ELF is stored
uncompressed.

BUG=b:449871690
TEST=Able to optimize boot time (tested on google/quartz) by ~200ms.

w/o this patch:

```
fallback/cpucp     0xc7500    simple elf     149498 none
```

w/ this patch:

```
fallback/cpucp     0xc7500    simple elf     496196 none
```

Change-Id: I77418ac05ad950943a538ad1c2976d5cdfe41324
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91809
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
---
 src/soc/qualcomm/x1p42100/Makefile.mk | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/soc/qualcomm/x1p42100/Makefile.mk b/src/soc/qualcomm/x1p42100/Makefile.mk
index 117b8e1e4d..dbb125aff9 100644
--- a/src/soc/qualcomm/x1p42100/Makefile.mk
+++ b/src/soc/qualcomm/x1p42100/Makefile.mk
@@ -224,7 +224,7 @@ CPUCP_FILE := $(X1P42100_BLOB)/cpucp/cpucp.elf
 CPUCP_CBFS := $(CONFIG_CBFS_PREFIX)/cpucp
 $(CPUCP_CBFS)-file := $(CPUCP_FILE)
 $(CPUCP_CBFS)-type := payload
-$(CPUCP_CBFS)-compression := $(CBFS_COMPRESS_FLAG)
+$(CPUCP_CBFS)-compression := none
 cbfs-files-y += $(CPUCP_CBFS)
 
 ################################################################################

From b42d1481711df8b3df6c54b20cb7b131aa2750aa Mon Sep 17 00:00:00 2001
From: Subrata Banik <subratabanik@google.com>
Date: Sat, 21 Mar 2026 21:39:33 +0530
Subject: [PATCH 3782/3886] soc/qualcomm/x1p42100: Define CPUCP region and map
 in MMU

The CPU Control Processor (CPUCP) requires a dedicated memory region
for firmware loading. Previously, accessing this region without
explicit MMU configuration could lead to suboptimal performance
during the transfer.

```
CPUCP Program Headers:
Type     Offset             VirtAddr           PhysAddr
         FileSiz            MemSiz              Flags  Align

LOAD     0x0000000000001000 0x000000001cb00000 0x000000001cb00000
         0x0000000000021d90 0x000000000002a630  RWE    0x1000
LOAD     0x0000000000023000 0x000000001cb2b000 0x000000001cb2b000
         0x000000000000b570 0x000000000000b570  RW     0x1000
LOAD     0x000000000002f000 0x000000001cb3e000 0x000000001cb3e000
         0x0000000000000890 0x0000000000000890  RW     0x1000
LOAD     0x0000000000000000 0x000000001cb3f000 0x000000001cb3f000
         0x0000000000000000 0x0000000000001000  RW     0x1000
```

Key changes:
- symbols_common.h: Declare the 'cpucp' region.
- memlayout.ld: Define the CPUCP region at 0x1CB00000 (size 256K)
  to align with SoC address maps.
- cpucp_load_reset.c: Map the CPUCP region as CACHED_RAM using
  mmu_config_range() before loading the firmware.
- Flush and remap back the CPUCP range to device memory.

By ensuring the region is cached during the load and reset phase,
the firmware handoff is optimized, saving approximately 20ms of
overall boot time.

BUG=b:449871690
TEST=Able to save 20ms of the boot time.

Change-Id: I769f2cb7436ebfcc07eb2748b524066281a60a6e
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91811
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
---
 .../qualcomm/common/include/soc/symbols_common.h    |  1 +
 src/soc/qualcomm/x1p42100/cpucp_load_reset.c        | 13 +++++++++++++
 src/soc/qualcomm/x1p42100/memlayout.ld              |  6 ++++++
 3 files changed, 20 insertions(+)

diff --git a/src/soc/qualcomm/common/include/soc/symbols_common.h b/src/soc/qualcomm/common/include/soc/symbols_common.h
index 847225216a..5b2cc1be11 100644
--- a/src/soc/qualcomm/common/include/soc/symbols_common.h
+++ b/src/soc/qualcomm/common/include/soc/symbols_common.h
@@ -31,6 +31,7 @@ DECLARE_REGION(dram_modem_extra)
 DECLARE_REGION(dram_wlan)
 DECLARE_REGION(dram_wpss)
 DECLARE_REGION(shrm)
+DECLARE_REGION(cpucp)
 DECLARE_REGION(dram_cpucp_dtbs)
 DECLARE_REGION(dram_cpucp)
 DECLARE_REGION(dram_modem)
diff --git a/src/soc/qualcomm/x1p42100/cpucp_load_reset.c b/src/soc/qualcomm/x1p42100/cpucp_load_reset.c
index 804c992425..274c724724 100644
--- a/src/soc/qualcomm/x1p42100/cpucp_load_reset.c
+++ b/src/soc/qualcomm/x1p42100/cpucp_load_reset.c
@@ -1,13 +1,21 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
+#include <arch/cache.h>
+#include <arch/mmu.h>
 #include <console/console.h>
 #include <program_loading.h>
 #include <soc/cpucp.h>
 #include <device/mmio.h>
 #include <soc/addressmap.h>
+#include <soc/mmu_common.h>
+#include <soc/symbols_common.h>
+#include <symbols.h>
 
 void cpucp_fw_load_reset(void)
 {
+	/* map to cached region to force address to be 4 byte aligned */
+	mmu_config_range((void *)_cpucp, REGION_SIZE(cpucp), CACHED_RAM);
+
 	struct prog cpucp_dtbs_prog =
 		PROG_INIT(PROG_PAYLOAD, CONFIG_CBFS_PREFIX "/cpucp_dtbs");
 
@@ -22,6 +30,11 @@ void cpucp_fw_load_reset(void)
 	if (!selfload(&cpucp_fw_prog))
 		die("SOC image: CPUCP load failed");
 
+	/* flush cached region */
+	dcache_clean_by_mva(_cpucp, REGION_SIZE(cpucp));
+	/* remap back to device memory */
+	mmu_config_range((void *)_cpucp, REGION_SIZE(cpucp), DEV_MEM);
+
 	printk(BIOS_DEBUG, "SOC image: CPUCP image loaded successfully.\n");
 
 	write32((void *) HWIO_APSS_CPUCP_CPUCP_LPM_SEQ_WAIT_EVT_CTRL_MASK_ADDR, 0x0);
diff --git a/src/soc/qualcomm/x1p42100/memlayout.ld b/src/soc/qualcomm/x1p42100/memlayout.ld
index 20dc57dc53..460a0e87cf 100644
--- a/src/soc/qualcomm/x1p42100/memlayout.ld
+++ b/src/soc/qualcomm/x1p42100/memlayout.ld
@@ -98,6 +98,10 @@
  *               |                         shrm                             |    SHRM
  * 0x24040000    +----------------------------------------------------------+ <---------
  *               |         ... (Memory not mapped: Unavailable) ...         | XXXXXXXXX
+ * 0x1CB40000    +----------------------------------------------------------+ <---------
+ *               |                         CPUCP                            |
+ * 0x1CB00000    +----------------------------------------------------------+ <---------
+ *               |         ... (Memory not mapped: Unavailable) ...         | XXXXXXXXX
  * 0x14A80000    +----------------------------------------------------------+ <---------
  *               |                    auth_metadata                         |      ^
  * 0x14A7E000    +----------------------------------------------------------+      |
@@ -233,6 +237,8 @@ SECTIONS
 	REGION(auth_metadata, 0x14A7E000, 8K, 4K)
 	BSRAM_END(0x14A80000)
 
+	REGION(cpucp, 0x1CB00000, 256K , 4K)
+
 	REGION(shrm, 0x24040000, 128K , 4K)
 
 	DRAM_START(0x80000000)

From cd8072191d337f83003d5f79024428961a62866d Mon Sep 17 00:00:00 2001
From: Patrick Rudolph <patrick.rudolph@9elements.com>
Date: Tue, 24 Feb 2026 09:16:23 +0100
Subject: [PATCH 3783/3886] soc/amd/common/block/psp: Get ROM Armor state from
 HSTI

Add a function to return ROM Armor state from HSTI bits.

As soon as ROM Armor is enforced never check HSTI bits again
as it cannot be deactivated without a reboot.

TEST=Function returns 0 before running command
     MBOX_BIOS_CMD_ARMOR_ENTER_SMM_MODE and returns 1 after
     sending it to PSP.

Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Change-Id: Ic9cf99b7f2461aa85fbd76998da5d035bf9e5ae3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91703
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 .../amd/common/block/include/amdblocks/psp.h  |  6 +++++
 src/soc/amd/common/block/psp/psp.c            | 27 +++++++++++++++++++
 src/soc/amd/common/block/psp/psp_def.h        |  1 +
 3 files changed, 34 insertions(+)

diff --git a/src/soc/amd/common/block/include/amdblocks/psp.h b/src/soc/amd/common/block/include/amdblocks/psp.h
index 40197396fe..5f0807870d 100644
--- a/src/soc/amd/common/block/include/amdblocks/psp.h
+++ b/src/soc/amd/common/block/include/amdblocks/psp.h
@@ -95,5 +95,11 @@ bool psp_ftpm_is_active(void);
 void psp_ftpm_needs_recovery(bool *psp_rpmc_nvram,
 			     bool *psp_nvram,
 			     bool *psp_dir);
+#if ENV_RAMSTAGE || ENV_SMM
+bool psp_get_hsti_state_rom_armor_enforced(void);
+#else
+/* ROM Armor might get activated after SMM has been set up. It's safe to return false here. */
+static inline bool psp_get_hsti_state_rom_armor_enforced(void) { return false; }
+#endif
 
 #endif /* AMD_BLOCK_PSP_H */
diff --git a/src/soc/amd/common/block/psp/psp.c b/src/soc/amd/common/block/psp/psp.c
index 98eb0f9e84..6368e028c5 100644
--- a/src/soc/amd/common/block/psp/psp.c
+++ b/src/soc/amd/common/block/psp/psp.c
@@ -101,6 +101,33 @@ enum cb_err psp_get_hsti_state(uint32_t *state)
 	return CB_SUCCESS;
 }
 
+/*
+ * Returns true if ROM Armor is enforced, that is after PSP command
+ * MBOX_BIOS_CMD_ARMOR_ENTER_SMM_MODE has been executed, false otherwise.
+ *
+ * When ROM Armor is enforced the result will be cached.
+ */
+#if ENV_RAMSTAGE || ENV_SMM
+bool psp_get_hsti_state_rom_armor_enforced(void)
+{
+	uint32_t hsti_state;
+
+	static bool enforced;
+	if (enforced)
+		return true; /* ROM Armor already enforced, no need to check again */
+
+	if (psp_get_hsti_state(&hsti_state) != CB_SUCCESS) {
+		printk(BIOS_EMERG, "PSP: Failed to get HSTI state\n");
+		return false;
+	}
+	enforced = hsti_state & HSTI_STATE_ROM_ARMOR_ENFORCED;
+	if (enforced)
+		printk(BIOS_INFO, "PSP: ROM Armor enforced\n");
+
+	return enforced;
+}
+#endif
+
 /*
  * Notify the PSP that the system is completing the boot process.  Upon
  * receiving this command, the PSP will only honor commands where the buffer
diff --git a/src/soc/amd/common/block/psp/psp_def.h b/src/soc/amd/common/block/psp/psp_def.h
index 9d60c264bf..c1513337cf 100644
--- a/src/soc/amd/common/block/psp/psp_def.h
+++ b/src/soc/amd/common/block/psp/psp_def.h
@@ -27,6 +27,7 @@
 #define MBOX_BIOS_CMD_S3_DATA_INFO		0x08
 #define MBOX_BIOS_CMD_NOP			0x09
 #define MBOX_BIOS_CMD_HSTI_QUERY		0x14
+#define  HSTI_STATE_ROM_ARMOR_ENFORCED		BIT(11)
 #define MBOX_BIOS_CMD_PSB_AUTO_FUSING		0x21
 #define MBOX_BIOS_CMD_PSP_CAPS_QUERY		0x27
 #define MBOX_BIOS_CMD_SET_SPL_FUSE		0x2d

From d72d7d1ba0e57efa27e87c73500a7f47e7acd4d2 Mon Sep 17 00:00:00 2001
From: Patrick Rudolph <patrick.rudolph@9elements.com>
Date: Tue, 24 Feb 2026 09:36:34 +0100
Subject: [PATCH 3784/3886] soc/amd/common/block/spi: Check if ROM Armor is
 enforced

Before trying to use the SPI flash controller in ramstage or SMM check
if the bus can be claimed. If ROM Armor is enabled abort claiming the
bus. Sanity check as the caller must use PSP mailbox interface when
ROM Armor is enabled.

This commit introduces SOC_AMD_COMMON_BLOCK_PSP_ROM_ARMOR3, that will
be used in the following commits to active ROM Armor support.

Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Change-Id: Id93747df92bfca46c15a1438c2804c0c574c9f99
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91704
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
---
 src/soc/amd/common/block/psp/psp.c          |  3 ++
 src/soc/amd/common/block/spi/Kconfig        | 38 +++++++++++++++++++++
 src/soc/amd/common/block/spi/fch_spi_ctrl.c |  6 ++++
 3 files changed, 47 insertions(+)

diff --git a/src/soc/amd/common/block/psp/psp.c b/src/soc/amd/common/block/psp/psp.c
index 6368e028c5..b8e908a928 100644
--- a/src/soc/amd/common/block/psp/psp.c
+++ b/src/soc/amd/common/block/psp/psp.c
@@ -112,6 +112,9 @@ bool psp_get_hsti_state_rom_armor_enforced(void)
 {
 	uint32_t hsti_state;
 
+	if (!CONFIG(SOC_AMD_COMMON_BLOCK_PSP_ROM_ARMOR3))
+		return false;
+
 	static bool enforced;
 	if (enforced)
 		return true; /* ROM Armor already enforced, no need to check again */
diff --git a/src/soc/amd/common/block/spi/Kconfig b/src/soc/amd/common/block/spi/Kconfig
index 085c02a2f6..10e88a98bb 100644
--- a/src/soc/amd/common/block/spi/Kconfig
+++ b/src/soc/amd/common/block/spi/Kconfig
@@ -132,3 +132,41 @@ config TPM_SPI_SPEED
 	    3: 16.66MHz
 	    4: 100MHz
 	    5: 800KHz
+
+config SOC_AMD_COMMON_BLOCK_PSP_ROM_ARMOR3
+	bool "Enable ROM Armor 3"
+	select BOOT_DEVICE_NOT_SPI_FLASH
+	select BOOT_DEVICE_MEMORY_MAPPED
+	select BOOT_DEVICE_SUPPORTS_WRITES
+	select SPI_FLASH
+	select SPI_FLASH_SMM
+	depends on HAVE_SMI_HANDLER
+	depends on SOC_AMD_COMMON_BLOCK_PSP
+	depends on SOC_AMD_COMMON_BLOCK_SPI
+	depends on !SOC_AMD_COMMON_BLOCK_PSP_SMI
+	help
+	  Select this option to use PSP ROM Armor3 protocol for SPI flash
+	  operations. This routes SPI read/write/erase operations through
+	  the SMM PSP firmware mailbox interface instead of direct FCH SPI
+	  controller access. After MPinit the SPI will become read only from
+	  x86 perspective and the SPI Ctrl interface will be deactived.
+
+	  You will be only able to write SPI regions that are marked 'writable' or
+	  are whitelisted by BIOS directory entries 0x6d (AMD_BIOS_NV_ST). To gain
+	  direct access to the SPI flash, you must issue a reboot.
+
+	  WARNING: Since the flash access in the SMI handler is a blocking
+	  operation during which all cores stay in SMM, an erase operation may
+	  lock up the system for a long enough time to be noticeable. Reads and
+	  writes with small data sizes are less problematic. This is AMD
+	  specific design and should be enabled when you don't want to service
+	  PSP SMI requests (see CONFIG_SOC_AMD_COMMON_BLOCK_PSP_SMI).
+
+config SOC_AMD_PSP_ROM_ARMOR_64K_ERASE
+	bool
+	depends on SOC_AMD_COMMON_BLOCK_PSP_ROM_ARMOR3
+	default n
+	help
+	  Enable 64KB erase block size support in addition to 4KB blocks.
+	  This can improve erase performance when erasing large regions.
+	  The PSP firmware must support 64KB erase commands for this to work.
diff --git a/src/soc/amd/common/block/spi/fch_spi_ctrl.c b/src/soc/amd/common/block/spi/fch_spi_ctrl.c
index 114c733244..79010a60c9 100644
--- a/src/soc/amd/common/block/spi/fch_spi_ctrl.c
+++ b/src/soc/amd/common/block/spi/fch_spi_ctrl.c
@@ -1,6 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
 #include <amdblocks/lpc.h>
+#include <amdblocks/psp.h>
 #include <amdblocks/smi.h>
 #include <amdblocks/spi.h>
 #include <console/console.h>
@@ -342,6 +343,11 @@ static int spi_ctrlr_claim_bus(const struct spi_slave *slave)
 {
 	uint8_t reg8;
 
+	if (psp_get_hsti_state_rom_armor_enforced()) {
+		printk(BIOS_ERR, "PSP ROM Armor is enforced, cannot access SPI flash directly\n");
+		return -1;
+	}
+
 	if (CONFIG(SOC_AMD_COMMON_BLOCK_PSP_SMI)) {
 		if (ENV_RAMSTAGE || ENV_SMM) {
 			reg8 = spi_read8(SPI_MISC_CNTRL);

From 28fbd247f645490d499b4bd1f1e52a3565ced64e Mon Sep 17 00:00:00 2001
From: Shon Wang <shon.wang@quanta.corp-partner.google.com>
Date: Tue, 3 Mar 2026 16:39:12 +0800
Subject: [PATCH 3785/3886] spd/lp5x: Generate initial SPD for SL5D32G32C2A-HC0

Generate initial SPD for SCY SL5D32G32C2A-HC0

BUG=b:438402880
BRANCH=firmware-nissa-15217.B
TEST=util/spd_tools/bin/spd_gen spd/lp5/memory_parts.json lp5

Change-Id: Ie0ec1ff9c2681564df1a1282d2e08bd9137d8bbe
Signed-off-by: Shon Wang <shon.wang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91518
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyle Lin <kylelinck@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
---
 spd/lp5/memory_parts.json                      | 11 +++++++++++
 spd/lp5/set-0/parts_spd_manifest.generated.txt |  1 +
 spd/lp5/set-1/parts_spd_manifest.generated.txt |  1 +
 3 files changed, 13 insertions(+)

diff --git a/spd/lp5/memory_parts.json b/spd/lp5/memory_parts.json
index a38e0ac23f..1510205023 100644
--- a/spd/lp5/memory_parts.json
+++ b/spd/lp5/memory_parts.json
@@ -467,6 +467,17 @@
             "speedMbps": 9600,
             "lp5x": true
         }
+    },
+    {
+	"name": "SL5D32G32C2A-HC0",
+        "attribs": {
+            "densityPerDieGb": 16,
+            "diesPerPackage": 2,
+            "bitWidthPerChannel": 16,
+            "ranksPerChannel": 1,
+            "speedMbps": 7500,
+            "lp5x": true
+        }
     }
     ]
 }
diff --git a/spd/lp5/set-0/parts_spd_manifest.generated.txt b/spd/lp5/set-0/parts_spd_manifest.generated.txt
index ac104fc010..bceebccba4 100644
--- a/spd/lp5/set-0/parts_spd_manifest.generated.txt
+++ b/spd/lp5/set-0/parts_spd_manifest.generated.txt
@@ -45,3 +45,4 @@ RS1G32LO5D2FDB-23BT,spd-11.hex
 BWMYAX32P8A-32G,spd-7.hex
 MT62F2G32D4DS-020 WT:D,spd-10.hex
 H58G56DK9BX068,spd-14.hex
+SL5D32G32C2A-HC0,spd-7.hex
diff --git a/spd/lp5/set-1/parts_spd_manifest.generated.txt b/spd/lp5/set-1/parts_spd_manifest.generated.txt
index ac104fc010..bceebccba4 100644
--- a/spd/lp5/set-1/parts_spd_manifest.generated.txt
+++ b/spd/lp5/set-1/parts_spd_manifest.generated.txt
@@ -45,3 +45,4 @@ RS1G32LO5D2FDB-23BT,spd-11.hex
 BWMYAX32P8A-32G,spd-7.hex
 MT62F2G32D4DS-020 WT:D,spd-10.hex
 H58G56DK9BX068,spd-14.hex
+SL5D32G32C2A-HC0,spd-7.hex

From d43421da65171a4d1f7236a1455331fa888b71af Mon Sep 17 00:00:00 2001
From: Shon Wang <shon.wang@quanta.corp-partner.google.com>
Date: Tue, 3 Mar 2026 16:44:51 +0800
Subject: [PATCH 3786/3886] mb/google/nissa/var/quandiso: Generate RAM ID for
 SL5D32G32C2A-HC0

Generate RAM ID for SCY SL5D32G32C2A-HC0

DRAM Part Name                 ID to assign
SL5D32G32C2A-HC0                3 (0011)

BUG=b:438402880
BRANCH=firmware-nissa-15217.B
TEST=emerge-nissa coreboot then check device boot

Change-Id: I354b950022cf05f69546d4c3d29f05981512ce51
Signed-off-by: Shon Wang <shon.wang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91519
Reviewed-by: Kyle Lin <kylelinck@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/google/brya/variants/quandiso/memory/Makefile.mk  | 2 +-
 .../google/brya/variants/quandiso/memory/dram_id.generated.txt  | 1 +
 .../google/brya/variants/quandiso/memory/mem_parts_used.txt     | 1 +
 3 files changed, 3 insertions(+), 1 deletion(-)

diff --git a/src/mainboard/google/brya/variants/quandiso/memory/Makefile.mk b/src/mainboard/google/brya/variants/quandiso/memory/Makefile.mk
index 6c970ad89e..084dea1af0 100644
--- a/src/mainboard/google/brya/variants/quandiso/memory/Makefile.mk
+++ b/src/mainboard/google/brya/variants/quandiso/memory/Makefile.mk
@@ -7,7 +7,7 @@ SPD_SOURCES =
 SPD_SOURCES += spd/lp5/set-0/spd-1.hex      # ID = 0(0b0000)  Parts = MT62F512M32D2DR-031 WT:B, H9JCNNNBK3MLYR-N6E
 SPD_SOURCES += spd/lp5/set-0/spd-2.hex      # ID = 1(0b0001)  Parts = MT62F1G32D4DR-031 WT:B
 SPD_SOURCES += spd/lp5/set-0/spd-3.hex      # ID = 2(0b0010)  Parts = H58G56AK6BX069, K3LKBKB0BM-MGCP
-SPD_SOURCES += spd/lp5/set-0/spd-7.hex      # ID = 3(0b0011)  Parts = H58G56BK7BX068, MT62F1G32D2DS-026 WT:B, K3KL8L80CM-MGCT, BWMYAX32P8A-32G
+SPD_SOURCES += spd/lp5/set-0/spd-7.hex      # ID = 3(0b0011)  Parts = H58G56BK7BX068, MT62F1G32D2DS-026 WT:B, K3KL8L80CM-MGCT, BWMYAX32P8A-32G, SL5D32G32C2A-HC0
 SPD_SOURCES += spd/lp5/set-0/spd-8.hex      # ID = 4(0b0100)  Parts = H58G66BK7BX067, MT62F2G32D4DS-026 WT:B, K3KL9L90CM-MGCT
 SPD_SOURCES += spd/lp5/set-0/spd-6.hex      # ID = 5(0b0101)  Parts = H58G66AK6BX070
 SPD_SOURCES += spd/lp5/set-0/spd-9.hex      # ID = 6(0b0110)  Parts = K3KL6L60GM-MGCT
diff --git a/src/mainboard/google/brya/variants/quandiso/memory/dram_id.generated.txt b/src/mainboard/google/brya/variants/quandiso/memory/dram_id.generated.txt
index 275125f0d2..25bb8227e8 100644
--- a/src/mainboard/google/brya/variants/quandiso/memory/dram_id.generated.txt
+++ b/src/mainboard/google/brya/variants/quandiso/memory/dram_id.generated.txt
@@ -22,3 +22,4 @@ H58G56CK8BX146                 7 (0111)
 K3KL8L80EM-MGCU                7 (0111)
 MT62F512M32D1DS-023 WT:E       7 (0111)
 BWMYAX32P8A-32G                3 (0011)
+SL5D32G32C2A-HC0               3 (0011)
diff --git a/src/mainboard/google/brya/variants/quandiso/memory/mem_parts_used.txt b/src/mainboard/google/brya/variants/quandiso/memory/mem_parts_used.txt
index 1570fe8962..5cdb4a05fa 100644
--- a/src/mainboard/google/brya/variants/quandiso/memory/mem_parts_used.txt
+++ b/src/mainboard/google/brya/variants/quandiso/memory/mem_parts_used.txt
@@ -27,3 +27,4 @@ H58G56CK8BX146
 K3KL8L80EM-MGCU
 MT62F512M32D1DS-023 WT:E
 BWMYAX32P8A-32G
+SL5D32G32C2A-HC0

From 4320fe713abdf8999fe1cceabd5ce91fd3dbcebd Mon Sep 17 00:00:00 2001
From: Shon Wang <shon.wang@quanta.corp-partner.google.com>
Date: Mon, 16 Mar 2026 09:36:13 +0800
Subject: [PATCH 3787/3886] mb/google/brask/var/constitution: Generate RAM ID
 for Samsung K4UBE3D4AA-MGCR

Generate RAM ID for Samsung K4UBE3D4AA-MGCR

DRAM Part Name                 ID to assign
K4UBE3D4AA-MGCR                  1 (0001)

BUG=b:420797833
BRANCH=firmware-brya-14505.B
TEST=emerge-constitution coreboot then check device boot

Change-Id: I9751baeec16d460b4d2b0de9158940e785ccf0ef
Signed-off-by: Shon Wang <shon.wang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91681
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 .../google/brya/variants/constitution/memory/Makefile.mk        | 2 +-
 .../brya/variants/constitution/memory/dram_id.generated.txt     | 1 +
 .../google/brya/variants/constitution/memory/mem_parts_used.txt | 1 +
 3 files changed, 3 insertions(+), 1 deletion(-)

diff --git a/src/mainboard/google/brya/variants/constitution/memory/Makefile.mk b/src/mainboard/google/brya/variants/constitution/memory/Makefile.mk
index da2ad15bbc..d5dfd9c8a5 100644
--- a/src/mainboard/google/brya/variants/constitution/memory/Makefile.mk
+++ b/src/mainboard/google/brya/variants/constitution/memory/Makefile.mk
@@ -5,5 +5,5 @@
 
 SPD_SOURCES =
 SPD_SOURCES += spd/lp4x/set-0/spd-1.hex      # ID = 0(0b0000)  Parts = K4U6E3S4AB-MGCL
-SPD_SOURCES += spd/lp4x/set-0/spd-3.hex      # ID = 1(0b0001)  Parts = MT53E1G32D2NP-046 WT:B, K4UBE3D4AB-MGCL, H54G56CYRBX247
+SPD_SOURCES += spd/lp4x/set-0/spd-3.hex      # ID = 1(0b0001)  Parts = MT53E1G32D2NP-046 WT:B, K4UBE3D4AB-MGCL, H54G56CYRBX247, K4UBE3D4AA-MGCR
 SPD_SOURCES += spd/lp4x/set-0/spd-10.hex      # ID = 2(0b0010)  Parts = B3221XM3BDGVI
diff --git a/src/mainboard/google/brya/variants/constitution/memory/dram_id.generated.txt b/src/mainboard/google/brya/variants/constitution/memory/dram_id.generated.txt
index f7b781c8cb..8670771de3 100644
--- a/src/mainboard/google/brya/variants/constitution/memory/dram_id.generated.txt
+++ b/src/mainboard/google/brya/variants/constitution/memory/dram_id.generated.txt
@@ -9,3 +9,4 @@ MT53E1G32D2NP-046 WT:B         1 (0001)
 K4UBE3D4AB-MGCL                1 (0001)
 H54G56CYRBX247                 1 (0001)
 B3221XM3BDGVI                  2 (0010)
+K4UBE3D4AA-MGCR                1 (0001)
diff --git a/src/mainboard/google/brya/variants/constitution/memory/mem_parts_used.txt b/src/mainboard/google/brya/variants/constitution/memory/mem_parts_used.txt
index 2fc4149f79..60a70eb48f 100644
--- a/src/mainboard/google/brya/variants/constitution/memory/mem_parts_used.txt
+++ b/src/mainboard/google/brya/variants/constitution/memory/mem_parts_used.txt
@@ -3,3 +3,4 @@ MT53E1G32D2NP-046 WT:B
 K4UBE3D4AB-MGCL
 H54G56CYRBX247
 B3221XM3BDGVI
+K4UBE3D4AA-MGCR

From 6f7f27e6c13b06ca355355d4aace671955b09a60 Mon Sep 17 00:00:00 2001
From: Kapil Porwal <kapilporwal@google.com>
Date: Thu, 5 Mar 2026 14:26:29 +0530
Subject: [PATCH 3788/3886] soc/qualcomm: Relocate translation tables to DRAM

On Qualcomm SoCs, the initial TTB is often placed in IMEM. During
ROMSTAGE, once DRAM is initialized and stable, the tables should be
moved to DRAM to ensure they remain accessible if IMEM is reclaimed
by other hardware blocks (like the ADSP).

Trigger mmu_relocate_ttb() at the end of the post-DRAM MMU
configuration flow.

BUG=b:436391478
TEST=Verify TTB moves to DRAM on Google/Quartz.

Debug logs:
```
[INFO ]  Relocating TTB: 0x14842000 -> 0x80010000 (offset 0x6b7ce000)
[INFO ]  TTB relocation is complete.
```

Change-Id: I123385e6cdd319c5ad4d3e7b266c506e7d2d5530
Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91565
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
---
 src/soc/qualcomm/common/mmu.c | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/src/soc/qualcomm/common/mmu.c b/src/soc/qualcomm/common/mmu.c
index c3f89a24c1..9a433ee976 100644
--- a/src/soc/qualcomm/common/mmu.c
+++ b/src/soc/qualcomm/common/mmu.c
@@ -82,4 +82,8 @@ void qc_mmu_dram_config_post_dram_init(size_t ddr_size)
 
 	if (REGION_SIZE(framebuffer))
 		mmu_config_range((void *)_framebuffer, REGION_SIZE(framebuffer), UNCACHED_RAM);
+
+	/* Do not call mmu_config_range() after this point. */
+	if (_preram_ttb != _postram_ttb)
+		mmu_relocate_ttb();
 }

From da362769554a7a1985139392631dcbfd8b3e1b94 Mon Sep 17 00:00:00 2001
From: Patrick Rudolph <patrick.rudolph@amd.com>
Date: Mon, 23 Feb 2026 12:10:17 +0100
Subject: [PATCH 3789/3886] smbios: Add smbios_cache_speed() implementation

Allow the SoC the specify the cache speed. Currently it's
always set to 0, which is unknown.

Change-Id: I317e248104c0026b7cca10b949fd47fba35b7338
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91387
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
---
 src/include/smbios.h | 1 +
 src/lib/smbios.c     | 7 ++++++-
 2 files changed, 7 insertions(+), 1 deletion(-)

diff --git a/src/include/smbios.h b/src/include/smbios.h
index 103e85b9af..b42140cb5a 100644
--- a/src/include/smbios.h
+++ b/src/include/smbios.h
@@ -104,6 +104,7 @@ unsigned int smbios_processor_family(struct cpuid_result res);
 unsigned int smbios_cache_error_correction_type(u8 level);
 unsigned int smbios_cache_sram_type(void);
 unsigned int smbios_cache_conf_operation_mode(u8 level);
+u8 smbios_cache_speed(u8 level);
 
 /* Used by mainboard to add port information of type 8 */
 struct port_information;
diff --git a/src/lib/smbios.c b/src/lib/smbios.c
index 35b4d7765f..ab563e2012 100644
--- a/src/lib/smbios.c
+++ b/src/lib/smbios.c
@@ -445,6 +445,11 @@ unsigned int __weak smbios_cache_conf_operation_mode(u8 level)
 	return SMBIOS_CACHE_OP_MODE_UNKNOWN; /* Unknown */
 }
 
+u8 __weak smbios_cache_speed(u8 level)
+{
+	return 0; /* Unknown */
+}
+
 /* Returns the processor voltage in 100mV units */
 unsigned int __weak smbios_cpu_get_voltage(void)
 {
@@ -583,7 +588,7 @@ int smbios_write_type7(unsigned long *current,
 	t->associativity = associativity;
 	t->supported_sram_type = sram_type;
 	t->current_sram_type = sram_type;
-	t->cache_speed = 0; /* Unknown */
+	t->cache_speed = smbios_cache_speed(level);
 	t->error_correction_type = smbios_cache_error_correction_type(level);
 	t->system_cache_type = type;
 

From 94dd3f3bba296822ecef6e8470f4e641dbaeb5e2 Mon Sep 17 00:00:00 2001
From: Subrata Banik <subratabanik@google.com>
Date: Mon, 23 Mar 2026 14:06:44 +0530
Subject: [PATCH 3790/3886] soc/qualcomm/x1p42100: Increase boot CPU frequency
 to 3.0GHz

Boost the initial CPU frequency from 1.36GHz to ~3.0GHz (2995.2 MHz)
during the boot phase to reduce the execution time of ramstage
and subsequent payload loading.

Changes:
- clock.h: Add L_VAL_2995P2MHz (0x9C) based on a 19.2MHz XO.
- clock.c: Update speed_up_boot_cpu() to use the 3.0GHz PLL
  multiplier for the APSS NCC0 clock.

This change helps in further optimizing the boot timeline,
leveraging the higher clock speed for faster initialization.

BUG=b:449871690
TEST=Able to save ~50ms of the boot time (mostly during Qclib).

Change-Id: I459001717298b10201c3b3c8bf6b0c20097ae830
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91818
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jayvik Desai <jayvik@google.com>
---
 src/soc/qualcomm/x1p42100/clock.c             | 6 +++---
 src/soc/qualcomm/x1p42100/include/soc/clock.h | 1 +
 2 files changed, 4 insertions(+), 3 deletions(-)

diff --git a/src/soc/qualcomm/x1p42100/clock.c b/src/soc/qualcomm/x1p42100/clock.c
index 76e964831f..9adbe230d1 100644
--- a/src/soc/qualcomm/x1p42100/clock.c
+++ b/src/soc/qualcomm/x1p42100/clock.c
@@ -697,9 +697,9 @@ void enable_disp_clock_tcsr(void)
 
 static void speed_up_boot_cpu(void)
 {
-	/* 1363.2 MHz */
-	if (!pll_init_and_set(apss_ncc0, L_VAL_1363P2MHz))
-		printk(BIOS_DEBUG, "NCC Frequency bumped to 1.363(GHz)\n");
+	/* 3 GHz */
+	if (!pll_init_and_set(apss_ncc0, L_VAL_2995P2MHz))
+		printk(BIOS_DEBUG, "NCC Frequency bumped to 3.0(GHz)\n");
 }
 
 void clock_init(void)
diff --git a/src/soc/qualcomm/x1p42100/include/soc/clock.h b/src/soc/qualcomm/x1p42100/include/soc/clock.h
index 474852940b..934c0fdb34 100644
--- a/src/soc/qualcomm/x1p42100/include/soc/clock.h
+++ b/src/soc/qualcomm/x1p42100/include/soc/clock.h
@@ -19,6 +19,7 @@
 #define CLK_37_5MHZ		(37.5 * MHz)
 
 /* CPU PLL*/
+#define L_VAL_2995P2MHz		0x9C
 #define L_VAL_1363P2MHz		0x47
 #define L_VAL_806MHz		0x2A
 

From 1c6f4618b6e2123cf78e3e0a9ab69d39b194e2a8 Mon Sep 17 00:00:00 2001
From: Kapil Porwal <kapilporwal@google.com>
Date: Tue, 24 Mar 2026 14:41:58 +0530
Subject: [PATCH 3791/3886] mb/google/bluey: Allow charger behind DAM

To support chargers connected through a Debug Accessory Mode (DAM)
cable, the PMIC must be configured to allow legacy charging paths even
when a debug accessory is detected.

Update the charging initialization to clear the suspend bit in the
SCHG_TYPE_C_SUSPEND_LEGACY_CHARGERS register. This ensures the SMB2360
can correctly negotiate and draw power when a DAM cable is in use.

BUG=none
TEST=Verify SMB2360 charging configuration on Google/Quartz.

Change-Id: I8d22abf92f4e8967efbe2ee3320c4a1461d6ef88
Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91832
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jayvik Desai <jayvik@google.com>
---
 src/mainboard/google/bluey/charging.c | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/src/mainboard/google/bluey/charging.c b/src/mainboard/google/bluey/charging.c
index e567b68575..c8b1126a42 100644
--- a/src/mainboard/google/bluey/charging.c
+++ b/src/mainboard/google/bluey/charging.c
@@ -25,6 +25,9 @@
 #define SCHG_TYPE_C_TYPE_C_DEBUG_ACCESS_SRC_CFG 0x2B4C
 #define SMB1_SCHG_TYPE_C_TYPE_C_DEBUG_ACCESS_SRC_CFG \
 ((SMB1_SLAVE_ID << 16) | SCHG_TYPE_C_TYPE_C_DEBUG_ACCESS_SRC_CFG)
+#define SCHG_TYPE_C_SUSPEND_LEGACY_CHARGERS 0x2B90
+#define SMB1_SCHG_TYPE_C_SUSPEND_LEGACY_CHARGERS \
+((SMB1_SLAVE_ID << 16) | SCHG_TYPE_C_SUSPEND_LEGACY_CHARGERS)
 #define SCHG_CHGR_CHARGING_FCC 0x260A
 #define SMB1_CHGR_CHARGING_FCC ((SMB1_SLAVE_ID << 16) | SCHG_CHGR_CHARGING_FCC)
 #define SMB2_CHGR_CHARGING_FCC ((SMB2_SLAVE_ID << 16) | SCHG_CHGR_CHARGING_FCC)
@@ -33,6 +36,7 @@
 #define FCC_DISABLE 0x8c
 #define EN_DEBUG_ACCESS_SNK 0x1B
 #define EN_DEBUG_ACCESS_SRC 0x01
+#define EN_SWITCHER_DAM_500 0x05
 
 #define PMC8380F_SLAVE_ID	0x05
 #define GPIO07_MODE_CTL			0x8E40
@@ -234,6 +238,7 @@ void configure_debug_access_port(void)
 	printk(BIOS_INFO, "Enable support of source and sink modes for debug access port\n");
 	spmi_write8(SMB1_SCHG_TYPE_C_TYPE_C_DEBUG_ACCESS_SRC_CFG, EN_DEBUG_ACCESS_SRC);
 	spmi_write8(SMB1_SCHG_TYPE_C_TYPE_C_DEBUG_ACCESS_SNK_CFG, EN_DEBUG_ACCESS_SNK);
+	spmi_write8(SMB1_SCHG_TYPE_C_SUSPEND_LEGACY_CHARGERS, EN_SWITCHER_DAM_500);
 }
 
 /*

From 2e3e690023aeb1679509a008d34dbf2e3f44fe77 Mon Sep 17 00:00:00 2001
From: Hari L <haril@qualcomm.corp-partner.google.com>
Date: Tue, 3 Mar 2026 15:31:53 +0530
Subject: [PATCH 3792/3886] soc/qualcomm/x1p42100: Support to load ADSP Lite
 firmware
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

ADSP Lite firmware along with its corresponding DTB must be loaded from coreboot to allow the LPASS/ADSP subsystem to initialize correctly.ADSP lite firmware supports off-mode charging.

This patch adds support to load the ADSP DTB and ADSP firmware images
on the X1P42100 platform. The register programming details required
for loading ADSP are derived from the HRD-X1P42100-S1 document.

Reference:
https://docs.qualcomm.com/bundle/resource/topics/HRD-X1P42100-S1/

TEST=1. Create an image.serial.bin and ensure it boots on X1P42100.
     2. Verified using ADSP load log from coreboot showing successful
        loading of ADSP DTB and ADSP firmware:
        'SOC:LPASS/ADSP image loaded successfully'

Logs:

[INFO ]  Initializing devices...
[DEBUG]  Root Device init
[DEBUG]  Starting cbfs_boot_device
[DEBUG]  FMAP: area FW_MAIN_A found @ c30000 (8904448 bytes)
[INFO ]  CBFS: Found 'fallback/adsp_dtbs' @0x237200 size 0x10794 in mcache @0x8669d794
[DEBUG]  Starting cbfs_boot_device
[INFO ]  CBFS: Found 'fallback/adsp_dtbs' @0x237200 size 0x10794 in mcache @0x8669d794
[DEBUG]  read SPI 0xe67258 0x10794: 3662 us, 18425 KB/s, 147.400 Mbps
[INFO ]  VB2:vb2_secdata_kernel_get() VB2_SECDATA_KERNEL_FLAGS not supported for secdata_kernel v0, return 0
[INFO ]  VB2:vb2_digest_init() 67476 bytes, hash algo 2, HW acceleration forbidden
[DEBUG]  Loading segment from ROM address 0x9f800000
[DEBUG]    code (compression=0)
[DEBUG]    New segment dstaddr 0x866c0000 memsize 0x1075c srcaddr 0x9f800038 filesize 0x1075c
[DEBUG]  Loading Segment: addr: 0x866c0000 memsz: 0x000000000001075c filesz: 0x000000000001075c
[DEBUG]  it's not compressed!
[SPEW ]  [ 0x866c0000, 866d075c, 0x866d075c) <- 9f800038
[DEBUG]  Loading segment from ROM address 0x9f80001c
[DEBUG]    Entry Point 0x866c0000
[SPEW ]  Loaded segments
[DEBUG]  Starting cbfs_boot_device
[INFO ]  CBFS: Found 'fallback/adsp_lite' @0xe7ac0 size 0x14f6aa in mcache @0x8669d73c
[DEBUG]  read SPI 0xd17b18 0x14f6aa: 74126 us, 18534 KB/s, 148.272 Mbps
[INFO ]  VB2:vb2_secdata_kernel_get() VB2_SECDATA_KERNEL_FLAGS not supported for secdata_kernel v0, return 0
[INFO ]  VB2:vb2_digest_init() 1373866 bytes, hash algo 2, HW acceleration forbidden
[DEBUG]  Loading segment from ROM address 0x9f800000
[DEBUG]    code (compression=1)
[DEBUG]    New segment dstaddr 0x86b00000 memsize 0x5000 srcaddr 0x9f800268 filesize 0x2072
[DEBUG]  Loading Segment: addr: 0x86b00000 memsz: 0x0000000000005000 filesz: 0x0000000000002072
[DEBUG]  using LZMA
[SPEW ]  [ 0x86b00000, 86b04620, 0x86b05000) <- 9f800268
[DEBUG]  Clearing Segment: addr: 0x0000000086b04620 memsz: 0x00000000000009e0
[DEBUG]  Loading segment from ROM address 0x9f80001c
[DEBUG]    data (compression=1)
[DEBUG]    New segment dstaddr 0x86b05000 memsize 0x240000 srcaddr 0x9f8022da filesize 0x6cf
[DEBUG]  Loading Segment: addr: 0x86b05000 memsz: 0x0000000000240000 filesz: 0x00000000000006cf
[DEBUG]  using LZMA
[SPEW ]  [ 0x86b05000, 86b14ffc, 0x86d45000) <- 9f8022da
[DEBUG]  Clearing Segment: addr: 0x0000000086b14ffc memsz: 0x0000000000230004
[DEBUG]  Loading segment from ROM address 0x9f800038
[DEBUG]    code (compression=1)
[DEBUG]    New segment dstaddr 0x86d45000 memsize 0x12000 srcaddr 0x9f8029a9 filesize 0xa2d6
[DEBUG]  Loading Segment: addr: 0x86d45000 memsz: 0x0000000000012000 filesz: 0x000000000000a2d6
[DEBUG]  using LZMA
[SPEW ]  [ 0x86d45000, 86d567dc, 0x86d57000) <- 9f8029a9
[DEBUG]  Clearing Segment: addr: 0x0000000086d567dc memsz: 0x0000000000000824
[DEBUG]  Loading segment from ROM address 0x9f800054
[DEBUG]    code (compression=1)
[DEBUG]    New segment dstaddr 0x86d57000 memsize 0x7000 srcaddr 0x9f80cc7f filesize 0x3c6c
[DEBUG]  Loading Segment: addr: 0x86d57000 memsz: 0x0000000000007000 filesz: 0x0000000000003c6c
[DEBUG]  using LZMA
[SPEW ]  [ 0x86d57000, 86d5da34, 0x86d5e000) <- 9f80cc7f
[DEBUG]  Clearing Segment: addr: 0x0000000086d5da34 memsz: 0x00000000000005cc
[DEBUG]  Loading segment from ROM address 0x9f800070
[DEBUG]    code (compression=1)
[DEBUG]    New segment dstaddr 0x86d5e000 memsize 0x8000 srcaddr 0x9f8108eb filesize 0x538
[DEBUG]  Loading Segment: addr: 0x86d5e000 memsz: 0x0000000000008000 filesz: 0x0000000000000538
[DEBUG]  using LZMA
[SPEW ]  [ 0x86d5e000, 86d65850, 0x86d66000) <- 9f8108eb
[DEBUG]  Clearing Segment: addr: 0x0000000086d65850 memsz: 0x00000000000007b0
[DEBUG]  Loading segment from ROM address 0x9f80008c
[DEBUG]    code (compression=1)
[DEBUG]    New segment dstaddr 0x86d70000 memsize 0x1000 srcaddr 0x9f810e23 filesize 0xc4
[DEBUG]  Loading Segment: addr: 0x86d70000 memsz: 0x0000000000001000 filesz: 0x00000000000000c4
[DEBUG]  using LZMA
[SPEW ]  [ 0x86d70000, 86d700f0, 0x86d71000) <- 9f810e23
[DEBUG]  Clearing Segment: addr: 0x0000000086d700f0 memsz: 0x0000000000000f10
[DEBUG]  Loading segment from ROM address 0x9f8000a8
[DEBUG]    data (compression=1)
[DEBUG]    New segment dstaddr 0x86d71000 memsize 0x3000 srcaddr 0x9f810ee7 filesize 0x4b1
[DEBUG]  Loading Segment: addr: 0x86d71000 memsz: 0x0000000000003000 filesz: 0x00000000000004b1
[DEBUG]  using LZMA
[SPEW ]  [ 0x86d71000, 86d7384c, 0x86d74000) <- 9f810ee7
[DEBUG]  Clearing Segment: addr: 0x0000000086d7384c memsz: 0x00000000000007b4
[DEBUG]  Loading segment from ROM address 0x9f8000c4
[DEBUG]    code (compression=1)
[DEBUG]    New segment dstaddr 0x86d74000 memsize 0x192000 srcaddr 0x9f811398 filesize 0xafc41
[DEBUG]  Loading Segment: addr: 0x86d74000 memsz: 0x0000000000192000 filesz: 0x00000000000afc41
[DEBUG]  using LZMA
[SPEW ]  [ 0x86d74000, 86f054a4, 0x86f06000) <- 9f811398
[DEBUG]  Clearing Segment: addr: 0x0000000086f054a4 memsz: 0x0000000000000b5c
[DEBUG]  Loading segment from ROM address 0x9f8000e0
[DEBUG]    data (compression=1)
[DEBUG]    New segment dstaddr 0x86f06000 memsize 0x375000 srcaddr 0x9f8c0fd9 filesize 0xb722
[DEBUG]  Loading Segment: addr: 0x86f06000 memsz: 0x0000000000375000 filesz: 0x000000000000b722
[DEBUG]  using LZMA
[SPEW ]  [ 0x86f06000, 86f7392c, 0x8727b000) <- 9f8c0fd9
[DEBUG]  Clearing Segment: addr: 0x0000000086f7392c memsz: 0x00000000003076d4
[DEBUG]  Loading segment from ROM address 0x9f8000fc
[DEBUG]    data (compression=1)
[DEBUG]    New segment dstaddr 0x8727b000 memsize 0x1000 srcaddr 0x9f8cc6fb filesize 0x1d
[DEBUG]  Loading Segment: addr: 0x8727b000 memsz: 0x0000000000001000 filesz: 0x000000000000001d
[DEBUG]  using LZMA
[SPEW ]  [ 0x8727b000, 8727b2a0, 0x8727c000) <- 9f8cc6fb
[DEBUG]  Clearing Segment: addr: 0x000000008727b2a0 memsz: 0x0000000000000d60
[DEBUG]  Loading segment from ROM address 0x9f800118
[DEBUG]    data (compression=1)
[DEBUG]    New segment dstaddr 0x8727c000 memsize 0x15000 srcaddr 0x9f8cc718 filesize 0x3d04
[DEBUG]  Loading Segment: addr: 0x8727c000 memsz: 0x0000000000015000 filesz: 0x0000000000003d04
[DEBUG]  using LZMA
[SPEW ]  [ 0x8727c000, 8729023c, 0x87291000) <- 9f8cc718
[DEBUG]  Clearing Segment: addr: 0x000000008729023c memsz: 0x0000000000000dc4
[DEBUG]  Loading segment from ROM address 0x9f800134
[DEBUG]    data (compression=1)
[DEBUG]    New segment dstaddr 0x87291000 memsize 0x1000 srcaddr 0x9f8d041c filesize 0x16c
[DEBUG]  Loading Segment: addr: 0x87291000 memsz: 0x0000000000001000 filesz: 0x000000000000016c
[DEBUG]  using LZMA
[SPEW ]  [ 0x87291000, 87291587, 0x87292000) <- 9f8d041c
[DEBUG]  Clearing Segment: addr: 0x0000000087291587 memsz: 0x0000000000000a79
[DEBUG]  Loading segment from ROM address 0x9f800150
[DEBUG]    data (compression=1)
[DEBUG]    New segment dstaddr 0x87292000 memsize 0x24600 srcaddr 0x9f8d0588 filesize 0x52c
[DEBUG]  Loading Segment: addr: 0x87292000 memsz: 0x0000000000024600 filesz: 0x000000000000052c
[DEBUG]  using LZMA
[SPEW ]  [ 0x87292000, 872b6600, 0x872b6600) <- 9f8d0588
[DEBUG]  Loading segment from ROM address 0x9f80016c
[DEBUG]    data (compression=1)
[DEBUG]    New segment dstaddr 0x872b6600 memsize 0x2a00 srcaddr 0x9f8d0ab4 filesize 0xef0
[DEBUG]  Loading Segment: addr: 0x872b6600 memsz: 0x0000000000002a00 filesz: 0x0000000000000ef0
[DEBUG]  using LZMA
[SPEW ]  [ 0x872b6600, 872b8de9, 0x872b9000) <- 9f8d0ab4
[DEBUG]  Clearing Segment: addr: 0x00000000872b8de9 memsz: 0x0000000000000217
[DEBUG]  Loading segment from ROM address 0x9f800188
[DEBUG]    data (compression=1)
[DEBUG]    New segment dstaddr 0x872b9000 memsize 0x6c srcaddr 0x9f8d19a4 filesize 0x4b
[DEBUG]  Loading Segment: addr: 0x872b9000 memsz: 0x000000000000006c filesz: 0x000000000000004b
[DEBUG]  using LZMA
[SPEW ]  [ 0x872b9000, 872b906c, 0x872b906c) <- 9f8d19a4
[DEBUG]  Loading segment from ROM address 0x9f8001a4
[DEBUG]    code (compression=1)
[DEBUG]    New segment dstaddr 0x872b906c memsize 0x1cf94 srcaddr 0x9f8d19ef filesize 0xffcc
[DEBUG]  Loading Segment: addr: 0x872b906c memsz: 0x000000000001cf94 filesz: 0x000000000000ffcc
[DEBUG]  using LZMA
[SPEW ]  [ 0x872b906c, 872d5368, 0x872d6000) <- 9f8d19ef
[DEBUG]  Clearing Segment: addr: 0x00000000872d5368 memsz: 0x0000000000000c98
[DEBUG]  Loading segment from ROM address 0x9f8001c0
[DEBUG]    code (compression=1)
[DEBUG]    New segment dstaddr 0x872e0000 memsize 0x1e0000 srcaddr 0x9f8e19bb filesize 0x62e09
[DEBUG]  Loading Segment: addr: 0x872e0000 memsz: 0x00000000001e0000 filesz: 0x0000000000062e09
[DEBUG]  using LZMA
[SPEW ]  [ 0x872e0000, 874bf3c4, 0x874c0000) <- 9f8e19bb
[DEBUG]  Clearing Segment: addr: 0x00000000874bf3c4 memsz: 0x0000000000000c3c
[DEBUG]  Loading segment from ROM address 0x9f8001dc
[DEBUG]    data (compression=1)
[DEBUG]    New segment dstaddr 0x874c0000 memsize 0xef000 srcaddr 0x9f9447c4 filesize 0xd8f
[DEBUG]  Loading Segment: addr: 0x874c0000 memsz: 0x00000000000ef000 filesz: 0x0000000000000d8f
[DEBUG]  using LZMA
[SPEW ]  [ 0x874c0000, 874c4130, 0x875af000) <- 9f9447c4
[DEBUG]  Clearing Segment: addr: 0x00000000874c4130 memsz: 0x00000000000eaed0
[DEBUG]  Loading segment from ROM address 0x9f8001f8
[DEBUG]    data (compression=1)
[DEBUG]    New segment dstaddr 0x875af000 memsize 0x1000 srcaddr 0x9f945553 filesize 0x3a
[DEBUG]  Loading Segment: addr: 0x875af000 memsz: 0x0000000000001000 filesz: 0x000000000000003a
[DEBUG]  using LZMA
[SPEW ]  [ 0x875af000, 875af078, 0x875b0000) <- 9f945553
[DEBUG]  Clearing Segment: addr: 0x00000000875af078 memsz: 0x0000000000000f88
[DEBUG]  Loading segment from ROM address 0x9f800214
[DEBUG]    data (compression=1)
[DEBUG]    New segment dstaddr 0x875b0000 memsize 0x4f000 srcaddr 0x9f94558d filesize 0xa11d
[DEBUG]  Loading Segment: addr: 0x875b0000 memsz: 0x000000000004f000 filesz: 0x000000000000a11d
[DEBUG]  using LZMA
[SPEW ]  [ 0x875b0000, 875fefd4, 0x875ff000) <- 9f94558d
[DEBUG]  Clearing Segment: addr: 0x00000000875fefd4 memsz: 0x000000000000002c
[DEBUG]  Loading segment from ROM address 0x9f800230
[DEBUG]    BSS 0x875ff000 (1052672 byte)
[DEBUG]  Loading Segment: addr: 0x875ff000 memsz: 0x0000000000101000 filesz: 0x0000000000000000
[DEBUG]  it's not compressed!
[SPEW ]  [ 0x875ff000, 875ff000, 0x87700000) <- 9f94f6aa
[DEBUG]  Clearing Segment: addr: 0x00000000875ff000 memsz: 0x0000000000101000
[DEBUG]  Loading segment from ROM address 0x9f80024c
[DEBUG]    Entry Point 0x86b00000
[SPEW ]  Loaded segments
[INFO] SOC: LPASS/ADSP image loaded successfully

Change-Id: I04ebd71bc06c971a39f0d4ae9fe299a64dfaaff8
Signed-off-by: Hari L <haril@qualcomm.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91520
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Jayvik Desai <jayvik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
---
 src/soc/qualcomm/x1p42100/Makefile.mk         |  18 +++
 src/soc/qualcomm/x1p42100/adsp_load_reset.c   | 119 ++++++++++++++++++
 .../x1p42100/include/soc/addressmap.h         |   2 +
 src/soc/qualcomm/x1p42100/include/soc/adsp.h  |  40 ++++++
 .../x1p42100/include/soc/platform_info.h      |  53 ++++++++
 5 files changed, 232 insertions(+)
 create mode 100644 src/soc/qualcomm/x1p42100/adsp_load_reset.c
 create mode 100644 src/soc/qualcomm/x1p42100/include/soc/adsp.h
 create mode 100644 src/soc/qualcomm/x1p42100/include/soc/platform_info.h

diff --git a/src/soc/qualcomm/x1p42100/Makefile.mk b/src/soc/qualcomm/x1p42100/Makefile.mk
index dbb125aff9..cfb8410e60 100644
--- a/src/soc/qualcomm/x1p42100/Makefile.mk
+++ b/src/soc/qualcomm/x1p42100/Makefile.mk
@@ -56,6 +56,7 @@ ramstage-$(CONFIG_PCI) += ../common/pcie_common.c
 ramstage-y += ../common/spmi.c
 ramstage-$(CONFIG_PCI) += pcie.c
 ramstage-y += cpucp_load_reset.c
+ramstage-y += adsp_load_reset.c
 ramstage-y += ../common/cmd_db.c
 ramstage-y += ../common/rpmh.c ../common/rpmh_bcm.c ../common/rpmh_regulator.c ../common/rpmh_rsc.c
 ramstage-y += rpmh_rsc_init.c
@@ -249,6 +250,23 @@ $(CPUCP_DTBS_CBFS)-type := payload
 $(CPUCP_DTBS_CBFS)-compression := $(CBFS_COMPRESS_FLAG)
 cbfs-files-y += $(CPUCP_DTBS_CBFS)
 
+################################################################################
+# ADSP (Audio DSP) Lite Firmware for Off-mode charging
+################################################################################
+ADSP_LITE_FILE := $(X1P42100_BLOB)/adsp/adsp.mbn
+ADSP_LITE_CBFS := $(CONFIG_CBFS_PREFIX)/adsp_lite
+$(ADSP_LITE_CBFS)-file := $(ADSP_LITE_FILE)
+$(ADSP_LITE_CBFS)-type := payload
+$(ADSP_LITE_CBFS)-compression := $(CBFS_COMPRESS_FLAG)
+cbfs-files-y += $(ADSP_LITE_CBFS)
+
+################################################################################
+ADSP_DTBS_FILE := $(X1P42100_BLOB)/adsp/adsp_dtbs.elf
+ADSP_DTBS_CBFS := $(CONFIG_CBFS_PREFIX)/adsp_dtbs
+$(ADSP_DTBS_CBFS)-file := $(ADSP_DTBS_FILE)
+$(ADSP_DTBS_CBFS)-type := payload
+cbfs-files-y += $(ADSP_DTBS_CBFS)
+
 ################################################################################
 SHRM_FILE := $(X1P42100_BLOB)/$(BLOB_VARIANT)/shrm/shrm.elf
 SHRM_CBFS := $(CONFIG_CBFS_PREFIX)/shrm
diff --git a/src/soc/qualcomm/x1p42100/adsp_load_reset.c b/src/soc/qualcomm/x1p42100/adsp_load_reset.c
new file mode 100644
index 0000000000..03433e8e6f
--- /dev/null
+++ b/src/soc/qualcomm/x1p42100/adsp_load_reset.c
@@ -0,0 +1,119 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <arch/barrier.h>
+#include <cbfs.h>
+#include <console/console.h>
+#include <device/mmio.h>
+#include <program_loading.h>
+#include <soc/adsp.h>
+#include <types.h>
+
+/**
+ * lpass_program_boot_addr() - Program ADSP boot address override
+ * @addr: ADSP firmware entry address
+ *
+ * Program EVB address/select so Q6 boots from @addr.
+ */
+static void lpass_program_boot_addr(uintptr_t addr)
+{
+	write32(&lpass_efuse_q6ss->evb_addr, (addr>>4));
+	write32(&lpass_efuse_q6ss->evb_sel, EVB_ENABLE);
+	dsb();
+}
+
+/**
+ * lpass_dtb_bring_up() - Configure ADSP Device Tree Boot parameters
+ * @dtb_entry_addr: Physical address where Device Tree image is loaded
+ * @dtb_size: Size of Device Tree image in bytes
+ *
+ * Configure the QDSP6SS boot parameter registers with:
+ * - Device Tree blob location and size
+ * - Chip identification (family and ID)
+ * - Chip version information
+ * - Platform type and version
+ *
+ * Boot Parameter Register Layout:
+ * BOOT_PARAMS[0]: DTB address (lower 32 bits)
+ * BOOT_PARAMS[1]: DTB address (upper 32 bits)
+ * BOOT_PARAMS[2]: Chip family (bits 31:16) | Chip ID (bits 15:0)
+ * BOOT_PARAMS[3]: Chip version - Major (bits 15:8) | Minor (bits 7:0)
+ * BOOT_PARAMS[4]: Platform type (bits 31:24) | Subtype (bits 23:16) |
+ *                 Version major (bits 15:8) | Version minor (bits 7:0) not programmed
+ * BOOT_PARAMS[5]: DTB size
+ *
+ * Return: CB_SUCCESS on success, CB_ERR on failure
+ */
+static enum cb_err lpass_dtb_bring_up(uintptr_t dtb_entry_addr, size_t dtb_size)
+{
+	uint32_t chip_family, chip_id;
+	uint32_t chip_major, chip_minor;
+	uint32_t boot_params2, boot_params3;
+
+	write32(&lpass_qdsp6ss->boot_params[0], (uint32_t)(dtb_entry_addr & 0xFFFFFFFF));
+	write32(&lpass_qdsp6ss->boot_params[1], (uint32_t)(dtb_entry_addr >> 32));
+
+	/* x1p42100 uses fixed SoC boot args; do not depend on SMEM init ordering. */
+
+	chip_family = CHIPINFO_FAMILY & CHIP_FAMILY_MASK;
+	chip_id = CHIPINFO_ID_SCP & CHIP_ID_MASK;
+	boot_params2 = (chip_family << CHIP_FAMILY_SHIFT) | chip_id;
+
+	chip_major = CHIPINFO_CHIP_VERSION_MAJOR;
+	chip_minor = CHIPINFO_CHIP_VERSION_MINOR;
+	boot_params3 = ((chip_major & CHIP_VERSION_MASK) << CHIP_VERSION_MAJOR_SHIFT) |
+		       (chip_minor & CHIP_VERSION_MASK);
+
+	write32(&lpass_qdsp6ss->boot_params[2], boot_params2);
+	write32(&lpass_qdsp6ss->boot_params[3], boot_params3);
+	write32(&lpass_qdsp6ss->boot_params[5], (uint32_t)dtb_size);
+	dsb();
+
+	return CB_SUCCESS;
+}
+
+/**
+ * adsp_fw_load() - Main entry point for ADSP firmware loading
+ *
+ * Orchestrate the complete ADSP firmware loading sequence:
+ * 1. Load ADSP Device Tree Blob from CBFS
+ * 2. Configure QDSP6SS boot parameters with DTB location and platform info
+ * 3. Load ADSP firmware from CBFS
+ * 4. Program ADSP boot address via EFUSE EVB registers
+ */
+void adsp_fw_load(void)
+{
+	struct prog adsp_dtbs_prog = PROG_INIT(PROG_PAYLOAD, ADSP_CBFS_DTBS);
+	struct prog adsp_fw_prog = PROG_INIT(PROG_PAYLOAD, ADSP_CBFS_FIRMWARE);
+	uintptr_t dtb_entry_addr;
+	uintptr_t fw_entry_addr;
+	size_t dtb_size;
+
+	dtb_size = cbfs_get_size(ADSP_CBFS_DTBS);
+	if (dtb_size == 0) {
+		printk(BIOS_ERR, "ADSP: Failed to get DTBS size from CBFS\n");
+		return;
+	}
+
+	if (!selfload(&adsp_dtbs_prog)) {
+		printk(BIOS_ERR, "ADSP: DTBS load failed\n");
+		return;
+	}
+
+	dtb_entry_addr = (uintptr_t)prog_entry(&adsp_dtbs_prog);
+
+	if (lpass_dtb_bring_up(dtb_entry_addr, dtb_size) != CB_SUCCESS) {
+		printk(BIOS_ERR, "ADSP: DTB bring up failed\n");
+		return;
+	}
+
+	if (!selfload(&adsp_fw_prog)) {
+		printk(BIOS_ERR, "ADSP: Firmware load failed\n");
+		return;
+	}
+
+	fw_entry_addr = (uintptr_t)prog_entry(&adsp_fw_prog);
+
+	lpass_program_boot_addr(fw_entry_addr);
+
+	printk(BIOS_INFO, "SOC: LPASS/ADSP image loaded successfully\n");
+}
diff --git a/src/soc/qualcomm/x1p42100/include/soc/addressmap.h b/src/soc/qualcomm/x1p42100/include/soc/addressmap.h
index dc45a668d6..6cb4b231e2 100644
--- a/src/soc/qualcomm/x1p42100/include/soc/addressmap.h
+++ b/src/soc/qualcomm/x1p42100/include/soc/addressmap.h
@@ -24,6 +24,8 @@
 #define LPASS_AON_CC_BASE		(LPASS_BASE + 0x00E08000)
 #define LPASS_AON_CC_PLL_CM_BASE	(LPASS_BASE + 0x00E01000)
 #define LPASS_CORE_GDSC_REG_BASE	(LPASS_BASE + 0x01E00000)
+#define LPASS_QDSP6SS_PUB_BASE		(LPASS_BASE + 0x00800000)
+#define LPASS_EFUSE_Q6SS_BASE		(LPASS_BASE + 0x0125B000)
 
 #define RPMH_BASE                       0x17520000
 #define CMD_DB_BASE_ADDR                0x81c60000
diff --git a/src/soc/qualcomm/x1p42100/include/soc/adsp.h b/src/soc/qualcomm/x1p42100/include/soc/adsp.h
new file mode 100644
index 0000000000..5e156f210b
--- /dev/null
+++ b/src/soc/qualcomm/x1p42100/include/soc/adsp.h
@@ -0,0 +1,40 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef __SOC_QUALCOMM_X1P42100_ADSP_H__
+#define __SOC_QUALCOMM_X1P42100_ADSP_H__
+
+#include <commonlib/helpers.h>
+#include <soc/addressmap.h>
+#include <soc/platform_info.h>
+#include <types.h>
+
+/* ADSP CBFS firmware paths */
+#define ADSP_CBFS_DTBS				CONFIG_CBFS_PREFIX "/adsp_dtbs"
+#define ADSP_CBFS_FIRMWARE			CONFIG_CBFS_PREFIX "/adsp_lite"
+
+/* LPASS QDSP6SS Register Structure */
+struct x1p42100_lpass_qdsp6ss {
+	u8 _res0[0x10];
+	u32 rst_evb;
+	u8 _res1[0x60 - 0x14];
+	u32 boot_params[6];
+};
+
+check_member(x1p42100_lpass_qdsp6ss, rst_evb, 0x10);
+check_member(x1p42100_lpass_qdsp6ss, boot_params, 0x60);
+
+/* LPASS EFUSE Q6SS Register Structure */
+struct x1p42100_lpass_efuse_q6ss {
+	u32 evb_sel;
+	u32 evb_addr;
+};
+
+check_member(x1p42100_lpass_efuse_q6ss, evb_sel, 0x0);
+check_member(x1p42100_lpass_efuse_q6ss, evb_addr, 0x4);
+
+static struct x1p42100_lpass_qdsp6ss *const lpass_qdsp6ss = (void *)LPASS_QDSP6SS_PUB_BASE;
+static struct x1p42100_lpass_efuse_q6ss *const lpass_efuse_q6ss = (void *)LPASS_EFUSE_Q6SS_BASE;
+
+void adsp_fw_load(void);
+
+#endif /* __SOC_QUALCOMM_X1P42100_ADSP_H__ */
diff --git a/src/soc/qualcomm/x1p42100/include/soc/platform_info.h b/src/soc/qualcomm/x1p42100/include/soc/platform_info.h
new file mode 100644
index 0000000000..bf27c7cb92
--- /dev/null
+++ b/src/soc/qualcomm/x1p42100/include/soc/platform_info.h
@@ -0,0 +1,53 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+#ifndef __SOC_QUALCOMM_X1P42100_PLATFORM_INFO_H__
+#define __SOC_QUALCOMM_X1P42100_PLATFORM_INFO_H__
+
+/* ADSP BOOT_PARAMS helpers */
+
+/* BOOT_PARAMS bitfield definitions */
+#define CHIP_FAMILY_MASK			0xFFFF
+#define CHIP_FAMILY_SHIFT			16
+#define CHIP_ID_MASK				0xFFFF
+#define CHIP_VERSION_MAJOR_SHIFT		8
+#define CHIP_VERSION_MASK			0xFF
+#define PLATFORM_FIELD_MASK			0xFF
+#define PLATFORM_SUBTYPE_SHIFT			16
+#define PLATFORM_TYPE_SHIFT			24
+#define PLATFORM_VERSION_MAJOR_SHIFT		8
+
+#define EVB_ENABLE				1
+
+/*
+ * ADSP BOOT_PARAMS chipinfo identifiers.
+ *
+ * Keep values as macros (no literals in packer code) to match SMEM chipinfo:
+ * - CHIPINFO_FAMILY_*: eChipInfoFamily
+ * - CHIPINFO_ID_SCP_*: eChipInfoId (SCP)
+ */
+#if CONFIG(SOC_QUALCOMM_HAMOA)
+/* Hamoa (SC8380XP) identifiers used by ADSP BOOT_PARAMS on x1p42100 platforms. */
+#define CHIPINFO_FAMILY				0x0088
+#define CHIPINFO_ID_SCP				0x022B
+
+/* Hamoa chip version used for BOOT_PARAMS[3] packing. */
+#define CHIPINFO_CHIP_VERSION			0x00020000 /* nChipVersion (SMEM) */
+#define CHIPINFO_CHIP_VERSION_MAJOR		0x02
+#define CHIPINFO_CHIP_VERSION_MINOR		0x00
+#else
+/* Purwa Compute (SC8340XP / X1P4x100) */
+#define CHIPINFO_FAMILY				0x009A
+#define CHIPINFO_ID_SCP				0x027B
+
+#define CHIPINFO_CHIP_VERSION			0x00020000 /* nChipVersion (SMEM) */
+#define CHIPINFO_CHIP_VERSION_MAJOR		0x02
+#define CHIPINFO_CHIP_VERSION_MINOR		0x00
+#endif
+
+/* x1p42100 platform info used for BOOT_PARAMS[4] packing. */
+#define PLATFORMINFO_TYPE			0x28 /* ePlatformType */
+#define PLATFORMINFO_SUBTYPE			0x00 /* nPlatformSubtype */
+#define PLATFORMINFO_VERSION			0x00010000 /* nPlatformVersion */
+#define PLATFORMINFO_VERSION_MAJOR		0x01
+#define PLATFORMINFO_VERSION_MINOR		0x00
+
+#endif /* __SOC_QUALCOMM_X1P42100_PLATFORM_INFO_H__ */

From a58f752d0f2dbc43a2f4b11ca8bd2f75327931d5 Mon Sep 17 00:00:00 2001
From: Hari L <haril@qualcomm.corp-partner.google.com>
Date: Wed, 4 Mar 2026 21:50:27 +0530
Subject: [PATCH 3793/3886] soc/qualcomm/common: add CBCR disable and config
 helpers

Add clock_disable() (clear CBCR EN and poll CLK_OFF).

Add CBCR helper APIs and common bit definitions for HW_CTL,
FORCE_MEM_CORE_ON, IGNORE_RPMH_CLK_DIS and IGNORE_PMU_CLK_DIS.

BUG=None
TEST=Built and booted image.serial.bin on Bluey

Change-Id: I253414d01ec97aee45df1af0ed8cd06367351ef8
Signed-off-by: Hari L <haril@qualcomm.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91546
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Jayvik Desai <jayvik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
---
 src/soc/qualcomm/common/clock.c               | 84 +++++++++++++++++--
 .../common/include/soc/clock_common.h         | 22 ++++-
 2 files changed, 97 insertions(+), 9 deletions(-)

diff --git a/src/soc/qualcomm/common/clock.c b/src/soc/qualcomm/common/clock.c
index ede523e298..2682721aa0 100644
--- a/src/soc/qualcomm/common/clock.c
+++ b/src/soc/qualcomm/common/clock.c
@@ -17,7 +17,7 @@ static bool clock_is_off(u32 *cbcr_addr)
 enum cb_err clock_enable_vote(void *cbcr_addr, void *vote_addr,
 				uint32_t vote_bit)
 {
-	int count = 100;
+	int count = CLK_POLL_COUNT;
 
 	setbits32(vote_addr, BIT(vote_bit));
 
@@ -34,7 +34,7 @@ enum cb_err clock_enable_vote(void *cbcr_addr, void *vote_addr,
 
 enum cb_err clock_enable(void *cbcr_addr)
 {
-	int count = 100;
+	int count = CLK_POLL_COUNT;
 
 	/* Set clock enable bit */
 	setbits32(cbcr_addr, BIT(CLK_CTL_EN_SHFT));
@@ -50,6 +50,74 @@ enum cb_err clock_enable(void *cbcr_addr)
 	return CB_ERR;
 }
 
+enum cb_err clock_disable(void *cbcr_addr)
+{
+	int count = CLK_POLL_COUNT;
+
+	if (!cbcr_addr)
+		return CB_ERR;
+
+	/* Clear clock enable bit */
+	clrbits32(cbcr_addr, BIT(CLK_CTL_EN_SHFT));
+
+	/* Ensure clock is disabled */
+	while (count-- > 0) {
+		if (clock_is_off(cbcr_addr))
+			return CB_SUCCESS;
+		udelay(1);
+	}
+
+	printk(BIOS_ERR, "Failed to disable clock, register val: 0x%x\n",
+	       read32(cbcr_addr));
+	return CB_ERR;
+}
+
+void clock_configure_ignore_rpmh_clk_dis(void *cbcr_addr, bool enable)
+{
+	if (!cbcr_addr)
+		return;
+
+	if (enable)
+		setbits32(cbcr_addr, BIT(CLK_CTL_IGNORE_RPMH_CLK_DIS_SHFT));
+	else
+		clrbits32(cbcr_addr, BIT(CLK_CTL_IGNORE_RPMH_CLK_DIS_SHFT));
+}
+
+void clock_configure_ignore_pmu_clk_dis(void *cbcr_addr, bool enable)
+{
+	if (!cbcr_addr)
+		return;
+
+	if (enable)
+		setbits32(cbcr_addr, BIT(CLK_CTL_IGNORE_PMU_CLK_DIS_SHFT));
+	else
+		clrbits32(cbcr_addr, BIT(CLK_CTL_IGNORE_PMU_CLK_DIS_SHFT));
+}
+
+void clock_configure_hw_ctl(void *cbcr_addr, bool enable)
+{
+	if (!cbcr_addr)
+		return;
+
+	/* Enable or disable hardware-controlled clock gating */
+	if (enable)
+		setbits32(cbcr_addr, BIT(CLK_CTL_HW_CTL_SHFT));
+	else
+		clrbits32(cbcr_addr, BIT(CLK_CTL_HW_CTL_SHFT));
+}
+
+void clock_configure_force_mem_core_on(void *cbcr_addr, bool enable)
+{
+	if (!cbcr_addr)
+		return;
+
+	/* Forces core-on signal to stay active during clk halt */
+	if (enable)
+		setbits32(cbcr_addr, BIT(CLK_CTL_FORCE_MEM_CORE_ON_SHFT));
+	else
+		clrbits32(cbcr_addr, BIT(CLK_CTL_FORCE_MEM_CORE_ON_SHFT));
+}
+
 /* Clock Block Reset Operations */
 void clock_reset_bcr(void *bcr_addr, bool assert)
 {
@@ -77,7 +145,7 @@ enum cb_err enable_and_poll_gdsc_status(void *gdscr_addr)
 	clrbits32(gdscr_addr, BIT(GDSC_ENABLE_BIT));
 
 	/* Ensure gdsc is enabled */
-	if (!wait_us(100, (read32(gdscr_addr) & CLK_CTL_OFF_BMSK)))
+	if (!wait_us(CLK_WAIT_US_TIMEOUT, (read32(gdscr_addr) & CLK_CTL_OFF_BMSK)))
 		return CB_ERR;
 
 	return CB_SUCCESS;
@@ -227,7 +295,7 @@ enum cb_err clock_configure_enable_gpll(struct alpha_pll_reg_val_config *cfg,
 		setbits32(cfg->reg_apcs_pll_br_en, BIT(br_enable));
 
 		/* Wait for Lock Detection */
-		if (!wait_us(100, read32(cfg->reg_mode) & PLL_LOCK_DET_BMSK)) {
+		if (!wait_us(CLK_WAIT_US_TIMEOUT, read32(cfg->reg_mode) & PLL_LOCK_DET_BMSK)) {
 			printk(BIOS_ERR, "PLL did not lock!\n");
 			return CB_ERR;
 		}
@@ -247,7 +315,7 @@ enum cb_err agera_pll_enable(struct alpha_pll_reg_val_config *cfg)
 	udelay(5);
 	setbits32(cfg->reg_mode, BIT(PLL_RESET_SHFT));
 
-	if (!wait_us(100, read32(cfg->reg_mode) & PLL_LOCK_DET_BMSK)) {
+	if (!wait_us(CLK_WAIT_US_TIMEOUT, read32(cfg->reg_mode) & PLL_LOCK_DET_BMSK)) {
 		printk(BIOS_ERR, "CPU PLL did not lock!\n");
 		return CB_ERR;
 	}
@@ -269,7 +337,7 @@ enum cb_err zonda_pll_enable(struct alpha_pll_reg_val_config *cfg)
 	setbits32(cfg->reg_mode, BIT(PLL_RESET_SHFT));
 	setbits32(cfg->reg_opmode, PLL_RUN_MODE);
 
-	if (!wait_us(100, read32(cfg->reg_mode) & PLL_LOCK_DET_BMSK)) {
+	if (!wait_us(CLK_WAIT_US_TIMEOUT, read32(cfg->reg_mode) & PLL_LOCK_DET_BMSK)) {
 		printk(BIOS_ERR, "CPU PLL did not lock!\n");
 		return CB_ERR;
 	}
@@ -292,7 +360,7 @@ enum cb_err zondaole_pll_enable(struct alpha_pll_reg_val_config *cfg)
 	setbits32(cfg->reg_mode, BIT(PLL_RESET_SHFT));
 	setbits32(cfg->reg_opmode, PLL_RUN_MODE);
 
-	if (!wait_us(100, read32(cfg->reg_mode) & PLL_LOCK_DET_BMSK)) {
+	if (!wait_us(CLK_WAIT_US_TIMEOUT, read32(cfg->reg_mode) & PLL_LOCK_DET_BMSK)) {
 		printk(BIOS_ERR, "CPU PLL did not lock!\n");
 		return CB_ERR;
 	}
@@ -312,7 +380,7 @@ enum cb_err lucidole_pll_enable(struct alpha_pll_reg_val_config *cfg)
 	setbits32(cfg->reg_opmode, PLL_RUN_MODE);
 	setbits32(cfg->reg_mode, BIT(PLL_RESET_SHFT));
 
-	if (!wait_us(100, read32(cfg->reg_mode) & PLL_LOCK_DET_BMSK)) {
+	if (!wait_us(CLK_WAIT_US_TIMEOUT, read32(cfg->reg_mode) & PLL_LOCK_DET_BMSK)) {
 		printk(BIOS_ERR, "CPU PLL did not lock!\n");
 		return CB_ERR;
 	}
diff --git a/src/soc/qualcomm/common/include/soc/clock_common.h b/src/soc/qualcomm/common/include/soc/clock_common.h
index fd3a073d01..20e01b83bc 100644
--- a/src/soc/qualcomm/common/include/soc/clock_common.h
+++ b/src/soc/qualcomm/common/include/soc/clock_common.h
@@ -4,6 +4,8 @@
 #define __SOC_QUALCOMM_COMMON_CLOCK_H__
 
 #define QCOM_CLOCK_DIV(div)	(2 * div - 1)
+#define CLK_POLL_COUNT		100
+#define CLK_WAIT_US_TIMEOUT	100
 
 /* Root Clock Generator */
 struct clock_rcg {
@@ -124,11 +126,19 @@ enum clk_ctl_cmd_rcgr {
 
 enum clk_ctl_cbcr {
 	CLK_CTL_EN_SHFT  = 0,
+	CLK_CTL_HW_CTL_SHFT = 1,
 	CLK_CTL_ARES_SHFT = 2,
+	CLK_CTL_FORCE_MEM_CORE_ON_SHFT = 14,
+	CLK_CTL_IGNORE_RPMH_CLK_DIS_SHFT = 20,
+	CLK_CTL_IGNORE_PMU_CLK_DIS_SHFT = 21,
 	CLK_CTL_OFF_SHFT = 31,
 	CLK_CTL_EN_BMSK = 0x1,
+	CLK_CTL_HW_CTL_BMSK = 0x1 << CLK_CTL_HW_CTL_SHFT,
 	CLK_CTL_ARES_BMSK = 0x1 << CLK_CTL_ARES_SHFT,
-	CLK_CTL_OFF_BMSK = 0x80000000,
+	CLK_CTL_FORCE_MEM_CORE_ON_BMSK = 0x1 << CLK_CTL_FORCE_MEM_CORE_ON_SHFT,
+	CLK_CTL_IGNORE_RPMH_CLK_DIS_BMSK = 0x1 << CLK_CTL_IGNORE_RPMH_CLK_DIS_SHFT,
+	CLK_CTL_IGNORE_PMU_CLK_DIS_BMSK = 0x1 << CLK_CTL_IGNORE_PMU_CLK_DIS_SHFT,
+	CLK_CTL_OFF_BMSK = 0x1 << CLK_CTL_OFF_SHFT,
 };
 
 enum clk_ctl_rcg_mnd {
@@ -155,6 +165,16 @@ enum cb_err clock_enable_vote(void *cbcr_addr, void *vote_addr,
 
 enum cb_err clock_enable(void *cbcr_addr);
 
+enum cb_err clock_disable(void *cbcr_addr);
+
+void clock_configure_ignore_rpmh_clk_dis(void *cbcr_addr, bool enable);
+
+void clock_configure_ignore_pmu_clk_dis(void *cbcr_addr, bool enable);
+
+void clock_configure_hw_ctl(void *cbcr_addr, bool enable);
+
+void clock_configure_force_mem_core_on(void *cbcr_addr, bool enable);
+
 enum cb_err enable_and_poll_gdsc_status(void *gdscr_addr);
 
 void clock_reset_bcr(void *bcr_addr, bool assert);

From 8beca9647022a90c54ce64ca1389c0f442bafbd1 Mon Sep 17 00:00:00 2001
From: Hari L <haril@qualcomm.corp-partner.google.com>
Date: Thu, 5 Mar 2026 14:22:14 +0530
Subject: [PATCH 3794/3886] soc/qualcomm/x1p42100: Add LPASS bring-up sequence
 for ADSP cold boot

Add LPASS(QDSP6) cold-boot support required to start the ADSP/LPASS
subsystem. Extend LPASS base/address definitions and register blocks,
add QDSP6SS register coverage with offset validation, and implement the
LPASS/Q6 bring-up sequence including RPMh votes, clock and GDSC enablement,
QDSP6SS PLL and core clock programming, TCM initialization, and Q6 boot
FSM start.

This enables correct ADSP initialization during cold boot on X1P42100 and
is required for off-mode charging support.

Reference:
  - HRD-X1P42100-S1
    https://docs.qualcomm.com/bundle/resource/topics/HRD-X1P42100-S1/

TEST:
  - Built image.serial.bin and verified boot on X1P42100.
  - Verified that ADSP Q6 comes out of reset and is enabled during cold boot.

Logs:
[INFO ]  SOC: LPASS/ADSP image loaded successfully
[INFO ]  RPMH RSC: Already initialized, skipping re-initialization
[DEBUG]  RPMH_REG: lcx.lvl ARC hlvl= 0 --> vlvl=   0
[DEBUG]  RPMH_REG: lcx.lvl ARC hlvl= 1 --> vlvl=  16
[DEBUG]  RPMH_REG: lcx.lvl ARC hlvl= 2 --> vlvl=  56
[DEBUG]  RPMH_REG: lcx.lvl ARC hlvl= 3 --> vlvl=  64
[DEBUG]  RPMH_REG: lcx.lvl ARC hlvl= 4 --> vlvl= 128
[DEBUG]  RPMH_REG: lcx.lvl ARC hlvl= 5 --> vlvl= 192
[DEBUG]  RPMH_REG: lcx.lvl ARC hlvl= 6 --> vlvl= 256
[DEBUG]  RPMH_REG: lcx.lvl ARC hlvl= 7 --> vlvl= 384
[INFO ]  RPMH_REG: Initialized lcx.lvl at addr=0x30030
[DEBUG]  RPMH_REG: Sent active request for lcx.lvl
[DEBUG]  BCM: Found address 0x00050048 for resource LP0
[INFO ]  BCM: Successfully voted for LP0 (addr=0x00050048, val=0x60004001)
[INFO ]  LPASS: BCM vote for LP0 and LPASS Init completed successfully
[INFO ]  LPASS: Processor setup complete
[INFO ]  LPASS: Q6 processor enabled

Change-Id: Icb06575be0c225c3b8fa7894f49ccc197ee7e072
Signed-off-by: Hari L <haril@qualcomm.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91563
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Jayvik Desai <jayvik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
---
 .../x1p42100/include/soc/addressmap.h         |   9 +
 src/soc/qualcomm/x1p42100/include/soc/adsp.h  |  12 +-
 src/soc/qualcomm/x1p42100/include/soc/clock.h | 266 +++++++++--
 src/soc/qualcomm/x1p42100/include/soc/lpass.h | 105 ++++-
 .../x1p42100/include/soc/rpmh_config.h        |   1 +
 src/soc/qualcomm/x1p42100/lpass.c             | 446 +++++++++++++++++-
 6 files changed, 788 insertions(+), 51 deletions(-)

diff --git a/src/soc/qualcomm/x1p42100/include/soc/addressmap.h b/src/soc/qualcomm/x1p42100/include/soc/addressmap.h
index 6cb4b231e2..63d96a3ea4 100644
--- a/src/soc/qualcomm/x1p42100/include/soc/addressmap.h
+++ b/src/soc/qualcomm/x1p42100/include/soc/addressmap.h
@@ -24,7 +24,15 @@
 #define LPASS_AON_CC_BASE		(LPASS_BASE + 0x00E08000)
 #define LPASS_AON_CC_PLL_CM_BASE	(LPASS_BASE + 0x00E01000)
 #define LPASS_CORE_GDSC_REG_BASE	(LPASS_BASE + 0x01E00000)
+#define LPASS_LPASS_CORE_CC_REG_BASE	(LPASS_BASE + 0x01B08000)
+#define LPASS_LPICX_NOC_BASE		(LPASS_BASE + 0x01430000)
+#define LPASS_LPI_TCM_REG_BASE		(LPASS_BASE + 0x0126A000)
+#define LPASS_MCC_LPASS_REG_BASE	(LPASS_BASE + 0x01250000)
 #define LPASS_QDSP6SS_PUB_BASE		(LPASS_BASE + 0x00800000)
+#define LPASS_QDSP6SS_PLL_BASE		(LPASS_BASE + 0x00840000)
+#define LPASS_QDSP6SS_CORE_CC_BASE	(LPASS_BASE + 0x00848000)
+#define LPASS_SSC_SCC_BASE		(LPASS_BASE + 0x01A01000)
+
 #define LPASS_EFUSE_Q6SS_BASE		(LPASS_BASE + 0x0125B000)
 
 #define RPMH_BASE                       0x17520000
@@ -172,6 +180,7 @@
 #define PCIE6A_BQPHY_PCS_PCIE_LANE1	0x01BFFE00
 
 /* TCSR */
+#define TCSR_BASE				0x01FC0000
 #define TCSR_GCC_PCIE_4L_CLKREF_EN_PCIE_ENABLE	((void *)0x1FD512C)
 #define TCSR_PCIE_CTRL_4LN_CONFIG_SEL	((void *)0x1FDA000)
 
diff --git a/src/soc/qualcomm/x1p42100/include/soc/adsp.h b/src/soc/qualcomm/x1p42100/include/soc/adsp.h
index 5e156f210b..6c53e49ad8 100644
--- a/src/soc/qualcomm/x1p42100/include/soc/adsp.h
+++ b/src/soc/qualcomm/x1p42100/include/soc/adsp.h
@@ -16,12 +16,22 @@
 struct x1p42100_lpass_qdsp6ss {
 	u8 _res0[0x10];
 	u32 rst_evb;
-	u8 _res1[0x60 - 0x14];
+	u8 _res1[0x18 - 0x14];
+	u32 dbg_cfg;
+	u32 ret_cfg;
+	u8 _res2[0x60 - 0x20];
 	u32 boot_params[6];
+	u8 _res3[0x400 - 0x78];
+	u32 boot_core_start;
+	u32 boot_cmd;
+	u32 boot_status;
 };
 
 check_member(x1p42100_lpass_qdsp6ss, rst_evb, 0x10);
+check_member(x1p42100_lpass_qdsp6ss, dbg_cfg, 0x18);
 check_member(x1p42100_lpass_qdsp6ss, boot_params, 0x60);
+check_member(x1p42100_lpass_qdsp6ss, boot_core_start, 0x400);
+check_member(x1p42100_lpass_qdsp6ss, boot_status, 0x408);
 
 /* LPASS EFUSE Q6SS Register Structure */
 struct x1p42100_lpass_efuse_q6ss {
diff --git a/src/soc/qualcomm/x1p42100/include/soc/clock.h b/src/soc/qualcomm/x1p42100/include/soc/clock.h
index 934c0fdb34..b60ea039c8 100644
--- a/src/soc/qualcomm/x1p42100/include/soc/clock.h
+++ b/src/soc/qualcomm/x1p42100/include/soc/clock.h
@@ -223,6 +223,36 @@ struct x1p42100_lpass_aon_cc_pll_clock {
 	u32 pll_test_ctl_u2;
 };
 
+/* LPASS QDSP6SS PLL register structure */
+struct x1p42100_lpass_qdsp6ss_pll_clock {
+	u32 pll_mode;
+	u32 pll_opmode;
+	u32 pll_state;
+	u32 pll_status;
+	u32 pll_l_val;
+	u32 pll_alpha_val;
+	u32 pll_user_ctl;
+	u32 pll_user_ctl_u;
+	u32 pll_config_ctl;
+	u32 pll_config_ctl_u;
+	u32 pll_config_ctl_u1;
+	u32 pll_test_ctl;
+	u32 pll_test_ctl_u;
+	u32 pll_test_ctl_u1;
+	u32 pll_test_ctl_u2;
+};
+
+/* LPASS QDSP6SS Core CC register structure */
+struct x1p42100_lpass_qdsp6ss_core_cc {
+	u32 core_cmd_rcgr;
+	u32 core_cfg_rcgr;
+	u8 _res0[0x0020 - 0x0008];
+	u32 core_cbcr;
+};
+
+check_member(x1p42100_lpass_qdsp6ss_core_cc, core_cfg_rcgr, 0x0004);
+check_member(x1p42100_lpass_qdsp6ss_core_cc, core_cbcr, 0x0020);
+
 /* LPASS Audio CC register structure */
 struct x1p42100_lpass_audio_cc {
 	u8 _res0[0x28018];
@@ -277,28 +307,102 @@ struct x1p42100_lpass_core_gdsc {
 check_member(x1p42100_lpass_core_gdsc, lpass_core_gds_hm_ready, 0x000B8);
 check_member(x1p42100_lpass_core_gdsc, lpass_top_cc_lpass_core_sway_ahb_ls_cbcr, 0x09000);
 
-/* LPASS AON CC register structure */
-struct x1p42100_lpass_aon_cc {
-	u8 _res0[0x9060];
-	u32 va_mem0_cbcr;
-	u8 _res1[0x2c];
-	u32 lpass_audio_hm_gdscr;
-	u8 _res2[0x2f6c];
-	u32 lpass_hm_collapse_vote_for_q6;
-	u8 _res3[0x6008];
-	u32 va_2x_cbcr;
-	u8 _res4[0x4];
-	u32 va_cbcr;
-	u8 _res5[0xffc];
-	u32 tx_mclk_cbcr;
+/* LPASS Core CC register structure */
+struct x1p42100_lpass_core_cc {
+	u8 _res0[0x23000];
+	u32 lpass_lpass_core_cc_sysnoc_mport_core_cbcr;
 };
 
+check_member(x1p42100_lpass_core_cc, lpass_lpass_core_cc_sysnoc_mport_core_cbcr, 0x23000);
+
+/* LPASS AON CC register structure */
+struct x1p42100_lpass_aon_cc {
+	u8 _res0[0x2000];
+	u32 lpass_noc_island_isolation;
+	u8 _res1[0x801C - 0x2004];
+	u32 q6_xo_cbcr;
+	u8 _res2[0x901C - 0x8020];
+	u32 q6_ahbm_cbcr;
+	u8 _res3[0x9060 - 0x9020];
+	u32 va_mem0_cbcr;
+	u8 _res4[0x9090 - 0x9064];
+	u32 lpass_audio_hm_gdscr;
+	u8 _res5[0x0A014 - 0x9094];
+	u32 pclkdbg_cbcr;
+	u8 _res6[0x0A020 - 0x0A018];
+	u32 at_cbcr;
+	u8 _res7[0xC000 - 0x0A024];
+	u32 lpass_hm_collapse_vote_for_q6;
+	u8 _res8[0x1200C - 0xC004];
+	u32 va_2x_cbcr;
+	u8 _res9[0x12014 - 0x12010];
+	u32 va_cbcr;
+	u8 _res10[0x13014 - 0x12018];
+	u32 tx_mclk_cbcr;
+	u8 _res11[0x19008 - 0x13018];
+	u32 lpi_noc_hs_cbcr;
+	u8 _res12[0x1902C - 0x1900C];
+	u32 q6_axim_cbcr;
+};
+
+check_member(x1p42100_lpass_aon_cc, lpass_noc_island_isolation, 0x02000);
+check_member(x1p42100_lpass_aon_cc, q6_xo_cbcr, 0x801C);
+check_member(x1p42100_lpass_aon_cc, q6_ahbm_cbcr, 0x901C);
 check_member(x1p42100_lpass_aon_cc, va_mem0_cbcr, 0x9060);
 check_member(x1p42100_lpass_aon_cc, lpass_audio_hm_gdscr, 0x9090);
+check_member(x1p42100_lpass_aon_cc, pclkdbg_cbcr, 0x0A014);
+check_member(x1p42100_lpass_aon_cc, at_cbcr, 0x0A020);
 check_member(x1p42100_lpass_aon_cc, lpass_hm_collapse_vote_for_q6, 0xc000);
 check_member(x1p42100_lpass_aon_cc, va_2x_cbcr, 0x1200C);
 check_member(x1p42100_lpass_aon_cc, va_cbcr, 0x12014);
 check_member(x1p42100_lpass_aon_cc, tx_mclk_cbcr, 0x13014);
+check_member(x1p42100_lpass_aon_cc, lpi_noc_hs_cbcr, 0x19008);
+check_member(x1p42100_lpass_aon_cc, q6_axim_cbcr, 0x1902C);
+
+/* LPASS LPICX NOC register structure */
+struct x1p42100_lpass_lpicx_noc {
+	u8 _res0[0x2040];
+	u32 sidebandmanager_chipcx_sbm_faultinen0_low;
+	u8 _res1[0x6090 - 0x2044];
+	u32 sidebandmanager_rcg_sbm_flagoutstatus0_low;
+};
+
+check_member(x1p42100_lpass_lpicx_noc, sidebandmanager_chipcx_sbm_faultinen0_low, 0x2040);
+check_member(x1p42100_lpass_lpicx_noc, sidebandmanager_rcg_sbm_flagoutstatus0_low, 0x6090);
+
+/* LPASS MCC_LPASS_REG register block */
+struct x1p42100_lpass_mcc_lpass_reg {
+	u8 _res0[0x18];
+	u32 rsc_wait_event_ovrd_mask;
+	u8 _res1[0x5014 - 0x001c];
+	u32 atb_low_power_handshake;
+	u32 apb_low_power_handshake;
+	u8 _res2[0x5020 - 0x501c];
+	u32 nts_low_power_handshake;
+	u32 dap_low_power_handshake;
+};
+
+check_member(x1p42100_lpass_mcc_lpass_reg, rsc_wait_event_ovrd_mask, 0x0018);
+check_member(x1p42100_lpass_mcc_lpass_reg, atb_low_power_handshake, 0x5014);
+check_member(x1p42100_lpass_mcc_lpass_reg, nts_low_power_handshake, 0x5020);
+
+/* LPASS SSC_SCC register block */
+struct x1p42100_lpass_ssc_scc {
+	u8 _res0[0x30];
+	u32 ssc_scc_smem_cbcr;
+};
+
+check_member(x1p42100_lpass_ssc_scc, ssc_scc_smem_cbcr, 0x0030);
+
+/* LPASS LPI TCM register block */
+struct x1p42100_lpass_lpi_tcm {
+	u32 tcm_256kb_block_cbcr[10];
+	u8 _res0[0x0300 - 0x0028];
+	u32 axis_hs_cbcr;
+};
+
+check_member(x1p42100_lpass_lpi_tcm, tcm_256kb_block_cbcr, 0x0000);
+check_member(x1p42100_lpass_lpi_tcm, axis_hs_cbcr, 0x0300);
 
 struct x1p42100_disp_cc {
 	uint8_t _res0[0x00C];
@@ -335,7 +439,7 @@ struct x1p42100_disp_cc {
 	uint32_t xo_cbcr;
 };
 
-/* Offset checks (relative to DISP_CC_BASE) */
+/* Offset checks */
 check_member(x1p42100_disp_cc, mdss_mdp_cbcr,		0x00000C);
 check_member(x1p42100_disp_cc, mdss_vsync_cbcr,		0x000024);
 check_member(x1p42100_disp_cc, mdss_dptx3_pixel0_cbcr,	0x000094);
@@ -521,82 +625,111 @@ struct x1p42100_gcc {
 	u32 gcc_aggre_usb3_prim_axi_cbcr;
 	u8  _res36[0x42004 - 0x39094];
 	struct qupv3_clock qup_wrap0_s[8];
-	u8 _res37[0x47000 - 0x429c4];
-	u32 lpass_cfg_noc_sway_cbcr;
-	u8 _res38[0x4b000 - 0x47004];
+	u8 _res37[0x45150 - 0x429c4];
+	/* LPASS boot clock */
+	u32 gcc_noc_lpass_dcd_xo_cbcr;
+	u32 gcc_ddrss_lpass_shub_cbcr;
+	u8 _res38[0x47000 - 0x45158];
+	u32 gcc_lpass_cfg_noc_sway_cbcr;
+	u32 gcc_qmip_lpass_qtb_ahb_cbcr;
+	u8 _res39[0x47010 - 0x47008];
+	u32 gcc_lpass_aon_noc_ddrss_shub_cbcr;
+	u32 gcc_lpass_aggre_noc_mpu_client_ddrss_shub_cbcr;
+	u32 gcc_lpass_hw_af_noc_ddrss_shub_cbcr;
+	u8 _res40[0x47024 - 0x4701c];
+	u32 gcc_lpass_aggre_noc_ddrss_shub_cbcr;
+	u8 _res41[0x4702c - 0x47028];
+	struct clock_rcg lpass_ddrss_shub_rcg;
+	u8 _res42[0x47160 - 0x47034];
+	u32 gcc_cfg_noc_lpass_cbcr;
+	u8 _res43[0x4b000 - 0x47164];
 	u32 qspi_bcr;
 	u32 qspi_cnoc_ahb_cbcr;
 	u32 qspi_core_cbcr;
 	struct clock_rcg qspi_core;
-	u8 _res39[0x50000 - 0x4b014];
+	u8 _res44[0x50000 - 0x4b014];
 	u32 gcc_usb3_phy_prim_bcr;
 	u32 gcc_usb3phy_phy_prim_bcr;
-	u8 _res40[0x50010 - 0x50008];
+	u8 _res45[0x50010 - 0x50008];
 	u32 gcc_usb4_0_dp0_phy_prim_bcr;
-	u8 _res41[0x52000 - 0x50014];
+	u8 _res46[0x52000 - 0x50014];
 	u32 apcs_clk_br_en;
-	u8 _res42[0x52008 - 0x52004];
+	u8 _res47[0x52008 - 0x52004];
 	u32 apcs_clk_br_en1;
-	u8 _res43[0x52010 - 0x5200c];
+	u8 _res48[0x52010 - 0x5200c];
 	u32 apcs_clk_br_en2;
-	u8 _res44[0x52018 - 0x52014];
+	u8 _res49[0x52018 - 0x52014];
 	u32 apcs_clk_br_en3;
-	u8 _res45[0x52020 - 0x5201c];
+	u8 _res50[0x52020 - 0x5201c];
 	u32 apcs_clk_br_en4;
-	u8 _res46[0x52028 - 0x52024];
+	u8 _res51[0x52028 - 0x52024];
 	u32 apcs_clk_br_en5;
-	u8 _res47[0x52030 - 0x5202c];
+	u8 _res52[0x52030 - 0x5202c];
 	u32 apcs_pll_br_en;
-	u8 _res48[0x54000 - 0x52034];
+	u8 _res53[0x54000 - 0x52034];
 	u32 usb3_uniphy_mp1_bcr;
 	u32 usb3uniphy_phy_mp1_bcr;
 	u32 gcc_usb3_mp_ss1_phy_bcr;
 	u32 gcc_usb3_mp_ss1_phy_gdscr;
-	u8 _res49[0x8e000 - 0x54010];
+	u8 _res54[0x55224 - 0x54010];
+	u32 gcc_lpass_dsp_gdsc_sleep_ena_vote;
+	u8 _res55[0x8e000 - 0x55228];
 	u32 pcie_6_phy_gdscr;
-	u8 _res50[0xa1000 - 0x8e004];
+	u8 _res56[0x99000 - 0x8e004];
+	u32 gcc_lpass_qtb_gdscr;
+	u8 _res57[0x99014 - 0x99004];
+	u32 gcc_lpass_qtb_ahb_cbcr;
+	u32 gcc_lpass_audio_qtb_cbcr;
+	u8 _res58[0x99024 - 0x9901c];
+	u32 gcc_lpass_qosgen_extref_cbcr;
+	u32 gcc_lpass_qdss_tsctr_cbcr;
+	u32 gcc_lpass_qtb_at_cbcr;
+	u32 gcc_lpass_xo_cbcr;
+	u32 gcc_lpass_pwrctl_cbcr;
+	u32 gcc_tcu_lpass_audio_qtb_cbcr;
+	u8 _res59[0xa1000 - 0x9903c];
 	u32 gcc_usb30_sec_bcr;
 	u32 gcc_usb30_sec_gdscr;
-	u8 _res51[0xa1018 - 0xa1008];
+	u8 _res60[0xa1018 - 0xa1008];
 	u32 gcc_usb30_sec_master_cbcr;
-	u8 _res52[0xa1024 - 0xa101c];
+	u8 _res61[0xa1024 - 0xa101c];
 	u32 gcc_usb30_sec_sleep_cbcr;
 	u32 gcc_usb30_sec_mock_utmi_cbcr;
 	struct clock_rcg usb30_sec_master_rcg;
-	u8 _res53[0xa1060 - 0xa1034];
+	u8 _res62[0xa1060 - 0xa1034];
 	u32 gcc_usb3_sec_phy_aux_cbcr;
 	u32 gcc_usb3_sec_phy_com_aux_cbcr;
 	u32 gcc_usb3_sec_phy_pipe_cbcr;
 	u32 gcc_usb3_sec_phy_pipe_muxr;
-	u8 _res54[0xa108c - 0xa1070];
+	u8 _res63[0xa108c - 0xa1070];
 	u32 gcc_cfg_noc_usb3_sec_axi_cbcr;
 	u32 gcc_aggre_usb3_sec_axi_cbcr;
-	u8 _res55[0xa2000 - 0xa1094];
+	u8 _res64[0xa2000 - 0xa1094];
 	u32 gcc_usb30_tert_bcr;
 	u32 gcc_usb30_tert_gdscr;
-	u8 _res56[0xa2018 - 0xa2008];
+	u8 _res65[0xa2018 - 0xa2008];
 	u32 gcc_usb30_tert_master_cbcr;
-	u8 _res57[0xa2024 - 0xa201c];
+	u8 _res66[0xa2024 - 0xa201c];
 	u32 gcc_usb30_tert_sleep_cbcr;
 	u32 gcc_usb30_tert_mock_utmi_cbcr;
-	u8 _res58[0xa2034 - 0xa202c];
+	u8 _res67[0xa2034 - 0xa202c];
 	u32 gcc_usb30_tert_master_m;
 	u32 gcc_usb30_tert_master_n;
 	u32 gcc_usb30_tert_master_d;
-	u8 _res59[0xa2060 - 0xa2040];
+	u8 _res68[0xa2060 - 0xa2040];
 	u32 gcc_usb3_tert_phy_aux_cbcr;
 	u32 gcc_usb3_tert_phy_com_aux_cbcr;
 	u32 gcc_usb3_tert_phy_pipe_cbcr;
 	u32 gcc_usb3_tert_phy_pipe_muxr;
-	u8 _res60[0xa208c - 0xa2070];
+	u8 _res69[0xa208c - 0xa2070];
 	u32 gcc_cfg_noc_usb3_tert_axi_cbcr;
 	u32 gcc_aggre_usb3_tert_axi_cbcr;
-	u8 _res61[0xa3000 - 0xa2094];
+	u8 _res70[0xa3000 - 0xa2094];
 	u32 gcc_usb3_phy_tert_bcr;
 	u32 gcc_usb3phy_phy_tert_bcr;
-	u8 _res62[0xa3010 - 0xa3008];
+	u8 _res71[0xa3010 - 0xa3008];
 	u32 gcc_usb4_2_dp0_phy_tert_bcr;
-	u8 _res63[0xac01c - 0xa3014];
+	u8 _res72[0xac01c - 0xa3014];
 	u32 pcie_6a_phy_bcr;
 };
 
@@ -645,7 +778,16 @@ check_member(x1p42100_gcc, gcc_aggre_usb_noc_axi_cbcr, 0x2d034);
 check_member(x1p42100_gcc, gcc_aggre_noc_usb_south_axi_cbcr, 0x2d174);
 check_member(x1p42100_gcc, gcc_aggre_noc_usb_north_axi_cbcr, 0x2d17c);
 check_member(x1p42100_gcc, qup_wrap0_s, 0x42004);
-check_member(x1p42100_gcc, lpass_cfg_noc_sway_cbcr, 0x47000);
+check_member(x1p42100_gcc, gcc_noc_lpass_dcd_xo_cbcr, 0x45150);
+check_member(x1p42100_gcc, gcc_ddrss_lpass_shub_cbcr, 0x45154);
+check_member(x1p42100_gcc, gcc_lpass_cfg_noc_sway_cbcr, 0x47000);
+check_member(x1p42100_gcc, gcc_qmip_lpass_qtb_ahb_cbcr, 0x47004);
+check_member(x1p42100_gcc, gcc_lpass_aon_noc_ddrss_shub_cbcr, 0x47010);
+check_member(x1p42100_gcc, gcc_lpass_aggre_noc_mpu_client_ddrss_shub_cbcr, 0x47014);
+check_member(x1p42100_gcc, gcc_lpass_hw_af_noc_ddrss_shub_cbcr, 0x47018);
+check_member(x1p42100_gcc, gcc_lpass_aggre_noc_ddrss_shub_cbcr, 0x47024);
+check_member(x1p42100_gcc, lpass_ddrss_shub_rcg, 0x4702c);
+check_member(x1p42100_gcc, gcc_cfg_noc_lpass_cbcr, 0x47160);
 check_member(x1p42100_gcc, qspi_bcr, 0x4b000);
 check_member(x1p42100_gcc, apcs_clk_br_en, 0x52000);
 check_member(x1p42100_gcc, apcs_clk_br_en1, 0x52008);
@@ -655,6 +797,16 @@ check_member(x1p42100_gcc, apcs_clk_br_en4, 0x52020);
 check_member(x1p42100_gcc, apcs_clk_br_en5, 0x52028);
 check_member(x1p42100_gcc, apcs_pll_br_en, 0x52030);
 check_member(x1p42100_gcc, pcie_6_phy_gdscr, 0x8e000);
+check_member(x1p42100_gcc, gcc_lpass_qtb_gdscr, 0x99000);
+check_member(x1p42100_gcc, gcc_lpass_qtb_ahb_cbcr, 0x99014);
+check_member(x1p42100_gcc, gcc_lpass_audio_qtb_cbcr, 0x99018);
+check_member(x1p42100_gcc, gcc_lpass_qosgen_extref_cbcr, 0x99024);
+check_member(x1p42100_gcc, gcc_lpass_qdss_tsctr_cbcr, 0x99028);
+check_member(x1p42100_gcc, gcc_lpass_qtb_at_cbcr, 0x9902c);
+check_member(x1p42100_gcc, gcc_lpass_xo_cbcr, 0x99030);
+check_member(x1p42100_gcc, gcc_lpass_pwrctl_cbcr, 0x99034);
+check_member(x1p42100_gcc, gcc_tcu_lpass_audio_qtb_cbcr, 0x99038);
+check_member(x1p42100_gcc, gcc_lpass_dsp_gdsc_sleep_ena_vote, 0x55224);
 check_member(x1p42100_gcc, pcie_6a_phy_bcr, 0xac01c);
 
 /* Generic QUPV3 wrapper structure - all wrappers have identical layout */
@@ -868,6 +1020,25 @@ enum clk_lpass {
 	LPASS_CLK_COUNT
 };
 
+enum lpass_boot_clk {
+	DDRSS_LPASS_SHUB_CBCR,
+	LPASS_AGGRE_NOC_DDRSS_SHUB_CBCR,
+	LPASS_AGGRE_NOC_MPU_CLIENT_DDRSS_SHUB_CBCR,
+	LPASS_AON_NOC_DDRSS_SHUB_CBCR,
+	LPASS_AUDIO_QTB_CBCR,
+	LPASS_HW_AF_NOC_DDRSS_SHUB_CBCR,
+	LPASS_PWRCTL_CBCR,
+	LPASS_QDSS_TSCTR_CBCR,
+	LPASS_QOSGEN_EXTREF_CBCR,
+	LPASS_QTB_AHB_CBCR,
+	LPASS_QTB_AT_CBCR,
+	LPASS_XO_CBCR,
+	NOC_LPASS_DCD_XO_CBCR,
+	QMIP_LPASS_QTB_AHB_CBCR,
+	TCU_LPASS_AUDIO_QTB_CBCR,
+	LPASS_BOOT_CLK_COUNT
+};
+
 enum subsystem_reset {
 	AOP_RESET_SHFT,
 	CORE_SW_RESET,
@@ -919,6 +1090,13 @@ static struct x1p42100_lpass_audio_cc *const lpass_audio_cc = (void *)LPASS_AUDI
 static struct x1p42100_lpass_aon_cc *const lpass_aon_cc = (void *)LPASS_AON_CC_BASE;
 static struct x1p42100_lpass_aon_cc_pll_clock *const lpass_aon_cc_pll = (void *)LPASS_AON_CC_PLL_CM_BASE;
 static struct x1p42100_lpass_core_gdsc *const lpass_core_gdsc = (void *)LPASS_CORE_GDSC_REG_BASE;
+static struct x1p42100_lpass_core_cc *const lpass_core_cc = (void *)LPASS_LPASS_CORE_CC_REG_BASE;
+static struct x1p42100_lpass_lpicx_noc *const lpass_lpicx_noc = (void *)LPASS_LPICX_NOC_BASE;
+static struct x1p42100_lpass_qdsp6ss_pll_clock *const lpass_qdsp6ss_pll = (void *)LPASS_QDSP6SS_PLL_BASE;
+static struct x1p42100_lpass_qdsp6ss_core_cc *const lpass_qdsp6ss_core_cc = (void *)LPASS_QDSP6SS_CORE_CC_BASE;
+static struct x1p42100_lpass_mcc_lpass_reg *const lpass_mcc_lpass_reg = (void *)LPASS_MCC_LPASS_REG_BASE;
+static struct x1p42100_lpass_ssc_scc *const lpass_ssc_scc = (void *)LPASS_SSC_SCC_BASE;
+static struct x1p42100_lpass_lpi_tcm *const lpass_lpi_tcm = (void *)LPASS_LPI_TCM_REG_BASE;
 
 /* Does nothing */
 #define clock_reset_aop() do {} while (0)
diff --git a/src/soc/qualcomm/x1p42100/include/soc/lpass.h b/src/soc/qualcomm/x1p42100/include/soc/lpass.h
index 0b5a8bd4dd..c3abd43149 100644
--- a/src/soc/qualcomm/x1p42100/include/soc/lpass.h
+++ b/src/soc/qualcomm/x1p42100/include/soc/lpass.h
@@ -3,6 +3,7 @@
 #ifndef _SOC_QUALCOMM_X1P42100_LPASS_H_
 #define _SOC_QUALCOMM_X1P42100_LPASS_H_
 
+#include <soc/addressmap.h>
 #include <types.h>
 
 /* LPASS AON CC PLL Settings */
@@ -20,12 +21,110 @@
 #define HAL_CLK_LPASS_AON_CC_PLL_USER_CTL	0x00E00041
 #define HAL_CLK_LPASS_AON_CC_PLL_USER_CTL_U	0x00000105
 
-#define LPASS_CORE_HM_READY			BIT(0)
-#define HW_CTL					BIT(1)
+enum lpass_voltage_level {
+	LPASS_VOLTAGE_LOWSVS_D1,
+	LPASS_VOLTAGE_LOWSVS,
+	LPASS_VOLTAGE_SVS,
+	LPASS_VOLTAGE_SVS_L1,
+	LPASS_VOLTAGE_NOMINAL,
+	LPASS_VOLTAGE_TURBO,
+	LPASS_VOLTAGE_MAX
+};
+
+/* Default voltage level for boot */
+#define LPASS_DEFAULT_VOLTAGE_LEVEL	LPASS_VOLTAGE_SVS_L1
+
+/* LPASS QDSP6SS PLL user control bit shifts */
+#define QDSP6SS_PLL_PLLOUT_MAIN_SHFT	0
+
+/* LPASS QDSP6SS PLL Settings - Voltage-dependent values */
+#define HAL_CLK_LPASS_QDSP6SS_PLL_L_VALUE_LOWSVS_D1		0x00000018
+#define HAL_CLK_LPASS_QDSP6SS_PLL_ALPHA_VALUE_LOWSVS_D1	0x00000000
+
+#define HAL_CLK_LPASS_QDSP6SS_PLL_L_VALUE_LOWSVS		0x0000001F
+#define HAL_CLK_LPASS_QDSP6SS_PLL_ALPHA_VALUE_LOWSVS		0x00000000
+
+#define HAL_CLK_LPASS_QDSP6SS_PLL_L_VALUE_SVS			0x00000029
+#define HAL_CLK_LPASS_QDSP6SS_PLL_ALPHA_VALUE_SVS		0x00000000
+
+#define HAL_CLK_LPASS_QDSP6SS_PLL_L_VALUE_SVS_L1		0x00000032
+#define HAL_CLK_LPASS_QDSP6SS_PLL_ALPHA_VALUE_SVS_L1		0x00000000
+
+#define HAL_CLK_LPASS_QDSP6SS_PLL_L_VALUE_NOMINAL		0x0000003E
+#define HAL_CLK_LPASS_QDSP6SS_PLL_ALPHA_VALUE_NOMINAL		0x00000000
+
+#define HAL_CLK_LPASS_QDSP6SS_PLL_L_VALUE_TURBO		0x0000004E
+#define HAL_CLK_LPASS_QDSP6SS_PLL_ALPHA_VALUE_TURBO		0x00000000
+
+#define HAL_CLK_LPASS_QDSP6SS_PLL_L_VALUE	HAL_CLK_LPASS_QDSP6SS_PLL_L_VALUE_SVS_L1
+#define HAL_CLK_LPASS_QDSP6SS_PLL_ALPHA_VALUE	HAL_CLK_LPASS_QDSP6SS_PLL_ALPHA_VALUE_SVS_L1
+#define HAL_CLK_LPASS_QDSP6SS_PLL_CAL_L_VALUE	0x00000044
+#define HAL_CLK_LPASS_QDSP6SS_PLL_CONFIG_CTL	0x20485699
+#define HAL_CLK_LPASS_QDSP6SS_PLL_CONFIG_CTL_U	0x00182261
+#define HAL_CLK_LPASS_QDSP6SS_PLL_CONFIG_CTL_U1	0x82AA299C
+#define HAL_CLK_LPASS_QDSP6SS_PLL_TEST_CTL	0x00000000
+#define HAL_CLK_LPASS_QDSP6SS_PLL_TEST_CTL_U	0x00000003
+#define HAL_CLK_LPASS_QDSP6SS_PLL_TEST_CTL_U1	0x00009000
+#define HAL_CLK_LPASS_QDSP6SS_PLL_TEST_CTL_U2	0x00000034
+#define HAL_CLK_LPASS_QDSP6SS_PLL_USER_CTL	0x00000000
+#define HAL_CLK_LPASS_QDSP6SS_PLL_USER_CTL_U	0x00000005
+
+#define LPASS_CORE_HM_READY			(1 << 0)
+#define HW_CTL					(1 << 1)
 #define GDSC_ENABLE_BIT				0
+#define GDSC_RETAIN_FF_ENABLE			(1 << 11)
 
 #define LPASS_CORE_HM_VOTE_POWER_ON		0x0
 #define GDSC_PWR_ON				BIT(31)
-
+#define LPASS_CORE_HM_VOTE_POWER_DOWN		0x1
 #define BCM_LP0_VOTE_VALUE			0x60004001
+
+/* NanoRCG status bits */
+#define LPASS_NANO_RCG_PORT2			(1 << 2)
+
+/* Low power handshake bits */
+#define LPASS_LP_HANDSHAKE_ACK			(1 << 0)  /* Bit 0: ACK status (RO) */
+#define LPASS_LP_HANDSHAKE_ACTIVE		(1 << 1)  /* Bit 1: ACTIVE status (RO) */
+#define LPASS_LP_HANDSHAKE_REQUEST		(1 << 2)  /* Bit 2: REQUEST control (RW) */
+
+/* NTS debug bridge handshake tuning */
+#define LPASS_NTS_HANDSHAKE_TIMEOUT_US		500000
+#define LPASS_NTS_HANDSHAKE_DELAY_US		100
+
+/* Q6 Core RCG configuration */
+#define Q6_CORE_RCG_CFG				0x201
+#define CLK_CTL_CMD_UPDATE_SHFT			0
+#define LPASS_RCG_UPDATE_TIMEOUT_US		100000
+
+/* RSC wait event override mask */
+#define LPASS_RSC_WAIT_EVENT_MASK		0x8
+
+/* CR QCTDD10442361 workaround - NOC island isolation bits */
+#define CHIP_CX_RSCC_BYPASS_EN			(1 << 21)
+#define AON_NOC_STALL_MASK			(1 << 22)
+#define CHIPCX_SBM_FAULTINEN0_PORT0		(1 << 0)
+
+/* TCM (Tightly Coupled Memory) control bits */
+#define LPASS_TCM_MAX_BLOCKS			9
+
+/* Q6 Boot control bits */
+#define BOOT_CORE_START				(1 << 0)
+#define BOOT_FSM_START				(1 << 0)
+#define LPASS_BOOT_FSM_TIMEOUT_US		1000000
+
+#define TCSR_BOOT_IMEM_DISABLE_OFF	0x013300
+#define TCSR_BOOT_IMEM_DISABLE		((void *)(TCSR_BASE + TCSR_BOOT_IMEM_DISABLE_OFF))
+
+enum cb_err lpass_bring_up(void);
+
+/*
+ * Clock workarounds for LPASS clocks.
+ *
+ * Keep these lists declarative (CBCR pointers only); apply behavior in
+ * lpass_apply_clock_workarounds().
+ */
+struct lpass_cbcr_list {
+	uint32_t *cbcr;
+};
+
 #endif /* _SOC_QUALCOMM_X1P42100_LPASS_H_ */
diff --git a/src/soc/qualcomm/x1p42100/include/soc/rpmh_config.h b/src/soc/qualcomm/x1p42100/include/soc/rpmh_config.h
index c1f9c4630c..f6abd98072 100644
--- a/src/soc/qualcomm/x1p42100/include/soc/rpmh_config.h
+++ b/src/soc/qualcomm/x1p42100/include/soc/rpmh_config.h
@@ -31,6 +31,7 @@
 #define RPMH_REGULATOR_LEVEL_MIN_MM0	1
 #define RPMH_REGULATOR_LEVEL_TURBO_MM0	6
 
+#define RPMH_REGULATOR_LEVEL_NOM_L1	5
 #define BCM_MM0_VOTE_VALUE		0x60004001
 
 #define AOP_BOOT_COOKIE			0xA0C00C1E
diff --git a/src/soc/qualcomm/x1p42100/lpass.c b/src/soc/qualcomm/x1p42100/lpass.c
index fb96616dbd..f467bcef38 100644
--- a/src/soc/qualcomm/x1p42100/lpass.c
+++ b/src/soc/qualcomm/x1p42100/lpass.c
@@ -1,12 +1,40 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
 #include <console/console.h>
+#include <delay.h>
 #include <device/mmio.h>
+#include <soc/adsp.h>
+#include <soc/addressmap.h>
 #include <soc/clock.h>
+#include <soc/cmd_db.h>
 #include <soc/lpass.h>
 #include <soc/rpmh_bcm.h>
+#include <soc/rpmh_config.h>
+#include <soc/rpmh_regulator.h>
 #include <timer.h>
 
+/* Debug configuration value (0 = no debug, non-zero = 0x20000000 = enable debug) */
+u32 lpass_q6_debug_val = 0;
+
+static struct clock_freq_config lpass_ddrss_shub_cfg[] = {
+	{
+		.hz = 400 * MHz,
+		.src = SRC_GPLL0_MAIN_600MHZ,
+		.div = QCOM_CLOCK_DIV(1.5),
+	},
+};
+
+/* Configure LPASS DDRSS SHUB RCG (RCGR + M/N) to 400 MHz */
+static void lpass_configure_ddrss_shub_rcg(void)
+{
+	if (clock_configure(&gcc->lpass_ddrss_shub_rcg,
+			    lpass_ddrss_shub_cfg,
+			    400 * MHz, ARRAY_SIZE(lpass_ddrss_shub_cfg)) != CB_SUCCESS) {
+		printk(BIOS_ERR, "LPASS: Failed to configure DDRSS SHUB RCG\n");
+		return;
+	}
+}
+
 static enum cb_err lpass_aon_cc_pll_enable(void)
 {
 	struct alpha_pll_reg_val_config pll_cfg = {0};
@@ -55,15 +83,79 @@ static enum cb_err lpass_aon_cc_pll_enable(void)
 	return CB_SUCCESS;
 }
 
+static enum cb_err lpass_qdsp6ss_pll_enable(void)
+{
+	struct alpha_pll_reg_val_config pll_cfg = {0};
+
+	pll_cfg.reg_mode = &lpass_qdsp6ss_pll->pll_mode;
+	pll_cfg.reg_l = &lpass_qdsp6ss_pll->pll_l_val;
+	pll_cfg.l_val = HAL_CLK_LPASS_QDSP6SS_PLL_L_VALUE_SVS_L1;
+
+	pll_cfg.reg_alpha = &lpass_qdsp6ss_pll->pll_alpha_val;
+	pll_cfg.alpha_val = HAL_CLK_LPASS_QDSP6SS_PLL_ALPHA_VALUE_SVS_L1;
+
+	pll_cfg.reg_cal_l = &lpass_qdsp6ss_pll->pll_l_val;
+	pll_cfg.cal_l_val = HAL_CLK_LPASS_QDSP6SS_PLL_CAL_L_VALUE;
+
+	pll_cfg.reg_config_ctl = &lpass_qdsp6ss_pll->pll_config_ctl;
+	pll_cfg.config_ctl_val = HAL_CLK_LPASS_QDSP6SS_PLL_CONFIG_CTL;
+	pll_cfg.reg_config_ctl_hi = &lpass_qdsp6ss_pll->pll_config_ctl_u;
+	pll_cfg.config_ctl_hi_val = HAL_CLK_LPASS_QDSP6SS_PLL_CONFIG_CTL_U;
+	pll_cfg.reg_config_ctl_hi1 = &lpass_qdsp6ss_pll->pll_config_ctl_u1;
+	pll_cfg.config_ctl_hi1_val = HAL_CLK_LPASS_QDSP6SS_PLL_CONFIG_CTL_U1;
+
+	pll_cfg.reg_user_ctl = &lpass_qdsp6ss_pll->pll_user_ctl;
+	pll_cfg.user_ctl_val = HAL_CLK_LPASS_QDSP6SS_PLL_USER_CTL;
+	pll_cfg.reg_user_ctl_hi = &lpass_qdsp6ss_pll->pll_user_ctl_u;
+	pll_cfg.user_ctl_hi_val = HAL_CLK_LPASS_QDSP6SS_PLL_USER_CTL_U;
+
+	pll_cfg.reg_opmode = &lpass_qdsp6ss_pll->pll_opmode;
+
+	if (clock_configure_enable_gpll(&pll_cfg, false, 0) != CB_SUCCESS) {
+		printk(BIOS_ERR, "LPASS: QDSP6SS PLL configuration failed\n");
+		return CB_ERR;
+	}
+
+	write32(&lpass_qdsp6ss_pll->pll_test_ctl, HAL_CLK_LPASS_QDSP6SS_PLL_TEST_CTL);
+	write32(&lpass_qdsp6ss_pll->pll_test_ctl_u, HAL_CLK_LPASS_QDSP6SS_PLL_TEST_CTL_U);
+	write32(&lpass_qdsp6ss_pll->pll_test_ctl_u1, HAL_CLK_LPASS_QDSP6SS_PLL_TEST_CTL_U1);
+	write32(&lpass_qdsp6ss_pll->pll_test_ctl_u2, HAL_CLK_LPASS_QDSP6SS_PLL_TEST_CTL_U2);
+
+	if (lucidole_pll_enable(&pll_cfg) != CB_SUCCESS) {
+		printk(BIOS_ERR, "LPASS: QDSP6SS PLL enable failed\n");
+		return CB_ERR;
+	}
+
+	/* Enable PLLOUT_MAIN for QDSP6SS PLL */
+	setbits32(&lpass_qdsp6ss_pll->pll_user_ctl, BIT(QDSP6SS_PLL_PLLOUT_MAIN_SHFT));
+
+	/* Configure Q6 Core RCG */
+	write32(&lpass_qdsp6ss_core_cc->core_cfg_rcgr, Q6_CORE_RCG_CFG);
+	setbits32(&lpass_qdsp6ss_core_cc->core_cmd_rcgr, BIT(CLK_CTL_CMD_UPDATE_SHFT));
+
+	/* Wait for RCG update */
+	if (!wait_us(LPASS_RCG_UPDATE_TIMEOUT_US,
+		     !(read32(&lpass_qdsp6ss_core_cc->core_cmd_rcgr) &
+		       BIT(CLK_CTL_CMD_UPDATE_SHFT)))) {
+		printk(BIOS_ERR, "LPASS: RCG update timeout\n");
+		return CB_ERR;
+	}
+
+	/* Enable QDSP6 core clock */
+	setbits32(&lpass_qdsp6ss_core_cc->core_cbcr, BIT(CLK_CTL_EN_SHFT));
+
+	return CB_SUCCESS;
+}
+
 static enum cb_err lpass_setup_core_infrastructure(void)
 {
 
-	if (clock_enable(&gcc->lpass_cfg_noc_sway_cbcr) != CB_SUCCESS) {
+	if (clock_enable(&gcc->gcc_lpass_cfg_noc_sway_cbcr) != CB_SUCCESS) {
 		printk(BIOS_ERR, "LPASS: Failed to enable CFG NOC SWAY clock\n");
 		return CB_ERR;
 	}
 
-	setbits32(&lpass_core_gdsc->lpass_top_cc_lpass_core_sway_ahb_ls_cbcr, HW_CTL);
+	clock_configure_hw_ctl(&lpass_core_gdsc->lpass_top_cc_lpass_core_sway_ahb_ls_cbcr, true);
 
 	write32(&lpass_aon_cc->lpass_hm_collapse_vote_for_q6, LPASS_CORE_HM_VOTE_POWER_ON);
 
@@ -77,9 +169,49 @@ static enum cb_err lpass_setup_core_infrastructure(void)
 		return CB_ERR;
 	}
 
+	/* Enable retention */
+	setbits32(&lpass_core_gdsc->core_hm_gdscr, GDSC_RETAIN_FF_ENABLE);
+
+	/* Enable SYSNOC interface */
+	if (clock_enable(&lpass_core_cc->lpass_lpass_core_cc_sysnoc_mport_core_cbcr) != CB_SUCCESS) {
+		printk(BIOS_ERR, "LPASS: Failed to enable SYSNOC interface\n");
+		return CB_ERR;
+	}
+
 	return CB_SUCCESS;
 }
 
+static const struct lpass_cbcr_list lpass_rpmh_ignore_clks[] = {
+	{ &gcc->gcc_ddrss_lpass_shub_cbcr },
+	{ &gcc->gcc_tcu_lpass_audio_qtb_cbcr },
+};
+
+static const struct lpass_cbcr_list lpass_pmu_ignore_clks[] = {
+	{ &gcc->gcc_lpass_hw_af_noc_ddrss_shub_cbcr },
+	{ &gcc->gcc_lpass_aggre_noc_ddrss_shub_cbcr },
+	{ &gcc->gcc_lpass_aggre_noc_mpu_client_ddrss_shub_cbcr },
+};
+
+/* Boot clocks (GCC CBCRs). */
+static u32 *lpass_boot_cbcr[LPASS_BOOT_CLK_COUNT] = {
+	[DDRSS_LPASS_SHUB_CBCR]                     = &gcc->gcc_ddrss_lpass_shub_cbcr,
+	[LPASS_AGGRE_NOC_DDRSS_SHUB_CBCR]           = &gcc->gcc_lpass_aggre_noc_ddrss_shub_cbcr,
+	[LPASS_AGGRE_NOC_MPU_CLIENT_DDRSS_SHUB_CBCR] = &gcc->gcc_lpass_aggre_noc_mpu_client_ddrss_shub_cbcr,
+	[LPASS_AON_NOC_DDRSS_SHUB_CBCR]             = &gcc->gcc_lpass_aon_noc_ddrss_shub_cbcr,
+	[LPASS_AUDIO_QTB_CBCR]                      = &gcc->gcc_lpass_audio_qtb_cbcr,
+	[LPASS_HW_AF_NOC_DDRSS_SHUB_CBCR]           = &gcc->gcc_lpass_hw_af_noc_ddrss_shub_cbcr,
+	[LPASS_PWRCTL_CBCR]                         = &gcc->gcc_lpass_pwrctl_cbcr,
+	[LPASS_QDSS_TSCTR_CBCR]                     = &gcc->gcc_lpass_qdss_tsctr_cbcr,
+	[LPASS_QOSGEN_EXTREF_CBCR]                  = &gcc->gcc_lpass_qosgen_extref_cbcr,
+	[LPASS_QTB_AHB_CBCR]                        = &gcc->gcc_lpass_qtb_ahb_cbcr,
+	[LPASS_QTB_AT_CBCR]                         = &gcc->gcc_lpass_qtb_at_cbcr,
+	[LPASS_XO_CBCR]                             = &gcc->gcc_lpass_xo_cbcr,
+	[NOC_LPASS_DCD_XO_CBCR]                     = &gcc->gcc_noc_lpass_dcd_xo_cbcr,
+	[QMIP_LPASS_QTB_AHB_CBCR]                   = &gcc->gcc_qmip_lpass_qtb_ahb_cbcr,
+	[TCU_LPASS_AUDIO_QTB_CBCR]                  = &gcc->gcc_tcu_lpass_audio_qtb_cbcr,
+};
+
+/* Array mapping enum clk_lpass to actual CBCR registers */
 static u32 *lpass_cbcr[LPASS_CLK_COUNT] = {
 	[LPASS_CODEC_MEM_CBCR] = &lpass_audio_cc->codec_mem_cbcr,
 	[LPASS_CODEC_MEM0_CBCR] = &lpass_audio_cc->codec_mem0_cbcr,
@@ -114,15 +246,323 @@ static enum cb_err lpass_audio_clocks_enable(void)
 	return CB_SUCCESS;
 }
 
-enum cb_err lpass_init(void)
+static enum cb_err lpass_rpmh_bcm_vote(void)
 {
+	struct rpmh_vreg arc_reg;
+	enum cb_err ret;
 	int rc;
+	volatile u32 *boot_cookie = (volatile u32 *)AOP_BOOT_COOKIE_ADDR;
+
+	if (!wait_us(AOP_BOOT_TIMEOUT_US, *boot_cookie == AOP_BOOT_COOKIE)) {
+		printk(BIOS_ERR,
+		       "AOP not booted after %dus (cookie: 0x%x, expected: 0x%x)\n",
+		       AOP_BOOT_TIMEOUT_US, *boot_cookie, AOP_BOOT_COOKIE);
+		return CB_ERR;
+	}
+
+	ret = cmd_db_ready();
+	if (ret != CB_SUCCESS) {
+		ret = cmd_db_init(CMD_DB_BASE_ADDR, CMD_DB_SIZE);
+		if (ret != CB_SUCCESS) {
+			printk(BIOS_ERR, "CMD_DB: init failed\n");
+			return CB_ERR;
+		}
+	}
+
+	rc = rpmh_rsc_init();
+	if (rc) {
+		printk(BIOS_ERR, "RPMH_RSC: init failed\n");
+		return CB_ERR;
+	}
+
+	/* Initialize LCX ARC regulator for LPASS power rail */
+	rc = rpmh_regulator_init(&arc_reg, "lcx.lvl", RPMH_REGULATOR_TYPE_ARC);
+	if (rc) {
+		printk(BIOS_ERR, "Failed to initialize LPASS power rail lcx ARC regulator\n");
+		return CB_ERR;
+	}
+
+	/* Set LCX level to NOM_L1 */
+	rc = rpmh_regulator_arc_set_level(&arc_reg, RPMH_REGULATOR_LEVEL_NOM_L1, true, false);
+	if (rc) {
+		printk(BIOS_ERR, "Failed to set LCX ARC level\n");
+		return CB_ERR;
+	}
+
 	rc = rpmh_bcm_vote("LP0", BCM_LP0_VOTE_VALUE);
 	if (rc) {
 		printk(BIOS_ERR, "LPASS: Failed to send BCM vote for LPASS bus clock manager LP0\n");
 		return CB_ERR;
 	}
 
+	return CB_SUCCESS;
+}
+
+static void lpass_apply_clock_workarounds(void)
+{
+	size_t i;
+
+	/* CR QCTDD08205470: ignore RPMh clock disable for TCU-QTB link clocks. */
+	for (i = 0; i < ARRAY_SIZE(lpass_rpmh_ignore_clks); i++)
+		clock_configure_ignore_rpmh_clk_dis(lpass_rpmh_ignore_clks[i].cbcr, true);
+
+	/* CR-3409636: keep AON NOC DDRSS SHUB clock enabled during sleep fencing. */
+	clock_configure_ignore_rpmh_clk_dis(&gcc->gcc_lpass_aon_noc_ddrss_shub_cbcr, true);
+
+	/* PMU-GCC spec: ignore PMU clock disable for these clocks. */
+	for (i = 0; i < ARRAY_SIZE(lpass_pmu_ignore_clks); i++)
+		clock_configure_ignore_pmu_clk_dis(lpass_pmu_ignore_clks[i].cbcr, true);
+
+	/* Prevent automatic GDSC collapse (HW defaults enable it). */
+	write32(&gcc->gcc_lpass_dsp_gdsc_sleep_ena_vote, 0x0);
+}
+
+static enum cb_err lpass_enable_boot_clocks(void)
+{
+	size_t i;
+	enum cb_err ret;
+
+	/* Configure LPASS DDRSS SHUB RCG */
+	lpass_configure_ddrss_shub_rcg();
+
+	/* Enable QTB power domain */
+	if (enable_and_poll_gdsc_status(&gcc->gcc_lpass_qtb_gdscr) != CB_SUCCESS) {
+		printk(BIOS_ERR, "LPASS: Failed to enable QTB GDSC\n");
+		return CB_ERR;
+	}
+
+	/* Ensure IGNORE_RPMH_CLK_DIS is set before enabling TCU-QTB link clock. */
+	clock_configure_ignore_rpmh_clk_dis(&gcc->gcc_tcu_lpass_audio_qtb_cbcr, true);
+
+	for (i = 0; i < LPASS_BOOT_CLK_COUNT; i++) {
+		ret = clock_enable(lpass_boot_cbcr[i]);
+		if (ret != CB_SUCCESS)
+			printk(BIOS_WARNING, "LPASS: Failed to enable boot clock %zu: %p\n", i, lpass_boot_cbcr[i]);
+	}
+
+	return CB_SUCCESS;
+}
+
+static enum cb_err lpass_enable_ssc_smem_clock(void)
+{
+	if (clock_enable(&lpass_ssc_scc->ssc_scc_smem_cbcr) != CB_SUCCESS) {
+		printk(BIOS_ERR, "LPASS: Failed to enable SSC_SCC_SMEM clock\n");
+		return CB_ERR;
+	}
+	return CB_SUCCESS;
+}
+
+static enum cb_err lpass_debug_bridge_setup(void)
+{
+	if (clock_enable(&lpass_aon_cc->at_cbcr) != CB_SUCCESS) {
+		printk(BIOS_ERR, "LPASS: Failed to enable AT clock\n");
+		return CB_ERR;
+	}
+
+	if (clock_enable(&lpass_aon_cc->pclkdbg_cbcr) != CB_SUCCESS) {
+		printk(BIOS_ERR, "LPASS: Failed to enable PCLKDBG clock\n");
+		return CB_ERR;
+	}
+
+	/* Allow debug bridge clocks/paths to settle before requesting handshake. */
+	udelay(LPASS_NTS_HANDSHAKE_DELAY_US);
+
+	/*
+	 * In order to attach debugger T32 APB, DAP and NTS bridges need to be enabled
+	 */
+	setbits32(&lpass_mcc_lpass_reg->atb_low_power_handshake, LPASS_LP_HANDSHAKE_REQUEST);
+	setbits32(&lpass_mcc_lpass_reg->apb_low_power_handshake, LPASS_LP_HANDSHAKE_REQUEST);
+	setbits32(&lpass_mcc_lpass_reg->nts_low_power_handshake, LPASS_LP_HANDSHAKE_REQUEST);
+	dsb();
+
+	/*
+	 * Wait for NTS ACK
+	 */
+	if (!wait_us(LPASS_NTS_HANDSHAKE_TIMEOUT_US,
+		     read32(&lpass_mcc_lpass_reg->nts_low_power_handshake) & LPASS_LP_HANDSHAKE_ACK)) {
+		printk(BIOS_WARNING, "LPASS: NTS handshake timeout (NTS=0x%x)\n",
+		       read32(&lpass_mcc_lpass_reg->nts_low_power_handshake));
+		/* Non-fatal: continue boot even if debug bridge handshake doesn't complete */
+	}
+
+	return CB_SUCCESS;
+}
+
+/* Enable TCM blocks for LPASS processor memory access. */
+static void lpass_tcm_init(void)
+{
+	uint32_t block;
+
+	if (clock_enable(&lpass_lpi_tcm->axis_hs_cbcr) != CB_SUCCESS) {
+		printk(BIOS_WARNING, "LPASS: Failed to enable TCM AXIS HS clock\n");
+		return;
+	}
+
+	/* Initialize all TCM 256KB blocks (n=0..9) */
+	for (block = 0; block <= LPASS_TCM_MAX_BLOCKS; block++) {
+		clock_configure_force_mem_core_on(&lpass_lpi_tcm->tcm_256kb_block_cbcr[block], true);
+
+		if (clock_enable(&lpass_lpi_tcm->tcm_256kb_block_cbcr[block]) != CB_SUCCESS) {
+			printk(BIOS_WARNING, "LPASS: Failed to enable TCM block %d clock\n", block);
+			return;
+		}
+	}
+}
+
+static enum cb_err setup_lpass_processor(void)
+{
+	/* HW_CTL settings */
+	clock_configure_hw_ctl(&gcc->gcc_ddrss_lpass_shub_cbcr, false);
+
+	/* Enable boot clocks */
+	if (lpass_enable_boot_clocks() != CB_SUCCESS) {
+		printk(BIOS_ERR, "LPASS: Failed to enable boot clocks\n");
+		return CB_ERR;
+	}
+
+	/* Apply clock workarounds */
+	lpass_apply_clock_workarounds();
+
+	/* HPG Step 4: Enable LPASS access */
+	if (clock_enable(&gcc->gcc_cfg_noc_lpass_cbcr) != CB_SUCCESS) {
+		printk(BIOS_ERR, "LPASS: Failed to enable CFG NOC access\n");
+		return CB_ERR;
+	}
+
+	/* HPG Step 11: Program LPASS_QDSP6SS_RET_CFG = 0x0 (CR QCTDD10415825) */
+	write32(&lpass_qdsp6ss->ret_cfg, 0);
+
+	/* HPG Step 12: Check NanoRCG and enable LPI_NOC_HS conditionally */
+	if ((read32(&lpass_lpicx_noc->sidebandmanager_rcg_sbm_flagoutstatus0_low) & LPASS_NANO_RCG_PORT2) == 0) {
+		if (clock_enable(&lpass_aon_cc->lpi_noc_hs_cbcr) != CB_SUCCESS) {
+			printk(BIOS_ERR, "LPASS: Failed to enable LPI NOC HS clock\n");
+			return CB_ERR;
+		}
+	} else {
+		if (clock_disable(&lpass_aon_cc->lpi_noc_hs_cbcr) != CB_SUCCESS) {
+			printk(BIOS_ERR, "LPASS: Failed to disable LPI NOC HS clock\n");
+			return CB_ERR;
+		}
+	}
+	/* HPG Step 13: Enable Q6 AXIM clock after NanoRCG-based LPI_NOC_HS handling */
+	if (clock_enable(&lpass_aon_cc->q6_axim_cbcr) != CB_SUCCESS) {
+		printk(BIOS_ERR, "LPASS: Failed to enable Q6 AXIM clock\n");
+		return CB_ERR;
+	}
+
+	/* Configure debug register */
+	write32(&lpass_qdsp6ss->dbg_cfg, lpass_q6_debug_val);
+
+	write32(&lpass_mcc_lpass_reg->rsc_wait_event_ovrd_mask, LPASS_RSC_WAIT_EVENT_MASK);
+
+	/* Initialize TCM */
+	lpass_tcm_init();
+
+	/* Enable Q6_AHBM clock for PRAM access */
+	if (clock_enable(&lpass_aon_cc->q6_ahbm_cbcr) != CB_SUCCESS) {
+		printk(BIOS_ERR, "LPASS: Failed to enable Q6_AHBM clock\n");
+		return CB_ERR;
+	}
+
+	/* Enable SSC_SCC_SMEM clock */
+	if (lpass_enable_ssc_smem_clock() != CB_SUCCESS) {
+		printk(BIOS_ERR, "LPASS: Failed to enable SSC_SCC_SMEM clock\n");
+		return CB_ERR;
+	}
+
+	/* Setup debug bridges if debug is enabled */
+	if (lpass_q6_debug_val != 0) {
+		if (lpass_debug_bridge_setup() != CB_SUCCESS)
+			printk(BIOS_WARNING, "LPASS: Debug bridge setup failed\n");
+	}
+	/* Enable QDSP6SS PLL */
+	if (lpass_qdsp6ss_pll_enable() != CB_SUCCESS) {
+		printk(BIOS_ERR, "LPASS: Failed to enable QDSP6SS PLL\n");
+		return CB_ERR;
+	}
+
+	/* CR QCTDD10442361: mask RSCp trigger and disable CHIP_CX QCHANNEL timeout SBM. */
+	/* HPG Step 24.e: Set CHIP_CX_RSCC_BYPASS_EN = 1 */
+	setbits32(&lpass_aon_cc->lpass_noc_island_isolation, CHIP_CX_RSCC_BYPASS_EN);
+
+	/* HPG Step 24.f: Set AON_NOC_STALL_MASK = 0 */
+	clrbits32(&lpass_aon_cc->lpass_noc_island_isolation, AON_NOC_STALL_MASK);
+
+	/* HPG Step 24.g: Set Port0 = 0 */
+	clrbits32(&lpass_lpicx_noc->sidebandmanager_chipcx_sbm_faultinen0_low,
+		  CHIPCX_SBM_FAULTINEN0_PORT0);
+
+	clock_configure_hw_ctl(&gcc->gcc_lpass_aon_noc_ddrss_shub_cbcr, true);
+
+	printk(BIOS_INFO, "LPASS: Processor setup complete\n");
+	return CB_SUCCESS;
+}
+
+static enum cb_err enable_lpass_processor(void)
+{
+	/* HPG Step 14: Q6 boot sequence */
+	/*
+	 * De-assert QDSP6 stop core. QDSP6 will execute instructions after out of reset.
+	 */
+	setbits32(&lpass_qdsp6ss->boot_core_start, BOOT_CORE_START);
+
+	/*
+	 * Trigger boot FSM to start QDSP6 out of reset sequence.
+	 */
+	write32(&lpass_qdsp6ss->boot_cmd, BOOT_FSM_START);
+	dsb();
+
+	/* Wait for boot FSM completion */
+	if (!wait_us(LPASS_BOOT_FSM_TIMEOUT_US, read32(&lpass_qdsp6ss->boot_status) != 0)) {
+		printk(BIOS_ERR, "LPASS: Boot FSM timeout (boot_status=0x%x)\n",
+		       read32(&lpass_qdsp6ss->boot_status));
+		return CB_ERR;
+	}
+
+	/* Wait for core to come out of reset */
+	udelay(5);
+
+	/* HPG Step 19: Disable Q6_AXIM clock after Q6 boots */
+	if (clock_disable(&lpass_aon_cc->q6_axim_cbcr) != CB_SUCCESS) {
+		printk(BIOS_ERR, "LPASS: Failed to disable Q6_AXIM clock\n");
+		return CB_ERR;
+	}
+
+	printk(BIOS_INFO, "LPASS: Q6 processor enabled\n");
+	return CB_SUCCESS;
+}
+
+enum cb_err lpass_bring_up(void)
+{
+	if (lpass_init() != CB_SUCCESS) {
+		printk(BIOS_ERR, "LPASS: lpass_init() failed\n");
+		return CB_ERR;
+	}
+
+	if (setup_lpass_processor() != CB_SUCCESS) {
+		printk(BIOS_ERR, "LPASS: Failed to setup LPASS processor\n");
+		return CB_ERR;
+	}
+
+	/* Disable BOOT IMEM */
+	write32((void *)TCSR_BOOT_IMEM_DISABLE, 0x1);
+
+	/* Boot the LPASS Q6 processor */
+	if (enable_lpass_processor() != CB_SUCCESS) {
+		printk(BIOS_ERR, "LPASS: Failed to enable LPASS processor\n");
+		return CB_ERR;
+	}
+
+	return CB_SUCCESS;
+}
+
+enum cb_err lpass_init(void)
+{
+	if (lpass_rpmh_bcm_vote() != CB_SUCCESS) {
+		printk(BIOS_ERR, "LPASS: Failed to initialize RPMH BCM vote\n");
+		return CB_ERR;
+	}
+
 	if (enable_and_poll_gdsc_status(&lpass_aon_cc->lpass_audio_hm_gdscr) != CB_SUCCESS) {
 		printk(BIOS_ERR, "LPASS: Failed to enable Core HM GDSC\n");
 		return CB_ERR;

From 9a86b9f729fa265185e95ea73a5394b72f6b353e Mon Sep 17 00:00:00 2001
From: Hari L <haril@qualcomm.corp-partner.google.com>
Date: Tue, 10 Mar 2026 17:23:12 +0530
Subject: [PATCH 3795/3886] mb/google/bluey: Integrate ADSP load and LPASS
 bring-up into charging flow
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Load ADSP firmware and then bring up LPASS/Q6 during the Bluey charging sequence.
This ensures ADSP‑dependent fast charging works reliably.

TEST:
 - Built and booted image.serial.bin on X1P42100.
 - Verified ADSP DTB and firmware load over UART.
 - Verified Q6 and LPASS init during cold boot.
 - Verified charging flow: device entered charging mode, battery current (~3550 mA)
   reported, and CRD RED LED glowed.

Change-Id: I6a1326f4271c5121cd7284d64b2912505b2a93a2
Signed-off-by: Hari L <haril@qualcomm.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91564
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Jayvik Desai <jayvik@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/google/bluey/board.h     |  1 +
 src/mainboard/google/bluey/charging.c  | 18 ++++++++++++++++++
 src/mainboard/google/bluey/mainboard.c |  3 +--
 3 files changed, 20 insertions(+), 2 deletions(-)

diff --git a/src/mainboard/google/bluey/board.h b/src/mainboard/google/bluey/board.h
index 04ef0ca3c1..b7084a30d5 100644
--- a/src/mainboard/google/bluey/board.h
+++ b/src/mainboard/google/bluey/board.h
@@ -65,5 +65,6 @@ void configure_debug_access_port(void);
 void enable_slow_battery_charging(void);
 void disable_slow_battery_charging(void);
 void launch_charger_applet(void);
+void enable_fast_battery_charging(void);
 
 #endif /* MAINBOARD_GOOGLE_BLUEY_BOARD_H */
diff --git a/src/mainboard/google/bluey/charging.c b/src/mainboard/google/bluey/charging.c
index c8b1126a42..a499ca5888 100644
--- a/src/mainboard/google/bluey/charging.c
+++ b/src/mainboard/google/bluey/charging.c
@@ -5,6 +5,8 @@
 #include <delay.h>
 #include <ec/google/chromeec/ec.h>
 #include <reset.h>
+#include <soc/adsp.h>
+#include <soc/lpass.h>
 #include <soc/pmic.h>
 #include <soc/qcom_spmi.h>
 #include <soc/qcom_tsens.h>
@@ -276,3 +278,19 @@ void disable_slow_battery_charging(void)
 	spmi_write8(SMB1_CHGR_MAX_FCC_CFG, FCC_DISABLE);
 	spmi_write8(SMB2_CHGR_MAX_FCC_CFG, FCC_DISABLE);
 }
+
+/*
+ * Enable fast battery charging with ADSP support.
+ *
+ * This function loads ADSP firmware and configures fast charging.
+ */
+void enable_fast_battery_charging(void)
+{
+	/* Load ADSP firmware first */
+	adsp_fw_load();
+
+	/* Bring up LPASS/QDSP6 (ADSP) for ADSP-dependent charging support */
+	if (lpass_bring_up() != CB_SUCCESS) {
+		printk(BIOS_ERR, "LPASS bring-up failed; skipping fast charging.\n");
+	}
+}
diff --git a/src/mainboard/google/bluey/mainboard.c b/src/mainboard/google/bluey/mainboard.c
index 1b9b9955a2..306fefafe9 100644
--- a/src/mainboard/google/bluey/mainboard.c
+++ b/src/mainboard/google/bluey/mainboard.c
@@ -188,8 +188,7 @@ static void trigger_critical_battery_shutdown(void)
  */
 static void handle_low_power_charging_boot(void)
 {
-	/* TODO: enable fast charging */
-	enable_slow_battery_charging();
+	enable_fast_battery_charging();
 
 	/*
 	 * Disable the lightbar for Low-Battery or Off-Mode charging sequences.

From 521e7949c1397f633905be2920e4d0d524666a42 Mon Sep 17 00:00:00 2001
From: Kirubakaran E <kirue@qualcomm.corp-partner.google.com>
Date: Wed, 18 Mar 2026 10:06:55 -0700
Subject: [PATCH 3796/3886] =?UTF-8?q?mb/google/bluey:=20Add=20support=20to?=
 =?UTF-8?q?=20reduce=20CPU=20clock=20to=20minimum=20frequency=20during=20O?=
 =?UTF-8?q?FF=E2=80=91mode=20charging?=
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

This change adds support to drop the CPU frequency to the minimum
806 MHz when the device enters OFF‑mode charging, improving power
efficiency. The register details are available in the
HRD-X1P42100-S1 hardware document:
https://docs.qualcomm.com/bundle/resource/topics/HRD-X1P42100-S1/

Tested by creating an image.serial.bin and verifying that it boots
on X1P42100 and the CPU runs at 806 MHz during OFF‑mode charging.

Change-Id: I8f0d5b598a4dad419195957be8b334a27ec18982
Signed-off-by: Kirubakaran E <kirue@qualcomm.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91727
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Jayvik Desai <jayvik@google.com>
---
 src/mainboard/google/bluey/mainboard.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/src/mainboard/google/bluey/mainboard.c b/src/mainboard/google/bluey/mainboard.c
index 306fefafe9..1395c097dd 100644
--- a/src/mainboard/google/bluey/mainboard.c
+++ b/src/mainboard/google/bluey/mainboard.c
@@ -188,6 +188,9 @@ static void trigger_critical_battery_shutdown(void)
  */
 static void handle_low_power_charging_boot(void)
 {
+	if (!pll_init_and_set(apss_ncc0, L_VAL_806MHz))
+		printk(BIOS_DEBUG, "CPU Frequency set to 806MHz\n");
+
 	enable_fast_battery_charging();
 
 	/*

From 710df3347106b079237e6a35c5b4b00007adea5e Mon Sep 17 00:00:00 2001
From: Kapil Porwal <kapilporwal@google.com>
Date: Mon, 16 Mar 2026 16:08:46 +0530
Subject: [PATCH 3797/3886] mb/google/bluey: Signal ADSP to skip Type-C port
 resets during boot

During certain boot sequences, such as low-battery or off-mode charging,
automatic USB Type-C port resets initiated by the ADSP can cause
unnecessary power fluctuations or connectivity drops.

Implement adsp_skip_port_reset(), which toggles the SKIP_PORT_RESET bit
in the PMIC_PD_NEGOTIATION_FLAG register. This bit informs the ADSP
firmware to bypass its default port reset logic. Use this during
low-power charging initialization to ensure a more stable boot process.

BUG=b:436391478
TEST=Verify no unexpected port resets occur during Google/Quartz boot.

Change-Id: I215a1806799a10355dd36b483f8d441f615f5258
Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91666
Reviewed-by: Jayvik Desai <jayvik@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/google/bluey/charging.c | 15 +++++++++++++++
 1 file changed, 15 insertions(+)

diff --git a/src/mainboard/google/bluey/charging.c b/src/mainboard/google/bluey/charging.c
index a499ca5888..1461ab86f9 100644
--- a/src/mainboard/google/bluey/charging.c
+++ b/src/mainboard/google/bluey/charging.c
@@ -40,6 +40,9 @@
 #define EN_DEBUG_ACCESS_SRC 0x01
 #define EN_SWITCHER_DAM_500 0x05
 
+#define PMIC_PD_NEGOTIATION_FLAG	0x7E7C
+#define SKIP_PORT_RESET			0x08
+
 #define PMC8380F_SLAVE_ID	0x05
 #define GPIO07_MODE_CTL			0x8E40
 #define GPIO07_DIG_OUT_SOURCE_CTL	0x8E44
@@ -279,6 +282,16 @@ void disable_slow_battery_charging(void)
 	spmi_write8(SMB2_CHGR_MAX_FCC_CFG, FCC_DISABLE);
 }
 
+/*
+ * Instruct ADSP to skip type-c port resets
+ */
+static void adsp_skip_port_reset(void)
+{
+	uint8_t flags = (uint8_t)spmi_read8(PMIC_PD_NEGOTIATION_FLAG);
+	spmi_write8(PMIC_PD_NEGOTIATION_FLAG, flags | SKIP_PORT_RESET);
+	printk(BIOS_INFO, "Configured ADSP to avoid port resets\n");
+}
+
 /*
  * Enable fast battery charging with ADSP support.
  *
@@ -286,6 +299,8 @@ void disable_slow_battery_charging(void)
  */
 void enable_fast_battery_charging(void)
 {
+	adsp_skip_port_reset();
+
 	/* Load ADSP firmware first */
 	adsp_fw_load();
 

From 1769b10be0dc1c80bc0c38f640a3d20b02d7af5d Mon Sep 17 00:00:00 2001
From: Subrata Banik <subratabanik@google.com>
Date: Tue, 24 Mar 2026 23:42:27 +0530
Subject: [PATCH 3798/3886] mb/google/bluey: Lower CPU frequency to 710.4MHz
 for low-power boot

In scenarios where the system is booting with a critical or low battery,
lowering the initial CPU frequency helps reduce the instantaneous power
draw, ensuring the battery can sustain the boot process while fast
charging is being enabled.

Changes:
- clock.h: Replace 806MHz (0x2A) with 710.4MHz (0x25) based on 19.2MHz
  XO.
- mainboard.c: Update handle_low_power_charging_boot() to use the
  new L-VAL and update the debug log accordingly.

BUG=b:436391478

Change-Id: Ida30824e344a4613c797083711c3f6ee31f9694d
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91838
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Jayvik Desai <jayvik@google.com>
---
 src/mainboard/google/bluey/mainboard.c        | 4 ++--
 src/soc/qualcomm/x1p42100/include/soc/clock.h | 2 +-
 2 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/src/mainboard/google/bluey/mainboard.c b/src/mainboard/google/bluey/mainboard.c
index 1395c097dd..5bb9ecd21d 100644
--- a/src/mainboard/google/bluey/mainboard.c
+++ b/src/mainboard/google/bluey/mainboard.c
@@ -188,8 +188,8 @@ static void trigger_critical_battery_shutdown(void)
  */
 static void handle_low_power_charging_boot(void)
 {
-	if (!pll_init_and_set(apss_ncc0, L_VAL_806MHz))
-		printk(BIOS_DEBUG, "CPU Frequency set to 806MHz\n");
+	if (!pll_init_and_set(apss_ncc0, L_VAL_710P4MHz))
+		printk(BIOS_DEBUG, "CPU Frequency set to 710MHz\n");
 
 	enable_fast_battery_charging();
 
diff --git a/src/soc/qualcomm/x1p42100/include/soc/clock.h b/src/soc/qualcomm/x1p42100/include/soc/clock.h
index b60ea039c8..fa3fe899ef 100644
--- a/src/soc/qualcomm/x1p42100/include/soc/clock.h
+++ b/src/soc/qualcomm/x1p42100/include/soc/clock.h
@@ -21,7 +21,7 @@
 /* CPU PLL*/
 #define L_VAL_2995P2MHz		0x9C
 #define L_VAL_1363P2MHz		0x47
-#define L_VAL_806MHz		0x2A
+#define L_VAL_710P4MHz		0x25
 
 /* DISP PLL */
 #define L_VAL_1725MHz		0x59

From ecab79365054c6f3582ef09528424130f8c7ac87 Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Wed, 18 Mar 2026 18:35:51 -0500
Subject: [PATCH 3799/3886] ec/chromeec: Add Kconfig and asl for vendor tablet
 ACPI

Introduce EC_CHROMEEC_USE_VENDOR_TABLET_CONTROLS to control inclusion of
Intel VBTN and AMD VGBI ACPI devices used for tablet/convertible mode.
Default is y for non-ChromeOS builds when the board selects
SYSTEM_TYPE_CONVERTIBLE or SYSTEM_TYPE_DETACHABLE.

Add vbtn.asl (Intel INT33D6/INT33D3) and vgbi.asl (AMD AMD33D6/AMD33D3).
In ec.asl, gate VBTN/VGBI notify and these includes on the new config.

Boards that are convertibles or detachables will enable the vendor
tablet controls by selecting the appropriate SMBIOS enclosure type in
subsequent changes.

Change-Id: I208c1f1856a9223af5109464ecf316e76de3a976
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91742
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
---
 src/ec/google/chromeec/Kconfig       |  8 ++++++
 src/ec/google/chromeec/acpi/ec.asl   | 21 +++++++++++++++
 src/ec/google/chromeec/acpi/vbtn.asl | 38 ++++++++++++++++++++++++++++
 src/ec/google/chromeec/acpi/vgbi.asl | 30 ++++++++++++++++++++++
 4 files changed, 97 insertions(+)
 create mode 100644 src/ec/google/chromeec/acpi/vbtn.asl
 create mode 100644 src/ec/google/chromeec/acpi/vgbi.asl

diff --git a/src/ec/google/chromeec/Kconfig b/src/ec/google/chromeec/Kconfig
index 081f7cb754..223d7caa6c 100644
--- a/src/ec/google/chromeec/Kconfig
+++ b/src/ec/google/chromeec/Kconfig
@@ -267,6 +267,14 @@ config EC_GOOGLE_CHROMEEC_LED_CONTROL
 	  Enable manual AP control over ChromeEC LEDs/lightbars to ensure
 	  visual continuity with AP-side boot animations.
 
+config EC_CHROMEEC_USE_VENDOR_TABLET_CONTROLS
+	bool "Include vendor tablet mode controls (VBTN/VGBI) in ACPI"
+	default y if !CHROMEOS && (SYSTEM_TYPE_CONVERTIBLE || SYSTEM_TYPE_DETACHABLE)
+	help
+	  Include ACPI devices for tablet mode / convertible controls (Intel VBTN,
+	  AMD VGBI). Default is enabled for non-ChromeOS builds when the board
+	  reports SMBIOS enclosure type convertible or detachable.
+
 endif # EC_GOOGLE_CHROMEEC
 
 source "src/ec/google/chromeec/*/Kconfig"
diff --git a/src/ec/google/chromeec/acpi/ec.asl b/src/ec/google/chromeec/acpi/ec.asl
index 93b04718ec..21e0045fb8 100644
--- a/src/ec/google/chromeec/acpi/ec.asl
+++ b/src/ec/google/chromeec/acpi/ec.asl
@@ -461,6 +461,18 @@ Device (EC0)
 #ifdef EC_ENABLE_TBMC_DEVICE
 		Notify (^CREC.TBMC, 0x80)
 #endif
+#if CONFIG(EC_CHROMEEC_USE_VENDOR_TABLET_CONTROLS)
+#if CONFIG(SOC_INTEL_COMMON)
+		If (^TBMD == 1) {
+			Notify (VBTN, 0xCC)
+		} Else {
+			Notify (VBTN, 0xCD)
+		}
+#endif
+#if CONFIG(SOC_AMD_COMMON)
+		Notify (VGBI, 0x81)
+#endif
+#endif
 #if CONFIG(SOC_AMD_COMMON_BLOCK_ACPI_DPTC)
 		If (CondRefOf (\_SB.DPTC)) {
 			\_SB.DPTC()
@@ -667,4 +679,13 @@ Device (EC0)
 #ifdef EC_ENABLE_KEYBOARD_BACKLIGHT
 	#include "keyboard_backlight.asl"
 #endif
+
+#if CONFIG(EC_CHROMEEC_USE_VENDOR_TABLET_CONTROLS)
+#if CONFIG(SOC_INTEL_COMMON)
+	#include "vbtn.asl"
+#endif
+#if CONFIG(SOC_AMD_COMMON)
+	#include "vgbi.asl"
+#endif
+#endif
 }
diff --git a/src/ec/google/chromeec/acpi/vbtn.asl b/src/ec/google/chromeec/acpi/vbtn.asl
new file mode 100644
index 0000000000..3bddc304de
--- /dev/null
+++ b/src/ec/google/chromeec/acpi/vbtn.asl
@@ -0,0 +1,38 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+/* VGBS reports 0x40 when NOT in tablet mode. */
+/* Sent event 0xCC for tablet mode, 0xCD for laptop */
+/* Linux driver expects SMBIOS_ENCLOSURE_TYPE=SMBIOS_ENCLOSURE_CONVERTIBLE */
+
+Device (VBTN)
+{
+	Name (_HID, "INT33D6")
+	Name (_DDN, "Tablet Virtual Buttons")
+
+	Method (VBDL, 0)
+	{
+	}
+
+	Method (VGBS)
+	{
+		If (^^RCTM == 1) {
+			Return (0x0)
+		} Else {
+			Return (0x40)
+		}
+	}
+	Method(_STA, 0)
+	{
+		Return (0xF)
+	}
+}
+
+Device (VBTO)
+{
+	Name (_HID, "INT33D3")
+	Name (_CID, "PNP0C60")
+	Method (_STA, 0)
+	{
+		Return (0xF)
+	}
+}
diff --git a/src/ec/google/chromeec/acpi/vgbi.asl b/src/ec/google/chromeec/acpi/vgbi.asl
new file mode 100644
index 0000000000..be71f11429
--- /dev/null
+++ b/src/ec/google/chromeec/acpi/vgbi.asl
@@ -0,0 +1,30 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+Device (CIND)
+{
+	Name (_HID, "AMD33D3")  // _HID: Hardware ID
+	Name (_CID, "PNP0C60" /* Display Sensor Device */)  // _CID: Compatible ID
+	Method (_STA, 0, Serialized)  // _STA: Status
+	{
+		Return (0x0F)
+	}
+}
+
+Device (VGBI)
+{
+	Name (_HID, "AMD33D6")  // _HID: Hardware ID
+
+	Method (_STA, 0, NotSerialized)  // _STA: Status
+	{
+		Return (0x0F)
+	}
+
+	Method (AMWF, 0, Serialized)
+	{
+		If (^^RCTM == 1) {
+			Return (0)
+		} Else {
+			Return (1)
+		}
+	}
+}

From c049dcc271fff0a38c2c25a51589bd215c683697 Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Wed, 18 Mar 2026 20:50:30 -0500
Subject: [PATCH 3800/3886] mb/google/brya: Set correct SYSTEM_TYPE for all
 variants

Set SYSTEM_TYPE_CONVERTIBLE for Brya 360/flip variants so SMBIOS
reports a convertible enclosure type. This allows non-ChromeOS
builds to enable EC_CHROMEEC_USE_VENDOR_TABLET_CONTROLS and use
the vendor tablet mode ACPI (VBTN).

Change-Id: I84bfd1df72d24b717f2b89906fd8dd2bef38d2b5
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91746
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
---
 src/mainboard/google/brya/Kconfig | 41 ++++++++++++++++++++++++-------
 1 file changed, 32 insertions(+), 9 deletions(-)

diff --git a/src/mainboard/google/brya/Kconfig b/src/mainboard/google/brya/Kconfig
index c7fad434f4..1084aa42ba 100644
--- a/src/mainboard/google/brya/Kconfig
+++ b/src/mainboard/google/brya/Kconfig
@@ -55,7 +55,7 @@ config BOARD_GOOGLE_BASEBOARD_BRYA
 	select HAVE_SLP_S0_GATE
 	select MEMORY_SOLDERDOWN if !BOARD_GOOGLE_BANSHEE
 	select SOC_INTEL_ALDERLAKE_PCH_P
-	select SYSTEM_TYPE_LAPTOP
+	select SYSTEM_TYPE_LAPTOP if !SYSTEM_TYPE_CONVERTIBLE
 	select TPM_GOOGLE_CR50
 
 config BOARD_GOOGLE_BASEBOARD_BRASK
@@ -103,7 +103,7 @@ config BOARD_GOOGLE_BASEBOARD_NISSA
 	select SOC_INTEL_ALDERLAKE_PCH_N
 	select SOC_INTEL_CSE_LITE_COMPRESS_ME_RW
 	select SOC_INTEL_CSE_LITE_SYNC_IN_RAMSTAGE
-	select SYSTEM_TYPE_LAPTOP if !SYSTEM_TYPE_MINIPC
+	select SYSTEM_TYPE_LAPTOP if !SYSTEM_TYPE_MINIPC && !SYSTEM_TYPE_CONVERTIBLE
 	select TPM_GOOGLE_TI50
 	select SOC_INTEL_COMMON_MMC_OVERRIDE
 
@@ -124,7 +124,7 @@ config BOARD_GOOGLE_BASEBOARD_TRULO
 	select SOC_INTEL_CSE_LITE_COMPRESS_ME_RW
 	select SOC_INTEL_CSE_LITE_SYNC_IN_RAMSTAGE
 	select SOC_INTEL_TWINLAKE
-	select SYSTEM_TYPE_LAPTOP
+	select SYSTEM_TYPE_LAPTOP if !SYSTEM_TYPE_CONVERTIBLE
 	select TPM_GOOGLE_TI50
 
 config BOARD_GOOGLE_AGAH
@@ -206,11 +206,13 @@ config BOARD_GOOGLE_CRAASK
 	select EC_GOOGLE_CHROMEEC_INCLUDE_SSFC_IN_FW_CONFIG
 	select HAVE_WWAN_POWER_SEQUENCE
 	select INTEL_GMA_HAVE_VBT
+	select SYSTEM_TYPE_CONVERTIBLE
 
 config BOARD_GOOGLE_CRAASKOV
 	select BOARD_GOOGLE_BASEBOARD_NISSA
-	select INTEL_GMA_HAVE_VBT
 	select CHROMEOS_WIFI_SAR if CHROMEOS
+	select INTEL_GMA_HAVE_VBT
+	select SYSTEM_TYPE_CONVERTIBLE
 
 config BOARD_GOOGLE_CONSTITUTION
 	select BOARD_GOOGLE_BASEBOARD_BRASK
@@ -227,6 +229,7 @@ config BOARD_GOOGLE_CROTA
 	select HAVE_WWAN_POWER_SEQUENCE
 	select INTEL_GMA_HAVE_VBT
 	select SOC_INTEL_RAPTORLAKE
+	select SYSTEM_TYPE_CONVERTIBLE
 
 config BOARD_GOOGLE_DIRKS
 	select BOARD_GOOGLE_BASEBOARD_NISSA
@@ -241,6 +244,7 @@ config BOARD_GOOGLE_DOCHI
 	select CHROMEOS_WIFI_SAR if CHROMEOS
 	select DRIVERS_INTEL_ISH
 	select SOC_INTEL_RAPTORLAKE
+	select SYSTEM_TYPE_CONVERTIBLE
 	select USE_UNIFIED_AP_FIRMWARE_FOR_UFS_AND_NON_UFS
 
 config BOARD_GOOGLE_DOMIKA
@@ -258,6 +262,7 @@ config BOARD_GOOGLE_FELWINTER
 	select DRIVERS_GENERIC_GPIO_KEYS
 	select DRIVERS_GENESYSLOGIC_GL9755
 	select INTEL_GMA_HAVE_VBT
+	select SYSTEM_TYPE_CONVERTIBLE
 
 config BOARD_GOOGLE_GAELIN
 	select BOARD_GOOGLE_BASEBOARD_BRASK
@@ -270,6 +275,7 @@ config BOARD_GOOGLE_GIMBLE
 	select GOOGLE_DSM_CALIB if VPD
 	select GOOGLE_DSM_PARAM_FILE_NAME if VPD
 	select INTEL_GMA_HAVE_VBT
+	select SYSTEM_TYPE_CONVERTIBLE
 
 config BOARD_GOOGLE_GIMBLE4ES
 	select BOARD_GOOGLE_BASEBOARD_BRYA
@@ -278,6 +284,7 @@ config BOARD_GOOGLE_GIMBLE4ES
 	select DRIVERS_I2C_MAX98390
 	select GOOGLE_DSM_CALIB if VPD
 	select GOOGLE_DSM_PARAM_FILE_NAME if VPD
+	select SYSTEM_TYPE_CONVERTIBLE
 
 config BOARD_GOOGLE_GLADIOS
 	select BOARD_GOOGLE_BASEBOARD_BRASK
@@ -306,6 +313,7 @@ config BOARD_GOOGLE_GOTHRAX
 	select DRIVERS_I2C_SX9324_SUPPORT_LEGACY_LINUX_DRIVER
 	select HAVE_WWAN_POWER_SEQUENCE
 	select CHROMEOS_WIFI_SAR if CHROMEOS
+	select SYSTEM_TYPE_CONVERTIBLE
 
 config BOARD_GOOGLE_GUREN
 	select BOARD_GOOGLE_BASEBOARD_NISSA
@@ -334,6 +342,7 @@ config BOARD_GOOGLE_KALADIN
 	select SOC_INTEL_COMMON_BLOCK_HDA_VERB
 	select SOC_INTEL_TCSS_USE_PDC_PMC_USBC_MUX_CONFIGURATION
 	select SOC_INTEL_TWINLAKE
+	select SYSTEM_TYPE_CONVERTIBLE
 	select USE_UNIFIED_AP_FIRMWARE_FOR_UFS_AND_NON_UFS
 
 config BOARD_GOOGLE_KANO
@@ -346,6 +355,7 @@ config BOARD_GOOGLE_KANO
 	select INTEL_GMA_HAVE_VBT
 	select SOC_INTEL_COMMON_BLOCK_IPU
 	select SOC_INTEL_RAPTORLAKE
+	select SYSTEM_TYPE_CONVERTIBLE
 
 config BOARD_GOOGLE_KINOX
 	select BOARD_GOOGLE_BASEBOARD_BRASK
@@ -371,6 +381,7 @@ config BOARD_GOOGLE_JOXER
 	select CHROMEOS_WIFI_SAR if CHROMEOS
 	select DRIVERS_GENESYSLOGIC_GL9750
 	select INTEL_GMA_HAVE_VBT
+	select SYSTEM_TYPE_CONVERTIBLE
 
 config BOARD_GOOGLE_LISBON
 	select BOARD_GOOGLE_BASEBOARD_BRASK
@@ -402,6 +413,7 @@ config BOARD_GOOGLE_MITHRAX
 	select DRIVERS_GENERIC_GPIO_KEYS
 	select DRIVERS_GENESYSLOGIC_GL9755
 	select INTEL_GMA_HAVE_VBT
+	select SYSTEM_TYPE_CONVERTIBLE
 
 config BOARD_GOOGLE_MOLI
 	select BOARD_GOOGLE_BASEBOARD_BRASK
@@ -490,6 +502,7 @@ config BOARD_GOOGLE_PUJJO
 	select DRIVERS_GENERIC_BAYHUB_LV2
 	select DRIVERS_GENERIC_GPIO_KEYS
 	select DRIVERS_GENESYSLOGIC_GL9750
+	select SYSTEM_TYPE_CONVERTIBLE
 	select DRIVERS_I2C_SX9324
 	select DRIVERS_I2C_SX9324_SUPPORT_LEGACY_LINUX_DRIVER
 	select DRIVERS_WWAN_FM350GL
@@ -512,6 +525,7 @@ config BOARD_GOOGLE_PUJJOGA
 	select ENFORCE_MEM_CHANNEL_DISABLE
 	select HAVE_WWAN_POWER_SEQUENCE
 	select INTEL_GMA_HAVE_VBT
+	select SYSTEM_TYPE_CONVERTIBLE
 
 config BOARD_GOOGLE_PUJJOGATWIN
 	select BOARD_GOOGLE_BASEBOARD_NISSA
@@ -523,33 +537,36 @@ config BOARD_GOOGLE_PUJJOGATWIN
 	select HAVE_WWAN_POWER_SEQUENCE
 	select INTEL_GMA_HAVE_VBT
 	select SOC_INTEL_TWINLAKE
+	select SYSTEM_TYPE_CONVERTIBLE
 
 config BOARD_GOOGLE_PUJJOLO
 	select BOARD_GOOGLE_BASEBOARD_TRULO
 	select CHROMEOS_WIFI_SAR if CHROMEOS
-	select DRIVERS_GENERIC_GPIO_KEYS
-	select DRIVERS_INTEL_MIPI_CAMERA
-	select DRIVERS_I2C_SX9324
 	select DRIVERS_GENERIC_BAYHUB_LV2
+	select DRIVERS_GENERIC_GPIO_KEYS
 	select DRIVERS_GFX_GENERIC
+	select DRIVERS_I2C_SX9324
 	select DRIVERS_I2C_SX9324_SUPPORT_LEGACY_LINUX_DRIVER
+	select DRIVERS_INTEL_MIPI_CAMERA
 	select ENFORCE_MEM_CHANNEL_DISABLE
 	select HAVE_WWAN_POWER_SEQUENCE
 	select MAINBOARD_HAS_GOOGLE_STRAUSS_KEYBOARD
 	select SOC_INTEL_COMMON_BLOCK_HDA_VERB
 	select SOC_INTEL_TCSS_USE_PDC_PMC_USBC_MUX_CONFIGURATION
 	select SOC_INTEL_TWINLAKE
+	select SYSTEM_TYPE_CONVERTIBLE
 
 config BOARD_GOOGLE_PUJJONIRU
 	select BOARD_GOOGLE_BASEBOARD_NISSA
 	select BOARD_ROMSIZE_KB_16384
 	select CHROMEOS_WIFI_SAR if CHROMEOS
+	select DRIVERS_AUDIO_SOF
 	select DRIVERS_GENERIC_BAYHUB_LV2
 	select DRIVERS_GENERIC_GPIO_KEYS
-	select DRIVERS_AUDIO_SOF
 	select ENFORCE_MEM_CHANNEL_DISABLE
 	select MAINBOARD_HAS_GOOGLE_STRAUSS_KEYBOARD
 	select SOC_INTEL_TWINLAKE
+	select SYSTEM_TYPE_CONVERTIBLE
 
 config BOARD_GOOGLE_PUJJOCENTO
 	select BOARD_GOOGLE_BASEBOARD_TRULO
@@ -592,6 +609,7 @@ config BOARD_GOOGLE_REDRIX
 	select GOOGLE_DSM_PARAM_FILE_NAME if VPD
 	select INTEL_GMA_HAVE_VBT
 	select SOC_INTEL_COMMON_BLOCK_IPU
+	select SYSTEM_TYPE_CONVERTIBLE
 
 config BOARD_GOOGLE_REDRIX4ES
 	select BOARD_GOOGLE_BASEBOARD_BRYA
@@ -603,6 +621,7 @@ config BOARD_GOOGLE_REDRIX4ES
 	select GOOGLE_DSM_CALIB if VPD
 	select GOOGLE_DSM_PARAM_FILE_NAME if VPD
 	select SOC_INTEL_COMMON_BLOCK_IPU
+	select SYSTEM_TYPE_CONVERTIBLE
 
 config BOARD_GOOGLE_RIVEN
 	select BOARD_GOOGLE_BASEBOARD_NISSA
@@ -614,6 +633,7 @@ config BOARD_GOOGLE_RIVEN
 	select INTEL_GMA_HAVE_VBT
 	select MAINBOARD_HAS_GOOGLE_STRAUSS_KEYBOARD
 	select SOC_INTEL_TWINLAKE
+	select SYSTEM_TYPE_CONVERTIBLE
 	select USE_UNIFIED_AP_FIRMWARE_FOR_UFS_AND_NON_UFS
 
 config BOARD_GOOGLE_RULL
@@ -657,6 +677,7 @@ config BOARD_GOOGLE_TAEKO
 	select DRIVERS_GENESYSLOGIC_GL9763E_L1_MAX if DRIVERS_GENESYSLOGIC_GL9763E
 	select INTEL_GMA_HAVE_VBT
 	select SOC_INTEL_RAPTORLAKE
+	select SYSTEM_TYPE_CONVERTIBLE
 
 config BOARD_GOOGLE_TAEKO4ES
 	select BOARD_GOOGLE_BASEBOARD_BRYA
@@ -665,6 +686,7 @@ config BOARD_GOOGLE_TAEKO4ES
 	select DRIVERS_GENERIC_BAYHUB_LV2
 	select DRIVERS_GENESYSLOGIC_GL9750
 	select DRIVERS_GENESYSLOGIC_GL9763E
+	select SYSTEM_TYPE_CONVERTIBLE
 
 config BOARD_GOOGLE_TANIKS
 	select BOARD_GOOGLE_BASEBOARD_BRYA
@@ -749,8 +771,8 @@ config BOARD_GOOGLE_ULDRENITE
 config BOARD_GOOGLE_VELL
 	select BOARD_GOOGLE_BASEBOARD_BRYA
 	select CHROMEOS_WIFI_SAR if CHROMEOS
-	select DRIVERS_INTEL_MIPI_CAMERA
 	select DRIVERS_I2C_CS35L53
+	select DRIVERS_INTEL_MIPI_CAMERA
 	select INTEL_GMA_HAVE_VBT
 	select SOC_INTEL_COMMON_BASECODE_RAMTOP
 	select SOC_INTEL_COMMON_BLOCK_IPU
@@ -770,6 +792,7 @@ config BOARD_GOOGLE_XIVU
 	select DRIVERS_GENESYSLOGIC_GL9750
 	select DRIVERS_INTEL_MIPI_CAMERA
 	select INTEL_GMA_HAVE_VBT
+	select SYSTEM_TYPE_CONVERTIBLE
 
 config BOARD_GOOGLE_XOL
 	select BOARD_GOOGLE_BASEBOARD_BRYA

From 025c0edeb28d90c9c70e621eaabdbd6a7b1e997a Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Fri, 20 Mar 2026 16:38:04 -0500
Subject: [PATCH 3801/3886] mb/google/dedede: Set correct SYSTEM_TYPE for all
 variants

Set SYSTEM_TYPE_CONVERTIBLE for Dedede-based Spin/Flip devices
so SMBIOS reports a convertible enclosure type. This enables
EC_CHROMEEC_USE_VENDOR_TABLET_CONTROLS on non-ChromeOS builds
and allows use of the vendor tablet mode ACPI (VBTN).

Adjust the system type check in mainboard_init() to account for
both laptops and convertibles.

Change-Id: I8cce636eb7e8ae6dfe16d6cd5004f463b5a7dd2d
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91745
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/google/dedede/Kconfig     | 14 +++++++++++---
 src/mainboard/google/dedede/mainboard.c |  3 ++-
 2 files changed, 13 insertions(+), 4 deletions(-)

diff --git a/src/mainboard/google/dedede/Kconfig b/src/mainboard/google/dedede/Kconfig
index 7e470d6b87..6a0b98712c 100644
--- a/src/mainboard/google/dedede/Kconfig
+++ b/src/mainboard/google/dedede/Kconfig
@@ -77,6 +77,7 @@ config BOARD_GOOGLE_BOTEN
 	select DRIVERS_I2C_SX9324_SUPPORT_LEGACY_LINUX_DRIVER
 	select GEO_SAR_ENABLE if CHROMEOS_WIFI_SAR
 	select INTEL_GMA_HAVE_VBT
+	select SYSTEM_TYPE_CONVERTIBLE
 
 config BOARD_GOOGLE_BOXY
 	select BOARD_GOOGLE_BASEBOARD_DEDEDE_CR50
@@ -93,6 +94,7 @@ config BOARD_GOOGLE_BUGZZY
 	select DRIVERS_I2C_SX9360
 	select GEO_SAR_ENABLE if CHROMEOS_WIFI_SAR
 	select INTEL_GMA_HAVE_VBT
+	select SYSTEM_TYPE_CONVERTIBLE
 
 config BOARD_GOOGLE_CAPPY2
 	select BOARD_GOOGLE_BASEBOARD_DEDEDE_TPM2
@@ -143,10 +145,11 @@ config BOARD_GOOGLE_DRAWCIA
 	select BOARD_GOOGLE_BASEBOARD_DEDEDE_CR50
 	select BASEBOARD_DEDEDE_LAPTOP
 	select DRIVERS_GENERIC_MAX98357A
-	select GEO_SAR_ENABLE if CHROMEOS_WIFI_SAR
 	select DRIVERS_INTEL_MIPI_CAMERA
+	select GEO_SAR_ENABLE if CHROMEOS_WIFI_SAR
 	select INTEL_GMA_HAVE_VBT
 	select SOC_INTEL_COMMON_BLOCK_IPU
+	select SYSTEM_TYPE_CONVERTIBLE
 
 config BOARD_GOOGLE_DRIBLEE
 	select BOARD_GOOGLE_BASEBOARD_DEDEDE_TPM2
@@ -182,6 +185,7 @@ config BOARD_GOOGLE_KRACKO
 	select DRIVERS_I2C_SX9324_SUPPORT_LEGACY_LINUX_DRIVER
 	select GEO_SAR_ENABLE if CHROMEOS_WIFI_SAR
 	select INTEL_GMA_HAVE_VBT
+	select SYSTEM_TYPE_CONVERTIBLE
 
 config BOARD_GOOGLE_LALALA
 	select BOARD_GOOGLE_BASEBOARD_DEDEDE_TPM2
@@ -202,6 +206,7 @@ config BOARD_GOOGLE_MADOO
 	select DRIVERS_GENERIC_MAX98357A
 	select GEO_SAR_ENABLE if CHROMEOS_WIFI_SAR
 	select INTEL_GMA_HAVE_VBT
+	select SYSTEM_TYPE_CONVERTIBLE
 
 config BOARD_GOOGLE_MAGOLOR
 	select BOARD_GOOGLE_BASEBOARD_DEDEDE_CR50
@@ -211,11 +216,13 @@ config BOARD_GOOGLE_MAGOLOR
 	select GEO_SAR_ENABLE if CHROMEOS_WIFI_SAR
 	select INTEL_GMA_HAVE_VBT
 	select SOC_INTEL_COMMON_BLOCK_IPU
+	select SYSTEM_TYPE_CONVERTIBLE
 
 config BOARD_GOOGLE_METAKNIGHT
 	select BOARD_GOOGLE_BASEBOARD_DEDEDE_CR50
 	select BASEBOARD_DEDEDE_LAPTOP
 	select INTEL_GMA_HAVE_VBT
+	select SYSTEM_TYPE_CONVERTIBLE
 
 config BOARD_GOOGLE_PIRIKA
 	select BOARD_GOOGLE_BASEBOARD_DEDEDE_CR50
@@ -246,9 +253,10 @@ config BOARD_GOOGLE_STORO
 	select DRIVERS_I2C_SX9324
 	select DRIVERS_I2C_SX9324_SUPPORT_LEGACY_LINUX_DRIVER
 	select DRIVERS_INTEL_MIPI_CAMERA
-	select SOC_INTEL_COMMON_BLOCK_IPU
 	select GEO_SAR_ENABLE if CHROMEOS_WIFI_SAR
 	select INTEL_GMA_HAVE_VBT
+	select SOC_INTEL_COMMON_BLOCK_IPU
+	select SYSTEM_TYPE_CONVERTIBLE
 
 config BOARD_GOOGLE_TARANZA
 	select BOARD_GOOGLE_BASEBOARD_DEDEDE_CR50
@@ -279,7 +287,7 @@ if BOARD_GOOGLE_BASEBOARD_DEDEDE
 config BASEBOARD_DEDEDE_LAPTOP
 	def_bool n
 	select DRIVERS_GFX_GENERIC
-	select SYSTEM_TYPE_LAPTOP
+	select SYSTEM_TYPE_LAPTOP if !SYSTEM_TYPE_CONVERTIBLE
 
 config CHROMEOS
 	select CHROMEOS_CSE_BOARD_RESET_OVERRIDE if BOARD_GOOGLE_BASEBOARD_DEDEDE_CR50
diff --git a/src/mainboard/google/dedede/mainboard.c b/src/mainboard/google/dedede/mainboard.c
index a668412003..39b408884b 100644
--- a/src/mainboard/google/dedede/mainboard.c
+++ b/src/mainboard/google/dedede/mainboard.c
@@ -87,7 +87,8 @@ static void mainboard_init(void *chip_info)
 	 * For chromeboxes, wait for DP HPD to be asserted before
 	 * entering FSP-S, otherwise display init may fail.
 	 */
-	if (!CONFIG(SYSTEM_TYPE_LAPTOP) && display_init_required())
+	if (!CONFIG(SYSTEM_TYPE_LAPTOP) && !CONFIG(SYSTEM_TYPE_CONVERTIBLE) &&
+	    display_init_required())
 		mainboard_wait_for_hpd();
 
 	base_pads = baseboard_gpio_table(&base_num);

From 3f100689368d677736458f9d34098a0bbec3a412 Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Wed, 18 Mar 2026 20:59:58 -0500
Subject: [PATCH 3802/3886] mb/google/glados/var/caroline: Mark board as
 convertible

Set SYSTEM_TYPE_CONVERTIBLE for the CAROLINE variant so SMBIOS
reports a convertible enclosure type. This allows non-ChromeOS
builds to enable EC_CHROMEEC_USE_VENDOR_TABLET_CONTROLS and use
the vendor tablet mode ACPI.

Change-Id: I67429b34a197cb4f1e3938040b0b1853462796c3
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91747
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
---
 src/mainboard/google/glados/Kconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/src/mainboard/google/glados/Kconfig b/src/mainboard/google/glados/Kconfig
index 746e326c04..a80fcecd68 100644
--- a/src/mainboard/google/glados/Kconfig
+++ b/src/mainboard/google/glados/Kconfig
@@ -38,6 +38,7 @@ config BOARD_GOOGLE_CAROLINE
 	select INTEL_GMA_HAVE_VBT
 	select MAINBOARD_NO_FSP_GOP
 	select NHLT_SSM4567 if INCLUDE_NHLT_BLOBS
+	select SYSTEM_TYPE_CONVERTIBLE
 
 config BOARD_GOOGLE_CAVE
 	select BOARD_GOOGLE_BASEBOARD_GLADOS

From 14ef3322421f4cc1877e964c72230037c8b08dc9 Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Wed, 18 Mar 2026 21:01:02 -0500
Subject: [PATCH 3803/3886] mb/google/hatch: Set correct SYSTEM_TYPE for all
 variants

Set SYSTEM_TYPE_CONVERTIBLE for Hatch-based Spin/Flip devices
so SMBIOS reports a convertible enclosure type. This enables
EC_CHROMEEC_USE_VENDOR_TABLET_CONTROLS on non-ChromeOS builds
and allows use of the vendor tablet mode ACPI (VBTN).

Change-Id: I8b72efb176087dda29b1c32b7ceef4c4544ef4d7
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91748
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/google/hatch/Kconfig | 6 +++++-
 1 file changed, 5 insertions(+), 1 deletion(-)

diff --git a/src/mainboard/google/hatch/Kconfig b/src/mainboard/google/hatch/Kconfig
index 1f9a7d2eb0..5db9a5061f 100644
--- a/src/mainboard/google/hatch/Kconfig
+++ b/src/mainboard/google/hatch/Kconfig
@@ -29,12 +29,13 @@ config BOARD_GOOGLE_BASEBOARD_HATCH
 	select SOC_INTEL_COMETLAKE_1
 	select SOC_INTEL_COMMON_BLOCK_DTT_STATIC_ASL
 	select SPI_TPM
-	select SYSTEM_TYPE_LAPTOP
+	select SYSTEM_TYPE_LAPTOP if !SYSTEM_TYPE_CONVERTIBLE
 	select TPM_GOOGLE_CR50
 
 config BOARD_GOOGLE_AKEMI
 	select BOARD_GOOGLE_BASEBOARD_HATCH
 	select INTEL_GMA_HAVE_VBT
+	select SYSTEM_TYPE_CONVERTIBLE
 
 config BOARD_GOOGLE_DRATINI
 	select BOARD_GOOGLE_BASEBOARD_HATCH
@@ -50,17 +51,20 @@ config BOARD_GOOGLE_HELIOS
 	select GOOGLE_DSM_CALIB if VPD
 	select DRIVERS_I2C_RT1011
 	select INTEL_GMA_HAVE_VBT
+	select SYSTEM_TYPE_CONVERTIBLE
 
 config BOARD_GOOGLE_HELIOS_DISKSWAP
 	select BOARD_GOOGLE_BASEBOARD_HATCH
 	select GOOGLE_DSM_CALIB if VPD
 	select DRIVERS_I2C_RT1011
 	select INTEL_GMA_HAVE_VBT
+	select SYSTEM_TYPE_CONVERTIBLE
 
 config BOARD_GOOGLE_JINLON
 	select BOARD_GOOGLE_BASEBOARD_HATCH
 	select DRIVERS_GFX_GENERIC
 	select INTEL_GMA_HAVE_VBT
+	select SYSTEM_TYPE_CONVERTIBLE
 
 config BOARD_GOOGLE_KINDRED
 	select BOARD_GOOGLE_BASEBOARD_HATCH

From 7995a1d3eaacb6cb5062769b7e2796f18d07d3f6 Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Wed, 18 Mar 2026 21:02:48 -0500
Subject: [PATCH 3804/3886] mb/google/octopus: Set correct SYSTEM_TYPE for all
 variants

Set SYSTEM_TYPE_CONVERTIBLE for Octopus-based Spin/Flip devices
so SMBIOS reports a convertible enclosure type. This enables
EC_CHROMEEC_USE_VENDOR_TABLET_CONTROLS on non-ChromeOS builds
and allows use of the vendor tablet mode ACPI (VBTN).

Change-Id: I298fb413480f6392990d00dc375db4d1e4176d9d
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91750
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
---
 src/mainboard/google/octopus/Kconfig | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/src/mainboard/google/octopus/Kconfig b/src/mainboard/google/octopus/Kconfig
index 8723820f14..47503b4364 100644
--- a/src/mainboard/google/octopus/Kconfig
+++ b/src/mainboard/google/octopus/Kconfig
@@ -27,17 +27,19 @@ config BOARD_GOOGLE_BASEBOARD_OCTOPUS
 	select SOC_ESPI
 	select SOC_INTEL_GEMINILAKE
 	select SPI_TPM
-	select SYSTEM_TYPE_LAPTOP
+	select SYSTEM_TYPE_LAPTOP if !SYSTEM_TYPE_CONVERTIBLE
 	select TPM_GOOGLE_CR50
 
 config BOARD_GOOGLE_AMPTON
 	select BOARD_GOOGLE_BASEBOARD_OCTOPUS
 	select NHLT_RT5682 if INCLUDE_NHLT_BLOBS
+	select SYSTEM_TYPE_CONVERTIBLE
 
 config BOARD_GOOGLE_BLOOG
 	select BOARD_GOOGLE_BASEBOARD_OCTOPUS
 	select NHLT_DA7219 if INCLUDE_NHLT_BLOBS
 	select NHLT_RT5682 if INCLUDE_NHLT_BLOBS
+	select SYSTEM_TYPE_CONVERTIBLE
 
 config BOARD_GOOGLE_BOBBA
 	select BOARD_GOOGLE_BASEBOARD_OCTOPUS
@@ -74,6 +76,7 @@ config BOARD_GOOGLE_MEEP
 	select BOARD_GOOGLE_BASEBOARD_OCTOPUS
 	select NHLT_DA7219 if INCLUDE_NHLT_BLOBS
 	select NHLT_RT5682 if INCLUDE_NHLT_BLOBS
+	select SYSTEM_TYPE_CONVERTIBLE
 
 config BOARD_GOOGLE_OCTOPUS
 	select BOARD_GOOGLE_BASEBOARD_OCTOPUS

From 7b87cda615671e2819a32304d512a995682dcdaa Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Wed, 18 Mar 2026 21:03:35 -0500
Subject: [PATCH 3805/3886] mb/google/reef: Set correct SYSTEM_TYPE for all
 variants

Set SYSTEM_TYPE_CONVERTIBLE for Reef-based Spin/Flip devices
so SMBIOS reports a convertible enclosure type. This enables
EC_CHROMEEC_USE_VENDOR_TABLET_CONTROLS on non-ChromeOS builds
and allows use of the vendor tablet mode ACPI (VBTN).

Change-Id: Iff5c8379ff318a5616fee0133fef6f0ad9b93003
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91751
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
---
 src/mainboard/google/reef/Kconfig | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/src/mainboard/google/reef/Kconfig b/src/mainboard/google/reef/Kconfig
index 1ce2353432..8ece7e2a48 100644
--- a/src/mainboard/google/reef/Kconfig
+++ b/src/mainboard/google/reef/Kconfig
@@ -21,23 +21,26 @@ config BOARD_GOOGLE_BASEBOARD_REEF
 	select MAINBOARD_HAS_CHROMEOS
 	select MAINBOARD_HAS_TPM2
 	select SOC_INTEL_APOLLOLAKE
-	select SYSTEM_TYPE_LAPTOP
 	select TPM_GOOGLE_CR50
 
 config BOARD_GOOGLE_REEF
 	select BOARD_GOOGLE_BASEBOARD_REEF
+	select SYSTEM_TYPE_CONVERTIBLE
 
 config BOARD_GOOGLE_PYRO
 	select BOARD_GOOGLE_BASEBOARD_REEF
+	select SYSTEM_TYPE_CONVERTIBLE
 
 config BOARD_GOOGLE_SAND
 	select BOARD_GOOGLE_BASEBOARD_REEF
 
 config BOARD_GOOGLE_SNAPPY
 	select BOARD_GOOGLE_BASEBOARD_REEF
+	select SYSTEM_TYPE_CONVERTIBLE
 
 config BOARD_GOOGLE_CORAL
 	select BOARD_GOOGLE_BASEBOARD_REEF
+	select SYSTEM_TYPE_LAPTOP
 
 if BOARD_GOOGLE_BASEBOARD_REEF
 

From 8f5477d92dd284643f3ddab3d06eab0c064face4 Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Wed, 18 Mar 2026 20:45:14 -0500
Subject: [PATCH 3806/3886] mb/google/volteer: Set correct SYSTEM_TYPE for all
 variants

Set SYSTEM_TYPE_CONVERTIBLE for Volteer-based Spin/Flip devices
so SMBIOS reports a convertible enclosure type. This enables
EC_CHROMEEC_USE_VENDOR_TABLET_CONTROLS on non-ChromeOS builds
and allows use of the vendor tablet mode ACPI (VBTN).

Set the default SYSTEM_TYPE for non-convertibles to LAPTOP as
is done for most newer ChromeOS boards.

Change-Id: I02337464953fdb654e99019af4d2f142e1910e97
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91743
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
---
 src/mainboard/google/volteer/Kconfig | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/src/mainboard/google/volteer/Kconfig b/src/mainboard/google/volteer/Kconfig
index dc586f1538..818bf9827e 100644
--- a/src/mainboard/google/volteer/Kconfig
+++ b/src/mainboard/google/volteer/Kconfig
@@ -40,6 +40,7 @@ config BOARD_GOOGLE_BASEBOARD_VOLTEER
 	select SOC_INTEL_COMMON_BLOCK_TCSS
 	select SOC_INTEL_CSE_LITE_SKU
 	select SOC_INTEL_TIGERLAKE
+	select SYSTEM_TYPE_LAPTOP if !SYSTEM_TYPE_CONVERTIBLE
 	select SPI_TPM if !BOARD_GOOGLE_VOLTEER2_TI50
 	select TPM_GOOGLE_TI50 if BOARD_GOOGLE_VOLTEER2_TI50
 	select TPM_GOOGLE_CR50 if !BOARD_GOOGLE_VOLTEER2_TI50
@@ -51,16 +52,19 @@ config BOARD_GOOGLE_CHRONICLER
 config BOARD_GOOGLE_COLLIS
 	select BOARD_GOOGLE_BASEBOARD_VOLTEER
 	select INTEL_GMA_HAVE_VBT
+	select SYSTEM_TYPE_CONVERTIBLE
 
 config BOARD_GOOGLE_COPANO
 	select BOARD_GOOGLE_BASEBOARD_VOLTEER
 	select INTEL_GMA_HAVE_VBT
 	select SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES
+	select SYSTEM_TYPE_CONVERTIBLE
 
 config BOARD_GOOGLE_DELBIN
 	select BOARD_GOOGLE_BASEBOARD_VOLTEER
 	select DRIVERS_GENESYSLOGIC_GL9755
 	select INTEL_GMA_HAVE_VBT
+	select SYSTEM_TYPE_CONVERTIBLE
 
 config BOARD_GOOGLE_DROBIT
 	select BOARD_GOOGLE_BASEBOARD_VOLTEER
@@ -71,6 +75,7 @@ config BOARD_GOOGLE_DROBIT
 config BOARD_GOOGLE_ELDRID
 	select BOARD_GOOGLE_BASEBOARD_VOLTEER
 	select INTEL_GMA_HAVE_VBT
+	select SYSTEM_TYPE_CONVERTIBLE
 
 config BOARD_GOOGLE_ELEMI
 	select BOARD_GOOGLE_BASEBOARD_VOLTEER
@@ -108,6 +113,7 @@ config BOARD_GOOGLE_VOEMA
 	select DRIVERS_GFX_GENERIC
 	select DRIVERS_INTEL_MIPI_CAMERA
 	select INTEL_GMA_HAVE_VBT
+	select SYSTEM_TYPE_CONVERTIBLE
 
 config BOARD_GOOGLE_VOLET
 	select BOARD_GOOGLE_BASEBOARD_VOLTEER
@@ -142,6 +148,7 @@ config BOARD_GOOGLE_VOXEL
 	select GEO_SAR_ENABLE if CHROMEOS_WIFI_SAR
 	select INTEL_GMA_HAVE_VBT
 	select SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES
+	select SYSTEM_TYPE_CONVERTIBLE
 
 if BOARD_GOOGLE_BASEBOARD_VOLTEER
 

From a8615bed6b12db857f659c89e61d39df0b32ca08 Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Thu, 19 Mar 2026 16:20:39 -0500
Subject: [PATCH 3807/3886] mb/google/cyan: Add support for EC mode change
 event

TMBC support has been backported to the EC firmware for CYAN
and KEFKA, so add SCI support for the MODE_CHANGE host event.

TEST=build/boot Win11, Linux on CYAN, verify tablet mode switching
functional via Intel VBTN driver.

Change-Id: Id3474e07bad1b6371644821dfe39a8105e4dd0f8
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91788
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
---
 src/mainboard/google/cyan/ec.h | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/src/mainboard/google/cyan/ec.h b/src/mainboard/google/cyan/ec.h
index 7955e33ab9..2f11940ce2 100644
--- a/src/mainboard/google/cyan/ec.h
+++ b/src/mainboard/google/cyan/ec.h
@@ -23,7 +23,8 @@
 	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_THRESHOLD) |\
 	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_START)    |\
 	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_STOP)     |\
-	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_MKBP))
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_MKBP)              |\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_MODE_CHANGE))
 
 #define MAINBOARD_EC_SMI_EVENTS \
 	(EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED))

From 25ad0950a84b21e9b4129903772667022c16d2ec Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Mon, 2 Feb 2026 14:57:58 -0600
Subject: [PATCH 3808/3886] mb/google/brya: Add non-ChromeOS TBMC support for
 360/flip variants

The TBMC ACPI device is used by Windows ChromeEC drivers to determine
tablet mode and to enable motion sensors (accelerometer, gyroscope).
Since it's not needed/used by ChromeOS, restrict its inclusion to
non-ChromeOS builds.

TEST=build/boot Win11/Linux on taeko, verify tablet mode and rotation
work properly, keyboard/touchpad disabled in tablet mode.

Change-Id: Ie26cd77c8a58034dbce05a1ab308b9dcc122484c
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91797
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 .../google/brya/variants/craask/include/variant/ec.h         | 5 +++++
 .../google/brya/variants/craaskov/include/variant/ec.h       | 5 +++++
 .../google/brya/variants/crota/include/variant/ec.h          | 5 +++++
 .../google/brya/variants/dochi/include/variant/ec.h          | 5 +++++
 .../google/brya/variants/felwinter/include/variant/ec.h      | 5 +++++
 .../google/brya/variants/gimble/include/variant/ec.h         | 5 +++++
 .../google/brya/variants/gimble4es/include/variant/ec.h      | 5 +++++
 .../google/brya/variants/gothrax/include/variant/ec.h        | 5 +++++
 .../google/brya/variants/joxer/include/variant/ec.h          | 5 +++++
 .../google/brya/variants/kaladin/include/variant/ec.h        | 5 +++++
 src/mainboard/google/brya/variants/kano/include/variant/ec.h | 5 +++++
 .../google/brya/variants/mithrax/include/variant/ec.h        | 5 +++++
 .../google/brya/variants/pujjo/include/variant/ec.h          | 5 +++++
 .../google/brya/variants/pujjoga/include/variant/ec.h        | 5 +++++
 .../google/brya/variants/pujjolo/include/variant/ec.h        | 5 +++++
 .../google/brya/variants/pujjoniru/include/variant/ec.h      | 5 +++++
 .../google/brya/variants/redrix/include/variant/ec.h         | 5 +++++
 .../google/brya/variants/redrix4es/include/variant/ec.h      | 5 +++++
 .../google/brya/variants/riven/include/variant/ec.h          | 5 +++++
 .../google/brya/variants/taeko/include/variant/ec.h          | 5 +++++
 .../google/brya/variants/taeko4es/include/variant/ec.h       | 5 +++++
 src/mainboard/google/brya/variants/xivu/include/variant/ec.h | 5 +++++
 22 files changed, 110 insertions(+)

diff --git a/src/mainboard/google/brya/variants/craask/include/variant/ec.h b/src/mainboard/google/brya/variants/craask/include/variant/ec.h
index 7a2a6ff8b7..dac67ca295 100644
--- a/src/mainboard/google/brya/variants/craask/include/variant/ec.h
+++ b/src/mainboard/google/brya/variants/craask/include/variant/ec.h
@@ -5,4 +5,9 @@
 
 #include <baseboard/ec.h>
 
+/* Enable Tablet switch for Windows drivers */
+#if !CONFIG(CHROMEOS)
+#define EC_ENABLE_TBMC_DEVICE
+#endif
+
 #endif
diff --git a/src/mainboard/google/brya/variants/craaskov/include/variant/ec.h b/src/mainboard/google/brya/variants/craaskov/include/variant/ec.h
index 7a2a6ff8b7..dac67ca295 100644
--- a/src/mainboard/google/brya/variants/craaskov/include/variant/ec.h
+++ b/src/mainboard/google/brya/variants/craaskov/include/variant/ec.h
@@ -5,4 +5,9 @@
 
 #include <baseboard/ec.h>
 
+/* Enable Tablet switch for Windows drivers */
+#if !CONFIG(CHROMEOS)
+#define EC_ENABLE_TBMC_DEVICE
+#endif
+
 #endif
diff --git a/src/mainboard/google/brya/variants/crota/include/variant/ec.h b/src/mainboard/google/brya/variants/crota/include/variant/ec.h
index 7a2a6ff8b7..dac67ca295 100644
--- a/src/mainboard/google/brya/variants/crota/include/variant/ec.h
+++ b/src/mainboard/google/brya/variants/crota/include/variant/ec.h
@@ -5,4 +5,9 @@
 
 #include <baseboard/ec.h>
 
+/* Enable Tablet switch for Windows drivers */
+#if !CONFIG(CHROMEOS)
+#define EC_ENABLE_TBMC_DEVICE
+#endif
+
 #endif
diff --git a/src/mainboard/google/brya/variants/dochi/include/variant/ec.h b/src/mainboard/google/brya/variants/dochi/include/variant/ec.h
index 6f104d5da4..74b96179aa 100644
--- a/src/mainboard/google/brya/variants/dochi/include/variant/ec.h
+++ b/src/mainboard/google/brya/variants/dochi/include/variant/ec.h
@@ -8,4 +8,9 @@
 /* Enable EC backed Keyboard Backlight in ACPI */
 #define EC_ENABLE_KEYBOARD_BACKLIGHT
 
+/* Enable Tablet switch for Windows drivers */
+#if !CONFIG(CHROMEOS)
+#define EC_ENABLE_TBMC_DEVICE
+#endif
+
 #endif
diff --git a/src/mainboard/google/brya/variants/felwinter/include/variant/ec.h b/src/mainboard/google/brya/variants/felwinter/include/variant/ec.h
index 7a2a6ff8b7..dac67ca295 100644
--- a/src/mainboard/google/brya/variants/felwinter/include/variant/ec.h
+++ b/src/mainboard/google/brya/variants/felwinter/include/variant/ec.h
@@ -5,4 +5,9 @@
 
 #include <baseboard/ec.h>
 
+/* Enable Tablet switch for Windows drivers */
+#if !CONFIG(CHROMEOS)
+#define EC_ENABLE_TBMC_DEVICE
+#endif
+
 #endif
diff --git a/src/mainboard/google/brya/variants/gimble/include/variant/ec.h b/src/mainboard/google/brya/variants/gimble/include/variant/ec.h
index 7a2a6ff8b7..dac67ca295 100644
--- a/src/mainboard/google/brya/variants/gimble/include/variant/ec.h
+++ b/src/mainboard/google/brya/variants/gimble/include/variant/ec.h
@@ -5,4 +5,9 @@
 
 #include <baseboard/ec.h>
 
+/* Enable Tablet switch for Windows drivers */
+#if !CONFIG(CHROMEOS)
+#define EC_ENABLE_TBMC_DEVICE
+#endif
+
 #endif
diff --git a/src/mainboard/google/brya/variants/gimble4es/include/variant/ec.h b/src/mainboard/google/brya/variants/gimble4es/include/variant/ec.h
index 7a2a6ff8b7..dac67ca295 100644
--- a/src/mainboard/google/brya/variants/gimble4es/include/variant/ec.h
+++ b/src/mainboard/google/brya/variants/gimble4es/include/variant/ec.h
@@ -5,4 +5,9 @@
 
 #include <baseboard/ec.h>
 
+/* Enable Tablet switch for Windows drivers */
+#if !CONFIG(CHROMEOS)
+#define EC_ENABLE_TBMC_DEVICE
+#endif
+
 #endif
diff --git a/src/mainboard/google/brya/variants/gothrax/include/variant/ec.h b/src/mainboard/google/brya/variants/gothrax/include/variant/ec.h
index 7a2a6ff8b7..dac67ca295 100644
--- a/src/mainboard/google/brya/variants/gothrax/include/variant/ec.h
+++ b/src/mainboard/google/brya/variants/gothrax/include/variant/ec.h
@@ -5,4 +5,9 @@
 
 #include <baseboard/ec.h>
 
+/* Enable Tablet switch for Windows drivers */
+#if !CONFIG(CHROMEOS)
+#define EC_ENABLE_TBMC_DEVICE
+#endif
+
 #endif
diff --git a/src/mainboard/google/brya/variants/joxer/include/variant/ec.h b/src/mainboard/google/brya/variants/joxer/include/variant/ec.h
index 7a2a6ff8b7..dac67ca295 100644
--- a/src/mainboard/google/brya/variants/joxer/include/variant/ec.h
+++ b/src/mainboard/google/brya/variants/joxer/include/variant/ec.h
@@ -5,4 +5,9 @@
 
 #include <baseboard/ec.h>
 
+/* Enable Tablet switch for Windows drivers */
+#if !CONFIG(CHROMEOS)
+#define EC_ENABLE_TBMC_DEVICE
+#endif
+
 #endif
diff --git a/src/mainboard/google/brya/variants/kaladin/include/variant/ec.h b/src/mainboard/google/brya/variants/kaladin/include/variant/ec.h
index 6f104d5da4..74b96179aa 100644
--- a/src/mainboard/google/brya/variants/kaladin/include/variant/ec.h
+++ b/src/mainboard/google/brya/variants/kaladin/include/variant/ec.h
@@ -8,4 +8,9 @@
 /* Enable EC backed Keyboard Backlight in ACPI */
 #define EC_ENABLE_KEYBOARD_BACKLIGHT
 
+/* Enable Tablet switch for Windows drivers */
+#if !CONFIG(CHROMEOS)
+#define EC_ENABLE_TBMC_DEVICE
+#endif
+
 #endif
diff --git a/src/mainboard/google/brya/variants/kano/include/variant/ec.h b/src/mainboard/google/brya/variants/kano/include/variant/ec.h
index 6f104d5da4..74b96179aa 100644
--- a/src/mainboard/google/brya/variants/kano/include/variant/ec.h
+++ b/src/mainboard/google/brya/variants/kano/include/variant/ec.h
@@ -8,4 +8,9 @@
 /* Enable EC backed Keyboard Backlight in ACPI */
 #define EC_ENABLE_KEYBOARD_BACKLIGHT
 
+/* Enable Tablet switch for Windows drivers */
+#if !CONFIG(CHROMEOS)
+#define EC_ENABLE_TBMC_DEVICE
+#endif
+
 #endif
diff --git a/src/mainboard/google/brya/variants/mithrax/include/variant/ec.h b/src/mainboard/google/brya/variants/mithrax/include/variant/ec.h
index 7a2a6ff8b7..dac67ca295 100644
--- a/src/mainboard/google/brya/variants/mithrax/include/variant/ec.h
+++ b/src/mainboard/google/brya/variants/mithrax/include/variant/ec.h
@@ -5,4 +5,9 @@
 
 #include <baseboard/ec.h>
 
+/* Enable Tablet switch for Windows drivers */
+#if !CONFIG(CHROMEOS)
+#define EC_ENABLE_TBMC_DEVICE
+#endif
+
 #endif
diff --git a/src/mainboard/google/brya/variants/pujjo/include/variant/ec.h b/src/mainboard/google/brya/variants/pujjo/include/variant/ec.h
index 7a2a6ff8b7..dac67ca295 100644
--- a/src/mainboard/google/brya/variants/pujjo/include/variant/ec.h
+++ b/src/mainboard/google/brya/variants/pujjo/include/variant/ec.h
@@ -5,4 +5,9 @@
 
 #include <baseboard/ec.h>
 
+/* Enable Tablet switch for Windows drivers */
+#if !CONFIG(CHROMEOS)
+#define EC_ENABLE_TBMC_DEVICE
+#endif
+
 #endif
diff --git a/src/mainboard/google/brya/variants/pujjoga/include/variant/ec.h b/src/mainboard/google/brya/variants/pujjoga/include/variant/ec.h
index 7a2a6ff8b7..dac67ca295 100644
--- a/src/mainboard/google/brya/variants/pujjoga/include/variant/ec.h
+++ b/src/mainboard/google/brya/variants/pujjoga/include/variant/ec.h
@@ -5,4 +5,9 @@
 
 #include <baseboard/ec.h>
 
+/* Enable Tablet switch for Windows drivers */
+#if !CONFIG(CHROMEOS)
+#define EC_ENABLE_TBMC_DEVICE
+#endif
+
 #endif
diff --git a/src/mainboard/google/brya/variants/pujjolo/include/variant/ec.h b/src/mainboard/google/brya/variants/pujjolo/include/variant/ec.h
index 7a2a6ff8b7..dac67ca295 100644
--- a/src/mainboard/google/brya/variants/pujjolo/include/variant/ec.h
+++ b/src/mainboard/google/brya/variants/pujjolo/include/variant/ec.h
@@ -5,4 +5,9 @@
 
 #include <baseboard/ec.h>
 
+/* Enable Tablet switch for Windows drivers */
+#if !CONFIG(CHROMEOS)
+#define EC_ENABLE_TBMC_DEVICE
+#endif
+
 #endif
diff --git a/src/mainboard/google/brya/variants/pujjoniru/include/variant/ec.h b/src/mainboard/google/brya/variants/pujjoniru/include/variant/ec.h
index 7a2a6ff8b7..dac67ca295 100644
--- a/src/mainboard/google/brya/variants/pujjoniru/include/variant/ec.h
+++ b/src/mainboard/google/brya/variants/pujjoniru/include/variant/ec.h
@@ -5,4 +5,9 @@
 
 #include <baseboard/ec.h>
 
+/* Enable Tablet switch for Windows drivers */
+#if !CONFIG(CHROMEOS)
+#define EC_ENABLE_TBMC_DEVICE
+#endif
+
 #endif
diff --git a/src/mainboard/google/brya/variants/redrix/include/variant/ec.h b/src/mainboard/google/brya/variants/redrix/include/variant/ec.h
index ea8fb54830..18716e4f50 100644
--- a/src/mainboard/google/brya/variants/redrix/include/variant/ec.h
+++ b/src/mainboard/google/brya/variants/redrix/include/variant/ec.h
@@ -23,4 +23,9 @@
 /* Enable EC backed Keyboard Backlight in ACPI */
 #define EC_ENABLE_KEYBOARD_BACKLIGHT
 
+/* Enable Tablet switch for Windows drivers */
+#if !CONFIG(CHROMEOS)
+#define EC_ENABLE_TBMC_DEVICE
+#endif
+
 #endif
diff --git a/src/mainboard/google/brya/variants/redrix4es/include/variant/ec.h b/src/mainboard/google/brya/variants/redrix4es/include/variant/ec.h
index d390746036..3034eef15a 100644
--- a/src/mainboard/google/brya/variants/redrix4es/include/variant/ec.h
+++ b/src/mainboard/google/brya/variants/redrix4es/include/variant/ec.h
@@ -44,4 +44,9 @@
 /* Enable EC backed Keyboard Backlight in ACPI */
 #define EC_ENABLE_KEYBOARD_BACKLIGHT
 
+/* Enable Tablet switch for Windows drivers */
+#if !CONFIG(CHROMEOS)
+#define EC_ENABLE_TBMC_DEVICE
+#endif
+
 #endif
diff --git a/src/mainboard/google/brya/variants/riven/include/variant/ec.h b/src/mainboard/google/brya/variants/riven/include/variant/ec.h
index 7a2a6ff8b7..dac67ca295 100644
--- a/src/mainboard/google/brya/variants/riven/include/variant/ec.h
+++ b/src/mainboard/google/brya/variants/riven/include/variant/ec.h
@@ -5,4 +5,9 @@
 
 #include <baseboard/ec.h>
 
+/* Enable Tablet switch for Windows drivers */
+#if !CONFIG(CHROMEOS)
+#define EC_ENABLE_TBMC_DEVICE
+#endif
+
 #endif
diff --git a/src/mainboard/google/brya/variants/taeko/include/variant/ec.h b/src/mainboard/google/brya/variants/taeko/include/variant/ec.h
index 7a2a6ff8b7..dac67ca295 100644
--- a/src/mainboard/google/brya/variants/taeko/include/variant/ec.h
+++ b/src/mainboard/google/brya/variants/taeko/include/variant/ec.h
@@ -5,4 +5,9 @@
 
 #include <baseboard/ec.h>
 
+/* Enable Tablet switch for Windows drivers */
+#if !CONFIG(CHROMEOS)
+#define EC_ENABLE_TBMC_DEVICE
+#endif
+
 #endif
diff --git a/src/mainboard/google/brya/variants/taeko4es/include/variant/ec.h b/src/mainboard/google/brya/variants/taeko4es/include/variant/ec.h
index 7a2a6ff8b7..dac67ca295 100644
--- a/src/mainboard/google/brya/variants/taeko4es/include/variant/ec.h
+++ b/src/mainboard/google/brya/variants/taeko4es/include/variant/ec.h
@@ -5,4 +5,9 @@
 
 #include <baseboard/ec.h>
 
+/* Enable Tablet switch for Windows drivers */
+#if !CONFIG(CHROMEOS)
+#define EC_ENABLE_TBMC_DEVICE
+#endif
+
 #endif
diff --git a/src/mainboard/google/brya/variants/xivu/include/variant/ec.h b/src/mainboard/google/brya/variants/xivu/include/variant/ec.h
index 7a2a6ff8b7..dac67ca295 100644
--- a/src/mainboard/google/brya/variants/xivu/include/variant/ec.h
+++ b/src/mainboard/google/brya/variants/xivu/include/variant/ec.h
@@ -5,4 +5,9 @@
 
 #include <baseboard/ec.h>
 
+/* Enable Tablet switch for Windows drivers */
+#if !CONFIG(CHROMEOS)
+#define EC_ENABLE_TBMC_DEVICE
+#endif
+
 #endif

From f867d8f76bc57d2ca537e5d804f02d213b74dec6 Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Fri, 14 Apr 2023 13:43:43 -0500
Subject: [PATCH 3809/3886] mb/google/dedede: Add non-ChromeOS TBMC support for
 360/flip variants

The TBMC ACPI device is used by Windows ChromeEC drivers to determine
tablet mode and to enable motion sensors (accelerometer, gyroscope).
Since it's not needed/used by ChromeOS, restrict its inclusion to
non-ChromeOS builds.

TEST=build/boot Win11/Linux on magolor, verify tablet mode and rotation
work properly, keyboard/touchpad disabled in tablet mode.

Change-Id: I6853465ba77be1f95cbe5795b318df02ecc1da39
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91798
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 .../google/dedede/variants/boten/include/variant/ec.h        | 5 +++++
 .../google/dedede/variants/bugzzy/include/variant/ec.h       | 5 +++++
 .../google/dedede/variants/drawcia/include/variant/ec.h      | 5 +++++
 .../google/dedede/variants/kracko/include/variant/ec.h       | 5 +++++
 .../google/dedede/variants/madoo/include/variant/ec.h        | 5 +++++
 .../google/dedede/variants/magolor/include/variant/ec.h      | 5 +++++
 .../google/dedede/variants/metaknight/include/variant/ec.h   | 5 +++++
 .../google/dedede/variants/storo/include/variant/ec.h        | 5 +++++
 8 files changed, 40 insertions(+)

diff --git a/src/mainboard/google/dedede/variants/boten/include/variant/ec.h b/src/mainboard/google/dedede/variants/boten/include/variant/ec.h
index 08870e0627..99ff519a84 100644
--- a/src/mainboard/google/dedede/variants/boten/include/variant/ec.h
+++ b/src/mainboard/google/dedede/variants/boten/include/variant/ec.h
@@ -5,4 +5,9 @@
 
 #include <baseboard/ec.h>
 
+/* Enable Tablet switch for Windows drivers */
+#if !CONFIG(CHROMEOS)
+#define EC_ENABLE_TBMC_DEVICE
+#endif
+
 #endif
diff --git a/src/mainboard/google/dedede/variants/bugzzy/include/variant/ec.h b/src/mainboard/google/dedede/variants/bugzzy/include/variant/ec.h
index 08870e0627..99ff519a84 100644
--- a/src/mainboard/google/dedede/variants/bugzzy/include/variant/ec.h
+++ b/src/mainboard/google/dedede/variants/bugzzy/include/variant/ec.h
@@ -5,4 +5,9 @@
 
 #include <baseboard/ec.h>
 
+/* Enable Tablet switch for Windows drivers */
+#if !CONFIG(CHROMEOS)
+#define EC_ENABLE_TBMC_DEVICE
+#endif
+
 #endif
diff --git a/src/mainboard/google/dedede/variants/drawcia/include/variant/ec.h b/src/mainboard/google/dedede/variants/drawcia/include/variant/ec.h
index 27c930d4f2..f721a22ec7 100644
--- a/src/mainboard/google/dedede/variants/drawcia/include/variant/ec.h
+++ b/src/mainboard/google/dedede/variants/drawcia/include/variant/ec.h
@@ -8,4 +8,9 @@
 /* Enable Keyboard Backlight in ACPI */
 #define EC_ENABLE_KEYBOARD_BACKLIGHT
 
+/* Enable Tablet switch for Windows drivers */
+#if !CONFIG(CHROMEOS)
+#define EC_ENABLE_TBMC_DEVICE
+#endif
+
 #endif
diff --git a/src/mainboard/google/dedede/variants/kracko/include/variant/ec.h b/src/mainboard/google/dedede/variants/kracko/include/variant/ec.h
index 08870e0627..99ff519a84 100644
--- a/src/mainboard/google/dedede/variants/kracko/include/variant/ec.h
+++ b/src/mainboard/google/dedede/variants/kracko/include/variant/ec.h
@@ -5,4 +5,9 @@
 
 #include <baseboard/ec.h>
 
+/* Enable Tablet switch for Windows drivers */
+#if !CONFIG(CHROMEOS)
+#define EC_ENABLE_TBMC_DEVICE
+#endif
+
 #endif
diff --git a/src/mainboard/google/dedede/variants/madoo/include/variant/ec.h b/src/mainboard/google/dedede/variants/madoo/include/variant/ec.h
index d6c3859c91..927b8a62d4 100644
--- a/src/mainboard/google/dedede/variants/madoo/include/variant/ec.h
+++ b/src/mainboard/google/dedede/variants/madoo/include/variant/ec.h
@@ -8,4 +8,9 @@
 /* Enable EC backed Keyboard Backlight in ACPI */
 #define EC_ENABLE_KEYBOARD_BACKLIGHT
 
+/* Enable Tablet switch for Windows drivers */
+#if !CONFIG(CHROMEOS)
+#define EC_ENABLE_TBMC_DEVICE
+#endif
+
 #endif
diff --git a/src/mainboard/google/dedede/variants/magolor/include/variant/ec.h b/src/mainboard/google/dedede/variants/magolor/include/variant/ec.h
index 27c930d4f2..f721a22ec7 100644
--- a/src/mainboard/google/dedede/variants/magolor/include/variant/ec.h
+++ b/src/mainboard/google/dedede/variants/magolor/include/variant/ec.h
@@ -8,4 +8,9 @@
 /* Enable Keyboard Backlight in ACPI */
 #define EC_ENABLE_KEYBOARD_BACKLIGHT
 
+/* Enable Tablet switch for Windows drivers */
+#if !CONFIG(CHROMEOS)
+#define EC_ENABLE_TBMC_DEVICE
+#endif
+
 #endif
diff --git a/src/mainboard/google/dedede/variants/metaknight/include/variant/ec.h b/src/mainboard/google/dedede/variants/metaknight/include/variant/ec.h
index 08870e0627..99ff519a84 100644
--- a/src/mainboard/google/dedede/variants/metaknight/include/variant/ec.h
+++ b/src/mainboard/google/dedede/variants/metaknight/include/variant/ec.h
@@ -5,4 +5,9 @@
 
 #include <baseboard/ec.h>
 
+/* Enable Tablet switch for Windows drivers */
+#if !CONFIG(CHROMEOS)
+#define EC_ENABLE_TBMC_DEVICE
+#endif
+
 #endif
diff --git a/src/mainboard/google/dedede/variants/storo/include/variant/ec.h b/src/mainboard/google/dedede/variants/storo/include/variant/ec.h
index 08870e0627..99ff519a84 100644
--- a/src/mainboard/google/dedede/variants/storo/include/variant/ec.h
+++ b/src/mainboard/google/dedede/variants/storo/include/variant/ec.h
@@ -5,4 +5,9 @@
 
 #include <baseboard/ec.h>
 
+/* Enable Tablet switch for Windows drivers */
+#if !CONFIG(CHROMEOS)
+#define EC_ENABLE_TBMC_DEVICE
+#endif
+
 #endif

From 79c98cca80cbd875ba2dd55f6a45543a8dbe0cb4 Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Fri, 14 Apr 2023 13:43:27 -0500
Subject: [PATCH 3810/3886] mb/google/volteer: Add non-ChromeOS TBMC support
 for 360/flip variants

The TBMC ACPI device is used by Windows ChromeEC drivers to determine
tablet mode and to enable motion sensors (accelerometer, gyroscope).
Since it's not needed/used by ChromeOS, restrict its inclusion to
non-ChromeOS builds.

TEST=build/boot Win11/Linux on eldrid, verify tablet mode and rotation
work properly, keyboard/touchpad disabled in tablet mode.

Change-Id: I65832388649daceb498c91e6405d2b8343ca2aeb
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91801
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
---
 .../google/volteer/variants/collis/include/variant/ec.h      | 5 +++++
 .../google/volteer/variants/copano/include/variant/ec.h      | 5 +++++
 .../google/volteer/variants/delbin/include/variant/ec.h      | 5 +++++
 .../google/volteer/variants/eldrid/include/variant/ec.h      | 5 +++++
 .../google/volteer/variants/voema/include/variant/ec.h       | 5 +++++
 .../google/volteer/variants/voxel/include/variant/ec.h       | 5 +++++
 6 files changed, 30 insertions(+)

diff --git a/src/mainboard/google/volteer/variants/collis/include/variant/ec.h b/src/mainboard/google/volteer/variants/collis/include/variant/ec.h
index 7a2a6ff8b7..dac67ca295 100644
--- a/src/mainboard/google/volteer/variants/collis/include/variant/ec.h
+++ b/src/mainboard/google/volteer/variants/collis/include/variant/ec.h
@@ -5,4 +5,9 @@
 
 #include <baseboard/ec.h>
 
+/* Enable Tablet switch for Windows drivers */
+#if !CONFIG(CHROMEOS)
+#define EC_ENABLE_TBMC_DEVICE
+#endif
+
 #endif
diff --git a/src/mainboard/google/volteer/variants/copano/include/variant/ec.h b/src/mainboard/google/volteer/variants/copano/include/variant/ec.h
index 7a2a6ff8b7..dac67ca295 100644
--- a/src/mainboard/google/volteer/variants/copano/include/variant/ec.h
+++ b/src/mainboard/google/volteer/variants/copano/include/variant/ec.h
@@ -5,4 +5,9 @@
 
 #include <baseboard/ec.h>
 
+/* Enable Tablet switch for Windows drivers */
+#if !CONFIG(CHROMEOS)
+#define EC_ENABLE_TBMC_DEVICE
+#endif
+
 #endif
diff --git a/src/mainboard/google/volteer/variants/delbin/include/variant/ec.h b/src/mainboard/google/volteer/variants/delbin/include/variant/ec.h
index 7a2a6ff8b7..dac67ca295 100644
--- a/src/mainboard/google/volteer/variants/delbin/include/variant/ec.h
+++ b/src/mainboard/google/volteer/variants/delbin/include/variant/ec.h
@@ -5,4 +5,9 @@
 
 #include <baseboard/ec.h>
 
+/* Enable Tablet switch for Windows drivers */
+#if !CONFIG(CHROMEOS)
+#define EC_ENABLE_TBMC_DEVICE
+#endif
+
 #endif
diff --git a/src/mainboard/google/volteer/variants/eldrid/include/variant/ec.h b/src/mainboard/google/volteer/variants/eldrid/include/variant/ec.h
index 7a2a6ff8b7..dac67ca295 100644
--- a/src/mainboard/google/volteer/variants/eldrid/include/variant/ec.h
+++ b/src/mainboard/google/volteer/variants/eldrid/include/variant/ec.h
@@ -5,4 +5,9 @@
 
 #include <baseboard/ec.h>
 
+/* Enable Tablet switch for Windows drivers */
+#if !CONFIG(CHROMEOS)
+#define EC_ENABLE_TBMC_DEVICE
+#endif
+
 #endif
diff --git a/src/mainboard/google/volteer/variants/voema/include/variant/ec.h b/src/mainboard/google/volteer/variants/voema/include/variant/ec.h
index 7a2a6ff8b7..dac67ca295 100644
--- a/src/mainboard/google/volteer/variants/voema/include/variant/ec.h
+++ b/src/mainboard/google/volteer/variants/voema/include/variant/ec.h
@@ -5,4 +5,9 @@
 
 #include <baseboard/ec.h>
 
+/* Enable Tablet switch for Windows drivers */
+#if !CONFIG(CHROMEOS)
+#define EC_ENABLE_TBMC_DEVICE
+#endif
+
 #endif
diff --git a/src/mainboard/google/volteer/variants/voxel/include/variant/ec.h b/src/mainboard/google/volteer/variants/voxel/include/variant/ec.h
index 4a9a461191..3e5ff526b5 100644
--- a/src/mainboard/google/volteer/variants/voxel/include/variant/ec.h
+++ b/src/mainboard/google/volteer/variants/voxel/include/variant/ec.h
@@ -5,4 +5,9 @@
 
 #include <baseboard/ec.h>
 
+/* Enable Tablet switch for Windows drivers */
+#if !CONFIG(CHROMEOS)
+#define EC_ENABLE_TBMC_DEVICE
+#endif
+
 #endif

From e232934f6ffa14b843181efa0f2d4b54a56669cc Mon Sep 17 00:00:00 2001
From: David Wu <david_wu@quanta.corp-partner.google.com>
Date: Thu, 19 Mar 2026 19:59:04 +0800
Subject: [PATCH 3811/3886] mb/google/nissa: Create dirkson variant

Create the dirkson variant of the dirks project by
copying the files to a new directory named for the variant.

BUG=b:494049087
TEST=util/abuild/abuild -p none -t google/brya -x -a
make sure the build includes GOOGLE_DIRKSON

Change-Id: I7e1257ebe8292e00a282eb75535466dcb2b459eb
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91772
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Derek Huang <derekhuang@google.com>
---
 src/mainboard/google/brya/Kconfig             |  12 +
 src/mainboard/google/brya/Kconfig.name        |   3 +
 .../google/brya/variants/dirkson/Makefile.mk  |   7 +
 .../google/brya/variants/dirkson/gpio.c       | 197 +++++++++
 .../variants/dirkson/include/variant/ec.h     |   8 +
 .../variants/dirkson/include/variant/gpio.h   |   8 +
 .../brya/variants/dirkson/memory/Makefile.mk  |  14 +
 .../dirkson/memory/dram_id.generated.txt      |  17 +
 .../dirkson/memory/mem_parts_used.txt         |  22 +
 .../brya/variants/dirkson/overridetree.cb     | 406 ++++++++++++++++++
 .../google/brya/variants/dirkson/ramstage.c   |  65 +++
 11 files changed, 759 insertions(+)
 create mode 100644 src/mainboard/google/brya/variants/dirkson/Makefile.mk
 create mode 100644 src/mainboard/google/brya/variants/dirkson/gpio.c
 create mode 100644 src/mainboard/google/brya/variants/dirkson/include/variant/ec.h
 create mode 100644 src/mainboard/google/brya/variants/dirkson/include/variant/gpio.h
 create mode 100644 src/mainboard/google/brya/variants/dirkson/memory/Makefile.mk
 create mode 100644 src/mainboard/google/brya/variants/dirkson/memory/dram_id.generated.txt
 create mode 100644 src/mainboard/google/brya/variants/dirkson/memory/mem_parts_used.txt
 create mode 100644 src/mainboard/google/brya/variants/dirkson/overridetree.cb
 create mode 100644 src/mainboard/google/brya/variants/dirkson/ramstage.c

diff --git a/src/mainboard/google/brya/Kconfig b/src/mainboard/google/brya/Kconfig
index 1084aa42ba..016c8a741a 100644
--- a/src/mainboard/google/brya/Kconfig
+++ b/src/mainboard/google/brya/Kconfig
@@ -239,6 +239,14 @@ config BOARD_GOOGLE_DIRKS
 	select SOC_INTEL_TWINLAKE
 	select SYSTEM_TYPE_MINIPC
 
+config BOARD_GOOGLE_DIRKSON
+	select BOARD_GOOGLE_BASEBOARD_NISSA
+	select RT8168_GEN_ACPI_POWER_RESOURCE
+	select RT8168_GET_MAC_FROM_VPD
+	select RT8168_SET_LED_MODE
+	select SOC_INTEL_TWINLAKE
+	select SYSTEM_TYPE_MINIPC
+
 config BOARD_GOOGLE_DOCHI
 	select BOARD_GOOGLE_BASEBOARD_BRYA
 	select CHROMEOS_WIFI_SAR if CHROMEOS
@@ -888,6 +896,7 @@ config DRIVER_TPM_I2C_BUS
 	default 0x0 if BOARD_GOOGLE_CRAASKOV
 	default 0x1 if BOARD_GOOGLE_CROTA
 	default 0x0 if BOARD_GOOGLE_DIRKS
+	default 0x0 if BOARD_GOOGLE_DIRKSON
 	default 0x1 if BOARD_GOOGLE_DOCHI
 	default 0x0 if BOARD_GOOGLE_DOMIKA
 	default 0x1 if BOARD_GOOGLE_FELWINTER
@@ -978,6 +987,7 @@ config TPM_TIS_ACPI_INTERRUPT
 	default 13 if BOARD_GOOGLE_CRAASKOV
 	default 13 if BOARD_GOOGLE_CROTA
 	default 13 if BOARD_GOOGLE_DIRKS
+	default 13 if BOARD_GOOGLE_DIRKSON
 	default 13 if BOARD_GOOGLE_DOCHI
 	default 13 if BOARD_GOOGLE_DOMIKA
 	default 13 if BOARD_GOOGLE_FELWINTER
@@ -1072,6 +1082,7 @@ config MAINBOARD_PART_NUMBER
 	default "Craaskov" if BOARD_GOOGLE_CRAASKOV
 	default "Crota" if BOARD_GOOGLE_CROTA
 	default "Dirks" if BOARD_GOOGLE_DIRKS
+	default "Dirkson" if BOARD_GOOGLE_DIRKSON
 	default "Dochi" if BOARD_GOOGLE_DOCHI
 	default "Domika" if BOARD_GOOGLE_DOMIKA
 	default "Felwinter" if BOARD_GOOGLE_FELWINTER
@@ -1155,6 +1166,7 @@ config VARIANT_DIR
 	default "craaskov" if BOARD_GOOGLE_CRAASKOV
 	default "crota" if BOARD_GOOGLE_CROTA
 	default "dirks" if BOARD_GOOGLE_DIRKS
+	default "dirkson" if BOARD_GOOGLE_DIRKSON
 	default "dochi" if BOARD_GOOGLE_DOCHI
 	default "yavilla" if BOARD_GOOGLE_DOMIKA
 	default "felwinter" if BOARD_GOOGLE_FELWINTER
diff --git a/src/mainboard/google/brya/Kconfig.name b/src/mainboard/google/brya/Kconfig.name
index bce6d1c83f..de17056ae2 100644
--- a/src/mainboard/google/brya/Kconfig.name
+++ b/src/mainboard/google/brya/Kconfig.name
@@ -45,6 +45,9 @@ config BOARD_GOOGLE_CROTA
 config BOARD_GOOGLE_DIRKS
 	bool "->  Dirks (Acer Chromebox Mini CXM2 (TWL))"
 
+config BOARD_GOOGLE_DIRKSON
+	bool "->  Dirkson"
+
 config BOARD_GOOGLE_DOCHI
 	bool "->  Dochi (Acer Chromebook Plus Spin 514)"
 
diff --git a/src/mainboard/google/brya/variants/dirkson/Makefile.mk b/src/mainboard/google/brya/variants/dirkson/Makefile.mk
new file mode 100644
index 0000000000..bc39984d6c
--- /dev/null
+++ b/src/mainboard/google/brya/variants/dirkson/Makefile.mk
@@ -0,0 +1,7 @@
+# SPDX-License-Identifier: GPL-2.0-only
+bootblock-y += gpio.c
+
+romstage-y += gpio.c
+
+ramstage-y += gpio.c
+ramstage-y += ramstage.c
diff --git a/src/mainboard/google/brya/variants/dirkson/gpio.c b/src/mainboard/google/brya/variants/dirkson/gpio.c
new file mode 100644
index 0000000000..a60615a865
--- /dev/null
+++ b/src/mainboard/google/brya/variants/dirkson/gpio.c
@@ -0,0 +1,197 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <baseboard/gpio.h>
+#include <baseboard/variants.h>
+#include <intelblocks/early_graphics.h>
+#include <soc/gpio.h>
+
+/* Pad configuration in ramstage for dirkson */
+static const struct pad_config override_gpio_table[] = {
+	/* A11 : EN_SPK_PA ==> NC */
+	PAD_NC(GPP_A11, NONE),
+	/* A14 : USB_OC1# ==> USB_A1_OC_ODL */
+	PAD_CFG_NF(GPP_A14, NONE, DEEP, NF1),
+	/* A15 : USB_OC2# ==> USB_A2_OC_ODL */
+	PAD_CFG_NF(GPP_A15, NONE, DEEP, NF1),
+	/* A16 : USB_OC3# ==> USB_A3_OC_ODL */
+	PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1),
+	/* A18 : NC ==> HDMI1_HPD_SUB_ODL*/
+	PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1),
+
+	/* B4 : LAN_PERST_L */
+	PAD_CFG_GPO(GPP_B4, 1, PLTRST),
+	/* B16 : I2C5_SDA ==> NC */
+	PAD_NC(GPP_B16, NONE),
+	/* B17 : I2C5_SCL ==> NC */
+	PAD_NC(GPP_B17, NONE),
+
+	/* C0  : SMBCLK ==> NC */
+	PAD_NC(GPP_C0, NONE),
+	/* C1  : SMBDATA ==> NC */
+	PAD_NC(GPP_C1, NONE),
+	/* C3  : SML0CLK ==> NC */
+	PAD_NC(GPP_C3, NONE),
+	/* C6  : SML1CLK ==> NC */
+	PAD_NC(GPP_C6, NONE),
+	/* C7  : SML1DATA ==> NC */
+	PAD_NC(GPP_C7, NONE),
+
+	/* D2  :  PWM_PP3300_BUZZER */
+	PAD_CFG_GPO(GPP_D2, 1, DEEP),
+	/* D3  : ISH_GP3 ==> NC */
+	PAD_NC(GPP_D3, NONE),
+	/* D6  : SRCCLKREQ1# ==> NC */
+	PAD_NC(GPP_D6, NONE),
+	/* D15  : ISH_UART0_RTS# ==> NC */
+	PAD_NC(GPP_D15, NONE),
+	/* D16  : ISH_UART0_CTS# ==> NC */
+	PAD_NC(GPP_D16, NONE),
+
+	/* E5 : [] ==> USB_A4_RT_RST_ODL */
+	PAD_CFG_GPO(GPP_E5, 1, DEEP),
+	/* E9 : USB_OC0# ==> USB_A0_OC_ODL */
+	PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1),
+	/* E22 : DDPA_CTRLCLK ==> DDPA_CTRLCLK */
+	PAD_CFG_NF(GPP_E22, NONE, DEEP, NF1),
+	/* E23 : DDPA_CTRLDATA ==> DDPA_CTRLDATA */
+	PAD_CFG_NF(GPP_E23, NONE, DEEP, NF1),
+
+	/* F13 : GSXSLOAD ==> NC */
+	PAD_NC(GPP_F13, NONE),
+	/* F14 : GSXDIN ==> LAN_WAKE_ODL */
+	PAD_CFG_GPI_SCI_LOW(GPP_F14, NONE, DEEP, EDGE_SINGLE),
+	/* F15 : GSXSRESET# ==> NC */
+	PAD_NC(GPP_F15, NONE),
+
+	/* H6  : I2C1_SDA ==> NC */
+	PAD_NC(GPP_H6, NONE),
+	/* H7  : I2C1_SCL ==> NC */
+	PAD_NC(GPP_H7, NONE),
+	/* H8  : CNV_MFUART2_RXD ==> NC */
+	PAD_NC(GPP_H8, NONE),
+	/* H9  : CNV_MFUART2_TXD ==> NC */
+	PAD_NC(GPP_H9, NONE),
+	/* H12 : UART0_RTS# ==> NC */
+	PAD_NC(GPP_H12, NONE),
+	/* H13 : UART0_CTS# ==> NC */
+	PAD_NC(GPP_H13, NONE),
+	/* H15 : HDMI_SRC_DDC_SCL */
+	PAD_CFG_NF(GPP_H15, NONE, DEEP, NF1),
+	/* H17 : HDMI_SRC_DDC_SDA */
+	PAD_CFG_NF(GPP_H17, NONE, DEEP, NF1),
+	/* H21 : IMGCLKOUT2==> LAN_PE_ISOLATE_ODL */
+	PAD_CFG_GPO(GPP_H21, 1, DEEP),
+	/* H22 : IMGCLKOUT3 ==> NC */
+	PAD_NC(GPP_H22, NONE),
+
+	/* R4 : DMIC_CLK_A_0A ==> NC */
+	PAD_NC(GPP_R4, NONE),
+	/* R5 : DMIC_DATA_0A ==> NC */
+	PAD_NC(GPP_R5, NONE),
+	/* R6 : DMIC_CLK_A_1A ==> NC */
+	PAD_NC(GPP_R6, NONE),
+	/* R7 : DMIC_DATA_1A ==> NC */
+	PAD_NC(GPP_R7, NONE),
+
+	/* S0 : I2S1_SCLK ==> NC */
+	PAD_NC(GPP_S0, NONE),
+	/* S1 : I2S1_SFRM ==> NC */
+	PAD_NC(GPP_S1, NONE),
+	/* S2 : I2S1_TXD ==> NC */
+	PAD_NC(GPP_S2, NONE),
+
+	/* Configure the virtual CNVi Bluetooth I2S GPIO pads */
+	/* BT_I2S_BCLK */
+	PAD_CFG_NF(GPP_VGPIO_30, NONE, DEEP, NF3),
+	/* BT_I2S_SYNC */
+	PAD_CFG_NF(GPP_VGPIO_31, NONE, DEEP, NF3),
+	/* BT_I2S_SDO */
+	PAD_CFG_NF(GPP_VGPIO_32, NONE, DEEP, NF3),
+	/* BT_I2S_SDI */
+	PAD_CFG_NF(GPP_VGPIO_33, NONE, DEEP, NF3),
+	/* SSP2_SCLK */
+	PAD_CFG_NF(GPP_VGPIO_34, NONE, DEEP, NF1),
+	/* SSP2_SFRM */
+	PAD_CFG_NF(GPP_VGPIO_35, NONE, DEEP, NF1),
+	/* SSP_TXD */
+	PAD_CFG_NF(GPP_VGPIO_36, NONE, DEEP, NF1),
+	/* SSP_RXD */
+	PAD_CFG_NF(GPP_VGPIO_37, NONE, DEEP, NF1),
+};
+
+/* Early pad configuration in bootblock */
+static const struct pad_config early_gpio_table[] = {
+	/* H21 : IMGCLKOUT2==> LAN_PE_ISOLATE_ODL */
+	PAD_CFG_GPO(GPP_H21, 1, DEEP),
+	/* GPP_B4 : [] ==> LAN_PERST_L */
+	PAD_CFG_GPO(GPP_B4, 0, DEEP),
+	/* H20 : IMGCLKOUT1 ==> WLAN_PERST_L */
+	PAD_CFG_GPO(GPP_H20, 0, DEEP),
+	/* A13 : GPP_A13 ==> GSC_SOC_INT_ODL */
+	PAD_CFG_GPI_APIC(GPP_A13, NONE, PLTRST, LEVEL, INVERT),
+	/* E12 : THC0_SPI1_IO1 ==> SOC_WP_OD */
+	PAD_CFG_GPI_GPIO_DRIVER(GPP_E12, NONE, DEEP),
+	/* F18 : THC1_SPI2_INT# ==> EC_IN_RW_OD */
+	PAD_CFG_GPI(GPP_F18, NONE, DEEP),
+	/* H4  : I2C0_SDA ==> SOC_I2C_GSC_SDA */
+	PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1),
+	/* H5  : I2C0_SCL ==> SOC_I2C_GSC_SCL */
+	PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1),
+	/* H10 : UART0_RXD ==> UART_SOC_RX_DBG_TX */
+	PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2),
+	/* H11 : UART0_TXD ==> UART_SOC_TX_DBG_RX */
+	PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2),
+};
+
+static const struct pad_config romstage_gpio_table[] = {
+
+	/* H20 : IMGCLKOUT1 ==> WLAN_PERST_L */
+	PAD_CFG_GPO(GPP_H20, 1, DEEP),
+};
+
+const struct pad_config early_graphics_gpio_table[] = {
+	/* A18 : NC ==> HDMI2_HPD*/
+	PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1),
+	/* A20 : DDSP_HPD2 ==> EC_SOC_HDMI_HPD */
+	PAD_CFG_NF(GPP_A20, NONE, DEEP, NF1),
+
+	/* E14 : DDSP_HPDA ==> HDMI1_HPD */
+	PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1),
+	/* E20 : DDP2_CTRLCLK ==> HDMI_DDC_SCL */
+	PAD_CFG_NF(GPP_E20, NONE, DEEP, NF1),
+	/* E21 : DDP2_CTRLDATA ==> HDMI_DDC_SDA_STRAP */
+	PAD_CFG_NF(GPP_E21, NONE, DEEP, NF1),
+	/* E22 : DDPA_CTRLCLK ==> DDPA_CTRLCLK */
+	PAD_CFG_NF(GPP_E22, NONE, DEEP, NF1),
+	/* E23 : DDPA_CTRLDATA ==> DDPA_CTRLDATA */
+	PAD_CFG_NF(GPP_E23, NONE, DEEP, NF1),
+
+	/* H15 : HDMI_SRC_DDC_SCL */
+	PAD_CFG_NF(GPP_H15, NONE, DEEP, NF1),
+	/* H17 : HDMI_SRC_DDC_SDA */
+	PAD_CFG_NF(GPP_H17, NONE, DEEP, NF1),
+};
+
+const struct pad_config *variant_early_graphics_gpio_table(size_t *num)
+{
+	*num = ARRAY_SIZE(early_graphics_gpio_table);
+	return early_graphics_gpio_table;
+}
+
+const struct pad_config *variant_gpio_override_table(size_t *num)
+{
+	*num = ARRAY_SIZE(override_gpio_table);
+	return override_gpio_table;
+}
+
+const struct pad_config *variant_early_gpio_table(size_t *num)
+{
+	*num = ARRAY_SIZE(early_gpio_table);
+	return early_gpio_table;
+}
+
+const struct pad_config *variant_romstage_gpio_table(size_t *num)
+{
+	*num = ARRAY_SIZE(romstage_gpio_table);
+	return romstage_gpio_table;
+}
diff --git a/src/mainboard/google/brya/variants/dirkson/include/variant/ec.h b/src/mainboard/google/brya/variants/dirkson/include/variant/ec.h
new file mode 100644
index 0000000000..469e75c834
--- /dev/null
+++ b/src/mainboard/google/brya/variants/dirkson/include/variant/ec.h
@@ -0,0 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#ifndef __VARIANT_EC_H__
+#define __VARIANT_EC_H__
+
+#include <baseboard/dirks/ec.h>
+
+#endif
diff --git a/src/mainboard/google/brya/variants/dirkson/include/variant/gpio.h b/src/mainboard/google/brya/variants/dirkson/include/variant/gpio.h
new file mode 100644
index 0000000000..c4fe342621
--- /dev/null
+++ b/src/mainboard/google/brya/variants/dirkson/include/variant/gpio.h
@@ -0,0 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#ifndef VARIANT_GPIO_H
+#define VARIANT_GPIO_H
+
+#include <baseboard/gpio.h>
+
+#endif
diff --git a/src/mainboard/google/brya/variants/dirkson/memory/Makefile.mk b/src/mainboard/google/brya/variants/dirkson/memory/Makefile.mk
new file mode 100644
index 0000000000..7991e5f735
--- /dev/null
+++ b/src/mainboard/google/brya/variants/dirkson/memory/Makefile.mk
@@ -0,0 +1,14 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+# This is an auto-generated file. Do not edit!!
+# Generated by:
+# util/spd_tools/bin/part_id_gen ADL lp5 src/mainboard/google/brya/variants/dirkson/memory/ src/mainboard/google/brya/variants/dirkson/memory/mem_parts_used.txt
+
+SPD_SOURCES =
+SPD_SOURCES += spd/lp5/set-0/spd-2.hex      # ID = 0(0b0000)  Parts = MT62F1G32D4DR-031 WT:B, H9JCNNNCP3MLYR-N6E
+SPD_SOURCES += spd/lp5/set-0/spd-1.hex      # ID = 1(0b0001)  Parts = MT62F512M32D2DR-031 WT:B, H9JCNNNBK3MLYR-N6E
+SPD_SOURCES += spd/lp5/set-0/spd-5.hex      # ID = 2(0b0010)  Parts = K3LKLKL0EM-MGCN
+SPD_SOURCES += spd/lp5/set-0/spd-3.hex      # ID = 3(0b0011)  Parts = K3LKBKB0BM-MGCP
+SPD_SOURCES += spd/lp5/set-0/spd-7.hex      # ID = 4(0b0100)  Parts = K3KL8L80CM-MGCT
+SPD_SOURCES += spd/lp5/set-0/spd-11.hex      # ID = 5(0b0101)  Parts = H58G56BK8BX068, H58G56CK8BX146
+SPD_SOURCES += spd/lp5/set-0/spd-8.hex      # ID = 6(0b0110)  Parts = K3KL9L90CM-MGCT
+SPD_SOURCES += spd/lp5/set-0/spd-10.hex      # ID = 7(0b0111)  Parts = H58G66BK8BX067
diff --git a/src/mainboard/google/brya/variants/dirkson/memory/dram_id.generated.txt b/src/mainboard/google/brya/variants/dirkson/memory/dram_id.generated.txt
new file mode 100644
index 0000000000..2a8769551c
--- /dev/null
+++ b/src/mainboard/google/brya/variants/dirkson/memory/dram_id.generated.txt
@@ -0,0 +1,17 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+# This is an auto-generated file. Do not edit!!
+# Generated by:
+# util/spd_tools/bin/part_id_gen ADL lp5 src/mainboard/google/brya/variants/dirkson/memory/ src/mainboard/google/brya/variants/dirkson/memory/mem_parts_used.txt
+
+DRAM Part Name                 ID to assign
+MT62F1G32D4DR-031 WT:B         0 (0000)
+MT62F512M32D2DR-031 WT:B       1 (0001)
+H9JCNNNBK3MLYR-N6E             1 (0001)
+K3LKLKL0EM-MGCN                2 (0010)
+K3LKBKB0BM-MGCP                3 (0011)
+H9JCNNNCP3MLYR-N6E             0 (0000)
+K3KL8L80CM-MGCT                4 (0100)
+H58G56BK8BX068                 5 (0101)
+K3KL9L90CM-MGCT                6 (0110)
+H58G66BK8BX067                 7 (0111)
+H58G56CK8BX146                 5 (0101)
diff --git a/src/mainboard/google/brya/variants/dirkson/memory/mem_parts_used.txt b/src/mainboard/google/brya/variants/dirkson/memory/mem_parts_used.txt
new file mode 100644
index 0000000000..f2459f39fa
--- /dev/null
+++ b/src/mainboard/google/brya/variants/dirkson/memory/mem_parts_used.txt
@@ -0,0 +1,22 @@
+# This is a CSV file containing a list of memory parts used by this variant.
+# One part per line with an optional fixed ID in column 2.
+# Only include a fixed ID if it is required for legacy reasons!
+# Generated IDs are dependent on the order of parts in this file,
+# so new parts must always be added at the end of the file!
+#
+# Generate an updated Makefile.mk and dram_id.generated.txt by running the
+# part_id_gen tool from util/spd_tools.
+# See util/spd_tools/README.md for more details and instructions.
+
+# Part Name
+MT62F1G32D4DR-031 WT:B
+MT62F512M32D2DR-031 WT:B
+H9JCNNNBK3MLYR-N6E
+K3LKLKL0EM-MGCN
+K3LKBKB0BM-MGCP
+H9JCNNNCP3MLYR-N6E
+K3KL8L80CM-MGCT
+H58G56BK8BX068
+K3KL9L90CM-MGCT
+H58G66BK8BX067
+H58G56CK8BX146
diff --git a/src/mainboard/google/brya/variants/dirkson/overridetree.cb b/src/mainboard/google/brya/variants/dirkson/overridetree.cb
new file mode 100644
index 0000000000..6a5d444f12
--- /dev/null
+++ b/src/mainboard/google/brya/variants/dirkson/overridetree.cb
@@ -0,0 +1,406 @@
+fw_config
+	field WIFI_SAR_ID 0 0
+		option ID_0			0
+		option ID_1			1
+	end
+	field WIFI_TYPE 1 2
+		option WIFI_ALL			0
+		option WIFI_CNVI		1
+		option WIFI_PCIE		2
+	end
+end
+
+chip soc/intel/alderlake
+
+	register "sagv" = "SaGv_Enabled"
+
+	# EMMC Tx CMD Delay
+	# Refer to EDS-Vol2-42.3.7.
+	# [14:8] steps of delay for DDR mode, each 125ps, range: 0 - 39.
+	# [6:0] steps of delay for SDR mode, each 125ps, range: 0 - 39.
+	register "common_soc_config.emmc_dll.emmc_tx_cmd_cntl" = "0x505"
+
+	# EMMC TX DATA Delay 1
+	# Refer to EDS-Vol2-42.3.8.
+	# [14:8] steps of delay for HS400, each 125ps, range: 0 - 78.
+	# [6:0] steps of delay for SDR104/HS200, each 125ps, range: 0 - 79.
+	register "common_soc_config.emmc_dll.emmc_tx_data_cntl1" = "0x909"
+
+	# EMMC TX DATA Delay 2
+	# Refer to EDS-Vol2-42.3.9.
+	# [30:24] steps of delay for SDR50, each 125ps, range: 0 - 79.
+	# [22:16] steps of delay for DDR50, each 125ps, range: 0 - 78.
+	# [14:8] steps of delay for SDR25/HS50, each 125ps, range: 0 -79.
+	# [6:0] steps of delay for SDR12, each 125ps. Range: 0 - 79.
+	register "common_soc_config.emmc_dll.emmc_tx_data_cntl2" = "0x1C2A2828"
+
+	# EMMC RX CMD/DATA Delay 1
+	# Refer to EDS-Vol2-42.3.10.
+	# [30:24] steps of delay for SDR50, each 125ps, range: 0 - 119.
+	# [22:16] steps of delay for DDR50, each 125ps, range: 0 - 78.
+	# [14:8] steps of delay for SDR25/HS50, each 125ps, range: 0 - 119.
+	# [6:0] steps of delay for SDR12, each 125ps, range: 0 - 119.
+	register "common_soc_config.emmc_dll.emmc_rx_cmd_data_cntl1" = "0x1C1B4F1B"
+
+	# EMMC RX CMD/DATA Delay 2
+	# Refer to EDS-Vol2-42.3.12.
+	# [17:16] stands for Rx Clock before Output Buffer,
+	#         00: Rx clock after output buffer,
+	#         01: Rx clock before output buffer,
+	#         10: Automatic selection based on working mode.
+	#         11: Reserved
+	# [14:8] steps of delay for Auto Tuning Mode, each 125ps, range: 0 - 39.
+	# [6:0] steps of delay for HS200, each 125ps, range: 0 - 79.
+	register "common_soc_config.emmc_dll.emmc_rx_cmd_data_cntl2" = "0x10023"
+
+	# EMMC Rx Strobe Delay
+	# Refer to EDS-Vol2-42.3.11.
+	# [14:8] Rx Strobe Delay DLL 1(HS400 Mode), each 125ps, range: 0 - 39.
+	# [6:0] Rx Strobe Delay DLL 2(HS400 Mode), each 125ps, range: 0 - 39.
+	register "common_soc_config.emmc_dll.emmc_rx_strobe_cntl" = "0x11515"
+
+	# SOC Aux orientation override:
+	# This is a bitfield that corresponds to up to 4 TCSS ports.
+	# Bits (0,1) allocated for TCSS Port1 configuration and Bits (2,3)for TCSS Port2.
+	# TcssAuxOri = 0101b
+	# Bit0,Bit2 set to "1" indicates no retimer on USBC Ports
+	# Bit1,Bit3 set to "0" indicates Aux lines are not swapped on the
+	# motherboard to USBC connector
+	register "tcss_aux_ori" = "0x1"
+
+	register "typec_aux_bias_pads[0]" = "{.pad_auxp_dc = GPP_A21, .pad_auxn_dc = GPP_A22}"
+
+	register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC_SKIP)"	# USB2_C0
+	# This port is repurposed from Type-C to type-A port.
+	# Still declare it as Type-C port in order to set PortResetMessageEnable UPD.
+	register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC0)"	# USB2_A0
+	register "usb2_ports[2]" = "USB2_PORT_MID(OC1)"		# USB2_A1
+	register "usb2_ports[3]" = "USB2_PORT_MID(OC2)"		# USB2_A2
+	register "usb2_ports[4]" = "USB2_PORT_MID(OC3)"		# USB2_A3
+	register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)"	# USB2_A4
+	register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)"	# Bluetooth port for PCIe WLAN
+	register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)"	# Bluetooth port for CNVi WLAN
+
+	register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)"	# USB3/2 Type A port A1
+	register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)"	# USB3/2 Type A port A2
+	register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)"	# USB3/2 Type A port A3
+	register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)"	# USB3/2 Type A port A4
+
+	register "tcss_ports[0]" = "TCSS_PORT_DEFAULT(OC_SKIP)" # USB3_C0
+	register "tcss_ports[1]" = "TCSS_PORT_DEFAULT(OC_SKIP)" # USB3/2 Type A port A0
+
+	register "serial_io_i2c_mode" = "{
+	[PchSerialIoIndexI2C0] = PchSerialIoPci,
+	[PchSerialIoIndexI2C1] = PchSerialIoDisabled,
+	[PchSerialIoIndexI2C2] = PchSerialIoDisabled,
+	[PchSerialIoIndexI2C3] = PchSerialIoPci,
+	[PchSerialIoIndexI2C4] = PchSerialIoDisabled,
+	[PchSerialIoIndexI2C5] = PchSerialIoDisabled,
+	}"
+
+	# Enable the Cnvi BT Audio Offload
+	register "cnvi_bt_audio_offload" = "1"
+
+	# Disable eDP on DDI portA
+	register "ddi_portA_config" = "0"
+
+	# Enable HPD and DDC for DDI port A
+	register "ddi_ports_config" = "{
+		[DDI_PORT_A] = DDI_ENABLE_HPD | DDI_ENABLE_DDC,
+		[DDI_PORT_B] = DDI_ENABLE_HPD | DDI_ENABLE_DDC,
+		[DDI_PORT_1] = DDI_ENABLE_HPD
+	}"
+
+	# Intel Common SoC Config
+	#+-------------------+---------------------------+
+	#| Field             |  Value                    |
+	#+-------------------+---------------------------+
+	#| I2C0              | TPM. Early init is        |
+	#|                   | required to set up a BAR  |
+	#|                   | for TPM communication     |
+	#| I2C3              | Audio                     |
+	#+-------------------+---------------------------+
+	register "common_soc_config" = "{
+		.i2c[0] = {
+			.early_init = 1,
+			.speed = I2C_SPEED_FAST_PLUS,
+			.speed_config[0] = {
+				.speed = I2C_SPEED_FAST_PLUS,
+				.scl_lcnt = 55,
+				.scl_hcnt = 30,
+				.sda_hold = 7,
+			}
+		},
+		.i2c[3] = {
+			.speed = I2C_SPEED_FAST,
+			.speed_config[0] = {
+				.speed = I2C_SPEED_FAST,
+				.scl_lcnt = 158,
+				.scl_hcnt = 79,
+				.sda_hold = 7,
+			}
+		},
+	}"
+
+	device domain 0 on
+		device ref dtt on
+			chip drivers/intel/dptf
+				## sensor information
+				register "options.tsr[0].desc" = ""Memory""
+				register "options.tsr[1].desc" = ""Charger""
+				register "options.tsr[2].desc" = ""Ambient""
+
+				# TODO: below values are initial reference values only
+				## Passive Policy
+				register "policies.passive" = "{
+					[0] = DPTF_PASSIVE(CPU,         CPU,           95, 5000),
+					[1] = DPTF_PASSIVE(CPU,         TEMP_SENSOR_0, 75, 5000),
+					[2] = DPTF_PASSIVE(CHARGER,     TEMP_SENSOR_1, 75, 5000),
+					[3] = DPTF_PASSIVE(CPU,         TEMP_SENSOR_2, 75, 5000),
+				}"
+
+				## Critical Policy
+				register "policies.critical" = "{
+					[0] = DPTF_CRITICAL(CPU,               105, SHUTDOWN),
+					[1] = DPTF_CRITICAL(TEMP_SENSOR_0,      85, SHUTDOWN),
+					[2] = DPTF_CRITICAL(TEMP_SENSOR_1,      85, SHUTDOWN),
+					[3] = DPTF_CRITICAL(TEMP_SENSOR_2,      85, SHUTDOWN),
+				}"
+
+				register "controls.power_limits" = "{
+					.pl1 = {
+							.min_power = 5500,
+							.max_power = 6000,
+							.time_window_min = 28 * MSECS_PER_SEC,
+							.time_window_max = 28 * MSECS_PER_SEC,
+							.granularity = 200
+						},
+					.pl2 = {
+							.min_power = 25000,
+							.max_power = 25000,
+							.time_window_min = 1,
+							.time_window_max = 1,
+							.granularity = 1000
+						}
+				}"
+
+				## Charger Performance Control (Control, mA)
+				register "controls.charger_perf" = "{
+					[0] = { 255, 1700 },
+					[1] = {  24, 1500 },
+					[2] = {  16, 1000 },
+					[3] = {   8,  500 }
+				}"
+
+				device generic 0 on end
+			end
+		end
+		device ref cnvi_wifi on
+			chip drivers/wifi/generic
+				register "enable_cnvi_ddr_rfim" = "true"
+				device generic 0 on
+					probe WIFI_TYPE WIFI_CNVI
+					probe WIFI_TYPE WIFI_ALL
+				end
+			end
+		end
+		device ref i2c3 on
+			chip drivers/i2c/generic
+				register "hid" = ""RTL5682""
+				register "name" = ""RT58""
+				register "desc" = ""Headset Codec""
+				register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_A23)"
+				# Set the jd_src to RT5668_JD1 for jack detection
+				register "property_count" = "1"
+				register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER"
+				register "property_list[0].name" = ""realtek,jd-src""
+				register "property_list[0].integer" = "1"
+				device i2c 1a on end
+			end
+		end
+		device ref hda on
+			chip drivers/sof
+				register "jack_tplg" = "rt5682"
+				device generic 0 on end
+			end
+		end
+		device ref pcie_rp7 on
+			# Enable PCIE 7 using clk 3
+			register "pch_pcie_rp[PCH_RP(7)]" = "{
+				.clk_src = 3,
+				.clk_req = 3,
+				.flags = PCIE_RP_LTR | PCIE_RP_AER,
+			}"
+			chip drivers/net
+				register "customized_leds" = "0x05af"
+				register "wake" = "GPE0_DW2_14"	# GPP_F14
+				register "device_index" = "0"
+				register "enable_aspm_l1_2" = "1"
+				register "add_acpi_dma_property" = "true"
+				device pci 00.0 on end
+			end
+		end # RTL8111H Ethernet NIC
+		device ref pcie_rp11 on
+			# Enable wlan PCIe 11 using clk 2
+			probe WIFI_TYPE WIFI_PCIE
+			probe WIFI_TYPE WIFI_ALL
+			register "pch_pcie_rp[PCH_RP(11)]" = "{
+				.clk_src = 2,
+				.clk_req = 2,
+				.flags = PCIE_RP_LTR | PCIE_RP_AER,
+			}"
+			chip drivers/wifi/generic
+				register "wake" = "GPE0_DW1_03"
+				register "add_acpi_dma_property" = "true"
+				use usb2_port8 as bluetooth_companion
+				device pci 00.0 on
+					probe WIFI_TYPE WIFI_PCIE
+					probe WIFI_TYPE WIFI_ALL
+				end
+			end
+			chip soc/intel/common/block/pcie/rtd3
+				register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B11)"
+				register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_H20)"
+				register "srcclk_pin" = "2"
+				device generic 0 on
+					probe WIFI_TYPE WIFI_PCIE
+					probe WIFI_TYPE WIFI_ALL
+				end
+			end
+		end
+		device ref emmc on end
+		device ref pch_espi on
+			chip ec/google/chromeec
+				use conn0 as mux_conn[0]
+				device pnp 0c09.0 on end
+			end
+		end
+		device ref pmc hidden
+			chip drivers/intel/pmc_mux
+				device generic 0 on
+					chip drivers/intel/pmc_mux/conn
+						use usb2_port1 as usb2_port
+						use tcss_usb3_port1 as usb3_port
+						device generic 0 alias conn0 on end
+					end
+				end
+			end
+		end
+		device ref tcss_xhci on
+			chip drivers/usb/acpi
+				device ref tcss_root_hub on
+					chip drivers/usb/acpi
+						register "desc" = ""USB3 Type-C Port C0""
+						register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
+						register "use_custom_pld" = "true"
+						register "custom_pld" = "ACPI_PLD_TYPE_C(BACK, RIGHT, ACPI_PLD_GROUP(2, 1))"
+						device ref tcss_usb3_port1 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB3 Type-A Port A0""
+						register "type" = "UPC_TYPE_A"
+						register "use_custom_pld" = "true"
+						register "custom_pld" = "ACPI_PLD_TYPE_A(FRONT, RIGHT, ACPI_PLD_GROUP(1, 1))"
+						device ref tcss_usb3_port2 on end
+					end
+				end
+			end
+		end
+		device ref xhci on
+			chip drivers/usb/acpi
+				device ref xhci_root_hub on
+					chip drivers/usb/acpi
+						register "desc" = ""USB2 Type-C Port C0""
+						register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
+						register "use_custom_pld" = "true"
+						register "custom_pld" = "ACPI_PLD_TYPE_C(BACK, RIGHT, ACPI_PLD_GROUP(2, 1))"
+						device ref usb2_port1 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB2 Type-A Port A0""
+						register "type" = "UPC_TYPE_A"
+						register "use_custom_pld" = "true"
+						register "custom_pld" = "ACPI_PLD_TYPE_A(FRONT, RIGHT, ACPI_PLD_GROUP(1, 1))"
+						device ref usb2_port2 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB2 Type-A Port A1""
+						register "type" = "UPC_TYPE_A"
+						register "use_custom_pld" = "true"
+						register "custom_pld" = "ACPI_PLD_TYPE_A(BACK, LEFT, ACPI_PLD_GROUP(2, 3))"
+						device ref usb2_port3 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB2 Type-A Port A2""
+						register "type" = "UPC_TYPE_A"
+						register "use_custom_pld" = "true"
+						register "custom_pld" = "ACPI_PLD_TYPE_A(FRONT, CENTER, ACPI_PLD_GROUP(1, 2))"
+						device ref usb2_port4 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB2 Type-A Port A3""
+						register "type" = "UPC_TYPE_A"
+						register "use_custom_pld" = "true"
+						register "custom_pld" = "ACPI_PLD_TYPE_A(FRONT, LEFT, ACPI_PLD_GROUP(1, 3))"
+						device ref usb2_port5 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB2 Type-A Port A4""
+						register "type" = "UPC_TYPE_A"
+						register "use_custom_pld" = "true"
+						register "custom_pld" = "ACPI_PLD_TYPE_A(BACK, CENTER, ACPI_PLD_GROUP(2, 2))"
+						device ref usb2_port6 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB2 Bluetooth""
+						register "type" = "UPC_TYPE_INTERNAL"
+						register "reset_gpio" =
+							"ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D4)"
+						device ref usb2_port8 on
+							probe WIFI_TYPE WIFI_PCIE
+							probe WIFI_TYPE WIFI_ALL
+						end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""CNVI Bluetooth""
+						register "type" = "UPC_TYPE_INTERNAL"
+						register "reset_gpio" =
+							"ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D4)"
+						device ref usb2_port10 on
+							probe WIFI_TYPE WIFI_CNVI
+							probe WIFI_TYPE WIFI_ALL
+						end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB3 Type-A Port A1""
+						register "type" = "UPC_TYPE_USB3_A"
+						register "use_custom_pld" = "true"
+						register "custom_pld" = "ACPI_PLD_TYPE_A(BACK, LEFT, ACPI_PLD_GROUP(2, 3))"
+						device ref usb3_port1 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB3 Type-A Port A2""
+						register "type" = "UPC_TYPE_USB3_A"
+						register "use_custom_pld" = "true"
+						register "custom_pld" = "ACPI_PLD_TYPE_A(FRONT, CENTER, ACPI_PLD_GROUP(1, 2))"
+						device ref usb3_port2 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB3 Type-A Port A3""
+						register "type" = "UPC_TYPE_USB3_A"
+						register "use_custom_pld" = "true"
+						register "custom_pld" = "ACPI_PLD_TYPE_A(FRONT, LEFT, ACPI_PLD_GROUP(1, 3))"
+						device ref usb3_port3 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB3 Type-A Port A4""
+						register "type" = "UPC_TYPE_USB3_A"
+						register "use_custom_pld" = "true"
+						register "custom_pld" = "ACPI_PLD_TYPE_A(BACK, CENTER, ACPI_PLD_GROUP(2, 2))"
+						device ref usb3_port4 on end
+					end
+				end
+			end
+		end
+	end
+end
diff --git a/src/mainboard/google/brya/variants/dirkson/ramstage.c b/src/mainboard/google/brya/variants/dirkson/ramstage.c
new file mode 100644
index 0000000000..1a9013b993
--- /dev/null
+++ b/src/mainboard/google/brya/variants/dirkson/ramstage.c
@@ -0,0 +1,65 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <baseboard/variants.h>
+#include <chip.h>
+#include <device/device.h>
+#include <device/pci_ids.h>
+#include <device/pci_ops.h>
+#include <ec/google/chromeec/ec.h>
+#include <intelblocks/power_limit.h>
+#include <soc/ramstage.h>
+
+void mainboard_silicon_init_params(FSP_S_CONFIG *params)
+{
+	/*Enable Type C port1 convert to Type A*/
+	params->EnableTcssCovTypeA[1] = 1;
+	/* PCH xchi port number for Type C port1 port mapping */
+	params->MappingPchXhciUsbA[1] = 2;
+
+}
+
+const struct cpu_power_limits limits[] = {
+	/* SKU_ID, TDP (Watts), pl1_min, pl1_max, pl2_min, pl2_max, pl4 */
+	{ PCI_DID_INTEL_ADL_N_ID_1, 7, 3000, 6000,  25000,  25000, 78000 },
+	{ PCI_DID_INTEL_ADL_N_ID_2, 6, 3000, 6000,  25000,  25000, 78000 },
+	{ PCI_DID_INTEL_ADL_N_ID_3, 6, 3000, 6000,  25000,  25000, 78000 },
+};
+
+const struct system_power_limits sys_limits[] = {
+	/* SKU_ID, TDP (Watts), psys_pl2 (Watts) */
+	{ PCI_DID_INTEL_ADL_N_ID_1, 7, 63 },
+	{ PCI_DID_INTEL_ADL_N_ID_2, 6, 63 },
+	{ PCI_DID_INTEL_ADL_N_ID_3, 6, 63 },
+};
+
+/*
+ * Psys_pmax considerations.
+ *
+ * Given the hardware design in dirkson, the serial shunt resistor is 0.01ohm.
+ * The full scale of hardware PSYS signal 1.6v maps to system current 6.009A
+ * instead of real system power. The equation is shown below:
+ * PSYS = 1.6v ~= (0.01ohm x 6.009A) x 50 (INA213, gain 50V/V) x PR222/(PR222 + R3193)
+ * PR222/(PR222 + R3193) = 0.5325 = 36K / (36K + 31.6K)
+ *
+ * The Psys_pmax is a SW setting which tells IMVP9.1 the mapping between system input
+ * current and the actual system power. Since there is no voltage information
+ * from PSYS, different voltage input would map to different Psys_pmax settings:
+ * For Type-C 15V, the Psys_pmax should be 15v x 6.009A = 90.135W
+ * For Type-C 20V, the Psys_pmax should be 20v x 6.009A = 120.18W
+ * For a barrel jack, the Psys_pmax should be 19v x 6.009A = 114.171W
+ *
+ * Imagine that there is a type-c 100W (20V/5A) connected to DUT w/ full loading,
+ * and the Psys_pmax setting is 120W. Then IMVP9.1 can calculate the current system
+ * power = 120W * 5A / 6.009A = 100W, which is the actual system power.
+ */
+const struct psys_config psys_config = {
+	.efficiency = 97,
+	.psys_imax_ma = 6009,
+	.bj_volts_mv = 19000,
+};
+
+void variant_devtree_update(void)
+{
+	size_t total_entries = ARRAY_SIZE(limits);
+	variant_update_psys_power_limits(limits, sys_limits, total_entries, &psys_config);
+}

From e021937f3585debe835fda7022436d2a8d9c2a0a Mon Sep 17 00:00:00 2001
From: Patrick Rudolph <patrick.rudolph@9elements.com>
Date: Mon, 23 Mar 2026 10:58:08 +0100
Subject: [PATCH 3812/3886] soc/amd/glinda: Add RAS Kconfig options

On Faegan the FSP supports RAS. Allow the user to configure
RAS features and pass them to the FSP using UPDs.

Change-Id: Ia7091d216a446d56632e64f9bba0e2a166410139
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91819
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
---
 src/soc/amd/glinda/Kconfig        | 45 +++++++++++++++++++++++++++++++
 src/soc/amd/glinda/fsp_m_params.c | 25 +++++++++++++++++
 2 files changed, 70 insertions(+)

diff --git a/src/soc/amd/glinda/Kconfig b/src/soc/amd/glinda/Kconfig
index 29b404ac3d..59c7b3a277 100644
--- a/src/soc/amd/glinda/Kconfig
+++ b/src/soc/amd/glinda/Kconfig
@@ -456,6 +456,51 @@ config CMOS_RECOVERY_BYTE
 	  This is the byte before the default first byte used by VBNV
 	  (0x26 + 0x0E - 1)
 
+menu "RAS Config Options"
+choice
+	prompt "PCIe AER Report Mechanism"
+	depends on SOC_AMD_FAEGAN
+	default AMD_PCIE_AER_OS_FIRST_HANDLING
+	help
+	  Choose a PCIe AER Report Mechanism.
+
+config AMD_PCIE_AER_PFEH_FIRMWARE_FIRST_REPORTING
+	bool "PFEH-based Firmware First reporting"
+
+config AMD_PCIE_AER_OS_FIRST_HANDLING
+	bool "OS First handling"
+
+config AMD_PCIE_AER_FIRMWARE_FIRST_HANDLING
+	bool "Firmware First handling through SMI"
+endchoice
+
+choice
+	prompt "AMD NBIO Ras Control V2"
+	depends on SOC_AMD_FAEGAN
+	default AMD_NBIO_RAS_MCA_REPORTING if SOC_AMD_FAEGAN
+	default AMD_NBIO_RAS_DISABLE
+	help
+	  Choose an AMD NBIO RAS control option.
+
+config AMD_NBIO_RAS_DISABLE
+	bool "Disable NBIO Ras Control"
+
+config AMD_NBIO_RAS_MCA_REPORTING
+	bool "MCA reporting"
+
+config AMD_NBIO_RAS_LEGACY_MODE
+	bool "Legacy Mode"
+endchoice
+
+config AMD_PCIE_ECRC_ENABLEMENT
+	bool "PCIe ECRC Enablement"
+	depends on SOC_AMD_FAEGAN
+	default y if SOC_AMD_FAEGAN
+	default n
+	help
+	  Enable/Disable PCIe ECRC support.
+endmenu
+
 if VBOOT_SLOTS_RW_AB && VBOOT_STARTS_BEFORE_BOOTBLOCK
 
 config RWA_REGION_ONLY
diff --git a/src/soc/amd/glinda/fsp_m_params.c b/src/soc/amd/glinda/fsp_m_params.c
index ff5f04c7f2..cff9b01ae2 100644
--- a/src/soc/amd/glinda/fsp_m_params.c
+++ b/src/soc/amd/glinda/fsp_m_params.c
@@ -160,6 +160,31 @@ void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version)
 	mcfg->enable_nb_azalia = is_dev_enabled(DEV_PTR(gfx_hda));
 	mcfg->hda_enable = is_dev_enabled(DEV_PTR(hda));
 
+	/* Faegan only: RAS Config Options */
+	if (CONFIG(SOC_AMD_FAEGAN)) {
+		if (CONFIG(AMD_PCIE_AER_OS_FIRST_HANDLING))
+			mcfg->amd_pcie_aer_report_mechanism = 1;
+		else if (CONFIG(AMD_PCIE_AER_FIRMWARE_FIRST_HANDLING))
+			mcfg->amd_pcie_aer_report_mechanism = 2;
+		else
+			mcfg->amd_pcie_aer_report_mechanism = 0;
+
+		if (CONFIG(AMD_NBIO_RAS_MCA_REPORTING))
+			mcfg->amd_nbio_ras_controlv2 = 1;
+		else if (CONFIG(AMD_NBIO_RAS_LEGACY_MODE))
+			mcfg->amd_nbio_ras_controlv2 = 2;
+		else
+			mcfg->amd_nbio_ras_controlv2 = 0;
+
+		mcfg->pcie_ecrc_enablement = CONFIG(AMD_PCIE_ECRC_ENABLEMENT);
+		printk(BIOS_SPEW, "mcfg->amd_pcie_aer_report_mechanism %x\n",
+		       mcfg->amd_pcie_aer_report_mechanism);
+		printk(BIOS_SPEW, "mcfg->amd_nbio_ras_controlv2 %x\n",
+		       mcfg->amd_nbio_ras_controlv2);
+		printk(BIOS_SPEW, "mcfg->pcie_ecrc_enablement %x\n",
+		       mcfg->pcie_ecrc_enablement);
+	}
+
 	if (config->usb_phy_custom) {
 		/* devicetree config is const, use local copy */
 		static struct usb_phy_config lcl_usb_phy;

From 82de37d171135f36344c1beb4493317aeb88f659 Mon Sep 17 00:00:00 2001
From: Yu-Ping Wu <yupingso@google.com>
Date: Thu, 5 Mar 2026 16:51:05 +0800
Subject: [PATCH 3813/3886] libpayload: Makefile.mk: Fix unrecognized option
 '--no-weak'

aarch64-elf nm doesn't support '--no-weak'. Replace the 'nm --no-weak'
call with 'grep' with "[TDRCB]" pattern to collect the non-weak
symbols.

Change-Id: I19195034b31f39086946b7e5ee15317d6f5dd880
Signed-off-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91566
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
---
 payloads/libpayload/Makefile.mk | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/payloads/libpayload/Makefile.mk b/payloads/libpayload/Makefile.mk
index f7c2c8bda0..0f5d1a0e11 100644
--- a/payloads/libpayload/Makefile.mk
+++ b/payloads/libpayload/Makefile.mk
@@ -111,8 +111,8 @@ includes-handler= \
 $(obj)/libpayload.a: $(foreach class,$(libraries),$$($(class)-objs))
 	printf "    AR         $(subst $(CURDIR)/,,$(@))\n"
 	printf "create $@\n$(foreach objc,$(filter-out %.a,$^),addmod $(objc)\n)$(foreach lib,$(filter %.a,$^),addlib $(lib)\n)save\nend\n" | $(AR) -M
-	for func in $$($(NM) $@ | awk '/ (w|W) / { print $$NF }'); do \
-		if $(NM) --no-weak --defined-only $@ | grep -Eq " $$func$$"; then \
+	for func in $$($(NM) $@ | awk '/ [wW] / { print $$NF }'); do \
+		if $(NM) $@ 2>/dev/null | grep -Eq " [TDRCB] $${func}$$"; then \
 			printf "\nERROR: Function '$$func' appears as both weak and strong symbol in libpayload.\n"; \
 			printf "       Weak symbol overrides don't work reliably from within the same library.\n\n"; \
 			rm $@; \

From c0e82f6963c291b30e4fef72ebcd93662c4f699c Mon Sep 17 00:00:00 2001
From: Felix Held <felix-coreboot@felixheld.de>
Date: Wed, 25 Mar 2026 16:54:34 +0100
Subject: [PATCH 3814/3886] 3rdparty/amd_blobs: advance submodule pointer

This pulls in the following change from the submodule:
- add binaries for V2000A

Change-Id: I606f7926bcdef2a02ed1f492f37a0d7aefa27714
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91856
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 3rdparty/amd_blobs | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/3rdparty/amd_blobs b/3rdparty/amd_blobs
index 0a6d270fb3..aa9288a33c 160000
--- a/3rdparty/amd_blobs
+++ b/3rdparty/amd_blobs
@@ -1 +1 @@
-Subproject commit 0a6d270fb36f726b26909c3369f155e44afeedc4
+Subproject commit aa9288a33c6d7a67e55b8757390029207593fa9f

From 800d3dbef4069a9e4d35e97af4617c944a82fb06 Mon Sep 17 00:00:00 2001
From: Subrata Banik <subratabanik@google.com>
Date: Wed, 25 Mar 2026 21:20:22 +0530
Subject: [PATCH 3815/3886] soc/qualcomm/x1p42100: Support separate RO/RW CPUCP
 binaries

The CPUCP (CPU Control Processor) binary is currently stored
uncompressed in the RO region. To save space in the RO section
while maintaining fast boot performance in normal mode, split the
CPUCP CBFS entry into two distinct files:

1. cpucp_rw: Stored in FW_MAIN_A and FW_MAIN_B with no compression
   for performance.
2. cpucp_ro: Stored in the COREBOOT (RO) region with LZMA
   compression to save flash space.

Update the loading logic in cpucp_load_reset.c to select the
appropriate binary based on the current vboot mode (Normal vs.
Recovery).

BUG=None
TEST=Verified that CPUCP loads from 'cpucp_rw' during normal boot
and 'cpucp_ro' when vboot recovery is triggered.

Normal Mode:
```
[INFO ]  CBFS: Found 'fallback/cpucp_rw' @0xc8640 size 0x79244
         in mcache @0x8669d628
```

Recovery Mode:
```
[INFO ]  CBFS: Found 'fallback/cpucp_ro' @0xc8640 size 0x79244
         in mcache @0x8669d628
```

Change-Id: Iec5294beec4377b13f8b7354d86055d5907c6556
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91852
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
---
 src/soc/qualcomm/x1p42100/Makefile.mk        | 19 ++++++++++++++-----
 src/soc/qualcomm/x1p42100/cpucp_load_reset.c |  8 ++++++--
 2 files changed, 20 insertions(+), 7 deletions(-)

diff --git a/src/soc/qualcomm/x1p42100/Makefile.mk b/src/soc/qualcomm/x1p42100/Makefile.mk
index cfb8410e60..2fdade4c6a 100644
--- a/src/soc/qualcomm/x1p42100/Makefile.mk
+++ b/src/soc/qualcomm/x1p42100/Makefile.mk
@@ -222,11 +222,20 @@ cbfs-files-y += $(AOP_DEVCFG_META_CBFS)
 
 ################################################################################
 CPUCP_FILE := $(X1P42100_BLOB)/cpucp/cpucp.elf
-CPUCP_CBFS := $(CONFIG_CBFS_PREFIX)/cpucp
-$(CPUCP_CBFS)-file := $(CPUCP_FILE)
-$(CPUCP_CBFS)-type := payload
-$(CPUCP_CBFS)-compression := none
-cbfs-files-y += $(CPUCP_CBFS)
+
+CPUCP_CBFS_RW := $(CONFIG_CBFS_PREFIX)/cpucp_rw
+regions-for-file-$(CPUCP_CBFS_RW) = FW_MAIN_A,FW_MAIN_B
+$(CPUCP_CBFS_RW)-file := $(CPUCP_FILE)
+$(CPUCP_CBFS_RW)-type := payload
+$(CPUCP_CBFS_RW)-compression := none
+cbfs-files-y += $(CPUCP_CBFS_RW)
+
+CPUCP_CBFS_RO := $(CONFIG_CBFS_PREFIX)/cpucp_ro
+regions-for-file-$(CPUCP_CBFS_RO) = COREBOOT
+$(CPUCP_CBFS_RO)-file := $(CPUCP_FILE)
+$(CPUCP_CBFS_RO)-type := payload
+$(CPUCP_CBFS_RO)-compression := $(CBFS_COMPRESS_FLAG)
+cbfs-files-y += $(CPUCP_CBFS_RO)
 
 ################################################################################
 # Rule to create cpucp_meta from cpucp.elf
diff --git a/src/soc/qualcomm/x1p42100/cpucp_load_reset.c b/src/soc/qualcomm/x1p42100/cpucp_load_reset.c
index 274c724724..80e3a39283 100644
--- a/src/soc/qualcomm/x1p42100/cpucp_load_reset.c
+++ b/src/soc/qualcomm/x1p42100/cpucp_load_reset.c
@@ -6,6 +6,7 @@
 #include <program_loading.h>
 #include <soc/cpucp.h>
 #include <device/mmio.h>
+#include <security/vboot/vboot_common.h>
 #include <soc/addressmap.h>
 #include <soc/mmu_common.h>
 #include <soc/symbols_common.h>
@@ -24,8 +25,11 @@ void cpucp_fw_load_reset(void)
 
 	printk(BIOS_DEBUG, "SOC image: CPUCP DTBS image loaded successfully.\n");
 
-	struct prog cpucp_fw_prog =
-		PROG_INIT(PROG_PAYLOAD, CONFIG_CBFS_PREFIX "/cpucp");
+	const char *cpucp_name = (CONFIG(VBOOT) && !vboot_recovery_mode_enabled())
+			 ? CONFIG_CBFS_PREFIX "/cpucp_rw"
+			 : CONFIG_CBFS_PREFIX "/cpucp_ro";
+
+	struct prog cpucp_fw_prog = PROG_INIT(PROG_PAYLOAD, cpucp_name);
 
 	if (!selfload(&cpucp_fw_prog))
 		die("SOC image: CPUCP load failed");

From 576515394c0c427289e780b6a11d374ce480f81d Mon Sep 17 00:00:00 2001
From: Patrick Rudolph <patrick.rudolph@9elements.com>
Date: Wed, 25 Mar 2026 16:45:28 +0100
Subject: [PATCH 3816/3886] util/amdfwtool: Use uint8_t for bitfields

Using a signed, non-fixed-width type for bitfields can cause problems.
So, use uint8_t since the affected bitfields occupy exactly one byte.

Change-Id: I728072b10baf77819a387df76b588b6a826e2841
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91855
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
---
 util/amdfwtool/amdfwtool.h | 10 +++++-----
 1 file changed, 5 insertions(+), 5 deletions(-)

diff --git a/util/amdfwtool/amdfwtool.h b/util/amdfwtool/amdfwtool.h
index 0d1a6a2e70..43acbd4807 100644
--- a/util/amdfwtool/amdfwtool.h
+++ b/util/amdfwtool/amdfwtool.h
@@ -296,11 +296,11 @@ typedef struct _bios_directory_hdr {
 typedef struct _bios_directory_entry {
 	uint8_t type;
 	uint8_t region_type;
-	int reset:1;
-	int copy:1;
-	int ro:1;
-	int compressed:1;
-	int inst:4;
+	uint8_t reset:1;
+	uint8_t copy:1;
+	uint8_t ro:1;
+	uint8_t compressed:1;
+	uint8_t inst:4;
 	uint8_t subprog:3;
 	uint8_t romid:2;
 	uint8_t writable:1;

From c5e905fa21a6c729b434ac7f9b5fec45a98c6cec Mon Sep 17 00:00:00 2001
From: Maximilian Brune <maximilian.brune@9elements.com>
Date: Thu, 26 Mar 2026 16:18:52 +0100
Subject: [PATCH 3817/3886] util/mec152x/Makefile: Include
 commonlib/bsd/compiler.h

cbfstool/flashmap/kv_pair.h uses the `__printf` macro. So we need to
include the header file defining `__printf` in the compilation.

The tooling can now be compiled on its own outside the coreboot build
system.

Change-Id: I5a622b50684c42773e66e6d9145d5de9858c9e9a
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91887
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 util/mec152x/Makefile | 1 +
 1 file changed, 1 insertion(+)

diff --git a/util/mec152x/Makefile b/util/mec152x/Makefile
index 43b350145c..fea5f364a0 100644
--- a/util/mec152x/Makefile
+++ b/util/mec152x/Makefile
@@ -13,6 +13,7 @@ HOSTCFLAGS ?= $(CFLAGS)
 HOSTCFLAGS += -Wall -Wextra -MMD -MP -O3
 HOSTCFLAGS += -I $(TOP)/util/cbfstool/flashmap/
 HOSTCFLAGS += -I $(ROOT)/commonlib/bsd/include
+HOSTCFLAGS += -include $(TOP)/src/commonlib/bsd/include/commonlib/bsd/compiler.h
 
 HOSTLDFLAGS ?= $(LDFLAGS)
 

From f1e95c55363bc52221c8dafa374c7fe6bd7fd3f1 Mon Sep 17 00:00:00 2001
From: Arthur Heymans <arthur@aheymans.xyz>
Date: Wed, 25 Mar 2026 23:12:58 +0100
Subject: [PATCH 3818/3886] mb/qemu/riscv: Intialize PCI root bus

Allocate resources to devices on the bus.
This booted to the fedora disk image using nvme with the CrabEFI payload.

Change-Id: I898b38fd4fa94f7d1a73132d6f821ff7c9e201dd
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91881
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
---
 .../emulation/qemu-riscv/devicetree.cb        |  5 +++
 .../qemu-riscv/include/mainboard/addressmap.h |  7 +++
 .../emulation/qemu-riscv/mainboard.c          | 44 +++++++++++++++++--
 src/mainboard/emulation/qemu-riscv/mmio.c     |  2 +-
 4 files changed, 53 insertions(+), 5 deletions(-)

diff --git a/src/mainboard/emulation/qemu-riscv/devicetree.cb b/src/mainboard/emulation/qemu-riscv/devicetree.cb
index 9de1b75f50..8df5c9843b 100644
--- a/src/mainboard/emulation/qemu-riscv/devicetree.cb
+++ b/src/mainboard/emulation/qemu-riscv/devicetree.cb
@@ -2,4 +2,9 @@
 
 chip mainboard/emulation/qemu-riscv
 	device cpu_cluster 0 on end
+
+	device domain 0 on
+		ops qemu_riscv_pci_domain_ops
+		device pci 00.0 on end
+	end
 end
diff --git a/src/mainboard/emulation/qemu-riscv/include/mainboard/addressmap.h b/src/mainboard/emulation/qemu-riscv/include/mainboard/addressmap.h
index eb0e9f3440..f36491c50c 100644
--- a/src/mainboard/emulation/qemu-riscv/include/mainboard/addressmap.h
+++ b/src/mainboard/emulation/qemu-riscv/include/mainboard/addressmap.h
@@ -1,9 +1,16 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
 #define QEMU_VIRT_CLINT		0x02000000
+#define QEMU_VIRT_PCIE_PIO	0x03000000
 #define QEMU_VIRT_PLIC		0x0c000000
 #define QEMU_VIRT_UART0		0x10000000
 #define QEMU_VIRT_VIRTIO	0x10001000
 #define QEMU_VIRT_FW_CFG	0x10100000
 #define QEMU_VIRT_FLASH		0x20000000
+#define QEMU_VIRT_PCIE_ECAM	0x30000000
+#define QEMU_VIRT_PCIE_ECAM_SIZE 0x10000000
+#define QEMU_VIRT_PCIE_MMIO_BASE  0x40000000
+#define QEMU_VIRT_PCIE_MMIO_LIMIT 0x7fffffff
 #define QEMU_VIRT_DRAM		0x80000000
+#define QEMU_VIRT_PCIE_MMIO_HIGH_BASE  0x300000000ULL
+#define QEMU_VIRT_PCIE_MMIO_HIGH_LIMIT 0x3ffffffffULL
diff --git a/src/mainboard/emulation/qemu-riscv/mainboard.c b/src/mainboard/emulation/qemu-riscv/mainboard.c
index 61e8f98925..e801d14ba7 100644
--- a/src/mainboard/emulation/qemu-riscv/mainboard.c
+++ b/src/mainboard/emulation/qemu-riscv/mainboard.c
@@ -2,16 +2,52 @@
 
 #include <console/console.h>
 #include <device/device.h>
+#include <device/pci.h>
 #include <symbols.h>
 #include <cbmem.h>
+#include <mainboard/addressmap.h>
+
+static void qemu_riscv_domain_read_resources(struct device *dev)
+{
+	struct resource *res;
+	int index = 0;
+
+	/* PCI I/O port window */
+	res = new_resource(dev, index++);
+	res->limit = 0xffff;
+	res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED;
+
+	/* 32-bit PCI MMIO window */
+	res = new_resource(dev, index++);
+	res->base = QEMU_VIRT_PCIE_MMIO_BASE;
+	res->limit = QEMU_VIRT_PCIE_MMIO_LIMIT;
+	res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED;
+
+	/*
+	 * NOTE: 64-bit MMIO window (0x300000000-0x3ffffffff) is omitted
+	 * because OpenSBI 1.1 (bundled with coreboot) does not add PMP
+	 * entries for it, causing S-mode load access faults.  All BARs
+	 * will be assigned in the 32-bit window which is plenty for the
+	 * QEMU virt machine's typical device set.
+	 */
+
+	/* ECAM config space (fixed MMIO) */
+	mmio_range(dev, index++, QEMU_VIRT_PCIE_ECAM, QEMU_VIRT_PCIE_ECAM_SIZE);
+
+	/* DRAM */
+	ram_from_to(dev, index++, (uintptr_t)_dram, cbmem_top());
+}
+
+struct device_operations qemu_riscv_pci_domain_ops = {
+	.read_resources    = qemu_riscv_domain_read_resources,
+	.set_resources     = pci_domain_set_resources,
+	.scan_bus          = pci_host_bridge_scan_bus,
+};
 
 static void mainboard_enable(struct device *dev)
 {
-	if (!dev) {
+	if (!dev)
 		die("No dev0; die\n");
-	}
-
-	ram_from_to(dev, 0, (uintptr_t)_dram, cbmem_top());
 }
 
 struct chip_operations mainboard_ops = {
diff --git a/src/mainboard/emulation/qemu-riscv/mmio.c b/src/mainboard/emulation/qemu-riscv/mmio.c
index 86fc626d14..9c38a74741 100644
--- a/src/mainboard/emulation/qemu-riscv/mmio.c
+++ b/src/mainboard/emulation/qemu-riscv/mmio.c
@@ -3,4 +3,4 @@
 #include <types.h>
 #include <mainboard/addressmap.h>
 
-uintptr_t io_port_mmio_base = QEMU_VIRT_FW_CFG;
+uintptr_t io_port_mmio_base = QEMU_VIRT_PCIE_PIO;

From 1a75cd1da295fb16671595b98f4def2788d346bf Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Fri, 20 Mar 2026 11:37:58 -0500
Subject: [PATCH 3819/3886] mb/google/glados: Add MKBP support

Add MKBP support for glados devices, so that vivaldi keyboard works for
devices running upstream coreboot and MrChromebox ECRW firmware.

TEST=build/boot google/chell, verify vivaldi keyboard mapping functional
under both Linux and Win11.

Change-Id: Ia1ea5cdece52d33f7467af0b6e1d891a04b63b94
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91783
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
---
 src/mainboard/google/glados/acpi/ec.asl | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/src/mainboard/google/glados/acpi/ec.asl b/src/mainboard/google/glados/acpi/ec.asl
index a1276b2167..132194a6a3 100644
--- a/src/mainboard/google/glados/acpi/ec.asl
+++ b/src/mainboard/google/glados/acpi/ec.asl
@@ -5,6 +5,9 @@
 #include <variant/ec.h>
 #include <variant/gpio.h>
 
+/* Enable MKBP for buttons and switches */
+#define EC_ENABLE_MKBP_DEVICE
+
 /* Enable EC backed PD MCU device in ACPI */
 #define EC_ENABLE_PD_MCU_DEVICE
 

From caf980b3fac701f5f840597060e30bf8183993f9 Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Fri, 20 Mar 2026 11:41:33 -0500
Subject: [PATCH 3820/3886] mb/google/hatch: Add MKBP support

Add MKBP support for hatch devices, so that vivaldi keyboard works for
devices running upstream coreboot and MrChromebox ECRW firmware.

TEST=build/boot google/akemi, verify vivaldi keyboard mapping functional
under both Linux and Win11.

Change-Id: I7bd222160efdd4de0d63ab9542c0d2828aac583a
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91784
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
---
 .../google/hatch/variants/baseboard/include/baseboard/ec.h     | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/src/mainboard/google/hatch/variants/baseboard/include/baseboard/ec.h b/src/mainboard/google/hatch/variants/baseboard/include/baseboard/ec.h
index a1a71c0fd0..771cd1e5b2 100644
--- a/src/mainboard/google/hatch/variants/baseboard/include/baseboard/ec.h
+++ b/src/mainboard/google/hatch/variants/baseboard/include/baseboard/ec.h
@@ -53,6 +53,9 @@
  * ACPI related definitions for ASL code.
  */
 
+/* Enable MKBP for buttons and switches */
+#define EC_ENABLE_MKBP_DEVICE
+
 /* Enable EC backed PD MCU device in ACPI */
 #define EC_ENABLE_PD_MCU_DEVICE
 

From 134b3e050a4439d9356d03190a9b1d80837cd6f8 Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Fri, 20 Mar 2026 11:42:04 -0500
Subject: [PATCH 3821/3886] mb/google/octopus: Add MKBP support

Add MKBP support for octopus devices, so that vivaldi keyboard works for
devices running upstream coreboot and MrChromebox ECRW firmware.

TEST=build/boot google/ampton, verify vivaldi keyboard mapping
functional under both Linux and Win11.

Change-Id: I31ecd87d8e9335dd4131f022370b32bf2d056b03
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91785
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
---
 .../google/octopus/variants/baseboard/include/baseboard/ec.h   | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/src/mainboard/google/octopus/variants/baseboard/include/baseboard/ec.h b/src/mainboard/google/octopus/variants/baseboard/include/baseboard/ec.h
index 857c1f933c..9a42083525 100644
--- a/src/mainboard/google/octopus/variants/baseboard/include/baseboard/ec.h
+++ b/src/mainboard/google/octopus/variants/baseboard/include/baseboard/ec.h
@@ -58,6 +58,9 @@
  * ACPI related definitions for ASL code.
  */
 
+/* Enable MKBP for buttons and switches */
+#define EC_ENABLE_MKBP_DEVICE
+
 /* Enable LID switch and provide wake pin for EC */
 #define EC_ENABLE_LID_SWITCH
 #define EC_ENABLE_WAKE_PIN      GPE_EC_WAKE

From a5b5591d31f4755b3f21e5f90a8e7551c9206e69 Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Fri, 20 Mar 2026 11:42:31 -0500
Subject: [PATCH 3822/3886] mb/google/reef: Add MKBP support

Add MKBP support for reef devices, so that vivaldi keyboard works for
devices running upstream coreboot and MrChromebox ECRW firmware.

TEST=build/boot google/reef, verify vivaldi keyboard mapping functional
under both Linux and Win11.

Change-Id: If7a8df8469c22404e22d80fd4d116b862b6b5cec
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91786
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 .../google/reef/variants/baseboard/include/baseboard/ec.h      | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/src/mainboard/google/reef/variants/baseboard/include/baseboard/ec.h b/src/mainboard/google/reef/variants/baseboard/include/baseboard/ec.h
index 6f22832d5f..4ad2f97cb1 100644
--- a/src/mainboard/google/reef/variants/baseboard/include/baseboard/ec.h
+++ b/src/mainboard/google/reef/variants/baseboard/include/baseboard/ec.h
@@ -47,6 +47,9 @@
  * ACPI related definitions for ASL code.
  */
 
+/* Enable MKBP for buttons and switches */
+#define EC_ENABLE_MKBP_DEVICE
+
 /* Enable EC backed PD MCU device in ACPI */
 #define EC_ENABLE_PD_MCU_DEVICE
 

From f1505f5e4647d05addded080d70e3d41ca25788f Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Fri, 20 Mar 2026 11:42:57 -0500
Subject: [PATCH 3823/3886] mb/google/zork: Add MKBP support

Add MKBP support for zork devices, so that vivaldi keyboard works for
devices running upstream coreboot and MrChromebox ECRW firmware.

TEST=build/boot google/morphius, verify vivaldi keyboard mapping
functional under both Linux and Win11.

Change-Id: I021454b92cdb90e2a385eee1b3d4cc0438c75132
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91787
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
---
 .../google/zork/variants/baseboard/include/baseboard/ec.h      | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/src/mainboard/google/zork/variants/baseboard/include/baseboard/ec.h b/src/mainboard/google/zork/variants/baseboard/include/baseboard/ec.h
index b28a4894c4..2c503aed1d 100644
--- a/src/mainboard/google/zork/variants/baseboard/include/baseboard/ec.h
+++ b/src/mainboard/google/zork/variants/baseboard/include/baseboard/ec.h
@@ -58,6 +58,9 @@
 /* Enable EC backed PD MCU device in ACPI */
 #define EC_ENABLE_PD_MCU_DEVICE
 
+/* Enable MKBP for buttons and switches */
+#define EC_ENABLE_MKBP_DEVICE
+
 #define SIO_EC_MEMMAP_ENABLE	/* EC Memory Map Resources */
 #define SIO_EC_HOST_ENABLE	/* EC Host Interface Resources */
 #define SIO_EC_ENABLE_PS2K	/* Enable PS/2 Keyboard */

From ed261d5447c53b76f4501e04d99dd79ac5b8623c Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Wed, 25 Mar 2026 20:05:15 +0000
Subject: [PATCH 3824/3886] mainboard/starlabs/common: include acpi_gnvs.h in
 gnvs.c

gnvs.c uses the global NVS definitions directly, so include
acpi/acpi_gnvs.h explicitly instead of relying on indirect headers.

Change-Id: Ifd19111a01ced3cb9bdb85ac192358e823dd3f44
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91857
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/starlabs/common/gnvs.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/src/mainboard/starlabs/common/gnvs.c b/src/mainboard/starlabs/common/gnvs.c
index b95bf314ad..1fe0b8c85c 100644
--- a/src/mainboard/starlabs/common/gnvs.c
+++ b/src/mainboard/starlabs/common/gnvs.c
@@ -1,5 +1,6 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
+#include <acpi/acpi_gnvs.h>
 #include <stddef.h>
 
 #include <starlabs/efi_option_smi.h>

From 040ff1ff39505c03346a7db0f9c014180195c693 Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Wed, 25 Mar 2026 20:06:28 +0000
Subject: [PATCH 3825/3886] mb/starlabs/adl/hz: fix panel timing values against
 datasheet

Fix the HZ panel VBT timing values against the panel datasheet for
panel entry 03.

eDP_DataOn_To_BkltEnable_Delay_03 changes from 10 to 800.
eDP_BkltDisable_To_DataOff_Delay_03 changes from 2000 to 500.
eDP_DataOff_To_PowerOff_Delay_03 changes from 500 to 5000.

Change-Id: Icc711c3c6f105cfd6fc1dc5bbab24d9b172a924f
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91860
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 .../starlabs/adl/variants/hz/data.vbt         | Bin 9216 -> 9216 bytes
 1 file changed, 0 insertions(+), 0 deletions(-)

diff --git a/src/mainboard/starlabs/adl/variants/hz/data.vbt b/src/mainboard/starlabs/adl/variants/hz/data.vbt
index a101af780b8ecc78fff9335c3dc0cab7239b2250..4e34f727e86d9b856cb92b92d63c74c4bd2ec756 100644
GIT binary patch
delta 30
mcmZqhXz-XI#XOb4U~(a&@J54bRyGCZFN__+n>Vuh%K-q7ObH7B

delta 31
ncmZqhXz-XI#azT-Fu9OXc%wlz>*W2cWs~2tiflGzJ1q+Uq<RXM


From f1bc59e66e41c9b2384c784f27e067ca778692df Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Wed, 25 Mar 2026 20:06:38 +0000
Subject: [PATCH 3826/3886] mb/starlabs/starfighter: fix panel timing values
 against datasheet

Fix the StarFighter panel VBT timing values against the panel datasheets for panel entry 03.

eDP_DataOn_To_BkltEnable_Delay_03 changes from 10 to 500.
eDP_BkltDisable_To_DataOff_Delay_03 changes from 2000 to 500.
eDP_DataOff_To_PowerOff_Delay_03 changes from 500 to 5000.

Change-Id: I382a1609aa7fee082b172ed07c761a7655a56dd3
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91861
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
---
 .../starfighter/variants/mtl/data.vbt         | Bin 7680 -> 7680 bytes
 .../starfighter/variants/rpl/data.vbt         | Bin 9216 -> 9216 bytes
 2 files changed, 0 insertions(+), 0 deletions(-)

diff --git a/src/mainboard/starlabs/starfighter/variants/mtl/data.vbt b/src/mainboard/starlabs/starfighter/variants/mtl/data.vbt
index cd70aad5d9189f370421e197dac094e155763603..511c79c61c12a64955f7190d4fc29e166b8323a6 100644
GIT binary patch
delta 38
ucmZp$X|S0f#e9XqU~(a&@J54lR<<vUUl==tCvRkJnf#trWV0#TX>kDjc@0tk

delta 31
ncmZp$X|S0f#oWwbFu9OXc%wl&>*UL<Nt55R+H5vuJ1q_Xqd*Ft

diff --git a/src/mainboard/starlabs/starfighter/variants/rpl/data.vbt b/src/mainboard/starlabs/starfighter/variants/rpl/data.vbt
index b0222677f63a502e639ba65c929273bee5409d70..eeb97ae9e84304813089da74bd74e9a7f914507e 100644
GIT binary patch
delta 38
ucmZqhXz-XI#T?9FFu9OXc%wlqE87>wFN__+lQ*(fO`gvxw^^I*sw@EPs0@_=

delta 35
pcmZqhXz-XI#mvNDFu9OXc%wlq>*UL<5tHAu+5j=vW^J~svH-^(3%CFP


From d0e2b5df61b4ea9cb611be7be0d627b168629c0f Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Wed, 25 Mar 2026 20:06:48 +0000
Subject: [PATCH 3827/3886] mb/starlabs/starbook/{adl_n,mtl}: fix panel timings

Fix the StarBook 14-inch 4K panel VBT timing values against the panel
datasheet for panel entry 03.

eDP_DataOn_To_BkltEnable_Delay_03 changes from 10 to 500.
eDP_BkltDisable_To_DataOff_Delay_03 changes from 2000 to 500.
eDP_DataOff_To_PowerOff_Delay_03 changes from 500 to 4500.

Change-Id: I941e268f6a05f74248b19eb75fc7f07f781e347c
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91862
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 .../starlabs/starbook/variants/adl_n/data.vbt | Bin 9216 -> 9216 bytes
 .../starlabs/starbook/variants/mtl/data.vbt   | Bin 7680 -> 7680 bytes
 2 files changed, 0 insertions(+), 0 deletions(-)

diff --git a/src/mainboard/starlabs/starbook/variants/adl_n/data.vbt b/src/mainboard/starlabs/starbook/variants/adl_n/data.vbt
index 0cd0ec4b7773a3710b525f434dbf9050e4800bb7..97350be6de5b65fd8be30c8820c1cd1a936f3851 100644
GIT binary patch
delta 38
ucmZqhXz-XI#eAB<U~(d(@J53|R<<vUUl^wdPTt5`HF-WO*Jf?DtFi$5SPcgN

delta 31
ncmZqhXz-XI#oWSRFgcM?c%wlf>*W2cIg{VB%5BzWyDAF+q!<d1

diff --git a/src/mainboard/starlabs/starbook/variants/mtl/data.vbt b/src/mainboard/starlabs/starbook/variants/mtl/data.vbt
index f855dabf240a70571e2c1c25eeae7efd490739cf..e7e17746904b02097a95c627e1c084aacf159965 100644
GIT binary patch
delta 30
mcmZp$X|S0f#q7jjFu9OXc%wlzE87>wFN{+JH*aM1mjD2cfeCg1

delta 31
ncmZp$X|S0f#r&JWU~(a&@J54b*2()>%O<~P71?acc3K<&u9OP`


From f13a9cb9105e01955167531e9ab1b38865edce64 Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Wed, 25 Mar 2026 20:06:59 +0000
Subject: [PATCH 3828/3886] mb/starlabs/adl/i5: fix panel timing values against
 datasheet

Fix the i5 panel VBT timing values against the panel datasheet for panel entry 03.

eDP_DataOn_To_BkltEnable_Delay_03 changes from 10 to 2000.

eDP_BkltDisable_To_DataOff_Delay_03 changes from 2000 to 500.

eDP_DataOff_To_PowerOff_Delay_03 changes from 500 to 4500.

Change-Id: I717be5863d0352224eae1053db77e8d3234a396f
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91863
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
---
 .../starlabs/adl/variants/i5/data.vbt         | Bin 9216 -> 9216 bytes
 1 file changed, 0 insertions(+), 0 deletions(-)

diff --git a/src/mainboard/starlabs/adl/variants/i5/data.vbt b/src/mainboard/starlabs/adl/variants/i5/data.vbt
index 13c5b92d61f599b4168691619efc28a28e05e7f4..4b8bf99626d6d4f318d4b9fd7777c6d46f56035d 100644
GIT binary patch
delta 34
qcmZqhXz-XI#r&MXU~(a&@J54HR<;Z5Ul^wdPTt5`wb_*Iv@8J4E(_=Y

delta 35
pcmZqhXz-XI#oWYTFu9OXc%wlp>tud5waM>U-GEqRvnktYSpdo13x5Cr


From 9f6ae2b5a27d3aa3020c4ab239e97d58a923e5b9 Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Wed, 25 Mar 2026 20:07:09 +0000
Subject: [PATCH 3829/3886] mb/starlabs/starbook/{adl,rpl,tgl}: fix panel
 timings

Fix the StarBook 14-inch 1080p panel VBT timing values against the
panel datasheet for panel entry 03.

eDP_DataOn_To_BkltEnable_Delay_03 changes from 10 to 800.
eDP_BkltDisable_To_DataOff_Delay_03 changes from 2000 to 500.
eDP_DataOff_To_PowerOff_Delay_03 changes from 500 to 5000.

Change-Id: Ie153c6272595268565e1966b7d7773d4d068680c
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91864
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 .../starlabs/starbook/variants/adl/data.vbt   | Bin 8704 -> 8704 bytes
 .../starlabs/starbook/variants/rpl/data.vbt   | Bin 9216 -> 9216 bytes
 .../starlabs/starbook/variants/tgl/data.vbt   | Bin 8704 -> 8704 bytes
 3 files changed, 0 insertions(+), 0 deletions(-)

diff --git a/src/mainboard/starlabs/starbook/variants/adl/data.vbt b/src/mainboard/starlabs/starbook/variants/adl/data.vbt
index 711e5311d306afdd0daa636ef0f8ad2c607ae226..b65242f8fd35c6a0c498ce975a63204904dd68d2 100644
GIT binary patch
delta 38
ucmZp0X>ge!#hl4tFgcM?c%wlsE1LrI7sd|Z$p=}}Ca-6e+pNxZQyKu?xC`3=

delta 35
pcmZp0X>ge!#q7plFgcM?c%wls>*VvS5tIM3Y5+0UW_7lk(g4k53;F;6

diff --git a/src/mainboard/starlabs/starbook/variants/rpl/data.vbt b/src/mainboard/starlabs/starbook/variants/rpl/data.vbt
index 32a044ccf76a1983a4ad1e4909487aef4bccb312..5f84717c7c4d0e562e319ba40b81a5b33accc45e 100644
GIT binary patch
delta 38
ucmZqhXz-XI#hk=oFgcM?c%wlfE1LrI7sd|Z$s1X#CeLT(+N{lXRTco=aSOr#

delta 31
ncmZqhXz-XI#ca=DFgcM?c%wlf>*W2cIg{VB%5BzWyDAF+ouCRz

diff --git a/src/mainboard/starlabs/starbook/variants/tgl/data.vbt b/src/mainboard/starlabs/starbook/variants/tgl/data.vbt
index ca57e717f303b0d00a9038814afb2d62b2f74fd4..bbb60e9d5e84e03abbf23b18631cc6a3948a6b80 100644
GIT binary patch
delta 30
lcmZp0X>ge!#car6FgcM?c%y+AE1LrI7sd|Z%?+##G5~=t2wVUF

delta 31
ncmZp0X>ge!#mvWGFgcM?c%y+A>*NEhE|V9qx@~4*`y&kil6wi7


From e970b9b0df77816f78c2bf4738baf46a3ee59fc9 Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Wed, 25 Mar 2026 20:07:19 +0000
Subject: [PATCH 3830/3886] mb/starlabs/adl/hz: restore panel minimum
 brightness

Restore the HZ panel VBT minimum brightness for panel entry 03 to the reference value.

Post_Min_Brightness_03 changes from 0 to 25.

Change-Id: I04ae425a1377b4a716127a0624872b74fb3eb962
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91865
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
---
 .../starlabs/adl/variants/hz/data.vbt         | Bin 9216 -> 9216 bytes
 1 file changed, 0 insertions(+), 0 deletions(-)

diff --git a/src/mainboard/starlabs/adl/variants/hz/data.vbt b/src/mainboard/starlabs/adl/variants/hz/data.vbt
index 4e34f727e86d9b856cb92b92d63c74c4bd2ec756..e60bb4e29fe172e32184f1b803c72dfaecc09b97 100644
GIT binary patch
delta 25
gcmZqhXz-XI#azQ+Fu9OXc%#8xK1RvSeEgq80A{xbz5oCK

delta 25
hcmZqhXz-XI#XOb4U~(a&@J55Xe2fg6`S?GH003v>2fhFR


From 1ca1c60019b37c552d99fee8b557d67d940b765b Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Wed, 25 Mar 2026 20:07:29 +0000
Subject: [PATCH 3831/3886] mb/starlabs/adl/hz: raise panel PWM frequency to
 10kHz

PWM_Frequency_03 changes from 200Hz to 10kHz.

The HZ panel is validated at 10kHz, so use that known-good value in
the board VBT instead of the old 200Hz default.

Change-Id: Ieaddba9a7fef42be8de2cc64f234a39dde62c25f
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91866
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
---
 .../starlabs/adl/variants/hz/data.vbt         | Bin 9216 -> 9216 bytes
 1 file changed, 0 insertions(+), 0 deletions(-)

diff --git a/src/mainboard/starlabs/adl/variants/hz/data.vbt b/src/mainboard/starlabs/adl/variants/hz/data.vbt
index e60bb4e29fe172e32184f1b803c72dfaecc09b97..f62deff97a0ada9e212edee396b171f8a1f36fe6 100644
GIT binary patch
delta 34
qcmZqhXz-XI#mviKFu9OXc%y+5ACrLk<ODv~$@zRdo0sxMivj?iYY7zq

delta 31
ncmZqhXz-XI#azQ+Fu9OXc%y+5-{d|%@yYpoW}D~pC5i$7nE?rP


From d4bfac65641003816e32e2de80cc89b4af6472e9 Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Wed, 25 Mar 2026 20:07:39 +0000
Subject: [PATCH 3832/3886] mb/starlabs/adl/i5: use safe shared panel PWM
 frequency

PWM_Frequency_03 changes from 200Hz to 10kHz.

The 12.5-inch 2K panel supports 100Hz to 10kHz, while the 12.5-inch
3K panel supports 200Hz to 25kHz. Keep the shared board VBT at 10kHz
until panel-specific selection exists.

Change-Id: Ia8bf5a324eb65698a8ba89b89cee8a9d10fba07d
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91867
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 .../starlabs/adl/variants/i5/data.vbt         | Bin 9216 -> 9216 bytes
 1 file changed, 0 insertions(+), 0 deletions(-)

diff --git a/src/mainboard/starlabs/adl/variants/i5/data.vbt b/src/mainboard/starlabs/adl/variants/i5/data.vbt
index 4b8bf99626d6d4f318d4b9fd7777c6d46f56035d..fd5596cac5cfad35ab4adf13df8dc90aab55e613 100644
GIT binary patch
delta 34
qcmZqhXz-XI#azK)Fu9OXc%y+5ACrLk<ODv~$@zRdo0sxMivj?tv<ZL!

delta 31
ncmZqhXz-XI#r&MXU~(a&@J0hAzR7)j;*<0F%r?*GOB4kFqX`M%


From bfaadde071cdc858adbfb493ec5da7160dc1ace6 Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Wed, 25 Mar 2026 20:07:49 +0000
Subject: [PATCH 3833/3886] mb/starlabs/starbook/{adl_n,mtl}: raise panel PWM
 frequency

PWM_Frequency_03 changes from 200Hz to 10kHz.

The 14-inch 4K panel supports 100Hz to 10kHz, so raise the board VBT
value to the panel's safe maximum.

Change-Id: I94694d06e09d58f92966a2c827aad52f15e1e4c6
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91868
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 .../starlabs/starbook/variants/adl_n/data.vbt | Bin 9216 -> 9216 bytes
 .../starlabs/starbook/variants/mtl/data.vbt   | Bin 7680 -> 7680 bytes
 2 files changed, 0 insertions(+), 0 deletions(-)

diff --git a/src/mainboard/starlabs/starbook/variants/adl_n/data.vbt b/src/mainboard/starlabs/starbook/variants/adl_n/data.vbt
index 97350be6de5b65fd8be30c8820c1cd1a936f3851..9e028cbe75d50582f4f3b90c5577342f5c0413da 100644
GIT binary patch
delta 34
qcmZqhXz-XI#T>(6FgcM?c%y*?ACrLk<N!YJ$?<$_n`iT-iUI(mU<oP!

delta 31
ncmZqhXz-XI#eAB<U~(d(@J0g(zR7ibvXkTa%r?*FOBDqGorejK

diff --git a/src/mainboard/starlabs/starbook/variants/mtl/data.vbt b/src/mainboard/starlabs/starbook/variants/mtl/data.vbt
index e7e17746904b02097a95c627e1c084aacf159965..6018e334b5446c9cdb32538bb11e725f94cc1f27 100644
GIT binary patch
delta 34
qcmZp$X|S0f#eA8;U~(a&@J0hSJ|+S6$rJc2C(q}T*nE=DoF4$TrwTy;

delta 31
ncmZp$X|S0f#q7jjFu9OXc%y+E-{d|%>&f%^BsQPqGv@~Ym3Iku


From 25eee46bbc71fc565b91c28dc31bcb2fa104ed65 Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Wed, 25 Mar 2026 20:07:59 +0000
Subject: [PATCH 3834/3886] mb/starlabs/starbook/{adl,rpl,tgl}: raise panel PWM
 frequency

PWM_Frequency_03 changes from 200Hz to 2kHz.

The 14-inch 1080p panel supports 190Hz to 2kHz, so use the panel's
safe maximum instead of the old 200Hz default.

Change-Id: Ibf21bf291fecfd2b10a74bb3667549ef2f271356
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91869
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
---
 .../starlabs/starbook/variants/adl/data.vbt   | Bin 8704 -> 8704 bytes
 .../starlabs/starbook/variants/rpl/data.vbt   | Bin 9216 -> 9216 bytes
 .../starlabs/starbook/variants/tgl/data.vbt   | Bin 8704 -> 8704 bytes
 3 files changed, 0 insertions(+), 0 deletions(-)

diff --git a/src/mainboard/starlabs/starbook/variants/adl/data.vbt b/src/mainboard/starlabs/starbook/variants/adl/data.vbt
index b65242f8fd35c6a0c498ce975a63204904dd68d2..fe19a320f779adec644c976fc19bb30196c041b8 100644
GIT binary patch
delta 34
qcmZp0X>ge!#T><8FgcM?c%y+3AJYZ)$pL(>ljHe#Hc#ct76t&T7zwxl

delta 31
mcmZp0X>ge!#hl4tFgcM?c%y+3-{d+z@yYRgW}Ex@3WWiZzX=!s

diff --git a/src/mainboard/starlabs/starbook/variants/rpl/data.vbt b/src/mainboard/starlabs/starbook/variants/rpl/data.vbt
index 5f84717c7c4d0e562e319ba40b81a5b33accc45e..8b3f851aa4846ce771aacbddccac8b7a967cf281 100644
GIT binary patch
delta 34
qcmZqhXz-XI#T?9FFgcM?c%y*?AJYZ)$pL)cljHf=HqYiu6$JpR?FqpE

delta 31
ncmZqhXz-XI#hk=oFgcM?c%y*?-{d+z*~#&IW}9d8rHTRoldlOU

diff --git a/src/mainboard/starlabs/starbook/variants/tgl/data.vbt b/src/mainboard/starlabs/starbook/variants/tgl/data.vbt
index bbb60e9d5e84e03abbf23b18631cc6a3948a6b80..0efa421a97f116786c9785552bbca7c958e7e9bd 100644
GIT binary patch
delta 26
icmZp0X>ge!#jM0&FgcM?c%#94UZxA|n-%%)3j+XZK?oWE

delta 31
ncmZp0X>ge!#car6FgcM?c%#94-pRInrjrf$<Te-a^$7z2mO=?q


From 26d005fb305e95004888ff6056d5c730802edfad Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Wed, 25 Mar 2026 20:08:09 +0000
Subject: [PATCH 3835/3886] mb/starlabs/starfighter: use safe shared panel PWM
 frequency

PWM_Frequency_03 changes from 200Hz to 2kHz.

The 16-inch QHD panel supports 200Hz to 2kHz, while the 16-inch 4K
panel supports 200Hz to 10kHz. Keep the shared board VBT at 2kHz for
now; the higher 10kHz value only applies to the 4K panel.

Change-Id: If5a6d1ea248132219f8c0115771fb26d9d5b228a
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91870
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 .../starfighter/variants/mtl/data.vbt         | Bin 7680 -> 7680 bytes
 .../starfighter/variants/rpl/data.vbt         | Bin 9216 -> 9216 bytes
 2 files changed, 0 insertions(+), 0 deletions(-)

diff --git a/src/mainboard/starlabs/starfighter/variants/mtl/data.vbt b/src/mainboard/starlabs/starfighter/variants/mtl/data.vbt
index 511c79c61c12a64955f7190d4fc29e166b8323a6..9eba8d21756f6f7b9051ff10c93c284e6c8270c0 100644
GIT binary patch
delta 34
qcmZp$X|S0f#e9^(U~(a&@J0hSKBf!olPB<5PM*&vvH2vQIX?ittqRis

delta 31
ncmZp$X|S0f#e9XqU~(a&@J0hSzR7)j)|2P+No+pJXU-1*qbCXp

diff --git a/src/mainboard/starlabs/starfighter/variants/rpl/data.vbt b/src/mainboard/starlabs/starfighter/variants/rpl/data.vbt
index eeb97ae9e84304813089da74bd74e9a7f914507e..eb78a25095df418e7d9da059eaa34371000e7b1a 100644
GIT binary patch
delta 34
qcmZqhXz-XI#q7dhFu9OXc%y*?AJYZ)$pL)cljHf=HqYiu6$JpR$O*y#

delta 31
ncmZqhXz-XI#T?9FFu9OXc%y*?-{d+z*~#&IW}9d8rHTRolZOc?


From 7609822730a2f3ffd80505eeb21030db1adf5ce7 Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Wed, 25 Mar 2026 20:08:19 +0000
Subject: [PATCH 3836/3886] mb/starlabs/*: disable TCO Intruder SMI

Some Star Labs boards can continuously trigger the TCO intruder SMI.
Default the common Kconfig symbol off to avoid those spurious events.

Change-Id: I4fbdc3d0f43d814564e972afcaaac1e967fb49f8
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91871
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
---
 src/mainboard/starlabs/common/Kconfig | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/src/mainboard/starlabs/common/Kconfig b/src/mainboard/starlabs/common/Kconfig
index 5501d43efe..9fe452d246 100644
--- a/src/mainboard/starlabs/common/Kconfig
+++ b/src/mainboard/starlabs/common/Kconfig
@@ -48,6 +48,9 @@ config STARLABS_ACPI_EFI_OPTION_SMI
 	  (e.g. keyboard backlight and trackpad state) to the UEFI variable
 	  store via an SMM APMC SMI handler.
 
+config SOC_INTEL_COMMON_BLOCK_SMM_TCO_INTRUDER_SMI_ENABLE
+	default n
+
 source "src/mainboard/starlabs/common/hda/Kconfig"
 
 endmenu

From cf541343a9e6a300a5dfa9197c1355cd76a99533 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Christian=20Schr=C3=B6tter?= <cs@fnx.li>
Date: Tue, 24 Mar 2026 17:18:03 +0100
Subject: [PATCH 3837/3886] ec/lenovo/h8: Implement LOGO LED
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Implement the red i-dot LED in the ThinkPad logo at the display lid.
On warm reboot the LOGO LED isn't automatically turned on by the EC.
Turn it on in the ramstage code, which allows to see when the reboot
has happened. (Similar to PWR LED; see change ID 88998)

Further testing on other devices running H8 EC is required!

TEST=LOGO LED is on after warm reboot on Lenovo T440p.

Reference: https://ch1p.io/t440p-leds-control-linux/#list-of-leds
Related: https://review.coreboot.org/c/coreboot/+/88998
Change-Id: I2ebba5a4c1ffc38f0c2e1b24793e4a252cc171bd
Signed-off-by: Christian Schrötter <cs@fnx.li>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91837
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/ec/lenovo/h8/h8.c    | 1 +
 src/ec/lenovo/h8/h8.h    | 3 ++-
 src/ec/lenovo/h8/panic.c | 1 +
 3 files changed, 4 insertions(+), 1 deletion(-)

diff --git a/src/ec/lenovo/h8/h8.c b/src/ec/lenovo/h8/h8.c
index 1ea3ccfa40..aeaceb2415 100644
--- a/src/ec/lenovo/h8/h8.c
+++ b/src/ec/lenovo/h8/h8.c
@@ -268,6 +268,7 @@ static void h8_enable(struct device *dev)
 	 * (Without this warm reboot leaves LEDs off)
 	 */
 	ec_write(H8_LED_CONTROL, H8_LED_CONTROL_ON | H8_LED_CONTROL_POWER_LED);
+	ec_write(H8_LED_CONTROL, H8_LED_CONTROL_ON | H8_LED_CONTROL_LOGO_LED);
 
 	beepmask0 = conf->beepmask0;
 	beepmask1 = conf->beepmask1;
diff --git a/src/ec/lenovo/h8/h8.h b/src/ec/lenovo/h8/h8.h
index 88d7b07136..064f8915b8 100644
--- a/src/ec/lenovo/h8/h8.h
+++ b/src/ec/lenovo/h8/h8.h
@@ -70,7 +70,7 @@ void h8_mb_init(void);
 #define H8_LED_CONTROL			0x0c
 #define H8_LED_CONTROL_OFF		0x00
 #define H8_LED_CONTROL_ON		0x80
-#define H8_LED_CONTROL_PULSE		0xa0	/* Some models, power LED only*/
+#define H8_LED_CONTROL_PULSE		0xa0	/* Some models, power LED and logo LED only*/
 #define H8_LED_CONTROL_BLINK		0xc0
 
 #define H8_LED_CONTROL_POWER_LED	0x00
@@ -80,6 +80,7 @@ void h8_mb_init(void);
 #define H8_LED_CONTROL_SUSPEND_LED	0x07
 #define H8_LED_CONTROL_DOCK_LED1	0x08
 #define H8_LED_CONTROL_DOCK_LED2	0x09
+#define H8_LED_CONTROL_LOGO_LED		0x0a	/* red i-dot LED in ThinkPad logo (display lid) */
 #define H8_LED_CONTROL_ACDC_LED		0x0c
 #define H8_LED_CONTROL_MUTE_LED		0x0e
 
diff --git a/src/ec/lenovo/h8/panic.c b/src/ec/lenovo/h8/panic.c
index 1bd8d1b162..f85462e148 100644
--- a/src/ec/lenovo/h8/panic.c
+++ b/src/ec/lenovo/h8/panic.c
@@ -15,6 +15,7 @@ static void h8_panic(void)
 			H8_LED_CONTROL_SUSPEND_LED,
 			H8_LED_CONTROL_DOCK_LED1,
 			H8_LED_CONTROL_DOCK_LED2,
+			H8_LED_CONTROL_LOGO_LED,
 			H8_LED_CONTROL_ACDC_LED,
 			H8_LED_CONTROL_MUTE_LED
 		};

From 492b7c7c098623d96e2882fdee0d349178cfc6f1 Mon Sep 17 00:00:00 2001
From: Zheng Bao <fishbaozi@gmail.com>
Date: Tue, 14 Jan 2025 22:04:52 +0800
Subject: [PATCH 3838/3886] soc/amd/common/block/psp: Add commands for A/B
 recovery

PSP supports A/B updates of the PSP directory structure. This
is unrelated to VBOOT's A/B update scheme. At boot the PSP
structures of partition A are verified. If A is found corrupted
partition B will used to read in the PSP files. x86 software can
then fix the A partition and switch back to the A partition.

Add functions to get, set and toggle the active boot partition used
on the next boot.

Change-Id: Ia7f2eedae5b277745cb34a0761bd1a8b61441695
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85650
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
---
 src/soc/amd/common/block/psp/psp_def.h  | 30 ++++++++++++++++
 src/soc/amd/common/block/psp/psp_gen2.c | 48 +++++++++++++++++++++++++
 2 files changed, 78 insertions(+)

diff --git a/src/soc/amd/common/block/psp/psp_def.h b/src/soc/amd/common/block/psp/psp_def.h
index c1513337cf..e20627e650 100644
--- a/src/soc/amd/common/block/psp/psp_def.h
+++ b/src/soc/amd/common/block/psp/psp_def.h
@@ -29,6 +29,8 @@
 #define MBOX_BIOS_CMD_HSTI_QUERY		0x14
 #define  HSTI_STATE_ROM_ARMOR_ENFORCED		BIT(11)
 #define MBOX_BIOS_CMD_PSB_AUTO_FUSING		0x21
+#define MBOX_BIOS_CMD_SET_BOOTPARTITION		0x26
+#define MBOX_BIOS_CMD_GET_BOOTPARTITION		0x36
 #define MBOX_BIOS_CMD_PSP_CAPS_QUERY		0x27
 #define MBOX_BIOS_CMD_SET_SPL_FUSE		0x2d
 #define MBOX_BIOS_CMD_SET_RPMC_ADDRESS		0x39
@@ -115,6 +117,17 @@ struct mbox_cmd_late_spl_buffer {
 	uint32_t	spl_value;
 } __packed __aligned(32);
 
+/*
+ * MBOX_BIOS_CMD_SET_BOOTPARTITION,
+ * MBOX_BIOS_CMD_GET_BOOTPARTITION
+ *
+ * boot_partition is typically 0 or 1.
+ */
+struct mbox_cmd_boot_partition_buffer {
+	struct mbox_buffer_header header;
+	uint32_t	boot_partition;
+} __packed __aligned(32);
+
 struct dtpm_config {
 	uint32_t gpio;
 } __packed;
@@ -179,4 +192,21 @@ void enable_psp_smi(void);
 void psp_set_smm_flag(void);
 void psp_clear_smm_flag(void);
 
+/* psp_ab_recovery_set_bootpartition - Set active partition on next boot.
+ * @param partition: Active partition on next boot. 0: A, 1: B.
+ * @return 0 on success
+ */
+int psp_ab_recovery_set_bootpartition(const uint32_t partition);
+
+/* psp_ab_recovery_get_bootpartition - Get active partition on next boot.
+ * @return negative on failure. 0 if A is active boot partition, 1 if B is active
+ *         boot partition.
+ */
+int psp_ab_recovery_get_bootpartition(void);
+
+/* psp_ab_recovery_toggle_bootpartition - Toggle active partition on next boot.
+ * @return 0 on success
+ */
+int psp_ab_recovery_toggle_bootpartition(void);
+
 #endif /* __AMD_PSP_DEF_H__ */
diff --git a/src/soc/amd/common/block/psp/psp_gen2.c b/src/soc/amd/common/block/psp/psp_gen2.c
index b3cb6ef8ed..10784acfc7 100644
--- a/src/soc/amd/common/block/psp/psp_gen2.c
+++ b/src/soc/amd/common/block/psp/psp_gen2.c
@@ -223,3 +223,51 @@ enum cb_err soc_read_c2p38(uint32_t *msg_38_value)
 	*msg_38_value = read32p(psp_mmio | CORE_2_PSP_MSG_38_OFFSET);
 	return CB_SUCCESS;
 }
+
+int psp_ab_recovery_set_bootpartition(const uint32_t partition)
+{
+	struct mbox_cmd_boot_partition_buffer  boot_partition_cmd = {
+		.header = {
+			.size = sizeof(boot_partition_cmd)
+		},
+		.boot_partition = partition,
+	};
+	int cmd_status;
+
+	cmd_status = send_psp_command(MBOX_BIOS_CMD_SET_BOOTPARTITION, &boot_partition_cmd);
+
+	/* buffer's status shouldn't change but report it if it does */
+	psp_print_cmd_status(cmd_status, &boot_partition_cmd.header);
+
+	return cmd_status;
+}
+
+int psp_ab_recovery_get_bootpartition(void)
+{
+	struct mbox_cmd_boot_partition_buffer  boot_partition_cmd = {
+		.header = {
+			.size = sizeof(boot_partition_cmd)
+		},
+		.boot_partition = 0xFFFFFFFF,
+	};
+	int cmd_status;
+
+	cmd_status = send_psp_command(MBOX_BIOS_CMD_GET_BOOTPARTITION, &boot_partition_cmd);
+
+	/* buffer's status shouldn't change but report it if it does */
+	psp_print_cmd_status(cmd_status, &boot_partition_cmd.header);
+
+	if (cmd_status < 0)
+		return cmd_status;
+
+	return boot_partition_cmd.boot_partition;
+}
+
+int psp_ab_recovery_toggle_bootpartition(void)
+{
+	int cmd_status = psp_ab_recovery_get_bootpartition();
+	if (cmd_status < 0)
+		return cmd_status;
+
+	return psp_ab_recovery_set_bootpartition(cmd_status ? 0 : 1);
+}

From e57478e23804c7414ec3027b1b2b0e65c8da7bb5 Mon Sep 17 00:00:00 2001
From: Felix Singer <felixsinger@posteo.net>
Date: Sun, 28 Dec 2025 18:20:31 +0100
Subject: [PATCH 3839/3886] treewide: Apply nonstring attribute to unterminated
 strings

Applying the attribute silences the following error and allows
compilation with GCC 15.2.

  error: initializer-string for array of 'char' truncates NUL terminator but destination lacks 'nonstring' attribute

Change-Id: I33cf3219f34e297de03f67d3e73058b10930c9f8
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90631
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
---
 src/commonlib/bsd/include/commonlib/bsd/metadata_hash.h | 2 +-
 src/commonlib/include/commonlib/coreboot_tables.h       | 2 +-
 src/include/cpu/intel/smm_reloc.h                       | 2 +-
 src/include/edid.h                                      | 4 ++--
 src/northbridge/intel/gm45/gm45.h                       | 2 +-
 5 files changed, 6 insertions(+), 6 deletions(-)

diff --git a/src/commonlib/bsd/include/commonlib/bsd/metadata_hash.h b/src/commonlib/bsd/include/commonlib/bsd/metadata_hash.h
index d5e54b508e..f73700ec02 100644
--- a/src/commonlib/bsd/include/commonlib/bsd/metadata_hash.h
+++ b/src/commonlib/bsd/include/commonlib/bsd/metadata_hash.h
@@ -8,7 +8,7 @@
 
 /* This structure is embedded somewhere in the (uncompressed) bootblock. */
 struct metadata_hash_anchor {
-	uint8_t magic[8];
+	uint8_t __nonstring magic[8];
 	struct vb2_hash cbfs_hash;
 	/* NOTE: This is just reserving space. sizeof(struct vb2_hash) may change between
 	   configurations/versions and cannot be relied upon, so the FMAP hash must be placed
diff --git a/src/commonlib/include/commonlib/coreboot_tables.h b/src/commonlib/include/commonlib/coreboot_tables.h
index 87da127ef9..70c9f17209 100644
--- a/src/commonlib/include/commonlib/coreboot_tables.h
+++ b/src/commonlib/include/commonlib/coreboot_tables.h
@@ -321,7 +321,7 @@ struct lb_gpio {
 #define ACTIVE_HIGH	1
 	uint32_t value;
 #define GPIO_MAX_NAME_LENGTH 16
-	uint8_t name[GPIO_MAX_NAME_LENGTH];
+	uint8_t __nonstring name[GPIO_MAX_NAME_LENGTH];
 };
 
 struct lb_gpios {
diff --git a/src/include/cpu/intel/smm_reloc.h b/src/include/cpu/intel/smm_reloc.h
index 2b25c75705..f3fc4d29e8 100644
--- a/src/include/cpu/intel/smm_reloc.h
+++ b/src/include/cpu/intel/smm_reloc.h
@@ -28,7 +28,7 @@ struct smm_relocation_params {
 extern struct smm_relocation_params smm_reloc_params;
 
 struct ied_header {
-	char signature[10];
+	char __nonstring signature[10];
 	u32 size;
 	u8 reserved[34];
 } __packed;
diff --git a/src/include/edid.h b/src/include/edid.h
index b2d6aa2cab..cd8df7e3ed 100644
--- a/src/include/edid.h
+++ b/src/include/edid.h
@@ -82,8 +82,8 @@ struct edid {
 	u32 bytes_per_line;
 
 	int hdmi_monitor_detected;
-	char ascii_string[EDID_ASCII_STRING_LENGTH + 1];
-	char manufacturer_name[3 + 1];
+	char __nonstring ascii_string[EDID_ASCII_STRING_LENGTH + 1];
+	char __nonstring manufacturer_name[3 + 1];
 };
 
 enum edid_status {
diff --git a/src/northbridge/intel/gm45/gm45.h b/src/northbridge/intel/gm45/gm45.h
index f68bfdee7a..90ab570524 100644
--- a/src/northbridge/intel/gm45/gm45.h
+++ b/src/northbridge/intel/gm45/gm45.h
@@ -441,7 +441,7 @@ void mb_pre_raminit_setup(sysinfo_t *); /* optional */
 void mb_post_raminit_setup(void); /* optional */
 
 struct blc_pwm_t {
-	char ascii_string[13];
+	char __nonstring ascii_string[13];
 	int pwm_freq; /* In Hz */
 };
 int get_blc_values(const struct blc_pwm_t **entries);

From 36a4d922396eccfb0748b44524517c7516056e75 Mon Sep 17 00:00:00 2001
From: Patrick Rudolph <patrick.rudolph@9elements.com>
Date: Mon, 23 Mar 2026 12:04:24 +0100
Subject: [PATCH 3840/3886] util/amdfwtool: Fix APOB_NV quirk

Fixes commit "util/amdfwtool: Move APOB_NV quirk to amdfwtool.c".
Allow the AMD_BIOS_NV_ST and AMD_BIOS_APOB_NV to end at 16MiB.

Fixes a build failure when the region is last in the FMAP.

Change-Id: Icfa5b74e98223ff5864299d4e9a2d23606935b80
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91820
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 util/amdfwtool/amdfwtool.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/util/amdfwtool/amdfwtool.c b/util/amdfwtool/amdfwtool.c
index 4e0901cb7d..fa6382c553 100644
--- a/util/amdfwtool/amdfwtool.c
+++ b/util/amdfwtool/amdfwtool.c
@@ -1484,7 +1484,7 @@ static void integrate_bios_firmwares(context *ctx,
 				 * using an MMIO address is then not as simply as adding
 				 * the SPI_ROM_BASE offset anymore.
 				 */
-				if (fw_table[i].src + fw_table[i].size >= 16*MiB) {
+				if (fw_table[i].src + fw_table[i].size > 16*MiB) {
 					fprintf(stderr,
 						"APOB_NV location too high (0x%lx + 0x%lx)\n",
 						fw_table[i].src, fw_table[i].size);

From 468f8131ec7220689427d44aacd8db895a8cbdef Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Sun, 1 Feb 2026 21:46:56 +0000
Subject: [PATCH 3841/3886] security/tcg/opal_s3: hook into default SMI/resume
 paths

Provide common entry points for the OPAL S3 unlock feature and wire them
into the generic x86 SMM and S3 resume code.

- Add opal_s3_smi_{apmc,sleep,sleep_finalize} helpers.
- Call these helpers from the default weak mainboard SMI hooks when
  CONFIG(TCG_OPAL_S3_UNLOCK) is enabled. This keeps the feature usable
  without forcing boards to implement new SMI handlers.
- Trigger the SMM unlock on S3 resume from arch/x86/acpi_s3.c.

Select SMM_OPAL_S3_STATE_SMRAM so the secret is persisted across SMM
handler reload. Add a delay and retry loop before unlock, and restore
NVMe BAR0 if the device loses PCI config state across S3.

The SMM side continues to whitelist only the OPAL service and unlock
APMC commands and fails closed if any invariant is violated.

TEST=tested with rest of patch train

Change-Id: I86a44760a189219a95914bd3549997880fb0242b
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91045
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/arch/x86/acpi_s3.c                      |   4 +
 src/include/security/tcg/opal_s3_resume.h   |  15 +
 src/include/security/tcg/opal_s3_smm.h      |  36 ++
 src/security/tcg/opal_s3/Kconfig            |   1 +
 src/security/tcg/opal_s3/opal_s3_resume.c   |  13 +
 src/security/tcg/opal_s3/opal_s3_smm.c      | 450 ++++++++++++++++++++
 src/soc/intel/common/block/smm/smihandler.c |   8 +
 7 files changed, 527 insertions(+)
 create mode 100644 src/include/security/tcg/opal_s3_resume.h
 create mode 100644 src/include/security/tcg/opal_s3_smm.h
 create mode 100644 src/security/tcg/opal_s3/opal_s3_resume.c
 create mode 100644 src/security/tcg/opal_s3/opal_s3_smm.c

diff --git a/src/arch/x86/acpi_s3.c b/src/arch/x86/acpi_s3.c
index f893e3a9f6..d65a079829 100644
--- a/src/arch/x86/acpi_s3.c
+++ b/src/arch/x86/acpi_s3.c
@@ -6,6 +6,7 @@
 #include <arch/cpu.h>
 #include <commonlib/helpers.h>
 #include <fallback.h>
+#include <security/tcg/opal_s3_resume.h>
 #include <timestamp.h>
 
 #define WAKEUP_BASE 0x600
@@ -20,6 +21,9 @@ void __noreturn acpi_resume(void *wake_vec)
 	/* Call mainboard resume handler first, if defined. */
 	mainboard_suspend_resume();
 
+	if (CONFIG(TCG_OPAL_S3_UNLOCK))
+		opal_s3_resume_unlock();
+
 	/* Copy wakeup trampoline in place. */
 	memcpy((void *)WAKEUP_BASE, &__wakeup, __wakeup_size);
 
diff --git a/src/include/security/tcg/opal_s3_resume.h b/src/include/security/tcg/opal_s3_resume.h
new file mode 100644
index 0000000000..f14ee90b49
--- /dev/null
+++ b/src/include/security/tcg/opal_s3_resume.h
@@ -0,0 +1,15 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef SECURITY_TCG_OPAL_S3_RESUME_H
+#define SECURITY_TCG_OPAL_S3_RESUME_H
+
+/*
+ * Trigger an SMM-assisted OPAL unlock during S3 resume.
+ *
+ * The unlock implementation lives in SMM; this is a small ramstage helper
+ * that issues the APMC trigger. It is called automatically from the x86
+ * resume path when enabled.
+ */
+void opal_s3_resume_unlock(void);
+
+#endif
diff --git a/src/include/security/tcg/opal_s3_smm.h b/src/include/security/tcg/opal_s3_smm.h
new file mode 100644
index 0000000000..798ed0ae0a
--- /dev/null
+++ b/src/include/security/tcg/opal_s3_smm.h
@@ -0,0 +1,36 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef SECURITY_TCG_OPAL_S3_SMM_H
+#define SECURITY_TCG_OPAL_S3_SMM_H
+
+#include <types.h>
+
+/*
+ * OPAL S3 SMM helpers.
+ *
+ * These helpers are called from SMI handlers. When the feature is disabled,
+ * these APIs compile to no-ops so callers do not need preprocessor guards.
+ */
+#if CONFIG(TCG_OPAL_S3_UNLOCK)
+int opal_s3_smi_apmc(u8 apmc);
+void opal_s3_smi_sleep(u8 slp_typ);
+void opal_s3_smi_sleep_finalize(u8 slp_typ);
+#else
+static inline int opal_s3_smi_apmc(u8 apmc)
+{
+	(void)apmc;
+	return 0;
+}
+
+static inline void opal_s3_smi_sleep(u8 slp_typ)
+{
+	(void)slp_typ;
+}
+
+static inline void opal_s3_smi_sleep_finalize(u8 slp_typ)
+{
+	(void)slp_typ;
+}
+#endif
+
+#endif
diff --git a/src/security/tcg/opal_s3/Kconfig b/src/security/tcg/opal_s3/Kconfig
index a34f34234e..15f19af46f 100644
--- a/src/security/tcg/opal_s3/Kconfig
+++ b/src/security/tcg/opal_s3/Kconfig
@@ -7,6 +7,7 @@ config TCG_OPAL_S3_UNLOCK
 	depends on HAVE_ACPI_RESUME
 	depends on PCI
 	select SMM_OPAL_S3_SCRATCH_CBMEM
+	select SMM_OPAL_S3_STATE_SMRAM
 	help
 	  Provide an SMM handler that accepts an OPAL password for the current
 	  sleep cycle and performs an NVMe Security Send/Receive unlock on S3
diff --git a/src/security/tcg/opal_s3/opal_s3_resume.c b/src/security/tcg/opal_s3/opal_s3_resume.c
new file mode 100644
index 0000000000..415564c204
--- /dev/null
+++ b/src/security/tcg/opal_s3/opal_s3_resume.c
@@ -0,0 +1,13 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <console/console.h>
+#include <security/tcg/opal_s3_resume.h>
+#include <smm_call.h>
+
+void opal_s3_resume_unlock(void)
+{
+	u32 rc = call_smm(APM_CNT_OPAL_S3_UNLOCK, 0, NULL);
+
+	if (CONFIG(DEBUG_SMI) && rc)
+		printk(BIOS_DEBUG, "OPAL-S3: resume unlock rc=0x%x\n", rc);
+}
diff --git a/src/security/tcg/opal_s3/opal_s3_smm.c b/src/security/tcg/opal_s3/opal_s3_smm.c
new file mode 100644
index 0000000000..4802b9dceb
--- /dev/null
+++ b/src/security/tcg/opal_s3/opal_s3_smm.c
@@ -0,0 +1,450 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <acpi/acpi.h>
+#include <commonlib/bsd/helpers.h>
+#include <console/console.h>
+#include <cpu/x86/save_state.h>
+#include <cpu/x86/smm.h>
+#include <delay.h>
+#include <device/pci_def.h>
+#include <device/pci_ops.h>
+#include <device/pci_type.h>
+#include <security/tcg/opal_s3.h>
+#include <security/tcg/opal_s3_smm.h>
+#include <vendorcode/tcg/opal/opal_unlock.h>
+#include <stddef.h>
+#include <string.h>
+#include <types.h>
+
+#include "opal_secure.h"
+
+#define OPAL_S3_SCRATCH_ALIGN     4096
+#define OPAL_S3_SCRATCH_PAGES     3
+#define OPAL_S3_SCRATCH_MIN_BYTES (OPAL_S3_SCRATCH_PAGES * OPAL_S3_SCRATCH_ALIGN)
+
+#define OPAL_S3_UNLOCK_RETRY_DELAY_MS   50
+#define OPAL_S3_UNLOCK_RETRIES          10
+
+#define OPAL_S3_STATE_SIGNATURE 0x33534c4f /* "OLS3" */
+#define OPAL_S3_STATE_VERSION   0x0001
+
+#define OPAL_S3_ARMED_NONE      0
+#define OPAL_S3_ARMED_S3        1
+
+#define OPAL_S3_MAX_SECRETS 8
+
+struct __packed opal_s3_secret {
+	u8 valid;
+	u8 reserved0;
+	u16 reserved1;
+
+	u8 bus;
+	u8 dev;
+	u8 func;
+	u8 reserved2;
+
+	u16 base_comid;
+	u8 password_len;
+	u8 reserved3;
+	u8 password[OPAL_S3_MAX_PASSWORD_LEN];
+
+	u32 nvme_bar0_low;
+	u32 nvme_bar0_high;
+
+	u32 unlocked_cycle;
+};
+
+struct __packed opal_s3_state {
+	u32 signature;
+	u16 version;
+	u16 size;
+
+	u8 armed_state;
+	u8 reserved0;
+	u16 reserved1;
+
+	u32 sleep_cycle;
+	u32 armed_cycle;
+
+	struct opal_s3_secret secret[OPAL_S3_MAX_SECRETS];
+};
+
+static struct opal_s3_state state_fallback;
+
+static struct opal_s3_state *opal_s3_get_state(void)
+{
+#if CONFIG(SMM_OPAL_S3_STATE_SMRAM)
+	uintptr_t base = 0;
+	size_t size = 0;
+
+	smm_get_opal_s3_state_buffer(&base, &size);
+	if (base && size >= sizeof(struct opal_s3_state))
+		return (struct opal_s3_state *)(uintptr_t)base;
+#endif
+
+	return &state_fallback;
+}
+
+static bool opal_s3_validate_scratch(uintptr_t base, size_t size, uintptr_t *aligned_base_out,
+				     size_t *aligned_size_out)
+{
+	uintptr_t aligned;
+	size_t aligned_size;
+
+	if (!base || !size)
+		return false;
+
+	if (base + size < base)
+		return false;
+
+	aligned = ALIGN_UP(base, OPAL_S3_SCRATCH_ALIGN);
+	if (aligned < base)
+		return false;
+
+	if (aligned - base > size)
+		return false;
+
+	aligned_size = size - (aligned - base);
+	if (aligned_size < OPAL_S3_SCRATCH_MIN_BYTES)
+		return false;
+
+	if ((aligned & (OPAL_S3_SCRATCH_ALIGN - 1)) != 0)
+		return false;
+
+	if (smm_points_to_smram((void *)(uintptr_t)aligned, OPAL_S3_SCRATCH_MIN_BYTES))
+		return false;
+
+	if (aligned + OPAL_S3_SCRATCH_MIN_BYTES < aligned)
+		return false;
+	if (aligned + OPAL_S3_SCRATCH_MIN_BYTES > base + size)
+		return false;
+
+	*aligned_base_out = aligned;
+	*aligned_size_out = aligned_size;
+	return true;
+}
+
+static u32 opal_s3_clear_secret(void)
+{
+	struct opal_s3_state *st = opal_s3_get_state();
+
+	opal_explicit_bzero(st, sizeof(*st));
+
+	return 0;
+}
+
+static struct opal_s3_secret *opal_s3_find_secret(struct opal_s3_state *st,
+						  const struct opal_s3_smm_ctx *ctx)
+{
+	for (size_t i = 0; i < ARRAY_SIZE(st->secret); i++) {
+		struct opal_s3_secret *s = &st->secret[i];
+
+		if (!s->valid)
+			continue;
+
+		if (s->bus == ctx->bus && s->dev == ctx->dev && s->func == ctx->func &&
+		    s->base_comid == ctx->base_comid)
+			return s;
+	}
+
+	return NULL;
+}
+
+static struct opal_s3_secret *opal_s3_alloc_secret(struct opal_s3_state *st)
+{
+	for (size_t i = 0; i < ARRAY_SIZE(st->secret); i++) {
+		struct opal_s3_secret *s = &st->secret[i];
+
+		if (!s->valid)
+			return s;
+	}
+
+	return NULL;
+}
+
+static u32 opal_s3_set_secret(const struct opal_s3_smm_ctx *ctx)
+{
+	struct opal_s3_state *st = opal_s3_get_state();
+	struct opal_s3_secret *s;
+	uintptr_t scratch_base = 0;
+	size_t scratch_size = 0;
+	uintptr_t aligned_base = 0;
+	size_t aligned_size = 0;
+	pci_devfn_t nvme_dev;
+
+	if (!ctx)
+		return 1;
+
+	if (smm_points_to_smram(ctx, sizeof(*ctx)))
+		return 2;
+
+	if (ctx->signature != OPAL_S3_SMM_CTX_SIGNATURE)
+		return 3;
+
+	if (ctx->version != OPAL_S3_SMM_CTX_VERSION)
+		return 4;
+
+	if (ctx->size < sizeof(*ctx))
+		return 5;
+
+	if (ctx->password_len == 0 || ctx->password_len > OPAL_S3_MAX_PASSWORD_LEN)
+		return 6;
+
+	smm_get_opal_s3_scratch_buffer(&scratch_base, &scratch_size);
+	if (!opal_s3_validate_scratch(scratch_base, scratch_size, &aligned_base,
+				      &aligned_size)) {
+		printk(BIOS_ERR, "OPAL: invalid scratch (base=0x%lx size=0x%zx)\n",
+		       (unsigned long)scratch_base, scratch_size);
+		return 7;
+	}
+
+	nvme_dev = PCI_DEV(ctx->bus, ctx->dev, ctx->func);
+
+	if (st->signature != OPAL_S3_STATE_SIGNATURE || st->version != OPAL_S3_STATE_VERSION ||
+	    st->size != sizeof(*st)) {
+		opal_s3_clear_secret();
+		st->signature = OPAL_S3_STATE_SIGNATURE;
+		st->version = OPAL_S3_STATE_VERSION;
+		st->size = sizeof(*st);
+		st->armed_state = OPAL_S3_ARMED_NONE;
+	}
+
+	s = opal_s3_find_secret(st, ctx);
+	if (!s)
+		s = opal_s3_alloc_secret(st);
+	if (!s)
+		return 8;
+
+	opal_explicit_bzero(s, sizeof(*s));
+	s->valid = 1;
+	s->bus = ctx->bus;
+	s->dev = ctx->dev;
+	s->func = ctx->func;
+	s->base_comid = ctx->base_comid;
+	s->password_len = ctx->password_len;
+	memcpy(s->password, ctx->password, ctx->password_len);
+
+	st->signature = OPAL_S3_STATE_SIGNATURE;
+	st->version = OPAL_S3_STATE_VERSION;
+	st->size = sizeof(*st);
+
+	s->nvme_bar0_low = pci_read_config32(nvme_dev, PCI_BASE_ADDRESS_0);
+	s->nvme_bar0_high = pci_read_config32(nvme_dev, PCI_BASE_ADDRESS_0 + 4);
+
+	return 0;
+}
+
+static void opal_s3_arm_for_s3(void)
+{
+	struct opal_s3_state *st = opal_s3_get_state();
+	bool any_secret = false;
+
+	if (st->signature != OPAL_S3_STATE_SIGNATURE || st->version != OPAL_S3_STATE_VERSION ||
+	    st->size != sizeof(*st))
+		return;
+
+	if (st->armed_state == OPAL_S3_ARMED_S3)
+		return;
+
+	for (size_t i = 0; i < ARRAY_SIZE(st->secret); i++) {
+		if (!st->secret[i].valid)
+			continue;
+
+		any_secret = true;
+		st->secret[i].unlocked_cycle = 0;
+	}
+	if (!any_secret)
+		return;
+
+	st->sleep_cycle++;
+	st->armed_cycle = st->sleep_cycle;
+	st->armed_state = OPAL_S3_ARMED_S3;
+}
+
+static void opal_s3_restore_nvme_bar0_if_needed(pci_devfn_t nvme_dev, u32 saved_bar0_low,
+						u32 saved_bar0_high)
+{
+	const u32 cur_low = pci_read_config32(nvme_dev, PCI_BASE_ADDRESS_0);
+	const u32 cur_base = cur_low & ~PCI_BASE_ADDRESS_MEM_ATTR_MASK;
+	const u32 saved_base = saved_bar0_low & ~PCI_BASE_ADDRESS_MEM_ATTR_MASK;
+	const bool is_saved_mem =
+		((saved_bar0_low & PCI_BASE_ADDRESS_SPACE) == PCI_BASE_ADDRESS_SPACE_MEMORY);
+	const bool is_saved_64 =
+		((saved_bar0_low & PCI_BASE_ADDRESS_MEM_LIMIT_MASK) == PCI_BASE_ADDRESS_MEM_LIMIT_64);
+
+	if (cur_low != 0xffffffff && cur_base != 0)
+		return;
+
+	if (!saved_bar0_low || saved_base == 0 || !is_saved_mem)
+		return;
+
+	pci_write_config32(nvme_dev, PCI_BASE_ADDRESS_0, saved_bar0_low);
+	if (is_saved_64)
+		pci_write_config32(nvme_dev, PCI_BASE_ADDRESS_0 + 4, saved_bar0_high);
+}
+
+static bool opal_s3_unlock_should_keep_armed(u32 rc)
+{
+	return rc == 1 || rc == 3;
+}
+
+static u32 opal_s3_unlock_if_armed(void)
+{
+	struct opal_s3_state *st = opal_s3_get_state();
+	u32 rc = 0;
+	uintptr_t scratch_base = 0;
+	size_t scratch_size = 0;
+	uintptr_t aligned_base = 0;
+	size_t aligned_size = 0;
+	bool keep_armed = false;
+
+	if (st->signature != OPAL_S3_STATE_SIGNATURE || st->version != OPAL_S3_STATE_VERSION ||
+	    st->size != sizeof(*st))
+		return 0x10;
+
+	if (st->armed_state == OPAL_S3_ARMED_NONE)
+		return 0x11;
+
+	if (st->armed_cycle != st->sleep_cycle) {
+		printk(BIOS_ERR, "OPAL: unlock rejected (invalid sequence)\n");
+		opal_s3_clear_secret();
+		return 0x12;
+	}
+
+	smm_get_opal_s3_scratch_buffer(&scratch_base, &scratch_size);
+	if (!opal_s3_validate_scratch(scratch_base, scratch_size, &aligned_base,
+				      &aligned_size)) {
+		printk(BIOS_ERR, "OPAL: scratch invariant failed at unlock\n");
+		st->armed_state = OPAL_S3_ARMED_NONE;
+		st->armed_cycle = 0;
+		return 2;
+	}
+
+	for (size_t i = 0; i < ARRAY_SIZE(st->secret); i++) {
+		struct opal_s3_secret *s = &st->secret[i];
+		pci_devfn_t nvme_dev;
+		u32 one_rc;
+
+		if (!s->valid)
+			continue;
+		if (s->password_len == 0 || s->password_len > OPAL_S3_MAX_PASSWORD_LEN)
+			continue;
+		if (s->unlocked_cycle == st->sleep_cycle)
+			continue;
+
+		nvme_dev = PCI_DEV(s->bus, s->dev, s->func);
+		opal_s3_restore_nvme_bar0_if_needed(nvme_dev, s->nvme_bar0_low,
+						    s->nvme_bar0_high);
+
+		one_rc = 1;
+		for (int attempt = 0; attempt < OPAL_S3_UNLOCK_RETRIES; attempt++) {
+			if (attempt)
+				mdelay(OPAL_S3_UNLOCK_RETRY_DELAY_MS);
+
+			one_rc = opal_nvme_opal_unlock(nvme_dev, s->base_comid, s->password,
+						       s->password_len,
+						       (void *)(uintptr_t)aligned_base,
+						       aligned_size);
+			if (one_rc == 0)
+				break;
+			if (one_rc != 1)
+				break;
+		}
+
+		if (one_rc == 0) {
+			s->unlocked_cycle = st->sleep_cycle;
+			continue;
+		}
+
+		if (opal_s3_unlock_should_keep_armed(one_rc)) {
+			keep_armed = true;
+			if (rc == 0 || rc == 1)
+				rc = one_rc;
+			continue;
+		}
+
+		if (rc == 0)
+			rc = one_rc;
+
+		s->unlocked_cycle = st->sleep_cycle;
+	}
+
+	if (!keep_armed) {
+		st->armed_state = OPAL_S3_ARMED_NONE;
+		st->armed_cycle = 0;
+	}
+
+	return rc;
+}
+
+int opal_s3_smi_apmc(u8 apmc)
+{
+	int node;
+	u64 rax;
+	u64 rbx;
+	u8 subcmd;
+	u32 ret;
+	u32 unlock_rc;
+
+	switch (apmc) {
+	case APM_CNT_OPAL_S3_UNLOCK:
+		unlock_rc = opal_s3_unlock_if_armed();
+
+		node = get_apmc_node(apmc);
+		if (node >= 0) {
+			const u64 rax_out = unlock_rc;
+			(void)set_save_state_reg(RAX, node, (void *)&rax_out, sizeof(rax_out));
+		}
+		return 1;
+
+	case APM_CNT_OPAL_SVC:
+		break;
+
+	default:
+		return 0;
+	}
+
+	node = get_apmc_node(apmc);
+	if (node < 0)
+		return 0;
+
+	if (get_save_state_reg(RAX, node, &rax, sizeof(rax)) < 0)
+		return 0;
+	if (get_save_state_reg(RBX, node, &rbx, sizeof(rbx)) < 0)
+		return 0;
+
+	subcmd = (rax >> 8) & 0xff;
+
+	switch (subcmd) {
+	case OPAL_SMM_SUBCMD_SET_SECRET:
+		ret = opal_s3_set_secret((const struct opal_s3_smm_ctx *)(uintptr_t)rbx);
+		break;
+	case OPAL_SMM_SUBCMD_CLEAR_SECRET:
+		ret = opal_s3_clear_secret();
+		break;
+	default:
+		ret = 0xfffffffe;
+		break;
+	}
+
+	{
+		const u64 rax_out = ret;
+
+		(void)set_save_state_reg(RAX, node, (void *)&rax_out, sizeof(rax_out));
+	}
+	return 1;
+}
+
+void opal_s3_smi_sleep(u8 slp_typ)
+{
+	if (slp_typ == ACPI_S3)
+		opal_s3_arm_for_s3();
+	else
+		opal_s3_clear_secret();
+}
+
+void opal_s3_smi_sleep_finalize(u8 slp_typ)
+{
+	if (slp_typ != ACPI_S3)
+		opal_s3_clear_secret();
+}
diff --git a/src/soc/intel/common/block/smm/smihandler.c b/src/soc/intel/common/block/smm/smihandler.c
index 58c980672c..fd72c25685 100644
--- a/src/soc/intel/common/block/smm/smihandler.c
+++ b/src/soc/intel/common/block/smm/smihandler.c
@@ -23,6 +23,7 @@
 #include <intelblocks/uart.h>
 #include <option.h>
 #include <security/lockdown/lockdown.h>
+#include <security/tcg/opal_s3_smm.h>
 #include <smmstore.h>
 #include <soc/nvs.h>
 #include <soc/pci_devs.h>
@@ -146,6 +147,8 @@ void smihandler_southbridge_sleep(
 	printk(BIOS_SPEW, "SMI#: SLP = 0x%08x\n", reg32);
 	slp_typ = acpi_sleep_from_pm1(reg32);
 
+	opal_s3_smi_sleep(slp_typ);
+
 	/* Do any mainboard sleep handling */
 	mainboard_smi_sleep(slp_typ);
 
@@ -205,6 +208,8 @@ void smihandler_southbridge_sleep(
 		break;
 	}
 
+	opal_s3_smi_sleep_finalize(slp_typ);
+
 	/* Allow mainboard to restore wake sources (e.g. for S5 WOL). */
 	mainboard_smi_sleep_finalize(slp_typ);
 
@@ -387,6 +392,9 @@ void smihandler_southbridge_apmc(
 		break;
 	}
 
+	if (opal_s3_smi_apmc(reg8))
+		return;
+
 	mainboard_smi_apmc(reg8);
 }
 

From 9fc27f4b154d90540fe9f1b3fd6c65c5ed665854 Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Mon, 23 Feb 2026 15:57:41 +0000
Subject: [PATCH 3842/3886] soc/intel/common/pcie/rtd3: Add RTD3 support for
 OPAL S3 unlock

OPAL S3 unlock may run before an RTD3 NVMe is powered on. When the
storage root port uses the RTD3 ACPI driver, trigger the OPAL unlock SMI
at the end of _ON once the port has powered the device.

Do not rely on _ON being invoked during S3 resume. Always trigger a
best-effort unlock during the coreboot resume path. If the NVMe init
path fails (rc=1), keep the sleep cycle armed so a later trigger (e.g.
RTD3 _ON) can retry the unlock.

TEST=tested with rest of patch train

Change-Id: If83b59973ad878c31e19d146fec8bdbb6406ec2f
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91416
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/soc/intel/common/block/pcie/rtd3/rtd3.c | 41 +++++++++++++++++++--
 1 file changed, 37 insertions(+), 4 deletions(-)

diff --git a/src/soc/intel/common/block/pcie/rtd3/rtd3.c b/src/soc/intel/common/block/pcie/rtd3/rtd3.c
index 3a7c8b4afc..32a22f8b92 100644
--- a/src/soc/intel/common/block/pcie/rtd3/rtd3.c
+++ b/src/soc/intel/common/block/pcie/rtd3/rtd3.c
@@ -3,6 +3,7 @@
 #include <acpi/acpigen.h>
 #include <acpi/acpi_device.h>
 #include <console/console.h>
+#include <cpu/x86/smm.h>
 #include <device/device.h>
 #include <device/pci_ids.h>
 #include <device/pci_ops.h>
@@ -138,7 +139,8 @@ static void
 pcie_rtd3_acpi_method_on(unsigned int pcie_rp,
 			 const struct soc_intel_common_block_pcie_rtd3_config *config,
 			 enum pcie_rp_type rp_type,
-			 const struct device *dev)
+			 const struct device *dev,
+			 bool trigger_opal_s3_unlock)
 {
 	const struct device *parent = dev->upstream->dev;
 
@@ -164,6 +166,13 @@ pcie_rtd3_acpi_method_on(unsigned int pcie_rp,
 	acpigen_emit_namestring(acpi_device_path_join(parent, "RTD3._STA"));
 	acpigen_emit_byte(LOCAL0_OP);
 	acpigen_write_if_lequal_op_int(LOCAL0_OP, ONE_OP);
+	/*
+	 * If _ON is called while the power resource is already ON (common during
+	 * resume), still trigger the OPAL S3 unlock request. The SMM handler will
+	 * ignore it unless an S3 resume cycle is armed.
+	 */
+	if (trigger_opal_s3_unlock)
+		acpigen_write_store_int_to_namestr(APM_CNT_OPAL_S3_UNLOCK, "APMC");
 	acpigen_write_return_op(ONE_OP);
 	acpigen_write_if_end();
 
@@ -201,6 +210,16 @@ pcie_rtd3_acpi_method_on(unsigned int pcie_rp,
 	if (!config->disable_l23)
 		pcie_rtd3_acpi_l23_exit();
 
+	/*
+	 * If this root port has a storage device that can be powered down via RTD3,
+	 * the OPAL S3 unlock may need to wait until _ON powers it back up.
+	 *
+	 * Writing the OPAL S3 APMC command triggers a synchronous SMI. If the OPAL
+	 * S3 resume path is not armed, the SMM handler will ignore the request.
+	 */
+	if (trigger_opal_s3_unlock)
+		acpigen_write_store_int_to_namestr(APM_CNT_OPAL_S3_UNLOCK, "APMC");
+
 	if (config->use_rp_mutex)
 		acpigen_write_release(acpi_device_path_join(parent, RP_MUTEX_NAME));
 
@@ -388,6 +407,9 @@ static void pcie_rtd3_acpi_fill_ssdt(const struct device *dev)
 	const struct device *parent = dev->upstream->dev;
 	const char *scope = acpi_device_path(parent);
 	const struct opregion opregion = OPREGION("PXCS", PCI_CONFIG, 0, 0xff);
+	const bool is_storage = config->is_storage ||
+		(dev->sibling && (dev->sibling->class >> 16) == PCI_BASE_CLASS_STORAGE);
+	const bool trigger_opal_s3_unlock = CONFIG(TCG_OPAL_S3_UNLOCK) && is_storage;
 	const struct fieldlist fieldlist[] = {
 		FIELDLIST_OFFSET(PCH_PCIE_CFG_LSTS),
 		FIELDLIST_RESERVED(13),
@@ -473,6 +495,18 @@ static void pcie_rtd3_acpi_fill_ssdt(const struct device *dev)
 	acpigen_write_field("PXCS", fieldlist, ARRAY_SIZE(fieldlist),
 			    FIELD_ANYACC | FIELD_NOLOCK | FIELD_PRESERVE);
 
+	if (trigger_opal_s3_unlock) {
+		const struct opregion apm_opregion = OPREGION("APOR", SYSTEMIO, APM_CNT, 1);
+		const struct fieldlist apm_fieldlist[] = {
+			FIELDLIST_OFFSET(0),
+			FIELDLIST_NAMESTR("APMC", 8),
+		};
+
+		acpigen_write_opregion(&apm_opregion);
+		acpigen_write_field("APOR", apm_fieldlist, ARRAY_SIZE(apm_fieldlist),
+				    FIELD_BYTEACC | FIELD_NOLOCK | FIELD_PRESERVE);
+	}
+
 	if (config->ext_pm_support & ACPI_PCIE_RP_EMIT_L23) {
 		pcie_rtd3_acpi_method_dl23();
 		pcie_rtd3_acpi_method_l23d();
@@ -506,7 +540,7 @@ static void pcie_rtd3_acpi_fill_ssdt(const struct device *dev)
 	}
 
 	pcie_rtd3_acpi_method_status(config);
-	pcie_rtd3_acpi_method_on(pcie_rp, config, rp_type, dev);
+	pcie_rtd3_acpi_method_on(pcie_rp, config, rp_type, dev, trigger_opal_s3_unlock);
 	pcie_rtd3_acpi_method_off(pcie_rp, config, rp_type, dev);
 	acpigen_pop_len(); /* PowerResource */
 
@@ -528,8 +562,7 @@ static void pcie_rtd3_acpi_fill_ssdt(const struct device *dev)
 	 * Check the sibling device on the root port to see if it is storage class and add the
 	 * property for the OS to enable storage D3, or allow it to be enabled by config.
 	 */
-	if (config->is_storage
-	    || (dev->sibling && (dev->sibling->class >> 16) == PCI_BASE_CLASS_STORAGE)) {
+	if (is_storage) {
 		acpigen_write_device(acpi_device_name(dev));
 		acpigen_write_ADR(0);
 		acpigen_write_STA(ACPI_STATUS_DEVICE_ALL_ON);

From e83905943519bc7f43fba9fce45e0f391a89ae41 Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Sun, 1 Feb 2026 21:49:59 +0000
Subject: [PATCH 3843/3886] mainboard/starlabs/common: enable OPAL S3 unlock

Default-enable CONFIG_TCG_OPAL_S3_UNLOCK for Star Labs boards so NVMe
OPAL devices can be unlocked via SMM on S3 resume when the payload
provides the password for the current sleep cycle.

TEST=build/boot adl/hz and starfighter/mtl with TCG enabled, suspend,
and verify SSD can be read after resume.

Change-Id: Ic3d9611295b1bdf9ea49cd6d4d6c924f8eafd746
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91046
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/starlabs/common/Kconfig | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/src/mainboard/starlabs/common/Kconfig b/src/mainboard/starlabs/common/Kconfig
index 9fe452d246..7d8e89ce92 100644
--- a/src/mainboard/starlabs/common/Kconfig
+++ b/src/mainboard/starlabs/common/Kconfig
@@ -34,6 +34,9 @@ config STARLABS_NVME_POWER_SEQUENCE
 	  `variant_nvme_power_sequence_pads()` and
 	  `variant_nvme_power_sequence_post_pads()`.
 
+config TCG_OPAL_S3_UNLOCK
+	default y
+
 config MB_COMMON_DIR
 	string
 	default "starlabs/common"

From 9bfab15070430021eda2a15a07403186ce7cc790 Mon Sep 17 00:00:00 2001
From: Daniel Maslowski <info@orangecms.org>
Date: Tue, 24 Mar 2026 23:44:26 +0100
Subject: [PATCH 3844/3886] docs/mb/hp: fix link to Sure Start whitepaper, add
 another

The URL must have the .pdf extension now, otherwise gets a 404.
Add a note on later revisions of Sure Start.

Change-Id: I00ab30b461795c672890a21d1fb2af929865c822
Signed-off-by: Daniel Maslowski <info@orangecms.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91840
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Khalifa Rouis <khalifa@missingno.tech>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
---
 Documentation/mainboard/hp/hp_sure_start.md | 6 +++++-
 1 file changed, 5 insertions(+), 1 deletion(-)

diff --git a/Documentation/mainboard/hp/hp_sure_start.md b/Documentation/mainboard/hp/hp_sure_start.md
index a07d9d02c7..9429a92008 100644
--- a/Documentation/mainboard/hp/hp_sure_start.md
+++ b/Documentation/mainboard/hp/hp_sure_start.md
@@ -7,6 +7,9 @@ It is implemented in HP notebooks since 2013, and desktops since 2015.
 This document talks about some mechanism of HP Sure Start on some machines, and
 the method to bypass it.
 
+The method may no longer be applicable to more recent boards. HP has a later
+[revision of the whitepaper] from 2019 and there may be others.
+
 ## Laptops with SMSC MEC1322 embedded controller
 
 Haswell EliteBook, ZBook and ProBook 600 series use SMSC MEC1322 embedded controller.
@@ -57,4 +60,5 @@ located at the high address of the flash chip (and in the protected region),
 we can leave it untouched, and do not need to extract the EC firmware to put it in
 the coreboot image.
 
-[HP Sure Start Technical Whitepaper]: http://h10032.www1.hp.com/ctg/Manual/c05163901
+[HP Sure Start Technical Whitepaper]: https://h10032.www1.hp.com/ctg/Manual/c05163901.pdf
+[revision of the whitepaper]: https://h10032.www1.hp.com/ctg/Manual/c06216928.pdf

From b8ed516097bda64f75f9e0e35e25c846bfcdf97c Mon Sep 17 00:00:00 2001
From: Subrata Banik <subratabanik@google.com>
Date: Wed, 25 Mar 2026 14:08:14 +0530
Subject: [PATCH 3845/3886] mb/google/bluey: Defer display initialization based
 on boot mode

Currently, display_startup() is called unconditionally during
mainboard_init(). For normal boot paths, this can lead to unnecessary
latency (40ms) issues.

Modify the initialization flow to:
1. Initialize display early only for low-battery or off-mode
   charging paths to ensure the user sees the charging UI.
2. Defer display initialization for all other modes to a new
   mainboard_late_init() function.
3. Use a static flag (display_init_done) to ensure display_startup()
   is only executed once regardless of the entry point.

TEST=Verified bluey still shows charging animation when low on
battery and boots to OS normally. Able to save 40ms of the boot time.

Change-Id: Id6bdda90b7f67c13cd7334ba17131a8243af0cdb
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91845
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/google/bluey/mainboard.c | 14 ++++++++++++--
 1 file changed, 12 insertions(+), 2 deletions(-)

diff --git a/src/mainboard/google/bluey/mainboard.c b/src/mainboard/google/bluey/mainboard.c
index 5bb9ecd21d..20710b1742 100644
--- a/src/mainboard/google/bluey/mainboard.c
+++ b/src/mainboard/google/bluey/mainboard.c
@@ -220,7 +220,9 @@ static void mainboard_init(void *chip_info)
 	configure_parallel_charging();
 	configure_debug_access_port();
 
-	display_startup();
+	/* Do early display init for low/off-mode charging */
+	if (get_boot_mode() != LB_BOOT_MODE_NORMAL)
+		display_startup();
 
 	/*
 	 * Low-battery boot indicator is done. Therefore, power off if battery
@@ -270,10 +272,13 @@ static void load_qc_se_firmware_late(void)
 		qupv3_se_fw_load_and_init(QUPV3_2_SE2, SE_PROTOCOL_SPI, MIXED); /* Fingerprint SPI */
 }
 
-static void mainboard_enable(struct device *dev)
+static void mainboard_late_init(struct device *dev)
 {
 	load_qc_se_firmware_late();
 
+	/* Do late display init in normal boot mode */
+	display_startup();
+
 	/* Enable touchpad power */
 	if (CONFIG_MAINBOARD_GPIO_PIN_FOR_TOUCHPAD_POWER)
 		gpio_output(GPIO_TP_POWER_EN, 1);
@@ -289,6 +294,11 @@ static void mainboard_enable(struct device *dev)
 	setup_audio();
 }
 
+static void mainboard_enable(struct device *dev)
+{
+	dev->ops->init = &mainboard_late_init;
+}
+
 struct chip_operations mainboard_ops = {
 	.enable_dev = mainboard_enable,
 	.init = mainboard_init,

From cb05d160d45209c19c6ead21ae7abd392e848d5e Mon Sep 17 00:00:00 2001
From: Subrata Banik <subratabanik@google.com>
Date: Thu, 26 Mar 2026 20:32:41 +0000
Subject: [PATCH 3846/3886] soc/qualcomm/x1p42100: Rename SOC_QUALCOMM_BASE to
 include SoC name

The generic config name SOC_QUALCOMM_BASE is too broad and could
potentially conflict with other Qualcomm SoC families or common
code.

Rename it to SOC_QUALCOMM_X1P42100_BASE in both Kconfig and
Makefile.mk to ensure the configuration is explicitly scoped to
the X1P42100 series.

Change-Id: Idb74ad5ecd6180e3b472a5d007157fcc76f3e89d
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91891
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/soc/qualcomm/x1p42100/Kconfig     | 8 ++++----
 src/soc/qualcomm/x1p42100/Makefile.mk | 4 ++--
 2 files changed, 6 insertions(+), 6 deletions(-)

diff --git a/src/soc/qualcomm/x1p42100/Kconfig b/src/soc/qualcomm/x1p42100/Kconfig
index b2244358aa..8b730906c3 100644
--- a/src/soc/qualcomm/x1p42100/Kconfig
+++ b/src/soc/qualcomm/x1p42100/Kconfig
@@ -1,6 +1,6 @@
 ## SPDX-License-Identifier: GPL-2.0-only
 
-config SOC_QUALCOMM_BASE
+config SOC_QUALCOMM_X1P42100_BASE
 	bool
 	default n
 	select ARCH_BOOTBLOCK_ARMV8_64
@@ -33,7 +33,7 @@ config SOC_QUALCOMM_BASE
 
 config SOC_QUALCOMM_X1P42100
 	bool
-	select SOC_QUALCOMM_BASE
+	select SOC_QUALCOMM_X1P42100_BASE
 	default n
 	help
 	  Choose this option if the mainboard is built using Qualcomm X1P42100 system-on-a-chip SoC.
@@ -42,12 +42,12 @@ config SOC_QUALCOMM_HAMOA
 	bool
 	select ARM64_USE_SECURE_OS
 	select ARM64_USE_SECURE_OS_PAYLOAD
-	select SOC_QUALCOMM_BASE
+	select SOC_QUALCOMM_X1P42100_BASE
 	default n
 	help
 	  Choose this option if the mainboard is built using Qualcomm Hamoa system-on-a-chip SoC.
 
-if SOC_QUALCOMM_BASE
+if SOC_QUALCOMM_X1P42100_BASE
 
 config QC_BLOBS_UPSTREAM
 	bool "QC blobs are available in upstream repository"
diff --git a/src/soc/qualcomm/x1p42100/Makefile.mk b/src/soc/qualcomm/x1p42100/Makefile.mk
index 2fdade4c6a..a7d1c32f4d 100644
--- a/src/soc/qualcomm/x1p42100/Makefile.mk
+++ b/src/soc/qualcomm/x1p42100/Makefile.mk
@@ -1,5 +1,5 @@
 ## SPDX-License-Identifier: GPL-2.0-only
-ifeq ($(CONFIG_SOC_QUALCOMM_BASE),y)
+ifeq ($(CONFIG_SOC_QUALCOMM_X1P42100_BASE),y)
 
 decompressor-y += decompressor.c
 decompressor-y += mmu.c
@@ -392,4 +392,4 @@ endif # ifeq ($(CONFIG_QC_RAMDUMP_ENABLE),y)
 endif # ifeq ($(CONFIG_USE_QC_BLOBS),y)
 
 endif # ifeq ($(CONFIG_QC_BLOBS_UPSTREAM),y)
-endif # ifeq ($(CONFIG_SOC_QUALCOMM_BASE),y)
+endif # ifeq ($(CONFIG_SOC_QUALCOMM_X1P42100_BASE),y)

From c7a7fbbf2c8ac22617cef5c34a70b02ef2d31860 Mon Sep 17 00:00:00 2001
From: Subrata Banik <subratabanik@google.com>
Date: Fri, 27 Mar 2026 18:12:27 +0000
Subject: [PATCH 3847/3886] soc/qualcomm: Add support for QUPV3 wrapper 3

The X1P42100 SoC and future Qualcomm platforms support more than two
QUPV3 wrappers. This patch extends the common Qualcomm drivers to
handle a third wrapper (QUP_WRAP3).

Details:
- clock.c: Update clock_configure_dfsr_table() to support wrap3.
- qupv3_config.c: Initialize the third wrapper if defined.
- addressmap.h: Add QUP_WRAP3_BASE defines for sc7180, sc7280,
  and x1p42100 (defaulting to 0 for older chips).

Change-Id: I58ed310c65319f26ec029071d170237130d9ba19
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91900
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
---
 src/soc/qualcomm/common/clock.c                    | 5 +++++
 src/soc/qualcomm/common/qupv3_config.c             | 2 ++
 src/soc/qualcomm/sc7180/include/soc/addressmap.h   | 3 +++
 src/soc/qualcomm/sc7280/include/soc/addressmap.h   | 3 +++
 src/soc/qualcomm/x1p42100/include/soc/addressmap.h | 3 +++
 5 files changed, 16 insertions(+)

diff --git a/src/soc/qualcomm/common/clock.c b/src/soc/qualcomm/common/clock.c
index 2682721aa0..175a44c59d 100644
--- a/src/soc/qualcomm/common/clock.c
+++ b/src/soc/qualcomm/common/clock.c
@@ -205,6 +205,11 @@ void clock_configure_dfsr_table(int qup, struct clock_freq_config *clk_cfg,
 	unsigned int idx, s = qup % QUP_WRAP1_S0;
 	uint32_t reg_val;
 
+#if QUP_WRAP3_BASE
+	if (qup >= QUP_WRAP3_S0)
+		qup_clk = &gcc->qup_wrap3_s[s];
+	else
+#endif
 #if QUP_WRAP2_BASE
 	if (qup >= QUP_WRAP2_S0)
 		qup_clk = &gcc->qup_wrap2_s[s];
diff --git a/src/soc/qualcomm/common/qupv3_config.c b/src/soc/qualcomm/common/qupv3_config.c
index 0b4d17ceb1..cb1591a4f8 100644
--- a/src/soc/qualcomm/common/qupv3_config.c
+++ b/src/soc/qualcomm/common/qupv3_config.c
@@ -264,4 +264,6 @@ void qupv3_fw_init(void)
 	qup_common_init(QUP_WRAP1_BASE);
 	if (QUP_WRAP2_BASE)
 		qup_common_init(QUP_WRAP2_BASE);
+	if (QUP_WRAP3_BASE)
+		qup_common_init(QUP_WRAP3_BASE);
 }
diff --git a/src/soc/qualcomm/sc7180/include/soc/addressmap.h b/src/soc/qualcomm/sc7180/include/soc/addressmap.h
index e445392274..f5438722c0 100644
--- a/src/soc/qualcomm/sc7180/include/soc/addressmap.h
+++ b/src/soc/qualcomm/sc7180/include/soc/addressmap.h
@@ -37,6 +37,9 @@
 /* QUPV3_2 - Dummy Entry */
 #define QUP_WRAP2_BASE			0x00000000
 
+/* QUPV3_3 - Dummy Entry */
+#define QUP_WRAP3_BASE			0x00000000
+
 /*
  * USB BASE ADDRESSES
  */
diff --git a/src/soc/qualcomm/sc7280/include/soc/addressmap.h b/src/soc/qualcomm/sc7280/include/soc/addressmap.h
index fb5bf6f0d5..74a0bb85fc 100644
--- a/src/soc/qualcomm/sc7280/include/soc/addressmap.h
+++ b/src/soc/qualcomm/sc7280/include/soc/addressmap.h
@@ -58,6 +58,9 @@
 /* QUPV3_2 - Dummy Entry */
 #define QUP_WRAP2_BASE			0x00000000
 
+/* QUPV3_3 - Dummy Entry */
+#define QUP_WRAP3_BASE			0x00000000
+
 #define EPSSTOP_EPSS_TOP		0x18598000
 #define EPSSFAST_BASE_ADDR		0x18580000
 
diff --git a/src/soc/qualcomm/x1p42100/include/soc/addressmap.h b/src/soc/qualcomm/x1p42100/include/soc/addressmap.h
index 63d96a3ea4..d61824b0ba 100644
--- a/src/soc/qualcomm/x1p42100/include/soc/addressmap.h
+++ b/src/soc/qualcomm/x1p42100/include/soc/addressmap.h
@@ -98,6 +98,9 @@
 #define QUP_WRAP2_BASE			0x008C0000
 #define QUP_2_GSI_BASE			0x00804000
 
+/* QUPV3_3 - Dummy Entry */
+#define QUP_WRAP3_BASE			0x00000000
+
 /* USB BASE ADDRESSES */
 #define HS_USB_SS0_PHY_BASE		0x00FD3000
 #define HS_USB_SS1_PHY_BASE		0x00FD9000

From 38e8eadfa7bb2eaec2cf4f20da122d14264bcfee Mon Sep 17 00:00:00 2001
From: Subrata Banik <subratabanik@google.com>
Date: Thu, 26 Mar 2026 20:40:08 +0000
Subject: [PATCH 3848/3886] soc/qualcomm/calypso: Add initial SoC skeleton for
 Calypso

This commit introduces a basic SoC framework for the Qualcomm
Calypso SoC enabling initial build integration.

Key changes:

- Add placeholder SoC callbacks to facilitate control flow from /lib
  and Qualcomm common code.
- Populate the calypso SoC directory with a copy of the X1P42100
  codebase, with SoC-specific implementations removed.

This provides a foundational structure for Calypso development
within the `soc/qualcomm/calypso` directory, ensuring the upstream
builder can successfully compile the SoC code.

This allows for incremental development and integration.

Reference Document: Calypso Hardware Register Description

BUG=b:496650089
TEST=Successfully built google/mensa with the Qualcomm Calypso SoC.

Change-Id: Iabbbf26c9e08906db2be024911061837fdf83bd9
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91892
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/soc/qualcomm/calypso/Kconfig              |  67 ++++
 src/soc/qualcomm/calypso/Makefile.mk          | 345 ++++++++++++++++++
 src/soc/qualcomm/calypso/bootblock.c          |  15 +
 src/soc/qualcomm/calypso/cbmem.c              |  10 +
 src/soc/qualcomm/calypso/clock.c              |  18 +
 src/soc/qualcomm/calypso/cpucp_load_reset.c   |   8 +
 src/soc/qualcomm/calypso/decompressor.c       |   9 +
 .../qualcomm/calypso/include/soc/addressmap.h |  69 ++++
 src/soc/qualcomm/calypso/include/soc/clock.h  |  52 +++
 src/soc/qualcomm/calypso/include/soc/cpucp.h  |   8 +
 src/soc/qualcomm/calypso/include/soc/gpio.h   |  24 ++
 src/soc/qualcomm/calypso/include/soc/mmu.h    |   8 +
 .../calypso/include/soc/qcom_qup_se.h         |  53 +++
 src/soc/qualcomm/calypso/include/soc/shrm.h   |   8 +
 src/soc/qualcomm/calypso/include/soc/uart.h   |   9 +
 src/soc/qualcomm/calypso/memlayout.ld         | 295 +++++++++++++++
 src/soc/qualcomm/calypso/mmu.c                |  21 ++
 src/soc/qualcomm/calypso/pcie.c               |  30 ++
 src/soc/qualcomm/calypso/qclib.c              |  17 +
 src/soc/qualcomm/calypso/qcom_qup_se.c        |   8 +
 src/soc/qualcomm/calypso/soc.c                |  75 ++++
 21 files changed, 1149 insertions(+)
 create mode 100644 src/soc/qualcomm/calypso/Kconfig
 create mode 100644 src/soc/qualcomm/calypso/Makefile.mk
 create mode 100644 src/soc/qualcomm/calypso/bootblock.c
 create mode 100644 src/soc/qualcomm/calypso/cbmem.c
 create mode 100644 src/soc/qualcomm/calypso/clock.c
 create mode 100644 src/soc/qualcomm/calypso/cpucp_load_reset.c
 create mode 100644 src/soc/qualcomm/calypso/decompressor.c
 create mode 100644 src/soc/qualcomm/calypso/include/soc/addressmap.h
 create mode 100644 src/soc/qualcomm/calypso/include/soc/clock.h
 create mode 100644 src/soc/qualcomm/calypso/include/soc/cpucp.h
 create mode 100644 src/soc/qualcomm/calypso/include/soc/gpio.h
 create mode 100644 src/soc/qualcomm/calypso/include/soc/mmu.h
 create mode 100644 src/soc/qualcomm/calypso/include/soc/qcom_qup_se.h
 create mode 100644 src/soc/qualcomm/calypso/include/soc/shrm.h
 create mode 100644 src/soc/qualcomm/calypso/include/soc/uart.h
 create mode 100644 src/soc/qualcomm/calypso/memlayout.ld
 create mode 100644 src/soc/qualcomm/calypso/mmu.c
 create mode 100644 src/soc/qualcomm/calypso/pcie.c
 create mode 100644 src/soc/qualcomm/calypso/qclib.c
 create mode 100644 src/soc/qualcomm/calypso/qcom_qup_se.c
 create mode 100644 src/soc/qualcomm/calypso/soc.c

diff --git a/src/soc/qualcomm/calypso/Kconfig b/src/soc/qualcomm/calypso/Kconfig
new file mode 100644
index 0000000000..5c988b39fc
--- /dev/null
+++ b/src/soc/qualcomm/calypso/Kconfig
@@ -0,0 +1,67 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
+config SOC_QUALCOMM_CALYPSO_BASE
+	bool
+	default n
+	select ARCH_BOOTBLOCK_ARMV8_64
+	select ARCH_RAMSTAGE_ARMV8_64
+	select ARCH_ROMSTAGE_ARMV8_64
+	select ARCH_VERSTAGE_ARMV8_64
+	select ARM64_USE_ARCH_TIMER
+	select CACHE_MRC_SETTINGS
+	select COMMONLIB_STORAGE
+	select COMMONLIB_STORAGE_SD
+	select FIXED_UART_FOR_CONSOLE
+	select GENERIC_GPIO_LIB
+	select GENERIC_UDELAY
+	select HAS_RECOVERY_MRC_CACHE
+	select HAVE_CBFS_FILE_OPTION_BACKEND
+	select HAVE_LINEAR_FRAMEBUFFER
+	select HAVE_MONOTONIC_TIMER
+	select HAVE_UART_SPECIAL
+	select MAINBOARD_FORCE_NATIVE_VGA_INIT
+	select MAINBOARD_HAS_NATIVE_VGA_INIT
+	select SOC_QUALCOMM_COMMON
+	select SOC_QUALCOMM_QCLIB_SKIP_MMU_TOGGLE
+
+config SOC_QUALCOMM_CALYPSO
+	bool
+	select SOC_QUALCOMM_CALYPSO_BASE
+	default n
+	help
+	  Choose this option if the mainboard is built using Calypso system-on-a-chip SoC.
+
+if SOC_QUALCOMM_CALYPSO_BASE
+
+config QC_BLOBS_UPSTREAM
+	bool "QC blobs are available in upstream repository"
+	select USE_QC_BLOBS
+	default n
+	help
+	  Select based on availability of QC blobs in upstream coreboot `3rdparty/qc_blobs`.
+
+config MEMLAYOUT_LD_FILE
+	string
+	default "src/soc/qualcomm/calypso/memlayout.ld"
+
+config VBOOT
+	select VBOOT_MUST_REQUEST_DISPLAY
+	select VBOOT_RETURN_FROM_VERSTAGE
+	select VBOOT_SEPARATE_VERSTAGE
+	select VBOOT_STARTS_IN_BOOTBLOCK
+
+config BOOT_DEVICE_SPI_FLASH_BUS
+	int
+	default 0 # TODO
+
+config UART_FOR_CONSOLE
+	int
+	default 0 # TODO
+	help
+	 Select the QUP instance to be used for UART console output.
+
+config UART_BITBANG_TX_DELAY_MS
+	int
+	default 1
+
+endif
diff --git a/src/soc/qualcomm/calypso/Makefile.mk b/src/soc/qualcomm/calypso/Makefile.mk
new file mode 100644
index 0000000000..01546a9f2f
--- /dev/null
+++ b/src/soc/qualcomm/calypso/Makefile.mk
@@ -0,0 +1,345 @@
+## SPDX-License-Identifier: GPL-2.0-only
+ifeq ($(CONFIG_SOC_QUALCOMM_CALYPSO_BASE),y)
+
+decompressor-y += decompressor.c
+decompressor-y += mmu.c
+decompressor-y += ../common/timer.c
+all-y += ../common/timer.c
+all-y += ../common/gpio.c
+all-y += clock.c
+all-y += ../common/spi.c
+all-y += ../common/qspi.c
+all-y += ../common/qupv3_config.c
+all-y += qcom_qup_se.c
+all-y += ../common/qup_se_handler.c
+all-y += ../common/qupv3_spi.c
+all-y += ../common/qupv3_i2c.c
+all-y += ../common/qupv3_spi.c
+
+################################################################################
+bootblock-y += bootblock.c
+bootblock-y += mmu.c
+bootblock-$(CONFIG_DRIVERS_UART) += ../common/uart_bitbang.c
+
+################################################################################
+verstage-$(CONFIG_DRIVERS_UART) += ../common/qupv3_uart.c
+
+################################################################################
+romstage-y += cbmem.c
+romstage-y += ../common/shrm_load_reset.c
+romstage-y += cpucp_load_reset.c
+romstage-y += ../common/qclib.c
+romstage-y += ../common/mmu.c
+romstage-y += ../common/watchdog.c
+romstage-y += mmu.c
+romstage-y += ../common/aop_load_reset.c
+romstage-$(CONFIG_DRIVERS_UART) += ../common/qupv3_uart.c
+
+################################################################################
+ramstage-y += soc.c
+ramstage-y += cbmem.c
+ramstage-y += ../common/mmu.c
+ramstage-$(CONFIG_DRIVERS_UART) += ../common/qupv3_uart.c
+ramstage-y += cpucp_load_reset.c
+
+################################################################################
+
+CPPFLAGS_common += -Isrc/soc/qualcomm/calypso/include
+CPPFLAGS_common += -Isrc/soc/qualcomm/common/include
+
+################################################################################
+# look for QC blobs if QC SoC blobs are only available in upstream else ignore
+ifeq ($(CONFIG_QC_BLOBS_UPSTREAM),y)
+ifeq ($(CONFIG_USE_QC_BLOBS),y)
+CALYPSO_BLOB := $(top)/3rdparty/qc_blobs/calypso
+
+ifeq ($(CONFIG_QC_SECURE_BOOT_BLOBS),y)
+BLOB_VARIANT := secure
+else
+BLOB_VARIANT := non_secure
+endif
+
+DTB_DCB_BLOB_PATH := calypso
+
+ifeq ($(CONFIG_QC_SDI_ENABLE),y)
+BL31_MAKEARGS += QTI_SDI_BUILD=1
+BL31_MAKEARGS += QTISECLIB_PATH=$(CALYPSO_BLOB)/qtiseclib/libqtisec_dbg.a
+else
+BL31_MAKEARGS += QTISECLIB_PATH=$(CALYPSO_BLOB)/qtiseclib/libqtisec.a
+endif # CONFIG_QC_SDI_ENABLE
+
+################################################################################
+ifeq ($(CONFIG_QC_SDI_ENABLE),y)
+QCSDI_FILE := $(CALYPSO_BLOB)/boot/QcSdi.elf
+QCSDI_CBFS := $(CONFIG_CBFS_PREFIX)/qcsdi
+$(QCSDI_CBFS)-file := $(QCSDI_FILE)
+$(QCSDI_CBFS)-type := stage
+$(QCSDI_CBFS)-compression := $(CBFS_COMPRESS_FLAG)
+cbfs-files-y += $(QCSDI_CBFS)
+endif
+
+################################################################################
+QC_SEC_FILE := $(CALYPSO_BLOB)/$(BLOB_VARIANT)/qc_sec/qc_sec.mbn
+TME_SEQ_FILE := $(CALYPSO_BLOB)/$(BLOB_VARIANT)/tme/sequencer_ram.elf
+TME_FW_FILE := $(CALYPSO_BLOB)/$(BLOB_VARIANT)/tme/signed_firmware_soc_view.elf
+
+$(objcbfs)/bootblock.bin: $(objcbfs)/bootblock.raw.elf
+	@util/qualcomm/createxbl.py --mbn_version 7 -f $(objcbfs)/bootblock.raw.elf \
+		-o $(objcbfs)/bootblock.mbn \
+		-a 64 -c 64
+	@util/qualcomm/create_multielf.py -f $(TME_SEQ_FILE),$(TME_FW_FILE),$(QC_SEC_FILE),$(objcbfs)/bootblock.mbn \
+		-o $(objcbfs)/merged_bb.melf
+	@printf "\nqgpt.py 4K sector size\n"
+	@util/qualcomm/qgpt.py $(objcbfs)/merged_bb.melf \
+		$(objcbfs)/bootblock.bin
+
+################################################################################
+QCLIB_FILE := $(CALYPSO_BLOB)/boot/QcLib.elf
+QCLIB_CBFS := $(CONFIG_CBFS_PREFIX)/qclib
+$(QCLIB_CBFS)-file := $(QCLIB_FILE)
+$(QCLIB_CBFS)-type := stage
+$(QCLIB_CBFS)-compression := $(CBFS_PRERAM_COMPRESS_FLAG)
+cbfs-files-y += $(QCLIB_CBFS)
+
+################################################################################
+DCB_FILE := $(CALYPSO_BLOB)/boot/$(DTB_DCB_BLOB_PATH)/dcb.bin
+DCB_CBFS := $(CONFIG_CBFS_PREFIX)/dcb
+$(DCB_CBFS)-file := $(DCB_FILE)
+$(DCB_CBFS)-type := raw
+$(DCB_CBFS)-compression := $(CBFS_COMPRESS_FLAG)
+cbfs-files-y += $(DCB_CBFS)
+
+################################################################################
+DTB_FILE := $(CALYPSO_BLOB)/boot/$(DTB_DCB_BLOB_PATH)/pre-ddr.dtb
+DTB_CBFS := $(CONFIG_CBFS_PREFIX)/dtb
+$(DTB_CBFS)-file := $(DTB_FILE)
+$(DTB_CBFS)-type := raw
+$(DTB_CBFS)-compression := $(CBFS_COMPRESS_FLAG)
+cbfs-files-y += $(DTB_CBFS)
+
+################################################################################
+CPR_FILE := $(CALYPSO_BLOB)/boot/$(DTB_DCB_BLOB_PATH)/cpr.bin
+CPR_CBFS := $(CONFIG_CBFS_PREFIX)/cpr
+$(CPR_CBFS)-file := $(CPR_FILE)
+$(CPR_CBFS)-type := raw
+$(CPR_CBFS)-compression := $(CBFS_PRERAM_COMPRESS_FLAG)
+cbfs-files-y += $(CPR_CBFS)
+
+################################################################################
+UART_FW_FILE := $(CALYPSO_BLOB)/qup_fw/uart_fw.bin
+UART_FW_CBFS := $(CONFIG_CBFS_PREFIX)/uart_fw
+$(UART_FW_CBFS)-file := $(UART_FW_FILE)
+$(UART_FW_CBFS)-type := raw
+$(UART_FW_CBFS)-compression := none
+cbfs-files-y += $(UART_FW_CBFS)
+
+################################################################################
+SPI_FW_FILE := $(CALYPSO_BLOB)/qup_fw/spi_fw.bin
+SPI_FW_CBFS := $(CONFIG_CBFS_PREFIX)/spi_fw
+$(SPI_FW_CBFS)-file := $(SPI_FW_FILE)
+$(SPI_FW_CBFS)-type := raw
+$(SPI_FW_CBFS)-compression := none
+cbfs-files-y += $(SPI_FW_CBFS)
+
+################################################################################
+I2C_FW_FILE := $(CALYPSO_BLOB)/qup_fw/i2c_fw.bin
+I2C_FW_CBFS := $(CONFIG_CBFS_PREFIX)/i2c_fw
+$(I2C_FW_CBFS)-file := $(I2C_FW_FILE)
+$(I2C_FW_CBFS)-type := raw
+$(I2C_FW_CBFS)-compression := none
+cbfs-files-y += $(I2C_FW_CBFS)
+
+################################################################################
+AOP_FILE := $(CALYPSO_BLOB)/$(BLOB_VARIANT)/aop/aop.mbn
+AOP_CBFS := $(CONFIG_CBFS_PREFIX)/aop
+$(AOP_CBFS)-file := $(AOP_FILE)
+$(AOP_CBFS)-type := payload
+$(AOP_CBFS)-compression := $(CBFS_COMPRESS_FLAG)
+cbfs-files-y += $(AOP_CBFS)
+
+################################################################################
+# Rule to create aop_meta from aop.mbn
+# This rule depends on aop.mbn built and the extractor script existing.
+$(obj)/mainboard/$(MAINBOARDDIR)/aop_meta: $(CALYPSO_BLOB)/$(BLOB_VARIANT)/aop/aop.mbn util/qualcomm/elf_segment_extractor.py
+	@echo "Extracting ELF headers and hash table segment from $< to $@"
+	@util/qualcomm/elf_segment_extractor.py --eh --pht --hashtable $< $@
+
+AOP_META_FILE := $(obj)/mainboard/$(MAINBOARDDIR)/aop_meta
+AOP_META_CBFS := $(CONFIG_CBFS_PREFIX)/aop_meta
+$(AOP_META_CBFS)-file := $(AOP_META_FILE)
+$(AOP_META_CBFS)-type := raw
+$(AOP_META_CBFS)-compression := $(CBFS_COMPRESS_FLAG)
+cbfs-files-y += $(AOP_META_CBFS)
+
+################################################################################
+AOP_CFG_FILE := $(CALYPSO_BLOB)/$(BLOB_VARIANT)/aop/aop_devcfg.mbn
+AOP_CFG_CBFS := $(CONFIG_CBFS_PREFIX)/aop_cfg
+$(AOP_CFG_CBFS)-file := $(AOP_CFG_FILE)
+$(AOP_CFG_CBFS)-type := payload
+$(AOP_CFG_CBFS)-compression := $(CBFS_COMPRESS_FLAG)
+cbfs-files-y += $(AOP_CFG_CBFS)
+
+################################################################################
+# Rule to create aop_meta from aop_devcfg.mbn
+# This rule depends on aop_devcfg.mbn built and the extractor script existing.
+$(obj)/mainboard/$(MAINBOARDDIR)/aop_devcfg_meta: $(CALYPSO_BLOB)/$(BLOB_VARIANT)/aop/aop_devcfg.mbn util/qualcomm/elf_segment_extractor.py
+	@echo "Extracting ELF headers and hash table segment from $< to $@"
+	@util/qualcomm/elf_segment_extractor.py --eh --pht --hashtable $< $@
+
+AOP_DEVCFG_META_FILE := $(obj)/mainboard/$(MAINBOARDDIR)/aop_devcfg_meta
+AOP_DEVCFG_META_CBFS := $(CONFIG_CBFS_PREFIX)/aop_devcfg_meta
+$(AOP_DEVCFG_META_CBFS)-file := $(AOP_DEVCFG_META_FILE)
+$(AOP_DEVCFG_META_CBFS)-type := raw
+$(AOP_DEVCFG_META_CBFS)-compression := $(CBFS_COMPRESS_FLAG)
+cbfs-files-y += $(AOP_DEVCFG_META_CBFS)
+
+################################################################################
+CPUCP_FILE := $(CALYPSO_BLOB)/cpucp/cpucp.elf
+CPUCP_CBFS := $(CONFIG_CBFS_PREFIX)/cpucp
+$(CPUCP_CBFS)-file := $(CPUCP_FILE)
+$(CPUCP_CBFS)-type := payload
+$(CPUCP_CBFS)-compression := none
+cbfs-files-y += $(CPUCP_CBFS)
+
+################################################################################
+# Rule to create cpucp_meta from cpucp.elf
+# This rule depends on cpucp.elf being built and the extractor script existing.
+$(obj)/mainboard/$(MAINBOARDDIR)/cpucp_meta: $(CALYPSO_BLOB)/cpucp/cpucp.elf util/qualcomm/elf_segment_extractor.py
+	@echo "Extracting ELF headers and hash table segment from $< to $@"
+	@util/qualcomm/elf_segment_extractor.py --eh --pht --hashtable $< $@
+
+CPUCP_META_FILE := $(obj)/mainboard/$(MAINBOARDDIR)/cpucp_meta
+CPUCP_META_CBFS := $(CONFIG_CBFS_PREFIX)/cpucp_meta
+$(CPUCP_META_CBFS)-file := $(CPUCP_META_FILE)
+$(CPUCP_META_CBFS)-type := raw
+$(CPUCP_META_CBFS)-compression := $(CBFS_COMPRESS_FLAG)
+cbfs-files-y += $(CPUCP_META_CBFS)
+
+################################################################################
+CPUCP_DTBS_FILE := $(CALYPSO_BLOB)/cpucp/cpucp_dtbs.elf
+CPUCP_DTBS_CBFS := $(CONFIG_CBFS_PREFIX)/cpucp_dtbs
+$(CPUCP_DTBS_CBFS)-file := $(CPUCP_DTBS_FILE)
+$(CPUCP_DTBS_CBFS)-type := payload
+$(CPUCP_DTBS_CBFS)-compression := $(CBFS_COMPRESS_FLAG)
+cbfs-files-y += $(CPUCP_DTBS_CBFS)
+
+################################################################################
+SHRM_FILE := $(CALYPSO_BLOB)/$(BLOB_VARIANT)/shrm/shrm.elf
+SHRM_CBFS := $(CONFIG_CBFS_PREFIX)/shrm
+$(SHRM_CBFS)-file := $(SHRM_FILE)
+$(SHRM_CBFS)-type := payload
+$(SHRM_CBFS)-compression := $(CBFS_PRERAM_COMPRESS_FLAG)
+cbfs-files-y += $(SHRM_CBFS)
+
+################################################################################
+# Rule to create shrm_meta from shrm.elf
+# This rule depends on shrm.elf being built and the extractor script existing.
+$(obj)/mainboard/$(MAINBOARDDIR)/shrm_meta: $(CALYPSO_BLOB)/$(BLOB_VARIANT)/shrm/shrm.elf util/qualcomm/elf_segment_extractor.py
+	@echo "Extracting ELF headers and hash table segment from $< to $@"
+	@util/qualcomm/elf_segment_extractor.py --eh --pht --hashtable $< $@
+
+SHRM_META_FILE := $(obj)/mainboard/$(MAINBOARDDIR)/shrm_meta
+SHRM_META_CBFS := $(CONFIG_CBFS_PREFIX)/shrm_meta
+$(SHRM_META_CBFS)-file := $(SHRM_META_FILE)
+$(SHRM_META_CBFS)-type := raw
+$(SHRM_META_CBFS)-compression := $(CBFS_PRERAM_COMPRESS_FLAG)
+cbfs-files-y += $(SHRM_META_CBFS)
+
+################################################################################
+GSI_FW_FILE := $(CALYPSO_BLOB)/qup_fw/gsi_fw.bin
+GSI_FW_CBFS := $(CONFIG_CBFS_PREFIX)/gsi_fw
+$(GSI_FW_CBFS)-file := $(GSI_FW_FILE)
+$(GSI_FW_CBFS)-type := raw
+$(GSI_FW_CBFS)-compression := none
+cbfs-files-y += $(GSI_FW_CBFS)
+
+################################################################################
+ifeq ($(CONFIG_ARM64_USE_SECURE_OS),y)
+
+DEVCFG_TZ_FILE := $(CALYPSO_BLOB)/qtee/tz_oem_config.mbn
+DEVCFG_TZ_FILE_CBFS := $(CONFIG_CBFS_PREFIX)/tzoem_cfg
+$(DEVCFG_TZ_FILE_CBFS)-file := $(DEVCFG_TZ_FILE)
+$(DEVCFG_TZ_FILE_CBFS)-type := payload
+$(DEVCFG_TZ_FILE_CBFS)-compression := $(CBFS_COMPRESS_FLAG)
+cbfs-files-y += $(DEVCFG_TZ_FILE_CBFS)
+
+################################################################################
+TZQTI_CFG_FILE := $(CALYPSO_BLOB)/qtee/tz_qti_config.mbn
+TZQTI_CFG_FILE_CBFS := $(CONFIG_CBFS_PREFIX)/tzqti_cfg
+$(TZQTI_CFG_FILE_CBFS)-file := $(TZQTI_CFG_FILE)
+$(TZQTI_CFG_FILE_CBFS)-type := payload
+$(TZQTI_CFG_FILE_CBFS)-compression := $(CBFS_COMPRESS_FLAG)
+cbfs-files-y += $(TZQTI_CFG_FILE_CBFS)
+
+################################################################################
+TZAC_CFG_FILE := $(CALYPSO_BLOB)/ac_policy/tz_ac_config.elf
+TZAC_CFG_FILE_CBFS := $(CONFIG_CBFS_PREFIX)/tzac_cfg
+$(TZAC_CFG_FILE_CBFS)-file := $(TZAC_CFG_FILE)
+$(TZAC_CFG_FILE_CBFS)-type := payload
+$(TZAC_CFG_FILE_CBFS)-compression := $(CBFS_COMPRESS_FLAG)
+cbfs-files-y += $(TZAC_CFG_FILE_CBFS)
+
+################################################################################
+HYPAC_CFG_FILE := $(CALYPSO_BLOB)/ac_policy/hyp_ac_config.elf
+HYPAC_CFG_FILE_CBFS := $(CONFIG_CBFS_PREFIX)/hypac_cfg
+$(HYPAC_CFG_FILE_CBFS)-file := $(HYPAC_CFG_FILE)
+$(HYPAC_CFG_FILE_CBFS)-type := payload
+$(HYPAC_CFG_FILE_CBFS)-compression := $(CBFS_COMPRESS_FLAG)
+cbfs-files-y += $(HYPAC_CFG_FILE_CBFS)
+
+endif # ifeq ($(CONFIG_ARM64_USE_SECURE_OS),y)
+################################################################################
+ifeq ($(CONFIG_QC_APDP_ENABLE),y)
+
+APDP_FILE := $(CALYPSO_BLOB)/qtee/apdp.mbn
+APDP_CBFS := $(CONFIG_CBFS_PREFIX)/apdp
+$(APDP_CBFS)-file := $(APDP_FILE)
+$(APDP_CBFS)-type := payload
+$(APDP_CBFS)-compression := $(CBFS_COMPRESS_FLAG)
+cbfs-files-y += $(APDP_CBFS)
+
+################################################################################
+# Rule to create apdp_meta from apdp.mbn
+# This rule depends on apdp.mbn being built and the extractor script existing.
+$(obj)/mainboard/$(MAINBOARDDIR)/apdp_meta: $(CALYPSO_BLOB)/qtee/apdp.mbn util/qualcomm/elf_segment_extractor.py
+	@echo "Extracting ELF headers and hash table segment from $< to $@"
+	@util/qualcomm/elf_segment_extractor.py --eh --pht --hashtable $< $@
+
+APDP_META_FILE := $(obj)/mainboard/$(MAINBOARDDIR)/apdp_meta
+APDP_META_CBFS := $(CONFIG_CBFS_PREFIX)/apdp_meta
+$(APDP_META_CBFS)-file := $(APDP_META_FILE)
+$(APDP_META_CBFS)-type := raw
+$(APDP_META_CBFS)-compression := $(CBFS_COMPRESS_FLAG)
+cbfs-files-y += $(APDP_META_CBFS)
+
+endif # ifeq ($(CONFIG_QC_APDP_ENABLE),y)
+################################################################################
+ifeq ($(CONFIG_QC_RAMDUMP_ENABLE),y)
+
+RAMDUMP_FILE := $(CALYPSO_BLOB)/boot/XblRamdump.elf
+RAMDUMP_CBFS := $(CONFIG_CBFS_PREFIX)/ramdump
+$(RAMDUMP_CBFS)-file := $(RAMDUMP_FILE)
+$(RAMDUMP_CBFS)-type := stage
+$(RAMDUMP_CBFS)-compression := $(CBFS_PRERAM_COMPRESS_FLAG)
+cbfs-files-y += $(RAMDUMP_CBFS)
+
+################################################################################
+# Rule to create ramdump_meta from XblRamdump.elf
+# This rule depends on XblRamdump.elf being built and the extractor script existing.
+$(obj)/mainboard/$(MAINBOARDDIR)/ramdump_meta: $(CALYPSO_BLOB)/boot/XblRamdump.elf util/qualcomm/elf_segment_extractor.py
+	@echo "Extracting ELF headers and hash table segment from $< to $@"
+	@util/qualcomm/elf_segment_extractor.py --eh --pht --hashtable $< $@
+
+RAMDUMP_META_FILE := $(obj)/mainboard/$(MAINBOARDDIR)/ramdump_meta
+RAMDUMP_META_CBFS := $(CONFIG_CBFS_PREFIX)/ramdump_meta
+$(RAMDUMP_META_CBFS)-file := $(RAMDUMP_META_FILE)
+$(RAMDUMP_META_CBFS)-type := raw
+$(RAMDUMP_META_CBFS)-compression := $(CBFS_COMPRESS_FLAG)
+cbfs-files-y += $(RAMDUMP_META_CBFS)
+
+endif # ifeq ($(CONFIG_QC_RAMDUMP_ENABLE),y)
+
+endif # ifeq ($(CONFIG_USE_QC_BLOBS),y)
+
+endif # ifeq ($(CONFIG_QC_BLOBS_UPSTREAM),y)
+endif # ifeq ($(CONFIG_SOC_QUALCOMM_CALYPSO_BASE),y)
diff --git a/src/soc/qualcomm/calypso/bootblock.c b/src/soc/qualcomm/calypso/bootblock.c
new file mode 100644
index 0000000000..ce000dbc40
--- /dev/null
+++ b/src/soc/qualcomm/calypso/bootblock.c
@@ -0,0 +1,15 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <bootblock_common.h>
+#include <soc/mmu.h>
+
+void bootblock_soc_early_init(void)
+{
+	if (!CONFIG(COMPRESS_BOOTBLOCK))
+		soc_mmu_init();
+}
+
+void bootblock_soc_init(void)
+{
+	/* Placeholder */
+}
diff --git a/src/soc/qualcomm/calypso/cbmem.c b/src/soc/qualcomm/calypso/cbmem.c
new file mode 100644
index 0000000000..f7c3f06fc3
--- /dev/null
+++ b/src/soc/qualcomm/calypso/cbmem.c
@@ -0,0 +1,10 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <cbmem.h>
+#include <console/console.h>
+
+uintptr_t cbmem_top_chipset(void)
+{
+	printk(BIOS_ERR, "%s: Update CBMEM TOP address.\n", __func__);
+	return (uintptr_t)NULL;
+}
diff --git a/src/soc/qualcomm/calypso/clock.c b/src/soc/qualcomm/calypso/clock.c
new file mode 100644
index 0000000000..9a4b16d810
--- /dev/null
+++ b/src/soc/qualcomm/calypso/clock.c
@@ -0,0 +1,18 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <soc/clock.h>
+
+void clock_configure_qspi(uint32_t hz)
+{
+	/* placeholder */
+}
+
+void clock_enable_qup(int qup)
+{
+	/* placeholder */
+}
+
+void clock_configure_dfsr(int qup)
+{
+	/* placeholder */
+}
diff --git a/src/soc/qualcomm/calypso/cpucp_load_reset.c b/src/soc/qualcomm/calypso/cpucp_load_reset.c
new file mode 100644
index 0000000000..03c8f5c7cd
--- /dev/null
+++ b/src/soc/qualcomm/calypso/cpucp_load_reset.c
@@ -0,0 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <soc/cpucp.h>
+
+void cpucp_fw_load_reset(void)
+{
+	/* Placeholder */
+}
diff --git a/src/soc/qualcomm/calypso/decompressor.c b/src/soc/qualcomm/calypso/decompressor.c
new file mode 100644
index 0000000000..12a3bac50b
--- /dev/null
+++ b/src/soc/qualcomm/calypso/decompressor.c
@@ -0,0 +1,9 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <bootblock_common.h>
+#include <soc/mmu.h>
+
+void decompressor_soc_init(void)
+{
+	soc_mmu_init();
+}
diff --git a/src/soc/qualcomm/calypso/include/soc/addressmap.h b/src/soc/qualcomm/calypso/include/soc/addressmap.h
new file mode 100644
index 0000000000..efabd6e059
--- /dev/null
+++ b/src/soc/qualcomm/calypso/include/soc/addressmap.h
@@ -0,0 +1,69 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef __SOC_QUALCOMM_CALYPSO_ADDRESS_MAP_H__
+#define __SOC_QUALCOMM_CALYPSO_ADDRESS_MAP_H__
+
+#include <stdint.h>
+#include <types.h>
+
+/* TODO: update as per datasheet */
+#define AOSS_CC_BASE			0x0C2A0000
+#define QSPI_BASE			0x088DC000
+#define TLMM_TILE_BASE			0x0F100000
+#define GCC_BASE			0x00100000
+#define NCC0_BASE			0x19A30000
+#define GCC_QUPV3_WRAP0_BASE		0x142004
+#define GCC_QUPV3_WRAP1_BASE		0x118004
+#define GCC_QUPV3_WRAP2_BASE		0x11e004
+
+/* CALPYSO QSPI GPIO PINS */
+#define QSPI_CS				GPIO(0)
+#define QSPI_DATA_0			GPIO(0)
+#define QSPI_DATA_1			GPIO(0)
+#define QSPI_CLK			GPIO(0)
+
+#define GPIO_FUNC_QSPI_DATA_0		0
+#define GPIO_FUNC_QSPI_DATA_1		0
+#define GPIO_FUNC_QSPI_CLK		0
+
+/* QUP SERIAL ENGINE BASE ADDRESSES */
+/* QUPV3_0 */
+#define QUP_SERIAL0_BASE		0x00B80000
+#define QUP_SERIAL1_BASE		0x00B84000
+#define QUP_SERIAL2_BASE		0x00B88000
+#define QUP_SERIAL3_BASE		0x00B8C000
+#define QUP_SERIAL4_BASE		0x00B90000
+#define QUP_SERIAL5_BASE		0x00B94000
+#define QUP_SERIAL6_BASE		0x00B98000
+#define QUP_SERIAL7_BASE		0x00B9C000
+#define QUP_WRAP0_BASE			0x00BC0000
+#define QUP_0_GSI_BASE			0x00B04000
+
+/* QUPV3_1 */
+#define QUP_SERIAL8_BASE		0x00A80000
+#define QUP_SERIAL9_BASE		0x00A84000
+#define QUP_SERIAL10_BASE		0x00A88000
+#define QUP_SERIAL11_BASE		0x00A8C000
+#define QUP_SERIAL12_BASE		0x00A90000
+#define QUP_SERIAL13_BASE		0x00A94000
+#define QUP_SERIAL14_BASE		0x00A98000
+#define QUP_SERIAL15_BASE		0x00A9C000
+#define QUP_WRAP1_BASE			0x00AC0000
+#define QUP_1_GSI_BASE			0x00A04000
+
+/* QUPV3_2 */
+#define QUP_SERIAL16_BASE		0x00880000
+#define QUP_SERIAL17_BASE		0x00884000
+#define QUP_SERIAL18_BASE		0x00888000
+#define QUP_SERIAL19_BASE		0x0088C000
+#define QUP_SERIAL20_BASE		0x00890000
+#define QUP_SERIAL21_BASE		0x00894000
+#define QUP_SERIAL22_BASE		0x00898000
+#define QUP_SERIAL23_BASE		0x0089C000
+#define QUP_WRAP2_BASE			0x008C0000
+#define QUP_2_GSI_BASE			0x00804000
+
+/* QUPV3_3 - Dummy Entry */
+#define QUP_WRAP3_BASE			0x007C0000
+
+#endif /*  __SOC_QUALCOMM_CALYPSO_ADDRESS_MAP_H__ */
diff --git a/src/soc/qualcomm/calypso/include/soc/clock.h b/src/soc/qualcomm/calypso/include/soc/clock.h
new file mode 100644
index 0000000000..3350ab6b26
--- /dev/null
+++ b/src/soc/qualcomm/calypso/include/soc/clock.h
@@ -0,0 +1,52 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <soc/addressmap.h>
+#include <types.h>
+#include <soc/clock_common.h>
+
+#ifndef __SOC_QUALCOMM_CALYPSO_CLOCK_H__
+#define __SOC_QUALCOMM_CALYPSO_CLOCK_H__
+
+#define SRC_XO_HZ		(19200 * KHz)
+
+/* TODO: update as per datasheet */
+void clock_configure_qspi(uint32_t hz);
+void clock_enable_qup(int qup);
+void clock_configure_dfsr(int qup);
+
+/* Does nothing */
+#define clock_reset_aop() do {} while (0)
+/* Does nothing */
+#define clock_reset_shrm() do {} while (0)
+
+enum clk_qup {
+	QUP_WRAP0_S0,
+	QUP_WRAP0_S1,
+	QUP_WRAP0_S2,
+	QUP_WRAP0_S3,
+	QUP_WRAP0_S4,
+	QUP_WRAP0_S5,
+	QUP_WRAP0_S6,
+	QUP_WRAP0_S7,
+	QUP_WRAP1_S0,
+	QUP_WRAP1_S1,
+	QUP_WRAP1_S2,
+	QUP_WRAP1_S3,
+	QUP_WRAP1_S4,
+	QUP_WRAP1_S5,
+	QUP_WRAP1_S6,
+	QUP_WRAP1_S7,
+	QUP_WRAP2_S0,
+	QUP_WRAP2_S1,
+	QUP_WRAP2_S2,
+	QUP_WRAP2_S3,
+	QUP_WRAP2_S4,
+	QUP_WRAP2_S5,
+	QUP_WRAP2_S6,
+	QUP_WRAP2_S7,
+};
+
+/* Subsystem Reset */
+static struct aoss *const aoss = (void *)AOSS_CC_BASE;
+
+#endif	// __SOC_QUALCOMM_CALYPSO_CLOCK_H__
diff --git a/src/soc/qualcomm/calypso/include/soc/cpucp.h b/src/soc/qualcomm/calypso/include/soc/cpucp.h
new file mode 100644
index 0000000000..ed22e02ec3
--- /dev/null
+++ b/src/soc/qualcomm/calypso/include/soc/cpucp.h
@@ -0,0 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef __SOC_QUALCOMM_CALYPSO_CPUCP_H__
+#define __SOC_QUALCOMM_CALYPSO_CPUCP_H__
+
+void cpucp_fw_load_reset(void);
+
+#endif  // __SOC_QUALCOMM_CALYPSO_CPUCP_H__
diff --git a/src/soc/qualcomm/calypso/include/soc/gpio.h b/src/soc/qualcomm/calypso/include/soc/gpio.h
new file mode 100644
index 0000000000..8954ebab1b
--- /dev/null
+++ b/src/soc/qualcomm/calypso/include/soc/gpio.h
@@ -0,0 +1,24 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef __SOC_QUALCOMM_CALYPSO_GPIO_H__
+#define __SOC_QUALCOMM_CALYPSO_GPIO_H__
+
+#include <types.h>
+#include <soc/addressmap.h>
+#include <soc/gpio_common.h>
+
+#define PIN(index, func1, func2, func3, func4, func5, func6) \
+	GPIO##index##_ADDR = (TLMM_TILE_BASE + ((index) * TLMM_GPIO_OFF_DELTA)), \
+	GPIO##index##_FUNC_##func1 = (1), \
+	GPIO##index##_FUNC_##func2 = (2), \
+	GPIO##index##_FUNC_##func3 = (3), \
+	GPIO##index##_FUNC_##func4 = (4), \
+	GPIO##index##_FUNC_##func5 = (5), \
+	GPIO##index##_FUNC_##func6 = (6)
+
+/* TODO: update as per datasheet */
+enum {
+	PIN(0, QUP0_SE0_L0, RES_2, RES_3, RES_4, RES_5, RES_6),
+};
+
+#endif /* __SOC_QUALCOMM_CALYPSO_GPIO_H__ */
diff --git a/src/soc/qualcomm/calypso/include/soc/mmu.h b/src/soc/qualcomm/calypso/include/soc/mmu.h
new file mode 100644
index 0000000000..115fdafe13
--- /dev/null
+++ b/src/soc/qualcomm/calypso/include/soc/mmu.h
@@ -0,0 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef __SOC_QUALCOMM_CALYPSO_MMU_H__
+#define __SOC_QUALCOMM_CALYPSO_MMU_H__
+
+void soc_mmu_init(void);
+
+#endif /* __SOC_QUALCOMM_CALYPSO_MMU_H__ */
diff --git a/src/soc/qualcomm/calypso/include/soc/qcom_qup_se.h b/src/soc/qualcomm/calypso/include/soc/qcom_qup_se.h
new file mode 100644
index 0000000000..d0313ca295
--- /dev/null
+++ b/src/soc/qualcomm/calypso/include/soc/qcom_qup_se.h
@@ -0,0 +1,53 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef __SOC_QUALCOMM_CALYPSO_QUP_SE_H__
+#define __SOC_QUALCOMM_CALYPSO_QUP_SE_H__
+
+#include <console/console.h>
+#include <device/mmio.h>
+#include <gpio.h>
+#include <soc/addressmap.h>
+#include <timer.h>
+#include <types.h>
+
+/* TODO: update as per datasheet */
+enum qup_se {
+	QUPV3_0_SE0,
+	QUPV3_0_SE1,
+	QUPV3_0_SE2,
+	QUPV3_0_SE3,
+	QUPV3_0_SE4,
+	QUPV3_0_SE5,
+	QUPV3_0_SE6,
+	QUPV3_0_SE7,
+	QUPV3_1_SE0,
+	QUPV3_1_SE1,
+	QUPV3_1_SE2,
+	QUPV3_1_SE3,
+	QUPV3_1_SE4,
+	QUPV3_1_SE5,
+	QUPV3_1_SE6,
+	QUPV3_1_SE7,
+	QUPV3_2_SE0,
+	QUPV3_2_SE1,
+	QUPV3_2_SE2,
+	QUPV3_2_SE3,
+	QUPV3_2_SE4,
+	QUPV3_2_SE5,
+	QUPV3_2_SE6,
+	QUPV3_2_SE7,
+	QUPV3_SE_MAX,
+};
+
+struct qup {
+	struct qup_regs *regs;
+	gpio_t pin[4];
+	u8 func[4];
+};
+
+extern struct qup qup[QUPV3_SE_MAX];
+
+/* TODO: update MAX_OFFSET_CFG_REG as per datasheet */
+#define MAX_OFFSET_CFG_REG		0x000001c4
+
+#endif /* __SOC_QUALCOMM_CALYPSO_QUP_SE_H__ */
diff --git a/src/soc/qualcomm/calypso/include/soc/shrm.h b/src/soc/qualcomm/calypso/include/soc/shrm.h
new file mode 100644
index 0000000000..8e3f7102eb
--- /dev/null
+++ b/src/soc/qualcomm/calypso/include/soc/shrm.h
@@ -0,0 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef __SOC_QUALCOMM_CALYPSO_SHRM_H__
+#define __SOC_QUALCOMM_CALYPSO_SHRM_H__
+
+void shrm_fw_load_reset(void);
+
+#endif  // __SOC_QUALCOMM_CALYPSO_SHRM_H__
diff --git a/src/soc/qualcomm/calypso/include/soc/uart.h b/src/soc/qualcomm/calypso/include/soc/uart.h
new file mode 100644
index 0000000000..362f8853fd
--- /dev/null
+++ b/src/soc/qualcomm/calypso/include/soc/uart.h
@@ -0,0 +1,9 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef __SOC_QUALCOMM_CALYPSO_UART_TX_H__
+#define __SOC_QUALCOMM_CALYPSO_UART_TX_H__
+
+/* TODO: update as per datasheet */
+#define UART_TX_PIN GPIO(0)
+
+#endif /* __SOC_QUALCOMM_CALYPSO_UART_TX_H__ */
diff --git a/src/soc/qualcomm/calypso/memlayout.ld b/src/soc/qualcomm/calypso/memlayout.ld
new file mode 100644
index 0000000000..5e29802cb3
--- /dev/null
+++ b/src/soc/qualcomm/calypso/memlayout.ld
@@ -0,0 +1,295 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <memlayout.h>
+#include <arch/header.ld>
+#include <soc/memlayout.h>
+
+/* Copied from Qualcomm previous generation SoC X1P42100 and need cleanup */
+
+/*
+ * The linker script below configures the memory layout for the Qualcomm X1P42100 SoC.
+ *
+ * The memory map and addressing scheme are implemented according to the official Qualcomm
+ * Hardware Reference Document (HRD) for this specific SoC.
+ *
+ * 0x10000000000 +----------------------------------------------------------+ <--------------
+ *               |                      dram_space_2                        | DRAM Space 2  ^
+ * 0x8800000000  +----------------------------------------------------------+ <---------    |
+ *               |         ... (Memory not mapped: Unavailable) ...         |  XXXXXXXXX    |
+ * 0x1000000000  +----------------------------------------------------------+ <---------    |
+ *               |                      dram_space_1                        | DRAM Space 1  |
+ * 0x880000000   +----------------------------------------------------------+ <---------    |
+ *               |         ... (Memory not mapped: Unavailable) ...         |  XXXXXXXXX    |
+ * 0x100000000   +----------------------------------------------------------+ <---------    |
+ *               |                 dram_smem (Shared Memory)                |      ^        |
+ * 0xFFE00000    +----------------------------------------------------------+      |        |
+ *               |                     dram_llcc_lpi                        |      |        |
+ * 0xFF800000    +----------------------------------------------------------+      |        |
+ *               |                       dram_acdb                          |      |        |
+ *               +----------------------------------------------------------+      |        |
+ *               |                ... Usable memory ...                     |      |        |
+ * 0xE69C0000    +----------------------------------------------------------+      |        |
+ *               |                     dram_display                         |      |        |
+ * 0xE4800000    +----------------------------------------------------------+      |        |
+ *               |                ... Usable memory ...                     |      |        |
+ * 0xD9632000    +----------------------------------------------------------+      |        |
+ *               |                       dram_ta                            |      |        |
+ * 0xD8632000    +----------------------------------------------------------+      |        |
+ *               |                 BL31 (ARM Trusted Firmware)              |      |        |
+ * 0xD856A000    +----------------------------------------------------------+      |        |
+ *               |                  dram_tz (TrustZone)                     |      |        |
+ * 0xD8000000    +----------------------------------------------------------+      |      DRAM
+ *               |               ... Usable memory ...                      |      |        |
+ * 0xD7800000    +----------------------------------------------------------+      |        |
+ *               |                 Linux Kernel Reserve                     |      |        |
+ * 0xC7800000    +----------------------------------------------------------+      |        |
+ *               |                ... Usable memory ...                     |      |        |
+ * 0xA1800000    +----------------------------------------------------------+      |        |
+ *               |                      RAMSTAGE                            | DRAM Space 0  |
+ * 0xA0800000    +----------------------------------------------------------+      |        |
+ *               |                 POSTRAM_CBFS_CACHE                       |      |        |
+ * 0x9F800000    +----------------------------------------------------------+      |        |
+ *               |                ... Usable memory ...                     |      |        |
+ * 0x91380000    +----------------------------------------------------------+      |        |
+ *               |                       dram_pil                           |      |        |
+ * 0x866C0000    +----------------------------------------------------------+      |        |
+ *               |                        CBMEM                             |      |        |
+ *               +----------------------------------------------------------+      |        |
+ *               |                ... Usable memory ...                     |      |        |
+ * 0x85F80000    +----------------------------------------------------------+      |        |
+ *               |                       dram_wlan                          |      |        |
+ * 0x85380000    +----------------------------------------------------------+      |        |
+ *               |                ... Usable memory ...                     |      |        |
+ * 0x82800000    +----------------------------------------------------------+      |        |
+ *               |                 dram_adsp_rpc_heap                       |      |        |
+ * 0x82000000    +----------------------------------------------------------+      |        |
+ *               |                   dram_tz_static                         |      |        |
+ * 0x81F00000    +----------------------------------------------------------+      |        |
+ *               |                       dram_pdp                           |      |        |
+ * 0x81E00000    +----------------------------------------------------------+      |        |
+ *               |                  ... Usable memory ...                   |      |        |
+ * 0x81CF4000    +----------------------------------------------------------+      |        |
+ *               |                       dram_dc_log                        |      |        |
+ * 0x81CE4000    +----------------------------------------------------------+      |        |
+ *               |                       dram_tme_log                       |      |        |
+ * 0x81CE0000    +----------------------------------------------------------+      |        |
+ *               |                  dram_tme_crashdump                      |      |        |
+ * 0x81CA0000    +----------------------------------------------------------+      |        |
+ *               |                   dram_aop_config                        |      |        |
+ * 0x81C80000    +----------------------------------------------------------+      |        |
+ *               |                   dram_aop_cmd_db                        |      |        |
+ * 0x81C60000    +----------------------------------------------------------+      |        |
+ *               |                       dram_aop                           |      |        |
+ * 0x81C00000    +----------------------------------------------------------+      |        |
+ *               |                     dram_ramdump                         |      |        |
+ * 0x81A40000    +----------------------------------------------------------+      |        |
+ *               |                     dram_xbl_log                         |      |        |
+ * 0x81A00000    +----------------------------------------------------------+      |        |
+ *               |                ... Usable memory ...                     |      |        |
+ * 0x815A0000    +----------------------------------------------------------+      |        |
+ *               |                      dram_cpucp                          |      |        |
+ * 0x80E00000    +----------------------------------------------------------+      |        |
+ *               |                      dram_ncc                            |      |        |
+ * 0x80A00000    +----------------------------------------------------------+      |        |
+ *               |              postram_dma_coherent_dram                   |      |        |
+ * 0x80004000    +----------------------------------------------------------+      |        |
+ *               |                    POSTRAM STACK                         |      v        v
+ * 0x80000000    +----------------------------------------------------------+ <--------------
+ *               |         ... (Memory not mapped: Unavailable) ...         | XXXXXXXXX
+ * 0x24060000    +----------------------------------------------------------+ <---------
+ *               |                         shrm                             |    SHRM
+ * 0x24040000    +----------------------------------------------------------+ <---------
+ *               |         ... (Memory not mapped: Unavailable) ...         | XXXXXXXXX
+ * 0x1CB40000    +----------------------------------------------------------+ <---------
+ *               |                         CPUCP                            |
+ * 0x1CB00000    +----------------------------------------------------------+ <---------
+ *               |         ... (Memory not mapped: Unavailable) ...         | XXXXXXXXX
+ * 0x14A80000    +----------------------------------------------------------+ <---------
+ *               |                    auth_metadata                         |      ^
+ * 0x14A7E000    +----------------------------------------------------------+      |
+ *               |                     debug_policy                         |      |
+ * 0x14A7D000    +----------------------------------------------------------+      |
+ *               |                ... Usable memory ...                     |      |
+ * 0x14A59000    +----------------------------------------------------------+      |
+ *               |         OVERLAP_DECOMPRESSOR_VERSTAGE_ROMSTAGE           |      |
+ * 0x14A38000    +----------------------------------------------------------+      |
+ *               |                 PRERAM_CBMEM_CONSOLE                     |      |
+ * 0x14A30000    +----------------------------------------------------------+      |
+ *               |                ... Usable memory ...                     |      |
+ * 0x14A1A000    +----------------------------------------------------------+      |
+ *               |                        CPR                               |      |
+ * 0x14A17000    +----------------------------------------------------------+      |
+ *               |                       qclib                              |      |
+ * 0x14897000    +----------------------------------------------------------+      |
+ *               |                ... Usable memory ...                     |      |
+ * 0x14891000    +----------------------------------------------------------+      |
+ *               |                  apdp_ramdump_meta                       |      |
+ * 0x14890000    +----------------------------------------------------------+      |
+ *               |                    aop_blob_meta                         |      |
+ * 0x1488C000    +----------------------------------------------------------+      |
+ *               |                    qc_blob_meta                          |      |
+ * 0x14888000    +----------------------------------------------------------+      |
+ *               |                    ddr_training                          |      |
+ * 0x14878000    +----------------------------------------------------------+      |
+ *               |               dtb (Device Tree Blob)                     |      |
+ * 0x14870000    +----------------------------------------------------------+      |
+ *               |                dcb (DDR Config Block)                    |      |
+ * 0x14862000    +----------------------------------------------------------+      |
+ *               |                ... Usable memory ...                     |      |
+ * 0x14860C00    +----------------------------------------------------------+      |
+ *               |                     FMAP_CACHE                           |      |
+ * 0x14861800    +----------------------------------------------------------+    BSRAM
+ *               |                    CBFS_MCACHE                           |      |
+ * 0x1485C000    +----------------------------------------------------------+      |
+ *               |                  qclib_serial_log                        |      |
+ * 0x1485B000    +----------------------------------------------------------+      |
+ *               |                ... Usable memory ...                     |      |
+ * 0x14859000    +----------------------------------------------------------+      |
+ *               |               preram_dma_coherent_dram                   |      |
+ * 0x14857000    +----------------------------------------------------------+      |
+ *               |                    VBOOT2_WORK                           |      |
+ * 0x14854000    +----------------------------------------------------------+      |
+ *               |                    PRERAM STACK                          |      |
+ * 0x14850000    +----------------------------------------------------------+      |
+ *               |             TTB (Translation Table Base)                 |      |
+ * 0x14842000    +----------------------------------------------------------+      |
+ *               |                     TIMESTAMP                            |      |
+ * 0x14841C00    +----------------------------------------------------------+      |
+ *               |                 PRERAM_CBFS_CACHE                        |      |
+ * 0x14828000    +----------------------------------------------------------+      |
+ *               |                     BOOTBLOCK                            |      |
+ * 0x14819000    +----------------------------------------------------------+      |
+ *               |                ... Usable memory ...                     |      |
+ * 0x14815000    +----------------------------------------------------------+      |
+ *               |                   pbl_timestamps                         |      v
+ * 0x14800000    +----------------------------------------------------------+ <---------
+ *               |              ... (Large Address Gap) ...                 |
+ *               +----------------------------------------------------------+
+ *               |                ... Usable memory ...                     |
+ * 0x146AC000    +----------------------------------------------------------+ <---------
+ *               |                 WATCHDOG_TOMBSTONE                       |      ^
+ * 0x146ABFFC    +----------------------------------------------------------+      |
+ *               |                   ddr_information                        |      |
+ * 0x146ABFE8    +----------------------------------------------------------+      |
+ *               |                     shared_imem                          |      |
+ * 0x146AA000    +----------------------------------------------------------+      |
+ *               |                      aop_imem                            |      |
+ * 0x146A8000    +----------------------------------------------------------+    SSRAM
+ *               |                   qdss_usb_trace                         |      |
+ * 0x146A6000    +----------------------------------------------------------+      |
+ *               |                ... Usable memory ...                     |      |
+ * 0x146A5000    +----------------------------------------------------------+      |
+ *               |                      AOP SDI                             |      |
+ * 0x14699000    +----------------------------------------------------------+      |
+ *               |                 Reserved for QSEE                        |      v
+ * 0x14680000    +----------------------------------------------------------+ <---------
+ *               |         ... (Memory not mapped: Unavailable) ...         | XXXXXXXXX
+ * 0x0B100000    +----------------------------------------------------------+ <---------
+ *               |                ... Usable memory ...                     |      ^
+ * 0x0B0E8000    +----------------------------------------------------------+      |
+ *               |                    aop_data_ram                          |      |
+ * 0x0B0E0000    +----------------------------------------------------------+   AOP SRAM
+ *               |                ... Usable memory ...                     |      |
+ * 0x0B018000    +----------------------------------------------------------+      |
+ *               |                    aop_code_ram                          |      v
+ * 0x0B000000    +----------------------------------------------------------+ <---------
+ *
+ */
+
+SECTIONS
+{
+	AOPSRAM_START(0x0B000000)
+	REGION(aop_code_ram, 0x0B000000, 0x18000, 4K)
+	REGION(aop_data_ram, 0x0B0E0000, 0x8000, 4K)
+	AOPSRAM_END(0x0B100000)
+
+	SSRAM_START(0x14680000)
+	REGION(qsee, 0x14680000, 100K, 4K)
+	REGION(aop_sdi, 0x14699000, 48K, 4K)
+	REGION(qdss_usb_trace, 0x146A6000, 8K, 4K)
+	REGION(aop_imem, 0x146A8000, 8K, 4K)
+	REGION(shared_imem, 0x146AA000, 0x1000, 4K)
+	REGION(ddr_information, 0x146ABFE8, 16, 8)
+	WATCHDOG_TOMBSTONE(0x146ABFFC, 4)
+	SSRAM_END(0x146AC000)
+
+	BSRAM_START(0x14800000)
+	REGION(pbl_timestamps, 0x14800000, 84K, 4K)
+	BOOTBLOCK(0x14819000, 60K)
+	PRERAM_CBFS_CACHE(0x14828000, 103K)
+	TIMESTAMP(0x14841C00, 1K)
+	TTB(0x14842000, 56K)
+	PRERAM_STACK(0x14850000, 16K)
+	VBOOT2_WORK(0x14854000, 12K)
+	PRERAM_DMA_COHERENT(0x14858000, 8K)
+	REGION(qclib_serial_log, 0x1485B000, 4K, 4K)
+	CBFS_MCACHE(0x1485C000,22K)
+	FMAP_CACHE(0x14861800, 2K)
+	REGION(dcb, 0x14862000, 56K, 4K)
+	REGION(dtb, 0x14870000, 32K, 4K)
+	REGION(ddr_training, 0x14878000, 64K, 4K)
+	REGION(qc_blob_meta, 0x14888000, 16K, 4K)
+	REGION(aop_blob_meta, 0x1488c000, 16K, 4K)
+	REGION(apdp_ramdump_meta, 0x14890000, 4K, 4K)
+	REGION(qclib, 0x14897000, 1536K, 4K)
+	REGION(cpr_settings, 0x14A17000, 12K, 4K)
+	PRERAM_CBMEM_CONSOLE(0x14A30000, 32K)
+	OVERLAP_DECOMPRESSOR_VERSTAGE_ROMSTAGE(0x14A38000, 132K)
+	REGION(debug_policy, 0x14A7D000 , 4K, 4K)
+	REGION(auth_metadata, 0x14A7E000, 8K, 4K)
+	BSRAM_END(0x14A80000)
+
+	REGION(cpucp, 0x1CB00000, 256K , 4K)
+
+	REGION(shrm, 0x24040000, 128K , 4K)
+
+	DRAM_START(0x80000000)
+	POSTRAM_STACK(0x80000000, 32K)
+	POSTRAM_DMA_COHERENT(0x8000C000, 16K)
+	REGION(dram_ncc, 0x80A00000, 0x400000, 4K)
+	REGION(dram_cpucp, 0x80E00000, 0x7A0000, 4K)
+
+	REGION(dram_xbl_log, 0x81A00000, 0x40000, 4K)
+	REGION(dram_ramdump, 0x81A40000, 0x1C0000, 4K)
+
+	REGION(dram_aop, 0x81C00000, 0x60000, 4K)
+	REGION(dram_aop_cmd_db, 0x81C60000, 0x20000, 4K)
+	REGION(dram_aop_config, 0x81C80000, 0x20000, 4K)
+	REGION(dram_tme_crashdump, 0x81CA0000, 0x40000, 4K)
+	REGION(dram_tme_log, 0x81CE0000, 0x4000, 4K)
+	REGION(dram_dc_log, 0x81CE4000, 0x10000, 4K)
+
+	REGION(dram_pdp, 0x81E00000, 0x100000, 4K)
+	REGION(dram_tz_static, 0x81F00000, 0x100000, 4K)
+	REGION(dram_adsp_rpc_heap, 0x82000000, 0x800000, 4K)
+	REGION(dram_wlan, 0x85380000, 0xC00000, 4K)
+	REGION(dram_pil, 0x866C0000, 0xACC0000, 4K)
+
+	POSTRAM_CBFS_CACHE(0x9F800000, 16M)
+	RAMSTAGE(0xA0800000, 16M)
+	REGION(dram_tz, 0xD8000000, 0x56A000, 4K)
+	BL31(0xD856A000, 800K)
+	REGION(dram_ta, 0xD8632000, 0x1000000, 4K)
+	REGION(dram_display, 0xE4800000, 0x21C0000, 4K)
+	REGION(dram_llcc_lpi, 0xFF800000, 0x600000, 4K)
+	REGION(dram_smem, 0xFFE00000, 0x200000, 4K)
+	DRAM_END(0x100000000)
+
+	/*
+	 * Define the address range limits for fragmented DRAM regions.
+	 *
+	 * These regions, `dram_space_1` and `dram_space_2`, are used to map physical
+	 * memory beyond the initial `_dram` region. The MMU configuration logic in
+	 * `mmu.c` uses `REGION_SIZE()` to dynamically size these ranges based on the
+	 * total system DRAM capacity, which is determined by the QCLib.
+	 *
+	 * Example for a 16GB DRAM system:
+	 * - `_dram` (2GB):          0x80000000 - 0x100000000
+	 * - `_dram_space_1` (14GB): 0x880000000 - 0x440000000 (0x880000000 + 14GB)
+	 *
+	 * Note: The example memory addresses are for illustration and depend on the
+	 * platform's specific memory map.
+	 */
+	REGION(dram_space_1, 0x880000000, 0x780000000, 4K)
+	REGION(dram_space_2, 0x8800000000, 0x7800000000, 4K)
+}
diff --git a/src/soc/qualcomm/calypso/mmu.c b/src/soc/qualcomm/calypso/mmu.c
new file mode 100644
index 0000000000..9279d8e1a0
--- /dev/null
+++ b/src/soc/qualcomm/calypso/mmu.c
@@ -0,0 +1,21 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <symbols.h>
+#include <arch/mmu.h>
+#include <arch/cache.h>
+#include <soc/mmu.h>
+#include <soc/mmu_common.h>
+#include <soc/symbols_common.h>
+
+void soc_mmu_init(void)
+{
+	mmu_init();
+
+	mmu_config_range((void *)(4 * KiB), ((4UL * GiB) - (4 * KiB)), DEV_MEM);
+	mmu_config_range((void *)_ssram, REGION_SIZE(ssram), CACHED_RAM);
+	mmu_config_range((void *)_bsram, REGION_SIZE(bsram), CACHED_RAM);
+	mmu_config_range((void *)_dma_coherent, REGION_SIZE(dma_coherent),
+			 UNCACHED_RAM);
+
+	mmu_enable();
+}
diff --git a/src/soc/qualcomm/calypso/pcie.c b/src/soc/qualcomm/calypso/pcie.c
new file mode 100644
index 0000000000..3e38450c4b
--- /dev/null
+++ b/src/soc/qualcomm/calypso/pcie.c
@@ -0,0 +1,30 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <soc/pcie.h>
+
+/* Enable PIPE clock */
+int qcom_dw_pcie_enable_pipe_clock(void)
+{
+	/* placeholder */
+
+	return 0;
+}
+
+/* Enable controller specific clocks */
+int32_t qcom_dw_pcie_enable_clock(void)
+{
+	/* placeholder */
+
+	return 0;
+}
+
+/* Turn on NVMe */
+void gcom_pcie_power_on_ep(void)
+{
+	/* placeholder */
+}
+
+void gcom_pcie_get_config(struct qcom_pcie_cntlr_t *host_cfg)
+{
+	/* placeholder */
+}
diff --git a/src/soc/qualcomm/calypso/qclib.c b/src/soc/qualcomm/calypso/qclib.c
new file mode 100644
index 0000000000..45dbcc0e43
--- /dev/null
+++ b/src/soc/qualcomm/calypso/qclib.c
@@ -0,0 +1,17 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <assert.h>
+#include <soc/qclib_common.h>
+
+__weak int qclib_mainboard_override(struct qclib_cb_if_table *table) { return 0; }
+
+int qclib_soc_override(struct qclib_cb_if_table *table)
+{
+	/* hook for platform specific policy configuration */
+	if (qclib_mainboard_override(table)) {
+		printk(BIOS_ERR, "qclib_mainboard_override failed\n");
+		return -1;
+	}
+
+	return 0;
+}
diff --git a/src/soc/qualcomm/calypso/qcom_qup_se.c b/src/soc/qualcomm/calypso/qcom_qup_se.c
new file mode 100644
index 0000000000..df1335c72a
--- /dev/null
+++ b/src/soc/qualcomm/calypso/qcom_qup_se.c
@@ -0,0 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <soc/qcom_qup_se.h>
+
+/* TODO: update QUP entries as per datasheet */
+struct qup qup[QUPV3_SE_MAX] = {
+
+};
diff --git a/src/soc/qualcomm/calypso/soc.c b/src/soc/qualcomm/calypso/soc.c
new file mode 100644
index 0000000000..47278fd40c
--- /dev/null
+++ b/src/soc/qualcomm/calypso/soc.c
@@ -0,0 +1,75 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <device/device.h>
+#include <soc/mmu.h>
+#include <soc/mmu_common.h>
+#include <soc/symbols_common.h>
+#include <soc/pcie.h>
+#include <soc/clock.h>
+#include <soc/cpucp.h>
+#include <program_loading.h>
+
+static struct device_operations pci_domain_ops = {
+	.read_resources = noop_read_resources,
+	.set_resources = noop_set_resources
+};
+
+static void soc_read_resources(struct device *dev)
+{
+	/* placeholder */
+}
+
+static void qtee_fw_config_load(void)
+{
+	if (!CONFIG(ARM64_USE_SECURE_OS))
+		return;
+
+	struct prog devcfg_tz = PROG_INIT(PROG_PAYLOAD,
+					CONFIG_CBFS_PREFIX"/tzoem_cfg");
+	if (!selfload(&devcfg_tz))
+		die("devcfg_tz load failed");
+
+	struct prog tzqti_cfg = PROG_INIT(PROG_PAYLOAD,
+					CONFIG_CBFS_PREFIX"/tzqti_cfg");
+	if (!selfload(&tzqti_cfg))
+		die("tzqti_cfg load failed");
+
+	struct prog tzac_cfg = PROG_INIT(PROG_PAYLOAD,
+					CONFIG_CBFS_PREFIX"/tzac_cfg");
+	if (!selfload(&tzac_cfg))
+		die("tzac_cfg load failed");
+
+	struct prog hypac_cfg = PROG_INIT(PROG_PAYLOAD,
+					CONFIG_CBFS_PREFIX"/hypac_cfg");
+	if (!selfload(&hypac_cfg))
+		die("hypac_cfg load failed");
+}
+
+static void soc_init(struct device *dev)
+{
+	cpucp_fw_load_reset();
+	qtee_fw_config_load();
+}
+
+static struct device_operations soc_ops = {
+	.read_resources = soc_read_resources,
+	.set_resources = noop_set_resources,
+	.init = soc_init,
+};
+
+static void enable_soc_dev(struct device *dev)
+{
+	/* Set the operations if it is a special bus type */
+	if (dev->path.type == DEVICE_PATH_DOMAIN) {
+		if (mainboard_needs_pcie_init())
+			dev->ops = &pci_domain_ops;
+		else
+			printk(BIOS_DEBUG, "Skip setting PCIe ops\n");
+	} else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER)
+		dev->ops = &soc_ops;
+}
+
+struct chip_operations soc_qualcomm_calypso_ops = {
+	.name = "Calypso",
+	.enable_dev = enable_soc_dev,
+};

From dde131c555ec553d28f144a3411de5994887cba2 Mon Sep 17 00:00:00 2001
From: Subrata Banik <subratabanik@google.com>
Date: Thu, 26 Mar 2026 20:43:42 +0000
Subject: [PATCH 3849/3886] mb/google/mensa: Add initial support for Mensa

This commit introduces basic support for the google/mensa mainboard,
based on the Qualcomm Calypso SoC.

Changes:

- Add placeholder mainboard callbacks to enable control flow from /lib
  and Qualcomm SoC code.
- Populate the bluey mainboard directory with a copy of the bluey
  codebase, removing SoC/mainboard-specific implementations.

This provides a minimal working build for google/mensa, allowing
upstream builders to compile the mainboard. This facilitates easier
verification of subsequent changes.

BUG=b:4966500890
TEST=Successfully built google/mensa with Qualcomm Calypso SoC.

Change-Id: Id30a766c1bc6b37a6d35ba933c207951ab83f4d1
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91893
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
---
 src/mainboard/google/mensa/Kconfig            | 97 +++++++++++++++++++
 src/mainboard/google/mensa/Kconfig.name       |  6 ++
 src/mainboard/google/mensa/Makefile.mk        | 13 +++
 src/mainboard/google/mensa/board.h            | 15 +++
 src/mainboard/google/mensa/board_info.txt     |  6 ++
 src/mainboard/google/mensa/boardid.c          | 17 ++++
 src/mainboard/google/mensa/bootblock.c        | 18 ++++
 src/mainboard/google/mensa/chromeos-nogsc.fmd | 45 +++++++++
 src/mainboard/google/mensa/chromeos.c         | 37 +++++++
 src/mainboard/google/mensa/chromeos.fmd       | 44 +++++++++
 src/mainboard/google/mensa/devicetree.cb      |  6 ++
 src/mainboard/google/mensa/mainboard.c        | 25 +++++
 src/mainboard/google/mensa/reset.c            | 12 +++
 src/mainboard/google/mensa/romstage.c         | 13 +++
 14 files changed, 354 insertions(+)
 create mode 100644 src/mainboard/google/mensa/Kconfig
 create mode 100644 src/mainboard/google/mensa/Kconfig.name
 create mode 100644 src/mainboard/google/mensa/Makefile.mk
 create mode 100644 src/mainboard/google/mensa/board.h
 create mode 100644 src/mainboard/google/mensa/board_info.txt
 create mode 100644 src/mainboard/google/mensa/boardid.c
 create mode 100644 src/mainboard/google/mensa/bootblock.c
 create mode 100644 src/mainboard/google/mensa/chromeos-nogsc.fmd
 create mode 100644 src/mainboard/google/mensa/chromeos.c
 create mode 100644 src/mainboard/google/mensa/chromeos.fmd
 create mode 100644 src/mainboard/google/mensa/devicetree.cb
 create mode 100644 src/mainboard/google/mensa/mainboard.c
 create mode 100644 src/mainboard/google/mensa/reset.c
 create mode 100644 src/mainboard/google/mensa/romstage.c

diff --git a/src/mainboard/google/mensa/Kconfig b/src/mainboard/google/mensa/Kconfig
new file mode 100644
index 0000000000..e93de807bf
--- /dev/null
+++ b/src/mainboard/google/mensa/Kconfig
@@ -0,0 +1,97 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
+config BOARD_GOOGLE_MENSA_COMMON
+	def_bool n
+	select COMMON_CBFS_SPI_WRAPPER
+	# FIXME: keep ADB for development phase
+	select GBB_FLAG_ENABLE_ADB if VBOOT
+	select MAINBOARD_HAS_CHROMEOS
+	select SPI_FLASH
+	select SPI_FLASH_FORCE_4_BYTE_ADDR_MODE
+	select SPI_FLASH_INCLUDE_ALL_DRIVERS
+
+config BOARD_GOOGLE_BASEBOARD_MENSA
+	def_bool n
+	select BOARD_GOOGLE_MENSA_COMMON
+
+config BOARD_GOOGLE_MODEL_MENSA
+	def_bool n
+	select BOARD_GOOGLE_BASEBOARD_MENSA
+	select BOARD_ROMSIZE_KB_32768
+	select EC_GOOGLE_CHROMEEC_BATTERY_SOC_DYNAMIC
+	select MAINBOARD_HAS_CHROME_EC
+	select MAINBOARD_HAS_GOOGLE_TPM
+
+config BOARD_GOOGLE_MENSA
+	select BOARD_GOOGLE_MODEL_MENSA
+	select SOC_QUALCOMM_CALYPSO
+
+if BOARD_GOOGLE_MENSA_COMMON
+
+config MAINBOARD_DIR
+	default "google/mensa"
+
+config MAINBOARD_HAS_GOOGLE_TPM
+	bool
+	default n
+	select I2C_TPM
+	select MAINBOARD_HAS_TPM2
+	select TPM_GOOGLE_TI50
+	help
+	  Enable this option if your mainboard is equipped with Google TPM aka GSC.
+
+config MAINBOARD_HAS_CHROME_EC
+	bool
+	default n
+	select EC_GOOGLE_CHROMEEC
+	select EC_GOOGLE_CHROMEEC_RTC
+	select EC_GOOGLE_CHROMEEC_SPI
+	select EC_GOOGLE_CHROMEEC_SWITCHES if VBOOT
+	select RTC
+	help
+	  Enable this option if your mainboard is equipped with Chrome EC.
+
+config MAINBOARD_VENDOR
+	string
+	default "Google"
+
+config VBOOT
+	select VBOOT_ALWAYS_ENABLE_DISPLAY
+	select VBOOT_LID_SWITCH if MAINBOARD_HAS_CHROME_EC
+	select VBOOT_NO_BOARD_SUPPORT if !MAINBOARD_HAS_CHROME_EC
+	select VBOOT_VBNV_FLASH
+
+##########################################################
+#### Update below when adding a new derivative board. ####
+##########################################################
+
+config MAINBOARD_PART_NUMBER
+	default "Mensa" if BOARD_GOOGLE_MENSA
+
+config DRIVER_TPM_I2C_BUS
+	depends on I2C_TPM
+	hex
+	default 0x0 # TODO
+
+config DRIVER_TPM_I2C_ADDR
+	default 0x50
+
+config EC_GOOGLE_CHROMEEC_SPI_BUS
+	depends on EC_GOOGLE_CHROMEEC
+	hex
+	default 0x0 # TODO
+
+config MAINBOARD_GPIO_PIN_FOR_GSC_AP_INTERRUPT
+	depends on TPM_GOOGLE_TI50
+	int
+	default 0 # TODO
+	help
+	  This option specifies the GPIO pin number on the mainboard that is
+	  used for the interrupt line from the Google Security Chip (GSC) to the
+	  Application Processor (AP).
+
+config FMDFILE
+	default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/chromeos.fmd" if MAINBOARD_HAS_GOOGLE_TPM
+	default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/chromeos-nogsc.fmd"
+
+endif # BOARD_GOOGLE_MENSA_COMMON
diff --git a/src/mainboard/google/mensa/Kconfig.name b/src/mainboard/google/mensa/Kconfig.name
new file mode 100644
index 0000000000..fcc1a07329
--- /dev/null
+++ b/src/mainboard/google/mensa/Kconfig.name
@@ -0,0 +1,6 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
+comment "Mensa (Qualcomm Calypso)"
+
+config BOARD_GOOGLE_MENSA
+	bool "->  Mensa"
diff --git a/src/mainboard/google/mensa/Makefile.mk b/src/mainboard/google/mensa/Makefile.mk
new file mode 100644
index 0000000000..6018c9152a
--- /dev/null
+++ b/src/mainboard/google/mensa/Makefile.mk
@@ -0,0 +1,13 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
+all-y += boardid.c
+all-y += chromeos.c
+ifneq ($(CONFIG_MISSING_BOARD_RESET),y)
+all-y += reset.c
+endif
+
+bootblock-y += bootblock.c
+
+romstage-y += romstage.c
+
+ramstage-y += mainboard.c
diff --git a/src/mainboard/google/mensa/board.h b/src/mainboard/google/mensa/board.h
new file mode 100644
index 0000000000..973c375d97
--- /dev/null
+++ b/src/mainboard/google/mensa/board.h
@@ -0,0 +1,15 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef MAINBOARD_GOOGLE_MENSA_BOARD_H
+#define MAINBOARD_GOOGLE_MENSA_BOARD_H
+
+#include <assert.h>
+#include <gpio.h>
+
+/* TODO: update as per datasheet */
+#define GPIO_AP_EC_INT		GPIO(0)
+#define GPIO_GSC_AP_INT		GPIO(0)
+
+void setup_chromeos_gpios(void);
+
+#endif /* MAINBOARD_GOOGLE_MENSA_BOARD_H */
diff --git a/src/mainboard/google/mensa/board_info.txt b/src/mainboard/google/mensa/board_info.txt
new file mode 100644
index 0000000000..0ccc771ead
--- /dev/null
+++ b/src/mainboard/google/mensa/board_info.txt
@@ -0,0 +1,6 @@
+Vendor name: Google
+Board name: Mensa reference board with Calypso SoC
+Category: eval
+ROM protocol: SPI
+ROM socketed: n
+Flashrom support: y
diff --git a/src/mainboard/google/mensa/boardid.c b/src/mainboard/google/mensa/boardid.c
new file mode 100644
index 0000000000..b529ff1ec1
--- /dev/null
+++ b/src/mainboard/google/mensa/boardid.c
@@ -0,0 +1,17 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <boardid.h>
+
+uint32_t board_id(void)
+{
+	static uint32_t id = UNDEFINED_STRAPPING_ID;
+	/* Placeholder */
+	return id;
+}
+
+uint32_t sku_id(void)
+{
+	static uint32_t id = UNDEFINED_STRAPPING_ID;
+	/* Placeholder */
+	return id;
+}
diff --git a/src/mainboard/google/mensa/bootblock.c b/src/mainboard/google/mensa/bootblock.c
new file mode 100644
index 0000000000..cb641d8510
--- /dev/null
+++ b/src/mainboard/google/mensa/bootblock.c
@@ -0,0 +1,18 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <bootblock_common.h>
+#include <soc/qupv3_i2c_common.h>
+#include <soc/qcom_qup_se.h>
+#include <soc/qupv3_spi_common.h>
+#include "board.h"
+
+void bootblock_mainboard_init(void)
+{
+	setup_chromeos_gpios();
+
+	if (CONFIG(I2C_TPM))
+		i2c_init(CONFIG_DRIVER_TPM_I2C_BUS, I2C_SPEED_FAST); /* H1/TPM I2C */
+
+	if (CONFIG(EC_GOOGLE_CHROMEEC))
+		qup_spi_init(CONFIG_EC_GOOGLE_CHROMEEC_SPI_BUS, 1010 * KHz); /* EC SPI */
+}
diff --git a/src/mainboard/google/mensa/chromeos-nogsc.fmd b/src/mainboard/google/mensa/chromeos-nogsc.fmd
new file mode 100644
index 0000000000..cd3caa84f2
--- /dev/null
+++ b/src/mainboard/google/mensa/chromeos-nogsc.fmd
@@ -0,0 +1,45 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
+FLASH@0x0 CONFIG_ROM_SIZE {
+	WP_RO 8M {
+		RO_SECTION {
+			BOOTBLOCK 512K
+			FMAP 4K
+			COREBOOT(CBFS)
+			GBB 0x2f00
+			RO_FRID 0x100
+		}
+		RO_VPD(PRESERVE) 16K
+	}
+
+	RW_MISC 184K {
+		UNIFIED_MRC_CACHE(PRESERVE) 128K {
+			RECOVERY_MRC_CACHE 64K
+			RW_MRC_CACHE 64K
+		}
+		RW_ELOG(PRESERVE) 4K
+		RW_SHARED 4K {
+			SHARED_DATA
+		}
+		RW_VPD(PRESERVE) 32K
+		RW_NVRAM(PRESERVE) 16K
+	}
+
+	RW_SECTION_A 8704K {
+		VBLOCK_A 8K
+		FW_MAIN_A(CBFS)
+		RW_FWID_A 256
+	}
+
+	RW_SECTION_B 8704K {
+		VBLOCK_B 8K
+		FW_MAIN_B(CBFS)
+		RW_FWID_B 256
+	}
+
+	RW_LEGACY(CBFS)
+
+	RW_UNUSED 3840K
+
+	RW_CDT 256K
+}
diff --git a/src/mainboard/google/mensa/chromeos.c b/src/mainboard/google/mensa/chromeos.c
new file mode 100644
index 0000000000..646bd1164e
--- /dev/null
+++ b/src/mainboard/google/mensa/chromeos.c
@@ -0,0 +1,37 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <boot/coreboot_tables.h>
+#include <bootmode.h>
+#include <drivers/tpm/cr50.h>
+#include "board.h"
+
+void setup_chromeos_gpios(void)
+{
+	if (CONFIG(EC_GOOGLE_CHROMEEC))
+		gpio_input_pullup(GPIO_AP_EC_INT);
+
+	if (CONFIG(TPM_GOOGLE_TI50))
+		gpio_input_irq(GPIO_GSC_AP_INT, IRQ_TYPE_RISING_EDGE, GPIO_PULL_UP);
+}
+
+void fill_lb_gpios(struct lb_gpios *gpios)
+{
+	/* TODO: Add required GPIO after referring to the schematics */
+	const struct lb_gpio chromeos_gpios[] = {
+#if CONFIG(EC_GOOGLE_CHROMEEC)
+		{GPIO_AP_EC_INT.addr, ACTIVE_LOW, gpio_get(GPIO_AP_EC_INT),
+			"EC interrupt"},
+#endif
+#if CONFIG(TPM_GOOGLE_TI50)
+		{GPIO_GSC_AP_INT.addr, ACTIVE_HIGH, gpio_get(GPIO_GSC_AP_INT),
+			"TPM interrupt"},
+#endif
+	};
+
+	lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios));
+}
+
+int cr50_plat_irq_status(void)
+{
+	return gpio_irq_status(GPIO_GSC_AP_INT);
+}
diff --git a/src/mainboard/google/mensa/chromeos.fmd b/src/mainboard/google/mensa/chromeos.fmd
new file mode 100644
index 0000000000..b70b49811d
--- /dev/null
+++ b/src/mainboard/google/mensa/chromeos.fmd
@@ -0,0 +1,44 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
+FLASH@0x0 CONFIG_ROM_SIZE {
+	WP_RO 8M {
+		RO_SECTION {
+			BOOTBLOCK 512K
+			FMAP 4K
+			COREBOOT(CBFS)
+			GBB 0x2f00
+			RO_FRID 0x100
+		}
+		RO_GSCVD 8K
+		RO_VPD(PRESERVE) 16K
+	}
+
+	RW_MISC 184K {
+		UNIFIED_MRC_CACHE(PRESERVE) 128K {
+			RECOVERY_MRC_CACHE 64K
+			RW_MRC_CACHE 64K
+		}
+		RW_ELOG(PRESERVE) 4K
+		RW_SHARED 4K {
+			SHARED_DATA
+		}
+		RW_VPD(PRESERVE) 32K
+		RW_NVRAM(PRESERVE) 16K
+	}
+
+	RW_SECTION_A 8704K {
+		VBLOCK_A 8K
+		FW_MAIN_A(CBFS)
+		RW_FWID_A 256
+	}
+
+	RW_SECTION_B 8704K {
+		VBLOCK_B 8K
+		FW_MAIN_B(CBFS)
+		RW_FWID_B 256
+	}
+
+	RW_UNUSED 4M
+
+	RW_LEGACY(CBFS)
+}
diff --git a/src/mainboard/google/mensa/devicetree.cb b/src/mainboard/google/mensa/devicetree.cb
new file mode 100644
index 0000000000..d6a9df1ff8
--- /dev/null
+++ b/src/mainboard/google/mensa/devicetree.cb
@@ -0,0 +1,6 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
+chip soc/qualcomm/calypso
+	device cpu_cluster 0 on end
+	device domain 0 on end
+end
diff --git a/src/mainboard/google/mensa/mainboard.c b/src/mainboard/google/mensa/mainboard.c
new file mode 100644
index 0000000000..cb2425502f
--- /dev/null
+++ b/src/mainboard/google/mensa/mainboard.c
@@ -0,0 +1,25 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <device/device.h>
+#include <soc/pcie.h>
+
+bool mainboard_needs_pcie_init(void)
+{
+	/* Placeholder */
+	return false;
+}
+
+static void mainboard_init(void *chip_info)
+{
+	/* Placeholder */
+}
+
+static void mainboard_enable(struct device *dev)
+{
+	/* Placeholder */
+}
+
+struct chip_operations mainboard_ops = {
+	.enable_dev = mainboard_enable,
+	.init = mainboard_init,
+};
diff --git a/src/mainboard/google/mensa/reset.c b/src/mainboard/google/mensa/reset.c
new file mode 100644
index 0000000000..deb0ba8096
--- /dev/null
+++ b/src/mainboard/google/mensa/reset.c
@@ -0,0 +1,12 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <ec/google/chromeec/ec.h>
+#include <reset.h>
+
+/* Can't do a "real" reset before the PMIC is initialized in QcLib (romstage),
+   but this works well enough for our purposes. */
+void do_board_reset(void)
+{
+	if (CONFIG(EC_GOOGLE_CHROMEEC))
+		google_chromeec_reboot(EC_REBOOT_COLD, EC_REBOOT_FLAG_IMMEDIATE);
+}
diff --git a/src/mainboard/google/mensa/romstage.c b/src/mainboard/google/mensa/romstage.c
new file mode 100644
index 0000000000..0805f5fc64
--- /dev/null
+++ b/src/mainboard/google/mensa/romstage.c
@@ -0,0 +1,13 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <arch/stages.h>
+
+void platform_romstage_main(void)
+{
+	/* Placeholder */
+}
+
+void platform_romstage_postram(void)
+{
+	/* Placeholder */
+}

From 79b6dde1a525980f06862d6ab3fc7b84adbde858 Mon Sep 17 00:00:00 2001
From: Subrata Banik <subratabanik@google.com>
Date: Fri, 27 Mar 2026 06:50:32 +0000
Subject: [PATCH 3850/3886] soc/qualcomm/calypso: Set correct Kconfig defaults
 for peripherals

Update the default Kconfig values for the `soc/qualcomm/calypso`
to specify the correct hardware instances/buses used for various
peripherals as per datasheet for mensa (dated 03/10).

Changes:
- Boot SPI flash bus set to 26.
- Console UART instance set to 21.

Additionally, remove previous used TODO placeholders.

BUG=b:496650089
TEST=Successfully built google/mensa.

Change-Id: I89a298b13eb7761f1767d054c09eafdb3daf0927
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91897
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
---
 src/soc/qualcomm/calypso/Kconfig | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/soc/qualcomm/calypso/Kconfig b/src/soc/qualcomm/calypso/Kconfig
index 5c988b39fc..0920a751d5 100644
--- a/src/soc/qualcomm/calypso/Kconfig
+++ b/src/soc/qualcomm/calypso/Kconfig
@@ -52,11 +52,11 @@ config VBOOT
 
 config BOOT_DEVICE_SPI_FLASH_BUS
 	int
-	default 0 # TODO
+	default 26
 
 config UART_FOR_CONSOLE
 	int
-	default 0 # TODO
+	default 21 # QUP2_SE5
 	help
 	 Select the QUP instance to be used for UART console output.
 

From 8dbf88a300e4f7e6dde139964d7f253cad712253 Mon Sep 17 00:00:00 2001
From: Subrata Banik <subratabanik@google.com>
Date: Sat, 28 Mar 2026 06:51:23 +0000
Subject: [PATCH 3851/3886] soc/qualcomm/calypso: Add QUP Serial Engine (SE)
 entries

This patch adds QUP-SE entries as applicable for the Qualcomm Calypso
SoC.

This includes:
- Add new entries for QUPV3_3 SEs.
- Update base addresses for all QUP-SEs.
- Base GPIO pin function assignments.
- Definition and GPIO mapping for relevant QUP Serial Engines (SEs).
- GPIO mapping for the QSPI interface.

Additionally, update GPIO PINS for QSPI and UART.

BUG=b:496650089
TEST=Successfully built google/mensa.

Change-Id: Iab0eecc08d11d99d2534010af86217e6cc2a1961
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91901
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
---
 .../qualcomm/calypso/include/soc/addressmap.h |  19 +-
 src/soc/qualcomm/calypso/include/soc/clock.h  |   2 +
 src/soc/qualcomm/calypso/include/soc/gpio.h   | 252 +++++++++++++++++-
 .../calypso/include/soc/qcom_qup_se.h         |   3 +-
 src/soc/qualcomm/calypso/include/soc/uart.h   |   2 +-
 src/soc/qualcomm/calypso/qcom_qup_se.c        | 132 ++++++++-
 6 files changed, 396 insertions(+), 14 deletions(-)

diff --git a/src/soc/qualcomm/calypso/include/soc/addressmap.h b/src/soc/qualcomm/calypso/include/soc/addressmap.h
index efabd6e059..b5a9eb9534 100644
--- a/src/soc/qualcomm/calypso/include/soc/addressmap.h
+++ b/src/soc/qualcomm/calypso/include/soc/addressmap.h
@@ -17,14 +17,14 @@
 #define GCC_QUPV3_WRAP2_BASE		0x11e004
 
 /* CALPYSO QSPI GPIO PINS */
-#define QSPI_CS				GPIO(0)
-#define QSPI_DATA_0			GPIO(0)
-#define QSPI_DATA_1			GPIO(0)
-#define QSPI_CLK			GPIO(0)
+#define QSPI_CS				GPIO(132)
+#define QSPI_DATA_0			GPIO(128)
+#define QSPI_DATA_1			GPIO(129)
+#define QSPI_CLK			GPIO(127)
 
-#define GPIO_FUNC_QSPI_DATA_0		0
-#define GPIO_FUNC_QSPI_DATA_1		0
-#define GPIO_FUNC_QSPI_CLK		0
+#define GPIO_FUNC_QSPI_DATA_0		GPIO128_FUNC_QSPI0_DATA_0
+#define GPIO_FUNC_QSPI_DATA_1		GPIO129_FUNC_QSPI0_DATA_1
+#define GPIO_FUNC_QSPI_CLK		GPIO127_FUNC_QSPI0_CLK
 
 /* QUP SERIAL ENGINE BASE ADDRESSES */
 /* QUPV3_0 */
@@ -63,7 +63,10 @@
 #define QUP_WRAP2_BASE			0x008C0000
 #define QUP_2_GSI_BASE			0x00804000
 
-/* QUPV3_3 - Dummy Entry */
+/* QUPV3_3 */
+#define QUP_SERIAL24_BASE		0x00780000
+#define QUP_SERIAL25_BASE		0x00784000
 #define QUP_WRAP3_BASE			0x007C0000
+#define QUP_3_GSI_BASE			0x00704000
 
 #endif /*  __SOC_QUALCOMM_CALYPSO_ADDRESS_MAP_H__ */
diff --git a/src/soc/qualcomm/calypso/include/soc/clock.h b/src/soc/qualcomm/calypso/include/soc/clock.h
index 3350ab6b26..a9d8b83f77 100644
--- a/src/soc/qualcomm/calypso/include/soc/clock.h
+++ b/src/soc/qualcomm/calypso/include/soc/clock.h
@@ -44,6 +44,8 @@ enum clk_qup {
 	QUP_WRAP2_S5,
 	QUP_WRAP2_S6,
 	QUP_WRAP2_S7,
+	QUP_WRAP3_S0,
+	QUP_WRAP3_S1,
 };
 
 /* Subsystem Reset */
diff --git a/src/soc/qualcomm/calypso/include/soc/gpio.h b/src/soc/qualcomm/calypso/include/soc/gpio.h
index 8954ebab1b..bec2f01604 100644
--- a/src/soc/qualcomm/calypso/include/soc/gpio.h
+++ b/src/soc/qualcomm/calypso/include/soc/gpio.h
@@ -16,9 +16,257 @@
 	GPIO##index##_FUNC_##func5 = (5), \
 	GPIO##index##_FUNC_##func6 = (6)
 
-/* TODO: update as per datasheet */
 enum {
-	PIN(0, QUP0_SE0_L0, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(0, QUP0_SE0_L0, IBI_I3C_QUP0_SE0_SDA, RES_3, RES_4, RES_5, RES_6),
+	PIN(1, QUP0_SE0_L1, IBI_I3C_QUP0_SE0_SCL, RES_3, RES_4, RES_5, RES_6),
+	PIN(2, QUP0_SE0_L2, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(3, QUP0_SE0_L3, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(4, QUP0_SE1_L0, QUP0_SE6_L2, IBI_I3C_QUP0_SE1_SDA, RES_4, RES_5, RES_6),
+	PIN(5, QUP0_SE1_L1, QUP0_SE6_L3, IBI_I3C_QUP0_SE1_SCL, RES_4, RES_5, RES_6),
+	PIN(6, QUP0_SE1_L2, QUP0_SE6_L0, I2C0_S_SDA, RES_4, RES_5, RES_6),
+	PIN(7, QUP0_SE1_L3, QUP0_SE6_L1, I2C0_S_SCL, RES_4, RES_5, RES_6),
+	PIN(8, QUP0_SE2_L0, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(9, QUP0_SE2_L1, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(10, QUP0_SE2_L2, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(11, QUP0_SE2_L3, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(12, QUP0_SE3_L0, QUP0_SE7_L2, RES_3, RES_4, RES_5, RES_6),
+	PIN(13, QUP0_SE3_L1, QUP0_SE7_L3, RES_3, RES_4, RES_5, RES_6),
+	PIN(14, QUP0_SE3_L2, QUP0_SE7_L0, RES_3, RES_4, RES_5, RES_6),
+	PIN(15, QUP0_SE3_L3, QUP0_SE7_L1, RES_3, RES_4, RES_5, RES_6),
+	PIN(16, QUP0_SE4_L0, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(17, QUP0_SE4_L1, QUP0_SE2_L4, RES_3, RES_4, RES_5, RES_6),
+	PIN(18, QUP0_SE4_L2, QUP0_SE2_L5, RES_3, RES_4, QDSS_CTI_TRIG0_OUT_MIRB, RES_6),
+	PIN(19, QUP0_SE4_L3, QUP0_SE2_L6, RES_3, RES_4, QDSS_CTI_TRIG1_OUT_MIRB, RES_6),
+	PIN(20, QUP0_SE5_L0, GP_PDM_MIRB_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(21, QUP0_SE5_L1, QUP0_SE3_L4, GP_PDM_MIRB_1, RES_4, RES_5, RES_6),
+	PIN(22, QUP0_SE5_L2, QUP0_SE3_L5, GP_PDM_MIRB_0, RES_4, RES_5, RES_6),
+	PIN(23, QUP0_SE5_L3, QUP0_SE3_L6, RES_3, RES_4, QDSS_CTI_TRIG0_IN_MIRA, RES_6),
+	PIN(24, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(25, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(26, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(27, RES_1, RES_2, QDSS_CTI_TRIG1_IN_MIRA, RES_4, RES_5, RES_6),
+	PIN(28, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(29, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(30, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(31, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(32, QUP1_SE0_L0, IBI_I3C_QUP1_SE0_SDA, RES_3, RES_4, RES_5, RES_6),
+	PIN(33, QUP1_SE0_L1, IBI_I3C_QUP1_SE0_SCL, QUP1_SE3_L4, RES_4, RES_5, RES_6),
+	PIN(34, QUP1_SE0_L2, QUP1_SE3_L5, RES_3, RES_4, RES_5, RES_6),
+	PIN(35, QUP1_SE0_L3, QUP1_SE3_L6, RES_3, RES_4, RES_5, RES_6),
+	PIN(36, QUP1_SE1_L0, IBI_I3C_QUP1_SE1_SDA, RES_3, RES_4, RES_5, RES_6),
+	PIN(37, QUP1_SE1_L1, IBI_I3C_QUP1_SE1_SCL, RES_3, RES_4, RES_5, RES_6),
+	PIN(38, QUP1_SE1_L2, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(39, QUP1_SE1_L3, SYS_THROTTLE_N_MIRA, RES_3, RES_4, RES_5, RES_6),
+	PIN(40, QUP1_SE2_L0, QUP3_SE1_L0, RES_3, RES_4, RES_5, RES_6),
+	PIN(41, QUP1_SE2_L1, QUP3_SE1_L1, RES_3, RES_4, RES_5, RES_6),
+	PIN(42, QUP1_SE2_L2, QUP3_SE1_L2, RES_3, RES_4, RES_5, RES_6),
+	PIN(43, QUP1_SE2_L3, QUP3_SE1_L3, RES_3, RES_4, RES_5, RES_6),
+	PIN(44, QUP1_SE3_L0, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(45, QUP1_SE3_L1, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(46, QUP1_SE3_L2, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(47, QUP1_SE3_L3, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(48, QUP1_SE4_L0, QUP3_SE1_L7, RES_3, RES_4, RES_5, RES_6),
+	PIN(49, QUP1_SE4_L1, QUP1_SE2_L4, QUP3_SE1_L4, RES_4, RES_5, RES_6),
+	PIN(50, QUP1_SE4_L2, QUP1_SE2_L5, QUP3_SE1_L5, RES_4, RES_5, RES_6),
+	PIN(51, QUP1_SE4_L3, QUP1_SE4_L4, QUP1_SE4_L5, RES_4, RES_5, RES_6),
+	PIN(52, QUP1_SE5_L0, QUP1_SE7_L2, RES_3, RES_4, RES_5, RES_6),
+	PIN(53, QUP1_SE5_L1, QUP1_SE7_L3, GP_MN, RES_4, RES_5, RES_6),
+	PIN(54, QUP1_SE5_L2, QUP1_SE7_L0, RES_3, RES_4, RES_5, RES_6),
+	PIN(55, QUP1_SE5_L3, QUP1_SE7_L1, RES_3, RES_4, RES_5, RES_6),
+	PIN(56, QUP1_SE6_L0, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(57, QUP1_SE6_L1, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(58, QUP1_SE6_L2, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(59, QUP1_SE6_L3, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(60, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(61, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(62, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(63, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(64, QUP2_SE0_L0, IBI_I3C_QUP2_SE0_SDA, GCC_GP2_CLK_MIRB, RES_4, RES_5, RES_6),
+	PIN(65, QUP2_SE0_L1, QUP2_SE3_L4, IBI_I3C_QUP2_SE0_SCL, RES_4, RES_5, RES_6),
+	PIN(66, QUP2_SE0_L2, QUP2_SE3_L5, RES_3, RES_4, RES_5, RES_6),
+	PIN(67, QUP2_SE0_L3, QUP2_SE3_L6, RES_3, RES_4, RES_5, RES_6),
+	PIN(68, QUP2_SE1_L0, IBI_I3C_QUP2_SE1_SDA, RES_3, RES_4, RES_5, RES_6),
+	PIN(69, QUP2_SE1_L1, IBI_I3C_QUP2_SE1_SCL, RES_3, RES_4, RES_5, RES_6),
+	PIN(70, QUP2_SE1_L2, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(71, QUP2_SE1_L3, GCC_GP1_CLK_MIRB, RES_3, RES_4, RES_5, RES_6),
+	PIN(72, QUP2_SE2_L0, GCC_GP1_CLK_MIRA, RES_3, RES_4, RES_5, RES_6),
+	PIN(73, QUP2_SE2_L1, GCC_GP2_CLK_MIRA, RES_3, RES_4, RES_5, RES_6),
+	PIN(74, QUP2_SE2_L2, GCC_GP3_CLK_MIRA, RES_3, RES_4, RES_5, RES_6),
+	PIN(75, QUP2_SE2_L3, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(76, QUP2_SE3_L0, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(77, QUP2_SE3_L1, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(78, QUP2_SE3_L2, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(79, QUP2_SE3_L3, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(80, QUP2_SE4_L0, QUP2_SE7_L0, RES_3, RES_4, RES_5, RES_6),
+	PIN(81, QUP2_SE4_L1, QUP2_SE2_L4, QUP2_SE7_L1, RES_4, RES_5, RES_6),
+	PIN(82, QUP2_SE4_L2, QUP2_SE2_L5, QUP2_SE7_L2, GCC_GP3_CLK_MIRB, RES_5, RES_6),
+	PIN(83, QUP2_SE4_L3, QUP2_SE2_L6, QUP2_SE7_L3, RES_4, RES_5, RES_6),
+	PIN(84, QUP2_SE5_L0, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(85, QUP2_SE5_L1, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(86, QUP2_SE5_L2, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(87, QUP2_SE5_L3, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(88, QUP2_SE6_L0, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(89, QUP2_SE6_L1, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(90, QUP2_SE6_L2, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(91, QUP2_SE6_L3, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(92, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(93, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(94, SYS_THROTTLE_N_MIRB, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(95, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(96, CAM_MCLK0, QDSS_GPIO_TRACEDATA_LOCA_0, RES_3, RES_4, RES_5, RES_6),
+	PIN(97, CAM_MCLK1, QDSS_GPIO_TRACEDATA_LOCA_1, RES_3, RES_4, RES_5, RES_6),
+	PIN(98, CAM_MCLK2, MDP_VSYNC_P, USB0_TMU_CLK_OUT, USB1_TMU_CLK_OUT, USB2_TMU_CLK_OUT, RES_6),
+	PIN(99, CAM_MCLK3, QDSS_GPIO_TRACEDATA_LOCA_3, RES_3, RES_4, RES_5, RES_6),
+	PIN(100, CAM_ASC_MCLK4, QDSS_GPIO_TRACEDATA_LOCA_4, RES_3, RES_4, RES_5, RES_6),
+	PIN(101, CCI_I2C_SDA0, QDSS_GPIO_TRACEDATA_LOCA_5, RES_3, RES_4, RES_5, RES_6),
+	PIN(102, CCI_I2C_SCL0, QDSS_GPIO_TRACEDATA_LOCA_6, RES_3, RES_4, RES_5, RES_6),
+	PIN(103, CCI_I2C_SDA1, QDSS_GPIO_TRACEDATA_LOCA_7, RES_3, RES_4, RES_5, RES_6),
+	PIN(104, CCI_I2C_SCL1, QDSS_GPIO_TRACECTL_LOCA, RES_3, RES_4, RES_5, RES_6),
+	PIN(105, CCI_I2C_SDA2, MDP_VSYNC_S, RES_3, RES_4, RES_5, RES_6),
+	PIN(106, CCI_I2C_SCL2, MDP_VSYNC_E, RES_3, RES_4, RES_5, RES_6),
+	PIN(107, QDSS_GPIO_TRACEDATA_LOCA_9, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(108, QDSS_GPIO_TRACEDATA_LOCA_10, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(109, CCI_TIMER0, MDP_VSYNC4_OUT, QDSS_GPIO_TRACEDATA_LOCA_11, RES_4, RES_5, RES_6),
+	PIN(110, CCI_TIMER1, MDP_VSYNC5_OUT, QDSS_GPIO_TRACEDATA_LOCA_12, RES_4, RES_5, RES_6),
+	PIN(111, CCI_TIMER2, CCI_ASYNC_IN2, MDP_VSYNC6_OUT, QDSS_GPIO_TRACEDATA_LOCA_13, RES_5, RES_6),
+	PIN(112, CCI_TIMER3, CCI_ASYNC_IN1, MDP_VSYNC7_OUT, QDSS_GPIO_TRACEDATA_LOCA_14, RES_5, RES_6),
+	PIN(113, CCI_TIMER4, CCI_ASYNC_IN0, MDP_VSYNC8_OUT, QDSS_GPIO_TRACEDATA_LOCA_15, RES_5, RES_6),
+	PIN(114, MDP_VSYNC0_OUT, MDP_VSYNC1_OUT, RES_3, RES_4, RES_5, RES_6),
+	PIN(115, MDP_VSYNC3_OUT, MDP_VSYNC2_OUT, RES_3, RES_4, RES_5, RES_6),
+	PIN(116, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(117, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(118, HOST2WLAN_SOL, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(119, EDP0_HOT_PLUG_DETECT, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(120, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(121, USB0_PHY_PS, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(122, USB0_DP_HOT_PLUG_DETECT, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(123, USB1_PHY_PS, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(124, USB1_DP_HOT_PLUG_DETECT, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(125, USB2_PHY_PS, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(126, USB2_DP_HOT_PLUG_DETECT, GP_PDM_MIRA_0, RES_3, RES_4, RES_5, RES_6),
+	PIN(127, QSPI0_CLK, SDC4_CLK, QUP3_SE0_L2, GP_PDM_MIRA_1, RES_5, RES_6),
+	PIN(128, QSPI0_DATA_0, SDC4_DATA_0, QUP3_SE0_L1, GP_PDM_MIRA_2, RES_5, RES_6),
+	PIN(129, QSPI0_DATA_1, SDC4_DATA_1, QUP3_SE0_L0, RES_4, RES_5, RES_6),
+	PIN(130, QSPI0_DATA_2, SDC4_DATA_2, QUP3_SE0_L4, RES_4, RES_5, RES_6),
+	PIN(131, QSPI0_DATA_3, SDC4_DATA_3, QUP3_SE0_L5, RES_4, RES_5, RES_6),
+	PIN(132, QSPI0_CS0_N, SDC4_CMD, QUP3_SE0_L3, RES_4, RES_5, RES_6),
+	PIN(133, QSPI0_CS1_N, RES_2, QUP3_SE0_L6, RES_4, RES_5, RES_6),
+	PIN(134, AUDIO_EXT_MCLK0, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(135, I2S0_SCK, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(136, I2S0_DATA0, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(137, I2S0_DATA1, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(138, I2S0_WS, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(139, I2S1_SCK, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(140, I2S1_DATA0, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(141, I2S1_WS, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(142, I2S1_DATA1, AUDIO_EXT_MCLK1, AUDIO_REF_CLK, RES_4, RES_5, RES_6),
+	PIN(143, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(144, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(145, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(146, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(147, PCIE4_CLK_REQ_N, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(148, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(149, QDSS_GPIO_TRACEDATA_LOCA_2, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(150, PCIE6_CLK_REQ_N, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(151, QDSS_GPIO_TRACECLK_LOCA, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(152, QDSS_GPIO_TRACEDATA_LOCA_8, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(153, PCIE5_CLK_REQ_N, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(154, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(155, PCIE3_RST_N, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(156, PCIE3_CLK_REQ_N, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(157, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(158, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(159, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(160, RESOUT_GPIO_N, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(161, QDSS_CTI_TRIG0_OUT_MIRA, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(162, SD_WRITE_PROTECT, QDSS_CTI_TRIG1_OUT_MIRA, RES_3, RES_4, RES_5, RES_6),
+	PIN(163, USB0_SBRX, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(164, USB0_SBTX, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(165, USB0_SBTX_DIR_OUT, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(166, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(167, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(168, EUSB0_AC_EN, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(169, EUSB3_AC_EN, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(170, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(171, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(172, USB1_SBRX, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(173, USB1_SBTX, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(174, USB1_SBTX_DIR_OUT, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(175, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(176, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(177, EUSB1_AC_EN, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(178, EUSB6_AC_EN, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(179, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(180, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(181, USB2_SBRX, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(182, USB2_SBTX, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(183, USB2_SBTX_DIR_OUT, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(184, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(185, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(186, EUSB2_AC_EN, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(187, EUSB5_AC_EN, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(188, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(189, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(190, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(191, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(192, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(193, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(194, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(195, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(196, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(197, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(198, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(199, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(200, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(201, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(202, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(203, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(204, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(205, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(206, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(207, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(208, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(209, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(210, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(211, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(212, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(213, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(214, WCN_SW_CTRL, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(215, RES_1, QDSS_CTI_TRIG1_IN_MIRB, RES_3, RES_4, RES_5, RES_6),
+	PIN(216, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(217, RES_1, QDSS_CTI_TRIG0_IN_MIRB, RES_3, RES_4, RES_5, RES_6),
+	PIN(218, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(219, RES_1, QDSS_GPIO_TRACEDATA_LOCB_0, RES_3, RES_4, RES_5, RES_6),
+	PIN(220, RES_1, QDSS_GPIO_TRACEDATA_LOCB_1, RES_3, RES_4, RES_5, RES_6),
+	PIN(221, WCN_SW_CTRL_WL_CX, RES_2, QDSS_GPIO_TRACEDATA_LOCB_2, RES_4, RES_5, RES_6),
+	PIN(222, RES_1, QDSS_GPIO_TRACEDATA_LOCB_3, RES_3, RES_4, RES_5, RES_6),
+	PIN(223, RES_1, QDSS_GPIO_TRACEDATA_LOCB_4, RES_3, RES_4, RES_5, RES_6),
+	PIN(224, RES_1, QDSS_GPIO_TRACEDATA_LOCB_5, RES_3, RES_4, RES_5, RES_6),
+	PIN(225, RES_1, QDSS_GPIO_TRACEDATA_LOCB_6, RES_3, RES_4, RES_5, RES_6),
+	PIN(226, RES_1, QDSS_GPIO_TRACEDATA_LOCB_7, RES_3, RES_4, RES_5, RES_6),
+	PIN(227, RES_1, QDSS_GPIO_TRACECLK_LOCB, RES_3, RES_4, RES_5, RES_6),
+	PIN(228, RES_1, QDSS_GPIO_TRACECTL_LOCB, RES_3, RES_4, RES_5, RES_6),
+	PIN(229, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(230, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(231, QDSS_GPIO_TRACEDATA_LOCB_10, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(232, QDSS_GPIO_TRACEDATA_LOCB_11, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(233, QDSS_GPIO_TRACEDATA_LOCB_12, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(234, QDSS_GPIO_TRACEDATA_LOCB_13, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(235, ASC_CCI_I2C_SDA3, QDSS_GPIO_TRACEDATA_LOCB_14, RES_3, RES_4, RES_5, RES_6),
+	PIN(236, ASC_CCI_I2C_SCL3, QDSS_GPIO_TRACEDATA_LOCB_15, RES_3, RES_4, RES_5, RES_6),
+	PIN(237, QDSS_GPIO_TRACEDATA_LOCB_8, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(238, QDSS_GPIO_TRACEDATA_LOCB_9, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(239, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(240, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(241, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(242, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(243, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(244, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(245, SMB_ACOK_N, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(246, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(247, QUP3_SE0_L7, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(248, PMC_UVA_N, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(249, PMC_OCA_N, RES_2, RES_3, RES_4, RES_5, RES_6),
 };
 
 #endif /* __SOC_QUALCOMM_CALYPSO_GPIO_H__ */
diff --git a/src/soc/qualcomm/calypso/include/soc/qcom_qup_se.h b/src/soc/qualcomm/calypso/include/soc/qcom_qup_se.h
index d0313ca295..6e5711d3ba 100644
--- a/src/soc/qualcomm/calypso/include/soc/qcom_qup_se.h
+++ b/src/soc/qualcomm/calypso/include/soc/qcom_qup_se.h
@@ -10,7 +10,6 @@
 #include <timer.h>
 #include <types.h>
 
-/* TODO: update as per datasheet */
 enum qup_se {
 	QUPV3_0_SE0,
 	QUPV3_0_SE1,
@@ -36,6 +35,8 @@ enum qup_se {
 	QUPV3_2_SE5,
 	QUPV3_2_SE6,
 	QUPV3_2_SE7,
+	QUPV3_3_SE0,
+	QUPV3_3_SE1,
 	QUPV3_SE_MAX,
 };
 
diff --git a/src/soc/qualcomm/calypso/include/soc/uart.h b/src/soc/qualcomm/calypso/include/soc/uart.h
index 362f8853fd..1684b9ba12 100644
--- a/src/soc/qualcomm/calypso/include/soc/uart.h
+++ b/src/soc/qualcomm/calypso/include/soc/uart.h
@@ -4,6 +4,6 @@
 #define __SOC_QUALCOMM_CALYPSO_UART_TX_H__
 
 /* TODO: update as per datasheet */
-#define UART_TX_PIN GPIO(0)
+#define UART_TX_PIN GPIO(86)
 
 #endif /* __SOC_QUALCOMM_CALYPSO_UART_TX_H__ */
diff --git a/src/soc/qualcomm/calypso/qcom_qup_se.c b/src/soc/qualcomm/calypso/qcom_qup_se.c
index df1335c72a..53ae41f5fd 100644
--- a/src/soc/qualcomm/calypso/qcom_qup_se.c
+++ b/src/soc/qualcomm/calypso/qcom_qup_se.c
@@ -2,7 +2,135 @@
 
 #include <soc/qcom_qup_se.h>
 
-/* TODO: update QUP entries as per datasheet */
 struct qup qup[QUPV3_SE_MAX] = {
-
+	[QUPV3_0_SE0] = { .regs = (void *)QUP_SERIAL0_BASE,
+		.pin = { GPIO(0), GPIO(1), GPIO(2), GPIO(3) },
+		.func = { GPIO0_FUNC_QUP0_SE0_L0, GPIO1_FUNC_QUP0_SE0_L1,
+			GPIO2_FUNC_QUP0_SE0_L2, GPIO3_FUNC_QUP0_SE0_L3 }
+		},
+	[QUPV3_0_SE1] = { .regs = (void *)QUP_SERIAL1_BASE,
+		.pin = { GPIO(4), GPIO(5), GPIO(6), GPIO(7) },
+		.func = { GPIO4_FUNC_QUP0_SE1_L0, GPIO5_FUNC_QUP0_SE1_L1,
+			GPIO6_FUNC_QUP0_SE1_L2, GPIO7_FUNC_QUP0_SE1_L3 }
+		},
+	[QUPV3_0_SE2] = { .regs = (void *)QUP_SERIAL2_BASE,
+		.pin = { GPIO(8), GPIO(9), GPIO(10), GPIO(11) },
+		.func = { GPIO8_FUNC_QUP0_SE2_L0, GPIO9_FUNC_QUP0_SE2_L1,
+			GPIO10_FUNC_QUP0_SE2_L2, GPIO11_FUNC_QUP0_SE2_L3 }
+		},
+	[QUPV3_0_SE3] = { .regs = (void *)QUP_SERIAL3_BASE,
+		.pin = { GPIO(12), GPIO(13), GPIO(14), GPIO(15) },
+		.func = { GPIO12_FUNC_QUP0_SE3_L0, GPIO13_FUNC_QUP0_SE3_L1,
+			GPIO14_FUNC_QUP0_SE3_L2, GPIO15_FUNC_QUP0_SE3_L3 }
+		},
+	[QUPV3_0_SE4] = { .regs = (void *)QUP_SERIAL4_BASE,
+		.pin = { GPIO(16), GPIO(17), GPIO(18), GPIO(19) },
+		.func = { GPIO16_FUNC_QUP0_SE4_L0, GPIO17_FUNC_QUP0_SE4_L1,
+			GPIO18_FUNC_QUP0_SE4_L2, GPIO19_FUNC_QUP0_SE4_L3 }
+		},
+	[QUPV3_0_SE5] = { .regs = (void *)QUP_SERIAL5_BASE,
+		.pin = { GPIO(20), GPIO(21), GPIO(22), GPIO(23) },
+		.func = { GPIO20_FUNC_QUP0_SE5_L0, GPIO21_FUNC_QUP0_SE5_L1,
+			GPIO22_FUNC_QUP0_SE5_L2, GPIO23_FUNC_QUP0_SE5_L3 }
+		},
+	[QUPV3_0_SE6] = { .regs = (void *)QUP_SERIAL6_BASE,
+		.pin = { GPIO(6), GPIO(7), GPIO(4), GPIO(5) },
+		.func = { GPIO6_FUNC_QUP0_SE6_L0, GPIO7_FUNC_QUP0_SE6_L1,
+			GPIO4_FUNC_QUP0_SE6_L2, GPIO5_FUNC_QUP0_SE6_L3 }
+		},
+	[QUPV3_0_SE7] = { .regs = (void *)QUP_SERIAL7_BASE,
+		.pin = { GPIO(14), GPIO(15), GPIO(12), GPIO(13) },
+		.func = { GPIO14_FUNC_QUP0_SE7_L0, GPIO15_FUNC_QUP0_SE7_L1,
+			GPIO12_FUNC_QUP0_SE7_L2, GPIO13_FUNC_QUP0_SE7_L3 }
+		},
+	[QUPV3_1_SE0] = { .regs = (void *)QUP_SERIAL8_BASE,
+		.pin = { GPIO(32), GPIO(33), GPIO(34), GPIO(35) },
+		.func = { GPIO32_FUNC_QUP1_SE0_L0, GPIO33_FUNC_QUP1_SE0_L1,
+			GPIO34_FUNC_QUP1_SE0_L2, GPIO35_FUNC_QUP1_SE0_L3 }
+		},
+	[QUPV3_1_SE1] = { .regs = (void *)QUP_SERIAL9_BASE,
+		.pin = { GPIO(36), GPIO(37), GPIO(38), GPIO(39) },
+		.func = { GPIO36_FUNC_QUP1_SE1_L0, GPIO37_FUNC_QUP1_SE1_L1,
+			GPIO38_FUNC_QUP1_SE1_L2, GPIO39_FUNC_QUP1_SE1_L3 }
+		},
+	[QUPV3_1_SE2] = { .regs = (void *)QUP_SERIAL10_BASE,
+		.pin = { GPIO(40), GPIO(41), GPIO(42), GPIO(43) },
+		.func = { GPIO40_FUNC_QUP1_SE2_L0, GPIO41_FUNC_QUP1_SE2_L1,
+			GPIO42_FUNC_QUP1_SE2_L2, GPIO43_FUNC_QUP1_SE2_L3 }
+		},
+	[QUPV3_1_SE3] = { .regs = (void *)QUP_SERIAL11_BASE,
+		.pin = { GPIO(44), GPIO(45), GPIO(46), GPIO(47) },
+		.func = { GPIO44_FUNC_QUP1_SE3_L0, GPIO45_FUNC_QUP1_SE3_L1,
+			GPIO46_FUNC_QUP1_SE3_L2, GPIO47_FUNC_QUP1_SE3_L3 }
+		},
+	[QUPV3_1_SE4] = { .regs = (void *)QUP_SERIAL12_BASE,
+		.pin = { GPIO(48), GPIO(49), GPIO(50), GPIO(51) },
+		.func = { GPIO48_FUNC_QUP1_SE4_L0, GPIO49_FUNC_QUP1_SE4_L1,
+			GPIO50_FUNC_QUP1_SE4_L2, GPIO51_FUNC_QUP1_SE4_L3 }
+		},
+	[QUPV3_1_SE5] = { .regs = (void *)QUP_SERIAL13_BASE,
+		.pin = { GPIO(52), GPIO(53), GPIO(54), GPIO(55) },
+		.func = { GPIO52_FUNC_QUP1_SE5_L0, GPIO53_FUNC_QUP1_SE5_L1,
+			GPIO54_FUNC_QUP1_SE5_L2, GPIO55_FUNC_QUP1_SE5_L3 }
+		},
+	[QUPV3_1_SE6] = { .regs = (void *)QUP_SERIAL14_BASE,
+		.pin = { GPIO(56), GPIO(57), GPIO(58), GPIO(59) },
+		.func = { GPIO56_FUNC_QUP1_SE6_L0, GPIO57_FUNC_QUP1_SE6_L1,
+			GPIO58_FUNC_QUP1_SE6_L2, GPIO59_FUNC_QUP1_SE6_L3 }
+		},
+	[QUPV3_1_SE7] = { .regs = (void *)QUP_SERIAL15_BASE,
+		.pin = { GPIO(54), GPIO(55), GPIO(52), GPIO(53) },
+		.func = { GPIO54_FUNC_QUP1_SE7_L0, GPIO55_FUNC_QUP1_SE7_L1,
+			GPIO52_FUNC_QUP1_SE7_L2, GPIO53_FUNC_QUP1_SE7_L3 }
+		},
+	[QUPV3_2_SE0] = { .regs = (void *)QUP_SERIAL16_BASE,
+		.pin = { GPIO(64), GPIO(65), GPIO(66), GPIO(67) },
+		.func = { GPIO64_FUNC_QUP2_SE0_L0, GPIO65_FUNC_QUP2_SE0_L1,
+			GPIO66_FUNC_QUP2_SE0_L2, GPIO67_FUNC_QUP2_SE0_L3 }
+		},
+	[QUPV3_2_SE1] = { .regs = (void *)QUP_SERIAL17_BASE,
+		.pin = { GPIO(68), GPIO(69), GPIO(70), GPIO(71) },
+		.func = { GPIO68_FUNC_QUP2_SE1_L0, GPIO69_FUNC_QUP2_SE1_L1,
+			GPIO70_FUNC_QUP2_SE1_L2, GPIO71_FUNC_QUP2_SE1_L3 }
+		},
+	[QUPV3_2_SE2] = { .regs = (void *)QUP_SERIAL18_BASE,
+		.pin = { GPIO(72), GPIO(73), GPIO(74), GPIO(75) },
+		.func = { GPIO72_FUNC_QUP2_SE2_L0, GPIO73_FUNC_QUP2_SE2_L1,
+			GPIO74_FUNC_QUP2_SE2_L2, GPIO75_FUNC_QUP2_SE2_L3 }
+		},
+	[QUPV3_2_SE3] = { .regs = (void *)QUP_SERIAL19_BASE,
+		.pin = { GPIO(76), GPIO(77), GPIO(78), GPIO(79) },
+		.func = { GPIO76_FUNC_QUP2_SE3_L0, GPIO77_FUNC_QUP2_SE3_L1,
+			GPIO78_FUNC_QUP2_SE3_L2, GPIO79_FUNC_QUP2_SE3_L3 }
+		},
+	[QUPV3_2_SE4] = { .regs = (void *)QUP_SERIAL20_BASE,
+		.pin = { GPIO(80), GPIO(81), GPIO(82), GPIO(83) },
+		.func = { GPIO80_FUNC_QUP2_SE4_L0, GPIO81_FUNC_QUP2_SE4_L1,
+			GPIO82_FUNC_QUP2_SE4_L2, GPIO83_FUNC_QUP2_SE4_L3 }
+		},
+	[QUPV3_2_SE5] = { .regs = (void *)QUP_SERIAL21_BASE,
+		.pin = { GPIO(84), GPIO(85), GPIO(86), GPIO(87) },
+		.func = { GPIO84_FUNC_QUP2_SE5_L0, GPIO85_FUNC_QUP2_SE5_L1,
+			GPIO86_FUNC_QUP2_SE5_L2, GPIO87_FUNC_QUP2_SE5_L3 }
+		},
+	[QUPV3_2_SE6] = { .regs = (void *)QUP_SERIAL22_BASE,
+		.pin = { GPIO(88), GPIO(89), GPIO(90), GPIO(91) },
+		.func = { GPIO88_FUNC_QUP2_SE6_L0, GPIO89_FUNC_QUP2_SE6_L1,
+			GPIO90_FUNC_QUP2_SE6_L2, GPIO91_FUNC_QUP2_SE6_L3 }
+		},
+	[QUPV3_2_SE7] = { .regs = (void *)QUP_SERIAL23_BASE,
+		.pin = { GPIO(80), GPIO(81), GPIO(82), GPIO(83) },
+		.func = { GPIO80_FUNC_QUP2_SE7_L0, GPIO81_FUNC_QUP2_SE7_L1,
+			GPIO82_FUNC_QUP2_SE7_L2, GPIO83_FUNC_QUP2_SE7_L3 }
+		},
+	[QUPV3_3_SE0] = { .regs = (void *)QUP_SERIAL24_BASE,
+		.pin = { GPIO(129), GPIO(128), GPIO(127), GPIO(132) },
+		.func = { GPIO129_FUNC_QUP3_SE0_L0, GPIO128_FUNC_QUP3_SE0_L1,
+			GPIO127_FUNC_QUP3_SE0_L2, GPIO132_FUNC_QUP3_SE0_L3 }
+		},
+	[QUPV3_3_SE1] = { .regs = (void *)QUP_SERIAL25_BASE,
+		.pin = { GPIO(40), GPIO(41), GPIO(42), GPIO(43) },
+		.func = { GPIO40_FUNC_QUP3_SE1_L0, GPIO41_FUNC_QUP3_SE1_L1,
+			GPIO42_FUNC_QUP3_SE1_L2, GPIO43_FUNC_QUP3_SE1_L3 }
+		},
 };

From 0fc956cd2ddf97c1a4f29907fc83f3bb466b12b8 Mon Sep 17 00:00:00 2001
From: Subrata Banik <subratabanik@google.com>
Date: Fri, 27 Mar 2026 11:55:34 +0000
Subject: [PATCH 3852/3886] mb/google/mensa: Set correct Kconfig defaults for
 peripherals

Update the default Kconfig values for the google/mensa mainboard
to specify the correct hardware instances/buses used for various
peripherals as per mensa schematics (dated 03/10).

Changes:
- TPM I2C bus set to 0x01.
- ChromeEC SPI bus set to 0x16.

Removes previous TODO placeholders.

BUG=b:496650089
TEST=Successfully built google/mensa.

Change-Id: Ic377be3dc165bf1c1e19031994d87ea45d6c2dc0
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91902
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
---
 src/mainboard/google/mensa/Kconfig | 6 +++---
 src/mainboard/google/mensa/board.h | 5 +++--
 2 files changed, 6 insertions(+), 5 deletions(-)

diff --git a/src/mainboard/google/mensa/Kconfig b/src/mainboard/google/mensa/Kconfig
index e93de807bf..5948aed0ad 100644
--- a/src/mainboard/google/mensa/Kconfig
+++ b/src/mainboard/google/mensa/Kconfig
@@ -71,7 +71,7 @@ config MAINBOARD_PART_NUMBER
 config DRIVER_TPM_I2C_BUS
 	depends on I2C_TPM
 	hex
-	default 0x0 # TODO
+	default 0x01 # QUP0_SE1
 
 config DRIVER_TPM_I2C_ADDR
 	default 0x50
@@ -79,12 +79,12 @@ config DRIVER_TPM_I2C_ADDR
 config EC_GOOGLE_CHROMEEC_SPI_BUS
 	depends on EC_GOOGLE_CHROMEEC
 	hex
-	default 0x0 # TODO
+	default 0x16 # QUP2_SE6
 
 config MAINBOARD_GPIO_PIN_FOR_GSC_AP_INTERRUPT
 	depends on TPM_GOOGLE_TI50
 	int
-	default 0 # TODO
+	default 23
 	help
 	  This option specifies the GPIO pin number on the mainboard that is
 	  used for the interrupt line from the Google Security Chip (GSC) to the
diff --git a/src/mainboard/google/mensa/board.h b/src/mainboard/google/mensa/board.h
index 973c375d97..72fc39fadf 100644
--- a/src/mainboard/google/mensa/board.h
+++ b/src/mainboard/google/mensa/board.h
@@ -7,8 +7,9 @@
 #include <gpio.h>
 
 /* TODO: update as per datasheet */
-#define GPIO_AP_EC_INT		GPIO(0)
-#define GPIO_GSC_AP_INT		GPIO(0)
+#define GPIO_AP_EC_INT		GPIO(66)
+#define GSC_AP_INT(x)		GPIO(x)
+#define GPIO_GSC_AP_INT		GSC_AP_INT(CONFIG_MAINBOARD_GPIO_PIN_FOR_GSC_AP_INTERRUPT)
 
 void setup_chromeos_gpios(void);
 

From 421c21c6cf2292d593aad3d88980be9cbb07181e Mon Sep 17 00:00:00 2001
From: Subrata Banik <subratabanik@google.com>
Date: Sat, 28 Mar 2026 06:58:29 +0000
Subject: [PATCH 3853/3886] soc/qualcomm/calypso: Initialize QSPI and QUPv3 in
 bootblock

The bootblock requires early initialization of the Quad-SPI (QSPI)
controller to enable reading firmware from flash memory.

This commit adds calls to `quadspi_init()` with a 75 MHz bus clock
and `qupv3_fw_init()` within `bootblock_soc_init()`. This ensures
that the essential hardware for flash access and related QUPv3
functions are properly configured during the boot process.

BUG=b:496650089
TEST=Able to build google/mensa.

Change-Id: I225485cf601c62b1ba695eb61f786a1360790f41
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91903
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/soc/qualcomm/calypso/bootblock.c | 7 ++++++-
 1 file changed, 6 insertions(+), 1 deletion(-)

diff --git a/src/soc/qualcomm/calypso/bootblock.c b/src/soc/qualcomm/calypso/bootblock.c
index ce000dbc40..e277dcce76 100644
--- a/src/soc/qualcomm/calypso/bootblock.c
+++ b/src/soc/qualcomm/calypso/bootblock.c
@@ -2,6 +2,10 @@
 
 #include <bootblock_common.h>
 #include <soc/mmu.h>
+#include <soc/qspi_common.h>
+#include <soc/qupv3_config_common.h>
+
+#define SPI_BUS_CLOCK_FREQ (75 * MHz)
 
 void bootblock_soc_early_init(void)
 {
@@ -11,5 +15,6 @@ void bootblock_soc_early_init(void)
 
 void bootblock_soc_init(void)
 {
-	/* Placeholder */
+	quadspi_init(SPI_BUS_CLOCK_FREQ);
+	qupv3_fw_init();
 }

From a6921f7fb9ce8a12c87535f4ca7ce0a20f3c13a8 Mon Sep 17 00:00:00 2001
From: Subrata Banik <subratabanik@google.com>
Date: Sat, 28 Mar 2026 07:03:02 +0000
Subject: [PATCH 3854/3886] soc/qualcomm/calypso: Add placeholder for early
 clock initialization

This commit adds the `clock_init()` function for the Qualcomm calypso
SoC. This function is now called at the beginning of
`bootblock_soc_init()` to enable SoC-specific clock setup early in the
boot process.

The `clock_init()` function definition is currently a placeholder
and will be populated with the required clock configurations in
subsequent changes.

BUG=b:496650089
TEST=Able to build google/mensa.

Change-Id: I3886670348e998b3d80d33643e2256af4eb47fd7
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91904
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
---
 src/soc/qualcomm/calypso/bootblock.c         | 2 ++
 src/soc/qualcomm/calypso/clock.c             | 5 +++++
 src/soc/qualcomm/calypso/include/soc/clock.h | 1 +
 3 files changed, 8 insertions(+)

diff --git a/src/soc/qualcomm/calypso/bootblock.c b/src/soc/qualcomm/calypso/bootblock.c
index e277dcce76..44641397d2 100644
--- a/src/soc/qualcomm/calypso/bootblock.c
+++ b/src/soc/qualcomm/calypso/bootblock.c
@@ -15,6 +15,8 @@ void bootblock_soc_early_init(void)
 
 void bootblock_soc_init(void)
 {
+	clock_init();
+
 	quadspi_init(SPI_BUS_CLOCK_FREQ);
 	qupv3_fw_init();
 }
diff --git a/src/soc/qualcomm/calypso/clock.c b/src/soc/qualcomm/calypso/clock.c
index 9a4b16d810..5e9706f698 100644
--- a/src/soc/qualcomm/calypso/clock.c
+++ b/src/soc/qualcomm/calypso/clock.c
@@ -16,3 +16,8 @@ void clock_configure_dfsr(int qup)
 {
 	/* placeholder */
 }
+
+void clock_init(void)
+{
+	/* placeholder */
+}
diff --git a/src/soc/qualcomm/calypso/include/soc/clock.h b/src/soc/qualcomm/calypso/include/soc/clock.h
index a9d8b83f77..61e5064a32 100644
--- a/src/soc/qualcomm/calypso/include/soc/clock.h
+++ b/src/soc/qualcomm/calypso/include/soc/clock.h
@@ -10,6 +10,7 @@
 #define SRC_XO_HZ		(19200 * KHz)
 
 /* TODO: update as per datasheet */
+void clock_init(void);
 void clock_configure_qspi(uint32_t hz);
 void clock_enable_qup(int qup);
 void clock_configure_dfsr(int qup);

From 888cc7f92a929051d6f6aacd39352427be685601 Mon Sep 17 00:00:00 2001
From: Subrata Banik <subratabanik@google.com>
Date: Sat, 28 Mar 2026 07:14:54 +0000
Subject: [PATCH 3855/3886] mb/google/mensa: Initialize FP GPIOs in bootblock

Perform early initialization of FP GPIOs inside the
`bootblock_mainboard_init()` function.

Specifically, this commit:
- Calls `setup_chromeos_gpios()` to conditionally sets up GPIOs for
  the FPMCU (reset, boot mode, power rails).

BUG=b:496650089
TEST=Able to build google/mensa.

Change-Id: I0c7f1e4c666c87b9bb5e1b3c615b3f04c0e8c423
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91905
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
---
 src/mainboard/google/mensa/Kconfig    | 22 ++++++++++++++++++++++
 src/mainboard/google/mensa/board.h    | 14 ++++++++++++++
 src/mainboard/google/mensa/chromeos.c |  9 +++++++++
 3 files changed, 45 insertions(+)

diff --git a/src/mainboard/google/mensa/Kconfig b/src/mainboard/google/mensa/Kconfig
index 5948aed0ad..a16f312ea7 100644
--- a/src/mainboard/google/mensa/Kconfig
+++ b/src/mainboard/google/mensa/Kconfig
@@ -24,6 +24,7 @@ config BOARD_GOOGLE_MODEL_MENSA
 
 config BOARD_GOOGLE_MENSA
 	select BOARD_GOOGLE_MODEL_MENSA
+	select MAINBOARD_HAS_FINGERPRINT_VIA_SPI
 	select SOC_QUALCOMM_CALYPSO
 
 if BOARD_GOOGLE_MENSA_COMMON
@@ -31,6 +32,27 @@ if BOARD_GOOGLE_MENSA_COMMON
 config MAINBOARD_DIR
 	default "google/mensa"
 
+config MAINBOARD_HAS_FINGERPRINT_VIA_SPI
+	bool
+	default n
+	help
+	  Enable this option if your mainboard's fingerprint reader
+	  is connected via the SPI interface.
+
+config MAINBOARD_HAS_FINGERPRINT_VIA_USB
+	bool
+	default n
+	help
+	  Enable this option if your mainboard's fingerprint reader
+	  is connected via the USB interface.
+
+config MAINBOARD_HAS_FINGERPRINT
+	bool
+	default y if MAINBOARD_HAS_FINGERPRINT_VIA_SPI || MAINBOARD_HAS_FINGERPRINT_VIA_USB
+	help
+	  Enable this option if your mainboard is equipped with an onboard
+	  fingerprint reader. This could be connected via SPI or USB.
+
 config MAINBOARD_HAS_GOOGLE_TPM
 	bool
 	default n
diff --git a/src/mainboard/google/mensa/board.h b/src/mainboard/google/mensa/board.h
index 72fc39fadf..f7225480e0 100644
--- a/src/mainboard/google/mensa/board.h
+++ b/src/mainboard/google/mensa/board.h
@@ -11,6 +11,20 @@
 #define GSC_AP_INT(x)		GPIO(x)
 #define GPIO_GSC_AP_INT		GSC_AP_INT(CONFIG_MAINBOARD_GPIO_PIN_FOR_GSC_AP_INTERRUPT)
 
+/* Fingerprint-specific GPIOs. Only for fingerprint-enabled devices. */
+#if CONFIG(MAINBOARD_HAS_FINGERPRINT)
+#define GPIO_FP_RST_L		GPIO(25)
+#if CONFIG(MAINBOARD_HAS_FINGERPRINT_VIA_SPI)
+#define GPIO_FPMCU_BOOT0	GPIO(24)
+#define GPIO_FPMCU_INT		GPIO(23)
+#define GPIO_EN_FP_RAILS	GPIO(22)
+#else
+#define GPIO_FPMCU_BOOT0	dead_code_t(gpio_t)
+#define GPIO_FPMCU_INT		dead_code_t(gpio_t)
+#define GPIO_EN_FP_RAILS	dead_code_t(gpio_t)
+#endif
+#endif
+
 void setup_chromeos_gpios(void);
 
 #endif /* MAINBOARD_GOOGLE_MENSA_BOARD_H */
diff --git a/src/mainboard/google/mensa/chromeos.c b/src/mainboard/google/mensa/chromeos.c
index 646bd1164e..ec2bfe7245 100644
--- a/src/mainboard/google/mensa/chromeos.c
+++ b/src/mainboard/google/mensa/chromeos.c
@@ -12,6 +12,15 @@ void setup_chromeos_gpios(void)
 
 	if (CONFIG(TPM_GOOGLE_TI50))
 		gpio_input_irq(GPIO_GSC_AP_INT, IRQ_TYPE_RISING_EDGE, GPIO_PULL_UP);
+
+	if (CONFIG(MAINBOARD_HAS_FINGERPRINT)) {
+		gpio_output(GPIO_FP_RST_L, 0);
+		if (CONFIG(MAINBOARD_HAS_FINGERPRINT_VIA_SPI)) {
+			gpio_output(GPIO_FPMCU_BOOT0, 0);
+			gpio_output(GPIO_EN_FP_RAILS, 0);
+			gpio_input_irq(GPIO_FPMCU_INT, IRQ_TYPE_LEVEL, GPIO_PULL_UP);
+		}
+	}
 }
 
 void fill_lb_gpios(struct lb_gpios *gpios)

From ba3b83e51e21b24d5c231d8d1a2e03c8975280ba Mon Sep 17 00:00:00 2001
From: Subrata Banik <subratabanik@google.com>
Date: Sat, 28 Mar 2026 07:22:39 +0000
Subject: [PATCH 3856/3886] mb/google/mensa: Implement SKU ID retrieval

Implement the sku_id() function for the Mensa mainboard to replace
the existing placeholder.

The SKU ID is retrieved from the Chrome EC using the common
google_chromeec_get_board_sku() interface. To optimize performance and
avoid redundant SPI transactions to the EC, the value is cached
after the initial read.

BUG=b:496650089
TEST=Build and boot on Mensa; verify SKU ID is correctly reported in
cbmem logs.

Change-Id: Ibaef20913e8043a02b2468d1157ac1a4a2087fc6
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91906
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
---
 src/mainboard/google/mensa/boardid.c | 8 +++++++-
 1 file changed, 7 insertions(+), 1 deletion(-)

diff --git a/src/mainboard/google/mensa/boardid.c b/src/mainboard/google/mensa/boardid.c
index b529ff1ec1..c7eaf9cf41 100644
--- a/src/mainboard/google/mensa/boardid.c
+++ b/src/mainboard/google/mensa/boardid.c
@@ -1,6 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
 #include <boardid.h>
+#include <ec/google/chromeec/ec.h>
 
 uint32_t board_id(void)
 {
@@ -12,6 +13,11 @@ uint32_t board_id(void)
 uint32_t sku_id(void)
 {
 	static uint32_t id = UNDEFINED_STRAPPING_ID;
-	/* Placeholder */
+	if (id != UNDEFINED_STRAPPING_ID)
+		return id;
+
+	if (CONFIG(EC_GOOGLE_CHROMEEC))
+		id = google_chromeec_get_board_sku();
+
 	return id;
 }

From 30b8524ff5f9973b694877c8f9df680260dadce9 Mon Sep 17 00:00:00 2001
From: Subrata Banik <subratabanik@google.com>
Date: Sat, 28 Mar 2026 07:29:01 +0000
Subject: [PATCH 3857/3886] soc/qualcomm/calypso: Enable basic PCIe support

This commit introduces initial support for PCI Express on the
Qualcomm Calypso SoC.

Key changes include:
- Selecting `CONFIG_PCI` in Kconfig to enable general PCI subsystem
  support for this SoC.
- Selecting `CONFIG_NO_ECAM_MMCONF_SUPPORT`, indicating that this
  platform will not use the standard MMCONFIG ECAM for PCI
  configuration space access. An alternative mechanism will be required.
- Adding `../common/pcie_common.c` to the ramstage build if `CONFIG_PCI`
  is enabled, incorporating common PCIe helper functions.

BUG=b:496650089
TEST=Able to build google/calypso.

Change-Id: I813e0811e9fd5b6ceefbf72635998a26536987c8
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91907
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
---
 src/soc/qualcomm/calypso/Kconfig     | 2 ++
 src/soc/qualcomm/calypso/Makefile.mk | 1 +
 2 files changed, 3 insertions(+)

diff --git a/src/soc/qualcomm/calypso/Kconfig b/src/soc/qualcomm/calypso/Kconfig
index 0920a751d5..4a1892cdd9 100644
--- a/src/soc/qualcomm/calypso/Kconfig
+++ b/src/soc/qualcomm/calypso/Kconfig
@@ -21,6 +21,8 @@ config SOC_QUALCOMM_CALYPSO_BASE
 	select HAVE_UART_SPECIAL
 	select MAINBOARD_FORCE_NATIVE_VGA_INIT
 	select MAINBOARD_HAS_NATIVE_VGA_INIT
+	select NO_ECAM_MMCONF_SUPPORT
+	select PCI
 	select SOC_QUALCOMM_COMMON
 	select SOC_QUALCOMM_QCLIB_SKIP_MMU_TOGGLE
 
diff --git a/src/soc/qualcomm/calypso/Makefile.mk b/src/soc/qualcomm/calypso/Makefile.mk
index 01546a9f2f..cfe46cf734 100644
--- a/src/soc/qualcomm/calypso/Makefile.mk
+++ b/src/soc/qualcomm/calypso/Makefile.mk
@@ -40,6 +40,7 @@ ramstage-y += soc.c
 ramstage-y += cbmem.c
 ramstage-y += ../common/mmu.c
 ramstage-$(CONFIG_DRIVERS_UART) += ../common/qupv3_uart.c
+ramstage-$(CONFIG_PCI) += ../common/pcie_common.c
 ramstage-y += cpucp_load_reset.c
 
 ################################################################################

From e2c419bc44d78192e90c9125e5537733b87e8f61 Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Tue, 3 Mar 2026 12:09:43 -0600
Subject: [PATCH 3858/3886] mb/google/zork: Use level-triggered IRQ for
 touchscreens

Change Raydium and ELAN touchscreen IRQ from edge to level triggering
across berknip, dalboz, ezkinil, trembyle, and vilboz variants.
Necessary for Windows driver compatibility.

TEST=build/boot Win11/Linux on ezkinil; verify touchscreen functional.

Change-Id: I126589f9412f405d69961919bf61c4c60f623676
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91789
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
---
 src/mainboard/google/zork/variants/berknip/overridetree.cb  | 4 ++--
 src/mainboard/google/zork/variants/dalboz/overridetree.cb   | 4 ++--
 src/mainboard/google/zork/variants/ezkinil/overridetree.cb  | 2 +-
 src/mainboard/google/zork/variants/trembyle/overridetree.cb | 4 ++--
 src/mainboard/google/zork/variants/vilboz/overridetree.cb   | 2 +-
 5 files changed, 8 insertions(+), 8 deletions(-)

diff --git a/src/mainboard/google/zork/variants/berknip/overridetree.cb b/src/mainboard/google/zork/variants/berknip/overridetree.cb
index 3a6c74a105..17c4117fd5 100644
--- a/src/mainboard/google/zork/variants/berknip/overridetree.cb
+++ b/src/mainboard/google/zork/variants/berknip/overridetree.cb
@@ -145,7 +145,7 @@ chip soc/amd/picasso
 			register "hid" = ""RAYD0001""
 			register "desc" = ""Raydium Touchscreen""
 			register "detect" = "1"
-			register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_LOW(GPIO_12)"
+			register "irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPIO_12)"
 			register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_90)"
 			register "enable_delay_ms" = "1"
 			register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPIO_140)"
@@ -159,7 +159,7 @@ chip soc/amd/picasso
 			register "hid" = ""ELAN0001""
 			register "desc" = ""ELAN Touchscreen""
 			register "detect" = "1"
-			register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_LOW(GPIO_12)"
+			register "irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPIO_12)"
 			register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_90)"
 			register "enable_delay_ms" = "1"
 			register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPIO_140)"
diff --git a/src/mainboard/google/zork/variants/dalboz/overridetree.cb b/src/mainboard/google/zork/variants/dalboz/overridetree.cb
index ffba885359..1f14c01fb1 100644
--- a/src/mainboard/google/zork/variants/dalboz/overridetree.cb
+++ b/src/mainboard/google/zork/variants/dalboz/overridetree.cb
@@ -47,7 +47,7 @@ chip soc/amd/picasso
 			register "hid" = ""RAYD0001""
 			register "desc" = ""Raydium Touchscreen""
 			register "detect" = "1"
-			register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_LOW(GPIO_12)"
+			register "irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPIO_12)"
 			register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPIO_140)"
 			# 32ms: Rise time of the reset line
 			# 20ms: Firmware ready time
@@ -59,7 +59,7 @@ chip soc/amd/picasso
 			register "hid" = ""ELAN0001""
 			register "desc" = ""ELAN Touchscreen""
 			register "detect" = "1"
-			register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_LOW(GPIO_12)"
+			register "irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPIO_12)"
 			register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPIO_140)"
 			register "reset_delay_ms" = "20"
 			register "has_power_resource" = "true"
diff --git a/src/mainboard/google/zork/variants/ezkinil/overridetree.cb b/src/mainboard/google/zork/variants/ezkinil/overridetree.cb
index dc18940866..07feb98968 100644
--- a/src/mainboard/google/zork/variants/ezkinil/overridetree.cb
+++ b/src/mainboard/google/zork/variants/ezkinil/overridetree.cb
@@ -103,7 +103,7 @@ chip soc/amd/picasso
 			register "hid" = ""RAYD0001""
 			register "desc" = ""Raydium Touchscreen""
 			register "detect" = "1"
-			register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_LOW(GPIO_12)"
+			register "irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPIO_12)"
 			register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_90)"
 			register "enable_delay_ms" = "1"
 			register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPIO_140)"
diff --git a/src/mainboard/google/zork/variants/trembyle/overridetree.cb b/src/mainboard/google/zork/variants/trembyle/overridetree.cb
index 62d324688f..c6a50ec70e 100644
--- a/src/mainboard/google/zork/variants/trembyle/overridetree.cb
+++ b/src/mainboard/google/zork/variants/trembyle/overridetree.cb
@@ -94,7 +94,7 @@ chip soc/amd/picasso
 			register "hid" = ""RAYD0001""
 			register "desc" = ""Raydium Touchscreen""
 			register "detect" = "1"
-			register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_LOW(GPIO_12)"
+			register "irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPIO_12)"
 			register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPIO_140)"
 			# 32ms: Rise time of the reset line
 			# 20ms: Firmware ready time
@@ -108,7 +108,7 @@ chip soc/amd/picasso
 			register "hid" = ""ELAN0001""
 			register "desc" = ""ELAN Touchscreen""
 			register "detect" = "1"
-			register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_LOW(GPIO_12)"
+			register "irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPIO_12)"
 			register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPIO_140)"
 			register "reset_delay_ms" = "20"
 			register "has_power_resource" = "true"
diff --git a/src/mainboard/google/zork/variants/vilboz/overridetree.cb b/src/mainboard/google/zork/variants/vilboz/overridetree.cb
index 8740611c6a..69ca9b5607 100644
--- a/src/mainboard/google/zork/variants/vilboz/overridetree.cb
+++ b/src/mainboard/google/zork/variants/vilboz/overridetree.cb
@@ -249,7 +249,7 @@ chip soc/amd/picasso
 			register "hid" = ""ELAN0001""
 			register "desc" = ""ELAN Touchscreen""
 			register "detect" = "1"
-			register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_LOW(GPIO_12)"
+			register "irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPIO_12)"
 			register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_32)"
 			register "enable_delay_ms" = "1"
 			register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPIO_140)"

From fd5b6323ea404e563df424aef44eca49e06f05f8 Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Tue, 3 Mar 2026 12:03:14 -0600
Subject: [PATCH 3859/3886] mb/google/zork: Use GpioInt wake for touchpad and
 fingerprint reader

Windows ACPI rejects devices that use both GpioInt in _CRS and a GPE in
_PRW (BSOD 0x1000D). Switch touchpad and fingerprint reader to
ACPI_GPIO_IRQ_*_WAKE so wake is expressed via GpioInt SharedAndWake
instead of a separate _PRW GPE, keeping wake support while staying
Windows-compliant.

TEST=build/boot Win11 on morphius

Change-Id: I2a47b8435fb19ec39d19e09967defa91ae58a85b
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91790
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 .../google/zork/variants/berknip/overridetree.cb         | 9 +++------
 .../google/zork/variants/dalboz/overridetree.cb          | 6 ++----
 .../google/zork/variants/dirinboz/overridetree.cb        | 3 +--
 .../google/zork/variants/ezkinil/overridetree.cb         | 6 ++----
 .../google/zork/variants/gumboz/overridetree.cb          | 3 +--
 .../google/zork/variants/morphius/overridetree.cb        | 9 +++------
 .../google/zork/variants/shuboz/overridetree.cb          | 6 ++----
 .../google/zork/variants/trembyle/overridetree.cb        | 9 +++------
 .../google/zork/variants/vilboz/overridetree.cb          | 6 ++----
 .../google/zork/variants/woomax/overridetree.cb          | 3 +--
 10 files changed, 20 insertions(+), 40 deletions(-)

diff --git a/src/mainboard/google/zork/variants/berknip/overridetree.cb b/src/mainboard/google/zork/variants/berknip/overridetree.cb
index 17c4117fd5..1be6e46068 100644
--- a/src/mainboard/google/zork/variants/berknip/overridetree.cb
+++ b/src/mainboard/google/zork/variants/berknip/overridetree.cb
@@ -126,8 +126,7 @@ chip soc/amd/picasso
 		chip drivers/i2c/generic
 			register "hid" = ""ELAN0000""
 			register "desc" = ""ELAN Touchpad""
-			register "irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPIO_9)"
-			register "wake" = "GEVENT_22"
+			register "irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW_WAKE(GPIO_9)"
 			register "detect" = "1"
 			device i2c 15 on end
 		end
@@ -135,8 +134,7 @@ chip soc/amd/picasso
 			register "generic.hid" = ""SYNA0000""
 			register "generic.cid" = ""ACPI0C50""
 			register "generic.desc" = ""Synaptics Touchpad""
-			register "generic.irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPIO_9)"
-			register "generic.wake" = "GEVENT_22"
+			register "generic.irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW_WAKE(GPIO_9)"
 			register "generic.detect" = "1"
 			register "hid_desc_reg_offset" = "0x20"
 			device i2c 2c on end
@@ -188,8 +186,7 @@ chip soc/amd/picasso
 			register "desc" = ""Fingerprint Reader""
 			register "hid" = "ACPI_DT_NAMESPACE_HID"
 			register "compat_string" = ""google,cros-ec-uart""
-			register "irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPIO_6)"
-			register "wake" = "GEVENT_10"
+			register "irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW_WAKE(GPIO_6)"
 			register "uart" = "ACPI_UART_RAW_DEVICE(3000000, 64)"
 			device generic 0 on end
 		end
diff --git a/src/mainboard/google/zork/variants/dalboz/overridetree.cb b/src/mainboard/google/zork/variants/dalboz/overridetree.cb
index 1f14c01fb1..63d4e0c641 100644
--- a/src/mainboard/google/zork/variants/dalboz/overridetree.cb
+++ b/src/mainboard/google/zork/variants/dalboz/overridetree.cb
@@ -93,8 +93,7 @@ chip soc/amd/picasso
 		chip drivers/i2c/generic
 			register "hid" = ""ELAN0000""
 			register "desc" = ""ELAN Touchpad""
-			register "irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPIO_9)"
-			register "wake" = "GEVENT_22"
+			register "irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW_WAKE(GPIO_9)"
 			register "detect" = "1"
 			device i2c 15 on end
 		end
@@ -102,8 +101,7 @@ chip soc/amd/picasso
 			register "generic.hid" = ""SYNA0000""
 			register "generic.cid" = ""ACPI0C50""
 			register "generic.desc" = ""Synaptics Touchpad""
-			register "generic.irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPIO_9)"
-			register "generic.wake" = "GEVENT_22"
+			register "generic.irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW_WAKE(GPIO_9)"
 			register "generic.detect" = "1"
 			register "hid_desc_reg_offset" = "0x20"
 			device i2c 2c on end
diff --git a/src/mainboard/google/zork/variants/dirinboz/overridetree.cb b/src/mainboard/google/zork/variants/dirinboz/overridetree.cb
index f7cdad96e3..0a4437f5f8 100644
--- a/src/mainboard/google/zork/variants/dirinboz/overridetree.cb
+++ b/src/mainboard/google/zork/variants/dirinboz/overridetree.cb
@@ -198,8 +198,7 @@ chip soc/amd/picasso
 		chip drivers/i2c/generic
 			register "hid" = ""ELAN0000""
 			register "desc" = ""ELAN Touchpad""
-			register "irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPIO_9)"
-			register "wake" = "GEVENT_22"
+			register "irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW_WAKE(GPIO_9)"
 			register "detect" = "1"
 			device i2c 15 on end
 		end
diff --git a/src/mainboard/google/zork/variants/ezkinil/overridetree.cb b/src/mainboard/google/zork/variants/ezkinil/overridetree.cb
index 07feb98968..e3d935ca78 100644
--- a/src/mainboard/google/zork/variants/ezkinil/overridetree.cb
+++ b/src/mainboard/google/zork/variants/ezkinil/overridetree.cb
@@ -84,8 +84,7 @@ chip soc/amd/picasso
 		chip drivers/i2c/generic
 			register "hid" = ""ELAN0000""
 			register "desc" = ""ELAN Touchpad""
-			register "irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPIO_9)"
-			register "wake" = "GEVENT_22"
+			register "irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW_WAKE(GPIO_9)"
 			register "detect" = "1"
 			device i2c 15 on end
 		end
@@ -93,8 +92,7 @@ chip soc/amd/picasso
 			register "generic.hid" = ""SYNA0000""
 			register "generic.cid" = ""ACPI0C50""
 			register "generic.desc" = ""Synaptics Touchpad""
-			register "generic.irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPIO_9)"
-			register "generic.wake" = "GEVENT_22"
+			register "generic.irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW_WAKE(GPIO_9)"
 			register "generic.detect" = "1"
 			register "hid_desc_reg_offset" = "0x20"
 			device i2c 2c on end
diff --git a/src/mainboard/google/zork/variants/gumboz/overridetree.cb b/src/mainboard/google/zork/variants/gumboz/overridetree.cb
index f7cdad96e3..0a4437f5f8 100644
--- a/src/mainboard/google/zork/variants/gumboz/overridetree.cb
+++ b/src/mainboard/google/zork/variants/gumboz/overridetree.cb
@@ -198,8 +198,7 @@ chip soc/amd/picasso
 		chip drivers/i2c/generic
 			register "hid" = ""ELAN0000""
 			register "desc" = ""ELAN Touchpad""
-			register "irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPIO_9)"
-			register "wake" = "GEVENT_22"
+			register "irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW_WAKE(GPIO_9)"
 			register "detect" = "1"
 			device i2c 15 on end
 		end
diff --git a/src/mainboard/google/zork/variants/morphius/overridetree.cb b/src/mainboard/google/zork/variants/morphius/overridetree.cb
index 2e4595ee96..c918aa3c0f 100644
--- a/src/mainboard/google/zork/variants/morphius/overridetree.cb
+++ b/src/mainboard/google/zork/variants/morphius/overridetree.cb
@@ -101,8 +101,7 @@ chip soc/amd/picasso
 		chip drivers/i2c/generic
 			register "hid" = ""ELAN0000""
 			register "desc" = ""ELAN Touchpad""
-			register "irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPIO_9)"
-			register "wake" = "GEVENT_22"
+			register "irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW_WAKE(GPIO_9)"
 			register "detect" = "1"
 			device i2c 15 on end
 		end
@@ -110,8 +109,7 @@ chip soc/amd/picasso
 			register "generic.hid" = ""SYNA0000""
 			register "generic.cid" = ""ACPI0C50""
 			register "generic.desc" = ""Synaptics Touchpad""
-			register "generic.irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPIO_9)"
-			register "generic.wake" = "GEVENT_22"
+			register "generic.irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW_WAKE(GPIO_9)"
 			register "generic.detect" = "1"
 			register "hid_desc_reg_offset" = "0x20"
 			device i2c 2c on end
@@ -151,8 +149,7 @@ chip soc/amd/picasso
 			register "desc" = ""Fingerprint Reader""
 			register "hid" = "ACPI_DT_NAMESPACE_HID"
 			register "compat_string" = ""google,cros-ec-uart""
-			register "irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPIO_6)"
-			register "wake" = "GEVENT_10"
+			register "irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW_WAKE(GPIO_6)"
 			register "uart" = "ACPI_UART_RAW_DEVICE(3000000, 64)"
 			device generic 0 hidden end
 		end
diff --git a/src/mainboard/google/zork/variants/shuboz/overridetree.cb b/src/mainboard/google/zork/variants/shuboz/overridetree.cb
index b0ecb494d9..49250a8e8f 100644
--- a/src/mainboard/google/zork/variants/shuboz/overridetree.cb
+++ b/src/mainboard/google/zork/variants/shuboz/overridetree.cb
@@ -155,8 +155,7 @@ chip soc/amd/picasso
 		chip drivers/i2c/generic
 			register "hid" = ""ELAN0000""
 			register "desc" = ""ELAN Touchpad""
-			register "irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPIO_9)"
-			register "wake" = "GEVENT_22"
+			register "irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW_WAKE(GPIO_9)"
 			register "detect" = "1"
 			device i2c 15 on
 				probe TOUCHPAD REGULAR_TOUCHPAD
@@ -165,8 +164,7 @@ chip soc/amd/picasso
 		chip drivers/i2c/hid
 			register "generic.hid" = ""ELAN2702""
 			register "generic.desc" = ""ELAN Touchpad""
-			register "generic.irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPIO_9)"
-			register "generic.wake" = "GEVENT_22"
+			register "generic.irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW_WAKE(GPIO_9)"
 			register "generic.detect" = "1"
 			register "hid_desc_reg_offset" = "0x01"
 			device i2c 15 on
diff --git a/src/mainboard/google/zork/variants/trembyle/overridetree.cb b/src/mainboard/google/zork/variants/trembyle/overridetree.cb
index c6a50ec70e..fa547c827d 100644
--- a/src/mainboard/google/zork/variants/trembyle/overridetree.cb
+++ b/src/mainboard/google/zork/variants/trembyle/overridetree.cb
@@ -75,8 +75,7 @@ chip soc/amd/picasso
 		chip drivers/i2c/generic
 			register "hid" = ""ELAN0000""
 			register "desc" = ""ELAN Touchpad""
-			register "irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPIO_9)"
-			register "wake" = "GEVENT_22"
+			register "irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW_WAKE(GPIO_9)"
 			register "detect" = "1"
 			device i2c 15 on end
 		end
@@ -84,8 +83,7 @@ chip soc/amd/picasso
 			register "generic.hid" = ""SYNA0000""
 			register "generic.cid" = ""ACPI0C50""
 			register "generic.desc" = ""Synaptics Touchpad""
-			register "generic.irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPIO_9)"
-			register "generic.wake" = "GEVENT_22"
+			register "generic.irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW_WAKE(GPIO_9)"
 			register "generic.detect" = "1"
 			register "hid_desc_reg_offset" = "0x20"
 			device i2c 2c on end
@@ -122,8 +120,7 @@ chip soc/amd/picasso
 			register "desc" = ""Fingerprint Reader""
 			register "hid" = "ACPI_DT_NAMESPACE_HID"
 			register "compat_string" = ""google,cros-ec-uart""
-			register "irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPIO_6)"
-			register "wake" = "GEVENT_10"
+			register "irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW_WAKE(GPIO_6)"
 			register "uart" = "ACPI_UART_RAW_DEVICE(3000000, 64)"
 			device generic 0 on end
 		end
diff --git a/src/mainboard/google/zork/variants/vilboz/overridetree.cb b/src/mainboard/google/zork/variants/vilboz/overridetree.cb
index 69ca9b5607..b694fe0127 100644
--- a/src/mainboard/google/zork/variants/vilboz/overridetree.cb
+++ b/src/mainboard/google/zork/variants/vilboz/overridetree.cb
@@ -275,8 +275,7 @@ chip soc/amd/picasso
 		chip drivers/i2c/generic
 			register "hid" = ""ELAN0000""
 			register "desc" = ""ELAN Touchpad""
-			register "irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPIO_9)"
-			register "wake" = "GEVENT_22"
+			register "irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW_WAKE(GPIO_9)"
 			register "detect" = "1"
 			device i2c 15 on end
 		end
@@ -284,8 +283,7 @@ chip soc/amd/picasso
 			register "generic.hid" = ""SYNA0000""
 			register "generic.cid" = ""ACPI0C50""
 			register "generic.desc" = ""Synaptics Touchpad""
-			register "generic.irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPIO_9)"
-			register "generic.wake" = "GEVENT_22"
+			register "generic.irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW_WAKE(GPIO_9)"
 			register "generic.detect" = "1"
 			register "hid_desc_reg_offset" = "0x20"
 			device i2c 2c on end
diff --git a/src/mainboard/google/zork/variants/woomax/overridetree.cb b/src/mainboard/google/zork/variants/woomax/overridetree.cb
index d0d47aae03..531df37b53 100644
--- a/src/mainboard/google/zork/variants/woomax/overridetree.cb
+++ b/src/mainboard/google/zork/variants/woomax/overridetree.cb
@@ -109,8 +109,7 @@ chip soc/amd/picasso
 		chip drivers/i2c/generic
 			register "hid" = ""ELAN0000""
 			register "desc" = ""ELAN Touchpad""
-			register "irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPIO_9)"
-			register "wake" = "GEVENT_22"
+			register "irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW_WAKE(GPIO_9)"
 			register "detect" = "1"
 			device i2c 15 on end
 		end

From 65858ad5c9721009b7401ec36f2fa66b4b199dd7 Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Fri, 12 Apr 2024 13:28:03 -0500
Subject: [PATCH 3860/3886] mb/google/zork/var/vilboz: Guard GPIO for SAR
 sensor

The GPIO for the proximity sensor, which is only used by ChromeOS for
WiFi power/SAR purposes, causes an IRQ storm under Windows. Only
configure it when building for ChromeOS.

TEST=build/boot Win11 on vilboz

Change-Id: I38955f2e11c7eb412416884b4769e70dd1bde6de
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91791
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
---
 src/mainboard/google/zork/variants/vilboz/gpio.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/src/mainboard/google/zork/variants/vilboz/gpio.c b/src/mainboard/google/zork/variants/vilboz/gpio.c
index e49ae8d8d4..ddb3d3b4d6 100644
--- a/src/mainboard/google/zork/variants/vilboz/gpio.c
+++ b/src/mainboard/google/zork/variants/vilboz/gpio.c
@@ -15,8 +15,10 @@ static const struct soc_amd_gpio bid_1_gpio_set_stage_ram[] = {
 };
 
 static const struct soc_amd_gpio vilboz_gpio_set_stage_ram[] = {
+#if CONFIG(CHROMEOS)
 	/* P sensor INT */
 	PAD_INT(GPIO_40, PULL_NONE, LEVEL_LOW, STATUS_DELIVERY),
+#endif
 	/* LTE_RST_L */
 	PAD_GPO(GPIO_89, HIGH),
 };

From 62abc7aca0ed617cbcdcbf0aad4ac5941cb0464a Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Tue, 3 Mar 2026 12:12:42 -0600
Subject: [PATCH 3861/3886] mb/google/guybrush: Switch touchpad IRQ to level
 triggering

Use ACPI_GPIO_IRQ_LEVEL_LOW instead of EDGE_LOW for Elan touchpads.
Required for Windows driver compatibility.

TEST=build/boot Win11/Linux on dewatt; verify touchpad functional.

Change-Id: I712134860eee456c2c103c2ca8543020c58027f2
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91792
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/google/guybrush/variants/guybrush/overridetree.cb | 2 +-
 .../google/guybrush/variants/nipperkin/overridetree.cb          | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/mainboard/google/guybrush/variants/guybrush/overridetree.cb b/src/mainboard/google/guybrush/variants/guybrush/overridetree.cb
index 669bf15d07..dc2b8f88fc 100644
--- a/src/mainboard/google/guybrush/variants/guybrush/overridetree.cb
+++ b/src/mainboard/google/guybrush/variants/guybrush/overridetree.cb
@@ -81,7 +81,7 @@ chip soc/amd/cezanne
 		chip drivers/i2c/generic
 			register "hid" = ""ELAN0000""
 			register "desc" = ""ELAN Touchpad""
-			register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_LOW(GPIO_9)"
+			register "irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPIO_9)"
 			register "wake" = "GEVENT_22"
 			register "detect" = "1"
 			device i2c 15 on end
diff --git a/src/mainboard/google/guybrush/variants/nipperkin/overridetree.cb b/src/mainboard/google/guybrush/variants/nipperkin/overridetree.cb
index f9845b701b..3e6dd028f0 100644
--- a/src/mainboard/google/guybrush/variants/nipperkin/overridetree.cb
+++ b/src/mainboard/google/guybrush/variants/nipperkin/overridetree.cb
@@ -289,7 +289,7 @@ chip soc/amd/cezanne
 		chip drivers/i2c/generic
 			register "hid" = ""ELAN0000""
 			register "desc" = ""ELAN Touchpad""
-			register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_LOW(GPIO_9)"
+			register "irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPIO_9)"
 			register "wake" = "GEVENT_22"
 			register "detect" = "1"
 			device i2c 15 on end

From 49803f2130215f004bd907aef53bdb98e3f22671 Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Tue, 3 Mar 2026 12:04:44 -0600
Subject: [PATCH 3862/3886] mb/google/guybrush: Use GpioInt wake for touchpad
 and fingerprint reader

Windows ACPI rejects devices that use both GpioInt in _CRS and a GPE in
_PRW (BSOD 0x1000D). Switch touchpad and fingerprint reader to
ACPI_GPIO_IRQ_*_WAKE so wake is expressed via GpioInt SharedAndWake
instead of a separate _PRW GPE, keeping wake support while staying
Windows-compliant.

TEST=build/boot Win11 on dewatt

Change-Id: I04593166aad8d3c2c601ba489237a5f45be95fa2
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91793
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 .../google/guybrush/variants/dewatt/overridetree.cb         | 6 ++----
 .../google/guybrush/variants/guybrush/overridetree.cb       | 6 ++----
 .../google/guybrush/variants/nipperkin/overridetree.cb      | 6 ++----
 3 files changed, 6 insertions(+), 12 deletions(-)

diff --git a/src/mainboard/google/guybrush/variants/dewatt/overridetree.cb b/src/mainboard/google/guybrush/variants/dewatt/overridetree.cb
index f6177006af..9a45731212 100644
--- a/src/mainboard/google/guybrush/variants/dewatt/overridetree.cb
+++ b/src/mainboard/google/guybrush/variants/dewatt/overridetree.cb
@@ -137,8 +137,7 @@ chip soc/amd/cezanne
 		chip drivers/i2c/generic
 			register "hid" = ""ELAN0000""
 			register "desc" = ""ELAN Touchpad""
-			register "irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPIO_9)"
-			register "wake" = "GEVENT_22"
+			register "irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW_WAKE(GPIO_9)"
 			register "detect" = "1"
 			device i2c 15 on end
 		end
@@ -146,8 +145,7 @@ chip soc/amd/cezanne
 			register "generic.hid" = ""SYNA0000""
 			register "generic.cid" = ""ACPI0C50""
 			register "generic.desc" = ""Synaptics Touchpad""
-			register "generic.irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPIO_9)"
-			register "generic.wake" = "GEVENT_22"
+			register "generic.irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW_WAKE(GPIO_9)"
 			register "generic.detect" = "1"
 			register "hid_desc_reg_offset" = "0x20"
 			device i2c 2c on end
diff --git a/src/mainboard/google/guybrush/variants/guybrush/overridetree.cb b/src/mainboard/google/guybrush/variants/guybrush/overridetree.cb
index dc2b8f88fc..c6e9a7a111 100644
--- a/src/mainboard/google/guybrush/variants/guybrush/overridetree.cb
+++ b/src/mainboard/google/guybrush/variants/guybrush/overridetree.cb
@@ -81,8 +81,7 @@ chip soc/amd/cezanne
 		chip drivers/i2c/generic
 			register "hid" = ""ELAN0000""
 			register "desc" = ""ELAN Touchpad""
-			register "irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPIO_9)"
-			register "wake" = "GEVENT_22"
+			register "irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW_WAKE(GPIO_9)"
 			register "detect" = "1"
 			device i2c 15 on end
 		end
@@ -169,8 +168,7 @@ chip soc/amd/cezanne
 			register "desc" = ""Fingerprint Reader""
 			register "hid" = "ACPI_DT_NAMESPACE_HID"
 			register "compat_string" = ""google,cros-ec-uart""
-			register "irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPIO_21)"
-			register "wake" = "GEVENT_5"
+			register "irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW_WAKE(GPIO_21)"
 			register "uart" = "ACPI_UART_RAW_DEVICE(3000000, 64)"
 			register "has_power_resource" = "true"
 			register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPIO_11)"
diff --git a/src/mainboard/google/guybrush/variants/nipperkin/overridetree.cb b/src/mainboard/google/guybrush/variants/nipperkin/overridetree.cb
index 3e6dd028f0..9b3cb03bb0 100644
--- a/src/mainboard/google/guybrush/variants/nipperkin/overridetree.cb
+++ b/src/mainboard/google/guybrush/variants/nipperkin/overridetree.cb
@@ -289,8 +289,7 @@ chip soc/amd/cezanne
 		chip drivers/i2c/generic
 			register "hid" = ""ELAN0000""
 			register "desc" = ""ELAN Touchpad""
-			register "irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPIO_9)"
-			register "wake" = "GEVENT_22"
+			register "irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW_WAKE(GPIO_9)"
 			register "detect" = "1"
 			device i2c 15 on end
 		end
@@ -344,8 +343,7 @@ chip soc/amd/cezanne
 			register "desc" = ""Fingerprint Reader""
 			register "hid" = "ACPI_DT_NAMESPACE_HID"
 			register "compat_string" = ""google,cros-ec-uart""
-			register "irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPIO_21)"
-			register "wake" = "GEVENT_5"
+			register "irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW_WAKE(GPIO_21)"
 			register "uart" = "ACPI_UART_RAW_DEVICE(3000000, 64)"
 			register "has_power_resource" = "true"
 			register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPIO_11)"

From fe445f4b9d580eb33277ee58103db5ae8aec1ea3 Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Tue, 3 Mar 2026 12:24:00 -0600
Subject: [PATCH 3863/3886] mb/google/skyrim: Use level-triggered IRQ for
 touchpad and touchscreen

Change touchpad and touchscreen IRQ from edge to level triggering across
all skyrim variants. Required for Windows driver compatibility.

TEST=build/boot Win11 on frostflow; verify touchpad/screen functional.

Change-Id: Ibbc275112536b4d555b127271ee264414d06c5cb
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91794
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 .../google/skyrim/variants/frostflow/overridetree.cb          | 2 +-
 src/mainboard/google/skyrim/variants/markarth/overridetree.cb | 2 +-
 src/mainboard/google/skyrim/variants/skyrim/overridetree.cb   | 4 ++--
 .../google/skyrim/variants/winterhold/overridetree.cb         | 4 ++--
 4 files changed, 6 insertions(+), 6 deletions(-)

diff --git a/src/mainboard/google/skyrim/variants/frostflow/overridetree.cb b/src/mainboard/google/skyrim/variants/frostflow/overridetree.cb
index c81fe11527..aae585cf59 100644
--- a/src/mainboard/google/skyrim/variants/frostflow/overridetree.cb
+++ b/src/mainboard/google/skyrim/variants/frostflow/overridetree.cb
@@ -54,7 +54,7 @@ chip soc/amd/mendocino
 		chip drivers/i2c/generic
 			register "hid" = ""ELAN0000""
 			register "desc" = ""ELAN Touchpad""
-			register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_LOW(GPIO_40)"
+			register "irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPIO_40)"
 			register "wake" = "GEVENT_20"
 			register "detect" = "1"
 			device i2c 15 on end
diff --git a/src/mainboard/google/skyrim/variants/markarth/overridetree.cb b/src/mainboard/google/skyrim/variants/markarth/overridetree.cb
index 3de0ec84d5..b2be0988d5 100644
--- a/src/mainboard/google/skyrim/variants/markarth/overridetree.cb
+++ b/src/mainboard/google/skyrim/variants/markarth/overridetree.cb
@@ -73,7 +73,7 @@ chip soc/amd/mendocino
 		chip drivers/i2c/generic
 			register "hid" = ""ELAN0000""
 			register "desc" = ""ELAN Touchpad""
-			register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_LOW(GPIO_40)"
+			register "irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPIO_40)"
 			register "wake" = "GEVENT_20"
 			register "detect" = "1"
 			device i2c 15 on end
diff --git a/src/mainboard/google/skyrim/variants/skyrim/overridetree.cb b/src/mainboard/google/skyrim/variants/skyrim/overridetree.cb
index 8272169dda..f16d9279b4 100644
--- a/src/mainboard/google/skyrim/variants/skyrim/overridetree.cb
+++ b/src/mainboard/google/skyrim/variants/skyrim/overridetree.cb
@@ -121,7 +121,7 @@ chip soc/amd/mendocino
 		chip drivers/i2c/generic
 			register "hid" = ""ELAN0000""
 			register "desc" = ""ELAN Touchpad""
-			register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_LOW(GPIO_40)"
+			register "irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPIO_40)"
 			register "wake" = "GEVENT_20"
 			register "detect" = "1"
 			device i2c 15 on end
@@ -149,7 +149,7 @@ chip soc/amd/mendocino
 			register "hid" = ""ELAN0001""
 			register "desc" = ""ELAN Touchscreen""
 			register "detect" = "1"
-			register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_LOW(GPIO_29)"
+			register "irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPIO_29)"
 			register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_131)"
 			register "enable_delay_ms" = "1"
 			register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPIO_136)"
diff --git a/src/mainboard/google/skyrim/variants/winterhold/overridetree.cb b/src/mainboard/google/skyrim/variants/winterhold/overridetree.cb
index 9fcf99f7f7..8c53dc1a4f 100644
--- a/src/mainboard/google/skyrim/variants/winterhold/overridetree.cb
+++ b/src/mainboard/google/skyrim/variants/winterhold/overridetree.cb
@@ -161,7 +161,7 @@ chip soc/amd/mendocino
 		chip drivers/i2c/generic
 			register "hid" = ""ELAN0000""
 			register "desc" = ""ELAN Touchpad""
-			register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_LOW(GPIO_40)"
+			register "irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPIO_40)"
 			register "wake" = "GEVENT_20"
 			register "detect" = "1"
 			device i2c 15 on end
@@ -198,7 +198,7 @@ chip soc/amd/mendocino
 			register "hid" = ""MLFS0000""
 			register "desc" = ""Melfas Touchscreen""
 			register "detect" = "1"
-			register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_LOW(GPIO_29)"
+			register "irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPIO_29)"
 			register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_131)"
 			register "enable_delay_ms" = "1"
 			register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPIO_136)"

From 227dbbad4ac3b519802ca2706eb365b768848004 Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Tue, 3 Mar 2026 12:05:23 -0600
Subject: [PATCH 3864/3886] mb/google/skyrim: Use GpioInt wake for touchpad and
 fingerprint reader

Windows ACPI rejects devices that use both GpioInt in _CRS and a GPE in
_PRW (BSOD 0x1000D). Switch touchpad and fingerprint reader to
ACPI_GPIO_IRQ_*_WAKE so wake is expressed via GpioInt SharedAndWake
instead of a separate _PRW GPE, keeping wake support while staying
Windows-compliant.

TEST=build/boot Win11 on frostflow

Change-Id: I2ced532443e60e9cbb4e482feceab175aed9a155
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91795
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 .../google/skyrim/variants/crystaldrift/overridetree.cb  | 3 +--
 .../google/skyrim/variants/frostflow/overridetree.cb     | 6 ++----
 .../google/skyrim/variants/markarth/overridetree.cb      | 6 ++----
 .../google/skyrim/variants/skyrim/overridetree.cb        | 6 ++----
 .../google/skyrim/variants/winterhold/overridetree.cb    | 9 +++------
 5 files changed, 10 insertions(+), 20 deletions(-)

diff --git a/src/mainboard/google/skyrim/variants/crystaldrift/overridetree.cb b/src/mainboard/google/skyrim/variants/crystaldrift/overridetree.cb
index d42dea7478..42c015038c 100644
--- a/src/mainboard/google/skyrim/variants/crystaldrift/overridetree.cb
+++ b/src/mainboard/google/skyrim/variants/crystaldrift/overridetree.cb
@@ -87,8 +87,7 @@ chip soc/amd/mendocino
 		chip drivers/i2c/hid
 			register "generic.hid" = ""PIXA2635""
 			register "generic.desc" = ""PIXA Touchpad""
-			register "generic.irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPIO_40)"
-			register "generic.wake" = "GEVENT_20"
+			register "generic.irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW_WAKE(GPIO_40)"
 			register "generic.detect" = "1"
 			register "hid_desc_reg_offset" = "0x01"
 			device i2c 15 on end
diff --git a/src/mainboard/google/skyrim/variants/frostflow/overridetree.cb b/src/mainboard/google/skyrim/variants/frostflow/overridetree.cb
index aae585cf59..c913bd9e28 100644
--- a/src/mainboard/google/skyrim/variants/frostflow/overridetree.cb
+++ b/src/mainboard/google/skyrim/variants/frostflow/overridetree.cb
@@ -54,8 +54,7 @@ chip soc/amd/mendocino
 		chip drivers/i2c/generic
 			register "hid" = ""ELAN0000""
 			register "desc" = ""ELAN Touchpad""
-			register "irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPIO_40)"
-			register "wake" = "GEVENT_20"
+			register "irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW_WAKE(GPIO_40)"
 			register "detect" = "1"
 			device i2c 15 on end
 		end
@@ -126,8 +125,7 @@ chip soc/amd/mendocino
 			register "desc" = ""Fingerprint Reader""
 			register "hid" = "ACPI_DT_NAMESPACE_HID"
 			register "compat_string" = ""google,cros-ec-uart""
-			register "irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPIO_24)"
-			register "wake" = "GEVENT_15"
+			register "irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW_WAKE(GPIO_24)"
 			register "uart" = "ACPI_UART_RAW_DEVICE(3000000, 64)"
 			register "has_power_resource" = "true"
 			register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPIO_12)"
diff --git a/src/mainboard/google/skyrim/variants/markarth/overridetree.cb b/src/mainboard/google/skyrim/variants/markarth/overridetree.cb
index b2be0988d5..e5333dc8f6 100644
--- a/src/mainboard/google/skyrim/variants/markarth/overridetree.cb
+++ b/src/mainboard/google/skyrim/variants/markarth/overridetree.cb
@@ -73,8 +73,7 @@ chip soc/amd/mendocino
 		chip drivers/i2c/generic
 			register "hid" = ""ELAN0000""
 			register "desc" = ""ELAN Touchpad""
-			register "irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPIO_40)"
-			register "wake" = "GEVENT_20"
+			register "irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW_WAKE(GPIO_40)"
 			register "detect" = "1"
 			device i2c 15 on end
 		end
@@ -82,8 +81,7 @@ chip soc/amd/mendocino
 			register "generic.hid" = ""SYNA0000""
 			register "generic.cid" = ""ACPI0C50""
 			register "generic.desc" = ""Synaptics Touchpad""
-			register "generic.irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPIO_40)"
-			register "generic.wake" = "GEVENT_20"
+			register "generic.irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW_WAKE(GPIO_40)"
 			register "generic.detect" = "1"
 			register "hid_desc_reg_offset" = "0x20"
 			device i2c 2c on end
diff --git a/src/mainboard/google/skyrim/variants/skyrim/overridetree.cb b/src/mainboard/google/skyrim/variants/skyrim/overridetree.cb
index f16d9279b4..2a6cb3b019 100644
--- a/src/mainboard/google/skyrim/variants/skyrim/overridetree.cb
+++ b/src/mainboard/google/skyrim/variants/skyrim/overridetree.cb
@@ -121,8 +121,7 @@ chip soc/amd/mendocino
 		chip drivers/i2c/generic
 			register "hid" = ""ELAN0000""
 			register "desc" = ""ELAN Touchpad""
-			register "irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPIO_40)"
-			register "wake" = "GEVENT_20"
+			register "irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW_WAKE(GPIO_40)"
 			register "detect" = "1"
 			device i2c 15 on end
 		end
@@ -231,8 +230,7 @@ chip soc/amd/mendocino
 			register "desc" = ""Fingerprint Reader""
 			register "hid" = "ACPI_DT_NAMESPACE_HID"
 			register "compat_string" = ""google,cros-ec-uart""
-			register "irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPIO_24)"
-			register "wake" = "GEVENT_15"
+			register "irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW_WAKE(GPIO_24)"
 			register "uart" = "ACPI_UART_RAW_DEVICE(3000000, 64)"
 			register "has_power_resource" = "true"
 			register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPIO_12)"
diff --git a/src/mainboard/google/skyrim/variants/winterhold/overridetree.cb b/src/mainboard/google/skyrim/variants/winterhold/overridetree.cb
index 8c53dc1a4f..6f015b7dee 100644
--- a/src/mainboard/google/skyrim/variants/winterhold/overridetree.cb
+++ b/src/mainboard/google/skyrim/variants/winterhold/overridetree.cb
@@ -161,16 +161,14 @@ chip soc/amd/mendocino
 		chip drivers/i2c/generic
 			register "hid" = ""ELAN0000""
 			register "desc" = ""ELAN Touchpad""
-			register "irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPIO_40)"
-			register "wake" = "GEVENT_20"
+			register "irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW_WAKE(GPIO_40)"
 			register "detect" = "1"
 			device i2c 15 on end
 		end
 		chip drivers/i2c/hid
 			register "generic.hid" = ""GXTP7863""
 			register "generic.desc" = ""Goodix Touchpad""
-			register "generic.irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPIO_40)"
-			register "generic.wake" = "GEVENT_20"
+			register "generic.irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW_WAKE(GPIO_40)"
 			register "generic.detect" = "1"
 			register "hid_desc_reg_offset" = "0x20"
 			device i2c 2c on end
@@ -243,8 +241,7 @@ chip soc/amd/mendocino
 			register "desc" = ""Fingerprint Reader""
 			register "hid" = "ACPI_DT_NAMESPACE_HID"
 			register "compat_string" = ""google,cros-ec-uart""
-			register "irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPIO_24)"
-			register "wake" = "GEVENT_15"
+			register "irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW_WAKE(GPIO_24)"
 			register "uart" = "ACPI_UART_RAW_DEVICE(3000000, 64)"
 			register "has_power_resource" = "true"
 			register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPIO_12)"

From 45378e6fc24330b8b9e8956f10da65a57fa9cbd1 Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Wed, 18 Mar 2026 20:46:49 -0500
Subject: [PATCH 3865/3886] mb/google/guybrush/dewatt: Mark board as
 convertible

Set SYSTEM_TYPE_CONVERTIBLE for the Dewatt variant so SMBIOS
reports a convertible enclosure type. This allows non-ChromeOS
builds to enable EC_CHROMEEC_USE_VENDOR_TABLET_CONTROLS and use
the vendor tablet mode ACPI.

Change-Id: I01bd8a4255b2cacc01e9eda703e88af57c8f58c7
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91744
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
---
 src/mainboard/google/guybrush/Kconfig | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/src/mainboard/google/guybrush/Kconfig b/src/mainboard/google/guybrush/Kconfig
index dae3bf7170..7007e342af 100644
--- a/src/mainboard/google/guybrush/Kconfig
+++ b/src/mainboard/google/guybrush/Kconfig
@@ -43,18 +43,20 @@ config BOARD_GOOGLE_BASEBOARD_GUYBRUSH
 	select SOC_AMD_COMMON_BLOCK_GRAPHICS_ATIF
 	select SOC_AMD_COMMON_BLOCK_I2C3_TPM_SHARED_WITH_PSP
 	select SOC_AMD_COMMON_BLOCK_USE_ESPI
-	select SYSTEM_TYPE_LAPTOP
 	select TPM_GOOGLE_CR50
 
 config BOARD_GOOGLE_DEWATT
 	select BOARD_GOOGLE_BASEBOARD_GUYBRUSH
+	select SYSTEM_TYPE_CONVERTIBLE
 
 config BOARD_GOOGLE_GUYBRUSH
 	select BOARD_GOOGLE_BASEBOARD_GUYBRUSH
+	select SYSTEM_TYPE_LAPTOP
 
 config BOARD_GOOGLE_NIPPERKIN
 	select BOARD_GOOGLE_BASEBOARD_GUYBRUSH
 	select DRIVERS_GFX_GENERIC
+	select SYSTEM_TYPE_LAPTOP
 
 if BOARD_GOOGLE_BASEBOARD_GUYBRUSH
 

From dbd05fc2dae00fc4d74b0940c0eab0d7a45993c7 Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Wed, 18 Mar 2026 21:02:00 -0500
Subject: [PATCH 3866/3886] mb/google/kahlee: Set correct SYSTEM_TYPE for all
 variants

Set SYSTEM_TYPE_CONVERTIBLE for Kahlee-based Spin/Flip devices
so SMBIOS reports a convertible enclosure type. This enables
EC_CHROMEEC_USE_VENDOR_TABLET_CONTROLS on non-ChromeOS builds
and allows use of the vendor tablet mode ACPI.

Change-Id: I63d815f4cf46aee064db4a23b97c399aa334aad0
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91749
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/google/kahlee/Kconfig | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/src/mainboard/google/kahlee/Kconfig b/src/mainboard/google/kahlee/Kconfig
index 157c317a62..347a40993b 100644
--- a/src/mainboard/google/kahlee/Kconfig
+++ b/src/mainboard/google/kahlee/Kconfig
@@ -37,11 +37,12 @@ config BOARD_GOOGLE_BASEBOARD_KAHLEE
 	select SOC_AMD_COMMON_BLOCK_GRAPHICS_ATIF
 	select SOC_AMD_SMU_FANLESS
 	select SOC_AMD_STONEYRIDGE
-	select SYSTEM_TYPE_LAPTOP
+	select SYSTEM_TYPE_LAPTOP if !SYSTEM_TYPE_CONVERTIBLE
 	select TPM_GOOGLE_CR50
 
 config BOARD_GOOGLE_ALEENA
 	select BOARD_GOOGLE_BASEBOARD_KAHLEE
+	select SYSTEM_TYPE_CONVERTIBLE
 
 config BOARD_GOOGLE_CAREENA
 	select BOARD_GOOGLE_BASEBOARD_KAHLEE
@@ -54,9 +55,11 @@ config BOARD_GOOGLE_LIARA
 
 config BOARD_GOOGLE_NUWANI
 	select BOARD_GOOGLE_BASEBOARD_KAHLEE
+	select SYSTEM_TYPE_CONVERTIBLE
 
 config BOARD_GOOGLE_TREEYA
 	select BOARD_GOOGLE_BASEBOARD_KAHLEE
+	select SYSTEM_TYPE_CONVERTIBLE
 
 if BOARD_GOOGLE_BASEBOARD_KAHLEE
 

From 7eb70b259b12571bca92c5f5d28a3cf2ef607140 Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Wed, 18 Mar 2026 21:05:07 -0500
Subject: [PATCH 3867/3886] mb/google/zork: Set correct SYSTEM_TYPE for all
 variants

Set SYSTEM_TYPE_CONVERTIBLE for Zork-based Spin/Flip devices
so SMBIOS reports a convertible enclosure type. This enables
EC_CHROMEEC_USE_VENDOR_TABLET_CONTROLS on non-ChromeOS builds
and allows use of the vendor tablet mode ACPI.

Change-Id: I53ce5222e6b6984ef6e3b3c89ecfbae7620aaf36
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91752
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
---
 src/mainboard/google/zork/Kconfig | 6 +++++-
 1 file changed, 5 insertions(+), 1 deletion(-)

diff --git a/src/mainboard/google/zork/Kconfig b/src/mainboard/google/zork/Kconfig
index b828a5a004..07ee99b02b 100644
--- a/src/mainboard/google/zork/Kconfig
+++ b/src/mainboard/google/zork/Kconfig
@@ -17,12 +17,15 @@ config BOARD_GOOGLE_DIRINBOZ
 
 config BOARD_GOOGLE_EZKINIL
 	select BOARD_GOOGLE_BASEBOARD_TREMBYLE
+	select SYSTEM_TYPE_CONVERTIBLE
 
 config BOARD_GOOGLE_GUMBOZ
 	select BOARD_GOOGLE_BASEBOARD_DALBOZ
+	select SYSTEM_TYPE_CONVERTIBLE
 
 config BOARD_GOOGLE_MORPHIUS
 	select BOARD_GOOGLE_BASEBOARD_TREMBYLE
+	select SYSTEM_TYPE_CONVERTIBLE
 
 config BOARD_GOOGLE_SHUBOZ
 	select BOARD_GOOGLE_BASEBOARD_DALBOZ
@@ -37,6 +40,7 @@ config BOARD_GOOGLE_VILBOZ
 
 config BOARD_GOOGLE_WOOMAX
 	select BOARD_GOOGLE_BASEBOARD_TREMBYLE
+	select SYSTEM_TYPE_CONVERTIBLE
 
 if BOARD_GOOGLE_BASEBOARD_TREMBYLE || BOARD_GOOGLE_BASEBOARD_DALBOZ
 
@@ -84,7 +88,7 @@ config BOARD_SPECIFIC_OPTIONS
 	select SOC_AMD_COMMON_BLOCK_USE_ESPI
 	select SOC_AMD_COMMON_BLOCK_GRAPHICS_ATIF
 	select SOC_AMD_PICASSO
-	select SYSTEM_TYPE_LAPTOP
+	select SYSTEM_TYPE_LAPTOP if !SYSTEM_TYPE_CONVERTIBLE
 	select TPM_GOOGLE_CR50
 
 config ELOG_BOOT_COUNT_CMOS_OFFSET

From d012a678e28561899a954149ae005178f4666d01 Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Fri, 6 Oct 2023 19:34:38 -0500
Subject: [PATCH 3868/3886] mb/google/guybrush/var/dewatt: Add non-ChromeOS
 TBMC support

The TBMC ACPI device is used by Windows ChromeEC drivers to determine
tablet mode and to enable motion sensors (accelerometer, gyroscope).
Since it's not needed/used by ChromeOS, restrict its inclusion to
non-ChromeOS builds.

TEST=build/boot Win11/Linux on dewatt, verify tablet mode and rotation
work properly, keyboard/touchpad disabled in tablet mode.

Change-Id: I3eeae7b453589a2253226709dd6cfcff1862ea17
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91799
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
---
 .../guybrush/variants/dewatt/include/variant/ec.h      | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/src/mainboard/google/guybrush/variants/dewatt/include/variant/ec.h b/src/mainboard/google/guybrush/variants/dewatt/include/variant/ec.h
index 9e61a440cf..dac67ca295 100644
--- a/src/mainboard/google/guybrush/variants/dewatt/include/variant/ec.h
+++ b/src/mainboard/google/guybrush/variants/dewatt/include/variant/ec.h
@@ -1,3 +1,13 @@
 /* SPDX-License-Identifier: GPL-2.0-or-later */
 
+#ifndef __VARIANT_EC_H__
+#define __VARIANT_EC_H__
+
 #include <baseboard/ec.h>
+
+/* Enable Tablet switch for Windows drivers */
+#if !CONFIG(CHROMEOS)
+#define EC_ENABLE_TBMC_DEVICE
+#endif
+
+#endif

From 102b9b42ae71048c3d1fda05880bb04163d0b7aa Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Fri, 6 Oct 2023 19:34:22 -0500
Subject: [PATCH 3869/3886] mb/google/skyrim/var/frostflow: Add non-ChromeOS
 TBMC support

The TBMC ACPI device is used by Windows ChromeEC drivers to determine
tablet mode and to enable motion sensors (accelerometer, gyroscope).
Since it's not needed/used by ChromeOS, restrict its inclusion to
non-ChromeOS builds.

TEST=build/boot Win11/Linux on frostflow, verify tablet mode and
rotation work properly, keyboard/touchpad disabled in tablet mode.

Change-Id: Iedc68797776d43f37dd97e5251cf9b9a016f1bd5
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91800
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
---
 .../skyrim/variants/frostflow/include/variant/ec.h     | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/src/mainboard/google/skyrim/variants/frostflow/include/variant/ec.h b/src/mainboard/google/skyrim/variants/frostflow/include/variant/ec.h
index 9e61a440cf..dac67ca295 100644
--- a/src/mainboard/google/skyrim/variants/frostflow/include/variant/ec.h
+++ b/src/mainboard/google/skyrim/variants/frostflow/include/variant/ec.h
@@ -1,3 +1,13 @@
 /* SPDX-License-Identifier: GPL-2.0-or-later */
 
+#ifndef __VARIANT_EC_H__
+#define __VARIANT_EC_H__
+
 #include <baseboard/ec.h>
+
+/* Enable Tablet switch for Windows drivers */
+#if !CONFIG(CHROMEOS)
+#define EC_ENABLE_TBMC_DEVICE
+#endif
+
+#endif

From 97d616b927a101fae5b6957d1a749bee43f113c7 Mon Sep 17 00:00:00 2001
From: Patrick Rudolph <patrick.rudolph@9elements.com>
Date: Mon, 21 Jul 2025 15:54:44 +0200
Subject: [PATCH 3870/3886] soc/amd/common/block/spi: Add helper functions

When a mainboard has a secondary SPI flash, also referred to as
DUAL SPIROM or backup SPI flash, and a board specific recovery
mechanism for failed flash updates it might need to access the
secondary SPI flash. A use case would be syncing the MRC cache
(APOB NV on AMD), RPMC and fTPM regions to the secondary flash.

Add generic code to access the "backup" SPI flash. It assumed
that both SPI flash have the same size and same type.
The backup SPI flash chip select line is determined at runtime
so that it is the opposite of boot_device_spi_cs().
Thus when booting from CS2, CS0 will become the backup flash.

TEST=Can access and use backup flash on AMD Glinda SoC.

Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: Ied683408d36850416fc1bbfaef0c415703ff183e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90780
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
---
 .../include/amdblocks/backup_boot_device.h    |  19 ++
 src/soc/amd/common/block/spi/Kconfig          |  20 ++
 src/soc/amd/common/block/spi/Makefile.mk      |   5 +
 .../block/spi/backup_boot_device_rw_nommap.c  | 192 ++++++++++++++++++
 4 files changed, 236 insertions(+)
 create mode 100644 src/soc/amd/common/block/include/amdblocks/backup_boot_device.h
 create mode 100644 src/soc/amd/common/block/spi/backup_boot_device_rw_nommap.c

diff --git a/src/soc/amd/common/block/include/amdblocks/backup_boot_device.h b/src/soc/amd/common/block/include/amdblocks/backup_boot_device.h
new file mode 100644
index 0000000000..6eb4b2b6be
--- /dev/null
+++ b/src/soc/amd/common/block/include/amdblocks/backup_boot_device.h
@@ -0,0 +1,19 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef AMD_BLOCK_BACKUP_BOOT_DEVICE_H
+#define AMD_BLOCK_BACKUP_BOOT_DEVICE_H
+
+#include <commonlib/region.h>
+#include <spi_flash.h>
+
+/* Retrieve the SPI CS index of the backup boot device. */
+int backup_boot_device_spi_cs(void);
+
+const struct region_device *backup_boot_device_rw(void);
+const struct spi_flash *backup_boot_device_spi_flash(void);
+int backup_boot_device_rw_subregion(const struct region *sub,
+				    struct region_device *subrd);
+int backup_boot_device_sync_subregion(const struct region *sub,
+				      const bool direction_prim_to_sec);
+
+#endif
diff --git a/src/soc/amd/common/block/spi/Kconfig b/src/soc/amd/common/block/spi/Kconfig
index 10e88a98bb..76ae3b7a0b 100644
--- a/src/soc/amd/common/block/spi/Kconfig
+++ b/src/soc/amd/common/block/spi/Kconfig
@@ -170,3 +170,23 @@ config SOC_AMD_PSP_ROM_ARMOR_64K_ERASE
 	  Enable 64KB erase block size support in addition to 4KB blocks.
 	  This can improve erase performance when erasing large regions.
 	  The PSP firmware must support 64KB erase commands for this to work.
+
+config SOC_AMD_COMMON_BLOCK_SPI_BACKUP_SPI_FLASH
+	bool
+	depends on SOC_AMD_COMMON_BLOCK_SPI
+	help
+	  Select this option when there is a second SPI flash
+	  which can be booted of when the primary SPI flash is
+	  corrupted. The recovery mechanism is board specific.
+	  The secondary SPI flash must be of the same type and
+	  same size as the primary SPI flash.
+
+config BACKUP_BOOT_DEVICE_SPI_CHIP_SELECT
+	int
+	depends on SOC_AMD_COMMON_BLOCK_SPI_BACKUP_SPI_FLASH
+	default 1
+	help
+	  Which chip select line the backup boot device is connected to.
+	  The assumption here is that chip select 0 and this one have an SPI flash connected to
+	  it. Depending on which chip select of these two we booted from, we deem one of them
+	  our backup/secondary (the one we didn't boot from) SPI flash.
diff --git a/src/soc/amd/common/block/spi/Makefile.mk b/src/soc/amd/common/block/spi/Makefile.mk
index 0dc78d9f3b..36e61e89f5 100644
--- a/src/soc/amd/common/block/spi/Makefile.mk
+++ b/src/soc/amd/common/block/spi/Makefile.mk
@@ -28,4 +28,9 @@ ramstage-y += fch_spi_util.c
 verstage-y += fch_spi_util.c
 smm-$(CONFIG_SPI_FLASH_SMM) += fch_spi_util.c
 
+ifeq ($(CONFIG_SOC_AMD_COMMON_BLOCK_SPI_BACKUP_SPI_FLASH),y)
+all_x86-y += backup_boot_device_rw_nommap.c
+smm-$(CONFIG_SPI_FLASH_SMM) += backup_boot_device_rw_nommap.c
+endif # CONFIG_SOC_AMD_COMMON_BLOCK_SPI_BACKUP_SPI_FLASH
+
 endif # CONFIG_SOC_AMD_COMMON_BLOCK_SPI
diff --git a/src/soc/amd/common/block/spi/backup_boot_device_rw_nommap.c b/src/soc/amd/common/block/spi/backup_boot_device_rw_nommap.c
new file mode 100644
index 0000000000..d1f7b1523e
--- /dev/null
+++ b/src/soc/amd/common/block/spi/backup_boot_device_rw_nommap.c
@@ -0,0 +1,192 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <amdblocks/backup_boot_device.h>
+#include <boot_device.h>
+#include <spi_flash.h>
+#include <spi-generic.h>
+#include <stdint.h>
+#include <string.h>
+
+static struct spi_flash sfg;
+static bool sfg_init_done;
+
+/*
+ * The assumption here is that chip select 0 and CONFIG_BACKUP_BOOT_DEVICE_SPI_CHIP_SELECT have
+ * an SPI flash connected to it. Depending on which chip select of these two we booted from, we
+ * deem one of them our backup/secondary (the one we didn't boot from) SPI flash.
+ */
+int backup_boot_device_spi_cs(void)
+{
+	if (boot_device_spi_cs() == 0)
+		return CONFIG_BACKUP_BOOT_DEVICE_SPI_CHIP_SELECT;
+	return 0;
+}
+
+static ssize_t spi_readat(const struct region_device *rd, void *b,
+				size_t offset, size_t size)
+{
+	if (spi_flash_read(&sfg, offset, size, b))
+		return -1;
+
+	return size;
+}
+
+static ssize_t spi_writeat(const struct region_device *rd, const void *b,
+				size_t offset, size_t size)
+{
+	if (spi_flash_write(&sfg, offset, size, b))
+		return -1;
+
+	return size;
+}
+
+static ssize_t spi_eraseat(const struct region_device *rd,
+				size_t offset, size_t size)
+{
+	if (spi_flash_erase(&sfg, offset, size))
+		return -1;
+
+	return size;
+}
+
+static const struct region_device_ops spi_ops = {
+	.readat = spi_readat,
+	.writeat = spi_writeat,
+	.eraseat = spi_eraseat,
+};
+
+static const struct region_device spi_rw =
+	REGION_DEV_INIT(&spi_ops, 0, CONFIG_ROM_SIZE);
+
+static void backup_boot_device_rw_init(void)
+{
+	const int bus = CONFIG_BOOT_DEVICE_SPI_FLASH_BUS;
+	const int cs = backup_boot_device_spi_cs();
+
+	if (sfg_init_done == true)
+		return;
+
+	/* Ensure any necessary setup is performed by the drivers. */
+	spi_init();
+
+	if (!spi_flash_probe(bus, cs, &sfg))
+		sfg_init_done = true;
+}
+
+/**
+ * Returns the secondary SPI flash as read-writable region device.
+ *
+ * @return NULL on error. The region_device on success.
+ */
+const struct region_device *backup_boot_device_rw(void)
+{
+	/* Probe for the SPI flash device if not already done. */
+	backup_boot_device_rw_init();
+
+	if (sfg_init_done != true)
+		return NULL;
+
+	return &spi_rw;
+}
+
+/**
+ * Returns the secondary SPI flash as spi_flash device.
+ *
+ * @return NULL on error. The region_device on success.
+ */
+const struct spi_flash *backup_boot_device_spi_flash(void)
+{
+	backup_boot_device_rw_init();
+
+	if (sfg_init_done != true)
+		return NULL;
+
+	return &sfg;
+}
+
+/**
+ * Returns a sub-region of the secondary SPI flash.
+ *
+ * @param sub   The subregion within the SPI flash
+ * @param subrd The region_device to return
+ *
+ * @return 0 on success.
+ */
+int backup_boot_device_rw_subregion(const struct region *sub,
+				    struct region_device *subrd)
+{
+	/* Ensure boot device has been initialized at least once. */
+	backup_boot_device_rw_init();
+
+	const struct region_device *parent = backup_boot_device_rw();
+
+	if (!parent)
+		return -1;
+
+	return rdev_chain(subrd, parent, region_offset(sub), region_sz(sub));
+}
+
+/**
+ * Synchronize the SPI flash contents from one chip to the other.
+ *
+ * @param sub                   The region to synchronize
+ * @param direction_prim_to_sec When true synchronize the primary (boot_device_rw())
+ *                              to the secondary (backup_boot_device_rw()).
+ *                              When false synchronize the secondary (backup_boot_device_rw())
+ *                              to the primary (boot_device_rw()):
+ *
+ * @return 0 on success.
+ */
+int backup_boot_device_sync_subregion(const struct region *sub,
+				      const bool direction_prim_to_sec)
+{
+	struct region_device prim, sec;
+	static uint8_t buffer_prim[64 * KiB], buffer_sec[64 * KiB];
+	struct region_device *rdev;
+	void *data;
+	int ret;
+
+	const struct spi_flash *flash = boot_device_spi_flash();
+	if (!flash)
+		return -1;
+
+	ret = boot_device_rw_subregion(sub, &prim);
+	if (ret)
+		return ret;
+
+	ret = backup_boot_device_rw_subregion(sub, &sec);
+	if (ret)
+		return ret;
+
+	/* Set target and source for transfer */
+	rdev = direction_prim_to_sec ? &sec : &prim;
+	data = direction_prim_to_sec ? buffer_prim : buffer_sec;
+
+	size_t remaining = region_device_sz(&prim);
+	size_t offset = 0, written = 0;
+	do {
+		size_t chunk = MIN(remaining, ARRAY_SIZE(buffer_prim));
+		chunk = MIN(chunk, flash->sector_size);
+
+		if (rdev_readat(&prim, buffer_prim, offset, chunk) != chunk)
+			return -1;
+		if (rdev_readat(&sec, buffer_sec, offset, chunk) != chunk)
+			return -1;
+
+		if (memcmp(buffer_prim, buffer_sec, chunk) != 0) {
+			if (rdev_eraseat(rdev, offset, chunk) != chunk)
+				return -1;
+			if (rdev_writeat(rdev, data, offset, chunk) != chunk)
+				return -1;
+			written += chunk;
+		}
+
+		remaining -= chunk;
+		offset += chunk;
+	} while (remaining);
+
+	printk(BIOS_INFO, "%s: Synced %ld bytes from SPI flash %s->%s\n", __func__,
+	       written, direction_prim_to_sec ? "PRIM" : "SEC",
+	       direction_prim_to_sec ? "SEC" : "PRIM");
+	return 0;
+}

From 1b284012b8d0298d372dd509e3657a906a755e87 Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Sun, 22 Mar 2026 20:33:56 +0000
Subject: [PATCH 3871/3886] mb/starlabs/starfighter: add configurable touchpad
 tuning

Apply StarFighter touchpad settings at boot and expose the tuning
controls through CFR.

Add CFR controls for vibration intensity, click force, release force,
and tracking speed. Apply the selected settings during payload boot, and
keep the touchpad controls grouped in a dedicated Trackpad menu.

Change-Id: I3a6a906f7a3ca89e42aa53bb9a4c3dd536c4fe0a
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91817
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
---
 src/mainboard/starlabs/common/Makefile.mk     |   1 +
 .../starlabs/common/include/common/cfr.h      |  61 +++++
 .../starlabs/common/include/common/touchpad.h |  74 ++++++
 .../starlabs/common/touchpad/Makefile.mk      |   3 +
 .../starlabs/common/touchpad/touchpad.c       | 225 ++++++++++++++++++
 src/mainboard/starlabs/starfighter/cfr.c      |  12 +
 6 files changed, 376 insertions(+)
 create mode 100644 src/mainboard/starlabs/common/include/common/touchpad.h
 create mode 100644 src/mainboard/starlabs/common/touchpad/Makefile.mk
 create mode 100644 src/mainboard/starlabs/common/touchpad/touchpad.c

diff --git a/src/mainboard/starlabs/common/Makefile.mk b/src/mainboard/starlabs/common/Makefile.mk
index 6887c47a7d..6bbf96bf2d 100644
--- a/src/mainboard/starlabs/common/Makefile.mk
+++ b/src/mainboard/starlabs/common/Makefile.mk
@@ -2,6 +2,7 @@
 
 subdirs-$(CONFIG_VENDOR_STARLABS) += cfr
 subdirs-$(CONFIG_VENDOR_STARLABS) += hda
+subdirs-$(CONFIG_BOARD_STARLABS_STARFIGHTER_SERIES) += touchpad
 subdirs-$(CONFIG_VENDOR_STARLABS) += powercap
 subdirs-$(CONFIG_VENDOR_STARLABS) += pin_mux
 subdirs-$(CONFIG_VENDOR_STARLABS) += smbios
diff --git a/src/mainboard/starlabs/common/include/common/cfr.h b/src/mainboard/starlabs/common/include/common/cfr.h
index 1a0dabbe86..ce35abe3ae 100644
--- a/src/mainboard/starlabs/common/include/common/cfr.h
+++ b/src/mainboard/starlabs/common/include/common/cfr.h
@@ -6,6 +6,7 @@
 #include <drivers/option/cfr_frontend.h>
 #include <soc/soc_chip.h>
 #include <common/powercap.h>
+#include <common/touchpad.h>
 
 void cfr_card_reader_update(struct sm_object *new_obj);
 void cfr_touchscreen_update(struct sm_object *new_obj);
@@ -111,6 +112,66 @@ static const struct sm_object thunderbolt = SM_DECLARE_BOOL({
 	.default_value	= true,
 });
 
+static const struct sm_object touchpad_haptics = SM_DECLARE_ENUM({
+	.opt_name	= "touchpad_haptics",
+	.ui_name	= "Touchpad Vibration Intensity",
+	.ui_helptext	= "Choose how strong the touchpad click vibration feels.",
+	.default_value	= STARLABS_TOUCHPAD_HAPTICS_DEFAULT,
+	.values		= (const struct sm_enum_value[]) {
+		{ "Off",	0 },
+		{ "Low",	1 },
+		{ "Medium",	2 },
+		{ "High",	3 },
+		{ "Maximum",	4 },
+		SM_ENUM_VALUE_END,
+	},
+});
+
+static const struct sm_object touchpad_force_press = SM_DECLARE_ENUM({
+	.opt_name	= "touchpad_force_press",
+	.ui_name	= "Touchpad Click Force",
+	.ui_helptext	= "Choose how much force it takes to click the touchpad.",
+	.default_value	= STARLABS_TOUCHPAD_PRESS_FORCE_DEFAULT,
+	.values		= (const struct sm_enum_value[]) {
+		{ "Minimal",	STARLABS_TOUCHPAD_FORCE_MINIMAL },
+		{ "Low",	STARLABS_TOUCHPAD_FORCE_LOW },
+		{ "Average",	STARLABS_TOUCHPAD_FORCE_AVERAGE },
+		{ "High",	STARLABS_TOUCHPAD_FORCE_HIGH },
+		{ "Hulk",	STARLABS_TOUCHPAD_FORCE_HULK },
+		SM_ENUM_VALUE_END,
+	},
+});
+
+static const struct sm_object touchpad_force_release = SM_DECLARE_ENUM({
+	.opt_name	= "touchpad_force_release",
+	.ui_name	= "Touchpad Release Force",
+	.ui_helptext	= "Choose how much force it takes for the touchpad click to release.",
+	.default_value	= STARLABS_TOUCHPAD_RELEASE_FORCE_DEFAULT,
+	.values		= (const struct sm_enum_value[]) {
+		{ "Minimal",	STARLABS_TOUCHPAD_FORCE_MINIMAL },
+		{ "Low",	STARLABS_TOUCHPAD_FORCE_LOW },
+		{ "Average",	STARLABS_TOUCHPAD_FORCE_AVERAGE },
+		{ "High",	STARLABS_TOUCHPAD_FORCE_HIGH },
+		{ "Hulk",	STARLABS_TOUCHPAD_FORCE_HULK },
+		SM_ENUM_VALUE_END,
+	},
+});
+
+static const struct sm_object touchpad_report_rate = SM_DECLARE_ENUM({
+	.opt_name	= "touchpad_report_rate",
+	.ui_name	= "Touchpad Tracking Speed",
+	.ui_helptext	= "Choose how quickly the touchpad reports movement.",
+	.default_value	= STARLABS_TOUCHPAD_REPORT_RATE_DEFAULT,
+	.values		= (const struct sm_enum_value[]) {
+		{ "Relaxed",	STARLABS_TOUCHPAD_RATE_RELAXED },
+		{ "Balanced",	STARLABS_TOUCHPAD_RATE_BALANCED },
+		{ "Fast",	STARLABS_TOUCHPAD_RATE_FAST },
+		{ "Ludicrous",	STARLABS_TOUCHPAD_RATE_LUDICROUS },
+		{ "Plaid",	STARLABS_TOUCHPAD_RATE_PLAID },
+		SM_ENUM_VALUE_END,
+	},
+});
+
 static const struct sm_object touchscreen = SM_DECLARE_BOOL({
 	.opt_name	= "touchscreen",
 	.ui_name	= "Touchscreen",
diff --git a/src/mainboard/starlabs/common/include/common/touchpad.h b/src/mainboard/starlabs/common/include/common/touchpad.h
new file mode 100644
index 0000000000..43bd274c1d
--- /dev/null
+++ b/src/mainboard/starlabs/common/include/common/touchpad.h
@@ -0,0 +1,74 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef _STARLABS_CMN_TOUCHPAD_H_
+#define _STARLABS_CMN_TOUCHPAD_H_
+
+#include <stdint.h>
+
+#define STARLABS_TOUCHPAD_HAPTICS_DEFAULT		1
+#define STARLABS_TOUCHPAD_HAPTICS_MAX			4
+
+#define STARLABS_TOUCHPAD_FORCE_MINIMAL		50
+#define STARLABS_TOUCHPAD_FORCE_LOW		125
+#define STARLABS_TOUCHPAD_FORCE_AVERAGE		250
+#define STARLABS_TOUCHPAD_FORCE_HIGH		350
+#define STARLABS_TOUCHPAD_FORCE_HULK		500
+
+#define STARLABS_TOUCHPAD_PRESS_FORCE_DEFAULT		STARLABS_TOUCHPAD_FORCE_HIGH
+#define STARLABS_TOUCHPAD_RELEASE_FORCE_DEFAULT		STARLABS_TOUCHPAD_FORCE_LOW
+
+#define STARLABS_TOUCHPAD_RATE_RELAXED		80
+#define STARLABS_TOUCHPAD_RATE_BALANCED		111
+#define STARLABS_TOUCHPAD_RATE_FAST		160
+#define STARLABS_TOUCHPAD_RATE_LUDICROUS	208
+#define STARLABS_TOUCHPAD_RATE_PLAID		255
+
+#define STARLABS_TOUCHPAD_REPORT_RATE_DEFAULT		111
+#define STARLABS_TOUCHPAD_REPORT_RATE_MIN		1
+#define STARLABS_TOUCHPAD_REPORT_RATE_MAX		255
+
+#define STARLABS_TOUCHPAD_HID_DESC_REG		0x0020
+#define STARLABS_TOUCHPAD_I2C_ADDR		0x2c
+#define STARLABS_TOUCHPAD_I2C_BUS		0
+
+#define STARLABS_TOUCHPAD_HAPTICS_REPORT_ID	0x0a
+#define STARLABS_TOUCHPAD_FORCE_REPORT_ID	0x0b
+#define STARLABS_TOUCHPAD_USER_REG_REPORT_ID	0x43
+#define STARLABS_TOUCHPAD_USER_REG_BANK		0x00
+#define STARLABS_TOUCHPAD_USER_REG_ADDR_RATE	0x12
+
+/*
+ * The HID descriptor may not be live immediately when this hook runs, but
+ * these command/data registers are stable enough to perform early HID bring-up.
+ */
+#define STARLABS_TOUCHPAD_FALLBACK_CMD_REG	0x0022
+#define STARLABS_TOUCHPAD_FALLBACK_DATA_REG	0x0023
+
+#define STARLABS_TOUCHPAD_RETRIES		3
+#define STARLABS_TOUCHPAD_RETRY_DELAY_MS	20
+
+#define I2C_HID_OPCODE_SET_REPORT		0x03
+#define I2C_HID_OPCODE_SET_POWER		0x08
+#define I2C_HID_REPORT_TYPE_FEATURE		0x03
+
+#define I2C_HID_PWR_ON				0x00
+
+enum starlabs_touchpad_desc_offset {
+	TOUCHPAD_DESC_CMD_REG		= 16,
+	TOUCHPAD_DESC_DATA_REG		= 18,
+	TOUCHPAD_DESC_LENGTH		= 30,
+};
+
+struct starlabs_touchpad_op_ctx {
+	unsigned int bus;
+	uint16_t cmd_reg;
+	uint16_t data_reg;
+	uint16_t press;
+	uint16_t release;
+	uint8_t bank;
+	uint8_t addr;
+	uint8_t value;
+	uint8_t level;
+};
+
+#endif /* _STARLABS_CMN_TOUCHPAD_H_ */
diff --git a/src/mainboard/starlabs/common/touchpad/Makefile.mk b/src/mainboard/starlabs/common/touchpad/Makefile.mk
new file mode 100644
index 0000000000..e65f7118d0
--- /dev/null
+++ b/src/mainboard/starlabs/common/touchpad/Makefile.mk
@@ -0,0 +1,3 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
+ramstage-y += touchpad.c
diff --git a/src/mainboard/starlabs/common/touchpad/touchpad.c b/src/mainboard/starlabs/common/touchpad/touchpad.c
new file mode 100644
index 0000000000..c044b7b860
--- /dev/null
+++ b/src/mainboard/starlabs/common/touchpad/touchpad.c
@@ -0,0 +1,225 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <bootstate.h>
+#include <console/console.h>
+#include <delay.h>
+#include <device/i2c_simple.h>
+#include <option.h>
+
+#include <common/touchpad.h>
+
+static uint16_t buf_get_le16(const uint8_t *buf, size_t offset)
+{
+	return (uint16_t)buf[offset] | ((uint16_t)buf[offset + 1] << 8);
+}
+
+static void buf_set_le16(uint8_t *buf, size_t offset, uint16_t value)
+{
+	buf[offset] = value & 0xff;
+	buf[offset + 1] = value >> 8;
+}
+
+static int starlabs_touchpad_read_desc(unsigned int bus, uint8_t *desc)
+{
+	return i2c_2ba_read_bytes(bus, STARLABS_TOUCHPAD_I2C_ADDR,
+				  STARLABS_TOUCHPAD_HID_DESC_REG,
+				  desc, TOUCHPAD_DESC_LENGTH);
+}
+
+static int starlabs_touchpad_set_power(unsigned int bus, uint16_t cmd_reg, uint8_t state)
+{
+	uint8_t buf[4];
+	int ret;
+
+	buf_set_le16(buf, 0, cmd_reg);
+	buf[2] = state;
+	buf[3] = I2C_HID_OPCODE_SET_POWER;
+
+	ret = i2c_write_raw(bus, STARLABS_TOUCHPAD_I2C_ADDR, buf, sizeof(buf));
+	if (ret != 0 && state == I2C_HID_PWR_ON) {
+		udelay(500);
+		ret = i2c_write_raw(bus, STARLABS_TOUCHPAD_I2C_ADDR, buf, sizeof(buf));
+	}
+
+	return ret;
+}
+
+static int starlabs_touchpad_set_haptics(unsigned int bus, uint16_t cmd_reg,
+					 uint16_t data_reg, uint8_t level)
+{
+	uint8_t buf[10];
+
+	buf_set_le16(buf, 0, cmd_reg);
+	buf[2] = (I2C_HID_REPORT_TYPE_FEATURE << 4) |
+		 STARLABS_TOUCHPAD_HAPTICS_REPORT_ID;
+	buf[3] = I2C_HID_OPCODE_SET_REPORT;
+	buf_set_le16(buf, 4, data_reg);
+	buf_set_le16(buf, 6, 4);
+	buf[8] = STARLABS_TOUCHPAD_HAPTICS_REPORT_ID;
+	buf[9] = level;
+
+	return i2c_write_raw(bus, STARLABS_TOUCHPAD_I2C_ADDR, buf, sizeof(buf));
+}
+
+static int starlabs_touchpad_set_force(unsigned int bus, uint16_t cmd_reg,
+				       uint16_t data_reg, uint16_t press,
+				       uint16_t release)
+{
+	uint8_t buf[13];
+
+	buf_set_le16(buf, 0, cmd_reg);
+	buf[2] = (I2C_HID_REPORT_TYPE_FEATURE << 4) |
+		 STARLABS_TOUCHPAD_FORCE_REPORT_ID;
+	buf[3] = I2C_HID_OPCODE_SET_REPORT;
+	buf_set_le16(buf, 4, data_reg);
+	buf_set_le16(buf, 6, 7);
+	buf[8] = STARLABS_TOUCHPAD_FORCE_REPORT_ID;
+	buf_set_le16(buf, 9, press);
+	buf_set_le16(buf, 11, release);
+
+	return i2c_write_raw(bus, STARLABS_TOUCHPAD_I2C_ADDR, buf, sizeof(buf));
+}
+
+static int starlabs_touchpad_write_user_reg(unsigned int bus, uint16_t cmd_reg,
+					    uint16_t data_reg, uint8_t bank,
+					    uint8_t addr, uint8_t value)
+{
+	uint8_t buf[12];
+
+	buf_set_le16(buf, 0, cmd_reg);
+	buf[2] = (I2C_HID_REPORT_TYPE_FEATURE << 4) |
+		 STARLABS_TOUCHPAD_USER_REG_REPORT_ID;
+	buf[3] = I2C_HID_OPCODE_SET_REPORT;
+	buf_set_le16(buf, 4, data_reg);
+	buf_set_le16(buf, 6, 6);
+	buf[8] = STARLABS_TOUCHPAD_USER_REG_REPORT_ID;
+	buf[9] = addr;
+	buf[10] = bank;
+	buf[11] = value;
+
+	return i2c_write_raw(bus, STARLABS_TOUCHPAD_I2C_ADDR, buf, sizeof(buf));
+}
+
+static int starlabs_touchpad_set_haptics_op(void *arg)
+{
+	const struct starlabs_touchpad_op_ctx *ctx = arg;
+
+	return starlabs_touchpad_set_haptics(ctx->bus, ctx->cmd_reg,
+					     ctx->data_reg, ctx->level);
+}
+
+static int starlabs_touchpad_set_force_op(void *arg)
+{
+	const struct starlabs_touchpad_op_ctx *ctx = arg;
+
+	return starlabs_touchpad_set_force(ctx->bus, ctx->cmd_reg,
+					   ctx->data_reg,
+					   ctx->press, ctx->release);
+}
+
+static int starlabs_touchpad_write_user_reg_op(void *arg)
+{
+	const struct starlabs_touchpad_op_ctx *ctx = arg;
+
+	return starlabs_touchpad_write_user_reg(ctx->bus, ctx->cmd_reg,
+						ctx->data_reg, ctx->bank,
+						ctx->addr, ctx->value);
+}
+
+static int starlabs_touchpad_retry(int (*op)(void *arg), void *arg)
+{
+	int ret;
+	int attempt;
+
+	for (attempt = 0; attempt < STARLABS_TOUCHPAD_RETRIES; attempt++) {
+		ret = op(arg);
+		if (ret == 0)
+			return 0;
+		mdelay(STARLABS_TOUCHPAD_RETRY_DELAY_MS);
+	}
+
+	return ret;
+}
+
+static void starlabs_touchpad_apply_settings(void *arg)
+{
+	uint8_t desc[TOUCHPAD_DESC_LENGTH];
+	uint16_t cmd_reg = STARLABS_TOUCHPAD_FALLBACK_CMD_REG;
+	uint16_t data_reg = STARLABS_TOUCHPAD_FALLBACK_DATA_REG;
+	uint16_t desc_cmd_reg;
+	uint16_t desc_data_reg;
+	int have_desc = 0;
+	int ret;
+	struct starlabs_touchpad_op_ctx op_ctx = {
+		.bus = STARLABS_TOUCHPAD_I2C_BUS,
+		.level = get_uint_option("touchpad_haptics",
+					 STARLABS_TOUCHPAD_HAPTICS_DEFAULT),
+		.press = get_uint_option("touchpad_force_press",
+					 STARLABS_TOUCHPAD_PRESS_FORCE_DEFAULT),
+		.release = get_uint_option("touchpad_force_release",
+					   STARLABS_TOUCHPAD_RELEASE_FORCE_DEFAULT),
+		.bank = STARLABS_TOUCHPAD_USER_REG_BANK,
+		.addr = STARLABS_TOUCHPAD_USER_REG_ADDR_RATE,
+		.value = get_uint_option("touchpad_report_rate",
+					 STARLABS_TOUCHPAD_REPORT_RATE_DEFAULT),
+	};
+
+	(void)arg;
+
+	ret = starlabs_touchpad_set_power(STARLABS_TOUCHPAD_I2C_BUS, cmd_reg, I2C_HID_PWR_ON);
+	if (ret != 0) {
+		printk(BIOS_ERR, "Touchpad settings: failed to power on device: %d\n", ret);
+		return;
+	}
+
+	ret = starlabs_touchpad_read_desc(STARLABS_TOUCHPAD_I2C_BUS, desc);
+	if (ret == 0) {
+		desc_cmd_reg = buf_get_le16(desc, TOUCHPAD_DESC_CMD_REG);
+		desc_data_reg = buf_get_le16(desc, TOUCHPAD_DESC_DATA_REG);
+		if (desc_cmd_reg != 0 || desc_data_reg != 0) {
+			cmd_reg = desc_cmd_reg;
+			data_reg = desc_data_reg;
+			have_desc = 1;
+		}
+	}
+
+	if (!have_desc) {
+		printk(BIOS_DEBUG,
+		       "Touchpad settings: HID descriptor stayed zero after power-on, using fallback regs %04x/%04x\n",
+		       cmd_reg, data_reg);
+	} else {
+		printk(BIOS_DEBUG, "Touchpad settings: using HID regs %04x/%04x\n", cmd_reg, data_reg);
+	}
+
+	op_ctx.cmd_reg = cmd_reg;
+	op_ctx.data_reg = data_reg;
+
+	ret = starlabs_touchpad_retry(starlabs_touchpad_set_haptics_op, &op_ctx);
+	if (ret != 0) {
+		printk(BIOS_ERR, "Touchpad settings: failed to set haptics level %u: %d\n",
+		       op_ctx.level, ret);
+		return;
+	}
+
+	ret = starlabs_touchpad_retry(starlabs_touchpad_set_force_op, &op_ctx);
+	if (ret != 0) {
+		printk(BIOS_ERR,
+		       "Touchpad settings: failed to set force thresholds %u/%u: %d\n",
+		       op_ctx.press, op_ctx.release, ret);
+		return;
+	}
+
+	ret = starlabs_touchpad_retry(starlabs_touchpad_write_user_reg_op, &op_ctx);
+	if (ret != 0) {
+		printk(BIOS_ERR, "Touchpad settings: failed to set report rate %u: %d\n",
+		       op_ctx.value, ret);
+		return;
+	}
+
+	printk(BIOS_INFO,
+	       "Touchpad settings: applied haptics=%u click=%u release=%u rate=%u\n",
+	       op_ctx.level, op_ctx.press, op_ctx.release, op_ctx.value);
+}
+
+BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_BOOT, BS_ON_ENTRY, starlabs_touchpad_apply_settings,
+		      NULL);
diff --git a/src/mainboard/starlabs/starfighter/cfr.c b/src/mainboard/starlabs/starfighter/cfr.c
index 9f8132be96..0a3af46dfa 100644
--- a/src/mainboard/starlabs/starfighter/cfr.c
+++ b/src/mainboard/starlabs/starfighter/cfr.c
@@ -67,6 +67,17 @@ static struct sm_obj_form keyboard_group = {
 	},
 };
 
+static struct sm_obj_form trackpad_group = {
+	.ui_name = "Trackpad",
+	.obj_list = (const struct sm_object *[]) {
+		&touchpad_haptics,
+		&touchpad_force_press,
+		&touchpad_force_release,
+		&touchpad_report_rate,
+		NULL
+	},
+};
+
 static struct sm_obj_form leds_group = {
 	.ui_name = "LEDs",
 	.obj_list = (const struct sm_object *[]) {
@@ -156,6 +167,7 @@ static struct sm_obj_form *sm_root[] = {
 	&io_expansion_group,
 	#endif
 	&keyboard_group,
+	&trackpad_group,
 	&leds_group,
 	&pcie_power_management_group,
 	&performance_group,

From d381d33a392eb2c6af642037453ef9be2af4a972 Mon Sep 17 00:00:00 2001
From: Patrick Rudolph <patrick.rudolph@9elements.com>
Date: Wed, 25 Mar 2026 15:44:02 +0100
Subject: [PATCH 3872/3886] soc/soc/amd/glinda: Hook up STX VBIOS

Hook up the VBIOS binary published on the amd_blobs submodule.

TEST=Graphics init works pre OS on AMD/birman+

Change-Id: I927ea1e6dd9be0c13719cf080fc7ca7505f83eba
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91854
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/soc/amd/glinda/Kconfig | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/src/soc/amd/glinda/Kconfig b/src/soc/amd/glinda/Kconfig
index 59c7b3a277..0553034cc1 100644
--- a/src/soc/amd/glinda/Kconfig
+++ b/src/soc/amd/glinda/Kconfig
@@ -117,10 +117,12 @@ config CHIPSET_DEVICETREE
 config VGA_BIOS_FILE
 	string
 	default "3rdparty/amd_blobs/strix_krackan/KRK2E_GENERIC_vbios.sbin" if SOC_AMD_FAEGAN
+	default "3rdparty/amd_blobs/strix_krackan/StrixKrackan_Generic_VBIOS.sbin"
 
 config VGA_BIOS_ID
 	string
-	default "1002,1902"
+	default "1002,1902" if SOC_AMD_FAEGAN
+	default "1002,150e"
 	help
 	  The default VGA BIOS PCI vendor/device ID should be set to the
 	  result of the map_oprom_vendev() function in graphics.c.

From 137b9c59eab4fe2caeb3762183f41c3ca0b3c94a Mon Sep 17 00:00:00 2001
From: Tongtong Pan <pantongtong@huaqin.corp-partner.google.com>
Date: Tue, 24 Mar 2026 21:45:37 +0800
Subject: [PATCH 3873/3886] mb/google/var/fatcat/lapis: adjust
 'cirrus,detect-us' property to  improve the noise situation

When a 3.5 mm headset is connected, noise occurs during system startup
or wake-up from suspend.Setting this value "detect-us" lower should
improve the noise situation, therefore, we adjust detect_us to 100us.

BUG=b/454450799
TEST=cat /sys/kernel/debug/regmap/<sdw_dev>/registers | grep 010040
to ensure the changes take effect and improve the noise situation.
Change-Id: I0c94a1d9862f6e201b451c19f292a12fe3b9ed68
Signed-off-by: Tongtong Pan <pantongtong@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91836
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/google/fatcat/variants/lapis/overridetree.cb | 1 +
 1 file changed, 1 insertion(+)

diff --git a/src/mainboard/google/fatcat/variants/lapis/overridetree.cb b/src/mainboard/google/fatcat/variants/lapis/overridetree.cb
index 3353bf5c8d..80169a62e3 100644
--- a/src/mainboard/google/fatcat/variants/lapis/overridetree.cb
+++ b/src/mainboard/google/fatcat/variants/lapis/overridetree.cb
@@ -508,6 +508,7 @@ chip soc/intel/pantherlake
 						# SoundWire Link 3 ID 0
 						register "desc" = ""Headset Codec""
 						register "sub" = ""1337""
+						register "detect_us" = "DET_100_US"
 						device generic 3.0 on end
 					end
 					chip drivers/soundwire/cs35l56

From 6d3e13a33a29767a2ffd8dd4ccce498958556137 Mon Sep 17 00:00:00 2001
From: Yang Wu <wuyang5@huaqin.corp-partner.google.com>
Date: Fri, 27 Mar 2026 15:55:58 +0800
Subject: [PATCH 3874/3886] mb/google/bluey: Conditionally enable FP rails in
 normal boot

Only enable GPIO_EN_FP_RAILS when booting in LB_BOOT_MODE_NORMAL.

This avoids powering the FP MCU in non-normal boot modes such as
low battery or charging scenarios where FP functionality is not
required.

BUG=b:494962574
TEST=Verified by normal boot and check FP LED.

Change-Id: I7dca803fb3414f7b6b12eb9a8f284a3f1b7b6d87
Signed-off-by: Yang Wu <wuyang5@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91898
Reviewed-by: wen zhang <zhangwen6@huaqin.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/google/bluey/romstage.c | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/src/mainboard/google/bluey/romstage.c b/src/mainboard/google/bluey/romstage.c
index 8fe088e350..3b63839d87 100644
--- a/src/mainboard/google/bluey/romstage.c
+++ b/src/mainboard/google/bluey/romstage.c
@@ -180,8 +180,10 @@ void platform_romstage_main(void)
 	 * when MAINBOARD_HAS_FINGERPRINT_VIA_SPI Kconfig is enabled.
 	 * Requires >=200ms delay after its pin was driven low in bootblock.
 	 */
-	if (CONFIG(MAINBOARD_HAS_FINGERPRINT_VIA_SPI))
-		gpio_output(GPIO_EN_FP_RAILS, 1);
+	if (CONFIG(MAINBOARD_HAS_FINGERPRINT_VIA_SPI)) {
+		if (boot_mode == LB_BOOT_MODE_NORMAL)
+			gpio_output(GPIO_EN_FP_RAILS, 1);
+	}
 }
 
 void platform_romstage_postram(void)

From 66ed61a73c288de56f2f0604ea6e6aa696efe1c2 Mon Sep 17 00:00:00 2001
From: Yanqiong Huang <huangyanqiong@huaqin.corp-partner.google.com>
Date: Tue, 17 Mar 2026 10:51:35 +0800
Subject: [PATCH 3875/3886] b/google/brox/var/lotso: Add RAM ID for
 MT62F1G32D2DS-031RF WT:C

Add support for the new memory Micron MT62F1G32D2DS-031RF WT:C using
spd-3.hex

DRAM Part Name                 ID to assign
K3KL6L60GM-MGCT                0 (0000)
H9JCNNNBK3MLYR-N6E             1 (0001)
K3KL8L80DM-MGCU                2 (0010)
MT62F1G32D2DS-023 WT:C         2 (0010)
H58G56BK8BX068                 2 (0010)
H58G56CK8BX146                 2 (0010)
K3KL8L80EM-MGCU                2 (0010)
H58G56BK7BX068                 3 (0011)
K3KL8L80CM-MGCT                3 (0011)
MT62F1G32D2DS-031RF WT:C       4 (0100)

BUG=b:493358220
TEST=Use part_id_gen to generate related settings

Change-Id: I84e4c408db1e3d3838549028a96c6f05afec81ca
Signed-off-by: Yanqiong Huang <huangyanqiong@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91691
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Rui Zhou <zhourui@huaqin.corp-partner.google.com>
---
 src/mainboard/google/brox/variants/lotso/memory/Makefile.mk    | 1 +
 .../google/brox/variants/lotso/memory/dram_id.generated.txt    | 1 +
 .../google/brox/variants/lotso/memory/mem_parts_used.txt       | 3 ++-
 3 files changed, 4 insertions(+), 1 deletion(-)

diff --git a/src/mainboard/google/brox/variants/lotso/memory/Makefile.mk b/src/mainboard/google/brox/variants/lotso/memory/Makefile.mk
index e38115911f..d5332d9e0b 100644
--- a/src/mainboard/google/brox/variants/lotso/memory/Makefile.mk
+++ b/src/mainboard/google/brox/variants/lotso/memory/Makefile.mk
@@ -8,3 +8,4 @@ SPD_SOURCES += spd/lp5/set-0/spd-9.hex      # ID = 0(0b0000)  Parts = K3KL6L60GM
 SPD_SOURCES += spd/lp5/set-0/spd-1.hex      # ID = 1(0b0001)  Parts = H9JCNNNBK3MLYR-N6E
 SPD_SOURCES += spd/lp5/set-0/spd-11.hex      # ID = 2(0b0010)  Parts = K3KL8L80DM-MGCU, MT62F1G32D2DS-023 WT:C, H58G56BK8BX068, H58G56CK8BX146, K3KL8L80EM-MGCU
 SPD_SOURCES += spd/lp5/set-0/spd-7.hex      # ID = 3(0b0011)  Parts = H58G56BK7BX068, K3KL8L80CM-MGCT
+SPD_SOURCES += spd/lp5/set-0/spd-3.hex      # ID = 4(0b0100)  Parts = MT62F1G32D2DS-031RF WT:C
diff --git a/src/mainboard/google/brox/variants/lotso/memory/dram_id.generated.txt b/src/mainboard/google/brox/variants/lotso/memory/dram_id.generated.txt
index c27f7926ca..e667d7e19d 100644
--- a/src/mainboard/google/brox/variants/lotso/memory/dram_id.generated.txt
+++ b/src/mainboard/google/brox/variants/lotso/memory/dram_id.generated.txt
@@ -13,3 +13,4 @@ H58G56CK8BX146                 2 (0010)
 K3KL8L80EM-MGCU                2 (0010)
 H58G56BK7BX068                 3 (0011)
 K3KL8L80CM-MGCT                3 (0011)
+MT62F1G32D2DS-031RF WT:C       4 (0100)
diff --git a/src/mainboard/google/brox/variants/lotso/memory/mem_parts_used.txt b/src/mainboard/google/brox/variants/lotso/memory/mem_parts_used.txt
index 7df5ad3b41..2ff8b79738 100644
--- a/src/mainboard/google/brox/variants/lotso/memory/mem_parts_used.txt
+++ b/src/mainboard/google/brox/variants/lotso/memory/mem_parts_used.txt
@@ -10,7 +10,6 @@
 
 # Part Name
 K3KL6L60GM-MGCT
-K3KL8L80CM-MGCT
 H9JCNNNBK3MLYR-N6E
 K3KL8L80DM-MGCU
 MT62F1G32D2DS-023 WT:C
@@ -18,3 +17,5 @@ H58G56BK8BX068
 H58G56CK8BX146
 K3KL8L80EM-MGCU
 H58G56BK7BX068
+K3KL8L80CM-MGCT
+MT62F1G32D2DS-031RF WT:C

From c683673095dbfaeee1b2e4d7117872eb1b9e0857 Mon Sep 17 00:00:00 2001
From: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Date: Wed, 25 Mar 2026 14:53:31 +0800
Subject: [PATCH 3876/3886] mb/google/nissa/var/yavilla: Add RAM ID
 H58G56BK8BX068

DRAM Part Name                 ID to assign
H58G56BK8BX068                 7 (0111)

BUG=b:496028135
TEST=build nissa coreboot
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>

Change-Id: Ibf816767acf2d1a2b087365615a68d15bededb98
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91842
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com>
---
 src/mainboard/google/brya/variants/yavilla/memory/Makefile.mk   | 2 +-
 .../google/brya/variants/yavilla/memory/dram_id.generated.txt   | 1 +
 .../google/brya/variants/yavilla/memory/mem_parts_used.txt      | 1 +
 3 files changed, 3 insertions(+), 1 deletion(-)

diff --git a/src/mainboard/google/brya/variants/yavilla/memory/Makefile.mk b/src/mainboard/google/brya/variants/yavilla/memory/Makefile.mk
index 99061e1d12..41dce82b34 100644
--- a/src/mainboard/google/brya/variants/yavilla/memory/Makefile.mk
+++ b/src/mainboard/google/brya/variants/yavilla/memory/Makefile.mk
@@ -11,4 +11,4 @@ SPD_SOURCES += spd/lp5/set-0/spd-7.hex      # ID = 3(0b0011)  Parts = H58G56BK7B
 SPD_SOURCES += spd/lp5/set-0/spd-8.hex      # ID = 4(0b0100)  Parts = H58G66BK7BX067, MT62F2G32D4DS-026 WT:B, K3KL9L90CM-MGCT
 SPD_SOURCES += spd/lp5/set-0/spd-6.hex      # ID = 5(0b0101)  Parts = H58G66AK6BX070, MT62F2G32D4DS-031RF WT:C
 SPD_SOURCES += spd/lp5/set-0/spd-9.hex      # ID = 6(0b0110)  Parts = K3KL6L60GM-MGCT
-SPD_SOURCES += spd/lp5/set-0/spd-11.hex      # ID = 7(0b0111)  Parts = H58G56CK8BX146
+SPD_SOURCES += spd/lp5/set-0/spd-11.hex      # ID = 7(0b0111)  Parts = H58G56CK8BX146, H58G56BK8BX068
diff --git a/src/mainboard/google/brya/variants/yavilla/memory/dram_id.generated.txt b/src/mainboard/google/brya/variants/yavilla/memory/dram_id.generated.txt
index 6b938ba8dd..407538532a 100644
--- a/src/mainboard/google/brya/variants/yavilla/memory/dram_id.generated.txt
+++ b/src/mainboard/google/brya/variants/yavilla/memory/dram_id.generated.txt
@@ -20,3 +20,4 @@ K3KL6L60GM-MGCT                6 (0110)
 H58G56CK8BX146                 7 (0111)
 MT62F1G32D2DS-031RF WT:C       2 (0010)
 MT62F2G32D4DS-031RF WT:C       5 (0101)
+H58G56BK8BX068                 7 (0111)
diff --git a/src/mainboard/google/brya/variants/yavilla/memory/mem_parts_used.txt b/src/mainboard/google/brya/variants/yavilla/memory/mem_parts_used.txt
index d0add1f65a..4fe824fdd8 100644
--- a/src/mainboard/google/brya/variants/yavilla/memory/mem_parts_used.txt
+++ b/src/mainboard/google/brya/variants/yavilla/memory/mem_parts_used.txt
@@ -25,3 +25,4 @@ K3KL6L60GM-MGCT
 H58G56CK8BX146
 MT62F1G32D2DS-031RF WT:C
 MT62F2G32D4DS-031RF WT:C
+H58G56BK8BX068

From 7bcb90047e66874056e97e9ec2f39c93d8287aff Mon Sep 17 00:00:00 2001
From: Qinghong Zeng <zengqinghong@huaqin.corp-partner.google.com>
Date: Tue, 3 Feb 2026 10:28:23 +0800
Subject: [PATCH 3877/3886] mb/google/nissa/var/pujjoniru: Add 2 Micron modules
 to RAM id table

Add support for the new memory Micron MT62F1G32D2DS-031RF WT:C using
spd-3.hex, and MT62F2G32D4DS-031RF WT:C using spd-6.hex

DRAM Part Name                 ID to assign
K3KL6L60GM-MGCT                0 (0000)
H9JCNNNBK3MLYR-N6E             1 (0001)
H58G56CK8BX146                 2 (0010)
MT62F1G32D2DS-026 WT:B         3 (0011)
K3KL8L80CM-MGCT                3 (0011)
MT62F1G32D2DS-031RF WT:C       4 (0100)
MT62F2G32D4DS-031RF WT:C       5 (0101)

BUG=b:493068113
TEST=Normal boot

Change-Id: I03afd40346890e99b2be83dfabc1c3e95ef0bf8c
Signed-off-by: Qinghong Zeng <zengqinghong@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91083
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: hualin wei <weihualin@huaqin.corp-partner.google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
---
 src/mainboard/google/brya/variants/pujjoniru/memory/Makefile.mk | 2 ++
 .../google/brya/variants/pujjoniru/memory/dram_id.generated.txt | 2 ++
 .../google/brya/variants/pujjoniru/memory/mem_parts_used.txt    | 2 ++
 3 files changed, 6 insertions(+)

diff --git a/src/mainboard/google/brya/variants/pujjoniru/memory/Makefile.mk b/src/mainboard/google/brya/variants/pujjoniru/memory/Makefile.mk
index 1cc183961b..8a5168b253 100644
--- a/src/mainboard/google/brya/variants/pujjoniru/memory/Makefile.mk
+++ b/src/mainboard/google/brya/variants/pujjoniru/memory/Makefile.mk
@@ -8,3 +8,5 @@ SPD_SOURCES += spd/lp5/set-0/spd-9.hex      # ID = 0(0b0000)  Parts = K3KL6L60GM
 SPD_SOURCES += spd/lp5/set-0/spd-1.hex      # ID = 1(0b0001)  Parts = H9JCNNNBK3MLYR-N6E
 SPD_SOURCES += spd/lp5/set-0/spd-11.hex      # ID = 2(0b0010)  Parts = H58G56CK8BX146
 SPD_SOURCES += spd/lp5/set-0/spd-7.hex      # ID = 3(0b0011)  Parts = MT62F1G32D2DS-026 WT:B, K3KL8L80CM-MGCT
+SPD_SOURCES += spd/lp5/set-0/spd-3.hex      # ID = 4(0b0100)  Parts = MT62F1G32D2DS-031RF WT:C
+SPD_SOURCES += spd/lp5/set-0/spd-6.hex      # ID = 5(0b0101)  Parts = MT62F2G32D4DS-031RF WT:C
diff --git a/src/mainboard/google/brya/variants/pujjoniru/memory/dram_id.generated.txt b/src/mainboard/google/brya/variants/pujjoniru/memory/dram_id.generated.txt
index 160fd2dd47..a11c24282a 100644
--- a/src/mainboard/google/brya/variants/pujjoniru/memory/dram_id.generated.txt
+++ b/src/mainboard/google/brya/variants/pujjoniru/memory/dram_id.generated.txt
@@ -9,3 +9,5 @@ H9JCNNNBK3MLYR-N6E             1 (0001)
 H58G56CK8BX146                 2 (0010)
 MT62F1G32D2DS-026 WT:B         3 (0011)
 K3KL8L80CM-MGCT                3 (0011)
+MT62F1G32D2DS-031RF WT:C       4 (0100)
+MT62F2G32D4DS-031RF WT:C       5 (0101)
diff --git a/src/mainboard/google/brya/variants/pujjoniru/memory/mem_parts_used.txt b/src/mainboard/google/brya/variants/pujjoniru/memory/mem_parts_used.txt
index 21e9cecfbc..b4b54d09ef 100644
--- a/src/mainboard/google/brya/variants/pujjoniru/memory/mem_parts_used.txt
+++ b/src/mainboard/google/brya/variants/pujjoniru/memory/mem_parts_used.txt
@@ -14,3 +14,5 @@ H9JCNNNBK3MLYR-N6E
 H58G56CK8BX146
 MT62F1G32D2DS-026 WT:B
 K3KL8L80CM-MGCT
+MT62F1G32D2DS-031RF WT:C
+MT62F2G32D4DS-031RF WT:C

From f67b5ed6fdc04bf98e873849ba212ad961537496 Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Thu, 26 Mar 2026 12:43:59 -0500
Subject: [PATCH 3878/3886] util/release: add get_new_authors helper

Add a standalone script to detect new contributors between two local
git refs and print the names and count. Support --update to merge new
names into AUTHORS in sorted order, and --full to include email plus
earliest commit date/hash/subject.

Functionality extracted from genrelnotes script; script largely
generated by Cursor AI.

Change-Id: I5841f68d04522f84e871a80778e0038fd6cba5a9
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91888
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 util/release/get_new_authors | 208 +++++++++++++++++++++++++++++++++++
 1 file changed, 208 insertions(+)
 create mode 100755 util/release/get_new_authors

diff --git a/util/release/get_new_authors b/util/release/get_new_authors
new file mode 100755
index 0000000000..5fb979e0eb
--- /dev/null
+++ b/util/release/get_new_authors
@@ -0,0 +1,208 @@
+#!/usr/bin/env bash
+#
+# SPDX-License-Identifier: GPL-2.0-only
+#
+# Identify new contributors between two git points in time.
+# Optionally update the AUTHORS file with any newly found names.
+
+set -euo pipefail
+
+usage() {
+	echo
+	echo "Usage: $0 [--update] [--full] <old_version> <new_version>"
+	echo
+	echo "Examples:"
+	echo "  $0 24.02 25.01"
+	echo "  $0 --update 24.02 25.01"
+	echo "  $0 --full 24.02 25.01"
+	echo
+	echo "Notes:"
+	echo "  * 'old_version' and 'new_version' can be tags, branches, or commit IDs."
+	echo "  * New contributors are names present in history up to new_version"
+	echo "    that were not present in history up to old_version."
+	echo
+}
+
+fail() {
+	echo "ERROR: $*" >&2
+	exit 1
+}
+
+UPDATE=0
+FULL=0
+
+while [ $# -gt 0 ]; do
+	case "$1" in
+	--update)
+		UPDATE=1
+		shift
+		;;
+	--full)
+		FULL=1
+		shift
+		;;
+	-h|--help)
+		usage
+		exit 0
+		;;
+	--)
+		shift
+		break
+		;;
+	-*)
+		fail "Unknown option: $1"
+		;;
+	*)
+		break
+		;;
+	esac
+done
+
+[ $# -eq 2 ] || { usage; exit 1; }
+
+OLD_GIT_VERSION="$1"
+NEW_GIT_VERSION="$2"
+
+if ! { cdup="$(git rev-parse --show-cdup 2>/dev/null)" && [ -z "${cdup}" ]; }; then
+	fail "This is not the top directory of a git repo."
+fi
+
+git rev-parse --verify "${OLD_GIT_VERSION}^{commit}" >/dev/null 2>&1 || \
+	fail "Invalid old_version: ${OLD_GIT_VERSION}"
+git rev-parse --verify "${NEW_GIT_VERSION}^{commit}" >/dev/null 2>&1 || \
+	fail "Invalid new_version: ${NEW_GIT_VERSION}"
+
+before_emails="$(mktemp)"
+after_emails="$(mktemp)"
+new_emails_tmp="$(mktemp)"
+new_names_tmp="$(mktemp)"
+trap 'rm -f "$before_emails" "$after_emails" "$new_emails_tmp" "$new_names_tmp"' EXIT
+
+git log --pretty=%ae "${OLD_GIT_VERSION}" 2>/dev/null | \
+	awk '{ print tolower($0) }' | sort -u > "$before_emails"
+git log --pretty=%ae "${NEW_GIT_VERSION}" 2>/dev/null | \
+	awk '{ print tolower($0) }' | sort -u > "$after_emails"
+
+grep -Fxv -f "$before_emails" "$after_emails" > "$new_emails_tmp" || true
+NEW_AUTHOR_COUNT="$(wc -l < "$new_emails_tmp" | tr -d ' ')"
+
+# Map each newly seen email to the first author name observed in the target range.
+git log --reverse --pretty=format:'%ae%x1f%an' "${OLD_GIT_VERSION}..${NEW_GIT_VERSION}" | \
+	awk -F '\x1f' '
+		NR == FNR {
+			new_emails[$1] = 1
+			next
+		}
+		{
+			email = tolower($1)
+			if (new_emails[email] && !seen[email]) {
+				print $2
+				seen[email] = 1
+			}
+		}
+	' "$new_emails_tmp" - > "$new_names_tmp"
+
+printf "New contributors between %s and %s:\n" "$OLD_GIT_VERSION" "$NEW_GIT_VERSION"
+if [ "$NEW_AUTHOR_COUNT" -eq 0 ]; then
+	echo "(none)"
+elif [ "$FULL" -eq 0 ]; then
+	cat "$new_names_tmp"
+else
+	while IFS= read -r author_email; do
+		first_commit="$(
+			git log --reverse --date=short \
+				--pretty=format:'%an%x1f%ae%x1f%ad%x1f%H%x1f%s' \
+				"${OLD_GIT_VERSION}..${NEW_GIT_VERSION}" | \
+				awk -F '\x1f' -v author_email="$author_email" '
+					!found && tolower($2) == author_email {
+						print $1 "\x1f" $2 "\x1f" $3 "\x1f" $4 "\x1f" $5
+						found = 1
+					}
+				'
+		)"
+		if [ -z "$first_commit" ]; then
+			printf "* (unknown) | email: %s | date: (unknown) | hash: (unknown) | subject: (unknown)\n" \
+				"$author_email"
+			continue
+		fi
+		IFS=$'\x1f' read -r author_name commit_email first_date first_hash first_subject <<EOF
+$first_commit
+EOF
+		printf "* %s | email: %s | date: %s | hash: %s | subject: %s\n" \
+			"$author_name" "$commit_email" "$first_date" "$first_hash" "$first_subject"
+	done < "$new_emails_tmp"
+fi
+
+printf "\nCount: %s\n" "$NEW_AUTHOR_COUNT"
+
+if [ "$UPDATE" -eq 1 ]; then
+
+	if [ "$NEW_AUTHOR_COUNT" -eq 0 ]; then
+		echo "No AUTHORS update needed."
+		exit 0
+	fi
+
+	AUTHORS_FILE="AUTHORS"
+	[ -f "$AUTHORS_FILE" ] || fail "AUTHORS file not found at repo root."
+
+	header_tmp="$(mktemp)"
+	existing_names_tmp="$(mktemp)"
+	new_names_sorted_tmp="$(mktemp)"
+	working_names_tmp="$(mktemp)"
+	inserted_tmp="$(mktemp)"
+	new_authors_file_tmp="$(mktemp)"
+	trap 'rm -f "$before_emails" "$after_emails" "$new_emails_tmp" "$new_names_tmp" "$header_tmp" "$existing_names_tmp" "$new_names_sorted_tmp" "$working_names_tmp" "$inserted_tmp" "$new_authors_file_tmp"' EXIT
+
+	# Header is the leading comment/blank block.
+	awk '
+		BEGIN { in_header = 1 }
+		in_header && ($0 ~ /^#/ || $0 ~ /^[[:space:]]*$/) { print; next }
+		{ in_header = 0 }
+	' "$AUTHORS_FILE" > "$header_tmp"
+
+	# Names start at the first non-comment, non-blank line.
+	awk '
+		BEGIN { in_names = 0 }
+		!in_names && ($0 ~ /^#/ || $0 ~ /^[[:space:]]*$/) { next }
+		{ in_names = 1; print }
+	' "$AUTHORS_FILE" > "$existing_names_tmp"
+
+	sed '/^[[:space:]]*$/d' "$new_names_tmp" | LC_ALL=C sort -fu > "$new_names_sorted_tmp"
+	cp "$existing_names_tmp" "$working_names_tmp"
+
+	while IFS= read -r new_author; do
+		# Skip if a case-insensitive match already exists.
+		if awk -v new_author="$new_author" '
+			BEGIN { found = 1; target = tolower(new_author) }
+			tolower($0) == target { found = 0; exit }
+			END { exit found }
+		' "$working_names_tmp"; then
+			continue
+		fi
+
+		# Insert at the first case-insensitive position that sorts after new_author.
+		awk -v new_author="$new_author" '
+			BEGIN { inserted = 0; target = tolower(new_author) }
+			{
+				if (!inserted && tolower($0) > target) {
+					print new_author
+					inserted = 1
+				}
+				print
+			}
+			END {
+				if (!inserted)
+					print new_author
+			}
+		' "$working_names_tmp" > "$inserted_tmp"
+		mv "$inserted_tmp" "$working_names_tmp"
+	done < "$new_names_sorted_tmp"
+
+	{
+		cat "$header_tmp"
+		cat "$working_names_tmp"
+	} > "$new_authors_file_tmp"
+
+	mv "$new_authors_file_tmp" "$AUTHORS_FILE"
+	echo "Updated AUTHORS with ${NEW_AUTHOR_COUNT} new contributor(s)."
+fi

From 63fc231480b0911f49b39642aa556f601da3c5f5 Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Thu, 26 Mar 2026 12:53:28 -0500
Subject: [PATCH 3879/3886] AUTHORS: Update with new authors from the 26.03
 release

Updated via 'util/release/get_new_authors --update 25.12 26.03'

Change-Id: I1a024e5a739875218f3395370281be845e7c5ba7
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91889
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
---
 AUTHORS | 13 ++++++++++++-
 1 file changed, 12 insertions(+), 1 deletion(-)

diff --git a/AUTHORS b/AUTHORS
index 21e1cd567f..bd3fc0e95b 100644
--- a/AUTHORS
+++ b/AUTHORS
@@ -207,6 +207,7 @@ Eltan B.V
 Eltan B.V.
 Elyes Haouas
 Emilie Roberts
+Enzo Potenza
 Eran Mitrani
 Eren Peng
 Eric Biederman
@@ -220,6 +221,7 @@ Ethan Tsao
 Eugene Myers
 Evan Green
 Evgeny Zinoviev
+Evie (Ivi) Ballou
 Fabian Groffen
 Fabian Kunkel
 Fabian Meyer
@@ -389,6 +391,7 @@ Kacper Stojek
 Kaiyen Chang
 Kane Chen
 Kangheui Won
+KangMin Wang
 Kapil Porwal
 Karol Zmyslowski
 Karthik Ramasubramanian
@@ -450,6 +453,7 @@ Lubomir Rintel
 Luc Verhaegen
 Luca Lai
 Lucas Chen
+Lukas Wunner
 Mac Chiang
 Maciej Matuszczyk
 Maciej Pijanowski
@@ -603,6 +607,7 @@ Philipp Bartsch
 Philipp Degler
 Philipp Deppenwiese
 Philipp Hug
+Pierce Chou
 Piotr Kleinschmidt
 Po Xu
 Poornima Tom
@@ -614,6 +619,7 @@ Pratikkumar Prajapati
 Pratikkumar V Prajapati
 Protectli
 PugzAreCute
+Purdea Andrei
 Purism, SPC
 Qii Wang
 Qinghong Zeng
@@ -784,6 +790,7 @@ Timothy Pearson
 tinghan shen
 Tobias Diedrich
 Tom Hiller
+Tomasz Michalec
 Tommie Lin
 Tongtong Pan
 Tony Huang
@@ -802,6 +809,7 @@ Usha P
 Uwe Hermann
 Uwe Poeche
 V Sowmya
+Vladimir Epifantsev
 Václav Straka
 Vadim Bendebury
 Valentyn Sudomyr
@@ -860,6 +868,7 @@ YADRO
 Yan Liu
 Yang Wu
 Yann Collet
+Yanqiong Huang
 Yaroslav Kurlaev
 YH Lin
 Yidi Lin
@@ -881,6 +890,7 @@ Zachary Yedidia
 Zanxi Chen
 Zebreus
 Zhanyong Wang
+Zhaoming Luo
 Zhaoqing Jiu
 Zheng Bao
 Zhenguo Li
@@ -894,6 +904,7 @@ Zhuohao Lee
 Ziang Wang
 Zoey Wu
 Zoltan Baldaszti
+一颗小土豆
 小田喜陽彦
 忧郁沙茶
-陳建宏
\ No newline at end of file
+陳建宏

From f45d6e696a44cca89dbbbe8e05790273917fad6e Mon Sep 17 00:00:00 2001
From: Kapil Porwal <kapilporwal@google.com>
Date: Fri, 27 Mar 2026 01:46:49 +0530
Subject: [PATCH 3880/3886] mb/google/bluey: Configure sink sensor for DAM port

Enable/disable the sink sensor for DAM port during power on/off.

BUG=b:491325845
TEST=Verify the configuration on power on/off on Google/Quartz.

Change-Id: Ib00e1cc1c86bafb19cde24c7faa624d3e6d00db8
Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91890
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/google/bluey/board.h     |  1 +
 src/mainboard/google/bluey/charging.c  | 19 +++++++++++++++++++
 src/mainboard/google/bluey/mainboard.c |  1 +
 3 files changed, 21 insertions(+)

diff --git a/src/mainboard/google/bluey/board.h b/src/mainboard/google/bluey/board.h
index b7084a30d5..a4e0d31ce7 100644
--- a/src/mainboard/google/bluey/board.h
+++ b/src/mainboard/google/bluey/board.h
@@ -62,6 +62,7 @@ bool is_off_mode(void);
 void configure_parallel_charging(void);
 void configure_parallel_charging_late(void);
 void configure_debug_access_port(void);
+void configure_dam_on_system_state_change(bool poweron);
 void enable_slow_battery_charging(void);
 void disable_slow_battery_charging(void);
 void launch_charger_applet(void);
diff --git a/src/mainboard/google/bluey/charging.c b/src/mainboard/google/bluey/charging.c
index 1461ab86f9..596891e514 100644
--- a/src/mainboard/google/bluey/charging.c
+++ b/src/mainboard/google/bluey/charging.c
@@ -30,6 +30,10 @@
 #define SCHG_TYPE_C_SUSPEND_LEGACY_CHARGERS 0x2B90
 #define SMB1_SCHG_TYPE_C_SUSPEND_LEGACY_CHARGERS \
 ((SMB1_SLAVE_ID << 16) | SCHG_TYPE_C_SUSPEND_LEGACY_CHARGERS)
+#define SCHG_TYPE_C_TYPE_C_CRUDE_SENSOR_CFG 0x2B4E
+#define SMB1_SCHG_TYPE_C_TYPE_C_CRUDE_SENSOR_CFG \
+((SMB1_SLAVE_ID << 16) | SCHG_TYPE_C_TYPE_C_CRUDE_SENSOR_CFG)
+
 #define SCHG_CHGR_CHARGING_FCC 0x260A
 #define SMB1_CHGR_CHARGING_FCC ((SMB1_SLAVE_ID << 16) | SCHG_CHGR_CHARGING_FCC)
 #define SMB2_CHGR_CHARGING_FCC ((SMB2_SLAVE_ID << 16) | SCHG_CHGR_CHARGING_FCC)
@@ -64,6 +68,16 @@ enum charging_status {
 	CHRG_ENABLE,
 };
 
+void configure_dam_on_system_state_change(bool poweron)
+{
+	uint8_t value = (uint8_t)spmi_read8(SMB1_SCHG_TYPE_C_TYPE_C_CRUDE_SENSOR_CFG);
+	if (poweron)
+		value |= BIT(0);
+	else
+		value &= ~BIT(0);
+	spmi_write8(SMB1_SCHG_TYPE_C_TYPE_C_CRUDE_SENSOR_CFG, value);
+}
+
 static int get_battery_icurr_ma(void)
 {
 	/* Read battery i-current value */
@@ -170,6 +184,7 @@ void launch_charger_applet(void)
 			if (detect_ac_unplug_event())
 				indicate_charging_status();
 			google_chromeec_offmode_heartbeat();
+			configure_dam_on_system_state_change(false);
 			google_chromeec_ap_poweroff();
 		}
 		mdelay(200);
@@ -188,6 +203,7 @@ void launch_charger_applet(void)
 			if (detect_ac_unplug_event())
 				indicate_charging_status();
 			google_chromeec_offmode_heartbeat();
+			configure_dam_on_system_state_change(false);
 			google_chromeec_ap_poweroff();
 		}
 
@@ -210,6 +226,7 @@ void launch_charger_applet(void)
 		if (has_crossed_threshold) {
 			printk(BIOS_INFO, "Issuing power-off due to temperature trip.\n");
 			google_chromeec_offmode_heartbeat();
+			configure_dam_on_system_state_change(false);
 			google_chromeec_ap_poweroff();
 		}
 	} while (true);
@@ -237,6 +254,8 @@ void configure_parallel_charging(void)
  */
 void configure_debug_access_port(void)
 {
+	configure_dam_on_system_state_change(true);
+
 	if (!CONFIG(HAVE_DEBUG_ACCESS_PORT_SOURCE_SINK))
 		return;
 
diff --git a/src/mainboard/google/bluey/mainboard.c b/src/mainboard/google/bluey/mainboard.c
index 20710b1742..7f78fb0f0b 100644
--- a/src/mainboard/google/bluey/mainboard.c
+++ b/src/mainboard/google/bluey/mainboard.c
@@ -178,6 +178,7 @@ static void trigger_critical_battery_shutdown(void)
 
 	platform_handle_emergency_low_battery();
 
+	configure_dam_on_system_state_change(false);
 	google_chromeec_ap_poweroff();
 }
 

From bdf757aa86f004889073390ed42138c65a8b5b10 Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Tue, 24 Mar 2026 14:37:56 -0500
Subject: [PATCH 3881/3886] soc/intel/common/power_limit: Add option-driven
 PL1/PL2 overrides and locking
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Add option-backed overrides for PL1 and PL2, to allow for runtime
configuration, with fallback to board programmed values. Clamp PL2
to at least PL1.

Add an option to control setting the lock bit, to prevent OS or user
tools from overriding the desired power limits.

Add a CFR object for setting the lock bit, but not for the PL1/2
overrides, as the desired values there are board specific.

TEST=tested with rest of patch train

Change-Id: I7194df93e0602b4e00d1d39e44cb0b0ed2582cb9
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91846
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Aralguppe, Sowmya <sowmya.aralguppe@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
---
 .../common/block/include/intelblocks/cfr.h      |  8 ++++++++
 .../common/block/include/intelblocks/msr.h      |  1 +
 .../common/block/power_limit/power_limit.c      | 17 +++++++++++++----
 3 files changed, 22 insertions(+), 4 deletions(-)

diff --git a/src/soc/intel/common/block/include/intelblocks/cfr.h b/src/soc/intel/common/block/include/intelblocks/cfr.h
index 0185b0c028..0905d2d65d 100644
--- a/src/soc/intel/common/block/include/intelblocks/cfr.h
+++ b/src/soc/intel/common/block/include/intelblocks/cfr.h
@@ -184,4 +184,12 @@ static const struct sm_object bios_lock = SM_DECLARE_BOOL({
 	.default_value	= CONFIG(BOOTMEDIA_SMM_BWP),
 }, WITH_CALLBACK(update_smm_bwp));
 
+static const struct sm_object pkg_power_limit_lock = SM_DECLARE_BOOL({
+	.opt_name	= "pkg_power_limit_lock",
+	.ui_name	= "Package power limit lock",
+	.ui_helptext	= "Lock the package power limits after programming.\n"
+			  "This prevents the power limits from being changed by the OS or runtime tools.",
+	.default_value	= false,
+});
+
 #endif /* SOC_INTEL_CMN_CFR_H */
diff --git a/src/soc/intel/common/block/include/intelblocks/msr.h b/src/soc/intel/common/block/include/intelblocks/msr.h
index 1965b36d59..26f433fb15 100644
--- a/src/soc/intel/common/block/include/intelblocks/msr.h
+++ b/src/soc/intel/common/block/include/intelblocks/msr.h
@@ -101,6 +101,7 @@
 #define PKG_POWER_LIMIT_TIME_MASK	(0x7f)
 #define PKG_POWER_LIMIT_DUTYCYCLE_SHIFT 24
 #define PKG_POWER_LIMIT_DUTYCYCLE_MASK  (0x7f)
+#define PKG_POWER_LIMIT_LOCK		(1 << 31)
 
 #define MSR_CORE_MKTME_ACTIVATION	0x9ff
 /* SMM save state MSRs */
diff --git a/src/soc/intel/common/block/power_limit/power_limit.c b/src/soc/intel/common/block/power_limit/power_limit.c
index 4758f09f82..167c8d7f73 100644
--- a/src/soc/intel/common/block/power_limit/power_limit.c
+++ b/src/soc/intel/common/block/power_limit/power_limit.c
@@ -6,6 +6,7 @@
 #include <drivers/intel/dptf/chip.h>
 #include <intelblocks/cpulib.h>
 #include <intelblocks/power_limit.h>
+#include <option.h>
 #include <soc/msr.h>
 #include <soc/pci_devs.h>
 #include <soc/soc_chip.h>
@@ -141,8 +142,8 @@ void set_power_limits(u8 power_limit_1_time,
 
 	/* Set long term power limit to TDP */
 	limit.lo = 0;
-	tdp_pl1 = ((conf->tdp_pl1_override == 0) ?
-			tdp : (conf->tdp_pl1_override * power_unit));
+	const unsigned int tdp_pl1_override = get_uint_option("tdp_pl1_override", conf->tdp_pl1_override);
+	tdp_pl1 = tdp_pl1_override ? (tdp_pl1_override * power_unit) : tdp;
 	printk(BIOS_INFO, "CPU PL1 = %u Watts\n", tdp_pl1 / power_unit);
 	limit.lo |= (tdp_pl1 & PKG_POWER_LIMIT_MASK);
 
@@ -155,13 +156,21 @@ void set_power_limits(u8 power_limit_1_time,
 
 	/* Set short term power limit to 1.25 * TDP if no config given */
 	limit.hi = 0;
-	tdp_pl2 = (conf->tdp_pl2_override == 0) ?
-		(tdp * 125) / 100 : (conf->tdp_pl2_override * power_unit);
+	const unsigned int tdp_pl2_override = get_uint_option("tdp_pl2_override", conf->tdp_pl2_override);
+	tdp_pl2 = tdp_pl2_override ? (tdp_pl2_override * power_unit) : ((tdp * 125) / 100);
+	/* Ensure PL2 isn't less than PL1 */
+	if (tdp_pl2 < tdp_pl1)
+		tdp_pl2 = tdp_pl1;
 	printk(BIOS_INFO, "CPU PL2 = %u Watts\n", tdp_pl2 / power_unit);
 	limit.hi |= (tdp_pl2) & PKG_POWER_LIMIT_MASK;
 	limit.hi |= PKG_POWER_LIMIT_CLAMP;
 	limit.hi |= PKG_POWER_LIMIT_EN;
 
+	if (get_uint_option("pkg_power_limit_lock", 0)) {
+		limit.hi |= PKG_POWER_LIMIT_LOCK;
+		printk(BIOS_INFO, "Locking package power limits\n");
+	}
+
 	/* Power limit 2 time is only programmable on server SKU */
 	wrmsr(MSR_PKG_POWER_LIMIT, limit);
 

From 976149a2f7aba4854b2d413aa36d6fc915bd3943 Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Wed, 25 Mar 2026 14:02:29 -0500
Subject: [PATCH 3882/3886] soc/intel/common/power_limit: Raise PsysPL1 when
 package PL1 is above TDP

When PL1 exceeds the SKU TDP, program MSR_PLATFORM_POWER_LIMIT (0x65c)
long-term (PsysPL1) to the same value.

This prevents the long-term system power from becoming a choke point
when raising the package PL1.

Change-Id: I85a604467ccbede84a668117ad588ac75b742a70
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91872
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
---
 .../intel/common/block/power_limit/power_limit.c   | 14 ++++++++++++++
 1 file changed, 14 insertions(+)

diff --git a/src/soc/intel/common/block/power_limit/power_limit.c b/src/soc/intel/common/block/power_limit/power_limit.c
index 167c8d7f73..aec631f6e4 100644
--- a/src/soc/intel/common/block/power_limit/power_limit.c
+++ b/src/soc/intel/common/block/power_limit/power_limit.c
@@ -178,6 +178,20 @@ void set_power_limits(u8 power_limit_1_time,
 	MCHBAR32(MCH_PKG_POWER_LIMIT_LO) = limit.lo & (~(PKG_POWER_LIMIT_EN));
 	MCHBAR32(MCH_PKG_POWER_LIMIT_HI) = limit.hi;
 
+	/*
+	 * Set PsysPL1 if PL1 is > TDP
+	 * POR value for most SKUs is same as TDP, so adjust it accordingly.
+	 */
+	if (tdp_pl1 > tdp) {
+		limit = rdmsr(MSR_PLATFORM_POWER_LIMIT);
+		limit.lo = 0;
+		printk(BIOS_INFO, "CPU PsysPL1 = %u Watts\n", tdp_pl1 / power_unit);
+		limit.lo |= tdp_pl1 & PKG_POWER_LIMIT_MASK;
+		limit.lo |= PKG_POWER_LIMIT_CLAMP;
+		limit.lo |= PKG_POWER_LIMIT_EN;
+		wrmsr(MSR_PLATFORM_POWER_LIMIT, limit);
+	}
+
 	/* Set PsysPl2 */
 	if (conf->tdp_psyspl2) {
 		limit = rdmsr(MSR_PLATFORM_POWER_LIMIT);

From 6c10b071460f72a8518459f5f08b3958bd6598cf Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Wed, 25 Mar 2026 23:05:58 -0500
Subject: [PATCH 3883/3886] mb/google/fizz: Refactor
 mainboard_set_power_limits()

Add helper functions to determine sku type and default PL2 value; the
latter will be exposed and used externally in a subsequent commit.

Rename and remove variables to clarify and simplify the function.
Defines for FIZZ_PSYSPL2_U22/U42 are renamed to clarify that they are
the max adapter power for those SKUs; PsysPL2 is set to 90% of these
values via the SET_PSYSPL2() macro.

Change-Id: I504b2dcedbf3817351516b051effc2c70082854d
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91882
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/google/fizz/mainboard.c | 50 ++++++++++++++-------------
 1 file changed, 26 insertions(+), 24 deletions(-)

diff --git a/src/mainboard/google/fizz/mainboard.c b/src/mainboard/google/fizz/mainboard.c
index e908b9e635..d0e2ed86ce 100644
--- a/src/mainboard/google/fizz/mainboard.c
+++ b/src/mainboard/google/fizz/mainboard.c
@@ -29,8 +29,8 @@
 #define FIZZ_SKU_ID_CEL_U22 0x0
 #define FIZZ_PL2_U42        44
 #define FIZZ_PL2_U22        29
-#define FIZZ_PSYSPL2_U22    65
-#define FIZZ_PSYSPL2_U42    90
+#define FIZZ_ADP_WATTS_U22  65
+#define FIZZ_ADP_WATTS_U42  90
 #define FIZZ_MAX_TIME_WINDOW 6
 #define FIZZ_MIN_DUTYCYCLE   4
 /*
@@ -69,6 +69,19 @@ static uint8_t board_sku_id(void)
 	return sku_id;
 }
 
+static bool is_u42_sku(void)
+{
+	uint8_t sku = board_sku_id();
+	return sku == FIZZ_SKU_ID_I7_U42 ||
+	       sku == FIZZ_SKU_ID_I5_U42 ||
+	       sku == FIZZ_SKU_ID_I3_U42;
+}
+
+static unsigned int fizz_default_pl2_watts(void)
+{
+	return is_u42_sku() ? FIZZ_PL2_U42 : FIZZ_PL2_U22;
+}
+
 /*
  * mainboard_set_power_limits
  *
@@ -102,44 +115,33 @@ static uint8_t board_sku_id(void)
 static void mainboard_set_power_limits(struct soc_power_limits_config *conf)
 {
 	enum usb_chg_type type;
-	u32 watts;
 	u16 volts_mv, current_ma;
-	u32 pl2, psyspl2;
+	u32 adapter_watts;
 	int rv = google_chromeec_get_usb_pd_power_info(&type, &current_ma, &volts_mv);
-	uint8_t sku = board_sku_id();
-	const uint32_t u42_mask = (1 << FIZZ_SKU_ID_I7_U42) |
-				  (1 << FIZZ_SKU_ID_I5_U42) |
-				  (1 << FIZZ_SKU_ID_I3_U42);
 
-	/* PL2 value is sku-based, no matter what charger we are using */
-	pl2 = FIZZ_PL2_U22;
-	if ((1 << sku) & u42_mask)
-		pl2 = FIZZ_PL2_U42;
 	conf->tdp_psyspl3 = conf->tdp_pl4 = 0;
 
 	/* If we can't get charger info or not PD charger, assume barrel jack */
 	if (rv != 0 || type != USB_CHG_TYPE_PD) {
-		/* using the barrel jack, get PsysPL2 based on sku id */
-		psyspl2 = FIZZ_PSYSPL2_U22;
-		/* Running a U42 SKU */
-		if ((1 << sku) & u42_mask)
-			psyspl2 = FIZZ_PSYSPL2_U42;
+		/* using the barrel jack, get max adapter power based on sku id */
+		adapter_watts = is_u42_sku() ? FIZZ_ADP_WATTS_U42 : FIZZ_ADP_WATTS_U22;
 	} else {
 		/* Detected TypeC.  Base on max value of adapter */
-		watts = ((u32)volts_mv * current_ma) / 1000000;
-		psyspl2 = watts;
-		conf->tdp_psyspl3 = SET_PSYSPL2(psyspl2);
+		adapter_watts = ((u32)volts_mv * current_ma) / 1000000;
+		conf->tdp_psyspl3 = SET_PSYSPL2(adapter_watts);
 		/* set max possible time window */
 		conf->tdp_psyspl3_time = FIZZ_MAX_TIME_WINDOW;
 		/* set minimum duty cycle */
 		conf->tdp_psyspl3_dutycycle = FIZZ_MIN_DUTYCYCLE;
-		if ((1 << sku) & u42_mask)
-			conf->tdp_pl4 = SET_PSYSPL2(psyspl2);
+		if (is_u42_sku())
+			conf->tdp_pl4 = SET_PSYSPL2(adapter_watts);
 	}
 
-	conf->tdp_pl2_override = pl2;
+	/* PL2 value is sku-based, no matter what charger we are using */
+	conf->tdp_pl2_override = fizz_default_pl2_watts();
+
 	/* set psyspl2 to 90% of max adapter power */
-	conf->tdp_psyspl2 = SET_PSYSPL2(psyspl2);
+	conf->tdp_psyspl2 = SET_PSYSPL2(adapter_watts);
 }
 
 static uint8_t read_oem_id_from_gpio(void)

From 0d95bb51580472350fb8d9949a66bb52f279e6f4 Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Mon, 23 Mar 2026 17:24:37 -0500
Subject: [PATCH 3884/3886] mb/google/fizz: Add CFR PL1/PL2 package power
 overrides

Expose PL1 and PL2 overrides in the Power CFR form, allowing users to
adjust the values within safe limits. Expose CFR option to lock the
programmed values.

TEST=build/boot Fizz, verify adjusted values reflected in cbmem log,
MSR 0x610, and MCHBAR registers.

Change-Id: Iab7b2cdf815cadfbc93e1d8395380706243ec203
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91847
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
---
 src/mainboard/google/fizz/board.h     |  8 +++++++
 src/mainboard/google/fizz/cfr.c       | 34 +++++++++++++++++++++++++++
 src/mainboard/google/fizz/mainboard.c |  5 +++-
 3 files changed, 46 insertions(+), 1 deletion(-)
 create mode 100644 src/mainboard/google/fizz/board.h

diff --git a/src/mainboard/google/fizz/board.h b/src/mainboard/google/fizz/board.h
new file mode 100644
index 0000000000..fe7d320364
--- /dev/null
+++ b/src/mainboard/google/fizz/board.h
@@ -0,0 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef MAINBOARD_GOOGLE_FIZZ_BOARD_H
+#define MAINBOARD_GOOGLE_FIZZ_BOARD_H
+
+unsigned int fizz_default_pl2_watts(void);
+
+#endif
diff --git a/src/mainboard/google/fizz/cfr.c b/src/mainboard/google/fizz/cfr.c
index 10df17757c..99cb3fb36f 100644
--- a/src/mainboard/google/fizz/cfr.c
+++ b/src/mainboard/google/fizz/cfr.c
@@ -5,6 +5,37 @@
 #include <ec/google/chromeec/cfr.h>
 #include <intelblocks/cfr.h>
 #include <soc/cfr.h>
+#include "board.h"
+
+static const struct sm_object tdp_pl1_override = SM_DECLARE_NUMBER({
+	.opt_name	= "tdp_pl1_override",
+	.ui_name	= "CPU PL1 power limit (W)",
+	.ui_helptext	= "Long-duration CPU package power limit.\n"
+			  "Default: 15 W. Range: 15-35 W.",
+	.default_value	= 15,
+	.min		= 15,
+	.max		= 35,
+	.step		= 1,
+	.display_flags	= 0,
+});
+
+static void update_tdp_pl2_default(struct sm_object *new)
+{
+	new->sm_number.default_value = fizz_default_pl2_watts();
+}
+
+static const struct sm_object tdp_pl2_override = SM_DECLARE_NUMBER({
+	.opt_name	= "tdp_pl2_override",
+	.ui_name	= "CPU PL2 power limit (W)",
+	.ui_helptext	= "Short-duration CPU package power limit.\n"
+			  "Default: 29 W (U22 SKUs) or 44 W (U42 SKUs). Range: 29-51 W.\n"
+			  "Must be >= PL1 (enforced at boot).",
+	.default_value	= 29,
+	.min		= 29,
+	.max		= 51,
+	.step		= 1,
+	.display_flags	= 0,
+}, WITH_CALLBACK(update_tdp_pl2_default));
 
 static struct sm_obj_form system = {
 	.ui_name = "System",
@@ -37,6 +68,9 @@ static struct sm_obj_form power = {
 	.ui_name = "Power",
 	.obj_list = (const struct sm_object *[]) {
 		&power_on_after_fail,
+		&tdp_pl1_override,
+		&tdp_pl2_override,
+		&pkg_power_limit_lock,
 		NULL
 	},
 };
diff --git a/src/mainboard/google/fizz/mainboard.c b/src/mainboard/google/fizz/mainboard.c
index d0e2ed86ce..06b877ecc6 100644
--- a/src/mainboard/google/fizz/mainboard.c
+++ b/src/mainboard/google/fizz/mainboard.c
@@ -11,6 +11,7 @@
 #include <ec/google/chromeec/ec.h>
 #include <gpio.h>
 #include <intelblocks/power_limit.h>
+#include <option.h>
 #include <smbios.h>
 #include <soc/pci_devs.h>
 #include <soc/nhlt.h>
@@ -20,6 +21,8 @@
 
 #include <variant/gpio.h>
 
+#include "board.h"
+
 #define FIZZ_SKU_ID_I7_U42  0x4
 #define FIZZ_SKU_ID_I5_U42  0x5
 #define FIZZ_SKU_ID_I3_U42  0x6
@@ -77,7 +80,7 @@ static bool is_u42_sku(void)
 	       sku == FIZZ_SKU_ID_I3_U42;
 }
 
-static unsigned int fizz_default_pl2_watts(void)
+unsigned int fizz_default_pl2_watts(void)
 {
 	return is_u42_sku() ? FIZZ_PL2_U42 : FIZZ_PL2_U22;
 }

From 1dc346e61e32457cc3bc2aafd1f34193228e65d6 Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Wed, 25 Mar 2026 15:22:23 -0500
Subject: [PATCH 3885/3886] cpu/intel/haswell: Add option-backed PL1/PL2
 overrides and package limit lock

Add option variables to allow user override of PL1/PL2 via CMOS/CFR,
which can be exposed by mainboards. Add the ability to lock the power
levels set to prevent the OS/userspace tools from meddling. Add a
CFR form for the lock option which mainboards can use.

TEST=build/boot google/beltino with PL1/2 and lock options exposed,
verify changes reflected in cbmem and by reading MSR/MCHBAR.

Change-Id: I3db0a44c1e8982348026fa9e66123fd41a0f9884
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91876
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/cpu/intel/haswell/cfr.h          | 16 ++++++++++++++++
 src/cpu/intel/haswell/haswell.h      |  1 +
 src/cpu/intel/haswell/haswell_init.c | 24 ++++++++++++++++++++----
 3 files changed, 37 insertions(+), 4 deletions(-)
 create mode 100644 src/cpu/intel/haswell/cfr.h

diff --git a/src/cpu/intel/haswell/cfr.h b/src/cpu/intel/haswell/cfr.h
new file mode 100644
index 0000000000..2c92c1540a
--- /dev/null
+++ b/src/cpu/intel/haswell/cfr.h
@@ -0,0 +1,16 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef _CPU_INTEL_HASWELL_CFR_H_
+#define _CPU_INTEL_HASWELL_CFR_H_
+
+#include <drivers/option/cfr_frontend.h>
+
+static const struct sm_object cpu_power_limit_lock = SM_DECLARE_BOOL({
+	.opt_name	= "cpu_power_limit_lock",
+	.ui_name	= "CPU power limit lock",
+	.ui_helptext	= "Lock CPU package power limits after programming.\n"
+			  "This prevents the power limits from being changed by the OS or runtime tools.\n",
+	.default_value	= false,
+});
+
+#endif /* _CPU_INTEL_HASWELL_CFR_H_ */
diff --git a/src/cpu/intel/haswell/haswell.h b/src/cpu/intel/haswell/haswell.h
index b8cc98a570..946a3c71df 100644
--- a/src/cpu/intel/haswell/haswell.h
+++ b/src/cpu/intel/haswell/haswell.h
@@ -84,6 +84,7 @@
 #define  PKG_POWER_LIMIT_CLAMP		(1 << 16)
 #define  PKG_POWER_LIMIT_TIME_SHIFT	17
 #define  PKG_POWER_LIMIT_TIME_MASK	0x7f
+#define  PKG_POWER_LIMIT_LOCK		(1U << 31)
 
 #define MSR_VR_CURRENT_CONFIG		0x601
 #define MSR_VR_MISC_CONFIG		0x603
diff --git a/src/cpu/intel/haswell/haswell_init.c b/src/cpu/intel/haswell/haswell_init.c
index 7d58795db0..11f8f1df9d 100644
--- a/src/cpu/intel/haswell/haswell_init.c
+++ b/src/cpu/intel/haswell/haswell_init.c
@@ -2,6 +2,7 @@
 
 #include <console/console.h>
 #include <device/device.h>
+
 #include <cpu/cpu.h>
 #include <cpu/x86/mtrr.h>
 #include <cpu/x86/msr.h>
@@ -12,6 +13,7 @@
 #include <cpu/intel/turbo.h>
 #include <cpu/x86/name.h>
 #include <delay.h>
+#include <option.h>
 #include <northbridge/intel/haswell/haswell.h>
 #include <southbridge/intel/lynxpoint/pch.h>
 #include <cpu/intel/common/common.h>
@@ -260,6 +262,7 @@ void set_power_limits(u8 power_limit_1_time)
 	msr_t limit;
 	unsigned int power_unit;
 	unsigned int tdp, min_power, max_power, max_time;
+	unsigned int pl1, pl2;
 	u8 power_limit_1_val;
 
 	if (power_limit_1_time >= ARRAY_SIZE(power_limit_time_sec_to_msr))
@@ -292,17 +295,30 @@ void set_power_limits(u8 power_limit_1_time)
 
 	power_limit_1_val = power_limit_time_sec_to_msr[power_limit_1_time];
 
-	/* Set long term power limit to TDP */
+	const unsigned int pl1_override_w = get_uint_option("tdp_pl1_override", 0);
+	const unsigned int pl2_override_w = get_uint_option("tdp_pl2_override", 0);
+
+	/* Set long term power limit to TDP if not overridden */
 	limit.lo = 0;
-	limit.lo |= tdp & PKG_POWER_LIMIT_MASK;
+	pl1 = pl1_override_w ? (pl1_override_w * power_unit) : tdp;
+	printk(BIOS_DEBUG, "CPU PL1 = %u Watts\n", pl1 / power_unit);
+	limit.lo |= pl1 & PKG_POWER_LIMIT_MASK;
 	limit.lo |= PKG_POWER_LIMIT_EN;
 	limit.lo |= (power_limit_1_val & PKG_POWER_LIMIT_TIME_MASK) <<
 		PKG_POWER_LIMIT_TIME_SHIFT;
 
-	/* Set short term power limit to 1.25 * TDP */
+	/* Set short term power limit to 1.25 * TDP if not overridden */
 	limit.hi = 0;
-	limit.hi |= ((tdp * 125) / 100) & PKG_POWER_LIMIT_MASK;
+	pl2 = pl2_override_w ? (pl2_override_w * power_unit) : ((tdp * 125) / 100);
+	if (pl2 < pl1)
+		pl2 = pl1;
+	printk(BIOS_DEBUG, "CPU PL2 = %u Watts\n", pl2 / power_unit);
+	limit.hi |= pl2 & PKG_POWER_LIMIT_MASK;
 	limit.hi |= PKG_POWER_LIMIT_EN;
+	if (get_uint_option("cpu_power_limit_lock", 0)) {
+		limit.hi |= PKG_POWER_LIMIT_LOCK;
+		printk(BIOS_DEBUG, "Locking package power limits\n");
+	}
 	/* Power limit 2 time is only programmable on server SKU */
 
 	wrmsr(MSR_PKG_POWER_LIMIT, limit);

From eda62af9dd8e2f3d491c3484a0a41c886a0e5c31 Mon Sep 17 00:00:00 2001
From: Subrata Banik <subratabanik@google.com>
Date: Mon, 30 Mar 2026 13:54:09 +0530
Subject: [PATCH 3886/3886] mb/google/bluey: Implement slow-to-fast charging
 transition logic

Update the charging flow to support a transition from slow charging
to fast charging based on the battery threshold.

Key changes:
- Pass boot_mode to launch_charger_applet() to allow mode-specific
  power management.
- In LB_BOOT_MODE_LOW_BATTERY_CHARGING, if the battery is above the
  critical threshold, issue an AP power-off to trigger a transition
  from slow to fast charging mode.
- Update handle_low_power_charging_boot() to default to slow charging
  for low-battery charging boots.

BUG=b:497622018
TEST=Verified Bluey correctly switches from slow charging to fast
charging once critical battery threshold is exceeded.

Change-Id: Ic65ab99360496c92a91795fce1352159066ab94e
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91912
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
---
 src/mainboard/google/bluey/board.h     |  2 ++
 src/mainboard/google/bluey/charging.c  | 40 ++++++++++++++++++++++++++
 src/mainboard/google/bluey/mainboard.c | 17 ++++++++++-
 src/mainboard/google/bluey/romstage.c  | 18 +++++-------
 4 files changed, 65 insertions(+), 12 deletions(-)

diff --git a/src/mainboard/google/bluey/board.h b/src/mainboard/google/bluey/board.h
index a4e0d31ce7..47515c605f 100644
--- a/src/mainboard/google/bluey/board.h
+++ b/src/mainboard/google/bluey/board.h
@@ -4,6 +4,7 @@
 #define MAINBOARD_GOOGLE_BLUEY_BOARD_H
 
 #include <assert.h>
+#include <commonlib/coreboot_tables.h>
 #include <gpio.h>
 
 #define GPIO_AP_EC_INT		GPIO(67)
@@ -66,6 +67,7 @@ void configure_dam_on_system_state_change(bool poweron);
 void enable_slow_battery_charging(void);
 void disable_slow_battery_charging(void);
 void launch_charger_applet(void);
+bool platform_get_battery_soc_information(uint32_t *batt_pct);
 void enable_fast_battery_charging(void);
 
 #endif /* MAINBOARD_GOOGLE_BLUEY_BOARD_H */
diff --git a/src/mainboard/google/bluey/charging.c b/src/mainboard/google/bluey/charging.c
index 596891e514..c5cf30ce8c 100644
--- a/src/mainboard/google/bluey/charging.c
+++ b/src/mainboard/google/bluey/charging.c
@@ -61,6 +61,7 @@
 
 #define DELAY_CHARGING_APPLET_MS 2000 /* 2sec */
 #define CHARGING_RAIL_STABILIZATION_DELAY_MS 3000 /* 3sec */
+#define LOW_BATTERY_CHARGING_LOOP_EXIT_MS (10 * 60 * 1000) /* 10min */
 #define DELAY_CHARGING_ACTIVE_LB_MS 4000 /* 4sec */
 
 enum charging_status {
@@ -162,6 +163,7 @@ void launch_charger_applet(void)
 	static const long charging_enable_timeout_ms = CHARGING_RAIL_STABILIZATION_DELAY_MS;
 	struct stopwatch sw;
 	bool has_crossed_threshold = false;
+	bool has_entered_low_battery_mode = false;
 
 	printk(BIOS_INFO, "Inside %s. Initiating charging\n", __func__);
 
@@ -191,10 +193,37 @@ void launch_charger_applet(void)
 	}
 	printk(BIOS_INFO, "Charging ready after %lld ms\n", stopwatch_duration_msecs(&sw));
 
+	static const long low_battery_charging_timeout_ms = LOW_BATTERY_CHARGING_LOOP_EXIT_MS;
+	uint32_t batt_pct;
+	if (!platform_get_battery_soc_information(&batt_pct)) {
+		printk(BIOS_WARNING, "Failed to get battery level\n");
+		return;
+	}
+	/*
+	 * If the battery is at 0%, enter low-battery charging mode and
+	 * start a timeout timer to prevent getting stuck in a dead-loop
+	 * if the battery fails to charge.
+	 *
+	 * FIXME: b/497622018
+	 */
+	if (!batt_pct) {
+		has_entered_low_battery_mode = true;
+		stopwatch_init_msecs_expire(&sw, low_battery_charging_timeout_ms);
+	}
+
 	do {
 		/* Add static delay before reading the charging applet pre-requisites */
 		mdelay(DELAY_CHARGING_APPLET_MS);
 
+		if (has_entered_low_battery_mode) {
+			if (stopwatch_expired(&sw)) {
+				printk(BIOS_INFO, "Issuing power-off as switching from slow charging "
+						"to fast charging mode.\n");
+				configure_dam_on_system_state_change(false);
+				google_chromeec_ap_poweroff();
+			}
+		}
+
 		/*
 		 * Issue a shutdown if not charging.
 		 */
@@ -328,3 +357,14 @@ void enable_fast_battery_charging(void)
 		printk(BIOS_ERR, "LPASS bring-up failed; skipping fast charging.\n");
 	}
 }
+
+bool platform_get_battery_soc_information(uint32_t *batt_pct)
+{
+	if (!CONFIG(EC_GOOGLE_CHROMEEC))
+		return false;
+
+	if (google_chromeec_read_batt_state_of_charge(batt_pct))
+		return false;
+
+	return true;
+}
diff --git a/src/mainboard/google/bluey/mainboard.c b/src/mainboard/google/bluey/mainboard.c
index 7f78fb0f0b..2090c3a782 100644
--- a/src/mainboard/google/bluey/mainboard.c
+++ b/src/mainboard/google/bluey/mainboard.c
@@ -192,7 +192,22 @@ static void handle_low_power_charging_boot(void)
 	if (!pll_init_and_set(apss_ncc0, L_VAL_710P4MHz))
 		printk(BIOS_DEBUG, "CPU Frequency set to 710MHz\n");
 
-	enable_fast_battery_charging();
+	uint32_t batt_pct;
+	if (!platform_get_battery_soc_information(&batt_pct)) {
+		printk(BIOS_WARNING, "Failed to get battery level\n");
+		return;
+	}
+
+	/*
+	 * Use slow charging for a completely depleted battery (0% SoC)
+	 * to ensure stability; otherwise, enable fast charging.
+	 *
+	 * FIXME: b/497622018
+	 */
+	if (!batt_pct)
+		enable_slow_battery_charging();
+	else
+		enable_fast_battery_charging();
 
 	/*
 	 * Disable the lightbar for Low-Battery or Off-Mode charging sequences.
diff --git a/src/mainboard/google/bluey/romstage.c b/src/mainboard/google/bluey/romstage.c
index 3b63839d87..26e9a0fd72 100644
--- a/src/mainboard/google/bluey/romstage.c
+++ b/src/mainboard/google/bluey/romstage.c
@@ -105,15 +105,6 @@ int qclib_mainboard_override(struct qclib_cb_if_table *table)
 	return 0;
 }
 
-static void platform_dump_battery_soc_information(void)
-{
-	uint32_t batt_pct;
-	if (google_chromeec_read_batt_state_of_charge(&batt_pct))
-		printk(BIOS_WARNING, "Failed to get battery level\n");
-	else
-		printk(BIOS_INFO, "Battery state-of-charge %d%%\n", batt_pct);
-}
-
 static void early_setup_usb_typec(void)
 {
 	gpio_output(GPIO_USB_C1_RETIMER_RESET_L, 0);
@@ -158,8 +149,13 @@ void platform_romstage_main(void)
 	/* Watchdog must be checked first to avoid erasing watchdog info later. */
 	check_wdog();
 
-	if (CONFIG(EC_GOOGLE_CHROMEEC) && CONFIG(CONSOLE_SERIAL))
-		platform_dump_battery_soc_information();
+	if (CONFIG(EC_GOOGLE_CHROMEEC) && CONFIG(CONSOLE_SERIAL)) {
+		uint32_t batt_pct;
+		if (platform_get_battery_soc_information(&batt_pct))
+			printk(BIOS_INFO, "Battery state-of-charge %d%%\n", batt_pct);
+		else
+			printk(BIOS_WARNING, "Failed to get battery level\n");
+	}
 
 	if (!qclib_check_dload_mode())
 		shrm_fw_load_reset();